Version in base suite: 525.147.05-1~deb12u1 Base version: nvidia-open-gpu-kernel-modules_525.147.05-1~deb12u1 Target version: nvidia-open-gpu-kernel-modules_535.161.08-1~deb12u1 Base file: /srv/ftp-master.debian.org/ftp/pool/contrib/n/nvidia-open-gpu-kernel-modules/nvidia-open-gpu-kernel-modules_525.147.05-1~deb12u1.dsc Target file: /srv/ftp-master.debian.org/policy/pool/contrib/n/nvidia-open-gpu-kernel-modules/nvidia-open-gpu-kernel-modules_535.161.08-1~deb12u1.dsc /srv/release.debian.org/tmp/PYKxhEfHRB/nvidia-open-gpu-kernel-modules-535.161.08/nouveau/nouveau_firmware_layout.ods |binary /srv/release.debian.org/tmp/PYKxhEfHRB/nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia-modeset/src/shaders/g_ampere_shaders |binary /srv/release.debian.org/tmp/PYKxhEfHRB/nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia-modeset/src/shaders/g_hopper_shaders |binary /srv/release.debian.org/tmp/PYKxhEfHRB/nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia-modeset/src/shaders/g_maxwell_shaders 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nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/arch/nvalloc/unix/include/nv-ioctl.h | 2 nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/arch/nvalloc/unix/include/nv-priv.h | 1 nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/arch/nvalloc/unix/include/nv-reg.h | 91 nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/arch/nvalloc/unix/include/nv.h | 51 nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/arch/nvalloc/unix/include/os-interface.h | 19 nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/arch/nvalloc/unix/include/osapi.h | 4 nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/arch/nvalloc/unix/include/osfuncs.h | 7 nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/arch/nvalloc/unix/include/x86emu/debug.h | 211 nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/arch/nvalloc/unix/include/x86emu/decode.h | 88 nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/arch/nvalloc/unix/include/x86emu/fpu.h | 61 nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/arch/nvalloc/unix/include/x86emu/fpu_regs.h | 119 nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/arch/nvalloc/unix/include/x86emu/ops.h | 45 nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/arch/nvalloc/unix/include/x86emu/prim_ops.h | 141 nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/arch/nvalloc/unix/include/x86emu/regs.h | 340 nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/arch/nvalloc/unix/include/x86emu/types.h | 93 nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/arch/nvalloc/unix/include/x86emu/x86emu.h | 205 nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/arch/nvalloc/unix/include/x86emu/x86emui.h | 113 nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/arch/nvalloc/unix/src/dynamic-power.c | 2742 nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/arch/nvalloc/unix/src/escape.c | 32 nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/arch/nvalloc/unix/src/exports-stubs.c | 207 nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/arch/nvalloc/unix/src/os-hypervisor.c | 31 nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/arch/nvalloc/unix/src/os.c | 363 nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/arch/nvalloc/unix/src/osapi.c | 601 nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/arch/nvalloc/unix/src/osinit.c | 189 nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/arch/nvalloc/unix/src/osmemdesc.c | 31 nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/arch/nvalloc/unix/src/osnvlink.c | 2 nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/arch/nvalloc/unix/src/osunix.c | 7 nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/arch/nvalloc/unix/src/rm-gpu-ops.c | 181 nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/arch/nvalloc/unix/src/rmobjexportimport.c | 9 nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/arch/nvalloc/unix/src/unix_console.c | 293 nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/arch/nvalloc/unix/src/unix_intr.c | 60 nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/arch/nvalloc/unix/src/vbioscall.c | 457 nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/arch/nvalloc/unix/x86emu/debug.c | 547 nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/arch/nvalloc/unix/x86emu/decode.c | 1094 nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/arch/nvalloc/unix/x86emu/fpu.c | 965 nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/arch/nvalloc/unix/x86emu/ops.c |11761 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/arch/nvalloc/unix/x86emu/ops2.c | 2877 nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/arch/nvalloc/unix/x86emu/prim_ops.c | 2655 nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/arch/nvalloc/unix/x86emu/sys.c | 663 nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/exports_link_command.txt | 15 nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_access_cntr_buffer_nvoc.c | 39 nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_access_cntr_buffer_nvoc.h | 30 nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_allclasses.h | 35 nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_binary_api_nvoc.c | 282 nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_binary_api_nvoc.h | 264 nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_bindata.c | 12 nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_bindata_kgspGetBinArchiveBooterLoadUcode_AD102.c | 6759 + nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_bindata_kgspGetBinArchiveBooterLoadUcode_GA100.c | 7206 + nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_bindata_kgspGetBinArchiveBooterLoadUcode_GA102.c | 7434 +- nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_bindata_kgspGetBinArchiveBooterLoadUcode_TU102.c | 7125 + nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_bindata_kgspGetBinArchiveBooterLoadUcode_TU116.c | 7118 + nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_bindata_kgspGetBinArchiveBooterUnloadUcode_AD102.c | 3416 nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_bindata_kgspGetBinArchiveBooterUnloadUcode_GA100.c | 3218 nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_bindata_kgspGetBinArchiveBooterUnloadUcode_GA102.c | 3397 nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_bindata_kgspGetBinArchiveBooterUnloadUcode_TU102.c | 3116 nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_bindata_kgspGetBinArchiveBooterUnloadUcode_TU116.c | 3114 nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_bindata_kgspGetBinArchiveConcatenatedFMCDesc_GH100.c | 98 nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_bindata_kgspGetBinArchiveConcatenatedFMC_GH100.c |22776 ++++++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_bindata_kgspGetBinArchiveGspRmBoot_AD102.c | 7418 +- nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_bindata_kgspGetBinArchiveGspRmBoot_GA102.c | 3213 nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_bindata_kgspGetBinArchiveGspRmBoot_GH100.c |36196 +++++----- nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_bindata_kgspGetBinArchiveGspRmCcFmcGfwProdSigned_GH100.c |10637 ++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_bindata_kgspGetBinArchiveGspRmFmcGfwDebugSigned_GH100.c |18129 ++--- nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_bindata_kgspGetBinArchiveGspRmFmcGfwProdSigned_GH100.c |18177 ++--- nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_ccsl_nvoc.c | 88 nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_ccsl_nvoc.h | 162 nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_ce_utils_nvoc.c | 166 nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_ce_utils_nvoc.h | 201 nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_channel_descendant_nvoc.c | 39 nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_channel_descendant_nvoc.h | 34 nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_chips2halspec_nvoc.c | 2 nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_chipset_nvoc.c | 15 nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_chipset_nvoc.h | 76 nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_client_nvoc.c | 30 nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_client_nvoc.h | 1 nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_client_resource_nvoc.c | 678 nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_client_resource_nvoc.h | 161 nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_compute_instance_subscription_nvoc.c | 141 nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_compute_instance_subscription_nvoc.h | 138 nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_conf_compute_api_nvoc.c | 482 nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_conf_compute_api_nvoc.h | 297 nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_conf_compute_nvoc.c | 442 nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_conf_compute_nvoc.h | 537 nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_console_mem_nvoc.c | 133 nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_console_mem_nvoc.h | 128 nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_context_dma_nvoc.c | 111 nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_context_dma_nvoc.h | 100 nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_crashcat_engine_nvoc.c | 123 nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_crashcat_engine_nvoc.h | 287 nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_crashcat_queue_nvoc.c | 179 nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_crashcat_queue_nvoc.h | 147 nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_crashcat_report_nvoc.c | 226 nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_crashcat_report_nvoc.h | 393 nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_crashcat_wayfinder_nvoc.c | 186 nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_crashcat_wayfinder_nvoc.h | 170 nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_dbgbuffer_nvoc.c | 129 nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_dbgbuffer_nvoc.h | 116 nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_dce_client_nvoc.h | 38 nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_deferred_api_nvoc.c | 53 nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_deferred_api_nvoc.h | 18 nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_device_nvoc.c | 341 nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_device_nvoc.h | 146 nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_disp_capabilities_nvoc.c | 135 nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_disp_capabilities_nvoc.h | 128 nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_disp_channel_nvoc.c | 117 nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_disp_channel_nvoc.h | 84 nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_disp_inst_mem_nvoc.c | 71 nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_disp_objs_nvoc.c | 1177 nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_disp_objs_nvoc.h | 726 nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_disp_sf_user_nvoc.c | 135 nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_disp_sf_user_nvoc.h | 128 nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_dispsw_nvoc.c | 34 nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_dispsw_nvoc.h | 20 nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_egm_mem_nvoc.c | 364 nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_egm_mem_nvoc.h | 257 nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_eng_desc_nvoc.h | 58 nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_eng_state_nvoc.c | 27 nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_eng_state_nvoc.h | 49 nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_event_buffer_nvoc.c | 45 nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_event_buffer_nvoc.h | 36 nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_event_nvoc.c | 60 nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_event_nvoc.h | 38 nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_fabric_nvoc.c | 15 nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_fabric_nvoc.h | 2 nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_fabric_vaspace_nvoc.c | 19 nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_fabric_vaspace_nvoc.h | 43 nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_fbsr_nvoc.c | 56 nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_fbsr_nvoc.h | 13 nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_fecs_event_list_nvoc.h | 3 nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_fla_mem_nvoc.c | 133 nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_fla_mem_nvoc.h | 128 nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_fm_session_api_nvoc.c | 129 nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_fm_session_api_nvoc.h | 120 nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_generic_engine_nvoc.c | 156 nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_generic_engine_nvoc.h | 135 nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_gpu_access_nvoc.c | 491 nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_gpu_access_nvoc.h | 633 nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_gpu_acct_nvoc.c | 15 nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_gpu_boost_mgr_nvoc.c | 15 nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_gpu_boost_mgr_nvoc.h | 10 nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_gpu_class_list.c | 30 nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_gpu_db_nvoc.c | 15 nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_gpu_group_nvoc.c | 15 nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_gpu_group_nvoc.h | 26 nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_gpu_instance_subscription_nvoc.c | 141 nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_gpu_instance_subscription_nvoc.h | 173 nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_gpu_mgmt_api_nvoc.c | 45 nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_gpu_mgmt_api_nvoc.h | 36 nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_gpu_mgr_nvoc.c | 15 nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_gpu_mgr_nvoc.h | 60 nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_gpu_nvoc.c | 322 nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_gpu_nvoc.h | 878 nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_gpu_resource_nvoc.c | 45 nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_gpu_resource_nvoc.h | 37 nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_gpu_user_shared_data_nvoc.c | 220 nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_gpu_user_shared_data_nvoc.h | 186 nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_gpu_vaspace_nvoc.c | 19 nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_gpu_vaspace_nvoc.h | 15 nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_gsync_api_nvoc.c | 123 nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_gsync_api_nvoc.h | 112 nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_gsync_nvoc.c | 15 nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_gsync_nvoc.h | 4 nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_hal.h | 1 nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_hal_mgr_nvoc.c | 15 nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_hal_nvoc.c | 15 nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_hal_nvoc.h | 6 nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_hal_stubs.h | 20 nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_hda_codec_api_nvoc.c | 147 nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_hda_codec_api_nvoc.h | 140 nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_heap_nvoc.c | 15 nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_host_eng_nvoc.c | 4 nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_host_eng_nvoc.h | 16 nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_hw_resources_nvoc.c | 133 nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_hw_resources_nvoc.h | 128 nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_hypervisor_nvoc.c | 15 nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_hypervisor_nvoc.h | 163 nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_i2c_api_nvoc.c | 147 nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_i2c_api_nvoc.h | 140 nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_intr_nvoc.c | 144 nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_intr_nvoc.h | 374 nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_intr_service_nvoc.h | 4 nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_io_vaspace_nvoc.c | 19 nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_io_vaspace_nvoc.h | 8 nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_ioaccess_nvoc.c | 113 nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_ioaccess_nvoc.h | 236 nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_journal_nvoc.c | 15 nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_journal_nvoc.h | 28 nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_kern_bus_nvoc.c | 476 nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_kern_bus_nvoc.h | 328 nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_kern_disp_nvoc.c | 183 nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_kern_disp_nvoc.h | 217 nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_kern_fsp_nvoc.c | 99 nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_kern_fsp_nvoc.h | 66 nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_kern_gmmu_nvoc.c | 221 nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_kern_gmmu_nvoc.h | 326 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nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/libraries/libspdm/2.3.1/library/spdm_common_lib/libspdm_com_crypto_service_session.c | 686 nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/libraries/libspdm/2.3.1/library/spdm_common_lib/libspdm_com_msg_log.c | 102 nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/libraries/libspdm/2.3.1/library/spdm_common_lib/libspdm_com_opaque_data.c | 232 nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/libraries/libspdm/2.3.1/library/spdm_common_lib/libspdm_com_support.c | 231 nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/libraries/libspdm/2.3.1/library/spdm_crypt_lib/libspdm_crypt_aead.c | 159 nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/libraries/libspdm/2.3.1/library/spdm_crypt_lib/libspdm_crypt_asym.c | 1154 nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/libraries/libspdm/2.3.1/library/spdm_crypt_lib/libspdm_crypt_cert.c | 1325 nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/libraries/libspdm/2.3.1/library/spdm_crypt_lib/libspdm_crypt_dhe.c | 270 nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/libraries/libspdm/2.3.1/library/spdm_crypt_lib/libspdm_crypt_hash.c | 477 nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/libraries/libspdm/2.3.1/library/spdm_crypt_lib/libspdm_crypt_hkdf.c | 127 nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/libraries/libspdm/2.3.1/library/spdm_crypt_lib/libspdm_crypt_hmac.c | 419 nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/libraries/libspdm/2.3.1/library/spdm_crypt_lib/libspdm_crypt_rng.c | 15 nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/libraries/libspdm/2.3.1/library/spdm_requester_lib/libspdm_req_common.c | 174 nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/libraries/libspdm/2.3.1/library/spdm_requester_lib/libspdm_req_communication.c | 368 nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/libraries/libspdm/2.3.1/library/spdm_requester_lib/libspdm_req_end_session.c | 165 nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/libraries/libspdm/2.3.1/library/spdm_requester_lib/libspdm_req_finish.c | 576 nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/libraries/libspdm/2.3.1/library/spdm_requester_lib/libspdm_req_get_capabilities.c | 337 nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/libraries/libspdm/2.3.1/library/spdm_requester_lib/libspdm_req_get_certificate.c | 511 nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/libraries/libspdm/2.3.1/library/spdm_requester_lib/libspdm_req_get_digests.c | 273 nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/libraries/libspdm/2.3.1/library/spdm_requester_lib/libspdm_req_get_measurements.c | 679 nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/libraries/libspdm/2.3.1/library/spdm_requester_lib/libspdm_req_get_version.c | 222 nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/libraries/libspdm/2.3.1/library/spdm_requester_lib/libspdm_req_handle_error_response.c | 418 nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/libraries/libspdm/2.3.1/library/spdm_requester_lib/libspdm_req_key_exchange.c | 777 nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/libraries/libspdm/2.3.1/library/spdm_requester_lib/libspdm_req_key_update.c | 326 nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/libraries/libspdm/2.3.1/library/spdm_requester_lib/libspdm_req_negotiate_algorithms.c | 531 nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/libraries/libspdm/2.3.1/library/spdm_requester_lib/libspdm_req_send_receive.c | 685 nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/libraries/libspdm/2.3.1/library/spdm_secured_message_lib/libspdm_secmes_context_data.c | 398 nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/libraries/libspdm/2.3.1/library/spdm_secured_message_lib/libspdm_secmes_encode_decode.c | 580 nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/libraries/libspdm/2.3.1/library/spdm_secured_message_lib/libspdm_secmes_key_exchange.c | 108 nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/libraries/libspdm/2.3.1/library/spdm_secured_message_lib/libspdm_secmes_session.c | 1113 nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/libraries/libspdm/2.3.1/os_stub/include/library/malloclib.h | 64 nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/libraries/libspdm/2.3.1/os_stub/include/library/rnglib.h | 27 nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/libraries/libspdm/2.3.1/os_stub/memlib/compare_mem.c | 49 nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/libraries/libspdm/2.3.1/os_stub/platform_lib_null/time_linux.c | 17 nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/libraries/libspdm/2.3.1/os_stub/platform_lib_null/watchdog.c | 45 nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/libraries/libspdm/2.3.1/os_stub/spdm_crypt_ext_lib/cryptlib_ext.h | 668 nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/libraries/libspdm/2.3.1/os_stub/spdm_device_secret_lib_null/lib.c | 105 nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/libraries/libspdm/nvidia/nvspdm_crypt_null.c | 54 nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/libraries/libspdm/nvidia/nvspdm_cryptlib_extensions.h | 41 nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/libraries/libspdm/nvidia/nvspdm_debuglib.c | 58 nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/libraries/libspdm/nvidia/nvspdm_malloclib.c | 49 nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/libraries/libspdm/nvidia/nvspdm_memlib.c | 147 nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/libraries/libspdm/nvidia/nvspdm_rmconfig.h | 129 nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/libraries/libspdm/nvidia/nvspdm_rng.c | 48 nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/libraries/libspdm/nvidia/openspdm.mk | 99 nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/libraries/mmu/gmmu_fmt.c | 2 nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/libraries/mmu/mmu_walk.c | 61 nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/libraries/mmu/mmu_walk_fill.c | 74 nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/libraries/mmu/mmu_walk_private.h | 2 nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/libraries/nvoc/src/runtime.c | 50 nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/libraries/nvport/cpu/cpu_common.c | 2 nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/libraries/nvport/cpu/cpu_x86_amd64.c | 64 nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/libraries/nvport/cpu/cpu_x86_amd64.h | 60 nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/libraries/nvport/crypto/crypto_random_xorshift.c | 18 nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/libraries/nvport/memory/memory_tracking.c | 478 nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/libraries/nvport/memory/memory_unix_kernel_os.c | 4 nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/libraries/poolalloc/poolalloc.c | 118 nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/libraries/prereq_tracker/prereq_tracker.c | 2 nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/libraries/resserv/src/rs_client.c | 83 nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/libraries/resserv/src/rs_resource.c | 44 nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/libraries/resserv/src/rs_server.c | 360 nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/libraries/utils/nvassert.c | 21 nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/srcs.mk | 120 nvidia-open-gpu-kernel-modules-535.161.08/version.mk | 2 1777 files changed, 323871 insertions(+), 114906 deletions(-) diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/CHANGELOG.md nvidia-open-gpu-kernel-modules-535.161.08/CHANGELOG.md --- nvidia-open-gpu-kernel-modules-525.147.05/CHANGELOG.md 2023-10-25 21:08:29.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/CHANGELOG.md 2024-03-05 23:13:29.000000000 +0000 @@ -1,11 +1,65 @@ # Changelog +## Release 535 Entries + +### [535.129.03] 2023-10-31 + +### [535.113.01] 2023-09-21 + +#### Fixed + +- Fixed building main against current centos stream 8 fails, [#550](https://github.com/NVIDIA/open-gpu-kernel-modules/issues/550) by @airlied + +### [535.104.05] 2023-08-22 + +### [535.98] 2023-08-08 + +### [535.86.10] 2023-07-31 + +### [535.86.05] 2023-07-18 + +### [535.54.03] 2023-06-14 + +### [535.43.02] 2023-05-30 + +#### Fixed + +- Fixed console restore with traditional VGA consoles. + +#### Added + +- Added support for Run Time D3 (RTD3) on Ampere and later GPUs. +- Added support for G-Sync on desktop GPUs. + +## Release 530 Entries + +### [530.41.03] 2023-03-23 + +### [530.30.02] 2023-02-28 + +#### Changed + +- GSP firmware is now distributed as `gsp_tu10x.bin` and `gsp_ga10x.bin` to better reflect the GPU architectures supported by each firmware file in this release. + - The .run installer will continue to install firmware to /lib/firmware/nvidia/ and the nvidia.ko kernel module will load the appropriate firmware for each GPU at runtime. + +#### Fixed + +- Add support for resizable BAR on Linux when NVreg_EnableResizableBar=1 module param is set. [#3](https://github.com/NVIDIA/open-gpu-kernel-modules/pull/3) by @sjkelly + +#### Added + +- Support for power management features like Suspend, Hibernate and Resume. + ## Release 525 Entries +### [525.147.05] 2023-10-31 + #### Fixed - Fix nvidia_p2p_get_pages(): Fix double-free in register-callback error path, [#557](https://github.com/NVIDIA/open-gpu-kernel-modules/pull/557) by @BrendanCunningham +### [525.125.06] 2023-06-26 + ### [525.116.04] 2023-05-09 ### [525.116.03] 2023-04-25 diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/README.md nvidia-open-gpu-kernel-modules-535.161.08/README.md --- nvidia-open-gpu-kernel-modules-525.147.05/README.md 2023-10-25 21:08:29.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/README.md 2024-03-05 23:13:29.000000000 +0000 @@ -1,7 +1,7 @@ # NVIDIA Linux Open GPU Kernel Module Source This is the source release of the NVIDIA Linux open GPU kernel modules, -version 525.147.05. +version 535.161.08. ## How to Build @@ -17,7 +17,7 @@ Note that the kernel modules built here must be used with GSP firmware and user-space NVIDIA GPU driver components from a corresponding -525.147.05 driver release. This can be achieved by installing +535.161.08 driver release. This can be achieved by installing the NVIDIA GPU driver from the .run file using the `--no-kernel-modules` option. E.g., @@ -162,12 +162,25 @@ - `src/nvidia/` The OS-agnostic code for nvidia.ko - `src/nvidia-modeset/` The OS-agnostic code for nvidia-modeset.ko - `src/common/` Utility code used by one or more of nvidia.ko and nvidia-modeset.ko +- `nouveau/` Tools for integration with the Nouveau device driver + + +## Nouveau device driver integration + +The Python script in the 'nouveau' directory is used to extract some of the +firmware binary images (and related data) encoded in the source code and +store them as distinct files. These files are used by the Nouveau device +driver to load and communicate with the GSP firmware. + +The layout of the binary files is described in nouveau_firmware_layout.ods, +which is an OpenDocument Spreadsheet file, compatible with most spreadsheet +software applications. ## Compatible GPUs The open-gpu-kernel-modules can be used on any Turing or later GPU -(see the table below). However, in the 525.147.05 release, +(see the table below). However, in the 535.161.08 release, GeForce and Workstation support is still considered alpha-quality. To enable use of the open kernel modules on GeForce and Workstation GPUs, @@ -175,7 +188,7 @@ parameter to 1. For more details, see the NVIDIA GPU driver end user README here: -https://us.download.nvidia.com/XFree86/Linux-x86_64/525.147.05/README/kernel_open.html +https://us.download.nvidia.com/XFree86/Linux-x86_64/535.161.08/README/kernel_open.html In the below table, if three IDs are listed, the first is the PCI Device ID, the second is the PCI Subsystem Vendor ID, and the third is the PCI @@ -654,6 +667,7 @@ | NVIDIA A30 | 20B7 10DE 1532 | | NVIDIA A30 | 20B7 10DE 1804 | | NVIDIA A30 | 20B7 10DE 1852 | +| NVIDIA A800-SXM4-40GB | 20BD 10DE 17F4 | | NVIDIA A100-PCIE-40GB | 20F1 10DE 145F | | NVIDIA A800-SXM4-80GB | 20F3 10DE 179B | | NVIDIA A800-SXM4-80GB | 20F3 10DE 179C | @@ -665,6 +679,11 @@ | NVIDIA A800-SXM4-80GB | 20F3 10DE 17A2 | | NVIDIA A800 80GB PCIe | 20F5 10DE 1799 | | NVIDIA A800 80GB PCIe LC | 20F5 10DE 179A | +| NVIDIA A800 40GB Active | 20F6 1028 180A | +| NVIDIA A800 40GB Active | 20F6 103C 180A | +| NVIDIA A800 40GB Active | 20F6 10DE 180A | +| NVIDIA A800 40GB Active | 20F6 17AA 180A | +| NVIDIA AX800 | 20FD 10DE 17F8 | | NVIDIA GeForce GTX 1660 Ti | 2182 | | NVIDIA GeForce GTX 1660 | 2184 | | NVIDIA GeForce GTX 1650 SUPER | 2187 | @@ -723,13 +742,20 @@ | NVIDIA A10 | 2236 10DE 1482 | | NVIDIA A10G | 2237 10DE 152F | | NVIDIA A10M | 2238 10DE 1677 | +| NVIDIA H100 NVL | 2321 10DE 1839 | | NVIDIA H800 PCIe | 2322 10DE 17A4 | | NVIDIA H800 | 2324 10DE 17A6 | | NVIDIA H800 | 2324 10DE 17A8 | +| NVIDIA H20 | 2329 10DE 198B | +| NVIDIA H20 | 2329 10DE 198C | | NVIDIA H100 80GB HBM3 | 2330 10DE 16C0 | | NVIDIA H100 80GB HBM3 | 2330 10DE 16C1 | | NVIDIA H100 PCIe | 2331 10DE 1626 | | NVIDIA H100 | 2339 10DE 17FC | +| NVIDIA H800 NVL | 233A 10DE 183A | +| NVIDIA GH200 120GB | 2342 10DE 16EB | +| NVIDIA GH200 120GB | 2342 10DE 1805 | +| NVIDIA GH200 480GB | 2342 10DE 1809 | | NVIDIA GeForce RTX 3060 Ti | 2414 | | NVIDIA GeForce RTX 3080 Ti Laptop GPU | 2420 | | NVIDIA RTX A5500 Laptop GPU | 2438 | @@ -782,6 +808,7 @@ | NVIDIA RTX A2000 12GB | 2571 10DE 1611 | | NVIDIA RTX A2000 12GB | 2571 17AA 1611 | | NVIDIA GeForce RTX 3050 | 2582 | +| NVIDIA GeForce RTX 3050 | 2584 | | NVIDIA GeForce RTX 3050 Ti Laptop GPU | 25A0 | | NVIDIA GeForce RTX 3050Ti Laptop GPU | 25A0 103C 8928 | | NVIDIA GeForce RTX 3050Ti Laptop GPU | 25A0 103C 89F9 | @@ -818,8 +845,17 @@ | NVIDIA RTX 6000 Ada Generation | 26B1 103C 16A1 | | NVIDIA RTX 6000 Ada Generation | 26B1 10DE 16A1 | | NVIDIA RTX 6000 Ada Generation | 26B1 17AA 16A1 | +| NVIDIA RTX 5000 Ada Generation | 26B2 1028 17FA | +| NVIDIA RTX 5000 Ada Generation | 26B2 103C 17FA | +| NVIDIA RTX 5000 Ada Generation | 26B2 10DE 17FA | +| NVIDIA RTX 5000 Ada Generation | 26B2 17AA 17FA | +| NVIDIA RTX 5880 Ada Generation | 26B3 103C 1934 | +| NVIDIA RTX 5880 Ada Generation | 26B3 10DE 1934 | | NVIDIA L40 | 26B5 10DE 169D | | NVIDIA L40 | 26B5 10DE 17DA | +| NVIDIA L40S | 26B9 10DE 1851 | +| NVIDIA L40S | 26B9 10DE 18CF | +| NVIDIA L20 | 26BA 10DE 1957 | | NVIDIA GeForce RTX 4080 | 2704 | | NVIDIA GeForce RTX 4090 Laptop GPU | 2717 | | NVIDIA RTX 5000 Ada Generation Laptop GPU | 2730 | @@ -832,11 +868,21 @@ | NVIDIA RTX 4000 SFF Ada Generation | 27B0 103C 16FA | | NVIDIA RTX 4000 SFF Ada Generation | 27B0 10DE 16FA | | NVIDIA RTX 4000 SFF Ada Generation | 27B0 17AA 16FA | +| NVIDIA RTX 4500 Ada Generation | 27B1 1028 180C | +| NVIDIA RTX 4500 Ada Generation | 27B1 103C 180C | +| NVIDIA RTX 4500 Ada Generation | 27B1 10DE 180C | +| NVIDIA RTX 4500 Ada Generation | 27B1 17AA 180C | +| NVIDIA RTX 4000 Ada Generation | 27B2 1028 181B | +| NVIDIA RTX 4000 Ada Generation | 27B2 103C 181B | +| NVIDIA RTX 4000 Ada Generation | 27B2 10DE 181B | +| NVIDIA RTX 4000 Ada Generation | 27B2 17AA 181B | +| NVIDIA L2 | 27B6 10DE 1933 | | NVIDIA L4 | 27B8 10DE 16CA | | NVIDIA L4 | 27B8 10DE 16EE | | NVIDIA RTX 4000 Ada Generation Laptop GPU | 27BA | | NVIDIA RTX 3500 Ada Generation Laptop GPU | 27BB | | NVIDIA GeForce RTX 4080 Laptop GPU | 27E0 | +| NVIDIA RTX 3500 Ada Generation Embedded GPU | 27FB | | NVIDIA GeForce RTX 4060 Ti | 2803 | | NVIDIA GeForce RTX 4060 Ti | 2805 | | NVIDIA GeForce RTX 4070 Laptop GPU | 2820 | diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/debian/.gitignore nvidia-open-gpu-kernel-modules-535.161.08/debian/.gitignore --- nvidia-open-gpu-kernel-modules-525.147.05/debian/.gitignore 1970-01-01 00:00:00.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/debian/.gitignore 2024-03-28 16:15:50.000000000 +0000 @@ -0,0 +1 @@ +/patches/*~ diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/debian/bug-control.mk nvidia-open-gpu-kernel-modules-535.161.08/debian/bug-control.mk --- nvidia-open-gpu-kernel-modules-525.147.05/debian/bug-control.mk 2023-12-03 11:31:14.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/debian/bug-control.mk 2024-03-28 16:15:50.000000000 +0000 @@ -49,11 +49,15 @@ libcuda1-any libcuda.so.1 libnvidia-ml.so.1 - nvidia-settings + nvidia-cuda-mps + nvidia-powerd + nvidia-suspend-common + nvidia-modprobe + nvidia-settings$(-variant) nvidia-xconfig + nvidia-persistenced nvidia-support nvidia-kernel-common - nvidia-modprobe xserver-xorg xserver-xorg-core xserver-xorg-legacy diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/debian/changelog nvidia-open-gpu-kernel-modules-535.161.08/debian/changelog --- nvidia-open-gpu-kernel-modules-525.147.05/debian/changelog 2023-12-03 11:31:14.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/debian/changelog 2024-03-28 16:15:50.000000000 +0000 @@ -1,3 +1,107 @@ +nvidia-open-gpu-kernel-modules (535.161.08-1~deb12u1) bookworm; urgency=medium + + * Rebuild for bookworm. + + -- Andreas Beckmann Thu, 28 Mar 2024 17:15:50 +0100 + +nvidia-open-gpu-kernel-modules (535.161.08-1) unstable; urgency=medium + + * New upstream Tesla branch release 535.161.08 (2024-03-18). + * Upload to unstable. + + -- Andreas Beckmann Thu, 28 Mar 2024 07:52:45 +0100 + +nvidia-open-gpu-kernel-modules (535.161.07-1) experimental; urgency=medium + + * New upstream LTS and Tesla branch release 535.161.07 (2024-02-22). + * Fixed CVE-2024-0074, CVE-2024-0075, CVE-2024-0078. (Closes: #1064991) + https://nvidia.custhelp.com/app/answers/detail/a_id/5520 + * Sync with src:nvidia-graphics-drivers. + * Refresh patches. + * Upload to experimental. + + -- Andreas Beckmann Wed, 27 Mar 2024 07:58:43 +0100 + +nvidia-open-gpu-kernel-modules (535.154.05-1) unstable; urgency=medium + + * New upstream LTS and Tesla branch release 535.154.05 (2024-01-16). + * New upstream long term support branch release 535.146.02 (2023-12-07). + * Sync with src:nvidia-graphics-drivers. + + -- Andreas Beckmann Wed, 27 Mar 2024 18:28:57 +0100 + +nvidia-open-gpu-kernel-modules (535.129.03-1) unstable; urgency=medium + + * New upstream LTS and Tesla branch release 535.129.03 (2023-10-31). + * Fixed CVE-2023-31022. (Closes: #1055144) + https://nvidia.custhelp.com/app/answers/detail/a_id/5491 + * Sync with src:nvidia-graphics-drivers. + + -- Andreas Beckmann Wed, 27 Mar 2024 11:14:40 +0100 + +nvidia-open-gpu-kernel-modules (535.113.01-1) unstable; urgency=medium + + * New upstream long term support branch release 535.113.01 (2023-09-21). + * New upstream Tesla branch release 535.104.12 (2023-09-25). + * New upstream LTS and Tesla branch release 535.104.05 (2023-08-22). + * New upstream long term support branch release 535.98 (2023-08-08). + * New upstream Tesla branch release 535.86.10 (2023-07-31). + * New upstream long term support branch release 535.86.05 (2023-07-18). + * Sync with src:nvidia-graphics-drivers. + * Refresh patches. + + -- Andreas Beckmann Mon, 25 Mar 2024 20:55:03 +0100 + +nvidia-open-gpu-kernel-modules (535.54.03-1) UNRELEASED; urgency=medium + + * New upstream LTS and Tesla branch release 535.54.03 (2023-06-14). + * Fixed CVE-2023-25515, CVE-2023-25516. (Closes: #1039686) + https://nvidia.custhelp.com/app/answers/detail/a_id/5468 + * Sync with src:nvidia-graphics-drivers. + + -- Andreas Beckmann Fri, 22 Mar 2024 10:37:58 +0100 + +nvidia-open-gpu-kernel-modules (535.43.02-1) UNRELEASED; urgency=medium + + * New upstream beta 535.43.02 (2023-05-30). + * Refresh patches. + * Sync with src:nvidia-graphics-drivers. + + -- Andreas Beckmann Thu, 21 Mar 2024 14:03:08 +0100 + +nvidia-open-gpu-kernel-modules (530.41.03-1) unstable; urgency=medium + + * New upstream new feature branch release 530.41.03 (2023-03-23). + * Fixed CVE-2023-0184, CVE-2023-0189, CVE-2023-0180, CVE-2023-0183, + CVE-2023-0185, CVE-2023-0187, CVE-2023-0198, CVE-2023-0199, + CVE-2023-0188, CVE-2023-0190, CVE-2023-0194, CVE-2023-0195, + CVE-2023-0191. (Closes: #1033783) + https://nvidia.custhelp.com/app/answers/detail/a_id/5452 + * Sync with src:nvidia-graphics-drivers. + * Fix package build reproducibility. + + -- Andreas Beckmann Wed, 20 Mar 2024 12:01:32 +0100 + +nvidia-open-gpu-kernel-modules (530.30.02-1) UNRELEASED; urgency=medium + + * New upstream beta 530.30.02 (2023-02-28). + * Refresh patches. + * Sync with src:nvidia-graphics-drivers. + + -- Andreas Beckmann Wed, 20 Mar 2024 09:50:41 +0100 + +nvidia-open-gpu-kernel-modules (525.147.05-3) unstable; urgency=medium + + * Sync with src:nvidia-graphics-drivers. + + -- Andreas Beckmann Fri, 08 Mar 2024 11:29:08 +0100 + +nvidia-open-gpu-kernel-modules (525.147.05-2) unstable; urgency=medium + + * Sync with src:nvidia-graphics-drivers. + + -- Andreas Beckmann Mon, 29 Jan 2024 01:36:28 +0100 + nvidia-open-gpu-kernel-modules (525.147.05-1~deb12u1) bookworm; urgency=medium * Rebuild for bookworm. @@ -6,7 +110,7 @@ nvidia-open-gpu-kernel-modules (525.147.05-1) unstable; urgency=medium - * New upstream production branch release 525.147.05 (2023-10-31). + * New upstream production and Tesla branch release 525.147.05 (2023-10-31). * Fixed CVE-2023-31022. (Closes: #1055144) https://nvidia.custhelp.com/app/answers/detail/a_id/5491 * Refresh patches. @@ -29,7 +133,7 @@ nvidia-open-gpu-kernel-modules (525.125.06-1) unstable; urgency=medium - * New upstream production branch release 525.125.06 (2023-06-26). + * New upstream production and Tesla branch release 525.125.06 (2023-06-26). * Fixed CVE-2023-25515, CVE-2023-25516. (Closes: #1039686) https://nvidia.custhelp.com/app/answers/detail/a_id/5468 @@ -52,7 +156,7 @@ nvidia-open-gpu-kernel-modules (525.105.17-1) unstable; urgency=medium - * New upstream production branch release 525.105.17 (2023-03-30). + * New upstream production and Tesla branch release 525.105.17 (2023-03-30). * Fixed CVE-2023-0184, CVE-2023-0189, CVE-2023-0180, CVE-2023-0183, CVE-2023-0185, CVE-2023-0187, CVE-2023-0198, CVE-2023-0199, CVE-2023-0188, CVE-2023-0190, CVE-2023-0194, CVE-2023-0195, @@ -70,10 +174,10 @@ nvidia-open-gpu-kernel-modules (525.85.12-1) unstable; urgency=medium - * New upstream production branch release 525.85.12 (2023-01-30). + * New upstream Tesla branch release 525.85.12 (2023-01-30). * New upstream production branch release 525.85.05 (2023-01-19). * New upstream production branch release 525.78.01 (2023-01-05). - * New upstream production branch release 525.60.13 (2022-12-05). + * New upstream production and Tesla branch release 525.60.13 (2022-12-05). * New upstream production branch release 525.60.11 (2022-11-28). * Fixed CVE-2022-34670, CVE-2022-34673, CVE-2022-34674, CVE-2022-34675, CVE-2022-34677, CVE-2022-34679, CVE-2022-34680, CVE-2022-34682, @@ -97,7 +201,7 @@ nvidia-open-gpu-kernel-modules (515.86.01-1) unstable; urgency=medium - * New upstream production branch release 515.86.01 (2022-11-22). + * New upstream production and Tesla branch release 515.86.01 (2022-11-22). * Fixed CVE-2022-34670, CVE-2022-34673, CVE-2022-34674, CVE-2022-34675, CVE-2022-34677, CVE-2022-34679, CVE-2022-34680, CVE-2022-34682, CVE-2022-34684, CVE-2022-42254, CVE-2022-42255, CVE-2022-42256, @@ -112,13 +216,14 @@ nvidia-open-gpu-kernel-modules (515.76-1) experimental; urgency=medium * New upstream production branch release 515.76 (2022-09-20). + * New upstream Tesla branch release (amd64 only) 515.65.07 (2022-10-19). * Refresh patches. -- Andreas Beckmann Thu, 26 Jan 2023 02:31:53 +0100 nvidia-open-gpu-kernel-modules (515.65.01-1) experimental; urgency=medium - * New upstream production branch release 515.65.01 (2022-08-02). + * New upstream production and Tesla branch release 515.65.01 (2022-08-02). * New upstream production branch release 515.57 (2022-06-28). * Add versioned Provides: nvidia-open-kernel-dkms-any. @@ -126,7 +231,7 @@ nvidia-open-gpu-kernel-modules (515.48.07-1) experimental; urgency=medium - * New upstream production branch release 515.48.07 (2022-05-31). + * New upstream production and Tesla branch release 515.48.07 (2022-05-31). * Refresh patches. * Add salsa-ci.yml. diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/debian/control nvidia-open-gpu-kernel-modules-535.161.08/debian/control --- nvidia-open-gpu-kernel-modules-525.147.05/debian/control 2023-12-03 11:31:14.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/debian/control 2024-03-28 16:15:50.000000000 +0000 @@ -24,7 +24,7 @@ Architecture: amd64 arm64 Multi-Arch: foreign Depends: - ${nvidia}-alternative-${nvidia:Version} | nvidia-alternative-${nvidia:Version} | nvidia-tesla-alternative-${nvidia:Version}, + ${nvidia}-alternative-${nvidia:Version} | nvidia-alternative-${nvidia:Version}, nvidia-kernel-common (>= 20151021), nvidia-modprobe (>= ${nvidia:Version:major}), ${misc:Depends} @@ -71,6 +71,9 @@ ${nvidia:Models} . Building the kernel modules has been tested up to Linux ${nvidia:kmod:tested:Linux}. + . + Note: The new 'non-free-firmware' archive area has to be enabled in apt's + sources.list(.d/) in order to install firmware-${nvidia}-gsp. #Package: ${nvidia-kernel}-source Package: nvidia-open-kernel-source diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/debian/copyright nvidia-open-gpu-kernel-modules-535.161.08/debian/copyright --- nvidia-open-gpu-kernel-modules-525.147.05/debian/copyright 2023-12-03 11:31:14.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/debian/copyright 2024-03-28 16:15:50.000000000 +0000 @@ -11,7 +11,7 @@ Files: * Copyright: - (c) 1993-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + (c) 1993-2024 NVIDIA CORPORATION & AFFILIATES. All rights reserved. License: Expat Comment: Except where noted otherwise, the individual files within this package are @@ -48,7 +48,7 @@ Files: debian/* Copyright: - © 2022-2023 Andreas Beckmann + © 2022-2024 Andreas Beckmann License: Expat License: Expat diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/debian/patches/hmm.patch nvidia-open-gpu-kernel-modules-535.161.08/debian/patches/hmm.patch --- nvidia-open-gpu-kernel-modules-525.147.05/debian/patches/hmm.patch 1970-01-01 00:00:00.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/debian/patches/hmm.patch 2024-03-28 16:15:50.000000000 +0000 @@ -0,0 +1,17 @@ +Author: Andreas Beckmann +Description: some hmm bits are not always available + hmm_pfn_to_page() was introduced in Linux 5.8 + +--- a/kernel-open/nvidia-uvm/uvm_ats.h ++++ b/kernel-open/nvidia-uvm/uvm_ats.h +@@ -38,7 +38,9 @@ + // hmm_range_fault() needs CONFIG_HMM_MIRROR. To detect racing CPU invalidates + // of memory regions while hmm_range_fault() is being called, MMU interval + // notifiers are needed. +- #if defined(CONFIG_HMM_MIRROR) && defined(NV_MMU_INTERVAL_NOTIFIER) ++// hmm_pfn_to_page() was added in Linux 5.8 (2733ea144dcce) ++ #if defined(CONFIG_HMM_MIRROR) && defined(NV_MMU_INTERVAL_NOTIFIER) && \ ++ LINUX_VERSION_CODE >= KERNEL_VERSION(5, 8, 0) + #define UVM_ATS_PREFETCH_SUPPORTED() 1 + #else + #define UVM_ATS_PREFETCH_SUPPORTED() 0 diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/debian/patches/module/0001-bump-minimum-supported-kernel-version-to-3.10.patch nvidia-open-gpu-kernel-modules-535.161.08/debian/patches/module/0001-bump-minimum-supported-kernel-version-to-3.10.patch --- nvidia-open-gpu-kernel-modules-525.147.05/debian/patches/module/0001-bump-minimum-supported-kernel-version-to-3.10.patch 2023-12-03 11:31:14.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/debian/patches/module/0001-bump-minimum-supported-kernel-version-to-3.10.patch 2024-03-28 16:15:50.000000000 +0000 @@ -1,4 +1,4 @@ -From fe3344d88a7c56419d42de6efef5161031c77928 Mon Sep 17 00:00:00 2001 +From e09fd1e4a2ef0ed3971d2d8798116559ce0ac25d Mon Sep 17 00:00:00 2001 From: Andreas Beckmann Date: Mon, 31 Oct 2022 15:10:08 +0100 Subject: [PATCH] bump minimum supported kernel version to 3.10 @@ -9,7 +9,7 @@ 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/common/inc/nv-linux.h b/common/inc/nv-linux.h -index 792287b..9f32e4e 100644 +index 90df696..2a4a756 100644 --- a/common/inc/nv-linux.h +++ b/common/inc/nv-linux.h @@ -57,8 +57,8 @@ diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/debian/patches/module/0002-conftest.sh-remove-empty-lines-from-uts_release-outp.patch nvidia-open-gpu-kernel-modules-535.161.08/debian/patches/module/0002-conftest.sh-remove-empty-lines-from-uts_release-outp.patch --- nvidia-open-gpu-kernel-modules-525.147.05/debian/patches/module/0002-conftest.sh-remove-empty-lines-from-uts_release-outp.patch 2023-12-03 11:31:14.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/debian/patches/module/0002-conftest.sh-remove-empty-lines-from-uts_release-outp.patch 2024-03-28 16:15:50.000000000 +0000 @@ -1,4 +1,4 @@ -From 40b15aa3ac67bfefa097f6a28b24e9d5cd9013a2 Mon Sep 17 00:00:00 2001 +From a1133243e871c1932499e29193c8afbd4349c915 Mon Sep 17 00:00:00 2001 From: Andreas Beckmann Date: Mon, 31 Oct 2022 14:40:42 +0100 Subject: [PATCH] conftest.sh: remove empty lines from uts_release output @@ -8,10 +8,10 @@ 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/conftest.sh b/conftest.sh -index 0ea3f3d..4af088d 100755 +index e883f3e..962b418 100755 --- a/conftest.sh +++ b/conftest.sh -@@ -5489,7 +5489,7 @@ compile_test() { +@@ -5856,7 +5856,7 @@ compile_test() { echo "#include UTS_RELEASE" > conftest$$.c diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/debian/patches/module/0034-fix-typos.patch nvidia-open-gpu-kernel-modules-535.161.08/debian/patches/module/0034-fix-typos.patch --- nvidia-open-gpu-kernel-modules-525.147.05/debian/patches/module/0034-fix-typos.patch 1970-01-01 00:00:00.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/debian/patches/module/0034-fix-typos.patch 2024-03-28 16:15:50.000000000 +0000 @@ -0,0 +1,48 @@ +From 73d99e0834961ad70a90963d42a8a1d8d225e87d Mon Sep 17 00:00:00 2001 +From: Andreas Beckmann +Date: Wed, 31 Jan 2024 03:06:19 +0100 +Subject: [PATCH] fix typos + +--- + nvidia-uvm/uvm_perf_thrashing.c | 4 ++-- + nvidia/nv.c | 2 +- + 2 files changed, 3 insertions(+), 3 deletions(-) + +diff --git a/nvidia-uvm/uvm_perf_thrashing.c b/nvidia-uvm/uvm_perf_thrashing.c +index ee5eef4..3032615 100644 +--- a/nvidia-uvm/uvm_perf_thrashing.c ++++ b/nvidia-uvm/uvm_perf_thrashing.c +@@ -318,7 +318,7 @@ module_param(uvm_perf_thrashing_max_resets, uint, S_IRUGO); + unsigned uvm_perf_map_remote_on_native_atomics_fault = 0; + module_param(uvm_perf_map_remote_on_native_atomics_fault, uint, S_IRUGO); + +-// Global post-processed values of the module parameters. They can be overriden ++// Global post-processed values of the module parameters. They can be overridden + // per VA-space. + static bool g_uvm_perf_thrashing_enable; + static unsigned g_uvm_perf_thrashing_threshold; +@@ -566,7 +566,7 @@ static void va_space_thrashing_info_init_params(va_space_thrashing_info_t *va_sp + va_space_thrashing->params.threshold = g_uvm_perf_thrashing_threshold; + va_space_thrashing->params.pin_threshold = g_uvm_perf_thrashing_pin_threshold; + +- // Default thrashing parameters are overriden for simulated/emulated GPUs ++ // Default thrashing parameters are overridden for simulated/emulated GPUs + if (g_uvm_global.num_simulated_devices > 0 && + (g_uvm_perf_thrashing_lapse_usec == UVM_PERF_THRASHING_LAPSE_USEC_DEFAULT)) { + va_space_thrashing->params.lapse_ns = UVM_PERF_THRASHING_LAPSE_USEC_DEFAULT_EMULATION * 1000; +diff --git a/nvidia/nv.c b/nvidia/nv.c +index 5a43c52..592a228 100644 +--- a/nvidia/nv.c ++++ b/nvidia/nv.c +@@ -4485,7 +4485,7 @@ NvU64 NV_API_CALL nv_get_dma_start_address( + * Otherwise, the DMA start address only needs to be set once, and it + * won't change afterward. Just return the cached value if asked again, + * to avoid the kernel printing redundant messages to the kernel +- * log when we call pci_set_dma_mask(). ++ * log when we call dma_set_mask(). + */ + if ((nv_tce_bypass_mode == NV_TCE_BYPASS_MODE_DISABLE) || + (nvl->tce_bypass_enabled)) +-- +2.20.1 + diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/debian/patches/module/bashisms.patch nvidia-open-gpu-kernel-modules-535.161.08/debian/patches/module/bashisms.patch --- nvidia-open-gpu-kernel-modules-525.147.05/debian/patches/module/bashisms.patch 2023-12-03 11:31:14.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/debian/patches/module/bashisms.patch 2024-03-28 16:15:50.000000000 +0000 @@ -3,7 +3,7 @@ --- a/conftest.sh +++ b/conftest.sh -@@ -6019,7 +6019,7 @@ case "$5" in +@@ -6696,7 +6696,7 @@ case "$5" in if [ -n "$VGX_BUILD" ]; then if [ -f /proc/xen/capabilities ]; then diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/debian/patches/module/cc_version_check-gcc5.patch nvidia-open-gpu-kernel-modules-535.161.08/debian/patches/module/cc_version_check-gcc5.patch --- nvidia-open-gpu-kernel-modules-525.147.05/debian/patches/module/cc_version_check-gcc5.patch 2023-12-03 11:31:14.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/debian/patches/module/cc_version_check-gcc5.patch 2024-03-28 16:15:50.000000000 +0000 @@ -5,7 +5,7 @@ --- a/conftest.sh +++ b/conftest.sh -@@ -5849,7 +5849,7 @@ case "$5" in +@@ -6530,7 +6530,7 @@ case "$5" in kernel_cc_minor=`echo ${kernel_cc_version} | cut -d '.' -f 2` echo " diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/debian/patches/module/conftest-prefer-arch-headers.patch nvidia-open-gpu-kernel-modules-535.161.08/debian/patches/module/conftest-prefer-arch-headers.patch --- nvidia-open-gpu-kernel-modules-525.147.05/debian/patches/module/conftest-prefer-arch-headers.patch 2023-12-03 11:31:14.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/debian/patches/module/conftest-prefer-arch-headers.patch 2024-03-28 16:15:50.000000000 +0000 @@ -5,7 +5,7 @@ --- a/conftest.sh +++ b/conftest.sh -@@ -149,18 +149,18 @@ build_cflags() { +@@ -144,18 +144,18 @@ build_cflags() { fi # Add the mach-default includes (only found on x86/older kernels) diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/debian/patches/module/conftest-verbose.patch nvidia-open-gpu-kernel-modules-535.161.08/debian/patches/module/conftest-verbose.patch --- nvidia-open-gpu-kernel-modules-525.147.05/debian/patches/module/conftest-verbose.patch 2023-12-03 11:31:14.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/debian/patches/module/conftest-verbose.patch 2024-03-28 16:15:50.000000000 +0000 @@ -3,7 +3,7 @@ --- a/Kbuild +++ b/Kbuild -@@ -162,6 +162,16 @@ NV_CONFTEST_HEADERS += $(obj)/conftest/h +@@ -170,6 +170,16 @@ NV_CONFTEST_HEADERS += $(obj)/conftest/h NV_CONFTEST_HEADERS += $(NV_CONFTEST_COMPILE_TEST_HEADERS) @@ -20,7 +20,7 @@ # # Generate a header file for a single conftest compile test. Each compile test # header depends on conftest.sh, as well as the generated conftest/headers.h -@@ -186,6 +196,8 @@ define NV_GENERATE_COMPILE_TEST_HEADER +@@ -194,6 +204,8 @@ define NV_GENERATE_COMPILE_TEST_HEADER @mkdir -p $(obj)/conftest @# concatenate /dev/null to prevent cat from hanging when $$^ is empty @cat $$^ /dev/null > $$@ @@ -29,7 +29,7 @@ endef # -@@ -205,9 +217,11 @@ $(eval $(call NV_GENERATE_COMPILE_TEST_H +@@ -213,9 +225,11 @@ $(eval $(call NV_GENERATE_COMPILE_TEST_H $(eval $(call NV_GENERATE_COMPILE_TEST_HEADER,symbols,$(NV_CONFTEST_SYMBOL_COMPILE_TESTS))) $(eval $(call NV_GENERATE_COMPILE_TEST_HEADER,types,$(NV_CONFTEST_TYPE_COMPILE_TESTS))) @@ -42,7 +42,7 @@ # Each of these headers is checked for presence with a test #include; a -@@ -309,6 +323,7 @@ NV_HEADER_PRESENCE_PART = $(addprefix $( +@@ -322,6 +336,7 @@ NV_HEADER_PRESENCE_PART = $(addprefix $( define NV_HEADER_PRESENCE_CHECK $$(call NV_HEADER_PRESENCE_PART,$(1)): $$(NV_CONFTEST_SCRIPT) $(obj)/conftest/uts_release @mkdir -p $$(dir $$@) @@ -50,7 +50,7 @@ @$$(NV_CONFTEST_CMD) test_kernel_header '$$(NV_CONFTEST_CFLAGS)' '$(1)' > $$@ endef -@@ -318,6 +333,8 @@ $(foreach header,$(NV_HEADER_PRESENCE_TE +@@ -331,6 +346,8 @@ $(foreach header,$(NV_HEADER_PRESENCE_TE # Concatenate all of the parts into headers.h. $(obj)/conftest/headers.h: $(call NV_HEADER_PRESENCE_PART,$(NV_HEADER_PRESENCE_TESTS)) @cat $^ > $@ @@ -59,7 +59,7 @@ clean-dirs := $(obj)/conftest -@@ -338,7 +355,8 @@ BUILD_SANITY_CHECKS = \ +@@ -351,7 +368,8 @@ BUILD_SANITY_CHECKS = \ .PHONY: $(BUILD_SANITY_CHECKS) @@ -69,7 +69,7 @@ @$(NV_CONFTEST_CMD) $@ full_output # Perform all sanity checks before generating the conftest headers -@@ -347,11 +365,13 @@ $(NV_CONFTEST_HEADERS): | $(BUILD_SANITY +@@ -360,11 +378,13 @@ $(NV_CONFTEST_HEADERS): | $(BUILD_SANITY # Make the conftest headers depend on the kernel version string diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/debian/patches/module/ppc64el.patch nvidia-open-gpu-kernel-modules-535.161.08/debian/patches/module/ppc64el.patch --- nvidia-open-gpu-kernel-modules-525.147.05/debian/patches/module/ppc64el.patch 2023-12-03 11:31:14.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/debian/patches/module/ppc64el.patch 1970-01-01 00:00:00.000000000 +0000 @@ -1,19 +0,0 @@ -Author: Andreas Beckmann -Description: fix ppc64el ftfbs - ---- a/nvidia/nvlink_common.h -+++ b/nvidia/nvlink_common.h -@@ -28,6 +28,13 @@ - extern "C" { - #endif - -+#if defined(NV_ASM_PROM_H_PRESENT) -+#if defined(NV_LINUX_OF_H_PRESENT) -+#include -+#endif -+#include -+#endif -+ - #include "nvtypes.h" - #include "nvCpuUuid.h" - #include "nvlink_errors.h" diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/debian/patches/module/series.in nvidia-open-gpu-kernel-modules-535.161.08/debian/patches/module/series.in --- nvidia-open-gpu-kernel-modules-525.147.05/debian/patches/module/series.in 2023-12-03 11:31:14.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/debian/patches/module/series.in 2024-03-28 16:15:50.000000000 +0000 @@ -4,7 +4,7 @@ # kernel support 0001-bump-minimum-supported-kernel-version-to-3.10.patch 0002-conftest.sh-remove-empty-lines-from-uts_release-outp.patch -ppc64el.patch +0034-fix-typos.patch # build system updates fragile-ARCH.patch diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/debian/patches/module/use-kbuild-compiler.patch nvidia-open-gpu-kernel-modules-535.161.08/debian/patches/module/use-kbuild-compiler.patch --- nvidia-open-gpu-kernel-modules-525.147.05/debian/patches/module/use-kbuild-compiler.patch 2023-12-03 11:31:14.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/debian/patches/module/use-kbuild-compiler.patch 2024-03-28 16:15:50.000000000 +0000 @@ -20,7 +20,7 @@ ./split-object-file.sh $$module.ko; \ --- a/Kbuild +++ b/Kbuild -@@ -139,7 +139,7 @@ NV_CONFTEST_SCRIPT := $(src)/conftest.sh +@@ -147,7 +147,7 @@ NV_CONFTEST_SCRIPT := $(src)/conftest.sh NV_CONFTEST_HEADER := $(obj)/conftest/headers.h NV_CONFTEST_CMD := /bin/sh $(NV_CONFTEST_SCRIPT) \ diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/debian/patches/module/use-kbuild-flags.patch nvidia-open-gpu-kernel-modules-535.161.08/debian/patches/module/use-kbuild-flags.patch --- nvidia-open-gpu-kernel-modules-525.147.05/debian/patches/module/use-kbuild-flags.patch 2023-12-03 11:31:14.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/debian/patches/module/use-kbuild-flags.patch 2024-03-28 16:15:50.000000000 +0000 @@ -13,7 +13,7 @@ --- a/Kbuild +++ b/Kbuild -@@ -144,6 +144,12 @@ NV_CONFTEST_CMD := /bin/sh $(NV_CONFTEST +@@ -152,6 +152,12 @@ NV_CONFTEST_CMD := /bin/sh $(NV_CONFTEST NV_CFLAGS_FROM_CONFTEST := $(shell $(NV_CONFTEST_CMD) build_cflags) NV_CONFTEST_CFLAGS = $(NV_CFLAGS_FROM_CONFTEST) $(EXTRA_CFLAGS) -fno-pie diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/debian/patches/series nvidia-open-gpu-kernel-modules-535.161.08/debian/patches/series --- nvidia-open-gpu-kernel-modules-525.147.05/debian/patches/series 2023-12-03 11:31:14.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/debian/patches/series 2024-03-28 16:15:50.000000000 +0000 @@ -1,2 +1,3 @@ hardening.patch typos.patch +hmm.patch diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/debian/patches/typos.patch nvidia-open-gpu-kernel-modules-535.161.08/debian/patches/typos.patch --- nvidia-open-gpu-kernel-modules-525.147.05/debian/patches/typos.patch 2023-12-03 11:31:14.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/debian/patches/typos.patch 2024-03-28 16:15:50.000000000 +0000 @@ -3,8 +3,8 @@ --- a/kernel-open/nvidia-uvm/uvm_mmu.c +++ b/kernel-open/nvidia-uvm/uvm_mmu.c -@@ -981,7 +981,7 @@ static NV_STATUS try_get_ptes(uvm_page_t - // bit index just beyond the most significant bit used to index the current entry +@@ -1337,7 +1337,7 @@ static NV_STATUS try_get_ptes(uvm_page_t + // entry NvU32 addr_bit_shift = hal->num_va_bits(); - // track depth upon which the invalidate occured @@ -14,7 +14,7 @@ --- a/src/common/nvlink/kernel/nvlink/core/nvlink_link_mgmt.c +++ b/src/common/nvlink/kernel/nvlink/core/nvlink_link_mgmt.c -@@ -289,7 +289,7 @@ nvlink_core_poll_link_state +@@ -300,7 +300,7 @@ nvlink_core_poll_link_state if (!timeout) { NVLINK_PRINT((DBG_MODULE_NVLINK_CORE, NVLINK_DBG_LEVEL_ERRORS, @@ -23,7 +23,7 @@ __FUNCTION__)); NVLINK_PRINT((DBG_MODULE_NVLINK_CORE, NVLINK_DBG_LEVEL_ERRORS, -@@ -413,7 +413,7 @@ nvlink_core_poll_tx_sublink_state +@@ -424,7 +424,7 @@ nvlink_core_poll_tx_sublink_state if (!timeout) { NVLINK_PRINT((DBG_MODULE_NVLINK_CORE, NVLINK_DBG_LEVEL_ERRORS, @@ -32,7 +32,7 @@ __FUNCTION__)); NVLINK_PRINT((DBG_MODULE_NVLINK_CORE, NVLINK_DBG_LEVEL_ERRORS, -@@ -476,7 +476,7 @@ nvlink_core_poll_rx_sublink_state +@@ -487,7 +487,7 @@ nvlink_core_poll_rx_sublink_state if (!timeout) { NVLINK_PRINT((DBG_MODULE_NVLINK_CORE, NVLINK_DBG_LEVEL_ERRORS, @@ -43,7 +43,7 @@ NVLINK_PRINT((DBG_MODULE_NVLINK_CORE, NVLINK_DBG_LEVEL_ERRORS, --- a/src/nvidia-modeset/include/nvkms-types.h +++ b/src/nvidia-modeset/include/nvkms-types.h -@@ -1663,7 +1663,7 @@ typedef struct _NVDispHeadStateEvoRec { +@@ -1848,7 +1848,7 @@ typedef struct _NVDispApiHeadStateEvoRec * * The numVblankSyncObjectsCreated will ideally always be equal to * NVKMS_MAX_VBLANK_SYNC_OBJECTS_PER_HEAD, but could be lower if errors @@ -65,7 +65,7 @@ k); --- a/src/nvidia/src/kernel/diagnostics/gpu_acct.c +++ b/src/nvidia/src/kernel/diagnostics/gpu_acct.c -@@ -522,7 +522,7 @@ gpuacctSampleGpuUtil_out: +@@ -523,7 +523,7 @@ gpuacctSampleGpuUtil_out: if (status != NV_OK) { NV_PRINTF(LEVEL_ERROR, @@ -76,7 +76,7 @@ } --- a/src/nvidia/src/kernel/gpu/bus/arch/maxwell/kern_bus_gm107.c +++ b/src/nvidia/src/kernel/gpu/bus/arch/maxwell/kern_bus_gm107.c -@@ -3515,7 +3515,7 @@ kbusVerifyBar2_GM107 +@@ -3741,7 +3741,7 @@ kbusVerifyBar2_GM107 (NvU8 *)(pOffset - pKernelBus->virtualBar2[GPU_GFID_PF].pCpuMapping), testMemorySize); NV_PRINTF_COND(IS_EMULATION(pGpu), LEVEL_NOTICE, LEVEL_INFO, @@ -98,7 +98,7 @@ // Mechanism #5 (TYPE_WDDM_FAST_DMA_DEFERRED_NONPAGED): --- a/src/nvidia/src/kernel/gpu/mem_mgr/mem_mgr.c +++ b/src/nvidia/src/kernel/gpu/mem_mgr/mem_mgr.c -@@ -1744,7 +1744,7 @@ memmgrSetPartitionableMem_IMPL +@@ -1861,7 +1861,7 @@ memmgrSetPartitionableMem_IMPL // // Find out the first and the last region for which internal heap or // bRsvdRegion is true. In Ampere we should never have more than two @@ -107,7 +107,7 @@ // To-Do - Bug 2301972 - Make sure that reserved memory is aligned to VMMU // segments // -@@ -1781,14 +1781,14 @@ memmgrSetPartitionableMem_IMPL +@@ -1898,14 +1898,14 @@ memmgrSetPartitionableMem_IMPL else { // diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/debian/rules nvidia-open-gpu-kernel-modules-535.161.08/debian/rules --- nvidia-open-gpu-kernel-modules-525.147.05/debian/rules 2023-12-03 11:31:14.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/debian/rules 2024-03-28 16:15:50.000000000 +0000 @@ -1,7 +1,7 @@ #!/usr/bin/make -f # For reproducible builds. -export DATE = date --utc --date="@$(SOURCE_DATE_EPOCH)" +export DATE = env LC_ALL=POSIX date --utc --date="@$(SOURCE_DATE_EPOCH)" export WHOAMI = echo buildd export HOSTNAME = debian @@ -10,15 +10,16 @@ include /usr/share/dpkg/pkg-info.mk +NVIDIA_RELEASE = $(DEB_VERSION_UPSTREAM) +NVIDIA_MAJOR = $(firstword $(subst ., ,$(NVIDIA_RELEASE))) include debian/rules.defs NVIDIA_TESLA ?= LINUX_KMOD_VARIANT ?= LINUX_KMOD_TESTED ?= ARCH_LIST ?= amd64 -NVIDIA_RELEASE = $(DEB_VERSION_UPSTREAM) version = $(NVIDIA_RELEASE) -version_major = $(firstword $(subst ., ,$(version))) +version_major = $(NVIDIA_MAJOR) ifeq (yes,$(NVIDIA_TESLA)) variant = $(if $(NVIDIA_TESLA),tesla) variant_description = $(if $(NVIDIA_TESLA), (Tesla version)) @@ -132,7 +133,7 @@ --sort=name \ --mtime='@$(SOURCE_DATE_EPOCH)' \ --clamp-mtime \ - modules | xz -9 > $(module_source_txz) + modules | xz -T1 -9 > $(module_source_txz) tar tfv $(module_source_txz) $(RM) -r $(module_source_pkg)/usr/src/modules diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/debian/rules.defs nvidia-open-gpu-kernel-modules-535.161.08/debian/rules.defs --- nvidia-open-gpu-kernel-modules-525.147.05/debian/rules.defs 2023-12-03 11:31:14.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/debian/rules.defs 2024-03-28 16:15:50.000000000 +0000 @@ -1,6 +1,6 @@ LINUX_KMOD_VARIANT = -open -LINUX_KMOD_TESTED = 6.6 +LINUX_KMOD_TESTED = 6.7 ARCH_LIST = amd64 ARCH_LIST += arm64 diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/debian/source/lintian-overrides nvidia-open-gpu-kernel-modules-535.161.08/debian/source/lintian-overrides --- nvidia-open-gpu-kernel-modules-525.147.05/debian/source/lintian-overrides 2023-12-03 11:31:14.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/debian/source/lintian-overrides 2024-03-28 16:15:50.000000000 +0000 @@ -7,8 +7,5 @@ # debian/patches/module/series gets generated and applied during the build process patch-file-present-but-not-mentioned-in-series [debian/patches/module/*.patch] -# generated file (no source available) -very-long-line-length-in-source-file * > 512 [src/common/sdk/nvidia/inc/ctrl/ctrl0000/ctrl0000system.h:*] - # binary data very-long-line-length-in-source-file * > 512 [src/nvidia-modeset/src/shaders/g_*_shaders:*] diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/debian/sync.sh nvidia-open-gpu-kernel-modules-535.161.08/debian/sync.sh --- nvidia-open-gpu-kernel-modules-525.147.05/debian/sync.sh 2023-12-03 11:31:14.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/debian/sync.sh 2024-03-28 16:15:50.000000000 +0000 @@ -16,6 +16,7 @@ debian/sync.sh debian/watch debian/source/lintian-overrides +debian/tests/autopkgtest-pkg-dkms.conf debian/tests/control debian/upstream/metadata " diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/kernel-open/Kbuild nvidia-open-gpu-kernel-modules-535.161.08/kernel-open/Kbuild --- nvidia-open-gpu-kernel-modules-525.147.05/kernel-open/Kbuild 2023-10-25 20:33:18.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/kernel-open/Kbuild 2024-03-05 22:26:09.000000000 +0000 @@ -70,9 +70,13 @@ EXTRA_CFLAGS += -I$(src)/common/inc EXTRA_CFLAGS += -I$(src) -EXTRA_CFLAGS += -Wall -MD $(DEFINES) $(INCLUDES) -Wno-cast-qual -Wno-error -Wno-format-extra-args +EXTRA_CFLAGS += -Wall $(DEFINES) $(INCLUDES) -Wno-cast-qual -Wno-error -Wno-format-extra-args EXTRA_CFLAGS += -D__KERNEL__ -DMODULE -DNVRM -EXTRA_CFLAGS += -DNV_VERSION_STRING=\"525.147.05\" +EXTRA_CFLAGS += -DNV_VERSION_STRING=\"535.161.08\" + +ifneq ($(SYSSRCHOST1X),) + EXTRA_CFLAGS += -I$(SYSSRCHOST1X) +endif EXTRA_CFLAGS += -Wno-unused-function @@ -87,7 +91,8 @@ endif ifeq ($(NV_BUILD_TYPE),debug) - EXTRA_CFLAGS += -g -gsplit-dwarf + EXTRA_CFLAGS += -g + EXTRA_CFLAGS += $(call cc-option,-gsplit-dwarf,) endif EXTRA_CFLAGS += -ffreestanding @@ -118,6 +123,9 @@ EXTRA_CFLAGS += -DNV_CONFIG_X86_UV endif +ifdef VGX_FORCE_VFIO_PCI_CORE + EXTRA_CFLAGS += -DNV_VGPU_FORCE_VFIO_PCI_CORE +endif # # The conftest.sh script tests various aspects of the target kernel. @@ -212,8 +220,10 @@ drm/drm_auth.h \ drm/drm_gem.h \ drm/drm_crtc.h \ + drm/drm_color_mgmt.h \ drm/drm_atomic.h \ drm/drm_atomic_helper.h \ + drm/drm_atomic_state_helper.h \ drm/drm_encoder.h \ drm/drm_atomic_uapi.h \ drm/drm_drv.h \ @@ -237,7 +247,6 @@ linux/efi.h \ linux/kconfig.h \ linux/platform/tegra/mc_utils.h \ - linux/semaphore.h \ linux/printk.h \ linux/ratelimit.h \ linux/prio_tree.h \ @@ -259,6 +268,7 @@ linux/platform/tegra/dce/dce-client-ipc.h \ linux/nvhost.h \ linux/nvhost_t194.h \ + linux/host1x-next.h \ asm/book3s/64/hash-64k.h \ asm/set_memory.h \ asm/prom.h \ @@ -292,8 +302,11 @@ linux/iosys-map.h \ asm/coco.h \ linux/vfio_pci_core.h \ + linux/mdev.h \ soc/tegra/bpmp-abi.h \ - soc/tegra/bpmp.h + soc/tegra/bpmp.h \ + linux/cc_platform.h \ + asm/cpufeature.h # Filename to store the define for the header in $(1); this is only consumed by # the rule below that concatenates all of these together. diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/kernel-open/common/inc/nv-firmware-registry.h nvidia-open-gpu-kernel-modules-535.161.08/kernel-open/common/inc/nv-firmware-registry.h --- nvidia-open-gpu-kernel-modules-525.147.05/kernel-open/common/inc/nv-firmware-registry.h 1970-01-01 00:00:00.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/kernel-open/common/inc/nv-firmware-registry.h 2024-03-05 22:25:35.000000000 +0000 @@ -0,0 +1,83 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +// +// This file holds GPU firmware related registry key definitions that are +// shared between Windows and Unix +// + +#ifndef NV_FIRMWARE_REGISTRY_H +#define NV_FIRMWARE_REGISTRY_H + +// +// Registry key that when enabled, will enable use of GPU firmware. +// +// Possible mode values: +// 0 - Do not enable GPU firmware +// 1 - Enable GPU firmware +// 2 - (Default) Use the default enablement policy for GPU firmware +// +// Setting this to anything other than 2 will alter driver firmware- +// enablement policies, possibly disabling GPU firmware where it would +// have otherwise been enabled by default. +// +// Policy bits: +// +// POLICY_ALLOW_FALLBACK: +// As the normal behavior is to fail GPU initialization if this registry +// entry is set in such a way that results in an invalid configuration, if +// instead the user would like the driver to automatically try to fallback +// to initializing the failing GPU with firmware disabled, then this bit can +// be set (ex: 0x11 means try to enable GPU firmware but fall back if needed). +// Note that this can result in a mixed mode configuration (ex: GPU0 has +// firmware enabled, but GPU1 does not). +// +#define NV_REG_STR_ENABLE_GPU_FIRMWARE "EnableGpuFirmware" + +#define NV_REG_ENABLE_GPU_FIRMWARE_MODE_MASK 0x0000000F +#define NV_REG_ENABLE_GPU_FIRMWARE_MODE_DISABLED 0x00000000 +#define NV_REG_ENABLE_GPU_FIRMWARE_MODE_ENABLED 0x00000001 +#define NV_REG_ENABLE_GPU_FIRMWARE_MODE_DEFAULT 0x00000002 + +#define NV_REG_ENABLE_GPU_FIRMWARE_POLICY_MASK 0x000000F0 +#define NV_REG_ENABLE_GPU_FIRMWARE_POLICY_ALLOW_FALLBACK 0x00000010 + +#define NV_REG_ENABLE_GPU_FIRMWARE_DEFAULT_VALUE 0x00000012 + +// +// Registry key that when enabled, will send GPU firmware logs +// to the system log, when possible. +// +// Possible values: +// 0 - Do not send GPU firmware logs to the system log +// 1 - Enable sending of GPU firmware logs to the system log +// 2 - (Default) Enable sending of GPU firmware logs to the system log for +// the debug kernel driver build only +// +#define NV_REG_STR_ENABLE_GPU_FIRMWARE_LOGS "EnableGpuFirmwareLogs" + +#define NV_REG_ENABLE_GPU_FIRMWARE_LOGS_DISABLE 0x00000000 +#define NV_REG_ENABLE_GPU_FIRMWARE_LOGS_ENABLE 0x00000001 +#define NV_REG_ENABLE_GPU_FIRMWARE_LOGS_ENABLE_ON_DEBUG 0x00000002 + +#endif // NV_FIRMWARE_REGISTRY_H diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/kernel-open/common/inc/nv-firmware.h nvidia-open-gpu-kernel-modules-535.161.08/kernel-open/common/inc/nv-firmware.h --- nvidia-open-gpu-kernel-modules-525.147.05/kernel-open/common/inc/nv-firmware.h 2023-10-25 20:33:23.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/kernel-open/common/inc/nv-firmware.h 2024-03-05 22:25:35.000000000 +0000 @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2022-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -81,12 +81,12 @@ { switch (fw_chip_family) { - case NV_FIRMWARE_CHIP_FAMILY_AD10X: - return NV_FIRMWARE_PATH_FOR_FILENAME("gsp_ad10x.bin"); - case NV_FIRMWARE_CHIP_FAMILY_GH100: // fall through + case NV_FIRMWARE_CHIP_FAMILY_AD10X: // fall through + case NV_FIRMWARE_CHIP_FAMILY_GA10X: + return NV_FIRMWARE_PATH_FOR_FILENAME("gsp_ga10x.bin"); + case NV_FIRMWARE_CHIP_FAMILY_GA100: // fall through - case NV_FIRMWARE_CHIP_FAMILY_GA10X: // fall through case NV_FIRMWARE_CHIP_FAMILY_TU11X: // fall through case NV_FIRMWARE_CHIP_FAMILY_TU10X: return NV_FIRMWARE_PATH_FOR_FILENAME("gsp_tu10x.bin"); @@ -100,12 +100,12 @@ { switch (fw_chip_family) { - case NV_FIRMWARE_CHIP_FAMILY_AD10X: - return NV_FIRMWARE_PATH_FOR_FILENAME("gsp_log_ad10x.bin"); - case NV_FIRMWARE_CHIP_FAMILY_GH100: // fall through + case NV_FIRMWARE_CHIP_FAMILY_AD10X: // fall through + case NV_FIRMWARE_CHIP_FAMILY_GA10X: + return NV_FIRMWARE_PATH_FOR_FILENAME("gsp_log_ga10x.bin"); + case NV_FIRMWARE_CHIP_FAMILY_GA100: // fall through - case NV_FIRMWARE_CHIP_FAMILY_GA10X: // fall through case NV_FIRMWARE_CHIP_FAMILY_TU11X: // fall through case NV_FIRMWARE_CHIP_FAMILY_TU10X: return NV_FIRMWARE_PATH_FOR_FILENAME("gsp_log_tu10x.bin"); @@ -125,7 +125,7 @@ // which will then be invoked (at the top-level) for each // gsp_*.bin (but not gsp_log_*.bin) #if defined(NV_FIRMWARE_DECLARE_GSP_FILENAME) -NV_FIRMWARE_DECLARE_GSP_FILENAME("gsp_ad10x.bin") +NV_FIRMWARE_DECLARE_GSP_FILENAME("gsp_ga10x.bin") NV_FIRMWARE_DECLARE_GSP_FILENAME("gsp_tu10x.bin") #endif // defined(NV_FIRMWARE_DECLARE_GSP_FILENAME) diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/kernel-open/common/inc/nv-hypervisor.h nvidia-open-gpu-kernel-modules-535.161.08/kernel-open/common/inc/nv-hypervisor.h --- nvidia-open-gpu-kernel-modules-525.147.05/kernel-open/common/inc/nv-hypervisor.h 2023-10-25 20:33:23.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/kernel-open/common/inc/nv-hypervisor.h 2024-03-05 22:25:35.000000000 +0000 @@ -41,6 +41,7 @@ #define CMD_VGPU_VFIO_INJECT_INTERRUPT 1 #define CMD_VGPU_VFIO_REGISTER_MDEV 2 #define CMD_VGPU_VFIO_PRESENT 3 +#define CMD_VFIO_PCI_CORE_PRESENT 4 #define MAX_VF_COUNT_PER_GPU 64 @@ -91,30 +92,6 @@ NV_VGPU_DEV_IN_USE = 2 } VGPU_DEVICE_STATE; -typedef enum _VMBUS_CMD_TYPE -{ - VMBUS_CMD_TYPE_INVALID = 0, - VMBUS_CMD_TYPE_SETUP = 1, - VMBUS_CMD_TYPE_SENDPACKET = 2, - VMBUS_CMD_TYPE_CLEANUP = 3, -} VMBUS_CMD_TYPE; - -typedef struct -{ - NvU32 request_id; - NvU32 page_count; - NvU64 *pPfns; - void *buffer; - NvU32 bufferlen; -} vmbus_send_packet_cmd_params; - - -typedef struct -{ - NvU32 override_sint; - NvU8 *nv_guid; -} vmbus_setup_cmd_params; - /* * Function prototypes */ diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/kernel-open/common/inc/nv-ioctl-numa.h nvidia-open-gpu-kernel-modules-535.161.08/kernel-open/common/inc/nv-ioctl-numa.h --- nvidia-open-gpu-kernel-modules-525.147.05/kernel-open/common/inc/nv-ioctl-numa.h 2023-10-25 20:33:21.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/kernel-open/common/inc/nv-ioctl-numa.h 2024-03-05 22:25:33.000000000 +0000 @@ -62,6 +62,7 @@ uint64_t memblock_size __aligned(8); uint64_t numa_mem_addr __aligned(8); uint64_t numa_mem_size __aligned(8); + uint8_t use_auto_online; nv_offline_addresses_t offline_addresses __aligned(8); } nv_ioctl_numa_info_t; diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/kernel-open/common/inc/nv-ioctl.h nvidia-open-gpu-kernel-modules-535.161.08/kernel-open/common/inc/nv-ioctl.h --- nvidia-open-gpu-kernel-modules-525.147.05/kernel-open/common/inc/nv-ioctl.h 2023-10-25 20:33:20.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/kernel-open/common/inc/nv-ioctl.h 2024-03-05 22:25:33.000000000 +0000 @@ -104,7 +104,7 @@ #define NV_RM_API_VERSION_CMD_STRICT 0 #define NV_RM_API_VERSION_CMD_RELAXED '1' -#define NV_RM_API_VERSION_CMD_OVERRIDE '2' +#define NV_RM_API_VERSION_CMD_QUERY '2' #define NV_RM_API_VERSION_REPLY_UNRECOGNIZED 0 #define NV_RM_API_VERSION_REPLY_RECOGNIZED 1 diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/kernel-open/common/inc/nv-kthread-q.h nvidia-open-gpu-kernel-modules-535.161.08/kernel-open/common/inc/nv-kthread-q.h --- nvidia-open-gpu-kernel-modules-525.147.05/kernel-open/common/inc/nv-kthread-q.h 2023-10-25 20:33:24.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/kernel-open/common/inc/nv-kthread-q.h 2024-03-05 22:25:38.000000000 +0000 @@ -28,15 +28,10 @@ #include // list #include // task_struct #include // NUMA_NO_NODE +#include #include "conftest.h" -#if defined(NV_LINUX_SEMAPHORE_H_PRESENT) - #include -#else - #include -#endif - //////////////////////////////////////////////////////////////////////////////// // nv_kthread_q: // diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/kernel-open/common/inc/nv-linux.h nvidia-open-gpu-kernel-modules-535.161.08/kernel-open/common/inc/nv-linux.h --- nvidia-open-gpu-kernel-modules-525.147.05/kernel-open/common/inc/nv-linux.h 2023-10-25 20:33:21.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/kernel-open/common/inc/nv-linux.h 2024-03-05 22:25:33.000000000 +0000 @@ -211,6 +211,7 @@ #include #include +#include #include /* workqueue */ #include "nv-kthread-q.h" /* kthread based queue */ @@ -510,7 +511,11 @@ static inline void *nv_ioremap(NvU64 phys, NvU64 size) { +#if IS_ENABLED(CONFIG_INTEL_TDX_GUEST) && defined(NV_IOREMAP_DRIVER_HARDENED_PRESENT) + void *ptr = ioremap_driver_hardened(phys, size); +#else void *ptr = ioremap(phys, size); +#endif if (ptr) NV_MEMDBG_ADD(ptr, size); return ptr; @@ -523,11 +528,11 @@ static inline void *nv_ioremap_cache(NvU64 phys, NvU64 size) { -#if defined(NV_IOREMAP_CACHE_PRESENT) - void *ptr = ioremap_cache(phys, size); - if (ptr) - NV_MEMDBG_ADD(ptr, size); - return ptr; + void *ptr = NULL; +#if IS_ENABLED(CONFIG_INTEL_TDX_GUEST) && defined(NV_IOREMAP_CACHE_SHARED_PRESENT) + ptr = ioremap_cache_shared(phys, size); +#elif defined(NV_IOREMAP_CACHE_PRESENT) + ptr = ioremap_cache(phys, size); #elif defined(NVCPU_PPC64LE) // // ioremap_cache() has been only implemented correctly for ppc64le with @@ -542,25 +547,32 @@ // (commit 40f1ce7fb7e8, kernel 3.0+) and that covers all kernels we // support on power. // - void *ptr = ioremap_prot(phys, size, pgprot_val(PAGE_KERNEL)); - if (ptr) - NV_MEMDBG_ADD(ptr, size); - return ptr; + ptr = ioremap_prot(phys, size, pgprot_val(PAGE_KERNEL)); #else return nv_ioremap(phys, size); #endif -} -static inline void *nv_ioremap_wc(NvU64 phys, NvU64 size) -{ -#if defined(NV_IOREMAP_WC_PRESENT) - void *ptr = ioremap_wc(phys, size); if (ptr) NV_MEMDBG_ADD(ptr, size); + return ptr; +} + +static inline void *nv_ioremap_wc(NvU64 phys, NvU64 size) +{ + void *ptr = NULL; +#if IS_ENABLED(CONFIG_INTEL_TDX_GUEST) && defined(NV_IOREMAP_DRIVER_HARDENED_WC_PRESENT) + ptr = ioremap_driver_hardened_wc(phys, size); +#elif defined(NV_IOREMAP_WC_PRESENT) + ptr = ioremap_wc(phys, size); #else return nv_ioremap_nocache(phys, size); #endif + + if (ptr) + NV_MEMDBG_ADD(ptr, size); + + return ptr; } static inline void nv_iounmap(void *ptr, NvU64 size) @@ -633,6 +645,26 @@ free_pages(ptr, order); \ } +static inline pgprot_t nv_sme_clr(pgprot_t prot) +{ +#if defined(__sme_clr) + return __pgprot(__sme_clr(pgprot_val(prot))); +#else + return prot; +#endif // __sme_clr +} + +static inline pgprot_t nv_adjust_pgprot(pgprot_t vm_prot, NvU32 extra) +{ + pgprot_t prot = __pgprot(pgprot_val(vm_prot) | extra); + +#if defined(pgprot_decrypted) + return pgprot_decrypted(prot); +#else + return nv_sme_clr(prot); +#endif // pgprot_decrypted +} + #if defined(PAGE_KERNEL_NOENC) #if defined(__pgprot_mask) #define NV_PAGE_KERNEL_NOCACHE_NOENC __pgprot_mask(__PAGE_KERNEL_NOCACHE) @@ -654,7 +686,8 @@ #if defined(PAGE_KERNEL_NOENC) if (unencrypted) { - prot = cached ? PAGE_KERNEL_NOENC : NV_PAGE_KERNEL_NOCACHE_NOENC; + prot = cached ? nv_adjust_pgprot(PAGE_KERNEL_NOENC, 0) : + nv_adjust_pgprot(NV_PAGE_KERNEL_NOCACHE_NOENC, 0); } else #endif @@ -939,26 +972,6 @@ return ret; } -static inline pgprot_t nv_adjust_pgprot(pgprot_t vm_prot, NvU32 extra) -{ - pgprot_t prot = __pgprot(pgprot_val(vm_prot) | extra); -#if defined(CONFIG_AMD_MEM_ENCRYPT) && defined(NV_PGPROT_DECRYPTED_PRESENT) - /* - * When AMD memory encryption is enabled, device memory mappings with the - * C-bit set read as 0xFF, so ensure the bit is cleared for user mappings. - * - * If cc_mkdec() is present, then pgprot_decrypted() can't be used. - */ -#if defined(NV_CC_MKDEC_PRESENT) - prot = __pgprot(__sme_clr(pgprot_val(vm_prot))); -#else - prot = pgprot_decrypted(prot); -#endif -#endif - - return prot; -} - static inline int nv_io_remap_page_range(struct vm_area_struct *vma, NvU64 phys_addr, NvU64 size, NvU32 extra_prot) { @@ -1182,7 +1195,7 @@ NvBool zeroed : 1; NvBool aliased : 1; NvBool user : 1; - NvBool node0 : 1; + NvBool node : 1; NvBool peer_io : 1; NvBool physical : 1; NvBool unencrypted : 1; @@ -1196,6 +1209,7 @@ unsigned int pid; struct page **user_pages; NvU64 guest_id; /* id of guest VM */ + NvS32 node_id; /* Node id for memory allocation when node is set in flags */ void *import_priv; struct sg_table *import_sgt; } nv_alloc_t; @@ -1308,7 +1322,7 @@ * SEV memory encryption") forces SWIOTLB to be enabled when AMD SEV * is active in all cases. */ - if (os_sev_enabled) + if (os_cc_enabled) swiotlb_in_use = NV_TRUE; #endif @@ -1436,6 +1450,35 @@ NvBool nvlink; }; +/* Properties of the coherent link */ +typedef struct coherent_link_info_s { + /* Physical Address of the GPU memory in SOC AMAP. In the case of + * baremetal OS environment it is System Physical Address(SPA) and in the case + * of virutalized OS environment it is Intermediate Physical Address(IPA) */ + NvU64 gpu_mem_pa; + /* Bitmap of NUMA node ids, corresponding to the reserved PXMs, + * available for adding GPU memory to the kernel as system RAM */ + DECLARE_BITMAP(free_node_bitmap, MAX_NUMNODES); +} coherent_link_info_t; + +#if defined(NV_LINUX_ACPI_EVENTS_SUPPORTED) +/* + * acpi data storage structure + * + * This structure retains the pointer to the device, + * and any other baggage we want to carry along + * + */ +typedef struct +{ + nvidia_stack_t *sp; + struct acpi_device *device; + struct acpi_handle *handle; + void *notifier_data; + int notify_handler_installed; +} nv_acpi_t; +#endif + /* linux-specific version of old nv_state_t */ /* this is a general os-specific state structure. the first element *must* be the general state structure, for the generic unix-based code */ @@ -1451,6 +1494,13 @@ /* IBM-NPU info associated with this GPU */ nv_ibmnpu_info_t *npu; + /* coherent link information */ + coherent_link_info_t coherent_link_info; + + /* Dedicated queue to be used for removing FB memory which is onlined + * to kernel as a NUMA node. Refer Bug : 3879845*/ + nv_kthread_q_t remove_numa_memory_q; + /* NUMA node information for the platforms where GPU memory is presented * as a NUMA node to the kernel */ struct { @@ -1461,6 +1511,7 @@ /* NUMA online/offline status for platforms that support GPU memory as * NUMA node */ atomic_t status; + NvBool use_auto_online; } numa_info; nvidia_stack_t *sp[NV_DEV_STACK_COUNT]; @@ -1530,8 +1581,13 @@ /* Per-device notifier block for ACPI events */ struct notifier_block acpi_nb; +#if defined(NV_LINUX_ACPI_EVENTS_SUPPORTED) + nv_acpi_t* nv_acpi_object; +#endif + /* Lock serializing ISRs for different SOC vectors */ nv_spinlock_t soc_isr_lock; + void *soc_bh_mutex; struct nv_timer snapshot_timer; nv_spinlock_t snapshot_timer_lock; @@ -1577,24 +1633,6 @@ extern NvBool nv_ats_supported; -#if defined(NV_LINUX_ACPI_EVENTS_SUPPORTED) -/* - * acpi data storage structure - * - * This structure retains the pointer to the device, - * and any other baggage we want to carry along - * - */ -typedef struct -{ - nvidia_stack_t *sp; - struct acpi_device *device; - struct acpi_handle *handle; - int notify_handler_installed; -} nv_acpi_t; - -#endif - /* * file-private data * hide a pointer to our data structures in a file-private ptr @@ -1744,6 +1782,7 @@ extern NvU32 NVreg_EnableUserNUMAManagement; extern NvU32 NVreg_RegisterPCIDriver; +extern NvU32 NVreg_EnableResizableBar; extern NvU32 num_probed_nv_devices; extern NvU32 num_nv_devices; @@ -1938,6 +1977,36 @@ return 0; } +static inline NvBool nv_platform_use_auto_online(nv_linux_state_t *nvl) +{ + return nvl->numa_info.use_auto_online; +} + +typedef struct { + NvU64 base; + NvU64 size; + NvU32 nodeId; + int ret; +} remove_numa_memory_info_t; + +static void offline_numa_memory_callback +( + void *args +) +{ +#ifdef NV_OFFLINE_AND_REMOVE_MEMORY_PRESENT + remove_numa_memory_info_t *pNumaInfo = (remove_numa_memory_info_t *)args; +#ifdef NV_REMOVE_MEMORY_HAS_NID_ARG + pNumaInfo->ret = offline_and_remove_memory(pNumaInfo->nodeId, + pNumaInfo->base, + pNumaInfo->size); +#else + pNumaInfo->ret = offline_and_remove_memory(pNumaInfo->base, + pNumaInfo->size); +#endif +#endif +} + typedef enum { NV_NUMA_STATUS_DISABLED = 0, @@ -1998,4 +2067,7 @@ #include #endif +#define NV_EXPORT_SYMBOL(symbol) EXPORT_SYMBOL_GPL(symbol) +#define NV_CHECK_EXPORT_SYMBOL(symbol) NV_IS_EXPORT_SYMBOL_PRESENT_##symbol + #endif /* _NV_LINUX_H_ */ diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/kernel-open/common/inc/nv-lock.h nvidia-open-gpu-kernel-modules-535.161.08/kernel-open/common/inc/nv-lock.h --- nvidia-open-gpu-kernel-modules-525.147.05/kernel-open/common/inc/nv-lock.h 2023-10-25 20:33:24.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/kernel-open/common/inc/nv-lock.h 2024-03-05 22:25:39.000000000 +0000 @@ -29,17 +29,12 @@ #include #include #include /* signal_pending, cond_resched */ +#include #if defined(NV_LINUX_SCHED_SIGNAL_H_PRESENT) #include /* signal_pending for kernels >= 4.11 */ #endif -#if defined(NV_LINUX_SEMAPHORE_H_PRESENT) -#include -#else -#include -#endif - #if defined(CONFIG_PREEMPT_RT) || defined(CONFIG_PREEMPT_RT_FULL) typedef raw_spinlock_t nv_spinlock_t; #define NV_SPIN_LOCK_INIT(lock) raw_spin_lock_init(lock) @@ -62,20 +57,7 @@ #define NV_SPIN_UNLOCK_WAIT(lock) spin_unlock_wait(lock) #endif -#if defined(NV_CONFIG_PREEMPT_RT) -#define NV_INIT_SEMA(sema, val) sema_init(sema,val) -#else -#if !defined(__SEMAPHORE_INITIALIZER) && defined(__COMPAT_SEMAPHORE_INITIALIZER) -#define __SEMAPHORE_INITIALIZER __COMPAT_SEMAPHORE_INITIALIZER -#endif -#define NV_INIT_SEMA(sema, val) \ - { \ - struct semaphore __sema = \ - __SEMAPHORE_INITIALIZER(*(sema), val); \ - *(sema) = __sema; \ - } -#endif -#define NV_INIT_MUTEX(mutex) NV_INIT_SEMA(mutex, 1) +#define NV_INIT_MUTEX(mutex) sema_init(mutex, 1) static inline int nv_down_read_interruptible(struct rw_semaphore *lock) { diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/kernel-open/common/inc/nv-pci.h nvidia-open-gpu-kernel-modules-535.161.08/kernel-open/common/inc/nv-pci.h --- nvidia-open-gpu-kernel-modules-525.147.05/kernel-open/common/inc/nv-pci.h 2023-10-25 20:33:21.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/kernel-open/common/inc/nv-pci.h 2024-03-05 22:25:33.000000000 +0000 @@ -27,6 +27,9 @@ #include #include "nv-linux.h" +#define NV_GPU_BAR1 1 +#define NV_GPU_BAR3 3 + int nv_pci_register_driver(void); void nv_pci_unregister_driver(void); int nv_pci_count_devices(void); diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/kernel-open/common/inc/nv.h nvidia-open-gpu-kernel-modules-535.161.08/kernel-open/common/inc/nv.h --- nvidia-open-gpu-kernel-modules-525.147.05/kernel-open/common/inc/nv.h 2023-10-25 20:33:20.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/kernel-open/common/inc/nv.h 2024-03-05 22:25:33.000000000 +0000 @@ -315,6 +315,7 @@ NV_SOC_IRQ_DPAUX_TYPE, NV_SOC_IRQ_GPIO_TYPE, NV_SOC_IRQ_HDACODEC_TYPE, + NV_SOC_IRQ_TCPC2DISP_TYPE, NV_SOC_IRQ_INVALID_TYPE } nv_soc_irq_type_t; @@ -329,6 +330,7 @@ NvU32 gpio_num; NvU32 dpaux_instance; } irq_data; + NvS32 ref_count; } nv_soc_irq_info_t; #define NV_MAX_SOC_IRQS 6 @@ -345,6 +347,12 @@ /* DMA-capable device data, defined by kernel interface layer */ typedef struct nv_dma_device nv_dma_device_t; +typedef struct nv_phys_addr_range +{ + NvU64 addr; + NvU64 len; +} nv_phys_addr_range_t; + typedef struct nv_state_t { void *priv; /* private data */ @@ -384,9 +392,11 @@ NvS32 current_soc_irq; NvU32 num_soc_irqs; NvU32 hdacodec_irq; + NvU32 tcpc2disp_irq; NvU8 *soc_dcb_blob; NvU32 soc_dcb_size; NvU32 disp_sw_soc_chip_id; + NvBool soc_is_dpalt_mode_supported; NvU32 igpu_stall_irq[NV_IGPU_MAX_STALL_IRQS]; NvU32 igpu_nonstall_irq; @@ -462,6 +472,9 @@ /* Bool to check if ISO iommu enabled */ NvBool iso_iommu_present; + /* Bool to check if NISO iommu enabled */ + NvBool niso_iommu_present; + /* Bool to check if dma-buf is supported */ NvBool dma_buf_supported; @@ -473,6 +486,8 @@ /* Bool to check if the device received a shutdown notification */ NvBool is_shutdown; + /* Bool to check if the GPU has a coherent sysmem link */ + NvBool coherent; } nv_state_t; // These define need to be in sync with defines in system.h @@ -507,6 +522,8 @@ typedef struct gpuSession *nvgpuSessionHandle_t; typedef struct gpuDevice *nvgpuDeviceHandle_t; typedef struct gpuAddressSpace *nvgpuAddressSpaceHandle_t; +typedef struct gpuTsg *nvgpuTsgHandle_t; +typedef struct UvmGpuTsgAllocParams_tag nvgpuTsgAllocParams_t; typedef struct gpuChannel *nvgpuChannelHandle_t; typedef struct UvmGpuChannelInfo_tag *nvgpuChannelInfo_t; typedef struct UvmGpuChannelAllocParams_tag nvgpuChannelAllocParams_t; @@ -533,7 +550,7 @@ typedef struct UvmGpuPagingChannel_tag *nvgpuPagingChannelHandle_t; typedef struct UvmGpuPagingChannelInfo_tag *nvgpuPagingChannelInfo_t; typedef enum UvmPmaGpuMemoryType_tag nvgpuGpuMemoryType_t; -typedef NV_STATUS (*nvPmaEvictPagesCallback)(void *, NvU32, NvU64 *, NvU32, NvU64, NvU64, nvgpuGpuMemoryType_t); +typedef NV_STATUS (*nvPmaEvictPagesCallback)(void *, NvU64, NvU64 *, NvU32, NvU64, NvU64, nvgpuGpuMemoryType_t); typedef NV_STATUS (*nvPmaEvictRangeCallback)(void *, NvU64, NvU64, nvgpuGpuMemoryType_t); /* @@ -598,9 +615,19 @@ #define NV_IS_DEVICE_IN_SURPRISE_REMOVAL(nv) \ (((nv)->flags & NV_FLAG_IN_SURPRISE_REMOVAL) != 0) +/* + * For console setup by EFI GOP, the base address is BAR1. + * For console setup by VBIOS, the base address is BAR2 + 16MB. + */ +#define NV_IS_CONSOLE_MAPPED(nv, addr) \ + (((addr) == (nv)->bars[NV_GPU_BAR_INDEX_FB].cpu_address) || \ + ((addr) == ((nv)->bars[NV_GPU_BAR_INDEX_IMEM].cpu_address + 0x1000000))) + #define NV_SOC_IS_ISO_IOMMU_PRESENT(nv) \ ((nv)->iso_iommu_present) +#define NV_SOC_IS_NISO_IOMMU_PRESENT(nv) \ + ((nv)->niso_iommu_present) /* * GPU add/remove events */ @@ -655,7 +682,8 @@ static inline NvBool IS_FB_OFFSET(nv_state_t *nv, NvU64 offset, NvU64 length) { - return ((nv->fb) && (offset >= nv->fb->cpu_address) && + return ((nv->fb) && (nv->fb->size != 0) && + (offset >= nv->fb->cpu_address) && ((offset + (length - 1)) >= offset) && ((offset + (length - 1)) <= (nv->fb->cpu_address + (nv->fb->size - 1)))); } @@ -745,7 +773,7 @@ void NV_API_CALL nv_set_dma_address_size (nv_state_t *, NvU32 ); NV_STATUS NV_API_CALL nv_alias_pages (nv_state_t *, NvU32, NvU32, NvU32, NvU64, NvU64 *, void **); -NV_STATUS NV_API_CALL nv_alloc_pages (nv_state_t *, NvU32, NvBool, NvU32, NvBool, NvBool, NvU64 *, void **); +NV_STATUS NV_API_CALL nv_alloc_pages (nv_state_t *, NvU32, NvBool, NvU32, NvBool, NvBool, NvS32, NvU64 *, void **); NV_STATUS NV_API_CALL nv_free_pages (nv_state_t *, NvU32, NvBool, NvU32, void *); NV_STATUS NV_API_CALL nv_register_user_pages (nv_state_t *, NvU64, NvU64 *, void *, void **); @@ -814,6 +842,7 @@ void NV_API_CALL nv_put_file_private(void *); NV_STATUS NV_API_CALL nv_get_device_memory_config(nv_state_t *, NvU64 *, NvU64 *, NvU32 *, NvS32 *); +NV_STATUS NV_API_CALL nv_get_egm_info(nv_state_t *, NvU64 *, NvU64 *, NvS32 *); NV_STATUS NV_API_CALL nv_get_ibmnpu_genreg_info(nv_state_t *, NvU64 *, NvU64 *, void**); NV_STATUS NV_API_CALL nv_get_ibmnpu_relaxed_ordering_mode(nv_state_t *nv, NvBool *mode); @@ -853,6 +882,8 @@ NvU32 NV_API_CALL nv_get_os_type(void); void NV_API_CALL nv_get_updated_emu_seg(NvU32 *start, NvU32 *end); +void NV_API_CALL nv_get_screen_info(nv_state_t *, NvU64 *, NvU16 *, NvU16 *, NvU16 *, NvU16 *, NvU64 *); + struct dma_buf; typedef struct nv_dma_buf nv_dma_buf_t; struct drm_gem_object; @@ -903,6 +934,7 @@ NvBool NV_API_CALL rm_isr (nvidia_stack_t *, nv_state_t *, NvU32 *); void NV_API_CALL rm_isr_bh (nvidia_stack_t *, nv_state_t *); void NV_API_CALL rm_isr_bh_unlocked (nvidia_stack_t *, nv_state_t *); +NvBool NV_API_CALL rm_is_msix_allowed (nvidia_stack_t *, nv_state_t *); NV_STATUS NV_API_CALL rm_power_management (nvidia_stack_t *, nv_state_t *, nv_pm_action_t); NV_STATUS NV_API_CALL rm_stop_user_channels (nvidia_stack_t *, nv_state_t *); NV_STATUS NV_API_CALL rm_restart_user_channels (nvidia_stack_t *, nv_state_t *); @@ -944,6 +976,8 @@ void NV_API_CALL rm_power_source_change_event (nvidia_stack_t *, NvU32); +void NV_API_CALL rm_request_dnotifier_state (nvidia_stack_t *, nv_state_t *); + void NV_API_CALL rm_disable_gpu_state_persistence (nvidia_stack_t *sp, nv_state_t *); NV_STATUS NV_API_CALL rm_p2p_init_mapping (nvidia_stack_t *, NvU64, NvU64 *, NvU64 *, NvU64 *, NvU64 *, NvU64, NvU64, NvU64, NvU64, void (*)(void *), void *); NV_STATUS NV_API_CALL rm_p2p_destroy_mapping (nvidia_stack_t *, NvU64); @@ -953,12 +987,12 @@ NV_STATUS NV_API_CALL rm_p2p_register_callback (nvidia_stack_t *, NvU64, NvU64, NvU64, void *, void (*)(void *), void *); NV_STATUS NV_API_CALL rm_p2p_put_pages (nvidia_stack_t *, NvU64, NvU32, NvU64, void *); NV_STATUS NV_API_CALL rm_p2p_put_pages_persistent(nvidia_stack_t *, void *, void *); -NV_STATUS NV_API_CALL rm_p2p_dma_map_pages (nvidia_stack_t *, nv_dma_device_t *, NvU8 *, NvU32, NvU32, NvU64 *, void **); -NV_STATUS NV_API_CALL rm_dma_buf_dup_mem_handle (nvidia_stack_t *, nv_state_t *, NvHandle, NvHandle, NvHandle, NvHandle, void *, NvHandle, NvU64, NvU64, NvHandle *); +NV_STATUS NV_API_CALL rm_p2p_dma_map_pages (nvidia_stack_t *, nv_dma_device_t *, NvU8 *, NvU64, NvU32, NvU64 *, void **); +NV_STATUS NV_API_CALL rm_dma_buf_dup_mem_handle (nvidia_stack_t *, nv_state_t *, NvHandle, NvHandle, NvHandle, NvHandle, void *, NvHandle, NvU64, NvU64, NvHandle *, void **); void NV_API_CALL rm_dma_buf_undup_mem_handle(nvidia_stack_t *, nv_state_t *, NvHandle, NvHandle); -NV_STATUS NV_API_CALL rm_dma_buf_map_mem_handle (nvidia_stack_t *, nv_state_t *, NvHandle, NvHandle, NvU64, NvU64, NvU64 *); -NV_STATUS NV_API_CALL rm_dma_buf_unmap_mem_handle(nvidia_stack_t *, nv_state_t *, NvHandle, NvHandle, NvU64, NvU64); -NV_STATUS NV_API_CALL rm_dma_buf_get_client_and_device(nvidia_stack_t *, nv_state_t *, NvHandle, NvHandle *, NvHandle *, NvHandle *, void **); +NV_STATUS NV_API_CALL rm_dma_buf_map_mem_handle (nvidia_stack_t *, nv_state_t *, NvHandle, NvHandle, NvU64, NvU64, void *, nv_phys_addr_range_t **, NvU32 *); +void NV_API_CALL rm_dma_buf_unmap_mem_handle(nvidia_stack_t *, nv_state_t *, NvHandle, NvHandle, NvU64, nv_phys_addr_range_t **, NvU32); +NV_STATUS NV_API_CALL rm_dma_buf_get_client_and_device(nvidia_stack_t *, nv_state_t *, NvHandle, NvHandle *, NvHandle *, NvHandle *, void **, NvBool *); void NV_API_CALL rm_dma_buf_put_client_and_device(nvidia_stack_t *, nv_state_t *, NvHandle, NvHandle, NvHandle, void *); NV_STATUS NV_API_CALL rm_log_gpu_crash (nv_stack_t *, nv_state_t *); @@ -991,6 +1025,7 @@ const char* NV_API_CALL rm_get_gpu_gcx_support(nvidia_stack_t *, nv_state_t *, NvBool); void NV_API_CALL rm_acpi_notify(nvidia_stack_t *, nv_state_t *, NvU32); +void NV_API_CALL rm_acpi_nvpcf_notify(nvidia_stack_t *); NvBool NV_API_CALL rm_is_altstack_in_use(void); diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/kernel-open/common/inc/nv_firmware_types.h nvidia-open-gpu-kernel-modules-535.161.08/kernel-open/common/inc/nv_firmware_types.h --- nvidia-open-gpu-kernel-modules-525.147.05/kernel-open/common/inc/nv_firmware_types.h 2023-10-25 20:33:22.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/kernel-open/common/inc/nv_firmware_types.h 1970-01-01 00:00:00.000000000 +0000 @@ -1,34 +0,0 @@ -/* - * SPDX-FileCopyrightText: Copyright (c) 2021 NVIDIA CORPORATION & AFFILIATES. All rights reserved. - * SPDX-License-Identifier: MIT - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER - * DEALINGS IN THE SOFTWARE. - */ - -#ifndef NV_FIRMWARE_TYPES_H -#define NV_FIRMWARE_TYPES_H - -typedef enum { - NV_FIRMWARE_MODE_DISABLED = 0, - NV_FIRMWARE_MODE_ENABLED = 1, - NV_FIRMWARE_MODE_DEFAULT = 2, - NV_FIRMWARE_MODE_INVALID = 0xFF -} NvFirmwareMode; - -#endif // NV_FIRMWARE_TYPES_H diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/kernel-open/common/inc/nv_uvm_interface.h nvidia-open-gpu-kernel-modules-535.161.08/kernel-open/common/inc/nv_uvm_interface.h --- nvidia-open-gpu-kernel-modules-525.147.05/kernel-open/common/inc/nv_uvm_interface.h 2023-10-25 20:33:22.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/kernel-open/common/inc/nv_uvm_interface.h 2024-03-05 22:25:35.000000000 +0000 @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 2013-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2013-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -327,7 +327,7 @@ // Mirrors pmaEvictPagesCb_t, see its documentation in pma.h. typedef NV_STATUS (*uvmPmaEvictPagesCallback)(void *callbackData, - NvU32 pageSize, + NvU64 pageSize, NvU64 *pPages, NvU32 count, NvU64 physBegin, @@ -390,7 +390,7 @@ */ NV_STATUS nvUvmInterfacePmaAllocPages(void *pPma, NvLength pageCount, - NvU32 pageSize, + NvU64 pageSize, UvmPmaAllocationOptions *pPmaAllocOptions, NvU64 *pPages); @@ -419,7 +419,7 @@ NV_STATUS nvUvmInterfacePmaPinPages(void *pPma, NvU64 *pPages, NvLength pageCount, - NvU32 pageSize, + NvU64 pageSize, NvU32 flags); /******************************************************************************* @@ -447,7 +447,7 @@ NV_STATUS nvUvmInterfacePmaUnpinPages(void *pPma, NvU64 *pPages, NvLength pageCount, - NvU32 pageSize); + NvU64 pageSize); /******************************************************************************* nvUvmInterfaceMemoryFree @@ -488,7 +488,7 @@ void nvUvmInterfacePmaFreePages(void *pPma, NvU64 *pPages, NvLength pageCount, - NvU32 pageSize, + NvU64 pageSize, NvU32 flags); /******************************************************************************* @@ -507,7 +507,7 @@ NV_STATUS nvUvmInterfaceMemoryCpuMap(uvmGpuAddressSpaceHandle vaSpace, UvmGpuPointer gpuPointer, NvLength length, void **cpuPtr, - NvU32 pageSize); + NvU64 pageSize); /******************************************************************************* uvmGpuMemoryCpuUnmap @@ -518,15 +518,58 @@ void *cpuPtr); /******************************************************************************* - nvUvmInterfaceChannelAllocate + nvUvmInterfaceTsgAllocate - This function will allocate a channel bound to a copy engine + This function allocates a Time-Slice Group (TSG). - allocParams must contain an engineIndex as channels need to be bound to an + allocParams must contain an engineIndex as TSGs need to be bound to an engine type at allocation time. The possible values are [0, - UVM_COPY_ENGINE_COUNT_MAX), but notably only the copy engines that have - UvmGpuCopyEngineCaps::supported set to true can be allocated. This struct - also contains information relative to GPFIFO and GPPut. + UVM_COPY_ENGINE_COUNT_MAX) for CE engine type. Notably only the copy engines + that have UvmGpuCopyEngineCaps::supported set to true can be allocated. + + Note that TSG is not supported on all GPU architectures for all engine + types, e.g., pre-Volta GPUs only support TSG for the GR/Compute engine type. + On devices that do not support HW TSGs on the requested engine, this API is + still required, i.e., a TSG handle is required in + nvUvmInterfaceChannelAllocate(), due to information stored in it necessary + for channel allocation. However, when HW TSGs aren't supported, a TSG handle + is essentially a "fake" TSG with no HW scheduling impact. + + tsg is filled with the address of the corresponding TSG handle. + + Arguments: + vaSpace[IN] - VA space linked to a client and a device under which + the TSG is allocated. + allocParams[IN] - structure with allocation settings. + tsg[OUT] - pointer to the new TSG handle. + + Error codes: + NV_ERR_GENERIC + NV_ERR_INVALID_ARGUMENT + NV_ERR_NO_MEMORY + NV_ERR_NOT_SUPPORTED +*/ +NV_STATUS nvUvmInterfaceTsgAllocate(uvmGpuAddressSpaceHandle vaSpace, + const UvmGpuTsgAllocParams *allocParams, + uvmGpuTsgHandle *tsg); + +/******************************************************************************* + nvUvmInterfaceTsgDestroy + + This function destroys a given TSG. + + Arguments: + tsg[IN] - Tsg handle +*/ +void nvUvmInterfaceTsgDestroy(uvmGpuTsgHandle tsg); + +/******************************************************************************* + nvUvmInterfaceChannelAllocate + + This function will allocate a channel bound to a copy engine(CE) or a SEC2 + engine. + + allocParams contains information relative to GPFIFO and GPPut. channel is filled with the address of the corresponding channel handle. @@ -536,17 +579,18 @@ Host channel submission doorbell. Arguments: - vaSpace[IN] - VA space linked to a client and a device under which - the channel will be allocated + tsg[IN] - Time-Slice Group that the channel will be a member. allocParams[IN] - structure with allocation settings channel[OUT] - pointer to the new channel handle channelInfo[OUT] - structure filled with channel information Error codes: NV_ERR_GENERIC + NV_ERR_INVALID_ARGUMENT NV_ERR_NO_MEMORY + NV_ERR_NOT_SUPPORTED */ -NV_STATUS nvUvmInterfaceChannelAllocate(uvmGpuAddressSpaceHandle vaSpace, +NV_STATUS nvUvmInterfaceChannelAllocate(const uvmGpuTsgHandle tsg, const UvmGpuChannelAllocParams *allocParams, uvmGpuChannelHandle *channel, UvmGpuChannelInfo *channelInfo); @@ -554,7 +598,7 @@ /******************************************************************************* nvUvmInterfaceChannelDestroy - This function destroys a given channel + This function destroys a given channel. Arguments: channel[IN] - channel handle @@ -575,7 +619,7 @@ NV_ERR_NO_MEMORY */ NV_STATUS nvUvmInterfaceQueryCaps(uvmGpuDeviceHandle device, - UvmGpuCaps * caps); + UvmGpuCaps *caps); /******************************************************************************* nvUvmInterfaceQueryCopyEnginesCaps @@ -922,6 +966,23 @@ NvU32 *numFaults); /******************************************************************************* + nvUvmInterfaceFlushReplayableFaultBuffer + + This function sends an RPC to GSP in order to flush the HW replayable fault buffer. + + NOTES: + - This function DOES NOT acquire the RM API or GPU locks. That is because + it is called during fault servicing, which could produce deadlocks. + + Arguments: + device[IN] - Device handle associated with the gpu + + Error codes: + NV_ERR_INVALID_ARGUMENT +*/ +NV_STATUS nvUvmInterfaceFlushReplayableFaultBuffer(uvmGpuDeviceHandle device); + +/******************************************************************************* nvUvmInterfaceInitAccessCntrInfo This function obtains access counter buffer address, size and a few register mappings @@ -929,13 +990,15 @@ Arguments: device[IN] - Device handle associated with the gpu pAccessCntrInfo[OUT] - Information provided by RM for access counter handling + accessCntrIndex[IN] - Access counter index Error codes: NV_ERR_GENERIC NV_ERR_INVALID_ARGUMENT */ NV_STATUS nvUvmInterfaceInitAccessCntrInfo(uvmGpuDeviceHandle device, - UvmGpuAccessCntrInfo *pAccessCntrInfo); + UvmGpuAccessCntrInfo *pAccessCntrInfo, + NvU32 accessCntrIndex); /******************************************************************************* nvUvmInterfaceDestroyAccessCntrInfo @@ -1054,11 +1117,13 @@ hMemory[IN] - Memory handle. offset [IN] - Offset from the beginning of the allocation where PTE mappings should begin. - Should be aligned with pagesize associated + Should be aligned with mappingPagesize + in gpuExternalMappingInfo associated with the allocation. size [IN] - Length of the allocation for which PTEs should be built. - Should be aligned with pagesize associated + Should be aligned with mappingPagesize + in gpuExternalMappingInfo associated with the allocation. size = 0 will be interpreted as the total size of the allocation. @@ -1383,4 +1448,243 @@ char *methodStream, NvU32 methodStreamSize); +/******************************************************************************* + CSL Interface and Locking + + The following functions do not acquire the RM API or GPU locks and must not be called + concurrently with the same UvmCslContext parameter in different threads. The caller must + guarantee this exclusion. + + * nvUvmInterfaceCslRotateIv + * nvUvmInterfaceCslEncrypt + * nvUvmInterfaceCslDecrypt + * nvUvmInterfaceCslSign + * nvUvmInterfaceCslQueryMessagePool + * nvUvmInterfaceCslIncrementIv +*/ + +/******************************************************************************* + nvUvmInterfaceCslInitContext + + Allocates and initializes a CSL context for a given secure channel. + + The lifetime of the context is the same as the lifetime of the secure channel + it is paired with. + + Arguments: + uvmCslContext[IN/OUT] - The CSL context. + channel[IN] - Handle to a secure channel. + + Error codes: + NV_ERR_INVALID_STATE - The system is not operating in Confidential Compute mode. + NV_ERR_INVALID_CHANNEL - The associated channel is not a secure channel. + NV_ERR_IN_USE - The context has already been initialized. +*/ +NV_STATUS nvUvmInterfaceCslInitContext(UvmCslContext *uvmCslContext, + uvmGpuChannelHandle channel); + +/******************************************************************************* + nvUvmInterfaceDeinitCslContext + + Securely deinitializes and clears the contents of a context. + + If context is already deinitialized then function returns immediately. + + Arguments: + uvmCslContext[IN] - The CSL context. +*/ +void nvUvmInterfaceDeinitCslContext(UvmCslContext *uvmCslContext); + +/******************************************************************************* + nvUvmInterfaceCslRotateIv + + Rotates the IV for a given channel and operation. + + This function will rotate the IV on both the CPU and the GPU. + Outstanding messages that have been encrypted by the GPU should first be + decrypted before calling this function with operation equal to + UVM_CSL_OPERATION_DECRYPT. Similarly, outstanding messages that have been + encrypted by the CPU should first be decrypted before calling this function + with operation equal to UVM_CSL_OPERATION_ENCRYPT. For a given operation + the channel must be idle before calling this function. This function can be + called regardless of the value of the IV's message counter. + + See "CSL Interface and Locking" for locking requirements. + This function does not perform dynamic memory allocation. + +Arguments: + uvmCslContext[IN/OUT] - The CSL context. + operation[IN] - Either + - UVM_CSL_OPERATION_ENCRYPT + - UVM_CSL_OPERATION_DECRYPT + + Error codes: + NV_ERR_INSUFFICIENT_RESOURCES - The rotate operation would cause a counter + to overflow. + NV_ERR_INVALID_ARGUMENT - Invalid value for operation. +*/ +NV_STATUS nvUvmInterfaceCslRotateIv(UvmCslContext *uvmCslContext, + UvmCslOperation operation); + +/******************************************************************************* + nvUvmInterfaceCslEncrypt + + Encrypts data and produces an authentication tag. + + Auth, input, and output buffers must not overlap. If they do then calling + this function produces undefined behavior. Performance is typically + maximized when the input and output buffers are 16-byte aligned. This is + natural alignment for AES block. + The encryptIV can be obtained from nvUvmInterfaceCslIncrementIv. + However, it is optional. If it is NULL, the next IV in line will be used. + + See "CSL Interface and Locking" for locking requirements. + This function does not perform dynamic memory allocation. + +Arguments: + uvmCslContext[IN/OUT] - The CSL context. + bufferSize[IN] - Size of the input and output buffers in + units of bytes. Value can range from 1 byte + to (2^32) - 1 bytes. + inputBuffer[IN] - Address of plaintext input buffer. + encryptIv[IN/OUT] - IV to use for encryption. Can be NULL. + outputBuffer[OUT] - Address of ciphertext output buffer. + authTagBuffer[OUT] - Address of authentication tag buffer. + Its size is UVM_CSL_CRYPT_AUTH_TAG_SIZE_BYTES. + + Error codes: + NV_ERR_INVALID_ARGUMENT - The size of the data is 0 bytes. + - The encryptIv has already been used. +*/ +NV_STATUS nvUvmInterfaceCslEncrypt(UvmCslContext *uvmCslContext, + NvU32 bufferSize, + NvU8 const *inputBuffer, + UvmCslIv *encryptIv, + NvU8 *outputBuffer, + NvU8 *authTagBuffer); + +/******************************************************************************* + nvUvmInterfaceCslDecrypt + + Verifies the authentication tag and decrypts data. + + Auth, input, and output buffers must not overlap. If they do then calling + this function produces undefined behavior. Performance is typically + maximized when the input and output buffers are 16-byte aligned. This is + natural alignment for AES block. + + See "CSL Interface and Locking" for locking requirements. + This function does not perform dynamic memory allocation. + + Arguments: + uvmCslContext[IN/OUT] - The CSL context. + bufferSize[IN] - Size of the input and output buffers in units of bytes. + Value can range from 1 byte to (2^32) - 1 bytes. + decryptIv[IN] - IV used to decrypt the ciphertext. Its value can either be given by + nvUvmInterfaceCslIncrementIv, or, if NULL, the CSL context's + internal counter is used. + inputBuffer[IN] - Address of ciphertext input buffer. + outputBuffer[OUT] - Address of plaintext output buffer. + addAuthData[IN] - Address of the plaintext additional authenticated data used to + calculate the authentication tag. Can be NULL. + addAuthDataSize[IN] - Size of the additional authenticated data in units of bytes. + Value can range from 1 byte to (2^32) - 1 bytes. + This parameter is ignored if addAuthData is NULL. + authTagBuffer[IN] - Address of authentication tag buffer. + Its size is UVM_CSL_CRYPT_AUTH_TAG_SIZE_BYTES. + + Error codes: + NV_ERR_INSUFFICIENT_RESOURCES - The decryption operation would cause a + counter overflow to occur. + NV_ERR_INVALID_ARGUMENT - The size of the data is 0 bytes. + NV_ERR_INVALID_DATA - Verification of the authentication tag fails. +*/ +NV_STATUS nvUvmInterfaceCslDecrypt(UvmCslContext *uvmCslContext, + NvU32 bufferSize, + NvU8 const *inputBuffer, + UvmCslIv const *decryptIv, + NvU8 *outputBuffer, + NvU8 const *addAuthData, + NvU32 addAuthDataSize, + NvU8 const *authTagBuffer); + +/******************************************************************************* + nvUvmInterfaceCslSign + + Generates an authentication tag for secure work launch. + + Auth and input buffers must not overlap. If they do then calling this function produces + undefined behavior. + + See "CSL Interface and Locking" for locking requirements. + This function does not perform dynamic memory allocation. + + Arguments: + uvmCslContext[IN/OUT] - The CSL context. + bufferSize[IN] - Size of the input buffer in units of bytes. + Value can range from 1 byte to (2^32) - 1 bytes. + inputBuffer[IN] - Address of plaintext input buffer. + authTagBuffer[OUT] - Address of authentication tag buffer. + Its size is UVM_CSL_SIGN_AUTH_TAG_SIZE_BYTES. + + Error codes: + NV_ERR_INSUFFICIENT_RESOURCES - The signing operation would cause a counter overflow to occur. + NV_ERR_INVALID_ARGUMENT - The size of the data is 0 bytes. +*/ +NV_STATUS nvUvmInterfaceCslSign(UvmCslContext *uvmCslContext, + NvU32 bufferSize, + NvU8 const *inputBuffer, + NvU8 *authTagBuffer); + +/******************************************************************************* + nvUvmInterfaceCslQueryMessagePool + + Returns the number of messages that can be encrypted before the message counter will overflow. + + See "CSL Interface and Locking" for locking requirements. + This function does not perform dynamic memory allocation. + + Arguments: + uvmCslContext[IN/OUT] - The CSL context. + operation[IN] - Either UVM_CSL_OPERATION_ENCRYPT or UVM_CSL_OPERATION_DECRYPT. + messageNum[OUT] - Number of messages left before overflow. + + Error codes: + NV_ERR_INVALID_ARGUMENT - The value of the operation parameter is illegal. +*/ +NV_STATUS nvUvmInterfaceCslQueryMessagePool(UvmCslContext *uvmCslContext, + UvmCslOperation operation, + NvU64 *messageNum); + +/******************************************************************************* + nvUvmInterfaceCslIncrementIv + + Increments the message counter by the specified amount. + + If iv is non-NULL then the incremented value is returned. + If operation is UVM_CSL_OPERATION_ENCRYPT then the returned IV's "freshness" bit is set and + can be used in nvUvmInterfaceCslEncrypt. If operation is UVM_CSL_OPERATION_DECRYPT then + the returned IV can be used in nvUvmInterfaceCslDecrypt. + + See "CSL Interface and Locking" for locking requirements. + This function does not perform dynamic memory allocation. + +Arguments: + uvmCslContext[IN/OUT] - The CSL context. + operation[IN] - Either + - UVM_CSL_OPERATION_ENCRYPT + - UVM_CSL_OPERATION_DECRYPT + increment[IN] - The amount by which the IV is incremented. Can be 0. + iv[out] - If non-NULL, a buffer to store the incremented IV. + + Error codes: + NV_ERR_INVALID_ARGUMENT - The value of the operation parameter is illegal. + NV_ERR_INSUFFICIENT_RESOURCES - Incrementing the message counter would result + in an overflow. +*/ +NV_STATUS nvUvmInterfaceCslIncrementIv(UvmCslContext *uvmCslContext, + UvmCslOperation operation, + NvU64 increment, + UvmCslIv *iv); + #endif // _NV_UVM_INTERFACE_H_ diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/kernel-open/common/inc/nv_uvm_types.h nvidia-open-gpu-kernel-modules-535.161.08/kernel-open/common/inc/nv_uvm_types.h --- nvidia-open-gpu-kernel-modules-525.147.05/kernel-open/common/inc/nv_uvm_types.h 2023-10-25 20:33:22.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/kernel-open/common/inc/nv_uvm_types.h 2024-03-05 22:25:35.000000000 +0000 @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 2014-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2014-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -92,6 +92,7 @@ typedef struct uvmGpuSession_tag *uvmGpuSessionHandle; // gpuSessionHandle typedef struct uvmGpuDevice_tag *uvmGpuDeviceHandle; // gpuDeviceHandle typedef struct uvmGpuAddressSpace_tag *uvmGpuAddressSpaceHandle; // gpuAddressSpaceHandle +typedef struct uvmGpuTsg_tag *uvmGpuTsgHandle; // gpuTsgHandle typedef struct uvmGpuChannel_tag *uvmGpuChannelHandle; // gpuChannelHandle typedef struct uvmGpuCopyEngine_tag *uvmGpuCopyEngineHandle; // gpuObjectHandle @@ -110,7 +111,7 @@ NvBool deviceDescendant; // Out: Page size associated with the phys alloc. - NvU32 pageSize; + NvU64 pageSize; // Out: Set to TRUE, if the allocation is contiguous. NvBool contig; @@ -280,6 +281,16 @@ // to kick off the new work. // volatile NvU32 *pWorkSubmissionToken; + + // GPU VAs of both GPFIFO and GPPUT are needed in Confidential Computing + // so a channel can be controlled via another channel (SEC2 or WLC/LCIC) + NvU64 gpFifoGpuVa; + NvU64 gpPutGpuVa; + NvU64 gpGetGpuVa; + // GPU VA of work submission offset is needed in Confidential Computing + // so CE channels can ring doorbell of other channels as required for + // WLC/LCIC work submission + NvU64 workSubmissionOffsetGpuVa; } UvmGpuChannelInfo; typedef enum @@ -292,6 +303,17 @@ UVM_BUFFER_LOCATION_VID = 2, } UVM_BUFFER_LOCATION; +typedef struct UvmGpuTsgAllocParams_tag +{ + // Interpreted as UVM_GPU_CHANNEL_ENGINE_TYPE + NvU32 engineType; + + // Index of the engine the TSG is bound to. + // Ignored if engineType is anything other than + // UVM_GPU_CHANNEL_ENGINE_TYPE_CE. + NvU32 engineIndex; +} UvmGpuTsgAllocParams; + typedef struct UvmGpuChannelAllocParams_tag { NvU32 numGpFifoEntries; @@ -299,13 +321,6 @@ // The next two fields store UVM_BUFFER_LOCATION values NvU32 gpFifoLoc; NvU32 gpPutLoc; - - // Index of the engine the channel will be bound to - // ignored if engineType is anything other than UVM_GPU_CHANNEL_ENGINE_TYPE_CE - NvU32 engineIndex; - - // interpreted as UVM_GPU_CHANNEL_ENGINE_TYPE - NvU32 engineType; } UvmGpuChannelAllocParams; typedef struct UvmGpuPagingChannelAllocParams_tag @@ -376,40 +391,16 @@ typedef struct UvmGpuCaps_tag { - NvU32 sysmemLink; // UVM_LINK_TYPE - NvU32 sysmemLinkRateMBps; // See UvmGpuP2PCapsParams::totalLinkLineRateMBps + // If numaEnabled is NV_TRUE, then the system address of allocated GPU + // memory can be converted to struct pages. See + // UvmGpuInfo::systemMemoryWindowStart. NvBool numaEnabled; NvU32 numaNodeId; - - // On ATS systems, GPUs connected to different CPU sockets can have peer - // traffic. They are called indirect peers. However, indirect peers are - // mapped using sysmem aperture. In order to disambiguate the location of a - // specific memory address, each GPU maps its memory to a different window - // in the System Physical Address (SPA) space. The following fields contain - // the base + size of such window for the GPU. systemMemoryWindowSize - // different than 0 indicates that the window is valid. - // - // - If the window is valid, then we can map GPU memory to the CPU as - // cache-coherent by adding the GPU address to the window start. - // - If numaEnabled is NV_TRUE, then we can also convert the system - // addresses of allocated GPU memory to struct pages. - // - // TODO: Bug 1986868: fix window start computation for SIMICS - NvU64 systemMemoryWindowStart; - NvU64 systemMemoryWindowSize; - - // This tells if the GPU is connected to NVSwitch. On systems with NVSwitch - // all GPUs are connected to it. If connectedToSwitch is NV_TRUE, - // nvswitchMemoryWindowStart tells the base address for the GPU in the - // NVSwitch address space. It is used when creating PTEs of memory mappings - // to NVSwitch peers. - NvBool connectedToSwitch; - NvU64 nvswitchMemoryWindowStart; } UvmGpuCaps; typedef struct UvmGpuAddressSpaceInfo_tag { - NvU32 bigPageSize; + NvU64 bigPageSize; NvBool atsEnabled; @@ -430,12 +421,14 @@ typedef struct UvmGpuAllocInfo_tag { NvU64 gpuPhysOffset; // Returns gpuPhysOffset if contiguous requested - NvU32 pageSize; // default is RM big page size - 64K or 128 K" else use 4K or 2M + NvU64 pageSize; // default is RM big page size - 64K or 128 K" else use 4K or 2M NvU64 alignment; // Virtual alignment NvBool bContiguousPhysAlloc; // Flag to request contiguous physical allocation NvBool bMemGrowsDown; // Causes RM to reserve physical heap from top of FB NvBool bPersistentVidmem; // Causes RM to allocate persistent video memory NvHandle hPhysHandle; // Handle for phys allocation either provided or retrieved + NvBool bUnprotected; // Allocation to be made in unprotected memory whenever + // SEV or GPU CC modes are enabled. Ignored otherwise } UvmGpuAllocInfo; typedef enum @@ -516,6 +509,13 @@ // In: Size of the buffer to store PTEs (in bytes). NvU64 pteBufferSize; + // In: Page size for mapping + // If this field is passed as 0, the page size + // of the allocation is used for mapping. + // nvUvmInterfaceGetExternalAllocPtes must pass + // this field as zero. + NvU64 mappingPageSize; + // In: Pointer to a buffer to store PTEs. // Out: The interface will fill the buffer with PTEs NvU64 *pteBuffer; @@ -566,8 +566,11 @@ // Out: ATS (Address Translation Services) is supported NvBool atsSupported; - // Out: AMD SEV (Secure Encrypted Virtualization) is enabled - NvBool sevEnabled; + // Out: True if HW trusted execution, such as AMD's SEV-SNP or Intel's TDX, + // is enabled in the VM, indicating that Confidential Computing must be + // also enabled in the GPU(s); these two security features are either both + // enabled, or both disabled. + NvBool confComputingEnabled; } UvmPlatformInfo; typedef struct UvmGpuClientInfo_tag @@ -577,6 +580,20 @@ NvHandle hSmcPartRef; } UvmGpuClientInfo; +typedef enum +{ + UVM_GPU_CONF_COMPUTE_MODE_NONE, + UVM_GPU_CONF_COMPUTE_MODE_APM, + UVM_GPU_CONF_COMPUTE_MODE_HCC, + UVM_GPU_CONF_COMPUTE_MODE_COUNT +} UvmGpuConfComputeMode; + +typedef struct UvmGpuConfComputeCaps_tag +{ + // Out: GPU's confidential compute mode + UvmGpuConfComputeMode mode; +} UvmGpuConfComputeCaps; + #define UVM_GPU_NAME_LENGTH 0x40 typedef struct UvmGpuInfo_tag @@ -641,6 +658,31 @@ UvmGpuClientInfo smcUserClientInfo; + // Confidential Compute capabilities of this GPU + UvmGpuConfComputeCaps gpuConfComputeCaps; + + // UVM_LINK_TYPE + NvU32 sysmemLink; + + // See UvmGpuP2PCapsParams::totalLinkLineRateMBps + NvU32 sysmemLinkRateMBps; + + // On coherent systems each GPU maps its memory to a window in the System + // Physical Address (SPA) space. The following fields describe that window. + // + // systemMemoryWindowSize > 0 indicates that the window is valid. meaning + // that GPU memory can be mapped by the CPU as cache-coherent by adding the + // GPU address to the window start. + NvU64 systemMemoryWindowStart; + NvU64 systemMemoryWindowSize; + + // This tells if the GPU is connected to NVSwitch. On systems with NVSwitch + // all GPUs are connected to it. If connectedToSwitch is NV_TRUE, + // nvswitchMemoryWindowStart tells the base address for the GPU in the + // NVSwitch address space. It is used when creating PTEs of memory mappings + // to NVSwitch peers. + NvBool connectedToSwitch; + NvU64 nvswitchMemoryWindowStart; } UvmGpuInfo; typedef struct UvmGpuFbInfo_tag @@ -683,6 +725,9 @@ volatile NvU64 numPages2m; // PMA-wide 2MB pages count across all regions volatile NvU64 numFreePages64k; // PMA-wide free 64KB page count across all regions volatile NvU64 numFreePages2m; // PMA-wide free 2MB pages count across all regions + volatile NvU64 numPages2mProtected; // PMA-wide 2MB pages count in protected memory + volatile NvU64 numFreePages64kProtected; // PMA-wide free 64KB page count in protected memory + volatile NvU64 numFreePages2mProtected; // PMA-wide free 2MB pages count in protected memory } UvmPmaStatistics; /******************************************************************************* @@ -790,24 +835,92 @@ #endif }; +#define UVM_CSL_SIGN_AUTH_TAG_SIZE_BYTES 32 +#define UVM_CSL_CRYPT_AUTH_TAG_SIZE_BYTES 16 + +typedef union UvmFaultMetadataPacket_tag +{ + struct { + NvU8 authTag[UVM_CSL_CRYPT_AUTH_TAG_SIZE_BYTES]; + NvBool valid; + }; + // padding to 32Bytes + NvU8 _padding[32]; +} UvmFaultMetadataPacket; + +// This struct shall not be accessed nor modified directly by UVM as it is +// entirely managed by the RM layer +typedef struct UvmCslContext_tag +{ + struct ccslContext_t *ctx; + void *nvidia_stack; +} UvmCslContext; + typedef struct UvmGpuFaultInfo_tag { struct { - // Register mappings obtained from RM + // Fault buffer GET register mapping. + // + // When Confidential Computing is enabled, GET refers to the shadow + // buffer (see bufferAddress below), and not to the actual HW buffer. + // In this setup, writes of GET (by UVM) do not result on re-evaluation + // of any interrupt condition. volatile NvU32* pFaultBufferGet; + + // Fault buffer PUT register mapping. + // + // When Confidential Computing is enabled, PUT refers to the shadow + // buffer (see bufferAddress below), and not to the actual HW buffer. + // In this setup, writes of PUT (by GSP-RM) do not result on + // re-evaluation of any interrupt condition. volatile NvU32* pFaultBufferPut; - // Note: this variable is deprecated since buffer overflow is not a separate - // register from future chips. + + // Note: this variable is deprecated since buffer overflow is not a + // separate register from future chips. volatile NvU32* pFaultBufferInfo; + + // Register mapping used to clear a replayable fault interrupt in + // Turing+ GPUs. volatile NvU32* pPmcIntr; + + // Register mapping used to enable replayable fault interrupts. volatile NvU32* pPmcIntrEnSet; + + // Register mapping used to disable replayable fault interrupts. volatile NvU32* pPmcIntrEnClear; + + // Register used to enable, or disable, faults on prefetches. volatile NvU32* pPrefetchCtrl; + + // Replayable fault interrupt mask identifier. NvU32 replayableFaultMask; - // fault buffer cpu mapping and size - void* bufferAddress; + + // Fault buffer CPU mapping + void* bufferAddress; + // + // When Confidential Computing is disabled, the mapping points to the + // actual HW fault buffer. + // + // When Confidential Computing is enabled, the mapping points to a + // copy of the HW fault buffer. This "shadow buffer" is maintained + // by GSP-RM. + + // Size, in bytes, of the fault buffer pointed by bufferAddress. NvU32 bufferSize; + // Mapping pointing to the start of the fault buffer metadata containing + // a 16Byte authentication tag and a valid byte. Always NULL when + // Confidential Computing is disabled. + UvmFaultMetadataPacket *bufferMetadata; + + // CSL context used for performing decryption of replayable faults when + // Confidential Computing is enabled. + UvmCslContext cslCtx; + + // Indicates whether UVM owns the replayable fault buffer. + // The value of this field is always NV_TRUE When Confidential Computing + // is disabled. + NvBool bUvmOwnsHwFaultBuffer; } replayable; struct { @@ -826,8 +939,20 @@ // Preallocated stack for functions called from the UVM isr bottom half void *isr_bh_sp; + + // Used only when Hopper Confidential Compute is enabled + // Register mappings obtained from RM + volatile NvU32* pFaultBufferPut; + + // Used only when Hopper Confidential Compute is enabled + // Cached get index of the non-replayable shadow buffer + NvU32 shadowBufferGet; + + // See replayable.bufferMetadata + UvmFaultMetadataPacket *shadowBufferMetadata; } nonReplayable; NvHandle faultBufferHandle; + struct Device *pDevice; } UvmGpuFaultInfo; struct Device; @@ -863,12 +988,6 @@ void* bufferAddress; NvU32 bufferSize; NvHandle accessCntrBufferHandle; - - // The Notification address in the access counter notification msg does not - // contain the correct upper bits 63-47 for GPA-based notifications. RM - // provides us with the correct offset to be added. - // See Bug 1803015 - NvU64 baseDmaSysmemAddr; } UvmGpuAccessCntrInfo; typedef enum @@ -911,6 +1030,7 @@ } UVM_PMA_GPU_MEMORY_TYPE; typedef UvmGpuChannelInfo gpuChannelInfo; +typedef UvmGpuTsgAllocParams gpuTsgAllocParams; typedef UvmGpuChannelAllocParams gpuChannelAllocParams; typedef UvmGpuCaps gpuCaps; typedef UvmGpuCopyEngineCaps gpuCeCaps; @@ -935,4 +1055,16 @@ typedef UvmGpuPagingChannelAllocParams gpuPagingChannelAllocParams; typedef UvmPmaAllocationOptions gpuPmaAllocationOptions; +typedef struct UvmCslIv +{ + NvU8 iv[12]; + NvU8 fresh; +} UvmCslIv; + +typedef enum UvmCslOperation +{ + UVM_CSL_OPERATION_ENCRYPT, + UVM_CSL_OPERATION_DECRYPT +} UvmCslOperation; + #endif // _NV_UVM_TYPES_H_ diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/kernel-open/common/inc/nvkms-kapi.h nvidia-open-gpu-kernel-modules-535.161.08/kernel-open/common/inc/nvkms-kapi.h --- nvidia-open-gpu-kernel-modules-525.147.05/kernel-open/common/inc/nvkms-kapi.h 2023-10-25 20:24:50.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/kernel-open/common/inc/nvkms-kapi.h 2024-03-05 22:14:19.000000000 +0000 @@ -165,8 +165,6 @@ NvU32 physicalIndex; - NvU32 headMask; - NvKmsConnectorSignalFormat signalFormat; NvKmsConnectorType type; @@ -194,6 +192,7 @@ NvU32 numPossibleClones; NvKmsKapiDisplay possibleCloneHandles[NVKMS_KAPI_MAX_CLONE_DISPLAYS]; + NvU32 headMask; }; struct NvKmsKapiSyncpt { @@ -520,14 +519,23 @@ ); /*! - * Revoke modeset permissions previously granted. This currently applies for all - * previous grant requests for this device. + * Revoke permissions previously granted. Only one (dispIndex, head, + * display) is currently supported. + * + * \param [in] device A device returned by allocateDevice(). * - * \param [in] device A device returned by allocateDevice(). + * \param [in] head head of display. + * + * \param [in] display The display to revoke. * * \return NV_TRUE on success, NV_FALSE on failure. */ - NvBool (*revokePermissions)(struct NvKmsKapiDevice *device); + NvBool (*revokePermissions) + ( + struct NvKmsKapiDevice *device, + NvU32 head, + NvKmsKapiDisplay display + ); /*! * Registers for notification, via @@ -1065,6 +1073,21 @@ NvU64 *pPages ); + /*! + * Check if this memory object can be scanned out for display. + * + * \param [in] device A device allocated using allocateDevice(). + * + * \param [in] memory The memory object to check for display support. + * + * \return NV_TRUE if this memory can be displayed, NV_FALSE if not. + */ + NvBool (*isMemoryValidForDisplay) + ( + const struct NvKmsKapiDevice *device, + const struct NvKmsKapiMemory *memory + ); + /* * Import SGT as a memory handle. * diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/kernel-open/common/inc/nvlimits.h nvidia-open-gpu-kernel-modules-535.161.08/kernel-open/common/inc/nvlimits.h --- nvidia-open-gpu-kernel-modules-525.147.05/kernel-open/common/inc/nvlimits.h 2023-10-25 20:33:24.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/kernel-open/common/inc/nvlimits.h 2024-03-05 22:25:38.000000000 +0000 @@ -25,7 +25,7 @@ // // This file was generated with FINN, an NVIDIA coding tool. -// Source file: nvlimits.finn +// Source file: nvlimits.finn // diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/kernel-open/common/inc/nvstatuscodes.h nvidia-open-gpu-kernel-modules-535.161.08/kernel-open/common/inc/nvstatuscodes.h --- nvidia-open-gpu-kernel-modules-525.147.05/kernel-open/common/inc/nvstatuscodes.h 2023-10-25 20:33:24.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/kernel-open/common/inc/nvstatuscodes.h 2024-03-05 22:25:38.000000000 +0000 @@ -149,6 +149,7 @@ NV_STATUS_CODE(NV_ERR_NVLINK_CONFIGURATION_ERROR, 0x00000078, "Nvlink Configuration Error") NV_STATUS_CODE(NV_ERR_RISCV_ERROR, 0x00000079, "Generic RISC-V assert or halt") NV_STATUS_CODE(NV_ERR_FABRIC_MANAGER_NOT_PRESENT, 0x0000007A, "Fabric Manager is not loaded") +NV_STATUS_CODE(NV_ERR_ALREADY_SIGNALLED, 0x0000007B, "Semaphore Surface value already >= requested wait value") // Warnings: NV_STATUS_CODE(NV_WARN_HOT_SWITCH, 0x00010001, "WARNING Hot switch") diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/kernel-open/common/inc/nvtypes.h nvidia-open-gpu-kernel-modules-535.161.08/kernel-open/common/inc/nvtypes.h --- nvidia-open-gpu-kernel-modules-525.147.05/kernel-open/common/inc/nvtypes.h 2023-10-25 20:33:23.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/kernel-open/common/inc/nvtypes.h 2024-03-05 22:25:38.000000000 +0000 @@ -513,6 +513,12 @@ // place to re-locate these from nvos.h which cannot be included by a number // of builds that need them +#if defined(__GNUC__) || defined(__clang__) || defined(__INTEL_COMPILER) + #define NV_ATTRIBUTE_UNUSED __attribute__((__unused__)) +#else + #define NV_ATTRIBUTE_UNUSED +#endif + #if defined(_MSC_VER) #if _MSC_VER >= 1310 @@ -536,8 +542,6 @@ #define NV_FORCERESULTCHECK - #define NV_ATTRIBUTE_UNUSED - #define NV_FORMAT_PRINTF(_f, _a) #else // ! defined(_MSC_VER) @@ -635,12 +639,6 @@ #define NV_FORCERESULTCHECK #endif - #if defined(__GNUC__) || defined(__clang__) || defined(__INTEL_COMPILER) - #define NV_ATTRIBUTE_UNUSED __attribute__((__unused__)) - #else - #define NV_ATTRIBUTE_UNUSED - #endif - /* * Functions decorated with NV_FORMAT_PRINTF(f, a) have a format string at * parameter number 'f' and variadic arguments start at parameter number 'a'. diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/kernel-open/common/inc/os-interface.h nvidia-open-gpu-kernel-modules-535.161.08/kernel-open/common/inc/os-interface.h --- nvidia-open-gpu-kernel-modules-525.147.05/kernel-open/common/inc/os-interface.h 2023-10-25 20:33:21.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/kernel-open/common/inc/os-interface.h 2024-03-05 22:25:34.000000000 +0000 @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 1999-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 1999-2024 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -162,10 +162,9 @@ NV_STATUS NV_API_CALL os_inject_vgx_msi (NvU16, NvU64, NvU32); NvBool NV_API_CALL os_is_grid_supported (void); NvU32 NV_API_CALL os_get_grid_csp_support (void); -void NV_API_CALL os_get_screen_info (NvU64 *, NvU16 *, NvU16 *, NvU16 *, NvU16 *, NvU64, NvU64); void NV_API_CALL os_bug_check (NvU32, const char *); NV_STATUS NV_API_CALL os_lock_user_pages (void *, NvU64, void **, NvU32); -NV_STATUS NV_API_CALL os_lookup_user_io_memory (void *, NvU64, NvU64 **, void**); +NV_STATUS NV_API_CALL os_lookup_user_io_memory (void *, NvU64, NvU64 **); NV_STATUS NV_API_CALL os_unlock_user_pages (NvU64, void *); NV_STATUS NV_API_CALL os_match_mmap_offset (void *, NvU64, NvU64 *); NV_STATUS NV_API_CALL os_get_euid (NvU32 *); @@ -181,7 +180,6 @@ NvU32 NV_API_CALL os_get_page_refcount (NvU64 address); NvU32 NV_API_CALL os_count_tail_pages (NvU64 address); void NV_API_CALL os_free_pages_phys (NvU64, NvU32); -NV_STATUS NV_API_CALL os_call_nv_vmbus (NvU32, void *); NV_STATUS NV_API_CALL os_open_temporary_file (void **); void NV_API_CALL os_close_file (void *); NV_STATUS NV_API_CALL os_write_file (void *, NvU8 *, NvU64, NvU64); @@ -189,7 +187,7 @@ NV_STATUS NV_API_CALL os_open_readonly_file (const char *, void **); NV_STATUS NV_API_CALL os_open_and_read_file (const char *, NvU8 *, NvU64); NvBool NV_API_CALL os_is_nvswitch_present (void); -void NV_API_CALL os_get_random_bytes (NvU8 *, NvU16); +NV_STATUS NV_API_CALL os_get_random_bytes (NvU8 *, NvU16); NV_STATUS NV_API_CALL os_alloc_wait_queue (os_wait_queue **); void NV_API_CALL os_free_wait_queue (os_wait_queue *); void NV_API_CALL os_wait_uninterruptible (os_wait_queue *); @@ -208,12 +206,19 @@ OS_INTF_PCIE_REQ_ATOMICS_128BIT }; NV_STATUS NV_API_CALL os_enable_pci_req_atomics (void *, enum os_pci_req_atomics_type); +NV_STATUS NV_API_CALL os_get_numa_node_memory_usage (NvS32, NvU64 *, NvU64 *); +NV_STATUS NV_API_CALL os_numa_add_gpu_memory (void *, NvU64, NvU64, NvU32 *); +NV_STATUS NV_API_CALL os_numa_remove_gpu_memory (void *, NvU64, NvU64, NvU32); +NV_STATUS NV_API_CALL os_offline_page_at_address(NvU64 address); +void* NV_API_CALL os_get_pid_info(void); +void NV_API_CALL os_put_pid_info(void *pid_info); +NV_STATUS NV_API_CALL os_find_ns_pid(void *pid_info, NvU32 *ns_pid); extern NvU32 os_page_size; extern NvU64 os_page_mask; extern NvU8 os_page_shift; -extern NvU32 os_sev_status; -extern NvBool os_sev_enabled; +extern NvBool os_cc_enabled; +extern NvBool os_cc_tdx_enabled; extern NvBool os_dma_buf_enabled; /* diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/kernel-open/common/inc/rm-gpu-ops.h nvidia-open-gpu-kernel-modules-535.161.08/kernel-open/common/inc/rm-gpu-ops.h --- nvidia-open-gpu-kernel-modules-525.147.05/kernel-open/common/inc/rm-gpu-ops.h 2023-10-25 20:33:20.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/kernel-open/common/inc/rm-gpu-ops.h 2024-03-05 22:25:33.000000000 +0000 @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 1999-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 1999-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -56,7 +56,9 @@ NV_STATUS NV_API_CALL rm_gpu_ops_memory_cpu_map(nvidia_stack_t *, nvgpuAddressSpaceHandle_t, NvU64, NvLength, void **, NvU32); NV_STATUS NV_API_CALL rm_gpu_ops_memory_cpu_ummap(nvidia_stack_t *, nvgpuAddressSpaceHandle_t, void*); -NV_STATUS NV_API_CALL rm_gpu_ops_channel_allocate(nvidia_stack_t *, nvgpuAddressSpaceHandle_t, const nvgpuChannelAllocParams_t *, nvgpuChannelHandle_t *, nvgpuChannelInfo_t); +NV_STATUS NV_API_CALL rm_gpu_ops_tsg_allocate(nvidia_stack_t *, nvgpuAddressSpaceHandle_t, const nvgpuTsgAllocParams_t *, nvgpuTsgHandle_t *); +NV_STATUS NV_API_CALL rm_gpu_ops_tsg_destroy(nvidia_stack_t *, nvgpuTsgHandle_t); +NV_STATUS NV_API_CALL rm_gpu_ops_channel_allocate(nvidia_stack_t *, const nvgpuTsgHandle_t, const nvgpuChannelAllocParams_t *, nvgpuChannelHandle_t *, nvgpuChannelInfo_t); NV_STATUS NV_API_CALL rm_gpu_ops_channel_destroy(nvidia_stack_t *, nvgpuChannelHandle_t); NV_STATUS NV_API_CALL rm_gpu_ops_memory_free(nvidia_stack_t *, nvgpuAddressSpaceHandle_t, NvU64); NV_STATUS NV_API_CALL rm_gpu_ops_query_caps(nvidia_stack_t *, nvgpuDeviceHandle_t, nvgpuCaps_t); @@ -74,8 +76,9 @@ NV_STATUS NV_API_CALL rm_gpu_ops_init_fault_info(nvidia_stack_t *, nvgpuDeviceHandle_t, nvgpuFaultInfo_t); NV_STATUS NV_API_CALL rm_gpu_ops_destroy_fault_info(nvidia_stack_t *, nvgpuDeviceHandle_t, nvgpuFaultInfo_t); NV_STATUS NV_API_CALL rm_gpu_ops_get_non_replayable_faults(nvidia_stack_t *, nvgpuFaultInfo_t, void *, NvU32 *); +NV_STATUS NV_API_CALL rm_gpu_ops_flush_replayable_fault_buffer(nvidia_stack_t *, nvgpuDeviceHandle_t); NV_STATUS NV_API_CALL rm_gpu_ops_has_pending_non_replayable_faults(nvidia_stack_t *, nvgpuFaultInfo_t, NvBool *); -NV_STATUS NV_API_CALL rm_gpu_ops_init_access_cntr_info(nvidia_stack_t *, nvgpuDeviceHandle_t, nvgpuAccessCntrInfo_t); +NV_STATUS NV_API_CALL rm_gpu_ops_init_access_cntr_info(nvidia_stack_t *, nvgpuDeviceHandle_t, nvgpuAccessCntrInfo_t, NvU32); NV_STATUS NV_API_CALL rm_gpu_ops_destroy_access_cntr_info(nvidia_stack_t *, nvgpuDeviceHandle_t, nvgpuAccessCntrInfo_t); NV_STATUS NV_API_CALL rm_gpu_ops_own_access_cntr_intr(nvidia_stack_t *, nvgpuSessionHandle_t, nvgpuAccessCntrInfo_t, NvBool); NV_STATUS NV_API_CALL rm_gpu_ops_enable_access_cntr(nvidia_stack_t *, nvgpuDeviceHandle_t, nvgpuAccessCntrInfo_t, nvgpuAccessCntrConfig_t); @@ -98,4 +101,14 @@ void NV_API_CALL rm_gpu_ops_paging_channels_unmap(nvidia_stack_t *, nvgpuAddressSpaceHandle_t, NvU64, nvgpuDeviceHandle_t); NV_STATUS NV_API_CALL rm_gpu_ops_paging_channel_push_stream(nvidia_stack_t *, nvgpuPagingChannelHandle_t, char *, NvU32); +NV_STATUS NV_API_CALL rm_gpu_ops_ccsl_context_init(nvidia_stack_t *, struct ccslContext_t **, nvgpuChannelHandle_t); +NV_STATUS NV_API_CALL rm_gpu_ops_ccsl_context_clear(nvidia_stack_t *, struct ccslContext_t *); +NV_STATUS NV_API_CALL rm_gpu_ops_ccsl_rotate_iv(nvidia_stack_t *, struct ccslContext_t *, NvU8); +NV_STATUS NV_API_CALL rm_gpu_ops_ccsl_encrypt(nvidia_stack_t *, struct ccslContext_t *, NvU32, NvU8 const *, NvU8 *, NvU8 *); +NV_STATUS NV_API_CALL rm_gpu_ops_ccsl_encrypt_with_iv(nvidia_stack_t *, struct ccslContext_t *, NvU32, NvU8 const *, NvU8*, NvU8 *, NvU8 *); +NV_STATUS NV_API_CALL rm_gpu_ops_ccsl_decrypt(nvidia_stack_t *, struct ccslContext_t *, NvU32, NvU8 const *, NvU8 const *, NvU8 *, NvU8 const *, NvU32, NvU8 const *); +NV_STATUS NV_API_CALL rm_gpu_ops_ccsl_sign(nvidia_stack_t *, struct ccslContext_t *, NvU32, NvU8 const *, NvU8 *); +NV_STATUS NV_API_CALL rm_gpu_ops_ccsl_query_message_pool(nvidia_stack_t *, struct ccslContext_t *, NvU8, NvU64 *); +NV_STATUS NV_API_CALL rm_gpu_ops_ccsl_increment_iv(nvidia_stack_t *, struct ccslContext_t *, NvU8, NvU64, NvU8 *); + #endif diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/kernel-open/conftest.sh nvidia-open-gpu-kernel-modules-535.161.08/kernel-open/conftest.sh --- nvidia-open-gpu-kernel-modules-525.147.05/kernel-open/conftest.sh 2023-10-25 20:15:02.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/kernel-open/conftest.sh 2024-02-22 04:52:54.000000000 +0000 @@ -8,19 +8,11 @@ CC="$1" ARCH=$2 -ISYSTEM=`$CC -print-file-name=include 2> /dev/null` SOURCES=$3 HEADERS=$SOURCES/include OUTPUT=$4 XEN_PRESENT=1 PREEMPT_RT_PRESENT=0 -KERNEL_ARCH="$ARCH" - -if [ "$ARCH" = "i386" -o "$ARCH" = "x86_64" ]; then - if [ -d "$SOURCES/arch/x86" ]; then - KERNEL_ARCH="x86" - fi -fi # VGX_BUILD parameter defined only for VGX builds (vGPU Host driver) # VGX_KVM_BUILD parameter defined only vGPU builds on KVM hypervisor @@ -69,16 +61,10 @@ # NV_LINUX_FENCE_H_PRESENT, and that is either defined or undefined, in the # output (which goes to stdout, just like the rest of this file). - # -MG or -MD can interfere with the use of -M and -M -MG for testing file - # existence; filter out any occurrences from CFLAGS. CFLAGS is intentionally - # wrapped with whitespace in the input to sed(1) so the regex can match zero - # or more occurrences of "-MD" or "-MG", surrounded by whitespace to avoid - # accidental matches with tokens that happen to contain either of those - # strings, without special handling of the beginning or the end of the line. - TEST_CFLAGS=`echo "-E -M $CFLAGS " | sed -e 's/\( -M[DG]\)* / /g'` + TEST_CFLAGS="-E -M $CFLAGS" file="$1" - file_define=NV_`echo $file | tr '/.' '_' | tr '-' '_' | tr 'a-z' 'A-Z'`_PRESENT + file_define=NV_`echo $file | tr '/.\-a-z' '___A-Z'`_PRESENT CODE="#include <$file>" @@ -99,6 +85,7 @@ } build_cflags() { + ISYSTEM=`$CC -print-file-name=include 2> /dev/null` BASE_CFLAGS="-O2 -D__KERNEL__ \ -DKBUILD_BASENAME=\"#conftest$$\" -DKBUILD_MODNAME=\"#conftest$$\" \ -nostdinc -isystem $ISYSTEM \ @@ -125,6 +112,14 @@ MACH_CFLAGS="-I$HEADERS/asm/mach-xen" fi + KERNEL_ARCH="$ARCH" + + if [ "$ARCH" = "i386" -o "$ARCH" = "x86_64" ]; then + if [ -d "$SOURCES/arch/x86" ]; then + KERNEL_ARCH="x86" + fi + fi + SOURCE_HEADERS="$HEADERS" SOURCE_ARCH_HEADERS="$SOURCES/arch/$KERNEL_ARCH/include" OUTPUT_HEADERS="$OUTPUT/include" @@ -321,7 +316,7 @@ SYMBOL="$1" TAB=' ' - if grep -e "${TAB}${SYMBOL}${TAB}.*${TAB}EXPORT_SYMBOL.*\$" \ + if grep -e "${TAB}${SYMBOL}${TAB}.*${TAB}EXPORT_SYMBOL\(_GPL\)\?\s*\$" \ "$OUTPUT/Module.symvers" >/dev/null 2>&1; then echo "#define NV_IS_EXPORT_SYMBOL_PRESENT_$SYMBOL 1" | append_conftest "symbols" @@ -342,7 +337,7 @@ SYMBOL="$1" TAB=' ' - if grep -e "${TAB}${SYMBOL}${TAB}.*${TAB}EXPORT_\(UNUSED_\)*SYMBOL_GPL\$" \ + if grep -e "${TAB}${SYMBOL}${TAB}.*${TAB}EXPORT_\(UNUSED_\)*SYMBOL_GPL\s*\$" \ "$OUTPUT/Module.symvers" >/dev/null 2>&1; then echo "#define NV_IS_EXPORT_SYMBOL_GPL_$SYMBOL 1" | append_conftest "symbols" @@ -712,6 +707,50 @@ compile_check_conftest "$CODE" "NV_IOREMAP_WC_PRESENT" "" "functions" ;; + ioremap_driver_hardened) + # + # Determine if the ioremap_driver_hardened() function is present. + # It does not exist on all architectures. + # TODO: Update the commit ID once the API is upstreamed. + # + CODE=" + #include + void conftest_ioremap_driver_hardened(void) { + ioremap_driver_hardened(); + }" + + compile_check_conftest "$CODE" "NV_IOREMAP_DRIVER_HARDENED_PRESENT" "" "functions" + ;; + + ioremap_driver_hardened_wc) + # + # Determine if the ioremap_driver_hardened_wc() function is present. + # It does not exist on all architectures. + # TODO: Update the commit ID once the API is upstreamed. + # + CODE=" + #include + void conftest_ioremap_driver_hardened_wc(void) { + ioremap_driver_hardened_wc(); + }" + + compile_check_conftest "$CODE" "NV_IOREMAP_DRIVER_HARDENED_WC_PRESENT" "" "functions" + ;; + + ioremap_cache_shared) + # + # Determine if the ioremap_cache_shared() function is present. + # It does not exist on all architectures. + # TODO: Update the commit ID once the API is upstreamed. + # + CODE=" + #include + void conftest_ioremap_cache_shared(void) { + ioremap_cache_shared(); + }" + + compile_check_conftest "$CODE" "NV_IOREMAP_CACHE_SHARED_PRESENT" "" "functions" + ;; dom0_kernel_present) # Add config parameter if running on DOM0. if [ -n "$VGX_BUILD" ]; then @@ -776,24 +815,6 @@ compile_check_conftest "$CODE" "NV_VFIO_INFO_ADD_CAPABILITY_HAS_CAP_TYPE_ID_ARGS" "" "types" ;; - vmbus_channel_has_ringbuffer_page) - # - # Check if ringbuffer_page field exist in vmbus_channel structure - # - # Changed in commit 52a42c2a90226dc61c99bbd0cb096deeb52c334b - # ("vmbus: keep pointer to ring buffer page") in v5.0 (2018-09-14) - # - - CODE=" - #include - - int conftest_vmbus_channel_has_ringbuffer_page(void) { - return offsetof(struct vmbus_channel, ringbuffer_page); - }" - - compile_check_conftest "$CODE" "NV_VMBUS_CHANNEL_HAS_RING_BUFFER_PAGE" "" "types" - ;; - nvidia_grid_build) if [ -n "$GRID_BUILD" ]; then echo "#define NV_GRID_BUILD" | append_conftest "generic" @@ -954,6 +975,37 @@ compile_check_conftest "$CODE" "NV_VFIO_MIGRATION_OPS_PRESENT" "" "types" ;; + vfio_precopy_info) + # + # Determine if vfio_precopy_info struct is present or not + # + # Added by commit 4db52602a6074 ("vfio: Extend the device migration + # protocol with PRE_COPY" in v6.2 + # + CODE=" + #include + struct vfio_precopy_info precopy_info; + " + + compile_check_conftest "$CODE" "NV_VFIO_PRECOPY_INFO_PRESENT" "" "types" + ;; + + vfio_log_ops) + # + # Determine if vfio_log_ops struct is present or not + # + # Added by commit 80c4b92a2dc48 ("vfio: Introduce the DMA + # logging feature support") in v6.1 + # + CODE=" + #include + #include + struct vfio_log_ops log_ops; + " + + compile_check_conftest "$CODE" "NV_VFIO_LOG_OPS_PRESENT" "" "types" + ;; + vfio_migration_ops_has_migration_get_data_size) # # Determine if vfio_migration_ops struct has .migration_get_data_size field. @@ -1139,6 +1191,23 @@ compile_check_conftest "$CODE" "NV_VFIO_DEVICE_OPS_HAS_DMA_UNMAP" "" "types" ;; + vfio_device_ops_has_bind_iommufd) + # + # Determine if 'vfio_device_ops' struct has 'bind_iommufd' field. + # + # Added by commit a4d1f91db5021 ("vfio-iommufd: Support iommufd + # for physical VFIO devices") in v6.2 + # + CODE=" + #include + #include + int conftest_vfio_device_ops_has_bind_iommufd(void) { + return offsetof(struct vfio_device_ops, bind_iommufd); + }" + + compile_check_conftest "$CODE" "NV_VFIO_DEVICE_OPS_HAS_BIND_IOMMUFD" "" "types" + ;; + pci_irq_vector_helpers) # # Determine if pci_alloc_irq_vectors(), pci_free_irq_vectors() @@ -1231,6 +1300,28 @@ compile_check_conftest "$CODE" "NV_VFIO_PCI_CORE_PRESENT" "" "generic" ;; + mdev_available) + # Determine if MDEV is available + # + # Added by commit 7b96953bc640 ("vfio: Mediated device Core driver") + # in v4.10 + # + CODE=" + #if defined(NV_LINUX_MDEV_H_PRESENT) + #include + #include + #endif + + #if !defined(CONFIG_VFIO_MDEV) && !defined(CONFIG_VFIO_MDEV_MODULE) + #error MDEV not enabled + #endif + void conftest_mdev_available(void) { + struct mdev_device *mdev; + }" + + compile_check_conftest "$CODE" "NV_MDEV_PRESENT" "" "generic" + ;; + vfio_alloc_device) # # Determine if vfio_alloc_device() function is present or not. @@ -1247,7 +1338,6 @@ compile_check_conftest "$CODE" "NV_VFIO_ALLOC_DEVICE_PRESENT" "" "functions" ;; - vfio_register_emulated_iommu_dev) # # Determine if vfio_register_emulated_iommu_dev() function is present or not. @@ -2140,6 +2230,84 @@ compile_check_conftest "$CODE" "NV_DRM_REINIT_PRIMARY_MODE_GROUP_PRESENT" "" "functions" ;; + drm_helper_crtc_enable_color_mgmt) + # + # Determine if the function drm_helper_crtc_enable_color_mgmt() is + # present. + # + # Added by commit 5488dc16fde7 ("drm: introduce pipe color + # correction properties") in v4.6 (2016-03-08). + # + # Removed by commit f8ed34ac7b45 ("drm: drm_helper_crtc_enable_color_mgmt() + # => drm_crtc_enable_color_mgmt()") in v4.8-rc1 (2016-06-07). + # + CODE=" + #include + void conftest_drm_helper_crtc_enable_color_mgmt(void) { + drm_helper_crtc_enable_color_mgmt(); + }" + + compile_check_conftest "$CODE" "NV_DRM_HELPER_CRTC_ENABLE_COLOR_MGMT_PRESENT" "" "functions" + + ;; + + drm_crtc_enable_color_mgmt) + # + # Determine if the function drm_crtc_enable_color_mgmt() is + # present. + # + # Added by commit f8ed34ac7b45 ("drm: drm_helper_crtc_enable_color_mgmt() + # => drm_crtc_enable_color_mgmt()") in v4.8-rc1 (2016-06-07), replacing + # drm_helper_crtc_enable_color_mgmt(). + # + # Moved to drm_color_mgmt.[ch] by commit f1e2f66ce2d9 ("drm: Extract + # drm_color_mgmt.[hc]") in v4.9-rc1 (2016-09-22) + # + CODE=" + #if defined(NV_DRM_DRM_CRTC_H_PRESENT) + #include + #endif + #if defined(NV_DRM_DRM_COLOR_MGMT_H_PRESENT) + #include + #endif + void conftest_drm_crtc_enable_color_mgmt(void) { + drm_crtc_enable_color_mgmt(); + }" + + compile_check_conftest "$CODE" "NV_DRM_CRTC_ENABLE_COLOR_MGMT_PRESENT" "" "functions" + ;; + + drm_atomic_helper_legacy_gamma_set) + # + # Determine if the function drm_atomic_helper_legacy_gamma_set() is + # present. + # + # Added by commit 5488dc16fde7 ("drm: introduce pipe color + # correction properties") in v4.6 (2016-03-08) + # + # Accidentally moved to drm_atomic_state_helper.[ch] by commit + # 9ef8a9dc4b21 ("drm: Extract drm_atomic_state_helper.[ch]") + # and moved back to drm_atomic_helper.[ch] by commit 1d8224e790c7 + # ("drm: Fix up drm_atomic_state_helper.[hc] extraction") in + # v5.0-rc1 + # + # Removed by commit 6ca2ab8086af ("drm: automatic legacy gamma + # support") in v5.12 (2020-12-15) + # + CODE=" + #if defined(NV_DRM_DRM_ATOMIC_HELPER_H_PRESENT) + #include + #endif + #if defined(NV_DRM_DRM_ATOMIC_STATE_HELPER_H_PRESENT) + #include + #endif + void conftest_drm_atomic_helper_legacy_gamma_set(void) { + drm_atomic_helper_legacy_gamma_set(); + }" + + compile_check_conftest "$CODE" "NV_DRM_ATOMIC_HELPER_LEGACY_GAMMA_SET_PRESENT" "" "functions" + ;; + wait_on_bit_lock_argument_count) # # Determine how many arguments wait_on_bit_lock takes. @@ -2926,6 +3094,24 @@ fi ;; + enable_apicv) + # + # Determine if enable_apicv boolean is exported by kernel. + # + # Added by commit fdf513e37a3bd ("KVM: x86: Use common 'enable_apicv' + # variable for both APICv and AVIC") + # + CODE=" + $CONFTEST_PREAMBLE + #include + + bool is_enable_apicv_present() { + return enable_apicv; + }" + + compile_check_conftest "$CODE" "NV_ENABLE_APICV_PRESENT" "" "types" + ;; + pci_driver_has_driver_managed_dma) # # Determine if "struct pci_driver" has .driver_managed_dma member. @@ -3009,6 +3195,63 @@ compile_check_conftest "$CODE" "NV_DRM_MASTER_DROP_HAS_FROM_RELEASE_ARG" "" "types" ;; + drm_master_has_leases) + # + # Determine if drm_master has 'leases', 'lessor', 'lessee_idr' fields. + # Also checks for struct drm_mode_revoke_lease. + # + # Added by commits 2ed077e467ee ("drm: Add drm_object lease infrastructure [v5]") + # and 62884cd386b8 ("drm: Add four ioctls for managing drm mode object leases [v7]") + # in v4.15 (2017-10-24) + # + CODE=" + #if defined(NV_DRM_DRMP_H_PRESENT) + #include + #endif + #if defined(NV_DRM_DRM_AUTH_H_PRESENT) + #include + #endif + #include + + int conftest_drm_master_leases(void) { + return offsetof(struct drm_master, leases); + } + int conftest_drm_master_lessor(void) { + return offsetof(struct drm_master, lessor); + } + int conftest_drm_master_lessee_idr(void) { + return offsetof(struct drm_master, lessee_idr); + } + int conftest_drm_mode_revoke_lease(void) { + return offsetof(struct drm_mode_revoke_lease, lessee_id); + }" + + compile_check_conftest "$CODE" "NV_DRM_MASTER_HAS_LEASES" "" "types" + ;; + + drm_file_get_master) + # + # Determine if function drm_file_get_master() is present. + # + # Added by commit 56f0729a510f ("drm: protect drm_master pointers in drm_lease.c") + # in v5.15 (2021-07-20) + # + + CODE=" + #if defined(NV_DRM_DRMP_H_PRESENT) + #include + #endif + #if defined(NV_DRM_DRM_AUTH_H_PRESENT) + #include + #endif + + void conftest_drm_file_get_master(void) { + drm_file_get_master(); + }" + + compile_check_conftest "$CODE" "NV_DRM_FILE_GET_MASTER_PRESENT" "" "functions" + ;; + drm_connector_lookup) # # Determine if function drm_connector_lookup() is present. @@ -4054,6 +4297,40 @@ compile_check_conftest "$CODE" "NV_TEGRA_BPMP_SEND_RECEIVE" "" "functions" ;; + cmd_uphy_display_port_init) + # + # Determine if CMD_UPHY_DISPLAY_PORT_INIT enum present in bpmp-abi header + # This enum is used only in Tegra down-stream kernel. + # + CODE=" + #include + #include + + int conftest_cmd_uphy_display_port_init(void) { + return CMD_UPHY_DISPLAY_PORT_INIT; + } + " + compile_check_conftest "$CODE" "NV_CMD_UPHY_DISPLAY_PORT_INIT_PRESENT" "" "generic" + + ;; + + cmd_uphy_display_port_off) + # + # Determine if CMD_UPHY_DISPLAY_PORT_OFF enum present in bpmp-abi header + # This enum is used only in Tegra down-stream kernel. + # + CODE=" + #include + #include + + int conftest_cmd_uphy_display_port_off(void) { + return CMD_UPHY_DISPLAY_PORT_OFF; + } + " + compile_check_conftest "$CODE" "NV_CMD_UPHY_DISPLAY_PORT_OFF_PRESENT" "" "generic" + + ;; + drm_alpha_blending_available) # # Determine if the DRM subsystem supports alpha blending @@ -4191,6 +4468,24 @@ compile_check_conftest "$CODE" "NV_MMU_NOTIFIER_OPS_HAS_INVALIDATE_RANGE" "" "types" ;; + mmu_notifier_ops_arch_invalidate_secondary_tlbs) + # + # Determine if the mmu_notifier_ops struct has the + # 'arch_invalidate_secondary_tlbs' member. + # + # struct mmu_notifier_ops.invalidate_range was renamed to + # arch_invalidate_secondary_tlbs by commit 1af5a8109904 + # ("mmu_notifiers: rename invalidate_range notifier") due to be + # added in v6.6 + CODE=" + #include + int conftest_mmu_notifier_ops_arch_invalidate_secondary_tlbs(void) { + return offsetof(struct mmu_notifier_ops, arch_invalidate_secondary_tlbs); + }" + + compile_check_conftest "$CODE" "NV_MMU_NOTIFIER_OPS_HAS_ARCH_INVALIDATE_SECONDARY_TLBS" "" "types" + ;; + drm_format_num_planes) # # Determine if drm_format_num_planes() function is present. @@ -4667,40 +4962,22 @@ compile_check_conftest "$CODE" "NV_PCI_CHANNEL_STATE_PRESENT" "" "types" ;; - pgprot_decrypted) - # - # Determine if the macro 'pgprot_decrypted()' is present. - # - # Added by commit 21729f81ce8a ("x86/mm: Provide general kernel - # support for memory encryption") in v4.14 (2017-07-18) - CODE=" - #include - - void conftest_pgprot_decrypted(void) - if(pgprot_decrypted()) {} - }" - - compile_check_conftest "$CODE" "NV_PGPROT_DECRYPTED_PRESENT" "" "functions" - - ;; - - cc_mkdec) - # - # Determine if cc_mkdec() is present. + cc_platform_has) # - # cc_mkdec() by commit b577f542f93c ("x86/coco: Add API to handle - # encryption mask) in v5.18-rc1 (2022-02-22). + # Determine if 'cc_platform_has()' is present. # + # Added by commit aa5a461171f9 ("x86/sev: Add an x86 version of + # cc_platform_has()") in v5.15.3 (2021-10-04) CODE=" - #if defined(NV_ASM_COCO_H_PRESENT) - #include + #if defined(NV_LINUX_CC_PLATFORM_H_PRESENT) + #include #endif - void conftest_cc_mkdec(void) { - cc_mkdec(); + void conftest_cc_platfrom_has(void) { + cc_platform_has(); }" - compile_check_conftest "$CODE" "NV_CC_MKDEC_PRESENT" "" "functions" + compile_check_conftest "$CODE" "NV_CC_PLATFORM_PRESENT" "" "functions" ;; drm_prime_pages_to_sg_has_drm_device_arg) @@ -4936,10 +5213,16 @@ # Added by commit 7b7b27214bba ("mm/memory_hotplug: introduce # add_memory_driver_managed()") in v5.8-rc1 (2020-06-05) # + # Before commit 3a0aaefe4134 ("mm/memory_hotplug: guard more + # declarations by CONFIG_MEMORY_HOTPLUG") in v5.10, the + # add_memory_driver_managed() was not guarded. + # CODE=" #include void conftest_add_memory_driver_managed() { + #if defined(CONFIG_MEMORY_HOTPLUG) add_memory_driver_managed(); + #endif }" compile_check_conftest "$CODE" "NV_ADD_MEMORY_DRIVER_MANAGED_PRESENT" "" "functions" @@ -4979,6 +5262,21 @@ compile_check_conftest "$CODE" "NV_REMOVE_MEMORY_HAS_NID_ARG" "" "types" ;; + offline_and_remove_memory) + # + # Determine if the offline_and_remove_memory function is present. + # + # Added by commit 08b3acd7a68fc179 ("mm/memory_hotplug: Introduce + # offline_and_remove_memory()") in v5.8-rc1 (2020-06-05) + # + CODE=" + #include + void conftest_offline_and_remove_memory() { + offline_and_remove_memory(); + }" + + compile_check_conftest "$CODE" "NV_OFFLINE_AND_REMOVE_MEMORY_PRESENT" "" "functions" + ;; device_property_read_u64) # @@ -5060,6 +5358,38 @@ fi ;; + of_property_read_variable_u32_array) + # + # Determine if of_property_read_variable_u32_array is present + # + # Added by commit 1df09bcof (" Move OF property and graph API from + # base.c to property.c" + # + # Test if linux/of.h header file inclusion is successful or not, + # depending on that, check for of_property_read_variable_u32_array + # presence + # + echo "$CONFTEST_PREAMBLE + #include + " > conftest$$.c + + $CC $CFLAGS -c conftest$$.c > /dev/null 2>&1 + rm -f conftest$$.c + + if [ -f conftest$$.o ]; then + rm -f conftest$$.o + CODE=" + #include + void conftest_of_property_read_variable_u32_array() { + of_property_read_variable_u32_array(); + }" + + compile_check_conftest "$CODE" "NV_OF_PROPERTY_READ_VARIABLE_U32_ARRAY_PRESENT" "" "functions" + else + echo "#undef NV_OF_PROPERTY_READ_VARIABLE_U32_ARRAY_PRESENT" | append_conftest "functions" + fi + ;; + devm_of_platform_populate) # # Determine if devm_of_platform_populate() function is present @@ -5386,6 +5716,22 @@ compile_check_conftest "$CODE" "NV_MAKE_DEVICE_EXCLUSIVE_RANGE_PRESENT" "" "functions" ;; + migrate_device_range) + # + # Determine if the migrate_device_range() function is present + # + # migrate_device_range() function was added by commit + # e778406b40dbb ("mm/migrate_device.c: add migrate_device_range()") + # in v6.1 (2022-09-28). + CODE=" + #include + int conftest_migrate_device_range(void) { + migrate_device_range(); + }" + + compile_check_conftest "$CODE" "NV_MIGRATE_DEVICE_RANGE_PRESENT" "" "functions" + ;; + ioasid_get) # # Determine if ioasid_get() function is present @@ -5404,6 +5750,27 @@ compile_check_conftest "$CODE" "NV_IOASID_GET_PRESENT" "" "functions" ;; + mm_pasid_drop) + # + # Determine if mm_pasid_drop() function is present + # + # Added by commit 701fac40384f ("iommu/sva: Assign a PASID to mm + # on PASID allocation and free it on mm exit") in v5.18. + # Moved to linux/iommu.h in commit cd3891158a77 ("iommu/sva: Move + # PASID helpers to sva code") in v6.4. + # + CODE=" + #if defined(NV_LINUX_SCHED_MM_H_PRESENT) + #include + #endif + #include + void conftest_mm_pasid_drop(void) { + mm_pasid_drop(); + }" + + compile_check_conftest "$CODE" "NV_MM_PASID_DROP_PRESENT" "" "functions" + ;; + drm_crtc_state_has_no_vblank) # # Determine if the 'drm_crtc_state' structure has 'no_vblank'. @@ -5551,6 +5918,28 @@ compile_check_conftest "$CODE" "NV_MMGET_NOT_ZERO_PRESENT" "" "functions" ;; + mmgrab) + # + # Determine if mmgrab() function is present + # + # mmgrab() function was added by commit + # f1f1007644ffc8051a4c11427d58b1967ae7b75a ("mm: add new + # mmgrab() helper") in v4.11 (2017-02-01). See comment for + # mmget_not_zero for a description of how the headers have + # changed. + CODE=" + #if defined(NV_LINUX_SCHED_MM_H_PRESENT) + #include + #elif defined(NV_LINUX_SCHED_H_PRESENT) + #include + #endif + void conftest_mmgrab(void) { + mmgrab(); + }" + + compile_check_conftest "$CODE" "NV_MMGRAB_PRESENT" "" "functions" + ;; + dma_resv_add_fence) # # Determine if the dma_resv_add_fence() function is present. @@ -5671,6 +6060,112 @@ compile_check_conftest "$CODE" "NV_ACPI_VIDEO_BACKLIGHT_USE_NATIVE" "" "functions" ;; + vm_fault_to_errno) + # + # Determine if the vm_fault_to_errno() function is present. + # + # vm_fault_to_errno() was added by commit 9a291a7c94281 (mm/hugetlb: + # report -EHWPOISON not -EFAULT when FOLL_HWPOISON is specified) in + # v4.12 (2017-06-02). + # + CODE=" + #include + void conftest_vm_fault_to_errno(void) { + vm_fault_to_errno(); + }" + + compile_check_conftest "$CODE" "NV_VM_FAULT_TO_ERRNO_PRESENT" "" "functions" + ;; + + handle_mm_fault_has_mm_arg) + # + # Determine if handle_mm_fault() has mm argument. + # + # mm argument was removed from handle_mm_fault() by commit + # dcddffd41d3f1d3bdcc1dce3f1cd142779b6d4c1 (07/26/2016) ("mm: do not + # pass mm_struct into handle_mm_fault") in v4.8. + # + # To test if handle_mm_fault() has mm argument, define a function + # with the expected signature and then define the corresponding + # function implementation with the expected signature. Successful + # compilation indicates that handle_mm_fault has the mm argument. + # + CODE=" + #include + #include + + typeof(handle_mm_fault) conftest_handle_mm_fault_has_mm_arg; + int conftest_handle_mm_fault_has_mm_arg(struct mm_struct *mm, + struct vm_area_struct *vma, + unsigned long address, + unsigned int flags) { + return 0; + }" + + compile_check_conftest "$CODE" "NV_HANDLE_MM_FAULT_HAS_MM_ARG" "" "types" + ;; + + handle_mm_fault_has_pt_regs_arg) + # + # Determine if handle_mm_fault() has pt_regs argument. + # + # pt_regs argument was added to handle_mm_fault by commit + # bce617edecada007aee8610fbe2c14d10b8de2f6 (08/12/2020) ("mm: do + # page fault accounting in handle_mm_fault") in v5.9. + # + # To test if handle_mm_fault() has pt_regs argument, define a + # function with the expected signature and then define the + # corresponding function implementation with the expected signature. + # Successful compilation indicates that handle_mm_fault has the + # pt_regs argument. + # + CODE=" + #include + #include + + typeof(handle_mm_fault) conftest_handle_mm_fault_has_pt_regs_arg; + vm_fault_t conftest_handle_mm_fault_has_pt_regs_arg(struct vm_area_struct *vma, + unsigned long address, + unsigned int flags, + struct pt_regs *regs) { + return 0; + }" + + compile_check_conftest "$CODE" "NV_HANDLE_MM_FAULT_HAS_PT_REGS_ARG" "" "types" + ;; + + pci_rebar_get_possible_sizes) + # + # Determine if the pci_rebar_get_possible_sizes() function is present. + # + # Added by commit 8fbdbb66f8c10 ("PCI: Add resizable BAR infrastructure + # ") in v5.12 + # + CODE=" + #include + void conftest_pci_rebar_get_possible_sizes(void) { + pci_rebar_get_possible_sizes(); + }" + + compile_check_conftest "$CODE" "NV_PCI_REBAR_GET_POSSIBLE_SIZES_PRESENT" "" "functions" + ;; + + wait_for_random_bytes) + # + # Determine if the wait_for_random_bytes() function is present. + # + # Added by commit e297a783e4156 ("random: add wait_for_random_bytes + # API") in v4.13 + # + CODE=" + #include + int conftest_wait_for_random_bytes(void) { + return wait_for_random_bytes(0); + }" + + compile_check_conftest "$CODE" "NV_WAIT_FOR_RANDOM_BYTES_PRESENT" "" "functions" + ;; + drm_connector_has_override_edid) # # Determine if 'struct drm_connector' has an 'override_edid' member. @@ -5693,6 +6188,27 @@ compile_check_conftest "$CODE" "NV_DRM_CONNECTOR_HAS_OVERRIDE_EDID" "" "types" ;; + iommu_sva_bind_device_has_drvdata_arg) + # + # Check if iommu_sva_bind_device() has drvdata parameter. + # + # drvdata argument was removed by commit + # 942fd5435dccb273f90176b046ae6bbba60cfbd8 ("iommu: Remove + # SVM_FLAG_SUPERVISOR_MODE support") in v6.2 (2022-10-31) + # + CODE=" + #include + #include + #include + void conftest_iommu_sva_bind_device_has_drvdata_arg(struct device *dev, + struct mm_struct *mm, + void *drvdata) { + (void) iommu_sva_bind_device(dev, mm, drvdata); + }" + + compile_check_conftest "$CODE" "NV_IOMMU_SVA_BIND_DEVICE_HAS_DRVDATA_ARG" "" "types" + ;; + vm_area_struct_has_const_vm_flags) # # Determine if the 'vm_area_struct' structure has @@ -5736,6 +6252,171 @@ compile_check_conftest "$CODE" "NV_DRM_DRIVER_HAS_DUMB_DESTROY" "" "types" ;; + memory_failure_has_trapno_arg) + # + # Check if memory_failure() has trapno parameter. + # + # trapno argument was removed by commit + # 83b57531c58f4173d1c0d0b2c0bc88c853c32ea5 ("mm/memory_failure: + # Remove unused trapno from memory_failure") in v4.15.0 (2017-7-9) + # + CODE=" + #include + void conftest_memory_failure_has_trapno_arg(unsigned long pfn, + int trapno, + int flags) { + (void) memory_failure(pfn, trapno, flags); + }" + + compile_check_conftest "$CODE" "NV_MEMORY_FAILURE_HAS_TRAPNO_ARG" "" "types" + ;; + + memory_failure_mf_sw_simulated_defined) + # + # Check if memory_failure() flag MF_SW_SIMULATED is defined. + # + # MF_SW_SIMULATED was added by commit + # 67f22ba7750f940bcd7e1b12720896c505c2d63f ("mm/hwpoison: + # fix unpoison_memory()") in v5.19.0-rc2 (2022-6-16) + # + CODE=" + #include + int conftest_memory_failure_mf_sw_simulated_defined(void) { + return MF_SW_SIMULATED; + }" + + compile_check_conftest "$CODE" "NV_MEMORY_FAILURE_MF_SW_SIMULATED_DEFINED" "" "types" + ;; + + crypto_tfm_ctx_aligned) + # Determine if 'crypto_tfm_ctx_aligned' is defined. + # + # Removed by commit 25c74a39e0f6 ("crypto: hmac - remove unnecessary + # alignment logic") in v6.7. + # + CODE=" + #include + void conftest_crypto_tfm_ctx_aligned(void) { + (void)crypto_tfm_ctx_aligned(); + }" + + compile_check_conftest "$CODE" "NV_CRYPTO_TFM_CTX_ALIGNED_PRESENT" "" "functions" + ;; + + crypto) + # + # Determine if we support various crypto functions. + # This test is not complete and may return false positive. + # + CODE=" + #include + #include + #include + #include + #include + #include + #include + #include + #include + #include + #include + void conftest_crypto(void) { + struct shash_desc sd; + struct crypto_shash cs; + (void)crypto_shash_tfm_digest; + }" + + compile_check_conftest "$CODE" "NV_CRYPTO_PRESENT" "" "symbols" + ;; + + mempolicy_has_unified_nodes) + # + # Determine if the 'mempolicy' structure has + # nodes union. + # + # nodes field was added by commit 269fbe72cd ("mm/mempolicy: + # use unified 'nodes' for bind/interleave/prefer policies") in + # v5.14 (2021-06-30). + # + CODE=" + #include + int conftest_mempolicy_has_unified_nodes(void) { + return offsetof(struct mempolicy, nodes); + }" + + compile_check_conftest "$CODE" "NV_MEMPOLICY_HAS_UNIFIED_NODES" "" "types" + ;; + + mempolicy_has_home_node) + # + # Determine if the 'mempolicy' structure has + # home_node field. + # + # home_node field was added by commit c6018b4b254 + # ("mm/mempolicy: add set_mempolicy_home_node syscall") in v5.17 + # (2022-01-14). + # + CODE=" + #include + int conftest_mempolicy_has_home_node(void) { + return offsetof(struct mempolicy, home_node); + }" + + compile_check_conftest "$CODE" "NV_MEMPOLICY_HAS_HOME_NODE" "" "types" + ;; + + mpol_preferred_many_present) + # + # Determine if MPOL_PREFERRED_MANY enum is present or not + # + # Added by commit b27abaccf8e8b ("mm/mempolicy: add + # MPOL_PREFERRED_MANY for multiple preferred nodes") in + # v5.15 + # + CODE=" + #include + int mpol_preferred_many = MPOL_PREFERRED_MANY; + " + + compile_check_conftest "$CODE" "NV_MPOL_PREFERRED_MANY_PRESENT" "" "types" + ;; + + mmu_interval_notifier) + # + # Determine if mmu_interval_notifier struct is present or not + # + # Added by commit 99cb252f5 ("mm/mmu_notifier: add an interval tree + # notifier") in v5.10 (2019-11-12). + # + CODE=" + #include + struct mmu_interval_notifier interval_notifier; + " + + compile_check_conftest "$CODE" "NV_MMU_INTERVAL_NOTIFIER" "" "types" + ;; + + drm_unlocked_ioctl_flag_present) + # Determine if DRM_UNLOCKED IOCTL flag is present. + # + # DRM_UNLOCKED was removed by commit 2798ffcc1d6a ("drm: Remove + # locking for legacy ioctls and DRM_UNLOCKED") in Linux + # next-20231208. + # + # DRM_UNLOCKED definition was moved from drmP.h to drm_ioctl.h by + # commit 2640981f3600 ("drm: document drm_ioctl.[hc]") in v4.12. + CODE=" + #if defined(NV_DRM_DRM_IOCTL_H_PRESENT) + #include + #endif + #if defined(NV_DRM_DRMP_H_PRESENT) + #include + #endif + int flags = DRM_UNLOCKED;" + + compile_check_conftest "$CODE" "NV_DRM_UNLOCKED_IOCTL_FLAG_PRESENT" "" "types" + ;; + # When adding a new conftest entry, please use the correct format for # specifying the relevant upstream Linux kernel commit. # @@ -6004,10 +6685,6 @@ for i in $*; do compile_test $i; done - for file in conftest*.d; do - rm -f $file > /dev/null 2>&1 - done - exit 0 ;; @@ -6041,9 +6718,11 @@ iommu=CONFIG_VFIO_IOMMU_TYPE1 mdev=CONFIG_VFIO_MDEV kvm=CONFIG_KVM_VFIO + vfio_pci_core=CONFIG_VFIO_PCI_CORE VFIO_IOMMU_PRESENT=0 VFIO_MDEV_PRESENT=0 KVM_PRESENT=0 + VFIO_PCI_CORE_PRESENT=0 if [ -n "$VGX_KVM_BUILD" ]; then if (test_configuration_option ${iommu} || test_configuration_option ${iommu}_MODULE); then @@ -6058,32 +6737,37 @@ KVM_PRESENT=1 fi - if [ "$VFIO_IOMMU_PRESENT" != "0" ] && - [ "$VFIO_MDEV_PRESENT" != "0" ] && - [ "$KVM_PRESENT" != "0" ] ; then + if (test_configuration_option ${vfio_pci_core} || test_configuration_option ${vfio_pci_core}_MODULE); then + VFIO_PCI_CORE_PRESENT=1 + fi + + if [ "$VFIO_IOMMU_PRESENT" != "0" ] && [ "$KVM_PRESENT" != "0" ] ; then + # vGPU requires either MDEV or vfio-pci-core framework to be present. + if [ "$VFIO_MDEV_PRESENT" != "0" ] || [ "$VFIO_PCI_CORE_PRESENT" != "0" ]; then exit 0 - else - echo "Below CONFIG options are missing on the kernel for installing"; - echo "NVIDIA vGPU driver on KVM host"; - if [ "$VFIO_IOMMU_PRESENT" = "0" ]; then - echo "CONFIG_VFIO_IOMMU_TYPE1"; fi + fi - if [ "$VFIO_MDEV_PRESENT" = "0" ]; then - echo "CONFIG_VFIO_MDEV"; - fi + echo "Below CONFIG options are missing on the kernel for installing"; + echo "NVIDIA vGPU driver on KVM host"; + if [ "$VFIO_IOMMU_PRESENT" = "0" ]; then + echo "CONFIG_VFIO_IOMMU_TYPE1"; + fi - if [ "$KVM_PRESENT" = "0" ]; then - echo "CONFIG_KVM"; - fi - echo "Please install the kernel with above CONFIG options set, then"; - echo "try installing again"; - echo ""; + if [ "$VFIO_MDEV_PRESENT" = "0" ] && [ "$VFIO_PCI_CORE_PRESENT" = "0" ]; then + echo "either CONFIG_VFIO_MDEV or CONFIG_VFIO_PCI_CORE"; + fi - if [ "$VERBOSE" = "full_output" ]; then - echo "*** Failed vGPU on KVM sanity check. Bailing out! ***"; - echo ""; - fi + if [ "$KVM_PRESENT" = "0" ]; then + echo "CONFIG_KVM"; + fi + echo "Please install the kernel with above CONFIG options set, then"; + echo "try installing again"; + echo ""; + + if [ "$VERBOSE" = "full_output" ]; then + echo "*** Failed vGPU on KVM sanity check. Bailing out! ***"; + echo ""; fi exit 1 else @@ -6143,10 +6827,6 @@ test_header_presence "${7}" - for file in conftest*.d; do - rm -f $file > /dev/null 2>&1 - done - exit $? ;; diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/kernel-open/nvidia/detect-self-hosted.h nvidia-open-gpu-kernel-modules-535.161.08/kernel-open/nvidia/detect-self-hosted.h --- nvidia-open-gpu-kernel-modules-525.147.05/kernel-open/nvidia/detect-self-hosted.h 1970-01-01 00:00:00.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/kernel-open/nvidia/detect-self-hosted.h 2024-03-05 22:25:35.000000000 +0000 @@ -0,0 +1,33 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef __DETECT_SELF_HOSTED_H__ +#define __DETECT_SELF_HOSTED_H__ + +// PCI devIds 0x2340-0x237f are for Self-Hosted Hopper +static inline int pci_devid_is_self_hosted(unsigned short devid) +{ + return devid >= 0x2340 && devid <= 0x237f; +} + +#endif diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/kernel-open/nvidia/export_nvswitch.h nvidia-open-gpu-kernel-modules-535.161.08/kernel-open/nvidia/export_nvswitch.h --- nvidia-open-gpu-kernel-modules-525.147.05/kernel-open/nvidia/export_nvswitch.h 2023-10-25 20:33:25.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/kernel-open/nvidia/export_nvswitch.h 2024-03-05 22:25:40.000000000 +0000 @@ -899,7 +899,6 @@ void nvswitch_os_assert_log ( - int cond, const char *pFormat, ... ); @@ -940,6 +939,12 @@ NvU32 *pBuildNum ); +NvlStatus +nvswitch_os_get_pid +( + NvU32 *pPid +); + void nvswitch_lib_smbpbi_log_sxid ( diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/kernel-open/nvidia/hal/library/cryptlib/cryptlib_aead.h nvidia-open-gpu-kernel-modules-535.161.08/kernel-open/nvidia/hal/library/cryptlib/cryptlib_aead.h --- nvidia-open-gpu-kernel-modules-525.147.05/kernel-open/nvidia/hal/library/cryptlib/cryptlib_aead.h 1970-01-01 00:00:00.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/kernel-open/nvidia/hal/library/cryptlib/cryptlib_aead.h 2024-03-05 22:25:36.000000000 +0000 @@ -0,0 +1,211 @@ +/** + * Copyright Notice: + * Copyright 2021-2022 DMTF. All rights reserved. + * License: BSD 3-Clause License. For full text see link: https://github.com/DMTF/libspdm/blob/main/LICENSE.md + **/ + +#ifndef CRYPTLIB_AEAD_H +#define CRYPTLIB_AEAD_H + +/*===================================================================================== + * Authenticated Encryption with Associated data (AEAD) Cryptography Primitives + *===================================================================================== + */ + +#if LIBSPDM_AEAD_GCM_SUPPORT +/** + * Performs AEAD AES-GCM authenticated encryption on a data buffer and additional authenticated + * data. + * + * iv_size must be 12, otherwise false is returned. + * key_size must be 16 or 32, otherwise false is returned. + * tag_size must be 12, 13, 14, 15, 16, otherwise false is returned. + * + * @param[in] key Pointer to the encryption key. + * @param[in] key_size Size of the encryption key in bytes. + * @param[in] iv Pointer to the IV value. + * @param[in] iv_size Size of the IV value in bytes. + * @param[in] a_data Pointer to the additional authenticated data. + * @param[in] a_data_size Size of the additional authenticated data in bytes. + * @param[in] data_in Pointer to the input data buffer to be encrypted. + * @param[in] data_in_size Size of the input data buffer in bytes. + * @param[out] tag_out Pointer to a buffer that receives the authentication tag output. + * @param[in] tag_size Size of the authentication tag in bytes. + * @param[out] data_out Pointer to a buffer that receives the encryption output. + * @param[out] data_out_size Size of the output data buffer in bytes. + * + * @retval true AEAD AES-GCM authenticated encryption succeeded. + * @retval false AEAD AES-GCM authenticated encryption failed. + **/ +extern bool libspdm_aead_aes_gcm_encrypt(const uint8_t *key, size_t key_size, + const uint8_t *iv, size_t iv_size, + const uint8_t *a_data, size_t a_data_size, + const uint8_t *data_in, size_t data_in_size, + uint8_t *tag_out, size_t tag_size, + uint8_t *data_out, size_t *data_out_size); + +/** + * Performs AEAD AES-GCM authenticated decryption on a data buffer and additional authenticated + * data. + * + * iv_size must be 12, otherwise false is returned. + * key_size must be 16 or 32, otherwise false is returned. + * tag_size must be 12, 13, 14, 15, 16, otherwise false is returned. + * + * If data verification fails, false is returned. + * + * @param[in] key Pointer to the encryption key. + * @param[in] key_size Size of the encryption key in bytes. + * @param[in] iv Pointer to the IV value. + * @param[in] iv_size Size of the IV value in bytes. + * @param[in] a_data Pointer to the additional authenticated data. + * @param[in] a_data_size Size of the additional authenticated data in bytes. + * @param[in] data_in Pointer to the input data buffer to be decrypted. + * @param[in] data_in_size Size of the input data buffer in bytes. + * @param[in] tag Pointer to a buffer that contains the authentication tag. + * @param[in] tag_size Size of the authentication tag in bytes. + * @param[out] data_out Pointer to a buffer that receives the decryption output. + * @param[out] data_out_size Size of the output data buffer in bytes. + * + * @retval true AEAD AES-GCM authenticated decryption succeeded. + * @retval false AEAD AES-GCM authenticated decryption failed. + **/ +extern bool libspdm_aead_aes_gcm_decrypt(const uint8_t *key, size_t key_size, + const uint8_t *iv, size_t iv_size, + const uint8_t *a_data, size_t a_data_size, + const uint8_t *data_in, size_t data_in_size, + const uint8_t *tag, size_t tag_size, + uint8_t *data_out, size_t *data_out_size); +#endif /* LIBSPDM_AEAD_GCM_SUPPORT */ + +#if LIBSPDM_AEAD_CHACHA20_POLY1305_SUPPORT +/** + * Performs AEAD ChaCha20Poly1305 authenticated encryption on a data buffer and additional + * authenticated data. + * + * iv_size must be 12, otherwise false is returned. + * key_size must be 32, otherwise false is returned. + * tag_size must be 16, otherwise false is returned. + * + * @param[in] key Pointer to the encryption key. + * @param[in] key_size Size of the encryption key in bytes. + * @param[in] iv Pointer to the IV value. + * @param[in] iv_size Size of the IV value in bytes. + * @param[in] a_data Pointer to the additional authenticated data. + * @param[in] a_data_size Size of the additional authenticated data in bytes. + * @param[in] data_in Pointer to the input data buffer to be encrypted. + * @param[in] data_in_size Size of the input data buffer in bytes. + * @param[out] tag_out Pointer to a buffer that receives the authentication tag output. + * @param[in] tag_size Size of the authentication tag in bytes. + * @param[out] data_out Pointer to a buffer that receives the encryption output. + * @param[out] data_out_size Size of the output data buffer in bytes. + * + * @retval true AEAD ChaCha20Poly1305 authenticated encryption succeeded. + * @retval false AEAD ChaCha20Poly1305 authenticated encryption failed. + **/ +extern bool libspdm_aead_chacha20_poly1305_encrypt( + const uint8_t *key, size_t key_size, const uint8_t *iv, + size_t iv_size, const uint8_t *a_data, size_t a_data_size, + const uint8_t *data_in, size_t data_in_size, uint8_t *tag_out, + size_t tag_size, uint8_t *data_out, size_t *data_out_size); + +/** + * Performs AEAD ChaCha20Poly1305 authenticated decryption on a data buffer and additional authenticated data (AAD). + * + * iv_size must be 12, otherwise false is returned. + * key_size must be 32, otherwise false is returned. + * tag_size must be 16, otherwise false is returned. + * + * If data verification fails, false is returned. + * + * @param[in] key Pointer to the encryption key. + * @param[in] key_size Size of the encryption key in bytes. + * @param[in] iv Pointer to the IV value. + * @param[in] iv_size Size of the IV value in bytes. + * @param[in] a_data Pointer to the additional authenticated data. + * @param[in] a_data_size Size of the additional authenticated data in bytes. + * @param[in] data_in Pointer to the input data buffer to be decrypted. + * @param[in] data_in_size Size of the input data buffer in bytes. + * @param[in] tag Pointer to a buffer that contains the authentication tag. + * @param[in] tag_size Size of the authentication tag in bytes. + * @param[out] data_out Pointer to a buffer that receives the decryption output. + * @param[out] data_out_size Size of the output data buffer in bytes. + * + * @retval true AEAD ChaCha20Poly1305 authenticated decryption succeeded. + * @retval false AEAD ChaCha20Poly1305 authenticated decryption failed. + * + **/ +extern bool libspdm_aead_chacha20_poly1305_decrypt( + const uint8_t *key, size_t key_size, const uint8_t *iv, + size_t iv_size, const uint8_t *a_data, size_t a_data_size, + const uint8_t *data_in, size_t data_in_size, const uint8_t *tag, + size_t tag_size, uint8_t *data_out, size_t *data_out_size); +#endif /* LIBSPDM_AEAD_CHACHA20_POLY1305_SUPPORT */ + +#if LIBSPDM_AEAD_SM4_SUPPORT +/** + * Performs AEAD SM4-GCM authenticated encryption on a data buffer and additional authenticated + * data. + * + * iv_size must be 12, otherwise false is returned. + * key_size must be 16, otherwise false is returned. + * tag_size must be 16, otherwise false is returned. + * + * @param[in] key Pointer to the encryption key. + * @param[in] key_size Size of the encryption key in bytes. + * @param[in] iv Pointer to the IV value. + * @param[in] iv_size Size of the IV value in bytes. + * @param[in] a_data Pointer to the additional authenticated data. + * @param[in] a_data_size Size of the additional authenticated data in bytes. + * @param[in] data_in Pointer to the input data buffer to be encrypted. + * @param[in] data_in_size Size of the input data buffer in bytes. + * @param[out] tag_out Pointer to a buffer that receives the authentication tag output. + * @param[in] tag_size Size of the authentication tag in bytes. + * @param[out] data_out Pointer to a buffer that receives the encryption output. + * @param[out] data_out_size Size of the output data buffer in bytes. + * + * @retval true AEAD SM4-GCM authenticated encryption succeeded. + * @retval false AEAD SM4-GCM authenticated encryption failed. + **/ +extern bool libspdm_aead_sm4_gcm_encrypt(const uint8_t *key, size_t key_size, + const uint8_t *iv, size_t iv_size, + const uint8_t *a_data, size_t a_data_size, + const uint8_t *data_in, size_t data_in_size, + uint8_t *tag_out, size_t tag_size, + uint8_t *data_out, size_t *data_out_size); + +/** + * Performs AEAD SM4-GCM authenticated decryption on a data buffer and additional authenticated + * data. + * + * iv_size must be 12, otherwise false is returned. + * key_size must be 16, otherwise false is returned. + * tag_size must be 16, otherwise false is returned. + * + * If data verification fails, false is returned. + * + * @param[in] key Pointer to the encryption key. + * @param[in] key_size Size of the encryption key in bytes. + * @param[in] iv Pointer to the IV value. + * @param[in] iv_size Size of the IV value in bytes. + * @param[in] a_data Pointer to the additional authenticated data. + * @param[in] a_data_size Size of the additional authenticated data in bytes. + * @param[in] data_in Pointer to the input data buffer to be decrypted. + * @param[in] data_in_size Size of the input data buffer in bytes. + * @param[in] tag Pointer to a buffer that contains the authentication tag. + * @param[in] tag_size Size of the authentication tag in bytes. + * @param[out] data_out Pointer to a buffer that receives the decryption output. + * @param[out] data_out_size Size of the output data buffer in bytes. + * + * @retval true AEAD SM4-GCM authenticated decryption succeeded. + * @retval false AEAD SM4-GCM authenticated decryption failed. + **/ +extern bool libspdm_aead_sm4_gcm_decrypt(const uint8_t *key, size_t key_size, + const uint8_t *iv, size_t iv_size, + const uint8_t *a_data, size_t a_data_size, + const uint8_t *data_in, size_t data_in_size, + const uint8_t *tag, size_t tag_size, + uint8_t *data_out, size_t *data_out_size); +#endif /* LIBSPDM_AEAD_SM4_SUPPORT */ + +#endif /* CRYPTLIB_AEAD_H */ diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/kernel-open/nvidia/hal/library/cryptlib/cryptlib_cert.h nvidia-open-gpu-kernel-modules-535.161.08/kernel-open/nvidia/hal/library/cryptlib/cryptlib_cert.h --- nvidia-open-gpu-kernel-modules-525.147.05/kernel-open/nvidia/hal/library/cryptlib/cryptlib_cert.h 1970-01-01 00:00:00.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/kernel-open/nvidia/hal/library/cryptlib/cryptlib_cert.h 2024-03-05 22:25:36.000000000 +0000 @@ -0,0 +1,416 @@ +/** + * Copyright Notice: + * Copyright 2021-2022 DMTF. All rights reserved. + * License: BSD 3-Clause License. For full text see link: https://github.com/DMTF/libspdm/blob/main/LICENSE.md + **/ + +#ifndef CRYPTLIB_CERT_H +#define CRYPTLIB_CERT_H + +/** + * Retrieve the tag and length of the tag. + * + * @param ptr The position in the ASN.1 data. + * @param end End of data. + * @param length The variable that will receive the length. + * @param tag The expected tag. + * + * @retval true Get tag successful. + * @retval false Failed to get tag or tag not match. + **/ +extern bool libspdm_asn1_get_tag(uint8_t **ptr, const uint8_t *end, size_t *length, uint32_t tag); + +/** + * Retrieve the subject bytes from one X.509 certificate. + * + * If cert is NULL, then return false. + * If subject_size is NULL, then return false. + * If this interface is not supported, then return false. + * + * @param[in] cert Pointer to the DER-encoded X509 certificate. + * @param[in] cert_size Size of the X509 certificate in bytes. + * @param[out] cert_subject Pointer to the retrieved certificate subject bytes. + * @param[in, out] subject_size The size in bytes of the cert_subject buffer on input, + * and the size of buffer returned cert_subject on output. + * + * @retval true The certificate subject retrieved successfully. + * @retval false Invalid certificate, or the subject_size is too small for the result. + * The subject_size will be updated with the required size. + * @retval false This interface is not supported. + **/ +extern bool libspdm_x509_get_subject_name(const uint8_t *cert, size_t cert_size, + uint8_t *cert_subject, + size_t *subject_size); + +/** + * Retrieve the version from one X.509 certificate. + * + * If cert is NULL, then return false. + * If cert_size is 0, then return false. + * If this interface is not supported, then return false. + * + * @param[in] cert Pointer to the DER-encoded X509 certificate. + * @param[in] cert_size Size of the X509 certificate in bytes. + * @param[out] version Pointer to the retrieved version integer. + * + * @retval true + * @retval false + **/ +extern bool libspdm_x509_get_version(const uint8_t *cert, size_t cert_size, size_t *version); + +/** + * Retrieve the serialNumber from one X.509 certificate. + * + * If cert is NULL, then return false. + * If cert_size is 0, then return false. + * If this interface is not supported, then return false. + * + * @param[in] cert Pointer to the DER-encoded X509 certificate. + * @param[in] cert_size Size of the X509 certificate in bytes. + * @param[out] serial_number Pointer to the retrieved certificate serial_number bytes. + * @param[in, out] serial_number_size The size in bytes of the serial_number buffer on input, + * and the size of buffer returned serial_number on output. + * + * @retval true + * @retval false + **/ +extern bool libspdm_x509_get_serial_number(const uint8_t *cert, size_t cert_size, + uint8_t *serial_number, + size_t *serial_number_size); + +/** + * Retrieve the issuer bytes from one X.509 certificate. + * + * If cert is NULL, then return false. + * If issuer_size is NULL, then return false. + * If this interface is not supported, then return false. + * + * @param[in] cert Pointer to the DER-encoded X509 certificate. + * @param[in] cert_size Size of the X509 certificate in bytes. + * @param[out] cert_issuer Pointer to the retrieved certificate subject bytes. + * @param[in, out] issuer_size The size in bytes of the cert_issuer buffer on input, + * and the size of buffer returned cert_issuer on output. + * + * @retval true The certificate issuer retrieved successfully. + * @retval false Invalid certificate, or the issuer_size is too small for the result. + * The issuer_size will be updated with the required size. + * @retval false This interface is not supported. + **/ +extern bool libspdm_x509_get_issuer_name(const uint8_t *cert, size_t cert_size, + uint8_t *cert_issuer, + size_t *issuer_size); + +/** + * Retrieve Extension data from one X.509 certificate. + * + * @param[in] cert Pointer to the DER-encoded X509 certificate. + * @param[in] cert_size Size of the X509 certificate in bytes. + * @param[in] oid Object identifier buffer + * @param[in] oid_size Object identifier buffer size + * @param[out] extension_data Extension bytes. + * @param[in, out] extension_data_size Extension bytes size. + * + * @retval true + * @retval false + **/ +extern bool libspdm_x509_get_extension_data(const uint8_t *cert, size_t cert_size, + const uint8_t *oid, size_t oid_size, + uint8_t *extension_data, + size_t *extension_data_size); + +/** + * Retrieve the Validity from one X.509 certificate + * + * If cert is NULL, then return false. + * If CertIssuerSize is NULL, then return false. + * If this interface is not supported, then return false. + * + * @param[in] cert Pointer to the DER-encoded X509 certificate. + * @param[in] cert_size Size of the X509 certificate in bytes. + * @param[out] from notBefore Pointer to date_time object. + * @param[in,out] from_size notBefore date_time object size. + * @param[out] to notAfter Pointer to date_time object. + * @param[in,out] to_size notAfter date_time object size. + * + * Note: libspdm_x509_compare_date_time to compare date_time oject + * x509SetDateTime to get a date_time object from a date_time_str + * + * @retval true The certificate Validity retrieved successfully. + * @retval false Invalid certificate, or Validity retrieve failed. + * @retval false This interface is not supported. + **/ +extern bool libspdm_x509_get_validity(const uint8_t *cert, size_t cert_size, + uint8_t *from, size_t *from_size, uint8_t *to, + size_t *to_size); + +/** + * Format a date_time object into DataTime buffer + * + * If date_time_str is NULL, then return false. + * If date_time_size is NULL, then return false. + * If this interface is not supported, then return false. + * + * @param[in] date_time_str date_time string like YYYYMMDDhhmmssZ + * Ref: https://www.w3.org/TR/NOTE-datetime + * Z stand for UTC time + * @param[out] date_time Pointer to a date_time object. + * @param[in,out] date_time_size date_time object buffer size. + * + * @retval true + * @retval false + **/ +extern bool libspdm_x509_set_date_time(const char *date_time_str, void *date_time, + size_t *date_time_size); + +/** + * Compare date_time1 object and date_time2 object. + * + * If date_time1 is NULL, then return -2. + * If date_time2 is NULL, then return -2. + * If date_time1 == date_time2, then return 0 + * If date_time1 > date_time2, then return 1 + * If date_time1 < date_time2, then return -1 + * + * @param[in] date_time1 Pointer to a date_time Ojbect + * @param[in] date_time2 Pointer to a date_time Object + * + * @retval 0 If date_time1 == date_time2 + * @retval 1 If date_time1 > date_time2 + * @retval -1 If date_time1 < date_time2 + **/ +extern int32_t libspdm_x509_compare_date_time(const void *date_time1, const void *date_time2); + +/** + * Retrieve the key usage from one X.509 certificate. + * + * @param[in] cert Pointer to the DER-encoded X509 certificate. + * @param[in] cert_size Size of the X509 certificate in bytes. + * @param[out] usage Key usage (LIBSPDM_CRYPTO_X509_KU_*) + * + * @retval true The certificate key usage retrieved successfully. + * @retval false Invalid certificate, or usage is NULL + * @retval false This interface is not supported. + **/ +extern bool libspdm_x509_get_key_usage(const uint8_t *cert, size_t cert_size, size_t *usage); + +/** + * Retrieve the Extended key usage from one X.509 certificate. + * + * @param[in] cert Pointer to the DER-encoded X509 certificate. + * @param[in] cert_size Size of the X509 certificate in bytes. + * @param[out] usage Key usage bytes. + * @param[in, out] usage_size Key usage buffer sizs in bytes. + * + * @retval true + * @retval false + **/ +extern bool libspdm_x509_get_extended_key_usage(const uint8_t *cert, + size_t cert_size, uint8_t *usage, + size_t *usage_size); + +/** + * Retrieve the basic constraints from one X.509 certificate. + * + * @param[in] cert Pointer to the DER-encoded X509 certificate. + * @param[in] cert_size Size of the X509 certificate in bytes. + * @param[out] basic_constraints Basic constraints bytes. + * @param[in, out] basic_constraints_size Basic constraints buffer sizs in bytes. + * + * @retval true + * @retval false + **/ +extern bool libspdm_x509_get_extended_basic_constraints(const uint8_t *cert, + size_t cert_size, + uint8_t *basic_constraints, + size_t *basic_constraints_size); + +/** + * Verify one X509 certificate was issued by the trusted CA. + * + * If cert is NULL, then return false. + * If ca_cert is NULL, then return false. + * If this interface is not supported, then return false. + * + * @param[in] cert Pointer to the DER-encoded X509 certificate to be verified. + * @param[in] cert_size Size of the X509 certificate in bytes. + * @param[in] ca_cert Pointer to the DER-encoded trusted CA certificate. + * @param[in] ca_cert_size Size of the CA Certificate in bytes. + * + * @retval true The certificate was issued by the trusted CA. + * @retval false Invalid certificate or the certificate was not issued by the given + * trusted CA. + * @retval false This interface is not supported. + * + **/ +extern bool libspdm_x509_verify_cert(const uint8_t *cert, size_t cert_size, + const uint8_t *ca_cert, size_t ca_cert_size); + +/** + * Verify one X509 certificate was issued by the trusted CA. + * + * @param[in] cert_chain One or more ASN.1 DER-encoded X.509 certificates + * where the first certificate is signed by the Root + * Certificate or is the Root Cerificate itself. and + * subsequent cerificate is signed by the preceding + * cerificate. + * @param[in] cert_chain_length Total length of the certificate chain, in bytes. + * + * @param[in] root_cert Trusted Root Certificate buffer. + * + * @param[in] root_cert_length Trusted Root Certificate buffer length. + * + * @retval true All cerificates were issued by the first certificate in X509Certchain. + * @retval false Invalid certificate or the certificate was not issued by the given + * trusted CA. + **/ +extern bool libspdm_x509_verify_cert_chain(const uint8_t *root_cert, size_t root_cert_length, + const uint8_t *cert_chain, + size_t cert_chain_length); + +/** + * Get one X509 certificate from cert_chain. + * + * @param[in] cert_chain One or more ASN.1 DER-encoded X.509 certificates + * where the first certificate is signed by the Root + * Certificate or is the Root Cerificate itself. and + * subsequent cerificate is signed by the preceding + * cerificate. + * @param[in] cert_chain_length Total length of the certificate chain, in bytes. + * + * @param[in] cert_index Index of certificate. If index is -1 indecate the + * last certificate in cert_chain. + * + * @param[out] cert The certificate at the index of cert_chain. + * @param[out] cert_length The length certificate at the index of cert_chain. + * + * @retval true Success. + * @retval false Failed to get certificate from certificate chain. + **/ +extern bool libspdm_x509_get_cert_from_cert_chain(const uint8_t *cert_chain, + size_t cert_chain_length, + const int32_t cert_index, const uint8_t **cert, + size_t *cert_length); + +#if (LIBSPDM_RSA_SSA_SUPPORT) || (LIBSPDM_RSA_PSS_SUPPORT) +/** + * Retrieve the RSA public key from one DER-encoded X509 certificate. + * + * If cert is NULL, then return false. + * If rsa_context is NULL, then return false. + * If this interface is not supported, then return false. + * + * @param[in] cert Pointer to the DER-encoded X509 certificate. + * @param[in] cert_size Size of the X509 certificate in bytes. + * @param[out] rsa_context Pointer to new-generated RSA context which contain the retrieved + * RSA public key component. Use libspdm_rsa_free() function to free the + * resource. + * + * @retval true RSA public key was retrieved successfully. + * @retval false Fail to retrieve RSA public key from X509 certificate. + * @retval false This interface is not supported. + **/ +extern bool libspdm_rsa_get_public_key_from_x509(const uint8_t *cert, size_t cert_size, + void **rsa_context); +#endif /* (LIBSPDM_RSA_SSA_SUPPORT) || (LIBSPDM_RSA_PSS_SUPPORT) */ + +#if LIBSPDM_ECDSA_SUPPORT +/** + * Retrieve the EC public key from one DER-encoded X509 certificate. + * + * @param[in] cert Pointer to the DER-encoded X509 certificate. + * @param[in] cert_size Size of the X509 certificate in bytes. + * @param[out] ec_context Pointer to new-generated EC DSA context which contain the retrieved + * EC public key component. Use libspdm_ec_free() function to free the + * resource. + * + * If cert is NULL, then return false. + * If ec_context is NULL, then return false. + * + * @retval true EC public key was retrieved successfully. + * @retval false Fail to retrieve EC public key from X509 certificate. + * + **/ +extern bool libspdm_ec_get_public_key_from_x509(const uint8_t *cert, size_t cert_size, + void **ec_context); +#endif /* LIBSPDM_ECDSA_SUPPORT */ + +#if (LIBSPDM_EDDSA_ED25519_SUPPORT) || (LIBSPDM_EDDSA_ED448_SUPPORT) +/** + * Retrieve the Ed public key from one DER-encoded X509 certificate. + * + * @param[in] cert Pointer to the DER-encoded X509 certificate. + * @param[in] cert_size Size of the X509 certificate in bytes. + * @param[out] ecd_context Pointer to new-generated Ed DSA context which contain the retrieved + * Ed public key component. Use libspdm_ecd_free() function to free the + * resource. + * + * If cert is NULL, then return false. + * If ecd_context is NULL, then return false. + * + * @retval true Ed public key was retrieved successfully. + * @retval false Fail to retrieve Ed public key from X509 certificate. + * + **/ +extern bool libspdm_ecd_get_public_key_from_x509(const uint8_t *cert, size_t cert_size, + void **ecd_context); +#endif /* (LIBSPDM_EDDSA_ED25519_SUPPORT) || (LIBSPDM_EDDSA_ED448_SUPPORT) */ + +#if LIBSPDM_SM2_DSA_SUPPORT +/** + * Retrieve the sm2 public key from one DER-encoded X509 certificate. + * + * @param[in] cert Pointer to the DER-encoded X509 certificate. + * @param[in] cert_size Size of the X509 certificate in bytes. + * @param[out] sm2_context Pointer to new-generated sm2 context which contain the retrieved + * sm2 public key component. Use sm2_free() function to free the + * resource. + * + * If cert is NULL, then return false. + * If sm2_context is NULL, then return false. + * + * @retval true sm2 public key was retrieved successfully. + * @retval false Fail to retrieve sm2 public key from X509 certificate. + * + **/ +extern bool libspdm_sm2_get_public_key_from_x509(const uint8_t *cert, size_t cert_size, + void **sm2_context); +#endif /* LIBSPDM_SM2_DSA_SUPPORT */ + +#if LIBSPDM_ENABLE_CAPABILITY_GET_CSR_CAP +/** + * Generate a CSR. + * + * @param[in] hash_nid hash algo for sign + * @param[in] asym_nid asym algo for sign + * + * @param[in] requester_info requester info to gen CSR + * @param[in] requester_info_length The len of requester info + * + * @param[in] context Pointer to asymmetric context + * @param[in] subject_name Subject name: should be break with ',' in the middle + * example: "C=AA,CN=BB" + * + * Subject names should contain a comma-separated list of OID types and values: + * The valid OID type name is in: + * {"CN", "commonName", "C", "countryName", "O", "organizationName","L", + * "OU", "organizationalUnitName", "ST", "stateOrProvinceName", "emailAddress", + * "serialNumber", "postalAddress", "postalCode", "dnQualifier", "title", + * "SN","givenName","GN", "initials", "pseudonym", "generationQualifier", "domainComponent", "DC"}. + * Note: The object of C and countryName should be CSR Supported Country Codes + * + * @param[in] csr_len For input, csr_len is the size of store CSR buffer. + * For output, csr_len is CSR len for DER format + * @param[in] csr_pointer For input, csr_pointer is buffer address to store CSR. + * For output, csr_pointer is address for stored CSR. + * The csr_pointer address will be changed. + * + * @retval true Success. + * @retval false Failed to gen CSR. + **/ +extern bool libspdm_gen_x509_csr(size_t hash_nid, size_t asym_nid, + uint8_t *requester_info, size_t requester_info_length, + void *context, char *subject_name, + size_t *csr_len, uint8_t **csr_pointer); +#endif /* LIBSPDM_ENABLE_CAPABILITY_GET_CSR_CAP */ + +#endif /* CRYPTLIB_CERT_H */ diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/kernel-open/nvidia/hal/library/cryptlib/cryptlib_dh.h nvidia-open-gpu-kernel-modules-535.161.08/kernel-open/nvidia/hal/library/cryptlib/cryptlib_dh.h --- nvidia-open-gpu-kernel-modules-525.147.05/kernel-open/nvidia/hal/library/cryptlib/cryptlib_dh.h 1970-01-01 00:00:00.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/kernel-open/nvidia/hal/library/cryptlib/cryptlib_dh.h 2024-03-05 22:25:37.000000000 +0000 @@ -0,0 +1,98 @@ +/** + * Copyright Notice: + * Copyright 2021-2022 DMTF. All rights reserved. + * License: BSD 3-Clause License. For full text see link: https://github.com/DMTF/libspdm/blob/main/LICENSE.md + **/ + +#ifndef CRYPTLIB_DH_H +#define CRYPTLIB_DH_H + +/*===================================================================================== + * Diffie-Hellman Key Exchange Primitives + *===================================================================================== + */ + +#if LIBSPDM_FFDHE_SUPPORT +/** + * Allocates and initializes one Diffie-Hellman context for subsequent use with the NID. + * + * @param nid cipher NID + * + * @return Pointer to the Diffie-Hellman context that has been initialized. + * If the allocations fails, libspdm_dh_new_by_nid() returns NULL. + * If the interface is not supported, libspdm_dh_new_by_nid() returns NULL. + **/ +extern void *libspdm_dh_new_by_nid(size_t nid); + +/** + * Release the specified DH context. + * + * @param[in] dh_context Pointer to the DH context to be released. + **/ +void libspdm_dh_free(void *dh_context); + +/** + * Generates DH public key. + * + * This function generates random secret exponent, and computes the public key, which is + * returned via parameter public_key and public_key_size. DH context is updated accordingly. + * If the public_key buffer is too small to hold the public key, false is returned and + * public_key_size is set to the required buffer size to obtain the public key. + * + * If dh_context is NULL, then return false. + * If public_key_size is NULL, then return false. + * If public_key_size is large enough but public_key is NULL, then return false. + * If this interface is not supported, then return false. + * + * For FFDHE2048, the public_size is 256. + * For FFDHE3072, the public_size is 384. + * For FFDHE4096, the public_size is 512. + * + * @param[in, out] dh_context Pointer to the DH context. + * @param[out] public_key Pointer to the buffer to receive generated public key. + * @param[in, out] public_key_size On input, the size of public_key buffer in bytes. + * On output, the size of data returned in public_key buffer in + * bytes. + * + * @retval true DH public key generation succeeded. + * @retval false DH public key generation failed. + * @retval false public_key_size is not large enough. + * @retval false This interface is not supported. + **/ +extern bool libspdm_dh_generate_key(void *dh_context, uint8_t *public_key, size_t *public_key_size); + +/** + * Computes exchanged common key. + * + * Given peer's public key, this function computes the exchanged common key, based on its own + * context including value of prime modulus and random secret exponent. + * + * If dh_context is NULL, then return false. + * If peer_public_key is NULL, then return false. + * If key_size is NULL, then return false. + * If key is NULL, then return false. + * If key_size is not large enough, then return false. + * If this interface is not supported, then return false. + * + * For FFDHE2048, the peer_public_size and key_size is 256. + * For FFDHE3072, the peer_public_size and key_size is 384. + * For FFDHE4096, the peer_public_size and key_size is 512. + * + * @param[in, out] dh_context Pointer to the DH context. + * @param[in] peer_public_key Pointer to the peer's public key. + * @param[in] peer_public_key_size size of peer's public key in bytes. + * @param[out] key Pointer to the buffer to receive generated key. + * @param[in, out] key_size On input, the size of key buffer in bytes. + * On output, the size of data returned in key buffer in + * bytes. + * + * @retval true DH exchanged key generation succeeded. + * @retval false DH exchanged key generation failed. + * @retval false key_size is not large enough. + * @retval false This interface is not supported. + **/ +extern bool libspdm_dh_compute_key(void *dh_context, const uint8_t *peer_public_key, + size_t peer_public_key_size, uint8_t *key, + size_t *key_size); +#endif /* LIBSPDM_FFDHE_SUPPORT */ +#endif /* CRYPTLIB_DH_H */ diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/kernel-open/nvidia/hal/library/cryptlib/cryptlib_ec.h nvidia-open-gpu-kernel-modules-535.161.08/kernel-open/nvidia/hal/library/cryptlib/cryptlib_ec.h --- nvidia-open-gpu-kernel-modules-525.147.05/kernel-open/nvidia/hal/library/cryptlib/cryptlib_ec.h 1970-01-01 00:00:00.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/kernel-open/nvidia/hal/library/cryptlib/cryptlib_ec.h 2024-03-05 22:25:37.000000000 +0000 @@ -0,0 +1,162 @@ +/** + * Copyright Notice: + * Copyright 2021-2022 DMTF. All rights reserved. + * License: BSD 3-Clause License. For full text see link: https://github.com/DMTF/libspdm/blob/main/LICENSE.md + **/ + +#ifndef CRYPTLIB_EC_H +#define CRYPTLIB_EC_H + +/*===================================================================================== + * Elliptic Curve Primitives + *=====================================================================================*/ + +#if (LIBSPDM_ECDHE_SUPPORT) || (LIBSPDM_ECDSA_SUPPORT) +/** + * Allocates and Initializes one Elliptic Curve context for subsequent use with the NID. + * + * @param nid cipher NID + * + * @return Pointer to the Elliptic Curve context that has been initialized. + * If the allocations fails, libspdm_ec_new_by_nid() returns NULL. + **/ +extern void *libspdm_ec_new_by_nid(size_t nid); + +/** + * Release the specified EC context. + * + * @param[in] ec_context Pointer to the EC context to be released. + **/ +extern void libspdm_ec_free(void *ec_context); +#endif /* (LIBSPDM_ECDHE_SUPPORT) || (LIBSPDM_ECDSA_SUPPORT) */ + +#if LIBSPDM_ECDHE_SUPPORT +/** + * Generates EC key and returns EC public key (X, Y). + * + * This function generates random secret, and computes the public key (X, Y), which is + * returned via parameter public, public_size. + * X is the first half of public with size being public_size / 2, + * Y is the second half of public with size being public_size / 2. + * EC context is updated accordingly. + * If the public buffer is too small to hold the public X, Y, false is returned and + * public_size is set to the required buffer size to obtain the public X, Y. + * + * For P-256, the public_size is 64. first 32-byte is X, second 32-byte is Y. + * For P-384, the public_size is 96. first 48-byte is X, second 48-byte is Y. + * For P-521, the public_size is 132. first 66-byte is X, second 66-byte is Y. + * + * If ec_context is NULL, then return false. + * If public_size is NULL, then return false. + * If public_size is large enough but public is NULL, then return false. + * + * @param[in, out] ec_context Pointer to the EC context. + * @param[out] public Pointer to the buffer to receive generated public X,Y. + * @param[in, out] public_size On input, the size of public buffer in bytes. + * On output, the size of data returned in public buffer in bytes. + * + * @retval true EC public X,Y generation succeeded. + * @retval false EC public X,Y generation failed. + * @retval false public_size is not large enough. + **/ +extern bool libspdm_ec_generate_key(void *ec_context, uint8_t *public_key, size_t *public_key_size); + +/** + * Computes exchanged common key. + * + * Given peer's public key (X, Y), this function computes the exchanged common key, + * based on its own context including value of curve parameter and random secret. + * X is the first half of peer_public with size being peer_public_size / 2, + * Y is the second half of peer_public with size being peer_public_size / 2. + * + * If ec_context is NULL, then return false. + * If peer_public is NULL, then return false. + * If peer_public_size is 0, then return false. + * If key is NULL, then return false. + * If key_size is not large enough, then return false. + * + * For P-256, the peer_public_size is 64. first 32-byte is X, second 32-byte is Y. + * The key_size is 32. + * For P-384, the peer_public_size is 96. first 48-byte is X, second 48-byte is Y. + * The key_size is 48. + * For P-521, the peer_public_size is 132. first 66-byte is X, second 66-byte is Y. + * The key_size is 66. + * + * @param[in, out] ec_context Pointer to the EC context. + * @param[in] peer_public Pointer to the peer's public X,Y. + * @param[in] peer_public_size Size of peer's public X,Y in bytes. + * @param[out] key Pointer to the buffer to receive generated key. + * @param[in, out] key_size On input, the size of key buffer in bytes. + * On output, the size of data returned in key buffer in bytes. + * + * @retval true EC exchanged key generation succeeded. + * @retval false EC exchanged key generation failed. + * @retval false key_size is not large enough. + **/ +extern bool libspdm_ec_compute_key(void *ec_context, const uint8_t *peer_public, + size_t peer_public_size, uint8_t *key, + size_t *key_size); +#endif /* LIBSPDM_ECDHE_SUPPORT */ + +#if LIBSPDM_ECDSA_SUPPORT +/** + * Carries out the EC-DSA signature. + * + * This function carries out the EC-DSA signature. + * If the signature buffer is too small to hold the contents of signature, false + * is returned and sig_size is set to the required buffer size to obtain the signature. + * + * If ec_context is NULL, then return false. + * If message_hash is NULL, then return false. + * If hash_size need match the hash_nid. hash_nid could be SHA256, SHA384, SHA512, SHA3_256, + * SHA3_384, SHA3_512. + * If sig_size is large enough but signature is NULL, then return false. + * + * For P-256, the sig_size is 64. first 32-byte is R, second 32-byte is S. + * For P-384, the sig_size is 96. first 48-byte is R, second 48-byte is S. + * For P-521, the sig_size is 132. first 66-byte is R, second 66-byte is S. + * + * @param[in] ec_context Pointer to EC context for signature generation. + * @param[in] hash_nid hash NID + * @param[in] message_hash Pointer to octet message hash to be signed. + * @param[in] hash_size Size of the message hash in bytes. + * @param[out] signature Pointer to buffer to receive EC-DSA signature. + * @param[in, out] sig_size On input, the size of signature buffer in bytes. + * On output, the size of data returned in signature buffer in bytes. + * + * @retval true signature successfully generated in EC-DSA. + * @retval false signature generation failed. + * @retval false sig_size is too small. + **/ +extern bool libspdm_ecdsa_sign(void *ec_context, size_t hash_nid, + const uint8_t *message_hash, size_t hash_size, + uint8_t *signature, size_t *sig_size); + +/** + * Verifies the EC-DSA signature. + * + * If ec_context is NULL, then return false. + * If message_hash is NULL, then return false. + * If signature is NULL, then return false. + * If hash_size need match the hash_nid. hash_nid could be SHA256, SHA384, SHA512, SHA3_256, + * SHA3_384, SHA3_512. + * + * For P-256, the sig_size is 64. first 32-byte is R, second 32-byte is S. + * For P-384, the sig_size is 96. first 48-byte is R, second 48-byte is S. + * For P-521, the sig_size is 132. first 66-byte is R, second 66-byte is S. + * + * @param[in] ec_context Pointer to EC context for signature verification. + * @param[in] hash_nid hash NID + * @param[in] message_hash Pointer to octet message hash to be checked. + * @param[in] hash_size Size of the message hash in bytes. + * @param[in] signature Pointer to EC-DSA signature to be verified. + * @param[in] sig_size Size of signature in bytes. + * + * @retval true Valid signature encoded in EC-DSA. + * @retval false Invalid signature or invalid EC context. + **/ +extern bool libspdm_ecdsa_verify(void *ec_context, size_t hash_nid, + const uint8_t *message_hash, size_t hash_size, + const uint8_t *signature, size_t sig_size); +#endif /* LIBSPDM_ECDSA_SUPPORT */ +#endif /* CRYPTLIB_EC_H */ diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/kernel-open/nvidia/hal/library/cryptlib/cryptlib_ecd.h nvidia-open-gpu-kernel-modules-535.161.08/kernel-open/nvidia/hal/library/cryptlib/cryptlib_ecd.h --- nvidia-open-gpu-kernel-modules-525.147.05/kernel-open/nvidia/hal/library/cryptlib/cryptlib_ecd.h 1970-01-01 00:00:00.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/kernel-open/nvidia/hal/library/cryptlib/cryptlib_ecd.h 2024-03-05 22:25:37.000000000 +0000 @@ -0,0 +1,100 @@ +/** + * Copyright Notice: + * Copyright 2021-2022 DMTF. All rights reserved. + * License: BSD 3-Clause License. For full text see link: https://github.com/DMTF/libspdm/blob/main/LICENSE.md + **/ + +#ifndef CRYPTLIB_ECD_H +#define CRYPTLIB_ECD_H + +/*===================================================================================== + * Edwards-Curve Primitives + *=====================================================================================*/ + +#if (LIBSPDM_EDDSA_ED25519_SUPPORT) || (LIBSPDM_EDDSA_ED448_SUPPORT) +/** + * Allocates and Initializes one Edwards-Curve context for subsequent use with the NID. + * + * @param nid cipher NID + * + * @return Pointer to the Edwards-Curve context that has been initialized. + * If the allocations fails, libspdm_ecd_new_by_nid() returns NULL. + **/ +extern void *libspdm_ecd_new_by_nid(size_t nid); + +/** + * Release the specified Ed context. + * + * @param[in] ecd_context Pointer to the Ed context to be released. + **/ +extern void libspdm_ecd_free(void *ecd_context); + +/** + * Carries out the Ed-DSA signature. + * + * This function carries out the Ed-DSA signature. + * If the signature buffer is too small to hold the contents of signature, false + * is returned and sig_size is set to the required buffer size to obtain the signature. + * + * If ecd_context is NULL, then return false. + * If message is NULL, then return false. + * hash_nid must be NULL. + * If sig_size is large enough but signature is NULL, then return false. + * + * For ed25519, context must be NULL and context_size must be 0. + * For ed448, context must be maximum of 255 octets. + * + * For ed25519, the sig_size is 64. first 32-byte is R, second 32-byte is S. + * For ed448, the sig_size is 114. first 57-byte is R, second 57-byte is S. + * + * @param[in] ecd_context Pointer to Ed context for signature generation. + * @param[in] hash_nid hash NID + * @param[in] context The EDDSA signing context. + * @param[in] context_size Size of EDDSA signing context. + * @param[in] message Pointer to octet message to be signed (before hash). + * @param[in] size size of the message in bytes. + * @param[out] signature Pointer to buffer to receive Ed-DSA signature. + * @param[in, out] sig_size On input, the size of signature buffer in bytes. + * On output, the size of data returned in signature buffer in bytes. + * + * @retval true signature successfully generated in Ed-DSA. + * @retval false signature generation failed. + * @retval false sig_size is too small. + **/ +extern bool libspdm_eddsa_sign(const void *ecd_context, size_t hash_nid, + const uint8_t *context, size_t context_size, + const uint8_t *message, size_t size, uint8_t *signature, + size_t *sig_size); + +/** + * Verifies the Ed-DSA signature. + * + * If ecd_context is NULL, then return false. + * If message is NULL, then return false. + * If signature is NULL, then return false. + * hash_nid must be NULL. + * + * For ed25519, context must be NULL and context_size must be 0. + * For ed448, context must be maximum of 255 octets. + * + * For ed25519, the sig_size is 64. first 32-byte is R, second 32-byte is S. + * For ed448, the sig_size is 114. first 57-byte is R, second 57-byte is S. + * + * @param[in] ecd_context Pointer to Ed context for signature verification. + * @param[in] hash_nid hash NID + * @param[in] context The EDDSA signing context. + * @param[in] context_size Size of EDDSA signing context. + * @param[in] message Pointer to octet message to be checked (before hash). + * @param[in] size Size of the message in bytes. + * @param[in] signature Pointer to Ed-DSA signature to be verified. + * @param[in] sig_size Size of signature in bytes. + * + * @retval true Valid signature encoded in Ed-DSA. + * @retval false Invalid signature or invalid Ed context. + **/ +extern bool libspdm_eddsa_verify(const void *ecd_context, size_t hash_nid, + const uint8_t *context, size_t context_size, + const uint8_t *message, size_t size, + const uint8_t *signature, size_t sig_size); +#endif /* (LIBSPDM_EDDSA_ED25519_SUPPORT) || (LIBSPDM_EDDSA_ED448_SUPPORT) */ +#endif /* CRYPTLIB_ECD_H */ diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/kernel-open/nvidia/hal/library/cryptlib/cryptlib_hash.h nvidia-open-gpu-kernel-modules-535.161.08/kernel-open/nvidia/hal/library/cryptlib/cryptlib_hash.h --- nvidia-open-gpu-kernel-modules-525.147.05/kernel-open/nvidia/hal/library/cryptlib/cryptlib_hash.h 1970-01-01 00:00:00.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/kernel-open/nvidia/hal/library/cryptlib/cryptlib_hash.h 2024-03-05 22:25:37.000000000 +0000 @@ -0,0 +1,772 @@ +/** + * Copyright Notice: + * Copyright 2021-2022 DMTF. All rights reserved. + * License: BSD 3-Clause License. For full text see link: https://github.com/DMTF/libspdm/blob/main/LICENSE.md + **/ + +#ifndef CRYPTLIB_HASH_H +#define CRYPTLIB_HASH_H + +/* SHA-256 digest size in bytes. */ +#define LIBSPDM_SHA256_DIGEST_SIZE 32 + +/* SHA-384 digest size in bytes. */ +#define LIBSPDM_SHA384_DIGEST_SIZE 48 + +/* SHA-512 digest size in bytes. */ +#define LIBSPDM_SHA512_DIGEST_SIZE 64 + +/* SHA3-256 digest size in bytes. */ +#define LIBSPDM_SHA3_256_DIGEST_SIZE 32 + +/* SHA3-384 digest size in bytes. */ +#define LIBSPDM_SHA3_384_DIGEST_SIZE 48 + +/* SHA3-512 digest size in bytes. */ +#define LIBSPDM_SHA3_512_DIGEST_SIZE 64 + +/* SM3_256 digest size in bytes. */ +#define LIBSPDM_SM3_256_DIGEST_SIZE 32 + +/*===================================================================================== + * One-way cryptographic hash SHA2 primitives. + *===================================================================================== + */ +#if LIBSPDM_SHA256_SUPPORT +/** + * Allocates and initializes one HASH_CTX context for subsequent SHA-256 use. + * + * @return Pointer to the HASH_CTX context that has been initialized. + * If the allocations fails, sha256_new() returns NULL. * + **/ +extern void *libspdm_sha256_new(void); + +/** + * Release the specified HASH_CTX context. + * + * @param[in] sha256_context Pointer to the HASH_CTX context to be released. + **/ +extern void libspdm_sha256_free(void *sha256_context); + +/** + * Initializes user-supplied memory pointed to by sha256_context as SHA-256 hash context for + * subsequent use. + * + * If sha256_context is NULL, then return false. + * + * @param[out] sha256_context Pointer to SHA-256 context being initialized. + * + * @retval true SHA-256 context initialization succeeded. + * @retval false SHA-256 context initialization failed. + **/ +extern bool libspdm_sha256_init(void *sha256_context); + +/** + * Makes a copy of an existing SHA-256 context. + * + * If sha256_context is NULL, then return false. + * If new_sha256_context is NULL, then return false. + * If this interface is not supported, then return false. + * + * @param[in] sha256_context Pointer to SHA-256 context being copied. + * @param[out] new_sha256_context Pointer to new SHA-256 context. + * + * @retval true SHA-256 context copy succeeded. + * @retval false SHA-256 context copy failed. + * @retval false This interface is not supported. + **/ +extern bool libspdm_sha256_duplicate(const void *sha256_context, void *new_sha256_context); + +/** + * Digests the input data and updates SHA-256 context. + * + * This function performs SHA-256 digest on a data buffer of the specified size. + * It can be called multiple times to compute the digest of long or discontinuous data streams. + * SHA-256 context should be already correctly initialized by libspdm_sha256_init(), and must not + * have been finalized by libspdm_sha256_final(). Behavior with invalid context is undefined. + * + * If sha256_context is NULL, then return false. + * + * @param[in, out] sha256_context Pointer to the SHA-256 context. + * @param[in] data Pointer to the buffer containing the data to be hashed. + * @param[in] data_size Size of data buffer in bytes. + * + * @retval true SHA-256 data digest succeeded. + * @retval false SHA-256 data digest failed. + **/ +extern bool libspdm_sha256_update(void *sha256_context, const void *data, size_t data_size); + +/** + * Completes computation of the SHA-256 digest value. + * + * This function completes SHA-256 hash computation and populates the digest value into + * the specified memory. After this function has been called, the SHA-256 context cannot + * be used again. SHA-256 context should be already correctly initialized by libspdm_sha256_init(), + * and must not have been finalized by libspdm_sha256_final(). Behavior with invalid SHA-256 context + * is undefined. + * + * If sha256_context is NULL, then return false. + * If hash_value is NULL, then return false. + * + * @param[in, out] sha256_context Pointer to the SHA-256 context. + * @param[out] hash_value Pointer to a buffer that receives the SHA-256 digest + * value (32 bytes). + * + * @retval true SHA-256 digest computation succeeded. + * @retval false SHA-256 digest computation failed. + **/ +extern bool libspdm_sha256_final(void *sha256_context, uint8_t *hash_value); + +/** + * Computes the SHA-256 message digest of an input data buffer. + * + * This function performs the SHA-256 message digest of a given data buffer, and places + * the digest value into the specified memory. + * + * If this interface is not supported, then return false. + * + * @param[in] data Pointer to the buffer containing the data to be hashed. + * @param[in] data_size Size of data buffer in bytes. + * @param[out] hash_value Pointer to a buffer that receives the SHA-256 digest value (32 bytes). + * + * @retval true SHA-256 digest computation succeeded. + * @retval false SHA-256 digest computation failed. + * @retval false This interface is not supported. + **/ +extern bool libspdm_sha256_hash_all(const void *data, size_t data_size, uint8_t *hash_value); +#endif /* LIBSPDM_SHA256_SUPPORT */ + +#if LIBSPDM_SHA384_SUPPORT +/** + * Allocates and initializes one HASH_CTX context for subsequent SHA-384 use. + * + * @return Pointer to the HASH_CTX context that has been initialized. + * If the allocations fails, libspdm_sha384_new() returns NULL. + **/ +extern void *libspdm_sha384_new(void); + +/** + * Release the specified HASH_CTX context. + * + * @param[in] sha384_context Pointer to the HASH_CTX context to be released. + **/ +extern void libspdm_sha384_free(void *sha384_context); + +/** + * Initializes user-supplied memory pointed to by sha384_context as SHA-384 hash context for + * subsequent use. + * + * If sha384_context is NULL, then return false. + * + * @param[out] sha384_context Pointer to SHA-384 context being initialized. + * + * @retval true SHA-384 context initialization succeeded. + * @retval false SHA-384 context initialization failed. + **/ +extern bool libspdm_sha384_init(void *sha384_context); + +/** + * Makes a copy of an existing SHA-384 context. + * + * If sha384_context is NULL, then return false. + * If new_sha384_context is NULL, then return false. + * If this interface is not supported, then return false. + * + * @param[in] sha384_context Pointer to SHA-384 context being copied. + * @param[out] new_sha384_context Pointer to new SHA-384 context. + * + * @retval true SHA-384 context copy succeeded. + * @retval false SHA-384 context copy failed. + * @retval false This interface is not supported. + **/ +extern bool libspdm_sha384_duplicate(const void *sha384_context, void *new_sha384_context); + +/** + * Digests the input data and updates SHA-384 context. + * + * This function performs SHA-384 digest on a data buffer of the specified size. + * It can be called multiple times to compute the digest of long or discontinuous data streams. + * SHA-384 context should be already correctly initialized by libspdm_sha384_init(), and must not + * have been finalized by libspdm_sha384_final(). Behavior with invalid context is undefined. + * + * If sha384_context is NULL, then return false. + * + * @param[in, out] sha384_context Pointer to the SHA-384 context. + * @param[in] data Pointer to the buffer containing the data to be hashed. + * @param[in] data_size Size of data buffer in bytes. + * + * @retval true SHA-384 data digest succeeded. + * @retval false SHA-384 data digest failed. + **/ +extern bool libspdm_sha384_update(void *sha384_context, const void *data, size_t data_size); + +/** + * Completes computation of the SHA-384 digest value. + * + * This function completes SHA-384 hash computation and populates the digest value into + * the specified memory. After this function has been called, the SHA-384 context cannot + * be used again. SHA-384 context should be already correctly initialized by libspdm_sha384_init(), + * and must not have been finalized by libspdm_sha384_final(). Behavior with invalid SHA-384 context + * is undefined. + * + * If sha384_context is NULL, then return false. + * If hash_value is NULL, then return false. + * + * @param[in, out] sha384_context Pointer to the SHA-384 context. + * @param[out] hash_value Pointer to a buffer that receives the SHA-384 digest + * value (48 bytes). + * + * @retval true SHA-384 digest computation succeeded. + * @retval false SHA-384 digest computation failed. + **/ +extern bool libspdm_sha384_final(void *sha384_context, uint8_t *hash_value); + +/** + * Computes the SHA-384 message digest of an input data buffer. + * + * This function performs the SHA-384 message digest of a given data buffer, and places + * the digest value into the specified memory. + * + * If this interface is not supported, then return false. + * + * @param[in] data Pointer to the buffer containing the data to be hashed. + * @param[in] data_size Size of data buffer in bytes. + * @param[out] hash_value Pointer to a buffer that receives the SHA-384 digest value (48 bytes). + * + * @retval true SHA-384 digest computation succeeded. + * @retval false SHA-384 digest computation failed. + * @retval false This interface is not supported. + **/ +extern bool libspdm_sha384_hash_all(const void *data, size_t data_size, uint8_t *hash_value); +#endif /* LIBSPDM_SHA384_SUPPORT */ + +#if LIBSPDM_SHA512_SUPPORT +/** + * Allocates and initializes one HASH_CTX context for subsequent SHA-512 use. + * + * @return Pointer to the HASH_CTX context that has been initialized. + * If the allocations fails, libspdm_sha512_new() returns NULL. + **/ +extern void *libspdm_sha512_new(void); + +/** + * Release the specified HASH_CTX context. + * + * @param[in] sha512_context Pointer to the HASH_CTX context to be released. + **/ +extern void libspdm_sha512_free(void *sha512_context); + +/** + * Initializes user-supplied memory pointed by sha512_context as SHA-512 hash context for + * subsequent use. + * + * If sha512_context is NULL, then return false. + * + * @param[out] sha512_context Pointer to SHA-512 context being initialized. + * + * @retval true SHA-512 context initialization succeeded. + * @retval false SHA-512 context initialization failed. + **/ +extern bool libspdm_sha512_init(void *sha512_context); + +/** + * Makes a copy of an existing SHA-512 context. + * + * If sha512_context is NULL, then return false. + * If new_sha512_context is NULL, then return false. + * If this interface is not supported, then return false. + * + * @param[in] sha512_context Pointer to SHA-512 context being copied. + * @param[out] new_sha512_context Pointer to new SHA-512 context. + * + * @retval true SHA-512 context copy succeeded. + * @retval false SHA-512 context copy failed. + * @retval false This interface is not supported. + **/ +extern bool libspdm_sha512_duplicate(const void *sha512_context, void *new_sha512_context); + +/** + * Digests the input data and updates SHA-512 context. + * + * This function performs SHA-512 digest on a data buffer of the specified size. + * It can be called multiple times to compute the digest of long or discontinuous data streams. + * SHA-512 context should be already correctly initialized by libspdm_sha512_init(), and must not + * have been finalized by libspdm_sha512_final(). Behavior with invalid context is undefined. + * + * If sha512_context is NULL, then return false. + * + * @param[in, out] sha512_context Pointer to the SHA-512 context. + * @param[in] data Pointer to the buffer containing the data to be hashed. + * @param[in] data_size Size of data buffer in bytes. + * + * @retval true SHA-512 data digest succeeded. + * @retval false SHA-512 data digest failed. + **/ +extern bool libspdm_sha512_update(void *sha512_context, const void *data, size_t data_size); + +/** + * Completes computation of the SHA-512 digest value. + * + * This function completes SHA-512 hash computation and populates the digest value into + * the specified memory. After this function has been called, the SHA-512 context cannot + * be used again. SHA-512 context should be already correctly initialized by libspdm_sha512_init(), + * and must not have been finalized by libspdm_sha512_final(). Behavior with invalid SHA-512 context + * is undefined. + * + * If sha512_context is NULL, then return false. + * If hash_value is NULL, then return false. + * + * @param[in, out] sha512_context Pointer to the SHA-512 context. + * @param[out] hash_value Pointer to a buffer that receives the SHA-512 digest + * value (64 bytes). + * + * @retval true SHA-512 digest computation succeeded. + * @retval false SHA-512 digest computation failed. + **/ +extern bool libspdm_sha512_final(void *sha512_context, uint8_t *hash_value); + +/** + * Computes the SHA-512 message digest of an input data buffer. + * + * This function performs the SHA-512 message digest of a given data buffer, and places + * the digest value into the specified memory. + * + * If this interface is not supported, then return false. + * + * @param[in] data Pointer to the buffer containing the data to be hashed. + * @param[in] data_size Size of data buffer in bytes. + * @param[out] hash_value Pointer to a buffer that receives the SHA-512 digest value (64 bytes). + * + * @retval true SHA-512 digest computation succeeded. + * @retval false SHA-512 digest computation failed. + * @retval false This interface is not supported. + **/ +extern bool libspdm_sha512_hash_all(const void *data, size_t data_size, uint8_t *hash_value); +#endif /* LIBSPDM_SHA512_SUPPORT */ + +/*===================================================================================== + * One-way cryptographic hash SHA3 primitives. + *===================================================================================== + */ +#if LIBSPDM_SHA3_256_SUPPORT +/** + * Allocates and initializes one HASH_CTX context for subsequent SHA3-256 use. + * + * @return Pointer to the HASH_CTX context that has been initialized. + * If the allocations fails, libspdm_sha3_256_new() returns NULL. + **/ +extern void *libspdm_sha3_256_new(void); + +/** + * Release the specified HASH_CTX context. + * + * @param[in] sha3_256_context Pointer to the HASH_CTX context to be released. + **/ +extern void libspdm_sha3_256_free(void *sha3_256_context); + +/** + * Initializes user-supplied memory pointed by sha3_256_context as SHA3-256 hash context for + * subsequent use. + * + * If sha3_256_context is NULL, then return false. + * + * @param[out] sha3_256_context Pointer to SHA3-256 context being initialized. + * + * @retval true SHA3-256 context initialization succeeded. + * @retval false SHA3-256 context initialization failed. + **/ +extern bool libspdm_sha3_256_init(void *sha3_256_context); + +/** + * Makes a copy of an existing SHA3-256 context. + * + * If sha3_256_context is NULL, then return false. + * If new_sha3_256_context is NULL, then return false. + * If this interface is not supported, then return false. + * + * @param[in] sha3_256_context Pointer to SHA3-256 context being copied. + * @param[out] new_sha3_256_context Pointer to new SHA3-256 context. + * + * @retval true SHA3-256 context copy succeeded. + * @retval false SHA3-256 context copy failed. + * @retval false This interface is not supported. + **/ +extern bool libspdm_sha3_256_duplicate(const void *sha3_256_context, void *new_sha3_256_context); + +/** + * Digests the input data and updates SHA3-256 context. + * + * This function performs SHA3-256 digest on a data buffer of the specified size. + * It can be called multiple times to compute the digest of long or discontinuous data streams. + * SHA3-256 context should be already correctly initialized by libspdm_sha3_256_init(), and must not + * have been finalized by libspdm_sha3_256_final(). Behavior with invalid context is undefined. + * + * If sha3_256_context is NULL, then return false. + * + * @param[in, out] sha3_256_context Pointer to the SHA3-256 context. + * @param[in] data Pointer to the buffer containing the data to be hashed. + * @param[in] data_size size of data buffer in bytes. + * + * @retval true SHA3-256 data digest succeeded. + * @retval false SHA3-256 data digest failed. + **/ +extern bool libspdm_sha3_256_update(void *sha3_256_context, const void *data, size_t data_size); + +/** + * Completes computation of the SHA3-256 digest value. + * + * This function completes SHA3-256 hash computation and populates the digest value into + * the specified memory. After this function has been called, the SHA3-512 context cannot + * be used again. SHA3-256 context should be already correctly initialized by + * libspdm_sha3_256_init(), and must not have been finalized by libspdm_sha3_256_final(). + * Behavior with invalid SHA3-256 context is undefined. + * + * If sha3_256_context is NULL, then return false. + * If hash_value is NULL, then return false. + * + * @param[in, out] sha3_256_context Pointer to the SHA3-256 context. + * @param[out] hash_value Pointer to a buffer that receives the SHA3-256 digest + * value (32 bytes). + * + * @retval true SHA3-256 digest computation succeeded. + * @retval false SHA3-256 digest computation failed. + **/ +extern bool libspdm_sha3_256_final(void *sha3_256_context, uint8_t *hash_value); + +/** + * Computes the SHA3-256 message digest of an input data buffer. + * + * This function performs the SHA3-256 message digest of a given data buffer, and places + * the digest value into the specified memory. + * + * If this interface is not supported, then return false. + * + * @param[in] data Pointer to the buffer containing the data to be hashed. + * @param[in] data_size Size of data buffer in bytes. + * @param[out] hash_value Pointer to a buffer that receives the SHA3-256 digest value (32 bytes). + * + * @retval true SHA3-256 digest computation succeeded. + * @retval false SHA3-256 digest computation failed. + * @retval false This interface is not supported. + **/ +extern bool libspdm_sha3_256_hash_all(const void *data, size_t data_size, uint8_t *hash_value); +#endif /* LIBSPDM_SHA3_256_SUPPORT */ + +#if LIBSPDM_SHA3_384_SUPPORT +/** + * Allocates and initializes one HASH_CTX context for subsequent SHA3-384 use. + * + * @return Pointer to the HASH_CTX context that has been initialized. + * If the allocations fails, libspdm_sha3_384_new() returns NULL. + **/ +extern void *libspdm_sha3_384_new(void); + +/** + * Release the specified HASH_CTX context. + * + * @param[in] sha3_384_context Pointer to the HASH_CTX context to be released. + **/ +extern void libspdm_sha3_384_free(void *sha3_384_context); + +/** + * Initializes user-supplied memory pointed by sha3_384_context as SHA3-384 hash context for + * subsequent use. + * + * If sha3_384_context is NULL, then return false. + * + * @param[out] sha3_384_context Pointer to SHA3-384 context being initialized. + * + * @retval true SHA3-384 context initialization succeeded. + * @retval false SHA3-384 context initialization failed. + **/ +extern bool libspdm_sha3_384_init(void *sha3_384_context); + +/** + * Makes a copy of an existing SHA3-384 context. + * + * If sha3_384_context is NULL, then return false. + * If new_sha3_384_context is NULL, then return false. + * If this interface is not supported, then return false. + * + * @param[in] sha3_384_context Pointer to SHA3-384 context being copied. + * @param[out] new_sha3_384_context Pointer to new SHA3-384 context. + * + * @retval true SHA3-384 context copy succeeded. + * @retval false SHA3-384 context copy failed. + * @retval false This interface is not supported. + **/ +extern bool libspdm_sha3_384_duplicate(const void *sha3_384_context, void *new_sha3_384_context); + +/** + * Digests the input data and updates SHA3-384 context. + * + * This function performs SHA3-384 digest on a data buffer of the specified size. + * It can be called multiple times to compute the digest of long or discontinuous data streams. + * SHA3-384 context should be already correctly initialized by libspdm_sha3_384_init(), and must not + * have been finalized by libspdm_sha3_384_final(). Behavior with invalid context is undefined. + * + * If sha3_384_context is NULL, then return false. + * + * @param[in, out] sha3_384_context Pointer to the SHA3-384 context. + * @param[in] data Pointer to the buffer containing the data to be hashed. + * @param[in] data_size Size of data buffer in bytes. + * + * @retval true SHA3-384 data digest succeeded. + * @retval false SHA3-384 data digest failed. + **/ +extern bool libspdm_sha3_384_update(void *sha3_384_context, const void *data, size_t data_size); + +/** + * Completes computation of the SHA3-384 digest value. + * + * This function completes SHA3-384 hash computation and populates the digest value into + * the specified memory. After this function has been called, the SHA3-384 context cannot + * be used again. SHA3-384 context should be already correctly initialized by + * libspdm_sha3_384_init(), and must not have been finalized by libspdm_sha3_384_final(). + * Behavior with invalid SHA3-384 context is undefined. + * + * If sha3_384_context is NULL, then return false. + * If hash_value is NULL, then return false. + * + * @param[in, out] sha3_384_context Pointer to the SHA3-384 context. + * @param[out] hash_value Pointer to a buffer that receives the SHA3-384 digest + * value (48 bytes). + * + * @retval true SHA3-384 digest computation succeeded. + * @retval false SHA3-384 digest computation failed. + * + **/ +extern bool libspdm_sha3_384_final(void *sha3_384_context, uint8_t *hash_value); + +/** + * Computes the SHA3-384 message digest of an input data buffer. + * + * This function performs the SHA3-384 message digest of a given data buffer, and places + * the digest value into the specified memory. + * + * If this interface is not supported, then return false. + * + * @param[in] data Pointer to the buffer containing the data to be hashed. + * @param[in] data_size Size of data buffer in bytes. + * @param[out] hash_value Pointer to a buffer that receives the SHA3-384 digest value (48 bytes). + * + * @retval true SHA3-384 digest computation succeeded. + * @retval false SHA3-384 digest computation failed. + * @retval false This interface is not supported. + **/ +extern bool libspdm_sha3_384_hash_all(const void *data, size_t data_size, uint8_t *hash_value); +#endif /* LIBSPDM_SHA3_384_SUPPORT */ + +#if LIBSPDM_SHA3_512_SUPPORT +/** + * Allocates and initializes one HASH_CTX context for subsequent SHA3-512 use. + * + * @return Pointer to the HASH_CTX context that has been initialized. + * If the allocations fails, libspdm_sha3_512_new() returns NULL. + **/ +extern void *libspdm_sha3_512_new(void); + +/** + * Release the specified HASH_CTX context. + * + * @param[in] sha3_512_context Pointer to the HASH_CTX context to be released. + **/ +extern void libspdm_sha3_512_free(void *sha3_512_context); + +/** + * Initializes user-supplied memory pointed by sha3_512_context as SHA3-512 hash context for + * subsequent use. + * + * If sha3_512_context is NULL, then return false. + * + * @param[out] sha3_512_context Pointer to SHA3-512 context being initialized. + * + * @retval true SHA3-512 context initialization succeeded. + * @retval false SHA3-512 context initialization failed. + **/ +extern bool libspdm_sha3_512_init(void *sha3_512_context); + +/** + * Makes a copy of an existing SHA3-512 context. + * + * If sha3_512_context is NULL, then return false. + * If new_sha3_512_context is NULL, then return false. + * If this interface is not supported, then return false. + * + * @param[in] sha3_512_context Pointer to SHA3-512 context being copied. + * @param[out] new_sha3_512_context Pointer to new SHA3-512 context. + * + * @retval true SHA3-512 context copy succeeded. + * @retval false SHA3-512 context copy failed. + * @retval false This interface is not supported. + * + **/ +extern bool libspdm_sha3_512_duplicate(const void *sha3_512_context, void *new_sha3_512_context); + +/** + * Digests the input data and updates SHA3-512 context. + * + * This function performs SHA3-512 digest on a data buffer of the specified size. + * It can be called multiple times to compute the digest of long or discontinuous data streams. + * SHA3-512 context should be already correctly initialized by libspdm_sha3_512_init(), and must not + * have been finalized by libspdm_sha3_512_final(). Behavior with invalid context is undefined. + * + * If sha3_512_context is NULL, then return false. + * + * @param[in, out] sha3_512_context Pointer to the SHA3-512 context. + * @param[in] data Pointer to the buffer containing the data to be hashed. + * @param[in] data_size Size of data buffer in bytes. + * + * @retval true SHA3-512 data digest succeeded. + * @retval false SHA3-512 data digest failed. + **/ +extern bool libspdm_sha3_512_update(void *sha3_512_context, const void *data, size_t data_size); + +/** + * Completes computation of the SHA3-512 digest value. + * + * This function completes SHA3-512 hash computation and populates the digest value into + * the specified memory. After this function has been called, the SHA3-512 context cannot + * be used again. SHA3-512 context should be already correctly initialized by + * libspdm_sha3_512_init(), and must not have been finalized by libspdm_sha3_512_final(). + * Behavior with invalid SHA3-512 context is undefined. + * + * If sha3_512_context is NULL, then return false. + * If hash_value is NULL, then return false. + * + * @param[in, out] sha3_512_context Pointer to the SHA3-512 context. + * @param[out] hash_value Pointer to a buffer that receives the SHA3-512 digest + * value (64 bytes). + * + * @retval true SHA3-512 digest computation succeeded. + * @retval false SHA3-512 digest computation failed. + **/ +extern bool libspdm_sha3_512_final(void *sha3_512_context, uint8_t *hash_value); + +/** + * Computes the SHA3-512 message digest of an input data buffer. + * + * This function performs the SHA3-512 message digest of a given data buffer, and places + * the digest value into the specified memory. + * + * If this interface is not supported, then return false. + * + * @param[in] data Pointer to the buffer containing the data to be hashed. + * @param[in] data_size Size of data buffer in bytes. + * @param[out] hash_value Pointer to a buffer that receives the SHA3-512 digest value (64 bytes). + * + * @retval true SHA3-512 digest computation succeeded. + * @retval false SHA3-512 digest computation failed. + * @retval false This interface is not supported. + **/ +extern bool libspdm_sha3_512_hash_all(const void *data, size_t data_size, uint8_t *hash_value); +#endif /* LIBSPDM_SHA3_512_SUPPORT */ + +/*===================================================================================== + * One-Way Cryptographic hash SM3 Primitives + *===================================================================================== + */ + +#if LIBSPDM_SM3_256_SUPPORT +/** + * Allocates and initializes one HASH_CTX context for subsequent SM3-256 use. + * + * @return Pointer to the HASH_CTX context that has been initialized. + * If the allocations fails, libspdm_sm3_256_new() returns NULL. + **/ +extern void *libspdm_sm3_256_new(void); + +/** + * Release the specified HASH_CTX context. + * + * @param[in] sm3_context Pointer to the HASH_CTX context to be released. + **/ +extern void libspdm_sm3_256_free(void *sm3_context); + +/** + * Initializes user-supplied memory pointed by sm3_context as SM3 hash context for + * subsequent use. + * + * If sm3_context is NULL, then return false. + * + * @param[out] sm3_context Pointer to SM3 context being initialized. + * + * @retval true SM3 context initialization succeeded. + * @retval false SM3 context initialization failed. + **/ +extern bool libspdm_sm3_256_init(void *sm3_context); + +/** + * Makes a copy of an existing SM3 context. + * + * If sm3_context is NULL, then return false. + * If new_sm3_context is NULL, then return false. + * If this interface is not supported, then return false. + * + * @param[in] sm3_context Pointer to SM3 context being copied. + * @param[out] new_sm3_context Pointer to new SM3 context. + * + * @retval true SM3 context copy succeeded. + * @retval false SM3 context copy failed. + * @retval false This interface is not supported. + **/ +extern bool libspdm_sm3_256_duplicate(const void *sm3_context, void *new_sm3_context); + +/** + * Digests the input data and updates SM3 context. + * + * This function performs SM3 digest on a data buffer of the specified size. + * It can be called multiple times to compute the digest of long or discontinuous data streams. + * SM3 context should be already correctly initialized by sm3_init(), and should not be finalized + * by sm3_final(). Behavior with invalid context is undefined. + * + * If sm3_context is NULL, then return false. + * + * @param[in, out] sm3_context Pointer to the SM3 context. + * @param[in] data Pointer to the buffer containing the data to be hashed. + * @param[in] data_size Size of data buffer in bytes. + * + * @retval true SM3 data digest succeeded. + * @retval false SM3 data digest failed. + **/ +extern bool libspdm_sm3_256_update(void *sm3_context, const void *data, size_t data_size); + +/** + * Completes computation of the SM3 digest value. + * + * This function completes SM3 hash computation and retrieves the digest value into + * the specified memory. After this function has been called, the SM3 context cannot + * be used again. SM3 context should be already correctly initialized by sm3_init(), and should not + * be finalized by sm3_final(). Behavior with invalid SM3 context is undefined. + * + * If sm3_context is NULL, then return false. + * If hash_value is NULL, then return false. + * + * @param[in, out] sm3_context Pointer to the SM3 context. + * @param[out] hash_value Pointer to a buffer that receives the SM3 digest value (32 bytes). + * + * @retval true SM3 digest computation succeeded. + * @retval false SM3 digest computation failed. + **/ +extern bool libspdm_sm3_256_final(void *sm3_context, uint8_t *hash_value); + +/** + * Computes the SM3 message digest of an input data buffer. + * + * This function performs the SM3 message digest of a given data buffer, and places + * the digest value into the specified memory. + * + * If this interface is not supported, then return false. + * + * @param[in] data Pointer to the buffer containing the data to be hashed. + * @param[in] data_size Size of data buffer in bytes. + * @param[out] hash_value Pointer to a buffer that receives the SM3 digest value (32 bytes). + * + * @retval true SM3 digest computation succeeded. + * @retval false SM3 digest computation failed. + * @retval false This interface is not supported. + **/ +extern bool libspdm_sm3_256_hash_all(const void *data, size_t data_size, uint8_t *hash_value); +#endif /* LIBSPDM_SM3_256_SUPPORT */ + +#endif /* CRYPTLIB_HASH_H */ diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/kernel-open/nvidia/hal/library/cryptlib/cryptlib_hkdf.h nvidia-open-gpu-kernel-modules-535.161.08/kernel-open/nvidia/hal/library/cryptlib/cryptlib_hkdf.h --- nvidia-open-gpu-kernel-modules-525.147.05/kernel-open/nvidia/hal/library/cryptlib/cryptlib_hkdf.h 1970-01-01 00:00:00.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/kernel-open/nvidia/hal/library/cryptlib/cryptlib_hkdf.h 2024-03-05 22:25:37.000000000 +0000 @@ -0,0 +1,266 @@ +/** + * Copyright Notice: + * Copyright 2021-2022 DMTF. All rights reserved. + * License: BSD 3-Clause License. For full text see link: https://github.com/DMTF/libspdm/blob/main/LICENSE.md + **/ + +#ifndef CRYPTLIB_HKDF_H +#define CRYPTLIB_HKDF_H + +/*===================================================================================== + * Key Derivation Function Primitives + *=====================================================================================*/ + +#if LIBSPDM_SHA256_SUPPORT +/** + * Derive SHA-256 HMAC-based Extract key Derivation Function (HKDF). + * + * @param[in] key Pointer to the user-supplied key. + * @param[in] key_size Key size in bytes. + * @param[in] salt Pointer to the salt value. + * @param[in] salt_size Salt size in bytes. + * @param[out] prk_out Pointer to buffer to receive prk value. + * @param[in] prk_out_size Size of prk bytes to generate. + * + * @retval true Hkdf generated successfully. + * @retval false Hkdf generation failed. + **/ +extern bool libspdm_hkdf_sha256_extract(const uint8_t *key, size_t key_size, + const uint8_t *salt, size_t salt_size, + uint8_t *prk_out, size_t prk_out_size); + +/** + * Derive SHA256 HMAC-based Expand key Derivation Function (HKDF). + * + * @param[in] prk Pointer to the user-supplied key. + * @param[in] prk_size Key size in bytes. + * @param[in] info Pointer to the application specific info. + * @param[in] info_size Info size in bytes. + * @param[out] out Pointer to buffer to receive hkdf value. + * @param[in] out_size Size of hkdf bytes to generate. + * + * @retval true Hkdf generated successfully. + * @retval false Hkdf generation failed. + **/ +extern bool libspdm_hkdf_sha256_expand(const uint8_t *prk, size_t prk_size, + const uint8_t *info, size_t info_size, + uint8_t *out, size_t out_size); +#endif /* LIBSPDM_SHA256_SUPPORT */ + +#if LIBSPDM_SHA384_SUPPORT +/** + * Derive SHA384 HMAC-based Extract key Derivation Function (HKDF). + * + * @param[in] key Pointer to the user-supplied key. + * @param[in] key_size Key size in bytes. + * @param[in] salt Pointer to the salt value. + * @param[in] salt_size Salt size in bytes. + * @param[out] prk_out Pointer to buffer to receive hkdf value. + * @param[in] prk_out_size Size of hkdf bytes to generate. + * + * @retval true Hkdf generated successfully. + * @retval false Hkdf generation failed. + **/ +extern bool libspdm_hkdf_sha384_extract(const uint8_t *key, size_t key_size, + const uint8_t *salt, size_t salt_size, + uint8_t *prk_out, size_t prk_out_size); + +/** + * Derive SHA384 HMAC-based Expand key Derivation Function (HKDF). + * + * @param[in] prk Pointer to the user-supplied key. + * @param[in] prk_size Key size in bytes. + * @param[in] info Pointer to the application specific info. + * @param[in] info_size Info size in bytes. + * @param[out] out Pointer to buffer to receive hkdf value. + * @param[in] out_size Size of hkdf bytes to generate. + * + * @retval true Hkdf generated successfully. + * @retval false Hkdf generation failed. + **/ +extern bool libspdm_hkdf_sha384_expand(const uint8_t *prk, size_t prk_size, + const uint8_t *info, size_t info_size, + uint8_t *out, size_t out_size); +#endif /* LIBSPDM_SHA384_SUPPORT */ + +#if LIBSPDM_SHA512_SUPPORT +/** + * Derive SHA512 HMAC-based Extract key Derivation Function (HKDF). + * + * @param[in] key Pointer to the user-supplied key. + * @param[in] key_size Key size in bytes. + * @param[in] salt Pointer to the salt value. + * @param[in] salt_size Salt size in bytes. + * @param[out] prk_out Pointer to buffer to receive hkdf value. + * @param[in] prk_out_size Size of hkdf bytes to generate. + * + * @retval true Hkdf generated successfully. + * @retval false Hkdf generation failed. + **/ +extern bool libspdm_hkdf_sha512_extract(const uint8_t *key, size_t key_size, + const uint8_t *salt, size_t salt_size, + uint8_t *prk_out, size_t prk_out_size); + +/** + * Derive SHA512 HMAC-based Expand key Derivation Function (HKDF). + * + * @param[in] prk Pointer to the user-supplied key. + * @param[in] prk_size Key size in bytes. + * @param[in] info Pointer to the application specific info. + * @param[in] info_size Info size in bytes. + * @param[out] out Pointer to buffer to receive hkdf value. + * @param[in] out_size Size of hkdf bytes to generate. + * + * @retval true Hkdf generated successfully. + * @retval false Hkdf generation failed. + **/ +extern bool libspdm_hkdf_sha512_expand(const uint8_t *prk, size_t prk_size, + const uint8_t *info, size_t info_size, + uint8_t *out, size_t out_size); +#endif /* LIBSPDM_SHA512_SUPPORT */ + +#if LIBSPDM_SHA3_256_SUPPORT +/** + * Derive SHA3_256 HMAC-based Extract key Derivation Function (HKDF). + * + * @param[in] key Pointer to the user-supplied key. + * @param[in] key_size Key size in bytes. + * @param[in] salt Pointer to the salt value. + * @param[in] salt_size Salt size in bytes. + * @param[out] prk_out Pointer to buffer to receive hkdf value. + * @param[in] prk_out_size Size of hkdf bytes to generate. + * + * @retval true Hkdf generated successfully. + * @retval false Hkdf generation failed. + **/ +extern bool libspdm_hkdf_sha3_256_extract(const uint8_t *key, size_t key_size, + const uint8_t *salt, size_t salt_size, + uint8_t *prk_out, size_t prk_out_size); + +/** + * Derive SHA3_256 HMAC-based Expand key Derivation Function (HKDF). + * + * @param[in] prk Pointer to the user-supplied key. + * @param[in] prk_size Key size in bytes. + * @param[in] info Pointer to the application specific info. + * @param[in] info_size Info size in bytes. + * @param[out] out Pointer to buffer to receive hkdf value. + * @param[in] out_size Size of hkdf bytes to generate. + * + * @retval true Hkdf generated successfully. + * @retval false Hkdf generation failed. + **/ +extern bool libspdm_hkdf_sha3_256_expand(const uint8_t *prk, size_t prk_size, + const uint8_t *info, size_t info_size, + uint8_t *out, size_t out_size); +#endif /* LIBSPDM_SHA3_256_SUPPORT */ + +#if LIBSPDM_SHA3_384_SUPPORT +/** + * Derive SHA3_384 HMAC-based Extract key Derivation Function (HKDF). + * + * @param[in] key Pointer to the user-supplied key. + * @param[in] key_size Key size in bytes. + * @param[in] salt Pointer to the salt value. + * @param[in] salt_size Salt size in bytes. + * @param[out] prk_out Pointer to buffer to receive hkdf value. + * @param[in] prk_out_size Size of hkdf bytes to generate. + * + * @retval true Hkdf generated successfully. + * @retval false Hkdf generation failed. + **/ +extern bool libspdm_hkdf_sha3_384_extract(const uint8_t *key, size_t key_size, + const uint8_t *salt, size_t salt_size, + uint8_t *prk_out, size_t prk_out_size); + +/** + * Derive SHA3_384 HMAC-based Expand key Derivation Function (HKDF). + * + * @param[in] prk Pointer to the user-supplied key. + * @param[in] prk_size Key size in bytes. + * @param[in] info Pointer to the application specific info. + * @param[in] info_size Info size in bytes. + * @param[out] out Pointer to buffer to receive hkdf value. + * @param[in] out_size Size of hkdf bytes to generate. + * + * @retval true Hkdf generated successfully. + * @retval false Hkdf generation failed. + **/ +extern bool libspdm_hkdf_sha3_384_expand(const uint8_t *prk, size_t prk_size, + const uint8_t *info, size_t info_size, + uint8_t *out, size_t out_size); +#endif /* LIBSPDM_SHA3_384_SUPPORT */ + +#if LIBSPDM_SHA3_512_SUPPORT +/** + * Derive SHA3_512 HMAC-based Extract key Derivation Function (HKDF). + * + * @param[in] key Pointer to the user-supplied key. + * @param[in] key_size Key size in bytes. + * @param[in] salt Pointer to the salt value. + * @param[in] salt_size Salt size in bytes. + * @param[out] prk_out Pointer to buffer to receive hkdf value. + * @param[in] prk_out_size Size of hkdf bytes to generate. + * + * @retval true Hkdf generated successfully. + * @retval false Hkdf generation failed. + **/ +extern bool libspdm_hkdf_sha3_512_extract(const uint8_t *key, size_t key_size, + const uint8_t *salt, size_t salt_size, + uint8_t *prk_out, size_t prk_out_size); + +/** + * Derive SHA3_512 HMAC-based Expand key Derivation Function (HKDF). + * + * @param[in] prk Pointer to the user-supplied key. + * @param[in] prk_size Key size in bytes. + * @param[in] info Pointer to the application specific info. + * @param[in] info_size Info size in bytes. + * @param[out] out Pointer to buffer to receive hkdf value. + * @param[in] out_size Size of hkdf bytes to generate. + * + * @retval true Hkdf generated successfully. + * @retval false Hkdf generation failed. + **/ +extern bool libspdm_hkdf_sha3_512_expand(const uint8_t *prk, size_t prk_size, + const uint8_t *info, size_t info_size, + uint8_t *out, size_t out_size); +#endif /* LIBSPDM_SHA3_512_SUPPORT */ + +#if LIBSPDM_SM3_256_SUPPORT +/** + * Derive SM3_256 HMAC-based Extract key Derivation Function (HKDF). + * + * @param[in] key Pointer to the user-supplied key. + * @param[in] key_size Key size in bytes. + * @param[in] salt Pointer to the salt value. + * @param[in] salt_size Salt size in bytes. + * @param[out] prk_out Pointer to buffer to receive hkdf value. + * @param[in] prk_out_size Size of hkdf bytes to generate. + * + * @retval true Hkdf generated successfully. + * @retval false Hkdf generation failed. + **/ +extern bool libspdm_hkdf_sm3_256_extract(const uint8_t *key, size_t key_size, + const uint8_t *salt, size_t salt_size, + uint8_t *prk_out, size_t prk_out_size); + +/** + * Derive SM3_256 HMAC-based Expand key Derivation Function (HKDF). + * + * @param[in] prk Pointer to the user-supplied key. + * @param[in] prk_size Key size in bytes. + * @param[in] info Pointer to the application specific info. + * @param[in] info_size Info size in bytes. + * @param[out] out Pointer to buffer to receive hkdf value. + * @param[in] out_size Size of hkdf bytes to generate. + * + * @retval true Hkdf generated successfully. + * @retval false Hkdf generation failed. + **/ +extern bool libspdm_hkdf_sm3_256_expand(const uint8_t *prk, size_t prk_size, + const uint8_t *info, size_t info_size, + uint8_t *out, size_t out_size); +#endif /* LIBSPDM_SM3_256_SUPPORT */ + +#endif /* CRYPTLIB_HKDF_H */ diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/kernel-open/nvidia/hal/library/cryptlib/cryptlib_mac.h nvidia-open-gpu-kernel-modules-535.161.08/kernel-open/nvidia/hal/library/cryptlib/cryptlib_mac.h --- nvidia-open-gpu-kernel-modules-525.147.05/kernel-open/nvidia/hal/library/cryptlib/cryptlib_mac.h 1970-01-01 00:00:00.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/kernel-open/nvidia/hal/library/cryptlib/cryptlib_mac.h 2024-03-05 22:25:37.000000000 +0000 @@ -0,0 +1,833 @@ +/** + * Copyright Notice: + * Copyright 2021-2022 DMTF. All rights reserved. + * License: BSD 3-Clause License. For full text see link: https://github.com/DMTF/libspdm/blob/main/LICENSE.md + **/ + +#ifndef CRYPTLIB_MAC_H +#define CRYPTLIB_MAC_H + +/*===================================================================================== + * Message Authentication Code (MAC) Primitives + *===================================================================================== + */ + +#if LIBSPDM_SHA256_SUPPORT +/** + * Allocates and initializes one HMAC_CTX context for subsequent HMAC-SHA256 use. + * + * @return Pointer to the HMAC_CTX context that has been initialized. + * If the allocations fails, libspdm_hmac_sha256_new() returns NULL. + **/ +extern void *libspdm_hmac_sha256_new(void); + +/** + * Release the specified HMAC_CTX context. + * + * @param[in] hmac_sha256_ctx Pointer to the HMAC_CTX context to be released. + **/ +extern void libspdm_hmac_sha256_free(void *hmac_sha256_ctx); + +/** + * Set user-supplied key for subsequent use. It must be done before any + * calling to libspdm_hmac_sha256_update(). + * + * If hmac_sha256_ctx is NULL, then return false. + * If this interface is not supported, then return false. + * + * @param[out] hmac_sha256_ctx Pointer to HMAC-SHA256 context. + * @param[in] key Pointer to the user-supplied key. + * @param[in] key_size Key size in bytes. + * + * @retval true The key is set successfully. + * @retval false The key is set unsuccessfully. + * @retval false This interface is not supported. + **/ +extern bool libspdm_hmac_sha256_set_key(void *hmac_sha256_ctx, const uint8_t *key, size_t key_size); + +/** + * Makes a copy of an existing HMAC-SHA256 context. + * + * If hmac_sha256_ctx is NULL, then return false. + * If new_hmac_sha256_ctx is NULL, then return false. + * If this interface is not supported, then return false. + * + * @param[in] hmac_sha256_ctx Pointer to HMAC-SHA256 context being copied. + * @param[out] new_hmac_sha256_ctx Pointer to new HMAC-SHA256 context. + * + * @retval true HMAC-SHA256 context copy succeeded. + * @retval false HMAC-SHA256 context copy failed. + * @retval false This interface is not supported. + **/ +extern bool libspdm_hmac_sha256_duplicate(const void *hmac_sha256_ctx, void *new_hmac_sha256_ctx); + +/** + * Digests the input data and updates HMAC-SHA256 context. + * + * This function performs HMAC-SHA256 digest on a data buffer of the specified size. + * It can be called multiple times to compute the digest of long or discontinuous data streams. + * HMAC-SHA256 context should be initialized by libspdm_hmac_sha256_new(), and should not be + * finalized by libspdm_hmac_sha256_final(). Behavior with invalid context is undefined. + * + * If hmac_sha256_ctx is NULL, then return false. + * If this interface is not supported, then return false. + * + * @param[in, out] hmac_sha256_ctx Pointer to the HMAC-SHA256 context. + * @param[in] data Pointer to the buffer containing the data to be digested. + * @param[in] data_size Size of data buffer in bytes. + * + * @retval true HMAC-SHA256 data digest succeeded. + * @retval false HMAC-SHA256 data digest failed. + * @retval false This interface is not supported. + **/ +extern bool libspdm_hmac_sha256_update(void *hmac_sha256_ctx, const void *data, size_t data_size); + +/** + * Completes computation of the HMAC-SHA256 digest value. + * + * This function completes HMAC-SHA256 hash computation and retrieves the digest value into + * the specified memory. After this function has been called, the HMAC-SHA256 context cannot + * be used again. HMAC-SHA256 context should be initialized by libspdm_hmac_sha256_new(), and should + * not be finalized by libspdm_hmac_sha256_final(). Behavior with invalid HMAC-SHA256 context is + * undefined. + * + * If hmac_sha256_ctx is NULL, then return false. + * If hmac_value is NULL, then return false. + * If this interface is not supported, then return false. + * + * @param[in, out] hmac_sha256_ctx Pointer to the HMAC-SHA256 context. + * @param[out] hmac_value Pointer to a buffer that receives the HMAC-SHA256 digest + * value (32 bytes). + * + * @retval true HMAC-SHA256 digest computation succeeded. + * @retval false HMAC-SHA256 digest computation failed. + * @retval false This interface is not supported. + **/ +extern bool libspdm_hmac_sha256_final(void *hmac_sha256_ctx, uint8_t *hmac_value); + +/** + * Computes the HMAC-SHA256 digest of a input data buffer. + * + * This function performs the HMAC-SHA256 digest of a given data buffer, and places + * the digest value into the specified memory. + * + * If this interface is not supported, then return false. + * + * @param[in] data Pointer to the buffer containing the data to be digested. + * @param[in] data_size Size of data buffer in bytes. + * @param[in] key Pointer to the user-supplied key. + * @param[in] key_size Key size in bytes. + * @param[out] hmac_value Pointer to a buffer that receives the HMAC-SHA256 digest + * value (32 bytes). + * + * @retval true HMAC-SHA256 digest computation succeeded. + * @retval false HMAC-SHA256 digest computation failed. + * @retval false This interface is not supported. + **/ +extern bool libspdm_hmac_sha256_all(const void *data, size_t data_size, + const uint8_t *key, size_t key_size, + uint8_t *hmac_value); +#endif /* LIBSPDM_SHA256_SUPPORT */ + +#if LIBSPDM_SHA384_SUPPORT +/** + * Allocates and initializes one HMAC_CTX context for subsequent HMAC-SHA384 use. + * + * @return Pointer to the HMAC_CTX context that has been initialized. + * If the allocations fails, libspdm_hmac_sha384_new() returns NULL. + **/ +extern void *libspdm_hmac_sha384_new(void); + +/** + * Release the specified HMAC_CTX context. + * + * @param[in] hmac_sha384_ctx Pointer to the HMAC_CTX context to be released. + **/ +extern void libspdm_hmac_sha384_free(void *hmac_sha384_ctx); + +/** + * Set user-supplied key for subsequent use. It must be done before any + * calling to libspdm_hmac_sha384_update(). + * + * If hmac_sha384_ctx is NULL, then return false. + * If this interface is not supported, then return false. + * + * @param[out] hmac_sha384_ctx Pointer to HMAC-SHA384 context. + * @param[in] key Pointer to the user-supplied key. + * @param[in] key_size key size in bytes. + * + * @retval true The key is set successfully. + * @retval false The key is set unsuccessfully. + * @retval false This interface is not supported. + **/ +extern bool libspdm_hmac_sha384_set_key(void *hmac_sha384_ctx, const uint8_t *key, size_t key_size); + +/** + * Makes a copy of an existing HMAC-SHA384 context. + * + * If hmac_sha384_ctx is NULL, then return false. + * If new_hmac_sha384_ctx is NULL, then return false. + * If this interface is not supported, then return false. + * + * @param[in] hmac_sha384_ctx Pointer to HMAC-SHA384 context being copied. + * @param[out] new_hmac_sha384_ctx Pointer to new HMAC-SHA384 context. + * + * @retval true HMAC-SHA384 context copy succeeded. + * @retval false HMAC-SHA384 context copy failed. + * @retval false This interface is not supported. + **/ +extern bool libspdm_hmac_sha384_duplicate(const void *hmac_sha384_ctx, void *new_hmac_sha384_ctx); + +/** + * Digests the input data and updates HMAC-SHA384 context. + * + * This function performs HMAC-SHA384 digest on a data buffer of the specified size. + * It can be called multiple times to compute the digest of long or discontinuous data streams. + * HMAC-SHA384 context should be initialized by libspdm_hmac_sha384_new(), and should not be + * finalized by libspdm_hmac_sha384_final(). Behavior with invalid context is undefined. + * + * If hmac_sha384_ctx is NULL, then return false. + * If this interface is not supported, then return false. + * + * @param[in, out] hmac_sha384_ctx Pointer to the HMAC-SHA384 context. + * @param[in] data Pointer to the buffer containing the data to be digested. + * @param[in] data_size Size of data buffer in bytes. + * + * @retval true HMAC-SHA384 data digest succeeded. + * @retval false HMAC-SHA384 data digest failed. + * @retval false This interface is not supported. + **/ +extern bool libspdm_hmac_sha384_update(void *hmac_sha384_ctx, const void *data, size_t data_size); + +/** + * Completes computation of the HMAC-SHA384 digest value. + * + * This function completes HMAC-SHA384 hash computation and retrieves the digest value into + * the specified memory. After this function has been called, the HMAC-SHA384 context cannot + * be used again. HMAC-SHA384 context should be initialized by libspdm_hmac_sha384_new(), and should + * not be finalized by libspdm_hmac_sha384_final(). Behavior with invalid HMAC-SHA384 context is + * undefined. + * + * If hmac_sha384_ctx is NULL, then return false. + * If hmac_value is NULL, then return false. + * If this interface is not supported, then return false. + * + * @param[in, out] hmac_sha384_ctx Pointer to the HMAC-SHA384 context. + * @param[out] hmac_value Pointer to a buffer that receives the HMAC-SHA384 digest + * value (48 bytes). + * + * @retval true HMAC-SHA384 digest computation succeeded. + * @retval false HMAC-SHA384 digest computation failed. + * @retval false This interface is not supported. + **/ +extern bool libspdm_hmac_sha384_final(void *hmac_sha384_ctx, uint8_t *hmac_value); + +/** + * Computes the HMAC-SHA384 digest of a input data buffer. + * + * This function performs the HMAC-SHA384 digest of a given data buffer, and places + * the digest value into the specified memory. + * + * If this interface is not supported, then return false. + * + * @param[in] data Pointer to the buffer containing the data to be digested. + * @param[in] data_size Size of data buffer in bytes. + * @param[in] key Pointer to the user-supplied key. + * @param[in] key_size Key size in bytes. + * @param[out] hmac_value Pointer to a buffer that receives the HMAC-SHA384 digest + * value (48 bytes). + * + * @retval true HMAC-SHA384 digest computation succeeded. + * @retval false HMAC-SHA384 digest computation failed. + * @retval false This interface is not supported. + **/ +extern bool libspdm_hmac_sha384_all(const void *data, size_t data_size, + const uint8_t *key, size_t key_size, + uint8_t *hmac_value); +#endif /* LIBSPDM_SHA384_SUPPORT */ + +#if LIBSPDM_SHA512_SUPPORT +/** + * Allocates and initializes one HMAC_CTX context for subsequent HMAC-SHA512 use. + * + * @return Pointer to the HMAC_CTX context that has been initialized. + * If the allocations fails, libspdm_hmac_sha512_new() returns NULL. + **/ +extern void *libspdm_hmac_sha512_new(void); + +/** + * Release the specified HMAC_CTX context. + * + * @param[in] hmac_sha512_ctx Pointer to the HMAC_CTX context to be released. + **/ +extern void libspdm_hmac_sha512_free(void *hmac_sha512_ctx); + +/** + * Set user-supplied key for subsequent use. It must be done before any + * calling to libspdm_hmac_sha512_update(). + * + * If hmac_sha512_ctx is NULL, then return false. + * If this interface is not supported, then return false. + * + * @param[out] hmac_sha512_ctx Pointer to HMAC-SHA512 context. + * @param[in] key Pointer to the user-supplied key. + * @param[in] key_size Key size in bytes. + * + * @retval true The key is set successfully. + * @retval false The key is set unsuccessfully. + * @retval false This interface is not supported. + **/ +extern bool libspdm_hmac_sha512_set_key(void *hmac_sha512_ctx, const uint8_t *key, size_t key_size); + +/** + * Makes a copy of an existing HMAC-SHA512 context. + * + * If hmac_sha512_ctx is NULL, then return false. + * If new_hmac_sha512_ctx is NULL, then return false. + * If this interface is not supported, then return false. + * + * @param[in] hmac_sha512_ctx Pointer to HMAC-SHA512 context being copied. + * @param[out] new_hmac_sha512_ctx Pointer to new HMAC-SHA512 context. + * + * @retval true HMAC-SHA512 context copy succeeded. + * @retval false HMAC-SHA512 context copy failed. + * @retval false This interface is not supported. + **/ +extern bool libspdm_hmac_sha512_duplicate(const void *hmac_sha512_ctx, void *new_hmac_sha512_ctx); + +/** + * Digests the input data and updates HMAC-SHA512 context. + * + * This function performs HMAC-SHA512 digest on a data buffer of the specified size. + * It can be called multiple times to compute the digest of long or discontinuous data streams. + * HMAC-SHA512 context should be initialized by libspdm_hmac_sha512_new(), and should not be + * finalized by libspdm_hmac_sha512_final(). Behavior with invalid context is undefined. + * + * If hmac_sha512_ctx is NULL, then return false. + * If this interface is not supported, then return false. + * + * @param[in, out] hmac_sha512_ctx Pointer to the HMAC-SHA512 context. + * @param[in] data Pointer to the buffer containing the data to be digested. + * @param[in] data_size Size of data buffer in bytes. + * + * @retval true HMAC-SHA512 data digest succeeded. + * @retval false HMAC-SHA512 data digest failed. + * @retval false This interface is not supported. + **/ +extern bool libspdm_hmac_sha512_update(void *hmac_sha512_ctx, const void *data, size_t data_size); + +/** + * Completes computation of the HMAC-SHA512 digest value. + * + * This function completes HMAC-SHA512 hash computation and retrieves the digest value into + * the specified memory. After this function has been called, the HMAC-SHA512 context cannot + * be used again. HMAC-SHA512 context should be initialized by libspdm_hmac_sha512_new(), and should + * not be finalized by libspdm_hmac_sha512_final(). Behavior with invalid HMAC-SHA512 context is + * undefined. + * + * If hmac_sha512_ctx is NULL, then return false. + * If hmac_value is NULL, then return false. + * If this interface is not supported, then return false. + * + * @param[in, out] hmac_sha512_ctx Pointer to the HMAC-SHA512 context. + * @param[out] hmac_value Pointer to a buffer that receives the HMAC-SHA512 digest + * value (64 bytes). + * + * @retval true HMAC-SHA512 digest computation succeeded. + * @retval false HMAC-SHA512 digest computation failed. + * @retval false This interface is not supported. + **/ +extern bool libspdm_hmac_sha512_final(void *hmac_sha512_ctx, uint8_t *hmac_value); + +/** + * Computes the HMAC-SHA512 digest of a input data buffer. + * + * This function performs the HMAC-SHA512 digest of a given data buffer, and places + * the digest value into the specified memory. + * + * If this interface is not supported, then return false. + * + * @param[in] data Pointer to the buffer containing the data to be digested. + * @param[in] data_size Size of data buffer in bytes. + * @param[in] key Pointer to the user-supplied key. + * @param[in] key_size Key size in bytes. + * @param[out] hmac_value Pointer to a buffer that receives the HMAC-SHA512 digest + * value (64 bytes). + * + * @retval true HMAC-SHA512 digest computation succeeded. + * @retval false HMAC-SHA512 digest computation failed. + * @retval false This interface is not supported. + * + **/ +extern bool libspdm_hmac_sha512_all(const void *data, size_t data_size, + const uint8_t *key, size_t key_size, + uint8_t *hmac_value); +#endif /* LIBSPDM_SHA512_SUPPORT */ + +#if LIBSPDM_SHA3_256_SUPPORT +/** + * Allocates and initializes one HMAC_CTX context for subsequent HMAC-SHA3-256 use. + * + * @return Pointer to the HMAC_CTX context that has been initialized. + * If the allocations fails, libspdm_hmac_sha3_256_new() returns NULL. + **/ +extern void *libspdm_hmac_sha3_256_new(void); + +/** + * Release the specified HMAC_CTX context. + * + * @param[in] hmac_sha3_256_ctx Pointer to the HMAC_CTX context to be released. + **/ +extern void libspdm_hmac_sha3_256_free(void *hmac_sha3_256_ctx); + +/** + * Set user-supplied key for subsequent use. It must be done before any + * calling to libspdm_hmac_sha3_256_update(). + * + * If hmac_sha3_256_ctx is NULL, then return false. + * + * @param[out] hmac_sha3_256_ctx Pointer to HMAC-SHA3-256 context. + * @param[in] key Pointer to the user-supplied key. + * @param[in] key_size Key size in bytes. + * + * @retval true The key is set successfully. + * @retval false The key is set unsuccessfully. + **/ +extern bool libspdm_hmac_sha3_256_set_key(void *hmac_sha3_256_ctx, + const uint8_t *key, + size_t key_size); + +/** + * Makes a copy of an existing HMAC-SHA3-256 context. + * + * If hmac_sha3_256_ctx is NULL, then return false. + * If new_hmac_sha3_256_ctx is NULL, then return false. + * + * @param[in] hmac_sha3_256_ctx Pointer to HMAC-SHA3-256 context being copied. + * @param[out] new_hmac_sha3_256_ctx Pointer to new HMAC-SHA3-256 context. + * + * @retval true HMAC-SHA3-256 context copy succeeded. + * @retval false HMAC-SHA3-256 context copy failed. + **/ +extern bool libspdm_hmac_sha3_256_duplicate(const void *hmac_sha3_256_ctx, + void *new_hmac_sha3_256_ctx); + +/** + * Digests the input data and updates HMAC-SHA3-256 context. + * + * This function performs HMAC-SHA3-256 digest on a data buffer of the specified size. + * It can be called multiple times to compute the digest of long or discontinuous data streams. + * HMAC-SHA3-256 context should be initialized by libspdm_hmac_sha3_256_new(), and should not be + * finalized by libspdm_hmac_sha3_256_final(). Behavior with invalid context is undefined. + * + * If hmac_sha3_256_ctx is NULL, then return false. + * + * @param[in, out] hmac_sha3_256_ctx Pointer to the HMAC-SHA3-256 context. + * @param[in] data Pointer to the buffer containing the data to be digested. + * @param[in] data_size Size of data buffer in bytes. + * + * @retval true HMAC-SHA3-256 data digest succeeded. + * @retval false HMAC-SHA3-256 data digest failed. + **/ +extern bool libspdm_hmac_sha3_256_update(void *hmac_sha3_256_ctx, + const void *data, size_t data_size); + +/** + * Completes computation of the HMAC-SHA3-256 digest value. + * + * This function completes HMAC-SHA3-256 hash computation and retrieves the digest value into + * the specified memory. After this function has been called, the HMAC-SHA3-256 context cannot + * be used again. HMAC-SHA3-256 context should be initialized by libspdm_hmac_sha3_256_new(), and + * should not be finalized by libspdm_hmac_sha3_256_final(). Behavior with invalid HMAC-SHA3-256 + * context is undefined. + * + * If hmac_sha3_256_ctx is NULL, then return false. + * If hmac_value is NULL, then return false. + * + * @param[in, out] hmac_sha3_256_ctx Pointer to the HMAC-SHA3-256 context. + * @param[out] hmac_value Pointer to a buffer that receives the HMAC-SHA3-256 digest + * value (32 bytes). + * + * @retval true HMAC-SHA3-256 digest computation succeeded. + * @retval false HMAC-SHA3-256 digest computation failed. + **/ +extern bool libspdm_hmac_sha3_256_final(void *hmac_sha3_256_ctx, uint8_t *hmac_value); + +/** + * Computes the HMAC-SHA3-256 digest of a input data buffer. + * + * This function performs the HMAC-SHA3-256 digest of a given data buffer, and places + * the digest value into the specified memory. + * + * If this interface is not supported, then return false. + * + * @param[in] data Pointer to the buffer containing the data to be digested. + * @param[in] data_size Size of data buffer in bytes. + * @param[in] key Pointer to the user-supplied key. + * @param[in] key_size Key size in bytes. + * @param[out] hmac_value Pointer to a buffer that receives the HMAC-SHA3-256 digest + * value (32 bytes). + * + * @retval true HMAC-SHA3-256 digest computation succeeded. + * @retval false HMAC-SHA3-256 digest computation failed. + * @retval false This interface is not supported. + **/ +extern bool libspdm_hmac_sha3_256_all(const void *data, size_t data_size, + const uint8_t *key, size_t key_size, + uint8_t *hmac_value); +#endif /* LIBSPDM_SHA3_256_SUPPORT */ + +#if LIBSPDM_SHA3_384_SUPPORT +/** + * Allocates and initializes one HMAC_CTX context for subsequent HMAC-SHA3-384 use. + * + * @return Pointer to the HMAC_CTX context that has been initialized. + * If the allocations fails, libspdm_hmac_sha3_384_new() returns NULL. + **/ +extern void *libspdm_hmac_sha3_384_new(void); + +/** + * Release the specified HMAC_CTX context. + * + * @param[in] hmac_sha3_384_ctx Pointer to the HMAC_CTX context to be released. + **/ +extern void libspdm_hmac_sha3_384_free(void *hmac_sha3_384_ctx); + +/** + * Set user-supplied key for subsequent use. It must be done before any + * calling to libspdm_hmac_sha3_384_update(). + * + * If hmac_sha3_384_ctx is NULL, then return false. + * If this interface is not supported, then return false. + * + * @param[out] hmac_sha3_384_ctx Pointer to HMAC-SHA3-384 context. + * @param[in] key Pointer to the user-supplied key. + * @param[in] key_size Key size in bytes. + * + * @retval true The key is set successfully. + * @retval false The key is set unsuccessfully. + * @retval false This interface is not supported. + **/ +extern bool libspdm_hmac_sha3_384_set_key(void *hmac_sha3_384_ctx, + const uint8_t *key, + size_t key_size); + +/** + * Makes a copy of an existing HMAC-SHA3-384 context. + * + * If hmac_sha3_384_ctx is NULL, then return false. + * If new_hmac_sha3_384_ctx is NULL, then return false. + * If this interface is not supported, then return false. + * + * @param[in] hmac_sha3_384_ctx Pointer to HMAC-SHA3-384 context being copied. + * @param[out] new_hmac_sha3_384_ctx Pointer to new HMAC-SHA3-384 context. + * + * @retval true HMAC-SHA3-384 context copy succeeded. + * @retval false HMAC-SHA3-384 context copy failed. + * @retval false This interface is not supported. + **/ +extern bool libspdm_hmac_sha3_384_duplicate(const void *hmac_sha3_384_ctx, + void *new_hmac_sha3_384_ctx); + +/** + * Digests the input data and updates HMAC-SHA3-384 context. + * + * This function performs HMAC-SHA3-384 digest on a data buffer of the specified size. + * It can be called multiple times to compute the digest of long or discontinuous data streams. + * HMAC-SHA3-384 context should be initialized by libspdm_hmac_sha3_384_new(), and should not be + * finalized by libspdm_hmac_sha3_384_final(). Behavior with invalid context is undefined. + * + * If hmac_sha3_384_ctx is NULL, then return false. + * If this interface is not supported, then return false. + * + * @param[in, out] hmac_sha3_384_ctx Pointer to the HMAC-SHA3-384 context. + * @param[in] data Pointer to the buffer containing the data to be digested. + * @param[in] data_size Size of data buffer in bytes. + * + * @retval true HMAC-SHA3-384 data digest succeeded. + * @retval false HMAC-SHA3-384 data digest failed. + * @retval false This interface is not supported. + **/ +extern bool libspdm_hmac_sha3_384_update(void *hmac_sha3_384_ctx, const void *data, + size_t data_size); + +/** + * Completes computation of the HMAC-SHA3-384 digest value. + * + * This function completes HMAC-SHA3-384 hash computation and retrieves the digest value into + * the specified memory. After this function has been called, the HMAC-SHA3-384 context cannot + * be used again. HMAC-SHA3-384 context should be initialized by libspdm_hmac_sha3_384_new(), and + * should not be finalized by libspdm_hmac_sha3_384_final(). Behavior with invalid HMAC-SHA3-384 + * context is undefined. + * + * If hmac_sha3_384_ctx is NULL, then return false. + * If hmac_value is NULL, then return false. + * If this interface is not supported, then return false. + * + * @param[in, out] hmac_sha3_384_ctx Pointer to the HMAC-SHA3-384 context. + * @param[out] hmac_value Pointer to a buffer that receives the HMAC-SHA3-384 digest + * value (48 bytes). + * + * @retval true HMAC-SHA3-384 digest computation succeeded. + * @retval false HMAC-SHA3-384 digest computation failed. + * @retval false This interface is not supported. + **/ +extern bool libspdm_hmac_sha3_384_final(void *hmac_sha3_384_ctx, uint8_t *hmac_value); + +/** + * Computes the HMAC-SHA3-384 digest of a input data buffer. + * + * This function performs the HMAC-SHA3-384 digest of a given data buffer, and places + * the digest value into the specified memory. + * + * If this interface is not supported, then return false. + * + * @param[in] data Pointer to the buffer containing the data to be digested. + * @param[in] data_size Size of data buffer in bytes. + * @param[in] key Pointer to the user-supplied key. + * @param[in] key_size Key size in bytes. + * @param[out] hmac_value Pointer to a buffer that receives the HMAC-SHA3-384 digest + * value (48 bytes). + * + * @retval true HMAC-SHA3-384 digest computation succeeded. + * @retval false HMAC-SHA3-384 digest computation failed. + * @retval false This interface is not supported. + **/ +extern bool libspdm_hmac_sha3_384_all(const void *data, size_t data_size, + const uint8_t *key, size_t key_size, + uint8_t *hmac_value); +#endif /* LIBSPDM_SHA3_384_SUPPORT */ + +#if LIBSPDM_SHA3_512_SUPPORT +/** + * Allocates and initializes one HMAC_CTX context for subsequent HMAC-SHA3-512 use. + * + * @return Pointer to the HMAC_CTX context that has been initialized. + * If the allocations fails, libspdm_hmac_sha3_512_new() returns NULL. + **/ +extern void *libspdm_hmac_sha3_512_new(void); + +/** + * Release the specified HMAC_CTX context. + * + * @param[in] hmac_sha3_512_ctx Pointer to the HMAC_CTX context to be released. + **/ +extern void libspdm_hmac_sha3_512_free(void *hmac_sha3_512_ctx); + +/** + * Set user-supplied key for subsequent use. It must be done before any + * calling to libspdm_hmac_sha3_512_update(). + * + * If hmac_sha3_512_ctx is NULL, then return false. + * If this interface is not supported, then return false. + * + * @param[out] hmac_sha3_512_ctx Pointer to HMAC-SHA3-512 context. + * @param[in] key Pointer to the user-supplied key. + * @param[in] key_size Key size in bytes. + * + * @retval true The key is set successfully. + * @retval false The key is set unsuccessfully. + * @retval false This interface is not supported. + **/ +extern bool libspdm_hmac_sha3_512_set_key(void *hmac_sha3_512_ctx, + const uint8_t *key, + size_t key_size); + +/** + * Makes a copy of an existing HMAC-SHA3-512 context. + * + * If hmac_sha3_512_ctx is NULL, then return false. + * If new_hmac_sha3_512_ctx is NULL, then return false. + * If this interface is not supported, then return false. + * + * @param[in] hmac_sha3_512_ctx Pointer to HMAC-SHA3-512 context being copied. + * @param[out] new_hmac_sha3_512_ctx Pointer to new HMAC-SHA3-512 context. + * + * @retval true HMAC-SHA3-512 context copy succeeded. + * @retval false HMAC-SHA3-512 context copy failed. + * @retval false This interface is not supported. + **/ +extern bool libspdm_hmac_sha3_512_duplicate(const void *hmac_sha3_512_ctx, + void *new_hmac_sha3_512_ctx); + +/** + * Digests the input data and updates HMAC-SHA3-512 context. + * + * This function performs HMAC-SHA3-512 digest on a data buffer of the specified size. + * It can be called multiple times to compute the digest of long or discontinuous data streams. + * HMAC-SHA3-512 context should be initialized by libspdm_hmac_sha3_512_new(), and should not be + * finalized by libspdm_hmac_sha3_512_final(). Behavior with invalid context is undefined. + * + * If hmac_sha3_512_ctx is NULL, then return false. + * If this interface is not supported, then return false. + * + * @param[in, out] hmac_sha3_512_ctx Pointer to the HMAC-SHA3-512 context. + * @param[in] data Pointer to the buffer containing the data to be digested. + * @param[in] data_size Size of data buffer in bytes. + * + * @retval true HMAC-SHA3-512 data digest succeeded. + * @retval false HMAC-SHA3-512 data digest failed. + * @retval false This interface is not supported. + **/ +extern bool libspdm_hmac_sha3_512_update(void *hmac_sha3_512_ctx, + const void *data, size_t data_size); + +/** + * Completes computation of the HMAC-SHA3-512 digest value. + * + * This function completes HMAC-SHA3-512 hash computation and retrieves the digest value into + * the specified memory. After this function has been called, the HMAC-SHA3-512 context cannot + * be used again. HMAC-SHA3-512 context should be initialized by libspdm_hmac_sha3_512_new(), and + * should not be finalized by libspdm_hmac_sha3_512_final(). Behavior with invalid HMAC-SHA3-512 + * context is undefined. + * + * If hmac_sha3_512_ctx is NULL, then return false. + * If hmac_value is NULL, then return false. + * If this interface is not supported, then return false. + * + * @param[in, out] hmac_sha3_512_ctx Pointer to the HMAC-SHA3-512 context. + * @param[out] hmac_value Pointer to a buffer that receives the HMAC-SHA3-512 digest + * value (64 bytes). + * + * @retval true HMAC-SHA3-512 digest computation succeeded. + * @retval false HMAC-SHA3-512 digest computation failed. + * @retval false This interface is not supported. + **/ +extern bool libspdm_hmac_sha3_512_final(void *hmac_sha3_512_ctx, uint8_t *hmac_value); + +/** + * Computes the HMAC-SHA3-512 digest of a input data buffer. + * + * This function performs the HMAC-SHA3-512 digest of a given data buffer, and places + * the digest value into the specified memory. + * + * If this interface is not supported, then return false. + * + * @param[in] data Pointer to the buffer containing the data to be digested. + * @param[in] data_size Size of data buffer in bytes. + * @param[in] key Pointer to the user-supplied key. + * @param[in] key_size Key size in bytes. + * @param[out] hmac_value Pointer to a buffer that receives the HMAC-SHA3-512 digest + * value (64 bytes). + * + * @retval true HMAC-SHA3-512 digest computation succeeded. + * @retval false HMAC-SHA3-512 digest computation failed. + * @retval false This interface is not supported. + **/ +extern bool libspdm_hmac_sha3_512_all(const void *data, size_t data_size, + const uint8_t *key, size_t key_size, + uint8_t *hmac_value); +#endif /* LIBSPDM_SHA3_512_SUPPORT */ + +#if LIBSPDM_SM3_256_SUPPORT +/** + * Allocates and initializes one HMAC_CTX context for subsequent HMAC-SM3-256 use. + * + * @return Pointer to the HMAC_CTX context that has been initialized. + * If the allocations fails, libspdm_hmac_sm3_256_new() returns NULL. + **/ +extern void *libspdm_hmac_sm3_256_new(void); + +/** + * Release the specified HMAC_CTX context. + * + * @param[in] hmac_sm3_256_ctx Pointer to the HMAC_CTX context to be released. + **/ +extern void libspdm_hmac_sm3_256_free(void *hmac_sm3_256_ctx); + +/** + * Set user-supplied key for subsequent use. It must be done before any + * calling to libspdm_hmac_sm3_256_update(). + * + * If hmac_sm3_256_ctx is NULL, then return false. + * + * @param[out] hmac_sm3_256_ctx Pointer to HMAC-SM3-256 context. + * @param[in] key Pointer to the user-supplied key. + * @param[in] key_size Key size in bytes. + * + * @retval true The key is set successfully. + * @retval false The key is set unsuccessfully. + **/ +extern bool libspdm_hmac_sm3_256_set_key(void *hmac_sm3_256_ctx, + const uint8_t *key, size_t key_size); + +/** + * Makes a copy of an existing HMAC-SM3-256 context. + * + * If hmac_sm3_256_ctx is NULL, then return false. + * If new_hmac_sm3_256_ctx is NULL, then return false. + * + * @param[in] hmac_sm3_256_ctx Pointer to HMAC-SM3-256 context being copied. + * @param[out] new_hmac_sm3_256_ctx Pointer to new HMAC-SM3-256 context. + * + * @retval true HMAC-SM3-256 context copy succeeded. + * @retval false HMAC-SM3-256 context copy failed. + **/ +extern bool libspdm_hmac_sm3_256_duplicate(const void *hmac_sm3_256_ctx, + void *new_hmac_sm3_256_ctx); + +/** + * Digests the input data and updates HMAC-SM3-256 context. + * + * This function performs HMAC-SM3-256 digest on a data buffer of the specified size. + * It can be called multiple times to compute the digest of long or discontinuous data streams. + * HMAC-SM3-256 context should be initialized by libspdm_hmac_sm3_256_new(), and should not be + * finalized by libspdm_hmac_sm3_256_final(). Behavior with invalid context is undefined. + * + * If hmac_sm3_256_ctx is NULL, then return false. + * + * @param[in, out] hmac_sm3_256_ctx Pointer to the HMAC-SM3-256 context. + * @param[in] data Pointer to the buffer containing the data to be digested. + * @param[in] data_size Size of data buffer in bytes. + * + * @retval true HMAC-SM3-256 data digest succeeded. + * @retval false HMAC-SM3-256 data digest failed. + **/ +extern bool libspdm_hmac_sm3_256_update(void *hmac_sm3_256_ctx, const void *data, size_t data_size); + +/** + * Completes computation of the HMAC-SM3-256 digest value. + * + * This function completes HMAC-SM3-256 hash computation and retrieves the digest value into + * the specified memory. After this function has been called, the HMAC-SM3-256 context cannot + * be used again. HMAC-SM3-256 context should be initialized by libspdm_hmac_sm3_256_new(), and + * should not be finalized by libspdm_hmac_sm3_256_final(). Behavior with invalid HMAC-SM3-256 + * context is undefined. + * + * If hmac_sm3_256_ctx is NULL, then return false. + * If hmac_value is NULL, then return false. + * + * @param[in, out] hmac_sm3_256_ctx Pointer to the HMAC-SM3-256 context. + * @param[out] hmac_value Pointer to a buffer that receives the HMAC-SM3-256 digest + * value (32 bytes). + * + * @retval true HMAC-SM3-256 digest computation succeeded. + * @retval false HMAC-SM3-256 digest computation failed. + **/ +extern bool libspdm_hmac_sm3_256_final(void *hmac_sm3_256_ctx, uint8_t *hmac_value); + +/** + * Computes the HMAC-SM3-256 digest of a input data buffer. + * + * This function performs the HMAC-SM3-256 digest of a given data buffer, and places + * the digest value into the specified memory. + * + * If this interface is not supported, then return false. + * + * @param[in] data Pointer to the buffer containing the data to be digested. + * @param[in] data_size Size of data buffer in bytes. + * @param[in] key Pointer to the user-supplied key. + * @param[in] key_size Key size in bytes. + * @param[out] hmac_value Pointer to a buffer that receives the HMAC-SM3-256 digest + * value (32 bytes). + * + * @retval true HMAC-SM3-256 digest computation succeeded. + * @retval false HMAC-SM3-256 digest computation failed. + * @retval false This interface is not supported. + **/ +extern bool libspdm_hmac_sm3_256_all(const void *data, size_t data_size, + const uint8_t *key, size_t key_size, + uint8_t *hmac_value); +#endif /* LIBSPDM_SM3_256_SUPPORT */ + +#endif /* CRYPTLIB_MAC_H */ diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/kernel-open/nvidia/hal/library/cryptlib/cryptlib_rng.h nvidia-open-gpu-kernel-modules-535.161.08/kernel-open/nvidia/hal/library/cryptlib/cryptlib_rng.h --- nvidia-open-gpu-kernel-modules-525.147.05/kernel-open/nvidia/hal/library/cryptlib/cryptlib_rng.h 1970-01-01 00:00:00.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/kernel-open/nvidia/hal/library/cryptlib/cryptlib_rng.h 2024-03-05 22:25:37.000000000 +0000 @@ -0,0 +1,30 @@ +/** + * Copyright Notice: + * Copyright 2021-2022 DMTF. All rights reserved. + * License: BSD 3-Clause License. For full text see link: https://github.com/DMTF/libspdm/blob/main/LICENSE.md + **/ + +#ifndef CRYPTLIB_RNG_H +#define CRYPTLIB_RNG_H + +/*===================================================================================== + * Random Number Generation Primitive + *=====================================================================================*/ + +/** + * Generates a random byte stream of the specified size. If initialization, testing, or seeding of + * the (pseudo)random number generator is required it should be done before this function is called. + * + * If output is NULL, then return false. + * If this interface is not supported, then return false. + * + * @param[out] output Pointer to buffer to receive random value. + * @param[in] size Size of random bytes to generate. + * + * @retval true Random byte stream generated successfully. + * @retval false Generation of random byte stream failed. + * @retval false This interface is not supported. + **/ +extern bool libspdm_random_bytes(uint8_t *output, size_t size); + +#endif /* CRYPTLIB_RNG_H */ diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/kernel-open/nvidia/hal/library/cryptlib/cryptlib_rsa.h nvidia-open-gpu-kernel-modules-535.161.08/kernel-open/nvidia/hal/library/cryptlib/cryptlib_rsa.h --- nvidia-open-gpu-kernel-modules-525.147.05/kernel-open/nvidia/hal/library/cryptlib/cryptlib_rsa.h 1970-01-01 00:00:00.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/kernel-open/nvidia/hal/library/cryptlib/cryptlib_rsa.h 2024-03-05 22:25:37.000000000 +0000 @@ -0,0 +1,264 @@ +/** + * Copyright Notice: + * Copyright 2021-2022 DMTF. All rights reserved. + * License: BSD 3-Clause License. For full text see link: https://github.com/DMTF/libspdm/blob/main/LICENSE.md + **/ + +#ifndef CRYPTLIB_RSA_H +#define CRYPTLIB_RSA_H + +/*===================================================================================== + * RSA Cryptography Primitives + *===================================================================================== + */ + +#if (LIBSPDM_RSA_SSA_SUPPORT) || (LIBSPDM_RSA_PSS_SUPPORT) +/* RSA key Tags Definition used in libspdm_rsa_set_key() function for key component + * identification. + */ +typedef enum { + LIBSPDM_RSA_KEY_N, /*< RSA public Modulus (N)*/ + LIBSPDM_RSA_KEY_E, /*< RSA public exponent (e)*/ + LIBSPDM_RSA_KEY_D, /*< RSA Private exponent (d)*/ + LIBSPDM_RSA_KEY_P, /*< RSA secret prime factor of Modulus (p)*/ + LIBSPDM_RSA_KEY_Q, /*< RSA secret prime factor of Modules (q)*/ + LIBSPDM_RSA_KEY_DP, /*< p's CRT exponent (== d mod (p - 1))*/ + LIBSPDM_RSA_KEY_DQ, /*< q's CRT exponent (== d mod (q - 1))*/ + LIBSPDM_RSA_KEY_Q_INV /*< The CRT coefficient (== 1/q mod p)*/ +} libspdm_rsa_key_tag_t; + +/** + * Allocates and initializes one RSA context for subsequent use. + * + * @return Pointer to the RSA context that has been initialized. + * If the allocations fails, libspdm_rsa_new() returns NULL. + **/ +extern void *libspdm_rsa_new(void); + +/** + * Release the specified RSA context. + * + * If rsa_context is NULL, then return false. + * + * @param[in] rsa_context Pointer to the RSA context to be released. + **/ +extern void libspdm_rsa_free(void *rsa_context); + +/** + * Sets the tag-designated key component into the established RSA context. + * + * This function sets the tag-designated RSA key component into the established + * RSA context from the user-specified non-negative integer (octet string format + * represented in RSA PKCS#1). + * If big_number is NULL, then the specified key component in RSA context is cleared. + * If rsa_context is NULL, then return false. + * + * @param[in, out] rsa_context Pointer to RSA context being set. + * @param[in] key_tag tag of RSA key component being set. + * @param[in] big_number Pointer to octet integer buffer. + * If NULL, then the specified key component in RSA + * context is cleared. + * @param[in] bn_size Size of big number buffer in bytes. + * If big_number is NULL, then it is ignored. + * + * @retval true RSA key component was set successfully. + * @retval false Invalid RSA key component tag. + **/ +extern bool libspdm_rsa_set_key(void *rsa_context, const libspdm_rsa_key_tag_t key_tag, + const uint8_t *big_number, size_t bn_size); + +/** + * Gets the tag-designated RSA key component from the established RSA context. + * + * This function retrieves the tag-designated RSA key component from the + * established RSA context as a non-negative integer (octet string format + * represented in RSA PKCS#1). + * If specified key component has not been set or has been cleared, then returned + * bn_size is set to 0. + * If the big_number buffer is too small to hold the contents of the key, false + * is returned and bn_size is set to the required buffer size to obtain the key. + * + * If rsa_context is NULL, then return false. + * If bn_size is NULL, then return false. + * If bn_size is large enough but big_number is NULL, then return false. + * If this interface is not supported, then return false. + * + * @param[in, out] rsa_context Pointer to RSA context being set. + * @param[in] key_tag Tag of RSA key component being set. + * @param[out] big_number Pointer to octet integer buffer. + * @param[in, out] bn_size On input, the size of big number buffer in bytes. + * On output, the size of data returned in big number buffer in bytes. + * + * @retval true RSA key component was retrieved successfully. + * @retval false Invalid RSA key component tag. + * @retval false bn_size is too small. + * @retval false This interface is not supported. + **/ +extern bool libspdm_rsa_get_key(void *rsa_context, const libspdm_rsa_key_tag_t key_tag, + uint8_t *big_number, size_t *bn_size); + +/** + * Generates RSA key components. + * + * This function generates RSA key components. It takes RSA public exponent E and + * length in bits of RSA modulus N as input, and generates all key components. + * If public_exponent is NULL, the default RSA public exponent (0x10001) will be used. + * + * If rsa_context is NULL, then return false. + * If this interface is not supported, then return false. + * + * @param[in, out] rsa_context Pointer to RSA context being set. + * @param[in] modulus_length Length of RSA modulus N in bits. + * @param[in] public_exponent Pointer to RSA public exponent. + * @param[in] public_exponent_size Size of RSA public exponent buffer in bytes. + * + * @retval true RSA key component was generated successfully. + * @retval false Invalid RSA key component tag. + * @retval false This interface is not supported. + **/ +extern bool libspdm_rsa_generate_key(void *rsa_context, size_t modulus_length, + const uint8_t *public_exponent, + size_t public_exponent_size); + +/** + * Validates key components of RSA context. + * NOTE: This function performs integrity checks on all the RSA key material, so + * the RSA key structure must contain all the private key data. + * + * This function validates key components of RSA context in following aspects: + * - Whether p is a prime + * - Whether q is a prime + * - Whether n = p * q + * - Whether d*e = 1 mod lcm(p-1,q-1) + * + * If rsa_context is NULL, then return false. + * If this interface is not supported, then return false. + * + * @param[in] rsa_context Pointer to RSA context to check. + * + * @retval true RSA key components are valid. + * @retval false RSA key components are not valid. + * @retval false This interface is not supported. + **/ +extern bool libspdm_rsa_check_key(void *rsa_context); +#endif /* (LIBSPDM_RSA_SSA_SUPPORT) || (LIBSPDM_RSA_PSS_SUPPORT) */ + +#if LIBSPDM_RSA_SSA_SUPPORT +/** + * Carries out the RSA-SSA signature generation with EMSA-PKCS1-v1_5 encoding scheme. + * + * This function carries out the RSA-SSA signature generation with EMSA-PKCS1-v1_5 encoding scheme + * defined in RSA PKCS#1. If the signature buffer is too small to hold the contents of signature, + * false is returned and sig_size is set to the required buffer size to obtain the signature. + * + * If rsa_context is NULL, then return false. + * If message_hash is NULL, then return false. + * If hash_size need match the hash_nid. hash_nid could be SHA256, SHA384, SHA512, SHA3_256, + * SHA3_384, SHA3_512. + * If sig_size is large enough but signature is NULL, then return false. + * If this interface is not supported, then return false. + * + * @param[in] rsa_context Pointer to RSA context for signature generation. + * @param[in] hash_nid hash NID + * @param[in] message_hash Pointer to octet message hash to be signed. + * @param[in] hash_size Size of the message hash in bytes. + * @param[out] signature Pointer to buffer to receive RSA PKCS1-v1_5 signature. + * @param[in, out] sig_size On input, the size of signature buffer in bytes. + * On output, the size of data returned in signature buffer in bytes. + * + * @retval true signature successfully generated in PKCS1-v1_5. + * @retval false signature generation failed. + * @retval false sig_size is too small. + * @retval false This interface is not supported. + **/ +extern bool libspdm_rsa_pkcs1_sign_with_nid(void *rsa_context, size_t hash_nid, + const uint8_t *message_hash, + size_t hash_size, uint8_t *signature, + size_t *sig_size); + +/** + * Verifies the RSA-SSA signature with EMSA-PKCS1-v1_5 encoding scheme defined in RSA PKCS#1. + * + * If rsa_context is NULL, then return false. + * If message_hash is NULL, then return false. + * If signature is NULL, then return false. + * If hash_size need match the hash_nid. hash_nid could be SHA256, SHA384, SHA512, SHA3_256, + * SHA3_384, SHA3_512. + * + * @param[in] rsa_context Pointer to RSA context for signature verification. + * @param[in] hash_nid hash NID + * @param[in] message_hash Pointer to octet message hash to be checked. + * @param[in] hash_size Size of the message hash in bytes. + * @param[in] signature Pointer to RSA PKCS1-v1_5 signature to be verified. + * @param[in] sig_size Size of signature in bytes. + * + * @retval true Valid signature encoded in PKCS1-v1_5. + * @retval false Invalid signature or invalid RSA context. + **/ +extern bool libspdm_rsa_pkcs1_verify_with_nid(void *rsa_context, size_t hash_nid, + const uint8_t *message_hash, + size_t hash_size, const uint8_t *signature, + size_t sig_size); +#endif /* LIBSPDM_RSA_SSA_SUPPORT */ + +#if LIBSPDM_RSA_PSS_SUPPORT +/** + * Carries out the RSA-SSA signature generation with EMSA-PSS encoding scheme. + * + * This function carries out the RSA-SSA signature generation with EMSA-PSS encoding scheme defined + * in RSA PKCS#1 v2.2. + * + * The salt length is same as digest length. + * + * If the signature buffer is too small to hold the contents of signature, false + * is returned and sig_size is set to the required buffer size to obtain the signature. + * + * If rsa_context is NULL, then return false. + * If message_hash is NULL, then return false. + * If hash_size need match the hash_nid. nid could be SHA256, SHA384, SHA512, SHA3_256, SHA3_384, + * SHA3_512. + * If sig_size is large enough but signature is NULL, then return false. + * + * @param[in] rsa_context Pointer to RSA context for signature generation. + * @param[in] hash_nid hash NID + * @param[in] message_hash Pointer to octet message hash to be signed. + * @param[in] hash_size Size of the message hash in bytes. + * @param[out] signature Pointer to buffer to receive RSA-SSA PSS signature. + * @param[in, out] sig_size On input, the size of signature buffer in bytes. + * On output, the size of data returned in signature buffer in bytes. + * + * @retval true signature successfully generated in RSA-SSA PSS. + * @retval false signature generation failed. + * @retval false sig_size is too small. + **/ +extern bool libspdm_rsa_pss_sign(void *rsa_context, size_t hash_nid, + const uint8_t *message_hash, size_t hash_size, + uint8_t *signature, size_t *sig_size); + +/** + * Verifies the RSA-SSA signature with EMSA-PSS encoding scheme defined in + * RSA PKCS#1 v2.2. + * + * The salt length is same as digest length. + * + * If rsa_context is NULL, then return false. + * If message_hash is NULL, then return false. + * If signature is NULL, then return false. + * If hash_size need match the hash_nid. nid could be SHA256, SHA384, SHA512, SHA3_256, SHA3_384, + * SHA3_512. + * + * @param[in] rsa_context Pointer to RSA context for signature verification. + * @param[in] hash_nid hash NID + * @param[in] message_hash Pointer to octet message hash to be checked. + * @param[in] hash_size Size of the message hash in bytes. + * @param[in] signature Pointer to RSA-SSA PSS signature to be verified. + * @param[in] sig_size Size of signature in bytes. + * + * @retval true Valid signature encoded in RSA-SSA PSS. + * @retval false Invalid signature or invalid RSA context. + **/ +extern bool libspdm_rsa_pss_verify(void *rsa_context, size_t hash_nid, + const uint8_t *message_hash, size_t hash_size, + const uint8_t *signature, size_t sig_size); +#endif /* LIBSPDM_RSA_PSS_SUPPORT */ +#endif /* CRYPTLIB_RSA_H */ diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/kernel-open/nvidia/hal/library/cryptlib/cryptlib_sm2.h nvidia-open-gpu-kernel-modules-535.161.08/kernel-open/nvidia/hal/library/cryptlib/cryptlib_sm2.h --- nvidia-open-gpu-kernel-modules-525.147.05/kernel-open/nvidia/hal/library/cryptlib/cryptlib_sm2.h 1970-01-01 00:00:00.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/kernel-open/nvidia/hal/library/cryptlib/cryptlib_sm2.h 2024-03-05 22:25:37.000000000 +0000 @@ -0,0 +1,194 @@ +/** + * Copyright Notice: + * Copyright 2021-2022 DMTF. All rights reserved. + * License: BSD 3-Clause License. For full text see link: https://github.com/DMTF/libspdm/blob/main/LICENSE.md + **/ + +#ifndef CRYPTLIB_SM2_H +#define CRYPTLIB_SM2_H + +/*===================================================================================== + * Shang-Mi2 Primitives + *=====================================================================================*/ + +#if LIBSPDM_SM2_DSA_SUPPORT +/** + * Allocates and Initializes one Shang-Mi2 context for subsequent use. + * + * @param nid cipher NID + * + * @return Pointer to the Shang-Mi2 context that has been initialized. + * If the allocations fails, sm2_new_by_nid() returns NULL. + **/ +extern void *libspdm_sm2_dsa_new_by_nid(size_t nid); + +/** + * Release the specified sm2 context. + * + * @param[in] sm2_context Pointer to the sm2 context to be released. + **/ +extern void libspdm_sm2_dsa_free(void *sm2_context); + +/** + * Carries out the SM2 signature, based upon GB/T 32918.2-2016: SM2 - Part2. + * + * This function carries out the SM2 signature. + * If the signature buffer is too small to hold the contents of signature, false + * is returned and sig_size is set to the required buffer size to obtain the signature. + * + * If sm2_context is NULL, then return false. + * If message is NULL, then return false. + * hash_nid must be SM3_256. + * If sig_size is large enough but signature is NULL, then return false. + * + * The id_a_size must be smaller than 2^16-1. + * The sig_size is 64. first 32-byte is R, second 32-byte is S. + * + * @param[in] sm2_context Pointer to sm2 context for signature generation. + * @param[in] hash_nid hash NID + * @param[in] id_a The ID-A of the signing context. + * @param[in] id_a_size Size of ID-A signing context. + * @param[in] message Pointer to octet message to be signed (before hash). + * @param[in] size Size of the message in bytes. + * @param[out] signature Pointer to buffer to receive SM2 signature. + * @param[in, out] sig_size On input, the size of signature buffer in bytes. + * On output, the size of data returned in signature buffer in bytes. + * + * @retval true signature successfully generated in SM2. + * @retval false signature generation failed. + * @retval false sig_size is too small. + **/ +extern bool libspdm_sm2_dsa_sign(const void *sm2_context, size_t hash_nid, + const uint8_t *id_a, size_t id_a_size, + const uint8_t *message, size_t size, + uint8_t *signature, size_t *sig_size); + +/** + * Verifies the SM2 signature, based upon GB/T 32918.2-2016: SM2 - Part2. + * + * If sm2_context is NULL, then return false. + * If message is NULL, then return false. + * If signature is NULL, then return false. + * hash_nid must be SM3_256. + * + * The id_a_size must be smaller than 2^16-1. + * The sig_size is 64. first 32-byte is R, second 32-byte is S. + * + * @param[in] sm2_context Pointer to SM2 context for signature verification. + * @param[in] hash_nid hash NID + * @param[in] id_a The ID-A of the signing context. + * @param[in] id_a_size Size of ID-A signing context. + * @param[in] message Pointer to octet message to be checked (before hash). + * @param[in] size Size of the message in bytes. + * @param[in] signature Pointer to SM2 signature to be verified. + * @param[in] sig_size Size of signature in bytes. + * + * @retval true Valid signature encoded in SM2. + * @retval false Invalid signature or invalid sm2 context. + * + **/ +extern bool libspdm_sm2_dsa_verify(const void *sm2_context, size_t hash_nid, + const uint8_t *id_a, size_t id_a_size, + const uint8_t *message, size_t size, + const uint8_t *signature, size_t sig_size); +#endif /* LIBSPDM_SM2_DSA_SUPPORT */ + +#if LIBSPDM_SM2_KEY_EXCHANGE_SUPPORT +/** + * Allocates and Initializes one Shang-Mi2 context for subsequent use. + * + * @param nid cipher NID + * + * @return Pointer to the Shang-Mi2 context that has been initialized. + * If the allocations fails, sm2_new_by_nid() returns NULL. + **/ +extern void *libspdm_sm2_key_exchange_new_by_nid(size_t nid); + +/** + * Release the specified sm2 context. + * + * @param[in] sm2_context Pointer to the sm2 context to be released. + * + **/ +extern void libspdm_sm2_key_exchange_free(void *sm2_context); + +/** + * Initialize the specified sm2 context. + * + * @param[in] sm2_context Pointer to the sm2 context to be released. + * @param[in] hash_nid hash NID, only SM3 is valid. + * @param[in] id_a The ID-A of the key exchange context. + * @param[in] id_a_size Size of ID-A key exchange context. + * @param[in] id_b The ID-B of the key exchange context. + * @param[in] id_b_size Size of ID-B key exchange context. + * @param[in] is_initiator If the caller is initiator. + * + * @retval true sm2 context is initialized. + * @retval false sm2 context is not initialized. + **/ +extern bool libspdm_sm2_key_exchange_init(const void *sm2_context, size_t hash_nid, + const uint8_t *id_a, size_t id_a_size, + const uint8_t *id_b, size_t id_b_size, + bool is_initiator); + +/** + * Generates sm2 key and returns sm2 public key (X, Y), based upon GB/T 32918.3-2016: SM2 - Part3. + * + * This function generates random secret, and computes the public key (X, Y), which is + * returned via parameter public, public_size. + * X is the first half of public with size being public_size / 2, + * Y is the second half of public with size being public_size / 2. + * sm2 context is updated accordingly. + * If the public buffer is too small to hold the public X, Y, false is returned and + * public_size is set to the required buffer size to obtain the public X, Y. + * + * The public_size is 64. first 32-byte is X, second 32-byte is Y. + * + * If sm2_context is NULL, then return false. + * If public_size is NULL, then return false. + * If public_size is large enough but public is NULL, then return false. + * + * @param[in, out] sm2_context Pointer to the sm2 context. + * @param[out] public_data Pointer to the buffer to receive generated public X,Y. + * @param[in, out] public_size On input, the size of public buffer in bytes. + * On output, the size of data returned in public buffer in bytes. + * + * @retval true sm2 public X,Y generation succeeded. + * @retval false sm2 public X,Y generation failed. + * @retval false public_size is not large enough. + **/ +extern bool libspdm_sm2_key_exchange_generate_key(void *sm2_context, uint8_t *public_data, + size_t *public_size); + +/** + * Computes exchanged common key, based upon GB/T 32918.3-2016: SM2 - Part3. + * + * Given peer's public key (X, Y), this function computes the exchanged common key, + * based on its own context including value of curve parameter and random secret. + * X is the first half of peer_public with size being peer_public_size / 2, + * Y is the second half of peer_public with size being peer_public_size / 2. + * + * If sm2_context is NULL, then return false. + * If peer_public is NULL, then return false. + * If peer_public_size is 0, then return false. + * If key is NULL, then return false. + * + * The id_a_size and id_b_size must be smaller than 2^16-1. + * The peer_public_size is 64. first 32-byte is X, second 32-byte is Y. + * The key_size must be smaller than 2^32-1, limited by KDF function. + * + * @param[in, out] sm2_context Pointer to the sm2 context. + * @param[in] peer_public Pointer to the peer's public X,Y. + * @param[in] peer_public_size Size of peer's public X,Y in bytes. + * @param[out] key Pointer to the buffer to receive generated key. + * @param[in] key_size On input, the size of key buffer in bytes. + * + * @retval true sm2 exchanged key generation succeeded. + * @retval false sm2 exchanged key generation failed. + **/ +extern bool libspdm_sm2_key_exchange_compute_key(void *sm2_context, + const uint8_t *peer_public, + size_t peer_public_size, uint8_t *key, + size_t *key_size); +#endif /* LIBSPDM_SM2_KEY_EXCHANGE_SUPPORT */ +#endif /* CRYPTLIB_SM2_H */ diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/kernel-open/nvidia/internal/libspdm_lib_config.h nvidia-open-gpu-kernel-modules-535.161.08/kernel-open/nvidia/internal/libspdm_lib_config.h --- nvidia-open-gpu-kernel-modules-525.147.05/kernel-open/nvidia/internal/libspdm_lib_config.h 1970-01-01 00:00:00.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/kernel-open/nvidia/internal/libspdm_lib_config.h 2024-03-05 22:25:37.000000000 +0000 @@ -0,0 +1,71 @@ +/** + * Copyright Notice: + * Copyright 2021-2022 DMTF. All rights reserved. + * License: BSD 3-Clause License. For full text see link: https://github.com/DMTF/libspdm/blob/main/LICENSE.md + **/ + +#ifndef LIBSPDM_LIB_CONFIG_H +#define LIBSPDM_LIB_CONFIG_H + +#ifndef LIBSPDM_CONFIG +#include "library/spdm_lib_config.h" +#else +#include LIBSPDM_CONFIG +#endif + +#if defined(LIBSPDM_ENABLE_SET_CERTIFICATE_CAP) && \ + !defined(LIBSPDM_ENABLE_CAPABILITY_SET_CERTIFICATE_CAP) +#ifdef _MSC_VER +#pragma message("LIBSPDM_ENABLE_SET_CERTIFICATE_CAP is deprecated. Use " \ + "LIBSPDM_ENABLE_CAPABILITY_SET_CERTIFICATE_CAP instead. This warning will be removed in a " \ + "future release.") +#else +#warning LIBSPDM_ENABLE_SET_CERTIFICATE_CAP is deprecated. Use \ + LIBSPDM_ENABLE_CAPABILITY_SET_CERTIFICATE_CAP instead. This warning will be removed in a \ + future release. +#endif /* _MSC_VER */ +#endif /* defined(LIBSPDM_ENABLE_SET_CERTIFICATE_CAP) */ + +#if defined(LIBSPDM_ENABLE_CHUNK_CAP) && !defined(LIBSPDM_ENABLE_CAPABILITY_CHUNK_CAP) +#ifdef _MSC_VER +#pragma message("LIBSPDM_ENABLE_CHUNK_CAP is deprecated. Use LIBSPDM_ENABLE_CAPABILITY_CHUNK_CAP " \ + "instead. This warning will be removed in a future release.") +#else +#warning LIBSPDM_ENABLE_CHUNK_CAP is deprecated. Use LIBSPDM_ENABLE_CAPABILITY_CHUNK_CAP \ + instead. This warning will be removed in a future release. +#endif /* _MSC_VER */ +#endif /* defined(LIBSPDM_ENABLE_CHUNK_CAP) */ + +#if defined(MDEPKG_NDEBUG) && !defined(LIBSPDM_DEBUG_ENABLE) +#ifdef _MSC_VER +#pragma message("MDEPKG_NDEBUG is deprecated. Use LIBSPDM_DEBUG_ENABLE " \ + "instead. This warning will be removed in a future release.") +#else +#warning MDEPKG_NDEBUG is deprecated. Use LIBSPDM_DEBUG_ENABLE \ + instead. This warning will be removed in a future release. +#endif /* _MSC_VER */ +#endif /* defined(MDEPKG_NDEBUG) */ + +#if defined(LIBSPDM_DEBUG_ENABLE) +#undef LIBSPDM_DEBUG_ASSERT_ENABLE +#undef LIBSPDM_DEBUG_PRINT_ENABLE +#undef LIBSPDM_DEBUG_BLOCK_ENABLE + +#define LIBSPDM_DEBUG_ASSERT_ENABLE (LIBSPDM_DEBUG_ENABLE) +#define LIBSPDM_DEBUG_PRINT_ENABLE (LIBSPDM_DEBUG_ENABLE) +#define LIBSPDM_DEBUG_BLOCK_ENABLE (LIBSPDM_DEBUG_ENABLE) +#elif defined(MDEPKG_NDEBUG) +#undef LIBSPDM_DEBUG_ASSERT_ENABLE +#undef LIBSPDM_DEBUG_PRINT_ENABLE +#undef LIBSPDM_DEBUG_BLOCK_ENABLE + +#define LIBSPDM_DEBUG_ASSERT_ENABLE 0 +#define LIBSPDM_DEBUG_PRINT_ENABLE 0 +#define LIBSPDM_DEBUG_BLOCK_ENABLE 0 +#endif /* defined(LIBSPDM_DEBUG_ENABLE) */ + +#if LIBSPDM_CHECK_MACRO +#include "internal/libspdm_macro_check.h" +#endif /* LIBSPDM_CHECK_MACRO */ + +#endif /* LIBSPDM_LIB_CONFIG_H */ diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/kernel-open/nvidia/internal_crypt_lib.h nvidia-open-gpu-kernel-modules-535.161.08/kernel-open/nvidia/internal_crypt_lib.h --- nvidia-open-gpu-kernel-modules-525.147.05/kernel-open/nvidia/internal_crypt_lib.h 1970-01-01 00:00:00.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/kernel-open/nvidia/internal_crypt_lib.h 2024-03-05 22:25:36.000000000 +0000 @@ -0,0 +1,154 @@ +/* +* SPDX-FileCopyrightText: Copyright (c) 2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. +* SPDX-License-Identifier: MIT +* +* Permission is hereby granted, free of charge, to any person obtaining a +* copy of this software and associated documentation files (the "Software"), +* to deal in the Software without restriction, including without limitation +* the rights to use, copy, modify, merge, publish, distribute, sublicense, +* and/or sell copies of the Software, and to permit persons to whom the +* Software is furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in +* all copies or substantial portions of the Software. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER +* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING +* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER +* DEALINGS IN THE SOFTWARE. +*/ + +#ifndef __INTERNAL_CRYPT_LIB_H__ +#define __INTERNAL_CRYPT_LIB_H__ + +/* + * This code uses Linux Kernel Crypto API extensively. Web page written by + * Stephan Mueller and Marek Vasut is a good starting reference on how linux + * kernel provides crypto api. + */ +#include "conftest.h" + +#include +#include +#include +#include +#include + +// Check if ECDH/ECDSA are there, on some platforms they might not be... +#ifndef AUTOCONF_INCLUDED +#if defined(NV_GENERATED_AUTOCONF_H_PRESENT) +#include +#else +#include +#endif +#endif +#if \ + (defined(CONFIG_CRYPTO_AEAD) || defined(CONFIG_CRYPTO_AEAD_MODULE)) && \ + (defined(CONFIG_CRYPTO_AKCIPHER) || defined(CONFIG_CRYPTO_AKCIPHER_MODULE)) && \ + (defined(CONFIG_CRYPTO_SKCIPHER) || defined(CONFIG_CRYPTO_SKCIPHER_MODULE)) && \ + (defined(CONFIG_CRYPTO_HASH) || defined(CONFIG_CRYPTO_HASH_MODULE)) && \ + (defined(CONFIG_CRYPTO_HMAC) || defined(CONFIG_CRYPTO_HMAC_MODULE)) && \ + (defined(CONFIG_CRYPTO_ECDH) || defined(CONFIG_CRYPTO_ECDH_MODULE)) && \ + (defined(CONFIG_CRYPTO_ECDSA) || defined(CONFIG_CRYPTO_ECDSA_MODULE)) && \ + (defined(CONFIG_X509_CERTIFICATE_PARSER) || defined(CONFIG_X509_CERTIFICATE_PARSER_MODULE)) +#define NV_CONFIG_CRYPTO_PRESENT 1 +#endif + +/* + * It is possible that we don't have access to all the functions we have. This + * could be either because we are running non-gpl kernel, because kernel is too + * old or even just user disabled. If we should use LKCA, include headers, else + * define stubs to return errors. + */ +#if defined(NV_CRYPTO_PRESENT) && defined (NV_CONFIG_CRYPTO_PRESENT) +#define USE_LKCA 1 +#endif + +#ifdef USE_LKCA +#include +#include +#include +#include +#include +#include + +// HASH_MAX_DIGESTSIZE is available since 4.20. +// This value is accurate as of 6.1 +#ifndef HASH_MAX_DIGESTSIZE +#define HASH_MAX_DIGESTSIZE 64 +#endif + +#else +// Just stub everything out +struct shash_desc; +struct crypto_shash; +#define crypto_shash_setkey(...) -ENOMEM +#define crypto_shash_init(...) -ENOMEM +#define crypto_shash_update(...) -ENOMEM +#define crypto_shash_update(...) -ENOMEM +#define crypto_shash_final(...) -ENOMEM +#endif + +#define CHAR_BIT 8U +#undef SIZE_MAX +#define SIZE_MAX 8 + +#include "library/cryptlib.h" + +#define LIBSPDM_ASSERT(...) +struct lkca_aead_ctx; +int lkca_aead_alloc(struct lkca_aead_ctx **ctx, char const *alg); +void lkca_aead_free(struct lkca_aead_ctx *ctx); +int lkca_aead_ex(struct lkca_aead_ctx *ctx, + const uint8_t *key, size_t key_size, + uint8_t *iv, size_t iv_size, + const uint8_t *data_in, size_t data_in_size, + uint8_t *tag, size_t tag_size, + uint8_t *data_out, size_t *data_out_size, + bool enc); + +int libspdm_aead(const uint8_t *key, size_t key_size, + const uint8_t *iv, size_t iv_size, + const uint8_t *a_data, size_t a_data_size, + const uint8_t *data_in, size_t data_in_size, + const uint8_t *tag, size_t tag_size, + uint8_t *data_out, size_t *data_out_size, + bool enc, char const *alg); + +void *lkca_hash_new(const char* alg_name); +void lkca_hash_free(struct shash_desc *ctx); +bool lkca_hash_duplicate(struct shash_desc *dst, struct shash_desc const *src); +bool lkca_hash_all(const char* alg_name, const void *data, + size_t data_size, uint8_t *hash_value); +bool lkca_hmac_duplicate(struct shash_desc *dst, struct shash_desc const *src); +bool lkca_hmac_set_key(struct shash_desc *ctx, const uint8_t *key, size_t key_size); +bool lkca_hmac_all(const char* alg_name, const uint8_t *key, size_t key_size, + const uint8_t *data, size_t data_size, uint8_t *hash_value); +bool lkca_hkdf_extract_and_expand(const char *alg_name, + const uint8_t *key, size_t key_size, + const uint8_t *salt, size_t salt_size, + const uint8_t *info, size_t info_size, + uint8_t *out, size_t out_size); +bool lkca_hkdf_expand(const char *alg_name, + const uint8_t *prk, size_t prk_size, + const uint8_t *info, size_t info_size, + uint8_t *out, size_t out_size); + + +bool lkca_ecdsa_set_priv_key(void *context, uint8_t *key, size_t key_size); +bool lkca_ec_set_pub_key(void *ec_context, const uint8_t *public_key, + size_t public_key_size); +bool lkca_ec_get_pub_key(void *ec_context, uint8_t *public_key, + size_t *public_key_size); +bool lkca_ec_generate_key(void *ec_context, uint8_t *public_data, + size_t *public_size); +bool lkca_ec_compute_key(void *ec_context, const uint8_t *peer_public, + size_t peer_public_size, uint8_t *key, + size_t *key_size); +bool lkca_ecdsa_verify(void *ec_context, size_t hash_nid, + const uint8_t *message_hash, size_t hash_size, + const uint8_t *signature, size_t sig_size); +#endif diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/kernel-open/nvidia/library/cryptlib.h nvidia-open-gpu-kernel-modules-535.161.08/kernel-open/nvidia/library/cryptlib.h --- nvidia-open-gpu-kernel-modules-525.147.05/kernel-open/nvidia/library/cryptlib.h 1970-01-01 00:00:00.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/kernel-open/nvidia/library/cryptlib.h 2024-03-05 22:25:36.000000000 +0000 @@ -0,0 +1,109 @@ +/** + * Copyright Notice: + * Copyright 2021-2022 DMTF. All rights reserved. + * License: BSD 3-Clause License. For full text see link: https://github.com/DMTF/libspdm/blob/main/LICENSE.md + **/ + +/** @file + * Defines base cryptographic library APIs. + * The Base Cryptographic Library provides implementations of basic cryptography + * primitives (hash Serials, HMAC, AES, RSA, Diffie-Hellman, Elliptic Curve, etc) for security + * functionality enabling. + **/ + +#ifndef CRYPTLIB_H +#define CRYPTLIB_H + +#include "internal/libspdm_lib_config.h" + +#define LIBSPDM_CRYPTO_NID_NULL 0x0000 + +/* Hash */ +#define LIBSPDM_CRYPTO_NID_SHA256 0x0001 +#define LIBSPDM_CRYPTO_NID_SHA384 0x0002 +#define LIBSPDM_CRYPTO_NID_SHA512 0x0003 +#define LIBSPDM_CRYPTO_NID_SHA3_256 0x0004 +#define LIBSPDM_CRYPTO_NID_SHA3_384 0x0005 +#define LIBSPDM_CRYPTO_NID_SHA3_512 0x0006 +#define LIBSPDM_CRYPTO_NID_SM3_256 0x0007 + +/* Signing */ +#define LIBSPDM_CRYPTO_NID_RSASSA2048 0x0101 +#define LIBSPDM_CRYPTO_NID_RSASSA3072 0x0102 +#define LIBSPDM_CRYPTO_NID_RSASSA4096 0x0103 +#define LIBSPDM_CRYPTO_NID_RSAPSS2048 0x0104 +#define LIBSPDM_CRYPTO_NID_RSAPSS3072 0x0105 +#define LIBSPDM_CRYPTO_NID_RSAPSS4096 0x0106 +#define LIBSPDM_CRYPTO_NID_ECDSA_NIST_P256 0x0107 +#define LIBSPDM_CRYPTO_NID_ECDSA_NIST_P384 0x0108 +#define LIBSPDM_CRYPTO_NID_ECDSA_NIST_P521 0x0109 +#define LIBSPDM_CRYPTO_NID_SM2_DSA_P256 0x010A +#define LIBSPDM_CRYPTO_NID_EDDSA_ED25519 0x010B +#define LIBSPDM_CRYPTO_NID_EDDSA_ED448 0x010C + +/* Key Exchange */ +#define LIBSPDM_CRYPTO_NID_FFDHE2048 0x0201 +#define LIBSPDM_CRYPTO_NID_FFDHE3072 0x0202 +#define LIBSPDM_CRYPTO_NID_FFDHE4096 0x0203 +#define LIBSPDM_CRYPTO_NID_SECP256R1 0x0204 +#define LIBSPDM_CRYPTO_NID_SECP384R1 0x0205 +#define LIBSPDM_CRYPTO_NID_SECP521R1 0x0206 +#define LIBSPDM_CRYPTO_NID_SM2_KEY_EXCHANGE_P256 0x0207 +#define LIBSPDM_CRYPTO_NID_CURVE_X25519 0x0208 +#define LIBSPDM_CRYPTO_NID_CURVE_X448 0x0209 + +/* AEAD */ +#define LIBSPDM_CRYPTO_NID_AES_128_GCM 0x0301 +#define LIBSPDM_CRYPTO_NID_AES_256_GCM 0x0302 +#define LIBSPDM_CRYPTO_NID_CHACHA20_POLY1305 0x0303 +#define LIBSPDM_CRYPTO_NID_SM4_128_GCM 0x0304 + +/* X.509 v3 key usage extension flags. */ +#define LIBSPDM_CRYPTO_X509_KU_DIGITAL_SIGNATURE 0x80 /* bit 0 */ +#define LIBSPDM_CRYPTO_X509_KU_NON_REPUDIATION 0x40 /* bit 1 */ +#define LIBSPDM_CRYPTO_X509_KU_KEY_ENCIPHERMENT 0x20 /* bit 2 */ +#define LIBSPDM_CRYPTO_X509_KU_DATA_ENCIPHERMENT 0x10 /* bit 3 */ +#define LIBSPDM_CRYPTO_X509_KU_KEY_AGREEMENT 0x08 /* bit 4 */ +#define LIBSPDM_CRYPTO_X509_KU_KEY_CERT_SIGN 0x04 /* bit 5 */ +#define LIBSPDM_CRYPTO_X509_KU_CRL_SIGN 0x02 /* bit 6 */ +#define LIBSPDM_CRYPTO_X509_KU_ENCIPHER_ONLY 0x01 /* bit 7 */ +#define LIBSPDM_CRYPTO_X509_KU_DECIPHER_ONLY 0x8000 /* bit 8 */ + +/* These constants comply with the DER encoded ASN.1 type tags. */ +#define LIBSPDM_CRYPTO_ASN1_BOOLEAN 0x01 +#define LIBSPDM_CRYPTO_ASN1_INTEGER 0x02 +#define LIBSPDM_CRYPTO_ASN1_BIT_STRING 0x03 +#define LIBSPDM_CRYPTO_ASN1_OCTET_STRING 0x04 +#define LIBSPDM_CRYPTO_ASN1_NULL 0x05 +#define LIBSPDM_CRYPTO_ASN1_OID 0x06 +#define LIBSPDM_CRYPTO_ASN1_UTF8_STRING 0x0C +#define LIBSPDM_CRYPTO_ASN1_SEQUENCE 0x10 +#define LIBSPDM_CRYPTO_ASN1_SET 0x11 +#define LIBSPDM_CRYPTO_ASN1_PRINTABLE_STRING 0x13 +#define LIBSPDM_CRYPTO_ASN1_T61_STRING 0x14 +#define LIBSPDM_CRYPTO_ASN1_IA5_STRING 0x16 +#define LIBSPDM_CRYPTO_ASN1_UTC_TIME 0x17 +#define LIBSPDM_CRYPTO_ASN1_GENERALIZED_TIME 0x18 +#define LIBSPDM_CRYPTO_ASN1_UNIVERSAL_STRING 0x1C +#define LIBSPDM_CRYPTO_ASN1_BMP_STRING 0x1E +#define LIBSPDM_CRYPTO_ASN1_PRIMITIVE 0x00 +#define LIBSPDM_CRYPTO_ASN1_CONSTRUCTED 0x20 +#define LIBSPDM_CRYPTO_ASN1_CONTEXT_SPECIFIC 0x80 + +#define LIBSPDM_CRYPTO_ASN1_TAG_CLASS_MASK 0xC0 +#define LIBSPDM_CRYPTO_ASN1_TAG_PC_MASK 0x20 +#define LIBSPDM_CRYPTO_ASN1_TAG_VALUE_MASK 0x1F + +#include "hal/library/cryptlib/cryptlib_hash.h" +#include "hal/library/cryptlib/cryptlib_mac.h" +#include "hal/library/cryptlib/cryptlib_aead.h" +#include "hal/library/cryptlib/cryptlib_cert.h" +#include "hal/library/cryptlib/cryptlib_hkdf.h" +#include "hal/library/cryptlib/cryptlib_rsa.h" +#include "hal/library/cryptlib/cryptlib_ec.h" +#include "hal/library/cryptlib/cryptlib_dh.h" +#include "hal/library/cryptlib/cryptlib_ecd.h" +#include "hal/library/cryptlib/cryptlib_sm2.h" +#include "hal/library/cryptlib/cryptlib_rng.h" + +#endif /* CRYPTLIB_H */ diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/kernel-open/nvidia/library/spdm_lib_config.h nvidia-open-gpu-kernel-modules-535.161.08/kernel-open/nvidia/library/spdm_lib_config.h --- nvidia-open-gpu-kernel-modules-525.147.05/kernel-open/nvidia/library/spdm_lib_config.h 1970-01-01 00:00:00.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/kernel-open/nvidia/library/spdm_lib_config.h 2024-03-05 22:25:37.000000000 +0000 @@ -0,0 +1,415 @@ +/** + * Copyright Notice: + * Copyright 2021-2022 DMTF. All rights reserved. + * License: BSD 3-Clause License. For full text see link: https://github.com/DMTF/libspdm/blob/main/LICENSE.md + **/ + +#ifndef SPDM_LIB_CONFIG_H +#define SPDM_LIB_CONFIG_H + +/* Enables assertions and debug printing. When `LIBSPDM_DEBUG_ENABLE` is defined it overrides or + * sets the values of `LIBSPDM_DEBUG_PRINT_ENABLE`, `LIBSPDM_DEBUG_ASSERT_ENABLE`, and + * `LIBSPDM_BLOCK_ENABLE` to the value of `LIBSPDM_DEBUG_ENABLE`. + * + * Note that if this file is used with CMake and `DTARGET=Release` is defined, then all debugging + * is disabled. + */ +#ifndef LIBSPDM_DEBUG_ENABLE +#define LIBSPDM_DEBUG_ENABLE 1 +#endif + +/* The SPDM specification allows a Responder to return up to 256 version entries in the `VERSION` + * response to the Requester, including duplicate entries. For a Requester this value specifies the + * maximum number of entries that libspdm will tolerate in a `VERSION` response before returning an + * error. A similiar macro, `SPDM_MAX_VERSION_COUNT`, exists for the Responder. However this macro + * is not meant to be configured by the Integrator. + */ +#ifndef LIBSPDM_MAX_VERSION_COUNT +#define LIBSPDM_MAX_VERSION_COUNT 5 +#endif + +/* This value specifies the maximum size, in bytes, of the `PSK_EXCHANGE.RequesterContext` and, + * if supported by the Responder, `PSK_EXCHANGE_RSP.ResponderContext` fields. The fields are + * typically random or monotonically increasing numbers. + */ +#ifndef LIBSPDM_PSK_CONTEXT_LENGTH +#define LIBSPDM_PSK_CONTEXT_LENGTH LIBSPDM_MAX_HASH_SIZE +#endif +/* This value specifies the maximum size, in bytes, of the `PSK_EXCHANGE.PSKHint` field.*/ +#ifndef LIBSPDM_PSK_MAX_HINT_LENGTH +#define LIBSPDM_PSK_MAX_HINT_LENGTH 16 +#endif + +/* libspdm allows an Integrator to specify multiple root certificates as trust anchors when + * verifying certificate chains from an endpoint. This value specifies the maximum number of root + * certificates that libspdm can support. + */ +#ifndef LIBSPDM_MAX_ROOT_CERT_SUPPORT +#define LIBSPDM_MAX_ROOT_CERT_SUPPORT 10 +#endif + +/* If the Responder supports it a Requester is allowed to establish multiple secure sessions with + * the Responder. This value specifies the maximum number of sessions libspdm can support. + */ +#ifndef LIBSPDM_MAX_SESSION_COUNT +#define LIBSPDM_MAX_SESSION_COUNT 4 +#endif +/* This value specifies the maximum size, in bytes, of a certificate chain that can be stored in a + * libspdm context. + */ +#ifndef LIBSPDM_MAX_CERT_CHAIN_SIZE +#define LIBSPDM_MAX_CERT_CHAIN_SIZE 0x1000 +#endif +#ifndef LIBSPDM_MAX_MEASUREMENT_RECORD_SIZE +#define LIBSPDM_MAX_MEASUREMENT_RECORD_SIZE 0x1000 +#endif +/* Partial certificates can be retrieved from a Requester or Responder and through multiple messages + * the complete certificate chain can be constructed. This value specifies the maximum size, + * in bytes, of a partial certificate that can be sent or received. + */ +#ifndef LIBSPDM_MAX_CERT_CHAIN_BLOCK_LEN +#define LIBSPDM_MAX_CERT_CHAIN_BLOCK_LEN 1024 +#endif + +#ifndef LIBSPDM_MAX_MESSAGE_BUFFER_SIZE +#define LIBSPDM_MAX_MESSAGE_BUFFER_SIZE 0x1200 +#endif +#ifndef LIBSPDM_MAX_MESSAGE_SMALL_BUFFER_SIZE +#define LIBSPDM_MAX_MESSAGE_SMALL_BUFFER_SIZE 0x100 /* to hold message_a before negotiate*/ +#endif +#ifndef LIBSPDM_MAX_MESSAGE_MEDIUM_BUFFER_SIZE +#define LIBSPDM_MAX_MESSAGE_MEDIUM_BUFFER_SIZE 0x300 /* to hold message_k before finished_key is ready*/ +#endif + +/* If the Responder replies with a Busy `ERROR` response to a request then the Requester is free to + * retry sending the request. This value specifies the maximum number of times libspdm will retry + * sending the request before returning an error. If its value is 0 then libspdm will not send any + * retry requests. + */ +#ifndef LIBSPDM_MAX_REQUEST_RETRY_TIMES +#define LIBSPDM_MAX_REQUEST_RETRY_TIMES 3 +#endif +#ifndef LIBSPDM_MAX_SESSION_STATE_CALLBACK_NUM +#define LIBSPDM_MAX_SESSION_STATE_CALLBACK_NUM 4 +#endif +#ifndef LIBSPDM_MAX_CONNECTION_STATE_CALLBACK_NUM +#define LIBSPDM_MAX_CONNECTION_STATE_CALLBACK_NUM 4 +#endif +#ifndef LIBSPDM_MAX_KEY_UPDATE_CALLBACK_NUM +#define LIBSPDM_MAX_KEY_UPDATE_CALLBACK_NUM 4 +#endif + +#ifndef LIBSPDM_MAX_CSR_SIZE +#define LIBSPDM_MAX_CSR_SIZE 0x1000 +#endif + +/* To ensure integrity in communication between the Requester and the Responder libspdm calculates + * cryptographic digests and signatures over multiple requests and responses. This value specifies + * whether libspdm will use a running calculation over the transcript, where requests and responses + * are discarded as they are cryptographically consumed, or whether libspdm will buffer the entire + * transcript before calculating the digest or signature. + */ +#ifndef LIBSPDM_RECORD_TRANSCRIPT_DATA_SUPPORT +#define LIBSPDM_RECORD_TRANSCRIPT_DATA_SUPPORT 0 +#endif + + +/* Cryptography Configuration + * In each category, at least one should be selected. + * NOTE: Not all combination can be supported. E.g. Don't mix NIST algo with SMx.*/ + +#ifndef LIBSPDM_RSA_SSA_SUPPORT +#define LIBSPDM_RSA_SSA_SUPPORT 1 +#endif +#ifndef LIBSPDM_RSA_PSS_SUPPORT +#define LIBSPDM_RSA_PSS_SUPPORT 1 +#endif +#ifndef LIBSPDM_ECDSA_SUPPORT +#define LIBSPDM_ECDSA_SUPPORT 1 +#endif +#ifndef LIBSPDM_SM2_DSA_SUPPORT +#define LIBSPDM_SM2_DSA_SUPPORT 1 +#endif +#ifndef LIBSPDM_EDDSA_ED25519_SUPPORT +#define LIBSPDM_EDDSA_ED25519_SUPPORT 1 +#endif +#ifndef LIBSPDM_EDDSA_ED448_SUPPORT +#define LIBSPDM_EDDSA_ED448_SUPPORT 1 +#endif + +#ifndef LIBSPDM_FFDHE_SUPPORT +#define LIBSPDM_FFDHE_SUPPORT 1 +#endif +#ifndef LIBSPDM_ECDHE_SUPPORT +#define LIBSPDM_ECDHE_SUPPORT 1 +#endif +#ifndef LIBSPDM_SM2_KEY_EXCHANGE_SUPPORT +#define LIBSPDM_SM2_KEY_EXCHANGE_SUPPORT 1 +#endif + +#ifndef LIBSPDM_AEAD_GCM_SUPPORT +#define LIBSPDM_AEAD_GCM_SUPPORT 1 +#endif +#ifndef LIBSPDM_AEAD_CHACHA20_POLY1305_SUPPORT +#define LIBSPDM_AEAD_CHACHA20_POLY1305_SUPPORT 1 +#endif +#ifndef LIBSPDM_AEAD_SM4_SUPPORT +#define LIBSPDM_AEAD_SM4_SUPPORT 1 +#endif + +#ifndef LIBSPDM_SHA256_SUPPORT +#define LIBSPDM_SHA256_SUPPORT 1 +#endif +#ifndef LIBSPDM_SHA384_SUPPORT +#define LIBSPDM_SHA384_SUPPORT 1 +#endif +#ifndef LIBSPDM_SHA512_SUPPORT +#define LIBSPDM_SHA512_SUPPORT 1 +#endif +#ifndef LIBSPDM_SHA3_256_SUPPORT +#define LIBSPDM_SHA3_256_SUPPORT 1 +#endif +#ifndef LIBSPDM_SHA3_384_SUPPORT +#define LIBSPDM_SHA3_384_SUPPORT 1 +#endif +#ifndef LIBSPDM_SHA3_512_SUPPORT +#define LIBSPDM_SHA3_512_SUPPORT 1 +#endif +#ifndef LIBSPDM_SM3_256_SUPPORT +#define LIBSPDM_SM3_256_SUPPORT 1 +#endif + +/* Code space optimization for Optional request/response messages.*/ + +/* Consumers of libspdm may wish to not fully implement all of the optional + * SPDM request/response messages. Therefore we have provided these + * SPDM_ENABLE_CAPABILITY_***_CAP compile time switches as an optimization + * disable the code (#if 0) related to said optional capability, thereby + * reducing the code space used in the image.*/ + +/* A single switch may enable/disable a single capability or group of related + * capabilities.*/ + +/* LIBSPDM_ENABLE_CAPABILITY_CERT_CAP - Enable/Disable single CERT capability. + * LIBSPDM_ENABLE_CAPABILITY_CHAL_CAP - Enable/Disable single CHAL capability. + * LIBSPDM_ENABLE_CAPABILTIY_MEAS_CAP - Enable/Disables multiple MEAS capabilities: + * (MEAS_CAP_NO_SIG, MEAS_CAP_SIG, MEAS_FRESH_CAP)*/ + +/* LIBSPDM_ENABLE_CAPABILITY_KEY_EX_CAP - Enable/Disable single Key Exchange capability. + * LIBSPDM_ENABLE_CAPABILITY_PSK_EX_CAP - Enable/Disable PSK_EX and PSK_FINISH.*/ + +/* LIBSPDM_ENABLE_CAPABILITY_MUT_AUTH_CAP - Enable/Disable mutual authentication. +* LIBSPDM_ENABLE_CAPABILITY_ENCAP_CAP - Enable/Disable encapsulated message.*/ + +/* LIBSPDM_ENABLE_CAPABILITY_GET_CSR_CAP - Enable/Disable get csr capability. + * LIBSPDM_ENABLE_CAPABILITY_SET_CERTIFICATE_CAP - Enable/Disable set certificate capability. */ + +#ifndef LIBSPDM_ENABLE_CAPABILITY_CERT_CAP +#define LIBSPDM_ENABLE_CAPABILITY_CERT_CAP 1 +#endif + +#ifndef LIBSPDM_ENABLE_CAPABILITY_CHAL_CAP +#define LIBSPDM_ENABLE_CAPABILITY_CHAL_CAP 1 +#endif + +#ifndef LIBSPDM_ENABLE_CAPABILITY_MEAS_CAP +#define LIBSPDM_ENABLE_CAPABILITY_MEAS_CAP 1 +#endif + +#ifndef LIBSPDM_ENABLE_CAPABILITY_KEY_EX_CAP +#define LIBSPDM_ENABLE_CAPABILITY_KEY_EX_CAP 1 +#endif + +#ifndef LIBSPDM_ENABLE_CAPABILITY_PSK_EX_CAP +#define LIBSPDM_ENABLE_CAPABILITY_PSK_EX_CAP 1 +#endif + +#ifndef LIBSPDM_ENABLE_CAPABILITY_HBEAT_CAP +#define LIBSPDM_ENABLE_CAPABILITY_HBEAT_CAP 1 +#endif + +#ifndef LIBSPDM_ENABLE_CAPABILITY_MUT_AUTH_CAP +#define LIBSPDM_ENABLE_CAPABILITY_MUT_AUTH_CAP 1 +#endif + +#ifndef LIBSPDM_ENABLE_CAPABILITY_ENCAP_CAP +#define LIBSPDM_ENABLE_CAPABILITY_ENCAP_CAP 1 +#endif + +#ifndef LIBSPDM_ENABLE_CAPABILITY_GET_CSR_CAP +#define LIBSPDM_ENABLE_CAPABILITY_GET_CSR_CAP 1 +#endif + +#ifndef LIBSPDM_ENABLE_CAPABILITY_SET_CERTIFICATE_CAP +#define LIBSPDM_ENABLE_CAPABILITY_SET_CERTIFICATE_CAP 1 +#endif + +#ifndef LIBSPDM_ENABLE_CAPABILITY_CHUNK_CAP +#define LIBSPDM_ENABLE_CAPABILITY_CHUNK_CAP 1 +#endif + +/* + * MinDataTransferSize = 42 + * + * H = HashLen = HmacLen = [32, 64] + * S = SigLen = [64, 512] + * D = ExchangeDataLen = [64, 512] + * R = RequesterContextLen >= 32 + * R = ResponderContextLen >= 0 + * O = OpaqueDataLen <= 1024 + * + * Max Chunk No = 1, if (message size <= 42) + * Max Chunk No = [(message size + 4) / 30] roundup, if (message size > 42) + * + * +==========================+==========================================+=========+ + * | Command | Size |MaxChunk | + * +==========================+==========================================+=========+ + * | GET_VERSION | 4 | 1 | + * | VERSION {1.0, 1.1, 1.2} | 6 + 2 * 3 = 12 | 1 | + * +--------------------------+------------------------------------------+---------+ + * | GET_CAPABILITIES 1.2 | 20 | 1 | + * | CAPABILITIES 1.2 | 20 | 1 | + * +--------------------------+------------------------------------------+---------+ + * | ERROR | 4 | 1 | + * | ERROR(ResponseTooLarge) | 4 + 4 = 8 | 1 | + * | ERROR(LargeResponse) | 4 + 1 = 5 | 1 | + * | ERROR(ResponseNotReady) | 4 + 4 = 8 | 1 | + * +--------------------------+------------------------------------------+---------+ + * | CHUNK_SEND header | 12 + L0 (0 or 4) | 1 | + * | CHUNK_RESPONSE header | 12 + L0 (0 or 4) | 1 | + * +==========================+==========================================+=========+ + * | NEGOTIATE_ALGORITHMS 1.2 | 32 + 4 * 4 = 48 | 2 | + * | ALGORITHMS 1.2 | 36 + 4 * 4 = 52 | 2 | + * +--------------------------+------------------------------------------+---------+ + * | GET_DIGESTS 1.2 | 4 | 1 | + * | DIGESTS 1.2 | 4 + H * SlotNum = [36, 516] | [1, 18] | + * +--------------------------+------------------------------------------+---------+ + * | GET_CERTIFICATE 1.2 | 8 | 1 | + * | CERTIFICATE 1.2 | 8 + PortionLen | [1, ] | + * +--------------------------+------------------------------------------+---------+ + * | CHALLENGE 1.2 | 40 | 1 | + * | CHALLENGE_AUTH 1.2 | 38 + H * 2 + S [+ O] = [166, 678] | [6, 23] | + * +--------------------------+------------------------------------------+---------+ + * | GET_MEASUREMENTS 1.2 | 5 + Nounce (0 or 32) | 1 | + * | MEASUREMENTS 1.2 | 42 + MeasRecLen (+ S) [+ O] = [106, 554] | [4, 19] | + * +--------------------------+------------------------------------------+---------+ + * | KEY_EXCHANGE 1.2 | 42 + D [+ O] = [106, 554] | [4, 19] | + * | KEY_EXCHANGE_RSP 1.2 | 42 + D + H + S (+ H) [+ O] = [234, 1194] | [8, 40] | + * +--------------------------+------------------------------------------+---------+ + * | FINISH 1.2 | 4 (+ S) + H = [100, 580] | [4, 20] | + * | FINISH_RSP 1.2 | 4 (+ H) = [36, 69] | [1, 3] | + * +--------------------------+------------------------------------------+---------+ + * | PSK_EXCHANGE 1.2 | 12 [+ PSKHint] + R [+ O] = 44 | 2 | + * | PSK_EXCHANGE_RSP 1.2 | 12 + R + H (+ H) [+ O] = [108, 172] | [4, 6] | + * +--------------------------+------------------------------------------+---------+ + * | PSK_FINISH 1.2 | 4 + H = [36, 68] | [1, 3] | + * | PSK_FINISH_RSP 1.2 | 4 | 1 | + * +--------------------------+------------------------------------------+---------+ + * | GET_CSR 1.2 | 8 + RequesterInfoLen [+ O] | [1, ] | + * | CSR 1.2 | 8 + CSRLength | [1, ] | + * +--------------------------+------------------------------------------+---------+ + * | SET_CERTIFICATE 1.2 | 4 + CertChainLen | [1, ] | + * | SET_CERTIFICATE_RSP 1.2 | 4 | 1 | + * +==========================+==========================================+=========+ + */ + +/* Maximum size of a large SPDM message. + * If chunk is unsupported, it must be same as LIBSPDM_DATA_TRANSFER_SIZE. + * If chunk is supported, it must be larger than LIBSPDM_DATA_TRANSFER_SIZE. + * It matches MaxSPDMmsgSize in SPDM specification. */ +#ifndef LIBSPDM_MAX_SPDM_MSG_SIZE +#define LIBSPDM_MAX_SPDM_MSG_SIZE LIBSPDM_MAX_MESSAGE_BUFFER_SIZE +#endif + +/* Maximum size of a single SPDM message. + * It matches DataTransferSize in SPDM specification. */ +#ifndef LIBSPDM_DATA_TRANSFER_SIZE +#define LIBSPDM_DATA_TRANSFER_SIZE LIBSPDM_MAX_MESSAGE_BUFFER_SIZE +#endif + +/* Required sender/receive buffer in device io. + * NOTE: This is transport specific. Below configuration is just an example. + * +-------+--------+---------------------------+------+--+------+---+--------+-----+ + * | TYPE |TransHdr| EncryptionHeader |AppHdr| |Random|MAC|AlignPad|FINAL| + * | | |SessionId|SeqNum|Len|AppLen| | | | | | | + * +-------+--------+---------------------------+------+ +------+---+--------+-----+ + * | MCTP | 1 | 4 | 2 | 2 | 2 | 1 | | 32 | 12| 0 | 56 | + * |PCI_DOE| 8 | 4 | 0 | 2 | 2 | 0 | | 0 | 12| 3 | 31 | + * +-------+--------+---------------------------+------+--+------+---+--------+-----+ + */ +#ifndef LIBSPDM_TRANSPORT_ADDITIONAL_SIZE +#define LIBSPDM_TRANSPORT_ADDITIONAL_SIZE 64 +#endif +#ifndef LIBSPDM_SENDER_RECEIVE_BUFFER_SIZE +#define LIBSPDM_SENDER_RECEIVE_BUFFER_SIZE (LIBSPDM_DATA_TRANSFER_SIZE + \ + LIBSPDM_TRANSPORT_ADDITIONAL_SIZE) +#endif + + +/* Required scratch buffer size for libspdm internal usage. + * It may be used to hold the encrypted/decrypted message and/or last sent/received message. + * It may be used to hold the large request/response and intermediate send/receive buffer + * in case of chunking. + * + * If chunking is not supported, it may be just LIBSPDM_SENDER_RECEIVE_BUFFER_SIZE. + * If chunking is supported, it should be at least below. + * + * +---------------+--------------+--------------------------+------------------------------+ + * |SECURE_MESSAGE |LARGE_MESSAGE | SENDER_RECEIVER | LARGE_SENDER_RECEIVER | + * +---------------+--------------+--------------------------+------------------------------+ + * |<-Secure msg ->|<-Large msg ->|<-Snd/Rcv buf for chunk ->|<-Snd/Rcv buf for large msg ->| + * + * The value is NOT configurable. + * The value MAY be changed in different libspdm version. + * It is exposed here, just in case the libspdm consumer wants to configure the setting at build time. + */ +#if LIBSPDM_ENABLE_CAPABILITY_CHUNK_CAP + +/* first section */ +#define LIBSPDM_SCRATCH_BUFFER_SECURE_MESSAGE_OFFSET 0 + +#define LIBSPDM_SCRATCH_BUFFER_SECURE_MESSAGE_CAPACITY (LIBSPDM_MAX_SPDM_MSG_SIZE) + +/* second section */ +#define LIBSPDM_SCRATCH_BUFFER_LARGE_MESSAGE_OFFSET (LIBSPDM_SCRATCH_BUFFER_SECURE_MESSAGE_CAPACITY) + +#define LIBSPDM_SCRATCH_BUFFER_LARGE_MESSAGE_CAPACITY (LIBSPDM_MAX_SPDM_MSG_SIZE) + +/* third section */ +#define LIBSPDM_SCRATCH_BUFFER_SENDER_RECEIVER_OFFSET \ + (LIBSPDM_SCRATCH_BUFFER_SECURE_MESSAGE_CAPACITY + \ + LIBSPDM_SCRATCH_BUFFER_LARGE_MESSAGE_CAPACITY) + +#define LIBSPDM_SCRATCH_BUFFER_SENDER_RECEIVER_CAPACITY (LIBSPDM_MAX_SPDM_MSG_SIZE) + +/* fourth section */ +#define LIBSPDM_SCRATCH_BUFFER_LARGE_SENDER_RECEIVER_OFFSET \ + (LIBSPDM_SCRATCH_BUFFER_SECURE_MESSAGE_CAPACITY + \ + LIBSPDM_SCRATCH_BUFFER_LARGE_MESSAGE_CAPACITY + \ + LIBSPDM_SCRATCH_BUFFER_SENDER_RECEIVER_CAPACITY) + +#define LIBSPDM_SCRATCH_BUFFER_LARGE_SENDER_RECEIVER_CAPACITY (LIBSPDM_MAX_SPDM_MSG_SIZE) + +#define LIBSPDM_SCRATCH_BUFFER_SIZE (LIBSPDM_SCRATCH_BUFFER_SECURE_MESSAGE_CAPACITY + \ + LIBSPDM_SCRATCH_BUFFER_LARGE_MESSAGE_CAPACITY + \ + LIBSPDM_SCRATCH_BUFFER_SENDER_RECEIVER_CAPACITY + \ + LIBSPDM_SCRATCH_BUFFER_LARGE_SENDER_RECEIVER_CAPACITY \ + ) + +#else +#define LIBSPDM_SCRATCH_BUFFER_SIZE (LIBSPDM_SENDER_RECEIVE_BUFFER_SIZE) +#endif + +/* Enable message logging. + * See https://github.com/DMTF/libspdm/blob/main/doc/user_guide.md#message-logging + * for more information */ +#ifndef LIBSPDM_ENABLE_MSG_LOG +#define LIBSPDM_ENABLE_MSG_LOG 1 +#endif + +/* Enable macro checking during compilation. */ +#ifndef LIBSPDM_CHECK_MACRO +#define LIBSPDM_CHECK_MACRO 0 +#endif + +#endif /* SPDM_LIB_CONFIG_H */ diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/kernel-open/nvidia/libspdm_aead.c nvidia-open-gpu-kernel-modules-535.161.08/kernel-open/nvidia/libspdm_aead.c --- nvidia-open-gpu-kernel-modules-525.147.05/kernel-open/nvidia/libspdm_aead.c 1970-01-01 00:00:00.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/kernel-open/nvidia/libspdm_aead.c 2024-03-05 22:25:35.000000000 +0000 @@ -0,0 +1,470 @@ +/* +* SPDX-FileCopyrightText: Copyright (c) 2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. +* SPDX-License-Identifier: MIT +* +* Permission is hereby granted, free of charge, to any person obtaining a +* copy of this software and associated documentation files (the "Software"), +* to deal in the Software without restriction, including without limitation +* the rights to use, copy, modify, merge, publish, distribute, sublicense, +* and/or sell copies of the Software, and to permit persons to whom the +* Software is furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in +* all copies or substantial portions of the Software. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER +* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING +* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER +* DEALINGS IN THE SOFTWARE. +*/ + +#include "internal_crypt_lib.h" +#include "nvspdm_cryptlib_extensions.h" + +#ifdef USE_LKCA +#define BUFFER_SIZE (2 * 1024 * 1024) +#define AUTH_TAG_SIZE 16 +struct lkca_aead_ctx +{ + struct crypto_aead *aead; + struct aead_request *req; + char *a_data_buffer; + char *in_buffer; + char *out_buffer; + char tag[AUTH_TAG_SIZE]; +}; +#endif + +int libspdm_aead_prealloc(void **context, char const *alg) +{ +#ifndef USE_LKCA + return -ENODEV; +#else + struct lkca_aead_ctx *ctx; + + ctx = kmalloc(sizeof(*ctx), GFP_KERNEL); + if (ctx == NULL) { + return -ENOMEM; + } + + memset(ctx, 0, sizeof(*ctx)); + + ctx->aead = crypto_alloc_aead(alg, CRYPTO_ALG_TYPE_AEAD, 0); + if (IS_ERR(ctx->aead)) { + pr_notice("could not allocate AEAD algorithm\n"); + kfree(ctx); + return -ENODEV; + } + + ctx->req = aead_request_alloc(ctx->aead, GFP_KERNEL); + if (ctx->req == NULL) { + pr_info("could not allocate skcipher request\n"); + crypto_free_aead(ctx->aead); + kfree(ctx); + return -ENOMEM; + } + + ctx->a_data_buffer = kmalloc(BUFFER_SIZE, GFP_KERNEL); + if (ctx->a_data_buffer == NULL) { + aead_request_free(ctx->req); + crypto_free_aead(ctx->aead); + kfree(ctx); + return -ENOMEM; + } + + ctx->in_buffer = kmalloc(BUFFER_SIZE, GFP_KERNEL); + if (ctx->in_buffer == NULL) { + kfree(ctx->a_data_buffer); + aead_request_free(ctx->req); + crypto_free_aead(ctx->aead); + kfree(ctx); + return -ENOMEM; + } + + ctx->out_buffer = kmalloc(BUFFER_SIZE, GFP_KERNEL); + if (ctx->out_buffer == NULL) { + kfree(ctx->a_data_buffer); + kfree(ctx->in_buffer); + aead_request_free(ctx->req); + crypto_free_aead(ctx->aead); + kfree(ctx); + return -ENOMEM; + } + + *context = ctx; + return 0; +#endif +} + +void libspdm_aead_free(void *context) +{ +#ifdef USE_LKCA + struct lkca_aead_ctx *ctx = context; + crypto_free_aead(ctx->aead); + aead_request_free(ctx->req); + kfree(ctx->a_data_buffer); + kfree(ctx->in_buffer); + kfree(ctx->out_buffer); + kfree(ctx); +#endif +} + +#define SG_AEAD_AAD 0 +#define SG_AEAD_TEXT 1 +#define SG_AEAD_SIG 2 +// Number of fields in AEAD scatterlist +#define SG_AEAD_LEN 3 + +#ifdef USE_LKCA +// This function doesn't do any allocs, it uses temp buffers instead +static int lkca_aead_internal(struct crypto_aead *aead, + struct aead_request *req, + const uint8_t *key, size_t key_size, + const uint8_t *iv, size_t iv_size, + struct scatterlist sg_in[], + struct scatterlist sg_out[], + size_t a_data_size, + size_t data_in_size, + size_t *data_out_size, + size_t tag_size, + bool enc) +{ + DECLARE_CRYPTO_WAIT(wait); + int rc = 0; + + if (crypto_aead_setkey(aead, key, key_size)) { + pr_info("key could not be set\n"); + return -EINVAL; + } + + if (crypto_aead_ivsize(aead) != iv_size) { + pr_info("iv could not be set\n"); + return -EINVAL; + } + + aead_request_set_ad(req, a_data_size); + + aead_request_set_callback(req, CRYPTO_TFM_REQ_MAY_BACKLOG | + CRYPTO_TFM_REQ_MAY_SLEEP, crypto_req_done, &wait); + + if (enc) { + aead_request_set_crypt(req, sg_in, sg_out, data_in_size, (u8 *) iv); + rc = crypto_wait_req(crypto_aead_encrypt(req), &wait); + } else { + aead_request_set_crypt(req, sg_in, sg_out, data_in_size + tag_size, (u8 *) iv); + rc = crypto_wait_req(crypto_aead_decrypt(req), &wait); + } + + if (rc != 0) { + pr_info("Encryption FAILED\n"); + } + + *data_out_size = data_in_size; + + return rc; +} +#endif + +int libspdm_aead_prealloced(void *context, + const uint8_t *key, size_t key_size, + const uint8_t *iv, size_t iv_size, + const uint8_t *a_data, size_t a_data_size, + const uint8_t *data_in, size_t data_in_size, + uint8_t *tag, size_t tag_size, + uint8_t *data_out, size_t *data_out_size, + bool enc) +{ +#ifndef USE_LKCA + return -ENODEV; +#else + int rc = 0; + struct scatterlist sg_in[SG_AEAD_LEN]; + struct scatterlist sg_out[SG_AEAD_LEN]; + struct lkca_aead_ctx *ctx = context; + + + sg_init_table(sg_in, SG_AEAD_LEN); + sg_init_table(sg_out, SG_AEAD_LEN); + + if (!virt_addr_valid(a_data)) { + if (a_data_size > BUFFER_SIZE) { + return -ENOMEM; + } + sg_set_buf(&sg_in[SG_AEAD_AAD], ctx->a_data_buffer, a_data_size); + sg_set_buf(&sg_out[SG_AEAD_AAD], ctx->a_data_buffer, a_data_size); + + memcpy(ctx->a_data_buffer, a_data, a_data_size); + } else { + sg_set_buf(&sg_in[SG_AEAD_AAD], a_data, a_data_size); + sg_set_buf(&sg_out[SG_AEAD_AAD], a_data, a_data_size); + } + + if (!virt_addr_valid(data_in)) { + if (data_in_size > BUFFER_SIZE) { + return -ENOMEM; + } + sg_set_buf(&sg_in[SG_AEAD_TEXT], ctx->in_buffer, data_in_size); + memcpy(ctx->in_buffer, data_in, data_in_size); + } else { + sg_set_buf(&sg_in[SG_AEAD_TEXT], data_in, data_in_size); + } + + if (!virt_addr_valid(data_out)) { + if (data_in_size > BUFFER_SIZE) { + return -ENOMEM; + } + sg_set_buf(&sg_out[SG_AEAD_TEXT], ctx->out_buffer, data_in_size); + } else { + sg_set_buf(&sg_out[SG_AEAD_TEXT], data_out, data_in_size); + } + + // Tag is small enough that memcpy is cheaper than checking if page is virtual + if(tag_size > AUTH_TAG_SIZE) { + return -ENOMEM; + } + sg_set_buf(&sg_in[SG_AEAD_SIG], ctx->tag, tag_size); + sg_set_buf(&sg_out[SG_AEAD_SIG], ctx->tag, tag_size); + + if(!enc) + memcpy(ctx->tag, tag, tag_size); + + rc = lkca_aead_internal(ctx->aead, ctx->req, key, key_size, iv, iv_size, + sg_in, sg_out, a_data_size, data_in_size, + data_out_size, tag_size, enc); + + if (enc) { + memcpy(tag, ctx->tag, tag_size); + } + + if (!virt_addr_valid(data_out)) { + memcpy(data_out, ctx->out_buffer, data_in_size); + } + + return rc; +#endif +} + +int libspdm_aead(const uint8_t *key, size_t key_size, + const uint8_t *iv, size_t iv_size, + const uint8_t *a_data, size_t a_data_size, + const uint8_t *data_in, size_t data_in_size, + const uint8_t *tag, size_t tag_size, + uint8_t *data_out, size_t *data_out_size, + bool enc, char const *alg) +{ +#ifndef USE_LKCA + return -ENODEV; +#else + struct crypto_aead *aead = NULL; + struct aead_request *req = NULL; + struct scatterlist sg_in[SG_AEAD_LEN]; + struct scatterlist sg_out[SG_AEAD_LEN]; + uint8_t *a_data_shadow = NULL; + uint8_t *data_in_shadow = NULL; + uint8_t *data_out_shadow = NULL; + uint8_t *tag_shadow = NULL; + int rc = 0; + + aead = crypto_alloc_aead(alg, CRYPTO_ALG_TYPE_AEAD, 0); + if (IS_ERR(aead)) { + pr_notice("could not allocate AEAD algorithm\n"); + return -ENODEV; + } + + req = aead_request_alloc(aead, GFP_KERNEL); + if (req == NULL) { + pr_info("could not allocate skcipher request\n"); + rc = -ENOMEM; + goto out; + } + + sg_init_table(sg_in, SG_AEAD_LEN); + sg_init_table(sg_out, SG_AEAD_LEN); + + if (!virt_addr_valid(a_data)) { + a_data_shadow = kmalloc(a_data_size, GFP_KERNEL); + if (a_data_shadow == NULL) { + rc = -ENOMEM; + goto out; + } + + sg_set_buf(&sg_in[SG_AEAD_AAD], a_data_shadow, a_data_size); + sg_set_buf(&sg_out[SG_AEAD_AAD], a_data_shadow, a_data_size); + + memcpy(a_data_shadow, a_data, a_data_size); + } else { + sg_set_buf(&sg_in[SG_AEAD_AAD], a_data, a_data_size); + sg_set_buf(&sg_out[SG_AEAD_AAD], a_data, a_data_size); + } + + if (!virt_addr_valid(data_in)) { + data_in_shadow = kmalloc(data_in_size, GFP_KERNEL); + if (data_in_shadow == NULL) { + rc = -ENOMEM; + goto out; + } + + sg_set_buf(&sg_in[SG_AEAD_TEXT], data_in_shadow, data_in_size); + + memcpy(data_in_shadow, data_in, data_in_size); + } else { + sg_set_buf(&sg_in[SG_AEAD_TEXT], data_in, data_in_size); + } + + if (!virt_addr_valid(data_out)) { + data_out_shadow = kmalloc(data_in_size, GFP_KERNEL); + if (data_out_shadow == NULL) { + rc = -ENOMEM; + goto out; + } + + sg_set_buf(&sg_out[SG_AEAD_TEXT], data_out_shadow, data_in_size); + } else { + sg_set_buf(&sg_out[SG_AEAD_TEXT], data_out, data_in_size); + } + + if (!virt_addr_valid(tag)) { + tag_shadow = kmalloc(tag_size, GFP_KERNEL); + if (tag_shadow == NULL) { + rc = -ENOMEM; + goto out; + } + + sg_set_buf(&sg_in[SG_AEAD_SIG], tag_shadow, tag_size); + sg_set_buf(&sg_out[SG_AEAD_SIG], tag_shadow, tag_size); + + if(!enc) + memcpy(tag_shadow, tag, tag_size); + } else { + sg_set_buf(&sg_in[SG_AEAD_SIG], tag, tag_size); + sg_set_buf(&sg_out[SG_AEAD_SIG], tag, tag_size); + } + + rc = lkca_aead_internal(aead, req, key, key_size, iv, iv_size, + sg_in, sg_out, a_data_size, data_in_size, + data_out_size, tag_size, enc); + + if (enc && (tag_shadow != NULL)) + memcpy((uint8_t *) tag, tag_shadow, tag_size); + + if (data_out_shadow != NULL) + memcpy(data_out, data_out_shadow, data_in_size); + +out: + if (a_data_shadow != NULL) + kfree(a_data_shadow); + if (data_in_shadow != NULL) + kfree(data_in_shadow); + if (data_out != NULL) + kfree(data_out_shadow); + if (tag != NULL) + kfree(tag_shadow); + if (aead != NULL) + crypto_free_aead(aead); + if (req != NULL) + aead_request_free(req); + return rc; +#endif +} + +// Wrapper to make look like libspdm +bool libspdm_aead_gcm_prealloc(void **context) +{ + return libspdm_aead_prealloc(context, "gcm(aes)") == 0; +} + +bool libspdm_aead_aes_gcm_encrypt_prealloc(void *context, + const uint8_t *key, size_t key_size, + const uint8_t *iv, size_t iv_size, + const uint8_t *a_data, size_t a_data_size, + const uint8_t *data_in, size_t data_in_size, + uint8_t *tag_out, size_t tag_size, + uint8_t *data_out, size_t *data_out_size) +{ + int32_t ret; + + if (data_in_size > INT_MAX) { + return false; + } + if (a_data_size > INT_MAX) { + return false; + } + if (iv_size != 12) { + return false; + } + switch (key_size) { + case 16: + case 24: + case 32: + break; + default: + return false; + } + if ((tag_size < 12) || (tag_size > 16)) { + return false; + } + if (data_out_size != NULL) { + if ((*data_out_size > INT_MAX) || + (*data_out_size < data_in_size)) { + return false; + } + } + + ret = libspdm_aead_prealloced(context, key, key_size, iv, iv_size, + a_data, a_data_size, data_in, data_in_size, + tag_out, tag_size, data_out, data_out_size, true); + + *data_out_size = data_in_size; + + return ret == 0; +} + +bool libspdm_aead_aes_gcm_decrypt_prealloc(void *context, + const uint8_t *key, size_t key_size, + const uint8_t *iv, size_t iv_size, + const uint8_t *a_data, size_t a_data_size, + const uint8_t *data_in, size_t data_in_size, + const uint8_t *tag, size_t tag_size, + uint8_t *data_out, size_t *data_out_size) +{ + int ret; + if (data_in_size > INT_MAX) { + return false; + } + if (a_data_size > INT_MAX) { + return false; + } + if (iv_size != 12) { + return false; + } + switch (key_size) { + case 16: + case 24: + case 32: + break; + default: + return false; + } + if ((tag_size < 12) || (tag_size > 16)) { + return false; + } + if (data_out_size != NULL) { + if ((*data_out_size > INT_MAX) || + (*data_out_size < data_in_size)) { + return false; + } + } + + ret = libspdm_aead_prealloced(context, key, key_size, iv, iv_size, + a_data, a_data_size, data_in, data_in_size, + (uint8_t *) tag, tag_size, data_out, data_out_size, false); + + *data_out_size = data_in_size; + + return ret == 0; + +} + diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/kernel-open/nvidia/libspdm_aead_aes_gcm.c nvidia-open-gpu-kernel-modules-535.161.08/kernel-open/nvidia/libspdm_aead_aes_gcm.c --- nvidia-open-gpu-kernel-modules-525.147.05/kernel-open/nvidia/libspdm_aead_aes_gcm.c 1970-01-01 00:00:00.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/kernel-open/nvidia/libspdm_aead_aes_gcm.c 2024-03-05 22:25:36.000000000 +0000 @@ -0,0 +1,117 @@ +/* +* SPDX-FileCopyrightText: Copyright (c) 2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. +* SPDX-License-Identifier: MIT +* +* Permission is hereby granted, free of charge, to any person obtaining a +* copy of this software and associated documentation files (the "Software"), +* to deal in the Software without restriction, including without limitation +* the rights to use, copy, modify, merge, publish, distribute, sublicense, +* and/or sell copies of the Software, and to permit persons to whom the +* Software is furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in +* all copies or substantial portions of the Software. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER +* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING +* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER +* DEALINGS IN THE SOFTWARE. +* +* Prototypes and checks taken from DMTF: Copyright 2021-2022 DMTF. All rights reserved. +* License: BSD 3-Clause License. For full text see link: https://github.com/DMTF/libspdm/blob/main/LICENSE.md +*/ + +#include "internal_crypt_lib.h" + +bool libspdm_aead_aes_gcm_encrypt(const uint8_t *key, size_t key_size, + const uint8_t *iv, size_t iv_size, + const uint8_t *a_data, size_t a_data_size, + const uint8_t *data_in, size_t data_in_size, + uint8_t *tag_out, size_t tag_size, + uint8_t *data_out, size_t *data_out_size) +{ + int32_t ret; + + if (data_in_size > INT_MAX) { + return false; + } + if (a_data_size > INT_MAX) { + return false; + } + if (iv_size != 12) { + return false; + } + switch (key_size) { + case 16: + case 24: + case 32: + break; + default: + return false; + } + if ((tag_size < 12) || (tag_size > 16)) { + return false; + } + if (data_out_size != NULL) { + if ((*data_out_size > INT_MAX) || + (*data_out_size < data_in_size)) { + return false; + } + } + + ret = libspdm_aead(key, key_size, iv, iv_size, a_data, a_data_size, + data_in, data_in_size, tag_out, tag_size, + data_out, data_out_size, true, "gcm(aes)"); + + *data_out_size = data_in_size; + + return ret == 0; +} + +bool libspdm_aead_aes_gcm_decrypt(const uint8_t *key, size_t key_size, + const uint8_t *iv, size_t iv_size, + const uint8_t *a_data, size_t a_data_size, + const uint8_t *data_in, size_t data_in_size, + const uint8_t *tag, size_t tag_size, + uint8_t *data_out, size_t *data_out_size) +{ + int ret; + if (data_in_size > INT_MAX) { + return false; + } + if (a_data_size > INT_MAX) { + return false; + } + if (iv_size != 12) { + return false; + } + switch (key_size) { + case 16: + case 24: + case 32: + break; + default: + return false; + } + if ((tag_size < 12) || (tag_size > 16)) { + return false; + } + if (data_out_size != NULL) { + if ((*data_out_size > INT_MAX) || + (*data_out_size < data_in_size)) { + return false; + } + } + + ret = libspdm_aead(key, key_size, iv, iv_size, a_data, a_data_size, + data_in, data_in_size, tag, tag_size, + data_out, data_out_size, false, "gcm(aes)"); + + *data_out_size = data_in_size; + + return ret == 0; + +} diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/kernel-open/nvidia/libspdm_ec.c nvidia-open-gpu-kernel-modules-535.161.08/kernel-open/nvidia/libspdm_ec.c --- nvidia-open-gpu-kernel-modules-525.147.05/kernel-open/nvidia/libspdm_ec.c 1970-01-01 00:00:00.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/kernel-open/nvidia/libspdm_ec.c 2024-03-05 22:25:36.000000000 +0000 @@ -0,0 +1,172 @@ +/* +* SPDX-FileCopyrightText: Copyright (c) 2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. +* SPDX-License-Identifier: MIT +* +* Permission is hereby granted, free of charge, to any person obtaining a +* copy of this software and associated documentation files (the "Software"), +* to deal in the Software without restriction, including without limitation +* the rights to use, copy, modify, merge, publish, distribute, sublicense, +* and/or sell copies of the Software, and to permit persons to whom the +* Software is furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in +* all copies or substantial portions of the Software. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER +* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING +* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER +* DEALINGS IN THE SOFTWARE. +* +* Comments, prototypes and checks taken from DMTF: Copyright 2021-2022 DMTF. All rights reserved. +* License: BSD 3-Clause License. For full text see link: https://github.com/DMTF/libspdm/blob/main/LICENSE.md +*/ + +#include "internal_crypt_lib.h" + +static bool lkca_ecdsa_sign(void *ec_context, + const uint8_t *message_hash, size_t hash_size, + uint8_t *signature, size_t *sig_size) +{ + return false; +} + +bool libspdm_ec_set_pub_key(void *ec_context, const uint8_t *public_key, + size_t public_key_size) +{ + if (ec_context == NULL || public_key == NULL) { + return false; + } + + return lkca_ec_set_pub_key(ec_context, public_key, public_key_size); +} + +bool libspdm_ec_get_pub_key(void *ec_context, uint8_t *public_key, + size_t *public_key_size) +{ + if (ec_context == NULL || public_key_size == NULL) { + return false; + } + + if (public_key == NULL && *public_key_size != 0) { + return false; + } + + return lkca_ec_get_pub_key(ec_context, public_key, public_key_size); +} + +bool libspdm_ec_check_key(const void *ec_context) +{ + /* TBD*/ + return true; +} + +bool libspdm_ec_generate_key(void *ec_context, uint8_t *public_data, + size_t *public_size) +{ + if (ec_context == NULL || public_size == NULL) { + return false; + } + + if (public_data == NULL && *public_size != 0) { + return false; + } + + return lkca_ec_generate_key(ec_context, public_data, public_size); +} + +bool libspdm_ec_compute_key(void *ec_context, const uint8_t *peer_public, + size_t peer_public_size, uint8_t *key, + size_t *key_size) +{ + if (ec_context == NULL || peer_public == NULL || key_size == NULL || + key == NULL) { + return false; + } + + if (peer_public_size > INT_MAX) { + return false; + } + + return lkca_ec_compute_key(ec_context, peer_public, peer_public_size, key, + key_size); +} + +bool libspdm_ecdsa_sign(void *ec_context, size_t hash_nid, + const uint8_t *message_hash, size_t hash_size, + uint8_t *signature, size_t *sig_size) +{ + if (ec_context == NULL || message_hash == NULL) { + return false; + } + + if (signature == NULL) { + return false; + } + + switch (hash_nid) { + case LIBSPDM_CRYPTO_NID_SHA256: + if (hash_size != LIBSPDM_SHA256_DIGEST_SIZE) { + return false; + } + break; + + case LIBSPDM_CRYPTO_NID_SHA384: + if (hash_size != LIBSPDM_SHA384_DIGEST_SIZE) { + return false; + } + break; + + case LIBSPDM_CRYPTO_NID_SHA512: + if (hash_size != LIBSPDM_SHA512_DIGEST_SIZE) { + return false; + } + break; + + default: + return false; + } + + return lkca_ecdsa_sign(ec_context, message_hash, hash_size, signature, sig_size); +} + +bool libspdm_ecdsa_verify(void *ec_context, size_t hash_nid, + const uint8_t *message_hash, size_t hash_size, + const uint8_t *signature, size_t sig_size) +{ + if (ec_context == NULL || message_hash == NULL || signature == NULL) { + return false; + } + + if (sig_size > INT_MAX || sig_size == 0) { + return false; + } + + switch (hash_nid) { + case LIBSPDM_CRYPTO_NID_SHA256: + if (hash_size != LIBSPDM_SHA256_DIGEST_SIZE) { + return false; + } + break; + + case LIBSPDM_CRYPTO_NID_SHA384: + if (hash_size != LIBSPDM_SHA384_DIGEST_SIZE) { + return false; + } + break; + + case LIBSPDM_CRYPTO_NID_SHA512: + if (hash_size != LIBSPDM_SHA512_DIGEST_SIZE) { + return false; + } + break; + + default: + return false; + } + + return lkca_ecdsa_verify(ec_context, hash_nid, message_hash, hash_size, + signature, sig_size); +} diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/kernel-open/nvidia/libspdm_ecc.c nvidia-open-gpu-kernel-modules-535.161.08/kernel-open/nvidia/libspdm_ecc.c --- nvidia-open-gpu-kernel-modules-525.147.05/kernel-open/nvidia/libspdm_ecc.c 1970-01-01 00:00:00.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/kernel-open/nvidia/libspdm_ecc.c 2024-03-05 22:25:36.000000000 +0000 @@ -0,0 +1,326 @@ +/* +* SPDX-FileCopyrightText: Copyright (c) 2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. +* SPDX-License-Identifier: MIT +* +* Permission is hereby granted, free of charge, to any person obtaining a +* copy of this software and associated documentation files (the "Software"), +* to deal in the Software without restriction, including without limitation +* the rights to use, copy, modify, merge, publish, distribute, sublicense, +* and/or sell copies of the Software, and to permit persons to whom the +* Software is furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in +* all copies or substantial portions of the Software. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER +* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING +* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER +* DEALINGS IN THE SOFTWARE. +*/ + +#include "internal_crypt_lib.h" + +#ifdef USE_LKCA +#include +MODULE_SOFTDEP("pre: ecdh_generic,ecdsa_generic"); + +#include +#include +#include + +struct ecc_ctx { + unsigned int curve_id; + u64 priv_key[ECC_MAX_DIGITS]; // In big endian + + struct { + // ecdsa wants byte preceding pub_key to be set to '4' + u64 pub_key_prefix; + u64 pub_key[2 * ECC_MAX_DIGITS]; + }; + + bool pub_key_set; + bool priv_key_set; + char const *name; + int size; +}; +#endif + +void *libspdm_ec_new_by_nid(size_t nid) +{ +#ifndef USE_LKCA + return NULL; +#else + struct ecc_ctx *ctx; + + if ((nid != LIBSPDM_CRYPTO_NID_SECP256R1) && (nid != LIBSPDM_CRYPTO_NID_SECP384R1)){ + return NULL; + } + + ctx = kmalloc(sizeof(*ctx), GFP_KERNEL); + if (!ctx) { + return NULL; + } + + if (nid == LIBSPDM_CRYPTO_NID_SECP256R1) { + ctx->curve_id = ECC_CURVE_NIST_P256; + ctx->size = 64; + ctx->name = "ecdsa-nist-p256"; + } else { + ctx->curve_id = ECC_CURVE_NIST_P384; + ctx->size = 96; + ctx->name = "ecdsa-nist-p384"; + } + ctx->pub_key_set = false; + ctx->priv_key_set = false; + + return ctx; +#endif +} + +void libspdm_ec_free(void *ec_context) +{ +#ifdef USE_LKCA + kfree(ec_context); +#endif +} + +bool lkca_ecdsa_set_priv_key(void *context, uint8_t *key, size_t key_size) +{ +#ifndef USE_LKCA + return false; +#else + struct ecc_ctx *ctx = context; + unsigned int ndigits = ctx->size / 16; + + if (key_size != (ctx->size / 2)) { + return false; + } + + memcpy(ctx->priv_key, key, key_size); + + // XXX: if this fails, do we want to retry generating new key? + if(ecc_make_pub_key(ctx->curve_id, ndigits, ctx->priv_key, ctx->pub_key)) { + return false; + } + + ctx->pub_key_set = true; + ctx->priv_key_set = true; + return true; +#endif +} + +bool lkca_ec_set_pub_key(void *ec_context, const uint8_t *public_key, + size_t public_key_size) +{ +#ifndef USE_LKCA + return false; +#else + struct ecc_ctx *ctx = ec_context; + struct ecc_point pub_key; + unsigned int ndigits; + + if (public_key_size != ctx->size) { + return false; + } + + // We can reuse pub_key for now + ndigits = ctx->size / 16; + pub_key = ECC_POINT_INIT(ctx->pub_key, ctx->pub_key + ndigits, ndigits); + + ecc_swap_digits(public_key, ctx->pub_key, ndigits); + ecc_swap_digits(((u64 *)public_key) + ndigits, ctx->pub_key + ndigits, ndigits); + if(ecc_is_pubkey_valid_full(ecc_get_curve(ctx->curve_id), &pub_key)) { + return false; + } + + memcpy(ctx->pub_key, public_key, public_key_size); + ctx->pub_key_set = true; + return true; +#endif +} + +bool lkca_ec_get_pub_key(void *ec_context, uint8_t *public_key, + size_t *public_key_size) +{ +#ifndef USE_LKCA + return false; +#else + struct ecc_ctx *ctx = ec_context; + + if (*public_key_size < ctx->size) { + *public_key_size = ctx->size; + return false; + } + *public_key_size = ctx->size; + + memcpy(public_key, ctx->pub_key, ctx->size); + return true; +#endif +} + +bool lkca_ec_generate_key(void *ec_context, uint8_t *public_data, + size_t *public_size) +{ +#ifndef USE_LKCA + return false; +#else + struct ecc_ctx *ctx = ec_context; + + unsigned int ndigits = ctx->size / 16; + + if(ecc_gen_privkey(ctx->curve_id, ndigits, ctx->priv_key)) { + return false; + } + // XXX: if this fails, do we want to retry generating new key? + if(ecc_make_pub_key(ctx->curve_id, ndigits, ctx->priv_key, ctx->pub_key)) { + return false; + } + + memcpy(public_data, ctx->pub_key, ctx->size); + *public_size = ctx->size; + ctx->priv_key_set = true; + ctx->pub_key_set = true; + + return true; +#endif +} + +bool lkca_ec_compute_key(void *ec_context, const uint8_t *peer_public, + size_t peer_public_size, uint8_t *key, + size_t *key_size) +{ +#ifndef USE_LKCA + return false; +#else + struct ecc_ctx *ctx = ec_context; + + if (peer_public_size != ctx->size) { + return false; + } + + if (!ctx->priv_key_set) { + return false; + } + + if ((ctx->size / 2) > *key_size) { + return false; + } + + if (crypto_ecdh_shared_secret(ctx->curve_id, ctx->size / 16, + (const u64 *) ctx->priv_key, + (const u64 *) peer_public, + (u64 *) key)) { + return false; + } + + *key_size = ctx->size / 2; + return true; +#endif +} + +bool lkca_ecdsa_verify(void *ec_context, size_t hash_nid, + const uint8_t *message_hash, size_t hash_size, + const uint8_t *signature, size_t sig_size) +{ +#ifndef USE_LKCA + return false; +#else + struct ecc_ctx *ctx = ec_context; + + // Roundabout way + u64 ber_max_len = 3 + 2 * (4 + (ECC_MAX_BYTES)); + u64 ber_len = 0; + u8 *ber = NULL; + u8 *pub_key; + struct akcipher_request *req = NULL; + struct crypto_akcipher *tfm = NULL; + struct scatterlist sg; + DECLARE_CRYPTO_WAIT(wait); + int err; + + if (sig_size != ctx->size) { + return false; + } + + if(ctx->pub_key_set == false){ + return false; + } + + tfm = crypto_alloc_akcipher(ctx->name, CRYPTO_ALG_TYPE_AKCIPHER, 0); + if (IS_ERR(tfm)) { + pr_info("ALLOC FAILED\n"); + return false; + } + + pub_key = (u8 *) ctx->pub_key; + pub_key--; // Go back into byte of pub_key_prefix + *pub_key = 4; // And set it to 4 to placate kernel + if ((err = crypto_akcipher_set_pub_key(tfm, pub_key, ctx->size + 1)) != 0) { + pr_info("SET PUB KEY FAILED: %d\n", -err); + goto failTfm; + } + + req = akcipher_request_alloc(tfm, GFP_KERNEL); + if (IS_ERR(req)) { + pr_info("REQUEST ALLOC FAILED\n"); + goto failTfm; + } + + // We concatenate signature and hash and ship it to kernel + ber = kmalloc(ber_max_len + hash_size, GFP_KERNEL); + if (ber == NULL) { + goto failReq; + } + + // XXX: NOTE THIS WILL WORK ONLY FOR 256 AND 384 bits. For larger keys + // length field will be longer than 1 byte and I haven't taken care of that! + + // Signature + ber[ber_len++] = 0x30; + ber[ber_len++] = 2 * (2 + ctx->size / 2); + ber[ber_len++] = 0x02; + if (signature[0] > 127) { + ber[ber_len++] = ctx->size / 2 + 1; + ber[1]++; + ber[ber_len++] = 0; + } else { + ber[ber_len++] = ctx->size / 2; + } + memcpy(ber + ber_len, signature, sig_size / 2); + ber_len += sig_size / 2; + ber[ber_len++] = 0x02; + if (signature[sig_size / 2] > 127) { + ber[ber_len++] = ctx->size / 2 + 1; + ber[1]++; + ber[ber_len++] = 0; + } else { + ber[ber_len++] = ctx->size / 2; + } + memcpy(ber + ber_len, signature + sig_size / 2, sig_size / 2); + ber_len += sig_size / 2; + + // Just append hash, for scatterlists it can't be on stack anyway + memcpy(ber + ber_len, message_hash, hash_size); + + sg_init_one(&sg, ber, ber_len + hash_size); + akcipher_request_set_callback(req, CRYPTO_TFM_REQ_MAY_BACKLOG | + CRYPTO_TFM_REQ_MAY_SLEEP, crypto_req_done, &wait); + akcipher_request_set_crypt(req, &sg, NULL, ber_len, hash_size); + err = crypto_wait_req(crypto_akcipher_verify(req), &wait); + + if (err != 0){ + pr_info("Verify FAILED %d\n", -err); + } + + kfree(ber); +failReq: + akcipher_request_free(req); +failTfm: + crypto_free_akcipher(tfm); + + return err == 0; +#endif +} diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/kernel-open/nvidia/libspdm_hkdf.c nvidia-open-gpu-kernel-modules-535.161.08/kernel-open/nvidia/libspdm_hkdf.c --- nvidia-open-gpu-kernel-modules-525.147.05/kernel-open/nvidia/libspdm_hkdf.c 1970-01-01 00:00:00.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/kernel-open/nvidia/libspdm_hkdf.c 2024-03-05 22:25:36.000000000 +0000 @@ -0,0 +1,158 @@ +/* +* SPDX-FileCopyrightText: Copyright (c) 2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. +* SPDX-License-Identifier: MIT +* +* Permission is hereby granted, free of charge, to any person obtaining a +* copy of this software and associated documentation files (the "Software"), +* to deal in the Software without restriction, including without limitation +* the rights to use, copy, modify, merge, publish, distribute, sublicense, +* and/or sell copies of the Software, and to permit persons to whom the +* Software is furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in +* all copies or substantial portions of the Software. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER +* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING +* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER +* DEALINGS IN THE SOFTWARE. +*/ + +#include "internal_crypt_lib.h" + +// RFC 5869 has some very non-intuitive points, reading it is advised +static bool lkca_hkdf_expand_only(struct crypto_shash *alg, + const uint8_t *prk, size_t prk_size, + const uint8_t *info, size_t info_size, + uint8_t *out, size_t out_size) +{ +#ifndef USE_LKCA + return false; +#else + int ret; + int i; + uint8_t ctr = 1; + uint8_t tmp[HASH_MAX_DIGESTSIZE]; + SHASH_DESC_ON_STACK(desc, alg); + desc->tfm = alg; + + ret = crypto_shash_setkey(desc->tfm, prk, prk_size); + if (ret != 0) { + pr_info("key size mismatch %ld\n", prk_size); + return false; + } + + for (i = 0, ctr = 1; i < out_size; i += prk_size, ctr++) { + ret = crypto_shash_init(desc); + if (ret) { + return false; + } + + if (i != 0) { + ret = crypto_shash_update(desc, out + i - prk_size, prk_size); + if (ret) { + return false; + } + } + + if (info_size > 0) { + ret = crypto_shash_update(desc, info, info_size); + if (ret) { + return false; + } + } + + ret = crypto_shash_update(desc, &ctr, 1); + if (ret) + return false; + + if ((out_size - i) < prk_size) { + ret = crypto_shash_final(desc, tmp); + if (ret) { + return false; + } + memcpy(out + i, tmp, out_size - i); + memzero_explicit(tmp, sizeof(tmp)); + } else { + ret = crypto_shash_final(desc, out + i); + if (ret) { + return false; + } + } + } + + return true; +#endif +} + +bool lkca_hkdf_extract_and_expand(const char *alg_name, + const uint8_t *key, size_t key_size, + const uint8_t *salt, size_t salt_size, + const uint8_t *info, size_t info_size, + uint8_t *out, size_t out_size) +{ +#ifndef USE_LKCA + return false; +#else + int ret = 0; + struct crypto_shash *alg; + uint8_t prk[HASH_MAX_DIGESTSIZE]; + + if (key == NULL || salt == NULL || info == NULL || out == NULL || + key_size > sizeof(prk) || salt_size > INT_MAX || info_size > INT_MAX || + out_size > (sizeof(prk) * 255)) { + return false; + } + + alg = crypto_alloc_shash(alg_name, 0, 0); + if (IS_ERR(alg)) { + return false; + } + + ret = crypto_shash_setkey(alg, salt, salt_size); + if (ret != 0) { + goto out; + } + ret = crypto_shash_tfm_digest(alg, key, key_size, prk); + if (ret != 0) { + goto out; + } + + ret = !lkca_hkdf_expand_only(alg, prk, crypto_shash_digestsize(alg), info, info_size, out, out_size); + +out: + crypto_free_shash(alg); + return ret == 0; +#endif +} + +bool lkca_hkdf_expand(const char *alg_name, + const uint8_t *prk, size_t prk_size, + const uint8_t *info, size_t info_size, + uint8_t *out, size_t out_size) +{ +#ifndef USE_LKCA + return false; +#else + bool ret = false; + struct crypto_shash *alg; + + if (prk == NULL || info == NULL || out == NULL || prk_size > (512 / 8) || + info_size > INT_MAX || (out_size > (prk_size * 255))) { + return false; + } + + alg = crypto_alloc_shash(alg_name, 0, 0); + if (IS_ERR(alg)) { + return false; + } + + ret = lkca_hkdf_expand_only(alg, prk, prk_size, info, info_size, out, out_size); + + crypto_free_shash(alg); + return ret; +#endif +} diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/kernel-open/nvidia/libspdm_hkdf_sha.c nvidia-open-gpu-kernel-modules-535.161.08/kernel-open/nvidia/libspdm_hkdf_sha.c --- nvidia-open-gpu-kernel-modules-525.147.05/kernel-open/nvidia/libspdm_hkdf_sha.c 1970-01-01 00:00:00.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/kernel-open/nvidia/libspdm_hkdf_sha.c 2024-03-05 22:25:36.000000000 +0000 @@ -0,0 +1,111 @@ +/* +* SPDX-FileCopyrightText: Copyright (c) 2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. +* SPDX-License-Identifier: MIT +* +* Permission is hereby granted, free of charge, to any person obtaining a +* copy of this software and associated documentation files (the "Software"), +* to deal in the Software without restriction, including without limitation +* the rights to use, copy, modify, merge, publish, distribute, sublicense, +* and/or sell copies of the Software, and to permit persons to whom the +* Software is furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in +* all copies or substantial portions of the Software. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER +* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING +* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER +* DEALINGS IN THE SOFTWARE. +* +* Prototypes and checks taken from DMTF: Copyright 2021-2022 DMTF. All rights reserved. +* License: BSD 3-Clause License. For full text see link: https://github.com/DMTF/libspdm/blob/main/LICENSE.md +*/ + +#include "internal_crypt_lib.h" + +bool libspdm_hkdf_sha256_extract_and_expand(const uint8_t *key, size_t key_size, + const uint8_t *salt, size_t salt_size, + const uint8_t *info, size_t info_size, + uint8_t *out, size_t out_size) +{ + return lkca_hkdf_extract_and_expand("hmac(sha256)", key, key_size, + salt, salt_size, info, info_size, + out, out_size); +} + +bool libspdm_hkdf_sha256_extract(const uint8_t *key, size_t key_size, + const uint8_t *salt, size_t salt_size, + uint8_t *prk_out, size_t prk_out_size) +{ + if (prk_out_size != (256 / 8)) + return false; + + return libspdm_hmac_sha256_all(key, key_size, salt, salt_size, prk_out); +} + +bool libspdm_hkdf_sha256_expand(const uint8_t *prk, size_t prk_size, + const uint8_t *info, size_t info_size, + uint8_t *out, size_t out_size) +{ + return lkca_hkdf_expand("hmac(sha256)", prk, prk_size, info, info_size, + out, out_size); +} + +bool libspdm_hkdf_sha384_extract_and_expand(const uint8_t *key, size_t key_size, + const uint8_t *salt, size_t salt_size, + const uint8_t *info, size_t info_size, + uint8_t *out, size_t out_size) +{ + return lkca_hkdf_extract_and_expand("hmac(sha384)", key, key_size, + salt, salt_size, info, info_size, + out, out_size); +} + +bool libspdm_hkdf_sha384_extract(const uint8_t *key, size_t key_size, + const uint8_t *salt, size_t salt_size, + uint8_t *prk_out, size_t prk_out_size) +{ + if (prk_out_size != (384 / 8)) + return false; + + return libspdm_hmac_sha384_all(key, key_size, salt, salt_size, prk_out); +} + +bool libspdm_hkdf_sha384_expand(const uint8_t *prk, size_t prk_size, + const uint8_t *info, size_t info_size, + uint8_t *out, size_t out_size) +{ + return lkca_hkdf_expand("hmac(sha384)", prk, prk_size, info, info_size, + out, out_size); +} + +bool libspdm_hkdf_sha512_extract_and_expand(const uint8_t *key, size_t key_size, + const uint8_t *salt, size_t salt_size, + const uint8_t *info, size_t info_size, + uint8_t *out, size_t out_size) +{ + return lkca_hkdf_extract_and_expand("hmac(sha512)", key, key_size, + salt, salt_size, info, info_size, out, + out_size); +} + +bool libspdm_hkdf_sha512_extract(const uint8_t *key, size_t key_size, + const uint8_t *salt, size_t salt_size, + uint8_t *prk_out, size_t prk_out_size) +{ + if (prk_out_size != (512 / 8)) + return false; + + return libspdm_hmac_sha512_all(key, key_size, salt, salt_size, prk_out); +} + +bool libspdm_hkdf_sha512_expand(const uint8_t *prk, size_t prk_size, + const uint8_t *info, size_t info_size, + uint8_t *out, size_t out_size) +{ + return lkca_hkdf_expand("hmac(sha512)", prk, prk_size, info, info_size, + out, out_size); +} diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/kernel-open/nvidia/libspdm_hmac_sha.c nvidia-open-gpu-kernel-modules-535.161.08/kernel-open/nvidia/libspdm_hmac_sha.c --- nvidia-open-gpu-kernel-modules-525.147.05/kernel-open/nvidia/libspdm_hmac_sha.c 1970-01-01 00:00:00.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/kernel-open/nvidia/libspdm_hmac_sha.c 2024-03-05 22:25:36.000000000 +0000 @@ -0,0 +1,282 @@ +/* +* SPDX-FileCopyrightText: Copyright (c) 2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. +* SPDX-License-Identifier: MIT +* +* Permission is hereby granted, free of charge, to any person obtaining a +* copy of this software and associated documentation files (the "Software"), +* to deal in the Software without restriction, including without limitation +* the rights to use, copy, modify, merge, publish, distribute, sublicense, +* and/or sell copies of the Software, and to permit persons to whom the +* Software is furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in +* all copies or substantial portions of the Software. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER +* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING +* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER +* DEALINGS IN THE SOFTWARE. +* +* Prototypes and checks taken from DMTF: Copyright 2021-2022 DMTF. All rights reserved. +* License: BSD 3-Clause License. For full text see link: https://github.com/DMTF/libspdm/blob/main/LICENSE.md +*/ + +#include "internal_crypt_lib.h" + +void *libspdm_hmac_sha256_new(void) +{ + return lkca_hash_new("hmac(sha256)"); +} + +void libspdm_hmac_sha256_free(void *hmac_sha256_ctx) +{ + lkca_hash_free(hmac_sha256_ctx); +} + +bool libspdm_hmac_sha256_set_key(void *hmac_sha256_ctx, const uint8_t *key, + size_t key_size) +{ + if (hmac_sha256_ctx == NULL) + return false; + + return lkca_hmac_set_key(hmac_sha256_ctx, key, key_size); +} + +bool libspdm_hmac_sha256_duplicate(const void *hmac_sha256_ctx, + void *new_hmac_sha256_ctx) +{ + if (hmac_sha256_ctx == NULL || new_hmac_sha256_ctx == NULL) { + return false; + } + + return lkca_hmac_duplicate(new_hmac_sha256_ctx, hmac_sha256_ctx); +} + +bool libspdm_hmac_sha256_update(void *hmac_sha256_ctx, const void *data, + size_t data_size) +{ + int32_t ret; + + if (hmac_sha256_ctx == NULL) { + return false; + } + + if (data == NULL && data_size != 0) { + return false; + } + if (data_size > INT_MAX) { + return false; + } + + ret = crypto_shash_update(hmac_sha256_ctx, data, data_size); + if (ret != 0) { + return false; + } + return true; +} + +bool libspdm_hmac_sha256_final(void *hmac_sha256_ctx, uint8_t *hmac_value) +{ + int32_t ret; + + if (hmac_sha256_ctx == NULL || hmac_value == NULL) { + return false; + } + + ret = crypto_shash_final(hmac_sha256_ctx, hmac_value); + + if (ret != 0) { + return false; + } + return true; +} + +bool libspdm_hmac_sha256_all(const void *data, size_t data_size, + const uint8_t *key, size_t key_size, + uint8_t *hmac_value) +{ + if (hmac_value == NULL) { + return false; + } + if (data == NULL && data_size != 0) { + return false; + } + if (data_size > INT_MAX) { + return false; + } + + return lkca_hmac_all("hmac(sha256)", key, key_size, data, data_size, hmac_value); +} + +void *libspdm_hmac_sha384_new(void) +{ + return lkca_hash_new("hmac(sha384)"); +} + +void libspdm_hmac_sha384_free(void *hmac_sha384_ctx) +{ + lkca_hash_free(hmac_sha384_ctx); +} + +bool libspdm_hmac_sha384_set_key(void *hmac_sha384_ctx, const uint8_t *key, + size_t key_size) +{ + if (hmac_sha384_ctx == NULL) + return false; + + return lkca_hmac_set_key(hmac_sha384_ctx, key, key_size); +} + +bool libspdm_hmac_sha384_duplicate(const void *hmac_sha384_ctx, + void *new_hmac_sha384_ctx) +{ + if (hmac_sha384_ctx == NULL || new_hmac_sha384_ctx == NULL) { + return false; + } + + return lkca_hmac_duplicate(new_hmac_sha384_ctx, hmac_sha384_ctx); +} + +bool libspdm_hmac_sha384_update(void *hmac_sha384_ctx, const void *data, + size_t data_size) +{ + int32_t ret; + + if (hmac_sha384_ctx == NULL) { + return false; + } + + if (data == NULL && data_size != 0) { + return false; + } + if (data_size > INT_MAX) { + return false; + } + + ret = crypto_shash_update(hmac_sha384_ctx, data, data_size); + if (ret != 0) { + return false; + } + return true; +} + +bool libspdm_hmac_sha384_final(void *hmac_sha384_ctx, uint8_t *hmac_value) +{ + int32_t ret; + + if (hmac_sha384_ctx == NULL || hmac_value == NULL) { + return false; + } + + ret = crypto_shash_final(hmac_sha384_ctx, hmac_value); + + if (ret != 0) { + return false; + } + return true; +} + +bool libspdm_hmac_sha384_all(const void *data, size_t data_size, + const uint8_t *key, size_t key_size, + uint8_t *hmac_value) +{ + if (hmac_value == NULL) { + return false; + } + if (data == NULL && data_size != 0) { + return false; + } + if (data_size > INT_MAX) { + return false; + } + + return lkca_hmac_all("hmac(sha384)", key, key_size, data, data_size, hmac_value); +} + +void *libspdm_hmac_sha512_new(void) +{ + return lkca_hash_new("hmac(sha512)"); +} + +void libspdm_hmac_sha512_free(void *hmac_sha512_ctx) +{ + lkca_hash_free(hmac_sha512_ctx); +} + +bool libspdm_hmac_sha512_set_key(void *hmac_sha512_ctx, const uint8_t *key, + size_t key_size) +{ + if (hmac_sha512_ctx == NULL) + return false; + + return lkca_hmac_set_key(hmac_sha512_ctx, key, key_size); +} + +bool libspdm_hmac_sha512_duplicate(const void *hmac_sha512_ctx, + void *new_hmac_sha512_ctx) +{ + if (new_hmac_sha512_ctx == NULL || new_hmac_sha512_ctx == NULL) { + return false; + } + + return lkca_hmac_duplicate(new_hmac_sha512_ctx, hmac_sha512_ctx); +} + +bool libspdm_hmac_sha512_update(void *hmac_sha512_ctx, const void *data, + size_t data_size) +{ + int32_t ret; + + if (hmac_sha512_ctx == NULL) { + return false; + } + + if (data == NULL && data_size != 0) { + return false; + } + if (data_size > INT_MAX) { + return false; + } + + ret = crypto_shash_update(hmac_sha512_ctx, data, data_size); + if (ret != 0) { + return false; + } + return true; +} + +bool libspdm_hmac_sha512_final(void *hmac_sha512_ctx, uint8_t *hmac_value) +{ + int32_t ret; + + if (hmac_sha512_ctx == NULL || hmac_value == NULL) { + return false; + } + + ret = crypto_shash_final(hmac_sha512_ctx, hmac_value); + + if (ret != 0) { + return false; + } + return true; +} + +bool libspdm_hmac_sha512_all(const void *data, size_t data_size, + const uint8_t *key, size_t key_size, + uint8_t *hmac_value) +{ + if (hmac_value == NULL) { + return false; + } + if (data == NULL && data_size != 0) { + return false; + } + if (data_size > INT_MAX) { + return false; + } + + return lkca_hmac_all("hmac(sha512)", key, key_size, data, data_size, hmac_value); +} diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/kernel-open/nvidia/libspdm_rand.c nvidia-open-gpu-kernel-modules-535.161.08/kernel-open/nvidia/libspdm_rand.c --- nvidia-open-gpu-kernel-modules-525.147.05/kernel-open/nvidia/libspdm_rand.c 1970-01-01 00:00:00.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/kernel-open/nvidia/libspdm_rand.c 2024-03-05 22:25:36.000000000 +0000 @@ -0,0 +1,37 @@ +/* +* SPDX-FileCopyrightText: Copyright (c) 2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. +* SPDX-License-Identifier: MIT +* +* Permission is hereby granted, free of charge, to any person obtaining a +* copy of this software and associated documentation files (the "Software"), +* to deal in the Software without restriction, including without limitation +* the rights to use, copy, modify, merge, publish, distribute, sublicense, +* and/or sell copies of the Software, and to permit persons to whom the +* Software is furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in +* all copies or substantial portions of the Software. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER +* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING +* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER +* DEALINGS IN THE SOFTWARE. +*/ + +#include "internal_crypt_lib.h" + +// This is non-gpl symbol and not part of LKCA so no need to stub it out +bool libspdm_random_bytes(uint8_t *output, size_t size) +{ + get_random_bytes(output, size); + return true; +} + +// This is specifically allowed by spdm +bool libspdm_random_seed(const uint8_t *seed, size_t seed_size) +{ + return true; +} diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/kernel-open/nvidia/libspdm_sha.c nvidia-open-gpu-kernel-modules-535.161.08/kernel-open/nvidia/libspdm_sha.c --- nvidia-open-gpu-kernel-modules-525.147.05/kernel-open/nvidia/libspdm_sha.c 1970-01-01 00:00:00.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/kernel-open/nvidia/libspdm_sha.c 2024-03-05 22:25:36.000000000 +0000 @@ -0,0 +1,264 @@ +/* +* SPDX-FileCopyrightText: Copyright (c) 2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. +* SPDX-License-Identifier: MIT +* +* Permission is hereby granted, free of charge, to any person obtaining a +* copy of this software and associated documentation files (the "Software"), +* to deal in the Software without restriction, including without limitation +* the rights to use, copy, modify, merge, publish, distribute, sublicense, +* and/or sell copies of the Software, and to permit persons to whom the +* Software is furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in +* all copies or substantial portions of the Software. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER +* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING +* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER +* DEALINGS IN THE SOFTWARE. +* +* Comments, prototypes and checks taken from DMTF: Copyright 2021-2022 DMTF. All rights reserved. +* License: BSD 3-Clause License. For full text see link: https://github.com/DMTF/libspdm/blob/main/LICENSE.md +*/ + +#include "internal_crypt_lib.h" + +void *libspdm_sha256_new(void) +{ + return lkca_hash_new("sha256"); +} + +void libspdm_sha256_free(void *sha256_ctx) +{ + lkca_hash_free(sha256_ctx); +} + +bool libspdm_sha256_init(void *sha256_context) +{ + return crypto_shash_init(sha256_context) == 0; +} + +bool libspdm_sha256_duplicate(const void *sha256_context, + void *new_sha256_context) +{ + if (sha256_context == NULL || new_sha256_context == NULL) { + return false; + } + + return lkca_hash_duplicate(new_sha256_context, sha256_context); +} + +bool libspdm_sha256_update(void *sha256_context, const void *data, + size_t data_size) +{ + int32_t ret; + + if (sha256_context == NULL) { + return false; + } + + if (data == NULL && data_size != 0) { + return false; + } + if (data_size > INT_MAX) { + return false; + } + + ret = crypto_shash_update(sha256_context, data, data_size); + if (ret != 0) { + return false; + } + return true; +} + +bool libspdm_sha256_final(void *sha256_context, uint8_t *hash_value) +{ + int32_t ret; + + if (sha256_context == NULL || hash_value == NULL) { + return false; + } + + ret = crypto_shash_final(sha256_context, hash_value); + if (ret != 0) { + return false; + } + return true; +} + +bool libspdm_sha256_hash_all(const void *data, size_t data_size, + uint8_t *hash_value) +{ + if (hash_value == NULL) { + return false; + } + if (data == NULL && data_size != 0) { + return false; + } + if (data_size > INT_MAX) { + return false; + } + + return lkca_hash_all("sha256", data, data_size, hash_value); +} + +void *libspdm_sha384_new(void) +{ + return lkca_hash_new("sha384"); +} + +void libspdm_sha384_free(void *sha384_ctx) +{ + lkca_hash_free(sha384_ctx); +} + +bool libspdm_sha384_init(void *sha384_context) +{ + return crypto_shash_init(sha384_context) == 0; +} + +bool libspdm_sha384_duplicate(const void *sha384_context, + void *new_sha384_context) +{ + if (sha384_context == NULL || new_sha384_context == NULL) { + return false; + } + + return lkca_hash_duplicate(new_sha384_context, sha384_context); +} + +bool libspdm_sha384_update(void *sha384_context, const void *data, + size_t data_size) +{ + int32_t ret; + + if (sha384_context == NULL) { + return false; + } + + if (data == NULL && data_size != 0) { + return false; + } + if (data_size > INT_MAX) { + return false; + } + + ret = crypto_shash_update(sha384_context, data, data_size); + if (ret != 0) { + return false; + } + return true; +} + +bool libspdm_sha384_final(void *sha384_context, uint8_t *hash_value) +{ + int32_t ret; + + if (sha384_context == NULL || hash_value == NULL) { + return false; + } + + ret = crypto_shash_final(sha384_context, hash_value); + if (ret != 0) { + return false; + } + return true; +} + +bool libspdm_sha384_hash_all(const void *data, size_t data_size, + uint8_t *hash_value) +{ + if (hash_value == NULL) { + return false; + } + if (data == NULL && data_size != 0) { + return false; + } + if (data_size > INT_MAX) { + return false; + } + + return lkca_hash_all("sha384", data, data_size, hash_value); +} + +void *libspdm_sha512_new(void) +{ + return lkca_hash_new("sha512"); +} + +void libspdm_sha512_free(void *sha512_ctx) +{ + lkca_hash_free(sha512_ctx); +} + +bool libspdm_sha512_init(void *sha512_context) +{ + return crypto_shash_init(sha512_context) == 0; +} + +bool libspdm_sha512_duplicate(const void *sha512_context, + void *new_sha512_context) +{ + if (sha512_context == NULL || new_sha512_context == NULL) { + return false; + } + + return lkca_hash_duplicate(new_sha512_context, sha512_context); +} + +bool libspdm_sha512_update(void *sha512_context, const void *data, + size_t data_size) +{ + int32_t ret; + + if (sha512_context == NULL) { + return false; + } + + if (data == NULL && data_size != 0) { + return false; + } + if (data_size > INT_MAX) { + return false; + } + + ret = crypto_shash_update(sha512_context, data, data_size); + if (ret != 0) { + return false; + } + return true; +} + +bool libspdm_sha512_final(void *sha512_context, uint8_t *hash_value) +{ + int32_t ret; + + if (sha512_context == NULL || hash_value == NULL) { + return false; + } + + ret = crypto_shash_final(sha512_context, hash_value); + if (ret != 0) { + return false; + } + return true; +} + +bool libspdm_sha512_hash_all(const void *data, size_t data_size, + uint8_t *hash_value) +{ + if (hash_value == NULL) { + return false; + } + if (data == NULL && data_size != 0) { + return false; + } + if (data_size > INT_MAX) { + return false; + } + + return lkca_hash_all("sha512", data, data_size, hash_value); +} diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/kernel-open/nvidia/libspdm_shash.c nvidia-open-gpu-kernel-modules-535.161.08/kernel-open/nvidia/libspdm_shash.c --- nvidia-open-gpu-kernel-modules-525.147.05/kernel-open/nvidia/libspdm_shash.c 1970-01-01 00:00:00.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/kernel-open/nvidia/libspdm_shash.c 2024-03-05 22:25:36.000000000 +0000 @@ -0,0 +1,181 @@ +/* +* SPDX-FileCopyrightText: Copyright (c) 2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. +* SPDX-License-Identifier: MIT +* +* Permission is hereby granted, free of charge, to any person obtaining a +* copy of this software and associated documentation files (the "Software"), +* to deal in the Software without restriction, including without limitation +* the rights to use, copy, modify, merge, publish, distribute, sublicense, +* and/or sell copies of the Software, and to permit persons to whom the +* Software is furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in +* all copies or substantial portions of the Software. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER +* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING +* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER +* DEALINGS IN THE SOFTWARE. +*/ + +#include "internal_crypt_lib.h" + +#ifdef USE_LKCA +#ifndef NV_CRYPTO_TFM_CTX_ALIGNED_PRESENT +#include +#endif +#endif + +void *lkca_hash_new(const char* alg_name) +{ +#ifndef USE_LKCA + return NULL; +#else + //XXX: can we reuse crypto_shash part and just allocate desc + struct crypto_shash *alg; + struct shash_desc *desc; + + alg = crypto_alloc_shash(alg_name, 0, 0); + if (IS_ERR(alg)) { + printk (KERN_INFO "Failed to alloc %s\n", alg_name); + return NULL; + } + + desc = kmalloc(sizeof(*desc) + crypto_shash_descsize(alg), GFP_KERNEL); + if (desc == NULL){ + printk (KERN_INFO "Kernel out of mem\n"); + crypto_free_shash(alg); + return NULL; + } + + desc->tfm = alg; + + return desc; +#endif +} + +void lkca_hash_free(struct shash_desc *ctx) +{ +#ifndef USE_LKCA +#else + crypto_free_shash(ctx->tfm); + kfree(ctx); +#endif +} + +bool lkca_hash_duplicate(struct shash_desc *dst, struct shash_desc const *src) +{ +#ifndef USE_LKCA + return false; +#else + SHASH_DESC_ON_STACK(tmp, src); + + if (crypto_shash_export((struct shash_desc *) src, tmp)) { + return false; + } + if (crypto_shash_import(dst, tmp)) { + return false; + } + + return true; +#endif +} + +bool lkca_hmac_duplicate(struct shash_desc *dst, struct shash_desc const *src) +{ +#ifndef USE_LKCA + return false; +#else + // in LKCA hmac export doesn't export ipad/opad, so we need to WAR it + + struct crypto_shash *src_tfm = src->tfm; + struct crypto_shash *dst_tfm = dst->tfm; + int ss = crypto_shash_statesize(dst_tfm); + +#ifdef NV_CRYPTO_TFM_CTX_ALIGNED_PRESENT + char *src_ipad = crypto_tfm_ctx_aligned(&src_tfm->base); + char *dst_ipad = crypto_tfm_ctx_aligned(&dst_tfm->base); +#else + int ctx_size = crypto_shash_alg(dst_tfm)->base.cra_ctxsize; + char *src_ipad = crypto_shash_ctx(src_tfm); + char *dst_ipad = crypto_shash_ctx(dst_tfm); + /* + * Actual struct definition is hidden, so I assume data we need is at + * the end. In 6.0 the struct has a pointer to crpyto_shash followed by: + * 'u8 ipad[statesize];', then 'u8 opad[statesize];' + */ + src_ipad += ctx_size - 2 * ss; + dst_ipad += ctx_size - 2 * ss; +#endif + + memcpy(dst_ipad, src_ipad, crypto_shash_blocksize(src->tfm)); + memcpy(dst_ipad + ss, src_ipad + ss, crypto_shash_blocksize(src->tfm)); + crypto_shash_clear_flags(dst->tfm, CRYPTO_TFM_NEED_KEY); + + return lkca_hash_duplicate(dst, src); +#endif +} + +bool lkca_hash_all(const char* alg_name, const void *data, + size_t data_size, uint8_t *hash_value) +{ +#ifndef USE_LKCA + return false; +#else + int ret; + struct crypto_shash *alg; + alg = crypto_alloc_shash(alg_name, 0, 0); + if (IS_ERR(alg)) { + return false; + } + + ret = crypto_shash_tfm_digest(alg, data, data_size, hash_value); + + crypto_free_shash(alg); + + return (ret == 0); +#endif +} + +bool lkca_hmac_set_key(struct shash_desc *desc, const uint8_t *key, size_t key_size) +{ +#ifndef USE_LKCA + return false; +#else + int ret; + ret = crypto_shash_setkey(desc->tfm, key, key_size); + if (ret == 0) { + ret = crypto_shash_init(desc); + } + return ret == 0; +#endif +} + +bool lkca_hmac_all(const char* alg_name, const uint8_t *key, size_t key_size, + const uint8_t *data, size_t data_size, uint8_t *hash_value) +{ +#ifndef USE_LKCA + return false; +#else + int ret; + struct crypto_shash *alg; + alg = crypto_alloc_shash(alg_name, 0, 0); + if (IS_ERR(alg)) { + return false; + } + + ret = crypto_shash_setkey(alg, key, key_size); + + if (ret == 0){ + ret = crypto_shash_tfm_digest(alg, data, data_size, hash_value); + } + + crypto_free_shash(alg); + + return (ret == 0); +#endif +} + diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/kernel-open/nvidia/libspdm_x509.c nvidia-open-gpu-kernel-modules-535.161.08/kernel-open/nvidia/libspdm_x509.c --- nvidia-open-gpu-kernel-modules-525.147.05/kernel-open/nvidia/libspdm_x509.c 1970-01-01 00:00:00.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/kernel-open/nvidia/libspdm_x509.c 2024-03-05 22:25:36.000000000 +0000 @@ -0,0 +1,456 @@ +/* +* SPDX-FileCopyrightText: Copyright (c) 2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. +* SPDX-License-Identifier: MIT +* +* Permission is hereby granted, free of charge, to any person obtaining a +* copy of this software and associated documentation files (the "Software"), +* to deal in the Software without restriction, including without limitation +* the rights to use, copy, modify, merge, publish, distribute, sublicense, +* and/or sell copies of the Software, and to permit persons to whom the +* Software is furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in +* all copies or substantial portions of the Software. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER +* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING +* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER +* DEALINGS IN THE SOFTWARE. +* +* libspdm_x509_verify_cert_chain, libspdm_x509_get_cert_from_cert_chain, check +* and prototypes taken from DMTF: Copyright 2021-2022 DMTF. All rights reserved. +* License: BSD 3-Clause License. For full text see link: https://github.com/DMTF/libspdm/blob/main/LICENSE.md +*/ + +#include "internal_crypt_lib.h" + +#ifdef USE_LKCA +#include +#include +#endif + +bool libspdm_x509_construct_certificate(const uint8_t *cert, size_t cert_size, + uint8_t **single_x509_cert) +{ + LIBSPDM_ASSERT(false); + return false; +} + +bool libspdm_x509_construct_certificate_stack(uint8_t **x509_stack, ...) +{ + LIBSPDM_ASSERT(false); + return false; +} + +void libspdm_x509_free(void *x509_cert) +{ + LIBSPDM_ASSERT(false); +} + +void libspdm_x509_stack_free(void *x509_stack) +{ + LIBSPDM_ASSERT(false); +} + +static bool lkca_asn1_get_tag(uint8_t const *ptr, uint8_t const *end, + size_t *length, uint32_t tag) +{ + uint64_t max_len = end - ptr; + + // Chain must be less than 1 GB + if ((max_len < 2) || (max_len > (1024 * 1024 * 1024))) { + return false; + } + + // We only deal with universal and application tags + if (ptr[0] != tag) { + return false; + } + + if (ptr[1] < 0x80) { + *length = ptr[1] + 2; + } else if (ptr[1] == 0x81) { + if (max_len < 3) { + return false; + } + *length = ptr[2] + 3; + } else if (ptr[1] == 0x82) { + if (max_len < 4) { + return false; + } + *length = (ptr[2] << 8) + ptr[3] + 4; + } else { + // In theory it could be bigger than 64KB + return false; + } + + if (*length > max_len) { + return false; + } + + return true; +} + +bool libspdm_asn1_get_tag(uint8_t **ptr, const uint8_t *end, size_t *length, + uint32_t tag) +{ + return lkca_asn1_get_tag(*ptr, end, length, tag); +} + +bool libspdm_x509_get_subject_name(const uint8_t *cert, size_t cert_size, + uint8_t *cert_subject, + size_t *subject_size) +{ + LIBSPDM_ASSERT(false); + return false; +} + +bool libspdm_x509_get_common_name(const uint8_t *cert, size_t cert_size, + char *common_name, + size_t *common_name_size) +{ + LIBSPDM_ASSERT(false); + return false; +} + +bool +libspdm_x509_get_organization_name(const uint8_t *cert, size_t cert_size, + char *name_buffer, + size_t *name_buffer_size) +{ + LIBSPDM_ASSERT(false); + return false; +} + +#if (LIBSPDM_RSA_SSA_SUPPORT) || (LIBSPDM_RSA_PSS_SUPPORT) +bool libspdm_rsa_get_public_key_from_x509(const uint8_t *cert, size_t cert_size, + void **rsa_context) +{ + LIBSPDM_ASSERT(false); + return false; +} +#endif /* (LIBSPDM_RSA_SSA_SUPPORT) || (LIBSPDM_RSA_PSS_SUPPORT) */ + +bool libspdm_ec_get_public_key_from_x509(const uint8_t *cert, size_t cert_size, + void **ec_context) +{ +#ifdef USE_LKCA + bool ret = false; + uint32_t key_size = 0; + struct key_preparsed_payload lkca_cert; + struct public_key *pub; + + lkca_cert.data = cert; + lkca_cert.datalen = cert_size; + + if (cert == NULL) { + return false; + } + + if(key_type_asymmetric.preparse(&lkca_cert)) { + return false; + } + + pub = lkca_cert.payload.data[asym_crypto]; + // -1 is since lkca prepends '4' to public keys... + key_size = pub->keylen - 1; + + if (key_size == (2 * 256 / 8)) { + *ec_context = libspdm_ec_new_by_nid(LIBSPDM_CRYPTO_NID_SECP256R1); + } else if (key_size == (2 * 384 / 8)) { + *ec_context = libspdm_ec_new_by_nid(LIBSPDM_CRYPTO_NID_SECP384R1); + } else { + goto err; + } + + if (*ec_context == NULL) { + goto err; + } + + // Again skip '4' in key to be in line with spdm protocol. We will add it + // back in ecda_verify + if (!lkca_ec_set_pub_key(*ec_context, (char *) pub->key + 1, key_size)) { + libspdm_ec_free(*ec_context); + goto err; + } + + ret = true; +err: + key_type_asymmetric.free_preparse(&lkca_cert); + return ret; +#else + return false; +#endif +} + +bool libspdm_ecd_get_public_key_from_x509(const uint8_t *cert, size_t cert_size, + void **ecd_context) +{ + LIBSPDM_ASSERT(false); + return false; +} + +bool libspdm_sm2_get_public_key_from_x509(const uint8_t *cert, size_t cert_size, + void **sm2_context) +{ + LIBSPDM_ASSERT(false); + return false; +} + +static int lkca_x509_verify_cert(const uint8_t *cert, size_t cert_size, + const uint8_t *ca_cert, size_t ca_cert_size) +{ +#ifdef USE_LKCA + int ret; + struct key_preparsed_payload lkca_cert; + struct key_preparsed_payload lkca_ca_cert; + + lkca_cert.data = cert; + lkca_cert.datalen = cert_size; + lkca_ca_cert.data = ca_cert; + lkca_ca_cert.datalen = ca_cert_size; + + ret = key_type_asymmetric.preparse(&lkca_cert); + if (ret) { + return ret; + } + + ret = key_type_asymmetric.preparse(&lkca_ca_cert); + if (ret) { + key_type_asymmetric.free_preparse(&lkca_cert); + return ret; + } + + ret = public_key_verify_signature(lkca_ca_cert.payload.data[asym_crypto], + lkca_cert.payload.data[asym_auth]); + + key_type_asymmetric.free_preparse(&lkca_cert); + key_type_asymmetric.free_preparse(&lkca_ca_cert); + + return ret; +#else + return false; +#endif +} + +bool libspdm_x509_verify_cert(const uint8_t *cert, size_t cert_size, + const uint8_t *ca_cert, size_t ca_cert_size) +{ + return lkca_x509_verify_cert(cert, cert_size, ca_cert, ca_cert_size) == 0; +} + +bool libspdm_x509_verify_cert_chain(const uint8_t *root_cert, size_t root_cert_length, + const uint8_t *cert_chain, size_t cert_chain_length) +{ + size_t preceding_cert_len; + const uint8_t *preceding_cert; + size_t current_cert_len; + const uint8_t *current_cert; + bool verify_flag; + int ret; + + verify_flag = false; + preceding_cert = root_cert; + preceding_cert_len = root_cert_length; + + current_cert = cert_chain; + + + /* Get Current certificate from certificates buffer and Verify with preceding cert*/ + do { + if (!lkca_asn1_get_tag( + current_cert, cert_chain + cert_chain_length, ¤t_cert_len, + LIBSPDM_CRYPTO_ASN1_CONSTRUCTED | LIBSPDM_CRYPTO_ASN1_SEQUENCE)) { + break; + } + + ret = lkca_x509_verify_cert(current_cert, current_cert_len, + preceding_cert, preceding_cert_len); + if (ret != 0) { + verify_flag = false; + break; + } else { + verify_flag = true; + } + + preceding_cert = current_cert; + preceding_cert_len = current_cert_len; + + current_cert = current_cert + current_cert_len; + } while (true); + + return verify_flag; +} + +bool libspdm_x509_get_cert_from_cert_chain(const uint8_t *cert_chain, + size_t cert_chain_length, + const int32_t cert_index, const uint8_t **cert, + size_t *cert_length) +{ + size_t asn1_len; + int32_t current_index; + size_t current_cert_len; + const uint8_t *current_cert; + + current_cert_len = 0; + + /* Check input parameters.*/ + if ((cert_chain == NULL) || (cert == NULL) || (cert_index < -1) || + (cert_length == NULL)) { + return false; + } + + current_cert = cert_chain; + current_index = -1; + + /* Traverse the certificate chain*/ + while (true) { + /* Get asn1 tag len*/ + if (!lkca_asn1_get_tag( + current_cert, cert_chain + cert_chain_length, &asn1_len, + LIBSPDM_CRYPTO_ASN1_CONSTRUCTED | LIBSPDM_CRYPTO_ASN1_SEQUENCE)) { + break; + } + + current_cert_len = asn1_len; + current_index++; + + if (current_index == cert_index) { + *cert = current_cert; + *cert_length = current_cert_len; + return true; + } + + current_cert = current_cert + current_cert_len; + } + + /* If cert_index is -1, Return the last certificate*/ + if (cert_index == -1 && current_index >= 0) { + *cert = current_cert - current_cert_len; + *cert_length = current_cert_len; + return true; + } + + return false; +} + +bool libspdm_x509_get_tbs_cert(const uint8_t *cert, size_t cert_size, + uint8_t **tbs_cert, size_t *tbs_cert_size) +{ + LIBSPDM_ASSERT(false); + return false; +} + +bool libspdm_x509_get_version(const uint8_t *cert, size_t cert_size, + size_t *version) +{ + LIBSPDM_ASSERT(false); + return false; +} + +bool libspdm_x509_get_serial_number(const uint8_t *cert, size_t cert_size, + uint8_t *serial_number, + size_t *serial_number_size) +{ + LIBSPDM_ASSERT(false); + return false; +} + +bool libspdm_x509_get_issuer_name(const uint8_t *cert, size_t cert_size, + uint8_t *cert_issuer, + size_t *issuer_size) +{ + LIBSPDM_ASSERT(false); + return false; +} + +bool +libspdm_x509_get_issuer_common_name(const uint8_t *cert, size_t cert_size, + char *common_name, + size_t *common_name_size) +{ + LIBSPDM_ASSERT(false); + return false; +} + +bool +libspdm_x509_get_issuer_orgnization_name(const uint8_t *cert, size_t cert_size, + char *name_buffer, + size_t *name_buffer_size) +{ + LIBSPDM_ASSERT(false); + return false; +} + +bool libspdm_x509_get_signature_algorithm(const uint8_t *cert, + size_t cert_size, uint8_t *oid, + size_t *oid_size) +{ + LIBSPDM_ASSERT(false); + return false; +} + +bool libspdm_x509_get_extension_data(const uint8_t *cert, size_t cert_size, + const uint8_t *oid, size_t oid_size, + uint8_t *extension_data, + size_t *extension_data_size) +{ + LIBSPDM_ASSERT(false); + return false; +} + +bool libspdm_x509_get_validity(const uint8_t *cert, size_t cert_size, + uint8_t *from, size_t *from_size, uint8_t *to, + size_t *to_size) +{ + LIBSPDM_ASSERT(false); + return false; +} + +bool libspdm_x509_get_key_usage(const uint8_t *cert, size_t cert_size, + size_t *usage) +{ + LIBSPDM_ASSERT(false); + return false; +} + +bool libspdm_x509_get_extended_key_usage(const uint8_t *cert, + size_t cert_size, uint8_t *usage, + size_t *usage_size) +{ + LIBSPDM_ASSERT(false); + return false; +} + +bool libspdm_x509_get_extended_basic_constraints(const uint8_t *cert, + size_t cert_size, + uint8_t *basic_constraints, + size_t *basic_constraints_size) +{ + LIBSPDM_ASSERT(false); + return false; +} + +bool libspdm_x509_set_date_time(char const *date_time_str, void *date_time, size_t *date_time_size) +{ + LIBSPDM_ASSERT(false); + return false; +} + +int32_t libspdm_x509_compare_date_time(const void *date_time1, const void *date_time2) +{ + LIBSPDM_ASSERT(false); + return -3; +} + +bool libspdm_gen_x509_csr(size_t hash_nid, size_t asym_nid, + uint8_t *requester_info, size_t requester_info_length, + void *context, char *subject_name, + size_t *csr_len, uint8_t **csr_pointer) +{ + LIBSPDM_ASSERT(false); + return false; +} diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/kernel-open/nvidia/linux_nvswitch.c nvidia-open-gpu-kernel-modules-535.161.08/kernel-open/nvidia/linux_nvswitch.c --- nvidia-open-gpu-kernel-modules-525.147.05/kernel-open/nvidia/linux_nvswitch.c 2023-10-25 20:33:25.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/kernel-open/nvidia/linux_nvswitch.c 2024-03-05 22:25:40.000000000 +0000 @@ -2509,26 +2509,22 @@ void nvswitch_os_assert_log ( - int cond, const char *fmt, ... ) { - if(cond == 0x0) + if (printk_ratelimit()) { - if (printk_ratelimit()) - { - va_list arglist; - char fmt_printk[NVSWITCH_LOG_BUFFER_SIZE]; + va_list arglist; + char fmt_printk[NVSWITCH_LOG_BUFFER_SIZE]; - va_start(arglist, fmt); - vsnprintf(fmt_printk, sizeof(fmt_printk), fmt, arglist); - va_end(arglist); - nvswitch_os_print(NVSWITCH_DBG_LEVEL_ERROR, fmt_printk); - WARN_ON(1); - } - dbg_breakpoint(); - } + va_start(arglist, fmt); + vsnprintf(fmt_printk, sizeof(fmt_printk), fmt, arglist); + va_end(arglist); + nvswitch_os_print(NVSWITCH_DBG_LEVEL_ERROR, fmt_printk); + WARN_ON(1); + } + dbg_breakpoint(); } /* @@ -2695,3 +2691,17 @@ *os_descriptor = NV_FALSE; return NVL_SUCCESS; } + +NvlStatus +nvswitch_os_get_pid +( + NvU32 *pPid +) +{ + if (pPid != NULL) + { + *pPid = task_pid_nr(current); + } + + return NVL_SUCCESS; +} diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/kernel-open/nvidia/linux_nvswitch.h nvidia-open-gpu-kernel-modules-535.161.08/kernel-open/nvidia/linux_nvswitch.h --- nvidia-open-gpu-kernel-modules-525.147.05/kernel-open/nvidia/linux_nvswitch.h 2023-10-25 20:33:25.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/kernel-open/nvidia/linux_nvswitch.h 2024-03-05 22:25:40.000000000 +0000 @@ -37,8 +37,12 @@ #define NVSWITCH_IRQ_PIN 3 #define NVSWITCH_OS_ASSERT(_cond) \ - nvswitch_os_assert_log((_cond), "NVSwitch: Assertion failed in %s() at %s:%d\n", \ - __FUNCTION__ , __FILE__, __LINE__) + do { \ + if (!(_cond)) { \ + nvswitch_os_assert_log("NVSwitch: Assertion failed in %s() at %s:%d\n", \ + __FUNCTION__ , __FILE__, __LINE__); \ + } \ + } while(0) #define NVSWITCH_KMALLOC_LIMIT (128 * 1024) diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/kernel-open/nvidia/nv-acpi.c nvidia-open-gpu-kernel-modules-535.161.08/kernel-open/nvidia/nv-acpi.c --- nvidia-open-gpu-kernel-modules-525.147.05/kernel-open/nvidia/nv-acpi.c 2023-10-25 20:33:19.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/kernel-open/nvidia/nv-acpi.c 2024-03-05 22:25:31.000000000 +0000 @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 1999-2021 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 1999-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -36,6 +36,7 @@ static NV_STATUS nv_acpi_extract_object (const union acpi_object *, void *, NvU32, NvU32 *); static void nv_acpi_powersource_hotplug_event(acpi_handle, u32, void *); +static void nv_acpi_nvpcf_event (acpi_handle, u32, void *); static acpi_status nv_acpi_find_methods (acpi_handle, u32, void *, void **); static NV_STATUS nv_acpi_nvif_method (NvU32, NvU32, void *, NvU16, NvU32 *, void *, NvU16 *); @@ -65,6 +66,13 @@ #define ACPI_VIDEO_CLASS "video" #endif +// Used for NVPCF event handling +static acpi_handle nvpcf_handle = NULL; +static acpi_handle nvpcf_device_handle = NULL; +static nv_acpi_t *nvpcf_nv_acpi_object = NULL; + +#define ACPI_NVPCF_EVENT_CHANGE 0xC0 + static int nv_acpi_get_device_handle(nv_state_t *nv, acpi_handle *dev_handle) { nv_linux_state_t *nvl = NV_GET_NVL_FROM_NV_STATE(nv); @@ -80,51 +88,39 @@ #endif } -static int nv_acpi_notify(struct notifier_block *nb, - unsigned long val, void *data) +/* + * This callback will be invoked by the acpi_notifier_call_chain() + */ +static int nv_acpi_notifier_call_chain_handler( + struct notifier_block *nb, + unsigned long val, + void *data +) { struct acpi_bus_event *info = data; - nv_stack_t *sp = NULL; - nv_linux_state_t *nvl = container_of(nb, nv_linux_state_t, acpi_nb); - nv_state_t *nv = NV_STATE_PTR(nvl); - - if (!strcmp(info->device_class, ACPI_VIDEO_CLASS)) { - if (nv_kmem_cache_alloc_stack(&sp) == 0) { - /* - * Function to handle device specific ACPI events - * such as display hotplug and D-notifier events. - */ - rm_acpi_notify(sp, nv, info->type); - nv_kmem_cache_free_stack(sp); - } - else - nv_printf(NV_DBG_ERRORS, - "NVRM: nv_acpi_notify: failed to allocate stack\n"); + /* + * The ACPI_VIDEO_NOTIFY_PROBE will be sent for display hot-plug/unplug. + * This event will be received first by the acpi-video driver + * and then it will be notified through acpi_notifier_call_chain(). + */ + if (!strcmp(info->device_class, ACPI_VIDEO_CLASS) && + (info->type == ACPI_VIDEO_NOTIFY_PROBE)) + { /* - * Special case for ACPI_VIDEO_NOTIFY_PROBE event: intentionally return - * NOTIFY_BAD to inform acpi-video to stop generating keypresses for - * this event. + * Intentionally return NOTIFY_BAD to inform acpi-video to stop + * generating keypresses for this event. The default behavior in the + * acpi-video driver for an ACPI_VIDEO_NOTIFY_PROBE, is to send a + * KEY_SWITCHVIDEOMODE evdev event, which causes the desktop settings + * daemons like gnome-setting-daemon to switch mode and this impacts + * the notebooks having external HDMI connected. */ - if (info->type == ACPI_VIDEO_NOTIFY_PROBE) { - return NOTIFY_BAD; - } + return NOTIFY_BAD; } return NOTIFY_DONE; } -void nv_acpi_register_notifier(nv_linux_state_t *nvl) -{ - nvl->acpi_nb.notifier_call = nv_acpi_notify; - register_acpi_notifier(&nvl->acpi_nb); -} - -void nv_acpi_unregister_notifier(nv_linux_state_t *nvl) -{ - unregister_acpi_notifier(&nvl->acpi_nb); -} - NV_STATUS NV_API_CALL nv_acpi_get_powersource(NvU32 *ac_plugged) { unsigned long long val; @@ -167,12 +163,31 @@ rm_power_source_change_event(pNvAcpiObject->sp, !ac_plugged); } } + +static void nv_acpi_nvpcf_event(acpi_handle handle, u32 event_type, void *data) +{ + nv_acpi_t *pNvAcpiObject = data; + + if (event_type == ACPI_NVPCF_EVENT_CHANGE) + { + rm_acpi_nvpcf_notify(pNvAcpiObject->sp); + } + else + { + nv_printf(NV_DBG_INFO,"NVRM: %s: NVPCF event 0x%x is not supported\n", event_type, __FUNCTION__); + } +} + /* * End of ACPI event handler functions */ /* Do the necessary allocations and install notifier "handler" on the device-node "device" */ -static nv_acpi_t* nv_install_notifier(struct acpi_handle *handle, acpi_notify_handler handler) +static nv_acpi_t* nv_install_notifier( + struct acpi_handle *handle, + acpi_notify_handler handler, + void *notifier_data +) { nvidia_stack_t *sp = NULL; nv_acpi_t *pNvAcpiObject = NULL; @@ -196,6 +211,7 @@ // store a handle reference in our object pNvAcpiObject->handle = handle; pNvAcpiObject->sp = sp; + pNvAcpiObject->notifier_data = notifier_data; status = acpi_install_notify_handler(handle, ACPI_DEVICE_NOTIFY, handler, pNvAcpiObject); @@ -237,6 +253,49 @@ return; } +static void nv_acpi_notify_event(acpi_handle handle, u32 event_type, void *data) +{ + nv_acpi_t *pNvAcpiObject = data; + nv_state_t *nvl = pNvAcpiObject->notifier_data; + + /* + * Function to handle device specific ACPI events such as display hotplug, + * GPS and D-notifier events. + */ + rm_acpi_notify(pNvAcpiObject->sp, NV_STATE_PTR(nvl), event_type); +} + +void nv_acpi_register_notifier(nv_linux_state_t *nvl) +{ + acpi_handle dev_handle = NULL; + + /* Install the ACPI notifier corresponding to dGPU ACPI device. */ + if ((nvl->nv_acpi_object == NULL) && + nv_acpi_get_device_handle(NV_STATE_PTR(nvl), &dev_handle) && + (dev_handle != NULL)) + { + nvl->nv_acpi_object = nv_install_notifier(dev_handle, nv_acpi_notify_event, nvl); + if (nvl->nv_acpi_object == NULL) + { + nv_printf(NV_DBG_ERRORS, + "NVRM: nv_acpi_register_notifier: failed to install notifier\n"); + } + } + + nvl->acpi_nb.notifier_call = nv_acpi_notifier_call_chain_handler; + register_acpi_notifier(&nvl->acpi_nb); +} + +void nv_acpi_unregister_notifier(nv_linux_state_t *nvl) +{ + unregister_acpi_notifier(&nvl->acpi_nb); + if (nvl->nv_acpi_object != NULL) + { + nv_uninstall_notifier(nvl->nv_acpi_object, nv_acpi_notify_event); + nvl->nv_acpi_object = NULL; + } +} + /* * acpi methods init function. * check if the NVIF, _DSM and WMMX methods are present in the acpi namespace. @@ -268,10 +327,15 @@ // devices if (psr_nv_acpi_object == NULL) { - psr_nv_acpi_object = nv_install_notifier(psr_device_handle, nv_acpi_powersource_hotplug_event); + psr_nv_acpi_object = nv_install_notifier(psr_device_handle, nv_acpi_powersource_hotplug_event, NULL); } } + if (nvpcf_handle && (nvpcf_nv_acpi_object == NULL)) + { + nvpcf_nv_acpi_object = nv_install_notifier(nvpcf_device_handle, nv_acpi_nvpcf_event, NULL); + } + return; } @@ -300,6 +364,12 @@ psr_device_handle = handle; } + if (!acpi_get_handle(handle, "NPCF", &method_handle)) + { + nvpcf_handle = method_handle; + nvpcf_device_handle = handle; + } + return 0; } @@ -316,6 +386,15 @@ psr_device_handle = NULL; psr_nv_acpi_object = NULL; } + + if (nvpcf_nv_acpi_object != NULL) + { + nv_uninstall_notifier(nvpcf_nv_acpi_object, nv_acpi_nvpcf_event); + + nvpcf_handle = NULL; + nvpcf_device_handle = NULL; + nvpcf_nv_acpi_object = NULL; + } } static NV_STATUS nv_acpi_extract_integer( @@ -980,7 +1059,10 @@ union acpi_object mmx_params[3]; if (!wmmx_handle) + { + *outDataSize = 0; return NV_ERR_NOT_SUPPORTED; + } if (!NV_MAY_SLEEP()) { diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/kernel-open/nvidia/nv-dmabuf.c nvidia-open-gpu-kernel-modules-535.161.08/kernel-open/nvidia/nv-dmabuf.c --- nvidia-open-gpu-kernel-modules-525.147.05/kernel-open/nvidia/nv-dmabuf.c 2023-10-25 20:33:19.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/kernel-open/nvidia/nv-dmabuf.c 2024-03-05 22:25:31.000000000 +0000 @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2022-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -25,37 +25,74 @@ #if defined(CONFIG_DMA_SHARED_BUFFER) -// -// The Linux kernel's dma_length in struct scatterlist is unsigned int -// which limits the maximum sg length to 4GB - 1. -// To get around this limitation, the BAR1 scatterlist returned by RM -// is split into (4GB - PAGE_SIZE) sized chunks to build the sg_table. -// -#define NV_DMA_BUF_SG_MAX_LEN ((NvU32)(NVBIT64(32) - PAGE_SIZE)) - typedef struct nv_dma_buf_mem_handle { - NvHandle h_memory; - NvU64 offset; - NvU64 size; - NvU64 bar1_va; + // Memory handle, offset and size + NvHandle h_memory; + NvU64 offset; + NvU64 size; + + // RM memdesc specific data + void *static_mem_info; + + // + // Refcount for phys addresses + // If refcount > 0, phys address ranges in phys_range are reused. + // + NvU64 phys_refcount; + + // Number of scatterlist entries in phys_range[] array + NvU32 phys_range_count; + + // List of phys address ranges to be used to dma map + nv_phys_addr_range_t *phys_range; } nv_dma_buf_mem_handle_t; typedef struct nv_dma_buf_file_private { + // GPU device state nv_state_t *nv; + + // Client, device, subdevice handles NvHandle h_client; NvHandle h_device; NvHandle h_subdevice; + + // Total number of handles supposed to be attached to this dma-buf NvU32 total_objects; + + // + // Number of handles actually attached to this dma-buf. + // This should equal total_objects, or map fails. + // NvU32 num_objects; + + // Total size of all handles supposed to be attached to this dma-buf NvU64 total_size; + + // + // Size of all handles actually attached to the dma-buf + // If all handles are attached, total_size and attached_size must match. + // NvU64 attached_size; + + // Mutex to lock priv state during dma-buf callbacks struct mutex lock; + + // Handle info: see nv_dma_buf_mem_handle_t nv_dma_buf_mem_handle_t *handles; - NvU64 bar1_va_ref_count; + + // RM-private info for MIG configs void *mig_info; + + // Flag to indicate if dma-buf mmap is allowed NvBool can_mmap; + + // + // Flag to indicate if phys addresses are static and can be + // fetched during dma-buf create/reuse instead of in map. + // + NvBool static_phys_addrs; } nv_dma_buf_file_private_t; static void @@ -108,31 +145,94 @@ return NULL; } +static void +nv_reset_phys_refcount( + nv_dma_buf_file_private_t *priv, + NvU32 start_index, + NvU32 handle_count +) +{ + NvU32 i; + for (i = 0; i < handle_count; i++) + { + NvU32 index = start_index + i; + priv->handles[index].phys_refcount = 0; + } +} + +static NvBool +nv_dec_and_check_zero_phys_refcount( + nv_dma_buf_file_private_t *priv, + NvU32 start_index, + NvU32 handle_count +) +{ + NvU32 i; + NvBool is_zero = NV_FALSE; + + for (i = 0; i < handle_count; i++) + { + NvU32 index = start_index + i; + priv->handles[index].phys_refcount--; + if (priv->handles[index].phys_refcount == 0) + { + is_zero = NV_TRUE; + } + } + + return is_zero; +} + +static NvBool +nv_inc_and_check_one_phys_refcount( + nv_dma_buf_file_private_t *priv, + NvU32 start_index, + NvU32 handle_count +) +{ + NvU32 i; + NvBool is_one = NV_FALSE; + + for (i = 0; i < handle_count; i++) + { + NvU32 index = start_index + i; + priv->handles[index].phys_refcount++; + if (priv->handles[index].phys_refcount == 1) + { + is_one = NV_TRUE; + } + } + + return is_one; +} + // Must be called with RMAPI lock and GPU lock taken static void nv_dma_buf_undup_mem_handles_unlocked( nvidia_stack_t *sp, - NvU32 index, + NvU32 start_index, NvU32 num_objects, nv_dma_buf_file_private_t *priv ) { - NvU32 i = 0; + NvU32 index, i; - for (i = index; i < num_objects; i++) + for (i = 0; i < num_objects; i++) { - if (priv->handles[i].h_memory == 0) + index = start_index + i; + + if (priv->handles[index].h_memory == 0) { continue; } rm_dma_buf_undup_mem_handle(sp, priv->nv, priv->h_client, - priv->handles[i].h_memory); + priv->handles[index].h_memory); - priv->attached_size -= priv->handles[i].size; - priv->handles[i].h_memory = 0; - priv->handles[i].offset = 0; - priv->handles[i].size = 0; + priv->attached_size -= priv->handles[index].size; + priv->handles[index].h_memory = 0; + priv->handles[index].offset = 0; + priv->handles[index].size = 0; priv->num_objects--; } } @@ -194,6 +294,7 @@ for (i = 0; i < params->numObjects; i++) { NvHandle h_memory_duped = 0; + void *mem_info = NULL; if (priv->handles[index].h_memory != 0) { @@ -216,7 +317,8 @@ params->handles[i], params->offsets[i], params->sizes[i], - &h_memory_duped); + &h_memory_duped, + &mem_info); if (status != NV_OK) { goto failed; @@ -226,6 +328,7 @@ priv->handles[index].h_memory = h_memory_duped; priv->handles[index].offset = params->offsets[i]; priv->handles[index].size = params->sizes[i]; + priv->handles[index].static_mem_info = mem_info; priv->num_objects++; index++; count++; @@ -255,260 +358,439 @@ return status; } -// Must be called with RMAPI lock and GPU lock taken static void -nv_dma_buf_unmap_unlocked( +nv_put_phys_addresses( nvidia_stack_t *sp, - nv_dma_device_t *peer_dma_dev, nv_dma_buf_file_private_t *priv, - struct sg_table *sgt, + NvU32 start_index, NvU32 mapped_handle_count ) { - NV_STATUS status; NvU32 i; - NvU64 dma_len; - NvU64 dma_addr; - NvBool bar1_unmap_needed; - struct scatterlist *sg = NULL; - - bar1_unmap_needed = (priv->bar1_va_ref_count == 0); - sg = sgt->sgl; for (i = 0; i < mapped_handle_count; i++) { - NvU64 handle_size = priv->handles[i].size; - - dma_addr = sg_dma_address(sg); - dma_len = 0; + NvU32 index = start_index + i; - // - // Seek ahead in the scatterlist until the handle size is covered. - // IOVA unmap can then be done all at once instead of doing it - // one sg at a time. - // - while(handle_size != dma_len) + if (priv->handles[index].phys_refcount > 0) { - dma_len += sg_dma_len(sg); - sg = sg_next(sg); + continue; } - nv_dma_unmap_peer(peer_dma_dev, (dma_len / os_page_size), dma_addr); + // Per-handle phys_range is freed by RM + rm_dma_buf_unmap_mem_handle(sp, priv->nv, priv->h_client, + priv->handles[index].h_memory, + priv->handles[index].size, + &priv->handles[index].phys_range, + priv->handles[index].phys_range_count); - if (bar1_unmap_needed) + priv->handles[index].phys_range_count = 0; + } +} + +static void +nv_dma_buf_put_phys_addresses ( + nv_dma_buf_file_private_t *priv, + NvU32 start_index, + NvU32 handle_count +) +{ + NV_STATUS status; + nvidia_stack_t *sp = NULL; + NvBool api_lock_taken = NV_FALSE; + NvBool gpu_lock_taken = NV_FALSE; + int rc = 0; + + if (!nv_dec_and_check_zero_phys_refcount(priv, start_index, handle_count)) + { + return; + } + + rc = nv_kmem_cache_alloc_stack(&sp); + if (WARN_ON(rc != 0)) + { + return; + } + + if (!priv->static_phys_addrs) + { + status = rm_acquire_api_lock(sp); + if (WARN_ON(status != NV_OK)) + { + goto free_sp; + } + api_lock_taken = NV_TRUE; + + status = rm_acquire_gpu_lock(sp, priv->nv); + if (WARN_ON(status != NV_OK)) { - status = rm_dma_buf_unmap_mem_handle(sp, priv->nv, priv->h_client, - priv->handles[i].h_memory, - priv->handles[i].size, - priv->handles[i].bar1_va); - WARN_ON(status != NV_OK); + goto unlock_api_lock; } + gpu_lock_taken = NV_TRUE; + } + + nv_put_phys_addresses(sp, priv, start_index, handle_count); + + if (gpu_lock_taken) + { + rm_release_gpu_lock(sp, priv->nv); } + +unlock_api_lock: + if (api_lock_taken) + { + rm_release_api_lock(sp); + } + +free_sp: + nv_kmem_cache_free_stack(sp); } -static struct sg_table* -nv_dma_buf_map( - struct dma_buf_attachment *attachment, - enum dma_data_direction direction +static NV_STATUS +nv_dma_buf_get_phys_addresses ( + nv_dma_buf_file_private_t *priv, + NvU32 start_index, + NvU32 handle_count ) { - NV_STATUS status; + NV_STATUS status = NV_OK; nvidia_stack_t *sp = NULL; - struct scatterlist *sg = NULL; - struct sg_table *sgt = NULL; - struct dma_buf *buf = attachment->dmabuf; - struct device *dev = attachment->dev; - nv_dma_buf_file_private_t *priv = buf->priv; - nv_dma_device_t peer_dma_dev = {{ 0 }}; - NvBool bar1_map_needed; - NvBool bar1_unmap_needed; - NvU32 mapped_handle_count = 0; - NvU32 num_sg_entries = 0; - NvU32 i = 0; + NvBool api_lock_taken = NV_FALSE; + NvBool gpu_lock_taken = NV_FALSE; + NvU32 i; int rc = 0; + if (!nv_inc_and_check_one_phys_refcount(priv, start_index, handle_count)) + { + return NV_OK; + } + + rc = nv_kmem_cache_alloc_stack(&sp); + if (rc != 0) + { + status = NV_ERR_NO_MEMORY; + goto failed; + } + // - // We support importers that are able to handle MMIO resources - // not backed by struct page. This will need to be revisited - // when dma-buf support for P9 will be added. + // Locking is not needed for static phys address configs because the memdesc + // is not expected to change in this case and we hold the refcount on the + // owner GPU and memory before referencing it. // -#if defined(NV_DMA_BUF_HAS_DYNAMIC_ATTACHMENT) && \ - defined(NV_DMA_BUF_ATTACHMENT_HAS_PEER2PEER) - if (dma_buf_attachment_is_dynamic(attachment) && - !attachment->peer2peer) + if (!priv->static_phys_addrs) { - nv_printf(NV_DBG_ERRORS, - "NVRM: failed to map dynamic attachment with no P2P support\n"); - return NULL; + status = rm_acquire_api_lock(sp); + if (status != NV_OK) + { + goto free_sp; + } + api_lock_taken = NV_TRUE; + + status = rm_acquire_gpu_lock(sp, priv->nv); + if (status != NV_OK) + { + goto unlock_api_lock; + } + gpu_lock_taken = NV_TRUE; } -#endif - mutex_lock(&priv->lock); + for (i = 0; i < handle_count; i++) + { + NvU32 index = start_index + i; - if (priv->num_objects != priv->total_objects) + if (priv->handles[index].phys_refcount > 1) + { + continue; + } + + // Per-handle phys_range is allocated by RM + status = rm_dma_buf_map_mem_handle(sp, priv->nv, priv->h_client, + priv->handles[index].h_memory, + priv->handles[index].offset, + priv->handles[index].size, + priv->handles[index].static_mem_info, + &priv->handles[index].phys_range, + &priv->handles[index].phys_range_count); + if (status != NV_OK) + { + goto unmap_handles; + } + } + + if (gpu_lock_taken) { - goto unlock_priv; + rm_release_gpu_lock(sp, priv->nv); } - rc = nv_kmem_cache_alloc_stack(&sp); - if (rc != 0) + if (api_lock_taken) { - goto unlock_priv; + rm_release_api_lock(sp); } - status = rm_acquire_api_lock(sp); - if (status != NV_OK) + nv_kmem_cache_free_stack(sp); + + return NV_OK; + +unmap_handles: + nv_put_phys_addresses(sp, priv, start_index, i); + + if (gpu_lock_taken) { - goto free_sp; + rm_release_gpu_lock(sp, priv->nv); } - status = rm_acquire_gpu_lock(sp, priv->nv); - if (status != NV_OK) +unlock_api_lock: + if (api_lock_taken) { - goto unlock_api_lock; + rm_release_api_lock(sp); } - NV_KZALLOC(sgt, sizeof(struct sg_table)); - if (sgt == NULL) +free_sp: + nv_kmem_cache_free_stack(sp); + +failed: + nv_reset_phys_refcount(priv, start_index, handle_count); + + return status; +} + +static void +nv_dma_buf_unmap_pages( + struct device *dev, + struct sg_table *sgt +) +{ + dma_unmap_sg(dev, sgt->sgl, sgt->nents, DMA_BIDIRECTIONAL); +} + +static void +nv_dma_buf_unmap_pfns( + struct device *dev, + struct sg_table *sgt +) +{ + nv_dma_device_t peer_dma_dev = {{ 0 }}; + struct scatterlist *sg = sgt->sgl; + NvU32 i; + + peer_dma_dev.dev = dev; + peer_dma_dev.addressable_range.limit = (NvU64)dev->dma_mask; + + for_each_sg(sgt->sgl, sg, sgt->nents, i) { - goto unlock_gpu_lock; + nv_dma_unmap_peer(&peer_dma_dev, + (sg_dma_len(sg) >> PAGE_SHIFT), + sg_dma_address(sg)); } +} - // - // Pre-calculate number of sg entries we need based on handle size. - // This is needed to allocate sg_table. - // +static struct sg_table* +nv_dma_buf_map_pages ( + struct device *dev, + nv_dma_buf_file_private_t *priv +) +{ + struct sg_table *sgt = NULL; + struct scatterlist *sg; + NvU32 nents = 0; + NvU32 i; + int rc; + + // Calculate nents needed to allocate sg_table for (i = 0; i < priv->num_objects; i++) { - NvU64 count = priv->handles[i].size + NV_DMA_BUF_SG_MAX_LEN - 1; - do_div(count, NV_DMA_BUF_SG_MAX_LEN); - num_sg_entries += count; + nents += priv->handles[i].phys_range_count; } - // - // RM currently returns contiguous BAR1, so we create as many - // sg entries as num_sg_entries calculated above. - // When RM can alloc discontiguous BAR1, this code will need to be revisited. - // - rc = sg_alloc_table(sgt, num_sg_entries, GFP_KERNEL); + NV_KZALLOC(sgt, sizeof(struct sg_table)); + if (sgt == NULL) + { + return NULL; + } + + rc = sg_alloc_table(sgt, nents, GFP_KERNEL); if (rc != 0) { goto free_sgt; } - peer_dma_dev.dev = dev; - peer_dma_dev.addressable_range.limit = (NvU64)dev->dma_mask; - bar1_map_needed = bar1_unmap_needed = (priv->bar1_va_ref_count == 0); - sg = sgt->sgl; + for (i = 0; i < priv->num_objects; i++) { - NvU64 dma_addr; - NvU64 dma_len; - - if (bar1_map_needed) + NvU32 range_count = priv->handles[i].phys_range_count; + NvU32 index = 0; + for (index = 0; index < range_count; index++) { - status = rm_dma_buf_map_mem_handle(sp, priv->nv, priv->h_client, - priv->handles[i].h_memory, - priv->handles[i].offset, - priv->handles[i].size, - &priv->handles[i].bar1_va); - if (status != NV_OK) + NvU64 addr = priv->handles[i].phys_range[index].addr; + NvU64 len = priv->handles[i].phys_range[index].len; + struct page *page = NV_GET_PAGE_STRUCT(addr); + + if ((page == NULL) || (sg == NULL)) { - goto unmap_handles; + goto free_table; } + + sg_set_page(sg, page, len, 0); + sg = sg_next(sg); } + } - mapped_handle_count++; + // DMA map the sg_table + rc = dma_map_sg(dev, sgt->sgl, sgt->orig_nents, DMA_BIDIRECTIONAL); + if (rc <= 0) + { + goto free_table; + } + sgt->nents = rc; - dma_addr = priv->handles[i].bar1_va; - dma_len = priv->handles[i].size; + return sgt; - // - // IOVA map the full handle at once and then breakdown the range - // (dma_addr, dma_addr + dma_len) into smaller sg entries. - // - status = nv_dma_map_peer(&peer_dma_dev, priv->nv->dma_dev, - 0x1, (dma_len / os_page_size), &dma_addr); - if (status != NV_OK) - { - if (bar1_unmap_needed) - { - // Unmap the recently mapped memory handle - (void) rm_dma_buf_unmap_mem_handle(sp, priv->nv, priv->h_client, - priv->handles[i].h_memory, - priv->handles[i].size, - priv->handles[i].bar1_va); - } +free_table: + sg_free_table(sgt); - mapped_handle_count--; +free_sgt: + NV_KFREE(sgt, sizeof(struct sg_table)); - // Unmap remaining memory handles - goto unmap_handles; - } + return NULL; +} - while(dma_len != 0) - { - NvU32 sg_len = NV_MIN(dma_len, NV_DMA_BUF_SG_MAX_LEN); +static struct sg_table* +nv_dma_buf_map_pfns ( + struct device *dev, + nv_dma_buf_file_private_t *priv +) +{ + NV_STATUS status; + struct sg_table *sgt = NULL; + struct scatterlist *sg; + nv_dma_device_t peer_dma_dev = {{ 0 }}; + NvU32 dma_max_seg_size; + NvU32 nents = 0; + NvU32 mapped_nents = 0; + NvU32 i = 0; + int rc = 0; - sg_set_page(sg, NULL, sg_len, 0); - sg_dma_address(sg) = (dma_addr_t)dma_addr; - sg_dma_len(sg) = sg_len; - dma_addr += sg_len; - dma_len -= sg_len; - sg = sg_next(sg); + peer_dma_dev.dev = dev; + peer_dma_dev.addressable_range.limit = (NvU64)dev->dma_mask; + + dma_max_seg_size = NV_ALIGN_DOWN(dma_get_max_seg_size(dev), PAGE_SIZE); + + if (dma_max_seg_size < PAGE_SIZE) + { + return NULL; + } + + // Calculate nents needed to allocate sg_table + for (i = 0; i < priv->num_objects; i++) + { + NvU32 range_count = priv->handles[i].phys_range_count; + NvU32 index; + + for (index = 0; index < range_count; index++) + { + NvU64 length = priv->handles[i].phys_range[index].len; + NvU64 count = length + dma_max_seg_size - 1; + do_div(count, dma_max_seg_size); + nents += count; } } - priv->bar1_va_ref_count++; + NV_KZALLOC(sgt, sizeof(struct sg_table)); + if (sgt == NULL) + { + return NULL; + } - rm_release_gpu_lock(sp, priv->nv); + rc = sg_alloc_table(sgt, nents, GFP_KERNEL); + if (rc != 0) + { + goto free_sgt; + } - rm_release_api_lock(sp); + sg = sgt->sgl; + for (i = 0; i < priv->num_objects; i++) + { + NvU32 range_count = priv->handles[i].phys_range_count; + NvU32 index = 0; - nv_kmem_cache_free_stack(sp); + for (index = 0; index < range_count; index++) + { + NvU64 dma_addr = priv->handles[i].phys_range[index].addr; + NvU64 dma_len = priv->handles[i].phys_range[index].len; - mutex_unlock(&priv->lock); + // Break the scatterlist into dma_max_seg_size chunks + while(dma_len != 0) + { + NvU32 sg_len = NV_MIN(dma_len, dma_max_seg_size); + + if (sg == NULL) + { + goto unmap_pfns; + } + + status = nv_dma_map_peer(&peer_dma_dev, priv->nv->dma_dev, 0x1, + (sg_len >> PAGE_SHIFT), &dma_addr); + if (status != NV_OK) + { + goto unmap_pfns; + } + + sg_set_page(sg, NULL, sg_len, 0); + sg_dma_address(sg) = (dma_addr_t) dma_addr; + sg_dma_len(sg) = sg_len; + dma_addr += sg_len; + dma_len -= sg_len; + mapped_nents++; + sg = sg_next(sg); + } + } + } + sgt->nents = mapped_nents; + + WARN_ON(sgt->nents != sgt->orig_nents); return sgt; -unmap_handles: - nv_dma_buf_unmap_unlocked(sp, &peer_dma_dev, priv, sgt, mapped_handle_count); +unmap_pfns: + sgt->nents = mapped_nents; + + nv_dma_buf_unmap_pfns(dev, sgt); sg_free_table(sgt); free_sgt: NV_KFREE(sgt, sizeof(struct sg_table)); -unlock_gpu_lock: - rm_release_gpu_lock(sp, priv->nv); - -unlock_api_lock: - rm_release_api_lock(sp); - -free_sp: - nv_kmem_cache_free_stack(sp); - -unlock_priv: - mutex_unlock(&priv->lock); - return NULL; } -static void -nv_dma_buf_unmap( +static struct sg_table* +nv_dma_buf_map( struct dma_buf_attachment *attachment, - struct sg_table *sgt, enum dma_data_direction direction ) { NV_STATUS status; + struct sg_table *sgt = NULL; struct dma_buf *buf = attachment->dmabuf; - struct device *dev = attachment->dev; - nvidia_stack_t *sp = NULL; nv_dma_buf_file_private_t *priv = buf->priv; - nv_dma_device_t peer_dma_dev = {{ 0 }}; - int rc = 0; + + // + // On non-coherent platforms, importers must be able to handle peer + // MMIO resources not backed by struct page. + // +#if defined(NV_DMA_BUF_HAS_DYNAMIC_ATTACHMENT) && \ + defined(NV_DMA_BUF_ATTACHMENT_HAS_PEER2PEER) + if (!priv->nv->coherent && + dma_buf_attachment_is_dynamic(attachment) && + !attachment->peer2peer) + { + nv_printf(NV_DBG_ERRORS, + "NVRM: failed to map dynamic attachment with no P2P support\n"); + return NULL; + } +#endif mutex_lock(&priv->lock); @@ -517,44 +799,78 @@ goto unlock_priv; } - rc = nv_kmem_cache_alloc_stack(&sp); - if (WARN_ON(rc != 0)) + if (!priv->static_phys_addrs) { - goto unlock_priv; + status = nv_dma_buf_get_phys_addresses(priv, 0, priv->num_objects); + if (status != NV_OK) + { + goto unlock_priv; + } } - status = rm_acquire_api_lock(sp); - if (WARN_ON(status != NV_OK)) + if (priv->nv->coherent) + { + sgt = nv_dma_buf_map_pages(attachment->dev, priv); + } + else + { + sgt = nv_dma_buf_map_pfns(attachment->dev, priv); + } + if (sgt == NULL) { - goto free_sp; + goto unmap_handles; } - status = rm_acquire_gpu_lock(sp, priv->nv); - if (WARN_ON(status != NV_OK)) + mutex_unlock(&priv->lock); + + return sgt; + +unmap_handles: + if (!priv->static_phys_addrs) { - goto unlock_api_lock; + nv_dma_buf_put_phys_addresses(priv, 0, priv->num_objects); } - peer_dma_dev.dev = dev; - peer_dma_dev.addressable_range.limit = (NvU64)dev->dma_mask; +unlock_priv: + mutex_unlock(&priv->lock); - priv->bar1_va_ref_count--; + return NULL; +} - nv_dma_buf_unmap_unlocked(sp, &peer_dma_dev, priv, sgt, priv->num_objects); +static void +nv_dma_buf_unmap( + struct dma_buf_attachment *attachment, + struct sg_table *sgt, + enum dma_data_direction direction +) +{ + struct dma_buf *buf = attachment->dmabuf; + nv_dma_buf_file_private_t *priv = buf->priv; - sg_free_table(sgt); + mutex_lock(&priv->lock); - NV_KFREE(sgt, sizeof(struct sg_table)); + if (priv->nv->coherent) + { + nv_dma_buf_unmap_pages(attachment->dev, sgt); + } + else + { + nv_dma_buf_unmap_pfns(attachment->dev, sgt); + } - rm_release_gpu_lock(sp, priv->nv); + // + // For static_phys_addrs platforms, this operation is done in release + // since getting the phys_addrs was done in create/reuse. + // + if (!priv->static_phys_addrs) + { + nv_dma_buf_put_phys_addresses(priv, 0, priv->num_objects); + } -unlock_api_lock: - rm_release_api_lock(sp); + sg_free_table(sgt); -free_sp: - nv_kmem_cache_free_stack(sp); + NV_KFREE(sgt, sizeof(struct sg_table)); -unlock_priv: mutex_unlock(&priv->lock); } @@ -564,6 +880,7 @@ ) { int rc = 0; + NvU32 i; nvidia_stack_t *sp = NULL; nv_dma_buf_file_private_t *priv = buf->priv; nv_state_t *nv; @@ -575,17 +892,31 @@ nv = priv->nv; + if (priv->static_phys_addrs) + { + nv_dma_buf_put_phys_addresses(priv, 0, priv->num_objects); + } + rc = nv_kmem_cache_alloc_stack(&sp); if (WARN_ON(rc != 0)) { return; } + // phys_addr refcounts must be zero at this point + for (i = 0; i < priv->num_objects; i++) + { + WARN_ON(priv->handles[i].phys_refcount > 0); + } + nv_dma_buf_undup_mem_handles(sp, 0, priv->num_objects, priv); rm_dma_buf_put_client_and_device(sp, priv->nv, priv->h_client, priv->h_device, priv->h_subdevice, priv->mig_info); + WARN_ON(priv->attached_size > 0); + WARN_ON(priv->num_objects > 0); + nv_dma_buf_free_file_private(priv); buf->priv = NULL; @@ -737,7 +1068,8 @@ &priv->h_client, &priv->h_device, &priv->h_subdevice, - &priv->mig_info); + &priv->mig_info, + &priv->static_phys_addrs); if (status != NV_OK) { goto cleanup_device; @@ -749,6 +1081,17 @@ goto cleanup_client_and_device; } + // Get CPU static phys addresses if possible to do so at this time. + if (priv->static_phys_addrs) + { + status = nv_dma_buf_get_phys_addresses(priv, params->index, + params->numObjects); + if (status != NV_OK) + { + goto cleanup_handles; + } + } + #if (NV_DMA_BUF_EXPORT_ARGUMENT_COUNT == 1) { DEFINE_DMA_BUF_EXPORT_INFO(exp_info); @@ -774,7 +1117,7 @@ status = NV_ERR_OPERATING_SYSTEM; - goto cleanup_handles; + goto put_phys_addrs; } nv_kmem_cache_free_stack(sp); @@ -797,8 +1140,14 @@ return NV_OK; +put_phys_addrs: + if (priv->static_phys_addrs) + { + nv_dma_buf_put_phys_addresses(priv, params->index, params->numObjects); + } + cleanup_handles: - nv_dma_buf_undup_mem_handles(sp, 0, priv->num_objects, priv); + nv_dma_buf_undup_mem_handles(sp, params->index, params->numObjects, priv); cleanup_client_and_device: rm_dma_buf_put_client_and_device(sp, priv->nv, priv->h_client, priv->h_device, @@ -877,6 +1226,28 @@ goto cleanup_sp; } + // Get CPU static phys addresses if possible to do so at this time. + if (priv->static_phys_addrs) + { + status = nv_dma_buf_get_phys_addresses(priv, params->index, + params->numObjects); + if (status != NV_OK) + { + goto cleanup_handles; + } + } + + nv_kmem_cache_free_stack(sp); + + mutex_unlock(&priv->lock); + + dma_buf_put(buf); + + return NV_OK; + +cleanup_handles: + nv_dma_buf_undup_mem_handles(sp, params->index, params->numObjects, priv); + cleanup_sp: nv_kmem_cache_free_stack(sp); diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/kernel-open/nvidia/nv-kthread-q.c nvidia-open-gpu-kernel-modules-535.161.08/kernel-open/nvidia/nv-kthread-q.c --- nvidia-open-gpu-kernel-modules-525.147.05/kernel-open/nvidia/nv-kthread-q.c 2023-10-25 20:33:20.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/kernel-open/nvidia/nv-kthread-q.c 2024-03-05 22:25:32.000000000 +0000 @@ -301,7 +301,7 @@ static void _raw_q_flush(nv_kthread_q_t *q) { nv_kthread_q_item_t q_item; - DECLARE_COMPLETION(completion); + DECLARE_COMPLETION_ONSTACK(completion); nv_kthread_q_item_init(&q_item, _q_flush_function, &completion); diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/kernel-open/nvidia/nv-mmap.c nvidia-open-gpu-kernel-modules-535.161.08/kernel-open/nvidia/nv-mmap.c --- nvidia-open-gpu-kernel-modules-525.147.05/kernel-open/nvidia/nv-mmap.c 2023-10-25 20:33:19.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/kernel-open/nvidia/nv-mmap.c 2024-03-05 22:25:31.000000000 +0000 @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 1999-2021 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 1999-2024 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -350,9 +350,15 @@ return 1; #endif case NV_MEMORY_CACHED: - if (NV_ALLOW_CACHING(memory_type)) - break; - // Intentional fallthrough. + if (!NV_ALLOW_CACHING(memory_type)) + { + nv_printf(NV_DBG_ERRORS, + "NVRM: VM: memory type %d does not allow caching!\n", + memory_type); + return 1; + } + break; + default: nv_printf(NV_DBG_ERRORS, "NVRM: VM: cache type %d not supported for memory type %d!\n", @@ -529,6 +535,7 @@ { return -ENXIO; } + if (IS_REG_OFFSET(nv, access_start, access_len)) { if (nv_encode_caching(&vma->vm_page_prot, NV_MEMORY_UNCACHED, @@ -570,12 +577,9 @@ // // This path is similar to the sysmem mapping code. // TODO: Refactor is needed as part of bug#2001704. - // Use pfn_valid to determine whether the physical address has - // backing struct page. This is used to isolate P8 from P9. // if ((nv_get_numa_status(nvl) == NV_NUMA_STATUS_ONLINE) && - !IS_REG_OFFSET(nv, access_start, access_len) && - (pfn_valid(PFN_DOWN(mmap_start)))) + !IS_REG_OFFSET(nv, access_start, access_len)) { ret = nvidia_mmap_numa(vma, mmap_context); if (ret) diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/kernel-open/nvidia/nv-msi.c nvidia-open-gpu-kernel-modules-535.161.08/kernel-open/nvidia/nv-msi.c --- nvidia-open-gpu-kernel-modules-525.147.05/kernel-open/nvidia/nv-msi.c 2023-10-25 20:33:20.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/kernel-open/nvidia/nv-msi.c 2024-03-05 22:25:33.000000000 +0000 @@ -156,7 +156,7 @@ { for( j = 0; j < i; j++) { - free_irq(nvl->msix_entries[i].vector, (void *)nvl); + free_irq(nvl->msix_entries[j].vector, (void *)nvl); } break; } diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/kernel-open/nvidia/nv-nano-timer.c nvidia-open-gpu-kernel-modules-535.161.08/kernel-open/nvidia/nv-nano-timer.c --- nvidia-open-gpu-kernel-modules-525.147.05/kernel-open/nvidia/nv-nano-timer.c 2023-10-25 20:33:19.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/kernel-open/nvidia/nv-nano-timer.c 2024-03-05 22:25:31.000000000 +0000 @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 2020-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2020-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -174,7 +174,7 @@ * * @param[in] nv Per gpu linux state * @param[in] nv_nstimer Pointer to nv_nano_timer_t object - * @param[in] timens time in nano seconds + * @param[in] time_ns Relative time in nano seconds */ void NV_API_CALL nv_start_nano_timer( nv_state_t *nv, diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/kernel-open/nvidia/nv-p2p.c nvidia-open-gpu-kernel-modules-535.161.08/kernel-open/nvidia/nv-p2p.c --- nvidia-open-gpu-kernel-modules-525.147.05/kernel-open/nvidia/nv-p2p.c 2023-10-25 20:33:19.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/kernel-open/nvidia/nv-p2p.c 2024-03-05 22:25:31.000000000 +0000 @@ -316,14 +316,14 @@ return -ENOTSUPP; } -EXPORT_SYMBOL(nvidia_p2p_init_mapping); +NV_EXPORT_SYMBOL(nvidia_p2p_init_mapping); int nvidia_p2p_destroy_mapping(uint64_t p2p_token) { return -ENOTSUPP; } -EXPORT_SYMBOL(nvidia_p2p_destroy_mapping); +NV_EXPORT_SYMBOL(nvidia_p2p_destroy_mapping); static void nv_p2p_mem_info_free_callback(void *data) { @@ -587,7 +587,7 @@ p2p_token, va_space, virtual_address, length, page_table, free_callback, data); } -EXPORT_SYMBOL(nvidia_p2p_get_pages); +NV_EXPORT_SYMBOL(nvidia_p2p_get_pages); int nvidia_p2p_get_pages_persistent( uint64_t virtual_address, @@ -605,7 +605,7 @@ virtual_address, length, page_table, NULL, NULL); } -EXPORT_SYMBOL(nvidia_p2p_get_pages_persistent); +NV_EXPORT_SYMBOL(nvidia_p2p_get_pages_persistent); /* * This function is a no-op, but is left in place (for now), in order to allow @@ -618,7 +618,7 @@ return 0; } -EXPORT_SYMBOL(nvidia_p2p_free_page_table); +NV_EXPORT_SYMBOL(nvidia_p2p_free_page_table); int nvidia_p2p_put_pages( uint64_t p2p_token, @@ -650,7 +650,7 @@ return nvidia_p2p_map_status(status); } -EXPORT_SYMBOL(nvidia_p2p_put_pages); +NV_EXPORT_SYMBOL(nvidia_p2p_put_pages); int nvidia_p2p_put_pages_persistent( uint64_t virtual_address, @@ -690,7 +690,7 @@ return nvidia_p2p_map_status(status); } -EXPORT_SYMBOL(nvidia_p2p_put_pages_persistent); +NV_EXPORT_SYMBOL(nvidia_p2p_put_pages_persistent); int nvidia_p2p_dma_map_pages( struct pci_dev *peer, @@ -805,7 +805,7 @@ return nvidia_p2p_map_status(status); } -EXPORT_SYMBOL(nvidia_p2p_dma_map_pages); +NV_EXPORT_SYMBOL(nvidia_p2p_dma_map_pages); int nvidia_p2p_dma_unmap_pages( struct pci_dev *peer, @@ -845,7 +845,7 @@ return 0; } -EXPORT_SYMBOL(nvidia_p2p_dma_unmap_pages); +NV_EXPORT_SYMBOL(nvidia_p2p_dma_unmap_pages); /* * This function is a no-op, but is left in place (for now), in order to allow @@ -860,7 +860,7 @@ return 0; } -EXPORT_SYMBOL(nvidia_p2p_free_dma_mapping); +NV_EXPORT_SYMBOL(nvidia_p2p_free_dma_mapping); int nvidia_p2p_register_rsync_driver( nvidia_p2p_rsync_driver_t *driver, @@ -889,7 +889,7 @@ driver->wait_for_rsync, data); } -EXPORT_SYMBOL(nvidia_p2p_register_rsync_driver); +NV_EXPORT_SYMBOL(nvidia_p2p_register_rsync_driver); void nvidia_p2p_unregister_rsync_driver( nvidia_p2p_rsync_driver_t *driver, @@ -921,7 +921,7 @@ driver->wait_for_rsync, data); } -EXPORT_SYMBOL(nvidia_p2p_unregister_rsync_driver); +NV_EXPORT_SYMBOL(nvidia_p2p_unregister_rsync_driver); int nvidia_p2p_get_rsync_registers( nvidia_p2p_rsync_reg_info_t **reg_info @@ -1014,7 +1014,7 @@ return 0; } -EXPORT_SYMBOL(nvidia_p2p_get_rsync_registers); +NV_EXPORT_SYMBOL(nvidia_p2p_get_rsync_registers); void nvidia_p2p_put_rsync_registers( nvidia_p2p_rsync_reg_info_t *reg_info @@ -1046,4 +1046,4 @@ os_free_mem(reg_info); } -EXPORT_SYMBOL(nvidia_p2p_put_rsync_registers); +NV_EXPORT_SYMBOL(nvidia_p2p_put_rsync_registers); diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/kernel-open/nvidia/nv-pci.c nvidia-open-gpu-kernel-modules-535.161.08/kernel-open/nvidia/nv-pci.c --- nvidia-open-gpu-kernel-modules-525.147.05/kernel-open/nvidia/nv-pci.c 2023-10-25 20:33:19.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/kernel-open/nvidia/nv-pci.c 2024-03-05 22:25:31.000000000 +0000 @@ -156,6 +156,185 @@ rm_init_dynamic_power_management(sp, nv, pr3_acpi_method_present); } +static int nv_resize_pcie_bars(struct pci_dev *pci_dev) { +#if defined(NV_PCI_REBAR_GET_POSSIBLE_SIZES_PRESENT) + u16 cmd; + int r, old_size, requested_size; + unsigned long sizes; + int ret = 0; +#if NV_IS_EXPORT_SYMBOL_PRESENT_pci_find_host_bridge + struct pci_host_bridge *host; +#endif + + if (NVreg_EnableResizableBar == 0) + { + nv_printf(NV_DBG_INFO, "NVRM: resizable BAR disabled by regkey, skipping\n"); + return 0; + } + + // Check if BAR1 has PCIe rebar capabilities + sizes = pci_rebar_get_possible_sizes(pci_dev, NV_GPU_BAR1); + if (sizes == 0) { + /* ReBAR not available. Nothing to do. */ + return 0; + } + + /* Try to resize the BAR to the largest supported size */ + requested_size = fls(sizes) - 1; + + /* Save the current size, just in case things go wrong */ + old_size = pci_rebar_bytes_to_size(pci_resource_len(pci_dev, NV_GPU_BAR1)); + + if (old_size == requested_size) { + nv_printf(NV_DBG_INFO, "NVRM: %04x:%02x:%02x.%x: BAR1 already at requested size.\n", + NV_PCI_DOMAIN_NUMBER(pci_dev), NV_PCI_BUS_NUMBER(pci_dev), + NV_PCI_SLOT_NUMBER(pci_dev), PCI_FUNC(pci_dev->devfn)); + return 0; + } +#if NV_IS_EXPORT_SYMBOL_PRESENT_pci_find_host_bridge + /* If the kernel will refuse us, don't even try to resize, + but give an informative error */ + host = pci_find_host_bridge(pci_dev->bus); + if (host->preserve_config) { + nv_printf(NV_DBG_INFO, "NVRM: Not resizing BAR because the firmware forbids moving windows.\n"); + return 0; + } +#endif + nv_printf(NV_DBG_INFO, "NVRM: %04x:%02x:%02x.%x: Attempting to resize BAR1.\n", + NV_PCI_DOMAIN_NUMBER(pci_dev), NV_PCI_BUS_NUMBER(pci_dev), + NV_PCI_SLOT_NUMBER(pci_dev), PCI_FUNC(pci_dev->devfn)); + + /* Disable memory decoding - required by the kernel APIs */ + pci_read_config_word(pci_dev, PCI_COMMAND, &cmd); + pci_write_config_word(pci_dev, PCI_COMMAND, cmd & ~PCI_COMMAND_MEMORY); + + /* Release BAR1 */ + pci_release_resource(pci_dev, NV_GPU_BAR1); + + /* Release BAR3 - we don't want to resize it, it's in the same bridge, so we'll want to move it */ + pci_release_resource(pci_dev, NV_GPU_BAR3); + +resize: + /* Attempt to resize BAR1 to the largest supported size */ + r = pci_resize_resource(pci_dev, NV_GPU_BAR1, requested_size); + + if (r) { + if (r == -ENOSPC) + { + /* step through smaller sizes down to original size */ + if (requested_size > old_size) + { + clear_bit(fls(sizes) - 1, &sizes); + requested_size = fls(sizes) - 1; + goto resize; + } + else + { + nv_printf(NV_DBG_ERRORS, "NVRM: No address space to allocate resized BAR1.\n"); + } + } + else if (r == -EOPNOTSUPP) + { + nv_printf(NV_DBG_WARNINGS, "NVRM: BAR resize resource not supported.\n"); + } + else + { + nv_printf(NV_DBG_WARNINGS, "NVRM: BAR resizing failed with error `%d`.\n", r); + } + } + + /* Re-attempt assignment of PCIe resources */ + pci_assign_unassigned_bus_resources(pci_dev->bus); + + if ((pci_resource_flags(pci_dev, NV_GPU_BAR1) & IORESOURCE_UNSET) || + (pci_resource_flags(pci_dev, NV_GPU_BAR3) & IORESOURCE_UNSET)) { + if (requested_size != old_size) { + /* Try to get the BAR back with the original size */ + requested_size = old_size; + goto resize; + } + /* Something went horribly wrong and the kernel didn't manage to re-allocate BAR1. + This is unlikely (because we had space before), but can happen. */ + nv_printf(NV_DBG_ERRORS, "NVRM: FATAL: Failed to re-allocate BAR1.\n"); + ret = -ENODEV; + } + + /* Re-enable memory decoding */ + pci_write_config_word(pci_dev, PCI_COMMAND, cmd); + + return ret; +#else + nv_printf(NV_DBG_INFO, "NVRM: Resizable BAR is not supported on this kernel version.\n"); + return 0; +#endif /* NV_PCI_REBAR_GET_POSSIBLE_SIZES_PRESENT */ +} + +static void +nv_init_coherent_link_info +( + nv_state_t *nv +) +{ +#if defined(NV_DEVICE_PROPERTY_READ_U64_PRESENT) && \ + defined(CONFIG_ACPI_NUMA) && \ + NV_IS_EXPORT_SYMBOL_PRESENT_pxm_to_node + nv_linux_state_t *nvl = NV_GET_NVL_FROM_NV_STATE(nv); + NvU64 pa = 0; + NvU64 pxm_start = 0; + NvU64 pxm_count = 0; + NvU32 pxm; + + if (!NVCPU_IS_AARCH64) + return; + + if (device_property_read_u64(nvl->dev, "nvidia,gpu-mem-base-pa", &pa) != 0) + goto failed; + if (device_property_read_u64(nvl->dev, "nvidia,gpu-mem-pxm-start", &pxm_start) != 0) + goto failed; + if (device_property_read_u64(nvl->dev, "nvidia,gpu-mem-pxm-count", &pxm_count) != 0) + goto failed; + + NV_DEV_PRINTF(NV_DBG_INFO, nv, "DSD properties: \n"); + NV_DEV_PRINTF(NV_DBG_INFO, nv, "\tGPU memory PA: 0x%lx \n", pa); + NV_DEV_PRINTF(NV_DBG_INFO, nv, "\tGPU memory PXM start: %u \n", pxm_start); + NV_DEV_PRINTF(NV_DBG_INFO, nv, "\tGPU memory PXM count: %u \n", pxm_count); + + nvl->coherent_link_info.gpu_mem_pa = pa; + + for (pxm = pxm_start; pxm < (pxm_start + pxm_count); pxm++) + { + NvU32 node = pxm_to_node(pxm); + if (node != NUMA_NO_NODE) + { + set_bit(node, nvl->coherent_link_info.free_node_bitmap); + } + } + + if (NVreg_EnableUserNUMAManagement) + { + NV_ATOMIC_SET(nvl->numa_info.status, NV_IOCTL_NUMA_STATUS_OFFLINE); + nvl->numa_info.use_auto_online = NV_TRUE; + + if (!bitmap_empty(nvl->coherent_link_info.free_node_bitmap, MAX_NUMNODES)) + { + nvl->numa_info.node_id = find_first_bit(nvl->coherent_link_info.free_node_bitmap, MAX_NUMNODES); + } + NV_DEV_PRINTF(NV_DBG_SETUP, nv, "GPU NUMA information: node id: %u PA: 0x%llx\n", + nvl->numa_info.node_id, nvl->coherent_link_info.gpu_mem_pa); + } + else + { + NV_DEV_PRINTF(NV_DBG_SETUP, nv, "User-mode NUMA onlining disabled.\n"); + } + + return; + +failed: + NV_DEV_PRINTF(NV_DBG_SETUP, nv, "Cannot get coherent link info.\n"); +#endif + return; +} + /* find nvidia devices and set initial state */ static int nv_pci_probe @@ -349,6 +528,14 @@ (NvU64)NV_PCI_RESOURCE_START(pci_dev, i), NV_PCI_DOMAIN_NUMBER(pci_dev), NV_PCI_BUS_NUMBER(pci_dev), NV_PCI_SLOT_NUMBER(pci_dev), PCI_FUNC(pci_dev->devfn)); + + // With GH180 C2C, VF BAR1/2 are disabled and therefore expected to be 0. + if (j != NV_GPU_BAR_INDEX_REGS) + { + nv_printf(NV_DBG_INFO, "NVRM: ignore invalid BAR failure for BAR%d\n", j); + continue; + } + goto failed; } @@ -365,6 +552,12 @@ goto failed; } + if (nv_resize_pcie_bars(pci_dev)) { + nv_printf(NV_DBG_ERRORS, + "NVRM: Fatal Error while attempting to resize PCIe BARs.\n"); + goto failed; + } + NV_KZALLOC(nvl, sizeof(nv_linux_state_t)); if (nvl == NULL) { @@ -427,11 +620,16 @@ nv_init_ibmnpu_info(nv); + nv_init_coherent_link_info(nv); + #if defined(NVCPU_PPC64LE) // Use HW NUMA support as a proxy for ATS support. This is true in the only // PPC64LE platform where ATS is currently supported (IBM P9). nv_ats_supported &= nv_platform_supports_numa(nvl); #else +#if defined(NV_PCI_DEV_HAS_ATS_ENABLED) + nv_ats_supported &= pci_dev->ats_enabled; +#endif #endif if (nv_ats_supported) { diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/kernel-open/nvidia/nv-procfs.c nvidia-open-gpu-kernel-modules-535.161.08/kernel-open/nvidia/nv-procfs.c --- nvidia-open-gpu-kernel-modules-525.147.05/kernel-open/nvidia/nv-procfs.c 2023-10-25 20:33:19.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/kernel-open/nvidia/nv-procfs.c 2024-03-05 22:25:32.000000000 +0000 @@ -1016,6 +1016,23 @@ rm_status = rm_get_gpu_numa_info(sp, nv, nid, numa_mem_addr, numa_mem_size, list->addresses, &list->numEntries); + + if (rm_status == NV_OK && *nid == NUMA_NO_NODE) + { + // + // RM returns NUMA_NO_NODE when running MIG instances because + // this rmClient is not subscribed to any MIG partition since + // it was subscribed to whole GPU only during RMInit and is not + // updated when MIG partitions are created. + // Returning error here so that numa_status results in EIO + // because of missing support in numa_status to use it for multiple + // numa nodes. + // + // TODO: add support for multiple numa nodes in numa_status interface + // and remove this check, bug 4006012 + // + rm_status = NV_ERR_NOT_SUPPORTED; + } *status = nv_get_numa_status(nvl); done: diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/kernel-open/nvidia/nv-reg.h nvidia-open-gpu-kernel-modules-535.161.08/kernel-open/nvidia/nv-reg.h --- nvidia-open-gpu-kernel-modules-525.147.05/kernel-open/nvidia/nv-reg.h 2023-10-25 20:33:21.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/kernel-open/nvidia/nv-reg.h 2024-03-05 22:25:34.000000000 +0000 @@ -21,10 +21,15 @@ * DEALINGS IN THE SOFTWARE. */ +// +// This file holds Unix-specific NVIDIA driver options +// + #ifndef _RM_REG_H_ #define _RM_REG_H_ #include "nvtypes.h" +#include "nv-firmware-registry.h" /* * use NV_REG_STRING to stringify a registry key when using that registry key @@ -700,6 +705,22 @@ NV_REG_STRING(__NV_ENABLE_PCIE_RELAXED_ORDERING_MODE) /* + * Option: EnableResizableBar + * + * Description: + * + * When this option is enabled, the NVIDIA driver will attempt to resize + * BAR1 to match framebuffer size, or the next largest available size on + * supported machines. This is currently only implemented for Linux. + * + * Possible values: + * 0 - Do not enable PCI BAR resizing + * 1 - Enable PCI BAR resizing + */ +#define __NV_ENABLE_RESIZABLE_BAR EnableResizableBar +#define NV_REG_ENABLE_RESIZABLE_BAR NV_REG_STRING(__NV_ENABLE_RESIZABLE_BAR) + +/* * Option: EnableGpuFirmware * * Description: @@ -707,72 +728,33 @@ * When this option is enabled, the NVIDIA driver will enable use of GPU * firmware. * - * Possible mode values: - * 0 - Do not enable GPU firmware - * 1 - Enable GPU firmware - * 2 - (Default) Use the default enablement policy for GPU firmware - * - * Setting this to anything other than 2 will alter driver firmware- - * enablement policies, possibly disabling GPU firmware where it would - * have otherwise been enabled by default. - * * If this key is set globally to the system, the driver may still attempt * to apply some policies to maintain uniform firmware modes across all * GPUS. This may result in the driver failing initialization on some GPUs * to maintain such a policy. - * + * * If this key is set using NVreg_RegistryDwordsPerDevice, then the driver * will attempt to honor whatever configuration is specified without applying * additional policies. This may also result in failed GPU initialzations if * the configuration is not possible (for example if the firmware is missing - * from the filesystem, or the GPU is not capable). - * - * Policy bits: - * - * POLICY_ALLOW_FALLBACK: - * As the normal behavior is to fail GPU initialization if this registry - * entry is set in such a way that results in an invalid configuration, if - * instead the user would like the driver to automatically try to fallback - * to initializing the failing GPU with firmware disabled, then this bit can - * be set (ex: 0x11 means try to enable GPU firmware but fall back if needed). - * Note that this can result in a mixed mode configuration (ex: GPU0 has - * firmware enabled, but GPU1 does not). + * from the filesystem, or the GPU is not capable). * + * NOTE: More details for this regkey can be found in nv-firmware-registry.h */ - #define __NV_ENABLE_GPU_FIRMWARE EnableGpuFirmware #define NV_REG_ENABLE_GPU_FIRMWARE NV_REG_STRING(__NV_ENABLE_GPU_FIRMWARE) -#define NV_REG_ENABLE_GPU_FIRMWARE_MODE_MASK 0x0000000F -#define NV_REG_ENABLE_GPU_FIRMWARE_MODE_DISABLED 0x00000000 -#define NV_REG_ENABLE_GPU_FIRMWARE_MODE_ENABLED 0x00000001 -#define NV_REG_ENABLE_GPU_FIRMWARE_MODE_DEFAULT 0x00000002 - -#define NV_REG_ENABLE_GPU_FIRMWARE_POLICY_MASK 0x000000F0 -#define NV_REG_ENABLE_GPU_FIRMWARE_POLICY_ALLOW_FALLBACK 0x00000010 - -#define NV_REG_ENABLE_GPU_FIRMWARE_DEFAULT_VALUE 0x00000012 -#define NV_REG_ENABLE_GPU_FIRMWARE_INVALID_VALUE 0xFFFFFFFF - /* * Option: EnableGpuFirmwareLogs * * When this option is enabled, the NVIDIA driver will send GPU firmware logs * to the system log, when possible. * - * Possible values: - * 0 - Do not send GPU firmware logs to the system log - * 1 - Enable sending of GPU firmware logs to the system log - * 2 - (Default) Enable sending of GPU firmware logs to the system log for - * the debug kernel driver build only + * NOTE: More details for this regkey can be found in nv-firmware-registry.h */ #define __NV_ENABLE_GPU_FIRMWARE_LOGS EnableGpuFirmwareLogs #define NV_REG_ENABLE_GPU_FIRMWARE_LOGS NV_REG_STRING(__NV_ENABLE_GPU_FIRMWARE_LOGS) -#define NV_REG_ENABLE_GPU_FIRMWARE_LOGS_DISABLE 0x00000000 -#define NV_REG_ENABLE_GPU_FIRMWARE_LOGS_ENABLE 0x00000001 -#define NV_REG_ENABLE_GPU_FIRMWARE_LOGS_ENABLE_ON_DEBUG 0x00000002 - /* * Option: EnableDbgBreakpoint * @@ -825,6 +807,26 @@ #define NV_DMA_REMAP_PEER_MMIO_DISABLE 0x00000000 #define NV_DMA_REMAP_PEER_MMIO_ENABLE 0x00000001 +/* + * Option: NVreg_RmNvlinkBandwidth + * + * Description: + * + * This option allows user to reduce the NVLINK P2P bandwidth to save power. + * The option is in the string format. + * + * Possible string values: + * OFF: 0% bandwidth + * MIN: 15%-25% bandwidth depending on the system's NVLink topology + * HALF: 50% bandwidth + * 3QUARTER: 75% bandwidth + * FULL: 100% bandwidth (default) + * + * This option is only for Hopper+ GPU with NVLINK version 4.0. + */ +#define __NV_RM_NVLINK_BW RmNvlinkBandwidth +#define NV_RM_NVLINK_BW NV_REG_STRING(__NV_RM_NVLINK_BW) + #if defined(NV_DEFINE_REGISTRY_KEY_TABLE) /* @@ -861,6 +863,7 @@ NV_DEFINE_REG_ENTRY_GLOBAL(__NV_NVLINK_DISABLE, 0); NV_DEFINE_REG_ENTRY_GLOBAL(__NV_ENABLE_PCIE_RELAXED_ORDERING_MODE, 0); NV_DEFINE_REG_ENTRY_GLOBAL(__NV_REGISTER_PCI_DRIVER, 1); +NV_DEFINE_REG_ENTRY_GLOBAL(__NV_ENABLE_RESIZABLE_BAR, 0); NV_DEFINE_REG_ENTRY_GLOBAL(__NV_ENABLE_DBG_BREAKPOINT, 0); NV_DEFINE_REG_STRING_ENTRY(__NV_REGISTRY_DWORDS, NULL); @@ -870,6 +873,7 @@ NV_DEFINE_REG_STRING_ENTRY(__NV_TEMPORARY_FILE_PATH, NULL); NV_DEFINE_REG_STRING_ENTRY(__NV_EXCLUDED_GPUS, NULL); NV_DEFINE_REG_ENTRY(__NV_DMA_REMAP_PEER_MMIO, NV_DMA_REMAP_PEER_MMIO_ENABLE); +NV_DEFINE_REG_STRING_ENTRY(__NV_RM_NVLINK_BW, NULL); /* *----------------registry database definition---------------------- @@ -910,6 +914,7 @@ NV_DEFINE_PARAMS_TABLE_ENTRY(__NV_DYNAMIC_POWER_MANAGEMENT_VIDEO_MEMORY_THRESHOLD), NV_DEFINE_PARAMS_TABLE_ENTRY(__NV_REGISTER_PCI_DRIVER), NV_DEFINE_PARAMS_TABLE_ENTRY(__NV_ENABLE_PCIE_RELAXED_ORDERING_MODE), + NV_DEFINE_PARAMS_TABLE_ENTRY(__NV_ENABLE_RESIZABLE_BAR), NV_DEFINE_PARAMS_TABLE_ENTRY(__NV_ENABLE_GPU_FIRMWARE), NV_DEFINE_PARAMS_TABLE_ENTRY(__NV_ENABLE_GPU_FIRMWARE_LOGS), NV_DEFINE_PARAMS_TABLE_ENTRY(__NV_ENABLE_DBG_BREAKPOINT), diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/kernel-open/nvidia/nv-vm.c nvidia-open-gpu-kernel-modules-535.161.08/kernel-open/nvidia/nv-vm.c --- nvidia-open-gpu-kernel-modules-525.147.05/kernel-open/nvidia/nv-vm.c 2023-10-25 20:33:19.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/kernel-open/nvidia/nv-vm.c 2024-03-05 22:25:32.000000000 +0000 @@ -265,7 +265,7 @@ gfp_mask |= __GFP_ZERO; #endif #if defined(__GFP_THISNODE) - if (at->flags.node0) + if (at->flags.node) gfp_mask |= __GFP_THISNODE; #endif // Compound pages are required by vm_insert_page for high-order page @@ -384,9 +384,9 @@ at->order = get_order(at->num_pages * PAGE_SIZE); gfp_mask = nv_compute_gfp_mask(nv, at); - if (at->flags.node0) + if (at->flags.node) { - NV_ALLOC_PAGES_NODE(virt_addr, 0, at->order, gfp_mask); + NV_ALLOC_PAGES_NODE(virt_addr, at->node_id, at->order, gfp_mask); } else { @@ -529,9 +529,9 @@ gfp_mask); at->flags.coherent = NV_TRUE; } - else if (at->flags.node0) + else if (at->flags.node) { - NV_ALLOC_PAGES_NODE(virt_addr, 0, 0, gfp_mask); + NV_ALLOC_PAGES_NODE(virt_addr, at->node_id, 0, gfp_mask); } else { diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/kernel-open/nvidia/nv.c nvidia-open-gpu-kernel-modules-535.161.08/kernel-open/nvidia/nv.c --- nvidia-open-gpu-kernel-modules-525.147.05/kernel-open/nvidia/nv.c 2023-10-25 20:33:19.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/kernel-open/nvidia/nv.c 2024-03-05 22:25:31.000000000 +0000 @@ -86,8 +86,18 @@ #include +#if defined(NV_LINUX_CC_PLATFORM_H_PRESENT) +#include +#endif + +#if defined(NV_ASM_CPUFEATURE_H_PRESENT) +#include +#endif + #include "conftest/patches.h" +#include "detect-self-hosted.h" + #define RM_THRESHOLD_TOTAL_IRQ_COUNT 100000 #define RM_THRESHOLD_UNAHNDLED_IRQ_COUNT 99900 #define RM_UNHANDLED_TIMEOUT_US 100000 @@ -142,6 +152,9 @@ // True if all the successfully probed devices support ATS // Assigned at device probe (module init) time NvBool nv_ats_supported = NVCPU_IS_PPC64LE +#if defined(NV_PCI_DEV_HAS_ATS_ENABLED) + || NV_TRUE +#endif ; // allow an easy way to convert all debug printfs related to events @@ -229,51 +242,23 @@ *** STATIC functions ***/ -#if defined(NVCPU_X86_64) -#define NV_AMD_SEV_BIT BIT(1) - static -NvBool nv_is_sev_supported( +void nv_detect_conf_compute_platform( void ) { - unsigned int eax, ebx, ecx, edx; +#if defined(NV_CC_PLATFORM_PRESENT) + os_cc_enabled = cc_platform_has(CC_ATTR_GUEST_MEM_ENCRYPT); - /* Check for the SME/SEV support leaf */ - eax = 0x80000000; - ecx = 0; - native_cpuid(&eax, &ebx, &ecx, &edx); - if (eax < 0x8000001f) - return NV_FALSE; - - eax = 0x8000001f; - ecx = 0; - native_cpuid(&eax, &ebx, &ecx, &edx); - /* Check whether SEV is supported */ - if (!(eax & NV_AMD_SEV_BIT)) - return NV_FALSE; - - return NV_TRUE; -} -#endif - -static -void nv_sev_init( - void -) -{ -#if defined(MSR_AMD64_SEV) && defined(NVCPU_X86_64) - NvU32 lo_val, hi_val; - - if (!nv_is_sev_supported()) - return; - - rdmsr(MSR_AMD64_SEV, lo_val, hi_val); - - os_sev_status = lo_val; -#if defined(MSR_AMD64_SEV_ENABLED) - os_sev_enabled = (os_sev_status & MSR_AMD64_SEV_ENABLED); +#if defined(X86_FEATURE_TDX_GUEST) + if (cpu_feature_enabled(X86_FEATURE_TDX_GUEST)) + { + os_cc_tdx_enabled = NV_TRUE; + } #endif +#else + os_cc_enabled = NV_FALSE; + os_cc_tdx_enabled = NV_FALSE; #endif } @@ -679,7 +664,7 @@ } nv_init_rsync_info(); - nv_sev_init(); + nv_detect_conf_compute_platform(); if (!rm_init_rm(*sp)) { @@ -1174,6 +1159,7 @@ #endif int rc = 0; NvBool kthread_init = NV_FALSE; + NvBool remove_numa_memory_kthread_init = NV_FALSE; NvBool power_ref = NV_FALSE; rc = nv_get_rsync_info(); @@ -1238,12 +1224,11 @@ rm_read_registry_dword(sp, nv, NV_REG_ENABLE_MSI, &msi_config); if (msi_config == 1) { - if (pci_find_capability(nvl->pci_dev, PCI_CAP_ID_MSIX)) + if (nvl->pci_dev->msix_cap && rm_is_msix_allowed(sp, nv)) { nv_init_msix(nv); } - if (pci_find_capability(nvl->pci_dev, PCI_CAP_ID_MSI) && - !(nv->flags & NV_FLAG_USES_MSIX)) + if (nvl->pci_dev->msi_cap && !(nv->flags & NV_FLAG_USES_MSIX)) { nv_init_msi(nv); } @@ -1311,6 +1296,15 @@ if (rc) goto failed; nv->queue = &nvl->queue; + + if (nv_platform_use_auto_online(nvl)) + { + rc = nv_kthread_q_init(&nvl->remove_numa_memory_q, + "nv_remove_numa_memory"); + if (rc) + goto failed; + remove_numa_memory_kthread_init = NV_TRUE; + } } if (!rm_init_adapter(sp, nv)) @@ -1355,6 +1349,8 @@ nv->flags |= NV_FLAG_OPEN; + rm_request_dnotifier_state(sp, nv); + /* * Now that RM init is done, allow dynamic power to control the GPU in FINE * mode, if enabled. (If the mode is COARSE, this unref will do nothing @@ -1399,6 +1395,12 @@ if (kthread_init && !(nv->flags & NV_FLAG_PERSISTENT_SW_STATE)) nv_kthread_q_stop(&nvl->bottom_half_q); + if (remove_numa_memory_kthread_init && + !(nv->flags & NV_FLAG_PERSISTENT_SW_STATE)) + { + nv_kthread_q_stop(&nvl->remove_numa_memory_q); + } + if (nvl->isr_bh_unlocked_mutex) { os_free_mutex(nvl->isr_bh_unlocked_mutex); @@ -1635,7 +1637,9 @@ nv_state_t *nv, nv_linux_state_t *nvl) { +#if defined(NVCPU_PPC64LE) validate_numa_shutdown_state(nvl); +#endif rm_disable_adapter(sp, nv); @@ -1687,6 +1691,9 @@ } rm_shutdown_adapter(sp, nv); + + if (nv_platform_use_auto_online(nvl)) + nv_kthread_q_stop(&nvl->remove_numa_memory_q); } /* @@ -2241,6 +2248,7 @@ } api->status = nv_get_numa_status(nvl); + api->use_auto_online = nv_platform_use_auto_online(nvl); api->memblock_size = nv_ctl_device.numa_memblock_size; break; } @@ -3321,6 +3329,7 @@ NvU32 cache_type, NvBool zeroed, NvBool unencrypted, + NvS32 node_id, NvU64 *pte_array, void **priv_data ) @@ -3332,7 +3341,7 @@ NvU32 i; struct device *dev = NULL; - nv_printf(NV_DBG_MEMINFO, "NVRM: VM: nv_alloc_pages: %d pages\n", page_count); + nv_printf(NV_DBG_MEMINFO, "NVRM: VM: nv_alloc_pages: %d pages, nodeid %d\n", page_count, node_id); nv_printf(NV_DBG_MEMINFO, "NVRM: VM: contig %d cache_type %d\n", contiguous, cache_type); @@ -3390,9 +3399,18 @@ * See Bug 1920398 for more details. */ if (nv && nvl->npu && !nvl->dma_dev.nvlink) - at->flags.node0 = NV_TRUE; + { + at->flags.node = NV_TRUE; + at->node_id = 0; + } #endif + if (node_id != NUMA_NO_NODE) + { + at->flags.node = NV_TRUE; + at->node_id = node_id; + } + if (at->flags.contig) status = nv_alloc_contig_pages(nv, at); else @@ -4903,6 +4921,28 @@ status = NV_OK; #endif +#if defined(NVCPU_AARCH64) + if (node_id != NULL) + { + *node_id = nvl->numa_info.node_id; + } + + if (compr_addr_sys_phys) + { + *compr_addr_sys_phys = nvl->coherent_link_info.gpu_mem_pa; + } + if (addr_guest_phys) + { + *addr_guest_phys = nvl->coherent_link_info.gpu_mem_pa; + } + if (addr_width) + { + // TH500 PA width - NV_PFB_PRI_MMU_ATS_ADDR_RANGE_GRANULARITY + *addr_width = 48 - 37; + } + + status = NV_OK; +#endif return status; } @@ -5087,23 +5127,36 @@ void NV_API_CALL nv_control_soc_irqs(nv_state_t *nv, NvBool bEnable) { int count; + unsigned long flags; + nv_linux_state_t *nvl = NV_GET_NVL_FROM_NV_STATE(nv); + if (nv->current_soc_irq != -1) + return; + + NV_SPIN_LOCK_IRQSAVE(&nvl->soc_isr_lock, flags); if (bEnable) { for (count = 0; count < nv->num_soc_irqs; count++) { - nv->soc_irq_info[count].bh_pending = NV_FALSE; - nv->current_soc_irq = -1; - enable_irq(nv->soc_irq_info[count].irq_num); + if (nv->soc_irq_info[count].ref_count == 0) + { + nv->soc_irq_info[count].ref_count++; + enable_irq(nv->soc_irq_info[count].irq_num); + } } } else { for (count = 0; count < nv->num_soc_irqs; count++) { - disable_irq_nosync(nv->soc_irq_info[count].irq_num); + if (nv->soc_irq_info[count].ref_count == 1) + { + nv->soc_irq_info[count].ref_count--; + disable_irq_nosync(nv->soc_irq_info[count].irq_num); + } } } + NV_SPIN_UNLOCK_IRQRESTORE(&nvl->soc_isr_lock, flags); } NvU32 NV_API_CALL nv_get_dev_minor(nv_state_t *nv) @@ -5527,3 +5580,188 @@ *end = min((resource_size_t)*end, p->end); } } + +NV_STATUS NV_API_CALL nv_get_egm_info( + nv_state_t *nv, + NvU64 *phys_addr, + NvU64 *size, + NvS32 *egm_node_id +) +{ +#if defined(NV_DEVICE_PROPERTY_READ_U64_PRESENT) && \ + defined(CONFIG_ACPI_NUMA) && \ + NV_IS_EXPORT_SYMBOL_PRESENT_pxm_to_node + nv_linux_state_t *nvl = NV_GET_NVL_FROM_NV_STATE(nv); + NvU64 pa, sz, pxm; + + if (device_property_read_u64(nvl->dev, "nvidia,egm-pxm", &pxm) != 0) + { + goto failed; + } + + if (device_property_read_u64(nvl->dev, "nvidia,egm-base-pa", &pa) != 0) + { + goto failed; + } + + if (device_property_read_u64(nvl->dev, "nvidia,egm-size", &sz) != 0) + { + goto failed; + } + + NV_DEV_PRINTF(NV_DBG_INFO, nv, "DSD properties: \n"); + NV_DEV_PRINTF(NV_DBG_INFO, nv, "\tEGM base PA: 0x%llx \n", pa); + NV_DEV_PRINTF(NV_DBG_INFO, nv, "\tEGM size: 0x%llx \n", sz); + NV_DEV_PRINTF(NV_DBG_INFO, nv, "\tEGM _PXM: 0x%llx \n", pxm); + + if (egm_node_id != NULL) + { + *egm_node_id = pxm_to_node(pxm); + nv_printf(NV_DBG_INFO, "EGM node id: %d\n", *egm_node_id); + } + + if (phys_addr != NULL) + { + *phys_addr = pa; + nv_printf(NV_DBG_INFO, "EGM base addr: 0x%llx\n", *phys_addr); + } + + if (size != NULL) + { + *size = sz; + nv_printf(NV_DBG_INFO, "EGM size: 0x%llx\n", *size); + } + + return NV_OK; + +failed: +#endif // NV_DEVICE_PROPERTY_READ_U64_PRESENT + + NV_DEV_PRINTF(NV_DBG_INFO, nv, "Cannot get EGM info\n"); + return NV_ERR_NOT_SUPPORTED; +} + +void NV_API_CALL nv_get_screen_info( + nv_state_t *nv, + NvU64 *pPhysicalAddress, + NvU16 *pFbWidth, + NvU16 *pFbHeight, + NvU16 *pFbDepth, + NvU16 *pFbPitch, + NvU64 *pFbSize +) +{ + *pPhysicalAddress = 0; + *pFbWidth = *pFbHeight = *pFbDepth = *pFbPitch = *pFbSize = 0; + +#if defined(CONFIG_FB) && defined(NV_NUM_REGISTERED_FB_PRESENT) + if (num_registered_fb > 0) + { + int i; + + for (i = 0; i < num_registered_fb; i++) + { + if (!registered_fb[i]) + continue; + + /* Make sure base address is mapped to GPU BAR */ + if (NV_IS_CONSOLE_MAPPED(nv, registered_fb[i]->fix.smem_start)) + { + *pPhysicalAddress = registered_fb[i]->fix.smem_start; + *pFbWidth = registered_fb[i]->var.xres; + *pFbHeight = registered_fb[i]->var.yres; + *pFbDepth = registered_fb[i]->var.bits_per_pixel; + *pFbPitch = registered_fb[i]->fix.line_length; + *pFbSize = (NvU64)(*pFbHeight) * (NvU64)(*pFbPitch); + return; + } + } + } +#endif + + /* + * If the screen info is not found in the registered FBs then fallback + * to the screen_info structure. + * + * The SYSFB_SIMPLEFB option, if enabled, marks VGA/VBE/EFI framebuffers as + * generic framebuffers so the new generic system-framebuffer drivers can + * be used instead. DRM_SIMPLEDRM drives the generic system-framebuffers + * device created by SYSFB_SIMPLEFB. + * + * SYSFB_SIMPLEFB registers a dummy framebuffer which does not contain the + * information required by nv_get_screen_info(), therefore you need to + * fall back onto the screen_info structure. + * + * After commit b8466fe82b79 ("efi: move screen_info into efi init code") + * in v6.7, 'screen_info' is exported as GPL licensed symbol for ARM64. + */ + +#if NV_CHECK_EXPORT_SYMBOL(screen_info) + /* + * If there is not a framebuffer console, return 0 size. + * + * orig_video_isVGA is set to 1 during early Linux kernel + * initialization, and then will be set to a value, such as + * VIDEO_TYPE_VLFB or VIDEO_TYPE_EFI if an fbdev console is used. + */ + if (screen_info.orig_video_isVGA > 1) + { + NvU64 physAddr = screen_info.lfb_base; +#if defined(VIDEO_CAPABILITY_64BIT_BASE) + physAddr |= (NvU64)screen_info.ext_lfb_base << 32; +#endif + + /* Make sure base address is mapped to GPU BAR */ + if (NV_IS_CONSOLE_MAPPED(nv, physAddr)) + { + *pPhysicalAddress = physAddr; + *pFbWidth = screen_info.lfb_width; + *pFbHeight = screen_info.lfb_height; + *pFbDepth = screen_info.lfb_depth; + *pFbPitch = screen_info.lfb_linelength; + *pFbSize = (NvU64)(*pFbHeight) * (NvU64)(*pFbPitch); + } + } +#else + { + nv_linux_state_t *nvl = NV_GET_NVL_FROM_NV_STATE(nv); + struct pci_dev *pci_dev = nvl->pci_dev; + int i; + + if (pci_dev == NULL) + return; + + BUILD_BUG_ON(NV_GPU_BAR_INDEX_IMEM != NV_GPU_BAR_INDEX_FB + 1); + for (i = NV_GPU_BAR_INDEX_FB; i <= NV_GPU_BAR_INDEX_IMEM; i++) + { + int bar_index = nv_bar_index_to_os_bar_index(pci_dev, i); + struct resource *gpu_bar_res = &pci_dev->resource[bar_index]; + struct resource *res = gpu_bar_res->child; + + /* + * Console resource will become child resource of pci-dev resource. + * Check if child resource start address matches with expected + * console start address. + */ + if ((res != NULL) && + NV_IS_CONSOLE_MAPPED(nv, res->start)) + { + NvU32 res_name_len = strlen(res->name); + + /* + * The resource name ends with 'fb' (efifb, vesafb, etc.). + * For simple-framebuffer, the resource name is 'BOOTFB'. + * Confirm if the resources name either ends with 'fb' or 'FB'. + */ + if ((res_name_len > 2) && + !strcasecmp((res->name + res_name_len - 2), "fb")) + { + *pPhysicalAddress = res->start; + *pFbSize = resource_size(res); + return; + } + } + } + } +#endif +} diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/kernel-open/nvidia/nv_gpu_ops.h nvidia-open-gpu-kernel-modules-535.161.08/kernel-open/nvidia/nv_gpu_ops.h --- nvidia-open-gpu-kernel-modules-525.147.05/kernel-open/nvidia/nv_gpu_ops.h 2023-10-25 20:33:21.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/kernel-open/nvidia/nv_gpu_ops.h 2024-03-05 22:25:34.000000000 +0000 @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 2013-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2013-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -39,6 +39,7 @@ typedef struct gpuSession *gpuSessionHandle; typedef struct gpuDevice *gpuDeviceHandle; typedef struct gpuAddressSpace *gpuAddressSpaceHandle; +typedef struct gpuTsg *gpuTsgHandle; typedef struct gpuChannel *gpuChannelHandle; typedef struct gpuObject *gpuObjectHandle; @@ -76,28 +77,32 @@ NV_STATUS nvGpuOpsPmaAllocPages(void *pPma, NvLength pageCount, - NvU32 pageSize, + NvU64 pageSize, gpuPmaAllocationOptions *pPmaAllocOptions, NvU64 *pPages); void nvGpuOpsPmaFreePages(void *pPma, NvU64 *pPages, NvLength pageCount, - NvU32 pageSize, + NvU64 pageSize, NvU32 flags); NV_STATUS nvGpuOpsPmaPinPages(void *pPma, NvU64 *pPages, NvLength pageCount, - NvU32 pageSize, + NvU64 pageSize, NvU32 flags); NV_STATUS nvGpuOpsPmaUnpinPages(void *pPma, NvU64 *pPages, NvLength pageCount, - NvU32 pageSize); + NvU64 pageSize); -NV_STATUS nvGpuOpsChannelAllocate(gpuAddressSpaceHandle vaSpace, +NV_STATUS nvGpuOpsTsgAllocate(gpuAddressSpaceHandle vaSpace, + const gpuTsgAllocParams *params, + gpuTsgHandle *tsgHandle); + +NV_STATUS nvGpuOpsChannelAllocate(const gpuTsgHandle tsgHandle, const gpuChannelAllocParams *params, gpuChannelHandle *channelHandle, gpuChannelInfo *channelInfo); @@ -105,6 +110,8 @@ NV_STATUS nvGpuOpsMemoryReopen(struct gpuAddressSpace *vaSpace, NvHandle hSrcClient, NvHandle hSrcAllocation, NvLength length, NvU64 *gpuOffset); +void nvGpuOpsTsgDestroy(struct gpuTsg *tsg); + void nvGpuOpsChannelDestroy(struct gpuChannel *channel); void nvGpuOpsMemoryFree(gpuAddressSpaceHandle vaSpace, @@ -112,7 +119,7 @@ NV_STATUS nvGpuOpsMemoryCpuMap(gpuAddressSpaceHandle vaSpace, NvU64 memory, NvLength length, - void **cpuPtr, NvU32 pageSize); + void **cpuPtr, NvU64 pageSize); void nvGpuOpsMemoryCpuUnMap(gpuAddressSpaceHandle vaSpace, void* cpuPtr); @@ -196,7 +203,7 @@ void **pPma, const UvmPmaStatistics **pPmaPubStats); -NV_STATUS nvGpuOpsInitAccessCntrInfo(struct gpuDevice *device, gpuAccessCntrInfo *pAccessCntrInfo); +NV_STATUS nvGpuOpsInitAccessCntrInfo(struct gpuDevice *device, gpuAccessCntrInfo *pAccessCntrInfo, NvU32 accessCntrIndex); NV_STATUS nvGpuOpsDestroyAccessCntrInfo(struct gpuDevice *device, gpuAccessCntrInfo *pAccessCntrInfo); @@ -276,4 +283,44 @@ char *methodStream, NvU32 methodStreamSize); +NV_STATUS nvGpuOpsFlushReplayableFaultBuffer(struct gpuDevice *device); + +// Interface used for CCSL + +NV_STATUS nvGpuOpsCcslContextInit(struct ccslContext_t **ctx, + gpuChannelHandle channel); +NV_STATUS nvGpuOpsCcslContextClear(struct ccslContext_t *ctx); +NV_STATUS nvGpuOpsCcslRotateIv(struct ccslContext_t *ctx, + NvU8 direction); +NV_STATUS nvGpuOpsCcslEncrypt(struct ccslContext_t *ctx, + NvU32 bufferSize, + NvU8 const *inputBuffer, + NvU8 *outputBuffer, + NvU8 *authTagBuffer); +NV_STATUS nvGpuOpsCcslEncryptWithIv(struct ccslContext_t *ctx, + NvU32 bufferSize, + NvU8 const *inputBuffer, + NvU8 *encryptIv, + NvU8 *outputBuffer, + NvU8 *authTagBuffer); +NV_STATUS nvGpuOpsCcslDecrypt(struct ccslContext_t *ctx, + NvU32 bufferSize, + NvU8 const *inputBuffer, + NvU8 const *decryptIv, + NvU8 *outputBuffer, + NvU8 const *addAuthData, + NvU32 addAuthDataSize, + NvU8 const *authTagBuffer); +NV_STATUS nvGpuOpsCcslSign(struct ccslContext_t *ctx, + NvU32 bufferSize, + NvU8 const *inputBuffer, + NvU8 *authTagBuffer); +NV_STATUS nvGpuOpsQueryMessagePool(struct ccslContext_t *ctx, + NvU8 direction, + NvU64 *messageNum); +NV_STATUS nvGpuOpsIncrementIv(struct ccslContext_t *ctx, + NvU8 direction, + NvU64 increment, + NvU8 *iv); + #endif /* _NV_GPU_OPS_H_*/ diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/kernel-open/nvidia/nv_uvm_interface.c nvidia-open-gpu-kernel-modules-535.161.08/kernel-open/nvidia/nv_uvm_interface.c --- nvidia-open-gpu-kernel-modules-525.147.05/kernel-open/nvidia/nv_uvm_interface.c 2023-10-25 20:33:22.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/kernel-open/nvidia/nv_uvm_interface.c 2024-03-05 22:25:35.000000000 +0000 @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 2013-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2013-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -126,6 +126,19 @@ nv_kmem_cache_free_stack(sp); } +static NV_STATUS nvUvmDestroyFaultInfoAndStacks(nvidia_stack_t *sp, + uvmGpuDeviceHandle device, + UvmGpuFaultInfo *pFaultInfo) +{ + nv_kmem_cache_free_stack(pFaultInfo->replayable.cslCtx.nvidia_stack); + nv_kmem_cache_free_stack(pFaultInfo->nonReplayable.isr_bh_sp); + nv_kmem_cache_free_stack(pFaultInfo->nonReplayable.isr_sp); + + return rm_gpu_ops_destroy_fault_info(sp, + (gpuDeviceHandle)device, + pFaultInfo); +} + NV_STATUS nvUvmInterfaceRegisterGpu(const NvProcessorUuid *gpuUuid, UvmGpuPlatformInfo *gpuInfo) { nvidia_stack_t *sp = NULL; @@ -196,7 +209,7 @@ memset(platformInfo, 0, sizeof(*platformInfo)); platformInfo->atsSupported = nv_ats_supported; - platformInfo->sevEnabled = os_sev_enabled; + platformInfo->confComputingEnabled = os_cc_enabled; status = rm_gpu_ops_create_session(sp, (gpuSessionHandle *)session); @@ -435,7 +448,7 @@ NV_STATUS nvUvmInterfacePmaAllocPages(void *pPma, NvLength pageCount, - NvU32 pageSize, + NvU64 pageSize, UvmPmaAllocationOptions *pPmaAllocOptions, NvU64 *pPages) { @@ -462,7 +475,7 @@ NV_STATUS nvUvmInterfacePmaPinPages(void *pPma, NvU64 *pPages, NvLength pageCount, - NvU32 pageSize, + NvU64 pageSize, NvU32 flags) { nvidia_stack_t *sp = NULL; @@ -483,7 +496,7 @@ NV_STATUS nvUvmInterfacePmaUnpinPages(void *pPma, NvU64 *pPages, NvLength pageCount, - NvU32 pageSize) + NvU64 pageSize) { nvidia_stack_t *sp = NULL; NV_STATUS status; @@ -516,7 +529,7 @@ void nvUvmInterfacePmaFreePages(void *pPma, NvU64 *pPages, NvLength pageCount, - NvU32 pageSize, + NvU64 pageSize, NvU32 flags) { nvidia_stack_t *sp = nvUvmGetSafeStack(); @@ -529,7 +542,7 @@ NV_STATUS nvUvmInterfaceMemoryCpuMap(uvmGpuAddressSpaceHandle vaSpace, UvmGpuPointer gpuPointer, NvLength length, void **cpuPtr, - NvU32 pageSize) + NvU64 pageSize) { nvidia_stack_t *sp = NULL; NV_STATUS status; @@ -557,7 +570,39 @@ } EXPORT_SYMBOL(nvUvmInterfaceMemoryCpuUnMap); -NV_STATUS nvUvmInterfaceChannelAllocate(uvmGpuAddressSpaceHandle vaSpace, +NV_STATUS nvUvmInterfaceTsgAllocate(uvmGpuAddressSpaceHandle vaSpace, + const UvmGpuTsgAllocParams *allocParams, + uvmGpuTsgHandle *tsg) +{ + nvidia_stack_t *sp = NULL; + NV_STATUS status; + + if (nv_kmem_cache_alloc_stack(&sp) != 0) + { + return NV_ERR_NO_MEMORY; + } + + status = rm_gpu_ops_tsg_allocate(sp, + (gpuAddressSpaceHandle)vaSpace, + allocParams, + (gpuTsgHandle *)tsg); + + nv_kmem_cache_free_stack(sp); + + return status; +} +EXPORT_SYMBOL(nvUvmInterfaceTsgAllocate); + +void nvUvmInterfaceTsgDestroy(uvmGpuTsgHandle tsg) +{ + nvidia_stack_t *sp = nvUvmGetSafeStack(); + rm_gpu_ops_tsg_destroy(sp, (gpuTsgHandle)tsg); + nvUvmFreeSafeStack(sp); +} +EXPORT_SYMBOL(nvUvmInterfaceTsgDestroy); + + +NV_STATUS nvUvmInterfaceChannelAllocate(const uvmGpuTsgHandle tsg, const UvmGpuChannelAllocParams *allocParams, uvmGpuChannelHandle *channel, UvmGpuChannelInfo *channelInfo) @@ -571,7 +616,7 @@ } status = rm_gpu_ops_channel_allocate(sp, - (gpuAddressSpaceHandle)vaSpace, + (gpuTsgHandle)tsg, allocParams, (gpuChannelHandle *)channel, channelInfo); @@ -823,6 +868,7 @@ { nvidia_stack_t *sp = NULL; NV_STATUS status; + int err; if (nv_kmem_cache_alloc_stack(&sp) != 0) { @@ -832,43 +878,56 @@ status = rm_gpu_ops_init_fault_info(sp, (gpuDeviceHandle)device, pFaultInfo); + if (status != NV_OK) + { + goto done; + } // Preallocate a stack for functions called from ISR top half pFaultInfo->nonReplayable.isr_sp = NULL; pFaultInfo->nonReplayable.isr_bh_sp = NULL; - if (status == NV_OK) + pFaultInfo->replayable.cslCtx.nvidia_stack = NULL; + + // NOTE: nv_kmem_cache_alloc_stack does not allocate a stack on PPC. + // Therefore, the pointer can be NULL on success. Always use the + // returned error code to determine if the operation was successful. + err = nv_kmem_cache_alloc_stack((nvidia_stack_t **)&pFaultInfo->nonReplayable.isr_sp); + if (err) { - // NOTE: nv_kmem_cache_alloc_stack does not allocate a stack on PPC. - // Therefore, the pointer can be NULL on success. Always use the - // returned error code to determine if the operation was successful. - int err = nv_kmem_cache_alloc_stack((nvidia_stack_t **)&pFaultInfo->nonReplayable.isr_sp); - if (!err) - { - err = nv_kmem_cache_alloc_stack((nvidia_stack_t **)&pFaultInfo->nonReplayable.isr_bh_sp); - if (err) - { - nv_kmem_cache_free_stack(pFaultInfo->nonReplayable.isr_sp); - pFaultInfo->nonReplayable.isr_sp = NULL; - } - } + goto error; + } + + err = nv_kmem_cache_alloc_stack((nvidia_stack_t **)&pFaultInfo->nonReplayable.isr_bh_sp); + if (err) + { + goto error; + } + // The cslCtx.ctx pointer is not NULL only when ConfidentialComputing is enabled. + if (pFaultInfo->replayable.cslCtx.ctx != NULL) + { + err = nv_kmem_cache_alloc_stack((nvidia_stack_t **)&pFaultInfo->replayable.cslCtx.nvidia_stack); if (err) { - rm_gpu_ops_destroy_fault_info(sp, - (gpuDeviceHandle)device, - pFaultInfo); - - status = NV_ERR_NO_MEMORY; + goto error; } } + goto done; +error: + nvUvmDestroyFaultInfoAndStacks(sp, + device, + pFaultInfo); + status = NV_ERR_NO_MEMORY; +done: nv_kmem_cache_free_stack(sp); return status; } EXPORT_SYMBOL(nvUvmInterfaceInitFaultInfo); NV_STATUS nvUvmInterfaceInitAccessCntrInfo(uvmGpuDeviceHandle device, - UvmGpuAccessCntrInfo *pAccessCntrInfo) + UvmGpuAccessCntrInfo *pAccessCntrInfo, + NvU32 accessCntrIndex) { nvidia_stack_t *sp = NULL; NV_STATUS status; @@ -880,7 +939,8 @@ status = rm_gpu_ops_init_access_cntr_info(sp, (gpuDeviceHandle)device, - pAccessCntrInfo); + pAccessCntrInfo, + accessCntrIndex); nv_kmem_cache_free_stack(sp); return status; @@ -915,23 +975,9 @@ nvidia_stack_t *sp = nvUvmGetSafeStack(); NV_STATUS status; - // Free the preallocated stack for functions called from ISR - if (pFaultInfo->nonReplayable.isr_sp != NULL) - { - nv_kmem_cache_free_stack((nvidia_stack_t *)pFaultInfo->nonReplayable.isr_sp); - pFaultInfo->nonReplayable.isr_sp = NULL; - } - - if (pFaultInfo->nonReplayable.isr_bh_sp != NULL) - { - nv_kmem_cache_free_stack((nvidia_stack_t *)pFaultInfo->nonReplayable.isr_bh_sp); - pFaultInfo->nonReplayable.isr_bh_sp = NULL; - } - - status = rm_gpu_ops_destroy_fault_info(sp, - (gpuDeviceHandle)device, - pFaultInfo); - + status = nvUvmDestroyFaultInfoAndStacks(sp, + device, + pFaultInfo); nvUvmFreeSafeStack(sp); return status; } @@ -957,6 +1003,18 @@ } EXPORT_SYMBOL(nvUvmInterfaceGetNonReplayableFaults); +NV_STATUS nvUvmInterfaceFlushReplayableFaultBuffer(uvmGpuDeviceHandle device) +{ + nvidia_stack_t *sp = nvUvmGetSafeStack(); + NV_STATUS status; + + status = rm_gpu_ops_flush_replayable_fault_buffer(sp, (gpuDeviceHandle)device); + + nvUvmFreeSafeStack(sp); + return status; +} +EXPORT_SYMBOL(nvUvmInterfaceFlushReplayableFaultBuffer); + NV_STATUS nvUvmInterfaceDestroyAccessCntrInfo(uvmGpuDeviceHandle device, UvmGpuAccessCntrInfo *pAccessCntrInfo) { @@ -1420,6 +1478,142 @@ } EXPORT_SYMBOL(nvUvmInterfacePagingChannelPushStream); +NV_STATUS nvUvmInterfaceCslInitContext(UvmCslContext *uvmCslContext, + uvmGpuChannelHandle channel) +{ + nvidia_stack_t *sp = NULL; + NV_STATUS status; + + if (nv_kmem_cache_alloc_stack(&sp) != 0) + { + return NV_ERR_NO_MEMORY; + } + + status = rm_gpu_ops_ccsl_context_init(sp, &uvmCslContext->ctx, (gpuChannelHandle)channel); + + // Saving the stack in the context allows UVM to safely use the CSL layer + // in interrupt context without making new allocations. UVM serializes CSL + // API usage for a given context so the stack pointer does not need + // additional protection. + if (status != NV_OK) + { + nv_kmem_cache_free_stack(sp); + } + else + { + uvmCslContext->nvidia_stack = sp; + } + + return status; +} +EXPORT_SYMBOL(nvUvmInterfaceCslInitContext); + +void nvUvmInterfaceDeinitCslContext(UvmCslContext *uvmCslContext) +{ + nvidia_stack_t *sp = uvmCslContext->nvidia_stack; + rm_gpu_ops_ccsl_context_clear(sp, uvmCslContext->ctx); + nvUvmFreeSafeStack(sp); +} +EXPORT_SYMBOL(nvUvmInterfaceDeinitCslContext); + +NV_STATUS nvUvmInterfaceCslRotateIv(UvmCslContext *uvmCslContext, + UvmCslOperation operation) +{ + NV_STATUS status; + nvidia_stack_t *sp = uvmCslContext->nvidia_stack; + + status = rm_gpu_ops_ccsl_rotate_iv(sp, uvmCslContext->ctx, operation); + + return status; +} +EXPORT_SYMBOL(nvUvmInterfaceCslRotateIv); + +NV_STATUS nvUvmInterfaceCslEncrypt(UvmCslContext *uvmCslContext, + NvU32 bufferSize, + NvU8 const *inputBuffer, + UvmCslIv *encryptIv, + NvU8 *outputBuffer, + NvU8 *authTagBuffer) +{ + NV_STATUS status; + nvidia_stack_t *sp = uvmCslContext->nvidia_stack; + + if (encryptIv != NULL) + status = rm_gpu_ops_ccsl_encrypt_with_iv(sp, uvmCslContext->ctx, bufferSize, inputBuffer, (NvU8*)encryptIv, outputBuffer, authTagBuffer); + else + status = rm_gpu_ops_ccsl_encrypt(sp, uvmCslContext->ctx, bufferSize, inputBuffer, outputBuffer, authTagBuffer); + + return status; +} +EXPORT_SYMBOL(nvUvmInterfaceCslEncrypt); + +NV_STATUS nvUvmInterfaceCslDecrypt(UvmCslContext *uvmCslContext, + NvU32 bufferSize, + NvU8 const *inputBuffer, + UvmCslIv const *decryptIv, + NvU8 *outputBuffer, + NvU8 const *addAuthData, + NvU32 addAuthDataSize, + NvU8 const *authTagBuffer) +{ + NV_STATUS status; + nvidia_stack_t *sp = uvmCslContext->nvidia_stack; + + status = rm_gpu_ops_ccsl_decrypt(sp, + uvmCslContext->ctx, + bufferSize, + inputBuffer, + (NvU8 *)decryptIv, + outputBuffer, + addAuthData, + addAuthDataSize, + authTagBuffer); + + return status; +} +EXPORT_SYMBOL(nvUvmInterfaceCslDecrypt); + +NV_STATUS nvUvmInterfaceCslSign(UvmCslContext *uvmCslContext, + NvU32 bufferSize, + NvU8 const *inputBuffer, + NvU8 *authTagBuffer) +{ + NV_STATUS status; + nvidia_stack_t *sp = uvmCslContext->nvidia_stack; + + status = rm_gpu_ops_ccsl_sign(sp, uvmCslContext->ctx, bufferSize, inputBuffer, authTagBuffer); + + return status; +} +EXPORT_SYMBOL(nvUvmInterfaceCslSign); + +NV_STATUS nvUvmInterfaceCslQueryMessagePool(UvmCslContext *uvmCslContext, + UvmCslOperation operation, + NvU64 *messageNum) +{ + NV_STATUS status; + nvidia_stack_t *sp = uvmCslContext->nvidia_stack; + + status = rm_gpu_ops_ccsl_query_message_pool(sp, uvmCslContext->ctx, operation, messageNum); + + return status; +} +EXPORT_SYMBOL(nvUvmInterfaceCslQueryMessagePool); + +NV_STATUS nvUvmInterfaceCslIncrementIv(UvmCslContext *uvmCslContext, + UvmCslOperation operation, + NvU64 increment, + UvmCslIv *iv) +{ + NV_STATUS status; + nvidia_stack_t *sp = uvmCslContext->nvidia_stack; + + status = rm_gpu_ops_ccsl_increment_iv(sp, uvmCslContext->ctx, operation, increment, (NvU8 *)iv); + + return status; +} +EXPORT_SYMBOL(nvUvmInterfaceCslIncrementIv); + #else // NV_UVM_ENABLE NV_STATUS nv_uvm_suspend(void) diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/kernel-open/nvidia/nvidia-sources.Kbuild nvidia-open-gpu-kernel-modules-535.161.08/kernel-open/nvidia/nvidia-sources.Kbuild --- nvidia-open-gpu-kernel-modules-525.147.05/kernel-open/nvidia/nvidia-sources.Kbuild 2023-10-25 21:08:29.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/kernel-open/nvidia/nvidia-sources.Kbuild 2024-03-05 23:13:30.000000000 +0000 @@ -32,6 +32,17 @@ NVIDIA_SOURCES += nvidia/nv-caps.c NVIDIA_SOURCES += nvidia/nv-frontend.c NVIDIA_SOURCES += nvidia/nv_uvm_interface.c +NVIDIA_SOURCES += nvidia/libspdm_aead.c +NVIDIA_SOURCES += nvidia/libspdm_ecc.c +NVIDIA_SOURCES += nvidia/libspdm_hkdf.c +NVIDIA_SOURCES += nvidia/libspdm_rand.c +NVIDIA_SOURCES += nvidia/libspdm_shash.c +NVIDIA_SOURCES += nvidia/libspdm_aead_aes_gcm.c +NVIDIA_SOURCES += nvidia/libspdm_sha.c +NVIDIA_SOURCES += nvidia/libspdm_hmac_sha.c +NVIDIA_SOURCES += nvidia/libspdm_hkdf_sha.c +NVIDIA_SOURCES += nvidia/libspdm_ec.c +NVIDIA_SOURCES += nvidia/libspdm_x509.c NVIDIA_SOURCES += nvidia/nvlink_linux.c NVIDIA_SOURCES += nvidia/nvlink_caps.c NVIDIA_SOURCES += nvidia/linux_nvswitch.c diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/kernel-open/nvidia/nvidia.Kbuild nvidia-open-gpu-kernel-modules-535.161.08/kernel-open/nvidia/nvidia.Kbuild --- nvidia-open-gpu-kernel-modules-525.147.05/kernel-open/nvidia/nvidia.Kbuild 2023-10-25 20:33:18.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/kernel-open/nvidia/nvidia.Kbuild 2024-03-05 22:25:31.000000000 +0000 @@ -120,6 +120,9 @@ NV_CONFTEST_FUNCTION_COMPILE_TESTS += set_pages_array_uc NV_CONFTEST_FUNCTION_COMPILE_TESTS += ioremap_cache NV_CONFTEST_FUNCTION_COMPILE_TESTS += ioremap_wc +NV_CONFTEST_FUNCTION_COMPILE_TESTS += ioremap_driver_hardened +NV_CONFTEST_FUNCTION_COMPILE_TESTS += ioremap_driver_hardened_wc +NV_CONFTEST_FUNCTION_COMPILE_TESTS += ioremap_cache_shared NV_CONFTEST_FUNCTION_COMPILE_TESTS += pci_get_domain_bus_and_slot NV_CONFTEST_FUNCTION_COMPILE_TESTS += get_num_physpages NV_CONFTEST_FUNCTION_COMPILE_TESTS += pde_data @@ -135,6 +138,8 @@ NV_CONFTEST_FUNCTION_COMPILE_TESTS += of_get_ibm_chip_id NV_CONFTEST_FUNCTION_COMPILE_TESTS += pci_bus_address NV_CONFTEST_FUNCTION_COMPILE_TESTS += pci_stop_and_remove_bus_device +NV_CONFTEST_FUNCTION_COMPILE_TESTS += pci_rebar_get_possible_sizes +NV_CONFTEST_FUNCTION_COMPILE_TESTS += wait_for_random_bytes NV_CONFTEST_FUNCTION_COMPILE_TESTS += register_cpu_notifier NV_CONFTEST_FUNCTION_COMPILE_TESTS += cpuhp_setup_state NV_CONFTEST_FUNCTION_COMPILE_TESTS += dma_map_resource @@ -154,8 +159,7 @@ NV_CONFTEST_FUNCTION_COMPILE_TESTS += full_name_hash NV_CONFTEST_FUNCTION_COMPILE_TESTS += pci_enable_atomic_ops_to_root NV_CONFTEST_FUNCTION_COMPILE_TESTS += vga_tryget -NV_CONFTEST_FUNCTION_COMPILE_TESTS += pgprot_decrypted -NV_CONFTEST_FUNCTION_COMPILE_TESTS += cc_mkdec +NV_CONFTEST_FUNCTION_COMPILE_TESTS += cc_platform_has NV_CONFTEST_FUNCTION_COMPILE_TESTS += seq_read_iter NV_CONFTEST_FUNCTION_COMPILE_TESTS += unsafe_follow_pfn NV_CONFTEST_FUNCTION_COMPILE_TESTS += drm_gem_object_get @@ -166,6 +170,7 @@ NV_CONFTEST_FUNCTION_COMPILE_TESTS += of_dma_configure NV_CONFTEST_FUNCTION_COMPILE_TESTS += of_property_count_elems_of_size NV_CONFTEST_FUNCTION_COMPILE_TESTS += of_property_read_variable_u8_array +NV_CONFTEST_FUNCTION_COMPILE_TESTS += of_property_read_variable_u32_array NV_CONFTEST_FUNCTION_COMPILE_TESTS += i2c_new_client_device NV_CONFTEST_FUNCTION_COMPILE_TESTS += i2c_unregister_device NV_CONFTEST_FUNCTION_COMPILE_TESTS += of_get_named_gpio @@ -189,6 +194,8 @@ NV_CONFTEST_FUNCTION_COMPILE_TESTS += devm_clk_bulk_get_all NV_CONFTEST_FUNCTION_COMPILE_TESTS += get_task_ioprio NV_CONFTEST_FUNCTION_COMPILE_TESTS += mdev_set_iommu_device +NV_CONFTEST_FUNCTION_COMPILE_TESTS += offline_and_remove_memory +NV_CONFTEST_FUNCTION_COMPILE_TESTS += crypto_tfm_ctx_aligned NV_CONFTEST_SYMBOL_COMPILE_TESTS += is_export_symbol_gpl_of_node_to_nid NV_CONFTEST_SYMBOL_COMPILE_TESTS += is_export_symbol_gpl_sme_active @@ -209,6 +216,18 @@ NV_CONFTEST_SYMBOL_COMPILE_TESTS += is_export_symbol_present_tegra_dram_types NV_CONFTEST_SYMBOL_COMPILE_TESTS += is_export_symbol_present_pxm_to_node NV_CONFTEST_SYMBOL_COMPILE_TESTS += is_export_symbol_present_screen_info +NV_CONFTEST_SYMBOL_COMPILE_TESTS += is_export_symbol_gpl_screen_info +NV_CONFTEST_SYMBOL_COMPILE_TESTS += is_export_symbol_present_i2c_bus_status +NV_CONFTEST_SYMBOL_COMPILE_TESTS += is_export_symbol_present_tegra_fuse_control_read +NV_CONFTEST_SYMBOL_COMPILE_TESTS += is_export_symbol_present_tegra_get_platform +NV_CONFTEST_SYMBOL_COMPILE_TESTS += is_export_symbol_present_pci_find_host_bridge +NV_CONFTEST_SYMBOL_COMPILE_TESTS += is_export_symbol_present_tsec_comms_send_cmd +NV_CONFTEST_SYMBOL_COMPILE_TESTS += is_export_symbol_present_tsec_comms_set_init_cb +NV_CONFTEST_SYMBOL_COMPILE_TESTS += is_export_symbol_present_tsec_comms_clear_init_cb +NV_CONFTEST_SYMBOL_COMPILE_TESTS += is_export_symbol_present_tsec_comms_alloc_mem_from_gscco +NV_CONFTEST_SYMBOL_COMPILE_TESTS += is_export_symbol_present_tsec_comms_free_gscco_mem +NV_CONFTEST_SYMBOL_COMPILE_TESTS += is_export_symbol_present_memory_block_size_bytes +NV_CONFTEST_SYMBOL_COMPILE_TESTS += crypto NV_CONFTEST_TYPE_COMPILE_TESTS += dma_ops NV_CONFTEST_TYPE_COMPILE_TESTS += swiotlb_dma_ops @@ -217,7 +236,6 @@ NV_CONFTEST_TYPE_COMPILE_TESTS += vm_insert_pfn_prot NV_CONFTEST_TYPE_COMPILE_TESTS += vmf_insert_pfn_prot NV_CONFTEST_TYPE_COMPILE_TESTS += vm_ops_fault_removed_vma_arg -NV_CONFTEST_TYPE_COMPILE_TESTS += vmbus_channel_has_ringbuffer_page NV_CONFTEST_TYPE_COMPILE_TESTS += kmem_cache_has_kobj_remove_work NV_CONFTEST_TYPE_COMPILE_TESTS += sysfs_slab_unlink NV_CONFTEST_TYPE_COMPILE_TESTS += proc_ops @@ -231,6 +249,7 @@ NV_CONFTEST_TYPE_COMPILE_TESTS += num_registered_fb NV_CONFTEST_TYPE_COMPILE_TESTS += pci_driver_has_driver_managed_dma NV_CONFTEST_TYPE_COMPILE_TESTS += vm_area_struct_has_const_vm_flags +NV_CONFTEST_TYPE_COMPILE_TESTS += memory_failure_has_trapno_arg NV_CONFTEST_GENERIC_COMPILE_TESTS += dom0_kernel_present NV_CONFTEST_GENERIC_COMPILE_TESTS += nvidia_vgpu_kvm_build @@ -245,3 +264,7 @@ NV_CONFTEST_GENERIC_COMPILE_TESTS += pci_class_multimedia_hd_audio NV_CONFTEST_GENERIC_COMPILE_TESTS += drm_available NV_CONFTEST_GENERIC_COMPILE_TESTS += vfio_pci_core_available +NV_CONFTEST_GENERIC_COMPILE_TESTS += mdev_available +NV_CONFTEST_GENERIC_COMPILE_TESTS += cmd_uphy_display_port_init +NV_CONFTEST_GENERIC_COMPILE_TESTS += cmd_uphy_display_port_off +NV_CONFTEST_GENERIC_COMPILE_TESTS += memory_failure_mf_sw_simulated_defined diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/kernel-open/nvidia/nvlink_os.h nvidia-open-gpu-kernel-modules-535.161.08/kernel-open/nvidia/nvlink_os.h --- nvidia-open-gpu-kernel-modules-525.147.05/kernel-open/nvidia/nvlink_os.h 2023-10-25 20:33:25.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/kernel-open/nvidia/nvlink_os.h 2024-03-05 22:25:39.000000000 +0000 @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 2019 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2019-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/kernel-open/nvidia/nvspdm_cryptlib_extensions.h nvidia-open-gpu-kernel-modules-535.161.08/kernel-open/nvidia/nvspdm_cryptlib_extensions.h --- nvidia-open-gpu-kernel-modules-525.147.05/kernel-open/nvidia/nvspdm_cryptlib_extensions.h 1970-01-01 00:00:00.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/kernel-open/nvidia/nvspdm_cryptlib_extensions.h 2024-03-05 22:25:37.000000000 +0000 @@ -0,0 +1,41 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + + +bool libspdm_aead_gcm_prealloc(void **context); +void libspdm_aead_free(void *context); +bool libspdm_aead_aes_gcm_encrypt_prealloc(void *context, + const uint8_t *key, size_t key_size, + const uint8_t *iv, size_t iv_size, + const uint8_t *a_data, size_t a_data_size, + const uint8_t *data_in, size_t data_in_size, + uint8_t *tag_out, size_t tag_size, + uint8_t *data_out, size_t *data_out_size); +bool libspdm_aead_aes_gcm_decrypt_prealloc(void *context, + const uint8_t *key, size_t key_size, + const uint8_t *iv, size_t iv_size, + const uint8_t *a_data, size_t a_data_size, + const uint8_t *data_in, size_t data_in_size, + const uint8_t *tag, size_t tag_size, + uint8_t *data_out, size_t *data_out_size); + diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/kernel-open/nvidia/os-interface.c nvidia-open-gpu-kernel-modules-535.161.08/kernel-open/nvidia/os-interface.c --- nvidia-open-gpu-kernel-modules-525.147.05/kernel-open/nvidia/os-interface.c 2023-10-25 20:33:19.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/kernel-open/nvidia/os-interface.c 2024-03-05 22:25:32.000000000 +0000 @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 1999-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 1999-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -28,6 +28,11 @@ #include "nv-time.h" +#include +#include + +#include + extern char *NVreg_TemporaryFilePath; #define MAX_ERROR_STRING 512 @@ -41,8 +46,8 @@ NvU32 os_page_size = PAGE_SIZE; NvU64 os_page_mask = NV_PAGE_MASK; NvU8 os_page_shift = PAGE_SHIFT; -NvU32 os_sev_status = 0; -NvBool os_sev_enabled = 0; +NvBool os_cc_enabled = 0; +NvBool os_cc_tdx_enabled = 0; #if defined(CONFIG_DMA_SHARED_BUFFER) NvBool os_dma_buf_enabled = NV_TRUE; @@ -173,7 +178,7 @@ return NULL; } - NV_INIT_SEMA(os_sema, initialValue); + sema_init(os_sema, initialValue); return (void *)os_sema; } @@ -1192,87 +1197,6 @@ return efi_enabled(EFI_BOOT); } -void NV_API_CALL os_get_screen_info( - NvU64 *pPhysicalAddress, - NvU16 *pFbWidth, - NvU16 *pFbHeight, - NvU16 *pFbDepth, - NvU16 *pFbPitch, - NvU64 consoleBar1Address, - NvU64 consoleBar2Address -) -{ - *pPhysicalAddress = 0; - *pFbWidth = *pFbHeight = *pFbDepth = *pFbPitch = 0; - -#if defined(CONFIG_FB) && defined(NV_NUM_REGISTERED_FB_PRESENT) - if (num_registered_fb > 0) - { - int i; - - for (i = 0; i < num_registered_fb; i++) - { - if (!registered_fb[i]) - continue; - - /* Make sure base address is mapped to GPU BAR */ - if ((registered_fb[i]->fix.smem_start == consoleBar1Address) || - (registered_fb[i]->fix.smem_start == consoleBar2Address)) - { - *pPhysicalAddress = registered_fb[i]->fix.smem_start; - *pFbWidth = registered_fb[i]->var.xres; - *pFbHeight = registered_fb[i]->var.yres; - *pFbDepth = registered_fb[i]->var.bits_per_pixel; - *pFbPitch = registered_fb[i]->fix.line_length; - return; - } - } - } -#endif - - /* - * If the screen info is not found in the registered FBs then fallback - * to the screen_info structure. - * - * The SYSFB_SIMPLEFB option, if enabled, marks VGA/VBE/EFI framebuffers as - * generic framebuffers so the new generic system-framebuffer drivers can - * be used instead. DRM_SIMPLEDRM drives the generic system-framebuffers - * device created by SYSFB_SIMPLEFB. - * - * SYSFB_SIMPLEFB registers a dummy framebuffer which does not contain the - * information required by os_get_screen_info(), therefore you need to - * fall back onto the screen_info structure. - */ - -#if NV_IS_EXPORT_SYMBOL_PRESENT_screen_info - /* - * If there is not a framebuffer console, return 0 size. - * - * orig_video_isVGA is set to 1 during early Linux kernel - * initialization, and then will be set to a value, such as - * VIDEO_TYPE_VLFB or VIDEO_TYPE_EFI if an fbdev console is used. - */ - if (screen_info.orig_video_isVGA > 1) - { - NvU64 physAddr = screen_info.lfb_base; -#if defined(VIDEO_CAPABILITY_64BIT_BASE) - physAddr |= (NvU64)screen_info.ext_lfb_base << 32; -#endif - - /* Make sure base address is mapped to GPU BAR */ - if ((physAddr == consoleBar1Address) || - (physAddr == consoleBar2Address)) - { - *pPhysicalAddress = physAddr; - *pFbWidth = screen_info.lfb_width; - *pFbHeight = screen_info.lfb_height; - *pFbDepth = screen_info.lfb_depth; - *pFbPitch = screen_info.lfb_linelength; - } - } -#endif -} - void NV_API_CALL os_dump_stack(void) { dump_stack(); @@ -1422,8 +1346,7 @@ return NV_OK; } -// These functions are needed only on x86_64 platforms. -#if defined(NVCPU_X86_64) +#if defined(NVCPU_X86_64) || defined(NVCPU_AARCH64) static NvBool os_verify_checksum(const NvU8 *pMappedAddr, NvU32 length) { @@ -1461,6 +1384,9 @@ static NV_STATUS os_get_smbios_header_legacy(NvU64 *pSmbsAddr) { +#if !defined(NVCPU_X86_64) + return NV_ERR_NOT_SUPPORTED; +#else NV_STATUS status = NV_ERR_OPERATING_SYSTEM; NvU8 *pMappedAddr = NULL; NvU8 *pIterAddr = NULL; @@ -1495,6 +1421,7 @@ os_unmap_kernel_space(pMappedAddr, SMBIOS_LEGACY_SIZE); return status; +#endif } // This function is needed only if "efi" is enabled. @@ -1571,13 +1498,13 @@ return status; } -#endif // defined(NVCPU_X86_64) +#endif // defined(NVCPU_X86_64) || defined(NVCPU_AARCH64) // The function locates the SMBIOS entry point. NV_STATUS NV_API_CALL os_get_smbios_header(NvU64 *pSmbsAddr) { -#if !defined(NVCPU_X86_64) +#if !defined(NVCPU_X86_64) && !defined(NVCPU_AARCH64) return NV_ERR_NOT_SUPPORTED; #else NV_STATUS status = NV_OK; @@ -1784,17 +1711,16 @@ NvU64 *memblock_size ) { +#if NV_IS_EXPORT_SYMBOL_PRESENT_memory_block_size_bytes + *memblock_size = memory_block_size_bytes(); + return NV_OK; +#endif if (nv_ctl_device.numa_memblock_size == 0) return NV_ERR_INVALID_STATE; *memblock_size = nv_ctl_device.numa_memblock_size; return NV_OK; } -NV_STATUS NV_API_CALL os_call_nv_vmbus(NvU32 vmbus_cmd, void *input) -{ - return NV_ERR_NOT_SUPPORTED; -} - NV_STATUS NV_API_CALL os_open_temporary_file ( void **ppFile @@ -2003,13 +1929,22 @@ return !!pci_dev_present(nvswitch_pci_table); } -void NV_API_CALL os_get_random_bytes +/* + * This function may sleep (interruptible). + */ +NV_STATUS NV_API_CALL os_get_random_bytes ( NvU8 *bytes, NvU16 numBytes ) { +#if defined NV_WAIT_FOR_RANDOM_BYTES_PRESENT + if (wait_for_random_bytes() < 0) + return NV_ERR_NOT_READY; +#endif + get_random_bytes(bytes, numBytes); + return NV_OK; } NV_STATUS NV_API_CALL os_alloc_wait_queue @@ -2111,3 +2046,316 @@ nv_cap_close_fd(fd); } +/* + * Reads the total memory and free memory of a NUMA node from the kernel. + */ +NV_STATUS NV_API_CALL os_get_numa_node_memory_usage +( + NvS32 node_id, + NvU64 *free_memory_bytes, + NvU64 *total_memory_bytes +) +{ + struct pglist_data *pgdat; + struct zone *zone; + NvU32 zone_id; + + if (node_id >= MAX_NUMNODES) + { + nv_printf(NV_DBG_ERRORS, "Invalid NUMA node ID\n"); + return NV_ERR_INVALID_ARGUMENT; + } + + pgdat = NODE_DATA(node_id); + + *free_memory_bytes = 0; + *total_memory_bytes = 0; + + for (zone_id = 0; zone_id < MAX_NR_ZONES; zone_id++) + { + zone = &(pgdat->node_zones[zone_id]); + if (!populated_zone(zone)) + continue; + *free_memory_bytes += (zone_page_state_snapshot(zone, NR_FREE_PAGES) * PAGE_SIZE); + *total_memory_bytes += (zone->present_pages * PAGE_SIZE); + } + + return NV_OK; +} + +typedef struct os_numa_gpu_mem_hotplug_notifier_s +{ + NvU64 start_pa; + NvU64 size; + nv_pci_info_t pci_info; + struct notifier_block memory_notifier; +} os_numa_gpu_mem_hotplug_notifier_t; + +static int os_numa_verify_gpu_memory_zone(struct notifier_block *nb, + unsigned long action, void *data) +{ + os_numa_gpu_mem_hotplug_notifier_t *notifier = container_of(nb, + os_numa_gpu_mem_hotplug_notifier_t, + memory_notifier); + struct memory_notify *mhp = data; + NvU64 start_pa = PFN_PHYS(mhp->start_pfn); + NvU64 size = PFN_PHYS(mhp->nr_pages); + + if (action == MEM_GOING_ONLINE) + { + // Check if onlining memory falls in the GPU memory range + if ((start_pa >= notifier->start_pa) && + (start_pa + size) <= (notifier->start_pa + notifier->size)) + { + /* + * Verify GPU memory NUMA node has memory only in ZONE_MOVABLE before + * onlining the memory so that incorrect auto online setting doesn't + * cause the memory onlined in a zone where kernel allocations + * could happen, resulting in GPU memory hot unpluggable and requiring + * system reboot. + */ + if (page_zonenum((pfn_to_page(mhp->start_pfn))) != ZONE_MOVABLE) + { + nv_printf(NV_DBG_ERRORS, "NVRM: Failing GPU memory onlining as the onlining zone " + "is not movable. pa: 0x%llx size: 0x%llx\n" + "NVRM: The NVIDIA GPU %04x:%02x:%02x.%x installed in the system\n" + "NVRM: requires auto onlining mode online_movable enabled in\n" + "NVRM: /sys/devices/system/memory/auto_online_blocks\n", + start_pa, size, notifier->pci_info.domain, notifier->pci_info.bus, + notifier->pci_info.slot, notifier->pci_info.function); + return NOTIFY_BAD; + } + } + } + return NOTIFY_OK; +} + +NV_STATUS NV_API_CALL os_numa_add_gpu_memory +( + void *handle, + NvU64 offset, + NvU64 size, + NvU32 *nodeId +) +{ +#if defined(NV_ADD_MEMORY_DRIVER_MANAGED_PRESENT) + int node = 0; + nv_linux_state_t *nvl = pci_get_drvdata(handle); + nv_state_t *nv = NV_STATE_PTR(nvl); + NvU64 base = offset + nvl->coherent_link_info.gpu_mem_pa; + int ret; + os_numa_gpu_mem_hotplug_notifier_t notifier = + { + .start_pa = base, + .size = size, + .pci_info = nv->pci_info, + .memory_notifier.notifier_call = os_numa_verify_gpu_memory_zone, + }; + + if (nodeId == NULL) + { + return NV_ERR_INVALID_ARGUMENT; + } + + if (bitmap_empty(nvl->coherent_link_info.free_node_bitmap, MAX_NUMNODES)) + { + return NV_ERR_IN_USE; + } + node = find_first_bit(nvl->coherent_link_info.free_node_bitmap, MAX_NUMNODES); + if (node == MAX_NUMNODES) + { + return NV_ERR_INVALID_STATE; + } + + NV_ATOMIC_SET(nvl->numa_info.status, NV_IOCTL_NUMA_STATUS_ONLINE_IN_PROGRESS); + + ret = register_memory_notifier(¬ifier.memory_notifier); + if (ret) + { + nv_printf(NV_DBG_ERRORS, "NVRM: Memory hotplug notifier registration failed\n"); + goto failed; + } + +#ifdef NV_ADD_MEMORY_DRIVER_MANAGED_HAS_MHP_FLAGS_ARG + ret = add_memory_driver_managed(node, base, size, "System RAM (NVIDIA)", MHP_NONE); +#else + ret = add_memory_driver_managed(node, base, size, "System RAM (NVIDIA)"); +#endif + unregister_memory_notifier(¬ifier.memory_notifier); + + if (ret == 0) + { + struct zone *zone = &NODE_DATA(node)->node_zones[ZONE_MOVABLE]; + NvU64 start_pfn = base >> PAGE_SHIFT; + NvU64 end_pfn = (base + size) >> PAGE_SHIFT; + + /* Verify the full GPU memory range passed on is onlined */ + if (zone->zone_start_pfn != start_pfn || + zone_end_pfn(zone) != end_pfn) + { + nv_printf(NV_DBG_ERRORS, "NVRM: GPU memory zone movable auto onlining failed!\n"); +#ifdef NV_OFFLINE_AND_REMOVE_MEMORY_PRESENT +#ifdef NV_REMOVE_MEMORY_HAS_NID_ARG + if (offline_and_remove_memory(node, base, size) != 0) +#else + if (offline_and_remove_memory(base, size) != 0) +#endif + { + nv_printf(NV_DBG_ERRORS, "NVRM: offline_and_remove_memory failed\n"); + } +#endif + goto failed; + } + + *nodeId = node; + clear_bit(node, nvl->coherent_link_info.free_node_bitmap); + NV_ATOMIC_SET(nvl->numa_info.status, NV_IOCTL_NUMA_STATUS_ONLINE); + return NV_OK; + } + nv_printf(NV_DBG_ERRORS, "NVRM: Memory add failed. base: 0x%lx size: 0x%lx ret: %d\n", + base, size, ret); +failed: + NV_ATOMIC_SET(nvl->numa_info.status, NV_IOCTL_NUMA_STATUS_ONLINE_FAILED); + return NV_ERR_OPERATING_SYSTEM; +#endif + return NV_ERR_NOT_SUPPORTED; +} + +NV_STATUS NV_API_CALL os_numa_remove_gpu_memory +( + void *handle, + NvU64 offset, + NvU64 size, + NvU32 nodeId +) +{ +#ifdef NV_ADD_MEMORY_DRIVER_MANAGED_PRESENT + nv_linux_state_t *nvl = pci_get_drvdata(handle); +#ifdef NV_OFFLINE_AND_REMOVE_MEMORY_PRESENT + NvU64 base = offset + nvl->coherent_link_info.gpu_mem_pa; + remove_numa_memory_info_t numa_info; + nv_kthread_q_item_t remove_numa_memory_q_item; + int ret; +#endif + + if (nodeId >= MAX_NUMNODES) + { + return NV_ERR_INVALID_ARGUMENT; + } + if ((nodeId == NUMA_NO_NODE) || test_bit(nodeId, nvl->coherent_link_info.free_node_bitmap)) + { + return NV_ERR_INVALID_ARGUMENT; + } + + NV_ATOMIC_SET(nvl->numa_info.status, NV_IOCTL_NUMA_STATUS_OFFLINE_IN_PROGRESS); + +#ifdef NV_OFFLINE_AND_REMOVE_MEMORY_PRESENT + numa_info.base = base; + numa_info.size = size; + numa_info.nodeId = nodeId; + numa_info.ret = 0; + + nv_kthread_q_item_init(&remove_numa_memory_q_item, + offline_numa_memory_callback, + &numa_info); + nv_kthread_q_schedule_q_item(&nvl->remove_numa_memory_q, + &remove_numa_memory_q_item); + nv_kthread_q_flush(&nvl->remove_numa_memory_q); + + ret = numa_info.ret; + + if (ret == 0) + { + set_bit(nodeId, nvl->coherent_link_info.free_node_bitmap); + + NV_ATOMIC_SET(nvl->numa_info.status, NV_IOCTL_NUMA_STATUS_OFFLINE); + return NV_OK; + } + + nv_printf(NV_DBG_ERRORS, "NVRM: Memory remove failed. base: 0x%lx size: 0x%lx ret: %d\n", + base, size, ret); +#endif + NV_ATOMIC_SET(nvl->numa_info.status, NV_IOCTL_NUMA_STATUS_OFFLINE_FAILED); + return NV_ERR_OPERATING_SYSTEM; +#endif + return NV_ERR_NOT_SUPPORTED; +} + +NV_STATUS NV_API_CALL os_offline_page_at_address +( + NvU64 address +) +{ +#if defined(CONFIG_MEMORY_FAILURE) + int flags = 0; + int ret; + NvU64 pfn; + struct page *page = NV_GET_PAGE_STRUCT(address); + + if (page == NULL) + { + nv_printf(NV_DBG_ERRORS, "NVRM: Failed to get page struct for address: 0x%llx\n", + address); + return NV_ERR_INVALID_ARGUMENT; + } + + pfn = page_to_pfn(page); + +#ifdef NV_MEMORY_FAILURE_MF_SW_SIMULATED_DEFINED + // + // Set MF_SW_SIMULATED flag so Linux kernel can differentiate this from a HW + // memory failure. HW memory failures cannot be unset via unpoison_memory() API. + // + // Currently, RM does not use unpoison_memory(), so it makes no difference + // whether or not MF_SW_SIMULATED is set. Regardless, it is semantically more + // correct to set MF_SW_SIMULATED. + // + flags |= MF_SW_SIMULATED; +#endif + +#ifdef NV_MEMORY_FAILURE_HAS_TRAPNO_ARG + ret = memory_failure(pfn, 0, flags); +#else + ret = memory_failure(pfn, flags); +#endif + + if (ret != 0) + { + nv_printf(NV_DBG_ERRORS, "NVRM: page offlining failed. address: 0x%llx pfn: 0x%llx ret: %d\n", + address, pfn, ret); + return NV_ERR_OPERATING_SYSTEM; + } + + return NV_OK; +#else // !defined(CONFIG_MEMORY_FAILURE) + nv_printf(NV_DBG_ERRORS, "NVRM: memory_failure() not supported by kernel. page offlining failed. address: 0x%llx\n", + address); + return NV_ERR_NOT_SUPPORTED; +#endif +} + +void* NV_API_CALL os_get_pid_info(void) +{ + return get_task_pid(current, PIDTYPE_PID); +} + +void NV_API_CALL os_put_pid_info(void *pid_info) +{ + if (pid_info != NULL) + put_pid(pid_info); +} + +NV_STATUS NV_API_CALL os_find_ns_pid(void *pid_info, NvU32 *ns_pid) +{ + if ((pid_info == NULL) || (ns_pid == NULL)) + return NV_ERR_INVALID_ARGUMENT; + + *ns_pid = pid_vnr((struct pid *)pid_info); + + // The call returns 0 if the PID is not found in the current ns + if (*ns_pid == 0) + return NV_ERR_OBJECT_NOT_FOUND; + + return NV_OK; +} + diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/kernel-open/nvidia/os-mlock.c nvidia-open-gpu-kernel-modules-535.161.08/kernel-open/nvidia/os-mlock.c --- nvidia-open-gpu-kernel-modules-525.147.05/kernel-open/nvidia/os-mlock.c 2023-10-25 20:33:20.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/kernel-open/nvidia/os-mlock.c 2024-03-05 22:25:32.000000000 +0000 @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 1999-2021 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 1999-2024 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -87,59 +87,10 @@ return NV_OK; } -/*! - * @brief Pins user IO pages that have been mapped to the user processes virtual - * address space with remap_pfn_range. - * - * @param[in] vma VMA that contains the virtual address range given by the - * start and the page count. - * @param[in] start Beginning of the virtual address range of the IO pages. - * @param[in] page_count Number of pages to pin from start. - * @param[in,out] page_array Storage array for pointers to the pinned pages. - * Must be large enough to contain at least page_count - * pointers. - * - * @return NV_OK if the pages were pinned successfully, error otherwise. - */ -static NV_STATUS get_io_pages(struct vm_area_struct *vma, - NvUPtr start, - NvU64 page_count, - struct page **page_array) -{ - NV_STATUS rmStatus = NV_OK; - NvU64 i, pinned = 0; - unsigned long pfn; - - for (i = 0; i < page_count; i++) - { - if ((nv_follow_pfn(vma, (start + (i * PAGE_SIZE)), &pfn) < 0) || - (!pfn_valid(pfn))) - { - rmStatus = NV_ERR_INVALID_ADDRESS; - break; - } - - // Page-backed memory mapped to userspace with remap_pfn_range - page_array[i] = pfn_to_page(pfn); - get_page(page_array[i]); - pinned++; - } - - if (pinned < page_count) - { - for (i = 0; i < pinned; i++) - put_page(page_array[i]); - rmStatus = NV_ERR_INVALID_ADDRESS; - } - - return rmStatus; -} - NV_STATUS NV_API_CALL os_lookup_user_io_memory( void *address, NvU64 page_count, - NvU64 **pte_array, - void **page_array + NvU64 **pte_array ) { NV_STATUS rmStatus; @@ -187,18 +138,9 @@ goto done; } - if (pfn_valid(pfn)) - { - rmStatus = get_io_pages(vma, start, page_count, (struct page **)result_array); - if (rmStatus == NV_OK) - *page_array = (void *)result_array; - } - else - { - rmStatus = get_io_ptes(vma, start, page_count, (NvU64 **)result_array); - if (rmStatus == NV_OK) - *pte_array = (NvU64 *)result_array; - } + rmStatus = get_io_ptes(vma, start, page_count, (NvU64 **)result_array); + if (rmStatus == NV_OK) + *pte_array = (NvU64 *)result_array; done: nv_mmap_read_unlock(mm); diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/kernel-open/nvidia/os-registry.c nvidia-open-gpu-kernel-modules-535.161.08/kernel-open/nvidia/os-registry.c --- nvidia-open-gpu-kernel-modules-525.147.05/kernel-open/nvidia/os-registry.c 2023-10-25 20:33:20.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/kernel-open/nvidia/os-registry.c 2024-03-05 22:25:32.000000000 +0000 @@ -317,6 +317,14 @@ return NV_ERR_NO_MEMORY; } + if (NVreg_RmNvlinkBandwidth != NULL) + { + rm_write_registry_string(sp, NULL, + "RmNvlinkBandwidth", + NVreg_RmNvlinkBandwidth, + strlen(NVreg_RmNvlinkBandwidth)); + } + if (NVreg_RmMsg != NULL) { rm_write_registry_string(sp, NULL, diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/kernel-open/nvidia-drm/nvidia-drm-connector.c nvidia-open-gpu-kernel-modules-535.161.08/kernel-open/nvidia-drm/nvidia-drm-connector.c --- nvidia-open-gpu-kernel-modules-525.147.05/kernel-open/nvidia-drm/nvidia-drm-connector.c 2023-10-25 20:25:17.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/kernel-open/nvidia-drm/nvidia-drm-connector.c 2024-03-05 22:14:11.000000000 +0000 @@ -27,6 +27,7 @@ #include "nvidia-drm-helper.h" #include "nvidia-drm-priv.h" #include "nvidia-drm-connector.h" +#include "nvidia-drm-crtc.h" #include "nvidia-drm-utils.h" #include "nvidia-drm-encoder.h" @@ -207,6 +208,11 @@ nv_drm_free(pDetectParams); + if (status == connector_status_disconnected && + nv_connector->modeset_permission_filep) { + nv_drm_connector_revoke_permissions(dev, nv_connector); + } + return status; } @@ -372,6 +378,8 @@ nv_connector->physicalIndex = physicalIndex; nv_connector->type = type; nv_connector->internal = internal; + nv_connector->modeset_permission_filep = NULL; + nv_connector->modeset_permission_crtc = NULL; strcpy(nv_connector->dpAddress, dpAddress); @@ -474,4 +482,26 @@ return connector; } +/* + * Revoke the permissions on this connector. + */ +bool nv_drm_connector_revoke_permissions(struct drm_device *dev, + struct nv_drm_connector* nv_connector) +{ + struct nv_drm_device *nv_dev = to_nv_device(dev); + bool ret = true; + + if (nv_connector->modeset_permission_crtc) { + if (nv_connector->nv_detected_encoder) { + ret = nvKms->revokePermissions( + nv_dev->pDevice, nv_connector->modeset_permission_crtc->head, + nv_connector->nv_detected_encoder->hDisplay); + } + nv_connector->modeset_permission_crtc->modeset_permission_filep = NULL; + nv_connector->modeset_permission_crtc = NULL; + } + nv_connector->modeset_permission_filep = NULL; + return ret; +} + #endif diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/kernel-open/nvidia-drm/nvidia-drm-connector.h nvidia-open-gpu-kernel-modules-535.161.08/kernel-open/nvidia-drm/nvidia-drm-connector.h --- nvidia-open-gpu-kernel-modules-525.147.05/kernel-open/nvidia-drm/nvidia-drm-connector.h 2023-10-25 20:25:16.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/kernel-open/nvidia-drm/nvidia-drm-connector.h 2024-03-05 22:14:09.000000000 +0000 @@ -51,6 +51,20 @@ atomic_t connection_status_dirty; + /** + * @modeset_permission_filep: + * + * The filep using this connector with DRM_IOCTL_NVIDIA_GRANT_PERMISSIONS. + */ + struct drm_file *modeset_permission_filep; + + /** + * @modeset_permission_crtc: + * + * The crtc using this connector with DRM_IOCTL_NVIDIA_GRANT_PERMISSIONS. + */ + struct nv_drm_crtc *modeset_permission_crtc; + struct drm_connector base; }; @@ -84,6 +98,9 @@ NvBool internal, char dpAddress[NVKMS_DP_ADDRESS_STRING_LENGTH]); +bool nv_drm_connector_revoke_permissions(struct drm_device *dev, + struct nv_drm_connector *nv_connector); + #endif /* NV_DRM_ATOMIC_MODESET_AVAILABLE */ #endif /* __NVIDIA_DRM_CONNECTOR_H__ */ diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/kernel-open/nvidia-drm/nvidia-drm-crtc.c nvidia-open-gpu-kernel-modules-535.161.08/kernel-open/nvidia-drm/nvidia-drm-crtc.c --- nvidia-open-gpu-kernel-modules-525.147.05/kernel-open/nvidia-drm/nvidia-drm-crtc.c 2023-10-25 20:25:17.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/kernel-open/nvidia-drm/nvidia-drm-crtc.c 2024-03-05 22:14:11.000000000 +0000 @@ -44,6 +44,8 @@ #if defined(NV_LINUX_NVHOST_H_PRESENT) && defined(CONFIG_TEGRA_GRHOST) #include +#elif defined(NV_LINUX_HOST1X_NEXT_H_PRESENT) +#include #endif #if defined(NV_DRM_HAS_HDR_OUTPUT_METADATA) @@ -361,6 +363,21 @@ if (nv_drm_plane_state->fd_user_ptr) { req_config->config.syncptParams.postSyncptRequested = true; + } +#elif defined(NV_LINUX_HOST1X_NEXT_H_PRESENT) + if (plane_state->fence != NULL) { + int ret = host1x_fence_extract( + plane_state->fence, + &req_config->config.syncptParams.preSyncptId, + &req_config->config.syncptParams.preSyncptValue); + if (ret != 0) { + return ret; + } + req_config->config.syncptParams.preSyncptSpecified = true; + } + + if (nv_drm_plane_state->fd_user_ptr) { + req_config->config.syncptParams.postSyncptRequested = true; } #else return -1; @@ -1181,6 +1198,7 @@ nv_crtc->head = head; INIT_LIST_HEAD(&nv_crtc->flip_list); spin_lock_init(&nv_crtc->flip_list_lock); + nv_crtc->modeset_permission_filep = NULL; ret = drm_crtc_init_with_planes(nv_dev->dev, &nv_crtc->base, @@ -1329,7 +1347,7 @@ return -ENOENT; } - crtc = nv_drm_crtc_find(dev, params->crtc_id); + crtc = nv_drm_crtc_find(dev, filep, params->crtc_id); if (!crtc) { return -ENOENT; } @@ -1357,7 +1375,7 @@ return -ENOENT; } - crtc = nv_drm_crtc_find(dev, params->crtc_id); + crtc = nv_drm_crtc_find(dev, filep, params->crtc_id); if (!crtc) { return -ENOENT; } diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/kernel-open/nvidia-drm/nvidia-drm-crtc.h nvidia-open-gpu-kernel-modules-535.161.08/kernel-open/nvidia-drm/nvidia-drm-crtc.h --- nvidia-open-gpu-kernel-modules-525.147.05/kernel-open/nvidia-drm/nvidia-drm-crtc.h 2023-10-25 20:25:16.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/kernel-open/nvidia-drm/nvidia-drm-crtc.h 2024-03-05 22:14:09.000000000 +0000 @@ -35,38 +35,9 @@ #include -#if defined(NV_DRM_ALPHA_BLENDING_AVAILABLE) || defined(NV_DRM_ROTATION_AVAILABLE) -/* For DRM_ROTATE_* , DRM_REFLECT_* */ -#include -#endif - -#if defined(NV_DRM_ROTATION_AVAILABLE) -/* For DRM_MODE_ROTATE_* and DRM_MODE_REFLECT_* */ -#include -#endif - #include "nvtypes.h" #include "nvkms-kapi.h" -#if defined(NV_DRM_ROTATION_AVAILABLE) -/* - * 19-05-2017 c2c446ad29437bb92b157423c632286608ebd3ec has added - * DRM_MODE_ROTATE_* and DRM_MODE_REFLECT_* to UAPI and removed - * DRM_ROTATE_* and DRM_MODE_REFLECT_* - */ -#if !defined(DRM_MODE_ROTATE_0) -#define DRM_MODE_ROTATE_0 DRM_ROTATE_0 -#define DRM_MODE_ROTATE_90 DRM_ROTATE_90 -#define DRM_MODE_ROTATE_180 DRM_ROTATE_180 -#define DRM_MODE_ROTATE_270 DRM_ROTATE_270 -#define DRM_MODE_REFLECT_X DRM_REFLECT_X -#define DRM_MODE_REFLECT_Y DRM_REFLECT_Y -#define DRM_MODE_ROTATE_MASK DRM_ROTATE_MASK -#define DRM_MODE_REFLECT_MASK DRM_REFLECT_MASK -#endif - -#endif //NV_DRM_ROTATION_AVAILABLE - struct nv_drm_crtc { NvU32 head; @@ -85,6 +56,13 @@ */ spinlock_t flip_list_lock; + /** + * @modeset_permission_filep: + * + * The filep using this crtc with DRM_IOCTL_NVIDIA_GRANT_PERMISSIONS. + */ + struct drm_file *modeset_permission_filep; + struct drm_crtc base; }; diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/kernel-open/nvidia-drm/nvidia-drm-drv.c nvidia-open-gpu-kernel-modules-535.161.08/kernel-open/nvidia-drm/nvidia-drm-drv.c --- nvidia-open-gpu-kernel-modules-525.147.05/kernel-open/nvidia-drm/nvidia-drm-drv.c 2023-10-25 20:25:17.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/kernel-open/nvidia-drm/nvidia-drm-drv.c 2024-03-05 22:14:11.000000000 +0000 @@ -30,7 +30,7 @@ #include "nvidia-drm-connector.h" #include "nvidia-drm-gem.h" #include "nvidia-drm-crtc.h" -#include "nvidia-drm-prime-fence.h" +#include "nvidia-drm-fence.h" #include "nvidia-drm-helper.h" #include "nvidia-drm-gem-nvkms-memory.h" #include "nvidia-drm-gem-user-memory.h" @@ -706,6 +706,16 @@ return 0; } +static int nv_drm_dmabuf_supported_ioctl(struct drm_device *dev, + void *data, struct drm_file *filep) +{ + /* check the pDevice since this only gets set if modeset = 1 + * which is a requirement for the dma_buf extension to work + */ + struct nv_drm_device *nv_dev = to_nv_device(dev); + return nv_dev->pDevice ? 0 : -EINVAL; +} + static int nv_drm_get_client_capability_ioctl(struct drm_device *dev, void *data, struct drm_file *filep) @@ -735,6 +745,455 @@ return 0; } +#if defined(NV_DRM_ATOMIC_MODESET_AVAILABLE) +static bool nv_drm_connector_is_dpy_id(struct drm_connector *connector, + NvU32 dpyId) +{ + struct nv_drm_connector *nv_connector = to_nv_connector(connector); + return nv_connector->nv_detected_encoder && + nv_connector->nv_detected_encoder->hDisplay == dpyId; +} + +static int nv_drm_get_dpy_id_for_connector_id_ioctl(struct drm_device *dev, + void *data, + struct drm_file *filep) +{ + struct drm_nvidia_get_dpy_id_for_connector_id_params *params = data; + // Importantly, drm_connector_lookup (with filep) will only return the + // connector if we are master, a lessee with the connector, or not master at + // all. It will return NULL if we are a lessee with other connectors. + struct drm_connector *connector = + nv_drm_connector_lookup(dev, filep, params->connectorId); + struct nv_drm_connector *nv_connector; + int ret = 0; + + if (!connector) { + return -EINVAL; + } + + nv_connector = to_nv_connector(connector); + if (!nv_connector) { + ret = -EINVAL; + goto done; + } + + if (!nv_connector->nv_detected_encoder) { + ret = -EINVAL; + goto done; + } + + params->dpyId = nv_connector->nv_detected_encoder->hDisplay; + +done: + nv_drm_connector_put(connector); + return ret; +} + +static int nv_drm_get_connector_id_for_dpy_id_ioctl(struct drm_device *dev, + void *data, + struct drm_file *filep) +{ + struct drm_nvidia_get_connector_id_for_dpy_id_params *params = data; + struct drm_connector *connector; + int ret = -EINVAL; +#if defined(NV_DRM_CONNECTOR_LIST_ITER_PRESENT) + struct drm_connector_list_iter conn_iter; + nv_drm_connector_list_iter_begin(dev, &conn_iter); +#endif + + /* Lookup for existing connector with same dpyId */ + nv_drm_for_each_connector(connector, &conn_iter, dev) { + if (nv_drm_connector_is_dpy_id(connector, params->dpyId)) { + params->connectorId = connector->base.id; + ret = 0; + break; + } + } +#if defined(NV_DRM_CONNECTOR_LIST_ITER_PRESENT) + nv_drm_connector_list_iter_end(&conn_iter); +#endif + + return ret; +} + +static NvU32 nv_drm_get_head_bit_from_connector(struct drm_connector *connector) +{ + struct nv_drm_connector *nv_connector = to_nv_connector(connector); + + if (connector->state && connector->state->crtc) { + struct nv_drm_crtc *nv_crtc = to_nv_crtc(connector->state->crtc); + return NVBIT(nv_crtc->head); + } else if (nv_connector->nv_detected_encoder && + nv_connector->nv_detected_encoder->base.crtc) { + struct nv_drm_crtc *nv_crtc = + to_nv_crtc(nv_connector->nv_detected_encoder->base.crtc); + return NVBIT(nv_crtc->head); + } + + return 0; +} + +static int nv_drm_grant_permission_ioctl(struct drm_device *dev, void *data, + struct drm_file *filep) +{ + struct drm_nvidia_grant_permissions_params *params = data; + struct nv_drm_device *nv_dev = to_nv_device(dev); + struct nv_drm_connector *target_nv_connector = NULL; + struct nv_drm_crtc *target_nv_crtc = NULL; + struct drm_connector *connector, *target_connector = NULL; + struct drm_crtc *crtc; + NvU32 head = 0, freeHeadBits, targetHeadBit, possible_crtcs; + int ret = 0; +#if defined(NV_DRM_CONNECTOR_LIST_ITER_PRESENT) + struct drm_connector_list_iter conn_iter; +#endif +#if NV_DRM_MODESET_LOCK_ALL_END_ARGUMENT_COUNT == 3 + struct drm_modeset_acquire_ctx ctx; + DRM_MODESET_LOCK_ALL_BEGIN(dev, ctx, DRM_MODESET_ACQUIRE_INTERRUPTIBLE, + ret); +#else + mutex_lock(&dev->mode_config.mutex); +#endif + + /* Get the connector for the dpyId. */ +#if defined(NV_DRM_CONNECTOR_LIST_ITER_PRESENT) + nv_drm_connector_list_iter_begin(dev, &conn_iter); +#endif + nv_drm_for_each_connector(connector, &conn_iter, dev) { + if (nv_drm_connector_is_dpy_id(connector, params->dpyId)) { + target_connector = + nv_drm_connector_lookup(dev, filep, connector->base.id); + break; + } + } +#if defined(NV_DRM_CONNECTOR_LIST_ITER_PRESENT) + nv_drm_connector_list_iter_end(&conn_iter); +#endif + + // Importantly, drm_connector_lookup/drm_crtc_find (with filep) will only + // return the object if we are master, a lessee with the object, or not + // master at all. It will return NULL if we are a lessee with other objects. + if (!target_connector) { + ret = -EINVAL; + goto done; + } + target_nv_connector = to_nv_connector(target_connector); + possible_crtcs = + target_nv_connector->nv_detected_encoder->base.possible_crtcs; + + /* Target connector must not be previously granted. */ + if (target_nv_connector->modeset_permission_filep) { + ret = -EINVAL; + goto done; + } + + /* Add all heads that are owned and not already granted. */ + freeHeadBits = 0; + nv_drm_for_each_crtc(crtc, dev) { + struct nv_drm_crtc *nv_crtc = to_nv_crtc(crtc); + if (nv_drm_crtc_find(dev, filep, crtc->base.id) && + !nv_crtc->modeset_permission_filep && + (drm_crtc_mask(crtc) & possible_crtcs)) { + freeHeadBits |= NVBIT(nv_crtc->head); + } + } + + targetHeadBit = nv_drm_get_head_bit_from_connector(target_connector); + if (targetHeadBit & freeHeadBits) { + /* If a crtc is already being used by this connector, use it. */ + freeHeadBits = targetHeadBit; + } else { + /* Otherwise, remove heads that are in use by other connectors. */ +#if defined(NV_DRM_CONNECTOR_LIST_ITER_PRESENT) + nv_drm_connector_list_iter_begin(dev, &conn_iter); +#endif + nv_drm_for_each_connector(connector, &conn_iter, dev) { + freeHeadBits &= ~nv_drm_get_head_bit_from_connector(connector); + } +#if defined(NV_DRM_CONNECTOR_LIST_ITER_PRESENT) + nv_drm_connector_list_iter_end(&conn_iter); +#endif + } + + /* Fail if no heads are available. */ + if (!freeHeadBits) { + ret = -EINVAL; + goto done; + } + + /* + * Loop through the crtc again and find a matching head. + * Record the filep that is using the crtc and the connector. + */ + nv_drm_for_each_crtc(crtc, dev) { + struct nv_drm_crtc *nv_crtc = to_nv_crtc(crtc); + if (freeHeadBits & NVBIT(nv_crtc->head)) { + target_nv_crtc = nv_crtc; + head = nv_crtc->head; + break; + } + } + + if (!nvKms->grantPermissions(params->fd, nv_dev->pDevice, head, + params->dpyId)) { + ret = -EINVAL; + goto done; + } + + target_nv_connector->modeset_permission_crtc = target_nv_crtc; + target_nv_connector->modeset_permission_filep = filep; + target_nv_crtc->modeset_permission_filep = filep; + +done: + if (target_connector) { + nv_drm_connector_put(target_connector); + } + +#if NV_DRM_MODESET_LOCK_ALL_END_ARGUMENT_COUNT == 3 + DRM_MODESET_LOCK_ALL_END(dev, ctx, ret); +#else + mutex_unlock(&dev->mode_config.mutex); +#endif + + return ret; +} + +static bool nv_drm_revoke_connector(struct nv_drm_device *nv_dev, + struct nv_drm_connector *nv_connector) +{ + bool ret = true; + if (nv_connector->modeset_permission_crtc) { + if (nv_connector->nv_detected_encoder) { + ret = nvKms->revokePermissions( + nv_dev->pDevice, nv_connector->modeset_permission_crtc->head, + nv_connector->nv_detected_encoder->hDisplay); + } + nv_connector->modeset_permission_crtc->modeset_permission_filep = NULL; + nv_connector->modeset_permission_crtc = NULL; + } + nv_connector->modeset_permission_filep = NULL; + return ret; +} + +static int nv_drm_revoke_permission(struct drm_device *dev, + struct drm_file *filep, NvU32 dpyId) +{ + struct drm_connector *connector; + struct drm_crtc *crtc; + int ret = 0; +#if defined(NV_DRM_CONNECTOR_LIST_ITER_PRESENT) + struct drm_connector_list_iter conn_iter; +#endif +#if NV_DRM_MODESET_LOCK_ALL_END_ARGUMENT_COUNT == 3 + struct drm_modeset_acquire_ctx ctx; + DRM_MODESET_LOCK_ALL_BEGIN(dev, ctx, DRM_MODESET_ACQUIRE_INTERRUPTIBLE, + ret); +#else + mutex_lock(&dev->mode_config.mutex); +#endif + + /* + * If dpyId is set, only revoke those specific resources. Otherwise, + * it is from closing the file so revoke all resources for that filep. + */ +#if defined(NV_DRM_CONNECTOR_LIST_ITER_PRESENT) + nv_drm_connector_list_iter_begin(dev, &conn_iter); +#endif + nv_drm_for_each_connector(connector, &conn_iter, dev) { + struct nv_drm_connector *nv_connector = to_nv_connector(connector); + if (nv_connector->modeset_permission_filep == filep && + (!dpyId || nv_drm_connector_is_dpy_id(connector, dpyId))) { + if (!nv_drm_connector_revoke_permissions(dev, nv_connector)) { + ret = -EINVAL; + // Continue trying to revoke as much as possible. + } + } + } +#if defined(NV_DRM_CONNECTOR_LIST_ITER_PRESENT) + nv_drm_connector_list_iter_end(&conn_iter); +#endif + + nv_drm_for_each_crtc(crtc, dev) { + struct nv_drm_crtc *nv_crtc = to_nv_crtc(crtc); + if (nv_crtc->modeset_permission_filep == filep && !dpyId) { + nv_crtc->modeset_permission_filep = NULL; + } + } + +#if NV_DRM_MODESET_LOCK_ALL_END_ARGUMENT_COUNT == 3 + DRM_MODESET_LOCK_ALL_END(dev, ctx, ret); +#else + mutex_unlock(&dev->mode_config.mutex); +#endif + + return ret; +} + +static int nv_drm_revoke_permission_ioctl(struct drm_device *dev, void *data, + struct drm_file *filep) +{ + struct drm_nvidia_revoke_permissions_params *params = data; + if (!params->dpyId) { + return -EINVAL; + } + return nv_drm_revoke_permission(dev, filep, params->dpyId); +} + +static void nv_drm_postclose(struct drm_device *dev, struct drm_file *filep) +{ + /* + * Some systems like android can reach here without initializing the + * device, so check for that. + */ + if (dev->mode_config.num_crtc > 0 && + dev->mode_config.crtc_list.next != NULL && + dev->mode_config.crtc_list.prev != NULL && + dev->mode_config.num_connector > 0 && + dev->mode_config.connector_list.next != NULL && + dev->mode_config.connector_list.prev != NULL) { + nv_drm_revoke_permission(dev, filep, 0); + } +} +#endif /* NV_DRM_ATOMIC_MODESET_AVAILABLE */ + +#if defined(NV_DRM_MASTER_HAS_LEASES) +static struct drm_master *nv_drm_find_lessee(struct drm_master *master, + int lessee_id) +{ + int object; + void *entry; + + while (master->lessor != NULL) { + master = master->lessor; + } + + idr_for_each_entry(&master->lessee_idr, entry, object) + { + if (object == lessee_id) { + return entry; + } + } + + return NULL; +} + +static void nv_drm_get_revoked_objects(struct drm_device *dev, + struct drm_file *filep, unsigned int cmd, + unsigned long arg, int **objects, + int *objects_count) +{ + unsigned int ioc_size; + struct drm_mode_revoke_lease revoke_lease; + struct drm_master *lessor, *lessee; + void *entry; + int *objs; + int obj, obj_count, obj_i; + + ioc_size = _IOC_SIZE(cmd); + if (ioc_size > sizeof(revoke_lease)) { + return; + } + + if (copy_from_user(&revoke_lease, (void __user *)arg, ioc_size) != 0) { + return; + } + + lessor = nv_drm_file_get_master(filep); + if (lessor == NULL) { + return; + } + + mutex_lock(&dev->mode_config.idr_mutex); + lessee = nv_drm_find_lessee(lessor, revoke_lease.lessee_id); + + if (lessee == NULL) { + goto done; + } + + obj_count = 0; + idr_for_each_entry(&lessee->leases, entry, obj) { + ++obj_count; + } + if (obj_count == 0) { + goto done; + } + + objs = nv_drm_calloc(obj_count, sizeof(int)); + if (objs == NULL) { + goto done; + } + + obj_i = 0; + idr_for_each_entry(&lessee->leases, entry, obj) { + objs[obj_i++] = obj; + } + *objects = objs; + *objects_count = obj_count; + +done: + mutex_unlock(&dev->mode_config.idr_mutex); + drm_master_put(&lessor); +} + +static bool nv_drm_is_in_objects(int object, int *objects, int objects_count) +{ + int i; + for (i = 0; i < objects_count; ++i) { + if (objects[i] == object) { + return true; + } + } + return false; +} + +static void nv_drm_finish_revoking_objects(struct drm_device *dev, + struct drm_file *filep, int *objects, + int objects_count) +{ + struct drm_connector *connector; + struct drm_crtc *crtc; +#if defined(NV_DRM_CONNECTOR_LIST_ITER_PRESENT) + struct drm_connector_list_iter conn_iter; +#endif +#if NV_DRM_MODESET_LOCK_ALL_END_ARGUMENT_COUNT == 3 + int ret = 0; + struct drm_modeset_acquire_ctx ctx; + DRM_MODESET_LOCK_ALL_BEGIN(dev, ctx, DRM_MODESET_ACQUIRE_INTERRUPTIBLE, + ret); +#else + mutex_lock(&dev->mode_config.mutex); +#endif + +#if defined(NV_DRM_CONNECTOR_LIST_ITER_PRESENT) + nv_drm_connector_list_iter_begin(dev, &conn_iter); +#endif + nv_drm_for_each_connector(connector, &conn_iter, dev) { + struct nv_drm_connector *nv_connector = to_nv_connector(connector); + if (nv_connector->modeset_permission_filep && + nv_drm_is_in_objects(connector->base.id, objects, objects_count)) { + nv_drm_connector_revoke_permissions(dev, nv_connector); + } + } +#if defined(NV_DRM_CONNECTOR_LIST_ITER_PRESENT) + nv_drm_connector_list_iter_end(&conn_iter); +#endif + + nv_drm_for_each_crtc(crtc, dev) { + struct nv_drm_crtc *nv_crtc = to_nv_crtc(crtc); + if (nv_crtc->modeset_permission_filep && + nv_drm_is_in_objects(crtc->base.id, objects, objects_count)) { + nv_crtc->modeset_permission_filep = NULL; + } + } + +#if NV_DRM_MODESET_LOCK_ALL_END_ARGUMENT_COUNT == 3 + DRM_MODESET_LOCK_ALL_END(dev, ctx, ret); +#else + mutex_unlock(&dev->mode_config.mutex); +#endif +} +#endif /* NV_DRM_MASTER_HAS_LEASES */ + #if defined(NV_DRM_BUS_PRESENT) #if defined(NV_DRM_BUS_HAS_GET_IRQ) @@ -766,12 +1225,50 @@ #endif /* NV_DRM_BUS_PRESENT */ +/* + * Wrapper around drm_ioctl to hook in to upstream ioctl. + * + * Currently used to add additional handling to REVOKE_LEASE. + */ +static long nv_drm_ioctl(struct file *filp, unsigned int cmd, unsigned long arg) +{ + long retcode; + +#if defined(NV_DRM_MASTER_HAS_LEASES) + struct drm_file *file_priv = filp->private_data; + struct drm_device *dev = file_priv->minor->dev; + int *objects = NULL; + int objects_count = 0; + + if (cmd == DRM_IOCTL_MODE_REVOKE_LEASE) { + // Save the revoked objects before revoking. + nv_drm_get_revoked_objects(dev, file_priv, cmd, arg, &objects, + &objects_count); + } +#endif + + retcode = drm_ioctl(filp, cmd, arg); + +#if defined(NV_DRM_MASTER_HAS_LEASES) + if (cmd == DRM_IOCTL_MODE_REVOKE_LEASE && objects) { + if (retcode == 0) { + // If revoking was successful, finish revoking the objects. + nv_drm_finish_revoking_objects(dev, file_priv, objects, + objects_count); + } + nv_drm_free(objects); + } +#endif + + return retcode; +} + static const struct file_operations nv_drm_fops = { .owner = THIS_MODULE, .open = drm_open, .release = drm_release, - .unlocked_ioctl = drm_ioctl, + .unlocked_ioctl = nv_drm_ioctl, #if defined(CONFIG_COMPAT) .compat_ioctl = drm_compat_ioctl, #endif @@ -807,17 +1304,29 @@ DRM_IOCTL_DEF_DRV(NVIDIA_FENCE_SUPPORTED, nv_drm_fence_supported_ioctl, DRM_RENDER_ALLOW|DRM_UNLOCKED), - DRM_IOCTL_DEF_DRV(NVIDIA_FENCE_CONTEXT_CREATE, - nv_drm_fence_context_create_ioctl, + DRM_IOCTL_DEF_DRV(NVIDIA_PRIME_FENCE_CONTEXT_CREATE, + nv_drm_prime_fence_context_create_ioctl, DRM_RENDER_ALLOW|DRM_UNLOCKED), - DRM_IOCTL_DEF_DRV(NVIDIA_GEM_FENCE_ATTACH, - nv_drm_gem_fence_attach_ioctl, + DRM_IOCTL_DEF_DRV(NVIDIA_GEM_PRIME_FENCE_ATTACH, + nv_drm_gem_prime_fence_attach_ioctl, DRM_RENDER_ALLOW|DRM_UNLOCKED), #endif + /* + * DRM_UNLOCKED is implicit for all non-legacy DRM driver IOCTLs since Linux + * v4.10 commit fa5386459f06 "drm: Used DRM_LEGACY for all legacy functions" + * (Linux v4.4 commit ea487835e887 "drm: Enforce unlocked ioctl operation + * for kms driver ioctls" previously did it only for drivers that set the + * DRM_MODESET flag), so this will race with SET_CLIENT_CAP. Linux v4.11 + * commit dcf727ab5d17 "drm: setclientcap doesn't need the drm BKL" also + * removed locking from SET_CLIENT_CAP so there is no use attempting to lock + * manually. The latter commit acknowledges that this can expose userspace + * to inconsistent behavior when racing with itself, but accepts that risk. + */ DRM_IOCTL_DEF_DRV(NVIDIA_GET_CLIENT_CAPABILITY, nv_drm_get_client_capability_ioctl, 0), + #if defined(NV_DRM_ATOMIC_MODESET_AVAILABLE) DRM_IOCTL_DEF_DRV(NVIDIA_GET_CRTC_CRC32, nv_drm_get_crtc_crc32_ioctl, @@ -837,6 +1346,21 @@ DRM_IOCTL_DEF_DRV(NVIDIA_GEM_IDENTIFY_OBJECT, nv_drm_gem_identify_object_ioctl, DRM_RENDER_ALLOW|DRM_UNLOCKED), + DRM_IOCTL_DEF_DRV(NVIDIA_DMABUF_SUPPORTED, + nv_drm_dmabuf_supported_ioctl, + DRM_RENDER_ALLOW|DRM_UNLOCKED), + DRM_IOCTL_DEF_DRV(NVIDIA_GET_DPY_ID_FOR_CONNECTOR_ID, + nv_drm_get_dpy_id_for_connector_id_ioctl, + DRM_RENDER_ALLOW|DRM_UNLOCKED), + DRM_IOCTL_DEF_DRV(NVIDIA_GET_CONNECTOR_ID_FOR_DPY_ID, + nv_drm_get_connector_id_for_dpy_id_ioctl, + DRM_RENDER_ALLOW|DRM_UNLOCKED), + DRM_IOCTL_DEF_DRV(NVIDIA_GRANT_PERMISSIONS, + nv_drm_grant_permission_ioctl, + DRM_UNLOCKED|DRM_MASTER), + DRM_IOCTL_DEF_DRV(NVIDIA_REVOKE_PERMISSIONS, + nv_drm_revoke_permission_ioctl, + DRM_UNLOCKED|DRM_MASTER), #endif /* NV_DRM_ATOMIC_MODESET_AVAILABLE */ }; @@ -894,6 +1418,9 @@ .load = nv_drm_load, .unload = nv_drm_unload, +#if defined(NV_DRM_ATOMIC_MODESET_AVAILABLE) + .postclose = nv_drm_postclose, +#endif .fops = &nv_drm_fops, diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/kernel-open/nvidia-drm/nvidia-drm-encoder.c nvidia-open-gpu-kernel-modules-535.161.08/kernel-open/nvidia-drm/nvidia-drm-encoder.c --- nvidia-open-gpu-kernel-modules-525.147.05/kernel-open/nvidia-drm/nvidia-drm-encoder.c 2023-10-25 20:25:17.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/kernel-open/nvidia-drm/nvidia-drm-encoder.c 2024-03-05 22:14:11.000000000 +0000 @@ -205,7 +205,7 @@ encoder = nv_drm_encoder_new(dev, displayInfo->handle, connectorInfo->signalFormat, - get_crtc_mask(dev, connectorInfo->headMask)); + get_crtc_mask(dev, displayInfo->headMask)); if (IS_ERR(encoder)) { ret = PTR_ERR(encoder); diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/kernel-open/nvidia-drm/nvidia-drm-fb.c nvidia-open-gpu-kernel-modules-535.161.08/kernel-open/nvidia-drm/nvidia-drm-fb.c --- nvidia-open-gpu-kernel-modules-525.147.05/kernel-open/nvidia-drm/nvidia-drm-fb.c 2023-10-25 20:25:18.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/kernel-open/nvidia-drm/nvidia-drm-fb.c 2024-03-05 22:14:11.000000000 +0000 @@ -150,6 +150,14 @@ for (i = 0; i < ARRAY_SIZE(nv_fb->nv_gem); i++) { if (nv_fb->nv_gem[i] != NULL) { + if (!nvKms->isMemoryValidForDisplay(nv_dev->pDevice, + nv_fb->nv_gem[i]->pMemory)) { + NV_DRM_DEV_LOG_INFO( + nv_dev, + "Framebuffer memory not appropriate for scanout"); + goto fail; + } + params.planes[i].memory = nv_fb->nv_gem[i]->pMemory; params.planes[i].offset = nv_fb->base.offsets[i]; params.planes[i].pitch = nv_fb->base.pitches[i]; @@ -164,6 +172,17 @@ params.layout = (modifier & 0x10) ? NvKmsSurfaceMemoryLayoutBlockLinear : NvKmsSurfaceMemoryLayoutPitch; + + // See definition of DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D, we are testing + // 'c', the lossless compression field of the modifier + if (params.layout == NvKmsSurfaceMemoryLayoutBlockLinear && + (modifier >> 23) & 0x7) { + NV_DRM_DEV_LOG_ERR( + nv_dev, + "Cannot create FB from compressible surface allocation"); + goto fail; + } + params.log2GobsPerBlockY = modifier & 0xf; } else { params.explicit_layout = false; @@ -174,11 +193,14 @@ nv_fb->pSurface = nvKms->createSurface(nv_dev->pDevice, ¶ms); if (nv_fb->pSurface == NULL) { NV_DRM_DEV_DEBUG_DRIVER(nv_dev, "Failed to create NvKmsKapiSurface"); - drm_framebuffer_cleanup(&nv_fb->base); - return -EINVAL; + goto fail; } return 0; + +fail: + drm_framebuffer_cleanup(&nv_fb->base); + return -EINVAL; } struct drm_framebuffer *nv_drm_internal_framebuffer_create( diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/kernel-open/nvidia-drm/nvidia-drm-fence.c nvidia-open-gpu-kernel-modules-535.161.08/kernel-open/nvidia-drm/nvidia-drm-fence.c --- nvidia-open-gpu-kernel-modules-525.147.05/kernel-open/nvidia-drm/nvidia-drm-fence.c 1970-01-01 00:00:00.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/kernel-open/nvidia-drm/nvidia-drm-fence.c 2024-03-05 22:14:11.000000000 +0000 @@ -0,0 +1,600 @@ +/* + * Copyright (c) 2016, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#include "nvidia-drm-conftest.h" + +#if defined(NV_DRM_AVAILABLE) + +#if defined(NV_DRM_DRMP_H_PRESENT) +#include +#endif + +#include "nvidia-drm-priv.h" +#include "nvidia-drm-ioctl.h" +#include "nvidia-drm-gem.h" +#include "nvidia-drm-fence.h" +#include "nvidia-dma-resv-helper.h" + +#if defined(NV_DRM_FENCE_AVAILABLE) + +#include "nvidia-dma-fence-helper.h" + +struct nv_drm_fence_context; + +struct nv_drm_fence_context_ops { + void (*destroy)(struct nv_drm_fence_context *nv_fence_context); +}; + +struct nv_drm_fence_context { + const struct nv_drm_fence_context_ops *ops; + + struct nv_drm_device *nv_dev; + uint32_t context; +}; + +struct nv_drm_prime_fence_context { + struct nv_drm_fence_context base; + + NvU64 fenceSemIndex; /* Index into semaphore surface */ + + /* Mapped semaphore surface */ + struct NvKmsKapiMemory *pSemSurface; + NvU32 *pLinearAddress; + + /* Protects nv_drm_fence_context::{pending, last_seqno} */ + spinlock_t lock; + + /* + * Software signaling structures. __nv_drm_prime_fence_context_new() + * allocates channel event and __nv_drm_prime_fence_context_destroy() frees + * it. There are no simultaneous read/write access to 'cb', therefore it + * does not require spin-lock protection. + */ + struct NvKmsKapiChannelEvent *cb; + + /* List of pending fences which are not yet signaled */ + struct list_head pending; + + unsigned last_seqno; +}; + +struct nv_drm_prime_fence { + struct list_head list_entry; + nv_dma_fence_t base; + spinlock_t lock; +}; + +static inline +struct nv_drm_prime_fence *to_nv_drm_prime_fence(nv_dma_fence_t *fence) +{ + return container_of(fence, struct nv_drm_prime_fence, base); +} + +static const char* +nv_drm_gem_fence_op_get_driver_name(nv_dma_fence_t *fence) +{ + return "NVIDIA"; +} + +static const char* +nv_drm_gem_prime_fence_op_get_timeline_name(nv_dma_fence_t *fence) +{ + return "nvidia.prime"; +} + +static bool nv_drm_gem_prime_fence_op_enable_signaling(nv_dma_fence_t *fence) +{ + // DO NOTHING + return true; +} + +static void nv_drm_gem_prime_fence_op_release(nv_dma_fence_t *fence) +{ + struct nv_drm_prime_fence *nv_fence = to_nv_drm_prime_fence(fence); + nv_drm_free(nv_fence); +} + +static signed long +nv_drm_gem_prime_fence_op_wait(nv_dma_fence_t *fence, + bool intr, signed long timeout) +{ + /* + * If the waiter requests to wait with no timeout, force a timeout to ensure + * that it won't get stuck forever in the kernel if something were to go + * wrong with signaling, such as a malicious userspace not releasing the + * semaphore. + * + * 96 ms (roughly 6 frames @ 60 Hz) is arbitrarily chosen to be long enough + * that it should never get hit during normal operation, but not so long + * that the system becomes unresponsive. + */ + return nv_dma_fence_default_wait(fence, intr, + (timeout == MAX_SCHEDULE_TIMEOUT) ? + msecs_to_jiffies(96) : timeout); +} + +static const nv_dma_fence_ops_t nv_drm_gem_prime_fence_ops = { + .get_driver_name = nv_drm_gem_fence_op_get_driver_name, + .get_timeline_name = nv_drm_gem_prime_fence_op_get_timeline_name, + .enable_signaling = nv_drm_gem_prime_fence_op_enable_signaling, + .release = nv_drm_gem_prime_fence_op_release, + .wait = nv_drm_gem_prime_fence_op_wait, +}; + +static inline void +__nv_drm_prime_fence_signal(struct nv_drm_prime_fence *nv_fence) +{ + list_del(&nv_fence->list_entry); + nv_dma_fence_signal(&nv_fence->base); + nv_dma_fence_put(&nv_fence->base); +} + +static void nv_drm_gem_prime_force_fence_signal( + struct nv_drm_prime_fence_context *nv_fence_context) +{ + WARN_ON(!spin_is_locked(&nv_fence_context->lock)); + + while (!list_empty(&nv_fence_context->pending)) { + struct nv_drm_prime_fence *nv_fence = list_first_entry( + &nv_fence_context->pending, + typeof(*nv_fence), + list_entry); + + __nv_drm_prime_fence_signal(nv_fence); + } +} + +static void nv_drm_gem_prime_fence_event +( + void *dataPtr, + NvU32 dataU32 +) +{ + struct nv_drm_prime_fence_context *nv_fence_context = dataPtr; + + spin_lock(&nv_fence_context->lock); + + while (!list_empty(&nv_fence_context->pending)) { + struct nv_drm_prime_fence *nv_fence = list_first_entry( + &nv_fence_context->pending, + typeof(*nv_fence), + list_entry); + + /* Index into surface with 16 byte stride */ + unsigned int seqno = *((nv_fence_context->pLinearAddress) + + (nv_fence_context->fenceSemIndex * 4)); + + if (nv_fence->base.seqno > seqno) { + /* + * Fences in list are placed in increasing order of sequence + * number, breaks a loop once found first fence not + * ready to signal. + */ + break; + } + + __nv_drm_prime_fence_signal(nv_fence); + } + + spin_unlock(&nv_fence_context->lock); +} + +static inline struct nv_drm_prime_fence_context* +to_prime_fence_context(struct nv_drm_fence_context *nv_fence_context) { + return (struct nv_drm_prime_fence_context *)nv_fence_context; +} + +static void __nv_drm_prime_fence_context_destroy( + struct nv_drm_fence_context *nv_fence_context) +{ + struct nv_drm_device *nv_dev = nv_fence_context->nv_dev; + struct nv_drm_prime_fence_context *nv_prime_fence_context = + to_prime_fence_context(nv_fence_context); + + /* + * Free channel event before destroying the fence context, otherwise event + * callback continue to get called. + */ + nvKms->freeChannelEvent(nv_dev->pDevice, nv_prime_fence_context->cb); + + /* Force signal all pending fences and empty pending list */ + spin_lock(&nv_prime_fence_context->lock); + + nv_drm_gem_prime_force_fence_signal(nv_prime_fence_context); + + spin_unlock(&nv_prime_fence_context->lock); + + /* Free nvkms resources */ + + nvKms->unmapMemory(nv_dev->pDevice, + nv_prime_fence_context->pSemSurface, + NVKMS_KAPI_MAPPING_TYPE_KERNEL, + (void *) nv_prime_fence_context->pLinearAddress); + + nvKms->freeMemory(nv_dev->pDevice, nv_prime_fence_context->pSemSurface); + + nv_drm_free(nv_fence_context); +} + +static struct nv_drm_fence_context_ops nv_drm_prime_fence_context_ops = { + .destroy = __nv_drm_prime_fence_context_destroy, +}; + +static inline struct nv_drm_prime_fence_context * +__nv_drm_prime_fence_context_new( + struct nv_drm_device *nv_dev, + struct drm_nvidia_prime_fence_context_create_params *p) +{ + struct nv_drm_prime_fence_context *nv_prime_fence_context; + struct NvKmsKapiMemory *pSemSurface; + NvU32 *pLinearAddress; + + /* Allocate backup nvkms resources */ + + pSemSurface = nvKms->importMemory(nv_dev->pDevice, + p->size, + p->import_mem_nvkms_params_ptr, + p->import_mem_nvkms_params_size); + if (!pSemSurface) { + NV_DRM_DEV_LOG_ERR( + nv_dev, + "Failed to import fence semaphore surface"); + + goto failed; + } + + if (!nvKms->mapMemory(nv_dev->pDevice, + pSemSurface, + NVKMS_KAPI_MAPPING_TYPE_KERNEL, + (void **) &pLinearAddress)) { + NV_DRM_DEV_LOG_ERR( + nv_dev, + "Failed to map fence semaphore surface"); + + goto failed_to_map_memory; + } + + /* + * Allocate a fence context object, initialize it and allocate channel + * event for it. + */ + + if ((nv_prime_fence_context = nv_drm_calloc( + 1, + sizeof(*nv_prime_fence_context))) == NULL) { + goto failed_alloc_fence_context; + } + + /* + * nv_dma_fence_context_alloc() cannot fail, so we do not need + * to check a return value. + */ + + *nv_prime_fence_context = (struct nv_drm_prime_fence_context) { + .base.ops = &nv_drm_prime_fence_context_ops, + .base.nv_dev = nv_dev, + .base.context = nv_dma_fence_context_alloc(1), + .pSemSurface = pSemSurface, + .pLinearAddress = pLinearAddress, + .fenceSemIndex = p->index, + }; + + INIT_LIST_HEAD(&nv_prime_fence_context->pending); + + spin_lock_init(&nv_prime_fence_context->lock); + + /* + * Except 'cb', the fence context should be completely initialized + * before channel event allocation because the fence context may start + * receiving events immediately after allocation. + * + * There are no simultaneous read/write access to 'cb', therefore it does + * not require spin-lock protection. + */ + nv_prime_fence_context->cb = + nvKms->allocateChannelEvent(nv_dev->pDevice, + nv_drm_gem_prime_fence_event, + nv_prime_fence_context, + p->event_nvkms_params_ptr, + p->event_nvkms_params_size); + if (!nv_prime_fence_context->cb) { + NV_DRM_DEV_LOG_ERR(nv_dev, + "Failed to allocate fence signaling event"); + goto failed_to_allocate_channel_event; + } + + return nv_prime_fence_context; + +failed_to_allocate_channel_event: + nv_drm_free(nv_prime_fence_context); + +failed_alloc_fence_context: + + nvKms->unmapMemory(nv_dev->pDevice, + pSemSurface, + NVKMS_KAPI_MAPPING_TYPE_KERNEL, + (void *) pLinearAddress); + +failed_to_map_memory: + nvKms->freeMemory(nv_dev->pDevice, pSemSurface); + +failed: + return NULL; +} + +static nv_dma_fence_t *__nv_drm_prime_fence_context_create_fence( + struct nv_drm_prime_fence_context *nv_prime_fence_context, + unsigned int seqno) +{ + struct nv_drm_prime_fence *nv_fence; + int ret = 0; + + if ((nv_fence = nv_drm_calloc(1, sizeof(*nv_fence))) == NULL) { + ret = -ENOMEM; + goto out; + } + + spin_lock(&nv_prime_fence_context->lock); + + /* + * If seqno wrapped, force signal fences to make sure none of them + * get stuck. + */ + if (seqno < nv_prime_fence_context->last_seqno) { + nv_drm_gem_prime_force_fence_signal(nv_prime_fence_context); + } + + INIT_LIST_HEAD(&nv_fence->list_entry); + + spin_lock_init(&nv_fence->lock); + + nv_dma_fence_init(&nv_fence->base, &nv_drm_gem_prime_fence_ops, + &nv_fence->lock, nv_prime_fence_context->base.context, + seqno); + + /* The context maintains a reference to any pending fences. */ + nv_dma_fence_get(&nv_fence->base); + + list_add_tail(&nv_fence->list_entry, &nv_prime_fence_context->pending); + + nv_prime_fence_context->last_seqno = seqno; + + spin_unlock(&nv_prime_fence_context->lock); + +out: + return ret != 0 ? ERR_PTR(ret) : &nv_fence->base; +} + +int nv_drm_fence_supported_ioctl(struct drm_device *dev, + void *data, struct drm_file *filep) +{ + struct nv_drm_device *nv_dev = to_nv_device(dev); + return nv_dev->pDevice ? 0 : -EINVAL; +} + +struct nv_drm_gem_fence_context { + struct nv_drm_gem_object base; + struct nv_drm_fence_context *nv_fence_context; +}; + +static inline struct nv_drm_gem_fence_context *to_gem_fence_context( + struct nv_drm_gem_object *nv_gem) +{ + if (nv_gem != NULL) { + return container_of(nv_gem, struct nv_drm_gem_fence_context, base); + } + + return NULL; +} + +/* + * Tear down of the 'struct nv_drm_gem_fence_context' object is not expected + * to be happen from any worker thread, if that happen it causes dead-lock + * because tear down sequence calls to flush all existing + * worker thread. + */ +static void +__nv_drm_gem_fence_context_free(struct nv_drm_gem_object *nv_gem) +{ + struct nv_drm_gem_fence_context *nv_gem_fence_context = + to_gem_fence_context(nv_gem); + struct nv_drm_fence_context *nv_fence_context = + nv_gem_fence_context->nv_fence_context; + + nv_fence_context->ops->destroy(nv_fence_context); + + nv_drm_free(nv_gem_fence_context); +} + +const struct nv_drm_gem_object_funcs nv_gem_fence_context_ops = { + .free = __nv_drm_gem_fence_context_free, +}; + +static inline +struct nv_drm_gem_fence_context * +__nv_drm_gem_object_fence_context_lookup( + struct drm_device *dev, + struct drm_file *filp, + u32 handle) +{ + struct nv_drm_gem_object *nv_gem = + nv_drm_gem_object_lookup(dev, filp, handle); + + if (nv_gem != NULL && nv_gem->ops != &nv_gem_fence_context_ops) { + nv_drm_gem_object_unreference_unlocked(nv_gem); + return NULL; + } + + return to_gem_fence_context(nv_gem); +} + +static int +__nv_drm_gem_fence_context_create(struct drm_device *dev, + struct nv_drm_fence_context *nv_fence_context, + u32 *handle, + struct drm_file *filep) +{ + struct nv_drm_device *nv_dev = to_nv_device(dev); + struct nv_drm_gem_fence_context *nv_gem_fence_context = NULL; + + if ((nv_gem_fence_context = nv_drm_calloc( + 1, + sizeof(struct nv_drm_gem_fence_context))) == NULL) { + goto done; + } + + nv_gem_fence_context->nv_fence_context = nv_fence_context; + + nv_drm_gem_object_init(nv_dev, + &nv_gem_fence_context->base, + &nv_gem_fence_context_ops, + 0 /* size */, + NULL /* pMemory */); + + return nv_drm_gem_handle_create_drop_reference(filep, + &nv_gem_fence_context->base, + handle); + +done: + return -ENOMEM; +} + +int nv_drm_prime_fence_context_create_ioctl(struct drm_device *dev, + void *data, struct drm_file *filep) +{ + struct nv_drm_device *nv_dev = to_nv_device(dev); + struct drm_nvidia_prime_fence_context_create_params *p = data; + struct nv_drm_prime_fence_context *nv_prime_fence_context = + __nv_drm_prime_fence_context_new(nv_dev, p); + int err; + + if (!nv_prime_fence_context) { + goto done; + } + + err = __nv_drm_gem_fence_context_create(dev, + &nv_prime_fence_context->base, + &p->handle, + filep); + if (err) { + __nv_drm_prime_fence_context_destroy(&nv_prime_fence_context->base); + } + + return err; + +done: + return -ENOMEM; +} + +int nv_drm_gem_prime_fence_attach_ioctl(struct drm_device *dev, + void *data, struct drm_file *filep) +{ + int ret = -EINVAL; + struct nv_drm_device *nv_dev = to_nv_device(dev); + struct drm_nvidia_gem_prime_fence_attach_params *p = data; + + struct nv_drm_gem_object *nv_gem; + struct nv_drm_gem_fence_context *nv_gem_fence_context; + + nv_dma_fence_t *fence; + nv_dma_resv_t *resv; + + nv_gem = nv_drm_gem_object_lookup(nv_dev->dev, filep, p->handle); + + if (!nv_gem) { + NV_DRM_DEV_LOG_ERR( + nv_dev, + "Failed to lookup gem object for fence attach: 0x%08x", + p->handle); + + goto done; + } + + if((nv_gem_fence_context = __nv_drm_gem_object_fence_context_lookup( + nv_dev->dev, + filep, + p->fence_context_handle)) == NULL) { + + NV_DRM_DEV_LOG_ERR( + nv_dev, + "Failed to lookup gem object for fence context: 0x%08x", + p->fence_context_handle); + + goto fence_context_lookup_failed; + } + + if (nv_gem_fence_context->nv_fence_context->ops != + &nv_drm_prime_fence_context_ops) { + + NV_DRM_DEV_LOG_ERR( + nv_dev, + "Wrong fence context type: 0x%08x", + p->fence_context_handle); + + goto fence_context_create_fence_failed; + } + + fence = __nv_drm_prime_fence_context_create_fence( + to_prime_fence_context(nv_gem_fence_context->nv_fence_context), + p->sem_thresh); + + if (IS_ERR(fence)) { + ret = PTR_ERR(fence); + + NV_DRM_DEV_LOG_ERR( + nv_dev, + "Failed to allocate fence: 0x%08x", p->handle); + + goto fence_context_create_fence_failed; + } + + resv = nv_drm_gem_res_obj(nv_gem); + + nv_dma_resv_lock(resv, NULL); + + ret = nv_dma_resv_reserve_fences(resv, 1, false); + if (ret == 0) { + nv_dma_resv_add_excl_fence(resv, fence); + } else { + NV_DRM_DEV_LOG_ERR( + nv_dev, + "Failed to reserve fence. Error code: %d", ret); + } + + nv_dma_resv_unlock(resv); + + /* dma_resv_add_excl_fence takes its own reference to the fence. */ + nv_dma_fence_put(fence); + +fence_context_create_fence_failed: + nv_drm_gem_object_unreference_unlocked(&nv_gem_fence_context->base); + +fence_context_lookup_failed: + nv_drm_gem_object_unreference_unlocked(nv_gem); + +done: + return ret; +} + +#endif /* NV_DRM_FENCE_AVAILABLE */ + +#endif /* NV_DRM_AVAILABLE */ diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/kernel-open/nvidia-drm/nvidia-drm-fence.h nvidia-open-gpu-kernel-modules-535.161.08/kernel-open/nvidia-drm/nvidia-drm-fence.h --- nvidia-open-gpu-kernel-modules-525.147.05/kernel-open/nvidia-drm/nvidia-drm-fence.h 1970-01-01 00:00:00.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/kernel-open/nvidia-drm/nvidia-drm-fence.h 2024-03-05 22:14:10.000000000 +0000 @@ -0,0 +1,48 @@ +/* + * Copyright (c) 2016, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef __NVIDIA_DRM_PRIME_FENCE_H__ +#define __NVIDIA_DRM_PRIME_FENCE_H__ + +#include "nvidia-drm-conftest.h" + +#if defined(NV_DRM_AVAILABLE) + +struct drm_file; +struct drm_device; + +#if defined(NV_DRM_FENCE_AVAILABLE) + +int nv_drm_fence_supported_ioctl(struct drm_device *dev, + void *data, struct drm_file *filep); + +int nv_drm_prime_fence_context_create_ioctl(struct drm_device *dev, + void *data, struct drm_file *filep); + +int nv_drm_gem_prime_fence_attach_ioctl(struct drm_device *dev, + void *data, struct drm_file *filep); + +#endif /* NV_DRM_FENCE_AVAILABLE */ + +#endif /* NV_DRM_AVAILABLE */ + +#endif /* __NVIDIA_DRM_PRIME_FENCE_H__ */ diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/kernel-open/nvidia-drm/nvidia-drm-gem-nvkms-memory.c nvidia-open-gpu-kernel-modules-535.161.08/kernel-open/nvidia-drm/nvidia-drm-gem-nvkms-memory.c --- nvidia-open-gpu-kernel-modules-525.147.05/kernel-open/nvidia-drm/nvidia-drm-gem-nvkms-memory.c 2023-10-25 20:25:17.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/kernel-open/nvidia-drm/nvidia-drm-gem-nvkms-memory.c 2024-03-05 22:14:11.000000000 +0000 @@ -131,11 +131,11 @@ const struct nv_drm_gem_object *nv_gem_src); static int __nv_drm_gem_nvkms_map( - struct nv_drm_device *nv_dev, - struct NvKmsKapiMemory *pMemory, - struct nv_drm_gem_nvkms_memory *nv_nvkms_memory, - uint64_t size) + struct nv_drm_gem_nvkms_memory *nv_nvkms_memory) { + struct nv_drm_device *nv_dev = nv_nvkms_memory->base.nv_dev; + struct NvKmsKapiMemory *pMemory = nv_nvkms_memory->base.pMemory; + if (!nv_dev->hasVideoMemory) { return 0; } @@ -153,7 +153,7 @@ nv_nvkms_memory->pWriteCombinedIORemapAddress = ioremap_wc( (uintptr_t)nv_nvkms_memory->pPhysicalAddress, - size); + nv_nvkms_memory->base.base.size); if (!nv_nvkms_memory->pWriteCombinedIORemapAddress) { NV_DRM_DEV_LOG_INFO( @@ -167,6 +167,22 @@ return 0; } +static void *__nv_drm_gem_nvkms_prime_vmap( + struct nv_drm_gem_object *nv_gem) +{ + struct nv_drm_gem_nvkms_memory *nv_nvkms_memory = + to_nv_nvkms_memory(nv_gem); + + if (!nv_nvkms_memory->physically_mapped) { + int ret = __nv_drm_gem_nvkms_map(nv_nvkms_memory); + if (ret) { + return ERR_PTR(ret); + } + } + + return nv_nvkms_memory->pWriteCombinedIORemapAddress; +} + static int __nv_drm_gem_map_nvkms_memory_offset( struct nv_drm_device *nv_dev, struct nv_drm_gem_object *nv_gem, @@ -176,10 +192,7 @@ to_nv_nvkms_memory(nv_gem); if (!nv_nvkms_memory->physically_mapped) { - int ret = __nv_drm_gem_nvkms_map(nv_dev, - nv_nvkms_memory->base.pMemory, - nv_nvkms_memory, - nv_nvkms_memory->base.base.size); + int ret = __nv_drm_gem_nvkms_map(nv_nvkms_memory); if (ret) { return ret; } @@ -214,6 +227,7 @@ const struct nv_drm_gem_object_funcs nv_gem_nvkms_memory_ops = { .free = __nv_drm_gem_nvkms_memory_free, .prime_dup = __nv_drm_gem_nvkms_prime_dup, + .prime_vmap = __nv_drm_gem_nvkms_prime_vmap, .mmap = __nv_drm_gem_nvkms_mmap, .handle_vma_fault = __nv_drm_gem_nvkms_handle_vma_fault, .create_mmap_offset = __nv_drm_gem_map_nvkms_memory_offset, @@ -229,6 +243,15 @@ NvU64 *pages = NULL; NvU32 numPages = 0; + if ((size % PAGE_SIZE) != 0) { + NV_DRM_DEV_LOG_ERR( + nv_dev, + "NvKmsKapiMemory 0x%p size should be in a multiple of page size to " + "create a gem object", + pMemory); + return -EINVAL; + } + nv_nvkms_memory->pPhysicalAddress = NULL; nv_nvkms_memory->pWriteCombinedIORemapAddress = NULL; nv_nvkms_memory->physically_mapped = false; @@ -314,7 +337,7 @@ * to use dumb buffers for software rendering, so they're not much use * without a CPU mapping. */ - ret = __nv_drm_gem_nvkms_map(nv_dev, pMemory, nv_nvkms_memory, args->size); + ret = __nv_drm_gem_nvkms_map(nv_nvkms_memory); if (ret) { nv_drm_gem_object_unreference_unlocked(&nv_nvkms_memory->base); goto fail; diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/kernel-open/nvidia-drm/nvidia-drm-gem.c nvidia-open-gpu-kernel-modules-535.161.08/kernel-open/nvidia-drm/nvidia-drm-gem.c --- nvidia-open-gpu-kernel-modules-525.147.05/kernel-open/nvidia-drm/nvidia-drm-gem.c 2023-10-25 20:25:17.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/kernel-open/nvidia-drm/nvidia-drm-gem.c 2024-03-05 22:14:11.000000000 +0000 @@ -26,7 +26,7 @@ #include "nvidia-drm-priv.h" #include "nvidia-drm-ioctl.h" -#include "nvidia-drm-prime-fence.h" +#include "nvidia-drm-fence.h" #include "nvidia-drm-gem.h" #include "nvidia-drm-gem-nvkms-memory.h" #include "nvidia-drm-gem-user-memory.h" @@ -81,10 +81,13 @@ static int nv_drm_gem_vmap(struct drm_gem_object *gem, nv_sysio_map_t *map) { - map->vaddr = nv_drm_gem_prime_vmap(gem); - if (map->vaddr == NULL) { + void *vaddr = nv_drm_gem_prime_vmap(gem); + if (vaddr == NULL) { return -ENOMEM; + } else if (IS_ERR(vaddr)) { + return PTR_ERR(vaddr); } + map->vaddr = vaddr; map->is_iomem = true; return 0; } @@ -132,13 +135,8 @@ /* Initialize the gem object */ -#if defined(NV_DRM_FENCE_AVAILABLE) +#if defined(NV_DRM_FENCE_AVAILABLE) && !defined(NV_DRM_GEM_OBJECT_HAS_RESV) nv_dma_resv_init(&nv_gem->resv); - -#if defined(NV_DRM_GEM_OBJECT_HAS_RESV) - nv_gem->base.resv = &nv_gem->resv; -#endif - #endif #if !defined(NV_DRM_DRIVER_HAS_GEM_FREE_OBJECT) @@ -212,8 +210,7 @@ nv_dma_resv_t* nv_drm_gem_prime_res_obj(struct drm_gem_object *obj) { struct nv_drm_gem_object *nv_gem = to_nv_gem_object(obj); - - return &nv_gem->resv; + return nv_drm_gem_res_obj(nv_gem); } #endif diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/kernel-open/nvidia-drm/nvidia-drm-gem.h nvidia-open-gpu-kernel-modules-535.161.08/kernel-open/nvidia-drm/nvidia-drm-gem.h --- nvidia-open-gpu-kernel-modules-525.147.05/kernel-open/nvidia-drm/nvidia-drm-gem.h 2023-10-25 20:25:16.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/kernel-open/nvidia-drm/nvidia-drm-gem.h 2024-03-05 22:14:10.000000000 +0000 @@ -45,6 +45,8 @@ #include "nvidia-dma-resv-helper.h" #endif +#include "linux/dma-buf.h" + struct nv_drm_gem_object; struct nv_drm_gem_object_funcs { @@ -71,7 +73,7 @@ struct NvKmsKapiMemory *pMemory; -#if defined(NV_DRM_FENCE_AVAILABLE) +#if defined(NV_DRM_FENCE_AVAILABLE) && !defined(NV_DRM_GEM_OBJECT_HAS_RESV) nv_dma_resv_t resv; #endif }; @@ -177,6 +179,17 @@ return drm_gem_handle_create(filp, &nv_gem->base, handle); } +#if defined(NV_DRM_FENCE_AVAILABLE) +static inline nv_dma_resv_t *nv_drm_gem_res_obj(struct nv_drm_gem_object *nv_gem) +{ +#if defined(NV_DRM_GEM_OBJECT_HAS_RESV) + return nv_gem->base.resv; +#else + return nv_gem->base.dma_buf ? nv_gem->base.dma_buf->resv : &nv_gem->resv; +#endif +} +#endif + void nv_drm_gem_object_init(struct nv_drm_device *nv_dev, struct nv_drm_gem_object *nv_gem, const struct nv_drm_gem_object_funcs * const ops, diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/kernel-open/nvidia-drm/nvidia-drm-helper.c nvidia-open-gpu-kernel-modules-535.161.08/kernel-open/nvidia-drm/nvidia-drm-helper.c --- nvidia-open-gpu-kernel-modules-525.147.05/kernel-open/nvidia-drm/nvidia-drm-helper.c 2023-10-25 20:25:17.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/kernel-open/nvidia-drm/nvidia-drm-helper.c 2024-03-05 22:14:11.000000000 +0000 @@ -28,6 +28,8 @@ */ #include "nvidia-drm-helper.h" +#include "nvidia-drm-priv.h" +#include "nvidia-drm-crtc.h" #include "nvmisc.h" @@ -148,6 +150,18 @@ goto free; } +#if defined(NV_DRM_ROTATION_AVAILABLE) + nv_drm_for_each_plane(plane, dev) { + plane_state = drm_atomic_get_plane_state(state, plane); + if (IS_ERR(plane_state)) { + ret = PTR_ERR(plane_state); + goto free; + } + + plane_state->rotation = DRM_MODE_ROTATE_0; + } +#endif + nv_drm_for_each_connector_in_state(state, conn, conn_state, i) { ret = drm_atomic_set_crtc_for_connector(conn_state, NULL); if (ret < 0) diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/kernel-open/nvidia-drm/nvidia-drm-helper.h nvidia-open-gpu-kernel-modules-535.161.08/kernel-open/nvidia-drm/nvidia-drm-helper.h --- nvidia-open-gpu-kernel-modules-525.147.05/kernel-open/nvidia-drm/nvidia-drm-helper.h 2023-10-25 20:25:15.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/kernel-open/nvidia-drm/nvidia-drm-helper.h 2024-03-05 22:14:09.000000000 +0000 @@ -35,6 +35,35 @@ #include #endif +#if defined(NV_DRM_ALPHA_BLENDING_AVAILABLE) || defined(NV_DRM_ROTATION_AVAILABLE) +/* For DRM_ROTATE_* , DRM_REFLECT_* */ +#include +#endif + +#if defined(NV_DRM_ROTATION_AVAILABLE) +/* For DRM_MODE_ROTATE_* and DRM_MODE_REFLECT_* */ +#include +#endif + +#if defined(NV_DRM_ROTATION_AVAILABLE) +/* + * 19-05-2017 c2c446ad29437bb92b157423c632286608ebd3ec has added + * DRM_MODE_ROTATE_* and DRM_MODE_REFLECT_* to UAPI and removed + * DRM_ROTATE_* and DRM_REFLECT_* + */ +#if !defined(DRM_MODE_ROTATE_0) +#define DRM_MODE_ROTATE_0 DRM_ROTATE_0 +#define DRM_MODE_ROTATE_90 DRM_ROTATE_90 +#define DRM_MODE_ROTATE_180 DRM_ROTATE_180 +#define DRM_MODE_ROTATE_270 DRM_ROTATE_270 +#define DRM_MODE_REFLECT_X DRM_REFLECT_X +#define DRM_MODE_REFLECT_Y DRM_REFLECT_Y +#define DRM_MODE_ROTATE_MASK DRM_ROTATE_MASK +#define DRM_MODE_REFLECT_MASK DRM_REFLECT_MASK +#endif + +#endif //NV_DRM_ROTATION_AVAILABLE + /* * drm_dev_put() is added by commit 9a96f55034e41b4e002b767e9218d55f03bdff7d * (2017-09-26) and drm_dev_unref() is removed by @@ -277,11 +306,33 @@ for_each_plane_in_state(__state, plane, plane_state, __i) #endif -static inline struct drm_crtc *nv_drm_crtc_find(struct drm_device *dev, - uint32_t id) +static inline struct drm_connector * +nv_drm_connector_lookup(struct drm_device *dev, struct drm_file *filep, + uint32_t id) +{ +#if !defined(NV_DRM_CONNECTOR_LOOKUP_PRESENT) + return drm_connector_find(dev, id); +#elif defined(NV_DRM_MODE_OBJECT_FIND_HAS_FILE_PRIV_ARG) + return drm_connector_lookup(dev, filep, id); +#else + return drm_connector_lookup(dev, id); +#endif +} + +static inline void nv_drm_connector_put(struct drm_connector *connector) +{ +#if defined(NV_DRM_CONNECTOR_PUT_PRESENT) + drm_connector_put(connector); +#elif defined(NV_DRM_CONNECTOR_LOOKUP_PRESENT) + drm_connector_unreference(connector); +#endif +} + +static inline struct drm_crtc * +nv_drm_crtc_find(struct drm_device *dev, struct drm_file *filep, uint32_t id) { #if defined(NV_DRM_MODE_OBJECT_FIND_HAS_FILE_PRIV_ARG) - return drm_crtc_find(dev, NULL /* file_priv */, id); + return drm_crtc_find(dev, filep, id); #else return drm_crtc_find(dev, id); #endif @@ -297,6 +348,30 @@ #endif } +#if defined(NV_DRM_DRM_AUTH_H_PRESENT) +#include +#endif +#if defined(NV_DRM_DRM_FILE_H_PRESENT) +#include +#endif + +/* + * drm_file_get_master() added by commit 56f0729a510f ("drm: protect drm_master + * pointers in drm_lease.c") in v5.15 (2021-07-20) + */ +static inline struct drm_master *nv_drm_file_get_master(struct drm_file *filep) +{ +#if defined(NV_DRM_FILE_GET_MASTER_PRESENT) + return drm_file_get_master(filep); +#else + if (filep->master) { + return drm_master_get(filep->master); + } else { + return NULL; + } +#endif +} + /* * drm_connector_for_each_possible_encoder() is added by commit * 83aefbb887b59df0b3520965c3701e01deacfc52 which was Signed-off-by: @@ -508,6 +583,19 @@ #endif /* defined(NV_DRM_FORMAT_MODIFIERS_PRESENT) */ /* + * DRM_UNLOCKED was removed with linux-next commit 2798ffcc1d6a ("drm: Remove + * locking for legacy ioctls and DRM_UNLOCKED"), but it was previously made + * implicit for all non-legacy DRM driver IOCTLs since Linux v4.10 commit + * fa5386459f06 "drm: Used DRM_LEGACY for all legacy functions" (Linux v4.4 + * commit ea487835e887 "drm: Enforce unlocked ioctl operation for kms driver + * ioctls" previously did it only for drivers that set the DRM_MODESET flag), so + * it was effectively a no-op anyway. + */ +#if !defined(NV_DRM_UNLOCKED_IOCTL_FLAG_PRESENT) +#define DRM_UNLOCKED 0 +#endif + +/* * drm_vma_offset_exact_lookup_locked() were added * by kernel commit 2225cfe46bcc which was Signed-off-by: * Daniel Vetter diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/kernel-open/nvidia-drm/nvidia-drm-ioctl.h nvidia-open-gpu-kernel-modules-535.161.08/kernel-open/nvidia-drm/nvidia-drm-ioctl.h --- nvidia-open-gpu-kernel-modules-525.147.05/kernel-open/nvidia-drm/nvidia-drm-ioctl.h 2023-10-25 20:25:17.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/kernel-open/nvidia-drm/nvidia-drm-ioctl.h 2024-03-05 22:14:10.000000000 +0000 @@ -34,8 +34,8 @@ #define DRM_NVIDIA_GEM_IMPORT_USERSPACE_MEMORY 0x02 #define DRM_NVIDIA_GET_DEV_INFO 0x03 #define DRM_NVIDIA_FENCE_SUPPORTED 0x04 -#define DRM_NVIDIA_FENCE_CONTEXT_CREATE 0x05 -#define DRM_NVIDIA_GEM_FENCE_ATTACH 0x06 +#define DRM_NVIDIA_PRIME_FENCE_CONTEXT_CREATE 0x05 +#define DRM_NVIDIA_GEM_PRIME_FENCE_ATTACH 0x06 #define DRM_NVIDIA_GET_CLIENT_CAPABILITY 0x08 #define DRM_NVIDIA_GEM_EXPORT_NVKMS_MEMORY 0x09 #define DRM_NVIDIA_GEM_MAP_OFFSET 0x0a @@ -43,6 +43,11 @@ #define DRM_NVIDIA_GET_CRTC_CRC32_V2 0x0c #define DRM_NVIDIA_GEM_EXPORT_DMABUF_MEMORY 0x0d #define DRM_NVIDIA_GEM_IDENTIFY_OBJECT 0x0e +#define DRM_NVIDIA_DMABUF_SUPPORTED 0x0f +#define DRM_NVIDIA_GET_DPY_ID_FOR_CONNECTOR_ID 0x10 +#define DRM_NVIDIA_GET_CONNECTOR_ID_FOR_DPY_ID 0x11 +#define DRM_NVIDIA_GRANT_PERMISSIONS 0x12 +#define DRM_NVIDIA_REVOKE_PERMISSIONS 0x13 #define DRM_IOCTL_NVIDIA_GEM_IMPORT_NVKMS_MEMORY \ DRM_IOWR((DRM_COMMAND_BASE + DRM_NVIDIA_GEM_IMPORT_NVKMS_MEMORY), \ @@ -65,50 +70,69 @@ #if defined(NV_LINUX) #define DRM_IOCTL_NVIDIA_FENCE_SUPPORTED \ DRM_IO(DRM_COMMAND_BASE + DRM_NVIDIA_FENCE_SUPPORTED) +#define DRM_IOCTL_NVIDIA_DMABUF_SUPPORTED \ + DRM_IO(DRM_COMMAND_BASE + DRM_NVIDIA_DMABUF_SUPPORTED) #else #define DRM_IOCTL_NVIDIA_FENCE_SUPPORTED 0 +#define DRM_IOCTL_NVIDIA_DMABUF_SUPPORTED 0 #endif -#define DRM_IOCTL_NVIDIA_FENCE_CONTEXT_CREATE \ - DRM_IOWR((DRM_COMMAND_BASE + DRM_NVIDIA_FENCE_CONTEXT_CREATE), \ - struct drm_nvidia_fence_context_create_params) - -#define DRM_IOCTL_NVIDIA_GEM_FENCE_ATTACH \ - DRM_IOW((DRM_COMMAND_BASE + DRM_NVIDIA_GEM_FENCE_ATTACH), \ - struct drm_nvidia_gem_fence_attach_params) +#define DRM_IOCTL_NVIDIA_PRIME_FENCE_CONTEXT_CREATE \ + DRM_IOWR((DRM_COMMAND_BASE + DRM_NVIDIA_PRIME_FENCE_CONTEXT_CREATE),\ + struct drm_nvidia_prime_fence_context_create_params) + +#define DRM_IOCTL_NVIDIA_GEM_PRIME_FENCE_ATTACH \ + DRM_IOW((DRM_COMMAND_BASE + DRM_NVIDIA_GEM_PRIME_FENCE_ATTACH), \ + struct drm_nvidia_gem_prime_fence_attach_params) -#define DRM_IOCTL_NVIDIA_GET_CLIENT_CAPABILITY \ - DRM_IOWR((DRM_COMMAND_BASE + DRM_NVIDIA_GET_CLIENT_CAPABILITY), \ +#define DRM_IOCTL_NVIDIA_GET_CLIENT_CAPABILITY \ + DRM_IOWR((DRM_COMMAND_BASE + DRM_NVIDIA_GET_CLIENT_CAPABILITY), \ struct drm_nvidia_get_client_capability_params) -#define DRM_IOCTL_NVIDIA_GET_CRTC_CRC32 \ - DRM_IOWR((DRM_COMMAND_BASE + DRM_NVIDIA_GET_CRTC_CRC32), \ +#define DRM_IOCTL_NVIDIA_GET_CRTC_CRC32 \ + DRM_IOWR((DRM_COMMAND_BASE + DRM_NVIDIA_GET_CRTC_CRC32), \ struct drm_nvidia_get_crtc_crc32_params) -#define DRM_IOCTL_NVIDIA_GET_CRTC_CRC32_V2 \ - DRM_IOWR((DRM_COMMAND_BASE + DRM_NVIDIA_GET_CRTC_CRC32_V2), \ +#define DRM_IOCTL_NVIDIA_GET_CRTC_CRC32_V2 \ + DRM_IOWR((DRM_COMMAND_BASE + DRM_NVIDIA_GET_CRTC_CRC32_V2), \ struct drm_nvidia_get_crtc_crc32_v2_params) -#define DRM_IOCTL_NVIDIA_GEM_EXPORT_NVKMS_MEMORY \ - DRM_IOWR((DRM_COMMAND_BASE + DRM_NVIDIA_GEM_EXPORT_NVKMS_MEMORY), \ +#define DRM_IOCTL_NVIDIA_GEM_EXPORT_NVKMS_MEMORY \ + DRM_IOWR((DRM_COMMAND_BASE + DRM_NVIDIA_GEM_EXPORT_NVKMS_MEMORY), \ struct drm_nvidia_gem_export_nvkms_memory_params) -#define DRM_IOCTL_NVIDIA_GEM_MAP_OFFSET \ - DRM_IOWR((DRM_COMMAND_BASE + DRM_NVIDIA_GEM_MAP_OFFSET), \ +#define DRM_IOCTL_NVIDIA_GEM_MAP_OFFSET \ + DRM_IOWR((DRM_COMMAND_BASE + DRM_NVIDIA_GEM_MAP_OFFSET), \ struct drm_nvidia_gem_map_offset_params) -#define DRM_IOCTL_NVIDIA_GEM_ALLOC_NVKMS_MEMORY \ - DRM_IOWR((DRM_COMMAND_BASE + DRM_NVIDIA_GEM_ALLOC_NVKMS_MEMORY), \ +#define DRM_IOCTL_NVIDIA_GEM_ALLOC_NVKMS_MEMORY \ + DRM_IOWR((DRM_COMMAND_BASE + DRM_NVIDIA_GEM_ALLOC_NVKMS_MEMORY), \ struct drm_nvidia_gem_alloc_nvkms_memory_params) -#define DRM_IOCTL_NVIDIA_GEM_EXPORT_DMABUF_MEMORY \ - DRM_IOWR((DRM_COMMAND_BASE + DRM_NVIDIA_GEM_EXPORT_DMABUF_MEMORY), \ +#define DRM_IOCTL_NVIDIA_GEM_EXPORT_DMABUF_MEMORY \ + DRM_IOWR((DRM_COMMAND_BASE + DRM_NVIDIA_GEM_EXPORT_DMABUF_MEMORY), \ struct drm_nvidia_gem_export_dmabuf_memory_params) -#define DRM_IOCTL_NVIDIA_GEM_IDENTIFY_OBJECT \ - DRM_IOWR((DRM_COMMAND_BASE + DRM_NVIDIA_GEM_IDENTIFY_OBJECT), \ +#define DRM_IOCTL_NVIDIA_GEM_IDENTIFY_OBJECT \ + DRM_IOWR((DRM_COMMAND_BASE + DRM_NVIDIA_GEM_IDENTIFY_OBJECT), \ struct drm_nvidia_gem_identify_object_params) +#define DRM_IOCTL_NVIDIA_GET_DPY_ID_FOR_CONNECTOR_ID \ + DRM_IOWR((DRM_COMMAND_BASE + DRM_NVIDIA_GET_DPY_ID_FOR_CONNECTOR_ID),\ + struct drm_nvidia_get_dpy_id_for_connector_id_params) + +#define DRM_IOCTL_NVIDIA_GET_CONNECTOR_ID_FOR_DPY_ID \ + DRM_IOWR((DRM_COMMAND_BASE + DRM_NVIDIA_GET_CONNECTOR_ID_FOR_DPY_ID),\ + struct drm_nvidia_get_connector_id_for_dpy_id_params) + +#define DRM_IOCTL_NVIDIA_GRANT_PERMISSIONS \ + DRM_IOWR((DRM_COMMAND_BASE + DRM_NVIDIA_GRANT_PERMISSIONS), \ + struct drm_nvidia_grant_permissions_params) + +#define DRM_IOCTL_NVIDIA_REVOKE_PERMISSIONS \ + DRM_IOWR((DRM_COMMAND_BASE + DRM_NVIDIA_REVOKE_PERMISSIONS), \ + struct drm_nvidia_revoke_permissions_params) + struct drm_nvidia_gem_import_nvkms_memory_params { uint64_t mem_size; /* IN */ @@ -136,7 +160,7 @@ uint32_t sector_layout; /* OUT */ }; -struct drm_nvidia_fence_context_create_params { +struct drm_nvidia_prime_fence_context_create_params { uint32_t handle; /* OUT GEM handle to fence context */ uint32_t index; /* IN Index of semaphore to use for fencing */ @@ -151,7 +175,7 @@ uint64_t event_nvkms_params_size; /* IN */ }; -struct drm_nvidia_gem_fence_attach_params { +struct drm_nvidia_gem_prime_fence_attach_params { uint32_t handle; /* IN GEM handle to attach fence to */ uint32_t fence_context_handle; /* IN GEM handle to fence context on which fence is run on */ uint32_t sem_thresh; /* IN Semaphore value to reach before signal */ @@ -232,4 +256,23 @@ drm_nvidia_gem_object_type object_type; /* OUT GEM object type */ }; +struct drm_nvidia_get_dpy_id_for_connector_id_params { + uint32_t connectorId; /* IN */ + uint32_t dpyId; /* OUT */ +}; + +struct drm_nvidia_get_connector_id_for_dpy_id_params { + uint32_t dpyId; /* IN */ + uint32_t connectorId; /* OUT */ +}; + +struct drm_nvidia_grant_permissions_params { + int32_t fd; /* IN */ + uint32_t dpyId; /* IN */ +}; + +struct drm_nvidia_revoke_permissions_params { + uint32_t dpyId; /* IN */ +}; + #endif /* _UAPI_NVIDIA_DRM_IOCTL_H_ */ diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/kernel-open/nvidia-drm/nvidia-drm-prime-fence.c nvidia-open-gpu-kernel-modules-535.161.08/kernel-open/nvidia-drm/nvidia-drm-prime-fence.c --- nvidia-open-gpu-kernel-modules-525.147.05/kernel-open/nvidia-drm/nvidia-drm-prime-fence.c 2023-10-25 20:25:18.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/kernel-open/nvidia-drm/nvidia-drm-prime-fence.c 1970-01-01 00:00:00.000000000 +0000 @@ -1,533 +0,0 @@ -/* - * Copyright (c) 2016, NVIDIA CORPORATION. All rights reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER - * DEALINGS IN THE SOFTWARE. - */ - -#include "nvidia-drm-conftest.h" - -#if defined(NV_DRM_AVAILABLE) - -#if defined(NV_DRM_DRMP_H_PRESENT) -#include -#endif - -#include "nvidia-drm-priv.h" -#include "nvidia-drm-ioctl.h" -#include "nvidia-drm-gem.h" -#include "nvidia-drm-prime-fence.h" -#include "nvidia-dma-resv-helper.h" - -#if defined(NV_DRM_FENCE_AVAILABLE) - -#include "nvidia-dma-fence-helper.h" - -struct nv_drm_fence_context { - struct nv_drm_device *nv_dev; - - uint32_t context; - - NvU64 fenceSemIndex; /* Index into semaphore surface */ - - /* Mapped semaphore surface */ - struct NvKmsKapiMemory *pSemSurface; - NvU32 *pLinearAddress; - - /* Protects nv_drm_fence_context::{pending, last_seqno} */ - spinlock_t lock; - - /* - * Software signaling structures. __nv_drm_fence_context_new() - * allocates channel event and __nv_drm_fence_context_destroy() frees it. - * There are no simultaneous read/write access to 'cb', therefore it does - * not require spin-lock protection. - */ - struct NvKmsKapiChannelEvent *cb; - - /* List of pending fences which are not yet signaled */ - struct list_head pending; - - unsigned last_seqno; -}; - -struct nv_drm_prime_fence { - struct list_head list_entry; - nv_dma_fence_t base; - spinlock_t lock; -}; - -static inline -struct nv_drm_prime_fence *to_nv_drm_prime_fence(nv_dma_fence_t *fence) -{ - return container_of(fence, struct nv_drm_prime_fence, base); -} - -static const char* -nv_drm_gem_prime_fence_op_get_driver_name(nv_dma_fence_t *fence) -{ - return "NVIDIA"; -} - -static const char* -nv_drm_gem_prime_fence_op_get_timeline_name(nv_dma_fence_t *fence) -{ - return "nvidia.prime"; -} - -static bool nv_drm_gem_prime_fence_op_enable_signaling(nv_dma_fence_t *fence) -{ - // DO NOTHING - return true; -} - -static void nv_drm_gem_prime_fence_op_release(nv_dma_fence_t *fence) -{ - struct nv_drm_prime_fence *nv_fence = to_nv_drm_prime_fence(fence); - nv_drm_free(nv_fence); -} - -static signed long -nv_drm_gem_prime_fence_op_wait(nv_dma_fence_t *fence, - bool intr, signed long timeout) -{ - /* - * If the waiter requests to wait with no timeout, force a timeout to ensure - * that it won't get stuck forever in the kernel if something were to go - * wrong with signaling, such as a malicious userspace not releasing the - * semaphore. - * - * 96 ms (roughly 6 frames @ 60 Hz) is arbitrarily chosen to be long enough - * that it should never get hit during normal operation, but not so long - * that the system becomes unresponsive. - */ - return nv_dma_fence_default_wait(fence, intr, - (timeout == MAX_SCHEDULE_TIMEOUT) ? - msecs_to_jiffies(96) : timeout); -} - -static const nv_dma_fence_ops_t nv_drm_gem_prime_fence_ops = { - .get_driver_name = nv_drm_gem_prime_fence_op_get_driver_name, - .get_timeline_name = nv_drm_gem_prime_fence_op_get_timeline_name, - .enable_signaling = nv_drm_gem_prime_fence_op_enable_signaling, - .release = nv_drm_gem_prime_fence_op_release, - .wait = nv_drm_gem_prime_fence_op_wait, -}; - -static inline void -__nv_drm_prime_fence_signal(struct nv_drm_prime_fence *nv_fence) -{ - list_del(&nv_fence->list_entry); - nv_dma_fence_signal(&nv_fence->base); - nv_dma_fence_put(&nv_fence->base); -} - -static void nv_drm_gem_prime_force_fence_signal( - struct nv_drm_fence_context *nv_fence_context) -{ - WARN_ON(!spin_is_locked(&nv_fence_context->lock)); - - while (!list_empty(&nv_fence_context->pending)) { - struct nv_drm_prime_fence *nv_fence = list_first_entry( - &nv_fence_context->pending, - typeof(*nv_fence), - list_entry); - - __nv_drm_prime_fence_signal(nv_fence); - } -} - -static void nv_drm_gem_prime_fence_event -( - void *dataPtr, - NvU32 dataU32 -) -{ - struct nv_drm_fence_context *nv_fence_context = dataPtr; - - spin_lock(&nv_fence_context->lock); - - while (!list_empty(&nv_fence_context->pending)) { - struct nv_drm_prime_fence *nv_fence = list_first_entry( - &nv_fence_context->pending, - typeof(*nv_fence), - list_entry); - - /* Index into surface with 16 byte stride */ - unsigned int seqno = *((nv_fence_context->pLinearAddress) + - (nv_fence_context->fenceSemIndex * 4)); - - if (nv_fence->base.seqno > seqno) { - /* - * Fences in list are placed in increasing order of sequence - * number, breaks a loop once found first fence not - * ready to signal. - */ - break; - } - - __nv_drm_prime_fence_signal(nv_fence); - } - - spin_unlock(&nv_fence_context->lock); -} - -static inline struct nv_drm_fence_context *__nv_drm_fence_context_new( - struct nv_drm_device *nv_dev, - struct drm_nvidia_fence_context_create_params *p) -{ - struct nv_drm_fence_context *nv_fence_context; - struct NvKmsKapiMemory *pSemSurface; - NvU32 *pLinearAddress; - - /* Allocate backup nvkms resources */ - - pSemSurface = nvKms->importMemory(nv_dev->pDevice, - p->size, - p->import_mem_nvkms_params_ptr, - p->import_mem_nvkms_params_size); - if (!pSemSurface) { - NV_DRM_DEV_LOG_ERR( - nv_dev, - "Failed to import fence semaphore surface"); - - goto failed; - } - - if (!nvKms->mapMemory(nv_dev->pDevice, - pSemSurface, - NVKMS_KAPI_MAPPING_TYPE_KERNEL, - (void **) &pLinearAddress)) { - NV_DRM_DEV_LOG_ERR( - nv_dev, - "Failed to map fence semaphore surface"); - - goto failed_to_map_memory; - } - - /* - * Allocate a fence context object, initialize it and allocate channel - * event for it. - */ - - if ((nv_fence_context = nv_drm_calloc( - 1, - sizeof(*nv_fence_context))) == NULL) { - goto failed_alloc_fence_context; - } - - /* - * nv_dma_fence_context_alloc() cannot fail, so we do not need - * to check a return value. - */ - - *nv_fence_context = (struct nv_drm_fence_context) { - .nv_dev = nv_dev, - .context = nv_dma_fence_context_alloc(1), - .pSemSurface = pSemSurface, - .pLinearAddress = pLinearAddress, - .fenceSemIndex = p->index, - }; - - INIT_LIST_HEAD(&nv_fence_context->pending); - - spin_lock_init(&nv_fence_context->lock); - - /* - * Except 'cb', the fence context should be completely initialized - * before channel event allocation because the fence context may start - * receiving events immediately after allocation. - * - * There are no simultaneous read/write access to 'cb', therefore it does - * not require spin-lock protection. - */ - nv_fence_context->cb = - nvKms->allocateChannelEvent(nv_dev->pDevice, - nv_drm_gem_prime_fence_event, - nv_fence_context, - p->event_nvkms_params_ptr, - p->event_nvkms_params_size); - if (!nv_fence_context->cb) { - NV_DRM_DEV_LOG_ERR(nv_dev, - "Failed to allocate fence signaling event"); - goto failed_to_allocate_channel_event; - } - - return nv_fence_context; - -failed_to_allocate_channel_event: - nv_drm_free(nv_fence_context); - -failed_alloc_fence_context: - - nvKms->unmapMemory(nv_dev->pDevice, - pSemSurface, - NVKMS_KAPI_MAPPING_TYPE_KERNEL, - (void *) pLinearAddress); - -failed_to_map_memory: - nvKms->freeMemory(nv_dev->pDevice, pSemSurface); - -failed: - return NULL; -} - -static void __nv_drm_fence_context_destroy( - struct nv_drm_fence_context *nv_fence_context) -{ - struct nv_drm_device *nv_dev = nv_fence_context->nv_dev; - - /* - * Free channel event before destroying the fence context, otherwise event - * callback continue to get called. - */ - nvKms->freeChannelEvent(nv_dev->pDevice, nv_fence_context->cb); - - /* Force signal all pending fences and empty pending list */ - spin_lock(&nv_fence_context->lock); - - nv_drm_gem_prime_force_fence_signal(nv_fence_context); - - spin_unlock(&nv_fence_context->lock); - - /* Free nvkms resources */ - - nvKms->unmapMemory(nv_dev->pDevice, - nv_fence_context->pSemSurface, - NVKMS_KAPI_MAPPING_TYPE_KERNEL, - (void *) nv_fence_context->pLinearAddress); - - nvKms->freeMemory(nv_dev->pDevice, nv_fence_context->pSemSurface); - - nv_drm_free(nv_fence_context); -} - -static nv_dma_fence_t *__nv_drm_fence_context_create_fence( - struct nv_drm_fence_context *nv_fence_context, - unsigned int seqno) -{ - struct nv_drm_prime_fence *nv_fence; - int ret = 0; - - if ((nv_fence = nv_drm_calloc(1, sizeof(*nv_fence))) == NULL) { - ret = -ENOMEM; - goto out; - } - - spin_lock(&nv_fence_context->lock); - - /* - * If seqno wrapped, force signal fences to make sure none of them - * get stuck. - */ - if (seqno < nv_fence_context->last_seqno) { - nv_drm_gem_prime_force_fence_signal(nv_fence_context); - } - - INIT_LIST_HEAD(&nv_fence->list_entry); - - spin_lock_init(&nv_fence->lock); - - nv_dma_fence_init(&nv_fence->base, &nv_drm_gem_prime_fence_ops, - &nv_fence->lock, nv_fence_context->context, - seqno); - - /* The context maintains a reference to any pending fences. */ - nv_dma_fence_get(&nv_fence->base); - - list_add_tail(&nv_fence->list_entry, &nv_fence_context->pending); - - nv_fence_context->last_seqno = seqno; - - spin_unlock(&nv_fence_context->lock); - -out: - return ret != 0 ? ERR_PTR(ret) : &nv_fence->base; -} - -int nv_drm_fence_supported_ioctl(struct drm_device *dev, - void *data, struct drm_file *filep) -{ - struct nv_drm_device *nv_dev = to_nv_device(dev); - return nv_dev->pDevice ? 0 : -EINVAL; -} - -struct nv_drm_gem_fence_context { - struct nv_drm_gem_object base; - struct nv_drm_fence_context *nv_fence_context; -}; - -static inline struct nv_drm_gem_fence_context *to_gem_fence_context( - struct nv_drm_gem_object *nv_gem) -{ - if (nv_gem != NULL) { - return container_of(nv_gem, struct nv_drm_gem_fence_context, base); - } - - return NULL; -} - -/* - * Tear down of the 'struct nv_drm_gem_fence_context' object is not expected - * to be happen from any worker thread, if that happen it causes dead-lock - * because tear down sequence calls to flush all existing - * worker thread. - */ -static void __nv_drm_gem_fence_context_free(struct nv_drm_gem_object *nv_gem) -{ - struct nv_drm_gem_fence_context *nv_gem_fence_context = - to_gem_fence_context(nv_gem); - - __nv_drm_fence_context_destroy(nv_gem_fence_context->nv_fence_context); - - nv_drm_free(nv_gem_fence_context); -} - -const struct nv_drm_gem_object_funcs nv_gem_fence_context_ops = { - .free = __nv_drm_gem_fence_context_free, -}; - -static inline -struct nv_drm_gem_fence_context *__nv_drm_gem_object_fence_context_lookup( - struct drm_device *dev, - struct drm_file *filp, - u32 handle) -{ - struct nv_drm_gem_object *nv_gem = - nv_drm_gem_object_lookup(dev, filp, handle); - - if (nv_gem != NULL && nv_gem->ops != &nv_gem_fence_context_ops) { - nv_drm_gem_object_unreference_unlocked(nv_gem); - return NULL; - } - - return to_gem_fence_context(nv_gem); -} - -int nv_drm_fence_context_create_ioctl(struct drm_device *dev, - void *data, struct drm_file *filep) -{ - struct nv_drm_device *nv_dev = to_nv_device(dev); - struct drm_nvidia_fence_context_create_params *p = data; - struct nv_drm_gem_fence_context *nv_gem_fence_context = NULL; - - if ((nv_gem_fence_context = nv_drm_calloc( - 1, - sizeof(struct nv_drm_gem_fence_context))) == NULL) { - goto done; - } - - if ((nv_gem_fence_context->nv_fence_context = - __nv_drm_fence_context_new(nv_dev, p)) == NULL) { - goto fence_context_new_failed; - } - - nv_drm_gem_object_init(nv_dev, - &nv_gem_fence_context->base, - &nv_gem_fence_context_ops, - 0 /* size */, - NULL /* pMemory */); - - return nv_drm_gem_handle_create_drop_reference(filep, - &nv_gem_fence_context->base, - &p->handle); - -fence_context_new_failed: - nv_drm_free(nv_gem_fence_context); - -done: - return -ENOMEM; -} - -int nv_drm_gem_fence_attach_ioctl(struct drm_device *dev, - void *data, struct drm_file *filep) -{ - int ret = -EINVAL; - struct nv_drm_device *nv_dev = to_nv_device(dev); - struct drm_nvidia_gem_fence_attach_params *p = data; - - struct nv_drm_gem_object *nv_gem; - struct nv_drm_gem_fence_context *nv_gem_fence_context; - - nv_dma_fence_t *fence; - - nv_gem = nv_drm_gem_object_lookup(nv_dev->dev, filep, p->handle); - - if (!nv_gem) { - NV_DRM_DEV_LOG_ERR( - nv_dev, - "Failed to lookup gem object for fence attach: 0x%08x", - p->handle); - - goto done; - } - - if((nv_gem_fence_context = __nv_drm_gem_object_fence_context_lookup( - nv_dev->dev, - filep, - p->fence_context_handle)) == NULL) { - - NV_DRM_DEV_LOG_ERR( - nv_dev, - "Failed to lookup gem object for fence context: 0x%08x", - p->fence_context_handle); - - goto fence_context_lookup_failed; - } - - if (IS_ERR(fence = __nv_drm_fence_context_create_fence( - nv_gem_fence_context->nv_fence_context, - p->sem_thresh))) { - ret = PTR_ERR(fence); - - NV_DRM_DEV_LOG_ERR( - nv_dev, - "Failed to allocate fence: 0x%08x", p->handle); - - goto fence_context_create_fence_failed; - } - - nv_dma_resv_lock(&nv_gem->resv, NULL); - - ret = nv_dma_resv_reserve_fences(&nv_gem->resv, 1, false); - if (ret == 0) { - nv_dma_resv_add_excl_fence(&nv_gem->resv, fence); - } else { - NV_DRM_DEV_LOG_ERR( - nv_dev, - "Failed to reserve fence. Error code: %d", ret); - } - - nv_dma_resv_unlock(&nv_gem->resv); - - /* dma_resv_add_excl_fence takes its own reference to the fence. */ - nv_dma_fence_put(fence); - -fence_context_create_fence_failed: - nv_drm_gem_object_unreference_unlocked(&nv_gem_fence_context->base); - -fence_context_lookup_failed: - nv_drm_gem_object_unreference_unlocked(nv_gem); - -done: - return ret; -} - -#endif /* NV_DRM_FENCE_AVAILABLE */ - -#endif /* NV_DRM_AVAILABLE */ diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/kernel-open/nvidia-drm/nvidia-drm-prime-fence.h nvidia-open-gpu-kernel-modules-535.161.08/kernel-open/nvidia-drm/nvidia-drm-prime-fence.h --- nvidia-open-gpu-kernel-modules-525.147.05/kernel-open/nvidia-drm/nvidia-drm-prime-fence.h 2023-10-25 20:25:17.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/kernel-open/nvidia-drm/nvidia-drm-prime-fence.h 1970-01-01 00:00:00.000000000 +0000 @@ -1,48 +0,0 @@ -/* - * Copyright (c) 2016, NVIDIA CORPORATION. All rights reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER - * DEALINGS IN THE SOFTWARE. - */ - -#ifndef __NVIDIA_DRM_PRIME_FENCE_H__ -#define __NVIDIA_DRM_PRIME_FENCE_H__ - -#include "nvidia-drm-conftest.h" - -#if defined(NV_DRM_AVAILABLE) - -struct drm_file; -struct drm_device; - -#if defined(NV_DRM_FENCE_AVAILABLE) - -int nv_drm_fence_supported_ioctl(struct drm_device *dev, - void *data, struct drm_file *filep); - -int nv_drm_fence_context_create_ioctl(struct drm_device *dev, - void *data, struct drm_file *filep); - -int nv_drm_gem_fence_attach_ioctl(struct drm_device *dev, - void *data, struct drm_file *filep); - -#endif /* NV_DRM_FENCE_AVAILABLE */ - -#endif /* NV_DRM_AVAILABLE */ - -#endif /* __NVIDIA_DRM_PRIME_FENCE_H__ */ diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/kernel-open/nvidia-drm/nvidia-drm.Kbuild nvidia-open-gpu-kernel-modules-535.161.08/kernel-open/nvidia-drm/nvidia-drm.Kbuild --- nvidia-open-gpu-kernel-modules-525.147.05/kernel-open/nvidia-drm/nvidia-drm.Kbuild 2023-10-25 20:18:09.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/kernel-open/nvidia-drm/nvidia-drm.Kbuild 2024-02-22 04:55:44.000000000 +0000 @@ -16,7 +16,7 @@ NVIDIA_DRM_SOURCES += nvidia-drm/nvidia-drm-gem.c NVIDIA_DRM_SOURCES += nvidia-drm/nvidia-drm-fb.c NVIDIA_DRM_SOURCES += nvidia-drm/nvidia-drm-modeset.c -NVIDIA_DRM_SOURCES += nvidia-drm/nvidia-drm-prime-fence.c +NVIDIA_DRM_SOURCES += nvidia-drm/nvidia-drm-fence.c NVIDIA_DRM_SOURCES += nvidia-drm/nvidia-drm-linux.c NVIDIA_DRM_SOURCES += nvidia-drm/nvidia-drm-helper.c NVIDIA_DRM_SOURCES += nvidia-drm/nv-pci-table.c @@ -126,5 +126,11 @@ NV_CONFTEST_TYPE_COMPILE_TESTS += dma_resv_reserve_fences NV_CONFTEST_TYPE_COMPILE_TESTS += reservation_object_reserve_shared_has_num_fences_arg NV_CONFTEST_TYPE_COMPILE_TESTS += drm_connector_has_override_edid +NV_CONFTEST_TYPE_COMPILE_TESTS += drm_master_has_leases +NV_CONFTEST_TYPE_COMPILE_TESTS += drm_file_get_master +NV_CONFTEST_TYPE_COMPILE_TESTS += drm_modeset_lock_all_end +NV_CONFTEST_TYPE_COMPILE_TESTS += drm_connector_lookup +NV_CONFTEST_TYPE_COMPILE_TESTS += drm_connector_put NV_CONFTEST_TYPE_COMPILE_TESTS += vm_area_struct_has_const_vm_flags NV_CONFTEST_TYPE_COMPILE_TESTS += drm_driver_has_dumb_destroy +NV_CONFTEST_TYPE_COMPILE_TESTS += drm_unlocked_ioctl_flag_present diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/kernel-open/nvidia-modeset/nv-kthread-q.c nvidia-open-gpu-kernel-modules-535.161.08/kernel-open/nvidia-modeset/nv-kthread-q.c --- nvidia-open-gpu-kernel-modules-525.147.05/kernel-open/nvidia-modeset/nv-kthread-q.c 2023-10-25 20:24:50.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/kernel-open/nvidia-modeset/nv-kthread-q.c 2024-03-05 22:14:19.000000000 +0000 @@ -301,7 +301,7 @@ static void _raw_q_flush(nv_kthread_q_t *q) { nv_kthread_q_item_t q_item; - DECLARE_COMPLETION(completion); + DECLARE_COMPLETION_ONSTACK(completion); nv_kthread_q_item_init(&q_item, _q_flush_function, &completion); diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/kernel-open/nvidia-modeset/nvidia-modeset-linux.c nvidia-open-gpu-kernel-modules-535.161.08/kernel-open/nvidia-modeset/nvidia-modeset-linux.c --- nvidia-open-gpu-kernel-modules-525.147.05/kernel-open/nvidia-modeset/nvidia-modeset-linux.c 2023-10-25 20:24:50.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/kernel-open/nvidia-modeset/nvidia-modeset-linux.c 2024-03-05 22:14:19.000000000 +0000 @@ -68,6 +68,9 @@ static bool disable_vrr_memclk_switch = false; module_param_named(disable_vrr_memclk_switch, disable_vrr_memclk_switch, bool, 0400); +static bool opportunistic_display_sync = true; +module_param_named(opportunistic_display_sync, opportunistic_display_sync, bool, 0400); + /* These parameters are used for fault injection tests. Normally the defaults * should be used. */ MODULE_PARM_DESC(fail_malloc, "Fail the Nth call to nvkms_alloc"); @@ -78,6 +81,15 @@ static bool malloc_verbose = false; module_param_named(malloc_verbose, malloc_verbose, bool, 0400); +/* This parameter is used to find the dpy override conf file */ +#define NVKMS_CONF_FILE_SPECIFIED (nvkms_conf != NULL) + +MODULE_PARM_DESC(config_file, + "Path to the nvidia-modeset configuration file " + "(default: disabled)"); +static char *nvkms_conf = NULL; +module_param_named(config_file, nvkms_conf, charp, 0400); + static atomic_t nvkms_alloc_called_count; NvBool nvkms_output_rounding_fix(void) @@ -90,6 +102,11 @@ return disable_vrr_memclk_switch; } +NvBool nvkms_opportunistic_display_sync(void) +{ + return opportunistic_display_sync; +} + #define NVKMS_SYNCPT_STUBS_NEEDED /************************************************************************* @@ -191,9 +208,23 @@ static inline void nvkms_read_lock_pm_lock(void) { - while (!down_read_trylock(&nvkms_pm_lock)) { - try_to_freeze(); - cond_resched(); + if ((current->flags & PF_NOFREEZE)) { + /* + * Non-freezable tasks (i.e. kthreads in this case) don't have to worry + * about being frozen during system suspend, but do need to block so + * that the CPU can go idle during s2idle. Do a normal uninterruptible + * blocking wait for the PM lock. + */ + down_read(&nvkms_pm_lock); + } else { + /* + * For freezable tasks, make sure we give the kernel an opportunity to + * freeze if taking the PM lock fails. + */ + while (!down_read_trylock(&nvkms_pm_lock)) { + try_to_freeze(); + cond_resched(); + } } } @@ -1371,6 +1402,117 @@ } /************************************************************************* + * NVKMS Config File Read + ************************************************************************/ +static NvBool nvkms_fs_mounted(void) +{ + return current->fs != NULL; +} + +static size_t nvkms_config_file_open +( + char *fname, + char ** const buff +) +{ + int i = 0; + struct file *file; + struct inode *file_inode; + size_t file_size = 0; + size_t read_size = 0; +#if defined(NV_KERNEL_READ_HAS_POINTER_POS_ARG) + loff_t pos = 0; +#endif + + if (!nvkms_fs_mounted()) { + printk(KERN_ERR NVKMS_LOG_PREFIX "ERROR: Filesystems not mounted\n"); + return 0; + } + + file = filp_open(fname, O_RDONLY, 0); + if (file == NULL || IS_ERR(file)) { + printk(KERN_WARNING NVKMS_LOG_PREFIX "WARNING: Failed to open %s\n", + fname); + return 0; + } + + file_inode = file->f_inode; + if (file_inode == NULL || IS_ERR(file_inode)) { + printk(KERN_WARNING NVKMS_LOG_PREFIX "WARNING: Inode is invalid\n"); + goto done; + } + file_size = file_inode->i_size; + if (file_size > NVKMS_READ_FILE_MAX_SIZE) { + printk(KERN_WARNING NVKMS_LOG_PREFIX "WARNING: File exceeds maximum size\n"); + goto done; + } + + *buff = nvkms_alloc(file_size, NV_FALSE); + if (*buff == NULL) { + printk(KERN_WARNING NVKMS_LOG_PREFIX "WARNING: Out of memory\n"); + goto done; + } + + /* + * TODO: Once we have access to GPL symbols, this can be replaced with + * kernel_read_file for kernels >= 4.6 + */ + while ((read_size < file_size) && (i++ < NVKMS_READ_FILE_MAX_LOOPS)) { +#if defined(NV_KERNEL_READ_HAS_POINTER_POS_ARG) + ssize_t ret = kernel_read(file, *buff + read_size, + file_size - read_size, &pos); +#else + ssize_t ret = kernel_read(file, read_size, + *buff + read_size, + file_size - read_size); +#endif + if (ret <= 0) { + break; + } + read_size += ret; + } + + if (read_size != file_size) { + printk(KERN_WARNING NVKMS_LOG_PREFIX "WARNING: Failed to read %s\n", + fname); + goto done; + } + + filp_close(file, current->files); + return file_size; + +done: + nvkms_free(*buff, file_size); + filp_close(file, current->files); + return 0; +} + +/* must be called with nvkms_lock locked */ +static void nvkms_read_config_file_locked(void) +{ + char *buffer = NULL; + size_t buf_size = 0; + + /* only read the config file if the kernel parameter is set */ + if (!NVKMS_CONF_FILE_SPECIFIED) { + return; + } + + buf_size = nvkms_config_file_open(nvkms_conf, &buffer); + + if (buf_size == 0) { + return; + } + + if (nvKmsReadConf(buffer, buf_size, nvkms_config_file_open)) { + printk(KERN_INFO NVKMS_LOG_PREFIX "Successfully read %s\n", + nvkms_conf); + } + + nvkms_free(buffer, buf_size); +} + +/************************************************************************* * NVKMS KAPI functions ************************************************************************/ @@ -1541,10 +1683,12 @@ if (!nvKmsModuleLoad()) { ret = -ENOMEM; } - up(&nvkms_lock); if (ret != 0) { + up(&nvkms_lock); goto fail_module_load; } + nvkms_read_config_file_locked(); + up(&nvkms_lock); nvkms_proc_init(); diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/kernel-open/nvidia-modeset/nvidia-modeset-os-interface.h nvidia-open-gpu-kernel-modules-535.161.08/kernel-open/nvidia-modeset/nvidia-modeset-os-interface.h --- nvidia-open-gpu-kernel-modules-525.147.05/kernel-open/nvidia-modeset/nvidia-modeset-os-interface.h 2023-10-25 20:24:50.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/kernel-open/nvidia-modeset/nvidia-modeset-os-interface.h 2024-03-05 22:14:19.000000000 +0000 @@ -40,17 +40,31 @@ #include "nv_stdarg.h" enum NvKmsSyncPtOp { + /* + * Call into Tegra's kernel nvhost driver, and allocate a syncpoint that can + * be exclusively used by the caller. Internally, this operation will call + * get() to set the initial refcount of the syncpoint to 1. + */ NVKMS_SYNCPT_OP_ALLOC, - NVKMS_SYNCPT_OP_GET, + /* + * Decrease the refcount of an already allocated syncpoint. Once the + * refcount drops to 0, the syncpoint will be returned to the free pool that + * nvhost manages, so PUT can also be used to balance out an ALLOC. + */ NVKMS_SYNCPT_OP_PUT, - NVKMS_SYNCPT_OP_INCR_MAX, - NVKMS_SYNCPT_OP_CPU_INCR, + /* + * Extract syncpt id and thresh from the sync-file file descriptor + */ NVKMS_SYNCPT_OP_FD_TO_ID_AND_THRESH, + /* + * Create dma-fence from syncpt id and thresh value and create sync_file + * file descriptor for the dma-fence handle created. + */ NVKMS_SYNCPT_OP_ID_AND_THRESH_TO_FD, + /* + * read syncpt minimum value of given syncpt + */ NVKMS_SYNCPT_OP_READ_MINVAL, - NVKMS_SYNCPT_OP_READ_MAXVAL, - NVKMS_SYNCPT_OP_SET_MIN_EQ_MAX, - NVKMS_SYNCPT_OP_SET_MAXVAL, }; typedef struct { @@ -62,23 +76,9 @@ struct { NvU32 id; /* in */ - } get; - - struct { - NvU32 id; /* in */ } put; struct { - NvU32 id; /* in */ - NvU32 incr; /* in */ - NvU32 value; /* out */ - } incr_max; - - struct { - NvU32 id; /* in */ - } cpu_incr; - - struct { NvS32 fd; /* in */ NvU32 id; /* out */ NvU32 thresh; /* out */ @@ -94,25 +94,12 @@ NvU32 id; /* in */ NvU32 minval; /* out */ } read_minval; - - struct { - NvU32 id; /* in */ - NvU32 maxval; /* out */ - } read_maxval; - - struct { - NvU32 id; /* in */ - } set_min_eq_max; - - struct { - NvU32 id; /* in */ - NvU32 val; /* in */ - } set_maxval; } NvKmsSyncPtOpParams; NvBool nvkms_output_rounding_fix(void); NvBool nvkms_disable_vrr_memclk_switch(void); +NvBool nvkms_opportunistic_display_sync(void); void nvkms_call_rm (void *ops); void* nvkms_alloc (size_t size, diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/kernel-open/nvidia-modeset/nvkms.h nvidia-open-gpu-kernel-modules-535.161.08/kernel-open/nvidia-modeset/nvkms.h --- nvidia-open-gpu-kernel-modules-525.147.05/kernel-open/nvidia-modeset/nvkms.h 2023-10-25 20:24:50.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/kernel-open/nvidia-modeset/nvkms.h 2024-03-05 22:14:19.000000000 +0000 @@ -42,6 +42,20 @@ char *buffer, size_t size, nvkms_procfs_out_string_func_t *outString); +/* max number of loops to prevent hanging the kernel if an edge case is hit */ +#define NVKMS_READ_FILE_MAX_LOOPS 1000 +/* max size for any file read by the config system */ +#define NVKMS_READ_FILE_MAX_SIZE 8192 + +/* + * The read file callback should allocate a buffer pointed to by *buff, fill it + * with the contents of fname, and return the size of the buffer. Buffer is not + * guaranteed to be null-terminated. The caller is responsible for freeing the + * buffer with nvkms_free, not nvFree. + */ +typedef size_t nvkms_config_read_file_func_t(char *fname, + char ** const buff); + typedef struct { const char *name; nvkms_procfs_proc_t *func; @@ -74,6 +88,9 @@ void nvKmsGetProcFiles(const nvkms_procfs_file_t **ppProcFiles); +NvBool nvKmsReadConf(const char *buff, size_t size, + nvkms_config_read_file_func_t readfile); + void nvKmsKapiHandleEventQueueChange ( struct NvKmsKapiDevice *device diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/kernel-open/nvidia-peermem/nvidia-peermem.c nvidia-open-gpu-kernel-modules-535.161.08/kernel-open/nvidia-peermem/nvidia-peermem.c --- nvidia-open-gpu-kernel-modules-525.147.05/kernel-open/nvidia-peermem/nvidia-peermem.c 2023-10-25 20:26:22.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/kernel-open/nvidia-peermem/nvidia-peermem.c 2024-03-05 22:15:03.000000000 +0000 @@ -1,20 +1,25 @@ -/* SPDX-License-Identifier: Linux-OpenIB */ /* * Copyright (c) 2006, 2007 Cisco Systems, Inc. All rights reserved. * Copyright (c) 2007, 2008 Mellanox Technologies. All rights reserved. * - * Redistribution and use in source and binary forms, with or - * without modification, are permitted provided that the following - * conditions are met: + * This software is available to you under a choice of one of two + * licenses. You may choose to be licensed under the terms of the GNU + * General Public License (GPL) Version 2, available from the file + * COPYING in the main directory of this source tree, or the + * OpenIB.org BSD license below: * - * - Redistributions of source code must retain the above - * copyright notice, this list of conditions and the following - * disclaimer. + * Redistribution and use in source and binary forms, with or + * without modification, are permitted provided that the following + * conditions are met: * - * - Redistributions in binary form must reproduce the above - * copyright notice, this list of conditions and the following - * disclaimer in the documentation and/or other materials - * provided with the distribution. + * - Redistributions of source code must retain the above + * copyright notice, this list of conditions and the following + * disclaimer. + * + * - Redistributions in binary form must reproduce the above + * copyright notice, this list of conditions and the following + * disclaimer in the documentation and/or other materials + * provided with the distribution. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF @@ -43,7 +48,9 @@ MODULE_AUTHOR("Yishai Hadas"); MODULE_DESCRIPTION("NVIDIA GPU memory plug-in"); -MODULE_LICENSE("Linux-OpenIB"); + +MODULE_LICENSE("Dual BSD/GPL"); + MODULE_VERSION(DRV_VERSION); enum { NV_MEM_PEERDIRECT_SUPPORT_DEFAULT = 0, @@ -53,7 +60,13 @@ module_param(peerdirect_support, int, S_IRUGO); MODULE_PARM_DESC(peerdirect_support, "Set level of support for Peer-direct, 0 [default] or 1 [legacy, for example MLNX_OFED 4.9 LTS]"); -#define peer_err(FMT, ARGS...) printk(KERN_ERR "nvidia-peermem" " %s:%d " FMT, __FUNCTION__, __LINE__, ## ARGS) + +#define peer_err(FMT, ARGS...) printk(KERN_ERR "nvidia-peermem" " %s:%d ERROR " FMT, __FUNCTION__, __LINE__, ## ARGS) +#ifdef NV_MEM_DEBUG +#define peer_trace(FMT, ARGS...) printk(KERN_DEBUG "nvidia-peermem" " %s:%d TRACE " FMT, __FUNCTION__, __LINE__, ## ARGS) +#else +#define peer_trace(FMT, ARGS...) do {} while (0) +#endif #if defined(NV_MLNX_IB_PEER_MEM_SYMBOLS_PRESENT) @@ -74,7 +87,10 @@ static void *reg_handle = NULL; static void *reg_handle_nc = NULL; +#define NV_MEM_CONTEXT_MAGIC ((u64)0xF1F4F1D0FEF0DAD0ULL) + struct nv_mem_context { + u64 pad1; struct nvidia_p2p_page_table *page_table; struct nvidia_p2p_dma_mapping *dma_mapping; u64 core_context; @@ -86,8 +102,22 @@ struct task_struct *callback_task; int sg_allocated; struct sg_table sg_head; + u64 pad2; }; +#define NV_MEM_CONTEXT_CHECK_OK(MC) ({ \ + struct nv_mem_context *mc = (MC); \ + int rc = ((0 != mc) && \ + (READ_ONCE(mc->pad1) == NV_MEM_CONTEXT_MAGIC) && \ + (READ_ONCE(mc->pad2) == NV_MEM_CONTEXT_MAGIC)); \ + if (!rc) { \ + peer_trace("invalid nv_mem_context=%px pad1=%016llx pad2=%016llx\n", \ + mc, \ + mc?mc->pad1:0, \ + mc?mc->pad2:0); \ + } \ + rc; \ +}) static void nv_get_p2p_free_callback(void *data) { @@ -97,8 +127,9 @@ struct nvidia_p2p_dma_mapping *dma_mapping = NULL; __module_get(THIS_MODULE); - if (!nv_mem_context) { - peer_err("nv_get_p2p_free_callback -- invalid nv_mem_context\n"); + + if (!NV_MEM_CONTEXT_CHECK_OK(nv_mem_context)) { + peer_err("detected invalid context, skipping further processing\n"); goto out; } @@ -169,9 +200,11 @@ /* Error case handled as not mine */ return 0; + nv_mem_context->pad1 = NV_MEM_CONTEXT_MAGIC; nv_mem_context->page_virt_start = addr & GPU_PAGE_MASK; nv_mem_context->page_virt_end = (addr + size + GPU_PAGE_SIZE - 1) & GPU_PAGE_MASK; nv_mem_context->mapped_size = nv_mem_context->page_virt_end - nv_mem_context->page_virt_start; + nv_mem_context->pad2 = NV_MEM_CONTEXT_MAGIC; ret = nvidia_p2p_get_pages(0, 0, nv_mem_context->page_virt_start, nv_mem_context->mapped_size, &nv_mem_context->page_table, nv_mem_dummy_callback, nv_mem_context); @@ -195,6 +228,7 @@ return 1; err: + memset(nv_mem_context, 0, sizeof(*nv_mem_context)); kfree(nv_mem_context); /* Error case handled as not mine */ @@ -342,6 +376,7 @@ sg_free_table(&nv_mem_context->sg_head); nv_mem_context->sg_allocated = 0; } + memset(nv_mem_context, 0, sizeof(*nv_mem_context)); kfree(nv_mem_context); module_put(THIS_MODULE); return; diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/kernel-open/nvidia-uvm/cla06fsubch.h nvidia-open-gpu-kernel-modules-535.161.08/kernel-open/nvidia-uvm/cla06fsubch.h --- nvidia-open-gpu-kernel-modules-525.147.05/kernel-open/nvidia-uvm/cla06fsubch.h 2023-10-25 20:33:28.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/kernel-open/nvidia-uvm/cla06fsubch.h 2024-03-05 22:25:42.000000000 +0000 @@ -1,29 +1,33 @@ -/******************************************************************************* - Copyright (c) 2013 NVIDIA Corporation - - Permission is hereby granted, free of charge, to any person obtaining a copy - of this software and associated documentation files (the "Software"), to - deal in the Software without restriction, including without limitation the - rights to use, copy, modify, merge, publish, distribute, sublicense, and/or - sell copies of the Software, and to permit persons to whom the Software is - furnished to do so, subject to the following conditions: - - The above copyright notice and this permission notice shall be - included in all copies or substantial portions of the Software. - - THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER - DEALINGS IN THE SOFTWARE. - -*******************************************************************************/ - -#ifndef __cla06fsubch_h__ -#define __cla06fsubch_h__ - +/* + * SPDX-FileCopyrightText: Copyright (c) 2003-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef _cla06fsubch_h_ +#define _cla06fsubch_h_ + +#define NVA06F_SUBCHANNEL_2D 3 +#define NVA06F_SUBCHANNEL_3D 0 +#define NVA06F_SUBCHANNEL_COMPUTE 1 #define NVA06F_SUBCHANNEL_COPY_ENGINE 4 +#define NVA06F_SUBCHANNEL_I2M 2 -#endif // {__cla06fsubch_h__} +#endif // _cla06fsubch_h_ diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/kernel-open/nvidia-uvm/cla16f.h nvidia-open-gpu-kernel-modules-535.161.08/kernel-open/nvidia-uvm/cla16f.h --- nvidia-open-gpu-kernel-modules-525.147.05/kernel-open/nvidia-uvm/cla16f.h 2023-10-25 20:33:28.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/kernel-open/nvidia-uvm/cla16f.h 2024-03-05 22:25:42.000000000 +0000 @@ -1,25 +1,25 @@ -/******************************************************************************* - Copyright (c) 2021-2022 NVIDIA Corporation - - Permission is hereby granted, free of charge, to any person obtaining a copy - of this software and associated documentation files (the "Software"), to - deal in the Software without restriction, including without limitation the - rights to use, copy, modify, merge, publish, distribute, sublicense, and/or - sell copies of the Software, and to permit persons to whom the Software is - furnished to do so, subject to the following conditions: - - The above copyright notice and this permission notice shall be - included in all copies or substantial portions of the Software. - - THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER - DEALINGS IN THE SOFTWARE. - -*******************************************************************************/ +/* + * SPDX-FileCopyrightText: Copyright (c) 2020-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ #ifndef _cla16f_h_ #define _cla16f_h_ @@ -30,9 +30,48 @@ #include "nvtypes.h" -#define KEPLER_CHANNEL_GPFIFO_B (0x0000A16F) - +/* class KEPLER_CHANNEL_GPFIFO */ +/* + * Documentation for KEPLER_CHANNEL_GPFIFO can be found in dev_pbdma.ref, + * chapter "User Control Registers". It is documented as device NV_UDMA. + * The GPFIFO format itself is also documented in dev_pbdma.ref, + * NV_PPBDMA_GP_ENTRY_*. The pushbuffer format is documented in dev_ram.ref, + * chapter "FIFO DMA RAM", NV_FIFO_DMA_*. + * + */ +#define KEPLER_CHANNEL_GPFIFO_B (0x0000A16F) + +/* pio method data structure */ +typedef volatile struct _cla16f_tag0 { + NvV32 Reserved00[0x7c0]; +} NvA16FTypedef, KEPLER_ChannelGPFifoB; +#define NVA16F_TYPEDEF KEPLER_CHANNELChannelGPFifo +/* dma flow control data structure */ +typedef volatile struct _cla16f_tag1 { + NvU32 Ignored00[0x010]; /* 0000-003f*/ + NvU32 Put; /* put offset, read/write 0040-0043*/ + NvU32 Get; /* get offset, read only 0044-0047*/ + NvU32 Reference; /* reference value, read only 0048-004b*/ + NvU32 PutHi; /* high order put offset bits 004c-004f*/ + NvU32 Ignored01[0x002]; /* 0050-0057*/ + NvU32 TopLevelGet; /* top level get offset, read only 0058-005b*/ + NvU32 TopLevelGetHi; /* high order top level get bits 005c-005f*/ + NvU32 GetHi; /* high order get offset bits 0060-0063*/ + NvU32 Ignored02[0x007]; /* 0064-007f*/ + NvU32 Ignored03; /* used to be engine yield 0080-0083*/ + NvU32 Ignored04[0x001]; /* 0084-0087*/ + NvU32 GPGet; /* GP FIFO get offset, read only 0088-008b*/ + NvU32 GPPut; /* GP FIFO put offset 008c-008f*/ + NvU32 Ignored05[0x5c]; +} NvA16FControl, KeplerBControlGPFifo; +/* fields and values */ +#define NVA16F_NUMBER_OF_SUBCHANNELS (8) #define NVA16F_SET_OBJECT (0x00000000) +#define NVA16F_SET_OBJECT_NVCLASS 15:0 +#define NVA16F_SET_OBJECT_ENGINE 20:16 +#define NVA16F_SET_OBJECT_ENGINE_SW 0x0000001f +#define NVA16F_ILLEGAL (0x00000004) +#define NVA16F_ILLEGAL_HANDLE 31:0 #define NVA16F_NOP (0x00000008) #define NVA16F_NOP_HANDLE 31:0 #define NVA16F_SEMAPHOREA (0x00000010) @@ -100,6 +139,12 @@ #define NVA16F_SET_REFERENCE_COUNT 31:0 #define NVA16F_WFI (0x00000078) #define NVA16F_WFI_HANDLE 31:0 +#define NVA16F_CRC_CHECK (0x0000007c) +#define NVA16F_CRC_CHECK_VALUE 31:0 +#define NVA16F_YIELD (0x00000080) +#define NVA16F_YIELD_OP 1:0 +#define NVA16F_YIELD_OP_NOP 0x00000000 + /* GPFIFO entry format */ #define NVA16F_GP_ENTRY__SIZE 8 @@ -126,13 +171,28 @@ #define NVA16F_GP_ENTRY1_OPCODE_PB_CRC 0x00000003 /* dma method formats */ +#define NVA16F_DMA_METHOD_ADDRESS_OLD 12:2 #define NVA16F_DMA_METHOD_ADDRESS 11:0 +#define NVA16F_DMA_SUBDEVICE_MASK 15:4 #define NVA16F_DMA_METHOD_SUBCHANNEL 15:13 +#define NVA16F_DMA_TERT_OP 17:16 +#define NVA16F_DMA_TERT_OP_GRP0_INC_METHOD (0x00000000) +#define NVA16F_DMA_TERT_OP_GRP0_SET_SUB_DEV_MASK (0x00000001) +#define NVA16F_DMA_TERT_OP_GRP0_STORE_SUB_DEV_MASK (0x00000002) +#define NVA16F_DMA_TERT_OP_GRP0_USE_SUB_DEV_MASK (0x00000003) +#define NVA16F_DMA_TERT_OP_GRP2_NON_INC_METHOD (0x00000000) +#define NVA16F_DMA_METHOD_COUNT_OLD 28:18 #define NVA16F_DMA_METHOD_COUNT 28:16 +#define NVA16F_DMA_IMMD_DATA 28:16 #define NVA16F_DMA_SEC_OP 31:29 +#define NVA16F_DMA_SEC_OP_GRP0_USE_TERT (0x00000000) #define NVA16F_DMA_SEC_OP_INC_METHOD (0x00000001) +#define NVA16F_DMA_SEC_OP_GRP2_USE_TERT (0x00000002) #define NVA16F_DMA_SEC_OP_NON_INC_METHOD (0x00000003) - +#define NVA16F_DMA_SEC_OP_IMMD_DATA_METHOD (0x00000004) +#define NVA16F_DMA_SEC_OP_ONE_INC (0x00000005) +#define NVA16F_DMA_SEC_OP_RESERVED6 (0x00000006) +#define NVA16F_DMA_SEC_OP_END_PB_SEGMENT (0x00000007) /* dma incrementing method format */ #define NVA16F_DMA_INCR_ADDRESS 11:0 #define NVA16F_DMA_INCR_SUBCHANNEL 15:13 @@ -140,7 +200,6 @@ #define NVA16F_DMA_INCR_OPCODE 31:29 #define NVA16F_DMA_INCR_OPCODE_VALUE (0x00000001) #define NVA16F_DMA_INCR_DATA 31:0 - /* dma non-incrementing method format */ #define NVA16F_DMA_NONINCR_ADDRESS 11:0 #define NVA16F_DMA_NONINCR_SUBCHANNEL 15:13 @@ -148,13 +207,45 @@ #define NVA16F_DMA_NONINCR_OPCODE 31:29 #define NVA16F_DMA_NONINCR_OPCODE_VALUE (0x00000003) #define NVA16F_DMA_NONINCR_DATA 31:0 - +/* dma increment-once method format */ +#define NVA16F_DMA_ONEINCR_ADDRESS 11:0 +#define NVA16F_DMA_ONEINCR_SUBCHANNEL 15:13 +#define NVA16F_DMA_ONEINCR_COUNT 28:16 +#define NVA16F_DMA_ONEINCR_OPCODE 31:29 +#define NVA16F_DMA_ONEINCR_OPCODE_VALUE (0x00000005) +#define NVA16F_DMA_ONEINCR_DATA 31:0 +/* dma no-operation format */ +#define NVA16F_DMA_NOP (0x00000000) /* dma immediate-data format */ #define NVA16F_DMA_IMMD_ADDRESS 11:0 #define NVA16F_DMA_IMMD_SUBCHANNEL 15:13 #define NVA16F_DMA_IMMD_DATA 28:16 #define NVA16F_DMA_IMMD_OPCODE 31:29 #define NVA16F_DMA_IMMD_OPCODE_VALUE (0x00000004) +/* dma set sub-device mask format */ +#define NVA16F_DMA_SET_SUBDEVICE_MASK_VALUE 15:4 +#define NVA16F_DMA_SET_SUBDEVICE_MASK_OPCODE 31:16 +#define NVA16F_DMA_SET_SUBDEVICE_MASK_OPCODE_VALUE (0x00000001) +/* dma store sub-device mask format */ +#define NVA16F_DMA_STORE_SUBDEVICE_MASK_VALUE 15:4 +#define NVA16F_DMA_STORE_SUBDEVICE_MASK_OPCODE 31:16 +#define NVA16F_DMA_STORE_SUBDEVICE_MASK_OPCODE_VALUE (0x00000002) +/* dma use sub-device mask format */ +#define NVA16F_DMA_USE_SUBDEVICE_MASK_OPCODE 31:16 +#define NVA16F_DMA_USE_SUBDEVICE_MASK_OPCODE_VALUE (0x00000003) +/* dma end-segment format */ +#define NVA16F_DMA_ENDSEG_OPCODE 31:29 +#define NVA16F_DMA_ENDSEG_OPCODE_VALUE (0x00000007) +/* dma legacy incrementing/non-incrementing formats */ +#define NVA16F_DMA_ADDRESS 12:2 +#define NVA16F_DMA_SUBCH 15:13 +#define NVA16F_DMA_OPCODE3 17:16 +#define NVA16F_DMA_OPCODE3_NONE (0x00000000) +#define NVA16F_DMA_COUNT 28:18 +#define NVA16F_DMA_OPCODE 31:29 +#define NVA16F_DMA_OPCODE_METHOD (0x00000000) +#define NVA16F_DMA_OPCODE_NONINC_METHOD (0x00000002) +#define NVA16F_DMA_DATA 31:0 #ifdef __cplusplus }; /* extern "C" */ diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/kernel-open/nvidia-uvm/clb069.h nvidia-open-gpu-kernel-modules-535.161.08/kernel-open/nvidia-uvm/clb069.h --- nvidia-open-gpu-kernel-modules-525.147.05/kernel-open/nvidia-uvm/clb069.h 2023-10-25 20:33:28.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/kernel-open/nvidia-uvm/clb069.h 2024-03-05 22:25:43.000000000 +0000 @@ -1,24 +1,26 @@ -/******************************************************************************* - Copyright (c) 2014 NVidia Corporation +/* + * SPDX-FileCopyrightText: Copyright (c) 2020-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ - Permission is hereby granted, free of charge, to any person obtaining a copy - of this software and associated documentation files (the "Software"), to - deal in the Software without restriction, including without limitation the - rights to use, copy, modify, merge, publish, distribute, sublicense, and/or - sell copies of the Software, and to permit persons to whom the Software is - furnished to do so, subject to the following conditions: - - The above copyright notice and this permission notice shall be - included in all copies or substantial portions of the Software. - - THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER - DEALINGS IN THE SOFTWARE. -*******************************************************************************/ #ifndef _clb069_h_ #define _clb069_h_ diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/kernel-open/nvidia-uvm/clb06f.h nvidia-open-gpu-kernel-modules-535.161.08/kernel-open/nvidia-uvm/clb06f.h --- nvidia-open-gpu-kernel-modules-525.147.05/kernel-open/nvidia-uvm/clb06f.h 2023-10-25 20:33:28.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/kernel-open/nvidia-uvm/clb06f.h 2024-03-05 22:25:42.000000000 +0000 @@ -1,28 +1,28 @@ -/******************************************************************************* - Copyright (c) 2014 NVIDIA Corporation +/* + * SPDX-FileCopyrightText: Copyright (c) 2020-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ - Permission is hereby granted, free of charge, to any person obtaining a copy - of this software and associated documentation files (the "Software"), to - deal in the Software without restriction, including without limitation the - rights to use, copy, modify, merge, publish, distribute, sublicense, and/or - sell copies of the Software, and to permit persons to whom the Software is - furnished to do so, subject to the following conditions: - - The above copyright notice and this permission notice shall be - included in all copies or substantial portions of the Software. - - THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER - DEALINGS IN THE SOFTWARE. - -*******************************************************************************/ - -#ifndef _clB06f_h_ -#define _clB06f_h_ +#ifndef _clb06f_h_ +#define _clb06f_h_ #ifdef __cplusplus extern "C" { @@ -30,10 +30,46 @@ #include "nvtypes.h" +/* class MAXWELL_CHANNEL_GPFIFO */ +/* + * Documentation for MAXWELL_CHANNEL_GPFIFO can be found in dev_pbdma.ref, + * chapter "User Control Registers". It is documented as device NV_UDMA. + * The GPFIFO format itself is also documented in dev_pbdma.ref, + * NV_PPBDMA_GP_ENTRY_*. The pushbuffer format is documented in dev_ram.ref, + * chapter "FIFO DMA RAM", NV_FIFO_DMA_*. + * + */ #define MAXWELL_CHANNEL_GPFIFO_A (0x0000B06F) -/* class MAXWELL_CHANNEL_GPFIFO */ +#define NVB06F_TYPEDEF MAXWELL_CHANNELChannelGPFifoA + +/* dma flow control data structure */ +typedef volatile struct _clb06f_tag0 { + NvU32 Ignored00[0x010]; /* 0000-003f*/ + NvU32 Put; /* put offset, read/write 0040-0043*/ + NvU32 Get; /* get offset, read only 0044-0047*/ + NvU32 Reference; /* reference value, read only 0048-004b*/ + NvU32 PutHi; /* high order put offset bits 004c-004f*/ + NvU32 Ignored01[0x002]; /* 0050-0057*/ + NvU32 TopLevelGet; /* top level get offset, read only 0058-005b*/ + NvU32 TopLevelGetHi; /* high order top level get bits 005c-005f*/ + NvU32 GetHi; /* high order get offset bits 0060-0063*/ + NvU32 Ignored02[0x007]; /* 0064-007f*/ + NvU32 Ignored03; /* used to be engine yield 0080-0083*/ + NvU32 Ignored04[0x001]; /* 0084-0087*/ + NvU32 GPGet; /* GP FIFO get offset, read only 0088-008b*/ + NvU32 GPPut; /* GP FIFO put offset 008c-008f*/ + NvU32 Ignored05[0x5c]; +} Nvb06FControl, MaxwellAControlGPFifo; + +/* fields and values */ +#define NVB06F_NUMBER_OF_SUBCHANNELS (8) #define NVB06F_SET_OBJECT (0x00000000) +#define NVB06F_SET_OBJECT_NVCLASS 15:0 +#define NVB06F_SET_OBJECT_ENGINE 20:16 +#define NVB06F_SET_OBJECT_ENGINE_SW 0x0000001f +#define NVB06F_ILLEGAL (0x00000004) +#define NVB06F_ILLEGAL_HANDLE 31:0 #define NVB06F_NOP (0x00000008) #define NVB06F_NOP_HANDLE 31:0 #define NVB06F_SEMAPHOREA (0x00000010) @@ -47,6 +83,8 @@ #define NVB06F_SEMAPHORED_OPERATION_ACQUIRE 0x00000001 #define NVB06F_SEMAPHORED_OPERATION_RELEASE 0x00000002 #define NVB06F_SEMAPHORED_OPERATION_ACQ_GEQ 0x00000004 +#define NVB06F_SEMAPHORED_OPERATION_ACQ_AND 0x00000008 +#define NVB06F_SEMAPHORED_OPERATION_REDUCTION 0x00000010 #define NVB06F_SEMAPHORED_ACQUIRE_SWITCH 12:12 #define NVB06F_SEMAPHORED_ACQUIRE_SWITCH_DISABLED 0x00000000 #define NVB06F_SEMAPHORED_ACQUIRE_SWITCH_ENABLED 0x00000001 @@ -56,8 +94,22 @@ #define NVB06F_SEMAPHORED_RELEASE_SIZE 24:24 #define NVB06F_SEMAPHORED_RELEASE_SIZE_16BYTE 0x00000000 #define NVB06F_SEMAPHORED_RELEASE_SIZE_4BYTE 0x00000001 - +#define NVB06F_SEMAPHORED_REDUCTION 30:27 +#define NVB06F_SEMAPHORED_REDUCTION_MIN 0x00000000 +#define NVB06F_SEMAPHORED_REDUCTION_MAX 0x00000001 +#define NVB06F_SEMAPHORED_REDUCTION_XOR 0x00000002 +#define NVB06F_SEMAPHORED_REDUCTION_AND 0x00000003 +#define NVB06F_SEMAPHORED_REDUCTION_OR 0x00000004 +#define NVB06F_SEMAPHORED_REDUCTION_ADD 0x00000005 +#define NVB06F_SEMAPHORED_REDUCTION_INC 0x00000006 +#define NVB06F_SEMAPHORED_REDUCTION_DEC 0x00000007 +#define NVB06F_SEMAPHORED_FORMAT 31:31 +#define NVB06F_SEMAPHORED_FORMAT_SIGNED 0x00000000 +#define NVB06F_SEMAPHORED_FORMAT_UNSIGNED 0x00000001 #define NVB06F_NON_STALL_INTERRUPT (0x00000020) +#define NVB06F_NON_STALL_INTERRUPT_HANDLE 31:0 +#define NVB06F_FB_FLUSH (0x00000024) +#define NVB06F_FB_FLUSH_HANDLE 31:0 // NOTE - MEM_OP_A and MEM_OP_B have been removed for gm20x to make room for // possible future MEM_OP features. MEM_OP_C/D have identical functionality // to the previous MEM_OP_A/B methods. @@ -84,10 +136,27 @@ #define NVB06F_MEM_OP_D_OPERATION_L2_CLEAN_COMPTAGS 0x0000000f #define NVB06F_MEM_OP_D_OPERATION_L2_FLUSH_DIRTY 0x00000010 #define NVB06F_MEM_OP_D_TLB_INVALIDATE_ADDR_HI 7:0 +#define NVB06F_SET_REFERENCE (0x00000050) +#define NVB06F_SET_REFERENCE_COUNT 31:0 #define NVB06F_WFI (0x00000078) +#define NVB06F_WFI_SCOPE 0:0 +#define NVB06F_WFI_SCOPE_CURRENT_SCG_TYPE 0x00000000 +#define NVB06F_WFI_SCOPE_ALL 0x00000001 +#define NVB06F_CRC_CHECK (0x0000007c) +#define NVB06F_CRC_CHECK_VALUE 31:0 +#define NVB06F_YIELD (0x00000080) +#define NVB06F_YIELD_OP 1:0 +#define NVB06F_YIELD_OP_NOP 0x00000000 +#define NVB06F_YIELD_OP_PBDMA_TIMESLICE 0x00000001 +#define NVB06F_YIELD_OP_RUNLIST_TIMESLICE 0x00000002 +#define NVB06F_YIELD_OP_TSG 0x00000003 + /* GPFIFO entry format */ #define NVB06F_GP_ENTRY__SIZE 8 +#define NVB06F_GP_ENTRY0_FETCH 0:0 +#define NVB06F_GP_ENTRY0_FETCH_UNCONDITIONAL 0x00000000 +#define NVB06F_GP_ENTRY0_FETCH_CONDITIONAL 0x00000001 #define NVB06F_GP_ENTRY0_GET 31:2 #define NVB06F_GP_ENTRY0_OPERAND 31:0 #define NVB06F_GP_ENTRY1_GET_HI 7:0 @@ -98,11 +167,38 @@ #define NVB06F_GP_ENTRY1_LEVEL_MAIN 0x00000000 #define NVB06F_GP_ENTRY1_LEVEL_SUBROUTINE 0x00000001 #define NVB06F_GP_ENTRY1_LENGTH 30:10 +#define NVB06F_GP_ENTRY1_SYNC 31:31 +#define NVB06F_GP_ENTRY1_SYNC_PROCEED 0x00000000 +#define NVB06F_GP_ENTRY1_SYNC_WAIT 0x00000001 +#define NVB06F_GP_ENTRY1_OPCODE 7:0 +#define NVB06F_GP_ENTRY1_OPCODE_NOP 0x00000000 +#define NVB06F_GP_ENTRY1_OPCODE_ILLEGAL 0x00000001 +#define NVB06F_GP_ENTRY1_OPCODE_GP_CRC 0x00000002 +#define NVB06F_GP_ENTRY1_OPCODE_PB_CRC 0x00000003 /* dma method formats */ +#define NVB06F_DMA_METHOD_ADDRESS_OLD 12:2 +#define NVB06F_DMA_METHOD_ADDRESS 11:0 +#define NVB06F_DMA_SUBDEVICE_MASK 15:4 +#define NVB06F_DMA_METHOD_SUBCHANNEL 15:13 +#define NVB06F_DMA_TERT_OP 17:16 +#define NVB06F_DMA_TERT_OP_GRP0_INC_METHOD (0x00000000) +#define NVB06F_DMA_TERT_OP_GRP0_SET_SUB_DEV_MASK (0x00000001) +#define NVB06F_DMA_TERT_OP_GRP0_STORE_SUB_DEV_MASK (0x00000002) +#define NVB06F_DMA_TERT_OP_GRP0_USE_SUB_DEV_MASK (0x00000003) +#define NVB06F_DMA_TERT_OP_GRP2_NON_INC_METHOD (0x00000000) +#define NVB06F_DMA_METHOD_COUNT_OLD 28:18 +#define NVB06F_DMA_METHOD_COUNT 28:16 +#define NVB06F_DMA_IMMD_DATA 28:16 #define NVB06F_DMA_SEC_OP 31:29 +#define NVB06F_DMA_SEC_OP_GRP0_USE_TERT (0x00000000) #define NVB06F_DMA_SEC_OP_INC_METHOD (0x00000001) +#define NVB06F_DMA_SEC_OP_GRP2_USE_TERT (0x00000002) #define NVB06F_DMA_SEC_OP_NON_INC_METHOD (0x00000003) +#define NVB06F_DMA_SEC_OP_IMMD_DATA_METHOD (0x00000004) +#define NVB06F_DMA_SEC_OP_ONE_INC (0x00000005) +#define NVB06F_DMA_SEC_OP_RESERVED6 (0x00000006) +#define NVB06F_DMA_SEC_OP_END_PB_SEGMENT (0x00000007) /* dma incrementing method format */ #define NVB06F_DMA_INCR_ADDRESS 11:0 #define NVB06F_DMA_INCR_SUBCHANNEL 15:13 @@ -132,9 +228,33 @@ #define NVB06F_DMA_IMMD_DATA 28:16 #define NVB06F_DMA_IMMD_OPCODE 31:29 #define NVB06F_DMA_IMMD_OPCODE_VALUE (0x00000004) +/* dma set sub-device mask format */ +#define NVB06F_DMA_SET_SUBDEVICE_MASK_VALUE 15:4 +#define NVB06F_DMA_SET_SUBDEVICE_MASK_OPCODE 31:16 +#define NVB06F_DMA_SET_SUBDEVICE_MASK_OPCODE_VALUE (0x00000001) +/* dma store sub-device mask format */ +#define NVB06F_DMA_STORE_SUBDEVICE_MASK_VALUE 15:4 +#define NVB06F_DMA_STORE_SUBDEVICE_MASK_OPCODE 31:16 +#define NVB06F_DMA_STORE_SUBDEVICE_MASK_OPCODE_VALUE (0x00000002) +/* dma use sub-device mask format */ +#define NVB06F_DMA_USE_SUBDEVICE_MASK_OPCODE 31:16 +#define NVB06F_DMA_USE_SUBDEVICE_MASK_OPCODE_VALUE (0x00000003) +/* dma end-segment format */ +#define NVB06F_DMA_ENDSEG_OPCODE 31:29 +#define NVB06F_DMA_ENDSEG_OPCODE_VALUE (0x00000007) +/* dma legacy incrementing/non-incrementing formats */ +#define NVB06F_DMA_ADDRESS 12:2 +#define NVB06F_DMA_SUBCH 15:13 +#define NVB06F_DMA_OPCODE3 17:16 +#define NVB06F_DMA_OPCODE3_NONE (0x00000000) +#define NVB06F_DMA_COUNT 28:18 +#define NVB06F_DMA_OPCODE 31:29 +#define NVB06F_DMA_OPCODE_METHOD (0x00000000) +#define NVB06F_DMA_OPCODE_NONINC_METHOD (0x00000002) +#define NVB06F_DMA_DATA 31:0 #ifdef __cplusplus }; /* extern "C" */ #endif -#endif /* _clB06F_h_ */ +#endif /* _clb06f_h_ */ diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/kernel-open/nvidia-uvm/clb0b5.h nvidia-open-gpu-kernel-modules-535.161.08/kernel-open/nvidia-uvm/clb0b5.h --- nvidia-open-gpu-kernel-modules-525.147.05/kernel-open/nvidia-uvm/clb0b5.h 2023-10-25 20:33:28.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/kernel-open/nvidia-uvm/clb0b5.h 2024-03-05 22:25:42.000000000 +0000 @@ -1,19 +1,19 @@ /******************************************************************************* - Copyright (c) 2014 NVIDIA Corporation + Copyright (c) 2019, NVIDIA CORPORATION. All rights reserved. - Permission is hereby granted, free of charge, to any person obtaining a copy - of this software and associated documentation files (the "Software"), to - deal in the Software without restriction, including without limitation the - rights to use, copy, modify, merge, publish, distribute, sublicense, and/or - sell copies of the Software, and to permit persons to whom the Software is - furnished to do so, subject to the following conditions: + Permission is hereby granted, free of charge, to any person obtaining a + copy of this software and associated documentation files (the "Software"), + to deal in the Software without restriction, including without limitation + the rights to use, copy, modify, merge, publish, distribute, sublicense, + and/or sell copies of the Software, and to permit persons to whom the + Software is furnished to do so, subject to the following conditions: - The above copyright notice and this permission notice shall be - included in all copies or substantial portions of the Software. + The above copyright notice and this permission notice shall be included in + all copies or substantial portions of the Software. THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER @@ -32,6 +32,10 @@ #define MAXWELL_DMA_COPY_A (0x0000B0B5) +#define NVB0B5_NOP (0x00000100) +#define NVB0B5_NOP_PARAMETER 31:0 +#define NVB0B5_PM_TRIGGER (0x00000140) +#define NVB0B5_PM_TRIGGER_V 31:0 #define NVB0B5_SET_SEMAPHORE_A (0x00000240) #define NVB0B5_SET_SEMAPHORE_A_UPPER 7:0 #define NVB0B5_SET_SEMAPHORE_B (0x00000244) @@ -183,9 +187,75 @@ #define NVB0B5_SET_REMAP_COMPONENTS_NUM_DST_COMPONENTS_TWO (0x00000001) #define NVB0B5_SET_REMAP_COMPONENTS_NUM_DST_COMPONENTS_THREE (0x00000002) #define NVB0B5_SET_REMAP_COMPONENTS_NUM_DST_COMPONENTS_FOUR (0x00000003) - +#define NVB0B5_SET_DST_BLOCK_SIZE (0x0000070C) +#define NVB0B5_SET_DST_BLOCK_SIZE_WIDTH 3:0 +#define NVB0B5_SET_DST_BLOCK_SIZE_WIDTH_QUARTER_GOB (0x0000000E) +#define NVB0B5_SET_DST_BLOCK_SIZE_WIDTH_ONE_GOB (0x00000000) +#define NVB0B5_SET_DST_BLOCK_SIZE_HEIGHT 7:4 +#define NVB0B5_SET_DST_BLOCK_SIZE_HEIGHT_ONE_GOB (0x00000000) +#define NVB0B5_SET_DST_BLOCK_SIZE_HEIGHT_TWO_GOBS (0x00000001) +#define NVB0B5_SET_DST_BLOCK_SIZE_HEIGHT_FOUR_GOBS (0x00000002) +#define NVB0B5_SET_DST_BLOCK_SIZE_HEIGHT_EIGHT_GOBS (0x00000003) +#define NVB0B5_SET_DST_BLOCK_SIZE_HEIGHT_SIXTEEN_GOBS (0x00000004) +#define NVB0B5_SET_DST_BLOCK_SIZE_HEIGHT_THIRTYTWO_GOBS (0x00000005) +#define NVB0B5_SET_DST_BLOCK_SIZE_DEPTH 11:8 +#define NVB0B5_SET_DST_BLOCK_SIZE_DEPTH_ONE_GOB (0x00000000) +#define NVB0B5_SET_DST_BLOCK_SIZE_DEPTH_TWO_GOBS (0x00000001) +#define NVB0B5_SET_DST_BLOCK_SIZE_DEPTH_FOUR_GOBS (0x00000002) +#define NVB0B5_SET_DST_BLOCK_SIZE_DEPTH_EIGHT_GOBS (0x00000003) +#define NVB0B5_SET_DST_BLOCK_SIZE_DEPTH_SIXTEEN_GOBS (0x00000004) +#define NVB0B5_SET_DST_BLOCK_SIZE_DEPTH_THIRTYTWO_GOBS (0x00000005) +#define NVB0B5_SET_DST_BLOCK_SIZE_GOB_HEIGHT 15:12 +#define NVB0B5_SET_DST_BLOCK_SIZE_GOB_HEIGHT_GOB_HEIGHT_TESLA_4 (0x00000000) +#define NVB0B5_SET_DST_BLOCK_SIZE_GOB_HEIGHT_GOB_HEIGHT_FERMI_8 (0x00000001) +#define NVB0B5_SET_DST_WIDTH (0x00000710) +#define NVB0B5_SET_DST_WIDTH_V 31:0 +#define NVB0B5_SET_DST_HEIGHT (0x00000714) +#define NVB0B5_SET_DST_HEIGHT_V 31:0 +#define NVB0B5_SET_DST_DEPTH (0x00000718) +#define NVB0B5_SET_DST_DEPTH_V 31:0 +#define NVB0B5_SET_DST_LAYER (0x0000071C) +#define NVB0B5_SET_DST_LAYER_V 31:0 +#define NVB0B5_SET_DST_ORIGIN (0x00000720) +#define NVB0B5_SET_DST_ORIGIN_X 15:0 +#define NVB0B5_SET_DST_ORIGIN_Y 31:16 +#define NVB0B5_SET_SRC_BLOCK_SIZE (0x00000728) +#define NVB0B5_SET_SRC_BLOCK_SIZE_WIDTH 3:0 +#define NVB0B5_SET_SRC_BLOCK_SIZE_WIDTH_QUARTER_GOB (0x0000000E) +#define NVB0B5_SET_SRC_BLOCK_SIZE_WIDTH_ONE_GOB (0x00000000) +#define NVB0B5_SET_SRC_BLOCK_SIZE_HEIGHT 7:4 +#define NVB0B5_SET_SRC_BLOCK_SIZE_HEIGHT_ONE_GOB (0x00000000) +#define NVB0B5_SET_SRC_BLOCK_SIZE_HEIGHT_TWO_GOBS (0x00000001) +#define NVB0B5_SET_SRC_BLOCK_SIZE_HEIGHT_FOUR_GOBS (0x00000002) +#define NVB0B5_SET_SRC_BLOCK_SIZE_HEIGHT_EIGHT_GOBS (0x00000003) +#define NVB0B5_SET_SRC_BLOCK_SIZE_HEIGHT_SIXTEEN_GOBS (0x00000004) +#define NVB0B5_SET_SRC_BLOCK_SIZE_HEIGHT_THIRTYTWO_GOBS (0x00000005) +#define NVB0B5_SET_SRC_BLOCK_SIZE_DEPTH 11:8 +#define NVB0B5_SET_SRC_BLOCK_SIZE_DEPTH_ONE_GOB (0x00000000) +#define NVB0B5_SET_SRC_BLOCK_SIZE_DEPTH_TWO_GOBS (0x00000001) +#define NVB0B5_SET_SRC_BLOCK_SIZE_DEPTH_FOUR_GOBS (0x00000002) +#define NVB0B5_SET_SRC_BLOCK_SIZE_DEPTH_EIGHT_GOBS (0x00000003) +#define NVB0B5_SET_SRC_BLOCK_SIZE_DEPTH_SIXTEEN_GOBS (0x00000004) +#define NVB0B5_SET_SRC_BLOCK_SIZE_DEPTH_THIRTYTWO_GOBS (0x00000005) +#define NVB0B5_SET_SRC_BLOCK_SIZE_GOB_HEIGHT 15:12 +#define NVB0B5_SET_SRC_BLOCK_SIZE_GOB_HEIGHT_GOB_HEIGHT_TESLA_4 (0x00000000) +#define NVB0B5_SET_SRC_BLOCK_SIZE_GOB_HEIGHT_GOB_HEIGHT_FERMI_8 (0x00000001) +#define NVB0B5_SET_SRC_WIDTH (0x0000072C) +#define NVB0B5_SET_SRC_WIDTH_V 31:0 +#define NVB0B5_SET_SRC_HEIGHT (0x00000730) +#define NVB0B5_SET_SRC_HEIGHT_V 31:0 +#define NVB0B5_SET_SRC_DEPTH (0x00000734) +#define NVB0B5_SET_SRC_DEPTH_V 31:0 +#define NVB0B5_SET_SRC_LAYER (0x00000738) +#define NVB0B5_SET_SRC_LAYER_V 31:0 +#define NVB0B5_SET_SRC_ORIGIN (0x0000073C) +#define NVB0B5_SET_SRC_ORIGIN_X 15:0 +#define NVB0B5_SET_SRC_ORIGIN_Y 31:16 +#define NVB0B5_PM_TRIGGER_END (0x00001114) +#define NVB0B5_PM_TRIGGER_END_V 31:0 #ifdef __cplusplus }; /* extern "C" */ #endif #endif // _clb0b5_h + diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/kernel-open/nvidia-uvm/clc06f.h nvidia-open-gpu-kernel-modules-535.161.08/kernel-open/nvidia-uvm/clc06f.h --- nvidia-open-gpu-kernel-modules-525.147.05/kernel-open/nvidia-uvm/clc06f.h 2023-10-25 20:33:28.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/kernel-open/nvidia-uvm/clc06f.h 2024-03-05 22:25:42.000000000 +0000 @@ -1,25 +1,25 @@ -/******************************************************************************* - Copyright (c) 2014 NVIDIA Corporation - - Permission is hereby granted, free of charge, to any person obtaining a copy - of this software and associated documentation files (the "Software"), to - deal in the Software without restriction, including without limitation the - rights to use, copy, modify, merge, publish, distribute, sublicense, and/or - sell copies of the Software, and to permit persons to whom the Software is - furnished to do so, subject to the following conditions: - - The above copyright notice and this permission notice shall be - included in all copies or substantial portions of the Software. - - THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER - DEALINGS IN THE SOFTWARE. - -*******************************************************************************/ +/* + * SPDX-FileCopyrightText: Copyright (c) 2020-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ #ifndef _clc06f_h_ #define _clc06f_h_ @@ -30,10 +30,47 @@ #include "nvtypes.h" +/* class PASCAL_CHANNEL_GPFIFO */ +/* + * Documentation for PASCAL_CHANNEL_GPFIFO can be found in dev_pbdma.ref, + * chapter "User Control Registers". It is documented as device NV_UDMA. + * The GPFIFO format itself is also documented in dev_pbdma.ref, + * NV_PPBDMA_GP_ENTRY_*. The pushbuffer format is documented in dev_ram.ref, + * chapter "FIFO DMA RAM", NV_FIFO_DMA_*. + * + * Note there is no .mfs file for this class. + */ #define PASCAL_CHANNEL_GPFIFO_A (0x0000C06F) -/* class PASCAL_CHANNEL_GPFIFO_A */ +#define NVC06F_TYPEDEF PASCAL_CHANNELChannelGPFifoA + +/* dma flow control data structure */ +typedef volatile struct Nvc06fControl_struct { + NvU32 Ignored00[0x010]; /* 0000-003f*/ + NvU32 Put; /* put offset, read/write 0040-0043*/ + NvU32 Get; /* get offset, read only 0044-0047*/ + NvU32 Reference; /* reference value, read only 0048-004b*/ + NvU32 PutHi; /* high order put offset bits 004c-004f*/ + NvU32 Ignored01[0x002]; /* 0050-0057*/ + NvU32 TopLevelGet; /* top level get offset, read only 0058-005b*/ + NvU32 TopLevelGetHi; /* high order top level get bits 005c-005f*/ + NvU32 GetHi; /* high order get offset bits 0060-0063*/ + NvU32 Ignored02[0x007]; /* 0064-007f*/ + NvU32 Ignored03; /* used to be engine yield 0080-0083*/ + NvU32 Ignored04[0x001]; /* 0084-0087*/ + NvU32 GPGet; /* GP FIFO get offset, read only 0088-008b*/ + NvU32 GPPut; /* GP FIFO put offset 008c-008f*/ + NvU32 Ignored05[0x5c]; +} Nvc06fControl, PascalAControlGPFifo; + +/* fields and values */ +#define NVC06F_NUMBER_OF_SUBCHANNELS (8) #define NVC06F_SET_OBJECT (0x00000000) +#define NVC06F_SET_OBJECT_NVCLASS 15:0 +#define NVC06F_SET_OBJECT_ENGINE 20:16 +#define NVC06F_SET_OBJECT_ENGINE_SW 0x0000001f +#define NVC06F_ILLEGAL (0x00000004) +#define NVC06F_ILLEGAL_HANDLE 31:0 #define NVC06F_NOP (0x00000008) #define NVC06F_NOP_HANDLE 31:0 #define NVC06F_SEMAPHOREA (0x00000010) @@ -47,54 +84,33 @@ #define NVC06F_SEMAPHORED_OPERATION_ACQUIRE 0x00000001 #define NVC06F_SEMAPHORED_OPERATION_RELEASE 0x00000002 #define NVC06F_SEMAPHORED_OPERATION_ACQ_GEQ 0x00000004 +#define NVC06F_SEMAPHORED_OPERATION_ACQ_AND 0x00000008 +#define NVC06F_SEMAPHORED_OPERATION_REDUCTION 0x00000010 #define NVC06F_SEMAPHORED_ACQUIRE_SWITCH 12:12 #define NVC06F_SEMAPHORED_ACQUIRE_SWITCH_DISABLED 0x00000000 #define NVC06F_SEMAPHORED_ACQUIRE_SWITCH_ENABLED 0x00000001 - - -/* GPFIFO entry format */ -#define NVC06F_GP_ENTRY__SIZE 8 -#define NVC06F_GP_ENTRY0_GET 31:2 -#define NVC06F_GP_ENTRY0_OPERAND 31:0 -#define NVC06F_GP_ENTRY1_GET_HI 7:0 -#define NVC06F_GP_ENTRY1_PRIV 8:8 -#define NVC06F_GP_ENTRY1_PRIV_USER 0x00000000 -#define NVC06F_GP_ENTRY1_PRIV_KERNEL 0x00000001 -#define NVC06F_GP_ENTRY1_LEVEL 9:9 -#define NVC06F_GP_ENTRY1_LEVEL_MAIN 0x00000000 -#define NVC06F_GP_ENTRY1_LEVEL_SUBROUTINE 0x00000001 -#define NVC06F_GP_ENTRY1_LENGTH 30:10 - -/* dma incrementing method format */ -#define NVC06F_DMA_INCR_ADDRESS 11:0 -#define NVC06F_DMA_INCR_SUBCHANNEL 15:13 -#define NVC06F_DMA_INCR_COUNT 28:16 -#define NVC06F_DMA_INCR_OPCODE 31:29 -#define NVC06F_DMA_INCR_OPCODE_VALUE (0x00000001) -#define NVC06F_DMA_INCR_DATA 31:0 -/* dma non-incrementing method format */ -#define NVC06F_DMA_NONINCR_ADDRESS 11:0 -#define NVC06F_DMA_NONINCR_SUBCHANNEL 15:13 -#define NVC06F_DMA_NONINCR_COUNT 28:16 -#define NVC06F_DMA_NONINCR_OPCODE 31:29 -#define NVC06F_DMA_NONINCR_OPCODE_VALUE (0x00000003) -#define NVC06F_DMA_NONINCR_DATA 31:0 -/* dma increment-once method format */ -#define NVC06F_DMA_ONEINCR_ADDRESS 11:0 -#define NVC06F_DMA_ONEINCR_SUBCHANNEL 15:13 -#define NVC06F_DMA_ONEINCR_COUNT 28:16 -#define NVC06F_DMA_ONEINCR_OPCODE 31:29 -#define NVC06F_DMA_ONEINCR_OPCODE_VALUE (0x00000005) -#define NVC06F_DMA_ONEINCR_DATA 31:0 -/* dma no-operation format */ -#define NVC06F_DMA_NOP (0x00000000) -/* dma immediate-data format */ -#define NVC06F_DMA_IMMD_ADDRESS 11:0 -#define NVC06F_DMA_IMMD_SUBCHANNEL 15:13 -#define NVC06F_DMA_IMMD_DATA 28:16 -#define NVC06F_DMA_IMMD_OPCODE 31:29 -#define NVC06F_DMA_IMMD_OPCODE_VALUE (0x00000004) - +#define NVC06F_SEMAPHORED_RELEASE_WFI 20:20 +#define NVC06F_SEMAPHORED_RELEASE_WFI_EN 0x00000000 +#define NVC06F_SEMAPHORED_RELEASE_WFI_DIS 0x00000001 +#define NVC06F_SEMAPHORED_RELEASE_SIZE 24:24 +#define NVC06F_SEMAPHORED_RELEASE_SIZE_16BYTE 0x00000000 +#define NVC06F_SEMAPHORED_RELEASE_SIZE_4BYTE 0x00000001 +#define NVC06F_SEMAPHORED_REDUCTION 30:27 +#define NVC06F_SEMAPHORED_REDUCTION_MIN 0x00000000 +#define NVC06F_SEMAPHORED_REDUCTION_MAX 0x00000001 +#define NVC06F_SEMAPHORED_REDUCTION_XOR 0x00000002 +#define NVC06F_SEMAPHORED_REDUCTION_AND 0x00000003 +#define NVC06F_SEMAPHORED_REDUCTION_OR 0x00000004 +#define NVC06F_SEMAPHORED_REDUCTION_ADD 0x00000005 +#define NVC06F_SEMAPHORED_REDUCTION_INC 0x00000006 +#define NVC06F_SEMAPHORED_REDUCTION_DEC 0x00000007 +#define NVC06F_SEMAPHORED_FORMAT 31:31 +#define NVC06F_SEMAPHORED_FORMAT_SIGNED 0x00000000 +#define NVC06F_SEMAPHORED_FORMAT_UNSIGNED 0x00000001 +#define NVC06F_NON_STALL_INTERRUPT (0x00000020) +#define NVC06F_NON_STALL_INTERRUPT_HANDLE 31:0 +#define NVC06F_FB_FLUSH (0x00000024) // Deprecated - use MEMBAR TYPE SYS_MEMBAR +#define NVC06F_FB_FLUSH_HANDLE 31:0 // NOTE - MEM_OP_A and MEM_OP_B have been replaced in gp100 with methods for // specifying the page address for a targeted TLB invalidate and the uTLB for // a targeted REPLAY_CANCEL for UVM. @@ -153,19 +169,142 @@ #define NVC06F_MEM_OP_D_OPERATION_L2_PEERMEM_INVALIDATE 0x0000000d #define NVC06F_MEM_OP_D_OPERATION_L2_SYSMEM_INVALIDATE 0x0000000e // CLEAN_LINES is an alias for Tegra/GPU IP usage +#define NVC06F_MEM_OP_D_OPERATION_L2_INVALIDATE_CLEAN_LINES 0x0000000e +// This B alias is confusing but it was missed as part of the update. Left here +// for compatibility. #define NVC06F_MEM_OP_B_OPERATION_L2_INVALIDATE_CLEAN_LINES 0x0000000e #define NVC06F_MEM_OP_D_OPERATION_L2_CLEAN_COMPTAGS 0x0000000f #define NVC06F_MEM_OP_D_OPERATION_L2_FLUSH_DIRTY 0x00000010 #define NVC06F_MEM_OP_D_OPERATION_L2_WAIT_FOR_SYS_PENDING_READS 0x00000015 #define NVC06F_SET_REFERENCE (0x00000050) #define NVC06F_SET_REFERENCE_COUNT 31:0 - +// Syncpoint methods are only available on Tegra parts. Attempting to use +// them on discrete GPUs will result in Host raising NV_PPBDMA_INTR_0_METHOD. +#define NVC06F_SYNCPOINTA (0x00000070) +#define NVC06F_SYNCPOINTA_PAYLOAD 31:0 +#define NVC06F_SYNCPOINTB (0x00000074) +#define NVC06F_SYNCPOINTB_OPERATION 0:0 +#define NVC06F_SYNCPOINTB_OPERATION_WAIT 0x00000000 +#define NVC06F_SYNCPOINTB_OPERATION_INCR 0x00000001 +#define NVC06F_SYNCPOINTB_WAIT_SWITCH 4:4 +#define NVC06F_SYNCPOINTB_WAIT_SWITCH_DIS 0x00000000 +#define NVC06F_SYNCPOINTB_WAIT_SWITCH_EN 0x00000001 +#define NVC06F_SYNCPOINTB_SYNCPT_INDEX 19:8 #define NVC06F_WFI (0x00000078) #define NVC06F_WFI_SCOPE 0:0 #define NVC06F_WFI_SCOPE_CURRENT_SCG_TYPE 0x00000000 #define NVC06F_WFI_SCOPE_ALL 0x00000001 +#define NVC06F_CRC_CHECK (0x0000007c) +#define NVC06F_CRC_CHECK_VALUE 31:0 +#define NVC06F_YIELD (0x00000080) +#define NVC06F_YIELD_OP 1:0 +#define NVC06F_YIELD_OP_NOP 0x00000000 +#define NVC06F_YIELD_OP_PBDMA_TIMESLICE 0x00000001 +#define NVC06F_YIELD_OP_RUNLIST_TIMESLICE 0x00000002 +#define NVC06F_YIELD_OP_TSG 0x00000003 +/* GPFIFO entry format */ +#define NVC06F_GP_ENTRY__SIZE 8 +#define NVC06F_GP_ENTRY0_FETCH 0:0 +#define NVC06F_GP_ENTRY0_FETCH_UNCONDITIONAL 0x00000000 +#define NVC06F_GP_ENTRY0_FETCH_CONDITIONAL 0x00000001 +#define NVC06F_GP_ENTRY0_GET 31:2 +#define NVC06F_GP_ENTRY0_OPERAND 31:0 +#define NVC06F_GP_ENTRY1_GET_HI 7:0 +#define NVC06F_GP_ENTRY1_PRIV 8:8 +#define NVC06F_GP_ENTRY1_PRIV_USER 0x00000000 +#define NVC06F_GP_ENTRY1_PRIV_KERNEL 0x00000001 +#define NVC06F_GP_ENTRY1_LEVEL 9:9 +#define NVC06F_GP_ENTRY1_LEVEL_MAIN 0x00000000 +#define NVC06F_GP_ENTRY1_LEVEL_SUBROUTINE 0x00000001 +#define NVC06F_GP_ENTRY1_LENGTH 30:10 +#define NVC06F_GP_ENTRY1_SYNC 31:31 +#define NVC06F_GP_ENTRY1_SYNC_PROCEED 0x00000000 +#define NVC06F_GP_ENTRY1_SYNC_WAIT 0x00000001 +#define NVC06F_GP_ENTRY1_OPCODE 7:0 +#define NVC06F_GP_ENTRY1_OPCODE_NOP 0x00000000 +#define NVC06F_GP_ENTRY1_OPCODE_ILLEGAL 0x00000001 +#define NVC06F_GP_ENTRY1_OPCODE_GP_CRC 0x00000002 +#define NVC06F_GP_ENTRY1_OPCODE_PB_CRC 0x00000003 + +/* dma method formats */ +#define NVC06F_DMA_METHOD_ADDRESS_OLD 12:2 +#define NVC06F_DMA_METHOD_ADDRESS 11:0 +#define NVC06F_DMA_SUBDEVICE_MASK 15:4 +#define NVC06F_DMA_METHOD_SUBCHANNEL 15:13 +#define NVC06F_DMA_TERT_OP 17:16 +#define NVC06F_DMA_TERT_OP_GRP0_INC_METHOD (0x00000000) +#define NVC06F_DMA_TERT_OP_GRP0_SET_SUB_DEV_MASK (0x00000001) +#define NVC06F_DMA_TERT_OP_GRP0_STORE_SUB_DEV_MASK (0x00000002) +#define NVC06F_DMA_TERT_OP_GRP0_USE_SUB_DEV_MASK (0x00000003) +#define NVC06F_DMA_TERT_OP_GRP2_NON_INC_METHOD (0x00000000) +#define NVC06F_DMA_METHOD_COUNT_OLD 28:18 +#define NVC06F_DMA_METHOD_COUNT 28:16 +#define NVC06F_DMA_IMMD_DATA 28:16 +#define NVC06F_DMA_SEC_OP 31:29 +#define NVC06F_DMA_SEC_OP_GRP0_USE_TERT (0x00000000) +#define NVC06F_DMA_SEC_OP_INC_METHOD (0x00000001) +#define NVC06F_DMA_SEC_OP_GRP2_USE_TERT (0x00000002) +#define NVC06F_DMA_SEC_OP_NON_INC_METHOD (0x00000003) +#define NVC06F_DMA_SEC_OP_IMMD_DATA_METHOD (0x00000004) +#define NVC06F_DMA_SEC_OP_ONE_INC (0x00000005) +#define NVC06F_DMA_SEC_OP_RESERVED6 (0x00000006) +#define NVC06F_DMA_SEC_OP_END_PB_SEGMENT (0x00000007) +/* dma incrementing method format */ +#define NVC06F_DMA_INCR_ADDRESS 11:0 +#define NVC06F_DMA_INCR_SUBCHANNEL 15:13 +#define NVC06F_DMA_INCR_COUNT 28:16 +#define NVC06F_DMA_INCR_OPCODE 31:29 +#define NVC06F_DMA_INCR_OPCODE_VALUE (0x00000001) +#define NVC06F_DMA_INCR_DATA 31:0 +/* dma non-incrementing method format */ +#define NVC06F_DMA_NONINCR_ADDRESS 11:0 +#define NVC06F_DMA_NONINCR_SUBCHANNEL 15:13 +#define NVC06F_DMA_NONINCR_COUNT 28:16 +#define NVC06F_DMA_NONINCR_OPCODE 31:29 +#define NVC06F_DMA_NONINCR_OPCODE_VALUE (0x00000003) +#define NVC06F_DMA_NONINCR_DATA 31:0 +/* dma increment-once method format */ +#define NVC06F_DMA_ONEINCR_ADDRESS 11:0 +#define NVC06F_DMA_ONEINCR_SUBCHANNEL 15:13 +#define NVC06F_DMA_ONEINCR_COUNT 28:16 +#define NVC06F_DMA_ONEINCR_OPCODE 31:29 +#define NVC06F_DMA_ONEINCR_OPCODE_VALUE (0x00000005) +#define NVC06F_DMA_ONEINCR_DATA 31:0 +/* dma no-operation format */ +#define NVC06F_DMA_NOP (0x00000000) +/* dma immediate-data format */ +#define NVC06F_DMA_IMMD_ADDRESS 11:0 +#define NVC06F_DMA_IMMD_SUBCHANNEL 15:13 +#define NVC06F_DMA_IMMD_DATA 28:16 +#define NVC06F_DMA_IMMD_OPCODE 31:29 +#define NVC06F_DMA_IMMD_OPCODE_VALUE (0x00000004) +/* dma set sub-device mask format */ +#define NVC06F_DMA_SET_SUBDEVICE_MASK_VALUE 15:4 +#define NVC06F_DMA_SET_SUBDEVICE_MASK_OPCODE 31:16 +#define NVC06F_DMA_SET_SUBDEVICE_MASK_OPCODE_VALUE (0x00000001) +/* dma store sub-device mask format */ +#define NVC06F_DMA_STORE_SUBDEVICE_MASK_VALUE 15:4 +#define NVC06F_DMA_STORE_SUBDEVICE_MASK_OPCODE 31:16 +#define NVC06F_DMA_STORE_SUBDEVICE_MASK_OPCODE_VALUE (0x00000002) +/* dma use sub-device mask format */ +#define NVC06F_DMA_USE_SUBDEVICE_MASK_OPCODE 31:16 +#define NVC06F_DMA_USE_SUBDEVICE_MASK_OPCODE_VALUE (0x00000003) +/* dma end-segment format */ +#define NVC06F_DMA_ENDSEG_OPCODE 31:29 +#define NVC06F_DMA_ENDSEG_OPCODE_VALUE (0x00000007) +/* dma legacy incrementing/non-incrementing formats */ +#define NVC06F_DMA_ADDRESS 12:2 +#define NVC06F_DMA_SUBCH 15:13 +#define NVC06F_DMA_OPCODE3 17:16 +#define NVC06F_DMA_OPCODE3_NONE (0x00000000) +#define NVC06F_DMA_COUNT 28:18 +#define NVC06F_DMA_OPCODE 31:29 +#define NVC06F_DMA_OPCODE_METHOD (0x00000000) +#define NVC06F_DMA_OPCODE_NONINC_METHOD (0x00000002) +#define NVC06F_DMA_DATA 31:0 + #ifdef __cplusplus }; /* extern "C" */ #endif diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/kernel-open/nvidia-uvm/clc0b5.h nvidia-open-gpu-kernel-modules-535.161.08/kernel-open/nvidia-uvm/clc0b5.h --- nvidia-open-gpu-kernel-modules-525.147.05/kernel-open/nvidia-uvm/clc0b5.h 2023-10-25 20:33:28.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/kernel-open/nvidia-uvm/clc0b5.h 2024-03-05 22:25:42.000000000 +0000 @@ -1,19 +1,19 @@ /******************************************************************************* - Copyright (c) 2014 NVIDIA Corporation + Copyright (c) 2019, NVIDIA CORPORATION. All rights reserved. - Permission is hereby granted, free of charge, to any person obtaining a copy - of this software and associated documentation files (the "Software"), to - deal in the Software without restriction, including without limitation the - rights to use, copy, modify, merge, publish, distribute, sublicense, and/or - sell copies of the Software, and to permit persons to whom the Software is - furnished to do so, subject to the following conditions: + Permission is hereby granted, free of charge, to any person obtaining a + copy of this software and associated documentation files (the "Software"), + to deal in the Software without restriction, including without limitation + the rights to use, copy, modify, merge, publish, distribute, sublicense, + and/or sell copies of the Software, and to permit persons to whom the + Software is furnished to do so, subject to the following conditions: - The above copyright notice and this permission notice shall be - included in all copies or substantial portions of the Software. + The above copyright notice and this permission notice shall be included in + all copies or substantial portions of the Software. THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER @@ -32,6 +32,10 @@ #define PASCAL_DMA_COPY_A (0x0000C0B5) +#define NVC0B5_NOP (0x00000100) +#define NVC0B5_NOP_PARAMETER 31:0 +#define NVC0B5_PM_TRIGGER (0x00000140) +#define NVC0B5_PM_TRIGGER_V 31:0 #define NVC0B5_SET_SEMAPHORE_A (0x00000240) #define NVC0B5_SET_SEMAPHORE_A_UPPER 16:0 #define NVC0B5_SET_SEMAPHORE_B (0x00000244) @@ -115,6 +119,10 @@ #define NVC0B5_LAUNCH_DMA_SRC_BYPASS_L2 20:20 #define NVC0B5_LAUNCH_DMA_SRC_BYPASS_L2_USE_PTE_SETTING (0x00000000) #define NVC0B5_LAUNCH_DMA_SRC_BYPASS_L2_FORCE_VOLATILE (0x00000001) +#define NVC0B5_LAUNCH_DMA_DST_BYPASS_L2 21:21 +#define NVC0B5_LAUNCH_DMA_DST_BYPASS_L2_USE_PTE_SETTING (0x00000000) +#define NVC0B5_LAUNCH_DMA_DST_BYPASS_L2_FORCE_VOLATILE (0x00000001) +#define NVC0B5_LAUNCH_DMA_RESERVED 31:28 #define NVC0B5_OFFSET_IN_UPPER (0x00000400) #define NVC0B5_OFFSET_IN_UPPER_UPPER 16:0 #define NVC0B5_OFFSET_IN_LOWER (0x00000404) @@ -183,6 +191,68 @@ #define NVC0B5_SET_REMAP_COMPONENTS_NUM_DST_COMPONENTS_TWO (0x00000001) #define NVC0B5_SET_REMAP_COMPONENTS_NUM_DST_COMPONENTS_THREE (0x00000002) #define NVC0B5_SET_REMAP_COMPONENTS_NUM_DST_COMPONENTS_FOUR (0x00000003) +#define NVC0B5_SET_DST_BLOCK_SIZE (0x0000070C) +#define NVC0B5_SET_DST_BLOCK_SIZE_WIDTH 3:0 +#define NVC0B5_SET_DST_BLOCK_SIZE_WIDTH_ONE_GOB (0x00000000) +#define NVC0B5_SET_DST_BLOCK_SIZE_HEIGHT 7:4 +#define NVC0B5_SET_DST_BLOCK_SIZE_HEIGHT_ONE_GOB (0x00000000) +#define NVC0B5_SET_DST_BLOCK_SIZE_HEIGHT_TWO_GOBS (0x00000001) +#define NVC0B5_SET_DST_BLOCK_SIZE_HEIGHT_FOUR_GOBS (0x00000002) +#define NVC0B5_SET_DST_BLOCK_SIZE_HEIGHT_EIGHT_GOBS (0x00000003) +#define NVC0B5_SET_DST_BLOCK_SIZE_HEIGHT_SIXTEEN_GOBS (0x00000004) +#define NVC0B5_SET_DST_BLOCK_SIZE_HEIGHT_THIRTYTWO_GOBS (0x00000005) +#define NVC0B5_SET_DST_BLOCK_SIZE_DEPTH 11:8 +#define NVC0B5_SET_DST_BLOCK_SIZE_DEPTH_ONE_GOB (0x00000000) +#define NVC0B5_SET_DST_BLOCK_SIZE_DEPTH_TWO_GOBS (0x00000001) +#define NVC0B5_SET_DST_BLOCK_SIZE_DEPTH_FOUR_GOBS (0x00000002) +#define NVC0B5_SET_DST_BLOCK_SIZE_DEPTH_EIGHT_GOBS (0x00000003) +#define NVC0B5_SET_DST_BLOCK_SIZE_DEPTH_SIXTEEN_GOBS (0x00000004) +#define NVC0B5_SET_DST_BLOCK_SIZE_DEPTH_THIRTYTWO_GOBS (0x00000005) +#define NVC0B5_SET_DST_BLOCK_SIZE_GOB_HEIGHT 15:12 +#define NVC0B5_SET_DST_BLOCK_SIZE_GOB_HEIGHT_GOB_HEIGHT_FERMI_8 (0x00000001) +#define NVC0B5_SET_DST_WIDTH (0x00000710) +#define NVC0B5_SET_DST_WIDTH_V 31:0 +#define NVC0B5_SET_DST_HEIGHT (0x00000714) +#define NVC0B5_SET_DST_HEIGHT_V 31:0 +#define NVC0B5_SET_DST_DEPTH (0x00000718) +#define NVC0B5_SET_DST_DEPTH_V 31:0 +#define NVC0B5_SET_DST_LAYER (0x0000071C) +#define NVC0B5_SET_DST_LAYER_V 31:0 +#define NVC0B5_SET_DST_ORIGIN (0x00000720) +#define NVC0B5_SET_DST_ORIGIN_X 15:0 +#define NVC0B5_SET_DST_ORIGIN_Y 31:16 +#define NVC0B5_SET_SRC_BLOCK_SIZE (0x00000728) +#define NVC0B5_SET_SRC_BLOCK_SIZE_WIDTH 3:0 +#define NVC0B5_SET_SRC_BLOCK_SIZE_WIDTH_ONE_GOB (0x00000000) +#define NVC0B5_SET_SRC_BLOCK_SIZE_HEIGHT 7:4 +#define NVC0B5_SET_SRC_BLOCK_SIZE_HEIGHT_ONE_GOB (0x00000000) +#define NVC0B5_SET_SRC_BLOCK_SIZE_HEIGHT_TWO_GOBS (0x00000001) +#define NVC0B5_SET_SRC_BLOCK_SIZE_HEIGHT_FOUR_GOBS (0x00000002) +#define NVC0B5_SET_SRC_BLOCK_SIZE_HEIGHT_EIGHT_GOBS (0x00000003) +#define NVC0B5_SET_SRC_BLOCK_SIZE_HEIGHT_SIXTEEN_GOBS (0x00000004) +#define NVC0B5_SET_SRC_BLOCK_SIZE_HEIGHT_THIRTYTWO_GOBS (0x00000005) +#define NVC0B5_SET_SRC_BLOCK_SIZE_DEPTH 11:8 +#define NVC0B5_SET_SRC_BLOCK_SIZE_DEPTH_ONE_GOB (0x00000000) +#define NVC0B5_SET_SRC_BLOCK_SIZE_DEPTH_TWO_GOBS (0x00000001) +#define NVC0B5_SET_SRC_BLOCK_SIZE_DEPTH_FOUR_GOBS (0x00000002) +#define NVC0B5_SET_SRC_BLOCK_SIZE_DEPTH_EIGHT_GOBS (0x00000003) +#define NVC0B5_SET_SRC_BLOCK_SIZE_DEPTH_SIXTEEN_GOBS (0x00000004) +#define NVC0B5_SET_SRC_BLOCK_SIZE_DEPTH_THIRTYTWO_GOBS (0x00000005) +#define NVC0B5_SET_SRC_BLOCK_SIZE_GOB_HEIGHT 15:12 +#define NVC0B5_SET_SRC_BLOCK_SIZE_GOB_HEIGHT_GOB_HEIGHT_FERMI_8 (0x00000001) +#define NVC0B5_SET_SRC_WIDTH (0x0000072C) +#define NVC0B5_SET_SRC_WIDTH_V 31:0 +#define NVC0B5_SET_SRC_HEIGHT (0x00000730) +#define NVC0B5_SET_SRC_HEIGHT_V 31:0 +#define NVC0B5_SET_SRC_DEPTH (0x00000734) +#define NVC0B5_SET_SRC_DEPTH_V 31:0 +#define NVC0B5_SET_SRC_LAYER (0x00000738) +#define NVC0B5_SET_SRC_LAYER_V 31:0 +#define NVC0B5_SET_SRC_ORIGIN (0x0000073C) +#define NVC0B5_SET_SRC_ORIGIN_X 15:0 +#define NVC0B5_SET_SRC_ORIGIN_Y 31:16 +#define NVC0B5_PM_TRIGGER_END (0x00001114) +#define NVC0B5_PM_TRIGGER_END_V 31:0 #ifdef __cplusplus }; /* extern "C" */ diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/kernel-open/nvidia-uvm/clc1b5.h nvidia-open-gpu-kernel-modules-535.161.08/kernel-open/nvidia-uvm/clc1b5.h --- nvidia-open-gpu-kernel-modules-525.147.05/kernel-open/nvidia-uvm/clc1b5.h 2023-10-25 20:33:28.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/kernel-open/nvidia-uvm/clc1b5.h 2024-03-05 22:25:43.000000000 +0000 @@ -1,19 +1,19 @@ /******************************************************************************* - Copyright (c) 2014 NVIDIA Corporation + Copyright (c) 2019, NVIDIA CORPORATION. All rights reserved. - Permission is hereby granted, free of charge, to any person obtaining a copy - of this software and associated documentation files (the "Software"), to - deal in the Software without restriction, including without limitation the - rights to use, copy, modify, merge, publish, distribute, sublicense, and/or - sell copies of the Software, and to permit persons to whom the Software is - furnished to do so, subject to the following conditions: + Permission is hereby granted, free of charge, to any person obtaining a + copy of this software and associated documentation files (the "Software"), + to deal in the Software without restriction, including without limitation + the rights to use, copy, modify, merge, publish, distribute, sublicense, + and/or sell copies of the Software, and to permit persons to whom the + Software is furnished to do so, subject to the following conditions: - The above copyright notice and this permission notice shall be - included in all copies or substantial portions of the Software. + The above copyright notice and this permission notice shall be included in + all copies or substantial portions of the Software. THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER @@ -32,6 +32,10 @@ #define PASCAL_DMA_COPY_B (0x0000C1B5) +#define NVC1B5_NOP (0x00000100) +#define NVC1B5_NOP_PARAMETER 31:0 +#define NVC1B5_PM_TRIGGER (0x00000140) +#define NVC1B5_PM_TRIGGER_V 31:0 #define NVC1B5_SET_SEMAPHORE_A (0x00000240) #define NVC1B5_SET_SEMAPHORE_A_UPPER 16:0 #define NVC1B5_SET_SEMAPHORE_B (0x00000244) @@ -115,6 +119,14 @@ #define NVC1B5_LAUNCH_DMA_SRC_BYPASS_L2 20:20 #define NVC1B5_LAUNCH_DMA_SRC_BYPASS_L2_USE_PTE_SETTING (0x00000000) #define NVC1B5_LAUNCH_DMA_SRC_BYPASS_L2_FORCE_VOLATILE (0x00000001) +#define NVC1B5_LAUNCH_DMA_DST_BYPASS_L2 21:21 +#define NVC1B5_LAUNCH_DMA_DST_BYPASS_L2_USE_PTE_SETTING (0x00000000) +#define NVC1B5_LAUNCH_DMA_DST_BYPASS_L2_FORCE_VOLATILE (0x00000001) +#define NVC1B5_LAUNCH_DMA_VPRMODE 23:22 +#define NVC1B5_LAUNCH_DMA_VPRMODE_VPR_NONE (0x00000000) +#define NVC1B5_LAUNCH_DMA_VPRMODE_VPR_VID2VID (0x00000001) +#define NVC1B5_LAUNCH_DMA_RESERVED_START_OF_COPY 24:24 +#define NVC1B5_LAUNCH_DMA_RESERVED_ERR_CODE 31:28 #define NVC1B5_OFFSET_IN_UPPER (0x00000400) #define NVC1B5_OFFSET_IN_UPPER_UPPER 16:0 #define NVC1B5_OFFSET_IN_LOWER (0x00000404) @@ -183,6 +195,76 @@ #define NVC1B5_SET_REMAP_COMPONENTS_NUM_DST_COMPONENTS_TWO (0x00000001) #define NVC1B5_SET_REMAP_COMPONENTS_NUM_DST_COMPONENTS_THREE (0x00000002) #define NVC1B5_SET_REMAP_COMPONENTS_NUM_DST_COMPONENTS_FOUR (0x00000003) +#define NVC1B5_SET_DST_BLOCK_SIZE (0x0000070C) +#define NVC1B5_SET_DST_BLOCK_SIZE_WIDTH 3:0 +#define NVC1B5_SET_DST_BLOCK_SIZE_WIDTH_ONE_GOB (0x00000000) +#define NVC1B5_SET_DST_BLOCK_SIZE_HEIGHT 7:4 +#define NVC1B5_SET_DST_BLOCK_SIZE_HEIGHT_ONE_GOB (0x00000000) +#define NVC1B5_SET_DST_BLOCK_SIZE_HEIGHT_TWO_GOBS (0x00000001) +#define NVC1B5_SET_DST_BLOCK_SIZE_HEIGHT_FOUR_GOBS (0x00000002) +#define NVC1B5_SET_DST_BLOCK_SIZE_HEIGHT_EIGHT_GOBS (0x00000003) +#define NVC1B5_SET_DST_BLOCK_SIZE_HEIGHT_SIXTEEN_GOBS (0x00000004) +#define NVC1B5_SET_DST_BLOCK_SIZE_HEIGHT_THIRTYTWO_GOBS (0x00000005) +#define NVC1B5_SET_DST_BLOCK_SIZE_DEPTH 11:8 +#define NVC1B5_SET_DST_BLOCK_SIZE_DEPTH_ONE_GOB (0x00000000) +#define NVC1B5_SET_DST_BLOCK_SIZE_DEPTH_TWO_GOBS (0x00000001) +#define NVC1B5_SET_DST_BLOCK_SIZE_DEPTH_FOUR_GOBS (0x00000002) +#define NVC1B5_SET_DST_BLOCK_SIZE_DEPTH_EIGHT_GOBS (0x00000003) +#define NVC1B5_SET_DST_BLOCK_SIZE_DEPTH_SIXTEEN_GOBS (0x00000004) +#define NVC1B5_SET_DST_BLOCK_SIZE_DEPTH_THIRTYTWO_GOBS (0x00000005) +#define NVC1B5_SET_DST_BLOCK_SIZE_GOB_HEIGHT 15:12 +#define NVC1B5_SET_DST_BLOCK_SIZE_GOB_HEIGHT_GOB_HEIGHT_FERMI_8 (0x00000001) +#define NVC1B5_SET_DST_WIDTH (0x00000710) +#define NVC1B5_SET_DST_WIDTH_V 31:0 +#define NVC1B5_SET_DST_HEIGHT (0x00000714) +#define NVC1B5_SET_DST_HEIGHT_V 31:0 +#define NVC1B5_SET_DST_DEPTH (0x00000718) +#define NVC1B5_SET_DST_DEPTH_V 31:0 +#define NVC1B5_SET_DST_LAYER (0x0000071C) +#define NVC1B5_SET_DST_LAYER_V 31:0 +#define NVC1B5_SET_DST_ORIGIN (0x00000720) +#define NVC1B5_SET_DST_ORIGIN_X 15:0 +#define NVC1B5_SET_DST_ORIGIN_Y 31:16 +#define NVC1B5_SET_SRC_BLOCK_SIZE (0x00000728) +#define NVC1B5_SET_SRC_BLOCK_SIZE_WIDTH 3:0 +#define NVC1B5_SET_SRC_BLOCK_SIZE_WIDTH_ONE_GOB (0x00000000) +#define NVC1B5_SET_SRC_BLOCK_SIZE_HEIGHT 7:4 +#define NVC1B5_SET_SRC_BLOCK_SIZE_HEIGHT_ONE_GOB (0x00000000) +#define NVC1B5_SET_SRC_BLOCK_SIZE_HEIGHT_TWO_GOBS (0x00000001) +#define NVC1B5_SET_SRC_BLOCK_SIZE_HEIGHT_FOUR_GOBS (0x00000002) +#define NVC1B5_SET_SRC_BLOCK_SIZE_HEIGHT_EIGHT_GOBS (0x00000003) +#define NVC1B5_SET_SRC_BLOCK_SIZE_HEIGHT_SIXTEEN_GOBS (0x00000004) +#define NVC1B5_SET_SRC_BLOCK_SIZE_HEIGHT_THIRTYTWO_GOBS (0x00000005) +#define NVC1B5_SET_SRC_BLOCK_SIZE_DEPTH 11:8 +#define NVC1B5_SET_SRC_BLOCK_SIZE_DEPTH_ONE_GOB (0x00000000) +#define NVC1B5_SET_SRC_BLOCK_SIZE_DEPTH_TWO_GOBS (0x00000001) +#define NVC1B5_SET_SRC_BLOCK_SIZE_DEPTH_FOUR_GOBS (0x00000002) +#define NVC1B5_SET_SRC_BLOCK_SIZE_DEPTH_EIGHT_GOBS (0x00000003) +#define NVC1B5_SET_SRC_BLOCK_SIZE_DEPTH_SIXTEEN_GOBS (0x00000004) +#define NVC1B5_SET_SRC_BLOCK_SIZE_DEPTH_THIRTYTWO_GOBS (0x00000005) +#define NVC1B5_SET_SRC_BLOCK_SIZE_GOB_HEIGHT 15:12 +#define NVC1B5_SET_SRC_BLOCK_SIZE_GOB_HEIGHT_GOB_HEIGHT_FERMI_8 (0x00000001) +#define NVC1B5_SET_SRC_WIDTH (0x0000072C) +#define NVC1B5_SET_SRC_WIDTH_V 31:0 +#define NVC1B5_SET_SRC_HEIGHT (0x00000730) +#define NVC1B5_SET_SRC_HEIGHT_V 31:0 +#define NVC1B5_SET_SRC_DEPTH (0x00000734) +#define NVC1B5_SET_SRC_DEPTH_V 31:0 +#define NVC1B5_SET_SRC_LAYER (0x00000738) +#define NVC1B5_SET_SRC_LAYER_V 31:0 +#define NVC1B5_SET_SRC_ORIGIN (0x0000073C) +#define NVC1B5_SET_SRC_ORIGIN_X 15:0 +#define NVC1B5_SET_SRC_ORIGIN_Y 31:16 +#define NVC1B5_SRC_ORIGIN_X (0x00000744) +#define NVC1B5_SRC_ORIGIN_X_VALUE 31:0 +#define NVC1B5_SRC_ORIGIN_Y (0x00000748) +#define NVC1B5_SRC_ORIGIN_Y_VALUE 31:0 +#define NVC1B5_DST_ORIGIN_X (0x0000074C) +#define NVC1B5_DST_ORIGIN_X_VALUE 31:0 +#define NVC1B5_DST_ORIGIN_Y (0x00000750) +#define NVC1B5_DST_ORIGIN_Y_VALUE 31:0 +#define NVC1B5_PM_TRIGGER_END (0x00001114) +#define NVC1B5_PM_TRIGGER_END_V 31:0 #ifdef __cplusplus }; /* extern "C" */ diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/kernel-open/nvidia-uvm/clc365.h nvidia-open-gpu-kernel-modules-535.161.08/kernel-open/nvidia-uvm/clc365.h --- nvidia-open-gpu-kernel-modules-525.147.05/kernel-open/nvidia-uvm/clc365.h 2023-10-25 20:33:29.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/kernel-open/nvidia-uvm/clc365.h 2024-03-05 22:25:43.000000000 +0000 @@ -1,5 +1,5 @@ /******************************************************************************* - Copyright (c) 2021 NVIDIA Corporation + Copyright (c) 2022 NVIDIA Corporation Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation files (the "Software"), to diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/kernel-open/nvidia-uvm/clc369.h nvidia-open-gpu-kernel-modules-535.161.08/kernel-open/nvidia-uvm/clc369.h --- nvidia-open-gpu-kernel-modules-525.147.05/kernel-open/nvidia-uvm/clc369.h 2023-10-25 20:33:29.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/kernel-open/nvidia-uvm/clc369.h 2024-03-05 22:25:43.000000000 +0000 @@ -1,5 +1,5 @@ /******************************************************************************* - Copyright (c) 2021 NVIDIA Corporation + Copyright (c) 2022 NVIDIA Corporation Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation files (the "Software"), to diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/kernel-open/nvidia-uvm/clc3b5.h nvidia-open-gpu-kernel-modules-535.161.08/kernel-open/nvidia-uvm/clc3b5.h --- nvidia-open-gpu-kernel-modules-525.147.05/kernel-open/nvidia-uvm/clc3b5.h 2023-10-25 20:33:30.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/kernel-open/nvidia-uvm/clc3b5.h 2024-03-05 22:25:44.000000000 +0000 @@ -1,19 +1,19 @@ /******************************************************************************* - Copyright (c) 2016 NVIDIA Corporation + Copyright (c) 2020, NVIDIA CORPORATION. All rights reserved. - Permission is hereby granted, free of charge, to any person obtaining a copy - of this software and associated documentation files (the "Software"), to - deal in the Software without restriction, including without limitation the - rights to use, copy, modify, merge, publish, distribute, sublicense, and/or - sell copies of the Software, and to permit persons to whom the Software is - furnished to do so, subject to the following conditions: + Permission is hereby granted, free of charge, to any person obtaining a + copy of this software and associated documentation files (the "Software"), + to deal in the Software without restriction, including without limitation + the rights to use, copy, modify, merge, publish, distribute, sublicense, + and/or sell copies of the Software, and to permit persons to whom the + Software is furnished to do so, subject to the following conditions: - The above copyright notice and this permission notice shall be - included in all copies or substantial portions of the Software. + The above copyright notice and this permission notice shall be included in + all copies or substantial portions of the Software. THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER @@ -32,6 +32,10 @@ #define VOLTA_DMA_COPY_A (0x0000C3B5) +#define NVC3B5_NOP (0x00000100) +#define NVC3B5_NOP_PARAMETER 31:0 +#define NVC3B5_PM_TRIGGER (0x00000140) +#define NVC3B5_PM_TRIGGER_V 31:0 #define NVC3B5_SET_SEMAPHORE_A (0x00000240) #define NVC3B5_SET_SEMAPHORE_A_UPPER 16:0 #define NVC3B5_SET_SEMAPHORE_B (0x00000244) @@ -69,6 +73,9 @@ #define NVC3B5_LAUNCH_DMA_FLUSH_ENABLE 2:2 #define NVC3B5_LAUNCH_DMA_FLUSH_ENABLE_FALSE (0x00000000) #define NVC3B5_LAUNCH_DMA_FLUSH_ENABLE_TRUE (0x00000001) +#define NVC3B5_LAUNCH_DMA_FLUSH_TYPE 25:25 +#define NVC3B5_LAUNCH_DMA_FLUSH_TYPE_SYS (0x00000000) +#define NVC3B5_LAUNCH_DMA_FLUSH_TYPE_GL (0x00000001) #define NVC3B5_LAUNCH_DMA_SEMAPHORE_TYPE 4:3 #define NVC3B5_LAUNCH_DMA_SEMAPHORE_TYPE_NONE (0x00000000) #define NVC3B5_LAUNCH_DMA_SEMAPHORE_TYPE_RELEASE_ONE_WORD_SEMAPHORE (0x00000001) @@ -123,8 +130,6 @@ #define NVC3B5_LAUNCH_DMA_VPRMODE 23:22 #define NVC3B5_LAUNCH_DMA_VPRMODE_VPR_NONE (0x00000000) #define NVC3B5_LAUNCH_DMA_VPRMODE_VPR_VID2VID (0x00000001) -#define NVC3B5_LAUNCH_DMA_VPRMODE_VPR_VID2SYS (0x00000002) -#define NVC3B5_LAUNCH_DMA_VPRMODE_VPR_SYS2VID (0x00000003) #define NVC3B5_LAUNCH_DMA_RESERVED_START_OF_COPY 24:24 #define NVC3B5_LAUNCH_DMA_RESERVED_ERR_CODE 31:28 #define NVC3B5_OFFSET_IN_UPPER (0x00000400) @@ -195,6 +200,76 @@ #define NVC3B5_SET_REMAP_COMPONENTS_NUM_DST_COMPONENTS_TWO (0x00000001) #define NVC3B5_SET_REMAP_COMPONENTS_NUM_DST_COMPONENTS_THREE (0x00000002) #define NVC3B5_SET_REMAP_COMPONENTS_NUM_DST_COMPONENTS_FOUR (0x00000003) +#define NVC3B5_SET_DST_BLOCK_SIZE (0x0000070C) +#define NVC3B5_SET_DST_BLOCK_SIZE_WIDTH 3:0 +#define NVC3B5_SET_DST_BLOCK_SIZE_WIDTH_ONE_GOB (0x00000000) +#define NVC3B5_SET_DST_BLOCK_SIZE_HEIGHT 7:4 +#define NVC3B5_SET_DST_BLOCK_SIZE_HEIGHT_ONE_GOB (0x00000000) +#define NVC3B5_SET_DST_BLOCK_SIZE_HEIGHT_TWO_GOBS (0x00000001) +#define NVC3B5_SET_DST_BLOCK_SIZE_HEIGHT_FOUR_GOBS (0x00000002) +#define NVC3B5_SET_DST_BLOCK_SIZE_HEIGHT_EIGHT_GOBS (0x00000003) +#define NVC3B5_SET_DST_BLOCK_SIZE_HEIGHT_SIXTEEN_GOBS (0x00000004) +#define NVC3B5_SET_DST_BLOCK_SIZE_HEIGHT_THIRTYTWO_GOBS (0x00000005) +#define NVC3B5_SET_DST_BLOCK_SIZE_DEPTH 11:8 +#define NVC3B5_SET_DST_BLOCK_SIZE_DEPTH_ONE_GOB (0x00000000) +#define NVC3B5_SET_DST_BLOCK_SIZE_DEPTH_TWO_GOBS (0x00000001) +#define NVC3B5_SET_DST_BLOCK_SIZE_DEPTH_FOUR_GOBS (0x00000002) +#define NVC3B5_SET_DST_BLOCK_SIZE_DEPTH_EIGHT_GOBS (0x00000003) +#define NVC3B5_SET_DST_BLOCK_SIZE_DEPTH_SIXTEEN_GOBS (0x00000004) +#define NVC3B5_SET_DST_BLOCK_SIZE_DEPTH_THIRTYTWO_GOBS (0x00000005) +#define NVC3B5_SET_DST_BLOCK_SIZE_GOB_HEIGHT 15:12 +#define NVC3B5_SET_DST_BLOCK_SIZE_GOB_HEIGHT_GOB_HEIGHT_FERMI_8 (0x00000001) +#define NVC3B5_SET_DST_WIDTH (0x00000710) +#define NVC3B5_SET_DST_WIDTH_V 31:0 +#define NVC3B5_SET_DST_HEIGHT (0x00000714) +#define NVC3B5_SET_DST_HEIGHT_V 31:0 +#define NVC3B5_SET_DST_DEPTH (0x00000718) +#define NVC3B5_SET_DST_DEPTH_V 31:0 +#define NVC3B5_SET_DST_LAYER (0x0000071C) +#define NVC3B5_SET_DST_LAYER_V 31:0 +#define NVC3B5_SET_DST_ORIGIN (0x00000720) +#define NVC3B5_SET_DST_ORIGIN_X 15:0 +#define NVC3B5_SET_DST_ORIGIN_Y 31:16 +#define NVC3B5_SET_SRC_BLOCK_SIZE (0x00000728) +#define NVC3B5_SET_SRC_BLOCK_SIZE_WIDTH 3:0 +#define NVC3B5_SET_SRC_BLOCK_SIZE_WIDTH_ONE_GOB (0x00000000) +#define NVC3B5_SET_SRC_BLOCK_SIZE_HEIGHT 7:4 +#define NVC3B5_SET_SRC_BLOCK_SIZE_HEIGHT_ONE_GOB (0x00000000) +#define NVC3B5_SET_SRC_BLOCK_SIZE_HEIGHT_TWO_GOBS (0x00000001) +#define NVC3B5_SET_SRC_BLOCK_SIZE_HEIGHT_FOUR_GOBS (0x00000002) +#define NVC3B5_SET_SRC_BLOCK_SIZE_HEIGHT_EIGHT_GOBS (0x00000003) +#define NVC3B5_SET_SRC_BLOCK_SIZE_HEIGHT_SIXTEEN_GOBS (0x00000004) +#define NVC3B5_SET_SRC_BLOCK_SIZE_HEIGHT_THIRTYTWO_GOBS (0x00000005) +#define NVC3B5_SET_SRC_BLOCK_SIZE_DEPTH 11:8 +#define NVC3B5_SET_SRC_BLOCK_SIZE_DEPTH_ONE_GOB (0x00000000) +#define NVC3B5_SET_SRC_BLOCK_SIZE_DEPTH_TWO_GOBS (0x00000001) +#define NVC3B5_SET_SRC_BLOCK_SIZE_DEPTH_FOUR_GOBS (0x00000002) +#define NVC3B5_SET_SRC_BLOCK_SIZE_DEPTH_EIGHT_GOBS (0x00000003) +#define NVC3B5_SET_SRC_BLOCK_SIZE_DEPTH_SIXTEEN_GOBS (0x00000004) +#define NVC3B5_SET_SRC_BLOCK_SIZE_DEPTH_THIRTYTWO_GOBS (0x00000005) +#define NVC3B5_SET_SRC_BLOCK_SIZE_GOB_HEIGHT 15:12 +#define NVC3B5_SET_SRC_BLOCK_SIZE_GOB_HEIGHT_GOB_HEIGHT_FERMI_8 (0x00000001) +#define NVC3B5_SET_SRC_WIDTH (0x0000072C) +#define NVC3B5_SET_SRC_WIDTH_V 31:0 +#define NVC3B5_SET_SRC_HEIGHT (0x00000730) +#define NVC3B5_SET_SRC_HEIGHT_V 31:0 +#define NVC3B5_SET_SRC_DEPTH (0x00000734) +#define NVC3B5_SET_SRC_DEPTH_V 31:0 +#define NVC3B5_SET_SRC_LAYER (0x00000738) +#define NVC3B5_SET_SRC_LAYER_V 31:0 +#define NVC3B5_SET_SRC_ORIGIN (0x0000073C) +#define NVC3B5_SET_SRC_ORIGIN_X 15:0 +#define NVC3B5_SET_SRC_ORIGIN_Y 31:16 +#define NVC3B5_SRC_ORIGIN_X (0x00000744) +#define NVC3B5_SRC_ORIGIN_X_VALUE 31:0 +#define NVC3B5_SRC_ORIGIN_Y (0x00000748) +#define NVC3B5_SRC_ORIGIN_Y_VALUE 31:0 +#define NVC3B5_DST_ORIGIN_X (0x0000074C) +#define NVC3B5_DST_ORIGIN_X_VALUE 31:0 +#define NVC3B5_DST_ORIGIN_Y (0x00000750) +#define NVC3B5_DST_ORIGIN_Y_VALUE 31:0 +#define NVC3B5_PM_TRIGGER_END (0x00001114) +#define NVC3B5_PM_TRIGGER_END_V 31:0 #ifdef __cplusplus }; /* extern "C" */ diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/kernel-open/nvidia-uvm/clcba2.h nvidia-open-gpu-kernel-modules-535.161.08/kernel-open/nvidia-uvm/clcba2.h --- nvidia-open-gpu-kernel-modules-525.147.05/kernel-open/nvidia-uvm/clcba2.h 1970-01-01 00:00:00.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/kernel-open/nvidia-uvm/clcba2.h 2024-03-05 22:25:40.000000000 +0000 @@ -0,0 +1,97 @@ +/******************************************************************************* + Copyright (c) 2021-2022 NVIDIA Corporation + + Permission is hereby granted, free of charge, to any person obtaining a copy + of this software and associated documentation files (the "Software"), to + deal in the Software without restriction, including without limitation the + rights to use, copy, modify, merge, publish, distribute, sublicense, and/or + sell copies of the Software, and to permit persons to whom the Software is + furnished to do so, subject to the following conditions: + + The above copyright notice and this permission notice shall be + included in all copies or substantial portions of the Software. + + THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + DEALINGS IN THE SOFTWARE. + +*******************************************************************************/ + +#include "nvtypes.h" + +#ifndef _clcba2_h_ +#define _clcba2_h_ + +#ifdef __cplusplus +extern "C" { +#endif + +#define HOPPER_SEC2_WORK_LAUNCH_A (0x0000CBA2) + +#define NVCBA2_DECRYPT_COPY_SRC_ADDR_HI (0x00000400) +#define NVCBA2_DECRYPT_COPY_SRC_ADDR_HI_DATA 24:0 +#define NVCBA2_DECRYPT_COPY_SRC_ADDR_LO (0x00000404) +#define NVCBA2_DECRYPT_COPY_SRC_ADDR_LO_DATA 31:4 +#define NVCBA2_DECRYPT_COPY_DST_ADDR_HI (0x00000408) +#define NVCBA2_DECRYPT_COPY_DST_ADDR_HI_DATA 24:0 +#define NVCBA2_DECRYPT_COPY_DST_ADDR_LO (0x0000040c) +#define NVCBA2_DECRYPT_COPY_DST_ADDR_LO_DATA 31:4 +#define NVCBA2_DECRYPT_COPY_SIZE (0x00000410) +#define NVCBA2_DECRYPT_COPY_SIZE_DATA 31:2 +#define NVCBA2_DECRYPT_COPY_AUTH_TAG_ADDR_HI (0x00000414) +#define NVCBA2_DECRYPT_COPY_AUTH_TAG_ADDR_HI_DATA 24:0 +#define NVCBA2_DECRYPT_COPY_AUTH_TAG_ADDR_LO (0x00000418) +#define NVCBA2_DECRYPT_COPY_AUTH_TAG_ADDR_LO_DATA 31:4 +#define NVCBA2_METHOD_STREAM_AUTH_TAG_ADDR_HI (0x0000041C) +#define NVCBA2_METHOD_STREAM_AUTH_TAG_ADDR_HI_DATA 24:0 +#define NVCBA2_METHOD_STREAM_AUTH_TAG_ADDR_LO (0x00000420) +#define NVCBA2_METHOD_STREAM_AUTH_TAG_ADDR_LO_DATA 31:4 +#define NVCBA2_SEMAPHORE_A (0x00000440) +#define NVCBA2_SEMAPHORE_A_UPPER 24:0 +#define NVCBA2_SEMAPHORE_B (0x00000444) +#define NVCBA2_SEMAPHORE_B_LOWER 31:2 +#define NVCBA2_SET_SEMAPHORE_PAYLOAD_LOWER (0x00000448) +#define NVCBA2_SET_SEMAPHORE_PAYLOAD_LOWER_DATA 31:0 +#define NVCBA2_SET_SEMAPHORE_PAYLOAD_UPPER (0x0000044C) +#define NVCBA2_SET_SEMAPHORE_PAYLOAD_UPPER_DATA 31:0 +#define NVCBA2_SEMAPHORE_D (0x00000450) +#define NVCBA2_SEMAPHORE_D_NOTIFY_INTR 0:0 +#define NVCBA2_SEMAPHORE_D_NOTIFY_INTR_DISABLE (0x00000000) +#define NVCBA2_SEMAPHORE_D_NOTIFY_INTR_ENABLE (0x00000001) +#define NVCBA2_SEMAPHORE_D_PAYLOAD_SIZE 1:1 +#define NVCBA2_SEMAPHORE_D_PAYLOAD_SIZE_32_BIT (0x00000000) +#define NVCBA2_SEMAPHORE_D_PAYLOAD_SIZE_64_BIT (0x00000001) +#define NVCBA2_SEMAPHORE_D_TIMESTAMP 2:2 +#define NVCBA2_SEMAPHORE_D_TIMESTAMP_DISABLE (0x00000000) +#define NVCBA2_SEMAPHORE_D_TIMESTAMP_ENABLE (0x00000001) +#define NVCBA2_SEMAPHORE_D_FLUSH_DISABLE 3:3 +#define NVCBA2_SEMAPHORE_D_FLUSH_DISABLE_FALSE (0x00000000) +#define NVCBA2_SEMAPHORE_D_FLUSH_DISABLE_TRUE (0x00000001) +#define NVCBA2_EXECUTE (0x00000470) +#define NVCBA2_EXECUTE_NOTIFY 0:0 +#define NVCBA2_EXECUTE_NOTIFY_DISABLE (0x00000000) +#define NVCBA2_EXECUTE_NOTIFY_ENABLE (0x00000001) +#define NVCBA2_EXECUTE_NOTIFY_ON 1:1 +#define NVCBA2_EXECUTE_NOTIFY_ON_END (0x00000000) +#define NVCBA2_EXECUTE_NOTIFY_ON_BEGIN (0x00000001) +#define NVCBA2_EXECUTE_FLUSH_DISABLE 2:2 +#define NVCBA2_EXECUTE_FLUSH_DISABLE_FALSE (0x00000000) +#define NVCBA2_EXECUTE_FLUSH_DISABLE_TRUE (0x00000001) +#define NVCBA2_EXECUTE_NOTIFY_INTR 3:3 +#define NVCBA2_EXECUTE_NOTIFY_INTR_DISABLE (0x00000000) +#define NVCBA2_EXECUTE_NOTIFY_INTR_ENABLE (0x00000001) +#define NVCBA2_EXECUTE_PAYLOAD_SIZE 4:4 +#define NVCBA2_EXECUTE_PAYLOAD_SIZE_32_BIT (0x00000000) +#define NVCBA2_EXECUTE_PAYLOAD_SIZE_64_BIT (0x00000001) +#define NVCBA2_EXECUTE_TIMESTAMP 5:5 +#define NVCBA2_EXECUTE_TIMESTAMP_DISABLE (0x00000000) +#define NVCBA2_EXECUTE_TIMESTAMP_ENABLE (0x00000001) + +#ifdef __cplusplus +}; /* extern "C" */ +#endif +#endif // _clcba2_h diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/kernel-open/nvidia-uvm/ctrl2080mc.h nvidia-open-gpu-kernel-modules-535.161.08/kernel-open/nvidia-uvm/ctrl2080mc.h --- nvidia-open-gpu-kernel-modules-525.147.05/kernel-open/nvidia-uvm/ctrl2080mc.h 2023-10-25 20:33:30.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/kernel-open/nvidia-uvm/ctrl2080mc.h 2024-03-05 22:25:44.000000000 +0000 @@ -1,5 +1,5 @@ /******************************************************************************* - Copyright (c) 2013-2021 NVIDIA Corporation + Copyright (c) 2013-2022 NVIDIA Corporation Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation files (the "Software"), to diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/kernel-open/nvidia-uvm/nv-kthread-q.c nvidia-open-gpu-kernel-modules-535.161.08/kernel-open/nvidia-uvm/nv-kthread-q.c --- nvidia-open-gpu-kernel-modules-525.147.05/kernel-open/nvidia-uvm/nv-kthread-q.c 2023-10-25 20:33:27.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/kernel-open/nvidia-uvm/nv-kthread-q.c 2024-03-05 22:25:42.000000000 +0000 @@ -301,7 +301,7 @@ static void _raw_q_flush(nv_kthread_q_t *q) { nv_kthread_q_item_t q_item; - DECLARE_COMPLETION(completion); + DECLARE_COMPLETION_ONSTACK(completion); nv_kthread_q_item_init(&q_item, _q_flush_function, &completion); diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/kernel-open/nvidia-uvm/nvidia-uvm-sources.Kbuild nvidia-open-gpu-kernel-modules-535.161.08/kernel-open/nvidia-uvm/nvidia-uvm-sources.Kbuild --- nvidia-open-gpu-kernel-modules-525.147.05/kernel-open/nvidia-uvm/nvidia-uvm-sources.Kbuild 2023-10-25 20:33:45.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/kernel-open/nvidia-uvm/nvidia-uvm-sources.Kbuild 2024-03-05 22:26:08.000000000 +0000 @@ -1,12 +1,11 @@ NVIDIA_UVM_SOURCES ?= NVIDIA_UVM_SOURCES_CXX ?= -NVIDIA_UVM_SOURCES += nvidia-uvm/uvm_hopper.c -NVIDIA_UVM_SOURCES += nvidia-uvm/uvm_hopper_fault_buffer.c -NVIDIA_UVM_SOURCES += nvidia-uvm/uvm_hopper_ce.c -NVIDIA_UVM_SOURCES += nvidia-uvm/uvm_hopper_host.c -NVIDIA_UVM_SOURCES += nvidia-uvm/uvm_hopper_mmu.c -NVIDIA_UVM_SOURCES += nvidia-uvm/uvm_ada.c +NVIDIA_UVM_SOURCES += nvidia-uvm/uvm_ats_sva.c +NVIDIA_UVM_SOURCES += nvidia-uvm/uvm_conf_computing.c +NVIDIA_UVM_SOURCES += nvidia-uvm/uvm_sec2_test.c +NVIDIA_UVM_SOURCES += nvidia-uvm/uvm_maxwell_sec2.c +NVIDIA_UVM_SOURCES += nvidia-uvm/uvm_hopper_sec2.c NVIDIA_UVM_SOURCES += nvidia-uvm/uvm_common.c NVIDIA_UVM_SOURCES += nvidia-uvm/uvm_linux.c NVIDIA_UVM_SOURCES += nvidia-uvm/uvm_debug_optimized.c @@ -58,6 +57,7 @@ NVIDIA_UVM_SOURCES += nvidia-uvm/uvm_pascal_host.c NVIDIA_UVM_SOURCES += nvidia-uvm/uvm_pascal_mmu.c NVIDIA_UVM_SOURCES += nvidia-uvm/uvm_pascal_fault_buffer.c +NVIDIA_UVM_SOURCES += nvidia-uvm/uvm_volta_ce.c NVIDIA_UVM_SOURCES += nvidia-uvm/uvm_volta_host.c NVIDIA_UVM_SOURCES += nvidia-uvm/uvm_volta_mmu.c NVIDIA_UVM_SOURCES += nvidia-uvm/uvm_volta.c @@ -72,6 +72,12 @@ NVIDIA_UVM_SOURCES += nvidia-uvm/uvm_ampere_ce.c NVIDIA_UVM_SOURCES += nvidia-uvm/uvm_ampere_host.c NVIDIA_UVM_SOURCES += nvidia-uvm/uvm_ampere_mmu.c +NVIDIA_UVM_SOURCES += nvidia-uvm/uvm_hopper.c +NVIDIA_UVM_SOURCES += nvidia-uvm/uvm_hopper_fault_buffer.c +NVIDIA_UVM_SOURCES += nvidia-uvm/uvm_hopper_ce.c +NVIDIA_UVM_SOURCES += nvidia-uvm/uvm_hopper_host.c +NVIDIA_UVM_SOURCES += nvidia-uvm/uvm_hopper_mmu.c +NVIDIA_UVM_SOURCES += nvidia-uvm/uvm_ada.c NVIDIA_UVM_SOURCES += nvidia-uvm/uvm_policy.c NVIDIA_UVM_SOURCES += nvidia-uvm/uvm_perf_utils.c NVIDIA_UVM_SOURCES += nvidia-uvm/uvm_kvmalloc.c @@ -94,7 +100,6 @@ NVIDIA_UVM_SOURCES += nvidia-uvm/uvm_range_tree_test.c NVIDIA_UVM_SOURCES += nvidia-uvm/uvm_range_allocator_test.c NVIDIA_UVM_SOURCES += nvidia-uvm/uvm_gpu_semaphore_test.c -NVIDIA_UVM_SOURCES += nvidia-uvm/uvm_hmm_sanity_test.c NVIDIA_UVM_SOURCES += nvidia-uvm/uvm_mem_test.c NVIDIA_UVM_SOURCES += nvidia-uvm/uvm_rm_mem_test.c NVIDIA_UVM_SOURCES += nvidia-uvm/uvm_page_tree_test.c diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/kernel-open/nvidia-uvm/nvidia-uvm.Kbuild nvidia-open-gpu-kernel-modules-535.161.08/kernel-open/nvidia-uvm/nvidia-uvm.Kbuild --- nvidia-open-gpu-kernel-modules-525.147.05/kernel-open/nvidia-uvm/nvidia-uvm.Kbuild 2023-10-25 20:33:18.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/kernel-open/nvidia-uvm/nvidia-uvm.Kbuild 2024-03-05 22:25:31.000000000 +0000 @@ -36,7 +36,7 @@ # ifeq ($(UVM_BUILD_TYPE),debug) - NVIDIA_UVM_CFLAGS += -DDEBUG $(call cc-option,-Og,-O0) -g + NVIDIA_UVM_CFLAGS += -DDEBUG -O1 -g else ifeq ($(UVM_BUILD_TYPE),develop) # -DDEBUG is required, in order to allow pr_devel() print statements to @@ -81,7 +81,11 @@ NV_CONFTEST_FUNCTION_COMPILE_TESTS += set_pages_uc NV_CONFTEST_FUNCTION_COMPILE_TESTS += ktime_get_raw_ts64 NV_CONFTEST_FUNCTION_COMPILE_TESTS += ioasid_get +NV_CONFTEST_FUNCTION_COMPILE_TESTS += mm_pasid_drop NV_CONFTEST_FUNCTION_COMPILE_TESTS += mmget_not_zero +NV_CONFTEST_FUNCTION_COMPILE_TESTS += mmgrab +NV_CONFTEST_FUNCTION_COMPILE_TESTS += iommu_sva_bind_device_has_drvdata_arg +NV_CONFTEST_FUNCTION_COMPILE_TESTS += vm_fault_to_errno NV_CONFTEST_TYPE_COMPILE_TESTS += backing_dev_info NV_CONFTEST_TYPE_COMPILE_TESTS += mm_context_t @@ -95,12 +99,19 @@ NV_CONFTEST_TYPE_COMPILE_TESTS += sysfs_slab_unlink NV_CONFTEST_TYPE_COMPILE_TESTS += vm_fault_t NV_CONFTEST_TYPE_COMPILE_TESTS += mmu_notifier_ops_invalidate_range +NV_CONFTEST_TYPE_COMPILE_TESTS += mmu_notifier_ops_arch_invalidate_secondary_tlbs NV_CONFTEST_TYPE_COMPILE_TESTS += proc_ops NV_CONFTEST_TYPE_COMPILE_TESTS += timespec64 NV_CONFTEST_TYPE_COMPILE_TESTS += mm_has_mmap_lock NV_CONFTEST_TYPE_COMPILE_TESTS += migrate_vma_added_flags -NV_CONFTEST_TYPE_COMPILE_TESTS += make_device_exclusive_range +NV_CONFTEST_TYPE_COMPILE_TESTS += migrate_device_range NV_CONFTEST_TYPE_COMPILE_TESTS += vm_area_struct_has_const_vm_flags +NV_CONFTEST_TYPE_COMPILE_TESTS += handle_mm_fault_has_mm_arg +NV_CONFTEST_TYPE_COMPILE_TESTS += handle_mm_fault_has_pt_regs_arg +NV_CONFTEST_TYPE_COMPILE_TESTS += mempolicy_has_unified_nodes +NV_CONFTEST_TYPE_COMPILE_TESTS += mempolicy_has_home_node +NV_CONFTEST_TYPE_COMPILE_TESTS += mpol_preferred_many_present +NV_CONFTEST_TYPE_COMPILE_TESTS += mmu_interval_notifier NV_CONFTEST_SYMBOL_COMPILE_TESTS += is_export_symbol_present_int_active_memcg NV_CONFTEST_SYMBOL_COMPILE_TESTS += is_export_symbol_present_migrate_vma_setup diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/kernel-open/nvidia-uvm/uvm.c nvidia-open-gpu-kernel-modules-535.161.08/kernel-open/nvidia-uvm/uvm.c --- nvidia-open-gpu-kernel-modules-525.147.05/kernel-open/nvidia-uvm/uvm.c 2023-10-25 20:33:32.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/kernel-open/nvidia-uvm/uvm.c 2024-03-05 22:25:48.000000000 +0000 @@ -28,6 +28,7 @@ #include "uvm_lock.h" #include "uvm_test.h" #include "uvm_va_space.h" +#include "uvm_va_space_mm.h" #include "uvm_va_range.h" #include "uvm_va_block.h" #include "uvm_tools.h" @@ -35,26 +36,200 @@ #include "uvm_linux_ioctl.h" #include "uvm_hmm.h" #include "uvm_mem.h" +#include "uvm_kvmalloc.h" #define NVIDIA_UVM_DEVICE_NAME "nvidia-uvm" static dev_t g_uvm_base_dev; static struct cdev g_uvm_cdev; +static const struct file_operations uvm_fops; +bool uvm_file_is_nvidia_uvm(struct file *filp) +{ + return (filp != NULL) && (filp->f_op == &uvm_fops); +} + +uvm_fd_type_t uvm_fd_type(struct file *filp, void **ptr_val) +{ + unsigned long uptr; + uvm_fd_type_t type; + void *ptr; + + UVM_ASSERT(uvm_file_is_nvidia_uvm(filp)); + + uptr = atomic_long_read_acquire((atomic_long_t *) (&filp->private_data)); + type = (uvm_fd_type_t)(uptr & UVM_FD_TYPE_MASK); + ptr = (void *)(uptr & ~UVM_FD_TYPE_MASK); + BUILD_BUG_ON(UVM_FD_COUNT > UVM_FD_TYPE_MASK + 1); + + switch (type) { + case UVM_FD_UNINITIALIZED: + case UVM_FD_INITIALIZING: + UVM_ASSERT(!ptr); + break; + + case UVM_FD_VA_SPACE: + UVM_ASSERT(ptr); + BUILD_BUG_ON(__alignof__(uvm_va_space_t) < (1UL << UVM_FD_TYPE_BITS)); + break; + + case UVM_FD_MM: + UVM_ASSERT(ptr); + BUILD_BUG_ON(__alignof__(struct file) < (1UL << UVM_FD_TYPE_BITS)); + break; + + default: + UVM_ASSERT(0); + } + + if (ptr_val) + *ptr_val = ptr; + + return type; +} + +void *uvm_fd_get_type(struct file *filp, uvm_fd_type_t type) +{ + void *ptr; + + UVM_ASSERT(uvm_file_is_nvidia_uvm(filp)); + + if (uvm_fd_type(filp, &ptr) == type) + return ptr; + else + return NULL; +} + +static NV_STATUS uvm_api_mm_initialize(UVM_MM_INITIALIZE_PARAMS *params, struct file *filp) +{ + uvm_va_space_t *va_space; + uvm_va_space_mm_t *va_space_mm; + struct file *uvm_file; + uvm_fd_type_t old_fd_type; + struct mm_struct *mm; + NV_STATUS status; + + uvm_file = fget(params->uvmFd); + if (!uvm_file_is_nvidia_uvm(uvm_file)) { + status = NV_ERR_INVALID_ARGUMENT; + goto err; + } + + if (uvm_fd_type(uvm_file, (void **)&va_space) != UVM_FD_VA_SPACE) { + status = NV_ERR_INVALID_ARGUMENT; + goto err; + } + + // Tell userspace the MM FD is not required and it may be released + // with no loss of functionality. + if (!uvm_va_space_mm_enabled(va_space)) { + status = NV_WARN_NOTHING_TO_DO; + goto err; + } + + old_fd_type = nv_atomic_long_cmpxchg((atomic_long_t *)&filp->private_data, + UVM_FD_UNINITIALIZED, + UVM_FD_INITIALIZING); + old_fd_type &= UVM_FD_TYPE_MASK; + if (old_fd_type != UVM_FD_UNINITIALIZED) { + status = NV_ERR_IN_USE; + goto err; + } + + va_space_mm = &va_space->va_space_mm; + uvm_spin_lock(&va_space_mm->lock); + switch (va_space->va_space_mm.state) { + // We only allow the va_space_mm to be initialised once. If + // userspace passed the UVM FD to another process it is up to + // userspace to ensure it also passes the UVM MM FD that + // initialised the va_space_mm or arranges some other way to keep + // a reference on the FD. + case UVM_VA_SPACE_MM_STATE_ALIVE: + status = NV_ERR_INVALID_STATE; + goto err_release_unlock; + break; + + // Once userspace has released the va_space_mm the GPU is + // effectively dead and no new work can be started. We don't + // support re-initializing once userspace has closed the FD. + case UVM_VA_SPACE_MM_STATE_RELEASED: + status = NV_ERR_PAGE_TABLE_NOT_AVAIL; + goto err_release_unlock; + break; + + // Keep the warnings at bay + case UVM_VA_SPACE_MM_STATE_UNINITIALIZED: + mm = va_space->va_space_mm.mm; + if (!mm || !mmget_not_zero(mm)) { + status = NV_ERR_PAGE_TABLE_NOT_AVAIL; + goto err_release_unlock; + } + + va_space_mm->state = UVM_VA_SPACE_MM_STATE_ALIVE; + break; + + default: + UVM_ASSERT(0); + break; + } + uvm_spin_unlock(&va_space_mm->lock); + atomic_long_set_release((atomic_long_t *)&filp->private_data, (long)uvm_file | UVM_FD_MM); + + return NV_OK; + +err_release_unlock: + uvm_spin_unlock(&va_space_mm->lock); + atomic_long_set_release((atomic_long_t *)&filp->private_data, UVM_FD_UNINITIALIZED); + +err: + if (uvm_file) + fput(uvm_file); + + return status; +} + +// Called when opening /dev/nvidia-uvm. This code doesn't take any UVM locks, so +// there's no need to acquire g_uvm_global.pm.lock, but if that changes the PM +// lock will need to be taken. static int uvm_open(struct inode *inode, struct file *filp) { + struct address_space *mapping; NV_STATUS status = uvm_global_get_status(); - if (status == NV_OK) { - if (!uvm_down_read_trylock(&g_uvm_global.pm.lock)) - return -EAGAIN; + if (status != NV_OK) + return -nv_status_to_errno(status); - status = uvm_va_space_create(inode, filp); + mapping = uvm_kvmalloc(sizeof(*mapping)); + if (!mapping) + return -ENOMEM; + + // By default all struct files on the same inode share the same + // address_space structure (the inode's) across all processes. This means + // unmap_mapping_range would unmap virtual mappings across all processes on + // that inode. + // + // Since the UVM driver uses the mapping offset as the VA of the file's + // process, we need to isolate the mappings to each process. + address_space_init_once(mapping); + mapping->host = inode; + + // Some paths in the kernel, for example force_page_cache_readahead which + // can be invoked from user-space via madvise MADV_WILLNEED and fadvise + // POSIX_FADV_WILLNEED, check the function pointers within + // file->f_mapping->a_ops for validity. However, those paths assume that a_ops + // itself is always valid. Handle that by using the inode's a_ops pointer, + // which is what f_mapping->a_ops would point to anyway if we weren't re- + // assigning f_mapping. + mapping->a_ops = inode->i_mapping->a_ops; - uvm_up_read(&g_uvm_global.pm.lock); - } +#if defined(NV_ADDRESS_SPACE_HAS_BACKING_DEV_INFO) + mapping->backing_dev_info = inode->i_mapping->backing_dev_info; +#endif + + filp->private_data = NULL; + filp->f_mapping = mapping; - return -nv_status_to_errno(status); + return NV_OK; } static int uvm_open_entry(struct inode *inode, struct file *filp) @@ -78,11 +253,44 @@ uvm_up_read(&g_uvm_global.pm.lock); } +static void uvm_mm_release(struct file *filp, struct file *uvm_file) +{ + uvm_va_space_t *va_space = uvm_va_space_get(uvm_file); + uvm_va_space_mm_t *va_space_mm = &va_space->va_space_mm; + struct mm_struct *mm = va_space_mm->mm; + + if (uvm_va_space_mm_enabled(va_space)) { + uvm_va_space_mm_unregister(va_space); + + if (uvm_va_space_mm_enabled(va_space)) + uvm_mmput(mm); + + va_space_mm->mm = NULL; + fput(uvm_file); + } +} + static int uvm_release(struct inode *inode, struct file *filp) { - uvm_va_space_t *va_space = uvm_va_space_get(filp); + void *ptr; + uvm_va_space_t *va_space; + uvm_fd_type_t fd_type; int ret; + fd_type = uvm_fd_type(filp, &ptr); + UVM_ASSERT(fd_type != UVM_FD_INITIALIZING); + if (fd_type == UVM_FD_UNINITIALIZED) { + uvm_kvfree(filp->f_mapping); + return 0; + } + else if (fd_type == UVM_FD_MM) { + uvm_kvfree(filp->f_mapping); + uvm_mm_release(filp, (struct file *)ptr); + return 0; + } + + UVM_ASSERT(fd_type == UVM_FD_VA_SPACE); + va_space = (uvm_va_space_t *)ptr; filp->private_data = NULL; filp->f_mapping = NULL; @@ -100,7 +308,7 @@ // been destroyed, and va_space->mapping won't be used again. Still, // the va_space survives the inode if its destruction is deferred, in // which case the references are rendered stale. - address_space_init_once(&va_space->mapping); + address_space_init_once(va_space->mapping); nv_kthread_q_item_init(&va_space->deferred_release_q_item, uvm_release_deferred, va_space); ret = nv_kthread_q_schedule_q_item(&g_uvm_global.deferred_release_q, &va_space->deferred_release_q_item); @@ -363,14 +571,11 @@ static void uvm_vm_close_managed(struct vm_area_struct *vma) { uvm_va_space_t *va_space = uvm_va_space_get(vma->vm_file); - uvm_gpu_t *gpu; bool make_zombie = false; if (current->mm != NULL) uvm_record_lock_mmap_lock_write(current->mm); - UVM_ASSERT(uvm_va_space_initialized(va_space) == NV_OK); - // current->mm will be NULL on process teardown, in which case we have // special handling. if (current->mm == NULL) { @@ -400,14 +605,6 @@ uvm_destroy_vma_managed(vma, make_zombie); - // Notify GPU address spaces that the fault buffer needs to be flushed to avoid finding stale entries - // that can be attributed to new VA ranges reallocated at the same address - for_each_va_space_gpu_in_mask(gpu, va_space, &va_space->registered_gpu_va_spaces) { - uvm_gpu_va_space_t *gpu_va_space = uvm_gpu_va_space_get(va_space, gpu); - UVM_ASSERT(gpu_va_space); - - gpu_va_space->needs_fault_buffer_flush = true; - } uvm_va_space_up_write(va_space); if (current->mm != NULL) @@ -556,7 +753,7 @@ static int uvm_mmap(struct file *filp, struct vm_area_struct *vma) { - uvm_va_space_t *va_space = uvm_va_space_get(filp); + uvm_va_space_t *va_space; uvm_va_range_t *va_range; NV_STATUS status = uvm_global_get_status(); int ret = 0; @@ -565,8 +762,8 @@ if (status != NV_OK) return -nv_status_to_errno(status); - status = uvm_va_space_initialized(va_space); - if (status != NV_OK) + va_space = uvm_fd_va_space(filp); + if (!va_space) return -EBADFD; // When the VA space is associated with an mm, all vmas under the VA space @@ -618,7 +815,11 @@ // Using VM_DONTCOPY would be nice, but madvise(MADV_DOFORK) can reset that // so we have to handle vm_open on fork anyway. We could disable MADV_DOFORK // with VM_IO, but that causes other mapping issues. - nv_vm_flags_set(vma, VM_MIXEDMAP | VM_DONTEXPAND); + // Make the default behavior be VM_DONTCOPY to avoid the performance impact + // of removing CPU mappings in the parent on fork()+exec(). Users can call + // madvise(MDV_DOFORK) if the child process requires access to the + // allocation. + nv_vm_flags_set(vma, VM_MIXEDMAP | VM_DONTEXPAND | VM_DONTCOPY); vma->vm_ops = &uvm_vm_ops_managed; @@ -678,6 +879,13 @@ return ret; } +bool uvm_vma_is_managed(struct vm_area_struct *vma) +{ + return vma->vm_ops == &uvm_vm_ops_disabled || + vma->vm_ops == &uvm_vm_ops_managed || + vma->vm_ops == &uvm_vm_ops_semaphore_pool; +} + static int uvm_mmap_entry(struct file *filp, struct vm_area_struct *vma) { UVM_ENTRY_RET(uvm_mmap(filp, vma)); @@ -685,7 +893,56 @@ static NV_STATUS uvm_api_initialize(UVM_INITIALIZE_PARAMS *params, struct file *filp) { - return uvm_va_space_initialize(uvm_va_space_get(filp), params->flags); + uvm_va_space_t *va_space; + NV_STATUS status; + uvm_fd_type_t old_fd_type; + + // Normally we expect private_data == UVM_FD_UNINITIALIZED. However multiple + // threads may call this ioctl concurrently so we have to be careful to + // avoid initializing multiple va_spaces and/or leaking memory. To do this + // we do an atomic compare and swap. Only one thread will observe + // UVM_FD_UNINITIALIZED and that thread will allocate and setup the + // va_space. + // + // Other threads will either see UVM_FD_INITIALIZING or UVM_FD_VA_SPACE. In + // the case of UVM_FD_VA_SPACE we return success if and only if the + // initialization flags match. If another thread is still initializing the + // va_space we return NV_ERR_BUSY_RETRY. + // + // If va_space initialization fails we return the failure code and reset the + // FD state back to UVM_FD_UNINITIALIZED to allow another initialization + // attempt to be made. This is safe because other threads will have only had + // a chance to observe UVM_FD_INITIALIZING and not UVM_FD_VA_SPACE in this + // case. + old_fd_type = nv_atomic_long_cmpxchg((atomic_long_t *)&filp->private_data, + UVM_FD_UNINITIALIZED, UVM_FD_INITIALIZING); + old_fd_type &= UVM_FD_TYPE_MASK; + if (old_fd_type == UVM_FD_UNINITIALIZED) { + status = uvm_va_space_create(filp->f_mapping, &va_space, params->flags); + if (status != NV_OK) { + atomic_long_set_release((atomic_long_t *)&filp->private_data, UVM_FD_UNINITIALIZED); + return status; + } + + atomic_long_set_release((atomic_long_t *)&filp->private_data, (long)va_space | UVM_FD_VA_SPACE); + } + else if (old_fd_type == UVM_FD_VA_SPACE) { + va_space = uvm_va_space_get(filp); + + if (params->flags != va_space->initialization_flags) + status = NV_ERR_INVALID_ARGUMENT; + else + status = NV_OK; + } + else if (old_fd_type == UVM_FD_MM) { + status = NV_ERR_INVALID_ARGUMENT; + } + else { + UVM_ASSERT(old_fd_type == UVM_FD_INITIALIZING); + status = NV_ERR_BUSY_RETRY; + } + + return status; } static NV_STATUS uvm_api_pageable_mem_access(UVM_PAGEABLE_MEM_ACCESS_PARAMS *params, struct file *filp) @@ -703,6 +960,7 @@ return 0; UVM_ROUTE_CMD_STACK_NO_INIT_CHECK(UVM_INITIALIZE, uvm_api_initialize); + UVM_ROUTE_CMD_STACK_NO_INIT_CHECK(UVM_MM_INITIALIZE, uvm_api_mm_initialize); UVM_ROUTE_CMD_STACK_INIT_CHECK(UVM_PAGEABLE_MEM_ACCESS, uvm_api_pageable_mem_access); UVM_ROUTE_CMD_STACK_INIT_CHECK(UVM_PAGEABLE_MEM_ACCESS_ON_GPU, uvm_api_pageable_mem_access_on_gpu); @@ -782,11 +1040,6 @@ .owner = THIS_MODULE, }; -bool uvm_file_is_nvidia_uvm(struct file *filp) -{ - return (filp != NULL) && (filp->f_op == &uvm_fops); -} - NV_STATUS uvm_test_register_unload_state_buffer(UVM_TEST_REGISTER_UNLOAD_STATE_BUFFER_PARAMS *params, struct file *filp) { long ret; diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/kernel-open/nvidia-uvm/uvm.h nvidia-open-gpu-kernel-modules-535.161.08/kernel-open/nvidia-uvm/uvm.h --- nvidia-open-gpu-kernel-modules-525.147.05/kernel-open/nvidia-uvm/uvm.h 2023-10-25 20:33:27.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/kernel-open/nvidia-uvm/uvm.h 2024-03-05 22:25:42.000000000 +0000 @@ -54,7 +54,7 @@ #ifndef _UVM_H_ #define _UVM_H_ -#define UVM_API_LATEST_REVISION 7 +#define UVM_API_LATEST_REVISION 8 #if !defined(UVM_API_REVISION) #error "please define UVM_API_REVISION macro to a desired version number or UVM_API_LATEST_REVISION macro" @@ -211,12 +211,12 @@ // UvmReopen // // Reinitializes the UVM driver after checking for minimal user-mode state. -// Before calling this function, all GPUs must be unregistered with +// Before calling this function, all GPUs must be unregistered with // UvmUnregisterGpu() and all allocated VA ranges must be freed with UvmFree(). // Note that it is not required to release VA ranges that were reserved with // UvmReserveVa(). // -// UvmReopen() closes the open file returned by UvmGetFileDescriptor() and +// UvmReopen() closes the open file returned by UvmGetFileDescriptor() and // replaces it with a new open file with the same name. // // Arguments: @@ -410,6 +410,12 @@ // location will have their range group association changed to // UVM_RANGE_GROUP_ID_NONE. // +// If the Confidential Computing feature is enabled in the system, any VA +// ranges allocated using UvmAllocSemaphorePool and owned by this GPU will be +// unmapped from all GPUs and the CPU. UvmFree must still be called on those +// ranges to reclaim the VA. See UvmAllocSemaphorePool to determine which GPU +// is considered the owner. +// // Arguments: // gpuUuid: (INPUT) // UUID of the GPU to unregister. @@ -1094,10 +1100,12 @@ // Creates a new mapping in the virtual address space of the process, populates // it at the specified preferred location, maps it on the provided list of // processors if feasible and associates the range with the given range group. +// If the preferredLocationUuid is the UUID of the CPU, preferred location is +// set to all CPU nodes allowed by the global and thread memory policies. // // This API is equivalent to the following code sequence: // UvmMemMap(base, length); -// UvmSetPreferredLocation(base, length, preferredLocationUuid); +// UvmSetPreferredLocation(base, length, preferredLocationUuid, -1); // for (i = 0; i < accessedByCount; i++) { // UvmSetAccessedBy(base, length, &accessedByUuids[i]); // } @@ -1262,6 +1270,12 @@ // // The VA range can be unmapped and freed via a call to UvmFree. // +// If the Confidential Computing feature is enabled in the system, at least one +// GPU must be provided in the perGpuAttribs array. The first GPU in the array +// is considered the owning GPU. If the owning GPU is unregistered via +// UvmUnregisterGpu, this allocation will no longer be usable. +// See UvmUnregisterGpu. +// // Arguments: // base: (INPUT) // Base address of the virtual address range. @@ -1298,6 +1312,8 @@ // NV_ERR_INVALID_ARGUMENT: // perGpuAttribs is NULL but gpuAttribsCount is non-zero or vice-versa, // or caching is requested on more than one GPU. +// The Confidential Computing feature is enabled and the perGpuAttribs +// list is empty. // // NV_ERR_NOT_SUPPORTED: // The current process is not the one which called UvmInitialize, and @@ -1444,7 +1460,7 @@ NV_STATUS UvmMigrate(void *base, NvLength length, const NvProcessorUuid *destinationUuid, - NvU32 preferredCpuMemoryNode); + NvS32 preferredCpuMemoryNode); #endif //------------------------------------------------------------------------------ @@ -1537,7 +1553,7 @@ NV_STATUS UvmMigrateAsync(void *base, NvLength length, const NvProcessorUuid *destinationUuid, - NvU32 preferredCpuMemoryNode, + NvS32 preferredCpuMemoryNode, void *semaphoreAddress, NvU32 semaphorePayload); #endif @@ -1746,17 +1762,20 @@ // GPUs. The external allocation can be unmapped from a specific GPU using // UvmUnmapExternal or from all GPUs using UvmFree. // -// The virtual address range specified by (base, length) must be aligned to the -// allocation's physical page size and must fall within a VA range previously -// created with UvmCreateExternalRange. A GPU VA space must have been registered -// for each GPU in the list. The offset in the physical allocation at which the -// allocation must be mapped should also be aligned to the allocation's physical -// page size. The (base, length) range must lie within the largest possible -// virtual address supported by the specified GPUs. +// The virtual address range specified by (base, length) must fall within a VA +// range previously created with UvmCreateExternalRange. A GPU VA space must +// have been registered for each GPU in the list. The (base, length) range must +// lie within the largest possible virtual address supported by the specified +// GPUs. +// +// The page size used for the mapping is the largest supported page size less +// than or equal to the alignments of base, length, offset, and the allocation +// page size. // // If the range specified by (base, length) falls within any existing mappings, // the behavior is the same as if UvmUnmapExternal with the range specified by -// (base, length) had been called first. +// (base, length) had been called first, provided that base and length are +// aligned to the page size used for the existing one. // // If the allocation resides in GPU memory, that GPU must have been registered // via UvmRegisterGpu. If the allocation resides in GPU memory and a mapping is @@ -1838,8 +1857,9 @@ // - The requested address range does not fall entirely within an // existing external VA range created with a single call to // UvmCreateExternalRange. -// - At least one of base and length is not aligned to the allocation's -// physical page size. +// - The mapping page size allowed by the alignments of base, length, +// and offset is smaller than the minimum supported page size on the +// GPU. // - base or base + length fall within an existing mapping but are not // aligned to that mapping's page size. // @@ -1848,8 +1868,7 @@ // address supported by one or more of the specified GPUs. // // NV_ERR_INVALID_OFFSET: -// offset is not aligned to the allocation's physical page size or -// offset+length exceeds the allocation size. +// - offset+length exceeds the allocation size. // // NV_ERR_INVALID_DEVICE: // One of the following occurred: @@ -2214,11 +2233,10 @@ // supported by the specified processor. // // The virtual address range specified by (base, length) must have been -// allocated via a call to either UvmAlloc or UvmMemMap, or be supported -// system-allocated pageable memory. If the input range is pageable memory and -// at least one GPU in the system supports transparent access to pageable -// memory, the behavior described below does not take effect and the preferred -// location of the pages in the given range does not change. +// allocated via a call to either UvmAlloc or UvmMemMap (managed memory), or be +// supported system-allocated pageable memory. If the input range corresponds to +// a file backed shared mapping and least one GPU in the system supports +// transparent access to pageable memory, the behavior below is not guaranteed. // // If any pages in the VA range are associated with a range group that was made // non-migratable via UvmPreventMigrationRangeGroups, then those pages are @@ -2237,17 +2255,17 @@ // not cause a migration if a mapping for that page from that processor can be // established without migrating the page. // -// When a page migrates away from its preferred location, the mapping on the -// preferred location's processor is cleared so that the next access from that -// processor will cause a fault and migrate the page back to its preferred -// location. In other words, a page is mapped on the preferred location's -// processor only if the page is in its preferred location. Thus, when the -// preferred location changes, mappings to pages in the given range are removed -// from the new preferred location if the pages are resident in a different -// processor. Note that if the preferred location's processor is a GPU, then a -// mapping from that GPU to a page in the VA range is only created if a GPU VA -// space has been registered for that GPU and the page is in its preferred -// location. +// When a page that was allocated via either UvmAlloc or UvmMemMap migrates away +// from its preferred location, the mapping on the preferred location's +// processor is cleared so that the next access from that processor will cause a +// fault and migrate the page back to its preferred location. In other words, a +// page is mapped on the preferred location's processor only if the page is in +// its preferred location. Thus, when the preferred location changes, mappings +// to pages in the given range are removed from the new preferred location if +// the pages are resident in a different processor. Note that if the preferred +// location's processor is a GPU, then a mapping from that GPU to a page in the +// VA range is only created if a GPU VA space has been registered for that GPU +// and the page is in its preferred location. // // If read duplication has been enabled for any pages in this VA range and // UvmPreventMigrationRangeGroups has not been called on the range group that @@ -2260,7 +2278,7 @@ // // If the preferred location processor is present in the accessed-by list of any // of the pages in this VA range, then the migration and mapping policies -// associated with associated with the accessed-by list. +// associated with this API override those associated with the accessed-by list. // // The state set by this API can be cleared either by calling // UvmUnsetPreferredLocation for the same VA range or by calling @@ -2281,35 +2299,66 @@ // preferredLocationUuid: (INPUT) // UUID of the preferred location. // +// preferredCpuNumaNode: (INPUT) +// Preferred CPU NUMA memory node used if preferredLocationUuid is the +// UUID of the CPU. -1 is a special value which indicates all CPU nodes +// allowed by the global and thread memory policies. This argument is +// ignored if preferredLocationUuid refers to a GPU or the given virtual +// address range corresponds to managed memory. If NUMA is not enabled, +// only 0 or -1 is allowed. +// // Errors: // NV_ERR_INVALID_ADDRESS: -// base and length are not properly aligned, or the range does not -// represent a valid UVM allocation, or the range is pageable memory and -// the system does not support accessing pageable memory, or the range -// does not represent a supported Operating System allocation. +// One of the following occurred: +// - base and length are not properly aligned. +// - The range does not represent a valid UVM allocation. +// - The range is pageable memory and the system does not support +// accessing pageable memory. +// - The range does not represent a supported Operating System +// allocation. // // NV_ERR_OUT_OF_RANGE: // The VA range exceeds the largest virtual address supported by the // specified processor. // // NV_ERR_INVALID_DEVICE: -// preferredLocationUuid is neither the UUID of the CPU nor the UUID of -// a GPU that was registered by this process. Or at least one page in -// VA range belongs to a non-migratable range group and the specified -// UUID represents a fault-capable GPU. Or preferredLocationUuid is the -// UUID of a non-fault-capable GPU and at least one page in the VA range -// belongs to a non-migratable range group and another non-fault-capable -// GPU is in the accessed-by list of the same page but P2P support -// between both GPUs has not been enabled. +// One of the following occurred: +// - preferredLocationUuid is neither the UUID of the CPU nor the UUID +// of a GPU that was registered by this process. +// - At least one page in VA range belongs to a non-migratable range +// group and the specified UUID represents a fault-capable GPU. +// - preferredLocationUuid is the UUID of a non-fault-capable GPU and at +// least one page in the VA range belongs to a non-migratable range +// group and another non-fault-capable GPU is in the accessed-by list +// of the same page but P2P support between both GPUs has not been +// enabled. +// +// NV_ERR_INVALID_ARGUMENT: +// One of the following occured: +// - preferredLocationUuid is the UUID of a CPU and preferredCpuNumaNode +// refers to a registered GPU. +// - preferredCpuNumaNode is invalid and preferredLocationUuid is the +// UUID of the CPU. +// +// NV_ERR_NOT_SUPPORTED: +// The UVM file descriptor is associated with another process and the +// input virtual range corresponds to system-allocated pageable memory. // // NV_ERR_GENERIC: // Unexpected error. We try hard to avoid returning this error code, // because it is not very informative. // //------------------------------------------------------------------------------ +#if UVM_API_REV_IS_AT_MOST(7) NV_STATUS UvmSetPreferredLocation(void *base, NvLength length, const NvProcessorUuid *preferredLocationUuid); +#else +NV_STATUS UvmSetPreferredLocation(void *base, + NvLength length, + const NvProcessorUuid *preferredLocationUuid, + NvS32 preferredCpuNumaNode); +#endif //------------------------------------------------------------------------------ // UvmUnsetPreferredLocation @@ -2323,10 +2372,9 @@ // // The virtual address range specified by (base, length) must have been // allocated via a call to either UvmAlloc or UvmMemMap, or be supported -// system-allocated pageable memory. If the input range is pageable memory and -// at least one GPU in the system supports transparent access to pageable -// memory, the behavior described below does not take effect and the preferred -// location of the pages in the given range does not change. +// system-allocated pageable memory. If the input range corresponds to a file +// backed shared mapping and least one GPU in the system supports transparent +// access to pageable memory, the behavior below is not guaranteed. // // If the VA range is associated with a non-migratable range group, then that // association is cleared. i.e. the pages in this VA range have their range @@ -2345,10 +2393,18 @@ // // Errors: // NV_ERR_INVALID_ADDRESS: -// base and length are not properly aligned or the range does not -// represent a valid UVM allocation, or the range is pageable memory and -// the system does not support accessing pageable memory, or the range -// does not represent a supported Operating System allocation. +// One of the following occured: +// - base and length are not properly aligned or the range does not +// represent a valid UVM allocation. +// - The range is pageable memory and the system does not support +// accessing pageable memory. +// - The range does not represent a supported Operating System +// allocation. +// - The range contains both managed and pageable memory allocations. +// +// NV_ERR_NOT_SUPPORTED: +// The UVM file descriptor is associated with another process and the +// input virtual range corresponds to system-allocated pageable memory. // // NV_ERR_GENERIC: // Unexpected error. We try hard to avoid returning this error code, @@ -2629,14 +2685,35 @@ // NV_ERR_INVALID_STATE: // UVM was not initialized before calling this function. // -// NV_ERR_GENERIC: -// Unexpected error. We try hard to avoid returning this error code, -// because it is not very informative. -// //------------------------------------------------------------------------------ NV_STATUS UvmGetFileDescriptor(UvmFileDescriptor *returnedFd); //------------------------------------------------------------------------------ +// UvmGetMmFileDescriptor +// +// Returns the UVM file descriptor currently being used to keep the +// memory management context valid. The data type of the returned file +// descriptor is platform specific. +// +// If UvmInitialize has not yet been called, an error is returned. +// +// Arguments: +// returnedFd: (OUTPUT) +// A platform specific file descriptor. +// +// Error codes: +// NV_ERR_INVALID_ARGUMENT: +// returnedFd is NULL. +// +// NV_ERR_INVALID_STATE: +// UVM was not initialized before calling this function. +// +// NV_ERR_NOT_SUPPORTED: +// This file descriptor is not required on this platform. +//------------------------------------------------------------------------------ +NV_STATUS UvmGetMmFileDescriptor(UvmFileDescriptor *returnedFd); + +//------------------------------------------------------------------------------ // UvmIs8Supported // // Returns whether the kernel driver has been loaded in UVM 8 mode or not. diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/kernel-open/nvidia-uvm/uvm_ada.c nvidia-open-gpu-kernel-modules-535.161.08/kernel-open/nvidia-uvm/uvm_ada.c --- nvidia-open-gpu-kernel-modules-525.147.05/kernel-open/nvidia-uvm/uvm_ada.c 2023-10-25 20:33:27.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/kernel-open/nvidia-uvm/uvm_ada.c 2024-03-05 22:25:59.000000000 +0000 @@ -1,5 +1,5 @@ /******************************************************************************* - Copyright (c) 2021 NVIDIA Corporation + Copyright (c) 2021-2023 NVIDIA Corporation Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation files (the "Software"), to @@ -49,11 +49,13 @@ // A single top level PDE on Ada covers 128 TB and that's the minimum size // that can be used. parent_gpu->rm_va_base = 0; - parent_gpu->rm_va_size = 128ull * 1024 * 1024 * 1024 * 1024; + parent_gpu->rm_va_size = 128 * UVM_SIZE_1TB; - parent_gpu->uvm_mem_va_base = 384ull * 1024 * 1024 * 1024 * 1024; + parent_gpu->uvm_mem_va_base = 384 * UVM_SIZE_1TB; parent_gpu->uvm_mem_va_size = UVM_MEM_VA_SIZE; + parent_gpu->ce_phys_vidmem_write_supported = true; + parent_gpu->peer_copy_mode = g_uvm_global.peer_copy_mode; // Not all units on Ada support 49-bit addressing, including those which @@ -92,4 +94,6 @@ parent_gpu->map_remap_larger_page_promotion = false; parent_gpu->plc_supported = true; + + parent_gpu->no_ats_range_required = false; } diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/kernel-open/nvidia-uvm/uvm_ampere.c nvidia-open-gpu-kernel-modules-535.161.08/kernel-open/nvidia-uvm/uvm_ampere.c --- nvidia-open-gpu-kernel-modules-525.147.05/kernel-open/nvidia-uvm/uvm_ampere.c 2023-10-25 20:33:39.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/kernel-open/nvidia-uvm/uvm_ampere.c 2024-03-05 22:25:57.000000000 +0000 @@ -47,14 +47,16 @@ // A single top level PDE on Ampere covers 128 TB and that's the minimum // size that can be used. parent_gpu->rm_va_base = 0; - parent_gpu->rm_va_size = 128ull * 1024 * 1024 * 1024 * 1024; + parent_gpu->rm_va_size = 128 * UVM_SIZE_1TB; - parent_gpu->uvm_mem_va_base = 384ull * 1024 * 1024 * 1024 * 1024; + parent_gpu->uvm_mem_va_base = 384 * UVM_SIZE_1TB; parent_gpu->uvm_mem_va_size = UVM_MEM_VA_SIZE; // See uvm_mmu.h for mapping placement - parent_gpu->flat_vidmem_va_base = 136ull * 1024 * 1024 * 1024 * 1024; - parent_gpu->flat_sysmem_va_base = 256ull * 1024 * 1024 * 1024 * 1024; + parent_gpu->flat_vidmem_va_base = 136 * UVM_SIZE_1TB; + parent_gpu->flat_sysmem_va_base = 256 * UVM_SIZE_1TB; + + parent_gpu->ce_phys_vidmem_write_supported = true; parent_gpu->peer_copy_mode = g_uvm_global.peer_copy_mode; @@ -99,4 +101,6 @@ parent_gpu->map_remap_larger_page_promotion = false; parent_gpu->plc_supported = true; + + parent_gpu->no_ats_range_required = false; } diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/kernel-open/nvidia-uvm/uvm_ampere_ce.c nvidia-open-gpu-kernel-modules-535.161.08/kernel-open/nvidia-uvm/uvm_ampere_ce.c --- nvidia-open-gpu-kernel-modules-525.147.05/kernel-open/nvidia-uvm/uvm_ampere_ce.c 2023-10-25 20:33:39.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/kernel-open/nvidia-uvm/uvm_ampere_ce.c 2024-03-05 22:25:57.000000000 +0000 @@ -27,7 +27,7 @@ #include "clc7b5.h" #include "clc56f.h" // Needed because HAL ce_init pushes SET_OBJECT -bool uvm_hal_ampere_ce_method_validate_c6b5(uvm_push_t *push, NvU32 method_address, NvU32 method_data) +bool uvm_hal_ampere_ce_method_is_valid_c6b5(uvm_push_t *push, NvU32 method_address, NvU32 method_data) { if (!uvm_channel_is_proxy(push->channel)) return true; @@ -112,7 +112,7 @@ return HWCONST(C7B5, LAUNCH_DMA, DISABLE_PLC, TRUE); } -bool uvm_hal_ampere_ce_memcopy_validate_c6b5(uvm_push_t *push, uvm_gpu_address_t dst, uvm_gpu_address_t src) +bool uvm_hal_ampere_ce_memcopy_is_valid_c6b5(uvm_push_t *push, uvm_gpu_address_t dst, uvm_gpu_address_t src) { NvU64 push_begin_gpu_va; uvm_gpu_t *gpu = uvm_push_get_gpu(push); @@ -121,6 +121,8 @@ return true; if (uvm_channel_is_proxy(push->channel)) { + uvm_pushbuffer_t *pushbuffer; + if (dst.is_virtual) { UVM_ERR_PRINT("Destination address of memcopy must be physical, not virtual\n"); return false; @@ -142,7 +144,8 @@ return false; } - push_begin_gpu_va = uvm_pushbuffer_get_gpu_va_for_push(push->channel->pool->manager->pushbuffer, push); + pushbuffer = uvm_channel_get_pushbuffer(push->channel); + push_begin_gpu_va = uvm_pushbuffer_get_gpu_va_for_push(pushbuffer, push); if ((src.address < push_begin_gpu_va) || (src.address >= push_begin_gpu_va + uvm_push_get_size(push))) { UVM_ERR_PRINT("Source address of memcopy must point to pushbuffer\n"); @@ -177,13 +180,19 @@ // irrespective of the virtualization mode. void uvm_hal_ampere_ce_memcopy_patch_src_c6b5(uvm_push_t *push, uvm_gpu_address_t *src) { + uvm_pushbuffer_t *pushbuffer; + if (!uvm_channel_is_proxy(push->channel)) return; - src->address -= uvm_pushbuffer_get_gpu_va_for_push(push->channel->pool->manager->pushbuffer, push); + pushbuffer = uvm_channel_get_pushbuffer(push->channel); + src->address -= uvm_pushbuffer_get_gpu_va_for_push(pushbuffer, push); } -bool uvm_hal_ampere_ce_memset_validate_c6b5(uvm_push_t *push, uvm_gpu_address_t dst, size_t element_size) +bool uvm_hal_ampere_ce_memset_is_valid_c6b5(uvm_push_t *push, + uvm_gpu_address_t dst, + size_t num_elements, + size_t element_size) { uvm_gpu_t *gpu = uvm_push_get_gpu(push); diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/kernel-open/nvidia-uvm/uvm_ampere_host.c nvidia-open-gpu-kernel-modules-535.161.08/kernel-open/nvidia-uvm/uvm_ampere_host.c --- nvidia-open-gpu-kernel-modules-525.147.05/kernel-open/nvidia-uvm/uvm_ampere_host.c 2023-10-25 20:33:39.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/kernel-open/nvidia-uvm/uvm_ampere_host.c 2024-03-05 22:25:57.000000000 +0000 @@ -29,7 +29,7 @@ #include "clc56f.h" #include "clc076.h" -bool uvm_hal_ampere_host_method_validate(uvm_push_t *push, NvU32 method_address, NvU32 method_data) +bool uvm_hal_ampere_host_method_is_valid(uvm_push_t *push, NvU32 method_address, NvU32 method_data) { uvm_gpu_t *gpu = uvm_push_get_gpu(push); @@ -82,7 +82,7 @@ return true; } -bool uvm_hal_ampere_host_sw_method_validate(uvm_push_t *push, NvU32 method_address, NvU32 method_data) +bool uvm_hal_ampere_host_sw_method_is_valid(uvm_push_t *push, NvU32 method_address, NvU32 method_data) { if (!uvm_channel_is_proxy(push->channel)) return true; diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/kernel-open/nvidia-uvm/uvm_api.h nvidia-open-gpu-kernel-modules-535.161.08/kernel-open/nvidia-uvm/uvm_api.h --- nvidia-open-gpu-kernel-modules-525.147.05/kernel-open/nvidia-uvm/uvm_api.h 2023-10-25 20:33:34.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/kernel-open/nvidia-uvm/uvm_api.h 2024-03-05 22:25:51.000000000 +0000 @@ -25,6 +25,7 @@ #define __UVM_API_H__ #include "uvm_types.h" +#include "uvm_common.h" #include "uvm_ioctl.h" #include "uvm_linux.h" #include "uvm_lock.h" @@ -51,8 +52,10 @@ \ params.rmStatus = uvm_global_get_status(); \ if (params.rmStatus == NV_OK) { \ - if (do_init_check) \ - params.rmStatus = uvm_va_space_initialized(uvm_va_space_get(filp)); \ + if (do_init_check) { \ + if (!uvm_fd_va_space(filp)) \ + params.rmStatus = NV_ERR_ILLEGAL_ACTION; \ + } \ if (likely(params.rmStatus == NV_OK)) \ params.rmStatus = function_name(¶ms, filp); \ } \ @@ -88,8 +91,10 @@ \ params->rmStatus = uvm_global_get_status(); \ if (params->rmStatus == NV_OK) { \ - if (do_init_check) \ - params->rmStatus = uvm_va_space_initialized(uvm_va_space_get(filp)); \ + if (do_init_check) { \ + if (!uvm_fd_va_space(filp)) \ + params->rmStatus = NV_ERR_ILLEGAL_ACTION; \ + } \ if (likely(params->rmStatus == NV_OK)) \ params->rmStatus = function_name(params, filp); \ } \ @@ -196,21 +201,20 @@ return uvm_api_range_invalid_aligned(base, length, UVM_PAGE_SIZE_64K); } -// Returns true if the interval [start, start + length -1] is entirely covered -// by vmas. -// -// LOCKING: mm->mmap_lock must be held in at least read mode. -bool uvm_is_valid_vma_range(struct mm_struct *mm, NvU64 start, NvU64 length); +typedef enum +{ + UVM_API_RANGE_TYPE_MANAGED, + UVM_API_RANGE_TYPE_HMM, + UVM_API_RANGE_TYPE_ATS, + UVM_API_RANGE_TYPE_INVALID +} uvm_api_range_type_t; -// Check that the interval [base, base + length) is fully covered by UVM -// managed ranges (NV_OK is returned), or (if ATS is enabled and mm != NULL) -// fully covered by valid vmas (NV_WARN_NOTHING_TO_DO is returned), or (if HMM -// is enabled and mm != NULL) fully covered by valid vmas (NV_OK is returned). -// Any other input results in a return status of NV_ERR_INVALID_ADDRESS. +// If the interval [base, base + length) is fully covered by VMAs which all have +// the same uvm_api_range_type_t, that range type is returned. // // LOCKING: va_space->lock must be held in at least read mode. If mm != NULL, // mm->mmap_lock must also be held in at least read mode. -NV_STATUS uvm_api_range_type_check(uvm_va_space_t *va_space, struct mm_struct *mm, NvU64 base, NvU64 length); +uvm_api_range_type_t uvm_api_range_type_check(uvm_va_space_t *va_space, struct mm_struct *mm, NvU64 base, NvU64 length); NV_STATUS uvm_api_pageable_mem_access_on_gpu(UVM_PAGEABLE_MEM_ACCESS_ON_GPU_PARAMS *params, struct file *filp); NV_STATUS uvm_api_register_gpu(UVM_REGISTER_GPU_PARAMS *params, struct file *filp); diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/kernel-open/nvidia-uvm/uvm_ats.c nvidia-open-gpu-kernel-modules-535.161.08/kernel-open/nvidia-uvm/uvm_ats.c --- nvidia-open-gpu-kernel-modules-525.147.05/kernel-open/nvidia-uvm/uvm_ats.c 2023-10-25 20:33:41.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/kernel-open/nvidia-uvm/uvm_ats.c 2024-03-05 22:26:05.000000000 +0000 @@ -44,6 +44,8 @@ void uvm_ats_init_va_space(uvm_va_space_t *va_space) { + uvm_init_rwsem(&va_space->ats.lock, UVM_LOCK_ORDER_LEAF); + if (UVM_ATS_IBM_SUPPORTED()) uvm_ats_ibm_init_va_space(va_space); } @@ -57,6 +59,10 @@ return uvm_ats_ibm_add_gpu(parent_gpu); } + else if (UVM_ATS_SVA_SUPPORTED()) { + if (g_uvm_global.ats.enabled) + return uvm_ats_sva_add_gpu(parent_gpu); + } return NV_OK; } @@ -71,6 +77,10 @@ uvm_ats_ibm_remove_gpu(parent_gpu); } + else if (UVM_ATS_SVA_SUPPORTED()) { + if (g_uvm_global.ats.enabled) + uvm_ats_sva_remove_gpu(parent_gpu); + } } NV_STATUS uvm_ats_bind_gpu(uvm_gpu_va_space_t *gpu_va_space) @@ -87,6 +97,8 @@ if (UVM_ATS_IBM_SUPPORTED()) status = uvm_ats_ibm_bind_gpu(gpu_va_space); + else if (UVM_ATS_SVA_SUPPORTED()) + status = uvm_ats_sva_bind_gpu(gpu_va_space); return status; } @@ -100,6 +112,8 @@ if (UVM_ATS_IBM_SUPPORTED()) uvm_ats_ibm_unbind_gpu(gpu_va_space); + else if (UVM_ATS_SVA_SUPPORTED()) + uvm_ats_sva_unbind_gpu(gpu_va_space); } NV_STATUS uvm_ats_register_gpu_va_space(uvm_gpu_va_space_t *gpu_va_space) @@ -126,6 +140,8 @@ if (UVM_ATS_IBM_SUPPORTED()) status = uvm_ats_ibm_register_gpu_va_space(gpu_va_space); + else if (UVM_ATS_SVA_SUPPORTED()) + status = uvm_ats_sva_register_gpu_va_space(gpu_va_space); if (status == NV_OK) uvm_processor_mask_set(&va_space->ats.registered_gpu_va_spaces, gpu_id); @@ -148,6 +164,8 @@ if (UVM_ATS_IBM_SUPPORTED()) uvm_ats_ibm_unregister_gpu_va_space(gpu_va_space); + else if (UVM_ATS_SVA_SUPPORTED()) + uvm_ats_sva_unregister_gpu_va_space(gpu_va_space); uvm_va_space_down_write(va_space); uvm_processor_mask_clear(&va_space->ats.registered_gpu_va_spaces, gpu_id); diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/kernel-open/nvidia-uvm/uvm_ats.h nvidia-open-gpu-kernel-modules-535.161.08/kernel-open/nvidia-uvm/uvm_ats.h --- nvidia-open-gpu-kernel-modules-525.147.05/kernel-open/nvidia-uvm/uvm_ats.h 2023-10-25 20:33:41.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/kernel-open/nvidia-uvm/uvm_ats.h 2024-03-05 22:26:05.000000000 +0000 @@ -28,8 +28,21 @@ #include "uvm_forward_decl.h" #include "uvm_ats_ibm.h" #include "nv_uvm_types.h" +#include "uvm_lock.h" - #define UVM_ATS_SUPPORTED() (UVM_ATS_IBM_SUPPORTED()) + #include "uvm_ats_sva.h" + + #define UVM_ATS_SUPPORTED() (UVM_ATS_IBM_SUPPORTED() || UVM_ATS_SVA_SUPPORTED()) + +// ATS prefetcher uses hmm_range_fault() to query residency information. +// hmm_range_fault() needs CONFIG_HMM_MIRROR. To detect racing CPU invalidates +// of memory regions while hmm_range_fault() is being called, MMU interval +// notifiers are needed. + #if defined(CONFIG_HMM_MIRROR) && defined(NV_MMU_INTERVAL_NOTIFIER) + #define UVM_ATS_PREFETCH_SUPPORTED() 1 + #else + #define UVM_ATS_PREFETCH_SUPPORTED() 0 + #endif typedef struct { @@ -37,10 +50,15 @@ // indexed by gpu->id. This mask is protected by the VA space lock. uvm_processor_mask_t registered_gpu_va_spaces; + // Protects racing invalidates in the VA space while hmm_range_fault() is + // being called in ats_compute_residency_mask(). + uvm_rw_semaphore_t lock; + union { uvm_ibm_va_space_t ibm; + uvm_sva_va_space_t sva; }; } uvm_ats_va_space_t; @@ -58,6 +76,7 @@ { uvm_ibm_gpu_va_space_t ibm; + uvm_sva_gpu_va_space_t sva; }; } uvm_ats_gpu_va_space_t; @@ -90,6 +109,8 @@ // LOCKING: mmap_lock must be lockable. // VA space lock must be lockable. // gpu_va_space->gpu must be retained. +// mm must be retained with uvm_va_space_mm_retain() iff +// UVM_ATS_SVA_SUPPORTED() is 1 NV_STATUS uvm_ats_bind_gpu(uvm_gpu_va_space_t *gpu_va_space); // Decrements the refcount on the {gpu, mm} pair. Removes the binding from the diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/kernel-open/nvidia-uvm/uvm_ats_faults.c nvidia-open-gpu-kernel-modules-535.161.08/kernel-open/nvidia-uvm/uvm_ats_faults.c --- nvidia-open-gpu-kernel-modules-525.147.05/kernel-open/nvidia-uvm/uvm_ats_faults.c 2023-10-25 20:33:42.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/kernel-open/nvidia-uvm/uvm_ats_faults.c 2024-03-05 22:26:05.000000000 +0000 @@ -1,5 +1,5 @@ /******************************************************************************* - Copyright (c) 2018 NVIDIA Corporation + Copyright (c) 2023 NVIDIA Corporation Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation files (the "Software"), to @@ -20,74 +20,33 @@ DEALINGS IN THE SOFTWARE. *******************************************************************************/ +#include "uvm_api.h" #include "uvm_tools.h" #include "uvm_va_range.h" +#include "uvm_ats.h" #include "uvm_ats_faults.h" #include "uvm_migrate_pageable.h" - -// TODO: Bug 2103669: Implement a real prefetching policy and remove or adapt -// these experimental parameters. These are intended to help guide that policy. -static unsigned int uvm_exp_perf_prefetch_ats_order_replayable = 0; -module_param(uvm_exp_perf_prefetch_ats_order_replayable, uint, 0644); -MODULE_PARM_DESC(uvm_exp_perf_prefetch_ats_order_replayable, - "Max order of pages (2^N) to prefetch on replayable ATS faults"); - -static unsigned int uvm_exp_perf_prefetch_ats_order_non_replayable = 0; -module_param(uvm_exp_perf_prefetch_ats_order_non_replayable, uint, 0644); -MODULE_PARM_DESC(uvm_exp_perf_prefetch_ats_order_non_replayable, - "Max order of pages (2^N) to prefetch on non-replayable ATS faults"); - -// Expand the fault region to the naturally-aligned region with order given by -// the module parameters, clamped to the vma containing fault_addr (if any). -// Note that this means the region contains fault_addr but may not begin at -// fault_addr. -static void expand_fault_region(struct mm_struct *mm, - NvU64 fault_addr, - uvm_fault_client_type_t client_type, - unsigned long *start, - unsigned long *size) -{ - struct vm_area_struct *vma; - unsigned int order; - unsigned long outer, aligned_start, aligned_size; - - *start = fault_addr; - *size = PAGE_SIZE; - - if (client_type == UVM_FAULT_CLIENT_TYPE_HUB) - order = uvm_exp_perf_prefetch_ats_order_non_replayable; - else - order = uvm_exp_perf_prefetch_ats_order_replayable; - - if (order == 0) - return; - - vma = find_vma_intersection(mm, fault_addr, fault_addr + 1); - if (!vma) - return; - - UVM_ASSERT(order < BITS_PER_LONG - PAGE_SHIFT); - - aligned_size = (1UL << order) * PAGE_SIZE; - - aligned_start = fault_addr & ~(aligned_size - 1); - - *start = max(vma->vm_start, aligned_start); - outer = min(vma->vm_end, aligned_start + aligned_size); - *size = outer - *start; -} - -static NV_STATUS uvm_ats_service_fault(uvm_gpu_va_space_t *gpu_va_space, - NvU64 fault_addr, - uvm_fault_access_type_t access_type, - uvm_fault_client_type_t client_type) +#include +#include +#include + +#if UVM_ATS_PREFETCH_SUPPORTED() +#include +#endif + +static NV_STATUS service_ats_faults(uvm_gpu_va_space_t *gpu_va_space, + struct vm_area_struct *vma, + NvU64 start, + size_t length, + uvm_fault_access_type_t access_type, + uvm_ats_fault_context_t *ats_context) { uvm_va_space_t *va_space = gpu_va_space->va_space; struct mm_struct *mm = va_space->va_space_mm.mm; bool write = (access_type >= UVM_FAULT_ACCESS_TYPE_WRITE); NV_STATUS status; - NvU64 start; - NvU64 length; + NvU64 user_space_start; + NvU64 user_space_length; // Request uvm_migrate_pageable() to touch the corresponding page after // population. @@ -96,17 +55,18 @@ // 2) guest physical -> host physical // // The overall ATS translation will fault if either of those translations is - // invalid. The get_user_pages() call above handles translation #1, but not - // #2. We don't know if we're running as a guest, but in case we are we can - // force that translation to be valid by touching the guest physical address - // from the CPU. If the translation is not valid then the access will cause - // a hypervisor fault. Note that dma_map_page() can't establish mappings - // used by GPU ATS SVA translations. GPU accesses to host physical addresses - // obtained as a result of the address translation request uses the CPU - // address space instead of the IOMMU address space since the translated - // host physical address isn't necessarily an IOMMU address. The only way to - // establish guest physical to host physical mapping in the CPU address - // space is to touch the page from the CPU. + // invalid. The pin_user_pages() call within uvm_migrate_pageable() call + // below handles translation #1, but not #2. We don't know if we're running + // as a guest, but in case we are we can force that translation to be valid + // by touching the guest physical address from the CPU. If the translation + // is not valid then the access will cause a hypervisor fault. Note that + // dma_map_page() can't establish mappings used by GPU ATS SVA translations. + // GPU accesses to host physical addresses obtained as a result of the + // address translation request uses the CPU address space instead of the + // IOMMU address space since the translated host physical address isn't + // necessarily an IOMMU address. The only way to establish guest physical to + // host physical mapping in the CPU address space is to touch the page from + // the CPU. // // We assume that the hypervisor mappings are all VM_PFNMAP, VM_SHARED, and // VM_WRITE, meaning that the mappings are all granted write access on any @@ -117,23 +77,22 @@ uvm_migrate_args_t uvm_migrate_args = { - .va_space = va_space, - .mm = mm, - .dst_id = gpu_va_space->gpu->parent->id, - .dst_node_id = -1, - .populate_permissions = write ? UVM_POPULATE_PERMISSIONS_WRITE : UVM_POPULATE_PERMISSIONS_ANY, - .touch = true, - .skip_mapped = true, - .user_space_start = &start, - .user_space_length = &length, + .va_space = va_space, + .mm = mm, + .dst_id = ats_context->residency_id, + .dst_node_id = ats_context->residency_node, + .start = start, + .length = length, + .populate_permissions = write ? UVM_POPULATE_PERMISSIONS_WRITE : UVM_POPULATE_PERMISSIONS_ANY, + .touch = true, + .skip_mapped = true, + .populate_on_cpu_alloc_failures = true, + .user_space_start = &user_space_start, + .user_space_length = &user_space_length, }; UVM_ASSERT(uvm_ats_can_service_faults(gpu_va_space, mm)); - expand_fault_region(mm, fault_addr, client_type, &uvm_migrate_args.start, &uvm_migrate_args.length); - - // TODO: Bug 2103669: Service more than a single fault at a time - // // We are trying to use migrate_vma API in the kernel (if it exists) to // populate and map the faulting region on the GPU. We want to do this only // on the first touch. That is, pages which are not already mapped. So, we @@ -148,114 +107,466 @@ return status; } -NV_STATUS uvm_ats_service_fault_entry(uvm_gpu_va_space_t *gpu_va_space, - uvm_fault_buffer_entry_t *current_entry, - uvm_ats_fault_invalidate_t *ats_invalidate) +static void flush_tlb_va_region(uvm_gpu_va_space_t *gpu_va_space, + NvU64 addr, + size_t size, + uvm_fault_client_type_t client_type) +{ + uvm_ats_fault_invalidate_t *ats_invalidate; + + if (client_type == UVM_FAULT_CLIENT_TYPE_GPC) + ats_invalidate = &gpu_va_space->gpu->parent->fault_buffer_info.replayable.ats_invalidate; + else + ats_invalidate = &gpu_va_space->gpu->parent->fault_buffer_info.non_replayable.ats_invalidate; + + if (!ats_invalidate->tlb_batch_pending) { + uvm_tlb_batch_begin(&gpu_va_space->page_tables, &ats_invalidate->tlb_batch); + ats_invalidate->tlb_batch_pending = true; + } + + uvm_tlb_batch_invalidate(&ats_invalidate->tlb_batch, addr, size, PAGE_SIZE, UVM_MEMBAR_NONE); +} + +static void ats_batch_select_residency(uvm_gpu_va_space_t *gpu_va_space, + struct vm_area_struct *vma, + uvm_ats_fault_context_t *ats_context) +{ + uvm_gpu_t *gpu = gpu_va_space->gpu; + int residency = uvm_gpu_numa_node(gpu); + +#if defined(NV_MEMPOLICY_HAS_UNIFIED_NODES) + struct mempolicy *vma_policy = vma_policy(vma); + unsigned short mode; + + ats_context->prefetch_state.has_preferred_location = false; + + // It's safe to read vma_policy since the mmap_lock is held in at least read + // mode in this path. + uvm_assert_mmap_lock_locked(vma->vm_mm); + + if (!vma_policy) + goto done; + + mode = vma_policy->mode; + + if ((mode == MPOL_BIND) +#if defined(NV_MPOL_PREFERRED_MANY_PRESENT) + || (mode == MPOL_PREFERRED_MANY) +#endif + || (mode == MPOL_PREFERRED)) { + int home_node = NUMA_NO_NODE; + +#if defined(NV_MEMPOLICY_HAS_HOME_NODE) + if ((mode != MPOL_PREFERRED) && (vma_policy->home_node != NUMA_NO_NODE)) + home_node = vma_policy->home_node; +#endif + + // Prefer home_node if set. Otherwise, prefer the faulting GPU if it's + // in the list of preferred nodes, else prefer the closest_cpu_numa_node + // to the GPU if closest_cpu_numa_node is in the list of preferred + // nodes. Fallback to the faulting GPU if all else fails. + if (home_node != NUMA_NO_NODE) { + residency = home_node; + } + else if (!node_isset(residency, vma_policy->nodes)) { + int closest_cpu_numa_node = gpu->parent->closest_cpu_numa_node; + + if ((closest_cpu_numa_node != NUMA_NO_NODE) && node_isset(closest_cpu_numa_node, vma_policy->nodes)) + residency = gpu->parent->closest_cpu_numa_node; + else + residency = first_node(vma_policy->nodes); + } + + if (!nodes_empty(vma_policy->nodes)) + ats_context->prefetch_state.has_preferred_location = true; + } + + // Update gpu if residency is not the faulting gpu. + if (residency != uvm_gpu_numa_node(gpu)) + gpu = uvm_va_space_find_gpu_with_memory_node_id(gpu_va_space->va_space, residency); + +done: +#else + ats_context->prefetch_state.has_preferred_location = false; +#endif + + ats_context->residency_id = gpu ? gpu->parent->id : UVM_ID_CPU; + ats_context->residency_node = residency; +} + +static void get_range_in_vma(struct vm_area_struct *vma, NvU64 base, NvU64 *start, NvU64 *end) +{ + *start = max(vma->vm_start, (unsigned long) base); + *end = min(vma->vm_end, (unsigned long) (base + UVM_VA_BLOCK_SIZE)); +} + +static uvm_page_index_t uvm_ats_cpu_page_index(NvU64 base, NvU64 addr) +{ + UVM_ASSERT(addr >= base); + UVM_ASSERT(addr <= (base + UVM_VA_BLOCK_SIZE)); + + return (addr - base) / PAGE_SIZE; +} + +// start and end must be aligned to PAGE_SIZE and must fall within +// [base, base + UVM_VA_BLOCK_SIZE] +static uvm_va_block_region_t uvm_ats_region_from_start_end(NvU64 start, NvU64 end) +{ + // base can be greater than, less than or equal to the start of a VMA. + NvU64 base = UVM_VA_BLOCK_ALIGN_DOWN(start); + + UVM_ASSERT(start < end); + UVM_ASSERT(PAGE_ALIGNED(start)); + UVM_ASSERT(PAGE_ALIGNED(end)); + UVM_ASSERT(IS_ALIGNED(base, UVM_VA_BLOCK_SIZE)); + + return uvm_va_block_region(uvm_ats_cpu_page_index(base, start), uvm_ats_cpu_page_index(base, end)); +} + +static uvm_va_block_region_t uvm_ats_region_from_vma(struct vm_area_struct *vma, NvU64 base) +{ + NvU64 start; + NvU64 end; + + get_range_in_vma(vma, base, &start, &end); + + return uvm_ats_region_from_start_end(start, end); +} + +#if UVM_ATS_PREFETCH_SUPPORTED() + +static bool uvm_ats_invalidate_notifier(struct mmu_interval_notifier *mni, unsigned long cur_seq) +{ + uvm_ats_fault_context_t *ats_context = container_of(mni, uvm_ats_fault_context_t, prefetch_state.notifier); + uvm_va_space_t *va_space = ats_context->prefetch_state.va_space; + + // The following write lock protects against concurrent invalidates while + // hmm_range_fault() is being called in ats_compute_residency_mask(). + uvm_down_write(&va_space->ats.lock); + + mmu_interval_set_seq(mni, cur_seq); + + uvm_up_write(&va_space->ats.lock); + + return true; +} + +static bool uvm_ats_invalidate_notifier_entry(struct mmu_interval_notifier *mni, + const struct mmu_notifier_range *range, + unsigned long cur_seq) +{ + UVM_ENTRY_RET(uvm_ats_invalidate_notifier(mni, cur_seq)); +} + +static const struct mmu_interval_notifier_ops uvm_ats_notifier_ops = +{ + .invalidate = uvm_ats_invalidate_notifier_entry, +}; + +#endif + +static NV_STATUS ats_compute_residency_mask(uvm_gpu_va_space_t *gpu_va_space, + struct vm_area_struct *vma, + NvU64 base, + uvm_ats_fault_context_t *ats_context) { - NvU64 gmmu_region_base; - bool in_gmmu_region; NV_STATUS status = NV_OK; - uvm_fault_access_type_t service_access_type; +#if UVM_ATS_PREFETCH_SUPPORTED() + int ret; + NvU64 start; + NvU64 end; + uvm_page_mask_t *residency_mask = &ats_context->prefetch_state.residency_mask; + struct hmm_range range; + uvm_page_index_t page_index; + uvm_va_block_region_t vma_region; + uvm_va_space_t *va_space = gpu_va_space->va_space; + struct mm_struct *mm = va_space->va_space_mm.mm; + + uvm_assert_rwsem_locked_read(&va_space->lock); + + ats_context->prefetch_state.first_touch = true; + + uvm_page_mask_zero(residency_mask); + + get_range_in_vma(vma, base, &start, &end); + + vma_region = uvm_ats_region_from_start_end(start, end); + + range.notifier = &ats_context->prefetch_state.notifier; + range.start = start; + range.end = end; + range.hmm_pfns = ats_context->prefetch_state.pfns; + range.default_flags = 0; + range.pfn_flags_mask = 0; + range.dev_private_owner = NULL; + + ats_context->prefetch_state.va_space = va_space; + + // mmu_interval_notifier_insert() will try to acquire mmap_lock for write + // and will deadlock since mmap_lock is already held for read in this path. + // This is prevented by calling __mmu_notifier_register() during va_space + // creation. See the comment in uvm_mmu_notifier_register() for more + // details. + ret = mmu_interval_notifier_insert(range.notifier, mm, start, end, &uvm_ats_notifier_ops); + if (ret) + return errno_to_nv_status(ret); + + while (true) { + range.notifier_seq = mmu_interval_read_begin(range.notifier); + ret = hmm_range_fault(&range); + if (ret == -EBUSY) + continue; + if (ret) { + status = errno_to_nv_status(ret); + UVM_ASSERT(status != NV_OK); + break; + } + + uvm_down_read(&va_space->ats.lock); + + // Pages may have been freed or re-allocated after hmm_range_fault() is + // called. So the PTE might point to a different page or nothing. In the + // memory hot-unplug case it is not safe to call page_to_nid() on the + // page as the struct page itself may have been freed. To protect + // against these cases, uvm_ats_invalidate_entry() blocks on va_space + // ATS write lock for concurrent invalidates since va_space ATS lock is + // held for read in this path. + if (!mmu_interval_read_retry(range.notifier, range.notifier_seq)) + break; + + uvm_up_read(&va_space->ats.lock); + } + + if (status == NV_OK) { + for_each_va_block_page_in_region(page_index, vma_region) { + unsigned long pfn = ats_context->prefetch_state.pfns[page_index - vma_region.first]; + + if (pfn & HMM_PFN_VALID) { + struct page *page = hmm_pfn_to_page(pfn); + + if (page_to_nid(page) == ats_context->residency_node) + uvm_page_mask_set(residency_mask, page_index); + + ats_context->prefetch_state.first_touch = false; + } + } + + uvm_up_read(&va_space->ats.lock); + } + + mmu_interval_notifier_remove(range.notifier); + +#endif + + return status; +} + +static void ats_expand_fault_region(uvm_gpu_va_space_t *gpu_va_space, + struct vm_area_struct *vma, + uvm_ats_fault_context_t *ats_context, + uvm_va_block_region_t max_prefetch_region, + uvm_page_mask_t *faulted_mask) +{ + uvm_page_mask_t *read_fault_mask = &ats_context->read_fault_mask; + uvm_page_mask_t *write_fault_mask = &ats_context->write_fault_mask; + uvm_page_mask_t *residency_mask = &ats_context->prefetch_state.residency_mask; + uvm_page_mask_t *prefetch_mask = &ats_context->prefetch_state.prefetch_pages_mask; + uvm_perf_prefetch_bitmap_tree_t *bitmap_tree = &ats_context->prefetch_state.bitmap_tree; + + if (uvm_page_mask_empty(faulted_mask)) + return; + + uvm_perf_prefetch_compute_ats(gpu_va_space->va_space, + faulted_mask, + uvm_va_block_region_from_mask(NULL, faulted_mask), + max_prefetch_region, + residency_mask, + bitmap_tree, + prefetch_mask); + + uvm_page_mask_or(read_fault_mask, read_fault_mask, prefetch_mask); + + if (vma->vm_flags & VM_WRITE) + uvm_page_mask_or(write_fault_mask, write_fault_mask, prefetch_mask); +} + +static NV_STATUS ats_fault_prefetch(uvm_gpu_va_space_t *gpu_va_space, + struct vm_area_struct *vma, + NvU64 base, + uvm_ats_fault_context_t *ats_context) +{ + NV_STATUS status = NV_OK; + uvm_page_mask_t *read_fault_mask = &ats_context->read_fault_mask; + uvm_page_mask_t *write_fault_mask = &ats_context->write_fault_mask; + uvm_page_mask_t *faulted_mask = &ats_context->faulted_mask; + uvm_page_mask_t *prefetch_mask = &ats_context->prefetch_state.prefetch_pages_mask; + uvm_va_block_region_t max_prefetch_region = uvm_ats_region_from_vma(vma, base); + + if (!uvm_perf_prefetch_enabled(gpu_va_space->va_space)) + return status; + + if (uvm_page_mask_empty(faulted_mask)) + return status; + + status = ats_compute_residency_mask(gpu_va_space, vma, base, ats_context); + if (status != NV_OK) + return status; + + // Prefetch the entire region if none of the pages are resident on any node + // and if preferred_location is the faulting GPU. + if (ats_context->prefetch_state.has_preferred_location && + ats_context->prefetch_state.first_touch && + uvm_id_equal(ats_context->residency_id, gpu_va_space->gpu->parent->id)) { + + uvm_page_mask_init_from_region(prefetch_mask, max_prefetch_region, NULL); + uvm_page_mask_or(read_fault_mask, read_fault_mask, prefetch_mask); + + if (vma->vm_flags & VM_WRITE) + uvm_page_mask_or(write_fault_mask, write_fault_mask, prefetch_mask); + + return status; + } + + ats_expand_fault_region(gpu_va_space, vma, ats_context, max_prefetch_region, faulted_mask); + + return status; +} + +NV_STATUS uvm_ats_service_faults(uvm_gpu_va_space_t *gpu_va_space, + struct vm_area_struct *vma, + NvU64 base, + uvm_ats_fault_context_t *ats_context) +{ + NV_STATUS status = NV_OK; + uvm_va_block_region_t subregion; + uvm_va_block_region_t region = uvm_va_block_region(0, PAGES_PER_UVM_VA_BLOCK); + uvm_page_mask_t *read_fault_mask = &ats_context->read_fault_mask; + uvm_page_mask_t *write_fault_mask = &ats_context->write_fault_mask; + uvm_page_mask_t *faults_serviced_mask = &ats_context->faults_serviced_mask; + uvm_page_mask_t *reads_serviced_mask = &ats_context->reads_serviced_mask; + uvm_fault_client_type_t client_type = ats_context->client_type; + + UVM_ASSERT(vma); + UVM_ASSERT(IS_ALIGNED(base, UVM_VA_BLOCK_SIZE)); UVM_ASSERT(g_uvm_global.ats.enabled); + UVM_ASSERT(gpu_va_space); UVM_ASSERT(gpu_va_space->ats.enabled); UVM_ASSERT(uvm_gpu_va_space_state(gpu_va_space) == UVM_GPU_VA_SPACE_STATE_ACTIVE); - UVM_ASSERT(current_entry->fault_access_type == - uvm_fault_access_type_mask_highest(current_entry->access_type_mask)); + uvm_page_mask_zero(faults_serviced_mask); + uvm_page_mask_zero(reads_serviced_mask); - service_access_type = current_entry->fault_access_type; + if (!(vma->vm_flags & VM_READ)) + return status; - // ATS lookups are disabled on all addresses within the same - // UVM_GMMU_ATS_GRANULARITY as existing GMMU mappings (see documentation in - // uvm_mmu.h). User mode is supposed to reserve VAs as appropriate to - // prevent any system memory allocations from falling within the NO_ATS - // range of other GMMU mappings, so this shouldn't happen during normal - // operation. However, since this scenario may lead to infinite fault loops, - // we handle it by canceling the fault. - // - // TODO: Bug 2103669: Remove redundant VA range lookups - gmmu_region_base = UVM_ALIGN_DOWN(current_entry->fault_address, UVM_GMMU_ATS_GRANULARITY); - in_gmmu_region = !uvm_va_space_range_empty(current_entry->va_space, - gmmu_region_base, - gmmu_region_base + UVM_GMMU_ATS_GRANULARITY - 1); - if (in_gmmu_region) { - status = NV_ERR_INVALID_ADDRESS; + if (!(vma->vm_flags & VM_WRITE)) { + // If VMA doesn't have write permissions, all write faults are fatal. + // Try servicing such faults for read iff they are also present in + // read_fault_mask. This is because for replayable faults, if there are + // pending read accesses on the same page, we have to service them + // before we can cancel the write/atomic faults. So we try with read + // fault access type even though these write faults are fatal. + if (ats_context->client_type == UVM_FAULT_CLIENT_TYPE_GPC) + uvm_page_mask_and(write_fault_mask, write_fault_mask, read_fault_mask); + else + uvm_page_mask_zero(write_fault_mask); + + // There are no pending faults beyond write faults to RO region. + if (uvm_page_mask_empty(read_fault_mask)) + return status; } - else { - // TODO: Bug 2103669: Service more than a single fault at a time - status = uvm_ats_service_fault(gpu_va_space, - current_entry->fault_address, - service_access_type, - current_entry->fault_source.client_type); - } - - // Do not flag prefetch faults as fatal unless something fatal happened - if (status == NV_ERR_INVALID_ADDRESS) { - if (current_entry->fault_access_type != UVM_FAULT_ACCESS_TYPE_PREFETCH) { - current_entry->is_fatal = true; - current_entry->fatal_reason = uvm_tools_status_to_fatal_fault_reason(status); - - // Compute cancel mode for replayable faults - if (current_entry->is_replayable) { - if (service_access_type == UVM_FAULT_ACCESS_TYPE_READ || in_gmmu_region) - current_entry->replayable.cancel_va_mode = UVM_FAULT_CANCEL_VA_MODE_ALL; - else - current_entry->replayable.cancel_va_mode = UVM_FAULT_CANCEL_VA_MODE_WRITE_AND_ATOMIC; - - // If there are pending read accesses on the same page, we have to - // service them before we can cancel the write/atomic faults. So we - // retry with read fault access type. - if (!in_gmmu_region && - current_entry->fault_access_type > UVM_FAULT_ACCESS_TYPE_READ && - uvm_fault_access_type_mask_test(current_entry->access_type_mask, UVM_FAULT_ACCESS_TYPE_READ)) { - status = uvm_ats_service_fault(gpu_va_space, - current_entry->fault_address, - UVM_FAULT_ACCESS_TYPE_READ, - current_entry->fault_source.client_type); - - // If read accesses are also invalid, cancel the fault. If a - // different error code is returned, exit - if (status == NV_ERR_INVALID_ADDRESS) - current_entry->replayable.cancel_va_mode = UVM_FAULT_CANCEL_VA_MODE_ALL; - else if (status != NV_OK) - return status; - } - } + + ats_batch_select_residency(gpu_va_space, vma, ats_context); + + ats_fault_prefetch(gpu_va_space, vma, base, ats_context); + + for_each_va_block_subregion_in_mask(subregion, write_fault_mask, region) { + NvU64 start = base + (subregion.first * PAGE_SIZE); + size_t length = uvm_va_block_region_num_pages(subregion) * PAGE_SIZE; + uvm_fault_access_type_t access_type = (vma->vm_flags & VM_WRITE) ? + UVM_FAULT_ACCESS_TYPE_WRITE : + UVM_FAULT_ACCESS_TYPE_READ; + + UVM_ASSERT(start >= vma->vm_start); + UVM_ASSERT((start + length) <= vma->vm_end); + + status = service_ats_faults(gpu_va_space, vma, start, length, access_type, ats_context); + if (status != NV_OK) + return status; + + if (vma->vm_flags & VM_WRITE) { + uvm_page_mask_region_fill(faults_serviced_mask, subregion); + uvm_ats_smmu_invalidate_tlbs(gpu_va_space, start, length); + + // The Linux kernel never invalidates TLB entries on mapping + // permission upgrade. This is a problem if the GPU has cached + // entries with the old permission. The GPU will re-fetch the entry + // if the PTE is invalid and page size is not 4K (this is the case + // on P9). However, if a page gets upgraded from R/O to R/W and GPU + // has the PTEs cached with R/O permissions we will enter an + // infinite loop because we just forward the fault to the Linux + // kernel and it will see that the permissions in the page table are + // correct. Therefore, we flush TLB entries on ATS write faults. + flush_tlb_va_region(gpu_va_space, start, length, client_type); } else { - current_entry->is_invalid_prefetch = true; + uvm_page_mask_region_fill(reads_serviced_mask, subregion); } - - // Do not fail overall fault servicing due to logical errors - status = NV_OK; } - // The Linux kernel never invalidates TLB entries on mapping permission - // upgrade. This is a problem if the GPU has cached entries with the old - // permission. The GPU will re-fetch the entry if the PTE is invalid and - // page size is not 4K (this is the case on P9). However, if a page gets - // upgraded from R/O to R/W and GPU has the PTEs cached with R/O - // permissions we will enter an infinite loop because we just forward the - // fault to the Linux kernel and it will see that the permissions in the - // page table are correct. Therefore, we flush TLB entries on ATS write - // faults. - if (!current_entry->is_fatal && current_entry->fault_access_type > UVM_FAULT_ACCESS_TYPE_READ) { - if (!ats_invalidate->write_faults_in_batch) { - uvm_tlb_batch_begin(&gpu_va_space->page_tables, &ats_invalidate->write_faults_tlb_batch); - ats_invalidate->write_faults_in_batch = true; - } + // Remove write faults from read_fault_mask + uvm_page_mask_andnot(read_fault_mask, read_fault_mask, write_fault_mask); + + for_each_va_block_subregion_in_mask(subregion, read_fault_mask, region) { + NvU64 start = base + (subregion.first * PAGE_SIZE); + size_t length = uvm_va_block_region_num_pages(subregion) * PAGE_SIZE; + uvm_fault_access_type_t access_type = UVM_FAULT_ACCESS_TYPE_READ; + + UVM_ASSERT(start >= vma->vm_start); + UVM_ASSERT((start + length) <= vma->vm_end); + + status = service_ats_faults(gpu_va_space, vma, start, length, access_type, ats_context); + if (status != NV_OK) + return status; + + uvm_page_mask_region_fill(faults_serviced_mask, subregion); + + // Similarly to permission upgrade scenario, discussed above, GPU + // will not re-fetch the entry if the PTE is invalid and page size + // is 4K. To avoid infinite faulting loop, invalidate TLB for every + // new translation written explicitly like in the case of permission + // upgrade. + if (PAGE_SIZE == UVM_PAGE_SIZE_4K) + flush_tlb_va_region(gpu_va_space, start, length, client_type); - uvm_tlb_batch_invalidate(&ats_invalidate->write_faults_tlb_batch, - current_entry->fault_address, - PAGE_SIZE, - PAGE_SIZE, - UVM_MEMBAR_NONE); } return status; } +bool uvm_ats_check_in_gmmu_region(uvm_va_space_t *va_space, NvU64 address, uvm_va_range_t *next) +{ + uvm_va_range_t *prev; + NvU64 gmmu_region_base = UVM_ALIGN_DOWN(address, UVM_GMMU_ATS_GRANULARITY); + + UVM_ASSERT(va_space); + + if (next) { + if (next->node.start <= gmmu_region_base + UVM_GMMU_ATS_GRANULARITY - 1) + return true; + + prev = uvm_va_range_container(uvm_range_tree_prev(&va_space->va_range_tree, &next->node)); + } + else { + // No VA range exists after address, so check the last VA range in the + // tree. + prev = uvm_va_range_container(uvm_range_tree_last(&va_space->va_range_tree)); + } + + return prev && (prev->node.end >= gmmu_region_base); +} + NV_STATUS uvm_ats_invalidate_tlbs(uvm_gpu_va_space_t *gpu_va_space, uvm_ats_fault_invalidate_t *ats_invalidate, uvm_tracker_t *out_tracker) @@ -263,7 +574,7 @@ NV_STATUS status; uvm_push_t push; - if (!ats_invalidate->write_faults_in_batch) + if (!ats_invalidate->tlb_batch_pending) return NV_OK; UVM_ASSERT(gpu_va_space); @@ -275,7 +586,7 @@ "Invalidate ATS entries"); if (status == NV_OK) { - uvm_tlb_batch_end(&ats_invalidate->write_faults_tlb_batch, &push, UVM_MEMBAR_NONE); + uvm_tlb_batch_end(&ats_invalidate->tlb_batch, &push, UVM_MEMBAR_NONE); uvm_push_end(&push); // Add this push to the GPU's tracker so that fault replays/clears can @@ -283,7 +594,7 @@ status = uvm_tracker_add_push_safe(out_tracker, &push); } - ats_invalidate->write_faults_in_batch = false; + ats_invalidate->tlb_batch_pending = false; return status; } diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/kernel-open/nvidia-uvm/uvm_ats_faults.h nvidia-open-gpu-kernel-modules-535.161.08/kernel-open/nvidia-uvm/uvm_ats_faults.h --- nvidia-open-gpu-kernel-modules-525.147.05/kernel-open/nvidia-uvm/uvm_ats_faults.h 2023-10-25 20:33:42.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/kernel-open/nvidia-uvm/uvm_ats_faults.h 2024-03-05 22:26:05.000000000 +0000 @@ -25,13 +25,34 @@ #include "uvm_lock.h" #include "uvm_global.h" #include "uvm_va_space.h" +#include "uvm_gpu.h" -NV_STATUS uvm_ats_service_fault_entry(uvm_gpu_va_space_t *gpu_va_space, - uvm_fault_buffer_entry_t *current_entry, - uvm_ats_fault_invalidate_t *ats_invalidate); +// Service ATS faults in the range (base, base + UVM_VA_BLOCK_SIZE) with service +// type for individual pages in the range requested by page masks set in +// ats_context->read_fault_mask/write_fault_mask. base must be aligned to +// UVM_VA_BLOCK_SIZE. The caller is responsible for ensuring that faulting +// addresses fall completely within the VMA. The caller is also responsible for +// ensuring that the faulting addresses don't overlap a GMMU region. (See +// uvm_ats_check_in_gmmu_region). The caller is also responsible for handling +// any errors returned by this function (fault cancellations etc.). +// +// Returns the fault service status in ats_context->faults_serviced_mask. In +// addition, ats_context->reads_serviced_mask returns whether read servicing +// worked on write faults iff the read service was also requested in the +// corresponding bit in read_fault_mask. These returned masks are only valid if +// the return status is NV_OK. Status other than NV_OK indicate system global +// fault servicing failures. +NV_STATUS uvm_ats_service_faults(uvm_gpu_va_space_t *gpu_va_space, + struct vm_area_struct *vma, + NvU64 base, + uvm_ats_fault_context_t *ats_context); + +// Return whether there are any VA ranges (and thus GMMU mappings) within the +// UVM_GMMU_ATS_GRANULARITY-aligned region containing address. +bool uvm_ats_check_in_gmmu_region(uvm_va_space_t *va_space, NvU64 address, uvm_va_range_t *next); // This function performs pending TLB invalidations for ATS and clears the -// ats_invalidate->write_faults_in_batch flag +// ats_invalidate->tlb_batch_pending flag NV_STATUS uvm_ats_invalidate_tlbs(uvm_gpu_va_space_t *gpu_va_space, uvm_ats_fault_invalidate_t *ats_invalidate, uvm_tracker_t *out_tracker); diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/kernel-open/nvidia-uvm/uvm_ats_sva.c nvidia-open-gpu-kernel-modules-535.161.08/kernel-open/nvidia-uvm/uvm_ats_sva.c --- nvidia-open-gpu-kernel-modules-525.147.05/kernel-open/nvidia-uvm/uvm_ats_sva.c 1970-01-01 00:00:00.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/kernel-open/nvidia-uvm/uvm_ats_sva.c 2024-03-05 22:25:40.000000000 +0000 @@ -0,0 +1,420 @@ +/******************************************************************************* + Copyright (c) 2018-2023 NVIDIA Corporation + + Permission is hereby granted, free of charge, to any person obtaining a copy + of this software and associated documentation files (the "Software"), to + deal in the Software without restriction, including without limitation the + rights to use, copy, modify, merge, publish, distribute, sublicense, and/or + sell copies of the Software, and to permit persons to whom the Software is + furnished to do so, subject to the following conditions: + + The above copyright notice and this permission notice shall be + included in all copies or substantial portions of the Software. + + THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + DEALINGS IN THE SOFTWARE. + +*******************************************************************************/ + +#include "uvm_ats_sva.h" + +#if UVM_ATS_SVA_SUPPORTED() + +#include "uvm_gpu.h" +#include "uvm_va_space.h" +#include "uvm_va_space_mm.h" + +#include +#include +#include +#include +#include +#include +#include + +// linux/sched/mm.h is needed for mmget_not_zero and mmput to get the mm +// reference required for the iommu_sva_bind_device() call. This header is not +// present in all the supported versions. Instead of adding a conftest just for +// this header file, use UVM_ATS_SVA_SUPPORTED(). +#include + +// iommu_sva_bind_device() removed drvdata paramter with commit +// 942fd5435dccb273f90176b046ae6bbba60cfbd8 (10/31/2022). +#if defined(NV_IOMMU_SVA_BIND_DEVICE_HAS_DRVDATA_ARG) +#define UVM_IOMMU_SVA_BIND_DEVICE(dev, mm) iommu_sva_bind_device(dev, mm, NULL) +#else +#define UVM_IOMMU_SVA_BIND_DEVICE(dev, mm) iommu_sva_bind_device(dev, mm) +#endif + +// Type to represent a 128-bit SMMU command queue command. +struct smmu_cmd { + NvU64 low; + NvU64 high; +}; + +// Base address of SMMU CMDQ-V for GSMMU0. +#define SMMU_CMDQV_BASE_ADDR(smmu_base) (smmu_base + 0x200000) +#define SMMU_CMDQV_BASE_LEN 0x00830000 + +// CMDQV configuration is done by firmware but we check status here. +#define SMMU_CMDQV_CONFIG 0x0 +#define SMMU_CMDQV_CONFIG_CMDQV_EN BIT(0) + +// Used to map a particular VCMDQ to a VINTF. +#define SMMU_CMDQV_CMDQ_ALLOC_MAP(vcmdq_id) (0x200 + 0x4 * (vcmdq_id)) +#define SMMU_CMDQV_CMDQ_ALLOC_MAP_ALLOC BIT(0) + +// Shift for the field containing the index of the virtual interface +// owning the VCMDQ. +#define SMMU_CMDQV_CMDQ_ALLOC_MAP_VIRT_INTF_INDX_SHIFT 15 + +// Base address for the VINTF registers. +#define SMMU_VINTF_BASE_ADDR(cmdqv_base_addr, vintf_id) (cmdqv_base_addr + 0x1000 + 0x100 * (vintf_id)) + +// Virtual interface (VINTF) configuration registers. The WAR only +// works on baremetal so we need to configure ourselves as the +// hypervisor owner. +#define SMMU_VINTF_CONFIG 0x0 +#define SMMU_VINTF_CONFIG_ENABLE BIT(0) +#define SMMU_VINTF_CONFIG_HYP_OWN BIT(17) + +#define SMMU_VINTF_STATUS 0x0 +#define SMMU_VINTF_STATUS_ENABLED BIT(0) + +// Caclulates the base address for a particular VCMDQ instance. +#define SMMU_VCMDQ_BASE_ADDR(cmdqv_base_addr, vcmdq_id) (cmdqv_base_addr + 0x10000 + 0x80 * (vcmdq_id)) + +// SMMU command queue consumer index register. Updated by SMMU +// when commands are consumed. +#define SMMU_VCMDQ_CONS 0x0 + +// SMMU command queue producer index register. Updated by UVM when +// commands are added to the queue. +#define SMMU_VCMDQ_PROD 0x4 + +// Configuration register used to enable a VCMDQ. +#define SMMU_VCMDQ_CONFIG 0x8 +#define SMMU_VCMDQ_CONFIG_ENABLE BIT(0) + +// Status register used to check the VCMDQ is enabled. +#define SMMU_VCMDQ_STATUS 0xc +#define SMMU_VCMDQ_STATUS_ENABLED BIT(0) + +// Base address offset for the VCMDQ registers. +#define SMMU_VCMDQ_CMDQ_BASE 0x10000 + +// Size of the command queue. Each command is 16 bytes and we can't +// have a command queue greater than one page in size. +#define SMMU_VCMDQ_CMDQ_BASE_LOG2SIZE (PAGE_SHIFT - ilog2(sizeof(struct smmu_cmd))) +#define SMMU_VCMDQ_CMDQ_ENTRIES (1UL << SMMU_VCMDQ_CMDQ_BASE_LOG2SIZE) + +// We always use VINTF63 for the WAR +#define VINTF 63 +static void smmu_vintf_write32(void __iomem *smmu_cmdqv_base, int reg, NvU32 val) +{ + iowrite32(val, SMMU_VINTF_BASE_ADDR(smmu_cmdqv_base, VINTF) + reg); +} + +static NvU32 smmu_vintf_read32(void __iomem *smmu_cmdqv_base, int reg) +{ + return ioread32(SMMU_VINTF_BASE_ADDR(smmu_cmdqv_base, VINTF) + reg); +} + +// We always use VCMDQ127 for the WAR +#define VCMDQ 127 +void smmu_vcmdq_write32(void __iomem *smmu_cmdqv_base, int reg, NvU32 val) +{ + iowrite32(val, SMMU_VCMDQ_BASE_ADDR(smmu_cmdqv_base, VCMDQ) + reg); +} + +NvU32 smmu_vcmdq_read32(void __iomem *smmu_cmdqv_base, int reg) +{ + return ioread32(SMMU_VCMDQ_BASE_ADDR(smmu_cmdqv_base, VCMDQ) + reg); +} + +static void smmu_vcmdq_write64(void __iomem *smmu_cmdqv_base, int reg, NvU64 val) +{ + iowrite64(val, SMMU_VCMDQ_BASE_ADDR(smmu_cmdqv_base, VCMDQ) + reg); +} + +// Fix for Bug 4130089: [GH180][r535] WAR for kernel not issuing SMMU +// TLB invalidates on read-only to read-write upgrades +static NV_STATUS uvm_ats_smmu_war_init(uvm_parent_gpu_t *parent_gpu) +{ + uvm_spin_loop_t spin; + NV_STATUS status; + unsigned long cmdqv_config; + void __iomem *smmu_cmdqv_base; + struct acpi_iort_node *node; + struct acpi_iort_smmu_v3 *iort_smmu; + + node = *(struct acpi_iort_node **) dev_get_platdata(parent_gpu->pci_dev->dev.iommu->iommu_dev->dev->parent); + iort_smmu = (struct acpi_iort_smmu_v3 *) node->node_data; + + smmu_cmdqv_base = ioremap(SMMU_CMDQV_BASE_ADDR(iort_smmu->base_address), SMMU_CMDQV_BASE_LEN); + if (!smmu_cmdqv_base) + return NV_ERR_NO_MEMORY; + + parent_gpu->smmu_war.smmu_cmdqv_base = smmu_cmdqv_base; + cmdqv_config = ioread32(smmu_cmdqv_base + SMMU_CMDQV_CONFIG); + if (!(cmdqv_config & SMMU_CMDQV_CONFIG_CMDQV_EN)) { + status = NV_ERR_OBJECT_NOT_FOUND; + goto out; + } + + // Allocate SMMU CMDQ pages for WAR + parent_gpu->smmu_war.smmu_cmdq = alloc_page(NV_UVM_GFP_FLAGS | __GFP_ZERO); + if (!parent_gpu->smmu_war.smmu_cmdq) { + status = NV_ERR_NO_MEMORY; + goto out; + } + + // Initialise VINTF for the WAR + smmu_vintf_write32(smmu_cmdqv_base, SMMU_VINTF_CONFIG, SMMU_VINTF_CONFIG_ENABLE | SMMU_VINTF_CONFIG_HYP_OWN); + UVM_SPIN_WHILE(!(smmu_vintf_read32(smmu_cmdqv_base, SMMU_VINTF_STATUS) & SMMU_VINTF_STATUS_ENABLED), &spin); + + // Allocate VCMDQ to VINTF + iowrite32((VINTF << SMMU_CMDQV_CMDQ_ALLOC_MAP_VIRT_INTF_INDX_SHIFT) | SMMU_CMDQV_CMDQ_ALLOC_MAP_ALLOC, + smmu_cmdqv_base + SMMU_CMDQV_CMDQ_ALLOC_MAP(VCMDQ)); + + smmu_vcmdq_write64(smmu_cmdqv_base, SMMU_VCMDQ_CMDQ_BASE, + page_to_phys(parent_gpu->smmu_war.smmu_cmdq) | SMMU_VCMDQ_CMDQ_BASE_LOG2SIZE); + smmu_vcmdq_write32(smmu_cmdqv_base, SMMU_VCMDQ_CONS, 0); + smmu_vcmdq_write32(smmu_cmdqv_base, SMMU_VCMDQ_PROD, 0); + smmu_vcmdq_write32(smmu_cmdqv_base, SMMU_VCMDQ_CONFIG, SMMU_VCMDQ_CONFIG_ENABLE); + UVM_SPIN_WHILE(!(smmu_vcmdq_read32(smmu_cmdqv_base, SMMU_VCMDQ_STATUS) & SMMU_VCMDQ_STATUS_ENABLED), &spin); + + uvm_mutex_init(&parent_gpu->smmu_war.smmu_lock, UVM_LOCK_ORDER_LEAF); + parent_gpu->smmu_war.smmu_prod = 0; + parent_gpu->smmu_war.smmu_cons = 0; + + return NV_OK; + +out: + iounmap(parent_gpu->smmu_war.smmu_cmdqv_base); + parent_gpu->smmu_war.smmu_cmdqv_base = NULL; + + return status; +} + +static void uvm_ats_smmu_war_deinit(uvm_parent_gpu_t *parent_gpu) +{ + void __iomem *smmu_cmdqv_base = parent_gpu->smmu_war.smmu_cmdqv_base; + NvU32 cmdq_alloc_map; + + if (parent_gpu->smmu_war.smmu_cmdqv_base) { + smmu_vcmdq_write32(smmu_cmdqv_base, SMMU_VCMDQ_CONFIG, 0); + cmdq_alloc_map = ioread32(smmu_cmdqv_base + SMMU_CMDQV_CMDQ_ALLOC_MAP(VCMDQ)); + iowrite32(cmdq_alloc_map & SMMU_CMDQV_CMDQ_ALLOC_MAP_ALLOC, smmu_cmdqv_base + SMMU_CMDQV_CMDQ_ALLOC_MAP(VCMDQ)); + smmu_vintf_write32(smmu_cmdqv_base, SMMU_VINTF_CONFIG, 0); + } + + if (parent_gpu->smmu_war.smmu_cmdq) + __free_page(parent_gpu->smmu_war.smmu_cmdq); + + if (parent_gpu->smmu_war.smmu_cmdqv_base) + iounmap(parent_gpu->smmu_war.smmu_cmdqv_base); +} + +// The SMMU on ARM64 can run under different translation regimes depending on +// what features the OS and CPU variant support. The CPU for GH180 supports +// virtualisation extensions and starts the kernel at EL2 meaning SMMU operates +// under the NS-EL2-E2H translation regime. Therefore we need to use the +// TLBI_EL2_* commands which invalidate TLB entries created under this +// translation regime. +#define CMDQ_OP_TLBI_EL2_ASID 0x21; +#define CMDQ_OP_TLBI_EL2_VA 0x22; +#define CMDQ_OP_CMD_SYNC 0x46 + +// Use the same maximum as used for MAX_TLBI_OPS in the upstream +// kernel. +#define UVM_MAX_TLBI_OPS (1UL << (PAGE_SHIFT - 3)) + +#if UVM_ATS_SMMU_WAR_REQUIRED() +void uvm_ats_smmu_invalidate_tlbs(uvm_gpu_va_space_t *gpu_va_space, NvU64 addr, size_t size) +{ + struct mm_struct *mm = gpu_va_space->va_space->va_space_mm.mm; + uvm_parent_gpu_t *parent_gpu = gpu_va_space->gpu->parent; + struct { + NvU64 low; + NvU64 high; + } *vcmdq; + unsigned long vcmdq_prod; + NvU64 end; + uvm_spin_loop_t spin; + NvU16 asid; + + if (!parent_gpu->smmu_war.smmu_cmdqv_base) + return; + + asid = arm64_mm_context_get(mm); + vcmdq = kmap(parent_gpu->smmu_war.smmu_cmdq); + uvm_mutex_lock(&parent_gpu->smmu_war.smmu_lock); + vcmdq_prod = parent_gpu->smmu_war.smmu_prod; + + // Our queue management is very simple. The mutex prevents multiple + // producers writing to the queue and all our commands require waiting for + // the queue to drain so we know it's empty. If we can't fit enough commands + // in the queue we just invalidate the whole ASID. + // + // The command queue is a cirular buffer with the MSB representing a wrap + // bit that must toggle on each wrap. See the SMMU architecture + // specification for more details. + // + // SMMU_VCMDQ_CMDQ_ENTRIES - 1 because we need to leave space for the + // CMD_SYNC. + if ((size >> PAGE_SHIFT) > min(UVM_MAX_TLBI_OPS, SMMU_VCMDQ_CMDQ_ENTRIES - 1)) { + vcmdq[vcmdq_prod % SMMU_VCMDQ_CMDQ_ENTRIES].low = CMDQ_OP_TLBI_EL2_ASID; + vcmdq[vcmdq_prod % SMMU_VCMDQ_CMDQ_ENTRIES].low |= (NvU64) asid << 48; + vcmdq[vcmdq_prod % SMMU_VCMDQ_CMDQ_ENTRIES].high = 0; + vcmdq_prod++; + } + else { + for (end = addr + size; addr < end; addr += PAGE_SIZE) { + vcmdq[vcmdq_prod % SMMU_VCMDQ_CMDQ_ENTRIES].low = CMDQ_OP_TLBI_EL2_VA; + vcmdq[vcmdq_prod % SMMU_VCMDQ_CMDQ_ENTRIES].low |= (NvU64) asid << 48; + vcmdq[vcmdq_prod % SMMU_VCMDQ_CMDQ_ENTRIES].high = addr & ~((1UL << 12) - 1); + vcmdq_prod++; + } + } + + vcmdq[vcmdq_prod % SMMU_VCMDQ_CMDQ_ENTRIES].low = CMDQ_OP_CMD_SYNC; + vcmdq[vcmdq_prod % SMMU_VCMDQ_CMDQ_ENTRIES].high = 0x0; + vcmdq_prod++; + + // MSB is the wrap bit + vcmdq_prod &= (1UL << (SMMU_VCMDQ_CMDQ_BASE_LOG2SIZE + 1)) - 1; + parent_gpu->smmu_war.smmu_prod = vcmdq_prod; + smmu_vcmdq_write32(parent_gpu->smmu_war.smmu_cmdqv_base, SMMU_VCMDQ_PROD, parent_gpu->smmu_war.smmu_prod); + + UVM_SPIN_WHILE( + (smmu_vcmdq_read32(parent_gpu->smmu_war.smmu_cmdqv_base, SMMU_VCMDQ_CONS) & GENMASK(19, 0)) != vcmdq_prod, + &spin); + + uvm_mutex_unlock(&parent_gpu->smmu_war.smmu_lock); + kunmap(parent_gpu->smmu_war.smmu_cmdq); + arm64_mm_context_put(mm); +} +#endif + +NV_STATUS uvm_ats_sva_add_gpu(uvm_parent_gpu_t *parent_gpu) +{ + int ret; + + ret = iommu_dev_enable_feature(&parent_gpu->pci_dev->dev, IOMMU_DEV_FEAT_SVA); + if (ret) + return errno_to_nv_status(ret); + + if (UVM_ATS_SMMU_WAR_REQUIRED()) + return uvm_ats_smmu_war_init(parent_gpu); + else + return NV_OK; +} + +void uvm_ats_sva_remove_gpu(uvm_parent_gpu_t *parent_gpu) +{ + if (UVM_ATS_SMMU_WAR_REQUIRED()) + uvm_ats_smmu_war_deinit(parent_gpu); + + iommu_dev_disable_feature(&parent_gpu->pci_dev->dev, IOMMU_DEV_FEAT_SVA); +} + +NV_STATUS uvm_ats_sva_bind_gpu(uvm_gpu_va_space_t *gpu_va_space) +{ + NV_STATUS status = NV_OK; + struct iommu_sva *iommu_handle; + struct pci_dev *pci_dev = gpu_va_space->gpu->parent->pci_dev; + uvm_sva_gpu_va_space_t *sva_gpu_va_space = &gpu_va_space->ats.sva; + struct mm_struct *mm = gpu_va_space->va_space->va_space_mm.mm; + + UVM_ASSERT(gpu_va_space->ats.enabled); + UVM_ASSERT(uvm_gpu_va_space_state(gpu_va_space) == UVM_GPU_VA_SPACE_STATE_INIT); + UVM_ASSERT(mm); + + // The mmput() below may trigger the kernel's mm teardown with exit_mmap() + // and uvm_va_space_mm_shutdown() and uvm_vm_close_managed() in that path + // will try to grab the va_space lock and deadlock if va_space was already + // locked. + uvm_assert_unlocked_order(UVM_LOCK_ORDER_VA_SPACE); + + // iommu_sva_bind_device() requires the mm reference to be acquired. Since + // the mm is already retained, mm is still valid but may be inactive since + // mm_users can still be zero since UVM doesn't use mm_users and maintains a + // separate refcount (retained_count) for the mm in va_space_mm. See the + // block comment in va_space_mm.c for more details. So, return an error if + // mm_users is zero. + if (!mmget_not_zero(mm)) + return NV_ERR_PAGE_TABLE_NOT_AVAIL; + + // Multiple calls for the {same pci_dev, mm} pair are refcounted by the ARM + // SMMU Layer. + iommu_handle = UVM_IOMMU_SVA_BIND_DEVICE(&pci_dev->dev, mm); + if (IS_ERR(iommu_handle)) { + status = errno_to_nv_status(PTR_ERR(iommu_handle)); + goto out; + } + + // If this is not the first bind of the gpu in the mm, then the previously + // stored iommu_handle in the gpu_va_space must match the handle returned by + // iommu_sva_bind_device(). + if (sva_gpu_va_space->iommu_handle) { + UVM_ASSERT(sva_gpu_va_space->iommu_handle == iommu_handle); + nv_kref_get(&sva_gpu_va_space->kref); + } + else { + sva_gpu_va_space->iommu_handle = iommu_handle; + nv_kref_init(&sva_gpu_va_space->kref); + } + +out: + mmput(mm); + return status; +} + +static void uvm_sva_reset_iommu_handle(nv_kref_t *nv_kref) +{ + uvm_sva_gpu_va_space_t *sva_gpu_va_space = container_of(nv_kref, uvm_sva_gpu_va_space_t, kref); + sva_gpu_va_space->iommu_handle = NULL; +} + +void uvm_ats_sva_unbind_gpu(uvm_gpu_va_space_t *gpu_va_space) +{ + uvm_sva_gpu_va_space_t *sva_gpu_va_space = &gpu_va_space->ats.sva; + + // ARM SMMU layer decrements the refcount for the {pci_dev, mm} pair. + // The actual unbind happens only when the refcount reaches zero. + if (sva_gpu_va_space->iommu_handle) { + iommu_sva_unbind_device(sva_gpu_va_space->iommu_handle); + nv_kref_put(&sva_gpu_va_space->kref, uvm_sva_reset_iommu_handle); + } +} + +NV_STATUS uvm_ats_sva_register_gpu_va_space(uvm_gpu_va_space_t *gpu_va_space) +{ + NvU32 pasid; + NV_STATUS status = NV_OK; + uvm_sva_gpu_va_space_t *sva_gpu_va_space = &gpu_va_space->ats.sva; + + // A successful iommu_sva_bind_device() should have preceded this call. + UVM_ASSERT(sva_gpu_va_space->iommu_handle); + + pasid = iommu_sva_get_pasid(sva_gpu_va_space->iommu_handle); + if (pasid == IOMMU_PASID_INVALID) + status = errno_to_nv_status(ENODEV); + else + gpu_va_space->ats.pasid = pasid; + + return status; +} + +void uvm_ats_sva_unregister_gpu_va_space(uvm_gpu_va_space_t *gpu_va_space) +{ + gpu_va_space->ats.pasid = -1U; +} + +#endif // UVM_ATS_SVA_SUPPORTED() diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/kernel-open/nvidia-uvm/uvm_ats_sva.h nvidia-open-gpu-kernel-modules-535.161.08/kernel-open/nvidia-uvm/uvm_ats_sva.h --- nvidia-open-gpu-kernel-modules-525.147.05/kernel-open/nvidia-uvm/uvm_ats_sva.h 1970-01-01 00:00:00.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/kernel-open/nvidia-uvm/uvm_ats_sva.h 2024-03-05 22:25:40.000000000 +0000 @@ -0,0 +1,143 @@ +/******************************************************************************* + Copyright (c) 2018-2023 NVIDIA Corporation + + Permission is hereby granted, free of charge, to any person obtaining a copy + of this software and associated documentation files (the "Software"), to + deal in the Software without restriction, including without limitation the + rights to use, copy, modify, merge, publish, distribute, sublicense, and/or + sell copies of the Software, and to permit persons to whom the Software is + furnished to do so, subject to the following conditions: + + The above copyright notice and this permission notice shall be + included in all copies or substantial portions of the Software. + + THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + DEALINGS IN THE SOFTWARE. + +*******************************************************************************/ + +#ifndef __UVM_ATS_SVA_H__ +#define __UVM_ATS_SVA_H__ + +#include "uvm_gpu.h" +#include "uvm_forward_decl.h" + +#include + +// For ATS support on aarch64, arm_smmu_sva_bind() is needed for +// iommu_sva_bind_device() calls. Unfortunately, arm_smmu_sva_bind() is not +// conftest-able. We instead look for the presence of ioasid_get() or +// mm_pasid_drop(). ioasid_get() was added in the same patch series as +// arm_smmu_sva_bind() and removed in v6.0. mm_pasid_drop() was added in the +// same patch as the removal of ioasid_get(). We assume the presence of +// arm_smmu_sva_bind() if ioasid_get(v5.11 - v5.17) or mm_pasid_drop(v5.18+) is +// present. +// +// arm_smmu_sva_bind() was added with commit +// 32784a9562fb0518b12e9797ee2aec52214adf6f and ioasid_get() was added with +// commit cb4789b0d19ff231ce9f73376a023341300aed96 (11/23/2020). Commit +// 701fac40384f07197b106136012804c3cae0b3de (02/15/2022) removed ioasid_get() +// and added mm_pasid_drop(). + #if UVM_CAN_USE_MMU_NOTIFIERS() && (defined(NV_IOASID_GET_PRESENT) || defined(NV_MM_PASID_DROP_PRESENT)) + #if defined(CONFIG_IOMMU_SVA) + #define UVM_ATS_SVA_SUPPORTED() 1 + #else + #define UVM_ATS_SVA_SUPPORTED() 0 + #endif + #else + #define UVM_ATS_SVA_SUPPORTED() 0 + #endif + +// If NV_ARCH_INVALIDATE_SECONDARY_TLBS is defined it means the upstream fix is +// in place so no need for the WAR from Bug 4130089: [GH180][r535] WAR for +// kernel not issuing SMMU TLB invalidates on read-only +#if defined(NV_ARCH_INVALIDATE_SECONDARY_TLBS) + #define UVM_ATS_SMMU_WAR_REQUIRED() 0 +#elif NVCPU_IS_AARCH64 + #define UVM_ATS_SMMU_WAR_REQUIRED() 1 +#else + #define UVM_ATS_SMMU_WAR_REQUIRED() 0 +#endif + +typedef struct +{ + int placeholder; +} uvm_sva_va_space_t; + +typedef struct +{ + // Reference count for the iommu_handle + nv_kref_t kref; + struct iommu_sva *iommu_handle; +} uvm_sva_gpu_va_space_t; + +#if UVM_ATS_SVA_SUPPORTED() + NV_STATUS uvm_ats_sva_add_gpu(uvm_parent_gpu_t *parent_gpu); + void uvm_ats_sva_remove_gpu(uvm_parent_gpu_t *parent_gpu); + + // LOCKING: mmap_lock must be lockable + // VA space lock must not be held. + NV_STATUS uvm_ats_sva_bind_gpu(uvm_gpu_va_space_t *gpu_va_space); + + // LOCKING: VA space lock must not be held. + void uvm_ats_sva_unbind_gpu(uvm_gpu_va_space_t *gpu_va_space); + + // LOCKING: None + NV_STATUS uvm_ats_sva_register_gpu_va_space(uvm_gpu_va_space_t *gpu_va_space); + + // LOCKING: None + void uvm_ats_sva_unregister_gpu_va_space(uvm_gpu_va_space_t *gpu_va_space); + + // Fix for Bug 4130089: [GH180][r535] WAR for kernel not issuing SMMU + // TLB invalidates on read-only to read-write upgrades + #if UVM_ATS_SMMU_WAR_REQUIRED() + void uvm_ats_smmu_invalidate_tlbs(uvm_gpu_va_space_t *gpu_va_space, NvU64 addr, size_t size); + #else + static void uvm_ats_smmu_invalidate_tlbs(uvm_gpu_va_space_t *gpu_va_space, NvU64 addr, size_t size) + { + + } + #endif +#else + static NV_STATUS uvm_ats_sva_add_gpu(uvm_parent_gpu_t *parent_gpu) + { + return NV_OK; + } + + static void uvm_ats_sva_remove_gpu(uvm_parent_gpu_t *parent_gpu) + { + + } + + static NV_STATUS uvm_ats_sva_bind_gpu(uvm_gpu_va_space_t *gpu_va_space) + { + return NV_OK; + } + + static void uvm_ats_sva_unbind_gpu(uvm_gpu_va_space_t *gpu_va_space) + { + + } + + static NV_STATUS uvm_ats_sva_register_gpu_va_space(uvm_gpu_va_space_t *gpu_va_space) + { + return NV_OK; + } + + static void uvm_ats_sva_unregister_gpu_va_space(uvm_gpu_va_space_t *gpu_va_space) + { + + } + + static void uvm_ats_smmu_invalidate_tlbs(uvm_gpu_va_space_t *gpu_va_space, NvU64 addr, size_t size) + { + + } +#endif // UVM_ATS_SVA_SUPPORTED + +#endif // __UVM_ATS_SVA_H__ diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/kernel-open/nvidia-uvm/uvm_ce_test.c nvidia-open-gpu-kernel-modules-535.161.08/kernel-open/nvidia-uvm/uvm_ce_test.c --- nvidia-open-gpu-kernel-modules-525.147.05/kernel-open/nvidia-uvm/uvm_ce_test.c 2023-10-25 20:33:43.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/kernel-open/nvidia-uvm/uvm_ce_test.c 2024-03-05 22:26:06.000000000 +0000 @@ -1,5 +1,5 @@ /******************************************************************************* - Copyright (c) 2015-2022 NVIDIA Corporation + Copyright (c) 2015-2023 NVIDIA Corporation Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation files (the "Software"), to @@ -24,12 +24,14 @@ #include "uvm_channel.h" #include "uvm_global.h" #include "uvm_hal.h" +#include "uvm_kvmalloc.h" #include "uvm_push.h" #include "uvm_test.h" #include "uvm_tracker.h" #include "uvm_va_space.h" #include "uvm_rm_mem.h" #include "uvm_mem.h" +#include "uvm_gpu.h" #define CE_TEST_MEM_SIZE (2 * 1024 * 1024) #define CE_TEST_MEM_END_SIZE 32 @@ -52,6 +54,11 @@ uvm_push_t push; bool is_proxy; + // TODO: Bug 3839176: the test is waived on Confidential Computing because + // it assumes that GPU can access system memory without using encryption. + if (uvm_conf_computing_mode_enabled(gpu)) + return NV_OK; + status = uvm_rm_mem_alloc_and_map_cpu(gpu, UVM_RM_MEM_TYPE_SYS, CE_TEST_MEM_SIZE, 0, &host_mem); TEST_CHECK_GOTO(status == NV_OK, done); host_ptr = (NvU32 *)uvm_rm_mem_get_cpu_va(host_mem); @@ -66,7 +73,7 @@ TEST_CHECK_GOTO(status == NV_OK, done); is_proxy = uvm_channel_is_proxy(push.channel); - host_mem_gpu_va = uvm_rm_mem_get_gpu_va(host_mem, gpu, is_proxy); + host_mem_gpu_va = uvm_rm_mem_get_gpu_va(host_mem, gpu, is_proxy).address; // All of the following CE transfers are done from a single (L)CE and // disabling pipelining is enough to order them when needed. Only push_end @@ -74,7 +81,7 @@ // Initialize to a bad value for (i = 0; i < CE_TEST_MEM_COUNT; ++i) { - mem_gpu_va = uvm_rm_mem_get_gpu_va(mem[i], gpu, is_proxy); + mem_gpu_va = uvm_rm_mem_get_gpu_va(mem[i], gpu, is_proxy).address; uvm_push_set_flag(&push, UVM_PUSH_FLAG_CE_NEXT_PIPELINED); uvm_push_set_flag(&push, UVM_PUSH_FLAG_NEXT_MEMBAR_NONE); @@ -83,7 +90,7 @@ // Set the first buffer to 1 uvm_push_set_flag(&push, UVM_PUSH_FLAG_NEXT_MEMBAR_NONE); - mem_gpu_va = uvm_rm_mem_get_gpu_va(mem[0], gpu, is_proxy); + mem_gpu_va = uvm_rm_mem_get_gpu_va(mem[0], gpu, is_proxy).address; gpu->parent->ce_hal->memset_v_4(&push, mem_gpu_va, 1, CE_TEST_MEM_SIZE); for (i = 0; i < CE_TEST_MEM_COUNT; ++i) { @@ -91,9 +98,9 @@ if (dst == CE_TEST_MEM_COUNT) dst_va = host_mem_gpu_va; else - dst_va = uvm_rm_mem_get_gpu_va(mem[dst], gpu, is_proxy); + dst_va = uvm_rm_mem_get_gpu_va(mem[dst], gpu, is_proxy).address; - src_va = uvm_rm_mem_get_gpu_va(mem[i], gpu, is_proxy); + src_va = uvm_rm_mem_get_gpu_va(mem[i], gpu, is_proxy).address; // The first memcpy needs to be non-pipelined as otherwise the previous // memset/memcpy to the source may not be done yet. @@ -167,6 +174,11 @@ uvm_push_t push; NvU32 value; + // TODO: Bug 3839176: the test is waived on Confidential Computing because + // it assumes that GPU can access system memory without using encryption. + if (uvm_conf_computing_mode_enabled(gpu)) + return NV_OK; + status = uvm_rm_mem_alloc_and_map_cpu(gpu, UVM_RM_MEM_TYPE_SYS, sizeof(NvU32), 0, &host_mem); TEST_CHECK_GOTO(status == NV_OK, done); host_ptr = (NvU32 *)uvm_rm_mem_get_cpu_va(host_mem); @@ -175,7 +187,7 @@ status = uvm_push_begin(gpu->channel_manager, UVM_CHANNEL_TYPE_GPU_TO_CPU, &push, "Membar test"); TEST_CHECK_GOTO(status == NV_OK, done); - host_mem_gpu_va = uvm_rm_mem_get_gpu_va(host_mem, gpu, uvm_channel_is_proxy(push.channel)); + host_mem_gpu_va = uvm_rm_mem_get_gpu_va(host_mem, gpu, uvm_channel_is_proxy(push.channel)).address; for (i = 0; i < REDUCTIONS; ++i) { uvm_push_set_flag(&push, UVM_PUSH_FLAG_NEXT_MEMBAR_NONE); @@ -333,6 +345,16 @@ return NV_ERR_INVALID_STATE; } + // If physical accesses aren't supported, silently convert to virtual to + // test the flat mapping. + TEST_CHECK_RET(gpu_verif_addr.is_virtual); + + if (!src.is_virtual) + src = uvm_gpu_address_copy(gpu, uvm_gpu_phys_address(src.aperture, src.address)); + + if (!dst.is_virtual) + dst = uvm_gpu_address_copy(gpu, uvm_gpu_phys_address(dst.aperture, dst.address)); + // Memset src with the appropriate element size, then memcpy to dst and from // dst to the verif location (physical sysmem). @@ -374,7 +396,7 @@ static NV_STATUS test_memcpy_and_memset(uvm_gpu_t *gpu) { NV_STATUS status = NV_OK; - bool is_proxy_va_space; + bool is_proxy_va_space = false; uvm_gpu_address_t gpu_verif_addr; void *cpu_verif_addr; uvm_mem_t *verif_mem = NULL; @@ -382,17 +404,17 @@ uvm_mem_t *gpu_uvm_mem = NULL; uvm_rm_mem_t *sys_rm_mem = NULL; uvm_rm_mem_t *gpu_rm_mem = NULL; - uvm_gpu_address_t gpu_addresses[4]; - NvU64 gpu_va; - size_t size; + uvm_gpu_address_t gpu_addresses[4] = {0}; + size_t size = gpu->big_page.internal_size; static const size_t element_sizes[] = {1, 4, 8}; const size_t iterations = 4; size_t i, j, k, s; uvm_mem_alloc_params_t mem_params = {0}; - size = gpu->big_page.internal_size; - - TEST_NV_CHECK_GOTO(uvm_mem_alloc_sysmem_and_map_cpu_kernel(size, current->mm, &verif_mem), done); + if (uvm_conf_computing_mode_enabled(gpu)) + TEST_NV_CHECK_GOTO(uvm_mem_alloc_sysmem_dma_and_map_cpu_kernel(size, gpu, current->mm, &verif_mem), done); + else + TEST_NV_CHECK_GOTO(uvm_mem_alloc_sysmem_and_map_cpu_kernel(size, current->mm, &verif_mem), done); TEST_NV_CHECK_GOTO(uvm_mem_map_gpu_kernel(verif_mem, gpu), done); gpu_verif_addr = uvm_mem_gpu_address_virtual_kernel(verif_mem, gpu); @@ -410,6 +432,34 @@ } } + // Virtual address (in UVM's internal address space) backed by sysmem + TEST_NV_CHECK_GOTO(uvm_rm_mem_alloc(gpu, UVM_RM_MEM_TYPE_SYS, size, 0, &sys_rm_mem), done); + gpu_addresses[0] = uvm_rm_mem_get_gpu_va(sys_rm_mem, gpu, is_proxy_va_space); + + if (uvm_conf_computing_mode_enabled(gpu)) { + for (i = 0; i < iterations; ++i) { + for (s = 0; s < ARRAY_SIZE(element_sizes); s++) { + TEST_NV_CHECK_GOTO(test_memcpy_and_memset_inner(gpu, + gpu_addresses[0], + gpu_addresses[0], + size, + element_sizes[s], + gpu_verif_addr, + cpu_verif_addr, + i), + done); + + } + } + + // Because gpu_verif_addr is in sysmem, when the Confidential + // Computing feature is enabled, only the previous cases are valid. + // TODO: Bug 3839176: the test partially waived on Confidential + // Computing because it assumes that GPU can access system memory + // without using encryption. + goto done; + } + // Using a page size equal to the allocation size ensures that the UVM // memories about to be allocated are physically contiguous. And since the // size is a valid GPU page size, the memories can be virtually mapped on @@ -421,23 +471,17 @@ // Physical address in sysmem TEST_NV_CHECK_GOTO(uvm_mem_alloc(&mem_params, &sys_uvm_mem), done); TEST_NV_CHECK_GOTO(uvm_mem_map_gpu_phys(sys_uvm_mem, gpu), done); - gpu_addresses[0] = uvm_mem_gpu_address_physical(sys_uvm_mem, gpu, 0, size); + gpu_addresses[1] = uvm_mem_gpu_address_physical(sys_uvm_mem, gpu, 0, size); // Physical address in vidmem mem_params.backing_gpu = gpu; TEST_NV_CHECK_GOTO(uvm_mem_alloc(&mem_params, &gpu_uvm_mem), done); - gpu_addresses[1] = uvm_mem_gpu_address_physical(gpu_uvm_mem, gpu, 0, size); + gpu_addresses[2] = uvm_mem_gpu_address_physical(gpu_uvm_mem, gpu, 0, size); // Virtual address (in UVM's internal address space) backed by vidmem TEST_NV_CHECK_GOTO(uvm_rm_mem_alloc(gpu, UVM_RM_MEM_TYPE_GPU, size, 0, &gpu_rm_mem), done); - is_proxy_va_space = false; - gpu_va = uvm_rm_mem_get_gpu_va(gpu_rm_mem, gpu, is_proxy_va_space); - gpu_addresses[2] = uvm_gpu_address_virtual(gpu_va); + gpu_addresses[3] = uvm_rm_mem_get_gpu_va(gpu_rm_mem, gpu, is_proxy_va_space); - // Virtual address (in UVM's internal address space) backed by sysmem - TEST_NV_CHECK_GOTO(uvm_rm_mem_alloc(gpu, UVM_RM_MEM_TYPE_SYS, size, 0, &sys_rm_mem), done); - gpu_va = uvm_rm_mem_get_gpu_va(sys_rm_mem, gpu, is_proxy_va_space); - gpu_addresses[3] = uvm_gpu_address_virtual(gpu_va); for (i = 0; i < iterations; ++i) { for (j = 0; j < ARRAY_SIZE(gpu_addresses); ++j) { @@ -513,6 +557,11 @@ // Semaphore reduction needs 1 word (4 bytes). const size_t size = sizeof(NvU32); + // TODO: Bug 3839176: the test is waived on Confidential Computing because + // it assumes that GPU can access system memory without using encryption. + if (uvm_conf_computing_mode_enabled(gpu)) + return NV_OK; + status = test_semaphore_alloc_sem(gpu, size, &mem); TEST_CHECK_RET(status == NV_OK); @@ -560,6 +609,11 @@ // Semaphore release needs 1 word (4 bytes). const size_t size = sizeof(NvU32); + // TODO: Bug 3839176: the test is waived on Confidential Computing because + // it assumes that GPU can access system memory without using encryption. + if (uvm_conf_computing_mode_enabled(gpu)) + return NV_OK; + status = test_semaphore_alloc_sem(gpu, size, &mem); TEST_CHECK_RET(status == NV_OK); @@ -609,6 +663,11 @@ // The semaphore is 4 words long (16 bytes). const size_t size = 16; + // TODO: Bug 3839176: the test is waived on Confidential Computing because + // it assumes that GPU can access system memory without using encryption. + if (uvm_conf_computing_mode_enabled(gpu)) + return NV_OK; + status = test_semaphore_alloc_sem(gpu, size, &mem); TEST_CHECK_RET(status == NV_OK); @@ -645,6 +704,517 @@ return status; } +static bool mem_match(uvm_mem_t *mem1, uvm_mem_t *mem2, size_t size) +{ + void *mem1_addr; + void *mem2_addr; + + UVM_ASSERT(uvm_mem_is_sysmem(mem1)); + UVM_ASSERT(uvm_mem_is_sysmem(mem2)); + UVM_ASSERT(mem1->size >= size); + UVM_ASSERT(mem2->size >= size); + + mem1_addr = uvm_mem_get_cpu_addr_kernel(mem1); + mem2_addr = uvm_mem_get_cpu_addr_kernel(mem2); + + return !memcmp(mem1_addr, mem2_addr, size); +} + +static NV_STATUS zero_vidmem(uvm_mem_t *mem) +{ + uvm_push_t push; + uvm_gpu_address_t gpu_address; + uvm_gpu_t *gpu = mem->backing_gpu; + + UVM_ASSERT(uvm_mem_is_vidmem(mem)); + + TEST_NV_CHECK_RET(uvm_push_begin(gpu->channel_manager, UVM_CHANNEL_TYPE_GPU_INTERNAL, &push, "zero vidmem")); + + gpu_address = uvm_mem_gpu_address_virtual_kernel(mem, gpu); + gpu->parent->ce_hal->memset_1(&push, gpu_address, 0, mem->size); + + TEST_NV_CHECK_RET(uvm_push_end_and_wait(&push)); + + return NV_OK; +} + +static void write_range_cpu(uvm_mem_t *mem, NvU64 base_val) +{ + NvU64 *mem_cpu_va; + unsigned i; + + UVM_ASSERT(uvm_mem_is_sysmem(mem)); + UVM_ASSERT(IS_ALIGNED(mem->size, sizeof(*mem_cpu_va))); + + mem_cpu_va = (NvU64 *) uvm_mem_get_cpu_addr_kernel(mem); + + for (i = 0; i < (mem->size / sizeof(*mem_cpu_va)); i++) + mem_cpu_va[i] = base_val++; +} + +static NV_STATUS alloc_vidmem_protected(uvm_gpu_t *gpu, uvm_mem_t **mem, size_t size) +{ + NV_STATUS status; + + UVM_ASSERT(mem); + + *mem = NULL; + + TEST_NV_CHECK_RET(uvm_mem_alloc_vidmem(size, gpu, mem)); + TEST_NV_CHECK_GOTO(uvm_mem_map_gpu_kernel(*mem, gpu), err); + TEST_NV_CHECK_GOTO(zero_vidmem(*mem), err); + + return NV_OK; + +err: + uvm_mem_free(*mem); + return status; +} + +static NV_STATUS alloc_sysmem_unprotected(uvm_gpu_t *gpu, uvm_mem_t **mem, size_t size) +{ + NV_STATUS status; + + UVM_ASSERT(mem); + + *mem = NULL; + + TEST_NV_CHECK_RET(uvm_mem_alloc_sysmem_dma(size, gpu, NULL, mem)); + TEST_NV_CHECK_GOTO(uvm_mem_map_cpu_kernel(*mem), err); + TEST_NV_CHECK_GOTO(uvm_mem_map_gpu_kernel(*mem, gpu), err); + + memset(uvm_mem_get_cpu_addr_kernel(*mem), 0, (*mem)->size); + + return NV_OK; + +err: + uvm_mem_free(*mem); + return status; +} + +static void cpu_encrypt(uvm_channel_t *channel, + uvm_mem_t *dst_mem, + uvm_mem_t *src_mem, + uvm_mem_t *auth_tag_mem, + size_t size, + NvU32 copy_size) +{ + size_t offset = 0; + char *src_plain = (char *) uvm_mem_get_cpu_addr_kernel(src_mem); + char *dst_cipher = (char *) uvm_mem_get_cpu_addr_kernel(dst_mem); + char *auth_tag_buffer = (char *) uvm_mem_get_cpu_addr_kernel(auth_tag_mem); + + while (offset < size) { + uvm_conf_computing_cpu_encrypt(channel, dst_cipher, src_plain, NULL, copy_size, auth_tag_buffer); + + offset += copy_size; + dst_cipher += copy_size; + src_plain += copy_size; + auth_tag_buffer += UVM_CONF_COMPUTING_AUTH_TAG_SIZE; + } +} + +static void cpu_acquire_encryption_ivs(uvm_channel_t *channel, + size_t size, + NvU32 copy_size, + UvmCslIv *ivs) +{ + size_t offset = 0; + int i = 0; + + for (; offset < size; offset += copy_size) + uvm_conf_computing_acquire_encryption_iv(channel, &ivs[i++]); +} + +static void cpu_encrypt_rev(uvm_channel_t *channel, + uvm_mem_t *dst_mem, + uvm_mem_t *src_mem, + uvm_mem_t *auth_tag_mem, + size_t size, + NvU32 copy_size, + UvmCslIv *encrypt_iv) +{ + char *src_plain = (char *) uvm_mem_get_cpu_addr_kernel(src_mem); + char *dst_cipher = (char *) uvm_mem_get_cpu_addr_kernel(dst_mem); + char *auth_tag_buffer = (char *) uvm_mem_get_cpu_addr_kernel(auth_tag_mem); + int i; + + // CPU encrypt order is the opposite of the GPU decrypt order + for (i = (size / copy_size) - 1; i >= 0; i--) { + uvm_conf_computing_cpu_encrypt(channel, + dst_cipher + i * copy_size, + src_plain + i * copy_size, + encrypt_iv + i, + copy_size, + auth_tag_buffer + i * UVM_CONF_COMPUTING_AUTH_TAG_SIZE); + } +} + +static NV_STATUS cpu_decrypt_in_order(uvm_channel_t *channel, + uvm_mem_t *dst_mem, + uvm_mem_t *src_mem, + const UvmCslIv *decrypt_iv, + uvm_mem_t *auth_tag_mem, + size_t size, + NvU32 copy_size) +{ + size_t i; + char *dst_plain = (char *) uvm_mem_get_cpu_addr_kernel(dst_mem); + char *src_cipher = (char *) uvm_mem_get_cpu_addr_kernel(src_mem); + char *auth_tag_buffer = (char *) uvm_mem_get_cpu_addr_kernel(auth_tag_mem); + + for (i = 0; i < size / copy_size; i++) { + TEST_NV_CHECK_RET(uvm_conf_computing_cpu_decrypt(channel, + dst_plain + i * copy_size, + src_cipher + i * copy_size, + decrypt_iv + i, + copy_size, + auth_tag_buffer + i * UVM_CONF_COMPUTING_AUTH_TAG_SIZE)); + } + + return NV_OK; +} +static NV_STATUS cpu_decrypt_out_of_order(uvm_channel_t *channel, + uvm_mem_t *dst_mem, + uvm_mem_t *src_mem, + const UvmCslIv *decrypt_iv, + uvm_mem_t *auth_tag_mem, + size_t size, + NvU32 copy_size) +{ + int i; + char *dst_plain = (char *) uvm_mem_get_cpu_addr_kernel(dst_mem); + char *src_cipher = (char *) uvm_mem_get_cpu_addr_kernel(src_mem); + char *auth_tag_buffer = (char *) uvm_mem_get_cpu_addr_kernel(auth_tag_mem); + + UVM_ASSERT((size / copy_size) <= INT_MAX); + + // CPU decrypt order is the opposite of the GPU decrypt order + for (i = (size / copy_size) - 1; i >= 0; i--) { + TEST_NV_CHECK_RET(uvm_conf_computing_cpu_decrypt(channel, + dst_plain + i * copy_size, + src_cipher + i * copy_size, + decrypt_iv + i, + copy_size, + auth_tag_buffer + i * UVM_CONF_COMPUTING_AUTH_TAG_SIZE)); + } + + return NV_OK; +} + +// GPU address to use as source or destination in CE decrypt/encrypt operations. +// If the uvm_mem backing storage is contiguous in the [offset, offset + size) +// interval, the physical address gets priority over the virtual counterpart. +static uvm_gpu_address_t gpu_address(uvm_mem_t *mem, uvm_gpu_t *gpu, NvU64 offset, NvU32 size) +{ + uvm_gpu_address_t gpu_virtual_address; + + if (uvm_mem_is_physically_contiguous(mem, offset, size)) + return uvm_mem_gpu_address_physical(mem, gpu, offset, size); + + gpu_virtual_address = uvm_mem_gpu_address_virtual_kernel(mem, gpu); + gpu_virtual_address.address += offset; + + return gpu_virtual_address; +} + +// Automatically get the correct address for the authentication tag. The +// addressing mode of the tag should match that of the reference address +// (destination pointer for GPU encrypt, source pointer for GPU encrypt) +static uvm_gpu_address_t auth_tag_gpu_address(uvm_mem_t *auth_tag_mem, + uvm_gpu_t *gpu, + size_t offset, + uvm_gpu_address_t reference) +{ + uvm_gpu_address_t auth_tag_gpu_address; + + if (!reference.is_virtual) + return uvm_mem_gpu_address_physical(auth_tag_mem, gpu, offset, UVM_CONF_COMPUTING_AUTH_TAG_SIZE); + + auth_tag_gpu_address = uvm_mem_gpu_address_virtual_kernel(auth_tag_mem, gpu); + auth_tag_gpu_address.address += offset; + + return auth_tag_gpu_address; +} + +// Note: no membar is issued in any of the GPU transfers (encryptions) +static void gpu_encrypt(uvm_push_t *push, + uvm_mem_t *dst_mem, + uvm_mem_t *src_mem, + uvm_mem_t *auth_tag_mem, + UvmCslIv *decrypt_iv, + size_t size, + NvU32 copy_size) +{ + size_t i; + size_t num_iterations = size / copy_size; + uvm_gpu_t *gpu = uvm_push_get_gpu(push); + + for (i = 0; i < num_iterations; i++) { + uvm_gpu_address_t dst_cipher = gpu_address(dst_mem, gpu, i * copy_size, copy_size); + uvm_gpu_address_t src_plain = gpu_address(src_mem, gpu, i * copy_size, copy_size); + uvm_gpu_address_t auth_tag = auth_tag_gpu_address(auth_tag_mem, + gpu, + i * UVM_CONF_COMPUTING_AUTH_TAG_SIZE, + dst_cipher); + + uvm_conf_computing_log_gpu_encryption(push->channel, decrypt_iv); + + if (i > 0) + uvm_push_set_flag(push, UVM_PUSH_FLAG_CE_NEXT_PIPELINED); + + uvm_push_set_flag(push, UVM_PUSH_FLAG_NEXT_MEMBAR_NONE); + + gpu->parent->ce_hal->encrypt(push, dst_cipher, src_plain, copy_size, auth_tag); + decrypt_iv++; + } +} + +// Note: no membar is issued in any of the GPU transfers (decryptions) +static void gpu_decrypt(uvm_push_t *push, + uvm_mem_t *dst_mem, + uvm_mem_t *src_mem, + uvm_mem_t *auth_tag_mem, + size_t size, + NvU32 copy_size) +{ + size_t i; + size_t num_iterations = size / copy_size; + uvm_gpu_t *gpu = uvm_push_get_gpu(push); + + for (i = 0; i < num_iterations; i++) { + uvm_gpu_address_t dst_plain = gpu_address(dst_mem, gpu, i * copy_size, copy_size); + uvm_gpu_address_t src_cipher = gpu_address(src_mem, gpu, i * copy_size, copy_size); + uvm_gpu_address_t auth_tag = auth_tag_gpu_address(auth_tag_mem, + gpu, + i * UVM_CONF_COMPUTING_AUTH_TAG_SIZE, + src_cipher); + + if (i > 0) + uvm_push_set_flag(push, UVM_PUSH_FLAG_CE_NEXT_PIPELINED); + + uvm_push_set_flag(push, UVM_PUSH_FLAG_NEXT_MEMBAR_NONE); + + gpu->parent->ce_hal->decrypt(push, dst_plain, src_cipher, copy_size, auth_tag); + } +} + +static NV_STATUS test_cpu_to_gpu_roundtrip(uvm_gpu_t *gpu, + uvm_channel_type_t decrypt_channel_type, + uvm_channel_type_t encrypt_channel_type, + size_t size, + NvU32 copy_size, + bool decrypt_in_order, + bool encrypt_in_order) +{ + uvm_push_t push; + NvU64 init_value; + NV_STATUS status = NV_OK; + uvm_mem_t *src_plain = NULL; + uvm_mem_t *src_cipher = NULL; + uvm_mem_t *dst_cipher = NULL; + uvm_mem_t *dst_plain_gpu = NULL; + uvm_mem_t *dst_plain = NULL; + uvm_mem_t *auth_tag_mem = NULL; + size_t auth_tag_buffer_size = (size / copy_size) * UVM_CONF_COMPUTING_AUTH_TAG_SIZE; + UvmCslIv *decrypt_iv = NULL; + UvmCslIv *encrypt_iv = NULL; + uvm_tracker_t tracker; + size_t src_plain_size; + + TEST_CHECK_RET(copy_size <= size); + TEST_CHECK_RET(IS_ALIGNED(size, copy_size)); + + uvm_tracker_init(&tracker); + + decrypt_iv = uvm_kvmalloc_zero((size / copy_size) * sizeof(UvmCslIv)); + if (!decrypt_iv) { + status = NV_ERR_NO_MEMORY; + goto out; + } + + encrypt_iv = uvm_kvmalloc_zero((size / copy_size) * sizeof(UvmCslIv)); + if (!encrypt_iv) { + status = NV_ERR_NO_MEMORY; + goto out; + } + + TEST_NV_CHECK_GOTO(alloc_sysmem_unprotected(gpu, &src_cipher, size), out); + TEST_NV_CHECK_GOTO(alloc_vidmem_protected(gpu, &dst_plain_gpu, size), out); + TEST_NV_CHECK_GOTO(alloc_sysmem_unprotected(gpu, &dst_cipher, size), out); + TEST_NV_CHECK_GOTO(alloc_sysmem_unprotected(gpu, &dst_plain, size), out); + TEST_NV_CHECK_GOTO(alloc_sysmem_unprotected(gpu, &auth_tag_mem, auth_tag_buffer_size), out); + + // The plaintext CPU buffer size should fit the initialization value + src_plain_size = UVM_ALIGN_UP(size, sizeof(init_value)); + TEST_NV_CHECK_GOTO(alloc_sysmem_unprotected(gpu, &src_plain, src_plain_size), out); + + // Initialize the plaintext CPU buffer using a value that uniquely + // identifies the given inputs + TEST_CHECK_GOTO((((NvU64) size) < (1ULL << 63)), out); + init_value = ((NvU64) decrypt_in_order << 63) | ((NvU64) size) | ((NvU64) copy_size); + write_range_cpu(src_plain, init_value); + + TEST_NV_CHECK_GOTO(uvm_push_begin(gpu->channel_manager, + decrypt_channel_type, + &push, + "CPU > GPU decrypt"), + out); + + // CPU (decrypted) > CPU (encrypted), using CPU, if in-order + // acquire IVs if not in-order + if (encrypt_in_order) + cpu_encrypt(push.channel, src_cipher, src_plain, auth_tag_mem, size, copy_size); + else + cpu_acquire_encryption_ivs(push.channel, size, copy_size, encrypt_iv); + + // CPU (encrypted) > GPU (decrypted), using GPU + gpu_decrypt(&push, dst_plain_gpu, src_cipher, auth_tag_mem, size, copy_size); + + // Use acquired IVs to encrypt in reverse order + if (!encrypt_in_order) + cpu_encrypt_rev(push.channel, src_cipher, src_plain, auth_tag_mem, size, copy_size, encrypt_iv); + + uvm_push_end(&push); + TEST_NV_CHECK_GOTO(uvm_tracker_add_push(&tracker, &push), out); + + // GPU (decrypted) > CPU (encrypted), using GPU + TEST_NV_CHECK_GOTO(uvm_push_begin_acquire(gpu->channel_manager, + encrypt_channel_type, + &tracker, + &push, + "GPU > CPU encrypt"), + out); + + gpu_encrypt(&push, dst_cipher, dst_plain_gpu, auth_tag_mem, decrypt_iv, size, copy_size); + + TEST_NV_CHECK_GOTO(uvm_push_end_and_wait(&push), out); + + TEST_CHECK_GOTO(!mem_match(src_plain, src_cipher, size), out); + + TEST_CHECK_GOTO(!mem_match(dst_cipher, src_plain, size), out); + + // CPU (encrypted) > CPU (decrypted), using CPU + if (decrypt_in_order) { + TEST_NV_CHECK_GOTO(cpu_decrypt_in_order(push.channel, + dst_plain, + dst_cipher, + decrypt_iv, + auth_tag_mem, + size, + copy_size), + out); + } + else { + TEST_NV_CHECK_GOTO(cpu_decrypt_out_of_order(push.channel, + dst_plain, + dst_cipher, + decrypt_iv, + auth_tag_mem, + size, + copy_size), + out); + } + + TEST_CHECK_GOTO(mem_match(src_plain, dst_plain, size), out); + +out: + uvm_mem_free(auth_tag_mem); + uvm_mem_free(dst_plain); + uvm_mem_free(dst_plain_gpu); + uvm_mem_free(dst_cipher); + uvm_mem_free(src_cipher); + uvm_mem_free(src_plain); + uvm_tracker_deinit(&tracker); + uvm_kvfree(decrypt_iv); + uvm_kvfree(encrypt_iv); + + return status; +} + +static NV_STATUS test_encryption_decryption(uvm_gpu_t *gpu, + uvm_channel_type_t decrypt_channel_type, + uvm_channel_type_t encrypt_channel_type) +{ + bool cpu_decrypt_in_order = true; + bool cpu_encrypt_in_order = true; + size_t size[] = {UVM_PAGE_SIZE_4K, UVM_PAGE_SIZE_4K * 2, UVM_PAGE_SIZE_2M}; + size_t copy_size[] = {UVM_PAGE_SIZE_4K, UVM_PAGE_SIZE_64K, UVM_PAGE_SIZE_2M}; + unsigned i; + + struct { + bool encrypt_in_order; + bool decrypt_in_order; + } orders[] = {{true, true}, {true, false}, {false, true}, {false, false}}; + + struct { + size_t size; + NvU32 copy_size; + } small_sizes[] = {{1, 1}, {3, 1}, {8, 1}, {2, 2}, {8, 4}, {UVM_PAGE_SIZE_4K - 8, 8}, {UVM_PAGE_SIZE_4K + 8, 8}}; + + // Only Confidential Computing uses CE encryption/decryption + if (!uvm_conf_computing_mode_enabled(gpu)) + return NV_OK; + + // Use a size, and copy size, that are not a multiple of common page sizes. + for (i = 0; i < ARRAY_SIZE(small_sizes); ++i) { + // Skip tests that need large pushbuffer on WLC. Secure work launch + // needs to do at least one decrypt operation so tests that only need + // one operation work ok. Tests using more operations might overflow + // UVM_MAX_WLC_PUSH_SIZE. + if (encrypt_channel_type == UVM_CHANNEL_TYPE_WLC && (small_sizes[i].size / small_sizes[i].copy_size > 1)) + continue; + + TEST_NV_CHECK_RET(test_cpu_to_gpu_roundtrip(gpu, + decrypt_channel_type, + encrypt_channel_type, + small_sizes[i].size, + small_sizes[i].copy_size, + cpu_decrypt_in_order, + cpu_encrypt_in_order)); + } + + // Use sizes, and copy sizes, that are a multiple of common page sizes. + // This is the most typical usage of encrypt/decrypt in the UVM driver. + for (i = 0; i < ARRAY_SIZE(orders); ++i) { + unsigned j; + + cpu_encrypt_in_order = orders[i].encrypt_in_order; + cpu_decrypt_in_order = orders[i].decrypt_in_order; + + for (j = 0; j < ARRAY_SIZE(size); ++j) { + unsigned k; + + for (k = 0; k < ARRAY_SIZE(copy_size); ++k) { + if (copy_size[k] > size[j]) + continue; + + // Skip tests that need large pushbuffer on WLC. Secure work + // launch needs to do at least one decrypt operation so tests + // that only need one operation work ok. Tests using more + // operations might overflow UVM_MAX_WLC_PUSH_SIZE. + if (encrypt_channel_type == UVM_CHANNEL_TYPE_WLC && (size[j] / copy_size[k] > 1)) + continue; + + // There is no difference between in-order and out-of-order + // decryption when encrypting once. + if ((copy_size[k] == size[j]) && !cpu_decrypt_in_order) + continue; + + TEST_NV_CHECK_RET(test_cpu_to_gpu_roundtrip(gpu, + decrypt_channel_type, + encrypt_channel_type, + size[j], + copy_size[k], + cpu_decrypt_in_order, + cpu_encrypt_in_order)); + } + } + } + + return NV_OK; +} + static NV_STATUS test_ce(uvm_va_space_t *va_space, bool skipTimestampTest) { uvm_gpu_t *gpu; @@ -655,9 +1225,13 @@ TEST_NV_CHECK_RET(test_memcpy_and_memset(gpu)); TEST_NV_CHECK_RET(test_semaphore_reduction_inc(gpu)); TEST_NV_CHECK_RET(test_semaphore_release(gpu)); + if (!skipTimestampTest) TEST_NV_CHECK_RET(test_semaphore_timestamp(gpu)); - } + + TEST_NV_CHECK_RET(test_encryption_decryption(gpu, UVM_CHANNEL_TYPE_CPU_TO_GPU, UVM_CHANNEL_TYPE_GPU_TO_CPU)); + TEST_NV_CHECK_RET(test_encryption_decryption(gpu, UVM_CHANNEL_TYPE_WLC, UVM_CHANNEL_TYPE_WLC)); + } return NV_OK; } diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/kernel-open/nvidia-uvm/uvm_channel.c nvidia-open-gpu-kernel-modules-535.161.08/kernel-open/nvidia-uvm/uvm_channel.c --- nvidia-open-gpu-kernel-modules-525.147.05/kernel-open/nvidia-uvm/uvm_channel.c 2023-10-25 20:33:34.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/kernel-open/nvidia-uvm/uvm_channel.c 2024-03-05 22:25:50.000000000 +0000 @@ -1,5 +1,5 @@ /******************************************************************************* - Copyright (c) 2015-2022 NVIDIA Corporation + Copyright (c) 2015-2023 NVIDIA Corporation Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation files (the "Software"), to @@ -33,8 +33,10 @@ #include "uvm_lock.h" #include "uvm_kvmalloc.h" +#include "nv_uvm_types.h" #include "nv_uvm_interface.h" #include "clb06f.h" +#include "uvm_conf_computing.h" static unsigned uvm_channel_num_gpfifo_entries = UVM_CHANNEL_NUM_GPFIFO_ENTRIES_DEFAULT; @@ -69,38 +71,55 @@ UVM_CHANNEL_UPDATE_MODE_FORCE_ALL } uvm_channel_update_mode_t; -static void channel_pool_lock_init(uvm_channel_pool_t *pool) +bool uvm_channel_pool_uses_mutex(uvm_channel_pool_t *pool) { + // Work submission to proxy channels in SR-IOV heavy entails calling RM API + // that acquires a mutex, so the proxy channel pool must use a mutex. if (uvm_channel_pool_is_proxy(pool)) - uvm_mutex_init(&pool->mutex, UVM_LOCK_ORDER_CHANNEL); + return true; + + // When Confidential Computing is enabled push submission requires call to + // CSL routines which acquire the CSL context mutex lock. Moreover, WLC + // submission uses UVM_SPIN_LOOP, which can call 'schedule', to wait for + // LCIC completion. Indirect submission is synchronous, calling + // uvm_push_wait which again uses UVM_SPIN_LOOP. + if (uvm_conf_computing_mode_enabled(pool->manager->gpu)) + return true; + + // Unless the mutex is required, the spinlock is preferred when work + // submission is expected to take little time. + return false; +} + +static void channel_pool_lock_init(uvm_channel_pool_t *pool) +{ + uvm_lock_order_t order = UVM_LOCK_ORDER_CHANNEL; + + if (uvm_conf_computing_mode_enabled(pool->manager->gpu) && uvm_channel_pool_is_wlc(pool)) + order = UVM_LOCK_ORDER_WLC_CHANNEL; + + if (uvm_channel_pool_uses_mutex(pool)) + uvm_mutex_init(&pool->mutex, order); else - uvm_spin_lock_init(&pool->spinlock, UVM_LOCK_ORDER_CHANNEL); + uvm_spin_lock_init(&pool->spinlock, order); } -void uvm_channel_pool_lock(uvm_channel_pool_t *pool) +static void channel_pool_lock(uvm_channel_pool_t *pool) { - if (uvm_channel_pool_is_proxy(pool)) + if (uvm_channel_pool_uses_mutex(pool)) uvm_mutex_lock(&pool->mutex); else uvm_spin_lock(&pool->spinlock); } -void uvm_channel_pool_unlock(uvm_channel_pool_t *pool) +static void channel_pool_unlock(uvm_channel_pool_t *pool) { - if (uvm_channel_pool_is_proxy(pool)) + if (uvm_channel_pool_uses_mutex(pool)) uvm_mutex_unlock(&pool->mutex); else uvm_spin_unlock(&pool->spinlock); } -void uvm_channel_pool_assert_locked(uvm_channel_pool_t *pool) -{ - if (uvm_channel_pool_is_proxy(pool)) - uvm_assert_mutex_locked(&pool->mutex); - else - uvm_assert_spinlock_locked(&pool->spinlock); -} - // Update channel progress, completing up to max_to_complete entries static NvU32 uvm_channel_update_progress_with_max(uvm_channel_t *channel, NvU32 max_to_complete, @@ -113,12 +132,14 @@ NvU64 completed_value = uvm_channel_update_completed_value(channel); - uvm_channel_pool_lock(channel->pool); + channel_pool_lock(channel->pool); // Completed value should never exceed the queued value UVM_ASSERT_MSG_RELEASE(completed_value <= channel->tracking_sem.queued_value, "GPU %s channel %s unexpected completed_value 0x%llx > queued_value 0x%llx\n", - channel->pool->manager->gpu->parent->name, channel->name, completed_value, + channel->pool->manager->gpu->parent->name, + channel->name, + completed_value, channel->tracking_sem.queued_value); cpu_put = channel->cpu_put; @@ -131,7 +152,7 @@ break; if (entry->type == UVM_GPFIFO_ENTRY_TYPE_NORMAL) { - uvm_pushbuffer_mark_completed(channel->pool->manager->pushbuffer, entry); + uvm_pushbuffer_mark_completed(channel, entry); list_add_tail(&entry->push_info->available_list_node, &channel->available_push_infos); } @@ -141,7 +162,7 @@ channel->gpu_get = gpu_get; - uvm_channel_pool_unlock(channel->pool); + channel_pool_unlock(channel->pool); if (cpu_put >= gpu_get) pending_gpfifos = cpu_put - gpu_get; @@ -154,7 +175,8 @@ NvU32 uvm_channel_update_progress(uvm_channel_t *channel) { // By default, don't complete too many entries at a time to spread the cost - // of doing so across callers and avoid holding a spin lock for too long. + // of doing so across callers and avoid potentially holding a spin lock for + // too long. return uvm_channel_update_progress_with_max(channel, 8, UVM_CHANNEL_UPDATE_MODE_COMPLETED); } @@ -186,52 +208,189 @@ return pending_gpfifos; } -static bool channel_is_available(uvm_channel_t *channel, NvU32 num_gpfifo_entries) +static NvU32 channel_get_available_gpfifo_entries(uvm_channel_t *channel) { - NvU32 pending_entries; + NvU32 available = channel->num_gpfifo_entries; uvm_channel_pool_assert_locked(channel->pool); + // Remove sentinel entry + available -= 1; + + // Remove entries of ongoing pushes + available -= channel->current_gpfifo_count; + + // Remove pending entries if (channel->cpu_put >= channel->gpu_get) - pending_entries = channel->cpu_put - channel->gpu_get; + available -= (channel->cpu_put - channel->gpu_get); else - pending_entries = channel->cpu_put + channel->num_gpfifo_entries - channel->gpu_get; + available -= (channel->cpu_put + channel->num_gpfifo_entries - channel->gpu_get); + + UVM_ASSERT(available < channel->num_gpfifo_entries); - return (pending_entries + channel->current_gpfifo_count + num_gpfifo_entries < channel->num_gpfifo_entries); + return available; } -static bool try_claim_channel(uvm_channel_t *channel, NvU32 num_gpfifo_entries) +NvU32 uvm_channel_get_available_gpfifo_entries(uvm_channel_t *channel) +{ + NvU32 available; + + channel_pool_lock(channel->pool); + available = channel_get_available_gpfifo_entries(channel); + channel_pool_unlock(channel->pool); + + return available; +} + +static bool try_claim_channel_locked(uvm_channel_t *channel, NvU32 num_gpfifo_entries) { bool claimed = false; UVM_ASSERT(num_gpfifo_entries > 0); UVM_ASSERT(num_gpfifo_entries < channel->num_gpfifo_entries); - uvm_channel_pool_lock(channel->pool); + uvm_channel_pool_assert_locked(channel->pool); - if (channel_is_available(channel, num_gpfifo_entries)) { + if (channel_get_available_gpfifo_entries(channel) >= num_gpfifo_entries) { channel->current_gpfifo_count += num_gpfifo_entries; claimed = true; } - uvm_channel_pool_unlock(channel->pool); - return claimed; } -static void lock_push(uvm_channel_t *channel) +static bool try_claim_channel(uvm_channel_t *channel, NvU32 num_gpfifo_entries) { + bool claimed; + + channel_pool_lock(channel->pool); + claimed = try_claim_channel_locked(channel, num_gpfifo_entries); + channel_pool_unlock(channel->pool); + + return claimed; } -static void unlock_push(uvm_channel_t *channel) +static void unlock_channel_for_push(uvm_channel_t *channel) { + NvU32 index; + uvm_gpu_t *gpu = uvm_channel_get_gpu(channel); + + if (!uvm_conf_computing_mode_enabled(gpu)) + return; + + index = uvm_channel_index_in_pool(channel); + + uvm_channel_pool_assert_locked(channel->pool); + UVM_ASSERT(test_bit(index, channel->pool->push_locks)); + + __clear_bit(index, channel->pool->push_locks); + uvm_up_out_of_order(&channel->pool->push_sem); } -static bool trylock_push(uvm_channel_t *channel) +static bool is_channel_locked_for_push(uvm_channel_t *channel) { + uvm_gpu_t *gpu = uvm_channel_get_gpu(channel); + + if (uvm_conf_computing_mode_enabled(gpu)) + return test_bit(uvm_channel_index_in_pool(channel), channel->pool->push_locks); + + // For CE and proxy channels, we always return that the channel is locked, + // which has no functional impact in the UVM channel code-flow, this is only + // used on UVM_ASSERTs. return true; } +static void lock_channel_for_push(uvm_channel_t *channel) +{ + uvm_gpu_t *gpu = uvm_channel_get_gpu(channel); + NvU32 index = uvm_channel_index_in_pool(channel); + + UVM_ASSERT(uvm_conf_computing_mode_enabled(gpu)); + uvm_channel_pool_assert_locked(channel->pool); + UVM_ASSERT(!test_bit(index, channel->pool->push_locks)); + + __set_bit(index, channel->pool->push_locks); +} + +static bool test_claim_and_lock_channel(uvm_channel_t *channel, NvU32 num_gpfifo_entries) +{ + uvm_gpu_t *gpu = uvm_channel_get_gpu(channel); + NvU32 index = uvm_channel_index_in_pool(channel); + + UVM_ASSERT(uvm_conf_computing_mode_enabled(gpu)); + uvm_channel_pool_assert_locked(channel->pool); + + if (!test_bit(index, channel->pool->push_locks) && try_claim_channel_locked(channel, num_gpfifo_entries)) { + lock_channel_for_push(channel); + return true; + } + + return false; +} + +// Reserve a channel in the specified pool. The channel is locked until the push +// ends +static NV_STATUS channel_reserve_and_lock_in_pool(uvm_channel_pool_t *pool, uvm_channel_t **channel_out) +{ + uvm_channel_t *channel; + uvm_spin_loop_t spin; + NvU32 index; + + UVM_ASSERT(pool); + UVM_ASSERT(uvm_conf_computing_mode_enabled(pool->manager->gpu)); + + // This semaphore is uvm_up() in unlock_channel_for_push() as part of the + // uvm_channel_end_push() routine. + uvm_down(&pool->push_sem); + + // At least one channel is unlocked. We check if any unlocked channel is + // available, i.e., if it has free GPFIFO entries. + + channel_pool_lock(pool); + + for_each_clear_bit(index, pool->push_locks, pool->num_channels) { + channel = &pool->channels[index]; + if (try_claim_channel_locked(channel, 1)) { + lock_channel_for_push(channel); + goto done; + } + } + + channel_pool_unlock(pool); + + // No channels are available. Update and check errors on all channels until + // one becomes available. + uvm_spin_loop_init(&spin); + while (1) { + uvm_for_each_channel_in_pool(channel, pool) { + NV_STATUS status; + + uvm_channel_update_progress(channel); + index = uvm_channel_index_in_pool(channel); + + channel_pool_lock(pool); + + if (test_claim_and_lock_channel(channel, 1)) + goto done; + + channel_pool_unlock(pool); + + status = uvm_channel_check_errors(channel); + if (status != NV_OK) { + uvm_up(&pool->push_sem); + return status; + } + + UVM_SPIN_LOOP(&spin); + } + } + +done: + channel_pool_unlock(pool); + *channel_out = channel; + return NV_OK; +} + // Reserve a channel in the specified pool static NV_STATUS channel_reserve_in_pool(uvm_channel_pool_t *pool, uvm_channel_t **channel_out) { @@ -240,16 +399,14 @@ UVM_ASSERT(pool); + if (uvm_conf_computing_mode_enabled(pool->manager->gpu)) + return channel_reserve_and_lock_in_pool(pool, channel_out); + uvm_for_each_channel_in_pool(channel, pool) { // TODO: Bug 1764953: Prefer idle/less busy channels - if (trylock_push(channel)) { - if (try_claim_channel(channel, 1)) { - *channel_out = channel; - return NV_OK; - } - else { - unlock_push(channel); - } + if (try_claim_channel(channel, 1)) { + *channel_out = channel; + return NV_OK; } } @@ -261,7 +418,6 @@ uvm_channel_update_progress(channel); if (try_claim_channel(channel, 1)) { - lock_push(channel); *channel_out = channel; return NV_OK; @@ -276,14 +432,18 @@ } UVM_ASSERT_MSG(0, "Cannot get here?!\n"); + return NV_ERR_GENERIC; } NV_STATUS uvm_channel_reserve_type(uvm_channel_manager_t *manager, uvm_channel_type_t type, uvm_channel_t **channel_out) { + uvm_channel_pool_t *pool = manager->pool_to_use.default_for_type[type]; + + UVM_ASSERT(pool != NULL); UVM_ASSERT(type < UVM_CHANNEL_TYPE_COUNT); - return channel_reserve_in_pool(manager->pool_to_use.default_for_type[type], channel_out); + return channel_reserve_in_pool(pool, channel_out); } NV_STATUS uvm_channel_reserve_gpu_to_gpu(uvm_channel_manager_t *manager, @@ -323,36 +483,109 @@ { uvm_push_info_t *push_info; - uvm_channel_pool_lock(channel->pool); + channel_pool_lock(channel->pool); push_info = list_first_entry_or_null(&channel->available_push_infos, uvm_push_info_t, available_list_node); UVM_ASSERT(push_info != NULL); UVM_ASSERT(push_info->on_complete == NULL && push_info->on_complete_data == NULL); list_del(&push_info->available_list_node); - uvm_channel_pool_unlock(channel->pool); + channel_pool_unlock(channel->pool); return push_info - channel->push_infos; } +static void channel_semaphore_gpu_encrypt_payload(uvm_push_t *push, NvU64 semaphore_va) +{ + NvU32 iv_index; + uvm_gpu_address_t notifier_gpu_va; + uvm_gpu_address_t auth_tag_gpu_va; + uvm_gpu_address_t semaphore_gpu_va; + uvm_gpu_address_t encrypted_payload_gpu_va; + uvm_gpu_t *gpu = push->gpu; + uvm_channel_t *channel = push->channel; + uvm_gpu_semaphore_t *semaphore = &channel->tracking_sem.semaphore; + UvmCslIv *iv_cpu_addr = semaphore->conf_computing.ivs; + NvU32 payload_size = sizeof(*semaphore->payload); + NvU32 *last_pushed_notifier = &semaphore->conf_computing.last_pushed_notifier; + + UVM_ASSERT(uvm_conf_computing_mode_enabled(gpu)); + UVM_ASSERT(uvm_channel_is_ce(channel)); + + encrypted_payload_gpu_va = uvm_rm_mem_get_gpu_va(semaphore->conf_computing.encrypted_payload, gpu, false); + notifier_gpu_va = uvm_rm_mem_get_gpu_va(semaphore->conf_computing.notifier, gpu, false); + auth_tag_gpu_va = uvm_rm_mem_get_gpu_va(semaphore->conf_computing.auth_tag, gpu, false); + semaphore_gpu_va = uvm_gpu_address_virtual(semaphore_va); + + iv_index = ((*last_pushed_notifier + 2) / 2) % channel->num_gpfifo_entries; + + uvm_conf_computing_log_gpu_encryption(channel, &iv_cpu_addr[iv_index]); + + gpu->parent->ce_hal->memset_4(push, notifier_gpu_va, ++(*last_pushed_notifier), sizeof(*last_pushed_notifier)); + gpu->parent->ce_hal->encrypt(push, encrypted_payload_gpu_va, semaphore_gpu_va, payload_size, auth_tag_gpu_va); + gpu->parent->ce_hal->memset_4(push, notifier_gpu_va, ++(*last_pushed_notifier), sizeof(*last_pushed_notifier)); +} + +// Auxiliary buffer only used by SEC2 channels for CPU computation of the method +// stream signature. Note that it is required that this inline pushbuffer buffer +// is reserved at push->begin. +static void push_reserve_csl_sign_buf(uvm_push_t *push) +{ + uvm_gpu_address_t dummy; + NvU32 *buf; + + buf = uvm_push_get_single_inline_buffer(push, UVM_CONF_COMPUTING_SIGN_BUF_MAX_SIZE, UVM_METHOD_SIZE, &dummy); + + // Offset UVM_METHOD_SIZE from buf due to the NOP method. + UVM_ASSERT((buf - UVM_METHOD_SIZE / sizeof(*buf)) == push->begin); +} + NV_STATUS uvm_channel_begin_push(uvm_channel_t *channel, uvm_push_t *push) { NV_STATUS status; uvm_channel_manager_t *manager; + uvm_gpu_t *gpu; UVM_ASSERT(channel); UVM_ASSERT(push); manager = channel->pool->manager; + gpu = uvm_channel_get_gpu(channel); + + // Only SEC2 and WLC with set up fixed schedule can use direct push + // submission. All other cases (including WLC pre-schedule) need to + // reserve a launch channel that will be used to submit this push + // indirectly. + if (uvm_conf_computing_mode_enabled(gpu) && uvm_channel_is_ce(channel) && + !(uvm_channel_is_wlc(channel) && uvm_channel_manager_is_wlc_ready(manager))) { + uvm_channel_type_t indirect_channel_type = uvm_channel_manager_is_wlc_ready(manager) ? + UVM_CHANNEL_TYPE_WLC : + UVM_CHANNEL_TYPE_SEC2; + status = uvm_channel_reserve_type(manager, indirect_channel_type, &push->launch_channel); + if (status != NV_OK) + return status; + } + + // When the Confidential Computing feature is enabled, the channel's lock + // should have already been acquired in uvm_channel_reserve() or + // channel_reserve_and_lock_in_pool(). + UVM_ASSERT(is_channel_locked_for_push(channel)); + + push->channel = channel; + push->channel_tracking_value = 0; + status = uvm_pushbuffer_begin_push(manager->pushbuffer, push); if (status != NV_OK) return status; - push->channel = channel; - push->channel_tracking_value = 0; push->push_info_index = channel_get_available_push_info_index(channel); + if (uvm_channel_is_sec2(push->channel)) + push_reserve_csl_sign_buf(push); + else if (uvm_channel_is_wlc(push->channel) && uvm_channel_manager_is_wlc_ready(manager)) + uvm_conf_computing_acquire_encryption_iv(push->channel, &push->launch_iv); + return NV_OK; } @@ -361,9 +594,8 @@ NvU64 *gpfifo_entry; NvU64 pushbuffer_va; uvm_channel_t *channel = push->channel; - uvm_channel_manager_t *channel_manager = channel->pool->manager; - uvm_pushbuffer_t *pushbuffer = channel_manager->pushbuffer; - uvm_gpu_t *gpu = channel_manager->gpu; + uvm_pushbuffer_t *pushbuffer = uvm_channel_get_pushbuffer(channel); + uvm_gpu_t *gpu = uvm_channel_get_gpu(channel); BUILD_BUG_ON(sizeof(*gpfifo_entry) != NVB06F_GP_ENTRY__SIZE); UVM_ASSERT(!uvm_channel_is_proxy(channel)); @@ -371,7 +603,15 @@ gpfifo_entry = (NvU64*)channel->channel_info.gpFifoEntries + channel->cpu_put; pushbuffer_va = uvm_pushbuffer_get_gpu_va_for_push(pushbuffer, push); - gpu->parent->host_hal->set_gpfifo_entry(gpfifo_entry, pushbuffer_va, push_size); + if (uvm_conf_computing_mode_enabled(gpu)) { + void *unprotected_pb = uvm_pushbuffer_get_unprotected_cpu_va_for_push(pushbuffer, push); + UVM_ASSERT(uvm_channel_is_sec2(channel)); + + // Copy push data to unprotected sysmem, it has already been signed. + memcpy(unprotected_pb, push->begin, push_size); + } + + gpu->parent->host_hal->set_gpfifo_entry(gpfifo_entry, pushbuffer_va, push_size, UVM_GPFIFO_SYNC_PROCEED); // Need to make sure all the pushbuffer and the GPFIFO entries writes // complete before updating GPPUT. We also don't want any reads to be moved @@ -408,22 +648,441 @@ } } -static void uvm_channel_semaphore_release(uvm_push_t *push, NvU64 semaphore_va, NvU32 new_payload) +static void do_semaphore_release(uvm_push_t *push, NvU64 semaphore_va, NvU32 new_payload) { uvm_gpu_t *gpu = uvm_push_get_gpu(push); + if (uvm_channel_is_ce(push->channel)) + gpu->parent->ce_hal->semaphore_release(push, semaphore_va, new_payload); + else + gpu->parent->sec2_hal->semaphore_release(push, semaphore_va, new_payload); +} + +static void uvm_channel_tracking_semaphore_release(uvm_push_t *push, NvU64 semaphore_va, NvU32 new_payload) +{ // We used to skip the membar or use membar GPU for the semaphore release // for a few pushes, but that doesn't provide sufficient ordering guarantees // in some cases (e.g. ga100 with an LCE with PCEs from both HSHUBs) for the // semaphore writes. To be safe, just always uses a membar sys for now. - // TODO bug 3770539: Optimize membars used by end of push semaphore releases + // TODO: Bug 3770539: Optimize membars used by end of push semaphore releases (void)uvm_push_get_and_reset_flag(push, UVM_PUSH_FLAG_NEXT_MEMBAR_GPU); (void)uvm_push_get_and_reset_flag(push, UVM_PUSH_FLAG_NEXT_MEMBAR_NONE); - if (uvm_channel_is_ce(push->channel)) - gpu->parent->ce_hal->semaphore_release(push, semaphore_va, new_payload); - else - UVM_ASSERT_MSG(0, "Semaphore release on an unsupported channel.\n"); + do_semaphore_release(push, semaphore_va, new_payload); + + // When the Confidential Computing feature is enabled, additional work + // needs to be scheduled to get an encrypted shadow copy in unprotected + // sysmem. This allows UVM to later decrypt it and observe the new + // semaphore value. + if (uvm_conf_computing_mode_enabled(push->gpu) && uvm_channel_is_ce(push->channel)) + channel_semaphore_gpu_encrypt_payload(push, semaphore_va); +} + +static uvm_channel_t *get_paired_channel(uvm_channel_t *channel) +{ + unsigned index; + uvm_channel_pool_t *paired_pool; + uvm_channel_type_t paired_channel_type; + + UVM_ASSERT(channel); + UVM_ASSERT(uvm_channel_is_wlc(channel) || uvm_channel_is_lcic(channel)); + + index = uvm_channel_index_in_pool(channel); + paired_channel_type = uvm_channel_is_wlc(channel) ? UVM_CHANNEL_TYPE_LCIC : UVM_CHANNEL_TYPE_WLC; + paired_pool = channel->pool->manager->pool_to_use.default_for_type[paired_channel_type]; + return paired_pool->channels + index; +} + +static uvm_channel_t *wlc_get_paired_lcic(uvm_channel_t *wlc_channel) +{ + UVM_ASSERT(wlc_channel); + UVM_ASSERT(uvm_channel_is_wlc(wlc_channel)); + + return get_paired_channel(wlc_channel); +} + +static uvm_channel_t *lcic_get_paired_wlc(uvm_channel_t *lcic_channel) +{ + UVM_ASSERT(lcic_channel); + UVM_ASSERT(uvm_channel_is_lcic(lcic_channel)); + + return get_paired_channel(lcic_channel); +} + +static void internal_channel_submit_work_wlc(uvm_push_t *push) +{ + uvm_channel_t *wlc_channel = push->channel; + uvm_channel_t *lcic_channel = wlc_get_paired_lcic(wlc_channel); + UvmCslIv *iv_cpu_addr = lcic_channel->tracking_sem.semaphore.conf_computing.ivs; + NvU32 *last_pushed_notifier; + NvU32 iv_index; + uvm_spin_loop_t spin; + + UVM_ASSERT(lcic_channel); + + // Wait for the WLC/LCIC to be primed. This means that PUT == GET + 2 + // and a WLC doorbell ring is enough to start work. + UVM_SPIN_WHILE(!uvm_gpu_tracking_semaphore_is_completed(&lcic_channel->tracking_sem), &spin); + + // Executing WLC adds an extra job to LCIC + ++lcic_channel->tracking_sem.queued_value; + + UVM_ASSERT_MSG(uvm_push_get_size(push) == UVM_MAX_WLC_PUSH_SIZE, + "WLC push submission size mismatch, expected: %u, got: %u", + UVM_MAX_WLC_PUSH_SIZE, + uvm_push_get_size(push)); + + // Handles the CPU part of the setup for the LCIC to be able to do GPU + // encryption of its tracking semaphore value. See setup_lcic_schedule(). + last_pushed_notifier = &lcic_channel->tracking_sem.semaphore.conf_computing.last_pushed_notifier; + *lcic_channel->conf_computing.static_notifier_entry_unprotected_sysmem_cpu = ++(*last_pushed_notifier); + *lcic_channel->conf_computing.static_notifier_exit_unprotected_sysmem_cpu = ++(*last_pushed_notifier); + iv_index = (*last_pushed_notifier / 2) % lcic_channel->num_gpfifo_entries; + uvm_conf_computing_log_gpu_encryption(lcic_channel, &iv_cpu_addr[iv_index]); + + // Move push data + uvm_conf_computing_cpu_encrypt(wlc_channel, + wlc_channel->conf_computing.static_pb_unprotected_sysmem_cpu, + push->begin, + &push->launch_iv, + UVM_MAX_WLC_PUSH_SIZE, + wlc_channel->conf_computing.static_pb_unprotected_sysmem_auth_tag_cpu); + + // Make sure all encrypted data is observable before ringing the doorbell. + wmb(); + + // Ring the WLC doorbell to start processing the above push + UVM_GPU_WRITE_ONCE(*wlc_channel->channel_info.workSubmissionOffset, wlc_channel->channel_info.workSubmissionToken); +} + +static void internal_channel_submit_work_indirect_wlc(uvm_push_t *push, NvU32 old_cpu_put, NvU32 new_gpu_put) +{ + uvm_pushbuffer_t *pushbuffer = uvm_channel_get_pushbuffer(push->channel); + uvm_gpu_t *gpu = uvm_push_get_gpu(push); + + uvm_push_t indirect_push; + NV_STATUS status; + NvU64 gpfifo_entry; + + void *push_enc_cpu = uvm_pushbuffer_get_unprotected_cpu_va_for_push(pushbuffer, push); + NvU64 push_enc_gpu = uvm_pushbuffer_get_unprotected_gpu_va_for_push(pushbuffer, push); + void *push_enc_auth_tag; + uvm_gpu_address_t push_enc_auth_tag_gpu; + NvU64 gpfifo_gpu_va = push->channel->channel_info.gpFifoGpuVa + old_cpu_put * sizeof(gpfifo_entry); + + UVM_ASSERT(uvm_channel_is_ce(push->channel)); + UVM_ASSERT(uvm_channel_is_wlc(push->launch_channel)); + + // WLC submissions are done under channel lock, so there should be no + // contention to get the right submission order. + UVM_ASSERT(push->channel->conf_computing.gpu_put == old_cpu_put); + + // This can never stall or return error. WLC launch after WLC channels are + // initialized uses private static pb space and it neither needs the general + // PB space, nor it counts towards max concurrent pushes. + status = uvm_push_begin_on_reserved_channel(push->launch_channel, + &indirect_push, + "Worklaunch to '%s' via '%s'", + push->channel->name, + push->launch_channel->name); + UVM_ASSERT(status == NV_OK); + + + // Move over the pushbuffer data + // WLC channels use a static preallocated space for launch auth tags + push_enc_auth_tag = indirect_push.channel->conf_computing.launch_auth_tag_cpu; + push_enc_auth_tag_gpu = uvm_gpu_address_virtual(indirect_push.channel->conf_computing.launch_auth_tag_gpu_va); + + uvm_conf_computing_cpu_encrypt(indirect_push.channel, + push_enc_cpu, + push->begin, + NULL, + uvm_push_get_size(push), + push_enc_auth_tag); + + uvm_push_set_flag(&indirect_push, UVM_PUSH_FLAG_NEXT_MEMBAR_NONE); + + gpu->parent->ce_hal->decrypt(&indirect_push, + uvm_gpu_address_virtual(uvm_pushbuffer_get_gpu_va_for_push(pushbuffer, push)), + uvm_gpu_address_virtual(push_enc_gpu), + uvm_push_get_size(push), + push_enc_auth_tag_gpu); + + gpu->parent->host_hal->set_gpfifo_entry(&gpfifo_entry, + uvm_pushbuffer_get_gpu_va_for_push(pushbuffer, push), + uvm_push_get_size(push), + UVM_GPFIFO_SYNC_PROCEED); + + gpu->parent->ce_hal->memset_8(&indirect_push, + uvm_gpu_address_virtual(gpfifo_gpu_va), + gpfifo_entry, + sizeof(gpfifo_entry)); + + uvm_push_set_flag(&indirect_push, UVM_PUSH_FLAG_NEXT_MEMBAR_GPU); + do_semaphore_release(&indirect_push, push->channel->channel_info.gpPutGpuVa, new_gpu_put); + + uvm_push_set_flag(&indirect_push, UVM_PUSH_FLAG_NEXT_MEMBAR_GPU); + do_semaphore_release(&indirect_push, + push->channel->channel_info.workSubmissionOffsetGpuVa, + push->channel->channel_info.workSubmissionToken); + + // Ignore return value of push_wait. It can only fail with channel error + // which will be detected when waiting for the primary push. + (void)uvm_push_end_and_wait(&indirect_push); + + push->channel->conf_computing.gpu_put = new_gpu_put; +} + +static void update_gpput_via_sec2(uvm_push_t *sec2_push, uvm_channel_t *channel, NvU32 new_gpu_put) +{ + uvm_gpu_t *gpu = uvm_push_get_gpu(sec2_push); + void *gpput_auth_tag_cpu, *gpput_enc_cpu; + uvm_gpu_address_t gpput_auth_tag_gpu, gpput_enc_gpu; + NvU32 gpput_scratchpad[UVM_CONF_COMPUTING_SEC2_BUF_ALIGNMENT/sizeof(new_gpu_put)]; + + UVM_ASSERT(uvm_channel_is_sec2(sec2_push->channel)); + + gpput_enc_cpu = uvm_push_get_single_inline_buffer(sec2_push, + UVM_CONF_COMPUTING_SEC2_BUF_ALIGNMENT, + UVM_CONF_COMPUTING_SEC2_BUF_ALIGNMENT, + &gpput_enc_gpu); + gpput_auth_tag_cpu = uvm_push_get_single_inline_buffer(sec2_push, + UVM_CONF_COMPUTING_AUTH_TAG_SIZE, + UVM_CONF_COMPUTING_AUTH_TAG_ALIGNMENT, + &gpput_auth_tag_gpu); + + // Update GPPUT. The update needs 4B write to specific offset, + // however we can only do 16B aligned decrypt writes. + // A poison value is written to all other locations, this is ignored in + // most locations and overwritten by HW for GPGET location + memset(gpput_scratchpad, 0, sizeof(gpput_scratchpad)); + UVM_ASSERT(sizeof(*gpput_scratchpad) == sizeof(new_gpu_put)); + gpput_scratchpad[(channel->channel_info.gpPutGpuVa % UVM_CONF_COMPUTING_AUTH_TAG_ALIGNMENT) / + sizeof(*gpput_scratchpad)] = new_gpu_put; + + // Set value of GPGET to be the same as GPPUT. It will be overwritten by + // HW next time GET value changes. UVM never reads GPGET. + // However, RM does read it when freeing a channel. When this function + // is called from 'channel_manager_stop_wlc' we set the value of GPGET + // to the same value as GPPUT. Mismatch between these two values makes + // RM wait for any "pending" tasks, leading to significant delays in the + // channel teardown sequence. + UVM_ASSERT(channel->channel_info.gpPutGpuVa / UVM_CONF_COMPUTING_AUTH_TAG_ALIGNMENT == + channel->channel_info.gpGetGpuVa / UVM_CONF_COMPUTING_AUTH_TAG_ALIGNMENT); + gpput_scratchpad[(channel->channel_info.gpGetGpuVa % UVM_CONF_COMPUTING_AUTH_TAG_ALIGNMENT) / + sizeof(*gpput_scratchpad)] = new_gpu_put; + + uvm_conf_computing_cpu_encrypt(sec2_push->channel, + gpput_enc_cpu, + gpput_scratchpad, + NULL, + sizeof(gpput_scratchpad), + gpput_auth_tag_cpu); + gpu->parent->sec2_hal->decrypt(sec2_push, + UVM_ALIGN_DOWN(channel->channel_info.gpPutGpuVa, + UVM_CONF_COMPUTING_SEC2_BUF_ALIGNMENT), + gpput_enc_gpu.address, + sizeof(gpput_scratchpad), + gpput_auth_tag_gpu.address); +} + +static void set_gpfifo_via_sec2(uvm_push_t *sec2_push, uvm_channel_t *channel, NvU32 put, NvU64 value) +{ + uvm_gpu_t *gpu = uvm_push_get_gpu(sec2_push); + void *gpfifo_auth_tag_cpu, *gpfifo_enc_cpu; + uvm_gpu_address_t gpfifo_auth_tag_gpu, gpfifo_enc_gpu; + NvU64 gpfifo_gpu = channel->channel_info.gpFifoGpuVa + put * sizeof(value); + NvU64 gpfifo_scratchpad[2]; + + UVM_ASSERT(uvm_channel_is_sec2(sec2_push->channel)); + + gpfifo_enc_cpu = uvm_push_get_single_inline_buffer(sec2_push, + sizeof(gpfifo_scratchpad), + UVM_CONF_COMPUTING_SEC2_BUF_ALIGNMENT, + &gpfifo_enc_gpu); + gpfifo_auth_tag_cpu = uvm_push_get_single_inline_buffer(sec2_push, + UVM_CONF_COMPUTING_AUTH_TAG_SIZE, + UVM_CONF_COMPUTING_AUTH_TAG_ALIGNMENT, + &gpfifo_auth_tag_gpu); + + if (IS_ALIGNED(gpfifo_gpu, UVM_CONF_COMPUTING_SEC2_BUF_ALIGNMENT)) { + gpfifo_scratchpad[0] = value; + + // Set the value of the odd entry to noop. + // It will be overwritten when the next entry is submitted. + gpu->parent->host_hal->set_gpfifo_noop(&gpfifo_scratchpad[1]); + } + else { + uvm_gpfifo_entry_t *previous_gpfifo; + + UVM_ASSERT(put > 0); + + previous_gpfifo = &channel->gpfifo_entries[put - 1]; + + if (previous_gpfifo->type == UVM_GPFIFO_ENTRY_TYPE_CONTROL) { + gpfifo_scratchpad[0] = previous_gpfifo->control_value; + } + else { + uvm_pushbuffer_t *pushbuffer = uvm_channel_get_pushbuffer(channel); + NvU64 prev_pb_va = uvm_pushbuffer_get_gpu_va_base(pushbuffer) + previous_gpfifo->pushbuffer_offset; + + // Reconstruct the previous gpfifo entry. UVM_GPFIFO_SYNC_WAIT is + // used only in static WLC schedule. + // Overwriting the previous entry with the same value doesn't hurt, + // whether the previous entry has been processed or not + gpu->parent->host_hal->set_gpfifo_entry(&gpfifo_scratchpad[0], + prev_pb_va, + previous_gpfifo->pushbuffer_size, + UVM_GPFIFO_SYNC_PROCEED); + } + + gpfifo_scratchpad[1] = value; + } + + uvm_conf_computing_cpu_encrypt(sec2_push->channel, + gpfifo_enc_cpu, + gpfifo_scratchpad, + NULL, + sizeof(gpfifo_scratchpad), + gpfifo_auth_tag_cpu); + gpu->parent->sec2_hal->decrypt(sec2_push, + UVM_ALIGN_DOWN(gpfifo_gpu, UVM_CONF_COMPUTING_SEC2_BUF_ALIGNMENT), + gpfifo_enc_gpu.address, + sizeof(gpfifo_scratchpad), + gpfifo_auth_tag_gpu.address); +} + +static NV_STATUS internal_channel_submit_work_indirect_sec2(uvm_push_t *push, NvU32 old_cpu_put, NvU32 new_gpu_put) +{ + uvm_pushbuffer_t *pushbuffer = uvm_channel_get_pushbuffer(push->channel); + uvm_gpu_t *gpu = uvm_push_get_gpu(push); + + uvm_push_t indirect_push; + NV_STATUS status; + NvU64 gpfifo_entry; + + void *push_enc_cpu = uvm_pushbuffer_get_unprotected_cpu_va_for_push(pushbuffer, push); + NvU64 push_enc_gpu = uvm_pushbuffer_get_unprotected_gpu_va_for_push(pushbuffer, push); + void *push_auth_tag_cpu; + uvm_gpu_address_t push_auth_tag_gpu; + uvm_spin_loop_t spin; + + UVM_ASSERT(uvm_channel_is_ce(push->channel)); + UVM_ASSERT(uvm_channel_is_sec2(push->launch_channel)); + + // If the old_cpu_put is not equal to the last gpu put, other pushes are + // pending that need to be submitted. That push/es' submission will update + // the gpu_put pointer to expected value. + UVM_SPIN_WHILE(push->channel->conf_computing.gpu_put != old_cpu_put, &spin); + + // This can never stall or return error. SEC2 launch used during init has + // plenty of PB space available before it needs to check for push + // completion/channel status. WLC launch after WLC channels are initialized + // uses private static pb space and needs neither general PB space, nor it + // counts towards max concurrent pushes. + status = uvm_push_begin_on_reserved_channel(push->launch_channel, + &indirect_push, + "Worklaunch to '%s' via '%s'", + push->channel->name, + push->launch_channel->name); + if (status != NV_OK) + return status; + + + // Move over the pushbuffer data + push_auth_tag_cpu = uvm_push_get_single_inline_buffer(&indirect_push, + UVM_CONF_COMPUTING_AUTH_TAG_SIZE, + UVM_CONF_COMPUTING_AUTH_TAG_ALIGNMENT, + &push_auth_tag_gpu); + + uvm_conf_computing_cpu_encrypt(indirect_push.channel, + push_enc_cpu, + push->begin, + NULL, + uvm_push_get_size(push), + push_auth_tag_cpu); + + uvm_push_set_flag(&indirect_push, UVM_PUSH_FLAG_NEXT_MEMBAR_NONE); + + gpu->parent->sec2_hal->decrypt(&indirect_push, + uvm_pushbuffer_get_gpu_va_for_push(pushbuffer, push), + push_enc_gpu, + uvm_push_get_size(push), + push_auth_tag_gpu.address); + + gpu->parent->host_hal->set_gpfifo_entry(&gpfifo_entry, + uvm_pushbuffer_get_gpu_va_for_push(pushbuffer, push), + uvm_push_get_size(push), + UVM_GPFIFO_SYNC_PROCEED); + + + set_gpfifo_via_sec2(&indirect_push, push->channel, old_cpu_put, gpfifo_entry); + update_gpput_via_sec2(&indirect_push, push->channel, new_gpu_put); + + // Ring the doorbell + uvm_push_set_flag(&indirect_push, UVM_PUSH_FLAG_NEXT_MEMBAR_GPU); + do_semaphore_release(&indirect_push, + push->channel->channel_info.workSubmissionOffsetGpuVa, + push->channel->channel_info.workSubmissionToken); + + status = uvm_push_end_and_wait(&indirect_push); + if (status != NV_OK) + return status; + + push->channel->conf_computing.gpu_put = new_gpu_put; + + return status; +} + +// When the Confidential Computing feature is enabled, the CPU is unable to +// access and read the pushbuffer. This is because it is located in the CPR of +// vidmem in this configuration. This function allows UVM to retrieve the +// content of the pushbuffer in an encrypted form for later decryption, hence, +// simulating the original access pattern. E.g, reading timestamp semaphores. +// See also: decrypt_push(). +static void encrypt_push(uvm_push_t *push) +{ + NvU64 push_protected_gpu_va; + NvU64 push_unprotected_gpu_va; + uvm_gpu_address_t auth_tag_gpu_va; + uvm_channel_t *channel = push->channel; + uvm_push_crypto_bundle_t *crypto_bundle; + uvm_gpu_t *gpu = uvm_push_get_gpu(push); + NvU32 push_size = uvm_push_get_size(push); + uvm_push_info_t *push_info = uvm_push_info_from_push(push); + uvm_pushbuffer_t *pushbuffer = uvm_channel_get_pushbuffer(channel); + unsigned auth_tag_offset = UVM_CONF_COMPUTING_AUTH_TAG_SIZE * push->push_info_index; + + if (!uvm_conf_computing_mode_enabled(gpu)) + return; + + if (!push_info->on_complete) + return; + + if (!uvm_channel_is_ce(channel)) + return; + + if (push_size == 0) + return; + + UVM_ASSERT(!uvm_channel_is_wlc(channel)); + UVM_ASSERT(!uvm_channel_is_lcic(channel)); + UVM_ASSERT(channel->conf_computing.push_crypto_bundles != NULL); + + crypto_bundle = channel->conf_computing.push_crypto_bundles + push->push_info_index; + auth_tag_gpu_va = uvm_rm_mem_get_gpu_va(channel->conf_computing.push_crypto_bundle_auth_tags, gpu, false); + auth_tag_gpu_va.address += auth_tag_offset; + + crypto_bundle->push_size = push_size; + push_protected_gpu_va = uvm_pushbuffer_get_gpu_va_for_push(pushbuffer, push); + push_unprotected_gpu_va = uvm_pushbuffer_get_unprotected_gpu_va_for_push(pushbuffer, push); + + uvm_conf_computing_log_gpu_encryption(channel, &crypto_bundle->iv); + gpu->parent->ce_hal->encrypt(push, + uvm_gpu_address_virtual_unprotected(push_unprotected_gpu_va), + uvm_gpu_address_virtual(push_protected_gpu_va), + push_size, + auth_tag_gpu_va); } void uvm_channel_end_push(uvm_push_t *push) @@ -438,14 +1097,38 @@ NvU32 push_size; NvU32 cpu_put; NvU32 new_cpu_put; + uvm_gpu_t *gpu = uvm_channel_get_gpu(channel); + bool needs_sec2_work_submit = false; + + channel_pool_lock(channel->pool); - uvm_channel_pool_lock(channel->pool); + encrypt_push(push); new_tracking_value = ++channel->tracking_sem.queued_value; new_payload = (NvU32)new_tracking_value; semaphore_va = uvm_channel_tracking_semaphore_get_gpu_va(channel); - uvm_channel_semaphore_release(push, semaphore_va, new_payload); + uvm_channel_tracking_semaphore_release(push, semaphore_va, new_payload); + + if (uvm_channel_is_wlc(channel) && uvm_channel_manager_is_wlc_ready(channel_manager)) { + uvm_channel_t *paired_lcic = wlc_get_paired_lcic(channel); + + gpu->parent->ce_hal->semaphore_reduction_inc(push, + paired_lcic->channel_info.gpPutGpuVa, + paired_lcic->num_gpfifo_entries - 1); + uvm_push_set_flag(push, UVM_PUSH_FLAG_NEXT_MEMBAR_GPU); + do_semaphore_release(push, + paired_lcic->channel_info.workSubmissionOffsetGpuVa, + paired_lcic->channel_info.workSubmissionToken); + + if (uvm_push_get_size(push) < UVM_MAX_WLC_PUSH_SIZE) { + // The UVM_MAX_WLC_PUSH_SIZE is set to fit indirect work launch + // pushes. However, direct pushes to WLC can be smaller than this + // size. This is used e.g. by indirect submission of control + // gpfifo entries. + gpu->parent->host_hal->noop(push, UVM_MAX_WLC_PUSH_SIZE - uvm_push_get_size(push)); + } + } push_size = uvm_push_get_size(push); UVM_ASSERT_MSG(push_size <= UVM_MAX_PUSH_SIZE, "push size %u\n", push_size); @@ -457,16 +1140,37 @@ entry->tracking_semaphore_value = new_tracking_value; entry->pushbuffer_offset = uvm_pushbuffer_get_offset_for_push(pushbuffer, push); entry->pushbuffer_size = push_size; + + // Indirect submission via SEC2/WLC needs pushes to be aligned for + // encryption/decryption. The pushbuffer_size of this push + // influences starting address of the next push. + if (uvm_conf_computing_mode_enabled(gpu)) + entry->pushbuffer_size = UVM_ALIGN_UP(push_size, UVM_CONF_COMPUTING_BUF_ALIGNMENT); entry->push_info = &channel->push_infos[push->push_info_index]; entry->type = UVM_GPFIFO_ENTRY_TYPE_NORMAL; UVM_ASSERT(channel->current_gpfifo_count > 0); --channel->current_gpfifo_count; - if (uvm_channel_is_proxy(channel)) + if (uvm_channel_is_proxy(channel)) { proxy_channel_submit_work(push, push_size); - else + } + else if (uvm_channel_is_wlc(channel) && uvm_channel_manager_is_wlc_ready(channel_manager)) { + internal_channel_submit_work_wlc(push); + } + else if (uvm_conf_computing_mode_enabled(gpu) && uvm_channel_is_ce(channel)) { + if (uvm_channel_manager_is_wlc_ready(channel_manager)) { + internal_channel_submit_work_indirect_wlc(push, cpu_put, new_cpu_put); + } + else { + // submitting via SEC2 starts a push, postpone until this push is + // ended + needs_sec2_work_submit = true; + } + } + else { internal_channel_submit_work(push, push_size, new_cpu_put); + } channel->cpu_put = new_cpu_put; @@ -476,8 +1180,8 @@ // may notice the GPU work to be completed and hence all state tracking the // push must be updated before that. Notably uvm_pushbuffer_end_push() has // to be called first. - uvm_channel_pool_unlock(channel->pool); - unlock_push(channel); + unlock_channel_for_push(channel); + channel_pool_unlock(channel->pool); // This memory barrier is borrowed from CUDA, as it supposedly fixes perf // issues on some systems. Comment from CUDA: "fixes throughput-related @@ -485,22 +1189,112 @@ // bug 124888, which GL works around by doing a clflush" wmb(); + if (needs_sec2_work_submit) { + NV_STATUS status = internal_channel_submit_work_indirect_sec2(push, cpu_put, new_cpu_put); + + // This codepath should only be used during initialization and thus + // NEVER return an error. + UVM_ASSERT(status == NV_OK); + } + push->push_info_index = channel->num_gpfifo_entries; push->channel_tracking_value = new_tracking_value; } +static void submit_ctrl_gpfifo(uvm_channel_t *channel, uvm_gpfifo_entry_t *entry, NvU32 new_cpu_put) +{ + uvm_gpu_t *gpu = uvm_channel_get_gpu(channel); + NvU32 cpu_put = channel->cpu_put; + NvU64 *gpfifo_entry; + + UVM_ASSERT(entry == &channel->gpfifo_entries[cpu_put]); + + if (uvm_conf_computing_mode_enabled(gpu) && uvm_channel_is_ce(channel)) + return; + + gpfifo_entry = (NvU64*)channel->channel_info.gpFifoEntries + cpu_put; + *gpfifo_entry = entry->control_value; + + // Need to make sure all the GPFIFO entries writes complete before updating + // GPPUT. We also don't want any reads to be moved after the GPPut write as + // the GPU might modify the data they read as soon as the GPPut write + // happens. + mb(); + + gpu->parent->host_hal->write_gpu_put(channel, new_cpu_put); +} + +static NV_STATUS submit_ctrl_gpfifo_indirect(uvm_channel_t *channel, + uvm_gpfifo_entry_t *entry, + NvU32 old_cpu_put, + NvU32 new_gpu_put) +{ + uvm_push_t indirect_push; + NV_STATUS status = NV_OK; + uvm_spin_loop_t spin; + uvm_channel_type_t indirect_channel_type = uvm_channel_manager_is_wlc_ready(channel->pool->manager) ? + UVM_CHANNEL_TYPE_WLC : + UVM_CHANNEL_TYPE_SEC2; + + UVM_ASSERT(uvm_channel_is_ce(channel)); + + // If the old_cpu_put is not equal to the last gpu put, + // Another push(es) is pending that needs to be submitted. + // That push/es' submission will update the gpu_put pointer + // to expected value. + UVM_SPIN_WHILE(channel->conf_computing.gpu_put != old_cpu_put, &spin); + + status = uvm_push_begin(channel->pool->manager, + indirect_channel_type, + &indirect_push, + "GPFIFO submit to '%s' via '%s'", + channel->name, + uvm_channel_type_to_string(indirect_channel_type)); + if (status != NV_OK) + return status; + + if (uvm_channel_is_sec2(indirect_push.channel)) { + set_gpfifo_via_sec2(&indirect_push, channel, old_cpu_put, entry->control_value); + update_gpput_via_sec2(&indirect_push, channel, new_gpu_put); + } else { + uvm_gpu_t *gpu = uvm_push_get_gpu(&indirect_push); + NvU64 gpfifo_gpu_va = channel->channel_info.gpFifoGpuVa + (old_cpu_put * sizeof(entry->control_value)); + + gpu->parent->ce_hal->memset_8(&indirect_push, + uvm_gpu_address_virtual(gpfifo_gpu_va), + entry->control_value, + sizeof(entry->control_value)); + + uvm_push_set_flag(&indirect_push, UVM_PUSH_FLAG_NEXT_MEMBAR_GPU); + do_semaphore_release(&indirect_push, channel->channel_info.gpPutGpuVa, new_gpu_put); + } + + uvm_push_set_flag(&indirect_push, UVM_PUSH_FLAG_NEXT_MEMBAR_GPU); + do_semaphore_release(&indirect_push, + channel->channel_info.workSubmissionOffsetGpuVa, + channel->channel_info.workSubmissionToken); + + status = uvm_push_end_and_wait(&indirect_push); + if (status != NV_OK) + return status; + + channel->conf_computing.gpu_put = new_gpu_put; + + return NV_OK; +} + // The caller must submit a normal GPFIFO entry with a semaphore release // following the control GPFIFO, refer to uvm_channel_write_ctrl_gpfifo() for an // example. static void write_ctrl_gpfifo(uvm_channel_t *channel, NvU64 ctrl_fifo_entry_value) { uvm_gpfifo_entry_t *entry; - NvU64 *gpfifo_entry; NvU32 cpu_put; NvU32 new_cpu_put; - uvm_gpu_t *gpu = channel->pool->manager->gpu; + bool needs_indirect_submit = false; + uvm_gpu_t *gpu = uvm_channel_get_gpu(channel); - uvm_channel_pool_lock(channel->pool); + channel_pool_lock(channel->pool); cpu_put = channel->cpu_put; new_cpu_put = (cpu_put + 1) % channel->num_gpfifo_entries; @@ -508,6 +1302,7 @@ entry = &channel->gpfifo_entries[cpu_put]; memset(entry, 0, sizeof(*entry)); entry->type = UVM_GPFIFO_ENTRY_TYPE_CONTROL; + entry->control_value = ctrl_fifo_entry_value; // Control GPFIFO entries are followed by a semaphore_release push in UVM. // We add the tracking semaphore value of the next GPFIFO entry, @@ -519,24 +1314,25 @@ UVM_ASSERT(channel->current_gpfifo_count > 1); --channel->current_gpfifo_count; - gpfifo_entry = (NvU64*)channel->channel_info.gpFifoEntries + cpu_put; - *gpfifo_entry = ctrl_fifo_entry_value; - - // Need to make sure all the GPFIFO entries writes complete before updating - // GPPUT. We also don't want any reads to be moved after the GPPut write as - // the GPU might modify the data they read as soon as the GPPut write - // happens. - mb(); - - gpu->parent->host_hal->write_gpu_put(channel, new_cpu_put); + submit_ctrl_gpfifo(channel, entry, new_cpu_put); + if (uvm_conf_computing_mode_enabled(gpu) && uvm_channel_is_ce(channel)) + needs_indirect_submit = true; channel->cpu_put = new_cpu_put; // The moment the channel is unlocked uvm_channel_update_progress_with_max() // may notice the GPU work to be completed and hence all state tracking the - // push must be updated before that. - uvm_channel_pool_unlock(channel->pool); - unlock_push(channel); + // push must be updated before that. Note that we do not call + // unlock_channel_for_push() because a control GPFIFO is followed by a + // semaphore release, where the channel is unlocked. + channel_pool_unlock(channel->pool); + + if (needs_indirect_submit) { + NV_STATUS status = submit_ctrl_gpfifo_indirect(channel, entry, cpu_put, new_cpu_put); + + // All failures are globally fatal. There's nothing we do to recover. + UVM_ASSERT_RELEASE(status == NV_OK); + } // This memory barrier is borrowed from CUDA, as it supposedly fixes perf // issues on some systems. Comment from CUDA: "fixes throughput-related @@ -553,6 +1349,11 @@ UVM_ASSERT(!uvm_channel_is_proxy(channel)); + // WLC/LCIC channels can only process custom gpfifo entries before + // their schedule is set up. + UVM_ASSERT(!uvm_channel_is_lcic(channel) || !uvm_channel_manager_is_wlc_ready(channel->pool->manager)); + UVM_ASSERT(!uvm_channel_is_wlc(channel) || !uvm_channel_manager_is_wlc_ready(channel->pool->manager)); + // We reserve two GPFIFO entries, i.e., the control GPFIFO entry and the // subsequent semaphore_release push. There is, however, a potential case // for GPFIFO control submission starvation. This may happen because a @@ -587,13 +1388,65 @@ return NV_OK; } +static NV_STATUS channel_reserve_and_lock(uvm_channel_t *channel, NvU32 num_gpfifo_entries) +{ + uvm_spin_loop_t spin; + uvm_channel_pool_t *pool = channel->pool; + + // This semaphore is uvm_up() in unlock_channel_for_push() as part of the + // uvm_channel_end_push() routine. Note that different than in + // channel_reserve_and_lock_in_pool, we cannot pick an unlocked channel from + // the pool, even when there is one available and *channel is locked. + // Not a concern given that uvm_channel_reserve() is not the common-case for + // channel reservation, and only used for channel initialization, GPFIFO + // control work submission, and testing. + uvm_down(&pool->push_sem); + + channel_pool_lock(pool); + + if (test_claim_and_lock_channel(channel, num_gpfifo_entries)) + goto out; + + channel_pool_unlock(pool); + + uvm_spin_loop_init(&spin); + while (1) { + NV_STATUS status; + + uvm_channel_update_progress(channel); + + channel_pool_lock(pool); + + if (test_claim_and_lock_channel(channel, num_gpfifo_entries)) + goto out; + + channel_pool_unlock(pool); + + status = uvm_channel_check_errors(channel); + if (status != NV_OK) { + uvm_up(&pool->push_sem); + return status; + } + + UVM_SPIN_LOOP(&spin); + } + +out: + channel_pool_unlock(pool); + return NV_OK; +} + NV_STATUS uvm_channel_reserve(uvm_channel_t *channel, NvU32 num_gpfifo_entries) { NV_STATUS status = NV_OK; uvm_spin_loop_t spin; + uvm_gpu_t *gpu = uvm_channel_get_gpu(channel); + + if (uvm_conf_computing_mode_enabled(gpu)) + return channel_reserve_and_lock(channel, num_gpfifo_entries); if (try_claim_channel(channel, num_gpfifo_entries)) - goto out; + return NV_OK; uvm_channel_update_progress(channel); @@ -604,10 +1457,6 @@ uvm_channel_update_progress(channel); } -out: - if (status == NV_OK) - lock_push(channel); - return status; } @@ -621,12 +1470,12 @@ if (pending_count == 0) return NULL; - uvm_channel_pool_lock(channel->pool); + channel_pool_lock(channel->pool); if (channel->gpu_get != channel->cpu_put) entry = &channel->gpfifo_entries[channel->gpu_get]; - uvm_channel_pool_unlock(channel->pool); + channel_pool_unlock(channel->pool); return entry; } @@ -687,13 +1536,10 @@ push_info->function); } else { - NvU64 *gpfifo_entry; - UVM_ASSERT(!uvm_channel_is_proxy(channel)); - gpfifo_entry = (NvU64*)channel->channel_info.gpFifoEntries + (fatal_entry - channel->gpfifo_entries); UVM_ERR_PRINT("Channel error likely caused by GPFIFO control entry, data: 0x%llx, gpu_get: %d\n", - *gpfifo_entry, + fatal_entry->control_value, channel->gpu_get); } } @@ -734,8 +1580,234 @@ return uvm_gpu_tracking_semaphore_update_completed_value(&channel->tracking_sem); } +static NV_STATUS csl_init(uvm_channel_t *channel) +{ + NV_STATUS status; + uvm_gpu_t *gpu = uvm_channel_get_gpu(channel); + + UVM_ASSERT(uvm_conf_computing_mode_enabled(gpu)); + + uvm_mutex_init(&channel->csl.ctx_lock, UVM_LOCK_ORDER_LEAF); + + status = uvm_rm_locked_call(nvUvmInterfaceCslInitContext(&channel->csl.ctx, channel->handle)); + if (status == NV_OK) { + channel->csl.is_ctx_initialized = true; + } + else { + UVM_DBG_PRINT("nvUvmInterfaceCslInitContext() failed: %s, GPU %s\n", + nvstatusToString(status), + uvm_gpu_name(gpu)); + } + + return status; +} + +static void csl_destroy(uvm_channel_t *channel) +{ + if (!channel->csl.is_ctx_initialized) + return; + + uvm_assert_mutex_unlocked(&channel->csl.ctx_lock); + UVM_ASSERT(!is_channel_locked_for_push(channel)); + + uvm_rm_locked_call_void(nvUvmInterfaceDeinitCslContext(&channel->csl.ctx)); + channel->csl.is_ctx_initialized = false; +} + +static void free_conf_computing_buffers(uvm_channel_t *channel) +{ + uvm_gpu_t *gpu = uvm_channel_get_gpu(channel); + + UVM_ASSERT(uvm_conf_computing_mode_enabled(gpu)); + UVM_ASSERT(uvm_channel_is_ce(channel)); + + uvm_rm_mem_free(channel->conf_computing.static_pb_protected_vidmem); + uvm_rm_mem_free(channel->conf_computing.static_pb_unprotected_sysmem); + uvm_rm_mem_free(channel->conf_computing.static_notifier_unprotected_sysmem); + uvm_rm_mem_free(channel->conf_computing.push_crypto_bundle_auth_tags); + uvm_kvfree(channel->conf_computing.static_pb_protected_sysmem); + uvm_kvfree(channel->conf_computing.push_crypto_bundles); + channel->conf_computing.static_pb_protected_vidmem = NULL; + channel->conf_computing.static_pb_unprotected_sysmem = NULL; + channel->conf_computing.static_notifier_unprotected_sysmem = NULL; + channel->conf_computing.push_crypto_bundle_auth_tags = NULL; + channel->conf_computing.static_pb_protected_sysmem = NULL; + channel->conf_computing.push_crypto_bundles = NULL; + + uvm_rm_mem_free(channel->tracking_sem.semaphore.conf_computing.encrypted_payload); + uvm_rm_mem_free(channel->tracking_sem.semaphore.conf_computing.notifier); + uvm_rm_mem_free(channel->tracking_sem.semaphore.conf_computing.auth_tag); + uvm_kvfree(channel->tracking_sem.semaphore.conf_computing.ivs); + channel->tracking_sem.semaphore.conf_computing.encrypted_payload = NULL; + channel->tracking_sem.semaphore.conf_computing.notifier = NULL; + channel->tracking_sem.semaphore.conf_computing.auth_tag = NULL; + channel->tracking_sem.semaphore.conf_computing.ivs = NULL; +} + +static NV_STATUS alloc_conf_computing_buffers_semaphore(uvm_channel_t *channel) +{ + uvm_gpu_semaphore_t *semaphore = &channel->tracking_sem.semaphore; + uvm_gpu_t *gpu = uvm_channel_get_gpu(channel); + NV_STATUS status; + + UVM_ASSERT(uvm_conf_computing_mode_enabled(gpu)); + UVM_ASSERT(uvm_channel_is_ce(channel)); + + status = uvm_rm_mem_alloc_and_map_cpu(gpu, + UVM_RM_MEM_TYPE_SYS, + sizeof(semaphore->conf_computing.last_pushed_notifier), + UVM_CONF_COMPUTING_BUF_ALIGNMENT, + &semaphore->conf_computing.notifier); + + if (status != NV_OK) + return status; + + status = uvm_rm_mem_alloc_and_map_cpu(gpu, + UVM_RM_MEM_TYPE_SYS, + sizeof(*channel->tracking_sem.semaphore.payload), + UVM_CONF_COMPUTING_BUF_ALIGNMENT, + &semaphore->conf_computing.encrypted_payload); + + if (status != NV_OK) + return status; + + status = uvm_rm_mem_alloc_and_map_cpu(gpu, + UVM_RM_MEM_TYPE_SYS, + UVM_CONF_COMPUTING_AUTH_TAG_SIZE, + UVM_CONF_COMPUTING_BUF_ALIGNMENT, + &semaphore->conf_computing.auth_tag); + + if (status != NV_OK) + return status; + + semaphore->conf_computing.ivs = uvm_kvmalloc_zero(sizeof(*semaphore->conf_computing.ivs) + * channel->num_gpfifo_entries); + + if (!semaphore->conf_computing.ivs) + return NV_ERR_NO_MEMORY; + + return status; +} + +static NV_STATUS alloc_conf_computing_buffers_wlc(uvm_channel_t *channel) +{ + uvm_gpu_t *gpu = uvm_channel_get_gpu(channel); + size_t aligned_wlc_push_size = UVM_ALIGN_UP(UVM_MAX_WLC_PUSH_SIZE, UVM_CONF_COMPUTING_AUTH_TAG_ALIGNMENT); + NV_STATUS status = uvm_rm_mem_alloc_and_map_cpu(gpu, + UVM_RM_MEM_TYPE_SYS, + aligned_wlc_push_size + UVM_CONF_COMPUTING_AUTH_TAG_SIZE * 2, + PAGE_SIZE, + &channel->conf_computing.static_pb_unprotected_sysmem); + if (status != NV_OK) + return status; + + // Both pushes will be targets for SEC2 decrypt operations and have to + // be aligned for SEC2. The first push location will also be a target + // for CE decrypt operation and has to be aligned for CE decrypt. + status = uvm_rm_mem_alloc(gpu, + UVM_RM_MEM_TYPE_GPU, + UVM_ALIGN_UP(UVM_MAX_WLC_PUSH_SIZE, UVM_CONF_COMPUTING_SEC2_BUF_ALIGNMENT) * 2, + UVM_CONF_COMPUTING_BUF_ALIGNMENT, + &channel->conf_computing.static_pb_protected_vidmem); + if (status != NV_OK) + return status; + + channel->conf_computing.static_pb_unprotected_sysmem_cpu = + uvm_rm_mem_get_cpu_va(channel->conf_computing.static_pb_unprotected_sysmem); + channel->conf_computing.static_pb_unprotected_sysmem_auth_tag_cpu = + (char*)channel->conf_computing.static_pb_unprotected_sysmem_cpu + aligned_wlc_push_size; + + // The location below is only used for launch pushes but reuses + // the same sysmem allocation + channel->conf_computing.launch_auth_tag_cpu = + (char*)channel->conf_computing.static_pb_unprotected_sysmem_cpu + + aligned_wlc_push_size + UVM_CONF_COMPUTING_AUTH_TAG_SIZE; + channel->conf_computing.launch_auth_tag_gpu_va = + uvm_rm_mem_get_gpu_uvm_va(channel->conf_computing.static_pb_unprotected_sysmem, gpu) + + aligned_wlc_push_size + UVM_CONF_COMPUTING_AUTH_TAG_SIZE; + + channel->conf_computing.static_pb_protected_sysmem = uvm_kvmalloc(UVM_MAX_WLC_PUSH_SIZE + UVM_PAGE_SIZE_4K); + if (!channel->conf_computing.static_pb_protected_sysmem) + return NV_ERR_NO_MEMORY; + + return status; +} + +static NV_STATUS alloc_conf_computing_buffers_lcic(uvm_channel_t *channel) +{ + uvm_gpu_t *gpu = uvm_channel_get_gpu(channel); + const size_t notifier_size = sizeof(*channel->conf_computing.static_notifier_entry_unprotected_sysmem_cpu); + NV_STATUS status = uvm_rm_mem_alloc_and_map_cpu(gpu, + UVM_RM_MEM_TYPE_SYS, + notifier_size * 2, + UVM_CONF_COMPUTING_BUF_ALIGNMENT, + &channel->conf_computing.static_notifier_unprotected_sysmem); + if (status != NV_OK) + return status; + + status = uvm_rm_mem_alloc(gpu, + UVM_RM_MEM_TYPE_GPU, + UVM_LCIC_PUSH_SIZE, + UVM_CONF_COMPUTING_BUF_ALIGNMENT, + &channel->conf_computing.static_pb_protected_vidmem); + if (status != NV_OK) + return status; + + channel->conf_computing.static_notifier_entry_unprotected_sysmem_cpu = + uvm_rm_mem_get_cpu_va(channel->conf_computing.static_notifier_unprotected_sysmem); + channel->conf_computing.static_notifier_exit_unprotected_sysmem_cpu = + channel->conf_computing.static_notifier_entry_unprotected_sysmem_cpu + 1; + + channel->conf_computing.static_notifier_entry_unprotected_sysmem_gpu_va = + uvm_rm_mem_get_gpu_va(channel->conf_computing.static_notifier_unprotected_sysmem, gpu, false); + channel->conf_computing.static_notifier_exit_unprotected_sysmem_gpu_va = + channel->conf_computing.static_notifier_entry_unprotected_sysmem_gpu_va; + channel->conf_computing.static_notifier_exit_unprotected_sysmem_gpu_va.address += notifier_size; + + return status; +} + +static NV_STATUS alloc_conf_computing_buffers(uvm_channel_t *channel) +{ + NV_STATUS status; + uvm_gpu_t *gpu = uvm_channel_get_gpu(channel); + + UVM_ASSERT(uvm_conf_computing_mode_enabled(gpu)); + UVM_ASSERT(uvm_channel_is_ce(channel)); + + status = alloc_conf_computing_buffers_semaphore(channel); + if (status != NV_OK) + return status; + + if (uvm_channel_is_wlc(channel)) { + status = alloc_conf_computing_buffers_wlc(channel); + } + else if (uvm_channel_is_lcic(channel)) { + status = alloc_conf_computing_buffers_lcic(channel); + } + else { + void *push_crypto_bundles = uvm_kvmalloc_zero(sizeof(*channel->conf_computing.push_crypto_bundles) * + channel->num_gpfifo_entries); + + if (push_crypto_bundles == NULL) + return NV_ERR_NO_MEMORY; + + channel->conf_computing.push_crypto_bundles = push_crypto_bundles; + + status = uvm_rm_mem_alloc_and_map_cpu(gpu, + UVM_RM_MEM_TYPE_SYS, + channel->num_gpfifo_entries * UVM_CONF_COMPUTING_AUTH_TAG_SIZE, + UVM_CONF_COMPUTING_BUF_ALIGNMENT, + &channel->conf_computing.push_crypto_bundle_auth_tags); + } + + return status; +} + static void channel_destroy(uvm_channel_pool_t *pool, uvm_channel_t *channel) { + uvm_gpu_t *gpu = uvm_channel_get_gpu(channel); + UVM_ASSERT(pool->num_channels > 0); if (channel->tracking_sem.queued_value > 0) { @@ -759,6 +1831,13 @@ uvm_kvfree(channel->gpfifo_entries); + if (uvm_conf_computing_mode_enabled(gpu)) { + csl_destroy(channel); + + if (uvm_channel_is_ce(channel)) + free_conf_computing_buffers(channel); + } + if (uvm_channel_is_proxy(channel)) uvm_rm_locked_call_void(nvUvmInterfacePagingChannelDestroy(channel->proxy.handle)); else @@ -772,7 +1851,56 @@ pool->num_channels--; } -static NV_STATUS internal_channel_create(uvm_channel_t *channel, unsigned engine_index) +static unsigned channel_pool_type_num_gpfifo_entries(uvm_channel_manager_t *manager, uvm_channel_pool_type_t pool_type) +{ + switch (pool_type) { + case UVM_CHANNEL_POOL_TYPE_CE: + case UVM_CHANNEL_POOL_TYPE_CE_PROXY: + return manager->conf.num_gpfifo_entries; + case UVM_CHANNEL_POOL_TYPE_SEC2: + return manager->conf.num_gpfifo_entries; + case UVM_CHANNEL_POOL_TYPE_WLC: { + // WLC benefits from larger number of entries since more available + // entries result in less frequent calls to + // uvm_channel_update_progress 16 is the maximum size that can + // re-use static pb preallocated memory when uploading the WLC + // schedule. + return 16; + } + case UVM_CHANNEL_POOL_TYPE_LCIC: { + // Every channel needs at least 3 entries; 1 for sentinel and 2 more + // for submitting GPFIFO control entries. The number also has to be + // power of 2, as the HW stores the size as log2 value. + // LCIC does not accept external pushes, uvm_channel_update_progress + // is not a concern. + return 4; + } + default: + UVM_ASSERT_MSG(0, "Unhandled pool type: %d", pool_type); + return 0; + } +} + +// Returns the TSG for a given channel. +static uvmGpuTsgHandle channel_get_tsg(uvm_channel_t *channel) +{ + unsigned tsg_index = 0; + uvm_channel_pool_t *pool = channel->pool; + + if (uvm_channel_pool_is_wlc(pool) || uvm_channel_pool_is_lcic(pool)) { + if (uvm_channel_pool_is_lcic(pool)) { + channel = lcic_get_paired_wlc(channel); + pool = channel->pool; + } + + tsg_index = uvm_channel_index_in_pool(channel); + } + UVM_ASSERT(tsg_index < pool->num_tsgs); + + return pool->tsg_handles[tsg_index]; +} + +static NV_STATUS internal_channel_create(uvm_channel_t *channel) { NV_STATUS status; UvmGpuChannelAllocParams channel_alloc_params; @@ -780,27 +1908,28 @@ uvm_channel_manager_t *manager = channel->pool->manager; uvm_gpu_t *gpu = manager->gpu; - if (uvm_channel_is_ce(channel)) { - UVM_ASSERT(channel->pool->pool_type == UVM_CHANNEL_POOL_TYPE_CE); - } - memset(&channel_alloc_params, 0, sizeof(channel_alloc_params)); - channel_alloc_params.numGpFifoEntries = manager->conf.num_gpfifo_entries; + channel_alloc_params.numGpFifoEntries = channel_pool_type_num_gpfifo_entries(manager, channel->pool->pool_type); channel_alloc_params.gpFifoLoc = manager->conf.gpfifo_loc; channel_alloc_params.gpPutLoc = manager->conf.gpput_loc; - channel_alloc_params.engineIndex = engine_index; - if (uvm_channel_is_ce(channel)) - channel_alloc_params.engineType = UVM_GPU_CHANNEL_ENGINE_TYPE_CE; + if (uvm_channel_is_sec2(channel)) { + UVM_ASSERT(uvm_conf_computing_mode_enabled(gpu)); + + // SEC2 channels' GPPUT and GPFIFO must be allocated in sysmem. + channel_alloc_params.gpFifoLoc = UVM_BUFFER_LOCATION_SYS; + channel_alloc_params.gpPutLoc = UVM_BUFFER_LOCATION_SYS; + } - status = uvm_rm_locked_call(nvUvmInterfaceChannelAllocate(gpu->rm_address_space, + status = uvm_rm_locked_call(nvUvmInterfaceChannelAllocate(channel_get_tsg(channel), &channel_alloc_params, &channel->handle, channel_info)); if (status != NV_OK) { - UVM_ERR_PRINT("nvUvmInterfaceChannelAllocate() failed: %s, GPU %s\n", + UVM_ERR_PRINT("nvUvmInterfaceChannelAllocate() failed: %s, GPU %s, type %s\n", nvstatusToString(status), - uvm_gpu_name(gpu)); + uvm_gpu_name(gpu), + uvm_channel_pool_type_to_string(channel->pool->pool_type)); return status; } @@ -811,8 +1940,10 @@ channel_info->hwChannelId, channel_info->hwRunlistId, channel_info->hwChannelId, - "CE", - engine_index); + uvm_channel_is_sec2(channel) ? "SEC2" : + uvm_channel_is_wlc(channel) ? "WLC" : + uvm_channel_is_lcic(channel) ? "LCIC" : "CE", + channel->pool->engine_index); return NV_OK; } @@ -852,6 +1983,7 @@ NV_STATUS status; uvm_channel_manager_t *manager = pool->manager; uvm_gpu_t *gpu = manager->gpu; + uvm_gpu_semaphore_pool_t *semaphore_pool = gpu->semaphore_pool; unsigned int i; UVM_ASSERT(channel != NULL); @@ -862,7 +1994,10 @@ channel->tools.pending_event_count = 0; INIT_LIST_HEAD(&channel->tools.channel_list_node); - status = uvm_gpu_tracking_semaphore_alloc(gpu->semaphore_pool, &channel->tracking_sem); + if (uvm_conf_computing_mode_enabled(gpu) && uvm_channel_is_ce(channel)) + semaphore_pool = gpu->secure_semaphore_pool; + + status = uvm_gpu_tracking_semaphore_alloc(semaphore_pool, &channel->tracking_sem); if (status != NV_OK) { UVM_ERR_PRINT("uvm_gpu_tracking_semaphore_alloc() failed: %s, GPU %s\n", nvstatusToString(status), @@ -873,18 +2008,32 @@ if (uvm_channel_is_proxy(channel)) status = proxy_channel_create(channel, pool->engine_index); else - status = internal_channel_create(channel, pool->engine_index); + status = internal_channel_create(channel); if (status != NV_OK) goto error; - channel->num_gpfifo_entries = manager->conf.num_gpfifo_entries; + channel->num_gpfifo_entries = channel_pool_type_num_gpfifo_entries(manager, pool->pool_type); channel->gpfifo_entries = uvm_kvmalloc_zero(sizeof(*channel->gpfifo_entries) * channel->num_gpfifo_entries); if (channel->gpfifo_entries == NULL) { status = NV_ERR_NO_MEMORY; goto error; } + if (uvm_conf_computing_mode_enabled(gpu)) { + status = csl_init(channel); + if (status != NV_OK) + goto error; + + if (uvm_channel_is_ce(channel)) { + // Must happen after the channel's num_gpfifo_entries is known, as + // UVM needs one IV slot per GPFIFO entry. + status = alloc_conf_computing_buffers(channel); + if (status != NV_OK) + goto error; + } + } + channel->push_infos = uvm_kvmalloc_zero(sizeof(*channel->push_infos) * channel->num_gpfifo_entries); if (channel->push_infos == NULL) { status = NV_ERR_NO_MEMORY; @@ -923,7 +2072,7 @@ return uvm_gpu_semaphore_get_gpu_va(semaphore, gpu, uvm_channel_is_proxy(access_channel)); } -static NV_STATUS init_channel(uvm_channel_t *channel) +static NV_STATUS channel_init(uvm_channel_t *channel) { uvm_push_t push; uvm_gpu_t *gpu = uvm_channel_get_gpu(channel); @@ -939,9 +2088,15 @@ if (uvm_gpu_has_pushbuffer_segments(gpu)) { NvU64 gpfifo_entry; - uvm_pushbuffer_t *pushbuffer = channel->pool->manager->pushbuffer; - gpu->parent->host_hal->set_gpfifo_pushbuffer_segment_base(&gpfifo_entry, - uvm_pushbuffer_get_gpu_va_base(pushbuffer)); + uvm_pushbuffer_t *pushbuffer = uvm_channel_get_pushbuffer(channel); + NvU64 pb_base = uvm_pushbuffer_get_gpu_va_base(pushbuffer); + + if (uvm_channel_is_sec2(channel)) + pb_base = uvm_pushbuffer_get_sec2_gpu_va_base(pushbuffer); + else if (channel->conf_computing.static_pb_protected_vidmem) + pb_base = uvm_rm_mem_get_gpu_uvm_va(channel->conf_computing.static_pb_protected_vidmem, gpu); + + gpu->parent->host_hal->set_gpfifo_pushbuffer_segment_base(&gpfifo_entry, pb_base); write_ctrl_gpfifo(channel, gpfifo_entry); } @@ -953,12 +2108,18 @@ if (uvm_channel_is_ce(channel)) gpu->parent->ce_hal->init(&push); + else + gpu->parent->sec2_hal->init(&push); gpu->parent->host_hal->init(&push); status = uvm_push_end_and_wait(&push); - if (status != NV_OK) - UVM_ERR_PRINT("Channel init failed: %s, GPU %s\n", nvstatusToString(status), uvm_gpu_name(gpu)); + if (status != NV_OK) { + UVM_ERR_PRINT("Channel '%s' init failed: %s, GPU %s\n", + channel->name, + nvstatusToString(status), + uvm_gpu_name(gpu)); + } return status; } @@ -978,17 +2139,88 @@ if (pool_type == UVM_CHANNEL_POOL_TYPE_CE_PROXY) return 1; + // Not all GPU architectures support more than 1 channel per TSG. Since SEC2 + // is not in UVM critical path for performance, we conservatively create a + // pool/TSG with a single channel. + if (pool_type == UVM_CHANNEL_POOL_TYPE_SEC2) + return 1; + + if (pool_type == UVM_CHANNEL_POOL_TYPE_WLC || pool_type == UVM_CHANNEL_POOL_TYPE_LCIC) + return UVM_PUSH_MAX_CONCURRENT_PUSHES; + return 2; } +// Number of TSGs to create in a pool of a given type. +static unsigned channel_pool_type_num_tsgs(uvm_channel_pool_type_t pool_type) +{ + // For WLC and LCIC channels, we create one TSG per WLC/LCIC channel pair. + // The TSG is stored in the WLC pool. + if (pool_type == UVM_CHANNEL_POOL_TYPE_WLC) + return channel_pool_type_num_channels(pool_type); + else if (pool_type == UVM_CHANNEL_POOL_TYPE_LCIC) + return 0; + + return 1; +} + +static UVM_GPU_CHANNEL_ENGINE_TYPE pool_type_to_engine_type(uvm_channel_pool_type_t pool_type) +{ + if (pool_type == UVM_CHANNEL_POOL_TYPE_SEC2) + return UVM_GPU_CHANNEL_ENGINE_TYPE_SEC2; + return UVM_GPU_CHANNEL_ENGINE_TYPE_CE; +} + +static void tsg_destroy(uvm_channel_pool_t *pool, uvmGpuTsgHandle tsg_handle) +{ + UVM_ASSERT(pool->num_tsgs > 0); + + uvm_rm_locked_call_void(nvUvmInterfaceTsgDestroy(tsg_handle)); + pool->num_tsgs--; +} + +static NV_STATUS tsg_create(uvm_channel_pool_t *pool, uvmGpuTsgHandle *tsg_handle) +{ + NV_STATUS status; + UvmGpuTsgAllocParams tsg_alloc_params; + uvm_gpu_t *gpu = pool->manager->gpu; + + pool->num_tsgs++; + + tsg_alloc_params.engineType = pool_type_to_engine_type(pool->pool_type); + tsg_alloc_params.engineIndex = pool->engine_index; + + status = uvm_rm_locked_call(nvUvmInterfaceTsgAllocate(gpu->rm_address_space, &tsg_alloc_params, tsg_handle)); + if (status != NV_OK) { + UVM_ERR_PRINT("nvUvmInterfaceTsgAllocate() failed: %s, GPU %s, type %s\n", + nvstatusToString(status), + uvm_gpu_name(gpu), + uvm_channel_pool_type_to_string(pool->pool_type)); + goto error; + } + + return NV_OK; + +error: + tsg_destroy(pool, *tsg_handle); + + return status; +} + static void channel_pool_destroy(uvm_channel_pool_t *pool) { UVM_ASSERT(pool->manager->num_channel_pools > 0); while (pool->num_channels > 0) channel_destroy(pool, pool->channels + pool->num_channels - 1); - uvm_kvfree(pool->channels); + pool->channels = NULL; + + while (pool->num_tsgs > 0) + tsg_destroy(pool, *(pool->tsg_handles + pool->num_tsgs - 1)); + uvm_kvfree(pool->tsg_handles); + pool->tsg_handles = NULL; + pool->manager->num_channel_pools--; } @@ -1000,22 +2232,56 @@ NV_STATUS status; unsigned i; unsigned num_channels; + unsigned num_tsgs; uvm_channel_pool_t *pool; + UVM_ASSERT(uvm_pool_type_is_valid(pool_type)); + pool = channel_manager->channel_pools + channel_manager->num_channel_pools; + channel_manager->num_channel_pools++; + pool->manager = channel_manager; pool->engine_index = engine_index; pool->pool_type = pool_type; + num_tsgs = channel_pool_type_num_tsgs(pool_type); + if (num_tsgs != 0) { + pool->tsg_handles = uvm_kvmalloc_zero(sizeof(*pool->tsg_handles) * num_tsgs); + if (!pool->tsg_handles) { + status = NV_ERR_NO_MEMORY; + goto error; + } + + for (i = 0; i < num_tsgs; i++) { + uvmGpuTsgHandle *tsg_handle = pool->tsg_handles + i; + + status = tsg_create(pool, tsg_handle); + if (status != NV_OK) + goto error; + } + } + channel_pool_lock_init(pool); num_channels = channel_pool_type_num_channels(pool_type); + UVM_ASSERT(num_channels <= UVM_CHANNEL_MAX_NUM_CHANNELS_PER_POOL); - pool->channels = uvm_kvmalloc_zero(sizeof(*pool->channels) * num_channels); - if (!pool->channels) - return NV_ERR_NO_MEMORY; + if (uvm_conf_computing_mode_enabled(channel_manager->gpu)) { + // Use different order lock for SEC2 and WLC channels. + // This allows reserving a SEC2 or WLC channel for indirect work + // submission while holding a reservation for a channel. + uvm_lock_order_t order = uvm_channel_pool_is_sec2(pool) ? UVM_LOCK_ORDER_CSL_SEC2_PUSH : + (uvm_channel_pool_is_wlc(pool) ? UVM_LOCK_ORDER_CSL_WLC_PUSH : + UVM_LOCK_ORDER_CSL_PUSH); - channel_manager->num_channel_pools++; + uvm_sema_init(&pool->push_sem, num_channels, order); + } + + pool->channels = uvm_kvmalloc_zero(sizeof(*pool->channels) * num_channels); + if (!pool->channels) { + status = NV_ERR_NO_MEMORY; + goto error; + } for (i = 0; i < num_channels; i++) { uvm_channel_t *channel = pool->channels + i; @@ -1024,7 +2290,7 @@ if (status != NV_OK) goto error; - status = init_channel(channel); + status = channel_init(channel); if (status != NV_OK) goto error; } @@ -1208,29 +2474,35 @@ { NV_STATUS status; unsigned i; - UvmGpuCopyEnginesCaps ces_caps; + UvmGpuCopyEnginesCaps *ces_caps; uvm_channel_type_t types[] = {UVM_CHANNEL_TYPE_CPU_TO_GPU, UVM_CHANNEL_TYPE_GPU_TO_CPU, UVM_CHANNEL_TYPE_GPU_INTERNAL, UVM_CHANNEL_TYPE_GPU_TO_GPU, UVM_CHANNEL_TYPE_MEMOPS}; - memset(&ces_caps, 0, sizeof(ces_caps)); - status = uvm_rm_locked_call(nvUvmInterfaceQueryCopyEnginesCaps(uvm_gpu_device_handle(manager->gpu), &ces_caps)); + ces_caps = uvm_kvmalloc_zero(sizeof(*ces_caps)); + if (!ces_caps) + return NV_ERR_NO_MEMORY; + + status = uvm_rm_locked_call(nvUvmInterfaceQueryCopyEnginesCaps(uvm_gpu_device_handle(manager->gpu), ces_caps)); if (status != NV_OK) - return status; + goto out; // The order of picking CEs for each type matters as it's affected by the // usage count of each CE and it increases every time a CE is selected. // MEMOPS has the least priority as it only cares about low usage of the // CE to improve latency for (i = 0; i < ARRAY_SIZE(types); ++i) { - status = pick_ce_for_channel_type(manager, ces_caps.copyEngineCaps, types[i], preferred_ce); + status = pick_ce_for_channel_type(manager, ces_caps->copyEngineCaps, types[i], preferred_ce); if (status != NV_OK) - return status; + goto out; } - return NV_OK; +out: + uvm_kvfree(ces_caps); + + return status; } // Return the pool corresponding to the given CE index @@ -1321,6 +2593,28 @@ // 2- Allocation locations + if (uvm_conf_computing_mode_is_hcc(gpu)) { + UVM_ASSERT(gpu->mem_info.size > 0); + + // When the Confidential Computing feature is enabled, the GPU is + // guaranteed to have a frame buffer and the hardware enforces the + // following apertures for all channel types but SEC2. We create SEC2 + // channels by overriding their GPPUT and GPFIFO locations and ignoring + // the location from the channel manager. SEC2 channels are used to + // bootstrap secure work submission. To setup secure work launch, data + // transfers from unprotected main memory to protected vidmem are + // performed by the SEC2 engine and the driver must push work to SEC2 + // channels using unprotected locations. + manager->conf.gpfifo_loc = UVM_BUFFER_LOCATION_VID; + manager->conf.gpput_loc = UVM_BUFFER_LOCATION_VID; + + // Pushbuffer is located in unprotected sysmem. This is the location + // that gets mapped to both CPU and GPU. It is populated either by + // signed pushes (SEC2 channels), or encrypted pushes (CE channels). + manager->conf.pushbuffer_loc = UVM_BUFFER_LOCATION_SYS; + return; + } + // Override if the GPU doesn't have memory if (gpu->mem_info.size == 0) { manager->conf.pushbuffer_loc = UVM_BUFFER_LOCATION_SYS; @@ -1385,17 +2679,29 @@ gpput_loc_value); } - // By default we place GPFIFO and GPPUT on vidmem as it potentially has - // lower latency. - manager->conf.gpfifo_loc = UVM_BUFFER_LOCATION_VID; - manager->conf.gpput_loc = UVM_BUFFER_LOCATION_VID; - - // TODO: Bug 1766129: However, this will likely be different on P9 systems. - // Leaving GPFIFO on sysmem for now. GPPut on sysmem is not supported in - // production, so we keep it on vidmem, too. - if (gpu->parent->sysmem_link >= UVM_GPU_LINK_NVLINK_2) + // On coherent platforms where the GPU does not cache sysmem but the CPU + // caches vidmem (and sysmem), we place GPFIFO and GPPUT on sysmem to avoid + // cache thrash. The memory access latency is reduced, despite the required + // access through the bus, because no cache coherence message is exchanged. + if (uvm_gpu_is_coherent(gpu->parent)) { manager->conf.gpfifo_loc = UVM_BUFFER_LOCATION_SYS; + // On GPUs with limited ESCHED addressing range, e.g., Volta on P9, RM + // cannot guarantee that USERD/GPPUT physical address is accessible by + // ESCHED. We set GPPUT location to vidmem where physical addresses are + // all accessible by ESCHED. We use the max_host_va as a proxy for the + // PA limitation, since all architectures with 40b VA limits also have + // 40b PA limits. + manager->conf.gpput_loc = gpu->parent->max_host_va == (1ull << 40) ? UVM_BUFFER_LOCATION_VID : + UVM_BUFFER_LOCATION_SYS; + } + else { + // By default we place GPFIFO and GPPUT on vidmem as it potentially has + // lower latency. + manager->conf.gpfifo_loc = UVM_BUFFER_LOCATION_VID; + manager->conf.gpput_loc = UVM_BUFFER_LOCATION_VID; + } + // Override defaults if (string_to_buffer_location(gpfifo_loc_value) != UVM_BUFFER_LOCATION_DEFAULT) manager->conf.gpfifo_loc = string_to_buffer_location(gpfifo_loc_value); @@ -1404,60 +2710,478 @@ manager->conf.gpput_loc = string_to_buffer_location(gpput_loc_value); } -// A pool is created for each usable CE, even if it has not been selected as the -// preferred CE for any type, because as more information is discovered (for -// example, a pair of peer GPUs is added) we may start using the previously idle -// channels. -static NV_STATUS channel_manager_create_pools(uvm_channel_manager_t *manager) +// Returns the maximum number of pools that are needed in the current +// configuration. The implementation may choose to create a smaller number of +// pools. +static unsigned channel_manager_get_max_pools(uvm_channel_manager_t *manager) { - NV_STATUS status; - unsigned ce, type; unsigned num_channel_pools; - unsigned preferred_ce[UVM_CHANNEL_TYPE_CE_COUNT]; - uvm_channel_pool_t *pool = NULL; - - for (type = 0; type < ARRAY_SIZE(preferred_ce); type++) - preferred_ce[type] = UVM_COPY_ENGINE_COUNT_MAX; - status = channel_manager_pick_copy_engines(manager, preferred_ce); - if (status != NV_OK) - return status; - - // CE channel pools + // Create one CE channel pool per usable CE num_channel_pools = bitmap_weight(manager->ce_mask, UVM_COPY_ENGINE_COUNT_MAX); // CE proxy channel pool. if (uvm_gpu_uses_proxy_channel_pool(manager->gpu)) num_channel_pools++; - manager->channel_pools = uvm_kvmalloc_zero(sizeof(*manager->channel_pools) * num_channel_pools); - if (!manager->channel_pools) - return NV_ERR_NO_MEMORY; + // SEC2 pool, WLC pool, LCIC pool + if (uvm_conf_computing_mode_enabled(manager->gpu)) + num_channel_pools += 3; + return num_channel_pools; +} + +static NV_STATUS channel_manager_create_ce_pools(uvm_channel_manager_t *manager, unsigned *preferred_ce) +{ + unsigned ce; + + // A pool is created for each usable CE, even if it has not been selected as + // the preferred CE for any type, because as more information is discovered + // (for example, a pair of peer GPUs is added) we may start using the + // previously idle pools. for_each_set_bit(ce, manager->ce_mask, UVM_COPY_ENGINE_COUNT_MAX) { + NV_STATUS status; + unsigned type; + uvm_channel_pool_t *pool = NULL; + status = channel_pool_add(manager, UVM_CHANNEL_POOL_TYPE_CE, ce, &pool); if (status != NV_OK) return status; + + for (type = 0; type < UVM_CHANNEL_TYPE_CE_COUNT; type++) { + // Set pool type if it hasn't been set before. + if (preferred_ce[type] == ce && manager->pool_to_use.default_for_type[type] == NULL) + manager->pool_to_use.default_for_type[type] = pool; + } } - // Assign channel types to pools - for (type = 0; type < ARRAY_SIZE(preferred_ce); type++) { - unsigned ce = preferred_ce[type]; + return NV_OK; +} - UVM_ASSERT(test_bit(ce, manager->ce_mask)); +static NV_STATUS setup_wlc_schedule(uvm_channel_t *wlc) +{ + uvm_gpu_t *gpu = uvm_channel_get_gpu(wlc); + NvU64 protected_vidmem = uvm_rm_mem_get_gpu_uvm_va(wlc->conf_computing.static_pb_protected_vidmem, gpu); + NvU64 unprotected_sysmem_gpu = uvm_rm_mem_get_gpu_uvm_va(wlc->conf_computing.static_pb_unprotected_sysmem, gpu); + void *unprotected_sysmem_cpu = wlc->conf_computing.static_pb_unprotected_sysmem_cpu; + NvU64 tag_offset = (uintptr_t)wlc->conf_computing.static_pb_unprotected_sysmem_auth_tag_cpu - + (uintptr_t)wlc->conf_computing.static_pb_unprotected_sysmem_cpu; + + NvU64 *wlc_gpfifo_entries; + uvm_push_t wlc_decrypt_push, sec2_push; + NvU32 decrypt_push_size; + int i; + NV_STATUS status = NV_OK; + + // "gpfifo" is the representation of GPFIFO copied to gpFifoGpu + const size_t gpfifo_size = wlc->num_gpfifo_entries * sizeof(*wlc_gpfifo_entries); + void *gpfifo_unprotected_cpu = unprotected_sysmem_cpu; + NvU64 gpfifo_unprotected_gpu = unprotected_sysmem_gpu; + + // "run_push" represents mutable push location used by WLC + uvm_gpu_address_t run_push_protected_gpu = uvm_gpu_address_virtual(protected_vidmem); + uvm_gpu_address_t run_push_unprotected_gpu = uvm_gpu_address_virtual(unprotected_sysmem_gpu); + uvm_gpu_address_t run_push_unprotected_auth_tag_gpu = uvm_gpu_address_virtual(unprotected_sysmem_gpu + tag_offset); + + // "decrypt_push" represents WLC decrypt push, constructed using fake_push. + // Copied to wlc_pb_base + UVM_MAX_WLC_PUSH_SIZE, as the second of the two + // pushes that make the WLC fixed schedule. + NvU64 decrypt_push_protected_gpu = UVM_ALIGN_UP(protected_vidmem + UVM_MAX_WLC_PUSH_SIZE, UVM_CONF_COMPUTING_SEC2_BUF_ALIGNMENT); + NvU64 decrypt_push_unprotected_gpu = unprotected_sysmem_gpu + gpfifo_size; + void *decrypt_push_unprotected_cpu = (char*)gpfifo_unprotected_cpu + gpfifo_size; + + // Tags for upload via SEC2 + void *decrypt_push_auth_tag, *gpfifo_auth_tag; + uvm_gpu_address_t decrypt_push_auth_tag_gpu, gpfifo_auth_tag_gpu; + + BUILD_BUG_ON(sizeof(*wlc_gpfifo_entries) != sizeof(*wlc->channel_info.gpFifoEntries)); + + UVM_ASSERT(uvm_channel_is_wlc(wlc)); + UVM_ASSERT(tag_offset == UVM_ALIGN_UP(UVM_MAX_WLC_PUSH_SIZE, UVM_CONF_COMPUTING_AUTH_TAG_ALIGNMENT)); + + // WLC schedule consists of two parts, the number of entries needs to be even. + // This also guarantees that the size is 16B aligned + UVM_ASSERT(IS_ALIGNED(wlc->num_gpfifo_entries, 2)); + + wlc_gpfifo_entries = uvm_kvmalloc(gpfifo_size); + if (!wlc_gpfifo_entries) + return NV_ERR_NO_MEMORY; + + // WLC can only process one job at a time. + // Prune any initialization entries and block all but one (+1 for sentinel) + uvm_channel_update_progress(wlc); + if (!try_claim_channel(wlc, wlc->num_gpfifo_entries - 2)) { + status = NV_ERR_INVALID_STATE; + goto free_gpfifo_entries; + } + + // WLC schedule has two steps: + // 1.) Decrypt from gpu_unprotected_base to wlc_pb_base + // Increment LCIC PUT + // 2.) Execute push at wlc_pb_base + // The first one is a push, the second one is just a GPFIFO entry + status = uvm_push_begin_fake(gpu, &wlc_decrypt_push); + if (status != NV_OK) + goto free_gpfifo_entries; + + // Begin WLC DECRYPT push + uvm_push_set_flag(&wlc_decrypt_push, UVM_PUSH_FLAG_NEXT_MEMBAR_GPU); + gpu->parent->ce_hal->decrypt(&wlc_decrypt_push, + run_push_protected_gpu, + run_push_unprotected_gpu, + UVM_MAX_WLC_PUSH_SIZE, + run_push_unprotected_auth_tag_gpu); + uvm_hal_wfi_membar(&wlc_decrypt_push, UVM_MEMBAR_NONE); + decrypt_push_size = uvm_push_get_size(&wlc_decrypt_push); + + // The code below reuses static unprotected sysmem buffer as a temporary + // storage for uploading the schedule. Check that everything fits. + UVM_ASSERT(gpfifo_size + decrypt_push_size <= UVM_MAX_WLC_PUSH_SIZE); + + // GPFIFO schedule should alternate between the decrypt routine + // we don't know if initialization used even or odd number of + // GPFIFO entries so the exact pattern depends on the value of "PUT" + for (i = 0; i < wlc->num_gpfifo_entries; ++i) { + if (i % 2 == wlc->cpu_put % 2) { + gpu->parent->host_hal->set_gpfifo_entry(wlc_gpfifo_entries + i, + decrypt_push_protected_gpu, + decrypt_push_size, + UVM_GPFIFO_SYNC_PROCEED); + } + else { + gpu->parent->host_hal->set_gpfifo_entry(wlc_gpfifo_entries + i, + run_push_protected_gpu.address, + UVM_MAX_WLC_PUSH_SIZE, + UVM_GPFIFO_SYNC_WAIT); + } + } + + // The schedule is prepared. Upload to vidmem + status = uvm_push_begin(wlc->pool->manager, + UVM_CHANNEL_TYPE_SEC2, + &sec2_push, + "Upload WLC schedule for: %s", wlc->name); + if (status != NV_OK) + goto end_wlc_dec_push; + + decrypt_push_auth_tag = uvm_push_get_single_inline_buffer(&sec2_push, + UVM_CONF_COMPUTING_AUTH_TAG_SIZE, + UVM_CONF_COMPUTING_AUTH_TAG_ALIGNMENT, + &decrypt_push_auth_tag_gpu); + + gpfifo_auth_tag = uvm_push_get_single_inline_buffer(&sec2_push, + UVM_CONF_COMPUTING_AUTH_TAG_SIZE, + UVM_CONF_COMPUTING_AUTH_TAG_ALIGNMENT, + &gpfifo_auth_tag_gpu); + + // Upload WLC pushbuffer + uvm_conf_computing_cpu_encrypt(sec2_push.channel, + decrypt_push_unprotected_cpu, + wlc_decrypt_push.begin, + NULL, + decrypt_push_size, + decrypt_push_auth_tag); + gpu->parent->sec2_hal->decrypt(&sec2_push, + decrypt_push_protected_gpu, + decrypt_push_unprotected_gpu, + decrypt_push_size, + decrypt_push_auth_tag_gpu.address); + + // Upload WLC GPFIFO + uvm_conf_computing_cpu_encrypt(sec2_push.channel, + gpfifo_unprotected_cpu, + wlc_gpfifo_entries, + NULL, + gpfifo_size, + gpfifo_auth_tag); + gpu->parent->sec2_hal->decrypt(&sec2_push, + wlc->channel_info.gpFifoGpuVa, + gpfifo_unprotected_gpu, + gpfifo_size, + gpfifo_auth_tag_gpu.address); + + // Prime the WLC by setting "PUT" two steps ahead. Reuse the current + // cpu_put value that was used during channel initialization. + // Don't update wlc->cpu_put, it will be used to track submitted pushes + // as any other channel. + update_gpput_via_sec2(&sec2_push, wlc, (wlc->cpu_put + 2) % wlc->num_gpfifo_entries); + + status = uvm_push_end_and_wait(&sec2_push); + +end_wlc_dec_push: + uvm_push_end_fake(&wlc_decrypt_push); +free_gpfifo_entries: + uvm_kvfree(wlc_gpfifo_entries); + return status; +} + +static NV_STATUS setup_lcic_schedule(uvm_channel_t *paired_wlc, uvm_channel_t *lcic) +{ + uvm_gpu_t *gpu = uvm_channel_get_gpu(lcic); + NvU64 lcic_pb_base = uvm_rm_mem_get_gpu_uvm_va(lcic->conf_computing.static_pb_protected_vidmem, gpu); + + // Reuse WLC sysmem allocation + NvU64 gpu_unprotected = uvm_rm_mem_get_gpu_uvm_va(paired_wlc->conf_computing.static_pb_unprotected_sysmem, gpu); + char *cpu_unprotected = paired_wlc->conf_computing.static_pb_unprotected_sysmem_cpu; + uvm_gpu_semaphore_t *lcic_gpu_semaphore = &lcic->tracking_sem.semaphore; + uvm_gpu_address_t notifier_src_entry_addr = lcic->conf_computing.static_notifier_entry_unprotected_sysmem_gpu_va; + uvm_gpu_address_t notifier_src_exit_addr = lcic->conf_computing.static_notifier_exit_unprotected_sysmem_gpu_va; + uvm_gpu_address_t notifier_dst_addr = uvm_rm_mem_get_gpu_va(lcic_gpu_semaphore->conf_computing.notifier, + gpu, + false); + uvm_gpu_address_t encrypted_payload_gpu_va = + uvm_rm_mem_get_gpu_va(lcic_gpu_semaphore->conf_computing.encrypted_payload, gpu, false); + uvm_gpu_address_t semaphore_gpu_va = uvm_gpu_address_virtual(uvm_channel_tracking_semaphore_get_gpu_va(lcic)); + uvm_gpu_address_t auth_tag_gpu_va = uvm_rm_mem_get_gpu_va(lcic_gpu_semaphore->conf_computing.auth_tag, gpu, false); + NvU32 payload_size = sizeof(*lcic->tracking_sem.semaphore.payload); + NvU32 notifier_size = sizeof(*lcic->conf_computing.static_notifier_entry_unprotected_sysmem_cpu); + + NvU64 *lcic_gpfifo_entries; + uvm_push_t lcic_push, sec2_push; + NvU32 lcic_push_size; + int i; + NV_STATUS status; + + const size_t gpfifo_size = lcic->num_gpfifo_entries * sizeof(*lcic_gpfifo_entries); + char *gpfifo_unprotected_cpu = cpu_unprotected; + NvU64 gpfifo_unprotected_gpu = gpu_unprotected; + char *lcic_push_unprotected_cpu = gpfifo_unprotected_cpu + gpfifo_size; + NvU64 lcic_push_unprotected_gpu = gpfifo_unprotected_gpu + gpfifo_size; + NvU64 lcic_push_protected_gpu = lcic_pb_base; + + char *lcic_push_enc_tag, *gpfifo_enc_tag; + uvm_gpu_address_t lcic_push_enc_tag_gpu, gpfifo_enc_tag_gpu; + + BUILD_BUG_ON(sizeof(*lcic_gpfifo_entries) != sizeof(*lcic->channel_info.gpFifoEntries)); + + UVM_ASSERT(uvm_channel_is_wlc(paired_wlc)); + UVM_ASSERT(uvm_channel_is_lcic(lcic)); + + lcic_gpfifo_entries = uvm_kvmalloc(gpfifo_size); + if (!lcic_gpfifo_entries) + return NV_ERR_NO_MEMORY; + + // LCIC can not process outside jobs. + // Prune any initialization entries and + // block all gpfifo entries (-1 for sentinel) + uvm_channel_update_progress(lcic); + if (!try_claim_channel(lcic, lcic->num_gpfifo_entries - 1)) { + status = NV_ERR_INVALID_STATE; + goto free_gpfifo_entries; + } + + status = uvm_push_begin_fake(gpu, &lcic_push); + if (status != NV_OK) + goto free_gpfifo_entries; + + // LCIC schedule is simple: + // 1.) wait for engine idle + // 2.) advance the WLC PUT by 2 + // 3.) release driver semaphore + uvm_hal_wfi_membar(&lcic_push, UVM_MEMBAR_NONE); + gpu->parent->ce_hal->semaphore_reduction_inc(&lcic_push, + paired_wlc->channel_info.gpPutGpuVa, + paired_wlc->num_gpfifo_entries - 1); + gpu->parent->ce_hal->semaphore_reduction_inc(&lcic_push, + paired_wlc->channel_info.gpPutGpuVa, + paired_wlc->num_gpfifo_entries - 1); + gpu->parent->ce_hal->semaphore_reduction_inc(&lcic_push, + semaphore_gpu_va.address, + 0xffffffff); + + gpu->parent->ce_hal->memcopy(&lcic_push, notifier_dst_addr, notifier_src_entry_addr, notifier_size); + gpu->parent->ce_hal->encrypt(&lcic_push, encrypted_payload_gpu_va, semaphore_gpu_va, payload_size, auth_tag_gpu_va); + gpu->parent->ce_hal->memcopy(&lcic_push, notifier_dst_addr, notifier_src_exit_addr, notifier_size); + + // End LCIC push + lcic_push_size = uvm_push_get_size(&lcic_push); + + // We're reusing pre-allocated structures from WLC, make sure we fit. + UVM_ASSERT(lcic_push_size == UVM_LCIC_PUSH_SIZE); + UVM_ASSERT(lcic_push_size + gpfifo_size <= UVM_MAX_WLC_PUSH_SIZE); + + // Set all entries to execute the above push + for (i = 0; i < lcic->num_gpfifo_entries; ++i) + gpu->parent->host_hal->set_gpfifo_entry(lcic_gpfifo_entries + i, + lcic_push_protected_gpu, + lcic_push_size, + UVM_GPFIFO_SYNC_PROCEED); + + // Upload the prepared schedule using SEC2 + status = uvm_push_begin(lcic->pool->manager, + UVM_CHANNEL_TYPE_SEC2, + &sec2_push, + "Upload LCIC schedule for: %s", lcic->name); + if (status != NV_OK) + goto end_lcic_push; + + lcic_push_enc_tag = uvm_push_get_single_inline_buffer(&sec2_push, + UVM_CONF_COMPUTING_AUTH_TAG_SIZE, + UVM_CONF_COMPUTING_AUTH_TAG_ALIGNMENT, + &lcic_push_enc_tag_gpu); + + gpfifo_enc_tag = uvm_push_get_single_inline_buffer(&sec2_push, + UVM_CONF_COMPUTING_AUTH_TAG_SIZE, + UVM_CONF_COMPUTING_AUTH_TAG_ALIGNMENT, + &gpfifo_enc_tag_gpu); + + // Upload LCIC pushbuffer + uvm_conf_computing_cpu_encrypt(sec2_push.channel, + lcic_push_unprotected_cpu, + lcic_push.begin, + NULL, + lcic_push_size, + lcic_push_enc_tag); + gpu->parent->sec2_hal->decrypt(&sec2_push, + lcic_push_protected_gpu, + lcic_push_unprotected_gpu, + lcic_push_size, + lcic_push_enc_tag_gpu.address); + + // Upload LCIC GPFIFO + uvm_conf_computing_cpu_encrypt(sec2_push.channel, + gpfifo_unprotected_cpu, + lcic_gpfifo_entries, + NULL, + gpfifo_size, + gpfifo_enc_tag); + gpu->parent->sec2_hal->decrypt(&sec2_push, + lcic->channel_info.gpFifoGpuVa, + gpfifo_unprotected_gpu, + gpfifo_size, + gpfifo_enc_tag_gpu.address); + status = uvm_push_end_and_wait(&sec2_push); + +end_lcic_push: + uvm_push_end_fake(&lcic_push); +free_gpfifo_entries: + uvm_kvfree(lcic_gpfifo_entries); + return status; +} + +static NV_STATUS channel_manager_setup_wlc_lcic(uvm_channel_pool_t *wlc_pool, uvm_channel_pool_t *lcic_pool) +{ + NvU32 i; + + UVM_ASSERT(wlc_pool->manager == lcic_pool->manager); + UVM_ASSERT(wlc_pool->manager->pool_to_use.default_for_type[UVM_CHANNEL_TYPE_WLC] != NULL); + UVM_ASSERT(lcic_pool->manager->pool_to_use.default_for_type[UVM_CHANNEL_TYPE_LCIC] == NULL); + UVM_ASSERT(wlc_pool->num_channels == lcic_pool->num_channels); + + for (i = 0; i < wlc_pool->num_channels; ++i) { + uvm_channel_t *wlc = wlc_pool->channels + i; + uvm_channel_t *lcic = lcic_pool->channels + i; + NV_STATUS status; + + status = setup_wlc_schedule(wlc); + if (status != NV_OK) + return status; - manager->pool_to_use.default_for_type[type] = channel_manager_ce_pool(manager, ce); + status = setup_lcic_schedule(wlc, lcic); + if (status != NV_OK) + return status; } + return NV_OK; +} + +static NV_STATUS channel_manager_create_conf_computing_pools(uvm_channel_manager_t *manager, unsigned *preferred_ce) +{ + NV_STATUS status; + unsigned wlc_lcic_ce_index; + uvm_channel_pool_t *sec2_pool = NULL; + uvm_channel_pool_t *wlc_pool = NULL; + uvm_channel_pool_t *lcic_pool = NULL; + + if (!uvm_conf_computing_mode_enabled(manager->gpu)) + return NV_OK; + + status = uvm_rm_mem_alloc(manager->gpu, + UVM_RM_MEM_TYPE_SYS, + sizeof(UvmCslIv), + UVM_CONF_COMPUTING_BUF_ALIGNMENT, + &manager->gpu->conf_computing.iv_rm_mem); + if (status != NV_OK) + return status; + + // Create SEC2 pool. This needs to be done first, initialization of + // other channels needs SEC2. + status = channel_pool_add(manager, UVM_CHANNEL_POOL_TYPE_SEC2, 0, &sec2_pool); + if (status != NV_OK) + return status; + + manager->pool_to_use.default_for_type[UVM_CHANNEL_TYPE_SEC2] = sec2_pool; + + // Use the same CE as CPU TO GPU channels for WLC/LCIC + // Both need to use the same engine for the fixed schedule to work. + // TODO: Bug 3981928: [hcc][uvm] Optimize parameters of WLC/LCIC secure + // work launch + // Find a metric to select the best CE to use + wlc_lcic_ce_index = preferred_ce[UVM_CHANNEL_TYPE_CPU_TO_GPU]; + + // Create WLC/LCIC pools. This should be done early, CE channels use + // them for secure launch. The WLC pool must be created before the LCIC. + status = channel_pool_add(manager, UVM_CHANNEL_POOL_TYPE_WLC, wlc_lcic_ce_index, &wlc_pool); + if (status != NV_OK) + return status; + + manager->pool_to_use.default_for_type[UVM_CHANNEL_TYPE_WLC] = wlc_pool; + + status = channel_pool_add(manager, UVM_CHANNEL_POOL_TYPE_LCIC, wlc_lcic_ce_index, &lcic_pool); + if (status != NV_OK) + return status; + + status = channel_manager_setup_wlc_lcic(wlc_pool, lcic_pool); + if (status != NV_OK) + return status; + + // The LCIC pool must be assigned after the call to + // channel_manager_setup_wlc_lcic(). It determines WLC and LCIC channels + // are ready to be used for secure work submission. + manager->pool_to_use.default_for_type[UVM_CHANNEL_TYPE_LCIC] = lcic_pool; + + return NV_OK; +} + +static NV_STATUS channel_manager_create_pools(uvm_channel_manager_t *manager) +{ + NV_STATUS status; + uvm_channel_type_t type; + unsigned max_channel_pools; + unsigned preferred_ce[UVM_CHANNEL_TYPE_CE_COUNT]; + + for (type = 0; type < ARRAY_SIZE(preferred_ce); type++) + preferred_ce[type] = UVM_COPY_ENGINE_COUNT_MAX; + + status = channel_manager_pick_copy_engines(manager, preferred_ce); + if (status != NV_OK) + return status; + + max_channel_pools = channel_manager_get_max_pools(manager); + + manager->channel_pools = uvm_kvmalloc_zero(sizeof(*manager->channel_pools) * max_channel_pools); + if (!manager->channel_pools) + return NV_ERR_NO_MEMORY; + + status = channel_manager_create_conf_computing_pools(manager, preferred_ce); + if (status != NV_OK) + return status; + + status = channel_manager_create_ce_pools(manager, preferred_ce); + if (status != NV_OK) + return status; + // In SR-IOV heavy, add an additional, single-channel, pool that is // dedicated to the MEMOPS type. if (uvm_gpu_uses_proxy_channel_pool(manager->gpu)) { + uvm_channel_pool_t *proxy_pool = NULL; uvm_channel_type_t channel_type = uvm_channel_proxy_channel_type(); - status = channel_pool_add(manager, UVM_CHANNEL_POOL_TYPE_CE_PROXY, preferred_ce[channel_type], &pool); + + status = channel_pool_add(manager, UVM_CHANNEL_POOL_TYPE_CE_PROXY, preferred_ce[channel_type], &proxy_pool); if (status != NV_OK) return status; - manager->pool_to_use.default_for_type[channel_type] = pool; + manager->pool_to_use.default_for_type[channel_type] = proxy_pool; } return NV_OK; @@ -1501,12 +3225,55 @@ static void channel_manager_destroy_pools(uvm_channel_manager_t *manager) { + uvm_rm_mem_free(manager->gpu->conf_computing.iv_rm_mem); + manager->gpu->conf_computing.iv_rm_mem = NULL; while (manager->num_channel_pools > 0) channel_pool_destroy(manager->channel_pools + manager->num_channel_pools - 1); uvm_kvfree(manager->channel_pools); } +// Because the WLC at rest state has PUT = GET + 2, there's always pending work +// This is what enables the driver to submit work just by ringing a doorbell. +// However, this also means that the pending work has to be removed before +// the channel is passed to RM for deallocation. +static void channel_manager_stop_wlc(uvm_channel_manager_t *manager) +{ + uvm_channel_pool_t *wlc_pool = manager->pool_to_use.default_for_type[UVM_CHANNEL_TYPE_WLC]; + uvm_channel_pool_t *lcic_pool = manager->pool_to_use.default_for_type[UVM_CHANNEL_TYPE_LCIC]; + uvm_channel_t *channel; + uvm_push_t push; + NV_STATUS status; + + uvm_for_each_channel_in_pool(channel, lcic_pool) { + uvm_spin_loop_t spin; + + // Wait for the WLC/LCIC to be primed. This means that PUT == GET + 2 + // and a WLC doorbell ring is enough to start work. + UVM_SPIN_WHILE(!uvm_gpu_tracking_semaphore_is_completed(&channel->tracking_sem), &spin); + } + + status = uvm_push_begin(manager, UVM_CHANNEL_TYPE_SEC2, &push, "Stop WLC channels"); + if (status != NV_OK) { + UVM_ERR_PRINT_NV_STATUS("Failed to begin stop push for WLC", status); + return; + } + + uvm_for_each_channel_in_pool(channel, wlc_pool) { + // Every gpfifo entry advances the gpu put of WLC by two so the current + // value is: (cpu_put * 2) % num_gpfifo_entries and it's ahead of the + // get pointer by 2. + update_gpput_via_sec2(&push, channel, (channel->cpu_put * 2 - 2) % channel->num_gpfifo_entries); + } + + status = uvm_push_end_and_wait(&push); + if (status != NV_OK) + UVM_ERR_PRINT_NV_STATUS("Failed to end stop push for WLC", status); + + manager->pool_to_use.default_for_type[UVM_CHANNEL_TYPE_WLC] = NULL; + manager->pool_to_use.default_for_type[UVM_CHANNEL_TYPE_LCIC] = NULL; +} + void uvm_channel_manager_destroy(uvm_channel_manager_t *channel_manager) { if (channel_manager == NULL) @@ -1514,6 +3281,9 @@ proc_remove(channel_manager->procfs.pending_pushes); + if (uvm_channel_manager_is_wlc_ready(channel_manager)) + channel_manager_stop_wlc(channel_manager); + channel_manager_destroy_pools(channel_manager); proc_remove(channel_manager->procfs.channels_dir); @@ -1585,7 +3355,7 @@ const char *uvm_channel_type_to_string(uvm_channel_type_t channel_type) { - BUILD_BUG_ON(UVM_CHANNEL_TYPE_COUNT != 5); + BUILD_BUG_ON(UVM_CHANNEL_TYPE_COUNT != 8); switch (channel_type) { UVM_ENUM_STRING_CASE(UVM_CHANNEL_TYPE_CPU_TO_GPU); @@ -1593,39 +3363,60 @@ UVM_ENUM_STRING_CASE(UVM_CHANNEL_TYPE_GPU_INTERNAL); UVM_ENUM_STRING_CASE(UVM_CHANNEL_TYPE_MEMOPS); UVM_ENUM_STRING_CASE(UVM_CHANNEL_TYPE_GPU_TO_GPU); + UVM_ENUM_STRING_CASE(UVM_CHANNEL_TYPE_SEC2); + UVM_ENUM_STRING_CASE(UVM_CHANNEL_TYPE_WLC); + UVM_ENUM_STRING_CASE(UVM_CHANNEL_TYPE_LCIC); UVM_ENUM_STRING_DEFAULT(); } } const char *uvm_channel_pool_type_to_string(uvm_channel_pool_type_t channel_pool_type) { - BUILD_BUG_ON(UVM_CHANNEL_POOL_TYPE_COUNT != 2); + BUILD_BUG_ON(UVM_CHANNEL_POOL_TYPE_COUNT != 5); switch (channel_pool_type) { UVM_ENUM_STRING_CASE(UVM_CHANNEL_POOL_TYPE_CE); UVM_ENUM_STRING_CASE(UVM_CHANNEL_POOL_TYPE_CE_PROXY); + UVM_ENUM_STRING_CASE(UVM_CHANNEL_POOL_TYPE_SEC2); + UVM_ENUM_STRING_CASE(UVM_CHANNEL_POOL_TYPE_WLC); + UVM_ENUM_STRING_CASE(UVM_CHANNEL_POOL_TYPE_LCIC); UVM_ENUM_STRING_DEFAULT(); } } +static const char *get_gpfifo_location_string(uvm_channel_t *channel) +{ + // SEC2 channels override the channel manager location for GPFIFO. + if (uvm_channel_is_sec2(channel)) + return buffer_location_to_string(UVM_BUFFER_LOCATION_SYS); + return buffer_location_to_string(channel->pool->manager->conf.gpfifo_loc); +} + +static const char *get_gpput_location_string(uvm_channel_t *channel) +{ + // SEC2 channels override the channel manager location for GPPUT. + if (uvm_channel_is_sec2(channel)) + return buffer_location_to_string(UVM_BUFFER_LOCATION_SYS); + return buffer_location_to_string(channel->pool->manager->conf.gpput_loc); +} + static void uvm_channel_print_info(uvm_channel_t *channel, struct seq_file *s) { - uvm_channel_manager_t *manager = channel->pool->manager; UVM_SEQ_OR_DBG_PRINT(s, "Channel %s\n", channel->name); - uvm_channel_pool_lock(channel->pool); + channel_pool_lock(channel->pool); UVM_SEQ_OR_DBG_PRINT(s, "completed %llu\n", uvm_channel_update_completed_value(channel)); UVM_SEQ_OR_DBG_PRINT(s, "queued %llu\n", channel->tracking_sem.queued_value); UVM_SEQ_OR_DBG_PRINT(s, "GPFIFO count %u\n", channel->num_gpfifo_entries); - UVM_SEQ_OR_DBG_PRINT(s, "GPFIFO location %s\n", buffer_location_to_string(manager->conf.gpfifo_loc)); - UVM_SEQ_OR_DBG_PRINT(s, "GPPUT location %s\n", buffer_location_to_string(manager->conf.gpput_loc)); + UVM_SEQ_OR_DBG_PRINT(s, "GPFIFO location %s\n", get_gpfifo_location_string(channel)); + UVM_SEQ_OR_DBG_PRINT(s, "GPPUT location %s\n", get_gpput_location_string(channel)); UVM_SEQ_OR_DBG_PRINT(s, "get %u\n", channel->gpu_get); UVM_SEQ_OR_DBG_PRINT(s, "put %u\n", channel->cpu_put); UVM_SEQ_OR_DBG_PRINT(s, "Semaphore GPU VA 0x%llx\n", uvm_channel_tracking_semaphore_get_gpu_va(channel)); UVM_SEQ_OR_DBG_PRINT(s, "Semaphore CPU VA 0x%llx\n", (NvU64)(uintptr_t)channel->tracking_sem.semaphore.payload); - uvm_channel_pool_unlock(channel->pool); + channel_pool_unlock(channel->pool); } static void channel_print_push_acquires(uvm_push_acquire_info_t *push_acquire_info, struct seq_file *seq) @@ -1669,7 +3460,7 @@ NvU64 completed_value = uvm_channel_update_completed_value(channel); - uvm_channel_pool_lock(channel->pool); + channel_pool_lock(channel->pool); cpu_put = channel->cpu_put; @@ -1682,14 +3473,11 @@ continue; if (entry->type == UVM_GPFIFO_ENTRY_TYPE_CONTROL) { - NvU64 *gpfifo_entry; - UVM_ASSERT(!uvm_channel_is_proxy(channel)); - gpfifo_entry = (NvU64*)channel->channel_info.gpFifoEntries + gpu_get; UVM_SEQ_OR_DBG_PRINT(seq, " control GPFIFO entry - data: 0x%llx, gpu_get: %d\n", - *gpfifo_entry, + entry->control_value, gpu_get); } else { @@ -1717,7 +3505,7 @@ channel_print_push_acquires(push_acquire_info, seq); } } - uvm_channel_pool_unlock(channel->pool); + channel_pool_unlock(channel->pool); } void uvm_channel_print_pending_pushes(uvm_channel_t *channel) diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/kernel-open/nvidia-uvm/uvm_channel.h nvidia-open-gpu-kernel-modules-535.161.08/kernel-open/nvidia-uvm/uvm_channel.h --- nvidia-open-gpu-kernel-modules-525.147.05/kernel-open/nvidia-uvm/uvm_channel.h 2023-10-25 20:33:34.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/kernel-open/nvidia-uvm/uvm_channel.h 2024-03-05 22:25:50.000000000 +0000 @@ -1,5 +1,5 @@ /******************************************************************************* - Copyright (c) 2015-2022 NVIDIA Corporation + Copyright (c) 2015-2023 NVIDIA Corporation Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation files (the "Software"), to @@ -50,6 +50,9 @@ #define UVM_CHANNEL_NUM_GPFIFO_ENTRIES_MIN 32 #define UVM_CHANNEL_NUM_GPFIFO_ENTRIES_MAX (1024 * 1024) +// Maximum number of channels per pool. +#define UVM_CHANNEL_MAX_NUM_CHANNELS_PER_POOL UVM_PUSH_MAX_CONCURRENT_PUSHES + // Semaphore payloads cannot advance too much between calls to // uvm_gpu_tracking_semaphore_update_completed_value(). In practice the jumps // are bound by gpfifo sizing as we have to update the completed value to @@ -61,6 +64,14 @@ // uvm_channel.h includes uvm_gpu_semaphore.h. #define UVM_GPU_SEMAPHORE_MAX_JUMP (2 * UVM_CHANNEL_NUM_GPFIFO_ENTRIES_MAX) +#define uvm_channel_pool_assert_locked(pool) ( \ +{ \ + if (uvm_channel_pool_uses_mutex(pool)) \ + uvm_assert_mutex_locked(&(pool)->mutex); \ + else \ + uvm_assert_spinlock_locked(&(pool)->spinlock); \ +}) + // Channel types typedef enum { @@ -83,7 +94,27 @@ // ^^^^^^ // Channel types backed by a CE. - UVM_CHANNEL_TYPE_COUNT = UVM_CHANNEL_TYPE_CE_COUNT, + // ---------------------------------- + // Channel types not backed by a CE. + // vvvvvv + + // SEC2 channels + UVM_CHANNEL_TYPE_SEC2 = UVM_CHANNEL_TYPE_CE_COUNT, + + // ---------------------------------- + // Channel type with fixed schedules + + // Work Launch Channel (WLC) is a specialized channel for launching work on + // other channels when the Confidential Computing is feature enabled. It is + // paired with LCIC (below) + UVM_CHANNEL_TYPE_WLC, + + // Launch Confirmation Indicator Channel (LCIC) is a specialized channel + // with fixed schedule. It gets triggered by executing WLC work, and makes + // sure that WLC get/put pointers are up-to-date. + UVM_CHANNEL_TYPE_LCIC, + + UVM_CHANNEL_TYPE_COUNT, } uvm_channel_type_t; typedef enum @@ -101,7 +132,15 @@ // There is a single proxy pool and channel per GPU. UVM_CHANNEL_POOL_TYPE_CE_PROXY = (1 << 1), - UVM_CHANNEL_POOL_TYPE_COUNT = 2, + // A pool of SEC2 channels owned by UVM. These channels are backed by a SEC2 + // engine. + UVM_CHANNEL_POOL_TYPE_SEC2 = (1 << 2), + + UVM_CHANNEL_POOL_TYPE_WLC = (1 << 3), + + UVM_CHANNEL_POOL_TYPE_LCIC = (1 << 4), + + UVM_CHANNEL_POOL_TYPE_COUNT = 5, // A mask used to select pools of any type. UVM_CHANNEL_POOL_TYPE_MASK = ((1U << UVM_CHANNEL_POOL_TYPE_COUNT) - 1) @@ -125,15 +164,23 @@ // this entry. NvU64 tracking_semaphore_value; - // The following fields are only valid when type is - // UVM_GPFIFO_ENTRY_TYPE_NORMAL. + union { + struct { + // Offset of the pushbuffer in the pushbuffer allocation used by + // this entry. + NvU32 pushbuffer_offset; - // Offset of the pushbuffer in the pushbuffer allocation used by - // this entry. - NvU32 pushbuffer_offset; + // Size of the pushbuffer used for this entry. + NvU32 pushbuffer_size; + }; - // Size of the pushbuffer used for this entry. - NvU32 pushbuffer_size; + // Value of control entry + // Exact value of GPFIFO entry copied directly to GPFIFO[PUT] location. + NvU64 control_value; + }; + + // The following fields are only valid when type is + // UVM_GPFIFO_ENTRY_TYPE_NORMAL. // List node used by the pushbuffer tracking struct list_head pending_list_node; @@ -149,6 +196,19 @@ // Owning channel manager uvm_channel_manager_t *manager; + // On Volta+ GPUs, all channels in a pool are members of the same TSG, i.e., + // num_tsgs is 1. Pre-Volta GPUs also have a single TSG object, but since HW + // does not support TSG for CE engines, a HW TSG is not created, but a TSG + // object is required to allocate channels. + // When Confidential Computing mode is enabled, the WLC and LCIC channel + // types require one TSG for each WLC/LCIC pair of channels. In this case, + // we do not use a TSG per channel pool, but instead a TSG per WLC/LCIC + // channel pair, num_tsgs equals to the number of channel pairs. + uvmGpuTsgHandle *tsg_handles; + + // Number TSG handles owned by this pool. + NvU32 num_tsgs; + // Channels in this pool uvm_channel_t *channels; @@ -162,12 +222,27 @@ // Pool type: Refer to the uvm_channel_pool_type_t enum. uvm_channel_pool_type_t pool_type; - // Lock protecting the state of channels in the pool + // Lock protecting the state of channels in the pool. + // + // There are two pool lock types available: spinlock and mutex. The mutex + // variant is required when the thread holding the pool lock must sleep + // (ex: acquire another mutex) deeper in the call stack, either in UVM or + // RM. union { uvm_spinlock_t spinlock; uvm_mutex_t mutex; }; + // Secure operations require that uvm_push_begin order matches + // uvm_push_end order, because the engine's state is used in its internal + // operation and each push may modify this state. push_locks is protected by + // the channel pool lock. + DECLARE_BITMAP(push_locks, UVM_CHANNEL_MAX_NUM_CHANNELS_PER_POOL); + + // Counting semaphore for available and unlocked channels, it must be + // acquired before submitting work to a channel when the Confidential + // Computing feature is enabled. + uvm_semaphore_t push_sem; } uvm_channel_pool_t; struct uvm_channel_struct @@ -218,6 +293,74 @@ // uvm_channel_end_push(). uvm_gpu_tracking_semaphore_t tracking_sem; + struct + { + // Secure operations require that uvm_push_begin order matches + // uvm_push_end order, because the engine's state is used in + // its internal operation and each push may modify this state. + uvm_mutex_t push_lock; + + // When the Confidential Computing feature is enabled, every channel has + // cryptographic state in HW, which is mirrored here for CPU-side + // operations. + UvmCslContext ctx; + bool is_ctx_initialized; + + // CPU-side CSL crypto operations which operate on the same CSL state + // are not thread-safe, so they must be wrapped in locks at the UVM + // level. Encryption, decryption and logging operations must be + // protected with the ctx_lock. + uvm_mutex_t ctx_lock; + } csl; + + struct + { + // The value of GPU side PUT index. + // Indirect work submission introduces delay between updating the CPU + // put when ending a push, and updating the GPU visible value via + // indirect work launch. It is used to order multiple pending indirect + // work launches to match the order of push end-s that triggered them. + volatile NvU32 gpu_put; + + // Static pushbuffer for channels with static schedule (WLC/LCIC) + uvm_rm_mem_t *static_pb_protected_vidmem; + + // Static pushbuffer staging buffer for WLC + uvm_rm_mem_t *static_pb_unprotected_sysmem; + void *static_pb_unprotected_sysmem_cpu; + void *static_pb_unprotected_sysmem_auth_tag_cpu; + + // The above static locations are required by the WLC (and LCIC) + // schedule. Protected sysmem location completes WLC's independence + // from the pushbuffer allocator. + void *static_pb_protected_sysmem; + + // Static tracking semaphore notifier values + // Because of LCIC's fixed schedule, the secure semaphore release + // mechanism uses two additional static locations for incrementing the + // notifier values. See: + // . channel_semaphore_secure_release() + // . setup_lcic_schedule() + // . internal_channel_submit_work_wlc() + uvm_rm_mem_t *static_notifier_unprotected_sysmem; + NvU32 *static_notifier_entry_unprotected_sysmem_cpu; + NvU32 *static_notifier_exit_unprotected_sysmem_cpu; + uvm_gpu_address_t static_notifier_entry_unprotected_sysmem_gpu_va; + uvm_gpu_address_t static_notifier_exit_unprotected_sysmem_gpu_va; + + // Explicit location for push launch tag used by WLC. + // Encryption auth tags have to be located in unprotected sysmem. + void *launch_auth_tag_cpu; + NvU64 launch_auth_tag_gpu_va; + + // Used to decrypt the push back to protected sysmem. + // This happens when profilers register callbacks for migration data. + uvm_push_crypto_bundle_t *push_crypto_bundles; + + // Accompanying authentication tags for the crypto bundles + uvm_rm_mem_t *push_crypto_bundle_auth_tags; + } conf_computing; + // RM channel information union { @@ -275,7 +418,7 @@ unsigned num_channel_pools; // Mask containing the indexes of the usable Copy Engines. Each usable CE - // has a pool associated with it, see channel_manager_ce_pool + // has at least one pool associated with it. DECLARE_BITMAP(ce_mask, UVM_COPY_ENGINE_COUNT_MAX); struct @@ -313,13 +456,50 @@ // Create a channel manager for the GPU NV_STATUS uvm_channel_manager_create(uvm_gpu_t *gpu, uvm_channel_manager_t **manager_out); -void uvm_channel_pool_lock(uvm_channel_pool_t *pool); -void uvm_channel_pool_unlock(uvm_channel_pool_t *pool); -void uvm_channel_pool_assert_locked(uvm_channel_pool_t *pool); +static bool uvm_pool_type_is_valid(uvm_channel_pool_type_t pool_type) +{ + return (is_power_of_2(pool_type) && (pool_type < UVM_CHANNEL_POOL_TYPE_MASK)); +} + +static bool uvm_channel_pool_is_sec2(uvm_channel_pool_t *pool) +{ + UVM_ASSERT(uvm_pool_type_is_valid(pool->pool_type)); + + return (pool->pool_type == UVM_CHANNEL_POOL_TYPE_SEC2); +} + +static bool uvm_channel_pool_is_wlc(uvm_channel_pool_t *pool) +{ + UVM_ASSERT(uvm_pool_type_is_valid(pool->pool_type)); + + return (pool->pool_type == UVM_CHANNEL_POOL_TYPE_WLC); +} + +static bool uvm_channel_pool_is_lcic(uvm_channel_pool_t *pool) +{ + UVM_ASSERT(uvm_pool_type_is_valid(pool->pool_type)); + + return (pool->pool_type == UVM_CHANNEL_POOL_TYPE_LCIC); +} + +static bool uvm_channel_is_sec2(uvm_channel_t *channel) +{ + return uvm_channel_pool_is_sec2(channel->pool); +} + +static bool uvm_channel_is_wlc(uvm_channel_t *channel) +{ + return uvm_channel_pool_is_wlc(channel->pool); +} + +static bool uvm_channel_is_lcic(uvm_channel_t *channel) +{ + return uvm_channel_pool_is_lcic(channel->pool); +} static bool uvm_channel_pool_is_proxy(uvm_channel_pool_t *pool) { - UVM_ASSERT(pool->pool_type < UVM_CHANNEL_POOL_TYPE_MASK); + UVM_ASSERT(uvm_pool_type_is_valid(pool->pool_type)); return pool->pool_type == UVM_CHANNEL_POOL_TYPE_CE_PROXY; } @@ -329,12 +509,18 @@ return uvm_channel_pool_is_proxy(channel->pool); } +static bool uvm_channel_pool_is_ce(uvm_channel_pool_t *pool) +{ + return !uvm_channel_pool_is_sec2(pool); +} + static bool uvm_channel_is_ce(uvm_channel_t *channel) { - UVM_ASSERT(channel->pool->pool_type < UVM_CHANNEL_POOL_TYPE_MASK); - return (channel->pool->pool_type == UVM_CHANNEL_POOL_TYPE_CE) || uvm_channel_is_proxy(channel); + return uvm_channel_pool_is_ce(channel->pool); } +bool uvm_channel_pool_uses_mutex(uvm_channel_pool_t *pool); + // Proxy channels are used to push page tree related methods, so their channel // type is UVM_CHANNEL_TYPE_MEMOPS. static uvm_channel_type_t uvm_channel_proxy_channel_type(void) @@ -389,6 +575,13 @@ // beginning. NV_STATUS uvm_channel_manager_wait(uvm_channel_manager_t *manager); +// Check if WLC/LCIC mechanism is ready/setup +// Should only return false during initialization +static bool uvm_channel_manager_is_wlc_ready(uvm_channel_manager_t *manager) +{ + return (manager->pool_to_use.default_for_type[UVM_CHANNEL_TYPE_WLC] != NULL) && + (manager->pool_to_use.default_for_type[UVM_CHANNEL_TYPE_LCIC] != NULL); +} // Get the GPU VA of semaphore_channel's tracking semaphore within the VA space // associated with access_channel. // @@ -449,6 +642,10 @@ const char *uvm_channel_type_to_string(uvm_channel_type_t channel_type); const char *uvm_channel_pool_type_to_string(uvm_channel_pool_type_t channel_pool_type); +// Returns the number of available GPFIFO entries. The function internally +// acquires the channel pool lock. +NvU32 uvm_channel_get_available_gpfifo_entries(uvm_channel_t *channel); + void uvm_channel_print_pending_pushes(uvm_channel_t *channel); static uvm_gpu_t *uvm_channel_get_gpu(uvm_channel_t *channel) @@ -456,6 +653,11 @@ return channel->pool->manager->gpu; } +static uvm_pushbuffer_t *uvm_channel_get_pushbuffer(uvm_channel_t *channel) +{ + return channel->pool->manager->pushbuffer; +} + // Index of a channel within the owning pool static unsigned uvm_channel_index_in_pool(const uvm_channel_t *channel) { diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/kernel-open/nvidia-uvm/uvm_channel_test.c nvidia-open-gpu-kernel-modules-535.161.08/kernel-open/nvidia-uvm/uvm_channel_test.c --- nvidia-open-gpu-kernel-modules-525.147.05/kernel-open/nvidia-uvm/uvm_channel_test.c 2023-10-25 20:33:43.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/kernel-open/nvidia-uvm/uvm_channel_test.c 2024-03-05 22:26:06.000000000 +0000 @@ -60,6 +60,11 @@ gpu = uvm_va_space_find_first_gpu(va_space); TEST_CHECK_RET(gpu != NULL); + // TODO: Bug 3839176: the test is waived on Confidential Computing because + // it assumes that GPU can access system memory without using encryption. + if (uvm_conf_computing_mode_enabled(gpu)) + return NV_OK; + status = uvm_rm_mem_alloc_and_map_all(gpu, UVM_RM_MEM_TYPE_SYS, buffer_size, 0, &mem); TEST_CHECK_GOTO(status == NV_OK, done); @@ -69,7 +74,7 @@ status = uvm_push_begin(gpu->channel_manager, UVM_CHANNEL_TYPE_GPU_TO_CPU, &push, "Initial memset"); TEST_CHECK_GOTO(status == NV_OK, done); - gpu_va = uvm_rm_mem_get_gpu_va(mem, gpu, uvm_channel_is_proxy(push.channel)); + gpu_va = uvm_rm_mem_get_gpu_va(mem, gpu, uvm_channel_is_proxy(push.channel)).address; // Semaphore release as part of uvm_push_end() will do the membar uvm_push_set_flag(&push, UVM_PUSH_FLAG_NEXT_MEMBAR_NONE); @@ -104,7 +109,7 @@ value + 1); TEST_CHECK_GOTO(status == NV_OK, done); - gpu_va_base = uvm_rm_mem_get_gpu_va(mem, gpu, uvm_channel_is_proxy(push.channel)); + gpu_va_base = uvm_rm_mem_get_gpu_va(mem, gpu, uvm_channel_is_proxy(push.channel)).address; gpu_va_src = gpu_va_base + (value % values_count) * sizeof(NvU32); gpu_va_dst = gpu_va_base + ((value + 1) % values_count) * sizeof(NvU32); @@ -167,11 +172,12 @@ completed_value = uvm_channel_update_completed_value(channel); uvm_gpu_semaphore_set_payload(&channel->tracking_sem.semaphore, (NvU32)completed_value + 1); - TEST_CHECK_RET(uvm_global_get_status() == NV_OK); + TEST_NV_CHECK_RET(uvm_global_get_status()); uvm_channel_update_progress_all(channel); TEST_CHECK_RET(uvm_global_reset_fatal_error() == NV_ERR_INVALID_STATE); uvm_channel_manager_destroy(gpu->channel_manager); + // Destruction will hit the error again, so clear one more time. uvm_global_reset_fatal_error(); @@ -199,6 +205,9 @@ uvm_for_each_pool(pool, manager) { uvm_channel_t *channel; + // Skip LCIC channels as those can't accept any pushes + if (uvm_channel_pool_is_lcic(pool)) + continue; uvm_for_each_channel_in_pool(channel, pool) { NvU32 i; for (i = 0; i < 512; ++i) { @@ -340,8 +349,8 @@ return; is_proxy_channel = uvm_channel_is_proxy(push->channel); - counter_gpu_va = uvm_rm_mem_get_gpu_va(counter_mem, gpu, is_proxy_channel); - snapshot_gpu_va = uvm_rm_mem_get_gpu_va(snapshot_mem, gpu, is_proxy_channel) + index * 2 * sizeof(NvU32); + counter_gpu_va = uvm_rm_mem_get_gpu_va(counter_mem, gpu, is_proxy_channel).address; + snapshot_gpu_va = uvm_rm_mem_get_gpu_va(snapshot_mem, gpu, is_proxy_channel).address + index * 2 * sizeof(NvU32); // Copy the last and first counter to a snapshot for later verification. @@ -366,7 +375,7 @@ bool is_proxy_channel; is_proxy_channel = uvm_channel_is_proxy(push->channel); - counter_gpu_va = uvm_rm_mem_get_gpu_va(counter_mem, gpu, is_proxy_channel); + counter_gpu_va = uvm_rm_mem_get_gpu_va(counter_mem, gpu, is_proxy_channel).address; gpu->parent->ce_hal->memset_v_4(push, counter_gpu_va, value, count * sizeof(NvU32)); } @@ -426,7 +435,7 @@ UVM_ASSERT(rm_mem->size % 4 == 0); gpu = uvm_push_get_gpu(push); - gpu_va = uvm_rm_mem_get_gpu_va(rm_mem, gpu, uvm_channel_is_proxy(push->channel)); + gpu_va = uvm_rm_mem_get_gpu_va(rm_mem, gpu, uvm_channel_is_proxy(push->channel)).address; gpu->parent->ce_hal->memset_v_4(push, gpu_va, value, rm_mem->size); } @@ -671,6 +680,72 @@ return status; } +// The following test is inspired by uvm_push_test.c:test_concurrent_pushes. +// This test verifies that concurrent pushes using the same channel pool +// select different channels, when the Confidential Computing feature is +// enabled. +NV_STATUS test_conf_computing_channel_selection(uvm_va_space_t *va_space) +{ + NV_STATUS status = NV_OK; + uvm_channel_pool_t *pool; + uvm_push_t *pushes; + uvm_gpu_t *gpu; + NvU32 i; + NvU32 num_pushes; + + gpu = uvm_va_space_find_first_gpu(va_space); + + if (!uvm_conf_computing_mode_enabled(gpu)) + return NV_OK; + + uvm_thread_context_lock_disable_tracking(); + + for_each_va_space_gpu(gpu, va_space) { + uvm_channel_type_t channel_type; + + for (channel_type = 0; channel_type < UVM_CHANNEL_TYPE_COUNT; channel_type++) { + pool = gpu->channel_manager->pool_to_use.default_for_type[channel_type]; + TEST_CHECK_RET(pool != NULL); + + // Skip LCIC channels as those can't accept any pushes + if (uvm_channel_pool_is_lcic(pool)) + continue; + + if (pool->num_channels < 2) + continue; + + num_pushes = min(pool->num_channels, (NvU32)UVM_PUSH_MAX_CONCURRENT_PUSHES); + + pushes = uvm_kvmalloc_zero(sizeof(*pushes) * num_pushes); + TEST_CHECK_RET(pushes != NULL); + + for (i = 0; i < num_pushes; i++) { + uvm_push_t *push = &pushes[i]; + status = uvm_push_begin(gpu->channel_manager, channel_type, push, "concurrent push %u", i); + TEST_NV_CHECK_GOTO(status, error); + if (i > 0) + TEST_CHECK_GOTO(pushes[i-1].channel != push->channel, error); + } + for (i = 0; i < num_pushes; i++) { + uvm_push_t *push = &pushes[i]; + status = uvm_push_end_and_wait(push); + TEST_NV_CHECK_GOTO(status, error); + } + + uvm_kvfree(pushes); + } + } + + uvm_thread_context_lock_enable_tracking(); + + return status; +error: + uvm_thread_context_lock_enable_tracking(); + uvm_kvfree(pushes); + + return status; +} + NV_STATUS test_write_ctrl_gpfifo_noop(uvm_va_space_t *va_space) { uvm_gpu_t *gpu; @@ -682,6 +757,14 @@ uvm_for_each_pool(pool, manager) { uvm_channel_t *channel; + // Skip LCIC channels as those can't accept any pushes + if (uvm_channel_pool_is_lcic(pool)) + continue; + + // Skip WLC channels as those can't accept ctrl gpfifos + // after their schedule is set up + if (uvm_channel_pool_is_wlc(pool)) + continue; uvm_for_each_channel_in_pool(channel, pool) { NvU32 i; @@ -713,6 +796,14 @@ uvm_for_each_pool(pool, manager) { uvm_channel_t *channel; + // Skip LCIC channels as those can't accept any pushes + if (uvm_channel_pool_is_lcic(pool)) + continue; + + // Skip WLC channels as those can't accept ctrl gpfifos + // after their schedule is set up + if (uvm_channel_pool_is_wlc(pool)) + continue; uvm_for_each_channel_in_pool(channel, pool) { NvU32 i; uvm_push_t push; @@ -742,22 +833,6 @@ return NV_OK; } -static NvU32 get_available_gpfifo_entries(uvm_channel_t *channel) -{ - NvU32 pending_entries; - - uvm_channel_pool_lock(channel->pool); - - if (channel->cpu_put >= channel->gpu_get) - pending_entries = channel->cpu_put - channel->gpu_get; - else - pending_entries = channel->cpu_put + channel->num_gpfifo_entries - channel->gpu_get; - - uvm_channel_pool_unlock(channel->pool); - - return channel->num_gpfifo_entries - pending_entries - 1; -} - NV_STATUS test_write_ctrl_gpfifo_tight(uvm_va_space_t *va_space) { NV_STATUS status = NV_OK; @@ -770,9 +845,15 @@ NvU64 entry; uvm_push_t push; + gpu = uvm_va_space_find_first_gpu(va_space); + + // TODO: Bug 3839176: the test is waived on Confidential Computing because + // it assumes that GPU can access system memory without using encryption. + if (uvm_conf_computing_mode_enabled(gpu)) + return NV_OK; + for_each_va_space_gpu(gpu, va_space) { uvm_channel_manager_t *manager = gpu->channel_manager; - gpu = manager->gpu; TEST_NV_CHECK_RET(uvm_rm_mem_alloc_and_map_cpu(gpu, UVM_RM_MEM_TYPE_SYS, sizeof(*cpu_ptr), 0, &mem)); cpu_ptr = uvm_rm_mem_get_cpu_va(mem); @@ -790,6 +871,12 @@ gpu->parent->host_hal->semaphore_acquire(&push, gpu_va, 1); uvm_push_end(&push); + // Flush all completed entries from the GPFIFO ring buffer. This test + // requires this flush because we verify (below with + // uvm_channel_get_available_gpfifo_entries) the number of free entries + // in the channel. + uvm_channel_update_progress_all(channel); + // Populate the remaining GPFIFO entries, leaving 2 slots available. // 2 available entries + 1 semaphore acquire (above) + 1 spare entry to // indicate a terminal condition for the GPFIFO ringbuffer, therefore we @@ -799,7 +886,7 @@ uvm_push_end(&push); } - TEST_CHECK_GOTO(get_available_gpfifo_entries(channel) == 2, error); + TEST_CHECK_GOTO(uvm_channel_get_available_gpfifo_entries(channel) == 2, error); // We should have room for the control GPFIFO and the subsequent // semaphore release. @@ -858,6 +945,9 @@ uvm_for_each_pool(pool, manager) { uvm_channel_t *channel; + // Skip LCIC channels as those can't accept any pushes + if (uvm_channel_pool_is_lcic(pool)) + continue; uvm_for_each_channel_in_pool(channel, pool) { NvU32 i; uvm_push_t push; @@ -905,6 +995,10 @@ if (status != NV_OK) goto done; + status = test_conf_computing_channel_selection(va_space); + if (status != NV_OK) + goto done; + // The following tests have side effects, they reset the GPU's // channel_manager. status = test_channel_pushbuffer_extension_base(va_space); @@ -935,7 +1029,7 @@ static NV_STATUS uvm_test_channel_stress_stream(uvm_va_space_t *va_space, const UVM_TEST_CHANNEL_STRESS_PARAMS *params) { - NV_STATUS status; + NV_STATUS status = NV_OK; if (params->iterations == 0 || params->num_streams == 0) return NV_ERR_INVALID_PARAMETER; @@ -945,13 +1039,16 @@ uvm_mutex_lock(&g_uvm_global.global_lock); uvm_va_space_down_read_rm(va_space); + // TODO: Bug 3839176: the test is waived on Confidential Computing because + // it assumes that GPU can access system memory without using encryption. + if (uvm_conf_computing_mode_enabled(uvm_va_space_find_first_gpu(va_space))) + goto done; + status = stress_test_all_gpus_in_va(va_space, params->num_streams, params->iterations, params->seed, params->verbose); - if (status != NV_OK) - goto done; done: uvm_va_space_up_read_rm(va_space); diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/kernel-open/nvidia-uvm/uvm_common.h nvidia-open-gpu-kernel-modules-535.161.08/kernel-open/nvidia-uvm/uvm_common.h --- nvidia-open-gpu-kernel-modules-525.147.05/kernel-open/nvidia-uvm/uvm_common.h 2023-10-25 20:33:27.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/kernel-open/nvidia-uvm/uvm_common.h 2024-03-05 22:25:42.000000000 +0000 @@ -21,8 +21,8 @@ *******************************************************************************/ -#ifndef _UVM_COMMON_H -#define _UVM_COMMON_H +#ifndef __UVM_COMMON_H__ +#define __UVM_COMMON_H__ #ifdef DEBUG #define UVM_IS_DEBUG() 1 @@ -211,6 +211,11 @@ { return memcmp(uuid, &NV_PROCESSOR_UUID_CPU_DEFAULT, sizeof(*uuid)) == 0; } +#define UVM_SIZE_1KB (1024ULL) +#define UVM_SIZE_1MB (1024 * UVM_SIZE_1KB) +#define UVM_SIZE_1GB (1024 * UVM_SIZE_1MB) +#define UVM_SIZE_1TB (1024 * UVM_SIZE_1GB) +#define UVM_SIZE_1PB (1024 * UVM_SIZE_1TB) #define UVM_ALIGN_DOWN(x, a) ({ \ typeof(x) _a = a; \ @@ -347,6 +352,22 @@ NvHandle user_object; } uvm_rm_user_object_t; +typedef enum +{ + UVM_FD_UNINITIALIZED, + UVM_FD_INITIALIZING, + UVM_FD_VA_SPACE, + UVM_FD_MM, + UVM_FD_COUNT +} uvm_fd_type_t; + +// This should be large enough to fit the valid values from uvm_fd_type_t above. +// Note we can't use order_base_2(UVM_FD_COUNT) to define this because our code +// coverage tool fails due when the preprocessor expands that to a huge mess of +// ternary operators. +#define UVM_FD_TYPE_BITS 2 +#define UVM_FD_TYPE_MASK ((1UL << UVM_FD_TYPE_BITS) - 1) + // Macro used to compare two values for types that support less than operator. // It returns -1 if a < b, 1 if a > b and 0 if a == 0 #define UVM_CMP_DEFAULT(a,b) \ @@ -369,6 +390,14 @@ // file. A NULL input returns false. bool uvm_file_is_nvidia_uvm(struct file *filp); +// Returns the type of data filp->private_data contains to and if ptr_val != +// NULL returns the value of the pointer. +uvm_fd_type_t uvm_fd_type(struct file *filp, void **ptr_val); + +// Returns the pointer stored in filp->private_data if the type +// matches, otherwise returns NULL. +void *uvm_fd_get_type(struct file *filp, uvm_fd_type_t type); + // Reads the first word in the supplied struct page. static inline void uvm_touch_page(struct page *page) { @@ -381,4 +410,43 @@ kunmap(page); } -#endif /* _UVM_COMMON_H */ +// Return true if the VMA is one used by UVM managed allocations. +bool uvm_vma_is_managed(struct vm_area_struct *vma); + +static bool uvm_platform_uses_canonical_form_address(void) +{ + if (NVCPU_IS_PPC64LE) + return false; + + return true; +} + +// Similar to the GPU MMU HAL num_va_bits(), it returns the CPU's num_va_bits(). +static NvU32 uvm_cpu_num_va_bits(void) +{ + return fls64(TASK_SIZE - 1) + 1; +} + +// Return the unaddressable range in a num_va_bits-wide VA space, [first, outer) +static void uvm_get_unaddressable_range(NvU32 num_va_bits, NvU64 *first, NvU64 *outer) +{ + UVM_ASSERT(num_va_bits < 64); + UVM_ASSERT(first); + UVM_ASSERT(outer); + + if (uvm_platform_uses_canonical_form_address()) { + *first = 1ULL << (num_va_bits - 1); + *outer = (NvU64)((NvS64)(1ULL << 63) >> (64 - num_va_bits)); + } + else { + *first = 1ULL << num_va_bits; + *outer = ~0Ull; + } +} + +static void uvm_cpu_get_unaddressable_range(NvU64 *first, NvU64 *outer) +{ + return uvm_get_unaddressable_range(uvm_cpu_num_va_bits(), first, outer); +} + +#endif /* __UVM_COMMON_H__ */ diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/kernel-open/nvidia-uvm/uvm_conf_computing.c nvidia-open-gpu-kernel-modules-535.161.08/kernel-open/nvidia-uvm/uvm_conf_computing.c --- nvidia-open-gpu-kernel-modules-525.147.05/kernel-open/nvidia-uvm/uvm_conf_computing.c 1970-01-01 00:00:00.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/kernel-open/nvidia-uvm/uvm_conf_computing.c 2024-03-05 22:25:40.000000000 +0000 @@ -0,0 +1,501 @@ +/******************************************************************************* + Copyright (c) 2021-2023 NVIDIA Corporation + + Permission is hereby granted, free of charge, to any person obtaining a copy + of this software and associated documentation files (the "Software"), to + deal in the Software without restriction, including without limitation the + rights to use, copy, modify, merge, publish, distribute, sublicense, and/or + sell copies of the Software, and to permit persons to whom the Software is + furnished to do so, subject to the following conditions: + + The above copyright notice and this permission notice shall be + included in all copies or substantial portions of the Software. + + THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + DEALINGS IN THE SOFTWARE. + +*******************************************************************************/ + +#include "uvm_common.h" +#include "uvm_global.h" +#include "uvm_conf_computing.h" +#include "uvm_kvmalloc.h" +#include "uvm_gpu.h" +#include "uvm_hal.h" +#include "uvm_mem.h" +#include "uvm_processors.h" +#include "uvm_tracker.h" +#include "nv_uvm_interface.h" +#include "uvm_va_block.h" + + +static UvmGpuConfComputeMode uvm_conf_computing_get_mode(const uvm_parent_gpu_t *parent) +{ + return parent->rm_info.gpuConfComputeCaps.mode; +} + +bool uvm_conf_computing_mode_enabled_parent(const uvm_parent_gpu_t *parent) +{ + return uvm_conf_computing_get_mode(parent) != UVM_GPU_CONF_COMPUTE_MODE_NONE; +} + +bool uvm_conf_computing_mode_enabled(const uvm_gpu_t *gpu) +{ + return uvm_conf_computing_mode_enabled_parent(gpu->parent); +} + +bool uvm_conf_computing_mode_is_hcc(const uvm_gpu_t *gpu) +{ + return uvm_conf_computing_get_mode(gpu->parent) == UVM_GPU_CONF_COMPUTE_MODE_HCC; +} + +void uvm_conf_computing_check_parent_gpu(const uvm_parent_gpu_t *parent) +{ + uvm_gpu_t *first_gpu; + + uvm_assert_mutex_locked(&g_uvm_global.global_lock); + + // The Confidential Computing state of the GPU should match that of the + // system. + UVM_ASSERT(uvm_conf_computing_mode_enabled_parent(parent) == g_uvm_global.conf_computing_enabled); + + // TODO: Bug 2844714: since we have no routine to traverse parent GPUs, + // find first child GPU and get its parent. + first_gpu = uvm_global_processor_mask_find_first_gpu(&g_uvm_global.retained_gpus); + if (first_gpu == NULL) + return; + + // All GPUs derive Confidential Computing status from their parent. By + // current policy all parent GPUs have identical Confidential Computing + // status. + UVM_ASSERT(uvm_conf_computing_get_mode(parent) == uvm_conf_computing_get_mode(first_gpu->parent)); +} + +static void dma_buffer_destroy_locked(uvm_conf_computing_dma_buffer_pool_t *dma_buffer_pool, + uvm_conf_computing_dma_buffer_t *dma_buffer) +{ + uvm_assert_mutex_locked(&dma_buffer_pool->lock); + + list_del(&dma_buffer->node); + uvm_tracker_wait_deinit(&dma_buffer->tracker); + + uvm_mem_free(dma_buffer->alloc); + uvm_mem_free(dma_buffer->auth_tag); + uvm_kvfree(dma_buffer); +} + +static uvm_gpu_t *dma_buffer_pool_to_gpu(uvm_conf_computing_dma_buffer_pool_t *dma_buffer_pool) +{ + return container_of(dma_buffer_pool, uvm_gpu_t, conf_computing.dma_buffer_pool); +} + +// Allocate and map a new DMA stage buffer to CPU and GPU (VA) +static NV_STATUS dma_buffer_create(uvm_conf_computing_dma_buffer_pool_t *dma_buffer_pool, + uvm_conf_computing_dma_buffer_t **dma_buffer_out) +{ + uvm_gpu_t *dma_owner; + uvm_conf_computing_dma_buffer_t *dma_buffer; + uvm_mem_t *alloc = NULL; + NV_STATUS status = NV_OK; + size_t auth_tags_size = (UVM_CONF_COMPUTING_DMA_BUFFER_SIZE / PAGE_SIZE) * UVM_CONF_COMPUTING_AUTH_TAG_SIZE; + + dma_buffer = uvm_kvmalloc_zero(sizeof(*dma_buffer)); + if (!dma_buffer) + return NV_ERR_NO_MEMORY; + + dma_owner = dma_buffer_pool_to_gpu(dma_buffer_pool); + uvm_tracker_init(&dma_buffer->tracker); + INIT_LIST_HEAD(&dma_buffer->node); + + status = uvm_mem_alloc_sysmem_dma_and_map_cpu_kernel(UVM_CONF_COMPUTING_DMA_BUFFER_SIZE, dma_owner, NULL, &alloc); + if (status != NV_OK) + goto err; + + dma_buffer->alloc = alloc; + + status = uvm_mem_map_gpu_kernel(alloc, dma_owner); + if (status != NV_OK) + goto err; + + status = uvm_mem_alloc_sysmem_dma_and_map_cpu_kernel(auth_tags_size, dma_owner, NULL, &alloc); + if (status != NV_OK) + goto err; + + dma_buffer->auth_tag = alloc; + + status = uvm_mem_map_gpu_kernel(alloc, dma_owner); + if (status != NV_OK) + goto err; + + *dma_buffer_out = dma_buffer; + + return status; + +err: + dma_buffer_destroy_locked(dma_buffer_pool, dma_buffer); + return status; +} + +void uvm_conf_computing_dma_buffer_pool_sync(uvm_conf_computing_dma_buffer_pool_t *dma_buffer_pool) +{ + uvm_conf_computing_dma_buffer_t *dma_buffer; + + if (dma_buffer_pool->num_dma_buffers == 0) + return; + + uvm_mutex_lock(&dma_buffer_pool->lock); + list_for_each_entry(dma_buffer, &dma_buffer_pool->free_dma_buffers, node) + uvm_tracker_wait(&dma_buffer->tracker); + uvm_mutex_unlock(&dma_buffer_pool->lock); +} + +static void conf_computing_dma_buffer_pool_deinit(uvm_conf_computing_dma_buffer_pool_t *dma_buffer_pool) +{ + uvm_conf_computing_dma_buffer_t *dma_buffer; + uvm_conf_computing_dma_buffer_t *next_buff; + + if (dma_buffer_pool->num_dma_buffers == 0) + return; + + // Because the pool is teared down at the same time the GPU is unregistered + // the lock is required only to quiet assertions not for functional reasons + // see dma_buffer_destroy_locked()). + uvm_mutex_lock(&dma_buffer_pool->lock); + + list_for_each_entry_safe(dma_buffer, next_buff, &dma_buffer_pool->free_dma_buffers, node) { + dma_buffer_destroy_locked(dma_buffer_pool, dma_buffer); + dma_buffer_pool->num_dma_buffers--; + } + + UVM_ASSERT(dma_buffer_pool->num_dma_buffers == 0); + UVM_ASSERT(list_empty(&dma_buffer_pool->free_dma_buffers)); + uvm_mutex_unlock(&dma_buffer_pool->lock); +} + +static void dma_buffer_pool_add(uvm_conf_computing_dma_buffer_pool_t *dma_buffer_pool, + uvm_conf_computing_dma_buffer_t *dma_buffer) +{ + uvm_assert_mutex_locked(&dma_buffer_pool->lock); + list_add_tail(&dma_buffer->node, &dma_buffer_pool->free_dma_buffers); +} + +static NV_STATUS conf_computing_dma_buffer_pool_init(uvm_conf_computing_dma_buffer_pool_t *dma_buffer_pool) +{ + size_t i; + uvm_gpu_t *gpu; + size_t num_dma_buffers = 32; + NV_STATUS status = NV_OK; + + UVM_ASSERT(dma_buffer_pool->num_dma_buffers == 0); + + gpu = dma_buffer_pool_to_gpu(dma_buffer_pool); + + UVM_ASSERT(uvm_conf_computing_mode_enabled(gpu)); + + INIT_LIST_HEAD(&dma_buffer_pool->free_dma_buffers); + uvm_mutex_init(&dma_buffer_pool->lock, UVM_LOCK_ORDER_CONF_COMPUTING_DMA_BUFFER_POOL); + dma_buffer_pool->num_dma_buffers = num_dma_buffers; + + uvm_mutex_lock(&dma_buffer_pool->lock); + for (i = 0; i < num_dma_buffers; i++) { + uvm_conf_computing_dma_buffer_t *dma_buffer; + + status = dma_buffer_create(dma_buffer_pool, &dma_buffer); + if (status != NV_OK) + break; + + dma_buffer_pool_add(dma_buffer_pool, dma_buffer); + } + uvm_mutex_unlock(&dma_buffer_pool->lock); + + if (i < num_dma_buffers) + conf_computing_dma_buffer_pool_deinit(dma_buffer_pool); + + return status; +} + +static NV_STATUS dma_buffer_pool_expand_locked(uvm_conf_computing_dma_buffer_pool_t *dma_buffer_pool) +{ + size_t i; + uvm_gpu_t *gpu; + size_t nb_to_alloc; + NV_STATUS status = NV_OK; + UVM_ASSERT(dma_buffer_pool->num_dma_buffers > 0); + + gpu = dma_buffer_pool_to_gpu(dma_buffer_pool); + nb_to_alloc = dma_buffer_pool->num_dma_buffers; + for (i = 0; i < nb_to_alloc; ++i) { + uvm_conf_computing_dma_buffer_t *dma_buffer; + + status = dma_buffer_create(dma_buffer_pool, &dma_buffer); + if (status != NV_OK) + break; + + dma_buffer_pool_add(dma_buffer_pool, dma_buffer); + } + + dma_buffer_pool->num_dma_buffers += i; + + if (i == 0) + return status; + + return NV_OK; +} + +NV_STATUS uvm_conf_computing_dma_buffer_alloc(uvm_conf_computing_dma_buffer_pool_t *dma_buffer_pool, + uvm_conf_computing_dma_buffer_t **dma_buffer_out, + uvm_tracker_t *out_tracker) +{ + uvm_conf_computing_dma_buffer_t *dma_buffer = NULL; + NV_STATUS status; + + UVM_ASSERT(dma_buffer_pool->num_dma_buffers > 0); + + // TODO: Bug 3385623: Heuristically expand DMA memory pool + uvm_mutex_lock(&dma_buffer_pool->lock); + if (list_empty(&dma_buffer_pool->free_dma_buffers)) { + status = dma_buffer_pool_expand_locked(dma_buffer_pool); + + if (status != NV_OK) { + uvm_mutex_unlock(&dma_buffer_pool->lock); + return status; + } + } + + // We're guaranteed that at least one DMA stage buffer is available at this + // point. + dma_buffer = list_first_entry(&dma_buffer_pool->free_dma_buffers, uvm_conf_computing_dma_buffer_t, node); + list_del_init(&dma_buffer->node); + uvm_mutex_unlock(&dma_buffer_pool->lock); + + status = uvm_tracker_wait_for_other_gpus(&dma_buffer->tracker, dma_buffer->alloc->dma_owner); + if (status != NV_OK) + goto error; + + if (out_tracker) + status = uvm_tracker_add_tracker_safe(out_tracker, &dma_buffer->tracker); + else + status = uvm_tracker_wait(&dma_buffer->tracker); + + if (status != NV_OK) + goto error; + + uvm_page_mask_zero(&dma_buffer->encrypted_page_mask); + *dma_buffer_out = dma_buffer; + + return status; + +error: + uvm_tracker_deinit(&dma_buffer->tracker); + uvm_conf_computing_dma_buffer_free(dma_buffer_pool, dma_buffer, NULL); + return status; +} + +void uvm_conf_computing_dma_buffer_free(uvm_conf_computing_dma_buffer_pool_t *dma_buffer_pool, + uvm_conf_computing_dma_buffer_t *dma_buffer, + uvm_tracker_t *tracker) +{ + + NV_STATUS status; + + if (!dma_buffer) + return; + + UVM_ASSERT(dma_buffer_pool->num_dma_buffers > 0); + + uvm_tracker_remove_completed(&dma_buffer->tracker); + if (tracker) { + uvm_tracker_remove_completed(tracker); + status = uvm_tracker_add_tracker_safe(&dma_buffer->tracker, tracker); + if (status != NV_OK) + UVM_ASSERT(status == uvm_global_get_status()); + } + + uvm_mutex_lock(&dma_buffer_pool->lock); + dma_buffer_pool_add(dma_buffer_pool, dma_buffer); + uvm_mutex_unlock(&dma_buffer_pool->lock); +} + +static void dummy_iv_mem_deinit(uvm_gpu_t *gpu) +{ + uvm_mem_free(gpu->conf_computing.iv_mem); +} + +static NV_STATUS dummy_iv_mem_init(uvm_gpu_t *gpu) +{ + NV_STATUS status; + + if (!uvm_conf_computing_mode_is_hcc(gpu)) + return NV_OK; + + status = uvm_mem_alloc_sysmem_dma(sizeof(UvmCslIv), gpu, NULL, &gpu->conf_computing.iv_mem); + if (status != NV_OK) + return status; + + status = uvm_mem_map_gpu_kernel(gpu->conf_computing.iv_mem, gpu); + if (status != NV_OK) + goto error; + + return NV_OK; + +error: + dummy_iv_mem_deinit(gpu); + return status; +} + +NV_STATUS uvm_conf_computing_gpu_init(uvm_gpu_t *gpu) +{ + NV_STATUS status; + + if (!uvm_conf_computing_mode_enabled(gpu)) + return NV_OK; + + status = conf_computing_dma_buffer_pool_init(&gpu->conf_computing.dma_buffer_pool); + if (status != NV_OK) + return status; + + status = dummy_iv_mem_init(gpu); + if (status != NV_OK) + goto error; + + return NV_OK; + +error: + uvm_conf_computing_gpu_deinit(gpu); + return status; +} + +void uvm_conf_computing_gpu_deinit(uvm_gpu_t *gpu) +{ + dummy_iv_mem_deinit(gpu); + conf_computing_dma_buffer_pool_deinit(&gpu->conf_computing.dma_buffer_pool); +} + +void uvm_conf_computing_log_gpu_encryption(uvm_channel_t *channel, UvmCslIv *iv) +{ + NV_STATUS status; + + uvm_mutex_lock(&channel->csl.ctx_lock); + status = nvUvmInterfaceCslIncrementIv(&channel->csl.ctx, UVM_CSL_OPERATION_DECRYPT, 1, iv); + uvm_mutex_unlock(&channel->csl.ctx_lock); + + // TODO: Bug 4014720: If nvUvmInterfaceCslIncrementIv returns with + // NV_ERR_INSUFFICIENT_RESOURCES then the IV needs to be rotated via + // nvUvmInterfaceCslRotateIv. + UVM_ASSERT(status == NV_OK); +} + +void uvm_conf_computing_acquire_encryption_iv(uvm_channel_t *channel, UvmCslIv *iv) +{ + NV_STATUS status; + + uvm_mutex_lock(&channel->csl.ctx_lock); + status = nvUvmInterfaceCslIncrementIv(&channel->csl.ctx, UVM_CSL_OPERATION_ENCRYPT, 1, iv); + uvm_mutex_unlock(&channel->csl.ctx_lock); + + // TODO: Bug 4014720: If nvUvmInterfaceCslIncrementIv returns with + // NV_ERR_INSUFFICIENT_RESOURCES then the IV needs to be rotated via + // nvUvmInterfaceCslRotateIv. + UVM_ASSERT(status == NV_OK); +} + +void uvm_conf_computing_cpu_encrypt(uvm_channel_t *channel, + void *dst_cipher, + const void *src_plain, + UvmCslIv *encrypt_iv, + size_t size, + void *auth_tag_buffer) +{ + NV_STATUS status; + + UVM_ASSERT(size); + + uvm_mutex_lock(&channel->csl.ctx_lock); + status = nvUvmInterfaceCslEncrypt(&channel->csl.ctx, + size, + (NvU8 const *) src_plain, + encrypt_iv, + (NvU8 *) dst_cipher, + (NvU8 *) auth_tag_buffer); + uvm_mutex_unlock(&channel->csl.ctx_lock); + + // nvUvmInterfaceCslEncrypt fails when a 64-bit encryption counter + // overflows. This is not supposed to happen on CC. + UVM_ASSERT(status == NV_OK); +} + +NV_STATUS uvm_conf_computing_cpu_decrypt(uvm_channel_t *channel, + void *dst_plain, + const void *src_cipher, + const UvmCslIv *src_iv, + size_t size, + const void *auth_tag_buffer) +{ + NV_STATUS status; + + uvm_mutex_lock(&channel->csl.ctx_lock); + status = nvUvmInterfaceCslDecrypt(&channel->csl.ctx, + size, + (const NvU8 *) src_cipher, + src_iv, + (NvU8 *) dst_plain, + NULL, + 0, + (const NvU8 *) auth_tag_buffer); + uvm_mutex_unlock(&channel->csl.ctx_lock); + + return status; +} + +NV_STATUS uvm_conf_computing_fault_decrypt(uvm_parent_gpu_t *parent_gpu, + void *dst_plain, + const void *src_cipher, + const void *auth_tag_buffer, + NvU8 valid) +{ + NV_STATUS status; + + // There is no dedicated lock for the CSL context associated with replayable + // faults. The mutual exclusion required by the RM CSL API is enforced by + // relying on the GPU replayable service lock (ISR lock), since fault + // decryption is invoked as part of fault servicing. + UVM_ASSERT(uvm_sem_is_locked(&parent_gpu->isr.replayable_faults.service_lock)); + + UVM_ASSERT(!uvm_parent_gpu_replayable_fault_buffer_is_uvm_owned(parent_gpu)); + + status = nvUvmInterfaceCslDecrypt(&parent_gpu->fault_buffer_info.rm_info.replayable.cslCtx, + parent_gpu->fault_buffer_hal->entry_size(parent_gpu), + (const NvU8 *) src_cipher, + NULL, + (NvU8 *) dst_plain, + &valid, + sizeof(valid), + (const NvU8 *) auth_tag_buffer); + + if (status != NV_OK) + UVM_ERR_PRINT("nvUvmInterfaceCslDecrypt() failed: %s, GPU %s\n", nvstatusToString(status), parent_gpu->name); + + return status; +} + +void uvm_conf_computing_fault_increment_decrypt_iv(uvm_parent_gpu_t *parent_gpu, NvU64 increment) +{ + NV_STATUS status; + + // See comment in uvm_conf_computing_fault_decrypt + UVM_ASSERT(uvm_sem_is_locked(&parent_gpu->isr.replayable_faults.service_lock)); + + UVM_ASSERT(!uvm_parent_gpu_replayable_fault_buffer_is_uvm_owned(parent_gpu)); + + status = nvUvmInterfaceCslIncrementIv(&parent_gpu->fault_buffer_info.rm_info.replayable.cslCtx, + UVM_CSL_OPERATION_DECRYPT, + increment, + NULL); + + UVM_ASSERT(status == NV_OK); +} diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/kernel-open/nvidia-uvm/uvm_conf_computing.h nvidia-open-gpu-kernel-modules-535.161.08/kernel-open/nvidia-uvm/uvm_conf_computing.h --- nvidia-open-gpu-kernel-modules-525.147.05/kernel-open/nvidia-uvm/uvm_conf_computing.h 1970-01-01 00:00:00.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/kernel-open/nvidia-uvm/uvm_conf_computing.h 2024-03-05 22:25:40.000000000 +0000 @@ -0,0 +1,202 @@ +/******************************************************************************* + Copyright (c) 2021-2023 NVIDIA Corporation + + Permission is hereby granted, free of charge, to any person obtaining a copy + of this software and associated documentation files (the "Software"), to + deal in the Software without restriction, including without limitation the + rights to use, copy, modify, merge, publish, distribute, sublicense, and/or + sell copies of the Software, and to permit persons to whom the Software is + furnished to do so, subject to the following conditions: + + The above copyright notice and this permission notice shall be + included in all copies or substantial portions of the Software. + + THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + DEALINGS IN THE SOFTWARE. + +*******************************************************************************/ + +#ifndef __UVM_CONF_COMPUTING_H__ +#define __UVM_CONF_COMPUTING_H__ + +#include "nv_uvm_types.h" +#include "uvm_forward_decl.h" +#include "uvm_lock.h" +#include "uvm_tracker.h" +#include "uvm_va_block_types.h" + +#include "linux/list.h" + +#define UVM_CONF_COMPUTING_AUTH_TAG_SIZE (UVM_CSL_CRYPT_AUTH_TAG_SIZE_BYTES) + +// An authentication tag pointer is required by HW to be 16-bytes aligned. +#define UVM_CONF_COMPUTING_AUTH_TAG_ALIGNMENT 16 + +// An IV pointer is required by HW to be 16-bytes aligned. +// +// Use sizeof(UvmCslIv) to refer to the IV size. +#define UVM_CONF_COMPUTING_IV_ALIGNMENT 16 + +// SEC2 decrypt operation buffers are required to be 16-bytes aligned. +#define UVM_CONF_COMPUTING_SEC2_BUF_ALIGNMENT 16 + +// CE encrypt/decrypt can be unaligned if the entire buffer lies in a single +// 32B segment. Otherwise, it needs to be 32B aligned. +#define UVM_CONF_COMPUTING_BUF_ALIGNMENT 32 + +#define UVM_CONF_COMPUTING_DMA_BUFFER_SIZE UVM_VA_BLOCK_SIZE + +// SEC2 supports at most a stream of 64 entries in the method stream for +// signing. Each entry is made of the method address and method data, therefore +// the maximum buffer size is: UVM_METHOD_SIZE * 2 * 64 = 512. +// UVM, however, won't use this amount of entries, in the worst case scenario, +// we push a semaphore_releases or a decrypt. A SEC2 semaphore_release uses 6 1U +// entries, whereas a SEC2 decrypt uses 10 1U entries. For 10 entries, +// UVM_METHOD_SIZE * 2 * 10 = 80. +#define UVM_CONF_COMPUTING_SIGN_BUF_MAX_SIZE 80 + +void uvm_conf_computing_check_parent_gpu(const uvm_parent_gpu_t *parent); + +bool uvm_conf_computing_mode_enabled_parent(const uvm_parent_gpu_t *parent); +bool uvm_conf_computing_mode_enabled(const uvm_gpu_t *gpu); +bool uvm_conf_computing_mode_is_hcc(const uvm_gpu_t *gpu); + +typedef struct +{ + // List of free DMA buffers (uvm_conf_computing_dma_buffer_t). + // A free DMA buffer can be grabbed anytime, though the tracker + // inside it may still have pending work. + struct list_head free_dma_buffers; + + // Used to grow the pool when full. + size_t num_dma_buffers; + + // Lock protecting the dma_buffer_pool + uvm_mutex_t lock; +} uvm_conf_computing_dma_buffer_pool_t; + +typedef struct +{ + // Backing DMA allocation + uvm_mem_t *alloc; + + // Used internally by the pool management code to track the state of + // a free buffer. + uvm_tracker_t tracker; + + // When the DMA buffer is used as the destination of a GPU encryption, SEC2 + // writes the authentication tag here. Later when the buffer is decrypted + // on the CPU the authentication tag is used again (read) for CSL to verify + // the authenticity. The allocation is big enough for one authentication + // tag per PAGE_SIZE page in the alloc buffer. + uvm_mem_t *auth_tag; + + // CSL supports out-of-order decryption, the decrypt IV is used similarly + // to the authentication tag. The allocation is big enough for one IV per + // PAGE_SIZE page in the alloc buffer. The granularity between the decrypt + // IV and authentication tag must match. + UvmCslIv decrypt_iv[(UVM_CONF_COMPUTING_DMA_BUFFER_SIZE / PAGE_SIZE)]; + + // Bitmap of the encrypted pages in the backing allocation + uvm_page_mask_t encrypted_page_mask; + + // See uvm_conf_computing_dma_pool lists + struct list_head node; +} uvm_conf_computing_dma_buffer_t; + +// Retrieve a DMA buffer from the given DMA allocation pool. +// NV_OK Stage buffer successfully retrieved +// NV_ERR_NO_MEMORY No free DMA buffers are available for grab, and +// expanding the memory pool to get new ones failed. +// +// out_dma_buffer is only valid if NV_OK is returned. The caller is responsible +// for calling uvm_conf_computing_dma_buffer_free once the operations on this +// buffer are done. +// When out_tracker is passed to the function, the buffer's dependencies are +// added to the tracker. The caller is guaranteed that all pending tracker +// entries come from the same GPU as the pool's owner. Before being able to use +// the DMA buffer, the caller is responsible for either acquiring or waiting +// on out_tracker. If out_tracker is NULL, the wait happens in the allocation +// itself. +// Upon success the encrypted_page_mask is cleared as part of the allocation. +NV_STATUS uvm_conf_computing_dma_buffer_alloc(uvm_conf_computing_dma_buffer_pool_t *dma_buffer_pool, + uvm_conf_computing_dma_buffer_t **out_dma_buffer, + uvm_tracker_t *out_tracker); + +// Free a DMA buffer to the DMA allocation pool. All DMA buffers must be freed +// prior to GPU deinit. +// +// The tracker is optional and a NULL tracker indicates that no new operation +// has been pushed for the buffer. A non-NULL tracker indicates any additional +// pending operations on the buffer pushed by the caller that need to be +// synchronized before freeing or re-using the buffer. +void uvm_conf_computing_dma_buffer_free(uvm_conf_computing_dma_buffer_pool_t *dma_buffer_pool, + uvm_conf_computing_dma_buffer_t *dma_buffer, + uvm_tracker_t *tracker); + +// Synchronize trackers in all entries in the GPU's DMA pool +void uvm_conf_computing_dma_buffer_pool_sync(uvm_conf_computing_dma_buffer_pool_t *dma_buffer_pool); + + +// Initialization and deinitialization of Confidential Computing data structures +// for the given GPU. +NV_STATUS uvm_conf_computing_gpu_init(uvm_gpu_t *gpu); +void uvm_conf_computing_gpu_deinit(uvm_gpu_t *gpu); + +// Logs encryption information from the GPU and returns the IV. +void uvm_conf_computing_log_gpu_encryption(uvm_channel_t *channel, UvmCslIv *iv); + +// Acquires next CPU encryption IV and returns it. +void uvm_conf_computing_acquire_encryption_iv(uvm_channel_t *channel, UvmCslIv *iv); + +// CPU side encryption helper with explicit IV, which is obtained from +// uvm_conf_computing_acquire_encryption_iv. Without an explicit IV +// the function uses the next IV in order. Encrypts data in src_plain and +// write the cipher text in dst_cipher. src_plain and dst_cipher can't overlap. +// The IV is invalidated and can't be used again after this operation. +void uvm_conf_computing_cpu_encrypt(uvm_channel_t *channel, + void *dst_cipher, + const void *src_plain, + UvmCslIv *encrypt_iv, + size_t size, + void *auth_tag_buffer); + +// CPU side decryption helper. Decrypts data from src_cipher and writes the +// plain text in dst_plain. src_cipher and dst_plain can't overlap. IV obtained +// from uvm_conf_computing_log_gpu_encryption() needs to be be passed to src_iv. +NV_STATUS uvm_conf_computing_cpu_decrypt(uvm_channel_t *channel, + void *dst_plain, + const void *src_cipher, + const UvmCslIv *src_iv, + size_t size, + const void *auth_tag_buffer); + +// CPU decryption of a single replayable fault, encrypted by GSP-RM. +// +// Replayable fault decryption depends not only on the encrypted fault contents, +// and the authentication tag, but also on the plaintext valid bit associated +// with the fault. +// +// When decrypting data previously encrypted by the Copy Engine, use +// uvm_conf_computing_cpu_decrypt instead. +// +// Locking: this function must be invoked while holding the replayable ISR lock. +NV_STATUS uvm_conf_computing_fault_decrypt(uvm_parent_gpu_t *parent_gpu, + void *dst_plain, + const void *src_cipher, + const void *auth_tag_buffer, + NvU8 valid); + +// Increment the CPU-side decrypt IV of the CSL context associated with +// replayable faults. The function is a no-op if the given increment is zero. +// +// The IV associated with a fault CSL context is a 64-bit counter. +// +// Locking: this function must be invoked while holding the replayable ISR lock. +void uvm_conf_computing_fault_increment_decrypt_iv(uvm_parent_gpu_t *parent_gpu, NvU64 increment); +#endif // __UVM_CONF_COMPUTING_H__ diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/kernel-open/nvidia-uvm/uvm_forward_decl.h nvidia-open-gpu-kernel-modules-535.161.08/kernel-open/nvidia-uvm/uvm_forward_decl.h --- nvidia-open-gpu-kernel-modules-525.147.05/kernel-open/nvidia-uvm/uvm_forward_decl.h 2023-10-25 20:33:34.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/kernel-open/nvidia-uvm/uvm_forward_decl.h 2024-03-05 22:25:51.000000000 +0000 @@ -28,6 +28,8 @@ typedef struct uvm_gpu_struct uvm_gpu_t; typedef struct uvm_parent_gpu_struct uvm_parent_gpu_t; +typedef struct uvm_gpu_chunk_struct uvm_gpu_chunk_t; +typedef struct uvm_cpu_chunk_struct uvm_cpu_chunk_t; typedef struct uvm_rm_mem_struct uvm_rm_mem_t; typedef struct uvm_mem_struct uvm_mem_t; typedef struct uvm_host_hal_struct uvm_host_hal_t; @@ -35,6 +37,7 @@ typedef struct uvm_arch_hal_struct uvm_arch_hal_t; typedef struct uvm_fault_buffer_hal_struct uvm_fault_buffer_hal_t; typedef struct uvm_access_counter_buffer_hal_struct uvm_access_counter_buffer_hal_t; +typedef struct uvm_sec2_hal_struct uvm_sec2_hal_t; typedef struct uvm_gpu_semaphore_struct uvm_gpu_semaphore_t; typedef struct uvm_gpu_tracking_semaphore_struct uvm_gpu_tracking_semaphore_t; typedef struct uvm_gpu_semaphore_pool_struct uvm_gpu_semaphore_pool_t; @@ -47,6 +50,7 @@ typedef struct uvm_user_channel_struct uvm_user_channel_t; typedef struct uvm_push_struct uvm_push_t; typedef struct uvm_push_info_struct uvm_push_info_t; +typedef struct uvm_push_crypto_bundle_struct uvm_push_crypto_bundle_t; typedef struct uvm_push_acquire_info_struct uvm_push_acquire_info_t; typedef struct uvm_pushbuffer_struct uvm_pushbuffer_t; typedef struct uvm_gpfifo_entry_struct uvm_gpfifo_entry_t; @@ -56,6 +60,7 @@ typedef struct uvm_va_block_struct uvm_va_block_t; typedef struct uvm_va_block_test_struct uvm_va_block_test_t; typedef struct uvm_va_block_wrapper_struct uvm_va_block_wrapper_t; +typedef struct uvm_va_block_retry_struct uvm_va_block_retry_t; typedef struct uvm_va_space_struct uvm_va_space_t; typedef struct uvm_va_space_mm_struct uvm_va_space_mm_t; diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/kernel-open/nvidia-uvm/uvm_global.c nvidia-open-gpu-kernel-modules-535.161.08/kernel-open/nvidia-uvm/uvm_global.c --- nvidia-open-gpu-kernel-modules-525.147.05/kernel-open/nvidia-uvm/uvm_global.c 2023-10-25 20:33:32.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/kernel-open/nvidia-uvm/uvm_global.c 2024-03-05 22:25:49.000000000 +0000 @@ -71,11 +71,6 @@ } } -static void sev_init(const UvmPlatformInfo *platform_info) -{ - g_uvm_global.sev_enabled = platform_info->sevEnabled; -} - NV_STATUS uvm_global_init(void) { NV_STATUS status; @@ -124,8 +119,7 @@ uvm_ats_init(&platform_info); g_uvm_global.num_simulated_devices = 0; - - sev_init(&platform_info); + g_uvm_global.conf_computing_enabled = platform_info.confComputingEnabled; status = uvm_gpu_init(); if (status != NV_OK) { diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/kernel-open/nvidia-uvm/uvm_global.h nvidia-open-gpu-kernel-modules-535.161.08/kernel-open/nvidia-uvm/uvm_global.h --- nvidia-open-gpu-kernel-modules-525.147.05/kernel-open/nvidia-uvm/uvm_global.h 2023-10-25 20:33:32.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/kernel-open/nvidia-uvm/uvm_global.h 2024-03-05 22:25:48.000000000 +0000 @@ -1,5 +1,5 @@ /******************************************************************************* - Copyright (c) 2015-2021 NVIDIA Corporation + Copyright (c) 2015-2023 NVIDIA Corporation Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation files (the "Software"), to @@ -143,11 +143,16 @@ struct page *page; } unload_state; - // AMD Secure Encrypted Virtualization (SEV) status. True if VM has SEV - // enabled. This field is set once during global initialization - // (uvm_global_init), and can be read afterwards without acquiring any - // locks. - bool sev_enabled; + // True if the VM has AMD's SEV, or equivalent HW security extensions such + // as Intel's TDX, enabled. The flag is always false on the host. + // + // This value moves in tandem with that of Confidential Computing in the + // GPU(s) in all supported configurations, so it is used as a proxy for the + // Confidential Computing state. + // + // This field is set once during global initialization (uvm_global_init), + // and can be read afterwards without acquiring any locks. + bool conf_computing_enabled; }; // Initialize global uvm state @@ -191,6 +196,16 @@ g_uvm_global.parent_gpus[gpu_index] = NULL; } +// Get a parent gpu by its id. +// Returns a pointer to the parent GPU object, or NULL if not found. +// +// LOCKING: requires that you hold the gpu_table_lock, the global lock, or have +// retained at least one of the child GPUs. +static uvm_parent_gpu_t *uvm_parent_gpu_get(uvm_gpu_id_t id) +{ + return g_uvm_global.parent_gpus[uvm_id_gpu_index(id)]; +} + // Get a gpu by its global id. // Returns a pointer to the GPU object, or NULL if not found. // diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/kernel-open/nvidia-uvm/uvm_gpu.c nvidia-open-gpu-kernel-modules-535.161.08/kernel-open/nvidia-uvm/uvm_gpu.c --- nvidia-open-gpu-kernel-modules-525.147.05/kernel-open/nvidia-uvm/uvm_gpu.c 2023-10-25 20:33:33.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/kernel-open/nvidia-uvm/uvm_gpu.c 2024-03-05 22:25:49.000000000 +0000 @@ -1,5 +1,5 @@ /******************************************************************************* - Copyright (c) 2015-2022 NVIDIA Corporation + Copyright (c) 2015-2023 NVIDIA Corporation Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation files (the "Software"), to @@ -41,6 +41,7 @@ #include "uvm_gpu_access_counters.h" #include "uvm_ats.h" #include "uvm_test.h" +#include "uvm_conf_computing.h" #include "uvm_linux.h" @@ -66,21 +67,6 @@ return container_of(node, uvm_user_channel_t, instance_ptr.node); } -static void fill_gpu_info(uvm_parent_gpu_t *parent_gpu, const UvmGpuInfo *gpu_info) -{ - char uuid_buffer[UVM_GPU_UUID_TEXT_BUFFER_LENGTH]; - - parent_gpu->rm_info = *gpu_info; - - format_uuid_to_buffer(uuid_buffer, sizeof(uuid_buffer), &parent_gpu->uuid); - snprintf(parent_gpu->name, - sizeof(parent_gpu->name), - "ID %u: %s: %s", - uvm_id_value(parent_gpu->id), - parent_gpu->rm_info.name, - uuid_buffer); -} - static uvm_gpu_link_type_t get_gpu_link_type(UVM_LINK_TYPE link_type) { switch (link_type) { @@ -101,39 +87,61 @@ } } -static NV_STATUS get_gpu_caps(uvm_parent_gpu_t *parent_gpu) +static void fill_gpu_info(uvm_parent_gpu_t *parent_gpu, const UvmGpuInfo *gpu_info) { - NV_STATUS status; - UvmGpuCaps gpu_caps; + char uuid_buffer[UVM_GPU_UUID_TEXT_BUFFER_LENGTH]; - memset(&gpu_caps, 0, sizeof(gpu_caps)); + parent_gpu->rm_info = *gpu_info; - status = uvm_rm_locked_call(nvUvmInterfaceQueryCaps(parent_gpu->rm_device, &gpu_caps)); - if (status != NV_OK) - return status; + parent_gpu->system_bus.link = get_gpu_link_type(gpu_info->sysmemLink); + UVM_ASSERT(parent_gpu->system_bus.link != UVM_GPU_LINK_INVALID); + + parent_gpu->system_bus.link_rate_mbyte_per_s = gpu_info->sysmemLinkRateMBps; - parent_gpu->sysmem_link = get_gpu_link_type(gpu_caps.sysmemLink); - UVM_ASSERT(parent_gpu->sysmem_link != UVM_GPU_LINK_INVALID); + if (gpu_info->systemMemoryWindowSize > 0) { + // memory_window_end is inclusive but uvm_gpu_is_coherent() checks + // memory_window_end > memory_window_start as its condition. + UVM_ASSERT(gpu_info->systemMemoryWindowSize > 1); + parent_gpu->system_bus.memory_window_start = gpu_info->systemMemoryWindowStart; + parent_gpu->system_bus.memory_window_end = gpu_info->systemMemoryWindowStart + + gpu_info->systemMemoryWindowSize - 1; + } - parent_gpu->sysmem_link_rate_mbyte_per_s = gpu_caps.sysmemLinkRateMBps; - parent_gpu->nvswitch_info.is_nvswitch_connected = gpu_caps.connectedToSwitch; + parent_gpu->nvswitch_info.is_nvswitch_connected = gpu_info->connectedToSwitch; // nvswitch is routed via physical pages, where the upper 13-bits of the // 47-bit address space holds the routing information for each peer. // Currently, this is limited to a 16GB framebuffer window size. if (parent_gpu->nvswitch_info.is_nvswitch_connected) - parent_gpu->nvswitch_info.fabric_memory_window_start = gpu_caps.nvswitchMemoryWindowStart; + parent_gpu->nvswitch_info.fabric_memory_window_start = gpu_info->nvswitchMemoryWindowStart; + + format_uuid_to_buffer(uuid_buffer, sizeof(uuid_buffer), &parent_gpu->uuid); + snprintf(parent_gpu->name, + sizeof(parent_gpu->name), + "ID %u: %s: %s", + uvm_id_value(parent_gpu->id), + parent_gpu->rm_info.name, + uuid_buffer); +} + +static NV_STATUS get_gpu_caps(uvm_gpu_t *gpu) +{ + NV_STATUS status; + UvmGpuCaps gpu_caps; + + memset(&gpu_caps, 0, sizeof(gpu_caps)); + + status = uvm_rm_locked_call(nvUvmInterfaceQueryCaps(uvm_gpu_device_handle(gpu), &gpu_caps)); + if (status != NV_OK) + return status; if (gpu_caps.numaEnabled) { - parent_gpu->numa_info.enabled = true; - parent_gpu->numa_info.node_id = gpu_caps.numaNodeId; - parent_gpu->numa_info.system_memory_window_start = gpu_caps.systemMemoryWindowStart; - parent_gpu->numa_info.system_memory_window_end = gpu_caps.systemMemoryWindowStart + - gpu_caps.systemMemoryWindowSize - - 1; + UVM_ASSERT(uvm_gpu_is_coherent(gpu->parent)); + gpu->mem_info.numa.enabled = true; + gpu->mem_info.numa.node_id = gpu_caps.numaNodeId; } else { - UVM_ASSERT(!g_uvm_global.ats.enabled); + UVM_ASSERT(!uvm_gpu_is_coherent(gpu->parent)); } return NV_OK; @@ -210,35 +218,16 @@ return parent_gpu->rm_info.subdeviceCount == 1; } -static bool parent_gpu_uses_canonical_form_address(uvm_parent_gpu_t *parent_gpu) -{ - NvU64 gpu_addr_shift; - NvU64 cpu_addr_shift; - - // PPC64LE doesn't use canonical form addresses. - if (NVCPU_IS_PPC64LE) - return false; - - // We use big_page_size as UVM_PAGE_SIZE_64K because num_va_bits() is - // big_page_size invariant in the MMU HAL. - UVM_ASSERT(!parent_gpu->arch_hal->mmu_mode_hal(UVM_PAGE_SIZE_128K) || - (parent_gpu->arch_hal->mmu_mode_hal(UVM_PAGE_SIZE_64K)->num_va_bits() == - parent_gpu->arch_hal->mmu_mode_hal(UVM_PAGE_SIZE_128K)->num_va_bits())); - - gpu_addr_shift = parent_gpu->arch_hal->mmu_mode_hal(UVM_PAGE_SIZE_64K)->num_va_bits(); - cpu_addr_shift = fls64(TASK_SIZE - 1) + 1; - - // Refer to the comments and diagram in uvm_gpu.c:uvm_gpu_can_address(). - return gpu_addr_shift >= cpu_addr_shift; - -} - bool uvm_gpu_can_address(uvm_gpu_t *gpu, NvU64 addr, NvU64 size) { // Lower and upper address spaces are typically found in platforms that use // the canonical address form. NvU64 max_va_lower; + NvU64 min_va_upper; NvU64 addr_end = addr + size - 1; + NvU8 gpu_addr_shift; + NvU8 cpu_addr_shift; + NvU8 addr_shift; // Watch out for calling this too early in init UVM_ASSERT(gpu->address_space_tree.hal); @@ -246,6 +235,10 @@ UVM_ASSERT(addr <= addr_end); UVM_ASSERT(size > 0); + gpu_addr_shift = gpu->address_space_tree.hal->num_va_bits(); + cpu_addr_shift = uvm_cpu_num_va_bits(); + addr_shift = gpu_addr_shift; + // Pascal+ GPUs are capable of accessing kernel pointers in various modes // by applying the same upper-bit checks that x86, ARM, and Power // processors do. x86 and ARM use canonical form addresses. For ARM, even @@ -255,13 +248,15 @@ // mapped (or addressed) by the GPU/CPU when the CPU uses canonical form. // (C) regions are only accessible by the CPU. Similarly, (G) regions // are only accessible by the GPU. (X) regions are not addressible. + // Note that we only consider (V) regions, i.e., address ranges that are + // addressable by both, the CPU and GPU. // // GPU MAX VA < CPU MAX VA GPU MAX VA >= CPU MAX VA // 0xF..F +----------------+ 0xF..F +----------------+ - // |CCCCCCCCCCCCCCCC| |VVVVVVVVVVVVVVVV| - // |CCCCCCCCCCCCCCCC| |VVVVVVVVVVVVVVVV| - // |CCCCCCCCCCCCCCCC| |VVVVVVVVVVVVVVVV| - // |CCCCCCCCCCCCCCCC| CPU MIN UPPER VA|----------------| + // |VVVVVVVVVVVVVVVV| |VVVVVVVVVVVVVVVV| + // |VVVVVVVVVVVVVVVV| |VVVVVVVVVVVVVVVV| + // |VVVVVVVVVVVVVVVV| |VVVVVVVVVVVVVVVV| + // GPU MIN UPPER VA|----------------| CPU MIN UPPER VA|----------------| // |CCCCCCCCCCCCCCCC| |GGGGGGGGGGGGGGGG| // |CCCCCCCCCCCCCCCC| |GGGGGGGGGGGGGGGG| // CPU MIN UPPER VA|----------------| GPU MIN UPPER VA|----------------| @@ -270,32 +265,77 @@ // CPU MAX LOWER VA|----------------| GPU MAX LOWER VA|----------------| // |CCCCCCCCCCCCCCCC| |GGGGGGGGGGGGGGGG| // |CCCCCCCCCCCCCCCC| |GGGGGGGGGGGGGGGG| - // GPU MAX VA|----------------| CPU MAX LOWER VA|----------------| + // GPU MAX LOWER VA|----------------| CPU MAX LOWER VA|----------------| // |VVVVVVVVVVVVVVVV| |VVVVVVVVVVVVVVVV| // |VVVVVVVVVVVVVVVV| |VVVVVVVVVVVVVVVV| // |VVVVVVVVVVVVVVVV| |VVVVVVVVVVVVVVVV| // 0 +----------------+ 0 +----------------+ - if (parent_gpu_uses_canonical_form_address(gpu->parent)) { - NvU64 min_va_upper = (NvU64)((NvS64)(1ULL << 63) >> (64 - gpu->address_space_tree.hal->num_va_bits())); - max_va_lower = 1ULL << (gpu->address_space_tree.hal->num_va_bits() - 1); - return (addr_end < max_va_lower) || (addr >= min_va_upper); - } - else { - max_va_lower = 1ULL << gpu->address_space_tree.hal->num_va_bits(); - return addr_end < max_va_lower; + // On canonical form address platforms and Pascal+ GPUs. + if (uvm_platform_uses_canonical_form_address() && gpu_addr_shift > 40) { + // On x86, when cpu_addr_shift > gpu_addr_shift, it means the CPU uses + // 5-level paging and the GPU is pre-Hopper. On Pascal-Ada GPUs (49b + // wide VA) we set addr_shift to match a 4-level paging x86 (48b wide). + // See more details on uvm_parent_gpu_canonical_address(..); + if (cpu_addr_shift > gpu_addr_shift) + addr_shift = NVCPU_IS_X86_64 ? 48 : 49; + else if (gpu_addr_shift == 57) + addr_shift = gpu_addr_shift; + else + addr_shift = cpu_addr_shift; } + + uvm_get_unaddressable_range(addr_shift, &max_va_lower, &min_va_upper); + + return (addr_end < max_va_lower) || (addr >= min_va_upper); } -NvU64 uvm_parent_gpu_canonical_address(uvm_parent_gpu_t *parent_gpu, NvU64 addr) +// The internal UVM VAS does not use canonical form addresses. +bool uvm_gpu_can_address_kernel(uvm_gpu_t *gpu, NvU64 addr, NvU64 size) { - NvU32 gpu_va_bits; - NvU32 shift; + NvU64 addr_end = addr + size - 1; + NvU64 max_gpu_va; - if (parent_gpu_uses_canonical_form_address(parent_gpu)) { - gpu_va_bits = parent_gpu->arch_hal->mmu_mode_hal(UVM_PAGE_SIZE_64K)->num_va_bits(); - shift = 64 - gpu_va_bits; - addr = (NvU64)((NvS64)(addr << shift) >> shift); + // Watch out for calling this too early in init + UVM_ASSERT(gpu->address_space_tree.hal); + UVM_ASSERT(gpu->address_space_tree.hal->num_va_bits() < 64); + UVM_ASSERT(addr <= addr_end); + UVM_ASSERT(size > 0); + + max_gpu_va = 1ULL << gpu->address_space_tree.hal->num_va_bits(); + return addr_end < max_gpu_va; +} + +NvU64 uvm_parent_gpu_canonical_address(uvm_parent_gpu_t *parent_gpu, NvU64 addr) +{ + NvU8 gpu_addr_shift; + NvU8 cpu_addr_shift; + NvU8 addr_shift; + NvU64 input_addr = addr; + + if (uvm_platform_uses_canonical_form_address()) { + // When the CPU VA width is larger than GPU's, it means that: + // On ARM: the CPU is on LVA mode and the GPU is pre-Hopper. + // On x86: the CPU uses 5-level paging and the GPU is pre-Hopper. + // We sign-extend on the 48b on ARM and on the 47b on x86 to mirror the + // behavior of CPUs with smaller (than GPU) VA widths. + gpu_addr_shift = parent_gpu->arch_hal->mmu_mode_hal(UVM_PAGE_SIZE_64K)->num_va_bits(); + cpu_addr_shift = uvm_cpu_num_va_bits(); + + if (cpu_addr_shift > gpu_addr_shift) + addr_shift = NVCPU_IS_X86_64 ? 48 : 49; + else if (gpu_addr_shift == 57) + addr_shift = gpu_addr_shift; + else + addr_shift = cpu_addr_shift; + + addr = (NvU64)((NvS64)(addr << (64 - addr_shift)) >> (64 - addr_shift)); + + // This protection acts on when the address is not covered by the GPU's + // OOR_ADDR_CHECK. This can only happen when OOR_ADDR_CHECK is in + // permissive (NO_CHECK) mode. + if ((addr << (64 - gpu_addr_shift)) != (input_addr << (64 - gpu_addr_shift))) + return input_addr; } return addr; @@ -304,26 +344,30 @@ static void gpu_info_print_ce_caps(uvm_gpu_t *gpu, struct seq_file *s) { NvU32 i; - UvmGpuCopyEnginesCaps ces_caps; + UvmGpuCopyEnginesCaps *ces_caps; NV_STATUS status; - memset(&ces_caps, 0, sizeof(ces_caps)); - status = uvm_rm_locked_call(nvUvmInterfaceQueryCopyEnginesCaps(uvm_gpu_device_handle(gpu), &ces_caps)); + ces_caps = uvm_kvmalloc_zero(sizeof(*ces_caps)); + if (!ces_caps) { + UVM_SEQ_OR_DBG_PRINT(s, "supported_ces: unavailable (no memory)\n"); + return; + } + status = uvm_rm_locked_call(nvUvmInterfaceQueryCopyEnginesCaps(uvm_gpu_device_handle(gpu), ces_caps)); if (status != NV_OK) { UVM_SEQ_OR_DBG_PRINT(s, "supported_ces: unavailable (query failed)\n"); - return; + goto out; } UVM_SEQ_OR_DBG_PRINT(s, "supported_ces:\n"); for (i = 0; i < UVM_COPY_ENGINE_COUNT_MAX; ++i) { - UvmGpuCopyEngineCaps *ce_caps = ces_caps.copyEngineCaps + i; + UvmGpuCopyEngineCaps *ce_caps = ces_caps->copyEngineCaps + i; if (!ce_caps->supported) continue; - UVM_SEQ_OR_DBG_PRINT(s, " ce %u pce mask 0x%08x grce %u shared %u sysmem read %u sysmem write %u sysmem %u nvlink p2p %u " - "p2p %u\n", + UVM_SEQ_OR_DBG_PRINT(s, " ce %u pce mask 0x%08x grce %u shared %u sysmem read %u sysmem write %u sysmem %u " + "nvlink p2p %u p2p %u\n", i, ce_caps->cePceMask, ce_caps->grce, @@ -334,6 +378,9 @@ ce_caps->nvlinkP2p, ce_caps->p2p); } + +out: + uvm_kvfree(ces_caps); } static const char *uvm_gpu_virt_type_string(UVM_VIRT_MODE virtMode) @@ -368,7 +415,6 @@ static void gpu_info_print_common(uvm_gpu_t *gpu, struct seq_file *s) { const UvmGpuInfo *gpu_info = &gpu->parent->rm_info; - uvm_numa_info_t *numa_info = &gpu->parent->numa_info; NvU64 num_pages_in; NvU64 num_pages_out; NvU64 mapped_cpu_pages_size; @@ -387,9 +433,9 @@ return; UVM_SEQ_OR_DBG_PRINT(s, "CPU link type %s\n", - uvm_gpu_link_type_string(gpu->parent->sysmem_link)); + uvm_gpu_link_type_string(gpu->parent->system_bus.link)); UVM_SEQ_OR_DBG_PRINT(s, "CPU link bandwidth %uMBps\n", - gpu->parent->sysmem_link_rate_mbyte_per_s); + gpu->parent->system_bus.link_rate_mbyte_per_s); UVM_SEQ_OR_DBG_PRINT(s, "architecture 0x%X\n", gpu_info->gpuArch); UVM_SEQ_OR_DBG_PRINT(s, "implementation 0x%X\n", gpu_info->gpuImplementation); @@ -411,13 +457,13 @@ gpu->mem_info.max_allocatable_address, gpu->mem_info.max_allocatable_address / (1024 * 1024)); - if (numa_info->enabled) { - NvU64 window_size = numa_info->system_memory_window_end - numa_info->system_memory_window_start + 1; - UVM_SEQ_OR_DBG_PRINT(s, "numa_node_id %u\n", numa_info->node_id); - UVM_SEQ_OR_DBG_PRINT(s, "system_memory_window_start 0x%llx\n", - numa_info->system_memory_window_start); - UVM_SEQ_OR_DBG_PRINT(s, "system_memory_window_end 0x%llx\n", - numa_info->system_memory_window_end); + if (gpu->mem_info.numa.enabled) { + NvU64 window_size = gpu->parent->system_bus.memory_window_end - gpu->parent->system_bus.memory_window_start + 1; + UVM_SEQ_OR_DBG_PRINT(s, "numa_node_id %u\n", uvm_gpu_numa_node(gpu)); + UVM_SEQ_OR_DBG_PRINT(s, "memory_window_start 0x%llx\n", + gpu->parent->system_bus.memory_window_start); + UVM_SEQ_OR_DBG_PRINT(s, "memory_window_end 0x%llx\n", + gpu->parent->system_bus.memory_window_end); UVM_SEQ_OR_DBG_PRINT(s, "system_memory_window_size 0x%llx (%llu MBs)\n", window_size, window_size / (1024 * 1024)); @@ -508,6 +554,10 @@ gpu_info_print_ce_caps(gpu, s); + if (uvm_conf_computing_mode_enabled(gpu)) { + UVM_SEQ_OR_DBG_PRINT(s, "dma_buffer_pool_num_buffers %lu\n", + gpu->conf_computing.dma_buffer_pool.num_dma_buffers); + } } static void @@ -801,7 +851,7 @@ proc_remove(peer_caps->procfs.peer_file[1]); } -static NV_STATUS init_semaphore_pool(uvm_gpu_t *gpu) +static NV_STATUS init_semaphore_pools(uvm_gpu_t *gpu) { NV_STATUS status; uvm_gpu_t *other_gpu; @@ -810,7 +860,17 @@ if (status != NV_OK) return status; + // When the Confidential Computing feature is enabled, a separate secure + // pool is created that holds page allocated in the CPR of vidmem. + if (uvm_conf_computing_mode_enabled(gpu)) { + status = uvm_gpu_semaphore_secure_pool_create(gpu, &gpu->secure_semaphore_pool); + if (status != NV_OK) + return status; + } + for_each_global_gpu(other_gpu) { + if (uvm_conf_computing_mode_enabled(gpu)) + break; if (other_gpu == gpu) continue; status = uvm_gpu_semaphore_pool_map_gpu(other_gpu->semaphore_pool, gpu); @@ -821,7 +881,7 @@ return NV_OK; } -static void deinit_semaphore_pool(uvm_gpu_t *gpu) +static void deinit_semaphore_pools(uvm_gpu_t *gpu) { uvm_gpu_t *other_gpu; @@ -832,6 +892,7 @@ } uvm_gpu_semaphore_pool_destroy(gpu->semaphore_pool); + uvm_gpu_semaphore_pool_destroy(gpu->secure_semaphore_pool); } static NV_STATUS find_unused_global_gpu_id(uvm_parent_gpu_t *parent_gpu, uvm_global_gpu_id_t *out_id) @@ -866,6 +927,7 @@ uvm_parent_gpu_t **parent_gpu_out) { uvm_parent_gpu_t *parent_gpu; + NV_STATUS status; parent_gpu = uvm_kvmalloc_zero(sizeof(*parent_gpu)); if (!parent_gpu) @@ -882,11 +944,14 @@ uvm_rb_tree_init(&parent_gpu->instance_ptr_table); uvm_rb_tree_init(&parent_gpu->tsg_table); + // TODO: Bug 3881835: revisit whether to use nv_kthread_q_t or workqueue. + status = errno_to_nv_status(nv_kthread_q_init(&parent_gpu->lazy_free_q, "vidmem lazy free")); + nv_kref_init(&parent_gpu->gpu_kref); *parent_gpu_out = parent_gpu; - return NV_OK; + return status; } // Allocates a uvm_gpu_t struct and initializes the basic fields and leaves all @@ -1021,6 +1086,8 @@ return status; } + uvm_conf_computing_check_parent_gpu(parent_gpu); + parent_gpu->pci_dev = gpu_platform_info->pci_dev; parent_gpu->closest_cpu_numa_node = dev_to_node(&parent_gpu->pci_dev->dev); parent_gpu->dma_addressable_start = gpu_platform_info->dma_addressable_start; @@ -1056,12 +1123,6 @@ uvm_mmu_init_gpu_chunk_sizes(parent_gpu); - status = get_gpu_caps(parent_gpu); - if (status != NV_OK) { - UVM_ERR_PRINT("Failed to get GPU caps: %s, GPU %s\n", nvstatusToString(status), parent_gpu->name); - return status; - } - status = uvm_ats_add_gpu(parent_gpu); if (status != NV_OK) { UVM_ERR_PRINT("uvm_ats_add_gpu failed: %s, GPU %s\n", nvstatusToString(status), parent_gpu->name); @@ -1120,6 +1181,12 @@ return status; } + status = get_gpu_caps(gpu); + if (status != NV_OK) { + UVM_ERR_PRINT("Failed to get GPU caps: %s, GPU %s\n", nvstatusToString(status), uvm_gpu_name(gpu)); + return status; + } + uvm_mmu_init_gpu_peer_addresses(gpu); status = alloc_and_init_address_space(gpu); @@ -1152,7 +1219,7 @@ return status; } - status = init_semaphore_pool(gpu); + status = init_semaphore_pools(gpu); if (status != NV_OK) { UVM_ERR_PRINT("Failed to initialize the semaphore pool: %s, GPU %s\n", nvstatusToString(status), @@ -1182,6 +1249,14 @@ return status; } + status = uvm_conf_computing_gpu_init(gpu); + if (status != NV_OK) { + UVM_ERR_PRINT("Failed to initialize Confidential Compute: %s for GPU %s\n", + nvstatusToString(status), + uvm_gpu_name(gpu)); + return status; + } + status = init_procfs_files(gpu); if (status != NV_OK) { UVM_ERR_PRINT("Failed to init procfs files: %s, GPU %s\n", nvstatusToString(status), uvm_gpu_name(gpu)); @@ -1357,6 +1432,8 @@ // Sync all trackers in PMM uvm_pmm_gpu_sync(&gpu->pmm); + // Sync all trackers in the GPU's DMA allocation pool + uvm_conf_computing_dma_buffer_pool_sync(&gpu->conf_computing.dma_buffer_pool); } // Remove all references to the given GPU from its parent, since it is being @@ -1439,7 +1516,7 @@ // pain during development. deconfigure_address_space(gpu); - deinit_semaphore_pool(gpu); + deinit_semaphore_pools(gpu); uvm_pmm_sysmem_mappings_deinit(&gpu->pmm_reverse_sysmem_mappings); @@ -1490,6 +1567,13 @@ if (free_parent) destroy_nvlink_peers(gpu); + // uvm_mem_free and other uvm_mem APIs invoked by the Confidential Compute + // deinitialization must be called before the GPU is removed from the global + // table. + // + // TODO: Bug 2008200: Add and remove the GPU in a more reasonable spot. + uvm_conf_computing_gpu_deinit(gpu); + // TODO: Bug 2844714: If the parent is not being freed, the following // gpu_table_lock is only needed to protect concurrent // find_first_valid_gpu() in BH from the __clear_bit here. After @@ -1539,6 +1623,8 @@ UVM_ASSERT(parent_gpu->num_retained_gpus == 0); UVM_ASSERT(bitmap_empty(parent_gpu->valid_gpus, UVM_ID_MAX_SUB_PROCESSORS)); + nv_kthread_q_stop(&parent_gpu->lazy_free_q); + for (sub_processor_index = 0; sub_processor_index < UVM_ID_MAX_SUB_PROCESSORS; sub_processor_index++) UVM_ASSERT(!parent_gpu->gpus[sub_processor_index]); @@ -2180,8 +2266,8 @@ peer_caps->is_indirect_peer = (p2p_caps_params->indirectAccess == NV_TRUE); if (peer_caps->is_indirect_peer) { - UVM_ASSERT(gpu0->parent->numa_info.enabled); - UVM_ASSERT(gpu1->parent->numa_info.enabled); + UVM_ASSERT(gpu0->mem_info.numa.enabled); + UVM_ASSERT(gpu1->mem_info.numa.enabled); status = uvm_pmm_gpu_indirect_peer_init(&gpu0->pmm, gpu1); if (status != NV_OK) @@ -2370,8 +2456,7 @@ // Indirect peers are only supported when onlined as NUMA nodes, because // we want to use vm_insert_page and dma_map_page. - if (p2p_caps_params.indirectAccess && - (!gpu->parent->numa_info.enabled || !other_gpu->parent->numa_info.enabled)) + if (p2p_caps_params.indirectAccess && (!gpu->mem_info.numa.enabled || !other_gpu->mem_info.numa.enabled)) continue; status = enable_nvlink_peer_access(gpu, other_gpu, &p2p_caps_params); @@ -2553,7 +2638,13 @@ uvm_aperture_t uvm_gpu_page_tree_init_location(const uvm_gpu_t *gpu) { // See comment in page_tree_set_location - return uvm_gpu_is_virt_mode_sriov_heavy(gpu)? UVM_APERTURE_VID : UVM_APERTURE_DEFAULT; + if (uvm_gpu_is_virt_mode_sriov_heavy(gpu)) + return UVM_APERTURE_VID; + + if (uvm_conf_computing_mode_enabled(gpu)) + return UVM_APERTURE_VID; + + return UVM_APERTURE_DEFAULT; } uvm_processor_id_t uvm_gpu_get_processor_id_by_address(uvm_gpu_t *gpu, uvm_gpu_phys_address_t addr) @@ -2964,9 +3055,6 @@ exit_unlock: uvm_spin_unlock(&gpu->parent->instance_ptr_table_lock); - if (status == NV_OK) - UVM_ASSERT(uvm_va_space_initialized(*out_va_space) == NV_OK); - return status; } @@ -3005,9 +3093,6 @@ exit_unlock: uvm_spin_unlock(&gpu->parent->instance_ptr_table_lock); - if (status == NV_OK) - UVM_ASSERT(uvm_va_space_initialized(*out_va_space) == NV_OK); - return status; } diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/kernel-open/nvidia-uvm/uvm_gpu.h nvidia-open-gpu-kernel-modules-535.161.08/kernel-open/nvidia-uvm/uvm_gpu.h --- nvidia-open-gpu-kernel-modules-525.147.05/kernel-open/nvidia-uvm/uvm_gpu.h 2023-10-25 20:33:32.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/kernel-open/nvidia-uvm/uvm_gpu.h 2024-03-05 22:25:49.000000000 +0000 @@ -46,6 +46,8 @@ #include "uvm_rb_tree.h" #include "uvm_perf_prefetch.h" #include "nv-kthread-q.h" +#include +#include "uvm_conf_computing.h" // Buffer length to store uvm gpu id, RM device name and gpu uuid. #define UVM_GPU_NICE_NAME_BUFFER_LENGTH (sizeof("ID 999: : ") + \ @@ -55,14 +57,16 @@ typedef struct { - // Number of faults from this uTLB that have been fetched but have not been serviced yet + // Number of faults from this uTLB that have been fetched but have not been + // serviced yet. NvU32 num_pending_faults; // Whether the uTLB contains fatal faults bool has_fatal_faults; - // We have issued a replay of type START_ACK_ALL while containing fatal faults. This puts - // the uTLB in lockdown mode and no new translations are accepted + // We have issued a replay of type START_ACK_ALL while containing fatal + // faults. This puts the uTLB in lockdown mode and no new translations are + // accepted. bool in_lockdown; // We have issued a cancel on this uTLB @@ -124,8 +128,8 @@ struct list_head service_context_list; // A mask of GPUs that need to be checked for ECC errors before the CPU - // fault handler returns, but after the VA space lock has been unlocked to - // avoid the RM/UVM VA space lock deadlocks. + // fault handler returns, but after the VA space lock has been unlocked + // to avoid the RM/UVM VA space lock deadlocks. uvm_processor_mask_t gpus_to_check_for_ecc; // This is set to throttle page fault thrashing. @@ -133,6 +137,12 @@ // This is set if the page migrated to/from the GPU and CPU. bool did_migrate; + + // Sequence number used to start a mmu notifier read side critical + // section. + unsigned long notifier_seq; + + struct vm_fault *vmf; } cpu_fault; // @@ -152,9 +162,9 @@ struct { - // Per-processor mask with the pages that will be resident after servicing. - // We need one mask per processor because we may coalesce faults that - // trigger migrations to different processors. + // Per-processor mask with the pages that will be resident after + // servicing. We need one mask per processor because we may coalesce + // faults that trigger migrations to different processors. uvm_page_mask_t new_residency; } per_processor_masks[UVM_ID_MAX_PROCESSORS]; @@ -168,6 +178,71 @@ uvm_perf_prefetch_bitmap_tree_t prefetch_bitmap_tree; }; +typedef struct +{ + // Mask of read faulted pages in a UVM_VA_BLOCK_SIZE aligned region of a SAM + // VMA. Used for batching ATS faults in a vma. + uvm_page_mask_t read_fault_mask; + + // Mask of write faulted pages in a UVM_VA_BLOCK_SIZE aligned region of a + // SAM VMA. Used for batching ATS faults in a vma. + uvm_page_mask_t write_fault_mask; + + // Mask of successfully serviced pages in a UVM_VA_BLOCK_SIZE aligned region + // of a SAM VMA. Used to return ATS fault status. + uvm_page_mask_t faults_serviced_mask; + + // Mask of successfully serviced read faults on pages in write_fault_mask. + uvm_page_mask_t reads_serviced_mask; + + // Mask of all faulted pages in a UVM_VA_BLOCK_SIZE aligned region of a + // SAM VMA. This is used as input to the prefetcher. + uvm_page_mask_t faulted_mask; + + // Client type of the service requestor. + uvm_fault_client_type_t client_type; + + // New residency ID of the faulting region. + uvm_processor_id_t residency_id; + + // New residency NUMA node ID of the faulting region. + int residency_node; + + struct + { + // True if preferred_location was set on this faulting region. + // UVM_VA_BLOCK_SIZE sized region in the faulting region bound by the + // VMA is is prefetched if preferred_location was set and if first_touch + // is true; + bool has_preferred_location; + + // True if the UVM_VA_BLOCK_SIZE sized region isn't resident on any + // node. False if any page in the region is resident somewhere. + bool first_touch; + + // Mask of prefetched pages in a UVM_VA_BLOCK_SIZE aligned region of a + // SAM VMA. + uvm_page_mask_t prefetch_pages_mask; + + // PFN info of the faulting region + unsigned long pfns[PAGES_PER_UVM_VA_BLOCK]; + + // Faulting/preferred processor residency mask of the faulting region. + uvm_page_mask_t residency_mask; + +#if defined(NV_MMU_INTERVAL_NOTIFIER) + // MMU notifier used to compute residency of this faulting region. + struct mmu_interval_notifier notifier; +#endif + + uvm_va_space_t *va_space; + + // Prefetch temporary state. + uvm_perf_prefetch_bitmap_tree_t bitmap_tree; + } prefetch_state; + +} uvm_ats_fault_context_t; + struct uvm_fault_service_batch_context_struct { // Array of elements fetched from the GPU fault buffer. The number of @@ -190,7 +265,10 @@ NvU32 num_coalesced_faults; - bool has_fatal_faults; + // One of the VA spaces in this batch which had fatal faults. If NULL, no + // faults were fatal. More than one VA space could have fatal faults, but we + // pick one to be the target of the cancel sequence. + uvm_va_space_t *fatal_va_space; bool has_throttled_faults; @@ -200,6 +278,8 @@ NvU32 num_replays; + uvm_ats_fault_context_t ats_context; + // Unique id (per-GPU) generated for tools events recording NvU32 batch_id; @@ -216,11 +296,8 @@ struct uvm_ats_fault_invalidate_struct { - // Whether the TLB batch contains any information - bool write_faults_in_batch; - - // Batch of TLB entries to be invalidated - uvm_tlb_batch_t write_faults_tlb_batch; + bool tlb_batch_pending; + uvm_tlb_batch_t tlb_batch; }; typedef struct @@ -338,6 +415,9 @@ // Unique id (per-GPU) generated for tools events recording NvU32 batch_id; + // Information required to service ATS faults. + uvm_ats_fault_context_t ats_context; + // Information required to invalidate stale ATS PTEs from the GPU TLBs uvm_ats_fault_invalidate_t ats_invalidate; } non_replayable; @@ -349,22 +429,6 @@ NvU64 disable_prefetch_faults_timestamp; } uvm_fault_buffer_info_t; -typedef struct -{ - // True if the platform supports HW coherence (P9) and RM has exposed the - // GPU's memory as a NUMA node to the kernel. - bool enabled; - - // Range in the system physical address space where the memory of this GPU - // is mapped - NvU64 system_memory_window_start; - NvU64 system_memory_window_end; - - NvU64 memblock_size; - - unsigned node_id; -} uvm_numa_info_t; - struct uvm_access_counter_service_batch_context_struct { uvm_access_counter_buffer_entry_t *notification_cache; @@ -378,19 +442,9 @@ NvU32 num_notifications; // Boolean used to avoid sorting the fault batch by instance_ptr if we - // determine at fetch time that all the access counter notifications in the - // batch report the same instance_ptr + // determine at fetch time that all the access counter notifications in + // the batch report the same instance_ptr bool is_single_instance_ptr; - - // Scratch space, used to generate artificial physically addressed notifications. - // Virtual address notifications are always aligned to 64k. This means up to 16 - // different physical locations could have been accessed to trigger one notification. - // The sub-granularity mask can correspond to any of them. - struct { - uvm_processor_id_t resident_processors[16]; - uvm_gpu_phys_address_t phys_addresses[16]; - uvm_access_counter_buffer_entry_t phys_entry; - } scratch; } virt; struct @@ -401,8 +455,8 @@ NvU32 num_notifications; // Boolean used to avoid sorting the fault batch by aperture if we - // determine at fetch time that all the access counter notifications in the - // batch report the same aperture + // determine at fetch time that all the access counter notifications in + // the batch report the same aperture bool is_single_aperture; } phys; @@ -501,6 +555,10 @@ // Page tables with the mapping. uvm_page_table_range_vec_t *range_vec; + + // Used during init to indicate whether the mapping has been fully + // initialized. + bool ready; } uvm_gpu_identity_mapping_t; // Root chunk mapping @@ -581,13 +639,21 @@ // Max (inclusive) physical address of this GPU's memory that the driver // can allocate through PMM (PMA). NvU64 max_allocatable_address; + + struct + { + // True if the platform supports HW coherence and the GPU's memory + // is exposed as a NUMA node to the kernel. + bool enabled; + unsigned int node_id; + } numa; } mem_info; struct { // Big page size used by the internal UVM VA space - // Notably it may be different than the big page size used by a user's VA - // space in general. + // Notably it may be different than the big page size used by a user's + // VA space in general. NvU32 internal_size; } big_page; @@ -613,8 +679,8 @@ // lazily-populated array of peer GPUs, indexed by the peer's GPU index uvm_gpu_t *peer_gpus[UVM_ID_MAX_GPUS]; - // Leaf spinlock used to synchronize access to the peer_gpus table so that - // it can be safely accessed from the access counters bottom half + // Leaf spinlock used to synchronize access to the peer_gpus table so + // that it can be safely accessed from the access counters bottom half uvm_spinlock_t peer_gpus_lock; } peer_info; @@ -637,6 +703,8 @@ uvm_gpu_semaphore_pool_t *semaphore_pool; + uvm_gpu_semaphore_pool_t *secure_semaphore_pool; + uvm_channel_manager_t *channel_manager; uvm_pmm_gpu_t pmm; @@ -696,6 +764,25 @@ // mappings (instead of kernel), and it is used in most configurations. uvm_pmm_sysmem_mappings_t pmm_reverse_sysmem_mappings; + struct + { + uvm_conf_computing_dma_buffer_pool_t dma_buffer_pool; + + // Dummy memory used to store the IV contents during CE encryption. + // This memory location is also only available after CE channels + // because we use them to write PTEs for allocations such as this one. + // This location is used when a physical addressing for the IV buffer + // is required. See uvm_hal_hopper_ce_encrypt(). + uvm_mem_t *iv_mem; + + // Dummy memory used to store the IV contents during CE encryption. + // Because of the limitations of `iv_mem', and the need to have such + // buffer at channel initialization, we use an RM allocation. + // This location is used when a virtual addressing for the IV buffer + // is required. See uvm_hal_hopper_ce_encrypt(). + uvm_rm_mem_t *iv_rm_mem; + } conf_computing; + // ECC handling // In order to trap ECC errors as soon as possible the driver has the hw // interrupt register mapped directly. If an ECC interrupt is ever noticed @@ -833,6 +920,10 @@ uvm_arch_hal_t *arch_hal; uvm_fault_buffer_hal_t *fault_buffer_hal; uvm_access_counter_buffer_hal_t *access_counter_buffer_hal; + uvm_sec2_hal_t *sec2_hal; + + // Whether CE supports physical addressing mode for writes to vidmem + bool ce_phys_vidmem_write_supported; uvm_gpu_peer_copy_mode_t peer_copy_mode; @@ -880,6 +971,10 @@ bool plc_supported; + // If true, page_tree initialization pre-populates no_ats_ranges. It only + // affects ATS systems. + bool no_ats_range_required; + // Parameters used by the TLB batching API struct { @@ -951,13 +1046,16 @@ // Interrupt handling state and locks uvm_isr_info_t isr; - // Fault buffer info. This is only valid if supports_replayable_faults is set to true + // Fault buffer info. This is only valid if supports_replayable_faults is + // set to true. uvm_fault_buffer_info_t fault_buffer_info; - // NUMA info, mainly for ATS - uvm_numa_info_t numa_info; + // PMM lazy free processing queue. + // TODO: Bug 3881835: revisit whether to use nv_kthread_q_t or workqueue. + nv_kthread_q_t lazy_free_q; - // Access counter buffer info. This is only valid if supports_access_counters is set to true + // Access counter buffer info. This is only valid if + // supports_access_counters is set to true. uvm_access_counter_buffer_info_t access_counter_buffer_info; // Number of uTLBs per GPC. This information is only valid on Pascal+ GPUs. @@ -1007,7 +1105,7 @@ uvm_rb_tree_t instance_ptr_table; uvm_spinlock_t instance_ptr_table_lock; - // This is set to true if the GPU belongs to an SLI group. Else, set to false. + // This is set to true if the GPU belongs to an SLI group. bool sli_enabled; struct @@ -1034,8 +1132,8 @@ // environment, rather than using the peer-id field of the PTE (which can // only address 8 gpus), all gpus are assigned a 47-bit physical address // space by the fabric manager. Any physical address access to these - // physical address spaces are routed through the switch to the corresponding - // peer. + // physical address spaces are routed through the switch to the + // corresponding peer. struct { bool is_nvswitch_connected; @@ -1045,8 +1143,32 @@ NvU64 fabric_memory_window_start; } nvswitch_info; - uvm_gpu_link_type_t sysmem_link; - NvU32 sysmem_link_rate_mbyte_per_s; + struct + { + // Note that this represents the link to system memory, not the link the + // system used to discover the GPU. There are some cases such as NVLINK2 + // where the GPU is still on the PCIe bus, but it accesses memory over + // this link rather than PCIe. + uvm_gpu_link_type_t link; + NvU32 link_rate_mbyte_per_s; + + // Range in the system physical address space where the memory of this + // GPU is exposed as coherent. memory_window_end is inclusive. + // memory_window_start == memory_window_end indicates that no window is + // present (coherence is not supported). + NvU64 memory_window_start; + NvU64 memory_window_end; + } system_bus; + + // WAR to issue ATS TLB invalidation commands ourselves. + struct + { + uvm_mutex_t smmu_lock; + struct page *smmu_cmdq; + void __iomem *smmu_cmdqv_base; + unsigned long smmu_prod; + unsigned long smmu_cons; + } smmu_war; }; static const char *uvm_gpu_name(uvm_gpu_t *gpu) @@ -1120,7 +1242,8 @@ // deletion. NvHandle p2p_handle; - struct { + struct + { struct proc_dir_entry *peer_file[2]; struct proc_dir_entry *peer_symlink_file[2]; @@ -1141,23 +1264,20 @@ void uvm_gpu_exit_va_space(uvm_va_space_t *va_space); -static uvm_numa_info_t *uvm_gpu_numa_info(uvm_gpu_t *gpu) +static unsigned int uvm_gpu_numa_node(uvm_gpu_t *gpu) { - UVM_ASSERT(gpu->parent->numa_info.enabled); - - return &gpu->parent->numa_info; + UVM_ASSERT(gpu->mem_info.numa.enabled); + return gpu->mem_info.numa.node_id; } static uvm_gpu_phys_address_t uvm_gpu_page_to_phys_address(uvm_gpu_t *gpu, struct page *page) { - uvm_numa_info_t *numa_info = uvm_gpu_numa_info(gpu); - unsigned long sys_addr = page_to_pfn(page) << PAGE_SHIFT; - unsigned long gpu_offset = sys_addr - numa_info->system_memory_window_start; + unsigned long gpu_offset = sys_addr - gpu->parent->system_bus.memory_window_start; - UVM_ASSERT(page_to_nid(page) == numa_info->node_id); - UVM_ASSERT(sys_addr >= numa_info->system_memory_window_start); - UVM_ASSERT(sys_addr + PAGE_SIZE - 1 <= numa_info->system_memory_window_end); + UVM_ASSERT(page_to_nid(page) == uvm_gpu_numa_node(gpu)); + UVM_ASSERT(sys_addr >= gpu->parent->system_bus.memory_window_start); + UVM_ASSERT(sys_addr + PAGE_SIZE - 1 <= gpu->parent->system_bus.memory_window_end); return uvm_gpu_phys_address(UVM_APERTURE_VID, gpu_offset); } @@ -1238,7 +1358,8 @@ // They must not be the same gpu. uvm_aperture_t uvm_gpu_peer_aperture(uvm_gpu_t *local_gpu, uvm_gpu_t *remote_gpu); -// Get the processor id accessible by the given GPU for the given physical address +// Get the processor id accessible by the given GPU for the given physical +// address. uvm_processor_id_t uvm_gpu_get_processor_id_by_address(uvm_gpu_t *gpu, uvm_gpu_phys_address_t addr); // Get the P2P capabilities between the gpus with the given indexes @@ -1265,8 +1386,8 @@ uvm_gpu_peer_t *peer_caps = uvm_gpu_peer_caps(gpu0, gpu1); if (peer_caps->link_type != UVM_GPU_LINK_INVALID && peer_caps->is_indirect_peer) { - UVM_ASSERT(gpu0->parent->numa_info.enabled); - UVM_ASSERT(gpu1->parent->numa_info.enabled); + UVM_ASSERT(gpu0->mem_info.numa.enabled); + UVM_ASSERT(gpu1->mem_info.numa.enabled); UVM_ASSERT(peer_caps->link_type != UVM_GPU_LINK_PCIE); UVM_ASSERT(!uvm_gpus_are_nvswitch_connected(gpu0, gpu1)); return true; @@ -1286,6 +1407,9 @@ UVM_ASSERT(uvm_mmu_gpu_needs_static_vidmem_mapping(gpu) || uvm_mmu_gpu_needs_dynamic_vidmem_mapping(gpu)); UVM_ASSERT(pa <= gpu->mem_info.max_allocatable_address); + if (uvm_mmu_gpu_needs_static_vidmem_mapping(gpu)) + UVM_ASSERT(gpu->static_flat_mapping.ready); + return uvm_gpu_address_virtual(gpu->parent->flat_vidmem_va_base + pa); } @@ -1303,6 +1427,23 @@ return uvm_gpu_address_virtual(gpu->parent->flat_sysmem_va_base + pa); } +// Given a GPU or CPU physical address (not peer), retrieve an address suitable +// for CE access. +static uvm_gpu_address_t uvm_gpu_address_copy(uvm_gpu_t *gpu, uvm_gpu_phys_address_t phys_addr) +{ + UVM_ASSERT(phys_addr.aperture == UVM_APERTURE_VID || phys_addr.aperture == UVM_APERTURE_SYS); + + if (phys_addr.aperture == UVM_APERTURE_VID) { + if (uvm_mmu_gpu_needs_static_vidmem_mapping(gpu) || uvm_mmu_gpu_needs_dynamic_vidmem_mapping(gpu)) + return uvm_gpu_address_virtual_from_vidmem_phys(gpu, phys_addr.address); + } + else if (uvm_mmu_gpu_needs_dynamic_sysmem_mapping(gpu)) { + return uvm_gpu_address_virtual_from_sysmem_phys(gpu, phys_addr.address); + } + + return uvm_gpu_address_from_phys(phys_addr); +} + static uvm_gpu_identity_mapping_t *uvm_gpu_get_peer_mapping(uvm_gpu_t *gpu, uvm_gpu_id_t peer_id) { return &gpu->peer_mappings[uvm_id_gpu_index(peer_id)]; @@ -1315,9 +1456,9 @@ // Check for ECC errors without calling into RM // -// Calling into RM is problematic in many places, this check is always safe to do. -// Returns NV_WARN_MORE_PROCESSING_REQUIRED if there might be an ECC error and -// it's required to call uvm_gpu_check_ecc_error() to be sure. +// Calling into RM is problematic in many places, this check is always safe to +// do. Returns NV_WARN_MORE_PROCESSING_REQUIRED if there might be an ECC error +// and it's required to call uvm_gpu_check_ecc_error() to be sure. NV_STATUS uvm_gpu_check_ecc_error_no_rm(uvm_gpu_t *gpu); // Map size bytes of contiguous sysmem on the GPU for physical access @@ -1364,10 +1505,27 @@ // The GPU must be initialized before calling this function. bool uvm_gpu_can_address(uvm_gpu_t *gpu, NvU64 addr, NvU64 size); +// Returns whether the given range is within the GPU's addressable VA ranges in +// the internal GPU VA "kernel" address space, which is a linear address space. +// Therefore, the input 'addr' must not be in canonical form, even platforms +// that use to the canonical form addresses, i.e., ARM64, and x86. +// Warning: This only checks whether the GPU's MMU can support the given +// address. Some HW units on that GPU might only support a smaller range. +// +// The GPU must be initialized before calling this function. +bool uvm_gpu_can_address_kernel(uvm_gpu_t *gpu, NvU64 addr, NvU64 size); + +bool uvm_platform_uses_canonical_form_address(void); + // Returns addr's canonical form for host systems that use canonical form // addresses. NvU64 uvm_parent_gpu_canonical_address(uvm_parent_gpu_t *parent_gpu, NvU64 addr); +static bool uvm_gpu_is_coherent(const uvm_parent_gpu_t *parent_gpu) +{ + return parent_gpu->system_bus.memory_window_end > parent_gpu->system_bus.memory_window_start; +} + static bool uvm_gpu_has_pushbuffer_segments(uvm_gpu_t *gpu) { return gpu->parent->max_host_va > (1ull << 40); @@ -1405,8 +1563,9 @@ // Debug print of GPU properties void uvm_gpu_print(uvm_gpu_t *gpu); -// Add the given instance pointer -> user_channel mapping to this GPU. The bottom -// half GPU page fault handler uses this to look up the VA space for GPU faults. +// Add the given instance pointer -> user_channel mapping to this GPU. The +// bottom half GPU page fault handler uses this to look up the VA space for GPU +// faults. NV_STATUS uvm_gpu_add_user_channel(uvm_gpu_t *gpu, uvm_user_channel_t *user_channel); void uvm_gpu_remove_user_channel(uvm_gpu_t *gpu, uvm_user_channel_t *user_channel); @@ -1431,6 +1590,7 @@ { UVM_GPU_BUFFER_FLUSH_MODE_CACHED_PUT, UVM_GPU_BUFFER_FLUSH_MODE_UPDATE_PUT, + UVM_GPU_BUFFER_FLUSH_MODE_WAIT_UPDATE_PUT, } uvm_gpu_buffer_flush_mode_t; #endif // __UVM_GPU_H__ diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/kernel-open/nvidia-uvm/uvm_gpu_access_counters.c nvidia-open-gpu-kernel-modules-535.161.08/kernel-open/nvidia-uvm/uvm_gpu_access_counters.c --- nvidia-open-gpu-kernel-modules-525.147.05/kernel-open/nvidia-uvm/uvm_gpu_access_counters.c 2023-10-25 20:33:36.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/kernel-open/nvidia-uvm/uvm_gpu_access_counters.c 2024-03-05 22:25:54.000000000 +0000 @@ -33,17 +33,17 @@ #include "uvm_va_space_mm.h" #include "uvm_pmm_sysmem.h" #include "uvm_perf_module.h" +#include "uvm_ats_ibm.h" #define UVM_PERF_ACCESS_COUNTER_BATCH_COUNT_MIN 1 #define UVM_PERF_ACCESS_COUNTER_BATCH_COUNT_DEFAULT 256 -#define UVM_PERF_ACCESS_COUNTER_GRANULARITY_DEFAULT "2m" +#define UVM_PERF_ACCESS_COUNTER_GRANULARITY UVM_ACCESS_COUNTER_GRANULARITY_2M #define UVM_PERF_ACCESS_COUNTER_THRESHOLD_MIN 1 #define UVM_PERF_ACCESS_COUNTER_THRESHOLD_MAX ((1 << 16) - 1) #define UVM_PERF_ACCESS_COUNTER_THRESHOLD_DEFAULT 256 -#define UVM_ACCESS_COUNTER_ACTION_NOTIFY 0x1 -#define UVM_ACCESS_COUNTER_ACTION_CLEAR 0x2 -#define UVM_ACCESS_COUNTER_ON_MANAGED 0x4 +#define UVM_ACCESS_COUNTER_ACTION_CLEAR 0x1 +#define UVM_ACCESS_COUNTER_PHYS_ON_MANAGED 0x2 // Each page in a tracked physical range may belong to a different VA Block. We // preallocate an array of reverse map translations. However, access counter @@ -54,12 +54,6 @@ #define UVM_MAX_TRANSLATION_SIZE (2 * 1024 * 1024ULL) #define UVM_SUB_GRANULARITY_REGIONS 32 -// The GPU offers the following tracking granularities: 64K, 2M, 16M, 16G -// -// Use the largest granularity to minimize the number of access counter -// notifications. This is fine because we simply drop the notifications during -// normal operation, and tests override these values. -static UVM_ACCESS_COUNTER_GRANULARITY g_uvm_access_counter_granularity; static unsigned g_uvm_access_counter_threshold; // Per-VA space access counters information @@ -87,7 +81,6 @@ static unsigned uvm_perf_access_counter_batch_count = UVM_PERF_ACCESS_COUNTER_BATCH_COUNT_DEFAULT; // See module param documentation below -static char *uvm_perf_access_counter_granularity = UVM_PERF_ACCESS_COUNTER_GRANULARITY_DEFAULT; static unsigned uvm_perf_access_counter_threshold = UVM_PERF_ACCESS_COUNTER_THRESHOLD_DEFAULT; // Module parameters for the tunables @@ -100,10 +93,6 @@ "Whether MOMC access counters will trigger migrations." "Valid values: <= -1 (default policy), 0 (off), >= 1 (on)"); module_param(uvm_perf_access_counter_batch_count, uint, S_IRUGO); -module_param(uvm_perf_access_counter_granularity, charp, S_IRUGO); -MODULE_PARM_DESC(uvm_perf_access_counter_granularity, - "Size of the physical memory region tracked by each counter. Valid values as" - "of Volta: 64k, 2m, 16m, 16g"); module_param(uvm_perf_access_counter_threshold, uint, S_IRUGO); MODULE_PARM_DESC(uvm_perf_access_counter_threshold, "Number of remote accesses on a region required to trigger a notification." @@ -136,7 +125,7 @@ // Whether access counter migrations are enabled or not. The policy is as // follows: -// - MIMC migrations are enabled by default on P9 systems with ATS support +// - MIMC migrations are disabled by default on all systems except P9. // - MOMC migrations are disabled by default on all systems // - Users can override this policy by specifying on/off static bool is_migration_enabled(uvm_access_counter_type_t type) @@ -159,7 +148,10 @@ if (type == UVM_ACCESS_COUNTER_TYPE_MOMC) return false; - return g_uvm_global.ats.supported; + if (UVM_ATS_IBM_SUPPORTED()) + return g_uvm_global.ats.supported; + + return false; } // Create the access counters tracking struct for the given VA space @@ -210,13 +202,13 @@ *bytes = 64 * 1024ULL; break; case UVM_ACCESS_COUNTER_GRANULARITY_2M: - *bytes = 2 * 1024 * 1024ULL; + *bytes = 2 * UVM_SIZE_1MB; break; case UVM_ACCESS_COUNTER_GRANULARITY_16M: - *bytes = 16 * 1024 * 1024ULL; + *bytes = 16 * UVM_SIZE_1MB; break; case UVM_ACCESS_COUNTER_GRANULARITY_16G: - *bytes = 16 * 1024 * 1024 * 1024ULL; + *bytes = 16 * UVM_SIZE_1GB; break; default: return NV_ERR_INVALID_ARGUMENT; @@ -225,30 +217,18 @@ return NV_OK; } -// Clear the given access counter and add it to the per-GPU clear tracker -static NV_STATUS access_counter_clear_targeted(uvm_gpu_t *gpu, - const uvm_access_counter_buffer_entry_t *entry) +// Clear the access counter notifications and add it to the per-GPU clear +// tracker. +static NV_STATUS access_counter_clear_notifications(uvm_gpu_t *gpu, + uvm_access_counter_buffer_entry_t **notification_start, + NvU32 num_notifications) { + NvU32 i; NV_STATUS status; uvm_push_t push; uvm_access_counter_buffer_info_t *access_counters = &gpu->parent->access_counter_buffer_info; - if (entry->address.is_virtual) { - status = uvm_push_begin(gpu->channel_manager, - UVM_CHANNEL_TYPE_MEMOPS, - &push, - "Clear access counter with virtual address: 0x%llx", - entry->address.address); - } - else { - status = uvm_push_begin(gpu->channel_manager, - UVM_CHANNEL_TYPE_MEMOPS, - &push, - "Clear access counter with physical address: 0x%llx:%s", - entry->address.address, - uvm_aperture_string(entry->address.aperture)); - } - + status = uvm_push_begin(gpu->channel_manager, UVM_CHANNEL_TYPE_MEMOPS, &push, "Clear access counter batch"); if (status != NV_OK) { UVM_ERR_PRINT("Error creating push to clear access counters: %s, GPU %s\n", nvstatusToString(status), @@ -256,7 +236,8 @@ return status; } - gpu->parent->host_hal->access_counter_clear_targeted(&push, entry); + for (i = 0; i < num_notifications; i++) + gpu->parent->host_hal->access_counter_clear_targeted(&push, notification_start[i]); uvm_push_end(&push); @@ -381,30 +362,12 @@ g_uvm_access_counter_threshold = uvm_perf_access_counter_threshold; } - if (strcmp(uvm_perf_access_counter_granularity, "64k") == 0) { - g_uvm_access_counter_granularity = UVM_ACCESS_COUNTER_GRANULARITY_64K; - } - else if (strcmp(uvm_perf_access_counter_granularity, "2m") == 0) { - g_uvm_access_counter_granularity = UVM_ACCESS_COUNTER_GRANULARITY_2M; - } - else if (strcmp(uvm_perf_access_counter_granularity, "16m") == 0) { - g_uvm_access_counter_granularity = UVM_ACCESS_COUNTER_GRANULARITY_16M; - } - else if (strcmp(uvm_perf_access_counter_granularity, "16g") == 0) { - g_uvm_access_counter_granularity = UVM_ACCESS_COUNTER_GRANULARITY_16G; - } - else { - g_uvm_access_counter_granularity = UVM_ACCESS_COUNTER_GRANULARITY_2M; - pr_info("Invalid value '%s' for uvm_perf_access_counter_granularity, using '%s' instead", - uvm_perf_access_counter_granularity, - UVM_PERF_ACCESS_COUNTER_GRANULARITY_DEFAULT); - } - uvm_assert_mutex_locked(&g_uvm_global.global_lock); UVM_ASSERT(parent_gpu->access_counter_buffer_hal != NULL); status = uvm_rm_locked_call(nvUvmInterfaceInitAccessCntrInfo(parent_gpu->rm_device, - &access_counters->rm_info)); + &access_counters->rm_info, + 0)); if (status != NV_OK) { UVM_ERR_PRINT("Failed to init notify buffer info from RM: %s, GPU %s\n", nvstatusToString(status), @@ -421,7 +384,7 @@ UVM_ASSERT(access_counters->rm_info.bufferSize % parent_gpu->access_counter_buffer_hal->entry_size(parent_gpu) == 0); - status = config_granularity_to_bytes(g_uvm_access_counter_granularity, &granularity_bytes); + status = config_granularity_to_bytes(UVM_PERF_ACCESS_COUNTER_GRANULARITY, &granularity_bytes); UVM_ASSERT(status == NV_OK); if (granularity_bytes > UVM_MAX_TRANSLATION_SIZE) UVM_ASSERT(granularity_bytes % UVM_MAX_TRANSLATION_SIZE == 0); @@ -640,8 +603,8 @@ else { UvmGpuAccessCntrConfig default_config = { - .mimcGranularity = g_uvm_access_counter_granularity, - .momcGranularity = g_uvm_access_counter_granularity, + .mimcGranularity = UVM_PERF_ACCESS_COUNTER_GRANULARITY, + .momcGranularity = UVM_PERF_ACCESS_COUNTER_GRANULARITY, .mimcUseLimit = UVM_ACCESS_COUNTER_USE_LIMIT_FULL, .momcUseLimit = UVM_ACCESS_COUNTER_USE_LIMIT_FULL, .threshold = g_uvm_access_counter_threshold, @@ -707,6 +670,7 @@ UVM_ASSERT(gpu->parent->access_counters_supported); // Read PUT pointer from the GPU if requested + UVM_ASSERT(flush_mode != UVM_GPU_BUFFER_FLUSH_MODE_WAIT_UPDATE_PUT); if (flush_mode == UVM_GPU_BUFFER_FLUSH_MODE_UPDATE_PUT) access_counters->cached_put = UVM_GPU_READ_ONCE(*access_counters->rm_info.pAccessCntrBufferPut); @@ -765,6 +729,22 @@ return cmp_access_counter_instance_ptr(a, b); } +// Sort comparator for pointers to GVA access counter notification buffer +// entries that sorts by va_space, and fault address. +static int cmp_sort_virt_notifications_by_va_space_address(const void *_a, const void *_b) +{ + const uvm_access_counter_buffer_entry_t **a = (const uvm_access_counter_buffer_entry_t **)_a; + const uvm_access_counter_buffer_entry_t **b = (const uvm_access_counter_buffer_entry_t **)_b; + + int result; + + result = UVM_CMP_DEFAULT((*a)->virtual_info.va_space, (*b)->virtual_info.va_space); + if (result != 0) + return result; + + return UVM_CMP_DEFAULT((*a)->address.address, (*b)->address.address); +} + // Sort comparator for pointers to GPA access counter notification buffer // entries that sorts by physical address' aperture static int cmp_sort_phys_notifications_by_processor_id(const void *_a, const void *_b) @@ -922,12 +902,11 @@ // GVA notifications provide an instance_ptr and ve_id that can be directly // translated to a VA space. In order to minimize translations, we sort the -// entries by instance_ptr. +// entries by instance_ptr, va_space and notification address in that order. static void preprocess_virt_notifications(uvm_gpu_t *gpu, uvm_access_counter_service_batch_context_t *batch_context) { if (!batch_context->virt.is_single_instance_ptr) { - // Sort by instance_ptr sort(batch_context->virt.notifications, batch_context->virt.num_notifications, sizeof(*batch_context->virt.notifications), @@ -936,6 +915,12 @@ } translate_virt_notifications_instance_ptrs(gpu, batch_context); + + sort(batch_context->virt.notifications, + batch_context->virt.num_notifications, + sizeof(*batch_context->virt.notifications), + cmp_sort_virt_notifications_by_va_space_address, + NULL); } // GPA notifications provide a physical address and an aperture. Sort @@ -944,7 +929,6 @@ static void preprocess_phys_notifications(uvm_access_counter_service_batch_context_t *batch_context) { if (!batch_context->phys.is_single_aperture) { - // Sort by instance_ptr sort(batch_context->phys.notifications, batch_context->phys.num_notifications, sizeof(*batch_context->phys.notifications), @@ -953,6 +937,28 @@ } } +static NV_STATUS notify_tools_and_process_flags(uvm_gpu_t *gpu, + uvm_access_counter_buffer_entry_t **notification_start, + NvU32 num_entries, + NvU32 flags) +{ + NV_STATUS status = NV_OK; + + if (uvm_enable_builtin_tests) { + // TODO: Bug 4310744: [UVM][TOOLS] Attribute access counter tools events + // to va_space instead of broadcasting. + NvU32 i; + + for (i = 0; i < num_entries; i++) + uvm_tools_broadcast_access_counter(gpu, notification_start[i], flags & UVM_ACCESS_COUNTER_PHYS_ON_MANAGED); + } + + if (flags & UVM_ACCESS_COUNTER_ACTION_CLEAR) + status = access_counter_clear_notifications(gpu, notification_start, num_entries); + + return status; +} + static NV_STATUS service_va_block_locked(uvm_processor_id_t processor, uvm_va_block_t *va_block, uvm_va_block_retry_t *va_block_retry, @@ -1007,6 +1013,7 @@ NvU64 address = uvm_va_block_cpu_page_address(va_block, page_index); bool read_duplicate = false; uvm_processor_id_t new_residency; + const uvm_va_policy_t *policy; // Ensure that the migratability iterator covers the current address while (iter.end < address) @@ -1033,21 +1040,23 @@ // If the underlying VMA is gone, skip HMM migrations. if (uvm_va_block_is_hmm(va_block)) { - status = uvm_hmm_find_vma(&service_context->block_context, address); + status = uvm_hmm_find_vma(service_context->block_context.mm, + &service_context->block_context.hmm.vma, + address); if (status == NV_ERR_INVALID_ADDRESS) continue; UVM_ASSERT(status == NV_OK); } - service_context->block_context.policy = uvm_va_policy_get(va_block, address); + policy = uvm_va_policy_get(va_block, address); new_residency = uvm_va_block_select_residency(va_block, &service_context->block_context, page_index, processor, uvm_fault_access_type_mask_bit(UVM_FAULT_ACCESS_TYPE_PREFETCH), - service_context->block_context.policy, + policy, &thrashing_hint, UVM_SERVICE_OPERATION_ACCESS_COUNTERS, &read_duplicate); @@ -1092,12 +1101,17 @@ if (!uvm_processor_mask_empty(&service_context->resident_processors)) { while (first_page_index <= last_page_index) { uvm_page_index_t outer = last_page_index + 1; + const uvm_va_policy_t *policy; if (uvm_va_block_is_hmm(va_block)) { - status = uvm_hmm_find_policy_vma_and_outer(va_block, - &service_context->block_context, - first_page_index, - &outer); + status = NV_ERR_INVALID_ADDRESS; + if (service_context->block_context.mm) { + status = uvm_hmm_find_policy_vma_and_outer(va_block, + &service_context->block_context.hmm.vma, + first_page_index, + &policy, + &outer); + } if (status != NV_OK) break; } @@ -1153,7 +1167,7 @@ const uvm_access_counter_buffer_entry_t *current_entry, const uvm_reverse_map_t *reverse_mappings, size_t num_reverse_mappings, - unsigned *out_flags) + NvU32 *out_flags) { size_t index; uvm_va_block_t *va_block = reverse_mappings[0].va_block; @@ -1180,7 +1194,6 @@ // If an mm is registered with the VA space, we have to retain it // in order to lock it before locking the VA space. mm = uvm_va_space_mm_retain_lock(va_space); - uvm_va_space_down_read(va_space); // Re-check that the VA block is valid after taking the VA block lock. @@ -1198,6 +1211,11 @@ service_context->num_retries = 0; service_context->block_context.mm = mm; + if (uvm_va_block_is_hmm(va_block)) { + uvm_hmm_service_context_init(service_context); + uvm_hmm_migrate_begin_wait(va_block); + } + uvm_mutex_lock(&va_block->lock); reverse_mappings_to_va_block_page_mask(va_block, reverse_mappings, num_reverse_mappings, accessed_pages); @@ -1211,6 +1229,9 @@ uvm_mutex_unlock(&va_block->lock); + if (uvm_va_block_is_hmm(va_block)) + uvm_hmm_migrate_finish(va_block); + if (status == NV_OK) *out_flags |= UVM_ACCESS_COUNTER_ACTION_CLEAR; } @@ -1233,7 +1254,7 @@ const uvm_access_counter_buffer_entry_t *current_entry, const uvm_reverse_map_t *reverse_mappings, size_t num_reverse_mappings, - unsigned *out_flags) + NvU32 *out_flags) { NV_STATUS status = NV_OK; size_t index; @@ -1241,7 +1262,7 @@ *out_flags &= ~UVM_ACCESS_COUNTER_ACTION_CLEAR; for (index = 0; index < num_reverse_mappings; ++index) { - unsigned out_flags_local = 0; + NvU32 out_flags_local = 0; status = service_phys_single_va_block(gpu, batch_context, current_entry, @@ -1300,7 +1321,7 @@ NvU64 address, unsigned long sub_granularity, size_t *num_reverse_mappings, - unsigned *out_flags) + NvU32 *out_flags) { NV_STATUS status; NvU32 region_start, region_end; @@ -1309,7 +1330,10 @@ // Get the reverse_map translations for all the regions set in the // sub_granularity field of the counter. - for_each_sub_granularity_region(region_start, region_end, sub_granularity, config->sub_granularity_regions_per_translation) { + for_each_sub_granularity_region(region_start, + region_end, + sub_granularity, + config->sub_granularity_regions_per_translation) { NvU64 local_address = address + region_start * config->sub_granularity_region_size; NvU32 local_translation_size = (region_end - region_start) * config->sub_granularity_region_size; uvm_reverse_map_t *local_reverse_mappings = batch_context->phys.translations + *num_reverse_mappings; @@ -1358,7 +1382,7 @@ static NV_STATUS service_phys_notification(uvm_gpu_t *gpu, uvm_access_counter_service_batch_context_t *batch_context, const uvm_access_counter_buffer_entry_t *current_entry, - unsigned *out_flags) + NvU32 *out_flags) { NvU64 address; NvU64 translation_index; @@ -1369,7 +1393,7 @@ size_t total_reverse_mappings = 0; uvm_gpu_t *resident_gpu = NULL; NV_STATUS status = NV_OK; - unsigned flags = 0; + NvU32 flags = 0; address = current_entry->address.address; UVM_ASSERT(address % config->translation_size == 0); @@ -1397,7 +1421,7 @@ for (translation_index = 0; translation_index < config->translations_per_counter; ++translation_index) { size_t num_reverse_mappings; - unsigned out_flags_local = 0; + NvU32 out_flags_local = 0; status = service_phys_notification_translation(gpu, resident_gpu, batch_context, @@ -1419,11 +1443,8 @@ sub_granularity = sub_granularity >> config->sub_granularity_regions_per_translation; } - // Currently we only report events for our tests, not for tools - if (uvm_enable_builtin_tests) { - *out_flags |= UVM_ACCESS_COUNTER_ACTION_NOTIFY; - *out_flags |= ((total_reverse_mappings != 0) ? UVM_ACCESS_COUNTER_ON_MANAGED : 0); - } + if (uvm_enable_builtin_tests) + *out_flags |= ((total_reverse_mappings != 0) ? UVM_ACCESS_COUNTER_PHYS_ON_MANAGED : 0); if (status == NV_OK && (flags & UVM_ACCESS_COUNTER_ACTION_CLEAR)) *out_flags |= UVM_ACCESS_COUNTER_ACTION_CLEAR; @@ -1436,22 +1457,21 @@ uvm_access_counter_service_batch_context_t *batch_context) { NvU32 i; + uvm_access_counter_buffer_entry_t **notifications = batch_context->phys.notifications; + preprocess_phys_notifications(batch_context); for (i = 0; i < batch_context->phys.num_notifications; ++i) { NV_STATUS status; - uvm_access_counter_buffer_entry_t *current_entry = batch_context->phys.notifications[i]; - unsigned flags = 0; + uvm_access_counter_buffer_entry_t *current_entry = notifications[i]; + NvU32 flags = 0; if (!UVM_ID_IS_VALID(current_entry->physical_info.resident_id)) continue; status = service_phys_notification(gpu, batch_context, current_entry, &flags); - if (flags & UVM_ACCESS_COUNTER_ACTION_NOTIFY) - uvm_tools_broadcast_access_counter(gpu, current_entry, flags & UVM_ACCESS_COUNTER_ON_MANAGED); - if (status == NV_OK && (flags & UVM_ACCESS_COUNTER_ACTION_CLEAR)) - status = access_counter_clear_targeted(gpu, current_entry); + notify_tools_and_process_flags(gpu, ¬ifications[i], 1, flags); if (status != NV_OK) return status; @@ -1460,152 +1480,218 @@ return NV_OK; } -static int cmp_sort_gpu_phys_addr(const void *_a, const void *_b) -{ - return uvm_gpu_phys_addr_cmp(*(uvm_gpu_phys_address_t*)_a, - *(uvm_gpu_phys_address_t*)_b); -} +static NV_STATUS service_notification_va_block_helper(struct mm_struct *mm, + uvm_va_block_t *va_block, + uvm_processor_id_t processor, + uvm_access_counter_service_batch_context_t *batch_context) +{ + uvm_va_block_retry_t va_block_retry; + uvm_page_mask_t *accessed_pages = &batch_context->accessed_pages; + uvm_service_block_context_t *service_context = &batch_context->block_service_context; + + if (uvm_page_mask_empty(accessed_pages)) + return NV_OK; + + uvm_assert_mutex_locked(&va_block->lock); -static bool gpu_phys_same_region(uvm_gpu_phys_address_t a, uvm_gpu_phys_address_t b, NvU64 granularity) + service_context->operation = UVM_SERVICE_OPERATION_ACCESS_COUNTERS; + service_context->num_retries = 0; + service_context->block_context.mm = mm; + + return UVM_VA_BLOCK_RETRY_LOCKED(va_block, + &va_block_retry, + service_va_block_locked(processor, + va_block, + &va_block_retry, + service_context, + accessed_pages)); +} + +static void expand_notification_block(struct mm_struct *mm, + uvm_gpu_va_space_t *gpu_va_space, + uvm_va_block_t *va_block, + uvm_page_mask_t *accessed_pages, + const uvm_access_counter_buffer_entry_t *current_entry) { - if (a.aperture != b.aperture) - return false; + NvU64 addr; + NvU64 granularity = 0; + uvm_gpu_t *resident_gpu = NULL; + uvm_processor_id_t resident_id; + uvm_page_index_t page_index; + uvm_gpu_t *gpu = gpu_va_space->gpu; + const uvm_access_counter_buffer_info_t *access_counters = &gpu->parent->access_counter_buffer_info; + const uvm_gpu_access_counter_type_config_t *config = get_config_for_type(access_counters, + UVM_ACCESS_COUNTER_TYPE_MIMC); + + config_granularity_to_bytes(config->rm.granularity, &granularity); + + // Granularities other than 2MB can only be enabled by UVM tests. Do nothing + // in that case. + if (granularity != UVM_PAGE_SIZE_2M) + return; - UVM_ASSERT(is_power_of_2(granularity)); + addr = current_entry->address.address; - return UVM_ALIGN_DOWN(a.address, granularity) == UVM_ALIGN_DOWN(b.address, granularity); -} + uvm_assert_rwsem_locked(&gpu_va_space->va_space->lock); + uvm_assert_mutex_locked(&va_block->lock); -static bool phys_address_in_accessed_sub_region(uvm_gpu_phys_address_t address, - NvU64 region_size, - NvU64 sub_region_size, - NvU32 accessed_mask) -{ - const unsigned accessed_index = (address.address % region_size) / sub_region_size; + page_index = uvm_va_block_cpu_page_index(va_block, addr); - // accessed_mask is only filled for tracking granularities larger than 64K - if (region_size == UVM_PAGE_SIZE_64K) - return true; + resident_id = uvm_va_block_page_get_closest_resident(va_block, page_index, gpu->id); - UVM_ASSERT(accessed_index < 32); - return ((1 << accessed_index) & accessed_mask) != 0; + // resident_id might be invalid or might already be the same as the GPU + // which received the notification if the memory was already migrated before + // acquiring the locks either during the servicing of previous notifications + // or during faults or because of explicit migrations or if the VA range was + // freed after receving the notification. Return NV_OK in such cases. + if (!UVM_ID_IS_VALID(resident_id) || uvm_id_equal(resident_id, gpu->id)) + return; + + if (UVM_ID_IS_GPU(resident_id)) + resident_gpu = uvm_va_space_get_gpu(gpu_va_space->va_space, resident_id); + + if (uvm_va_block_get_physical_size(va_block, resident_id, page_index) != granularity) { + uvm_page_mask_set(accessed_pages, page_index); + } + else { + NvU32 region_start; + NvU32 region_end; + unsigned long sub_granularity = current_entry->sub_granularity; + NvU32 num_regions = config->sub_granularity_regions_per_translation; + NvU32 num_sub_pages = config->sub_granularity_region_size / PAGE_SIZE; + uvm_page_mask_t *resident_mask = uvm_va_block_resident_mask_get(va_block, resident_id); + + UVM_ASSERT(num_sub_pages >= 1); + + // region_start and region_end refer to sub_granularity indices, not + // page_indices. + for_each_sub_granularity_region(region_start, region_end, sub_granularity, num_regions) { + uvm_page_mask_region_fill(accessed_pages, + uvm_va_block_region(region_start * num_sub_pages, + region_end * num_sub_pages)); + } + + // Remove pages in the va_block which are not resident on resident_id. + // If the GPU is heavily accessing those pages, future access counter + // migrations will migrate them to the GPU. + uvm_page_mask_and(accessed_pages, accessed_pages, resident_mask); + } } -static NV_STATUS service_virt_notification(uvm_gpu_t *gpu, - uvm_access_counter_service_batch_context_t *batch_context, - const uvm_access_counter_buffer_entry_t *current_entry, - unsigned *out_flags) +static NV_STATUS service_virt_notifications_in_block(struct mm_struct *mm, + uvm_gpu_va_space_t *gpu_va_space, + uvm_va_block_t *va_block, + uvm_access_counter_service_batch_context_t *batch_context, + NvU32 index, + NvU32 *out_index) { + NvU32 i = index; + NvU32 flags = 0; NV_STATUS status = NV_OK; - NvU64 notification_size; - NvU64 address; - uvm_processor_id_t *resident_processors = batch_context->virt.scratch.resident_processors; - uvm_gpu_phys_address_t *phys_addresses = batch_context->virt.scratch.phys_addresses; - int num_addresses = 0; - int i; + NV_STATUS flags_status; + uvm_gpu_t *gpu = gpu_va_space->gpu; + uvm_va_space_t *va_space = gpu_va_space->va_space; + uvm_page_mask_t *accessed_pages = &batch_context->accessed_pages; + uvm_access_counter_buffer_entry_t **notifications = batch_context->virt.notifications; - // Virtual address notifications are always 64K aligned - NvU64 region_start = current_entry->address.address; - NvU64 region_end = current_entry->address.address + UVM_PAGE_SIZE_64K; - + UVM_ASSERT(va_block); + UVM_ASSERT(i < batch_context->virt.num_notifications); - uvm_access_counter_buffer_info_t *access_counters = &gpu->parent->access_counter_buffer_info; - uvm_access_counter_type_t counter_type = current_entry->counter_type; + uvm_assert_rwsem_locked(&va_space->lock); - const uvm_gpu_access_counter_type_config_t *config = get_config_for_type(access_counters, counter_type); + uvm_page_mask_zero(accessed_pages); - uvm_va_space_t *va_space = current_entry->virtual_info.va_space; + uvm_mutex_lock(&va_block->lock); - UVM_ASSERT(counter_type == UVM_ACCESS_COUNTER_TYPE_MIMC); + while (i < batch_context->virt.num_notifications) { + uvm_access_counter_buffer_entry_t *current_entry = notifications[i]; + NvU64 address = current_entry->address.address; - // Entries with NULL va_space are simply dropped. - if (!va_space) - return NV_OK; + if ((current_entry->virtual_info.va_space != va_space) || (address > va_block->end)) { + *out_index = i; + break; + } - status = config_granularity_to_bytes(config->rm.granularity, ¬ification_size); - if (status != NV_OK) - return status; + expand_notification_block(mm, gpu_va_space, va_block, accessed_pages, current_entry); - // Collect physical locations that could have been touched - // in the reported 64K VA region. The notification mask can - // correspond to any of them. - uvm_va_space_down_read(va_space); - for (address = region_start; address < region_end;) { - uvm_va_block_t *va_block; - - NV_STATUS local_status = uvm_va_block_find(va_space, address, &va_block); - if (local_status == NV_ERR_INVALID_ADDRESS || local_status == NV_ERR_OBJECT_NOT_FOUND) { - address += PAGE_SIZE; - continue; - } + i++; + *out_index = i; + } - uvm_mutex_lock(&va_block->lock); - while (address < va_block->end && address < region_end) { - const unsigned page_index = uvm_va_block_cpu_page_index(va_block, address); + status = service_notification_va_block_helper(mm, va_block, gpu->id, batch_context); - // UVM va_block always maps the closest resident location to processor - const uvm_processor_id_t res_id = uvm_va_block_page_get_closest_resident(va_block, page_index, gpu->id); + uvm_mutex_unlock(&va_block->lock); - // Add physical location if it's valid and not local vidmem - if (UVM_ID_IS_VALID(res_id) && !uvm_id_equal(res_id, gpu->id)) { - uvm_gpu_phys_address_t phys_address = uvm_va_block_res_phys_page_address(va_block, page_index, res_id, gpu); - if (phys_address_in_accessed_sub_region(phys_address, - notification_size, - config->sub_granularity_region_size, - current_entry->sub_granularity)) { - resident_processors[num_addresses] = res_id; - phys_addresses[num_addresses] = phys_address; - ++num_addresses; - } - else { - UVM_DBG_PRINT_RL("Skipping phys address %llx:%s, because it couldn't have been accessed in mask %x", - phys_address.address, - uvm_aperture_string(phys_address.aperture), - current_entry->sub_granularity); - } - } + // Atleast one notification should have been processed. + UVM_ASSERT(index < *out_index); - address += PAGE_SIZE; - } - uvm_mutex_unlock(&va_block->lock); - } - uvm_va_space_up_read(va_space); + if (status == NV_OK) + flags |= UVM_ACCESS_COUNTER_ACTION_CLEAR; - // The addresses need to be sorted to aid coalescing. - sort(phys_addresses, - num_addresses, - sizeof(*phys_addresses), - cmp_sort_gpu_phys_addr, - NULL); + flags_status = notify_tools_and_process_flags(gpu, ¬ifications[index], *out_index - index, flags); - for (i = 0; i < num_addresses; ++i) { - uvm_access_counter_buffer_entry_t *fake_entry = &batch_context->virt.scratch.phys_entry; + if ((status == NV_OK) && (flags_status != NV_OK)) + status = flags_status; - // Skip the current pointer if the physical region was already handled - if (i > 0 && gpu_phys_same_region(phys_addresses[i - 1], phys_addresses[i], notification_size)) { - UVM_ASSERT(uvm_id_equal(resident_processors[i - 1], resident_processors[i])); - continue; - } - UVM_DBG_PRINT_RL("Faking MIMC address[%i/%i]: %llx (granularity mask: %llx) in aperture %s on device %s\n", - i, - num_addresses, - phys_addresses[i].address, - notification_size - 1, - uvm_aperture_string(phys_addresses[i].aperture), - uvm_gpu_name(gpu)); - - // Construct a fake phys addr AC entry - fake_entry->counter_type = current_entry->counter_type; - fake_entry->address.address = UVM_ALIGN_DOWN(phys_addresses[i].address, notification_size); - fake_entry->address.aperture = phys_addresses[i].aperture; - fake_entry->address.is_virtual = false; - fake_entry->physical_info.resident_id = resident_processors[i]; - fake_entry->counter_value = current_entry->counter_value; - fake_entry->sub_granularity = current_entry->sub_granularity; + return status; +} - status = service_phys_notification(gpu, batch_context, fake_entry, out_flags); - if (status != NV_OK) - break; +static NV_STATUS service_virt_notifications_batch(struct mm_struct *mm, + uvm_gpu_va_space_t *gpu_va_space, + uvm_access_counter_service_batch_context_t *batch_context, + NvU32 index, + NvU32 *out_index) +{ + NV_STATUS status; + uvm_va_block_t *va_block; + uvm_va_space_t *va_space = gpu_va_space->va_space; + uvm_access_counter_buffer_entry_t *current_entry = batch_context->virt.notifications[index]; + NvU64 address = current_entry->address.address; + + UVM_ASSERT(va_space); + + uvm_assert_rwsem_locked(&va_space->lock); + + // Virtual address notifications are always 64K aligned + UVM_ASSERT(IS_ALIGNED(address, UVM_PAGE_SIZE_64K)); + + // TODO: Bug 4309292: [UVM][HMM] Re-enable access counter HMM block + // migrations for virtual notifications on configs with + // 4KB page size + status = uvm_va_block_find(va_space, address, &va_block); + if ((status == NV_OK) && !uvm_va_block_is_hmm(va_block)) { + + UVM_ASSERT(va_block); + + status = service_virt_notifications_in_block(mm, gpu_va_space, va_block, batch_context, index, out_index); + } + else { + NvU32 flags = 0; + + UVM_ASSERT((status == NV_ERR_OBJECT_NOT_FOUND) || + (status == NV_ERR_INVALID_ADDRESS) || + uvm_va_block_is_hmm(va_block)); + + // NV_ERR_OBJECT_NOT_FOUND is returned if the VA range is valid but no + // VA block has been allocated yet. This can happen if there are stale + // notifications in the batch. A new VA range may have been allocated in + // that range. So, clear the notification entry to continue getting + // notifications for the new VA range. + if (status == NV_ERR_OBJECT_NOT_FOUND) + flags |= UVM_ACCESS_COUNTER_ACTION_CLEAR; + + // NV_ERR_INVALID_ADDRESS is returned if the corresponding VA range + // doesn't exist or it's not a managed range. Access counter migrations + // are not currently supported on such ranges. + // + // TODO: Bug 1990466: [uvm] Use access counters to trigger migrations + // When support for SAM migrations is addded, clear the notification + // entry if the VA range doesn't exist in order to receive notifications + // when a new VA range is allocated in that region. + status = notify_tools_and_process_flags(gpu_va_space->gpu, &batch_context->virt.notifications[index], 1, flags); + *out_index = index + 1; + + status = NV_OK; } return status; @@ -1614,33 +1700,67 @@ static NV_STATUS service_virt_notifications(uvm_gpu_t *gpu, uvm_access_counter_service_batch_context_t *batch_context) { - NvU32 i; + NvU32 i = 0; NV_STATUS status = NV_OK; + struct mm_struct *mm = NULL; + uvm_va_space_t *va_space = NULL; + uvm_va_space_t *prev_va_space = NULL; + uvm_gpu_va_space_t *gpu_va_space = NULL; + + // TODO: Bug 4299018 : Add support for virtual access counter migrations on + // 4K page sizes. + if (PAGE_SIZE == UVM_PAGE_SIZE_4K) { + return notify_tools_and_process_flags(gpu, + batch_context->virt.notifications, + batch_context->virt.num_notifications, + 0); + } + preprocess_virt_notifications(gpu, batch_context); - for (i = 0; i < batch_context->virt.num_notifications; ++i) { - unsigned flags = 0; + while (i < batch_context->virt.num_notifications) { uvm_access_counter_buffer_entry_t *current_entry = batch_context->virt.notifications[i]; + va_space = current_entry->virtual_info.va_space; + + if (va_space != prev_va_space) { + + // New va_space detected, drop locks of the old va_space. + if (prev_va_space) { + uvm_va_space_up_read(prev_va_space); + uvm_va_space_mm_release_unlock(prev_va_space, mm); - status = service_virt_notification(gpu, batch_context, current_entry, &flags); + mm = NULL; + gpu_va_space = NULL; + } + + // Acquire locks for the new va_space. + if (va_space) { + mm = uvm_va_space_mm_retain_lock(va_space); + uvm_va_space_down_read(va_space); - UVM_DBG_PRINT_RL("Processed virt access counter (%d/%d): %sMANAGED (status: %d) clear: %s\n", - i + 1, - batch_context->virt.num_notifications, - (flags & UVM_ACCESS_COUNTER_ON_MANAGED) ? "" : "NOT ", - status, - (flags & UVM_ACCESS_COUNTER_ACTION_CLEAR) ? "YES" : "NO"); + gpu_va_space = uvm_gpu_va_space_get_by_parent_gpu(va_space, gpu->parent); + } - if (uvm_enable_builtin_tests) - uvm_tools_broadcast_access_counter(gpu, current_entry, flags & UVM_ACCESS_COUNTER_ON_MANAGED); + prev_va_space = va_space; + } - if (status == NV_OK && (flags & UVM_ACCESS_COUNTER_ACTION_CLEAR)) - status = access_counter_clear_targeted(gpu, current_entry); + if (va_space && gpu_va_space && uvm_va_space_has_access_counter_migrations(va_space)) { + status = service_virt_notifications_batch(mm, gpu_va_space, batch_context, i, &i); + } + else { + status = notify_tools_and_process_flags(gpu, &batch_context->virt.notifications[i], 1, 0); + i++; + } if (status != NV_OK) break; } + if (va_space) { + uvm_va_space_up_read(va_space); + uvm_va_space_mm_release_unlock(va_space, mm); + } + return status; } @@ -1923,6 +2043,7 @@ } else { uvm_access_counter_buffer_entry_t entry = { 0 }; + uvm_access_counter_buffer_entry_t *notification = &entry; if (params->counter_type == UVM_TEST_ACCESS_COUNTER_TYPE_MIMC) entry.counter_type = UVM_ACCESS_COUNTER_TYPE_MIMC; @@ -1932,7 +2053,7 @@ entry.bank = params->bank; entry.tag = params->tag; - status = access_counter_clear_targeted(gpu, &entry); + status = access_counter_clear_notifications(gpu, ¬ification, 1); } if (status == NV_OK) diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/kernel-open/nvidia-uvm/uvm_gpu_isr.c nvidia-open-gpu-kernel-modules-535.161.08/kernel-open/nvidia-uvm/uvm_gpu_isr.c --- nvidia-open-gpu-kernel-modules-525.147.05/kernel-open/nvidia-uvm/uvm_gpu_isr.c 2023-10-25 20:33:33.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/kernel-open/nvidia-uvm/uvm_gpu_isr.c 2024-03-05 22:25:49.000000000 +0000 @@ -85,76 +85,86 @@ static unsigned schedule_replayable_faults_handler(uvm_parent_gpu_t *parent_gpu) { + uvm_assert_spinlock_locked(&parent_gpu->isr.interrupts_lock); + + if (parent_gpu->isr.is_suspended) + return 0; + // handling gets set to false for all handlers during removal, so quit if // the GPU is in the process of being removed. - if (parent_gpu->isr.replayable_faults.handling) { + if (!parent_gpu->isr.replayable_faults.handling) + return 0; - // Use raw call instead of UVM helper. Ownership will be recorded in the - // bottom half. See comment replayable_faults_isr_bottom_half(). - if (down_trylock(&parent_gpu->isr.replayable_faults.service_lock.sem) == 0) { - if (uvm_gpu_replayable_faults_pending(parent_gpu)) { - nv_kref_get(&parent_gpu->gpu_kref); - - // Interrupts need to be disabled here to avoid an interrupt - // storm - uvm_gpu_replayable_faults_intr_disable(parent_gpu); - - // Schedule a bottom half, but do *not* release the GPU ISR - // lock. The bottom half releases the GPU ISR lock as part of - // its cleanup. - nv_kthread_q_schedule_q_item(&parent_gpu->isr.bottom_half_q, - &parent_gpu->isr.replayable_faults.bottom_half_q_item); - return 1; - } - else { - up(&parent_gpu->isr.replayable_faults.service_lock.sem); - } - } + // Use raw call instead of UVM helper. Ownership will be recorded in the + // bottom half. See comment replayable_faults_isr_bottom_half(). + if (down_trylock(&parent_gpu->isr.replayable_faults.service_lock.sem) != 0) + return 0; + + if (!uvm_gpu_replayable_faults_pending(parent_gpu)) { + up(&parent_gpu->isr.replayable_faults.service_lock.sem); + return 0; } - return 0; + nv_kref_get(&parent_gpu->gpu_kref); + + // Interrupts need to be disabled here to avoid an interrupt storm + uvm_gpu_replayable_faults_intr_disable(parent_gpu); + + // Schedule a bottom half, but do *not* release the GPU ISR lock. The bottom + // half releases the GPU ISR lock as part of its cleanup. + nv_kthread_q_schedule_q_item(&parent_gpu->isr.bottom_half_q, + &parent_gpu->isr.replayable_faults.bottom_half_q_item); + + return 1; } static unsigned schedule_non_replayable_faults_handler(uvm_parent_gpu_t *parent_gpu) { + bool scheduled; + + if (parent_gpu->isr.is_suspended) + return 0; + // handling gets set to false for all handlers during removal, so quit if // the GPU is in the process of being removed. - if (parent_gpu->isr.non_replayable_faults.handling) { - // Non-replayable_faults are stored in a synchronized circular queue - // shared by RM/UVM. Therefore, we can query the number of pending - // faults. This type of faults are not replayed and since RM advances - // GET to PUT when copying the fault packets to the queue, no further - // interrupts will be triggered by the gpu and faults may stay - // unserviced. Therefore, if there is a fault in the queue, we schedule - // a bottom half unconditionally. - if (uvm_gpu_non_replayable_faults_pending(parent_gpu)) { - bool scheduled; - nv_kref_get(&parent_gpu->gpu_kref); - - scheduled = nv_kthread_q_schedule_q_item(&parent_gpu->isr.bottom_half_q, - &parent_gpu->isr.non_replayable_faults.bottom_half_q_item) != 0; - - // If the q_item did not get scheduled because it was already - // queued, that instance will handle the pending faults. Just - // drop the GPU kref. - if (!scheduled) - uvm_parent_gpu_kref_put(parent_gpu); + if (!parent_gpu->isr.non_replayable_faults.handling) + return 0; - return 1; - } - } + // Non-replayable_faults are stored in a synchronized circular queue + // shared by RM/UVM. Therefore, we can query the number of pending + // faults. This type of faults are not replayed and since RM advances + // GET to PUT when copying the fault packets to the queue, no further + // interrupts will be triggered by the gpu and faults may stay + // unserviced. Therefore, if there is a fault in the queue, we schedule + // a bottom half unconditionally. + if (!uvm_gpu_non_replayable_faults_pending(parent_gpu)) + return 0; + + nv_kref_get(&parent_gpu->gpu_kref); - return 0; + scheduled = nv_kthread_q_schedule_q_item(&parent_gpu->isr.bottom_half_q, + &parent_gpu->isr.non_replayable_faults.bottom_half_q_item) != 0; + + // If the q_item did not get scheduled because it was already + // queued, that instance will handle the pending faults. Just + // drop the GPU kref. + if (!scheduled) + uvm_parent_gpu_kref_put(parent_gpu); + + return 1; } static unsigned schedule_access_counters_handler(uvm_parent_gpu_t *parent_gpu) { uvm_assert_spinlock_locked(&parent_gpu->isr.interrupts_lock); + if (parent_gpu->isr.is_suspended) + return 0; + if (!parent_gpu->isr.access_counters.handling_ref_count) return 0; - if (down_trylock(&parent_gpu->isr.access_counters.service_lock.sem)) + if (down_trylock(&parent_gpu->isr.access_counters.service_lock.sem) != 0) return 0; if (!uvm_gpu_access_counters_pending(parent_gpu)) { @@ -199,7 +209,7 @@ { uvm_parent_gpu_t *parent_gpu; unsigned num_handlers_scheduled = 0; - NV_STATUS status; + NV_STATUS status = NV_OK; if (!in_interrupt() && in_atomic()) { // Early-out if we're not in interrupt context, but memory allocations @@ -238,18 +248,15 @@ ++parent_gpu->isr.interrupt_count; - if (parent_gpu->isr.is_suspended) { - status = NV_ERR_NO_INTR_PENDING; - } - else { - num_handlers_scheduled += schedule_replayable_faults_handler(parent_gpu); - num_handlers_scheduled += schedule_non_replayable_faults_handler(parent_gpu); - num_handlers_scheduled += schedule_access_counters_handler(parent_gpu); - - if (num_handlers_scheduled == 0) - status = NV_WARN_MORE_PROCESSING_REQUIRED; + num_handlers_scheduled += schedule_replayable_faults_handler(parent_gpu); + num_handlers_scheduled += schedule_non_replayable_faults_handler(parent_gpu); + num_handlers_scheduled += schedule_access_counters_handler(parent_gpu); + + if (num_handlers_scheduled == 0) { + if (parent_gpu->isr.is_suspended) + status = NV_ERR_NO_INTR_PENDING; else - status = NV_OK; + status = NV_WARN_MORE_PROCESSING_REQUIRED; } uvm_spin_unlock_irqrestore(&parent_gpu->isr.interrupts_lock); @@ -511,6 +518,9 @@ uvm_gpu_replayable_faults_isr_unlock(parent_gpu); put_kref: + // It is OK to drop a reference on the parent GPU if a bottom half has + // been retriggered within uvm_gpu_replayable_faults_isr_unlock, because the + // rescheduling added an additional reference. uvm_parent_gpu_kref_put(parent_gpu); } @@ -591,6 +601,51 @@ UVM_ENTRY_VOID(access_counters_isr_bottom_half(args)); } +static void replayable_faults_retrigger_bottom_half(uvm_parent_gpu_t *parent_gpu) +{ + bool retrigger = false; + + // When Confidential Computing is enabled, UVM does not (indirectly) trigger + // the replayable fault interrupt by updating GET. This is because, in this + // configuration, GET is a dummy register used to inform GSP-RM (the owner + // of the HW replayable fault buffer) of the latest entry consumed by the + // UVM driver. The real GET register is owned by GSP-RM. + // + // The retriggering of a replayable faults bottom half happens then + // manually, by scheduling a bottom half for later if there is any pending + // work in the fault buffer accessible by UVM. The retriggering adddresses + // two problematic scenarios caused by GET updates not setting any + // interrupt: + // + // (1) UVM didn't process all the entries up to cached PUT + // + // (2) UVM did process all the entries up to cached PUT, but GPS-RM + // added new entries such that cached PUT is out-of-date + // + // In both cases, re-enablement of interrupts would have caused the + // replayable fault to be triggered in a non-CC setup, because the updated + // value of GET is different from PUT. But this not the case in Confidential + // Computing, so a bottom half needs to be manually scheduled in order to + // ensure that all faults are serviced. + // + // While in the typical case the retriggering happens within a replayable + // fault bottom half, it can also happen within a non-interrupt path such as + // uvm_gpu_fault_buffer_flush. + if (uvm_conf_computing_mode_enabled_parent(parent_gpu)) + retrigger = true; + + if (!retrigger) + return; + + uvm_spin_lock_irqsave(&parent_gpu->isr.interrupts_lock); + + // If there is pending work, schedule a replayable faults bottom + // half. It is valid for a bottom half (q_item) to reschedule itself. + (void) schedule_replayable_faults_handler(parent_gpu); + + uvm_spin_unlock_irqrestore(&parent_gpu->isr.interrupts_lock); +} + void uvm_gpu_replayable_faults_isr_lock(uvm_parent_gpu_t *parent_gpu) { UVM_ASSERT(nv_kref_read(&parent_gpu->gpu_kref) > 0); @@ -632,9 +687,9 @@ // service_lock mutex is released. if (parent_gpu->isr.replayable_faults.handling) { - // Turn page fault interrupts back on, unless remove_gpu() has already removed this GPU - // from the GPU table. remove_gpu() indicates that situation by setting - // gpu->replayable_faults.handling to false. + // Turn page fault interrupts back on, unless remove_gpu() has already + // removed this GPU from the GPU table. remove_gpu() indicates that + // situation by setting gpu->replayable_faults.handling to false. // // This path can only be taken from the bottom half. User threads // calling this function must have previously retained the GPU, so they @@ -671,6 +726,8 @@ uvm_up_out_of_order(&parent_gpu->isr.replayable_faults.service_lock); uvm_spin_unlock_irqrestore(&parent_gpu->isr.interrupts_lock); + + replayable_faults_retrigger_bottom_half(parent_gpu); } void uvm_gpu_non_replayable_faults_isr_lock(uvm_parent_gpu_t *parent_gpu) diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/kernel-open/nvidia-uvm/uvm_gpu_non_replayable_faults.c nvidia-open-gpu-kernel-modules-535.161.08/kernel-open/nvidia-uvm/uvm_gpu_non_replayable_faults.c --- nvidia-open-gpu-kernel-modules-525.147.05/kernel-open/nvidia-uvm/uvm_gpu_non_replayable_faults.c 2023-10-25 20:33:36.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/kernel-open/nvidia-uvm/uvm_gpu_non_replayable_faults.c 2024-03-05 22:25:53.000000000 +0000 @@ -177,31 +177,34 @@ return has_pending_faults == NV_TRUE; } -static NvU32 fetch_non_replayable_fault_buffer_entries(uvm_gpu_t *gpu) +static NV_STATUS fetch_non_replayable_fault_buffer_entries(uvm_parent_gpu_t *parent_gpu, NvU32 *cached_faults) { NV_STATUS status; - NvU32 i = 0; - NvU32 cached_faults = 0; - uvm_fault_buffer_entry_t *fault_cache; - NvU32 entry_size = gpu->parent->fault_buffer_hal->entry_size(gpu->parent); - uvm_non_replayable_fault_buffer_info_t *non_replayable_faults = &gpu->parent->fault_buffer_info.non_replayable; + NvU32 i; + NvU32 entry_size = parent_gpu->fault_buffer_hal->entry_size(parent_gpu); + uvm_non_replayable_fault_buffer_info_t *non_replayable_faults = &parent_gpu->fault_buffer_info.non_replayable; char *current_hw_entry = (char *)non_replayable_faults->shadow_buffer_copy; + uvm_fault_buffer_entry_t *fault_entry = non_replayable_faults->fault_cache; - fault_cache = non_replayable_faults->fault_cache; + UVM_ASSERT(uvm_sem_is_locked(&parent_gpu->isr.non_replayable_faults.service_lock)); + UVM_ASSERT(parent_gpu->non_replayable_faults_supported); - UVM_ASSERT(uvm_sem_is_locked(&gpu->parent->isr.non_replayable_faults.service_lock)); - UVM_ASSERT(gpu->parent->non_replayable_faults_supported); + status = nvUvmInterfaceGetNonReplayableFaults(&parent_gpu->fault_buffer_info.rm_info, + current_hw_entry, + cached_faults); - status = nvUvmInterfaceGetNonReplayableFaults(&gpu->parent->fault_buffer_info.rm_info, - non_replayable_faults->shadow_buffer_copy, - &cached_faults); - UVM_ASSERT(status == NV_OK); + if (status != NV_OK) { + UVM_ERR_PRINT("nvUvmInterfaceGetNonReplayableFaults() failed: %s, GPU %s\n", + nvstatusToString(status), + parent_gpu->name); - // Parse all faults - for (i = 0; i < cached_faults; ++i) { - uvm_fault_buffer_entry_t *fault_entry = &non_replayable_faults->fault_cache[i]; + uvm_global_set_fatal_error(status); + return status; + } - gpu->parent->fault_buffer_hal->parse_non_replayable_entry(gpu->parent, current_hw_entry, fault_entry); + // Parse all faults + for (i = 0; i < *cached_faults; ++i) { + parent_gpu->fault_buffer_hal->parse_non_replayable_entry(parent_gpu, current_hw_entry, fault_entry); // The GPU aligns the fault addresses to 4k, but all of our tracking is // done in PAGE_SIZE chunks which might be larger. @@ -226,22 +229,33 @@ } current_hw_entry += entry_size; + fault_entry++; } - return cached_faults; + return NV_OK; } -// In SRIOV, the UVM (guest) driver does not have access to the privileged -// registers used to clear the faulted bit. Instead, UVM requests host RM to do -// the clearing on its behalf, using a SW method. static bool use_clear_faulted_channel_sw_method(uvm_gpu_t *gpu) { - if (uvm_gpu_is_virt_mode_sriov(gpu)) { + // If true, UVM uses a SW method to request RM to do the clearing on its + // behalf. + bool use_sw_method = false; + + // In SRIOV, the UVM (guest) driver does not have access to the privileged + // registers used to clear the faulted bit. + if (uvm_gpu_is_virt_mode_sriov(gpu)) + use_sw_method = true; + + // In Confidential Computing access to the privileged registers is blocked, + // in order to prevent interference between guests, or between the + // (untrusted) host and the guests. + if (g_uvm_global.conf_computing_enabled) + use_sw_method = true; + + if (use_sw_method) UVM_ASSERT(gpu->parent->has_clear_faulted_channel_sw_method); - return true; - } - return false; + return use_sw_method; } static NV_STATUS clear_faulted_method_on_gpu(uvm_gpu_t *gpu, @@ -339,6 +353,7 @@ bool read_duplicate; uvm_va_space_t *va_space = uvm_va_block_get_va_space(va_block); uvm_non_replayable_fault_buffer_info_t *non_replayable_faults = &gpu->parent->fault_buffer_info.non_replayable; + const uvm_va_policy_t *policy; UVM_ASSERT(!fault_entry->is_fatal); @@ -348,7 +363,7 @@ UVM_ASSERT(fault_entry->fault_address >= va_block->start); UVM_ASSERT(fault_entry->fault_address <= va_block->end); - service_context->block_context.policy = uvm_va_policy_get(va_block, fault_entry->fault_address); + policy = uvm_va_policy_get(va_block, fault_entry->fault_address); if (service_context->num_retries == 0) { // notify event to tools/performance heuristics. For now we use a @@ -357,7 +372,7 @@ uvm_perf_event_notify_gpu_fault(&va_space->perf_events, va_block, gpu->id, - service_context->block_context.policy->preferred_location, + policy->preferred_location, fault_entry, ++non_replayable_faults->batch_id, false); @@ -392,7 +407,7 @@ page_index, gpu->id, fault_entry->access_type_mask, - service_context->block_context.policy, + policy, &thrashing_hint, UVM_SERVICE_OPERATION_NON_REPLAYABLE_FAULTS, &read_duplicate); @@ -435,6 +450,11 @@ service_context->operation = UVM_SERVICE_OPERATION_NON_REPLAYABLE_FAULTS; service_context->num_retries = 0; + if (uvm_va_block_is_hmm(va_block)) { + uvm_hmm_service_context_init(service_context); + uvm_hmm_migrate_begin_wait(va_block); + } + uvm_mutex_lock(&va_block->lock); status = UVM_VA_BLOCK_RETRY_LOCKED(va_block, &va_block_retry, @@ -449,6 +469,9 @@ uvm_mutex_unlock(&va_block->lock); + if (uvm_va_block_is_hmm(va_block)) + uvm_hmm_migrate_finish(va_block); + return status == NV_OK? tracker_status: status; } @@ -459,8 +482,6 @@ uvm_user_channel_t *user_channel = (uvm_user_channel_t *)_user_channel; uvm_va_space_t *va_space = user_channel->kill_channel.va_space; - UVM_ASSERT(uvm_va_space_initialized(va_space) == NV_OK); - uvm_va_space_down_read_rm(va_space); if (user_channel->gpu_va_space) { // RM handles the fault, which will do the correct fault reporting in the @@ -514,6 +535,14 @@ &user_channel->kill_channel.kill_channel_q_item); } +static void service_fault_fatal(uvm_fault_buffer_entry_t *fault_entry, NV_STATUS status) +{ + UVM_ASSERT(fault_entry->fault_access_type != UVM_FAULT_ACCESS_TYPE_PREFETCH); + + fault_entry->is_fatal = true; + fault_entry->fatal_reason = uvm_tools_status_to_fatal_fault_reason(status); +} + static NV_STATUS service_non_managed_fault(uvm_gpu_va_space_t *gpu_va_space, struct mm_struct *mm, uvm_fault_buffer_entry_t *fault_entry, @@ -523,6 +552,7 @@ uvm_non_replayable_fault_buffer_info_t *non_replayable_faults = &gpu->parent->fault_buffer_info.non_replayable; uvm_ats_fault_invalidate_t *ats_invalidate = &non_replayable_faults->ats_invalidate; NV_STATUS status = lookup_status; + NV_STATUS fatal_fault_status = NV_ERR_INVALID_ADDRESS; UVM_ASSERT(!fault_entry->is_fatal); @@ -539,27 +569,63 @@ return status; if (uvm_ats_can_service_faults(gpu_va_space, mm)) { - ats_invalidate->write_faults_in_batch = false; + struct vm_area_struct *vma; + uvm_va_range_t *va_range_next; + NvU64 fault_address = fault_entry->fault_address; + uvm_fault_access_type_t fault_access_type = fault_entry->fault_access_type; + uvm_ats_fault_context_t *ats_context = &non_replayable_faults->ats_context; + + uvm_page_mask_zero(&ats_context->read_fault_mask); + uvm_page_mask_zero(&ats_context->write_fault_mask); + + ats_context->client_type = UVM_FAULT_CLIENT_TYPE_HUB; + + ats_invalidate->tlb_batch_pending = false; + + va_range_next = uvm_va_space_iter_first(gpu_va_space->va_space, fault_entry->fault_address, ~0ULL); // The VA isn't managed. See if ATS knows about it. - status = uvm_ats_service_fault_entry(gpu_va_space, fault_entry, ats_invalidate); + vma = find_vma_intersection(mm, fault_address, fault_address + 1); + if (!vma || uvm_ats_check_in_gmmu_region(gpu_va_space->va_space, fault_address, va_range_next)) { - // Invalidate ATS TLB entries if needed - if (status == NV_OK) { - status = uvm_ats_invalidate_tlbs(gpu_va_space, - ats_invalidate, - &non_replayable_faults->fault_service_tracker); + // Do not return error due to logical errors in the application + status = NV_OK; + } + else { + NvU64 base = UVM_VA_BLOCK_ALIGN_DOWN(fault_address); + uvm_page_mask_t *faults_serviced_mask = &ats_context->faults_serviced_mask; + uvm_page_index_t page_index = (fault_address - base) / PAGE_SIZE; + uvm_page_mask_t *fault_mask = (fault_access_type >= UVM_FAULT_ACCESS_TYPE_WRITE) ? + &ats_context->write_fault_mask : + &ats_context->read_fault_mask; + + uvm_page_mask_set(fault_mask, page_index); + + status = uvm_ats_service_faults(gpu_va_space, vma, base, ats_context); + if (status == NV_OK) { + // Invalidate ATS TLB entries if needed + if (uvm_page_mask_test(faults_serviced_mask, page_index)) { + status = uvm_ats_invalidate_tlbs(gpu_va_space, + ats_invalidate, + &non_replayable_faults->fault_service_tracker); + fatal_fault_status = NV_OK; + } + } + else { + fatal_fault_status = status; + } } } else { - UVM_ASSERT(fault_entry->fault_access_type != UVM_FAULT_ACCESS_TYPE_PREFETCH); - fault_entry->is_fatal = true; - fault_entry->fatal_reason = uvm_tools_status_to_fatal_fault_reason(status); + fatal_fault_status = status; // Do not return error due to logical errors in the application status = NV_OK; } + if (fatal_fault_status != NV_OK) + service_fault_fatal(fault_entry, fatal_fault_status); + return status; } @@ -623,10 +689,17 @@ fault_entry->fault_source.channel_id = user_channel->hw_channel_id; if (!fault_entry->is_fatal) { - status = uvm_va_block_find_create(fault_entry->va_space, - fault_entry->fault_address, - va_block_context, - &va_block); + if (mm) { + status = uvm_va_block_find_create(fault_entry->va_space, + fault_entry->fault_address, + &va_block_context->hmm.vma, + &va_block); + } + else { + status = uvm_va_block_find_create_managed(fault_entry->va_space, + fault_entry->fault_address, + &va_block); + } if (status == NV_OK) status = service_managed_fault_in_block(gpu_va_space->gpu, va_block, fault_entry); else @@ -654,31 +727,35 @@ uvm_va_space_up_read(va_space); uvm_va_space_mm_release_unlock(va_space, mm); + if (status != NV_OK) + UVM_DBG_PRINT("Error servicing non-replayable faults on GPU: %s\n", uvm_gpu_name(gpu)); + return status; } void uvm_gpu_service_non_replayable_fault_buffer(uvm_gpu_t *gpu) { - NV_STATUS status = NV_OK; NvU32 cached_faults; // If this handler is modified to handle fewer than all of the outstanding // faults, then special handling will need to be added to uvm_suspend() // to guarantee that fault processing has completed before control is // returned to the RM. - while ((cached_faults = fetch_non_replayable_fault_buffer_entries(gpu)) > 0) { + do { + NV_STATUS status; NvU32 i; + status = fetch_non_replayable_fault_buffer_entries(gpu->parent, &cached_faults); + if (status != NV_OK) + return; + // Differently to replayable faults, we do not batch up and preprocess // non-replayable faults since getting multiple faults on the same // memory region is not very likely for (i = 0; i < cached_faults; ++i) { status = service_fault(gpu, &gpu->parent->fault_buffer_info.non_replayable.fault_cache[i]); if (status != NV_OK) - break; + return; } - } - - if (status != NV_OK) - UVM_DBG_PRINT("Error servicing non-replayable faults on GPU: %s\n", uvm_gpu_name(gpu)); + } while (cached_faults > 0); } diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/kernel-open/nvidia-uvm/uvm_gpu_replayable_faults.c nvidia-open-gpu-kernel-modules-535.161.08/kernel-open/nvidia-uvm/uvm_gpu_replayable_faults.c --- nvidia-open-gpu-kernel-modules-525.147.05/kernel-open/nvidia-uvm/uvm_gpu_replayable_faults.c 2023-10-25 20:33:36.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/kernel-open/nvidia-uvm/uvm_gpu_replayable_faults.c 2024-03-05 22:25:53.000000000 +0000 @@ -1,5 +1,5 @@ /******************************************************************************* - Copyright (c) 2015-2022 NVIDIA Corporation + Copyright (c) 2015-2023 NVIDIA Corporation Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation files (the "Software"), to @@ -23,6 +23,7 @@ #include "linux/sort.h" #include "nv_uvm_interface.h" +#include "uvm_common.h" #include "uvm_linux.h" #include "uvm_global.h" #include "uvm_gpu_replayable_faults.h" @@ -296,6 +297,19 @@ } } +// TODO: Bug 4098289: this function can be removed, and the calls to it replaced +// with calls to uvm_conf_computing_mode_enabled_parent, once UVM ownership is +// dictated by Confidential Computing enablement. Currently we support a +// non-production scenario in which Confidential Computing is enabled, but +// UVM still owns the replayable fault buffer. +bool uvm_parent_gpu_replayable_fault_buffer_is_uvm_owned(uvm_parent_gpu_t *parent_gpu) +{ + if (uvm_conf_computing_mode_enabled_parent(parent_gpu)) + return parent_gpu->fault_buffer_info.rm_info.replayable.bUvmOwnsHwFaultBuffer; + + return true; +} + bool uvm_gpu_replayable_faults_pending(uvm_parent_gpu_t *parent_gpu) { uvm_replayable_fault_buffer_info_t *replayable_faults = &parent_gpu->fault_buffer_info.replayable; @@ -348,7 +362,8 @@ "Cancel targeting instance_ptr {0x%llx:%s}\n", instance_ptr.address, uvm_aperture_string(instance_ptr.aperture)); - } else { + } + else { status = uvm_push_begin_acquire(gpu->channel_manager, UVM_CHANNEL_TYPE_MEMOPS, &replayable_faults->replay_tracker, @@ -472,7 +487,9 @@ return status; } -static NV_STATUS push_replay_on_gpu(uvm_gpu_t *gpu, uvm_fault_replay_type_t type, uvm_fault_service_batch_context_t *batch_context) +static NV_STATUS push_replay_on_gpu(uvm_gpu_t *gpu, + uvm_fault_replay_type_t type, + uvm_fault_service_batch_context_t *batch_context) { NV_STATUS status; uvm_push_t push; @@ -529,6 +546,48 @@ parent_gpu->fault_buffer_hal->write_get(parent_gpu, get); } +static NV_STATUS hw_fault_buffer_flush_locked(uvm_parent_gpu_t *parent_gpu) +{ + NV_STATUS status = NV_OK; + + // When Confidential Computing is enabled, GSP-RM owns the HW replayable + // fault buffer. Flushing the fault buffer implies flushing both the HW + // buffer (using a RM API), and the SW buffer accessible by UVM ("shadow" + // buffer). + // + // The HW buffer needs to be flushed first. This is because, once that + // flush completes, any faults that were present in the HW buffer when + // fault_buffer_flush_locked is called, are now either flushed from the HW + // buffer, or are present in the shadow buffer and are about to be discarded + // too. + if (!uvm_conf_computing_mode_enabled_parent(parent_gpu)) + return NV_OK; + + // nvUvmInterfaceFlushReplayableFaultBuffer relies on the caller to ensure + // serialization for a given GPU. + UVM_ASSERT(uvm_sem_is_locked(&parent_gpu->isr.replayable_faults.service_lock)); + + // Flush the HW replayable buffer owned by GSP-RM. + status = nvUvmInterfaceFlushReplayableFaultBuffer(parent_gpu->rm_device); + + UVM_ASSERT(status == NV_OK); + + return status; +} + +static void fault_buffer_skip_replayable_entry(uvm_parent_gpu_t *parent_gpu, NvU32 index) +{ + UVM_ASSERT(parent_gpu->fault_buffer_hal->entry_is_valid(parent_gpu, index)); + + // Flushed faults are never decrypted, but the decryption IV associated with + // replayable faults still requires manual adjustment so it is kept in sync + // with the encryption IV on the GSP-RM's side. + if (!uvm_parent_gpu_replayable_fault_buffer_is_uvm_owned(parent_gpu)) + uvm_conf_computing_fault_increment_decrypt_iv(parent_gpu, 1); + + parent_gpu->fault_buffer_hal->entry_clear_valid(parent_gpu, index); +} + static NV_STATUS fault_buffer_flush_locked(uvm_gpu_t *gpu, uvm_gpu_buffer_flush_mode_t flush_mode, uvm_fault_replay_type_t fault_replay, @@ -537,23 +596,37 @@ NvU32 get; NvU32 put; uvm_spin_loop_t spin; - uvm_replayable_fault_buffer_info_t *replayable_faults = &gpu->parent->fault_buffer_info.replayable; + uvm_parent_gpu_t *parent_gpu = gpu->parent; + uvm_replayable_fault_buffer_info_t *replayable_faults = &parent_gpu->fault_buffer_info.replayable; + NV_STATUS status; - UVM_ASSERT(uvm_sem_is_locked(&gpu->parent->isr.replayable_faults.service_lock)); - UVM_ASSERT(gpu->parent->replayable_faults_supported); + UVM_ASSERT(uvm_sem_is_locked(&parent_gpu->isr.replayable_faults.service_lock)); + UVM_ASSERT(parent_gpu->replayable_faults_supported); + + // Wait for the prior replay to flush out old fault messages + if (flush_mode == UVM_GPU_BUFFER_FLUSH_MODE_WAIT_UPDATE_PUT) { + status = uvm_tracker_wait(&replayable_faults->replay_tracker); + if (status != NV_OK) + return status; + } // Read PUT pointer from the GPU if requested - if (flush_mode == UVM_GPU_BUFFER_FLUSH_MODE_UPDATE_PUT) - replayable_faults->cached_put = gpu->parent->fault_buffer_hal->read_put(gpu->parent); + if (flush_mode == UVM_GPU_BUFFER_FLUSH_MODE_UPDATE_PUT || flush_mode == UVM_GPU_BUFFER_FLUSH_MODE_WAIT_UPDATE_PUT) { + status = hw_fault_buffer_flush_locked(parent_gpu); + if (status != NV_OK) + return status; + + replayable_faults->cached_put = parent_gpu->fault_buffer_hal->read_put(parent_gpu); + } get = replayable_faults->cached_get; put = replayable_faults->cached_put; while (get != put) { // Wait until valid bit is set - UVM_SPIN_WHILE(!gpu->parent->fault_buffer_hal->entry_is_valid(gpu->parent, get), &spin); + UVM_SPIN_WHILE(!parent_gpu->fault_buffer_hal->entry_is_valid(parent_gpu, get), &spin); - gpu->parent->fault_buffer_hal->entry_clear_valid(gpu->parent, get); + fault_buffer_skip_replayable_entry(parent_gpu, get); ++get; if (get == replayable_faults->max_faults) get = 0; @@ -575,7 +648,7 @@ uvm_gpu_replayable_faults_isr_lock(gpu->parent); status = fault_buffer_flush_locked(gpu, - UVM_GPU_BUFFER_FLUSH_MODE_UPDATE_PUT, + UVM_GPU_BUFFER_FLUSH_MODE_WAIT_UPDATE_PUT, UVM_FAULT_REPLAY_TYPE_START, NULL); @@ -625,9 +698,6 @@ typedef enum { - // Fetch a batch of faults from the buffer. - FAULT_FETCH_MODE_BATCH_ALL, - // Fetch a batch of faults from the buffer. Stop at the first entry that is // not ready yet FAULT_FETCH_MODE_BATCH_READY, @@ -728,9 +798,9 @@ // This optimization cannot be performed during fault cancel on Pascal GPUs // (fetch_mode == FAULT_FETCH_MODE_ALL) since we need accurate tracking of all // the faults in each uTLB in order to guarantee precise fault attribution. -static void fetch_fault_buffer_entries(uvm_gpu_t *gpu, - uvm_fault_service_batch_context_t *batch_context, - fault_fetch_mode_t fetch_mode) +static NV_STATUS fetch_fault_buffer_entries(uvm_gpu_t *gpu, + uvm_fault_service_batch_context_t *batch_context, + fault_fetch_mode_t fetch_mode) { NvU32 get; NvU32 put; @@ -739,6 +809,7 @@ NvU32 utlb_id; uvm_fault_buffer_entry_t *fault_cache; uvm_spin_loop_t spin; + NV_STATUS status = NV_OK; uvm_replayable_fault_buffer_info_t *replayable_faults = &gpu->parent->fault_buffer_info.replayable; const bool in_pascal_cancel_path = (!gpu->parent->fault_cancel_va_supported && fetch_mode == FAULT_FETCH_MODE_ALL); const bool may_filter = uvm_perf_fault_coalesce && !in_pascal_cancel_path; @@ -784,9 +855,7 @@ // written out of order UVM_SPIN_WHILE(!gpu->parent->fault_buffer_hal->entry_is_valid(gpu->parent, get), &spin) { // We have some entry to work on. Let's do the rest later. - if (fetch_mode != FAULT_FETCH_MODE_ALL && - fetch_mode != FAULT_FETCH_MODE_BATCH_ALL && - fault_index > 0) + if (fetch_mode == FAULT_FETCH_MODE_BATCH_READY && fault_index > 0) goto done; } @@ -794,7 +863,9 @@ smp_mb__after_atomic(); // Got valid bit set. Let's cache. - gpu->parent->fault_buffer_hal->parse_entry(gpu->parent, get, current_entry); + status = gpu->parent->fault_buffer_hal->parse_replayable_entry(gpu->parent, get, current_entry); + if (status != NV_OK) + goto done; // The GPU aligns the fault addresses to 4k, but all of our tracking is // done in PAGE_SIZE chunks which might be larger. @@ -813,6 +884,7 @@ current_entry->va_space = NULL; current_entry->filtered = false; + current_entry->replayable.cancel_va_mode = UVM_FAULT_CANCEL_VA_MODE_ALL; if (current_entry->fault_source.utlb_id > batch_context->max_utlb_id) { UVM_ASSERT(current_entry->fault_source.utlb_id < replayable_faults->utlb_count); @@ -861,6 +933,8 @@ batch_context->num_cached_faults = fault_index; batch_context->num_coalesced_faults = num_coalesced_faults; + + return status; } // Sort comparator for pointers to fault buffer entries that sorts by @@ -956,6 +1030,10 @@ // If the channel is gone then we're looking at a stale fault entry. // The fault must have been resolved already (serviced or // cancelled), so we can just flush the fault buffer. + // + // No need to use UVM_GPU_BUFFER_FLUSH_MODE_WAIT_UPDATE_PUT since + // there was a context preemption for the entries we want to flush, + // meaning PUT must reflect them. status = fault_buffer_flush_locked(gpu, UVM_GPU_BUFFER_FLUSH_MODE_UPDATE_PUT, UVM_FAULT_REPLAY_TYPE_START, @@ -1034,6 +1112,99 @@ return NV_OK; } +static bool check_fault_entry_duplicate(const uvm_fault_buffer_entry_t *current_entry, + const uvm_fault_buffer_entry_t *previous_entry) +{ + bool is_duplicate = false; + + if (previous_entry) { + is_duplicate = (current_entry->va_space == previous_entry->va_space) && + (current_entry->fault_address == previous_entry->fault_address); + } + + return is_duplicate; +} + +static void update_batch_and_notify_fault(uvm_gpu_t *gpu, + uvm_fault_service_batch_context_t *batch_context, + uvm_va_block_t *va_block, + uvm_processor_id_t preferred_location, + uvm_fault_buffer_entry_t *current_entry, + bool is_duplicate) +{ + if (is_duplicate) + batch_context->num_duplicate_faults += current_entry->num_instances; + else + batch_context->num_duplicate_faults += current_entry->num_instances - 1; + + uvm_perf_event_notify_gpu_fault(¤t_entry->va_space->perf_events, + va_block, + gpu->id, + preferred_location, + current_entry, + batch_context->batch_id, + is_duplicate); +} + +static void mark_fault_invalid_prefetch(uvm_fault_service_batch_context_t *batch_context, + uvm_fault_buffer_entry_t *fault_entry) +{ + fault_entry->is_invalid_prefetch = true; + + // For block faults, the following counter might be updated more than once + // for the same fault if block_context->num_retries > 0. As a result, this + // counter might be higher than the actual count. In order for this counter + // to be always accurate, block_context needs to passed down the stack from + // all callers. But since num_retries > 0 case is uncommon and imprecise + // invalid_prefetch counter doesn't affect functionality (other than + // disabling prefetching if the counter indicates lots of invalid prefetch + // faults), this is ok. + batch_context->num_invalid_prefetch_faults += fault_entry->num_instances; +} + +static void mark_fault_throttled(uvm_fault_service_batch_context_t *batch_context, + uvm_fault_buffer_entry_t *fault_entry) +{ + fault_entry->is_throttled = true; + batch_context->has_throttled_faults = true; +} + +static void mark_fault_fatal(uvm_fault_service_batch_context_t *batch_context, + uvm_fault_buffer_entry_t *fault_entry, + UvmEventFatalReason fatal_reason, + uvm_fault_cancel_va_mode_t cancel_va_mode) +{ + uvm_fault_utlb_info_t *utlb = &batch_context->utlbs[fault_entry->fault_source.utlb_id]; + + fault_entry->is_fatal = true; + fault_entry->fatal_reason = fatal_reason; + fault_entry->replayable.cancel_va_mode = cancel_va_mode; + + utlb->has_fatal_faults = true; + + if (!batch_context->fatal_va_space) { + UVM_ASSERT(fault_entry->va_space); + batch_context->fatal_va_space = fault_entry->va_space; + } +} + +static void fault_entry_duplicate_flags(uvm_fault_service_batch_context_t *batch_context, + uvm_fault_buffer_entry_t *current_entry, + const uvm_fault_buffer_entry_t *previous_entry) +{ + UVM_ASSERT(previous_entry); + UVM_ASSERT(check_fault_entry_duplicate(current_entry, previous_entry)); + + // Propagate the is_invalid_prefetch flag across all prefetch faults + // on the page + if (previous_entry->is_invalid_prefetch) + mark_fault_invalid_prefetch(batch_context, current_entry); + + // If a page is throttled, all faults on the page must be skipped + if (previous_entry->is_throttled) + mark_fault_throttled(batch_context, current_entry); +} + // This function computes the maximum access type that can be serviced for the // reported fault instances given the logical permissions of the VA range. If // none of the fault instances can be serviced UVM_FAULT_ACCESS_TYPE_COUNT is @@ -1054,12 +1225,17 @@ // Return values: // - service_access_type: highest access type that can be serviced. static uvm_fault_access_type_t check_fault_access_permissions(uvm_gpu_t *gpu, + uvm_fault_service_batch_context_t *batch_context, uvm_va_block_t *va_block, - uvm_va_block_context_t *va_block_context, + uvm_service_block_context_t *service_block_context, uvm_fault_buffer_entry_t *fault_entry, bool allow_migration) { NV_STATUS perm_status; + UvmEventFatalReason fatal_reason; + uvm_fault_cancel_va_mode_t cancel_va_mode; + uvm_fault_access_type_t ret = UVM_FAULT_ACCESS_TYPE_COUNT; + uvm_va_block_context_t *va_block_context = &service_block_context->block_context; perm_status = uvm_va_block_check_logical_permissions(va_block, va_block_context, @@ -1072,16 +1248,20 @@ return fault_entry->fault_access_type; if (fault_entry->fault_access_type == UVM_FAULT_ACCESS_TYPE_PREFETCH) { - fault_entry->is_invalid_prefetch = true; - return UVM_FAULT_ACCESS_TYPE_COUNT; + // Only update the count the first time since logical permissions cannot + // change while we hold the VA space lock + // TODO: Bug 1750144: That might not be true with HMM. + if (service_block_context->num_retries == 0) + mark_fault_invalid_prefetch(batch_context, fault_entry); + + return ret; } // At this point we know that some fault instances cannot be serviced - fault_entry->is_fatal = true; - fault_entry->fatal_reason = uvm_tools_status_to_fatal_fault_reason(perm_status); + fatal_reason = uvm_tools_status_to_fatal_fault_reason(perm_status); if (fault_entry->fault_access_type > UVM_FAULT_ACCESS_TYPE_READ) { - fault_entry->replayable.cancel_va_mode = UVM_FAULT_CANCEL_VA_MODE_WRITE_AND_ATOMIC; + cancel_va_mode = UVM_FAULT_CANCEL_VA_MODE_WRITE_AND_ATOMIC; // If there are pending read accesses on the same page, we have to // service them before we can cancel the write/atomic faults. So we @@ -1094,19 +1274,23 @@ fault_entry->fault_address), UVM_FAULT_ACCESS_TYPE_READ, allow_migration); - if (perm_status == NV_OK) - return UVM_FAULT_ACCESS_TYPE_READ; - - // If that didn't succeed, cancel all faults - fault_entry->replayable.cancel_va_mode = UVM_FAULT_CANCEL_VA_MODE_ALL; - fault_entry->fatal_reason = uvm_tools_status_to_fatal_fault_reason(perm_status); + if (perm_status == NV_OK) { + ret = UVM_FAULT_ACCESS_TYPE_READ; + } + else { + // Read accesses didn't succeed, cancel all faults + cancel_va_mode = UVM_FAULT_CANCEL_VA_MODE_ALL; + fatal_reason = uvm_tools_status_to_fatal_fault_reason(perm_status); + } } } else { - fault_entry->replayable.cancel_va_mode = UVM_FAULT_CANCEL_VA_MODE_ALL; + cancel_va_mode = UVM_FAULT_CANCEL_VA_MODE_ALL; } - return UVM_FAULT_ACCESS_TYPE_COUNT; + mark_fault_fatal(batch_context, fault_entry, fatal_reason, cancel_va_mode); + + return ret; } // We notify the fault event for all faults within the block so that the @@ -1122,12 +1306,12 @@ // - NV_ERR_MORE_PROCESSING_REQUIRED if servicing needs allocation retry // - NV_ERR_NO_MEMORY if the faults could not be serviced due to OOM // - Any other value is a UVM-global error -static NV_STATUS service_batch_managed_faults_in_block_locked(uvm_gpu_t *gpu, - uvm_va_block_t *va_block, - uvm_va_block_retry_t *va_block_retry, - NvU32 first_fault_index, - uvm_fault_service_batch_context_t *batch_context, - NvU32 *block_faults) +static NV_STATUS service_fault_batch_block_locked(uvm_gpu_t *gpu, + uvm_va_block_t *va_block, + uvm_va_block_retry_t *va_block_retry, + uvm_fault_service_batch_context_t *batch_context, + NvU32 first_fault_index, + NvU32 *block_faults) { NV_STATUS status = NV_OK; NvU32 i; @@ -1139,6 +1323,7 @@ uvm_fault_buffer_entry_t **ordered_fault_cache = batch_context->ordered_fault_cache; uvm_service_block_context_t *block_context = &replayable_faults->block_service_context; uvm_va_space_t *va_space = uvm_va_block_get_va_space(va_block); + const uvm_va_policy_t *policy; NvU64 end; // Check that all uvm_fault_access_type_t values can fit into an NvU8 @@ -1164,13 +1349,13 @@ UVM_ASSERT(ordered_fault_cache[first_fault_index]->fault_address <= va_block->end); if (uvm_va_block_is_hmm(va_block)) { - uvm_hmm_find_policy_end(va_block, - &block_context->block_context, - ordered_fault_cache[first_fault_index]->fault_address, - &end); + policy = uvm_hmm_find_policy_end(va_block, + block_context->block_context.hmm.vma, + ordered_fault_cache[first_fault_index]->fault_address, + &end); } else { - block_context->block_context.policy = uvm_va_range_get_policy(va_block->va_range); + policy = uvm_va_range_get_policy(va_block->va_range); end = va_block->end; } @@ -1194,38 +1379,38 @@ UVM_ASSERT(current_entry->fault_access_type == uvm_fault_access_type_mask_highest(current_entry->access_type_mask)); - current_entry->is_fatal = false; + // Unserviceable faults were already skipped by the caller. There are no + // unserviceable fault types that could be in the same VA block as a + // serviceable fault. + UVM_ASSERT(!current_entry->is_fatal); current_entry->is_throttled = false; current_entry->is_invalid_prefetch = false; if (i > first_fault_index) { previous_entry = ordered_fault_cache[i - 1]; - is_duplicate = current_entry->fault_address == previous_entry->fault_address; + is_duplicate = check_fault_entry_duplicate(current_entry, previous_entry); } + // Only update counters the first time since logical permissions cannot + // change while we hold the VA space lock. + // TODO: Bug 1750144: That might not be true with HMM. if (block_context->num_retries == 0) { - uvm_perf_event_notify_gpu_fault(&va_space->perf_events, - va_block, - gpu->id, - block_context->block_context.policy->preferred_location, - current_entry, - batch_context->batch_id, - is_duplicate); + update_batch_and_notify_fault(gpu, + batch_context, + va_block, + policy->preferred_location, + current_entry, + is_duplicate); } // Service the most intrusive fault per page, only. Waive the rest if (is_duplicate) { - // Propagate the is_invalid_prefetch flag across all prefetch - // faults on the page - current_entry->is_invalid_prefetch = previous_entry->is_invalid_prefetch; - - // If a page is throttled, all faults on the page must be skipped - current_entry->is_throttled = previous_entry->is_throttled; + fault_entry_duplicate_flags(batch_context, current_entry, previous_entry); // The previous fault was non-fatal so the page has been already // serviced if (!previous_entry->is_fatal) - goto next; + continue; } // Ensure that the migratability iterator covers the current fault @@ -1236,15 +1421,16 @@ UVM_ASSERT(iter.start <= current_entry->fault_address && iter.end >= current_entry->fault_address); service_access_type = check_fault_access_permissions(gpu, + batch_context, va_block, - &block_context->block_context, + block_context, current_entry, iter.migratable); // Do not exit early due to logical errors such as access permission // violation. if (service_access_type == UVM_FAULT_ACCESS_TYPE_COUNT) - goto next; + continue; if (service_access_type != current_entry->fault_access_type) { // Some of the fault instances cannot be serviced due to invalid @@ -1263,15 +1449,21 @@ page_index, gpu->id, uvm_fault_access_type_to_prot(service_access_type))) - goto next; + continue; thrashing_hint = uvm_perf_thrashing_get_hint(va_block, current_entry->fault_address, gpu->id); if (thrashing_hint.type == UVM_PERF_THRASHING_HINT_TYPE_THROTTLE) { // Throttling is implemented by sleeping in the fault handler on // the CPU and by continuing to process faults on other pages on // the GPU - current_entry->is_throttled = true; - goto next; + // + // Only update the flag the first time since logical permissions + // cannot change while we hold the VA space lock. + // TODO: Bug 1750144: That might not be true with HMM. + if (block_context->num_retries == 0) + mark_fault_throttled(batch_context, current_entry); + + continue; } else if (thrashing_hint.type == UVM_PERF_THRASHING_HINT_TYPE_PIN) { if (block_context->thrashing_pin_count++ == 0) @@ -1286,7 +1478,7 @@ page_index, gpu->id, service_access_type_mask, - block_context->block_context.policy, + policy, &thrashing_hint, UVM_SERVICE_OPERATION_REPLAYABLE_FAULTS, &read_duplicate); @@ -1311,30 +1503,6 @@ first_page_index = page_index; if (page_index > last_page_index) last_page_index = page_index; - - next: - // Only update counters the first time since logical permissions cannot - // change while we hold the VA space lock - // TODO: Bug 1750144: That might not be true with HMM. - if (block_context->num_retries == 0) { - uvm_fault_utlb_info_t *utlb = &batch_context->utlbs[current_entry->fault_source.utlb_id]; - - if (current_entry->is_invalid_prefetch) - batch_context->num_invalid_prefetch_faults += current_entry->num_instances; - - if (is_duplicate) - batch_context->num_duplicate_faults += current_entry->num_instances; - else - batch_context->num_duplicate_faults += current_entry->num_instances - 1; - - if (current_entry->is_throttled) - batch_context->has_throttled_faults = true; - - if (current_entry->is_fatal) { - utlb->has_fatal_faults = true; - batch_context->has_fatal_faults = true; - } - } } // Apply the changes computed in the fault service block context, if there @@ -1348,7 +1516,7 @@ ++block_context->num_retries; - if (status == NV_OK && batch_context->has_fatal_faults) + if (status == NV_OK && batch_context->fatal_va_space) status = uvm_va_block_set_cancel(va_block, &block_context->block_context, gpu); return status; @@ -1361,11 +1529,11 @@ // // See the comments for function service_fault_batch_block_locked for // implementation details and error codes. -static NV_STATUS service_batch_managed_faults_in_block(uvm_gpu_t *gpu, - uvm_va_block_t *va_block, - NvU32 first_fault_index, - uvm_fault_service_batch_context_t *batch_context, - NvU32 *block_faults) +static NV_STATUS service_fault_batch_block(uvm_gpu_t *gpu, + uvm_va_block_t *va_block, + uvm_fault_service_batch_context_t *batch_context, + NvU32 first_fault_index, + NvU32 *block_faults) { NV_STATUS status; uvm_va_block_retry_t va_block_retry; @@ -1375,20 +1543,26 @@ fault_block_context->operation = UVM_SERVICE_OPERATION_REPLAYABLE_FAULTS; fault_block_context->num_retries = 0; + if (uvm_va_block_is_hmm(va_block)) + uvm_hmm_migrate_begin_wait(va_block); + uvm_mutex_lock(&va_block->lock); status = UVM_VA_BLOCK_RETRY_LOCKED(va_block, &va_block_retry, - service_batch_managed_faults_in_block_locked(gpu, - va_block, - &va_block_retry, - first_fault_index, - batch_context, - block_faults)); + service_fault_batch_block_locked(gpu, + va_block, + &va_block_retry, + batch_context, + first_fault_index, + block_faults)); tracker_status = uvm_tracker_add_tracker_safe(&batch_context->tracker, &va_block->tracker); uvm_mutex_unlock(&va_block->lock); + if (uvm_va_block_is_hmm(va_block)) + uvm_hmm_migrate_finish(va_block); + return status == NV_OK? tracker_status: status; } @@ -1402,98 +1576,565 @@ FAULT_SERVICE_MODE_CANCEL, } fault_service_mode_t; -static NV_STATUS service_non_managed_fault(uvm_fault_buffer_entry_t *current_entry, - const uvm_fault_buffer_entry_t *previous_entry, - NV_STATUS lookup_status, - uvm_gpu_va_space_t *gpu_va_space, - struct mm_struct *mm, - uvm_fault_service_batch_context_t *batch_context, - uvm_ats_fault_invalidate_t *ats_invalidate, - uvm_fault_utlb_info_t *utlb) +static void service_fault_batch_fatal(uvm_gpu_t *gpu, + uvm_fault_service_batch_context_t *batch_context, + NvU32 first_fault_index, + NV_STATUS status, + uvm_fault_cancel_va_mode_t cancel_va_mode, + NvU32 *block_faults) +{ + uvm_fault_buffer_entry_t *current_entry = batch_context->ordered_fault_cache[first_fault_index]; + const uvm_fault_buffer_entry_t *previous_entry = first_fault_index > 0 ? + batch_context->ordered_fault_cache[first_fault_index - 1] : NULL; + bool is_duplicate = check_fault_entry_duplicate(current_entry, previous_entry); + + if (is_duplicate) + fault_entry_duplicate_flags(batch_context, current_entry, previous_entry); + + if (current_entry->fault_access_type == UVM_FAULT_ACCESS_TYPE_PREFETCH) + mark_fault_invalid_prefetch(batch_context, current_entry); + else + mark_fault_fatal(batch_context, current_entry, uvm_tools_status_to_fatal_fault_reason(status), cancel_va_mode); + + (*block_faults)++; +} + +static void service_fault_batch_fatal_notify(uvm_gpu_t *gpu, + uvm_fault_service_batch_context_t *batch_context, + NvU32 first_fault_index, + NV_STATUS status, + uvm_fault_cancel_va_mode_t cancel_va_mode, + NvU32 *block_faults) { - NV_STATUS status = lookup_status; - bool is_duplicate = false; - UVM_ASSERT(utlb->num_pending_faults > 0); - UVM_ASSERT(lookup_status != NV_OK); + uvm_fault_buffer_entry_t *current_entry = batch_context->ordered_fault_cache[first_fault_index]; + const uvm_fault_buffer_entry_t *previous_entry = first_fault_index > 0 ? + batch_context->ordered_fault_cache[first_fault_index - 1] : NULL; + bool is_duplicate = check_fault_entry_duplicate(current_entry, previous_entry); - if (previous_entry) { - is_duplicate = (current_entry->va_space == previous_entry->va_space) && - (current_entry->fault_address == previous_entry->fault_address); + service_fault_batch_fatal(gpu, batch_context, first_fault_index, status, cancel_va_mode, block_faults); - if (is_duplicate) { - // Propagate the is_invalid_prefetch flag across all prefetch faults - // on the page - if (previous_entry->is_invalid_prefetch) - current_entry->is_invalid_prefetch = true; + update_batch_and_notify_fault(gpu, batch_context, NULL, UVM_ID_INVALID, current_entry, is_duplicate); +} - // If a page is throttled, all faults on the page must be skipped - if (previous_entry->is_throttled) - current_entry->is_throttled = true; +static NV_STATUS service_fault_batch_ats_sub_vma(uvm_gpu_va_space_t *gpu_va_space, + struct vm_area_struct *vma, + NvU64 base, + uvm_fault_service_batch_context_t *batch_context, + NvU32 fault_index_start, + NvU32 fault_index_end, + NvU32 *block_faults) +{ + NvU32 i; + NV_STATUS status = NV_OK; + uvm_gpu_t *gpu = gpu_va_space->gpu; + uvm_ats_fault_context_t *ats_context = &batch_context->ats_context; + const uvm_page_mask_t *read_fault_mask = &ats_context->read_fault_mask; + const uvm_page_mask_t *write_fault_mask = &ats_context->write_fault_mask; + const uvm_page_mask_t *reads_serviced_mask = &ats_context->reads_serviced_mask; + uvm_page_mask_t *faults_serviced_mask = &ats_context->faults_serviced_mask; + uvm_page_mask_t *faulted_mask = &ats_context->faulted_mask; + + UVM_ASSERT(vma); + + ats_context->client_type = UVM_FAULT_CLIENT_TYPE_GPC; + + uvm_page_mask_or(faulted_mask, write_fault_mask, read_fault_mask); + + status = uvm_ats_service_faults(gpu_va_space, vma, base, &batch_context->ats_context); + + // Remove prefetched pages from the serviced mask since fault servicing + // failures belonging to prefetch pages need to be ignored. + uvm_page_mask_and(faults_serviced_mask, faults_serviced_mask, faulted_mask); + + UVM_ASSERT(uvm_page_mask_subset(faults_serviced_mask, faulted_mask)); + + if ((status != NV_OK) || uvm_page_mask_equal(faults_serviced_mask, faulted_mask)) { + (*block_faults) += (fault_index_end - fault_index_start); + return status; + } + + // Check faults_serviced_mask and reads_serviced_mask for precise fault + // attribution after calling the ATS servicing routine. The + // errors returned from ATS servicing routine should only be + // global errors such as OOM or ECC. uvm_gpu_service_replayable_faults() + // handles global errors by calling cancel_fault_batch(). Precise + // attribution isn't currently supported in such cases. + // + // Precise fault attribution for global errors can be handled by + // servicing one fault at a time until fault servicing encounters an + // error. + // TODO: Bug 3989244: Precise ATS fault attribution for global errors. + for (i = fault_index_start; i < fault_index_end; i++) { + uvm_page_index_t page_index; + uvm_fault_cancel_va_mode_t cancel_va_mode; + uvm_fault_buffer_entry_t *current_entry = batch_context->ordered_fault_cache[i]; + uvm_fault_access_type_t access_type = current_entry->fault_access_type; + + page_index = (current_entry->fault_address - base) / PAGE_SIZE; + + if (uvm_page_mask_test(faults_serviced_mask, page_index)) { + (*block_faults)++; + continue; } + + if (access_type <= UVM_FAULT_ACCESS_TYPE_READ) { + cancel_va_mode = UVM_FAULT_CANCEL_VA_MODE_ALL; + } + else { + UVM_ASSERT(access_type >= UVM_FAULT_ACCESS_TYPE_WRITE); + if (uvm_fault_access_type_mask_test(current_entry->access_type_mask, UVM_FAULT_ACCESS_TYPE_READ) && + !uvm_page_mask_test(reads_serviced_mask, page_index)) + cancel_va_mode = UVM_FAULT_CANCEL_VA_MODE_ALL; + else + cancel_va_mode = UVM_FAULT_CANCEL_VA_MODE_WRITE_AND_ATOMIC; + } + + service_fault_batch_fatal(gpu, batch_context, i, NV_ERR_INVALID_ADDRESS, cancel_va_mode, block_faults); } - // Generate fault events for all fault packets - uvm_perf_event_notify_gpu_fault(¤t_entry->va_space->perf_events, - NULL, - gpu_va_space->gpu->id, - UVM_ID_INVALID, - current_entry, - batch_context->batch_id, - is_duplicate); + return status; +} - if (status != NV_ERR_INVALID_ADDRESS) - return status; +static void start_new_sub_batch(NvU64 *sub_batch_base, + NvU64 address, + NvU32 *sub_batch_fault_index, + NvU32 fault_index, + uvm_ats_fault_context_t *ats_context) +{ + uvm_page_mask_zero(&ats_context->read_fault_mask); + uvm_page_mask_zero(&ats_context->write_fault_mask); + + *sub_batch_fault_index = fault_index; + *sub_batch_base = UVM_VA_BLOCK_ALIGN_DOWN(address); +} + +static NV_STATUS service_fault_batch_ats_sub(uvm_gpu_va_space_t *gpu_va_space, + struct vm_area_struct *vma, + uvm_fault_service_batch_context_t *batch_context, + NvU32 fault_index, + NvU64 outer, + NvU32 *block_faults) +{ + NV_STATUS status = NV_OK; + NvU32 i = fault_index; + NvU32 sub_batch_fault_index; + NvU64 sub_batch_base; + uvm_fault_buffer_entry_t *previous_entry = NULL; + uvm_fault_buffer_entry_t *current_entry = batch_context->ordered_fault_cache[i]; + uvm_ats_fault_context_t *ats_context = &batch_context->ats_context; + uvm_page_mask_t *read_fault_mask = &ats_context->read_fault_mask; + uvm_page_mask_t *write_fault_mask = &ats_context->write_fault_mask; + uvm_gpu_t *gpu = gpu_va_space->gpu; + bool replay_per_va_block = + (gpu->parent->fault_buffer_info.replayable.replay_policy == UVM_PERF_FAULT_REPLAY_POLICY_BLOCK); + + UVM_ASSERT(vma); + + outer = min(outer, (NvU64) vma->vm_end); + + start_new_sub_batch(&sub_batch_base, current_entry->fault_address, &sub_batch_fault_index, i, ats_context); + + do { + uvm_page_index_t page_index; + NvU64 fault_address = current_entry->fault_address; + uvm_fault_access_type_t access_type = current_entry->fault_access_type; + bool is_duplicate = check_fault_entry_duplicate(current_entry, previous_entry); + + // ATS faults can't be unserviceable, since unserviceable faults require + // GMMU PTEs. + UVM_ASSERT(!current_entry->is_fatal); + + i++; + + update_batch_and_notify_fault(gpu_va_space->gpu, + batch_context, + NULL, + UVM_ID_INVALID, + current_entry, + is_duplicate); + + // End of sub-batch. Service faults gathered so far. + if (fault_address >= (sub_batch_base + UVM_VA_BLOCK_SIZE)) { + UVM_ASSERT(!uvm_page_mask_empty(read_fault_mask) || !uvm_page_mask_empty(write_fault_mask)); + + status = service_fault_batch_ats_sub_vma(gpu_va_space, + vma, + sub_batch_base, + batch_context, + sub_batch_fault_index, + i - 1, + block_faults); + if (status != NV_OK || replay_per_va_block) + break; - if (uvm_ats_can_service_faults(gpu_va_space, mm)) { - // The VA isn't managed. See if ATS knows about it, unless it is a - // duplicate and the previous fault was non-fatal so the page has - // already been serviced - if (!is_duplicate || previous_entry->is_fatal) - status = uvm_ats_service_fault_entry(gpu_va_space, current_entry, ats_invalidate); - else + start_new_sub_batch(&sub_batch_base, fault_address, &sub_batch_fault_index, i - 1, ats_context); + } + + page_index = (fault_address - sub_batch_base) / PAGE_SIZE; + + if ((access_type <= UVM_FAULT_ACCESS_TYPE_READ) || + uvm_fault_access_type_mask_test(current_entry->access_type_mask, UVM_FAULT_ACCESS_TYPE_READ)) + uvm_page_mask_set(read_fault_mask, page_index); + + if (access_type >= UVM_FAULT_ACCESS_TYPE_WRITE) + uvm_page_mask_set(write_fault_mask, page_index); + + previous_entry = current_entry; + current_entry = i < batch_context->num_coalesced_faults ? batch_context->ordered_fault_cache[i] : NULL; + + } while (current_entry && + (current_entry->fault_address < outer) && + (previous_entry->va_space == current_entry->va_space)); + + // Service the last sub-batch. + if ((status == NV_OK) && (!uvm_page_mask_empty(read_fault_mask) || !uvm_page_mask_empty(write_fault_mask))) { + status = service_fault_batch_ats_sub_vma(gpu_va_space, + vma, + sub_batch_base, + batch_context, + sub_batch_fault_index, + i, + block_faults); + } + + return status; +} + +static NV_STATUS service_fault_batch_ats(uvm_gpu_va_space_t *gpu_va_space, + struct mm_struct *mm, + uvm_fault_service_batch_context_t *batch_context, + NvU32 first_fault_index, + NvU64 outer, + NvU32 *block_faults) +{ + NvU32 i; + NV_STATUS status = NV_OK; + + for (i = first_fault_index; i < batch_context->num_coalesced_faults;) { + uvm_fault_buffer_entry_t *current_entry = batch_context->ordered_fault_cache[i]; + const uvm_fault_buffer_entry_t *previous_entry = i > first_fault_index ? + batch_context->ordered_fault_cache[i - 1] : NULL; + NvU64 fault_address = current_entry->fault_address; + struct vm_area_struct *vma; + NvU32 num_faults_before = (*block_faults); + + if (previous_entry && (previous_entry->va_space != current_entry->va_space)) + break; + + if (fault_address >= outer) + break; + + vma = find_vma_intersection(mm, fault_address, fault_address + 1); + if (!vma) { + // Since a vma wasn't found, cancel all accesses on the page since + // cancelling write and atomic accesses will not cancel pending read + // faults and this can lead to a deadlock since read faults need to + // be serviced first before cancelling write faults. + service_fault_batch_fatal_notify(gpu_va_space->gpu, + batch_context, + i, + NV_ERR_INVALID_ADDRESS, + UVM_FAULT_CANCEL_VA_MODE_ALL, + block_faults); + + // Do not fail due to logical errors. status = NV_OK; + + break; + } + + status = service_fault_batch_ats_sub(gpu_va_space, vma, batch_context, i, outer, block_faults); + if (status != NV_OK) + break; + + i += ((*block_faults) - num_faults_before); } - else { - // If the VA block cannot be found, set the fatal fault flag, - // unless it is a prefetch fault - if (current_entry->fault_access_type == UVM_FAULT_ACCESS_TYPE_PREFETCH) { - current_entry->is_invalid_prefetch = true; + + return status; +} + +static NV_STATUS service_fault_batch_dispatch(uvm_va_space_t *va_space, + uvm_gpu_va_space_t *gpu_va_space, + uvm_fault_service_batch_context_t *batch_context, + NvU32 fault_index, + NvU32 *block_faults, + bool replay_per_va_block) +{ + NV_STATUS status; + uvm_va_range_t *va_range = NULL; + uvm_va_range_t *va_range_next = NULL; + uvm_va_block_t *va_block; + uvm_gpu_t *gpu = gpu_va_space->gpu; + uvm_va_block_context_t *va_block_context = + &gpu->parent->fault_buffer_info.replayable.block_service_context.block_context; + uvm_fault_buffer_entry_t *current_entry = batch_context->ordered_fault_cache[fault_index]; + struct mm_struct *mm = va_block_context->mm; + NvU64 fault_address = current_entry->fault_address; + + (*block_faults) = 0; + + va_range_next = uvm_va_space_iter_first(va_space, fault_address, ~0ULL); + if (va_range_next && (fault_address >= va_range_next->node.start)) { + UVM_ASSERT(fault_address < va_range_next->node.end); + + va_range = va_range_next; + va_range_next = uvm_va_space_iter_next(va_range_next, ~0ULL); + } + + if (va_range) + status = uvm_va_block_find_create_in_range(va_space, va_range, fault_address, &va_block); + else if (mm) + status = uvm_hmm_va_block_find_create(va_space, fault_address, &va_block_context->hmm.vma, &va_block); + else + status = NV_ERR_INVALID_ADDRESS; + + if (status == NV_OK) { + status = service_fault_batch_block(gpu, va_block, batch_context, fault_index, block_faults); + } + else if ((status == NV_ERR_INVALID_ADDRESS) && uvm_ats_can_service_faults(gpu_va_space, mm)) { + NvU64 outer = ~0ULL; + + UVM_ASSERT(replay_per_va_block == + (gpu->parent->fault_buffer_info.replayable.replay_policy == UVM_PERF_FAULT_REPLAY_POLICY_BLOCK)); + + // Limit outer to the minimum of next va_range.start and first + // fault_address' next UVM_GMMU_ATS_GRANULARITY alignment so that it's + // enough to check whether the first fault in this dispatch belongs to a + // GMMU region. + if (va_range_next) { + outer = min(va_range_next->node.start, + UVM_ALIGN_DOWN(fault_address + UVM_GMMU_ATS_GRANULARITY, UVM_GMMU_ATS_GRANULARITY)); + } + + // ATS lookups are disabled on all addresses within the same + // UVM_GMMU_ATS_GRANULARITY as existing GMMU mappings (see documentation + // in uvm_mmu.h). User mode is supposed to reserve VAs as appropriate to + // prevent any system memory allocations from falling within the NO_ATS + // range of other GMMU mappings, so this shouldn't happen during normal + // operation. However, since this scenario may lead to infinite fault + // loops, we handle it by canceling the fault. + if (uvm_ats_check_in_gmmu_region(va_space, fault_address, va_range_next)) { + service_fault_batch_fatal_notify(gpu, + batch_context, + fault_index, + NV_ERR_INVALID_ADDRESS, + UVM_FAULT_CANCEL_VA_MODE_ALL, + block_faults); + + // Do not fail due to logical errors + status = NV_OK; } else { - current_entry->is_fatal = true; - current_entry->fatal_reason = uvm_tools_status_to_fatal_fault_reason(status); - current_entry->replayable.cancel_va_mode = UVM_FAULT_CANCEL_VA_MODE_ALL; + status = service_fault_batch_ats(gpu_va_space, mm, batch_context, fault_index, outer, block_faults); } + } + else { + service_fault_batch_fatal_notify(gpu, + batch_context, + fault_index, + status, + UVM_FAULT_CANCEL_VA_MODE_ALL, + block_faults); // Do not fail due to logical errors status = NV_OK; } - if (is_duplicate) - batch_context->num_duplicate_faults += current_entry->num_instances; - else - batch_context->num_duplicate_faults += current_entry->num_instances - 1; + return status; +} - if (current_entry->is_invalid_prefetch) - batch_context->num_invalid_prefetch_faults += current_entry->num_instances; +// Called when a fault in the batch has been marked fatal. Flush the buffer +// under the VA and mmap locks to remove any potential stale fatal faults, then +// service all new faults for just that VA space and cancel those which are +// fatal. Faults in other VA spaces are replayed when done and will be processed +// when normal fault servicing resumes. +static NV_STATUS service_fault_batch_for_cancel(uvm_gpu_t *gpu, uvm_fault_service_batch_context_t *batch_context) +{ + NV_STATUS status = NV_OK; + NvU32 i; + uvm_va_space_t *va_space = batch_context->fatal_va_space; + uvm_gpu_va_space_t *gpu_va_space = NULL; + struct mm_struct *mm; + uvm_replayable_fault_buffer_info_t *replayable_faults = &gpu->parent->fault_buffer_info.replayable; + uvm_service_block_context_t *service_context = &gpu->parent->fault_buffer_info.replayable.block_service_context; + uvm_va_block_context_t *va_block_context = &service_context->block_context; - if (current_entry->is_fatal) { - utlb->has_fatal_faults = true; - batch_context->has_fatal_faults = true; + UVM_ASSERT(gpu->parent->replayable_faults_supported); + UVM_ASSERT(va_space); + + // Perform the flush and re-fetch while holding the mmap_lock and the + // VA space lock. This avoids stale faults because it prevents any vma + // modifications (mmap, munmap, mprotect) from happening between the time HW + // takes the fault and we cancel it. + mm = uvm_va_space_mm_retain_lock(va_space); + va_block_context->mm = mm; + uvm_va_space_down_read(va_space); + + // We saw fatal faults in this VA space before. Flush while holding + // mmap_lock to make sure those faults come back (aren't stale). + // + // We need to wait until all old fault messages have arrived before + // flushing, hence UVM_GPU_BUFFER_FLUSH_MODE_WAIT_UPDATE_PUT. + status = fault_buffer_flush_locked(gpu, + UVM_GPU_BUFFER_FLUSH_MODE_WAIT_UPDATE_PUT, + UVM_FAULT_REPLAY_TYPE_START, + batch_context); + if (status != NV_OK) + goto done; + + // Wait for the flush's replay to finish to give the legitimate faults a + // chance to show up in the buffer again. + status = uvm_tracker_wait(&replayable_faults->replay_tracker); + if (status != NV_OK) + goto done; + + // We expect all replayed faults to have arrived in the buffer so we can re- + // service them. The replay-and-wait sequence above will ensure they're all + // in the HW buffer. When GSP owns the HW buffer, we also have to wait for + // GSP to copy all available faults from the HW buffer into the shadow + // buffer. + // + // TODO: Bug 2533557: This flush does not actually guarantee that GSP will + // copy over all faults. + status = hw_fault_buffer_flush_locked(gpu->parent); + if (status != NV_OK) + goto done; + + // If there is no GPU VA space for the GPU, ignore all faults in the VA + // space. This can happen if the GPU VA space has been destroyed since we + // unlocked the VA space in service_fault_batch. That means the fatal faults + // are stale, because unregistering the GPU VA space requires preempting the + // context and detaching all channels in that VA space. Restart fault + // servicing from the top. + gpu_va_space = uvm_gpu_va_space_get_by_parent_gpu(va_space, gpu->parent); + if (!gpu_va_space) + goto done; + + // Re-parse the new faults + batch_context->num_invalid_prefetch_faults = 0; + batch_context->num_duplicate_faults = 0; + batch_context->num_replays = 0; + batch_context->fatal_va_space = NULL; + batch_context->has_throttled_faults = false; + + status = fetch_fault_buffer_entries(gpu, batch_context, FAULT_FETCH_MODE_ALL); + if (status != NV_OK) + goto done; + + // No more faults left. Either the previously-seen fatal entry was stale, or + // RM killed the context underneath us. + if (batch_context->num_cached_faults == 0) + goto done; + + ++batch_context->batch_id; + + status = preprocess_fault_batch(gpu, batch_context); + if (status != NV_OK) { + if (status == NV_WARN_MORE_PROCESSING_REQUIRED) { + // Another flush happened due to stale faults or a context-fatal + // error. The previously-seen fatal fault might not exist anymore, + // so restart fault servicing from the top. + status = NV_OK; + } + + goto done; + } + + // Search for the target VA space + for (i = 0; i < batch_context->num_coalesced_faults; i++) { + uvm_fault_buffer_entry_t *current_entry = batch_context->ordered_fault_cache[i]; + UVM_ASSERT(current_entry->va_space); + if (current_entry->va_space == va_space) + break; } - if (current_entry->is_throttled) - batch_context->has_throttled_faults = true; + while (i < batch_context->num_coalesced_faults) { + uvm_fault_buffer_entry_t *current_entry = batch_context->ordered_fault_cache[i]; + + if (current_entry->va_space != va_space) + break; + + // service_fault_batch_dispatch() doesn't expect unserviceable faults. + // Just cancel them directly. + if (current_entry->is_fatal) { + status = cancel_fault_precise_va(gpu, current_entry, UVM_FAULT_CANCEL_VA_MODE_ALL); + if (status != NV_OK) + break; + + ++i; + } + else { + uvm_ats_fault_invalidate_t *ats_invalidate = &gpu->parent->fault_buffer_info.replayable.ats_invalidate; + NvU32 block_faults; + + ats_invalidate->tlb_batch_pending = false; + uvm_hmm_service_context_init(service_context); + + // Service all the faults that we can. We only really need to search + // for fatal faults, but attempting to service all is the easiest + // way to do that. + status = service_fault_batch_dispatch(va_space, gpu_va_space, batch_context, i, &block_faults, false); + if (status != NV_OK) { + // TODO: Bug 3900733: clean up locking in service_fault_batch(). + // We need to drop lock and retry. That means flushing and + // starting over. + if (status == NV_WARN_MORE_PROCESSING_REQUIRED) + status = NV_OK; + + break; + } + + // Invalidate TLBs before cancel to ensure that fatal faults don't + // get stuck in HW behind non-fatal faults to the same line. + status = uvm_ats_invalidate_tlbs(gpu_va_space, ats_invalidate, &batch_context->tracker); + if (status != NV_OK) + break; + + while (block_faults-- > 0) { + current_entry = batch_context->ordered_fault_cache[i]; + if (current_entry->is_fatal) { + status = cancel_fault_precise_va(gpu, current_entry, current_entry->replayable.cancel_va_mode); + if (status != NV_OK) + break; + } + + ++i; + } + } + } + +done: + uvm_va_space_up_read(va_space); + uvm_va_space_mm_release_unlock(va_space, mm); + + if (status == NV_OK) { + // There are two reasons to flush the fault buffer here. + // + // 1) Functional. We need to replay both the serviced non-fatal faults + // and the skipped faults in other VA spaces. The former need to be + // restarted and the latter need to be replayed so the normal fault + // service mechanism can fetch and process them. + // + // 2) Performance. After cancelling the fatal faults, a flush removes + // any potential duplicated fault that may have been added while + // processing the faults in this batch. This flush also avoids doing + // unnecessary processing after the fatal faults have been cancelled, + // so all the rest are unlikely to remain after a replay because the + // context is probably in the process of dying. + status = fault_buffer_flush_locked(gpu, + UVM_GPU_BUFFER_FLUSH_MODE_UPDATE_PUT, + UVM_FAULT_REPLAY_TYPE_START, + batch_context); + } return status; } - -// Scan the ordered view of faults and group them by different va_blocks. -// Service faults for each va_block, in batch. +// Scan the ordered view of faults and group them by different va_blocks +// (managed faults) and service faults for each va_block, in batch. +// Service non-managed faults one at a time as they are encountered during the +// scan. // -// This function returns NV_WARN_MORE_PROCESSING_REQUIRED if the fault buffer -// was flushed because the needs_fault_buffer_flush flag was set on some GPU VA -// space +// Fatal faults are marked for later processing by the caller. static NV_STATUS service_fault_batch(uvm_gpu_t *gpu, fault_service_mode_t service_mode, uvm_fault_service_batch_context_t *batch_context) @@ -1503,18 +2144,19 @@ uvm_va_space_t *va_space = NULL; uvm_gpu_va_space_t *gpu_va_space = NULL; uvm_ats_fault_invalidate_t *ats_invalidate = &gpu->parent->fault_buffer_info.replayable.ats_invalidate; + struct mm_struct *mm = NULL; const bool replay_per_va_block = service_mode != FAULT_SERVICE_MODE_CANCEL && gpu->parent->fault_buffer_info.replayable.replay_policy == UVM_PERF_FAULT_REPLAY_POLICY_BLOCK; - struct mm_struct *mm = NULL; - uvm_va_block_context_t *va_block_context = - &gpu->parent->fault_buffer_info.replayable.block_service_context.block_context; + uvm_service_block_context_t *service_context = + &gpu->parent->fault_buffer_info.replayable.block_service_context; + uvm_va_block_context_t *va_block_context = &service_context->block_context; UVM_ASSERT(gpu->parent->replayable_faults_supported); - ats_invalidate->write_faults_in_batch = false; + ats_invalidate->tlb_batch_pending = false; + uvm_hmm_service_context_init(service_context); for (i = 0; i < batch_context->num_coalesced_faults;) { - uvm_va_block_t *va_block; NvU32 block_faults; uvm_fault_buffer_entry_t *current_entry = batch_context->ordered_fault_cache[i]; uvm_fault_utlb_info_t *utlb = &batch_context->utlbs[current_entry->fault_source.utlb_id]; @@ -1546,89 +2188,53 @@ va_block_context->mm = mm; uvm_va_space_down_read(va_space); - gpu_va_space = uvm_gpu_va_space_get_by_parent_gpu(va_space, gpu->parent); - if (gpu_va_space && gpu_va_space->needs_fault_buffer_flush) { - // flush if required and clear the flush flag - status = fault_buffer_flush_locked(gpu, - UVM_GPU_BUFFER_FLUSH_MODE_UPDATE_PUT, - UVM_FAULT_REPLAY_TYPE_START, - batch_context); - gpu_va_space->needs_fault_buffer_flush = false; - - if (status == NV_OK) - status = NV_WARN_MORE_PROCESSING_REQUIRED; - - break; - } - - // The case where there is no valid GPU VA space for the GPU in this - // VA space is handled next } // Some faults could be already fatal if they cannot be handled by // the UVM driver if (current_entry->is_fatal) { ++i; - batch_context->has_fatal_faults = true; + if (!batch_context->fatal_va_space) + batch_context->fatal_va_space = va_space; + utlb->has_fatal_faults = true; UVM_ASSERT(utlb->num_pending_faults > 0); continue; } - if (!uvm_processor_mask_test(&va_space->registered_gpu_va_spaces, gpu->parent->id)) { + if (!gpu_va_space) { // If there is no GPU VA space for the GPU, ignore the fault. This // can happen if a GPU VA space is destroyed without explicitly - // freeing all memory ranges (destroying the VA range triggers a - // flush of the fault buffer) and there are stale entries in the + // freeing all memory ranges and there are stale entries in the // buffer that got fixed by the servicing in a previous batch. ++i; continue; } - // TODO: Bug 2103669: Service more than one ATS fault at a time so we - // don't do an unconditional VA range lookup for every ATS fault. - status = uvm_va_block_find_create(va_space, - current_entry->fault_address, - va_block_context, - &va_block); - if (status == NV_OK) { - status = service_batch_managed_faults_in_block(gpu_va_space->gpu, - va_block, - i, - batch_context, - &block_faults); - - // When service_batch_managed_faults_in_block returns != NV_OK - // something really bad happened - if (status != NV_OK) - goto fail; - - i += block_faults; + status = service_fault_batch_dispatch(va_space, + gpu_va_space, + batch_context, + i, + &block_faults, + replay_per_va_block); + // TODO: Bug 3900733: clean up locking in service_fault_batch(). + if (status == NV_WARN_MORE_PROCESSING_REQUIRED) { + uvm_va_space_up_read(va_space); + uvm_va_space_mm_release_unlock(va_space, mm); + mm = NULL; + va_space = NULL; + status = NV_OK; + continue; } - else { - const uvm_fault_buffer_entry_t *previous_entry = i == 0? NULL : batch_context->ordered_fault_cache[i - 1]; - - status = service_non_managed_fault(current_entry, - previous_entry, - status, - gpu_va_space, - mm, - batch_context, - ats_invalidate, - utlb); - // When service_non_managed_fault returns != NV_OK something really - // bad happened - if (status != NV_OK) - goto fail; + if (status != NV_OK) + goto fail; - ++i; - continue; - } + i += block_faults; // Don't issue replays in cancel mode - if (replay_per_va_block) { + if (replay_per_va_block && !batch_context->fatal_va_space) { status = push_replay_on_gpu(gpu, UVM_FAULT_REPLAY_TYPE_START, batch_context); if (status != NV_OK) goto fail; @@ -1640,8 +2246,6 @@ } } - // Only clobber status if invalidate_status != NV_OK, since status may also - // contain NV_WARN_MORE_PROCESSING_REQUIRED. if (va_space != NULL) { NV_STATUS invalidate_status = uvm_ats_invalidate_tlbs(gpu_va_space, ats_invalidate, &batch_context->tracker); if (invalidate_status != NV_OK) @@ -1849,77 +2453,48 @@ return false; } -typedef enum -{ - // Only cancel faults flagged as fatal - FAULT_CANCEL_MODE_FATAL, - - // Cancel all faults in the batch unconditionally - FAULT_CANCEL_MODE_ALL, -} fault_cancel_mode_t; - -// Cancel faults in the given fault service batch context. The function provides -// two different modes depending on the value of cancel_mode: -// - If cancel_mode == FAULT_CANCEL_MODE_FATAL, only faults flagged as fatal -// will be cancelled. In this case, the reason reported to tools is the one -// contained in the fault entry itself. -// - If cancel_mode == FAULT_CANCEL_MODE_ALL, all faults will be cancelled -// unconditionally. In this case, the reason reported to tools for non-fatal -// faults is the one passed to this function. -static NV_STATUS cancel_faults_precise_va(uvm_gpu_t *gpu, - uvm_fault_service_batch_context_t *batch_context, - fault_cancel_mode_t cancel_mode, - UvmEventFatalReason reason) +// Cancel all faults in the given fault service batch context, even those not +// marked as fatal. +static NV_STATUS cancel_faults_all(uvm_gpu_t *gpu, + uvm_fault_service_batch_context_t *batch_context, + UvmEventFatalReason reason) { NV_STATUS status = NV_OK; NV_STATUS fault_status; - uvm_va_space_t *va_space = NULL; - NvU32 i; + NvU32 i = 0; UVM_ASSERT(gpu->parent->fault_cancel_va_supported); - if (cancel_mode == FAULT_CANCEL_MODE_ALL) - UVM_ASSERT(reason != UvmEventFatalReasonInvalid); + UVM_ASSERT(reason != UvmEventFatalReasonInvalid); - for (i = 0; i < batch_context->num_coalesced_faults; ++i) { + while (i < batch_context->num_coalesced_faults && status == NV_OK) { uvm_fault_buffer_entry_t *current_entry = batch_context->ordered_fault_cache[i]; + uvm_va_space_t *va_space = current_entry->va_space; + bool skip_va_space; - UVM_ASSERT(current_entry->va_space); + UVM_ASSERT(va_space); - if (current_entry->va_space != va_space) { - // Fault on a different va_space, drop the lock of the old one... - if (va_space != NULL) - uvm_va_space_up_read(va_space); + uvm_va_space_down_read(va_space); - va_space = current_entry->va_space; + // If there is no GPU VA space for the GPU, ignore all faults in + // that VA space. This can happen if the GPU VA space has been + // destroyed since we unlocked the VA space in service_fault_batch. + // Ignoring the fault avoids targetting a PDB that might have been + // reused by another process. + skip_va_space = !uvm_gpu_va_space_get_by_parent_gpu(va_space, gpu->parent); + + for (; + i < batch_context->num_coalesced_faults && current_entry->va_space == va_space; + current_entry = batch_context->ordered_fault_cache[++i]) { + uvm_fault_cancel_va_mode_t cancel_va_mode; - // ... and take the lock of the new one - uvm_va_space_down_read(va_space); + if (skip_va_space) + continue; - // We don't need to check whether a buffer flush is required - // (due to VA range destruction). - // - For cancel_mode == FAULT_CANCEL_MODE_FATAL, once a fault is - // flagged as fatal we need to cancel it, even if its VA range no - // longer exists. - // - For cancel_mode == FAULT_CANCEL_MODE_ALL we don't care about - // any of this, we just want to trigger RC in RM. - } - - if (!uvm_processor_mask_test(&va_space->registered_gpu_va_spaces, gpu->parent->id)) { - // If there is no GPU VA space for the GPU, ignore the fault. - // This can happen if the GPU VA did not exist in - // service_fault_batch(), or it was destroyed since then. - // This is to avoid targetting a PDB that might have been reused - // by another process. - continue; - } - - // Cancel the fault - if (cancel_mode == FAULT_CANCEL_MODE_ALL || current_entry->is_fatal) { - uvm_fault_cancel_va_mode_t cancel_va_mode = current_entry->replayable.cancel_va_mode; - - // If cancelling unconditionally and the fault was not fatal, - // set the cancel reason passed to this function - if (!current_entry->is_fatal) { + if (current_entry->is_fatal) { + UVM_ASSERT(current_entry->fatal_reason != UvmEventFatalReasonInvalid); + cancel_va_mode = current_entry->replayable.cancel_va_mode; + } + else { current_entry->fatal_reason = reason; cancel_va_mode = UVM_FAULT_CANCEL_VA_MODE_ALL; } @@ -1928,17 +2503,13 @@ if (status != NV_OK) break; } - } - if (va_space != NULL) uvm_va_space_up_read(va_space); + } - // After cancelling the fatal faults, the fault buffer is flushed to remove - // any potential duplicated fault that may have been added while processing - // the faults in this batch. This flush also avoids doing unnecessary - // processing after the fatal faults have been cancelled, so all the rest - // are unlikely to remain after a replay because the context is probably in - // the process of dying. + // Because each cancel itself triggers a replay, there may be a large number + // of new duplicated faults in the buffer after cancelling all the known + // ones. Flushing the buffer discards them to avoid unnecessary processing. fault_status = fault_buffer_flush_locked(gpu, UVM_GPU_BUFFER_FLUSH_MODE_UPDATE_PUT, UVM_FAULT_REPLAY_TYPE_START, @@ -1986,12 +2557,12 @@ uvm_fault_service_batch_context_t *batch_context, UvmEventFatalReason reason) { - if (gpu->parent->fault_cancel_va_supported) { - cancel_faults_precise_va(gpu, batch_context, FAULT_CANCEL_MODE_ALL, reason); - return; - } - - cancel_fault_batch_tlb(gpu, batch_context, reason); + // Return code is ignored since we're on a global error path and wouldn't be + // able to recover anyway. + if (gpu->parent->fault_cancel_va_supported) + cancel_faults_all(gpu, batch_context, reason); + else + cancel_fault_batch_tlb(gpu, batch_context, reason); } @@ -2059,7 +2630,11 @@ // arriving. Therefore, in each iteration we just try to cancel faults // from uTLBs that contained fatal faults in the previous iterations // and will cause the TLB to stop generating new page faults after the - // following replay with type UVM_FAULT_REPLAY_TYPE_START_ACK_ALL + // following replay with type UVM_FAULT_REPLAY_TYPE_START_ACK_ALL. + // + // No need to use UVM_GPU_BUFFER_FLUSH_MODE_WAIT_UPDATE_PUT since we + // don't care too much about old faults, just new faults from uTLBs + // which faulted before the replay. status = fault_buffer_flush_locked(gpu, UVM_GPU_BUFFER_FLUSH_MODE_UPDATE_PUT, UVM_FAULT_REPLAY_TYPE_START_ACK_ALL, @@ -2074,11 +2649,14 @@ batch_context->num_invalid_prefetch_faults = 0; batch_context->num_replays = 0; - batch_context->has_fatal_faults = false; + batch_context->fatal_va_space = NULL; batch_context->has_throttled_faults = false; // 5) Fetch all faults from buffer - fetch_fault_buffer_entries(gpu, batch_context, FAULT_FETCH_MODE_ALL); + status = fetch_fault_buffer_entries(gpu, batch_context, FAULT_FETCH_MODE_ALL); + if (status != NV_OK) + break; + ++batch_context->batch_id; UVM_ASSERT(batch_context->num_cached_faults == batch_context->num_coalesced_faults); @@ -2118,9 +2696,6 @@ // 8) Service all non-fatal faults and mark all non-serviceable faults // as fatal status = service_fault_batch(gpu, FAULT_SERVICE_MODE_CANCEL, batch_context); - if (status == NV_WARN_MORE_PROCESSING_REQUIRED) - continue; - UVM_ASSERT(batch_context->num_replays == 0); if (status == NV_ERR_NO_MEMORY) continue; @@ -2128,7 +2703,7 @@ break; // No more fatal faults left, we are done - if (!batch_context->has_fatal_faults) + if (!batch_context->fatal_va_space) break; // 9) Search for uTLBs that contain fatal faults and meet the @@ -2150,13 +2725,9 @@ static NV_STATUS cancel_faults_precise(uvm_gpu_t *gpu, uvm_fault_service_batch_context_t *batch_context) { - UVM_ASSERT(batch_context->has_fatal_faults); - if (gpu->parent->fault_cancel_va_supported) { - return cancel_faults_precise_va(gpu, - batch_context, - FAULT_CANCEL_MODE_FATAL, - UvmEventFatalReasonInvalid); - } + UVM_ASSERT(batch_context->fatal_va_space); + if (gpu->parent->fault_cancel_va_supported) + return service_fault_batch_for_cancel(gpu, batch_context); return cancel_faults_precise_tlb(gpu, batch_context); } @@ -2168,6 +2739,8 @@ // If more than 66% of faults are invalid prefetch accesses, disable // prefetch faults for a while. + // num_invalid_prefetch_faults may be higher than the actual count. See the + // comment in mark_fault_invalid_prefetch(..). // Some tests rely on this logic (and ratio) to correctly disable prefetch // fault reporting. If the logic changes, the tests will have to be changed. if (parent_gpu->fault_buffer_info.prefetch_faults_enabled && @@ -2210,10 +2783,13 @@ batch_context->num_invalid_prefetch_faults = 0; batch_context->num_duplicate_faults = 0; batch_context->num_replays = 0; - batch_context->has_fatal_faults = false; + batch_context->fatal_va_space = NULL; batch_context->has_throttled_faults = false; - fetch_fault_buffer_entries(gpu, batch_context, FAULT_FETCH_MODE_BATCH_READY); + status = fetch_fault_buffer_entries(gpu, batch_context, FAULT_FETCH_MODE_BATCH_READY); + if (status != NV_OK) + break; + if (batch_context->num_cached_faults == 0) break; @@ -2235,9 +2811,6 @@ // was flushed num_replays += batch_context->num_replays; - if (status == NV_WARN_MORE_PROCESSING_REQUIRED) - continue; - enable_disable_prefetch_faults(gpu->parent, batch_context); if (status != NV_OK) { @@ -2251,10 +2824,17 @@ break; } - if (batch_context->has_fatal_faults) { + if (batch_context->fatal_va_space) { status = uvm_tracker_wait(&batch_context->tracker); - if (status == NV_OK) + if (status == NV_OK) { status = cancel_faults_precise(gpu, batch_context); + if (status == NV_OK) { + // Cancel handling should've issued at least one replay + UVM_ASSERT(batch_context->num_replays > 0); + ++num_batches; + continue; + } + } break; } diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/kernel-open/nvidia-uvm/uvm_gpu_replayable_faults.h nvidia-open-gpu-kernel-modules-535.161.08/kernel-open/nvidia-uvm/uvm_gpu_replayable_faults.h --- nvidia-open-gpu-kernel-modules-525.147.05/kernel-open/nvidia-uvm/uvm_gpu_replayable_faults.h 2023-10-25 20:33:36.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/kernel-open/nvidia-uvm/uvm_gpu_replayable_faults.h 2024-03-05 22:25:53.000000000 +0000 @@ -75,4 +75,7 @@ // only called from the ISR bottom half void uvm_gpu_service_replayable_faults(uvm_gpu_t *gpu); +// Returns true if UVM owns the hardware replayable fault buffer +bool uvm_parent_gpu_replayable_fault_buffer_is_uvm_owned(uvm_parent_gpu_t *parent_gpu); + #endif // __UVM_GPU_PAGE_FAULT_H__ diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/kernel-open/nvidia-uvm/uvm_gpu_semaphore.c nvidia-open-gpu-kernel-modules-535.161.08/kernel-open/nvidia-uvm/uvm_gpu_semaphore.c --- nvidia-open-gpu-kernel-modules-525.147.05/kernel-open/nvidia-uvm/uvm_gpu_semaphore.c 2023-10-25 20:33:33.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/kernel-open/nvidia-uvm/uvm_gpu_semaphore.c 2024-03-05 22:25:50.000000000 +0000 @@ -26,6 +26,7 @@ #include "uvm_global.h" #include "uvm_kvmalloc.h" #include "uvm_channel.h" // For UVM_GPU_SEMAPHORE_MAX_JUMP +#include "uvm_conf_computing.h" #define UVM_SEMAPHORE_SIZE 4 #define UVM_SEMAPHORE_PAGE_SIZE PAGE_SIZE @@ -44,6 +45,9 @@ // List of all the semaphore pages belonging to the pool struct list_head pages; + // Pages aperture. + uvm_aperture_t aperture; + // Count of free semaphores among all the pages NvU32 free_semaphores_count; @@ -66,11 +70,24 @@ DECLARE_BITMAP(free_semaphores, UVM_SEMAPHORE_COUNT_PER_PAGE); }; +static bool gpu_semaphore_pool_is_secure(uvm_gpu_semaphore_pool_t *pool) +{ + return uvm_conf_computing_mode_enabled(pool->gpu) && (pool->aperture == UVM_APERTURE_VID); +} + +static bool gpu_semaphore_is_secure(uvm_gpu_semaphore_t *semaphore) +{ + return gpu_semaphore_pool_is_secure(semaphore->page->pool); +} + static NvU32 get_index(uvm_gpu_semaphore_t *semaphore) { NvU32 offset; NvU32 index; + if (gpu_semaphore_is_secure(semaphore)) + return semaphore->conf_computing.index; + UVM_ASSERT(semaphore->payload != NULL); UVM_ASSERT(semaphore->page != NULL); @@ -118,6 +135,14 @@ return (val & ~UVM_SEMAPHORE_CANARY_MASK) == UVM_SEMAPHORE_CANARY_BASE; } +static bool semaphore_uses_canary(uvm_gpu_semaphore_pool_t *pool) +{ + // A pool allocated in the CPR of vidmem cannot be read/written from the + // CPU. + return !gpu_semaphore_pool_is_secure(pool) && UVM_IS_DEBUG(); + return UVM_IS_DEBUG(); +} + // Can the GPU access the semaphore, i.e., can Host/Esched address the semaphore // pool? static bool gpu_can_access_semaphore_pool(uvm_gpu_t *gpu, uvm_rm_mem_t *rm_mem) @@ -125,12 +150,34 @@ return ((uvm_rm_mem_get_gpu_uvm_va(rm_mem, gpu) + rm_mem->size - 1) < gpu->parent->max_host_va); } +// Secure semaphore pools are allocated in the CPR of vidmem and only mapped to +// the owning GPU as no other processor have access to it. +static NV_STATUS pool_alloc_secure_page(uvm_gpu_semaphore_pool_t *pool, + uvm_gpu_semaphore_pool_page_t *pool_page, + uvm_rm_mem_type_t memory_type) +{ + NV_STATUS status; + + UVM_ASSERT(gpu_semaphore_pool_is_secure(pool)); + status = uvm_rm_mem_alloc(pool->gpu, + memory_type, + UVM_SEMAPHORE_PAGE_SIZE, + UVM_CONF_COMPUTING_BUF_ALIGNMENT, + &pool_page->memory); + + if (status != NV_OK) + return status; + + return NV_OK; +} + static NV_STATUS pool_alloc_page(uvm_gpu_semaphore_pool_t *pool) { NV_STATUS status; uvm_gpu_semaphore_pool_page_t *pool_page; NvU32 *payloads; size_t i; + uvm_rm_mem_type_t memory_type = (pool->aperture == UVM_APERTURE_SYS) ? UVM_RM_MEM_TYPE_SYS : UVM_RM_MEM_TYPE_GPU; uvm_assert_mutex_locked(&pool->mutex); @@ -141,13 +188,24 @@ pool_page->pool = pool; + // Whenever the Confidential Computing feature is enabled, engines can + // access semaphores only in the CPR of vidmem. Mapping to other GPUs is + // also disabled. + if (gpu_semaphore_pool_is_secure(pool)) { + status = pool_alloc_secure_page(pool, pool_page, memory_type); + + if (status != NV_OK) + goto error; + } + else { status = uvm_rm_mem_alloc_and_map_all(pool->gpu, - UVM_RM_MEM_TYPE_SYS, + memory_type, UVM_SEMAPHORE_PAGE_SIZE, 0, &pool_page->memory); if (status != NV_OK) goto error; + } // Verify the GPU can access the semaphore pool. UVM_ASSERT(gpu_can_access_semaphore_pool(pool->gpu, pool_page->memory)); @@ -158,8 +216,7 @@ list_add(&pool_page->all_pages_node, &pool->pages); pool->free_semaphores_count += UVM_SEMAPHORE_COUNT_PER_PAGE; - // Initialize the semaphore payloads to known values - if (UVM_IS_DEBUG()) { + if (semaphore_uses_canary(pool)) { payloads = uvm_rm_mem_get_cpu_va(pool_page->memory); for (i = 0; i < UVM_SEMAPHORE_COUNT_PER_PAGE; i++) payloads[i] = make_canary(0); @@ -175,8 +232,6 @@ static void pool_free_page(uvm_gpu_semaphore_pool_page_t *page) { uvm_gpu_semaphore_pool_t *pool; - NvU32 *payloads; - size_t i; UVM_ASSERT(page); pool = page->pool; @@ -189,9 +244,9 @@ "count: %u\n", pool->free_semaphores_count); - // Check for semaphore release-after-free - if (UVM_IS_DEBUG()) { - payloads = uvm_rm_mem_get_cpu_va(page->memory); + if (semaphore_uses_canary(pool)) { + size_t i; + NvU32 *payloads = uvm_rm_mem_get_cpu_va(page->memory); for (i = 0; i < UVM_SEMAPHORE_COUNT_PER_PAGE; i++) UVM_ASSERT(is_canary(payloads[i])); } @@ -222,11 +277,18 @@ if (semaphore_index == UVM_SEMAPHORE_COUNT_PER_PAGE) continue; - semaphore->payload = (NvU32*)((char*)uvm_rm_mem_get_cpu_va(page->memory) + semaphore_index * UVM_SEMAPHORE_SIZE); + if (gpu_semaphore_pool_is_secure(pool)) { + semaphore->conf_computing.index = semaphore_index; + } + else { + semaphore->payload = (NvU32*)((char*)uvm_rm_mem_get_cpu_va(page->memory) + + semaphore_index * UVM_SEMAPHORE_SIZE); + } + semaphore->page = page; - // Check for semaphore release-after-free - UVM_ASSERT(is_canary(uvm_gpu_semaphore_get_payload(semaphore))); + if (semaphore_uses_canary(pool)) + UVM_ASSERT(is_canary(uvm_gpu_semaphore_get_payload(semaphore))); uvm_gpu_semaphore_set_payload(semaphore, 0); @@ -265,7 +327,7 @@ // Write a known value lower than the current payload in an attempt to catch // release-after-free and acquire-after-free. - if (UVM_IS_DEBUG()) + if (semaphore_uses_canary(pool)) uvm_gpu_semaphore_set_payload(semaphore, make_canary(uvm_gpu_semaphore_get_payload(semaphore))); uvm_mutex_lock(&pool->mutex); @@ -293,12 +355,26 @@ pool->free_semaphores_count = 0; pool->gpu = gpu; + pool->aperture = UVM_APERTURE_SYS; *pool_out = pool; return NV_OK; } +NV_STATUS uvm_gpu_semaphore_secure_pool_create(uvm_gpu_t *gpu, uvm_gpu_semaphore_pool_t **pool_out) +{ + NV_STATUS status; + + UVM_ASSERT(uvm_conf_computing_mode_enabled(gpu)); + + status = uvm_gpu_semaphore_pool_create(gpu, pool_out); + if (status == NV_OK) + (*pool_out)->aperture = UVM_APERTURE_VID; + + return status; +} + void uvm_gpu_semaphore_pool_destroy(uvm_gpu_semaphore_pool_t *pool) { uvm_gpu_semaphore_pool_page_t *page; @@ -374,13 +450,16 @@ NvU64 uvm_gpu_semaphore_get_gpu_va(uvm_gpu_semaphore_t *semaphore, uvm_gpu_t *gpu, bool is_proxy_va_space) { NvU32 index = get_index(semaphore); - NvU64 base_va = uvm_rm_mem_get_gpu_va(semaphore->page->memory, gpu, is_proxy_va_space); + NvU64 base_va = uvm_rm_mem_get_gpu_va(semaphore->page->memory, gpu, is_proxy_va_space).address; return base_va + UVM_SEMAPHORE_SIZE * index; } NvU32 uvm_gpu_semaphore_get_payload(uvm_gpu_semaphore_t *semaphore) { + if (gpu_semaphore_is_secure(semaphore)) + return UVM_GPU_READ_ONCE(semaphore->conf_computing.cached_payload); + return UVM_GPU_READ_ONCE(*semaphore->payload); } @@ -397,6 +476,10 @@ // being optimized out on non-SMP configs (we need them for interacting with // the GPU correctly even on non-SMP). mb(); + + if (gpu_semaphore_is_secure(semaphore)) + UVM_GPU_WRITE_ONCE(semaphore->conf_computing.cached_payload, payload); + else UVM_GPU_WRITE_ONCE(*semaphore->payload, payload); } @@ -424,9 +507,22 @@ return true; } +bool tracking_semaphore_uses_mutex(uvm_gpu_tracking_semaphore_t *tracking_semaphore) +{ + uvm_gpu_t *gpu = tracking_semaphore->semaphore.page->pool->gpu; + + UVM_ASSERT(tracking_semaphore_check_gpu(tracking_semaphore)); + if (uvm_conf_computing_mode_enabled(gpu)) + return true; + + return false; +} + + NV_STATUS uvm_gpu_tracking_semaphore_alloc(uvm_gpu_semaphore_pool_t *pool, uvm_gpu_tracking_semaphore_t *tracking_sem) { NV_STATUS status; + uvm_lock_order_t order = UVM_LOCK_ORDER_LEAF; memset(tracking_sem, 0, sizeof(*tracking_sem)); @@ -436,7 +532,14 @@ UVM_ASSERT(uvm_gpu_semaphore_get_payload(&tracking_sem->semaphore) == 0); - uvm_spin_lock_init(&tracking_sem->lock, UVM_LOCK_ORDER_LEAF); + if (uvm_conf_computing_mode_enabled(pool->gpu)) + order = UVM_LOCK_ORDER_SECURE_SEMAPHORE; + + if (tracking_semaphore_uses_mutex(tracking_sem)) + uvm_mutex_init(&tracking_sem->m_lock, order); + else + uvm_spin_lock_init(&tracking_sem->s_lock, order); + atomic64_set(&tracking_sem->completed_value, 0); tracking_sem->queued_value = 0; @@ -448,15 +551,119 @@ uvm_gpu_semaphore_free(&tracking_sem->semaphore); } +static bool should_skip_secure_semaphore_update(NvU32 last_observed_notifier, NvU32 gpu_notifier) +{ + // No new value, or the GPU is currently writing the new encrypted material + // and no change in value would still result in corrupted data. + return (last_observed_notifier == gpu_notifier) || (gpu_notifier % 2); +} + +static void uvm_gpu_semaphore_encrypted_payload_update(uvm_channel_t *channel, uvm_gpu_semaphore_t *semaphore) +{ + UvmCslIv local_iv; + NvU32 local_payload; + NvU32 new_sem_value; + NvU32 gpu_notifier; + NvU32 last_observed_notifier; + NvU32 new_gpu_notifier = 0; + NvU32 iv_index = 0; + + // A channel can have multiple entries pending and the tracking semaphore + // update of each entry can race with this function. Since the semaphore + // needs to be updated to release a used entry, we never need more + // than 'num_gpfifo_entries' re-tries. + unsigned tries_left = channel->num_gpfifo_entries; + NV_STATUS status = NV_OK; + NvU8 local_auth_tag[UVM_CONF_COMPUTING_AUTH_TAG_SIZE]; + UvmCslIv *ivs_cpu_addr = semaphore->conf_computing.ivs; + void *auth_tag_cpu_addr = uvm_rm_mem_get_cpu_va(semaphore->conf_computing.auth_tag); + NvU32 *gpu_notifier_cpu_addr = (NvU32 *)uvm_rm_mem_get_cpu_va(semaphore->conf_computing.notifier); + NvU32 *payload_cpu_addr = (NvU32 *)uvm_rm_mem_get_cpu_va(semaphore->conf_computing.encrypted_payload); + uvm_gpu_t *gpu = uvm_channel_get_gpu(channel); + + UVM_ASSERT(uvm_conf_computing_mode_enabled(gpu)); + UVM_ASSERT(uvm_channel_is_ce(channel)); + + last_observed_notifier = semaphore->conf_computing.last_observed_notifier; + gpu_notifier = UVM_READ_ONCE(*gpu_notifier_cpu_addr); + UVM_ASSERT(last_observed_notifier <= gpu_notifier); + + if (should_skip_secure_semaphore_update(last_observed_notifier, gpu_notifier)) + return; + + do { + gpu_notifier = UVM_READ_ONCE(*gpu_notifier_cpu_addr); + + // Odd notifier value means there's an update in progress. + if (gpu_notifier % 2) + continue; + + // Make sure no memory accesses happen before we read the notifier + smp_mb__after_atomic(); + + iv_index = (gpu_notifier / 2) % channel->num_gpfifo_entries; + memcpy(local_auth_tag, auth_tag_cpu_addr, sizeof(local_auth_tag)); + local_payload = UVM_READ_ONCE(*payload_cpu_addr); + memcpy(&local_iv, &ivs_cpu_addr[iv_index], sizeof(local_iv)); + + // Make sure the second read of notifier happens after + // all memory accesses. + smp_mb__before_atomic(); + new_gpu_notifier = UVM_READ_ONCE(*gpu_notifier_cpu_addr); + tries_left--; + } while ((tries_left > 0) && ((gpu_notifier != new_gpu_notifier) || (gpu_notifier % 2))); + + if (!tries_left) { + status = NV_ERR_INVALID_STATE; + goto error; + } + + if (gpu_notifier == new_gpu_notifier) { + status = uvm_conf_computing_cpu_decrypt(channel, + &new_sem_value, + &local_payload, + &local_iv, + sizeof(new_sem_value), + &local_auth_tag); + + if (status != NV_OK) + goto error; + + uvm_gpu_semaphore_set_payload(semaphore, new_sem_value); + UVM_WRITE_ONCE(semaphore->conf_computing.last_observed_notifier, new_gpu_notifier); + } + + return; + +error: + // Decryption failure is a fatal error as well as running out of try left. + // Upon testing, all decryption happened within one try, anything that + // would require ten retry would be considered active tampering with the + // data structures. + uvm_global_set_fatal_error(status); +} + static NvU64 update_completed_value_locked(uvm_gpu_tracking_semaphore_t *tracking_semaphore) { NvU64 old_value = atomic64_read(&tracking_semaphore->completed_value); // The semaphore value is the bottom 32 bits of completed_value NvU32 old_sem_value = (NvU32)old_value; - NvU32 new_sem_value = uvm_gpu_semaphore_get_payload(&tracking_semaphore->semaphore); + NvU32 new_sem_value; NvU64 new_value; - uvm_assert_spinlock_locked(&tracking_semaphore->lock); + if (tracking_semaphore_uses_mutex(tracking_semaphore)) + uvm_assert_mutex_locked(&tracking_semaphore->m_lock); + else + uvm_assert_spinlock_locked(&tracking_semaphore->s_lock); + + if (tracking_semaphore->semaphore.conf_computing.encrypted_payload) { + // TODO: Bug 4008734: [UVM][HCC] Extend secure tracking semaphore + // mechanism to all semaphore + uvm_channel_t *channel = container_of(tracking_semaphore, uvm_channel_t, tracking_sem); + uvm_gpu_semaphore_encrypted_payload_update(channel, &tracking_semaphore->semaphore); + } + + new_sem_value = uvm_gpu_semaphore_get_payload(&tracking_semaphore->semaphore); // The following logic to update the completed value is very subtle, it // helps to read https://www.kernel.org/doc/Documentation/memory-barriers.txt @@ -465,7 +672,7 @@ if (old_sem_value == new_sem_value) { // No progress since the last update. // No additional memory barrier required in this case as completed_value - // is always updated under the spinlock that this thread just acquired. + // is always updated under the lock that this thread just acquired. // That guarantees full ordering with all the accesses the thread that // updated completed_value did under the lock including the GPU // semaphore read. @@ -492,7 +699,7 @@ (NvU64)(uintptr_t)tracking_semaphore->semaphore.payload, old_value, new_value); - // Use an atomic write even though the spinlock is held so that the value can + // Use an atomic write even though the lock is held so that the value can // be (carefully) read atomically outside of the lock. // // atomic64_set() on its own doesn't imply any memory barriers and we need @@ -520,9 +727,9 @@ // guarantees that no accesses will be ordered above the atomic (and hence // the GPU semaphore read). // - // Notably the soon following uvm_spin_unlock() is a release barrier that - // allows later memory accesses to be reordered above it and hence doesn't - // provide the necessary ordering with the GPU semaphore read. + // Notably the soon following unlock is a release barrier that allows later + // memory accesses to be reordered above it and hence doesn't provide the + // necessary ordering with the GPU semaphore read. // // Also notably this would still need to be handled if we ever switch to // atomic64_set_release() and atomic64_read_acquire() for accessing @@ -539,11 +746,17 @@ // Check that the GPU which owns the semaphore is still present UVM_ASSERT(tracking_semaphore_check_gpu(tracking_semaphore)); - uvm_spin_lock(&tracking_semaphore->lock); + if (tracking_semaphore_uses_mutex(tracking_semaphore)) + uvm_mutex_lock(&tracking_semaphore->m_lock); + else + uvm_spin_lock(&tracking_semaphore->s_lock); completed = update_completed_value_locked(tracking_semaphore); - uvm_spin_unlock(&tracking_semaphore->lock); + if (tracking_semaphore_uses_mutex(tracking_semaphore)) + uvm_mutex_unlock(&tracking_semaphore->m_lock); + else + uvm_spin_unlock(&tracking_semaphore->s_lock); return completed; } diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/kernel-open/nvidia-uvm/uvm_gpu_semaphore.h nvidia-open-gpu-kernel-modules-535.161.08/kernel-open/nvidia-uvm/uvm_gpu_semaphore.h --- nvidia-open-gpu-kernel-modules-525.147.05/kernel-open/nvidia-uvm/uvm_gpu_semaphore.h 2023-10-25 20:33:33.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/kernel-open/nvidia-uvm/uvm_gpu_semaphore.h 2024-03-05 22:25:50.000000000 +0000 @@ -47,6 +47,16 @@ // Pointer to the memory location NvU32 *payload; + struct { + NvU16 index; + NvU32 cached_payload; + uvm_rm_mem_t *encrypted_payload; + uvm_rm_mem_t *notifier; + uvm_rm_mem_t *auth_tag; + UvmCslIv *ivs; + NvU32 last_pushed_notifier; + NvU32 last_observed_notifier; + } conf_computing; }; // A primitive used for tracking progress of the GPU @@ -67,7 +77,10 @@ atomic64_t completed_value; // Lock protecting updates to the completed_value - uvm_spinlock_t lock; + union { + uvm_spinlock_t s_lock; + uvm_mutex_t m_lock; + }; // Last queued value // All accesses to the queued value should be handled by the user of the GPU @@ -78,6 +91,12 @@ // Create a semaphore pool for a GPU. NV_STATUS uvm_gpu_semaphore_pool_create(uvm_gpu_t *gpu, uvm_gpu_semaphore_pool_t **pool_out); +// When the Confidential Computing feature is enabled, semaphore pools +// associated with CE channels are allocated in the CPR of vidmem and as such +// have all the associated access restrictions. Because of this, they're called +// secure pools and secure semaphores are allocated out of said secure pools. +NV_STATUS uvm_gpu_semaphore_secure_pool_create(uvm_gpu_t *gpu, uvm_gpu_semaphore_pool_t **pool_out); + // Destroy a semaphore pool // Locking: // - Global lock needs to be held in read mode (for unmapping from all GPUs) @@ -90,6 +109,9 @@ // Allocate a semaphore from the pool. // The semaphore will be mapped on all GPUs currently registered with the UVM // driver, and on all new GPUs which will be registered in the future. +// Unless the Confidential Computing feature is enabled and the pool is a +// secure pool. In this case, it is only mapped to the GPU that holds the +// allocation. // The mappings are added to UVM's internal address space, and (in SR-IOV heavy) // to the proxy address space. // diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/kernel-open/nvidia-uvm/uvm_hal.c nvidia-open-gpu-kernel-modules-535.161.08/kernel-open/nvidia-uvm/uvm_hal.c --- nvidia-open-gpu-kernel-modules-525.147.05/kernel-open/nvidia-uvm/uvm_hal.c 2023-10-25 20:33:34.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/kernel-open/nvidia-uvm/uvm_hal.c 2024-03-05 22:25:51.000000000 +0000 @@ -1,5 +1,5 @@ /******************************************************************************* - Copyright (c) 2015-2021 NVIDIA Corporation + Copyright (c) 2015-2023 NVIDIA Corporation Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation files (the "Software"), to @@ -44,11 +44,16 @@ #include "clc86f.h" #include "clc8b5.h" +static int uvm_downgrade_force_membar_sys = 1; +module_param(uvm_downgrade_force_membar_sys, uint, 0644); +MODULE_PARM_DESC(uvm_downgrade_force_membar_sys, "Force all TLB invalidation downgrades to use MEMBAR_SYS"); + #define CE_OP_COUNT (sizeof(uvm_ce_hal_t) / sizeof(void *)) #define HOST_OP_COUNT (sizeof(uvm_host_hal_t) / sizeof(void *)) #define ARCH_OP_COUNT (sizeof(uvm_arch_hal_t) / sizeof(void *)) #define FAULT_BUFFER_OP_COUNT (sizeof(uvm_fault_buffer_hal_t) / sizeof(void *)) #define ACCESS_COUNTER_BUFFER_OP_COUNT (sizeof(uvm_access_counter_buffer_hal_t) / sizeof(void *)) +#define SEC2_OP_COUNT (sizeof(uvm_sec2_hal_t) / sizeof(void *)) // Table for copy engine functions. // Each entry is associated with a copy engine class through the 'class' field. @@ -61,7 +66,7 @@ .id = MAXWELL_DMA_COPY_A, .u.ce_ops = { .init = uvm_hal_maxwell_ce_init, - .method_validate = uvm_hal_method_validate_stub, + .method_is_valid = uvm_hal_method_is_valid_stub, .semaphore_release = uvm_hal_maxwell_ce_semaphore_release, .semaphore_timestamp = uvm_hal_maxwell_ce_semaphore_timestamp, .semaphore_reduction_inc = uvm_hal_maxwell_ce_semaphore_reduction_inc, @@ -69,15 +74,18 @@ .offset_in_out = uvm_hal_maxwell_ce_offset_in_out, .phys_mode = uvm_hal_maxwell_ce_phys_mode, .plc_mode = uvm_hal_maxwell_ce_plc_mode, - .memcopy_validate = uvm_hal_ce_memcopy_validate_stub, + .memcopy_copy_type = uvm_hal_maxwell_ce_memcopy_copy_type, + .memcopy_is_valid = uvm_hal_ce_memcopy_is_valid_stub, .memcopy_patch_src = uvm_hal_ce_memcopy_patch_src_stub, .memcopy = uvm_hal_maxwell_ce_memcopy, .memcopy_v_to_v = uvm_hal_maxwell_ce_memcopy_v_to_v, - .memset_validate = uvm_hal_ce_memset_validate_stub, + .memset_is_valid = uvm_hal_ce_memset_is_valid_stub, .memset_1 = uvm_hal_maxwell_ce_memset_1, .memset_4 = uvm_hal_maxwell_ce_memset_4, .memset_8 = uvm_hal_maxwell_ce_memset_8, .memset_v_4 = uvm_hal_maxwell_ce_memset_v_4, + .encrypt = uvm_hal_maxwell_ce_encrypt_unsupported, + .decrypt = uvm_hal_maxwell_ce_decrypt_unsupported, } }, { @@ -99,7 +107,15 @@ { .id = VOLTA_DMA_COPY_A, .parent_id = PASCAL_DMA_COPY_B, - .u.ce_ops = {}, + .u.ce_ops = { + .semaphore_release = uvm_hal_volta_ce_semaphore_release, + .semaphore_timestamp = uvm_hal_volta_ce_semaphore_timestamp, + .semaphore_reduction_inc = uvm_hal_volta_ce_semaphore_reduction_inc, + .memcopy = uvm_hal_volta_ce_memcopy, + .memset_1 = uvm_hal_volta_ce_memset_1, + .memset_4 = uvm_hal_volta_ce_memset_4, + .memset_8 = uvm_hal_volta_ce_memset_8, + }, }, { .id = TURING_DMA_COPY_A, @@ -110,22 +126,22 @@ .id = AMPERE_DMA_COPY_A, .parent_id = TURING_DMA_COPY_A, .u.ce_ops = { - .method_validate = uvm_hal_ampere_ce_method_validate_c6b5, + .method_is_valid = uvm_hal_ampere_ce_method_is_valid_c6b5, .phys_mode = uvm_hal_ampere_ce_phys_mode, - .memcopy_validate = uvm_hal_ampere_ce_memcopy_validate_c6b5, + .memcopy_is_valid = uvm_hal_ampere_ce_memcopy_is_valid_c6b5, .memcopy_patch_src = uvm_hal_ampere_ce_memcopy_patch_src_c6b5, - .memset_validate = uvm_hal_ampere_ce_memset_validate_c6b5, + .memset_is_valid = uvm_hal_ampere_ce_memset_is_valid_c6b5, }, }, { .id = AMPERE_DMA_COPY_B, .parent_id = AMPERE_DMA_COPY_A, .u.ce_ops = { - .method_validate = uvm_hal_method_validate_stub, + .method_is_valid = uvm_hal_method_is_valid_stub, .plc_mode = uvm_hal_ampere_ce_plc_mode_c7b5, - .memcopy_validate = uvm_hal_ce_memcopy_validate_stub, + .memcopy_is_valid = uvm_hal_ce_memcopy_is_valid_stub, .memcopy_patch_src = uvm_hal_ce_memcopy_patch_src_stub, - .memset_validate = uvm_hal_ce_memset_validate_stub, + .memset_is_valid = uvm_hal_ce_memset_is_valid_stub, }, }, { @@ -137,9 +153,14 @@ .semaphore_reduction_inc = uvm_hal_hopper_ce_semaphore_reduction_inc, .offset_out = uvm_hal_hopper_ce_offset_out, .offset_in_out = uvm_hal_hopper_ce_offset_in_out, + .memcopy_copy_type = uvm_hal_hopper_ce_memcopy_copy_type, .memset_1 = uvm_hal_hopper_ce_memset_1, .memset_4 = uvm_hal_hopper_ce_memset_4, .memset_8 = uvm_hal_hopper_ce_memset_8, + .memcopy_is_valid = uvm_hal_hopper_ce_memcopy_is_valid, + .memset_is_valid = uvm_hal_hopper_ce_memset_is_valid, + .encrypt = uvm_hal_hopper_ce_encrypt, + .decrypt = uvm_hal_hopper_ce_decrypt, }, }, }; @@ -152,8 +173,8 @@ .id = KEPLER_CHANNEL_GPFIFO_B, .u.host_ops = { .init = uvm_hal_maxwell_host_init_noop, - .method_validate = uvm_hal_method_validate_stub, - .sw_method_validate = uvm_hal_method_validate_stub, + .method_is_valid = uvm_hal_method_is_valid_stub, + .sw_method_is_valid = uvm_hal_method_is_valid_stub, .wait_for_idle = uvm_hal_maxwell_host_wait_for_idle, .membar_sys = uvm_hal_maxwell_host_membar_sys, // No MEMBAR GPU until Pascal, just do a MEMBAR SYS. @@ -235,8 +256,8 @@ .id = AMPERE_CHANNEL_GPFIFO_A, .parent_id = TURING_CHANNEL_GPFIFO_A, .u.host_ops = { - .method_validate = uvm_hal_ampere_host_method_validate, - .sw_method_validate = uvm_hal_ampere_host_sw_method_validate, + .method_is_valid = uvm_hal_ampere_host_method_is_valid, + .sw_method_is_valid = uvm_hal_ampere_host_sw_method_is_valid, .clear_faulted_channel_sw_method = uvm_hal_ampere_host_clear_faulted_channel_sw_method, .clear_faulted_channel_register = uvm_hal_ampere_host_clear_faulted_channel_register, .tlb_invalidate_all = uvm_hal_ampere_host_tlb_invalidate_all, @@ -248,8 +269,8 @@ .id = HOPPER_CHANNEL_GPFIFO_A, .parent_id = AMPERE_CHANNEL_GPFIFO_A, .u.host_ops = { - .method_validate = uvm_hal_method_validate_stub, - .sw_method_validate = uvm_hal_method_validate_stub, + .method_is_valid = uvm_hal_method_is_valid_stub, + .sw_method_is_valid = uvm_hal_method_is_valid_stub, .semaphore_acquire = uvm_hal_hopper_host_semaphore_acquire, .semaphore_release = uvm_hal_hopper_host_semaphore_release, .semaphore_timestamp = uvm_hal_hopper_host_semaphore_timestamp, @@ -352,11 +373,12 @@ .read_get = uvm_hal_maxwell_fault_buffer_read_get_unsupported, .write_get = uvm_hal_maxwell_fault_buffer_write_get_unsupported, .get_ve_id = uvm_hal_maxwell_fault_buffer_get_ve_id_unsupported, - .parse_entry = uvm_hal_maxwell_fault_buffer_parse_entry_unsupported, + .parse_replayable_entry = uvm_hal_maxwell_fault_buffer_parse_replayable_entry_unsupported, .entry_is_valid = uvm_hal_maxwell_fault_buffer_entry_is_valid_unsupported, .entry_clear_valid = uvm_hal_maxwell_fault_buffer_entry_clear_valid_unsupported, .entry_size = uvm_hal_maxwell_fault_buffer_entry_size_unsupported, .parse_non_replayable_entry = uvm_hal_maxwell_fault_buffer_parse_non_replayable_entry_unsupported, + .get_fault_type = uvm_hal_maxwell_fault_buffer_get_fault_type_unsupported, } }, { @@ -374,10 +396,11 @@ .read_put = uvm_hal_pascal_fault_buffer_read_put, .read_get = uvm_hal_pascal_fault_buffer_read_get, .write_get = uvm_hal_pascal_fault_buffer_write_get, - .parse_entry = uvm_hal_pascal_fault_buffer_parse_entry, + .parse_replayable_entry = uvm_hal_pascal_fault_buffer_parse_replayable_entry, .entry_is_valid = uvm_hal_pascal_fault_buffer_entry_is_valid, .entry_clear_valid = uvm_hal_pascal_fault_buffer_entry_clear_valid, .entry_size = uvm_hal_pascal_fault_buffer_entry_size, + .get_fault_type = uvm_hal_pascal_fault_buffer_get_fault_type, } }, { @@ -388,8 +411,9 @@ .read_get = uvm_hal_volta_fault_buffer_read_get, .write_get = uvm_hal_volta_fault_buffer_write_get, .get_ve_id = uvm_hal_volta_fault_buffer_get_ve_id, - .parse_entry = uvm_hal_volta_fault_buffer_parse_entry, + .parse_replayable_entry = uvm_hal_volta_fault_buffer_parse_replayable_entry, .parse_non_replayable_entry = uvm_hal_volta_fault_buffer_parse_non_replayable_entry, + .get_fault_type = uvm_hal_volta_fault_buffer_get_fault_type, } }, { @@ -481,6 +505,59 @@ }, }; +static uvm_hal_class_ops_t sec2_table[] = +{ + { + .id = NV2080_CTRL_MC_ARCH_INFO_ARCHITECTURE_GM000, + .u.sec2_ops = { + .init = uvm_hal_maxwell_sec2_init_noop, + .decrypt = uvm_hal_maxwell_sec2_decrypt_unsupported, + .semaphore_release = uvm_hal_maxwell_sec2_semaphore_release_unsupported, + .semaphore_timestamp = uvm_hal_maxwell_sec2_semaphore_timestamp_unsupported, + } + }, + { + .id = NV2080_CTRL_MC_ARCH_INFO_ARCHITECTURE_GM200, + .parent_id = NV2080_CTRL_MC_ARCH_INFO_ARCHITECTURE_GM000, + .u.sec2_ops = {} + }, + { + .id = NV2080_CTRL_MC_ARCH_INFO_ARCHITECTURE_GP100, + .parent_id = NV2080_CTRL_MC_ARCH_INFO_ARCHITECTURE_GM200, + .u.sec2_ops = {} + }, + { + .id = NV2080_CTRL_MC_ARCH_INFO_ARCHITECTURE_GV100, + .parent_id = NV2080_CTRL_MC_ARCH_INFO_ARCHITECTURE_GP100, + .u.sec2_ops = {} + }, + { + .id = NV2080_CTRL_MC_ARCH_INFO_ARCHITECTURE_TU100, + .parent_id = NV2080_CTRL_MC_ARCH_INFO_ARCHITECTURE_GV100, + .u.sec2_ops = {} + }, + { + .id = NV2080_CTRL_MC_ARCH_INFO_ARCHITECTURE_GA100, + .parent_id = NV2080_CTRL_MC_ARCH_INFO_ARCHITECTURE_TU100, + .u.sec2_ops = {} + }, + { + .id = NV2080_CTRL_MC_ARCH_INFO_ARCHITECTURE_AD100, + .parent_id = NV2080_CTRL_MC_ARCH_INFO_ARCHITECTURE_GA100, + .u.sec2_ops = {} + }, + { + .id = NV2080_CTRL_MC_ARCH_INFO_ARCHITECTURE_GH100, + .parent_id = NV2080_CTRL_MC_ARCH_INFO_ARCHITECTURE_AD100, + .u.sec2_ops = { + .init = uvm_hal_hopper_sec2_init, + .semaphore_release = uvm_hal_hopper_sec2_semaphore_release, + .semaphore_timestamp = uvm_hal_hopper_sec2_semaphore_timestamp_unsupported, + .decrypt = uvm_hal_hopper_sec2_decrypt, + } + }, +}; + static inline uvm_hal_class_ops_t *ops_find_by_id(uvm_hal_class_ops_t *table, NvU32 row_count, NvU32 id) { NvLength i; @@ -584,6 +661,15 @@ return status; } + status = ops_init_from_parent(sec2_table, + ARRAY_SIZE(sec2_table), + SEC2_OP_COUNT, + offsetof(uvm_hal_class_ops_t, u.sec2_ops)); + if (status != NV_OK) { + UVM_ERR_PRINT("ops_init_from_parent(sec2_table) failed: %s\n", nvstatusToString(status)); + return status; + } + return NV_OK; } @@ -634,17 +720,34 @@ parent_gpu->access_counter_buffer_hal = &class_ops->u.access_counter_buffer_ops; + class_ops = ops_find_by_id(sec2_table, ARRAY_SIZE(sec2_table), gpu_info->gpuArch); + if (class_ops == NULL) { + UVM_ERR_PRINT("SEC2 HAL not found, GPU %s, arch: 0x%X\n", parent_gpu->name, gpu_info->gpuArch); + return NV_ERR_INVALID_CLASS; + } + + parent_gpu->sec2_hal = &class_ops->u.sec2_ops; + return NV_OK; } +static void hal_override_properties(uvm_parent_gpu_t *parent_gpu) +{ + // Access counters are currently not supported in vGPU. + // + // TODO: Bug 200692962: Add support for access counters in vGPU + if (parent_gpu->virt_mode != UVM_VIRT_MODE_NONE) + parent_gpu->access_counters_supported = false; + // Access counters are not supported in CC. + else if (uvm_conf_computing_mode_enabled_parent(parent_gpu)) + parent_gpu->access_counters_supported = false; +} + void uvm_hal_init_properties(uvm_parent_gpu_t *parent_gpu) { parent_gpu->arch_hal->init_properties(parent_gpu); - // Override the HAL when in non-passthrough virtualization - // TODO: Bug 200692962: [UVM] Add support for access counters in UVM on SR-IOV configurations - if (parent_gpu->virt_mode != UVM_VIRT_MODE_NONE) - parent_gpu->access_counters_supported = false; + hal_override_properties(parent_gpu); } void uvm_hal_tlb_invalidate_membar(uvm_push_t *push, uvm_membar_t membar) @@ -663,6 +766,44 @@ uvm_hal_membar(gpu, push, membar); } +bool uvm_hal_membar_before_semaphore(uvm_push_t *push) +{ + uvm_membar_t membar = uvm_push_get_and_reset_membar_flag(push); + + if (membar == UVM_MEMBAR_NONE) { + // No MEMBAR requested, don't use a flush. + return false; + } + + if (membar == UVM_MEMBAR_GPU) { + // MEMBAR GPU requested, do it on the HOST and skip the engine flush as + // it doesn't have this capability. + uvm_hal_wfi_membar(push, UVM_MEMBAR_GPU); + return false; + } + + // By default do a MEMBAR SYS and for that we can just use flush on the + // semaphore operation. + return true; +} + +uvm_membar_t uvm_hal_downgrade_membar_type(uvm_gpu_t *gpu, bool is_local_vidmem) +{ + // If the mapped memory was local, and we're not using a coherence protocol, + // we only need a GPU-local membar. This is because all accesses to this + // memory, including those from other processors like the CPU or peer GPUs, + // must come through this GPU's L2. In all current architectures, MEMBAR_GPU + // is sufficient to resolve ordering at the L2 level. + if (is_local_vidmem && !uvm_gpu_is_coherent(gpu->parent) && !uvm_downgrade_force_membar_sys) + return UVM_MEMBAR_GPU; + + // If the mapped memory was remote, or if a coherence protocol can cache + // this GPU's memory, then there are external ways for other processors to + // access the memory without always going the local GPU L2, so we must use a + // MEMBAR_SYS. + return UVM_MEMBAR_SYS; +} + const char *uvm_aperture_string(uvm_aperture_t aperture) { BUILD_BUG_ON(UVM_APERTURE_MAX != 12); @@ -823,12 +964,12 @@ UVM_DBG_PRINT(" tag %x\n", entry->tag); } -bool uvm_hal_method_validate_stub(uvm_push_t *push, NvU32 method_address, NvU32 method_data) +bool uvm_hal_method_is_valid_stub(uvm_push_t *push, NvU32 method_address, NvU32 method_data) { return true; } -bool uvm_hal_ce_memcopy_validate_stub(uvm_push_t *push, uvm_gpu_address_t dst, uvm_gpu_address_t src) +bool uvm_hal_ce_memcopy_is_valid_stub(uvm_push_t *push, uvm_gpu_address_t dst, uvm_gpu_address_t src) { return true; } @@ -837,7 +978,7 @@ { } -bool uvm_hal_ce_memset_validate_stub(uvm_push_t *push, uvm_gpu_address_t dst, size_t element_size) +bool uvm_hal_ce_memset_is_valid_stub(uvm_push_t *push, uvm_gpu_address_t dst, size_t num_elements, size_t element_size) { return true; } diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/kernel-open/nvidia-uvm/uvm_hal.h nvidia-open-gpu-kernel-modules-535.161.08/kernel-open/nvidia-uvm/uvm_hal.h --- nvidia-open-gpu-kernel-modules-525.147.05/kernel-open/nvidia-uvm/uvm_hal.h 2023-10-25 20:33:34.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/kernel-open/nvidia-uvm/uvm_hal.h 2024-03-05 22:25:51.000000000 +0000 @@ -1,5 +1,5 @@ /******************************************************************************* - Copyright (c) 2015-2022 NVIDIA Corporation + Copyright (c) 2015-2023 NVIDIA Corporation Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation files (the "Software"), to @@ -34,20 +34,22 @@ // A dummy method validation that always returns true; it can be used to skip // CE/Host/SW method validations for a given architecture -bool uvm_hal_method_validate_stub(uvm_push_t *push, NvU32 method_address, NvU32 method_data); +bool uvm_hal_method_is_valid_stub(uvm_push_t *push, NvU32 method_address, NvU32 method_data); typedef void (*uvm_hal_init_t)(uvm_push_t *push); void uvm_hal_maxwell_ce_init(uvm_push_t *push); void uvm_hal_maxwell_host_init_noop(uvm_push_t *push); void uvm_hal_pascal_host_init(uvm_push_t *push); +void uvm_hal_maxwell_sec2_init_noop(uvm_push_t *push); +void uvm_hal_hopper_sec2_init(uvm_push_t *push); // Host method validation -typedef bool (*uvm_hal_host_method_validate)(uvm_push_t *push, NvU32 method_address, NvU32 method_data); -bool uvm_hal_ampere_host_method_validate(uvm_push_t *push, NvU32 method_address, NvU32 method_data); +typedef bool (*uvm_hal_host_method_is_valid)(uvm_push_t *push, NvU32 method_address, NvU32 method_data); +bool uvm_hal_ampere_host_method_is_valid(uvm_push_t *push, NvU32 method_address, NvU32 method_data); // SW method validation -typedef bool (*uvm_hal_host_sw_method_validate)(uvm_push_t *push, NvU32 method_address, NvU32 method_data); -bool uvm_hal_ampere_host_sw_method_validate(uvm_push_t *push, NvU32 method_address, NvU32 method_data); +typedef bool (*uvm_hal_host_sw_method_is_valid)(uvm_push_t *push, NvU32 method_address, NvU32 method_data); +bool uvm_hal_ampere_host_sw_method_is_valid(uvm_push_t *push, NvU32 method_address, NvU32 method_data); // Wait for idle typedef void (*uvm_hal_wait_for_idle_t)(uvm_push_t *push); @@ -207,8 +209,11 @@ typedef void (*uvm_hal_semaphore_release_t)(uvm_push_t *push, NvU64 gpu_va, NvU32 payload); void uvm_hal_maxwell_host_semaphore_release(uvm_push_t *push, NvU64 gpu_va, NvU32 payload); void uvm_hal_maxwell_ce_semaphore_release(uvm_push_t *push, NvU64 gpu_va, NvU32 payload); +void uvm_hal_maxwell_sec2_semaphore_release_unsupported(uvm_push_t *push, NvU64 gpu_va, NvU32 payload); void uvm_hal_pascal_ce_semaphore_release(uvm_push_t *push, NvU64 gpu_va, NvU32 payload); +void uvm_hal_volta_ce_semaphore_release(uvm_push_t *push, NvU64 gpu_va, NvU32 payload); void uvm_hal_turing_host_semaphore_release(uvm_push_t *push, NvU64 gpu_va, NvU32 payload); +void uvm_hal_hopper_sec2_semaphore_release(uvm_push_t *push, NvU64 gpu_va, NvU32 payload); void uvm_hal_hopper_ce_semaphore_release(uvm_push_t *push, NvU64 gpu_va, NvU32 payload); void uvm_hal_hopper_host_semaphore_release(uvm_push_t *push, NvU64 gpu_va, NvU32 payload); @@ -220,21 +225,37 @@ typedef void (*uvm_hal_semaphore_timestamp_t)(uvm_push_t *push, NvU64 gpu_va); void uvm_hal_maxwell_ce_semaphore_timestamp(uvm_push_t *push, NvU64 gpu_va); void uvm_hal_pascal_ce_semaphore_timestamp(uvm_push_t *push, NvU64 gpu_va); +void uvm_hal_volta_ce_semaphore_timestamp(uvm_push_t *push, NvU64 gpu_va); void uvm_hal_hopper_ce_semaphore_timestamp(uvm_push_t *push, NvU64 gpu_va); void uvm_hal_maxwell_host_semaphore_timestamp(uvm_push_t *push, NvU64 gpu_va); void uvm_hal_volta_host_semaphore_timestamp(uvm_push_t *push, NvU64 gpu_va); void uvm_hal_hopper_host_semaphore_timestamp(uvm_push_t *push, NvU64 gpu_va); +void uvm_hal_maxwell_sec2_semaphore_timestamp_unsupported(uvm_push_t *push, NvU64 gpu_va); +void uvm_hal_hopper_sec2_semaphore_timestamp_unsupported(uvm_push_t *push, NvU64 gpu_va); + typedef void (*uvm_hal_semaphore_acquire_t)(uvm_push_t *push, NvU64 gpu_va, NvU32 payload); void uvm_hal_maxwell_host_semaphore_acquire(uvm_push_t *push, NvU64 gpu_va, NvU32 payload); void uvm_hal_turing_host_semaphore_acquire(uvm_push_t *push, NvU64 gpu_va, NvU32 payload); void uvm_hal_hopper_host_semaphore_acquire(uvm_push_t *push, NvU64 gpu_va, NvU32 payload); -typedef void (*uvm_hal_host_set_gpfifo_entry_t)(NvU64 *fifo_entry, NvU64 pushbuffer_va, NvU32 pushbuffer_length); -void uvm_hal_maxwell_host_set_gpfifo_entry(NvU64 *fifo_entry, NvU64 pushbuffer_va, NvU32 pushbuffer_length); -void uvm_hal_turing_host_set_gpfifo_entry(NvU64 *fifo_entry, NvU64 pushbuffer_va, NvU32 pushbuffer_length); -void uvm_hal_hopper_host_set_gpfifo_entry(NvU64 *fifo_entry, NvU64 pushbuffer_va, NvU32 pushbuffer_length); +typedef void (*uvm_hal_host_set_gpfifo_entry_t)(NvU64 *fifo_entry, + NvU64 pushbuffer_va, + NvU32 pushbuffer_length, + uvm_gpfifo_sync_t sync_flag); +void uvm_hal_maxwell_host_set_gpfifo_entry(NvU64 *fifo_entry, + NvU64 pushbuffer_va, + NvU32 pushbuffer_length, + uvm_gpfifo_sync_t sync_flag); +void uvm_hal_turing_host_set_gpfifo_entry(NvU64 *fifo_entry, + NvU64 pushbuffer_va, + NvU32 pushbuffer_length, + uvm_gpfifo_sync_t sync_flag); +void uvm_hal_hopper_host_set_gpfifo_entry(NvU64 *fifo_entry, + NvU64 pushbuffer_va, + NvU32 pushbuffer_length, + uvm_gpfifo_sync_t sync_flag); typedef void (*uvm_hal_host_set_gpfifo_noop_t)(NvU64 *fifo_entry); void uvm_hal_maxwell_host_set_gpfifo_noop(NvU64 *fifo_entry); @@ -271,17 +292,22 @@ NvU32 uvm_hal_maxwell_ce_plc_mode(void); NvU32 uvm_hal_ampere_ce_plc_mode_c7b5(void); +typedef NvU32 (*uvm_hal_ce_memcopy_type_t)(uvm_push_t *push, uvm_gpu_address_t dst, uvm_gpu_address_t src); +NvU32 uvm_hal_maxwell_ce_memcopy_copy_type(uvm_push_t *push, uvm_gpu_address_t dst, uvm_gpu_address_t src); +NvU32 uvm_hal_hopper_ce_memcopy_copy_type(uvm_push_t *push, uvm_gpu_address_t dst, uvm_gpu_address_t src); + // CE method validation -typedef bool (*uvm_hal_ce_method_validate)(uvm_push_t *push, NvU32 method_address, NvU32 method_data); -bool uvm_hal_ampere_ce_method_validate_c6b5(uvm_push_t *push, NvU32 method_address, NvU32 method_data); +typedef bool (*uvm_hal_ce_method_is_valid)(uvm_push_t *push, NvU32 method_address, NvU32 method_data); +bool uvm_hal_ampere_ce_method_is_valid_c6b5(uvm_push_t *push, NvU32 method_address, NvU32 method_data); // Memcopy validation. // The validation happens at the start of the memcopy (uvm_hal_memcopy_t) -// execution. Use uvm_hal_ce_memcopy_validate_stub to skip the validation for +// execution. Use uvm_hal_ce_memcopy_is_valid_stub to skip the validation for // a given architecture. -typedef bool (*uvm_hal_ce_memcopy_validate)(uvm_push_t *push, uvm_gpu_address_t dst, uvm_gpu_address_t src); -bool uvm_hal_ce_memcopy_validate_stub(uvm_push_t *push, uvm_gpu_address_t dst, uvm_gpu_address_t src); -bool uvm_hal_ampere_ce_memcopy_validate_c6b5(uvm_push_t *push, uvm_gpu_address_t dst, uvm_gpu_address_t src); +typedef bool (*uvm_hal_ce_memcopy_is_valid)(uvm_push_t *push, uvm_gpu_address_t dst, uvm_gpu_address_t src); +bool uvm_hal_ce_memcopy_is_valid_stub(uvm_push_t *push, uvm_gpu_address_t dst, uvm_gpu_address_t src); +bool uvm_hal_ampere_ce_memcopy_is_valid_c6b5(uvm_push_t *push, uvm_gpu_address_t dst, uvm_gpu_address_t src); +bool uvm_hal_hopper_ce_memcopy_is_valid(uvm_push_t *push, uvm_gpu_address_t dst, uvm_gpu_address_t src); // Patching of the memcopy source; if not needed for a given architecture use // the (empty) uvm_hal_ce_memcopy_patch_src_stub implementation @@ -296,6 +322,7 @@ // UVM_PUSH_FLAG_NEXT_CE_* flags with uvm_push_set_flag(). typedef void (*uvm_hal_memcopy_t)(uvm_push_t *push, uvm_gpu_address_t dst, uvm_gpu_address_t src, size_t size); void uvm_hal_maxwell_ce_memcopy(uvm_push_t *push, uvm_gpu_address_t dst, uvm_gpu_address_t src, size_t size); +void uvm_hal_volta_ce_memcopy(uvm_push_t *push, uvm_gpu_address_t dst, uvm_gpu_address_t src, size_t size); // Simple wrapper for uvm_hal_memcopy_t with both addresses being virtual typedef void (*uvm_hal_memcopy_v_to_v_t)(uvm_push_t *push, NvU64 dst, NvU64 src, size_t size); @@ -303,11 +330,21 @@ // Memset validation. // The validation happens at the start of the memset (uvm_hal_memset_*_t) -// execution. Use uvm_hal_ce_memset_validate_stub to skip the validation for +// execution. Use uvm_hal_ce_memset_is_valid_stub to skip the validation for // a given architecture. -typedef bool (*uvm_hal_ce_memset_validate)(uvm_push_t *push, uvm_gpu_address_t dst, size_t element_size); -bool uvm_hal_ce_memset_validate_stub(uvm_push_t *push, uvm_gpu_address_t dst, size_t element_size); -bool uvm_hal_ampere_ce_memset_validate_c6b5(uvm_push_t *push, uvm_gpu_address_t dst, size_t element_size); +typedef bool (*uvm_hal_ce_memset_is_valid)(uvm_push_t *push, + uvm_gpu_address_t dst, + size_t num_elements, + size_t element_size); +bool uvm_hal_ce_memset_is_valid_stub(uvm_push_t *push, uvm_gpu_address_t dst, size_t num_elements, size_t element_size); +bool uvm_hal_ampere_ce_memset_is_valid_c6b5(uvm_push_t *push, + uvm_gpu_address_t dst, + size_t num_elements, + size_t element_size); +bool uvm_hal_hopper_ce_memset_is_valid(uvm_push_t *push, + uvm_gpu_address_t dst, + size_t num_elements, + size_t element_size); // Memset size bytes at dst to a given N-byte input value. // @@ -329,10 +366,62 @@ void uvm_hal_maxwell_ce_memset_8(uvm_push_t *push, uvm_gpu_address_t dst, NvU64 value, size_t size); void uvm_hal_maxwell_ce_memset_v_4(uvm_push_t *push, NvU64 dst_va, NvU32 value, size_t size); +void uvm_hal_volta_ce_memset_1(uvm_push_t *push, uvm_gpu_address_t dst, NvU8 value, size_t size); +void uvm_hal_volta_ce_memset_4(uvm_push_t *push, uvm_gpu_address_t dst, NvU32 value, size_t size); +void uvm_hal_volta_ce_memset_8(uvm_push_t *push, uvm_gpu_address_t dst, NvU64 value, size_t size); + void uvm_hal_hopper_ce_memset_1(uvm_push_t *push, uvm_gpu_address_t dst, NvU8 value, size_t size); void uvm_hal_hopper_ce_memset_4(uvm_push_t *push, uvm_gpu_address_t dst, NvU32 value, size_t size); void uvm_hal_hopper_ce_memset_8(uvm_push_t *push, uvm_gpu_address_t dst, NvU64 value, size_t size); +// Encrypts the contents of the source buffer into the destination buffer, up to +// the given size. The authentication tag of the encrypted contents is written +// to auth_tag, so it can be verified later on by a decrypt operation. +// +// The addressing modes of the destination and authentication tag addresses +// should match. If the addressing mode is physical, then the address apertures +// should also match. +typedef void (*uvm_hal_ce_encrypt_t)(uvm_push_t *push, + uvm_gpu_address_t dst, + uvm_gpu_address_t src, + NvU32 size, + uvm_gpu_address_t auth_tag); + +// Decrypts the contents of the source buffer into the destination buffer, up to +// the given size. The method also verifies the integrity of the encrypted +// buffer by calculating its authentication tag, and comparing it with the one +// provided as argument. +// +// The addressing modes of the source and authentication tag addresses should +// match. If the addressing mode is physical, then the address apertures should +// also match. +typedef void (*uvm_hal_ce_decrypt_t)(uvm_push_t *push, + uvm_gpu_address_t dst, + uvm_gpu_address_t src, + NvU32 size, + uvm_gpu_address_t auth_tag); + +void uvm_hal_maxwell_ce_encrypt_unsupported(uvm_push_t *push, + uvm_gpu_address_t dst, + uvm_gpu_address_t src, + NvU32 size, + uvm_gpu_address_t auth_tag); +void uvm_hal_maxwell_ce_decrypt_unsupported(uvm_push_t *push, + uvm_gpu_address_t dst, + uvm_gpu_address_t src, + NvU32 size, + uvm_gpu_address_t auth_tag); +void uvm_hal_hopper_ce_encrypt(uvm_push_t *push, + uvm_gpu_address_t dst, + uvm_gpu_address_t src, + NvU32 size, + uvm_gpu_address_t auth_tag); +void uvm_hal_hopper_ce_decrypt(uvm_push_t *push, + uvm_gpu_address_t dst, + uvm_gpu_address_t src, + NvU32 size, + uvm_gpu_address_t auth_tag); + // Increments the semaphore by 1, or resets to 0 if the incremented value would // exceed the payload. // @@ -342,6 +431,7 @@ typedef void (*uvm_hal_semaphore_reduction_inc_t)(uvm_push_t *push, NvU64 gpu_va, NvU32 payload); void uvm_hal_maxwell_ce_semaphore_reduction_inc(uvm_push_t *push, NvU64 gpu_va, NvU32 payload); void uvm_hal_pascal_ce_semaphore_reduction_inc(uvm_push_t *push, NvU64 gpu_va, NvU32 payload); +void uvm_hal_volta_ce_semaphore_reduction_inc(uvm_push_t *push, NvU64 gpu_va, NvU32 payload); void uvm_hal_hopper_ce_semaphore_reduction_inc(uvm_push_t *push, NvU64 gpu_va, NvU32 payload); // Initialize GPU architecture dependent properties @@ -395,15 +485,29 @@ typedef void (*uvm_hal_fault_buffer_write_get_t)(uvm_parent_gpu_t *parent_gpu, NvU32 get); typedef NvU8 (*uvm_hal_fault_buffer_get_ve_id_t)(NvU16 mmu_engine_id, uvm_mmu_engine_type_t mmu_engine_type); -// Parse the entry on the given buffer index. This also clears the valid bit of -// the entry in the buffer. -typedef void (*uvm_hal_fault_buffer_parse_entry_t)(uvm_parent_gpu_t *gpu, - NvU32 index, - uvm_fault_buffer_entry_t *buffer_entry); +// Parse the replayable entry at the given buffer index. This also clears the +// valid bit of the entry in the buffer. +typedef NV_STATUS (*uvm_hal_fault_buffer_parse_replayable_entry_t)(uvm_parent_gpu_t *gpu, + NvU32 index, + uvm_fault_buffer_entry_t *buffer_entry); + +NV_STATUS uvm_hal_maxwell_fault_buffer_parse_replayable_entry_unsupported(uvm_parent_gpu_t *parent_gpu, + NvU32 index, + uvm_fault_buffer_entry_t *buffer_entry); + +NV_STATUS uvm_hal_pascal_fault_buffer_parse_replayable_entry(uvm_parent_gpu_t *parent_gpu, + NvU32 index, + uvm_fault_buffer_entry_t *buffer_entry); + +NV_STATUS uvm_hal_volta_fault_buffer_parse_replayable_entry(uvm_parent_gpu_t *parent_gpu, + NvU32 index, + uvm_fault_buffer_entry_t *buffer_entry); + typedef bool (*uvm_hal_fault_buffer_entry_is_valid_t)(uvm_parent_gpu_t *parent_gpu, NvU32 index); typedef void (*uvm_hal_fault_buffer_entry_clear_valid_t)(uvm_parent_gpu_t *parent_gpu, NvU32 index); typedef NvU32 (*uvm_hal_fault_buffer_entry_size_t)(uvm_parent_gpu_t *parent_gpu); typedef void (*uvm_hal_fault_buffer_replay_t)(uvm_push_t *push, uvm_fault_replay_type_t type); +typedef uvm_fault_type_t (*uvm_hal_fault_buffer_get_fault_type_t)(const NvU32 *fault_entry); typedef void (*uvm_hal_fault_cancel_global_t)(uvm_push_t *push, uvm_gpu_phys_address_t instance_ptr); typedef void (*uvm_hal_fault_cancel_targeted_t)(uvm_push_t *push, uvm_gpu_phys_address_t instance_ptr, @@ -417,25 +521,24 @@ NvU32 uvm_hal_maxwell_fault_buffer_read_get_unsupported(uvm_parent_gpu_t *parent_gpu); void uvm_hal_maxwell_fault_buffer_write_get_unsupported(uvm_parent_gpu_t *parent_gpu, NvU32 index); NvU8 uvm_hal_maxwell_fault_buffer_get_ve_id_unsupported(NvU16 mmu_engine_id, uvm_mmu_engine_type_t mmu_engine_type); -void uvm_hal_maxwell_fault_buffer_parse_entry_unsupported(uvm_parent_gpu_t *parent_gpu, - NvU32 index, - uvm_fault_buffer_entry_t *buffer_entry); +uvm_fault_type_t uvm_hal_maxwell_fault_buffer_get_fault_type_unsupported(const NvU32 *fault_entry); + void uvm_hal_pascal_enable_replayable_faults(uvm_parent_gpu_t *parent_gpu); void uvm_hal_pascal_disable_replayable_faults(uvm_parent_gpu_t *parent_gpu); void uvm_hal_pascal_clear_replayable_faults(uvm_parent_gpu_t *parent_gpu, NvU32 get); NvU32 uvm_hal_pascal_fault_buffer_read_put(uvm_parent_gpu_t *parent_gpu); NvU32 uvm_hal_pascal_fault_buffer_read_get(uvm_parent_gpu_t *parent_gpu); void uvm_hal_pascal_fault_buffer_write_get(uvm_parent_gpu_t *parent_gpu, NvU32 index); -void uvm_hal_pascal_fault_buffer_parse_entry(uvm_parent_gpu_t *parent_gpu, - NvU32 index, - uvm_fault_buffer_entry_t *buffer_entry); + +uvm_fault_type_t uvm_hal_pascal_fault_buffer_get_fault_type(const NvU32 *fault_entry); + NvU32 uvm_hal_volta_fault_buffer_read_put(uvm_parent_gpu_t *parent_gpu); NvU32 uvm_hal_volta_fault_buffer_read_get(uvm_parent_gpu_t *parent_gpu); void uvm_hal_volta_fault_buffer_write_get(uvm_parent_gpu_t *parent_gpu, NvU32 index); NvU8 uvm_hal_volta_fault_buffer_get_ve_id(NvU16 mmu_engine_id, uvm_mmu_engine_type_t mmu_engine_type); -void uvm_hal_volta_fault_buffer_parse_entry(uvm_parent_gpu_t *parent_gpu, - NvU32 index, - uvm_fault_buffer_entry_t *buffer_entry); + +uvm_fault_type_t uvm_hal_volta_fault_buffer_get_fault_type(const NvU32 *fault_entry); + void uvm_hal_turing_disable_replayable_faults(uvm_parent_gpu_t *parent_gpu); void uvm_hal_turing_clear_replayable_faults(uvm_parent_gpu_t *parent_gpu, NvU32 get); NvU8 uvm_hal_hopper_fault_buffer_get_ve_id(NvU16 mmu_engine_id, uvm_mmu_engine_type_t mmu_engine_type); @@ -576,11 +679,33 @@ void uvm_hal_turing_disable_access_counter_notifications(uvm_parent_gpu_t *parent_gpu); void uvm_hal_turing_clear_access_counter_notifications(uvm_parent_gpu_t *parent_gpu, NvU32 get); +// The source and destination addresses must be 16-byte aligned. Note that the +// best performance is achieved with 256-byte alignment. The decrypt size must +// be larger than 0, and a multiple of 4 bytes. +// +// The authentication tag address must also be 16-byte aligned. +// The authentication tag buffer size is UVM_CONF_COMPUTING_AUTH_TAG_SIZE bytes +// defined in uvm_conf_computing.h. +// +// Decrypts the src buffer into the dst buffer of the given size. +// The method also verifies integrity of the src buffer by calculating its +// authentication tag and comparing it with the provided one. +// +// Note: SEC2 does not support encryption. +typedef void (*uvm_hal_sec2_decrypt_t)(uvm_push_t *push, NvU64 dst_va, NvU64 src_va, NvU32 size, NvU64 auth_tag_va); + +void uvm_hal_maxwell_sec2_decrypt_unsupported(uvm_push_t *push, + NvU64 dst_va, + NvU64 src_va, + NvU32 size, + NvU64 auth_tag_va); +void uvm_hal_hopper_sec2_decrypt(uvm_push_t *push, NvU64 dst_va, NvU64 src_va, NvU32 size, NvU64 auth_tag_va); + struct uvm_host_hal_struct { uvm_hal_init_t init; - uvm_hal_host_method_validate method_validate; - uvm_hal_host_sw_method_validate sw_method_validate; + uvm_hal_host_method_is_valid method_is_valid; + uvm_hal_host_sw_method_is_valid sw_method_is_valid; uvm_hal_wait_for_idle_t wait_for_idle; uvm_hal_membar_sys_t membar_sys; uvm_hal_membar_gpu_t membar_gpu; @@ -612,23 +737,26 @@ struct uvm_ce_hal_struct { uvm_hal_init_t init; - uvm_hal_ce_method_validate method_validate; + uvm_hal_ce_method_is_valid method_is_valid; uvm_hal_semaphore_release_t semaphore_release; uvm_hal_semaphore_timestamp_t semaphore_timestamp; uvm_hal_ce_offset_out_t offset_out; uvm_hal_ce_offset_in_out_t offset_in_out; uvm_hal_ce_phys_mode_t phys_mode; uvm_hal_ce_plc_mode_t plc_mode; - uvm_hal_ce_memcopy_validate memcopy_validate; + uvm_hal_ce_memcopy_type_t memcopy_copy_type; + uvm_hal_ce_memcopy_is_valid memcopy_is_valid; uvm_hal_ce_memcopy_patch_src memcopy_patch_src; uvm_hal_memcopy_t memcopy; uvm_hal_memcopy_v_to_v_t memcopy_v_to_v; - uvm_hal_ce_memset_validate memset_validate; + uvm_hal_ce_memset_is_valid memset_is_valid; uvm_hal_memset_1_t memset_1; uvm_hal_memset_4_t memset_4; uvm_hal_memset_8_t memset_8; uvm_hal_memset_v_4_t memset_v_4; uvm_hal_semaphore_reduction_inc_t semaphore_reduction_inc; + uvm_hal_ce_encrypt_t encrypt; + uvm_hal_ce_decrypt_t decrypt; }; struct uvm_arch_hal_struct @@ -650,11 +778,12 @@ uvm_hal_fault_buffer_read_get_t read_get; uvm_hal_fault_buffer_write_get_t write_get; uvm_hal_fault_buffer_get_ve_id_t get_ve_id; - uvm_hal_fault_buffer_parse_entry_t parse_entry; + uvm_hal_fault_buffer_parse_replayable_entry_t parse_replayable_entry; uvm_hal_fault_buffer_entry_is_valid_t entry_is_valid; uvm_hal_fault_buffer_entry_clear_valid_t entry_clear_valid; uvm_hal_fault_buffer_entry_size_t entry_size; uvm_hal_fault_buffer_parse_non_replayable_entry_t parse_non_replayable_entry; + uvm_hal_fault_buffer_get_fault_type_t get_fault_type; }; struct uvm_access_counter_buffer_hal_struct @@ -668,6 +797,14 @@ uvm_hal_access_counter_buffer_entry_size_t entry_size; }; +struct uvm_sec2_hal_struct +{ + uvm_hal_init_t init; + uvm_hal_sec2_decrypt_t decrypt; + uvm_hal_semaphore_release_t semaphore_release; + uvm_hal_semaphore_timestamp_t semaphore_timestamp; +}; + typedef struct { // id is either a hardware class or GPU architecture @@ -690,6 +827,8 @@ // access_counter_buffer_ops: id is an architecture uvm_access_counter_buffer_hal_t access_counter_buffer_ops; + // sec2_ops: id is an architecture + uvm_sec2_hal_t sec2_ops; } u; } uvm_hal_class_ops_t; @@ -726,4 +865,20 @@ // appropriate Host membar(s) after a TLB invalidate. void uvm_hal_tlb_invalidate_membar(uvm_push_t *push, uvm_membar_t membar); +// Internal helper used by architectures/engines that don't support a FLUSH +// operation with a FLUSH_TYPE on the semaphore release method, e.g., pre-Volta +// CE. It inspects and clears the MEMBAR push flags, issues a Host WFI + +// membar.gpu for MEMBAR_GPU or returns true to indicate the caller to use the +// engine's FLUSH for MEMBAR_SYS. +bool uvm_hal_membar_before_semaphore(uvm_push_t *push); + +// Determine the appropriate membar to use on TLB invalidates for GPU PTE +// permissions downgrades. +// +// gpu is the GPU on which the TLB invalidate is happening. +// +// is_local_vidmem indicates whether all mappings being invalidated pointed to +// the local GPU's memory. +uvm_membar_t uvm_hal_downgrade_membar_type(uvm_gpu_t *gpu, bool is_local_vidmem); + #endif // __UVM_HAL_H__ diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/kernel-open/nvidia-uvm/uvm_hal_types.h nvidia-open-gpu-kernel-modules-535.161.08/kernel-open/nvidia-uvm/uvm_hal_types.h --- nvidia-open-gpu-kernel-modules-525.147.05/kernel-open/nvidia-uvm/uvm_hal_types.h 2023-10-25 20:33:34.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/kernel-open/nvidia-uvm/uvm_hal_types.h 2024-03-05 22:25:51.000000000 +0000 @@ -1,5 +1,5 @@ /******************************************************************************* - Copyright (c) 2016-2019 NVIDIA Corporation + Copyright (c) 2016-2023 NVIDIA Corporation Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation files (the "Software"), to @@ -111,6 +111,11 @@ // Whether the address is virtual bool is_virtual; + + // Whether the address resides in a non-protected memory region when the + // Confidential Computing feature is enabled. Default is protected. + // Ignored if the feature is disabled and should not be used. + bool is_unprotected; } uvm_gpu_address_t; // Create a virtual GPU address @@ -123,6 +128,13 @@ return address; } +static uvm_gpu_address_t uvm_gpu_address_virtual_unprotected(NvU64 va) +{ + uvm_gpu_address_t address = uvm_gpu_address_virtual(va); + address.is_unprotected = true; + return address; +} + // Create a physical GPU address static uvm_gpu_address_t uvm_gpu_address_physical(uvm_aperture_t aperture, NvU64 pa) { @@ -258,8 +270,8 @@ UVM_FAULT_CANCEL_VA_MODE_COUNT, } uvm_fault_cancel_va_mode_t; -// Types of faults that can show up in the fault buffer. Non-UVM related faults are grouped in FATAL category -// since we don't care about the specific type +// Types of faults that can show up in the fault buffer. Non-UVM related faults +// are grouped in FATAL category since we don't care about the specific type. typedef enum { UVM_FAULT_TYPE_INVALID_PDE = 0, @@ -272,7 +284,8 @@ // READ to WRITE-ONLY (ATS) UVM_FAULT_TYPE_READ, - // The next values are considered fatal and are not handled by the UVM driver + // The next values are considered fatal and are not handled by the UVM + // driver UVM_FAULT_TYPE_FATAL, // Values required for tools @@ -311,10 +324,24 @@ UVM_MMU_ENGINE_TYPE_COUNT, } uvm_mmu_engine_type_t; +typedef enum +{ + // Allow entry to be fetched before the previous entry finishes ESCHED + // execution. + UVM_GPFIFO_SYNC_PROCEED = 0, + + // Fetch of this entry has to wait until the previous entry has finished + // executing by ESCHED. + // For a complete engine sync the previous entry needs to include + // WAIT_FOR_IDLE command or other engine synchronization. + UVM_GPFIFO_SYNC_WAIT, +} uvm_gpfifo_sync_t; + const char *uvm_mmu_engine_type_string(uvm_mmu_engine_type_t mmu_engine_type); -// HW unit that triggered the fault. We include the fields required for fault cancelling. Including more information -// might be useful for performance heuristics in the future +// HW unit that triggered the fault. We include the fields required for fault +// cancelling. Including more information might be useful for performance +// heuristics in the future. typedef struct { uvm_fault_client_type_t client_type : order_base_2(UVM_FAULT_CLIENT_TYPE_COUNT) + 1; @@ -429,7 +456,8 @@ // Completes when all fault replays are in-flight UVM_FAULT_REPLAY_TYPE_START = 0, - // Completes when all faulting accesses have been correctly translated or faulted again + // Completes when all faulting accesses have been correctly translated or + // faulted again UVM_FAULT_REPLAY_TYPE_START_ACK_ALL, UVM_FAULT_REPLAY_TYPE_MAX @@ -467,18 +495,18 @@ { struct { - // Instance pointer of one of the channels in the TSG that triggered the - // notification + // Instance pointer of one of the channels in the TSG that triggered + // the notification. uvm_gpu_phys_address_t instance_ptr; uvm_mmu_engine_type_t mmu_engine_type; NvU32 mmu_engine_id; - // Identifier of the subcontext that performed the memory accesses that - // triggered the notification. This value, combined with the instance_ptr, - // is needed to obtain the GPU VA space of the process that triggered the - // notification. + // Identifier of the subcontext that performed the memory accesses + // that triggered the notification. This value, combined with the + // instance_ptr, is needed to obtain the GPU VA space of the process + // that triggered the notification. NvU32 ve_id; // VA space for the address that triggered the notification @@ -524,8 +552,8 @@ return UVM_PROT_READ_WRITE; default: - // Prefetch faults, if not ignored, are handled like read faults and require - // a mapping with, at least, READ_ONLY access permission + // Prefetch faults, if not ignored, are handled like read faults and + // requirea mapping with, at least, READ_ONLY access permission. return UVM_PROT_READ_ONLY; } } diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/kernel-open/nvidia-uvm/uvm_hmm.c nvidia-open-gpu-kernel-modules-535.161.08/kernel-open/nvidia-uvm/uvm_hmm.c --- nvidia-open-gpu-kernel-modules-525.147.05/kernel-open/nvidia-uvm/uvm_hmm.c 2023-10-25 20:33:41.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/kernel-open/nvidia-uvm/uvm_hmm.c 2024-03-05 22:26:04.000000000 +0000 @@ -1,5 +1,5 @@ /******************************************************************************* - Copyright (c) 2016-2022 NVIDIA Corporation + Copyright (c) 2016-2023 NVIDIA Corporation Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation files (the "Software"), to @@ -23,43 +23,114 @@ #include "uvm_hmm.h" +// Support for HMM ( https://docs.kernel.org/mm/hmm.html ): + +#ifdef NVCPU_X86_64 static bool uvm_disable_hmm = false; -module_param(uvm_disable_hmm, bool, 0444); MODULE_PARM_DESC(uvm_disable_hmm, "Force-disable HMM functionality in the UVM driver. " - "Default: false (i.e, HMM is potentially enabled). Ignored if " - "HMM is not supported in the driver, or if ATS settings " - "conflict with HMM."); + "Default: false (HMM is enabled if possible). " + "However, even with uvm_disable_hmm=false, HMM will not be " + "enabled if is not supported in this driver build " + "configuration, or if ATS settings conflict with HMM."); +#else +// So far, we've only tested HMM on x86_64, so disable it by default everywhere +// else. +static bool uvm_disable_hmm = true; +MODULE_PARM_DESC(uvm_disable_hmm, + "Force-disable HMM functionality in the UVM driver. " + "Default: true (HMM is not enabled on this CPU architecture). " + "However, even with uvm_disable_hmm=false, HMM will not be " + "enabled if is not supported in this driver build " + "configuration, or if ATS settings conflict with HMM."); +#endif + +module_param(uvm_disable_hmm, bool, 0444); #if UVM_IS_CONFIG_HMM() #include +#include +#include #include +#include +#include #include "uvm_common.h" #include "uvm_gpu.h" +#include "uvm_pmm_gpu.h" +#include "uvm_hal_types.h" #include "uvm_va_block_types.h" #include "uvm_va_space_mm.h" #include "uvm_va_space.h" #include "uvm_va_range.h" #include "uvm_range_tree.h" +#include "uvm_pmm_sysmem.h" #include "uvm_lock.h" #include "uvm_api.h" #include "uvm_va_policy.h" #include "uvm_tools.h" +static NV_STATUS gpu_chunk_add(uvm_va_block_t *va_block, + uvm_page_index_t page_index, + struct page *page); + +typedef struct +{ + uvm_processor_id_t processor_id; + uvm_processor_id_t new_residency; + uvm_va_block_t *va_block; + uvm_va_block_retry_t *va_block_retry; + uvm_service_block_context_t *service_context; + uvm_page_mask_t page_mask; + uvm_page_mask_t same_devmem_page_mask; +} uvm_hmm_gpu_fault_event_t; + +typedef struct +{ + uvm_va_block_t *va_block; + uvm_va_block_retry_t *va_block_retry; + uvm_va_block_context_t *va_block_context; + uvm_va_block_region_t region; + uvm_processor_id_t dest_id; + uvm_make_resident_cause_t cause; + uvm_page_mask_t page_mask; + uvm_page_mask_t same_devmem_page_mask; +} uvm_hmm_migrate_event_t; + +typedef struct +{ + uvm_processor_id_t processor_id; + uvm_va_block_t *va_block; + uvm_va_block_retry_t *va_block_retry; + uvm_service_block_context_t *service_context; + uvm_page_mask_t page_mask; + uvm_page_mask_t same_devmem_page_mask; +} uvm_hmm_devmem_fault_context_t; + bool uvm_hmm_is_enabled_system_wide(void) { - return !uvm_disable_hmm && !g_uvm_global.ats.enabled && uvm_va_space_mm_enabled_system(); + if (uvm_disable_hmm) + return false; + + if (g_uvm_global.ats.enabled) + return false; + + // Confidential Computing and HMM impose mutually exclusive constraints. In + // Confidential Computing the GPU can only access pages resident in vidmem, + // but in HMM pages may be required to be resident in sysmem: file backed + // VMAs, huge pages, etc. + if (g_uvm_global.conf_computing_enabled) + return false; + + return uvm_va_space_mm_enabled_system(); } bool uvm_hmm_is_enabled(uvm_va_space_t *va_space) { - // TODO: Bug 3351822: [UVM-HMM] Remove temporary testing changes. return uvm_hmm_is_enabled_system_wide() && uvm_va_space_mm_enabled(va_space) && - !(va_space->initialization_flags & UVM_INIT_FLAGS_DISABLE_HMM) && - !va_space->hmm.disable; + !(va_space->initialization_flags & UVM_INIT_FLAGS_DISABLE_HMM); } static uvm_va_block_t *hmm_va_block_from_node(uvm_range_tree_node_t *node) @@ -69,88 +140,130 @@ return container_of(node, uvm_va_block_t, hmm.node); } -NV_STATUS uvm_hmm_va_space_initialize(uvm_va_space_t *va_space) +void uvm_hmm_va_space_initialize(uvm_va_space_t *va_space) { - struct mm_struct *mm = va_space->va_space_mm.mm; + uvm_hmm_va_space_t *hmm_va_space = &va_space->hmm; if (!uvm_hmm_is_enabled(va_space)) - return NV_OK; - - uvm_assert_mmap_lock_locked_write(mm); - uvm_assert_rwsem_locked_write(&va_space->lock); + return; - // TODO: Bug 3351822: [UVM-HMM] Remove temporary testing changes. - // Disable HMM by default for each va_space until enough functionality is - // implemented that this can be enabled by default. - // Note that it can be enabled for testing under controlled circumstances. - va_space->hmm.disable = true; + uvm_range_tree_init(&hmm_va_space->blocks); + uvm_mutex_init(&hmm_va_space->blocks_lock, UVM_LOCK_ORDER_LEAF); - return NV_OK; + return; } -NV_STATUS uvm_hmm_va_space_initialize_test(uvm_va_space_t *va_space) +void uvm_hmm_va_space_destroy(uvm_va_space_t *va_space) { uvm_hmm_va_space_t *hmm_va_space = &va_space->hmm; - struct mm_struct *mm = va_space->va_space_mm.mm; - int ret; + uvm_range_tree_node_t *node, *next; + uvm_va_block_t *va_block; + + if (!uvm_hmm_is_enabled(va_space)) + return; + + uvm_assert_rwsem_locked_write(&va_space->lock); - if (!uvm_hmm_is_enabled_system_wide() || !mm) - return NV_WARN_NOTHING_TO_DO; + // The blocks_lock is not needed when the va_space lock is held for write. + uvm_range_tree_for_each_safe(node, next, &hmm_va_space->blocks) { + va_block = hmm_va_block_from_node(node); + uvm_range_tree_remove(&hmm_va_space->blocks, node); + mmu_interval_notifier_remove(&va_block->hmm.notifier); + uvm_va_block_kill(va_block); + } +} + +static void hmm_va_block_unregister_gpu(uvm_va_block_t *va_block, + uvm_gpu_t *gpu, + struct mm_struct *mm) +{ + uvm_va_policy_node_t *node; + + uvm_mutex_lock(&va_block->lock); - if (va_space->initialization_flags & UVM_INIT_FLAGS_DISABLE_HMM) - return NV_ERR_INVALID_STATE; + // Reset preferred location and accessed-by of policy nodes if needed. + uvm_for_each_va_policy_node_in(node, va_block, va_block->start, va_block->end) { + if (uvm_id_equal(node->policy.preferred_location, gpu->id)) + node->policy.preferred_location = UVM_ID_INVALID; - uvm_assert_mmap_lock_locked_write(mm); + uvm_processor_mask_clear(&node->policy.accessed_by, gpu->id); + } + + // Migrate and free any remaining resident allocations on this GPU. + uvm_va_block_unregister_gpu_locked(va_block, gpu, mm); + + uvm_mutex_unlock(&va_block->lock); +} + +void uvm_hmm_unregister_gpu(uvm_va_space_t *va_space, uvm_gpu_t *gpu, struct mm_struct *mm) +{ + uvm_range_tree_node_t *node; + uvm_va_block_t *va_block; + + if (!uvm_hmm_is_enabled(va_space)) + return; + + if (mm) + uvm_assert_mmap_lock_locked(mm); uvm_assert_rwsem_locked_write(&va_space->lock); - // Temporarily enable HMM for testing. - va_space->hmm.disable = false; + uvm_range_tree_for_each(node, &va_space->hmm.blocks) { + va_block = hmm_va_block_from_node(node); - // Initialize MMU interval notifiers for this process. - // This allows mmu_interval_notifier_insert() to be called without holding - // the mmap_lock for write. - // Note: there is no __mmu_notifier_unregister(), this call just allocates - // memory which is attached to the mm_struct and freed when the mm_struct - // is freed. - ret = __mmu_notifier_register(NULL, mm); - if (ret) - return errno_to_nv_status(ret); + hmm_va_block_unregister_gpu(va_block, gpu, mm); + } +} - uvm_range_tree_init(&hmm_va_space->blocks); - uvm_mutex_init(&hmm_va_space->blocks_lock, UVM_LOCK_ORDER_LEAF); +static void hmm_va_block_remove_gpu_va_space(uvm_va_block_t *va_block, + uvm_gpu_va_space_t *gpu_va_space, + uvm_va_block_context_t *va_block_context) +{ + uvm_mutex_lock(&va_block->lock); - return NV_OK; + uvm_va_block_remove_gpu_va_space(va_block, gpu_va_space, va_block_context); + + uvm_mutex_unlock(&va_block->lock); + + // TODO: Bug 3660922: Need to handle read duplication at some point. + // See range_remove_gpu_va_space_managed(). } -void uvm_hmm_va_space_destroy(uvm_va_space_t *va_space) +void uvm_hmm_remove_gpu_va_space(uvm_va_space_t *va_space, + uvm_gpu_va_space_t *gpu_va_space, + struct mm_struct *mm) { - uvm_hmm_va_space_t *hmm_va_space = &va_space->hmm; + uvm_va_block_context_t *va_block_context; uvm_range_tree_node_t *node, *next; uvm_va_block_t *va_block; - if (!uvm_hmm_is_enabled(va_space) || uvm_va_space_initialized(va_space) != NV_OK) + if (!uvm_hmm_is_enabled(va_space)) return; + if (mm) + uvm_assert_mmap_lock_locked(mm); uvm_assert_rwsem_locked_write(&va_space->lock); - // The blocks_lock is not needed when the va_space lock is held for write. - uvm_range_tree_for_each_safe(node, next, &hmm_va_space->blocks) { + va_block_context = uvm_va_space_block_context(va_space, mm); + + uvm_range_tree_for_each_safe(node, next, &va_space->hmm.blocks) { va_block = hmm_va_block_from_node(node); - uvm_range_tree_remove(&hmm_va_space->blocks, node); - mmu_interval_notifier_remove(&va_block->hmm.notifier); - uvm_va_block_kill(va_block); - } - // TODO: Bug 3351822: [UVM-HMM] Remove temporary testing changes. - va_space->hmm.disable = true; + hmm_va_block_remove_gpu_va_space(va_block, gpu_va_space, va_block_context); + } } static bool hmm_invalidate(uvm_va_block_t *va_block, const struct mmu_notifier_range *range, unsigned long cur_seq) { + uvm_thread_context_t *uvm_context = uvm_thread_context(); struct mmu_interval_notifier *mni = &va_block->hmm.notifier; + struct mm_struct *mm = mni->mm; + uvm_va_block_context_t *va_block_context; + uvm_va_block_region_t region; NvU64 start, end; + uvm_processor_id_t id; + NV_STATUS status = NV_OK; // The MMU_NOTIFY_RELEASE event isn't really needed since mn_itree_release() // doesn't remove the interval notifiers from the struct_mm so there will @@ -165,22 +278,25 @@ if (!mmu_notifier_range_blockable(range)) return false; - // Ignore invalidation callbacks for device private pages since the - // invalidation is handled as part of the migration process. - // Note that the va_space pointer won't be NULL if the callback is for - // MMU_NOTIFY_MIGRATE/MMU_NOTIFY_EXCLUSIVE because the va_block lock - // is already held and we have to prevent recursively getting the lock. - if ((range->event == MMU_NOTIFY_MIGRATE || range->event == MMU_NOTIFY_EXCLUSIVE) && - range->owner == va_block->hmm.va_space) + // We only ignore invalidations in this context whilst holding the + // va_block lock. This prevents deadlock when try_to_migrate() + // calls the notifier, but holding the lock prevents other threads + // invalidating PTEs so we can safely assume the results of + // migrate_vma_setup() are correct. + if (uvm_context->ignore_hmm_invalidate_va_block == va_block || + ((range->event == MMU_NOTIFY_MIGRATE || range->event == MMU_NOTIFY_EXCLUSIVE) && + range->owner == &g_uvm_global)) return true; - uvm_mutex_lock(&va_block->lock); + va_block_context = uvm_va_block_context_alloc(mm); + if (!va_block_context) + return true; - // Ignore this invalidation callback if the block is dead. - if (uvm_va_block_is_dead(va_block)) - goto unlock; + uvm_mutex_lock(&va_block->lock); - mmu_interval_set_seq(mni, cur_seq); + // mmu_interval_notifier_remove() is always called before marking a + // va_block as dead so this va_block has to be alive. + UVM_ASSERT(!uvm_va_block_is_dead(va_block)); // Note: unmap_vmas() does MMU_NOTIFY_UNMAP [0, 0xffffffffffffffff] // Also note that hmm_invalidate() can be called when a new va_block is not @@ -197,12 +313,46 @@ if (start > end) goto unlock; - if (range->event == MMU_NOTIFY_UNMAP) - uvm_va_policy_clear(va_block, start, end); + // These will be equal if no other thread causes an invalidation + // whilst the va_block lock was dropped. + uvm_context->hmm_invalidate_seqnum++; + va_block->hmm.changed++; + + mmu_interval_set_seq(mni, cur_seq); + + region = uvm_va_block_region_from_start_end(va_block, start, end); + + va_block_context->hmm.vma = NULL; + + // We only need to unmap GPUs since Linux handles the CPUs. + for_each_gpu_id_in_mask(id, &va_block->mapped) { + status = uvm_va_block_unmap(va_block, + va_block_context, + id, + region, + uvm_va_block_map_mask_get(va_block, id), + &va_block->tracker); + // Note that the va_block lock can be dropped, relocked, and + // NV_ERR_MORE_PROCESSING_REQUIRED returned. + if (status != NV_OK) + break; + } + + if (range->event == MMU_NOTIFY_UNMAP || range->event == MMU_NOTIFY_CLEAR) + uvm_va_block_munmap_region(va_block, region); + + if (status == NV_OK) + status = uvm_tracker_wait(&va_block->tracker); + + // Remove stale HMM struct page pointers to system memory. + uvm_va_block_remove_cpu_chunks(va_block, region); unlock: uvm_mutex_unlock(&va_block->lock); + uvm_va_block_context_free(va_block_context); + + UVM_ASSERT(status == NV_OK); return true; } @@ -229,7 +379,6 @@ if (!uvm_hmm_is_enabled(va_space)) return NV_ERR_INVALID_ADDRESS; - UVM_ASSERT(uvm_va_space_initialized(va_space) == NV_OK); uvm_assert_rwsem_locked(&va_space->lock); uvm_mutex_lock(&va_space->hmm.blocks_lock); @@ -244,29 +393,59 @@ return NV_OK; } +static int migrate_vma_setup_locked(struct migrate_vma *args, uvm_va_block_t *va_block) +{ + uvm_thread_context_t *uvm_context = uvm_thread_context(); + int ret; + + // It's only safe to ignore invalidations whilst doing a migration + // and holding the va_block lock. + uvm_assert_mutex_locked(&va_block->lock); + uvm_context->ignore_hmm_invalidate_va_block = va_block; + ret = migrate_vma_setup(args); + + // We shouldn't be generating any more invalidations now. + uvm_context->ignore_hmm_invalidate_va_block = NULL; + return ret; +} + static bool uvm_hmm_vma_is_valid(struct vm_area_struct *vma, unsigned long addr, bool allow_unreadable_vma) { // UVM doesn't support userfaultfd. hmm_range_fault() doesn't support - // VM_IO, VM_PFNMAP, or VM_MIXEDMAP VMAs. It also doesn't support - // VMAs without VM_READ but we allow those VMAs to have policy set on - // them. + // VM_IO or VM_PFNMAP VMAs. It also doesn't support VMAs without VM_READ + // but we allow those VMAs to have policy set on them. + // migrate_vma_setup() doesn't support VM_SPECIAL VMAs but that is handled + // by uvm_hmm_must_use_sysmem() forcing residency to the CPU. return vma && addr >= vma->vm_start && !userfaultfd_armed(vma) && - !(vma->vm_flags & (VM_IO | VM_PFNMAP | VM_MIXEDMAP)) && + !(vma->vm_flags & (VM_IO | VM_PFNMAP)) && + !uvm_vma_is_managed(vma) && (allow_unreadable_vma || (vma->vm_flags & VM_READ)); } +static void hmm_va_block_init(uvm_va_block_t *va_block, + uvm_va_space_t *va_space, + NvU64 start, + NvU64 end) +{ + va_block->hmm.va_space = va_space; + va_block->hmm.node.start = start; + va_block->hmm.node.end = end; + uvm_range_tree_init(&va_block->hmm.va_policy_tree); + uvm_mutex_init(&va_block->hmm.migrate_lock, UVM_LOCK_ORDER_VA_BLOCK_MIGRATE); +} + static NV_STATUS hmm_va_block_find_create(uvm_va_space_t *va_space, NvU64 addr, bool allow_unreadable_vma, - uvm_va_block_context_t *va_block_context, + struct vm_area_struct **vma_out, uvm_va_block_t **va_block_ptr) { - struct mm_struct *mm = va_space->va_space_mm.mm; - struct vm_area_struct *vma; + struct mm_struct *mm; + struct vm_area_struct *va_block_vma; uvm_va_block_t *va_block; NvU64 start, end; NV_STATUS status; @@ -275,16 +454,14 @@ if (!uvm_hmm_is_enabled(va_space)) return NV_ERR_INVALID_ADDRESS; - UVM_ASSERT(uvm_va_space_initialized(va_space) == NV_OK); - UVM_ASSERT(mm); - UVM_ASSERT(!va_block_context || va_block_context->mm == mm); + mm = va_space->va_space_mm.mm; uvm_assert_mmap_lock_locked(mm); uvm_assert_rwsem_locked(&va_space->lock); UVM_ASSERT(PAGE_ALIGNED(addr)); // Note that we have to allow PROT_NONE VMAs so that policies can be set. - vma = find_vma(mm, addr); - if (!uvm_hmm_vma_is_valid(vma, addr, allow_unreadable_vma)) + va_block_vma = find_vma(mm, addr); + if (!uvm_hmm_vma_is_valid(va_block_vma, addr, allow_unreadable_vma)) return NV_ERR_INVALID_ADDRESS; // Since we only hold the va_space read lock, there can be multiple @@ -319,10 +496,7 @@ if (status != NV_OK) goto err_unlock; - va_block->hmm.node.start = start; - va_block->hmm.node.end = end; - va_block->hmm.va_space = va_space; - uvm_range_tree_init(&va_block->hmm.va_policy_tree); + hmm_va_block_init(va_block, va_space, start, end); ret = mmu_interval_notifier_insert(&va_block->hmm.notifier, mm, @@ -339,8 +513,8 @@ done: uvm_mutex_unlock(&va_space->hmm.blocks_lock); - if (va_block_context) - va_block_context->hmm.vma = vma; + if (vma_out) + *vma_out = va_block_vma; *va_block_ptr = va_block; return NV_OK; @@ -354,43 +528,36 @@ NV_STATUS uvm_hmm_va_block_find_create(uvm_va_space_t *va_space, NvU64 addr, - uvm_va_block_context_t *va_block_context, + struct vm_area_struct **vma, uvm_va_block_t **va_block_ptr) { - return hmm_va_block_find_create(va_space, addr, false, va_block_context, va_block_ptr); + return hmm_va_block_find_create(va_space, addr, false, vma, va_block_ptr); } -NV_STATUS uvm_hmm_find_vma(uvm_va_block_context_t *va_block_context, NvU64 addr) +NV_STATUS uvm_hmm_find_vma(struct mm_struct *mm, struct vm_area_struct **vma_out, NvU64 addr) { - struct mm_struct *mm = va_block_context->mm; - struct vm_area_struct *vma; - if (!mm) return NV_ERR_INVALID_ADDRESS; uvm_assert_mmap_lock_locked(mm); - vma = find_vma(mm, addr); - if (!uvm_hmm_vma_is_valid(vma, addr, false)) + *vma_out = find_vma(mm, addr); + if (!uvm_hmm_vma_is_valid(*vma_out, addr, false)) return NV_ERR_INVALID_ADDRESS; - va_block_context->hmm.vma = vma; - return NV_OK; } -bool uvm_hmm_va_block_context_vma_is_valid(uvm_va_block_t *va_block, - uvm_va_block_context_t *va_block_context, - uvm_va_block_region_t region) +bool uvm_hmm_check_context_vma_is_valid(uvm_va_block_t *va_block, + struct vm_area_struct *vma, + uvm_va_block_region_t region) { uvm_assert_mutex_locked(&va_block->lock); if (uvm_va_block_is_hmm(va_block)) { - struct vm_area_struct *vma = va_block_context->hmm.vma; - UVM_ASSERT(vma); - UVM_ASSERT(va_block_context->mm == vma->vm_mm); - uvm_assert_mmap_lock_locked(va_block_context->mm); + UVM_ASSERT(va_block->hmm.va_space->va_space_mm.mm == vma->vm_mm); + uvm_assert_mmap_lock_locked(va_block->hmm.va_space->va_space_mm.mm); UVM_ASSERT(vma->vm_start <= uvm_va_block_region_start(va_block, region)); UVM_ASSERT(vma->vm_end > uvm_va_block_region_end(va_block, region)); } @@ -398,6 +565,113 @@ return true; } +void uvm_hmm_service_context_init(uvm_service_block_context_t *service_context) +{ + // TODO: Bug 4050579: Remove this when swap cached pages can be migrated. + service_context->block_context.hmm.swap_cached = false; +} + +NV_STATUS uvm_hmm_migrate_begin(uvm_va_block_t *va_block) +{ + if (uvm_mutex_trylock(&va_block->hmm.migrate_lock)) + return NV_OK; + + return NV_ERR_BUSY_RETRY; +} + +void uvm_hmm_migrate_begin_wait(uvm_va_block_t *va_block) +{ + uvm_mutex_lock(&va_block->hmm.migrate_lock); +} + +void uvm_hmm_migrate_finish(uvm_va_block_t *va_block) +{ + uvm_mutex_unlock(&va_block->hmm.migrate_lock); +} + +// Migrate the given range [start end] within a va_block to dest_id. +static NV_STATUS hmm_migrate_range(uvm_va_block_t *va_block, + uvm_va_block_retry_t *va_block_retry, + uvm_va_block_context_t *va_block_context, + uvm_processor_id_t dest_id, + NvU64 start, + NvU64 end, + uvm_migrate_mode_t mode, + uvm_tracker_t *out_tracker) +{ + uvm_va_block_region_t region; + uvm_va_policy_node_t *node; + const uvm_va_policy_t *policy; + NV_STATUS status = NV_OK; + + uvm_hmm_migrate_begin_wait(va_block); + uvm_mutex_lock(&va_block->lock); + + uvm_for_each_va_policy_in(policy, va_block, start, end, node, region) { + // Even though UVM_VA_BLOCK_RETRY_LOCKED() may unlock and relock the + // va_block lock, the policy remains valid because we hold the mmap + // lock so munmap can't remove the policy, and the va_space lock so the + // policy APIs can't change the policy. + status = UVM_VA_BLOCK_RETRY_LOCKED(va_block, + va_block_retry, + uvm_va_block_migrate_locked(va_block, + va_block_retry, + va_block_context, + region, + dest_id, + mode, + out_tracker)); + if (status != NV_OK) + break; + } + + uvm_mutex_unlock(&va_block->lock); + uvm_hmm_migrate_finish(va_block); + + return status; +} + +void uvm_hmm_evict_va_blocks(uvm_va_space_t *va_space) +{ + // We can't use uvm_va_space_mm_retain(), because the va_space_mm + // should already be dead by now. + struct mm_struct *mm = va_space->va_space_mm.mm; + uvm_hmm_va_space_t *hmm_va_space = &va_space->hmm; + uvm_range_tree_node_t *node, *next; + uvm_va_block_t *va_block; + uvm_va_block_context_t *block_context; + + uvm_down_read_mmap_lock(mm); + uvm_va_space_down_write(va_space); + + uvm_range_tree_for_each_safe(node, next, &hmm_va_space->blocks) { + uvm_va_block_region_t region; + struct vm_area_struct *vma; + + va_block = hmm_va_block_from_node(node); + block_context = uvm_va_space_block_context(va_space, mm); + uvm_hmm_migrate_begin_wait(va_block); + uvm_mutex_lock(&va_block->lock); + for_each_va_block_vma_region(va_block, mm, vma, ®ion) { + if (!uvm_hmm_vma_is_valid(vma, vma->vm_start, false)) + continue; + + block_context->hmm.vma = vma; + uvm_hmm_va_block_migrate_locked(va_block, + NULL, + block_context, + UVM_ID_CPU, + region, + UVM_MAKE_RESIDENT_CAUSE_API_MIGRATE); + } + uvm_mutex_unlock(&va_block->lock); + uvm_hmm_migrate_finish(va_block); + } + + uvm_va_space_up_write(va_space); + uvm_up_read_mmap_lock(mm); +} + NV_STATUS uvm_hmm_test_va_block_inject_split_error(uvm_va_space_t *va_space, NvU64 addr) { uvm_va_block_test_t *block_test; @@ -480,10 +754,7 @@ return status; // Initialize the newly created HMM va_block. - new_va_block->hmm.node.start = new_va_block->start; - new_va_block->hmm.node.end = new_va_block->end; - new_va_block->hmm.va_space = va_space; - uvm_range_tree_init(&new_va_block->hmm.va_policy_tree); + hmm_va_block_init(new_va_block, va_space, new_va_block->start, new_va_block->end); ret = mmu_interval_notifier_insert(&new_va_block->hmm.notifier, mm, @@ -565,6 +836,12 @@ NvU64 end, uvm_va_block_t **out_va_block) { + uvm_va_block_context_t *va_block_context; + uvm_va_space_t *va_space; + struct mm_struct *mm; + struct vm_area_struct *vma; + uvm_va_block_region_t region; + NvU64 addr, from, to; uvm_va_block_t *new; NV_STATUS status; @@ -587,6 +864,40 @@ *out_va_block = va_block; + // Migrate any GPU data to sysmem before destroying the HMM va_block. + // We do this because the new va_range might be for a UVM external + // allocation which could be converting an address range that was first + // operated on by UVM-HMM and the exteral allocation should see that data. + va_space = va_block->hmm.va_space; + mm = va_space->va_space_mm.mm; + va_block_context = uvm_va_space_block_context(va_space, mm); + + for (addr = va_block->start; addr < va_block->end; addr = to + 1) { + vma = find_vma_intersection(mm, addr, va_block->end); + if (!vma) + break; + + from = max(addr, (NvU64)vma->vm_start); + to = min(va_block->end, (NvU64)vma->vm_end - 1); + region = uvm_va_block_region_from_start_end(va_block, from, to); + + if (!uvm_hmm_vma_is_valid(vma, from, false)) + continue; + + va_block_context->hmm.vma = vma; + + status = hmm_migrate_range(va_block, + NULL, + va_block_context, + UVM_ID_CPU, + from, + to, + UVM_MIGRATE_MODE_MAKE_RESIDENT_AND_MAP, + NULL); + if (status != NV_OK) + return status; + } + return NV_OK; } @@ -598,9 +909,9 @@ // the invalidate callback due to Linux locking constraints. If a process // calls mmap()/munmap() for SAM and then creates a managed allocation, // the same VMA range can be picked and there would be a UVM/HMM va_block -// conflict. Creating a managed allocation (or other va_range) calls this -// function to remove stale HMM va_blocks or split the HMM va_block so there -// is no overlap. +// conflict. Creating a managed allocation, external allocation, or other +// va_range types, calls this function to remove stale HMM va_blocks or split +// the HMM va_block so there is no overlap. NV_STATUS uvm_hmm_va_block_reclaim(uvm_va_space_t *va_space, struct mm_struct *mm, NvU64 start, @@ -613,10 +924,8 @@ if (!uvm_hmm_is_enabled(va_space)) return NV_OK; - if (mm) { - UVM_ASSERT(mm == va_space->va_space_mm.mm); + if (mm) uvm_assert_mmap_lock_locked(mm); - } uvm_assert_rwsem_locked_write(&va_space->lock); // Process each HMM va_block that overlaps the interval [start, end]. @@ -692,12 +1001,76 @@ return status; } +static NV_STATUS hmm_set_preferred_location_locked(uvm_va_block_t *va_block, + uvm_va_block_context_t *va_block_context, + uvm_processor_id_t preferred_location, + NvU64 addr, + NvU64 end, + uvm_tracker_t *out_tracker) +{ + uvm_processor_mask_t set_accessed_by_processors; + const uvm_va_policy_t *old_policy; + uvm_va_policy_node_t *node; + uvm_va_block_region_t region; + uvm_processor_id_t id; + NV_STATUS status, tracker_status; + + // Note that we can't just call uvm_va_policy_set_range() for the whole + // range [addr end] because we need to examine the old value of + // policy->preferred_location before setting it. Thus we iterate over + // the existing policy nodes. + uvm_for_each_va_policy_in(old_policy, va_block, addr, end, node, region) { + if (uvm_id_equal(old_policy->preferred_location, preferred_location)) + continue; + + // If the old preferred location is a valid processor ID, remote + // mappings should be established to the new preferred location if + // accessed-by is set. + uvm_processor_mask_zero(&set_accessed_by_processors); + + if (UVM_ID_IS_VALID(old_policy->preferred_location) && + uvm_processor_mask_test(&old_policy->accessed_by, old_policy->preferred_location)) + uvm_processor_mask_set(&set_accessed_by_processors, old_policy->preferred_location); + + if (!uvm_va_policy_set_preferred_location(va_block, region, preferred_location, old_policy)) + return NV_ERR_NO_MEMORY; + + // Establish new remote mappings if the old preferred location had + // accessed-by set. + for_each_id_in_mask(id, &set_accessed_by_processors) { + status = uvm_va_block_set_accessed_by_locked(va_block, va_block_context, id, region, out_tracker); + if (status != NV_OK) + return status; + } + + // Even though the UVM_VA_BLOCK_RETRY_LOCKED() may unlock and relock + // the va_block lock, the policy remains valid because we hold the mmap + // lock so munmap can't remove the policy, and the va_space lock so the + // policy APIs can't change the policy. + status = UVM_VA_BLOCK_RETRY_LOCKED(va_block, + NULL, + uvm_va_block_set_preferred_location_locked(va_block, + va_block_context, + region)); + + tracker_status = uvm_tracker_add_tracker_safe(out_tracker, &va_block->tracker); + if (status == NV_OK) + status = tracker_status; + + if (status != NV_OK) + return status; + } + + return NV_OK; +} + NV_STATUS uvm_hmm_set_preferred_location(uvm_va_space_t *va_space, uvm_processor_id_t preferred_location, NvU64 base, - NvU64 last_address) + NvU64 last_address, + uvm_tracker_t *out_tracker) { - bool is_default = UVM_ID_IS_INVALID(preferred_location); + uvm_va_block_context_t *va_block_context; uvm_va_block_t *va_block; NvU64 addr; NV_STATUS status = NV_OK; @@ -713,10 +1086,12 @@ // Update HMM preferred location policy. + va_block_context = uvm_va_space_block_context(va_space, va_space->va_space_mm.mm); + for (addr = base; addr < last_address; addr = va_block->end + 1) { NvU64 end; - status = hmm_va_block_find_create(va_space, addr, true, NULL, &va_block); + status = hmm_va_block_find_create(va_space, addr, true, &va_block_context->hmm.vma, &va_block); if (status != NV_OK) break; @@ -724,18 +1099,12 @@ uvm_mutex_lock(&va_block->lock); - status = uvm_va_policy_set_range(va_block, - addr, - end, - UVM_VA_POLICY_PREFERRED_LOCATION, - is_default, - preferred_location, - UVM_READ_DUPLICATION_MAX); - - // TODO: Bug 1750144: unset requires re-evaluating accessed-by mappings - // (see uvm_va_range_set_preferred_location's call of - // uvm_va_block_set_accessed_by), and set requires unmapping remote - // mappings (uvm_va_block_set_preferred_location_locked). + status = hmm_set_preferred_location_locked(va_block, + va_block_context, + preferred_location, + addr, + end, + out_tracker); uvm_mutex_unlock(&va_block->lock); @@ -746,12 +1115,48 @@ return status; } +static NV_STATUS hmm_set_accessed_by_start_end_locked(uvm_va_block_t *va_block, + uvm_va_block_context_t *va_block_context, + uvm_processor_id_t processor_id, + NvU64 start, + NvU64 end, + uvm_tracker_t *out_tracker) +{ + uvm_va_space_t *va_space = va_block->hmm.va_space; + uvm_va_policy_node_t *node; + uvm_va_block_region_t region; + NV_STATUS status = NV_OK; + + uvm_for_each_va_policy_node_in(node, va_block, start, end) { + // Read duplication takes precedence over SetAccessedBy. + // Do not add mappings if read duplication is enabled. + if (uvm_va_policy_is_read_duplicate(&node->policy, va_space)) + continue; + + region = uvm_va_block_region_from_start_end(va_block, + max(start, node->node.start), + min(end, node->node.end)); + + status = uvm_va_block_set_accessed_by_locked(va_block, + va_block_context, + processor_id, + region, + out_tracker); + if (status != NV_OK) + break; + } + + return status; +} + NV_STATUS uvm_hmm_set_accessed_by(uvm_va_space_t *va_space, uvm_processor_id_t processor_id, bool set_bit, NvU64 base, - NvU64 last_address) + NvU64 last_address, + uvm_tracker_t *out_tracker) { + uvm_va_block_context_t *va_block_context; uvm_va_block_t *va_block; NvU64 addr; NV_STATUS status = NV_OK; @@ -767,10 +1172,12 @@ // Update HMM accessed by policy. + va_block_context = uvm_va_space_block_context(va_space, va_space->va_space_mm.mm); + for (addr = base; addr < last_address; addr = va_block->end + 1) { NvU64 end; - status = hmm_va_block_find_create(va_space, addr, true, NULL, &va_block); + status = hmm_va_block_find_create(va_space, addr, true, &va_block_context->hmm.vma, &va_block); if (status != NV_OK) break; @@ -786,8 +1193,14 @@ processor_id, UVM_READ_DUPLICATION_MAX); - // TODO: Bug 1750144: need to call va_block_set_accessed_by_locked() - // if read duplication isn't enabled. + if (status == NV_OK && set_bit) { + status = hmm_set_accessed_by_start_end_locked(va_block, + va_block_context, + processor_id, + addr, + end, + out_tracker); + } uvm_mutex_unlock(&va_block->lock); @@ -798,13 +1211,90 @@ return status; } -void uvm_hmm_find_policy_end(uvm_va_block_t *va_block, - uvm_va_block_context_t *va_block_context, - unsigned long addr, - NvU64 *endp) +void uvm_hmm_block_add_eviction_mappings(uvm_va_space_t *va_space, + uvm_va_block_t *va_block, + uvm_va_block_context_t *block_context) { - struct vm_area_struct *vma = va_block_context->hmm.vma; + uvm_tracker_t local_tracker = UVM_TRACKER_INIT(); uvm_va_policy_node_t *node; + uvm_va_block_region_t region; + uvm_processor_mask_t map_processors; + uvm_processor_id_t id; + NV_STATUS tracker_status; + NV_STATUS status = NV_OK; + + UVM_ASSERT(uvm_va_block_is_hmm(va_block)); + uvm_assert_mmap_lock_locked(va_space->va_space_mm.mm); + uvm_assert_rwsem_locked(&va_space->lock); + + uvm_mutex_lock(&va_block->lock); + + uvm_for_each_va_policy_node_in(node, va_block, va_block->start, va_block->end) { + for_each_id_in_mask(id, &node->policy.accessed_by) { + status = hmm_set_accessed_by_start_end_locked(va_block, + block_context, + id, + node->node.start, + node->node.end, + &local_tracker); + if (status != NV_OK) + break; + + if (!uvm_va_space_map_remote_on_eviction(va_space)) + continue; + + // Exclude the processors that have been already mapped due to + // AccessedBy. + uvm_processor_mask_andnot(&map_processors, &va_block->evicted_gpus, &node->policy.accessed_by); + + for_each_gpu_id_in_mask(id, &map_processors) { + uvm_gpu_t *gpu = uvm_va_space_get_gpu(va_space, id); + uvm_va_block_gpu_state_t *gpu_state; + + if (!gpu->parent->access_counters_supported) + continue; + + gpu_state = uvm_va_block_gpu_state_get(va_block, id); + UVM_ASSERT(gpu_state); + + // TODO: Bug 2096389: uvm_va_block_add_mappings does not add + // remote mappings to read-duplicated pages. Add support for it + // or create a new function. + status = uvm_va_block_add_mappings(va_block, + block_context, + id, + region, + &gpu_state->evicted, + UvmEventMapRemoteCauseEviction); + tracker_status = uvm_tracker_add_tracker_safe(&local_tracker, &va_block->tracker); + status = (status == NV_OK) ? tracker_status : status; + if (status != NV_OK) { + UVM_ASSERT(status != NV_ERR_MORE_PROCESSING_REQUIRED); + break; + } + } + } + } + + uvm_mutex_unlock(&va_block->lock); + + tracker_status = uvm_tracker_wait_deinit(&local_tracker); + status = (status == NV_OK) ? tracker_status : status; + if (status != NV_OK) { + UVM_ERR_PRINT("Deferred mappings to evicted memory for block [0x%llx, 0x%llx] failed %s\n", + va_block->start, + va_block->end, + nvstatusToString(status)); + } +} + +const uvm_va_policy_t *uvm_hmm_find_policy_end(uvm_va_block_t *va_block, + struct vm_area_struct *vma, + unsigned long addr, + NvU64 *endp) +{ + const uvm_va_policy_node_t *node; + const uvm_va_policy_t *policy; NvU64 end = va_block->end; uvm_assert_mmap_lock_locked(vma->vm_mm); @@ -815,40 +1305,45 @@ node = uvm_va_policy_node_find(va_block, addr); if (node) { - va_block_context->policy = &node->policy; + policy = &node->policy; if (end > node->node.end) end = node->node.end; } else { - va_block_context->policy = &uvm_va_policy_default; + policy = &uvm_va_policy_default; } *endp = end; + + return policy; } NV_STATUS uvm_hmm_find_policy_vma_and_outer(uvm_va_block_t *va_block, - uvm_va_block_context_t *va_block_context, + struct vm_area_struct **vma_out, uvm_page_index_t page_index, + const uvm_va_policy_t **policy, uvm_page_index_t *outerp) { - struct vm_area_struct *vma; unsigned long addr; NvU64 end; uvm_page_index_t outer; + uvm_va_space_t *va_space = uvm_va_block_get_va_space(va_block); + struct mm_struct *mm = va_space->va_space_mm.mm; + + if (!mm) + return NV_ERR_INVALID_ADDRESS; UVM_ASSERT(uvm_va_block_is_hmm(va_block)); - uvm_assert_mmap_lock_locked(va_block_context->mm); + uvm_assert_mmap_lock_locked(mm); uvm_assert_mutex_locked(&va_block->lock); addr = uvm_va_block_cpu_page_address(va_block, page_index); - vma = vma_lookup(va_block_context->mm, addr); - if (!vma || !(vma->vm_flags & VM_READ)) + *vma_out = vma_lookup(mm, addr); + if (!*vma_out || !((*vma_out)->vm_flags & VM_READ)) return NV_ERR_INVALID_ADDRESS; - va_block_context->hmm.vma = vma; - - uvm_hmm_find_policy_end(va_block, va_block_context, addr, &end); + *policy = uvm_hmm_find_policy_end(va_block, *vma_out, addr, &end); outer = uvm_va_block_cpu_page_index(va_block, end) + 1; if (*outerp > outer) @@ -860,7 +1355,7 @@ static NV_STATUS hmm_clear_thrashing_policy(uvm_va_block_t *va_block, uvm_va_block_context_t *block_context) { - uvm_va_policy_t *policy; + const uvm_va_policy_t *policy; uvm_va_policy_node_t *node; uvm_va_block_region_t region; NV_STATUS status = NV_OK; @@ -868,8 +1363,6 @@ uvm_mutex_lock(&va_block->lock); uvm_for_each_va_policy_in(policy, va_block, va_block->start, va_block->end, node, region) { - block_context->policy = policy; - // Unmap may split PTEs and require a retry. Needs to be called // before the pinned pages information is destroyed. status = UVM_VA_BLOCK_RETRY_LOCKED(va_block, @@ -913,11 +1406,10 @@ } uvm_va_block_region_t uvm_hmm_get_prefetch_region(uvm_va_block_t *va_block, - uvm_va_block_context_t *va_block_context, + struct vm_area_struct *vma, + const uvm_va_policy_t *policy, NvU64 address) { - struct vm_area_struct *vma = va_block_context->hmm.vma; - uvm_va_policy_t *policy = va_block_context->policy; NvU64 start, end; UVM_ASSERT(uvm_va_block_is_hmm(va_block)); @@ -927,7 +1419,7 @@ end = min(va_block->end, (NvU64)vma->vm_end - 1); // Also, we need to limit the prefetch region to the policy range. - if (policy == &uvm_va_policy_default) { + if (uvm_va_policy_is_default(policy)) { NV_STATUS status = uvm_range_tree_find_hole_in(&va_block->hmm.va_policy_tree, address, &start, @@ -936,7 +1428,7 @@ UVM_ASSERT(status == NV_OK); } else { - uvm_va_policy_node_t *node = uvm_va_policy_node_from_policy(policy); + const uvm_va_policy_node_t *node = uvm_va_policy_node_from_policy(policy); start = max(start, node->node.start); end = min(end, node->node.end); @@ -946,13 +1438,11 @@ } uvm_prot_t uvm_hmm_compute_logical_prot(uvm_va_block_t *va_block, - uvm_va_block_context_t *va_block_context, + struct vm_area_struct *vma, NvU64 addr) { - struct vm_area_struct *vma = va_block_context->hmm.vma; - UVM_ASSERT(uvm_va_block_is_hmm(va_block)); - uvm_assert_mmap_lock_locked(va_block_context->mm); + uvm_assert_mmap_lock_locked(va_block->hmm.va_space->va_space_mm.mm); UVM_ASSERT(vma && addr >= vma->vm_start && addr < vma->vm_end); if (!(vma->vm_flags & VM_READ)) @@ -963,44 +1453,2055 @@ return UVM_PROT_READ_WRITE_ATOMIC; } -NV_STATUS uvm_test_split_invalidate_delay(UVM_TEST_SPLIT_INVALIDATE_DELAY_PARAMS *params, struct file *filp) +static NV_STATUS hmm_va_block_cpu_page_populate(uvm_va_block_t *va_block, + uvm_page_index_t page_index, + struct page *page) { - uvm_va_space_t *va_space = uvm_va_space_get(filp); + uvm_cpu_chunk_t *chunk; + NV_STATUS status; - atomic64_set(&va_space->test.split_invalidate_delay_us, params->delay_us); + UVM_ASSERT(uvm_va_block_is_hmm(va_block)); + UVM_ASSERT(!uvm_page_mask_test(&va_block->cpu.allocated, page_index)); + + if (page == ZERO_PAGE(uvm_va_block_cpu_page_address(va_block, page_index))) + return NV_ERR_INVALID_ADDRESS; + + status = uvm_cpu_chunk_alloc_hmm(page, &chunk); + if (status != NV_OK) + return status; + + status = uvm_cpu_chunk_insert_in_block(va_block, chunk, page_index); + if (status != NV_OK) { + uvm_cpu_chunk_free(chunk); + return status; + } + + status = uvm_va_block_map_cpu_chunk_on_gpus(va_block, page_index); + if (status != NV_OK) { + uvm_cpu_chunk_remove_from_block(va_block, page_index); + uvm_cpu_chunk_free(chunk); + } + + return status; +} + +static void hmm_va_block_cpu_page_unpopulate(uvm_va_block_t *va_block, + uvm_page_index_t page_index) +{ + uvm_cpu_chunk_t *chunk = uvm_cpu_chunk_get_chunk_for_page(va_block, page_index); + + UVM_ASSERT(uvm_va_block_is_hmm(va_block)); + + if (!chunk) + return; + + UVM_ASSERT(!uvm_processor_mask_test(&va_block->resident, UVM_ID_CPU) || + !uvm_page_mask_test(&va_block->cpu.resident, page_index)); + + uvm_cpu_chunk_remove_from_block(va_block, page_index); + uvm_va_block_unmap_cpu_chunk_on_gpus(va_block, chunk, page_index); + uvm_cpu_chunk_free(chunk); +} + +static bool hmm_va_block_cpu_page_is_same(uvm_va_block_t *va_block, + uvm_page_index_t page_index, + struct page *page) +{ + struct page *old_page = uvm_cpu_chunk_get_cpu_page(va_block, page_index); + + UVM_ASSERT(uvm_cpu_chunk_is_hmm(uvm_cpu_chunk_get_chunk_for_page(va_block, page_index))); + return old_page == page; +} + +// uvm_va_block_service_copy() and uvm_va_block_service_finish() expect the +// service_context masks to match what is being processed. Since a page +// that was expected to be processed isn't migrating, we have to clear the +// masks to make service_context consistent with what is actually being +// handled. +static void clear_service_context_masks(uvm_service_block_context_t *service_context, + uvm_processor_id_t new_residency, + uvm_page_index_t page_index) +{ + uvm_page_mask_clear(&service_context->block_context.caller_page_mask, page_index); + + uvm_page_mask_clear(&service_context->per_processor_masks[uvm_id_value(new_residency)].new_residency, + page_index); + + if (uvm_page_mask_empty(&service_context->per_processor_masks[uvm_id_value(new_residency)].new_residency)) + uvm_processor_mask_clear(&service_context->resident_processors, new_residency); + + if (UVM_ID_IS_VALID(service_context->prefetch_hint.residency)) + uvm_page_mask_clear(&service_context->prefetch_hint.prefetch_pages_mask, page_index); + + if (service_context->thrashing_pin_count > 0 && + uvm_page_mask_test_and_clear(&service_context->thrashing_pin_mask, page_index)) { + service_context->thrashing_pin_count--; + } + + if (service_context->read_duplicate_count > 0 && + uvm_page_mask_test_and_clear(&service_context->read_duplicate_mask, page_index)) { + service_context->read_duplicate_count--; + } +} + +static void cpu_mapping_set(uvm_va_block_t *va_block, + bool is_write, + uvm_page_index_t page_index) +{ + uvm_processor_mask_set(&va_block->mapped, UVM_ID_CPU); + uvm_page_mask_set(&va_block->maybe_mapped_pages, page_index); + uvm_page_mask_set(&va_block->cpu.pte_bits[UVM_PTE_BITS_CPU_READ], page_index); + if (is_write) + uvm_page_mask_set(&va_block->cpu.pte_bits[UVM_PTE_BITS_CPU_WRITE], page_index); + else + uvm_page_mask_clear(&va_block->cpu.pte_bits[UVM_PTE_BITS_CPU_WRITE], page_index); +} + +static void cpu_mapping_clear(uvm_va_block_t *va_block, uvm_page_index_t page_index) +{ + uvm_page_mask_clear(&va_block->cpu.pte_bits[UVM_PTE_BITS_CPU_WRITE], page_index); + uvm_page_mask_clear(&va_block->cpu.pte_bits[UVM_PTE_BITS_CPU_READ], page_index); + if (uvm_page_mask_empty(&va_block->cpu.pte_bits[UVM_PTE_BITS_CPU_READ])) + uvm_processor_mask_clear(&va_block->mapped, UVM_ID_CPU); +} + +static void gpu_chunk_remove(uvm_va_block_t *va_block, + uvm_page_index_t page_index, + struct page *page) +{ + uvm_va_block_gpu_state_t *gpu_state; + uvm_gpu_chunk_t *gpu_chunk; + uvm_gpu_id_t id; + + id = uvm_pmm_devmem_page_to_gpu_id(page); + gpu_state = uvm_va_block_gpu_state_get(va_block, id); + UVM_ASSERT(gpu_state); + + gpu_chunk = gpu_state->chunks[page_index]; + if (!gpu_chunk) { + // If we didn't find a chunk it's because the page was unmapped for + // mremap and no fault has established a new mapping. + UVM_ASSERT(!uvm_page_mask_test(&gpu_state->resident, page_index)); + return; + } + + // TODO: Bug 3898467: unmap indirect peers when freeing GPU chunks + + uvm_mmu_chunk_unmap(gpu_chunk, &va_block->tracker); + gpu_state->chunks[page_index] = NULL; +} + +static NV_STATUS gpu_chunk_add(uvm_va_block_t *va_block, + uvm_page_index_t page_index, + struct page *page) +{ + uvm_va_block_gpu_state_t *gpu_state; + uvm_gpu_chunk_t *gpu_chunk; + uvm_gpu_id_t id; + NV_STATUS status; + + id = uvm_pmm_devmem_page_to_gpu_id(page); + gpu_state = uvm_va_block_gpu_state_get(va_block, id); + + // It's possible that this is a fresh va_block we're trying to add an + // existing gpu_chunk to. This occurs for example when a GPU faults on a + // virtual address that has been remapped with mremap(). + if (!gpu_state) { + status = uvm_va_block_gpu_state_alloc(va_block); + if (status != NV_OK) + return status; + gpu_state = uvm_va_block_gpu_state_get(va_block, id); + } + + UVM_ASSERT(gpu_state); + + // Note that a mremap() might be to a CPU virtual address that is nolonger + // aligned with a larger GPU chunk size. We would need to allocate a new + // aligned GPU chunk and copy from old to new. + // TODO: Bug 3368756: add support for large GPU pages. + gpu_chunk = uvm_pmm_devmem_page_to_chunk(page); + UVM_ASSERT(gpu_chunk->state == UVM_PMM_GPU_CHUNK_STATE_ALLOCATED); + UVM_ASSERT(gpu_chunk->is_referenced); + UVM_ASSERT(page->zone_device_data == va_block->hmm.va_space); + + if (gpu_state->chunks[page_index] == gpu_chunk) + return NV_OK; + + UVM_ASSERT(!gpu_state->chunks[page_index]); + + // In some configurations such as SR-IOV heavy, the chunk cannot be + // referenced using its physical address. Create a virtual mapping. + status = uvm_mmu_chunk_map(gpu_chunk); + if (status != NV_OK) + return status; + + // TODO: Bug 3898467: map indirect peers. + + uvm_processor_mask_set(&va_block->resident, id); + uvm_page_mask_set(&gpu_state->resident, page_index); + + // It is safe to modify the page index field without holding any PMM locks + // because the chunk is allocated, which means that none of the other + // fields in the bitmap can change. + gpu_chunk->va_block = va_block; + gpu_chunk->va_block_page_index = page_index; + + gpu_state->chunks[page_index] = gpu_chunk; return NV_OK; } -NV_STATUS uvm_test_hmm_init(UVM_TEST_HMM_INIT_PARAMS *params, struct file *filp) +// This is called just before calling migrate_vma_finalize() in order to wait +// for GPU operations to complete and update the va_block state to match which +// pages migrated (or not) and therefore which pages will be released by +// migrate_vma_finalize(). +// 'migrated_pages' is the mask of pages that migrated, +// 'same_devmem_page_mask' is the mask of pages that are the same in src_pfns +// and dst_pfns and therefore appear to migrate_vma_*() to be not migrating. +// 'region' is the page index region of all migrated, non-migrated, and +// same_devmem_page_mask pages. +static NV_STATUS sync_page_and_chunk_state(uvm_va_block_t *va_block, + const unsigned long *src_pfns, + const unsigned long *dst_pfns, + uvm_va_block_region_t region, + const uvm_page_mask_t *migrated_pages, + const uvm_page_mask_t *same_devmem_page_mask) { - uvm_va_space_t *va_space = uvm_va_space_get(filp); - struct mm_struct *mm; + uvm_page_index_t page_index; NV_STATUS status; - mm = uvm_va_space_mm_or_current_retain(va_space); - if (!mm) - return NV_WARN_NOTHING_TO_DO; + // Wait for the GPU to finish. migrate_vma_finalize() will release the + // migrated source pages (or non migrating destination pages), so GPU + // opererations must be finished by then. + status = uvm_tracker_wait(&va_block->tracker); + + for_each_va_block_page_in_region(page_index, region) { + struct page *page; + + if (uvm_page_mask_test(same_devmem_page_mask, page_index)) + continue; + + // If a page migrated, clean up the source page. + // Otherwise, clean up the destination page. + if (uvm_page_mask_test(migrated_pages, page_index)) + page = migrate_pfn_to_page(src_pfns[page_index]); + else + page = migrate_pfn_to_page(dst_pfns[page_index]); - uvm_down_write_mmap_lock(mm); - uvm_va_space_down_write(va_space); - if (va_space->hmm.disable) - status = uvm_hmm_va_space_initialize_test(va_space); + if (!page) + continue; + + if (is_device_private_page(page)) { + gpu_chunk_remove(va_block, page_index, page); + } + else { + // If the source page is a system memory page, + // migrate_vma_finalize() will release the reference so we should + // clear our pointer to it. + // TODO: Bug 3660922: Need to handle read duplication at some point. + hmm_va_block_cpu_page_unpopulate(va_block, page_index); + } + } + + return status; +} + +// Update va_block state to reflect that the page isn't migrating. +static void clean_up_non_migrating_page(uvm_va_block_t *va_block, + const unsigned long *src_pfns, + unsigned long *dst_pfns, + uvm_page_index_t page_index) +{ + struct page *dst_page = migrate_pfn_to_page(dst_pfns[page_index]); + + if (!dst_page) + return; + + // migrate_vma_finalize() will release the dst_page reference so don't keep + // a pointer to it. + if (is_device_private_page(dst_page)) { + gpu_chunk_remove(va_block, page_index, dst_page); + } + else { + UVM_ASSERT(page_ref_count(dst_page) == 1); + + hmm_va_block_cpu_page_unpopulate(va_block, page_index); + } + + unlock_page(dst_page); + put_page(dst_page); + dst_pfns[page_index] = 0; +} + +static void clean_up_non_migrating_pages(uvm_va_block_t *va_block, + const unsigned long *src_pfns, + unsigned long *dst_pfns, + uvm_va_block_region_t region, + uvm_page_mask_t *page_mask) +{ + uvm_page_index_t page_index; + NV_STATUS status; + + status = uvm_tracker_wait(&va_block->tracker); + UVM_ASSERT(status == NV_OK); + + for_each_va_block_page_in_region_mask(page_index, page_mask, region) { + clean_up_non_migrating_page(va_block, src_pfns, dst_pfns, page_index); + } +} + +// CPU page fault handling. + +// Fill in the dst_pfns[page_index] entry given that there is an allocated +// CPU page. +static void lock_block_cpu_page(uvm_va_block_t *va_block, + uvm_page_index_t page_index, + struct page *src_page, + unsigned long *dst_pfns, + uvm_page_mask_t *same_devmem_page_mask) +{ + uvm_cpu_chunk_t *chunk = uvm_cpu_chunk_get_chunk_for_page(va_block, page_index); + uvm_va_block_region_t chunk_region; + struct page *dst_page; + + UVM_ASSERT(chunk); + UVM_ASSERT(chunk->page); + + chunk_region = uvm_va_block_chunk_region(va_block, uvm_cpu_chunk_get_size(chunk), page_index); + + dst_page = chunk->page + (page_index - chunk_region.first); + + UVM_ASSERT(dst_page != ZERO_PAGE(uvm_va_block_cpu_page_address(va_block, page_index))); + UVM_ASSERT(!is_device_private_page(dst_page)); + + // The source page is usually a device private page but it could be a GPU + // remote mapped system memory page. It could also be a driver allocated + // page for GPU-to-GPU staged copies (i.e., not a resident copy and owned + // by the driver). + if (is_device_private_page(src_page)) { + // Since the page isn't mirrored, it was allocated by alloc_pages() + // and UVM owns the reference. We leave the reference count unchanged + // and mark the page pointer as mirrored since UVM is transferring + // ownership to Linux and we don't want UVM to double free the page in + // hmm_va_block_cpu_page_unpopulate() or block_kill(). If the page + // does not migrate, it will be freed though. + UVM_ASSERT(!uvm_processor_mask_test(&va_block->resident, UVM_ID_CPU) || + !uvm_page_mask_test(&va_block->cpu.resident, page_index)); + UVM_ASSERT(chunk->type == UVM_CPU_CHUNK_TYPE_PHYSICAL); + UVM_ASSERT(page_ref_count(dst_page) == 1); + uvm_cpu_chunk_make_hmm(chunk); + } + else { + UVM_ASSERT(same_devmem_page_mask); + UVM_ASSERT(src_page == dst_page); + uvm_page_mask_set(same_devmem_page_mask, page_index); + + // The call to migrate_vma_setup() will have inserted a migration PTE + // so the CPU has no access. + cpu_mapping_clear(va_block, page_index); + return; + } + + lock_page(dst_page); + dst_pfns[page_index] = migrate_pfn(page_to_pfn(dst_page)); +} + +static void hmm_mark_gpu_chunk_referenced(uvm_va_block_t *va_block, + uvm_gpu_t *gpu, + uvm_gpu_chunk_t *gpu_chunk) +{ + // Tell PMM to expect a callback from Linux to free the page since the + // device private struct page reference count will determine when the + // GPU chunk is free. + UVM_ASSERT(gpu_chunk->state == UVM_PMM_GPU_CHUNK_STATE_TEMP_PINNED); + list_del_init(&gpu_chunk->list); + uvm_pmm_gpu_unpin_referenced(&gpu->pmm, gpu_chunk, va_block); +} + +static void fill_dst_pfn(uvm_va_block_t *va_block, + uvm_gpu_t *gpu, + const unsigned long *src_pfns, + unsigned long *dst_pfns, + uvm_page_index_t page_index, + uvm_page_mask_t *same_devmem_page_mask) +{ + unsigned long src_pfn = src_pfns[page_index]; + uvm_gpu_chunk_t *gpu_chunk; + unsigned long pfn; + struct page *dpage; + + gpu_chunk = uvm_va_block_lookup_gpu_chunk(va_block, gpu, uvm_va_block_cpu_page_address(va_block, page_index)); + UVM_ASSERT(gpu_chunk); + UVM_ASSERT(gpu_chunk->log2_size == PAGE_SHIFT); + pfn = uvm_pmm_gpu_devmem_get_pfn(&gpu->pmm, gpu_chunk); + + // If the same GPU page is both source and destination, migrate_vma_pages() + // will see the wrong "expected" reference count and not migrate it, so we + // mark it as not migrating but we keep track of this so we don't confuse + // it with a page that migrate_vma_pages() actually does not migrate. + if ((src_pfn & MIGRATE_PFN_VALID) && (src_pfn >> MIGRATE_PFN_SHIFT) == pfn) { + uvm_page_mask_set(same_devmem_page_mask, page_index); + return; + } + + dpage = pfn_to_page(pfn); + UVM_ASSERT(is_device_private_page(dpage)); + UVM_ASSERT(dpage->pgmap->owner == &g_uvm_global); + + hmm_mark_gpu_chunk_referenced(va_block, gpu, gpu_chunk); + UVM_ASSERT(!page_count(dpage)); + zone_device_page_init(dpage); + dpage->zone_device_data = va_block->hmm.va_space; + + dst_pfns[page_index] = migrate_pfn(pfn); +} + +static void fill_dst_pfns(uvm_va_block_t *va_block, + const unsigned long *src_pfns, + unsigned long *dst_pfns, + uvm_va_block_region_t region, + uvm_page_mask_t *page_mask, + uvm_page_mask_t *same_devmem_page_mask, + uvm_processor_id_t dest_id) +{ + uvm_gpu_t *gpu = uvm_va_space_get_gpu(va_block->hmm.va_space, dest_id); + uvm_page_index_t page_index; + + uvm_page_mask_zero(same_devmem_page_mask); + + for_each_va_block_page_in_region_mask(page_index, page_mask, region) { + if (!(src_pfns[page_index] & MIGRATE_PFN_MIGRATE)) + continue; + + fill_dst_pfn(va_block, + gpu, + src_pfns, + dst_pfns, + page_index, + same_devmem_page_mask); + } +} + +static NV_STATUS alloc_and_copy_to_cpu(uvm_va_block_t *va_block, + struct vm_area_struct *vma, + const unsigned long *src_pfns, + unsigned long *dst_pfns, + uvm_va_block_region_t region, + uvm_page_mask_t *page_mask, + uvm_page_mask_t *same_devmem_page_mask, + uvm_processor_id_t processor_id, + uvm_service_block_context_t *service_context) +{ + uvm_page_index_t page_index; + NV_STATUS status = NV_OK; + + for_each_va_block_page_in_region_mask(page_index, page_mask, region) { + struct page *src_page; + struct page *dst_page; + gfp_t gfp; + + if (!(src_pfns[page_index] & MIGRATE_PFN_MIGRATE)) { + // Device exclusive PTEs are not selected but we still want to + // process the page so record it as such. + if (service_context && !UVM_ID_IS_CPU(processor_id) && + service_context->access_type[page_index] == UVM_FAULT_ACCESS_TYPE_ATOMIC_STRONG) { + uvm_page_mask_set(same_devmem_page_mask, page_index); + continue; + } + + // We have previously found a page that is CPU resident which can't + // be migrated (probably a shared mapping) so make sure we establish + // a remote mapping for it. + if (uvm_page_mask_test(same_devmem_page_mask, page_index)) + continue; + + goto clr_mask; + } + + // This is the page that will be copied to system memory. + src_page = migrate_pfn_to_page(src_pfns[page_index]); + + if (src_page) { + // mremap may have caused us to loose the gpu_chunk associated with + // this va_block/page_index so make sure we have the correct chunk. + if (is_device_private_page(src_page)) + gpu_chunk_add(va_block, page_index, src_page); + + if (uvm_page_mask_test(&va_block->cpu.allocated, page_index)) { + lock_block_cpu_page(va_block, page_index, src_page, dst_pfns, same_devmem_page_mask); + continue; + } + } + + UVM_ASSERT(!uvm_processor_mask_test(&va_block->resident, UVM_ID_CPU) || + !uvm_page_mask_test(&va_block->cpu.resident, page_index)); + + // Allocate a user system memory page for the destination. + // This is the typical case since Linux will free the source page when + // migrating to device private memory. + // If there is no source page, it means the page is pte_none() or the + // zero page. This case "shouldn't happen" because we asked + // migrate_vma_setup() only for device private pages but + // migrate_vma_collect_hole() doesn't check the + // MIGRATE_VMA_SELECT_SYSTEM flag. + gfp = GFP_HIGHUSER_MOVABLE; + if (!src_page) + gfp |= __GFP_ZERO; + + dst_page = alloc_page_vma(gfp, + vma, + va_block->start + (page_index << PAGE_SHIFT)); + if (!dst_page) { + // Ignore errors if the page is only for prefetching. + if (service_context && + service_context->access_type[page_index] == UVM_FAULT_ACCESS_TYPE_PREFETCH) + goto clr_mask; + UVM_ERR_PRINT("cannot allocate page %u (addr 0x%llx)\n", + page_index, va_block->start + (page_index << PAGE_SHIFT)); + status = NV_ERR_NO_MEMORY; + break; + } + + status = hmm_va_block_cpu_page_populate(va_block, page_index, dst_page); + if (status != NV_OK) { + __free_page(dst_page); + // Ignore errors if the page is only for prefetching. + if (service_context && + service_context->access_type[page_index] == UVM_FAULT_ACCESS_TYPE_PREFETCH) + goto clr_mask; + break; + } + + // Note that we don't call get_page(dst_page) since alloc_page_vma() + // returns with a page reference count of one and we are passing + // ownership to Linux. Also, uvm_va_block_cpu_page_populate() recorded + // the page as "mirrored" so that migrate_vma_finalize() and + // hmm_va_block_cpu_page_unpopulate() don't double free the page. + lock_page(dst_page); + dst_pfns[page_index] = migrate_pfn(page_to_pfn(dst_page)); + continue; + + clr_mask: + // TODO: Bug 3900774: clean up murky mess of mask clearing. + uvm_page_mask_clear(page_mask, page_index); + if (service_context) + clear_service_context_masks(service_context, UVM_ID_CPU, page_index); + } + + if (status != NV_OK) + clean_up_non_migrating_pages(va_block, src_pfns, dst_pfns, region, page_mask); + else if (uvm_page_mask_empty(page_mask)) + return NV_WARN_MORE_PROCESSING_REQUIRED; + + return status; +} + +static NV_STATUS uvm_hmm_devmem_fault_alloc_and_copy(uvm_hmm_devmem_fault_context_t *devmem_fault_context) +{ + uvm_processor_id_t processor_id; + uvm_service_block_context_t *service_context; + uvm_va_block_retry_t *va_block_retry; + const unsigned long *src_pfns; + unsigned long *dst_pfns; + uvm_page_mask_t *page_mask; + uvm_page_mask_t *same_devmem_page_mask = &devmem_fault_context->same_devmem_page_mask; + uvm_va_block_t *va_block; + NV_STATUS status = NV_OK; + + processor_id = devmem_fault_context->processor_id; + service_context = devmem_fault_context->service_context; + va_block_retry = devmem_fault_context->va_block_retry; + va_block = devmem_fault_context->va_block; + src_pfns = service_context->block_context.hmm.src_pfns; + dst_pfns = service_context->block_context.hmm.dst_pfns; + + // Build the migration page mask. + // Note that thrashing pinned pages and prefetch pages are already + // accounted for in service_context->per_processor_masks. + page_mask = &devmem_fault_context->page_mask; + uvm_page_mask_copy(page_mask, &service_context->per_processor_masks[UVM_ID_CPU_VALUE].new_residency); + + status = alloc_and_copy_to_cpu(va_block, + service_context->block_context.hmm.vma, + src_pfns, + dst_pfns, + service_context->region, + page_mask, + same_devmem_page_mask, + processor_id, + service_context); + if (status != NV_OK) + return status; + + // Do the copy but don't update the residency or mapping for the new + // location yet. + return uvm_va_block_service_copy(processor_id, UVM_ID_CPU, va_block, va_block_retry, service_context); +} + +static NV_STATUS uvm_hmm_devmem_fault_finalize_and_map(uvm_hmm_devmem_fault_context_t *devmem_fault_context) +{ + uvm_processor_id_t processor_id; + uvm_service_block_context_t *service_context; + uvm_perf_prefetch_hint_t *prefetch_hint; + uvm_va_block_retry_t *va_block_retry; + const unsigned long *src_pfns; + unsigned long *dst_pfns; + uvm_page_mask_t *page_mask; + uvm_va_block_t *va_block; + uvm_va_block_region_t region; + uvm_page_index_t page_index; + NV_STATUS status, tracker_status; + + processor_id = devmem_fault_context->processor_id; + service_context = devmem_fault_context->service_context; + prefetch_hint = &service_context->prefetch_hint; + va_block = devmem_fault_context->va_block; + va_block_retry = devmem_fault_context->va_block_retry; + src_pfns = service_context->block_context.hmm.src_pfns; + dst_pfns = service_context->block_context.hmm.dst_pfns; + region = service_context->region; + + page_mask = &devmem_fault_context->page_mask; + + // There are a number of reasons why HMM will mark a page as not migrating + // even if we set a valid entry in dst_pfns[]. Mark these pages accordingly. + for_each_va_block_page_in_region_mask(page_index, page_mask, region) { + if (src_pfns[page_index] & MIGRATE_PFN_MIGRATE) + continue; + + // If a page isn't migrating and only the GPU page table is being + // updated, continue to process it normally. + if (uvm_page_mask_test(&devmem_fault_context->same_devmem_page_mask, page_index)) + continue; + + // TODO: Bug 3900774: clean up murky mess of mask clearing. + uvm_page_mask_clear(page_mask, page_index); + clear_service_context_masks(service_context, UVM_ID_CPU, page_index); + } + + if (uvm_page_mask_empty(page_mask)) + status = NV_WARN_MORE_PROCESSING_REQUIRED; + else + status = uvm_va_block_service_finish(processor_id, va_block, service_context); + + tracker_status = sync_page_and_chunk_state(va_block, + src_pfns, + dst_pfns, + region, + page_mask, + &devmem_fault_context->same_devmem_page_mask); + + return status == NV_OK ? tracker_status : status; +} + +static NV_STATUS populate_region(uvm_va_block_t *va_block, + unsigned long *pfns, + uvm_va_block_region_t region, + uvm_page_mask_t *populated_page_mask) +{ + uvm_page_index_t page_index; + NV_STATUS status; + + // Make sure GPU state is allocated or else the GPU DMA mappings to + // system memory won't be saved. + status = uvm_va_block_gpu_state_alloc(va_block); + if (status != NV_OK) + return status; + + for_each_va_block_page_in_region(page_index, region) { + struct page *page; + + // This case should only happen when querying CPU residency and we ask + // for something not covered by a VMA. Otherwise, hmm_range_fault() + // returns -EFAULT instead of setting the HMM_PFN_ERROR bit. + if (pfns[page_index] & HMM_PFN_ERROR) + return NV_ERR_INVALID_ADDRESS; + + if (pfns[page_index] & HMM_PFN_VALID) { + page = hmm_pfn_to_page(pfns[page_index]); + } + else { + // The page can't be evicted since it has to be migrated to the GPU + // first which would leave a device private page entry so this has + // to be a pte_none(), swapped out, or similar entry. + // The page would have been allocated if populate_region() is being + // called from uvm_hmm_va_block_service_locked() so this must be + // for uvm_hmm_va_block_update_residency_info(). Just leave the + // residency/populated information unchanged since + // uvm_hmm_invalidate() should handle that if the underlying page + // is invalidated. + // Also note there can be an allocated page due to GPU-to-GPU + // migration between non-peer or indirect peer GPUs. + continue; + } + + if (is_device_private_page(page)) { + // Linux can call hmm_invalidate() and we have to clear the GPU + // chunk pointer in uvm_va_block_gpu_state_t::chunks[] but it might + // not release the device private struct page reference. Since + // hmm_range_fault() did find a device private PTE, we can + // re-establish the GPU chunk pointer. + status = gpu_chunk_add(va_block, page_index, page); + if (status != NV_OK) + return status; + continue; + } + + // If a CPU chunk is already allocated, check to see it matches what + // hmm_range_fault() found. + if (uvm_page_mask_test(&va_block->cpu.allocated, page_index)) { + UVM_ASSERT(hmm_va_block_cpu_page_is_same(va_block, page_index, page)); + } + else { + status = hmm_va_block_cpu_page_populate(va_block, page_index, page); + if (status != NV_OK) + return status; + + // Record that we populated this page. hmm_block_cpu_fault_locked() + // uses this to ensure pages that don't migrate get remote mapped. + if (populated_page_mask) + uvm_page_mask_set(populated_page_mask, page_index); + } + + // Since we have a stable snapshot of the CPU pages, we can + // update the residency and protection information. + uvm_processor_mask_set(&va_block->resident, UVM_ID_CPU); + uvm_page_mask_set(&va_block->cpu.resident, page_index); + + cpu_mapping_set(va_block, pfns[page_index] & HMM_PFN_WRITE, page_index); + } + + return NV_OK; +} + +static void hmm_range_fault_begin(uvm_va_block_t *va_block) +{ + uvm_thread_context_t *uvm_context = uvm_thread_context(); + + uvm_assert_mutex_locked(&va_block->lock); + uvm_context->hmm_invalidate_seqnum = va_block->hmm.changed; +} + +static bool hmm_range_fault_retry(uvm_va_block_t *va_block) +{ + uvm_thread_context_t *uvm_context = uvm_thread_context(); + + uvm_assert_mutex_locked(&va_block->lock); + return uvm_context->hmm_invalidate_seqnum != va_block->hmm.changed; +} + +// Make the region be resident on the CPU by calling hmm_range_fault() to fault +// in CPU pages. +static NV_STATUS hmm_make_resident_cpu(uvm_va_block_t *va_block, + struct vm_area_struct *vma, + unsigned long *hmm_pfns, + uvm_va_block_region_t region, + NvU8 *access_type, + uvm_page_mask_t *populated_page_mask) +{ + uvm_page_index_t page_index; + int ret; + struct hmm_range range = { + .notifier = &va_block->hmm.notifier, + .start = uvm_va_block_region_start(va_block, region), + .end = uvm_va_block_region_end(va_block, region) + 1, + .hmm_pfns = hmm_pfns + region.first, + .pfn_flags_mask = HMM_PFN_REQ_FAULT | HMM_PFN_REQ_WRITE, + .dev_private_owner = &g_uvm_global, + }; + + for_each_va_block_page_in_region(page_index, region) { + if ((access_type && access_type[page_index] >= UVM_FAULT_ACCESS_TYPE_WRITE) || + (vma->vm_flags & VM_WRITE)) + hmm_pfns[page_index] = HMM_PFN_REQ_FAULT | HMM_PFN_REQ_WRITE; + else + hmm_pfns[page_index] = HMM_PFN_REQ_FAULT; + } + + hmm_range_fault_begin(va_block); + + // Mirror the VA block to the HMM address range. + // Note that we request HMM to handle page faults, which means that it will + // populate and map potentially not-yet-existing pages to the VMA. + // Also note that mmu_interval_read_begin() calls wait_event() for any + // parallel invalidation callbacks to finish so we can't hold locks that + // the invalidation callback acquires. + uvm_mutex_unlock(&va_block->lock); + + range.notifier_seq = mmu_interval_read_begin(range.notifier); + ret = hmm_range_fault(&range); + + uvm_mutex_lock(&va_block->lock); + + if (ret) + return (ret == -EBUSY) ? NV_WARN_MORE_PROCESSING_REQUIRED : errno_to_nv_status(ret); + + if (hmm_range_fault_retry(va_block)) + return NV_WARN_MORE_PROCESSING_REQUIRED; + + return populate_region(va_block, + hmm_pfns, + region, + populated_page_mask); +} + +// Release the reference count on any pages that were made device exclusive. +static void hmm_release_atomic_pages(uvm_va_block_t *va_block, + uvm_service_block_context_t *service_context) +{ + uvm_va_block_region_t region = service_context->region; + uvm_page_index_t page_index; + + for_each_va_block_page_in_region(page_index, region) { + struct page *page = service_context->block_context.hmm.pages[page_index]; + + if (!page) + continue; + + unlock_page(page); + put_page(page); + } +} + +static NV_STATUS hmm_block_atomic_fault_locked(uvm_processor_id_t processor_id, + uvm_va_block_t *va_block, + uvm_va_block_retry_t *va_block_retry, + uvm_service_block_context_t *service_context) +{ + uvm_va_block_region_t region = service_context->region; + struct page **pages = service_context->block_context.hmm.pages; + int npages; + uvm_page_index_t page_index; + uvm_make_resident_cause_t cause; + NV_STATUS status; + + if (!uvm_processor_mask_test(&va_block->resident, UVM_ID_CPU) || + !uvm_page_mask_region_full(&va_block->cpu.resident, region)) { + // There is an atomic GPU fault. We need to make sure no pages are + // GPU resident so that make_device_exclusive_range() doesn't call + // migrate_to_ram() and cause a va_space lock recursion problem. + if (service_context->operation == UVM_SERVICE_OPERATION_REPLAYABLE_FAULTS) + cause = UVM_MAKE_RESIDENT_CAUSE_REPLAYABLE_FAULT; + else if (service_context->operation == UVM_SERVICE_OPERATION_NON_REPLAYABLE_FAULTS) + cause = UVM_MAKE_RESIDENT_CAUSE_NON_REPLAYABLE_FAULT; + else + cause = UVM_MAKE_RESIDENT_CAUSE_ACCESS_COUNTER; + + status = uvm_hmm_va_block_migrate_locked(va_block, + va_block_retry, + &service_context->block_context, + UVM_ID_CPU, + region, + cause); + if (status != NV_OK) + goto done; + + // make_device_exclusive_range() will try to call migrate_to_ram() + // and deadlock with ourself if the data isn't CPU resident. + if (!uvm_processor_mask_test(&va_block->resident, UVM_ID_CPU) || + !uvm_page_mask_region_full(&va_block->cpu.resident, region)) { + status = NV_WARN_MORE_PROCESSING_REQUIRED; + goto done; + } + } + + // TODO: Bug 4014681: atomic GPU operations are not supported on MAP_SHARED + // mmap() files so we check for that here and report a fatal fault. + // Otherwise with the current Linux 6.1 make_device_exclusive_range(), + // it doesn't make the page exclusive and we end up in an endless loop. + if (service_context->block_context.hmm.vma->vm_flags & VM_SHARED) { + status = NV_ERR_NOT_SUPPORTED; + goto done; + } + + hmm_range_fault_begin(va_block); + + uvm_mutex_unlock(&va_block->lock); + + npages = make_device_exclusive_range(service_context->block_context.mm, + uvm_va_block_cpu_page_address(va_block, region.first), + uvm_va_block_cpu_page_address(va_block, region.outer - 1) + PAGE_SIZE, + pages + region.first, + &g_uvm_global); + + uvm_mutex_lock(&va_block->lock); + + if (npages < 0) { + status = (npages == -EBUSY) ? NV_WARN_MORE_PROCESSING_REQUIRED : errno_to_nv_status(npages); + goto done; + } + + while ((size_t)npages < uvm_va_block_region_num_pages(region)) + pages[region.first + npages++] = NULL; + + if (hmm_range_fault_retry(va_block)) { + status = NV_WARN_MORE_PROCESSING_REQUIRED; + goto release; + } + + status = NV_OK; + + for_each_va_block_page_in_region(page_index, region) { + struct page *page = pages[page_index]; + + if (!page) { + // Record that one of the pages isn't exclusive but keep converting + // the others. + status = NV_WARN_MORE_PROCESSING_REQUIRED; + continue; + } + + // If a CPU chunk is already allocated, check to see it matches what + // make_device_exclusive_range() found. + if (uvm_page_mask_test(&va_block->cpu.allocated, page_index)) { + UVM_ASSERT(hmm_va_block_cpu_page_is_same(va_block, page_index, page)); + UVM_ASSERT(uvm_processor_mask_test(&va_block->resident, UVM_ID_CPU)); + UVM_ASSERT(uvm_page_mask_test(&va_block->cpu.resident, page_index)); + } + else { + NV_STATUS s = hmm_va_block_cpu_page_populate(va_block, page_index, page); + + if (s == NV_OK) { + uvm_processor_mask_set(&va_block->resident, UVM_ID_CPU); + uvm_page_mask_set(&va_block->cpu.resident, page_index); + } + } + + cpu_mapping_clear(va_block, page_index); + } + + if (status != NV_OK) + goto release; + + status = uvm_va_block_service_copy(processor_id, UVM_ID_CPU, va_block, va_block_retry, service_context); + if (status != NV_OK) + goto release; + + status = uvm_va_block_service_finish(processor_id, va_block, service_context); + +release: + hmm_release_atomic_pages(va_block, service_context); + +done: + return status; +} + +static bool is_atomic_fault(NvU8 *access_type, uvm_va_block_region_t region) +{ + uvm_page_index_t page_index; + + for_each_va_block_page_in_region(page_index, region) { + if (access_type[page_index] == UVM_FAULT_ACCESS_TYPE_ATOMIC_STRONG) + return true; + } + + return false; +} + +static bool is_gpu_resident(uvm_va_block_t *va_block, uvm_va_block_region_t region) +{ + uvm_processor_id_t gpu_id; + + for_each_gpu_id_in_mask(gpu_id, &va_block->resident) { + uvm_va_block_gpu_state_t *gpu_state; + + gpu_state = uvm_va_block_gpu_state_get(va_block, gpu_id); + if (!uvm_page_mask_region_empty(&gpu_state->resident, region)) + return true; + } + + return false; +} + +static NV_STATUS hmm_block_cpu_fault_locked(uvm_processor_id_t processor_id, + uvm_va_block_t *va_block, + uvm_va_block_retry_t *va_block_retry, + uvm_service_block_context_t *service_context) +{ + uvm_va_block_region_t region = service_context->region; + struct migrate_vma *args = &service_context->block_context.hmm.migrate_vma_args; + NV_STATUS status; + int ret; + uvm_hmm_devmem_fault_context_t fault_context = { + .processor_id = processor_id, + .va_block = va_block, + .va_block_retry = va_block_retry, + .service_context = service_context, + }; + + // Normally the source page will be a device private page that is being + // migrated to system memory. However, when it is a GPU fault, the source + // page can be a system memory page that the GPU needs to remote map + // instead. However migrate_vma_setup() won't select these types of + // mappings/pages: + // - device exclusive PTEs + // - shared mappings + // - file backed mappings + // Also, if the source and destination page are the same, the page reference + // count won't be the "expected" count and migrate_vma_pages() won't migrate + // it. This mask records that uvm_hmm_devmem_fault_alloc_and_copy() and + // uvm_hmm_devmem_fault_finalize_and_map() still needs to process these + // pages even if src_pfn indicates they are not migrating. + uvm_page_mask_zero(&fault_context.same_devmem_page_mask); + + if (!UVM_ID_IS_CPU(processor_id)) { + if (is_atomic_fault(service_context->access_type, region)) { + return hmm_block_atomic_fault_locked(processor_id, + va_block, + va_block_retry, + service_context); + } + + status = hmm_make_resident_cpu(va_block, + service_context->block_context.hmm.vma, + service_context->block_context.hmm.src_pfns, + region, + service_context->access_type, + &fault_context.same_devmem_page_mask); + if (status != NV_OK) + return status; + + // If no GPU has a resident copy, we can skip the migrate_vma_*(). + // This is necessary if uvm_hmm_must_use_sysmem() returned true. + if (!is_gpu_resident(va_block, region)) { + status = uvm_va_block_service_copy(processor_id, + UVM_ID_CPU, + va_block, + va_block_retry, + service_context); + if (status != NV_OK) + return status; + + return uvm_va_block_service_finish(processor_id, va_block, service_context); + } + } + + args->vma = service_context->block_context.hmm.vma; + args->src = service_context->block_context.hmm.src_pfns + region.first; + args->dst = service_context->block_context.hmm.dst_pfns + region.first; + args->start = uvm_va_block_region_start(va_block, region); + args->end = uvm_va_block_region_end(va_block, region) + 1; + args->flags = MIGRATE_VMA_SELECT_DEVICE_PRIVATE; + args->pgmap_owner = &g_uvm_global; + + if (UVM_ID_IS_CPU(processor_id)) { + args->fault_page = service_context->cpu_fault.vmf->page; + } + else { + args->flags |= MIGRATE_VMA_SELECT_SYSTEM; + args->fault_page = NULL; + } + + ret = migrate_vma_setup_locked(args, va_block); + UVM_ASSERT(!ret); + + // The overall process here is to migrate pages from the GPU to the CPU + // and possibly remote map the GPU to sysmem if accessed_by is set. + // This is safe because we hold the va_block lock across the calls to + // uvm_hmm_devmem_fault_alloc_and_copy(), migrate_vma_pages(), + // uvm_hmm_devmem_fault_finalize_and_map(), and migrate_vma_finalize(). + // If uvm_hmm_devmem_fault_alloc_and_copy() needs to drop the va_block + // lock, a sequence number is used to tell if an invalidate() callback + // occurred while not holding the lock. If the sequence number changes, + // all the locks need to be dropped (mm, va_space, va_block) and the whole + // uvm_va_block_service_locked() called again. Otherwise, there were no + // conflicting invalidate callbacks and our snapshots of the CPU page + // tables are accurate and can be used to DMA pages and update GPU page + // tables. + status = uvm_hmm_devmem_fault_alloc_and_copy(&fault_context); + if (status == NV_OK) { + migrate_vma_pages(args); + status = uvm_hmm_devmem_fault_finalize_and_map(&fault_context); + } + + migrate_vma_finalize(args); + + if (status == NV_WARN_NOTHING_TO_DO) + status = NV_OK; + + return status; +} + +static NV_STATUS dmamap_src_sysmem_pages(uvm_va_block_t *va_block, + struct vm_area_struct *vma, + const unsigned long *src_pfns, + unsigned long *dst_pfns, + uvm_va_block_region_t region, + uvm_page_mask_t *page_mask, + uvm_processor_id_t dest_id, + uvm_service_block_context_t *service_context) +{ + uvm_page_index_t page_index; + NV_STATUS status = NV_OK; + + for_each_va_block_page_in_region_mask(page_index, page_mask, region) { + struct page *src_page; + + if (!(src_pfns[page_index] & MIGRATE_PFN_MIGRATE)) { + // HMM currently has some limitations on what pages can be migrated. + // For example, no file backed pages, device private pages owned by + // a different device, device exclusive or swapped out pages. + goto clr_mask; + } + + // This is the page that will be copied to the destination GPU. + src_page = migrate_pfn_to_page(src_pfns[page_index]); + if (src_page) { + if (is_device_private_page(src_page)) { + status = gpu_chunk_add(va_block, page_index, src_page); + if (status != NV_OK) + break; + continue; + } + + if (PageSwapCache(src_page)) { + // TODO: Bug 4050579: Remove this when swap cached pages can be + // migrated. + if (service_context) { + service_context->block_context.hmm.swap_cached = true; + break; + } + + goto clr_mask; + } + + // If the page is already allocated, it is most likely a mirrored + // page. Check to be sure it matches what we have recorded. The + // page shouldn't be a staging page from a GPU to GPU migration + // or a remote mapped atomic sysmem page because migrate_vma_setup() + // found a normal page and non-mirrored pages are only known + // privately to the UVM driver. + if (uvm_page_mask_test(&va_block->cpu.allocated, page_index)) { + UVM_ASSERT(hmm_va_block_cpu_page_is_same(va_block, page_index, src_page)); + UVM_ASSERT(uvm_processor_mask_test(&va_block->resident, UVM_ID_CPU)); + UVM_ASSERT(uvm_page_mask_test(&va_block->cpu.resident, page_index)); + } + else { + status = hmm_va_block_cpu_page_populate(va_block, page_index, src_page); + if (status != NV_OK) + goto clr_mask; + + // Since there is a CPU resident page, there shouldn't be one + // anywhere else. TODO: Bug 3660922: Need to handle read + // duplication at some point. + UVM_ASSERT(!uvm_va_block_page_resident_processors_count(va_block, page_index)); + + // migrate_vma_setup() was able to isolate and lock the page; + // therefore, it is CPU resident and not mapped. + uvm_processor_mask_set(&va_block->resident, UVM_ID_CPU); + uvm_page_mask_set(&va_block->cpu.resident, page_index); + } + + // The call to migrate_vma_setup() will have inserted a migration + // PTE so the CPU has no access. + cpu_mapping_clear(va_block, page_index); + } + else { + // It is OK to migrate an empty anonymous page, a zero page will + // be allocated on the GPU. Just be sure to free any pages + // used for GPU to GPU copies. It can't be an evicted page because + // migrate_vma_setup() would have found a source page. + if (uvm_page_mask_test(&va_block->cpu.allocated, page_index)) { + UVM_ASSERT(!uvm_va_block_page_resident_processors_count(va_block, page_index)); + + hmm_va_block_cpu_page_unpopulate(va_block, page_index); + } + } + + continue; + + clr_mask: + // TODO: Bug 3900774: clean up murky mess of mask clearing. + uvm_page_mask_clear(page_mask, page_index); + if (service_context) + clear_service_context_masks(service_context, dest_id, page_index); + } + + if (uvm_page_mask_empty(page_mask) || + (service_context && service_context->block_context.hmm.swap_cached)) + status = NV_WARN_MORE_PROCESSING_REQUIRED; + + if (status != NV_OK) + clean_up_non_migrating_pages(va_block, src_pfns, dst_pfns, region, page_mask); + + return status; +} + +static NV_STATUS uvm_hmm_gpu_fault_alloc_and_copy(struct vm_area_struct *vma, + uvm_hmm_gpu_fault_event_t *uvm_hmm_gpu_fault_event) +{ + uvm_processor_id_t processor_id; + uvm_processor_id_t new_residency; + uvm_va_block_t *va_block; + uvm_va_block_retry_t *va_block_retry; + uvm_service_block_context_t *service_context; + uvm_perf_prefetch_hint_t *prefetch_hint; + const unsigned long *src_pfns; + unsigned long *dst_pfns; + uvm_va_block_region_t region; + uvm_page_mask_t *page_mask; + NV_STATUS status; + + processor_id = uvm_hmm_gpu_fault_event->processor_id; + new_residency = uvm_hmm_gpu_fault_event->new_residency; + va_block = uvm_hmm_gpu_fault_event->va_block; + va_block_retry = uvm_hmm_gpu_fault_event->va_block_retry; + service_context = uvm_hmm_gpu_fault_event->service_context; + region = service_context->region; + prefetch_hint = &service_context->prefetch_hint; + src_pfns = service_context->block_context.hmm.src_pfns; + dst_pfns = service_context->block_context.hmm.dst_pfns; + + // Build the migration mask. + // Note that thrashing pinned pages are already accounted for in + // service_context->resident_processors. + page_mask = &uvm_hmm_gpu_fault_event->page_mask; + uvm_page_mask_copy(page_mask, + &service_context->per_processor_masks[uvm_id_value(new_residency)].new_residency); + + status = dmamap_src_sysmem_pages(va_block, + vma, + src_pfns, + dst_pfns, + region, + page_mask, + new_residency, + service_context); + if (status != NV_OK) + return status; + + // Do the alloc and copy but don't update the residency or mapping for the + // new location yet. + status = uvm_va_block_service_copy(processor_id, new_residency, va_block, va_block_retry, service_context); + if (status != NV_OK) + return status; + + // Record the destination PFNs of device private struct pages now that + // uvm_va_block_service_copy() has populated the GPU destination pages. + fill_dst_pfns(va_block, + src_pfns, + dst_pfns, + region, + page_mask, + &uvm_hmm_gpu_fault_event->same_devmem_page_mask, + new_residency); + + return status; +} + +static NV_STATUS uvm_hmm_gpu_fault_finalize_and_map(uvm_hmm_gpu_fault_event_t *uvm_hmm_gpu_fault_event) +{ + uvm_processor_id_t processor_id; + uvm_processor_id_t new_residency; + uvm_va_block_t *va_block; + uvm_va_block_retry_t *va_block_retry; + uvm_service_block_context_t *service_context; + const unsigned long *src_pfns; + unsigned long *dst_pfns; + uvm_va_block_region_t region; + uvm_page_index_t page_index; + uvm_page_mask_t *page_mask; + NV_STATUS status, tracker_status; + + processor_id = uvm_hmm_gpu_fault_event->processor_id; + new_residency = uvm_hmm_gpu_fault_event->new_residency; + va_block = uvm_hmm_gpu_fault_event->va_block; + va_block_retry = uvm_hmm_gpu_fault_event->va_block_retry; + service_context = uvm_hmm_gpu_fault_event->service_context; + src_pfns = service_context->block_context.hmm.src_pfns; + dst_pfns = service_context->block_context.hmm.dst_pfns; + region = service_context->region; + page_mask = &uvm_hmm_gpu_fault_event->page_mask; + + // There are a number of reasons why HMM will mark a page as not migrating + // even if we set a valid entry in dst_pfns[]. Mark these pages accordingly. + for_each_va_block_page_in_region_mask(page_index, page_mask, region) { + unsigned long src_pfn = src_pfns[page_index]; + + if (src_pfn & MIGRATE_PFN_MIGRATE) + continue; + + // If a device private page isn't migrating and only the GPU page table + // is being updated, continue to process it normally. + if (uvm_page_mask_test(&uvm_hmm_gpu_fault_event->same_devmem_page_mask, page_index)) + continue; + + // TODO: Bug 3900774: clean up murky mess of mask clearing. + uvm_page_mask_clear(page_mask, page_index); + clear_service_context_masks(service_context, new_residency, page_index); + } + + if (uvm_page_mask_empty(page_mask)) + status = NV_WARN_MORE_PROCESSING_REQUIRED; else + status = uvm_va_block_service_finish(processor_id, va_block, service_context); + + tracker_status = sync_page_and_chunk_state(va_block, + src_pfns, + dst_pfns, + region, + page_mask, + &uvm_hmm_gpu_fault_event->same_devmem_page_mask); + + return status == NV_OK ? tracker_status : status; +} + +NV_STATUS uvm_hmm_va_block_service_locked(uvm_processor_id_t processor_id, + uvm_processor_id_t new_residency, + uvm_va_block_t *va_block, + uvm_va_block_retry_t *va_block_retry, + uvm_service_block_context_t *service_context) +{ + struct mm_struct *mm = service_context->block_context.mm; + struct vm_area_struct *vma = service_context->block_context.hmm.vma; + uvm_va_block_region_t region = service_context->region; + uvm_hmm_gpu_fault_event_t uvm_hmm_gpu_fault_event; + struct migrate_vma *args = &service_context->block_context.hmm.migrate_vma_args; + int ret; + NV_STATUS status = NV_ERR_INVALID_ADDRESS; + + if (!mm) + return status; + + uvm_assert_mmap_lock_locked(mm); + uvm_assert_rwsem_locked(&va_block->hmm.va_space->lock); + uvm_assert_mutex_locked(&va_block->hmm.migrate_lock); + uvm_assert_mutex_locked(&va_block->lock); + UVM_ASSERT(vma); + + // If the desired destination is the CPU, try to fault in CPU pages. + if (UVM_ID_IS_CPU(new_residency)) + return hmm_block_cpu_fault_locked(processor_id, va_block, va_block_retry, service_context); + + uvm_hmm_gpu_fault_event.processor_id = processor_id; + uvm_hmm_gpu_fault_event.new_residency = new_residency; + uvm_hmm_gpu_fault_event.va_block = va_block; + uvm_hmm_gpu_fault_event.va_block_retry = va_block_retry; + uvm_hmm_gpu_fault_event.service_context = service_context; + + args->vma = vma; + args->src = service_context->block_context.hmm.src_pfns + region.first; + args->dst = service_context->block_context.hmm.dst_pfns + region.first; + args->start = uvm_va_block_region_start(va_block, region); + args->end = uvm_va_block_region_end(va_block, region) + 1; + args->flags = MIGRATE_VMA_SELECT_DEVICE_PRIVATE | MIGRATE_VMA_SELECT_SYSTEM; + args->pgmap_owner = &g_uvm_global; + args->fault_page = NULL; + + ret = migrate_vma_setup_locked(args, va_block); + UVM_ASSERT(!ret); + + // The overall process here is to migrate pages from the CPU or GPUs to the + // faulting GPU. + // This is safe because we hold the va_block lock across the calls to + // uvm_hmm_gpu_fault_alloc_and_copy(), migrate_vma_pages(), + // uvm_hmm_gpu_fault_finalize_and_map(), and migrate_vma_finalize(). + // If uvm_hmm_gpu_fault_alloc_and_copy() needs to drop the va_block + // lock, a sequence number is used to tell if an invalidate() callback + // occurred while not holding the lock. If the sequence number changes, + // all the locks need to be dropped (mm, va_space, va_block) and the whole + // uvm_va_block_service_locked() called again. Otherwise, there were no + // conflicting invalidate callbacks and our snapshots of the CPU page + // tables are accurate and can be used to DMA pages and update GPU page + // tables. TODO: Bug 3901904: there might be better ways of handling no + // page being migrated. + status = uvm_hmm_gpu_fault_alloc_and_copy(vma, &uvm_hmm_gpu_fault_event); + if (status == NV_WARN_MORE_PROCESSING_REQUIRED) { + migrate_vma_finalize(args); + + // migrate_vma_setup() might have not been able to lock/isolate any + // pages because they are swapped out or are device exclusive. + // We do know that none of the pages in the region are zero pages + // since migrate_vma_setup() would have reported that information. + // Try to make it resident in system memory and retry the migration. + status = hmm_make_resident_cpu(va_block, + service_context->block_context.hmm.vma, + service_context->block_context.hmm.src_pfns, + region, + service_context->access_type, + NULL); + return NV_WARN_MORE_PROCESSING_REQUIRED; + } + + if (status == NV_OK) { + migrate_vma_pages(args); + status = uvm_hmm_gpu_fault_finalize_and_map(&uvm_hmm_gpu_fault_event); + } + + migrate_vma_finalize(args); + + if (status == NV_WARN_NOTHING_TO_DO) status = NV_OK; - uvm_va_space_up_write(va_space); - uvm_up_write_mmap_lock(mm); - uvm_va_space_mm_or_current_release(va_space, mm); return status; } +static NV_STATUS uvm_hmm_migrate_alloc_and_copy(struct vm_area_struct *vma, + uvm_hmm_migrate_event_t *uvm_hmm_migrate_event) +{ + uvm_va_block_t *va_block; + uvm_va_block_retry_t *va_block_retry; + uvm_va_block_context_t *va_block_context; + const unsigned long *src_pfns; + unsigned long *dst_pfns; + uvm_va_block_region_t region; + uvm_processor_id_t dest_id; + uvm_page_mask_t *page_mask; + NV_STATUS status; + + va_block = uvm_hmm_migrate_event->va_block; + va_block_retry = uvm_hmm_migrate_event->va_block_retry; + va_block_context = uvm_hmm_migrate_event->va_block_context; + src_pfns = va_block_context->hmm.src_pfns; + dst_pfns = va_block_context->hmm.dst_pfns; + region = uvm_hmm_migrate_event->region; + dest_id = uvm_hmm_migrate_event->dest_id; + page_mask = &uvm_hmm_migrate_event->page_mask; + uvm_page_mask_init_from_region(page_mask, region, NULL); + uvm_page_mask_zero(&uvm_hmm_migrate_event->same_devmem_page_mask); + + uvm_assert_mutex_locked(&va_block->lock); + + if (UVM_ID_IS_CPU(dest_id)) { + status = alloc_and_copy_to_cpu(va_block, + vma, + src_pfns, + dst_pfns, + region, + page_mask, + &uvm_hmm_migrate_event->same_devmem_page_mask, + UVM_ID_INVALID, + NULL); + } + else { + status = dmamap_src_sysmem_pages(va_block, + vma, + src_pfns, + dst_pfns, + region, + page_mask, + dest_id, + NULL); + } + if (status != NV_OK) + return status; + + status = uvm_va_block_make_resident_copy(va_block, + va_block_retry, + va_block_context, + dest_id, + region, + page_mask, + NULL, + uvm_hmm_migrate_event->cause); + if (status != NV_OK) + return status; + + if (!UVM_ID_IS_CPU(dest_id)) { + // Record the destination PFNs of device private struct pages now that + // uvm_va_block_make_resident_copy() has populated the GPU destination + // pages. + fill_dst_pfns(va_block, + src_pfns, + dst_pfns, + region, + page_mask, + &uvm_hmm_migrate_event->same_devmem_page_mask, + dest_id); + } + + return status; +} + +static NV_STATUS uvm_hmm_migrate_finalize(uvm_hmm_migrate_event_t *uvm_hmm_migrate_event) +{ + uvm_va_block_t *va_block; + uvm_va_block_retry_t *va_block_retry; + uvm_va_block_context_t *va_block_context; + uvm_va_block_region_t region; + uvm_processor_id_t dest_id; + uvm_page_index_t page_index; + uvm_page_mask_t *page_mask; + const unsigned long *src_pfns; + unsigned long *dst_pfns; + + va_block = uvm_hmm_migrate_event->va_block; + va_block_retry = uvm_hmm_migrate_event->va_block_retry; + va_block_context = uvm_hmm_migrate_event->va_block_context; + region = uvm_hmm_migrate_event->region; + dest_id = uvm_hmm_migrate_event->dest_id; + page_mask = &uvm_hmm_migrate_event->page_mask; + src_pfns = va_block_context->hmm.src_pfns; + dst_pfns = va_block_context->hmm.dst_pfns; + + uvm_assert_mutex_locked(&va_block->lock); + + // There are a number of reasons why HMM will mark a page as not migrating + // even if we set a valid entry in dst_pfns[]. Mark these pages accordingly. + for_each_va_block_page_in_region_mask(page_index, page_mask, region) { + unsigned long src_pfn = src_pfns[page_index]; + + if (src_pfn & MIGRATE_PFN_MIGRATE) + continue; + + // If a device private page isn't migrating and only the GPU page table + // is being updated, continue to process it normally. + if (uvm_page_mask_test(&uvm_hmm_migrate_event->same_devmem_page_mask, page_index)) + continue; + + uvm_page_mask_clear(page_mask, page_index); + } + + uvm_va_block_make_resident_finish(va_block, va_block_context, region, page_mask); + + return sync_page_and_chunk_state(va_block, + src_pfns, + dst_pfns, + region, + page_mask, + &uvm_hmm_migrate_event->same_devmem_page_mask); +} + +static bool is_resident(uvm_va_block_t *va_block, + uvm_processor_id_t dest_id, + uvm_va_block_region_t region) +{ + if (!uvm_processor_mask_test(&va_block->resident, dest_id)) + return false; + + return uvm_page_mask_region_full(uvm_va_block_resident_mask_get(va_block, dest_id), region); +} + +// Note that migrate_vma_*() doesn't handle asynchronous migrations so the +// migration flag UVM_MIGRATE_FLAG_SKIP_CPU_MAP doesn't have an effect. +// TODO: Bug 3900785: investigate ways to implement async migration. +NV_STATUS uvm_hmm_va_block_migrate_locked(uvm_va_block_t *va_block, + uvm_va_block_retry_t *va_block_retry, + uvm_va_block_context_t *va_block_context, + uvm_processor_id_t dest_id, + uvm_va_block_region_t region, + uvm_make_resident_cause_t cause) +{ + uvm_hmm_migrate_event_t uvm_hmm_migrate_event; + struct vm_area_struct *vma = va_block_context->hmm.vma; + NvU64 start; + NvU64 end; + struct migrate_vma *args = &va_block_context->hmm.migrate_vma_args; + NV_STATUS status; + int ret; + + UVM_ASSERT(vma); + UVM_ASSERT(va_block_context->mm == vma->vm_mm); + uvm_assert_mmap_lock_locked(va_block_context->mm); + uvm_assert_rwsem_locked(&va_block->hmm.va_space->lock); + uvm_assert_mutex_locked(&va_block->hmm.migrate_lock); + uvm_assert_mutex_locked(&va_block->lock); + + start = uvm_va_block_region_start(va_block, region); + end = uvm_va_block_region_end(va_block, region); + UVM_ASSERT(vma->vm_start <= start && end < vma->vm_end); + + uvm_hmm_migrate_event.va_block = va_block; + uvm_hmm_migrate_event.va_block_retry = va_block_retry; + uvm_hmm_migrate_event.va_block_context = va_block_context; + uvm_hmm_migrate_event.region = region; + uvm_hmm_migrate_event.dest_id = dest_id; + uvm_hmm_migrate_event.cause = cause; + + args->vma = vma; + args->src = va_block_context->hmm.src_pfns + region.first; + args->dst = va_block_context->hmm.dst_pfns + region.first; + args->start = uvm_va_block_region_start(va_block, region); + args->end = uvm_va_block_region_end(va_block, region) + 1; + args->flags = UVM_ID_IS_CPU(dest_id) ? MIGRATE_VMA_SELECT_DEVICE_PRIVATE : + MIGRATE_VMA_SELECT_DEVICE_PRIVATE | MIGRATE_VMA_SELECT_SYSTEM; + args->pgmap_owner = &g_uvm_global; + args->fault_page = NULL; + + // Note that migrate_vma_setup() doesn't handle file backed or VM_SPECIAL + // VMAs so if UvmMigrate() tries to migrate such a region, -EINVAL will + // be returned and we will only try to make the pages be CPU resident. + ret = migrate_vma_setup_locked(args, va_block); + if (ret) + return hmm_make_resident_cpu(va_block, + vma, + va_block_context->hmm.src_pfns, + region, + NULL, + NULL); + + // The overall process here is to migrate pages from the CPU or GPUs to the + // destination processor. Note that block_migrate_add_mappings() handles + // updating GPU mappings after the migration. + // This is safe because we hold the va_block lock across the calls to + // uvm_hmm_migrate_alloc_and_copy(), migrate_vma_pages(), + // uvm_hmm_migrate_finalize(), migrate_vma_finalize() and + // block_migrate_add_mappings(). + // If uvm_hmm_migrate_alloc_and_copy() needs to drop the va_block + // lock, a sequence number is used to tell if an invalidate() callback + // occurred while not holding the lock. If the sequence number changes, + // all the locks need to be dropped (mm, va_space, va_block) and the whole + // uvm_hmm_va_block_migrate_locked() called again. Otherwise, there were no + // conflicting invalidate callbacks and our snapshots of the CPU page + // tables are accurate and can be used to DMA pages and update GPU page + // tables. + status = uvm_hmm_migrate_alloc_and_copy(vma, &uvm_hmm_migrate_event); + if (status == NV_WARN_MORE_PROCESSING_REQUIRED) { + uvm_processor_id_t id; + uvm_page_mask_t *page_mask; + + migrate_vma_finalize(args); + + // The CPU pages tables might contain only device private pages or + // the migrate_vma_setup() might have not been able to lock/isolate + // any pages because they are swapped out, or on another device. + // We do know that none of the pages in the region are zero pages + // since migrate_vma_setup() would have reported that information. + // Collect all the pages that need to be faulted in and made CPU + // resident, then do the hmm_range_fault() and retry. + page_mask = &va_block_context->caller_page_mask; + uvm_page_mask_init_from_region(page_mask, region, NULL); + + for_each_id_in_mask(id, &va_block->resident) { + if (!uvm_page_mask_andnot(page_mask, + page_mask, + uvm_va_block_resident_mask_get(va_block, id))) + return NV_OK; + } + + return hmm_make_resident_cpu(va_block, + vma, + va_block_context->hmm.src_pfns, + region, + NULL, + NULL); + } + + if (status == NV_OK) { + migrate_vma_pages(args); + status = uvm_hmm_migrate_finalize(&uvm_hmm_migrate_event); + } + + migrate_vma_finalize(args); + + if (status == NV_WARN_NOTHING_TO_DO) + status = NV_OK; + + return status; +} + +NV_STATUS uvm_hmm_migrate_ranges(uvm_va_space_t *va_space, + uvm_va_block_context_t *va_block_context, + NvU64 base, + NvU64 length, + uvm_processor_id_t dest_id, + uvm_migrate_mode_t mode, + uvm_tracker_t *out_tracker) +{ + struct mm_struct *mm; + uvm_va_block_t *va_block; + uvm_va_block_retry_t va_block_retry; + NvU64 addr, end, last_address; + NV_STATUS status = NV_OK; + + if (!uvm_hmm_is_enabled(va_space)) + return NV_ERR_INVALID_ADDRESS; + + mm = va_block_context->mm; + UVM_ASSERT(mm == va_space->va_space_mm.mm); + uvm_assert_mmap_lock_locked(mm); + uvm_assert_rwsem_locked(&va_space->lock); + + last_address = base + length - 1; + + for (addr = base; addr < last_address; addr = end + 1) { + struct vm_area_struct *vma; + + status = hmm_va_block_find_create(va_space, addr, false, &va_block_context->hmm.vma, &va_block); + if (status != NV_OK) + return status; + + end = va_block->end; + if (end > last_address) + end = last_address; + + vma = va_block_context->hmm.vma; + if (end > vma->vm_end - 1) + end = vma->vm_end - 1; + + status = hmm_migrate_range(va_block, + &va_block_retry, + va_block_context, + dest_id, + addr, + end, + mode, + out_tracker); + if (status != NV_OK) + break; + } + + return status; +} + +NV_STATUS uvm_hmm_va_block_evict_chunk_prep(uvm_va_block_t *va_block, + uvm_va_block_context_t *va_block_context, + uvm_gpu_chunk_t *gpu_chunk, + uvm_va_block_region_t chunk_region) +{ + uvm_thread_context_t *uvm_context = uvm_thread_context(); + unsigned long *src_pfns = va_block_context->hmm.src_pfns; + uvm_gpu_t *gpu = uvm_gpu_chunk_get_gpu(gpu_chunk); + unsigned long pfn = uvm_pmm_gpu_devmem_get_pfn(&gpu->pmm, gpu_chunk); + uvm_page_index_t page_index = chunk_region.first; + int ret; + + uvm_assert_mutex_locked(&va_block->lock); + // TODO: Bug 3368756: add support for large GPU pages. + UVM_ASSERT(uvm_va_block_region_num_pages(chunk_region) == 1); + + uvm_context->ignore_hmm_invalidate_va_block = va_block; + ret = migrate_device_range(src_pfns + page_index, pfn, uvm_va_block_region_num_pages(chunk_region)); + uvm_context->ignore_hmm_invalidate_va_block = NULL; + if (ret) + return errno_to_nv_status(ret); + + return NV_OK; +} + +// Note that the caller must initialize va_block_context->hmm.src_pfns by +// calling uvm_hmm_va_block_evict_chunk_prep() before calling this. +static NV_STATUS hmm_va_block_evict_chunks(uvm_va_block_t *va_block, + uvm_va_block_context_t *va_block_context, + const uvm_page_mask_t *pages_to_evict, + uvm_va_block_region_t region, + uvm_make_resident_cause_t cause, + bool *out_accessed_by_set) +{ + NvU64 start = uvm_va_block_region_start(va_block, region); + NvU64 end = uvm_va_block_region_end(va_block, region); + unsigned long *src_pfns = va_block_context->hmm.src_pfns; + unsigned long *dst_pfns = va_block_context->hmm.dst_pfns; + uvm_hmm_migrate_event_t uvm_hmm_migrate_event = { + .va_block = va_block, + .va_block_retry = NULL, + .va_block_context = va_block_context, + .region = region, + .dest_id = UVM_ID_CPU, + .cause = cause, + }; + uvm_page_mask_t *page_mask = &uvm_hmm_migrate_event.page_mask; + const uvm_va_policy_t *policy; + uvm_va_policy_node_t *node; + unsigned long npages; + NV_STATUS status; + + uvm_assert_mutex_locked(&va_block->lock); + + if (out_accessed_by_set) + *out_accessed_by_set = false; + + // Note that there is no VMA available when evicting HMM pages. + va_block_context->hmm.vma = NULL; + + uvm_page_mask_copy(page_mask, pages_to_evict); + + uvm_for_each_va_policy_in(policy, va_block, start, end, node, region) { + npages = uvm_va_block_region_num_pages(region); + + if (out_accessed_by_set && uvm_processor_mask_get_count(&policy->accessed_by) > 0) + *out_accessed_by_set = true; + + // Pages resident on the GPU should not have a resident page in system + // memory. + // TODO: Bug 3660922: Need to handle read duplication at some point. + UVM_ASSERT(uvm_page_mask_region_empty(&va_block->cpu.resident, region)); + + status = alloc_and_copy_to_cpu(va_block, + NULL, + src_pfns, + dst_pfns, + region, + page_mask, + NULL, + UVM_ID_INVALID, + NULL); + if (status != NV_OK) + goto err; + + status = uvm_va_block_make_resident_copy(va_block, + NULL, + va_block_context, + UVM_ID_CPU, + region, + page_mask, + NULL, + cause); + if (status != NV_OK) + goto err; + + migrate_device_pages(src_pfns + region.first, dst_pfns + region.first, npages); + + uvm_hmm_migrate_event.region = region; + + status = uvm_hmm_migrate_finalize(&uvm_hmm_migrate_event); + if (status != NV_OK) + goto err; + + migrate_device_finalize(src_pfns + region.first, dst_pfns + region.first, npages); + } + + return NV_OK; + +err: + migrate_device_finalize(src_pfns + region.first, dst_pfns + region.first, npages); + return status; +} + +NV_STATUS uvm_hmm_va_block_evict_chunks(uvm_va_block_t *va_block, + uvm_va_block_context_t *va_block_context, + const uvm_page_mask_t *pages_to_evict, + uvm_va_block_region_t region, + bool *out_accessed_by_set) +{ + return hmm_va_block_evict_chunks(va_block, + va_block_context, + pages_to_evict, + region, + UVM_MAKE_RESIDENT_CAUSE_EVICTION, + out_accessed_by_set); +} + +NV_STATUS uvm_hmm_va_block_evict_pages_from_gpu(uvm_va_block_t *va_block, + uvm_gpu_t *gpu, + uvm_va_block_context_t *va_block_context, + const uvm_page_mask_t *pages_to_evict, + uvm_va_block_region_t region) +{ + unsigned long *src_pfns = va_block_context->hmm.src_pfns; + uvm_va_block_gpu_state_t *gpu_state; + uvm_page_index_t page_index; + uvm_gpu_chunk_t *gpu_chunk; + NV_STATUS status; + + uvm_assert_mutex_locked(&va_block->lock); + + gpu_state = uvm_va_block_gpu_state_get(va_block, gpu->id); + UVM_ASSERT(gpu_state); + UVM_ASSERT(gpu_state->chunks); + + // Fill in the src_pfns[] with the ZONE_DEVICE private PFNs of the GPU. + memset(src_pfns, 0, sizeof(va_block_context->hmm.src_pfns)); + + // TODO: Bug 3368756: add support for large GPU pages. + for_each_va_block_page_in_region_mask(page_index, pages_to_evict, region) { + gpu_chunk = uvm_va_block_lookup_gpu_chunk(va_block, + gpu, + uvm_va_block_cpu_page_address(va_block, page_index)); + status = uvm_hmm_va_block_evict_chunk_prep(va_block, + va_block_context, + gpu_chunk, + uvm_va_block_region_for_page(page_index)); + if (status != NV_OK) + return status; + } + + return hmm_va_block_evict_chunks(va_block, + va_block_context, + pages_to_evict, + region, + UVM_MAKE_RESIDENT_CAUSE_API_MIGRATE, + NULL); +} + +NV_STATUS uvm_hmm_pmm_gpu_evict_pfn(unsigned long pfn) +{ + unsigned long src_pfn = 0; + unsigned long dst_pfn = 0; + struct page *dst_page; + NV_STATUS status = NV_OK; + int ret; + + ret = migrate_device_range(&src_pfn, pfn, 1); + if (ret) + return errno_to_nv_status(ret); + + if (src_pfn & MIGRATE_PFN_MIGRATE) { + // All the code for copying a vidmem page to sysmem relies on + // having a va_block. However certain combinations of mremap() + // and fork() can result in device-private pages being mapped + // in a child process without a va_block. + // + // We don't expect the above to be a common occurance so for + // now we allocate a fresh zero page when evicting without a + // va_block. However this results in child processes losing + // data so make sure we warn about it. Ideally we would just + // not migrate and SIGBUS the child if it tries to access the + // page. However that would prevent unloading of the driver so + // we're stuck with this until we fix the problem. + // TODO: Bug 3902536: add code to migrate GPU memory without having a + // va_block. + WARN_ON(1); + dst_page = alloc_page(GFP_HIGHUSER_MOVABLE | __GFP_ZERO); + if (!dst_page) { + status = NV_ERR_NO_MEMORY; + goto out; + } + + lock_page(dst_page); + dst_pfn = migrate_pfn(page_to_pfn(dst_page)); + + migrate_device_pages(&src_pfn, &dst_pfn, 1); + } + +out: + migrate_device_finalize(&src_pfn, &dst_pfn, 1); + + return status; +} + +// The routines below are all for UVM-HMM tests. + +NV_STATUS uvm_hmm_va_block_range_bounds(uvm_va_space_t *va_space, + struct mm_struct *mm, + NvU64 lookup_address, + NvU64 *startp, + NvU64 *endp, + UVM_TEST_VA_RESIDENCY_INFO_PARAMS *params) +{ + struct vm_area_struct *vma; + NvU64 start; + NvU64 end; + + if (!uvm_hmm_is_enabled(va_space) || !mm) + return NV_ERR_INVALID_ADDRESS; + + uvm_assert_mmap_lock_locked(mm); + uvm_assert_rwsem_locked(&va_space->lock); + + // The VMA might have changed while not holding mmap_lock so check it. + vma = find_vma(mm, lookup_address); + if (!uvm_hmm_vma_is_valid(vma, lookup_address, false)) + return NV_ERR_INVALID_ADDRESS; + + // Since managed VA ranges don't cover more than one VMA, return only the + // intersecting range of the VA block and VMA. + start = UVM_VA_BLOCK_ALIGN_DOWN(lookup_address); + end = start + UVM_VA_BLOCK_SIZE - 1; + if (start < vma->vm_start) + start = vma->vm_start; + if (end > vma->vm_end - 1) + end = vma->vm_end - 1; + + *startp = start; + *endp = end; + + if (params) { + uvm_va_space_processor_uuid(va_space, ¶ms->resident_on[0], UVM_ID_CPU); + params->resident_physical_size[0] = PAGE_SIZE; + params->resident_on_count = 1; + + uvm_va_space_processor_uuid(va_space, ¶ms->mapped_on[0], UVM_ID_CPU); + params->mapping_type[0] = (vma->vm_flags & VM_WRITE) ? + UVM_PROT_READ_WRITE_ATOMIC : UVM_PROT_READ_ONLY; + params->page_size[0] = PAGE_SIZE; + params->mapped_on_count = 1; + + uvm_va_space_processor_uuid(va_space, ¶ms->populated_on[0], UVM_ID_CPU); + params->populated_on_count = 1; + } + + return NV_OK; +} + +NV_STATUS uvm_hmm_va_block_update_residency_info(uvm_va_block_t *va_block, + struct mm_struct *mm, + NvU64 lookup_address, + bool populate) +{ + uvm_va_space_t *va_space = va_block->hmm.va_space; + struct vm_area_struct *vma; + struct hmm_range range; + uvm_va_block_region_t region; + unsigned long pfn; + NvU64 end; + int ret; + NV_STATUS status; + + if (!uvm_hmm_is_enabled(va_space) || !mm) + return NV_ERR_INVALID_ADDRESS; + + uvm_assert_mmap_lock_locked(mm); + uvm_assert_rwsem_locked(&va_space->lock); + + // The VMA might have changed while not holding mmap_lock so check it. + vma = find_vma(mm, lookup_address); + if (!uvm_hmm_vma_is_valid(vma, lookup_address, false)) + return NV_ERR_INVALID_ADDRESS; + + end = lookup_address + PAGE_SIZE; + region = uvm_va_block_region_from_start_end(va_block, lookup_address, end - 1); + + range.notifier = &va_block->hmm.notifier; + range.start = lookup_address; + range.end = end; + range.hmm_pfns = &pfn; + range.default_flags = 0; + range.pfn_flags_mask = 0; + range.dev_private_owner = &g_uvm_global; + + if (populate) { + range.default_flags = HMM_PFN_REQ_FAULT; + if (vma->vm_flags & VM_WRITE) + range.default_flags |= HMM_PFN_REQ_WRITE; + } + + uvm_hmm_migrate_begin_wait(va_block); + + while (true) { + range.notifier_seq = mmu_interval_read_begin(range.notifier); + ret = hmm_range_fault(&range); + if (ret == -EBUSY) + continue; + if (ret) { + uvm_hmm_migrate_finish(va_block); + return errno_to_nv_status(ret); + } + + uvm_mutex_lock(&va_block->lock); + + if (!mmu_interval_read_retry(range.notifier, range.notifier_seq)) + break; + + uvm_mutex_unlock(&va_block->lock); + } + + // Update the va_block CPU state based on the snapshot. + // Note that we have to adjust the pfns address since it will be indexed + // by region.first. + status = populate_region(va_block, &pfn - region.first, region, NULL); + + uvm_mutex_unlock(&va_block->lock); + uvm_hmm_migrate_finish(va_block); + + return NV_OK; +} + +NV_STATUS uvm_test_split_invalidate_delay(UVM_TEST_SPLIT_INVALIDATE_DELAY_PARAMS *params, struct file *filp) +{ + uvm_va_space_t *va_space = uvm_va_space_get(filp); + + atomic64_set(&va_space->test.split_invalidate_delay_us, params->delay_us); + + return NV_OK; +} + NV_STATUS uvm_hmm_va_range_info(uvm_va_space_t *va_space, struct mm_struct *mm, UVM_TEST_VA_RANGE_INFO_PARAMS *params) { uvm_range_tree_node_t *tree_node; - uvm_va_policy_node_t *node; + const uvm_va_policy_node_t *node; struct vm_area_struct *vma; uvm_va_block_t *va_block; @@ -1090,7 +3591,18 @@ UVM_ASSERT(va_block_context->mm == vma->vm_mm); uvm_assert_mmap_lock_locked(va_block_context->mm); - return !vma_is_anonymous(vma); + // TODO: Bug 4050579: Remove this when swap cached pages can be migrated. + if (va_block_context->hmm.swap_cached) + return true; + + // migrate_vma_setup() can't migrate VM_SPECIAL so we have to force GPU + // remote mapping. + // TODO: Bug 3660968: add support for file-backed migrations. + // TODO: Bug 3368756: add support for transparent huge page migrations. + return !vma_is_anonymous(vma) || + (vma->vm_flags & VM_SPECIAL) || + vma_is_dax(vma) || + is_vm_hugetlb_page(vma); } #endif // UVM_IS_CONFIG_HMM() diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/kernel-open/nvidia-uvm/uvm_hmm.h nvidia-open-gpu-kernel-modules-535.161.08/kernel-open/nvidia-uvm/uvm_hmm.h --- nvidia-open-gpu-kernel-modules-525.147.05/kernel-open/nvidia-uvm/uvm_hmm.h 2023-10-25 20:33:41.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/kernel-open/nvidia-uvm/uvm_hmm.h 2024-03-05 22:26:04.000000000 +0000 @@ -1,5 +1,5 @@ /******************************************************************************* - Copyright (c) 2016-2022 NVIDIA Corporation + Copyright (c) 2016-2023 NVIDIA Corporation Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation files (the "Software"), to @@ -37,19 +37,10 @@ // This stores pointers to uvm_va_block_t for HMM blocks. uvm_range_tree_t blocks; uvm_mutex_t blocks_lock; - - // TODO: Bug 3351822: [UVM-HMM] Remove temporary testing changes. - // This flag is set true by default for each va_space so most processes - // don't see partially implemented UVM-HMM behavior but can be enabled by - // test code for a given va_space so the test process can do some interim - // testing. It needs to be a separate flag instead of modifying - // uvm_disable_hmm or va_space->flags since those are user inputs and are - // visible/checked by test code. - // Remove this when UVM-HMM is fully integrated into chips_a. - bool disable; } uvm_hmm_va_space_t; #if UVM_IS_CONFIG_HMM() + // Tells whether HMM is enabled for the given va_space. // If it is not enabled, all of the functions below are no-ops. bool uvm_hmm_is_enabled(uvm_va_space_t *va_space); @@ -58,21 +49,27 @@ bool uvm_hmm_is_enabled_system_wide(void); // Initialize HMM for the given the va_space. - // Locking: the va_space->va_space_mm.mm mmap_lock must be write locked - // and the va_space lock must be held in write mode. - NV_STATUS uvm_hmm_va_space_initialize(uvm_va_space_t *va_space); - - // Initialize HMM for the given the va_space for testing. - // Bug 1750144: UVM: Add HMM (Heterogeneous Memory Management) support to - // the UVM driver. Remove this when enough HMM functionality is implemented. - // Locking: the va_space->va_space_mm.mm mmap_lock must be write locked - // and the va_space lock must be held in write mode. - NV_STATUS uvm_hmm_va_space_initialize_test(uvm_va_space_t *va_space); + void uvm_hmm_va_space_initialize(uvm_va_space_t *va_space); // Destroy any HMM state for the given the va_space. // Locking: va_space lock must be held in write mode. void uvm_hmm_va_space_destroy(uvm_va_space_t *va_space); + // Unmap all page tables in this VA space which map memory owned by this + // GPU. Any memory still resident on this GPU will be evicted to system + // memory. Note that 'mm' can be NULL (e.g., when closing the UVM file) + // in which case any GPU memory is simply freed. + // Locking: if mm is not NULL, the caller must hold mm->mmap_lock in at + // least read mode and the va_space lock must be held in write mode. + void uvm_hmm_unregister_gpu(uvm_va_space_t *va_space, uvm_gpu_t *gpu, struct mm_struct *mm); + + // Destroy the VA space's mappings on the GPU, if it has any. + // Locking: if mm is not NULL, the caller must hold mm->mmap_lock in at + // least read mode and the va_space lock must be held in write mode. + void uvm_hmm_remove_gpu_va_space(uvm_va_space_t *va_space, + uvm_gpu_va_space_t *gpu_va_space, + struct mm_struct *mm); + // Find an existing HMM va_block. // This function can be called without having retained and locked the mm, // but in that case, the only allowed operations on the returned block are @@ -91,32 +88,51 @@ // address 'addr' or the VMA does not have at least PROT_READ permission. // The caller is also responsible for checking that there is no UVM // va_range covering the given address before calling this function. - // If va_block_context is not NULL, the VMA is cached in - // va_block_context->hmm.vma. + // The VMA is returned in vma_out if it's not NULL. // Locking: This function must be called with mm retained and locked for // at least read and the va_space lock at least for read. NV_STATUS uvm_hmm_va_block_find_create(uvm_va_space_t *va_space, NvU64 addr, - uvm_va_block_context_t *va_block_context, + struct vm_area_struct **vma_out, uvm_va_block_t **va_block_ptr); - // Find the VMA for the given address and set va_block_context->hmm.vma. - // Return NV_ERR_INVALID_ADDRESS if va_block_context->mm is NULL or there - // is no VMA associated with the address 'addr' or the VMA does not have at - // least PROT_READ permission. + // Find the VMA for the given address and return it in vma_out. Return + // NV_ERR_INVALID_ADDRESS if mm is NULL or there is no VMA associated with + // the address 'addr' or the VMA does not have at least PROT_READ + // permission. // Locking: This function must be called with mm retained and locked for // at least read or mm equal to NULL. - NV_STATUS uvm_hmm_find_vma(uvm_va_block_context_t *va_block_context, NvU64 addr); + NV_STATUS uvm_hmm_find_vma(struct mm_struct *mm, struct vm_area_struct **vma_out, NvU64 addr); - // If va_block is a HMM va_block, check that va_block_context->hmm.vma is - // not NULL and covers the given region. This always returns true and is - // intended to only be used with UVM_ASSERT(). + // If va_block is a HMM va_block, check that vma is not NULL and covers the + // given region. This always returns true and is intended to only be used + // with UVM_ASSERT(). // Locking: This function must be called with the va_block lock held and if - // va_block is a HMM block, va_block_context->mm must be retained and - // locked for at least read. - bool uvm_hmm_va_block_context_vma_is_valid(uvm_va_block_t *va_block, - uvm_va_block_context_t *va_block_context, - uvm_va_block_region_t region); + // va_block is a HMM block, va_space->va_space_mm.mm->mmap_lock must be + // retained and locked for at least read. + bool uvm_hmm_check_context_vma_is_valid(uvm_va_block_t *va_block, + struct vm_area_struct *vma, + uvm_va_block_region_t region); + + // Initialize the HMM portion of the service_context. + // This should be called one time before any retry loops calling + // uvm_va_block_service_locked(). + void uvm_hmm_service_context_init(uvm_service_block_context_t *service_context); + + // Begin a migration critical section. When calling into the kernel it is + // sometimes necessary to drop the va_block lock. This function returns + // NV_OK when no other thread has started a migration critical section. + // Otherwise, it returns NV_ERR_BUSY_RETRY and threads should then retry + // this function to begin a critical section. + // Locking: va_block lock must not be held. + NV_STATUS uvm_hmm_migrate_begin(uvm_va_block_t *va_block); + + // Same as uvm_hmm_migrate_begin() but waits if required before beginning a + // critical section. + void uvm_hmm_migrate_begin_wait(uvm_va_block_t *va_block); + + // Finish a migration critical section. + void uvm_hmm_migrate_finish(uvm_va_block_t *va_block); // Find or create a HMM va_block and mark it so the next va_block split // will fail for testing purposes. @@ -168,7 +184,8 @@ NV_STATUS uvm_hmm_set_preferred_location(uvm_va_space_t *va_space, uvm_processor_id_t preferred_location, NvU64 base, - NvU64 last_address); + NvU64 last_address, + uvm_tracker_t *out_tracker); // Set the accessed by policy for the given range. This also tries to // map the range. Note that 'last_address' is inclusive. @@ -178,7 +195,17 @@ uvm_processor_id_t processor_id, bool set_bit, NvU64 base, - NvU64 last_address); + NvU64 last_address, + uvm_tracker_t *out_tracker); + + // Deferred work item to reestablish accessed by mappings after eviction. On + // GPUs with access counters enabled, the evicted GPU will also get remote + // mappings. + // Locking: the va_space->va_space_mm.mm mmap_lock must be locked + // and the va_space lock must be held in at least read mode. + void uvm_hmm_block_add_eviction_mappings(uvm_va_space_t *va_space, + uvm_va_block_t *va_block, + uvm_va_block_context_t *block_context); // Set the read duplication policy for the given range. // Note that 'last_address' is inclusive. @@ -195,31 +222,29 @@ return NV_OK; } - // This function assigns va_block_context->policy to the policy covering - // the given address 'addr' and assigns the ending address '*endp' to the - // minimum of va_block->end, va_block_context->hmm.vma->vm_end - 1, and the - // ending address of the policy range. Note that va_block_context->hmm.vma - // is expected to be initialized before calling this function. - // Locking: This function must be called with - // va_block_context->hmm.vma->vm_mm retained and locked for least read and - // the va_block lock held. - void uvm_hmm_find_policy_end(uvm_va_block_t *va_block, - uvm_va_block_context_t *va_block_context, - unsigned long addr, - NvU64 *endp); - - // This function finds the VMA for the page index 'page_index' and assigns - // it to va_block_context->vma, sets va_block_context->policy to the policy - // covering the given address, and sets the ending page range '*outerp' - // to the minimum of *outerp, va_block_context->hmm.vma->vm_end - 1, the - // ending address of the policy range, and va_block->end. - // Return NV_ERR_INVALID_ADDRESS if no VMA is found; otherwise, NV_OK. - // Locking: This function must be called with - // va_block_context->hmm.vma->vm_mm retained and locked for least read and - // the va_block lock held. + // This function returns the policy covering the given address 'addr' and + // assigns the ending address '*endp' to the minimum of va_block->end, + // vma->vm_end - 1, and the ending address of the policy range. Locking: + // This function must be called with vma->vm_mm retained and locked for at + // least read and the va_block and va_space lock held. + const uvm_va_policy_t *uvm_hmm_find_policy_end(uvm_va_block_t *va_block, + struct vm_area_struct *vma, + unsigned long addr, + NvU64 *endp); + + // This function finds the VMA for the page index 'page_index' and returns + // it in vma_out which must not be NULL. Returns the policy covering the + // given address, and sets the ending page range '*outerp' to the minimum of + // *outerp, vma->vm_end - 1, the ending address of the policy range, and + // va_block->end. + // Return NV_ERR_INVALID_ADDRESS if no VMA is found; otherwise sets *vma + // and returns NV_OK. + // Locking: This function must be called with mm retained and locked for at + // least read and the va_block and va_space lock held. NV_STATUS uvm_hmm_find_policy_vma_and_outer(uvm_va_block_t *va_block, - uvm_va_block_context_t *va_block_context, + struct vm_area_struct **vma, uvm_page_index_t page_index, + const uvm_va_policy_t **policy, uvm_page_index_t *outerp); // Clear thrashing policy information from all HMM va_blocks. @@ -228,27 +253,126 @@ // Return the expanded region around 'address' limited to the intersection // of va_block start/end, vma start/end, and policy start/end. - // va_block_context must not be NULL, va_block_context->hmm.vma must be - // valid (this is usually set by uvm_hmm_va_block_find_create()), and - // va_block_context->policy must be valid. - // Locking: the caller must hold mm->mmap_lock in at least read mode, the - // va_space lock must be held in at least read mode, and the va_block lock - // held. + // Locking: the caller must hold va_space->va_space_mm.mm->mmap_lock in at + // least read mode, the va_space lock must be held in at least read mode, + // and the va_block lock held. uvm_va_block_region_t uvm_hmm_get_prefetch_region(uvm_va_block_t *va_block, - uvm_va_block_context_t *va_block_context, + struct vm_area_struct *vma, + const uvm_va_policy_t *policy, NvU64 address); // Return the logical protection allowed of a HMM va_block for the page at - // the given address. - // va_block_context must not be NULL and va_block_context->hmm.vma must be - // valid (this is usually set by uvm_hmm_va_block_find_create()). - // Locking: the caller must hold va_block_context->mm mmap_lock in at least - // read mode. + // the given address within the vma which must be valid. This is usually + // obtained from uvm_hmm_va_block_find_create()). + // Locking: the caller must hold va_space->va_space_mm.mm mmap_lock in at + // least read mode. uvm_prot_t uvm_hmm_compute_logical_prot(uvm_va_block_t *va_block, - uvm_va_block_context_t *va_block_context, + struct vm_area_struct *vma, NvU64 addr); - NV_STATUS uvm_test_hmm_init(UVM_TEST_HMM_INIT_PARAMS *params, struct file *filp); + // This is called to service a GPU fault. + // Locking: the va_space->va_space_mm.mm mmap_lock must be locked, + // the va_space read lock must be held, and the va_block lock held. + NV_STATUS uvm_hmm_va_block_service_locked(uvm_processor_id_t processor_id, + uvm_processor_id_t new_residency, + uvm_va_block_t *va_block, + uvm_va_block_retry_t *va_block_retry, + uvm_service_block_context_t *service_context); + + // This is called to migrate a region within a HMM va_block. + // va_block_context must not be NULL and va_block_context->hmm.vma + // must be valid. + // Locking: the va_space->va_space_mm.mm must be retained, mmap_lock must be + // locked, and the va_block lock held. + NV_STATUS uvm_hmm_va_block_migrate_locked(uvm_va_block_t *va_block, + uvm_va_block_retry_t *va_block_retry, + uvm_va_block_context_t *va_block_context, + uvm_processor_id_t dest_id, + uvm_va_block_region_t region, + uvm_make_resident_cause_t cause); + + // This is called to migrate an address range of HMM allocations via + // UvmMigrate(). + // + // va_block_context must not be NULL. The caller is not required to set + // va_block_context->hmm.vma. + // + // Locking: the va_space->va_space_mm.mm mmap_lock must be locked and + // the va_space read lock must be held. + NV_STATUS uvm_hmm_migrate_ranges(uvm_va_space_t *va_space, + uvm_va_block_context_t *va_block_context, + NvU64 base, + NvU64 length, + uvm_processor_id_t dest_id, + uvm_migrate_mode_t mode, + uvm_tracker_t *out_tracker); + + // Evicts all va_blocks in the va_space to the CPU. Unlike the + // other va_block eviction functions this is based on virtual + // address and therefore takes mmap_lock for read. + void uvm_hmm_evict_va_blocks(uvm_va_space_t *va_space); + + // This sets the va_block_context->hmm.src_pfns[] to the ZONE_DEVICE private + // PFN for the GPU chunk memory. + NV_STATUS uvm_hmm_va_block_evict_chunk_prep(uvm_va_block_t *va_block, + uvm_va_block_context_t *va_block_context, + uvm_gpu_chunk_t *gpu_chunk, + uvm_va_block_region_t chunk_region); + + // Migrate pages to system memory for the given page mask. + // Note that the mmap lock is not held and there is no MM retained. + // This must be called after uvm_hmm_va_block_evict_chunk_prep() has + // initialized va_block_context->hmm.src_pfns[] for the source GPU physical + // PFNs being migrated. Note that the input mask 'pages_to_evict' can be + // modified. If any of the evicted pages has the accessed by policy set, + // then record that by setting out_accessed_by_set. + // Locking: the va_block lock must be locked. + NV_STATUS uvm_hmm_va_block_evict_chunks(uvm_va_block_t *va_block, + uvm_va_block_context_t *va_block_context, + const uvm_page_mask_t *pages_to_evict, + uvm_va_block_region_t region, + bool *out_accessed_by_set); + + // Migrate pages from the given GPU to system memory for the given page + // mask and region. va_block_context must not be NULL. + // Note that the mmap lock is not held and there is no MM retained. + // Locking: the va_block lock must be locked. + NV_STATUS uvm_hmm_va_block_evict_pages_from_gpu(uvm_va_block_t *va_block, + uvm_gpu_t *gpu, + uvm_va_block_context_t *va_block_context, + const uvm_page_mask_t *pages_to_evict, + uvm_va_block_region_t region); + + // Migrate a GPU device-private page to system memory. This is + // called to remove CPU page table references to device private + // struct pages for the given GPU after all other references in + // va_blocks have been released and the GPU is in the process of + // being removed/torn down. Note that there is no mm, VMA, + // va_block or any user channel activity on this GPU. + NV_STATUS uvm_hmm_pmm_gpu_evict_pfn(unsigned long pfn); + + // This returns what would be the intersection of va_block start/end and + // VMA start/end-1 for the given 'lookup_address' if + // uvm_hmm_va_block_find_create() was called. + // Locking: the caller must hold mm->mmap_lock in at least read mode and + // the va_space lock must be held in at least read mode. + NV_STATUS uvm_hmm_va_block_range_bounds(uvm_va_space_t *va_space, + struct mm_struct *mm, + NvU64 lookup_address, + NvU64 *startp, + NvU64 *endp, + UVM_TEST_VA_RESIDENCY_INFO_PARAMS *params); + + // This updates the HMM va_block CPU residency information for a single + // page at 'lookup_address' by calling hmm_range_fault(). If 'populate' is + // true, the CPU page will be faulted in read/write or read-only + // (depending on the permission of the underlying VMA at lookup_address). + // Locking: the caller must hold mm->mmap_lock in at least read mode and + // the va_space lock must be held in at least read mode. + NV_STATUS uvm_hmm_va_block_update_residency_info(uvm_va_block_t *va_block, + struct mm_struct *mm, + NvU64 lookup_address, + bool populate); NV_STATUS uvm_test_split_invalidate_delay(UVM_TEST_SPLIT_INVALIDATE_DELAY_PARAMS *params, struct file *filp); @@ -280,17 +404,21 @@ return false; } - static NV_STATUS uvm_hmm_va_space_initialize(uvm_va_space_t *va_space) + static void uvm_hmm_va_space_initialize(uvm_va_space_t *va_space) { - return NV_OK; } - static NV_STATUS uvm_hmm_va_space_initialize_test(uvm_va_space_t *va_space) + static void uvm_hmm_va_space_destroy(uvm_va_space_t *va_space) { - return NV_WARN_NOTHING_TO_DO; } - static void uvm_hmm_va_space_destroy(uvm_va_space_t *va_space) + static void uvm_hmm_unregister_gpu(uvm_va_space_t *va_space, uvm_gpu_t *gpu, struct mm_struct *mm) + { + } + + static void uvm_hmm_remove_gpu_va_space(uvm_va_space_t *va_space, + uvm_gpu_va_space_t *gpu_va_space, + struct mm_struct *mm) { } @@ -303,24 +431,41 @@ static NV_STATUS uvm_hmm_va_block_find_create(uvm_va_space_t *va_space, NvU64 addr, - uvm_va_block_context_t *va_block_context, + struct vm_area_struct **vma, uvm_va_block_t **va_block_ptr) { return NV_ERR_INVALID_ADDRESS; } - static NV_STATUS uvm_hmm_find_vma(uvm_va_block_context_t *va_block_context, NvU64 addr) + static NV_STATUS uvm_hmm_find_vma(struct mm_struct *mm, struct vm_area_struct **vma, NvU64 addr) { return NV_OK; } - static bool uvm_hmm_va_block_context_vma_is_valid(uvm_va_block_t *va_block, - uvm_va_block_context_t *va_block_context, - uvm_va_block_region_t region) + static bool uvm_hmm_check_context_vma_is_valid(uvm_va_block_t *va_block, + struct vm_area_struct *vma, + uvm_va_block_region_t region) { return true; } + static void uvm_hmm_service_context_init(uvm_service_block_context_t *service_context) + { + } + + static NV_STATUS uvm_hmm_migrate_begin(uvm_va_block_t *va_block) + { + return NV_OK; + } + + static void uvm_hmm_migrate_begin_wait(uvm_va_block_t *va_block) + { + } + + static void uvm_hmm_migrate_finish(uvm_va_block_t *va_block) + { + } + static NV_STATUS uvm_hmm_test_va_block_inject_split_error(uvm_va_space_t *va_space, NvU64 addr) { return NV_ERR_INVALID_ADDRESS; @@ -349,7 +494,8 @@ static NV_STATUS uvm_hmm_set_preferred_location(uvm_va_space_t *va_space, uvm_processor_id_t preferred_location, NvU64 base, - NvU64 last_address) + NvU64 last_address, + uvm_tracker_t *out_tracker) { return NV_ERR_INVALID_ADDRESS; } @@ -358,11 +504,18 @@ uvm_processor_id_t processor_id, bool set_bit, NvU64 base, - NvU64 last_address) + NvU64 last_address, + uvm_tracker_t *out_tracker) { return NV_ERR_INVALID_ADDRESS; } + static void uvm_hmm_block_add_eviction_mappings(uvm_va_space_t *va_space, + uvm_va_block_t *va_block, + uvm_va_block_context_t *block_context) + { + } + static NV_STATUS uvm_hmm_set_read_duplication(uvm_va_space_t *va_space, uvm_read_duplication_policy_t new_policy, NvU64 base, @@ -371,16 +524,19 @@ return NV_ERR_INVALID_ADDRESS; } - static void uvm_hmm_find_policy_end(uvm_va_block_t *va_block, - uvm_va_block_context_t *va_block_context, - unsigned long addr, - NvU64 *endp) + static const uvm_va_policy_t *uvm_hmm_find_policy_end(uvm_va_block_t *va_block, + struct vm_area_struct *vma, + unsigned long addr, + NvU64 *endp) { + UVM_ASSERT(0); + return NULL; } static NV_STATUS uvm_hmm_find_policy_vma_and_outer(uvm_va_block_t *va_block, - uvm_va_block_context_t *va_block_context, + struct vm_area_struct **vma, uvm_page_index_t page_index, + const uvm_va_policy_t **policy, uvm_page_index_t *outerp) { return NV_OK; @@ -392,22 +548,101 @@ } static uvm_va_block_region_t uvm_hmm_get_prefetch_region(uvm_va_block_t *va_block, - uvm_va_block_context_t *va_block_context, + struct vm_area_struct *vma, + const uvm_va_policy_t *policy, NvU64 address) { return (uvm_va_block_region_t){}; } static uvm_prot_t uvm_hmm_compute_logical_prot(uvm_va_block_t *va_block, - uvm_va_block_context_t *va_block_context, + struct vm_area_struct *vma, NvU64 addr) { return UVM_PROT_NONE; } - static NV_STATUS uvm_test_hmm_init(UVM_TEST_HMM_INIT_PARAMS *params, struct file *filp) + static NV_STATUS uvm_hmm_va_block_service_locked(uvm_processor_id_t processor_id, + uvm_processor_id_t new_residency, + uvm_va_block_t *va_block, + uvm_va_block_retry_t *va_block_retry, + uvm_service_block_context_t *service_context) + { + return NV_ERR_INVALID_ADDRESS; + } + + static NV_STATUS uvm_hmm_va_block_migrate_locked(uvm_va_block_t *va_block, + uvm_va_block_retry_t *va_block_retry, + uvm_va_block_context_t *va_block_context, + uvm_processor_id_t dest_id, + uvm_va_block_region_t region, + uvm_make_resident_cause_t cause) + { + return NV_ERR_INVALID_ADDRESS; + } + + static NV_STATUS uvm_hmm_migrate_ranges(uvm_va_space_t *va_space, + uvm_va_block_context_t *va_block_context, + NvU64 base, + NvU64 length, + uvm_processor_id_t dest_id, + uvm_migrate_mode_t mode, + uvm_tracker_t *out_tracker) + { + return NV_ERR_INVALID_ADDRESS; + } + + static void uvm_hmm_evict_va_blocks(uvm_va_space_t *va_space) { - return NV_WARN_NOTHING_TO_DO; + } + + static NV_STATUS uvm_hmm_va_block_evict_chunk_prep(uvm_va_block_t *va_block, + uvm_va_block_context_t *va_block_context, + uvm_gpu_chunk_t *gpu_chunk, + uvm_va_block_region_t chunk_region) + { + return NV_OK; + } + + static NV_STATUS uvm_hmm_va_block_evict_chunks(uvm_va_block_t *va_block, + uvm_va_block_context_t *va_block_context, + const uvm_page_mask_t *pages_to_evict, + uvm_va_block_region_t region, + bool *out_accessed_by_set) + { + return NV_OK; + } + + static NV_STATUS uvm_hmm_va_block_evict_pages_from_gpu(uvm_va_block_t *va_block, + uvm_gpu_t *gpu, + uvm_va_block_context_t *va_block_context, + const uvm_page_mask_t *pages_to_evict, + uvm_va_block_region_t region) + { + return NV_OK; + } + + static NV_STATUS uvm_hmm_pmm_gpu_evict_pfn(unsigned long pfn) + { + return NV_OK; + } + + static NV_STATUS uvm_hmm_va_block_range_bounds(uvm_va_space_t *va_space, + struct mm_struct *mm, + NvU64 lookup_address, + NvU64 *startp, + NvU64 *endp, + UVM_TEST_VA_RESIDENCY_INFO_PARAMS *params) + { + return NV_ERR_INVALID_ADDRESS; + } + + static NV_STATUS uvm_hmm_va_block_update_residency_info(uvm_va_block_t *va_block, + struct mm_struct *mm, + NvU64 lookup_address, + bool populate) + { + return NV_ERR_INVALID_ADDRESS; } static NV_STATUS uvm_test_split_invalidate_delay(UVM_TEST_SPLIT_INVALIDATE_DELAY_PARAMS *params, diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/kernel-open/nvidia-uvm/uvm_hmm_sanity_test.c nvidia-open-gpu-kernel-modules-535.161.08/kernel-open/nvidia-uvm/uvm_hmm_sanity_test.c --- nvidia-open-gpu-kernel-modules-525.147.05/kernel-open/nvidia-uvm/uvm_hmm_sanity_test.c 2023-10-25 20:33:42.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/kernel-open/nvidia-uvm/uvm_hmm_sanity_test.c 1970-01-01 00:00:00.000000000 +0000 @@ -1,90 +0,0 @@ -/******************************************************************************* - Copyright (c) 2021-2022 NVIDIA Corporation - - Permission is hereby granted, free of charge, to any person obtaining a copy - of this software and associated documentation files (the "Software"), to - deal in the Software without restriction, including without limitation the - rights to use, copy, modify, merge, publish, distribute, sublicense, and/or - sell copies of the Software, and to permit persons to whom the Software is - furnished to do so, subject to the following conditions: - - The above copyright notice and this permission notice shall be - included in all copies or substantial portions of the Software. - - THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER - DEALINGS IN THE SOFTWARE. - -*******************************************************************************/ - -#include "uvm_common.h" -#include "uvm_linux.h" -#include "uvm_test.h" -#include "uvm_va_space.h" -#include "uvm_va_range.h" -#include "uvm_hmm.h" - -NV_STATUS uvm_test_hmm_sanity(UVM_TEST_HMM_SANITY_PARAMS *params, struct file *filp) -{ - uvm_va_space_t *va_space = uvm_va_space_get(filp); - struct mm_struct *mm; - uvm_va_block_t *hmm_block = NULL; - NV_STATUS status; - - mm = uvm_va_space_mm_or_current_retain(va_space); - if (!mm) - return NV_WARN_NOTHING_TO_DO; - - uvm_down_write_mmap_lock(mm); - uvm_va_space_down_write(va_space); - - // TODO: Bug 3351822: [UVM-HMM] Remove temporary testing changes. - // By default, HMM is enabled system wide but disabled per va_space. - // This will initialize the va_space for HMM. - status = uvm_hmm_va_space_initialize_test(va_space); - if (status != NV_OK) - goto out; - - uvm_va_space_up_write(va_space); - uvm_up_write_mmap_lock(mm); - - uvm_down_read_mmap_lock(mm); - uvm_va_space_down_read(va_space); - - // Try to create an HMM va_block to virtual address zero (NULL). - // It should fail. There should be no VMA but a va_block for range - // [0x0 0x1fffff] is possible. - status = uvm_hmm_va_block_find_create(va_space, 0UL, NULL, &hmm_block); - TEST_CHECK_GOTO(status == NV_ERR_INVALID_ADDRESS, done); - - // Try to create an HMM va_block which overlaps a managed block. - // It should fail. - status = uvm_hmm_va_block_find_create(va_space, params->uvm_address, NULL, &hmm_block); - TEST_CHECK_GOTO(status == NV_ERR_INVALID_ADDRESS, done); - - // Try to create an HMM va_block; it should succeed. - status = uvm_hmm_va_block_find_create(va_space, params->hmm_address, NULL, &hmm_block); - TEST_CHECK_GOTO(status == NV_OK, done); - - // Try to find an existing HMM va_block; it should succeed. - status = uvm_hmm_va_block_find(va_space, params->hmm_address, &hmm_block); - TEST_CHECK_GOTO(status == NV_OK, done); - -done: - uvm_va_space_up_read(va_space); - uvm_up_read_mmap_lock(mm); - uvm_va_space_mm_or_current_release(va_space, mm); - - return status; - -out: - uvm_va_space_up_write(va_space); - uvm_up_write_mmap_lock(mm); - uvm_va_space_mm_or_current_release(va_space, mm); - - return status; -} diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/kernel-open/nvidia-uvm/uvm_hopper.c nvidia-open-gpu-kernel-modules-535.161.08/kernel-open/nvidia-uvm/uvm_hopper.c --- nvidia-open-gpu-kernel-modules-525.147.05/kernel-open/nvidia-uvm/uvm_hopper.c 2023-10-25 20:33:26.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/kernel-open/nvidia-uvm/uvm_hopper.c 2024-03-05 22:25:57.000000000 +0000 @@ -49,12 +49,23 @@ // A single top level PDE on Hopper covers 64 PB and that's the minimum // size that can be used. parent_gpu->rm_va_base = 0; - parent_gpu->rm_va_size = 64ull * 1024 * 1024 * 1024 * 1024 * 1024; + parent_gpu->rm_va_size = 64 * UVM_SIZE_1PB; - parent_gpu->uvm_mem_va_base = parent_gpu->rm_va_size + 384ull * 1024 * 1024 * 1024 * 1024; + parent_gpu->uvm_mem_va_base = parent_gpu->rm_va_size + 384 * UVM_SIZE_1TB; parent_gpu->uvm_mem_va_size = UVM_MEM_VA_SIZE; - parent_gpu->peer_copy_mode = g_uvm_global.peer_copy_mode; + // See uvm_mmu.h for mapping placement + parent_gpu->flat_vidmem_va_base = (64 * UVM_SIZE_1PB) + (8 * UVM_SIZE_1TB); + + // Physical CE writes to vidmem are non-coherent with respect to the CPU on + // GH180. + parent_gpu->ce_phys_vidmem_write_supported = !uvm_gpu_is_coherent(parent_gpu); + + // TODO: Bug 4174553: [HGX-SkinnyJoe][GH180] channel errors discussion/debug + // portion for the uvm tests became nonresponsive after + // some time and then failed even after reboot + parent_gpu->peer_copy_mode = uvm_gpu_is_coherent(parent_gpu) ? + UVM_GPU_PEER_COPY_MODE_VIRTUAL : g_uvm_global.peer_copy_mode; // All GR context buffers may be mapped to 57b wide VAs. All "compute" units // accessing GR context buffers support the 57-bit VA range. @@ -92,5 +103,7 @@ parent_gpu->map_remap_larger_page_promotion = false; parent_gpu->plc_supported = true; + + parent_gpu->no_ats_range_required = true; } diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/kernel-open/nvidia-uvm/uvm_hopper_ce.c nvidia-open-gpu-kernel-modules-535.161.08/kernel-open/nvidia-uvm/uvm_hopper_ce.c --- nvidia-open-gpu-kernel-modules-525.147.05/kernel-open/nvidia-uvm/uvm_hopper_ce.c 2023-10-25 20:33:26.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/kernel-open/nvidia-uvm/uvm_hopper_ce.c 2024-03-05 22:25:58.000000000 +0000 @@ -1,5 +1,5 @@ /******************************************************************************* - Copyright (c) 2020 NVIDIA Corporation + Copyright (c) 2020-2022 NVIDIA Corporation Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation files (the "Software"), to @@ -23,25 +23,10 @@ #include "uvm_hal.h" #include "uvm_push.h" +#include "uvm_mem.h" +#include "uvm_conf_computing.h" #include "clc8b5.h" -static void hopper_membar_after_transfer(uvm_push_t *push) -{ - uvm_gpu_t *gpu = uvm_push_get_gpu(push); - - if (uvm_push_get_and_reset_flag(push, UVM_PUSH_FLAG_NEXT_MEMBAR_NONE)) - return; - - // TODO: [UVM-Volta] Remove Host WFI + Membar WAR for CE flush-only bug - // http://nvbugs/1734761 - gpu->parent->host_hal->wait_for_idle(push); - - if (uvm_push_get_and_reset_flag(push, UVM_PUSH_FLAG_NEXT_MEMBAR_GPU)) - gpu->parent->host_hal->membar_gpu(push); - else - gpu->parent->host_hal->membar_sys(push); -} - static NvU32 ce_aperture(uvm_aperture_t aperture) { BUILD_BUG_ON(HWCONST(C8B5, SET_SRC_PHYS_MODE, TARGET, LOCAL_FB) != @@ -78,45 +63,32 @@ OFFSET_OUT_LOWER, HWVALUE(C8B5, OFFSET_OUT_LOWER, VALUE, NvOffset_LO32(offset_out))); } -// Perform an appropriate membar before a semaphore operation. Returns whether -// the semaphore operation should include a flush. -static bool hopper_membar_before_semaphore(uvm_push_t *push) +// Return the flush type and the flush enablement. +static NvU32 hopper_get_flush_value(uvm_push_t *push) { - uvm_gpu_t *gpu; + NvU32 flush_value; + uvm_membar_t membar = uvm_push_get_and_reset_membar_flag(push); - if (uvm_push_get_and_reset_flag(push, UVM_PUSH_FLAG_NEXT_MEMBAR_NONE)) { + if (membar == UVM_MEMBAR_NONE) { // No MEMBAR requested, don't use a flush. - return false; + flush_value = HWCONST(C8B5, LAUNCH_DMA, FLUSH_ENABLE, FALSE); } + else { + flush_value = HWCONST(C8B5, LAUNCH_DMA, FLUSH_ENABLE, TRUE); - if (!uvm_push_get_and_reset_flag(push, UVM_PUSH_FLAG_NEXT_MEMBAR_GPU)) { - // By default do a MEMBAR SYS and for that we can just use flush on the - // semaphore operation. - return true; + if (membar == UVM_MEMBAR_GPU) + flush_value |= HWCONST(C8B5, LAUNCH_DMA, FLUSH_TYPE, GL); + else + flush_value |= HWCONST(C8B5, LAUNCH_DMA, FLUSH_TYPE, SYS); } - // TODO: Bug 1734761: Remove the HOST WFI+membar WAR, i.e, perform the CE - // flush when MEMBAR GPU is requested. - gpu = uvm_push_get_gpu(push); - gpu->parent->host_hal->wait_for_idle(push); - gpu->parent->host_hal->membar_gpu(push); - - return false; + return flush_value; } void uvm_hal_hopper_ce_semaphore_release(uvm_push_t *push, NvU64 gpu_va, NvU32 payload) { uvm_gpu_t *gpu = uvm_push_get_gpu(push); - NvU32 flush_value; NvU32 launch_dma_plc_mode; - bool use_flush; - - use_flush = hopper_membar_before_semaphore(push); - - if (use_flush) - flush_value = HWCONST(C8B5, LAUNCH_DMA, FLUSH_ENABLE, TRUE); - else - flush_value = HWCONST(C8B5, LAUNCH_DMA, FLUSH_ENABLE, FALSE); NV_PUSH_3U(C8B5, SET_SEMAPHORE_A, HWVALUE(C8B5, SET_SEMAPHORE_A, UPPER, NvOffset_HI32(gpu_va)), SET_SEMAPHORE_B, HWVALUE(C8B5, SET_SEMAPHORE_B, LOWER, NvOffset_LO32(gpu_va)), @@ -124,25 +96,17 @@ launch_dma_plc_mode = gpu->parent->ce_hal->plc_mode(); - NV_PUSH_1U(C8B5, LAUNCH_DMA, flush_value | + NV_PUSH_1U(C8B5, LAUNCH_DMA, hopper_get_flush_value(push) | HWCONST(C8B5, LAUNCH_DMA, DATA_TRANSFER_TYPE, NONE) | - HWCONST(C8B5, LAUNCH_DMA, SEMAPHORE_TYPE, RELEASE_ONE_WORD_SEMAPHORE) | + HWCONST(C8B5, LAUNCH_DMA, SEMAPHORE_PAYLOAD_SIZE, ONE_WORD) | + HWCONST(C8B5, LAUNCH_DMA, SEMAPHORE_TYPE, RELEASE_SEMAPHORE_NO_TIMESTAMP) | launch_dma_plc_mode); } void uvm_hal_hopper_ce_semaphore_reduction_inc(uvm_push_t *push, NvU64 gpu_va, NvU32 payload) { uvm_gpu_t *gpu = uvm_push_get_gpu(push); - NvU32 flush_value; NvU32 launch_dma_plc_mode; - bool use_flush; - - use_flush = hopper_membar_before_semaphore(push); - - if (use_flush) - flush_value = HWCONST(C8B5, LAUNCH_DMA, FLUSH_ENABLE, TRUE); - else - flush_value = HWCONST(C8B5, LAUNCH_DMA, FLUSH_ENABLE, FALSE); NV_PUSH_3U(C8B5, SET_SEMAPHORE_A, HWVALUE(C8B5, SET_SEMAPHORE_A, UPPER, NvOffset_HI32(gpu_va)), SET_SEMAPHORE_B, HWVALUE(C8B5, SET_SEMAPHORE_B, LOWER, NvOffset_LO32(gpu_va)), @@ -150,9 +114,10 @@ launch_dma_plc_mode = gpu->parent->ce_hal->plc_mode(); - NV_PUSH_1U(C8B5, LAUNCH_DMA, flush_value | + NV_PUSH_1U(C8B5, LAUNCH_DMA, hopper_get_flush_value(push) | HWCONST(C8B5, LAUNCH_DMA, DATA_TRANSFER_TYPE, NONE) | - HWCONST(C8B5, LAUNCH_DMA, SEMAPHORE_TYPE, RELEASE_ONE_WORD_SEMAPHORE) | + HWCONST(C8B5, LAUNCH_DMA, SEMAPHORE_PAYLOAD_SIZE, ONE_WORD) | + HWCONST(C8B5, LAUNCH_DMA, SEMAPHORE_TYPE, RELEASE_SEMAPHORE_NO_TIMESTAMP) | HWCONST(C8B5, LAUNCH_DMA, SEMAPHORE_REDUCTION, INC) | HWCONST(C8B5, LAUNCH_DMA, SEMAPHORE_REDUCTION_SIGN, UNSIGNED) | HWCONST(C8B5, LAUNCH_DMA, SEMAPHORE_REDUCTION_ENABLE, TRUE) | @@ -162,16 +127,7 @@ void uvm_hal_hopper_ce_semaphore_timestamp(uvm_push_t *push, NvU64 gpu_va) { uvm_gpu_t *gpu; - NvU32 flush_value; NvU32 launch_dma_plc_mode; - bool use_flush; - - use_flush = hopper_membar_before_semaphore(push); - - if (use_flush) - flush_value = HWCONST(C8B5, LAUNCH_DMA, FLUSH_ENABLE, TRUE); - else - flush_value = HWCONST(C8B5, LAUNCH_DMA, FLUSH_ENABLE, FALSE); NV_PUSH_3U(C8B5, SET_SEMAPHORE_A, HWVALUE(C8B5, SET_SEMAPHORE_A, UPPER, NvOffset_HI32(gpu_va)), SET_SEMAPHORE_B, HWVALUE(C8B5, SET_SEMAPHORE_B, LOWER, NvOffset_LO32(gpu_va)), @@ -180,9 +136,10 @@ gpu = uvm_push_get_gpu(push); launch_dma_plc_mode = gpu->parent->ce_hal->plc_mode(); - NV_PUSH_1U(C8B5, LAUNCH_DMA, flush_value | + NV_PUSH_1U(C8B5, LAUNCH_DMA, hopper_get_flush_value(push) | HWCONST(C8B5, LAUNCH_DMA, DATA_TRANSFER_TYPE, NONE) | - HWCONST(C8B5, LAUNCH_DMA, SEMAPHORE_TYPE, RELEASE_FOUR_WORD_SEMAPHORE) | + HWCONST(C8B5, LAUNCH_DMA, SEMAPHORE_PAYLOAD_SIZE, ONE_WORD) | + HWCONST(C8B5, LAUNCH_DMA, SEMAPHORE_TYPE, RELEASE_SEMAPHORE_WITH_TIMESTAMP) | launch_dma_plc_mode); } @@ -195,12 +152,46 @@ return HWCONST(C8B5, LAUNCH_DMA, DST_TYPE, PHYSICAL); } -static bool hopper_scrub_enable(uvm_gpu_address_t dst, size_t size) +static bool va_is_flat_vidmem(uvm_gpu_t *gpu, NvU64 va) { - return !dst.is_virtual && - dst.aperture == UVM_APERTURE_VID && - IS_ALIGNED(dst.address, UVM_PAGE_SIZE_4K) && - IS_ALIGNED(size, UVM_PAGE_SIZE_4K); + return (uvm_mmu_gpu_needs_static_vidmem_mapping(gpu) || uvm_mmu_gpu_needs_dynamic_vidmem_mapping(gpu)) && + va >= gpu->parent->flat_vidmem_va_base && + va < gpu->parent->flat_vidmem_va_base + UVM_GPU_MAX_PHYS_MEM; +} + +// Return whether a memset should use the fast scrubber. If so, convert dst to +// the address needed by the fast scrubber. +static bool hopper_scrub_enable(uvm_gpu_t *gpu, uvm_gpu_address_t *dst, size_t size) +{ + if (!IS_ALIGNED(dst->address, UVM_PAGE_SIZE_4K) || !IS_ALIGNED(size, UVM_PAGE_SIZE_4K)) + return false; + + // When CE physical writes are disallowed, higher layers will convert + // physical memsets to virtual using the flat mapping. Those layers are + // unaware of the fast scrubber, which is safe to use specifically when CE + // physical access is disallowed. Detect such memsets within the flat vidmem + // region and convert them back to physical, since the fast scrubber only + // works with physical addressing. + if (dst->is_virtual && !gpu->parent->ce_phys_vidmem_write_supported && va_is_flat_vidmem(gpu, dst->address)) { + *dst = uvm_gpu_address_physical(UVM_APERTURE_VID, dst->address - gpu->parent->flat_vidmem_va_base); + return true; + } + + return !dst->is_virtual && dst->aperture == UVM_APERTURE_VID; +} + +static NvU32 hopper_memset_copy_type(uvm_push_t *push, uvm_gpu_address_t dst) +{ + if (uvm_conf_computing_mode_enabled(uvm_push_get_gpu(push)) && dst.is_unprotected) + return HWCONST(C8B5, LAUNCH_DMA, COPY_TYPE, NONPROT2NONPROT); + return HWCONST(C8B5, LAUNCH_DMA, COPY_TYPE, DEFAULT); +} + +NvU32 uvm_hal_hopper_ce_memcopy_copy_type(uvm_push_t *push, uvm_gpu_address_t dst, uvm_gpu_address_t src) +{ + if (uvm_conf_computing_mode_enabled(uvm_push_get_gpu(push)) && dst.is_unprotected && src.is_unprotected) + return HWCONST(C8B5, LAUNCH_DMA, COPY_TYPE, NONPROT2NONPROT); + return HWCONST(C8B5, LAUNCH_DMA, COPY_TYPE, DEFAULT); } static void hopper_memset_common(uvm_push_t *push, @@ -218,8 +209,11 @@ NvU32 launch_dma_plc_mode; NvU32 launch_dma_remap_enable; NvU32 launch_dma_scrub_enable; + NvU32 flush_value = HWCONST(C8B5, LAUNCH_DMA, FLUSH_ENABLE, FALSE); + NvU32 copy_type_value = hopper_memset_copy_type(push, dst); + bool is_scrub = hopper_scrub_enable(gpu, &dst, num_elements * memset_element_size); - UVM_ASSERT_MSG(gpu->parent->ce_hal->memset_validate(push, dst, memset_element_size), + UVM_ASSERT_MSG(gpu->parent->ce_hal->memset_is_valid(push, dst, num_elements, memset_element_size), "Memset validation failed in channel %s, GPU %s", push->channel->name, uvm_gpu_name(gpu)); @@ -232,7 +226,7 @@ else pipelined_value = HWCONST(C8B5, LAUNCH_DMA, DATA_TRANSFER_TYPE, NON_PIPELINED); - if (memset_element_size == 8 && hopper_scrub_enable(dst, num_elements * memset_element_size)) { + if (memset_element_size == 8 && is_scrub) { launch_dma_remap_enable = HWCONST(C8B5, LAUNCH_DMA, REMAP_ENABLE, FALSE); launch_dma_scrub_enable = HWCONST(C8B5, LAUNCH_DMA, MEMORY_SCRUB_ENABLE, TRUE); @@ -252,6 +246,10 @@ do { NvU32 memset_this_time = (NvU32)min(num_elements, max_single_memset); + // In the last operation, a flush/membar may be issued after the memset. + if (num_elements == memset_this_time) + flush_value = hopper_get_flush_value(push); + gpu->parent->ce_hal->offset_out(push, dst.address); NV_PUSH_1U(C8B5, LINE_LENGTH_IN, memset_this_time); @@ -260,19 +258,18 @@ HWCONST(C8B5, LAUNCH_DMA, SRC_MEMORY_LAYOUT, PITCH) | HWCONST(C8B5, LAUNCH_DMA, DST_MEMORY_LAYOUT, PITCH) | HWCONST(C8B5, LAUNCH_DMA, MULTI_LINE_ENABLE, FALSE) | - HWCONST(C8B5, LAUNCH_DMA, FLUSH_ENABLE, FALSE) | + flush_value | launch_dma_remap_enable | launch_dma_scrub_enable | launch_dma_dst_type | launch_dma_plc_mode | + copy_type_value | pipelined_value); dst.address += memset_this_time * memset_element_size; num_elements -= memset_this_time; - pipelined_value = HWCONST(C8B5, LAUNCH_DMA, DATA_TRANSFER_TYPE, NON_PIPELINED); + pipelined_value = HWCONST(C8B5, LAUNCH_DMA, DATA_TRANSFER_TYPE, PIPELINED); } while (num_elements > 0); - - hopper_membar_after_transfer(push); } void uvm_hal_hopper_ce_memset_8(uvm_push_t *push, uvm_gpu_address_t dst, NvU64 value, size_t size) @@ -294,7 +291,7 @@ void uvm_hal_hopper_ce_memset_1(uvm_push_t *push, uvm_gpu_address_t dst, NvU8 value, size_t size) { - if (hopper_scrub_enable(dst, size)) { + if (hopper_scrub_enable(uvm_push_get_gpu(push), &dst, size)) { NvU64 value64 = value; value64 |= value64 << 8; @@ -318,7 +315,7 @@ { UVM_ASSERT_MSG(size % 4 == 0, "size: %zd\n", size); - if (hopper_scrub_enable(dst, size)) { + if (hopper_scrub_enable(uvm_push_get_gpu(push), &dst, size)) { NvU64 value64 = value; value64 |= value64 << 32; @@ -337,3 +334,234 @@ hopper_memset_common(push, dst, size, 4); } + +bool uvm_hal_hopper_ce_memset_is_valid(uvm_push_t *push, + uvm_gpu_address_t dst, + size_t num_elements, + size_t element_size) +{ + uvm_gpu_t *gpu = uvm_push_get_gpu(push); + + // In HCC, if a memset uses physical addressing for the destination, then + // it must write to (protected) vidmem. If the memset uses virtual + // addressing, and the backing storage is not vidmem, the access is only + // legal if the copy type is NONPROT2NONPROT, and the destination is + // unprotected sysmem, but the validation does not detect it. + if (uvm_conf_computing_mode_is_hcc(gpu) && !dst.is_virtual && dst.aperture != UVM_APERTURE_VID) + return false; + + if (!gpu->parent->ce_phys_vidmem_write_supported) { + size_t size = num_elements * element_size; + uvm_gpu_address_t temp = dst; + + // Physical vidmem writes are disallowed, unless using the scrubber + if (!dst.is_virtual && dst.aperture == UVM_APERTURE_VID && !hopper_scrub_enable(gpu, &temp, size)) { + UVM_ERR_PRINT("Destination address of vidmem memset must be virtual, not physical: {%s, 0x%llx} size %zu\n", + uvm_gpu_address_aperture_string(dst), + dst.address, + size); + return false; + } + } + + return true; +} + +bool uvm_hal_hopper_ce_memcopy_is_valid(uvm_push_t *push, uvm_gpu_address_t dst, uvm_gpu_address_t src) +{ + uvm_gpu_t *gpu = uvm_push_get_gpu(push); + + if (uvm_conf_computing_mode_is_hcc(gpu)) { + // In HCC, if a memcopy uses physical addressing for either the + // destination or the source, then the corresponding aperture must be + // vidmem. If virtual addressing is used, and the backing storage is + // sysmem the access is only legal if the copy type is NONPROT2NONPROT, + // but the validation does not detect it. In other words the copy + // source and destination is unprotected sysmem. + if (!src.is_virtual && (src.aperture != UVM_APERTURE_VID)) + return false; + + if (!dst.is_virtual && (dst.aperture != UVM_APERTURE_VID)) + return false; + + if (dst.is_unprotected != src.is_unprotected) + return false; + } + + if (!gpu->parent->ce_phys_vidmem_write_supported && !dst.is_virtual && dst.aperture == UVM_APERTURE_VID) { + UVM_ERR_PRINT("Destination address of vidmem memcopy must be virtual, not physical: {%s, 0x%llx}\n", + uvm_gpu_address_aperture_string(dst), + dst.address); + return false; + } + + return true; +} + +// Specialized version of uvm_hal_volta_ce_memcopy used for encryption and +// decryption. Pre-Hopper functionality, such as validation or address patching, +// has been removed. +static void encrypt_or_decrypt(uvm_push_t *push, uvm_gpu_address_t dst, uvm_gpu_address_t src, NvU32 size) +{ + NvU32 pipelined_value; + NvU32 launch_dma_src_dst_type; + NvU32 launch_dma_plc_mode; + NvU32 flush_value; + uvm_gpu_t *gpu = uvm_push_get_gpu(push); + + // HW allows unaligned operations only if the entire buffer is in one 32B + // sector. Operations on buffers larger than 32B have to be aligned. + if (size > UVM_CONF_COMPUTING_BUF_ALIGNMENT) { + UVM_ASSERT(IS_ALIGNED(src.address, UVM_CONF_COMPUTING_BUF_ALIGNMENT)); + UVM_ASSERT(IS_ALIGNED(dst.address, UVM_CONF_COMPUTING_BUF_ALIGNMENT)); + } + else { + UVM_ASSERT((dst.address >> UVM_CONF_COMPUTING_BUF_ALIGNMENT) == + ((dst.address + size - 1) >> UVM_CONF_COMPUTING_BUF_ALIGNMENT)); + UVM_ASSERT((src.address >> UVM_CONF_COMPUTING_BUF_ALIGNMENT) == + ((src.address + size - 1) >> UVM_CONF_COMPUTING_BUF_ALIGNMENT)); + } + + launch_dma_src_dst_type = gpu->parent->ce_hal->phys_mode(push, dst, src); + launch_dma_plc_mode = gpu->parent->ce_hal->plc_mode(); + + if (uvm_push_get_and_reset_flag(push, UVM_PUSH_FLAG_CE_NEXT_PIPELINED)) + pipelined_value = HWCONST(C8B5, LAUNCH_DMA, DATA_TRANSFER_TYPE, PIPELINED); + else + pipelined_value = HWCONST(C8B5, LAUNCH_DMA, DATA_TRANSFER_TYPE, NON_PIPELINED); + + flush_value = hopper_get_flush_value(push); + + gpu->parent->ce_hal->offset_in_out(push, src.address, dst.address); + + NV_PUSH_1U(C8B5, LINE_LENGTH_IN, size); + + NV_PUSH_1U(C8B5, LAUNCH_DMA, HWCONST(C8B5, LAUNCH_DMA, SRC_MEMORY_LAYOUT, PITCH) | + HWCONST(C8B5, LAUNCH_DMA, DST_MEMORY_LAYOUT, PITCH) | + HWCONST(C8B5, LAUNCH_DMA, MULTI_LINE_ENABLE, FALSE) | + HWCONST(C8B5, LAUNCH_DMA, REMAP_ENABLE, FALSE) | + HWCONST(C8B5, LAUNCH_DMA, COPY_TYPE, SECURE) | + flush_value | + launch_dma_src_dst_type | + launch_dma_plc_mode | + pipelined_value); +} + +// The GPU CE encrypt operation requires clients to pass a valid +// address where the used IV will be written. But this requirement is +// unnecessary, because UVM should instead rely on the CSL +// nvUvmInterfaceCslLogDeviceEncryption API to independently track +// the expected IV. +// +// To satisfy the HW requirement the same unprotected sysmem address is +// passed to all GPU-side encryptions. This dummy buffer is allocated at +// GPU initialization time. +static NvU64 encrypt_iv_address(uvm_push_t *push, uvm_gpu_address_t dst) +{ + NvU64 iv_address; + uvm_gpu_t *gpu = uvm_push_get_gpu(push); + + // Match addressing mode of destination and IV + if (dst.is_virtual) { + iv_address = uvm_rm_mem_get_gpu_va(gpu->conf_computing.iv_rm_mem, gpu, false).address; + } + else { + iv_address = uvm_mem_gpu_physical(gpu->conf_computing.iv_mem, + gpu, + 0, + gpu->conf_computing.iv_mem->size).address; + } + + UVM_ASSERT(IS_ALIGNED(iv_address, UVM_CONF_COMPUTING_IV_ALIGNMENT)); + + return iv_address; +} + +// TODO: Bug 3842953: adapt CE encrypt/decrypt for p2p encrypted transfers +void uvm_hal_hopper_ce_encrypt(uvm_push_t *push, + uvm_gpu_address_t dst, + uvm_gpu_address_t src, + NvU32 size, + uvm_gpu_address_t auth_tag) +{ + + NvU32 auth_tag_address_hi32, auth_tag_address_lo32; + NvU64 iv_address; + NvU32 iv_address_hi32, iv_address_lo32; + uvm_gpu_t *gpu = uvm_push_get_gpu(push); + + UVM_ASSERT(uvm_conf_computing_mode_is_hcc(gpu)); + UVM_ASSERT(IS_ALIGNED(auth_tag.address, UVM_CONF_COMPUTING_AUTH_TAG_ALIGNMENT)); + + if (!src.is_virtual) + UVM_ASSERT(src.aperture == UVM_APERTURE_VID); + + // The addressing mode (and aperture, if applicable) of the destination + // pointer determines the addressing mode and aperture used by the + // encryption to reference the other two addresses written by it: + // authentication tag, and IV. If the client passes a sysmem physical + // address as destination, then the authentication tag must also be a sysmem + // physical address. + UVM_ASSERT(dst.is_virtual == auth_tag.is_virtual); + + if (!dst.is_virtual) { + UVM_ASSERT(dst.aperture == UVM_APERTURE_SYS); + UVM_ASSERT(auth_tag.aperture == UVM_APERTURE_SYS); + } + + NV_PUSH_1U(C8B5, SET_SECURE_COPY_MODE, HWCONST(C8B5, SET_SECURE_COPY_MODE, MODE, ENCRYPT)); + + auth_tag_address_hi32 = HWVALUE(C8B5, SET_ENCRYPT_AUTH_TAG_ADDR_UPPER, UPPER, NvU64_HI32(auth_tag.address)); + auth_tag_address_lo32 = HWVALUE(C8B5, SET_ENCRYPT_AUTH_TAG_ADDR_LOWER, LOWER, NvU64_LO32(auth_tag.address)); + + iv_address = encrypt_iv_address(push, dst); + + iv_address_hi32 = HWVALUE(C8B5, SET_ENCRYPT_IV_ADDR_UPPER, UPPER, NvU64_HI32(iv_address)); + iv_address_lo32 = HWVALUE(C8B5, SET_ENCRYPT_IV_ADDR_LOWER, LOWER, NvU64_LO32(iv_address)); + + NV_PUSH_4U(C8B5, SET_ENCRYPT_AUTH_TAG_ADDR_UPPER, auth_tag_address_hi32, + SET_ENCRYPT_AUTH_TAG_ADDR_LOWER, auth_tag_address_lo32, + SET_ENCRYPT_IV_ADDR_UPPER, iv_address_hi32, + SET_ENCRYPT_IV_ADDR_LOWER, iv_address_lo32); + + encrypt_or_decrypt(push, dst, src, size); +} + +// TODO: Bug 3842953: adapt CE encrypt/decrypt for p2p encrypted transfers +void uvm_hal_hopper_ce_decrypt(uvm_push_t *push, + uvm_gpu_address_t dst, + uvm_gpu_address_t src, + NvU32 size, + uvm_gpu_address_t auth_tag) +{ + + NvU32 auth_tag_address_hi32, auth_tag_address_lo32; + uvm_gpu_t *gpu = uvm_push_get_gpu(push); + + UVM_ASSERT(uvm_conf_computing_mode_is_hcc(gpu)); + UVM_ASSERT(IS_ALIGNED(auth_tag.address, UVM_CONF_COMPUTING_AUTH_TAG_ALIGNMENT)); + + // The addressing mode (and aperture, if applicable) of the source and + // authentication pointers should match. But unlike in the encryption case, + // clients are not forced to pass a valid IV address. + UVM_ASSERT(src.is_virtual == auth_tag.is_virtual); + + if (!src.is_virtual) { + UVM_ASSERT(src.aperture == UVM_APERTURE_SYS); + UVM_ASSERT(auth_tag.aperture == UVM_APERTURE_SYS); + } + + if (!dst.is_virtual) + UVM_ASSERT(dst.aperture == UVM_APERTURE_VID); + + NV_PUSH_1U(C8B5, SET_SECURE_COPY_MODE, HWCONST(C8B5, SET_SECURE_COPY_MODE, MODE, DECRYPT)); + + auth_tag_address_hi32 = HWVALUE(C8B5, SET_DECRYPT_AUTH_TAG_COMPARE_ADDR_UPPER, UPPER, NvU64_HI32(auth_tag.address)); + auth_tag_address_lo32 = HWVALUE(C8B5, SET_DECRYPT_AUTH_TAG_COMPARE_ADDR_LOWER, LOWER, NvU64_LO32(auth_tag.address)); + + NV_PUSH_2U(C8B5, SET_DECRYPT_AUTH_TAG_COMPARE_ADDR_UPPER, auth_tag_address_hi32, + SET_DECRYPT_AUTH_TAG_COMPARE_ADDR_LOWER, auth_tag_address_lo32); + + encrypt_or_decrypt(push, dst, src, size); +} + diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/kernel-open/nvidia-uvm/uvm_hopper_host.c nvidia-open-gpu-kernel-modules-535.161.08/kernel-open/nvidia-uvm/uvm_hopper_host.c --- nvidia-open-gpu-kernel-modules-525.147.05/kernel-open/nvidia-uvm/uvm_hopper_host.c 2023-10-25 20:33:26.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/kernel-open/nvidia-uvm/uvm_hopper_host.c 2024-03-05 22:25:58.000000000 +0000 @@ -391,10 +391,15 @@ *fifo_entry |= (NvU64)(HWCONST(C86F, GP_ENTRY1, OPCODE, SET_PB_SEGMENT_EXTENDED_BASE)) << 32; } -void uvm_hal_hopper_host_set_gpfifo_entry(NvU64 *fifo_entry, NvU64 pushbuffer_va, NvU32 pushbuffer_length) +void uvm_hal_hopper_host_set_gpfifo_entry(NvU64 *fifo_entry, + NvU64 pushbuffer_va, + NvU32 pushbuffer_length, + uvm_gpfifo_sync_t sync_flag) { NvU64 fifo_entry_value; NvU64 pb_low_bits_mask = (1ull << 40) - 1; + const NvU32 sync_value = (sync_flag == UVM_GPFIFO_SYNC_WAIT) ? HWCONST(C86F, GP_ENTRY1, SYNC, WAIT) : + HWCONST(C86F, GP_ENTRY1, SYNC, PROCEED); UVM_ASSERT(!uvm_global_is_suspended()); UVM_ASSERT_MSG(IS_ALIGNED(pushbuffer_va, 4), "pushbuffer va unaligned: %llu\n", pushbuffer_va); @@ -406,7 +411,8 @@ pushbuffer_va &= pb_low_bits_mask; fifo_entry_value = HWVALUE(C86F, GP_ENTRY0, GET, NvU64_LO32(pushbuffer_va) >> 2); fifo_entry_value |= (NvU64)(HWVALUE(C86F, GP_ENTRY1, GET_HI, NvU64_HI32(pushbuffer_va)) | - HWVALUE(C86F, GP_ENTRY1, LENGTH, pushbuffer_length >> 2)) << 32; + HWVALUE(C86F, GP_ENTRY1, LENGTH, pushbuffer_length >> 2) | + sync_value) << 32; *fifo_entry = fifo_entry_value; } diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/kernel-open/nvidia-uvm/uvm_hopper_mmu.c nvidia-open-gpu-kernel-modules-535.161.08/kernel-open/nvidia-uvm/uvm_hopper_mmu.c --- nvidia-open-gpu-kernel-modules-525.147.05/kernel-open/nvidia-uvm/uvm_hopper_mmu.c 2023-10-25 20:33:26.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/kernel-open/nvidia-uvm/uvm_hopper_mmu.c 2024-03-05 22:25:58.000000000 +0000 @@ -1,5 +1,5 @@ /******************************************************************************* - Copyright (c) 2020-2022 NVIDIA Corporation + Copyright (c) 2020-2023 NVIDIA Corporation Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation files (the "Software"), to @@ -33,6 +33,7 @@ #include "uvm_types.h" #include "uvm_global.h" +#include "uvm_common.h" #include "uvm_hal.h" #include "uvm_hal_types.h" #include "uvm_hopper_fault_buffer.h" @@ -42,6 +43,10 @@ #define MMU_BIG 0 #define MMU_SMALL 1 +// Used in pde_pcf(). +#define ATS_ALLOWED 0 +#define ATS_NOT_ALLOWED 1 + uvm_mmu_engine_type_t uvm_hal_hopper_mmu_engine_id_to_type(NvU16 mmu_engine_id) { if (mmu_engine_id >= NV_PFAULT_MMU_ENG_ID_HOST0 && mmu_engine_id <= NV_PFAULT_MMU_ENG_ID_HOST44) @@ -260,7 +265,108 @@ return WRITE_HWCONST64(pte_bits, _MMU_VER3, PTE, PCF, PRIVILEGE_RO_NO_ATOMIC_UNCACHED_ACD); } -static NvU64 single_pde_hopper(uvm_mmu_page_table_alloc_t *phys_alloc, NvU32 depth) +typedef enum +{ + PDE_TYPE_SINGLE, + PDE_TYPE_DUAL_BIG, + PDE_TYPE_DUAL_SMALL, + PDE_TYPE_COUNT, +} pde_type_t; + +static const NvU8 valid_pcf[][2] = { { NV_MMU_VER3_PDE_PCF_VALID_UNCACHED_ATS_ALLOWED, + NV_MMU_VER3_PDE_PCF_VALID_UNCACHED_ATS_NOT_ALLOWED }, + { NV_MMU_VER3_DUAL_PDE_PCF_BIG_VALID_UNCACHED_ATS_ALLOWED, + NV_MMU_VER3_DUAL_PDE_PCF_BIG_VALID_UNCACHED_ATS_NOT_ALLOWED }, + { NV_MMU_VER3_DUAL_PDE_PCF_SMALL_VALID_UNCACHED_ATS_ALLOWED, + NV_MMU_VER3_DUAL_PDE_PCF_SMALL_VALID_UNCACHED_ATS_NOT_ALLOWED } }; + +static const NvU8 invalid_pcf[][2] = { { NV_MMU_VER3_PDE_PCF_INVALID_ATS_ALLOWED, + NV_MMU_VER3_PDE_PCF_INVALID_ATS_NOT_ALLOWED }, + { NV_MMU_VER3_DUAL_PDE_PCF_BIG_INVALID_ATS_ALLOWED, + NV_MMU_VER3_DUAL_PDE_PCF_BIG_INVALID_ATS_NOT_ALLOWED }, + { NV_MMU_VER3_DUAL_PDE_PCF_SMALL_INVALID_ATS_ALLOWED, + NV_MMU_VER3_DUAL_PDE_PCF_SMALL_INVALID_ATS_NOT_ALLOWED } }; + +static const NvU8 va_base[] = { 56, 47, 38, 29, 21 }; + +static bool is_ats_range_valid(uvm_page_directory_t *dir, NvU32 child_index) +{ + NvU64 pde_base_va; + NvU64 min_va_upper; + NvU64 max_va_lower; + NvU32 index_in_dir; + + uvm_cpu_get_unaddressable_range(&max_va_lower, &min_va_upper); + + UVM_ASSERT(dir->depth < ARRAY_SIZE(va_base)); + + // We can use UVM_PAGE_SIZE_AGNOSTIC because page_size is only used in + // index_bits_hopper() for PTE table, i.e., depth 5+, which does not use a + // PDE PCF or an ATS_ALLOWED/NOT_ALLOWED setting. + UVM_ASSERT(child_index < (1ull << index_bits_hopper(dir->depth, UVM_PAGE_SIZE_AGNOSTIC))); + + pde_base_va = 0; + index_in_dir = child_index; + while (dir) { + pde_base_va += index_in_dir * (1ull << va_base[dir->depth]); + index_in_dir = dir->index_in_parent; + dir = dir->host_parent; + } + pde_base_va = (NvU64)((NvS64)(pde_base_va << (64 - num_va_bits_hopper())) >> (64 - num_va_bits_hopper())); + + if (pde_base_va < max_va_lower || pde_base_va >= min_va_upper) + return true; + + return false; +} + +// PDE Permission Control Flags +static NvU32 pde_pcf(bool valid, pde_type_t pde_type, uvm_page_directory_t *dir, NvU32 child_index) +{ + const NvU8 (*pcf)[2] = valid ? valid_pcf : invalid_pcf; + NvU8 depth = dir->depth; + + UVM_ASSERT(pde_type < PDE_TYPE_COUNT); + UVM_ASSERT(depth < 5); + + // On non-ATS systems, PDE PCF only sets the valid and volatile/cache bits. + if (!g_uvm_global.ats.enabled) + return pcf[pde_type][ATS_ALLOWED]; + + // We assume all supported ATS platforms use canonical form address. + // See comments in uvm_gpu.c:uvm_gpu_can_address() and in + // uvm_mmu.c:page_tree_ats_init(); + UVM_ASSERT(uvm_platform_uses_canonical_form_address()); + + // Hopper GPUs on ATS-enabled systems, perform a parallel lookup on both + // ATS and GMMU page tables. For managed memory we need to prevent this + // parallel lookup since we would not get any GPU fault if the CPU has + // a valid mapping. Also, for external ranges that are known to be + // mapped entirely on the GMMU page table we can skip the ATS lookup + // for performance reasons. Parallel ATS lookup is disabled in PDE1 + // (depth 3) and, therefore, it applies to the underlying 512MB VA + // range. + // + // UVM sets ATS_NOT_ALLOWED for all Hopper+ mappings on ATS systems. + // This is fine because CUDA ensures that all managed and external + // allocations are properly compartmentalized in 512MB-aligned VA + // regions. For cudaHostRegister CUDA cannot control the VA range, but + // we rely on ATS for those allocations so they can't choose the + // ATS_NOT_ALLOWED mode. + // TODO: Bug 3254055: Relax the NO_ATS setting from 512MB (pde1) range to + // PTEs. + // HW complies with the leaf PDE's ATS_ALLOWED/ATS_NOT_ALLOWED settings, + // enabling us to treat any upper-level PDE as a don't care as long as there + // are leaf PDEs for the entire upper-level PDE range. We assume PDE4 + // entries (depth == 0) are always ATS enabled, and the no_ats_range is in + // PDE3 or lower. + if (depth == 0 || (!valid && is_ats_range_valid(dir, child_index))) + return pcf[pde_type][ATS_ALLOWED]; + + return pcf[pde_type][ATS_NOT_ALLOWED]; +} + +static NvU64 single_pde_hopper(uvm_mmu_page_table_alloc_t *phys_alloc, uvm_page_directory_t *dir, NvU32 child_index) { NvU64 pde_bits = 0; @@ -280,38 +386,17 @@ break; } - // PCF (permission control flags) 5:3 - // Hopper GPUs on ATS-enabled systems, perform a parallel lookup on both - // ATS and GMMU page tables. For managed memory we need to prevent this - // parallel lookup since we would not get any GPU fault if the CPU has - // a valid mapping. Also, for external ranges that are known to be - // mapped entirely on the GMMU page table we can skip the ATS lookup - // for performance reasons. Parallel ATS lookup is disabled in PDE1 - // (depth 3) and, therefore, it applies to the underlying 512MB VA - // range. - // - // UVM sets ATS_NOT_ALLOWED for all Hopper+ mappings on ATS systems. - // This is fine because CUDA ensures that all managed and external - // allocations are properly compartmentalized in 512MB-aligned VA - // regions. For cudaHostRegister CUDA cannot control the VA range, but - // we rely on ATS for those allocations so they can't choose the - // ATS_NOT_ALLOWED mode. - // - // TODO: Bug 3254055: Relax the NO_ATS setting from 512MB (pde1) range - // to PTEs. - if (depth == 3 && g_uvm_global.ats.enabled) - pde_bits |= HWCONST64(_MMU_VER3, PDE, PCF, VALID_UNCACHED_ATS_NOT_ALLOWED); - else - pde_bits |= HWCONST64(_MMU_VER3, PDE, PCF, VALID_UNCACHED_ATS_ALLOWED); - // address 51:12 pde_bits |= HWVALUE64(_MMU_VER3, PDE, ADDRESS, address); } + // PCF (permission control flags) 5:3 + pde_bits |= HWVALUE64(_MMU_VER3, PDE, PCF, pde_pcf(phys_alloc != NULL, PDE_TYPE_SINGLE, dir, child_index)); + return pde_bits; } -static NvU64 big_half_pde_hopper(uvm_mmu_page_table_alloc_t *phys_alloc) +static NvU64 big_half_pde_hopper(uvm_mmu_page_table_alloc_t *phys_alloc, uvm_page_directory_t *dir, NvU32 child_index) { NvU64 pde_bits = 0; @@ -330,17 +415,20 @@ break; } - // PCF (permission control flags) 5:3 - pde_bits |= HWCONST64(_MMU_VER3, DUAL_PDE, PCF_BIG, VALID_UNCACHED_ATS_NOT_ALLOWED); - // address 51:8 pde_bits |= HWVALUE64(_MMU_VER3, DUAL_PDE, ADDRESS_BIG, address); } + // PCF (permission control flags) 5:3 + pde_bits |= HWVALUE64(_MMU_VER3, + DUAL_PDE, + PCF_BIG, + pde_pcf(phys_alloc != NULL, PDE_TYPE_DUAL_BIG, dir, child_index)); + return pde_bits; } -static NvU64 small_half_pde_hopper(uvm_mmu_page_table_alloc_t *phys_alloc) +static NvU64 small_half_pde_hopper(uvm_mmu_page_table_alloc_t *phys_alloc, uvm_page_directory_t *dir, NvU32 child_index) { NvU64 pde_bits = 0; @@ -359,29 +447,40 @@ break; } - // PCF (permission control flags) 69:67 [5:3] - pde_bits |= HWCONST64(_MMU_VER3, DUAL_PDE, PCF_SMALL, VALID_UNCACHED_ATS_NOT_ALLOWED); - // address 115:76 [51:12] pde_bits |= HWVALUE64(_MMU_VER3, DUAL_PDE, ADDRESS_SMALL, address); } + + // PCF (permission control flags) 69:67 [5:3] + pde_bits |= HWVALUE64(_MMU_VER3, + DUAL_PDE, + PCF_SMALL, + pde_pcf(phys_alloc != NULL, PDE_TYPE_DUAL_SMALL, dir, child_index)); + return pde_bits; } -static void make_pde_hopper(void *entry, uvm_mmu_page_table_alloc_t **phys_allocs, NvU32 depth) +static void make_pde_hopper(void *entry, + uvm_mmu_page_table_alloc_t **phys_allocs, + uvm_page_directory_t *dir, + NvU32 child_index) { - NvU32 entry_count = entries_per_index_hopper(depth); + NvU32 entry_count; NvU64 *entry_bits = (NvU64 *)entry; + UVM_ASSERT(dir); + + entry_count = entries_per_index_hopper(dir->depth); + if (entry_count == 1) { - *entry_bits = single_pde_hopper(*phys_allocs, depth); + *entry_bits = single_pde_hopper(*phys_allocs, dir, child_index); } else if (entry_count == 2) { - entry_bits[MMU_BIG] = big_half_pde_hopper(phys_allocs[MMU_BIG]); - entry_bits[MMU_SMALL] = small_half_pde_hopper(phys_allocs[MMU_SMALL]); + entry_bits[MMU_BIG] = big_half_pde_hopper(phys_allocs[MMU_BIG], dir, child_index); + entry_bits[MMU_SMALL] = small_half_pde_hopper(phys_allocs[MMU_SMALL], dir, child_index); // This entry applies to the whole dual PDE but is stored in the lower - // bits + // bits. entry_bits[MMU_BIG] |= HWCONST64(_MMU_VER3, DUAL_PDE, IS_PTE, FALSE); } else { diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/kernel-open/nvidia-uvm/uvm_hopper_sec2.c nvidia-open-gpu-kernel-modules-535.161.08/kernel-open/nvidia-uvm/uvm_hopper_sec2.c --- nvidia-open-gpu-kernel-modules-525.147.05/kernel-open/nvidia-uvm/uvm_hopper_sec2.c 1970-01-01 00:00:00.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/kernel-open/nvidia-uvm/uvm_hopper_sec2.c 2024-03-05 22:25:41.000000000 +0000 @@ -0,0 +1,213 @@ +/******************************************************************************* + Copyright (c) 2022-2023 NVIDIA Corporation + + Permission is hereby granted, free of charge, to any person obtaining a copy + of this software and associated documentation files (the "Software"), to + deal in the Software without restriction, including without limitation the + rights to use, copy, modify, merge, publish, distribute, sublicense, and/or + sell copies of the Software, and to permit persons to whom the Software is + furnished to do so, subject to the following conditions: + + The above copyright notice and this permission notice shall be + included in all copies or substantial portions of the Software. + + THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + DEALINGS IN THE SOFTWARE. + +*******************************************************************************/ + +#include "uvm_hal.h" +#include "uvm_hal_types.h" +#include "uvm_push.h" +#include "uvm_push_macros.h" +#include "nv_uvm_types.h" +#include "nv_uvm_interface.h" +#include "clcba2.h" +#include "clc86f.h" +#include "clb06f.h" + +#define UVM_CSL_SIGN_AUTH_TAG_ALIGNMENT_BYTES (1 << HWSHIFT(CBA2, METHOD_STREAM_AUTH_TAG_ADDR_LO, DATA)) + +static void sign_push(uvm_push_t *push, NvU32 *init_method, NvU8 *auth_tag) +{ + NvU32 *sign_input_buf = push->begin + UVM_METHOD_SIZE / sizeof(*push->begin); + NvU32 sign_size = 0; + NV_STATUS status; + + UVM_ASSERT(init_method < push->next); + + while (init_method < push->next) { + NvU8 subch = READ_HWVALUE(*init_method, B06F, DMA, METHOD_SUBCHANNEL); + NvU32 count = READ_HWVALUE(*init_method, B06F, DMA, METHOD_COUNT); + + if (subch == UVM_SUBCHANNEL_CBA2) { + NvU32 method_addr = READ_HWVALUE(*init_method, B06F, DMA, METHOD_ADDRESS) << 2; + + UVM_ASSERT(count == 1); + UVM_ASSERT((sign_size + 2) * UVM_METHOD_SIZE <= UVM_CONF_COMPUTING_SIGN_BUF_MAX_SIZE); + + sign_input_buf[sign_size] = method_addr; + sign_input_buf[sign_size + 1] = init_method[1]; + + // We consume the method address and the method data from the input, + // we advance the sign_input_buf by 2. + sign_size += 2; + } + + init_method += (count + 1); + } + + UVM_ASSERT(sign_size > 0); + + status = nvUvmInterfaceCslSign(&push->channel->csl.ctx, + sign_size * UVM_METHOD_SIZE, + (NvU8 *)sign_input_buf, + auth_tag); + + UVM_ASSERT_MSG(status == NV_OK, + "Failure to sign method stream auth tag, err: %s, GPU: %s.\n", + nvstatusToString(status), + uvm_gpu_name(uvm_push_get_gpu(push))); +} + +void uvm_hal_hopper_sec2_init(uvm_push_t *push) +{ + // Commonly, we would push a SET_OBJECT HOPPER_SEC2_WORK_LAUNCH_A in the + // init function. During channel initialization, this method would be sent + // to ESCHED to notify the expected SEC2 class ID. ESCHED forwards this + // method to the SEC2 engine. SEC2 is not guaranteed to support the + // SET_OBJECT method, so we shouldn't submit it. +} + +void uvm_hal_hopper_sec2_semaphore_release(uvm_push_t *push, NvU64 gpu_va, NvU32 payload) +{ + NvU32 sem_lo; + NvU32 flush_value; + NvU8 *sign_auth_tag_ptr; + NvU32 sign_auth_tag_addr_lo; + uvm_gpu_address_t sign_auth_tag_gpu_va; + NvU32 *csl_sign_init = push->next; + + UVM_ASSERT(IS_ALIGNED(NvU64_LO32(gpu_va), 1 << HWSHIFT(CBA2, SEMAPHORE_B, LOWER))); + + sem_lo = READ_HWVALUE(NvU64_LO32(gpu_va), CBA2, SEMAPHORE_B, LOWER); + + flush_value = uvm_hal_membar_before_semaphore(push) ? HWCONST(CBA2, SEMAPHORE_D, FLUSH_DISABLE, FALSE) : + HWCONST(CBA2, SEMAPHORE_D, FLUSH_DISABLE, TRUE); + + // The push and the method stream signature have the same lifetime, we + // reserve space in the pushbuffer to store the signature. After the push is + // processed by the GPU, the pushbuffer is recycled entirely, including the + // signature buffer. + sign_auth_tag_ptr = uvm_push_get_single_inline_buffer(push, + UVM_CSL_SIGN_AUTH_TAG_SIZE_BYTES, + UVM_CSL_SIGN_AUTH_TAG_ALIGNMENT_BYTES, + &sign_auth_tag_gpu_va); + + NV_PUSH_1U(CBA2, + METHOD_STREAM_AUTH_TAG_ADDR_HI, + HWVALUE(CBA2, METHOD_STREAM_AUTH_TAG_ADDR_HI, DATA, NvU64_HI32(sign_auth_tag_gpu_va.address))); + + sign_auth_tag_addr_lo = READ_HWVALUE(NvU64_LO32(sign_auth_tag_gpu_va.address), + CBA2, + METHOD_STREAM_AUTH_TAG_ADDR_LO, + DATA); + NV_PUSH_1U(CBA2, + METHOD_STREAM_AUTH_TAG_ADDR_LO, + HWVALUE(CBA2, METHOD_STREAM_AUTH_TAG_ADDR_LO, DATA, sign_auth_tag_addr_lo)); + + NV_PUSH_1U(CBA2, SEMAPHORE_A, HWVALUE(CBA2, SEMAPHORE_A, UPPER, NvU64_HI32(gpu_va))); + NV_PUSH_1U(CBA2, SEMAPHORE_B, HWVALUE(CBA2, SEMAPHORE_B, LOWER, sem_lo)); + NV_PUSH_1U(CBA2, SET_SEMAPHORE_PAYLOAD_LOWER, payload); + + NV_PUSH_1U(CBA2, SEMAPHORE_D, HWCONST(CBA2, SEMAPHORE_D, TIMESTAMP, DISABLE) | + HWCONST(CBA2, SEMAPHORE_D, PAYLOAD_SIZE, 32_BIT) | + flush_value); + + sign_push(push, csl_sign_init, sign_auth_tag_ptr); +} + +void uvm_hal_hopper_sec2_semaphore_timestamp_unsupported(uvm_push_t *push, NvU64 gpu_va) +{ + // TODO: Bug 3804752: [uvm][HCC] Add support for Hopper SEC2 HAL in UVM. + // Semaphore_timestamp is not implemented in the SEC2 engine yet. We will + // add support in UVM when they become available. + uvm_gpu_t *gpu = uvm_push_get_gpu(push); + UVM_ASSERT_MSG(false, "SEC2 semaphore_timestamp is not supported on GPU: %s.\n", uvm_gpu_name(gpu)); +} + +static void execute_with_membar(uvm_push_t *push) +{ + uvm_gpu_t *gpu = uvm_push_get_gpu(push); + uvm_membar_t membar = uvm_push_get_and_reset_membar_flag(push); + + NvU32 flush_value = (membar == UVM_MEMBAR_SYS) ? HWCONST(CBA2, EXECUTE, FLUSH_DISABLE, FALSE) : + HWCONST(CBA2, EXECUTE, FLUSH_DISABLE, TRUE); + + NV_PUSH_1U(CBA2, EXECUTE, flush_value | + HWCONST(CBA2, EXECUTE, NOTIFY, DISABLE)); + + if (membar == UVM_MEMBAR_GPU) { + gpu->parent->host_hal->wait_for_idle(push); + gpu->parent->host_hal->membar_gpu(push); + } +} + +void uvm_hal_hopper_sec2_decrypt(uvm_push_t *push, NvU64 dst_va, NvU64 src_va, NvU32 size, NvU64 auth_tag_va) +{ + NvU8 *sign_auth_tag_ptr; + NvU32 sign_auth_tag_addr_lo; + uvm_gpu_address_t sign_auth_tag_gpu_va; + NvU32 *csl_sign_init = push->next; + + // Check that the provided alignment matches HW + BUILD_BUG_ON(UVM_CONF_COMPUTING_SEC2_BUF_ALIGNMENT != (1 << HWSHIFT(CBA2, DECRYPT_COPY_DST_ADDR_LO, DATA))); + BUILD_BUG_ON(UVM_CONF_COMPUTING_BUF_ALIGNMENT < (1 << HWSHIFT(CBA2, DECRYPT_COPY_DST_ADDR_LO, DATA))); + BUILD_BUG_ON(UVM_CONF_COMPUTING_BUF_ALIGNMENT % (1 << HWSHIFT(CBA2, DECRYPT_COPY_DST_ADDR_LO, DATA)) != 0); + + // No overlapping. + UVM_ASSERT(!uvm_ranges_overlap(src_va, src_va + size - 1, dst_va, dst_va + size - 1)); + + // Alignment requirements. + UVM_ASSERT(IS_ALIGNED(NvU64_LO32(src_va), 1 << HWSHIFT(CBA2, DECRYPT_COPY_SRC_ADDR_LO, DATA))); + UVM_ASSERT(IS_ALIGNED(NvU64_LO32(dst_va), 1 << HWSHIFT(CBA2, DECRYPT_COPY_DST_ADDR_LO, DATA))); + UVM_ASSERT(IS_ALIGNED(NvU64_LO32(auth_tag_va), 1 << HWSHIFT(CBA2, DECRYPT_COPY_AUTH_TAG_ADDR_LO, DATA))); + UVM_ASSERT(IS_ALIGNED(size, 1 << HWSHIFT(CBA2, DECRYPT_COPY_SIZE, DATA))); + + // See comments in SEC2 semaphore_release. + sign_auth_tag_ptr = uvm_push_get_single_inline_buffer(push, + UVM_CSL_SIGN_AUTH_TAG_SIZE_BYTES, + UVM_CSL_SIGN_AUTH_TAG_ALIGNMENT_BYTES, + &sign_auth_tag_gpu_va); + + NV_PUSH_1U(CBA2, DECRYPT_COPY_SRC_ADDR_HI, NvU64_HI32(src_va)); + NV_PUSH_1U(CBA2, DECRYPT_COPY_SRC_ADDR_LO, NvU64_LO32(src_va)); + + NV_PUSH_1U(CBA2, DECRYPT_COPY_DST_ADDR_HI, NvU64_HI32(dst_va)); + NV_PUSH_1U(CBA2, DECRYPT_COPY_DST_ADDR_LO, NvU64_LO32(dst_va)); + + NV_PUSH_1U(CBA2, DECRYPT_COPY_SIZE, size); + NV_PUSH_1U(CBA2, DECRYPT_COPY_AUTH_TAG_ADDR_HI, NvU64_HI32(auth_tag_va)); + NV_PUSH_1U(CBA2, DECRYPT_COPY_AUTH_TAG_ADDR_LO, NvU64_LO32(auth_tag_va)); + + NV_PUSH_1U(CBA2, + METHOD_STREAM_AUTH_TAG_ADDR_HI, + HWVALUE(CBA2, METHOD_STREAM_AUTH_TAG_ADDR_HI, DATA, NvU64_HI32(sign_auth_tag_gpu_va.address))); + + sign_auth_tag_addr_lo = READ_HWVALUE(NvU64_LO32(sign_auth_tag_gpu_va.address), + CBA2, + METHOD_STREAM_AUTH_TAG_ADDR_LO, + DATA); + NV_PUSH_1U(CBA2, + METHOD_STREAM_AUTH_TAG_ADDR_LO, + HWVALUE(CBA2, METHOD_STREAM_AUTH_TAG_ADDR_LO, DATA, sign_auth_tag_addr_lo)); + + execute_with_membar(push); + + sign_push(push, csl_sign_init, sign_auth_tag_ptr); +} diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/kernel-open/nvidia-uvm/uvm_ioctl.h nvidia-open-gpu-kernel-modules-535.161.08/kernel-open/nvidia-uvm/uvm_ioctl.h --- nvidia-open-gpu-kernel-modules-525.147.05/kernel-open/nvidia-uvm/uvm_ioctl.h 2023-10-25 20:33:28.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/kernel-open/nvidia-uvm/uvm_ioctl.h 2024-03-05 22:25:42.000000000 +0000 @@ -1049,6 +1049,41 @@ } UVM_MAP_EXTERNAL_SPARSE_PARAMS; // +// Used to initialise a secondary UVM file-descriptor which holds a +// reference on the memory map to prevent it being torn down without +// first notifying UVM. This is achieved by preventing mmap() calls on +// the secondary file-descriptor so that on process exit +// uvm_mm_release() will be called while the memory map is present +// such that UVM can cleanly shutdown the GPU by handling faults +// instead of cancelling them. +// +// This ioctl must be called after the primary file-descriptor has +// been initialised with the UVM_INITIALIZE ioctl. The primary FD +// should be passed in the uvmFd field and the UVM_MM_INITIALIZE ioctl +// will hold a reference on the primary FD. Therefore uvm_release() is +// guaranteed to be called after uvm_mm_release(). +// +// Once this file-descriptor has been closed the UVM context is +// effectively dead and subsequent operations requiring a memory map +// will fail. Calling UVM_MM_INITIALIZE on a context that has already +// been initialized via any FD will return NV_ERR_INVALID_STATE. +// +// Calling this with a non-UVM file-descriptor in uvmFd will return +// NV_ERR_INVALID_ARGUMENT. Calling this on the same file-descriptor +// as UVM_INITIALIZE or more than once on the same FD will return +// NV_ERR_IN_USE. +// +// Not all platforms require this secondary file-descriptor. On those +// platforms NV_WARN_NOTHING_TO_DO will be returned and users may +// close the file-descriptor at anytime. +#define UVM_MM_INITIALIZE UVM_IOCTL_BASE(75) +typedef struct +{ + NvS32 uvmFd; // IN + NV_STATUS rmStatus; // OUT +} UVM_MM_INITIALIZE_PARAMS; + +// // Temporary ioctls which should be removed before UVM 8 release // Number backwards from 2047 - highest custom ioctl function number // windows can handle. diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/kernel-open/nvidia-uvm/uvm_linux.h nvidia-open-gpu-kernel-modules-535.161.08/kernel-open/nvidia-uvm/uvm_linux.h --- nvidia-open-gpu-kernel-modules-525.147.05/kernel-open/nvidia-uvm/uvm_linux.h 2023-10-25 20:33:27.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/kernel-open/nvidia-uvm/uvm_linux.h 2024-03-05 22:25:42.000000000 +0000 @@ -108,7 +108,7 @@ #endif } - #if defined(CONFIG_HMM_MIRROR) && defined(CONFIG_DEVICE_PRIVATE) && defined(NV_MAKE_DEVICE_EXCLUSIVE_RANGE_PRESENT) + #if defined(CONFIG_HMM_MIRROR) && defined(CONFIG_DEVICE_PRIVATE) && defined(NV_MIGRATE_DEVICE_RANGE_PRESENT) #define UVM_IS_CONFIG_HMM() 1 #else #define UVM_IS_CONFIG_HMM() 0 @@ -128,8 +128,9 @@ // present if we see the callback. // // The callback was added in commit 0f0a327fa12cd55de5e7f8c05a70ac3d047f405e, -// v3.19 (2014-11-13). - #if defined(NV_MMU_NOTIFIER_OPS_HAS_INVALIDATE_RANGE) +// v3.19 (2014-11-13) and renamed in commit 1af5a8109904. + #if defined(NV_MMU_NOTIFIER_OPS_HAS_INVALIDATE_RANGE) || \ + defined(NV_MMU_NOTIFIER_OPS_HAS_ARCH_INVALIDATE_SECONDARY_TLBS) #define UVM_CAN_USE_MMU_NOTIFIERS() 1 #else #define UVM_CAN_USE_MMU_NOTIFIERS() 0 @@ -404,6 +405,7 @@ // 654672d4ba1a6001c365833be895f9477c4d5eab ("locking/atomics: // Add _{acquire|release|relaxed}() variants of some atomic operations") in v4.3 // (2015-08-06). +// TODO: Bug 3849079: We always use this definition on newer kernels. #ifndef atomic_read_acquire #define atomic_read_acquire(p) smp_load_acquire(&(p)->counter) #endif @@ -412,6 +414,24 @@ #define atomic_set_release(p, v) smp_store_release(&(p)->counter, v) #endif +// atomic_long_read_acquire and atomic_long_set_release were added in commit +// b5d47ef9ea5c5fe31d7eabeb79f697629bd9e2cb ("locking/atomics: Switch to +// generated atomic-long") in v5.1 (2019-05-05). +// TODO: Bug 3849079: We always use these definitions on newer kernels. +#define atomic_long_read_acquire uvm_atomic_long_read_acquire +static inline long uvm_atomic_long_read_acquire(atomic_long_t *p) +{ + long val = atomic_long_read(p); + smp_mb(); + return val; +} + +#define atomic_long_set_release uvm_atomic_long_set_release +static inline void uvm_atomic_long_set_release(atomic_long_t *p, long v) +{ + smp_mb(); + atomic_long_set(p, v); +} // Added in 3.11 #ifndef PAGE_ALIGNED @@ -521,6 +541,7 @@ #endif // NV_IS_EXPORT_SYMBOL_PRESENT_int_active_memcg #if defined(NVCPU_X86) || defined(NVCPU_X86_64) + #include #include #endif @@ -528,6 +549,27 @@ #define PAGE_KERNEL_NOENC PAGE_KERNEL #endif +// uvm_pgprot_decrypted is a GPL-aware version of pgprot_decrypted that returns +// the given input when UVM cannot use GPL symbols, or pgprot_decrypted is not +// defined. Otherwise, the function is equivalent to pgprot_decrypted. UVM only +// depends on pgprot_decrypted when the driver is allowed to use GPL symbols: +// both AMD's SEV and Intel's TDX are only supported in conjunction with OpenRM. +// +// It is safe to invoke uvm_pgprot_decrypted in KVM + AMD SEV-SNP guests, even +// if the call is not required, because pgprot_decrypted(PAGE_KERNEL_NOENC) == +// PAGE_KERNEL_NOENC. +// +// pgprot_decrypted was added by commit 21729f81ce8a ("x86/mm: Provide general +// kernel support for memory encryption") in v4.14 (2017-07-18) +static inline pgprot_t uvm_pgprot_decrypted(pgprot_t prot) +{ +#if defined(pgprot_decrypted) + return pgprot_decrypted(prot); +#endif + + return prot; +} + // Commit 1dff8083a024650c75a9c961c38082473ceae8cf (v4.7). // // Archs with CONFIG_MMU should have their own page.h, and can't include diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/kernel-open/nvidia-uvm/uvm_lock.c nvidia-open-gpu-kernel-modules-535.161.08/kernel-open/nvidia-uvm/uvm_lock.c --- nvidia-open-gpu-kernel-modules-525.147.05/kernel-open/nvidia-uvm/uvm_lock.c 2023-10-25 20:33:34.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/kernel-open/nvidia-uvm/uvm_lock.c 2024-03-05 22:25:50.000000000 +0000 @@ -27,7 +27,7 @@ const char *uvm_lock_order_to_string(uvm_lock_order_t lock_order) { - BUILD_BUG_ON(UVM_LOCK_ORDER_COUNT != 26); + BUILD_BUG_ON(UVM_LOCK_ORDER_COUNT != 33); switch (lock_order) { UVM_ENUM_STRING_CASE(UVM_LOCK_ORDER_INVALID); @@ -43,18 +43,25 @@ UVM_ENUM_STRING_CASE(UVM_LOCK_ORDER_GPU_SEMAPHORE_POOL); UVM_ENUM_STRING_CASE(UVM_LOCK_ORDER_RM_API); UVM_ENUM_STRING_CASE(UVM_LOCK_ORDER_RM_GPUS); + UVM_ENUM_STRING_CASE(UVM_LOCK_ORDER_VA_BLOCK_MIGRATE); UVM_ENUM_STRING_CASE(UVM_LOCK_ORDER_VA_BLOCK); + UVM_ENUM_STRING_CASE(UVM_LOCK_ORDER_CONF_COMPUTING_DMA_BUFFER_POOL); UVM_ENUM_STRING_CASE(UVM_LOCK_ORDER_CHUNK_MAPPING); UVM_ENUM_STRING_CASE(UVM_LOCK_ORDER_PAGE_TREE); + UVM_ENUM_STRING_CASE(UVM_LOCK_ORDER_CSL_PUSH); + UVM_ENUM_STRING_CASE(UVM_LOCK_ORDER_CSL_WLC_PUSH); + UVM_ENUM_STRING_CASE(UVM_LOCK_ORDER_CSL_SEC2_PUSH); UVM_ENUM_STRING_CASE(UVM_LOCK_ORDER_PUSH); UVM_ENUM_STRING_CASE(UVM_LOCK_ORDER_PMM); UVM_ENUM_STRING_CASE(UVM_LOCK_ORDER_PMM_PMA); UVM_ENUM_STRING_CASE(UVM_LOCK_ORDER_PMM_ROOT_CHUNK); UVM_ENUM_STRING_CASE(UVM_LOCK_ORDER_CHANNEL); + UVM_ENUM_STRING_CASE(UVM_LOCK_ORDER_WLC_CHANNEL); UVM_ENUM_STRING_CASE(UVM_LOCK_ORDER_TOOLS_VA_SPACE_LIST); UVM_ENUM_STRING_CASE(UVM_LOCK_ORDER_VA_SPACE_EVENTS); UVM_ENUM_STRING_CASE(UVM_LOCK_ORDER_VA_SPACE_TOOLS); UVM_ENUM_STRING_CASE(UVM_LOCK_ORDER_SEMA_POOL_TRACKER); + UVM_ENUM_STRING_CASE(UVM_LOCK_ORDER_SECURE_SEMAPHORE); UVM_ENUM_STRING_CASE(UVM_LOCK_ORDER_LEAF); UVM_ENUM_STRING_DEFAULT(); } diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/kernel-open/nvidia-uvm/uvm_lock.h nvidia-open-gpu-kernel-modules-535.161.08/kernel-open/nvidia-uvm/uvm_lock.h --- nvidia-open-gpu-kernel-modules-525.147.05/kernel-open/nvidia-uvm/uvm_lock.h 2023-10-25 20:33:34.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/kernel-open/nvidia-uvm/uvm_lock.h 2024-03-05 22:25:50.000000000 +0000 @@ -75,26 +75,29 @@ // // Protects: // - gpu->parent->isr.replayable_faults.service_lock: -// Changes to the state of a GPU as it transitions from top-half to bottom-half -// interrupt handler for replayable faults. This lock is acquired for that GPU, -// in the ISR top-half. Then a bottom-half is scheduled (to run in a workqueue). -// Then the bottom-half releases the lock when that GPU's processing appears to -// be done. +// Changes to the state of a GPU as it transitions from top-half to +// bottom-half interrupt handler for replayable faults. This lock is +// acquired for that GPU, in the ISR top-half. Then a bottom-half is +// scheduled (to run in a workqueue). Then the bottom-half releases the +// lock when that GPU's processing appears to be done. +// // - gpu->parent->isr.non_replayable_faults.service_lock: -// Changes to the state of a GPU in the bottom-half for non-replayable faults. -// Non-replayable faults are handed-off from RM instead of directly from the GPU -// hardware. This means that we do not keep receiving interrupts after RM pops -// out the faults from the HW buffer. In order not to miss fault notifications, -// we will always schedule a bottom-half for non-replayable faults if there are -// faults ready to be consumed in the buffer, even if there already is some -// bottom-half running or scheduled. This lock serializes all scheduled bottom -// halves per GPU which service non-replayable faults. +// Changes to the state of a GPU in the bottom-half for non-replayable +// faults. Non-replayable faults are handed-off from RM instead of +// directly from the GPU hardware. This means that we do not keep +// receiving interrupts after RM pops out the faults from the HW buffer. +// In order not to miss fault notifications, we will always schedule a +// bottom-half for non-replayable faults if there are faults ready to be +// consumed in the buffer, even if there already is some bottom-half +// running or scheduled. This lock serializes all scheduled bottom halves +// per GPU which service non-replayable faults. +// // - gpu->parent->isr.access_counters.service_lock: -// Changes to the state of a GPU as it transitions from top-half to bottom-half -// interrupt handler for access counter notifications. This lock is acquired for -// that GPU, in the ISR top-half. Then a bottom-half is scheduled (to run in a -// workqueue). Then the bottom-half releases the lock when that GPU's processing -// appears to be done. +// Changes to the state of a GPU as it transitions from top-half to +// bottom-half interrupt handler for access counter notifications. This +// lock is acquired for that GPU, in the ISR top-half. Then a bottom-half +// is scheduled (to run in a workqueue). Then the bottom-half releases +// the lock when that GPU's processing appears to be done. // // - mmap_lock (mmap_sem in kernels < 5.8) // Order: UVM_LOCK_ORDER_MMAP_LOCK @@ -276,6 +279,15 @@ // Operations not allowed while holding the lock: // - GPU memory allocation which can evict memory (would require nesting // block locks) +// +// - GPU DMA Allocation pool lock (gpu->conf_computing.dma_buffer_pool.lock) +// Order: UVM_LOCK_ORDER_CONF_COMPUTING_DMA_BUFFER_POOL +// Condition: The Confidential Computing feature is enabled +// Exclusive lock (mutex) +// +// Protects: +// - Protect the state of the uvm_conf_computing_dma_buffer_pool_t +// // - Chunk mapping lock (gpu->root_chunk_mappings.bitlocks and // gpu->sysmem_mappings.bitlock) // Order: UVM_LOCK_ORDER_CHUNK_MAPPING @@ -310,6 +322,62 @@ // Operations not allowed while holding this lock // - GPU memory allocation which can evict // +// - CE channel CSL channel pool semaphore +// Order: UVM_LOCK_ORDER_CSL_PUSH +// Condition: The Confidential Computing feature is enabled +// Semaphore per CE channel pool +// +// The semaphore controls concurrent pushes to CE channels that are not WCL +// channels. Secure work submission depends on channel availability in +// GPFIFO entries (as in any other channel type) but also on channel +// locking. Each channel has a lock to enforce ordering of pushes. The +// channel's CSL lock is taken on channel reservation until uvm_push_end. +// When the Confidential Computing feature is enabled, channels are +// stateful, and the CSL lock protects their CSL state/context. +// +// Operations allowed while holding this lock +// - Pushing work to CE channels (except for WLC channels) +// +// - WLC CSL channel pool semaphore +// Order: UVM_LOCK_ORDER_CSL_WLC_PUSH +// Condition: The Confidential Computing feature is enabled +// Semaphore per WLC channel pool +// +// The semaphore controls concurrent pushes to WLC channels. WLC work +// submission depends on channel availability in GPFIFO entries (as in any +// other channel type) but also on channel locking. Each WLC channel has a +// lock to enforce ordering of pushes. The channel's CSL lock is taken on +// channel reservation until uvm_push_end. SEC2 channels are stateful +// channels and the CSL lock protects their CSL state/context. +// +// This lock ORDER is different and sits below the generic channel CSL +// lock and above the SEC2 CSL lock. This reflects the dual nature of WLC +// channels; they use SEC2 indirect work launch during initialization, +// and after their schedule is initialized they provide indirect launch +// functionality to other CE channels. +// +// Operations allowed while holding this lock +// - Pushing work to WLC channels +// +// - SEC2 CSL channel pool semaphore +// Order: UVM_LOCK_ORDER_SEC2_CSL_PUSH +// Condition: The Confidential Computing feature is enabled +// Semaphore per SEC2 channel pool +// +// The semaphore controls concurrent pushes to SEC2 channels. SEC2 work +// submission depends on channel availability in GPFIFO entries (as in any +// other channel type) but also on channel locking. Each SEC2 channel has a +// lock to enforce ordering of pushes. The channel's CSL lock is taken on +// channel reservation until uvm_push_end. SEC2 channels are stateful +// channels and the CSL lock protects their CSL state/context. +// +// This lock ORDER is different and lower than UVM_LOCK_ORDER_CSL_PUSH +// to allow secure work submission to use a SEC2 channel to submit +// work before releasing the CSL lock of the originating channel. +// +// Operations allowed while holding this lock +// - Pushing work to SEC2 channels +// // - Concurrent push semaphore // Order: UVM_LOCK_ORDER_PUSH // Semaphore (uvm_semaphore_t) @@ -339,11 +407,24 @@ // Order: UVM_LOCK_ORDER_CHANNEL // Spinlock (uvm_spinlock_t) or exclusive lock (mutex) // -// Lock protecting the state of all the channels in a channel pool. +// Lock protecting the state of all the channels in a channel pool. The +// channel pool lock documentation contains the guidelines about which lock +// type (mutex or spinlock) to use. +// +// - WLC Channel lock +// Order: UVM_LOCK_ORDER_WLC_CHANNEL +// Condition: The Confidential Computing feature is enabled +// Spinlock (uvm_spinlock_t) +// +// Lock protecting the state of WLC channels in a channel pool. This lock +// is separate from the generic channel lock (UVM_LOCK_ORDER_CHANNEL) +// to allow for indirect worklaunch pushes while holding the main channel +// lock (WLC pushes don't need any of the pushbuffer locks described +// above) // // - Tools global VA space list lock (g_tools_va_space_list_lock) // Order: UVM_LOCK_ORDER_TOOLS_VA_SPACE_LIST -// Reader/writer lock (rw_sempahore) +// Reader/writer lock (rw_semaphore) // // This lock protects the list of VA spaces used when broadcasting // UVM profiling events. @@ -361,6 +442,13 @@ // events come from perf events, both VA_SPACE_EVENTS and VA_SPACE_TOOLS // must be taken to register/report some tools events. // +// - Tracking semaphores +// Order: UVM_LOCK_ORDER_SECURE_SEMAPHORE +// Condition: The Confidential Computing feature is enabled +// +// CE semaphore payloads are encrypted, and require to take the CSL lock +// (UVM_LOCK_ORDER_LEAF) to decrypt the payload. +// // - Leaf locks // Order: UVM_LOCK_ORDER_LEAF // @@ -385,18 +473,25 @@ UVM_LOCK_ORDER_GPU_SEMAPHORE_POOL, UVM_LOCK_ORDER_RM_API, UVM_LOCK_ORDER_RM_GPUS, + UVM_LOCK_ORDER_VA_BLOCK_MIGRATE, UVM_LOCK_ORDER_VA_BLOCK, + UVM_LOCK_ORDER_CONF_COMPUTING_DMA_BUFFER_POOL, UVM_LOCK_ORDER_CHUNK_MAPPING, UVM_LOCK_ORDER_PAGE_TREE, + UVM_LOCK_ORDER_CSL_PUSH, + UVM_LOCK_ORDER_CSL_WLC_PUSH, + UVM_LOCK_ORDER_CSL_SEC2_PUSH, UVM_LOCK_ORDER_PUSH, UVM_LOCK_ORDER_PMM, UVM_LOCK_ORDER_PMM_PMA, UVM_LOCK_ORDER_PMM_ROOT_CHUNK, UVM_LOCK_ORDER_CHANNEL, + UVM_LOCK_ORDER_WLC_CHANNEL, UVM_LOCK_ORDER_TOOLS_VA_SPACE_LIST, UVM_LOCK_ORDER_VA_SPACE_EVENTS, UVM_LOCK_ORDER_VA_SPACE_TOOLS, UVM_LOCK_ORDER_SEMA_POOL_TRACKER, + UVM_LOCK_ORDER_SECURE_SEMAPHORE, UVM_LOCK_ORDER_LEAF, UVM_LOCK_ORDER_COUNT, } uvm_lock_order_t; @@ -909,9 +1004,10 @@ // be the same as the string passed to "spinlock". // See uvm_spin_lock() and uvm_spin_unlock() below as examples. // -#define uvm_assert_spinlock_locked(spinlock) ({ \ - typeof(spinlock) _lock_ = (spinlock); \ - UVM_ASSERT(spin_is_locked(&_lock_->lock) && uvm_check_locked(_lock_, UVM_LOCK_FLAGS_MODE_EXCLUSIVE)); \ +#define uvm_assert_spinlock_locked(spinlock) ({ \ + typeof(spinlock) _lock_ = (spinlock); \ + UVM_ASSERT(spin_is_locked(&_lock_->lock)); \ + UVM_ASSERT(uvm_check_locked(_lock_, UVM_LOCK_FLAGS_MODE_EXCLUSIVE)); \ }) #define uvm_assert_spinlock_unlocked(spinlock) UVM_ASSERT(!spin_is_locked(&(spinlock)->lock)) diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/kernel-open/nvidia-uvm/uvm_map_external.c nvidia-open-gpu-kernel-modules-535.161.08/kernel-open/nvidia-uvm/uvm_map_external.c --- nvidia-open-gpu-kernel-modules-525.147.05/kernel-open/nvidia-uvm/uvm_map_external.c 2023-10-25 20:33:40.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/kernel-open/nvidia-uvm/uvm_map_external.c 2024-03-05 22:26:03.000000000 +0000 @@ -106,6 +106,9 @@ pte_buffer->mapping_info.formatType = map_rm_params->format_type; pte_buffer->mapping_info.elementBits = map_rm_params->element_bits; pte_buffer->mapping_info.compressionType = map_rm_params->compression_type; + if (va_range->type == UVM_VA_RANGE_TYPE_EXTERNAL) + pte_buffer->mapping_info.mappingPageSize = page_size; + pte_buffer->page_size = page_size; pte_buffer->pte_size = uvm_mmu_pte_size(tree, page_size); num_all_ptes = uvm_div_pow2_64(length, page_size); @@ -341,9 +344,8 @@ static uvm_membar_t va_range_downgrade_membar(uvm_va_range_t *va_range, uvm_ext_gpu_map_t *ext_gpu_map) { if (va_range->type == UVM_VA_RANGE_TYPE_CHANNEL) { - if (va_range->channel.aperture == UVM_APERTURE_VID) - return UVM_MEMBAR_GPU; - return UVM_MEMBAR_SYS; + return uvm_hal_downgrade_membar_type(va_range->channel.gpu_va_space->gpu, + va_range->channel.aperture == UVM_APERTURE_VID); } // If there is no mem_handle, this is a sparse mapping. @@ -353,9 +355,8 @@ if (!ext_gpu_map->mem_handle) return UVM_MEMBAR_GPU; - if (ext_gpu_map->is_sysmem || ext_gpu_map->gpu != ext_gpu_map->owning_gpu) - return UVM_MEMBAR_SYS; - return UVM_MEMBAR_GPU; + return uvm_hal_downgrade_membar_type(ext_gpu_map->gpu, + !ext_gpu_map->is_sysmem && ext_gpu_map->gpu == ext_gpu_map->owning_gpu); } NV_STATUS uvm_va_range_map_rm_allocation(uvm_va_range_t *va_range, @@ -398,9 +399,7 @@ page_tree = &gpu_va_space->page_tables; - // Verify that the GPU VA space supports this page size - if ((mem_info->pageSize & page_tree->hal->page_sizes()) == 0) - return NV_ERR_INVALID_ADDRESS; + UVM_ASSERT(uvm_mmu_page_size_supported(page_tree, mem_info->pageSize)); if (va_range->type == UVM_VA_RANGE_TYPE_EXTERNAL) { // We should be never called with ext_gpu_map == NULL @@ -414,13 +413,12 @@ pt_range_vec = &va_range->channel.pt_range_vec; } - if (!IS_ALIGNED(map_offset, mem_info->pageSize) || - map_offset + uvm_range_tree_node_size(node) > mem_info->size) + if (map_offset + uvm_range_tree_node_size(node) > mem_info->size) return NV_ERR_INVALID_OFFSET; - // Consolidate input checks for API-level callers - if (!IS_ALIGNED(node->start, mem_info->pageSize) || !IS_ALIGNED(node->end + 1, mem_info->pageSize)) - return NV_ERR_INVALID_ADDRESS; + UVM_ASSERT(IS_ALIGNED(node->start, mem_info->pageSize) && + IS_ALIGNED(node->end + 1, mem_info->pageSize) && + IS_ALIGNED(map_offset, mem_info->pageSize)); status = uvm_pte_buffer_init(va_range, mapping_gpu, @@ -845,6 +843,10 @@ uvm_ext_gpu_map_t *ext_gpu_map = NULL; uvm_ext_gpu_range_tree_t *range_tree = uvm_ext_gpu_range_tree(va_range, mapping_gpu); UvmGpuMemoryInfo mem_info; + uvm_gpu_va_space_t *gpu_va_space = uvm_gpu_va_space_get(va_space, mapping_gpu); + NvU32 mapping_page_size; + NvU64 alignments; + NvU32 smallest_alignment; NV_STATUS status; uvm_assert_rwsem_locked_read(&va_space->lock); @@ -915,12 +917,25 @@ if (status != NV_OK) goto error; - status = uvm_va_range_map_rm_allocation(va_range, - mapping_gpu, - &mem_info, - map_rm_params, - ext_gpu_map, - out_tracker); + // Determine the proper mapping page size. + // This will be the largest supported page size less than or equal to the + // smallest of the base VA address, length, offset, and allocation page size + // alignments. + alignments = mem_info.pageSize | base | length | map_rm_params->map_offset; + smallest_alignment = alignments & ~(alignments - 1); + + // Check that alignment bits did not get truncated. + UVM_ASSERT(smallest_alignment); + + mapping_page_size = uvm_mmu_biggest_page_size_up_to(&gpu_va_space->page_tables, smallest_alignment); + if (!mapping_page_size) { + status = NV_ERR_INVALID_ADDRESS; + goto error; + } + + mem_info.pageSize = mapping_page_size; + + status = uvm_va_range_map_rm_allocation(va_range, mapping_gpu, &mem_info, map_rm_params, ext_gpu_map, out_tracker); if (status != NV_OK) goto error; diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/kernel-open/nvidia-uvm/uvm_maxwell.c nvidia-open-gpu-kernel-modules-535.161.08/kernel-open/nvidia-uvm/uvm_maxwell.c --- nvidia-open-gpu-kernel-modules-525.147.05/kernel-open/nvidia-uvm/uvm_maxwell.c 2023-10-25 20:33:37.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/kernel-open/nvidia-uvm/uvm_maxwell.c 2024-03-05 22:25:55.000000000 +0000 @@ -1,5 +1,5 @@ /******************************************************************************* - Copyright (c) 2016-2021 NVIDIA Corporation + Copyright (c) 2016-2023 NVIDIA Corporation Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation files (the "Software"), to @@ -33,11 +33,13 @@ // space for UVM internal mappings. // A single top level PDE covers 64 or 128 MB on Maxwell so 128 GB is fine to use. parent_gpu->rm_va_base = 0; - parent_gpu->rm_va_size = 128ull * 1024 * 1024 * 1024; + parent_gpu->rm_va_size = 128 * UVM_SIZE_1GB; - parent_gpu->uvm_mem_va_base = 768ull * 1024 * 1024 * 1024; + parent_gpu->uvm_mem_va_base = 768 * UVM_SIZE_1GB; parent_gpu->uvm_mem_va_size = UVM_MEM_VA_SIZE; + parent_gpu->ce_phys_vidmem_write_supported = true; + // We don't have a compelling use case in UVM-Lite for direct peer // migrations between GPUs, so don't bother setting them up. parent_gpu->peer_copy_mode = UVM_GPU_PEER_COPY_MODE_UNSUPPORTED; @@ -69,4 +71,6 @@ parent_gpu->smc.supported = false; parent_gpu->plc_supported = false; + + parent_gpu->no_ats_range_required = false; } diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/kernel-open/nvidia-uvm/uvm_maxwell_ce.c nvidia-open-gpu-kernel-modules-535.161.08/kernel-open/nvidia-uvm/uvm_maxwell_ce.c --- nvidia-open-gpu-kernel-modules-525.147.05/kernel-open/nvidia-uvm/uvm_maxwell_ce.c 2023-10-25 20:33:38.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/kernel-open/nvidia-uvm/uvm_maxwell_ce.c 2024-03-05 22:25:55.000000000 +0000 @@ -1,5 +1,5 @@ /******************************************************************************* - Copyright (c) 2021 NVIDIA Corporation + Copyright (c) 2021-2023 NVIDIA Corporation Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation files (the "Software"), to @@ -29,10 +29,10 @@ void uvm_hal_maxwell_ce_init(uvm_push_t *push) { // Notably this sends SET_OBJECT with the CE class on subchannel 0 instead - // of the recommended by HW subchannel 4 (subchannel 4 is recommended to + // of the recommended by HW subchannel 4 (subchannel 4 is required to // match CE usage on GRCE). For the UVM driver using subchannel 0 has the - // benefit of also verifying that we ended up on the right PBDMA though as - // SET_OBJECT with CE class on subchannel 0 would fail on GRCE. + // benefit of also verifying that we ended up on the right CE engine type + // though as SET_OBJECT with CE class on subchannel 0 would fail on GRCE. NV_PUSH_1U(B06F, SET_OBJECT, uvm_push_get_gpu(push)->parent->rm_info.ceClass); } @@ -50,38 +50,12 @@ OFFSET_OUT_LOWER, HWVALUE(B0B5, OFFSET_OUT_LOWER, VALUE, NvOffset_LO32(offset_out))); } -// Perform an appropriate membar before a semaphore operation. Returns whether -// the semaphore operation should include a flush. -static bool maxwell_membar_before_semaphore(uvm_push_t *push) -{ - uvm_gpu_t *gpu; - - if (uvm_push_get_and_reset_flag(push, UVM_PUSH_FLAG_NEXT_MEMBAR_NONE)) { - // No MEMBAR requested, don't use a flush. - return false; - } - - if (!uvm_push_get_and_reset_flag(push, UVM_PUSH_FLAG_NEXT_MEMBAR_GPU)) { - // By default do a MEMBAR SYS and for that we can just use flush on the - // semaphore operation. - return true; - } - - // MEMBAR GPU requested, do it on the HOST and skip the CE flush as CE - // doesn't have this capability. - gpu = uvm_push_get_gpu(push); - gpu->parent->host_hal->wait_for_idle(push); - gpu->parent->host_hal->membar_gpu(push); - - return false; -} - void uvm_hal_maxwell_ce_semaphore_release(uvm_push_t *push, NvU64 gpu_va, NvU32 payload) { NvU32 flush_value; bool use_flush; - use_flush = maxwell_membar_before_semaphore(push); + use_flush = uvm_hal_membar_before_semaphore(push); if (use_flush) flush_value = HWCONST(B0B5, LAUNCH_DMA, FLUSH_ENABLE, TRUE); @@ -102,7 +76,7 @@ NvU32 flush_value; bool use_flush; - use_flush = maxwell_membar_before_semaphore(push); + use_flush = uvm_hal_membar_before_semaphore(push); if (use_flush) flush_value = HWCONST(B0B5, LAUNCH_DMA, FLUSH_ENABLE, TRUE); @@ -126,7 +100,7 @@ NvU32 flush_value; bool use_flush; - use_flush = maxwell_membar_before_semaphore(push); + use_flush = uvm_hal_membar_before_semaphore(push); if (use_flush) flush_value = HWCONST(B0B5, LAUNCH_DMA, FLUSH_ENABLE, TRUE); @@ -211,6 +185,12 @@ return 0; } +// Noop, since COPY_TYPE doesn't exist in Maxwell. +NvU32 uvm_hal_maxwell_ce_memcopy_copy_type(uvm_push_t *push, uvm_gpu_address_t dst, uvm_gpu_address_t src) +{ + return 0; +} + void uvm_hal_maxwell_ce_memcopy(uvm_push_t *push, uvm_gpu_address_t dst, uvm_gpu_address_t src, size_t size) { // If >4GB copies ever become an important use case, this function should @@ -221,10 +201,10 @@ NvU32 pipelined_value; NvU32 launch_dma_src_dst_type; NvU32 launch_dma_plc_mode; - bool first_operation = true; + NvU32 copy_type_value; - UVM_ASSERT_MSG(gpu->parent->ce_hal->memcopy_validate(push, dst, src), - "Memcopy validation failed in channel %s, GPU %s", + UVM_ASSERT_MSG(gpu->parent->ce_hal->memcopy_is_valid(push, dst, src), + "Memcopy validation failed in channel %s, GPU %s.\n", push->channel->name, uvm_gpu_name(gpu)); @@ -232,15 +212,16 @@ launch_dma_src_dst_type = gpu->parent->ce_hal->phys_mode(push, dst, src); launch_dma_plc_mode = gpu->parent->ce_hal->plc_mode(); + copy_type_value = gpu->parent->ce_hal->memcopy_copy_type(push, dst, src); + + if (uvm_push_get_and_reset_flag(push, UVM_PUSH_FLAG_CE_NEXT_PIPELINED)) + pipelined_value = HWCONST(B0B5, LAUNCH_DMA, DATA_TRANSFER_TYPE, PIPELINED); + else + pipelined_value = HWCONST(B0B5, LAUNCH_DMA, DATA_TRANSFER_TYPE, NON_PIPELINED); do { NvU32 copy_this_time = (NvU32)min(size, max_single_copy_size); - if (first_operation && uvm_push_get_and_reset_flag(push, UVM_PUSH_FLAG_CE_NEXT_PIPELINED)) - pipelined_value = HWCONST(B0B5, LAUNCH_DMA, DATA_TRANSFER_TYPE, PIPELINED); - else - pipelined_value = HWCONST(B0B5, LAUNCH_DMA, DATA_TRANSFER_TYPE, NON_PIPELINED); - gpu->parent->ce_hal->offset_in_out(push, src.address, dst.address); NV_PUSH_1U(B0B5, LINE_LENGTH_IN, copy_this_time); @@ -253,12 +234,13 @@ HWCONST(B0B5, LAUNCH_DMA, FLUSH_ENABLE, FALSE) | launch_dma_src_dst_type | launch_dma_plc_mode | + copy_type_value | pipelined_value); + pipelined_value = HWCONST(B0B5, LAUNCH_DMA, DATA_TRANSFER_TYPE, PIPELINED); dst.address += copy_this_time; src.address += copy_this_time; size -= copy_this_time; - first_operation = false; } while (size > 0); maxwell_membar_after_transfer(push); @@ -266,11 +248,14 @@ void uvm_hal_maxwell_ce_memcopy_v_to_v(uvm_push_t *push, NvU64 dst_va, NvU64 src_va, size_t size) { - uvm_hal_maxwell_ce_memcopy(push, uvm_gpu_address_virtual(dst_va), uvm_gpu_address_virtual(src_va), size); + uvm_push_get_gpu(push)->parent->ce_hal->memcopy(push, + uvm_gpu_address_virtual(dst_va), + uvm_gpu_address_virtual(src_va), + size); } // Push SET_DST_PHYS mode if needed and return LAUNCH_DMA_DST_TYPE flags -static NvU32 memset_push_phys_mode(uvm_push_t *push, uvm_gpu_address_t dst) +static NvU32 maxwell_memset_push_phys_mode(uvm_push_t *push, uvm_gpu_address_t dst) { if (dst.is_virtual) return HWCONST(B0B5, LAUNCH_DMA, DST_TYPE, VIRTUAL); @@ -290,12 +275,12 @@ NvU32 launch_dma_dst_type; NvU32 launch_dma_plc_mode; - UVM_ASSERT_MSG(gpu->parent->ce_hal->memset_validate(push, dst, memset_element_size), - "Memset validation failed in channel %s, GPU %s", + UVM_ASSERT_MSG(gpu->parent->ce_hal->memset_is_valid(push, dst, size, memset_element_size), + "Memset validation failed in channel %s, GPU %s.\n", push->channel->name, uvm_gpu_name(gpu)); - launch_dma_dst_type = memset_push_phys_mode(push, dst); + launch_dma_dst_type = maxwell_memset_push_phys_mode(push, dst); launch_dma_plc_mode = gpu->parent->ce_hal->plc_mode(); if (uvm_push_get_and_reset_flag(push, UVM_PUSH_FLAG_CE_NEXT_PIPELINED)) @@ -322,7 +307,7 @@ dst.address += memset_this_time * memset_element_size; size -= memset_this_time; - pipelined_value = HWCONST(B0B5, LAUNCH_DMA, DATA_TRANSFER_TYPE, NON_PIPELINED); + pipelined_value = HWCONST(B0B5, LAUNCH_DMA, DATA_TRANSFER_TYPE, PIPELINED); } while (size > 0); maxwell_membar_after_transfer(push); @@ -373,5 +358,27 @@ void uvm_hal_maxwell_ce_memset_v_4(uvm_push_t *push, NvU64 dst_va, NvU32 value, size_t size) { - uvm_hal_maxwell_ce_memset_4(push, uvm_gpu_address_virtual(dst_va), value, size); + uvm_push_get_gpu(push)->parent->ce_hal->memset_4(push, uvm_gpu_address_virtual(dst_va), value, size); +} + +void uvm_hal_maxwell_ce_encrypt_unsupported(uvm_push_t *push, + uvm_gpu_address_t dst, + uvm_gpu_address_t src, + NvU32 size, + uvm_gpu_address_t auth_tag) +{ + uvm_gpu_t *gpu = uvm_push_get_gpu(push); + + UVM_ASSERT_MSG(false, "CE encrypt is not supported on GPU: %s.\n", uvm_gpu_name(gpu)); +} + +void uvm_hal_maxwell_ce_decrypt_unsupported(uvm_push_t *push, + uvm_gpu_address_t dst, + uvm_gpu_address_t src, + NvU32 size, + uvm_gpu_address_t auth_tag) +{ + uvm_gpu_t *gpu = uvm_push_get_gpu(push); + + UVM_ASSERT_MSG(false, "CE decrypt is not supported on GPU: %s.\n", uvm_gpu_name(gpu)); } diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/kernel-open/nvidia-uvm/uvm_maxwell_fault_buffer.c nvidia-open-gpu-kernel-modules-535.161.08/kernel-open/nvidia-uvm/uvm_maxwell_fault_buffer.c --- nvidia-open-gpu-kernel-modules-525.147.05/kernel-open/nvidia-uvm/uvm_maxwell_fault_buffer.c 2023-10-25 20:33:38.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/kernel-open/nvidia-uvm/uvm_maxwell_fault_buffer.c 2024-03-05 22:25:55.000000000 +0000 @@ -1,5 +1,5 @@ /******************************************************************************* - Copyright (c) 2021 NVIDIA Corporation + Copyright (c) 2021-2023 NVIDIA Corporation Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation files (the "Software"), to @@ -62,11 +62,18 @@ return 0; } -void uvm_hal_maxwell_fault_buffer_parse_entry_unsupported(uvm_parent_gpu_t *parent_gpu, - NvU32 index, - uvm_fault_buffer_entry_t *buffer_entry) +uvm_fault_type_t uvm_hal_maxwell_fault_buffer_get_fault_type_unsupported(const NvU32 *fault_entry) +{ + UVM_ASSERT_MSG(false, "fault_buffer_get_fault_type is not supported.\n"); + return UVM_FAULT_TYPE_COUNT; +} + +NV_STATUS uvm_hal_maxwell_fault_buffer_parse_replayable_entry_unsupported(uvm_parent_gpu_t *parent_gpu, + NvU32 index, + uvm_fault_buffer_entry_t *buffer_entry) { UVM_ASSERT_MSG(false, "fault_buffer_parse_entry is not supported on GPU: %s.\n", parent_gpu->name); + return NV_ERR_NOT_SUPPORTED; } bool uvm_hal_maxwell_fault_buffer_entry_is_valid_unsupported(uvm_parent_gpu_t *parent_gpu, NvU32 index) diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/kernel-open/nvidia-uvm/uvm_maxwell_host.c nvidia-open-gpu-kernel-modules-535.161.08/kernel-open/nvidia-uvm/uvm_maxwell_host.c --- nvidia-open-gpu-kernel-modules-525.147.05/kernel-open/nvidia-uvm/uvm_maxwell_host.c 2023-10-25 20:33:38.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/kernel-open/nvidia-uvm/uvm_maxwell_host.c 2024-03-05 22:25:55.000000000 +0000 @@ -217,9 +217,14 @@ HWCONST(A16F, SEMAPHORED, RELEASE_WFI, DIS)); } -void uvm_hal_maxwell_host_set_gpfifo_entry(NvU64 *fifo_entry, NvU64 pushbuffer_va, NvU32 pushbuffer_length) +void uvm_hal_maxwell_host_set_gpfifo_entry(NvU64 *fifo_entry, + NvU64 pushbuffer_va, + NvU32 pushbuffer_length, + uvm_gpfifo_sync_t sync_flag) { NvU64 fifo_entry_value; + const NvU32 sync_value = (sync_flag == UVM_GPFIFO_SYNC_WAIT) ? HWCONST(A16F, GP_ENTRY1, SYNC, WAIT) : + HWCONST(A16F, GP_ENTRY1, SYNC, PROCEED); UVM_ASSERT(!uvm_global_is_suspended()); UVM_ASSERT_MSG(pushbuffer_va % 4 == 0, "pushbuffer va unaligned: %llu\n", pushbuffer_va); @@ -228,7 +233,8 @@ fifo_entry_value = HWVALUE(A16F, GP_ENTRY0, GET, NvU64_LO32(pushbuffer_va) >> 2); fifo_entry_value |= (NvU64)(HWVALUE(A16F, GP_ENTRY1, GET_HI, NvU64_HI32(pushbuffer_va)) | HWVALUE(A16F, GP_ENTRY1, LENGTH, pushbuffer_length >> 2) | - HWCONST(A16F, GP_ENTRY1, PRIV, KERNEL)) << 32; + HWCONST(A16F, GP_ENTRY1, PRIV, KERNEL) | + sync_value) << 32; *fifo_entry = fifo_entry_value; } diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/kernel-open/nvidia-uvm/uvm_maxwell_mmu.c nvidia-open-gpu-kernel-modules-535.161.08/kernel-open/nvidia-uvm/uvm_maxwell_mmu.c --- nvidia-open-gpu-kernel-modules-525.147.05/kernel-open/nvidia-uvm/uvm_maxwell_mmu.c 2023-10-25 20:33:38.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/kernel-open/nvidia-uvm/uvm_maxwell_mmu.c 2024-03-05 22:25:55.000000000 +0000 @@ -1,5 +1,5 @@ /******************************************************************************* - Copyright (c) 2016-2021 NVIDIA Corporation + Copyright (c) 2016-2023 NVIDIA Corporation Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation files (the "Software"), to @@ -106,10 +106,16 @@ return pde_bits; } -static void make_pde_maxwell(void *entry, uvm_mmu_page_table_alloc_t **phys_allocs, NvU32 depth) +static void make_pde_maxwell(void *entry, + uvm_mmu_page_table_alloc_t **phys_allocs, + uvm_page_directory_t *dir, + NvU32 child_index) { NvU64 pde_bits = 0; - UVM_ASSERT(depth == 0); + + UVM_ASSERT(dir); + UVM_ASSERT(dir->depth == 0); + pde_bits |= HWCONST64(_MMU, PDE, SIZE, FULL); pde_bits |= big_half_pde_maxwell(phys_allocs[MMU_BIG]) | small_half_pde_maxwell(phys_allocs[MMU_SMALL]); diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/kernel-open/nvidia-uvm/uvm_maxwell_sec2.c nvidia-open-gpu-kernel-modules-535.161.08/kernel-open/nvidia-uvm/uvm_maxwell_sec2.c --- nvidia-open-gpu-kernel-modules-525.147.05/kernel-open/nvidia-uvm/uvm_maxwell_sec2.c 1970-01-01 00:00:00.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/kernel-open/nvidia-uvm/uvm_maxwell_sec2.c 2024-03-05 22:25:40.000000000 +0000 @@ -0,0 +1,53 @@ +/******************************************************************************* + Copyright (c) 2021-2023 NVIDIA Corporation + + Permission is hereby granted, free of charge, to any person obtaining a copy + of this software and associated documentation files (the "Software"), to + deal in the Software without restriction, including without limitation the + rights to use, copy, modify, merge, publish, distribute, sublicense, and/or + sell copies of the Software, and to permit persons to whom the Software is + furnished to do so, subject to the following conditions: + + The above copyright notice and this permission notice shall be + included in all copies or substantial portions of the Software. + + THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + DEALINGS IN THE SOFTWARE. + +*******************************************************************************/ + +#include "uvm_gpu.h" +#include "uvm_hal.h" +#include "uvm_push.h" +#include "uvm_common.h" + +void uvm_hal_maxwell_sec2_init_noop(uvm_push_t *push) +{ +} + +void uvm_hal_maxwell_sec2_semaphore_release_unsupported(uvm_push_t *push, NvU64 gpu_va, NvU32 payload) +{ + uvm_gpu_t *gpu = uvm_push_get_gpu(push); + UVM_ASSERT_MSG(false, "SEC2 semaphore_release is not supported on GPU: %s.\n", uvm_gpu_name(gpu)); +} + +void uvm_hal_maxwell_sec2_semaphore_timestamp_unsupported(uvm_push_t *push, NvU64 gpu_va) +{ + uvm_gpu_t *gpu = uvm_push_get_gpu(push); + UVM_ASSERT_MSG(false, "SEC2 semaphore_timestamp is not supported on GPU: %s.\n", uvm_gpu_name(gpu)); +} + +void uvm_hal_maxwell_sec2_decrypt_unsupported(uvm_push_t *push, + NvU64 dst_va, + NvU64 src_va, + NvU32 size, + NvU64 auth_tag_va) +{ + uvm_gpu_t *gpu = uvm_push_get_gpu(push); + UVM_ASSERT_MSG(false, "SEC2 decrypt is not supported on GPU: %s.\n", uvm_gpu_name(gpu)); +} diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/kernel-open/nvidia-uvm/uvm_mem.c nvidia-open-gpu-kernel-modules-535.161.08/kernel-open/nvidia-uvm/uvm_mem.c --- nvidia-open-gpu-kernel-modules-525.147.05/kernel-open/nvidia-uvm/uvm_mem.c 2023-10-25 20:33:33.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/kernel-open/nvidia-uvm/uvm_mem.c 2024-03-05 22:25:50.000000000 +0000 @@ -1,5 +1,5 @@ /******************************************************************************* - Copyright (c) 2016-2021 NVIDIA Corporation + Copyright (c) 2016-2023 NVIDIA Corporation Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation files (the "Software"), to @@ -22,6 +22,7 @@ *******************************************************************************/ #include "uvm_mem.h" +#include "uvm_hal_types.h" #include "uvm_mmu.h" #include "uvm_processors.h" #include "uvm_va_space.h" @@ -67,26 +68,15 @@ return true; } -static bool sysmem_can_be_mapped(uvm_mem_t *sysmem) -{ - UVM_ASSERT(uvm_mem_is_sysmem(sysmem)); - - // If SEV is enabled, only unprotected memory can be mapped - if (g_uvm_global.sev_enabled) - return uvm_mem_is_sysmem_dma(sysmem); - - return true; -} - static bool mem_can_be_mapped_on_cpu(uvm_mem_t *mem, bool is_user_space) { if (uvm_mem_is_sysmem(mem)) - return sysmem_can_be_mapped(mem); + return true; if (!vidmem_can_be_mapped(mem, is_user_space)) return false; - return mem->backing_gpu->parent->numa_info.enabled && PAGE_ALIGNED(mem->chunk_size); + return mem->backing_gpu->mem_info.numa.enabled && PAGE_ALIGNED(mem->chunk_size); } static bool mem_can_be_mapped_on_cpu_kernel(uvm_mem_t *mem) @@ -99,10 +89,22 @@ return mem_can_be_mapped_on_cpu(mem, true); } +static bool sysmem_can_be_mapped_on_gpu(uvm_mem_t *sysmem) +{ + UVM_ASSERT(uvm_mem_is_sysmem(sysmem)); + + // In Confidential Computing, only unprotected memory can be mapped on the + // GPU + if (g_uvm_global.conf_computing_enabled) + return uvm_mem_is_sysmem_dma(sysmem); + + return true; +} + static bool mem_can_be_mapped_on_gpu(uvm_mem_t *mem, uvm_gpu_t *gpu, bool is_user_space) { if (uvm_mem_is_sysmem(mem)) - return sysmem_can_be_mapped(mem); + return sysmem_can_be_mapped_on_gpu(mem); if (!vidmem_can_be_mapped(mem, is_user_space)) return false; @@ -312,7 +314,7 @@ // When UVM_PAGE_SIZE_DEFAULT is used on NUMA-enabled GPUs, we force // chunk_size to be PAGE_SIZE at least, to allow CPU mappings. - if (mem->backing_gpu->parent->numa_info.enabled) + if (mem->backing_gpu->mem_info.numa.enabled) chunk_size = max(chunk_size, (NvU32)PAGE_SIZE); return chunk_size; @@ -449,13 +451,16 @@ return gfp_flags; } +// This allocation is a non-protected memory allocation under Confidential +// Computing. +// // There is a tighter coupling between allocation and mapping because of the // allocator UVM must use. Hence, this function does the equivalent of // uvm_mem_map_gpu_phys(). // // In case of failure, the caller is required to handle cleanup by calling // uvm_mem_free -static NV_STATUS mem_alloc_sysmem_dma_chunks(uvm_mem_t *mem, struct mm_struct *mm, gfp_t gfp_flags) +static NV_STATUS mem_alloc_sysmem_dma_chunks(uvm_mem_t *mem, gfp_t gfp_flags) { size_t i; NV_STATUS status; @@ -500,7 +505,7 @@ // In case of failure, the caller is required to handle cleanup by calling // uvm_mem_free -static NV_STATUS mem_alloc_sysmem_chunks(uvm_mem_t *mem, struct mm_struct *mm, gfp_t gfp_flags) +static NV_STATUS mem_alloc_sysmem_chunks(uvm_mem_t *mem, gfp_t gfp_flags) { size_t i; int order; @@ -523,9 +528,10 @@ // In case of failure, the caller is required to handle cleanup by calling // uvm_mem_free -static NV_STATUS mem_alloc_vidmem_chunks(uvm_mem_t *mem, bool zero, bool is_protected) +static NV_STATUS mem_alloc_vidmem_chunks(uvm_mem_t *mem, bool zero, bool is_unprotected) { NV_STATUS status; + uvm_pmm_gpu_memory_type_t mem_type; UVM_ASSERT(uvm_mem_is_vidmem(mem)); @@ -542,14 +548,23 @@ if (!mem->vidmem.chunks) return NV_ERR_NO_MEMORY; - status = uvm_pmm_gpu_alloc_kernel(&mem->backing_gpu->pmm, - mem->chunks_count, - mem->chunk_size, - UVM_PMM_ALLOC_FLAGS_NONE, - mem->vidmem.chunks, - NULL); + // When CC is disabled the behavior is identical to that of PMM, and the + // protection flag is ignored (squashed by PMM internally). + if (is_unprotected) + mem_type = UVM_PMM_GPU_MEMORY_TYPE_KERNEL_UNPROTECTED; + else + mem_type = UVM_PMM_GPU_MEMORY_TYPE_KERNEL_PROTECTED; + + status = uvm_pmm_gpu_alloc(&mem->backing_gpu->pmm, + mem->chunks_count, + mem->chunk_size, + mem_type, + UVM_PMM_ALLOC_FLAGS_NONE, + mem->vidmem.chunks, + NULL); + if (status != NV_OK) { - UVM_ERR_PRINT("pmm_gpu_alloc(count=%zd, size=0x%x) failed: %s\n", + UVM_ERR_PRINT("uvm_pmm_gpu_alloc (count=%zd, size=0x%x) failed: %s\n", mem->chunks_count, mem->chunk_size, nvstatusToString(status)); @@ -559,7 +574,7 @@ return NV_OK; } -static NV_STATUS mem_alloc_chunks(uvm_mem_t *mem, struct mm_struct *mm, bool zero, bool is_protected) +static NV_STATUS mem_alloc_chunks(uvm_mem_t *mem, struct mm_struct *mm, bool zero, bool is_unprotected) { if (uvm_mem_is_sysmem(mem)) { gfp_t gfp_flags; @@ -573,23 +588,15 @@ uvm_memcg_context_start(&memcg_context, mm); if (uvm_mem_is_sysmem_dma(mem)) - status = mem_alloc_sysmem_dma_chunks(mem, mm, gfp_flags); + status = mem_alloc_sysmem_dma_chunks(mem, gfp_flags); else - status = mem_alloc_sysmem_chunks(mem, mm, gfp_flags); + status = mem_alloc_sysmem_chunks(mem, gfp_flags); uvm_memcg_context_end(&memcg_context); return status; } - return mem_alloc_vidmem_chunks(mem, zero, is_protected); -} - -static const char *mem_physical_source(uvm_mem_t *mem) -{ - if (uvm_mem_is_vidmem(mem)) - return uvm_gpu_name(mem->backing_gpu); - - return "CPU"; + return mem_alloc_vidmem_chunks(mem, zero, is_unprotected); } NV_STATUS uvm_mem_map_kernel(uvm_mem_t *mem, const uvm_global_processor_mask_t *mask) @@ -617,8 +624,9 @@ NV_STATUS uvm_mem_alloc(const uvm_mem_alloc_params_t *params, uvm_mem_t **mem_out) { NV_STATUS status; + NvU64 physical_size; uvm_mem_t *mem = NULL; - bool is_protected = false; + bool is_unprotected = false; UVM_ASSERT(params->size > 0); @@ -637,10 +645,15 @@ UVM_ASSERT(mem->chunk_size > 0); - mem->physical_allocation_size = UVM_ALIGN_UP(mem->size, mem->chunk_size); - mem->chunks_count = mem->physical_allocation_size / mem->chunk_size; + physical_size = UVM_ALIGN_UP(mem->size, mem->chunk_size); + mem->chunks_count = physical_size / mem->chunk_size; + + if (params->is_unprotected) + UVM_ASSERT(uvm_mem_is_vidmem(mem)); + + is_unprotected = params->is_unprotected; - status = mem_alloc_chunks(mem, params->mm, params->zero, is_protected); + status = mem_alloc_chunks(mem, params->mm, params->zero, is_unprotected); if (status != NV_OK) goto error; @@ -665,7 +678,7 @@ } UVM_ASSERT(IS_ALIGNED((NvU64)user_addr, mem->chunk_size)); - UVM_ASSERT(mem->physical_allocation_size == mem->size); + UVM_ASSERT(uvm_mem_physical_size(mem) == mem->size); mem->user = uvm_kvmalloc_zero(sizeof(*mem->user)); if (mem->user == NULL) @@ -691,7 +704,7 @@ static NvU64 reserved_gpu_va(uvm_mem_t *mem, uvm_gpu_t *gpu) { - UVM_ASSERT(mem->kernel.range_alloc.aligned_start + mem->physical_allocation_size < gpu->parent->uvm_mem_va_size); + UVM_ASSERT(mem->kernel.range_alloc.aligned_start + uvm_mem_physical_size(mem) < gpu->parent->uvm_mem_va_size); return gpu->parent->uvm_mem_va_base + mem->kernel.range_alloc.aligned_start; } @@ -709,7 +722,7 @@ static NV_STATUS mem_map_cpu_to_sysmem_kernel(uvm_mem_t *mem) { struct page **pages = mem->sysmem.pages; - size_t num_pages = mem->physical_allocation_size / PAGE_SIZE; + size_t num_pages = uvm_mem_physical_size(mem) / PAGE_SIZE; pgprot_t prot = PAGE_KERNEL; UVM_ASSERT(uvm_mem_is_sysmem(mem)); @@ -725,8 +738,8 @@ pages[page_index] = mem_cpu_page(mem, page_index * PAGE_SIZE); } - if (g_uvm_global.sev_enabled) - prot = PAGE_KERNEL_NOENC; + if (g_uvm_global.conf_computing_enabled && uvm_mem_is_sysmem_dma(mem)) + prot = uvm_pgprot_decrypted(PAGE_KERNEL_NOENC); mem->kernel.cpu_addr = vmap(pages, num_pages, VM_MAP, prot); @@ -743,7 +756,7 @@ { struct page **pages; size_t num_chunk_pages = mem->chunk_size / PAGE_SIZE; - size_t num_pages = mem->physical_allocation_size / PAGE_SIZE; + size_t num_pages = uvm_mem_physical_size(mem) / PAGE_SIZE; size_t page_index; size_t chunk_index; @@ -798,7 +811,7 @@ // compound pages in order to be able to use vm_insert_page on them. This // is not currently being exercised because the only allocations using this // are semaphore pools (which typically use a single page). - for (offset = 0; offset < mem->physical_allocation_size; offset += PAGE_SIZE) { + for (offset = 0; offset < uvm_mem_physical_size(mem); offset += PAGE_SIZE) { int ret = vm_insert_page(vma, (unsigned long)mem->user->addr + offset, mem_cpu_page(mem, offset)); if (ret) { UVM_ASSERT_MSG(ret == -ENOMEM, "ret: %d\n", ret); @@ -810,7 +823,7 @@ return NV_OK; error: - unmap_mapping_range(&mem->user->va_space->mapping, (size_t)mem->user->addr, mem->physical_allocation_size, 1); + unmap_mapping_range(mem->user->va_space->mapping, (size_t)mem->user->addr, uvm_mem_physical_size(mem), 1); return status; } @@ -819,7 +832,7 @@ if (!uvm_mem_mapped_on_cpu_user(mem)) return; - unmap_mapping_range(&mem->user->va_space->mapping, (size_t)mem->user->addr, mem->physical_allocation_size, 1); + unmap_mapping_range(mem->user->va_space->mapping, (size_t)mem->user->addr, uvm_mem_physical_size(mem), 1); mem_clear_mapped_on_cpu_user(mem); mem_deinit_user_mapping(mem); } @@ -959,21 +972,17 @@ return uvm_gpu_phys_address(UVM_APERTURE_SYS, dma_addr + offset % mem->chunk_size); } -static bool mem_check_range(uvm_mem_t *mem, NvU64 offset, NvU64 size) +bool uvm_mem_is_physically_contiguous(uvm_mem_t *mem, NvU64 offset, NvU64 size) { UVM_ASSERT(size != 0); - UVM_ASSERT_MSG(UVM_ALIGN_DOWN(offset, mem->chunk_size) == UVM_ALIGN_DOWN(offset + size - 1, mem->chunk_size), - "offset %llu size %llu page_size %u\n", - offset, - size, - mem->chunk_size); - UVM_ASSERT_MSG(offset / mem->chunk_size < mem->chunks_count, "offset %llu\n", offset); - return true; + UVM_ASSERT((offset + size) <= uvm_mem_physical_size(mem)); + + return UVM_ALIGN_DOWN(offset, mem->chunk_size) == UVM_ALIGN_DOWN(offset + size - 1, mem->chunk_size); } uvm_gpu_phys_address_t uvm_mem_gpu_physical(uvm_mem_t *mem, uvm_gpu_t *gpu, NvU64 offset, NvU64 size) { - UVM_ASSERT(mem_check_range(mem, offset, size)); + UVM_ASSERT(uvm_mem_is_physically_contiguous(mem, offset, size)); if (uvm_mem_is_vidmem(mem)) { UVM_ASSERT(uvm_mem_is_local_vidmem(mem, gpu)); @@ -990,10 +999,10 @@ size_t chunk_offset; uvm_gpu_chunk_t *chunk; - UVM_ASSERT(mem_check_range(mem, offset, size)); + UVM_ASSERT(uvm_mem_is_physically_contiguous(mem, offset, size)); if (uvm_mem_is_sysmem(mem) || uvm_mem_is_local_vidmem(mem, accessing_gpu)) - return uvm_mem_gpu_address_physical(mem, accessing_gpu, offset, size); + return uvm_gpu_address_copy(accessing_gpu, uvm_mem_gpu_physical(mem, accessing_gpu, offset, size)); // Peer GPUs may need to use some form of translation (identity mappings, // indirect peers) to copy. @@ -1024,13 +1033,8 @@ static void mem_unmap_gpu(uvm_mem_t *mem, uvm_gpu_t *gpu, uvm_page_table_range_vec_t **range_vec) { - NV_STATUS status; - uvm_membar_t tlb_membar = UVM_MEMBAR_SYS; - - if (uvm_mem_is_local_vidmem(mem, gpu)) - tlb_membar = UVM_MEMBAR_GPU; - - status = uvm_page_table_range_vec_clear_ptes(*range_vec, tlb_membar); + uvm_membar_t tlb_membar = uvm_hal_downgrade_membar_type(gpu, uvm_mem_is_local_vidmem(mem, gpu)); + NV_STATUS status = uvm_page_table_range_vec_clear_ptes(*range_vec, tlb_membar); if (status != NV_OK) UVM_ERR_PRINT("Clearing PTEs failed: %s, GPU %s\n", nvstatusToString(status), uvm_gpu_name(gpu)); @@ -1054,22 +1058,29 @@ .attrs = attrs }; - if (!uvm_gpu_can_address(gpu, gpu_va, mem->size)) - return NV_ERR_OUT_OF_RANGE; - page_size = mem_pick_gpu_page_size(mem, gpu, tree); UVM_ASSERT_MSG(uvm_mmu_page_size_supported(tree, page_size), "page_size 0x%x\n", page_size); + // When the Confidential Computing feature is enabled, DMA allocations are + // majoritarily allocated and managed by a per-GPU DMA buffer pool + // (uvm_conf_computing_dma_buffer_pool_t). Because we would typically + // already hold the DMA_BUFFER_POOL lock at this time, we cannot hold + // the block lock. Allocate PTEs without eviction in this context. + // + // See uvm_pmm_gpu_alloc() + if (uvm_mem_is_sysmem_dma(mem)) + pmm_flags = UVM_PMM_ALLOC_FLAGS_NONE; + status = uvm_page_table_range_vec_create(tree, gpu_va, - mem->physical_allocation_size, + uvm_mem_physical_size(mem), page_size, pmm_flags, range_vec); if (status != NV_OK) { UVM_ERR_PRINT("Failed to init page mapping at [0x%llx, 0x%llx): %s, GPU %s\n", gpu_va, - gpu_va + mem->physical_allocation_size, + gpu_va + uvm_mem_physical_size(mem), nvstatusToString(status), uvm_gpu_name(gpu)); return status; @@ -1079,7 +1090,7 @@ if (status != NV_OK) { UVM_ERR_PRINT("Failed to write PTEs for mapping at [0x%llx, 0x%llx): %s, GPU %s\n", gpu_va, - gpu_va + mem->physical_allocation_size, + gpu_va + uvm_mem_physical_size(mem), nvstatusToString(status), uvm_gpu_name(gpu)); goto error; @@ -1098,7 +1109,7 @@ return NV_OK; return uvm_range_allocator_alloc(&g_free_ranges, - mem->physical_allocation_size, + uvm_mem_physical_size(mem), mem->chunk_size, &mem->kernel.range_alloc); } @@ -1139,7 +1150,7 @@ if (status != NV_OK) return status; - gpu_va = uvm_parent_gpu_canonical_address(gpu->parent, reserved_gpu_va(mem, gpu)); + gpu_va = reserved_gpu_va(mem, gpu); range_vec = &mem->kernel.range_vecs[uvm_global_id_gpu_index(gpu->global_id)]; status = mem_map_gpu(mem, gpu, gpu_va, &gpu->address_space_tree, &attrs, range_vec); @@ -1165,6 +1176,7 @@ NV_STATUS status; uvm_gpu_va_space_t *gpu_va_space; uvm_page_table_range_vec_t **range_vec; + NvU64 gpu_va; UVM_ASSERT(mem_can_be_mapped_on_gpu_user(mem, gpu)); uvm_assert_rwsem_locked(&user_va_space->lock); @@ -1172,6 +1184,10 @@ if (uvm_mem_mapped_on_gpu_user(mem, gpu)) return NV_OK; + gpu_va = (NvU64)user_addr; + if (!uvm_gpu_can_address(gpu, gpu_va, mem->size)) + return NV_ERR_OUT_OF_RANGE; + status = uvm_mem_map_gpu_phys(mem, gpu); if (status != NV_OK) return status; @@ -1183,7 +1199,7 @@ gpu_va_space = uvm_gpu_va_space_get(mem->user->va_space, gpu); range_vec = &mem->user->range_vecs[uvm_global_id_gpu_index(gpu->global_id)]; - status = mem_map_gpu(mem, gpu, (NvU64)mem->user->addr, &gpu_va_space->page_tables, attrs, range_vec); + status = mem_map_gpu(mem, gpu, gpu_va, &gpu_va_space->page_tables, attrs, range_vec); if (status != NV_OK) goto cleanup; @@ -1219,7 +1235,7 @@ static bool mem_can_be_phys_mapped_on_gpu(uvm_mem_t *mem, uvm_gpu_t *gpu) { if (uvm_mem_is_sysmem(mem)) - return sysmem_can_be_mapped(mem); + return sysmem_can_be_mapped_on_gpu(mem); else return uvm_mem_is_local_vidmem(mem, gpu); } @@ -1320,10 +1336,16 @@ uvm_gpu_address_t uvm_mem_gpu_address_virtual_kernel(uvm_mem_t *mem, uvm_gpu_t *gpu) { - return uvm_gpu_address_virtual(uvm_mem_get_gpu_va_kernel(mem, gpu)); + uvm_gpu_address_t addr = uvm_gpu_address_virtual(uvm_mem_get_gpu_va_kernel(mem, gpu)); + if (uvm_conf_computing_mode_enabled(gpu) && mem->dma_owner) + addr.is_unprotected = true; + return addr; } uvm_gpu_address_t uvm_mem_gpu_address_physical(uvm_mem_t *mem, uvm_gpu_t *gpu, NvU64 offset, NvU64 size) { - return uvm_gpu_address_from_phys(uvm_mem_gpu_physical(mem, gpu, offset, size)); + uvm_gpu_address_t addr = uvm_gpu_address_from_phys(uvm_mem_gpu_physical(mem, gpu, offset, size)); + if (uvm_conf_computing_mode_enabled(gpu) && mem->dma_owner) + addr.is_unprotected = true; + return addr; } diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/kernel-open/nvidia-uvm/uvm_mem.h nvidia-open-gpu-kernel-modules-535.161.08/kernel-open/nvidia-uvm/uvm_mem.h --- nvidia-open-gpu-kernel-modules-525.147.05/kernel-open/nvidia-uvm/uvm_mem.h 2023-10-25 20:33:33.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/kernel-open/nvidia-uvm/uvm_mem.h 2024-03-05 22:25:50.000000000 +0000 @@ -86,7 +86,7 @@ // The size of the VA used for mapping uvm_mem_t allocations // 128 GBs should be plenty for internal allocations and fits easily on all // supported architectures. -#define UVM_MEM_VA_SIZE (128ull * 1024 * 1024 * 1024) +#define UVM_MEM_VA_SIZE (128 * UVM_SIZE_1GB) typedef struct { @@ -128,6 +128,11 @@ // has to be aligned to PAGE_SIZE. NvU32 page_size; + // The protection flag is only observed for vidmem allocations when CC is + // enabled. If set to true, the allocation returns unprotected vidmem; + // otherwise, the allocation returns protected vidmem. + bool is_unprotected; + // If true, the allocation is zeroed (scrubbed). bool zero; } uvm_mem_alloc_params_t; @@ -161,11 +166,10 @@ // lifetime of the GPU. For CPU allocations there is no lifetime limitation. uvm_gpu_t *backing_gpu; + // For Confidential Computing, the accessing GPU needs to be known at alloc + // time for sysmem allocations. uvm_gpu_t *dma_owner; - // Size of the physical chunks. - NvU32 chunk_size; - union { struct @@ -194,12 +198,12 @@ // Count of chunks (vidmem) or CPU pages (sysmem) above size_t chunks_count; + // Size of each physical chunk (vidmem) or CPU page (sysmem) + NvU32 chunk_size; + // Size of the allocation NvU64 size; - // Size of the physical allocation backing - NvU64 physical_allocation_size; - uvm_mem_user_mapping_t *user; // Information specific to allocations mapped in UVM internal VA space. @@ -235,6 +239,20 @@ uvm_chunk_sizes_mask_t uvm_mem_kernel_chunk_sizes(uvm_gpu_t *gpu); +// Size of all the physical allocations backing the given memory. +static inline NvU64 uvm_mem_physical_size(const uvm_mem_t *mem) +{ + NvU64 physical_size = mem->chunks_count * mem->chunk_size; + + UVM_ASSERT(mem->size <= physical_size); + + return physical_size; +} + +// Returns true if the memory is physically contiguous in the +// [offset, offset + size) interval. +bool uvm_mem_is_physically_contiguous(uvm_mem_t *mem, NvU64 offset, NvU64 size); + // Allocate memory according to the given allocation parameters. // // In the case of sysmem, the memory is immediately physically accessible from diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/kernel-open/nvidia-uvm/uvm_mem_test.c nvidia-open-gpu-kernel-modules-535.161.08/kernel-open/nvidia-uvm/uvm_mem_test.c --- nvidia-open-gpu-kernel-modules-525.147.05/kernel-open/nvidia-uvm/uvm_mem_test.c 2023-10-25 20:33:42.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/kernel-open/nvidia-uvm/uvm_mem_test.c 2024-03-05 22:26:06.000000000 +0000 @@ -1,5 +1,5 @@ /******************************************************************************* - Copyright (c) 2016-2021 NVIDIA Corporation + Copyright (c) 2016-2023 NVIDIA Corporation Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation files (the "Software"), to @@ -25,6 +25,7 @@ #include "uvm_kvmalloc.h" #include "uvm_mem.h" #include "uvm_push.h" +#include "uvm_conf_computing.h" #include "uvm_test.h" #include "uvm_test_ioctl.h" #include "uvm_va_space.h" @@ -43,10 +44,10 @@ static inline NV_STATUS __alloc_map_sysmem(NvU64 size, uvm_gpu_t *gpu, uvm_mem_t **sys_mem) { - if (g_uvm_global.sev_enabled) + if (g_uvm_global.conf_computing_enabled) return uvm_mem_alloc_sysmem_dma_and_map_cpu_kernel(size, gpu, current->mm, sys_mem); - else - return uvm_mem_alloc_sysmem_and_map_cpu_kernel(size, current->mm, sys_mem); + + return uvm_mem_alloc_sysmem_and_map_cpu_kernel(size, current->mm, sys_mem); } static NV_STATUS check_accessible_from_gpu(uvm_gpu_t *gpu, uvm_mem_t *mem) @@ -62,7 +63,7 @@ verif_size = UVM_ALIGN_UP(verif_size, sizeof(*sys_verif)); - UVM_ASSERT(mem->physical_allocation_size >= verif_size); + UVM_ASSERT(uvm_mem_physical_size(mem) >= verif_size); UVM_ASSERT(verif_size >= sizeof(*sys_verif)); TEST_NV_CHECK_GOTO(__alloc_map_sysmem(verif_size, gpu, &sys_mem), done); @@ -80,17 +81,14 @@ for (offset = 0; offset < verif_size; offset += mem->chunk_size) { uvm_gpu_address_t sys_mem_gpu_address, mem_gpu_address; size_t size_this_time = min((NvU64)mem->chunk_size, verif_size - offset); - bool should_use_pa; TEST_NV_CHECK_GOTO(uvm_push_begin(gpu->channel_manager, UVM_CHANNEL_TYPE_CPU_TO_GPU, &push, " "), done); sys_mem_gpu_address = uvm_mem_gpu_address_virtual_kernel(sys_mem, gpu); sys_mem_gpu_address.address += offset; - should_use_pa = uvm_channel_is_privileged(push.channel); - - if (should_use_pa) { - mem_gpu_address = uvm_mem_gpu_address_physical(mem, gpu, offset, size_this_time); + if (uvm_channel_is_privileged(push.channel)) { + mem_gpu_address = uvm_mem_gpu_address_copy(mem, gpu, offset, size_this_time); } else { mem_gpu_address = uvm_mem_gpu_address_virtual_kernel(mem, gpu); @@ -130,7 +128,7 @@ mem_gpu_address.address += offset; if (uvm_channel_is_privileged(push.channel)) { - sys_mem_gpu_address = uvm_mem_gpu_address_physical(sys_mem, gpu, offset, size_this_time); + sys_mem_gpu_address = uvm_mem_gpu_address_copy(sys_mem, gpu, offset, size_this_time); } else { sys_mem_gpu_address = uvm_mem_gpu_address_virtual_kernel(sys_mem, gpu); @@ -185,7 +183,7 @@ gpu_va = uvm_mem_get_gpu_va_kernel(mem, gpu); TEST_CHECK_RET(gpu_va >= gpu->parent->uvm_mem_va_base); - TEST_CHECK_RET(gpu_va + mem->physical_allocation_size <= gpu->parent->uvm_mem_va_base + gpu->parent->uvm_mem_va_size); + TEST_CHECK_RET(gpu_va + uvm_mem_physical_size(mem) <= gpu->parent->uvm_mem_va_base + gpu->parent->uvm_mem_va_size); // Mapping if already mapped is OK TEST_NV_CHECK_RET(uvm_mem_map_gpu_kernel(mem, gpu)); @@ -212,7 +210,7 @@ char *cpu_addr; if (uvm_mem_is_vidmem(mem)) - UVM_ASSERT(mem->backing_gpu->parent->numa_info.enabled); + UVM_ASSERT(mem->backing_gpu->mem_info.numa.enabled); // Map TEST_NV_CHECK_RET(uvm_mem_map_cpu_kernel(mem)); @@ -315,7 +313,7 @@ TEST_CHECK_GOTO(status == NV_OK, error); if (page_size == UVM_PAGE_SIZE_DEFAULT) { - if (gpu->parent->numa_info.enabled) + if (gpu->mem_info.numa.enabled) TEST_CHECK_GOTO(mem->chunk_size >= PAGE_SIZE && mem->chunk_size <= max(size, (size_t)PAGE_SIZE), error); else TEST_CHECK_GOTO(mem->chunk_size == UVM_PAGE_SIZE_4K || mem->chunk_size <= size, error); @@ -323,7 +321,7 @@ TEST_NV_CHECK_GOTO(test_map_gpu(mem, gpu), error); - if (gpu->parent->numa_info.enabled && (page_size == UVM_PAGE_SIZE_DEFAULT || page_size >= PAGE_SIZE)) + if (gpu->mem_info.numa.enabled && (page_size == UVM_PAGE_SIZE_DEFAULT || page_size >= PAGE_SIZE)) TEST_CHECK_GOTO(test_map_cpu(mem) == NV_OK, error); *mem_out = mem; @@ -337,9 +335,6 @@ static bool should_test_page_size(size_t alloc_size, NvU32 page_size) { - if (g_uvm_global.sev_enabled) - return false; - if (g_uvm_global.num_simulated_devices == 0) return true; @@ -370,6 +365,12 @@ static const int max_supported_page_sizes = 4 + 1; int i; + + // TODO: Bug 3839176: the test is waived on Confidential Computing because + // it assumes that GPU can access system memory without using encryption. + if (uvm_conf_computing_mode_enabled(uvm_va_space_find_first_gpu(va_space))) + return NV_OK; + gpu_count = uvm_processor_mask_get_gpu_count(&va_space->registered_gpus); // +1 for the CPU @@ -468,7 +469,7 @@ page_sizes &= UVM_CHUNK_SIZES_MASK; for_each_page_size(page_size, page_sizes) { TEST_CHECK_GOTO(uvm_mem_alloc_vidmem(page_size - 1, gpu, &mem) == NV_OK, done); - if (gpu->parent->numa_info.enabled) + if (gpu->mem_info.numa.enabled) TEST_CHECK_GOTO(mem->chunk_size >= PAGE_SIZE && mem->chunk_size <= max(page_size, (NvU32)PAGE_SIZE), done); else TEST_CHECK_GOTO(mem->chunk_size < page_size || page_size == smallest_page_size, done); @@ -476,7 +477,7 @@ mem = NULL; TEST_CHECK_GOTO(uvm_mem_alloc_vidmem(page_size, gpu, &mem) == NV_OK, done); - if (gpu->parent->numa_info.enabled) + if (gpu->mem_info.numa.enabled) TEST_CHECK_GOTO(mem->chunk_size == max(page_size, (NvU32)PAGE_SIZE), done); else TEST_CHECK_GOTO(mem->chunk_size == page_size, done); @@ -492,6 +493,41 @@ return status; } +static NV_STATUS test_basic_vidmem_unprotected(uvm_gpu_t *gpu) +{ + NV_STATUS status = NV_OK; + uvm_mem_t *mem = NULL; + + uvm_mem_alloc_params_t params = { 0 }; + params.size = UVM_PAGE_SIZE_4K; + params.backing_gpu = gpu; + params.page_size = UVM_PAGE_SIZE_4K; + + // If CC is enabled, the protection flag is observed. Because currently all + // vidmem is in the protected region, the allocation should succeed. + // + // If CC is disabled, the protection flag is ignored. + params.is_unprotected = false; + TEST_NV_CHECK_RET(uvm_mem_alloc(¶ms, &mem)); + + uvm_mem_free(mem); + mem = NULL; + + // If CC is enabled, the allocation should fail because currently the + // unprotected region is empty. + // + // If CC is disabled, the behavior should be identical to that of a + // protected allocation. + params.is_unprotected = true; + if (uvm_conf_computing_mode_enabled(gpu)) + TEST_CHECK_RET(uvm_mem_alloc(¶ms, &mem) == NV_ERR_NO_MEMORY); + else + TEST_NV_CHECK_RET(uvm_mem_alloc(¶ms, &mem)); + + uvm_mem_free(mem); + return status; +} + static NV_STATUS test_basic_sysmem(void) { NV_STATUS status = NV_OK; @@ -530,15 +566,54 @@ return status; } +static NV_STATUS test_basic_dma_pool(uvm_gpu_t *gpu) +{ + size_t i, j; + size_t num_buffers; + size_t status = NV_OK; + uvm_conf_computing_dma_buffer_t **dma_buffers; + + // If the Confidential Computing feature is disabled, the DMA buffers + // pool is not initialized. + if (!uvm_conf_computing_mode_enabled(gpu)) + return NV_OK; + + // We're going to reclaim one more chunks that the pool have. Triggerring + // one expansion. + num_buffers = gpu->conf_computing.dma_buffer_pool.num_dma_buffers + 1; + dma_buffers = uvm_kvmalloc_zero(sizeof(*dma_buffers) * num_buffers); + if (dma_buffers == NULL) + return NV_ERR_NO_MEMORY; + + for (i = 0; i < num_buffers; ++i) { + status = uvm_conf_computing_dma_buffer_alloc(&gpu->conf_computing.dma_buffer_pool, &dma_buffers[i], NULL); + if (status != NV_OK) + break; + } + + TEST_CHECK_GOTO(gpu->conf_computing.dma_buffer_pool.num_dma_buffers >= num_buffers, done); + TEST_CHECK_GOTO(i == num_buffers, done); + +done: + j = i; + for (i = 0; i < j; ++i) + uvm_conf_computing_dma_buffer_free(&gpu->conf_computing.dma_buffer_pool, dma_buffers[i], NULL); + + uvm_kvfree(dma_buffers); + return status; +} + static NV_STATUS test_basic(uvm_va_space_t *va_space) { uvm_gpu_t *gpu; - TEST_CHECK_RET(test_basic_sysmem() == NV_OK); + TEST_NV_CHECK_RET(test_basic_sysmem()); for_each_va_space_gpu(gpu, va_space) { - TEST_CHECK_RET(test_basic_vidmem(gpu) == NV_OK); - TEST_CHECK_RET(test_basic_sysmem_dma(gpu) == NV_OK); + TEST_NV_CHECK_RET(test_basic_vidmem(gpu)); + TEST_NV_CHECK_RET(test_basic_sysmem_dma(gpu)); + TEST_NV_CHECK_RET(test_basic_vidmem_unprotected(gpu)); + TEST_NV_CHECK_RET(test_basic_dma_pool(gpu)); } return NV_OK; diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/kernel-open/nvidia-uvm/uvm_migrate.c nvidia-open-gpu-kernel-modules-535.161.08/kernel-open/nvidia-uvm/uvm_migrate.c --- nvidia-open-gpu-kernel-modules-525.147.05/kernel-open/nvidia-uvm/uvm_migrate.c 2023-10-25 20:33:40.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/kernel-open/nvidia-uvm/uvm_migrate.c 2024-03-05 22:26:01.000000000 +0000 @@ -86,7 +86,8 @@ // Only map those pages that are not already mapped on destination for_each_va_block_unset_page_in_region_mask(page_index, pages_mapped_on_destination, region) { prot = uvm_va_block_page_compute_highest_permission(va_block, dest_id, page_index); - UVM_ASSERT(prot != UVM_PROT_NONE); + if (prot == UVM_PROT_NONE) + continue; if (va_block_context->mask_by_prot[prot - 1].count++ == 0) uvm_page_mask_zero(&va_block_context->mask_by_prot[prot - 1].page_mask); @@ -133,6 +134,22 @@ // first map operation uvm_page_mask_complement(&va_block_context->caller_page_mask, &va_block->maybe_mapped_pages); + if (uvm_va_block_is_hmm(va_block) && !UVM_ID_IS_CPU(dest_id)) { + // Do not map pages that are already resident on the CPU. This is in + // order to avoid breaking system-wide atomic operations on HMM. HMM's + // implementation of system-side atomic operations involves restricting + // mappings to one processor (CPU or a GPU) at a time. If we were to + // grant a GPU a mapping to system memory, this gets into trouble + // because, on the CPU side, Linux can silently upgrade PTE permissions + // (move from read-only, to read-write, without any MMU notifiers + // firing), thus breaking the model by allowing simultaneous read-write + // access from two separate processors. To avoid that, just don't map + // such pages at all, when migrating. + uvm_page_mask_andnot(&va_block_context->caller_page_mask, + &va_block_context->caller_page_mask, + uvm_va_block_resident_mask_get(va_block, UVM_ID_CPU)); + } + // Only map those pages that are not mapped anywhere else (likely due // to a first touch or a migration). We pass // UvmEventMapRemoteCauseInvalid since the destination processor of a @@ -206,28 +223,39 @@ NV_STATUS status, tracker_status = NV_OK; uvm_assert_mutex_locked(&va_block->lock); + UVM_ASSERT(uvm_hmm_check_context_vma_is_valid(va_block, va_block_context->hmm.vma, region)); - va_block_context->policy = uvm_va_range_get_policy(va_block->va_range); - - if (uvm_va_policy_is_read_duplicate(va_block_context->policy, va_space)) { - status = uvm_va_block_make_resident_read_duplicate(va_block, - va_block_retry, - va_block_context, - dest_id, - region, - NULL, - NULL, - UVM_MAKE_RESIDENT_CAUSE_API_MIGRATE); + if (uvm_va_block_is_hmm(va_block)) { + status = uvm_hmm_va_block_migrate_locked(va_block, + va_block_retry, + va_block_context, + dest_id, + region, + UVM_MAKE_RESIDENT_CAUSE_API_MIGRATE); } else { - status = uvm_va_block_make_resident(va_block, - va_block_retry, - va_block_context, - dest_id, - region, - NULL, - NULL, - UVM_MAKE_RESIDENT_CAUSE_API_MIGRATE); + uvm_va_policy_t *policy = uvm_va_range_get_policy(va_block->va_range); + + if (uvm_va_policy_is_read_duplicate(policy, va_space)) { + status = uvm_va_block_make_resident_read_duplicate(va_block, + va_block_retry, + va_block_context, + dest_id, + region, + NULL, + NULL, + UVM_MAKE_RESIDENT_CAUSE_API_MIGRATE); + } + else { + status = uvm_va_block_make_resident(va_block, + va_block_retry, + va_block_context, + dest_id, + region, + NULL, + NULL, + UVM_MAKE_RESIDENT_CAUSE_API_MIGRATE); + } } if (status == NV_OK && mode == UVM_MIGRATE_MODE_MAKE_RESIDENT_AND_MAP) { @@ -316,7 +344,8 @@ // read-duplication is enabled in the VA range. This is because, when migrating // read-duplicated VA blocks, the source processor doesn't need to be unmapped // (though it may need write access revoked). -static bool va_range_should_do_cpu_preunmap(uvm_va_policy_t *policy, uvm_va_space_t *va_space) +static bool va_range_should_do_cpu_preunmap(const uvm_va_policy_t *policy, + uvm_va_space_t *va_space) { return !uvm_va_policy_is_read_duplicate(policy, va_space); } @@ -342,8 +371,6 @@ if (!va_block) return true; - UVM_ASSERT(va_range_should_do_cpu_preunmap(va_block_context->policy, uvm_va_block_get_va_space(va_block))); - region = uvm_va_block_region_from_start_end(va_block, max(start, va_block->start), min(end, va_block->end)); uvm_mutex_lock(&va_block->lock); @@ -406,7 +433,7 @@ } if (num_unmap_pages > 0) - unmap_mapping_range(&va_range->va_space->mapping, start, end - start + 1, 1); + unmap_mapping_range(va_range->va_space->mapping, start, end - start + 1, 1); } static NV_STATUS uvm_va_range_migrate_multi_block(uvm_va_range_t *va_range, @@ -467,11 +494,9 @@ uvm_tracker_t *out_tracker) { NvU64 preunmap_range_start = start; + uvm_va_policy_t *policy = uvm_va_range_get_policy(va_range); - UVM_ASSERT(va_block_context->policy == uvm_va_range_get_policy(va_range)); - - should_do_cpu_preunmap = should_do_cpu_preunmap && va_range_should_do_cpu_preunmap(va_block_context->policy, - va_range->va_space); + should_do_cpu_preunmap = should_do_cpu_preunmap && va_range_should_do_cpu_preunmap(policy, va_range->va_space); // Divide migrations into groups of contiguous VA blocks. This is to trigger // CPU unmaps for that region before the migration starts. @@ -524,6 +549,17 @@ NV_STATUS status = NV_OK; bool skipped_migrate = false; + if (!first_va_range) { + // For HMM, we iterate over va_blocks since there is no va_range. + return uvm_hmm_migrate_ranges(va_space, + va_block_context, + base, + length, + dest_id, + mode, + out_tracker); + } + UVM_ASSERT(first_va_range == uvm_va_space_iter_first(va_space, base, base)); va_range_last = NULL; @@ -537,8 +573,6 @@ break; } - va_block_context->policy = uvm_va_range_get_policy(va_range); - // For UVM-Lite GPUs, the CUDA driver may suballocate a single va_range // into many range groups. For this reason, we iterate over each va_range first // then through the range groups within. @@ -594,10 +628,10 @@ NvU64 length, uvm_processor_id_t dest_id, NvU32 migrate_flags, + uvm_va_range_t *first_va_range, uvm_tracker_t *out_tracker) { NV_STATUS status = NV_OK; - uvm_va_range_t *first_va_range = uvm_va_space_iter_first(va_space, base, base); uvm_va_block_context_t *va_block_context; bool do_mappings; bool do_two_passes; @@ -606,9 +640,6 @@ uvm_assert_rwsem_locked(&va_space->lock); - if (!first_va_range || first_va_range->type != UVM_VA_RANGE_TYPE_MANAGED) - return NV_ERR_INVALID_ADDRESS; - // If the GPU has its memory disabled, just skip the migration and let // faults take care of things. if (!uvm_va_space_processor_has_memory(va_space, dest_id)) @@ -616,6 +647,9 @@ if (mm) uvm_assert_mmap_lock_locked(mm); + else if (!first_va_range) + return NV_ERR_INVALID_ADDRESS; + va_block_context = uvm_va_block_context_alloc(mm); if (!va_block_context) return NV_ERR_NO_MEMORY; @@ -638,7 +672,9 @@ // 1- Transfer all VA blocks (do not add mappings) // 2- Go block by block reexecuting the transfer (in case someone moved it // since the first pass), and adding the mappings. - is_single_block = is_migration_single_block(first_va_range, base, length); + // + // For HMM (!first_va_range), we always do a single pass. + is_single_block = !first_va_range || is_migration_single_block(first_va_range, base, length); do_mappings = UVM_ID_IS_GPU(dest_id) || !(migrate_flags & UVM_MIGRATE_FLAG_SKIP_CPU_MAP); do_two_passes = do_mappings && !is_single_block; @@ -854,6 +890,7 @@ if ((params->flags & UVM_MIGRATE_FLAGS_TEST_ALL) && !uvm_enable_builtin_tests) { UVM_INFO_PRINT("Test flag set for UVM_MIGRATE. Did you mean to insmod with uvm_enable_builtin_tests=1?\n"); + UVM_INFO_PRINT("TEMP\n"); return NV_ERR_INVALID_ARGUMENT; } @@ -908,34 +945,45 @@ tracker_ptr = &tracker; if (params->length > 0) { - status = uvm_api_range_type_check(va_space, mm, params->base, params->length); - if (status == NV_OK) { + uvm_api_range_type_t type; + + type = uvm_api_range_type_check(va_space, mm, params->base, params->length); + if (type == UVM_API_RANGE_TYPE_INVALID) { + status = NV_ERR_INVALID_ADDRESS; + goto done; + } + + if (type == UVM_API_RANGE_TYPE_ATS) { + uvm_migrate_args_t uvm_migrate_args = + { + .va_space = va_space, + .mm = mm, + .start = params->base, + .length = params->length, + .dst_id = (dest_gpu ? dest_gpu->id : UVM_ID_CPU), + .dst_node_id = (int)params->cpuNumaNode, + .populate_permissions = UVM_POPULATE_PERMISSIONS_INHERIT, + .touch = false, + .skip_mapped = false, + .populate_on_cpu_alloc_failures = false, + .user_space_start = ¶ms->userSpaceStart, + .user_space_length = ¶ms->userSpaceLength, + }; + + status = uvm_migrate_pageable(&uvm_migrate_args); + } + else { status = uvm_migrate(va_space, mm, params->base, params->length, (dest_gpu ? dest_gpu->id : UVM_ID_CPU), params->flags, + uvm_va_space_iter_first(va_space, + params->base, + params->base), tracker_ptr); } - else if (status == NV_WARN_NOTHING_TO_DO) { - uvm_migrate_args_t uvm_migrate_args = - { - .va_space = va_space, - .mm = mm, - .start = params->base, - .length = params->length, - .dst_id = (dest_gpu ? dest_gpu->id : UVM_ID_CPU), - .dst_node_id = (int)params->cpuNumaNode, - .populate_permissions = UVM_POPULATE_PERMISSIONS_INHERIT, - .touch = false, - .skip_mapped = false, - .user_space_start = ¶ms->userSpaceStart, - .user_space_length = ¶ms->userSpaceLength, - }; - - status = uvm_migrate_pageable(&uvm_migrate_args); - } } done: @@ -1029,10 +1077,26 @@ NvU64 start = rgr->node.start; NvU64 length = rgr->node.end - rgr->node.start + 1; - if (gpu && !uvm_gpu_can_address(gpu, start, length)) + if (gpu && !uvm_gpu_can_address(gpu, start, length)) { status = NV_ERR_OUT_OF_RANGE; - else - status = uvm_migrate(va_space, mm, start, length, dest_id, migrate_flags, &local_tracker); + } + else { + uvm_va_range_t *first_va_range = uvm_va_space_iter_first(va_space, start, start); + + if (!first_va_range || first_va_range->type != UVM_VA_RANGE_TYPE_MANAGED) { + status = NV_ERR_INVALID_ADDRESS; + goto done; + } + + status = uvm_migrate(va_space, + mm, + start, + length, + dest_id, + migrate_flags, + first_va_range, + &local_tracker); + } if (status != NV_OK) goto done; diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/kernel-open/nvidia-uvm/uvm_migrate_pageable.c nvidia-open-gpu-kernel-modules-535.161.08/kernel-open/nvidia-uvm/uvm_migrate_pageable.c --- nvidia-open-gpu-kernel-modules-525.147.05/kernel-open/nvidia-uvm/uvm_migrate_pageable.c 2023-10-25 20:33:40.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/kernel-open/nvidia-uvm/uvm_migrate_pageable.c 2024-03-05 22:26:02.000000000 +0000 @@ -63,7 +63,7 @@ if (owning_gpu == copying_gpu) { // Local vidmem address - *gpu_addr = uvm_gpu_address_from_phys(uvm_gpu_page_to_phys_address(owning_gpu, page)); + *gpu_addr = uvm_gpu_address_copy(owning_gpu, uvm_gpu_page_to_phys_address(owning_gpu, page)); } else if (direct_peer) { // Direct GPU peer @@ -88,25 +88,13 @@ __set_bit(page_index, state->dma.page_mask); - *gpu_addr = uvm_gpu_address_physical(UVM_APERTURE_SYS, state->dma.addrs[page_index]); + *gpu_addr = uvm_gpu_address_copy(copying_gpu, + uvm_gpu_phys_address(UVM_APERTURE_SYS, state->dma.addrs[page_index])); } return NV_OK; } -// Return the GPU identified with the given NUMA node id -static uvm_gpu_t *get_gpu_from_node_id(uvm_va_space_t *va_space, int node_id) -{ - uvm_gpu_t *gpu; - - for_each_va_space_gpu(gpu, va_space) { - if (uvm_gpu_numa_info(gpu)->node_id == node_id) - return gpu; - } - - return NULL; -} - // Create a new push to zero pages on dst_id static NV_STATUS migrate_vma_zero_begin_push(uvm_va_space_t *va_space, uvm_processor_id_t dst_id, @@ -169,7 +157,7 @@ // NUMA-enabled GPUs can copy to any other NUMA node in the system even if // P2P access has not been explicitly enabled (ie va_space->can_copy_from // is not set). - if (!gpu->parent->numa_info.enabled) { + if (!gpu->mem_info.numa.enabled) { UVM_ASSERT_MSG(uvm_processor_mask_test(&va_space->can_copy_from[uvm_id_value(gpu->id)], dst_id), "GPU %s dst %s src %s\n", uvm_va_space_processor_name(va_space, gpu->id), @@ -281,7 +269,7 @@ continue; } - src_gpu = get_gpu_from_node_id(uvm_migrate_args->va_space, src_nid); + src_gpu = uvm_va_space_find_gpu_with_memory_node_id(uvm_migrate_args->va_space, src_nid); // Already resident on a node with no CPUs that doesn't belong to a // GPU, don't move @@ -519,6 +507,22 @@ return NV_OK; } +void migrate_vma_cleanup_pages(unsigned long *dst, unsigned long npages) +{ + unsigned long i; + + for (i = 0; i < npages; i++) { + struct page *dst_page = migrate_pfn_to_page(dst[i]); + + if (!dst_page) + continue; + + unlock_page(dst_page); + __free_page(dst_page); + dst[i] = 0; + } +} + void uvm_migrate_vma_alloc_and_copy(struct migrate_vma *args, migrate_vma_state_t *state) { struct vm_area_struct *vma = args->vma; @@ -543,6 +547,10 @@ if (state->status == NV_OK) state->status = tracker_status; + + // Mark all pages as not migrating if we're failing + if (state->status != NV_OK) + migrate_vma_cleanup_pages(args->dst, state->num_pages); } void uvm_migrate_vma_alloc_and_copy_helper(struct vm_area_struct *vma, @@ -814,7 +822,7 @@ // If the destination is the CPU, signal user-space to retry with a // different node. Otherwise, just try to populate anywhere in the // system - if (UVM_ID_IS_CPU(uvm_migrate_args->dst_id)) { + if (UVM_ID_IS_CPU(uvm_migrate_args->dst_id) && !uvm_migrate_args->populate_on_cpu_alloc_failures) { *next_addr = start + find_first_bit(state->scratch2_mask, num_pages) * PAGE_SIZE; return NV_ERR_MORE_PROCESSING_REQUIRED; } @@ -828,6 +836,17 @@ return NV_OK; } +NV_STATUS uvm_test_skip_migrate_vma(UVM_TEST_SKIP_MIGRATE_VMA_PARAMS *params, struct file *filp) +{ + uvm_va_space_t *va_space = uvm_va_space_get(filp); + + uvm_va_space_down_write(va_space); + va_space->test.skip_migrate_vma = params->skip; + uvm_va_space_up_write(va_space); + + return NV_OK; +} + static NV_STATUS migrate_pageable_vma(struct vm_area_struct *vma, unsigned long start, unsigned long outer, @@ -850,6 +869,9 @@ start = max(start, vma->vm_start); outer = min(outer, vma->vm_end); + if (va_space->test.skip_migrate_vma) + return NV_WARN_NOTHING_TO_DO; + // TODO: Bug 2419180: support file-backed pages in migrate_vma, when // support for it is added to the Linux kernel if (!vma_is_anonymous(vma)) @@ -912,7 +934,9 @@ bool touch = uvm_migrate_args->touch; uvm_populate_permissions_t populate_permissions = uvm_migrate_args->populate_permissions; - UVM_ASSERT(!vma_is_anonymous(vma) || uvm_processor_mask_empty(&va_space->registered_gpus)); + UVM_ASSERT(va_space->test.skip_migrate_vma || + !vma_is_anonymous(vma) || + uvm_processor_mask_empty(&va_space->registered_gpus)); // We can't use migrate_vma to move the pages as desired. Normally // this fallback path is supposed to populate the memory then inform @@ -973,20 +997,18 @@ // We only check that dst_node_id is a valid node in the system and it // doesn't correspond to a GPU node. This is fine because // alloc_pages_node will clamp the allocation to - // cpuset_current_mems_allowed, and uvm_migrate_pageable is only called - // from process context (uvm_migrate) when dst_id is CPU. UVM bottom - // half never calls uvm_migrate_pageable when dst_id is CPU. So, assert - // that we're in a user thread. However, this would need to change if we - // wanted to call this function from a bottom half with CPU dst_id. - UVM_ASSERT(!(current->flags & PF_KTHREAD)); - - if (!nv_numa_node_has_memory(dst_node_id) || get_gpu_from_node_id(va_space, dst_node_id) != NULL) + // cpuset_current_mems_allowed when uvm_migrate_pageable is called from + // process context (uvm_migrate) when dst_id is CPU. UVM bottom half + // calls uvm_migrate_pageable with CPU dst_id only when the VMA memory + // policy is set to dst_node_id and dst_node_id is not NUMA_NO_NODE. + if (!nv_numa_node_has_memory(dst_node_id) || + uvm_va_space_find_gpu_with_memory_node_id(va_space, dst_node_id) != NULL) return NV_ERR_INVALID_ARGUMENT; } else { // Incoming dst_node_id is only valid if dst_id belongs to the CPU. Use // dst_node_id as the GPU node id if dst_id doesn't belong to the CPU. - uvm_migrate_args->dst_node_id = uvm_gpu_numa_info(uvm_va_space_get_gpu(va_space, dst_id))->node_id; + uvm_migrate_args->dst_node_id = uvm_gpu_numa_node(uvm_va_space_get_gpu(va_space, dst_id)); } state = kmem_cache_alloc(g_uvm_migrate_vma_state_cache, NV_UVM_GFP_FLAGS); diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/kernel-open/nvidia-uvm/uvm_migrate_pageable.h nvidia-open-gpu-kernel-modules-535.161.08/kernel-open/nvidia-uvm/uvm_migrate_pageable.h --- nvidia-open-gpu-kernel-modules-525.147.05/kernel-open/nvidia-uvm/uvm_migrate_pageable.h 2023-10-25 20:33:40.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/kernel-open/nvidia-uvm/uvm_migrate_pageable.h 2024-03-05 22:26:03.000000000 +0000 @@ -34,8 +34,8 @@ { uvm_va_space_t *va_space; struct mm_struct *mm; - unsigned long start; - unsigned long length; + const unsigned long start; + const unsigned long length; uvm_processor_id_t dst_id; // dst_node_id may be clobbered by uvm_migrate_pageable(). @@ -43,6 +43,7 @@ uvm_populate_permissions_t populate_permissions; bool touch : 1; bool skip_mapped : 1; + bool populate_on_cpu_alloc_failures : 1; NvU64 *user_space_start; NvU64 *user_space_length; } uvm_migrate_args_t; @@ -58,11 +59,13 @@ #ifdef UVM_MIGRATE_VMA_SUPPORTED #include -// The calls to migrate_vma are capped at 32MB to set an upper bound on the +// The calls to migrate_vma are capped at 512 pages to set an upper bound on the // amount of metadata that needs to be allocated for the operation. This number -// was chosen because performance seems to plateau at this size. -#define UVM_MIGRATE_VMA_MAX_SIZE (32UL * 1024 * 1024) -#define UVM_MIGRATE_VMA_MAX_PAGES (UVM_MIGRATE_VMA_MAX_SIZE >> PAGE_SHIFT) +// was chosen because performance seems to plateau at this size on 64K-pages +// kernels. On kernels with PAGE_SIZE == 4K, 512 pages correspond to 2M VA block, +// which is also a standard size for batch operations. +#define UVM_MIGRATE_VMA_MAX_PAGES (512UL) +#define UVM_MIGRATE_VMA_MAX_SIZE (UVM_MIGRATE_VMA_MAX_PAGES * PAGE_SIZE) typedef struct { @@ -215,6 +218,9 @@ NV_STATUS uvm_migrate_pageable_init(void); void uvm_migrate_pageable_exit(void); + +NV_STATUS uvm_test_skip_migrate_vma(UVM_TEST_SKIP_MIGRATE_VMA_PARAMS *params, struct file *filp); + #else // UVM_MIGRATE_VMA_SUPPORTED static NV_STATUS uvm_migrate_pageable(uvm_migrate_args_t *uvm_migrate_args) @@ -248,6 +254,10 @@ { } +static inline NV_STATUS uvm_test_skip_migrate_vma(UVM_TEST_SKIP_MIGRATE_VMA_PARAMS *params, struct file *filp) +{ + return NV_OK; +} #endif // UVM_MIGRATE_VMA_SUPPORTED #endif diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/kernel-open/nvidia-uvm/uvm_mmu.c nvidia-open-gpu-kernel-modules-535.161.08/kernel-open/nvidia-uvm/uvm_mmu.c --- nvidia-open-gpu-kernel-modules-525.147.05/kernel-open/nvidia-uvm/uvm_mmu.c 2023-10-25 20:33:36.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/kernel-open/nvidia-uvm/uvm_mmu.c 2024-03-05 22:25:54.000000000 +0000 @@ -34,6 +34,7 @@ #include "uvm_mem.h" #include "uvm_va_space.h" +#include // The page tree has 6 levels on Hopper+ GPUs, and the root is never freed by a // normal 'put' operation which leaves a maximum of 5 levels. @@ -244,28 +245,234 @@ dir->ref_count += range->entry_count; } +static bool uvm_mmu_use_cpu(uvm_page_tree_t *tree) +{ + // When physical CE writes can't be used for vidmem we use a flat virtual + // mapping instead. The GPU PTEs for that flat mapping have to be + // bootstrapped using the CPU. + return tree->location != UVM_APERTURE_SYS && + !tree->gpu->parent->ce_phys_vidmem_write_supported && + !tree->gpu->static_flat_mapping.ready; +} + +// uvm_mmu_page_table_page() and the uvm_mmu_page_table_cpu_* family of +// functions can only be used when uvm_mmu_use_cpu() returns true, which implies +// a coherent system. + +static struct page *uvm_mmu_page_table_page(uvm_gpu_t *gpu, uvm_mmu_page_table_alloc_t *phys_alloc) +{ + // All platforms that require CPU PTE writes for bootstrapping can fit + // tables within a page. + UVM_ASSERT(phys_alloc->size <= PAGE_SIZE); + + if (phys_alloc->addr.aperture == UVM_APERTURE_SYS) + return phys_alloc->handle.page; + + return uvm_gpu_chunk_to_page(&gpu->pmm, phys_alloc->handle.chunk); +} + +static void *uvm_mmu_page_table_cpu_map(uvm_gpu_t *gpu, uvm_mmu_page_table_alloc_t *phys_alloc) +{ + struct page *page = uvm_mmu_page_table_page(gpu, phys_alloc); + NvU64 page_offset = offset_in_page(phys_alloc->addr.address); + return (char *)kmap(page) + page_offset; +} + +static void uvm_mmu_page_table_cpu_unmap(uvm_gpu_t *gpu, uvm_mmu_page_table_alloc_t *phys_alloc) +{ + kunmap(uvm_mmu_page_table_page(gpu, phys_alloc)); +} + +static void uvm_mmu_page_table_cpu_memset_8(uvm_gpu_t *gpu, + uvm_mmu_page_table_alloc_t *phys_alloc, + NvU32 start_index, + NvU64 pattern, + NvU32 num_entries) +{ + NvU64 *ptr = uvm_mmu_page_table_cpu_map(gpu, phys_alloc); + size_t i; + + UVM_ASSERT(IS_ALIGNED((uintptr_t)ptr, sizeof(*ptr))); + UVM_ASSERT((start_index + num_entries) * sizeof(*ptr) <= phys_alloc->size); + + for (i = 0; i < num_entries; i++) + ptr[start_index + i] = pattern; + + uvm_mmu_page_table_cpu_unmap(gpu, phys_alloc); +} + +static void uvm_mmu_page_table_cpu_memset_16(uvm_gpu_t *gpu, + uvm_mmu_page_table_alloc_t *phys_alloc, + NvU32 start_index, + NvU64 *pattern, + NvU32 num_entries) +{ + struct + { + NvU64 u0, u1; + } *ptr; + size_t i; + + ptr = uvm_mmu_page_table_cpu_map(gpu, phys_alloc); + UVM_ASSERT(IS_ALIGNED((uintptr_t)ptr, sizeof(*ptr))); + UVM_ASSERT((start_index + num_entries) * sizeof(*ptr) <= phys_alloc->size); + + for (i = 0; i < num_entries; i++) + memcpy(&ptr[start_index + i], pattern, sizeof(*ptr)); + + uvm_mmu_page_table_cpu_unmap(gpu, phys_alloc); +} + +static void pde_fill_cpu(uvm_page_tree_t *tree, + uvm_page_directory_t *directory, + NvU32 start_index, + NvU32 pde_count, + uvm_mmu_page_table_alloc_t **phys_addr) +{ + NvU64 pde_data[2], entry_size; + NvU32 i; + + UVM_ASSERT(uvm_mmu_use_cpu(tree)); + + entry_size = tree->hal->entry_size(directory->depth); + UVM_ASSERT(sizeof(pde_data) >= entry_size); + + for (i = 0; i < pde_count; i++) { + tree->hal->make_pde(pde_data, phys_addr, directory, start_index + i); + + if (entry_size == sizeof(pde_data[0])) + uvm_mmu_page_table_cpu_memset_8(tree->gpu, &directory->phys_alloc, start_index + i, pde_data[0], 1); + else + uvm_mmu_page_table_cpu_memset_16(tree->gpu, &directory->phys_alloc, start_index + i, pde_data, 1); + } +} + +static void pde_fill_gpu(uvm_page_tree_t *tree, + uvm_page_directory_t *directory, + NvU32 start_index, + NvU32 pde_count, + uvm_mmu_page_table_alloc_t **phys_addr, + uvm_push_t *push) +{ + NvU64 pde_data[2], entry_size; + uvm_gpu_address_t pde_entry_addr = uvm_mmu_gpu_address(tree->gpu, directory->phys_alloc.addr); + NvU32 max_inline_entries; + uvm_push_flag_t push_membar_flag = UVM_PUSH_FLAG_COUNT; + uvm_gpu_address_t inline_data_addr; + uvm_push_inline_data_t inline_data; + NvU32 entry_count, i, j; + + UVM_ASSERT(!uvm_mmu_use_cpu(tree)); + + entry_size = tree->hal->entry_size(directory->depth); + UVM_ASSERT(sizeof(pde_data) >= entry_size); + + max_inline_entries = UVM_PUSH_INLINE_DATA_MAX_SIZE / entry_size; + + if (uvm_push_get_and_reset_flag(push, UVM_PUSH_FLAG_NEXT_MEMBAR_NONE)) + push_membar_flag = UVM_PUSH_FLAG_NEXT_MEMBAR_NONE; + else if (uvm_push_get_and_reset_flag(push, UVM_PUSH_FLAG_NEXT_MEMBAR_GPU)) + push_membar_flag = UVM_PUSH_FLAG_NEXT_MEMBAR_GPU; + + pde_entry_addr.address += start_index * entry_size; + + for (i = 0; i < pde_count;) { + // All but the first memory operation can be pipelined. We respect the + // caller's pipelining settings for the first push. + if (i != 0) + uvm_push_set_flag(push, UVM_PUSH_FLAG_CE_NEXT_PIPELINED); + + entry_count = min(pde_count - i, max_inline_entries); + + // No membar is needed until the last memory operation. Otherwise, + // use caller's membar flag. + if ((i + entry_count) < pde_count) + uvm_push_set_flag(push, UVM_PUSH_FLAG_NEXT_MEMBAR_NONE); + else if (push_membar_flag != UVM_PUSH_FLAG_COUNT) + uvm_push_set_flag(push, push_membar_flag); + + uvm_push_inline_data_begin(push, &inline_data); + for (j = 0; j < entry_count; j++) { + tree->hal->make_pde(pde_data, phys_addr, directory, start_index + i + j); + uvm_push_inline_data_add(&inline_data, pde_data, entry_size); + } + inline_data_addr = uvm_push_inline_data_end(&inline_data); + + tree->gpu->parent->ce_hal->memcopy(push, pde_entry_addr, inline_data_addr, entry_count * entry_size); + + i += entry_count; + pde_entry_addr.address += entry_size * entry_count; + } +} + +// pde_fill() populates pde_count PDE entries (starting at start_index) with +// the same mapping, i.e., with the same physical address (phys_addr). +// pde_fill() is optimized for pde_count == 1, which is the common case. +static void pde_fill(uvm_page_tree_t *tree, + uvm_page_directory_t *directory, + NvU32 start_index, + NvU32 pde_count, + uvm_mmu_page_table_alloc_t **phys_addr, + uvm_push_t *push) +{ + UVM_ASSERT(start_index + pde_count <= uvm_mmu_page_tree_entries(tree, directory->depth, UVM_PAGE_SIZE_AGNOSTIC)); + + if (push) + pde_fill_gpu(tree, directory, start_index, pde_count, phys_addr, push); + else + pde_fill_cpu(tree, directory, start_index, pde_count, phys_addr); +} + static void phys_mem_init(uvm_page_tree_t *tree, NvU32 page_size, uvm_page_directory_t *dir, uvm_push_t *push) { - NvU64 clear_bits[2]; - uvm_mmu_mode_hal_t *hal = tree->hal; + NvU32 entries_count = uvm_mmu_page_tree_entries(tree, dir->depth, page_size); + NvU8 max_pde_depth = tree->hal->page_table_depth(UVM_PAGE_SIZE_AGNOSTIC) - 1; + + // Passing in NULL for the phys_allocs will mark the child entries as + // invalid. + uvm_mmu_page_table_alloc_t *phys_allocs[2] = {NULL, NULL}; + + // Init with an invalid PTE or clean PDE. Only Maxwell PDEs can have more + // than 512 entries. In this case, we initialize them all with the same + // clean PDE. ATS systems may require clean PDEs with + // ATS_ALLOWED/ATS_NOT_ALLOWED bit settings based on the mapping VA. + // We only clean_bits to 0 at the lowest page table level (PTE table), i.e., + // when depth is greater than the max_pde_depth. + if ((dir->depth > max_pde_depth) || (entries_count > 512 && !g_uvm_global.ats.enabled)) { + NvU64 clear_bits[2]; + + // If it is not a PTE, make a clean PDE. + if (dir->depth != tree->hal->page_table_depth(page_size)) { + // make_pde() child index is zero/ignored, since it is only used in + // PDEs on ATS-enabled systems where pde_fill() is preferred. + tree->hal->make_pde(clear_bits, phys_allocs, dir, 0); + + // Make sure that using only clear_bits[0] will work. + UVM_ASSERT(tree->hal->entry_size(dir->depth) == sizeof(clear_bits[0]) || clear_bits[0] == clear_bits[1]); + } + else { + *clear_bits = 0; + } - if (dir->depth == tree->hal->page_table_depth(page_size)) { - *clear_bits = 0; // Invalid PTE + // Initialize the memory to a reasonable value. + if (push) { + tree->gpu->parent->ce_hal->memset_8(push, + uvm_mmu_gpu_address(tree->gpu, dir->phys_alloc.addr), + *clear_bits, + dir->phys_alloc.size); + } + else { + uvm_mmu_page_table_cpu_memset_8(tree->gpu, + &dir->phys_alloc, + 0, + *clear_bits, + dir->phys_alloc.size / sizeof(*clear_bits)); + } } else { - // passing in NULL for the phys_allocs will mark the child entries as invalid - uvm_mmu_page_table_alloc_t *phys_allocs[2] = {NULL, NULL}; - hal->make_pde(clear_bits, phys_allocs, dir->depth); - - // Make sure that using only clear_bits[0] will work - UVM_ASSERT(hal->entry_size(dir->depth) == sizeof(clear_bits[0]) || clear_bits[0] == clear_bits[1]); + pde_fill(tree, dir, 0, entries_count, phys_allocs, push); } - // initialize the memory to a reasonable value - tree->gpu->parent->ce_hal->memset_8(push, - uvm_gpu_address_from_phys(dir->phys_alloc.addr), - *clear_bits, - dir->phys_alloc.size); } static uvm_page_directory_t *allocate_directory(uvm_page_tree_t *tree, @@ -279,8 +486,10 @@ NvLength phys_alloc_size = hal->allocation_size(depth, page_size); uvm_page_directory_t *dir; - // The page tree doesn't cache PTEs so space is not allocated for entries that are always PTEs. - // 2M PTEs may later become PDEs so pass UVM_PAGE_SIZE_AGNOSTIC, not page_size. + // The page tree doesn't cache PTEs so space is not allocated for entries + // that are always PTEs. + // 2M PTEs may later become PDEs so pass UVM_PAGE_SIZE_AGNOSTIC, not + // page_size. if (depth == hal->page_table_depth(UVM_PAGE_SIZE_AGNOSTIC)) entry_count = 0; else @@ -321,71 +530,6 @@ return hal->entries_per_index(depth) * entry_index + hal->entry_offset(depth, page_size); } -// pde_fill() populates pde_count PDE entries (starting at start_index) with -// the same mapping, i.e., with the same physical address (phys_addr). -static void pde_fill(uvm_page_tree_t *tree, - NvU32 depth, - uvm_mmu_page_table_alloc_t *directory, - NvU32 start_index, - NvU32 pde_count, - uvm_mmu_page_table_alloc_t **phys_addr, - uvm_push_t *push) -{ - NvU64 pde_data[2], entry_size; - uvm_gpu_address_t pde_entry_addr; - - UVM_ASSERT(start_index + pde_count <= uvm_mmu_page_tree_entries(tree, depth, UVM_PAGE_SIZE_AGNOSTIC)); - entry_size = tree->hal->entry_size(depth); - UVM_ASSERT(sizeof(pde_data) >= entry_size); - - tree->hal->make_pde(pde_data, phys_addr, depth); - pde_entry_addr = uvm_gpu_address_from_phys(directory->addr); - pde_entry_addr.address += start_index * entry_size; - - if (entry_size == sizeof(pde_data[0])) { - tree->gpu->parent->ce_hal->memset_8(push, pde_entry_addr, pde_data[0], sizeof(pde_data[0]) * pde_count); - } - else { - NvU32 max_inline_entries = UVM_PUSH_INLINE_DATA_MAX_SIZE / sizeof(pde_data); - uvm_gpu_address_t inline_data_addr; - uvm_push_inline_data_t inline_data; - NvU32 membar_flag = 0; - NvU32 i; - - if (uvm_push_get_and_reset_flag(push, UVM_PUSH_FLAG_NEXT_MEMBAR_NONE)) - membar_flag = UVM_PUSH_FLAG_NEXT_MEMBAR_NONE; - else if (uvm_push_get_and_reset_flag(push, UVM_PUSH_FLAG_NEXT_MEMBAR_GPU)) - membar_flag = UVM_PUSH_FLAG_NEXT_MEMBAR_GPU; - - for (i = 0; i < pde_count;) { - NvU32 j; - NvU32 entry_count = min(pde_count - i, max_inline_entries); - - uvm_push_inline_data_begin(push, &inline_data); - for (j = 0; j < entry_count; j++) - uvm_push_inline_data_add(&inline_data, pde_data, sizeof(pde_data)); - inline_data_addr = uvm_push_inline_data_end(&inline_data); - - // All but the first memcopy can be pipelined. We respect the - // caller's pipelining settings for the first push. - if (i != 0) - uvm_push_set_flag(push, UVM_PUSH_FLAG_CE_NEXT_PIPELINED); - - // No membar is needed until the last copy. Otherwise, use - // caller's membar flag. - if (i + entry_count < pde_count) - uvm_push_set_flag(push, UVM_PUSH_FLAG_NEXT_MEMBAR_NONE); - else if (membar_flag) - uvm_push_set_flag(push, membar_flag); - - tree->gpu->parent->ce_hal->memcopy(push, pde_entry_addr, inline_data_addr, entry_count * sizeof(pde_data)); - - i += entry_count; - pde_entry_addr.address += sizeof(pde_data) * entry_count; - } - } -} - static uvm_page_directory_t *host_pde_write(uvm_page_directory_t *dir, uvm_page_directory_t *parent, NvU32 index_in_parent) @@ -415,7 +559,7 @@ phys_allocs[i] = &entry->phys_alloc; } - pde_fill(tree, dir->depth, &dir->phys_alloc, entry_index, 1, phys_allocs, push); + pde_fill(tree, dir, entry_index, 1, phys_allocs, push); } static void host_pde_clear(uvm_page_tree_t *tree, uvm_page_directory_t *dir, NvU32 entry_index, NvU32 page_size) @@ -426,7 +570,11 @@ dir->ref_count--; } -static void pde_clear(uvm_page_tree_t *tree, uvm_page_directory_t *dir, NvU32 entry_index, NvU32 page_size, void *push) +static void pde_clear(uvm_page_tree_t *tree, + uvm_page_directory_t *dir, + NvU32 entry_index, + NvU32 page_size, + uvm_push_t *push) { host_pde_clear(tree, dir, entry_index, page_size); pde_write(tree, dir, entry_index, false, push); @@ -492,12 +640,62 @@ return NV_OK; } -// initialize new page tables and insert them into the tree -static NV_STATUS write_gpu_state(uvm_page_tree_t *tree, - NvU32 page_size, - NvS32 invalidate_depth, - NvU32 used_count, - uvm_page_directory_t **dirs_used) +static NV_STATUS write_gpu_state_cpu(uvm_page_tree_t *tree, + NvU32 page_size, + NvS32 invalidate_depth, + NvU32 used_count, + uvm_page_directory_t **dirs_used) +{ + NvS32 i; + uvm_push_t push; + NV_STATUS status; + + uvm_assert_mutex_locked(&tree->lock); + UVM_ASSERT(uvm_mmu_use_cpu(tree)); + + if (used_count == 0) + return NV_OK; + + status = uvm_tracker_wait(&tree->tracker); + if (status != NV_OK) + return status; + + for (i = 0; i < used_count; i++) + phys_mem_init(tree, page_size, dirs_used[i], NULL); + + // Only a single membar is needed between the memsets of the page tables + // and the writes of the PDEs pointing to those page tables. + mb(); + + // write entries bottom up, so that they are valid once they're inserted + // into the tree + for (i = used_count - 1; i >= 0; i--) + pde_write(tree, dirs_used[i]->host_parent, dirs_used[i]->index_in_parent, false, NULL); + + // A CPU membar is needed between the PDE writes and the subsequent TLB + // invalidate. Work submission guarantees such a membar. + status = page_tree_begin_acquire(tree, &tree->tracker, &push, "%u dirs", used_count); + if (status != NV_OK) + return status; + + UVM_ASSERT(invalidate_depth >= 0); + + // See the comments in write_gpu_state_gpu() + tree->gpu->parent->host_hal->tlb_invalidate_all(&push, + uvm_page_tree_pdb(tree)->addr, + invalidate_depth, + UVM_MEMBAR_NONE); + page_tree_end(tree, &push); + page_tree_tracker_overwrite_with_push(tree, &push); + + return NV_OK; +} + +static NV_STATUS write_gpu_state_gpu(uvm_page_tree_t *tree, + NvU32 page_size, + NvS32 invalidate_depth, + NvU32 used_count, + uvm_page_directory_t **dirs_used) { NvS32 i; uvm_push_t push; @@ -508,11 +706,12 @@ uvm_membar_t membar_after_writes = UVM_MEMBAR_GPU; uvm_assert_mutex_locked(&tree->lock); + UVM_ASSERT(!uvm_mmu_use_cpu(tree)); if (used_count == 0) return NV_OK; - status = page_tree_begin_acquire(tree, &tree->tracker, &push, "write_gpu_state: %u dirs", used_count); + status = page_tree_begin_acquire(tree, &tree->tracker, &push, "%u dirs", used_count); if (status != NV_OK) return status; @@ -533,15 +732,15 @@ // Only a single membar is needed between the memsets of the page tables // and the writes of the PDEs pointing to those page tables. - // The membar can be local if all of the page tables and PDEs are in GPU memory, - // but must be a sysmembar if any of them are in sysmem. - tree->gpu->parent->host_hal->wait_for_idle(&push); - uvm_hal_membar(tree->gpu, &push, membar_after_writes); + // The membar can be local if all of the page tables and PDEs are in GPU + // memory, but must be a sysmembar if any of them are in sysmem. + uvm_hal_wfi_membar(&push, membar_after_writes); // Reset back to a local membar by default membar_after_writes = UVM_MEMBAR_GPU; - // write entries bottom up, so that they are valid once they're inserted into the tree + // write entries bottom up, so that they are valid once they're inserted + // into the tree for (i = used_count - 1; i >= 0; i--) { uvm_page_directory_t *dir = dirs_used[i]; @@ -553,18 +752,19 @@ // If any of the written PDEs is in sysmem, a sysmembar is needed before // the TLB invalidate. - // Notably sysmembar is needed even though the writer (CE) and reader (MMU) are - // on the same GPU, because CE physical writes take the L2 bypass path. + // Notably sysmembar is needed even though the writer (CE) and reader + // (MMU) are on the same GPU, because CE physical writes take the L2 + // bypass path. if (dir->host_parent->phys_alloc.addr.aperture == UVM_APERTURE_SYS) membar_after_writes = UVM_MEMBAR_SYS; } - tree->gpu->parent->host_hal->wait_for_idle(&push); - uvm_hal_membar(tree->gpu, &push, membar_after_writes); + uvm_hal_wfi_membar(&push, membar_after_writes); UVM_ASSERT(invalidate_depth >= 0); - // Upgrades don't have to flush out accesses, so no membar is needed on the TLB invalidate. + // Upgrades don't have to flush out accesses, so no membar is needed on the + // TLB invalidate. tree->gpu->parent->host_hal->tlb_invalidate_all(&push, uvm_page_tree_pdb(tree)->addr, invalidate_depth, @@ -582,6 +782,19 @@ return NV_OK; } +// initialize new page tables and insert them into the tree +static NV_STATUS write_gpu_state(uvm_page_tree_t *tree, + NvU32 page_size, + NvS32 invalidate_depth, + NvU32 used_count, + uvm_page_directory_t **dirs_used) +{ + if (uvm_mmu_use_cpu(tree)) + return write_gpu_state_cpu(tree, page_size, invalidate_depth, used_count, dirs_used); + else + return write_gpu_state_gpu(tree, page_size, invalidate_depth, used_count, dirs_used); +} + static void free_unused_directories(uvm_page_tree_t *tree, NvU32 used_count, uvm_page_directory_t **dirs_used, @@ -606,7 +819,6 @@ } } } - } static NV_STATUS allocate_page_table(uvm_page_tree_t *tree, NvU32 page_size, uvm_mmu_page_table_alloc_t *out) @@ -617,10 +829,93 @@ return phys_mem_allocate(tree, alloc_size, tree->location, UVM_PMM_ALLOC_FLAGS_EVICT, out); } +static bool page_tree_ats_init_required(uvm_page_tree_t *tree) +{ + // We have full control of the kernel page tables mappings, no ATS address + // aliases is expected. + if (tree->type == UVM_PAGE_TREE_TYPE_KERNEL) + return false; + + // Enable uvm_page_tree_init() from the page_tree test. + if (uvm_enable_builtin_tests && tree->gpu_va_space == NULL) + return false; + + if (!tree->gpu_va_space->ats.enabled) + return false; + + return tree->gpu->parent->no_ats_range_required; +} + +static NV_STATUS page_tree_ats_init(uvm_page_tree_t *tree) +{ + NV_STATUS status; + NvU64 min_va_upper, max_va_lower; + NvU32 page_size; + + if (!page_tree_ats_init_required(tree)) + return NV_OK; + + page_size = uvm_mmu_biggest_page_size(tree); + + uvm_cpu_get_unaddressable_range(&max_va_lower, &min_va_upper); + + // Potential violation of the UVM internal get/put_ptes contract. get_ptes() + // creates and initializes enough PTEs to populate all PDEs covering the + // no_ats_ranges. We store the no_ats_ranges in the tree, so they can be + // put_ptes()'ed on deinit(). It doesn't preclude the range to be used by a + // future get_ptes(), since we don't write to the PTEs (range->table) from + // the tree->no_ats_ranges. + // + // Lower half + status = uvm_page_tree_get_ptes(tree, + page_size, + max_va_lower, + page_size, + UVM_PMM_ALLOC_FLAGS_EVICT, + &tree->no_ats_ranges[0]); + if (status != NV_OK) + return status; + + UVM_ASSERT(tree->no_ats_ranges[0].entry_count == 1); + + if (uvm_platform_uses_canonical_form_address()) { + // Upper half + status = uvm_page_tree_get_ptes(tree, + page_size, + min_va_upper - page_size, + page_size, + UVM_PMM_ALLOC_FLAGS_EVICT, + &tree->no_ats_ranges[1]); + if (status != NV_OK) + return status; + + UVM_ASSERT(tree->no_ats_ranges[1].entry_count == 1); + } + + return NV_OK; +} + +static void page_tree_ats_deinit(uvm_page_tree_t *tree) +{ + size_t i; + + if (page_tree_ats_init_required(tree)) { + for (i = 0; i < ARRAY_SIZE(tree->no_ats_ranges); i++) { + if (tree->no_ats_ranges[i].entry_count) + uvm_page_tree_put_ptes(tree, &tree->no_ats_ranges[i]); + } + + memset(tree->no_ats_ranges, 0, sizeof(tree->no_ats_ranges)); + } +} + static void map_remap_deinit(uvm_page_tree_t *tree) { - if (tree->map_remap.pde0.size) - phys_mem_deallocate(tree, &tree->map_remap.pde0); + if (tree->map_remap.pde0) { + phys_mem_deallocate(tree, &tree->map_remap.pde0->phys_alloc); + uvm_kvfree(tree->map_remap.pde0); + tree->map_remap.pde0 = NULL; + } if (tree->map_remap.ptes_invalid_4k.size) phys_mem_deallocate(tree, &tree->map_remap.ptes_invalid_4k); @@ -633,6 +928,8 @@ uvm_pte_batch_t batch; NvU32 entry_size; + UVM_ASSERT(!uvm_mmu_use_cpu(tree)); + // Allocate the ptes_invalid_4k. status = allocate_page_table(tree, UVM_PAGE_SIZE_4K, &tree->map_remap.ptes_invalid_4k); if (status != NV_OK) @@ -643,10 +940,16 @@ // PDE1-depth(512M) PTE. We first map it to the pde0 directory, then we // return the PTE for the get_ptes()'s caller. if (tree->hal->page_sizes() & UVM_PAGE_SIZE_512M) { - status = allocate_page_table(tree, UVM_PAGE_SIZE_2M, &tree->map_remap.pde0); - if (status != NV_OK) + tree->map_remap.pde0 = allocate_directory(tree, + UVM_PAGE_SIZE_2M, + tree->hal->page_table_depth(UVM_PAGE_SIZE_2M), + UVM_PMM_ALLOC_FLAGS_EVICT); + if (tree->map_remap.pde0 == NULL) { + status = NV_ERR_NO_MEMORY; goto error; + } } + status = page_tree_begin_acquire(tree, &tree->tracker, &push, "map remap init"); if (status != NV_OK) goto error; @@ -668,22 +971,23 @@ uvm_mmu_page_table_alloc_t *phys_allocs[2] = {NULL, NULL}; NvU32 depth = tree->hal->page_table_depth(UVM_PAGE_SIZE_4K) - 1; size_t index_4k = tree->hal->entry_offset(depth, UVM_PAGE_SIZE_4K); - - // pde0 depth equals UVM_PAGE_SIZE_2M. - NvU32 pde0_depth = tree->hal->page_table_depth(UVM_PAGE_SIZE_2M); - NvU32 pde0_entries = tree->map_remap.pde0.size / tree->hal->entry_size(pde0_depth); + NvU32 pde0_entries = tree->map_remap.pde0->phys_alloc.size / tree->hal->entry_size(tree->map_remap.pde0->depth); // The big-page entry is NULL which makes it an invalid entry. phys_allocs[index_4k] = &tree->map_remap.ptes_invalid_4k; // By default CE operations include a MEMBAR_SYS. MEMBAR_GPU is // sufficient when pde0 is allocated in VIDMEM. - if (tree->map_remap.pde0.addr.aperture == UVM_APERTURE_VID) + if (tree->map_remap.pde0->phys_alloc.addr.aperture == UVM_APERTURE_VID) uvm_push_set_flag(&push, UVM_PUSH_FLAG_NEXT_MEMBAR_GPU); + // This is an orphan directory, make_pde() requires a directory to + // compute the VA. The UVM depth map_remap() operates on is not in the + // range make_pde() must operate. We only need to supply the fields used + // by make_pde() to not access invalid memory addresses. + pde_fill(tree, - pde0_depth, - &tree->map_remap.pde0, + tree->map_remap.pde0, 0, pde0_entries, (uvm_mmu_page_table_alloc_t **)&phys_allocs, @@ -710,14 +1014,16 @@ // --------------|-------------------------||----------------|---------------- // vidmem | - || vidmem | false // sysmem | - || sysmem | false -// default | || vidmem | true (1) +// default | || vidmem | true // default | vidmem || vidmem | false // default | sysmem || sysmem | false // -// (1) When SEV mode is enabled, the fallback path is disabled. // // In SR-IOV heavy the the page tree must be in vidmem, to prevent guest drivers // from updating GPU page tables without hypervisor knowledge. +// When the Confidential Computing feature is enabled, all kernel +// allocations must be made in the CPR of vidmem. This is a hardware security +// constraint. // Inputs Outputs // init location | uvm_page_table_location || tree->location | tree->location_sys_fallback // -------------|-------------------------||----------------|---------------- @@ -733,18 +1039,21 @@ (location == UVM_APERTURE_DEFAULT), "Invalid location %s (%d)\n", uvm_aperture_string(location), (int)location); - // The tree must be explicitly initialized in vidmem when in SR-IOV heavy. - // The only exception are "fake" GPUs used during page tree testing, which - // can be identified by having no channel manager. - if ((tree->gpu->channel_manager != NULL) && uvm_gpu_is_virt_mode_sriov_heavy(tree->gpu)) - UVM_ASSERT(location == UVM_APERTURE_VID); + // The page tree of a "fake" GPU used during page tree testing can be in + // sysmem in scenarios where a "real" GPU must be in vidmem. Fake GPUs can + // be identified by having no channel manager. + if (tree->gpu->channel_manager != NULL) { + + if (uvm_gpu_is_virt_mode_sriov_heavy(tree->gpu)) + UVM_ASSERT(location == UVM_APERTURE_VID); + else if (uvm_conf_computing_mode_enabled(tree->gpu)) + UVM_ASSERT(location == UVM_APERTURE_VID); + } if (location == UVM_APERTURE_DEFAULT) { if (page_table_aperture == UVM_APERTURE_DEFAULT) { tree->location = UVM_APERTURE_VID; - - // See the comment (1) above. - tree->location_sys_fallback = !g_uvm_global.sev_enabled; + tree->location_sys_fallback = true; } else { tree->location = page_table_aperture; @@ -795,16 +1104,32 @@ return status; } + if (uvm_mmu_use_cpu(tree)) { + phys_mem_init(tree, UVM_PAGE_SIZE_AGNOSTIC, tree->root, NULL); + return NV_OK; + } + status = page_tree_begin_acquire(tree, &tree->tracker, &push, "init page tree"); if (status != NV_OK) return status; phys_mem_init(tree, UVM_PAGE_SIZE_AGNOSTIC, tree->root, &push); - return page_tree_end_and_wait(tree, &push); + + status = page_tree_end_and_wait(tree, &push); + if (status != NV_OK) + return status; + + status = page_tree_ats_init(tree); + if (status != NV_OK) + return status; + + return NV_OK; } void uvm_page_tree_deinit(uvm_page_tree_t *tree) { + page_tree_ats_deinit(tree); + UVM_ASSERT(tree->root->ref_count == 0); // Take the tree lock only to avoid assertions. It is not required for @@ -855,7 +1180,7 @@ uvm_page_directory_t *free_queue[MAX_OPERATION_DEPTH]; uvm_page_directory_t *dir = range->table; uvm_push_t push; - NV_STATUS status; + NV_STATUS status = NV_OK; NvU32 invalidate_depth = 0; // The logic of what membar is needed when is pretty subtle, please refer to @@ -874,38 +1199,62 @@ // traverse until we hit an in-use page, or the root while (dir->host_parent != NULL && dir->ref_count == 0) { uvm_page_directory_t *parent = dir->host_parent; + uvm_membar_t this_membar; if (free_count == 0) { + if (uvm_mmu_use_cpu(tree)) + status = uvm_tracker_wait(&tree->tracker); - // begin a push which will be submitted before the memory gets freed - status = page_tree_begin_acquire(tree, &tree->tracker, &push, "put ptes: start: %u, count: %u", - range->start_index, range->entry_count); - // Failure to get a push can only happen if we've hit a fatal UVM - // channel error. We can't perform the unmap, so just leave things - // in place for debug. + if (status == NV_OK) { + // Begin a push which will be submitted before the memory gets + // freed. + // + // When writing with the CPU we don't strictly need to begin + // this push until after the writes are done, but doing it here + // doesn't hurt and makes the function's logic simpler. + status = page_tree_begin_acquire(tree, + &tree->tracker, + &push, + "put ptes: start: %u, count: %u", + range->start_index, + range->entry_count); + } + + // Failure to wait for a tracker or get a push can only happen if + // we've hit a fatal UVM channel error. We can't perform the unmap, + // so just leave things in place for debug. if (status != NV_OK) { UVM_ASSERT(status == uvm_global_get_status()); dir->ref_count += range->entry_count; - uvm_mutex_unlock(&tree->lock); - return; + goto done; } } - // All writes can be pipelined as put_ptes() cannot be called with any - // operations pending on the affected PTEs and PDEs. - uvm_push_set_flag(&push, UVM_PUSH_FLAG_CE_NEXT_PIPELINED); - - // Don't issue any membars as part of the clear, a single membar will be - // done below before the invalidate. - uvm_push_set_flag(&push, UVM_PUSH_FLAG_NEXT_MEMBAR_NONE); - pde_clear(tree, dir->host_parent, dir->index_in_parent, range->page_size, &push); + if (uvm_mmu_use_cpu(tree)) { + pde_clear(tree, dir->host_parent, dir->index_in_parent, range->page_size, NULL); + } + else { + // All writes can be pipelined as put_ptes() cannot be called with + // any operations pending on the affected PTEs and PDEs. + uvm_push_set_flag(&push, UVM_PUSH_FLAG_CE_NEXT_PIPELINED); + + // Don't issue any membars as part of the clear, a single membar + // will be done below before the invalidate. + uvm_push_set_flag(&push, UVM_PUSH_FLAG_NEXT_MEMBAR_NONE); + pde_clear(tree, dir->host_parent, dir->index_in_parent, range->page_size, &push); + } invalidate_depth = dir->host_parent->depth; - // If any of the pointed to PDEs were in sysmem then a SYS membar is - // required after the TLB invalidate. - if (dir->phys_alloc.addr.aperture == UVM_APERTURE_SYS) - membar_after_invalidate = UVM_MEMBAR_SYS; + // If we're using the CPU to do the write a SYS membar is required. + // Otherwise, take the membar with the widest scope of any of the + // pointed-to PDEs. + if (uvm_mmu_use_cpu(tree)) + this_membar = UVM_MEMBAR_SYS; + else + this_membar = uvm_hal_downgrade_membar_type(tree->gpu, dir->phys_alloc.addr.aperture == UVM_APERTURE_VID); + + membar_after_invalidate = max(membar_after_invalidate, this_membar); // If any of the cleared PDEs were in sysmem then a SYS membar is // required after the clears and before the TLB invalidate. @@ -920,23 +1269,28 @@ dir = parent; } - if (free_count == 0) { - uvm_mutex_unlock(&tree->lock); - return; - } + if (free_count == 0) + goto done; + + if (uvm_mmu_use_cpu(tree)) + mb(); + else + uvm_hal_wfi_membar(&push, membar_after_pde_clears); - tree->gpu->parent->host_hal->wait_for_idle(&push); - uvm_hal_membar(tree->gpu, &push, membar_after_pde_clears); tree->gpu->parent->host_hal->tlb_invalidate_all(&push, uvm_page_tree_pdb(tree)->addr, invalidate_depth, membar_after_invalidate); - // We just did the appropriate membar above, no need for another one in push_end(). - // At least currently as if the L2 bypass path changes to only require a GPU - // membar between PDE write and TLB invalidate, we'll need to push a - // sysmembar so the end-of-push semaphore is ordered behind the PDE writes. - uvm_push_set_flag(&push, UVM_PUSH_FLAG_NEXT_MEMBAR_NONE); + if (!uvm_mmu_use_cpu(tree)) { + // We just did the appropriate membar above, no need for another one in + // push_end(). If the L2 bypass path changes to only require a GPU + // membar between PDE write and TLB invalidate, we'll need to push a + // sysmembar so the end-of-push semaphore is ordered behind the PDE + // writes. + uvm_push_set_flag(&push, UVM_PUSH_FLAG_NEXT_MEMBAR_NONE); + } + page_tree_end(tree, &push); page_tree_tracker_overwrite_with_push(tree, &push); @@ -946,6 +1300,7 @@ uvm_kvfree(free_queue[i]); } +done: uvm_mutex_unlock(&tree->lock); } @@ -978,7 +1333,8 @@ { uvm_mmu_mode_hal_t *hal = tree->hal; - // bit index just beyond the most significant bit used to index the current entry + // bit index just beyond the most significant bit used to index the current + // entry NvU32 addr_bit_shift = hal->num_va_bits(); // track depth upon which the invalidate occured @@ -997,19 +1353,27 @@ // ensure that the caller has specified a valid page size UVM_ASSERT((page_size & hal->page_sizes()) != 0); - // This algorithm will work with unaligned ranges, but the caller's intent is unclear - UVM_ASSERT_MSG(start % page_size == 0 && size % page_size == 0, "start 0x%llx size 0x%zx page_size 0x%x", - start, (size_t)size, page_size); + // This algorithm will work with unaligned ranges, but the caller's intent + // is unclear + UVM_ASSERT_MSG(start % page_size == 0 && size % page_size == 0, + "start 0x%llx size 0x%zx page_size 0x%x\n", + start, + (size_t)size, + page_size); // The GPU should be capable of addressing the passed range - UVM_ASSERT(uvm_gpu_can_address(tree->gpu, start, size)); + if (tree->type == UVM_PAGE_TREE_TYPE_USER) + UVM_ASSERT(uvm_gpu_can_address(tree->gpu, start, size)); + else + UVM_ASSERT(uvm_gpu_can_address_kernel(tree->gpu, start, size)); while (true) { - - // index of the entry, for the first byte of the range, within its containing directory + // index of the entry, for the first byte of the range, within its + // containing directory NvU32 start_index; - // index of the entry, for the last byte of the range, within its containing directory + // index of the entry, for the last byte of the range, within its + // containing directory NvU32 end_index; // pointer to PDE/PTE @@ -1035,7 +1399,8 @@ if (dir_cache[dir->depth] == NULL) { *cur_depth = dir->depth; - // Undo the changes to the tree so that the dir cache remains private to the thread + // Undo the changes to the tree so that the dir cache + // remains private to the thread. for (i = 0; i < used_count; i++) host_pde_clear(tree, dirs_used[i]->host_parent, dirs_used[i]->index_in_parent, page_size); @@ -1086,10 +1451,9 @@ if (uvm_page_table_range_aperture(range) == UVM_APERTURE_VID) uvm_push_set_flag(&push, UVM_PUSH_FLAG_NEXT_MEMBAR_GPU); - phys_alloc[0] = &tree->map_remap.pde0; + phys_alloc[0] = &tree->map_remap.pde0->phys_alloc; pde_fill(tree, - range->table->depth, - &range->table->phys_alloc, + range->table, range->start_index, range->entry_count, (uvm_mmu_page_table_alloc_t **)&phys_alloc, @@ -1134,7 +1498,8 @@ dir_cache)) == NV_ERR_MORE_PROCESSING_REQUIRED) { uvm_mutex_unlock(&tree->lock); - // try_get_ptes never needs depth 0, so store a directory at its parent's depth + // try_get_ptes never needs depth 0, so store a directory at its + // parent's depth. // TODO: Bug 1766655: Allocate everything below cur_depth instead of // retrying for every level. dir_cache[cur_depth] = allocate_directory(tree, page_size, cur_depth + 1, pmm_flags); @@ -1242,19 +1607,22 @@ UVM_ASSERT(pte_dir->depth == tree->hal->page_table_depth(page_size)); + // The flat mappings should always be set up when executing this path + UVM_ASSERT(!uvm_mmu_use_cpu(tree)); + status = page_tree_begin_acquire(tree, &tree->tracker, &push, "Poisoning child table of page size %u", page_size); if (status != NV_OK) return status; tree->gpu->parent->ce_hal->memset_8(&push, - uvm_gpu_address_from_phys(pte_dir->phys_alloc.addr), + uvm_mmu_gpu_address(tree->gpu, pte_dir->phys_alloc.addr), tree->hal->poisoned_pte(), pte_dir->phys_alloc.size); // If both the new PTEs and the parent PDE are in vidmem, then a GPU- // local membar is enough to keep the memset of the PTEs ordered with // any later write of the PDE. Otherwise we need a sysmembar. See the - // comments in write_gpu_state. + // comments in write_gpu_state_gpu. if (pte_dir->phys_alloc.addr.aperture == UVM_APERTURE_VID && parent->phys_alloc.addr.aperture == UVM_APERTURE_VID) uvm_push_set_flag(&push, UVM_PUSH_FLAG_NEXT_MEMBAR_GPU); @@ -1414,8 +1782,12 @@ range); if (status != NV_OK) { UVM_ERR_PRINT("Failed to get PTEs for subrange %zd [0x%llx, 0x%llx) size 0x%llx, part of [0x%llx, 0x%llx)\n", - i, range_start, range_start + range_size, range_size, - start, size); + i, + range_start, + range_start + range_size, + range_size, + start, + size); goto out; } } @@ -1514,7 +1886,43 @@ return NV_OK; } -NV_STATUS uvm_page_table_range_vec_clear_ptes(uvm_page_table_range_vec_t *range_vec, uvm_membar_t tlb_membar) +static NV_STATUS uvm_page_table_range_vec_clear_ptes_cpu(uvm_page_table_range_vec_t *range_vec, uvm_membar_t tlb_membar) +{ + uvm_page_tree_t *tree = range_vec->tree; + NvU32 entry_size = uvm_mmu_pte_size(tree, range_vec->page_size); + NvU64 invalid_ptes[2] = {0, 0}; + uvm_push_t push; + NV_STATUS status; + size_t i; + + UVM_ASSERT(uvm_mmu_use_cpu(tree)); + + for (i = 0; i < range_vec->range_count; ++i) { + uvm_page_table_range_t *range = &range_vec->ranges[i]; + uvm_mmu_page_table_alloc_t *dir = &range->table->phys_alloc; + + if (entry_size == 8) + uvm_mmu_page_table_cpu_memset_8(tree->gpu, dir, range->start_index, invalid_ptes[0], range->entry_count); + else + uvm_mmu_page_table_cpu_memset_16(tree->gpu, dir, range->start_index, invalid_ptes, range->entry_count); + } + + // A CPU membar is needed between the PTE writes and the subsequent TLB + // invalidate. Work submission guarantees such a membar. + status = page_tree_begin_acquire(tree, + NULL, + &push, + "Invalidating [0x%llx, 0x%llx)", + range_vec->start, + range_vec->start + range_vec->size); + if (status != NV_OK) + return status; + + uvm_tlb_batch_single_invalidate(tree, &push, range_vec->start, range_vec->size, range_vec->page_size, tlb_membar); + return page_tree_end_and_wait(tree, &push); +} + +static NV_STATUS uvm_page_table_range_vec_clear_ptes_gpu(uvm_page_table_range_vec_t *range_vec, uvm_membar_t tlb_membar) { NV_STATUS status = NV_OK; NV_STATUS tracker_status; @@ -1532,6 +1940,7 @@ UVM_ASSERT(range_vec); UVM_ASSERT(tree); UVM_ASSERT(gpu); + UVM_ASSERT(!uvm_mmu_use_cpu(tree)); i = 0; while (i < range_vec->range_count) { @@ -1582,6 +1991,14 @@ return status; } +NV_STATUS uvm_page_table_range_vec_clear_ptes(uvm_page_table_range_vec_t *range_vec, uvm_membar_t tlb_membar) +{ + if (uvm_mmu_use_cpu(range_vec->tree)) + return uvm_page_table_range_vec_clear_ptes_cpu(range_vec, tlb_membar); + else + return uvm_page_table_range_vec_clear_ptes_gpu(range_vec, tlb_membar); +} + void uvm_page_table_range_vec_deinit(uvm_page_table_range_vec_t *range_vec) { size_t i; @@ -1613,10 +2030,58 @@ uvm_kvfree(range_vec); } -NV_STATUS uvm_page_table_range_vec_write_ptes(uvm_page_table_range_vec_t *range_vec, - uvm_membar_t tlb_membar, - uvm_page_table_range_pte_maker_t pte_maker, - void *caller_data) +static NV_STATUS uvm_page_table_range_vec_write_ptes_cpu(uvm_page_table_range_vec_t *range_vec, + uvm_membar_t tlb_membar, + uvm_page_table_range_pte_maker_t pte_maker, + void *caller_data) +{ + NV_STATUS status; + size_t i; + uvm_page_tree_t *tree = range_vec->tree; + NvU32 entry_size = uvm_mmu_pte_size(tree, range_vec->page_size); + uvm_push_t push; + NvU64 offset = 0; + + UVM_ASSERT(uvm_mmu_use_cpu(tree)); + + // Enforce ordering with prior accesses to the pages being mapped before the + // mappings are activated. + mb(); + + for (i = 0; i < range_vec->range_count; ++i) { + uvm_page_table_range_t *range = &range_vec->ranges[i]; + uvm_mmu_page_table_alloc_t *dir = &range->table->phys_alloc; + NvU32 entry; + + for (entry = range->start_index; entry < range->entry_count; ++entry) { + NvU64 pte_bits[2] = {pte_maker(range_vec, offset, caller_data), 0}; + + if (entry_size == 8) + uvm_mmu_page_table_cpu_memset_8(tree->gpu, dir, entry, pte_bits[0], 1); + else + uvm_mmu_page_table_cpu_memset_16(tree->gpu, dir, entry, pte_bits, 1); + + offset += range_vec->page_size; + } + } + + status = page_tree_begin_acquire(tree, + NULL, + &push, + "Invalidating [0x%llx, 0x%llx)", + range_vec->start, + range_vec->start + range_vec->size); + if (status != NV_OK) + return status; + + uvm_tlb_batch_single_invalidate(tree, &push, range_vec->start, range_vec->size, range_vec->page_size, tlb_membar); + return page_tree_end_and_wait(tree, &push); +} + +static NV_STATUS uvm_page_table_range_vec_write_ptes_gpu(uvm_page_table_range_vec_t *range_vec, + uvm_membar_t tlb_membar, + uvm_page_table_range_pte_maker_t pte_maker, + void *caller_data) { NV_STATUS status = NV_OK; NV_STATUS tracker_status; @@ -1637,6 +2102,8 @@ NvU32 max_entries_per_push = max_total_entry_size_per_push / entry_size; + UVM_ASSERT(!uvm_mmu_use_cpu(tree)); + for (i = 0; i < range_vec->range_count; ++i) { uvm_page_table_range_t *range = &range_vec->ranges[i]; NvU64 range_start = range_vec_calc_range_start(range_vec, i); @@ -1715,6 +2182,17 @@ return status; } +NV_STATUS uvm_page_table_range_vec_write_ptes(uvm_page_table_range_vec_t *range_vec, + uvm_membar_t tlb_membar, + uvm_page_table_range_pte_maker_t pte_maker, + void *caller_data) +{ + if (uvm_mmu_use_cpu(range_vec->tree)) + return uvm_page_table_range_vec_write_ptes_cpu(range_vec, tlb_membar, pte_maker, caller_data); + else + return uvm_page_table_range_vec_write_ptes_gpu(range_vec, tlb_membar, pte_maker, caller_data); +} + typedef struct identity_mapping_pte_maker_data_struct { NvU64 phys_offset; @@ -1732,13 +2210,12 @@ } static NV_STATUS create_identity_mapping(uvm_gpu_t *gpu, - NvU64 base, + uvm_gpu_identity_mapping_t *mapping, NvU64 size, uvm_aperture_t aperture, NvU64 phys_offset, NvU32 page_size, - uvm_pmm_alloc_flags_t pmm_flags, - uvm_page_table_range_vec_t **range_vec) + uvm_pmm_alloc_flags_t pmm_flags) { NV_STATUS status; identity_mapping_pte_maker_data_t data = @@ -1748,32 +2225,36 @@ }; status = uvm_page_table_range_vec_create(&gpu->address_space_tree, - base, + mapping->base, size, page_size, pmm_flags, - range_vec); + &mapping->range_vec); if (status != NV_OK) { UVM_ERR_PRINT("Failed to init range vec for aperture %d identity mapping at [0x%llx, 0x%llx): %s, GPU %s\n", aperture, - base, - base + size, + mapping->base, + mapping->base + size, nvstatusToString(status), uvm_gpu_name(gpu)); return status; } - status = uvm_page_table_range_vec_write_ptes(*range_vec, UVM_MEMBAR_NONE, identity_mapping_pte_maker, &data); + status = uvm_page_table_range_vec_write_ptes(mapping->range_vec, + UVM_MEMBAR_NONE, + identity_mapping_pte_maker, + &data); if (status != NV_OK) { UVM_ERR_PRINT("Failed to write PTEs for aperture %d identity mapping at [0x%llx, 0x%llx): %s, GPU %s\n", aperture, - base, - base + size, + mapping->base, + mapping->base + size, nvstatusToString(status), uvm_gpu_name(gpu)); return status; } + mapping->ready = true; return NV_OK; } @@ -1782,6 +2263,10 @@ if (mapping->range_vec == NULL) return; + // Tell the teardown routines they can't use this mapping as part of their + // teardown. + mapping->ready = false; + (void)uvm_page_table_range_vec_clear_ptes(mapping->range_vec, UVM_MEMBAR_SYS); uvm_page_table_range_vec_destroy(mapping->range_vec); mapping->range_vec = NULL; @@ -1789,7 +2274,7 @@ bool uvm_mmu_gpu_needs_static_vidmem_mapping(uvm_gpu_t *gpu) { - return false; + return !gpu->parent->ce_phys_vidmem_write_supported; } bool uvm_mmu_gpu_needs_dynamic_vidmem_mapping(uvm_gpu_t *gpu) @@ -1825,13 +2310,12 @@ flat_mapping->base = gpu->parent->flat_vidmem_va_base; return create_identity_mapping(gpu, - flat_mapping->base, + flat_mapping, size, aperture, phys_offset, page_size, - UVM_PMM_ALLOC_FLAGS_EVICT, - &flat_mapping->range_vec); + UVM_PMM_ALLOC_FLAGS_EVICT); } static void destroy_static_vidmem_mapping(uvm_gpu_t *gpu) @@ -1871,13 +2355,12 @@ UVM_ASSERT(peer_mapping->base); return create_identity_mapping(gpu, - peer_mapping->base, + peer_mapping, size, aperture, phys_offset, page_size, - UVM_PMM_ALLOC_FLAGS_EVICT, - &peer_mapping->range_vec); + UVM_PMM_ALLOC_FLAGS_EVICT); } void uvm_mmu_destroy_peer_identity_mappings(uvm_gpu_t *gpu, uvm_gpu_t *peer) @@ -2280,9 +2763,9 @@ UVM_ASSERT(gpu->parent->flat_sysmem_va_base != 0); // The DMA addressable window is the maximum system physical memory - // addressable by the GPU (this limit is 128TB in Pascal-Ampere). The - // virtual mapping to sysmem is linear, so its size matches that of the - // physical address space. + // addressable by the GPU (this limit is 128TB in Pascal-Ada). The virtual + // mapping to sysmem is linear, so its size matches that of the physical + // address space. flat_sysmem_va_size = gpu->parent->dma_addressable_limit + 1 - gpu->parent->dma_addressable_start; // The optimal mapping granularity is dependent on multiple factors: @@ -2291,14 +2774,14 @@ // SR-IOV each mapping addition adds a lot of overhead due to vGPU plugin // involvement), metadata memory footprint (inversely proportional to the // mapping size), etc. - mapping_size = 4ULL * 1024 * 1024 * 1024; + mapping_size = 4 * UVM_SIZE_1GB; // The mapping size should be at least 1GB, due to bitlock limitations. This // shouldn't be a problem because the expectation is to use 512MB PTEs, and // using a granularity of 1GB already results in allocating a large array of // sysmem mappings with 128K entries. UVM_ASSERT(is_power_of_2(mapping_size)); - UVM_ASSERT(mapping_size >= 1ULL * 1024 * 1024 * 1024); + UVM_ASSERT(mapping_size >= UVM_SIZE_1GB); UVM_ASSERT(mapping_size >= uvm_mmu_biggest_page_size(&gpu->address_space_tree)); UVM_ASSERT(mapping_size <= flat_sysmem_va_size); @@ -2351,16 +2834,15 @@ // because in the common case the VA block lock is held. pmm_flags = UVM_PMM_ALLOC_FLAGS_NONE; - sysmem_mapping->base = uvm_parent_gpu_canonical_address(gpu->parent, virtual_address.address); + sysmem_mapping->base = virtual_address.address; status = create_identity_mapping(gpu, - sysmem_mapping->base, + sysmem_mapping, gpu->sysmem_mappings.mapping_size, UVM_APERTURE_SYS, phys_offset, page_size, - pmm_flags, - &sysmem_mapping->range_vec); + pmm_flags); } sysmem_mapping_unlock(gpu, sysmem_mapping); @@ -2381,14 +2863,14 @@ { NV_STATUS status; - status = create_dynamic_sysmem_mapping(gpu); - if (status != NV_OK) - return status; - status = create_static_vidmem_mapping(gpu); if (status != NV_OK) goto error; + status = create_dynamic_sysmem_mapping(gpu); + if (status != NV_OK) + return status; + status = create_dynamic_vidmem_mapping(gpu); if (status != NV_OK) goto error; @@ -2403,8 +2885,16 @@ void uvm_mmu_destroy_flat_mappings(uvm_gpu_t *gpu) { destroy_dynamic_vidmem_mapping(gpu); - destroy_static_vidmem_mapping(gpu); destroy_dynamic_sysmem_mapping(gpu); + destroy_static_vidmem_mapping(gpu); +} + +uvm_gpu_address_t uvm_mmu_gpu_address(uvm_gpu_t *gpu, uvm_gpu_phys_address_t phys_addr) +{ + if (phys_addr.aperture == UVM_APERTURE_VID && !gpu->parent->ce_phys_vidmem_write_supported) + return uvm_gpu_address_virtual_from_vidmem_phys(gpu, phys_addr.address); + + return uvm_gpu_address_from_phys(phys_addr); } NV_STATUS uvm_test_invalidate_tlb(UVM_TEST_INVALIDATE_TLB_PARAMS *params, struct file *filp) diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/kernel-open/nvidia-uvm/uvm_mmu.h nvidia-open-gpu-kernel-modules-535.161.08/kernel-open/nvidia-uvm/uvm_mmu.h --- nvidia-open-gpu-kernel-modules-525.147.05/kernel-open/nvidia-uvm/uvm_mmu.h 2023-10-25 20:33:36.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/kernel-open/nvidia-uvm/uvm_mmu.h 2024-03-05 22:25:54.000000000 +0000 @@ -1,5 +1,5 @@ /******************************************************************************* - Copyright (c) 2015-2022 NVIDIA Corporation + Copyright (c) 2015-2023 NVIDIA Corporation Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation files (the "Software"), to @@ -36,7 +36,9 @@ #define UVM_PAGE_SIZE_AGNOSTIC 0 // Memory layout of UVM's kernel VA space. -// The following memory regions are not to scale. +// The following memory regions are not to scale. The memory layout is linear, +// i.e., no canonical form address conversion. +// // Hopper: // +----------------+ 128PB // | | @@ -48,7 +50,11 @@ // | | // | (not used) | // | | -// ------------------ 64PB + 8TB +// ------------------ 64PB + 8TB + 256GB (UVM_GPU_MAX_PHYS_MEM) +// | vidmem | +// | flat mapping | ==> UVM_GPU_MAX_PHYS_MEM +// | (256GB) | +// ------------------ 64PB + 8TB (flat_vidmem_va_base) // |peer ident. maps| // |32 * 256GB = 8TB| ==> NV_MAX_DEVICES * UVM_PEER_IDENTITY_VA_SIZE // ------------------ 64PB @@ -57,7 +63,7 @@ // | | // +----------------+ 0 (rm_va_base) // -// Pascal-Ampere: +// Pascal-Ada: // +----------------+ 512TB // | | // | (not used) | @@ -103,7 +109,7 @@ // +----------------+ 0 (rm_va_base) // Maximum memory of any GPU. -#define UVM_GPU_MAX_PHYS_MEM (256ull * 1024 * 1024 * 1024) +#define UVM_GPU_MAX_PHYS_MEM (256 * UVM_SIZE_1GB) // The size of VA that should be reserved per peer identity mapping. // This should be at least the maximum amount of memory of any GPU. @@ -209,11 +215,14 @@ // memory out-of-range error so we can immediately identify bad PTE usage. NvU64 (*poisoned_pte)(void); - // write a PDE bit-pattern to entry based on the data in entries (which may + // Write a PDE bit-pattern to entry based on the data in allocs (which may // point to two items for dual PDEs). - // any of allocs are allowed to be NULL, in which case they are to be - // treated as empty. - void (*make_pde)(void *entry, uvm_mmu_page_table_alloc_t **allocs, NvU32 depth); + // Any of allocs are allowed to be NULL, in which case they are to be + // treated as empty. make_pde() uses dir and child_index to compute the + // mapping PDE VA. On ATS-enabled systems, we may set PDE's PCF as + // ATS_ALLOWED or ATS_NOT_ALLOWED based on the mapping PDE VA, even for + // invalid/clean PDE entries. + void (*make_pde)(void *entry, uvm_mmu_page_table_alloc_t **allocs, uvm_page_directory_t *dir, NvU32 child_index); // size of an entry in a directory/table. Generally either 8 or 16 bytes. // (in the case of Pascal dual PDEs) @@ -223,7 +232,7 @@ NvU32 (*entries_per_index)(NvU32 depth); // For dual PDEs, this is ether 1 or 0, depending on the page size. - // This is used to index the host copy only. GPU PDEs are always entirely + // This is used to index the host copy only. GPU PDEs are always entirely // re-written using make_pde. NvLength (*entry_offset)(NvU32 depth, NvU32 page_size); @@ -289,11 +298,16 @@ // PDE0 where all big-page entries are invalid, and small-page entries // point to ptes_invalid_4k. - // pde0 is only used on Pascal-Ampere, i.e., they have the same PDE - // format. - uvm_mmu_page_table_alloc_t pde0; + // pde0 is used on Pascal+ GPUs, i.e., they have the same PDE format. + uvm_page_directory_t *pde0; } map_remap; + // On ATS-enabled systems where the CPU VA width is smaller than the GPU VA + // width, the excess address range is set with ATS_NOT_ALLOWED on all leaf + // PDEs covering that range. We have at most 2 no_ats_ranges, due to + // canonical form address systems. + uvm_page_table_range_t no_ats_ranges[2]; + // Tracker for all GPU operations on the tree uvm_tracker_t tracker; }; @@ -359,21 +373,32 @@ // the same page size without an intervening put_ptes. To duplicate a subset of // an existing range or change the size of an existing range, use // uvm_page_table_range_get_upper() and/or uvm_page_table_range_shrink(). -NV_STATUS uvm_page_tree_get_ptes(uvm_page_tree_t *tree, NvU32 page_size, NvU64 start, NvLength size, - uvm_pmm_alloc_flags_t pmm_flags, uvm_page_table_range_t *range); +NV_STATUS uvm_page_tree_get_ptes(uvm_page_tree_t *tree, + NvU32 page_size, + NvU64 start, + NvLength size, + uvm_pmm_alloc_flags_t pmm_flags, + uvm_page_table_range_t *range); // Same as uvm_page_tree_get_ptes(), but doesn't synchronize the GPU work. // // All pending operations can be waited on with uvm_page_tree_wait(). -NV_STATUS uvm_page_tree_get_ptes_async(uvm_page_tree_t *tree, NvU32 page_size, NvU64 start, NvLength size, - uvm_pmm_alloc_flags_t pmm_flags, uvm_page_table_range_t *range); +NV_STATUS uvm_page_tree_get_ptes_async(uvm_page_tree_t *tree, + NvU32 page_size, + NvU64 start, + NvLength size, + uvm_pmm_alloc_flags_t pmm_flags, + uvm_page_table_range_t *range); // Returns a single-entry page table range for the addresses passed. // The size parameter must be a page size supported by this tree. // This is equivalent to calling uvm_page_tree_get_ptes() with size equal to // page_size. -NV_STATUS uvm_page_tree_get_entry(uvm_page_tree_t *tree, NvU32 page_size, NvU64 start, - uvm_pmm_alloc_flags_t pmm_flags, uvm_page_table_range_t *single); +NV_STATUS uvm_page_tree_get_entry(uvm_page_tree_t *tree, + NvU32 page_size, + NvU64 start, + uvm_pmm_alloc_flags_t pmm_flags, + uvm_page_table_range_t *single); // For a single-entry page table range, write the PDE (which could be a dual // PDE) to the GPU. @@ -472,8 +497,8 @@ // new_range_vec will contain the upper portion of range_vec, starting at // new_end + 1. // -// new_end + 1 is required to be within the address range of range_vec and be aligned to -// range_vec's page_size. +// new_end + 1 is required to be within the address range of range_vec and be +// aligned to range_vec's page_size. // // On failure, the original range vector is left unmodified. NV_STATUS uvm_page_table_range_vec_split_upper(uvm_page_table_range_vec_t *range_vec, @@ -495,18 +520,22 @@ // for each offset. // The caller_data pointer is what the caller passed in as caller_data to // uvm_page_table_range_vec_write_ptes(). -typedef NvU64 (*uvm_page_table_range_pte_maker_t)(uvm_page_table_range_vec_t *range_vec, NvU64 offset, - void *caller_data); +typedef NvU64 (*uvm_page_table_range_pte_maker_t)(uvm_page_table_range_vec_t *range_vec, + NvU64 offset, + void *caller_data); -// Write all PTEs covered by the range vector using the given PTE making function. +// Write all PTEs covered by the range vector using the given PTE making +// function. // // After writing all the PTEs a TLB invalidate operation is performed including // the passed in tlb_membar. // // See comments about uvm_page_table_range_pte_maker_t for details about the // PTE making callback. -NV_STATUS uvm_page_table_range_vec_write_ptes(uvm_page_table_range_vec_t *range_vec, uvm_membar_t tlb_membar, - uvm_page_table_range_pte_maker_t pte_maker, void *caller_data); +NV_STATUS uvm_page_table_range_vec_write_ptes(uvm_page_table_range_vec_t *range_vec, + uvm_membar_t tlb_membar, + uvm_page_table_range_pte_maker_t pte_maker, + void *caller_data); // Set all PTEs covered by the range vector to an empty PTE // @@ -592,13 +621,18 @@ static NvU32 uvm_mmu_biggest_page_size_up_to(uvm_page_tree_t *tree, NvU32 max_page_size) { + NvU32 gpu_page_sizes = tree->hal->page_sizes(); + NvU32 smallest_gpu_page_size = gpu_page_sizes & ~(gpu_page_sizes - 1); NvU32 page_sizes; NvU32 page_size; UVM_ASSERT_MSG(is_power_of_2(max_page_size), "0x%x\n", max_page_size); + if (max_page_size < smallest_gpu_page_size) + return 0; + // Calculate the supported page sizes that are not larger than the max - page_sizes = tree->hal->page_sizes() & (max_page_size | (max_page_size - 1)); + page_sizes = gpu_page_sizes & (max_page_size | (max_page_size - 1)); // And pick the biggest one of them page_size = 1 << __fls(page_sizes); @@ -625,8 +659,9 @@ // Get the physical address of the entry at entry_index within the range // (counted from range->start_index). -static uvm_gpu_phys_address_t uvm_page_table_range_entry_address(uvm_page_tree_t *tree, uvm_page_table_range_t *range, - size_t entry_index) +static uvm_gpu_phys_address_t uvm_page_table_range_entry_address(uvm_page_tree_t *tree, + uvm_page_table_range_t *range, + size_t entry_index) { NvU32 entry_size = uvm_mmu_pte_size(tree, range->page_size); uvm_gpu_phys_address_t entry = range->table->phys_alloc.addr; @@ -642,6 +677,14 @@ return range->table->phys_alloc.addr.aperture; } +// Given a GPU or CPU physical address that refers to pages tables, retrieve an +// address suitable for CE writes to those page tables. This should be used +// instead of uvm_gpu_address_copy because PTE writes are used to bootstrap the +// various flat virtual mappings, so we usually ensure that PTE writes work even +// if virtual mappings are required for other accesses. This is only needed when +// CE has system-wide physical addressing restrictions. +uvm_gpu_address_t uvm_mmu_gpu_address(uvm_gpu_t *gpu, uvm_gpu_phys_address_t phys_addr); + NV_STATUS uvm_test_invalidate_tlb(UVM_TEST_INVALIDATE_TLB_PARAMS *params, struct file *filp); #endif diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/kernel-open/nvidia-uvm/uvm_page_tree_test.c nvidia-open-gpu-kernel-modules-535.161.08/kernel-open/nvidia-uvm/uvm_page_tree_test.c --- nvidia-open-gpu-kernel-modules-525.147.05/kernel-open/nvidia-uvm/uvm_page_tree_test.c 2023-10-25 20:33:43.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/kernel-open/nvidia-uvm/uvm_page_tree_test.c 2024-03-05 22:26:06.000000000 +0000 @@ -1,5 +1,5 @@ /******************************************************************************* - Copyright (c) 2015-2021 NVIDIA Corporation + Copyright (c) 2015-2023 NVIDIA Corporation Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation files (the "Software"), to @@ -146,9 +146,15 @@ g_fake_tlb_invals_tracking_enabled = false; } -// Fake TLB invalidate VA that just saves off the parameters so that they can be verified later -static void fake_tlb_invalidate_va(uvm_push_t *push, uvm_gpu_phys_address_t pdb, - NvU32 depth, NvU64 base, NvU64 size, NvU32 page_size, uvm_membar_t membar) +// Fake TLB invalidate VA that just saves off the parameters so that they can be +// verified later. +static void fake_tlb_invalidate_va(uvm_push_t *push, + uvm_gpu_phys_address_t pdb, + NvU32 depth, + NvU64 base, + NvU64 size, + NvU32 page_size, + uvm_membar_t membar) { if (!g_fake_tlb_invals_tracking_enabled) return; @@ -210,8 +216,8 @@ } if ((g_last_fake_inval->membar == UVM_MEMBAR_NONE) == expected_membar) { UVM_TEST_PRINT("Expected %s membar, got %s instead\n", - expected_membar ? "a" : "no", - uvm_membar_string(g_last_fake_inval->membar)); + expected_membar ? "a" : "no", + uvm_membar_string(g_last_fake_inval->membar)); result = false; } @@ -230,7 +236,8 @@ } if (g_last_fake_inval->base != 0 || g_last_fake_inval->size != -1) { UVM_TEST_PRINT("Expected invalidate all but got range [0x%llx, 0x%llx) instead\n", - g_last_fake_inval->base, g_last_fake_inval->base + g_last_fake_inval->size); + g_last_fake_inval->base, + g_last_fake_inval->base + g_last_fake_inval->size); return false; } if (g_last_fake_inval->depth != expected_depth) { @@ -247,15 +254,16 @@ UVM_ASSERT(g_fake_tlb_invals_tracking_enabled); if (g_fake_invals_count == 0) { - UVM_TEST_PRINT("Expected an invalidate for range [0x%llx, 0x%llx), but got none\n", - base, base + size); + UVM_TEST_PRINT("Expected an invalidate for range [0x%llx, 0x%llx), but got none\n", base, base + size); return false; } if ((inval->base != base || inval->size != size) && inval->base != 0 && inval->size != -1) { UVM_TEST_PRINT("Expected invalidate range [0x%llx, 0x%llx), but got range [0x%llx, 0x%llx) instead\n", - base, base + size, - inval->base, inval->base + inval->size); + base, + base + size, + inval->base, + inval->base + inval->size); return false; } if (inval->depth != expected_depth) { @@ -270,7 +278,13 @@ return true; } -static bool assert_invalidate_range(NvU64 base, NvU64 size, NvU32 page_size, bool allow_inval_all, NvU32 range_depth, NvU32 all_depth, bool expected_membar) +static bool assert_invalidate_range(NvU64 base, + NvU64 size, + NvU32 page_size, + bool allow_inval_all, + NvU32 range_depth, + NvU32 all_depth, + bool expected_membar) { NvU32 i; @@ -305,18 +319,25 @@ return uvm_page_tree_init(gpu, NULL, UVM_PAGE_TREE_TYPE_USER, big_page_size, UVM_APERTURE_SYS, tree); } +static NV_STATUS test_page_tree_init_kernel(uvm_gpu_t *gpu, NvU32 big_page_size, uvm_page_tree_t *tree) +{ + return uvm_page_tree_init(gpu, NULL, UVM_PAGE_TREE_TYPE_KERNEL, big_page_size, UVM_APERTURE_SYS, tree); +} + static NV_STATUS test_page_tree_get_ptes(uvm_page_tree_t *tree, NvU32 page_size, NvU64 start, NvLength size, uvm_page_table_range_t *range) { - return uvm_page_tree_get_ptes(tree, - page_size, - uvm_parent_gpu_canonical_address(tree->gpu->parent, start), - size, - UVM_PMM_ALLOC_FLAGS_NONE, - range); + uvm_mmu_mode_hal_t *hal = tree->gpu->parent->arch_hal->mmu_mode_hal(UVM_PAGE_SIZE_64K); + + // Maxwell GPUs don't use canonical form address even on platforms that + // support it. + start = (tree->type == UVM_PAGE_TREE_TYPE_USER) && (hal->num_va_bits() > 40) ? + uvm_parent_gpu_canonical_address(tree->gpu->parent, start) : + start; + return uvm_page_tree_get_ptes(tree, page_size, start, size, UVM_PMM_ALLOC_FLAGS_NONE, range); } static NV_STATUS test_page_tree_get_entry(uvm_page_tree_t *tree, @@ -324,11 +345,13 @@ NvU64 start, uvm_page_table_range_t *single) { - return uvm_page_tree_get_entry(tree, - page_size, - uvm_parent_gpu_canonical_address(tree->gpu->parent, start), - UVM_PMM_ALLOC_FLAGS_NONE, - single); + uvm_mmu_mode_hal_t *hal = tree->gpu->parent->arch_hal->mmu_mode_hal(UVM_PAGE_SIZE_64K); + + // See comment above (test_page_tree_get_ptes) + start = (tree->type == UVM_PAGE_TREE_TYPE_USER) && (hal->num_va_bits() > 40) ? + uvm_parent_gpu_canonical_address(tree->gpu->parent, start) : + start; + return uvm_page_tree_get_entry(tree, page_size, start, UVM_PMM_ALLOC_FLAGS_NONE, single); } static NV_STATUS test_page_tree_alloc_table(uvm_page_tree_t *tree, @@ -411,7 +434,10 @@ uvm_page_table_range_t range; NvLength size = 64 * 1024; - MEM_NV_CHECK_RET(test_page_tree_init(gpu, BIG_PAGE_SIZE_PASCAL, &tree), NV_OK); + + // We use a kernel-type page tree to decouple the test from the CPU VA width + // and canonical form address limits. + MEM_NV_CHECK_RET(test_page_tree_init_kernel(gpu, BIG_PAGE_SIZE_PASCAL, &tree), NV_OK); MEM_NV_CHECK_RET(test_page_tree_get_ptes(&tree, UVM_PAGE_SIZE_64K, 0x100000000000000ULL, size, &range), NV_OK); TEST_CHECK_RET(range.entry_count == 1); TEST_CHECK_RET(range.table->depth == 5); @@ -476,7 +502,6 @@ return NV_OK; } - static NV_STATUS alloc_nearby_pde_64k_memory(uvm_gpu_t *gpu) { uvm_page_tree_t tree; @@ -529,10 +554,10 @@ NvLength size = 64 * 1024; NvLength stride = 32 * size; - NvLength start = stride * 248 + 256LL * 1024 * 1024 * 1024 + (1LL << 47); + NvLength start = (248 * stride) + (256 * UVM_SIZE_1GB) + (128 * UVM_SIZE_1TB); int i; - MEM_NV_CHECK_RET(test_page_tree_init(gpu, BIG_PAGE_SIZE_PASCAL, &tree), NV_OK); + MEM_NV_CHECK_RET(test_page_tree_init_kernel(gpu, BIG_PAGE_SIZE_PASCAL, &tree), NV_OK); for (i = 0; i < 16; i++) MEM_NV_CHECK_RET(test_page_tree_get_ptes(&tree, UVM_PAGE_SIZE_64K, start + i * stride, size, range + i), NV_OK); @@ -650,9 +675,9 @@ NvU64 start = 1UL << 47; - NvLength size = 1 << 21; + NvLength size = 2 * UVM_SIZE_1MB; - MEM_NV_CHECK_RET(test_page_tree_init(gpu, BIG_PAGE_SIZE_PASCAL, &tree), NV_OK); + MEM_NV_CHECK_RET(test_page_tree_init_kernel(gpu, BIG_PAGE_SIZE_PASCAL, &tree), NV_OK); MEM_NV_CHECK_RET(test_page_tree_get_ptes(&tree, UVM_PAGE_SIZE_4K, start, size, &range), NV_OK); TEST_CHECK_RET(range.table == tree.root->entries[1]->entries[0]->entries[0]->entries[1]); @@ -672,13 +697,13 @@ uvm_page_tree_t tree; uvm_page_table_range_t range; - NvU64 start = 1UL << 47; - NvLength size = 512UL * 512 * 1024 * 1024; + NvU64 start = 1UL << 48; + NvLength size = 512UL * UVM_PAGE_SIZE_512M; - MEM_NV_CHECK_RET(test_page_tree_init(gpu, BIG_PAGE_SIZE_PASCAL, &tree), NV_OK); + MEM_NV_CHECK_RET(test_page_tree_init_kernel(gpu, BIG_PAGE_SIZE_PASCAL, &tree), NV_OK); MEM_NV_CHECK_RET(test_page_tree_get_ptes(&tree, UVM_PAGE_SIZE_512M, start, size, &range), NV_OK); - TEST_CHECK_RET(range.table == tree.root->entries[1]->entries[0]); + TEST_CHECK_RET(range.table == tree.root->entries[2]->entries[0]); TEST_CHECK_RET(range.entry_count == 512); TEST_CHECK_RET(range.table->depth == 2); TEST_CHECK_RET(range.page_size == UVM_PAGE_SIZE_512M); @@ -699,9 +724,9 @@ uvm_page_table_range_t range_64k; NvU64 start = 1UL << 48; - NvLength size = 1 << 21; + NvLength size = 2 * UVM_SIZE_1MB; - MEM_NV_CHECK_RET(test_page_tree_init(gpu, BIG_PAGE_SIZE_PASCAL, &tree), NV_OK); + MEM_NV_CHECK_RET(test_page_tree_init_kernel(gpu, BIG_PAGE_SIZE_PASCAL, &tree), NV_OK); MEM_NV_CHECK_RET(test_page_tree_get_ptes(&tree, UVM_PAGE_SIZE_2M, start, size, &range_2m), NV_OK); MEM_NV_CHECK_RET(test_page_tree_get_ptes(&tree, UVM_PAGE_SIZE_2M, start + size, size, &range_adj), NV_OK); @@ -747,9 +772,9 @@ uvm_page_table_range_t range_2m; NvU64 start = 1UL << 48; - NvLength size = 512UL * 1024 * 1024; + NvLength size = UVM_PAGE_SIZE_512M; - MEM_NV_CHECK_RET(test_page_tree_init(gpu, BIG_PAGE_SIZE_PASCAL, &tree), NV_OK); + MEM_NV_CHECK_RET(test_page_tree_init_kernel(gpu, BIG_PAGE_SIZE_PASCAL, &tree), NV_OK); MEM_NV_CHECK_RET(test_page_tree_get_ptes(&tree, UVM_PAGE_SIZE_512M, start, size, &range_512m), NV_OK); MEM_NV_CHECK_RET(test_page_tree_get_ptes(&tree, UVM_PAGE_SIZE_512M, start + size, size, &range_adj), NV_OK); @@ -800,7 +825,7 @@ uvm_page_tree_t tree; uvm_page_table_range_t range; - NvU64 start = 2UL * (1 << 30); + NvU64 start = 2 * UVM_SIZE_1GB; NvU64 size = start; MEM_NV_CHECK_RET(test_page_tree_init(gpu, BIG_PAGE_SIZE_PASCAL, &tree), NV_OK); @@ -830,6 +855,7 @@ TEST_CHECK_RET(range2.entry_count == 256); TEST_CHECK_RET(range2.table->ref_count == 512); TEST_CHECK_RET(range1.table == range2.table); + // 4k page is second entry in a dual PDE TEST_CHECK_RET(range1.table == tree.root->entries[0]->entries[0]->entries[0]->entries[1]); TEST_CHECK_RET(range1.start_index == 256); @@ -859,6 +885,7 @@ MEM_NV_CHECK_RET(test_page_tree_get_ptes(&tree, UVM_PAGE_SIZE_64K, size, size, &range64k), NV_OK); TEST_CHECK_RET(range64k.entry_count == 16); TEST_CHECK_RET(range64k.table->ref_count == 16); + // 4k page is second entry in a dual PDE TEST_CHECK_RET(range64k.table == tree.root->entries[0]->entries[0]->entries[0]->entries[0]); TEST_CHECK_RET(range64k.start_index == 16); @@ -1018,14 +1045,17 @@ // Depth 4 NvU64 extent_pte = UVM_PAGE_SIZE_2M; + // Depth 3 NvU64 extent_pde0 = extent_pte * (1ull << 8); + // Depth 2 NvU64 extent_pde1 = extent_pde0 * (1ull << 9); + // Depth 1 NvU64 extent_pde2 = extent_pde1 * (1ull << 9); - MEM_NV_CHECK_RET(test_page_tree_init(gpu, BIG_PAGE_SIZE_PASCAL, &tree), NV_OK); + MEM_NV_CHECK_RET(test_page_tree_init_kernel(gpu, BIG_PAGE_SIZE_PASCAL, &tree), NV_OK); fake_tlb_invals_enable(); @@ -1069,7 +1099,11 @@ return status; } -static NV_STATUS test_tlb_batch_invalidates_case(uvm_page_tree_t *tree, NvU64 base, NvU64 size, NvU32 min_page_size, NvU32 max_page_size) +static NV_STATUS test_tlb_batch_invalidates_case(uvm_page_tree_t *tree, + NvU64 base, + NvU64 size, + NvU32 min_page_size, + NvU32 max_page_size) { NV_STATUS status = NV_OK; uvm_push_t push; @@ -1193,7 +1227,11 @@ NvU64 expected_pte = expecting_cleared ? 0 : range_vec->size + offset; if (*pte != expected_pte) { UVM_TEST_PRINT("PTE is 0x%llx instead of 0x%llx for offset 0x%llx within range [0x%llx, 0x%llx)\n", - *pte, expected_pte, offset, range_vec->start, range_vec->size); + *pte, + expected_pte, + offset, + range_vec->start, + range_vec->size); return false; } offset += range_vec->page_size; @@ -1214,7 +1252,11 @@ TEST_CHECK_RET(data.status == NV_OK); TEST_CHECK_RET(data.count == range_vec->size / range_vec->page_size); TEST_CHECK_RET(assert_invalidate_range_specific(g_last_fake_inval, - range_vec->start, range_vec->size, range_vec->page_size, page_table_depth, membar != UVM_MEMBAR_NONE)); + range_vec->start, + range_vec->size, + range_vec->page_size, + page_table_depth, + membar != UVM_MEMBAR_NONE)); TEST_CHECK_RET(assert_range_vec_ptes(range_vec, false)); fake_tlb_invals_disable(); @@ -1237,7 +1279,11 @@ return NV_OK; } -static NV_STATUS test_range_vec_create(uvm_page_tree_t *tree, NvU64 start, NvU64 size, NvU32 page_size, uvm_page_table_range_vec_t **range_vec_out) +static NV_STATUS test_range_vec_create(uvm_page_tree_t *tree, + NvU64 start, + NvU64 size, + NvU32 page_size, + uvm_page_table_range_vec_t **range_vec_out) { uvm_page_table_range_vec_t *range_vec; uvm_pmm_alloc_flags_t pmm_flags = UVM_PMM_ALLOC_FLAGS_EVICT; @@ -1270,7 +1316,7 @@ NvU32 i; NvU64 offsets[4]; - MEM_NV_CHECK_RET(test_page_tree_init(gpu, big_page_size, &tree), NV_OK); + MEM_NV_CHECK_RET(test_page_tree_init_kernel(gpu, big_page_size, &tree), NV_OK); pde_coverage = uvm_mmu_pde_coverage(&tree, page_size); page_table_entries = pde_coverage / page_size; @@ -1532,25 +1578,28 @@ uvm_mmu_page_table_alloc_t alloc_sys = fake_table_alloc(UVM_APERTURE_SYS, 0x9999999000LL); uvm_mmu_page_table_alloc_t alloc_vid = fake_table_alloc(UVM_APERTURE_VID, 0x1BBBBBB000LL); uvm_mmu_mode_hal_t *hal; + uvm_page_directory_t dir; NvU32 i, j, big_page_size, page_size; + dir.depth = 0; + for (i = 0; i < ARRAY_SIZE(big_page_sizes); i++) { big_page_size = big_page_sizes[i]; hal = gpu->parent->arch_hal->mmu_mode_hal(big_page_size); memset(phys_allocs, 0, sizeof(phys_allocs)); - hal->make_pde(&pde_bits, phys_allocs, 0); + hal->make_pde(&pde_bits, phys_allocs, &dir, 0); TEST_CHECK_RET(pde_bits == 0x0L); phys_allocs[0] = &alloc_sys; phys_allocs[1] = &alloc_vid; - hal->make_pde(&pde_bits, phys_allocs, 0); + hal->make_pde(&pde_bits, phys_allocs, &dir, 0); TEST_CHECK_RET(pde_bits == 0x1BBBBBBD99999992LL); phys_allocs[0] = &alloc_vid; phys_allocs[1] = &alloc_sys; - hal->make_pde(&pde_bits, phys_allocs, 0); + hal->make_pde(&pde_bits, phys_allocs, &dir, 0); TEST_CHECK_RET(pde_bits == 0x9999999E1BBBBBB1LL); for (j = 0; j <= 2; j++) { @@ -1620,38 +1669,47 @@ uvm_mmu_page_table_alloc_t *phys_allocs[2] = {NULL, NULL}; uvm_mmu_page_table_alloc_t alloc_sys = fake_table_alloc(UVM_APERTURE_SYS, 0x399999999999000LL); uvm_mmu_page_table_alloc_t alloc_vid = fake_table_alloc(UVM_APERTURE_VID, 0x1BBBBBB000LL); + uvm_page_directory_t dir; + // big versions have [11:8] set as well to test the page table merging uvm_mmu_page_table_alloc_t alloc_big_sys = fake_table_alloc(UVM_APERTURE_SYS, 0x399999999999900LL); uvm_mmu_page_table_alloc_t alloc_big_vid = fake_table_alloc(UVM_APERTURE_VID, 0x1BBBBBBB00LL); uvm_mmu_mode_hal_t *hal = gpu->parent->arch_hal->mmu_mode_hal(UVM_PAGE_SIZE_64K); + dir.index_in_parent = 0; + dir.host_parent = NULL; + dir.depth = 0; + // Make sure cleared PDEs work as expected - hal->make_pde(pde_bits, phys_allocs, 0); + hal->make_pde(pde_bits, phys_allocs, &dir, 0); TEST_CHECK_RET(pde_bits[0] == 0); memset(pde_bits, 0xFF, sizeof(pde_bits)); - hal->make_pde(pde_bits, phys_allocs, 3); + dir.depth = 3; + hal->make_pde(pde_bits, phys_allocs, &dir, 0); TEST_CHECK_RET(pde_bits[0] == 0 && pde_bits[1] == 0); // Sys and vidmem PDEs phys_allocs[0] = &alloc_sys; - hal->make_pde(pde_bits, phys_allocs, 0); + dir.depth = 0; + hal->make_pde(pde_bits, phys_allocs, &dir, 0); TEST_CHECK_RET(pde_bits[0] == 0x3999999999990C); phys_allocs[0] = &alloc_vid; - hal->make_pde(pde_bits, phys_allocs, 0); + hal->make_pde(pde_bits, phys_allocs, &dir, 0); TEST_CHECK_RET(pde_bits[0] == 0x1BBBBBB0A); // Dual PDEs phys_allocs[0] = &alloc_big_sys; phys_allocs[1] = &alloc_vid; - hal->make_pde(pde_bits, phys_allocs, 3); + dir.depth = 3; + hal->make_pde(pde_bits, phys_allocs, &dir, 0); TEST_CHECK_RET(pde_bits[0] == 0x3999999999999C && pde_bits[1] == 0x1BBBBBB0A); phys_allocs[0] = &alloc_big_vid; phys_allocs[1] = &alloc_sys; - hal->make_pde(pde_bits, phys_allocs, 3); + hal->make_pde(pde_bits, phys_allocs, &dir, 0); TEST_CHECK_RET(pde_bits[0] == 0x1BBBBBBBA && pde_bits[1] == 0x3999999999990C); // uncached, i.e., the sysmem data is not cached in GPU's L2 cache. Clear @@ -1707,6 +1765,7 @@ uvm_mmu_page_table_alloc_t *phys_allocs[2] = {NULL, NULL}; uvm_mmu_page_table_alloc_t alloc_sys = fake_table_alloc(UVM_APERTURE_SYS, 0x399999999999000LL); uvm_mmu_page_table_alloc_t alloc_vid = fake_table_alloc(UVM_APERTURE_VID, 0x1BBBBBB000LL); + uvm_page_directory_t dir; // big versions have [11:8] set as well to test the page table merging uvm_mmu_page_table_alloc_t alloc_big_sys = fake_table_alloc(UVM_APERTURE_SYS, 0x399999999999900LL); @@ -1714,37 +1773,45 @@ uvm_mmu_mode_hal_t *hal = gpu->parent->arch_hal->mmu_mode_hal(UVM_PAGE_SIZE_64K); + dir.index_in_parent = 0; + dir.host_parent = NULL; + dir.depth = 0; + // Make sure cleared PDEs work as expected - hal->make_pde(pde_bits, phys_allocs, 0); + hal->make_pde(pde_bits, phys_allocs, &dir, 0); TEST_CHECK_RET(pde_bits[0] == 0); memset(pde_bits, 0xFF, sizeof(pde_bits)); - hal->make_pde(pde_bits, phys_allocs, 3); + dir.depth = 3; + hal->make_pde(pde_bits, phys_allocs, &dir, 0); TEST_CHECK_RET(pde_bits[0] == 0 && pde_bits[1] == 0); // Sys and vidmem PDEs phys_allocs[0] = &alloc_sys; - hal->make_pde(pde_bits, phys_allocs, 0); + dir.depth = 0; + hal->make_pde(pde_bits, phys_allocs, &dir, 0); TEST_CHECK_RET(pde_bits[0] == 0x3999999999990C); phys_allocs[0] = &alloc_vid; - hal->make_pde(pde_bits, phys_allocs, 0); + hal->make_pde(pde_bits, phys_allocs, &dir, 0); TEST_CHECK_RET(pde_bits[0] == 0x1BBBBBB0A); // Dual PDEs phys_allocs[0] = &alloc_big_sys; phys_allocs[1] = &alloc_vid; - hal->make_pde(pde_bits, phys_allocs, 3); + dir.depth = 3; + hal->make_pde(pde_bits, phys_allocs, &dir, 0); TEST_CHECK_RET(pde_bits[0] == 0x3999999999999C && pde_bits[1] == 0x1BBBBBB0A); phys_allocs[0] = &alloc_big_vid; phys_allocs[1] = &alloc_sys; - hal->make_pde(pde_bits, phys_allocs, 3); + hal->make_pde(pde_bits, phys_allocs, &dir, 0); TEST_CHECK_RET(pde_bits[0] == 0x1BBBBBBBA && pde_bits[1] == 0x3999999999990C); // NO_ATS PDE1 (depth 2) phys_allocs[0] = &alloc_vid; - hal->make_pde(pde_bits, phys_allocs, 2); + dir.depth = 2; + hal->make_pde(pde_bits, phys_allocs, &dir, 0); if (g_uvm_global.ats.enabled) TEST_CHECK_RET(pde_bits[0] == 0x1BBBBBB2A); else @@ -1779,104 +1846,203 @@ static NV_STATUS entry_test_hopper(uvm_gpu_t *gpu, entry_test_page_size_func entry_test_page_size) { + NV_STATUS status = NV_OK; NvU32 page_sizes[MAX_NUM_PAGE_SIZES]; NvU64 pde_bits[2]; + uvm_page_directory_t *dirs[5]; size_t i, num_page_sizes; uvm_mmu_page_table_alloc_t *phys_allocs[2] = {NULL, NULL}; uvm_mmu_page_table_alloc_t alloc_sys = fake_table_alloc(UVM_APERTURE_SYS, 0x9999999999000LL); uvm_mmu_page_table_alloc_t alloc_vid = fake_table_alloc(UVM_APERTURE_VID, 0xBBBBBBB000LL); - // big versions have [11:8] set as well to test the page table merging + // Big versions have [11:8] set as well to test the page table merging uvm_mmu_page_table_alloc_t alloc_big_sys = fake_table_alloc(UVM_APERTURE_SYS, 0x9999999999900LL); uvm_mmu_page_table_alloc_t alloc_big_vid = fake_table_alloc(UVM_APERTURE_VID, 0xBBBBBBBB00LL); uvm_mmu_mode_hal_t *hal = gpu->parent->arch_hal->mmu_mode_hal(UVM_PAGE_SIZE_64K); - // Make sure cleared PDEs work as expected - hal->make_pde(pde_bits, phys_allocs, 0); - TEST_CHECK_RET(pde_bits[0] == 0); + memset(dirs, 0, sizeof(dirs)); + // Fake directory tree. + for (i = 0; i < ARRAY_SIZE(dirs); i++) { + dirs[i] = uvm_kvmalloc_zero(sizeof(uvm_page_directory_t) + sizeof(dirs[i]->entries[0]) * 512); + TEST_CHECK_GOTO(dirs[i] != NULL, cleanup); + + dirs[i]->depth = i; + dirs[i]->index_in_parent = 0; + + if (i == 0) + dirs[i]->host_parent = NULL; + else + dirs[i]->host_parent = dirs[i - 1]; + } + + // Make sure cleared PDEs work as expected. + hal->make_pde(pde_bits, phys_allocs, dirs[0], 0); + TEST_CHECK_GOTO(pde_bits[0] == 0, cleanup); // Cleared PDEs work as expected for big and small PDEs. memset(pde_bits, 0xFF, sizeof(pde_bits)); - hal->make_pde(pde_bits, phys_allocs, 4); - TEST_CHECK_RET(pde_bits[0] == 0 && pde_bits[1] == 0); + hal->make_pde(pde_bits, phys_allocs, dirs[4], 0); + TEST_CHECK_GOTO(pde_bits[0] == 0 && pde_bits[1] == 0, cleanup); // Sys and vidmem PDEs, uncached ATS allowed. phys_allocs[0] = &alloc_sys; - hal->make_pde(pde_bits, phys_allocs, 0); - TEST_CHECK_RET(pde_bits[0] == 0x999999999900C); + hal->make_pde(pde_bits, phys_allocs, dirs[0], 0); + TEST_CHECK_GOTO(pde_bits[0] == 0x999999999900C, cleanup); phys_allocs[0] = &alloc_vid; - hal->make_pde(pde_bits, phys_allocs, 0); - TEST_CHECK_RET(pde_bits[0] == 0xBBBBBBB00A); + hal->make_pde(pde_bits, phys_allocs, dirs[0], 0); + TEST_CHECK_GOTO(pde_bits[0] == 0xBBBBBBB00A, cleanup); - // Dual PDEs, uncached. + // Dual PDEs, uncached. We don't use child_dir in the depth 4 checks because + // our policy decides the PDE's PCF without using it. phys_allocs[0] = &alloc_big_sys; phys_allocs[1] = &alloc_vid; - hal->make_pde(pde_bits, phys_allocs, 4); - TEST_CHECK_RET(pde_bits[0] == 0x999999999991C && pde_bits[1] == 0xBBBBBBB01A); + hal->make_pde(pde_bits, phys_allocs, dirs[4], 0); + if (g_uvm_global.ats.enabled) + TEST_CHECK_GOTO(pde_bits[0] == 0x999999999991C && pde_bits[1] == 0xBBBBBBB01A, cleanup); + else + TEST_CHECK_GOTO(pde_bits[0] == 0x999999999990C && pde_bits[1] == 0xBBBBBBB00A, cleanup); phys_allocs[0] = &alloc_big_vid; phys_allocs[1] = &alloc_sys; - hal->make_pde(pde_bits, phys_allocs, 4); - TEST_CHECK_RET(pde_bits[0] == 0xBBBBBBBB1A && pde_bits[1] == 0x999999999901C); + hal->make_pde(pde_bits, phys_allocs, dirs[4], 0); + if (g_uvm_global.ats.enabled) + TEST_CHECK_GOTO(pde_bits[0] == 0xBBBBBBBB1A && pde_bits[1] == 0x999999999901C, cleanup); + else + TEST_CHECK_GOTO(pde_bits[0] == 0xBBBBBBBB0A && pde_bits[1] == 0x999999999900C, cleanup); + + // We only need to test make_pde() on ATS when the CPU VA width < GPU's. + if (g_uvm_global.ats.enabled && uvm_cpu_num_va_bits() < hal->num_va_bits()) { + phys_allocs[0] = &alloc_sys; + + dirs[1]->index_in_parent = 0; + hal->make_pde(pde_bits, phys_allocs, dirs[0], 0); + TEST_CHECK_GOTO(pde_bits[0] == 0x999999999900C, cleanup); + + dirs[2]->index_in_parent = 0; + hal->make_pde(pde_bits, phys_allocs, dirs[1], 0); + TEST_CHECK_GOTO(pde_bits[0] == 0x999999999901C, cleanup); + + dirs[2]->index_in_parent = 1; + hal->make_pde(pde_bits, phys_allocs, dirs[1], 1); + TEST_CHECK_GOTO(pde_bits[0] == 0x999999999901C, cleanup); + + dirs[2]->index_in_parent = 2; + hal->make_pde(pde_bits, phys_allocs, dirs[1], 2); + TEST_CHECK_GOTO(pde_bits[0] == 0x999999999901C, cleanup); + + dirs[2]->index_in_parent = 511; + hal->make_pde(pde_bits, phys_allocs, dirs[1], 511); + TEST_CHECK_GOTO(pde_bits[0] == 0x999999999901C, cleanup); + + dirs[1]->index_in_parent = 1; + hal->make_pde(pde_bits, phys_allocs, dirs[0], 1); + TEST_CHECK_GOTO(pde_bits[0] == 0x999999999900C, cleanup); + + dirs[2]->index_in_parent = 0; + hal->make_pde(pde_bits, phys_allocs, dirs[1], 0); + TEST_CHECK_GOTO(pde_bits[0] == 0x999999999901C, cleanup); + + dirs[2]->index_in_parent = 509; + hal->make_pde(pde_bits, phys_allocs, dirs[1], 509); + TEST_CHECK_GOTO(pde_bits[0] == 0x999999999901C, cleanup); + + dirs[2]->index_in_parent = 510; + hal->make_pde(pde_bits, phys_allocs, dirs[1], 510); + TEST_CHECK_GOTO(pde_bits[0] == 0x999999999901C, cleanup); + + phys_allocs[0] = NULL; + + dirs[1]->index_in_parent = 0; + hal->make_pde(pde_bits, phys_allocs, dirs[0], 0); + TEST_CHECK_GOTO(pde_bits[0] == 0x0, cleanup); + + dirs[2]->index_in_parent = 0; + hal->make_pde(pde_bits, phys_allocs, dirs[1], 0); + TEST_CHECK_GOTO(pde_bits[0] == 0x0, cleanup); + + dirs[2]->index_in_parent = 2; + hal->make_pde(pde_bits, phys_allocs, dirs[1], 2); + TEST_CHECK_GOTO(pde_bits[0] == 0x10, cleanup); + + dirs[1]->index_in_parent = 1; + dirs[2]->index_in_parent = 509; + hal->make_pde(pde_bits, phys_allocs, dirs[1], 509); + TEST_CHECK_GOTO(pde_bits[0] == 0x10, cleanup); + + dirs[2]->index_in_parent = 510; + hal->make_pde(pde_bits, phys_allocs, dirs[1], 510); + TEST_CHECK_GOTO(pde_bits[0] == 0x0, cleanup); + } // uncached, i.e., the sysmem data is not cached in GPU's L2 cache, and // access counters disabled. - TEST_CHECK_RET(hal->make_pte(UVM_APERTURE_SYS, - 0x9999999999000LL, - UVM_PROT_READ_WRITE_ATOMIC, - UVM_MMU_PTE_FLAGS_ACCESS_COUNTERS_DISABLED) == 0x999999999968D); + TEST_CHECK_GOTO(hal->make_pte(UVM_APERTURE_SYS, + 0x9999999999000LL, + UVM_PROT_READ_WRITE_ATOMIC, + UVM_MMU_PTE_FLAGS_ACCESS_COUNTERS_DISABLED) == 0x999999999968D, + cleanup); // change to cached. - TEST_CHECK_RET(hal->make_pte(UVM_APERTURE_SYS, - 0x9999999999000LL, - UVM_PROT_READ_WRITE_ATOMIC, - UVM_MMU_PTE_FLAGS_CACHED | UVM_MMU_PTE_FLAGS_ACCESS_COUNTERS_DISABLED) == - 0x9999999999685); + TEST_CHECK_GOTO(hal->make_pte(UVM_APERTURE_SYS, + 0x9999999999000LL, + UVM_PROT_READ_WRITE_ATOMIC, + UVM_MMU_PTE_FLAGS_CACHED | UVM_MMU_PTE_FLAGS_ACCESS_COUNTERS_DISABLED) == + 0x9999999999685, + cleanup); // enable access counters. - TEST_CHECK_RET(hal->make_pte(UVM_APERTURE_SYS, - 0x9999999999000LL, - UVM_PROT_READ_WRITE_ATOMIC, - UVM_MMU_PTE_FLAGS_CACHED) == 0x9999999999605); + TEST_CHECK_GOTO(hal->make_pte(UVM_APERTURE_SYS, + 0x9999999999000LL, + UVM_PROT_READ_WRITE_ATOMIC, + UVM_MMU_PTE_FLAGS_CACHED) == 0x9999999999605, + cleanup); // remove atomic - TEST_CHECK_RET(hal->make_pte(UVM_APERTURE_SYS, - 0x9999999999000LL, - UVM_PROT_READ_WRITE, - UVM_MMU_PTE_FLAGS_CACHED) == 0x9999999999645); + TEST_CHECK_GOTO(hal->make_pte(UVM_APERTURE_SYS, + 0x9999999999000LL, + UVM_PROT_READ_WRITE, + UVM_MMU_PTE_FLAGS_CACHED) == 0x9999999999645, + cleanup); // read only - TEST_CHECK_RET(hal->make_pte(UVM_APERTURE_SYS, - 0x9999999999000LL, - UVM_PROT_READ_ONLY, - UVM_MMU_PTE_FLAGS_CACHED) == 0x9999999999665); + TEST_CHECK_GOTO(hal->make_pte(UVM_APERTURE_SYS, + 0x9999999999000LL, + UVM_PROT_READ_ONLY, + UVM_MMU_PTE_FLAGS_CACHED) == 0x9999999999665, + cleanup); // local video - TEST_CHECK_RET(hal->make_pte(UVM_APERTURE_VID, - 0xBBBBBBB000LL, - UVM_PROT_READ_ONLY, - UVM_MMU_PTE_FLAGS_CACHED) == 0xBBBBBBB661); + TEST_CHECK_GOTO(hal->make_pte(UVM_APERTURE_VID, + 0xBBBBBBB000LL, + UVM_PROT_READ_ONLY, + UVM_MMU_PTE_FLAGS_CACHED) == 0xBBBBBBB661, + cleanup); // peer 1 - TEST_CHECK_RET(hal->make_pte(UVM_APERTURE_PEER_1, - 0xBBBBBBB000LL, - UVM_PROT_READ_ONLY, - UVM_MMU_PTE_FLAGS_CACHED) == 0x200000BBBBBBB663); + TEST_CHECK_GOTO(hal->make_pte(UVM_APERTURE_PEER_1, + 0xBBBBBBB000LL, + UVM_PROT_READ_ONLY, + UVM_MMU_PTE_FLAGS_CACHED) == 0x200000BBBBBBB663, + cleanup); // sparse - TEST_CHECK_RET(hal->make_sparse_pte() == 0x8); + TEST_CHECK_GOTO(hal->make_sparse_pte() == 0x8, cleanup); // sked reflected - TEST_CHECK_RET(hal->make_sked_reflected_pte() == 0xF09); + TEST_CHECK_GOTO(hal->make_sked_reflected_pte() == 0xF09, cleanup); num_page_sizes = get_page_sizes(gpu, page_sizes); for (i = 0; i < num_page_sizes; i++) - TEST_NV_CHECK_RET(entry_test_page_size(gpu, page_sizes[i])); + TEST_NV_CHECK_GOTO(entry_test_page_size(gpu, page_sizes[i]), cleanup); - return NV_OK; +cleanup: + for (i = 0; i < ARRAY_SIZE(dirs); i++) + uvm_kvfree(dirs[i]); + + return status; } static NV_STATUS alloc_4k_maxwell(uvm_gpu_t *gpu) @@ -2291,7 +2457,8 @@ gpu->parent = parent_gpu; // At least test_tlb_invalidates() relies on global state - // (g_tlb_invalidate_*) so make sure only one test instance can run at a time. + // (g_tlb_invalidate_*) so make sure only one test instance can run at a + // time. uvm_mutex_lock(&g_uvm_global.global_lock); // Allocate the fake TLB tracking state. Notably tests still need to enable @@ -2299,7 +2466,13 @@ // calls. TEST_NV_CHECK_GOTO(fake_tlb_invals_alloc(), done); - TEST_NV_CHECK_GOTO(maxwell_test_page_tree(gpu), done); + // We prevent the maxwell_test_page_tree test from running on ATS-enabled + // systems. On "fake" Maxwell-based ATS systems pde_fill() may push more + // methods than what we support in UVM. Specifically, on + // uvm_page_tree_init() which eventually calls phys_mem_init(). On Maxwell, + // upper PDE levels have more than 512 entries. + if (!g_uvm_global.ats.enabled) + TEST_NV_CHECK_GOTO(maxwell_test_page_tree(gpu), done); TEST_NV_CHECK_GOTO(pascal_test_page_tree(gpu), done); TEST_NV_CHECK_GOTO(volta_test_page_tree(gpu), done); TEST_NV_CHECK_GOTO(ampere_test_page_tree(gpu), done); diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/kernel-open/nvidia-uvm/uvm_pascal.c nvidia-open-gpu-kernel-modules-535.161.08/kernel-open/nvidia-uvm/uvm_pascal.c --- nvidia-open-gpu-kernel-modules-525.147.05/kernel-open/nvidia-uvm/uvm_pascal.c 2023-10-25 20:33:38.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/kernel-open/nvidia-uvm/uvm_pascal.c 2024-03-05 22:25:55.000000000 +0000 @@ -1,5 +1,5 @@ /******************************************************************************* - Copyright (c) 2016-2020 NVIDIA Corporation + Copyright (c) 2016-2023 NVIDIA Corporation Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation files (the "Software"), to @@ -49,11 +49,13 @@ // A single top level PDE on Pascal covers 128 TB and that's the minimum // size that can be used. parent_gpu->rm_va_base = 0; - parent_gpu->rm_va_size = 128ull * 1024 * 1024 * 1024 * 1024; + parent_gpu->rm_va_size = 128 * UVM_SIZE_1TB; - parent_gpu->uvm_mem_va_base = 384ull * 1024 * 1024 * 1024 * 1024; + parent_gpu->uvm_mem_va_base = 384 * UVM_SIZE_1TB; parent_gpu->uvm_mem_va_size = UVM_MEM_VA_SIZE; + parent_gpu->ce_phys_vidmem_write_supported = true; + parent_gpu->peer_copy_mode = UVM_GPU_PEER_COPY_MODE_VIRTUAL; // Not all units on Pascal support 49-bit addressing, including those which @@ -98,4 +100,6 @@ parent_gpu->smc.supported = false; parent_gpu->plc_supported = false; + + parent_gpu->no_ats_range_required = false; } diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/kernel-open/nvidia-uvm/uvm_pascal_ce.c nvidia-open-gpu-kernel-modules-535.161.08/kernel-open/nvidia-uvm/uvm_pascal_ce.c --- nvidia-open-gpu-kernel-modules-525.147.05/kernel-open/nvidia-uvm/uvm_pascal_ce.c 2023-10-25 20:33:38.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/kernel-open/nvidia-uvm/uvm_pascal_ce.c 2024-03-05 22:25:55.000000000 +0000 @@ -39,32 +39,6 @@ OFFSET_OUT_LOWER, HWVALUE(C0B5, OFFSET_OUT_LOWER, VALUE, NvOffset_LO32(offset_out))); } -// Perform an appropriate membar before a semaphore operation. Returns whether -// the semaphore operation should include a flush. -static bool pascal_membar_before_semaphore(uvm_push_t *push) -{ - uvm_gpu_t *gpu; - - if (uvm_push_get_and_reset_flag(push, UVM_PUSH_FLAG_NEXT_MEMBAR_NONE)) { - // No MEMBAR requested, don't use a flush. - return false; - } - - if (!uvm_push_get_and_reset_flag(push, UVM_PUSH_FLAG_NEXT_MEMBAR_GPU)) { - // By default do a MEMBAR SYS and for that we can just use flush on the - // semaphore operation. - return true; - } - - // MEMBAR GPU requested, do it on the HOST and skip the CE flush as CE - // doesn't have this capability. - gpu = uvm_push_get_gpu(push); - gpu->parent->host_hal->wait_for_idle(push); - gpu->parent->host_hal->membar_gpu(push); - - return false; -} - void uvm_hal_pascal_ce_semaphore_release(uvm_push_t *push, NvU64 gpu_va, NvU32 payload) { uvm_gpu_t *gpu = uvm_push_get_gpu(push); @@ -72,7 +46,7 @@ NvU32 launch_dma_plc_mode; bool use_flush; - use_flush = pascal_membar_before_semaphore(push); + use_flush = uvm_hal_membar_before_semaphore(push); if (use_flush) flush_value = HWCONST(C0B5, LAUNCH_DMA, FLUSH_ENABLE, TRUE); @@ -98,7 +72,7 @@ NvU32 launch_dma_plc_mode; bool use_flush; - use_flush = pascal_membar_before_semaphore(push); + use_flush = uvm_hal_membar_before_semaphore(push); if (use_flush) flush_value = HWCONST(C0B5, LAUNCH_DMA, FLUSH_ENABLE, TRUE); @@ -127,7 +101,7 @@ NvU32 launch_dma_plc_mode; bool use_flush; - use_flush = pascal_membar_before_semaphore(push); + use_flush = uvm_hal_membar_before_semaphore(push); if (use_flush) flush_value = HWCONST(C0B5, LAUNCH_DMA, FLUSH_ENABLE, TRUE); diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/kernel-open/nvidia-uvm/uvm_pascal_fault_buffer.c nvidia-open-gpu-kernel-modules-535.161.08/kernel-open/nvidia-uvm/uvm_pascal_fault_buffer.c --- nvidia-open-gpu-kernel-modules-525.147.05/kernel-open/nvidia-uvm/uvm_pascal_fault_buffer.c 2023-10-25 20:33:38.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/kernel-open/nvidia-uvm/uvm_pascal_fault_buffer.c 2024-03-05 22:25:56.000000000 +0000 @@ -1,5 +1,5 @@ /******************************************************************************* - Copyright (c) 2016-2021 NVIDIA Corporation + Copyright (c) 2016-2023 NVIDIA Corporation Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation files (the "Software"), to @@ -105,7 +105,7 @@ return UVM_FAULT_ACCESS_TYPE_COUNT; } -static uvm_fault_type_t get_fault_type(const NvU32 *fault_entry) +uvm_fault_type_t uvm_hal_pascal_fault_buffer_get_fault_type(const NvU32 *fault_entry) { NvU32 hw_fault_type_value = READ_HWVALUE_MW(fault_entry, B069, FAULT_BUF_ENTRY, FAULT_TYPE); @@ -197,11 +197,27 @@ return fault_entry; } -void uvm_hal_pascal_fault_buffer_parse_entry(uvm_parent_gpu_t *parent_gpu, - NvU32 index, - uvm_fault_buffer_entry_t *buffer_entry) +// When Confidential Computing is enabled, fault entries are encrypted. Each +// fault has (unencrypted) metadata containing the authentication tag, and a +// valid bit that allows UVM to check if an encrypted fault is valid, without +// having to decrypt it first. +static UvmFaultMetadataPacket *get_fault_buffer_entry_metadata(uvm_parent_gpu_t *parent_gpu, NvU32 index) +{ + UvmFaultMetadataPacket *fault_entry_metadata; + + UVM_ASSERT(index < parent_gpu->fault_buffer_info.replayable.max_faults); + UVM_ASSERT(!uvm_parent_gpu_replayable_fault_buffer_is_uvm_owned(parent_gpu)); + + fault_entry_metadata = parent_gpu->fault_buffer_info.rm_info.replayable.bufferMetadata; + UVM_ASSERT(fault_entry_metadata != NULL); + + return fault_entry_metadata + index; +} + +NV_STATUS uvm_hal_pascal_fault_buffer_parse_replayable_entry(uvm_parent_gpu_t *parent_gpu, + NvU32 index, + uvm_fault_buffer_entry_t *buffer_entry) { - NV_STATUS status; NvU32 *fault_entry; NvU64 addr_hi, addr_lo; NvU64 timestamp_hi, timestamp_lo; @@ -209,13 +225,12 @@ NvU32 utlb_id; BUILD_BUG_ON(NVB069_FAULT_BUF_SIZE > UVM_GPU_MMU_MAX_FAULT_PACKET_SIZE); - status = NV_OK; - - fault_entry = get_fault_buffer_entry(parent_gpu, index); // Valid bit must be set before this function is called UVM_ASSERT(parent_gpu->fault_buffer_hal->entry_is_valid(parent_gpu, index)); + fault_entry = get_fault_buffer_entry(parent_gpu, index); + addr_hi = READ_HWVALUE_MW(fault_entry, B069, FAULT_BUF_ENTRY, INST_HI); addr_lo = READ_HWVALUE_MW(fault_entry, B069, FAULT_BUF_ENTRY, INST_LO); buffer_entry->instance_ptr.address = addr_lo + (addr_hi << HWSIZE_MW(B069, FAULT_BUF_ENTRY, INST_LO)); @@ -233,7 +248,7 @@ timestamp_lo = READ_HWVALUE_MW(fault_entry, B069, FAULT_BUF_ENTRY, TIMESTAMP_LO); buffer_entry->timestamp = timestamp_lo + (timestamp_hi << HWSIZE_MW(B069, FAULT_BUF_ENTRY, TIMESTAMP_LO)); - buffer_entry->fault_type = get_fault_type(fault_entry); + buffer_entry->fault_type = parent_gpu->fault_buffer_hal->get_fault_type(fault_entry); buffer_entry->fault_access_type = get_fault_access_type(fault_entry); @@ -265,27 +280,45 @@ // Automatically clear valid bit for the entry in the fault buffer uvm_hal_pascal_fault_buffer_entry_clear_valid(parent_gpu, index); + + return NV_OK; } bool uvm_hal_pascal_fault_buffer_entry_is_valid(uvm_parent_gpu_t *parent_gpu, NvU32 index) { - NvU32 *fault_entry; - bool is_valid; + if (uvm_parent_gpu_replayable_fault_buffer_is_uvm_owned(parent_gpu)) { + NvU32 *fault_entry = get_fault_buffer_entry(parent_gpu, index); - fault_entry = get_fault_buffer_entry(parent_gpu, index); + return READ_HWVALUE_MW(fault_entry, B069, FAULT_BUF_ENTRY, VALID); + } + else { + // Use the valid bit present in the encryption metadata, which is + // unencrypted, instead of the valid bit present in the (encrypted) + // fault itself. + UvmFaultMetadataPacket *fault_entry_metadata = get_fault_buffer_entry_metadata(parent_gpu, index); - is_valid = READ_HWVALUE_MW(fault_entry, B069, FAULT_BUF_ENTRY, VALID); + return fault_entry_metadata->valid; + } - return is_valid; + UVM_ASSERT_MSG(false, "Invalid path"); + return false; } void uvm_hal_pascal_fault_buffer_entry_clear_valid(uvm_parent_gpu_t *parent_gpu, NvU32 index) { - NvU32 *fault_entry; + if (uvm_parent_gpu_replayable_fault_buffer_is_uvm_owned(parent_gpu)) { + NvU32 *fault_entry = get_fault_buffer_entry(parent_gpu, index); - fault_entry = get_fault_buffer_entry(parent_gpu, index); + WRITE_HWCONST_MW(fault_entry, B069, FAULT_BUF_ENTRY, VALID, FALSE); + } + else { + // Use the valid bit present in the encryption metadata, which is + // unencrypted, instead of the valid bit present in the (encrypted) + // fault itself. + UvmFaultMetadataPacket *fault_entry_metadata = get_fault_buffer_entry_metadata(parent_gpu, index); - WRITE_HWCONST_MW(fault_entry, B069, FAULT_BUF_ENTRY, VALID, FALSE); + fault_entry_metadata->valid = false; + } } NvU32 uvm_hal_pascal_fault_buffer_entry_size(uvm_parent_gpu_t *parent_gpu) diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/kernel-open/nvidia-uvm/uvm_pascal_mmu.c nvidia-open-gpu-kernel-modules-535.161.08/kernel-open/nvidia-uvm/uvm_pascal_mmu.c --- nvidia-open-gpu-kernel-modules-525.147.05/kernel-open/nvidia-uvm/uvm_pascal_mmu.c 2023-10-25 20:33:38.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/kernel-open/nvidia-uvm/uvm_pascal_mmu.c 2024-03-05 22:25:56.000000000 +0000 @@ -1,5 +1,5 @@ /******************************************************************************* - Copyright (c) 2015-2020 NVIDIA Corporation + Copyright (c) 2015-2023 NVIDIA Corporation Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation files (the "Software"), to @@ -140,11 +140,18 @@ return pde_bits; } -static void make_pde_pascal(void *entry, uvm_mmu_page_table_alloc_t **phys_allocs, NvU32 depth) +static void make_pde_pascal(void *entry, + uvm_mmu_page_table_alloc_t **phys_allocs, + uvm_page_directory_t *dir, + NvU32 child_index) { - NvU32 entry_count = entries_per_index_pascal(depth); + NvU32 entry_count; NvU64 *entry_bits = (NvU64 *)entry; + UVM_ASSERT(dir); + + entry_count = entries_per_index_pascal(dir->depth); + if (entry_count == 1) { *entry_bits = single_pde_pascal(*phys_allocs); } @@ -152,7 +159,8 @@ entry_bits[MMU_BIG] = big_half_pde_pascal(phys_allocs[MMU_BIG]); entry_bits[MMU_SMALL] = small_half_pde_pascal(phys_allocs[MMU_SMALL]); - // This entry applies to the whole dual PDE but is stored in the lower bits + // This entry applies to the whole dual PDE but is stored in the lower + // bits. entry_bits[MMU_BIG] |= HWCONST64(_MMU_VER2, DUAL_PDE, IS_PDE, TRUE); } else { diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/kernel-open/nvidia-uvm/uvm_perf_events.h nvidia-open-gpu-kernel-modules-535.161.08/kernel-open/nvidia-uvm/uvm_perf_events.h --- nvidia-open-gpu-kernel-modules-525.147.05/kernel-open/nvidia-uvm/uvm_perf_events.h 2023-10-25 20:33:36.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/kernel-open/nvidia-uvm/uvm_perf_events.h 2024-03-05 22:25:54.000000000 +0000 @@ -54,6 +54,9 @@ // Locking: uvm_va_space: write UVM_PERF_EVENT_BLOCK_SHRINK, + // Locking: HMM uvm_va_block lock + UVM_PERF_EVENT_BLOCK_MUNMAP, + // Locking: uvm_va_space: write UVM_PERF_EVENT_RANGE_DESTROY, @@ -91,6 +94,12 @@ struct { + uvm_va_block_t *block; + uvm_va_block_region_t region; + } block_munmap; + + struct + { uvm_va_range_t *range; } range_destroy; diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/kernel-open/nvidia-uvm/uvm_perf_prefetch.c nvidia-open-gpu-kernel-modules-535.161.08/kernel-open/nvidia-uvm/uvm_perf_prefetch.c --- nvidia-open-gpu-kernel-modules-525.147.05/kernel-open/nvidia-uvm/uvm_perf_prefetch.c 2023-10-25 20:33:41.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/kernel-open/nvidia-uvm/uvm_perf_prefetch.c 2024-03-05 22:26:05.000000000 +0000 @@ -1,5 +1,5 @@ /******************************************************************************* - Copyright (c) 2016-2022 NVIDIA Corporation + Copyright (c) 2016-2023 NVIDIA Corporation Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation files (the "Software"), to @@ -218,57 +218,11 @@ } } -// Within a block we only allow prefetching to a single processor. Therefore, -// if two processors are accessing non-overlapping regions within the same -// block they won't benefit from prefetching. -// -// TODO: Bug 1778034: [uvm] Explore prefetching to different processors within -// a VA block. -static NvU32 uvm_perf_prefetch_prenotify_fault_migrations(uvm_va_block_t *va_block, - uvm_va_block_context_t *va_block_context, - uvm_processor_id_t new_residency, - const uvm_page_mask_t *faulted_pages, - uvm_va_block_region_t faulted_region, - uvm_page_mask_t *prefetch_pages, - uvm_perf_prefetch_bitmap_tree_t *bitmap_tree) +static void init_bitmap_tree_from_region(uvm_perf_prefetch_bitmap_tree_t *bitmap_tree, + uvm_va_block_region_t max_prefetch_region, + const uvm_page_mask_t *resident_mask, + const uvm_page_mask_t *faulted_pages) { - uvm_page_index_t page_index; - const uvm_page_mask_t *resident_mask = NULL; - const uvm_page_mask_t *thrashing_pages = NULL; - uvm_va_space_t *va_space = uvm_va_block_get_va_space(va_block); - uvm_va_policy_t *policy = va_block_context->policy; - uvm_va_block_region_t max_prefetch_region; - NvU32 big_page_size; - uvm_va_block_region_t big_pages_region; - - if (!uvm_id_equal(va_block->prefetch_info.last_migration_proc_id, new_residency)) { - va_block->prefetch_info.last_migration_proc_id = new_residency; - va_block->prefetch_info.fault_migrations_to_last_proc = 0; - } - - // Compute the expanded region that prefetching is allowed from. - if (uvm_va_block_is_hmm(va_block)) { - max_prefetch_region = uvm_hmm_get_prefetch_region(va_block, - va_block_context, - uvm_va_block_region_start(va_block, faulted_region)); - } - else { - max_prefetch_region = uvm_va_block_region_from_block(va_block); - } - - uvm_page_mask_zero(prefetch_pages); - - if (UVM_ID_IS_CPU(new_residency) || va_block->gpus[uvm_id_gpu_index(new_residency)] != NULL) - resident_mask = uvm_va_block_resident_mask_get(va_block, new_residency); - - // If this is a first-touch fault and the destination processor is the - // preferred location, populate the whole max_prefetch_region. - if (uvm_processor_mask_empty(&va_block->resident) && - uvm_id_equal(new_residency, policy->preferred_location)) { - uvm_page_mask_region_fill(prefetch_pages, max_prefetch_region); - goto done; - } - if (resident_mask) uvm_page_mask_or(&bitmap_tree->pages, resident_mask, faulted_pages); else @@ -277,6 +231,29 @@ // If we are using a subregion of the va_block, align bitmap_tree uvm_page_mask_shift_right(&bitmap_tree->pages, &bitmap_tree->pages, max_prefetch_region.first); + bitmap_tree->offset = 0; + bitmap_tree->leaf_count = uvm_va_block_region_num_pages(max_prefetch_region); + bitmap_tree->level_count = ilog2(roundup_pow_of_two(bitmap_tree->leaf_count)) + 1; +} + +static void update_bitmap_tree_from_va_block(uvm_perf_prefetch_bitmap_tree_t *bitmap_tree, + uvm_va_block_t *va_block, + uvm_va_block_context_t *va_block_context, + uvm_processor_id_t new_residency, + const uvm_page_mask_t *faulted_pages, + uvm_va_block_region_t max_prefetch_region) + +{ + NvU32 big_page_size; + uvm_va_block_region_t big_pages_region; + uvm_va_space_t *va_space; + const uvm_page_mask_t *thrashing_pages; + + UVM_ASSERT(va_block); + UVM_ASSERT(va_block_context); + + va_space = uvm_va_block_get_va_space(va_block); + // Get the big page size for the new residency. // Assume 64K size if the new residency is the CPU or no GPU va space is // registered in the current process for this GPU. @@ -302,13 +279,9 @@ UVM_ASSERT(bitmap_tree->leaf_count <= PAGES_PER_UVM_VA_BLOCK); uvm_page_mask_shift_left(&bitmap_tree->pages, &bitmap_tree->pages, bitmap_tree->offset); - } - else { - bitmap_tree->offset = 0; - bitmap_tree->leaf_count = uvm_va_block_region_num_pages(max_prefetch_region); - } - bitmap_tree->level_count = ilog2(roundup_pow_of_two(bitmap_tree->leaf_count)) + 1; + bitmap_tree->level_count = ilog2(roundup_pow_of_two(bitmap_tree->leaf_count)) + 1; + } thrashing_pages = uvm_perf_thrashing_get_thrashing_pages(va_block); @@ -320,25 +293,99 @@ max_prefetch_region, faulted_pages, thrashing_pages); +} - // Do not compute prefetch regions with faults on pages that are thrashing - if (thrashing_pages) - uvm_page_mask_andnot(&va_block_context->scratch_page_mask, faulted_pages, thrashing_pages); - else - uvm_page_mask_copy(&va_block_context->scratch_page_mask, faulted_pages); +static void compute_prefetch_mask(uvm_va_block_region_t faulted_region, + uvm_va_block_region_t max_prefetch_region, + uvm_perf_prefetch_bitmap_tree_t *bitmap_tree, + const uvm_page_mask_t *faulted_pages, + uvm_page_mask_t *out_prefetch_mask) +{ + uvm_page_index_t page_index; + + uvm_page_mask_zero(out_prefetch_mask); - // Update the tree using the scratch mask to compute the pages to prefetch - for_each_va_block_page_in_region_mask(page_index, &va_block_context->scratch_page_mask, faulted_region) { + // Update the tree using the faulted mask to compute the pages to prefetch. + for_each_va_block_page_in_region_mask(page_index, faulted_pages, faulted_region) { uvm_va_block_region_t region = compute_prefetch_region(page_index, bitmap_tree, max_prefetch_region); - uvm_page_mask_region_fill(prefetch_pages, region); + uvm_page_mask_region_fill(out_prefetch_mask, region); // Early out if we have already prefetched until the end of the VA block if (region.outer == max_prefetch_region.outer) break; } +} + +// Within a block we only allow prefetching to a single processor. Therefore, +// if two processors are accessing non-overlapping regions within the same +// block they won't benefit from prefetching. +// +// TODO: Bug 1778034: [uvm] Explore prefetching to different processors within +// a VA block. +static NvU32 uvm_perf_prefetch_prenotify_fault_migrations(uvm_va_block_t *va_block, + uvm_va_block_context_t *va_block_context, + uvm_processor_id_t new_residency, + const uvm_page_mask_t *faulted_pages, + uvm_va_block_region_t faulted_region, + uvm_page_mask_t *prefetch_pages, + uvm_perf_prefetch_bitmap_tree_t *bitmap_tree) +{ + const uvm_page_mask_t *resident_mask = NULL; + const uvm_va_policy_t *policy = uvm_va_policy_get_region(va_block, faulted_region); + uvm_va_block_region_t max_prefetch_region; + const uvm_page_mask_t *thrashing_pages = uvm_perf_thrashing_get_thrashing_pages(va_block); + + if (!uvm_id_equal(va_block->prefetch_info.last_migration_proc_id, new_residency)) { + va_block->prefetch_info.last_migration_proc_id = new_residency; + va_block->prefetch_info.fault_migrations_to_last_proc = 0; + } + + // Compute the expanded region that prefetching is allowed from. + if (uvm_va_block_is_hmm(va_block)) { + max_prefetch_region = uvm_hmm_get_prefetch_region(va_block, + va_block_context->hmm.vma, + policy, + uvm_va_block_region_start(va_block, faulted_region)); + } + else { + max_prefetch_region = uvm_va_block_region_from_block(va_block); + } + + uvm_page_mask_zero(prefetch_pages); + + if (UVM_ID_IS_CPU(new_residency) || va_block->gpus[uvm_id_gpu_index(new_residency)] != NULL) + resident_mask = uvm_va_block_resident_mask_get(va_block, new_residency); + + // If this is a first-touch fault and the destination processor is the + // preferred location, populate the whole max_prefetch_region. + if (uvm_processor_mask_empty(&va_block->resident) && + uvm_id_equal(new_residency, policy->preferred_location)) { + uvm_page_mask_region_fill(prefetch_pages, max_prefetch_region); + } + else { + init_bitmap_tree_from_region(bitmap_tree, max_prefetch_region, resident_mask, faulted_pages); + + update_bitmap_tree_from_va_block(bitmap_tree, + va_block, + va_block_context, + new_residency, + faulted_pages, + max_prefetch_region); + + // Do not compute prefetch regions with faults on pages that are thrashing + if (thrashing_pages) + uvm_page_mask_andnot(&va_block_context->scratch_page_mask, faulted_pages, thrashing_pages); + else + uvm_page_mask_copy(&va_block_context->scratch_page_mask, faulted_pages); + + compute_prefetch_mask(faulted_region, + max_prefetch_region, + bitmap_tree, + &va_block_context->scratch_page_mask, + prefetch_pages); + } -done: // Do not prefetch pages that are going to be migrated/populated due to a // fault uvm_page_mask_andnot(prefetch_pages, prefetch_pages, faulted_pages); @@ -364,30 +411,58 @@ return uvm_page_mask_weight(prefetch_pages); } -void uvm_perf_prefetch_get_hint(uvm_va_block_t *va_block, - uvm_va_block_context_t *va_block_context, - uvm_processor_id_t new_residency, - const uvm_page_mask_t *faulted_pages, - uvm_va_block_region_t faulted_region, - uvm_perf_prefetch_bitmap_tree_t *bitmap_tree, - uvm_perf_prefetch_hint_t *out_hint) +bool uvm_perf_prefetch_enabled(uvm_va_space_t *va_space) +{ + if (!g_uvm_perf_prefetch_enable) + return false; + + UVM_ASSERT(va_space); + + return va_space->test.page_prefetch_enabled; +} + +void uvm_perf_prefetch_compute_ats(uvm_va_space_t *va_space, + const uvm_page_mask_t *faulted_pages, + uvm_va_block_region_t faulted_region, + uvm_va_block_region_t max_prefetch_region, + const uvm_page_mask_t *residency_mask, + uvm_perf_prefetch_bitmap_tree_t *bitmap_tree, + uvm_page_mask_t *out_prefetch_mask) +{ + UVM_ASSERT(faulted_pages); + UVM_ASSERT(bitmap_tree); + UVM_ASSERT(out_prefetch_mask); + + uvm_page_mask_zero(out_prefetch_mask); + + if (!uvm_perf_prefetch_enabled(va_space)) + return; + + init_bitmap_tree_from_region(bitmap_tree, max_prefetch_region, residency_mask, faulted_pages); + + compute_prefetch_mask(faulted_region, max_prefetch_region, bitmap_tree, faulted_pages, out_prefetch_mask); +} + +void uvm_perf_prefetch_get_hint_va_block(uvm_va_block_t *va_block, + uvm_va_block_context_t *va_block_context, + uvm_processor_id_t new_residency, + const uvm_page_mask_t *faulted_pages, + uvm_va_block_region_t faulted_region, + uvm_perf_prefetch_bitmap_tree_t *bitmap_tree, + uvm_perf_prefetch_hint_t *out_hint) { - uvm_va_policy_t *policy = va_block_context->policy; uvm_va_space_t *va_space = uvm_va_block_get_va_space(va_block); uvm_page_mask_t *prefetch_pages = &out_hint->prefetch_pages_mask; NvU32 pending_prefetch_pages; uvm_assert_rwsem_locked(&va_space->lock); uvm_assert_mutex_locked(&va_block->lock); - UVM_ASSERT(uvm_va_block_check_policy_is_valid(va_block, policy, faulted_region)); - UVM_ASSERT(uvm_hmm_va_block_context_vma_is_valid(va_block, va_block_context, faulted_region)); + UVM_ASSERT(uvm_hmm_check_context_vma_is_valid(va_block, va_block_context->hmm.vma, faulted_region)); out_hint->residency = UVM_ID_INVALID; + uvm_page_mask_zero(prefetch_pages); - if (!g_uvm_perf_prefetch_enable) - return; - - if (!va_space->test.page_prefetch_enabled) + if (!uvm_perf_prefetch_enabled(va_space)) return; pending_prefetch_pages = uvm_perf_prefetch_prenotify_fault_migrations(va_block, diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/kernel-open/nvidia-uvm/uvm_perf_prefetch.h nvidia-open-gpu-kernel-modules-535.161.08/kernel-open/nvidia-uvm/uvm_perf_prefetch.h --- nvidia-open-gpu-kernel-modules-525.147.05/kernel-open/nvidia-uvm/uvm_perf_prefetch.h 2023-10-25 20:33:41.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/kernel-open/nvidia-uvm/uvm_perf_prefetch.h 2024-03-05 22:26:05.000000000 +0000 @@ -61,21 +61,41 @@ // Global initialization function (no clean up needed). NV_STATUS uvm_perf_prefetch_init(void); +// Returns whether prefetching is enabled in the VA space. +// va_space cannot be NULL. +bool uvm_perf_prefetch_enabled(uvm_va_space_t *va_space); + +// Return the prefetch mask with the pages that may be prefetched in a ATS +// block. ATS block is a system allocated memory block with base aligned to +// UVM_VA_BLOCK_SIZE and a maximum size of UVM_VA_BLOCK_SIZE. The faulted_pages +// mask and faulted_region are the pages being faulted on the given residency. +// +// Only residency_mask can be NULL. +// +// Locking: The caller must hold the va_space lock. +void uvm_perf_prefetch_compute_ats(uvm_va_space_t *va_space, + const uvm_page_mask_t *faulted_pages, + uvm_va_block_region_t faulted_region, + uvm_va_block_region_t max_prefetch_region, + const uvm_page_mask_t *residency_mask, + uvm_perf_prefetch_bitmap_tree_t *bitmap_tree, + uvm_page_mask_t *out_prefetch_mask); + // Return a hint with the pages that may be prefetched in the block. // The faulted_pages mask and faulted_region are the pages being migrated to // the given residency. -// va_block_context must not be NULL, va_block_context->policy must be valid, -// and if the va_block is a HMM block, va_block_context->hmm.vma must be valid -// which also means the va_block_context->mm is not NULL, retained, and locked -// for at least read. +// va_block_context must not be NULL, and if the va_block is a HMM +// block, va_block_context->hmm.vma must be valid which also means the +// va_block_context->mm is not NULL, retained, and locked for at least +// read. // Locking: The caller must hold the va_space lock and va_block lock. -void uvm_perf_prefetch_get_hint(uvm_va_block_t *va_block, - uvm_va_block_context_t *va_block_context, - uvm_processor_id_t new_residency, - const uvm_page_mask_t *faulted_pages, - uvm_va_block_region_t faulted_region, - uvm_perf_prefetch_bitmap_tree_t *bitmap_tree, - uvm_perf_prefetch_hint_t *out_hint); +void uvm_perf_prefetch_get_hint_va_block(uvm_va_block_t *va_block, + uvm_va_block_context_t *va_block_context, + uvm_processor_id_t new_residency, + const uvm_page_mask_t *faulted_pages, + uvm_va_block_region_t faulted_region, + uvm_perf_prefetch_bitmap_tree_t *bitmap_tree, + uvm_perf_prefetch_hint_t *out_hint); void uvm_perf_prefetch_bitmap_tree_iter_init(const uvm_perf_prefetch_bitmap_tree_t *bitmap_tree, uvm_page_index_t page_index, diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/kernel-open/nvidia-uvm/uvm_perf_thrashing.c nvidia-open-gpu-kernel-modules-535.161.08/kernel-open/nvidia-uvm/uvm_perf_thrashing.c --- nvidia-open-gpu-kernel-modules-525.147.05/kernel-open/nvidia-uvm/uvm_perf_thrashing.c 2023-10-25 20:33:41.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/kernel-open/nvidia-uvm/uvm_perf_thrashing.c 2024-03-05 22:26:05.000000000 +0000 @@ -1,5 +1,5 @@ /******************************************************************************* - Copyright (c) 2016-2022 NVIDIA Corporation + Copyright (c) 2016-2023 NVIDIA Corporation Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation files (the "Software"), to @@ -22,6 +22,7 @@ *******************************************************************************/ #include "uvm_api.h" +#include "uvm_conf_computing.h" #include "uvm_perf_events.h" #include "uvm_perf_module.h" #include "uvm_perf_thrashing.h" @@ -262,6 +263,7 @@ // detection/prevention parameters #define UVM_PERF_THRASHING_LAPSE_USEC_DEFAULT 500 #define UVM_PERF_THRASHING_LAPSE_USEC_DEFAULT_EMULATION (UVM_PERF_THRASHING_LAPSE_USEC_DEFAULT * 800) +#define UVM_PERF_THRASHING_LAPSE_USEC_DEFAULT_HCC (UVM_PERF_THRASHING_LAPSE_USEC_DEFAULT * 10) // Lapse of time in microseconds that determines if two consecutive events on // the same page can be considered thrashing @@ -398,11 +400,13 @@ // Callback declaration for the performance heuristics events static void thrashing_event_cb(uvm_perf_event_t event_id, uvm_perf_event_data_t *event_data); static void thrashing_block_destroy_cb(uvm_perf_event_t event_id, uvm_perf_event_data_t *event_data); +static void thrashing_block_munmap_cb(uvm_perf_event_t event_id, uvm_perf_event_data_t *event_data); static uvm_perf_module_event_callback_desc_t g_callbacks_thrashing[] = { { UVM_PERF_EVENT_BLOCK_DESTROY, thrashing_block_destroy_cb }, { UVM_PERF_EVENT_MODULE_UNLOAD, thrashing_block_destroy_cb }, { UVM_PERF_EVENT_BLOCK_SHRINK , thrashing_block_destroy_cb }, + { UVM_PERF_EVENT_BLOCK_MUNMAP , thrashing_block_munmap_cb }, { UVM_PERF_EVENT_MIGRATION, thrashing_event_cb }, { UVM_PERF_EVENT_REVOCATION, thrashing_event_cb } }; @@ -530,18 +534,20 @@ // Get the thrashing detection struct for the given VA space if it exists // -// VA space lock needs to be held +// The caller must ensure that the va_space cannot be deleted, for the +// duration of this call. Holding either the va_block or va_space lock will do +// that. static va_space_thrashing_info_t *va_space_thrashing_info_get_or_null(uvm_va_space_t *va_space) { - uvm_assert_rwsem_locked(&va_space->lock); - return uvm_perf_module_type_data(va_space->perf_modules_data, UVM_PERF_MODULE_TYPE_THRASHING); } // Get the thrashing detection struct for the given VA space. It asserts that // the information has been previously created. // -// VA space lock needs to be held +// The caller must ensure that the va_space cannot be deleted, for the +// duration of this call. Holding either the va_block or va_space lock will do +// that. static va_space_thrashing_info_t *va_space_thrashing_info_get(uvm_va_space_t *va_space) { va_space_thrashing_info_t *va_space_thrashing = va_space_thrashing_info_get_or_null(va_space); @@ -689,6 +695,20 @@ uvm_perf_thrashing_info_destroy(va_block); } +void thrashing_block_munmap_cb(uvm_perf_event_t event_id, uvm_perf_event_data_t *event_data) +{ + uvm_va_block_t *va_block = event_data->block_munmap.block; + uvm_va_block_region_t region = event_data->block_munmap.region; + + UVM_ASSERT(g_uvm_perf_thrashing_enable); + UVM_ASSERT(event_id == UVM_PERF_EVENT_BLOCK_MUNMAP); + UVM_ASSERT(va_block); + + thrashing_reset_pages_in_region(va_block, + uvm_va_block_region_start(va_block, region), + uvm_va_block_region_size(region)); +} + // Sanity checks of the thrashing tracking state static bool thrashing_state_checks(uvm_va_block_t *va_block, block_thrashing_info_t *block_thrashing, @@ -1075,7 +1095,7 @@ NV_STATUS tracker_status; uvm_tracker_t local_tracker = UVM_TRACKER_INIT(); uvm_processor_id_t processor_id; - uvm_va_policy_t *policy = va_block_context->policy; + const uvm_va_policy_t *policy = uvm_va_policy_get(va_block, uvm_va_block_region_start(va_block, region)); uvm_assert_mutex_locked(&va_block->lock); @@ -1121,10 +1141,9 @@ { block_thrashing_info_t *block_thrashing; uvm_processor_mask_t unmap_processors; - uvm_va_policy_t *policy = va_block_context->policy; + const uvm_va_policy_t *policy = uvm_va_policy_get_region(va_block, region); uvm_assert_mutex_locked(&va_block->lock); - UVM_ASSERT(uvm_va_block_check_policy_is_valid(va_block, policy, region)); block_thrashing = thrashing_info_get(va_block); if (!block_thrashing || !block_thrashing->pages) @@ -1425,7 +1444,7 @@ uvm_va_space_t *va_space = uvm_va_block_get_va_space(va_block); uvm_processor_id_t do_not_throttle_processor = page_thrashing->do_not_throttle_processor_id; uvm_processor_id_t pinned_residency = page_thrashing->pinned_residency_id; - uvm_va_policy_t *policy; + const uvm_va_policy_t *policy; uvm_processor_id_t preferred_location; policy = uvm_va_policy_get(va_block, uvm_va_block_cpu_page_address(va_block, page_index)); @@ -1435,7 +1454,18 @@ hint.type = UVM_PERF_THRASHING_HINT_TYPE_NONE; closest_resident_id = uvm_va_block_page_get_closest_resident(va_block, page_index, requester); - UVM_ASSERT(UVM_ID_IS_VALID(closest_resident_id)); + if (uvm_va_block_is_hmm(va_block)) { + // HMM pages always start out resident on the CPU but may not be + // recorded in the va_block state because hmm_range_fault() or + // similar functions haven't been called to get an accurate snapshot + // of the Linux state. We can assume pages are CPU resident for the + // purpose of deciding where to migrate to reduce thrashing. + if (UVM_ID_IS_INVALID(closest_resident_id)) + closest_resident_id = UVM_ID_CPU; + } + else { + UVM_ASSERT(UVM_ID_IS_VALID(closest_resident_id)); + } if (thrashing_processors_can_access(va_space, page_thrashing, preferred_location)) { // The logic in uvm_va_block_select_residency chooses the preferred @@ -1519,8 +1549,9 @@ } } } - else if (uvm_processor_mask_test(&va_space->accessible_from[uvm_id_value(page_thrashing->pinned_residency_id)], requester)) { - UVM_ASSERT(uvm_id_equal(closest_resident_id, pinned_residency)); + else if (uvm_processor_mask_test(&va_space->accessible_from[uvm_id_value(pinned_residency)], requester)) { + if (!uvm_va_block_is_hmm(va_block)) + UVM_ASSERT(uvm_id_equal(closest_resident_id, pinned_residency)); hint.type = UVM_PERF_THRASHING_HINT_TYPE_PIN; hint.pin.residency = pinned_residency; @@ -1766,22 +1797,6 @@ return &block_thrashing->thrashing_pages; } -bool uvm_perf_thrashing_is_block_thrashing(uvm_va_block_t *va_block) -{ - uvm_va_space_t *va_space = uvm_va_block_get_va_space(va_block); - va_space_thrashing_info_t *va_space_thrashing = va_space_thrashing_info_get(va_space); - block_thrashing_info_t *block_thrashing = NULL; - - if (!va_space_thrashing->params.enable) - return false; - - block_thrashing = thrashing_info_get(va_block); - if (!block_thrashing) - return false; - - return block_thrashing->num_thrashing_pages > 0; -} - #define TIMER_GRANULARITY_NS 20000ULL static void thrashing_unpin_pages(struct work_struct *work) { @@ -1790,8 +1805,6 @@ uvm_va_space_t *va_space = va_space_thrashing->va_space; uvm_va_block_context_t *va_block_context = &va_space_thrashing->pinned_pages.va_block_context; - UVM_ASSERT(uvm_va_space_initialized(va_space) == NV_OK); - // Take the VA space lock so that VA blocks don't go away during this // operation. uvm_va_space_down_read(va_space); @@ -1839,6 +1852,8 @@ break; va_block = pinned_page->va_block; + if (uvm_va_block_is_hmm(va_block)) + uvm_hmm_migrate_begin_wait(va_block); uvm_mutex_lock(&va_block->lock); // Only operate if the pinned page's tracking state isn't already @@ -1851,8 +1866,6 @@ UVM_ASSERT(uvm_page_mask_test(&block_thrashing->pinned_pages.mask, page_index)); uvm_va_block_context_init(va_block_context, NULL); - va_block_context->policy = - uvm_va_policy_get(va_block, uvm_va_block_cpu_page_address(va_block, page_index)); uvm_perf_thrashing_unmap_remote_pinned_pages_all(va_block, va_block_context, @@ -1861,6 +1874,8 @@ } uvm_mutex_unlock(&va_block->lock); + if (uvm_va_block_is_hmm(va_block)) + uvm_hmm_migrate_finish(va_block); kmem_cache_free(g_pinned_page_cache, pinned_page); } @@ -1932,12 +1947,24 @@ NV_STATUS uvm_perf_thrashing_register_gpu(uvm_va_space_t *va_space, uvm_gpu_t *gpu) { // If a simulated GPU is registered, re-initialize thrashing parameters in - // case they need to be adjusted - if (g_uvm_global.num_simulated_devices > 0) { + // case they need to be adjusted. + bool params_need_readjusting = g_uvm_global.num_simulated_devices > 0; + + // Likewise, when the Confidential Computing feature is enabled, the DMA + // path is slower due to cryptographic operations & other associated + // overhead. Enforce a larger window to allow the thrashing mitigation + // mechanisms to work properly. + params_need_readjusting = params_need_readjusting || uvm_conf_computing_mode_enabled(gpu); + + if (params_need_readjusting) { va_space_thrashing_info_t *va_space_thrashing = va_space_thrashing_info_get(va_space); - if (!va_space_thrashing->params.test_overrides) + if (!va_space_thrashing->params.test_overrides) { + if (uvm_conf_computing_mode_enabled(gpu)) + g_uvm_perf_thrashing_lapse_usec = UVM_PERF_THRASHING_LAPSE_USEC_DEFAULT_HCC; + va_space_thrashing_info_init_params(va_space_thrashing); + } } return NV_OK; @@ -2093,8 +2120,6 @@ uvm_va_block_region_t va_block_region = uvm_va_block_region_from_block(va_block); uvm_va_block_context_t *block_context = uvm_va_space_block_context(va_space, NULL); - block_context->policy = uvm_va_range_get_policy(va_range); - uvm_mutex_lock(&va_block->lock); // Unmap may split PTEs and require a retry. Needs to be called diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/kernel-open/nvidia-uvm/uvm_perf_thrashing.h nvidia-open-gpu-kernel-modules-535.161.08/kernel-open/nvidia-uvm/uvm_perf_thrashing.h --- nvidia-open-gpu-kernel-modules-525.147.05/kernel-open/nvidia-uvm/uvm_perf_thrashing.h 2023-10-25 20:33:41.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/kernel-open/nvidia-uvm/uvm_perf_thrashing.h 2024-03-05 22:26:04.000000000 +0000 @@ -84,9 +84,6 @@ const uvm_page_mask_t *uvm_perf_thrashing_get_thrashing_pages(uvm_va_block_t *va_block); -// Returns true if any page in the block is thrashing, or false otherwise -bool uvm_perf_thrashing_is_block_thrashing(uvm_va_block_t *va_block); - // Global initialization/cleanup functions NV_STATUS uvm_perf_thrashing_init(void); void uvm_perf_thrashing_exit(void); @@ -106,11 +103,11 @@ // Destroy the thrashing detection struct for the given block. void uvm_perf_thrashing_info_destroy(uvm_va_block_t *va_block); -// Unmap remote mappings from all processors on the pinned pages -// described by region and block_thrashing->pinned pages. -// va_block_context must not be NULL and va_block_context->policy must be valid. -// See the comments for uvm_va_block_check_policy_is_valid() in uvm_va_block.h. -// Locking: the va_block lock must be held. +// Unmap remote mappings from all processors on the pinned pages described by +// region and block_thrashing->pinned pages. va_block_context must not be NULL +// and policy for the region must match. See the comments for +// uvm_va_block_check_policy_is_valid() in uvm_va_block.h. Locking: the +// va_block lock must be held. NV_STATUS uvm_perf_thrashing_unmap_remote_pinned_pages_all(uvm_va_block_t *va_block, uvm_va_block_context_t *va_block_context, uvm_va_block_region_t region); diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/kernel-open/nvidia-uvm/uvm_pmm_gpu.c nvidia-open-gpu-kernel-modules-535.161.08/kernel-open/nvidia-uvm/uvm_pmm_gpu.c --- nvidia-open-gpu-kernel-modules-525.147.05/kernel-open/nvidia-uvm/uvm_pmm_gpu.c 2023-10-25 20:33:40.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/kernel-open/nvidia-uvm/uvm_pmm_gpu.c 2024-03-05 22:26:01.000000000 +0000 @@ -1,5 +1,5 @@ /******************************************************************************* - Copyright (c) 2015-2022 NVIDIA Corporation + Copyright (c) 2015-2023 NVIDIA Corporation Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation files (the "Software"), to @@ -100,10 +100,10 @@ // All allocated user memory root chunks are tracked in an LRU list // (root_chunks.va_block_used). A root chunk is moved to the tail of that list // whenever any of its subchunks is allocated (unpinned) by a VA block (see -// uvm_pmm_gpu_unpin_temp()). When a root chunk is selected for eviction, it has -// the eviction flag set (see pick_root_chunk_to_evict()). This flag affects -// many of the PMM operations on all of the subchunks of the root chunk being -// evicted. See usage of (root_)chunk_is_in_eviction(), in particular in +// uvm_pmm_gpu_unpin_allocated()). When a root chunk is selected for eviction, +// it has the eviction flag set (see pick_root_chunk_to_evict()). This flag +// affects many of the PMM operations on all of the subchunks of the root chunk +// being evicted. See usage of (root_)chunk_is_in_eviction(), in particular in // chunk_free_locked() and claim_free_chunk(). // // To evict a root chunk, all of its free subchunks are pinned, then all @@ -172,6 +172,7 @@ #include "uvm_va_block.h" #include "uvm_test.h" #include "uvm_linux.h" +#include "uvm_conf_computing.h" static int uvm_global_oversubscription = 1; module_param(uvm_global_oversubscription, int, S_IRUGO); @@ -242,11 +243,13 @@ { switch (type) { UVM_ENUM_STRING_CASE(UVM_PMM_GPU_MEMORY_TYPE_USER); + UVM_ENUM_STRING_CASE(UVM_PMM_GPU_MEMORY_TYPE_USER_UNPROTECTED); UVM_ENUM_STRING_CASE(UVM_PMM_GPU_MEMORY_TYPE_KERNEL); + UVM_ENUM_STRING_CASE(UVM_PMM_GPU_MEMORY_TYPE_KERNEL_UNPROTECTED); UVM_ENUM_STRING_DEFAULT(); } - BUILD_BUG_ON(UVM_PMM_GPU_MEMORY_TYPE_COUNT != 2); + BUILD_BUG_ON(UVM_PMM_GPU_MEMORY_TYPE_COUNT != 4); } const char *uvm_pmm_gpu_chunk_state_string(uvm_pmm_gpu_chunk_state_t state) @@ -394,7 +397,8 @@ return chunk->suballoc->pinned_leaf_chunks > 0; } -// Pin a chunk and update its root chunk's pinned leaf chunks count if the chunk is not a root chunk +// Pin a chunk and update its root chunk's pinned leaf chunks count if the +// chunk is not a root chunk. static void chunk_pin(uvm_pmm_gpu_t *pmm, uvm_gpu_chunk_t *chunk) { uvm_gpu_root_chunk_t *root_chunk = root_chunk_from_chunk(pmm, chunk); @@ -406,17 +410,20 @@ if (chunk_is_root_chunk(chunk)) return; - // For subchunks, update the pinned leaf chunks count tracked in the suballoc of the root chunk. + // For subchunks, update the pinned leaf chunks count tracked in the + // suballoc of the root chunk. chunk = &root_chunk->chunk; - // The passed-in subchunk is not the root chunk so the root chunk has to be split + // The passed-in subchunk is not the root chunk so the root chunk has to be + // split. UVM_ASSERT_MSG(chunk->state == UVM_PMM_GPU_CHUNK_STATE_IS_SPLIT, "chunk state %s\n", uvm_pmm_gpu_chunk_state_string(chunk->state)); chunk->suballoc->pinned_leaf_chunks++; } -// Unpin a chunk and update its root chunk's pinned leaf chunks count if the chunk is not a root chunk +// Unpin a chunk and update its root chunk's pinned leaf chunks count if the +// chunk is not a root chunk. static void chunk_unpin(uvm_pmm_gpu_t *pmm, uvm_gpu_chunk_t *chunk, uvm_pmm_gpu_chunk_state_t new_state) { uvm_gpu_root_chunk_t *root_chunk = root_chunk_from_chunk(pmm, chunk); @@ -432,10 +439,12 @@ if (chunk_is_root_chunk(chunk)) return; - // For subchunks, update the pinned leaf chunks count tracked in the suballoc of the root chunk. + // For subchunks, update the pinned leaf chunks count tracked in the + // suballoc of the root chunk. chunk = &root_chunk->chunk; - // The passed-in subchunk is not the root chunk so the root chunk has to be split + // The passed-in subchunk is not the root chunk so the root chunk has to be + // split. UVM_ASSERT_MSG(chunk->state == UVM_PMM_GPU_CHUNK_STATE_IS_SPLIT, "chunk state %s\n", uvm_pmm_gpu_chunk_state_string(chunk->state)); @@ -448,7 +457,19 @@ UVM_ASSERT(type < UVM_PMM_GPU_MEMORY_TYPE_COUNT); switch (type) { - case UVM_PMM_GPU_MEMORY_TYPE_USER: + case UVM_PMM_GPU_MEMORY_TYPE_USER: // Alias UVM_PMM_GPU_MEMORY_TYPE_USER_PROTECTED + case UVM_PMM_GPU_MEMORY_TYPE_USER_UNPROTECTED: + return true; + default: + return false; + } +} + +static bool memory_type_is_protected(uvm_pmm_gpu_memory_type_t type) +{ + switch (type) { + case UVM_PMM_GPU_MEMORY_TYPE_USER: // Alias UVM_PMM_GPU_MEMORY_TYPE_USER_PROTECTED + case UVM_PMM_GPU_MEMORY_TYPE_KERNEL: // Alias UVM_PMM_GPU_MEMORY_TYPE_KERNEL_PROTECTED: return true; default: return false; @@ -480,11 +501,11 @@ struct page *uvm_gpu_chunk_to_page(uvm_pmm_gpu_t *pmm, uvm_gpu_chunk_t *chunk) { uvm_gpu_t *gpu = uvm_pmm_to_gpu(pmm); - NvU64 sys_addr = chunk->address + uvm_gpu_numa_info(gpu)->system_memory_window_start; + NvU64 sys_addr = chunk->address + gpu->parent->system_bus.memory_window_start; unsigned long pfn = sys_addr >> PAGE_SHIFT; - UVM_ASSERT(sys_addr + uvm_gpu_chunk_get_size(chunk) <= uvm_gpu_numa_info(gpu)->system_memory_window_end + 1); - UVM_ASSERT(gpu->parent->numa_info.enabled); + UVM_ASSERT(sys_addr + uvm_gpu_chunk_get_size(chunk) <= gpu->parent->system_bus.memory_window_end + 1); + UVM_ASSERT(gpu->mem_info.numa.enabled); return pfn_to_page(pfn); } @@ -514,7 +535,16 @@ static uvm_pmm_gpu_memory_type_t pmm_squash_memory_type(uvm_parent_gpu_t *parent_gpu, uvm_pmm_gpu_memory_type_t type) { - return type; + if (uvm_conf_computing_mode_enabled_parent(parent_gpu)) + return type; + + // Enforce the contract that when the Confidential Computing feature is + // disabled, all user types are alike, as well as all kernel types, + // respectively. See uvm_pmm_gpu_memory_type_t. + if (uvm_pmm_gpu_memory_type_is_user(type)) + return UVM_PMM_GPU_MEMORY_TYPE_USER; + + return UVM_PMM_GPU_MEMORY_TYPE_KERNEL; } NV_STATUS uvm_pmm_gpu_alloc(uvm_pmm_gpu_t *pmm, @@ -609,24 +639,13 @@ uvm_spin_lock(&pmm->list_lock); chunk_unpin(pmm, chunks[i], UVM_PMM_GPU_CHUNK_STATE_ALLOCATED); + chunks[i]->is_referenced = false; uvm_spin_unlock(&pmm->list_lock); } return NV_OK; } -NV_STATUS uvm_pmm_gpu_alloc_kernel(uvm_pmm_gpu_t *pmm, - size_t num_chunks, - uvm_chunk_size_t chunk_size, - uvm_pmm_alloc_flags_t flags, - uvm_gpu_chunk_t **chunks, - uvm_tracker_t *out_tracker) -{ - uvm_pmm_gpu_memory_type_t memory_type = UVM_PMM_GPU_MEMORY_TYPE_KERNEL; - - return pmm_gpu_alloc_kernel(pmm, num_chunks, chunk_size, memory_type, flags, chunks, out_tracker); -} - static void chunk_update_lists_locked(uvm_pmm_gpu_t *pmm, uvm_gpu_chunk_t *chunk) { uvm_gpu_root_chunk_t *root_chunk = root_chunk_from_chunk(pmm, chunk); @@ -653,7 +672,10 @@ list_del_init(&chunk->list); } -void uvm_pmm_gpu_unpin_temp(uvm_pmm_gpu_t *pmm, uvm_gpu_chunk_t *chunk, uvm_va_block_t *va_block) +static void gpu_unpin_temp(uvm_pmm_gpu_t *pmm, + uvm_gpu_chunk_t *chunk, + uvm_va_block_t *va_block, + bool is_referenced) { UVM_ASSERT(chunk->state == UVM_PMM_GPU_CHUNK_STATE_TEMP_PINNED); UVM_ASSERT(uvm_pmm_gpu_memory_type_is_user(chunk->type)); @@ -667,16 +689,26 @@ UVM_ASSERT(chunk->va_block_page_index < uvm_va_block_num_cpu_pages(va_block)); chunk_unpin(pmm, chunk, UVM_PMM_GPU_CHUNK_STATE_ALLOCATED); + chunk->is_referenced = is_referenced; chunk->va_block = va_block; chunk_update_lists_locked(pmm, chunk); uvm_spin_unlock(&pmm->list_lock); } +void uvm_pmm_gpu_unpin_allocated(uvm_pmm_gpu_t *pmm, uvm_gpu_chunk_t *chunk, uvm_va_block_t *va_block) +{ + gpu_unpin_temp(pmm, chunk, va_block, false); +} + +void uvm_pmm_gpu_unpin_referenced(uvm_pmm_gpu_t *pmm, uvm_gpu_chunk_t *chunk, uvm_va_block_t *va_block) +{ + gpu_unpin_temp(pmm, chunk, va_block, true); +} + void uvm_pmm_gpu_free(uvm_pmm_gpu_t *pmm, uvm_gpu_chunk_t *chunk, uvm_tracker_t *tracker) { NV_STATUS status; - uvm_gpu_root_chunk_t *root_chunk; if (!chunk) return; @@ -684,11 +716,12 @@ UVM_ASSERT(chunk->state == UVM_PMM_GPU_CHUNK_STATE_ALLOCATED || chunk->state == UVM_PMM_GPU_CHUNK_STATE_TEMP_PINNED); - root_chunk = root_chunk_from_chunk(pmm, chunk); - if (tracker) { + uvm_gpu_root_chunk_t *root_chunk; + uvm_tracker_remove_completed(tracker); + root_chunk = root_chunk_from_chunk(pmm, chunk); root_chunk_lock(pmm, root_chunk); // Remove any completed entries from the root tracker to prevent it from @@ -756,6 +789,7 @@ UVM_ASSERT(child->va_block == child_va_block); UVM_ASSERT(child->va_block_page_index == prev_child->va_block_page_index + uvm_gpu_chunk_get_size(prev_child) / PAGE_SIZE); + UVM_ASSERT(child->is_referenced == prev_child->is_referenced); } } @@ -799,6 +833,7 @@ UVM_ASSERT(subchunk->va_block); chunk->va_block = subchunk->va_block; chunk->va_block_page_index = subchunk->va_block_page_index; + chunk->is_referenced = subchunk->is_referenced; } else if (child_state == UVM_PMM_GPU_CHUNK_STATE_TEMP_PINNED) { UVM_ASSERT(root_chunk->chunk.suballoc->pinned_leaf_chunks >= num_sub); @@ -1512,7 +1547,7 @@ uvm_gpu_chunk_t *chunk = &root_chunk->chunk; struct page *page; - if (!gpu->parent->numa_info.enabled) + if (!gpu->mem_info.numa.enabled) return false; page = uvm_gpu_chunk_to_page(pmm, chunk); @@ -2013,8 +2048,8 @@ UVM_PANIC(); } -// Allocates a single chunk of a given size. If needed splits a chunk of bigger size -// or, if that is not possible, allocates from PMA or evicts. +// Allocates a single chunk of a given size. If needed, splits a chunk of +// bigger size or, if that is not possible, allocates from PMA or evicts. NV_STATUS alloc_chunk(uvm_pmm_gpu_t *pmm, uvm_pmm_gpu_memory_type_t type, uvm_chunk_size_t chunk_size, @@ -2027,8 +2062,7 @@ chunk = claim_free_chunk(pmm, type, chunk_size); if (chunk) { // A free chunk could be claimed, we are done. - *out_chunk = chunk; - return NV_OK; + goto out; } if (chunk_size == UVM_CHUNK_SIZE_MAX) { @@ -2039,11 +2073,11 @@ if (status != NV_OK) return status; - *out_chunk = chunk; - return NV_OK; + goto out; } - // We didn't find a free chunk and we will require splits so acquire the PMM lock. + // We didn't find a free chunk and we will require splits so acquire the + // PMM lock. uvm_mutex_lock(&pmm->lock); status = alloc_chunk_with_splits(pmm, type, chunk_size, flags, &chunk); @@ -2055,6 +2089,7 @@ return status; } +out: *out_chunk = chunk; return NV_OK; @@ -2132,7 +2167,7 @@ // Also, user pages that are about to be overwritten, don't need to be // zeroed, either. Add an interface to uvm_pmm_gpu_alloc for callers to // specify when they don't need zeroed pages. - const bool skip_pma_scrubbing = gpu->parent->numa_info.enabled; + const bool skip_pma_scrubbing = gpu->mem_info.numa.enabled; UVM_ASSERT(uvm_pmm_gpu_memory_type_is_user(type) || uvm_pmm_gpu_memory_type_is_kernel(type)); options.flags = UVM_PMA_ALLOCATE_DONT_EVICT; @@ -2145,9 +2180,14 @@ // TODO: Bug 200480500: Batching is currently disabled on P9. Re-enable // when the performance of best-effort allocations is verified. - if (gpu->parent->numa_info.enabled) + if (gpu->mem_info.numa.enabled) flags |= UVM_PMM_ALLOC_FLAGS_DONT_BATCH; + // When the confidential computing feature is enabled, allocate GPU memory + // in the protected region, unless specified otherwise. + if (uvm_conf_computing_mode_enabled(gpu) && memory_type_is_protected(type)) + options.flags |= UVM_PMA_ALLOCATE_PROTECTED_REGION; + if (!gpu->parent->rm_info.isSimulated && !(options.flags & UVM_PMA_ALLOCATE_PINNED) && !(flags & UVM_PMM_ALLOC_FLAGS_DONT_BATCH)) { @@ -2273,7 +2313,8 @@ } // Splits the input chunk into subchunks of the next size down. The chunk state -// can be UVM_PMM_GPU_CHUNK_STATE_TEMP_PINNED or UVM_PMM_GPU_CHUNK_STATE_ALLOCATED. +// can be UVM_PMM_GPU_CHUNK_STATE_TEMP_PINNED or +// UVM_PMM_GPU_CHUNK_STATE_ALLOCATED. // // UVM_PMM_GPU_CHUNK_STATE_TEMP_PINNED: This is a split for allocation. // @@ -2339,6 +2380,7 @@ uvm_assert_mutex_locked(&chunk->va_block->lock); subchunk->va_block = chunk->va_block; subchunk->va_block_page_index = chunk->va_block_page_index + (i * subchunk_size) / PAGE_SIZE; + subchunk->is_referenced = chunk->is_referenced; } } @@ -2354,6 +2396,7 @@ if (chunk->state == UVM_PMM_GPU_CHUNK_STATE_ALLOCATED) { chunk->va_block = NULL; chunk->va_block_page_index = PAGES_PER_UVM_VA_BLOCK; + chunk->is_referenced = false; } else if (chunk->state == UVM_PMM_GPU_CHUNK_STATE_TEMP_PINNED) { // -1 for the parent chunk that is going to transition into the split state. @@ -2398,6 +2441,12 @@ UVM_ASSERT(uvm_global_id_equal(uvm_global_gpu_id_from_index(chunk->gpu_global_index), gpu->global_id)); + // See pmm_squash_memory_type(). + if (!uvm_conf_computing_mode_enabled(gpu)) { + UVM_ASSERT(chunk->type == UVM_PMM_GPU_MEMORY_TYPE_USER || + chunk->type == UVM_PMM_GPU_MEMORY_TYPE_KERNEL); + } + if (chunk->state == UVM_PMM_GPU_CHUNK_STATE_IS_SPLIT) UVM_ASSERT(chunk_size > uvm_chunk_find_first_size(chunk_sizes)); @@ -2511,6 +2560,8 @@ uvm_spin_lock(&pmm->list_lock); + UVM_ASSERT(chunk->state != UVM_PMM_GPU_CHUNK_STATE_ALLOCATED || !chunk->is_referenced); + chunk->inject_split_error = false; // Chunks that are the last allocated child need to trigger a merge and are @@ -2728,6 +2779,11 @@ UVM_ASSERT(IS_ALIGNED(UVM_CHUNK_SIZE_MAX, page_size)); UVM_ASSERT(UVM_CHUNK_SIZE_MAX >= page_size); + // Currently, when the Confidential Computing feature is enabled, the + // entirety of vidmem is protected. + if (uvm_conf_computing_mode_enabled(uvm_pmm_to_gpu(pmm)) && (mem_type != UVM_PMA_GPU_MEMORY_TYPE_PROTECTED)) + return NV_ERR_INVALID_ARGUMENT; + while (num_pages_left_to_evict > 0) { uvm_gpu_root_chunk_t *root_chunk; uvm_page_index_t page_index; @@ -2828,7 +2884,7 @@ } static NV_STATUS uvm_pmm_gpu_pma_evict_pages_wrapper_entry(void *void_pmm, - NvU32 page_size, + NvU64 page_size, NvU64 *pages, NvU32 num_pages_to_evict, NvU64 phys_start, @@ -3254,13 +3310,306 @@ return num_mappings; } +#if UVM_IS_CONFIG_HMM() + +static uvm_pmm_gpu_t *devmem_page_to_pmm(struct page *page) +{ + return container_of(page->pgmap, uvm_pmm_gpu_t, devmem.pagemap); +} + +static uvm_gpu_chunk_t *devmem_page_to_chunk_locked(struct page *page) +{ + uvm_pmm_gpu_t *pmm = devmem_page_to_pmm(page); + NvU64 chunk_addr = ((NvU64)page_to_pfn(page) << PAGE_SHIFT) - pmm->devmem.pagemap.range.start; + size_t index = chunk_addr / UVM_CHUNK_SIZE_MAX; + uvm_gpu_chunk_t *root_chunk; + uvm_gpu_chunk_t *chunk; + uvm_gpu_chunk_t *parent; + uvm_chunk_size_t chunk_size; + + UVM_ASSERT(index < pmm->root_chunks.count); + root_chunk = &pmm->root_chunks.array[index].chunk; + UVM_ASSERT(root_chunk->address == UVM_ALIGN_DOWN(chunk_addr, UVM_CHUNK_SIZE_MAX)); + + // Find the uvm_gpu_chunk_t that corresponds to the device private struct + // page's PFN. The loop is only 0, 1, or 2 iterations. + for (chunk = root_chunk; + uvm_gpu_chunk_get_size(chunk) != page_size(page); + chunk = parent->suballoc->subchunks[index]) { + + parent = chunk; + UVM_ASSERT(parent->state == UVM_PMM_GPU_CHUNK_STATE_IS_SPLIT); + UVM_ASSERT(parent->suballoc); + + chunk_size = uvm_gpu_chunk_get_size(parent->suballoc->subchunks[0]); + index = (size_t)uvm_div_pow2_64(chunk_addr - parent->address, chunk_size); + UVM_ASSERT(index < num_subchunks(parent)); + } + + UVM_ASSERT(chunk->address = chunk_addr); + UVM_ASSERT(chunk->state == UVM_PMM_GPU_CHUNK_STATE_ALLOCATED); + UVM_ASSERT(chunk->is_referenced); + + return chunk; +} + +uvm_gpu_chunk_t *uvm_pmm_devmem_page_to_chunk(struct page *page) +{ + uvm_pmm_gpu_t *pmm = devmem_page_to_pmm(page); + uvm_gpu_chunk_t *chunk; + + UVM_ASSERT(is_device_private_page(page)); + + uvm_spin_lock(&pmm->list_lock); + chunk = devmem_page_to_chunk_locked(page); + uvm_spin_unlock(&pmm->list_lock); + + return chunk; +} + +uvm_gpu_id_t uvm_pmm_devmem_page_to_gpu_id(struct page *page) +{ + uvm_pmm_gpu_t *pmm = devmem_page_to_pmm(page); + uvm_gpu_t *gpu = uvm_pmm_to_gpu(pmm); + + UVM_ASSERT(is_device_private_page(page)); + + return gpu->id; +} + +static void evict_orphan_pages(uvm_pmm_gpu_t *pmm, uvm_gpu_chunk_t *chunk) +{ + NvU32 i; + + UVM_ASSERT(chunk->state == UVM_PMM_GPU_CHUNK_STATE_IS_SPLIT); + UVM_ASSERT(chunk->suballoc); + + for (i = 0; i < num_subchunks(chunk); i++) { + uvm_gpu_chunk_t *subchunk = chunk->suballoc->subchunks[i]; + + uvm_spin_lock(&pmm->list_lock); + + if (subchunk->state == UVM_PMM_GPU_CHUNK_STATE_IS_SPLIT) { + uvm_spin_unlock(&pmm->list_lock); + + evict_orphan_pages(pmm, subchunk); + continue; + } + + if (subchunk->state == UVM_PMM_GPU_CHUNK_STATE_ALLOCATED && subchunk->is_referenced) { + unsigned long pfn = uvm_pmm_gpu_devmem_get_pfn(pmm, subchunk); + + // TODO: Bug 3368756: add support for large GPU pages. + UVM_ASSERT(uvm_gpu_chunk_get_size(subchunk) == PAGE_SIZE); + uvm_spin_unlock(&pmm->list_lock); + + // The above check for subchunk state is racy because the + // chunk may be freed after the lock is dropped. It is + // still safe to proceed in that case because the struct + // page reference will have dropped to zero and cannot + // have been re-allocated as this is only called during + // GPU teardown. Therefore migrate_device_range() will + // simply fail. + uvm_hmm_pmm_gpu_evict_pfn(pfn); + continue; + } + + uvm_spin_unlock(&pmm->list_lock); + } +} + +// Free any orphan pages. +// This should be called as part of removing a GPU: after all work is stopped +// and all va_blocks have been destroyed. There normally won't be any +// device private struct page references left but there can be cases after +// fork() where a child process still holds a reference. This function searches +// for pages that still have a reference and migrates the page to the GPU in +// order to release the reference in the CPU page table. +static void uvm_pmm_gpu_free_orphan_pages(uvm_pmm_gpu_t *pmm) +{ + size_t i; + + if (!pmm->initialized) + return; + + // This is only safe to call during GPU teardown where chunks + // cannot be re-allocated. + UVM_ASSERT(uvm_gpu_retained_count(uvm_pmm_to_gpu(pmm)) == 0); + + // Scan all the root chunks looking for subchunks which are still + // referenced. This is slow, but we only do this when unregistering a GPU + // and is not critical for performance. + for (i = 0; i < pmm->root_chunks.count; i++) { + uvm_gpu_root_chunk_t *root_chunk = &pmm->root_chunks.array[i]; + + root_chunk_lock(pmm, root_chunk); + if (root_chunk->chunk.state == UVM_PMM_GPU_CHUNK_STATE_IS_SPLIT) + evict_orphan_pages(pmm, &root_chunk->chunk); + root_chunk_unlock(pmm, root_chunk); + } +} + +static void devmem_page_free(struct page *page) +{ + uvm_pmm_gpu_t *pmm = devmem_page_to_pmm(page); + uvm_gpu_t *gpu = uvm_pmm_to_gpu(pmm); + uvm_gpu_chunk_t *chunk; + + page->zone_device_data = NULL; + + // We should be calling free_chunk() except that it acquires a mutex and + // we may be in an interrupt context where we can't do that. Instead, + // do a lazy free. Note that we have to use a "normal" spin lock because + // the UVM context is not available. + spin_lock(&pmm->list_lock.lock); + + chunk = devmem_page_to_chunk_locked(page); + UVM_ASSERT(chunk->is_referenced); + chunk->is_referenced = false; + list_add_tail(&chunk->list, &pmm->root_chunks.va_block_lazy_free); + + spin_unlock(&pmm->list_lock.lock); + + nv_kthread_q_schedule_q_item(&gpu->parent->lazy_free_q, + &pmm->root_chunks.va_block_lazy_free_q_item); +} + +// This is called by HMM when the CPU faults on a ZONE_DEVICE private entry. +static vm_fault_t devmem_fault(struct vm_fault *vmf) +{ + uvm_va_space_t *va_space = vmf->page->zone_device_data; + + if (!va_space || va_space->va_space_mm.mm != vmf->vma->vm_mm) + return VM_FAULT_SIGBUS; + + return uvm_va_space_cpu_fault_hmm(va_space, vmf->vma, vmf); +} + +static vm_fault_t devmem_fault_entry(struct vm_fault *vmf) +{ + UVM_ENTRY_RET(devmem_fault(vmf)); +} + +static const struct dev_pagemap_ops uvm_pmm_devmem_ops = +{ + .page_free = devmem_page_free, + .migrate_to_ram = devmem_fault_entry, +}; + +static NV_STATUS devmem_init(uvm_pmm_gpu_t *pmm) +{ + unsigned long size = pmm->root_chunks.count * UVM_CHUNK_SIZE_MAX; + uvm_pmm_gpu_devmem_t *devmem = &pmm->devmem; + struct resource *res; + void *ptr; + NV_STATUS status; + + if (!uvm_hmm_is_enabled_system_wide()) { + devmem->pagemap.owner = NULL; + return NV_OK; + } + + res = request_free_mem_region(&iomem_resource, size, "nvidia-uvm-hmm"); + if (IS_ERR(res)) { + UVM_ERR_PRINT("request_free_mem_region() err %ld\n", PTR_ERR(res)); + status = errno_to_nv_status(PTR_ERR(res)); + goto err; + } + + devmem->pagemap.type = MEMORY_DEVICE_PRIVATE; + devmem->pagemap.range.start = res->start; + devmem->pagemap.range.end = res->end; + devmem->pagemap.nr_range = 1; + devmem->pagemap.ops = &uvm_pmm_devmem_ops; + devmem->pagemap.owner = &g_uvm_global; + + // Numa node ID doesn't matter for ZONE_DEVICE private pages. + ptr = memremap_pages(&devmem->pagemap, NUMA_NO_NODE); + if (IS_ERR(ptr)) { + UVM_ERR_PRINT("memremap_pages() err %ld\n", PTR_ERR(ptr)); + status = errno_to_nv_status(PTR_ERR(ptr)); + goto err_release; + } + + return NV_OK; + +err_release: + release_mem_region(res->start, resource_size(res)); +err: + devmem->pagemap.owner = NULL; + return status; +} + +static void devmem_deinit(uvm_pmm_gpu_t *pmm) +{ + uvm_pmm_gpu_devmem_t *devmem = &pmm->devmem; + + if (!devmem->pagemap.owner) + return; + + memunmap_pages(&devmem->pagemap); + release_mem_region(devmem->pagemap.range.start, range_len(&devmem->pagemap.range)); +} + +unsigned long uvm_pmm_gpu_devmem_get_pfn(uvm_pmm_gpu_t *pmm, uvm_gpu_chunk_t *chunk) +{ + return (pmm->devmem.pagemap.range.start + chunk->address) >> PAGE_SHIFT; +} + +#endif // UVM_IS_CONFIG_HMM() + +#if !UVM_IS_CONFIG_HMM() +static NV_STATUS devmem_init(uvm_pmm_gpu_t *pmm) +{ + return NV_OK; +} + +static void devmem_deinit(uvm_pmm_gpu_t *pmm) +{ +} + +static void uvm_pmm_gpu_free_orphan_pages(uvm_pmm_gpu_t *pmm) +{ +} +#endif // UVM_IS_CONFIG_HMM() + +static void process_lazy_free(uvm_pmm_gpu_t *pmm) +{ + uvm_gpu_chunk_t *chunk; + + uvm_spin_lock(&pmm->list_lock); + + // Note: We can't use list_for_each_safe_entry() because we drop the lock + // in the loop. Instead, just keep removing the first entry until the list + // is empty. + while (!list_empty(&pmm->root_chunks.va_block_lazy_free)) { + chunk = list_first_entry(&pmm->root_chunks.va_block_lazy_free, uvm_gpu_chunk_t, list); + list_del_init(&chunk->list); + uvm_spin_unlock(&pmm->list_lock); + + free_chunk(pmm, chunk); + + uvm_spin_lock(&pmm->list_lock); + } + + uvm_spin_unlock(&pmm->list_lock); +} + +static void process_lazy_free_entry(void *args) +{ + UVM_ENTRY_VOID(process_lazy_free(args)); +} + NV_STATUS uvm_pmm_gpu_init(uvm_pmm_gpu_t *pmm) { uvm_gpu_t *gpu = uvm_pmm_to_gpu(pmm); const uvm_chunk_sizes_mask_t chunk_size_init[][UVM_PMM_GPU_MEMORY_TYPE_COUNT] = { - { gpu->parent->mmu_user_chunk_sizes, gpu->parent->mmu_kernel_chunk_sizes }, - { 0, uvm_mem_kernel_chunk_sizes(gpu)}, + { gpu->parent->mmu_user_chunk_sizes, + gpu->parent->mmu_user_chunk_sizes, + gpu->parent->mmu_kernel_chunk_sizes, + gpu->parent->mmu_kernel_chunk_sizes }, + { 0, 0, uvm_mem_kernel_chunk_sizes(gpu), uvm_mem_kernel_chunk_sizes(gpu)}, }; NV_STATUS status = NV_OK; size_t i, j, k; @@ -3279,6 +3628,8 @@ } INIT_LIST_HEAD(&pmm->root_chunks.va_block_used); INIT_LIST_HEAD(&pmm->root_chunks.va_block_unused); + INIT_LIST_HEAD(&pmm->root_chunks.va_block_lazy_free); + nv_kthread_q_item_init(&pmm->root_chunks.va_block_lazy_free_q_item, process_lazy_free_entry, pmm); uvm_mutex_init(&pmm->lock, UVM_LOCK_ORDER_PMM); uvm_init_rwsem(&pmm->pma_lock, UVM_LOCK_ORDER_PMM_PMA); @@ -3303,13 +3654,13 @@ goto cleanup; // Assert that max physical address of the GPU is not unreasonably big for - // creating the flat array of root chunks. Currently the worst case is a - // Maxwell GPU that has 0.5 GB of its physical memory mapped at the 64GB - // physical address. 256GB should provide reasonable amount of - // future-proofing and results in 128K chunks which is still manageable. - UVM_ASSERT_MSG(gpu->mem_info.max_allocatable_address < 256ull * 1024 * 1024 * 1024, - "Max physical address over 256GB: %llu\n", - gpu->mem_info.max_allocatable_address); + // creating the flat array of root chunks. 256GB should provide a reasonable + // amount of future-proofing and results in 128K chunks which is still + // manageable. + UVM_ASSERT_MSG(gpu->mem_info.max_allocatable_address < UVM_GPU_MAX_PHYS_MEM, + "Max physical address 0x%llx exceeds limit of 0x%llx\n", + gpu->mem_info.max_allocatable_address, + UVM_GPU_MAX_PHYS_MEM); // Align up the size to have a root chunk for the last part of the FB. PMM // won't be able to allocate it, if it doesn't fit a whole root chunk, but @@ -3354,6 +3705,10 @@ } } + status = devmem_init(pmm); + if (status != NV_OK) + goto cleanup; + return NV_OK; cleanup: uvm_pmm_gpu_deinit(pmm); @@ -3387,9 +3742,13 @@ if (!pmm->initialized) return; + gpu = uvm_pmm_to_gpu(pmm); + + uvm_pmm_gpu_free_orphan_pages(pmm); + nv_kthread_q_flush(&gpu->parent->lazy_free_q); + UVM_ASSERT(list_empty(&pmm->root_chunks.va_block_lazy_free)); release_free_root_chunks(pmm); - gpu = uvm_pmm_to_gpu(pmm); if (gpu->mem_info.size != 0 && gpu_supports_pma_eviction(gpu)) nvUvmInterfacePmaUnregisterEvictionCallbacks(pmm->pma); @@ -3425,6 +3784,8 @@ deinit_caches(pmm); + devmem_deinit(pmm); + pmm->initialized = false; } @@ -3459,18 +3820,11 @@ // For virtual mode, look up and retain the block first so that eviction can // be started without the VA space lock held. if (params->eviction_mode == UvmTestEvictModeVirtual) { - uvm_va_block_context_t *block_context; - - block_context = uvm_va_block_context_alloc(mm); - if (!block_context) { - status = NV_ERR_NO_MEMORY; - uvm_va_space_up_read(va_space); - uvm_va_space_mm_release_unlock(va_space, mm); - goto out; - } + if (mm) + status = uvm_va_block_find_create(va_space, params->address, NULL, &block); + else + status = uvm_va_block_find_create_managed(va_space, params->address, &block); - status = uvm_va_block_find_create(va_space, params->address, block_context, &block); - uvm_va_block_context_free(block_context); if (status != NV_OK) { uvm_va_space_up_read(va_space); uvm_va_space_mm_or_current_release_unlock(va_space, mm); diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/kernel-open/nvidia-uvm/uvm_pmm_gpu.h nvidia-open-gpu-kernel-modules-535.161.08/kernel-open/nvidia-uvm/uvm_pmm_gpu.h --- nvidia-open-gpu-kernel-modules-525.147.05/kernel-open/nvidia-uvm/uvm_pmm_gpu.h 2023-10-25 20:33:40.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/kernel-open/nvidia-uvm/uvm_pmm_gpu.h 2024-03-05 22:26:01.000000000 +0000 @@ -59,6 +59,9 @@ #include "uvm_linux.h" #include "uvm_types.h" #include "nv_uvm_types.h" +#if UVM_IS_CONFIG_HMM() +#include +#endif typedef enum { @@ -94,9 +97,18 @@ { // Memory type for backing user pages. On Pascal+ it can be evicted. UVM_PMM_GPU_MEMORY_TYPE_USER, + // When the Confidential Computing feature is enabled, the protected flavor + // allocates memory out of the VPR region. When it's disabled, all flavors + // have no effects and are equivalent to the base type. + UVM_PMM_GPU_MEMORY_TYPE_USER_PROTECTED = UVM_PMM_GPU_MEMORY_TYPE_USER, + UVM_PMM_GPU_MEMORY_TYPE_USER_UNPROTECTED, // Memory type for internal UVM allocations. It cannot be evicted. UVM_PMM_GPU_MEMORY_TYPE_KERNEL, + // See user types for the behavior description when the Confidential + // Computing feature is ON or OFF. + UVM_PMM_GPU_MEMORY_TYPE_KERNEL_PROTECTED = UVM_PMM_GPU_MEMORY_TYPE_KERNEL, + UVM_PMM_GPU_MEMORY_TYPE_KERNEL_UNPROTECTED, // Number of types - MUST BE LAST. UVM_PMM_GPU_MEMORY_TYPE_COUNT @@ -195,7 +207,26 @@ typedef struct uvm_pmm_gpu_chunk_suballoc_struct uvm_pmm_gpu_chunk_suballoc_t; -typedef struct uvm_gpu_chunk_struct uvm_gpu_chunk_t; +#if UVM_IS_CONFIG_HMM() + +typedef struct uvm_pmm_gpu_struct uvm_pmm_gpu_t; + +typedef struct +{ + struct dev_pagemap pagemap; +} uvm_pmm_gpu_devmem_t; + +// Return the GPU chunk for a given device private struct page. +uvm_gpu_chunk_t *uvm_pmm_devmem_page_to_chunk(struct page *page); + +// Return the GPU id for a given device private struct page. +uvm_gpu_id_t uvm_pmm_devmem_page_to_gpu_id(struct page *page); + +// Return the PFN of the device private struct page for the given GPU chunk. +unsigned long uvm_pmm_gpu_devmem_get_pfn(uvm_pmm_gpu_t *pmm, uvm_gpu_chunk_t *chunk); + +#endif + struct uvm_gpu_chunk_struct { // Physical address of GPU chunk. This may be removed to save memory @@ -208,15 +239,15 @@ // We use +1 in the order_base_2 calls appropriately to avoid compiler // warnings due to the bitfields being too narrow for the values of // their types. - uvm_pmm_gpu_memory_type_t type : order_base_2(UVM_PMM_GPU_MEMORY_TYPE_COUNT + 1); + uvm_pmm_gpu_memory_type_t type : order_base_2(UVM_PMM_GPU_MEMORY_TYPE_COUNT + 1); // The eviction flag is internal and used only for root chunks. It's // set by the eviction path once a chunk is chosen for eviction in // chunk_start_eviction(). Also see the (root_)chunk_is_in_eviction() // helpers. - bool in_eviction : 1; + bool in_eviction : 1; - bool inject_split_error : 1; + bool inject_split_error : 1; // This flag is initalized when allocating a new root chunk from PMA. // It is set to true, if PMA already scrubbed the chunk. The flag is @@ -224,19 +255,23 @@ // the caller is not required to clear it before freeing the chunk. The // VA block chunk population code can query it to skip zeroing the // chunk. - bool is_zero : 1; + bool is_zero : 1; + + // This flag indicates an allocated chunk is referenced by a device + // private struct page PTE and therefore expects a page_free() callback. + bool is_referenced : 1; - uvm_pmm_gpu_chunk_state_t state : order_base_2(UVM_PMM_GPU_CHUNK_STATE_COUNT + 1); + uvm_pmm_gpu_chunk_state_t state : order_base_2(UVM_PMM_GPU_CHUNK_STATE_COUNT + 1); - size_t log2_size : order_base_2(UVM_CHUNK_SIZE_MASK_SIZE); + size_t log2_size : order_base_2(UVM_CHUNK_SIZE_MASK_SIZE); // Start page index within va_block - uvm_page_index_t va_block_page_index : order_base_2(PAGES_PER_UVM_VA_BLOCK + 1); + uvm_page_index_t va_block_page_index : order_base_2(PAGES_PER_UVM_VA_BLOCK + 1); // This allows determining what PMM owns the chunk. Users of this field // must only use it if the owning GPU is retained. // TODO: Bug 2008200: Enforce single PMM instance per GPU - NvU32 gpu_global_index : order_base_2(UVM_GLOBAL_ID_MAX_PROCESSORS); + NvU32 gpu_global_index : order_base_2(UVM_GLOBAL_ID_MAX_PROCESSORS); }; // List entry. @@ -309,7 +344,7 @@ atomic64_t map_count; } uvm_gpu_root_chunk_indirect_peer_t; -typedef struct +typedef struct uvm_pmm_gpu_struct { // Sizes of the MMU uvm_chunk_sizes_mask_t chunk_sizes[UVM_PMM_GPU_MEMORY_TYPE_COUNT]; @@ -348,9 +383,19 @@ // List of root chunks used by VA blocks struct list_head va_block_used; + // List of chunks needing to be lazily freed and a queue for processing + // the list. TODO: Bug 3881835: revisit whether to use nv_kthread_q_t + // or workqueue. + struct list_head va_block_lazy_free; + nv_kthread_q_item_t va_block_lazy_free_q_item; + uvm_gpu_root_chunk_indirect_peer_t indirect_peer[UVM_ID_MAX_GPUS]; } root_chunks; +#if UVM_IS_CONFIG_HMM() + uvm_pmm_gpu_devmem_t devmem; +#endif + // Lock protecting PMA allocation, freeing and eviction uvm_rw_semaphore_t pma_lock; @@ -410,18 +455,23 @@ // Allocates num_chunks chunks of size chunk_size in caller-supplied array (chunks). // // Returned chunks are in the TEMP_PINNED state, requiring a call to either -// uvm_pmm_gpu_unpin_temp or uvm_pmm_gpu_free. If a tracker is passed in, all +// uvm_pmm_gpu_unpin_allocated, uvm_pmm_gpu_unpin_referenced, or +// uvm_pmm_gpu_free. If a tracker is passed in, all // the pending operations on the allocated chunks will be added to it // guaranteeing that all the entries come from the same GPU as the PMM. // Otherwise, when tracker is NULL, all the pending operations will be // synchronized before returning to the caller. // // Each of the allocated chunks list nodes (uvm_gpu_chunk_t::list) can be used -// by the caller until the chunk is unpinned (uvm_pmm_gpu_unpin_temp) or freed -// (uvm_pmm_gpu_free). If used, the list node has to be returned to a valid -// state before calling either of the APIs. +// by the caller until the chunk is unpinned (uvm_pmm_gpu_unpin_allocated, +// uvm_pmm_gpu_unpin_referenced) or freed (uvm_pmm_gpu_free). If used, the list +// node has to be returned to a valid state before calling either of the APIs. // // In case of an error, the chunks array is guaranteed to be cleared. +// +// If the memory returned by the PMM allocator cannot be physically addressed, +// the MMU interface provides user chunk mapping and unmapping functions +// (uvm_mmu_chunk_map/unmap) that enable virtual addressing. NV_STATUS uvm_pmm_gpu_alloc(uvm_pmm_gpu_t *pmm, size_t num_chunks, uvm_chunk_size_t chunk_size, @@ -434,21 +484,26 @@ // // Internally calls uvm_pmm_gpu_alloc() and sets the state of all chunks to // allocated on success. -NV_STATUS uvm_pmm_gpu_alloc_kernel(uvm_pmm_gpu_t *pmm, - size_t num_chunks, - uvm_chunk_size_t chunk_size, - uvm_pmm_alloc_flags_t flags, - uvm_gpu_chunk_t **chunks, - uvm_tracker_t *out_tracker); +// +// If Confidential Computing is enabled, this helper allocates protected kernel +// memory. +static NV_STATUS uvm_pmm_gpu_alloc_kernel(uvm_pmm_gpu_t *pmm, + size_t num_chunks, + uvm_chunk_size_t chunk_size, + uvm_pmm_alloc_flags_t flags, + uvm_gpu_chunk_t **chunks, + uvm_tracker_t *out_tracker) +{ + return uvm_pmm_gpu_alloc(pmm, num_chunks, chunk_size, UVM_PMM_GPU_MEMORY_TYPE_KERNEL, flags, chunks, out_tracker); +} // Helper for allocating user memory // // Simple wrapper that just uses UVM_PMM_GPU_MEMORY_TYPE_USER for the memory // type. // -// If the memory returned by the PMM allocator cannot be physically addressed, -// the MMU interface provides user chunk mapping and unmapping functions -// (uvm_mmu_chunk_map/unmap) that enable virtual addressing. +// If Confidential Computing is enabled, this helper allocates protected user +// memory. static NV_STATUS uvm_pmm_gpu_alloc_user(uvm_pmm_gpu_t *pmm, size_t num_chunks, uvm_chunk_size_t chunk_size, @@ -459,10 +514,17 @@ return uvm_pmm_gpu_alloc(pmm, num_chunks, chunk_size, UVM_PMM_GPU_MEMORY_TYPE_USER, flags, chunks, out_tracker); } -// Unpin a temporarily pinned chunk and set its reverse map to a VA block +// Unpin a temporarily pinned chunk, set its reverse map to a VA block, and +// mark it as allocated. +// +// Can only be used on user memory. +void uvm_pmm_gpu_unpin_allocated(uvm_pmm_gpu_t *pmm, uvm_gpu_chunk_t *chunk, uvm_va_block_t *va_block); + +// Unpin a temporarily pinned chunk, set its reverse map to a VA block, and +// mark it as referenced. // // Can only be used on user memory. -void uvm_pmm_gpu_unpin_temp(uvm_pmm_gpu_t *pmm, uvm_gpu_chunk_t *chunk, uvm_va_block_t *va_block); +void uvm_pmm_gpu_unpin_referenced(uvm_pmm_gpu_t *pmm, uvm_gpu_chunk_t *chunk, uvm_va_block_t *va_block); // Frees the chunk. This also unpins the chunk if it is temporarily pinned. // diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/kernel-open/nvidia-uvm/uvm_pmm_sysmem.c nvidia-open-gpu-kernel-modules-535.161.08/kernel-open/nvidia-uvm/uvm_pmm_sysmem.c --- nvidia-open-gpu-kernel-modules-525.147.05/kernel-open/nvidia-uvm/uvm_pmm_sysmem.c 2023-10-25 20:33:40.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/kernel-open/nvidia-uvm/uvm_pmm_sysmem.c 2024-03-05 22:26:00.000000000 +0000 @@ -40,6 +40,15 @@ if (!g_reverse_page_map_cache) return NV_ERR_NO_MEMORY; + // Ensure that only supported CPU chunk sizes are enabled. + uvm_cpu_chunk_allocation_sizes &= UVM_CPU_CHUNK_SIZES; + if (!uvm_cpu_chunk_allocation_sizes || !(uvm_cpu_chunk_allocation_sizes & PAGE_SIZE)) { + pr_info("Invalid value for uvm_cpu_chunk_allocation_sizes = 0x%x, using 0x%lx instead\n", + uvm_cpu_chunk_allocation_sizes, + UVM_CPU_CHUNK_SIZES); + uvm_cpu_chunk_allocation_sizes = UVM_CPU_CHUNK_SIZES; + } + return NV_OK; } @@ -430,1031 +439,669 @@ static void uvm_cpu_chunk_set_size(uvm_cpu_chunk_t *chunk, uvm_chunk_size_t size) { -#if !UVM_CPU_CHUNK_SIZE_IS_PAGE_SIZE() chunk->log2_size = ilog2(size); -#endif } uvm_chunk_size_t uvm_cpu_chunk_get_size(uvm_cpu_chunk_t *chunk) { -#if UVM_CPU_CHUNK_SIZE_IS_PAGE_SIZE() - return PAGE_SIZE; -#else return ((uvm_chunk_size_t)1) << chunk->log2_size; -#endif } -#if UVM_CPU_CHUNK_SIZE_IS_PAGE_SIZE() -struct page *uvm_cpu_chunk_get_cpu_page(uvm_va_block_t *va_block, uvm_cpu_chunk_t *chunk, uvm_page_index_t page_index) +static NvU32 compute_gpu_mappings_entry_index(uvm_processor_mask_t *dma_addrs_mask, uvm_gpu_id_t id) { - UVM_ASSERT(chunk); - return chunk; -} + uvm_processor_mask_t subset_mask; -void uvm_cpu_chunk_put(uvm_cpu_chunk_t *chunk) -{ - UVM_ASSERT(chunk); - put_page(chunk); + // Compute the array index for the given GPU ID by masking off all bits + // above and including the id and then counting the number of bits + // remaining. + uvm_processor_mask_zero(&subset_mask); + bitmap_set(subset_mask.bitmap, UVM_ID_GPU0_VALUE, uvm_id_gpu_index(id)); + uvm_processor_mask_and(&subset_mask, dma_addrs_mask, &subset_mask); + + return uvm_processor_mask_get_gpu_count(&subset_mask); } -NV_STATUS uvm_cpu_chunk_gpu_mapping_alloc(uvm_va_block_t *va_block, uvm_gpu_id_t id) +static void cpu_chunk_release(nv_kref_t *kref) { - uvm_va_block_gpu_state_t *gpu_state = uvm_va_block_gpu_state_get(va_block, id); - size_t num_pages = uvm_va_block_num_cpu_pages(va_block); + uvm_cpu_chunk_t *chunk = container_of(kref, uvm_cpu_chunk_t, refcount); + uvm_processor_mask_t *mapping_mask; + uvm_processor_id_t id; + uvm_cpu_physical_chunk_t *phys_chunk = NULL; + uvm_cpu_logical_chunk_t *logical_chunk = NULL; + + if (uvm_cpu_chunk_is_physical(chunk)) { + phys_chunk = uvm_cpu_chunk_to_physical(chunk); + uvm_assert_mutex_unlocked(&phys_chunk->lock); + mapping_mask = &phys_chunk->gpu_mappings.dma_addrs_mask; + } + else { + logical_chunk = uvm_cpu_chunk_to_logical(chunk); + mapping_mask = &logical_chunk->mapped_gpus; + } - UVM_ASSERT(gpu_state); - gpu_state->cpu_chunks_dma_addrs = uvm_kvmalloc_zero(num_pages * sizeof(gpu_state->cpu_chunks_dma_addrs[0])); - if (!gpu_state->cpu_chunks_dma_addrs) - return NV_ERR_NO_MEMORY; + for_each_id_in_mask(id, mapping_mask) { + uvm_parent_gpu_t *parent_gpu = uvm_parent_gpu_get(id); + uvm_cpu_chunk_unmap_gpu_phys(chunk, parent_gpu); + } - return NV_OK; -} + if (uvm_cpu_chunk_is_physical(chunk)) { + if (phys_chunk->gpu_mappings.max_entries > 1) + uvm_kvfree(phys_chunk->gpu_mappings.dynamic_entries); -void uvm_cpu_chunk_gpu_mapping_split(uvm_va_block_t *existing, uvm_va_block_t *new, uvm_gpu_id_t id) -{ - uvm_va_block_gpu_state_t *existing_state = uvm_va_block_gpu_state_get(existing, id); - uvm_va_block_gpu_state_t *new_state = uvm_va_block_gpu_state_get(new, id); - size_t new_pages = uvm_va_block_num_cpu_pages(new); + if (uvm_cpu_chunk_get_size(chunk) > PAGE_SIZE && + !bitmap_empty(phys_chunk->dirty_bitmap, uvm_cpu_chunk_num_pages(chunk))) + SetPageDirty(phys_chunk->common.page); - memcpy(&new_state->cpu_chunks_dma_addrs[0], - &existing_state->cpu_chunks_dma_addrs[uvm_va_block_num_cpu_pages(existing) - new_pages], - new_pages * sizeof(new_state->cpu_chunks_dma_addrs[0])); -} + uvm_kvfree(phys_chunk->dirty_bitmap); -void uvm_cpu_chunk_gpu_mapping_free(uvm_va_block_t *va_block, uvm_gpu_id_t id) -{ - uvm_va_block_gpu_state_t *gpu_state = uvm_va_block_gpu_state_get(va_block, id); + if (chunk->type != UVM_CPU_CHUNK_TYPE_HMM) + put_page(phys_chunk->common.page); + } + else { + uvm_cpu_chunk_free(logical_chunk->parent); + } - if (gpu_state) - uvm_kvfree(gpu_state->cpu_chunks_dma_addrs); + uvm_kvfree(chunk); } -NV_STATUS uvm_cpu_chunk_set_gpu_mapping_addr(uvm_va_block_t *va_block, - uvm_page_index_t page_index, - uvm_cpu_chunk_t *chunk, - uvm_gpu_id_t id, - NvU64 dma_addr) +static void uvm_cpu_chunk_get(uvm_cpu_chunk_t *chunk) { - uvm_va_block_gpu_state_t *gpu_state = uvm_va_block_gpu_state_get(va_block, id); - - gpu_state->cpu_chunks_dma_addrs[page_index] = dma_addr; - return NV_OK; + UVM_ASSERT(chunk); + nv_kref_get(&chunk->refcount); } -NvU64 uvm_cpu_chunk_get_gpu_mapping_addr(uvm_va_block_t *va_block, - uvm_page_index_t page_index, - uvm_cpu_chunk_t *chunk, - uvm_gpu_id_t id) +void uvm_cpu_chunk_free(uvm_cpu_chunk_t *chunk) { - uvm_va_block_gpu_state_t *gpu_state = uvm_va_block_gpu_state_get(va_block, id); + if (!chunk) + return; - return gpu_state->cpu_chunks_dma_addrs[page_index]; + nv_kref_put(&chunk->refcount, cpu_chunk_release); } -NV_STATUS uvm_cpu_chunk_insert_in_block(uvm_va_block_t *va_block, uvm_cpu_chunk_t *chunk, uvm_page_index_t page_index) +static uvm_cpu_physical_chunk_t *get_physical_parent(uvm_cpu_chunk_t *chunk) { - if (!va_block->cpu.chunks) { - va_block->cpu.chunks = (unsigned long)uvm_kvmalloc_zero(uvm_va_block_num_cpu_pages(va_block) * - sizeof(uvm_cpu_chunk_t *)); - if (!va_block->cpu.chunks) - return NV_ERR_NO_MEMORY; - } + UVM_ASSERT(chunk); + UVM_ASSERT(chunk->page); - UVM_ASSERT(!uvm_page_mask_test(&va_block->cpu.allocated, page_index)); - UVM_ASSERT(((uvm_cpu_chunk_t **)va_block->cpu.chunks)[page_index] == NULL); - ((uvm_cpu_chunk_t **)va_block->cpu.chunks)[page_index] = chunk; - uvm_page_mask_set(&va_block->cpu.allocated, page_index); - return NV_OK; -} + while (!uvm_cpu_chunk_is_physical(chunk)) + chunk = uvm_cpu_chunk_to_logical(chunk)->parent; -void uvm_cpu_chunk_remove_from_block(uvm_va_block_t *va_block, uvm_cpu_chunk_t *chunk, uvm_page_index_t page_index) -{ - UVM_ASSERT(uvm_page_mask_test(&va_block->cpu.allocated, page_index)); - UVM_ASSERT(((uvm_cpu_chunk_t **)va_block->cpu.chunks)[page_index] != NULL); - ((uvm_cpu_chunk_t **)va_block->cpu.chunks)[page_index] = NULL; - uvm_page_mask_clear(&va_block->cpu.allocated, page_index); + return uvm_cpu_chunk_to_physical(chunk); } -uvm_cpu_chunk_t *uvm_cpu_chunk_get_chunk_for_page(uvm_va_block_t *va_block, uvm_page_index_t page_index) +static uvm_page_index_t cpu_chunk_get_phys_index(uvm_cpu_logical_chunk_t *chunk) { - UVM_ASSERT(page_index < uvm_va_block_num_cpu_pages(va_block)); - if (!uvm_page_mask_test(&va_block->cpu.allocated, page_index)) - return NULL; + uvm_cpu_physical_chunk_t *phys_chunk = get_physical_parent(&chunk->common); - return ((uvm_cpu_chunk_t **)va_block->cpu.chunks)[page_index]; + UVM_ASSERT(phys_chunk->common.page); + return (uvm_page_index_t)(chunk->common.page - phys_chunk->common.page); } -NV_STATUS uvm_cpu_chunk_alloc(uvm_va_block_t *va_block, - uvm_page_index_t page_index, - struct mm_struct *mm, - uvm_cpu_chunk_t **new_chunk) +static uvm_cpu_phys_mapping_t *chunk_phys_mapping_alloc(uvm_cpu_physical_chunk_t *chunk, uvm_gpu_id_t id) { - uvm_cpu_chunk_t *chunk = NULL; - gfp_t alloc_flags; - NV_STATUS status; + NvU32 num_active_entries = uvm_processor_mask_get_gpu_count(&chunk->gpu_mappings.dma_addrs_mask); + uvm_cpu_phys_mapping_t *new_entries; + NvU32 array_index; - UVM_ASSERT(!uvm_page_mask_test(&va_block->cpu.allocated, page_index)); - UVM_ASSERT(new_chunk); + uvm_assert_mutex_locked(&chunk->lock); - alloc_flags = (mm ? NV_UVM_GFP_FLAGS_ACCOUNT : NV_UVM_GFP_FLAGS) | GFP_HIGHUSER; + if (chunk->gpu_mappings.max_entries == 1 && num_active_entries == 0) + return &chunk->gpu_mappings.static_entry; - if (!uvm_va_block_page_resident_processors_count(va_block, page_index)) - alloc_flags |= __GFP_ZERO; + if (num_active_entries == chunk->gpu_mappings.max_entries) { + NvU32 num_new_entries = chunk->gpu_mappings.max_entries * 2; - chunk = alloc_pages(alloc_flags, 0); - if (!chunk) - return NV_ERR_NO_MEMORY; + if (chunk->gpu_mappings.max_entries == 1) { + new_entries = uvm_kvmalloc(sizeof(*new_entries) * num_new_entries); + if (new_entries) + new_entries[0] = chunk->gpu_mappings.static_entry; + } + else { + new_entries = uvm_kvrealloc(chunk->gpu_mappings.dynamic_entries, + sizeof(*new_entries) * num_new_entries); + } - if (alloc_flags & __GFP_ZERO) - SetPageDirty(chunk); + if (!new_entries) + return NULL; - status = uvm_cpu_chunk_insert_in_block(va_block, chunk, page_index); - if (status != NV_OK) { - uvm_cpu_chunk_put(chunk); - return status; + chunk->gpu_mappings.max_entries = num_new_entries; + chunk->gpu_mappings.dynamic_entries = new_entries; } - *new_chunk = chunk; - return NV_OK; -} - -#else - -struct page *uvm_cpu_chunk_get_cpu_page(uvm_va_block_t *va_block, uvm_cpu_chunk_t *chunk, uvm_page_index_t page_index) -{ - uvm_va_block_region_t chunk_region; - - UVM_ASSERT(chunk); - UVM_ASSERT(chunk->page); - chunk_region = uvm_va_block_chunk_region(va_block, uvm_cpu_chunk_get_size(chunk), page_index); - return chunk->page + (page_index - chunk_region.first); -} + array_index = compute_gpu_mappings_entry_index(&chunk->gpu_mappings.dma_addrs_mask, id); + while (num_active_entries > array_index) { + chunk->gpu_mappings.dynamic_entries[num_active_entries] = + chunk->gpu_mappings.dynamic_entries[num_active_entries - 1]; + num_active_entries--; + } -static NvU64 uvm_cpu_chunk_get_virt_addr(uvm_va_block_t *va_block, uvm_cpu_chunk_t *chunk) -{ - UVM_ASSERT(chunk); - UVM_ASSERT(chunk->region.first < chunk->region.outer); - return uvm_va_block_cpu_page_address(va_block, chunk->region.first); + return &chunk->gpu_mappings.dynamic_entries[array_index]; } -static void cpu_chunk_release(nv_kref_t *kref) +static uvm_cpu_phys_mapping_t *chunk_phys_mapping_get(uvm_cpu_physical_chunk_t *chunk, uvm_gpu_id_t id) { - uvm_cpu_chunk_t *chunk = container_of(kref, uvm_cpu_chunk_t, refcount); - uvm_cpu_chunk_t *parent = chunk->parent; - - if (uvm_processor_mask_get_gpu_count(&chunk->gpu_mappings.dma_addrs_mask) > 1) - uvm_kvfree(chunk->gpu_mappings.dynamic_entries); - - if (!parent) { - uvm_assert_spinlock_unlocked(&chunk->lock); - uvm_kvfree(chunk->dirty_bitmap); - put_page(chunk->page); - } - else { - uvm_cpu_chunk_put(parent); + uvm_assert_mutex_locked(&chunk->lock); + if (uvm_processor_mask_test(&chunk->gpu_mappings.dma_addrs_mask, id)) { + if (chunk->gpu_mappings.max_entries == 1) { + return &chunk->gpu_mappings.static_entry; + } + else { + NvU32 array_index = compute_gpu_mappings_entry_index(&chunk->gpu_mappings.dma_addrs_mask, id); + return &chunk->gpu_mappings.dynamic_entries[array_index]; + } } - uvm_kvfree(chunk); + return NULL; } -void uvm_cpu_chunk_get(uvm_cpu_chunk_t *chunk) +static void chunk_inc_gpu_mapping(uvm_cpu_physical_chunk_t *chunk, uvm_gpu_id_t id) { - UVM_ASSERT(chunk); - nv_kref_get(&chunk->refcount); + uvm_cpu_phys_mapping_t *mapping; + + uvm_assert_mutex_locked(&chunk->lock); + mapping = chunk_phys_mapping_get(chunk, id); + UVM_ASSERT(mapping); + mapping->map_count++; } -void uvm_cpu_chunk_put(uvm_cpu_chunk_t *chunk) +static void chunk_dec_gpu_mapping(uvm_cpu_physical_chunk_t *chunk, uvm_gpu_id_t id) { - UVM_ASSERT(chunk); + uvm_cpu_phys_mapping_t *mapping; - nv_kref_put(&chunk->refcount, cpu_chunk_release); -} + uvm_assert_mutex_locked(&chunk->lock); + mapping = chunk_phys_mapping_get(chunk, id); + UVM_ASSERT(mapping); + UVM_ASSERT(mapping->dma_addr && mapping->map_count); + mapping->map_count--; + if (mapping->map_count == 0) { + uvm_parent_gpu_t *parent_gpu = uvm_parent_gpu_get(id); -NV_STATUS uvm_cpu_chunk_gpu_mapping_alloc(uvm_va_block_t *va_block, uvm_gpu_id_t id) -{ - return NV_OK; -} + uvm_gpu_unmap_cpu_pages(parent_gpu, mapping->dma_addr, uvm_cpu_chunk_get_size(&chunk->common)); + mapping->dma_addr = 0; + if (chunk->gpu_mappings.max_entries > 1) { + NvU32 num_active_entries = uvm_processor_mask_get_gpu_count(&chunk->gpu_mappings.dma_addrs_mask); + NvU32 array_index = compute_gpu_mappings_entry_index(&chunk->gpu_mappings.dma_addrs_mask, id); -void uvm_cpu_chunk_gpu_mapping_split(uvm_va_block_t *existing, uvm_va_block_t *va_block, uvm_gpu_id_t id) -{ - return; -} + // Shift any GPU mappings above this one down in the mappings array. + for (; array_index < num_active_entries - 1; array_index++) + chunk->gpu_mappings.dynamic_entries[array_index] = chunk->gpu_mappings.dynamic_entries[array_index+1]; + } -void uvm_cpu_chunk_gpu_mapping_free(uvm_va_block_t *va_block, uvm_gpu_id_t id) -{ - return; + uvm_processor_mask_clear(&chunk->gpu_mappings.dma_addrs_mask, id); + } } -static NvU32 compute_gpu_mappings_entry_index(uvm_processor_mask_t dma_addrs_mask, uvm_gpu_id_t id) +NvU64 uvm_cpu_chunk_get_gpu_phys_addr(uvm_cpu_chunk_t *chunk, uvm_parent_gpu_t *parent_gpu) { - uvm_processor_mask_t subset_mask; + uvm_cpu_physical_chunk_t *phys_chunk = get_physical_parent(chunk); + uvm_cpu_phys_mapping_t *mapping; + uvm_page_index_t parent_offset = 0; + NvU64 dma_addr = 0; - // Compute the array index for the given GPU ID by masking off all bits - // above the id and then counting the number of bits remaining. - uvm_processor_mask_zero(&subset_mask); - bitmap_set(subset_mask.bitmap, 0, uvm_id_value(id) + 1); - uvm_processor_mask_and(&subset_mask, &dma_addrs_mask, &subset_mask); + if (uvm_cpu_chunk_is_logical(chunk)) { + uvm_cpu_logical_chunk_t *logical_chunk = uvm_cpu_chunk_to_logical(chunk); - if (uvm_processor_mask_empty(&subset_mask)) - return 0; + if (!uvm_processor_mask_test(&logical_chunk->mapped_gpus, parent_gpu->id)) + return 0; - return uvm_processor_mask_get_gpu_count(&subset_mask) - 1; -} - -NV_STATUS uvm_cpu_chunk_set_gpu_mapping_addr(uvm_va_block_t *va_block, - uvm_page_index_t page_index, - uvm_cpu_chunk_t *chunk, - uvm_gpu_id_t id, - NvU64 dma_addr) -{ - NvU32 num_existing_entries = uvm_processor_mask_get_gpu_count(&chunk->gpu_mappings.dma_addrs_mask); - NvU32 num_new_entries; - NvU32 array_index; - NvU64 *new_entries; - - if (uvm_processor_mask_empty(&chunk->gpu_mappings.dma_addrs_mask)) { - uvm_processor_mask_set(&chunk->gpu_mappings.dma_addrs_mask, id); - chunk->gpu_mappings.static_entry = dma_addr; - return NV_OK; + parent_offset = cpu_chunk_get_phys_index(logical_chunk); } - if (uvm_processor_mask_test(&chunk->gpu_mappings.dma_addrs_mask, id)) { - if (num_existing_entries == 1) { - chunk->gpu_mappings.static_entry = dma_addr; - } - else { - array_index = compute_gpu_mappings_entry_index(chunk->gpu_mappings.dma_addrs_mask, id); - chunk->gpu_mappings.dynamic_entries[array_index] = dma_addr; - } - return NV_OK; - } + uvm_mutex_lock(&phys_chunk->lock); + mapping = chunk_phys_mapping_get(phys_chunk, parent_gpu->id); + if (mapping) + dma_addr = mapping->dma_addr + (parent_offset * PAGE_SIZE); - num_new_entries = num_existing_entries + 1; - if (num_existing_entries == 1) { - new_entries = uvm_kvmalloc(sizeof(*new_entries) * num_new_entries); + uvm_mutex_unlock(&phys_chunk->lock); + return dma_addr; +} - if (new_entries) { - uvm_processor_id_t first = uvm_processor_mask_find_first_id(&chunk->gpu_mappings.dma_addrs_mask); +// Create a DMA mapping for the chunk on the given parent GPU. This will map the +// entire parent physical chunk on the GPU. +// +// Returns NV_OK on success. On error, any of the errors returned by +// uvm_gpu_map_cpu_pages() can be returned. In the case that the DMA mapping +// structure could not be allocated, NV_ERR_NO_MEMORY is returned. +static NV_STATUS cpu_chunk_map_gpu_phys(uvm_cpu_chunk_t *chunk, uvm_parent_gpu_t *parent_gpu) +{ + uvm_cpu_physical_chunk_t *phys_chunk; + uvm_cpu_logical_chunk_t *logical_chunk = NULL; + NV_STATUS status = NV_OK; - if (uvm_id_value(first) < uvm_id_value(id)) - new_entries[0] = chunk->gpu_mappings.static_entry; - else - new_entries[1] = chunk->gpu_mappings.static_entry; + if (uvm_cpu_chunk_is_logical(chunk)) { + logical_chunk = uvm_cpu_chunk_to_logical(chunk); + if (uvm_processor_mask_test(&logical_chunk->mapped_gpus, parent_gpu->id)) + return status; + } + + phys_chunk = get_physical_parent(chunk); + uvm_mutex_lock(&phys_chunk->lock); + + if (!uvm_processor_mask_test(&phys_chunk->gpu_mappings.dma_addrs_mask, parent_gpu->id)) { + uvm_chunk_size_t chunk_size = uvm_cpu_chunk_get_size(&phys_chunk->common); + uvm_cpu_phys_mapping_t *mapping; + NvU64 dma_addr; + + status = uvm_gpu_map_cpu_pages(parent_gpu, phys_chunk->common.page, chunk_size, &dma_addr); + if (status != NV_OK) + goto done; + + mapping = chunk_phys_mapping_alloc(phys_chunk, parent_gpu->id); + if (!mapping) { + uvm_gpu_unmap_cpu_pages(parent_gpu, dma_addr, chunk_size); + status = NV_ERR_NO_MEMORY; + goto done; } + + mapping->dma_addr = dma_addr; + mapping->map_count = 1; + uvm_processor_mask_set(&phys_chunk->gpu_mappings.dma_addrs_mask, parent_gpu->id); } else { - new_entries = uvm_kvrealloc(chunk->gpu_mappings.dynamic_entries, - sizeof(*new_entries) * num_new_entries); - if (new_entries) { - // Get the number of bits set below the input id. - num_existing_entries = compute_gpu_mappings_entry_index(chunk->gpu_mappings.dma_addrs_mask, id); - for (; num_existing_entries < num_new_entries - 1; num_existing_entries++) - new_entries[num_existing_entries + 1] = new_entries[num_existing_entries]; - } + // The mapping count on the physical chunk is only increased when + // mapping logical chunks. + if (uvm_cpu_chunk_is_logical(chunk)) + chunk_inc_gpu_mapping(phys_chunk, parent_gpu->id); } - if (!new_entries) - return NV_ERR_NO_MEMORY; +done: + uvm_mutex_unlock(&phys_chunk->lock); - chunk->gpu_mappings.dynamic_entries = new_entries; - uvm_processor_mask_set(&chunk->gpu_mappings.dma_addrs_mask, id); - array_index = compute_gpu_mappings_entry_index(chunk->gpu_mappings.dma_addrs_mask, id); - chunk->gpu_mappings.dynamic_entries[array_index] = dma_addr; + if (status == NV_OK && uvm_cpu_chunk_is_logical(chunk)) + uvm_processor_mask_set(&logical_chunk->mapped_gpus, parent_gpu->id); - return NV_OK; + return status; } -NvU64 uvm_cpu_chunk_get_gpu_mapping_addr(uvm_va_block_t *va_block, - uvm_page_index_t page_index, - uvm_cpu_chunk_t *chunk, - uvm_gpu_id_t id) +void uvm_cpu_chunk_unmap_gpu_phys(uvm_cpu_chunk_t *chunk, uvm_parent_gpu_t *parent_gpu) { - NvU64 dma_addr; - - if (!uvm_processor_mask_test(&chunk->gpu_mappings.dma_addrs_mask, id)) - return 0; + uvm_cpu_physical_chunk_t *phys_chunk; + uvm_cpu_logical_chunk_t *logical_chunk; - if (uvm_processor_mask_get_gpu_count(&chunk->gpu_mappings.dma_addrs_mask) == 1) { - dma_addr = chunk->gpu_mappings.static_entry; + if (uvm_cpu_chunk_is_logical(chunk)) { + logical_chunk = uvm_cpu_chunk_to_logical(chunk); + if (!uvm_processor_mask_test_and_clear(&logical_chunk->mapped_gpus, parent_gpu->id)) + return; } - else { - NvU32 array_index = compute_gpu_mappings_entry_index(chunk->gpu_mappings.dma_addrs_mask, id); - dma_addr = chunk->gpu_mappings.dynamic_entries[array_index]; - } + phys_chunk = get_physical_parent(chunk); + uvm_mutex_lock(&phys_chunk->lock); + if (uvm_processor_mask_test(&phys_chunk->gpu_mappings.dma_addrs_mask, parent_gpu->id)) + chunk_dec_gpu_mapping(phys_chunk, parent_gpu->id); - return dma_addr; + uvm_mutex_unlock(&phys_chunk->lock); } -// The bottom two bits of uvm_va_block_t::chunks is used to indicate how -// CPU chunks are stored. -// -// CPU chunk storage is handled in three different ways depending on the -// type of chunks the VA block owns. This is done to minimize the memory -// required to hold metadata. -typedef enum -{ - // The uvm_va_block_t::chunk pointer points to a single 2MB - // CPU chunk. - UVM_CPU_CHUNK_STORAGE_CHUNK = 0, - - // The uvm_va_block_t::chunks pointer points to an array of - // pointers to CPU chunks. - UVM_CPU_CHUNK_STORAGE_ARRAY, - - // The uvm_va_block_t::chunks pointer points to a - // structure of mixed (64K and 4K) chunks. - UVM_CPU_CHUNK_STORAGE_MIXED, - UVM_CPU_CHUNK_STORAGE_COUNT, -} uvm_cpu_chunk_storage_type_t; - -#define UVM_CPU_CHUNK_STORAGE_MASK 0x3 - -#define UVM_CPU_STORAGE_GET_PTR(block) ((void *)((block)->cpu.chunks & ~UVM_CPU_CHUNK_STORAGE_MASK)) -#define UVM_CPU_STORAGE_GET_TYPE(block) \ - ((uvm_cpu_chunk_storage_type_t)((block)->cpu.chunks & UVM_CPU_CHUNK_STORAGE_MASK)) - -// The maximum number of slots in the mixed chunk mode (64K + 4K chunks) is one -// more than MAX_BIG_PAGES_PER_UVM_VA_BLOCK to account for misaligned VA blocks. -#define MAX_BIG_CPU_CHUNK_SLOTS_PER_UVM_VA_BLOCK (MAX_BIG_PAGES_PER_UVM_VA_BLOCK + 1) - -#define MAX_SMALL_CHUNK_PER_BIG_SLOT (UVM_CHUNK_SIZE_64K / PAGE_SIZE) - -// This structure is used when a VA block contains 64K or a mix of 64K and 4K -// CPU chunks. -// For every 64K CPU chunks, big_chunks will have its corresponding bit set -// and the corresponding index in slots will point directly to the -// uvm_cpu_chunk_t structure. -// -// For 4K CPU chunks, the corresponding bit in big_chunks will be clear and -// the element in slots will point to an array of 16 uvm_cpu_chunk_t pointers. -typedef struct { - DECLARE_BITMAP(big_chunks, MAX_BIG_CPU_CHUNK_SLOTS_PER_UVM_VA_BLOCK); - void *slots[MAX_BIG_CPU_CHUNK_SLOTS_PER_UVM_VA_BLOCK]; -} uvm_cpu_chunk_storage_mixed_t; - -static uvm_page_index_t compute_slot_index(uvm_va_block_t *va_block, uvm_page_index_t page_index) +NV_STATUS uvm_cpu_chunk_map_gpu(uvm_cpu_chunk_t *chunk, uvm_gpu_t *gpu) { - uvm_va_block_region_t block_region = uvm_va_block_region_from_block(va_block); - size_t prefix; - uvm_page_index_t big_page_index; - - if (page_index < block_region.first || page_index >= block_region.outer) - return MAX_BIG_PAGES_PER_UVM_VA_BLOCK; - - prefix = (UVM_ALIGN_UP(va_block->start, UVM_CHUNK_SIZE_64K) - va_block->start) / PAGE_SIZE; - - if (page_index < prefix) - return 0; - - big_page_index = ((page_index - prefix) / MAX_SMALL_CHUNK_PER_BIG_SLOT) + !!prefix; - UVM_ASSERT(big_page_index < MAX_BIG_CPU_CHUNK_SLOTS_PER_UVM_VA_BLOCK); - - return big_page_index; -} + NV_STATUS status; + uvm_chunk_size_t chunk_size = uvm_cpu_chunk_get_size(chunk); -static size_t compute_small_index(uvm_va_block_t *va_block, uvm_page_index_t page_index) -{ - size_t prefix = (UVM_ALIGN_UP(va_block->start, UVM_CHUNK_SIZE_64K) - va_block->start) / PAGE_SIZE; + status = cpu_chunk_map_gpu_phys(chunk, gpu->parent); + if (status != NV_OK) + return status; - if (page_index < prefix) - return page_index; + status = uvm_mmu_sysmem_map(gpu, uvm_cpu_chunk_get_gpu_phys_addr(chunk, gpu->parent), chunk_size); + if (status != NV_OK) + uvm_cpu_chunk_unmap_gpu_phys(chunk, gpu->parent); - return (page_index - prefix) % MAX_SMALL_CHUNK_PER_BIG_SLOT; + return status; } -NV_STATUS uvm_cpu_chunk_insert_in_block(uvm_va_block_t *va_block, uvm_cpu_chunk_t *chunk, uvm_page_index_t page_index) +static struct page *uvm_cpu_chunk_alloc_page(uvm_chunk_size_t alloc_size, + uvm_cpu_chunk_alloc_flags_t alloc_flags) { - uvm_chunk_size_t chunk_size = uvm_cpu_chunk_get_size(chunk); - uvm_page_index_t big_page_index; - uvm_cpu_chunk_storage_mixed_t *mixed; - uvm_cpu_chunk_t **chunks = NULL; - - // We only want to use the bottom two bits of a pointer. - BUILD_BUG_ON(UVM_CPU_CHUNK_STORAGE_COUNT > 4); - - chunk->region = uvm_va_block_region(page_index, page_index + uvm_cpu_chunk_num_pages(chunk)); - UVM_ASSERT(chunk->region.outer <= PAGES_PER_UVM_VA_BLOCK); - - // We want to protect against two threads manipulating the VA block's CPU - // chunks at the same time. However, when a block is split, the new block's - // lock is locked without tracking. So, we can't use - // uvm_assert_mutex_locked(). - UVM_ASSERT(mutex_is_locked(&va_block->lock.m)); - - if (!va_block->cpu.chunks) { - switch (chunk_size) { - case UVM_CHUNK_SIZE_2M: - break; - case UVM_CHUNK_SIZE_64K: - mixed = uvm_kvmalloc_zero(sizeof(*mixed)); - if (!mixed) - return NV_ERR_NO_MEMORY; - - va_block->cpu.chunks = (unsigned long)mixed | UVM_CPU_CHUNK_STORAGE_MIXED; - break; - case UVM_CHUNK_SIZE_4K: - chunks = uvm_kvmalloc_zero(sizeof(*chunks) * uvm_va_block_num_cpu_pages(va_block)); - if (!chunks) - return NV_ERR_NO_MEMORY; + gfp_t kernel_alloc_flags; + struct page *page; - va_block->cpu.chunks = (unsigned long)chunks | UVM_CPU_CHUNK_STORAGE_ARRAY; - break; - default: - return NV_ERR_INVALID_ARGUMENT; - } - } + UVM_ASSERT(is_power_of_2(alloc_size)); + UVM_ASSERT(alloc_size & uvm_cpu_chunk_get_allocation_sizes()); - switch (UVM_CPU_STORAGE_GET_TYPE(va_block)) { - case UVM_CPU_CHUNK_STORAGE_CHUNK: - if (va_block->cpu.chunks) - return NV_ERR_INVALID_STATE; - UVM_ASSERT(chunk_size == UVM_CHUNK_SIZE_2M); - va_block->cpu.chunks = (unsigned long)chunk | UVM_CPU_CHUNK_STORAGE_CHUNK; - break; - case UVM_CPU_CHUNK_STORAGE_MIXED: - mixed = UVM_CPU_STORAGE_GET_PTR(va_block); - big_page_index = compute_slot_index(va_block, page_index); - UVM_ASSERT(big_page_index != MAX_BIG_PAGES_PER_UVM_VA_BLOCK); - UVM_ASSERT(compute_slot_index(va_block, page_index + uvm_cpu_chunk_num_pages(chunk) - 1) == big_page_index); - - if (test_bit(big_page_index, mixed->big_chunks)) - return NV_ERR_INVALID_STATE; - - if (chunk_size == UVM_CHUNK_SIZE_64K) { - mixed->slots[big_page_index] = chunk; - set_bit(big_page_index, mixed->big_chunks); - } - else { - size_t slot_index; - - UVM_ASSERT(chunk_size == UVM_CHUNK_SIZE_4K); - chunks = mixed->slots[big_page_index]; - - if (!chunks) { - chunks = uvm_kvmalloc_zero(sizeof(*chunks) * MAX_SMALL_CHUNK_PER_BIG_SLOT); - if (!chunks) - return NV_ERR_NO_MEMORY; - mixed->slots[big_page_index] = chunks; - } - - slot_index = compute_small_index(va_block, page_index); - chunks[slot_index] = chunk; - } - break; - case UVM_CPU_CHUNK_STORAGE_ARRAY: - chunks = UVM_CPU_STORAGE_GET_PTR(va_block); - if (chunk_size == UVM_CHUNK_SIZE_64K) { - uvm_cpu_chunk_t **subchunks = NULL; - uvm_page_index_t sub_page_index; - - mixed = uvm_kvmalloc_zero(sizeof(*mixed)); - if (!mixed) - return NV_ERR_NO_MEMORY; - - big_page_index = compute_slot_index(va_block, page_index); - UVM_ASSERT(big_page_index != MAX_BIG_PAGES_PER_UVM_VA_BLOCK); - UVM_ASSERT(compute_slot_index(va_block, page_index + uvm_cpu_chunk_num_pages(chunk) - 1) == - big_page_index); - mixed->slots[big_page_index] = chunk; - set_bit(big_page_index, mixed->big_chunks); - - for (sub_page_index = 0; sub_page_index < uvm_va_block_num_cpu_pages(va_block); sub_page_index++) { - uvm_cpu_chunk_t *subchunk = chunks[sub_page_index]; - size_t subchunk_index = compute_small_index(va_block, sub_page_index); - - if (!subchunk) - continue; - - if (!subchunks || compute_slot_index(va_block, sub_page_index) != big_page_index) { - subchunks = uvm_kvmalloc_zero(sizeof(*subchunks) * MAX_SMALL_CHUNK_PER_BIG_SLOT); - if (!subchunks) { - size_t i; - - for (i = 0; i < MAX_BIG_CPU_CHUNK_SLOTS_PER_UVM_VA_BLOCK; i++) { - if (!test_bit(i, mixed->big_chunks) && mixed->slots[i]) - uvm_kvfree(mixed->slots[i]); - } - - uvm_kvfree(mixed); - return NV_ERR_NO_MEMORY; - } - - big_page_index = compute_slot_index(va_block, sub_page_index); - UVM_ASSERT(mixed->slots[big_page_index] == NULL); - mixed->slots[big_page_index] = subchunks; - } - - subchunks[subchunk_index] = subchunk; - if (subchunk_index == MAX_SMALL_CHUNK_PER_BIG_SLOT - 1) - subchunks = NULL; - } - - va_block->cpu.chunks = (unsigned long)mixed | UVM_CPU_CHUNK_STORAGE_MIXED; - uvm_kvfree(chunks); - } - else { - chunks[page_index] = chunk; - } + if (alloc_flags & UVM_CPU_CHUNK_ALLOC_FLAGS_ACCOUNT) + kernel_alloc_flags = NV_UVM_GFP_FLAGS_ACCOUNT; + else + kernel_alloc_flags = NV_UVM_GFP_FLAGS; - default: - break; - } + kernel_alloc_flags |= GFP_HIGHUSER; - uvm_page_mask_region_fill(&va_block->cpu.allocated, - uvm_va_block_region(page_index, page_index + uvm_cpu_chunk_num_pages(chunk))); + // For allocation sizes higher than PAGE_SIZE, use __GFP_NORETRY in + // order to avoid higher allocation latency from the kernel compacting + // memory to satisfy the request. + if (alloc_size > PAGE_SIZE) + kernel_alloc_flags |= __GFP_COMP | __GFP_NORETRY; - return NV_OK; -} + if (alloc_flags & UVM_CPU_CHUNK_ALLOC_FLAGS_ZERO) + kernel_alloc_flags |= __GFP_ZERO; -void uvm_cpu_chunk_remove_from_block(uvm_va_block_t *va_block, uvm_cpu_chunk_t *chunk, uvm_page_index_t page_index) -{ - uvm_cpu_chunk_storage_mixed_t *mixed; - uvm_page_index_t big_page_index; - uvm_cpu_chunk_t **chunks; - - // We want to protect against two threads manipulating the VA block's CPU - // chunks at the same time. However, when a block is split, the new block's - // lock is locked without tracking. So, we can't use - // uvm_assert_mutex_locked(). - UVM_ASSERT(mutex_is_locked(&va_block->lock.m)); - UVM_ASSERT(va_block->cpu.chunks); - - switch (UVM_CPU_STORAGE_GET_TYPE(va_block)) { - case UVM_CPU_CHUNK_STORAGE_CHUNK: - UVM_ASSERT(uvm_cpu_chunk_get_size(chunk) == UVM_CHUNK_SIZE_2M); - UVM_ASSERT(UVM_CPU_STORAGE_GET_PTR(va_block) == chunk); - va_block->cpu.chunks = 0; - break; - case UVM_CPU_CHUNK_STORAGE_MIXED: - UVM_ASSERT(uvm_cpu_chunk_get_size(chunk) != UVM_CHUNK_SIZE_2M); - mixed = UVM_CPU_STORAGE_GET_PTR(va_block); - big_page_index = compute_slot_index(va_block, page_index); - UVM_ASSERT(big_page_index != MAX_BIG_PAGES_PER_UVM_VA_BLOCK); - UVM_ASSERT(mixed->slots[big_page_index] != NULL); - - if (test_bit(big_page_index, mixed->big_chunks)) { - UVM_ASSERT(uvm_cpu_chunk_get_size(chunk) == UVM_CHUNK_SIZE_64K); - UVM_ASSERT(mixed->slots[big_page_index] == chunk); - mixed->slots[big_page_index] = NULL; - clear_bit(big_page_index, mixed->big_chunks); - } - else { - size_t slot_index; - - UVM_ASSERT(uvm_cpu_chunk_get_size(chunk) == UVM_CHUNK_SIZE_4K); - chunks = mixed->slots[big_page_index]; - slot_index = compute_small_index(va_block, page_index); - UVM_ASSERT(chunks[slot_index] == chunk); - chunks[slot_index] = NULL; - - for (slot_index = 0; slot_index < MAX_SMALL_CHUNK_PER_BIG_SLOT; slot_index++) { - if (chunks[slot_index]) - break; - } - - if (slot_index == MAX_SMALL_CHUNK_PER_BIG_SLOT) { - uvm_kvfree(chunks); - mixed->slots[big_page_index] = NULL; - } - } + page = alloc_pages(kernel_alloc_flags, get_order(alloc_size)); + if (page && (alloc_flags & UVM_CPU_CHUNK_ALLOC_FLAGS_ZERO)) + SetPageDirty(page); - break; - case UVM_CPU_CHUNK_STORAGE_ARRAY: - UVM_ASSERT(uvm_cpu_chunk_get_size(chunk) == UVM_CHUNK_SIZE_4K); - chunks = UVM_CPU_STORAGE_GET_PTR(va_block); - UVM_ASSERT(chunks[page_index] == chunk); - chunks[page_index] = NULL; - break; - default: - return; - }; - - uvm_page_mask_region_clear(&va_block->cpu.allocated, chunk->region); - - if (uvm_page_mask_empty(&va_block->cpu.allocated)) { - if (UVM_CPU_STORAGE_GET_TYPE(va_block) != UVM_CPU_CHUNK_STORAGE_CHUNK) - uvm_kvfree(UVM_CPU_STORAGE_GET_PTR(va_block)); - va_block->cpu.chunks = 0; - } + return page; } -uvm_cpu_chunk_t *uvm_cpu_chunk_get_chunk_for_page(uvm_va_block_t *va_block, uvm_page_index_t page_index) +static uvm_cpu_physical_chunk_t *uvm_cpu_chunk_create(uvm_chunk_size_t alloc_size) { - uvm_cpu_chunk_storage_mixed_t *mixed; - uvm_cpu_chunk_t *chunk; - uvm_cpu_chunk_t **chunks; - uvm_page_index_t big_page_index; - size_t slot_index; + uvm_cpu_physical_chunk_t *chunk; - if (page_index >= uvm_va_block_num_cpu_pages(va_block) || !uvm_page_mask_test(&va_block->cpu.allocated, page_index)) + chunk = uvm_kvmalloc_zero(sizeof(*chunk)); + if (!chunk) return NULL; - UVM_ASSERT(va_block->cpu.chunks); - - switch (UVM_CPU_STORAGE_GET_TYPE(va_block)) { - case UVM_CPU_CHUNK_STORAGE_CHUNK: - return UVM_CPU_STORAGE_GET_PTR(va_block); - case UVM_CPU_CHUNK_STORAGE_MIXED: - mixed = UVM_CPU_STORAGE_GET_PTR(va_block); - big_page_index = compute_slot_index(va_block, page_index); - UVM_ASSERT(big_page_index != MAX_BIG_PAGES_PER_UVM_VA_BLOCK); - UVM_ASSERT(mixed->slots[big_page_index] != NULL); - if (test_bit(big_page_index, mixed->big_chunks)) - return mixed->slots[big_page_index]; - - chunks = mixed->slots[big_page_index]; - slot_index = compute_small_index(va_block, page_index); - chunk = chunks[slot_index]; - break; - case UVM_CPU_CHUNK_STORAGE_ARRAY: - chunks = UVM_CPU_STORAGE_GET_PTR(va_block); - chunk = chunks[page_index]; - break; - default: + uvm_cpu_chunk_set_size(&chunk->common, alloc_size); + nv_kref_init(&chunk->common.refcount); + uvm_mutex_init(&chunk->lock, UVM_LOCK_ORDER_LEAF); + chunk->gpu_mappings.max_entries = 1; + if (alloc_size > PAGE_SIZE) { + chunk->dirty_bitmap = uvm_kvmalloc_zero(BITS_TO_LONGS(alloc_size / PAGE_SIZE) * sizeof(*chunk->dirty_bitmap)); + if (!chunk->dirty_bitmap) { + uvm_kvfree(chunk); return NULL; + } } - UVM_ASSERT(chunk); return chunk; } -NV_STATUS uvm_cpu_chunk_alloc(uvm_va_block_t *va_block, - uvm_page_index_t page_index, - struct mm_struct *mm, +NV_STATUS uvm_cpu_chunk_alloc(uvm_chunk_size_t alloc_size, + uvm_cpu_chunk_alloc_flags_t alloc_flags, uvm_cpu_chunk_t **new_chunk) { - uvm_va_block_test_t *block_test = uvm_va_block_get_test(va_block); - uvm_cpu_chunk_t *chunk = NULL; - NvU32 cpu_allocation_sizes; - uvm_page_mask_t zero_page_mask; - uvm_gpu_id_t id; - struct page *page = NULL; - uvm_chunk_size_t alloc_size; - uvm_va_block_region_t region; - uvm_va_space_t *va_space; - uvm_processor_mask_t uvm_lite_gpus; - gfp_t base_alloc_flags; - NV_STATUS status; + uvm_cpu_physical_chunk_t *chunk; + struct page *page; UVM_ASSERT(new_chunk); - // Limit the allocation sizes only to the ones supported. - cpu_allocation_sizes = uvm_cpu_chunk_get_allocation_sizes(); - - if (block_test && block_test->cpu_chunk_allocation_size_mask) - cpu_allocation_sizes &= block_test->cpu_chunk_allocation_size_mask; - - // Get a mask of all the block pages that are resident somewhere. - uvm_page_mask_zero(&zero_page_mask); - for_each_id_in_mask(id, &va_block->resident) - uvm_page_mask_or(&zero_page_mask, &zero_page_mask, uvm_va_block_resident_mask_get(va_block, id)); - - // If the VA space has a UVM-Lite GPU registered, only PAGE_SIZE allocations - // should be used in order to avoid extra copies due to dirty compound - // pages. - va_space = uvm_va_block_get_va_space(va_block); - uvm_processor_mask_andnot(&uvm_lite_gpus, &va_space->registered_gpus, &va_space->faultable_processors); - if (!uvm_processor_mask_empty(&uvm_lite_gpus)) - cpu_allocation_sizes = PAGE_SIZE; - - base_alloc_flags = (mm ? NV_UVM_GFP_FLAGS_ACCOUNT : NV_UVM_GFP_FLAGS) | GFP_HIGHUSER; - - // Attempt to allocate CPU pages with the largest physically contiguous - // size from the set of CPU chunk sizes that we can. - // This is accomplished by: - // 1. Aligning the CPU page address down to the allocation size. - // 2. Ensuring that the entire allocation region fits withing the VA - // block. - // 3. Ensuring that the region covered by the allocation is empty. - for_each_chunk_size_rev(alloc_size, cpu_allocation_sizes) { - NvU64 alloc_virt_addr; - uvm_page_mask_t scratch_page_mask; - uvm_page_index_t alloc_page_index; - gfp_t alloc_flags = base_alloc_flags; - - if (alloc_size < PAGE_SIZE) - break; - - alloc_virt_addr = UVM_ALIGN_DOWN(uvm_va_block_cpu_page_address(va_block, page_index), alloc_size); - - if (!uvm_va_block_contains_address(va_block, alloc_virt_addr) || - !uvm_va_block_contains_address(va_block, alloc_virt_addr + alloc_size - 1)) - continue; - - alloc_page_index = uvm_va_block_cpu_page_index(va_block, alloc_virt_addr); - region = uvm_va_block_region(alloc_page_index, alloc_page_index + (alloc_size / PAGE_SIZE)); - uvm_page_mask_init_from_region(&scratch_page_mask, region, NULL); - uvm_page_mask_and(&scratch_page_mask, &va_block->cpu.allocated, &scratch_page_mask); - - if (!uvm_page_mask_empty(&scratch_page_mask)) - continue; - - // For allocation sizes higher than PAGE_SIZE, use __GFP_NORETRY in - // order to avoid higher allocation latency from the kernel compacting - // memory to satisfy the request. - if (alloc_size > PAGE_SIZE) - alloc_flags |= __GFP_COMP | __GFP_NORETRY; - - // If not all pages in the allocation region are resident somewhere, - // zero out the allocated page. - // This could be wasteful if only a few pages in high-order allocation - // need to be zero'ed out but the alternative is to map single sub- - // pages one-by-one. - if (!uvm_page_mask_region_full(&zero_page_mask, region)) - alloc_flags |= __GFP_ZERO; - - page = alloc_pages(alloc_flags, get_order(alloc_size)); - if (page) { - if (alloc_flags & __GFP_ZERO) - SetPageDirty(page); - break; - } - } - - if (!page) { - status = NV_ERR_NO_MEMORY; - goto error; - } + page = uvm_cpu_chunk_alloc_page(alloc_size, alloc_flags); + if (!page) + return NV_ERR_NO_MEMORY; - chunk = uvm_kvmalloc_zero(sizeof(*chunk)); + chunk = uvm_cpu_chunk_create(alloc_size); if (!chunk) { - status = NV_ERR_NO_MEMORY; - goto error; + __free_pages(page, get_order(alloc_size)); + return NV_ERR_NO_MEMORY; } - chunk->page = page; - uvm_cpu_chunk_set_size(chunk, alloc_size); - chunk->region = region; - nv_kref_init(&chunk->refcount); - uvm_spin_lock_init(&chunk->lock, UVM_LOCK_ORDER_LEAF); - if (alloc_size > PAGE_SIZE) { - chunk->dirty_bitmap = uvm_kvmalloc_zero(BITS_TO_LONGS(alloc_size / PAGE_SIZE) * sizeof(*chunk->dirty_bitmap)); - if (!chunk->dirty_bitmap) { - status = NV_ERR_NO_MEMORY; - goto error; - } - } + chunk->common.type = UVM_CPU_CHUNK_TYPE_PHYSICAL; + chunk->common.page = page; - status = uvm_cpu_chunk_insert_in_block(va_block, chunk, chunk->region.first); - if (status != NV_OK) - goto error; + *new_chunk = &chunk->common; + return NV_OK; +} - if (new_chunk) - *new_chunk = chunk; +NV_STATUS uvm_cpu_chunk_alloc_hmm(struct page *page, + uvm_cpu_chunk_t **new_chunk) +{ + uvm_cpu_physical_chunk_t *chunk; - return NV_OK; + UVM_ASSERT(new_chunk); -error: + chunk = uvm_cpu_chunk_create(PAGE_SIZE); + if (!chunk) + return NV_ERR_NO_MEMORY; - // If chunk has been allocated, uvm_cpu_chunk_put() will release the chunk - // and the page. Otherwise, only release the page. - if (chunk) - uvm_cpu_chunk_put(chunk); - else if (page) - __free_pages(page, get_order(alloc_size)); + chunk->common.type = UVM_CPU_CHUNK_TYPE_HMM; + chunk->common.page = page; - return status; + *new_chunk = &chunk->common; + return NV_OK; } -NV_STATUS uvm_cpu_chunk_split(uvm_va_block_t *va_block, - uvm_cpu_chunk_t *chunk, - uvm_chunk_size_t new_size, - uvm_page_index_t page_index, - uvm_cpu_chunk_t **new_chunks) +NV_STATUS uvm_cpu_chunk_split(uvm_cpu_chunk_t *chunk, uvm_cpu_chunk_t **new_chunks) { NV_STATUS status = NV_OK; - uvm_cpu_chunk_t *new_chunk; - uvm_page_index_t running_page_index = page_index; + uvm_cpu_logical_chunk_t *new_chunk; + uvm_cpu_physical_chunk_t *phys_chunk = get_physical_parent(chunk); + uvm_cpu_logical_chunk_t *logical_chunk = NULL; + uvm_processor_id_t id; + uvm_processor_mask_t *dma_map_mask; + uvm_chunk_size_t new_size; size_t num_new_chunks; size_t num_subchunk_pages; size_t i; UVM_ASSERT(chunk); - UVM_ASSERT(is_power_of_2(new_size)); - UVM_ASSERT(new_size < uvm_cpu_chunk_get_size(chunk)); UVM_ASSERT(new_chunks); + UVM_ASSERT(chunk->type != UVM_CPU_CHUNK_TYPE_HMM); + // This should never be true as HMM chunks are currently all of size + // PAGE_SIZE and can't be split and attempting to won't work as it requires + // kernel interaction. + // TODO: Bug 3368756: add support for transparent huge page (THP) + if (chunk->type == UVM_CPU_CHUNK_TYPE_HMM) + return NV_ERR_INVALID_ARGUMENT; + + // Get the largest size below the size of the input chunk. + new_size = uvm_chunk_find_prev_size(uvm_cpu_chunk_get_allocation_sizes(), uvm_cpu_chunk_get_size(chunk)); + UVM_ASSERT(new_size != UVM_CHUNK_SIZE_INVALID); num_new_chunks = uvm_cpu_chunk_get_size(chunk) / new_size; num_subchunk_pages = new_size / PAGE_SIZE; - for (i = 0; i < num_new_chunks; i++) { - uvm_page_index_t relative_page_index = running_page_index - page_index; - uvm_gpu_id_t id; + if (uvm_cpu_chunk_is_physical(chunk)) { + dma_map_mask = &phys_chunk->gpu_mappings.dma_addrs_mask; + } + else { + logical_chunk = uvm_cpu_chunk_to_logical(chunk); + dma_map_mask = &logical_chunk->mapped_gpus; + } - new_chunk = uvm_kvmalloc_zero(sizeof(*new_chunk)); + uvm_mutex_lock(&phys_chunk->lock); + for (i = 0; i < num_new_chunks; i++) { + new_chunk = uvm_kvmalloc_zero(sizeof(*logical_chunk)); if (!new_chunk) { + uvm_mutex_unlock(&phys_chunk->lock); status = NV_ERR_NO_MEMORY; goto error; } - new_chunk->page = chunk->page + relative_page_index; - new_chunk->offset = chunk->offset + relative_page_index; - new_chunk->region = uvm_va_block_region(running_page_index, running_page_index + num_subchunk_pages); - uvm_cpu_chunk_set_size(new_chunk, new_size); - nv_kref_init(&new_chunk->refcount); - - // This lock is unused for logical chunks but initialize it for - // consistency. - uvm_spin_lock_init(&new_chunk->lock, UVM_LOCK_ORDER_LEAF); + new_chunk->common.type = UVM_CPU_CHUNK_TYPE_LOGICAL; + new_chunk->common.page = chunk->page + (i * num_subchunk_pages); + uvm_cpu_chunk_set_size(&new_chunk->common, new_size); + nv_kref_init(&new_chunk->common.refcount); new_chunk->parent = chunk; uvm_cpu_chunk_get(new_chunk->parent); + for_each_id_in_mask(id, dma_map_mask) + chunk_inc_gpu_mapping(phys_chunk, id); + uvm_processor_mask_copy(&new_chunk->mapped_gpus, dma_map_mask); + new_chunks[i] = &new_chunk->common; + } - for_each_gpu_id(id) { - NvU64 parent_dma_addr = uvm_cpu_chunk_get_gpu_mapping_addr(va_block, running_page_index, chunk, id); + // Release the references that are held by the chunk being split. + for_each_id_in_mask(id, dma_map_mask) + chunk_dec_gpu_mapping(phys_chunk, id); - if (!parent_dma_addr) - continue; + // If the chunk being split is a logical chunk clear it's mapped_gpus mask. + if (uvm_cpu_chunk_is_logical(chunk)) + uvm_processor_mask_zero(&logical_chunk->mapped_gpus); - uvm_cpu_chunk_set_gpu_mapping_addr(va_block, - relative_page_index, - new_chunk, - id, - parent_dma_addr + (relative_page_index * PAGE_SIZE)); - } - - new_chunks[i] = new_chunk; - running_page_index += num_subchunk_pages; - } + uvm_mutex_unlock(&phys_chunk->lock); // Drop the original reference count on the parent (from its creation). This // is done so the parent's reference count goes to 0 when all the children // are released. - uvm_cpu_chunk_put(chunk); + uvm_cpu_chunk_free(chunk); error: if (status != NV_OK) { while (i--) - uvm_cpu_chunk_put(new_chunk); + uvm_cpu_chunk_free(new_chunks[i]); } return status; } -NV_STATUS uvm_cpu_chunk_merge(uvm_va_block_t *va_block, - uvm_cpu_chunk_t **chunks, - size_t num_merge_chunks, - uvm_chunk_size_t merge_size, - uvm_cpu_chunk_t **merged_chunk) +static bool verify_merging_chunks(uvm_cpu_chunk_t **chunks, size_t num_chunks) +{ + uvm_cpu_logical_chunk_t *logical_chunk; + uvm_cpu_chunk_t *first_chunk_parent; + uvm_processor_mask_t *first_chunk_mapped_gpus; + uvm_chunk_size_t first_chunk_size; + size_t i; + + logical_chunk = uvm_cpu_chunk_to_logical(chunks[0]); + first_chunk_size = uvm_cpu_chunk_get_size(chunks[0]); + first_chunk_parent = logical_chunk->parent; + first_chunk_mapped_gpus = &logical_chunk->mapped_gpus; + + // Only chunks with the same size and parent can be merged. + for (i = 1; i < num_chunks; i++) { + UVM_ASSERT(uvm_cpu_chunk_is_logical(chunks[i])); + + logical_chunk = uvm_cpu_chunk_to_logical(chunks[i]); + UVM_ASSERT(logical_chunk->parent); + UVM_ASSERT(logical_chunk->parent == first_chunk_parent); + UVM_ASSERT(uvm_cpu_chunk_get_size(&logical_chunk->common) == first_chunk_size); + UVM_ASSERT(nv_kref_read(&logical_chunk->common.refcount) == 1); + + // For now, we require that all logical chunks to be merged have to be + // mapped on the same set of processors in order to be merged. + // + // If this requirement is relaxed in the future, the process to handle + // GPU mappings would be: + // 1. If mapped_gpus matches for all child chunks, the parent chunk's + // mapped_gpus mask is set to + // (child_mapped_gpus | parent_mapped_gpus). + // 2. If the mapped_gpus masks for the child chunks don't match: + // 2.1 All mappings to GPUs in each of child chunks' masks that are + // not also present in the parent chunk's mask are destroyed. + // 2.2 mapped_gpus mask of the parent chunk remains unmodified. + UVM_ASSERT(uvm_processor_mask_equal(&logical_chunk->mapped_gpus, first_chunk_mapped_gpus)); + } + + return true; +} + +uvm_cpu_chunk_t *uvm_cpu_chunk_merge(uvm_cpu_chunk_t **chunks) { uvm_cpu_chunk_t *parent; + uvm_cpu_logical_chunk_t *logical_chunk; + uvm_cpu_physical_chunk_t *phys_chunk; + uvm_processor_id_t id; uvm_chunk_size_t chunk_size; + uvm_chunk_size_t parent_chunk_size; + size_t num_merge_chunks; size_t i; UVM_ASSERT(chunks); - UVM_ASSERT(num_merge_chunks > 0); - UVM_ASSERT(merged_chunk); + UVM_ASSERT(!uvm_cpu_chunk_is_physical(chunks[0])); - parent = chunks[0]->parent; - if (!parent) - return NV_WARN_NOTHING_TO_DO; + logical_chunk = uvm_cpu_chunk_to_logical(chunks[0]); + parent = logical_chunk->parent; + UVM_ASSERT(parent); chunk_size = uvm_cpu_chunk_get_size(chunks[0]); - - UVM_ASSERT(uvm_cpu_chunk_get_size(parent) == merge_size); - UVM_ASSERT(merge_size > chunk_size); - - for (i = 1; i < num_merge_chunks; i++) { - if (chunks[i]->parent != parent || uvm_cpu_chunk_get_size(chunks[i]) != chunk_size) - return NV_ERR_INVALID_ARGUMENT; - - UVM_ASSERT(nv_kref_read(&chunks[i]->refcount) == 1); - } + parent_chunk_size = uvm_cpu_chunk_get_size(parent); + UVM_ASSERT(IS_ALIGNED(parent_chunk_size, chunk_size)); + num_merge_chunks = parent_chunk_size / chunk_size; + + // This assert will never trigger since verify_merging_chunks() always + // returns true. However, it will eliminate the call on release builds. + UVM_ASSERT(verify_merging_chunks(chunks, num_merge_chunks)); // Take a reference on the parent chunk so it doesn't get released when all // of the children are released below. uvm_cpu_chunk_get(parent); + phys_chunk = get_physical_parent(chunks[0]); - for (i = 0; i < num_merge_chunks; i++) - uvm_cpu_chunk_put(chunks[i]); + uvm_mutex_lock(&phys_chunk->lock); + for_each_id_in_mask(id, &logical_chunk->mapped_gpus) + chunk_inc_gpu_mapping(phys_chunk, id); - *merged_chunk = parent; + if (!uvm_cpu_chunk_is_physical(parent)) + uvm_processor_mask_copy(&uvm_cpu_chunk_to_logical(parent)->mapped_gpus, &logical_chunk->mapped_gpus); - return NV_OK; -} + uvm_mutex_unlock(&phys_chunk->lock); -static uvm_cpu_chunk_t *get_parent_cpu_chunk(uvm_cpu_chunk_t *chunk) -{ - UVM_ASSERT(chunk); - - while (chunk->parent) - chunk = chunk->parent; + for (i = 0; i < num_merge_chunks; i++) + uvm_cpu_chunk_free(chunks[i]); - return chunk; + return parent; } // Check the CPU PTE dirty bit and if set, clear it and fill the // physical chunk's dirty bitmap. -static void check_cpu_dirty_flag(uvm_cpu_chunk_t *chunk, uvm_page_index_t page_index) +static void check_cpu_dirty_flag(uvm_cpu_physical_chunk_t *chunk, uvm_page_index_t page_index) { struct page *page; - UVM_ASSERT(!chunk->parent); - uvm_assert_spinlock_locked(&chunk->lock); + uvm_assert_mutex_locked(&chunk->lock); // Kernels prior to v4.5 used the flags within the individual pages even for - // compound pages. - page = chunk->page + page_index; - if (PageDirty(page)) { - bitmap_fill(chunk->dirty_bitmap, uvm_cpu_chunk_get_size(chunk) / PAGE_SIZE); - ClearPageDirty(page); - } -} - -static uvm_cpu_chunk_t *get_parent_and_page_index(uvm_cpu_chunk_t *chunk, uvm_page_index_t *out_page_index) -{ - uvm_cpu_chunk_t *parent; - uvm_page_index_t page_index; - - UVM_ASSERT(chunk); - UVM_ASSERT(chunk->page); - UVM_ASSERT(out_page_index); - page_index = *out_page_index; - UVM_ASSERT(chunk->region.first <= page_index && page_index < chunk->region.outer); - - page_index = chunk->offset + (page_index - chunk->region.first); - parent = get_parent_cpu_chunk(chunk); - UVM_ASSERT(page_index < uvm_cpu_chunk_get_size(parent) / PAGE_SIZE); - *out_page_index = page_index; - return parent; + // compound pages. For those kernels, we don't necessarily need the bitmap + // but using it allows for a single implementation. + page = chunk->common.page + page_index; + if (TestClearPageDirty(page)) + bitmap_fill(chunk->dirty_bitmap, uvm_cpu_chunk_num_pages(&chunk->common)); } void uvm_cpu_chunk_mark_dirty(uvm_cpu_chunk_t *chunk, uvm_page_index_t page_index) { - uvm_cpu_chunk_t *parent; + uvm_cpu_physical_chunk_t *parent; - parent = get_parent_and_page_index(chunk, &page_index); - if (uvm_cpu_chunk_get_size(parent) == PAGE_SIZE) { - SetPageDirty(parent->page); + UVM_ASSERT(page_index < uvm_cpu_chunk_num_pages(chunk)); + UVM_ASSERT(!uvm_cpu_chunk_is_hmm(chunk)); + + if (uvm_cpu_chunk_is_physical(chunk) && uvm_cpu_chunk_get_size(chunk) == PAGE_SIZE) { + SetPageDirty(chunk->page); return; } - uvm_spin_lock(&parent->lock); + parent = get_physical_parent(chunk); + if (uvm_cpu_chunk_is_logical(chunk)) { + uvm_cpu_logical_chunk_t *logical_chunk = uvm_cpu_chunk_to_logical(chunk); + page_index += cpu_chunk_get_phys_index(logical_chunk); + } + + uvm_mutex_lock(&parent->lock); set_bit(page_index, parent->dirty_bitmap); - uvm_spin_unlock(&parent->lock); + uvm_mutex_unlock(&parent->lock); } void uvm_cpu_chunk_mark_clean(uvm_cpu_chunk_t *chunk, uvm_page_index_t page_index) { - uvm_cpu_chunk_t *parent; + uvm_cpu_physical_chunk_t *parent; - parent = get_parent_and_page_index(chunk, &page_index); - if (uvm_cpu_chunk_get_size(parent) == PAGE_SIZE) { - ClearPageDirty(parent->page); + UVM_ASSERT(page_index < uvm_cpu_chunk_num_pages(chunk)); + UVM_ASSERT(!uvm_cpu_chunk_is_hmm(chunk)); + + if (uvm_cpu_chunk_is_physical(chunk) && uvm_cpu_chunk_get_size(chunk) == PAGE_SIZE) { + ClearPageDirty(chunk->page); return; } - uvm_spin_lock(&parent->lock); + parent = get_physical_parent(chunk); + if (uvm_cpu_chunk_is_logical(chunk)) { + uvm_cpu_logical_chunk_t *logical_chunk = uvm_cpu_chunk_to_logical(chunk); + page_index += cpu_chunk_get_phys_index(logical_chunk); + } + + uvm_mutex_lock(&parent->lock); check_cpu_dirty_flag(parent, page_index); clear_bit(page_index, parent->dirty_bitmap); - uvm_spin_unlock(&parent->lock); + uvm_mutex_unlock(&parent->lock); } bool uvm_cpu_chunk_is_dirty(uvm_cpu_chunk_t *chunk, uvm_page_index_t page_index) { - uvm_cpu_chunk_t *parent; + uvm_cpu_physical_chunk_t *parent; bool dirty; - parent = get_parent_and_page_index(chunk, &page_index); - if (uvm_cpu_chunk_get_size(parent) == PAGE_SIZE) - return PageDirty(parent->page); + UVM_ASSERT(page_index < uvm_cpu_chunk_num_pages(chunk)); + UVM_ASSERT(!uvm_cpu_chunk_is_hmm(chunk)); + + if (uvm_cpu_chunk_is_physical(chunk) && uvm_cpu_chunk_get_size(chunk) == PAGE_SIZE) + return PageDirty(chunk->page); + + parent = get_physical_parent(chunk); + if (uvm_cpu_chunk_is_logical(chunk)) { + uvm_cpu_logical_chunk_t *logical_chunk = uvm_cpu_chunk_to_logical(chunk); + page_index += cpu_chunk_get_phys_index(logical_chunk); + } - uvm_spin_lock(&parent->lock); + uvm_mutex_lock(&parent->lock); check_cpu_dirty_flag(parent, page_index); dirty = test_bit(page_index, parent->dirty_bitmap); - uvm_spin_unlock(&parent->lock); + uvm_mutex_unlock(&parent->lock); return dirty; } -#endif // !UVM_CPU_CHUNK_SIZE_IS_PAGE_SIZE() - -uvm_cpu_chunk_t *uvm_cpu_chunk_first_in_block(uvm_va_block_t *va_block, uvm_page_index_t *out_page_index) -{ - uvm_cpu_chunk_t *chunk = NULL; - uvm_page_index_t page_index; - uvm_va_block_region_t block_region = uvm_va_block_region_from_block(va_block); - - page_index = uvm_va_block_first_page_in_mask(block_region, &va_block->cpu.allocated); - if (page_index < block_region.outer) - chunk = uvm_cpu_chunk_get_chunk_for_page(va_block, page_index); - - if (out_page_index) - *out_page_index = page_index; - - return chunk; -} - -uvm_cpu_chunk_t *uvm_cpu_chunk_next(uvm_va_block_t *va_block, uvm_page_index_t *previous_page_index) -{ - uvm_va_block_region_t block_region; - - UVM_ASSERT(va_block); - UVM_ASSERT(previous_page_index); - - block_region = uvm_va_block_region_from_block(va_block); - *previous_page_index = uvm_va_block_next_page_in_mask(block_region, &va_block->cpu.allocated, *previous_page_index); - if (*previous_page_index == block_region.outer) - return NULL; - - return uvm_cpu_chunk_get_chunk_for_page(va_block, *previous_page_index); -} diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/kernel-open/nvidia-uvm/uvm_pmm_sysmem.h nvidia-open-gpu-kernel-modules-535.161.08/kernel-open/nvidia-uvm/uvm_pmm_sysmem.h --- nvidia-open-gpu-kernel-modules-525.147.05/kernel-open/nvidia-uvm/uvm_pmm_sysmem.h 2023-10-25 20:33:40.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/kernel-open/nvidia-uvm/uvm_pmm_sysmem.h 2024-03-05 22:26:00.000000000 +0000 @@ -28,6 +28,7 @@ #include "uvm_linux.h" #include "uvm_forward_decl.h" #include "uvm_lock.h" +#include "uvm_pmm_gpu.h" // Module to handle per-GPU user mappings to sysmem physical memory. Notably, // this implements a reverse map of the DMA address to {va_block, virt_addr}. @@ -176,17 +177,25 @@ uvm_reverse_map_t *out_mappings, size_t max_out_mappings); -#define UVM_CPU_CHUNK_SIZES PAGE_SIZE +#define UVM_CPU_CHUNK_SIZES (UVM_PAGE_SIZE_2M | UVM_PAGE_SIZE_64K | PAGE_SIZE) -#if UVM_CPU_CHUNK_SIZES == PAGE_SIZE -#define UVM_CPU_CHUNK_SIZE_IS_PAGE_SIZE() 1 -typedef struct page uvm_cpu_chunk_t; +typedef enum +{ + UVM_CPU_CHUNK_ALLOC_FLAGS_NONE = 0, -#define UVM_CPU_CHUNK_PAGE_INDEX(chunk, page_index) (page_index) + // Zero the chunk. + UVM_CPU_CHUNK_ALLOC_FLAGS_ZERO = (1 << 0), -#else -#define UVM_CPU_CHUNK_SIZE_IS_PAGE_SIZE() 0 -typedef struct uvm_cpu_chunk_struct uvm_cpu_chunk_t; + // Account for the chunk in the cgroup context. + UVM_CPU_CHUNK_ALLOC_FLAGS_ACCOUNT = (1 << 1), +} uvm_cpu_chunk_alloc_flags_t; + +typedef enum +{ + UVM_CPU_CHUNK_TYPE_PHYSICAL, + UVM_CPU_CHUNK_TYPE_LOGICAL, + UVM_CPU_CHUNK_TYPE_HMM +} uvm_cpu_chunk_type_t; // CPU memory chunk descriptor. // CPU memory chunks represent a physically contiguous CPU memory @@ -197,6 +206,22 @@ // splitting are referred to as "logical chunks". struct uvm_cpu_chunk_struct { + uvm_cpu_chunk_type_t type:2; + + // Size of the chunk. + // For chunks resulting from page allocations (physical chunks), + // this value is the size of the physical allocation. + size_t log2_size : order_base_2(UVM_CHUNK_SIZE_MASK_SIZE); + + // Chunk reference count used when a CPU chunk is split. Each + // child sub-chunk will increment the reference count of its + // parent. + // The reference count is set to 1 when the chunk is created. + // This initial reference is dropped if the chunk is split in + // order to automatically destroy the chunk when all logical + // chunks resulting from the split are destroyed. + nv_kref_t refcount; + // Pointer to the CPU page backing this CPU chunk. // For physical chunks, this will point to the head page. Physical // chunk allocation will set the reference count for the struct @@ -209,100 +234,110 @@ // reference counted, there is no need to take separate references // to the struct page for logical chunks. struct page *page; +}; - // For logical chunks, this points to the parent chunk (which - // could also be a logical chunk). For physical chunks, this - // is NULL. - uvm_cpu_chunk_t *parent; - - // Page offset of this chunk within the physical size of - // the parent. - uvm_page_index_t offset; - - // Region within the VA block covered by this CPU chunk. - uvm_va_block_region_t region; +typedef struct +{ + NvU64 dma_addr; + NvU32 map_count; +} uvm_cpu_phys_mapping_t; - // Chunk reference count used when a CPU chunk is split. Each - // child sub-chunk will increment the reference count of its - // parent. - nv_kref_t refcount; +typedef struct +{ + uvm_cpu_chunk_t common; - // Size of the chunk. - // For chunks resulting from page allocations (physical chunks), - // this value is the size of the physical allocation. - size_t log2_size : order_base_2(UVM_CHUNK_SIZE_MASK_SIZE); + // Lock protecting dirty_bitmap and gpu_mappings. + uvm_mutex_t lock; - struct { + struct + { // Per-GPU array of DMA mapping addresses for the chunk. // The DMA mapping addresses for logical chunks are adjusted // to the correct offset within the parent chunk. - union { - NvU64 static_entry; - NvU64 *dynamic_entries; + union + { + uvm_cpu_phys_mapping_t static_entry; + uvm_cpu_phys_mapping_t *dynamic_entries; }; + + // Miximum number of physical mapping entries available. + // The initial value is 1 since the static_entry is always + // available. + // When using the dynamic_entries, it holds the size of the + // dynamic_entries array. This may be more than the number + // of GPUs with active mappings. The number of active entries + // is the number of set bits in dma_addrs_mask. + size_t max_entries; + + // The set of GPU ID's that have an active physical mapping. + // Since physical mappings are shared by all GPUs under a + // parent GPU, this mask only needs to track uvm_parent_gpu_t. uvm_processor_mask_t dma_addrs_mask; } gpu_mappings; - // Lock protecting dirty_bitmap - uvm_spinlock_t lock; - // A dynamically allocated bitmap (one per PAGE_SIZE page) used // to track dirty state of each PAGE_SIZE page. - // Dirty state is tracked only by physical chunks. Therefore, - // for logical chunks this will be NULL; + // Large CPU chunks are allocated as compound pages. For such + // pages, the kernel keeps dirtiness state with a single bit + // (in the compound page head) that covers the entire compound + // page. + // + // In the case of UVM-Lite GPUs, using the dirty bit of the + // the compound page will cause performance regression due to + // the copying of extra data. We mitigate this by using this + // bitmap to track which base pages are dirty. unsigned long *dirty_bitmap; -}; -#define UVM_CPU_CHUNK_PAGE_INDEX(chunk, page_index) (chunk->region.first) -#endif // UVM_CPU_CHUNK_SIZES == PAGE_SIZE +} uvm_cpu_physical_chunk_t; + +typedef struct +{ + uvm_cpu_chunk_t common; + + // Pointer to the parent chunk (which could also be a logical chunk). + uvm_cpu_chunk_t *parent; + uvm_processor_mask_t mapped_gpus; +} uvm_cpu_logical_chunk_t; // Return the set of allowed CPU chunk allocation sizes. uvm_chunk_sizes_mask_t uvm_cpu_chunk_get_allocation_sizes(void); -// Allocate a physical CPU chunk for the specified page index and owned by -// va_block. +// Allocate a physical CPU chunk of the specified size. // -// The size of the allocated CPU chunk may be any of the allowed sizes and -// depends on several factors: -// * Allocation will be attempted in reverse order - highest to lowest - in -// order ensure that the highest possible size is used. -// * An allocation size will be used if: -// - the VA region within the block covered by the allocation size is -// aligned to that allocation size, -// - the VA block region corresponding to the allocation size is empty -// (has no previously populated pages), and -// - the system allows a page allocation of that size. -// -// If mm is not NULL, the chunks memory will be added to the mm's memory cgroup. -// -// If a CPU chunk allocation succeeds, NV_OK is returned. If new_chunk is not -// NULL it will be set to point to the newly allocated chunk. On failure, -// NV_ERR_NO_MEMORY is returned. -NV_STATUS uvm_cpu_chunk_alloc(uvm_va_block_t *va_block, - uvm_page_index_t page_index, - struct mm_struct *mm, +// If a CPU chunk allocation succeeds, NV_OK is returned. new_chunk will be set +// to point to the newly allocated chunk. On failure, NV_ERR_NO_MEMORY is +// returned. +NV_STATUS uvm_cpu_chunk_alloc(uvm_chunk_size_t alloc_size, + uvm_cpu_chunk_alloc_flags_t flags, uvm_cpu_chunk_t **new_chunk); -// Insert a CPU chunk in the va_block's storage structures. +// Allocate a HMM CPU chunk. // -// On success, NV_OK is returned. On error, -// - NV_ERR_NO_MEMORY is returned if memory allocation for any if the internal -// structures did not succeed. -// - NV_ERR_INVALID_ARGUMENT is returned if the size of the chunk to be inserted -// in invalid. -// - NV_ERR_INVALID_STATE is returned if a matching chunk already exists in the -// block. -NV_STATUS uvm_cpu_chunk_insert_in_block(uvm_va_block_t *va_block, uvm_cpu_chunk_t *chunk, uvm_page_index_t page_index); - -// Remove a CPU chunk from the va_block's storage structures. -// The chunk is not freed, only removed from the block's storage structures. -void uvm_cpu_chunk_remove_from_block(uvm_va_block_t *va_block, uvm_cpu_chunk_t *chunk, uvm_page_index_t page_index); - -// Return the CPU chunk backing page_index within the VA block. -// If page_index is beyond the boundary of the VA block or a CPU chunk for -// the specified page has not been allocated and/or inserted into the block, -// NULL is returned. -uvm_cpu_chunk_t *uvm_cpu_chunk_get_chunk_for_page(uvm_va_block_t *block, uvm_page_index_t page_index); +// HMM chunks differ from normal CPU chunks in that the kernel has already +// allocated the page for them. This means we don't allocate any CPU memory +// here. It also means the kernel holds the reference to the page, so we +// shouldn't call put_page() when freeing the chunk. +// +// If a CPU chunk allocation succeeds NV_OK is returned and new_chunk will be +// set to point to the newly allocated chunk. On failure, NV_ERR_NO_MEMORY is +// returned. +// +// Note that the kernel retains logical ownership of the page. This means page +// properties should not be directly modified by UVM. In particular page flags +// such as PageDirty should not be modified by UVM, nor can UVM directly free +// the page. The kernel is also responsible for mapping/unmapping the page on +// the CPU. We create a CPU chunk for the page primarily to allow GPU mappings +// for the page to be created. +NV_STATUS uvm_cpu_chunk_alloc_hmm(struct page *page, + uvm_cpu_chunk_t **new_chunk); + +// Convert a physical chunk to an HMM chunk. +static void uvm_cpu_chunk_make_hmm(uvm_cpu_chunk_t *chunk) +{ + UVM_ASSERT(chunk->type == UVM_CPU_CHUNK_TYPE_PHYSICAL); + + chunk->type = UVM_CPU_CHUNK_TYPE_HMM; +} uvm_chunk_size_t uvm_cpu_chunk_get_size(uvm_cpu_chunk_t *chunk); @@ -313,157 +348,104 @@ return uvm_cpu_chunk_get_size(chunk) / PAGE_SIZE; } -static bool uvm_cpu_chunk_is_physical(uvm_cpu_chunk_t *chunk) +static inline bool uvm_cpu_chunk_is_hmm(uvm_cpu_chunk_t *chunk) { -#if UVM_CPU_CHUNK_SIZE_IS_PAGE_SIZE() - return true; -#else - return chunk->parent == NULL; -#endif + return chunk->type == UVM_CPU_CHUNK_TYPE_HMM; } -// Return a pointer to the struct page backing page_index within the owning -// VA block. -struct page *uvm_cpu_chunk_get_cpu_page(uvm_va_block_t *va_block, uvm_cpu_chunk_t *chunk, uvm_page_index_t page_index); - -// Take a reference to the CPU chunk. -void uvm_cpu_chunk_get(uvm_cpu_chunk_t *chunk); - -// Release a reference to the CPU chunk. When the reference count -// drops to zero, the CPU chunk will be freed. Physical CPU chunks -// will also free the CPU pages backing the chunk. -void uvm_cpu_chunk_put(uvm_cpu_chunk_t *chunk); - -NV_STATUS uvm_cpu_chunk_gpu_mapping_alloc(uvm_va_block_t *va_block, uvm_gpu_id_t id); -void uvm_cpu_chunk_gpu_mapping_split(uvm_va_block_t *existing, uvm_va_block_t *new, uvm_gpu_id_t id); -void uvm_cpu_chunk_gpu_mapping_free(uvm_va_block_t *va_block, uvm_gpu_id_t id); - -// Set the CPU chunk's DMA mapping address for the specified GPU ID. -NV_STATUS uvm_cpu_chunk_set_gpu_mapping_addr(uvm_va_block_t *va_block, - uvm_page_index_t page_index, - uvm_cpu_chunk_t *chunk, - uvm_gpu_id_t id, - NvU64 dma_addr); - -// Get the CPU chunk's DMA mapping address for the specified GPU ID. -NvU64 uvm_cpu_chunk_get_gpu_mapping_addr(uvm_va_block_t *block, - uvm_page_index_t page_index, - uvm_cpu_chunk_t *chunk, - uvm_gpu_id_t id); - -#if !UVM_CPU_CHUNK_SIZE_IS_PAGE_SIZE() -// Split a CPU chunk into a set of CPU chunks of size new_size. -// new_size has to be one of the supported CPU chunk allocation sizes and has to -// be smaller than the current size of chunk. -// -// On success, NV_OK is returned. On failure NV_ERR_NO_MEMORY will be returned. -NV_STATUS uvm_cpu_chunk_split(uvm_va_block_t *va_block, - uvm_cpu_chunk_t *chunk, - uvm_chunk_size_t new_size, - uvm_page_index_t page_index, - uvm_cpu_chunk_t **new_chunks); - -// Merge chunks to merge_size. -// -// All input chunks must have the same parent and size. If not, -// NV_ERR_INVALID_ARGUMENT is returned. -// -// If a merge cannot be done, NV_WARN_NOTHING_TO_DO is returned. -// -// On success, NV_OK is returned and merged_chunk is set to point to the -// merged chunk. -NV_STATUS uvm_cpu_chunk_merge(uvm_va_block_t *va_block, - uvm_cpu_chunk_t **chunks, - size_t num_merge_chunks, - uvm_chunk_size_t merge_size, - uvm_cpu_chunk_t **merged_chunk); - -// Mark the CPU sub-page page_index in the CPU chunk as dirty. -// page_index has to be a page withing the chunk's region. -void uvm_cpu_chunk_mark_dirty(uvm_cpu_chunk_t *chunk, uvm_page_index_t page_index); - -// Mark the CPU sub-pages page_index in the CPU chunk as clean. -// page_index has to be a page withing the chunk's region. -void uvm_cpu_chunk_mark_clean(uvm_cpu_chunk_t *chunk, uvm_page_index_t page_index); - -// Return true if the CPU sub-pages page_index in the CPU chunk are dirty. -// page_index has to be a page withing the chunk's region. -bool uvm_cpu_chunk_is_dirty(uvm_cpu_chunk_t *chunk, uvm_page_index_t page_index); - -#else // UVM_CPU_CHUNK_SIZE_IS_PAGE_SIZE() - -static NV_STATUS uvm_cpu_chunk_split(uvm_va_block_t *va_block, - uvm_cpu_chunk_t *chunk, - uvm_chunk_size_t new_size, - uvm_page_index_t page_index, - uvm_cpu_chunk_t **new_chunks) +static bool uvm_cpu_chunk_is_physical(uvm_cpu_chunk_t *chunk) { - return NV_OK; + return (chunk->type == UVM_CPU_CHUNK_TYPE_PHYSICAL || uvm_cpu_chunk_is_hmm(chunk)); } -static NV_STATUS uvm_cpu_chunk_merge(uvm_va_block_t *va_block, - uvm_cpu_chunk_t **chunk, - size_t num_merge_chunks, - uvm_chunk_size_t merge_size, - uvm_cpu_chunk_t **merged_chunk) +static bool uvm_cpu_chunk_is_logical(uvm_cpu_chunk_t *chunk) { - return NV_WARN_NOTHING_TO_DO; + return chunk->type == UVM_CPU_CHUNK_TYPE_LOGICAL; } -static void uvm_cpu_chunk_mark_dirty(uvm_cpu_chunk_t *chunk, uvm_page_index_t page_index) +static uvm_cpu_physical_chunk_t *uvm_cpu_chunk_to_physical(uvm_cpu_chunk_t *chunk) { - SetPageDirty(chunk); + UVM_ASSERT(uvm_cpu_chunk_is_physical(chunk)); + return container_of((chunk), uvm_cpu_physical_chunk_t, common); } -static void uvm_cpu_chunk_mark_clean(uvm_cpu_chunk_t *chunk, uvm_page_index_t page_index) +static uvm_cpu_logical_chunk_t *uvm_cpu_chunk_to_logical(uvm_cpu_chunk_t *chunk) { - ClearPageDirty(chunk); + UVM_ASSERT(uvm_cpu_chunk_is_logical(chunk)); + return container_of((chunk), uvm_cpu_logical_chunk_t, common); } -static bool uvm_cpu_chunk_is_dirty(uvm_cpu_chunk_t *chunk, uvm_page_index_t page_index) -{ - return PageDirty(chunk); -} -#endif // !UVM_CPU_CHUNK_SIZE_IS_PAGE_SIZE() +// Free a CPU chunk. +// This may not result in the immediate freeing of the physical pages of the +// chunk if this is a logical chunk and there are other logical chunks holding +// references to the physical chunk. +// If any DMA mappings to this chunk are still active, they are implicitly +// destroyed. +void uvm_cpu_chunk_free(uvm_cpu_chunk_t *chunk); -// Return the first CPU chunk in the block. If no CPU chunks have been -// allocated and/or inserted into the block, NULL is returned. -// If not NULL, page_index will be set to the first page of the block covered by -// the returned chunk. -uvm_cpu_chunk_t *uvm_cpu_chunk_first_in_block(uvm_va_block_t *va_block, uvm_page_index_t *out_page_index); +// In some configurations such as SR-IOV heavy, a CPU chunk cannot be +// referenced using its physical address. There needs to be a kernel virtual +// mapping created. +// +// This helper function creates a DMA mapping on the GPU (see +// uvm_cpu_chunk_map_gpu()) and if necessary a kernel virtual mapping for the +// chunk. The virtual mapping persists until GPU deinitialization, such that no +// unmap functionality is exposed. For more details see uvm_mmu_sysmem_map(). +// +// Note that unlike uvm_cpu_chunk_map_gpu(), this helper requires the GPU +// object instead of the parent GPU object. +NV_STATUS uvm_cpu_chunk_map_gpu(uvm_cpu_chunk_t *chunk, uvm_gpu_t *gpu); -// Return the next CPU chunk in the block owning chunk. -// previous_page_index is the index after which to start searching. Its value -// will be updated with the starting page index of the next chunk in the block. -uvm_cpu_chunk_t *uvm_cpu_chunk_next(uvm_va_block_t *va_block, uvm_page_index_t *previous_page_index); +// Destroy a CPU chunk's DMA mapping for the parent GPU. +// If chunk is a logical chunk, this call may not necessary destroy the DMA +// mapping of the parent physical chunk since all logical chunks share the +// parent's DMA mapping. +void uvm_cpu_chunk_unmap_gpu_phys(uvm_cpu_chunk_t *chunk, uvm_parent_gpu_t *parent_gpu); -#define for_each_cpu_chunk_in_block(chunk, page_index, va_block) \ - for ((chunk) = uvm_cpu_chunk_first_in_block((va_block), &(page_index)); \ - (chunk) != NULL; \ - (page_index) += uvm_cpu_chunk_num_pages(chunk) - 1, (chunk) = uvm_cpu_chunk_next((va_block), &(page_index))) +// Get the CPU chunk's DMA mapping address for the specified GPU ID. +// If there is no mapping for the GPU, 0 is returned. +NvU64 uvm_cpu_chunk_get_gpu_phys_addr(uvm_cpu_chunk_t *chunk, uvm_parent_gpu_t *parent_gpu); -#define for_each_cpu_chunk_in_block_safe(chunk, page_index, next_page_index, va_block) \ - for ((chunk) = uvm_cpu_chunk_first_in_block((va_block), &(page_index)), \ - (next_page_index) = (page_index) + ((chunk) ? uvm_cpu_chunk_num_pages(chunk) : 0); \ - (chunk) != NULL; \ - (page_index) = (next_page_index) - 1, (chunk) = uvm_cpu_chunk_next((va_block), &(page_index)), \ - (next_page_index) = (page_index) + ((chunk) ? uvm_cpu_chunk_num_pages(chunk) : 0)) +// Split a CPU chunk into a set of CPU chunks of the next size down from the set +// of enabled CPU chunk sizes. +// +// This function expects that the chunk to be split is larger than the minimum +// enabled chunk size and that new_chunks has enough space for all chunks +// resulting from the split. +// +// On success, NV_OK is returned and the caller-provided new_chunks array will +// be filled out with the newly-created logical chunks. +// +// After a successfull split, the input chunk can no longer be used. +// +// On failure NV_ERR_NO_MEMORY will be returned. +// +// Should never be called for HMM chunks as these don't need splitting (they can +// only be PAGE_SIZE) and even if larger chunks could exist UVM could not split +// them without kernel interaction which currently isn't exported. Will return +// NV_ERR_INVALID_ARGUMENT for a HMM chunk. +// TODO: Bug 3368756: add support for transparent huge page (THP) +NV_STATUS uvm_cpu_chunk_split(uvm_cpu_chunk_t *chunk, uvm_cpu_chunk_t **new_chunks); + +// Merge an array of logical chunks into their parent chunk. All chunks have to +// have the same size, parent, and set of mapped GPUs. +uvm_cpu_chunk_t *uvm_cpu_chunk_merge(uvm_cpu_chunk_t **chunks); + +// Mark the page_index sub-page of the chunk as dirty. +// page_index is an offset into the chunk. +// +// Note that dirty status for HMM chunks should not be modified directly from +// UVM. Instead the kernel will mark the backing struct pages dirty either on +// fault when written to from the CPU, or when the PTE is mirrored to the GPU +// using hmm_range_fault(). +void uvm_cpu_chunk_mark_dirty(uvm_cpu_chunk_t *chunk, uvm_page_index_t page_index); -// Use a special symbol for the region so it does not replace the chunk's region -// structure member. -#define for_each_cpu_chunk_in_block_region(chunk, page_index, va_block, __region) \ - for ((page_index) = uvm_va_block_first_page_in_mask((__region), &(va_block)->cpu.allocated), \ - (chunk) = uvm_cpu_chunk_get_chunk_for_page((va_block), (page_index)); \ - (chunk) != NULL && page_index < (__region).outer; \ - (page_index) += uvm_cpu_chunk_num_pages(chunk) - 1, (chunk) = uvm_cpu_chunk_next((va_block), &(page_index)) +// Mark the page_index sub-page of the chunk as clean. +// page_index is an offset into the chunk. +void uvm_cpu_chunk_mark_clean(uvm_cpu_chunk_t *chunk, uvm_page_index_t page_index); -#define for_each_cpu_chunk_in_block_region_safe(chunk, page_index, next_page_index, va_block, __region) \ - for ((page_index) = uvm_va_block_first_page_in_mask((__region), &(va_block)->cpu.allocated), \ - (chunk) = uvm_cpu_chunk_get_chunk_for_page((va_block), (page_index)), \ - (next_page_index) = (page_index) + (chunk ? uvm_cpu_chunk_num_pages(chunk) : 0); \ - (chunk) != NULL && page_index < (__region).outer; \ - (page_index) = (next_page_index) - 1, (chunk) = uvm_cpu_chunk_next((va_block), &(page_index)), \ - (next_page_index) = (page_index) + (chunk ? uvm_cpu_chunk_num_pages(chunk) : 0)) +// Return true if the page_index base page of the CPU chunk is dirty. +bool uvm_cpu_chunk_is_dirty(uvm_cpu_chunk_t *chunk, uvm_page_index_t page_index); static NV_STATUS uvm_test_get_cpu_chunk_allocation_sizes(UVM_TEST_GET_CPU_CHUNK_ALLOC_SIZES_PARAMS *params, struct file *filp) diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/kernel-open/nvidia-uvm/uvm_pmm_sysmem_test.c nvidia-open-gpu-kernel-modules-535.161.08/kernel-open/nvidia-uvm/uvm_pmm_sysmem_test.c --- nvidia-open-gpu-kernel-modules-525.147.05/kernel-open/nvidia-uvm/uvm_pmm_sysmem_test.c 2023-10-25 20:33:43.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/kernel-open/nvidia-uvm/uvm_pmm_sysmem_test.c 2024-03-05 22:26:06.000000000 +0000 @@ -30,6 +30,10 @@ #include "uvm_va_block.h" #include "uvm_va_range.h" #include "uvm_va_space.h" +#include "uvm_kvmalloc.h" +#include "uvm_hal.h" +#include "uvm_push.h" +#include "uvm_processors.h" // Pre-allocated array used for dma-to-virt translations static uvm_reverse_map_t g_sysmem_translations[PAGES_PER_UVM_VA_BLOCK]; @@ -576,3 +580,634 @@ return status; } + +static NV_STATUS cpu_chunk_map_on_cpu(uvm_cpu_chunk_t *chunk, void **cpu_addr) +{ + struct page **pages; + uvm_chunk_size_t chunk_size = uvm_cpu_chunk_get_size(chunk); + size_t num_pages = uvm_cpu_chunk_num_pages(chunk); + NV_STATUS status = NV_OK; + + UVM_ASSERT(cpu_addr); + + // Map the CPU chunk on the CPU. + if (chunk_size > PAGE_SIZE) { + size_t i; + + pages = uvm_kvmalloc(num_pages * sizeof(*pages)); + if (!pages) + return NV_ERR_NO_MEMORY; + + for (i = 0; i < num_pages; i++) + pages[i] = chunk->page + i; + } + else { + pages = &chunk->page; + } + + *cpu_addr = vmap(pages, num_pages, VM_MAP, PAGE_KERNEL); + if (!*cpu_addr) + status = NV_ERR_NO_MEMORY; + + if (chunk_size > PAGE_SIZE) + uvm_kvfree(pages); + + return status; +} + +static NV_STATUS test_cpu_chunk_mapping_access(uvm_cpu_chunk_t *chunk, uvm_gpu_t *gpu) +{ + NvU64 dma_addr; + uvm_gpu_address_t gpu_addr; + uvm_push_t push; + NvU32 *cpu_addr; + uvm_chunk_size_t chunk_size = uvm_cpu_chunk_get_size(chunk); + size_t i; + NV_STATUS status = NV_OK; + + TEST_NV_CHECK_RET(cpu_chunk_map_on_cpu(chunk, (void **)&cpu_addr)); + memset(cpu_addr, 0, chunk_size); + + dma_addr = uvm_cpu_chunk_get_gpu_phys_addr(chunk, gpu->parent); + gpu_addr = uvm_gpu_address_copy(gpu, uvm_gpu_phys_address(UVM_APERTURE_SYS, dma_addr)); + + TEST_NV_CHECK_GOTO(uvm_push_begin_acquire(gpu->channel_manager, + UVM_CHANNEL_TYPE_GPU_TO_CPU, + NULL, + &push, + "GPU -> CPU {%s, %llx} %u bytes", + uvm_gpu_address_aperture_string(gpu_addr), + gpu_addr.address, + chunk_size), + done); + gpu->parent->ce_hal->memset_4(&push, gpu_addr, 0xdeadc0de, chunk_size); + TEST_NV_CHECK_GOTO(uvm_push_end_and_wait(&push), done); + + for (i = 0; i < chunk_size / sizeof(*cpu_addr); i++) { + if (cpu_addr[i] != 0xdeadc0de) { + UVM_TEST_PRINT("GPU write of {%s, 0x%llx} %u bytes expected pattern 0x%08x, but offset %zu is 0x%08x\n", + uvm_gpu_address_aperture_string(gpu_addr), + gpu_addr.address, + chunk_size, + 0xdeadc0de, + i * sizeof(*cpu_addr), + cpu_addr[i]); + status = NV_ERR_INVALID_STATE; + break; + } + } + +done: + vunmap(cpu_addr); + return status; +} + +static NV_STATUS test_cpu_chunk_alloc(uvm_chunk_size_t size, + uvm_cpu_chunk_alloc_flags_t flags, + uvm_cpu_chunk_t **out_chunk) +{ + uvm_cpu_chunk_t *chunk; + NV_STATUS status = NV_OK; + size_t i; + + UVM_ASSERT(out_chunk); + + // It is possible that the allocation fails due to lack of large pages + // rather than an API issue, which will result in a false negative. + // However, that should be very rare. + TEST_NV_CHECK_RET(uvm_cpu_chunk_alloc(size, flags, &chunk)); + + // Check general state of the chunk: + // - chunk should be a physical chunk, + // - chunk should have the correct size, + // - chunk should have the correct number of base pages, and + TEST_CHECK_GOTO(uvm_cpu_chunk_is_physical(chunk), done); + TEST_CHECK_GOTO(uvm_cpu_chunk_get_size(chunk) == size, done); + TEST_CHECK_GOTO(uvm_cpu_chunk_num_pages(chunk) == size / PAGE_SIZE, done); + + if (flags & UVM_CPU_CHUNK_ALLOC_FLAGS_ZERO) { + NvU64 *cpu_addr; + + TEST_NV_CHECK_GOTO(cpu_chunk_map_on_cpu(chunk, (void **)&cpu_addr), done); + for (i = 0; i < size / sizeof(*cpu_addr); i++) + TEST_CHECK_GOTO(cpu_addr[i] == 0, done); + vunmap(cpu_addr); + } + + for (i = 0; i < size / PAGE_SIZE; i++) { + if (flags & UVM_CPU_CHUNK_ALLOC_FLAGS_ZERO) + TEST_CHECK_GOTO(uvm_cpu_chunk_is_dirty(chunk, i), done); + else + TEST_CHECK_GOTO(!uvm_cpu_chunk_is_dirty(chunk, i), done); + } + +done: + if (status == NV_OK) + *out_chunk = chunk; + else + uvm_cpu_chunk_free(chunk); + + return status; +} + +static NV_STATUS test_cpu_chunk_mapping_basic_verify(uvm_gpu_t *gpu, + uvm_cpu_chunk_alloc_flags_t flags, + uvm_chunk_size_t size) +{ + uvm_cpu_chunk_t *chunk; + uvm_cpu_physical_chunk_t *phys_chunk; + NvU64 dma_addr; + NV_STATUS status = NV_OK; + + TEST_NV_CHECK_RET(test_cpu_chunk_alloc(size, flags, &chunk)); + phys_chunk = uvm_cpu_chunk_to_physical(chunk); + + // Check state of the physical chunk: + // - gpu_mappings.max_entries should be 1 (for the static entry), + // - gpu_mappings.dma_addrs_mask should be 0. + // - no GPU mapping address. + TEST_CHECK_GOTO(phys_chunk->gpu_mappings.max_entries == 1, done); + TEST_CHECK_GOTO(uvm_processor_mask_get_gpu_count(&phys_chunk->gpu_mappings.dma_addrs_mask) == 0, done); + TEST_CHECK_GOTO(uvm_cpu_chunk_get_gpu_phys_addr(chunk, gpu->parent) == 0, done); + TEST_NV_CHECK_GOTO(uvm_cpu_chunk_map_gpu(chunk, gpu), done); + + // Test basic access. + TEST_NV_CHECK_GOTO(test_cpu_chunk_mapping_access(chunk, gpu), done); + + // Test double map is harmless. + dma_addr = uvm_cpu_chunk_get_gpu_phys_addr(chunk, gpu->parent); + TEST_NV_CHECK_GOTO(uvm_cpu_chunk_map_gpu(chunk, gpu), done); + TEST_CHECK_GOTO(uvm_cpu_chunk_get_gpu_phys_addr(chunk, gpu->parent) == dma_addr, done); + TEST_NV_CHECK_GOTO(test_cpu_chunk_mapping_access(chunk, gpu), done); + + // Test unmap, remap. + uvm_cpu_chunk_unmap_gpu_phys(chunk, gpu->parent); + TEST_CHECK_GOTO(uvm_cpu_chunk_get_gpu_phys_addr(chunk, gpu->parent) == 0, done); + TEST_NV_CHECK_GOTO(uvm_cpu_chunk_map_gpu(chunk, gpu), done); + TEST_NV_CHECK_GOTO(test_cpu_chunk_mapping_access(chunk, gpu), done); + +done: + // Test free with mapped GPUs still works. + uvm_cpu_chunk_free(chunk); + return status;; +} + +static NV_STATUS test_cpu_chunk_mapping_basic(uvm_gpu_t *gpu, uvm_cpu_chunk_alloc_flags_t flags) +{ + uvm_chunk_sizes_mask_t chunk_sizes = uvm_cpu_chunk_get_allocation_sizes(); + uvm_chunk_size_t size; + + for_each_chunk_size(size, chunk_sizes) + TEST_NV_CHECK_RET(test_cpu_chunk_mapping_basic_verify(gpu, flags, size)); + + return NV_OK; +} + +static NV_STATUS test_cpu_chunk_mapping_array(uvm_gpu_t *gpu1, uvm_gpu_t *gpu2, uvm_gpu_t *gpu3) +{ + NV_STATUS status = NV_OK; + uvm_cpu_chunk_t *chunk; + uvm_cpu_physical_chunk_t *phys_chunk; + NvU64 dma_addr_gpu2; + + TEST_NV_CHECK_RET(test_cpu_chunk_alloc(PAGE_SIZE, UVM_CPU_CHUNK_ALLOC_FLAGS_NONE, &chunk)); + phys_chunk = uvm_cpu_chunk_to_physical(chunk); + + TEST_NV_CHECK_GOTO(uvm_cpu_chunk_map_gpu(chunk, gpu2), done); + TEST_NV_CHECK_GOTO(test_cpu_chunk_mapping_access(chunk, gpu2), done); + TEST_NV_CHECK_GOTO(uvm_cpu_chunk_map_gpu(chunk, gpu3), done); + TEST_NV_CHECK_GOTO(test_cpu_chunk_mapping_access(chunk, gpu2), done); + TEST_NV_CHECK_GOTO(test_cpu_chunk_mapping_access(chunk, gpu3), done); + dma_addr_gpu2 = uvm_cpu_chunk_get_gpu_phys_addr(chunk, gpu2->parent); + uvm_cpu_chunk_unmap_gpu_phys(chunk, gpu3->parent); + TEST_NV_CHECK_GOTO(test_cpu_chunk_mapping_access(chunk, gpu2), done); + TEST_NV_CHECK_GOTO(uvm_cpu_chunk_map_gpu(chunk, gpu1), done); + TEST_NV_CHECK_GOTO(test_cpu_chunk_mapping_access(chunk, gpu1), done); + TEST_NV_CHECK_GOTO(test_cpu_chunk_mapping_access(chunk, gpu2), done); + + // DMA mapping addresses for different GPUs live in different IOMMU spaces, + // so it would be perfectly legal for them to have the same IOVA, and even + // if they lived in the same space we freed GPU3's address so it would be + // available for reuse. + // What we need to ensure is that GPU2's address didn't change after we map + // GPU1. It's true that we may get a false negative if both addresses + // happened to alias and we had a bug in how the addresses are shifted in + // the dense array, but that's better than intermittent failure. + TEST_CHECK_GOTO(uvm_cpu_chunk_get_gpu_phys_addr(chunk, gpu2->parent) == dma_addr_gpu2, done); + +done: + uvm_cpu_chunk_free(chunk); + return status; +} + +static NV_STATUS do_test_cpu_chunk_split_and_merge(uvm_cpu_chunk_t *chunk, uvm_gpu_t *gpu) +{ + NV_STATUS status = NV_OK; + uvm_chunk_size_t size = uvm_cpu_chunk_get_size(chunk); + uvm_chunk_sizes_mask_t alloc_sizes = uvm_cpu_chunk_get_allocation_sizes(); + size_t num_split_chunks; + uvm_cpu_chunk_t **split_chunks; + uvm_cpu_chunk_t *merged_chunk; + uvm_chunk_size_t split_size; + NvU64 phys_dma_addr; + size_t map_chunk; + size_t i; + + split_size = uvm_chunk_find_prev_size(alloc_sizes, size); + UVM_ASSERT(split_size != UVM_CHUNK_SIZE_INVALID); + num_split_chunks = size / split_size; + split_chunks = uvm_kvmalloc_zero(num_split_chunks * sizeof(*split_chunks)); + + if (!split_chunks) + return NV_ERR_NO_MEMORY; + + TEST_NV_CHECK_GOTO(uvm_cpu_chunk_map_gpu(chunk, gpu), done_free); + TEST_NV_CHECK_GOTO(test_cpu_chunk_mapping_access(chunk, gpu), done_free); + uvm_cpu_chunk_unmap_gpu_phys(chunk, gpu->parent); + + TEST_NV_CHECK_GOTO(uvm_cpu_chunk_split(chunk, split_chunks), done_free); + TEST_CHECK_GOTO(nv_kref_read(&chunk->refcount) == num_split_chunks, done); + + for (i = 0; i < num_split_chunks; i++) { + TEST_CHECK_GOTO(split_chunks[i], done); + TEST_CHECK_GOTO(uvm_cpu_chunk_is_logical(split_chunks[i]), done); + TEST_CHECK_GOTO(uvm_cpu_chunk_get_size(split_chunks[i]) == split_size, done); + TEST_NV_CHECK_GOTO(uvm_cpu_chunk_map_gpu(split_chunks[i], gpu), done); + TEST_NV_CHECK_GOTO(test_cpu_chunk_mapping_access(split_chunks[i], gpu), done); + } + + // Test CPU chunk merging. + merged_chunk = uvm_cpu_chunk_merge(split_chunks); + TEST_CHECK_GOTO(uvm_cpu_chunk_get_size(merged_chunk) == size, done_free); + TEST_CHECK_GOTO(merged_chunk == chunk, done_free); + + // Since all logical chunks were mapped, the entire merged chunk should + // be accessible without needing to map it. + TEST_NV_CHECK_GOTO(test_cpu_chunk_mapping_access(merged_chunk, gpu), done_free); + + // Test that GPU mappings are transferred after a split + phys_dma_addr = uvm_cpu_chunk_get_gpu_phys_addr(chunk, gpu->parent); + + TEST_NV_CHECK_GOTO(uvm_cpu_chunk_split(chunk, split_chunks), done_free); + + for (i = 0; i < num_split_chunks; i++) { + NvU64 dma_addr; + + TEST_NV_CHECK_GOTO(test_cpu_chunk_mapping_access(split_chunks[i], gpu), done); + dma_addr = uvm_cpu_chunk_get_gpu_phys_addr(split_chunks[i], gpu->parent); + TEST_CHECK_GOTO(dma_addr == phys_dma_addr + (i * split_size), done); + uvm_cpu_chunk_unmap_gpu_phys(split_chunks[i], gpu->parent); + } + + // Test that mapping one logical chunk does not affect others. + map_chunk = num_split_chunks / 2; + TEST_NV_CHECK_GOTO(uvm_cpu_chunk_map_gpu(split_chunks[map_chunk], gpu), done); + TEST_NV_CHECK_GOTO(test_cpu_chunk_mapping_access(split_chunks[map_chunk], gpu), done); + + for (i = 0; i < num_split_chunks; i++) { + if (i != map_chunk) + TEST_CHECK_GOTO(uvm_cpu_chunk_get_gpu_phys_addr(split_chunks[i], gpu->parent) == 0, done); + } + + if (split_size > PAGE_SIZE) { + for (i = 0; i < num_split_chunks; i++) + TEST_NV_CHECK_GOTO(do_test_cpu_chunk_split_and_merge(split_chunks[i], gpu), done); + } + + // Map all chunks before merging. + for (i = 0; i < num_split_chunks; i++) + TEST_NV_CHECK_GOTO(uvm_cpu_chunk_map_gpu(split_chunks[i], gpu), done); + + // Test CPU chunk merging. + merged_chunk = uvm_cpu_chunk_merge(split_chunks); + + // At this point, all split chunks have been merged. + num_split_chunks = 0; + + TEST_CHECK_GOTO(uvm_cpu_chunk_get_size(merged_chunk) == size, done_free); + TEST_CHECK_GOTO(merged_chunk == chunk, done_free); + + // Since all logical chunks were mapped, the entire merged chunk should + // be accessible without needing to map it. + TEST_NV_CHECK_GOTO(test_cpu_chunk_mapping_access(merged_chunk, gpu), done_free); + +done: + for (i = 0; i < num_split_chunks; i++) + uvm_cpu_chunk_free(split_chunks[i]); + +done_free: + uvm_kvfree(split_chunks); + + return status; +} + +static NV_STATUS test_cpu_chunk_split_and_merge(uvm_gpu_t *gpu) +{ + uvm_chunk_sizes_mask_t alloc_sizes = uvm_cpu_chunk_get_allocation_sizes(); + uvm_chunk_size_t size; + + size = uvm_chunk_find_next_size(alloc_sizes, PAGE_SIZE); + for_each_chunk_size_from(size, alloc_sizes) { + uvm_cpu_chunk_t *chunk; + NV_STATUS status; + + TEST_NV_CHECK_RET(test_cpu_chunk_alloc(size, UVM_CPU_CHUNK_ALLOC_FLAGS_NONE, &chunk)); + status = do_test_cpu_chunk_split_and_merge(chunk, gpu); + uvm_cpu_chunk_free(chunk); + + if (status != NV_OK) + return status; + } + + return NV_OK; +} + +static NV_STATUS test_cpu_chunk_dirty_split(uvm_cpu_chunk_t *chunk) +{ + uvm_chunk_size_t size = uvm_cpu_chunk_get_size(chunk); + uvm_chunk_size_t split_size; + uvm_chunk_sizes_mask_t alloc_sizes = uvm_cpu_chunk_get_allocation_sizes(); + uvm_cpu_chunk_t **split_chunks; + uvm_cpu_chunk_t *merged_chunk; + size_t num_pages = size / PAGE_SIZE; + size_t num_split_chunks; + size_t num_split_chunk_pages; + size_t i; + NV_STATUS status = NV_OK; + + split_size = uvm_chunk_find_prev_size(alloc_sizes, size); + UVM_ASSERT(split_size != UVM_CHUNK_SIZE_INVALID); + num_split_chunks = size / split_size; + num_split_chunk_pages = split_size / PAGE_SIZE; + split_chunks = uvm_kvmalloc_zero(num_split_chunks * sizeof(*split_chunks)); + if (!split_chunks) + return NV_ERR_NO_MEMORY; + + TEST_NV_CHECK_GOTO(uvm_cpu_chunk_split(chunk, split_chunks), done_free); + + // The parent chunk had only the even pages set as dirty. Make sure + // that's still the case after the split. + for (i = 0; i < num_split_chunks; i++) { + uvm_page_index_t chunk_page; + + for (chunk_page = 0; chunk_page < num_split_chunk_pages; chunk_page++) { + if (((i * num_split_chunk_pages) + chunk_page) % 2) + TEST_CHECK_GOTO(!uvm_cpu_chunk_is_dirty(split_chunks[i], chunk_page), done); + else + TEST_CHECK_GOTO(uvm_cpu_chunk_is_dirty(split_chunks[i], chunk_page), done); + } + } + + if (split_size > PAGE_SIZE) { + for (i = 0; i < num_split_chunks; i++) + TEST_NV_CHECK_GOTO(test_cpu_chunk_dirty_split(split_chunks[i]), done); + } + + merged_chunk = uvm_cpu_chunk_merge(split_chunks); + num_split_chunks = 0; + for (i = 0; i < num_pages; i++) { + if (i % 2) + TEST_CHECK_GOTO(!uvm_cpu_chunk_is_dirty(merged_chunk, i), done_free); + else + TEST_CHECK_GOTO(uvm_cpu_chunk_is_dirty(merged_chunk, i), done_free); + } + +done: + for (i = 0; i < num_split_chunks; i++) + uvm_cpu_chunk_free(split_chunks[i]); + +done_free: + uvm_kvfree(split_chunks); + return status; +} + +static NV_STATUS test_cpu_chunk_dirty(uvm_gpu_t *gpu) +{ + NV_STATUS status = NV_OK; + uvm_cpu_chunk_t *chunk; + uvm_chunk_size_t size; + uvm_chunk_sizes_mask_t alloc_sizes = uvm_cpu_chunk_get_allocation_sizes(); + size_t i; + + for_each_chunk_size(size, alloc_sizes) { + uvm_cpu_physical_chunk_t *phys_chunk; + size_t num_pages; + + TEST_NV_CHECK_RET(test_cpu_chunk_alloc(size, UVM_CPU_CHUNK_ALLOC_FLAGS_NONE, &chunk)); + phys_chunk = uvm_cpu_chunk_to_physical(chunk); + num_pages = uvm_cpu_chunk_num_pages(chunk); + + for (i = 0; i < num_pages; i++) + TEST_CHECK_GOTO(!uvm_cpu_chunk_is_dirty(chunk, i), done); + + if (size > PAGE_SIZE) + TEST_CHECK_GOTO(bitmap_empty(phys_chunk->dirty_bitmap, num_pages), done); + + uvm_cpu_chunk_free(chunk); + + TEST_NV_CHECK_RET(test_cpu_chunk_alloc(size, UVM_CPU_CHUNK_ALLOC_FLAGS_ZERO, &chunk)); + phys_chunk = uvm_cpu_chunk_to_physical(chunk); + num_pages = uvm_cpu_chunk_num_pages(chunk); + + // Allocating the chunk with UVM_CPU_CHUNK_ALLOC_FLAGS_ZERO will set the + // entire chunk as dirty. + for (i = 0; i < num_pages; i++) + TEST_CHECK_GOTO(uvm_cpu_chunk_is_dirty(chunk, i), done); + + if (size > PAGE_SIZE) + TEST_CHECK_GOTO(bitmap_full(phys_chunk->dirty_bitmap, num_pages), done); + + // For chunks larger than PAGE_SIZE, marking individual pages in a + // physical chunk should not affect the entire chunk. + for (i = 0; i < num_pages; i++) { + uvm_cpu_chunk_mark_clean(chunk, i); + TEST_CHECK_GOTO(!uvm_cpu_chunk_is_dirty(chunk, i), done); + if (size > PAGE_SIZE) { + TEST_CHECK_GOTO(bitmap_empty(phys_chunk->dirty_bitmap, i + 1), done); + TEST_CHECK_GOTO(bitmap_weight(phys_chunk->dirty_bitmap, num_pages) == num_pages - (i + 1), done); + } + } + + for (i = 0; i < num_pages; i++) { + uvm_cpu_chunk_mark_dirty(chunk, i); + TEST_CHECK_GOTO(uvm_cpu_chunk_is_dirty(chunk, i), done); + if (size > PAGE_SIZE) { + TEST_CHECK_GOTO(bitmap_full(phys_chunk->dirty_bitmap, i + 1), done); + TEST_CHECK_GOTO(bitmap_weight(phys_chunk->dirty_bitmap, num_pages) == i + 1, done); + } + } + + // Leave only even pages as dirty + for (i = 1; i < num_pages; i += 2) + uvm_cpu_chunk_mark_clean(chunk, i); + + for (i = 0; i < num_pages; i++) { + if (i % 2) { + TEST_CHECK_GOTO(!uvm_cpu_chunk_is_dirty(chunk, i), done); + if (size > PAGE_SIZE) + TEST_CHECK_GOTO(!test_bit(i, phys_chunk->dirty_bitmap), done); + } + else { + TEST_CHECK_GOTO(uvm_cpu_chunk_is_dirty(chunk, i), done); + if (size > PAGE_SIZE) + TEST_CHECK_GOTO(test_bit(i, phys_chunk->dirty_bitmap), done); + } + } + + if (size > PAGE_SIZE) + TEST_NV_CHECK_GOTO(test_cpu_chunk_dirty_split(chunk), done); + +done: + uvm_cpu_chunk_free(chunk); + + if (status != NV_OK) + break; + } + + return status; +} + +NV_STATUS do_test_cpu_chunk_free(uvm_cpu_chunk_t *chunk, uvm_va_space_t *va_space, uvm_processor_mask_t *test_gpus) +{ + NV_STATUS status = NV_OK; + uvm_cpu_chunk_t **split_chunks; + uvm_chunk_sizes_mask_t alloc_sizes = uvm_cpu_chunk_get_allocation_sizes(); + size_t size = uvm_cpu_chunk_get_size(chunk); + uvm_chunk_size_t split_size = uvm_chunk_find_prev_size(alloc_sizes, size); + size_t num_split_chunks = size / split_size; + uvm_gpu_t *gpu; + size_t i; + size_t j; + + split_chunks = uvm_kvmalloc_zero(num_split_chunks * sizeof(*split_chunks)); + if (!split_chunks) { + UVM_TEST_PRINT("Failed to allocate split chunk array memory"); + status = NV_ERR_NO_MEMORY; + goto done_free; + } + + TEST_NV_CHECK_GOTO(uvm_cpu_chunk_split(chunk, split_chunks), done_free); + + // The caller does not free the input chunk. + // So, we have to do it in this function. However, beyond this point + // the input chunk will be freed by freeing the split chunks. + chunk = NULL; + + // Map every other chunk. + // The call to uvm_cpu_chunk_unmap_gpu_phys() is here in case this is part + // of a double split (see below). In that case, the parent chunk would be + // either mapped or unmapped. + // + // If it is mapped, we have to unmap the subchunks in + // order for the mapping check below to succeed. If it is unmapped, the + // calls are noops. + for (i = 0; i < num_split_chunks; i++) { + for_each_va_space_gpu_in_mask(gpu, va_space, test_gpus) { + if (i & (1 << uvm_id_gpu_index(gpu->id))) + TEST_NV_CHECK_GOTO(uvm_cpu_chunk_map_gpu(split_chunks[i], gpu), done); + else + uvm_cpu_chunk_unmap_gpu_phys(split_chunks[i], gpu->parent); + } + } + + // Do a double split if we can + if (split_size > PAGE_SIZE) { + size_t chunk_to_be_resplit; + + // Test an even (mapped) chunk. + chunk_to_be_resplit = num_split_chunks / 2; + TEST_NV_CHECK_GOTO(do_test_cpu_chunk_free(split_chunks[chunk_to_be_resplit], va_space, test_gpus), done); + + // The chunk would have been freed by do_test_cpu_chunk_free(). + split_chunks[chunk_to_be_resplit] = NULL; + + // Test an odd (unmapped) chunk. + chunk_to_be_resplit += 1; + TEST_NV_CHECK_GOTO(do_test_cpu_chunk_free(split_chunks[chunk_to_be_resplit], va_space, test_gpus), done); + split_chunks[chunk_to_be_resplit] = NULL; + } + + for (i = 0; i < num_split_chunks; i++) { + if (!split_chunks[i]) + continue; + + uvm_cpu_chunk_free(split_chunks[i]); + split_chunks[i] = NULL; + + for (j = i + 1; j < num_split_chunks; j++) { + if (!split_chunks[j]) + continue; + + TEST_CHECK_GOTO(uvm_cpu_chunk_is_logical(split_chunks[j]), done); + TEST_CHECK_GOTO(uvm_cpu_chunk_get_size(split_chunks[j]) == split_size, done); + for_each_va_space_gpu_in_mask(gpu, va_space, test_gpus) { + if (j & (1 << uvm_id_gpu_index(gpu->id))) + TEST_CHECK_GOTO(uvm_cpu_chunk_get_gpu_phys_addr(split_chunks[j], gpu->parent), done); + else + TEST_CHECK_GOTO(!uvm_cpu_chunk_get_gpu_phys_addr(split_chunks[j], gpu->parent), done); + } + } + } + +done: + for (i = 0; i < num_split_chunks; i++) { + if (split_chunks[i]) + uvm_cpu_chunk_free(split_chunks[i]); + } + +done_free: + if (chunk) + uvm_cpu_chunk_free(chunk); + + uvm_kvfree(split_chunks); + return status; +} + +NV_STATUS test_cpu_chunk_free(uvm_va_space_t *va_space, uvm_processor_mask_t *test_gpus) +{ + uvm_cpu_chunk_t *chunk; + uvm_chunk_sizes_mask_t alloc_sizes = uvm_cpu_chunk_get_allocation_sizes(); + size_t size = uvm_chunk_find_next_size(alloc_sizes, PAGE_SIZE); + + for_each_chunk_size_from(size, alloc_sizes) { + TEST_NV_CHECK_RET(test_cpu_chunk_alloc(size, UVM_CPU_CHUNK_ALLOC_FLAGS_NONE, &chunk)); + TEST_NV_CHECK_RET(do_test_cpu_chunk_free(chunk, va_space, test_gpus)); + } + + return NV_OK; +} + +NV_STATUS uvm_test_cpu_chunk_api(UVM_TEST_CPU_CHUNK_API_PARAMS *params, struct file *filp) +{ + uvm_va_space_t *va_space = uvm_va_space_get(filp); + uvm_processor_mask_t test_gpus; + uvm_gpu_t *gpu; + NV_STATUS status = NV_OK; + + uvm_va_space_down_read(va_space); + uvm_processor_mask_and(&test_gpus, + &va_space->registered_gpus, + &va_space->accessible_from[uvm_id_value(UVM_ID_CPU)]); + + for_each_va_space_gpu_in_mask(gpu, va_space, &test_gpus) { + TEST_NV_CHECK_GOTO(test_cpu_chunk_mapping_basic(gpu, UVM_CPU_CHUNK_ALLOC_FLAGS_NONE), done); + TEST_NV_CHECK_GOTO(test_cpu_chunk_mapping_basic(gpu, UVM_CPU_CHUNK_ALLOC_FLAGS_ZERO), done); + TEST_NV_CHECK_GOTO(test_cpu_chunk_split_and_merge(gpu), done); + TEST_NV_CHECK_GOTO(test_cpu_chunk_dirty(gpu), done); + } + + TEST_NV_CHECK_GOTO(test_cpu_chunk_free(va_space, &test_gpus), done); + + if (uvm_processor_mask_get_gpu_count(&test_gpus) >= 3) { + uvm_gpu_t *gpu2, *gpu3; + + gpu = uvm_processor_mask_find_first_va_space_gpu(&test_gpus, va_space); + gpu2 = uvm_processor_mask_find_next_va_space_gpu(&test_gpus, va_space, gpu); + gpu3 = uvm_processor_mask_find_next_va_space_gpu(&test_gpus, va_space, gpu2); + TEST_NV_CHECK_GOTO(test_cpu_chunk_mapping_array(gpu, gpu2, gpu3), done); + } + +done: + uvm_va_space_up_read(va_space); + return status; +} diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/kernel-open/nvidia-uvm/uvm_pmm_test.c nvidia-open-gpu-kernel-modules-535.161.08/kernel-open/nvidia-uvm/uvm_pmm_test.c --- nvidia-open-gpu-kernel-modules-525.147.05/kernel-open/nvidia-uvm/uvm_pmm_test.c 2023-10-25 20:33:43.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/kernel-open/nvidia-uvm/uvm_pmm_test.c 2024-03-05 22:26:06.000000000 +0000 @@ -1,5 +1,5 @@ /******************************************************************************* - Copyright (c) 2015-2022 NVIDIA Corporation + Copyright (c) 2015-2023 NVIDIA Corporation Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation files (the "Software"), to @@ -100,6 +100,22 @@ // It is duplicated because we do not want to expose it as an API. static uvm_pmm_gpu_memory_type_t pmm_squash_memory_type(uvm_parent_gpu_t *parent_gpu, uvm_pmm_gpu_memory_type_t type) { + if (uvm_conf_computing_mode_enabled_parent(parent_gpu)) + return type; + + // Enforce the contract that when the Confidential Computing feature is + // disabled, all user types are alike, as well as all kernel types, + // respectively. See uvm_pmm_gpu_memory_type_t. + switch (type) { + case UVM_PMM_GPU_MEMORY_TYPE_USER: // Alias UVM_PMM_GPU_MEMORY_TYPE_USER_PROTECTED + case UVM_PMM_GPU_MEMORY_TYPE_USER_UNPROTECTED: + return UVM_PMM_GPU_MEMORY_TYPE_USER; + case UVM_PMM_GPU_MEMORY_TYPE_KERNEL: // Alias UVM_PMM_GPU_MEMORY_TYPE_KERNEL_PROTECTED + case UVM_PMM_GPU_MEMORY_TYPE_KERNEL_UNPROTECTED: + return UVM_PMM_GPU_MEMORY_TYPE_KERNEL; + default: + UVM_ASSERT(0); + } return type; } @@ -306,6 +322,13 @@ NvU32 *verif_cpu_addr = uvm_mem_get_cpu_addr_kernel(verif_mem); size_t i; + // TODO: Bug 3839176: [UVM][HCC][uvm_test] Update tests that assume GPU + // engines can directly access sysmem + // Skip this test for now. To enable this test in Confidential Computing, + // The GPU->CPU CE copy needs to be updated so it uses encryption when + // CC is enabled. + if (uvm_conf_computing_mode_enabled(gpu)) + return NV_OK; UVM_ASSERT(verif_mem->size >= size); memset(verif_cpu_addr, 0, size); @@ -341,6 +364,11 @@ return NV_OK; } +static uvm_gpu_address_t chunk_copy_addr(uvm_gpu_t *gpu, uvm_gpu_chunk_t *chunk) +{ + return uvm_gpu_address_copy(gpu, uvm_gpu_phys_address(UVM_APERTURE_VID, chunk->address)); +} + static NV_STATUS init_test_chunk(uvm_va_space_t *va_space, uvm_pmm_gpu_t *pmm, test_chunk_t *test_chunk, @@ -362,10 +390,7 @@ TEST_NV_CHECK_GOTO(uvm_mmu_chunk_map(test_chunk->chunk), chunk_free); - if (uvm_mmu_gpu_needs_static_vidmem_mapping(gpu) || uvm_mmu_gpu_needs_dynamic_vidmem_mapping(gpu)) - chunk_addr = uvm_gpu_address_virtual_from_vidmem_phys(gpu, test_chunk->chunk->address); - else - chunk_addr = uvm_gpu_address_physical(UVM_APERTURE_VID, test_chunk->chunk->address); + chunk_addr = chunk_copy_addr(gpu, test_chunk->chunk); // Fill the chunk TEST_NV_CHECK_GOTO(do_memset_4(gpu, chunk_addr, pattern, size, &test_chunk->tracker), chunk_unmap); @@ -407,15 +432,10 @@ { uvm_gpu_t *gpu = uvm_pmm_to_gpu(pmm); NV_STATUS status; - uvm_gpu_address_t chunk_addr; uvm_gpu_chunk_t *chunk = test_chunk->chunk; + uvm_gpu_address_t chunk_addr = chunk_copy_addr(gpu, chunk); uvm_chunk_size_t size = uvm_gpu_chunk_get_size(chunk); - if (uvm_mmu_gpu_needs_static_vidmem_mapping(gpu) || uvm_mmu_gpu_needs_dynamic_vidmem_mapping(gpu)) - chunk_addr = uvm_gpu_address_virtual_from_vidmem_phys(gpu, chunk->address); - else - chunk_addr = uvm_gpu_address_physical(UVM_APERTURE_VID, chunk->address); - status = gpu_mem_check(gpu, verif_mem, chunk_addr, size, test_chunk->pattern, &test_chunk->tracker); list_del(&test_chunk->node); @@ -511,7 +531,7 @@ if (mode == UvmTestPmmSanityModeBasic) { first_memory_type = UVM_PMM_GPU_MEMORY_TYPE_USER; - last_memory_type = UVM_PMM_GPU_MEMORY_TYPE_USER; + last_memory_type = UVM_PMM_GPU_MEMORY_TYPE_USER_UNPROTECTED; first_free_pattern = BASIC_TEST_FREE_PATTERN_EVERY_N; last_free_pattern = BASIC_TEST_FREE_PATTERN_EVERY_N; } @@ -867,6 +887,8 @@ uvm_pmm_gpu_memory_type_t last_user_mode = UVM_PMM_GPU_MEMORY_TYPE_USER; uvm_pmm_gpu_memory_type_t current_user_mode = first_user_mode; + last_user_mode = UVM_PMM_GPU_MEMORY_TYPE_USER_UNPROTECTED; + if (params->alloc_limit < -1) return NV_ERR_INVALID_ARGUMENT; @@ -1002,6 +1024,8 @@ uvm_pmm_gpu_memory_type_t last_user_mode = UVM_PMM_GPU_MEMORY_TYPE_USER; uvm_pmm_gpu_memory_type_t current_user_mode = first_user_mode; + last_user_mode = UVM_PMM_GPU_MEMORY_TYPE_USER_UNPROTECTED; + uvm_va_space_down_read(va_space); gpu = uvm_va_space_get_gpu_by_uuid(va_space, ¶ms->gpu_uuid); if (!gpu) { @@ -1199,8 +1223,6 @@ if (!chunks) return NV_ERR_NO_MEMORY; - UVM_ASSERT(!g_uvm_global.sev_enabled); - TEST_NV_CHECK_GOTO(uvm_mem_alloc_sysmem_and_map_cpu_kernel(UVM_CHUNK_SIZE_MAX, current->mm, &verif_mem), out); TEST_NV_CHECK_GOTO(uvm_mem_map_gpu_kernel(verif_mem, owning_gpu), out); TEST_NV_CHECK_GOTO(uvm_mem_map_gpu_kernel(verif_mem, accessing_gpu), out); @@ -1226,7 +1248,7 @@ } // Check that accessing_gpu can read and write - local_addr = uvm_gpu_address_physical(UVM_APERTURE_VID, chunks[0]->address); + local_addr = chunk_copy_addr(owning_gpu, chunks[0]); peer_addr = uvm_pmm_gpu_peer_copy_address(&owning_gpu->pmm, chunks[0], accessing_gpu); // Init on local GPU @@ -1391,7 +1413,7 @@ uvm_va_space_down_read(va_space); for_each_va_space_gpu(gpu, va_space) { - if (!gpu->parent->numa_info.enabled) + if (!gpu->mem_info.numa.enabled) continue; ran_test = true; diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/kernel-open/nvidia-uvm/uvm_policy.c nvidia-open-gpu-kernel-modules-535.161.08/kernel-open/nvidia-uvm/uvm_policy.c --- nvidia-open-gpu-kernel-modules-525.147.05/kernel-open/nvidia-uvm/uvm_policy.c 2023-10-25 20:33:39.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/kernel-open/nvidia-uvm/uvm_policy.c 2024-03-05 22:25:59.000000000 +0000 @@ -30,7 +30,7 @@ #include "uvm_gpu.h" #include "uvm_va_space_mm.h" -bool uvm_is_valid_vma_range(struct mm_struct *mm, NvU64 start, NvU64 length) +static bool uvm_is_valid_vma_range(struct mm_struct *mm, NvU64 start, NvU64 length) { const NvU64 end = start + length; struct vm_area_struct *vma; @@ -50,7 +50,7 @@ return false; } -NV_STATUS uvm_api_range_type_check(uvm_va_space_t *va_space, struct mm_struct *mm, NvU64 base, NvU64 length) +uvm_api_range_type_t uvm_api_range_type_check(uvm_va_space_t *va_space, struct mm_struct *mm, NvU64 base, NvU64 length) { uvm_va_range_t *va_range, *va_range_last; const NvU64 last_address = base + length - 1; @@ -61,21 +61,23 @@ uvm_assert_rwsem_locked(&va_space->lock); if (uvm_api_range_invalid(base, length)) - return NV_ERR_INVALID_ADDRESS; + return UVM_API_RANGE_TYPE_INVALID; // Check if passed interval overlaps with any VA range. if (uvm_va_space_range_empty(va_space, base, last_address)) { if (g_uvm_global.ats.enabled && uvm_va_space_pageable_mem_access_supported(va_space) && mm && - uvm_is_valid_vma_range(mm, base, length)) - return NV_WARN_NOTHING_TO_DO; - else if (uvm_hmm_is_enabled(va_space) && - mm && - uvm_is_valid_vma_range(mm, base, length)) - return NV_OK; - else - return NV_ERR_INVALID_ADDRESS; + uvm_is_valid_vma_range(mm, base, length)) { + + return UVM_API_RANGE_TYPE_ATS; + } + else if (uvm_hmm_is_enabled(va_space) && mm && uvm_is_valid_vma_range(mm, base, length)) { + return UVM_API_RANGE_TYPE_HMM; + } + else { + return UVM_API_RANGE_TYPE_INVALID; + } } va_range_last = NULL; @@ -86,10 +88,10 @@ // Check if passed interval overlaps with an unmanaged VA range, or a // sub-interval not tracked by a VA range if (!va_range_last || va_range_last->node.end < last_address) - return NV_ERR_INVALID_ADDRESS; + return UVM_API_RANGE_TYPE_INVALID; // Passed interval is fully covered by managed VA ranges - return NV_OK; + return UVM_API_RANGE_TYPE_MANAGED; } static NV_STATUS split_as_needed(uvm_va_space_t *va_space, @@ -141,7 +143,7 @@ return split_as_needed(va_space, end_addr, split_needed_cb, data); } -static bool preferred_location_is_split_needed(uvm_va_policy_t *policy, void *data) +static bool preferred_location_is_split_needed(const uvm_va_policy_t *policy, void *data) { uvm_processor_id_t processor_id; @@ -152,12 +154,13 @@ } static NV_STATUS preferred_location_unmap_remote_pages(uvm_va_block_t *va_block, - uvm_va_block_context_t *va_block_context) + uvm_va_block_context_t *va_block_context, + uvm_va_block_region_t region) { NV_STATUS status = NV_OK; NV_STATUS tracker_status; uvm_tracker_t local_tracker = UVM_TRACKER_INIT(); - uvm_va_policy_t *policy = va_block_context->policy; + const uvm_va_policy_t *policy = uvm_va_policy_get_region(va_block, region); uvm_processor_id_t preferred_location = policy->preferred_location; uvm_va_space_t *va_space = uvm_va_block_get_va_space(va_block); const uvm_page_mask_t *mapped_mask; @@ -185,7 +188,7 @@ status = uvm_va_block_unmap(va_block, va_block_context, preferred_location, - uvm_va_block_region_from_block(va_block), + region, &va_block_context->caller_page_mask, &local_tracker); @@ -200,17 +203,15 @@ } NV_STATUS uvm_va_block_set_preferred_location_locked(uvm_va_block_t *va_block, - uvm_va_block_context_t *va_block_context) + uvm_va_block_context_t *va_block_context, + uvm_va_block_region_t region) { uvm_assert_mutex_locked(&va_block->lock); - // TODO: Bug 1750144: remove this restriction when HMM handles setting - // the preferred location semantics instead of just recording the policy. - UVM_ASSERT(!uvm_va_block_is_hmm(va_block)); - UVM_ASSERT(va_block_context->policy == uvm_va_range_get_policy(va_block->va_range)); - uvm_va_block_mark_cpu_dirty(va_block); + if (!uvm_va_block_is_hmm(va_block)) + uvm_va_block_mark_cpu_dirty(va_block); - return preferred_location_unmap_remote_pages(va_block, va_block_context); + return preferred_location_unmap_remote_pages(va_block, va_block_context, region); } static NV_STATUS preferred_location_set(uvm_va_space_t *va_space, @@ -278,12 +279,15 @@ return NV_OK; } - return uvm_hmm_set_preferred_location(va_space, preferred_location, base, last_address); + if (!mm) + return NV_ERR_INVALID_ADDRESS; + + return uvm_hmm_set_preferred_location(va_space, preferred_location, base, last_address, out_tracker); } NV_STATUS uvm_api_set_preferred_location(const UVM_SET_PREFERRED_LOCATION_PARAMS *params, struct file *filp) { - NV_STATUS status; + NV_STATUS status = NV_OK; NV_STATUS tracker_status; uvm_tracker_t local_tracker = UVM_TRACKER_INIT(); uvm_va_space_t *va_space = uvm_va_space_get(filp); @@ -295,7 +299,7 @@ const NvU64 start = params->requestedBase; const NvU64 length = params->length; const NvU64 end = start + length - 1; - bool range_is_ats = false; + uvm_api_range_type_t type; UVM_ASSERT(va_space); @@ -303,13 +307,10 @@ uvm_va_space_down_write(va_space); has_va_space_write_lock = true; - status = uvm_api_range_type_check(va_space, mm, start, length); - if (status != NV_OK) { - if (status != NV_WARN_NOTHING_TO_DO) - goto done; - - status = NV_OK; - range_is_ats = true; + type = uvm_api_range_type_check(va_space, mm, start, length); + if (type == UVM_API_RANGE_TYPE_INVALID) { + status = NV_ERR_INVALID_ADDRESS; + goto done; } // If the CPU is the preferred location, we don't have to find the associated uvm_gpu_t @@ -334,10 +335,23 @@ UVM_ASSERT(status == NV_OK); - // TODO: Bug 2098544: On ATS systems, honor the preferred location policy - // for system memory ranges instead of ignoring it. - if (range_is_ats) + // UvmSetPreferredLocation on non-ATS regions targets the VA range of the + // associated file descriptor, not the calling process. Since + // UvmSetPreferredLocation on ATS regions are handled in userspace, + // implementing the non-ATS behavior is not possible. So, return an error + // instead. Although the out of process case can be supported for HMM, + // return an error to make the API behavior consistent for all SAM regions. + if ((type != UVM_API_RANGE_TYPE_MANAGED) && (current->mm != mm)) { + status = NV_ERR_NOT_SUPPORTED; goto done; + } + + // For ATS regions, let userspace handle it. + if (type == UVM_API_RANGE_TYPE_ATS) { + UVM_ASSERT(g_uvm_global.ats.enabled); + status = NV_WARN_NOTHING_TO_DO; + goto done; + } status = preferred_location_set(va_space, mm, start, length, preferred_location_id, &first_va_range_to_migrate, &local_tracker); if (status != NV_OK) @@ -385,19 +399,38 @@ uvm_va_space_t *va_space = uvm_va_space_get(filp); struct mm_struct *mm; uvm_tracker_t local_tracker = UVM_TRACKER_INIT(); + uvm_api_range_type_t type; UVM_ASSERT(va_space); mm = uvm_va_space_mm_or_current_retain_lock(va_space); uvm_va_space_down_write(va_space); - status = uvm_api_range_type_check(va_space, mm, params->requestedBase, params->length); + type = uvm_api_range_type_check(va_space, mm, params->requestedBase, params->length); + if (type == UVM_API_RANGE_TYPE_INVALID) { + status = NV_ERR_INVALID_ADDRESS; + goto done; + } - if (status == NV_OK) - status = preferred_location_set(va_space, mm, params->requestedBase, params->length, UVM_ID_INVALID, NULL, &local_tracker); - else if (status == NV_WARN_NOTHING_TO_DO) - status = NV_OK; + if ((type != UVM_API_RANGE_TYPE_MANAGED) && (current->mm != mm)) { + status = NV_ERR_NOT_SUPPORTED; + goto done; + } + + if (type == UVM_API_RANGE_TYPE_ATS) { + status = NV_WARN_NOTHING_TO_DO; + goto done; + } + + status = preferred_location_set(va_space, + mm, + params->requestedBase, + params->length, + UVM_ID_INVALID, + NULL, + &local_tracker); +done: tracker_status = uvm_tracker_wait_deinit(&local_tracker); uvm_va_space_up_write(va_space); @@ -405,10 +438,11 @@ return status == NV_OK ? tracker_status : status; } -static NV_STATUS va_block_set_accessed_by_locked(uvm_va_block_t *va_block, - uvm_va_block_context_t *va_block_context, - uvm_processor_id_t processor_id, - uvm_tracker_t *out_tracker) +NV_STATUS uvm_va_block_set_accessed_by_locked(uvm_va_block_t *va_block, + uvm_va_block_context_t *va_block_context, + uvm_processor_id_t processor_id, + uvm_va_block_region_t region, + uvm_tracker_t *out_tracker) { NV_STATUS status; NV_STATUS tracker_status; @@ -418,7 +452,7 @@ status = uvm_va_block_add_mappings(va_block, va_block_context, processor_id, - uvm_va_block_region_from_block(va_block), + region, NULL, UvmEventMapRemoteCausePolicy); @@ -432,22 +466,25 @@ uvm_processor_id_t processor_id) { uvm_va_space_t *va_space = uvm_va_block_get_va_space(va_block); + uvm_va_block_region_t region = uvm_va_block_region_from_block(va_block); NV_STATUS status; uvm_tracker_t local_tracker = UVM_TRACKER_INIT(); + uvm_va_policy_t *policy = uvm_va_range_get_policy(va_block->va_range); UVM_ASSERT(!uvm_va_block_is_hmm(va_block)); - UVM_ASSERT(va_block_context->policy == uvm_va_range_get_policy(va_block->va_range)); // Read duplication takes precedence over SetAccessedBy. Do not add mappings // if read duplication is enabled. - if (uvm_va_policy_is_read_duplicate(va_block_context->policy, va_space)) + if (uvm_va_policy_is_read_duplicate(policy, va_space)) return NV_OK; - status = UVM_VA_BLOCK_LOCK_RETRY(va_block, NULL, - va_block_set_accessed_by_locked(va_block, - va_block_context, - processor_id, - &local_tracker)); + status = UVM_VA_BLOCK_LOCK_RETRY(va_block, + NULL, + uvm_va_block_set_accessed_by_locked(va_block, + va_block_context, + processor_id, + region, + &local_tracker)); // TODO: Bug 1767224: Combine all accessed_by operations into single tracker if (status == NV_OK) @@ -463,7 +500,7 @@ bool set_bit; } accessed_by_split_params_t; -static bool accessed_by_is_split_needed(uvm_va_policy_t *policy, void *data) +static bool accessed_by_is_split_needed(const uvm_va_policy_t *policy, void *data) { accessed_by_split_params_t *params = (accessed_by_split_params_t*)data; @@ -479,26 +516,23 @@ bool set_bit) { uvm_processor_id_t processor_id = UVM_ID_INVALID; - uvm_va_range_t *va_range, *va_range_last; struct mm_struct *mm; const NvU64 last_address = base + length - 1; - bool range_is_sysmem = false; accessed_by_split_params_t split_params; uvm_tracker_t local_tracker = UVM_TRACKER_INIT(); - NV_STATUS status; + NV_STATUS status = NV_OK; NV_STATUS tracker_status; + uvm_api_range_type_t type; UVM_ASSERT(va_space); mm = uvm_va_space_mm_or_current_retain_lock(va_space); uvm_va_space_down_write(va_space); - status = uvm_api_range_type_check(va_space, mm, base, length); - if (status != NV_OK) { - if (status != NV_WARN_NOTHING_TO_DO) - goto done; - status = NV_OK; - range_is_sysmem = true; + type = uvm_api_range_type_check(va_space, mm, base, length); + if (type == UVM_API_RANGE_TYPE_INVALID) { + status = NV_ERR_INVALID_ADDRESS; + goto done; } if (uvm_uuid_is_cpu(processor_uuid)) { @@ -519,8 +553,10 @@ processor_id = gpu->id; } - if (range_is_sysmem) + if (type == UVM_API_RANGE_TYPE_ATS) { + status = NV_OK; goto done; + } split_params.processor_id = processor_id; split_params.set_bit = set_bit; @@ -532,35 +568,42 @@ if (status != NV_OK) goto done; - va_range_last = NULL; - uvm_for_each_managed_va_range_in_contig(va_range, va_space, base, last_address) { - va_range_last = va_range; + if (type == UVM_API_RANGE_TYPE_MANAGED) { + uvm_va_range_t *va_range; + uvm_va_range_t *va_range_last = NULL; - // If we didn't split the ends, check that they match - if (va_range->node.start < base || va_range->node.end > last_address) - UVM_ASSERT(uvm_processor_mask_test(&uvm_va_range_get_policy(va_range)->accessed_by, - processor_id) == set_bit); + uvm_for_each_managed_va_range_in_contig(va_range, va_space, base, last_address) { + va_range_last = va_range; - if (set_bit) { - status = uvm_va_range_set_accessed_by(va_range, processor_id, mm, &local_tracker); - if (status != NV_OK) - goto done; - } - else { - uvm_va_range_unset_accessed_by(va_range, processor_id, &local_tracker); + // If we didn't split the ends, check that they match + if (va_range->node.start < base || va_range->node.end > last_address) + UVM_ASSERT(uvm_processor_mask_test(&uvm_va_range_get_policy(va_range)->accessed_by, + processor_id) == set_bit); + + if (set_bit) { + status = uvm_va_range_set_accessed_by(va_range, processor_id, mm, &local_tracker); + if (status != NV_OK) + goto done; + } + else { + uvm_va_range_unset_accessed_by(va_range, processor_id, &local_tracker); + } } - } - if (va_range_last) { + UVM_ASSERT(va_range_last); UVM_ASSERT(va_range_last->node.end >= last_address); - goto done; } - - status = uvm_hmm_set_accessed_by(va_space, - processor_id, - set_bit, - base, - last_address); + else { + // NULL mm case already filtered by uvm_api_range_type_check() + UVM_ASSERT(mm); + UVM_ASSERT(type == UVM_API_RANGE_TYPE_HMM); + status = uvm_hmm_set_accessed_by(va_space, + processor_id, + set_bit, + base, + last_address, + &local_tracker); + } done: tracker_status = uvm_tracker_wait_deinit(&local_tracker); @@ -622,7 +665,6 @@ // TODO: Bug 3660922: need to implement HMM read duplication support. UVM_ASSERT(!uvm_va_block_is_hmm(va_block)); - UVM_ASSERT(va_block_context->policy == uvm_va_range_get_policy(va_block->va_range)); status = UVM_VA_BLOCK_LOCK_RETRY(va_block, &va_block_retry, va_block_set_read_duplication_locked(va_block, @@ -641,7 +683,7 @@ uvm_processor_id_t processor_id; uvm_va_block_region_t block_region = uvm_va_block_region_from_block(va_block); uvm_page_mask_t *break_read_duplication_pages = &va_block_context->caller_page_mask; - uvm_va_policy_t *policy = va_block_context->policy; + const uvm_va_policy_t *policy = uvm_va_range_get_policy(va_block->va_range); uvm_processor_id_t preferred_location = policy->preferred_location; uvm_processor_mask_t accessed_by = policy->accessed_by; @@ -703,10 +745,11 @@ // 2- Re-establish SetAccessedBy mappings for_each_id_in_mask(processor_id, &accessed_by) { - status = va_block_set_accessed_by_locked(va_block, - va_block_context, - processor_id, - out_tracker); + status = uvm_va_block_set_accessed_by_locked(va_block, + va_block_context, + processor_id, + block_region, + out_tracker); if (status != NV_OK) return status; } @@ -722,7 +765,6 @@ uvm_tracker_t local_tracker = UVM_TRACKER_INIT(); UVM_ASSERT(!uvm_va_block_is_hmm(va_block)); - UVM_ASSERT(va_block_context->policy == uvm_va_range_get_policy(va_block->va_range)); // Restore all SetAccessedBy mappings status = UVM_VA_BLOCK_LOCK_RETRY(va_block, &va_block_retry, @@ -738,7 +780,7 @@ return status; } -static bool read_duplication_is_split_needed(uvm_va_policy_t *policy, void *data) +static bool read_duplication_is_split_needed(const uvm_va_policy_t *policy, void *data) { uvm_read_duplication_policy_t new_policy; @@ -750,11 +792,11 @@ static NV_STATUS read_duplication_set(uvm_va_space_t *va_space, NvU64 base, NvU64 length, bool enable) { - uvm_va_range_t *va_range, *va_range_last; struct mm_struct *mm; const NvU64 last_address = base + length - 1; NV_STATUS status; uvm_read_duplication_policy_t new_policy; + uvm_api_range_type_t type; UVM_ASSERT(va_space); @@ -762,11 +804,13 @@ mm = uvm_va_space_mm_or_current_retain_lock(va_space); uvm_va_space_down_write(va_space); - status = uvm_api_range_type_check(va_space, mm, base, length); - if (status != NV_OK) { - if (status == NV_WARN_NOTHING_TO_DO) - status = NV_OK; - + type = uvm_api_range_type_check(va_space, mm, base, length); + if (type == UVM_API_RANGE_TYPE_INVALID) { + status = NV_ERR_INVALID_ADDRESS; + goto done; + } + else if (type == UVM_API_RANGE_TYPE_ATS) { + status = NV_OK; goto done; } @@ -781,43 +825,44 @@ if (status != NV_OK) goto done; - va_range_last = NULL; - uvm_for_each_managed_va_range_in_contig(va_range, va_space, base, last_address) { - va_range_last = va_range; + if (type == UVM_API_RANGE_TYPE_MANAGED) { + uvm_va_range_t *va_range; + uvm_va_range_t *va_range_last = NULL; - // If we didn't split the ends, check that they match - if (va_range->node.start < base || va_range->node.end > last_address) - UVM_ASSERT(uvm_va_range_get_policy(va_range)->read_duplication == new_policy); + uvm_for_each_managed_va_range_in_contig(va_range, va_space, base, last_address) { + va_range_last = va_range; - // If the va_space cannot currently read duplicate, only change the user - // state. All memory should already have read duplication unset. - if (uvm_va_space_can_read_duplicate(va_space, NULL)) { - - // Handle SetAccessedBy mappings - if (new_policy == UVM_READ_DUPLICATION_ENABLED) { - status = uvm_va_range_set_read_duplication(va_range, mm); - if (status != NV_OK) - goto done; + // If we didn't split the ends, check that they match + if (va_range->node.start < base || va_range->node.end > last_address) + UVM_ASSERT(uvm_va_range_get_policy(va_range)->read_duplication == new_policy); + + // If the va_space cannot currently read duplicate, only change the user + // state. All memory should already have read duplication unset. + if (uvm_va_space_can_read_duplicate(va_space, NULL)) { + + // Handle SetAccessedBy mappings + if (new_policy == UVM_READ_DUPLICATION_ENABLED) { + status = uvm_va_range_set_read_duplication(va_range, mm); + if (status != NV_OK) + goto done; + } + else { + // If unsetting read duplication fails, the return status is + // not propagated back to the caller + (void)uvm_va_range_unset_read_duplication(va_range, mm); + } } - else { - // If unsetting read duplication fails, the return status is - // not propagated back to the caller - (void)uvm_va_range_unset_read_duplication(va_range, mm); - } - } - uvm_va_range_get_policy(va_range)->read_duplication = new_policy; - } + uvm_va_range_get_policy(va_range)->read_duplication = new_policy; + } - if (va_range_last) { + UVM_ASSERT(va_range_last); UVM_ASSERT(va_range_last->node.end >= last_address); - goto done; } - - status = uvm_hmm_set_read_duplication(va_space, - new_policy, - base, - last_address); + else { + UVM_ASSERT(type == UVM_API_RANGE_TYPE_HMM); + status = uvm_hmm_set_read_duplication(va_space, new_policy, base, last_address); + } done: uvm_va_space_up_write(va_space); @@ -877,7 +922,6 @@ if (va_range->type != UVM_VA_RANGE_TYPE_MANAGED) continue; - va_block_context->policy = uvm_va_range_get_policy(va_range); for_each_va_block_in_va_range(va_range, va_block) { uvm_page_mask_t *non_resident_pages = &va_block_context->caller_page_mask; diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/kernel-open/nvidia-uvm/uvm_populate_pageable.c nvidia-open-gpu-kernel-modules-535.161.08/kernel-open/nvidia-uvm/uvm_populate_pageable.c --- nvidia-open-gpu-kernel-modules-525.147.05/kernel-open/nvidia-uvm/uvm_populate_pageable.c 2023-10-25 20:33:40.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/kernel-open/nvidia-uvm/uvm_populate_pageable.c 2024-03-05 22:26:01.000000000 +0000 @@ -30,6 +30,14 @@ #include "uvm_va_space.h" #include "uvm_populate_pageable.h" +#if defined(NV_HANDLE_MM_FAULT_HAS_MM_ARG) +#define UVM_HANDLE_MM_FAULT(vma, addr, flags) handle_mm_fault(vma->vm_mm, vma, addr, flags) +#elif defined(NV_HANDLE_MM_FAULT_HAS_PT_REGS_ARG) +#define UVM_HANDLE_MM_FAULT(vma, addr, flags) handle_mm_fault(vma, addr, flags, NULL) +#else +#define UVM_HANDLE_MM_FAULT(vma, addr, flags) handle_mm_fault(vma, addr, flags) +#endif + static bool is_write_populate(struct vm_area_struct *vma, uvm_populate_permissions_t populate_permissions) { switch (populate_permissions) { @@ -45,6 +53,34 @@ } } +NV_STATUS uvm_handle_fault(struct vm_area_struct *vma, unsigned long start, unsigned long vma_num_pages, bool write) +{ + NV_STATUS status = NV_OK; + + unsigned long i; + unsigned int ret = 0; + unsigned int fault_flags = write ? FAULT_FLAG_WRITE : 0; + +#ifdef FAULT_FLAG_REMOTE + fault_flags |= (FAULT_FLAG_REMOTE); +#endif + + for (i = 0; i < vma_num_pages; i++) { + ret = UVM_HANDLE_MM_FAULT(vma, start + (i * PAGE_SIZE), fault_flags); + if (ret & VM_FAULT_ERROR) { +#if defined(NV_VM_FAULT_TO_ERRNO_PRESENT) + int err = vm_fault_to_errno(ret, fault_flags); + status = errno_to_nv_status(err); +#else + status = errno_to_nv_status(-EFAULT); +#endif + break; + } + } + + return status; +} + NV_STATUS uvm_populate_pageable_vma(struct vm_area_struct *vma, unsigned long start, unsigned long length, @@ -97,6 +133,10 @@ if (uvm_managed_vma) uvm_record_unlock_mmap_lock_read(mm); + status = uvm_handle_fault(vma, start, vma_num_pages, !!(gup_flags & FOLL_WRITE)); + if (status != NV_OK) + goto out; + if (touch) ret = NV_PIN_USER_PAGES_REMOTE(mm, start, vma_num_pages, gup_flags, pages, NULL, NULL); else diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/kernel-open/nvidia-uvm/uvm_processors.h nvidia-open-gpu-kernel-modules-535.161.08/kernel-open/nvidia-uvm/uvm_processors.h --- nvidia-open-gpu-kernel-modules-525.147.05/kernel-open/nvidia-uvm/uvm_processors.h 2023-10-25 20:33:34.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/kernel-open/nvidia-uvm/uvm_processors.h 2024-03-05 22:25:52.000000000 +0000 @@ -314,6 +314,14 @@ return id1.val == id2.val; } +static int uvm_global_id_cmp(uvm_global_processor_id_t id1, uvm_global_processor_id_t id2) +{ + UVM_GLOBAL_ID_CHECK_BOUNDS(id1); + UVM_GLOBAL_ID_CHECK_BOUNDS(id2); + + return UVM_CMP_DEFAULT(id1.val, id2.val); +} + static bool uvm_global_id_equal(uvm_global_processor_id_t id1, uvm_global_processor_id_t id2) { UVM_GLOBAL_ID_CHECK_BOUNDS(id1); diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/kernel-open/nvidia-uvm/uvm_pte_batch.c nvidia-open-gpu-kernel-modules-535.161.08/kernel-open/nvidia-uvm/uvm_pte_batch.c --- nvidia-open-gpu-kernel-modules-525.147.05/kernel-open/nvidia-uvm/uvm_pte_batch.c 2023-10-25 20:33:37.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/kernel-open/nvidia-uvm/uvm_pte_batch.c 2024-03-05 22:25:54.000000000 +0000 @@ -54,7 +54,7 @@ uvm_push_set_flag(batch->push, UVM_PUSH_FLAG_NEXT_MEMBAR_NONE); uvm_push_set_flag(batch->push, UVM_PUSH_FLAG_CE_NEXT_PIPELINED); gpu->parent->ce_hal->memcopy(batch->push, - uvm_gpu_address_from_phys(batch->pte_first_address), + uvm_mmu_gpu_address(gpu, batch->pte_first_address), inline_data_addr, ptes_size); } @@ -62,7 +62,7 @@ static void uvm_pte_batch_flush_ptes_memset(uvm_pte_batch_t *batch) { uvm_gpu_t *gpu = uvm_push_get_gpu(batch->push); - uvm_gpu_address_t addr = uvm_gpu_address_from_phys(batch->pte_first_address); + uvm_gpu_address_t addr = uvm_mmu_gpu_address(gpu, batch->pte_first_address); NvU32 i; UVM_ASSERT(batch->pte_count != 0); @@ -201,7 +201,7 @@ uvm_push_set_flag(batch->push, UVM_PUSH_FLAG_CE_NEXT_PIPELINED); uvm_push_set_flag(batch->push, UVM_PUSH_FLAG_NEXT_MEMBAR_NONE); gpu->parent->ce_hal->memset_8(batch->push, - uvm_gpu_address_from_phys(first_pte), + uvm_mmu_gpu_address(gpu, first_pte), empty_pte_bits, entry_size * entry_count); diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/kernel-open/nvidia-uvm/uvm_push.c nvidia-open-gpu-kernel-modules-535.161.08/kernel-open/nvidia-uvm/uvm_push.c --- nvidia-open-gpu-kernel-modules-525.147.05/kernel-open/nvidia-uvm/uvm_push.c 2023-10-25 20:33:37.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/kernel-open/nvidia-uvm/uvm_push.c 2024-03-05 22:25:54.000000000 +0000 @@ -1,5 +1,5 @@ /******************************************************************************* - Copyright (c) 2015-2021 NVIDIA Corporation + Copyright (c) 2015-2023 NVIDIA Corporation Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation files (the "Software"), to @@ -351,11 +351,11 @@ UVM_ASSERT(!uvm_global_is_suspended()); UVM_ASSERT_MSG(uvm_push_get_size(data->push) + uvm_push_inline_data_size(data) + UVM_METHOD_SIZE + size <= UVM_MAX_PUSH_SIZE, - "push size %u inline data size %zu new data size %zu max push %u\n", - uvm_push_get_size(data->push), uvm_push_inline_data_size(data), size, UVM_MAX_PUSH_SIZE); + "push size %u inline data size %zu new data size %zu max push %u\n", + uvm_push_get_size(data->push), uvm_push_inline_data_size(data), size, UVM_MAX_PUSH_SIZE); UVM_ASSERT_MSG(uvm_push_inline_data_size(data) + size <= UVM_PUSH_INLINE_DATA_MAX_SIZE, - "inline data size %zu new data size %zu max %u\n", - uvm_push_inline_data_size(data), size, UVM_PUSH_INLINE_DATA_MAX_SIZE); + "inline data size %zu new data size %zu max %u\n", + uvm_push_inline_data_size(data), size, UVM_PUSH_INLINE_DATA_MAX_SIZE); data->next_data += size; @@ -368,6 +368,7 @@ size_t offset = 0; char *buffer; + UVM_ASSERT(alignment <= UVM_PAGE_SIZE_4K); UVM_ASSERT_MSG(IS_ALIGNED(alignment, UVM_METHOD_SIZE), "alignment %zu\n", alignment); offset = UVM_ALIGN_UP(next_ptr, alignment) - next_ptr; @@ -390,11 +391,13 @@ inline_data_address = (NvU64) (uintptr_t)(push->next + 1); } else { + uvm_pushbuffer_t *pushbuffer = uvm_channel_get_pushbuffer(channel); + // Offset of the inlined data within the push. inline_data_address = (push->next - push->begin + 1) * UVM_METHOD_SIZE; // Add GPU VA of the push begin - inline_data_address += uvm_pushbuffer_get_gpu_va_for_push(channel->pool->manager->pushbuffer, push); + inline_data_address += uvm_pushbuffer_get_gpu_va_for_push(pushbuffer, push); } // This will place a noop right before the inline data that was written. @@ -404,16 +407,16 @@ return uvm_gpu_address_virtual(inline_data_address); } -// Same as uvm_push_get_single_inline_buffer() but provides the specified -// alignment. -static void *push_get_single_inline_buffer_aligned(uvm_push_t *push, - size_t size, - size_t alignment, - uvm_gpu_address_t *gpu_address) +void *uvm_push_get_single_inline_buffer(uvm_push_t *push, + size_t size, + size_t alignment, + uvm_gpu_address_t *gpu_address) { uvm_push_inline_data_t data; void *buffer; + UVM_ASSERT(IS_ALIGNED(alignment, UVM_METHOD_SIZE)); + uvm_push_inline_data_begin(push, &data); buffer = uvm_push_inline_data_get_aligned(&data, size, alignment); *gpu_address = uvm_push_inline_data_end(&data); @@ -423,11 +426,6 @@ return buffer; } -void *uvm_push_get_single_inline_buffer(uvm_push_t *push, size_t size, uvm_gpu_address_t *gpu_address) -{ - return push_get_single_inline_buffer_aligned(push, size, UVM_METHOD_SIZE, gpu_address); -} - NvU64 *uvm_push_timestamp(uvm_push_t *push) { uvm_gpu_t *gpu = uvm_push_get_gpu(push); @@ -435,28 +433,31 @@ NvU64 *timestamp; uvm_gpu_address_t address; - timestamp = (NvU64 *)push_get_single_inline_buffer_aligned(push, timestamp_size, timestamp_size, &address); + timestamp = (NvU64 *)uvm_push_get_single_inline_buffer(push, timestamp_size, timestamp_size, &address); + // Timestamp is in the second half of the 16 byte semaphore release timestamp += 1; if (uvm_channel_is_ce(push->channel)) gpu->parent->ce_hal->semaphore_timestamp(push, address.address); else - UVM_ASSERT_MSG(0, "Semaphore release timestamp on an unsupported channel.\n"); + gpu->parent->sec2_hal->semaphore_timestamp(push, address.address); return timestamp; } -bool uvm_push_method_validate(uvm_push_t *push, NvU8 subch, NvU32 method_address, NvU32 method_data) +bool uvm_push_method_is_valid(uvm_push_t *push, NvU8 subch, NvU32 method_address, NvU32 method_data) { uvm_gpu_t *gpu = uvm_push_get_gpu(push); if (subch == UVM_SUBCHANNEL_CE) - return gpu->parent->ce_hal->method_validate(push, method_address, method_data); + return gpu->parent->ce_hal->method_is_valid(push, method_address, method_data); else if (subch == UVM_SUBCHANNEL_HOST) - return gpu->parent->host_hal->method_validate(push, method_address, method_data); + return gpu->parent->host_hal->method_is_valid(push, method_address, method_data); else if (subch == UVM_SW_OBJ_SUBCHANNEL) - return gpu->parent->host_hal->sw_method_validate(push, method_address, method_data); + return gpu->parent->host_hal->sw_method_is_valid(push, method_address, method_data); + else if (subch == UVM_SUBCHANNEL_SEC2) + return true; UVM_ERR_PRINT("Unsupported subchannel 0x%x\n", subch); return false; diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/kernel-open/nvidia-uvm/uvm_push.h nvidia-open-gpu-kernel-modules-535.161.08/kernel-open/nvidia-uvm/uvm_push.h --- nvidia-open-gpu-kernel-modules-525.147.05/kernel-open/nvidia-uvm/uvm_push.h 2023-10-25 20:33:37.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/kernel-open/nvidia-uvm/uvm_push.h 2024-03-05 22:25:54.000000000 +0000 @@ -1,5 +1,5 @@ /******************************************************************************* - Copyright (c) 2015-2021 NVIDIA Corporation + Copyright (c) 2015-2023 NVIDIA Corporation Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation files (the "Software"), to @@ -31,10 +31,6 @@ #include "uvm_tracker.h" #include "nvtypes.h" -// Space (in bytes) used by uvm_push_end() on a CE channel. -// This is the storage required by a semaphore release. -#define UVM_PUSH_CE_END_SIZE 24 - // The max amount of inline push data is limited by how much space can be jumped // over with a single NOOP method. #define UVM_PUSH_INLINE_DATA_MAX_SIZE (UVM_METHOD_COUNT_MAX * UVM_METHOD_SIZE) @@ -68,6 +64,14 @@ UVM_PUSH_FLAG_COUNT, } uvm_push_flag_t; +struct uvm_push_crypto_bundle_struct { + // Initialization vector used to decrypt the push + UvmCslIv iv; + + // Size of the pushbuffer that is encrypted/decrypted + NvU32 push_size; +}; + struct uvm_push_struct { // Location of the first method of the push @@ -93,6 +97,12 @@ // A bitmap of flags from uvm_push_flag_t DECLARE_BITMAP(flags, UVM_PUSH_FLAG_COUNT); + + // IV to use when launching WLC push + UvmCslIv launch_iv; + + // Channel to use for indirect submission + uvm_channel_t *launch_channel; }; #define UVM_PUSH_ACQUIRE_INFO_MAX_ENTRIES 16 @@ -127,7 +137,7 @@ }; } values[UVM_PUSH_ACQUIRE_INFO_MAX_ENTRIES]; - NvU32 num_values; + NvU32 num_values; }; struct uvm_push_info_struct @@ -149,7 +159,8 @@ char description[128]; // Procedure to be called when the corresponding push is complete. - // This procedure is called with the UVM_LOCK_ORDER_CHANNEL spin lock held. + // This procedure is called with the channel pool lock held, which + // may be a spinlock. void (*on_complete)(void *); void *on_complete_data; }; @@ -360,6 +371,9 @@ // These do just enough for inline push data and uvm_push_get_gpu() to work. // Used by tests that run on fake GPUs without a channel manager (see // uvm_page_tree_test.c for an example). +// When the Confidential Computing feature is enabled, LCIC channels also use +// fake push for other things, like encrypting semaphore values to unprotected +// sysmem. NV_STATUS uvm_push_begin_fake(uvm_gpu_t *gpu, uvm_push_t *push); void uvm_push_end_fake(uvm_push_t *push); @@ -379,6 +393,7 @@ static void uvm_push_inline_data_begin(uvm_push_t *push, uvm_push_inline_data_t *data) { data->push = push; + // +1 for the NOOP method inserted at inline_data_end() data->next_data = (char*)(push->next + 1); } @@ -406,7 +421,8 @@ // Same as uvm_push_inline_data_get() but provides the specified alignment. void *uvm_push_inline_data_get_aligned(uvm_push_inline_data_t *data, size_t size, size_t alignment); -// Get a single buffer of size bytes of inline data in the push +// Get a single buffer of size bytes of inline data in the push, alignment must +// be positive and a multiple of UVM_METHOD_SIZE. // // Returns the CPU pointer to the beginning of the buffer. The buffer can be // accessed as long as the push is on-going. Also returns the GPU address of the @@ -414,7 +430,10 @@ // // This is a wrapper around uvm_push_inline_data_begin() and // uvm_push_inline_data_end() so see their comments for more details. -void *uvm_push_get_single_inline_buffer(uvm_push_t *push, size_t size, uvm_gpu_address_t *gpu_address); +void *uvm_push_get_single_inline_buffer(uvm_push_t *push, + size_t size, + size_t alignment, + uvm_gpu_address_t *gpu_address); // Helper that copies size bytes of data from src into the inline data fragment static void uvm_push_inline_data_add(uvm_push_inline_data_t *data, const void *src, size_t size) @@ -438,7 +457,7 @@ // Validate that the given method can be pushed to the underlying channel. The // method contents can be used to further validate individual fields. -bool uvm_push_method_validate(uvm_push_t *push, NvU8 subch, NvU32 method_address, NvU32 method_data); +bool uvm_push_method_is_valid(uvm_push_t *push, NvU8 subch, NvU32 method_address, NvU32 method_data); // Retrieve the push info object for a push that has already started static uvm_push_info_t *uvm_push_info_from_push(uvm_push_t *push) diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/kernel-open/nvidia-uvm/uvm_push_macros.h nvidia-open-gpu-kernel-modules-535.161.08/kernel-open/nvidia-uvm/uvm_push_macros.h --- nvidia-open-gpu-kernel-modules-525.147.05/kernel-open/nvidia-uvm/uvm_push_macros.h 2023-10-25 20:33:37.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/kernel-open/nvidia-uvm/uvm_push_macros.h 2024-03-05 22:25:54.000000000 +0000 @@ -1,5 +1,5 @@ /******************************************************************************* - Copyright (c) 2015-2021 NVIDIA Corporation + Copyright (c) 2015-2023 NVIDIA Corporation Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation files (the "Software"), to @@ -34,6 +34,7 @@ #include "clb06f.h" #define HWMASK(d, r, f) DRF_MASK(NV ## d ## _ ## r ## _ ## f) +#define HWSHIFT(d, r, f) DRF_SHIFT(NV ## d ## _ ## r ## _ ## f) #define HWSHIFTMASK(d, r, f) DRF_SHIFTMASK(NV ## d ## _ ## r ## _ ## f) #define HWSIZE(d, r, f) DRF_SIZE(NV ## d ## _ ## r ## _ ## f) #define HWCONST(d, r, f, c) DRF_DEF(d, _ ## r, _ ## f, _ ## c) @@ -92,6 +93,8 @@ #define UVM_SUBCHANNEL_C0B5 UVM_SUBCHANNEL_CE #define UVM_SUBCHANNEL_C36F UVM_SUBCHANNEL_HOST +#define UVM_SUBCHANNEL_C3B5 UVM_SUBCHANNEL_CE + #define UVM_SUBCHANNEL_C46F UVM_SUBCHANNEL_HOST #define UVM_SUBCHANNEL_C56F UVM_SUBCHANNEL_HOST @@ -105,6 +108,14 @@ // value. For example, Kepler reserves subchannels 5-7 for software objects. #define UVM_SUBCHANNEL_C076 UVM_SW_OBJ_SUBCHANNEL +// NVA06F_SUBCHANNEL_COMPUTE is a semi-arbitrary value for UVM_SUBCHANNEL_SEC2. +// We need a "unique" subchannel across all subchannels UVM submits work. This +// is used when we are post-processing a pushbuffer and we need to extract SEC2 +// methods from a it, having a unique subchannel facilitates the SEC2 method +// identification. +#define UVM_SUBCHANNEL_SEC2 NVA06F_SUBCHANNEL_COMPUTE +#define UVM_SUBCHANNEL_CBA2 UVM_SUBCHANNEL_SEC2 + #define UVM_METHOD_SIZE 4 #define UVM_METHOD_COUNT_MAX HWMASK(B06F, DMA, INCR_COUNT) #if HWMASK(B06F, DMA, INCR_COUNT) != HWMASK(B06F, DMA, NONINCR_COUNT) @@ -123,29 +134,29 @@ HWVALUE(B06F, DMA, NONINCR_SUBCHANNEL, (subch)) | \ HWVALUE(B06F, DMA, NONINCR_COUNT, (count))) -#define __UVM_ASSERT_CONTIGUOUS_METHODS(a1, a2) BUILD_BUG_ON((a2) - (a1) != 4) +#define __UVM_ASSERT_CONTIGUOUS_METHODS(a1, a2) BUILD_BUG_ON((a2) - (a1) != UVM_METHOD_SIZE) // __NV_PUSH_*U support being called recursively from the N+1 sized method with // the _0U doing all the common things. // Notably all the push macros assume that symbol "push" of type uvm_push_t * is // in scope. -#define __NV_PUSH_0U(subch, count, a1) \ - do { \ - UVM_ASSERT(!uvm_global_is_suspended()); \ - UVM_ASSERT(uvm_push_get_size(push) + (count + 1) * 4 <= UVM_MAX_PUSH_SIZE); \ - UVM_ASSERT_MSG(a1 % 4 == 0, "Address %u\n", a1); \ - \ - push->next[0] = UVM_METHOD_INC(subch, a1, count); \ - ++push->next; \ +#define __NV_PUSH_0U(subch, count, a1) \ + do { \ + UVM_ASSERT(!uvm_global_is_suspended()); \ + UVM_ASSERT(uvm_push_get_size(push) + (count + 1) * UVM_METHOD_SIZE <= UVM_MAX_PUSH_SIZE); \ + UVM_ASSERT_MSG(IS_ALIGNED(a1, UVM_METHOD_SIZE), "Address %u\n", a1); \ + \ + push->next[0] = UVM_METHOD_INC(subch, a1, count); \ + ++push->next; \ } while (0) #define __NV_PUSH_1U(subch, count, a1,d1) \ do { \ __NV_PUSH_0U(subch, count, a1); \ + UVM_ASSERT_MSG(uvm_push_method_is_valid(push, subch, a1, d1), \ + "Method validation failed in channel %s\n", \ + push->channel->name); \ push->next[0] = d1; \ - UVM_ASSERT_MSG(uvm_push_method_validate(push, subch, a1, d1), \ - "Method validation failed in channel %s\n", \ - push->channel->name); \ ++push->next; \ } while (0) @@ -153,9 +164,9 @@ do { \ __UVM_ASSERT_CONTIGUOUS_METHODS(a1, a2); \ __NV_PUSH_1U(subch, count, a1,d1); \ - UVM_ASSERT_MSG(uvm_push_method_validate(push, subch, a2, d2), \ - "Method validation failed in channel %s\n", \ - push->channel->name); \ + UVM_ASSERT_MSG(uvm_push_method_is_valid(push, subch, a2, d2), \ + "Method validation failed in channel %s\n", \ + push->channel->name); \ push->next[0] = d2; \ ++push->next; \ } while (0) @@ -164,9 +175,9 @@ do { \ __UVM_ASSERT_CONTIGUOUS_METHODS(a2, a3); \ __NV_PUSH_2U(subch, count, a1,d1, a2,d2); \ - UVM_ASSERT_MSG(uvm_push_method_validate(push, subch, a3, d3), \ - "Method validation failed in channel %s\n", \ - push->channel->name); \ + UVM_ASSERT_MSG(uvm_push_method_is_valid(push, subch, a3, d3), \ + "Method validation failed in channel %s\n", \ + push->channel->name); \ push->next[0] = d3; \ ++push->next; \ } while (0) @@ -175,9 +186,9 @@ do { \ __UVM_ASSERT_CONTIGUOUS_METHODS(a3, a4); \ __NV_PUSH_3U(subch, count, a1,d1, a2,d2, a3,d3); \ - UVM_ASSERT_MSG(uvm_push_method_validate(push, subch, a4, d4), \ - "Method validation failed in channel %s\n", \ - push->channel->name); \ + UVM_ASSERT_MSG(uvm_push_method_is_valid(push, subch, a4, d4), \ + "Method validation failed in channel %s\n", \ + push->channel->name); \ push->next[0] = d4; \ ++push->next; \ } while (0) @@ -186,9 +197,9 @@ do { \ __UVM_ASSERT_CONTIGUOUS_METHODS(a4, a5); \ __NV_PUSH_4U(subch, count, a1,d1, a2,d2, a3,d3, a4,d4); \ - UVM_ASSERT_MSG(uvm_push_method_validate(push, subch, a5, d5), \ - "Method validation failed in channel %s\n", \ - push->channel->name); \ + UVM_ASSERT_MSG(uvm_push_method_is_valid(push, subch, a5, d5), \ + "Method validation failed in channel %s\n", \ + push->channel->name); \ push->next[0] = d5; \ ++push->next; \ } while (0) @@ -197,9 +208,9 @@ do { \ __UVM_ASSERT_CONTIGUOUS_METHODS(a5, a6); \ __NV_PUSH_5U(subch, count, a1,d1, a2,d2, a3,d3, a4,d4, a5,d5); \ - UVM_ASSERT_MSG(uvm_push_method_validate(push, subch, a6, d6), \ - "Method validation failed in channel %s\n", \ - push->channel->name); \ + UVM_ASSERT_MSG(uvm_push_method_is_valid(push, subch, a6, d6), \ + "Method validation failed in channel %s\n", \ + push->channel->name); \ push->next[0] = d6; \ ++push->next; \ } while (0) @@ -245,13 +256,13 @@ // Non-incrementing method with count data fields following it. The data is left // untouched and hence it's primarily useful for a NOP method. -#define __NV_PUSH_NU_NONINC(subch, count, address) \ - do { \ - UVM_ASSERT(!uvm_global_is_suspended()); \ - UVM_ASSERT(uvm_push_get_size(push) + (count + 1) * 4 <= UVM_MAX_PUSH_SIZE); \ - UVM_ASSERT_MSG(address % 4 == 0, "Address %u\n", address); \ - push->next[0] = UVM_METHOD_NONINC(subch, address, count); \ - push->next += count + 1; \ +#define __NV_PUSH_NU_NONINC(subch, count, address) \ + do { \ + UVM_ASSERT(!uvm_global_is_suspended()); \ + UVM_ASSERT(uvm_push_get_size(push) + (count + 1) * UVM_METHOD_SIZE <= UVM_MAX_PUSH_SIZE); \ + UVM_ASSERT_MSG(IS_ALIGNED(address, UVM_METHOD_SIZE), "Address %u\n", address); \ + push->next[0] = UVM_METHOD_NONINC(subch, address, count); \ + push->next += count + 1; \ } while (0) #define NV_PUSH_NU_NONINC(class, a1, count) \ diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/kernel-open/nvidia-uvm/uvm_push_test.c nvidia-open-gpu-kernel-modules-535.161.08/kernel-open/nvidia-uvm/uvm_push_test.c --- nvidia-open-gpu-kernel-modules-525.147.05/kernel-open/nvidia-uvm/uvm_push_test.c 2023-10-25 20:33:43.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/kernel-open/nvidia-uvm/uvm_push_test.c 2024-03-05 22:26:06.000000000 +0000 @@ -1,5 +1,5 @@ /******************************************************************************* - Copyright (c) 2015-2022 NVIDIA Corporation + Copyright (c) 2015-2023 NVIDIA Corporation Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation files (the "Software"), to @@ -38,50 +38,142 @@ #define TEST_PUSH_INTERLEAVING_NUM_PAUSED_PUSHES 2 -static NvU32 get_push_end_size(uvm_channel_t *channel) +static NvU32 get_push_begin_size(uvm_channel_t *channel) { - if (uvm_channel_is_ce(channel)) - return UVM_PUSH_CE_END_SIZE; + // SEC2 channels allocate CSL signature buffer at the beginning. + if (uvm_channel_is_sec2(channel)) + return UVM_CONF_COMPUTING_SIGN_BUF_MAX_SIZE + UVM_METHOD_SIZE; return 0; } +// This is the storage required by a semaphore release. +static NvU32 get_push_end_min_size(uvm_channel_t *channel) +{ + uvm_gpu_t *gpu = uvm_channel_get_gpu(channel); + + if (uvm_conf_computing_mode_enabled(gpu)) { + if (uvm_channel_is_ce(channel)) { + // Space (in bytes) used by uvm_push_end() on a CE channel when + // the Confidential Computing feature is enabled. + // + // Note that CE semaphore release pushes two memset and one + // encryption method on top of the regular release. + // Memset size + // ------------- + // PUSH_2U (SET_REMAP) : 3 Words + // PUSH_2U (OFFSET_OUT) : 3 Words + // PUSH_1U (LINE_LENGTH_IN) : 2 Words + // PUSH_1U (LAUNCH_DMA) : 2 Words + // Total 10 * UVM_METHOD_SIZE : 40 Bytes + // + // Encrypt size + // ------------- + // PUSH_1U (SET_SECURE_COPY_MODE) : 2 Words + // PUSH_4U (ENCRYPT_AUTH_TAG + IV) : 5 Words + // PUSH_4U (OFFSET_IN_OUT) : 5 Words + // PUSH_2U (LINE_LENGTH_IN) : 2 Words + // PUSH_2U (LAUNCH_DMA) : 2 Words + // Total 16 * UVM_METHOD_SIZE : 64 Bytes + // + // TOTAL : 144 Bytes + + if (uvm_channel_is_wlc(channel)) { + // Same as CE + LCIC GPPut update + LCIC doorbell + return 24 + 144 + 24 + 24; + } + + return 24 + 144; + } + + UVM_ASSERT(uvm_channel_is_sec2(channel)); + + // A perfectly aligned inline buffer in SEC2 semaphore release. + // We add UVM_METHOD_SIZE because of the NOP method to reserve + // UVM_CSL_SIGN_AUTH_TAG_SIZE_BYTES (the inline buffer.) + return 48 + UVM_CSL_SIGN_AUTH_TAG_SIZE_BYTES + UVM_METHOD_SIZE; + } + + UVM_ASSERT(uvm_channel_is_ce(channel)); + + // Space (in bytes) used by uvm_push_end() on a CE channel. + return 24; +} + +static NvU32 get_push_end_max_size(uvm_channel_t *channel) +{ + // WLC pushes are always padded to UVM_MAX_WLC_PUSH_SIZE + if (uvm_channel_is_wlc(channel)) + return UVM_MAX_WLC_PUSH_SIZE; + + // Space (in bytes) used by uvm_push_end() on a SEC2 channel. + // Note that SEC2 semaphore release uses an inline buffer with alignment + // requirements. This is the "worst" case semaphore_release storage. + if (uvm_channel_is_sec2(channel)) + return 48 + UVM_CSL_SIGN_AUTH_TAG_SIZE_BYTES + UVM_CONF_COMPUTING_AUTH_TAG_ALIGNMENT; + + UVM_ASSERT(uvm_channel_is_ce(channel)); + + // Space (in bytes) used by uvm_push_end() on a CE channel. + return get_push_end_min_size(channel); +} + static NV_STATUS test_push_end_size(uvm_va_space_t *va_space) { - NV_STATUS status = NV_OK; uvm_gpu_t *gpu; - NvU32 push_size; - NvU32 i; for_each_va_space_gpu(gpu, va_space) { - for (i = 0; i < UVM_CHANNEL_TYPE_COUNT; ++i) { - uvm_push_t push; - NvU32 push_end_size; - uvm_channel_type_t type = i; + uvm_channel_type_t type; - status = uvm_push_begin(gpu->channel_manager, type, &push, "type %u\n", (unsigned)type); - TEST_CHECK_GOTO(status == NV_OK, done); + for (type = 0; type < UVM_CHANNEL_TYPE_COUNT; ++type) { + uvm_push_t push; + NvU32 push_size_before; + NvU32 push_end_size_observed; + NvU32 push_end_size_expected[2]; + + // SEC2 is only available when Confidential Computing is enabled + if ((type == UVM_CHANNEL_TYPE_SEC2) && !uvm_conf_computing_mode_enabled(gpu)) + continue; + + // WLC is only available when Confidential Computing is enabled + if ((type == UVM_CHANNEL_TYPE_WLC) && !uvm_conf_computing_mode_enabled(gpu)) + continue; + + // LCIC doesn't accept pushes + if (type == UVM_CHANNEL_TYPE_LCIC) + continue; + TEST_NV_CHECK_RET(uvm_push_begin(gpu->channel_manager, + type, + &push, + "type %s", + uvm_channel_type_to_string(type))); - push_end_size = get_push_end_size(push.channel); - push_size = uvm_push_get_size(&push); + push_size_before = uvm_push_get_size(&push); uvm_push_end(&push); - if (uvm_push_get_size(&push) - push_size != push_end_size) { - UVM_TEST_PRINT("push_end_size incorrect, %u instead of %u for GPU %s\n", - uvm_push_get_size(&push) - push_size, - push_end_size, + push_end_size_observed = uvm_push_get_size(&push) - push_size_before; + + push_end_size_expected[0] = get_push_end_min_size(push.channel); + push_end_size_expected[1] = get_push_end_max_size(push.channel); + + if (push_end_size_observed < push_end_size_expected[0] || + push_end_size_observed > push_end_size_expected[1]) { + UVM_TEST_PRINT("push_end_size incorrect, %u instead of [%u:%u] on channel type %s for GPU %s\n", + push_end_size_observed, + push_end_size_expected[0], + push_end_size_expected[1], + uvm_channel_type_to_string(type), uvm_gpu_name(gpu)); - status = NV_ERR_INVALID_STATE; - goto done; + // The size mismatch error gets precedence over a wait error + (void) uvm_push_wait(&push); + + return NV_ERR_INVALID_STATE; } - } - } -done: - for_each_va_space_gpu(gpu, va_space) { - uvm_channel_manager_wait(gpu->channel_manager); + TEST_NV_CHECK_RET(uvm_push_wait(&push)); + } } - return status; + return NV_OK; } typedef enum { @@ -101,6 +193,11 @@ uvm_mem_t *mem = NULL; char *verif; + // TODO: Bug 3839176: test is waived on Confidential Computing because + // it assumes that GPU can access system memory without using encryption. + if (uvm_conf_computing_mode_enabled(gpu)) + return NV_OK; + status = uvm_mem_alloc_sysmem_and_map_cpu_kernel(UVM_PUSH_INLINE_DATA_MAX_SIZE, current->mm, &mem); TEST_CHECK_GOTO(status == NV_OK, done); @@ -146,7 +243,10 @@ inline_buf[j] = 1 + i + j; break; case TEST_INLINE_SINGLE_BUFFER: - inline_buf = (char*)uvm_push_get_single_inline_buffer(&push, test_size, &data_gpu_address); + inline_buf = (char*)uvm_push_get_single_inline_buffer(&push, + test_size, + UVM_METHOD_SIZE, + &data_gpu_address); inline_data_size = test_size; for (j = 0; j < test_size; ++j) inline_buf[j] = 1 + i + j; @@ -198,9 +298,19 @@ { NV_STATUS status = NV_OK; uvm_gpu_t *gpu; - NvU32 i; uvm_push_t *pushes; - uvm_tracker_t tracker = UVM_TRACKER_INIT(); + uvm_tracker_t tracker; + + // When the Confidential Computing feature is enabled, a channel reserved at + // the start of a push cannot be reserved again until that push ends. The + // test is waived, because the number of pushes it starts per pool exceeds + // the number of channels in the pool, so it would block indefinitely. + gpu = uvm_va_space_find_first_gpu(va_space); + + if ((gpu != NULL) && uvm_conf_computing_mode_enabled(gpu)) + return NV_OK; + + uvm_tracker_init(&tracker); // As noted above, this test does unsafe things that would be detected by // lock tracking, opt-out. @@ -213,9 +323,11 @@ } for_each_va_space_gpu(gpu, va_space) { + NvU32 i; + for (i = 0; i < UVM_PUSH_MAX_CONCURRENT_PUSHES; ++i) { uvm_push_t *push = &pushes[i]; - status = uvm_push_begin(gpu->channel_manager, UVM_CHANNEL_TYPE_CPU_TO_GPU, push, "concurrent push %u", i); + status = uvm_push_begin(gpu->channel_manager, UVM_CHANNEL_TYPE_GPU_INTERNAL, push, "concurrent push %u", i); TEST_CHECK_GOTO(status == NV_OK, done); } for (i = 0; i < UVM_PUSH_MAX_CONCURRENT_PUSHES; ++i) { @@ -270,6 +382,11 @@ uvm_rm_mem_t *mem = NULL; atomic_t on_complete_counter = ATOMIC_INIT(0); + // TODO: Bug 3839176: test is waived on Confidential Computing because + // it assumes that GPU can access system memory without using encryption. + if (uvm_conf_computing_mode_enabled(gpu)) + return NV_OK; + // This test issues virtual memcopies/memsets, which in SR-IOV heavy cannot // be pushed to a proxy channel. Pushing to a UVM internal CE channel works // in all scenarios. @@ -286,7 +403,7 @@ num_non_paused_pushes = channel->num_gpfifo_entries; // The UVM driver only allows push interleaving across separate threads, but - // it is hard to consistenly replicate the interleaving. Instead, we + // it is hard to consistently replicate the interleaving. Instead, we // temporarily disable lock tracking, so we can interleave pushes from a // single thread. uvm_thread_context_lock_disable_tracking(); @@ -294,7 +411,7 @@ status = uvm_rm_mem_alloc_and_map_cpu(gpu, UVM_RM_MEM_TYPE_SYS, size, 0, &mem); TEST_CHECK_GOTO(status == NV_OK, done); host_va = (NvU32*)uvm_rm_mem_get_cpu_va(mem); - gpu_va = uvm_rm_mem_get_gpu_va(mem, gpu, uvm_channel_is_proxy(channel)); + gpu_va = uvm_rm_mem_get_gpu_va(mem, gpu, uvm_channel_is_proxy(channel)).address; memset(host_va, 0, size); // Begin a few pushes on the channel, but do not end them yet. @@ -426,14 +543,14 @@ if (status != NV_OK) return status; - TEST_CHECK_RET(uvm_push_has_space(push, UVM_MAX_PUSH_SIZE)); - TEST_CHECK_RET(!uvm_push_has_space(push, UVM_MAX_PUSH_SIZE + 1)); + TEST_CHECK_RET(uvm_push_has_space(push, UVM_MAX_PUSH_SIZE - get_push_begin_size(push->channel))); + TEST_CHECK_RET(!uvm_push_has_space(push, UVM_MAX_PUSH_SIZE - get_push_begin_size(push->channel) + 1)); semaphore_gpu_va = uvm_gpu_semaphore_get_gpu_va(sema_to_acquire, gpu, uvm_channel_is_proxy(push->channel)); gpu->parent->host_hal->semaphore_acquire(push, semaphore_gpu_va, value); // Push a noop leaving just push_end_size in the pushbuffer. - push_end_size = get_push_end_size(push->channel); + push_end_size = get_push_end_max_size(push->channel); gpu->parent->host_hal->noop(push, UVM_MAX_PUSH_SIZE - uvm_push_get_size(push) - push_end_size); TEST_CHECK_RET(uvm_push_has_space(push, push_end_size)); @@ -468,7 +585,7 @@ // Test doing pushes of exactly UVM_MAX_PUSH_SIZE size and only allowing them to // complete one by one. -static NV_STATUS test_max_pushes_on_gpu_and_channel_type(uvm_gpu_t *gpu, uvm_channel_type_t channel_type) +static NV_STATUS test_max_pushes_on_gpu(uvm_gpu_t *gpu) { NV_STATUS status; @@ -477,6 +594,7 @@ NvU32 total_push_size = 0; NvU32 push_count = 0; NvU32 i; + uvm_channel_type_t channel_type = UVM_CHANNEL_TYPE_GPU_INTERNAL; uvm_tracker_init(&tracker); @@ -484,6 +602,13 @@ TEST_CHECK_GOTO(status == NV_OK, done); uvm_gpu_semaphore_set_payload(&sema, 0); + if (uvm_conf_computing_mode_enabled(gpu)) { + // Use SEC2 channel when Confidential Compute is enabled + // since all other channel types need extra space for + // work launch, and the channel type really doesn't + // matter for this test. + channel_type = UVM_CHANNEL_TYPE_SEC2; + } // Need to wait for all channels to completely idle so that the pushbuffer // is in completely idle state when we begin. @@ -545,14 +670,6 @@ return status; } -static NV_STATUS test_max_pushes_on_gpu(uvm_gpu_t *gpu) -{ - - TEST_NV_CHECK_RET(test_max_pushes_on_gpu_and_channel_type(gpu, UVM_CHANNEL_TYPE_GPU_INTERNAL)); - - return NV_OK; -} - // Test doing UVM_PUSHBUFFER_CHUNKS independent pushes expecting each one to use // a different chunk in the pushbuffer. static NV_STATUS test_idle_chunks_on_gpu(uvm_gpu_t *gpu) @@ -562,6 +679,15 @@ uvm_gpu_semaphore_t sema; uvm_tracker_t tracker = UVM_TRACKER_INIT(); NvU32 i; + uvm_channel_type_t channel_type = UVM_CHANNEL_TYPE_GPU_INTERNAL; + + if (uvm_conf_computing_mode_enabled(gpu)) { + // Use SEC2 channel when Confidential Compute is enabled + // since all other channel types need extra space for + // work launch, and the channel type really doesn't + // matter for this test. + channel_type = UVM_CHANNEL_TYPE_SEC2; + } uvm_tracker_init(&tracker); @@ -579,7 +705,7 @@ NvU64 semaphore_gpu_va; uvm_push_t push; - status = uvm_push_begin(gpu->channel_manager, UVM_CHANNEL_TYPE_GPU_INTERNAL, &push, "Push using chunk %u", i); + status = uvm_push_begin(gpu->channel_manager, channel_type, &push, "Push using chunk %u", i); TEST_CHECK_GOTO(status == NV_OK, done); semaphore_gpu_va = uvm_gpu_semaphore_get_gpu_va(&sema, gpu, uvm_channel_is_proxy(push.channel)); @@ -760,6 +886,11 @@ bool waive = true; for_each_va_space_gpu(gpu_a, va_space) { + + // TODO: Bug 3839176: the test is waived on Confidential Computing because + // it assumes that GPU can access system memory without using encryption. + if (uvm_conf_computing_mode_enabled(gpu_a)) + return NV_OK; for_each_va_space_gpu(gpu_b, va_space) { if (can_do_peer_copies(va_space, gpu_a, gpu_b)) { waive = false; diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/kernel-open/nvidia-uvm/uvm_pushbuffer.c nvidia-open-gpu-kernel-modules-535.161.08/kernel-open/nvidia-uvm/uvm_pushbuffer.c --- nvidia-open-gpu-kernel-modules-525.147.05/kernel-open/nvidia-uvm/uvm_pushbuffer.c 2023-10-25 20:33:37.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/kernel-open/nvidia-uvm/uvm_pushbuffer.c 2024-03-05 22:25:55.000000000 +0000 @@ -32,6 +32,7 @@ #include "uvm_gpu.h" #include "uvm_common.h" #include "uvm_linux.h" +#include "uvm_conf_computing.h" // Print pushbuffer state into a seq_file if provided or with UVM_DBG_PRINT() if not. static void uvm_pushbuffer_print_common(uvm_pushbuffer_t *pushbuffer, struct seq_file *s); @@ -120,6 +121,36 @@ if (status != NV_OK) goto error; + if (uvm_conf_computing_mode_enabled(gpu)) { + UVM_ASSERT(channel_manager->conf.pushbuffer_loc == UVM_BUFFER_LOCATION_SYS); + + // Move the above allocation to unprotected_sysmem + pushbuffer->memory_unprotected_sysmem = pushbuffer->memory; + pushbuffer->memory = NULL; + + // Make sure the base can be least 4KB aligned. Pushes can include inline buffers + // with specific alignment requirement. Different base between backing memory + // locations would change that. + pushbuffer->memory_protected_sysmem = uvm_kvmalloc_zero(UVM_PUSHBUFFER_SIZE + UVM_PAGE_SIZE_4K); + if (!pushbuffer->memory_protected_sysmem) { + status = NV_ERR_NO_MEMORY; + goto error; + } + + + status = uvm_rm_mem_alloc(gpu, + UVM_RM_MEM_TYPE_GPU, + UVM_PUSHBUFFER_SIZE, + pushbuffer_alignment, + &pushbuffer->memory); + if (status != NV_OK) + goto error; + + status = uvm_rm_mem_map_gpu(pushbuffer->memory_unprotected_sysmem, gpu, pushbuffer_alignment); + if (status != NV_OK) + goto error; + } + // Verify the GPU can access the pushbuffer. UVM_ASSERT((uvm_pushbuffer_get_gpu_va_base(pushbuffer) + UVM_PUSHBUFFER_SIZE - 1) < gpu->parent->max_host_va); @@ -227,9 +258,24 @@ return chunk != NULL; } +static char *get_base_cpu_va(uvm_pushbuffer_t *pushbuffer) +{ + // Confidential Computing pushes are assembled in protected sysmem + // and safely (through encrypt/decrypt) moved to protected vidmem. + // Or signed and moved to unprotected sysmem. + if (uvm_conf_computing_mode_enabled(pushbuffer->channel_manager->gpu)) { + // Align protected sysmem base to 4kB. This should be enough to give + // the same alignment behaviour for inline buffers as the other two + // backing memory locations. + return (char*)(UVM_ALIGN_UP((uintptr_t)pushbuffer->memory_protected_sysmem, UVM_PAGE_SIZE_4K)); + } + + return (char *)uvm_rm_mem_get_cpu_va(pushbuffer->memory); +} + static NvU32 *chunk_get_next_push_start_addr(uvm_pushbuffer_t *pushbuffer, uvm_pushbuffer_chunk_t *chunk) { - char *push_start = (char *)uvm_rm_mem_get_cpu_va(pushbuffer->memory); + char *push_start = get_base_cpu_va(pushbuffer); push_start += chunk_get_offset(pushbuffer, chunk); push_start += chunk->next_push_start; @@ -266,6 +312,16 @@ UVM_ASSERT(pushbuffer); UVM_ASSERT(push); + UVM_ASSERT(push->channel); + + if (uvm_channel_is_wlc(push->channel)) { + // WLC pushes use static PB and don't count against max concurrent + // pushes. + push->begin = (void*)UVM_ALIGN_UP((uintptr_t)push->channel->conf_computing.static_pb_protected_sysmem, + UVM_PAGE_SIZE_4K); + push->next = push->begin; + return NV_OK; + } // Note that this semaphore is uvm_up()ed in end_push(). uvm_down(&pushbuffer->concurrent_pushes_sema); @@ -374,6 +430,8 @@ proc_remove(pushbuffer->procfs.info_file); + uvm_rm_mem_free(pushbuffer->memory_unprotected_sysmem); + uvm_kvfree(pushbuffer->memory_protected_sysmem); uvm_rm_mem_free(pushbuffer->memory); uvm_kvfree(pushbuffer); } @@ -391,21 +449,68 @@ return chunk; } -void uvm_pushbuffer_mark_completed(uvm_pushbuffer_t *pushbuffer, uvm_gpfifo_entry_t *gpfifo) +static void decrypt_push(uvm_channel_t *channel, uvm_gpfifo_entry_t *gpfifo) +{ + NV_STATUS status; + NvU32 auth_tag_offset; + void *auth_tag_cpu_va; + void *push_protected_cpu_va; + void *push_unprotected_cpu_va; + NvU32 pushbuffer_offset = gpfifo->pushbuffer_offset; + NvU32 push_info_index = gpfifo->push_info - channel->push_infos; + uvm_pushbuffer_t *pushbuffer = uvm_channel_get_pushbuffer(channel); + uvm_push_crypto_bundle_t *crypto_bundle = channel->conf_computing.push_crypto_bundles + push_info_index; + + if (channel->conf_computing.push_crypto_bundles == NULL) + return; + + // When the crypto bundle is used, the push size cannot be zero + if (crypto_bundle->push_size == 0) + return; + + UVM_ASSERT(!uvm_channel_is_wlc(channel)); + UVM_ASSERT(!uvm_channel_is_lcic(channel)); + + push_protected_cpu_va = (char *)get_base_cpu_va(pushbuffer) + pushbuffer_offset; + push_unprotected_cpu_va = (char *)uvm_rm_mem_get_cpu_va(pushbuffer->memory_unprotected_sysmem) + pushbuffer_offset; + auth_tag_offset = push_info_index * UVM_CONF_COMPUTING_AUTH_TAG_SIZE; + auth_tag_cpu_va = (char *)uvm_rm_mem_get_cpu_va(channel->conf_computing.push_crypto_bundle_auth_tags) + + auth_tag_offset; + + status = uvm_conf_computing_cpu_decrypt(channel, + push_protected_cpu_va, + push_unprotected_cpu_va, + &crypto_bundle->iv, + crypto_bundle->push_size, + auth_tag_cpu_va); + + // A decryption failure here is not fatal because it does not + // prevent UVM from running fine in the future and cannot be used + // maliciously to leak information or otherwise derail UVM from its + // regular duties. + UVM_ASSERT_MSG_RELEASE(status == NV_OK, "Pushbuffer decryption failure: %s\n", nvstatusToString(status)); + + // Avoid reusing the bundle across multiple pushes + crypto_bundle->push_size = 0; +} + +void uvm_pushbuffer_mark_completed(uvm_channel_t *channel, uvm_gpfifo_entry_t *gpfifo) { uvm_pushbuffer_chunk_t *chunk; - uvm_push_info_t *push_info = gpfifo->push_info; bool need_to_update_chunk = false; + uvm_push_info_t *push_info = gpfifo->push_info; + uvm_pushbuffer_t *pushbuffer = uvm_channel_get_pushbuffer(channel); UVM_ASSERT(gpfifo->type == UVM_GPFIFO_ENTRY_TYPE_NORMAL); chunk = gpfifo_to_chunk(pushbuffer, gpfifo); - if (push_info->on_complete != NULL) + if (push_info->on_complete != NULL) { + decrypt_push(channel, gpfifo); push_info->on_complete(push_info->on_complete_data); - - push_info->on_complete = NULL; - push_info->on_complete_data = NULL; + push_info->on_complete = NULL; + push_info->on_complete_data = NULL; + } uvm_spin_lock(&pushbuffer->lock); @@ -426,7 +531,17 @@ NvU32 uvm_pushbuffer_get_offset_for_push(uvm_pushbuffer_t *pushbuffer, uvm_push_t *push) { - NvU32 offset = (char*)push->begin - (char *)uvm_rm_mem_get_cpu_va(pushbuffer->memory); + NvU32 offset; + + if (uvm_channel_is_wlc(push->channel)) { + // WLC channels use private static PB and their gpfifo entries are not + // added to any chunk's list. This only needs to return legal offset. + // Completion cleanup will not find WLC gpfifo entries as either first + // or last entry of any chunk. + return 0; + } + + offset = (char*)push->begin - get_base_cpu_va(pushbuffer); UVM_ASSERT(((NvU64)offset) % sizeof(NvU32) == 0); @@ -439,14 +554,65 @@ uvm_gpu_t *gpu = uvm_push_get_gpu(push); bool is_proxy_channel = uvm_channel_is_proxy(push->channel); - pushbuffer_base = uvm_rm_mem_get_gpu_va(pushbuffer->memory, gpu, is_proxy_channel); + pushbuffer_base = uvm_rm_mem_get_gpu_va(pushbuffer->memory, gpu, is_proxy_channel).address; + + if (uvm_channel_is_wlc(push->channel) || uvm_channel_is_lcic(push->channel)) { + // We need to use the same static locations for PB as the fixed + // schedule because that's what the channels are initialized to use. + return uvm_rm_mem_get_gpu_uvm_va(push->channel->conf_computing.static_pb_protected_vidmem, gpu); + } + else if (uvm_channel_is_sec2(push->channel)) { + // SEC2 PBs are in unprotected sysmem + pushbuffer_base = uvm_pushbuffer_get_sec2_gpu_va_base(pushbuffer); + } + + return pushbuffer_base + uvm_pushbuffer_get_offset_for_push(pushbuffer, push); +} + +void *uvm_pushbuffer_get_unprotected_cpu_va_for_push(uvm_pushbuffer_t *pushbuffer, uvm_push_t *push) +{ + char *pushbuffer_base; + + if (uvm_channel_is_wlc(push->channel)) { + // Reuse existing WLC static pb for initialization + UVM_ASSERT(!uvm_channel_manager_is_wlc_ready(push->channel->pool->manager)); + return push->channel->conf_computing.static_pb_unprotected_sysmem_cpu; + } + + pushbuffer_base = uvm_rm_mem_get_cpu_va(pushbuffer->memory_unprotected_sysmem); + + return pushbuffer_base + uvm_pushbuffer_get_offset_for_push(pushbuffer, push); +} + +NvU64 uvm_pushbuffer_get_unprotected_gpu_va_for_push(uvm_pushbuffer_t *pushbuffer, uvm_push_t *push) +{ + NvU64 pushbuffer_base; + + if (uvm_channel_is_wlc(push->channel)) { + // Reuse existing WLC static pb for initialization + UVM_ASSERT(!uvm_channel_manager_is_wlc_ready(push->channel->pool->manager)); + return uvm_rm_mem_get_gpu_uvm_va(push->channel->conf_computing.static_pb_unprotected_sysmem, + uvm_push_get_gpu(push)); + } + + pushbuffer_base = uvm_rm_mem_get_gpu_uvm_va(pushbuffer->memory_unprotected_sysmem, uvm_push_get_gpu(push)); return pushbuffer_base + uvm_pushbuffer_get_offset_for_push(pushbuffer, push); } void uvm_pushbuffer_end_push(uvm_pushbuffer_t *pushbuffer, uvm_push_t *push, uvm_gpfifo_entry_t *gpfifo) { - uvm_pushbuffer_chunk_t *chunk = gpfifo_to_chunk(pushbuffer, gpfifo); + uvm_pushbuffer_chunk_t *chunk; + + if (uvm_channel_is_wlc(push->channel)) { + // WLC channels use static pushbuffer and don't count towards max + // concurrent pushes. Initializing the list as head makes sure the + // deletion in "uvm_pushbuffer_mark_completed" doesn't crash. + INIT_LIST_HEAD(&gpfifo->pending_list_node); + return; + } + + chunk = gpfifo_to_chunk(pushbuffer, gpfifo); uvm_channel_pool_assert_locked(push->channel->pool); @@ -513,3 +679,10 @@ { return uvm_rm_mem_get_gpu_uvm_va(pushbuffer->memory, pushbuffer->channel_manager->gpu); } + +NvU64 uvm_pushbuffer_get_sec2_gpu_va_base(uvm_pushbuffer_t *pushbuffer) +{ + UVM_ASSERT(uvm_conf_computing_mode_enabled(pushbuffer->channel_manager->gpu)); + + return uvm_rm_mem_get_gpu_uvm_va(pushbuffer->memory_unprotected_sysmem, pushbuffer->channel_manager->gpu); +} diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/kernel-open/nvidia-uvm/uvm_pushbuffer.h nvidia-open-gpu-kernel-modules-535.161.08/kernel-open/nvidia-uvm/uvm_pushbuffer.h --- nvidia-open-gpu-kernel-modules-525.147.05/kernel-open/nvidia-uvm/uvm_pushbuffer.h 2023-10-25 20:33:37.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/kernel-open/nvidia-uvm/uvm_pushbuffer.h 2024-03-05 22:25:55.000000000 +0000 @@ -1,5 +1,5 @@ /******************************************************************************* - Copyright (c) 2015-2022 NVIDIA Corporation + Copyright (c) 2015-2023 NVIDIA Corporation Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation files (the "Software"), to @@ -155,6 +155,42 @@ // uvm_push_end(). #define UVM_PUSH_MAX_CONCURRENT_PUSHES UVM_PUSHBUFFER_CHUNKS +// Push space needed for static part for the WLC schedule, as initialized in +// 'setup_wlc_schedule': +// * CE decrypt (of WLC PB): 56B +// * WFI: 8B +// Total: 64B +// +// Push space needed for secure work launch is 364B. The push is constructed +// in 'internal_channel_submit_work_indirect' and 'uvm_channel_end_push' +// * CE decrypt (of indirect PB): 56B +// * memset_8 (indirect GPFIFO entry): 44B +// * semaphore release (indirect GPPUT): 24B +// * semaphore release (indirect doorbell): 24B +// Appendix added in 'uvm_channel_end_push': +// * semaphore release (WLC tracking): 168B +// * semaphore release (payload): 24B +// * notifier memset: 40B +// * payload encryption: 64B +// * notifier memset: 40B +// * semaphore increment (LCIC GPPUT): 24B +// * semaphore release (LCIC doorbell): 24B +// Total: 364B +#define UVM_MAX_WLC_PUSH_SIZE (364) + +// Push space needed for static LCIC schedule, as initialized in +// 'setup_lcic_schedule': +// * WFI: 8B +// * semaphore increment (WLC GPPUT): 24B +// * semaphore increment (WLC GPPUT): 24B +// * semaphore increment (LCIC tracking): 160B +// * semaphore increment (payload): 24B +// * notifier memcopy: 36B +// * payload encryption: 64B +// * notifier memcopy: 36B +// Total: 216B +#define UVM_LCIC_PUSH_SIZE (216) + typedef struct { // Offset within the chunk of where a next push should begin if there is @@ -176,6 +212,12 @@ // Memory allocation backing the pushbuffer uvm_rm_mem_t *memory; + // Mirror image of memory in dma sysmem + uvm_rm_mem_t *memory_unprotected_sysmem; + + // Secure sysmem backing memory + void *memory_protected_sysmem; + // Array of the pushbuffer chunks uvm_pushbuffer_chunk_t chunks[UVM_PUSHBUFFER_CHUNKS]; @@ -216,11 +258,17 @@ // Complete a pending push // Updates the chunk state the pending push used -void uvm_pushbuffer_mark_completed(uvm_pushbuffer_t *pushbuffer, uvm_gpfifo_entry_t *gpfifo); +void uvm_pushbuffer_mark_completed(uvm_channel_t *channel, uvm_gpfifo_entry_t *gpfifo); // Get the GPU VA for an ongoing push NvU64 uvm_pushbuffer_get_gpu_va_for_push(uvm_pushbuffer_t *pushbuffer, uvm_push_t *push); +// Get the CPU VA for encrypted sysmem mirror +void *uvm_pushbuffer_get_unprotected_cpu_va_for_push(uvm_pushbuffer_t *pushbuffer, uvm_push_t *push); + +// Get the GPU VA for encrypted sysmem mirror +NvU64 uvm_pushbuffer_get_unprotected_gpu_va_for_push(uvm_pushbuffer_t *pushbuffer, uvm_push_t *push); + // Get the offset of the beginning of the push from the base of the pushbuffer allocation NvU32 uvm_pushbuffer_get_offset_for_push(uvm_pushbuffer_t *pushbuffer, uvm_push_t *push); @@ -239,4 +287,8 @@ // Helper to retrieve the pushbuffer->memory GPU VA. NvU64 uvm_pushbuffer_get_gpu_va_base(uvm_pushbuffer_t *pushbuffer); +// SEC2 variant to retrieve GPU VA for push location. +// Unlike other channels, SEC2 uses signed pushes in unprotected sysmem. +NvU64 uvm_pushbuffer_get_sec2_gpu_va_base(uvm_pushbuffer_t *pushbuffer); + #endif // __UVM_PUSHBUFFER_H__ diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/kernel-open/nvidia-uvm/uvm_range_allocator_test.c nvidia-open-gpu-kernel-modules-535.161.08/kernel-open/nvidia-uvm/uvm_range_allocator_test.c --- nvidia-open-gpu-kernel-modules-525.147.05/kernel-open/nvidia-uvm/uvm_range_allocator_test.c 2023-10-25 20:33:42.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/kernel-open/nvidia-uvm/uvm_range_allocator_test.c 2024-03-05 22:26:06.000000000 +0000 @@ -78,7 +78,7 @@ return size; } -#define BASIC_TEST_SIZE (1024ull * 1024 * 1024) +#define BASIC_TEST_SIZE UVM_SIZE_1GB #define BASIC_TEST_MAX_ALLOCS (128) // Check that a specific range is free in the allocator diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/kernel-open/nvidia-uvm/uvm_range_group.c nvidia-open-gpu-kernel-modules-535.161.08/kernel-open/nvidia-uvm/uvm_range_group.c --- nvidia-open-gpu-kernel-modules-525.147.05/kernel-open/nvidia-uvm/uvm_range_group.c 2023-10-25 20:33:35.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/kernel-open/nvidia-uvm/uvm_range_group.c 2024-03-05 22:25:53.000000000 +0000 @@ -264,7 +264,6 @@ return NV_ERR_NO_MEMORY; uvm_assert_rwsem_locked(&va_range->va_space->lock); - va_block_context->policy = uvm_va_range_get_policy(va_range); // Iterate over blocks, populating them if necessary for (i = uvm_va_range_block_index(va_range, start); i <= uvm_va_range_block_index(va_range, end); ++i) { diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/kernel-open/nvidia-uvm/uvm_rm_mem.c nvidia-open-gpu-kernel-modules-535.161.08/kernel-open/nvidia-uvm/uvm_rm_mem.c --- nvidia-open-gpu-kernel-modules-525.147.05/kernel-open/nvidia-uvm/uvm_rm_mem.c 2023-10-25 20:33:34.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/kernel-open/nvidia-uvm/uvm_rm_mem.c 2024-03-05 22:25:50.000000000 +0000 @@ -102,12 +102,21 @@ return rm_mem->proxy_vas[uvm_global_id_value(gpu->global_id)]; } -NvU64 uvm_rm_mem_get_gpu_va(uvm_rm_mem_t *rm_mem, uvm_gpu_t *gpu, bool is_proxy_va_space) +uvm_gpu_address_t uvm_rm_mem_get_gpu_va(uvm_rm_mem_t *rm_mem, uvm_gpu_t *gpu, bool is_proxy_va_space) { + uvm_gpu_address_t gpu_va = {0}; + + gpu_va.aperture = UVM_APERTURE_MAX; + gpu_va.is_virtual = true; + if (uvm_conf_computing_mode_enabled(gpu) && (rm_mem->type == UVM_RM_MEM_TYPE_SYS)) + gpu_va.is_unprotected = true; + if (is_proxy_va_space) - return uvm_rm_mem_get_gpu_proxy_va(rm_mem, gpu); + gpu_va.address = uvm_rm_mem_get_gpu_proxy_va(rm_mem, gpu); else - return uvm_rm_mem_get_gpu_uvm_va(rm_mem, gpu); + gpu_va.address = uvm_rm_mem_get_gpu_uvm_va(rm_mem, gpu); + + return gpu_va; } void *uvm_rm_mem_get_cpu_va(uvm_rm_mem_t *rm_mem) @@ -199,6 +208,9 @@ if (rm_mem == NULL) return NV_ERR_NO_MEMORY; + if (!uvm_conf_computing_mode_enabled(gpu) || type == UVM_RM_MEM_TYPE_SYS) + alloc_info.bUnprotected = NV_TRUE; + alloc_info.alignment = gpu_alignment; if (type == UVM_RM_MEM_TYPE_SYS) @@ -245,6 +257,8 @@ gpu = rm_mem->gpu_owner; gpu_va = uvm_rm_mem_get_gpu_uvm_va(rm_mem, gpu); + if (uvm_conf_computing_mode_enabled(gpu)) + UVM_ASSERT(rm_mem->type == UVM_RM_MEM_TYPE_SYS); status = uvm_rm_locked_call(nvUvmInterfaceMemoryCpuMap(gpu->rm_address_space, gpu_va, @@ -284,12 +298,12 @@ UVM_ASSERT(rm_mem); UVM_ASSERT(gpu); - // Peer mappings not supported yet - UVM_ASSERT(rm_mem->type == UVM_RM_MEM_TYPE_SYS); - if (uvm_rm_mem_mapped_on_gpu(rm_mem, gpu)) return NV_OK; + // Peer mappings are not supported yet + UVM_ASSERT(rm_mem->type == UVM_RM_MEM_TYPE_SYS); + gpu_owner = rm_mem->gpu_owner; gpu_owner_va = uvm_rm_mem_get_gpu_uvm_va(rm_mem, gpu_owner); @@ -334,8 +348,9 @@ UVM_ASSERT(rm_mem); UVM_ASSERT(gpu); - // Cannot unmap from the gpu that owns the allocation. - UVM_ASSERT_MSG(rm_mem->gpu_owner != gpu, "GPU %s\n", uvm_gpu_name(gpu)); + // The GPU owner mapping remains valid until the memory is freed. + if (gpu == rm_mem->gpu_owner) + return; rm_mem_unmap_gpu(rm_mem, gpu); } diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/kernel-open/nvidia-uvm/uvm_rm_mem.h nvidia-open-gpu-kernel-modules-535.161.08/kernel-open/nvidia-uvm/uvm_rm_mem.h --- nvidia-open-gpu-kernel-modules-525.147.05/kernel-open/nvidia-uvm/uvm_rm_mem.h 2023-10-25 20:33:34.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/kernel-open/nvidia-uvm/uvm_rm_mem.h 2024-03-05 22:25:50.000000000 +0000 @@ -27,6 +27,7 @@ #include "uvm_forward_decl.h" #include "uvm_processors.h" #include "uvm_test_ioctl.h" +#include "uvm_hal_types.h" typedef enum { @@ -120,8 +121,9 @@ // Map/Unmap on UVM's internal address space of a GPU. In SR-IOV heavy the // operation is also applied on the GPU's proxy address space. // -// Supported only for sysmem (UVM_RM_MEM_TYPE_SYS). The GPU has to be different -// from the one the memory was originally allocated for. +// Mapping/unmapping on the GPU owner, or mapping on an already mapped GPU, are +// no-ops. Mapping/unmapping on a GPU different from the owner is only supported +// for system memory. // // Locking same as uvm_rm_mem_alloc() NV_STATUS uvm_rm_mem_map_gpu(uvm_rm_mem_t *rm_mem, uvm_gpu_t *gpu, NvU64 gpu_alignment); @@ -142,9 +144,7 @@ // Get the GPU VA of the given memory in UVM's internal address space (if the // flag is false), or proxy address space (if flag is true). -NvU64 uvm_rm_mem_get_gpu_va(uvm_rm_mem_t *rm_mem, - uvm_gpu_t *gpu, - bool is_proxy_va_space); +uvm_gpu_address_t uvm_rm_mem_get_gpu_va(uvm_rm_mem_t *rm_mem, uvm_gpu_t *gpu, bool is_proxy_va_space); // Query if the memory is mapped on the CPU, GPU (UVM internal/kernel address // space), or GPU (proxy address space) diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/kernel-open/nvidia-uvm/uvm_rm_mem_test.c nvidia-open-gpu-kernel-modules-535.161.08/kernel-open/nvidia-uvm/uvm_rm_mem_test.c --- nvidia-open-gpu-kernel-modules-525.147.05/kernel-open/nvidia-uvm/uvm_rm_mem_test.c 2023-10-25 20:33:42.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/kernel-open/nvidia-uvm/uvm_rm_mem_test.c 2024-03-05 22:26:06.000000000 +0000 @@ -64,10 +64,9 @@ { // Alignment requirements only apply to mappings in the UVM-owned VA space if (alignment != 0) { - bool is_proxy_va_space = false; - NvU64 gpu_va = uvm_rm_mem_get_gpu_va(rm_mem, gpu, is_proxy_va_space); + NvU64 gpu_uvm_va = uvm_rm_mem_get_gpu_uvm_va(rm_mem, gpu); - TEST_CHECK_RET(IS_ALIGNED(gpu_va, alignment)); + TEST_CHECK_RET(IS_ALIGNED(gpu_uvm_va, alignment)); } return NV_OK; @@ -76,20 +75,51 @@ static NV_STATUS map_gpu_owner(uvm_rm_mem_t *rm_mem, NvU64 alignment) { uvm_gpu_t *gpu = rm_mem->gpu_owner; + NvU64 gpu_uvm_va; + NvU64 gpu_proxy_va = 0; // The memory should have been automatically mapped in the GPU owner TEST_CHECK_RET(uvm_rm_mem_mapped_on_gpu(rm_mem, gpu)); + gpu_uvm_va = uvm_rm_mem_get_gpu_uvm_va(rm_mem, gpu); + // In SR-IOV heavy, there are two VA spaces per GPU, so there are two // mappings for a single rm_mem object on a GPU, even if the memory is // located in vidmem. - TEST_CHECK_RET(uvm_rm_mem_mapped_on_gpu_proxy(rm_mem, gpu) == uvm_gpu_uses_proxy_channel_pool(gpu)); + if (uvm_gpu_uses_proxy_channel_pool(gpu)) { + TEST_CHECK_RET(uvm_rm_mem_mapped_on_gpu_proxy(rm_mem, gpu)); + + gpu_proxy_va = uvm_rm_mem_get_gpu_proxy_va(rm_mem, gpu); + } + else { + TEST_CHECK_RET(!uvm_rm_mem_mapped_on_gpu_proxy(rm_mem, gpu)); + } TEST_NV_CHECK_RET(check_alignment(rm_mem, gpu, alignment)); - // Explicitly mapping or unmapping to the GPU that owns the allocation is - // not allowed, so the testing related to GPU owners is simpler than that of - // other GPUs. + // Mappings are not ref counted, so additional map calls are no-ops; the + // GPU VA should remain the same for all the applicable VA spaces. + TEST_NV_CHECK_RET(uvm_rm_mem_map_gpu(rm_mem, gpu, alignment)); + + TEST_CHECK_RET(gpu_uvm_va == uvm_rm_mem_get_gpu_uvm_va(rm_mem, gpu)); + + if (uvm_gpu_uses_proxy_channel_pool(gpu)) + TEST_CHECK_RET(gpu_proxy_va == uvm_rm_mem_get_gpu_proxy_va(rm_mem, gpu)); + + // Unmapping the GPU owner is a no-op + uvm_rm_mem_unmap_gpu(rm_mem, gpu); + + TEST_CHECK_RET(uvm_rm_mem_mapped_on_gpu(rm_mem, gpu)); + TEST_CHECK_RET(gpu_uvm_va == uvm_rm_mem_get_gpu_uvm_va(rm_mem, gpu)); + + if (uvm_gpu_uses_proxy_channel_pool(gpu)) { + TEST_CHECK_RET(uvm_rm_mem_mapped_on_gpu_proxy(rm_mem, gpu)); + TEST_CHECK_RET(gpu_proxy_va == uvm_rm_mem_get_gpu_proxy_va(rm_mem, gpu)); + } + else { + TEST_CHECK_RET(!uvm_rm_mem_mapped_on_gpu_proxy(rm_mem, gpu)); + } + return NV_OK; } @@ -165,12 +195,16 @@ for (i = 0; i < ARRAY_SIZE(sizes); ++i) { for (j = 0; j < ARRAY_SIZE(mem_types); ++j) { for (k = 0; k < ARRAY_SIZE(alignments); ++k) { + bool test_cpu_mappings = true; // Create an allocation in the GPU's address space TEST_NV_CHECK_RET(uvm_rm_mem_alloc(gpu, mem_types[j], sizes[i], alignments[k], &rm_mem)); + test_cpu_mappings = mem_types[j] == UVM_RM_MEM_TYPE_SYS || + !uvm_conf_computing_mode_enabled(gpu); // Test CPU mappings - TEST_NV_CHECK_GOTO(map_cpu(rm_mem), error); + if (test_cpu_mappings) + TEST_NV_CHECK_GOTO(map_cpu(rm_mem), error); // Test mappings in the GPU owning the allocation TEST_NV_CHECK_GOTO(map_gpu_owner(rm_mem, alignments[k]), error); diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/kernel-open/nvidia-uvm/uvm_sec2_test.c nvidia-open-gpu-kernel-modules-535.161.08/kernel-open/nvidia-uvm/uvm_sec2_test.c --- nvidia-open-gpu-kernel-modules-525.147.05/kernel-open/nvidia-uvm/uvm_sec2_test.c 1970-01-01 00:00:00.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/kernel-open/nvidia-uvm/uvm_sec2_test.c 2024-03-05 22:25:40.000000000 +0000 @@ -0,0 +1,571 @@ +/******************************************************************************* + Copyright (c) 2021-2023 NVIDIA Corporation + + Permission is hereby granted, free of charge, to any person obtaining a copy + of this software and associated documentation files (the "Software"), to + deal in the Software without restriction, including without limitation the + rights to use, copy, modify, merge, publish, distribute, sublicense, and/or + sell copies of the Software, and to permit persons to whom the Software is + furnished to do so, subject to the following conditions: + + The above copyright notice and this permission notice shall be + included in all copies or substantial portions of the Software. + + THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + DEALINGS IN THE SOFTWARE. + +*******************************************************************************/ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "nv_uvm_interface.h" + +typedef struct test_sem_mem_t { + void *cpu_va; + NvU64 gpu_va; + + union { + uvm_mem_t *uvm_mem; + uvm_rm_mem_t *rm_mem; + }; +} test_sem_mem; + +static NV_STATUS test_semaphore_alloc_uvm_rm_mem(uvm_gpu_t *gpu, const size_t size, test_sem_mem *mem_out) +{ + NV_STATUS status; + uvm_rm_mem_t *mem = NULL; + NvU64 gpu_va; + + status = uvm_rm_mem_alloc_and_map_cpu(gpu, UVM_RM_MEM_TYPE_SYS, size, 0, &mem); + TEST_NV_CHECK_RET(status); + + gpu_va = uvm_rm_mem_get_gpu_uvm_va(mem, gpu); + TEST_CHECK_GOTO(gpu_va < gpu->parent->max_host_va, error); + + mem_out->cpu_va = uvm_rm_mem_get_cpu_va(mem); + mem_out->gpu_va = gpu_va; + mem_out->rm_mem = mem; + + return NV_OK; + +error: + uvm_rm_mem_free(mem); + return status; +} + +static NV_STATUS test_semaphore_alloc_sem(uvm_gpu_t *gpu, const size_t size, test_sem_mem *mem_out) +{ + NV_STATUS status = NV_OK; + uvm_mem_t *mem = NULL; + NvU64 gpu_va; + + TEST_NV_CHECK_RET(uvm_mem_alloc_sysmem_dma(size, gpu, current->mm, &mem)); + + TEST_NV_CHECK_GOTO(uvm_mem_map_gpu_kernel(mem, gpu), error); + gpu_va = uvm_mem_get_gpu_va_kernel(mem, gpu); + + // Use an RM allocation when SEC2 cannot address the semaphore. + // SEC2 VA width is similar to Host's. + if (gpu_va >= gpu->parent->max_host_va) { + uvm_mem_free(mem); + return test_semaphore_alloc_uvm_rm_mem(gpu, size, mem_out); + } + + // This semaphore resides in the uvm_mem region, i.e., it has the GPU VA + // MSbit set. The intent is to validate semaphore operations when the + // semaphore's VA is in the high-end of the GPU effective virtual address + // space spectrum, i.e., its VA upper-bit is set. + TEST_CHECK_GOTO(gpu_va & (1ULL << (gpu->address_space_tree.hal->num_va_bits() - 1)), error); + + TEST_NV_CHECK_GOTO(uvm_mem_map_cpu_kernel(mem), error); + + mem_out->cpu_va = uvm_mem_get_cpu_addr_kernel(mem); + mem_out->gpu_va = gpu_va; + mem_out->uvm_mem = mem; + + return NV_OK; + +error: + uvm_mem_free(mem); + return status; +} + +static void test_semaphore_free_sem(uvm_gpu_t *gpu, test_sem_mem *mem) +{ + if (mem->gpu_va >= gpu->parent->uvm_mem_va_base) + uvm_mem_free(mem->uvm_mem); + else + uvm_rm_mem_free(mem->rm_mem); +} + +// This test is similar to the test_semaphore_release() test in +// uvm_host_test.c, except that this one uses sec2_hal->semaphore_release(); +static NV_STATUS test_semaphore_release(uvm_gpu_t *gpu) +{ + NV_STATUS status; + test_sem_mem mem = { 0 }; + uvm_push_t push; + NvU32 value; + NvU32 payload = 0xA5A55A5A; + NvU32 *cpu_ptr; + + // Semaphore release needs 1 word (4 bytes). + const size_t size = sizeof(NvU32); + + status = test_semaphore_alloc_sem(gpu, size, &mem); + TEST_NV_CHECK_RET(status); + + // Initialize the payload. + cpu_ptr = (NvU32 *)mem.cpu_va; + *cpu_ptr = 0; + + status = uvm_push_begin(gpu->channel_manager, UVM_CHANNEL_TYPE_SEC2, &push, "semaphore_release test"); + TEST_NV_CHECK_GOTO(status, done); + + gpu->parent->sec2_hal->semaphore_release(&push, mem.gpu_va, payload); + + status = uvm_push_end_and_wait(&push); + TEST_NV_CHECK_GOTO(status, done); + + value = *cpu_ptr; + if (value != payload) { + UVM_TEST_PRINT("Semaphore payload = %u instead of %u, GPU %s\n", value, payload, uvm_gpu_name(gpu)); + status = NV_ERR_INVALID_STATE; + goto done; + } + +done: + test_semaphore_free_sem(gpu, &mem); + + return status; +} + +// This test is similiar to the test_semaphore_timestamp() test in +// uvm_ce_test.c, except that this one uses sec2_hal->semaphore_timestamp(); +static NV_STATUS test_semaphore_timestamp(uvm_gpu_t *gpu) +{ + NV_STATUS status; + test_sem_mem mem = { 0 }; + uvm_push_t push; + NvU32 i; + NvU64 *timestamp; + NvU64 last_timestamp = 0; + + // 2 iterations: + // 1: compare retrieved timestamp with 0; + // 2: compare retrieved timestamp with previous timestamp (obtained in 1). + const NvU32 iterations = 2; + + // The semaphore is 4 words long (16 bytes). + const size_t size = 16; + + // TODO: Bug 3804752: SEC2 semaphore timestamp is not implemented for + // Hopper + if (uvm_conf_computing_mode_is_hcc(gpu)) + return NV_OK; + + status = test_semaphore_alloc_sem(gpu, size, &mem); + TEST_NV_CHECK_RET(status); + + timestamp = (NvU64 *)mem.cpu_va; + TEST_CHECK_GOTO(timestamp != NULL, done); + memset(timestamp, 0, size); + + // Shift the timestamp pointer to where the semaphore timestamp info is. + timestamp += 1; + + for (i = 0; i < iterations; i++) { + status = uvm_push_begin(gpu->channel_manager, + UVM_CHANNEL_TYPE_SEC2, + &push, + "semaphore_timestamp test, iter: %u", + i); + TEST_NV_CHECK_GOTO(status, done); + + gpu->parent->sec2_hal->semaphore_timestamp(&push, mem.gpu_va); + + status = uvm_push_end_and_wait(&push); + TEST_NV_CHECK_GOTO(status, done); + + TEST_CHECK_GOTO(*timestamp != 0, done); + TEST_CHECK_GOTO(*timestamp >= last_timestamp, done); + last_timestamp = *timestamp; + } + +done: + test_semaphore_free_sem(gpu, &mem); + + return status; +} + +typedef enum +{ + MEM_ALLOC_TYPE_SYSMEM_DMA, + MEM_ALLOC_TYPE_SYSMEM_PROTECTED, + MEM_ALLOC_TYPE_VIDMEM_PROTECTED +} mem_alloc_type_t; + +static bool mem_match(uvm_mem_t *mem1, uvm_mem_t *mem2) +{ + void *mem1_addr; + void *mem2_addr; + + UVM_ASSERT(uvm_mem_is_sysmem(mem1)); + UVM_ASSERT(uvm_mem_is_sysmem(mem2)); + UVM_ASSERT(mem1->size == mem2->size); + + mem1_addr = uvm_mem_get_cpu_addr_kernel(mem1); + mem2_addr = uvm_mem_get_cpu_addr_kernel(mem2); + + return !memcmp(mem1_addr, mem2_addr, mem1->size); +} + +static NV_STATUS ce_memset_gpu(uvm_gpu_t *gpu, uvm_mem_t *mem, size_t size, NvU32 val) +{ + uvm_push_t push; + + TEST_NV_CHECK_RET(uvm_push_begin(gpu->channel_manager, + UVM_CHANNEL_TYPE_GPU_INTERNAL, + &push, + "VPR memset")); + + gpu->parent->ce_hal->memset_4(&push, uvm_mem_gpu_address_virtual_kernel(mem, gpu), val, size); + + TEST_NV_CHECK_RET(uvm_push_end_and_wait(&push)); + + return NV_OK; +} + +static void write_range_cpu(uvm_mem_t *mem, size_t size, NvU64 base_val) +{ + char *start, *end; + + UVM_ASSERT(uvm_mem_is_sysmem(mem)); + + start = uvm_mem_get_cpu_addr_kernel(mem); + end = start + size; + + for (; start < end; start += sizeof(NvU64)) + *(NvU64 *) start = base_val++; +} + +static NV_STATUS alloc_and_init_mem(uvm_gpu_t *gpu, uvm_mem_t **mem, size_t size, mem_alloc_type_t type) +{ + NV_STATUS status = NV_OK; + + UVM_ASSERT(mem); + + *mem = NULL; + + if (type == MEM_ALLOC_TYPE_VIDMEM_PROTECTED) { + TEST_NV_CHECK_RET(uvm_mem_alloc_vidmem(size, gpu, mem)); + TEST_NV_CHECK_GOTO(uvm_mem_map_gpu_kernel(*mem, gpu), err); + TEST_NV_CHECK_GOTO(ce_memset_gpu(gpu, *mem, size, 0xdead), err); + } + else { + if (type == MEM_ALLOC_TYPE_SYSMEM_DMA) { + TEST_NV_CHECK_RET(uvm_mem_alloc_sysmem_dma(size, gpu, NULL, mem)); + TEST_NV_CHECK_GOTO(uvm_mem_map_gpu_kernel(*mem, gpu), err); + } + else { + TEST_NV_CHECK_RET(uvm_mem_alloc_sysmem(size, NULL, mem)); + } + + TEST_NV_CHECK_GOTO(uvm_mem_map_cpu_kernel(*mem), err); + write_range_cpu(*mem, size, 0xdeaddead); + } + + return NV_OK; + +err: + uvm_mem_free(*mem); + return status; +} + +static void cpu_encrypt(uvm_channel_t *channel, + uvm_mem_t *dst_mem, + uvm_mem_t *src_mem, + uvm_mem_t *auth_tag_mem, + size_t size, + size_t copy_size) +{ + size_t i; + void *src_plain = uvm_mem_get_cpu_addr_kernel(src_mem); + void *dst_cipher = uvm_mem_get_cpu_addr_kernel(dst_mem); + void *auth_tag_buffer = uvm_mem_get_cpu_addr_kernel(auth_tag_mem); + + UVM_ASSERT(IS_ALIGNED(size, copy_size)); + + for (i = 0; i < size / copy_size; i++) { + uvm_conf_computing_cpu_encrypt(channel, dst_cipher, src_plain, NULL, copy_size, auth_tag_buffer); + + src_plain = (char *) src_plain + copy_size; + dst_cipher = (char *) dst_cipher + copy_size; + auth_tag_buffer = (char *) auth_tag_buffer + UVM_CONF_COMPUTING_AUTH_TAG_SIZE; + } +} + +static NV_STATUS cpu_decrypt(uvm_channel_t *channel, + uvm_mem_t *dst_mem, + uvm_mem_t *src_mem, + UvmCslIv *decrypt_iv, + uvm_mem_t *auth_tag_mem, + size_t size, + size_t copy_size) +{ + size_t i; + void *src_cipher = uvm_mem_get_cpu_addr_kernel(src_mem); + void *dst_plain = uvm_mem_get_cpu_addr_kernel(dst_mem); + void *auth_tag_buffer = uvm_mem_get_cpu_addr_kernel(auth_tag_mem); + + UVM_ASSERT(IS_ALIGNED(size, copy_size)); + + for (i = 0; i < size / copy_size; i++) { + TEST_NV_CHECK_RET(uvm_conf_computing_cpu_decrypt(channel, + dst_plain, + src_cipher, + &decrypt_iv[i], + copy_size, + auth_tag_buffer)); + + dst_plain = (char *) dst_plain + copy_size; + src_cipher = (char *) src_cipher + copy_size; + auth_tag_buffer = (char *) auth_tag_buffer + UVM_CONF_COMPUTING_AUTH_TAG_SIZE; + } + + return NV_OK; +} + +// gpu_encrypt uses the Copy Engine for encryption, instead of SEC2. SEC2 does +// not support encryption. The following function is copied from uvm_ce_test.c +// and adapted to SEC2 tests. +static void gpu_encrypt(uvm_push_t *push, + uvm_mem_t *dst_mem, + uvm_mem_t *src_mem, + UvmCslIv *decrypt_iv, + uvm_mem_t *auth_tag_mem, + size_t size, + size_t copy_size) +{ + size_t i; + size_t num_iterations = size / copy_size; + uvm_gpu_t *gpu = uvm_push_get_gpu(push); + uvm_gpu_address_t dst_cipher_address = uvm_mem_gpu_address_virtual_kernel(dst_mem, gpu); + uvm_gpu_address_t src_plain_address = uvm_mem_gpu_address_virtual_kernel(src_mem, gpu); + uvm_gpu_address_t auth_tag_address = uvm_mem_gpu_address_virtual_kernel(auth_tag_mem, gpu); + + for (i = 0; i < num_iterations; i++) { + uvm_conf_computing_log_gpu_encryption(push->channel, decrypt_iv); + + if (i > 0) + uvm_push_set_flag(push, UVM_PUSH_FLAG_CE_NEXT_PIPELINED); + + uvm_push_set_flag(push, UVM_PUSH_FLAG_NEXT_MEMBAR_NONE); + + gpu->parent->ce_hal->encrypt(push, dst_cipher_address, src_plain_address, copy_size, auth_tag_address); + dst_cipher_address.address += copy_size; + src_plain_address.address += copy_size; + auth_tag_address.address += UVM_CONF_COMPUTING_AUTH_TAG_SIZE; + decrypt_iv++; + } +} + +static void gpu_decrypt(uvm_push_t *push, + uvm_mem_t *dst_mem, + uvm_mem_t *src_mem, + uvm_mem_t *auth_tag_mem, + size_t size, + size_t copy_size) +{ + size_t i; + size_t num_iterations = size / copy_size; + uvm_gpu_t *gpu = uvm_push_get_gpu(push); + uvm_gpu_address_t src_cipher_address = uvm_mem_gpu_address_virtual_kernel(src_mem, gpu); + uvm_gpu_address_t dst_plain_address = uvm_mem_gpu_address_virtual_kernel(dst_mem, gpu); + uvm_gpu_address_t auth_tag_gpu_address = uvm_mem_gpu_address_virtual_kernel(auth_tag_mem, gpu); + + UVM_ASSERT(IS_ALIGNED(size, copy_size)); + + for (i = 0; i < num_iterations; i++) { + uvm_push_set_flag(push, UVM_PUSH_FLAG_NEXT_MEMBAR_NONE); + gpu->parent->sec2_hal->decrypt(push, + dst_plain_address.address, + src_cipher_address.address, + copy_size, + auth_tag_gpu_address.address); + + dst_plain_address.address += copy_size; + src_cipher_address.address += copy_size; + auth_tag_gpu_address.address += UVM_CONF_COMPUTING_AUTH_TAG_SIZE; + } +} + +// This test depends on the CE for the encryption, so we assume tests from +// uvm_ce_test.c have successfully passed. +static NV_STATUS test_cpu_to_gpu_roundtrip(uvm_gpu_t *gpu, size_t copy_size, size_t size) +{ + NV_STATUS status = NV_OK; + uvm_mem_t *src_plain = NULL; + uvm_mem_t *src_cipher = NULL; + uvm_mem_t *dst_cipher = NULL; + uvm_mem_t *dst_plain = NULL; + uvm_mem_t *dst_plain_cpu = NULL; + uvm_mem_t *auth_tag_mem = NULL; + size_t auth_tag_buffer_size = (size / copy_size) * UVM_CONF_COMPUTING_AUTH_TAG_SIZE; + uvm_push_t push; + UvmCslIv *decrypt_iv; + + decrypt_iv = uvm_kvmalloc_zero((size / copy_size) * sizeof(UvmCslIv)); + if (!decrypt_iv) + return NV_ERR_NO_MEMORY; + + TEST_NV_CHECK_GOTO(alloc_and_init_mem(gpu, &src_plain, size, MEM_ALLOC_TYPE_SYSMEM_PROTECTED), out); + TEST_NV_CHECK_GOTO(alloc_and_init_mem(gpu, &src_cipher, size, MEM_ALLOC_TYPE_SYSMEM_DMA), out); + TEST_NV_CHECK_GOTO(alloc_and_init_mem(gpu, &dst_cipher, size, MEM_ALLOC_TYPE_SYSMEM_DMA), out); + TEST_NV_CHECK_GOTO(alloc_and_init_mem(gpu, &dst_plain, size, MEM_ALLOC_TYPE_VIDMEM_PROTECTED), out); + TEST_NV_CHECK_GOTO(alloc_and_init_mem(gpu, &dst_plain_cpu, size, MEM_ALLOC_TYPE_SYSMEM_PROTECTED), out); + TEST_NV_CHECK_GOTO(alloc_and_init_mem(gpu, &auth_tag_mem, auth_tag_buffer_size, MEM_ALLOC_TYPE_SYSMEM_DMA), out); + + write_range_cpu(src_plain, size, uvm_get_stale_thread_id()); + + TEST_NV_CHECK_GOTO(uvm_push_begin(gpu->channel_manager, UVM_CHANNEL_TYPE_SEC2, &push, "enc(cpu)_dec(gpu)"), out); + + cpu_encrypt(push.channel, src_cipher, src_plain, auth_tag_mem, size, copy_size); + gpu_decrypt(&push, dst_plain, src_cipher, auth_tag_mem, size, copy_size); + + // Wait for SEC2 before launching the CE part. + // SEC2 is only allowed to release semaphores in unprotected sysmem, + // and CE can only acquire semaphores in protected vidmem. + TEST_NV_CHECK_GOTO(uvm_push_end_and_wait(&push), out); + + TEST_NV_CHECK_GOTO(uvm_push_begin(gpu->channel_manager, UVM_CHANNEL_TYPE_GPU_TO_CPU, &push, "enc(gpu)_dec(cpu)"), + out); + + gpu_encrypt(&push, dst_cipher, dst_plain, decrypt_iv, auth_tag_mem, size, copy_size); + + TEST_NV_CHECK_GOTO(uvm_push_end_and_wait(&push), out); + + TEST_CHECK_GOTO(!mem_match(src_plain, src_cipher), out); + TEST_CHECK_GOTO(!mem_match(dst_cipher, src_plain), out); + + TEST_NV_CHECK_GOTO(cpu_decrypt(push.channel, + dst_plain_cpu, + dst_cipher, + decrypt_iv, + auth_tag_mem, + size, + copy_size), + out); + + TEST_CHECK_GOTO(mem_match(src_plain, dst_plain_cpu), out); + +out: + uvm_mem_free(auth_tag_mem); + uvm_mem_free(dst_plain_cpu); + uvm_mem_free(dst_plain); + uvm_mem_free(dst_cipher); + uvm_mem_free(src_cipher); + uvm_mem_free(src_plain); + + uvm_kvfree(decrypt_iv); + + return status; +} + +static NV_STATUS test_encryption_decryption(uvm_gpu_t *gpu) +{ + size_t copy_sizes[] = { 4, 16, 512, 2 * UVM_SIZE_1KB, 4 * UVM_SIZE_1KB, 64 * UVM_SIZE_1KB, 2 * UVM_SIZE_1MB }; + int i; + + for (i = 0; i < ARRAY_SIZE(copy_sizes); i++) { + // Limit the number of methods in the gpu_encrypt()/gpu_decrypt() work + // submission. + size_t size = min(UVM_VA_BLOCK_SIZE, 256ull * copy_sizes[i]); + + // gpu_encrypt() and gpu_decrypt() iterate over a 'size' buffer. If + // copy_sizes[i] < 16 (SEC2 src and dst alignment requirement is + // 16-byte), SEC2 and our HAL implementation assert/fail. When + // copy_sizes[i] < 16, we only perform a single copy_sizes[i] copy. + if (copy_sizes[i] < 16) + size = copy_sizes[i]; + + UVM_ASSERT(size % copy_sizes[i] == 0); + + TEST_NV_CHECK_RET(test_cpu_to_gpu_roundtrip(gpu, copy_sizes[i], size)); + } + + return NV_OK; +} + +static NV_STATUS test_sec2(uvm_va_space_t *va_space) +{ + uvm_gpu_t *gpu; + + for_each_va_space_gpu(gpu, va_space) { + TEST_CHECK_RET(uvm_conf_computing_mode_enabled(gpu)); + + TEST_NV_CHECK_RET(test_semaphore_release(gpu)); + TEST_NV_CHECK_RET(test_semaphore_timestamp(gpu)); + TEST_NV_CHECK_RET(test_encryption_decryption(gpu)); + } + + return NV_OK; +} + +NV_STATUS uvm_test_sec2_sanity(UVM_TEST_SEC2_SANITY_PARAMS *params, struct file *filp) +{ + NV_STATUS status; + uvm_va_space_t *va_space = uvm_va_space_get(filp); + + uvm_va_space_down_read_rm(va_space); + + status = test_sec2(va_space); + if (status != NV_OK) + goto done; + +done: + uvm_va_space_up_read_rm(va_space); + + return status; +} + +NV_STATUS uvm_test_sec2_cpu_gpu_roundtrip(UVM_TEST_SEC2_CPU_GPU_ROUNDTRIP_PARAMS *params, struct file *filp) +{ + NV_STATUS status = NV_OK; + uvm_va_space_t *va_space = uvm_va_space_get(filp); + uvm_gpu_t *gpu; + + uvm_va_space_down_read(va_space); + + for_each_va_space_gpu(gpu, va_space) { + TEST_CHECK_RET(uvm_conf_computing_mode_enabled(gpu)); + + // To exercise certain SEC2 context save/restore races, do a looped + // decrypt with smaller copy sizes instead of larger copy sizes since we + // need SEC2 to context switch with pending work in different channels + // and smaller copies decrypt increases the probability of exercising + // SEC2 context switching. A single push of the entire size may not be + // enough to re-create this scenario since SEC2 doesn't preempt in the + // middle of the decrypt. + status = test_cpu_to_gpu_roundtrip(gpu, UVM_PAGE_SIZE_4K, UVM_VA_BLOCK_SIZE); + if (status != NV_OK) + goto done; + } + +done: + uvm_va_space_up_read(va_space); + + return status; +} diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/kernel-open/nvidia-uvm/uvm_test.c nvidia-open-gpu-kernel-modules-535.161.08/kernel-open/nvidia-uvm/uvm_test.c --- nvidia-open-gpu-kernel-modules-525.147.05/kernel-open/nvidia-uvm/uvm_test.c 2023-10-25 20:33:42.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/kernel-open/nvidia-uvm/uvm_test.c 2024-03-05 22:26:05.000000000 +0000 @@ -36,6 +36,7 @@ #include "uvm_mmu.h" #include "uvm_gpu_access_counters.h" #include "uvm_pmm_sysmem.h" +#include "uvm_migrate_pageable.h" static NV_STATUS uvm_test_get_gpu_ref_count(UVM_TEST_GET_GPU_REF_COUNT_PARAMS *params, struct file *filp) { @@ -300,7 +301,6 @@ UVM_ROUTE_CMD_STACK_INIT_CHECK(UVM_TEST_PMM_REVERSE_MAP, uvm_test_pmm_reverse_map); UVM_ROUTE_CMD_STACK_INIT_CHECK(UVM_TEST_PMM_INDIRECT_PEERS, uvm_test_pmm_indirect_peers); UVM_ROUTE_CMD_STACK_INIT_CHECK(UVM_TEST_VA_SPACE_MM_RETAIN, uvm_test_va_space_mm_retain); - UVM_ROUTE_CMD_STACK_INIT_CHECK(UVM_TEST_VA_SPACE_MM_DELAY_SHUTDOWN, uvm_test_va_space_mm_delay_shutdown); UVM_ROUTE_CMD_STACK_INIT_CHECK(UVM_TEST_PMM_CHUNK_WITH_ELEVATED_PAGE, uvm_test_pmm_chunk_with_elevated_page); UVM_ROUTE_CMD_STACK_INIT_CHECK(UVM_TEST_VA_SPACE_INJECT_ERROR, uvm_test_va_space_inject_error); UVM_ROUTE_CMD_STACK_INIT_CHECK(UVM_TEST_GET_GPU_TIME, uvm_test_get_gpu_time); @@ -324,13 +324,15 @@ UVM_ROUTE_CMD_STACK_INIT_CHECK(UVM_TEST_RB_TREE_RANDOM, uvm_test_rb_tree_random); UVM_ROUTE_CMD_STACK_NO_INIT_CHECK(UVM_TEST_GET_USER_SPACE_END_ADDRESS, uvm_test_get_user_space_end_address); UVM_ROUTE_CMD_STACK_NO_INIT_CHECK(UVM_TEST_GET_CPU_CHUNK_ALLOC_SIZES, uvm_test_get_cpu_chunk_allocation_sizes); - UVM_ROUTE_CMD_STACK_INIT_CHECK(UVM_TEST_HMM_SANITY, uvm_test_hmm_sanity); UVM_ROUTE_CMD_STACK_INIT_CHECK(UVM_TEST_VA_RANGE_INJECT_ADD_GPU_VA_SPACE_ERROR, uvm_test_va_range_inject_add_gpu_va_space_error); UVM_ROUTE_CMD_STACK_INIT_CHECK(UVM_TEST_DESTROY_GPU_VA_SPACE_DELAY, uvm_test_destroy_gpu_va_space_delay); + UVM_ROUTE_CMD_STACK_INIT_CHECK(UVM_TEST_SEC2_SANITY, uvm_test_sec2_sanity); + UVM_ROUTE_CMD_STACK_INIT_CHECK(UVM_TEST_SEC2_CPU_GPU_ROUNDTRIP, uvm_test_sec2_cpu_gpu_roundtrip); UVM_ROUTE_CMD_STACK_NO_INIT_CHECK(UVM_TEST_CGROUP_ACCOUNTING_SUPPORTED, uvm_test_cgroup_accounting_supported); - UVM_ROUTE_CMD_STACK_INIT_CHECK(UVM_TEST_HMM_INIT, uvm_test_hmm_init); UVM_ROUTE_CMD_STACK_INIT_CHECK(UVM_TEST_SPLIT_INVALIDATE_DELAY, uvm_test_split_invalidate_delay); + UVM_ROUTE_CMD_STACK_INIT_CHECK(UVM_TEST_CPU_CHUNK_API, uvm_test_cpu_chunk_api); + UVM_ROUTE_CMD_STACK_INIT_CHECK(UVM_TEST_SKIP_MIGRATE_VMA, uvm_test_skip_migrate_vma); } return -EINVAL; diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/kernel-open/nvidia-uvm/uvm_test.h nvidia-open-gpu-kernel-modules-535.161.08/kernel-open/nvidia-uvm/uvm_test.h --- nvidia-open-gpu-kernel-modules-525.147.05/kernel-open/nvidia-uvm/uvm_test.h 2023-10-25 20:33:42.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/kernel-open/nvidia-uvm/uvm_test.h 2024-03-05 22:26:05.000000000 +0000 @@ -187,5 +187,7 @@ NV_STATUS uvm_test_register_unload_state_buffer(UVM_TEST_REGISTER_UNLOAD_STATE_BUFFER_PARAMS *params, struct file *filp); NV_STATUS uvm_test_rb_tree_directed(UVM_TEST_RB_TREE_DIRECTED_PARAMS *params, struct file *filp); NV_STATUS uvm_test_rb_tree_random(UVM_TEST_RB_TREE_RANDOM_PARAMS *params, struct file *filp); -NV_STATUS uvm_test_hmm_sanity(UVM_TEST_HMM_SANITY_PARAMS *params, struct file *filp); +NV_STATUS uvm_test_sec2_sanity(UVM_TEST_SEC2_SANITY_PARAMS *params, struct file *filp); +NV_STATUS uvm_test_sec2_cpu_gpu_roundtrip(UVM_TEST_SEC2_CPU_GPU_ROUNDTRIP_PARAMS *params, struct file *filp); +NV_STATUS uvm_test_cpu_chunk_api(UVM_TEST_CPU_CHUNK_API_PARAMS *params, struct file *filp); #endif diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/kernel-open/nvidia-uvm/uvm_test_ioctl.h nvidia-open-gpu-kernel-modules-535.161.08/kernel-open/nvidia-uvm/uvm_test_ioctl.h --- nvidia-open-gpu-kernel-modules-525.147.05/kernel-open/nvidia-uvm/uvm_test_ioctl.h 2023-10-25 20:33:44.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/kernel-open/nvidia-uvm/uvm_test_ioctl.h 2024-03-05 22:26:07.000000000 +0000 @@ -28,6 +28,13 @@ #include "uvm_ioctl.h" #include "nv_uvm_types.h" +#define UVM_TEST_SKIP_MIGRATE_VMA UVM_TEST_IOCTL_BASE(103) +typedef struct +{ + NvBool skip; // In + NV_STATUS rmStatus; // Out +} UVM_TEST_SKIP_MIGRATE_VMA_PARAMS; + #ifdef __cplusplus extern "C" { #endif @@ -616,6 +623,7 @@ // Array of processors which have a virtual mapping covering lookup_address. NvProcessorUuid mapped_on[UVM_MAX_PROCESSORS]; // Out NvU32 mapping_type[UVM_MAX_PROCESSORS]; // Out + NvU64 mapping_physical_address[UVM_MAX_PROCESSORS] NV_ALIGN_BYTES(8); // Out NvU32 mapped_on_count; // Out // The size of the virtual mapping covering lookup_address on each @@ -1080,20 +1088,6 @@ NV_STATUS rmStatus; // Out } UVM_TEST_VA_SPACE_MM_RETAIN_PARAMS; -// Forces the VA space mm_shutdown callback to delay until more than one thread -// has entered the callback. This provides a high probability of exercising code -// to handle this race condition between exit_mmap and file close. -// -// The delay has an upper bound to prevent an infinite stall. -#define UVM_TEST_VA_SPACE_MM_DELAY_SHUTDOWN UVM_TEST_IOCTL_BASE(68) -typedef struct -{ - NvBool verbose; - - // NV_ERR_PAGE_TABLE_NOT_AVAIL if no va_space_mm is present - NV_STATUS rmStatus; -} UVM_TEST_VA_SPACE_MM_DELAY_SHUTDOWN_PARAMS; - #define UVM_TEST_PMM_CHUNK_WITH_ELEVATED_PAGE UVM_TEST_IOCTL_BASE(69) typedef struct { @@ -1370,10 +1364,6 @@ // Approximate duration for which to sleep with the va_space_mm retained. NvU64 sleep_us NV_ALIGN_BYTES(8); // In - // On success, this contains the value of mm->mm_users before mmput() is - // called. - NvU64 mm_users NV_ALIGN_BYTES(8); // Out - // NV_ERR_PAGE_TABLE_NOT_AVAIL Could not retain va_space_mm // (uvm_va_space_mm_or_current_retain returned // NULL) @@ -1394,16 +1384,6 @@ NvU32 rmStatus; // Out } UVM_TEST_GET_CPU_CHUNK_ALLOC_SIZES_PARAMS; -#define UVM_TEST_HMM_SANITY UVM_TEST_IOCTL_BASE(92) -typedef struct -{ - NvU64 hmm_address NV_ALIGN_BYTES(8); // In - NvU64 hmm_length NV_ALIGN_BYTES(8); // In - NvU64 uvm_address NV_ALIGN_BYTES(8); // In - NvU64 uvm_length NV_ALIGN_BYTES(8); // In - NV_STATUS rmStatus; // Out -} UVM_TEST_HMM_SANITY_PARAMS; - // Forces the next range covering the lookup_address to fail in // uvm_va_range_add_gpu_va_space() with an out-of-memory error. Only the next // uvm_va_range_add_gpu_va_space() will fail. Subsequent ones will succeed. @@ -1429,17 +1409,17 @@ NV_STATUS rmStatus; // Out } UVM_TEST_DESTROY_GPU_VA_SPACE_DELAY_PARAMS; -#define UVM_TEST_CGROUP_ACCOUNTING_SUPPORTED UVM_TEST_IOCTL_BASE(96) +#define UVM_TEST_SEC2_SANITY UVM_TEST_IOCTL_BASE(95) typedef struct { NV_STATUS rmStatus; // Out -} UVM_TEST_CGROUP_ACCOUNTING_SUPPORTED_PARAMS; +} UVM_TEST_SEC2_SANITY_PARAMS; -#define UVM_TEST_HMM_INIT UVM_TEST_IOCTL_BASE(97) +#define UVM_TEST_CGROUP_ACCOUNTING_SUPPORTED UVM_TEST_IOCTL_BASE(96) typedef struct { NV_STATUS rmStatus; // Out -} UVM_TEST_HMM_INIT_PARAMS; +} UVM_TEST_CGROUP_ACCOUNTING_SUPPORTED_PARAMS; #define UVM_TEST_SPLIT_INVALIDATE_DELAY UVM_TEST_IOCTL_BASE(98) typedef struct @@ -1448,6 +1428,19 @@ NV_STATUS rmStatus; // Out } UVM_TEST_SPLIT_INVALIDATE_DELAY_PARAMS; +// Tests the CSL/SEC2 encryption/decryption methods by doing a secure transfer +// of memory from CPU->GPU and a subsequent GPU->CPU transfer. +#define UVM_TEST_SEC2_CPU_GPU_ROUNDTRIP UVM_TEST_IOCTL_BASE(99) +typedef struct +{ + NV_STATUS rmStatus; // Out +} UVM_TEST_SEC2_CPU_GPU_ROUNDTRIP_PARAMS; + +#define UVM_TEST_CPU_CHUNK_API UVM_TEST_IOCTL_BASE(100) +typedef struct +{ + NV_STATUS rmStatus; // Out +} UVM_TEST_CPU_CHUNK_API_PARAMS; #ifdef __cplusplus } #endif diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/kernel-open/nvidia-uvm/uvm_thread_context.c nvidia-open-gpu-kernel-modules-535.161.08/kernel-open/nvidia-uvm/uvm_thread_context.c --- nvidia-open-gpu-kernel-modules-525.147.05/kernel-open/nvidia-uvm/uvm_thread_context.c 2023-10-25 20:33:37.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/kernel-open/nvidia-uvm/uvm_thread_context.c 2024-03-05 22:25:55.000000000 +0000 @@ -1,5 +1,5 @@ /******************************************************************************* - Copyright (c) 2015-2019 NVIDIA Corporation + Copyright (c) 2015-2023 NVIDIA Corporation Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation files (the "Software"), to @@ -498,6 +498,7 @@ uvm_thread_context_global_init(); thread_context->task = current; + thread_context->ignore_hmm_invalidate_va_block = NULL; table_entry = thread_context_non_interrupt_table_entry(&array_index); return thread_context_non_interrupt_add(thread_context, table_entry, array_index); } diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/kernel-open/nvidia-uvm/uvm_thread_context.h nvidia-open-gpu-kernel-modules-535.161.08/kernel-open/nvidia-uvm/uvm_thread_context.h --- nvidia-open-gpu-kernel-modules-525.147.05/kernel-open/nvidia-uvm/uvm_thread_context.h 2023-10-25 20:33:37.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/kernel-open/nvidia-uvm/uvm_thread_context.h 2024-03-05 22:25:55.000000000 +0000 @@ -1,5 +1,5 @@ /******************************************************************************* - Copyright (c) 2015-2019 NVIDIA Corporation + Copyright (c) 2015-2023 NVIDIA Corporation Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation files (the "Software"), to @@ -70,6 +70,15 @@ // This field is ignored in interrupt paths NvU32 array_index; + // Set if uvm_hmm_invalidate() callbacks should be ignored on this va_block. + // This needs to be set whenever the va_block lock is held and + // migrate_vma_setup() needs to be called since the "slow path" which + // calls try_to_migrate() doesn't pass the pgmap_owner. + uvm_va_block_t *ignore_hmm_invalidate_va_block; + + // Used to filter out invalidations we don't care about. + unsigned long hmm_invalidate_seqnum; + // Pointer to enclosing node (if any) in red-black tree // // This field is ignored in interrupt paths diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/kernel-open/nvidia-uvm/uvm_tools.c nvidia-open-gpu-kernel-modules-535.161.08/kernel-open/nvidia-uvm/uvm_tools.c --- nvidia-open-gpu-kernel-modules-525.147.05/kernel-open/nvidia-uvm/uvm_tools.c 2023-10-25 20:33:32.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/kernel-open/nvidia-uvm/uvm_tools.c 2024-03-05 22:25:48.000000000 +0000 @@ -1,5 +1,5 @@ /******************************************************************************* - Copyright (c) 2016-2022 NVIDIA Corporation + Copyright (c) 2016-2023 NVIDIA Corporation Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation files (the "Software"), to @@ -208,7 +208,6 @@ uvm_va_space_t *va_space; UVM_ASSERT(event_tracker->uvm_file); va_space = uvm_va_space_get(event_tracker->uvm_file); - UVM_ASSERT(uvm_va_space_initialized(va_space) == NV_OK); return va_space; } @@ -230,6 +229,24 @@ uvm_kvfree(pages); } +// This must be called with the mmap_lock held in read mode or better. +static NV_STATUS check_vmas(struct mm_struct *mm, NvU64 start_va, NvU64 size) +{ + struct vm_area_struct *vma; + NvU64 addr = start_va; + NvU64 region_end = start_va + size; + + do { + vma = find_vma(mm, addr); + if (!vma || !(addr >= vma->vm_start) || uvm_file_is_nvidia_uvm(vma->vm_file)) + return NV_ERR_INVALID_ARGUMENT; + + addr = vma->vm_end; + } while (addr < region_end); + + return NV_OK; +} + // Map virtual memory of data from [user_va, user_va + size) of current process into kernel. // Sets *addr to kernel mapping and *pages to the array of struct pages that contain the memory. static NV_STATUS map_user_pages(NvU64 user_va, NvU64 size, void **addr, struct page ***pages) @@ -238,7 +255,6 @@ long ret = 0; long num_pages; long i; - struct vm_area_struct **vmas = NULL; *addr = NULL; *pages = NULL; @@ -255,22 +271,30 @@ goto fail; } - vmas = uvm_kvmalloc(sizeof(struct vm_area_struct *) * num_pages); - if (vmas == NULL) { - status = NV_ERR_NO_MEMORY; + // Although uvm_down_read_mmap_lock() is preferable due to its participation + // in the UVM lock dependency tracker, it cannot be used here. That's + // because pin_user_pages() may fault in HMM pages which are GPU-resident. + // When that happens, the UVM page fault handler would record another + // mmap_read_lock() on the same thread as this one, leading to a false + // positive lock dependency report. + // + // Therefore, use the lower level nv_mmap_read_lock() here. + nv_mmap_read_lock(current->mm); + status = check_vmas(current->mm, user_va, size); + if (status != NV_OK) { + nv_mmap_read_unlock(current->mm); goto fail; } - - nv_mmap_read_lock(current->mm); - ret = NV_PIN_USER_PAGES(user_va, num_pages, FOLL_WRITE, *pages, vmas); + ret = NV_PIN_USER_PAGES(user_va, num_pages, FOLL_WRITE, *pages, NULL); nv_mmap_read_unlock(current->mm); + if (ret != num_pages) { status = NV_ERR_INVALID_ARGUMENT; goto fail; } for (i = 0; i < num_pages; i++) { - if (page_count((*pages)[i]) > MAX_PAGE_COUNT || uvm_file_is_nvidia_uvm(vmas[i]->vm_file)) { + if (page_count((*pages)[i]) > MAX_PAGE_COUNT) { status = NV_ERR_INVALID_ARGUMENT; goto fail; } @@ -280,15 +304,12 @@ if (*addr == NULL) goto fail; - uvm_kvfree(vmas); return NV_OK; fail: if (*pages == NULL) return status; - uvm_kvfree(vmas); - if (ret > 0) uvm_put_user_pages_dirty(*pages, ret); else if (ret < 0) @@ -1061,25 +1082,19 @@ } -void uvm_tools_broadcast_replay_sync(uvm_gpu_t *gpu, - NvU32 batch_id, - uvm_fault_client_type_t client_type) +void uvm_tools_broadcast_replay_sync(uvm_gpu_t *gpu, NvU32 batch_id, uvm_fault_client_type_t client_type) { UVM_ASSERT(!gpu->parent->has_clear_faulted_channel_method); if (!tools_is_event_enabled_in_any_va_space(UvmEventTypeGpuFaultReplay)) return; - record_replay_event_helper(gpu->id, - batch_id, - client_type, - NV_GETTIME(), - gpu->parent->host_hal->get_time(gpu)); + record_replay_event_helper(gpu->id, batch_id, client_type, NV_GETTIME(), gpu->parent->host_hal->get_time(gpu)); } void uvm_tools_broadcast_access_counter(uvm_gpu_t *gpu, const uvm_access_counter_buffer_entry_t *buffer_entry, - bool on_managed) + bool on_managed_phys) { UvmEventEntry entry; UvmEventTestAccessCounterInfo *info = &entry.testEventData.accessCounter; @@ -1098,6 +1113,7 @@ info->srcIndex = uvm_id_value(gpu->id); info->address = buffer_entry->address.address; info->isVirtual = buffer_entry->address.is_virtual? 1: 0; + if (buffer_entry->address.is_virtual) { info->instancePtr = buffer_entry->virtual_info.instance_ptr.address; info->instancePtrAperture = g_hal_to_tools_aperture_table[buffer_entry->virtual_info.instance_ptr.aperture]; @@ -1105,9 +1121,10 @@ } else { info->aperture = g_hal_to_tools_aperture_table[buffer_entry->address.aperture]; + info->physOnManaged = on_managed_phys? 1 : 0; } + info->isFromCpu = buffer_entry->counter_type == UVM_ACCESS_COUNTER_TYPE_MOMC? 1: 0; - info->onManaged = on_managed? 1 : 0; info->value = buffer_entry->counter_value; info->subGranularity = buffer_entry->sub_granularity; info->bank = buffer_entry->bank; @@ -1614,10 +1631,12 @@ goto fail; } - status = uvm_va_space_initialized(uvm_va_space_get(event_tracker->uvm_file)); - if (status != NV_OK) { + // We don't use uvm_fd_va_space() here because tools can work + // without an associated va_space_mm. + if (!uvm_fd_get_type(event_tracker->uvm_file, UVM_FD_VA_SPACE)) { fput(event_tracker->uvm_file); event_tracker->uvm_file = NULL; + status = NV_ERR_ILLEGAL_ACTION; goto fail; } @@ -1758,7 +1777,6 @@ uvm_assert_rwsem_locked_write(&g_tools_va_space_list_lock); uvm_assert_rwsem_locked_write(&va_space->perf_events.lock); uvm_assert_rwsem_locked_write(&va_space->tools.lock); - UVM_ASSERT(uvm_va_space_initialized(va_space) == NV_OK); status = tools_update_perf_events_callbacks(va_space); if (status != NV_OK) @@ -2016,12 +2034,10 @@ if (status != NV_OK) goto exit; - if (is_write) { - block_context = uvm_va_block_context_alloc(mm); - if (!block_context) { - status = NV_ERR_NO_MEMORY; - goto exit; - } + block_context = uvm_va_block_context_alloc(mm); + if (!block_context) { + status = NV_ERR_NO_MEMORY; + goto exit; } stage_addr = uvm_mem_get_cpu_addr_kernel(stage_mem); @@ -2044,17 +2060,32 @@ } } + if (mm) + uvm_down_read_mmap_lock(mm); + // The RM flavor of the lock is needed to perform ECC checks. uvm_va_space_down_read_rm(va_space); - status = uvm_va_block_find_create_managed(va_space, target_va_start, &block); - if (status != NV_OK) { - uvm_va_space_up_read_rm(va_space); - goto exit; - } + if (mm) + status = uvm_va_block_find_create(va_space, UVM_PAGE_ALIGN_DOWN(target_va_start), &block_context->hmm.vma, &block); + else + status = uvm_va_block_find_create_managed(va_space, UVM_PAGE_ALIGN_DOWN(target_va_start), &block); + + if (status != NV_OK) + goto unlock_and_exit; uvm_va_space_global_gpus(va_space, global_gpus); for_each_global_gpu_in_mask(gpu, global_gpus) { + + // When CC is enabled, the staging memory cannot be mapped on the + // GPU (it is protected sysmem), but it is still used to store the + // unencrypted version of the page contents when the page is + // resident on vidmem. + if (uvm_conf_computing_mode_enabled(gpu)) { + UVM_ASSERT(uvm_global_processor_mask_empty(retained_global_gpus)); + + break; + } if (uvm_global_processor_mask_test_and_set(retained_global_gpus, gpu->global_id)) continue; @@ -2068,10 +2099,15 @@ // (even if those mappings may never be used) as tools read/write is // not on a performance critical path. status = uvm_mem_map_gpu_kernel(stage_mem, gpu); - if (status != NV_OK) { - uvm_va_space_up_read_rm(va_space); - goto exit; - } + if (status != NV_OK) + goto unlock_and_exit; + } + + // Make sure a CPU resident page has an up to date struct page pointer. + if (uvm_va_block_is_hmm(block)) { + status = uvm_hmm_va_block_update_residency_info(block, mm, UVM_PAGE_ALIGN_DOWN(target_va_start), true); + if (status != NV_OK) + goto unlock_and_exit; } status = tools_access_va_block(block, block_context, target_va_start, bytes_now, is_write, stage_mem); @@ -2082,6 +2118,9 @@ status = uvm_global_mask_check_ecc_error(global_gpus); uvm_va_space_up_read_rm(va_space); + if (mm) + uvm_up_read_mmap_lock(mm); + if (status != NV_OK) goto exit; @@ -2107,6 +2146,13 @@ *bytes += bytes_now; } +unlock_and_exit: + if (status != NV_OK) { + uvm_va_space_up_read_rm(va_space); + if (mm) + uvm_up_read_mmap_lock(mm); + } + exit: uvm_va_block_context_free(block_context); diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/kernel-open/nvidia-uvm/uvm_tools.h nvidia-open-gpu-kernel-modules-535.161.08/kernel-open/nvidia-uvm/uvm_tools.h --- nvidia-open-gpu-kernel-modules-525.147.05/kernel-open/nvidia-uvm/uvm_tools.h 2023-10-25 20:33:32.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/kernel-open/nvidia-uvm/uvm_tools.h 2024-03-05 22:25:48.000000000 +0000 @@ -102,18 +102,13 @@ uvm_va_block_region_t region, const uvm_page_mask_t *page_mask); -void uvm_tools_broadcast_replay(uvm_gpu_t *gpu, - uvm_push_t *push, - NvU32 batch_id, - uvm_fault_client_type_t client_type); +void uvm_tools_broadcast_replay(uvm_gpu_t *gpu, uvm_push_t *push, NvU32 batch_id, uvm_fault_client_type_t client_type); -void uvm_tools_broadcast_replay_sync(uvm_gpu_t *gpu, - NvU32 batch_id, - uvm_fault_client_type_t client_type); +void uvm_tools_broadcast_replay_sync(uvm_gpu_t *gpu, NvU32 batch_id, uvm_fault_client_type_t client_type); void uvm_tools_broadcast_access_counter(uvm_gpu_t *gpu, const uvm_access_counter_buffer_entry_t *buffer_entry, - bool on_managed); + bool on_managed_phys); void uvm_tools_test_hmm_split_invalidate(uvm_va_space_t *va_space); diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/kernel-open/nvidia-uvm/uvm_tracker_test.c nvidia-open-gpu-kernel-modules-535.161.08/kernel-open/nvidia-uvm/uvm_tracker_test.c --- nvidia-open-gpu-kernel-modules-525.147.05/kernel-open/nvidia-uvm/uvm_tracker_test.c 2023-10-25 20:33:43.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/kernel-open/nvidia-uvm/uvm_tracker_test.c 2024-03-05 22:26:06.000000000 +0000 @@ -69,6 +69,14 @@ gpu = uvm_va_space_find_first_gpu(va_space); TEST_CHECK_RET(gpu != NULL); + // TODO: Bug 4008734: [UVM][HCC] Extend secure tracking semaphore mechanism + // to all semaphore + // This test allocates semaphore in vidmem and then releases it from the CPU + // SEC2 channels cannot target semaphores in vidmem. Moreover, CPU cannot + // directly release values to vidmem for CE channels. + if (uvm_conf_computing_mode_enabled(gpu)) + return NV_OK; + TEST_NV_CHECK_RET(uvm_gpu_semaphore_alloc(gpu->semaphore_pool, &sema)); uvm_tracker_init(&tracker); @@ -83,6 +91,13 @@ uvm_for_each_pool(pool, gpu->channel_manager) { uvm_channel_t *channel; + // Skip WLC channels as they are used for secure work launch + if (uvm_channel_pool_is_wlc(pool)) + continue; + + // Skip LCIC channels as those can't accept pushes + if (uvm_channel_pool_is_lcic(pool)) + continue; uvm_for_each_channel_in_pool(channel, pool) { uvm_push_t push; NvU64 semaphore_gpu_va; @@ -214,6 +229,9 @@ uvm_for_each_pool(pool, gpu->channel_manager) { uvm_channel_t *channel; + // Skip LCIC channels as those can't accept pushes + if (uvm_channel_pool_is_lcic(pool)) + continue; uvm_for_each_channel_in_pool(channel, pool) { uvm_push_t push; status = uvm_push_begin_on_channel(channel, &push, "Test push"); diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/kernel-open/nvidia-uvm/uvm_turing.c nvidia-open-gpu-kernel-modules-535.161.08/kernel-open/nvidia-uvm/uvm_turing.c --- nvidia-open-gpu-kernel-modules-525.147.05/kernel-open/nvidia-uvm/uvm_turing.c 2023-10-25 20:33:39.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/kernel-open/nvidia-uvm/uvm_turing.c 2024-03-05 22:25:56.000000000 +0000 @@ -1,5 +1,5 @@ /******************************************************************************* - Copyright (c) 2017-2021 NVIDIA Corporation + Copyright (c) 2017-2023 NVIDIA Corporation Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation files (the "Software"), to @@ -46,11 +46,13 @@ // A single top level PDE on Turing covers 128 TB and that's the minimum // size that can be used. parent_gpu->rm_va_base = 0; - parent_gpu->rm_va_size = 128ull * 1024 * 1024 * 1024 * 1024; + parent_gpu->rm_va_size = 128 * UVM_SIZE_1TB; - parent_gpu->uvm_mem_va_base = 384ull * 1024 * 1024 * 1024 * 1024; + parent_gpu->uvm_mem_va_base = 384 * UVM_SIZE_1TB; parent_gpu->uvm_mem_va_size = UVM_MEM_VA_SIZE; + parent_gpu->ce_phys_vidmem_write_supported = true; + parent_gpu->peer_copy_mode = UVM_GPU_PEER_COPY_MODE_VIRTUAL; // Not all units on Turing support 49-bit addressing, including those which @@ -91,4 +93,6 @@ parent_gpu->smc.supported = false; parent_gpu->plc_supported = true; + + parent_gpu->no_ats_range_required = false; } diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/kernel-open/nvidia-uvm/uvm_turing_host.c nvidia-open-gpu-kernel-modules-535.161.08/kernel-open/nvidia-uvm/uvm_turing_host.c --- nvidia-open-gpu-kernel-modules-525.147.05/kernel-open/nvidia-uvm/uvm_turing_host.c 2023-10-25 20:33:39.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/kernel-open/nvidia-uvm/uvm_turing_host.c 2024-03-05 22:25:57.000000000 +0000 @@ -83,9 +83,14 @@ // Direct copy of uvm_hal_maxwell_host_set_gpfifo_entry(). It removes // GP_ENTRY1_PRIV_KERNEL, which has been deprecated in Turing+. -void uvm_hal_turing_host_set_gpfifo_entry(NvU64 *fifo_entry, NvU64 pushbuffer_va, NvU32 pushbuffer_length) +void uvm_hal_turing_host_set_gpfifo_entry(NvU64 *fifo_entry, + NvU64 pushbuffer_va, + NvU32 pushbuffer_length, + uvm_gpfifo_sync_t sync_flag) { NvU64 fifo_entry_value; + const NvU32 sync_value = (sync_flag == UVM_GPFIFO_SYNC_WAIT) ? HWCONST(C46F, GP_ENTRY1, SYNC, WAIT) : + HWCONST(C46F, GP_ENTRY1, SYNC, PROCEED); UVM_ASSERT(!uvm_global_is_suspended()); UVM_ASSERT_MSG(pushbuffer_va % 4 == 0, "pushbuffer va unaligned: %llu\n", pushbuffer_va); @@ -93,7 +98,8 @@ fifo_entry_value = HWVALUE(C46F, GP_ENTRY0, GET, NvU64_LO32(pushbuffer_va) >> 2); fifo_entry_value |= (NvU64)(HWVALUE(C46F, GP_ENTRY1, GET_HI, NvU64_HI32(pushbuffer_va)) | - HWVALUE(C46F, GP_ENTRY1, LENGTH, pushbuffer_length >> 2)) << 32; + HWVALUE(C46F, GP_ENTRY1, LENGTH, pushbuffer_length >> 2) | + sync_value) << 32; *fifo_entry = fifo_entry_value; } diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/kernel-open/nvidia-uvm/uvm_types.h nvidia-open-gpu-kernel-modules-535.161.08/kernel-open/nvidia-uvm/uvm_types.h --- nvidia-open-gpu-kernel-modules-525.147.05/kernel-open/nvidia-uvm/uvm_types.h 2023-10-25 20:33:28.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/kernel-open/nvidia-uvm/uvm_types.h 2024-03-05 22:25:42.000000000 +0000 @@ -1,5 +1,5 @@ /******************************************************************************* - Copyright (c) 2013-2020 NVidia Corporation + Copyright (c) 2013-2023 NVidia Corporation Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation files (the "Software"), to @@ -493,7 +493,8 @@ UvmEventFatalReasonInternalError = 5, // This value is reported when a fault is triggered in an invalid context - // Example: CPU fault on a managed allocation while a kernel is running on a pre-Pascal GPU + // Example: CPU fault on a managed allocation while a kernel is running on a + // pre-Pascal GPU UvmEventFatalReasonInvalidOperation = 6, // ---- Add new values above this line UvmEventNumFatalReasons @@ -659,8 +660,8 @@ // or malign-double will have no effect on the field offsets // NvU8 padding8bits; - NvU32 batchId; // Per-GPU unique id to identify the faults that have - // been serviced in batch + NvU32 batchId; // Per-GPU unique id to identify the faults that + // have been serviced in batch NvU64 timeStamp; // cpu time when the replay of the faulting memory // accesses is queued on the gpu NvU64 timeStampGpu; // gpu time stamp when the replay operation finished @@ -674,15 +675,16 @@ { // // eventType has to be the 1st argument of this structure. - // Setting eventType = UvmEventTypeFatalFault helps to identify event data in - // a queue. + // Setting eventType = UvmEventTypeFatalFault helps to identify event data + // in a queue. // NvU8 eventType; - NvU8 faultType; // type of gpu fault, refer UvmEventFaultType. Only valid - // if processorIndex is a GPU + NvU8 faultType; // type of gpu fault, refer UvmEventFaultType. Only + // valid if processorIndex is a GPU NvU8 accessType; // memory access type, refer UvmEventMemoryAccessType NvU8 processorIndex; // processor that experienced the fault - NvU8 reason; // reason why the fault is fatal, refer UvmEventFatalReason + NvU8 reason; // reason why the fault is fatal, refer + // UvmEventFatalReason NvU8 padding8bits; NvU16 padding16bits; NvU64 address; // virtual address at which the processor faulted @@ -798,8 +800,8 @@ { // // eventType has to be the 1st argument of this structure. - // Setting eventType = UvmEventTypeThrottlingStart helps to identify event data - // in a queue. + // Setting eventType = UvmEventTypeThrottlingStart helps to identify event + // data in a queue. // NvU8 eventType; NvU8 processorIndex; // index of the cpu/gpu that was throttled @@ -819,8 +821,8 @@ { // // eventType has to be the 1st argument of this structure. - // Setting eventType = UvmEventTypeThrottlingEnd helps to identify event data - // in a queue. + // Setting eventType = UvmEventTypeThrottlingEnd helps to identify event + // data in a queue. // NvU8 eventType; NvU8 processorIndex; // index of the cpu/gpu that was throttled @@ -946,8 +948,8 @@ { // // eventType has to be the 1st argument of this structure. - // Setting eventType = UvmEventTypeAccessCounter helps to identify event data - // in a queue. + // Setting eventType = UvmEventTypeAccessCounter helps to identify event + // data in a queue. // NvU8 eventType; NvU8 srcIndex; // index of the gpu that received the access counter @@ -965,8 +967,10 @@ NvU8 isFromCpu; NvU8 veId; - NvU8 onManaged; // The access counter notification was triggered on - // a managed memory region + + // The physical access counter notification was triggered on a managed + // memory region. This is not set for virtual access counter notifications. + NvU8 physOnManaged; NvU32 value; NvU32 subGranularity; diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/kernel-open/nvidia-uvm/uvm_user_channel.c nvidia-open-gpu-kernel-modules-535.161.08/kernel-open/nvidia-uvm/uvm_user_channel.c --- nvidia-open-gpu-kernel-modules-525.147.05/kernel-open/nvidia-uvm/uvm_user_channel.c 2023-10-25 20:33:41.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/kernel-open/nvidia-uvm/uvm_user_channel.c 2024-03-05 22:26:04.000000000 +0000 @@ -984,14 +984,13 @@ goto out; } - va_space = uvm_va_space_get(va_space_filp); - uvm_va_space_down_read(va_space); - - // We can do this query outside of the lock, but doing it within the lock - // simplifies error handling. - status = uvm_va_space_initialized(va_space); - if (status != NV_OK) + va_space = uvm_fd_va_space(va_space_filp); + if (!va_space) { + status = NV_ERR_INVALID_ARGUMENT; goto out; + } + + uvm_va_space_down_read(va_space); gpu = uvm_va_space_get_gpu_by_uuid(va_space, ¶ms->gpu_uuid); if (!gpu || !uvm_processor_mask_test(&va_space->faultable_processors, gpu->id)) { diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/kernel-open/nvidia-uvm/uvm_va_block.c nvidia-open-gpu-kernel-modules-535.161.08/kernel-open/nvidia-uvm/uvm_va_block.c --- nvidia-open-gpu-kernel-modules-525.147.05/kernel-open/nvidia-uvm/uvm_va_block.c 2023-10-25 20:33:35.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/kernel-open/nvidia-uvm/uvm_va_block.c 2024-03-05 22:25:53.000000000 +0000 @@ -1,5 +1,5 @@ /******************************************************************************* - Copyright (c) 2015-2022 NVIDIA Corporation + Copyright (c) 2015-2023 NVIDIA Corporation Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation files (the "Software"), to @@ -39,6 +39,7 @@ #include "uvm_gpu_access_counters.h" #include "uvm_va_space_mm.h" #include "uvm_test_ioctl.h" +#include "uvm_conf_computing.h" typedef enum { @@ -78,7 +79,7 @@ "Force caching for mappings to system memory. " "This is an experimental parameter that may cause correctness issues if used."); -static void block_deferred_eviction_mappings_entry(void *args); +static void block_add_eviction_mappings_entry(void *args); uvm_va_space_t *uvm_va_block_get_va_space_maybe_dead(uvm_va_block_t *va_block) { @@ -105,36 +106,6 @@ return va_space; } -bool uvm_va_block_check_policy_is_valid(uvm_va_block_t *va_block, - uvm_va_policy_t *policy, - uvm_va_block_region_t region) -{ - uvm_assert_mutex_locked(&va_block->lock); - - if (uvm_va_block_is_hmm(va_block)) { - uvm_va_policy_node_t *node; - - if (policy == &uvm_va_policy_default) { - // There should only be the default policy within the region. - node = uvm_va_policy_node_iter_first(va_block, - uvm_va_block_region_start(va_block, region), - uvm_va_block_region_end(va_block, region)); - UVM_ASSERT(!node); - } - else { - // The policy node should cover the region. - node = uvm_va_policy_node_from_policy(policy); - UVM_ASSERT(node->node.start <= uvm_va_block_region_start(va_block, region)); - UVM_ASSERT(node->node.end >= uvm_va_block_region_end(va_block, region)); - } - } - else { - UVM_ASSERT(policy == uvm_va_range_get_policy(va_block->va_range)); - } - - return true; -} - static NvU64 block_gpu_pte_flag_cacheable(uvm_va_block_t *block, uvm_gpu_t *gpu, uvm_processor_id_t resident_id) { uvm_va_space_t *va_space = uvm_va_block_get_va_space(block); @@ -180,7 +151,7 @@ return uvm_enable_builtin_tests && uvm_fault_force_sysmem != 0; } -static bool va_space_map_remote_on_eviction(uvm_va_space_t *va_space) +bool uvm_va_space_map_remote_on_eviction(uvm_va_space_t *va_space) { return uvm_perf_map_remote_on_eviction && uvm_va_space_has_access_counter_migrations(va_space); @@ -208,79 +179,366 @@ INIT_LIST_HEAD(&retry->free_chunks); } -static bool block_verify_cpu_chunks(uvm_va_block_t *block) +// The bottom bit of uvm_va_block_t::chunks is used to indicate how CPU chunks +// are stored. +// +// CPU chunk storage is handled in three different ways depending on the +// type of chunks the VA block owns. This is done to minimize the memory +// required to hold metadata. +typedef enum { - uvm_cpu_chunk_t *chunk; - size_t alloced_pages = 0; - NvU64 tracking_virt_addr = block->start; - uvm_page_mask_t region_mask; - uvm_page_index_t page_index; - uvm_va_block_region_t block_region = uvm_va_block_region_from_block(block); + // The uvm_va_block_t::chunk pointer points to a single 2MB + // CPU chunk. + UVM_CPU_CHUNK_STORAGE_CHUNK = 0, + + // The uvm_va_block_t::chunks pointer points to a + // structure of mixed (64K and 4K) chunks. + UVM_CPU_CHUNK_STORAGE_MIXED, + UVM_CPU_CHUNK_STORAGE_COUNT, +} uvm_cpu_chunk_storage_type_t; + +#define UVM_CPU_CHUNK_STORAGE_MASK 0x1 + +// The maximum number of slots in the mixed chunk mode (64K + 4K chunks) is +// MAX_BIG_PAGES_PER_UVM_VA_BLOCK. Any leading/trailing misaligned pages will +// be stored in the first/last entry, respectively. +#define MAX_BIG_CPU_CHUNK_SLOTS_PER_UVM_VA_BLOCK MAX_BIG_PAGES_PER_UVM_VA_BLOCK + +#define MAX_SMALL_CHUNKS_PER_BIG_SLOT (UVM_MIN_BIG_PAGE_SIZE / PAGE_SIZE) + +// This structure is used when a VA block contains 64K or a mix of 64K and 4K +// CPU chunks. +// For every 64K CPU chunks, big_chunks will have its corresponding bit set +// and the corresponding index in slots will point directly to the +// uvm_cpu_chunk_t structure. +// +// For 4K CPU chunks, the corresponding bit in big_chunks will be clear and +// the element in slots will point to an array of 16 uvm_cpu_chunk_t pointers. +typedef struct { + DECLARE_BITMAP(big_chunks, MAX_BIG_CPU_CHUNK_SLOTS_PER_UVM_VA_BLOCK); + void *slots[MAX_BIG_CPU_CHUNK_SLOTS_PER_UVM_VA_BLOCK]; +} uvm_cpu_chunk_storage_mixed_t; - for_each_cpu_chunk_in_block(chunk, page_index, block) { - NvU64 chunk_virt_addr = uvm_va_block_cpu_page_address(block, page_index); - size_t num_chunk_pages = uvm_cpu_chunk_num_pages(chunk); - uvm_page_index_t chunk_page; +static uvm_va_block_region_t uvm_cpu_chunk_block_region(uvm_va_block_t *va_block, + uvm_cpu_chunk_t *chunk, + uvm_page_index_t page_index) +{ + UVM_ASSERT(chunk); + return uvm_va_block_chunk_region(va_block, uvm_cpu_chunk_get_size(chunk), page_index); +} - UVM_ASSERT(tracking_virt_addr <= chunk_virt_addr); - if (tracking_virt_addr > chunk_virt_addr) - return false; +static void *uvm_cpu_storage_get_ptr(uvm_va_block_t *block) +{ + return (void *)(block->cpu.chunks & ~UVM_CPU_CHUNK_STORAGE_MASK); +} - UVM_ASSERT(uvm_va_block_contains_address(block, chunk_virt_addr)); - if (!uvm_va_block_contains_address(block, chunk_virt_addr)) - return false; +static uvm_cpu_chunk_storage_type_t uvm_cpu_storage_get_type(uvm_va_block_t *block) +{ + return block->cpu.chunks & UVM_CPU_CHUNK_STORAGE_MASK; +} - alloced_pages += uvm_cpu_chunk_num_pages(chunk); - uvm_page_mask_init_from_region(®ion_mask, - uvm_va_block_region(page_index, page_index + uvm_cpu_chunk_num_pages(chunk)), - NULL); - UVM_ASSERT(uvm_page_mask_intersects(&block->cpu.allocated, ®ion_mask)); - if (!uvm_page_mask_intersects(&block->cpu.allocated, ®ion_mask)) - return false; +static uvm_page_index_t compute_page_prefix(uvm_va_block_t *va_block, uvm_chunk_size_t size) +{ + return (UVM_ALIGN_UP(va_block->start, size) - va_block->start) / PAGE_SIZE; +} - tracking_virt_addr = chunk_virt_addr; +static size_t compute_slot_index(uvm_va_block_t *va_block, uvm_page_index_t page_index) +{ + uvm_va_block_region_t block_region = uvm_va_block_region_from_block(va_block); + uvm_page_index_t prefix; + size_t slot_index; - for (chunk_page = page_index; chunk_page < page_index + num_chunk_pages; chunk_page++) { - UVM_ASSERT(uvm_cpu_chunk_get_chunk_for_page(block, chunk_page) == chunk); - if (uvm_cpu_chunk_get_chunk_for_page(block, chunk_page) != chunk) - return false; + UVM_ASSERT(page_index < block_region.outer); + prefix = compute_page_prefix(va_block, UVM_PAGE_SIZE_64K); + + if (page_index < prefix) + return 0; + + slot_index = ((page_index - prefix) / MAX_SMALL_CHUNKS_PER_BIG_SLOT) + !!prefix; + UVM_ASSERT(slot_index < MAX_BIG_CPU_CHUNK_SLOTS_PER_UVM_VA_BLOCK); + + return slot_index; +} + +static size_t compute_small_index(uvm_va_block_t *va_block, uvm_page_index_t page_index) +{ + size_t prefix = compute_page_prefix(va_block, UVM_PAGE_SIZE_64K); + + if (page_index < prefix) + return page_index; + + return (page_index - prefix) % MAX_SMALL_CHUNKS_PER_BIG_SLOT; +} + +NV_STATUS uvm_cpu_chunk_insert_in_block(uvm_va_block_t *va_block, + uvm_cpu_chunk_t *chunk, + uvm_page_index_t page_index) +{ + uvm_chunk_size_t chunk_size = uvm_cpu_chunk_get_size(chunk); + uvm_va_block_region_t chunk_region = uvm_va_block_region(page_index, page_index + uvm_cpu_chunk_num_pages(chunk)); + size_t slot_index; + uvm_cpu_chunk_storage_mixed_t *mixed; + uvm_cpu_chunk_t **chunks = NULL; + + // We only want to use the bottom bit of a pointer. + BUILD_BUG_ON(UVM_CPU_CHUNK_STORAGE_COUNT > 2); + + // We want to protect against two threads manipulating the VA block's CPU + // chunks at the same time. However, when a block is split, the new block's + // lock is locked without tracking. So, we can't use + // uvm_assert_mutex_locked(). + UVM_ASSERT(mutex_is_locked(&va_block->lock.m)); + + if (chunk_size == UVM_CHUNK_SIZE_2M) { + UVM_ASSERT(uvm_va_block_size(va_block) == UVM_PAGE_SIZE_2M); + UVM_ASSERT(!va_block->cpu.chunks); + va_block->cpu.chunks = (unsigned long)chunk | UVM_CPU_CHUNK_STORAGE_CHUNK; + } + else { + if (!va_block->cpu.chunks) { + mixed = uvm_kvmalloc_zero(sizeof(*mixed)); + if (!mixed) + return NV_ERR_NO_MEMORY; + + va_block->cpu.chunks = (unsigned long)mixed | UVM_CPU_CHUNK_STORAGE_MIXED; + } + + UVM_ASSERT(uvm_cpu_storage_get_type(va_block) == UVM_CPU_CHUNK_STORAGE_MIXED); + mixed = uvm_cpu_storage_get_ptr(va_block); + slot_index = compute_slot_index(va_block, page_index); + UVM_ASSERT(compute_slot_index(va_block, page_index + uvm_cpu_chunk_num_pages(chunk) - 1) == slot_index); + UVM_ASSERT(!test_bit(slot_index, mixed->big_chunks)); + + if (chunk_size == UVM_CHUNK_SIZE_64K) { + mixed->slots[slot_index] = chunk; + set_bit(slot_index, mixed->big_chunks); + } + else { + size_t small_index; + + UVM_ASSERT(chunk_size == UVM_CHUNK_SIZE_4K); + chunks = mixed->slots[slot_index]; + + if (!chunks) { + chunks = uvm_kvmalloc_zero(sizeof(*chunks) * MAX_SMALL_CHUNKS_PER_BIG_SLOT); + if (!chunks) + return NV_ERR_NO_MEMORY; + mixed->slots[slot_index] = chunks; + } + + small_index = compute_small_index(va_block, page_index); + chunks[small_index] = chunk; } } - UVM_ASSERT(alloced_pages == uvm_page_mask_weight(&block->cpu.allocated)); - if (alloced_pages != uvm_page_mask_weight(&block->cpu.allocated)) - return false; + uvm_page_mask_region_fill(&va_block->cpu.allocated, chunk_region); + return NV_OK; +} - for_each_va_block_page_in_region_mask(page_index, &block->cpu.allocated, block_region) { - uvm_cpu_chunk_t *next; - uvm_page_index_t next_page_index; +uvm_cpu_chunk_t *uvm_cpu_chunk_get_chunk_for_page(uvm_va_block_t *va_block, uvm_page_index_t page_index) +{ + uvm_cpu_chunk_storage_mixed_t *mixed; + uvm_cpu_chunk_t *chunk; + uvm_cpu_chunk_t **chunks; + size_t slot_index; - chunk = uvm_cpu_chunk_get_chunk_for_page(block, page_index); - UVM_ASSERT(chunk); - if (!chunk) - return false; + UVM_ASSERT(page_index < uvm_va_block_num_cpu_pages(va_block)); + if (!uvm_page_mask_test(&va_block->cpu.allocated, page_index)) + return NULL; - next_page_index = uvm_va_block_next_page_in_mask(block_region, - &block->cpu.allocated, - page_index + uvm_cpu_chunk_num_pages(chunk) - 1); - next = uvm_cpu_chunk_next(block, &next_page_index); - - if (next_page_index < block_region.outer) { - UVM_ASSERT(next && - uvm_va_block_cpu_page_address(block, page_index) + uvm_cpu_chunk_get_size(chunk) <= - uvm_va_block_cpu_page_address(block, next_page_index)); - if (!next || - (uvm_va_block_cpu_page_address(block, page_index) + uvm_cpu_chunk_get_size(chunk) > - uvm_va_block_cpu_page_address(block, next_page_index))) - return false; + UVM_ASSERT(va_block->cpu.chunks); + + if (uvm_cpu_storage_get_type(va_block) == UVM_CPU_CHUNK_STORAGE_CHUNK) { + return uvm_cpu_storage_get_ptr(va_block); + } + else { + mixed = uvm_cpu_storage_get_ptr(va_block); + slot_index = compute_slot_index(va_block, page_index); + UVM_ASSERT(mixed->slots[slot_index] != NULL); + if (test_bit(slot_index, mixed->big_chunks)) + return mixed->slots[slot_index]; + + chunks = mixed->slots[slot_index]; + chunk = chunks[compute_small_index(va_block, page_index)]; + } + + UVM_ASSERT(chunk); + return chunk; +} + +void uvm_cpu_chunk_remove_from_block(uvm_va_block_t *va_block, + uvm_page_index_t page_index) +{ + uvm_cpu_chunk_storage_mixed_t *mixed; + uvm_cpu_chunk_t *chunk = uvm_cpu_chunk_get_chunk_for_page(va_block, page_index); + uvm_va_block_region_t chunk_region = uvm_cpu_chunk_block_region(va_block, chunk, page_index); + size_t slot_index; + uvm_cpu_chunk_t **chunks; + + // We want to protect against two threads manipulating the VA block's CPU + // chunks at the same time. However, when a block is split, the new block's + // lock is locked without tracking. So, we can't use + // uvm_assert_mutex_locked(). + UVM_ASSERT(mutex_is_locked(&va_block->lock.m)); + UVM_ASSERT(va_block->cpu.chunks); + UVM_ASSERT(uvm_va_block_region_num_pages(chunk_region) == uvm_cpu_chunk_num_pages(chunk)); + + if (uvm_cpu_storage_get_type(va_block) == UVM_CPU_CHUNK_STORAGE_CHUNK) { + UVM_ASSERT(uvm_cpu_chunk_get_size(chunk) == UVM_CHUNK_SIZE_2M); + UVM_ASSERT(uvm_cpu_storage_get_ptr(va_block) == chunk); + va_block->cpu.chunks = 0; + } + else { + UVM_ASSERT(uvm_cpu_chunk_get_size(chunk) != UVM_CHUNK_SIZE_2M); + mixed = uvm_cpu_storage_get_ptr(va_block); + slot_index = compute_slot_index(va_block, page_index); + UVM_ASSERT(mixed->slots[slot_index] != NULL); + + if (test_bit(slot_index, mixed->big_chunks)) { + UVM_ASSERT(uvm_cpu_chunk_get_size(chunk) == UVM_CHUNK_SIZE_64K); + UVM_ASSERT(mixed->slots[slot_index] == chunk); + mixed->slots[slot_index] = NULL; + clear_bit(slot_index, mixed->big_chunks); } else { - UVM_ASSERT(next == NULL); - if (next != NULL) - return false; + size_t small_index; + + UVM_ASSERT(uvm_cpu_chunk_get_size(chunk) == UVM_CHUNK_SIZE_4K); + chunks = mixed->slots[slot_index]; + small_index = compute_small_index(va_block, page_index); + UVM_ASSERT(chunks[small_index] == chunk); + chunks[small_index] = NULL; + + for (small_index = 0; small_index < MAX_SMALL_CHUNKS_PER_BIG_SLOT; small_index++) { + if (chunks[small_index]) + break; + } + + if (small_index == MAX_SMALL_CHUNKS_PER_BIG_SLOT) { + uvm_kvfree(chunks); + mixed->slots[slot_index] = NULL; + } } } + uvm_page_mask_region_clear(&va_block->cpu.allocated, chunk_region); + + if (uvm_page_mask_empty(&va_block->cpu.allocated) && va_block->cpu.chunks) { + uvm_kvfree(uvm_cpu_storage_get_ptr(va_block)); + va_block->cpu.chunks = 0; + } +} + +struct page *uvm_cpu_chunk_get_cpu_page(uvm_va_block_t *va_block, uvm_page_index_t page_index) +{ + uvm_va_block_region_t chunk_region; + uvm_cpu_chunk_t *chunk = uvm_cpu_chunk_get_chunk_for_page(va_block, page_index); + + UVM_ASSERT(chunk); + UVM_ASSERT(chunk->page); + chunk_region = uvm_va_block_chunk_region(va_block, uvm_cpu_chunk_get_size(chunk), page_index); + return chunk->page + (page_index - chunk_region.first); +} + +static uvm_cpu_chunk_t *uvm_cpu_chunk_first_in_region(uvm_va_block_t *va_block, + uvm_va_block_region_t region, + uvm_page_index_t *first_chunk_page) +{ + uvm_cpu_chunk_t *chunk = NULL; + uvm_page_index_t page_index; + + page_index = uvm_va_block_first_page_in_mask(region, &va_block->cpu.allocated); + if (page_index < region.outer) + chunk = uvm_cpu_chunk_get_chunk_for_page(va_block, page_index); + + if (first_chunk_page && chunk) { + uvm_va_block_region_t chunk_region = uvm_cpu_chunk_block_region(va_block, chunk, page_index); + *first_chunk_page = chunk_region.first; + } + + return chunk; +} + +#define for_each_cpu_chunk_in_block_region(chunk, page_index, va_block, region) \ + for ((chunk) = uvm_cpu_chunk_first_in_region((va_block), (region), &(page_index)); \ + (chunk) != NULL; \ + (chunk) = uvm_cpu_chunk_first_in_region((va_block), \ + uvm_va_block_region((page_index) + uvm_cpu_chunk_num_pages((chunk)), \ + (region).outer), \ + &(page_index))) + +#define for_each_cpu_chunk_in_block_region_safe(chunk, page_index, next_page_index, va_block, region) \ + for ((chunk) = uvm_cpu_chunk_first_in_region((va_block), (region), &(page_index)), \ + (next_page_index) = (page_index) + (chunk ? uvm_cpu_chunk_num_pages(chunk) : 0); \ + (chunk) != NULL; \ + (chunk) = uvm_cpu_chunk_first_in_region((va_block), \ + uvm_va_block_region((next_page_index), (region).outer), \ + &(page_index)), \ + (next_page_index) = (page_index) + ((chunk) ? uvm_cpu_chunk_num_pages((chunk)) : 0)) + +#define for_each_cpu_chunk_in_block(chunk, page_index, va_block) \ + for_each_cpu_chunk_in_block_region((chunk), (page_index), (va_block), uvm_va_block_region_from_block((va_block))) + +#define for_each_cpu_chunk_in_block_safe(chunk, page_index, next_page_index, va_block) \ + for_each_cpu_chunk_in_block_region_safe((chunk), \ + (page_index), \ + (next_page_index), \ + (va_block), \ + uvm_va_block_region_from_block((va_block))) + +struct vm_area_struct *uvm_va_block_find_vma_region(uvm_va_block_t *va_block, + struct mm_struct *mm, + NvU64 start, + uvm_va_block_region_t *region) +{ + struct vm_area_struct *vma; + NvU64 end; + + if (start > va_block->end) + return NULL; + + vma = find_vma_intersection(mm, start, va_block->end + 1); + if (!vma) + return NULL; + + if (start < vma->vm_start) + start = vma->vm_start; + + end = vma->vm_end - 1; + if (end > va_block->end) + end = va_block->end; + + *region = uvm_va_block_region_from_start_end(va_block, start, end); + + return vma; +} + +static bool block_check_cpu_chunks(uvm_va_block_t *block) +{ + uvm_cpu_chunk_t *chunk; + size_t alloced_pages = 0; + uvm_va_block_region_t prev_region = { 0 }; + uvm_page_index_t page_index; + + for_each_cpu_chunk_in_block(chunk, page_index, block) { + uvm_va_block_region_t chunk_region = uvm_cpu_chunk_block_region(block, chunk, page_index); + size_t num_chunk_pages = uvm_cpu_chunk_num_pages(chunk); + uvm_page_index_t chunk_page; + + UVM_ASSERT(prev_region.outer <= chunk_region.first); + UVM_ASSERT(IS_ALIGNED(uvm_va_block_region_start(block, chunk_region), uvm_cpu_chunk_get_size(chunk))); + UVM_ASSERT(chunk_region.outer <= uvm_va_block_num_cpu_pages(block)); + + alloced_pages += uvm_cpu_chunk_num_pages(chunk); + UVM_ASSERT(uvm_page_mask_region_full(&block->cpu.allocated, chunk_region)); + prev_region = chunk_region; + + for (chunk_page = page_index; chunk_page < page_index + num_chunk_pages; chunk_page++) + UVM_ASSERT(uvm_cpu_chunk_get_chunk_for_page(block, chunk_page) == chunk); + } + + UVM_ASSERT(alloced_pages == uvm_page_mask_weight(&block->cpu.allocated)); + return true; } @@ -307,7 +565,12 @@ list_for_each_entry_safe(gpu_chunk, next_chunk, &retry->used_chunks, list) { list_del_init(&gpu_chunk->list); gpu = uvm_gpu_chunk_get_gpu(gpu_chunk); - uvm_pmm_gpu_unpin_temp(&gpu->pmm, gpu_chunk, va_block); + // HMM should have already moved allocated blocks to the referenced + // state so any left over were not migrated and should be freed. + if (uvm_va_block_is_hmm(va_block)) + uvm_pmm_gpu_free(&gpu->pmm, gpu_chunk, NULL); + else + uvm_pmm_gpu_unpin_allocated(&gpu->pmm, gpu_chunk, va_block); } } @@ -440,9 +703,6 @@ // Next common case: the whole block is aligned and sized to perfectly fit // the largest page size. - // - // TODO: Bug 1750144: This might not be the common case for HMM. Verify that - // this helps performance more than it hurts. final_chunk_size = uvm_chunk_find_last_size(chunk_sizes); if (IS_ALIGNED(start, final_chunk_size) && IS_ALIGNED(size, final_chunk_size)) { num_chunks_total = (size_t)uvm_div_pow2_64(page_index * PAGE_SIZE, final_chunk_size); @@ -519,6 +779,22 @@ return num_chunks_total; } +static size_t block_gpu_chunk_index_range(uvm_va_block_t *va_block, + NvU64 start, + NvU64 size, + uvm_gpu_t *gpu, + uvm_page_index_t page_index, + uvm_chunk_size_t *out_chunk_size) +{ + if (uvm_va_block_is_hmm(va_block)) { + if (out_chunk_size) + *out_chunk_size = PAGE_SIZE; + return page_index; + } + + return uvm_va_block_gpu_chunk_index_range(start, size, gpu, page_index, out_chunk_size); +} + static size_t block_gpu_chunk_index(uvm_va_block_t *block, uvm_gpu_t *gpu, uvm_page_index_t page_index, @@ -527,8 +803,9 @@ uvm_va_block_gpu_state_t *gpu_state = uvm_va_block_gpu_state_get(block, gpu->id); uvm_chunk_size_t size; uvm_gpu_chunk_t *chunk; + size_t index; - size_t index = uvm_va_block_gpu_chunk_index_range(block->start, uvm_va_block_size(block), gpu, page_index, &size); + index = block_gpu_chunk_index_range(block, block->start, uvm_va_block_size(block), gpu, page_index, &size); UVM_ASSERT(size >= PAGE_SIZE); @@ -556,6 +833,9 @@ NvU64 start = uvm_va_block_cpu_page_address(block, start_page_index); NvU64 size = block->end - start + 1; + if (uvm_va_block_is_hmm(block)) + return PAGE_SIZE; + // Create a mask of all sizes for which start is aligned. x ^ (x-1) yields a // mask of the rightmost 1 bit in x, as well as all trailing 0 bits in x. // Example: 1011000 -> 0001111 @@ -582,10 +862,10 @@ return block_gpu_chunk_index(block, gpu, uvm_va_block_cpu_page_index(block, block->end), NULL) + 1; } -static size_t block_num_gpu_chunks_range(NvU64 start, NvU64 size, uvm_gpu_t *gpu) +static size_t block_num_gpu_chunks_range(uvm_va_block_t *block, NvU64 start, NvU64 size, uvm_gpu_t *gpu) { uvm_page_index_t last_page_index = (size_t)((size / PAGE_SIZE) - 1); - return uvm_va_block_gpu_chunk_index_range(start, size, gpu, last_page_index, NULL) + 1; + return block_gpu_chunk_index_range(block, start, size, gpu, last_page_index, NULL) + 1; } uvm_gpu_chunk_t *uvm_va_block_lookup_gpu_chunk(uvm_va_block_t *va_block, uvm_gpu_t *gpu, NvU64 address) @@ -649,28 +929,64 @@ uvm_tracker_init(&block->tracker); block->prefetch_info.last_migration_proc_id = UVM_ID_INVALID; - nv_kthread_q_item_init(&block->eviction_mappings_q_item, block_deferred_eviction_mappings_entry, block); + nv_kthread_q_item_init(&block->eviction_mappings_q_item, block_add_eviction_mappings_entry, block); *out_block = block; return NV_OK; } +static void cpu_chunk_remove_sysmem_gpu_mapping(uvm_cpu_chunk_t *chunk, uvm_gpu_t *gpu) +{ + NvU64 gpu_mapping_addr = uvm_cpu_chunk_get_gpu_phys_addr(chunk, gpu->parent); + if (gpu_mapping_addr == 0) + return; + + uvm_pmm_sysmem_mappings_remove_gpu_mapping(&gpu->pmm_reverse_sysmem_mappings, gpu_mapping_addr); + uvm_cpu_chunk_unmap_gpu_phys(chunk, gpu->parent); +} + +static NV_STATUS cpu_chunk_add_sysmem_gpu_mapping(uvm_cpu_chunk_t *chunk, + uvm_va_block_t *block, + uvm_page_index_t page_index, + uvm_gpu_t *gpu) +{ + NV_STATUS status; + uvm_chunk_size_t chunk_size; + + // When the Confidential Computing feature is enabled the transfers don't + // use the DMA mapping of CPU chunks (since it's protected memory), but + // the DMA address of the unprotected dma buffer. + if (uvm_conf_computing_mode_enabled(gpu)) + return NV_OK; + + status = uvm_cpu_chunk_map_gpu(chunk, gpu); + if (status != NV_OK) + return status; + + chunk_size = uvm_cpu_chunk_get_size(chunk); + + // TODO: Bug 3744779: Handle benign assertion in + // pmm_sysmem_mappings_remove_gpu_mapping() in case of a + // failure. + status = uvm_pmm_sysmem_mappings_add_gpu_mapping(&gpu->pmm_reverse_sysmem_mappings, + uvm_cpu_chunk_get_gpu_phys_addr(chunk, gpu->parent), + uvm_va_block_cpu_page_address(block, page_index), + chunk_size, + block, + UVM_ID_CPU); + if (status != NV_OK) + cpu_chunk_remove_sysmem_gpu_mapping(chunk, gpu); + + return status; +} + static void block_gpu_unmap_phys_all_cpu_pages(uvm_va_block_t *block, uvm_gpu_t *gpu) { uvm_cpu_chunk_t *chunk; uvm_page_index_t page_index; - for_each_cpu_chunk_in_block(chunk, page_index, block) { - NvU64 gpu_mapping_addr; - - UVM_ASSERT(chunk); - gpu_mapping_addr = uvm_cpu_chunk_get_gpu_mapping_addr(block, page_index, chunk, gpu->id); - if (gpu_mapping_addr != 0) { - uvm_pmm_sysmem_mappings_remove_gpu_mapping(&gpu->pmm_reverse_sysmem_mappings, gpu_mapping_addr); - uvm_gpu_unmap_cpu_pages(gpu->parent, gpu_mapping_addr, uvm_cpu_chunk_get_size(chunk)); - uvm_cpu_chunk_set_gpu_mapping_addr(block, page_index, chunk, gpu->id, 0); - } - } + for_each_cpu_chunk_in_block(chunk, page_index, block) + cpu_chunk_remove_sysmem_gpu_mapping(chunk, gpu); } static NV_STATUS block_gpu_map_phys_all_cpu_pages(uvm_va_block_t *block, uvm_gpu_t *gpu) @@ -683,35 +999,12 @@ UVM_ASSERT(IS_ALIGNED(block_mapping_size, UVM_PAGE_SIZE_4K)); for_each_cpu_chunk_in_block(chunk, page_index, block) { - uvm_chunk_size_t chunk_size = uvm_cpu_chunk_get_size(chunk); - NvU64 gpu_mapping_addr = uvm_cpu_chunk_get_gpu_mapping_addr(block, page_index, chunk, gpu->id); - - UVM_ASSERT_MSG(gpu_mapping_addr == 0, "GPU%u DMA address 0x%llx\n", uvm_id_value(gpu->id), gpu_mapping_addr); - - status = uvm_gpu_map_cpu_pages(gpu->parent, - uvm_cpu_chunk_get_cpu_page(block, chunk, page_index), - chunk_size, - &gpu_mapping_addr); - if (status != NV_OK) - goto error; - - uvm_cpu_chunk_set_gpu_mapping_addr(block, page_index, chunk, gpu->id, gpu_mapping_addr); + UVM_ASSERT_MSG(uvm_cpu_chunk_get_gpu_phys_addr(chunk, gpu->parent) == 0, + "GPU%u DMA address 0x%llx\n", + uvm_id_value(gpu->id), + uvm_cpu_chunk_get_gpu_phys_addr(chunk, gpu->parent)); - // In some configurations such as SR-IOV heavy, the chunk cannot be - // referenced using its physical address. Create a kernel mapping. - status = uvm_mmu_sysmem_map(gpu, gpu_mapping_addr, chunk_size); - if (status != NV_OK) - goto error; - - status = uvm_pmm_sysmem_mappings_add_gpu_mapping(&gpu->pmm_reverse_sysmem_mappings, - uvm_cpu_chunk_get_gpu_mapping_addr(block, - page_index, - chunk, - gpu->id), - uvm_va_block_cpu_page_address(block, page_index), - chunk_size, - block, - UVM_ID_CPU); + status = cpu_chunk_add_sysmem_gpu_mapping(chunk, block, page_index, gpu); if (status != NV_OK) goto error; } @@ -819,7 +1112,9 @@ } } -// Retrieves the gpu_state for the given GPU, allocating it if it doesn't exist +// Retrieves the gpu_state for the given GPU. The returned pointer is +// internally managed and will be allocated (and freed) automatically, +// rather than by the caller. static uvm_va_block_gpu_state_t *block_gpu_state_get_alloc(uvm_va_block_t *block, uvm_gpu_t *gpu) { NV_STATUS status; @@ -838,10 +1133,6 @@ block->gpus[uvm_id_gpu_index(gpu->id)] = gpu_state; - status = uvm_cpu_chunk_gpu_mapping_alloc(block, gpu->id); - if (status != NV_OK) - goto error; - status = block_gpu_map_phys_all_cpu_pages(block, gpu); if (status != NV_OK) goto error; @@ -849,40 +1140,43 @@ return gpu_state; error: - if (gpu_state) { - if (gpu_state->chunks) - uvm_kvfree(gpu_state->chunks); - uvm_cpu_chunk_gpu_mapping_free(block, gpu->id); - kmem_cache_free(g_uvm_va_block_gpu_state_cache, gpu_state); - } + uvm_kvfree(gpu_state->chunks); + kmem_cache_free(g_uvm_va_block_gpu_state_cache, gpu_state); block->gpus[uvm_id_gpu_index(gpu->id)] = NULL; return NULL; } -static void block_unmap_cpu_chunk_on_gpus(uvm_va_block_t *block, uvm_cpu_chunk_t *chunk, uvm_page_index_t page_index) +NV_STATUS uvm_va_block_gpu_state_alloc(uvm_va_block_t *va_block) { - uvm_gpu_id_t id; + uvm_va_space_t *va_space = uvm_va_block_get_va_space(va_block); + uvm_gpu_id_t gpu_id; - for_each_gpu_id(id) { - NvU64 gpu_mapping_addr; - uvm_gpu_t *gpu; + UVM_ASSERT(uvm_va_block_is_hmm(va_block)); + uvm_assert_mutex_locked(&va_block->lock); - if (!uvm_va_block_gpu_state_get(block, id)) - continue; + for_each_gpu_id_in_mask(gpu_id, &va_space->registered_gpus) { + if (!block_gpu_state_get_alloc(va_block, uvm_va_space_get_gpu(va_space, gpu_id))) + return NV_ERR_NO_MEMORY; + } - gpu_mapping_addr = uvm_cpu_chunk_get_gpu_mapping_addr(block, page_index, chunk, id); - if (gpu_mapping_addr == 0) - continue; + return NV_OK; +} - gpu = block_get_gpu(block, id); - uvm_pmm_sysmem_mappings_remove_gpu_mapping(&gpu->pmm_reverse_sysmem_mappings, gpu_mapping_addr); - uvm_gpu_unmap_cpu_pages(gpu->parent, gpu_mapping_addr, uvm_cpu_chunk_get_size(chunk)); - uvm_cpu_chunk_set_gpu_mapping_addr(block, page_index, chunk, id, 0); +void uvm_va_block_unmap_cpu_chunk_on_gpus(uvm_va_block_t *block, + uvm_cpu_chunk_t *chunk, + uvm_page_index_t page_index) +{ + uvm_gpu_id_t id; + + for_each_gpu_id(id) { + if (uvm_va_block_gpu_state_get(block, id)) + cpu_chunk_remove_sysmem_gpu_mapping(chunk, block_get_gpu(block, id)); } } -static NV_STATUS block_map_cpu_chunk_on_gpus(uvm_va_block_t *block, uvm_page_index_t page_index) +NV_STATUS uvm_va_block_map_cpu_chunk_on_gpus(uvm_va_block_t *block, + uvm_page_index_t page_index) { NV_STATUS status; uvm_gpu_id_t id; @@ -890,51 +1184,19 @@ uvm_chunk_size_t chunk_size = uvm_cpu_chunk_get_size(chunk); uvm_va_block_region_t chunk_region = uvm_va_block_chunk_region(block, chunk_size, page_index); - UVM_ASSERT(chunk); - // We can't iterate over va_space->registered_gpus because we might be // on the eviction path, which does not have the VA space lock held. We have // the VA block lock held however, so the gpu_states can't change. uvm_assert_mutex_locked(&block->lock); - // Only physical chunks can be mapped. - UVM_ASSERT(uvm_cpu_chunk_is_physical(chunk)); - for_each_gpu_id(id) { - NvU64 gpu_mapping_addr; uvm_gpu_t *gpu; if (!uvm_va_block_gpu_state_get(block, id)) continue; - gpu_mapping_addr = uvm_cpu_chunk_get_gpu_mapping_addr(block, page_index, chunk, id); - UVM_ASSERT_MSG(gpu_mapping_addr == 0, "GPU%u DMA address 0x%llx\n", uvm_id_value(id), gpu_mapping_addr); - gpu = block_get_gpu(block, id); - status = uvm_gpu_map_cpu_pages(gpu->parent, - uvm_cpu_chunk_get_cpu_page(block, chunk, chunk_region.first), - chunk_size, - &gpu_mapping_addr); - if (status != NV_OK) - goto error; - - uvm_cpu_chunk_set_gpu_mapping_addr(block, chunk_region.first, chunk, id, gpu_mapping_addr); - - // In some configurations such as SR-IOV heavy, the chunk cannot be - // referenced using its physical address. Create a kernel mapping. - status = uvm_mmu_sysmem_map(gpu, gpu_mapping_addr, chunk_size); - if (status != NV_OK) - goto error; - - status = uvm_pmm_sysmem_mappings_add_gpu_mapping(&gpu->pmm_reverse_sysmem_mappings, - uvm_cpu_chunk_get_gpu_mapping_addr(block, - chunk_region.first, - chunk, - id), - uvm_va_block_cpu_page_address(block, chunk_region.first), - chunk_size, - block, - UVM_ID_CPU); + status = cpu_chunk_add_sysmem_gpu_mapping(chunk, block, chunk_region.first, gpu); if (status != NV_OK) goto error; } @@ -942,10 +1204,33 @@ return NV_OK; error: - block_unmap_cpu_chunk_on_gpus(block, chunk, page_index); + uvm_va_block_unmap_cpu_chunk_on_gpus(block, chunk, page_index); return status; } +void uvm_va_block_remove_cpu_chunks(uvm_va_block_t *va_block, uvm_va_block_region_t region) +{ + uvm_cpu_chunk_t *chunk; + uvm_page_index_t page_index, next_page_index; + uvm_va_block_region_t chunk_region; + + for_each_cpu_chunk_in_block_region_safe(chunk, page_index, next_page_index, va_block, region) { + chunk_region = uvm_va_block_region(page_index, page_index + uvm_cpu_chunk_num_pages(chunk)); + + uvm_page_mask_region_clear(&va_block->cpu.pte_bits[UVM_PTE_BITS_CPU_READ], chunk_region); + uvm_page_mask_region_clear(&va_block->cpu.pte_bits[UVM_PTE_BITS_CPU_WRITE], chunk_region); + uvm_page_mask_region_clear(&va_block->cpu.resident, chunk_region); + uvm_cpu_chunk_remove_from_block(va_block, page_index); + uvm_va_block_unmap_cpu_chunk_on_gpus(va_block, chunk, page_index); + uvm_cpu_chunk_free(chunk); + } + + if (uvm_page_mask_empty(&va_block->cpu.pte_bits[UVM_PTE_BITS_CPU_READ])) + uvm_processor_mask_clear(&va_block->mapped, UVM_ID_CPU); + if (uvm_page_mask_empty(&va_block->cpu.resident)) + uvm_processor_mask_clear(&va_block->resident, UVM_ID_CPU); +} + // Create physical mappings to allow other GPUs to access this chunk. static NV_STATUS block_map_indirect_peers_to_gpu_chunk(uvm_va_block_t *block, uvm_gpu_t *gpu, uvm_gpu_chunk_t *chunk) { @@ -953,8 +1238,8 @@ uvm_gpu_t *accessing_gpu, *remove_gpu; NV_STATUS status; - // Unlike block_map_cpu_chunk_on_gpus, this function isn't called on the - // eviction path, so we can assume that the VA space is locked. + // Unlike uvm_va_block_map_cpu_chunk_on_gpus, this function isn't called on + // the eviction path, so we can assume that the VA space is locked. // // TODO: Bug 2007346: In the future we may want to enable eviction to peers, // meaning we may need to allocate peer memory and map it on the @@ -1009,41 +1294,33 @@ static void block_mark_cpu_page_dirty(uvm_va_block_t *block, uvm_page_index_t page_index) { uvm_cpu_chunk_t *chunk = uvm_cpu_chunk_get_chunk_for_page(block, page_index); - uvm_cpu_chunk_mark_dirty(chunk, page_index); + uvm_va_block_region_t chunk_region = uvm_va_block_chunk_region(block, uvm_cpu_chunk_get_size(chunk), page_index); + uvm_cpu_chunk_mark_dirty(chunk, page_index - chunk_region.first); } // Mark a CPU page as clean. static void block_mark_cpu_page_clean(uvm_va_block_t *block, uvm_page_index_t page_index) { uvm_cpu_chunk_t *chunk = uvm_cpu_chunk_get_chunk_for_page(block, page_index); - uvm_cpu_chunk_mark_clean(chunk, page_index); + uvm_va_block_region_t chunk_region = uvm_va_block_chunk_region(block, uvm_cpu_chunk_get_size(chunk), page_index); + uvm_cpu_chunk_mark_clean(chunk, page_index - chunk_region.first); } // Check if a CPU page is dirty. static bool block_cpu_page_is_dirty(uvm_va_block_t *block, uvm_page_index_t page_index) { uvm_cpu_chunk_t *chunk = uvm_cpu_chunk_get_chunk_for_page(block, page_index); - return uvm_cpu_chunk_is_dirty(chunk, page_index); + uvm_va_block_region_t chunk_region = uvm_va_block_chunk_region(block, uvm_cpu_chunk_get_size(chunk), page_index); + return uvm_cpu_chunk_is_dirty(chunk, page_index - chunk_region.first); } -// Allocates the input page in the block, if it doesn't already exist -// -// Also maps the page for physical access by all GPUs used by the block, which -// is required for IOMMU support. -// -// TODO: Bug 1995015: Optimize this function and its callers to avoid calling for -// each page index. -static NV_STATUS block_populate_page_cpu(uvm_va_block_t *block, uvm_page_index_t page_index, struct mm_struct *mm) +static NV_STATUS block_alloc_cpu_chunk(uvm_va_block_t *block, + uvm_chunk_size_t alloc_size, + uvm_cpu_chunk_alloc_flags_t flags, + uvm_cpu_chunk_t **chunk) { - NV_STATUS status; - uvm_cpu_chunk_t *chunk = NULL; uvm_va_block_test_t *block_test = uvm_va_block_get_test(block); - if (uvm_page_mask_test(&block->cpu.allocated, page_index)) - return NV_OK; - - UVM_ASSERT(!uvm_page_mask_test(&block->cpu.resident, page_index)); - // Return out of memory error if the tests have requested it. As opposed to // other error injection settings, this one fails N times and then succeeds. // TODO: Bug 3701182: This will print a warning in Linux kernels newer than @@ -1054,16 +1331,134 @@ return NV_ERR_NO_MEMORY; } - status = uvm_cpu_chunk_alloc(block, page_index, mm, &chunk); - if (status != NV_OK) - goto error; + return uvm_cpu_chunk_alloc(alloc_size, flags, chunk); +} - status = block_map_cpu_chunk_on_gpus(block, page_index); +// Allocates the input page in the block, if it doesn't already exist +// +// Also maps the page for physical access by all GPUs used by the block, which +// is required for IOMMU support. Skipped on GPUs without access to CPU memory. +// e.g., this happens when the Confidential Computing Feature is enabled. +static NV_STATUS block_populate_pages_cpu(uvm_va_block_t *block, + uvm_page_mask_t *populate_page_mask, + uvm_va_block_region_t populate_region, + uvm_va_block_context_t *block_context) +{ + NV_STATUS status = NV_OK; + uvm_cpu_chunk_t *chunk; + uvm_va_block_test_t *block_test = uvm_va_block_get_test(block); + uvm_chunk_sizes_mask_t cpu_allocation_sizes = uvm_cpu_chunk_get_allocation_sizes(); + uvm_chunk_size_t alloc_size; + uvm_page_mask_t *resident_mask = &block_context->scratch_page_mask; + uvm_cpu_chunk_alloc_flags_t alloc_flags = UVM_CPU_CHUNK_ALLOC_FLAGS_NONE; + uvm_va_space_t *va_space = uvm_va_block_get_va_space(block); + uvm_processor_mask_t uvm_lite_gpus; + uvm_page_index_t page_index; + uvm_gpu_id_t id; + + // Check whether all requested pages have already been allocated. + uvm_page_mask_init_from_region(&block_context->scratch_page_mask, populate_region, populate_page_mask); + if (!uvm_page_mask_andnot(&block_context->scratch_page_mask, + &block_context->scratch_page_mask, + &block->cpu.allocated)) + return NV_OK; + + if (block_test) { + if (block_test->cpu_chunk_allocation_size_mask) + cpu_allocation_sizes &= block_test->cpu_chunk_allocation_size_mask; + } + + uvm_page_mask_zero(resident_mask); + for_each_id_in_mask (id, &block->resident) + uvm_page_mask_or(resident_mask, resident_mask, uvm_va_block_resident_mask_get(block, id)); + + // If the VA space has a UVM-Lite GPU registered, only PAGE_SIZE allocations + // should be used in order to avoid extra copies due to dirty compound + // pages. HMM va_blocks also require PAGE_SIZE allocations. + // TODO: Bug 3368756: add support for HMM transparent huge page (THP) + // migrations. + uvm_processor_mask_andnot(&uvm_lite_gpus, &va_space->registered_gpus, &va_space->faultable_processors); + if (!uvm_processor_mask_empty(&uvm_lite_gpus) || uvm_va_block_is_hmm(block)) + cpu_allocation_sizes = PAGE_SIZE; + + if (block_context->mm) + alloc_flags |= UVM_CPU_CHUNK_ALLOC_FLAGS_ACCOUNT; + + UVM_ASSERT(cpu_allocation_sizes >= PAGE_SIZE); + UVM_ASSERT(cpu_allocation_sizes & PAGE_SIZE); + + for_each_va_block_page_in_region_mask(page_index, populate_page_mask, populate_region) { + uvm_cpu_chunk_alloc_flags_t chunk_alloc_flags; + uvm_va_block_region_t region = populate_region; + + if (uvm_page_mask_test(&block->cpu.allocated, page_index)) { + page_index = uvm_va_block_next_unset_page_in_mask(populate_region, &block->cpu.allocated, page_index) - 1; + continue; + } + + UVM_ASSERT(!uvm_page_mask_test(&block->cpu.resident, page_index)); + + chunk_alloc_flags = alloc_flags; + + // Attempt to allocate CPU pages with the largest physically contiguous + // size from the set of CPU chunk sizes that we can. + // This is accomplished by: + // 1. Aligning the CPU page address down to the allocation size. + // 2. Ensuring that the entire allocation region fits withing the VA + // block. + // 3. Ensuring that the region covered by the allocation is empty. + for_each_chunk_size_rev(alloc_size, cpu_allocation_sizes) { + NvU64 alloc_virt_addr; + + chunk = NULL; + alloc_virt_addr = UVM_ALIGN_DOWN(uvm_va_block_cpu_page_address(block, page_index), alloc_size); + + if (!uvm_va_block_contains_address(block, alloc_virt_addr) || + !uvm_va_block_contains_address(block, alloc_virt_addr + alloc_size - 1)) + continue; + + region = uvm_va_block_region_from_start_end(block, alloc_virt_addr, alloc_virt_addr + alloc_size - 1); + + if (!uvm_page_mask_region_empty(&block->cpu.allocated, region)) + continue; + + // If not all pages in the allocation region are resident somewhere, + // zero out the allocated page. + // This could be wasteful if only a few pages in high-order + // allocation need to be zero'ed out but the alternative is to map + // single sub-pages one-by-one. + if (!uvm_page_mask_region_full(resident_mask, region)) + chunk_alloc_flags |= UVM_CPU_CHUNK_ALLOC_FLAGS_ZERO; + + status = block_alloc_cpu_chunk(block, alloc_size, chunk_alloc_flags, &chunk); + if (status == NV_OK) { + page_index = region.first; + break; + } + + UVM_ASSERT(status == NV_ERR_NO_MEMORY); + } + + if (status != NV_OK) + break; + + status = uvm_cpu_chunk_insert_in_block(block, chunk, page_index); + if (status != NV_OK) { + uvm_cpu_chunk_free(chunk); + return status; + } + + status = uvm_va_block_map_cpu_chunk_on_gpus(block, page_index); + if (status != NV_OK) + break; + + // Skip iterating over all pages covered by the allocated chunk. + page_index = region.outer - 1; + } -error: if (status != NV_OK && chunk) { - uvm_cpu_chunk_remove_from_block(block, chunk, page_index); - uvm_cpu_chunk_put(chunk); + uvm_cpu_chunk_remove_from_block(block, page_index); + uvm_cpu_chunk_free(chunk); } return status; @@ -1172,7 +1567,8 @@ { uvm_gpu_va_space_t *gpu_va_space; - if (uvm_va_block_size(block) < UVM_PAGE_SIZE_2M) + // TODO: Bug 3368756: add HMM support for transparent huge page migrations. + if (uvm_va_block_size(block) < UVM_PAGE_SIZE_2M || uvm_va_block_is_hmm(block)) return false; UVM_ASSERT(uvm_va_block_size(block) == UVM_PAGE_SIZE_2M); @@ -1364,6 +1760,21 @@ return (NvU32)chunk_size; } +NvU32 uvm_va_block_get_physical_size(uvm_va_block_t *block, + uvm_processor_id_t processor, + uvm_page_index_t page_index) +{ + block_phys_page_t page; + + UVM_ASSERT(block); + + uvm_assert_mutex_locked(&block->lock); + + page = block_phys_page(processor, page_index); + + return block_phys_page_size(block, page); +} + static uvm_pte_bits_cpu_t get_cpu_pte_bit_index(uvm_prot_t prot) { uvm_pte_bits_cpu_t pte_bit_index = UVM_PTE_BITS_CPU_MAX; @@ -1499,7 +1910,10 @@ return uvm_page_mask_test(resident_mask, page_index); } -void uvm_va_block_region_authorized_gpus(uvm_va_block_t *va_block, +// Compute the gpus that have at least the given access permissions for the +// range described by region and page_mask. The function sets the bit if any +// page in the region has the permissions. +static void block_region_authorized_gpus(uvm_va_block_t *va_block, uvm_va_block_region_t region, uvm_prot_t access_permission, uvm_processor_mask_t *authorized_gpus) @@ -1517,7 +1931,10 @@ } } -void uvm_va_block_region_authorized_processors(uvm_va_block_t *va_block, +// Compute the processors that have at least the given access permissions for +// the range described by region and page_mask. The function sets the bit if any +// page in the region has the permissions. +static void block_region_authorized_processors(uvm_va_block_t *va_block, uvm_va_block_region_t region, uvm_prot_t access_permission, uvm_processor_mask_t *authorized_processors) @@ -1525,7 +1942,7 @@ uvm_pte_bits_cpu_t search_cpu_bit = get_cpu_pte_bit_index(access_permission); // Compute GPUs - uvm_va_block_region_authorized_gpus(va_block, region, access_permission, authorized_processors); + block_region_authorized_gpus(va_block, region, access_permission, authorized_processors); // Test CPU if (uvm_processor_mask_test(&va_block->mapped, UVM_ID_CPU) && @@ -1534,29 +1951,18 @@ } } -void uvm_va_block_page_authorized_gpus(uvm_va_block_t *va_block, - uvm_page_index_t page_index, - uvm_prot_t access_permission, - uvm_processor_mask_t *authorized_gpus) -{ - uvm_va_block_region_authorized_gpus(va_block, - uvm_va_block_region_for_page(page_index), - access_permission, - authorized_gpus); -} - -void uvm_va_block_page_authorized_processors(uvm_va_block_t *va_block, +static void block_page_authorized_processors(uvm_va_block_t *va_block, uvm_page_index_t page_index, uvm_prot_t access_permission, uvm_processor_mask_t *authorized_processors) { - uvm_va_block_region_authorized_processors(va_block, - uvm_va_block_region_for_page(page_index), - access_permission, - authorized_processors); + block_region_authorized_processors(va_block, + uvm_va_block_region_for_page(page_index), + access_permission, + authorized_processors); } -bool uvm_va_block_is_gpu_authorized_on_whole_region(uvm_va_block_t *va_block, +static bool block_is_gpu_authorized_on_whole_region(uvm_va_block_t *va_block, uvm_va_block_region_t region, uvm_gpu_id_t gpu_id, uvm_prot_t required_prot) @@ -1570,7 +1976,7 @@ return uvm_page_mask_region_full(&gpu_state->pte_bits[search_gpu_bit], region); } -bool uvm_va_block_is_processor_authorized_on_whole_region(uvm_va_block_t *va_block, +static bool block_is_processor_authorized_on_whole_region(uvm_va_block_t *va_block, uvm_va_block_region_t region, uvm_processor_id_t processor_id, uvm_prot_t required_prot) @@ -1581,7 +1987,7 @@ return uvm_page_mask_region_full(&va_block->cpu.pte_bits[search_cpu_bit], region); } else { - return uvm_va_block_is_gpu_authorized_on_whole_region(va_block, region, processor_id, required_prot); + return block_is_gpu_authorized_on_whole_region(va_block, region, processor_id, required_prot); } } @@ -1590,24 +1996,25 @@ uvm_gpu_id_t gpu_id, uvm_prot_t required_prot) { - return uvm_va_block_is_gpu_authorized_on_whole_region(va_block, - uvm_va_block_region_for_page(page_index), - gpu_id, - required_prot); + return block_is_gpu_authorized_on_whole_region(va_block, + uvm_va_block_region_for_page(page_index), + gpu_id, + required_prot); } -bool uvm_va_block_page_is_processor_authorized(uvm_va_block_t *va_block, +static bool block_page_is_processor_authorized(uvm_va_block_t *va_block, uvm_page_index_t page_index, uvm_processor_id_t processor_id, uvm_prot_t required_prot) { - return uvm_va_block_is_processor_authorized_on_whole_region(va_block, - uvm_va_block_region_for_page(page_index), - processor_id, - required_prot); + return block_is_processor_authorized_on_whole_region(va_block, + uvm_va_block_region_for_page(page_index), + processor_id, + required_prot); } -void uvm_va_block_page_resident_gpus(uvm_va_block_t *va_block, +// Compute the gpus that have a copy of the given page resident in their memory +static void block_page_resident_gpus(uvm_va_block_t *va_block, uvm_page_index_t page_index, uvm_processor_mask_t *resident_gpus) { @@ -1626,7 +2033,7 @@ uvm_page_index_t page_index, uvm_processor_mask_t *resident_processors) { - uvm_va_block_page_resident_gpus(va_block, page_index, resident_processors); + block_page_resident_gpus(va_block, page_index, resident_processors); if (uvm_page_mask_test(uvm_va_block_resident_mask_get(va_block, UVM_ID_CPU), page_index)) { UVM_ASSERT(block_processor_page_is_populated(va_block, UVM_ID_CPU, page_index)); @@ -1642,14 +2049,7 @@ return uvm_processor_mask_get_count(&resident_processors); } -uvm_processor_id_t uvm_va_block_page_get_closest_resident(uvm_va_block_t *va_block, - uvm_page_index_t page_index, - uvm_processor_id_t processor) -{ - return uvm_va_block_page_get_closest_resident_in_mask(va_block, page_index, processor, NULL); -} - -uvm_processor_id_t uvm_va_block_page_get_closest_resident_in_mask(uvm_va_block_t *va_block, +static uvm_processor_id_t block_page_get_closest_resident_in_mask(uvm_va_block_t *va_block, uvm_page_index_t page_index, uvm_processor_id_t processor, const uvm_processor_mask_t *processor_mask) @@ -1671,6 +2071,13 @@ return UVM_ID_INVALID; } +uvm_processor_id_t uvm_va_block_page_get_closest_resident(uvm_va_block_t *va_block, + uvm_page_index_t page_index, + uvm_processor_id_t processor) +{ + return block_page_get_closest_resident_in_mask(va_block, page_index, processor, NULL); +} + // We don't track the specific aperture of each mapped page. Instead, we assume // that each virtual mapping from a given processor always targets the closest // processor on which that page is resident (with special rules for UVM-Lite). @@ -1866,11 +2273,7 @@ // are the pages which must be zeroed. uvm_page_mask_complement(zero_mask, zero_mask); - if (uvm_mmu_gpu_needs_static_vidmem_mapping(gpu) || uvm_mmu_gpu_needs_dynamic_vidmem_mapping(gpu)) - memset_addr_base = uvm_gpu_address_virtual_from_vidmem_phys(gpu, chunk->address); - else - memset_addr_base = uvm_gpu_address_physical(UVM_APERTURE_VID, chunk->address); - + memset_addr_base = uvm_gpu_address_copy(gpu, uvm_gpu_phys_address(UVM_APERTURE_VID, chunk->address)); memset_addr = memset_addr_base; status = uvm_push_begin_acquire(gpu->channel_manager, @@ -2053,9 +2456,8 @@ uvm_va_block_region_t region, const uvm_page_mask_t *page_mask) { - NV_STATUS status = NV_OK; + NV_STATUS status; const uvm_page_mask_t *resident_mask = block_resident_mask_get_alloc(block, dest_id); - uvm_page_index_t page_index; uvm_page_mask_t *populate_page_mask = &block_context->make_resident.page_mask; uvm_memcg_context_t memcg_context; @@ -2071,13 +2473,7 @@ return block_populate_pages_gpu(block, retry, block_get_gpu(block, dest_id), region, populate_page_mask); uvm_memcg_context_start(&memcg_context, block_context->mm); - - for_each_va_block_page_in_region_mask(page_index, populate_page_mask, region) { - status = block_populate_page_cpu(block, page_index, block_context->mm); - if (status != NV_OK) - break; - } - + status = block_populate_pages_cpu(block, populate_page_mask, region, block_context); uvm_memcg_context_end(&memcg_context); return status; } @@ -2133,7 +2529,7 @@ if (UVM_ID_IS_CPU(block_page.processor)) { uvm_cpu_chunk_t *chunk = uvm_cpu_chunk_get_chunk_for_page(block, block_page.page_index); - NvU64 dma_addr = uvm_cpu_chunk_get_gpu_mapping_addr(block, block_page.page_index, chunk, gpu->id); + NvU64 dma_addr = uvm_cpu_chunk_get_gpu_phys_addr(chunk, gpu->parent); uvm_va_block_region_t chunk_region = uvm_va_block_chunk_region(block, uvm_cpu_chunk_get_size(chunk), block_page.page_index); @@ -2177,29 +2573,16 @@ uvm_gpu_chunk_t *chunk; uvm_gpu_address_t copy_addr; uvm_va_space_t *va_space; - bool page_in_cpu, page_in_local_gpu; UVM_ASSERT_MSG(block_can_copy_from(block, gpu->id, block_page.processor), "from %s to %s\n", block_processor_name(block, gpu->id), block_processor_name(block, block_page.processor)); - page_in_cpu = UVM_ID_IS_CPU(block_page.processor); - page_in_local_gpu = uvm_id_equal(block_page.processor, gpu->id); - // CPU and local GPU accesses can rely on block_phys_page_address, but the // resulting physical address may need to be converted into virtual. - if (page_in_cpu || page_in_local_gpu) { - uvm_gpu_phys_address_t gpu_phys_address = block_phys_page_address(block, block_page, gpu); - - if (page_in_cpu && uvm_mmu_gpu_needs_dynamic_sysmem_mapping(gpu)) - return uvm_gpu_address_virtual_from_sysmem_phys(gpu, gpu_phys_address.address); - - if (page_in_local_gpu && uvm_mmu_gpu_needs_dynamic_vidmem_mapping(gpu)) - return uvm_gpu_address_virtual_from_vidmem_phys(gpu, gpu_phys_address.address); - - return uvm_gpu_address_from_phys(gpu_phys_address); - } + if (UVM_ID_IS_CPU(block_page.processor) || uvm_id_equal(block_page.processor, gpu->id)) + return uvm_gpu_address_copy(gpu, block_phys_page_address(block, block_page, gpu)); va_space = uvm_va_block_get_va_space(block); @@ -2232,16 +2615,41 @@ return uvm_va_block_res_phys_page_address(va_block, page_index, gpu->id, gpu); } +typedef struct +{ + // Location of the memory + uvm_processor_id_t id; + + // Whether the whole block has a single physically-contiguous chunk of + // storage on the processor. + bool is_block_contig; + + // Starting address of the physically-contiguous allocation, from the view + // of the copying GPU. Valid only if is_block_contig. + uvm_gpu_address_t gpu_address; +} block_copy_addr_t; + +typedef struct +{ + block_copy_addr_t src; + block_copy_addr_t dst; + uvm_conf_computing_dma_buffer_t *dma_buffer; +} block_copy_state_t; + // Begin a push appropriate for copying data from src_id processor to dst_id processor. // One of src_id and dst_id needs to be a GPU. static NV_STATUS block_copy_begin_push(uvm_va_block_t *va_block, - uvm_processor_id_t dst_id, - uvm_processor_id_t src_id, + block_copy_state_t *copy_state, uvm_tracker_t *tracker, uvm_push_t *push) { - uvm_channel_type_t channel_type; uvm_gpu_t *gpu; + NV_STATUS status; + uvm_channel_type_t channel_type; + uvm_tracker_t *tracker_ptr = tracker; + uvm_processor_id_t dst_id = copy_state->dst.id; + uvm_processor_id_t src_id = copy_state->src.id; + uvm_tracker_t local_tracker = UVM_TRACKER_INIT(); UVM_ASSERT_MSG(!uvm_id_equal(src_id, dst_id), "Unexpected copy to self, processor %s\n", @@ -2287,15 +2695,50 @@ va_block->end); } - return uvm_push_begin_acquire(gpu->channel_manager, - channel_type, - tracker, - push, - "Copy from %s to %s for block [0x%llx, 0x%llx]", - block_processor_name(va_block, src_id), - block_processor_name(va_block, dst_id), - va_block->start, - va_block->end); + if (uvm_conf_computing_mode_enabled(gpu)) { + // When the Confidential Feature is enabled, additional dependencies + // apply to the input tracker as well as the dma_buffer tracker. + // * In the CPU to GPU case, because UVM performs CPU side + // crypto-operations first before the GPU copy, we both need to + // ensure that the dma_buffer and the input tracker are completed. + // * In the GPU to CPU case, the GPU copy happens first, but the same + // principles apply. Hence, UVM acquires the input tracker and the + // dma buffer. + status = uvm_tracker_overwrite_safe(&local_tracker, tracker); + if (status != NV_OK) + goto error; + + UVM_ASSERT(copy_state->dma_buffer == NULL); + status = uvm_conf_computing_dma_buffer_alloc(&gpu->conf_computing.dma_buffer_pool, + ©_state->dma_buffer, + &local_tracker); + + if (status != NV_OK) + goto error; + + if (channel_type == UVM_CHANNEL_TYPE_CPU_TO_GPU) { + status = uvm_tracker_wait(&local_tracker); + if (status != NV_OK) + goto error; + } + + tracker_ptr = &local_tracker; + } + + status = uvm_push_begin_acquire(gpu->channel_manager, + channel_type, + tracker_ptr, + push, + "Copy from %s to %s for block [0x%llx, 0x%llx]", + block_processor_name(va_block, src_id), + block_processor_name(va_block, dst_id), + va_block->start, + va_block->end); + +error: + // Caller is responsible for freeing the DMA buffer on error + uvm_tracker_deinit(&local_tracker); + return status; } // A page is clean iff... @@ -2323,7 +2766,7 @@ uvm_processor_id_t src_id, uvm_page_index_t page_index) { - if (UVM_ID_IS_GPU(dst_id) || uvm_va_block_is_hmm(block)) + if (UVM_ID_IS_GPU(dst_id)) return; if (uvm_id_equal(src_id, uvm_va_range_get_policy(block->va_range)->preferred_location)) @@ -2343,7 +2786,10 @@ // If the block is of the max size and the GPU supports eviction, mark the // root chunk as used in PMM. - if (uvm_va_block_size(block) == UVM_CHUNK_SIZE_MAX && uvm_gpu_supports_eviction(gpu)) { + // HMM always allocates PAGE_SIZE GPU chunks so skip HMM va_blocks. + if (!uvm_va_block_is_hmm(block) && + uvm_va_block_size(block) == UVM_CHUNK_SIZE_MAX && + uvm_gpu_supports_eviction(gpu)) { // The chunk has to be there if this GPU is resident UVM_ASSERT(uvm_processor_mask_test(&block->resident, id)); uvm_pmm_gpu_mark_root_chunk_used(&gpu->pmm, uvm_va_block_gpu_state_get(block, gpu->id)->chunks[0]); @@ -2376,7 +2822,9 @@ // If the block is of the max size and the GPU supports eviction, mark the // root chunk as unused in PMM. - if (uvm_va_block_size(block) == UVM_CHUNK_SIZE_MAX && uvm_gpu_supports_eviction(gpu)) { + if (!uvm_va_block_is_hmm(block) && + uvm_va_block_size(block) == UVM_CHUNK_SIZE_MAX && + uvm_gpu_supports_eviction(gpu)) { // The chunk may not be there any more when residency is cleared. uvm_va_block_gpu_state_t *gpu_state = uvm_va_block_gpu_state_get(block, gpu->id); if (gpu_state && gpu_state->chunks[0]) @@ -2384,39 +2832,6 @@ } } -typedef enum -{ - BLOCK_TRANSFER_MODE_INTERNAL_MOVE = 1, - BLOCK_TRANSFER_MODE_INTERNAL_COPY = 2, - BLOCK_TRANSFER_MODE_INTERNAL_MOVE_TO_STAGE = 3, - BLOCK_TRANSFER_MODE_INTERNAL_MOVE_FROM_STAGE = 4, - BLOCK_TRANSFER_MODE_INTERNAL_COPY_TO_STAGE = 5, - BLOCK_TRANSFER_MODE_INTERNAL_COPY_FROM_STAGE = 6, - BLOCK_TRANSFER_MODE_INTERNAL_COPY_ONLY = 7 -} block_transfer_mode_internal_t; - -static uvm_va_block_transfer_mode_t get_block_transfer_mode_from_internal(block_transfer_mode_internal_t transfer_mode) -{ - switch (transfer_mode) { - // For HMM, BLOCK_TRANSFER_MODE_INTERNAL_COPY_ONLY is just part of a - // two phase move. First the pages are copied, then after - // migrate_vma_pages() succeeds, residency and mapping are updated. - case BLOCK_TRANSFER_MODE_INTERNAL_COPY_ONLY: - case BLOCK_TRANSFER_MODE_INTERNAL_MOVE: - case BLOCK_TRANSFER_MODE_INTERNAL_MOVE_TO_STAGE: - case BLOCK_TRANSFER_MODE_INTERNAL_MOVE_FROM_STAGE: - return UVM_VA_BLOCK_TRANSFER_MODE_MOVE; - - case BLOCK_TRANSFER_MODE_INTERNAL_COPY: - case BLOCK_TRANSFER_MODE_INTERNAL_COPY_TO_STAGE: - case BLOCK_TRANSFER_MODE_INTERNAL_COPY_FROM_STAGE: - return UVM_VA_BLOCK_TRANSFER_MODE_COPY; - } - - UVM_ASSERT_MSG(0, "Invalid transfer mode %u\n", transfer_mode); - return 0; -} - static bool block_phys_copy_contig_check(uvm_va_block_t *block, uvm_page_index_t page_index, const uvm_gpu_address_t *base_address, @@ -2437,12 +2852,13 @@ // on the processor. static bool is_block_phys_contig(uvm_va_block_t *block, uvm_processor_id_t id) { - uvm_cpu_chunk_t *chunk = uvm_cpu_chunk_first_in_block(block, NULL); + uvm_cpu_chunk_t *chunk; if (UVM_ID_IS_GPU(id)) return uvm_va_block_size(block) == block_gpu_chunk_size(block, block_get_gpu(block, id), 0); - return chunk && (uvm_va_block_size(block) <= uvm_cpu_chunk_get_size(chunk)); + chunk = uvm_cpu_chunk_first_in_region(block, uvm_va_block_region_from_block(block), NULL); + return chunk && (uvm_va_block_size(block) == uvm_cpu_chunk_get_size(chunk)); } static uvm_va_block_region_t block_phys_contig_region(uvm_va_block_t *block, @@ -2451,7 +2867,7 @@ { if (UVM_ID_IS_CPU(resident_id)) { uvm_cpu_chunk_t *chunk = uvm_cpu_chunk_get_chunk_for_page(block, page_index); - return uvm_va_block_region(page_index, page_index + uvm_cpu_chunk_num_pages(chunk)); + return uvm_cpu_chunk_block_region(block, chunk, page_index); } else { uvm_chunk_size_t chunk_size; @@ -2460,26 +2876,6 @@ } } -typedef struct -{ - // Location of the memory - uvm_processor_id_t id; - - // Whether the whole block has a single physically-contiguous chunk of - // storage on the processor. - bool is_block_contig; - - // Starting address of the physically-contiguous allocation, from the view - // of the copying GPU. Valid only if is_block_contig. - uvm_gpu_address_t address; -} block_copy_addr_t; - -typedef struct -{ - block_copy_addr_t src; - block_copy_addr_t dst; -} block_copy_state_t; - // Like block_phys_page_copy_address, but uses the address cached in bca when // possible. static uvm_gpu_address_t block_copy_get_address(uvm_va_block_t *block, @@ -2488,27 +2884,260 @@ uvm_gpu_t *copying_gpu) { if (bca->is_block_contig) { - uvm_gpu_address_t addr = bca->address; + uvm_gpu_address_t addr = bca->gpu_address; addr.address += page_index * PAGE_SIZE; - UVM_ASSERT(block_phys_copy_contig_check(block, page_index, &bca->address, bca->id, copying_gpu)); + UVM_ASSERT(block_phys_copy_contig_check(block, page_index, &bca->gpu_address, bca->id, copying_gpu)); return addr; } return block_phys_page_copy_address(block, block_phys_page(bca->id, page_index), copying_gpu); } +// When the Confidential Computing feature is enabled, the function performs +// CPU side page encryption and GPU side decryption to the CPR. +// GPU operations respect the caller's membar previously set in the push. +static void conf_computing_block_copy_push_cpu_to_gpu(uvm_va_block_t *block, + block_copy_state_t *copy_state, + uvm_va_block_region_t region, + uvm_push_t *push) +{ + uvm_push_flag_t membar_flag = 0; + uvm_gpu_t *gpu = uvm_push_get_gpu(push); + uvm_page_index_t page_index = region.first; + uvm_conf_computing_dma_buffer_t *dma_buffer = copy_state->dma_buffer; + struct page *src_page = uvm_cpu_chunk_get_cpu_page(block, page_index); + uvm_gpu_address_t staging_buffer = uvm_mem_gpu_address_virtual_kernel(dma_buffer->alloc, gpu); + uvm_gpu_address_t auth_tag_buffer = uvm_mem_gpu_address_virtual_kernel(dma_buffer->auth_tag, gpu); + char *cpu_auth_tag_buffer = (char *)uvm_mem_get_cpu_addr_kernel(dma_buffer->auth_tag) + + (page_index * UVM_CONF_COMPUTING_AUTH_TAG_SIZE); + uvm_gpu_address_t dst_address = block_copy_get_address(block, ©_state->dst, page_index, gpu); + char *cpu_va_staging_buffer = (char *)uvm_mem_get_cpu_addr_kernel(dma_buffer->alloc) + (page_index * PAGE_SIZE); + + UVM_ASSERT(UVM_ID_IS_CPU(copy_state->src.id)); + UVM_ASSERT(UVM_ID_IS_GPU(copy_state->dst.id)); + + UVM_ASSERT(uvm_conf_computing_mode_enabled(gpu)); + + // See comment in block_copy_begin_push. + UVM_ASSERT(uvm_tracker_is_completed(&block->tracker)); + + staging_buffer.address += page_index * PAGE_SIZE; + auth_tag_buffer.address += page_index * UVM_CONF_COMPUTING_AUTH_TAG_SIZE; + + if (uvm_push_get_and_reset_flag(push, UVM_PUSH_FLAG_NEXT_MEMBAR_NONE)) + membar_flag = UVM_PUSH_FLAG_NEXT_MEMBAR_NONE; + else if (uvm_push_get_and_reset_flag(push, UVM_PUSH_FLAG_NEXT_MEMBAR_GPU)) + membar_flag = UVM_PUSH_FLAG_NEXT_MEMBAR_GPU; + + // kmap() only guarantees PAGE_SIZE contiguity, all encryption and + // decryption must happen on a PAGE_SIZE basis. + for_each_va_block_page_in_region(page_index, region) { + void *src_cpu_virt_addr; + + // The caller guarantees that all pages in region are contiguous, + // meaning they're guaranteed to be part of the same compound page. + UVM_ASSERT(src_page == uvm_cpu_chunk_get_cpu_page(block, page_index)); + + src_cpu_virt_addr = kmap(src_page); + uvm_conf_computing_cpu_encrypt(push->channel, + cpu_va_staging_buffer, + src_cpu_virt_addr, + NULL, + PAGE_SIZE, + cpu_auth_tag_buffer); + kunmap(src_page); + + // First LCE operation should be non-pipelined to guarantee ordering as + // we do not know when was the last non-pipelined copy. + // Last one applies the membar originally planned for the push if any + // TODO: 3857691: Inherit policy instead of forcing first invocation to + // be non pipelined. + if (page_index > region.first) + uvm_push_set_flag(push, UVM_PUSH_FLAG_CE_NEXT_PIPELINED); + + if (page_index < (region.outer - 1)) + uvm_push_set_flag(push, UVM_PUSH_FLAG_NEXT_MEMBAR_NONE); + else if (membar_flag) + uvm_push_set_flag(push, membar_flag); + + gpu->parent->ce_hal->decrypt(push, dst_address, staging_buffer, PAGE_SIZE, auth_tag_buffer); + + src_page++; + dst_address.address += PAGE_SIZE; + cpu_va_staging_buffer += PAGE_SIZE; + staging_buffer.address += PAGE_SIZE; + cpu_auth_tag_buffer += UVM_CONF_COMPUTING_AUTH_TAG_SIZE; + auth_tag_buffer.address += UVM_CONF_COMPUTING_AUTH_TAG_SIZE; + } +} + +// When the Confidential Computing feature is enabled, the function performs +// GPU side page encryption. GPU operations respect the caller's membar +// previously set in the push. +static void conf_computing_block_copy_push_gpu_to_cpu(uvm_va_block_t *block, + block_copy_state_t *copy_state, + uvm_va_block_region_t region, + uvm_push_t *push) +{ + uvm_push_flag_t membar_flag = 0; + uvm_gpu_t *gpu = uvm_push_get_gpu(push); + uvm_page_index_t page_index = region.first; + uvm_conf_computing_dma_buffer_t *dma_buffer = copy_state->dma_buffer; + uvm_gpu_address_t staging_buffer = uvm_mem_gpu_address_virtual_kernel(dma_buffer->alloc, gpu); + uvm_gpu_address_t auth_tag_buffer = uvm_mem_gpu_address_virtual_kernel(dma_buffer->auth_tag, gpu); + uvm_gpu_address_t src_address = block_copy_get_address(block, ©_state->src, page_index, gpu); + + UVM_ASSERT(UVM_ID_IS_GPU(copy_state->src.id)); + UVM_ASSERT(UVM_ID_IS_CPU(copy_state->dst.id)); + + UVM_ASSERT(uvm_conf_computing_mode_enabled(gpu)); + + staging_buffer.address += page_index * PAGE_SIZE; + auth_tag_buffer.address += page_index * UVM_CONF_COMPUTING_AUTH_TAG_SIZE; + + if (uvm_push_get_and_reset_flag(push, UVM_PUSH_FLAG_NEXT_MEMBAR_NONE)) + membar_flag = UVM_PUSH_FLAG_NEXT_MEMBAR_NONE; + else if (uvm_push_get_and_reset_flag(push, UVM_PUSH_FLAG_NEXT_MEMBAR_GPU)) + membar_flag = UVM_PUSH_FLAG_NEXT_MEMBAR_GPU; + + // Because we use kmap() for mapping pages for CPU side + // crypto-operations and it only guarantees PAGE_SIZE contiguity, all + // encryptions and decryptions must happen on a PAGE_SIZE basis. + for_each_va_block_page_in_region(page_index, region) { + uvm_conf_computing_log_gpu_encryption(push->channel, &dma_buffer->decrypt_iv[page_index]); + + // First LCE operation should be non-pipelined to guarantee ordering as + // we do not know when was the last non-pipelined copy. + // Last one applies the membar originally planned for the push if any + // TODO: 3857691: Inherit policy instead of forcing first invocation to + // be non pipelined. + if (page_index > region.first) + uvm_push_set_flag(push, UVM_PUSH_FLAG_CE_NEXT_PIPELINED); + + if (page_index < (region.outer - 1)) + uvm_push_set_flag(push, UVM_PUSH_FLAG_NEXT_MEMBAR_NONE); + else if (membar_flag) + uvm_push_set_flag(push, membar_flag); + + gpu->parent->ce_hal->encrypt(push, staging_buffer, src_address, PAGE_SIZE, auth_tag_buffer); + + src_address.address += PAGE_SIZE; + staging_buffer.address += PAGE_SIZE; + auth_tag_buffer.address += UVM_CONF_COMPUTING_AUTH_TAG_SIZE; + } + + uvm_page_mask_region_fill(&dma_buffer->encrypted_page_mask, region); +} + +static NV_STATUS conf_computing_copy_pages_finish(uvm_va_block_t *block, + block_copy_state_t *copy_state, + uvm_push_t *push) +{ + NV_STATUS status; + uvm_page_index_t page_index; + uvm_conf_computing_dma_buffer_t *dma_buffer = copy_state->dma_buffer; + uvm_page_mask_t *encrypted_page_mask = &dma_buffer->encrypted_page_mask; + void *auth_tag_buffer_base = uvm_mem_get_cpu_addr_kernel(dma_buffer->auth_tag); + void *staging_buffer_base = uvm_mem_get_cpu_addr_kernel(dma_buffer->alloc); + + UVM_ASSERT(uvm_conf_computing_mode_enabled(push->gpu)); + + if (UVM_ID_IS_GPU(copy_state->dst.id)) + return NV_OK; + + UVM_ASSERT(UVM_ID_IS_GPU(copy_state->src.id)); + + status = uvm_push_wait(push); + if (status != NV_OK) + return status; + + // kmap() only guarantees PAGE_SIZE contiguity, all encryption and + // decryption must happen on a PAGE_SIZE basis. + for_each_va_block_page_in_mask(page_index, encrypted_page_mask, block) { + struct page *dst_page = uvm_cpu_chunk_get_cpu_page(block, page_index); + void *staging_buffer = (char *)staging_buffer_base + (page_index * PAGE_SIZE); + void *auth_tag_buffer = (char *)auth_tag_buffer_base + (page_index * UVM_CONF_COMPUTING_AUTH_TAG_SIZE); + void *cpu_page_address = kmap(dst_page); + + status = uvm_conf_computing_cpu_decrypt(push->channel, + cpu_page_address, + staging_buffer, + &dma_buffer->decrypt_iv[page_index], + PAGE_SIZE, + auth_tag_buffer); + kunmap(dst_page); + if (status != NV_OK) { + // TODO: Bug 3814087: [UVM][HCC] Handle CSL auth_tag verification + // failures & other failures gracefully. + // uvm_conf_computing_cpu_decrypt() can fail if the authentication + // tag verification fails. May this happen, it is considered a + // critical failure and cannot be recovered. + uvm_global_set_fatal_error(status); + return status; + } + } + + return NV_OK; +} + static void block_copy_push(uvm_va_block_t *block, - block_copy_state_t *state, + block_copy_state_t *copy_state, uvm_va_block_region_t region, uvm_push_t *push) { + uvm_gpu_address_t gpu_dst_address; + uvm_gpu_address_t gpu_src_address; + uvm_gpu_t *gpu = uvm_push_get_gpu(push); - uvm_gpu_t *copying_gpu = uvm_push_get_gpu(push); uvm_push_set_flag(push, UVM_PUSH_FLAG_NEXT_MEMBAR_NONE); - copying_gpu->parent->ce_hal->memcopy(push, - block_copy_get_address(block, &state->dst, region.first, copying_gpu), - block_copy_get_address(block, &state->src, region.first, copying_gpu), - uvm_va_block_region_size(region)); + + if (uvm_conf_computing_mode_enabled(gpu)) { + if (UVM_ID_IS_CPU(copy_state->src.id)) + conf_computing_block_copy_push_cpu_to_gpu(block, copy_state, region, push); + else + conf_computing_block_copy_push_gpu_to_cpu(block, copy_state, region, push); + + return; + } + + gpu_dst_address = block_copy_get_address(block, ©_state->dst, region.first, gpu); + gpu_src_address = block_copy_get_address(block, ©_state->src, region.first, gpu); + gpu->parent->ce_hal->memcopy(push, gpu_dst_address, gpu_src_address, uvm_va_block_region_size(region)); +} + +static NV_STATUS block_copy_end_push(uvm_va_block_t *block, + block_copy_state_t *copy_state, + uvm_tracker_t *copy_tracker, + NV_STATUS push_status, + uvm_push_t *push) +{ + NV_STATUS tracker_status; + + // TODO: Bug 1766424: If the destination is a GPU and the copy was done + // by that GPU, use a GPU-local membar if no peer can currently + // map this page. When peer access gets enabled, do a MEMBAR_SYS + // at that point. + uvm_push_end(push); + + if ((push_status == NV_OK) && uvm_conf_computing_mode_enabled(push->gpu)) + push_status = conf_computing_copy_pages_finish(block, copy_state, push); + + tracker_status = uvm_tracker_add_push_safe(copy_tracker, push); + if (push_status == NV_OK) + push_status = tracker_status; + + if (uvm_conf_computing_mode_enabled(push->gpu)) { + uvm_tracker_t local_tracker = UVM_TRACKER_INIT(); + + uvm_tracker_overwrite_with_push(&local_tracker, push); + uvm_conf_computing_dma_buffer_free(&push->gpu->conf_computing.dma_buffer_pool, + copy_state->dma_buffer, + &local_tracker); + copy_state->dma_buffer = NULL; + uvm_tracker_deinit(&local_tracker); + } + + return push_status; } // Copies pages resident on the src_id processor to the dst_id processor @@ -2525,13 +3154,12 @@ uvm_va_block_region_t region, uvm_page_mask_t *copy_mask, const uvm_page_mask_t *prefetch_page_mask, - block_transfer_mode_internal_t transfer_mode, + uvm_va_block_transfer_mode_t transfer_mode, uvm_page_mask_t *migrated_pages, NvU32 *copied_pages, uvm_tracker_t *copy_tracker) { - NV_STATUS tracker_status, status = NV_OK; - uvm_page_mask_t *src_resident_mask = uvm_va_block_resident_mask_get(block, src_id); + NV_STATUS status = NV_OK; uvm_page_mask_t *dst_resident_mask = uvm_va_block_resident_mask_get(block, dst_id); uvm_gpu_t *copying_gpu = NULL; uvm_push_t push; @@ -2545,15 +3173,14 @@ const bool may_prefetch = (cause == UVM_MAKE_RESIDENT_CAUSE_REPLAYABLE_FAULT || cause == UVM_MAKE_RESIDENT_CAUSE_NON_REPLAYABLE_FAULT || cause == UVM_MAKE_RESIDENT_CAUSE_ACCESS_COUNTER) && !!prefetch_page_mask; - block_copy_state_t state = {0}; + block_copy_state_t copy_state = {0}; uvm_va_range_t *va_range = block->va_range; uvm_va_space_t *va_space = uvm_va_block_get_va_space(block); - const uvm_va_block_transfer_mode_t block_transfer_mode = get_block_transfer_mode_from_internal(transfer_mode); - state.src.id = src_id; - state.dst.id = dst_id; - state.src.is_block_contig = is_block_phys_contig(block, src_id); - state.dst.is_block_contig = is_block_phys_contig(block, dst_id); + copy_state.src.id = src_id; + copy_state.dst.id = dst_id; + copy_state.src.is_block_contig = is_block_phys_contig(block, src_id); + copy_state.dst.is_block_contig = is_block_phys_contig(block, dst_id); *copied_pages = 0; @@ -2572,28 +3199,27 @@ rgr_has_changed = true; } + if (UVM_ID_IS_CPU(dst_id)) { + uvm_memcg_context_t memcg_context; + + // To support staging through CPU, populate CPU pages on demand. + // GPU destinations should have their pages populated already, but + // that might change if we add staging through GPUs. + uvm_memcg_context_start(&memcg_context, block_context->mm); + status = block_populate_pages_cpu(block, copy_mask, region, block_context); + uvm_memcg_context_end(&memcg_context); + if (status != NV_OK) + return status; + } + // TODO: Bug 3745051: This function is complicated and needs refactoring for_each_va_block_page_in_region_mask(page_index, copy_mask, region) { NvU64 page_start = uvm_va_block_cpu_page_address(block, page_index); - uvm_make_resident_cause_t page_cause = (may_prefetch && uvm_page_mask_test(prefetch_page_mask, page_index))? + uvm_make_resident_cause_t page_cause = (may_prefetch && uvm_page_mask_test(prefetch_page_mask, page_index)) ? UVM_MAKE_RESIDENT_CAUSE_PREFETCH: cause; UVM_ASSERT(block_check_resident_proximity(block, page_index, dst_id)); - - if (UVM_ID_IS_CPU(dst_id)) { - uvm_memcg_context_t memcg_context; - - // To support staging through CPU, populate CPU pages on demand. - // GPU destinations should have their pages populated already, but - // that might change if we add staging through GPUs. - uvm_memcg_context_start(&memcg_context, block_context->mm); - status = block_populate_page_cpu(block, page_index, block_context->mm); - uvm_memcg_context_end(&memcg_context); - if (status != NV_OK) - break; - } - UVM_ASSERT(block_processor_page_is_populated(block, dst_id, page_index)); // If we're not evicting and we're migrating away from the preferred @@ -2637,7 +3263,8 @@ continue; if (!copying_gpu) { - status = block_copy_begin_push(block, dst_id, src_id, &block->tracker, &push); + status = block_copy_begin_push(block, ©_state, &block->tracker, &push); + if (status != NV_OK) break; copying_gpu = uvm_push_get_gpu(&push); @@ -2657,21 +3284,36 @@ uvm_push_set_flag(&push, UVM_PUSH_FLAG_CE_NEXT_PIPELINED); } - block_update_page_dirty_state(block, dst_id, src_id, page_index); + if (!uvm_va_block_is_hmm(block)) + block_update_page_dirty_state(block, dst_id, src_id, page_index); if (last_index == region.outer) { + bool can_cache_src_phys_addr = copy_state.src.is_block_contig; + bool can_cache_dst_phys_addr = copy_state.dst.is_block_contig; contig_start_index = page_index; contig_cause = page_cause; + // When CC is enabled, transfers between GPU and CPU don't rely on + // any GPU mapping of CPU chunks, physical or virtual. + if (UVM_ID_IS_CPU(src_id) && uvm_conf_computing_mode_enabled(copying_gpu)) + can_cache_src_phys_addr = false; + if (UVM_ID_IS_CPU(dst_id) && uvm_conf_computing_mode_enabled(copying_gpu)) + can_cache_dst_phys_addr = false; // Computing the physical address is a non-trivial operation and // seems to be a performance limiter on systems with 2 or more // NVLINK links. Therefore, for physically-contiguous block // storage, we cache the start address and compute the page address // using the page index. - if (state.src.is_block_contig) - state.src.address = block_phys_page_copy_address(block, block_phys_page(src_id, 0), copying_gpu); - if (state.dst.is_block_contig) - state.dst.address = block_phys_page_copy_address(block, block_phys_page(dst_id, 0), copying_gpu); + if (can_cache_src_phys_addr) { + copy_state.src.gpu_address = block_phys_page_copy_address(block, + block_phys_page(src_id, 0), + copying_gpu); + } + if (can_cache_dst_phys_addr) { + copy_state.dst.gpu_address = block_phys_page_copy_address(block, + block_phys_page(dst_id, 0), + copying_gpu); + } } else if ((page_index != last_index + 1) || contig_cause != page_cause) { uvm_va_block_region_t contig_region = uvm_va_block_region(contig_start_index, last_index + 1); @@ -2679,8 +3321,8 @@ // If both src and dst are physically-contiguous, consolidate copies // of contiguous pages into a single method. - if (state.src.is_block_contig && state.dst.is_block_contig) - block_copy_push(block, &state, contig_region, &push); + if (copy_state.src.is_block_contig && copy_state.dst.is_block_contig) + block_copy_push(block, ©_state, contig_region, &push); uvm_perf_event_notify_migration(&va_space->perf_events, &push, @@ -2689,7 +3331,7 @@ src_id, uvm_va_block_region_start(block, contig_region), uvm_va_block_region_size(contig_region), - block_transfer_mode, + transfer_mode, contig_cause, &block_context->make_resident); @@ -2697,8 +3339,8 @@ contig_cause = page_cause; } - if (!state.src.is_block_contig || !state.dst.is_block_contig) - block_copy_push(block, &state, uvm_va_block_region_for_page(page_index), &push); + if (!copy_state.src.is_block_contig || !copy_state.dst.is_block_contig) + block_copy_push(block, ©_state, uvm_va_block_region_for_page(page_index), &push); last_index = page_index; } @@ -2708,8 +3350,8 @@ uvm_va_block_region_t contig_region = uvm_va_block_region(contig_start_index, last_index + 1); UVM_ASSERT(uvm_va_block_region_contains_region(region, contig_region)); - if (state.src.is_block_contig && state.dst.is_block_contig) - block_copy_push(block, &state, contig_region, &push); + if (copy_state.src.is_block_contig && copy_state.dst.is_block_contig) + block_copy_push(block, ©_state, contig_region, &push); uvm_perf_event_notify_migration(&va_space->perf_events, &push, @@ -2718,83 +3360,23 @@ src_id, uvm_va_block_region_start(block, contig_region), uvm_va_block_region_size(contig_region), - block_transfer_mode, + transfer_mode, contig_cause, &block_context->make_resident); - // TODO: Bug 1766424: If the destination is a GPU and the copy was done - // by that GPU, use a GPU-local membar if no peer can currently - // map this page. When peer access gets enabled, do a MEMBAR_SYS - // at that point. - uvm_push_end(&push); - tracker_status = uvm_tracker_add_push_safe(copy_tracker, &push); - if (status == NV_OK) - status = tracker_status; + status = block_copy_end_push(block, ©_state, copy_tracker, status, &push); } // Update VA block status bits // - // Only update the bits for the pages that succeded + // Only update the bits for the pages that succeeded if (status != NV_OK) uvm_page_mask_region_clear(copy_mask, uvm_va_block_region(page_index, PAGES_PER_UVM_VA_BLOCK)); *copied_pages = uvm_page_mask_weight(copy_mask); - - if (*copied_pages) { + if (*copied_pages) uvm_page_mask_or(migrated_pages, migrated_pages, copy_mask); - // For HMM, the residency is updated after migrate_vma_pages() succeeds. - if (transfer_mode != BLOCK_TRANSFER_MODE_INTERNAL_COPY_ONLY) { - uvm_page_mask_or(dst_resident_mask, dst_resident_mask, copy_mask); - block_set_resident_processor(block, dst_id); - } - - if (transfer_mode == BLOCK_TRANSFER_MODE_INTERNAL_MOVE_FROM_STAGE) { - // Check whether there are any resident pages left on src - if (!uvm_page_mask_andnot(src_resident_mask, src_resident_mask, copy_mask)) - block_clear_resident_processor(block, src_id); - } - - // If we are staging the copy due to read duplication, we keep the copy - // there - if (transfer_mode == BLOCK_TRANSFER_MODE_INTERNAL_COPY || - transfer_mode == BLOCK_TRANSFER_MODE_INTERNAL_COPY_TO_STAGE) - uvm_page_mask_or(&block->read_duplicated_pages, &block->read_duplicated_pages, copy_mask); - - if (transfer_mode == BLOCK_TRANSFER_MODE_INTERNAL_COPY_FROM_STAGE) - UVM_ASSERT(uvm_page_mask_subset(copy_mask, &block->read_duplicated_pages)); - - // Any move operation implies that mappings have been removed from all - // non-UVM-Lite GPUs - if (transfer_mode == BLOCK_TRANSFER_MODE_INTERNAL_MOVE || - transfer_mode == BLOCK_TRANSFER_MODE_INTERNAL_MOVE_TO_STAGE) - uvm_page_mask_andnot(&block->maybe_mapped_pages, &block->maybe_mapped_pages, copy_mask); - - // Record ReadDuplicate events here, after the residency bits have been - // updated - if (block_transfer_mode == UVM_VA_BLOCK_TRANSFER_MODE_COPY) - uvm_tools_record_read_duplicate(block, dst_id, region, copy_mask); - - // If we are migrating due to an eviction, set the GPU as evicted and - // mark the evicted pages. If we are migrating away from the CPU this - // means that those pages are not evicted. - if (cause == UVM_MAKE_RESIDENT_CAUSE_EVICTION) { - uvm_va_block_gpu_state_t *src_gpu_state = uvm_va_block_gpu_state_get(block, src_id); - UVM_ASSERT(src_gpu_state); - UVM_ASSERT(UVM_ID_IS_CPU(dst_id)); - - uvm_page_mask_or(&src_gpu_state->evicted, &src_gpu_state->evicted, copy_mask); - uvm_processor_mask_set(&block->evicted_gpus, src_id); - } - else if (UVM_ID_IS_GPU(dst_id) && uvm_processor_mask_test(&block->evicted_gpus, dst_id)) { - uvm_va_block_gpu_state_t *dst_gpu_state = uvm_va_block_gpu_state_get(block, dst_id); - UVM_ASSERT(dst_gpu_state); - - if (!uvm_page_mask_andnot(&dst_gpu_state->evicted, &dst_gpu_state->evicted, copy_mask)) - uvm_processor_mask_clear(&block->evicted_gpus, dst_id); - } - } - return status; } @@ -2811,7 +3393,7 @@ uvm_va_block_region_t region, const uvm_page_mask_t *page_mask, const uvm_page_mask_t *prefetch_page_mask, - block_transfer_mode_internal_t transfer_mode, + uvm_va_block_transfer_mode_t transfer_mode, NvU32 max_pages_to_copy, uvm_page_mask_t *migrated_pages, NvU32 *copied_pages_out, @@ -2820,7 +3402,7 @@ uvm_va_space_t *va_space = uvm_va_block_get_va_space(block); uvm_processor_id_t src_id; uvm_processor_mask_t search_mask; - uvm_page_mask_t *copy_mask = &block_context->make_resident.copy_resident_pages_between_mask; + uvm_page_mask_t *copy_mask = &block_context->make_resident.copy_resident_pages_mask; uvm_processor_mask_copy(&search_mask, src_processor_mask); @@ -2926,17 +3508,11 @@ first_touch_mask); } -// Copy resident pages from other processors to the destination and mark any -// pages not resident anywhere as resident on the destination. +// Copy resident pages from other processors to the destination. // All the pages on the destination need to be populated by the caller first. // Pages not resident anywhere else need to be zeroed out as well. -// -// If UVM_VA_BLOCK_TRANSFER_MODE_COPY is passed, processors that already have a -// copy of the page will keep it. Conversely, if UVM_VA_BLOCK_TRANSFER_MODE_MOVE -// is passed, the page will no longer be resident in any processor other than -// dst_id. If UVM_VA_BLOCK_TRANSFER_MODE_COPY_ONLY is passed, the destination -// pages are copied into but the residency bits for source and destination are -// not updated. +// The transfer_mode is only used to tell uvm_perf_event_notify_migration() +// whether the copy is for a migration or read duplication. static NV_STATUS block_copy_resident_pages(uvm_va_block_t *block, uvm_va_block_context_t *block_context, uvm_processor_id_t dst_id, @@ -2956,9 +3532,9 @@ uvm_page_mask_t *copy_page_mask = &block_context->make_resident.page_mask; uvm_page_mask_t *migrated_pages = &block_context->make_resident.pages_migrated; uvm_page_mask_t *staged_pages = &block_context->make_resident.pages_staged; - block_transfer_mode_internal_t transfer_mode_internal; uvm_page_mask_zero(migrated_pages); + uvm_page_mask_zero(staged_pages); if (page_mask) uvm_page_mask_andnot(copy_page_mask, page_mask, resident_mask); @@ -2967,8 +3543,6 @@ missing_pages_count = uvm_page_mask_region_weight(copy_page_mask, region); - // If nothing needs to be copied, just check if we need to break - // read-duplication (i.e. transfer_mode is UVM_VA_BLOCK_TRANSFER_MODE_MOVE) if (missing_pages_count == 0) goto out; @@ -2980,20 +3554,13 @@ uvm_processor_mask_zero(&src_processor_mask); if (!uvm_id_equal(dst_id, UVM_ID_CPU)) { - // If the destination is a GPU, first move everything from processors - // with copy access supported. Notably this will move pages from the CPU + // If the destination is a GPU, first copy everything from processors + // with copy access supported. Notably this will copy pages from the CPU // as well even if later some extra copies from CPU are required for // staged copies. uvm_processor_mask_and(&src_processor_mask, block_get_can_copy_from_mask(block, dst_id), &block->resident); uvm_processor_mask_clear(&src_processor_mask, dst_id); - if (transfer_mode == UVM_VA_BLOCK_TRANSFER_MODE_MOVE) - transfer_mode_internal = BLOCK_TRANSFER_MODE_INTERNAL_MOVE; - else if (transfer_mode == UVM_VA_BLOCK_TRANSFER_MODE_COPY) - transfer_mode_internal = BLOCK_TRANSFER_MODE_INTERNAL_COPY; - else - transfer_mode_internal = BLOCK_TRANSFER_MODE_INTERNAL_COPY_ONLY; - status = block_copy_resident_pages_mask(block, block_context, dst_id, @@ -3001,7 +3568,7 @@ region, copy_page_mask, prefetch_page_mask, - transfer_mode_internal, + transfer_mode, missing_pages_count, migrated_pages, &pages_copied, @@ -3027,21 +3594,6 @@ uvm_processor_mask_clear(&src_processor_mask, dst_id); uvm_processor_mask_clear(&src_processor_mask, UVM_ID_CPU); - uvm_page_mask_zero(staged_pages); - - if (transfer_mode == UVM_VA_BLOCK_TRANSFER_MODE_COPY_ONLY) - transfer_mode_internal = BLOCK_TRANSFER_MODE_INTERNAL_COPY_ONLY; - else if (UVM_ID_IS_CPU(dst_id)) { - transfer_mode_internal = transfer_mode == UVM_VA_BLOCK_TRANSFER_MODE_COPY? - BLOCK_TRANSFER_MODE_INTERNAL_COPY: - BLOCK_TRANSFER_MODE_INTERNAL_MOVE; - } - else { - transfer_mode_internal = transfer_mode == UVM_VA_BLOCK_TRANSFER_MODE_COPY? - BLOCK_TRANSFER_MODE_INTERNAL_COPY_TO_STAGE: - BLOCK_TRANSFER_MODE_INTERNAL_MOVE_TO_STAGE; - } - status = block_copy_resident_pages_mask(block, block_context, UVM_ID_CPU, @@ -3049,7 +3601,7 @@ region, copy_page_mask, prefetch_page_mask, - transfer_mode_internal, + transfer_mode, missing_pages_count, staged_pages, &pages_copied_to_cpu, @@ -3072,13 +3624,6 @@ goto out; uvm_tracker_clear(&local_tracker); - if (transfer_mode == UVM_VA_BLOCK_TRANSFER_MODE_MOVE) - transfer_mode_internal = BLOCK_TRANSFER_MODE_INTERNAL_MOVE_FROM_STAGE; - else if (transfer_mode == UVM_VA_BLOCK_TRANSFER_MODE_COPY) - transfer_mode_internal = BLOCK_TRANSFER_MODE_INTERNAL_COPY_FROM_STAGE; - else - transfer_mode_internal = BLOCK_TRANSFER_MODE_INTERNAL_COPY_ONLY; - // Now copy staged pages from the CPU to the destination. status = block_copy_resident_pages_between(block, block_context, @@ -3087,7 +3632,7 @@ region, staged_pages, prefetch_page_mask, - transfer_mode_internal, + transfer_mode, migrated_pages, &pages_copied, &local_tracker); @@ -3103,57 +3648,23 @@ UVM_ASSERT(pages_copied == pages_copied_to_cpu); out: - // Pages that weren't resident anywhere else were populated at the - // destination directly. Mark them as resident now. We only do it if there - // have been no errors because we cannot identify which pages failed. - // For HMM, don't do this until migrate_vma_pages() succeeds. - if (status == NV_OK && missing_pages_count > 0 && transfer_mode != UVM_VA_BLOCK_TRANSFER_MODE_COPY_ONLY) - block_copy_set_first_touch_residency(block, block_context, dst_id, region, page_mask); - - // Break read duplication - if (transfer_mode == UVM_VA_BLOCK_TRANSFER_MODE_MOVE) { - const uvm_page_mask_t *break_read_duplication_mask; - - if (status == NV_OK) { - break_read_duplication_mask = page_mask; - } - else { - // We reuse this mask since copy_page_mask is no longer used in the - // function - - if (page_mask) - uvm_page_mask_and(&block_context->make_resident.page_mask, resident_mask, page_mask); - else - uvm_page_mask_copy(&block_context->make_resident.page_mask, resident_mask); - - break_read_duplication_mask = &block_context->make_resident.page_mask; - } - break_read_duplication_in_region(block, block_context, dst_id, region, break_read_duplication_mask); - } - - // Accumulate the pages that migrated into the output mask - uvm_page_mask_or(&block_context->make_resident.pages_changed_residency, - &block_context->make_resident.pages_changed_residency, - migrated_pages); - // Add everything from the local tracker to the block's tracker. - // Notably this is also needed for handling block_copy_resident_pages_between() - // failures in the first loop. + // Notably this is also needed for handling + // block_copy_resident_pages_between() failures in the first loop. tracker_status = uvm_tracker_add_tracker_safe(&block->tracker, &local_tracker); uvm_tracker_deinit(&local_tracker); return status == NV_OK ? tracker_status : status; } -static NV_STATUS block_make_resident(uvm_va_block_t *va_block, - uvm_va_block_retry_t *va_block_retry, - uvm_va_block_context_t *va_block_context, - uvm_processor_id_t dest_id, - uvm_va_block_region_t region, - const uvm_page_mask_t *page_mask, - const uvm_page_mask_t *prefetch_page_mask, - uvm_make_resident_cause_t cause, - uvm_va_block_transfer_mode_t transfer_mode) +NV_STATUS uvm_va_block_make_resident_copy(uvm_va_block_t *va_block, + uvm_va_block_retry_t *va_block_retry, + uvm_va_block_context_t *va_block_context, + uvm_processor_id_t dest_id, + uvm_va_block_region_t region, + const uvm_page_mask_t *page_mask, + const uvm_page_mask_t *prefetch_page_mask, + uvm_make_resident_cause_t cause) { NV_STATUS status; uvm_processor_mask_t unmap_processor_mask; @@ -3171,7 +3682,6 @@ uvm_assert_mutex_locked(&va_block->lock); UVM_ASSERT(uvm_va_block_is_hmm(va_block) || va_block->va_range->type == UVM_VA_RANGE_TYPE_MANAGED); - UVM_ASSERT(uvm_va_block_check_policy_is_valid(va_block, va_block_context->policy, region)); resident_mask = block_resident_mask_get_alloc(va_block, dest_id); if (!resident_mask) @@ -3185,6 +3695,7 @@ uvm_page_mask_andnot(unmap_page_mask, page_mask, resident_mask); else uvm_page_mask_complement(unmap_page_mask, resident_mask); + uvm_page_mask_region_clear_outside(unmap_page_mask, region); // Unmap all pages not resident on the destination status = uvm_va_block_unmap_mask(va_block, va_block_context, &unmap_processor_mask, region, unmap_page_mask); @@ -3195,6 +3706,7 @@ uvm_page_mask_and(unmap_page_mask, page_mask, &va_block->read_duplicated_pages); else uvm_page_mask_init_from_region(unmap_page_mask, region, &va_block->read_duplicated_pages); + uvm_page_mask_region_clear_outside(unmap_page_mask, region); // Also unmap read-duplicated pages excluding dest_id uvm_processor_mask_clear(&unmap_processor_mask, dest_id); @@ -3207,7 +3719,7 @@ region, unmap_page_mask); - // Note that block_populate_pages and block_move_resident_pages also use + // Note that block_populate_pages and block_copy_resident_pages also use // va_block_context->make_resident.page_mask. unmap_page_mask = NULL; @@ -3215,76 +3727,77 @@ if (status != NV_OK) return status; - status = block_copy_resident_pages(va_block, - va_block_context, - dest_id, - region, - page_mask, - prefetch_page_mask, - transfer_mode); - if (status != NV_OK) - return status; + return block_copy_resident_pages(va_block, + va_block_context, + dest_id, + region, + page_mask, + prefetch_page_mask, + UVM_VA_BLOCK_TRANSFER_MODE_MOVE); +} - // Update eviction heuristics, if needed. Notably this could repeat the call - // done in block_set_resident_processor(), but that doesn't do anything bad - // and it's simpler to keep it in both places. - // - // Skip this if we didn't do anything (the input region and/or page mask was - // empty). - if (transfer_mode == UVM_VA_BLOCK_TRANSFER_MODE_MOVE && uvm_processor_mask_test(&va_block->resident, dest_id)) - block_mark_memory_used(va_block, dest_id); +static void block_make_resident_clear_evicted(uvm_va_block_t *va_block, + uvm_processor_id_t dst_id, + uvm_page_mask_t *page_mask) +{ + uvm_va_block_gpu_state_t *dst_gpu_state = uvm_va_block_gpu_state_get(va_block, dst_id); - return NV_OK; + UVM_ASSERT(dst_gpu_state); + + if (!uvm_page_mask_andnot(&dst_gpu_state->evicted, &dst_gpu_state->evicted, page_mask)) + uvm_processor_mask_clear(&va_block->evicted_gpus, dst_id); } -NV_STATUS uvm_va_block_make_resident(uvm_va_block_t *va_block, - uvm_va_block_retry_t *va_block_retry, - uvm_va_block_context_t *va_block_context, - uvm_processor_id_t dest_id, - uvm_va_block_region_t region, - const uvm_page_mask_t *page_mask, - const uvm_page_mask_t *prefetch_page_mask, - uvm_make_resident_cause_t cause) +static void block_make_resident_update_state(uvm_va_block_t *va_block, + uvm_va_block_context_t *va_block_context, + uvm_processor_id_t dst_id, + uvm_va_block_region_t region, + uvm_page_mask_t *copy_mask, + uvm_make_resident_cause_t cause) { - return block_make_resident(va_block, - va_block_retry, - va_block_context, - dest_id, - region, - page_mask, - prefetch_page_mask, - cause, - UVM_VA_BLOCK_TRANSFER_MODE_MOVE); -} + uvm_page_mask_t *dst_resident_mask = uvm_va_block_resident_mask_get(va_block, dst_id); -NV_STATUS uvm_va_block_make_resident_pre(uvm_va_block_t *va_block, - uvm_va_block_retry_t *va_block_retry, - uvm_va_block_context_t *va_block_context, - uvm_processor_id_t dest_id, - uvm_va_block_region_t region, - const uvm_page_mask_t *page_mask, - const uvm_page_mask_t *prefetch_page_mask, - uvm_make_resident_cause_t cause) -{ - return block_make_resident(va_block, - va_block_retry, - va_block_context, - dest_id, - region, - page_mask, - prefetch_page_mask, - cause, - UVM_VA_BLOCK_TRANSFER_MODE_COPY_ONLY); + uvm_page_mask_or(dst_resident_mask, dst_resident_mask, copy_mask); + block_set_resident_processor(va_block, dst_id); + + // Accumulate the pages that migrated into the output mask. + uvm_page_mask_or(&va_block_context->make_resident.pages_changed_residency, + &va_block_context->make_resident.pages_changed_residency, + copy_mask); + + // Any move operation implies that mappings have been removed from all + // non-UVM-Lite GPUs. + uvm_page_mask_andnot(&va_block->maybe_mapped_pages, &va_block->maybe_mapped_pages, copy_mask); + + // If we are migrating due to an eviction, set the GPU as evicted and + // mark the evicted pages. If we are migrating away from the CPU this + // means that those pages are not evicted. + if (cause == UVM_MAKE_RESIDENT_CAUSE_EVICTION) { + uvm_processor_id_t src_id; + + UVM_ASSERT(UVM_ID_IS_CPU(dst_id)); + + // Note that the destination is the CPU so this loop excludes it. + for_each_gpu_id_in_mask(src_id, &va_block_context->make_resident.all_involved_processors) { + uvm_va_block_gpu_state_t *src_gpu_state = uvm_va_block_gpu_state_get(va_block, src_id); + + UVM_ASSERT(src_gpu_state); + + uvm_page_mask_or(&src_gpu_state->evicted, &src_gpu_state->evicted, copy_mask); + uvm_processor_mask_set(&va_block->evicted_gpus, src_id); + } + } + else if (UVM_ID_IS_GPU(dst_id) && uvm_processor_mask_test(&va_block->evicted_gpus, dst_id)) + block_make_resident_clear_evicted(va_block, dst_id, copy_mask); } -void uvm_va_block_make_resident_post(uvm_va_block_t *va_block, - uvm_va_block_context_t *va_block_context, - uvm_va_block_region_t region, - const uvm_page_mask_t *page_mask) +void uvm_va_block_make_resident_finish(uvm_va_block_t *va_block, + uvm_va_block_context_t *va_block_context, + uvm_va_block_region_t region, + const uvm_page_mask_t *page_mask) { uvm_page_mask_t *migrated_pages = &va_block_context->make_resident.pages_migrated; uvm_processor_id_t dst_id = va_block_context->make_resident.dest_id; - uvm_page_mask_t *dst_resident_mask = uvm_va_block_resident_mask_get(va_block, dst_id); uvm_assert_mutex_locked(&va_block->lock); @@ -3293,20 +3806,18 @@ if (!uvm_page_mask_empty(migrated_pages)) { // The migrated pages are now resident on the destination. - uvm_page_mask_or(dst_resident_mask, dst_resident_mask, migrated_pages); - block_set_resident_processor(va_block, dst_id); + block_make_resident_update_state(va_block, + va_block_context, + dst_id, + region, + migrated_pages, + va_block_context->make_resident.cause); } // Pages that weren't resident anywhere else were populated at the - // destination directly. Mark them as resident now. We only do it if there - // have been no errors because we cannot identify which pages failed. - // For HMM, don't do this until migrate_vma_pages() succeeds. + // destination directly. Mark them as resident now. block_copy_set_first_touch_residency(va_block, va_block_context, dst_id, region, page_mask); - // Any move operation implies that mappings have been removed from all - // non-UVM-Lite GPUs. - uvm_page_mask_andnot(&va_block->maybe_mapped_pages, &va_block->maybe_mapped_pages, migrated_pages); - // Break read duplication and clear residency from other processors. break_read_duplication_in_region(va_block, va_block_context, dst_id, region, page_mask); @@ -3320,6 +3831,36 @@ block_mark_memory_used(va_block, dst_id); } +NV_STATUS uvm_va_block_make_resident(uvm_va_block_t *va_block, + uvm_va_block_retry_t *va_block_retry, + uvm_va_block_context_t *va_block_context, + uvm_processor_id_t dest_id, + uvm_va_block_region_t region, + const uvm_page_mask_t *page_mask, + const uvm_page_mask_t *prefetch_page_mask, + uvm_make_resident_cause_t cause) +{ + NV_STATUS status; + + status = uvm_va_block_make_resident_copy(va_block, + va_block_retry, + va_block_context, + dest_id, + region, + page_mask, + prefetch_page_mask, + cause); + if (status != NV_OK) + return status; + + uvm_va_block_make_resident_finish(va_block, + va_block_context, + region, + page_mask); + + return NV_OK; +} + // Combination function which prepares the input {region, page_mask} for // entering read-duplication. It: // - Unmaps all processors but revoke_id @@ -3379,10 +3920,14 @@ { NV_STATUS status = NV_OK; uvm_processor_id_t src_id; + uvm_page_mask_t *dst_resident_mask; + uvm_page_mask_t *cpu_resident_mask; + uvm_page_mask_t *migrated_pages; + uvm_page_mask_t *staged_pages; + uvm_page_mask_t *first_touch_mask; // TODO: Bug 3660922: need to implement HMM read duplication support. UVM_ASSERT(!uvm_va_block_is_hmm(va_block)); - UVM_ASSERT(va_block_context->policy == uvm_va_range_get_policy(va_block->va_range)); va_block_context->make_resident.dest_id = dest_id; va_block_context->make_resident.cause = cause; @@ -3405,7 +3950,7 @@ // - Revokes write access from the processor with the resident copy for_each_id_in_mask(src_id, &va_block->resident) { // Note that the below calls to block_populate_pages and - // block_move_resident_pages also use + // block_copy_resident_pages also use // va_block_context->make_resident.page_mask. uvm_page_mask_t *preprocess_page_mask = &va_block_context->make_resident.page_mask; const uvm_page_mask_t *resident_mask = uvm_va_block_resident_mask_get(va_block, src_id); @@ -3440,6 +3985,42 @@ if (status != NV_OK) return status; + // Pages that weren't resident anywhere else were populated at the + // destination directly. Mark them as resident now, since there were no + // errors from block_copy_resident_pages() above. + // Note that va_block_context->scratch_page_mask is passed to + // block_copy_set_first_touch_residency() which is generally unsafe but in + // this case, block_copy_set_first_touch_residency() copies page_mask + // before scratch_page_mask could be clobbered. + migrated_pages = &va_block_context->make_resident.pages_migrated; + first_touch_mask = &va_block_context->scratch_page_mask; + uvm_page_mask_init_from_region(first_touch_mask, region, page_mask); + uvm_page_mask_andnot(first_touch_mask, first_touch_mask, migrated_pages); + + if (!uvm_page_mask_empty(first_touch_mask)) + block_copy_set_first_touch_residency(va_block, va_block_context, dest_id, region, first_touch_mask); + + staged_pages = &va_block_context->make_resident.pages_staged; + if (!UVM_ID_IS_CPU(dest_id) && !uvm_page_mask_empty(staged_pages)) { + cpu_resident_mask = uvm_va_block_resident_mask_get(va_block, UVM_ID_CPU); + uvm_page_mask_or(cpu_resident_mask, cpu_resident_mask, staged_pages); + block_set_resident_processor(va_block, UVM_ID_CPU); + uvm_page_mask_or(&va_block->read_duplicated_pages, &va_block->read_duplicated_pages, staged_pages); + uvm_tools_record_read_duplicate(va_block, UVM_ID_CPU, region, staged_pages); + } + + if (!uvm_page_mask_empty(migrated_pages)) { + dst_resident_mask = uvm_va_block_resident_mask_get(va_block, dest_id); + uvm_page_mask_or(dst_resident_mask, dst_resident_mask, migrated_pages); + block_set_resident_processor(va_block, dest_id); + uvm_page_mask_or(&va_block->read_duplicated_pages, &va_block->read_duplicated_pages, migrated_pages); + uvm_tools_record_read_duplicate(va_block, dest_id, region, migrated_pages); + } + + UVM_ASSERT(cause != UVM_MAKE_RESIDENT_CAUSE_EVICTION); + if (UVM_ID_IS_GPU(dest_id) && uvm_processor_mask_test(&va_block->evicted_gpus, dest_id)) + block_make_resident_clear_evicted(va_block, dest_id, migrated_pages); + // Update eviction heuristics, if needed. Notably this could repeat the call // done in block_set_resident_processor(), but that doesn't do anything bad // and it's simpler to keep it in both places. @@ -3558,7 +4139,7 @@ } // Sanity check the given GPU's chunks array -static bool block_check_chunks(uvm_va_block_t *block, uvm_gpu_id_t id) +static bool block_check_gpu_chunks(uvm_va_block_t *block, uvm_gpu_id_t id) { uvm_va_block_gpu_state_t *gpu_state = uvm_va_block_gpu_state_get(block, id); uvm_gpu_t *gpu; @@ -3624,6 +4205,18 @@ return true; } +static bool block_check_chunks(uvm_va_block_t *va_block) +{ + uvm_gpu_id_t id; + + for_each_gpu_id(id) { + if (!block_check_gpu_chunks(va_block, id)) + return false; + } + + return block_check_cpu_chunks(va_block); +} + // Sanity checks for page mappings static bool block_check_mappings_page(uvm_va_block_t *block, uvm_page_index_t page_index) { @@ -3641,12 +4234,9 @@ UVM_ID_INVALID; const uvm_processor_mask_t *uvm_lite_gpus = block_get_uvm_lite_gpus(block); - uvm_va_block_page_authorized_processors(block, page_index, UVM_PROT_READ_WRITE_ATOMIC, - &atomic_mappings); - uvm_va_block_page_authorized_processors(block, page_index, UVM_PROT_READ_WRITE, - &write_mappings); - uvm_va_block_page_authorized_processors(block, page_index, UVM_PROT_READ_ONLY, - &read_mappings); + block_page_authorized_processors(block, page_index, UVM_PROT_READ_WRITE_ATOMIC, &atomic_mappings); + block_page_authorized_processors(block, page_index, UVM_PROT_READ_WRITE, &write_mappings); + block_page_authorized_processors(block, page_index, UVM_PROT_READ_ONLY, &read_mappings); // Each access bit implies all accesses below it UVM_ASSERT(uvm_processor_mask_subset(&atomic_mappings, &write_mappings)); @@ -3952,7 +4542,9 @@ UVM_ASSERT(uvm_gpu_chunk_get_size(resident_gpu_state->chunks[0]) == UVM_CHUNK_SIZE_2M); } else { - uvm_cpu_chunk_t *chunk = uvm_cpu_chunk_first_in_block(block, NULL); + uvm_cpu_chunk_t *chunk = uvm_cpu_chunk_first_in_region(block, + uvm_va_block_region_from_block(block), + NULL); UVM_ASSERT(uvm_page_mask_full(&block->cpu.allocated)); UVM_ASSERT(chunk); @@ -4078,9 +4670,17 @@ uvm_va_block_region_t subregion; NvU32 num_mapped_processors; - // Early-out if nothing in the region is mapped - if (!block_has_valid_mapping_cpu(block, region)) + // Early-out if nothing in the region is mapped or being unmapped. + if (!block_has_valid_mapping_cpu(block, region) || + (unmap_pages && !uvm_page_mask_intersects(unmap_pages, &block->cpu.pte_bits[UVM_PTE_BITS_CPU_READ]))) + return; + + // We can't actually unmap HMM ranges from the CPU here. + // Unmapping happens as part of migrate_vma_setup(). + if (uvm_va_block_is_hmm(block)) { + UVM_ASSERT(!uvm_va_block_is_hmm(block)); return; + } num_mapped_processors = uvm_processor_mask_get_count(&block->mapped); @@ -4095,12 +4695,9 @@ if (!block_has_valid_mapping_cpu(block, subregion)) continue; - // We can't actually unmap HMM ranges from the CPU here. - // It happens as part of migrate_vma_setup(). - if (!uvm_va_block_is_hmm(block)) - unmap_mapping_range(&va_space->mapping, - uvm_va_block_region_start(block, subregion), - uvm_va_block_region_size(subregion), 1); + unmap_mapping_range(va_space->mapping, + uvm_va_block_region_start(block, subregion), + uvm_va_block_region_size(subregion), 1); for (pte_bit = 0; pte_bit < UVM_PTE_BITS_CPU_MAX; pte_bit++) uvm_page_mask_region_clear(&block->cpu.pte_bits[pte_bit], subregion); @@ -4128,7 +4725,7 @@ // Given a mask of mapped pages, returns true if any of the pages in the mask // are mapped remotely by the given GPU. static bool block_has_remote_mapping_gpu(uvm_va_block_t *block, - uvm_va_block_context_t *block_context, + uvm_page_mask_t *scratch_page_mask, uvm_gpu_id_t gpu_id, const uvm_page_mask_t *mapped_pages) { @@ -4150,7 +4747,7 @@ } // Remote pages are pages which are mapped but not resident locally - return uvm_page_mask_andnot(&block_context->scratch_page_mask, mapped_pages, &gpu_state->resident); + return uvm_page_mask_andnot(scratch_page_mask, mapped_pages, &gpu_state->resident); } // Writes pte_clear_val to the 4k PTEs covered by clear_page_mask. If @@ -4226,7 +4823,7 @@ size_t i; // Assume that this mapping will be used to write to the page - if (new_prot > UVM_PROT_READ_ONLY && UVM_ID_IS_CPU(resident_id)) + if (new_prot > UVM_PROT_READ_ONLY && UVM_ID_IS_CPU(resident_id) && !uvm_va_block_is_hmm(block)) block_mark_cpu_page_dirty(block, page_index); if (page_index >= contig_region.outer) { @@ -4434,7 +5031,7 @@ uvm_va_block_region_t big_region = uvm_va_block_big_page_region(block, big_page_index, big_page_size); // Assume that this mapping will be used to write to the page - if (new_prot > UVM_PROT_READ_ONLY && UVM_ID_IS_CPU(resident_id)) { + if (new_prot > UVM_PROT_READ_ONLY && UVM_ID_IS_CPU(resident_id) && !uvm_va_block_is_hmm(block)) { uvm_page_index_t page_index; for_each_va_block_page_in_region(page_index, big_region) @@ -4586,7 +5183,7 @@ UVM_ASSERT(new_prot != UVM_PROT_NONE); UVM_ASSERT(UVM_ID_IS_VALID(resident_id)); - if (UVM_ID_IS_CPU(resident_id)) + if (UVM_ID_IS_CPU(resident_id) && !uvm_va_block_is_hmm(block)) block_mark_cpu_page_dirty(block, 0); page_addr = block_phys_page_address(block, block_phys_page(resident_id, 0), gpu); @@ -4775,13 +5372,7 @@ UVM_ASSERT(UVM_ID_IS_VALID(resident_id)); UVM_ASSERT(pte_op == BLOCK_PTE_OP_REVOKE); - // Permissions downgrades always need a membar on TLB invalidate. If the - // mapped memory was local, we only need a GPU-local membar. - if (uvm_id_equal(gpu->id, resident_id)) - return UVM_MEMBAR_GPU; - - // Otherwise, remote memory needs a sysmembar - return UVM_MEMBAR_SYS; + return uvm_hal_downgrade_membar_type(gpu, uvm_id_equal(gpu->id, resident_id)); } // Write the 2M PTE for {block, gpu} to the memory on resident_id with new_prot @@ -5605,17 +6196,26 @@ if (gpu_state->force_4k_ptes) return; + // Limit HMM GPU allocations to PAGE_SIZE since migrate_vma_*(), + // hmm_range_fault(), and make_device_exclusive_range() don't handle folios + // yet. Also, it makes mremap() difficult since the new address may not + // align with the GPU block size otherwise. + // If PAGE_SIZE is 64K, the code following this check is OK since 64K + // big_pages is supported on all HMM supported GPUs (Turing+). + // TODO: Bug 3368756: add support for transparent huge pages (THP). + if (uvm_va_block_is_hmm(block) && PAGE_SIZE == UVM_PAGE_SIZE_4K) + return; + UVM_ASSERT(uvm_page_mask_subset(pages_changing, page_mask_after)); - if (block_gpu_supports_2m(block, gpu)) { - // If all pages in the 2M mask have the same attributes after the - // operation is applied, we can use a 2M PTE. - if (uvm_page_mask_full(page_mask_after) && - (!UVM_ID_IS_CPU(resident_id) || is_block_phys_contig(block, UVM_ID_CPU))) { - new_pte_state->pte_is_2m = true; - new_pte_state->needs_4k = false; - return; - } + // If all pages in the 2M mask have the same attributes after the + // operation is applied, we can use a 2M PTE. + if (block_gpu_supports_2m(block, gpu) && + uvm_page_mask_full(page_mask_after) && + (UVM_ID_IS_INVALID(resident_id) || is_block_phys_contig(block, resident_id))) { + new_pte_state->pte_is_2m = true; + new_pte_state->needs_4k = false; + return; } // Find big PTEs with matching attributes @@ -5736,7 +6336,6 @@ uvm_tracker_t *pending_tracker) { uvm_va_block_gpu_state_t *gpu_state = uvm_va_block_gpu_state_get(va_block, gpu->id); - uvm_va_space_t *va_space = uvm_va_block_get_va_space(va_block); uvm_gpu_va_space_t *gpu_va_space = uvm_va_block_get_gpu_va_space(va_block, gpu); uvm_page_tree_t *page_tables = &gpu_va_space->page_tables; uvm_va_block_test_t *va_block_test = uvm_va_block_get_test(va_block); @@ -5754,7 +6353,6 @@ // to allocate the lower levels. bool use_alloc_table = block_gpu_supports_2m(va_block, gpu) && page_size < UVM_PAGE_SIZE_2M; - uvm_assert_rwsem_locked(&va_space->lock); UVM_ASSERT(page_table_range->table == NULL); if (va_block_test && va_block_test->page_table_allocation_retry_force_count > 0) { @@ -5946,26 +6544,31 @@ uvm_gpu_va_space_t *gpu_va_space, uvm_tracker_t *pending_tracker) { - NvU32 page_sizes = 0; - uvm_gpu_t *gpu = gpu_va_space->gpu; - uvm_va_block_gpu_state_t *gpu_state = block_gpu_state_get_alloc(block, gpu); + NvU32 page_sizes; + NvU32 big_page_size; + uvm_gpu_t *gpu; + uvm_va_block_gpu_state_t *gpu_state; - UVM_ASSERT(gpu_state); + UVM_ASSERT(block); UVM_ASSERT(gpu_va_space); - UVM_ASSERT(uvm_gpu_va_space_state(gpu_va_space) == UVM_GPU_VA_SPACE_STATE_ACTIVE); UVM_ASSERT(gpu_va_space->ats.enabled); + UVM_ASSERT(uvm_gpu_va_space_state(gpu_va_space) == UVM_GPU_VA_SPACE_STATE_ACTIVE); + + gpu = gpu_va_space->gpu; + big_page_size = gpu_va_space->page_tables.big_page_size; + + gpu_state = block_gpu_state_get_alloc(block, gpu); + if (!gpu_state) + return NV_ERR_NO_MEMORY; // If the VA Block supports 2M pages, allocate the 2M PTE only, as it // requires less memory - if (block_gpu_supports_2m(block, gpu)) { + if (block_gpu_supports_2m(block, gpu)) page_sizes = UVM_PAGE_SIZE_2M; - } - else { - // ATS is only enabled on P9 + Volta, therefore, PAGE_SIZE should - // be 64K and should match Volta big page size - UVM_ASSERT(uvm_va_block_gpu_big_page_size(block, gpu) == PAGE_SIZE); - page_sizes = UVM_PAGE_SIZE_64K; - } + else if (uvm_va_block_num_big_pages(block, big_page_size) > 0) + page_sizes = big_page_size; + else + page_sizes = UVM_PAGE_SIZE_4K; return block_alloc_ptes_with_retry(block, gpu, page_sizes, pending_tracker); } @@ -6004,7 +6607,8 @@ uvm_va_block_gpu_state_t *gpu_state = uvm_va_block_gpu_state_get(block, gpu->id); uvm_pte_bits_gpu_t pte_bit; uvm_push_t push; - uvm_membar_t tlb_membar = UVM_MEMBAR_GPU; + uvm_membar_t tlb_membar; + bool only_local_mappings; uvm_page_mask_t *pages_to_unmap = &block_context->mapping.page_mask; NV_STATUS status; uvm_va_block_new_pte_state_t *new_pte_state = &block_context->mapping.new_pte_state; @@ -6038,10 +6642,8 @@ if (status != NV_OK) return status; - // All PTE downgrades need a membar. If any of the unmapped PTEs pointed to - // remote memory, we must use a sysmembar. - if (block_has_remote_mapping_gpu(block, block_context, gpu->id, pages_to_unmap)) - tlb_membar = UVM_MEMBAR_SYS; + only_local_mappings = !block_has_remote_mapping_gpu(block, &block_context->scratch_page_mask, gpu->id, pages_to_unmap); + tlb_membar = uvm_hal_downgrade_membar_type(gpu, only_local_mappings); status = uvm_push_begin_acquire(gpu->channel_manager, UVM_CHANNEL_TYPE_MEMOPS, @@ -6175,16 +6777,15 @@ } static uvm_prot_t compute_logical_prot(uvm_va_block_t *va_block, - uvm_va_block_context_t *va_block_context, + struct vm_area_struct *hmm_vma, uvm_page_index_t page_index) { - struct vm_area_struct *vma; uvm_prot_t logical_prot; if (uvm_va_block_is_hmm(va_block)) { NvU64 addr = uvm_va_block_cpu_page_address(va_block, page_index); - logical_prot = uvm_hmm_compute_logical_prot(va_block, va_block_context, addr); + logical_prot = uvm_hmm_compute_logical_prot(va_block, hmm_vma, addr); } else { uvm_va_range_t *va_range = va_block->va_range; @@ -6196,6 +6797,8 @@ logical_prot = UVM_PROT_NONE; } else { + struct vm_area_struct *vma; + vma = uvm_va_range_vma(va_range); if (!(vma->vm_flags & VM_READ)) @@ -6210,6 +6813,27 @@ return logical_prot; } +static struct page *block_page_get(uvm_va_block_t *block, block_phys_page_t block_page) +{ + struct page *page; + + if (UVM_ID_IS_CPU(block_page.processor)) { + page = uvm_cpu_chunk_get_cpu_page(block, block_page.page_index); + } + else { + uvm_va_space_t *va_space = uvm_va_block_get_va_space(block); + uvm_gpu_t *gpu = uvm_va_space_get_gpu(va_space, block_page.processor); + size_t chunk_offset; + uvm_gpu_chunk_t *chunk = block_phys_page_chunk(block, block_page, &chunk_offset); + + UVM_ASSERT(gpu->mem_info.numa.enabled); + page = uvm_gpu_chunk_to_page(&gpu->pmm, chunk) + chunk_offset / PAGE_SIZE; + } + + UVM_ASSERT(page); + return page; +} + // Creates or upgrades a CPU mapping for the given page, updating the block's // mapping and pte_bits bitmaps as appropriate. Upon successful return, the page // will be mapped with at least new_prot permissions. @@ -6224,13 +6848,15 @@ // with new_prot permissions // - Guarantee that vm_insert_page is safe to use (vma->vm_mm has a reference // and mmap_lock is held in at least read mode) +// - For HMM blocks that vma is valid and safe to use, vma->vm_mm has a +// reference and mmap_lock is held in at least read mode // - Ensure that the struct page corresponding to the physical memory being // mapped exists // - Manage the block's residency bitmap // - Ensure that the block hasn't been killed (block->va_range is present) // - Update the pte/mapping tracking state on success static NV_STATUS block_map_cpu_page_to(uvm_va_block_t *block, - uvm_va_block_context_t *va_block_context, + struct vm_area_struct *hmm_vma, uvm_processor_id_t resident_id, uvm_page_index_t page_index, uvm_prot_t new_prot) @@ -6243,7 +6869,7 @@ NvU64 addr; struct page *page; - UVM_ASSERT(uvm_va_block_is_hmm(block) || va_range->type == UVM_VA_RANGE_TYPE_MANAGED); + UVM_ASSERT((uvm_va_block_is_hmm(block) && hmm_vma) || va_range->type == UVM_VA_RANGE_TYPE_MANAGED); UVM_ASSERT(new_prot != UVM_PROT_NONE); UVM_ASSERT(new_prot < UVM_PROT_MAX); UVM_ASSERT(uvm_processor_mask_test(&va_space->accessible_from[uvm_id_value(resident_id)], UVM_ID_CPU)); @@ -6264,7 +6890,7 @@ // Check for existing VMA permissions. They could have been modified after // the initial mmap by mprotect. - if (new_prot > compute_logical_prot(block, va_block_context, page_index)) + if (new_prot > compute_logical_prot(block, hmm_vma, page_index)) return NV_ERR_INVALID_ACCESS_TYPE; if (uvm_va_block_is_hmm(block)) { @@ -6304,7 +6930,7 @@ // there's already a mapping present at fault_addr, so we have to unmap // first anyway when upgrading from RO -> RW. if (curr_prot != UVM_PROT_NONE) - unmap_mapping_range(&va_space->mapping, addr, PAGE_SIZE, 1); + unmap_mapping_range(va_space->mapping, addr, PAGE_SIZE, 1); // Don't map the CPU until prior copies and GPU PTE updates finish, // otherwise we might not stay coherent. @@ -6312,24 +6938,7 @@ if (status != NV_OK) return status; - if (UVM_ID_IS_CPU(resident_id)) { - uvm_cpu_chunk_t *chunk = uvm_cpu_chunk_get_chunk_for_page(block, page_index); - - // TODO: Bug 3283417: This can be removed if vm_insert_pages() is used instead of - // vm_insert_page(). - page = uvm_cpu_chunk_get_cpu_page(block, chunk, page_index); - UVM_ASSERT(page); - } - else { - uvm_gpu_t *gpu = uvm_va_space_get_gpu(va_space, resident_id); - size_t chunk_offset; - uvm_gpu_chunk_t *chunk = block_phys_page_chunk(block, block_phys_page(resident_id, page_index), &chunk_offset); - - UVM_ASSERT(gpu->parent->numa_info.enabled); - - page = uvm_gpu_chunk_to_page(&gpu->pmm, chunk) + chunk_offset / PAGE_SIZE; - } - + page = block_page_get(block, block_phys_page(resident_id, page_index)); return uvm_cpu_insert_page(vma, addr, page, new_prot); } @@ -6378,7 +6987,7 @@ for_each_va_block_page_in_region_mask(page_index, pages_to_map, region) { status = block_map_cpu_page_to(block, - block_context, + block_context->hmm.vma, resident_id, page_index, new_prot); @@ -6559,7 +7168,8 @@ } static void map_get_allowed_destinations(uvm_va_block_t *block, - uvm_va_policy_t *policy, + uvm_va_block_context_t *va_block_context, + const uvm_va_policy_t *policy, uvm_processor_id_t id, uvm_processor_mask_t *allowed_mask) { @@ -6570,7 +7180,10 @@ uvm_processor_mask_zero(allowed_mask); uvm_processor_mask_set(allowed_mask, policy->preferred_location); } - else if ((uvm_va_policy_is_read_duplicate(policy, va_space) || uvm_id_equal(policy->preferred_location, id)) && + else if ((uvm_va_policy_is_read_duplicate(policy, va_space) || + (uvm_id_equal(policy->preferred_location, id) && + !is_uvm_fault_force_sysmem_set() && + !uvm_hmm_must_use_sysmem(block, va_block_context))) && uvm_va_space_processor_has_memory(va_space, id)) { // When operating under read-duplication we should only map the local // processor to cause fault-and-duplicate of remote pages. @@ -6607,13 +7220,13 @@ const uvm_page_mask_t *pte_mask; uvm_page_mask_t *running_page_mask = &va_block_context->mapping.map_running_page_mask; NV_STATUS status; + const uvm_va_policy_t *policy = uvm_va_policy_get_region(va_block, region); va_block_context->mapping.cause = cause; UVM_ASSERT(new_prot != UVM_PROT_NONE); UVM_ASSERT(new_prot < UVM_PROT_MAX); uvm_assert_mutex_locked(&va_block->lock); - UVM_ASSERT(uvm_va_block_check_policy_is_valid(va_block, va_block_context->policy, region)); // Mapping is not supported on the eviction path that doesn't hold the VA // space lock. @@ -6655,7 +7268,7 @@ // Map per resident location so we can more easily detect physically- // contiguous mappings. - map_get_allowed_destinations(va_block, va_block_context->policy, id, &allowed_destinations); + map_get_allowed_destinations(va_block, va_block_context, policy, id, &allowed_destinations); for_each_closest_id(resident_id, &allowed_destinations, id, va_space) { if (UVM_ID_IS_CPU(id)) { @@ -6893,6 +7506,12 @@ if (prot_to_revoke == UVM_PROT_READ_WRITE_ATOMIC) return NV_OK; + if (uvm_va_block_is_hmm(va_block)) { + // Linux is responsible for CPU page table updates. + uvm_page_mask_region_clear(&va_block->cpu.pte_bits[UVM_PTE_BITS_CPU_WRITE], region); + return NV_OK; + } + uvm_page_mask_init_from_region(running_page_mask, region, revoke_page_mask); if (uvm_page_mask_and(running_page_mask, running_page_mask, &va_block->cpu.pte_bits[UVM_PTE_BITS_CPU_WRITE])) @@ -6955,8 +7574,6 @@ NV_STATUS tracker_status; uvm_processor_id_t id; - UVM_ASSERT(uvm_va_block_check_policy_is_valid(va_block, va_block_context->policy, region)); - for_each_id_in_mask(id, map_processor_mask) { status = uvm_va_block_map(va_block, va_block_context, @@ -7151,7 +7768,6 @@ uvm_tracker_wait(&block->tracker); block_gpu_unmap_phys_all_cpu_pages(block, gpu); - uvm_cpu_chunk_gpu_mapping_free(block, gpu->id); uvm_processor_mask_clear(&block->evicted_gpus, id); kmem_cache_free(g_uvm_va_block_gpu_state_cache, gpu_state); @@ -7405,13 +8021,22 @@ // Move all subregions resident on the GPU to the CPU for_each_va_block_subregion_in_mask(subregion, resident, region) { - status = uvm_va_block_migrate_locked(va_block, - NULL, - block_context, - subregion, - UVM_ID_CPU, - UVM_MIGRATE_MODE_MAKE_RESIDENT_AND_MAP, - NULL); + if (uvm_va_block_is_hmm(va_block)) { + status = uvm_hmm_va_block_evict_pages_from_gpu(va_block, + gpu, + block_context, + resident, + subregion); + } + else { + status = uvm_va_block_migrate_locked(va_block, + NULL, + block_context, + subregion, + UVM_ID_CPU, + UVM_MIGRATE_MODE_MAKE_RESIDENT_AND_MAP, + NULL); + } if (status != NV_OK) return status; } @@ -7420,9 +8045,7 @@ return NV_OK; } -// This handles allocation-retry internally and hence might unlock and relock -// block's lock. -static void block_unregister_gpu_locked(uvm_va_block_t *va_block, uvm_gpu_t *gpu, struct mm_struct *mm) +void uvm_va_block_unregister_gpu_locked(uvm_va_block_t *va_block, uvm_gpu_t *gpu, struct mm_struct *mm) { NV_STATUS status; uvm_va_block_gpu_state_t *gpu_state = uvm_va_block_gpu_state_get(va_block, gpu->id); @@ -7467,7 +8090,7 @@ // Take the lock internally to not expose the caller to allocation-retry. uvm_mutex_lock(&va_block->lock); - block_unregister_gpu_locked(va_block, gpu, mm); + uvm_va_block_unregister_gpu_locked(va_block, gpu, mm); uvm_mutex_unlock(&va_block->lock); } @@ -7496,6 +8119,7 @@ NV_STATUS status; uvm_va_block_region_t region = uvm_va_block_region_from_block(block); uvm_page_index_t page_index; + uvm_page_index_t next_page_index; if (uvm_va_block_is_dead(block)) return; @@ -7510,6 +8134,14 @@ if (!uvm_processor_mask_empty(&block->mapped)) { uvm_va_block_context_t *block_context = uvm_va_space_block_context(va_space, NULL); + // HMM CPU mappings are controlled by Linux so no need to unmap. + // Remote GPU mappings will be removed below. + if (uvm_va_block_is_hmm(block) && uvm_processor_mask_test(&block->mapped, UVM_ID_CPU)) { + uvm_page_mask_zero(&block->cpu.pte_bits[UVM_PTE_BITS_CPU_WRITE]); + uvm_page_mask_zero(&block->cpu.pte_bits[UVM_PTE_BITS_CPU_READ]); + uvm_processor_mask_clear(&block->mapped, UVM_ID_CPU); + } + // We could only be killed with mapped GPU state by VA range free or VA // space teardown, so it's safe to use the va_space's block_context // because both of those have the VA space lock held in write mode. @@ -7530,16 +8162,14 @@ UVM_ASSERT(block_check_processor_not_mapped(block, UVM_ID_CPU)); // Free CPU pages - for_each_va_block_page(page_index, block) { - chunk = uvm_cpu_chunk_get_chunk_for_page(block, page_index); - if (!chunk) - continue; - + for_each_cpu_chunk_in_block_safe(chunk, page_index, next_page_index, block) { // be conservative. - // Tell the OS we wrote to the page because we sometimes clear the dirty bit after writing to it. - uvm_cpu_chunk_mark_dirty(chunk, page_index); - uvm_cpu_chunk_remove_from_block(block, chunk, page_index); - uvm_cpu_chunk_put(chunk); + // Tell the OS we wrote to the page because we sometimes clear the dirty + // bit after writing to it. HMM dirty flags are managed by the kernel. + if (!uvm_va_block_is_hmm(block)) + uvm_cpu_chunk_mark_dirty(chunk, 0); + uvm_cpu_chunk_remove_from_block(block, page_index); + uvm_cpu_chunk_free(chunk); } uvm_kvfree((void *)block->cpu.chunks); @@ -7591,6 +8221,75 @@ uvm_va_block_release(va_block); } +static void block_gpu_release_region(uvm_va_block_t *va_block, + uvm_gpu_id_t gpu_id, + uvm_va_block_gpu_state_t *gpu_state, + uvm_page_mask_t *page_mask, + uvm_va_block_region_t region) +{ + uvm_page_index_t page_index; + + for_each_va_block_page_in_region_mask(page_index, page_mask, region) { + uvm_gpu_chunk_t *gpu_chunk = gpu_state->chunks[page_index]; + + if (!gpu_chunk) + continue; + + // TODO: Bug 3898467: unmap indirect peers when freeing GPU chunks + + uvm_mmu_chunk_unmap(gpu_chunk, &va_block->tracker); + + // The GPU chunk will be freed when the device private reference drops. + if (uvm_page_mask_test_and_clear(&gpu_state->resident, page_index) && + uvm_page_mask_empty(&gpu_state->resident)) + block_clear_resident_processor(va_block, gpu_id); + + gpu_state->chunks[page_index] = NULL; + } +} + +void uvm_va_block_munmap_region(uvm_va_block_t *va_block, + uvm_va_block_region_t region) +{ + uvm_va_space_t *va_space = uvm_va_block_get_va_space(va_block); + uvm_perf_event_data_t event_data; + uvm_gpu_id_t gpu_id; + + UVM_ASSERT(uvm_va_block_is_hmm(va_block)); + uvm_assert_mutex_locked(&va_block->lock); + + // Reset thrashing state for the region. + event_data.block_munmap.block = va_block; + event_data.block_munmap.region = region; + uvm_perf_event_notify(&va_space->perf_events, UVM_PERF_EVENT_BLOCK_MUNMAP, &event_data); + + // Release any remaining vidmem chunks in the given region. + for_each_gpu_id(gpu_id) { + uvm_va_block_gpu_state_t *gpu_state = uvm_va_block_gpu_state_get(va_block, gpu_id); + + if (!gpu_state) + continue; + + uvm_page_mask_region_clear(&gpu_state->evicted, region); + if (uvm_page_mask_empty(&gpu_state->evicted)) + uvm_processor_mask_clear(&va_block->evicted_gpus, gpu_id); + + if (gpu_state->chunks) { + block_gpu_release_region(va_block, gpu_id, gpu_state, NULL, region); + + // TODO: bug 3660922: Need to update the read duplicated pages mask + // when read duplication is supported for HMM. + } + else { + UVM_ASSERT(!uvm_processor_mask_test(&va_block->resident, gpu_id)); + } + } + + uvm_va_policy_clear(va_block, + uvm_va_block_region_start(va_block, region), + uvm_va_block_region_end(va_block, region)); +} + static NV_STATUS block_split_presplit_ptes_gpu(uvm_va_block_t *existing, uvm_va_block_t *new, uvm_gpu_t *gpu) { uvm_va_block_gpu_state_t *existing_gpu_state = uvm_va_block_gpu_state_get(existing, gpu->id); @@ -7713,15 +8412,16 @@ uvm_chunk_size_t chunk_size; } block_gpu_chunk_split_state_t; -static void block_gpu_chunk_get_split_state(block_gpu_chunk_split_state_t *state, +static void block_gpu_chunk_get_split_state(uvm_va_block_t *block, + block_gpu_chunk_split_state_t *state, NvU64 start, NvU64 end, uvm_page_index_t page_index, uvm_gpu_t *gpu) { NvU64 size = end - start + 1; - state->num_chunks = block_num_gpu_chunks_range(start, size, gpu); - state->chunk_index = uvm_va_block_gpu_chunk_index_range(start, size, gpu, page_index, &state->chunk_size); + state->num_chunks = block_num_gpu_chunks_range(block, start, size, gpu); + state->chunk_index = block_gpu_chunk_index_range(block, start, size, gpu, page_index, &state->chunk_size); } static void block_merge_chunk(uvm_va_block_t *block, uvm_gpu_t *gpu, uvm_gpu_chunk_t *chunk) @@ -7755,9 +8455,24 @@ NV_STATUS status; block_gpu_chunk_split_state_t existing_before_state, existing_after_state, new_state; - block_gpu_chunk_get_split_state(&existing_before_state, existing->start, existing->end, split_page_index, gpu); - block_gpu_chunk_get_split_state(&existing_after_state, existing->start, new->start - 1, split_page_index - 1, gpu); - block_gpu_chunk_get_split_state(&new_state, new->start, new->end, 0, gpu); + block_gpu_chunk_get_split_state(existing, + &existing_before_state, + existing->start, + existing->end, + split_page_index, + gpu); + block_gpu_chunk_get_split_state(existing, + &existing_after_state, + existing->start, + new->start - 1, + split_page_index - 1, + gpu); + block_gpu_chunk_get_split_state(new, + &new_state, + new->start, + new->end, + 0, + gpu); // Even though we're splitting existing, we could wind up requiring a larger // chunks array if we split a large chunk into many smaller ones. @@ -7837,33 +8552,89 @@ return status; } -static NV_STATUS block_split_cpu_chunk_to_size(uvm_va_block_t *block, - uvm_page_index_t page_index, - uvm_cpu_chunk_t *chunk, - uvm_chunk_size_t new_size) +static NV_STATUS block_split_cpu_chunk_to_64k(uvm_va_block_t *block) { - size_t num_new_chunks = uvm_cpu_chunk_get_size(chunk) / new_size; - uvm_cpu_chunk_t **new_chunks = NULL; + uvm_cpu_chunk_storage_mixed_t *mixed; + uvm_cpu_chunk_t *chunk = uvm_cpu_chunk_get_chunk_for_page(block, 0); + NV_STATUS status; + + UVM_ASSERT(uvm_cpu_chunk_get_size(chunk) == UVM_CHUNK_SIZE_2M); + UVM_ASSERT(uvm_cpu_storage_get_type(block) == UVM_CPU_CHUNK_STORAGE_CHUNK); + + mixed = uvm_kvmalloc_zero(sizeof(*mixed)); + if (!mixed) + return NV_ERR_NO_MEMORY; + + status = uvm_cpu_chunk_split(chunk, (uvm_cpu_chunk_t **)&mixed->slots); + if (status != NV_OK) { + uvm_kvfree(mixed); + return status; + } + + bitmap_fill(mixed->big_chunks, MAX_BIG_CPU_CHUNK_SLOTS_PER_UVM_VA_BLOCK); + block->cpu.chunks = (unsigned long)mixed | UVM_CPU_CHUNK_STORAGE_MIXED; + return status; +} + +static NV_STATUS block_split_cpu_chunk_to_4k(uvm_va_block_t *block, uvm_page_index_t page_index) +{ + uvm_cpu_chunk_storage_mixed_t *mixed; + uvm_cpu_chunk_t *chunk = uvm_cpu_chunk_get_chunk_for_page(block, page_index); + uvm_cpu_chunk_t **small_chunks; + size_t slot_index; + NV_STATUS status; + + UVM_ASSERT(chunk); + UVM_ASSERT(uvm_cpu_chunk_get_size(chunk) == UVM_CHUNK_SIZE_64K); + UVM_ASSERT(uvm_cpu_storage_get_type(block) == UVM_CPU_CHUNK_STORAGE_MIXED); + + mixed = uvm_cpu_storage_get_ptr(block); + slot_index = compute_slot_index(block, page_index); + small_chunks = uvm_kvmalloc_zero(sizeof(*small_chunks) * MAX_SMALL_CHUNKS_PER_BIG_SLOT); + if (!small_chunks) + return NV_ERR_NO_MEMORY; + + status = uvm_cpu_chunk_split(chunk, small_chunks); + if (status != NV_OK) { + uvm_kvfree(small_chunks); + return status; + } + + mixed->slots[slot_index] = small_chunks; + clear_bit(slot_index, mixed->big_chunks); + return status; +} + +static NV_STATUS block_split_cpu_chunk_one(uvm_va_block_t *block, uvm_page_index_t page_index) +{ + uvm_cpu_chunk_t *chunk = uvm_cpu_chunk_get_chunk_for_page(block, page_index); + uvm_chunk_size_t chunk_size = uvm_cpu_chunk_get_size(chunk); + uvm_chunk_size_t new_size; uvm_gpu_t *gpu; NvU64 gpu_mapping_addr; uvm_processor_mask_t gpu_split_mask; uvm_gpu_id_t id; NV_STATUS status; - size_t i; - UVM_ASSERT(IS_ALIGNED(uvm_cpu_chunk_get_size(chunk), new_size)); + if (chunk_size == UVM_CHUNK_SIZE_2M) + new_size = UVM_CHUNK_SIZE_64K; + else + new_size = UVM_CHUNK_SIZE_4K; + + UVM_ASSERT(IS_ALIGNED(chunk_size, new_size)); uvm_processor_mask_zero(&gpu_split_mask); for_each_gpu_id(id) { if (!uvm_va_block_gpu_state_get(block, id)) continue; + gpu = block_get_gpu(block, id); + // If the parent chunk has not been mapped, there is nothing to split. - gpu_mapping_addr = uvm_cpu_chunk_get_gpu_mapping_addr(block, page_index, chunk, id); + gpu_mapping_addr = uvm_cpu_chunk_get_gpu_phys_addr(chunk, gpu->parent); if (gpu_mapping_addr == 0) continue; - gpu = block_get_gpu(block, id); status = uvm_pmm_sysmem_mappings_split_gpu_mappings(&gpu->pmm_reverse_sysmem_mappings, gpu_mapping_addr, new_size); @@ -7873,39 +8644,91 @@ uvm_processor_mask_set(&gpu_split_mask, id); } - uvm_cpu_chunk_remove_from_block(block, chunk, page_index); - new_chunks = uvm_kvmalloc(num_new_chunks * sizeof(*new_chunks)); - if (new_chunks) - status = uvm_cpu_chunk_split(block, chunk, new_size, UVM_CPU_CHUNK_PAGE_INDEX(chunk, page_index), new_chunks); + if (new_size == UVM_CHUNK_SIZE_64K) + status = block_split_cpu_chunk_to_64k(block); else - status = NV_ERR_NO_MEMORY; + status = block_split_cpu_chunk_to_4k(block, page_index); if (status != NV_OK) { - uvm_cpu_chunk_insert_in_block(block, chunk, UVM_CPU_CHUNK_PAGE_INDEX(chunk, page_index)); - merge: - for_each_gpu_id_in_mask (id, &gpu_split_mask) { - gpu_mapping_addr = uvm_cpu_chunk_get_gpu_mapping_addr(block, page_index, chunk, id); + for_each_gpu_id_in_mask(id, &gpu_split_mask) { gpu = block_get_gpu(block, id); + gpu_mapping_addr = uvm_cpu_chunk_get_gpu_phys_addr(chunk, gpu->parent); uvm_pmm_sysmem_mappings_merge_gpu_mappings(&gpu->pmm_reverse_sysmem_mappings, gpu_mapping_addr, - uvm_cpu_chunk_get_size(chunk)); + chunk_size); } - } else { - for (i = 0; i < num_new_chunks; i++) { - status = uvm_cpu_chunk_insert_in_block(block, - new_chunks[i], - UVM_CPU_CHUNK_PAGE_INDEX(new_chunks[i], - (page_index + - (i * (new_size / PAGE_SIZE))))); - UVM_ASSERT(status == NV_OK); + } + + return status; +} + +static NV_STATUS block_prealloc_cpu_chunk_storage(uvm_va_block_t *existing, uvm_va_block_t *new) +{ + uvm_cpu_chunk_storage_mixed_t *existing_mixed; + uvm_cpu_chunk_storage_mixed_t *new_mixed = NULL; + size_t slot_offset; + size_t existing_slot; + NV_STATUS status = NV_OK; + + UVM_ASSERT(uvm_cpu_storage_get_type(existing) == UVM_CPU_CHUNK_STORAGE_MIXED); + existing_mixed = uvm_cpu_storage_get_ptr(existing); + + // Pre-allocate chunk storage for the new block. By definition, the new block + // will contain either 64K and/or 4K chunks. + // + // We do this here so there are no failures in block_split_cpu(). + new_mixed = uvm_kvmalloc_zero(sizeof(*new_mixed)); + if (!new_mixed) + return NV_ERR_NO_MEMORY; + + slot_offset = compute_slot_index(existing, uvm_va_block_cpu_page_index(existing, new->start)); + existing_slot = slot_offset; + for_each_clear_bit_from(existing_slot, existing_mixed->big_chunks, MAX_BIG_CPU_CHUNK_SLOTS_PER_UVM_VA_BLOCK) { + size_t new_slot = existing_slot - slot_offset; + + if (existing_mixed->slots[existing_slot]) { + uvm_cpu_chunk_t **small_chunks = uvm_kvmalloc_zero(sizeof(*small_chunks) * MAX_SMALL_CHUNKS_PER_BIG_SLOT); + + if (!small_chunks) { + status = NV_ERR_NO_MEMORY; + goto done; + } + + new_mixed->slots[new_slot] = small_chunks; } } - uvm_kvfree(new_chunks); + new->cpu.chunks = (unsigned long)new_mixed | UVM_CPU_CHUNK_STORAGE_MIXED; + UVM_ASSERT(status == NV_OK); + +done: + if (status != NV_OK) { + for (; existing_slot > slot_offset; existing_slot--) + uvm_kvfree(new_mixed->slots[existing_slot - slot_offset]); + + uvm_kvfree(new_mixed); + } + return status; } +static void block_free_cpu_chunk_storage(uvm_va_block_t *block) +{ + if (block->cpu.chunks) { + uvm_cpu_chunk_storage_mixed_t *mixed; + size_t slot_index; + + UVM_ASSERT(uvm_cpu_storage_get_type(block) == UVM_CPU_CHUNK_STORAGE_MIXED); + mixed = uvm_cpu_storage_get_ptr(block); + for (slot_index = 0; slot_index < MAX_BIG_CPU_CHUNK_SLOTS_PER_UVM_VA_BLOCK; slot_index++) + uvm_kvfree(mixed->slots[slot_index]); + + uvm_kvfree(mixed); + block->cpu.chunks = 0; + } +} + // Perform any CPU chunk splitting that may be required for this block split. // Just like block_presplit_gpu_chunks, no chunks are moved to the new block. static NV_STATUS block_presplit_cpu_chunks(uvm_va_block_t *existing, uvm_va_block_t *new) @@ -7917,16 +8740,15 @@ NV_STATUS status = NV_OK; UVM_ASSERT(!IS_ALIGNED(new->start, UVM_VA_BLOCK_SIZE)); + splitting_chunk = uvm_cpu_chunk_get_chunk_for_page(existing, page_index); // If the page covering the split point has not been populated, there is no // need to split. - if (!uvm_page_mask_test(&existing->cpu.allocated, page_index)) + if (!splitting_chunk) return NV_OK; - splitting_chunk = uvm_cpu_chunk_get_chunk_for_page(existing, page_index); - - // If the chunk spanning the split point is already at the correct size, - // there is nothing to do. + // If the split point is aligned on the chunk size, there is no need to + // split. if (IS_ALIGNED(new->start, uvm_cpu_chunk_get_size(splitting_chunk))) return NV_OK; @@ -7936,59 +8758,59 @@ split_sizes &= ~(IS_ALIGNED(new->start, UVM_CHUNK_SIZE_64K) ? UVM_CHUNK_SIZE_64K - 1 : 0); for_each_chunk_size_rev(subchunk_size, split_sizes) { - status = block_split_cpu_chunk_to_size(existing, page_index, splitting_chunk, subchunk_size); + status = block_split_cpu_chunk_one(existing, page_index); if (status != NV_OK) return status; - - splitting_chunk = uvm_cpu_chunk_get_chunk_for_page(existing, page_index); } - return NV_OK; + return block_prealloc_cpu_chunk_storage(existing, new); } -static NV_STATUS block_merge_cpu_chunks_to_size(uvm_va_block_t *block, - uvm_chunk_size_t size, - uvm_page_index_t page_index) +static void block_merge_cpu_chunks_to_64k(uvm_va_block_t *block, uvm_page_index_t page_index) { - uvm_cpu_chunk_t *chunk; - size_t num_merge_chunks; - uvm_chunk_size_t chunk_size; - uvm_cpu_chunk_t **merge_chunks; - uvm_gpu_id_t id; - size_t i; - NV_STATUS status; + uvm_cpu_chunk_storage_mixed_t *mixed = uvm_cpu_storage_get_ptr(block); + size_t slot_index = compute_slot_index(block, page_index); + uvm_cpu_chunk_t **small_chunks = mixed->slots[slot_index]; + uvm_cpu_chunk_t *merged_chunk; - chunk = uvm_cpu_chunk_get_chunk_for_page(block, page_index); - chunk_size = uvm_cpu_chunk_get_size(chunk); - num_merge_chunks = size / chunk_size; + UVM_ASSERT(uvm_cpu_storage_get_type(block) == UVM_CPU_CHUNK_STORAGE_MIXED); + UVM_ASSERT(small_chunks); + UVM_ASSERT(!test_bit(slot_index, mixed->big_chunks)); - // It's OK if we can't merge here. We know that the CPU chunk split - // operation completed successfully. Therefore, the CPU chunks are in a - // sane state. - merge_chunks = uvm_kvmalloc(num_merge_chunks * sizeof(*merge_chunks)); - if (!merge_chunks) - return NV_ERR_NO_MEMORY; + merged_chunk = uvm_cpu_chunk_merge(small_chunks); + mixed->slots[slot_index] = merged_chunk; + set_bit(slot_index, mixed->big_chunks); + uvm_kvfree(small_chunks); +} - for (i = 0; i < num_merge_chunks; i++) { - merge_chunks[i] = uvm_cpu_chunk_get_chunk_for_page(block, page_index + (i * (chunk_size / PAGE_SIZE))); - UVM_ASSERT(merge_chunks[i]); - UVM_ASSERT(uvm_cpu_chunk_get_size(merge_chunks[i]) == chunk_size); - uvm_cpu_chunk_remove_from_block(block, merge_chunks[i], page_index + (i * (chunk_size / PAGE_SIZE))); - } +static void block_merge_cpu_chunks_to_2m(uvm_va_block_t *block, uvm_page_index_t page_index) +{ + uvm_cpu_chunk_storage_mixed_t *mixed = uvm_cpu_storage_get_ptr(block); + uvm_cpu_chunk_t **big_chunks = (uvm_cpu_chunk_t **)&mixed->slots; + uvm_cpu_chunk_t *merged_chunk; - // Merge the CPU chunk. If a merge was not done, re-insert the original chunks. - status = uvm_cpu_chunk_merge(block, merge_chunks, num_merge_chunks, size, &chunk); - if (status == NV_WARN_NOTHING_TO_DO) { - for (i = 0; i < num_merge_chunks; i++) - uvm_cpu_chunk_insert_in_block(block, merge_chunks[i], page_index + (i * (chunk_size / PAGE_SIZE))); + UVM_ASSERT(uvm_cpu_storage_get_type(block) == UVM_CPU_CHUNK_STORAGE_MIXED); + UVM_ASSERT(bitmap_full(mixed->big_chunks, MAX_BIG_CPU_CHUNK_SLOTS_PER_UVM_VA_BLOCK)); - goto done; - } + merged_chunk = uvm_cpu_chunk_merge(big_chunks); + block->cpu.chunks = (unsigned long)merged_chunk | UVM_CPU_CHUNK_STORAGE_CHUNK; + uvm_kvfree(mixed); +} - UVM_ASSERT(status == NV_OK); +static void block_merge_cpu_chunks_one(uvm_va_block_t *block, uvm_page_index_t page_index) +{ + uvm_cpu_chunk_t *chunk = uvm_cpu_chunk_get_chunk_for_page(block, page_index); + uvm_gpu_id_t id; - status = uvm_cpu_chunk_insert_in_block(block, chunk, page_index); - UVM_ASSERT(status == NV_OK); + if (uvm_cpu_chunk_get_size(chunk) == UVM_CHUNK_SIZE_4K) { + block_merge_cpu_chunks_to_64k(block, page_index); + } + else { + UVM_ASSERT(uvm_cpu_chunk_get_size(chunk) == UVM_CHUNK_SIZE_64K); + block_merge_cpu_chunks_to_2m(block, page_index); + } + + chunk = uvm_cpu_chunk_get_chunk_for_page(block, page_index); for_each_gpu_id(id) { NvU64 gpu_mapping_addr; @@ -7997,17 +8819,15 @@ if (!uvm_va_block_gpu_state_get(block, id)) continue; - gpu_mapping_addr = uvm_cpu_chunk_get_gpu_mapping_addr(block, page_index, chunk, id); + gpu = block_get_gpu(block, id); + gpu_mapping_addr = uvm_cpu_chunk_get_gpu_phys_addr(chunk, gpu->parent); if (gpu_mapping_addr == 0) continue; - gpu = block_get_gpu(block, id); - uvm_pmm_sysmem_mappings_merge_gpu_mappings(&gpu->pmm_reverse_sysmem_mappings, gpu_mapping_addr, size); + uvm_pmm_sysmem_mappings_merge_gpu_mappings(&gpu->pmm_reverse_sysmem_mappings, + gpu_mapping_addr, + uvm_cpu_chunk_get_size(chunk)); } - -done: - uvm_kvfree(merge_chunks); - return status; } static void block_merge_cpu_chunks(uvm_va_block_t *existing, uvm_va_block_t *new) @@ -8019,9 +8839,8 @@ uvm_chunk_size_t chunk_size; uvm_chunk_size_t merge_size; size_t block_size = uvm_va_block_size(existing); - NV_STATUS status; - if (!chunk) + if (!chunk || uvm_cpu_chunk_is_physical(chunk)) return; chunk_size = uvm_cpu_chunk_get_size(chunk); @@ -8051,10 +8870,13 @@ if (!uvm_page_mask_region_full(&existing->cpu.allocated, chunk_region)) break; - status = block_merge_cpu_chunks_to_size(existing, merge_size, chunk_region.first); - if (status != NV_OK) + block_merge_cpu_chunks_one(existing, chunk_region.first); + chunk = uvm_cpu_chunk_get_chunk_for_page(existing, page_index); + if (uvm_cpu_chunk_is_physical(chunk)) break; } + + block_free_cpu_chunk_storage(new); } // Pre-allocate everything which doesn't require retry on both existing and new @@ -8228,6 +9050,7 @@ uvm_va_block_region_t block_region = uvm_va_block_region_from_block(existing); uvm_page_index_t split_page_index = uvm_va_block_cpu_page_index(existing, new->start); uvm_page_index_t page_index; + uvm_page_index_t next_page_index; uvm_cpu_chunk_t *chunk; uvm_va_range_t *existing_va_range = existing->va_range; @@ -8235,6 +9058,7 @@ UVM_ASSERT(existing->va_range->type == UVM_VA_RANGE_TYPE_MANAGED); UVM_ASSERT(existing->va_range->type == new->va_range->type); } + UVM_ASSERT(existing->start < new->start); UVM_ASSERT(existing->end == new->end); @@ -8248,22 +9072,23 @@ page_index = uvm_va_block_next_page_in_mask(block_region, &existing->cpu.allocated, split_page_index - 1); - while (page_index < block_region.outer) { + for_each_cpu_chunk_in_block_region_safe(chunk, + page_index, + next_page_index, + existing, + uvm_va_block_region(split_page_index, block_region.outer)) { uvm_page_index_t new_chunk_page_index; NV_STATUS status; - chunk = uvm_cpu_chunk_get_chunk_for_page(existing, page_index); - UVM_ASSERT(chunk); - - uvm_cpu_chunk_remove_from_block(existing, chunk, page_index); + uvm_cpu_chunk_remove_from_block(existing, page_index); // The chunk has to be adjusted for the new block before inserting it. new_chunk_page_index = page_index - split_page_index; + + // This should never fail because all necessary storage was allocated + // in block_presplit_cpu_chunks(). status = uvm_cpu_chunk_insert_in_block(new, chunk, new_chunk_page_index); UVM_ASSERT(status == NV_OK); - page_index = uvm_va_block_next_page_in_mask(block_region, - &existing->cpu.allocated, - page_index + uvm_cpu_chunk_num_pages(chunk) - 1); } new->cpu.ever_mapped = existing->cpu.ever_mapped; @@ -8287,9 +9112,24 @@ uvm_page_index_t split_page_index = uvm_va_block_cpu_page_index(existing, new->start); size_t i; - block_gpu_chunk_get_split_state(&existing_before_state, existing->start, existing->end, split_page_index, gpu); - block_gpu_chunk_get_split_state(&existing_after_state, existing->start, new->start - 1, split_page_index - 1, gpu); - block_gpu_chunk_get_split_state(&new_state, new->start, new->end, 0, gpu); + block_gpu_chunk_get_split_state(existing, + &existing_before_state, + existing->start, + existing->end, + split_page_index, + gpu); + block_gpu_chunk_get_split_state(existing, + &existing_after_state, + existing->start, + new->start - 1, + split_page_index - 1, + gpu); + block_gpu_chunk_get_split_state(new, + &new_state, + new->start, + new->end, + 0, + gpu); // General case (B is original_chunk): // split @@ -8416,14 +9256,9 @@ UVM_ASSERT(PAGE_ALIGNED(existing->start)); existing_pages = (new->start - existing->start) / PAGE_SIZE; - uvm_cpu_chunk_gpu_mapping_split(existing, new, gpu_id); - for_each_cpu_chunk_in_block(cpu_chunk, page_index, new) { uvm_pmm_sysmem_mappings_reparent_gpu_mapping(&gpu->pmm_reverse_sysmem_mappings, - uvm_cpu_chunk_get_gpu_mapping_addr(new, - page_index, - cpu_chunk, - gpu_id), + uvm_cpu_chunk_get_gpu_phys_addr(cpu_chunk, gpu->parent), new); } @@ -8594,8 +9429,7 @@ NV_STATUS status; uvm_perf_event_data_t event_data; - for_each_gpu_id(id) - UVM_ASSERT(block_check_chunks(existing_va_block, id)); + UVM_ASSERT(block_check_chunks(existing_va_block)); // As soon as we update existing's reverse mappings to point to the newly- // split block, the eviction path could try to operate on the new block. @@ -8672,17 +9506,14 @@ out: // Run checks on existing_va_block even on failure, since an error must // leave the block in a consistent state. - for_each_gpu_id(id) { - UVM_ASSERT(block_check_chunks(existing_va_block, id)); - if (status == NV_OK) - UVM_ASSERT(block_check_chunks(new_block, id)); - } - + UVM_ASSERT(block_check_chunks(existing_va_block)); UVM_ASSERT(block_check_mappings(existing_va_block)); - UVM_ASSERT(block_verify_cpu_chunks(existing_va_block)); if (status == NV_OK) { + UVM_ASSERT(block_check_chunks(new_block)); UVM_ASSERT(block_check_mappings(new_block)); - UVM_ASSERT(block_verify_cpu_chunks(new_block)); + } + else { + block_free_cpu_chunk_storage(new_block); } uvm_mutex_unlock_no_tracking(&new_block->lock); @@ -8718,7 +9549,7 @@ // could be changed in the future to optimize multiple faults/counters on // contiguous pages. static uvm_prot_t compute_new_permission(uvm_va_block_t *va_block, - uvm_va_block_context_t *va_block_context, + struct vm_area_struct *hmm_vma, uvm_page_index_t page_index, uvm_processor_id_t fault_processor_id, uvm_processor_id_t new_residency, @@ -8731,7 +9562,7 @@ // query_promote: upgrade access privileges to avoid future faults IF // they don't trigger further revocations. new_prot = uvm_fault_access_type_to_prot(access_type); - logical_prot = compute_logical_prot(va_block, va_block_context, page_index); + logical_prot = compute_logical_prot(va_block, hmm_vma, page_index); UVM_ASSERT(logical_prot >= new_prot); @@ -8740,16 +9571,17 @@ uvm_processor_mask_t processors_with_atomic_mapping; uvm_processor_mask_t revoke_processors; - uvm_va_block_page_authorized_processors(va_block, - page_index, - UVM_PROT_READ_WRITE_ATOMIC, - &processors_with_atomic_mapping); + block_page_authorized_processors(va_block, + page_index, + UVM_PROT_READ_WRITE_ATOMIC, + &processors_with_atomic_mapping); uvm_processor_mask_andnot(&revoke_processors, &processors_with_atomic_mapping, &va_space->has_native_atomics[uvm_id_value(new_residency)]); - // Only check if there are no faultable processors in the revoke processors mask + // Only check if there are no faultable processors in the revoke + // processors mask. uvm_processor_mask_and(&revoke_processors, &revoke_processors, &va_space->faultable_processors); if (uvm_processor_mask_empty(&revoke_processors)) @@ -8873,11 +9705,10 @@ uvm_va_space_t *va_space = uvm_va_block_get_va_space(va_block); const uvm_page_mask_t *final_page_mask = map_page_mask; uvm_tracker_t local_tracker = UVM_TRACKER_INIT(); - uvm_va_policy_t *policy = va_block_context->policy; + const uvm_va_policy_t *policy = uvm_va_policy_get_region(va_block, region); uvm_processor_id_t preferred_location; uvm_assert_mutex_locked(&va_block->lock); - UVM_ASSERT(uvm_va_block_check_policy_is_valid(va_block, policy, region)); // Read duplication takes precedence over SetAccessedBy. // @@ -8994,8 +9825,6 @@ return status == NV_OK ? tracker_status : status; } -// TODO: Bug 1750144: check logical permissions from HMM to know what's the -// maximum allowed. uvm_prot_t uvm_va_block_page_compute_highest_permission(uvm_va_block_t *va_block, uvm_processor_id_t processor_id, uvm_page_index_t page_index) @@ -9049,7 +9878,7 @@ if (!uvm_page_mask_test(&va_block->maybe_mapped_pages, page_index)) return UVM_PROT_READ_WRITE_ATOMIC; - uvm_va_block_page_authorized_processors(va_block, page_index, UVM_PROT_READ_WRITE_ATOMIC, &atomic_mappings); + block_page_authorized_processors(va_block, page_index, UVM_PROT_READ_WRITE_ATOMIC, &atomic_mappings); // Exclude processors with system-wide atomics disabled from atomic_mappings uvm_processor_mask_and(&atomic_mappings, @@ -9067,19 +9896,23 @@ return UVM_PROT_READ_ONLY; } - uvm_va_block_page_authorized_processors(va_block, page_index, UVM_PROT_READ_WRITE, &write_mappings); + block_page_authorized_processors(va_block, page_index, UVM_PROT_READ_WRITE, &write_mappings); // Exclude the processor for which the mapping protections are being computed uvm_processor_mask_clear(&write_mappings, processor_id); - // At this point, any processor with atomic mappings either has native atomics support to the - // processor with the resident copy or has disabled system-wide atomics. If the requesting - // processor has disabled system-wide atomics or has native atomics to that processor, we can - // map with ATOMIC privileges. Likewise, if there are no other processors with WRITE or ATOMIC - // mappings, we can map with ATOMIC privileges. + // At this point, any processor with atomic mappings either has native + // atomics support to the processor with the resident copy or has + // disabled system-wide atomics. If the requesting processor has + // disabled system-wide atomics or has native atomics to that processor, + // we can map with ATOMIC privileges. Likewise, if there are no other + // processors with WRITE or ATOMIC mappings, we can map with ATOMIC + // privileges. For HMM, don't allow GPU atomic access to remote mapped + // system memory even if there are no write mappings since CPU access + // can be upgraded without notification. if (!uvm_processor_mask_test(&va_space->system_wide_atomics_enabled_processors, processor_id) || uvm_processor_mask_test(&va_space->has_native_atomics[uvm_id_value(residency)], processor_id) || - uvm_processor_mask_empty(&write_mappings)) { + (uvm_processor_mask_empty(&write_mappings) && !uvm_va_block_is_hmm(va_block))) { return UVM_PROT_READ_WRITE_ATOMIC; } @@ -9101,8 +9934,6 @@ uvm_range_group_range_iter_t iter; uvm_prot_t prot_to_map; - UVM_ASSERT(uvm_va_block_check_policy_is_valid(va_block, va_block_context->policy, region)); - if (UVM_ID_IS_CPU(processor_id) && !uvm_va_block_is_hmm(va_block)) { if (!uvm_va_range_vma_check(va_range, va_block_context->mm)) return NV_OK; @@ -9164,7 +9995,7 @@ static bool can_read_duplicate(uvm_va_block_t *va_block, uvm_page_index_t page_index, - uvm_va_policy_t *policy, + const uvm_va_policy_t *policy, const uvm_perf_thrashing_hint_t *thrashing_hint) { if (uvm_va_policy_is_read_duplicate(policy, uvm_va_block_get_va_space(va_block))) @@ -9225,7 +10056,7 @@ uvm_page_index_t page_index, uvm_processor_id_t processor_id, NvU32 access_type_mask, - uvm_va_policy_t *policy, + const uvm_va_policy_t *policy, const uvm_perf_thrashing_hint_t *thrashing_hint, uvm_service_operation_t operation, bool *read_duplicate) @@ -9274,6 +10105,12 @@ return processor_id; } + // If the faulting processor is the CPU, HMM has to migrate the block to + // system memory. + // TODO: Bug 3900021: [UVM-HMM] investigate thrashing improvements. + if (UVM_ID_IS_CPU(processor_id) && uvm_va_block_is_hmm(va_block)) + return processor_id; + if (thrashing_hint->type == UVM_PERF_THRASHING_HINT_TYPE_PIN) { UVM_ASSERT(uvm_processor_mask_test(&va_space->accessible_from[uvm_id_value(thrashing_hint->pin.residency)], processor_id)); @@ -9325,6 +10162,34 @@ uvm_processor_mask_test(&va_space->accessible_from[uvm_id_value(preferred_location)], processor_id)) return preferred_location; + // Check if we should map the closest resident processor remotely on remote CPU fault + // + // When faulting on CPU, there's a linux process on behalf of it, which is associated + // with a unique VM pointed by current->mm. A block of memory residing on GPU is also + // associated with VM, pointed by va_block_context->mm. If they match, it's a regular + // (local) fault, and we may want to migrate a page from GPU to CPU. + // If it's a 'remote' fault, i.e. linux process differs from one associated with block + // VM, we might preserve residence. + // + // Establishing a remote fault without access counters means the memory could stay in + // the wrong spot for a long time, which is why we prefer to avoid creating remote + // mappings. However when NIC accesses a memory residing on GPU, it's worth to keep it + // in place for NIC accesses. + // + // The logic that's used to detect remote faulting also keeps memory in place for + // ptrace accesses. We would prefer to control those policies separately, but the + // NIC case takes priority. + // If the accessing processor is CPU, we're either handling a fault + // from other than owning process, or we're handling an MOMC + // notification. Only prevent migration for the former. + if (UVM_ID_IS_CPU(processor_id) && + operation != UVM_SERVICE_OPERATION_ACCESS_COUNTERS && + uvm_processor_mask_test(&va_space->accessible_from[uvm_id_value(closest_resident_processor)], processor_id) && + va_block_context->mm != current->mm) { + UVM_ASSERT(va_block_context->mm != NULL); + return closest_resident_processor; + } + // If the page is resident on a processor other than the preferred location, // or the faulting processor can't access the preferred location, we select // the faulting processor as the new residency. @@ -9336,19 +10201,16 @@ uvm_page_index_t page_index, uvm_processor_id_t processor_id, NvU32 access_type_mask, - uvm_va_policy_t *policy, + const uvm_va_policy_t *policy, const uvm_perf_thrashing_hint_t *thrashing_hint, uvm_service_operation_t operation, bool *read_duplicate) { uvm_processor_id_t id; - UVM_ASSERT(uvm_va_block_check_policy_is_valid(va_block, - va_block_context->policy, + UVM_ASSERT(uvm_hmm_check_context_vma_is_valid(va_block, + va_block_context->hmm.vma, uvm_va_block_region_for_page(page_index))); - UVM_ASSERT(uvm_hmm_va_block_context_vma_is_valid(va_block, - va_block_context, - uvm_va_block_region_for_page(page_index))); id = block_select_residency(va_block, va_block_context, @@ -9391,6 +10253,7 @@ // Update service_context->prefetch_hint, service_context->per_processor_masks, // and service_context->region. static void uvm_va_block_get_prefetch_hint(uvm_va_block_t *va_block, + const uvm_va_policy_t *policy, uvm_service_block_context_t *service_context) { uvm_processor_id_t new_residency; @@ -9401,20 +10264,19 @@ if (uvm_processor_mask_get_count(&service_context->resident_processors) == 1) { uvm_page_index_t page_index; uvm_page_mask_t *new_residency_mask; - uvm_va_policy_t *policy = service_context->block_context.policy; new_residency = uvm_processor_mask_find_first_id(&service_context->resident_processors); new_residency_mask = &service_context->per_processor_masks[uvm_id_value(new_residency)].new_residency; // Update prefetch tracking structure with the pages that will migrate // due to faults - uvm_perf_prefetch_get_hint(va_block, - &service_context->block_context, - new_residency, - new_residency_mask, - service_context->region, - &service_context->prefetch_bitmap_tree, - &service_context->prefetch_hint); + uvm_perf_prefetch_get_hint_va_block(va_block, + &service_context->block_context, + new_residency, + new_residency_mask, + service_context->region, + &service_context->prefetch_bitmap_tree, + &service_context->prefetch_hint); // Obtain the prefetch hint and give a fake fault access type to the // prefetched pages @@ -9445,221 +10307,89 @@ } } -NV_STATUS uvm_va_block_service_locked(uvm_processor_id_t processor_id, - uvm_va_block_t *va_block, - uvm_va_block_retry_t *block_retry, - uvm_service_block_context_t *service_context) +NV_STATUS uvm_va_block_service_copy(uvm_processor_id_t processor_id, + uvm_processor_id_t new_residency, + uvm_va_block_t *va_block, + uvm_va_block_retry_t *block_retry, + uvm_service_block_context_t *service_context) { - NV_STATUS status = NV_OK; - uvm_processor_id_t new_residency; - uvm_prot_t new_prot; uvm_va_space_t *va_space = uvm_va_block_get_va_space(va_block); - uvm_processor_mask_t processors_involved_in_cpu_migration; - - uvm_assert_mutex_locked(&va_block->lock); - UVM_ASSERT(uvm_va_block_check_policy_is_valid(va_block, - service_context->block_context.policy, - service_context->region)); - - // GPU fault servicing must be done under the VA space read lock. GPU fault - // servicing is required for RM to make forward progress, and we allow other - // threads to call into RM while holding the VA space lock in read mode. If - // we took the VA space lock in write mode on the GPU fault service path, - // we could deadlock because the thread in RM which holds the VA space lock - // for read wouldn't be able to complete until fault servicing completes. - if (service_context->operation != UVM_SERVICE_OPERATION_REPLAYABLE_FAULTS || UVM_ID_IS_CPU(processor_id)) - uvm_assert_rwsem_locked(&va_space->lock); - else - uvm_assert_rwsem_locked_read(&va_space->lock); - - uvm_va_block_get_prefetch_hint(va_block, service_context); - - for (new_prot = UVM_PROT_READ_ONLY; new_prot < UVM_PROT_MAX; ++new_prot) - service_context->mappings_by_prot[new_prot-1].count = 0; - - uvm_processor_mask_zero(&processors_involved_in_cpu_migration); - - // 1- Migrate pages and compute mapping protections - for_each_id_in_mask(new_residency, &service_context->resident_processors) { - uvm_processor_mask_t *all_involved_processors = &service_context->block_context.make_resident.all_involved_processors; - uvm_page_mask_t *new_residency_mask = &service_context->per_processor_masks[uvm_id_value(new_residency)].new_residency; - uvm_page_mask_t *did_migrate_mask = &service_context->block_context.make_resident.pages_changed_residency; - uvm_page_index_t page_index; - uvm_make_resident_cause_t cause; - - UVM_ASSERT_MSG(service_context->operation == UVM_SERVICE_OPERATION_REPLAYABLE_FAULTS || - service_context->operation == UVM_SERVICE_OPERATION_NON_REPLAYABLE_FAULTS || - service_context->operation == UVM_SERVICE_OPERATION_ACCESS_COUNTERS, - "Invalid operation value %u\n", service_context->operation); + uvm_processor_mask_t *all_involved_processors = + &service_context->block_context.make_resident.all_involved_processors; + uvm_page_mask_t *new_residency_mask = + &service_context->per_processor_masks[uvm_id_value(new_residency)].new_residency; + uvm_page_mask_t *did_migrate_mask = &service_context->block_context.make_resident.pages_changed_residency; + uvm_page_mask_t *caller_page_mask = &service_context->block_context.caller_page_mask; + uvm_make_resident_cause_t cause; + NV_STATUS status; - if (service_context->operation == UVM_SERVICE_OPERATION_REPLAYABLE_FAULTS) + // 1- Migrate pages + switch (service_context->operation) { + case UVM_SERVICE_OPERATION_REPLAYABLE_FAULTS: cause = UVM_MAKE_RESIDENT_CAUSE_REPLAYABLE_FAULT; - else if (service_context->operation == UVM_SERVICE_OPERATION_NON_REPLAYABLE_FAULTS) + break; + case UVM_SERVICE_OPERATION_NON_REPLAYABLE_FAULTS: cause = UVM_MAKE_RESIDENT_CAUSE_NON_REPLAYABLE_FAULT; - else + break; + case UVM_SERVICE_OPERATION_ACCESS_COUNTERS: cause = UVM_MAKE_RESIDENT_CAUSE_ACCESS_COUNTER; + break; + default: + UVM_ASSERT_MSG(false, "Invalid operation value %d\n", service_context->operation); + // Set cause to silence compiler warning that it may be unused. + cause = UVM_MAKE_RESIDENT_CAUSE_ACCESS_COUNTER; + break; + } - // 1.1- Migrate pages - - // Reset masks before all of the make_resident calls - uvm_page_mask_zero(did_migrate_mask); - uvm_processor_mask_zero(all_involved_processors); - - if (UVM_ID_IS_VALID(service_context->prefetch_hint.residency)) { - UVM_ASSERT(uvm_id_equal(service_context->prefetch_hint.residency, new_residency)); - - uvm_page_mask_or(new_residency_mask, new_residency_mask, &service_context->prefetch_hint.prefetch_pages_mask); - } - - if (service_context->read_duplicate_count == 0 || - uvm_page_mask_andnot(&service_context->block_context.caller_page_mask, - new_residency_mask, - &service_context->read_duplicate_mask)) { - status = uvm_va_block_make_resident(va_block, - block_retry, - &service_context->block_context, - new_residency, - service_context->region, - service_context->read_duplicate_count == 0? - new_residency_mask: - &service_context->block_context.caller_page_mask, - &service_context->prefetch_hint.prefetch_pages_mask, - cause); - if (status != NV_OK) - return status; - } - - if (service_context->read_duplicate_count != 0 && - uvm_page_mask_and(&service_context->block_context.caller_page_mask, - new_residency_mask, - &service_context->read_duplicate_mask)) { - status = uvm_va_block_make_resident_read_duplicate(va_block, - block_retry, - &service_context->block_context, - new_residency, - service_context->region, - &service_context->block_context.caller_page_mask, - &service_context->prefetch_hint.prefetch_pages_mask, - cause); - if (status != NV_OK) - return status; - } - - if (UVM_ID_IS_CPU(new_residency)) { - // Save all the processors involved in migrations to the CPU for - // an ECC check before establishing the CPU mappings. - uvm_processor_mask_copy(&processors_involved_in_cpu_migration, all_involved_processors); - } - - if (UVM_ID_IS_CPU(processor_id) && !uvm_processor_mask_empty(all_involved_processors)) - service_context->cpu_fault.did_migrate = true; - - uvm_page_mask_andnot(&service_context->did_not_migrate_mask, new_residency_mask, did_migrate_mask); - - // 1.2 - Compute mapping protections for the requesting processor on - // the new residency - for_each_va_block_page_in_region_mask(page_index, new_residency_mask, service_context->region) { - new_prot = compute_new_permission(va_block, - &service_context->block_context, - page_index, - processor_id, - new_residency, - service_context->access_type[page_index]); - - if (service_context->mappings_by_prot[new_prot-1].count++ == 0) - uvm_page_mask_zero(&service_context->mappings_by_prot[new_prot-1].page_mask); - - uvm_page_mask_set(&service_context->mappings_by_prot[new_prot-1].page_mask, page_index); - } - - // 1.3- Revoke permissions - // - // NOTE: uvm_va_block_make_resident destroys mappings to old locations. - // Thus, we need to revoke only if residency did not change and we - // are mapping higher than READ ONLY. - for (new_prot = UVM_PROT_READ_WRITE; new_prot <= UVM_PROT_READ_WRITE_ATOMIC; ++new_prot) { - bool pages_need_revocation; - uvm_processor_mask_t revoke_processors; - uvm_prot_t revoke_prot; - bool this_processor_has_enabled_atomics; - - if (service_context->mappings_by_prot[new_prot-1].count == 0) - continue; - - pages_need_revocation = uvm_page_mask_and(&service_context->revocation_mask, - &service_context->did_not_migrate_mask, - &service_context->mappings_by_prot[new_prot-1].page_mask); - if (!pages_need_revocation) - continue; - - uvm_processor_mask_and(&revoke_processors, &va_block->mapped, &va_space->faultable_processors); - - // Do not revoke the processor that took the fault - uvm_processor_mask_clear(&revoke_processors, processor_id); - - this_processor_has_enabled_atomics = uvm_processor_mask_test(&va_space->system_wide_atomics_enabled_processors, - processor_id); - - // Atomic operations on processors with system-wide atomics - // disabled or with native atomics access to new_residency - // behave like writes. - if (new_prot == UVM_PROT_READ_WRITE || - !this_processor_has_enabled_atomics || - uvm_processor_mask_test(&va_space->has_native_atomics[uvm_id_value(new_residency)], processor_id)) { - - // Exclude processors with native atomics on the resident copy - uvm_processor_mask_andnot(&revoke_processors, - &revoke_processors, - &va_space->has_native_atomics[uvm_id_value(new_residency)]); - - // Exclude processors with disabled system-wide atomics - uvm_processor_mask_and(&revoke_processors, - &revoke_processors, - &va_space->system_wide_atomics_enabled_processors); - } + // Reset masks before all of the make_resident calls + uvm_page_mask_zero(did_migrate_mask); + uvm_processor_mask_zero(all_involved_processors); - if (UVM_ID_IS_CPU(processor_id)) { - revoke_prot = UVM_PROT_READ_WRITE_ATOMIC; - } - else { - revoke_prot = (new_prot == UVM_PROT_READ_WRITE_ATOMIC)? UVM_PROT_READ_WRITE: - UVM_PROT_READ_WRITE_ATOMIC; - } - - // UVM-Lite processors must always have RWA mappings - if (uvm_processor_mask_andnot(&revoke_processors, &revoke_processors, block_get_uvm_lite_gpus(va_block))) { - // Access counters should never trigger revocations apart from - // read-duplication, which are performed in the calls to - // uvm_va_block_make_resident_read_duplicate, above. - if (service_context->operation == UVM_SERVICE_OPERATION_ACCESS_COUNTERS) { - UVM_ASSERT(check_access_counters_dont_revoke(va_block, - &service_context->block_context, - service_context->region, - &revoke_processors, - &service_context->revocation_mask, - revoke_prot)); - } + // Handle read duplication first so that the caller_page_mask will be free + // to use below and still valid in uvm_va_block_service_finish(). + // TODO: Bug 3660922: need to implement HMM read duplication support. + if (service_context->read_duplicate_count != 0 && + uvm_page_mask_and(caller_page_mask, + new_residency_mask, + &service_context->read_duplicate_mask)) { + status = uvm_va_block_make_resident_read_duplicate(va_block, + block_retry, + &service_context->block_context, + new_residency, + service_context->region, + caller_page_mask, + &service_context->prefetch_hint.prefetch_pages_mask, + cause); + if (status != NV_OK) + return status; + } - // Downgrade other processors' mappings - status = uvm_va_block_revoke_prot_mask(va_block, - &service_context->block_context, - &revoke_processors, - service_context->region, - &service_context->revocation_mask, - revoke_prot); - if (status != NV_OK) - return status; - } - } + if (service_context->read_duplicate_count == 0 || + uvm_page_mask_andnot(caller_page_mask, new_residency_mask, &service_context->read_duplicate_mask)) { + if (service_context->read_duplicate_count == 0) + uvm_page_mask_copy(caller_page_mask, new_residency_mask); + status = uvm_va_block_make_resident_copy(va_block, + block_retry, + &service_context->block_context, + new_residency, + service_context->region, + caller_page_mask, + &service_context->prefetch_hint.prefetch_pages_mask, + cause); + if (status != NV_OK) + return status; } + if (UVM_ID_IS_CPU(processor_id) && !uvm_processor_mask_empty(all_involved_processors)) + service_context->cpu_fault.did_migrate = true; + // 2- Check for ECC errors on all GPUs involved in the migration if CPU is // the destination. Migrations in response to CPU faults are special // because they're on the only path (apart from tools) where CUDA is not // involved and wouldn't have a chance to do its own ECC checking. if (service_context->operation == UVM_SERVICE_OPERATION_REPLAYABLE_FAULTS && - UVM_ID_IS_CPU(processor_id) && - !uvm_processor_mask_empty(&processors_involved_in_cpu_migration)) { + UVM_ID_IS_CPU(new_residency) && + !uvm_processor_mask_empty(all_involved_processors)) { uvm_gpu_t *gpu; // Before checking for ECC errors, make sure all of the GPU work @@ -9669,7 +10399,7 @@ if (status != NV_OK) return status; - for_each_va_space_gpu_in_mask(gpu, va_space, &processors_involved_in_cpu_migration) { + for_each_va_space_gpu_in_mask(gpu, va_space, all_involved_processors) { // We cannot call into RM here so use the no RM ECC check. status = uvm_gpu_check_ecc_error_no_rm(gpu); if (status == NV_WARN_MORE_PROCESSING_REQUIRED) { @@ -9691,16 +10421,152 @@ } } + return NV_OK; +} + +NV_STATUS uvm_va_block_service_finish(uvm_processor_id_t processor_id, + uvm_va_block_t *va_block, + uvm_service_block_context_t *service_context) +{ + uvm_processor_id_t new_residency = service_context->block_context.make_resident.dest_id; + uvm_page_mask_t *new_residency_mask = + &service_context->per_processor_masks[uvm_id_value(new_residency)].new_residency; + uvm_page_mask_t *did_migrate_mask = &service_context->block_context.make_resident.pages_changed_residency; + uvm_page_mask_t *caller_page_mask = &service_context->block_context.caller_page_mask; + uvm_va_space_t *va_space = uvm_va_block_get_va_space(va_block); + uvm_prot_t new_prot; + uvm_page_index_t page_index; + NV_STATUS status; + + // Update residency. + if (service_context->read_duplicate_count == 0 || !uvm_page_mask_empty(caller_page_mask)) + uvm_va_block_make_resident_finish(va_block, + &service_context->block_context, + service_context->region, + caller_page_mask); + + uvm_page_mask_andnot(&service_context->did_not_migrate_mask, new_residency_mask, did_migrate_mask); + + // The loops below depend on the enums having the following values in order + // to index into service_context->mappings_by_prot[]. + BUILD_BUG_ON(UVM_PROT_READ_ONLY != 1); + BUILD_BUG_ON(UVM_PROT_READ_WRITE != 2); + BUILD_BUG_ON(UVM_PROT_READ_WRITE_ATOMIC != 3); + BUILD_BUG_ON(UVM_PROT_MAX != 4); + + // 1- Compute mapping protections for the requesting processor on the new + // residency. + for (new_prot = UVM_PROT_READ_ONLY; new_prot < UVM_PROT_MAX; ++new_prot) + service_context->mappings_by_prot[new_prot - 1].count = 0; + + for_each_va_block_page_in_region_mask(page_index, new_residency_mask, service_context->region) { + new_prot = compute_new_permission(va_block, + service_context->block_context.hmm.vma, + page_index, + processor_id, + new_residency, + service_context->access_type[page_index]); + + if (service_context->mappings_by_prot[new_prot - 1].count++ == 0) + uvm_page_mask_zero(&service_context->mappings_by_prot[new_prot - 1].page_mask); + + uvm_page_mask_set(&service_context->mappings_by_prot[new_prot - 1].page_mask, page_index); + } + + // 2- Revoke permissions + // + // NOTE: uvm_va_block_make_resident_copy destroys mappings to old locations. + // Thus, we need to revoke only if residency did not change and we + // are mapping higher than READ ONLY. + for (new_prot = UVM_PROT_READ_WRITE; new_prot <= UVM_PROT_READ_WRITE_ATOMIC; ++new_prot) { + bool pages_need_revocation; + uvm_processor_mask_t revoke_processors; + uvm_prot_t revoke_prot; + bool this_processor_has_enabled_atomics; + + if (service_context->mappings_by_prot[new_prot - 1].count == 0) + continue; + + pages_need_revocation = uvm_page_mask_and(&service_context->revocation_mask, + &service_context->did_not_migrate_mask, + &service_context->mappings_by_prot[new_prot - 1].page_mask); + if (!pages_need_revocation) + continue; + + uvm_processor_mask_and(&revoke_processors, &va_block->mapped, &va_space->faultable_processors); + + // Do not revoke the processor that took the fault + uvm_processor_mask_clear(&revoke_processors, processor_id); + + this_processor_has_enabled_atomics = uvm_processor_mask_test(&va_space->system_wide_atomics_enabled_processors, + processor_id); + + // Atomic operations on processors with system-wide atomics + // disabled or with native atomics access to new_residency + // behave like writes. + if (new_prot == UVM_PROT_READ_WRITE || + !this_processor_has_enabled_atomics || + uvm_processor_mask_test(&va_space->has_native_atomics[uvm_id_value(new_residency)], processor_id)) { + + // Exclude processors with native atomics on the resident copy + uvm_processor_mask_andnot(&revoke_processors, + &revoke_processors, + &va_space->has_native_atomics[uvm_id_value(new_residency)]); + + // Exclude processors with disabled system-wide atomics + uvm_processor_mask_and(&revoke_processors, + &revoke_processors, + &va_space->system_wide_atomics_enabled_processors); + } + + if (UVM_ID_IS_CPU(processor_id)) { + revoke_prot = UVM_PROT_READ_WRITE_ATOMIC; + } + else { + revoke_prot = (new_prot == UVM_PROT_READ_WRITE_ATOMIC)? UVM_PROT_READ_WRITE: + UVM_PROT_READ_WRITE_ATOMIC; + } + + // UVM-Lite processors must always have RWA mappings + if (uvm_processor_mask_andnot(&revoke_processors, &revoke_processors, block_get_uvm_lite_gpus(va_block))) { + // Access counters should never trigger revocations apart from + // read-duplication, which are performed in the calls to + // uvm_va_block_make_resident_read_duplicate, above. + if (service_context->operation == UVM_SERVICE_OPERATION_ACCESS_COUNTERS) { + UVM_ASSERT(check_access_counters_dont_revoke(va_block, + &service_context->block_context, + service_context->region, + &revoke_processors, + &service_context->revocation_mask, + revoke_prot)); + } + + // Downgrade other processors' mappings + status = uvm_va_block_revoke_prot_mask(va_block, + &service_context->block_context, + &revoke_processors, + service_context->region, + &service_context->revocation_mask, + revoke_prot); + if (status != NV_OK) + return status; + } + } + // 3- Map requesting processor with the necessary privileges for (new_prot = UVM_PROT_READ_ONLY; new_prot <= UVM_PROT_READ_WRITE_ATOMIC; ++new_prot) { - const uvm_page_mask_t *map_prot_mask = &service_context->mappings_by_prot[new_prot-1].page_mask; + const uvm_page_mask_t *map_prot_mask = &service_context->mappings_by_prot[new_prot - 1].page_mask; - if (service_context->mappings_by_prot[new_prot-1].count == 0) + if (service_context->mappings_by_prot[new_prot - 1].count == 0) continue; // 3.1 - Unmap CPU pages - if (service_context->operation != UVM_SERVICE_OPERATION_ACCESS_COUNTERS && UVM_ID_IS_CPU(processor_id)) { - // The kernel can downgrade our CPU mappings at any time without + // HMM cpu mappings can be upgraded at any time without notification + // so no need to downgrade first. + if (service_context->operation != UVM_SERVICE_OPERATION_ACCESS_COUNTERS && + UVM_ID_IS_CPU(processor_id) && + !uvm_va_block_is_hmm(va_block)) { + // The kernel can downgrade managed CPU mappings at any time without // notifying us, which means our PTE state could be stale. We // handle this by unmapping the CPU PTE and re-mapping it again. // @@ -9763,92 +10629,134 @@ return status; } - // 4- If pages did migrate, map SetAccessedBy processors, except for UVM-Lite - for_each_id_in_mask(new_residency, &service_context->resident_processors) { - const uvm_page_mask_t *new_residency_mask; - new_residency_mask = &service_context->per_processor_masks[uvm_id_value(new_residency)].new_residency; + // 4- If pages did migrate, map SetAccessedBy processors, except for + // UVM-Lite + for (new_prot = UVM_PROT_READ_ONLY; new_prot <= UVM_PROT_READ_WRITE_ATOMIC; ++new_prot) { + bool pages_need_mapping; - for (new_prot = UVM_PROT_READ_ONLY; new_prot <= UVM_PROT_READ_WRITE_ATOMIC; ++new_prot) { - uvm_page_mask_t *map_prot_mask = &service_context->block_context.caller_page_mask; - bool pages_need_mapping; + if (service_context->mappings_by_prot[new_prot - 1].count == 0) + continue; - if (service_context->mappings_by_prot[new_prot-1].count == 0) - continue; + pages_need_mapping = uvm_page_mask_and(caller_page_mask, + new_residency_mask, + &service_context->mappings_by_prot[new_prot - 1].page_mask); + if (!pages_need_mapping) + continue; - pages_need_mapping = uvm_page_mask_and(map_prot_mask, - new_residency_mask, - &service_context->mappings_by_prot[new_prot-1].page_mask); + // Map pages that are thrashing + if (service_context->thrashing_pin_count > 0) { + uvm_page_index_t page_index; + + for_each_va_block_page_in_region_mask(page_index, + &service_context->thrashing_pin_mask, + service_context->region) { + uvm_processor_mask_t *map_thrashing_processors = NULL; + NvU64 page_addr = uvm_va_block_cpu_page_address(va_block, page_index); + + // Check protection type + if (!uvm_page_mask_test(caller_page_mask, page_index)) + continue; + + map_thrashing_processors = uvm_perf_thrashing_get_thrashing_processors(va_block, page_addr); + + status = uvm_va_block_add_mappings_after_migration(va_block, + &service_context->block_context, + new_residency, + processor_id, + uvm_va_block_region_for_page(page_index), + caller_page_mask, + new_prot, + map_thrashing_processors); + if (status != NV_OK) + return status; + } + + pages_need_mapping = uvm_page_mask_andnot(caller_page_mask, + caller_page_mask, + &service_context->thrashing_pin_mask); if (!pages_need_mapping) continue; + } - // Map pages that are thrashing - if (service_context->thrashing_pin_count > 0) { - uvm_page_index_t page_index; - - for_each_va_block_page_in_region_mask(page_index, - &service_context->thrashing_pin_mask, - service_context->region) { - uvm_processor_mask_t *map_thrashing_processors = NULL; - NvU64 page_addr = uvm_va_block_cpu_page_address(va_block, page_index); + // Map the rest of pages in a single shot + status = uvm_va_block_add_mappings_after_migration(va_block, + &service_context->block_context, + new_residency, + processor_id, + service_context->region, + caller_page_mask, + new_prot, + NULL); + if (status != NV_OK) + return status; + } - // Check protection type - if (!uvm_page_mask_test(map_prot_mask, page_index)) - continue; + return NV_OK; +} - map_thrashing_processors = uvm_perf_thrashing_get_thrashing_processors(va_block, page_addr); +NV_STATUS uvm_va_block_service_locked(uvm_processor_id_t processor_id, + uvm_va_block_t *va_block, + uvm_va_block_retry_t *block_retry, + uvm_service_block_context_t *service_context) +{ + uvm_va_space_t *va_space = uvm_va_block_get_va_space(va_block); + uvm_processor_id_t new_residency; + NV_STATUS status = NV_OK; - status = uvm_va_block_add_mappings_after_migration(va_block, - &service_context->block_context, - new_residency, - processor_id, - uvm_va_block_region_for_page(page_index), - map_prot_mask, - new_prot, - map_thrashing_processors); - if (status != NV_OK) - return status; - } + uvm_assert_mutex_locked(&va_block->lock); + UVM_ASSERT(uvm_hmm_check_context_vma_is_valid(va_block, + service_context->block_context.hmm.vma, + service_context->region)); - pages_need_mapping = uvm_page_mask_andnot(map_prot_mask, - map_prot_mask, - &service_context->thrashing_pin_mask); - if (!pages_need_mapping) - continue; - } + // GPU fault servicing must be done under the VA space read lock. GPU fault + // servicing is required for RM to make forward progress, and we allow other + // threads to call into RM while holding the VA space lock in read mode. If + // we took the VA space lock in write mode on the GPU fault service path, + // we could deadlock because the thread in RM which holds the VA space lock + // for read wouldn't be able to complete until fault servicing completes. + if (service_context->operation != UVM_SERVICE_OPERATION_REPLAYABLE_FAULTS || UVM_ID_IS_CPU(processor_id)) + uvm_assert_rwsem_locked(&va_space->lock); + else + uvm_assert_rwsem_locked_read(&va_space->lock); - // Map the the rest of pages in a single shot - status = uvm_va_block_add_mappings_after_migration(va_block, - &service_context->block_context, - new_residency, - processor_id, - service_context->region, - map_prot_mask, - new_prot, - NULL); + uvm_va_block_get_prefetch_hint(va_block, + uvm_va_policy_get_region(va_block, service_context->region), + service_context); + + for_each_id_in_mask(new_residency, &service_context->resident_processors) { + if (uvm_va_block_is_hmm(va_block)) { + status = uvm_hmm_va_block_service_locked(processor_id, new_residency, va_block, block_retry, service_context); if (status != NV_OK) - return status; + break; + + continue; } + + status = uvm_va_block_service_copy(processor_id, new_residency, va_block, block_retry, service_context); + if (status != NV_OK) + break; + + status = uvm_va_block_service_finish(processor_id, va_block, service_context); + if (status != NV_OK) + break; } - return NV_OK; + return status; } NV_STATUS uvm_va_block_check_logical_permissions(uvm_va_block_t *va_block, uvm_va_block_context_t *va_block_context, uvm_processor_id_t processor_id, uvm_page_index_t page_index, - uvm_fault_type_t access_type, + uvm_fault_access_type_t access_type, bool allow_migration) { uvm_va_range_t *va_range = va_block->va_range; uvm_prot_t access_prot = uvm_fault_access_type_to_prot(access_type); - UVM_ASSERT(uvm_va_block_check_policy_is_valid(va_block, - va_block_context->policy, + UVM_ASSERT(uvm_hmm_check_context_vma_is_valid(va_block, + va_block_context->hmm.vma, uvm_va_block_region_for_page(page_index))); - UVM_ASSERT(uvm_hmm_va_block_context_vma_is_valid(va_block, - va_block_context, - uvm_va_block_region_for_page(page_index))); // CPU permissions are checked later by block_map_cpu_page. // @@ -9865,8 +10773,8 @@ // vm_flags at any moment (for example on mprotect) and here we are not // guaranteed to have vma->vm_mm->mmap_lock. During tests we ensure that // this scenario does not happen. - if ((va_block_context->mm || uvm_enable_builtin_tests) && - (access_prot > compute_logical_prot(va_block, va_block_context, page_index))) + if (((va_block->hmm.va_space && va_block->hmm.va_space->va_space_mm.mm) || uvm_enable_builtin_tests) && + (access_prot > compute_logical_prot(va_block, va_block_context->hmm.vma, page_index))) return NV_ERR_INVALID_ACCESS_TYPE; } @@ -9899,10 +10807,15 @@ uvm_page_index_t page_index, uvm_fault_access_type_t fault_access_type) { - if (uvm_va_block_page_is_processor_authorized(va_block, - page_index, - UVM_ID_CPU, - uvm_fault_access_type_to_prot(fault_access_type))) { + // TODO: Bug 3900038: is skip_cpu_fault_with_valid_permissions() needed for + // HMM? + if (uvm_va_block_is_hmm(va_block)) + return false; + + if (block_page_is_processor_authorized(va_block, + page_index, + UVM_ID_CPU, + uvm_fault_access_type_to_prot(fault_access_type))) { NvU64 now = NV_GETTIME(); pid_t pid = current->pid; @@ -9941,29 +10854,28 @@ uvm_fault_access_type_t fault_access_type, uvm_service_block_context_t *service_context) { - uvm_va_range_t *va_range = va_block->va_range; uvm_va_space_t *va_space = uvm_va_block_get_va_space(va_block); NV_STATUS status = NV_OK; uvm_page_index_t page_index; uvm_perf_thrashing_hint_t thrashing_hint; uvm_processor_id_t new_residency; bool read_duplicate; + const uvm_va_policy_t *policy; uvm_assert_rwsem_locked(&va_space->lock); - UVM_ASSERT(va_range->type == UVM_VA_RANGE_TYPE_MANAGED); UVM_ASSERT(fault_addr >= va_block->start); UVM_ASSERT(fault_addr <= va_block->end); uvm_assert_mmap_lock_locked(service_context->block_context.mm); - service_context->block_context.policy = uvm_va_policy_get(va_block, fault_addr); + policy = uvm_va_policy_get(va_block, fault_addr); if (service_context->num_retries == 0) { // notify event to tools/performance heuristics uvm_perf_event_notify_cpu_fault(&va_space->perf_events, va_block, - service_context->block_context.policy->preferred_location, + policy->preferred_location, fault_addr, fault_access_type > UVM_FAULT_ACCESS_TYPE_READ, KSTK_EIP(current)); @@ -10008,7 +10920,7 @@ page_index, UVM_ID_CPU, uvm_fault_access_type_mask_bit(fault_access_type), - service_context->block_context.policy, + policy, &thrashing_hint, UVM_SERVICE_OPERATION_REPLAYABLE_FAULTS, &read_duplicate); @@ -10105,23 +11017,19 @@ return NV_OK; } -NV_STATUS uvm_va_block_find_create(uvm_va_space_t *va_space, - NvU64 addr, - uvm_va_block_context_t *va_block_context, - uvm_va_block_t **out_block) +NV_STATUS uvm_va_block_find_create_in_range(uvm_va_space_t *va_space, + uvm_va_range_t *va_range, + NvU64 addr, + uvm_va_block_t **out_block) { - uvm_va_range_t *va_range; size_t index; if (uvm_enable_builtin_tests && atomic_dec_if_positive(&va_space->test.va_block_allocation_fail_nth) == 0) return NV_ERR_NO_MEMORY; - va_range = uvm_va_range_find(va_space, addr); - if (!va_range) { - if (!va_block_context || !va_block_context->mm) - return NV_ERR_INVALID_ADDRESS; - return uvm_hmm_va_block_find_create(va_space, addr, va_block_context, out_block); - } + UVM_ASSERT(va_range); + UVM_ASSERT(addr >= va_range->node.start); + UVM_ASSERT(addr <= va_range->node.end); UVM_ASSERT(uvm_hmm_va_block_find(va_space, addr, out_block) == NV_ERR_INVALID_ADDRESS || uvm_hmm_va_block_find(va_space, addr, out_block) == NV_ERR_OBJECT_NOT_FOUND); @@ -10133,6 +11041,190 @@ return uvm_va_range_block_create(va_range, index, out_block); } +NV_STATUS uvm_va_block_find_create_managed(uvm_va_space_t *va_space, + NvU64 addr, + uvm_va_block_t **out_block) +{ + uvm_va_range_t *va_range = uvm_va_range_find(va_space, addr); + + if (va_range) + return uvm_va_block_find_create_in_range(va_space, va_range, addr, out_block); + else + return NV_ERR_INVALID_ADDRESS; +} + +NV_STATUS uvm_va_block_find_create(uvm_va_space_t *va_space, + NvU64 addr, + struct vm_area_struct **hmm_vma, + uvm_va_block_t **out_block) +{ + uvm_va_range_t *va_range = uvm_va_range_find(va_space, addr); + + if (hmm_vma) + *hmm_vma = NULL; + + if (va_range) + return uvm_va_block_find_create_in_range(va_space, va_range, addr, out_block); + else + return uvm_hmm_va_block_find_create(va_space, addr, hmm_vma, out_block); +} + +// Launch a synchronous, encrypted copy between GPU and CPU. +// +// The copy entails a GPU-side encryption (relying on the Copy Engine), and a +// CPU-side decryption step, such that the destination CPU buffer pointed by +// dst_plain will contain the unencrypted (plain text) contents. The destination +// buffer can be in protected or unprotected sysmem, while the source buffer +// must be in protected vidmem. +// +// The maximum copy size allowed is UVM_CONF_COMPUTING_DMA_BUFFER_SIZE. +// +// The input tracker, if not NULL, is internally acquired by the push +// responsible for the encrypted copy. +__attribute__ ((format(printf, 6, 7))) +static NV_STATUS encrypted_memcopy_gpu_to_cpu(uvm_gpu_t *gpu, + void *dst_plain, + uvm_gpu_address_t src_gpu_address, + size_t size, + uvm_tracker_t *tracker, + const char *format, + ...) +{ + NV_STATUS status; + UvmCslIv decrypt_iv; + uvm_push_t push; + uvm_conf_computing_dma_buffer_t *dma_buffer; + uvm_gpu_address_t dst_gpu_address, auth_tag_gpu_address; + void *src_cipher, *auth_tag; + va_list args; + + UVM_ASSERT(uvm_conf_computing_mode_enabled(gpu)); + UVM_ASSERT(size <= UVM_CONF_COMPUTING_DMA_BUFFER_SIZE); + + status = uvm_conf_computing_dma_buffer_alloc(&gpu->conf_computing.dma_buffer_pool, &dma_buffer, NULL); + if (status != NV_OK) + return status; + + va_start(args, format); + status = uvm_push_begin_acquire(gpu->channel_manager, UVM_CHANNEL_TYPE_GPU_TO_CPU, tracker, &push, format, args); + va_end(args); + + if (status != NV_OK) + goto out; + + uvm_conf_computing_log_gpu_encryption(push.channel, &decrypt_iv); + + dst_gpu_address = uvm_mem_gpu_address_virtual_kernel(dma_buffer->alloc, gpu); + auth_tag_gpu_address = uvm_mem_gpu_address_virtual_kernel(dma_buffer->auth_tag, gpu); + gpu->parent->ce_hal->encrypt(&push, dst_gpu_address, src_gpu_address, size, auth_tag_gpu_address); + + status = uvm_push_end_and_wait(&push); + if (status != NV_OK) + goto out; + + src_cipher = uvm_mem_get_cpu_addr_kernel(dma_buffer->alloc); + auth_tag = uvm_mem_get_cpu_addr_kernel(dma_buffer->auth_tag); + status = uvm_conf_computing_cpu_decrypt(push.channel, dst_plain, src_cipher, &decrypt_iv, size, auth_tag); + + out: + uvm_conf_computing_dma_buffer_free(&gpu->conf_computing.dma_buffer_pool, dma_buffer, NULL); + return status; +} + +// Launch a synchronous, encrypted copy between CPU and GPU. +// +// The source CPU buffer pointed by src_plain contains the unencrypted (plain +// text) contents; the function internally performs a CPU-side encryption step +// before launching the GPU-side CE decryption. The source buffer can be in +// protected or unprotected sysmem, while the destination buffer must be in +// protected vidmem. +// +// The maximum copy size allowed is UVM_CONF_COMPUTING_DMA_BUFFER_SIZE. +// +// The input tracker, if not NULL, is internally acquired by the push +// responsible for the encrypted copy. +__attribute__ ((format(printf, 6, 7))) +static NV_STATUS encrypted_memcopy_cpu_to_gpu(uvm_gpu_t *gpu, + uvm_gpu_address_t dst_gpu_address, + void *src_plain, + size_t size, + uvm_tracker_t *tracker, + const char *format, + ...) +{ + NV_STATUS status; + uvm_push_t push; + uvm_conf_computing_dma_buffer_t *dma_buffer; + uvm_gpu_address_t src_gpu_address, auth_tag_gpu_address; + void *dst_cipher, *auth_tag; + va_list args; + + UVM_ASSERT(uvm_conf_computing_mode_enabled(gpu)); + UVM_ASSERT(size <= UVM_CONF_COMPUTING_DMA_BUFFER_SIZE); + + status = uvm_conf_computing_dma_buffer_alloc(&gpu->conf_computing.dma_buffer_pool, &dma_buffer, NULL); + if (status != NV_OK) + return status; + + va_start(args, format); + status = uvm_push_begin_acquire(gpu->channel_manager, UVM_CHANNEL_TYPE_CPU_TO_GPU, tracker, &push, format, args); + va_end(args); + + if (status != NV_OK) + goto out; + + dst_cipher = uvm_mem_get_cpu_addr_kernel(dma_buffer->alloc); + auth_tag = uvm_mem_get_cpu_addr_kernel(dma_buffer->auth_tag); + uvm_conf_computing_cpu_encrypt(push.channel, dst_cipher, src_plain, NULL, size, auth_tag); + + src_gpu_address = uvm_mem_gpu_address_virtual_kernel(dma_buffer->alloc, gpu); + auth_tag_gpu_address = uvm_mem_gpu_address_virtual_kernel(dma_buffer->auth_tag, gpu); + gpu->parent->ce_hal->decrypt(&push, dst_gpu_address, src_gpu_address, size, auth_tag_gpu_address); + + status = uvm_push_end_and_wait(&push); + +out: + uvm_conf_computing_dma_buffer_free(&gpu->conf_computing.dma_buffer_pool, dma_buffer, NULL); + return status; +} + +static NV_STATUS va_block_write_cpu_to_gpu(uvm_va_block_t *va_block, + uvm_gpu_t *gpu, + uvm_gpu_address_t dst_gpu_address, + NvU64 dst, + uvm_mem_t *src_mem, + size_t size) +{ + NV_STATUS status; + uvm_push_t push; + uvm_gpu_address_t src_gpu_address; + + if (uvm_conf_computing_mode_enabled(gpu)) { + return encrypted_memcopy_cpu_to_gpu(gpu, + dst_gpu_address, + uvm_mem_get_cpu_addr_kernel(src_mem), + size, + &va_block->tracker, + "Encrypted write to [0x%llx, 0x%llx)", + dst, + dst + size); + } + + status = uvm_push_begin_acquire(gpu->channel_manager, + UVM_CHANNEL_TYPE_CPU_TO_GPU, + &va_block->tracker, + &push, + "Direct write to [0x%llx, 0x%llx)", + dst, + dst + size); + if (status != NV_OK) + return status; + + src_gpu_address = uvm_mem_gpu_address_virtual_kernel(src_mem, gpu); + gpu->parent->ce_hal->memcopy(&push, dst_gpu_address, src_gpu_address, size); + return uvm_push_end_and_wait(&push); +} + NV_STATUS uvm_va_block_write_from_cpu(uvm_va_block_t *va_block, uvm_va_block_context_t *block_context, NvU64 dst, @@ -10144,21 +11236,13 @@ NvU64 page_offset = dst & (PAGE_SIZE - 1); uvm_processor_id_t proc = uvm_va_block_page_get_closest_resident(va_block, page_index, UVM_ID_CPU); uvm_va_block_region_t region = uvm_va_block_region_for_page(page_index); - void *src = uvm_mem_get_cpu_addr_kernel(src_mem); - uvm_gpu_t *gpu; - uvm_gpu_address_t src_gpu_address; - uvm_gpu_address_t dst_gpu_address; - uvm_push_t push; uvm_assert_mutex_locked(&va_block->lock); - UVM_ASSERT_MSG(UVM_ALIGN_DOWN(dst, PAGE_SIZE) == UVM_ALIGN_DOWN(dst + size - 1, PAGE_SIZE), - "dst 0x%llx size 0x%zx\n", dst, size); + UVM_ASSERT_MSG(page_offset + size <= PAGE_SIZE, "Write spans multiple pages: dst 0x%llx, size 0x%zx\n", dst, size); if (UVM_ID_IS_INVALID(proc)) proc = UVM_ID_CPU; - block_context->policy = uvm_va_policy_get(va_block, dst); - // Use make_resident() in all cases to break read-duplication, but // block_retry can be NULL as if the page is not resident yet we will make // it resident on the CPU. @@ -10178,8 +11262,8 @@ if (UVM_ID_IS_CPU(proc)) { char *mapped_page; - uvm_cpu_chunk_t *chunk = uvm_cpu_chunk_get_chunk_for_page(va_block, page_index); - struct page *page = uvm_cpu_chunk_get_cpu_page(va_block, chunk, page_index); + struct page *page = uvm_cpu_chunk_get_cpu_page(va_block, page_index); + void *src = uvm_mem_get_cpu_addr_kernel(src_mem); status = uvm_tracker_wait(&va_block->tracker); if (status != NV_OK) @@ -10191,53 +11275,76 @@ return NV_OK; } + else { + uvm_gpu_t *dst_gpu; + uvm_gpu_address_t dst_gpu_address; - gpu = block_get_gpu(va_block, proc); + UVM_ASSERT(UVM_ID_IS_GPU(proc)); - dst_gpu_address = block_phys_page_copy_address(va_block, block_phys_page(proc, page_index), gpu); - dst_gpu_address.address += page_offset; + dst_gpu = block_get_gpu(va_block, proc); - src_gpu_address = uvm_mem_gpu_address_virtual_kernel(src_mem, gpu); + dst_gpu_address = block_phys_page_copy_address(va_block, block_phys_page(proc, page_index), dst_gpu); + dst_gpu_address.address += page_offset; + + return va_block_write_cpu_to_gpu(va_block, dst_gpu, dst_gpu_address, dst, src_mem, size); + } +} + +static NV_STATUS va_block_read_gpu_to_cpu(uvm_va_block_t *va_block, + uvm_mem_t *dst_mem, + uvm_gpu_t *gpu, + uvm_gpu_address_t src_gpu_address, + NvU64 src, + size_t size) +{ + NV_STATUS status; + uvm_push_t push; + uvm_gpu_address_t dst_gpu_address; + + if (uvm_conf_computing_mode_enabled(gpu)) { + return encrypted_memcopy_gpu_to_cpu(gpu, + uvm_mem_get_cpu_addr_kernel(dst_mem), + src_gpu_address, + size, + &va_block->tracker, + "Encrypted read from [0x%llx, 0x%llx)", + src, + src + size); + } status = uvm_push_begin_acquire(gpu->channel_manager, - UVM_CHANNEL_TYPE_CPU_TO_GPU, + UVM_CHANNEL_TYPE_GPU_TO_CPU, &va_block->tracker, &push, - "Direct write to [0x%llx, 0x%llx)", - dst, - dst + size); + "Direct read from [0x%llx, 0x%llx)", + src, + src + size); if (status != NV_OK) return status; + dst_gpu_address = uvm_mem_gpu_address_virtual_kernel(dst_mem, gpu); gpu->parent->ce_hal->memcopy(&push, dst_gpu_address, src_gpu_address, size); return uvm_push_end_and_wait(&push); } NV_STATUS uvm_va_block_read_to_cpu(uvm_va_block_t *va_block, uvm_mem_t *dst_mem, NvU64 src, size_t size) { - NV_STATUS status; uvm_page_index_t page_index = uvm_va_block_cpu_page_index(va_block, src); NvU64 page_offset = src & (PAGE_SIZE - 1); uvm_processor_id_t proc = uvm_va_block_page_get_closest_resident(va_block, page_index, UVM_ID_CPU); void *dst = uvm_mem_get_cpu_addr_kernel(dst_mem); - uvm_gpu_t *gpu; - uvm_gpu_address_t src_gpu_address; - uvm_gpu_address_t dst_gpu_address; - uvm_push_t push; uvm_assert_mutex_locked(&va_block->lock); - UVM_ASSERT_MSG(UVM_ALIGN_DOWN(src, PAGE_SIZE) == UVM_ALIGN_DOWN(src + size - 1, PAGE_SIZE), - "src 0x%llx size 0x%zx\n", src, size); + UVM_ASSERT_MSG(page_offset + size <= PAGE_SIZE, "Read spans multiple pages: src 0x%llx, size 0x%zx\n", src, size); if (UVM_ID_IS_INVALID(proc)) { memset(dst, 0, size); return NV_OK; } - - if (UVM_ID_IS_CPU(proc)) { + else if (UVM_ID_IS_CPU(proc)) { + NV_STATUS status; char *mapped_page; - uvm_cpu_chunk_t *chunk = uvm_cpu_chunk_get_chunk_for_page(va_block, page_index); - struct page *page = uvm_cpu_chunk_get_cpu_page(va_block, chunk, page_index); + struct page *page = uvm_cpu_chunk_get_cpu_page(va_block, page_index); status = uvm_tracker_wait(&va_block->tracker); if (status != NV_OK) @@ -10249,33 +11356,21 @@ return NV_OK; } + else { + uvm_gpu_address_t src_gpu_address; + uvm_gpu_t *gpu = block_get_gpu(va_block, proc); - gpu = block_get_gpu(va_block, proc); - - dst_gpu_address = uvm_mem_gpu_address_virtual_kernel(dst_mem, gpu); - - src_gpu_address = block_phys_page_copy_address(va_block, block_phys_page(proc, page_index), gpu); - src_gpu_address.address += page_offset; - - status = uvm_push_begin_acquire(gpu->channel_manager, - UVM_CHANNEL_TYPE_GPU_TO_CPU, - &va_block->tracker, - &push, - "Direct read from [0x%llx, 0x%llx)", - src, - src + size); - if (status != NV_OK) - return status; - - gpu->parent->ce_hal->memcopy(&push, dst_gpu_address, src_gpu_address, size); + src_gpu_address = block_phys_page_copy_address(va_block, block_phys_page(proc, page_index), gpu); + src_gpu_address.address += page_offset; - return uvm_push_end_and_wait(&push); + return va_block_read_gpu_to_cpu(va_block, dst_mem, gpu, src_gpu_address, src, size); + } } // Deferred work item reestablishing accessed by mappings after eviction. On // GPUs with access counters enabled, the evicted GPU will also get remote // mappings. -static void block_deferred_eviction_mappings(void *args) +static void block_add_eviction_mappings(void *args) { uvm_va_block_t *va_block = (uvm_va_block_t*)args; uvm_va_space_t *va_space; @@ -10309,20 +11404,20 @@ if (uvm_va_block_is_dead(va_block)) goto unlock; - if (!uvm_va_block_is_hmm(va_block)) { + if (uvm_va_block_is_hmm(va_block)) { + uvm_hmm_block_add_eviction_mappings(va_space, va_block, block_context); + } + else { uvm_va_range_t *va_range = va_block->va_range; NV_STATUS status = NV_OK; - block_context->policy = uvm_va_range_get_policy(va_range); for_each_id_in_mask(id, &uvm_va_range_get_policy(va_range)->accessed_by) { status = uvm_va_block_set_accessed_by(va_block, block_context, id); if (status != NV_OK) break; } - // On Volta+ GPUs, we can map evicted memory since we can pull it back - // thanks to the access counters notifications - if (status == NV_OK && va_space_map_remote_on_eviction(va_space)) { + if (status == NV_OK && uvm_va_space_map_remote_on_eviction(va_space)) { uvm_processor_mask_t map_processors; // Exclude the processors that have been already mapped due to @@ -10374,9 +11469,9 @@ uvm_va_block_release(va_block); } -static void block_deferred_eviction_mappings_entry(void *args) +static void block_add_eviction_mappings_entry(void *args) { - UVM_ENTRY_VOID(block_deferred_eviction_mappings(args)); + UVM_ENTRY_VOID(block_add_eviction_mappings(args)); } NV_STATUS uvm_va_block_evict_chunks(uvm_va_block_t *va_block, @@ -10395,6 +11490,7 @@ uvm_va_block_test_t *va_block_test = uvm_va_block_get_test(va_block); uvm_va_space_t *va_space = uvm_va_block_get_va_space_maybe_dead(va_block); struct mm_struct *mm; + bool accessed_by_set = false; uvm_assert_mutex_locked(&va_block->lock); @@ -10414,7 +11510,7 @@ // We cannot take this block's VA space or mmap_lock locks on the eviction // path, however, we retain mm in order to support accounting of CPU memory // allocations. If mappings need to be created, - // block_deferred_eviction_mappings() will be scheduled below. + // block_add_eviction_mappings() will be scheduled below. mm = uvm_va_space_mm_retain(va_space); block_context = uvm_va_block_context_alloc(mm); if (!block_context) { @@ -10440,6 +11536,12 @@ if (!uvm_gpu_chunk_same_root(gpu_state->chunks[i], root_chunk)) continue; + if (uvm_va_block_is_hmm(va_block)) { + status = uvm_hmm_va_block_evict_chunk_prep(va_block, block_context, gpu_state->chunks[i], chunk_region); + if (status != NV_OK) + break; + } + uvm_page_mask_region_fill(pages_to_evict, chunk_region); ++chunks_to_evict; } @@ -10449,20 +11551,31 @@ // Only move pages resident on the GPU uvm_page_mask_and(pages_to_evict, pages_to_evict, uvm_va_block_resident_mask_get(va_block, gpu->id)); + uvm_processor_mask_zero(&block_context->make_resident.all_involved_processors); - block_context->policy = uvm_va_range_get_policy(va_block->va_range); + if (uvm_va_block_is_hmm(va_block)) { + status = uvm_hmm_va_block_evict_chunks(va_block, + block_context, + pages_to_evict, + uvm_va_block_region_from_block(va_block), + &accessed_by_set); + } + else { + const uvm_va_policy_t *policy = uvm_va_range_get_policy(va_block->va_range); + accessed_by_set = uvm_processor_mask_get_count(&policy->accessed_by) > 0; - // TODO: Bug 1765193: make_resident() breaks read-duplication, but it's not - // necessary to do so for eviction. Add a version that unmaps only the - // processors that have mappings to the pages being evicted. - status = uvm_va_block_make_resident(va_block, - NULL, - block_context, - UVM_ID_CPU, - uvm_va_block_region_from_block(va_block), - pages_to_evict, - NULL, - UVM_MAKE_RESIDENT_CAUSE_EVICTION); + // TODO: Bug 1765193: make_resident() breaks read-duplication, but it's + // not necessary to do so for eviction. Add a version that unmaps only + // the processors that have mappings to the pages being evicted. + status = uvm_va_block_make_resident(va_block, + NULL, + block_context, + UVM_ID_CPU, + uvm_va_block_region_from_block(va_block), + pages_to_evict, + NULL, + UVM_MAKE_RESIDENT_CAUSE_EVICTION); + } if (status != NV_OK) goto out; @@ -10482,16 +11595,13 @@ // // If a processor gets removed from the mask then we might not notice and // schedule the work item anyway, but that's benign as - // block_deferred_eviction_mappings() re-examines the mask. + // block_add_eviction_mappings() re-examines the mask. // // Checking if access counters migrations are enabled on a VA space is racy // without holding the VA space lock. However, this is fine as - // block_deferred_eviction_mappings() reexamines the value with the VA space + // block_add_eviction_mappings() reexamines the value with the VA space // lock being held. - if (uvm_processor_mask_get_count(&block_context->policy->accessed_by) > 0 || - (gpu->parent->access_counters_supported && - va_space_map_remote_on_eviction(va_space) && - !uvm_va_block_is_hmm(va_block))) { + if (accessed_by_set || (gpu->parent->access_counters_supported && uvm_va_space_map_remote_on_eviction(va_space))) { // Always retain the VA block first so that it's safe for the deferred // callback to release it immediately after it runs. uvm_va_block_retain(va_block); @@ -10643,19 +11753,16 @@ struct mm_struct *mm; uvm_va_block_t *va_block; uvm_va_block_test_t *va_block_test; - uvm_va_block_context_t *block_context = NULL; NV_STATUS status = NV_OK; mm = uvm_va_space_mm_or_current_retain_lock(va_space); uvm_va_space_down_read(va_space); - block_context = uvm_va_block_context_alloc(mm); - if (!block_context) { - status = NV_ERR_NO_MEMORY; - goto out; - } + if (mm) + status = uvm_va_block_find_create(va_space, params->lookup_address, NULL, &va_block); + else + status = uvm_va_block_find_create_managed(va_space, params->lookup_address, &va_block); - status = uvm_va_block_find_create(va_space, params->lookup_address, block_context, &va_block); if (status != NV_OK) goto out; @@ -10670,8 +11777,15 @@ if (params->user_pages_allocation_retry_force_count) va_block_test->user_pages_allocation_retry_force_count = params->user_pages_allocation_retry_force_count; - if (params->cpu_chunk_allocation_size_mask) - va_block_test->cpu_chunk_allocation_size_mask = params->cpu_chunk_allocation_size_mask; + if (params->cpu_chunk_allocation_size_mask) { + if (params->cpu_chunk_allocation_size_mask & ~UVM_CPU_CHUNK_SIZES || + !(params->cpu_chunk_allocation_size_mask & PAGE_SIZE)) { + status = NV_ERR_INVALID_ARGUMENT; + goto block_unlock; + } + + va_block_test->cpu_chunk_allocation_size_mask = params->cpu_chunk_allocation_size_mask & UVM_CPU_CHUNK_SIZES; + } if (params->eviction_error) va_block_test->inject_eviction_error = params->eviction_error; @@ -10682,12 +11796,12 @@ if (params->populate_error) va_block_test->inject_populate_error = params->populate_error; +block_unlock: uvm_mutex_unlock(&va_block->lock); out: uvm_va_space_up_read(va_space); uvm_va_space_mm_or_current_release_unlock(va_space, mm); - uvm_va_block_context_free(block_context); return status; } @@ -10758,10 +11872,18 @@ goto out; } - status = uvm_va_block_find_create(va_space, params->va, block_context, &block); + if (mm) + status = uvm_va_block_find_create(va_space, params->va, &block_context->hmm.vma, &block); + else + status = uvm_va_block_find_create_managed(va_space, params->va, &block); + if (status != NV_OK) goto out; + // TODO: Bug 3912902: UvmTestChangePteMapping() doesn't work on CPU. + if (UVM_ID_IS_CPU(id) && uvm_va_block_is_hmm(block)) + goto out; + uvm_mutex_lock(&block->lock); region = uvm_va_block_region_from_start_size(block, params->va, PAGE_SIZE); @@ -10781,8 +11903,6 @@ goto out_block; } - block_context->policy = uvm_va_policy_get(block, params->va); - if (new_prot == UVM_PROT_NONE) { status = uvm_va_block_unmap(block, block_context, id, region, NULL, &block->tracker); } @@ -10791,7 +11911,7 @@ // Revoking CPU mappings performs a combination of unmap + map. The map // portion requires a valid mm. - if (UVM_ID_IS_CPU(id) && !uvm_va_block_is_hmm(block) && !uvm_va_range_vma_check(block->va_range, mm)) { + if (UVM_ID_IS_CPU(id) && !uvm_va_range_vma_check(block->va_range, mm)) { status = NV_ERR_INVALID_STATE; } else { @@ -10827,21 +11947,47 @@ { uvm_va_space_t *va_space = uvm_va_space_get(filp); uvm_va_block_t *va_block; + uvm_va_range_t *va_range; + struct mm_struct *mm; + size_t index; NV_STATUS status = NV_OK; BUILD_BUG_ON(UVM_TEST_VA_BLOCK_SIZE != UVM_VA_BLOCK_SIZE); + mm = uvm_va_space_mm_or_current_retain_lock(va_space); uvm_va_space_down_read(va_space); - status = uvm_va_block_find(va_space, params->lookup_address, &va_block); - if (status != NV_OK) - goto out; + va_range = uvm_va_range_find(va_space, params->lookup_address); + if (!va_range) { + status = uvm_hmm_va_block_find(va_space, params->lookup_address, &va_block); + if (status == NV_ERR_OBJECT_NOT_FOUND) { + status = uvm_hmm_va_block_range_bounds(va_space, + mm, + params->lookup_address, + ¶ms->va_block_start, + ¶ms->va_block_end, + NULL); + goto out; + } + else if (status != NV_OK) { + goto out; + } + } + else { + index = uvm_va_range_block_index(va_range, params->lookup_address); + va_block = uvm_va_range_block(va_range, index); + if (!va_block) { + status = NV_ERR_OBJECT_NOT_FOUND; + goto out; + } + } params->va_block_start = va_block->start; params->va_block_end = va_block->end; out: uvm_va_space_up_read(va_space); + uvm_va_space_mm_or_current_release_unlock(va_space, mm); return status; } @@ -10849,34 +11995,55 @@ { NV_STATUS status = NV_OK; uvm_va_space_t *va_space = uvm_va_space_get(filp); - uvm_va_range_t *va_range = NULL; + uvm_va_range_t *va_range; uvm_va_block_t *block = NULL; + struct mm_struct *mm; NvU32 count = 0; uvm_processor_mask_t resident_on_mask; uvm_processor_id_t id; uvm_page_index_t page_index; unsigned release_block_count = 0; NvU64 addr = UVM_ALIGN_DOWN(params->lookup_address, PAGE_SIZE); + size_t index; + mm = uvm_va_space_mm_or_current_retain_lock(va_space); uvm_va_space_down_read(va_space); + // Inline uvm_va_block_find() to get the va_range. va_range = uvm_va_range_find(va_space, addr); - if (!va_range || va_range->type != UVM_VA_RANGE_TYPE_MANAGED) { + if (!va_range) { + NvU64 start, end; + + status = uvm_hmm_va_block_find(va_space, addr, &block); + if (status != NV_OK) { + if (status != NV_ERR_OBJECT_NOT_FOUND) + goto out; + status = uvm_hmm_va_block_range_bounds(va_space, mm, addr, &start, &end, params); + goto out; + } + // Update current CPU mapping information. + status = uvm_hmm_va_block_update_residency_info(block, mm, addr, false); + if (status != NV_OK) { + block = NULL; + goto out; + } + } + else if (va_range->type != UVM_VA_RANGE_TYPE_MANAGED) { status = NV_ERR_INVALID_ADDRESS; goto out; } + else { + index = uvm_va_range_block_index(va_range, addr); + block = uvm_va_range_block(va_range, index); + if (!block) { + params->resident_on_count = 0; + params->populated_on_count = 0; + params->mapped_on_count = 0; - status = uvm_va_block_find(va_space, addr, &block); - if (status != NV_OK) { - UVM_ASSERT(status == NV_ERR_OBJECT_NOT_FOUND); - - params->resident_on_count = 0; - params->populated_on_count = 0; - params->mapped_on_count = 0; - - status = NV_OK; + status = NV_OK; - goto out; + goto out; + } } uvm_mutex_lock(&block->lock); @@ -10889,11 +12056,7 @@ uvm_va_space_processor_uuid(va_space, ¶ms->resident_on[count], id); params->resident_physical_size[count] = block_phys_page_size(block, block_page); if (UVM_ID_IS_CPU(id)) { - uvm_cpu_chunk_t *chunk = uvm_cpu_chunk_get_chunk_for_page(block, page_index); - - params->resident_physical_address[count] = page_to_phys(uvm_cpu_chunk_get_cpu_page(block, - chunk, - page_index)); + params->resident_physical_address[count] = page_to_phys(uvm_cpu_chunk_get_cpu_page(block, page_index)); } else { params->resident_physical_address[count] = @@ -10905,7 +12068,10 @@ count = 0; for_each_id_in_mask(id, &block->mapped) { + uvm_processor_id_t processor_to_map; + block_phys_page_t block_page; NvU32 page_size = uvm_va_block_page_size_processor(block, id, page_index); + if (page_size == 0) continue; @@ -10913,6 +12079,20 @@ params->mapping_type[count] = g_uvm_prot_to_test_pte_mapping[block_page_prot(block, id, page_index)]; UVM_ASSERT(params->mapping_type[count] != UVM_TEST_PTE_MAPPING_INVALID); + processor_to_map = block_get_processor_to_map(block, id, page_index); + block_page = block_phys_page(processor_to_map, page_index); + + if (!UVM_ID_IS_CPU(id)) { + uvm_gpu_phys_address_t gpu_phys_addr = block_phys_page_address(block, + block_page, + uvm_va_space_get_gpu(va_space, id)); + params->mapping_physical_address[count] = gpu_phys_addr.address; + } + else { + struct page *page = block_page_get(block, block_page); + + params->mapping_physical_address[count] = page_to_phys(page); + } params->page_size[count] = page_size; ++count; @@ -10937,10 +12117,7 @@ continue; num_pages = uvm_pmm_sysmem_mappings_dma_to_virt(&gpu->pmm_reverse_sysmem_mappings, - uvm_cpu_chunk_get_gpu_mapping_addr(block, - page_index, - chunk, - id), + uvm_cpu_chunk_get_gpu_phys_addr(chunk, gpu->parent), uvm_cpu_chunk_get_size(chunk), &sysmem_page, 1); @@ -11002,6 +12179,7 @@ uvm_va_block_release(block); } uvm_va_space_up_read(va_space); + uvm_va_space_mm_or_current_release_unlock(va_space, mm); return status; } diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/kernel-open/nvidia-uvm/uvm_va_block.h nvidia-open-gpu-kernel-modules-535.161.08/kernel-open/nvidia-uvm/uvm_va_block.h --- nvidia-open-gpu-kernel-modules-525.147.05/kernel-open/nvidia-uvm/uvm_va_block.h 2023-10-25 20:33:35.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/kernel-open/nvidia-uvm/uvm_va_block.h 2024-03-05 22:25:53.000000000 +0000 @@ -1,5 +1,5 @@ /******************************************************************************* - Copyright (c) 2015-2022 NVIDIA Corporation + Copyright (c) 2015-2023 NVIDIA Corporation Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation files (the "Software"), to @@ -43,6 +43,7 @@ #include "nv-kthread-q.h" #include +#include // VA blocks are the leaf nodes in the uvm_va_space tree for managed allocations // (VA ranges with type == UVM_VA_RANGE_TYPE_MANAGED): @@ -328,7 +329,7 @@ // allocations. See uvm_pmm_sysmem.h for more details on CPU chunks. // This member is meant to hold an opaque value indicating the CPU // chunk storage method. For more details on CPU chunk storage, - // see uvm_cpu_chunk_storage_type_t in uvm_pmm_sysmem.c. + // see uvm_cpu_chunk_storage_type_t in uvm_va_block.c. unsigned long chunks; // Per-page allocation bit vector. @@ -352,12 +353,18 @@ // UVM_PTE_BITS_CPU_WRITE is not set, the mapping is read-only. // Otherwise, the mapping is read-write. // - // Note that this is the maximum permissions a PTE could have, but not - // necessarily the actual current permissions of the CPU PTEs. The UVM - // driver will never change the PTEs without updating this state, but - // the kernel can downgrade our CPU mappings at any time without - // notifying the UVM driver (for example in response to user space - // calling madvise with MADV_DONTNEED). + // For managed allocations, this is the maximum permissions a PTE + // could have, but not necessarily the actual current permissions of the + // CPU PTEs. The UVM driver will never change the PTEs without updating + // this state, but the kernel can downgrade our CPU mappings at any time + // without notifying the UVM driver (for example in response to user + // space calling madvise with MADV_DONTNEED). + // + // For HMM allocations, this is the minimum permission the CPU has since + // Linux can upgrade a read-only PTE to read-write without notifying + // the UVM driver. This is why read duplication isn't currently + // supported. + // TODO: Bug 3660922: Need to handle read duplication at some point. uvm_page_mask_t pte_bits[UVM_PTE_BITS_CPU_MAX]; // Whether the CPU has ever mapped a page on this VA block. This is @@ -446,11 +453,23 @@ NvU16 fault_migrations_to_last_proc; } prefetch_info; -#if UVM_IS_CONFIG_HMM() struct { +#if UVM_IS_CONFIG_HMM() // The MMU notifier is registered per va_block. struct mmu_interval_notifier notifier; +#endif + + // This is used to serialize migrations between CPU and GPU while + // allowing the va_block lock to be dropped. + // This must be acquired before locking the va_block lock if the + // critical section can change the residency state. + // Do not access directly, use the uvm_hmm_migrate_*() routines. + uvm_mutex_t migrate_lock; + + // Sequence number to tell if any changes were made to the va_block + // while not holding the block lock and calling hmm_range_fault(). + unsigned long changed; // Parent VA space pointer. It is NULL for managed blocks or if // the HMM block is dead. This field can be read while holding the @@ -469,7 +488,6 @@ // Storage node for range tree of va_blocks. uvm_range_tree_node_t node; } hmm; -#endif }; // We define additional per-VA Block fields for testing. When @@ -522,7 +540,7 @@ }; // Tracking needed for supporting allocation-retry of user GPU memory -typedef struct +struct uvm_va_block_retry_struct { // A tracker used for all allocations from PMM. uvm_tracker_t tracker; @@ -537,7 +555,7 @@ // can contain chunks from multiple GPUs. All the used chunks are unpinned // when the operation is finished with uvm_va_block_retry_deinit(). struct list_head used_chunks; -} uvm_va_block_retry_t; +}; // Module load/exit NV_STATUS uvm_va_block_init(void); @@ -635,6 +653,12 @@ // is held in write mode. uvm_va_space_t *uvm_va_block_get_va_space(uvm_va_block_t *va_block); +// Return true if the VA space has access counter migrations enabled and should +// remote map pages evicted to system memory. This is OK since access counters +// can pull the data back to vidmem if sufficient accesses trigger a migration. +// The caller must ensure that the VA space cannot go away. +bool uvm_va_space_map_remote_on_eviction(uvm_va_space_t *va_space); + // Dynamic cache-based allocation for uvm_va_block_context_t. // // See uvm_va_block_context_init() for a description of the mm parameter. @@ -654,18 +678,8 @@ memset(va_block_context, 0xff, sizeof(*va_block_context)); va_block_context->mm = mm; -#if UVM_IS_CONFIG_HMM() - va_block_context->hmm.vma = NULL; -#endif } -// Check that a single policy covers the given region for the given va_block. -// This always returns true and is intended to only be used with UVM_ASSERT(). -// Locking: the va_block lock must be held. -bool uvm_va_block_check_policy_is_valid(uvm_va_block_t *va_block, - uvm_va_policy_t *policy, - uvm_va_block_region_t region); - // TODO: Bug 1766480: Using only page masks instead of a combination of regions // and page masks could simplify the below APIs and their implementations // at the cost of having to scan the whole mask for small regions. @@ -697,7 +711,7 @@ // // Allocation-retry: this operation may need to perform eviction to be able to // allocate GPU memory successfully and if that happens, -// NV_WARN_MORE_PROCESSING_REQUIRED will be returned. That also means that the +// NV_ERR_MORE_PROCESSING_REQUIRED will be returned. That also means that the // block's lock has been unlocked and relocked as part of the call and that the // whole sequence of operations performed under the block's lock needs to be // attempted again. To facilitate that, the caller needs to provide the same @@ -707,22 +721,25 @@ // caller. // // If dest_id is the CPU then va_block_retry can be NULL and allocation-retry of -// user memory is guaranteed not to happen. Allocation-retry of page tables can -// still occur though. +// user memory is guaranteed not to happen. Allocation-retry of GPU page tables +// can still occur though. // -// va_block_context must not be NULL. This function will set a bit in -// va_block_context->make_resident.pages_changed_residency for each page that -// changed residency (due to a migration or first population) as a result of the -// operation. This function only sets bits in that mask. It is the caller's -// responsiblity to zero the mask or not first. -// -// va_block_context->policy must also be set by the caller for the given region. -// See the comments for uvm_va_block_check_policy_is_valid(). +// va_block_context must not be NULL and policy for the region must +// match. This function will set a bit in +// va_block_context->make_resident.pages_changed_residency for each +// page that changed residency (due to a migration or first +// population) as a result of the operation and +// va_block_context->make_resident.all_involved_processors for each +// processor involved in the copy. This function only sets bits in +// those masks. It is the caller's responsiblity to zero the masks or +// not first. // // Notably any status other than NV_OK indicates that the block's lock might // have been unlocked and relocked. // // LOCKING: The caller must hold the va_block lock. +// If va_block_context->mm != NULL, va_block_context->mm->mmap_lock must be +// held in at least read mode. NV_STATUS uvm_va_block_make_resident(uvm_va_block_t *va_block, uvm_va_block_retry_t *va_block_retry, uvm_va_block_context_t *va_block_context, @@ -743,8 +760,6 @@ // are broken // - Only managed va_blocks are supported. // TODO: Bug 3660922: need to implement HMM read duplication support. -// - LOCKING: If va_block_context->mm != NULL, va_block_context->mm->mmap_lock -// must be held in at least read mode. NV_STATUS uvm_va_block_make_resident_read_duplicate(uvm_va_block_t *va_block, uvm_va_block_retry_t *va_block_retry, uvm_va_block_context_t *va_block_context, @@ -756,31 +771,35 @@ // Similar to uvm_va_block_make_resident() (read documentation there). The // difference is that source pages are only copied to the destination and the -// residency is not updated until uvm_va_block_make_resident_post() is called. -// Otherwise, the combination of uvm_va_block_make_resident_pre() and -// uvm_va_block_make_resident_post() should be the same as just calling -// uvm_va_block_make_resident(). +// residency is not updated until uvm_va_block_make_resident_finish() is called. +// Otherwise, the combination of uvm_va_block_make_resident_copy() and +// uvm_va_block_make_resident_finish() is the same as just calling +// uvm_va_block_make_resident(). Note, however, that the va_block lock must be +// held across the two calls for the operation to be complete. The va_block +// lock can be dropped after calling uvm_va_block_make_resident_copy() but +// uvm_va_block_make_resident_copy() must be called again after relocking the +// va_block lock and before calling uvm_va_block_make_resident_finish(). // This split is needed when using migrate_vma_setup() and migrate_vma_pages() // so that when migrate_vma_pages() indicates a page is not migrating, the // va_block state is not updated. // LOCKING: The caller must hold the va_block lock. -NV_STATUS uvm_va_block_make_resident_pre(uvm_va_block_t *va_block, - uvm_va_block_retry_t *va_block_retry, - uvm_va_block_context_t *va_block_context, - uvm_processor_id_t dest_id, - uvm_va_block_region_t region, - const uvm_page_mask_t *page_mask, - const uvm_page_mask_t *prefetch_page_mask, - uvm_make_resident_cause_t cause); +NV_STATUS uvm_va_block_make_resident_copy(uvm_va_block_t *va_block, + uvm_va_block_retry_t *va_block_retry, + uvm_va_block_context_t *va_block_context, + uvm_processor_id_t dest_id, + uvm_va_block_region_t region, + const uvm_page_mask_t *page_mask, + const uvm_page_mask_t *prefetch_page_mask, + uvm_make_resident_cause_t cause); // The page_mask must be the same or a subset of the page_mask passed to -// uvm_va_block_make_resident_pre(). This step updates the residency and breaks +// uvm_va_block_make_resident_copy(). This step updates the residency and breaks // read duplication. // LOCKING: The caller must hold the va_block lock. -void uvm_va_block_make_resident_post(uvm_va_block_t *va_block, - uvm_va_block_context_t *va_block_context, - uvm_va_block_region_t region, - const uvm_page_mask_t *page_mask); +void uvm_va_block_make_resident_finish(uvm_va_block_t *va_block, + uvm_va_block_context_t *va_block_context, + uvm_va_block_region_t region, + const uvm_page_mask_t *page_mask); // Creates or upgrades a mapping from the input processor to the given virtual // address region. Pages which already have new_prot permissions or higher are @@ -810,7 +829,7 @@ // pages because the earlier operation can cause a PTE split or merge which is // assumed by the later operation. // -// va_block_context must not be NULL and va_block_context->policy must be valid. +// va_block_context must not be NULL and policy for the region must match. // See the comments for uvm_va_block_check_policy_is_valid(). // // If allocation-retry was required as part of the operation and was successful, @@ -867,7 +886,7 @@ // pages because the earlier operation can cause a PTE split or merge which is // assumed by the later operation. // -// va_block_context must not be NULL. The va_block_context->policy is unused. +// va_block_context must not be NULL. // // If allocation-retry was required as part of the operation and was successful, // NV_ERR_MORE_PROCESSING_REQUIRED is returned. In this case, the entries in the @@ -900,18 +919,19 @@ // - Unmap the preferred location's processor from any pages in this region // which are not resident on the preferred location. // -// va_block_context must not be NULL and va_block_context->policy must be valid. +// va_block_context must not be NULL and policy for the region must match. // See the comments for uvm_va_block_check_policy_is_valid(). // // LOCKING: The caller must hold the VA block lock. NV_STATUS uvm_va_block_set_preferred_location_locked(uvm_va_block_t *va_block, - uvm_va_block_context_t *va_block_context); + uvm_va_block_context_t *va_block_context, + uvm_va_block_region_t region); // Maps the given processor to all resident pages in this block, as allowed by // location and policy. Waits for the operation to complete before returning. // This function should only be called with managed va_blocks. // -// va_block_context must not be NULL and va_block_context->policy must be valid. +// va_block_context must not be NULL and policy for the region must match. // See the comments for uvm_va_block_check_policy_is_valid(). // // LOCKING: This takes and releases the VA block lock. If va_block_context->mm @@ -921,10 +941,26 @@ uvm_va_block_context_t *va_block_context, uvm_processor_id_t processor_id); +// Maps given processor to all resident pages in this block and region, as +// allowed by location and policy. The caller is responsible for waiting for +// the tracker after all mappings have been started. +// This function can be called with HMM and managed va_blocks. +// +// va_block_context must not be NULL and policy for the region must match. +// See the comments for uvm_va_block_check_policy_is_valid(). +// +// LOCKING: The caller must hold the va_block lock and +// va_block_context->mm->mmap_lock must be held in at least read mode. +NV_STATUS uvm_va_block_set_accessed_by_locked(uvm_va_block_t *va_block, + uvm_va_block_context_t *va_block_context, + uvm_processor_id_t processor_id, + uvm_va_block_region_t region, + uvm_tracker_t *out_tracker); + // Breaks SetAccessedBy and remote mappings // This function should only be called with managed va_blocks. // -// va_block_context must not be NULL and va_block_context->policy must be valid. +// va_block_context must not be NULL and policy for the region must match. // See the comments for uvm_va_block_check_policy_is_valid(). // // LOCKING: This takes and releases the VA block lock. If va_block_context->mm @@ -936,7 +972,7 @@ // Restores SetAccessedBy mappings // This function should only be called with managed va_blocks. // -// va_block_context must not be NULL and va_block_context->policy must be valid. +// va_block_context must not be NULL and policy for the region must match. // See the comments for uvm_va_block_check_policy_is_valid(). // // LOCKING: This takes and releases the VA block lock. If va_block_context->mm @@ -956,16 +992,15 @@ // NV_ERR_INVALID_OPERATION The access would violate the policies specified // by UvmPreventMigrationRangeGroups. // -// va_block_context must not be NULL, va_block_context->policy must be valid, -// and if the va_block is a HMM block, va_block_context->hmm.vma must be valid -// which also means the va_block_context->mm is not NULL, retained, and locked -// for at least read. +// va_block_context must not be NULL, policy must match, and if the va_block is +// a HMM block, va_block_context->hmm.vma must be valid which also means the +// va_block_context->mm is not NULL, retained, and locked for at least read. // Locking: the va_block lock must be held. NV_STATUS uvm_va_block_check_logical_permissions(uvm_va_block_t *va_block, uvm_va_block_context_t *va_block_context, uvm_processor_id_t processor_id, uvm_page_index_t page_index, - uvm_fault_type_t access_type, + uvm_fault_access_type_t access_type, bool allow_migration); // API for access privilege revocation @@ -995,7 +1030,7 @@ // different pages because the earlier operation can cause a PTE split or merge // which is assumed by the later operation. // -// va_block_context must not be NULL. The va_block_context->policy is unused. +// va_block_context must not be NULL. // // If allocation-retry was required as part of the operation and was successful, // NV_ERR_MORE_PROCESSING_REQUIRED is returned. In this case, the entries in the @@ -1035,7 +1070,7 @@ // processor_id, which triggered the migration and should have already been // mapped). // -// va_block_context must not be NULL and va_block_context->policy must be valid. +// va_block_context must not be NULL and policy for the region must match. // See the comments for uvm_va_block_check_policy_is_valid(). // // This function acquires/waits for the va_block tracker and updates that @@ -1066,7 +1101,7 @@ // Note that this can return NV_ERR_MORE_PROCESSING_REQUIRED just like // uvm_va_block_map() indicating that the operation needs to be retried. // -// va_block_context must not be NULL and va_block_context->policy must be valid. +// va_block_context must not be NULL and policy must for the region must match. // See the comments for uvm_va_block_check_policy_is_valid(). // // LOCKING: The caller must hold the va block lock. If va_block_context->mm != @@ -1088,7 +1123,7 @@ // If mm != NULL, that mm is used for any CPU mappings which may be created as // a result of this call. See uvm_va_block_context_t::mm for details. // -// va_block_context must not be NULL. The va_block_context->policy is unused. +// va_block_context must not be NULL. // // LOCKING: The caller must hold the va_block lock. If block_context->mm is not // NULL, the caller must hold mm->mmap_lock in at least read mode. @@ -1124,6 +1159,11 @@ // must hold mm->mmap_lock in at least read mode. void uvm_va_block_unregister_gpu(uvm_va_block_t *va_block, uvm_gpu_t *gpu, struct mm_struct *mm); +// Same as uvm_va_block_unregister_gpu() but the VA block lock must be held. +// Note that this handles allocation-retry internally and hence might unlock +// and relock block's lock. +void uvm_va_block_unregister_gpu_locked(uvm_va_block_t *va_block, uvm_gpu_t *gpu, struct mm_struct *mm); + // Unmaps all memory associated with the block and drops the ref count of the // block. This allows the caller to free resources associated with this block // regardless of the block's current ref count. Most importantly it allows the @@ -1174,7 +1214,6 @@ // - va_space lock must be held in at least read mode // // service_context->block_context.mm is ignored and vma->vm_mm is used instead. -// service_context->block_context.policy is set by this function. // // Returns NV_ERR_INVALID_ACCESS_TYPE if a CPU mapping to fault_addr cannot be // accessed, for example because it's within a range group which is non- @@ -1186,9 +1225,13 @@ // Performs any operations necessary to establish a coherent mapping // (migrations, cache invalidates, etc.) in response to the given service block -// context +// context. // -// service_context->block_context.policy is set by this function. +// service_context must not be NULL and policy for service_context->region must +// match. See the comments for uvm_va_block_check_policy_is_valid(). If +// va_block is a HMM block, va_block_context->hmm.vma must be valid. See the +// comments for uvm_hmm_check_context_vma_is_valid() in uvm_hmm.h. +// service_context->prefetch_hint is set by this function. // // Locking: // - service_context->block_context.mm->mmap_lock must be held in at least @@ -1197,8 +1240,8 @@ // - va_block lock must be held // // If allocation-retry was required as part of the operation and was successful, -// NV_ERR_MORE_PROCESSING_REQUIRED is returned. In this case, the block's lock was -// unlocked and relocked. +// NV_ERR_MORE_PROCESSING_REQUIRED is returned. In this case, the block's lock +// was unlocked and relocked. // // NV_WARN_MORE_PROCESSING_REQUIRED indicates that thrashing has been detected // and the performance heuristics logic decided to throttle execution. @@ -1209,6 +1252,77 @@ uvm_va_block_retry_t *block_retry, uvm_service_block_context_t *service_context); +// Performs population of the destination pages, unmapping and copying source +// pages to new_residency. +// +// service_context must not be NULL and policy for service_context->region must +// match. See the comments for uvm_va_block_check_policy_is_valid(). If +// va_block is a HMM block, va_block_context->hmm.vma must be valid. See the +// comments for uvm_hmm_check_context_vma_is_valid() in uvm_hmm.h. +// service_context->prefetch_hint should be set before calling this function. +// +// Locking: +// - service_context->block_context.mm->mmap_lock must be held in at least +// read mode, if valid. +// - va_space lock must be held in at least read mode +// - va_block lock must be held +// +// If allocation-retry was required as part of the operation and was successful, +// NV_ERR_MORE_PROCESSING_REQUIRED is returned. In this case, the block's lock +// was unlocked and relocked. +// +// NV_WARN_MORE_PROCESSING_REQUIRED indicates that thrashing has been detected +// and the performance heuristics logic decided to throttle execution. +// Any other error code different than NV_OK indicates OOM or a global fatal +// error. +NV_STATUS uvm_va_block_service_copy(uvm_processor_id_t processor_id, + uvm_processor_id_t new_residency, + uvm_va_block_t *va_block, + uvm_va_block_retry_t *block_retry, + uvm_service_block_context_t *service_context); + +// This updates the va_block residency state and maps the faulting processor_id +// to the new residency (which may be remote). +// +// service_context must not be NULL and policy for service_context->region must +// match. See the comments for uvm_va_block_check_policy_is_valid(). If +// va_block is a HMM block, va_block_context->hmm.vma must be valid. See the +// comments for uvm_hmm_check_context_vma_is_valid() in uvm_hmm.h. +// service_context must be initialized by calling uvm_va_block_service_copy() +// before calling this function. +// +// Locking: +// - service_context->block_context.mm->mmap_lock must be held in at least +// read mode, if valid. +// - va_space lock must be held in at least read mode +// - va_block lock must be held +// - the mmap lock and va_space lock must be held across the calls to +// uvm_va_block_service_copy() and this function. If the va_block lock is +// dropped inbetween, special care is needed to check for eviction and +// invalidation callbacks. +// +// If allocation-retry was required as part of the operation and was successful, +// NV_ERR_MORE_PROCESSING_REQUIRED is returned. In this case, the block's lock +// was unlocked and relocked. +// +// NV_WARN_MORE_PROCESSING_REQUIRED indicates that thrashing has been detected +// and the performance heuristics logic decided to throttle execution. +// Any other error code different than NV_OK indicates OOM or a global fatal +// error. +NV_STATUS uvm_va_block_service_finish(uvm_processor_id_t processor_id, + uvm_va_block_t *va_block, + uvm_service_block_context_t *service_context); + +// Allocate GPU state for the given va_block and registered GPUs. +// Locking: The block lock must be held. +NV_STATUS uvm_va_block_gpu_state_alloc(uvm_va_block_t *va_block); + +// Release any GPU or policy data associated with the given region in response +// to munmap(). +// Locking: The va_block lock must be held. +void uvm_va_block_munmap_region(uvm_va_block_t *va_block, + uvm_va_block_region_t region); + // Size of the block in bytes. Guaranteed to be a page-aligned value between // PAGE_SIZE and UVM_VA_BLOCK_SIZE. static inline NvU64 uvm_va_block_size(uvm_va_block_t *block) @@ -1275,7 +1389,7 @@ // VA block lookup functions. There are a number of permutations which might be // useful, such as looking up the block from {va_space, va_range} x {addr, // block index}. The ones implemented here and in uvm_va_range.h support the -// primary two use cases, which are: +// primary three use cases, which are: // 1) Iterating over all VA blocks in a VA range. This uses block indices on the // VA range: // uvm_va_range_num_blocks @@ -1286,6 +1400,9 @@ // VA space and address: // uvm_va_block_find // uvm_va_block_find_create +// 3) Operating on a single VA block (fault). This looks up the block using the +// supplied VA range and address: +// uvm_va_block_find_create_in_range // Finds the UVM or HMM VA block containing addr, if any. The va_space->lock // must be held in at least read mode. Return values: @@ -1299,40 +1416,38 @@ NV_STATUS uvm_va_block_find(uvm_va_space_t *va_space, NvU64 addr, uvm_va_block_t **out_block); // Same as uvm_va_block_find except that the block is created if not found. -// If addr is covered by a UVM_VA_RANGE_TYPE_MANAGED va_range, a managed block -// will be created. Otherwise, if addr is not covered by any va_range, HMM is -// enabled in the va_space, and va_block_context and va_block_context->mm are -// non-NULL, then a HMM block will be created and va_block_context->hmm.vma is -// set to the VMA covering 'addr'. The va_block_context->policy field is left -// unchanged. -// In either case, if va_block_context->mm is non-NULL, it must be retained and -// locked in at least read mode. Return values: +// If addr is covered by a UVM_VA_RANGE_TYPE_MANAGED va_range a managed block +// will be created. If addr is not covered by any va_range and HMM is +// enabled in the va_space then a HMM block will be created and hmm_vma is +// set to the VMA covering 'addr'. The va_space_mm must be retained and locked. +// Otherwise hmm_vma is set to NULL. +// Return values: // NV_ERR_INVALID_ADDRESS addr is not a UVM_VA_RANGE_TYPE_MANAGED va_range nor // a HMM enabled VMA. // NV_ERR_NO_MEMORY memory could not be allocated. NV_STATUS uvm_va_block_find_create(uvm_va_space_t *va_space, NvU64 addr, - uvm_va_block_context_t *va_block_context, + struct vm_area_struct **hmm_vma, uvm_va_block_t **out_block); // Same as uvm_va_block_find_create except that only managed va_blocks are -// created if not already present in the VA range. -static NV_STATUS uvm_va_block_find_create_managed(uvm_va_space_t *va_space, - NvU64 addr, - uvm_va_block_t **out_block) -{ - return uvm_va_block_find_create(va_space, addr, NULL, out_block); -} +// created if not already present in the VA range. Does not require va_space_mm +// to be locked or retained. +NV_STATUS uvm_va_block_find_create_managed(uvm_va_space_t *va_space, + NvU64 addr, + uvm_va_block_t **out_block); + +// Same as uvm_va_block_find_create_managed except that va_range lookup was +// already done by the caller. The supplied va_range must not be NULL. +NV_STATUS uvm_va_block_find_create_in_range(uvm_va_space_t *va_space, + uvm_va_range_t *va_range, + NvU64 addr, + uvm_va_block_t **out_block); -// Look up a chunk backing a specific address within the VA block. Returns NULL if none. +// Look up a chunk backing a specific address within the VA block. +// Returns NULL if none. uvm_gpu_chunk_t *uvm_va_block_lookup_gpu_chunk(uvm_va_block_t *va_block, uvm_gpu_t *gpu, NvU64 address); -typedef enum -{ - UVM_MIGRATE_MODE_MAKE_RESIDENT, - UVM_MIGRATE_MODE_MAKE_RESIDENT_AND_MAP, -} uvm_migrate_mode_t; - // Implementation of the UvmMigrate() API at the VA block scope. // // The out_tracker can be NULL. @@ -1343,8 +1458,10 @@ // The caller needs to handle allocation-retry. va_block_retry can be NULL if // the destination is the CPU. // -// va_block_context must not be NULL and va_block_context->policy must be valid. -// See the comments for uvm_va_block_check_policy_is_valid(). +// va_block_context must not be NULL and policy for the region must match. See +// the comments for uvm_va_block_check_policy_is_valid(). If va_block is a HMM +// block, va_block_context->hmm.vma must be valid. See the comments for +// uvm_hmm_check_context_vma_is_valid() in uvm_hmm.h. // // LOCKING: The caller must hold the va_block lock. If va_block_context->mm != // NULL, va_block_context->mm->mmap_lock must be held in at least @@ -1362,7 +1479,7 @@ // The [dst, dst + size) range has to fit within a single PAGE_SIZE page. // // va_block_context must not be NULL. The caller is not required to set -// va_block_context->policy. +// va_block_context->hmm.vma. // // The caller needs to support allocation-retry of page tables. // @@ -1416,6 +1533,8 @@ // Computes the size and index in the gpu_state chunks array of the GPU chunk // which corresponds to the given page_index of the VA region. +// Note this is only used for testing and does not work on HMM va_blocks as it +// returns incorrect results for those. size_t uvm_va_block_gpu_chunk_index_range(NvU64 start, NvU64 size, uvm_gpu_t *gpu, @@ -1432,7 +1551,7 @@ // successful, NV_ERR_MORE_PROCESSING_REQUIRED is returned. In this case the // block's lock was unlocked and relocked. // -// va_block_context must not be NULL. The va_block_context->policy is unused. +// va_block_context must not be NULL. // // LOCKING: The caller must hold the va_block lock. NV_STATUS uvm_va_block_set_cancel(uvm_va_block_t *va_block, uvm_va_block_context_t *block_context, uvm_gpu_t *gpu); @@ -1513,12 +1632,18 @@ return uvm_va_block_region(0, uvm_va_block_num_cpu_pages(va_block)); } -// Create a block region from a va block and page mask. Note that the region +// Create a block region from a va block and page mask. If va_block is NULL, the +// region is assumed to cover the maximum va_block size. Note that the region // covers the first through the last set bit and may have unset bits in between. static uvm_va_block_region_t uvm_va_block_region_from_mask(uvm_va_block_t *va_block, const uvm_page_mask_t *page_mask) { uvm_va_block_region_t region; - uvm_page_index_t outer = uvm_va_block_num_cpu_pages(va_block); + uvm_page_index_t outer; + + if (va_block) + outer = uvm_va_block_num_cpu_pages(va_block); + else + outer = PAGES_PER_UVM_VA_BLOCK; region.first = find_first_bit(page_mask->bitmap, outer); if (region.first >= outer) { @@ -1666,6 +1791,11 @@ return bitmap_subset(subset->bitmap, mask->bitmap, PAGES_PER_UVM_VA_BLOCK); } +static bool uvm_page_mask_equal(const uvm_page_mask_t *mask_in1, const uvm_page_mask_t *mask_in2) +{ + return bitmap_equal(mask_in1->bitmap, mask_in2->bitmap, PAGES_PER_UVM_VA_BLOCK); +} + static bool uvm_page_mask_init_from_region(uvm_page_mask_t *mask_out, uvm_va_block_region_t region, const uvm_page_mask_t *mask_in) @@ -1852,6 +1982,23 @@ #define for_each_va_block_page(page_index, va_block) \ for_each_va_block_page_in_region((page_index), uvm_va_block_region_from_block(va_block)) +// Return the first vma intersecting the region [start, va_block->end] +// or NULL if no such vma exists. Also returns the region covered by +// the vma within the va_block. +struct vm_area_struct *uvm_va_block_find_vma_region(uvm_va_block_t *va_block, + struct mm_struct *mm, + NvU64 start, + uvm_va_block_region_t *region); + +// Iterate over all vma regions covered by a va_block +#define for_each_va_block_vma_region(va_block, mm, vma, region) \ + for (vma = uvm_va_block_find_vma_region((va_block), (mm), (va_block)->start, (region)); \ + (vma); \ + vma = uvm_va_block_find_vma_region((va_block), \ + (mm), \ + uvm_va_block_region_end((va_block), *(region)) + 1, \ + (region))) + // Return the block region covered by the given chunk size. page_index must be // any page within the block known to be covered by the chunk. static uvm_va_block_region_t uvm_va_block_chunk_region(uvm_va_block_t *block, @@ -1868,77 +2015,74 @@ // Helpers for page state (permissions, size, residency) // -// Compute the gpus that have at least the given access permissions for the -// range described by region and page_mask. The function sets the bit if any -// page in the region has the permissions. -void uvm_va_block_region_authorized_gpus(uvm_va_block_t *va_block, - uvm_va_block_region_t region, - uvm_prot_t access_permission, - uvm_processor_mask_t *authorized_gpus); - -// Compute the processors that have at least the given access permissions for the -// range described by region and page_mask. The function sets the bit if any -// page in the region has the permissions. -void uvm_va_block_region_authorized_processors(uvm_va_block_t *va_block, - uvm_va_block_region_t region, - uvm_prot_t access_permission, - uvm_processor_mask_t *authorized_processors); - -void uvm_va_block_page_authorized_gpus(uvm_va_block_t *va_block, - uvm_page_index_t page_index, - uvm_prot_t access_permission, - uvm_processor_mask_t *authorized_gpus); - -void uvm_va_block_page_authorized_processors(uvm_va_block_t *va_block, - uvm_page_index_t page_index, - uvm_prot_t access_permission, - uvm_processor_mask_t *authorized_processors); - -bool uvm_va_block_is_gpu_authorized_on_whole_region(uvm_va_block_t *va_block, - uvm_va_block_region_t region, - uvm_gpu_id_t gpu_id, - uvm_prot_t required_prot); - -bool uvm_va_block_is_processor_authorized_on_whole_region(uvm_va_block_t *va_block, - uvm_va_block_region_t region, - uvm_processor_id_t processor_id, - uvm_prot_t required_prot); - bool uvm_va_block_page_is_gpu_authorized(uvm_va_block_t *va_block, uvm_page_index_t page_index, uvm_gpu_id_t gpu_id, uvm_prot_t required_prot); -bool uvm_va_block_page_is_processor_authorized(uvm_va_block_t *va_block, - uvm_page_index_t page_index, - uvm_processor_id_t processor_id, - uvm_prot_t required_prot); - -// Compute the gpus that have a copy of the given page resident in their memory -void uvm_va_block_page_resident_gpus(uvm_va_block_t *va_block, - uvm_page_index_t page_index, - uvm_processor_mask_t *resident_gpus); - -// Compute the processors that have a copy of the given page resident in their memory +// Compute the processors that have a copy of the given page resident in their +// memory. void uvm_va_block_page_resident_processors(uvm_va_block_t *va_block, uvm_page_index_t page_index, uvm_processor_mask_t *resident_processors); -// Count how many processors have a copy of the given page resident in their memory +// Count how many processors have a copy of the given page resident in their +// memory. NvU32 uvm_va_block_page_resident_processors_count(uvm_va_block_t *va_block, uvm_page_index_t page_index); -// Get the processor with a resident copy of a page closest to the given processor +// Get the processor with a resident copy of a page closest to the given +// processor. uvm_processor_id_t uvm_va_block_page_get_closest_resident(uvm_va_block_t *va_block, uvm_page_index_t page_index, uvm_processor_id_t processor); -uvm_processor_id_t uvm_va_block_page_get_closest_resident_in_mask(uvm_va_block_t *va_block, - uvm_page_index_t page_index, - uvm_processor_id_t processor, - const uvm_processor_mask_t *processor_mask); +// Insert a CPU chunk at the given page_index into the va_block. +// Locking: The va_block lock must be held. +NV_STATUS uvm_cpu_chunk_insert_in_block(uvm_va_block_t *va_block, + uvm_cpu_chunk_t *chunk, + uvm_page_index_t page_index); + +// Remove a CPU chunk at the given page_index from the va_block. +// Locking: The va_block lock must be held. +void uvm_cpu_chunk_remove_from_block(uvm_va_block_t *va_block, + uvm_page_index_t page_index); + +// Return the CPU chunk at the given page_index from the va_block. +// Locking: The va_block lock must be held. +uvm_cpu_chunk_t *uvm_cpu_chunk_get_chunk_for_page(uvm_va_block_t *va_block, + uvm_page_index_t page_index); + +// Return the CPU chunk at the given page_index from the va_block. +// Locking: The va_block lock must be held. +struct page *uvm_cpu_chunk_get_cpu_page(uvm_va_block_t *va_block, + uvm_page_index_t page_index); + +// Physically map a CPU chunk so it is DMA'able from all registered GPUs. +// Locking: The va_block lock must be held. +NV_STATUS uvm_va_block_map_cpu_chunk_on_gpus(uvm_va_block_t *va_block, + uvm_page_index_t page_index); + +// Physically unmap a CPU chunk from all registered GPUs. +// Locking: The va_block lock must be held. +void uvm_va_block_unmap_cpu_chunk_on_gpus(uvm_va_block_t *va_block, + uvm_cpu_chunk_t *chunk, + uvm_page_index_t page_index); + +// Remove any CPU chunks in the given region. +// Locking: The va_block lock must be held. +void uvm_va_block_remove_cpu_chunks(uvm_va_block_t *va_block, uvm_va_block_region_t region); + +// Get the size of the physical allocation backing the page at page_index on the +// specified processor in the block. Returns 0 if the address is not resident on +// the specified processor. +// Locking: The va_block lock must be held. +NvU32 uvm_va_block_get_physical_size(uvm_va_block_t *block, + uvm_processor_id_t processor, + uvm_page_index_t page_index); // Get CPU page size or 0 if it is not mapped -NvU32 uvm_va_block_page_size_cpu(uvm_va_block_t *va_block, uvm_page_index_t page_index); +NvU32 uvm_va_block_page_size_cpu(uvm_va_block_t *va_block, + uvm_page_index_t page_index); // Get GPU page size or 0 if it is not mapped on the given GPU NvU32 uvm_va_block_page_size_gpu(uvm_va_block_t *va_block, uvm_gpu_id_t gpu_id, uvm_page_index_t page_index); @@ -1992,21 +2136,20 @@ // MAX_BIG_PAGES_PER_UVM_VA_BLOCK is returned. size_t uvm_va_block_big_page_index(uvm_va_block_t *va_block, uvm_page_index_t page_index, NvU32 big_page_size); -// Returns the new residency for a page that faulted or triggered access -// counter notifications. The read_duplicate output parameter indicates if the -// page meets the requirements to be read-duplicated -// va_block_context must not be NULL, va_block_context->policy must be valid, -// and if the va_block is a HMM block, va_block_context->hmm.vma must be valid -// which also means the va_block_context->mm is not NULL, retained, and locked -// for at least read. See the comments for uvm_va_block_check_policy_is_valid() -// and uvm_hmm_va_block_context_vma_is_valid() in uvm_hmm.h. -// Locking: the va_block lock must be held. +// Returns the new residency for a page that faulted or triggered access counter +// notifications. The read_duplicate output parameter indicates if the page +// meets the requirements to be read-duplicated va_block_context must not be +// NULL, and if the va_block is a HMM block, va_block_context->hmm.vma must be +// valid which also means the va_block_context->mm is not NULL, retained, and +// locked for at least read. See the comments for +// uvm_va_block_check_policy_is_valid() and uvm_hmm_check_context_vma_is_valid() +// in uvm_hmm.h. Locking: the va_block lock must be held. uvm_processor_id_t uvm_va_block_select_residency(uvm_va_block_t *va_block, uvm_va_block_context_t *va_block_context, uvm_page_index_t page_index, uvm_processor_id_t processor_id, NvU32 access_type_mask, - uvm_va_policy_t *policy, + const uvm_va_policy_t *policy, const uvm_perf_thrashing_hint_t *thrashing_hint, uvm_service_operation_t operation, bool *read_duplicate); diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/kernel-open/nvidia-uvm/uvm_va_block_types.h nvidia-open-gpu-kernel-modules-535.161.08/kernel-open/nvidia-uvm/uvm_va_block_types.h --- nvidia-open-gpu-kernel-modules-525.147.05/kernel-open/nvidia-uvm/uvm_va_block_types.h 2023-10-25 20:33:35.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/kernel-open/nvidia-uvm/uvm_va_block_types.h 2024-03-05 22:25:53.000000000 +0000 @@ -1,5 +1,5 @@ /******************************************************************************* - Copyright (c) 2016-2019 NVIDIA Corporation + Copyright (c) 2016-2023 NVIDIA Corporation Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation files (the "Software"), to @@ -27,6 +27,9 @@ #include "uvm_common.h" #include "uvm_pte_batch.h" #include "uvm_tlb_batch.h" +#include "uvm_forward_decl.h" + +#include // UVM_VA_BLOCK_BITS is 21, meaning the maximum block size is 2MB. Rationale: // - 2MB matches the largest Pascal GPU page size so it's a natural fit @@ -161,8 +164,12 @@ { // Masks used internally uvm_page_mask_t page_mask; - uvm_page_mask_t copy_resident_pages_between_mask; + uvm_page_mask_t copy_resident_pages_mask; uvm_page_mask_t pages_staged; + + // This is used to store which pages were successfully copied to the + // destination processor and used by uvm_va_block_make_resident_finish() + // to update the va_block state. uvm_page_mask_t pages_migrated; // Out mask filled in by uvm_va_block_make_resident to indicate which @@ -225,15 +232,31 @@ // the mm, such as creating CPU mappings. struct mm_struct *mm; - uvm_va_policy_t *policy; - -#if UVM_IS_CONFIG_HMM() struct { + // These are used for migrate_vma_*(), hmm_range_fault(), and + // make_device_exclusive_range() handling. + unsigned long src_pfns[PAGES_PER_UVM_VA_BLOCK]; + union { + unsigned long dst_pfns[PAGES_PER_UVM_VA_BLOCK]; + struct page *pages[PAGES_PER_UVM_VA_BLOCK]; + }; + + // This flag indicates that at least one page in range being migrated + // or process for a GPU fault (i.e, faulted or prefetched), then + // the whole range will be migrated or remote mapped to system memory. + // TODO: Bug 4050579: Remove this when swap cached pages can be + // migrated. + bool swap_cached; + // Cached VMA pointer. This is only valid while holding the mmap_lock. struct vm_area_struct *vma; - } hmm; + +#if UVM_IS_CONFIG_HMM() + // Used for migrate_vma_*() to migrate pages to/from GPU/CPU. + struct migrate_vma migrate_vma_args; #endif + } hmm; // Convenience buffer for page mask prints char page_mask_string_buffer[UVM_PAGE_MASK_PRINT_MIN_BUFFER_SIZE]; @@ -242,8 +265,7 @@ typedef enum { UVM_VA_BLOCK_TRANSFER_MODE_MOVE = 1, - UVM_VA_BLOCK_TRANSFER_MODE_COPY = 2, - UVM_VA_BLOCK_TRANSFER_MODE_COPY_ONLY = 3 + UVM_VA_BLOCK_TRANSFER_MODE_COPY = 2 } uvm_va_block_transfer_mode_t; struct uvm_reverse_map_struct @@ -266,4 +288,10 @@ UVM_SERVICE_OPERATION_ACCESS_COUNTERS, } uvm_service_operation_t; +typedef enum +{ + UVM_MIGRATE_MODE_MAKE_RESIDENT, + UVM_MIGRATE_MODE_MAKE_RESIDENT_AND_MAP, +} uvm_migrate_mode_t; + #endif diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/kernel-open/nvidia-uvm/uvm_va_policy.c nvidia-open-gpu-kernel-modules-535.161.08/kernel-open/nvidia-uvm/uvm_va_policy.c --- nvidia-open-gpu-kernel-modules-525.147.05/kernel-open/nvidia-uvm/uvm_va_policy.c 2023-10-25 20:33:35.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/kernel-open/nvidia-uvm/uvm_va_policy.c 2024-03-05 22:25:53.000000000 +0000 @@ -29,23 +29,23 @@ #include "uvm_va_space.h" #include "uvm_va_range.h" -uvm_va_policy_t uvm_va_policy_default __read_mostly = { +const uvm_va_policy_t uvm_va_policy_default = { .preferred_location = UVM_ID_INVALID, .read_duplication = UVM_READ_DUPLICATION_UNSET, }; -bool uvm_va_policy_is_read_duplicate(uvm_va_policy_t *policy, uvm_va_space_t *va_space) +bool uvm_va_policy_is_read_duplicate(const uvm_va_policy_t *policy, uvm_va_space_t *va_space) { return policy->read_duplication == UVM_READ_DUPLICATION_ENABLED && uvm_va_space_can_read_duplicate(va_space, NULL); } -uvm_va_policy_t *uvm_va_policy_get(uvm_va_block_t *va_block, NvU64 addr) +const uvm_va_policy_t *uvm_va_policy_get(uvm_va_block_t *va_block, NvU64 addr) { uvm_assert_mutex_locked(&va_block->lock); if (uvm_va_block_is_hmm(va_block)) { - uvm_va_policy_node_t *node = uvm_va_policy_node_find(va_block, addr); + const uvm_va_policy_node_t *node = uvm_va_policy_node_find(va_block, addr); return node ? &node->policy : &uvm_va_policy_default; } @@ -54,6 +54,52 @@ } } +// HMM va_blocks can have different polices for different regions withing the +// va_block. This function checks the given region is covered by the same policy +// and asserts if the region is covered by different policies. +// This always returns true and is intended to only be used with UVM_ASSERT() to +// avoid calling it on release builds. +// Locking: the va_block lock must be held. +static bool uvm_hmm_va_block_assert_policy_is_valid(uvm_va_block_t *va_block, + const uvm_va_policy_t *policy, + uvm_va_block_region_t region) +{ + const uvm_va_policy_node_t *node; + + if (uvm_va_policy_is_default(policy)) { + // There should only be the default policy within the region. + node = uvm_va_policy_node_iter_first(va_block, + uvm_va_block_region_start(va_block, region), + uvm_va_block_region_end(va_block, region)); + UVM_ASSERT(!node); + } + else { + // The policy node should cover the region. + node = uvm_va_policy_node_from_policy(policy); + UVM_ASSERT(node->node.start <= uvm_va_block_region_start(va_block, region)); + UVM_ASSERT(node->node.end >= uvm_va_block_region_end(va_block, region)); + } + + return true; +} + +const uvm_va_policy_t *uvm_va_policy_get_region(uvm_va_block_t *va_block, uvm_va_block_region_t region) +{ + uvm_assert_mutex_locked(&va_block->lock); + + if (uvm_va_block_is_hmm(va_block)) { + const uvm_va_policy_t *policy; + const uvm_va_policy_node_t *node = uvm_va_policy_node_find(va_block, uvm_va_block_region_start(va_block, region)); + + policy = node ? &node->policy : &uvm_va_policy_default; + UVM_ASSERT(uvm_hmm_va_block_assert_policy_is_valid(va_block, policy, region)); + return policy; + } + else { + return uvm_va_range_get_policy(va_block->va_range); + } +} + #if UVM_IS_CONFIG_HMM() static struct kmem_cache *g_uvm_va_policy_node_cache __read_mostly; @@ -63,14 +109,6 @@ return container_of(tree_node, uvm_va_policy_node_t, node); } -static uvm_va_policy_t *uvm_va_policy_container(uvm_range_tree_node_t *tree_node) -{ - if (!tree_node) - return NULL; - - return &uvm_va_policy_node_container(tree_node)->policy; -} - NV_STATUS uvm_va_policy_init(void) { g_uvm_va_policy_node_cache = NV_KMEM_CACHE_CREATE("uvm_va_policy_node_t", uvm_va_policy_node_t); @@ -173,15 +211,15 @@ return uvm_va_policy_node_container(tree_node); } -uvm_va_policy_t *uvm_va_policy_iter_first(uvm_va_block_t *va_block, - NvU64 start, - NvU64 end, - uvm_va_policy_node_t **out_node, - uvm_va_block_region_t *out_region) +const uvm_va_policy_t *uvm_va_policy_iter_first(uvm_va_block_t *va_block, + NvU64 start, + NvU64 end, + uvm_va_policy_node_t **out_node, + uvm_va_block_region_t *out_region) { uvm_range_tree_node_t *tree_node; uvm_va_policy_node_t *node; - uvm_va_policy_t *policy; + const uvm_va_policy_t *policy; uvm_va_block_region_t region; UVM_ASSERT(uvm_va_block_is_hmm(va_block)); @@ -219,11 +257,11 @@ return policy; } -uvm_va_policy_t *uvm_va_policy_iter_next(uvm_va_block_t *va_block, - uvm_va_policy_t *policy, - NvU64 end, - uvm_va_policy_node_t **inout_node, - uvm_va_block_region_t *inout_region) +const uvm_va_policy_t *uvm_va_policy_iter_next(uvm_va_block_t *va_block, + const uvm_va_policy_t *policy, + NvU64 end, + uvm_va_policy_node_t **inout_node, + uvm_va_block_region_t *inout_region) { uvm_va_policy_node_t *node = *inout_node; uvm_va_policy_node_t *next; @@ -234,7 +272,7 @@ next = uvm_va_policy_node_iter_next(va_block, node, end); - if (policy == &uvm_va_policy_default) { + if (uvm_va_policy_is_default(policy)) { // We haven't used the current policy node yet so use it now. next = node; policy = &node->policy; @@ -563,4 +601,39 @@ return NV_OK; } +const uvm_va_policy_t *uvm_va_policy_set_preferred_location(uvm_va_block_t *va_block, + uvm_va_block_region_t region, + uvm_processor_id_t processor_id, + const uvm_va_policy_t *old_policy) +{ + NvU64 start = uvm_va_block_region_start(va_block, region); + NvU64 end = uvm_va_block_region_end(va_block, region); + uvm_va_policy_node_t *node; + + if (uvm_va_policy_is_default(old_policy)) { + + UVM_ASSERT(!UVM_ID_IS_INVALID(processor_id)); + UVM_ASSERT(!uvm_range_tree_iter_first(&va_block->hmm.va_policy_tree, start, end)); + + node = uvm_va_policy_node_create(va_block, start, end); + if (!node) + return NULL; + } + else { + // Since the old_policy isn't the constant default policy, we know it + // is an allocated uvm_va_policy_node_t and can be cast. + node = container_of((uvm_va_policy_t *)old_policy, uvm_va_policy_node_t, policy); + + // The caller guarantees that the policy node doesn't require splitting + // and that the policy is changing. + UVM_ASSERT(node->node.start >= start); + UVM_ASSERT(node->node.end <= end); + UVM_ASSERT(!uvm_id_equal(node->policy.preferred_location, processor_id)); + } + + node->policy.preferred_location = processor_id; + + return &node->policy; +} + #endif // UVM_IS_CONFIG_HMM() diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/kernel-open/nvidia-uvm/uvm_va_policy.h nvidia-open-gpu-kernel-modules-535.161.08/kernel-open/nvidia-uvm/uvm_va_policy.h --- nvidia-open-gpu-kernel-modules-525.147.05/kernel-open/nvidia-uvm/uvm_va_policy.h 2023-10-25 20:33:35.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/kernel-open/nvidia-uvm/uvm_va_policy.h 2024-03-05 22:25:53.000000000 +0000 @@ -82,20 +82,29 @@ } uvm_va_policy_node_t; // Function pointer prototype for uvm_hmm_split_as_needed() callback. -typedef bool (*uvm_va_policy_is_split_needed_t)(uvm_va_policy_t *policy, void *data); +typedef bool (*uvm_va_policy_is_split_needed_t)(const uvm_va_policy_t *policy, void *data); // Default policy to save uvm_va_policy_node_t space in HMM va_blocks. -extern uvm_va_policy_t uvm_va_policy_default; +extern const uvm_va_policy_t uvm_va_policy_default; -bool uvm_va_policy_is_read_duplicate(uvm_va_policy_t *policy, uvm_va_space_t *va_space); +// Return true if policy is the default policy. +static bool uvm_va_policy_is_default(const uvm_va_policy_t *policy) +{ + return policy == &uvm_va_policy_default; +} + +bool uvm_va_policy_is_read_duplicate(const uvm_va_policy_t *policy, uvm_va_space_t *va_space); // Returns the uvm_va_policy_t containing addr or default policy if not found. // The va_block can be either a UVM or HMM va_block. // Locking: The va_block lock must be held. -uvm_va_policy_t *uvm_va_policy_get(uvm_va_block_t *va_block, NvU64 addr); +const uvm_va_policy_t *uvm_va_policy_get(uvm_va_block_t *va_block, NvU64 addr); + +// Same as above but asserts the policy covers the whole region +const uvm_va_policy_t *uvm_va_policy_get_region(uvm_va_block_t *va_block, uvm_va_block_region_t region); // Return a uvm_va_policy_node_t given a uvm_va_policy_t pointer. -static uvm_va_policy_node_t *uvm_va_policy_node_from_policy(uvm_va_policy_t *policy) +static const uvm_va_policy_node_t *uvm_va_policy_node_from_policy(const uvm_va_policy_t *policy) { return container_of(policy, uvm_va_policy_node_t, policy); } @@ -151,6 +160,17 @@ uvm_processor_id_t processor_id, uvm_read_duplication_policy_t new_policy); +// This is an optimized version of uvm_va_policy_set_range() where the caller +// guarantees that the the processor_id is not the same as the existing +// policy for the given region and that the region doesn't require splitting +// the existing policy node 'old_policy'. +// Returns the updated policy or NULL if memory could not be allocated. +// Locking: The va_block lock must be held. +const uvm_va_policy_t *uvm_va_policy_set_preferred_location(uvm_va_block_t *va_block, + uvm_va_block_region_t region, + uvm_processor_id_t processor_id, + const uvm_va_policy_t *old_policy); + // Iterators for specific VA policy ranges. // Returns the first policy node in the range [start, end], if any. @@ -173,24 +193,25 @@ for ((node) = uvm_va_policy_node_iter_first((va_block), (start), (end)), \ (next) = uvm_va_policy_node_iter_next((va_block), (node), (end)); \ (node); \ - (node) = (next)) + (node) = (next), \ + (next) = uvm_va_policy_node_iter_next((va_block), (node), (end))) // Returns the first policy in the range [start, end], if any. // Locking: The va_block lock must be held. -uvm_va_policy_t *uvm_va_policy_iter_first(uvm_va_block_t *va_block, - NvU64 start, - NvU64 end, - uvm_va_policy_node_t **out_node, - uvm_va_block_region_t *out_region); +const uvm_va_policy_t *uvm_va_policy_iter_first(uvm_va_block_t *va_block, + NvU64 start, + NvU64 end, + uvm_va_policy_node_t **out_node, + uvm_va_block_region_t *out_region); // Returns the next VA policy following the provided policy in address order, // if that policy's start <= the provided end. // Locking: The va_block lock must be held. -uvm_va_policy_t *uvm_va_policy_iter_next(uvm_va_block_t *va_block, - uvm_va_policy_t *policy, - NvU64 end, - uvm_va_policy_node_t **inout_node, - uvm_va_block_region_t *inout_region); +const uvm_va_policy_t *uvm_va_policy_iter_next(uvm_va_block_t *va_block, + const uvm_va_policy_t *policy, + NvU64 end, + uvm_va_policy_node_t **inout_node, + uvm_va_block_region_t *inout_region); // Note that policy and region are set and usable in the loop body. // The 'node' variable is used to retain loop state and 'policy' doesn't diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/kernel-open/nvidia-uvm/uvm_va_range.c nvidia-open-gpu-kernel-modules-535.161.08/kernel-open/nvidia-uvm/uvm_va_range.c --- nvidia-open-gpu-kernel-modules-525.147.05/kernel-open/nvidia-uvm/uvm_va_range.c 2023-10-25 20:33:35.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/kernel-open/nvidia-uvm/uvm_va_range.c 2024-03-05 22:25:53.000000000 +0000 @@ -1,5 +1,5 @@ /******************************************************************************* - Copyright (c) 2015-2022 NVIDIA Corporation + Copyright (c) 2015-2023 NVIDIA Corporation Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation files (the "Software"), to @@ -25,11 +25,13 @@ #include "uvm_linux.h" #include "uvm_types.h" #include "uvm_api.h" +#include "uvm_hal.h" #include "uvm_va_range.h" #include "uvm_va_block.h" #include "uvm_kvmalloc.h" #include "uvm_map_external.h" #include "uvm_perf_thrashing.h" +#include "uvm_conf_computing.h" #include "nv_uvm_interface.h" static struct kmem_cache *g_uvm_va_range_cache __read_mostly; @@ -114,7 +116,6 @@ return NULL; uvm_assert_rwsem_locked_write(&va_space->lock); - UVM_ASSERT(uvm_va_space_initialized(va_space) == NV_OK); va_range->va_space = va_space; va_range->node.start = start; @@ -375,7 +376,7 @@ if (status != NV_OK) goto error; - if (i == 0 && g_uvm_global.sev_enabled) + if (i == 0 && g_uvm_global.conf_computing_enabled) mem_alloc_params.dma_owner = gpu; if (attrs.is_cacheable) { @@ -466,11 +467,7 @@ // Unmap the buffer if (gpu_va_space && va_range->channel.pt_range_vec.ranges) { - if (va_range->channel.aperture == UVM_APERTURE_VID) - membar = UVM_MEMBAR_GPU; - else - membar = UVM_MEMBAR_SYS; - + membar = uvm_hal_downgrade_membar_type(gpu_va_space->gpu, va_range->channel.aperture == UVM_APERTURE_VID); uvm_page_table_range_vec_clear_ptes(&va_range->channel.pt_range_vec, membar); uvm_page_table_range_vec_deinit(&va_range->channel.pt_range_vec); } @@ -611,7 +608,6 @@ uvm_va_block_t *va_block; uvm_va_block_context_t *va_block_context = uvm_va_space_block_context(va_space, mm); - va_block_context->policy = uvm_va_range_get_policy(va_range); // TODO: Bug 2090378. Consolidate all per-VA block operations within // uvm_va_block_add_gpu_va_space so we only need to take the VA block @@ -690,7 +686,6 @@ bool should_enable_read_duplicate; uvm_va_block_context_t *va_block_context = uvm_va_space_block_context(va_space, mm); - va_block_context->policy = uvm_va_range_get_policy(va_range); should_enable_read_duplicate = uvm_va_range_get_policy(va_range)->read_duplication == UVM_READ_DUPLICATION_ENABLED && uvm_va_space_can_read_duplicate(va_space, NULL) != uvm_va_space_can_read_duplicate(va_space, gpu_va_space->gpu); @@ -727,7 +722,10 @@ { UVM_ASSERT(va_range->type == UVM_VA_RANGE_TYPE_SEMAPHORE_POOL); - uvm_mem_unmap_gpu_user(va_range->semaphore_pool.mem, gpu); + if (uvm_conf_computing_mode_enabled(gpu) && (va_range->semaphore_pool.mem->dma_owner == gpu)) + uvm_va_range_destroy(va_range, NULL); + else + uvm_mem_unmap_gpu_user(va_range->semaphore_pool.mem, gpu); } void uvm_va_range_remove_gpu_va_space(uvm_va_range_t *va_range, @@ -769,7 +767,6 @@ uvm_va_space_t *va_space = va_range->va_space; uvm_va_block_context_t *va_block_context = uvm_va_space_block_context(va_space, NULL); - va_block_context->policy = uvm_va_range_get_policy(va_range); for_each_va_block_in_va_range(va_range, va_block) { // TODO: Bug 1767224: Refactor the uvm_va_block_set_accessed_by logic @@ -1079,7 +1076,7 @@ // Even if there was no block split above, there is no guarantee that one // of our blocks doesn't have the 'inject_split_error' flag set. We clear // that here to prevent multiple errors caused by one - // 'uvm_test_va_range_inject_split_error' call. + // 'uvm_test_va_range_inject_split_error' call. if (existing->inject_split_error) { UVM_ASSERT(!block); existing->inject_split_error = false; @@ -1196,13 +1193,6 @@ } -static inline uvm_va_range_t *uvm_va_range_container(uvm_range_tree_node_t *node) -{ - if (!node) - return NULL; - return container_of(node, uvm_va_range_t, node); -} - uvm_va_range_t *uvm_va_range_find(uvm_va_space_t *va_space, NvU64 addr) { uvm_assert_rwsem_locked(&va_space->lock); @@ -1329,7 +1319,6 @@ if (uvm_processor_mask_empty(mask)) return NV_OK; - block_context->policy = uvm_va_range_get_policy(va_range); for_each_va_block_in_va_range(va_range, block) { NV_STATUS status; @@ -1371,7 +1360,6 @@ if (uvm_processor_mask_empty(&va_range->uvm_lite_gpus)) return NV_OK; - va_block_context->policy = uvm_va_range_get_policy(va_range); for_each_va_block_in_va_range(va_range, va_block) { // UVM-Lite GPUs always map with RWA @@ -1535,10 +1523,10 @@ uvm_processor_mask_copy(&va_range->uvm_lite_gpus, &new_uvm_lite_gpus); va_block_context = uvm_va_space_block_context(va_space, mm); - va_block_context->policy = uvm_va_range_get_policy(va_range); for_each_va_block_in_va_range(va_range, va_block) { uvm_processor_id_t id; + uvm_va_block_region_t region = uvm_va_block_region_from_block(va_block); for_each_id_in_mask(id, &set_accessed_by_processors) { status = uvm_va_block_set_accessed_by(va_block, va_block_context, id); @@ -1551,16 +1539,22 @@ uvm_mutex_lock(&va_block->lock); status = UVM_VA_BLOCK_RETRY_LOCKED(va_block, NULL, - uvm_va_block_set_preferred_location_locked(va_block, va_block_context)); - - if (out_tracker) - uvm_tracker_add_tracker_safe(out_tracker, &va_block->tracker); + uvm_va_block_set_preferred_location_locked(va_block, + va_block_context, + region)); + + if (out_tracker) { + NV_STATUS tracker_status; + + tracker_status = uvm_tracker_add_tracker_safe(out_tracker, &va_block->tracker); + if (status == NV_OK) + status = tracker_status; + } uvm_mutex_unlock(&va_block->lock); if (status != NV_OK) return status; - } // And lastly map all of the current UVM-Lite GPUs to the resident pages on @@ -1610,7 +1604,6 @@ uvm_processor_mask_copy(&va_range->uvm_lite_gpus, &new_uvm_lite_gpus); va_block_context = uvm_va_space_block_context(va_space, mm); - va_block_context->policy = policy; for_each_va_block_in_va_range(va_range, va_block) { status = uvm_va_block_set_accessed_by(va_block, va_block_context, processor_id); @@ -1657,7 +1650,6 @@ return NV_OK; va_block_context = uvm_va_space_block_context(va_range->va_space, mm); - va_block_context->policy = uvm_va_range_get_policy(va_range); for_each_va_block_in_va_range(va_range, va_block) { NV_STATUS status = uvm_va_block_set_read_duplication(va_block, va_block_context); @@ -1679,7 +1671,6 @@ return NV_OK; va_block_context = uvm_va_space_block_context(va_range->va_space, mm); - va_block_context->policy = uvm_va_range_get_policy(va_range); for_each_va_block_in_va_range(va_range, va_block) { status = uvm_va_block_unset_read_duplication(va_block, va_block_context); @@ -1816,7 +1807,7 @@ if (params->gpuAttributesCount > UVM_MAX_GPUS) return NV_ERR_INVALID_ARGUMENT; - if (g_uvm_global.sev_enabled && params->gpuAttributesCount == 0) + if (g_uvm_global.conf_computing_enabled && params->gpuAttributesCount == 0) return NV_ERR_INVALID_ARGUMENT; // The mm needs to be locked in order to remove stale HMM va_blocks. diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/kernel-open/nvidia-uvm/uvm_va_range.h nvidia-open-gpu-kernel-modules-535.161.08/kernel-open/nvidia-uvm/uvm_va_range.h --- nvidia-open-gpu-kernel-modules-525.147.05/kernel-open/nvidia-uvm/uvm_va_range.h 2023-10-25 20:33:35.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/kernel-open/nvidia-uvm/uvm_va_range.h 2024-03-05 22:25:53.000000000 +0000 @@ -537,6 +537,13 @@ // TODO: Bug 1707562: Merge va ranges +static uvm_va_range_t *uvm_va_range_container(uvm_range_tree_node_t *node) +{ + if (!node) + return NULL; + return container_of(node, uvm_va_range_t, node); +} + // Returns the va_range containing addr, if any uvm_va_range_t *uvm_va_range_find(uvm_va_space_t *va_space, NvU64 addr); diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/kernel-open/nvidia-uvm/uvm_va_space.c nvidia-open-gpu-kernel-modules-535.161.08/kernel-open/nvidia-uvm/uvm_va_space.c --- nvidia-open-gpu-kernel-modules-525.147.05/kernel-open/nvidia-uvm/uvm_va_space.c 2023-10-25 20:33:33.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/kernel-open/nvidia-uvm/uvm_va_space.c 2024-03-05 22:25:50.000000000 +0000 @@ -1,5 +1,5 @@ /******************************************************************************* - Copyright (c) 2015-2022 NVIDIA Corporation + Copyright (c) 2015-2023 NVIDIA Corporation Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation files (the "Software"), to @@ -160,15 +160,21 @@ return true; } -NV_STATUS uvm_va_space_create(struct inode *inode, struct file *filp) +NV_STATUS uvm_va_space_create(struct address_space *mapping, uvm_va_space_t **va_space_ptr, NvU64 flags) { NV_STATUS status; uvm_va_space_t *va_space = uvm_kvmalloc_zero(sizeof(*va_space)); uvm_gpu_id_t gpu_id; + *va_space_ptr = NULL; if (!va_space) return NV_ERR_NO_MEMORY; + if (flags & ~UVM_INIT_FLAGS_MASK) { + uvm_kvfree(va_space); + return NV_ERR_INVALID_ARGUMENT; + } + uvm_init_rwsem(&va_space->lock, UVM_LOCK_ORDER_VA_SPACE); uvm_mutex_init(&va_space->serialize_writers_lock, UVM_LOCK_ORDER_VA_SPACE_SERIALIZE_WRITERS); uvm_mutex_init(&va_space->read_acquire_write_release_lock, @@ -177,29 +183,6 @@ uvm_range_tree_init(&va_space->va_range_tree); uvm_ats_init_va_space(va_space); - // By default all struct files on the same inode share the same - // address_space structure (the inode's) across all processes. This means - // unmap_mapping_range would unmap virtual mappings across all processes on - // that inode. - // - // Since the UVM driver uses the mapping offset as the VA of the file's - // process, we need to isolate the mappings to each process. - address_space_init_once(&va_space->mapping); - va_space->mapping.host = inode; - - // Some paths in the kernel, for example force_page_cache_readahead which - // can be invoked from user-space via madvise MADV_WILLNEED and fadvise - // POSIX_FADV_WILLNEED, check the function pointers within - // file->f_mapping->a_ops for validity. However, those paths assume that a_ops - // itself is always valid. Handle that by using the inode's a_ops pointer, - // which is what f_mapping->a_ops would point to anyway if we weren't re- - // assigning f_mapping. - va_space->mapping.a_ops = inode->i_mapping->a_ops; - -#if defined(NV_ADDRESS_SPACE_HAS_BACKING_DEV_INFO) - va_space->mapping.backing_dev_info = inode->i_mapping->backing_dev_info; -#endif - // Init to 0 since we rely on atomic_inc_return behavior to return 1 as the first ID atomic64_set(&va_space->range_group_id_counter, 0); @@ -231,13 +214,12 @@ init_waitqueue_head(&va_space->va_space_mm.last_retainer_wait_queue); init_waitqueue_head(&va_space->gpu_va_space_deferred_free.wait_queue); - filp->private_data = va_space; - filp->f_mapping = &va_space->mapping; - + va_space->mapping = mapping; va_space->test.page_prefetch_enabled = true; init_tools_data(va_space); + uvm_down_write_mmap_lock(current->mm); uvm_va_space_down_write(va_space); status = uvm_perf_init_va_space_events(va_space, &va_space->perf_events); @@ -254,18 +236,34 @@ UVM_ASSERT(va_space_check_processors_masks(va_space)); + va_space->initialization_flags = flags; + + status = uvm_va_space_mm_register(va_space); + if (status != NV_OK) + goto fail; + + uvm_hmm_va_space_initialize(va_space); + uvm_va_space_up_write(va_space); + uvm_up_write_mmap_lock(current->mm); uvm_mutex_lock(&g_uvm_global.va_spaces.lock); list_add_tail(&va_space->list_node, &g_uvm_global.va_spaces.list); uvm_mutex_unlock(&g_uvm_global.va_spaces.lock); + *va_space_ptr = va_space; + return NV_OK; fail: uvm_perf_heuristics_unload(va_space); uvm_perf_destroy_va_space_events(&va_space->perf_events); uvm_va_space_up_write(va_space); + uvm_up_write_mmap_lock(current->mm); + + // See the comment in uvm_va_space_mm_unregister() for why this has to be + // called after releasing the locks. + uvm_va_space_mm_unregister(va_space); uvm_kvfree(va_space); @@ -296,6 +294,8 @@ uvm_for_each_va_range(va_range, va_space) uvm_va_range_unregister_gpu(va_range, gpu, mm, deferred_free_list); + uvm_hmm_unregister_gpu(va_space, gpu, mm); + // If this GPU has any peer-to-peer pair that was explicitly enabled, but // not explicitly disabled, disable it. // Notably do this only after unregistering the GPU from VA ranges to make @@ -365,6 +365,11 @@ } } + if (va_space->gpu_unregister_dma_buffer[uvm_id_gpu_index(gpu->id)]) { + uvm_conf_computing_dma_buffer_free(&gpu->conf_computing.dma_buffer_pool, + va_space->gpu_unregister_dma_buffer[uvm_id_gpu_index(gpu->id)], + &va_space->gpu_unregister_dma_buffer[uvm_id_gpu_index(gpu->id)]->tracker); + } va_space_check_processors_masks(va_space); } @@ -516,17 +521,15 @@ uvm_deferred_free_object_list(&deferred_free_list); - // Remove the mm_struct association on this VA space, if any. This may - // invoke uvm_va_space_mm_shutdown(), which in turn will disable all - // channels and wait for any retainers to finish, so it has to be done - // outside of the VA space lock. - // - // Since we must already handle mm shutdown being called at any point prior - // to this call, this call can be made at any point in - // uvm_va_space_destroy(). It's beneficial to do it late after doing all - // deferred frees for GPU VA spaces and channels, because then - // uvm_va_space_mm_shutdown() will have minimal work to do. - uvm_va_space_mm_unregister(va_space); + // Normally we'd expect this to happen as part of uvm_mm_release() + // but if userspace never initialized uvm_mm_fd that won't happen. + // We don't have to take the va_space_mm spinlock and update state + // here because we know no other thread can be in or subsequently + // call uvm_api_mm_initialize successfully because the UVM + // file-descriptor has been released. + if (va_space->va_space_mm.state == UVM_VA_SPACE_MM_STATE_UNINITIALIZED) + uvm_va_space_mm_unregister(va_space); + UVM_ASSERT(!uvm_va_space_mm_alive(&va_space->va_space_mm)); uvm_mutex_lock(&g_uvm_global.global_lock); @@ -560,55 +563,10 @@ uvm_mutex_unlock(&g_uvm_global.global_lock); + uvm_kvfree(va_space->mapping); uvm_kvfree(va_space); } -NV_STATUS uvm_va_space_initialize(uvm_va_space_t *va_space, NvU64 flags) -{ - NV_STATUS status = NV_OK; - - if (flags & ~UVM_INIT_FLAGS_MASK) - return NV_ERR_INVALID_ARGUMENT; - - uvm_down_write_mmap_lock(current->mm); - uvm_va_space_down_write(va_space); - - if (atomic_read(&va_space->initialized)) { - // Already initialized - check if parameters match - if (flags != va_space->initialization_flags) - status = NV_ERR_INVALID_ARGUMENT; - } - else { - va_space->initialization_flags = flags; - - status = uvm_va_space_mm_register(va_space); - if (status != NV_OK) - goto out; - - status = uvm_hmm_va_space_initialize(va_space); - if (status != NV_OK) - goto unreg; - - // Use release semantics to match the acquire semantics in - // uvm_va_space_initialized. See that function for details. All - // initialization must be complete by this point. - atomic_set_release(&va_space->initialized, 1); - } - -out: - uvm_va_space_up_write(va_space); - uvm_up_write_mmap_lock(current->mm); - return status; - -unreg: - uvm_va_space_up_write(va_space); - uvm_up_write_mmap_lock(current->mm); - // See the comment in uvm_va_space_mm_unregister() for why this has to be - // called after releasing the locks. - uvm_va_space_mm_unregister(va_space); - return status; -} - void uvm_va_space_stop_all_user_channels(uvm_va_space_t *va_space) { uvm_gpu_va_space_t *gpu_va_space; @@ -700,6 +658,7 @@ uvm_va_range_t *va_range; uvm_gpu_t *gpu; uvm_gpu_t *other_gpu; + bool gpu_can_access_sysmem = true; status = uvm_gpu_retain_by_uuid(gpu_uuid, user_rm_device, &gpu); if (status != NV_OK) @@ -727,12 +686,9 @@ goto done; } - // Mixing Volta and Pascal GPUs is not supported on P9 systems. + // Mixing coherent and non-coherent GPUs is not supported for_each_va_space_gpu(other_gpu, va_space) { - if ((gpu->parent->sysmem_link >= UVM_GPU_LINK_NVLINK_2 && - other_gpu->parent->sysmem_link < UVM_GPU_LINK_NVLINK_2) || - (gpu->parent->sysmem_link < UVM_GPU_LINK_NVLINK_2 && - other_gpu->parent->sysmem_link >= UVM_GPU_LINK_NVLINK_2)) { + if (uvm_gpu_is_coherent(gpu->parent) != uvm_gpu_is_coherent(other_gpu->parent)) { status = NV_ERR_INVALID_DEVICE; goto done; } @@ -744,6 +700,17 @@ goto done; } + if (uvm_conf_computing_mode_enabled(gpu)) { + NvU32 gpu_index = uvm_id_gpu_index(gpu->id); + status = uvm_conf_computing_dma_buffer_alloc(&gpu->conf_computing.dma_buffer_pool, + &va_space->gpu_unregister_dma_buffer[gpu_index], + NULL); + if (status != NV_OK) + goto done; + + gpu_can_access_sysmem = false; + } + uvm_processor_mask_set(&va_space->registered_gpus, gpu->id); va_space->registered_gpus_table[uvm_id_gpu_index(gpu->id)] = gpu; @@ -757,15 +724,15 @@ processor_mask_array_set(va_space->has_native_atomics, gpu->id, gpu->id); // TODO: Bug 3252572: Support the new link type UVM_GPU_LINK_C2C - if (gpu->parent->sysmem_link >= UVM_GPU_LINK_NVLINK_1) { + if (gpu->parent->system_bus.link >= UVM_GPU_LINK_NVLINK_1) { processor_mask_array_set(va_space->has_nvlink, gpu->id, UVM_ID_CPU); processor_mask_array_set(va_space->has_nvlink, UVM_ID_CPU, gpu->id); } - if (gpu->parent->sysmem_link >= UVM_GPU_LINK_NVLINK_2) { + if (uvm_gpu_is_coherent(gpu->parent)) { processor_mask_array_set(va_space->has_native_atomics, gpu->id, UVM_ID_CPU); - if (gpu->parent->numa_info.enabled) { + if (gpu->mem_info.numa.enabled) { processor_mask_array_set(va_space->can_access, UVM_ID_CPU, gpu->id); processor_mask_array_set(va_space->accessible_from, gpu->id, UVM_ID_CPU); processor_mask_array_set(va_space->has_native_atomics, UVM_ID_CPU, gpu->id); @@ -776,8 +743,7 @@ processor_mask_array_set(va_space->can_access, gpu->id, gpu->id); processor_mask_array_set(va_space->accessible_from, gpu->id, gpu->id); - // All GPUs have direct access to sysmem, unless we're in SEV mode - if (!g_uvm_global.sev_enabled) { + if (gpu_can_access_sysmem) { processor_mask_array_set(va_space->can_access, gpu->id, UVM_ID_CPU); processor_mask_array_set(va_space->accessible_from, UVM_ID_CPU, gpu->id); } @@ -822,9 +788,9 @@ goto cleanup; } - if (gpu->parent->numa_info.enabled) { + if (gpu->mem_info.numa.enabled) { *numa_enabled = NV_TRUE; - *numa_node_id = (NvS32)uvm_gpu_numa_info(gpu)->node_id; + *numa_node_id = (NvS32)uvm_gpu_numa_node(gpu); } else { *numa_enabled = NV_FALSE; @@ -1032,6 +998,7 @@ return NV_ERR_NOT_COMPATIBLE; } + // TODO: Bug 3848497: Disable GPU Peer Mapping when HCC is enabled processor_mask_array_set(va_space->can_access, gpu0->id, gpu1->id); processor_mask_array_set(va_space->can_access, gpu1->id, gpu0->id); processor_mask_array_set(va_space->accessible_from, gpu0->id, gpu1->id); @@ -1057,8 +1024,8 @@ if (peer_caps->is_indirect_peer) { UVM_ASSERT(peer_caps->link_type >= UVM_GPU_LINK_NVLINK_2); - UVM_ASSERT(gpu0->parent->numa_info.enabled); - UVM_ASSERT(gpu1->parent->numa_info.enabled); + UVM_ASSERT(gpu0->mem_info.numa.enabled); + UVM_ASSERT(gpu1->mem_info.numa.enabled); processor_mask_array_set(va_space->indirect_peers, gpu0->id, gpu1->id); processor_mask_array_set(va_space->indirect_peers, gpu1->id, gpu0->id); @@ -1456,6 +1423,10 @@ return NV_ERR_INVALID_DEVICE; mm = uvm_va_space_mm_or_current_retain(va_space); + if (!mm) { + status = NV_ERR_PAGE_TABLE_NOT_AVAIL; + goto error_gpu_release; + } status = create_gpu_va_space(gpu, va_space, user_rm_va_space, &gpu_va_space); if (status != NV_OK) @@ -1558,6 +1529,8 @@ uvm_for_each_va_range_safe(va_range, va_range_next, va_space) uvm_va_range_remove_gpu_va_space(va_range, gpu_va_space, mm, deferred_free_list); + uvm_hmm_remove_gpu_va_space(va_space, gpu_va_space, mm); + uvm_deferred_free_object_add(deferred_free_list, &gpu_va_space->deferred_free, UVM_DEFERRED_FREE_OBJECT_GPU_VA_SPACE); @@ -1840,8 +1813,6 @@ bool uvm_va_space_pageable_mem_access_supported(uvm_va_space_t *va_space) { - UVM_ASSERT(uvm_va_space_initialized(va_space) == NV_OK); - // Any pageable memory access requires that we have mm_struct association // via va_space_mm. if (!uvm_va_space_mm_enabled(va_space)) @@ -2243,7 +2214,28 @@ if (do_sleep) uvm_tools_record_throttling_end(va_space, fault_addr, UVM_ID_CPU); - if (!is_hmm) { + if (is_hmm) { + // Note that normally we should find a va_block for the faulting + // address because the block had to be created when migrating a + // page to the GPU and a device private PTE inserted into the CPU + // page tables in order for migrate_to_ram() to be called. Not + // finding it means the PTE was remapped to a different virtual + // address with mremap() so create a new va_block if needed. + status = uvm_hmm_va_block_find_create(va_space, + fault_addr, + &service_context->block_context.hmm.vma, + &va_block); + if (status != NV_OK) + break; + + UVM_ASSERT(service_context->block_context.hmm.vma == vma); + status = uvm_hmm_migrate_begin(va_block); + if (status != NV_OK) + break; + + service_context->cpu_fault.vmf = vmf; + } + else { status = uvm_va_block_find_create_managed(va_space, fault_addr, &va_block); if (status != NV_OK) { UVM_ASSERT_MSG(status == NV_ERR_NO_MEMORY, "status: %s\n", nvstatusToString(status)); @@ -2256,9 +2248,12 @@ // Loop until thrashing goes away. status = uvm_va_block_cpu_fault(va_block, fault_addr, is_write, service_context); + + if (is_hmm) + uvm_hmm_migrate_finish(va_block); } while (status == NV_WARN_MORE_PROCESSING_REQUIRED); - if (status != NV_OK) { + if (status != NV_OK && !(is_hmm && status == NV_ERR_BUSY_RETRY)) { UvmEventFatalReason reason; reason = uvm_tools_status_to_fatal_fault_reason(status); @@ -2318,3 +2313,10 @@ return uvm_va_space_cpu_fault(va_space, vma, vmf, false); } + +vm_fault_t uvm_va_space_cpu_fault_hmm(uvm_va_space_t *va_space, + struct vm_area_struct *vma, + struct vm_fault *vmf) +{ + return uvm_va_space_cpu_fault(va_space, vma, vmf, true); +} diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/kernel-open/nvidia-uvm/uvm_va_space.h nvidia-open-gpu-kernel-modules-535.161.08/kernel-open/nvidia-uvm/uvm_va_space.h --- nvidia-open-gpu-kernel-modules-525.147.05/kernel-open/nvidia-uvm/uvm_va_space.h 2023-10-25 20:33:33.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/kernel-open/nvidia-uvm/uvm_va_space.h 2024-03-05 22:25:50.000000000 +0000 @@ -43,6 +43,7 @@ #include "uvm_test_ioctl.h" #include "uvm_ats.h" #include "uvm_va_space_mm.h" +#include "uvm_conf_computing.h" // uvm_deferred_free_object provides a mechanism for building and later freeing // a list of objects which are owned by a VA space, but can't be freed while the @@ -124,16 +125,6 @@ // because multiple threads may set it to 1 concurrently. atomic_t disallow_new_channels; - // On VMA destruction, the fault buffer needs to be flushed for all the GPUs - // registered in the VA space to avoid leaving stale entries of the VA range - // that is going to be destroyed. Otherwise, these fault entries can be - // attributed to new VA ranges reallocated at the same addresses. However, - // uvm_vm_close is called with mm->mmap_lock taken and we cannot take the ISR - // lock. Therefore, we use a flag no notify the GPU fault handler that the - // fault buffer needs to be flushed, before servicing the faults that belong - // to the va_space. - bool needs_fault_buffer_flush; - // Node for the deferred free list where this GPU VA space is stored upon // being unregistered. uvm_deferred_free_object_t deferred_free; @@ -189,7 +180,7 @@ // Kernel mapping structure passed to unmap_mapping range to unmap CPU PTEs // in this process. - struct address_space mapping; + struct address_space *mapping; // Storage in g_uvm_global.va_spaces.list struct list_head list_node; @@ -277,6 +268,11 @@ // stored in the VA space to avoid taking the global lock. uvm_cpu_gpu_affinity_t gpu_cpu_numa_affinity[UVM_ID_MAX_GPUS]; + // Unregistering a GPU may trigger memory eviction from the GPU to the CPU. + // This must happen without allocation, thus, a buffer is preallocated + // at GPU register and freed at GPU unregister. + uvm_conf_computing_dma_buffer_t *gpu_unregister_dma_buffer[UVM_ID_MAX_GPUS]; + // Array of GPU VA spaces uvm_gpu_va_space_t *gpu_va_spaces[UVM_ID_MAX_GPUS]; @@ -330,10 +326,6 @@ // lock is held in write mode. Access using uvm_va_space_block_context(). uvm_va_block_context_t va_block_context; - // UVM_INITIALIZE has been called. Until this is set, the VA space is - // inoperable. Use uvm_va_space_initialized() to check whether the VA space - // has been initialized. - atomic_t initialized; NvU64 initialization_flags; // The mm currently associated with this VA space, if any. @@ -350,6 +342,7 @@ struct { bool page_prefetch_enabled; + bool skip_migrate_vma; atomic_t migrate_vma_allocation_fail_nth; @@ -409,34 +402,7 @@ return uvm_va_space_get_gpu(va_space, id)->mem_info.size > 0; } -// Checks if the VA space has been fully initialized (UVM_INITIALIZE has been -// called). Returns NV_OK if so, NV_ERR_ILLEGAL_ACTION otherwise. -// -// Locking: No requirements. The VA space lock does NOT need to be held when -// calling this function, though it is allowed. -static NV_STATUS uvm_va_space_initialized(uvm_va_space_t *va_space) -{ - // The common case by far is for the VA space to have already been - // initialized. This combined with the fact that some callers may never hold - // the VA space lock means we don't want the VA space lock to be taken to - // perform this check. - // - // Instead of locks, we rely on acquire/release memory ordering semantics. - // The release is done at the end of uvm_api_initialize() when the - // UVM_INITIALIZE ioctl completes. That opens the gate for any other - // threads. - // - // Using acquire semantics as opposed to a normal read will add slight - // overhead to every entry point on platforms with relaxed ordering. Should - // that overhead become noticeable we could have UVM_INITIALIZE use - // on_each_cpu to broadcast memory barriers. - if (likely(atomic_read_acquire(&va_space->initialized))) - return NV_OK; - - return NV_ERR_ILLEGAL_ACTION; -} - -NV_STATUS uvm_va_space_create(struct inode *inode, struct file *filp); +NV_STATUS uvm_va_space_create(struct address_space *mapping, uvm_va_space_t **va_space_ptr, NvU64 flags); void uvm_va_space_destroy(uvm_va_space_t *va_space); // All VA space locking should be done with these wrappers. They're macros so @@ -497,10 +463,6 @@ uvm_mutex_unlock(&(__va_space)->serialize_writers_lock); \ } while (0) -// Initialize the VA space with the user-provided flags, enabling ioctls and -// mmap. -NV_STATUS uvm_va_space_initialize(uvm_va_space_t *va_space, NvU64 flags); - // Get a registered gpu by uuid. This restricts the search for GPUs, to those that // have been registered with a va_space. This returns NULL if the GPU is not present, or not // registered with the va_space. @@ -571,12 +533,30 @@ // VA space. Both GPUs must be registered in the VA space. bool uvm_va_space_peer_enabled(uvm_va_space_t *va_space, uvm_gpu_t *gpu1, uvm_gpu_t *gpu2); +// Returns the va_space this file points to. Returns NULL if this file +// does not point to a va_space. +static uvm_va_space_t *uvm_fd_va_space(struct file *filp) +{ + uvm_va_space_t *va_space; + uvm_fd_type_t type; + + type = uvm_fd_type(filp, (void **) &va_space); + if (type != UVM_FD_VA_SPACE) + return NULL; + + return va_space; +} + static uvm_va_space_t *uvm_va_space_get(struct file *filp) { + uvm_fd_type_t fd_type; + uvm_va_space_t *va_space; + + fd_type = uvm_fd_type(filp, (void **)&va_space); UVM_ASSERT(uvm_file_is_nvidia_uvm(filp)); - UVM_ASSERT_MSG(filp->private_data != NULL, "filp: 0x%llx", (NvU64)filp); + UVM_ASSERT_MSG(fd_type == UVM_FD_VA_SPACE, "filp: 0x%llx", (NvU64)filp); - return (uvm_va_space_t *)filp->private_data; + return va_space; } static uvm_va_block_context_t *uvm_va_space_block_context(uvm_va_space_t *va_space, struct mm_struct *mm) @@ -788,9 +768,7 @@ return NULL; for_each_va_space_gpu(gpu, va_space) { - UVM_ASSERT(gpu->parent->numa_info.enabled); - - if (uvm_gpu_numa_info(gpu)->node_id == node_id) + if (uvm_gpu_numa_node(gpu) == node_id) return gpu; } @@ -868,4 +846,20 @@ struct vm_area_struct *vma, struct vm_fault *vmf); +// Handle a CPU fault in the given VA space for a HMM allocation, +// performing any operations necessary to establish a coherent CPU mapping +// (migrations, cache invalidates, etc.). +// +// Locking: +// - vma->vm_mm->mmap_lock must be held in at least read mode. Note, that +// might not be the same as current->mm->mmap_lock. +// Returns: +// VM_FAULT_NOPAGE: if page was faulted in OK +// (possibly or'ed with VM_FAULT_MAJOR if a migration was needed). +// VM_FAULT_OOM: if system memory wasn't available. +// VM_FAULT_SIGBUS: if a CPU mapping to fault_addr cannot be accessed. +vm_fault_t uvm_va_space_cpu_fault_hmm(uvm_va_space_t *va_space, + struct vm_area_struct *vma, + struct vm_fault *vmf); + #endif // __UVM_VA_SPACE_H__ diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/kernel-open/nvidia-uvm/uvm_va_space_mm.c nvidia-open-gpu-kernel-modules-535.161.08/kernel-open/nvidia-uvm/uvm_va_space_mm.c --- nvidia-open-gpu-kernel-modules-525.147.05/kernel-open/nvidia-uvm/uvm_va_space_mm.c 2023-10-25 20:33:33.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/kernel-open/nvidia-uvm/uvm_va_space_mm.c 2024-03-05 22:25:50.000000000 +0000 @@ -30,78 +30,62 @@ #include "uvm_test.h" #include "uvm_test_ioctl.h" -#if defined(NV_LINUX_SCHED_MM_H_PRESENT) -#include -#elif defined(NV_LINUX_SCHED_H_PRESENT) -#include -#endif - // // This comment block describes some implementation rationale. See the header // for the API descriptions. // // ========================= Retain count vs mm_users ========================== // -// We use two methods to guarantee the mm is available and won't be destroyed. -// -// On the call paths where mmput() can be called, we call -// uvm_va_space_mm_or_current_retain() which calls mmget_not_zero(). This -// prevents mm teardown and avoids races with uvm_va_space_mm_shutdown() since -// it prevents mmput() -> __mmput() -> exit_mmap() -> mmu_notifier_release() -> -// uvm_va_space_mm_shutdown() until uvm_va_space_mm_or_current_release(), and -// we guarantee that we can't call uvm_va_space_mm_unregister() -> -// mmu_notifier_unregister() -> uvm_va_space_mm_shutdown() path when someone is -// about to call uvm_va_space_mm_or_current_retain(). -// Kernel calls like mmu_interval_notifier_insert() require mm_users to be -// greater than 0. In general, these are the ioctl paths. -// -// On the replayable GPU fault handling path, we need the mm to be able to -// service faults in the window when mm_users == 0 but mmu_notifier_release() -// hasn't yet been called. We can't call mmput() because it may result in -// exit_mmap(), which could result in RM calls and VA space destroy. Those need -// to wait for the GPU fault handler to finish, so on that path we use an -// internal retained reference count and wait queue. When the mm is disabled -// via mmu_notifier_release(), we use the wait queue to wait for the reference -// count to go to 0. -// We also use this path for older Linux kernels where mm_users > 0 isn't -// required. +// To guarantee the mm is available and won't be destroyed we require +// userspace to open a second file descriptor (uvm_mm_fd) and +// initialize it with uvm_api_mm_initialize(). During initialization +// we take a mm_users reference to ensure the mm remains valid until +// the file descriptor is closed. +// +// To ensure userspace can't close the file descriptor and drop the +// mm_users refcount while it is in use threads must call either +// uvm_va_space_mm_retain() or uvm_va_space_mm_or_current_retain() to +// increment the retained count. This also checks that userspace has +// initialized the uvm_mm_fd and therefore holds a valid pagetable +// pin. +// +// Closing uvm_mm_fd will call uvm_va_space_mm_shutdown() prior to +// mmput() which ensures there are no active users of the mm. This +// indirection is required because not all threads can call mmput() +// directly. In particular the replayable GPU fault handling path +// can't call mmput() because it may result in exit_mmap() which could +// result in RM calls and VA space destroy and those need to wait for +// the GPU fault handler to finish. // // ============================ Handling mm teardown =========================== // -// mmu_notifiers call the mm release callback both when the mm is really getting -// shut down, and whenever mmu_notifier_unregister is called. This has several -// consequences, including that these two paths can race. If they do race, they -// wait for each other to finish (real teardown of the mm won't start until the -// mmu_notifier_unregister's callback has returned, and mmu_notifier_unregister -// won't return until the mm release callback has returned). -// -// When the mm is really getting torn down, uvm_va_space_mm_shutdown is expected -// to stop all GPU memory accesses to that mm and stop servicing faults in that -// mm. This essentially shuts down the VA space for new work. The VA space -// object remains valid for most teardown ioctls until the file is closed, -// because it's legal for the associated process to die then for another process -// with a reference on the file to perform the unregisters or associated ioctls. -// This is particularly true for tools users. +// When the process is exiting we will get notified either via an +// explict close of uvm_mm_fd or implicitly as part of +// exit_files(). We are guaranteed to get this call because we don't +// allow mmap on uvm_mm_fd, and the userspace pagetables (mm_users) +// are guaranteed to exist because we hold a mm_users refcount +// which is released as part of file close. +// +// This allows any outstanding GPU faults to be processed. To prevent +// new faults occurring uvm_va_space_mm_shutdown() is called to stop +// all GPU memory accesses to the mm. Once all GPU memory has been +// stopped no new retainers of the va_space will be allowed and the +// mm_users reference will be dropped, potentially tearing down the mm +// and associated pagetables. +// +// This essentially shuts down the VA space for new work. The VA space +// object remains valid for most teardown ioctls until the file is +// closed, because it's legal for the associated process to die then +// for another process with a reference on the file to perform the +// unregisters or associated ioctls. This is particularly true for +// tools users. // // An exception to the above is UvmUnregisterChannel. Since channels are // completely removed from the VA space on mm teardown, later channel // unregisters will fail to find the handles and will return an error. // -// The UVM driver will only call mmu_notifier_unregister during VA space destroy -// (file close). -// -// Here is a table of the various teardown scenarios: -// -// Can race with -// Scenario mm teardown -// ----------------------------------------------------------------------------- -// 1) Process exit (mm teardown, file open) - -// 2) Explicit file close in original mm No -// 3) Explicit file close in different mm Yes -// 4) Implicit file close (exit) in original mm No -// 5) Implicit file close (exit) in different mm Yes -// -// At a high level, the sequence of operations to perform during mm teardown is: +// At a high level, the sequence of operations to perform prior to mm +// teardown is: // // 1) Stop all channels // - Prevents new faults and accesses on non-MPS @@ -121,7 +105,7 @@ // the case of MPS, cancel real faults after. // 4) UnsetPageDir // - Prevents new accesses on MPS -// 5) Mark the va_space_mm as dead +// 5) Mark the va_space_mm as released // - Prevents new retainers from using the mm. There won't be any more on // the fault handling paths, but there could be others in worker threads. // @@ -170,7 +154,7 @@ // // ============================================================================= -#define UVM_VA_SPACE_MM_SHUTDOWN_DELAY_MAX_MS 100 +static void uvm_va_space_mm_shutdown(uvm_va_space_t *va_space); static int uvm_enable_va_space_mm = 1; module_param(uvm_enable_va_space_mm, int, S_IRUGO); @@ -195,22 +179,7 @@ return uvm_va_space_mm_enabled_system(); } -static void uvm_va_space_mm_shutdown(uvm_va_space_t *va_space); - -#if !defined(NV_MMGET_NOT_ZERO_PRESENT) -static bool mmget_not_zero(struct mm_struct *mm) -{ - return atomic_inc_not_zero(&mm->mm_users); -} -#endif - #if UVM_CAN_USE_MMU_NOTIFIERS() - - static void uvm_mmput(struct mm_struct *mm) - { - mmput(mm); - } - static uvm_va_space_t *get_va_space(struct mmu_notifier *mn) { // This may be called without a thread context present, so be careful @@ -218,11 +187,6 @@ return container_of(mn, uvm_va_space_t, va_space_mm.mmu_notifier); } - static void uvm_mmu_notifier_release(struct mmu_notifier *mn, struct mm_struct *mm) - { - UVM_ENTRY_VOID(uvm_va_space_mm_shutdown(get_va_space(mn))); - } - static void uvm_mmu_notifier_invalidate_range_ats(struct mmu_notifier *mn, struct mm_struct *mm, unsigned long start, @@ -249,15 +213,15 @@ UVM_ENTRY_VOID(uvm_ats_invalidate(get_va_space(mn), start, end)); } - static struct mmu_notifier_ops uvm_mmu_notifier_ops_release = - { - .release = uvm_mmu_notifier_release, - }; - static struct mmu_notifier_ops uvm_mmu_notifier_ops_ats = { - .release = uvm_mmu_notifier_release, +#if defined(NV_MMU_NOTIFIER_OPS_HAS_INVALIDATE_RANGE) .invalidate_range = uvm_mmu_notifier_invalidate_range_ats, +#elif defined(NV_MMU_NOTIFIER_OPS_HAS_ARCH_INVALIDATE_SECONDARY_TLBS) + .arch_invalidate_secondary_tlbs = uvm_mmu_notifier_invalidate_range_ats, +#else + #error One of invalidate_range/arch_invalid_secondary must be present +#endif }; static int uvm_mmu_notifier_register(uvm_va_space_mm_t *va_space_mm) @@ -265,11 +229,7 @@ UVM_ASSERT(va_space_mm->mm); uvm_assert_mmap_lock_locked_write(va_space_mm->mm); - if (UVM_ATS_IBM_SUPPORTED_IN_DRIVER() && g_uvm_global.ats.enabled) - va_space_mm->mmu_notifier.ops = &uvm_mmu_notifier_ops_ats; - else - va_space_mm->mmu_notifier.ops = &uvm_mmu_notifier_ops_release; - + va_space_mm->mmu_notifier.ops = &uvm_mmu_notifier_ops_ats; return __mmu_notifier_register(&va_space_mm->mmu_notifier, va_space_mm->mm); } @@ -278,11 +238,6 @@ mmu_notifier_unregister(&va_space_mm->mmu_notifier, va_space_mm->mm); } #else - static void uvm_mmput(struct mm_struct *mm) - { - UVM_ASSERT(0); - } - static int uvm_mmu_notifier_register(uvm_va_space_mm_t *va_space_mm) { UVM_ASSERT(0); @@ -303,26 +258,43 @@ uvm_assert_mmap_lock_locked_write(current->mm); uvm_assert_rwsem_locked_write(&va_space->lock); - UVM_ASSERT(uvm_va_space_initialized(va_space) != NV_OK); + va_space_mm->state = UVM_VA_SPACE_MM_STATE_UNINITIALIZED; + if (!uvm_va_space_mm_enabled(va_space)) return NV_OK; UVM_ASSERT(!va_space_mm->mm); va_space_mm->mm = current->mm; + uvm_mmgrab(va_space_mm->mm); // We must be prepared to handle callbacks as soon as we make this call, // except for ->release() which can't be called since the mm belongs to // current. - ret = uvm_mmu_notifier_register(va_space_mm); - if (ret) { - // Inform uvm_va_space_mm_unregister() that it has nothing to do. - va_space_mm->mm = NULL; - return errno_to_nv_status(ret); + if (UVM_ATS_IBM_SUPPORTED_IN_DRIVER() && g_uvm_global.ats.enabled) { + ret = uvm_mmu_notifier_register(va_space_mm); + if (ret) { + // Inform uvm_va_space_mm_unregister() that it has nothing to do. + uvm_mmdrop(va_space_mm->mm); + va_space_mm->mm = NULL; + return errno_to_nv_status(ret); + } } - uvm_spin_lock(&va_space_mm->lock); - va_space_mm->alive = true; - uvm_spin_unlock(&va_space_mm->lock); + if ((UVM_IS_CONFIG_HMM() || UVM_ATS_PREFETCH_SUPPORTED()) && uvm_va_space_pageable_mem_access_supported(va_space)) { + #if UVM_CAN_USE_MMU_NOTIFIERS() + // Initialize MMU interval notifiers for this process. This allows + // mmu_interval_notifier_insert() to be called without holding the + // mmap_lock for write. + // Note: there is no __mmu_notifier_unregister(), this call just + // allocates memory which is attached to the mm_struct and freed + // when the mm_struct is freed. + ret = __mmu_notifier_register(NULL, current->mm); + if (ret) + return errno_to_nv_status(ret); + #else + UVM_ASSERT(0); + #endif + } return NV_OK; } @@ -331,25 +303,35 @@ { uvm_va_space_mm_t *va_space_mm = &va_space->va_space_mm; - // We can't hold the VA space lock or mmap_lock across this function since - // mmu_notifier_unregister() may trigger uvm_va_space_mm_shutdown(), which - // takes those locks and also waits for other threads which may take those - // locks. + // We can't hold the VA space lock or mmap_lock because + // uvm_va_space_mm_shutdown() waits for retainers which may take + // these locks. uvm_assert_unlocked_order(UVM_LOCK_ORDER_MMAP_LOCK); uvm_assert_unlocked_order(UVM_LOCK_ORDER_VA_SPACE); + uvm_va_space_mm_shutdown(va_space); + UVM_ASSERT(va_space_mm->retained_count == 0); + + // Only happens if uvm_va_space_mm_register() fails if (!va_space_mm->mm) return; - UVM_ASSERT(uvm_va_space_mm_enabled(va_space)); - uvm_mmu_notifier_unregister(va_space_mm); + // At this point the mm is still valid because uvm_mm_release() + // hasn't yet called mmput(). uvm_hmm_va_space_destroy() will kill + // all the va_blocks along with any associated gpu_chunks, so we + // need to make sure these chunks are free. However freeing them + // requires a valid mm so we can call migrate_vma_setup(), so we + // do that here. + // TODO: Bug 3902536: [UVM-HMM] add code to migrate GPU memory + // without having a va_block + if (uvm_hmm_is_enabled(va_space)) + uvm_hmm_evict_va_blocks(va_space); - // We're guaranteed that upon return from mmu_notifier_unregister(), - // uvm_va_space_mm_shutdown() will have been called (though perhaps not by - // this thread). Therefore all retainers have been flushed. - UVM_ASSERT(!va_space_mm->alive); - UVM_ASSERT(va_space_mm->retained_count == 0); - va_space_mm->mm = NULL; + if (uvm_va_space_mm_enabled(va_space)) { + if (UVM_ATS_IBM_SUPPORTED_IN_DRIVER() && g_uvm_global.ats.enabled) + uvm_mmu_notifier_unregister(va_space_mm); + uvm_mmdrop(va_space_mm->mm); + } } struct mm_struct *uvm_va_space_mm_retain(uvm_va_space_t *va_space) @@ -357,18 +339,24 @@ uvm_va_space_mm_t *va_space_mm = &va_space->va_space_mm; struct mm_struct *mm = NULL; - UVM_ASSERT(uvm_va_space_initialized(va_space) == NV_OK); - if (!uvm_va_space_mm_enabled(va_space)) return NULL; uvm_spin_lock(&va_space_mm->lock); - if (va_space_mm->alive) { - ++va_space_mm->retained_count; - mm = va_space_mm->mm; - UVM_ASSERT(mm); - } + if (!uvm_va_space_mm_alive(va_space_mm)) + goto out; + + ++va_space_mm->retained_count; + + mm = va_space_mm->mm; + UVM_ASSERT(mm); + +out: + + // uvm_api_mm_init() holds a reference + if (mm) + UVM_ASSERT(atomic_read(&mm->mm_users) > 0); uvm_spin_unlock(&va_space_mm->lock); @@ -377,31 +365,30 @@ struct mm_struct *uvm_va_space_mm_or_current_retain(uvm_va_space_t *va_space) { - uvm_va_space_mm_t *va_space_mm = &va_space->va_space_mm; - // We should only attempt to use current->mm from a user thread UVM_ASSERT(!(current->flags & PF_KTHREAD)); - UVM_ASSERT(uvm_va_space_initialized(va_space) == NV_OK); - // current->mm is NULL when we're in process teardown. In that case it // doesn't make sense to use any mm. if (!current->mm) return NULL; - // If the va_space_mm matches current->mm then it would be safe but sub- - // optimal to call mmget_not_zero(). current->mm is always valid to - // use when non-NULL so there is no need to retain it. - if (!uvm_va_space_mm_enabled(va_space) || va_space_mm->mm == current->mm) + // If !uvm_va_space_mm_enabled() we use current->mm on the ioctl + // paths. In that case we don't need to mmget(current->mm) because + // the current thread mm is always valid. On + // uvm_va_space_mm_enabled() systems we skip trying to retain the + // mm if it is current->mm because userspace may not have + // initialised the mm fd but UVM callers on the ioctl path still + // assume retaining current->mm will succeed. + if (!uvm_va_space_mm_enabled(va_space)) return current->mm; - return mmget_not_zero(va_space_mm->mm) ? va_space_mm->mm : NULL; + return uvm_va_space_mm_retain(va_space); } void uvm_va_space_mm_release(uvm_va_space_t *va_space) { uvm_va_space_mm_t *va_space_mm = &va_space->va_space_mm; - bool do_wake = false; UVM_ASSERT(uvm_va_space_mm_enabled(va_space)); @@ -414,84 +401,26 @@ --va_space_mm->retained_count; // If we're the last retainer on a dead mm, signal any potential waiters - if (va_space_mm->retained_count == 0 && !va_space_mm->alive) - do_wake = true; + if (va_space_mm->retained_count == 0 && !uvm_va_space_mm_alive(va_space_mm)) { + uvm_spin_unlock(&va_space_mm->lock); - uvm_spin_unlock(&va_space_mm->lock); - - // There could be multiple threads in uvm_va_space_mm_shutdown() waiting on - // us, so we have to wake up all waiters. - if (do_wake) - wake_up_all(&va_space_mm->last_retainer_wait_queue); + // There could be a thread in uvm_va_space_mm_shutdown() + // waiting on us, so wake it up. + wake_up(&va_space_mm->last_retainer_wait_queue); + } + else { + uvm_spin_unlock(&va_space_mm->lock); + } } void uvm_va_space_mm_or_current_release(uvm_va_space_t *va_space, struct mm_struct *mm) { - // We can't hold the VA space lock or mmap_lock across this function since - // mmput() may trigger uvm_va_space_mm_shutdown(), which takes those locks - // and also waits for other threads which may take those locks. - uvm_assert_unlocked_order(UVM_LOCK_ORDER_MMAP_LOCK); - uvm_assert_unlocked_order(UVM_LOCK_ORDER_VA_SPACE); - - if (mm && mm != current->mm) - uvm_mmput(mm); -} - -static void uvm_va_space_mm_shutdown_delay(uvm_va_space_t *va_space) -{ - uvm_va_space_mm_t *va_space_mm = &va_space->va_space_mm; - NvU64 start_time; - int num_threads; - bool timed_out = false; - - if (!va_space_mm->test.delay_shutdown) + if (!uvm_va_space_mm_enabled(va_space) || !mm) return; - start_time = NV_GETTIME(); - - num_threads = atomic_inc_return(&va_space_mm->test.num_mm_shutdown_threads); - UVM_ASSERT(num_threads > 0); - - if (num_threads == 1) { - // Wait for another thread to arrive unless we time out - while (atomic_read(&va_space_mm->test.num_mm_shutdown_threads) == 1) { - if (NV_GETTIME() - start_time >= 1000*1000*UVM_VA_SPACE_MM_SHUTDOWN_DELAY_MAX_MS) { - timed_out = true; - break; - } - } - - if (va_space_mm->test.verbose) - UVM_TEST_PRINT("Multiple threads: %d\n", !timed_out); - } - - // No need to decrement num_mm_shutdown_threads since this va_space_mm is - // being shut down. + uvm_va_space_mm_release(va_space); } -// Handles the va_space's mm being torn down while the VA space still exists. -// This function won't return until all in-flight retainers have called -// uvm_va_space_mm_release(). Subsequent calls to uvm_va_space_mm_retain() will -// return NULL. -// -// uvm_va_space_mm_unregister() must still be called. It is guaranteed that -// uvm_va_space_mm_shutdown() will not be called after -// uvm_va_space_mm_unregister() returns, though they may execute concurrently. -// If so, uvm_va_space_mm_unregister() will not return until -// uvm_va_space_mm_shutdown() is done. -// -// After this call returns the VA space is essentially dead. GPUs cannot make -// any new memory accesses in registered GPU VA spaces, and no more GPU faults -// which are attributed to this VA space will arrive. Additionally, no more -// registration within the VA space is allowed (GPU, GPU VA space, or channel). -// -// The requirements for this callback are that, once we return, the GPU and -// driver are completely done using the associated mm_struct. This includes: -// -// 1) GPUs will not issue any more memory accesses under this mm -// 2) [ATS only] GPUs will not issue any more ATRs under this mm -// 3) The driver will not ask the kernel to service faults on this mm -// static void uvm_va_space_mm_shutdown(uvm_va_space_t *va_space) { uvm_va_space_mm_t *va_space_mm = &va_space->va_space_mm; @@ -500,29 +429,6 @@ uvm_global_processor_mask_t gpus_to_flush; LIST_HEAD(deferred_free_list); - // The mm must not have been torn down completely yet, but it may have been - // marked as dead by a concurrent thread. - UVM_ASSERT(uvm_va_space_mm_enabled(va_space)); - UVM_ASSERT(va_space_mm->mm); - - // Inject a delay for testing if requested - uvm_va_space_mm_shutdown_delay(va_space); - - // There can be at most two threads here concurrently: - // - // 1) Thread A in process teardown of the original process - // - // 2) Thread B must be in the file close path of another process (either - // implicit or explicit), having already stopped all GPU accesses and - // having called uvm_va_space_mm_unregister. - // - // This corresponds to scenario #5 in the mm teardown block comment at the - // top of the file. We serialize between these threads with the VA space - // lock, but otherwise don't have any special handling: both threads will - // execute the full teardown sequence below. Also, remember that the threads - // won't return to their callers until both threads have returned from this - // function (following the rules for mmu_notifier_unregister). - uvm_va_space_down_write(va_space); // Prevent future registrations of any kind. We'll be iterating over all @@ -550,9 +456,9 @@ uvm_global_mask_retain(&gpus_to_flush); uvm_va_space_up_write(va_space); - // Flush the fault buffer on all GPUs. This will avoid spurious cancels - // of stale pending translated faults after we clear va_space_mm->alive - // later. + // Flush the fault buffer on all GPUs. This will avoid spurious + // cancels of stale pending translated faults after we set + // UVM_VA_SPACE_MM_STATE_RELEASED later. for_each_global_gpu_in_mask(gpu, &gpus_to_flush) uvm_gpu_fault_buffer_flush(gpu); @@ -598,7 +504,7 @@ // Now that there won't be any new GPU faults, prevent subsequent retainers // from accessing this mm. uvm_spin_lock(&va_space_mm->lock); - va_space_mm->alive = false; + va_space_mm->state = UVM_VA_SPACE_MM_STATE_RELEASED; uvm_spin_unlock(&va_space_mm->lock); // Finish channel destroy. This can be done at any point after detach as @@ -646,7 +552,7 @@ uvm_mutex_lock(&g_uvm_global.va_spaces.lock); list_for_each_entry(va_space, &g_uvm_global.va_spaces.list, list_node) { - if ((uintptr_t)va_space == params->va_space_ptr && uvm_va_space_initialized(va_space) == NV_OK) { + if ((uintptr_t)va_space == params->va_space_ptr) { mm = uvm_va_space_mm_retain(va_space); break; } @@ -671,26 +577,6 @@ return status; } -NV_STATUS uvm_test_va_space_mm_delay_shutdown(UVM_TEST_VA_SPACE_MM_DELAY_SHUTDOWN_PARAMS *params, struct file *filp) -{ - uvm_va_space_t *va_space = uvm_va_space_get(filp); - uvm_va_space_mm_t *va_space_mm = &va_space->va_space_mm; - NV_STATUS status = NV_ERR_PAGE_TABLE_NOT_AVAIL; - - uvm_va_space_down_write(va_space); - - if (uvm_va_space_mm_retain(va_space)) { - va_space_mm->test.delay_shutdown = true; - va_space_mm->test.verbose = params->verbose; - uvm_va_space_mm_release(va_space); - status = NV_OK; - } - - uvm_va_space_up_write(va_space); - - return status; -} - NV_STATUS uvm_test_va_space_mm_or_current_retain(UVM_TEST_VA_SPACE_MM_OR_CURRENT_RETAIN_PARAMS *params, struct file *filp) { @@ -709,13 +595,9 @@ status = NV_ERR_INVALID_ARGUMENT; } - if (status == NV_OK) { - if (params->sleep_us) + if (status == NV_OK && params->sleep_us) usleep_range(params->sleep_us, params->sleep_us + 1000); - params->mm_users = atomic_read(&mm->mm_users); - } - uvm_va_space_mm_or_current_release(va_space, mm); return status; diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/kernel-open/nvidia-uvm/uvm_va_space_mm.h nvidia-open-gpu-kernel-modules-535.161.08/kernel-open/nvidia-uvm/uvm_va_space_mm.h --- nvidia-open-gpu-kernel-modules-525.147.05/kernel-open/nvidia-uvm/uvm_va_space_mm.h 2023-10-25 20:33:33.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/kernel-open/nvidia-uvm/uvm_va_space_mm.h 2024-03-05 22:25:50.000000000 +0000 @@ -32,27 +32,50 @@ #include +#if defined(NV_LINUX_SCHED_MM_H_PRESENT) +#include +#elif defined(NV_LINUX_SCHED_H_PRESENT) +#include +#endif + +typedef enum +{ + // The va_space_mm has not yet been initialized by + // uvm_api_mm_initialize(). Only current->mm can be retained for + // !uvm_va_space_mm_enabled() VA spaces. + UVM_VA_SPACE_MM_STATE_UNINITIALIZED, + + // The va_space_mm has been initialized and if this is a + // uvm_va_space_mm_enabled() space CPU user space page tables are + // valid due to holding a mm_struct reference. However the GPU VA + // space may be in the process of being torn down. + UVM_VA_SPACE_MM_STATE_ALIVE, + + // The va_space_mm has been released. There is no longer any + // mm_struct associated with this va_space_mm and CPU page tables + // may have been released. GPU VA state has been destroyed. + UVM_VA_SPACE_MM_STATE_RELEASED, +} uvm_va_space_mm_state_t; + struct uvm_va_space_mm_struct { - // The mm currently associated with this VA space. Most callers shouldn't - // access this directly, but should instead use uvm_va_space_mm_retain()/ - // uvm_va_space_mm_release(). - // - // The pointer itself is valid between uvm_va_space_mm_register() and - // uvm_va_space_mm_unregister(), but should only be considered usable when - // retained or current. - struct mm_struct *mm; + // The mm currently associated with this VA space. Most callers shouldn't + // access this directly, but should instead use uvm_va_space_mm_retain()/ + // uvm_va_space_mm_release(). + // + // The pointer itself is valid when the va_space_mm state is + // UVM_VA_SPACE_MM_STATE_ALIVE, but should only be considered usable + // when retained or current. + struct mm_struct *mm; #if UVM_CAN_USE_MMU_NOTIFIERS() struct mmu_notifier mmu_notifier; #endif - // Lock protecting the alive and retained_count fields. + // Lock protecting the state and retained_count fields. uvm_spinlock_t lock; - // Whether the mm is usable. uvm_va_space_mm_register() marks the mm as - // alive and uvm_va_space_mm_shutdown() marks it as dead. - bool alive; + uvm_va_space_mm_state_t state; // Refcount for uvm_va_space_mm_retain()/uvm_va_space_mm_release() NvU32 retained_count; @@ -60,22 +83,13 @@ // Wait queue for threads waiting for retainers to finish (retained_count // going to 0 when not alive). wait_queue_head_t last_retainer_wait_queue; - - // State which is only injected by test ioctls - struct - { - // Whether uvm_va_space_mm_shutdown() should do a timed wait for other - // threads to arrive. - bool delay_shutdown; - - bool verbose; - - // Number of threads which have called uvm_va_space_mm_shutdown(). Only - // used when delay_shutdown is true. - atomic_t num_mm_shutdown_threads; - } test; }; +static bool uvm_va_space_mm_alive(struct uvm_va_space_mm_struct *va_space_mm) +{ + return va_space_mm->state == UVM_VA_SPACE_MM_STATE_ALIVE; +} + // Whether the system can support creating an association between a VA space and // an mm. bool uvm_va_space_mm_enabled_system(void); @@ -94,18 +108,24 @@ // Locking: mmap_lock and the VA space lock must both be held for write. NV_STATUS uvm_va_space_mm_register(uvm_va_space_t *va_space); -// De-associate the mm from the va_space. This function won't return until all -// in-flight retainers have called uvm_va_space_mm_release(). -// uvm_va_space_mm_retain() and friends must not be called after this returns. -// -// This function may invoke uvm_va_space_mm_shutdown() so the caller must not -// hold either mmap_lock or the VA space lock. Since this API must provide the -// same guarantees as uvm_va_space_mm_shutdown(), the caller must also guarantee -// prior to calling this function that all GPUs in this VA space have stopped -// making accesses under this mm and will not be able to start again under that -// VA space. +// Handles the va_space's mm being torn down while the VA space still exists. +// This function won't return until all in-flight retainers have called +// uvm_va_space_mm_release(). Subsequent calls to uvm_va_space_mm_retain() will +// return NULL. +// +// After this call returns the VA space is essentially dead. GPUs cannot make +// any new memory accesses in registered GPU VA spaces, and no more GPU faults +// which are attributed to this VA space will arrive. Additionally, no more +// registration within the VA space is allowed (GPU, GPU VA space, or channel). +// +// The requirements for this call are that, once we return, the GPU and +// driver are completely done using the associated mm_struct. This includes: +// +// 1) GPUs will not issue any more memory accesses under this mm +// 2) [ATS only] GPUs will not issue any more ATRs under this mm +// 3) The driver will not ask the kernel to service faults on this mm // -// Locking: This function may take both mmap_lock and the VA space lock. +// Locking: This function will take both mmap_lock and the VA space lock. void uvm_va_space_mm_unregister(uvm_va_space_t *va_space); // Retains the current mm registered with this VA space. If no mm is currently @@ -114,26 +134,23 @@ // (locking mmap_lock, find_vma, get_user_pages, cgroup-accounted allocations, // etc) until uvm_va_space_mm_release() is called. // -// Please, note that a retained mm could have mm->users == 0. +// A retained mm is guaranteed to have mm->users >= 1. // // It is NOT necessary to hold the VA space lock when calling this function. struct mm_struct *uvm_va_space_mm_retain(uvm_va_space_t *va_space); -// Similar to uvm_va_space_mm_retain(), but falls back to returning current->mm -// when there is no mm registered with the VA space (that is, -// uvm_va_space_mm_enabled() would return false). This is both a convenience and -// an optimization of the common case in which current->mm == va_space_mm. -// uvm_va_space_mm_or_current_release() must be called to release the mm, and it -// must be called from the same thread which called +// Similar to uvm_va_space_mm_retain(), but falls back to returning +// current->mm when there is no mm registered with the VA space (that +// is, uvm_va_space_mm_enabled() would return false). +// uvm_va_space_mm_or_current_release() must be called to release the +// mm, and it must be called from the same thread which called // uvm_va_space_mm_or_current_retain(). // // If a non-NULL mm is returned, the guarantees described by -// uvm_va_space_mm_retain() apply. Unlike uvm_va_space_mm_retain() however, -// mm_users is guaranteed to be greater than 0 until -// uvm_va_space_mm_or_current_release(). -// If uvm_va_space_mm_enabled() is false, the caller is responsible for -// validating that the returned mm matches the desired mm before performing an -// operation such as vm_insert_page(). See uvm_va_range_vma_check(). +// uvm_va_space_mm_retain() apply. If uvm_va_space_mm_enabled() is +// false, the caller is responsible for validating that the returned +// mm matches the desired mm before performing an operation such as +// vm_insert_page(). See uvm_va_range_vma_check(). // // This should not be called from a kernel thread. struct mm_struct *uvm_va_space_mm_or_current_retain(uvm_va_space_t *va_space); @@ -185,8 +202,50 @@ } } +#if !defined(NV_MMGET_NOT_ZERO_PRESENT) +static bool mmget_not_zero(struct mm_struct *mm) +{ + return atomic_inc_not_zero(&mm->mm_users); +} +#endif + +#if UVM_CAN_USE_MMU_NOTIFIERS() +static void uvm_mmput(struct mm_struct *mm) +{ + mmput(mm); +} + +static void uvm_mmgrab(struct mm_struct *mm) +{ +#if defined(NV_MMGRAB_PRESENT) + mmgrab(mm); +#else + atomic_inc(&mm->mm_count); +#endif +} + +static void uvm_mmdrop(struct mm_struct *mm) +{ + mmdrop(mm); +} +#else +static void uvm_mmput(struct mm_struct *mm) +{ + UVM_ASSERT(0); +} + +static void uvm_mmgrab(struct mm_struct *mm) +{ + UVM_ASSERT(0); +} + +static void uvm_mmdrop(struct mm_struct *mm) +{ + UVM_ASSERT(0); +} +#endif + NV_STATUS uvm_test_va_space_mm_retain(UVM_TEST_VA_SPACE_MM_RETAIN_PARAMS *params, struct file *filp); -NV_STATUS uvm_test_va_space_mm_delay_shutdown(UVM_TEST_VA_SPACE_MM_DELAY_SHUTDOWN_PARAMS *params, struct file *filp); NV_STATUS uvm_test_va_space_mm_or_current_retain(UVM_TEST_VA_SPACE_MM_OR_CURRENT_RETAIN_PARAMS *params, struct file *filp); diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/kernel-open/nvidia-uvm/uvm_volta.c nvidia-open-gpu-kernel-modules-535.161.08/kernel-open/nvidia-uvm/uvm_volta.c --- nvidia-open-gpu-kernel-modules-525.147.05/kernel-open/nvidia-uvm/uvm_volta.c 2023-10-25 20:33:38.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/kernel-open/nvidia-uvm/uvm_volta.c 2024-03-05 22:25:56.000000000 +0000 @@ -1,5 +1,5 @@ /******************************************************************************* - Copyright (c) 2016-2021 NVIDIA Corporation + Copyright (c) 2016-2023 NVIDIA Corporation Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation files (the "Software"), to @@ -46,11 +46,13 @@ // A single top level PDE on Volta covers 128 TB and that's the minimum // size that can be used. parent_gpu->rm_va_base = 0; - parent_gpu->rm_va_size = 128ull * 1024 * 1024 * 1024 * 1024; + parent_gpu->rm_va_size = 128 * UVM_SIZE_1TB; - parent_gpu->uvm_mem_va_base = 384ull * 1024 * 1024 * 1024 * 1024; + parent_gpu->uvm_mem_va_base = 384 * UVM_SIZE_1TB; parent_gpu->uvm_mem_va_size = UVM_MEM_VA_SIZE; + parent_gpu->ce_phys_vidmem_write_supported = true; + parent_gpu->peer_copy_mode = UVM_GPU_PEER_COPY_MODE_VIRTUAL; // Not all units on Volta support 49-bit addressing, including those which @@ -96,4 +98,6 @@ parent_gpu->smc.supported = false; parent_gpu->plc_supported = false; + + parent_gpu->no_ats_range_required = false; } diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/kernel-open/nvidia-uvm/uvm_volta_ce.c nvidia-open-gpu-kernel-modules-535.161.08/kernel-open/nvidia-uvm/uvm_volta_ce.c --- nvidia-open-gpu-kernel-modules-525.147.05/kernel-open/nvidia-uvm/uvm_volta_ce.c 1970-01-01 00:00:00.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/kernel-open/nvidia-uvm/uvm_volta_ce.c 2024-03-05 22:25:56.000000000 +0000 @@ -0,0 +1,280 @@ +/******************************************************************************* + Copyright (c) 2022 NVIDIA Corporation + + Permission is hereby granted, free of charge, to any person obtaining a copy + of this software and associated documentation files (the "Software"), to + deal in the Software without restriction, including without limitation the + rights to use, copy, modify, merge, publish, distribute, sublicense, and/or + sell copies of the Software, and to permit persons to whom the Software is + furnished to do so, subject to the following conditions: + + The above copyright notice and this permission notice shall be + included in all copies or substantial portions of the Software. + + THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + DEALINGS IN THE SOFTWARE. + +*******************************************************************************/ + +#include "uvm_hal.h" +#include "uvm_push.h" +#include "clc3b5.h" + +// Return the flush type and the flush enablement. +static NvU32 volta_get_flush_value(uvm_push_t *push) +{ + NvU32 flush_value; + uvm_membar_t membar = uvm_push_get_and_reset_membar_flag(push); + + if (membar == UVM_MEMBAR_NONE) { + // No MEMBAR requested, don't use a flush. + flush_value = HWCONST(C3B5, LAUNCH_DMA, FLUSH_ENABLE, FALSE); + } + else { + flush_value = HWCONST(C3B5, LAUNCH_DMA, FLUSH_ENABLE, TRUE); + + if (membar == UVM_MEMBAR_GPU) + flush_value |= HWCONST(C3B5, LAUNCH_DMA, FLUSH_TYPE, GL); + else + flush_value |= HWCONST(C3B5, LAUNCH_DMA, FLUSH_TYPE, SYS); + } + + return flush_value; +} + +void uvm_hal_volta_ce_semaphore_release(uvm_push_t *push, NvU64 gpu_va, NvU32 payload) +{ + uvm_gpu_t *gpu = uvm_push_get_gpu(push); + NvU32 launch_dma_plc_mode; + + NV_PUSH_3U(C3B5, SET_SEMAPHORE_A, HWVALUE(C3B5, SET_SEMAPHORE_A, UPPER, NvOffset_HI32(gpu_va)), + SET_SEMAPHORE_B, HWVALUE(C3B5, SET_SEMAPHORE_B, LOWER, NvOffset_LO32(gpu_va)), + SET_SEMAPHORE_PAYLOAD, payload); + + launch_dma_plc_mode = gpu->parent->ce_hal->plc_mode(); + + NV_PUSH_1U(C3B5, LAUNCH_DMA, volta_get_flush_value(push) | + HWCONST(C3B5, LAUNCH_DMA, DATA_TRANSFER_TYPE, NONE) | + HWCONST(C3B5, LAUNCH_DMA, SEMAPHORE_TYPE, RELEASE_ONE_WORD_SEMAPHORE) | + launch_dma_plc_mode); +} + +void uvm_hal_volta_ce_semaphore_reduction_inc(uvm_push_t *push, NvU64 gpu_va, NvU32 payload) +{ + uvm_gpu_t *gpu = uvm_push_get_gpu(push); + NvU32 launch_dma_plc_mode; + + NV_PUSH_3U(C3B5, SET_SEMAPHORE_A, HWVALUE(C3B5, SET_SEMAPHORE_A, UPPER, NvOffset_HI32(gpu_va)), + SET_SEMAPHORE_B, HWVALUE(C3B5, SET_SEMAPHORE_B, LOWER, NvOffset_LO32(gpu_va)), + SET_SEMAPHORE_PAYLOAD, payload); + + launch_dma_plc_mode = gpu->parent->ce_hal->plc_mode(); + + NV_PUSH_1U(C3B5, LAUNCH_DMA, volta_get_flush_value(push) | + HWCONST(C3B5, LAUNCH_DMA, DATA_TRANSFER_TYPE, NONE) | + HWCONST(C3B5, LAUNCH_DMA, SEMAPHORE_TYPE, RELEASE_ONE_WORD_SEMAPHORE) | + HWCONST(C3B5, LAUNCH_DMA, SEMAPHORE_REDUCTION, INC) | + HWCONST(C3B5, LAUNCH_DMA, SEMAPHORE_REDUCTION_SIGN, UNSIGNED) | + HWCONST(C3B5, LAUNCH_DMA, SEMAPHORE_REDUCTION_ENABLE, TRUE) | + launch_dma_plc_mode); +} + +void uvm_hal_volta_ce_semaphore_timestamp(uvm_push_t *push, NvU64 gpu_va) +{ + uvm_gpu_t *gpu; + NvU32 launch_dma_plc_mode; + + NV_PUSH_3U(C3B5, SET_SEMAPHORE_A, HWVALUE(C3B5, SET_SEMAPHORE_A, UPPER, NvOffset_HI32(gpu_va)), + SET_SEMAPHORE_B, HWVALUE(C3B5, SET_SEMAPHORE_B, LOWER, NvOffset_LO32(gpu_va)), + SET_SEMAPHORE_PAYLOAD, 0xdeadbeef); + + gpu = uvm_push_get_gpu(push); + launch_dma_plc_mode = gpu->parent->ce_hal->plc_mode(); + + NV_PUSH_1U(C3B5, LAUNCH_DMA, volta_get_flush_value(push) | + HWCONST(C3B5, LAUNCH_DMA, DATA_TRANSFER_TYPE, NONE) | + HWCONST(C3B5, LAUNCH_DMA, SEMAPHORE_TYPE, RELEASE_FOUR_WORD_SEMAPHORE) | + launch_dma_plc_mode); +} + +void uvm_hal_volta_ce_memcopy(uvm_push_t *push, uvm_gpu_address_t dst, uvm_gpu_address_t src, size_t size) +{ + // If >4GB copies ever become an important use case, this function should + // use multi-line transfers so we don't have to iterate (bug 1766588). + static const size_t max_single_copy_size = 0xFFFFFFFF; + uvm_gpu_t *gpu = uvm_push_get_gpu(push); + + NvU32 pipelined_value; + NvU32 launch_dma_src_dst_type; + NvU32 launch_dma_plc_mode; + NvU32 flush_value = HWCONST(C3B5, LAUNCH_DMA, FLUSH_ENABLE, FALSE); + NvU32 copy_type_value = gpu->parent->ce_hal->memcopy_copy_type(push, dst, src); + + UVM_ASSERT_MSG(gpu->parent->ce_hal->memcopy_is_valid(push, dst, src), + "Memcopy validation failed in channel %s, GPU %s.\n", + push->channel->name, + uvm_gpu_name(gpu)); + + gpu->parent->ce_hal->memcopy_patch_src(push, &src); + + launch_dma_src_dst_type = gpu->parent->ce_hal->phys_mode(push, dst, src); + launch_dma_plc_mode = gpu->parent->ce_hal->plc_mode(); + + if (uvm_push_get_and_reset_flag(push, UVM_PUSH_FLAG_CE_NEXT_PIPELINED)) + pipelined_value = HWCONST(C3B5, LAUNCH_DMA, DATA_TRANSFER_TYPE, PIPELINED); + else + pipelined_value = HWCONST(C3B5, LAUNCH_DMA, DATA_TRANSFER_TYPE, NON_PIPELINED); + + do { + NvU32 copy_this_time = (NvU32)min(size, max_single_copy_size); + + // In the last operation, a flush/membar may be issued after the copy. + if (size == copy_this_time) + flush_value = volta_get_flush_value(push); + + gpu->parent->ce_hal->offset_in_out(push, src.address, dst.address); + + NV_PUSH_1U(C3B5, LINE_LENGTH_IN, copy_this_time); + + NV_PUSH_1U(C3B5, LAUNCH_DMA, + HWCONST(C3B5, LAUNCH_DMA, SRC_MEMORY_LAYOUT, PITCH) | + HWCONST(C3B5, LAUNCH_DMA, DST_MEMORY_LAYOUT, PITCH) | + HWCONST(C3B5, LAUNCH_DMA, MULTI_LINE_ENABLE, FALSE) | + HWCONST(C3B5, LAUNCH_DMA, REMAP_ENABLE, FALSE) | + flush_value | + launch_dma_src_dst_type | + launch_dma_plc_mode | + copy_type_value | + pipelined_value); + + pipelined_value = HWCONST(C3B5, LAUNCH_DMA, DATA_TRANSFER_TYPE, PIPELINED); + dst.address += copy_this_time; + src.address += copy_this_time; + size -= copy_this_time; + } while (size > 0); +} + +static NvU32 ce_aperture(uvm_aperture_t aperture) +{ + BUILD_BUG_ON(HWCONST(C3B5, SET_SRC_PHYS_MODE, TARGET, LOCAL_FB) != + HWCONST(C3B5, SET_DST_PHYS_MODE, TARGET, LOCAL_FB)); + BUILD_BUG_ON(HWCONST(C3B5, SET_SRC_PHYS_MODE, TARGET, COHERENT_SYSMEM) != + HWCONST(C3B5, SET_DST_PHYS_MODE, TARGET, COHERENT_SYSMEM)); + + UVM_ASSERT_MSG(aperture == UVM_APERTURE_VID || aperture == UVM_APERTURE_SYS, "aperture 0x%x\n", aperture); + + if (aperture == UVM_APERTURE_SYS) + return HWCONST(C3B5, SET_SRC_PHYS_MODE, TARGET, COHERENT_SYSMEM); + else + return HWCONST(C3B5, SET_SRC_PHYS_MODE, TARGET, LOCAL_FB); +} + +static NvU32 volta_memset_push_phys_mode(uvm_push_t *push, uvm_gpu_address_t dst) +{ + if (dst.is_virtual) + return HWCONST(C3B5, LAUNCH_DMA, DST_TYPE, VIRTUAL); + + NV_PUSH_1U(C3B5, SET_DST_PHYS_MODE, ce_aperture(dst.aperture)); + return HWCONST(C3B5, LAUNCH_DMA, DST_TYPE, PHYSICAL); +} + +static void memset_common(uvm_push_t *push, uvm_gpu_address_t dst, size_t size, size_t memset_element_size) +{ + // If >4GB memsets ever become an important use case, this function should + // use multi-line transfers so we don't have to iterate (bug 1766588). + static const size_t max_single_memset_size = 0xFFFFFFFF; + + uvm_gpu_t *gpu = uvm_push_get_gpu(push); + NvU32 pipelined_value; + NvU32 launch_dma_dst_type; + NvU32 launch_dma_plc_mode; + NvU32 flush_value = HWCONST(C3B5, LAUNCH_DMA, FLUSH_ENABLE, FALSE); + + UVM_ASSERT_MSG(gpu->parent->ce_hal->memset_is_valid(push, dst, size, memset_element_size), + "Memset validation failed in channel %s, GPU %s.\n", + push->channel->name, + uvm_gpu_name(gpu)); + + launch_dma_dst_type = volta_memset_push_phys_mode(push, dst); + launch_dma_plc_mode = gpu->parent->ce_hal->plc_mode(); + + if (uvm_push_get_and_reset_flag(push, UVM_PUSH_FLAG_CE_NEXT_PIPELINED)) + pipelined_value = HWCONST(C3B5, LAUNCH_DMA, DATA_TRANSFER_TYPE, PIPELINED); + else + pipelined_value = HWCONST(C3B5, LAUNCH_DMA, DATA_TRANSFER_TYPE, NON_PIPELINED); + + do { + NvU32 memset_this_time = (NvU32)min(size, max_single_memset_size); + + // In the last operation, a flush/membar may be issue after the memset. + if (size == memset_this_time) + flush_value = volta_get_flush_value(push); + + gpu->parent->ce_hal->offset_out(push, dst.address); + + NV_PUSH_1U(C3B5, LINE_LENGTH_IN, memset_this_time); + + NV_PUSH_1U(C3B5, LAUNCH_DMA, + HWCONST(C3B5, LAUNCH_DMA, SRC_MEMORY_LAYOUT, PITCH) | + HWCONST(C3B5, LAUNCH_DMA, DST_MEMORY_LAYOUT, PITCH) | + HWCONST(C3B5, LAUNCH_DMA, MULTI_LINE_ENABLE, FALSE) | + HWCONST(C3B5, LAUNCH_DMA, REMAP_ENABLE, TRUE) | + flush_value | + launch_dma_dst_type | + launch_dma_plc_mode | + pipelined_value); + + dst.address += memset_this_time * memset_element_size; + size -= memset_this_time; + pipelined_value = HWCONST(C3B5, LAUNCH_DMA, DATA_TRANSFER_TYPE, NON_PIPELINED); + } while (size > 0); +} + +void uvm_hal_volta_ce_memset_1(uvm_push_t *push, uvm_gpu_address_t dst, NvU8 value, size_t size) +{ + NV_PUSH_2U(C3B5, SET_REMAP_CONST_B, (NvU32)value, + SET_REMAP_COMPONENTS, + HWCONST(C3B5, SET_REMAP_COMPONENTS, DST_X, CONST_B) | + HWCONST(C3B5, SET_REMAP_COMPONENTS, COMPONENT_SIZE, ONE) | + HWCONST(C3B5, SET_REMAP_COMPONENTS, NUM_DST_COMPONENTS, ONE)); + + memset_common(push, dst, size, 1); +} + +void uvm_hal_volta_ce_memset_4(uvm_push_t *push, uvm_gpu_address_t dst, NvU32 value, size_t size) +{ + UVM_ASSERT_MSG(size % 4 == 0, "size: %zd\n", size); + + size /= 4; + + NV_PUSH_2U(C3B5, SET_REMAP_CONST_B, value, + SET_REMAP_COMPONENTS, + HWCONST(C3B5, SET_REMAP_COMPONENTS, DST_X, CONST_B) | + HWCONST(C3B5, SET_REMAP_COMPONENTS, COMPONENT_SIZE, FOUR) | + HWCONST(C3B5, SET_REMAP_COMPONENTS, NUM_DST_COMPONENTS, ONE)); + + memset_common(push, dst, size, 4); +} + +void uvm_hal_volta_ce_memset_8(uvm_push_t *push, uvm_gpu_address_t dst, NvU64 value, size_t size) +{ + UVM_ASSERT_MSG(size % 8 == 0, "size: %zd\n", size); + + size /= 8; + + NV_PUSH_3U(C3B5, SET_REMAP_CONST_A, (NvU32)value, + SET_REMAP_CONST_B, (NvU32)(value >> 32), + SET_REMAP_COMPONENTS, + HWCONST(C3B5, SET_REMAP_COMPONENTS, DST_X, CONST_A) | + HWCONST(C3B5, SET_REMAP_COMPONENTS, DST_Y, CONST_B) | + HWCONST(C3B5, SET_REMAP_COMPONENTS, COMPONENT_SIZE, FOUR) | + HWCONST(C3B5, SET_REMAP_COMPONENTS, NUM_DST_COMPONENTS, TWO)); + + memset_common(push, dst, size, 8); +} + diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/kernel-open/nvidia-uvm/uvm_volta_fault_buffer.c nvidia-open-gpu-kernel-modules-535.161.08/kernel-open/nvidia-uvm/uvm_volta_fault_buffer.c --- nvidia-open-gpu-kernel-modules-525.147.05/kernel-open/nvidia-uvm/uvm_volta_fault_buffer.c 2023-10-25 20:33:38.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/kernel-open/nvidia-uvm/uvm_volta_fault_buffer.c 2024-03-05 22:25:56.000000000 +0000 @@ -1,5 +1,5 @@ /******************************************************************************* - Copyright (c) 2016-2021 NVIDIA Corporation + Copyright (c) 2016-2023 NVIDIA Corporation Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation files (the "Software"), to @@ -25,7 +25,8 @@ #include "uvm_global.h" #include "uvm_gpu.h" #include "uvm_hal.h" -#include "uvm_push.h" +#include "uvm_conf_computing.h" +#include "nv_uvm_types.h" #include "hwref/volta/gv100/dev_fault.h" #include "hwref/volta/gv100/dev_fb.h" #include "clc369.h" @@ -56,21 +57,29 @@ void uvm_hal_volta_fault_buffer_write_get(uvm_parent_gpu_t *parent_gpu, NvU32 index) { NvU32 get = HWVALUE(_PFB_PRI_MMU, FAULT_BUFFER_GET, PTR, index); + UVM_ASSERT(index < parent_gpu->fault_buffer_info.replayable.max_faults); // If HW has detected an overflow condition (PUT == GET - 1 and a fault has - // arrived, which is dropped due to no more space in the fault buffer), it will - // not deliver any more faults into the buffer until the overflow condition has - // been cleared. The overflow condition is cleared by updating the GET index to - // indicate space in the buffer and writing 1 to the OVERFLOW bit in GET. - // Unfortunately, this can not be done in the same write because it can collide - // with an arriving fault on the same cycle, resulting in the overflow condition - // being instantly reasserted. - // However, if the index is updated first and then the OVERFLOW bit is cleared - // such a collision will not cause a reassertion of the overflow condition. + // arrived, which is dropped due to no more space in the fault buffer), it + // will not deliver any more faults into the buffer until the overflow + // condition has been cleared. The overflow condition is cleared by + // updating the GET index to indicate space in the buffer and writing 1 to + // the OVERFLOW bit in GET. Unfortunately, this can not be done in the same + // write because it can collide with an arriving fault on the same cycle, + // resulting in the overflow condition being instantly reasserted. However, + // if the index is updated first and then the OVERFLOW bit is cleared such + // a collision will not cause a reassertion of the overflow condition. UVM_GPU_WRITE_ONCE(*parent_gpu->fault_buffer_info.rm_info.replayable.pFaultBufferGet, get); - // Clear the getptr_corrupted/overflow bits. + // Clearing GETPTR_CORRUPTED and OVERFLOW is not needed when GSP-RM owns + // the HW replayable fault buffer, because UVM does not write to the actual + // GET register; GSP-RM is responsible for clearing the bits in the real + // GET register. + if (!uvm_parent_gpu_replayable_fault_buffer_is_uvm_owned(parent_gpu)) + return; + + // Clear the GETPTR_CORRUPTED and OVERFLOW bits. get |= HWCONST(_PFB_PRI_MMU, FAULT_BUFFER_GET, GETPTR_CORRUPTED, CLEAR) | HWCONST(_PFB_PRI_MMU, FAULT_BUFFER_GET, OVERFLOW, CLEAR); UVM_GPU_WRITE_ONCE(*parent_gpu->fault_buffer_info.rm_info.replayable.pFaultBufferGet, get); @@ -144,7 +153,7 @@ return UVM_FAULT_ACCESS_TYPE_COUNT; } -static uvm_fault_type_t get_fault_type(const NvU32 *fault_entry) +uvm_fault_type_t uvm_hal_volta_fault_buffer_get_fault_type(const NvU32 *fault_entry) { NvU32 hw_fault_type_value = READ_HWVALUE_MW(fault_entry, C369, BUF_ENTRY, FAULT_TYPE); @@ -238,17 +247,28 @@ return fault_entry; } +// See uvm_pascal_fault_buffer.c::get_fault_buffer_entry_metadata +static UvmFaultMetadataPacket *get_fault_buffer_entry_metadata(uvm_parent_gpu_t *parent_gpu, NvU32 index) +{ + UvmFaultMetadataPacket *fault_entry_metadata; + + UVM_ASSERT(index < parent_gpu->fault_buffer_info.replayable.max_faults); + UVM_ASSERT(!uvm_parent_gpu_replayable_fault_buffer_is_uvm_owned(parent_gpu)); + + fault_entry_metadata = parent_gpu->fault_buffer_info.rm_info.replayable.bufferMetadata; + UVM_ASSERT(fault_entry_metadata != NULL); + + return fault_entry_metadata + index; +} + static void parse_fault_entry_common(uvm_parent_gpu_t *parent_gpu, NvU32 *fault_entry, uvm_fault_buffer_entry_t *buffer_entry) { - NV_STATUS status; NvU64 addr_hi, addr_lo; NvU64 timestamp_hi, timestamp_lo; bool replayable_fault_enabled; - status = NV_OK; - addr_hi = READ_HWVALUE_MW(fault_entry, C369, BUF_ENTRY, INST_HI); addr_lo = READ_HWVALUE_MW(fault_entry, C369, BUF_ENTRY, INST_LO); buffer_entry->instance_ptr.address = addr_lo + (addr_hi << HWSIZE_MW(C369, BUF_ENTRY, INST_LO)); @@ -267,7 +287,7 @@ timestamp_lo = READ_HWVALUE_MW(fault_entry, C369, BUF_ENTRY, TIMESTAMP_LO); buffer_entry->timestamp = timestamp_lo + (timestamp_hi << HWSIZE_MW(C369, BUF_ENTRY, TIMESTAMP_LO)); - buffer_entry->fault_type = get_fault_type(fault_entry); + buffer_entry->fault_type = parent_gpu->fault_buffer_hal->get_fault_type(fault_entry); buffer_entry->fault_access_type = get_fault_access_type(fault_entry); @@ -318,22 +338,47 @@ UVM_ASSERT_MSG(replayable_fault_enabled, "Fault with REPLAYABLE_FAULT_EN bit unset\n"); } -void uvm_hal_volta_fault_buffer_parse_entry(uvm_parent_gpu_t *parent_gpu, - NvU32 index, - uvm_fault_buffer_entry_t *buffer_entry) +NV_STATUS uvm_hal_volta_fault_buffer_parse_replayable_entry(uvm_parent_gpu_t *parent_gpu, + NvU32 index, + uvm_fault_buffer_entry_t *buffer_entry) { + fault_buffer_entry_c369_t entry; NvU32 *fault_entry; - BUILD_BUG_ON(NVC369_BUF_SIZE > UVM_GPU_MMU_MAX_FAULT_PACKET_SIZE); - fault_entry = get_fault_buffer_entry(parent_gpu, index); + BUILD_BUG_ON(sizeof(entry) > UVM_GPU_MMU_MAX_FAULT_PACKET_SIZE); // Valid bit must be set before this function is called UVM_ASSERT(parent_gpu->fault_buffer_hal->entry_is_valid(parent_gpu, index)); + fault_entry = get_fault_buffer_entry(parent_gpu, index); + + // When Confidential Computing is enabled, faults are encrypted by RM, so + // they need to be decrypted before they can be parsed + if (!uvm_parent_gpu_replayable_fault_buffer_is_uvm_owned(parent_gpu)) { + NV_STATUS status; + UvmFaultMetadataPacket *fault_entry_metadata = get_fault_buffer_entry_metadata(parent_gpu, index); + + status = uvm_conf_computing_fault_decrypt(parent_gpu, + &entry, + fault_entry, + fault_entry_metadata->authTag, + fault_entry_metadata->valid); + if (status != NV_OK) { + uvm_global_set_fatal_error(status); + return status; + } + + fault_entry = (NvU32 *) &entry; + } + parse_fault_entry_common(parent_gpu, fault_entry, buffer_entry); + UVM_ASSERT(buffer_entry->is_replayable); + // Automatically clear valid bit for the entry in the fault buffer parent_gpu->fault_buffer_hal->entry_clear_valid(parent_gpu, index); + + return NV_OK; } void uvm_hal_volta_fault_buffer_parse_non_replayable_entry(uvm_parent_gpu_t *parent_gpu, @@ -344,4 +389,5 @@ // No need to clear the valid bit since the fault buffer for non-replayable // faults is owned by RM and we are just parsing a copy of the packet + UVM_ASSERT(!buffer_entry->is_replayable); } diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/kernel-open/nvidia-uvm/uvm_volta_mmu.c nvidia-open-gpu-kernel-modules-535.161.08/kernel-open/nvidia-uvm/uvm_volta_mmu.c --- nvidia-open-gpu-kernel-modules-525.147.05/kernel-open/nvidia-uvm/uvm_volta_mmu.c 2023-10-25 20:33:38.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/kernel-open/nvidia-uvm/uvm_volta_mmu.c 2024-03-05 22:25:56.000000000 +0000 @@ -1,5 +1,5 @@ /******************************************************************************* - Copyright (c) 2017-2021 NVIDIA Corporation + Copyright (c) 2017-2023 NVIDIA Corporation Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation files (the "Software"), to @@ -145,13 +145,20 @@ return pde_bits; } -static void make_pde_volta(void *entry, uvm_mmu_page_table_alloc_t **phys_allocs, NvU32 depth) +static void make_pde_volta(void *entry, + uvm_mmu_page_table_alloc_t **phys_allocs, + uvm_page_directory_t *dir, + NvU32 child_index) { - NvU32 entry_count = entries_per_index_volta(depth); + NvU32 entry_count; NvU64 *entry_bits = (NvU64 *)entry; + UVM_ASSERT(dir); + + entry_count = entries_per_index_volta(dir->depth); + if (entry_count == 1) { - *entry_bits = single_pde_volta(*phys_allocs, depth); + *entry_bits = single_pde_volta(*phys_allocs, dir->depth); } else if (entry_count == 2) { entry_bits[MMU_BIG] = big_half_pde_volta(phys_allocs[MMU_BIG]); diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/nouveau/extract-firmware-nouveau.py nvidia-open-gpu-kernel-modules-535.161.08/nouveau/extract-firmware-nouveau.py --- nvidia-open-gpu-kernel-modules-525.147.05/nouveau/extract-firmware-nouveau.py 1970-01-01 00:00:00.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/nouveau/extract-firmware-nouveau.py 2024-02-22 04:52:55.000000000 +0000 @@ -0,0 +1,342 @@ +#!/usr/bin/env python3 + +# SPDX-FileCopyrightText: Copyright (c) 2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. +# SPDX-License-Identifier: MIT +# +# Permission is hereby granted, free of charge, to any person obtaining a +# copy of this software and associated documentation files (the "Software"), +# to deal in the Software without restriction, including without limitation +# the rights to use, copy, modify, merge, publish, distribute, sublicense, +# and/or sell copies of the Software, and to permit persons to whom the +# Software is furnished to do so, subject to the following conditions: +# +# The above copyright notice and this permission notice shall be included in +# all copies or substantial portions of the Software. +# +# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +# THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER +# LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING +# FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER +# DEALINGS IN THE SOFTWARE. + +# Converts OpenRM binhex-encoded images to Nouveau-compatible binary blobs +# See nouveau_firmware_layout.ods for documentation on the file format + +import sys +import os +import argparse +import shutil +import re +import gzip +import struct + +class MyException(Exception): + pass + +def round_up_to_base(x, base = 10): + return x + (base - x) % base + +def getbytes(filename, array): + """Extract the bytes for the given array in the given file. + + :param filename: the file to parse + :param array: the name of the array to parse + :returns: byte array + + This function scans the file for the array and returns a bytearray of + its contents, uncompressing the data if it is tagged as compressed. + + This function assumes that each array is immediately preceded with a comment + section that specifies whether the array is compressed and how many bytes of + data there should be. Example: + + #if defined(BINDATA_INCLUDE_DATA) + // + // FUNCTION: ksec2GetBinArchiveSecurescrubUcode_AD10X("header_prod") + // FILE NAME: kernel/inc/securescrub/bin/ad10x/g_securescrubuc_sec2_ad10x_boot_from_hs_prod.h + // FILE TYPE: TEXT + // VAR NAME: securescrub_ucode_header_ad10x_boot_from_hs + // COMPRESSION: YES + // COMPLEX_STRUCT: NO + // DATA SIZE (bytes): 36 + // COMPRESSED SIZE (bytes): 27 + // + static BINDATA_CONST NvU8 ksec2BinArchiveSecurescrubUcode_AD10X_header_prod_data[] = + { + 0x63, 0x60, 0x00, 0x02, 0x46, 0x20, 0x96, 0x02, 0x62, 0x66, 0x08, 0x13, 0x4c, 0x48, 0x42, 0x69, + 0x20, 0x00, 0x00, 0x30, 0x39, 0x0a, 0xfc, 0x24, 0x00, 0x00, 0x00, + }; + #endif // defined(BINDATA_INCLUDE_DATA) + """ + + with open(filename) as f: + for line in f: + if "COMPRESSION: NO" in line: + compressed = False + if "COMPRESSION: YES" in line: + compressed = True + m = re.search("DATA SIZE \(bytes\): (\d+)", line) + if m: + data_size = int(m.group(1)) + m = re.search("COMPRESSED SIZE \(bytes\): (\d+)", line) + if m: + compressed_size = int(m.group(1)) + if "static BINDATA_CONST NvU8 " + array in line: + break + else: + raise MyException(f"array {array} not found in {filename}") + + output = b'' + for line in f: + if "};" in line: + break + bytes = [int(b, 16) for b in re.findall('0x[0-9a-f][0-9a-f]', line)] + if len(bytes) > 0: + output += struct.pack(f"{len(bytes)}B", *bytes) + + if len(output) == 0: + raise MyException(f"no data found for {array}") + + if compressed: + if len(output) != compressed_size: + raise MyException(f"compressed array {array} in {filename} should be {compressed_size} bytes but is actually {len(output)}.") + gzipheader = struct.pack("<4BL2B", 0x1f, 0x8b, 8, 0, 0, 0, 3) + output = gzip.decompress(gzipheader + output) + if len(output) != data_size: + raise MyException(f"array {array} in {filename} decompressed to {len(output)} bytes but should have been {data_size} bytes.") + return output + else: + if len(output) != data_size: + raise MyException(f"array {array} in {filename} should be {compressed_size} bytes but is actually {len(output)}.") + return output + +# GSP bootloader +def bootloader(gpu, type): + global outputpath + global version + + GPU=gpu.upper() + filename = f"src/nvidia/generated/g_bindata_kgspGetBinArchiveGspRmBoot_{GPU}.c" + + print(f"Creating nvidia/{gpu}/gsp/bootloader-{version}.bin") + os.makedirs(f"{outputpath}/nvidia/{gpu}/gsp/", exist_ok = True) + + with open(f"{outputpath}/nvidia/{gpu}/gsp/bootloader-{version}.bin", "wb") as f: + # Extract the actual bootloader firmware + array = f"kgspBinArchiveGspRmBoot_{GPU}_ucode_image{type}data" + firmware = getbytes(filename, array) + firmware_size = len(firmware) + + # Extract the descriptor (RM_RISCV_UCODE_DESC) + array = f"kgspBinArchiveGspRmBoot_{GPU}_ucode_desc{type}data" + descriptor = getbytes(filename, array) + descriptor_size = len(descriptor) + + # First, add the nvfw_bin_hdr header + total_size = round_up_to_base(24 + firmware_size + descriptor_size, 256) + firmware_offset = 24 + descriptor_size + f.write(struct.pack("<6L", 0x10de, 1, total_size, 24, firmware_offset, firmware_size)) + + # Second, add the descriptor + f.write(descriptor) + + # Finally, the actual bootloader image + f.write(firmware) + +# GSP Booter load and unload +def booter(gpu, load, sigsize): + global outputpath + global version + + GPU = gpu.upper() + LOAD = load.capitalize() + + filename = f"src/nvidia/generated/g_bindata_kgspGetBinArchiveBooter{LOAD}Ucode_{GPU}.c" + + print(f"Creating nvidia/{gpu}/gsp/booter_{load}-{version}.bin") + os.makedirs(f"{outputpath}/nvidia/{gpu}/gsp/", exist_ok = True) + + with open(f"{outputpath}/nvidia/{gpu}/gsp/booter_{load}-{version}.bin", "wb") as f: + # Extract the actual scrubber firmware + array = f"kgspBinArchiveBooter{LOAD}Ucode_{GPU}_image_prod_data" + firmware = getbytes(filename, array) + firmware_size = len(firmware) + + # Extract the signatures + array = f"kgspBinArchiveBooter{LOAD}Ucode_{GPU}_sig_prod_data" + signatures = getbytes(filename, array) + signatures_size = len(signatures) + if signatures_size % sigsize: + raise MyException(f"signature file size for {array} is uneven value of {sigsize}") + num_sigs = int(signatures_size / sigsize); + if num_sigs < 1: + raise MyException(f"invalid number of signatures {num_sigs}") + + # First, add the nvfw_bin_hdr header + total_size = round_up_to_base(120 + signatures_size + firmware_size, 256) + firmware_offset = 120 + signatures_size + f.write(struct.pack("<6L", 0x10de, 1, total_size, 24, firmware_offset, firmware_size)) + + # Second, add the nvfw_hs_header_v2 header + patch_loc_offset = 60 + signatures_size + patch_sig_offset = patch_loc_offset + 4 + meta_data_offset = patch_sig_offset + 4 + num_sig_offset = meta_data_offset + 12 + header_offset = num_sig_offset + 4 + f.write(struct.pack("<9L", 60, signatures_size, patch_loc_offset, + patch_sig_offset, meta_data_offset, 12, + num_sig_offset, header_offset, 36)) + + # Third, the actual signatures + f.write(signatures) + + # Extract the patch location + array = f"kgspBinArchiveBooter{LOAD}Ucode_{GPU}_patch_loc_data" + bytes = getbytes(filename, array) + patchloc = struct.unpack("messageOffset show how far into // the message we are. + // + EncodedMessage * messageOutstanding; unsigned assemblyTransmitted; public: void set(EncodedMessage * messageOutstanding) @@ -62,7 +65,7 @@ // bool get(Buffer & assemblyBuffer); - MessageTransactionSplitter() + MessageTransactionSplitter() : messageOutstanding(0), assemblyTransmitted(0) {} }; diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/common/displayport/src/dp_configcaps.cpp nvidia-open-gpu-kernel-modules-535.161.08/src/common/displayport/src/dp_configcaps.cpp --- nvidia-open-gpu-kernel-modules-525.147.05/src/common/displayport/src/dp_configcaps.cpp 2023-10-25 20:22:25.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/common/displayport/src/dp_configcaps.cpp 2024-03-05 22:11:59.000000000 +0000 @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 1993-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 1993-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -115,14 +115,6 @@ // DPCD Offset 0119h [0] - If we grant the extendedSleepWakeTimeoutRequest bool bExtendedSleepWakeTimeoutGranted; - // 0x2206, if the sink supports 128b/132b - bool bDP20ChannelCodingSupported; - // 0x2215 - bool bUHBR_10GSupported; - bool bUHBR_13_5GSupported; - bool bUHBR_20GSupported; - - // DPCD Offset F0002h - Number of Physical Repeaters present (after mapping) between Source and Sink unsigned phyRepeaterCount; // DPCD offset 700 - EDP_DPCD_REV @@ -134,13 +126,6 @@ LinkRate maxLinkRate; // DPCD offset F0001h unsigned maxLaneCount; // DPCD offset F0004h unsigned phyRepeaterExtendedWakeTimeoutMs; // DPCD offset F0005h - - // 0xF0006, if the PHY Repeater supports 128b/132b - bool bDP20ChannelCodingSupported; - // 0xF0007 - bool UHBR_10GSupported; - bool UHBR_13_5GSupported; - bool UHBR_20GSupported; } repeaterCaps; PCONCaps pconCaps; @@ -506,45 +491,6 @@ caps.numberAudioEndpoints = (unsigned)(DRF_VAL(_DPCD, _NUMBER_OF_AUDIO_ENDPOINTS, _VALUE, buffer[0x2])); - // 02206h - if (AuxRetry::ack == bus.read(NV_DPCD14_EXTENDED_MAIN_LINK_CHANNEL_CODING, &buffer[0], 1)) - { - caps.bDP20ChannelCodingSupported = - FLD_TEST_DRF(_DPCD14, - _EXTENDED_MAIN_LINK_CHANNEL_CODING, - _ANSI_128B_132B, - _YES, - buffer[0]); - if (caps.bDP20ChannelCodingSupported == true) - { - // 0x2215 - if (AuxRetry::ack == bus.read(NV_DPCD20_128B_132B_SUPPORTED_LINK_RATES, &buffer[0], 1)) - { - caps.bUHBR_10GSupported = - FLD_TEST_DRF(_DPCD20, - _128B_132B_SUPPORTED_LINK_RATES, - _UHBR10, - _YES, - buffer[0]); - - caps.bUHBR_13_5GSupported = - FLD_TEST_DRF(_DPCD20, - _128B_132B_SUPPORTED_LINK_RATES, - _UHBR13_5, - _YES, - buffer[0]); - - caps.bUHBR_20GSupported = - FLD_TEST_DRF(_DPCD20, - _128B_132B_SUPPORTED_LINK_RATES, - _UHBR20, - _YES, - buffer[0]); - } - DP_ASSERT(caps.bUHBR_10GSupported && "Unknown max link rate or HBR2 without at least DP 1.2. Assuming DP 1.1 defaults"); - } - } - if (bLttprSupported) { // Burst read from 0xF0000 to 0xF0007 @@ -583,42 +529,6 @@ _PHY_REPEATER_EXTENDED_WAKE_TIMEOUT, _REQ, buffer[0x5]) * 10; - // An LTTPR that supports 128b/132b channel coding shall program this register to 20h. - if (lttprIsAtLeastVersion(2, 0)) - { - caps.repeaterCaps.bDP20ChannelCodingSupported = - FLD_TEST_DRF(_DPCD14, - _PHY_REPEATER_MAIN_LINK_CHANNEL_CODING, - _128B_132B_SUPPORTED, - _YES, - buffer[6]); - - caps.repeaterCaps.UHBR_10GSupported = - FLD_TEST_DRF(_DPCD14, - _PHY_REPEATER_128B_132B_RATES, - _10G_SUPPORTED, - _YES, - buffer[7]); - - caps.repeaterCaps.UHBR_13_5GSupported = - FLD_TEST_DRF(_DPCD14, - _PHY_REPEATER_128B_132B_RATES, - _13_5G_SUPPORTED, - _YES, - buffer[7]); - - caps.repeaterCaps.UHBR_20GSupported = - FLD_TEST_DRF(_DPCD14, - _PHY_REPEATER_128B_132B_RATES, - _20G_SUPPORTED, - _YES, - buffer[7]); - - if (buffer[7] && !caps.repeaterCaps.bDP20ChannelCodingSupported) - { - DP_ASSERT(0 && "UHBR is supported without 128b/132b Channel Encoding Supported!"); - } - } } else { @@ -830,6 +740,23 @@ return bSDPExtnForColorimetry; } + virtual bool getRootAsyncSDPSupported() + { + NvU8 byte = 0; + if (!caps.extendedRxCapsPresent) + return false; + if (AuxRetry::ack != bus.read(NV_DPCD14_DPRX_FEATURE_ENUM_LIST, &byte, sizeof byte) || + FLD_TEST_DRF(_DPCD14, _DPRX_FEATURE_ENUM_LIST, _ADAPTIVE_SYNC_SDP_SUPPORTED, _NO, byte)) + { + return false; + } + if (AuxRetry::ack != bus.read(NV_DPCD_DOWN_STREAM_PORT, &byte, sizeof byte) || + FLD_TEST_DRF(_DPCD, _DOWN_STREAM_PORT, _MSA_TIMING_PAR_IGNORED, _NO, byte)) + { + return false; + } + return true; + } virtual AuxRetry::status setOuiSource(unsigned ouiId, const char * model, size_t modelNameLength, NvU8 chipRevision) { @@ -2721,8 +2648,8 @@ virtual void resetProtocolConverter() { NvU8 data = 0; - bus.write(NV_DPCD20_PCON_FRL_LINK_CONFIG_1, &data, sizeof(data)); - bus.write(NV_DPCD20_PCON_FRL_LINK_CONFIG_2, &data, sizeof(data)); + bus.write(NV_DPCD14_PCON_FRL_LINK_CONFIG_1, &data, sizeof(data)); + bus.write(NV_DPCD14_PCON_FRL_LINK_CONFIG_2, &data, sizeof(data)); } @@ -2732,26 +2659,26 @@ if (bEnableSourceControlMode) { - data = FLD_SET_DRF(_DPCD20, _PCON_FRL_LINK_CONFIG_1, _SRC_CONTROL_MODE, _ENABLE, data); + data = FLD_SET_DRF(_DPCD14, _PCON_FRL_LINK_CONFIG_1, _SRC_CONTROL_MODE, _ENABLE, data); if (bEnableFRLMode) { - data = FLD_SET_DRF(_DPCD20, _PCON_FRL_LINK_CONFIG_1, _LINK_FRL_MODE, _ENABLE, data); - data = FLD_SET_DRF(_DPCD20, _PCON_FRL_LINK_CONFIG_1, _IRQ_LINK_FRL_MODE, _ENABLE, data); + data = FLD_SET_DRF(_DPCD14, _PCON_FRL_LINK_CONFIG_1, _LINK_FRL_MODE, _ENABLE, data); + data = FLD_SET_DRF(_DPCD14, _PCON_FRL_LINK_CONFIG_1, _IRQ_LINK_FRL_MODE, _ENABLE, data); } else { - data = FLD_SET_DRF(_DPCD20, _PCON_FRL_LINK_CONFIG_1, _LINK_FRL_MODE, _DISABLE, data); - data = FLD_SET_DRF(_DPCD20, _PCON_FRL_LINK_CONFIG_1, _IRQ_LINK_FRL_MODE, _DISABLE, data); + data = FLD_SET_DRF(_DPCD14, _PCON_FRL_LINK_CONFIG_1, _LINK_FRL_MODE, _DISABLE, data); + data = FLD_SET_DRF(_DPCD14, _PCON_FRL_LINK_CONFIG_1, _IRQ_LINK_FRL_MODE, _DISABLE, data); } } else { - data = FLD_SET_DRF(_DPCD20, _PCON_FRL_LINK_CONFIG_1, _SRC_CONTROL_MODE, _DISABLE, data); - data = FLD_SET_DRF(_DPCD20, _PCON_FRL_LINK_CONFIG_1, _LINK_FRL_MODE, _DISABLE, data); - data = FLD_SET_DRF(_DPCD20, _PCON_FRL_LINK_CONFIG_1, _IRQ_LINK_FRL_MODE, _DISABLE, data); + data = FLD_SET_DRF(_DPCD14, _PCON_FRL_LINK_CONFIG_1, _SRC_CONTROL_MODE, _DISABLE, data); + data = FLD_SET_DRF(_DPCD14, _PCON_FRL_LINK_CONFIG_1, _LINK_FRL_MODE, _DISABLE, data); + data = FLD_SET_DRF(_DPCD14, _PCON_FRL_LINK_CONFIG_1, _IRQ_LINK_FRL_MODE, _DISABLE, data); } - if (AuxRetry::ack != bus.write(NV_DPCD20_PCON_FRL_LINK_CONFIG_1, &data, sizeof(data))) + if (AuxRetry::ack != bus.write(NV_DPCD14_PCON_FRL_LINK_CONFIG_1, &data, sizeof(data))) { return false; } @@ -2789,12 +2716,12 @@ // Clear only this interrupt bit. this->clearHdmiLinkStatusChanged(); - if (AuxRetry::ack != bus.read(NV_DPCD20_PCON_HDMI_TX_LINK_STATUS, &data, sizeof(data))) + if (AuxRetry::ack != bus.read(NV_DPCD14_PCON_HDMI_TX_LINK_STATUS, &data, sizeof(data))) { return false; } - if (FLD_TEST_DRF(_DPCD20, _PCON_HDMI_TX_LINK_STATUS, _LINK_READY, _YES, data)) + if (FLD_TEST_DRF(_DPCD14, _PCON_HDMI_TX_LINK_STATUS, _LINK_READY, _YES, data)) { *bFrlReady = true; } @@ -2819,22 +2746,22 @@ // PCON FW trains for all Link BW selected in Link BW Mask (Bit 0~5) // data = linkBwMask; - data = FLD_SET_DRF(_DPCD20, _PCON_FRL_LINK_CONFIG_2, _FRL_LT_CONTROL, + data = FLD_SET_DRF(_DPCD14, _PCON_FRL_LINK_CONFIG_2, _FRL_LT_CONTROL, _EXTENDED, data); } else { // Set FRL_LT_CONTROL to Normal mode, so PCON stops when first FRL LT succeed. - data = FLD_SET_DRF(_DPCD20, _PCON_FRL_LINK_CONFIG_2, _FRL_LT_CONTROL, + data = FLD_SET_DRF(_DPCD14, _PCON_FRL_LINK_CONFIG_2, _FRL_LT_CONTROL, _NORMAL, data); } - if (AuxRetry::ack != bus.write(NV_DPCD20_PCON_FRL_LINK_CONFIG_2, &data, sizeof(data))) + if (AuxRetry::ack != bus.write(NV_DPCD14_PCON_FRL_LINK_CONFIG_2, &data, sizeof(data))) { return false; } - if (AuxRetry::ack != bus.read(NV_DPCD20_PCON_FRL_LINK_CONFIG_1, &data, sizeof(data))) + if (AuxRetry::ack != bus.read(NV_DPCD14_PCON_FRL_LINK_CONFIG_1, &data, sizeof(data))) { return false; } @@ -2842,7 +2769,7 @@ if (bEnableConcurrentMode && caps.pconCaps.bConcurrentLTSupported) { // Client selects concurrent. - data = FLD_SET_DRF(_DPCD20, _PCON_FRL_LINK_CONFIG_1, _CONCURRENT_LT_MODE, + data = FLD_SET_DRF(_DPCD14, _PCON_FRL_LINK_CONFIG_1, _CONCURRENT_LT_MODE, _ENABLE, data); } else @@ -2850,15 +2777,15 @@ // // Don't do concurrent LT for now. // - data = FLD_SET_DRF(_DPCD20, _PCON_FRL_LINK_CONFIG_1, _CONCURRENT_LT_MODE, + data = FLD_SET_DRF(_DPCD14, _PCON_FRL_LINK_CONFIG_1, _CONCURRENT_LT_MODE, _DISABLE, data); } - data = FLD_SET_DRF(_DPCD20, _PCON_FRL_LINK_CONFIG_1, _HDMI_LINK, + data = FLD_SET_DRF(_DPCD14, _PCON_FRL_LINK_CONFIG_1, _HDMI_LINK, _ENABLE, data); - data = FLD_SET_DRF_NUM(_DPCD20, _PCON_FRL_LINK_CONFIG_1, _MAX_LINK_BW, + data = FLD_SET_DRF_NUM(_DPCD14, _PCON_FRL_LINK_CONFIG_1, _MAX_LINK_BW, targetBw, data); - if (AuxRetry::ack != bus.write(NV_DPCD20_PCON_FRL_LINK_CONFIG_1, &data, sizeof(data))) + if (AuxRetry::ack != bus.write(NV_DPCD14_PCON_FRL_LINK_CONFIG_1, &data, sizeof(data))) { return false; } @@ -2888,16 +2815,16 @@ return false; } // Check HDMI Link Active status (0x303B Bit 0) and Link Config (0x3036) - if (AuxRetry::ack != bus.read(NV_DPCD20_PCON_HDMI_TX_LINK_STATUS, &data, sizeof(data))) + if (AuxRetry::ack != bus.read(NV_DPCD14_PCON_HDMI_TX_LINK_STATUS, &data, sizeof(data))) { return false; } - if (FLD_TEST_DRF(_DPCD20, _PCON_HDMI_TX_LINK_STATUS, _LINK_ACTIVE, _YES, data)) + if (FLD_TEST_DRF(_DPCD14, _PCON_HDMI_TX_LINK_STATUS, _LINK_ACTIVE, _YES, data)) { - if (AuxRetry::ack == bus.read(NV_DPCD20_PCON_HDMI_LINK_CONFIG_STATUS, &data, sizeof(data))) + if (AuxRetry::ack == bus.read(NV_DPCD14_PCON_HDMI_LINK_CONFIG_STATUS, &data, sizeof(data))) { - *frlRateMask = DRF_VAL(_DPCD20, _PCON_HDMI_LINK_CONFIG_STATUS, _LT_RESULT, data); + *frlRateMask = DRF_VAL(_DPCD14, _PCON_HDMI_LINK_CONFIG_STATUS, _LT_RESULT, data); } } @@ -2912,18 +2839,18 @@ if (bLinkActive == NULL && bLinkReady == NULL) return false; - if (AuxRetry::ack != bus.read(NV_DPCD20_PCON_HDMI_TX_LINK_STATUS, &data, sizeof(data))) + if (AuxRetry::ack != bus.read(NV_DPCD14_PCON_HDMI_TX_LINK_STATUS, &data, sizeof(data))) { return false; } if (bLinkReady != NULL) { - *bLinkReady = (FLD_TEST_DRF(_DPCD20, _PCON_HDMI_TX_LINK_STATUS, + *bLinkReady = (FLD_TEST_DRF(_DPCD14, _PCON_HDMI_TX_LINK_STATUS, _LINK_READY, _YES, data)); } if (bLinkActive != NULL) { - *bLinkActive = (FLD_TEST_DRF(_DPCD20, _PCON_HDMI_TX_LINK_STATUS, + *bLinkActive = (FLD_TEST_DRF(_DPCD14, _PCON_HDMI_TX_LINK_STATUS, _LINK_ACTIVE, _YES, data)); } return true; @@ -2938,12 +2865,12 @@ NvU8 data = 0; NvU32 loopCount; NvU32 frlRate; - if (AuxRetry::ack != bus.read(NV_DPCD20_PCON_FRL_LINK_CONFIG_1, &data, sizeof(data))) + if (AuxRetry::ack != bus.read(NV_DPCD14_PCON_FRL_LINK_CONFIG_1, &data, sizeof(data))) { return false; } - data = FLD_SET_DRF(_DPCD20, _PCON_FRL_LINK_CONFIG_1, _HDMI_LINK, _DISABLE, data); - if (AuxRetry::ack != bus.write(NV_DPCD20_PCON_FRL_LINK_CONFIG_1, &data, sizeof(data))) + data = FLD_SET_DRF(_DPCD14, _PCON_FRL_LINK_CONFIG_1, _HDMI_LINK, _DISABLE, data); + if (AuxRetry::ack != bus.write(NV_DPCD14_PCON_FRL_LINK_CONFIG_1, &data, sizeof(data))) { return false; } @@ -2954,14 +2881,14 @@ data = 0; do { - if (AuxRetry::ack != bus.read(NV_DPCD20_PCON_HDMI_TX_LINK_STATUS, + if (AuxRetry::ack != bus.read(NV_DPCD14_PCON_HDMI_TX_LINK_STATUS, &data, sizeof(data))) continue; - if (FLD_TEST_DRF(_DPCD20, _PCON_HDMI_TX_LINK_STATUS, _LINK_READY, _YES, data)) + if (FLD_TEST_DRF(_DPCD14, _PCON_HDMI_TX_LINK_STATUS, _LINK_READY, _YES, data)) break; } while (timeout.valid()); - if (FLD_TEST_DRF(_DPCD20, _PCON_HDMI_TX_LINK_STATUS, _LINK_READY, _NO, data)) + if (FLD_TEST_DRF(_DPCD14, _PCON_HDMI_TX_LINK_STATUS, _LINK_READY, _NO, data)) { return false; } @@ -2970,12 +2897,12 @@ // 5. Set HDMI Enable Bit. data = 0; - if (AuxRetry::ack != bus.read(NV_DPCD20_PCON_FRL_LINK_CONFIG_1, &data, sizeof(data))) + if (AuxRetry::ack != bus.read(NV_DPCD14_PCON_FRL_LINK_CONFIG_1, &data, sizeof(data))) { return false; } - data = FLD_SET_DRF(_DPCD20, _PCON_FRL_LINK_CONFIG_1, _HDMI_LINK, _ENABLE, data); - if (AuxRetry::ack != bus.write(NV_DPCD20_PCON_FRL_LINK_CONFIG_1, &data, sizeof(data))) + data = FLD_SET_DRF(_DPCD14, _PCON_FRL_LINK_CONFIG_1, _HDMI_LINK, _ENABLE, data); + if (AuxRetry::ack != bus.write(NV_DPCD14_PCON_FRL_LINK_CONFIG_1, &data, sizeof(data))) { return false; } @@ -3202,9 +3129,9 @@ if (retVal) { psrEvt->sinkCapChange = DRF_VAL(_DPCD, - _PANEL_SELF_REFRESH_EVENT_STATUS, - _CAP_CHANGE, - config); + _PANEL_SELF_REFRESH_EVENT_STATUS, + _CAP_CHANGE, + config); } return retVal; } diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/common/displayport/src/dp_connectorimpl.cpp nvidia-open-gpu-kernel-modules-535.161.08/src/common/displayport/src/dp_connectorimpl.cpp --- nvidia-open-gpu-kernel-modules-525.147.05/src/common/displayport/src/dp_connectorimpl.cpp 2023-10-25 20:22:25.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/common/displayport/src/dp_connectorimpl.cpp 2024-03-05 22:11:59.000000000 +0000 @@ -50,22 +50,6 @@ using namespace DisplayPort; -// These wrappers are specifically for DSC PPS library malloc and free callbacks -// Pointer to these functions are populated to dscMalloc/dscFree in DSC_InitializeCallBack and it is initialized from both DPLib and HDMiPacketLib. -// In HDMI case, callback function for malloc/free needs client handle so to match function prototype, in DP case, adding these wrappers. -extern "C" void * dpMallocCb(const void *clientHandle, NvLength size); -extern "C" void dpFreeCb(const void *clientHandle, void *pMemPtr); - -extern "C" void * dpMallocCb(const void *clientHandle, NvLength size) -{ - return dpMalloc(size); -} - -extern "C" void dpFreeCb(const void *clientHandle, void *pMemPtr) -{ - dpFree(pMemPtr); -} - ConnectorImpl::ConnectorImpl(MainLink * main, AuxBus * auxBus, Timer * timer, Connector::EventSink * sink) : main(main), auxBus(auxBus), @@ -116,6 +100,7 @@ bKeepOptLinkAlive(false), bNoFallbackInPostLQA(false), LT2FecLatencyMs(0), + bFECEnable(false), bDscCapBasedOnParent(false), ResStatus(this) { @@ -126,7 +111,6 @@ constructorFailed = true; return; } - highestAssessedLC = getMaxLinkConfig(); firmwareGroup = createFirmwareGroup(); if (firmwareGroup == NULL) @@ -135,6 +119,9 @@ return; } + main->queryGPUCapability(); + main->queryAndUpdateDfpParams(); + hal->setPC2Disabled(main->isPC2Disabled()); // @@ -149,17 +136,12 @@ // Set if LTTPR training is supported per regKey hal->setLttprSupported(main->isLttprSupported()); + const DP_REGKEY_DATABASE& dpRegkeyDatabase = main->getRegkeyDatabase(); this->applyRegkeyOverrides(dpRegkeyDatabase); hal->applyRegkeyOverrides(dpRegkeyDatabase); - // Initialize DSC callbacks - DSC_CALLBACK callback; - callback.clientHandle = NULL; - callback.dscPrint = NULL; - callback.dscMalloc = dpMallocCb; - callback.dscFree = dpFreeCb; - DSC_InitializeCallback(callback); + highestAssessedLC = getMaxLinkConfig(); } void ConnectorImpl::applyRegkeyOverrides(const DP_REGKEY_DATABASE& dpRegkeyDatabase) @@ -188,7 +170,6 @@ this->bDisableSSC = dpRegkeyDatabase.bSscDisabled; this->bEnableFastLT = dpRegkeyDatabase.bFastLinkTrainingEnabled; this->bDscMstCapBug3143315 = dpRegkeyDatabase.bDscMstCapBug3143315; - this->bEnableOuiRestoring = dpRegkeyDatabase.bEnableOuiRestoring; this->bPowerDownPhyBeforeD3 = dpRegkeyDatabase.bPowerDownPhyBeforeD3; this->bReassessMaxLink = dpRegkeyDatabase.bReassessMaxLink; } @@ -687,6 +668,28 @@ } } + if (newDev->peerDevice == Dongle) + { + // For Dongle, we need to read detailed port caps if DPCD access is available on DP 1.4+. + if (newDev->isAtLeastVersion(1,4)) + { + newDev->getPCONCaps(&(newDev->pconCaps)); + } + + // + // If dongle does not have DPCD access but it is native PCON with Virtual peer support, + // we can get dongle port capabilities from parent VP DPCD detailed port descriptors. + // + else if (newDev->parent && (newDev->parent)->isVirtualPeerDevice()) + { + if (!main->isMSTPCONCapsReadDisabled()) + { + newDev->parent->getPCONCaps(&(newDev->pconCaps)); + newDev->connectorType = newDev->parent->getConnectorType(); + } + } + } + // Read panel replay capabilities newDev->getPanelReplayCaps(); @@ -707,7 +710,7 @@ newDev->applyOUIOverrides(); - if (main->isEDP() && this->bEnableOuiRestoring) + if (main->isEDP()) { // Save Source OUI information for eDP. hal->getOuiSource(cachedSourceOUI, &cachedSourceModelName[0], @@ -1103,6 +1106,7 @@ { DP_ASSERT( compoundQueryActive ); ModesetInfo localModesetInfo = modesetParams.modesetInfo; + NVT_STATUS result; compoundQueryCount++; @@ -1198,6 +1202,7 @@ NvU64 availableBandwidthBitsPerSecond = 0; unsigned PPS[DSC_MAX_PPS_SIZE_DWORD]; unsigned bitsPerPixelX16 = 0; + bool bDscBppForced = false; if (!pDscParams->bitsPerPixelX16) { @@ -1207,6 +1212,10 @@ // pDscParams->bitsPerPixelX16 = PREDEFINED_DSC_MST_BPPX16; } + else + { + bDscBppForced = true; + } bitsPerPixelX16 = pDscParams->bitsPerPixelX16; @@ -1279,10 +1288,34 @@ warData.dpData.hBlank = modesetParams.modesetInfo.rasterWidth - modesetParams.modesetInfo.surfaceWidth; warData.connectorType = DSC_DP; - if ((DSC_GeneratePPS(&dscInfo, &modesetInfoDSC, - &warData, availableBandwidthBitsPerSecond, - (NvU32*)(PPS), - (NvU32*)(&bitsPerPixelX16))) != NVT_STATUS_SUCCESS) + DSC_GENERATE_PPS_OPAQUE_WORKAREA *pScratchBuffer = nullptr; + pScratchBuffer = (DSC_GENERATE_PPS_OPAQUE_WORKAREA*) dpMalloc(sizeof(DSC_GENERATE_PPS_OPAQUE_WORKAREA)); + + result = DSC_GeneratePPS(&dscInfo, &modesetInfoDSC, + &warData, availableBandwidthBitsPerSecond, + (NvU32*)(PPS), + (NvU32*)(&bitsPerPixelX16), pScratchBuffer); + + // Try max dsc compression bpp = 8 once to check if that can support that mode. + if (result != NVT_STATUS_SUCCESS && !bDscBppForced) + { + pDscParams->bitsPerPixelX16 = MAX_DSC_COMPRESSION_BPPX16; + + bitsPerPixelX16 = pDscParams->bitsPerPixelX16; + + result = DSC_GeneratePPS(&dscInfo, &modesetInfoDSC, + &warData, availableBandwidthBitsPerSecond, + (NvU32*)(PPS), + (NvU32*)(&bitsPerPixelX16), pScratchBuffer); + } + + if (pScratchBuffer) + { + dpFree(pScratchBuffer); + pScratchBuffer = nullptr; + } + + if (result != NVT_STATUS_SUCCESS) { // // If generating PPS failed @@ -1321,7 +1354,50 @@ localModesetInfo.bEnableDsc = true; localModesetInfo.depth = bitsPerPixelX16; - if (dev->devDoingDscDecompression != dev) + if (dev->peerDevice == Dongle && dev->connectorType == connectorHDMI) + { + // + // For DP2HDMI PCON, if FRL BW is available in detailed caps, + // we need to check if we have enough BW for the stream on FRL link. + // + if (dev->pconCaps.maxHdmiLinkBandwidthGbps != 0) + { + NvU64 requiredBW = (NvU64)(modesetParams.modesetInfo.pixelClockHz * modesetParams.modesetInfo.depth); + NvU64 availableBw = (NvU64)(dev->pconCaps.maxHdmiLinkBandwidthGbps * (NvU64)1000000000); + if (requiredBW > availableBw) + { + compoundQueryResult = false; + pDscParams->bEnableDsc = false; + return false; + } + } + // + // If DP2HDMI PCON does not support FRL, but advertises TMDS + // Character clock rate on detailed caps, we need to honor that. + // + else if (dev->pconCaps.maxTmdsClkRate != 0) + { + NvU64 maxTmdsClkRateU64 = (NvU64)(dev->pconCaps.maxTmdsClkRate); + NvU64 requiredBw = (NvU64)(modesetParams.modesetInfo.pixelClockHz * modesetParams.modesetInfo.depth); + if (modesetParams.colorFormat == dpColorFormat_YCbCr420) + { + if (maxTmdsClkRateU64 < ((requiredBw/24)/2)) + { + compoundQueryResult = false; + return false; + } + } + else + { + if (maxTmdsClkRateU64 < (requiredBw/24)) + { + compoundQueryResult = false; + return false; + } + } + } + } + else if (dev->devDoingDscDecompression != dev) { // // Device's parent is doing DSC decompression so we need to check @@ -1526,10 +1602,21 @@ warData.dpData.dpMode = DSC_DP_SST; warData.connectorType = DSC_DP; - if ((DSC_GeneratePPS(&dscInfo, &modesetInfoDSC, - &warData, availableBandwidthBitsPerSecond, - (NvU32*)(PPS), - (NvU32*)(&bitsPerPixelX16))) != NVT_STATUS_SUCCESS) + DSC_GENERATE_PPS_OPAQUE_WORKAREA *pScratchBuffer = nullptr; + pScratchBuffer = (DSC_GENERATE_PPS_OPAQUE_WORKAREA*)dpMalloc(sizeof(DSC_GENERATE_PPS_OPAQUE_WORKAREA)); + + bool bPpsFailure = ((DSC_GeneratePPS(&dscInfo, &modesetInfoDSC, + &warData, availableBandwidthBitsPerSecond, + (NvU32*)(PPS), + (NvU32*)(&bitsPerPixelX16), + pScratchBuffer)) != NVT_STATUS_SUCCESS); + if (pScratchBuffer) + { + dpFree(pScratchBuffer); + pScratchBuffer = nullptr; + } + + if (bPpsFailure) { compoundQueryResult = false; pDscParams->bEnableDsc = false; @@ -1862,7 +1949,7 @@ bool ConnectorImpl::endCompoundQuery() { - DP_ASSERT( compoundQueryActive && "Spurious compoundQuery end."); + DP_ASSERT(compoundQueryActive && "Spurious compoundQuery end."); compoundQueryActive = false; return compoundQueryResult; } @@ -1891,7 +1978,7 @@ { if (!isLinkQuiesced) { - DP_ASSERT(0 && "Link is already in use."); + DP_LOG(("DPCONN> Link is already in use.")); return; } @@ -2703,7 +2790,7 @@ highestAssessedLC.enableFEC(this->bFECEnable); - if (main->isEDP() && this->bEnableOuiRestoring) + if (main->isEDP()) { main->configurePowerState(true); hal->setOuiSource(cachedSourceOUI, &cachedSourceModelName[0], 6 /* string length of ieeeOuiDevId */, @@ -3138,8 +3225,6 @@ bool ConnectorImpl::assessPCONLinkCapability(PCONLinkControl *pConControl) { - NvU32 status; - if (pConControl == NULL || !this->previousPlugged) return false; @@ -3152,8 +3237,7 @@ if (pConControl->flags.bSourceControlMode) { - status = trainPCONFrlLink(pConControl); - if (status == false) + if (trainPCONFrlLink(pConControl) == false) { // restore Autonomous mode and treat this as an active DP dongle. hal->resetProtocolConverter(); @@ -3164,12 +3248,17 @@ bSkipAssessLinkForPCon = false; assessLink(); } - return status; + return false; } activePConLinkControl.flags = pConControl->flags; activePConLinkControl.frlHdmiBwMask = pConControl->frlHdmiBwMask; activePConLinkControl.result = pConControl->result; } + else + { + // restore Autonomous mode and treat this as an active DP dongle. + hal->resetProtocolConverter(); + } // Step 3: Assess DP Link capability. LinkConfiguration lConfig = getMaxLinkConfig(); @@ -3195,7 +3284,7 @@ disableFlush(); this->bKeepLinkAliveForPCON = pConControl->flags.bKeepPCONLinkAlive; - return status; + return true; } bool ConnectorImpl::getOuiSink(unsigned &ouiId, char * modelName, size_t modelNameBufferSize, NvU8 & chipRevision) @@ -4654,7 +4743,7 @@ { LinkTrainingType preferredTrainingType = trainType; bool result; - bool bEnableFecOnSor; + // // Validate link config against caps // @@ -4746,17 +4835,7 @@ result = postLTAdjustment(activeLinkConfig, force); } - bEnableFecOnSor = lConfig.bEnableFEC; - - if (main->isEDP()) - { - DeviceImpl * nativeDev = findDeviceInList(Address()); - - if (nativeDev && nativeDev->bIsPreviouslyFakedMuxDevice) - bEnableFecOnSor = activeLinkConfig.bEnableFEC; - } - - if((lConfig.lanes != 0) && result && bEnableFecOnSor) + if((lConfig.lanes != 0) && result && activeLinkConfig.bEnableFEC) { // // Extended latency from link-train end to FEC enable pattern @@ -5676,7 +5755,7 @@ // Reset all settings for previous downstream device configInit(); - if (! hal->isAtLeastVersion(1, 0 ) ) + if (!hal->isAtLeastVersion(1, 0)) goto completed; DP_LOG(("DP> HPD v%d.%d", hal->getRevisionMajor(), hal->getRevisionMinor())); @@ -5972,7 +6051,7 @@ if (this->bReassessMaxLink) { // - // If the highest assessed LC is not equal to + // If the highest assessed LC is not equal to // max possible link config, re-assess link // NvU8 retries = 0U; @@ -6958,7 +7037,6 @@ { // Query current GPU capabilities. main->queryGPUCapability(); - } void ConnectorImpl::notifyHBR2WAREngage() diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/common/displayport/src/dp_deviceimpl.cpp nvidia-open-gpu-kernel-modules-535.161.08/src/common/displayport/src/dp_deviceimpl.cpp --- nvidia-open-gpu-kernel-modules-525.147.05/src/common/displayport/src/dp_deviceimpl.cpp 2023-10-25 20:22:25.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/common/displayport/src/dp_deviceimpl.cpp 2024-03-05 22:12:00.000000000 +0000 @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 1993-2021 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 1993-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -94,6 +94,7 @@ bIgnoreMsaCap(false), bIgnoreMsaCapCached(false), bSdpExtCapable(Indeterminate), + bAsyncSDPCapable(Indeterminate), bDscPassThroughColorFormatWar(false) { bandwidth.enum_path.dataValid = false; @@ -928,7 +929,7 @@ // color formats that are listed in 0x69h even in pass through mode. // this->bDscPassThroughColorFormatWar = true; - + if ((buffer[8] == 0x31) || (buffer[8] == 0x20)) { this->bSdpExtCapable = False; @@ -953,6 +954,53 @@ } } +bool DeviceImpl::getAsyncSDPSupported() +{ + NvU8 byte = 0; + unsigned size = 1; + unsigned sizeCompleted; + unsigned nakReason = NakUndefined; + // + // On faked mux devices, we cannot check if the device has + // the capability as we don't have access to aux. + // + if (this->isFakedMuxDevice()) + { + return false; + } + // If the capability is queried/set already. + if (this->bAsyncSDPCapable != Indeterminate) + { + return (this->bAsyncSDPCapable == True); + } + // Check device capabilities first. + if (AuxBus::success != this->getDpcdData(NV_DPCD_DOWN_STREAM_PORT, &byte, + size, &sizeCompleted, &nakReason) || + (FLD_TEST_DRF(_DPCD, _DOWN_STREAM_PORT, _MSA_TIMING_PAR_IGNORED, _NO, byte))) + { + this->bAsyncSDPCapable = False; + return false; + } + if (AuxBus::success != this->getDpcdData(NV_DPCD14_DPRX_FEATURE_ENUM_LIST, &byte, + size, &sizeCompleted, &nakReason) || + (FLD_TEST_DRF(_DPCD14, _DPRX_FEATURE_ENUM_LIST, _ADAPTIVE_SYNC_SDP_SUPPORTED, _NO, byte))) + { + this->bAsyncSDPCapable = False; + return false; + } + if (this->isMultistream()) + { + // For MST devices, check root branch capability. + this->bAsyncSDPCapable = hal->getRootAsyncSDPSupported() ? True : False; + } + else + { + // For SST, it supports Async SDP once reaches here. + this->bAsyncSDPCapable = True; + } + return (this->bAsyncSDPCapable == True); +} + bool DeviceImpl::getSDPExtnForColorimetrySupported() { DeviceImpl *targetDevice = NULL; @@ -1020,6 +1068,12 @@ } } + if (!targetDevice) + { + DP_ASSERT(0 && "targetDevice is invalid for SDP_EXT COLORIMETRY"); + return false; + } + // Send remote DPCD for devices behind the branch if ((AuxBus::success == targetDevice->getDpcdData(NV_DPCD_TRAINING_AUX_RD_INTERVAL, &byte, sizeof byte, &size, &nakReason)) && @@ -1279,7 +1333,9 @@ if (nack.reason == NakDefer || nack.reason == NakTimeout) continue; - bandwidth.enum_path.total = bandwidth.enum_path.free = 0; + bandwidth.enum_path.total = 0; + bandwidth.enum_path.free = 0; + bandwidth.enum_path.availableStreams = 0; break; } else @@ -1287,6 +1343,8 @@ bandwidth.enum_path.total = epr.reply.TotalPBN; bandwidth.enum_path.free = epr.reply.FreePBN; bandwidth.enum_path.bPathFECCapable = epr.reply.bFECCapability; + bandwidth.enum_path.availableStreams = epr.reply.availableStreams; + break; } } @@ -1610,11 +1668,10 @@ return true; } else - { + { return false; } } - bool DeviceImpl::getFECSupport() { NvU8 byte = 0; @@ -1810,7 +1867,7 @@ return false; } - dscCaps.branchDSCOverallThroughputMode0 = DRF_VAL(_DPCD20, _BRANCH_DSC_OVERALL_THROUGHPUT_MODE_0, _VALUE, buffer[0x0]); + dscCaps.branchDSCOverallThroughputMode0 = DRF_VAL(_DPCD14, _BRANCH_DSC_OVERALL_THROUGHPUT_MODE_0, _VALUE, buffer[0x0]); if (dscCaps.branchDSCOverallThroughputMode0 == 1) { dscCaps.branchDSCOverallThroughputMode0 = 680; @@ -1820,7 +1877,7 @@ dscCaps.branchDSCOverallThroughputMode0 = 600 + dscCaps.branchDSCOverallThroughputMode0 * 50; } - dscCaps.branchDSCOverallThroughputMode1 = DRF_VAL(_DPCD20, _BRANCH_DSC_OVERALL_THROUGHPUT_MODE_1, _VALUE, buffer[0x1]); + dscCaps.branchDSCOverallThroughputMode1 = DRF_VAL(_DPCD14, _BRANCH_DSC_OVERALL_THROUGHPUT_MODE_1, _VALUE, buffer[0x1]); if (dscCaps.branchDSCOverallThroughputMode1 == 1) { dscCaps.branchDSCOverallThroughputMode1 = 680; @@ -1830,7 +1887,7 @@ dscCaps.branchDSCOverallThroughputMode1 = 600 + dscCaps.branchDSCOverallThroughputMode1 * 50; } - dscCaps.branchDSCMaximumLineBufferWidth = DRF_VAL(_DPCD20, _BRANCH_DSC_MAXIMUM_LINE_BUFFER_WIDTH, _VALUE, buffer[0x2]); + dscCaps.branchDSCMaximumLineBufferWidth = DRF_VAL(_DPCD14, _BRANCH_DSC_MAXIMUM_LINE_BUFFER_WIDTH, _VALUE, buffer[0x2]); if (dscCaps.branchDSCMaximumLineBufferWidth != 0) { if (dscCaps.branchDSCMaximumLineBufferWidth >= 16) @@ -1871,8 +1928,10 @@ unsigned nakReason = NakUndefined; NvU8 rawBranchSpecificDscCaps[3]; - if(AuxBus::success != this->getDpcdData(NV_DPCD20_BRANCH_DSC_OVERALL_THROUGHPUT_MODE_0, - &rawBranchSpecificDscCaps[0], sizeof(rawBranchSpecificDscCaps), &sizeCompleted, &nakReason)) + if(AuxBus::success != this->getDpcdData(NV_DPCD14_BRANCH_DSC_OVERALL_THROUGHPUT_MODE_0, + &rawBranchSpecificDscCaps[0], + sizeof(rawBranchSpecificDscCaps), + &sizeCompleted, &nakReason)) { return false; } @@ -1887,8 +1946,8 @@ Address::StringBuffer sb; DP_USED(sb); - if(AuxBus::success == this->getDpcdData(NV_DPCD20_GUID_2, - &this->guid2.data[0], DPCD_GUID_SIZE, &sizeCompleted, &nakReason)) + if(AuxBus::success == this->getDpcdData(NV_DPCD14_GUID_2, &this->guid2.data[0], + DPCD_GUID_SIZE, &sizeCompleted, &nakReason)) { if (!(this->guid2.isGuidZero())) { @@ -1954,8 +2013,8 @@ else { // - // Check the device's own and its parent's DSC capability. - // - Sink device will do DSC cecompression when + // Check the device's own and its parent's DSC capability. + // - Sink device will do DSC cecompression when // 1. Sink device is capable of DSC decompression // 2. Sink is on a logical port (8-15) // @@ -1965,7 +2024,7 @@ // 2. Parent of sink is a Virtual Peer device // 3. Parent of sink supports DSC Pass through // - // - Sink device's parent will do DSC decompression + // - Sink device's parent will do DSC decompression // 1. Above conditions are not true. // 2. Parent of sink supports DSC decompression. // @@ -1978,11 +2037,11 @@ this->devDoingDscDecompression = this; this->bDSCPossible = true; } - else if (this->parent->isVirtualPeerDevice() && + else if (this->parent->isVirtualPeerDevice() && this->parent->isDSCPassThroughSupported()) { // - // This condition takes care of DSC capable sink devices + // This condition takes care of DSC capable sink devices // connected behind a DSC Pass through capable branch // this->devDoingDscDecompression = this; @@ -1991,12 +2050,12 @@ else if (this->parent->isDSCDecompressionSupported()) { // - // This condition takes care of DSC capable sink devices + // This condition takes care of DSC capable sink devices // connected behind a branch device that is not capable // of DSC pass through but can do DSC decompression. // this->bDSCPossible = true; - this->devDoingDscDecompression = this->parent; + this->devDoingDscDecompression = this->parent; } } else @@ -2012,7 +2071,7 @@ else if (this->parent && this->parent->isDSCDecompressionSupported()) { // - // This condition takes care of sink devices not capable of DSC + // This condition takes care of sink devices not capable of DSC // but parent is capable of DSC decompression. // this->bDSCPossible = true; @@ -2032,7 +2091,7 @@ bool DeviceImpl::setDscEnable(bool enable) { - NvU8 dscEnableByte = 0; + NvU8 dscEnableByte = 0; NvU8 dscPassthroughByte = 0; unsigned size = 0; unsigned nakReason = NakUndefined; @@ -2049,12 +2108,12 @@ return false; } - if ((this->devDoingDscDecompression == this) && !this->isLogical() && this->parent != NULL) + if ((this->devDoingDscDecompression == this) && !this->isLogical() && !(this->peerDevice == Dongle) && this->parent != NULL) { // // If the device has a parent, that means the sink is on a MST link and - // and on a MST link if DSC is possible on the path and devDoingDscDecompression - // is the sink itself and sink is not on a logical port, then the parent should be + // and on a MST link if DSC is possible on the path and devDoingDscDecompression + // is the sink itself and sink is not on a logical port, then the parent should be // DSC Pass through capable. // bDscPassThrough = true; @@ -2064,7 +2123,7 @@ // Get Current DSC Enable State // Ideally we don't need to check the current state but Synaptics DSC device, // which was used for inital DSC code developement did not follow spec and so - // we have added this code. Overwriting the same value should not have any + // we have added this code. Overwriting the same value should not have any // impact as per the spec. Will remove this check once all DSC devices follow spec. // if (!getDscEnable(&bCurrDscEnable)) @@ -2077,7 +2136,7 @@ { if(bDscPassThrough) { - dscPassthroughByte = FLD_SET_DRF(_DPCD20, _DSC_PASS_THROUGH, _ENABLE, _YES, dscPassthroughByte); + dscPassthroughByte = FLD_SET_DRF(_DPCD20, _DSC_ENABLE, _PASS_THROUGH, _YES, dscPassthroughByte); DP_LOG(("DP-DEV> Enabling DSC Pass through on branch device - %s", this->parent->getTopologyAddress().toString(buffer))); } @@ -2090,7 +2149,7 @@ } else { - DP_LOG(("DP-DEV> DSC decompression is already enabled on device - %s", + DP_LOG(("DP-DEV> DSC decompression is already enabled on device - %s", this->devDoingDscDecompression->getTopologyAddress().toString(buffer))); } } @@ -2098,7 +2157,7 @@ { if(bDscPassThrough) { - dscPassthroughByte = FLD_SET_DRF(_DPCD20, _DSC_PASS_THROUGH, _ENABLE, _NO, dscPassthroughByte); + dscPassthroughByte = FLD_SET_DRF(_DPCD20, _DSC_ENABLE, _PASS_THROUGH, _NO, dscPassthroughByte); DP_LOG(("DP-DEV> Disabling DSC Pass through on branch device - %s", this->parent->getTopologyAddress().toString(buffer))); } @@ -2111,18 +2170,18 @@ } else { - DP_LOG(("DP-DEV> DSC decompression is already disabled on device - %s", + DP_LOG(("DP-DEV> DSC decompression is already disabled on device - %s", this->devDoingDscDecompression->getTopologyAddress().toString(buffer))); } } if (bDscPassThrough) { - dscPassThroughStatus = this->parent->setDpcdData(NV_DPCD20_DSC_PASS_THROUGH, + dscPassThroughStatus = this->parent->setDpcdData(NV_DPCD14_DSC_ENABLE, &dscPassthroughByte, sizeof dscPassthroughByte, &size, &nakReason); if (dscPassThroughStatus != AuxBus::success) { - DP_LOG(("DP-DEV> Setting DSC Passthrough on parent branch %s failed", + DP_LOG(("DP-DEV> Setting DSC Passthrough on parent branch %s failed", this->parent->getTopologyAddress().toString(buffer))); } } @@ -2133,9 +2192,9 @@ &dscEnableByte, sizeof dscEnableByte, &size, &nakReason); if (dscEnableStatus != AuxBus::success) { - DP_LOG(("DP-DEV> Setting DSC Enable on sink %s failed", + DP_LOG(("DP-DEV> Setting DSC Enable on sink %s failed", this->devDoingDscDecompression->getTopologyAddress().toString(buffer))); - + } } @@ -2153,7 +2212,7 @@ bool DeviceImpl::setDscEnableDPToHDMIPCON(bool bDscEnable, bool bEnablePassThroughForPCON) { - NvU8 dscEnableByte = 0; + NvU8 dscEnableByte = 0; unsigned size = 0; unsigned nakReason = NakUndefined; AuxBus::status dscEnableStatus = AuxBus::success; @@ -2170,7 +2229,7 @@ { if(bEnablePassThroughForPCON) { - dscEnableByte = FLD_SET_DRF(_DPCD20, _DSC_PASS_THROUGH, _ENABLE, _YES, dscEnableByte); + dscEnableByte = FLD_SET_DRF(_DPCD20, _DSC_ENABLE, _PASS_THROUGH, _YES, dscEnableByte); DP_LOG(("DP-DEV> Enabling DSC Pass through on DP to HDMI PCON device - %s", this->getTopologyAddress().toString(buffer))); } @@ -2188,10 +2247,10 @@ if (dscEnableStatus != AuxBus::success) { - DP_LOG(("DP-DEV> Setting DSC Enable on DP to HDMI PCON %s failed", + DP_LOG(("DP-DEV> Setting DSC Enable on DP to HDMI PCON %s failed", this->getTopologyAddress().toString(buffer))); return false; - + } return true; @@ -2361,51 +2420,76 @@ bool DeviceImpl::getPCONCaps(PCONCaps *pPCONCaps) { AuxBus::status status = AuxBus::success; - NvU32 addr = NV_DPCD_DETAILED_CAP_INFO_ONE(0); - NvU8 data = 0; - unsigned size = 1; + NvU32 addr = NV_DPCD_DETAILED_CAP_INFO_DWNSTRM_PORT(0); + NvU8 data[4] = {0}; unsigned sizeCompleted = 0; unsigned nakReason = 0; + NvU8 pConType = 0; - if (isMultistream()) - return false; - - status = getDpcdData(addr, &data, size, &sizeCompleted, &nakReason); - if (status != AuxBus::success) + status = this->getDpcdData(addr, &data[0], sizeof(data), &sizeCompleted, &nakReason); + if (status == AuxBus::success) { - return false; - } - pPCONCaps->maxTmdsClkRate = data; + pConType = DRF_VAL(_DPCD, _DETAILED_CAP_INFO, _DWNSTRM_PORT_TX_TYPE, data[0]); + if (pConType == NV_DPCD_DETAILED_CAP_INFO_DWNSTRM_PORT_TX_TYPE_HDMI) + { + this->connectorType = connectorHDMI; + pPCONCaps->maxTmdsClkRate = data[1] * 2500000; - addr = NV_DPCD_DETAILED_CAP_INFO_TWO(0); - status = getDpcdData(addr, &data, size, &sizeCompleted, &nakReason); - if (status != AuxBus::success) - { - return false; - } + pPCONCaps->bSourceControlModeSupported = + FLD_TEST_DRF(_DPCD, _DETAILED_CAP_INFO, _SRC_CONTROL_MODE_SUPPORT, _YES, data[2]); + pPCONCaps->bConcurrentLTSupported = + FLD_TEST_DRF(_DPCD, _DETAILED_CAP_INFO, _CONCURRENT_LT_SUPPORT, _YES, data[2]); + + switch (DRF_VAL(_DPCD, _DETAILED_CAP_INFO, _MAX_FRL_LINK_BW_SUPPORT, data[2])) + { + case NV_DPCD_DETAILED_CAP_INFO_MAX_FRL_LINK_BW_SUPPORT_9G: + pPCONCaps->maxHdmiLinkBandwidthGbps = 9; + break; + case NV_DPCD_DETAILED_CAP_INFO_MAX_FRL_LINK_BW_SUPPORT_18G: + pPCONCaps->maxHdmiLinkBandwidthGbps = 18; + break; + case NV_DPCD_DETAILED_CAP_INFO_MAX_FRL_LINK_BW_SUPPORT_24G: + pPCONCaps->maxHdmiLinkBandwidthGbps = 24; + break; + case NV_DPCD_DETAILED_CAP_INFO_MAX_FRL_LINK_BW_SUPPORT_32G: + pPCONCaps->maxHdmiLinkBandwidthGbps = 32; + break; + case NV_DPCD_DETAILED_CAP_INFO_MAX_FRL_LINK_BW_SUPPORT_40G: + pPCONCaps->maxHdmiLinkBandwidthGbps = 40; + break; + case NV_DPCD_DETAILED_CAP_INFO_MAX_FRL_LINK_BW_SUPPORT_48G: + pPCONCaps->maxHdmiLinkBandwidthGbps = 48; + break; + default: + pPCONCaps->maxHdmiLinkBandwidthGbps = 0; + break; + } - pPCONCaps->bSourceControlModeSupported = - FLD_TEST_DRF(_DPCD, _DETAILED_CAP_INFO, _SRC_CONTROL_MODE_SUPPORT, _YES, data); - pPCONCaps->bConcurrentLTSupported = - FLD_TEST_DRF(_DPCD, _DETAILED_CAP_INFO, _CONCURRENT_LT_SUPPORT, _YES, data); - pPCONCaps->maxHdmiLinkBandwidthGbps = - DRF_VAL(_DPCD, _DETAILED_CAP_INFO, _MAX_FRL_LINK_BW_SUPPORT, data); + switch (DRF_VAL(_DPCD, _DETAILED_CAP_INFO, _MAX_BITS_PER_COMPONENT_DEF, data[2])) + { + case NV_DPCD_DETAILED_CAP_INFO_MAX_BITS_PER_COMPONENT_DEF_10BPC: + pPCONCaps->maxBpc = 10; + break; + case NV_DPCD_DETAILED_CAP_INFO_MAX_BITS_PER_COMPONENT_DEF_12BPC: + pPCONCaps->maxBpc = 12; + break; + case NV_DPCD_DETAILED_CAP_INFO_MAX_BITS_PER_COMPONENT_DEF_16BPC: + pPCONCaps->maxBpc = 16; + break; + case NV_DPCD_DETAILED_CAP_INFO_MAX_BITS_PER_COMPONENT_DEF_8BPC: + default: + pPCONCaps->maxBpc = 8; + break; + } - switch (DRF_VAL(_DPCD, _DETAILED_CAP_INFO, _MAX_BITS_PER_COMPONENT_DEF, data)) + DP_LOG((" DP2HDMI PCON caps - Max TMDS Clk: %u LinkBWGbps: %u MaxBpc: %u", + pPCONCaps->maxTmdsClkRate, pPCONCaps->maxHdmiLinkBandwidthGbps, pPCONCaps->maxBpc)); + } + } + else { - case NV_DPCD_DETAILED_CAP_INFO_MAX_BITS_PER_COMPONENT_DEF_10BPC: - pPCONCaps->maxBpc = 10; - break; - case NV_DPCD_DETAILED_CAP_INFO_MAX_BITS_PER_COMPONENT_DEF_12BPC: - pPCONCaps->maxBpc = 12; - break; - case NV_DPCD_DETAILED_CAP_INFO_MAX_BITS_PER_COMPONENT_DEF_16BPC: - pPCONCaps->maxBpc = 16; - break; - case NV_DPCD_DETAILED_CAP_INFO_MAX_BITS_PER_COMPONENT_DEF_8BPC: - default: - pPCONCaps->maxBpc = 8; - break; + DP_LOG((" DP-DEV> Error - DPCD Read for detailed port capabilities (0x80) failed.")); + return false; } return true; } diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/common/displayport/src/dp_edid.cpp nvidia-open-gpu-kernel-modules-535.161.08/src/common/displayport/src/dp_edid.cpp --- nvidia-open-gpu-kernel-modules-525.147.05/src/common/displayport/src/dp_edid.cpp 2023-10-25 20:22:25.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/common/displayport/src/dp_edid.cpp 2024-03-05 22:12:00.000000000 +0000 @@ -193,9 +193,11 @@ fallbackEdid = false; patchedChecksum = false; - // clear the WARFlags - _WARFlags temp = {0}; - WARFlags = temp; + // clear the WARFlags and WARData. + _WARFlags flagTemp = {0}; + _WARData dataTemp = {0}; + WARFlags = flagTemp; + WARData = dataTemp; } Edid::~Edid() diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/common/displayport/src/dp_evoadapter.cpp nvidia-open-gpu-kernel-modules-535.161.08/src/common/displayport/src/dp_evoadapter.cpp --- nvidia-open-gpu-kernel-modules-525.147.05/src/common/displayport/src/dp_evoadapter.cpp 2023-10-25 20:22:25.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/common/displayport/src/dp_evoadapter.cpp 2024-03-05 22:12:00.000000000 +0000 @@ -40,7 +40,6 @@ #include #include #include - using namespace DisplayPort; // @@ -94,10 +93,10 @@ {NV_DP_REGKEY_KEEP_OPT_LINK_ALIVE_SST, &dpRegkeyDatabase.bOptLinkKeptAliveSst, DP_REG_VAL_BOOL}, {NV_DP_REGKEY_FORCE_EDP_ILR, &dpRegkeyDatabase.bBypassEDPRevCheck, DP_REG_VAL_BOOL}, {NV_DP_DSC_MST_CAP_BUG_3143315, &dpRegkeyDatabase.bDscMstCapBug3143315, DP_REG_VAL_BOOL}, - {NV_DP_REGKEY_ENABLE_OUI_RESTORING, &dpRegkeyDatabase.bEnableOuiRestoring, DP_REG_VAL_BOOL}, {NV_DP_CHECK_FEC_FOR_DDS_DSC_PANEL, &dpRegkeyDatabase.bCheckFECForDynamicMuxDSCPanel, DP_REG_VAL_BOOL}, {NV_DP_REGKEY_POWER_DOWN_PHY, &dpRegkeyDatabase.bPowerDownPhyBeforeD3, DP_REG_VAL_BOOL}, - {NV_DP_REGKEY_REASSESS_MAX_LINK, &dpRegkeyDatabase.bReassessMaxLink, DP_REG_VAL_BOOL} + {NV_DP_REGKEY_REASSESS_MAX_LINK, &dpRegkeyDatabase.bReassessMaxLink, DP_REG_VAL_BOOL}, + {NV_DP_REGKEY_MST_PCON_CAPS_READ_DISABLED, &dpRegkeyDatabase.bMSTPCONCapsReadDisabled, DP_REG_VAL_BOOL} }; EvoMainLink::EvoMainLink(EvoInterface * provider, Timer * timer) : @@ -119,9 +118,6 @@ _isLTPhyRepeaterSupported = true; _rmPhyRepeaterCount = 0; dpMemZero(&_DSC, sizeof(_DSC)); - queryGPUCapability(); - - queryAndUpdateDfpParams(); // // Tell RM to hands off on the DisplayPort hardware @@ -899,6 +895,7 @@ _applyLinkBwOverrideWarRegVal = dpRegkeyDatabase.bLinkBwOverrideWarApplied; _enableMSAOverrideOverMST = dpRegkeyDatabase.bMsaOverMstEnabled; _enableFecCheckForDDS = dpRegkeyDatabase.bCheckFECForDynamicMuxDSCPanel; + _isMSTPCONCapsReadDisabled = dpRegkeyDatabase.bMSTPCONCapsReadDisabled; } NvU32 EvoMainLink::getRegkeyValue(const char *key) @@ -1050,7 +1047,6 @@ case EDP_3_24GHZ: case EDP_4_32GHZ: case HBR2: - case EDP_6_75GHZ: case HBR3: linkBw = linkrate / DP_LINK_BW_FREQ_MULTI_MBPS; dpCtrlData = FLD_SET_DRF_NUM(0073_CTRL, _DP_DATA, _SET_LINK_BW, @@ -1167,7 +1163,7 @@ // if (!requestRmLC.lowerConfig()) { - // If no valid link config could be found, break here. + // If no valid link config could be found, break here. break; } fallback = true; @@ -1516,6 +1512,10 @@ return _skipPowerdownEDPPanelWhenHeadDetach; } +bool EvoMainLink::isMSTPCONCapsReadDisabled() +{ + return _isMSTPCONCapsReadDisabled; +} bool EvoMainLink::isActive() { @@ -1814,7 +1814,6 @@ case linkBW_3_24Gbps: case linkBW_4_32Gbps: case linkBW_5_40Gbps: - case linkBW_6_75Gbps: case linkBW_8_10Gbps: pLinkRates->import(params.linkBwTbl[i]); break; diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/common/displayport/src/dp_messagecodings.cpp nvidia-open-gpu-kernel-modules-535.161.08/src/common/displayport/src/dp_messagecodings.cpp --- nvidia-open-gpu-kernel-modules-525.147.05/src/common/displayport/src/dp_messagecodings.cpp 2023-10-25 20:22:26.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/common/displayport/src/dp_messagecodings.cpp 2024-03-05 22:12:00.000000000 +0000 @@ -227,11 +227,11 @@ ParseResponseStatus EnumPathResMessage::parseResponseAck(EncodedMessage * message, BitStreamReader * reader) { - reply.portNumber = reader->readOrDefault(4 /*Port_Number*/, 0xF); - reader->readOrDefault(3 /*zeroes*/, 0); - reply.bFECCapability = (reader->readOrDefault(1 /*FEC*/, 0x0) == 1) ? true : false; - reply.TotalPBN = reader->readOrDefault(16 /*PBN*/, 0xFFFF); - reply.FreePBN = reader->readOrDefault(16 /*PBN*/, 0xFFFF); + reply.portNumber = reader->readOrDefault(4 /*Port_Number*/, 0xF); + reply.availableStreams = reader->readOrDefault(3 /*Available_Streams*/, 0); + reply.bFECCapability = (reader->readOrDefault(1 /*FEC*/, 0x0) == 1) ? true : false; + reply.TotalPBN = reader->readOrDefault(16 /*PBN*/, 0xFFFF); + reply.FreePBN = reader->readOrDefault(16 /*PBN*/, 0xFFFF); if (this->getSinkPort() != reply.portNumber) return ParseResponseWrong; @@ -353,10 +353,11 @@ bool status; // read the request body - request.port = reader->readOrDefault(4/*Port_Number*/, 0xF); - reader->readOrDefault(4/*zeroes*/, 0); - status = DisplayPort::extractGUID(reader, &request.guid); - request.PBN = reader->readOrDefault(16/*Available_PBN*/, 0); + request.port = reader->readOrDefault(4 /*Port_Number*/, 0xF); + request.availableStreams = reader->readOrDefault(3 /*Available_Streams*/, 0); + request.bFECCapability = reader->readOrDefault(1 /*FEC Capability*/, 0); + status = DisplayPort::extractGUID(reader, &request.guid); + request.PBN = reader->readOrDefault(16/*Available_PBN*/, 0); // action will be implemented by evensink this->sink->messageProcessed(this); diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/common/inc/displayport/displayport.h nvidia-open-gpu-kernel-modules-535.161.08/src/common/inc/displayport/displayport.h --- nvidia-open-gpu-kernel-modules-525.147.05/src/common/inc/displayport/displayport.h 2023-10-25 20:22:14.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/common/inc/displayport/displayport.h 2024-03-05 22:11:43.000000000 +0000 @@ -97,6 +97,7 @@ typedef enum { + // enum value unit = 270M linkBW_1_62Gbps = 0x06, linkBW_2_16Gbps = 0x08, linkBW_2_43Gbps = 0x09, @@ -104,7 +105,6 @@ linkBW_3_24Gbps = 0x0C, linkBW_4_32Gbps = 0x10, linkBW_5_40Gbps = 0x14, - linkBW_6_75Gbps = 0x19, linkBW_8_10Gbps = 0x1E, linkBW_Supported } DP_LINK_BANDWIDTH; @@ -119,11 +119,9 @@ linkSpeedId_2_43Gbps = 0x05, linkSpeedId_3_24Gbps = 0x06, linkSpeedId_4_32Gbps = 0x07, - linkSpeedId_6_75Gbps = 0x08, linkSpeedId_Supported } DP_LINK_SPEED_INDEX; - typedef enum { postCursor2_Level0 = 0, @@ -291,7 +289,7 @@ NvBool bSourceControlModeSupported; NvBool bConcurrentLTSupported; NvBool bConv444To420Supported; - NvU8 maxTmdsClkRate; + NvU32 maxTmdsClkRate; NvU8 maxBpc; NvU8 maxHdmiLinkBandwidthGbps; } PCONCaps; @@ -477,7 +475,7 @@ // Multiplier constant to get link frequency in KHZ // Maximum link rate of Main Link lanes = Value x 270M. // To get it to KHz unit, we need to multiply 270K. -#define DP_LINK_BW_FREQUENCY_MULTIPLIER_KHZ (270*1000) +#define DP_LINK_BW_FREQUENCY_MULTIPLIER_KHZ (270*1000) // Multiplier constant to get link rate table's in KHZ #define DP_LINK_RATE_TABLE_MULTIPLIER_KHZ 200 @@ -553,11 +551,11 @@ #define IS_INTERMEDIATE_LINKBW(val) (((NvU32)(val)==linkBW_2_16Gbps) || \ ((NvU32)(val)==linkBW_2_43Gbps) || \ ((NvU32)(val)==linkBW_3_24Gbps) || \ - ((NvU32)(val)==linkBW_4_32Gbps) || \ - ((NvU32)(val)==linkBW_6_75Gbps)) + ((NvU32)(val)==linkBW_4_32Gbps)) -#define IS_VALID_LINKBW(val) (IS_STANDARD_LINKBW(val) || \ +#define IS_VALID_LINKBW(val) (IS_STANDARD_LINKBW(val) || \ IS_INTERMEDIATE_LINKBW(val)) + // // Phy Repeater count read from DPCD offset F0002h is an // 8 bit value where each bit represents the total count diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/common/inc/displayport/dpcd14.h nvidia-open-gpu-kernel-modules-535.161.08/src/common/inc/displayport/dpcd14.h --- nvidia-open-gpu-kernel-modules-525.147.05/src/common/inc/displayport/dpcd14.h 2023-10-25 20:22:14.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/common/inc/displayport/dpcd14.h 2024-03-05 22:11:43.000000000 +0000 @@ -24,6 +24,8 @@ #ifndef _DISPLAYPORT14_H_ #define _DISPLAYPORT14_H_ +#define NV_DPCD14_GUID_2 (0x00000040) /* R-XUR */ + #define NV_DPCD14_EXTEND_CAP_BASE (0x00002200) #define NV_DPCD14_MAX_LINK_BANDWIDTH (0x00000001) /* R-XUR */ @@ -187,11 +189,6 @@ #define NV_DPCD14_DSC_BITS_PER_PIXEL_INCREMENT_SUPPORTED_1_2 (0x00000003) /* R-XUV */ #define NV_DPCD14_DSC_BITS_PER_PIXEL_INCREMENT_SUPPORTED_1 (0x00000004) /* R-XUV */ -// Field definition only used only with 128b/132b for DP2.0+ -#define NV_DPCD20_TRAINING_LANE_SET(i) (0x00000103+(i)) /* RW-1A */ -#define NV_DPCD20_TRAINING_LANE_SET__SIZE 4 /* RW--S */ -#define NV_DPCD20_TRAINING_LANE_SET_TX_FFE_PRESET_VALUE 3:0 /* RWXUF */ - #define NV_DPCD14_DSC_ENABLE (0x00000160) /* R-XUR */ #define NV_DPCD14_DSC_ENABLE_SINK 0:0 /* R-XUF */ #define NV_DPCD14_DSC_ENABLE_SINK_NO (0x00000000) /* R-XUV */ @@ -239,15 +236,6 @@ #define NV_DPCD14_TRAINING_PATTERN_SET_SYM_ERR_SEL_DISPARITY_ERROR (0x00000001) /* RWXUV */ #define NV_DPCD14_TRAINING_PATTERN_SET_SYM_ERR_SEL_ILLEGAL_SYMBOL_ERROR (0x00000002) /* RWXUV */ -// Field definition only used only with 128b/132b for DP2.0+ -#define NV_DPCD20_128B_132B_TRAINING_PATTERN (0x00000102) /* RWXUR */ -#define NV_DPCD20_128B_132B_TRAINING_PATTERN_SELECT 3:0 /* RWXUF */ -#define NV_DPCD20_128B_132B_TRAINING_PATTERN_SELECT_NONE (0x00000000) /* RWXUV */ -#define NV_DPCD20_128B_132B_TRAINING_PATTERN_SELECT_TPS1 (0x00000001) /* RWXUV */ -#define NV_DPCD20_128B_132B_TRAINING_PATTERN_SELECT_TPS2 (0x00000002) /* RWXUV */ -#define NV_DPCD20_128B_132B_TRAINING_PATTERN_SELECT_TPS2_CDS (0x00000003) /* RWXUV */ -// Note: Bit 7:4 are reserved for 128b/132b. Driver should keep them 0 - #define NV_DPCD14_LINK_QUAL_LANE_SET(i) (0x0000010B+(i)) /* RW-1A */ #define NV_DPCD14_LINK_QUAL_LANE_SET__SIZE 4 /* R---S */ #define NV_DPCD14_LINK_QUAL_LANE_SET_LQS 2:0 /* RWXUF */ @@ -270,36 +258,6 @@ #define NV_DPCD14_FEC_CONFIGURATION_LANE_SELECT_LANE_2 (0x00000002) /* RWXUV */ #define NV_DPCD14_FEC_CONFIGURATION_LANE_SELECT_LANE_3 (0x00000003) /* RWXUV */ -// Field definition only used only with 128b/132b for DP2.0+ -#define NV_DPCD20_LANE_ALIGN_STATUS_UPDATED (0x00000204) /* R-XUR */ -#define NV_DPCD20_LANE_ALIGN_STATUS_UPDATED_128B_132B_DPRX_EQ_INTERLANE_ALIGN_DONE 2:2 /* R-XUF */ -#define NV_DPCD20_LANE_ALIGN_STATUS_UPDATED_128B_132B_DPRX_EQ_INTERLANE_ALIGN_DONE_NO (0x00000000) /* R-XUV */ -#define NV_DPCD20_LANE_ALIGN_STATUS_UPDATED_128B_132B_DPRX_EQ_INTERLANE_ALIGN_DONE_YES (0x00000001) /* R-XUV */ -#define NV_DPCD20_LANE_ALIGN_STATUS_UPDATED_128B_132B_DPRX_CDS_INTERLANE_ALIGN_DONE 3:3 /* R-XUF */ -#define NV_DPCD20_LANE_ALIGN_STATUS_UPDATED_128B_132B_DPRX_CDS_INTERLANE_ALIGN_DONE_NO (0x00000000) /* R-XUV */ -#define NV_DPCD20_LANE_ALIGN_STATUS_UPDATED_128B_132B_DPRX_CDS_INTERLANE_ALIGN_DONE_YES (0x00000001) /* R-XUV */ -#define NV_DPCD20_LANE_ALIGN_STATUS_UPDATED_128B_132B_LT_FAILED 4:4 /* R-XUF */ -#define NV_DPCD20_LANE_ALIGN_STATUS_UPDATED_128B_132B_LT_FAILED_NO (0x00000000) /* R-XUV */ -#define NV_DPCD20_LANE_ALIGN_STATUS_UPDATED_128B_132B_LT_FAILED_YES (0x00000001) /* R-XUV */ - -// Field definition for 0x0206/0x0207h (ADJUST_REQUEST_LANEX), only used only with 128b/132b for DP2.0+ -#define NV_DPCD20_LANEX_XPLUS1_ADJUST_REQ_LANEX_TX_FFE_PRESET_VALUE 3:0 /* R-XUF */ -#define NV_DPCD20_LANEX_XPLUS1_ADJUST_REQ_LANEXPLUS1_TX_FFE_PRESET_VALUE 7:4 /* R-XUF */ - -// PANEL REPLAY RELATED DPCD -#define NV_DPCD20_PANEL_REPLAY_CAPABILITY (0x000000B0) -#define NV_DPCD20_PANEL_REPLAY_CAPABILITY_SUPPORTED 0:0 -#define NV_DPCD20_PANEL_REPLAY_CAPABILITY_SUPPORTED_NO (0x00000000) -#define NV_DPCD20_PANEL_REPLAY_CAPABILITY_SUPPORTED_YES (0x00000001) -#define NV_DPCD20_PANEL_REPLAY_CAPABILITY_SEL_UPDATE 1:1 -#define NV_DPCD20_PANEL_REPLAY_CAPABILITY_SEL_UPDATE_NO (0x00000000) -#define NV_DPCD20_PANEL_REPLAY_CAPABILITY_SEL_UPDATE_YES (0x00000001) - -#define NV_DPCD20_PANEL_REPLAY_CONFIGURATION (0x000001B0) -#define NV_DPCD20_PANEL_REPLAY_CONFIGURATION_ENABLE_PR_MODE 0:0 -#define NV_DPCD20_PANEL_REPLAY_CONFIGURATION_ENABLE_PR_MODE_NO (0x00000000) -#define NV_DPCD20_PANEL_REPLAY_CONFIGURATION_ENABLE_PR_MODE_YES (0x00000001) - #define NV_DPCD14_PHY_TEST_PATTERN (0x00000248) /* R-XUR */ #define NV_DPCD14_PHY_TEST_PATTERN_SEL_CP2520PAT3 (0x00000007) /* R-XUV */ @@ -334,24 +292,6 @@ #define NV_DPCD14_FW_SW_REVISION_MAJOR (0x0000040A) /* R-XUR */ #define NV_DPCD14_FW_SW_REVISION_MINOR (0x0000040B) /* R-XUR */ -// Field definition for 0x0200E (LANE_ALIGN_STATUS_UPDATED_ESI), used only when DP2.0+ 128b/132b is enabled. -#define NV_DPCD20_LANE_ALIGN_STATUS_UPDATED_ESI (0x0000200E) /* R-XUR */ -#define NV_DPCD20_LANE_ALIGN_STATUS_UPDATED_ESI_128B_132B_DPRX_EQ_INTERLANE_ALIGN_DONE 2:2 /* R-XUF */ -#define NV_DPCD20_LANE_ALIGN_STATUS_UPDATED_ESI_128B_132B_DPRX_EQ_INTERLANE_ALIGN_DONE_NO (0x00000000) /* R-XUV */ -#define NV_DPCD20_LANE_ALIGN_STATUS_UPDATED_ESI_128B_132B_DPRX_EQ_INTERLANE_ALIGN_DONE_YES (0x00000001) /* R-XUV */ -#define NV_DPCD20_LANE_ALIGN_STATUS_UPDATED_ESI_128B_132B_DPRX_CDS_INTERLANE_ALIGN_DONE 3:3 /* R-XUF */ -#define NV_DPCD20_LANE_ALIGN_STATUS_UPDATED_ESI_128B_132B_DPRX_CDS_INTERLANE_ALIGN_DONE_NO (0x00000000) /* R-XUV */ -#define NV_DPCD20_LANE_ALIGN_STATUS_UPDATED_ESI_128B_132B_DPRX_CDS_INTERLANE_ALIGN_DONE_YES (0x00000001) /* R-XUV */ -#define NV_DPCD20_LANE_ALIGN_STATUS_UPDATED_ESI_128B_132B_LT_FAILED 4:4 /* R-XUF */ -#define NV_DPCD20_LANE_ALIGN_STATUS_UPDATED_ESI_128B_132B_LT_FAILED_NO (0x00000000) /* R-XUV */ -#define NV_DPCD20_LANE_ALIGN_STATUS_UPDATED_ESI_128B_132B_LT_FAILED_YES (0x00000001) /* R-XUV */ - -// Field definition for 0x0200F (SINK_STATUS_ESI), used only when DP2.0+ 128b/132b is enabled. -#define NV_DPCD20_SINK_STATUS_ESI (0x0000200F) /* R-XUR */ -#define NV_DPCD20_SINK_STATUS_ESI_INTRA_HOP_AUX_REPLY 3:3 /* R-XUF */ -#define NV_DPCD20_SINK_STATUS_ESI_INTRA_HOP_AUX_REPLY_DPRX (0x00000000) /* R-XUV */ -#define NV_DPCD20_SINK_STATUS_ESI_INTRA_HOP_AUX_REPLY_LTTPR (0x00000001) /* R-XUV */ - #define NV_DPCD14_EXTENDED_REV (0x00002200) /* R-XUR */ #define NV_DPCD14_EXTENDED_REV_MAJOR 7:4 /* R-XUF */ #define NV_DPCD14_EXTENDED_REV_MAJOR_1 (0x00000001) /* R-XUV */ @@ -532,98 +472,76 @@ #define NV_DPCD14_DPRX_FEATURE_ENUM_LIST_VSC_EXT_FRAMEWORK_V1_SUPPORTED_NO (0x00000000) /* R-XUV */ #define NV_DPCD14_DPRX_FEATURE_ENUM_LIST_VSC_EXT_FRAMEWORK_V1_SUPPORTED_YES (0x00000001) /* R-XUV */ -#define NV_DPCD20_128B_132B_SUPPORTED_LINK_RATES (0x00002215) /* R-XUR */ -#define NV_DPCD20_128B_132B_SUPPORTED_LINK_RATES_UHBR10 0:0 /* R-XUF */ -#define NV_DPCD20_128B_132B_SUPPORTED_LINK_RATES_UHBR10_NO (0x00000000) /* R-XUV */ -#define NV_DPCD20_128B_132B_SUPPORTED_LINK_RATES_UHBR10_YES (0x00000001) /* R-XUV */ -#define NV_DPCD20_128B_132B_SUPPORTED_LINK_RATES_UHBR20 1:1 /* R-XUF */ -#define NV_DPCD20_128B_132B_SUPPORTED_LINK_RATES_UHBR20_NO (0x00000000) /* R-XUV */ -#define NV_DPCD20_128B_132B_SUPPORTED_LINK_RATES_UHBR20_YES (0x00000001) /* R-XUV */ -#define NV_DPCD20_128B_132B_SUPPORTED_LINK_RATES_UHBR13_5 2:2 /* R-XUF */ -#define NV_DPCD20_128B_132B_SUPPORTED_LINK_RATES_UHBR13_5_NO (0x00000000) /* R-XUV */ -#define NV_DPCD20_128B_132B_SUPPORTED_LINK_RATES_UHBR13_5_YES (0x00000001) /* R-XUV */ - -// -// The interval is (128b/132b_TRAINING_AUX_RD_INTERVAL value + 1) * INTERVAL_UNIT. -// The maximum is 256 ms. -// -#define NV_DPCD20_128B_132B_TRAINING_AUX_RD_INTERVAL (0x00002216) /* R-XUR */ -#define NV_DPCD20_128B_132B_TRAINING_AUX_RD_INTERVAL_VAL 6:0 /* R-XUF */ -#define NV_DPCD20_128B_132B_TRAINING_AUX_RD_INTERVAL_UNIT 7:7 /* R-XUF */ -#define NV_DPCD20_128B_132B_TRAINING_AUX_RD_INTERVAL_UNIT_2MS (0x00000000) /* R-XUV */ -#define NV_DPCD20_128B_132B_TRAINING_AUX_RD_INTERVAL_UNIT_1MS (0x00000001) /* R-XUV */ -#define NV_DPCD20_128B_132B_TRAINING_AUX_RD_INTERVAL_MAX_MS 256 - -#define NV_DPCD20_PCON_HDMI_LINK_CONFIG_STATUS (0x00003036) /* R-XUR */ -#define NV_DPCD20_PCON_HDMI_LINK_CONFIG_STATUS_MODE 0:0 /* R-XUF */ -#define NV_DPCD20_PCON_HDMI_LINK_CONFIG_STATUS_MODE_TMDS (0x00000000) /* R-XUV */ -#define NV_DPCD20_PCON_HDMI_LINK_CONFIG_STATUS_MODE_FRL (0x00000001) /* R-XUV */ -#define NV_DPCD20_PCON_HDMI_LINK_CONFIG_STATUS_LT_RESULT 6:1 /* R-XUF */ -#define NV_DPCD20_PCON_HDMI_LINK_CONFIG_STATUS_LT_RES_9G 1:1 /* R-XUF */ -#define NV_DPCD20_PCON_HDMI_LINK_CONFIG_STATUS_LT_RES_9G_NO (0x00000000) /* R-XUV */ -#define NV_DPCD20_PCON_HDMI_LINK_CONFIG_STATUS_LT_RES_9G_YES (0x00000001) /* R-XUV */ -#define NV_DPCD20_PCON_HDMI_LINK_CONFIG_STATUS_LT_RES_18G 2:2 /* R-XUF */ -#define NV_DPCD20_PCON_HDMI_LINK_CONFIG_STATUS_LT_RES_18G_NO (0x00000000) /* R-XUV */ -#define NV_DPCD20_PCON_HDMI_LINK_CONFIG_STATUS_LT_RES_18G_YES (0x00000001) /* R-XUV */ -#define NV_DPCD20_PCON_HDMI_LINK_CONFIG_STATUS_LT_RES_24G 3:3 /* R-XUF */ -#define NV_DPCD20_PCON_HDMI_LINK_CONFIG_STATUS_LT_RES_24G_NO (0x00000000) /* R-XUV */ -#define NV_DPCD20_PCON_HDMI_LINK_CONFIG_STATUS_LT_RES_24G_YES (0x00000001) /* R-XUV */ -#define NV_DPCD20_PCON_HDMI_LINK_CONFIG_STATUS_LT_RES_32G 4:4 /* R-XUF */ -#define NV_DPCD20_PCON_HDMI_LINK_CONFIG_STATUS_LT_RES_32G_NO (0x00000000) /* R-XUV */ -#define NV_DPCD20_PCON_HDMI_LINK_CONFIG_STATUS_LT_RES_32G_YES (0x00000001) /* R-XUV */ -#define NV_DPCD20_PCON_HDMI_LINK_CONFIG_STATUS_LT_RES_40G 5:5 /* R-XUF */ -#define NV_DPCD20_PCON_HDMI_LINK_CONFIG_STATUS_LT_RES_40G_NO (0x00000000) /* R-XUV */ -#define NV_DPCD20_PCON_HDMI_LINK_CONFIG_STATUS_LT_RES_40G_YES (0x00000001) /* R-XUV */ -#define NV_DPCD20_PCON_HDMI_LINK_CONFIG_STATUS_LT_RES_48G 6:6 /* R-XUF */ -#define NV_DPCD20_PCON_HDMI_LINK_CONFIG_STATUS_LT_RES_48G_NO (0x00000000) /* R-XUV */ -#define NV_DPCD20_PCON_HDMI_LINK_CONFIG_STATUS_LT_RES_48G_YES (0x00000001) /* R-XUV */ - -#define NV_DPCD20_PCON_DOWNSTREAM_LINK_ERROR_LANE(i) (0x00003037+(i)) /* RW-1A */ -#define NV_DPCD20_PCON_DOWNSTREAM_LINK_ERROR_LANE__SIZE 4 /* R---S */ -#define NV_DPCD20_PCON_DOWNSTREAM_LINK_ERROR_LANE_COUNT 3:0 /* R-XUF */ -#define NV_DPCD20_PCON_DOWNSTREAM_LINK_ERROR_LANE_COUNT_ZERO (0x00000000) /* R-XUV */ -#define NV_DPCD20_PCON_DOWNSTREAM_LINK_ERROR_LANE_COUNT_THREE (0x00000001) /* R-XUV */ -#define NV_DPCD20_PCON_DOWNSTREAM_LINK_ERROR_LANE_COUNT_TEN (0x00000002) /* R-XUV */ -#define NV_DPCD20_PCON_DOWNSTREAM_LINK_ERROR_LANE_COUNT_HUNDRED (0x00000004) /* R-XUV */ - -#define NV_DPCD20_PCON_HDMI_TX_LINK_STATUS (0x0000303B) /* R-XUR */ -#define NV_DPCD20_PCON_HDMI_TX_LINK_STATUS_LINK_ACTIVE 0:0 /* R-XUF */ -#define NV_DPCD20_PCON_HDMI_TX_LINK_STATUS_LINK_ACTIVE_NO (0x00000000) /* R-XUV */ -#define NV_DPCD20_PCON_HDMI_TX_LINK_STATUS_LINK_ACTIVE_YES (0x00000001) /* R-XUV */ -#define NV_DPCD20_PCON_HDMI_TX_LINK_STATUS_LINK_READY 1:1 /* R-XUF */ -#define NV_DPCD20_PCON_HDMI_TX_LINK_STATUS_LINK_READY_NO (0x00000000) /* R-XUV */ -#define NV_DPCD20_PCON_HDMI_TX_LINK_STATUS_LINK_READY_YES (0x00000001) /* R-XUV */ - -#define NV_DPCD20_PCON_CONTROL_0 (0x00003050) /* RWXUR */ -#define NV_DPCD20_PCON_CONTROL_0_OUTPUT_CONFIG 0:0 /* RWXUF */ -#define NV_DPCD20_PCON_CONTROL_0_OUTPUT_CONFIG_DVI (0x00000000) /* RWXUV */ -#define NV_DPCD20_PCON_CONTROL_0_OUTPUT_CONFIG_HDMI (0x00000001) /* RWXUV */ - -#define NV_DPCD20_PCON_CONTROL_1 (0x00003051) /* RWXUR */ -#define NV_DPCD20_PCON_CONTROL_1_CONVERT_YCBCR420 0:0 /* RWXUF */ -#define NV_DPCD20_PCON_CONTROL_1_CONVERT_YCBCR420_DISABLE (0x00000000) /* RWXUV */ -#define NV_DPCD20_PCON_CONTROL_1_CONVERT_YCBCR420_ENABLE (0x00000001) /* RWXUV */ -#define NV_DPCD20_PCON_CONTROL_1_DISABLE_HDMI_EDID_PROCESS 1:1 /* RWXUF */ -#define NV_DPCD20_PCON_CONTROL_1_DISABLE_HDMI_EDID_PROCESS_NO (0x00000000) /* RWXUV */ -#define NV_DPCD20_PCON_CONTROL_1_DISABLE_HDMI_EDID_PROCESS_YES (0x00000001) /* RWXUV */ -#define NV_DPCD20_PCON_CONTROL_1_DISABLE_HDMI_AUTO_SCRAMBLING 2:2 /* RWXUF */ -#define NV_DPCD20_PCON_CONTROL_1_DISABLE_HDMI_AUTO_SCRAMBLING_NO (0x00000000) /* RWXUV */ -#define NV_DPCD20_PCON_CONTROL_1_DISABLE_HDMI_AUTO_SCRAMBLING_YES (0x00000001) /* RWXUV */ -#define NV_DPCD20_PCON_CONTROL_1_DISABLE_HDMI_FORCE_SCRAMBLING 3:3 /* RWXUF */ -#define NV_DPCD20_PCON_CONTROL_1_DISABLE_HDMI_FORCE_SCRAMBLING_NO (0x00000000) /* RWXUV */ -#define NV_DPCD20_PCON_CONTROL_1_DISABLE_HDMI_FORCE_SCRAMBLING_YES (0x00000001) /* RWXUV */ - -#define NV_DPCD20_PCON_CONTROL_2 (0x00003052) /* RWXUR */ -#define NV_DPCD20_PCON_CONTROL_2_CONVERT_YCBCR422 0:0 /* RWXUF */ -#define NV_DPCD20_PCON_CONTROL_2_CONVERT_YCBCR422_DISABLE (0x00000000) /* RWXUV */ -#define NV_DPCD20_PCON_CONTROL_2_CONVERT_YCBCR422_ENABLE (0x00000001) /* RWXUV */ - -#define NV_DPCD20_PCON_CONTROL_3 (0x00003053) /* RWXUR */ -#define NV_DPCD20_PCON_CONTROL_3_COMPONENT_BIT_DEPTH 1:0 /* RWXUF */ -#define NV_DPCD20_PCON_CONTROL_3_COMPONENT_BIT_DEPTH_SAME_AS_INC (0x00000000) /* RWXUV */ -#define NV_DPCD20_PCON_CONTROL_3_COMPONENT_BIT_DEPTH_8BPC (0x00000001) /* RWXUV */ -#define NV_DPCD20_PCON_CONTROL_3_COMPONENT_BIT_DEPTH_10BPC (0x00000002) /* RWXUV */ -#define NV_DPCD20_PCON_CONTROL_3_COMPONENT_BIT_DEPTH_12BPC (0x00000003) /* RWXUV */ +#define NV_DPCD14_PCON_HDMI_LINK_CONFIG_STATUS (0x00003036) /* R-XUR */ +#define NV_DPCD14_PCON_HDMI_LINK_CONFIG_STATUS_MODE 0:0 /* R-XUF */ +#define NV_DPCD14_PCON_HDMI_LINK_CONFIG_STATUS_MODE_TMDS (0x00000000) /* R-XUV */ +#define NV_DPCD14_PCON_HDMI_LINK_CONFIG_STATUS_MODE_FRL (0x00000001) /* R-XUV */ +#define NV_DPCD14_PCON_HDMI_LINK_CONFIG_STATUS_LT_RESULT 6:1 /* R-XUF */ +#define NV_DPCD14_PCON_HDMI_LINK_CONFIG_STATUS_LT_RES_9G 1:1 /* R-XUF */ +#define NV_DPCD14_PCON_HDMI_LINK_CONFIG_STATUS_LT_RES_9G_NO (0x00000000) /* R-XUV */ +#define NV_DPCD14_PCON_HDMI_LINK_CONFIG_STATUS_LT_RES_9G_YES (0x00000001) /* R-XUV */ +#define NV_DPCD14_PCON_HDMI_LINK_CONFIG_STATUS_LT_RES_18G 2:2 /* R-XUF */ +#define NV_DPCD14_PCON_HDMI_LINK_CONFIG_STATUS_LT_RES_18G_NO (0x00000000) /* R-XUV */ +#define NV_DPCD14_PCON_HDMI_LINK_CONFIG_STATUS_LT_RES_18G_YES (0x00000001) /* R-XUV */ +#define NV_DPCD14_PCON_HDMI_LINK_CONFIG_STATUS_LT_RES_24G 3:3 /* R-XUF */ +#define NV_DPCD14_PCON_HDMI_LINK_CONFIG_STATUS_LT_RES_24G_NO (0x00000000) /* R-XUV */ +#define NV_DPCD14_PCON_HDMI_LINK_CONFIG_STATUS_LT_RES_24G_YES (0x00000001) /* R-XUV */ +#define NV_DPCD14_PCON_HDMI_LINK_CONFIG_STATUS_LT_RES_32G 4:4 /* R-XUF */ +#define NV_DPCD14_PCON_HDMI_LINK_CONFIG_STATUS_LT_RES_32G_NO (0x00000000) /* R-XUV */ +#define NV_DPCD14_PCON_HDMI_LINK_CONFIG_STATUS_LT_RES_32G_YES (0x00000001) /* R-XUV */ +#define NV_DPCD14_PCON_HDMI_LINK_CONFIG_STATUS_LT_RES_40G 5:5 /* R-XUF */ +#define NV_DPCD14_PCON_HDMI_LINK_CONFIG_STATUS_LT_RES_40G_NO (0x00000000) /* R-XUV */ +#define NV_DPCD14_PCON_HDMI_LINK_CONFIG_STATUS_LT_RES_40G_YES (0x00000001) /* R-XUV */ +#define NV_DPCD14_PCON_HDMI_LINK_CONFIG_STATUS_LT_RES_48G 6:6 /* R-XUF */ +#define NV_DPCD14_PCON_HDMI_LINK_CONFIG_STATUS_LT_RES_48G_NO (0x00000000) /* R-XUV */ +#define NV_DPCD14_PCON_HDMI_LINK_CONFIG_STATUS_LT_RES_48G_YES (0x00000001) /* R-XUV */ + +#define NV_DPCD14_PCON_DOWNSTREAM_LINK_ERROR_LANE(i) (0x00003037+(i)) /* RW-1A */ +#define NV_DPCD14_PCON_DOWNSTREAM_LINK_ERROR_LANE__SIZE 4 /* R---S */ +#define NV_DPCD14_PCON_DOWNSTREAM_LINK_ERROR_LANE_COUNT 3:0 /* R-XUF */ +#define NV_DPCD14_PCON_DOWNSTREAM_LINK_ERROR_LANE_COUNT_ZERO (0x00000000) /* R-XUV */ +#define NV_DPCD14_PCON_DOWNSTREAM_LINK_ERROR_LANE_COUNT_THREE (0x00000001) /* R-XUV */ +#define NV_DPCD14_PCON_DOWNSTREAM_LINK_ERROR_LANE_COUNT_TEN (0x00000002) /* R-XUV */ +#define NV_DPCD14_PCON_DOWNSTREAM_LINK_ERROR_LANE_COUNT_HUNDRED (0x00000004) /* R-XUV */ + +#define NV_DPCD14_PCON_HDMI_TX_LINK_STATUS (0x0000303B) /* R-XUR */ +#define NV_DPCD14_PCON_HDMI_TX_LINK_STATUS_LINK_ACTIVE 0:0 /* R-XUF */ +#define NV_DPCD14_PCON_HDMI_TX_LINK_STATUS_LINK_ACTIVE_NO (0x00000000) /* R-XUV */ +#define NV_DPCD14_PCON_HDMI_TX_LINK_STATUS_LINK_ACTIVE_YES (0x00000001) /* R-XUV */ +#define NV_DPCD14_PCON_HDMI_TX_LINK_STATUS_LINK_READY 1:1 /* R-XUF */ +#define NV_DPCD14_PCON_HDMI_TX_LINK_STATUS_LINK_READY_NO (0x00000000) /* R-XUV */ +#define NV_DPCD14_PCON_HDMI_TX_LINK_STATUS_LINK_READY_YES (0x00000001) /* R-XUV */ + +#define NV_DPCD14_PCON_CONTROL_0 (0x00003050) /* RWXUR */ +#define NV_DPCD14_PCON_CONTROL_0_OUTPUT_CONFIG 0:0 /* RWXUF */ +#define NV_DPCD14_PCON_CONTROL_0_OUTPUT_CONFIG_DVI (0x00000000) /* RWXUV */ +#define NV_DPCD14_PCON_CONTROL_0_OUTPUT_CONFIG_HDMI (0x00000001) /* RWXUV */ + +#define NV_DPCD14_PCON_CONTROL_1 (0x00003051) /* RWXUR */ +#define NV_DPCD14_PCON_CONTROL_1_CONVERT_YCBCR420 0:0 /* RWXUF */ +#define NV_DPCD14_PCON_CONTROL_1_CONVERT_YCBCR420_DISABLE (0x00000000) /* RWXUV */ +#define NV_DPCD14_PCON_CONTROL_1_CONVERT_YCBCR420_ENABLE (0x00000001) /* RWXUV */ +#define NV_DPCD14_PCON_CONTROL_1_DISABLE_HDMI_EDID_PROCESS 1:1 /* RWXUF */ +#define NV_DPCD14_PCON_CONTROL_1_DISABLE_HDMI_EDID_PROCESS_NO (0x00000000) /* RWXUV */ +#define NV_DPCD14_PCON_CONTROL_1_DISABLE_HDMI_EDID_PROCESS_YES (0x00000001) /* RWXUV */ +#define NV_DPCD14_PCON_CONTROL_1_DISABLE_HDMI_AUTO_SCRAMBLING 2:2 /* RWXUF */ +#define NV_DPCD14_PCON_CONTROL_1_DISABLE_HDMI_AUTO_SCRAMBLING_NO (0x00000000) /* RWXUV */ +#define NV_DPCD14_PCON_CONTROL_1_DISABLE_HDMI_AUTO_SCRAMBLING_YES (0x00000001) /* RWXUV */ +#define NV_DPCD14_PCON_CONTROL_1_DISABLE_HDMI_FORCE_SCRAMBLING 3:3 /* RWXUF */ +#define NV_DPCD14_PCON_CONTROL_1_DISABLE_HDMI_FORCE_SCRAMBLING_NO (0x00000000) /* RWXUV */ +#define NV_DPCD14_PCON_CONTROL_1_DISABLE_HDMI_FORCE_SCRAMBLING_YES (0x00000001) /* RWXUV */ + +#define NV_DPCD14_PCON_CONTROL_2 (0x00003052) /* RWXUR */ +#define NV_DPCD14_PCON_CONTROL_2_CONVERT_YCBCR422 0:0 /* RWXUF */ +#define NV_DPCD14_PCON_CONTROL_2_CONVERT_YCBCR422_DISABLE (0x00000000) /* RWXUV */ +#define NV_DPCD14_PCON_CONTROL_2_CONVERT_YCBCR422_ENABLE (0x00000001) /* RWXUV */ + +#define NV_DPCD14_PCON_CONTROL_3 (0x00003053) /* RWXUR */ +#define NV_DPCD14_PCON_CONTROL_3_COMPONENT_BIT_DEPTH 1:0 /* RWXUF */ +#define NV_DPCD14_PCON_CONTROL_3_COMPONENT_BIT_DEPTH_SAME_AS_INC (0x00000000) /* RWXUV */ +#define NV_DPCD14_PCON_CONTROL_3_COMPONENT_BIT_DEPTH_8BPC (0x00000001) /* RWXUV */ +#define NV_DPCD14_PCON_CONTROL_3_COMPONENT_BIT_DEPTH_10BPC (0x00000002) /* RWXUV */ +#define NV_DPCD14_PCON_CONTROL_3_COMPONENT_BIT_DEPTH_12BPC (0x00000003) /* RWXUV */ #define NV_DPCD14_OUTPUT_HTOTAL_LOW (0x00003054) /* RWXUR */ #define NV_DPCD14_OUTPUT_HTOTAL_HIGH (0x00003055) /* RWXUR */ @@ -638,42 +556,42 @@ #define NV_DPCD14_OUTPUT_HSP_HSW_HIGH_OUTPUT_HSP_POSITIVE (0x00000000) /* RWXUV */ #define NV_DPCD14_OUTPUT_HSP_HSW_HIGH_OUTPUT_HSP_NEGATIVE (0x00000001) /* RWXUV */ -#define NV_DPCD20_PCON_FRL_LINK_CONFIG_1 (0x0000305A) /* RWXUR */ -#define NV_DPCD20_PCON_FRL_LINK_CONFIG_1_MAX_LINK_BW 2:0 /* RWXUF */ -#define NV_DPCD20_PCON_FRL_LINK_CONFIG_1_MAX_LINK_BW_ZERO (0x00000000) /* RWXUV */ -#define NV_DPCD20_PCON_FRL_LINK_CONFIG_1_MAX_LINK_BW_9G (0x00000001) /* RWXUV */ -#define NV_DPCD20_PCON_FRL_LINK_CONFIG_1_MAX_LINK_BW_18G (0x00000002) /* RWXUV */ -#define NV_DPCD20_PCON_FRL_LINK_CONFIG_1_MAX_LINK_BW_24G (0x00000003) /* RWXUV */ -#define NV_DPCD20_PCON_FRL_LINK_CONFIG_1_MAX_LINK_BW_32G (0x00000004) /* RWXUV */ -#define NV_DPCD20_PCON_FRL_LINK_CONFIG_1_MAX_LINK_BW_40G (0x00000005) /* RWXUV */ -#define NV_DPCD20_PCON_FRL_LINK_CONFIG_1_MAX_LINK_BW_48G (0x00000006) /* RWXUV */ -#define NV_DPCD20_PCON_FRL_LINK_CONFIG_1_SRC_CONTROL_MODE 3:3 /* RWXUF */ -#define NV_DPCD20_PCON_FRL_LINK_CONFIG_1_SRC_CONTROL_MODE_DISABLE (0x00000000) /* RWXUV */ -#define NV_DPCD20_PCON_FRL_LINK_CONFIG_1_SRC_CONTROL_MODE_ENABLE (0x00000001) /* RWXUV */ -#define NV_DPCD20_PCON_FRL_LINK_CONFIG_1_CONCURRENT_LT_MODE 4:4 /* RWXUF */ -#define NV_DPCD20_PCON_FRL_LINK_CONFIG_1_CONCURRENT_LT_MODE_DISABLE (0x00000000) /* RWXUV */ -#define NV_DPCD20_PCON_FRL_LINK_CONFIG_1_CONCURRENT_LT_MODE_ENABLE (0x00000001) /* RWXUV */ -#define NV_DPCD20_PCON_FRL_LINK_CONFIG_1_LINK_FRL_MODE 5:5 /* RWXUF */ -#define NV_DPCD20_PCON_FRL_LINK_CONFIG_1_LINK_FRL_MODE_DISABLE (0x00000000) /* RWXUV */ -#define NV_DPCD20_PCON_FRL_LINK_CONFIG_1_LINK_FRL_MODE_ENABLE (0x00000001) /* RWXUV */ -#define NV_DPCD20_PCON_FRL_LINK_CONFIG_1_IRQ_LINK_FRL_MODE 6:6 /* RWXUF */ -#define NV_DPCD20_PCON_FRL_LINK_CONFIG_1_IRQ_LINK_FRL_MODE_DISABLE (0x00000000) /* RWXUV */ -#define NV_DPCD20_PCON_FRL_LINK_CONFIG_1_IRQ_LINK_FRL_MODE_ENABLE (0x00000001) /* RWXUV */ -#define NV_DPCD20_PCON_FRL_LINK_CONFIG_1_HDMI_LINK 7:7 /* RWXUF */ -#define NV_DPCD20_PCON_FRL_LINK_CONFIG_1_HDMI_LINK_DISABLE (0x00000000) /* RWXUV */ -#define NV_DPCD20_PCON_FRL_LINK_CONFIG_1_HDMI_LINK_ENABLE (0x00000001) /* RWXUV */ - -#define NV_DPCD20_PCON_FRL_LINK_CONFIG_2 (0x0000305B) /* RWXUR */ -#define NV_DPCD20_PCON_FRL_LINK_CONFIG_2_LINK_BW_MASK 5:0 /* RWXUF */ -#define NV_DPCD20_PCON_FRL_LINK_CONFIG_2_LINK_BW_MASK_9G (0x00000001) /* RWXUV */ -#define NV_DPCD20_PCON_FRL_LINK_CONFIG_2_LINK_BW_MASK_18G (0x00000002) /* RWXUV */ -#define NV_DPCD20_PCON_FRL_LINK_CONFIG_2_LINK_BW_MASK_24G (0x00000004) /* RWXUV */ -#define NV_DPCD20_PCON_FRL_LINK_CONFIG_2_LINK_BW_MASK_32G (0x00000008) /* RWXUV */ -#define NV_DPCD20_PCON_FRL_LINK_CONFIG_2_LINK_BW_MASK_40G (0x00000010) /* RWXUV */ -#define NV_DPCD20_PCON_FRL_LINK_CONFIG_2_LINK_BW_MASK_48G (0x00000020) /* RWXUV */ -#define NV_DPCD20_PCON_FRL_LINK_CONFIG_2_FRL_LT_CONTROL 6:6 /* RWXUF */ -#define NV_DPCD20_PCON_FRL_LINK_CONFIG_2_FRL_LT_CONTROL_NORMAL (0x00000000) /* RWXUV */ -#define NV_DPCD20_PCON_FRL_LINK_CONFIG_2_FRL_LT_CONTROL_EXTENDED (0x00000001) /* RWXUV */ +#define NV_DPCD14_PCON_FRL_LINK_CONFIG_1 (0x0000305A) /* RWXUR */ +#define NV_DPCD14_PCON_FRL_LINK_CONFIG_1_MAX_LINK_BW 2:0 /* RWXUF */ +#define NV_DPCD14_PCON_FRL_LINK_CONFIG_1_MAX_LINK_BW_ZERO (0x00000000) /* RWXUV */ +#define NV_DPCD14_PCON_FRL_LINK_CONFIG_1_MAX_LINK_BW_9G (0x00000001) /* RWXUV */ +#define NV_DPCD14_PCON_FRL_LINK_CONFIG_1_MAX_LINK_BW_18G (0x00000002) /* RWXUV */ +#define NV_DPCD14_PCON_FRL_LINK_CONFIG_1_MAX_LINK_BW_24G (0x00000003) /* RWXUV */ +#define NV_DPCD14_PCON_FRL_LINK_CONFIG_1_MAX_LINK_BW_32G (0x00000004) /* RWXUV */ +#define NV_DPCD14_PCON_FRL_LINK_CONFIG_1_MAX_LINK_BW_40G (0x00000005) /* RWXUV */ +#define NV_DPCD14_PCON_FRL_LINK_CONFIG_1_MAX_LINK_BW_48G (0x00000006) /* RWXUV */ +#define NV_DPCD14_PCON_FRL_LINK_CONFIG_1_SRC_CONTROL_MODE 3:3 /* RWXUF */ +#define NV_DPCD14_PCON_FRL_LINK_CONFIG_1_SRC_CONTROL_MODE_DISABLE (0x00000000) /* RWXUV */ +#define NV_DPCD14_PCON_FRL_LINK_CONFIG_1_SRC_CONTROL_MODE_ENABLE (0x00000001) /* RWXUV */ +#define NV_DPCD14_PCON_FRL_LINK_CONFIG_1_CONCURRENT_LT_MODE 4:4 /* RWXUF */ +#define NV_DPCD14_PCON_FRL_LINK_CONFIG_1_CONCURRENT_LT_MODE_DISABLE (0x00000000) /* RWXUV */ +#define NV_DPCD14_PCON_FRL_LINK_CONFIG_1_CONCURRENT_LT_MODE_ENABLE (0x00000001) /* RWXUV */ +#define NV_DPCD14_PCON_FRL_LINK_CONFIG_1_LINK_FRL_MODE 5:5 /* RWXUF */ +#define NV_DPCD14_PCON_FRL_LINK_CONFIG_1_LINK_FRL_MODE_DISABLE (0x00000000) /* RWXUV */ +#define NV_DPCD14_PCON_FRL_LINK_CONFIG_1_LINK_FRL_MODE_ENABLE (0x00000001) /* RWXUV */ +#define NV_DPCD14_PCON_FRL_LINK_CONFIG_1_IRQ_LINK_FRL_MODE 6:6 /* RWXUF */ +#define NV_DPCD14_PCON_FRL_LINK_CONFIG_1_IRQ_LINK_FRL_MODE_DISABLE (0x00000000) /* RWXUV */ +#define NV_DPCD14_PCON_FRL_LINK_CONFIG_1_IRQ_LINK_FRL_MODE_ENABLE (0x00000001) /* RWXUV */ +#define NV_DPCD14_PCON_FRL_LINK_CONFIG_1_HDMI_LINK 7:7 /* RWXUF */ +#define NV_DPCD14_PCON_FRL_LINK_CONFIG_1_HDMI_LINK_DISABLE (0x00000000) /* RWXUV */ +#define NV_DPCD14_PCON_FRL_LINK_CONFIG_1_HDMI_LINK_ENABLE (0x00000001) /* RWXUV */ + +#define NV_DPCD14_PCON_FRL_LINK_CONFIG_2 (0x0000305B) /* RWXUR */ +#define NV_DPCD14_PCON_FRL_LINK_CONFIG_2_LINK_BW_MASK 5:0 /* RWXUF */ +#define NV_DPCD14_PCON_FRL_LINK_CONFIG_2_LINK_BW_MASK_9G (0x00000001) /* RWXUV */ +#define NV_DPCD14_PCON_FRL_LINK_CONFIG_2_LINK_BW_MASK_18G (0x00000002) /* RWXUV */ +#define NV_DPCD14_PCON_FRL_LINK_CONFIG_2_LINK_BW_MASK_24G (0x00000004) /* RWXUV */ +#define NV_DPCD14_PCON_FRL_LINK_CONFIG_2_LINK_BW_MASK_32G (0x00000008) /* RWXUV */ +#define NV_DPCD14_PCON_FRL_LINK_CONFIG_2_LINK_BW_MASK_40G (0x00000010) /* RWXUV */ +#define NV_DPCD14_PCON_FRL_LINK_CONFIG_2_LINK_BW_MASK_48G (0x00000020) /* RWXUV */ +#define NV_DPCD14_PCON_FRL_LINK_CONFIG_2_FRL_LT_CONTROL 6:6 /* RWXUF */ +#define NV_DPCD14_PCON_FRL_LINK_CONFIG_2_FRL_LT_CONTROL_NORMAL (0x00000000) /* RWXUV */ +#define NV_DPCD14_PCON_FRL_LINK_CONFIG_2_FRL_LT_CONTROL_EXTENDED (0x00000001) /* RWXUV */ // LT Tunable Repeater Related offsets @@ -790,5 +708,15 @@ #define NV_DPCD14_ADJUST_REQUEST_LANE0_1_PHY_REPEATER (0x00000023) /* R-XUR */ #define NV_DPCD14_ADJUST_REQUEST_LANE2_3_PHY_REPEATER (0x00000024) /* R-XUR */ +// BRANCH SPECIFIC DSC CAPS +#define NV_DPCD14_BRANCH_DSC_OVERALL_THROUGHPUT_MODE_0 (0x000000A0) +#define NV_DPCD14_BRANCH_DSC_OVERALL_THROUGHPUT_MODE_0_VALUE 7:0 + +#define NV_DPCD14_BRANCH_DSC_OVERALL_THROUGHPUT_MODE_1 (0x000000A1) +#define NV_DPCD14_BRANCH_DSC_OVERALL_THROUGHPUT_MODE_1_VALUE 7:0 + +#define NV_DPCD14_BRANCH_DSC_MAXIMUM_LINE_BUFFER_WIDTH (0x000000A2) +#define NV_DPCD14_BRANCH_DSC_MAXIMUM_LINE_BUFFER_WIDTH_VALUE 7:0 + #endif // #ifndef _DISPLAYPORT14_H_ diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/common/inc/displayport/dpcd20.h nvidia-open-gpu-kernel-modules-535.161.08/src/common/inc/displayport/dpcd20.h --- nvidia-open-gpu-kernel-modules-525.147.05/src/common/inc/displayport/dpcd20.h 2023-10-25 20:22:14.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/common/inc/displayport/dpcd20.h 2024-03-05 22:11:44.000000000 +0000 @@ -21,17 +21,16 @@ * DEALINGS IN THE SOFTWARE. */ -#define NV_DPCD20_DSC_SUPPORT (0x00000060) /* R-XUR */ +#include "nvcfg_sdk.h" + +// DSC Pass Through related DPCD. New bits in DPCD 0x0060h defined in DPCD2.0. #define NV_DPCD20_DSC_SUPPORT_PASS_THROUGH_SUPPORT 1:1 /* R-XUF */ #define NV_DPCD20_DSC_SUPPORT_PASS_THROUGH_SUPPORT_NO (0x00000000) /* R-XUV */ #define NV_DPCD20_DSC_SUPPORT_PASS_THROUGH_SUPPORT_YES (0x00000001) /* R-XUV */ - -#define NV_DPCD20_DSC_PASS_THROUGH (0x00000160) /* R-XUR */ -#define NV_DPCD20_DSC_PASS_THROUGH_ENABLE 1:1 /* R-XUF */ -#define NV_DPCD20_DSC_PASS_THROUGH_ENABLE_NO (0x00000000) /* R-XUV */ -#define NV_DPCD20_DSC_PASS_THROUGH_ENABLE_YES (0x00000001) /* R-XUV */ - -#define NV_DPCD20_GUID_2 (0x00000040) /* R-XUR */ +// DSC Pass Through related DPCD. New bits in DPCD 0x0160h defined in DPCD2.0. +#define NV_DPCD20_DSC_ENABLE_PASS_THROUGH 1:1 /* R-XUF */ +#define NV_DPCD20_DSC_ENABLE_PASS_THROUGH_NO (0x00000000) /* R-XUV */ +#define NV_DPCD20_DSC_ENABLE_PASS_THROUGH_YES (0x00000001) /* R-XUV */ // PANEL REPLAY RELATED DPCD #define NV_DPCD20_PANEL_REPLAY_CAPABILITY (0x000000B0) @@ -59,12 +58,3 @@ #define NV_DPCD20_PANEL_REPLAY_AND_FRAME_LOCK_STATUS_SINK_FRAME_LOCKED_GOVERNING (0x00000002) #define NV_DPCD20_PANEL_REPLAY_AND_FRAME_LOCK_STATUS_SINK_FRAME_LOCKED_RELOCKING (0x00000003) -// BRANCH SPECIFIC DSC CAPS -#define NV_DPCD20_BRANCH_DSC_OVERALL_THROUGHPUT_MODE_0 (0x000000A0) -#define NV_DPCD20_BRANCH_DSC_OVERALL_THROUGHPUT_MODE_0_VALUE 7:0 - -#define NV_DPCD20_BRANCH_DSC_OVERALL_THROUGHPUT_MODE_1 (0x000000A1) -#define NV_DPCD20_BRANCH_DSC_OVERALL_THROUGHPUT_MODE_1_VALUE 7:0 - -#define NV_DPCD20_BRANCH_DSC_MAXIMUM_LINE_BUFFER_WIDTH (0x000000A2) -#define NV_DPCD20_BRANCH_DSC_MAXIMUM_LINE_BUFFER_WIDTH_VALUE 7:0 diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/common/inc/gps.h nvidia-open-gpu-kernel-modules-535.161.08/src/common/inc/gps.h --- nvidia-open-gpu-kernel-modules-525.147.05/src/common/inc/gps.h 2023-10-25 20:19:43.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/common/inc/gps.h 2024-03-05 22:11:43.000000000 +0000 @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 2011-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2011-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -30,6 +30,7 @@ #define GPS_FUNC_SUPPORT 0x00000000 // Bit list of supported functions #define GPS_FUNC_GETOBJBYTYPE 0x00000010 // Fetch any specific Object by Type #define GPS_FUNC_GETALLOBJS 0x00000011 // Fetch all Objects +#define GPS_FUNC_REQUESTDXSTATE 0x00000012 // Request D-Notifier state #define GPS_FUNC_GETCALLBACKS 0x00000013 // Get system requested callbacks #define GPS_FUNC_PCONTROL 0x0000001C // GPU power control function #define GPS_FUNC_PSHARESTATUS 0x00000020 // Get system requested Power Steering settings @@ -43,6 +44,8 @@ #define GPS_FUNC_GETPPM 0x00000028 // Get system power modes #define GPS_FUNC_SETPPM 0x00000029 // Set system power modes #define GPS_FUNC_PSHAREPARAMS 0x0000002A // Get sensor information and capabilities +#define GPS_FUNC_SETEDPPLIMITINFO 0x0000002B // Send the GPU EDPPeak limit info to platform +#define GPS_FUNC_GETEDPPLIMIT 0x0000002C // Get EDPPeak limit from platform #define GPS_EVENT_STATUS_CHANGE 0x000000C0 // when received call GPS_FUNC_PCONTROL, // depends on whether system is GPS enabled. diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/common/inc/jt.h nvidia-open-gpu-kernel-modules-535.161.08/src/common/inc/jt.h --- nvidia-open-gpu-kernel-modules-525.147.05/src/common/inc/jt.h 2023-10-25 20:19:43.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/common/inc/jt.h 2024-03-05 22:11:43.000000000 +0000 @@ -90,5 +90,26 @@ #define NV_JT_FUNC_CAPS_REVISION_ID_1_03 0x00000103 #define NV_JT_FUNC_CAPS_REVISION_ID_2_00 0x00000200 +// +// JT_FUNC_POWERCONTROL argument definitions (Rev 1.0) +// + +// +// GPU Power Control +// +#define NV_JT_FUNC_POWERCONTROL_GPU_POWER_CONTROL 2:0 +#define NV_JT_FUNC_POWERCONTROL_GPU_POWER_CONTROL_GSS 0x00000000 +// +// JT_FUNC_POWERCONTROL return buffer definitions +// +#define NV_JT_FUNC_POWERCONTROL_GPU_GC_STATE 2:0 +#define NV_JT_FUNC_POWERCONTROL_GPU_GC_STATE_TRANSITION 0x00000000 +#define NV_JT_FUNC_POWERCONTROL_GPU_GC_STATE_ON 0x00000001 +#define NV_JT_FUNC_POWERCONTROL_GPU_GC_STATE_OFF 0x00000002 +#define NV_JT_FUNC_POWERCONTROL_GPU_GC_STATE_GC6 0x00000003 +#define NV_JT_FUNC_POWERCONTROL_GPU_POWER_STATE 3:3 +#define NV_JT_FUNC_POWERCONTROL_GPU_POWER_STATE_OFF 0x00000000 +#define NV_JT_FUNC_POWERCONTROL_GPU_POWER_STATE_PWOK 0x00000001 + #endif // JT_H diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/common/inc/nvBldVer.h nvidia-open-gpu-kernel-modules-535.161.08/src/common/inc/nvBldVer.h --- nvidia-open-gpu-kernel-modules-525.147.05/src/common/inc/nvBldVer.h 2023-10-25 20:19:44.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/common/inc/nvBldVer.h 2024-03-05 22:11:43.000000000 +0000 @@ -36,26 +36,26 @@ // and then checked back in. You cannot make changes to these sections without // corresponding changes to the buildmeister script #ifndef NV_BUILD_BRANCH - #define NV_BUILD_BRANCH r529_18 + #define NV_BUILD_BRANCH r538_27 #endif #ifndef NV_PUBLIC_BRANCH - #define NV_PUBLIC_BRANCH r529_18 + #define NV_PUBLIC_BRANCH r538_27 #endif #if defined(NV_LINUX) || defined(NV_BSD) || defined(NV_SUNOS) -#define NV_BUILD_BRANCH_VERSION "rel/gpu_drv/r525/r529_18-534" -#define NV_BUILD_CHANGELIST_NUM (33451322) +#define NV_BUILD_BRANCH_VERSION "rel/gpu_drv/r535/r538_27-451" +#define NV_BUILD_CHANGELIST_NUM (33992350) #define NV_BUILD_TYPE "Official" -#define NV_BUILD_NAME "rel/gpu_drv/r525/r529_18-534" -#define NV_LAST_OFFICIAL_CHANGELIST_NUM (33451322) +#define NV_BUILD_NAME "rel/gpu_drv/r535/r538_27-451" +#define NV_LAST_OFFICIAL_CHANGELIST_NUM (33992350) #else /* Windows builds */ -#define NV_BUILD_BRANCH_VERSION "r529_18-2" -#define NV_BUILD_CHANGELIST_NUM (33403873) +#define NV_BUILD_BRANCH_VERSION "r538_27-6" +#define NV_BUILD_CHANGELIST_NUM (33992350) #define NV_BUILD_TYPE "Official" -#define NV_BUILD_NAME "529.19" -#define NV_LAST_OFFICIAL_CHANGELIST_NUM (33403873) -#define NV_BUILD_BRANCH_BASE_VERSION R525 +#define NV_BUILD_NAME "538.46" +#define NV_LAST_OFFICIAL_CHANGELIST_NUM (33992350) +#define NV_BUILD_BRANCH_BASE_VERSION R535 #endif // End buildmeister python edited section diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/common/inc/nvPNPVendorIds.h nvidia-open-gpu-kernel-modules-535.161.08/src/common/inc/nvPNPVendorIds.h --- nvidia-open-gpu-kernel-modules-525.147.05/src/common/inc/nvPNPVendorIds.h 2023-10-25 20:22:14.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/common/inc/nvPNPVendorIds.h 2024-03-05 22:11:44.000000000 +0000 @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 2009-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2009 - 2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -158,6 +158,7 @@ { "CSE", _VENDOR_NAME_ENTRY("Compu Shack") }, { "CSI", _VENDOR_NAME_ENTRY("Cabletron") }, { "CSS", _VENDOR_NAME_ENTRY("CSS Laboratories") }, + { "CSW", _VENDOR_NAME_ENTRY("China Star Optoelectronics Technology Co., Ltd") }, { "CTN", _VENDOR_NAME_ENTRY("Computone") }, { "CTX", _VENDOR_NAME_ENTRY("Chuntex/CTX") }, { "CUB", _VENDOR_NAME_ENTRY("Cubix") }, @@ -443,11 +444,13 @@ { "SAN", _VENDOR_NAME_ENTRY("Sanyo Electric Co.,Ltd.") }, { "SCC", _VENDOR_NAME_ENTRY("SORD") }, { "SCD", _VENDOR_NAME_ENTRY("Sanyo") }, + { "SDC", _VENDOR_NAME_ENTRY("Samsung Display Corp.") }, { "SDI", _VENDOR_NAME_ENTRY("Samtron/Sigma Designs") }, { "SDT", _VENDOR_NAME_ENTRY("Siemens AG") }, { "SEA", _VENDOR_NAME_ENTRY("Segate") }, { "SEC", _VENDOR_NAME_ENTRY("Seiko/Epson") }, { "SEN", _VENDOR_NAME_ENTRY("Sencore") }, + { "SFL", _VENDOR_NAME_ENTRY("Shiftall Inc") }, { "SGT", _VENDOR_NAME_ENTRY("Stargate Technology/AT&T") }, { "SGX", _VENDOR_NAME_ENTRY("SGI") }, { "SHP", _VENDOR_NAME_ENTRY("Sharp") }, @@ -504,6 +507,7 @@ { "TEI", _VENDOR_NAME_ENTRY("TECO") }, { "TGI", _VENDOR_NAME_ENTRY("TriGem") }, { "TGS", _VENDOR_NAME_ENTRY("Torus") }, + { "TMA", _VENDOR_NAME_ENTRY("Tianma Microelectronics") }, { "TOS", _VENDOR_NAME_ENTRY("Toshiba") }, { "TRI", _VENDOR_NAME_ENTRY("Tricord") }, { "TRM", _VENDOR_NAME_ENTRY("Tekram") }, diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/common/inc/nvSemaphoreCommon.h nvidia-open-gpu-kernel-modules-535.161.08/src/common/inc/nvSemaphoreCommon.h --- nvidia-open-gpu-kernel-modules-525.147.05/src/common/inc/nvSemaphoreCommon.h 2023-10-25 20:22:14.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/common/inc/nvSemaphoreCommon.h 2024-03-05 22:11:44.000000000 +0000 @@ -63,23 +63,23 @@ * the CPU or submitted to be written by the GPU, which is stashed in the * timestamp field of the semaphore by the CPU in both these cases. */ -static inline void NvTimeSemFermiSetMaxSubmitted( - NvReportSemaphore32 *report, +static inline void NvTimeSemFermiSetMaxSubmittedVal( + volatile NvU64 *maxSubmittedPtr, const NvU64 value) { NvU64 oldValue = - (NvU64)__NVatomicCompareExchange64((volatile NvS64 *)&report->timer, + (NvU64)__NVatomicCompareExchange64((volatile NvS64 *)maxSubmittedPtr, 0, 0); // Atomically set report->timer to max(value, report->time). while (oldValue < value) { const NvU64 prevValue = - (NvU64)__NVatomicCompareExchange64((volatile NvS64 *)&report->timer, + (NvU64)__NVatomicCompareExchange64((volatile NvS64 *)maxSubmittedPtr, (NvS64)value, (NvS64)oldValue); if (prevValue == oldValue) { // The specified value was set. Done. - nvAssert(report->timer >= value); + nvAssert(*maxSubmittedPtr >= value); break; } @@ -87,6 +87,13 @@ } } +static inline void NvTimeSemFermiSetMaxSubmitted( + NvReportSemaphore32 *report, + const NvU64 value) +{ + NvTimeSemFermiSetMaxSubmittedVal(&report->timer, value); +} + static inline NvU64 NvTimeSemFermiGetPayload( NvReportSemaphore32 *report) { @@ -150,7 +157,7 @@ const NvU64 payload) { // First save the actual value to the reserved/timer bits - NvTimeSemFermiSetMaxSubmitted(report, payload); + NvTimeSemFermiSetMaxSubmittedVal(&report->timer, payload); // Then write the low bits to the GPU-accessible semaphore value. report->payload = (NvU32)(payload & 0xFFFFFFFFULL); diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/common/inc/nvUnixVersion.h nvidia-open-gpu-kernel-modules-535.161.08/src/common/inc/nvUnixVersion.h --- nvidia-open-gpu-kernel-modules-525.147.05/src/common/inc/nvUnixVersion.h 2023-10-25 20:19:44.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/common/inc/nvUnixVersion.h 2024-03-05 22:11:44.000000000 +0000 @@ -4,7 +4,7 @@ #if defined(NV_LINUX) || defined(NV_BSD) || defined(NV_SUNOS) || defined(NV_VMWARE) || defined(NV_QNX) || defined(NV_INTEGRITY) || \ (defined(RMCFG_FEATURE_PLATFORM_GSP) && RMCFG_FEATURE_PLATFORM_GSP == 1) -#define NV_VERSION_STRING "525.147.05" +#define NV_VERSION_STRING "535.161.08" #else diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/common/inc/nvVer.h nvidia-open-gpu-kernel-modules-535.161.08/src/common/inc/nvVer.h --- nvidia-open-gpu-kernel-modules-525.147.05/src/common/inc/nvVer.h 2023-10-25 20:19:44.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/common/inc/nvVer.h 2024-03-05 22:11:44.000000000 +0000 @@ -3,7 +3,7 @@ #define NV_COMPANY_NAME_STRING_SHORT "NVIDIA" #define NV_COMPANY_NAME_STRING_FULL "NVIDIA Corporation" #define NV_COMPANY_NAME_STRING NV_COMPANY_NAME_STRING_FULL -#define NV_COPYRIGHT_YEAR "2023" +#define NV_COPYRIGHT_YEAR "2024" #define NV_COPYRIGHT "(C) " NV_COPYRIGHT_YEAR " NVIDIA Corporation. All rights reserved." // Please do not use the non-ascii copyright symbol for (C). #if defined(NV_LINUX) || defined(NV_BSD) || defined(NV_SUNOS) || defined(NV_VMWARE) || defined(NV_QNX) || defined(NV_INTEGRITY) || \ diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/common/inc/nveGPUConfig.h nvidia-open-gpu-kernel-modules-535.161.08/src/common/inc/nveGPUConfig.h --- nvidia-open-gpu-kernel-modules-525.147.05/src/common/inc/nveGPUConfig.h 2023-10-25 20:19:44.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/common/inc/nveGPUConfig.h 2024-03-05 22:11:44.000000000 +0000 @@ -39,48 +39,63 @@ #endif //NV_UNIX #endif //!__cplusplus -// Surprise removal capable TB3 and TB2 BUS Device ID -#define BUS_DEVICE_ID_TB3_ALPINE_RIDGE_01 0x1578 -#define BUS_DEVICE_ID_TB3_02 0x1576 -#define BUS_DEVICE_ID_TB3_03 0x15C0 -#define BUS_DEVICE_ID_TB3_04 0x15D3 -#define BUS_DEVICE_ID_TB3_05 0x15DA -#define BUS_DEVICE_ID_TB3_06 0x15EA -#define BUS_DEVICE_ID_TB3_07 0x15E7 -#define BUS_DEVICE_ID_TB3_08 0x15EF -#define BUS_DEVICE_ID_TB3_09 0x1133 -#define BUS_DEVICE_ID_TB3_10 0x1136 - -// IceLake-U TB3 device ids. Below TB3 would be integrated to CPU. -#define BUS_DEVICE_ID_ICELAKE_TB3_01 0x8A1D -#define BUS_DEVICE_ID_ICELAKE_TB3_02 0x8A1F -#define BUS_DEVICE_ID_ICELAKE_TB3_03 0x8A21 -#define BUS_DEVICE_ID_ICELAKE_TB3_04 0x8A23 -#define BUS_DEVICE_ID_ICELAKE_TB3_05 0x8A0D -#define BUS_DEVICE_ID_ICELAKE_TB3_06 0x8A17 - -// TigerLake Thunderbolt device ids. -#define BUS_DEVICE_ID_TIGERLAKE_TB3_01 0x9A1B -#define BUS_DEVICE_ID_TIGERLAKE_TB3_02 0x9A1D -#define BUS_DEVICE_ID_TIGERLAKE_TB3_03 0x9A1F -#define BUS_DEVICE_ID_TIGERLAKE_TB3_04 0x9A21 -#define BUS_DEVICE_ID_TIGERLAKE_TB3_05 0x9A23 -#define BUS_DEVICE_ID_TIGERLAKE_TB3_06 0x9A25 -#define BUS_DEVICE_ID_TIGERLAKE_TB3_07 0x9A27 -#define BUS_DEVICE_ID_TIGERLAKE_TB3_08 0x9A29 -#define BUS_DEVICE_ID_TIGERLAKE_TB3_09 0x9A2B -#define BUS_DEVICE_ID_TIGERLAKE_TB3_10 0x9A2D - -//#define BUS_DEVICE_ID_TB2_FALCON_RIDGE_DSL5520_01 0X156C // obsolete -#define BUS_DEVICE_ID_TB2_FALCON_RIDGE_DSL5520_02 0X156D -#define BUS_DEVICE_ID_TB2_03 0x157E -#define BUS_DEVICE_ID_TB2_04 0x156B -#define BUS_DEVICE_ID_TB2_05 0x1567 -#define BUS_DEVICE_ID_TB2_06 0x1569 -//#define BUS_DEVICE_ID_TB2_07 0x1548 // obsolete -#define BUS_DEVICE_ID_TB2_08 0x151B -#define BUS_DEVICE_ID_TB2_09 0x1549 -#define BUS_DEVICE_ID_TB2_10 0x1513 +#define PARENT_EGPU_BUS_DEVICE_43 0x57A4 +#define PARENT_EGPU_BUS_DEVICE_42 0x5786 +#define PARENT_EGPU_BUS_DEVICE_41 0x1578 +#define PARENT_EGPU_BUS_DEVICE_40 0x1576 +#define PARENT_EGPU_BUS_DEVICE_39 0x15C0 +#define PARENT_EGPU_BUS_DEVICE_38 0x15D3 +#define PARENT_EGPU_BUS_DEVICE_37 0x15DA +#define PARENT_EGPU_BUS_DEVICE_36 0x15EA +#define PARENT_EGPU_BUS_DEVICE_35 0x15E7 +#define PARENT_EGPU_BUS_DEVICE_34 0x15EF +#define PARENT_EGPU_BUS_DEVICE_33 0x1133 +#define PARENT_EGPU_BUS_DEVICE_32 0x1136 + +#define PARENT_EGPU_BUS_DEVICE_31 0x8A1D +#define PARENT_EGPU_BUS_DEVICE_30 0x8A1F +#define PARENT_EGPU_BUS_DEVICE_29 0x8A21 +#define PARENT_EGPU_BUS_DEVICE_28 0x8A23 +#define PARENT_EGPU_BUS_DEVICE_27 0x8A0D +#define PARENT_EGPU_BUS_DEVICE_26 0x8A17 + + +#define PARENT_EGPU_BUS_DEVICE_25 0x9A1B +#define PARENT_EGPU_BUS_DEVICE_24 0x9A1D +#define PARENT_EGPU_BUS_DEVICE_23 0x9A1F +#define PARENT_EGPU_BUS_DEVICE_22 0x9A21 +#define PARENT_EGPU_BUS_DEVICE_21 0x9A23 +#define PARENT_EGPU_BUS_DEVICE_20 0x9A25 +#define PARENT_EGPU_BUS_DEVICE_19 0x9A27 +#define PARENT_EGPU_BUS_DEVICE_18 0x9A29 +#define PARENT_EGPU_BUS_DEVICE_17 0x9A2B +#define PARENT_EGPU_BUS_DEVICE_16 0x9A2D + +#define PARENT_EGPU_BUS_DEVICE_15 0x7EB2 +#define PARENT_EGPU_BUS_DEVICE_14 0x7EC2 +#define PARENT_EGPU_BUS_DEVICE_13 0x7EC3 +#define PARENT_EGPU_BUS_DEVICE_12 0x7EB4 +#define PARENT_EGPU_BUS_DEVICE_11 0x7EC4 +#define PARENT_EGPU_BUS_DEVICE_10 0x7EB5 +#define PARENT_EGPU_BUS_DEVICE_09 0x7EC5 +#define PARENT_EGPU_BUS_DEVICE_08 0x7EC6 +#define PARENT_EGPU_BUS_DEVICE_07 0x7EC7 + +#define PARENT_EGPU_BUS_DEVICE_06 0xA73E +#define PARENT_EGPU_BUS_DEVICE_05 0xA76D +#define PARENT_EGPU_BUS_DEVICE_04 0x466E +#define PARENT_EGPU_BUS_DEVICE_03 0x463F +#define PARENT_EGPU_BUS_DEVICE_02 0x462F +#define PARENT_EGPU_BUS_DEVICE_01 0x461F + +#define PARENT_EGPU_BUS_DEVICE_02_08 0X156D +#define PARENT_EGPU_BUS_DEVICE_02_07 0x157E +#define PARENT_EGPU_BUS_DEVICE_02_06 0x156B +#define PARENT_EGPU_BUS_DEVICE_02_05 0x1567 +#define PARENT_EGPU_BUS_DEVICE_02_04 0x1569 +#define PARENT_EGPU_BUS_DEVICE_02_03 0x151B +#define PARENT_EGPU_BUS_DEVICE_02_02 0x1549 +#define PARENT_EGPU_BUS_DEVICE_02_01 0x1513 //***************************************************************************** // Function: isTB3DeviceID @@ -103,33 +118,51 @@ EGPU_INLINE NvBool isTB3DeviceID(NvU16 deviceID) { NvU32 index; - NvU16 tb3DeviceIDList[]={ BUS_DEVICE_ID_TB3_ALPINE_RIDGE_01, - BUS_DEVICE_ID_TB3_02, - BUS_DEVICE_ID_TB3_03, - BUS_DEVICE_ID_TB3_04, - BUS_DEVICE_ID_TB3_05, - BUS_DEVICE_ID_TB3_06, - BUS_DEVICE_ID_TB3_07, - BUS_DEVICE_ID_TB3_08, - BUS_DEVICE_ID_TB3_09, - BUS_DEVICE_ID_TB3_10, - BUS_DEVICE_ID_ICELAKE_TB3_01, - BUS_DEVICE_ID_ICELAKE_TB3_02, - BUS_DEVICE_ID_ICELAKE_TB3_03, - BUS_DEVICE_ID_ICELAKE_TB3_04, - BUS_DEVICE_ID_ICELAKE_TB3_05, - BUS_DEVICE_ID_ICELAKE_TB3_06, - BUS_DEVICE_ID_TIGERLAKE_TB3_01, - BUS_DEVICE_ID_TIGERLAKE_TB3_02, - BUS_DEVICE_ID_TIGERLAKE_TB3_03, - BUS_DEVICE_ID_TIGERLAKE_TB3_04, - BUS_DEVICE_ID_TIGERLAKE_TB3_05, - BUS_DEVICE_ID_TIGERLAKE_TB3_06, - BUS_DEVICE_ID_TIGERLAKE_TB3_07, - BUS_DEVICE_ID_TIGERLAKE_TB3_08, - BUS_DEVICE_ID_TIGERLAKE_TB3_09, - BUS_DEVICE_ID_TIGERLAKE_TB3_10 - }; + NvU16 tb3DeviceIDList[]={ PARENT_EGPU_BUS_DEVICE_01, + PARENT_EGPU_BUS_DEVICE_02, + PARENT_EGPU_BUS_DEVICE_03, + PARENT_EGPU_BUS_DEVICE_04, + PARENT_EGPU_BUS_DEVICE_05, + PARENT_EGPU_BUS_DEVICE_06, + PARENT_EGPU_BUS_DEVICE_07, + PARENT_EGPU_BUS_DEVICE_08, + PARENT_EGPU_BUS_DEVICE_09, + PARENT_EGPU_BUS_DEVICE_10, + PARENT_EGPU_BUS_DEVICE_11, + PARENT_EGPU_BUS_DEVICE_12, + PARENT_EGPU_BUS_DEVICE_13, + PARENT_EGPU_BUS_DEVICE_14, + PARENT_EGPU_BUS_DEVICE_15, + PARENT_EGPU_BUS_DEVICE_16, + PARENT_EGPU_BUS_DEVICE_17, + PARENT_EGPU_BUS_DEVICE_18, + PARENT_EGPU_BUS_DEVICE_19, + PARENT_EGPU_BUS_DEVICE_20, + PARENT_EGPU_BUS_DEVICE_21, + PARENT_EGPU_BUS_DEVICE_22, + PARENT_EGPU_BUS_DEVICE_23, + PARENT_EGPU_BUS_DEVICE_24, + PARENT_EGPU_BUS_DEVICE_25, + PARENT_EGPU_BUS_DEVICE_26, + PARENT_EGPU_BUS_DEVICE_27, + PARENT_EGPU_BUS_DEVICE_28, + PARENT_EGPU_BUS_DEVICE_29, + PARENT_EGPU_BUS_DEVICE_30, + PARENT_EGPU_BUS_DEVICE_31, + PARENT_EGPU_BUS_DEVICE_32, + PARENT_EGPU_BUS_DEVICE_33, + PARENT_EGPU_BUS_DEVICE_34, + PARENT_EGPU_BUS_DEVICE_35, + PARENT_EGPU_BUS_DEVICE_36, + PARENT_EGPU_BUS_DEVICE_37, + PARENT_EGPU_BUS_DEVICE_38, + PARENT_EGPU_BUS_DEVICE_39, + PARENT_EGPU_BUS_DEVICE_40, + PARENT_EGPU_BUS_DEVICE_41, + PARENT_EGPU_BUS_DEVICE_42, + PARENT_EGPU_BUS_DEVICE_43 + }; + for (index = 0; index < (sizeof(tb3DeviceIDList)/sizeof(NvU16)); index++) { if (deviceID == tb3DeviceIDList[index]) @@ -161,11 +194,14 @@ EGPU_INLINE NvBool isTB2DeviceID(NvU16 deviceID) { NvU32 index; - NvU16 tb2DeviceIDList[]={ BUS_DEVICE_ID_TB2_FALCON_RIDGE_DSL5520_02, - BUS_DEVICE_ID_TB2_03, BUS_DEVICE_ID_TB2_04, - BUS_DEVICE_ID_TB2_05, BUS_DEVICE_ID_TB2_06, - BUS_DEVICE_ID_TB2_08, BUS_DEVICE_ID_TB2_09, - BUS_DEVICE_ID_TB2_10 + NvU16 tb2DeviceIDList[]={ PARENT_EGPU_BUS_DEVICE_02_01, + PARENT_EGPU_BUS_DEVICE_02_02, + PARENT_EGPU_BUS_DEVICE_02_03, + PARENT_EGPU_BUS_DEVICE_02_04, + PARENT_EGPU_BUS_DEVICE_02_05, + PARENT_EGPU_BUS_DEVICE_02_06, + PARENT_EGPU_BUS_DEVICE_02_07, + PARENT_EGPU_BUS_DEVICE_02_08 }; for (index = 0; index < (sizeof(tb2DeviceIDList)/sizeof(NvU16)); index++) { diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/common/inc/swref/published/ada/ad102/dev_bus.h nvidia-open-gpu-kernel-modules-535.161.08/src/common/inc/swref/published/ada/ad102/dev_bus.h --- nvidia-open-gpu-kernel-modules-525.147.05/src/common/inc/swref/published/ada/ad102/dev_bus.h 2023-10-25 20:19:45.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/common/inc/swref/published/ada/ad102/dev_bus.h 2024-03-05 22:11:45.000000000 +0000 @@ -30,3 +30,4 @@ #define NV_PBUS_SW_SCRATCH_FIELD_INIT 0x00000000 /* RWI-V */ #endif // ad102_dev_nv_bus_h + diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/common/inc/swref/published/ada/ad102/dev_bus_addendum.h nvidia-open-gpu-kernel-modules-535.161.08/src/common/inc/swref/published/ada/ad102/dev_bus_addendum.h --- nvidia-open-gpu-kernel-modules-525.147.05/src/common/inc/swref/published/ada/ad102/dev_bus_addendum.h 2023-10-25 20:19:45.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/common/inc/swref/published/ada/ad102/dev_bus_addendum.h 2024-03-05 22:11:45.000000000 +0000 @@ -37,3 +37,4 @@ #define NV_PBUS_SW_GLOBAL_EROT_GRANT_ALLOW_NO 0 #endif // ad102_dev_nv_bus_addendum_h + diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/common/inc/swref/published/ampere/ga100/hwproject.h nvidia-open-gpu-kernel-modules-535.161.08/src/common/inc/swref/published/ampere/ga100/hwproject.h --- nvidia-open-gpu-kernel-modules-525.147.05/src/common/inc/swref/published/ampere/ga100/hwproject.h 1970-01-01 00:00:00.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/common/inc/swref/published/ampere/ga100/hwproject.h 2024-03-05 22:11:48.000000000 +0000 @@ -0,0 +1,28 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2023 NVIDIA CORPORATION & AFFILIATES + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ +#ifndef __ga100_hwproject_h__ +#define __ga100_hwproject_h__ + +#define NV_SCAL_LITTER_NUM_FBPAS 24 + +#endif // __ga100_hwproject_h__ diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/common/inc/swref/published/disp/v03_00/dev_disp.h nvidia-open-gpu-kernel-modules-535.161.08/src/common/inc/swref/published/disp/v03_00/dev_disp.h --- nvidia-open-gpu-kernel-modules-525.147.05/src/common/inc/swref/published/disp/v03_00/dev_disp.h 2023-10-25 20:19:50.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/common/inc/swref/published/disp/v03_00/dev_disp.h 2024-03-05 22:11:51.000000000 +0000 @@ -70,4 +70,8 @@ #define NV_PDISP_RG_DPCA_FRM_CNT 31:16 /* R--UF */ #define NV_PDISP_FE_FLIPLOCK 0x0061206C /* RW-4R */ #define NV_PDISP_FE_FLIPLOCK_LSR_MIN_TIME 23:0 /* RWIVF */ +#define NV_PDISP_FE_RM_INTR_STAT_CTRL_DISP 0x00611C30 /* R--4R */ +#define NV_PDISP_FE_RM_INTR_STAT_CTRL_DISP_AWAKEN 8:8 /* R-IVF */ +#define NV_PDISP_FE_RM_INTR_STAT_CTRL_DISP_AWAKEN_NOT_PENDING 0x00000000 /* R-I-V */ +#define NV_PDISP_FE_RM_INTR_STAT_CTRL_DISP_AWAKEN_PENDING 0x00000001 /* R---V */ #endif // __v03_00_dev_disp_h__ diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/common/inc/swref/published/disp/v04_00/dev_disp.h nvidia-open-gpu-kernel-modules-535.161.08/src/common/inc/swref/published/disp/v04_00/dev_disp.h --- nvidia-open-gpu-kernel-modules-525.147.05/src/common/inc/swref/published/disp/v04_00/dev_disp.h 2023-10-25 20:19:50.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/common/inc/swref/published/disp/v04_00/dev_disp.h 2024-03-05 22:11:52.000000000 +0000 @@ -37,9 +37,18 @@ #define NV_PDISP_FE_RM_INTR_DISPATCH_HEAD_TIMING(i) (0+(i)):(0+(i)) /* R--VF */ #define NV_PDISP_FE_RM_INTR_DISPATCH_HEAD_TIMING_NOT_PENDING 0x00000000 /* R---V */ #define NV_PDISP_FE_RM_INTR_DISPATCH_HEAD_TIMING_PENDING 0x00000001 /* R---V */ -#define NV_PDISP_VGA_WORKSPACE_BASE 0x00625F04 /* RW-4R */ -#define NV_PDISP_VGA_WORKSPACE_BASE_STATUS 3:3 /* RWIVF */ -#define NV_PDISP_VGA_WORKSPACE_BASE_STATUS_VALID 0x00000001 /* RW--V */ -#define NV_PDISP_VGA_WORKSPACE_BASE_ADDR 31:8 /* RWIVF */ - +#define NV_PDISP_VGA_WORKSPACE_BASE 0x00625F04 /* RW-4R */ +#define NV_PDISP_VGA_WORKSPACE_BASE_STATUS 3:3 /* RWIVF */ +#define NV_PDISP_VGA_WORKSPACE_BASE_STATUS_VALID 0x00000001 /* RW--V */ +#define NV_PDISP_VGA_WORKSPACE_BASE_ADDR 31:8 /* RWIVF */ +#define NV_PDISP_FE_CORE_HEAD_STATE(i) (0x00612078+(i)*2048) /* R--4A */ +#define NV_PDISP_FE_CORE_HEAD_STATE_OPERATING_MODE 9:8 /* R--VF */ +#define NV_PDISP_FE_CORE_HEAD_STATE_OPERATING_MODE_SLEEP 0x00000000 /* R---V */ +#define NV_PDISP_FE_CORE_HEAD_STATE_OPERATING_MODE_SNOOZE 0x00000001 /* R---V */ +#define NV_PDISP_FE_CORE_HEAD_STATE_OPERATING_MODE_AWAKE 0x00000002 /* R---V */ +#define NV_PDISP_FE_RM_INTR_EN_HEAD_TIMING(i) (0x00611D80+(i)*4) /* RW-4A */ +#define NV_PDISP_FE_RM_INTR_EN_HEAD_TIMING_LAST_DATA 1:1 /* RWIVF */ +#define NV_PDISP_FE_RM_INTR_EN_HEAD_TIMING_LAST_DATA_INIT 0x00000000 /* RWI-V */ +#define NV_PDISP_FE_RM_INTR_EN_HEAD_TIMING_LAST_DATA_DISABLE 0x00000000 /* RW--V */ +#define NV_PDISP_FE_RM_INTR_EN_HEAD_TIMING_LAST_DATA_ENABLE 0x00000001 /* RW--V */ #endif // __v04_00_dev_disp_h__ diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/common/inc/swref/published/hopper/gh100/dev_fb.h nvidia-open-gpu-kernel-modules-535.161.08/src/common/inc/swref/published/hopper/gh100/dev_fb.h --- nvidia-open-gpu-kernel-modules-525.147.05/src/common/inc/swref/published/hopper/gh100/dev_fb.h 2023-10-25 20:19:50.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/common/inc/swref/published/hopper/gh100/dev_fb.h 2024-03-05 22:11:53.000000000 +0000 @@ -21,7 +21,7 @@ * DEALINGS IN THE SOFTWARE. */ -#ifndef __gh100_dev_fb_h +#ifndef __gh100_dev_fb_h_ #define __gh100_dev_fb_h_ #define NV_PFB_NISO_FLUSH_SYSMEM_ADDR_SHIFT 8 /* */ #define NV_PFB_FBHUB_PCIE_FLUSH_SYSMEM_ADDR_LO 0x00100A34 /* RW-4R */ @@ -30,24 +30,4 @@ #define NV_PFB_FBHUB_PCIE_FLUSH_SYSMEM_ADDR_HI_ADR 31:0 /* RWIVF */ #define NV_PFB_FBHUB_PCIE_FLUSH_SYSMEM_ADDR_HI_ADR_MASK 0x000FFFFF /* ----V */ -#define NV_PFB_PRI_MMU_L2TLB_ECC_UNCORRECTED_ERR_COUNT 0x00100E78 /* RW-4R */ -#define NV_PFB_PRI_MMU_L2TLB_ECC_UNCORRECTED_ERR_COUNT 0x00100E78 /* RW-4R */ -#define NV_PFB_PRI_MMU_L2TLB_ECC_UNCORRECTED_ERR_COUNT_TOTAL 15:0 /* RWEVF */ -#define NV_PFB_PRI_MMU_L2TLB_ECC_UNCORRECTED_ERR_COUNT_TOTAL_INIT 0 /* RWE-V */ -#define NV_PFB_PRI_MMU_L2TLB_ECC_UNCORRECTED_ERR_COUNT_UNIQUE 31:16 /* RWEVF */ -#define NV_PFB_PRI_MMU_L2TLB_ECC_UNCORRECTED_ERR_COUNT_UNIQUE_INIT 0 /* RWE-V */ - -#define NV_PFB_PRI_MMU_HUBTLB_ECC_UNCORRECTED_ERR_COUNT 0x00100E8C /* RW-4R */ -#define NV_PFB_PRI_MMU_HUBTLB_ECC_UNCORRECTED_ERR_COUNT 0x00100E8C /* RW-4R */ -#define NV_PFB_PRI_MMU_HUBTLB_ECC_UNCORRECTED_ERR_COUNT_TOTAL 15:0 /* RWEVF */ -#define NV_PFB_PRI_MMU_HUBTLB_ECC_UNCORRECTED_ERR_COUNT_TOTAL_INIT 0 /* RWE-V */ -#define NV_PFB_PRI_MMU_HUBTLB_ECC_UNCORRECTED_ERR_COUNT_UNIQUE 31:16 /* RWEVF */ -#define NV_PFB_PRI_MMU_HUBTLB_ECC_UNCORRECTED_ERR_COUNT_UNIQUE_INIT 0 /* RWE-V */ - -#define NV_PFB_PRI_MMU_FILLUNIT_ECC_UNCORRECTED_ERR_COUNT 0x00100EA0 /* RW-4R */ -#define NV_PFB_PRI_MMU_FILLUNIT_ECC_UNCORRECTED_ERR_COUNT 0x00100EA0 /* RW-4R */ -#define NV_PFB_PRI_MMU_FILLUNIT_ECC_UNCORRECTED_ERR_COUNT_TOTAL 15:0 /* RWEVF */ -#define NV_PFB_PRI_MMU_FILLUNIT_ECC_UNCORRECTED_ERR_COUNT_TOTAL_INIT 0 /* RWE-V */ -#define NV_PFB_PRI_MMU_FILLUNIT_ECC_UNCORRECTED_ERR_COUNT_UNIQUE 31:16 /* RWEVF */ -#define NV_PFB_PRI_MMU_FILLUNIT_ECC_UNCORRECTED_ERR_COUNT_UNIQUE_INIT 0 /* RWE-V */ -#endif // __gh100_dev_fb_h__ +#endif // __gh100_dev_fb_h_ diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/common/inc/swref/published/hopper/gh100/dev_fsp_addendum.h nvidia-open-gpu-kernel-modules-535.161.08/src/common/inc/swref/published/hopper/gh100/dev_fsp_addendum.h --- nvidia-open-gpu-kernel-modules-525.147.05/src/common/inc/swref/published/hopper/gh100/dev_fsp_addendum.h 2023-10-25 20:19:51.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/common/inc/swref/published/hopper/gh100/dev_fsp_addendum.h 2024-03-05 22:11:53.000000000 +0000 @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 2022-2023 NVIDIA CORPORATION & AFFILIATES + * SPDX-FileCopyrightText: Copyright (c) 2023 NVIDIA CORPORATION & AFFILIATES * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -29,55 +29,4 @@ #define NV_GFW_FSP_UCODE_VERSION_MAJOR 11:8 #define NV_GFW_FSP_UCODE_VERSION_MINOR 7:0 -// -// RM uses channel 0 for FSP EMEM on GH100. -// -#define FSP_EMEM_CHANNEL_RM 0x0 - -// -// PMU/SOE use channel 4 for FSP EMEM on GH100. -// -#define FSP_EMEM_CHANNEL_PMU_SOE 0x4 -#define FSP_EMEM_CHANNEL_MAX 0x8 - -// EMEM channel 0 (RM) is allocated 1K bytes. -#define FSP_EMEM_CHANNEL_RM_SIZE 1024 - -// EMEM channel 4 (PMU/SOE) is allocated 1K bytes. -#define FSP_EMEM_CHANNEL_PMU_SOE_SIZE 1024 -#define FSP_EMEM_CHANNEL_PMU_SOE_OFFSET 4096 - -// -// MCTP (Management Component Transport Protocol) overlayed on NVDM (NVIDIA Data -// Model) is the mechanism used between FSP management partition and CPU-RM. -// - -#define MCTP_HEADER_RSVD 7:4 -#define MCTP_HEADER_VERSION 3:0 - -#define MCTP_HEADER_DEID 15:8 - -#define MCTP_HEADER_SEID 23:16 - -#define MCTP_HEADER_SOM 31:31 -#define MCTP_HEADER_EOM 30:30 -#define MCTP_HEADER_SEQ 29:28 -#define MCTP_HEADER_TO 27:27 -#define MCTP_HEADER_TAG 26:24 - -#define MCTP_MSG_HEADER_IC 7:7 -#define MCTP_MSG_HEADER_TYPE 6:0 -#define MCTP_MSG_HEADER_VENDOR_ID 23:8 -#define MCTP_MSG_HEADER_NVDM_TYPE 31:24 - -#define MCTP_MSG_HEADER_TYPE_VENDOR_PCI 0x7e -#define MCTP_MSG_HEADER_VENDOR_ID_NV 0x10de - -#define NVDM_TYPE_HULK 0x11 -#define NVDM_TYPE_FIRMWARE_UPDATE 0x12 -#define NVDM_TYPE_COT 0x14 -#define NVDM_TYPE_FSP_RESPONSE 0x15 -#define NVDM_TYPE_INFOROM 0x17 -#define NVDM_TYPE_SMBPBI 0x18 - #endif // __gh100_dev_fsp_addendum_h__ diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/common/inc/swref/published/hopper/gh100/dev_fuse.h nvidia-open-gpu-kernel-modules-535.161.08/src/common/inc/swref/published/hopper/gh100/dev_fuse.h --- nvidia-open-gpu-kernel-modules-525.147.05/src/common/inc/swref/published/hopper/gh100/dev_fuse.h 1970-01-01 00:00:00.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/common/inc/swref/published/hopper/gh100/dev_fuse.h 2024-03-05 22:11:54.000000000 +0000 @@ -0,0 +1,52 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2003-2023 NVIDIA CORPORATION & AFFILIATES + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef __gh100_dev_fuse_h__ +#define __gh100_dev_fuse_h__ + +#define NV_FUSE_OPT_SECURE_GSP_DEBUG_DIS 0x0082074C /* RW-4R */ +#define NV_FUSE_OPT_SECURE_GSP_DEBUG_DIS_DATA 0:0 /* RWIVF */ +#define NV_FUSE_OPT_SECURE_GSP_DEBUG_DIS_DATA_NO 0x00000000 /* RW--V */ +#define NV_FUSE_OPT_SECURE_GSP_DEBUG_DIS_DATA_YES 0x00000001 /* RW--V */ +#define NV_FUSE_SPARE_BIT_0 0x00824E04 /* RW-4R */ +#define NV_FUSE_SPARE_BIT_0_DATA 0:0 /* RWIVF */ +#define NV_FUSE_SPARE_BIT_0_DATA_INIT 0x00000000 /* RWI-V */ +#define NV_FUSE_SPARE_BIT_0_DATA_DISABLE 0x00000000 /* RW--V */ +#define NV_FUSE_SPARE_BIT_0_DATA_ENABLE 0x00000001 /* RW--V */ +#define NV_FUSE_SPARE_BIT_1 0x00824E08 /* RW-4R */ +#define NV_FUSE_SPARE_BIT_1_DATA 0:0 /* RWIVF */ +#define NV_FUSE_SPARE_BIT_1_DATA_INIT 0x00000000 /* RWI-V */ +#define NV_FUSE_SPARE_BIT_1_DATA_DISABLE 0x00000000 /* RW--V */ +#define NV_FUSE_SPARE_BIT_1_DATA_ENABLE 0x00000001 /* RW--V */ +#define NV_FUSE_SPARE_BIT_2 0x00824E0C /* RW-4R */ +#define NV_FUSE_SPARE_BIT_2_DATA 0:0 /* RWIVF */ +#define NV_FUSE_SPARE_BIT_2_DATA_INIT 0x00000000 /* RWI-V */ +#define NV_FUSE_SPARE_BIT_2_DATA_DISABLE 0x00000000 /* RW--V */ +#define NV_FUSE_SPARE_BIT_2_DATA_ENABLE 0x00000001 /* RW--V */ +#define NV_FUSE_SPARE_BIT_3 0x00824E10 /* RW-4R */ +#define NV_FUSE_SPARE_BIT_3_DATA 0:0 /* RWIVF */ +#define NV_FUSE_SPARE_BIT_3_DATA_INIT 0x00000000 /* RWI-V */ +#define NV_FUSE_SPARE_BIT_3_DATA_DISABLE 0x00000000 /* RW--V */ +#define NV_FUSE_SPARE_BIT_3_DATA_ENABLE 0x00000001 /* RW--V */ + +#endif // __gh100_dev_fuse_h__ diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/common/inc/swref/published/hopper/gh100/dev_gc6_island.h nvidia-open-gpu-kernel-modules-535.161.08/src/common/inc/swref/published/hopper/gh100/dev_gc6_island.h --- nvidia-open-gpu-kernel-modules-525.147.05/src/common/inc/swref/published/hopper/gh100/dev_gc6_island.h 2023-10-25 20:19:51.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/common/inc/swref/published/hopper/gh100/dev_gc6_island.h 2024-03-05 22:11:54.000000000 +0000 @@ -41,5 +41,8 @@ #define NV_PGC6_SCI_SYS_TIMER_OFFSET_1 0x00118df8 /* RW-4R */ #define NV_PGC6_SCI_SYS_TIMER_OFFSET_1_NSEC 28:0 /* RWEUF */ #define NV_PGC6_SCI_SYS_TIMER_OFFSET_1_NSEC_ZERO 0x00000000 /* RWE-V */ +#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_20 0x001182cc /* RW-4R */ +#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_20_DATA 31:0 /* RWIVF */ +#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_20_DATA_INIT 0x00000000 /* RWI-V */ #endif // __gh100_dev_gc6_island_h__ diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/common/inc/swref/published/hopper/gh100/dev_gc6_island_addendum.h nvidia-open-gpu-kernel-modules-535.161.08/src/common/inc/swref/published/hopper/gh100/dev_gc6_island_addendum.h --- nvidia-open-gpu-kernel-modules-525.147.05/src/common/inc/swref/published/hopper/gh100/dev_gc6_island_addendum.h 2023-10-25 20:19:51.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/common/inc/swref/published/hopper/gh100/dev_gc6_island_addendum.h 2024-03-05 22:11:55.000000000 +0000 @@ -26,4 +26,12 @@ #define NV_PGC6_AON_FRTS_INPUT_WPR_SIZE_SECURE_SCRATCH_GROUP_03_0_WPR_SIZE_1MB_IN_4K 0x100 +#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_20_CC NV_PGC6_AON_SECURE_SCRATCH_GROUP_20 +#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_20_CC_MODE_ENABLED 0:0 +#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_20_CC_MODE_ENABLED_TRUE 0x1 +#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_20_CC_MODE_ENABLED_FALSE 0x0 +#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_20_CC_DEV_ENABLED 1:1 +#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_20_CC_DEV_ENABLED_TRUE 0x1 +#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_20_CC_DEV_ENABLED_FALSE 0x0 + #endif // __gh100_dev_gc6_island_addendum_h__ diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/common/inc/swref/published/hopper/gh100/dev_gsp.h nvidia-open-gpu-kernel-modules-535.161.08/src/common/inc/swref/published/hopper/gh100/dev_gsp.h --- nvidia-open-gpu-kernel-modules-525.147.05/src/common/inc/swref/published/hopper/gh100/dev_gsp.h 2023-10-25 20:19:51.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/common/inc/swref/published/hopper/gh100/dev_gsp.h 2024-03-05 22:11:55.000000000 +0000 @@ -22,6 +22,7 @@ */ #ifndef __gh100_dev_gsp_h__ #define __gh100_dev_gsp_h__ +#define NV_PGSP 0x113fff:0x110000 /* RW--D */ #define NV_PGSP_FALCON_ENGINE 0x1103c0 /* RW-4R */ #define NV_PGSP_FALCON_ENGINE_RESET 0:0 /* RWEVF */ #define NV_PGSP_FALCON_ENGINE_RESET_DEASSERT 0 /* */ @@ -30,4 +31,22 @@ #define NV_PGSP_FALCON_ENGINE_RESET_STATUS_ASSERTED 0x00000000 /* R-E-V */ #define NV_PGSP_FALCON_ENGINE_RESET_STATUS_DEASSERTED 0x00000002 /* R---V */ #define NV_PGSP_MAILBOX(i) (0x110804+(i)*4) /* RW-4A */ +#define NV_PGSP_EMEMC(i) (0x110ac0+(i)*8) /* RW-4A */ +#define NV_PGSP_EMEMC__SIZE_1 8 /* */ +#define NV_PGSP_EMEMC_OFFS 7:2 /* RWIVF */ +#define NV_PGSP_EMEMC_OFFS_INIT 0x00000000 /* RWI-V */ +#define NV_PGSP_EMEMC_BLK 15:8 /* RWIVF */ +#define NV_PGSP_EMEMC_BLK_INIT 0x00000000 /* RWI-V */ +#define NV_PGSP_EMEMC_AINCW 24:24 /* RWIVF */ +#define NV_PGSP_EMEMC_AINCW_INIT 0x00000000 /* RWI-V */ +#define NV_PGSP_EMEMC_AINCW_TRUE 0x00000001 /* RW--V */ +#define NV_PGSP_EMEMC_AINCW_FALSE 0x00000000 /* RW--V */ +#define NV_PGSP_EMEMC_AINCR 25:25 /* RWIVF */ +#define NV_PGSP_EMEMC_AINCR_INIT 0x00000000 /* RWI-V */ +#define NV_PGSP_EMEMC_AINCR_TRUE 0x00000001 /* RW--V */ +#define NV_PGSP_EMEMC_AINCR_FALSE 0x00000000 /* RW--V */ +#define NV_PGSP_EMEMD(i) (0x110ac4+(i)*8) /* RW-4A */ +#define NV_PGSP_EMEMD__SIZE_1 8 /* */ +#define NV_PGSP_EMEMD_DATA 31:0 /* RWXVF */ + #endif // __gh100_dev_gsp_h__ diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/common/inc/swref/published/hopper/gh100/dev_ltc.h nvidia-open-gpu-kernel-modules-535.161.08/src/common/inc/swref/published/hopper/gh100/dev_ltc.h --- nvidia-open-gpu-kernel-modules-525.147.05/src/common/inc/swref/published/hopper/gh100/dev_ltc.h 2023-10-25 20:19:51.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/common/inc/swref/published/hopper/gh100/dev_ltc.h 1970-01-01 00:00:00.000000000 +0000 @@ -1,33 +0,0 @@ -/* - * SPDX-FileCopyrightText: Copyright (c) 2023 NVIDIA CORPORATION & AFFILIATES - * SPDX-License-Identifier: MIT - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER - * DEALINGS IN THE SOFTWARE. - */ - -#ifndef __gh100_dev_ltc_h_ -#define __gh100_dev_ltc_h_ - -#define NV_PLTCG_LTC0_LTS0_L2_CACHE_ECC_UNCORRECTED_ERR_COUNT 0x001404f8 /* RW-4R */ -#define NV_PLTCG_LTC0_LTS0_L2_CACHE_ECC_UNCORRECTED_ERR_COUNT_TOTAL 15:0 /* RWIVF */ -#define NV_PLTCG_LTC0_LTS0_L2_CACHE_ECC_UNCORRECTED_ERR_COUNT_TOTAL_INIT 0x0000 /* RWI-V */ -#define NV_PLTCG_LTC0_LTS0_L2_CACHE_ECC_UNCORRECTED_ERR_COUNT_UNIQUE 31:16 /* RWIVF */ -#define NV_PLTCG_LTC0_LTS0_L2_CACHE_ECC_UNCORRECTED_ERR_COUNT_UNIQUE_INIT 0x0000 /* RWI-V */ - -#endif // __gh100_dev_ltc_h_ diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/common/inc/swref/published/hopper/gh100/dev_vm.h nvidia-open-gpu-kernel-modules-535.161.08/src/common/inc/swref/published/hopper/gh100/dev_vm.h --- nvidia-open-gpu-kernel-modules-525.147.05/src/common/inc/swref/published/hopper/gh100/dev_vm.h 2023-10-25 20:19:52.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/common/inc/swref/published/hopper/gh100/dev_vm.h 2024-03-05 22:11:56.000000000 +0000 @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2022-23 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -46,5 +46,19 @@ #define NV_VIRTUAL_FUNCTION_PRIV_CPU_INTR_LEAF_EN_CLEAR__SIZE_1 16 /* */ #define NV_VIRTUAL_FUNCTION_PRIV_TIMER(i) (0x2300+(i)*4) /* RW-4A */ #define NV_VIRTUAL_FUNCTION_PRIV_TIMER__SIZE_1 2 /* */ +#define NV_VIRTUAL_FUNCTION_PRIV_ACCESS_COUNTER_NOTIFY_BUFFER_LO 0x00003108 /* RW-4R */ +#define NV_VIRTUAL_FUNCTION_PRIV_ACCESS_COUNTER_NOTIFY_BUFFER_LO_BASE 31:12 /* RWXVF */ +#define NV_VIRTUAL_FUNCTION_PRIV_ACCESS_COUNTER_NOTIFY_BUFFER_HI 0x0000310C /* RW-4R */ +#define NV_VIRTUAL_FUNCTION_PRIV_DOORBELL 0x2200 /* -W-4R */ +#define NV_VIRTUAL_FUNCTION_PRIV_CPU_INTR_LEAF(i) (0x1000+(i)*4) /* RW-4A */ +#define NV_VIRTUAL_FUNCTION_PRIV_CPU_INTR_LEAF_VALUE 31:0 /* RWXVF */ +#define NV_VIRTUAL_FUNCTION_PRIV_CPU_INTR_LEAF_VALUE_INIT 0x00000000 /* R---V */ +#define NV_VIRTUAL_FUNCTION_PRIV_CPU_INTR_LEAF_EN_SET(i) (0x1200+(i)*4) /* RW-4A */ +#define NV_VIRTUAL_FUNCTION_PRIV_CPU_INTR_LEAF_EN_SET_VALUE 31:0 /* RWIVF */ +#define NV_VIRTUAL_FUNCTION_PRIV_CPU_INTR_LEAF_EN_SET_VALUE_INIT 0x00000000 /* R-I-V */ +#define NV_VIRTUAL_FUNCTION_PRIV_CPU_INTR_LEAF_EN_CLEAR(i) (0x1400+(i)*4) /* RW-4A */ +#define NV_VIRTUAL_FUNCTION_PRIV_CPU_INTR_LEAF_EN_CLEAR_VALUE 31:0 /* RWIVF */ +#define NV_VIRTUAL_FUNCTION_PRIV_CPU_INTR_LEAF_EN_CLEAR_VALUE_INIT 0x00000000 /* R-I-V */ +#define NV_VIRTUAL_FUNCTION_PRIV_MMU_PAGE_FAULT_CTRL 0x00003070 /* RW-4R */ #endif // __gh100_dev_vm_h__ diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/common/inc/swref/published/hopper/gh100/dev_vm_addendum.h nvidia-open-gpu-kernel-modules-535.161.08/src/common/inc/swref/published/hopper/gh100/dev_vm_addendum.h --- nvidia-open-gpu-kernel-modules-525.147.05/src/common/inc/swref/published/hopper/gh100/dev_vm_addendum.h 2023-10-25 20:19:52.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/common/inc/swref/published/hopper/gh100/dev_vm_addendum.h 2024-03-05 22:11:57.000000000 +0000 @@ -50,4 +50,8 @@ // #define NV_CTRL_CPU_DOORBELL_VECTORID_VALUE_CONSTANT 0x00000081 +#define NV_VIRTUAL_FUNCTION_PRIV_NON_REPLAYABLE_FAULT_SHADOW_BUFFER_PUT NV_VIRTUAL_FUNCTION_PRIV_ACCESS_COUNTER_NOTIFY_BUFFER_LO +#define NV_VIRTUAL_FUNCTION_PRIV_NON_REPLAYABLE_FAULT_SHADOW_BUFFER_PUT_PTR NV_VIRTUAL_FUNCTION_PRIV_ACCESS_COUNTER_NOTIFY_BUFFER_LO_BASE +#define NV_VIRTUAL_FUNCTION_PRIV_REPLAYABLE_FAULT_SHADOW_BUFFER_PUT NV_VIRTUAL_FUNCTION_PRIV_ACCESS_COUNTER_NOTIFY_BUFFER_HI + #endif // __gh100_dev_vm_addendum_h__ diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/common/inc/swref/published/hopper/gh100/dev_xtl_ep_pcfg_gpu.h nvidia-open-gpu-kernel-modules-535.161.08/src/common/inc/swref/published/hopper/gh100/dev_xtl_ep_pcfg_gpu.h --- nvidia-open-gpu-kernel-modules-525.147.05/src/common/inc/swref/published/hopper/gh100/dev_xtl_ep_pcfg_gpu.h 2023-10-25 20:19:52.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/common/inc/swref/published/hopper/gh100/dev_xtl_ep_pcfg_gpu.h 2024-03-05 22:11:57.000000000 +0000 @@ -27,6 +27,12 @@ #define NV_EP_PCFG_GPU_CTRL_CMD_AND_STATUS 0x00000004 /* RW-4R */ #define NV_EP_PCFG_GPU_CTRL_CMD_AND_STATUS_CMD_IO_SPACE 0:0 /* RWIVF */ #define NV_EP_PCFG_GPU_CTRL_CMD_AND_STATUS_CMD_IO_SPACE_ENABLE 0x00000001 /* RW--V */ +#define NV_EP_PCFG_GPU_CTRL_CMD_AND_STATUS_CMD_MEM_SPACE 1:1 /* RWIVF */ +#define NV_EP_PCFG_GPU_CTRL_CMD_AND_STATUS_CMD_MEM_SPACE_DEFAULT 0x00000000 /* RWI-V */ +#define NV_EP_PCFG_GPU_CTRL_CMD_AND_STATUS_CMD_MEM_SPACE_ENABLE 0x00000001 /* RW--V */ +#define NV_EP_PCFG_GPU_CTRL_CMD_AND_STATUS_CMD_BUS_MASTER 2:2 /* RWIVF */ +#define NV_EP_PCFG_GPU_CTRL_CMD_AND_STATUS_CMD_BUS_MASTER_DISABLE 0x00000000 /* RWI-V */ +#define NV_EP_PCFG_GPU_CTRL_CMD_AND_STATUS_CMD_BUS_MASTER_ENABLE 0x00000001 /* RW--V */ #define NV_EP_PCFG_GPU_REVISION_ID_AND_CLASSCODE 0x00000008 /* R--4R */ #define NV_EP_PCFG_GPU_REVISION_ID_AND_CLASSCODE_PGM_INTERFACE 15:8 /* R-IVF */ #define NV_EP_PCFG_GPU_REVISION_ID_AND_CLASSCODE_SUB_CLASSCODE 23:16 /* R-IVF */ @@ -36,6 +42,8 @@ #define NV_EP_PCFG_GPU_BARREG0_REG_ADDR_TYPE 2:1 /* R-IVF */ #define NV_EP_PCFG_GPU_BARREG0_REG_ADDR_TYPE_32BIT 0x00000000 /* R-I-V */ #define NV_EP_PCFG_GPU_BARREG0_REG_ADDR_TYPE_64BIT 0x00000002 /* R---V */ +#define NV_EP_PCFG_GPU_BARREG0_REG_BASE_ADDRESS 31:18 /* RWIVF */ +#define NV_EP_PCFG_GPU_BARREG0_REG_BASE_ADDRESS_INIT 0x00000000 /* RWI-V */ #define NV_EP_PCFG_GPU_BARREG5 0x00000024 /* RW-4R */ #define NV_EP_PCFG_GPU_SUBSYSTEM_ID 0x0000002C /* R--4R */ #define NV_EP_PCFG_GPU_MSI_64_HEADER 0x00000048 /* RW-4R */ diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/common/inc/swref/published/hopper/gh100/hwproject.h nvidia-open-gpu-kernel-modules-535.161.08/src/common/inc/swref/published/hopper/gh100/hwproject.h --- nvidia-open-gpu-kernel-modules-525.147.05/src/common/inc/swref/published/hopper/gh100/hwproject.h 2023-10-25 20:19:52.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/common/inc/swref/published/hopper/gh100/hwproject.h 2024-03-05 22:11:57.000000000 +0000 @@ -21,9 +21,6 @@ * DEALINGS IN THE SOFTWARE. */ #define NV_CHIP_EXTENDED_SYSTEM_PHYSICAL_ADDRESS_BITS 52 -#define NV_LTC_PRI_STRIDE 8192 -#define NV_LTS_PRI_STRIDE 512 -#define NV_FBPA_PRI_STRIDE 16384 -#define NV_SCAL_LITTER_NUM_FBPAS 24 #define NV_XPL_BASE_ADDRESS 540672 #define NV_XTL_BASE_ADDRESS 593920 +#define NV_FBPA_PRI_STRIDE 16384 diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/common/inc/swref/published/maxwell/gm107/dev_nv_xve.h nvidia-open-gpu-kernel-modules-535.161.08/src/common/inc/swref/published/maxwell/gm107/dev_nv_xve.h --- nvidia-open-gpu-kernel-modules-525.147.05/src/common/inc/swref/published/maxwell/gm107/dev_nv_xve.h 2023-10-25 20:19:53.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/common/inc/swref/published/maxwell/gm107/dev_nv_xve.h 2024-03-05 22:11:58.000000000 +0000 @@ -31,9 +31,18 @@ #define NV_XVE_DEV_CTRL_CMD_IO_SPACE 0:0 /* RWIVF */ #define NV_XVE_DEV_CTRL_CMD_IO_SPACE_DISABLED 0x00000000 /* RWI-V */ #define NV_XVE_DEV_CTRL_CMD_IO_SPACE_ENABLED 0x00000001 /* RW--V */ +#define NV_XVE_DEV_CTRL_CMD_MEMORY_SPACE 1:1 /* RWIVF */ +#define NV_XVE_DEV_CTRL_CMD_MEMORY_SPACE_DISABLED 0x00000000 /* RWI-V */ +#define NV_XVE_DEV_CTRL_CMD_MEMORY_SPACE_ENABLED 0x00000001 /* RW--V */ +#define NV_XVE_DEV_CTRL_CMD_BUS_MASTER 2:2 /* RWIVF */ +#define NV_XVE_DEV_CTRL_CMD_BUS_MASTER_DISABLED 0x00000000 /* RWI-V */ +#define NV_XVE_DEV_CTRL_CMD_BUS_MASTER_ENABLED 0x00000001 /* RW--V */ #define NV_XVE_REV_ID 0x00000008 /* R--4R */ #define NV_XVE_REV_ID_CLASS_CODE 31:8 /* R-CVF */ #define NV_XVE_REV_ID_CLASS_CODE_3D 0x00030200 /* ----V */ +#define NV_XVE_BAR0 0x00000010 /* RW-4R */ +#define NV_XVE_BAR0_BASE_ADDRESS 31:24 /* RWIVF */ +#define NV_XVE_BAR0_BASE_ADDRESS_INIT 0x00000000 /* RWI-V */ #define NV_XVE_SUBSYSTEM 0x0000002C /* R--4R */ #define NV_XVE_MSI_CTRL 0x00000068 /* RW-4R */ #define NV_XVE_MSI_CTRL_MSI 16:16 /* RWIVF */ diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/common/inc/swref/published/maxwell/gm107/dev_ram.h nvidia-open-gpu-kernel-modules-535.161.08/src/common/inc/swref/published/maxwell/gm107/dev_ram.h --- nvidia-open-gpu-kernel-modules-525.147.05/src/common/inc/swref/published/maxwell/gm107/dev_ram.h 2023-10-25 20:19:54.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/common/inc/swref/published/maxwell/gm107/dev_ram.h 2024-03-05 22:11:58.000000000 +0000 @@ -47,6 +47,7 @@ #define NV_RAMUSERD_GP_GET (34*32+31):(34*32+0) /* RWXUF */ #define NV_RAMUSERD_GP_PUT (35*32+31):(35*32+0) /* RWXUF */ #define NV_RAMUSERD_BASE_SHIFT 9 /* */ +#define NV_RAMUSERD_CHAN_SIZE 512 /* */ #define NV_RAMUSERD_GP_TOP_LEVEL_GET (22*32+31):(22*32+0) /* RWXUF */ #define NV_RAMUSERD_GP_TOP_LEVEL_GET_HI (23*32+31):(23*32+0) /* RWXUF */ #define NV_RAMRL_BASE_SHIFT 12 /* */ diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/common/inc/swref/published/nvswitch/ls10/dev_nvldl_ip_addendum.h nvidia-open-gpu-kernel-modules-535.161.08/src/common/inc/swref/published/nvswitch/ls10/dev_nvldl_ip_addendum.h --- nvidia-open-gpu-kernel-modules-525.147.05/src/common/inc/swref/published/nvswitch/ls10/dev_nvldl_ip_addendum.h 2023-10-25 20:20:00.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/common/inc/swref/published/nvswitch/ls10/dev_nvldl_ip_addendum.h 2024-03-05 22:12:08.000000000 +0000 @@ -25,12 +25,12 @@ #define __ls10_dev_nvldl_ip_addendum_h__ #define NV_NVLDL_CRC_BIT_ERROR_RATE_SHORT_THRESHOLD_MAN 2:0 -#define NV_NVLDL_CRC_BIT_ERROR_RATE_SHORT_THRESHOLD_MAN_DEFAULT 0x00000007 +#define NV_NVLDL_CRC_BIT_ERROR_RATE_SHORT_THRESHOLD_MAN_DEFAULT 0x00000003 #define NV_NVLDL_CRC_BIT_ERROR_RATE_SHORT_THRESHOLD_EXP 3:3 -#define NV_NVLDL_CRC_BIT_ERROR_RATE_SHORT_THRESHOLD_EXP_DEFAULT 0x00000000 +#define NV_NVLDL_CRC_BIT_ERROR_RATE_SHORT_THRESHOLD_EXP_DEFAULT 0x00000001 #define NV_NVLDL_CRC_BIT_ERROR_RATE_SHORT_TIMESCALE_MAN 6:4 -#define NV_NVLDL_CRC_BIT_ERROR_RATE_SHORT_TIMESCALE_MAN_DEFAULT 0x00000005 +#define NV_NVLDL_CRC_BIT_ERROR_RATE_SHORT_TIMESCALE_MAN_DEFAULT 0x00000000 #define NV_NVLDL_CRC_BIT_ERROR_RATE_SHORT_TIMESCALE_EXP 12:8 -#define NV_NVLDL_CRC_BIT_ERROR_RATE_SHORT_TIMESCALE_EXP_DEFAULT 0x00000005 +#define NV_NVLDL_CRC_BIT_ERROR_RATE_SHORT_TIMESCALE_EXP_DEFAULT 0x00000006 #endif // __ls10_dev_nvldl_ip_addendum_h__ diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/common/inc/swref/published/turing/tu102/dev_falcon_v4.h nvidia-open-gpu-kernel-modules-535.161.08/src/common/inc/swref/published/turing/tu102/dev_falcon_v4.h --- nvidia-open-gpu-kernel-modules-525.147.05/src/common/inc/swref/published/turing/tu102/dev_falcon_v4.h 2023-10-25 20:20:05.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/common/inc/swref/published/turing/tu102/dev_falcon_v4.h 2024-03-05 22:12:14.000000000 +0000 @@ -110,7 +110,18 @@ #define NV_PFALCON_FALCON_DMEMC_AINCW 24:24 /* RWIVF */ #define NV_PFALCON_FALCON_DMEMC_AINCW_TRUE 0x00000001 /* RW--V */ #define NV_PFALCON_FALCON_DMEMC_AINCW_FALSE 0x00000000 /* RW--V */ +#define NV_PFALCON_FALCON_DMEMC_AINCR 25:25 /* RWIVF */ +#define NV_PFALCON_FALCON_DMEMC_AINCR_TRUE 0x00000001 /* RW--V */ +#define NV_PFALCON_FALCON_DMEMC_AINCR_FALSE 0x00000000 /* RW--V */ #define NV_PFALCON_FALCON_DMEMD(i) (0x000001c4+(i)*8) /* RW-4A */ #define NV_PFALCON_FALCON_DMEMD_DATA 31:0 /* RW-VF */ +#define NV_PFALCON_FALCON_COMMON_SCRATCH_GROUP_0(i) (0x00000300+(i)*4) /* RW-4A */ +#define NV_PFALCON_FALCON_COMMON_SCRATCH_GROUP_0__SIZE_1 4 /* */ +#define NV_PFALCON_FALCON_COMMON_SCRATCH_GROUP_1(i) (0x00000310+(i)*4) /* RW-4A */ +#define NV_PFALCON_FALCON_COMMON_SCRATCH_GROUP_1__SIZE_1 4 /* */ +#define NV_PFALCON_FALCON_COMMON_SCRATCH_GROUP_2(i) (0x00000320+(i)*4) /* RW-4A */ +#define NV_PFALCON_FALCON_COMMON_SCRATCH_GROUP_2__SIZE_1 4 /* */ +#define NV_PFALCON_FALCON_COMMON_SCRATCH_GROUP_3(i) (0x00000330+(i)*4) /* RW-4A */ +#define NV_PFALCON_FALCON_COMMON_SCRATCH_GROUP_3__SIZE_1 4 /* */ #endif // __tu102_dev_falcon_v4_h__ diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/common/inc/swref/published/turing/tu102/dev_fb.h nvidia-open-gpu-kernel-modules-535.161.08/src/common/inc/swref/published/turing/tu102/dev_fb.h --- nvidia-open-gpu-kernel-modules-525.147.05/src/common/inc/swref/published/turing/tu102/dev_fb.h 2023-10-25 20:20:05.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/common/inc/swref/published/turing/tu102/dev_fb.h 2024-03-05 22:12:14.000000000 +0000 @@ -38,4 +38,25 @@ #define NV_PFB_PRI_MMU_WPR2_ADDR_HI_VAL 31:4 /* RWEVF */ #define NV_PFB_PRI_MMU_WPR2_ADDR_HI_ALIGNMENT 0x0000000c /* */ +#define NV_PFB_PRI_MMU_L2TLB_ECC_UNCORRECTED_ERR_COUNT 0x00100E78 /* RW-4R */ +#define NV_PFB_PRI_MMU_L2TLB_ECC_UNCORRECTED_ERR_COUNT 0x00100E78 /* RW-4R */ +#define NV_PFB_PRI_MMU_L2TLB_ECC_UNCORRECTED_ERR_COUNT_TOTAL 15:0 /* RWEVF */ +#define NV_PFB_PRI_MMU_L2TLB_ECC_UNCORRECTED_ERR_COUNT_TOTAL_INIT 0 /* RWE-V */ +#define NV_PFB_PRI_MMU_L2TLB_ECC_UNCORRECTED_ERR_COUNT_UNIQUE 31:16 /* RWEVF */ +#define NV_PFB_PRI_MMU_L2TLB_ECC_UNCORRECTED_ERR_COUNT_UNIQUE_INIT 0 /* RWE-V */ + +#define NV_PFB_PRI_MMU_HUBTLB_ECC_UNCORRECTED_ERR_COUNT 0x00100E8C /* RW-4R */ +#define NV_PFB_PRI_MMU_HUBTLB_ECC_UNCORRECTED_ERR_COUNT 0x00100E8C /* RW-4R */ +#define NV_PFB_PRI_MMU_HUBTLB_ECC_UNCORRECTED_ERR_COUNT_TOTAL 15:0 /* RWEVF */ +#define NV_PFB_PRI_MMU_HUBTLB_ECC_UNCORRECTED_ERR_COUNT_TOTAL_INIT 0 /* RWE-V */ +#define NV_PFB_PRI_MMU_HUBTLB_ECC_UNCORRECTED_ERR_COUNT_UNIQUE 31:16 /* RWEVF */ +#define NV_PFB_PRI_MMU_HUBTLB_ECC_UNCORRECTED_ERR_COUNT_UNIQUE_INIT 0 /* RWE-V */ + +#define NV_PFB_PRI_MMU_FILLUNIT_ECC_UNCORRECTED_ERR_COUNT 0x00100EA0 /* RW-4R */ +#define NV_PFB_PRI_MMU_FILLUNIT_ECC_UNCORRECTED_ERR_COUNT 0x00100EA0 /* RW-4R */ +#define NV_PFB_PRI_MMU_FILLUNIT_ECC_UNCORRECTED_ERR_COUNT_TOTAL 15:0 /* RWEVF */ +#define NV_PFB_PRI_MMU_FILLUNIT_ECC_UNCORRECTED_ERR_COUNT_TOTAL_INIT 0 /* RWE-V */ +#define NV_PFB_PRI_MMU_FILLUNIT_ECC_UNCORRECTED_ERR_COUNT_UNIQUE 31:16 /* RWEVF */ +#define NV_PFB_PRI_MMU_FILLUNIT_ECC_UNCORRECTED_ERR_COUNT_UNIQUE_INIT 0 /* RWE-V */ + #endif // __tu102_dev_fb_h__ diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/common/inc/swref/published/turing/tu102/dev_fbpa.h nvidia-open-gpu-kernel-modules-535.161.08/src/common/inc/swref/published/turing/tu102/dev_fbpa.h --- nvidia-open-gpu-kernel-modules-525.147.05/src/common/inc/swref/published/turing/tu102/dev_fbpa.h 1970-01-01 00:00:00.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/common/inc/swref/published/turing/tu102/dev_fbpa.h 2024-03-05 22:12:15.000000000 +0000 @@ -0,0 +1,29 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2023 NVIDIA CORPORATION & AFFILIATES + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef __tu102_dev_fbpa_h_ +#define __tu102_dev_fbpa_h_ + +#define NV_PFB_FBPA_0_ECC_DED_COUNT__SIZE_1 2 /* */ +#define NV_PFB_FBPA_0_ECC_DED_COUNT(i) (0x00900488+(i)*4) /* RW-4A */ +#endif // __tu102_dev_fbpa_h_ diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/common/inc/swref/published/turing/tu102/dev_gc6_island.h nvidia-open-gpu-kernel-modules-535.161.08/src/common/inc/swref/published/turing/tu102/dev_gc6_island.h --- nvidia-open-gpu-kernel-modules-525.147.05/src/common/inc/swref/published/turing/tu102/dev_gc6_island.h 2023-10-25 20:20:05.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/common/inc/swref/published/turing/tu102/dev_gc6_island.h 2024-03-05 22:12:15.000000000 +0000 @@ -24,6 +24,7 @@ #ifndef __tu102_dev_gc6_island_h__ #define __tu102_dev_gc6_island_h__ +#define NV_PGC6 0x118fff:0x118000 /* RW--D */ #define NV_PGC6_AON_SECURE_SCRATCH_GROUP_05_PRIV_LEVEL_MASK 0x00118128 /* RW-4R */ #define NV_PGC6_AON_SECURE_SCRATCH_GROUP_05_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */ #define NV_PGC6_AON_SECURE_SCRATCH_GROUP_05_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */ diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/common/inc/swref/published/turing/tu102/dev_gsp.h nvidia-open-gpu-kernel-modules-535.161.08/src/common/inc/swref/published/turing/tu102/dev_gsp.h --- nvidia-open-gpu-kernel-modules-525.147.05/src/common/inc/swref/published/turing/tu102/dev_gsp.h 2023-10-25 20:20:06.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/common/inc/swref/published/turing/tu102/dev_gsp.h 2024-03-05 22:12:15.000000000 +0000 @@ -38,5 +38,22 @@ #define NV_PGSP_QUEUE_HEAD(i) (0x110c00+(i)*8) /* RW-4A */ #define NV_PGSP_QUEUE_HEAD__SIZE_1 8 /* */ #define NV_PGSP_QUEUE_HEAD_ADDRESS 31:0 /* RWIVF */ +#define NV_PGSP_EMEMC(i) (0x110ac0+(i)*8) /* RW-4A */ +#define NV_PGSP_EMEMC__SIZE_1 4 /* */ +#define NV_PGSP_EMEMC_OFFS 7:2 /* RWIVF */ +#define NV_PGSP_EMEMC_OFFS_INIT 0x00000000 /* RWI-V */ +#define NV_PGSP_EMEMC_BLK 15:8 /* RWIVF */ +#define NV_PGSP_EMEMC_BLK_INIT 0x00000000 /* RWI-V */ +#define NV_PGSP_EMEMC_AINCW 24:24 /* RWIVF */ +#define NV_PGSP_EMEMC_AINCW_INIT 0x00000000 /* RWI-V */ +#define NV_PGSP_EMEMC_AINCW_TRUE 0x00000001 /* RW--V */ +#define NV_PGSP_EMEMC_AINCW_FALSE 0x00000000 /* RW--V */ +#define NV_PGSP_EMEMC_AINCR 25:25 /* RWIVF */ +#define NV_PGSP_EMEMC_AINCR_INIT 0x00000000 /* RWI-V */ +#define NV_PGSP_EMEMC_AINCR_TRUE 0x00000001 /* RW--V */ +#define NV_PGSP_EMEMC_AINCR_FALSE 0x00000000 /* RW--V */ +#define NV_PGSP_EMEMD(i) (0x110ac4+(i)*8) /* RW-4A */ +#define NV_PGSP_EMEMD__SIZE_1 4 /* */ +#define NV_PGSP_EMEMD_DATA 31:0 /* RW-VF */ #endif // __tu102_dev_gsp_h__ diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/common/inc/swref/published/turing/tu102/dev_ltc.h nvidia-open-gpu-kernel-modules-535.161.08/src/common/inc/swref/published/turing/tu102/dev_ltc.h --- nvidia-open-gpu-kernel-modules-525.147.05/src/common/inc/swref/published/turing/tu102/dev_ltc.h 1970-01-01 00:00:00.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/common/inc/swref/published/turing/tu102/dev_ltc.h 2024-03-05 22:12:17.000000000 +0000 @@ -0,0 +1,33 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2023 NVIDIA CORPORATION & AFFILIATES + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef __tu102_dev_ltc_h_ +#define __tu102_dev_ltc_h_ + +#define NV_PLTCG_LTC0_LTS0_L2_CACHE_ECC_UNCORRECTED_ERR_COUNT 0x001404f8 /* RW-4R */ +#define NV_PLTCG_LTC0_LTS0_L2_CACHE_ECC_UNCORRECTED_ERR_COUNT_TOTAL 15:0 /* RWIVF */ +#define NV_PLTCG_LTC0_LTS0_L2_CACHE_ECC_UNCORRECTED_ERR_COUNT_TOTAL_INIT 0x0000 /* RWI-V */ +#define NV_PLTCG_LTC0_LTS0_L2_CACHE_ECC_UNCORRECTED_ERR_COUNT_UNIQUE 31:16 /* RWIVF */ +#define NV_PLTCG_LTC0_LTS0_L2_CACHE_ECC_UNCORRECTED_ERR_COUNT_UNIQUE_INIT 0x0000 /* RWI-V */ + +#endif // __tu102_dev_ltc_h_ diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/common/inc/swref/published/turing/tu102/dev_nv_xve.h nvidia-open-gpu-kernel-modules-535.161.08/src/common/inc/swref/published/turing/tu102/dev_nv_xve.h --- nvidia-open-gpu-kernel-modules-525.147.05/src/common/inc/swref/published/turing/tu102/dev_nv_xve.h 2023-10-25 20:20:06.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/common/inc/swref/published/turing/tu102/dev_nv_xve.h 2024-03-05 22:12:18.000000000 +0000 @@ -28,6 +28,10 @@ #define NV_XVE_MSIX_CAP_HDR_ENABLE 31:31 /* RWIVF */ #define NV_XVE_MSIX_CAP_HDR_ENABLE_ENABLED 0x00000001 /* RW--V */ #define NV_XVE_MSIX_CAP_HDR_ENABLE_DISABLED 0x00000000 /* RWI-V */ +#define NV_XVE_PRIV_MISC_1 0x0000041C /* RW-4R */ +#define NV_XVE_PRIV_MISC_1_CYA_HIDE_MSIX_CAP 29:29 /* RWCVF */ +#define NV_XVE_PRIV_MISC_1_CYA_HIDE_MSIX_CAP_TRUE 0x00000001 /* RW--V */ +#define NV_XVE_PRIV_MISC_1_CYA_HIDE_MSIX_CAP_FALSE 0x00000000 /* RWC-V */ #define NV_XVE_SRIOV_CAP_HDR3 0x00000BD8 /* R--4R */ #define NV_XVE_SRIOV_CAP_HDR3_TOTAL_VFS 31:16 /* R-EVF */ #define NV_XVE_SRIOV_CAP_HDR5 0x00000BE0 /* R--4R */ diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/common/inc/swref/published/turing/tu102/hwproject.h nvidia-open-gpu-kernel-modules-535.161.08/src/common/inc/swref/published/turing/tu102/hwproject.h --- nvidia-open-gpu-kernel-modules-525.147.05/src/common/inc/swref/published/turing/tu102/hwproject.h 2023-10-25 20:20:07.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/common/inc/swref/published/turing/tu102/hwproject.h 2024-03-05 22:12:20.000000000 +0000 @@ -25,5 +25,9 @@ #define __tu102_hwproject_h__ #define NV_CHIP_EXTENDED_SYSTEM_PHYSICAL_ADDRESS_BITS 47 +#define NV_SCAL_LITTER_NUM_FBPAS 16 +#define NV_FBPA_PRI_STRIDE 16384 +#define NV_LTC_PRI_STRIDE 8192 +#define NV_LTS_PRI_STRIDE 512 #endif // __tu102_hwproject_h__ diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/common/modeset/hdmipacket/nvhdmipkt.c nvidia-open-gpu-kernel-modules-535.161.08/src/common/modeset/hdmipacket/nvhdmipkt.c --- nvidia-open-gpu-kernel-modules-525.147.05/src/common/modeset/hdmipacket/nvhdmipkt.c 2023-10-25 20:22:26.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/common/modeset/hdmipacket/nvhdmipkt.c 2024-03-05 22:12:01.000000000 +0000 @@ -181,24 +181,6 @@ }, }; -#if defined(DSC_CALLBACK_MODIFIED) -// Callbacks for DSC PPS library -void *hdmipktMallocCb(const void *clientHandle, NvLength size); -void hdmipktFreeCb(const void *clientHandle, void *pMemPtr); - -void *hdmipktMallocCb(const void *clientHandle, NvLength size) -{ - const NVHDMIPKT_CLASS *pClass = (const NVHDMIPKT_CLASS*)(clientHandle); - return pClass->callback.malloc(pClass->cbHandle, size); -} - -void hdmipktFreeCb(const void *clientHandle, void *pMemPtr) -{ - const NVHDMIPKT_CLASS *pClass = (const NVHDMIPKT_CLASS*)(clientHandle); - pClass->callback.free(pClass->cbHandle, pMemPtr); -} -#endif // DSC_CALLBACK_MODIFIED - /********************************** HDMI Library interfaces *************************************/ /* * NvHdmiPkt_PacketCtrl @@ -581,15 +563,6 @@ // 2. Constructor calls result = NvHdmiPkt_CallConstructors(thisClassId, pClass); -#if defined(DSC_CALLBACK_MODIFIED) - DSC_CALLBACK callbacks; - NVMISC_MEMSET(&callbacks, 0, sizeof(DSC_CALLBACK)); - callbacks.clientHandle = pClass; - callbacks.dscMalloc = hdmipktMallocCb; - callbacks.dscFree = hdmipktFreeCb; - DSC_InitializeCallback(callbacks); -#endif // DSC_CALLBACK_MODIFIED - NvHdmiPkt_InitializeLibrary_exit: if (result) { diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/common/modeset/hdmipacket/nvhdmipkt_9171.c nvidia-open-gpu-kernel-modules-535.161.08/src/common/modeset/hdmipacket/nvhdmipkt_9171.c --- nvidia-open-gpu-kernel-modules-525.147.05/src/common/modeset/hdmipacket/nvhdmipkt_9171.c 2023-10-25 20:22:27.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/common/modeset/hdmipacket/nvhdmipkt_9171.c 2024-03-05 22:12:02.000000000 +0000 @@ -573,12 +573,13 @@ packetLen == 0 || pPacketIn == 0 || pktType9171 == NVHDMIPKT_9171_INVALID_PKT_TYPE) { result = NVHDMIPKT_INVALID_ARG; + NvHdmiPkt_Print(pThis, "Invalid arg"); goto hdmiPacketWrite9171_exit; } if ((result = validateInputPacketLength(pktType9171, packetLen, pPacketIn)) != NVHDMIPKT_SUCCESS) { - NvHdmiPkt_Print(pThis, "ERROR - input packet length incorrect"); + NvHdmiPkt_Print(pThis, "ERROR - input packet length incorrect %d", packetLen); NvHdmiPkt_Assert(0); goto hdmiPacketWrite9171_exit; } diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/common/modeset/hdmipacket/nvhdmipkt_C671.c nvidia-open-gpu-kernel-modules-535.161.08/src/common/modeset/hdmipacket/nvhdmipkt_C671.c --- nvidia-open-gpu-kernel-modules-525.147.05/src/common/modeset/hdmipacket/nvhdmipkt_C671.c 2023-10-25 20:22:27.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/common/modeset/hdmipacket/nvhdmipkt_C671.c 2024-03-05 22:12:02.000000000 +0000 @@ -460,6 +460,7 @@ #endif // NVHDMIPKT_RM_CALLS_INTERNAL { bIsDSCPossible = pGetHdmiFrlCapacityComputationParams->dsc.bIsDSCPossible; + *pFRLParams = pGetHdmiFrlCapacityComputationParams->input; } pThis->callback.free(pThis->cbHandle, pGetHdmiFrlCapacityComputationParams); @@ -1167,18 +1168,29 @@ NvU64 availableLinkBw = (NvU64)(frlBitRateGbps) * (NvU64)(numLanes) * MULTIPLIER_1G; warData.connectorType = DSC_HDMI; + DSC_GENERATE_PPS_OPAQUE_WORKAREA *pDscScratchBuffer = NULL; + pDscScratchBuffer = (DSC_GENERATE_PPS_OPAQUE_WORKAREA*)pThis->callback.malloc(pThis->cbHandle, + sizeof(DSC_GENERATE_PPS_OPAQUE_WORKAREA)); + if ((DSC_GeneratePPS(&dscInfo, &dscModesetInfo, &warData, availableLinkBw, pFRLConfig->dscInfo.pps, - &bitsPerPixelX16)) != NVT_STATUS_SUCCESS) + &bitsPerPixelX16, + pDscScratchBuffer)) != NVT_STATUS_SUCCESS) { NvHdmiPkt_Print(pThis, "ERROR - DSC PPS calculation failed."); NvHdmiPkt_Assert(0); result = NVHDMIPKT_FAIL; } + if (pDscScratchBuffer != NULL) + { + pThis->callback.free(pThis->cbHandle, pDscScratchBuffer); + pDscScratchBuffer = NULL; + } + // DSC lib should honor the bpp setting passed from client, assert here just in case NvHdmiPkt_Assert(bitsPerPixelX16 == pFRLConfig->dscInfo.bitsPerPixelX16); } diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/common/modeset/timing/displayid20.h nvidia-open-gpu-kernel-modules-535.161.08/src/common/modeset/timing/displayid20.h --- nvidia-open-gpu-kernel-modules-525.147.05/src/common/modeset/timing/displayid20.h 2023-10-25 20:22:28.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/common/modeset/timing/displayid20.h 2024-03-05 22:12:03.000000000 +0000 @@ -1,6 +1,6 @@ //***************************************************************************** // -// SPDX-FileCopyrightText: Copyright (c) 2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. +// SPDX-FileCopyrightText: Copyright (c) 2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. // SPDX-License-Identifier: MIT // // Permission is hereby granted, free of charge, to any person obtaining a @@ -275,7 +275,7 @@ #define DISPLAYID_2_0_TIMING_DSC_PASSTHRU_TIMING 1 -// the following fields apply to Timing Descriptors 7 (Not all of them are +// the following fields apply to Timing 7 Descriptors (Not all of them are // used per descriptor, but the format is the same #define DISPLAYID_2_0_TIMING_ASPECT_RATIO_1_1 0 #define DISPLAYID_2_0_TIMING_ASPECT_RATIO_5_4 1 @@ -308,29 +308,15 @@ NvU8 data_bytes; // Values range from 1(0x01) to 248(0xF8) } DISPLAYID_2_0_TIMING_8_BLOCK_HEADER; -typedef struct _tagDISPLAYID_2_0_TIMING_8_ONE_BYTE_CODE -{ - NvU8 timing_code; -} DISPLAYID_2_0_TIMING_8_ONE_BYTE_CODE; - -typedef struct _tagDISPLAYID_2_0_TIMING_8_TWO_BYTE_CODE -{ - NvU8 timing_code[2]; -} DISPLAYID_2_0_TIMING_8_TWO_BYTE_CODE; - #define DISPLAYID_2_0_TIMING_8_MAX_CODES 248 typedef struct _tagDISPLAYID_2_0_TIMING_8_BLOCK { DISPLAYID_2_0_TIMING_8_BLOCK_HEADER header; - - union - { - DISPLAYID_2_0_TIMING_8_ONE_BYTE_CODE timing_code_1[DISPLAYID_2_0_TIMING_8_MAX_CODES]; - DISPLAYID_2_0_TIMING_8_TWO_BYTE_CODE timing_code_2[DISPLAYID_2_0_TIMING_8_MAX_CODES / 2]; - }; + NvU8 timingCode[DISPLAYID_2_0_TIMING_8_MAX_CODES]; } DISPLAYID_2_0_TIMING_8_BLOCK; +// the following fields apply to Timing 8 Descriptors #define DISPLAYID_2_0_TIMING_CODE_DMT 0 #define DISPLAYID_2_0_TIMING_CODE_CTA_VIC 1 #define DISPLAYID_2_0_TIMING_CODE_HDMI_VIC 2 @@ -353,6 +339,7 @@ NvU8 refresh_rate; // 1 Hz to 256 Hz } DISPLAYID_2_0_TIMING_9_DESCRIPTOR; +// the following fields apply to Timing 9/10 Descriptors #define DISPLAYID_2_0_TIMING_FORMULA_CVT_1_2_STANDARD 0 #define DISPLAYID_2_0_TIMING_FORMULA_CVT_1_2_REDUCED_BLANKING_1 1 #define DISPLAYID_2_0_TIMING_FORMULA_CVT_2_0_REDUCED_BLANKING_2 2 @@ -384,8 +371,8 @@ { struct { NvU8 timing_formula :3; - NvU8 early_vsync :1; - NvU8 rr1000div1001_or_hblank :1; + NvU8 early_vsync :1; + NvU8 rr1000div1001_or_hblank :1; NvU8 stereo_support :2; NvU8 ycc420_support :1; } options; diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/common/modeset/timing/nvt_displayid20.c nvidia-open-gpu-kernel-modules-535.161.08/src/common/modeset/timing/nvt_displayid20.c --- nvidia-open-gpu-kernel-modules-525.147.05/src/common/modeset/timing/nvt_displayid20.c 2023-10-25 20:22:28.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/common/modeset/timing/nvt_displayid20.c 2024-03-05 22:12:03.000000000 +0000 @@ -1,6 +1,6 @@ //***************************************************************************** // -// SPDX-FileCopyrightText: Copyright (c) 2021 NVIDIA CORPORATION & AFFILIATES. All rights reserved. +// SPDX-FileCopyrightText: Copyright (c) 2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. // SPDX-License-Identifier: MIT // // Permission is hereby granted, free of charge, to any person obtaining a @@ -42,7 +42,7 @@ static NVT_STATUS parseDisplayId20ExtensionSection(const DISPLAYID_2_0_SECTION *pSection, NVT_DISPLAYID_2_0_INFO *pDisplayIdInfo); // DisplayID20 Data Block Tag Alloction -static NVT_STATUS parseDisplayId20ProductIdentity(const DISPLAYID_2_0_DATA_BLOCK_HEADER *pDataBlock, NVT_DISPLAYID_2_0_INFO *pDisplayIdInfo); // 0x20 Product Identificaton Block Tag +static NVT_STATUS parseDisplayId20ProductIdentity(const DISPLAYID_2_0_DATA_BLOCK_HEADER *pDataBlock, NVT_DISPLAYID_2_0_INFO *pDisplayIdInfo); // 0x20 Product Identificaton static NVT_STATUS parseDisplayId20DisplayParam(const DISPLAYID_2_0_DATA_BLOCK_HEADER *pDataBlock, NVT_DISPLAYID_2_0_INFO *pDisplayIdInfo); // 0x21 Display Parameters static NVT_STATUS parseDisplayId20Timing7(const DISPLAYID_2_0_DATA_BLOCK_HEADER *pDataBlock, NVT_DISPLAYID_2_0_INFO *pDisplayIdInfo); // 0x22 Type VII Timing - Detailed Timing static NVT_STATUS parseDisplayId20Timing8(const DISPLAYID_2_0_DATA_BLOCK_HEADER *pDataBlock, NVT_DISPLAYID_2_0_INFO *pDisplayIdInfo); // 0x23 Type VIII Timing - Enumerated Timing @@ -52,18 +52,16 @@ static NVT_STATUS parseDisplayId20Stereo(const DISPLAYID_2_0_DATA_BLOCK_HEADER *pDataBlock, NVT_DISPLAYID_2_0_INFO *pDisplayIdInfo); // 0x27 Stereo Display Interface static NVT_STATUS parseDisplayId20TiledDisplay(const DISPLAYID_2_0_DATA_BLOCK_HEADER *pDataBlock, NVT_DISPLAYID_2_0_INFO *pDisplayIdInfo); // 0x28 Tiled Display Topology static NVT_STATUS parseDisplayId20ContainerId(const DISPLAYID_2_0_DATA_BLOCK_HEADER *pDataBlock, NVT_DISPLAYID_2_0_INFO *pDisplayIdInfo); // 0x29 ContainerID -static NVT_STATUS parseDisplayId20Timing10(const DISPLAYID_2_0_DATA_BLOCK_HEADER *pDataBlock, NVT_DISPLAYID_2_0_INFO *pDisplayIdInfo); // 0x2A Type X Timing - Formula-based RR up to 1024Hz +static NVT_STATUS parseDisplayId20Timing10(const DISPLAYID_2_0_DATA_BLOCK_HEADER *pDataBlock, NVT_DISPLAYID_2_0_INFO *pDisplayIdInfo); // 0x2A Type X Timing - Formula-based Timing static NVT_STATUS parseDisplayId20AdaptiveSync(const DISPLAYID_2_0_DATA_BLOCK_HEADER *pDataBlock, NVT_DISPLAYID_2_0_INFO *pDisplayIdInfo); // 0x2B Adaptive-Sync -static NVT_STATUS parseDisplayId20ARVRHMD(const DISPLAYID_2_0_DATA_BLOCK_HEADER *pDataBlock, NVT_DISPLAYID_2_0_INFO *pDisplayIdInfo); // 0x2C ARVR HMD -static NVT_STATUS parseDisplayId20ARVRLayer(const DISPLAYID_2_0_DATA_BLOCK_HEADER *pDataBlock, NVT_DISPLAYID_2_0_INFO *pDisplayIdInfo); // 0x2D ARVR Layer +static NVT_STATUS parseDisplayId20ARVRHMD(const DISPLAYID_2_0_DATA_BLOCK_HEADER *pDataBlock, NVT_DISPLAYID_2_0_INFO *pDisplayIdInfo); // 0x2C ARVR HMD +static NVT_STATUS parseDisplayId20ARVRLayer(const DISPLAYID_2_0_DATA_BLOCK_HEADER *pDataBlock, NVT_DISPLAYID_2_0_INFO *pDisplayIdInfo); // 0x2D ARVR Layer static NVT_STATUS parseDisplayId20VendorSpecific(const DISPLAYID_2_0_DATA_BLOCK_HEADER *pDataBlock, NVT_DISPLAYID_2_0_INFO *pDisplayIdInfo); // 0x7E Vendor-specific static NVT_STATUS parseDisplayId20CtaData(const DISPLAYID_2_0_DATA_BLOCK_HEADER *pDataBlock, NVT_DISPLAYID_2_0_INFO *pDisplayIdInfo); // 0x81 CTA DisplayID // Helper function static NVT_STATUS getPrimaryUseCase(NvU8 product_type, NVT_DISPLAYID_PRODUCT_PRIMARY_USE_CASE *primary_use_case); -static NVT_STATUS parseDisplayId20Timing7Descriptor(const DISPLAYID_2_0_TIMING_7_DESCRIPTOR *pDescriptor, NVT_TIMING *pTiming, NvU8 revision, NvU8 count); static NVT_STATUS parseDisplayId20Timing9Descriptor(const DISPLAYID_2_0_TIMING_9_DESCRIPTOR *pDescriptor, NVT_TIMING *pTiming, NvU8 count); -static NVT_STATUS parseDisplayId20Timing10Descriptor(const void *pDescriptor, NVT_TIMING *pTiming, NvU8 payloadbytes, NvU8 count); static NvU32 greatestCommonDenominator(NvU32 x, NvU32 y); static NvU8 getExistedTimingSeqNumber(NVT_DISPLAYID_2_0_INFO *pDisplayIdInfo, enum NVT_TIMING_TYPE); @@ -626,6 +624,7 @@ return NVT_STATUS_ERR; } + revision = pTiming7Block->header.revision; descriptorCount = pDataBlock->data_bytes / (sizeof(DISPLAYID_2_0_TIMING_7_DESCRIPTOR) + pTiming7Block->header.payload_bytes_len); if (descriptorCount < 1 || descriptorCount > DISPLAYID_2_0_TIMING_7_MAX_DESCRIPTORS) @@ -642,8 +641,36 @@ for (i = 0; i < descriptorCount; i++) { NVMISC_MEMSET(&newTiming, 0, sizeof(newTiming)); - if (parseDisplayId20Timing7Descriptor(&pTiming7Block->descriptors[i], &newTiming, revision, startSeqNumber+i) == NVT_STATUS_SUCCESS) + if (parseDisplayId20Timing7Descriptor(&pTiming7Block->descriptors[i], &newTiming, startSeqNumber+i) == NVT_STATUS_SUCCESS) { + newTiming.etc.flag |= (revision >= DISPLAYID_2_0_TYPE7_DSC_PASSTHRU_REVISION && pTiming7Block->header.dsc_passthrough == 1) ? + NVT_FLAG_DISPLAYID_T7_DSC_PASSTHRU : + 0; + + if (revision >= DISPLAYID_2_0_TYPE7_YCC420_SUPPORT_REVISION) + { + newTiming.etc.flag |= pTiming7Block->descriptors[i].options.is_preferred_or_ycc420 ? NVT_FLAG_DISPLAYID_T7_T8_EXPLICT_YUV420 : 0; + + if (pTiming7Block->descriptors[i].options.is_preferred_or_ycc420) // YCC 420 support + { + UPDATE_BPC_FOR_COLORFORMAT(newTiming.etc.yuv420, 0, 1, 1, 1, 0, 1); + } + } + else + { + newTiming.etc.flag |= pTiming7Block->descriptors[i].options.is_preferred_or_ycc420 ? NVT_FLAG_DISPLAYID_DTD_PREFERRED_TIMING : 0; + } + + NVT_SNPRINTF((char *)newTiming.etc.name, sizeof(newTiming.etc.name), "DID20-Type7:#%2d:%dx%dx%3d.%03dHz/%s", + (int)NVT_GET_TIMING_STATUS_SEQ(newTiming.etc.status), + (int)newTiming.HVisible, + (int)((newTiming.interlaced ? 2 : 1)*newTiming.VVisible), + (int)newTiming.etc.rrx1k/1000, + (int)newTiming.etc.rrx1k%1000, + (newTiming.interlaced ? "I":"P")); + newTiming.etc.name[sizeof(newTiming.etc.name) - 1] = '\0'; + newTiming.etc.rep = 0x1; + if (!assignNextAvailableDisplayId20Timing(pDisplayIdInfo, &newTiming)) { break; @@ -668,80 +695,50 @@ NVT_STATUS status = NVT_STATUS_SUCCESS; const DISPLAYID_2_0_TIMING_8_BLOCK *pTiming8Block = NULL; NVT_TIMING newTiming; - NvU8 codeType = DISPLAYID_2_0_TIMING_CODE_RSERVED; + NvU8 codeCount = 0; NvU8 startSeqNumber = 0; NvU8 i; pTiming8Block = (const DISPLAYID_2_0_TIMING_8_BLOCK *)pDataBlock; + codeCount = pDataBlock->data_bytes; - // 1-byte descriptor timing code - if (pTiming8Block->header.timing_code_size == DISPLAYID_2_0_TIMING_CODE_SIZE_1_BYTE) + if (codeCount == 0) { - if (pDataBlock->data_bytes % sizeof(DISPLAYID_2_0_TIMING_8_ONE_BYTE_CODE) != 0) - { - return NVT_STATUS_ERR; - } - - codeCount = pDataBlock->data_bytes / sizeof(DISPLAYID_2_0_TIMING_8_ONE_BYTE_CODE); - if (codeCount < 1 || codeCount > DISPLAYID_2_0_TIMING_8_MAX_CODES) - { - return NVT_STATUS_ERR; - } - - codeType = pTiming8Block->header.timing_code_type; + nvt_assert(0 && "No available byte code!"); + return NVT_STATUS_SUCCESS; + } - if (pDisplayIdInfo != NULL) - { - startSeqNumber = getExistedTimingSeqNumber(pDisplayIdInfo, NVT_TYPE_DISPLAYID_8); - } + if (codeCount > DISPLAYID_2_0_TIMING_8_MAX_CODES) + { + nvt_assert(0 && "one byte code is out of range!"); + return NVT_STATUS_SUCCESS; + } - for (i = 0; i < codeCount; i++) - { - NVMISC_MEMSET(&newTiming, 0, sizeof(newTiming)); + if (pDisplayIdInfo != NULL) + { + startSeqNumber = getExistedTimingSeqNumber(pDisplayIdInfo, NVT_TYPE_DISPLAYID_8); + } - if (codeType == DISPLAYID_2_0_TIMING_CODE_DMT) - { - if (NvTiming_EnumDMT((NvU32)(pTiming8Block->timing_code_1[i].timing_code), - &newTiming) != NVT_STATUS_SUCCESS) - { - if (pDisplayIdInfo == NULL) return NVT_STATUS_ERR; - break; - } - } - else if (codeType == DISPLAYID_2_0_TIMING_CODE_CTA_VIC) - { - if (NvTiming_EnumCEA861bTiming((NvU32)(pTiming8Block->timing_code_1[i].timing_code), - &newTiming) != NVT_STATUS_SUCCESS) - { - if (pDisplayIdInfo == NULL) return NVT_STATUS_ERR; - break; - } - } - else if (codeType == DISPLAYID_2_0_TIMING_CODE_HDMI_VIC) - { - if (NvTiming_EnumHdmiVsdbExtendedTiming((NvU32)(pTiming8Block->timing_code_1[i].timing_code), - &newTiming) != NVT_STATUS_SUCCESS) - { - if (pDisplayIdInfo == NULL) return NVT_STATUS_ERR; - break; - } - } - else - { - // RESERVED - break; - } + for (i = 0; i < codeCount; i++) + { + NVMISC_MEMSET(&newTiming, 0, sizeof(newTiming)); - newTiming.etc.flag |= ((pTiming8Block->header.revision >= 1) && pTiming8Block->header.is_support_yuv420) ? NVT_FLAG_DISPLAYID_T7_T8_EXPLICT_YUV420 : 0; - newTiming.etc.status = NVT_STATUS_DISPLAYID_8N(++startSeqNumber); + if (parseDisplayId20Timing8Descriptor(&pTiming8Block->timingCode, &newTiming, + pTiming8Block->header.timing_code_type, + pTiming8Block->header.timing_code_size, i, startSeqNumber+i) == NVT_STATUS_SUCCESS) + { + newTiming.etc.flag |= ((pTiming8Block->header.revision == 1) && pTiming8Block->header.is_support_yuv420) ? + NVT_FLAG_DISPLAYID_T7_T8_EXPLICT_YUV420 : + 0; NVT_SNPRINTF((char *)newTiming.etc.name, sizeof(newTiming.etc.name), "DID20-Type8:#%3d:%dx%dx%3d.%03dHz/%s", - (int)NVT_GET_TIMING_STATUS_SEQ(newTiming.etc.status), - (int)newTiming.HVisible, (int)newTiming.VVisible, - (int)newTiming.etc.rrx1k/1000, (int)newTiming.etc.rrx1k%1000, - (newTiming.interlaced ? "I":"P")); + (int)NVT_GET_TIMING_STATUS_SEQ(newTiming.etc.status), + (int)newTiming.HVisible, (int)newTiming.VVisible, + (int)newTiming.etc.rrx1k/1000, (int)newTiming.etc.rrx1k%1000, + (newTiming.interlaced ? "I":"P")); newTiming.etc.name[sizeof(newTiming.etc.name) - 1] = '\0'; + newTiming.etc.rep = 0x1; if (!assignNextAvailableDisplayId20Timing(pDisplayIdInfo, &newTiming)) { @@ -749,11 +746,6 @@ } } } - else - { - nvt_assert(0); - // TODO : 2-byte descriptor timing code did not define yet in DID20. - } return status; } @@ -812,11 +804,13 @@ NVT_DISPLAYID_2_0_INFO *pDisplayIdInfo) { NVT_STATUS status = NVT_STATUS_SUCCESS; - const DISPLAYID_2_0_TIMING_10_BLOCK *pTiming10Block = NULL; - NvU32 descriptorCount = 0; - NvU8 startSeqNumber = 0; - NvU8 i = 0; - NvU8 eachOfDescriptorsSize = sizeof(DISPLAYID_2_0_TIMING_10_6BYTES_DESCRIPTOR); + NvU32 descriptorCount = 0; + NvU8 startSeqNumber = 0; + NvU8 i = 0; + NvU8 eachOfDescriptorsSize = sizeof(DISPLAYID_2_0_TIMING_10_6BYTES_DESCRIPTOR); + + const DISPLAYID_2_0_TIMING_10_BLOCK *pTiming10Block = NULL; + const DISPLAYID_2_0_TIMING_10_6BYTES_DESCRIPTOR *p6bytesDescriptor = NULL; NVT_TIMING newTiming; @@ -859,9 +853,43 @@ for (i = 0; i < descriptorCount; i++) { NVMISC_MEMSET(&newTiming, 0, sizeof(newTiming)); - - if (NVT_STATUS_SUCCESS == parseDisplayId20Timing10Descriptor(&pTiming10Block->descriptors[i*eachOfDescriptorsSize], &newTiming, pTiming10Block->header.payload_bytes_len, startSeqNumber+i)) + if (NVT_STATUS_SUCCESS == parseDisplayId20Timing10Descriptor(&pTiming10Block->descriptors[i*eachOfDescriptorsSize], + &newTiming, + pTiming10Block->header.payload_bytes_len, + startSeqNumber+i)) { + p6bytesDescriptor = (const DISPLAYID_2_0_TIMING_10_6BYTES_DESCRIPTOR *)&pTiming10Block->descriptors[i*eachOfDescriptorsSize]; + + if (p6bytesDescriptor->options.ycc420_support) + { + UPDATE_BPC_FOR_COLORFORMAT(newTiming.etc.yuv420, 0, 1, 1, 1, 0, 1); + } + + if (p6bytesDescriptor->options.timing_formula == DISPLAYID_2_0_TIMING_FORMULA_CVT_1_2_STANDARD) + { + NVT_SNPRINTF((char *)newTiming.etc.name, sizeof(newTiming.etc.name), "DID20-Type10:#%3d:%dx%dx%3d.%03dHz/%s", + (int)NVT_GET_TIMING_STATUS_SEQ(newTiming.etc.status), + (int)newTiming.HVisible, + (int)newTiming.VVisible, + (int)newTiming.etc.rrx1k/1000, + (int)newTiming.etc.rrx1k%1000, + (newTiming.interlaced ? "I":"P")); + } + else + { + NVT_SNPRINTF((char *)newTiming.etc.name, sizeof(newTiming.etc.name), "DID20-Type10RB%d:#%3d:%dx%dx%3d.%03dHz/%s", + p6bytesDescriptor->options.timing_formula, + (int)NVT_GET_TIMING_STATUS_SEQ(newTiming.etc.status), + (int)newTiming.HVisible, + (int)newTiming.VVisible, + (int)newTiming.etc.rrx1k/1000, + (int)newTiming.etc.rrx1k%1000, + (newTiming.interlaced ? "I":"P")); + + } + newTiming.etc.name[sizeof(newTiming.etc.name) - 1] = '\0'; + newTiming.etc.rep = 0x1; + if (!assignNextAvailableDisplayId20Timing(pDisplayIdInfo, &newTiming)) { break; @@ -869,7 +897,11 @@ } else { - if (pDisplayIdInfo == NULL) return NVT_STATUS_ERR; + if (pDisplayIdInfo == NULL) + { + return NVT_STATUS_ERR; + } + continue; } } @@ -1306,14 +1338,18 @@ // TODO: below parser shall be updated if DID21 changed in the future if (pDataBlock->data_bytes == NVT_VESA_VENDOR_SPECIFIC_LENGTH) { - pVendorSpecific->vesaVsdb.data_struct_type.type = block->vendor_specific_data[3] & NVT_VESA_ORG_VSDB_DATA_TYPE_MASK; - pVendorSpecific->vesaVsdb.data_struct_type.color_space_and_eotf = (block->vendor_specific_data[3] & NVT_VESA_ORG_VSDB_COLOR_SPACE_AND_EOTF_MASK) >> NVT_VESA_ORG_VSDB_COLOR_SPACE_AND_EOTF_SHIFT; - - pVendorSpecific->vesaVsdb.overlapping.pixels_overlapping_count = block->vendor_specific_data[4] & NVT_VESA_ORG_VSDB_PIXELS_OVERLAPPING_MASK; - pVendorSpecific->vesaVsdb.overlapping.multi_sst = (block->vendor_specific_data[4] & NVT_VESA_ORG_VSDB_MULTI_SST_MODE_MASK) >> NVT_VESA_ORG_VSDB_MULTI_SST_MODE_SHIFT; - - pVendorSpecific->vesaVsdb.pass_through_integer.pass_through_integer_dsc = block->vendor_specific_data[5] & NVT_VESA_ORG_VSDB_PASS_THROUGH_INTEGER_MASK; - pVendorSpecific->vesaVsdb.pass_through_fractional.pass_through_fraction_dsc = block->vendor_specific_data[6] & NVT_VESA_ORG_VSDB_PASS_THROUGH_FRACTIOINAL_MASK; + pVendorSpecific->vesaVsdb.data_struct_type.type = + block->vendor_specific_data[3] & NVT_VESA_ORG_VSDB_DATA_TYPE_MASK; + pVendorSpecific->vesaVsdb.data_struct_type.color_space_and_eotf = + (block->vendor_specific_data[3] & NVT_VESA_ORG_VSDB_COLOR_SPACE_AND_EOTF_MASK) >> NVT_VESA_ORG_VSDB_COLOR_SPACE_AND_EOTF_SHIFT; + pVendorSpecific->vesaVsdb.overlapping.pixels_overlapping_count = + block->vendor_specific_data[4] & NVT_VESA_ORG_VSDB_PIXELS_OVERLAPPING_MASK; + pVendorSpecific->vesaVsdb.overlapping.multi_sst = + (block->vendor_specific_data[4] & NVT_VESA_ORG_VSDB_MULTI_SST_MODE_MASK) >> NVT_VESA_ORG_VSDB_MULTI_SST_MODE_SHIFT; + pVendorSpecific->vesaVsdb.pass_through_integer.pass_through_integer_dsc = + block->vendor_specific_data[5] & NVT_VESA_ORG_VSDB_PASS_THROUGH_INTEGER_MASK; + pVendorSpecific->vesaVsdb.pass_through_fractional.pass_through_fraction_dsc = + block->vendor_specific_data[6] & NVT_VESA_ORG_VSDB_PASS_THROUGH_FRACTIOINAL_MASK; } else { @@ -1374,9 +1410,9 @@ parseCea861Hdr10PlusDataBlock(p861Info, pDisplayIdInfo, FROM_DISPLAYID_20_DATA_BLOCK); // CEA861-F at 7.5.12 section about VFPDB block. - if (p861Info->total_vfpdb > 0) + if (p861Info->total_svr > 0) { - parse861bShortPreferredTiming(p861Info, pDisplayIdInfo, FROM_DISPLAYID_20_DATA_BLOCK); + parseCta861NativeOrPreferredTiming(p861Info, pDisplayIdInfo, FROM_DISPLAYID_20_DATA_BLOCK); } return status; @@ -1489,16 +1525,19 @@ } CODE_SEGMENT(PAGE_DD_CODE) -static NVT_STATUS +NVT_STATUS parseDisplayId20Timing7Descriptor( - const DISPLAYID_2_0_TIMING_7_DESCRIPTOR *pDescriptor, + const void *pVoidDescriptor, NVT_TIMING *pTiming, - NvU8 revision, NvU8 count) { NVT_STATUS status = NVT_STATUS_SUCCESS; NvU32 gdc = 0; + const DISPLAYID_2_0_TIMING_7_DESCRIPTOR *pDescriptor = NULL; + + pDescriptor = (const DISPLAYID_2_0_TIMING_7_DESCRIPTOR *)pVoidDescriptor; + // pclk is in 10Khz // pixel_clock is in kHz pTiming->pclk = ((pDescriptor->pixel_clock[2] << 16 | @@ -1593,36 +1632,63 @@ pTiming->etc.rrx1k = NvTiming_CalcRRx1k(pTiming->pclk, pTiming->interlaced, pTiming->HTotal, - pTiming->VTotal); + pTiming->VTotal); - pTiming->etc.flag |= (revision >= DISPLAYID_2_0_TYPE7_DSC_PASSTHRU_REVISION ) ? NVT_FLAG_DISPLAYID_T7_DSC_PASSTHRU : 0; + pTiming->etc.status = NVT_STATUS_DISPLAYID_7N(++count); - if (revision >= DISPLAYID_2_0_TYPE7_YCC420_SUPPORT_REVISION) - { - pTiming->etc.flag |= pDescriptor->options.is_preferred_or_ycc420 ? NVT_FLAG_DISPLAYID_T7_T8_EXPLICT_YUV420 : 0; + return status; +} - if (pDescriptor->options.is_preferred_or_ycc420) // YCC 420 support +CODE_SEGMENT(PAGE_DD_CODE) +NVT_STATUS +parseDisplayId20Timing8Descriptor( + const void *pVoidDescriptor, + NVT_TIMING *pTiming, + NvU8 codeType, + NvU8 codeSize, + NvU8 idx, + NvU8 count) +{ + NVT_STATUS status = NVT_STATUS_SUCCESS; + + const NvU8 *pTimingCode = (const NvU8 *)pVoidDescriptor; + const NvU16 *pTiming2ByteCode = (const NvU16 *)pVoidDescriptor; + + if (codeSize == DISPLAYID_2_0_TIMING_CODE_SIZE_1_BYTE) + { + switch (codeType) { - UPDATE_BPC_FOR_COLORFORMAT(pTiming->etc.yuv420, 0, 1, 1, 1, 0, 1); + case DISPLAYID_2_0_TIMING_CODE_DMT: //single-byte DMT ID Codes + status = NvTiming_EnumDMT((NvU32)(pTimingCode[idx]), pTiming); + break; + case DISPLAYID_2_0_TIMING_CODE_CTA_VIC: + status = NvTiming_EnumCEA861bTiming((NvU32)(pTimingCode[idx]), pTiming); + break; + case DISPLAYID_2_0_TIMING_CODE_HDMI_VIC: + status = NvTiming_EnumHdmiVsdbExtendedTiming((NvU32)(pTimingCode[idx]), pTiming); + break; + default: + { + nvt_assert(0 && "RESERVED timing code type"); + status = NVT_STATUS_ERR; + } + break; } } - else + else if (codeSize == DISPLAYID_2_0_TIMING_CODE_SIZE_2_BYTE) { - pTiming->etc.flag |= pDescriptor->options.is_preferred_or_ycc420 ? NVT_FLAG_DISPLAYID_DTD_PREFERRED_TIMING : 0; + // Standard two-byte codes + if (codeType == DISPLAYID_2_0_TIMING_CODE_DMT) + { + status = NvTiming_EnumStdTwoBytesCode((NvU16)pTiming2ByteCode[idx], pTiming); + } } - pTiming->etc.status = NVT_STATUS_DISPLAYID_7N(++count); - - NVT_SNPRINTF((char *)pTiming->etc.name, sizeof(pTiming->etc.name), "DID20-Type7:#%2d:%dx%dx%3d.%03dHz/%s", - (int)NVT_GET_TIMING_STATUS_SEQ(pTiming->etc.status), - (int)pTiming->HVisible, - (int)((pTiming->interlaced ? 2 : 1)*pTiming->VVisible), - (int)pTiming->etc.rrx1k/1000, - (int)pTiming->etc.rrx1k%1000, - (pTiming->interlaced ? "I":"P")); - pTiming->etc.name[sizeof(pTiming->etc.name) - 1] = '\0'; - - pTiming->etc.rep = 0x1; + if (status == NVT_STATUS_SUCCESS) + { + pTiming->etc.status = NVT_STATUS_DISPLAYID_8N(++count); + return status; + } return status; } @@ -1655,18 +1721,21 @@ status = NvTiming_CalcCVT_RB2(width, height, rr, pDescriptor->options.rr_1000div1001_support, pTiming); break; default: + { + nvt_assert(0 && "Unknown timing formula"); status = NVT_STATUS_ERR; + } break; } if (status == NVT_STATUS_SUCCESS) - { + { NVMISC_MEMSET(pTiming->etc.name, 0, sizeof(pTiming->etc.name)); pTiming->etc.status = NVT_STATUS_DISPLAYID_9N(++count); - if ( pDescriptor->options.timing_formula== DISPLAYID_2_0_TIMING_FORMULA_CVT_1_2_STANDARD) + if (pDescriptor->options.timing_formula == DISPLAYID_2_0_TIMING_FORMULA_CVT_1_2_STANDARD) { - NVT_SNPRINTF((char *)pTiming->etc.name, sizeof(pTiming->etc.name), "DID20-Type9:#%3d:%dx%dx%3d.%03dHz/%s", + NVT_SNPRINTF((char *)pTiming->etc.name, sizeof(pTiming->etc.name), "DID20-Type9:#%3d:%dx%dx%3d.%03dHz/%s", (int)NVT_GET_TIMING_STATUS_SEQ(pTiming->etc.status), (int)pTiming->HVisible, (int)pTiming->VVisible, @@ -1674,19 +1743,10 @@ (int)pTiming->etc.rrx1k%1000, (pTiming->interlaced ? "I":"P")); } - else if (pDescriptor->options.timing_formula == DISPLAYID_2_0_TIMING_FORMULA_CVT_1_2_REDUCED_BLANKING_1) - { - NVT_SNPRINTF((char *)pTiming->etc.name, sizeof(pTiming->etc.name), "DID20-Type9-RB1:#%3d:%dx%dx%3d.%03dHz/%s", - (int)NVT_GET_TIMING_STATUS_SEQ(pTiming->etc.status), - (int)pTiming->HVisible, - (int)pTiming->VVisible, - (int)pTiming->etc.rrx1k/1000, - (int)pTiming->etc.rrx1k%1000, - (pTiming->interlaced ? "I":"P")); - } - else if (pDescriptor->options.timing_formula == DISPLAYID_2_0_TIMING_FORMULA_CVT_2_0_REDUCED_BLANKING_2) + else { - NVT_SNPRINTF((char *)pTiming->etc.name, sizeof(pTiming->etc.name), "DID20-Type9-RB2:#%3d:%dx%dx%3d.%03dHz/%s", + NVT_SNPRINTF((char *)pTiming->etc.name, sizeof(pTiming->etc.name), "DID20-Type9RB%d:#%3d:%dx%dx%3d.%03dHz/%s", + pDescriptor->options.timing_formula, (int)NVT_GET_TIMING_STATUS_SEQ(pTiming->etc.status), (int)pTiming->HVisible, (int)pTiming->VVisible, @@ -1695,18 +1755,18 @@ (pTiming->interlaced ? "I":"P")); } } - pTiming->etc.name[sizeof(pTiming->etc.name) - 1] = '\0'; + pTiming->etc.rep = 0x1; return status; } CODE_SEGMENT(PAGE_DD_CODE) -static NVT_STATUS +NVT_STATUS parseDisplayId20Timing10Descriptor( const void *pDescriptor, NVT_TIMING *pTiming, - NvU8 payloadbytes, + NvU8 payloadBytes, NvU8 count) { NVT_STATUS status = NVT_STATUS_SUCCESS; @@ -1722,7 +1782,7 @@ height = (p6bytesDescriptor->vertical_active_lines[1] << 8 | p6bytesDescriptor->vertical_active_lines[0]) + 1; rr = p6bytesDescriptor->refresh_rate + 1; - if (payloadbytes == DISPLAYID_2_0_TIMING_10_PAYLOAD_BYTES_7) + if (payloadBytes == DISPLAYID_2_0_TIMING_10_PAYLOAD_BYTES_7) { p7bytesDescriptor = (const DISPLAYID_2_0_TIMING_10_7BYTES_DESCRIPTOR *)pDescriptor; rr = (p7bytesDescriptor->descriptor_6_bytes.refresh_rate | p7bytesDescriptor->refresh_rate_high << 8) + 1; @@ -1740,92 +1800,46 @@ status = NvTiming_CalcCVT_RB2(width, height, rr, p6bytesDescriptor->options.rr1000div1001_or_hblank, pTiming); break; case DISPLAYID_2_0_TIMING_FORMULA_CVT_2_0_REDUCED_BLANKING_3: + { + NvU32 deltaHBlank = 0; + if (p7bytesDescriptor != NULL) { - NvU32 deltaHBlank = 0; - - if (p7bytesDescriptor != NULL) + if (p6bytesDescriptor->options.rr1000div1001_or_hblank == 0) // Horizontal Blank in Pixels = [Field Value] * 8 + 80 { - if (p6bytesDescriptor->options.rr1000div1001_or_hblank == 0) // Horizontal Blank in Pixels = [Field Value] * 8 + 80 - { - deltaHBlank = p7bytesDescriptor->delta_hblank * 8; - } - else if (p6bytesDescriptor->options.rr1000div1001_or_hblank == 1) - { - if (p7bytesDescriptor->delta_hblank <= 5) - deltaHBlank = (p7bytesDescriptor->delta_hblank * 8 + 160) - 80; - else // if 5 < Field Value <=7 - deltaHBlank = (160 - ((p7bytesDescriptor->delta_hblank - 5) * 8)) - 80; - } - - status = NvTiming_CalcCVT_RB3(width, height, rr, deltaHBlank, p7bytesDescriptor->additional_vblank_timing * 35, p6bytesDescriptor->options.early_vsync, pTiming); + deltaHBlank = p7bytesDescriptor->delta_hblank * 8; } - else // 6 bytes descriptor + else if (p6bytesDescriptor->options.rr1000div1001_or_hblank == 1) { - if (p6bytesDescriptor->options.rr1000div1001_or_hblank == 1) - deltaHBlank = 80; - - status = NvTiming_CalcCVT_RB3(width, height, rr, deltaHBlank, 0, p6bytesDescriptor->options.early_vsync, pTiming); + if (p7bytesDescriptor->delta_hblank <= 5) + deltaHBlank = (p7bytesDescriptor->delta_hblank * 8 + 160) - 80; + else // if 5 < Field Value <=7 + deltaHBlank = (160 - ((p7bytesDescriptor->delta_hblank - 5) * 8)) - 80; } - break; + status = NvTiming_CalcCVT_RB3(width, height, rr, deltaHBlank, p7bytesDescriptor->additional_vblank_timing * 35, p6bytesDescriptor->options.early_vsync, pTiming); } - } - - if ( status == NVT_STATUS_SUCCESS ) - { - NVMISC_MEMSET(pTiming->etc.name, 0, sizeof(pTiming->etc.name)); - pTiming->etc.status = NVT_STATUS_DISPLAYID_10N(++count); - - if (p6bytesDescriptor->options.ycc420_support) - { - // YCC 420 support - UPDATE_BPC_FOR_COLORFORMAT(pTiming->etc.yuv420, 0, 1, 1, 1, 0, 1); - } - - if (p6bytesDescriptor->options.timing_formula == DISPLAYID_2_0_TIMING_FORMULA_CVT_1_2_STANDARD) + else // 6 bytes descriptor { - NVT_SNPRINTF((char *)pTiming->etc.name, sizeof(pTiming->etc.name), "DID20-Type10:#%3d:%dx%dx%3d.%03dHz/%s", - (int)NVT_GET_TIMING_STATUS_SEQ(pTiming->etc.status), - (int)pTiming->HVisible, - (int)pTiming->VVisible, - (int)pTiming->etc.rrx1k/1000, - (int)pTiming->etc.rrx1k%1000, - (pTiming->interlaced ? "I":"P")); + if (p6bytesDescriptor->options.rr1000div1001_or_hblank == 1) + deltaHBlank = 80; - } - else if (p6bytesDescriptor->options.timing_formula == DISPLAYID_2_0_TIMING_FORMULA_CVT_1_2_REDUCED_BLANKING_1) - { - NVT_SNPRINTF((char *)pTiming->etc.name, sizeof(pTiming->etc.name), "DID20-Type10RB1:#%3d:%dx%dx%3d.%03dHz/%s", - (int)NVT_GET_TIMING_STATUS_SEQ(pTiming->etc.status), - (int)pTiming->HVisible, - (int)pTiming->VVisible, - (int)pTiming->etc.rrx1k/1000, - (int)pTiming->etc.rrx1k%1000, - (pTiming->interlaced ? "I":"P")); - } - else if (p6bytesDescriptor->options.timing_formula == DISPLAYID_2_0_TIMING_FORMULA_CVT_2_0_REDUCED_BLANKING_2) - { - NVT_SNPRINTF((char *)pTiming->etc.name, sizeof(pTiming->etc.name), "DID20-Type10RB2:#%3d:%dx%dx%3d.%03dHz/%s", - (int)NVT_GET_TIMING_STATUS_SEQ(pTiming->etc.status), - (int)pTiming->HVisible, - (int)pTiming->VVisible, - (int)pTiming->etc.rrx1k/1000, - (int)pTiming->etc.rrx1k%1000, - (pTiming->interlaced ? "I":"P")); - } - else if (p6bytesDescriptor->options.timing_formula == DISPLAYID_2_0_TIMING_FORMULA_CVT_2_0_REDUCED_BLANKING_3) - { - NVT_SNPRINTF((char *)pTiming->etc.name, sizeof(pTiming->etc.name), "DID20-Type10RB3:#%3d:%dx%dx%3d.%03dHz/%s", - (int)NVT_GET_TIMING_STATUS_SEQ(pTiming->etc.status), - (int)pTiming->HVisible, - (int)pTiming->VVisible, - (int)pTiming->etc.rrx1k/1000, - (int)pTiming->etc.rrx1k%1000, - (pTiming->interlaced ? "I":"P")); + status = NvTiming_CalcCVT_RB3(width, height, rr, deltaHBlank, 0, p6bytesDescriptor->options.early_vsync, pTiming); } } + break; + default: + { + nvt_assert(0 && "Unknown timing formula"); + status = NVT_STATUS_ERR; + } + break; + } - pTiming->etc.name[sizeof(pTiming->etc.name) - 1] = '\0'; + if (status == NVT_STATUS_SUCCESS) + { + pTiming->etc.status = NVT_STATUS_DISPLAYID_10N(++count); + return status; + } return status; } @@ -1842,7 +1856,7 @@ switch (timingType) { - case NVT_TYPE_DISPLAYID_7: + case NVT_TYPE_DISPLAYID_7: case NVT_TYPE_DISPLAYID_8: case NVT_TYPE_DISPLAYID_9: case NVT_TYPE_DISPLAYID_10: diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/common/modeset/timing/nvt_dmt.c nvidia-open-gpu-kernel-modules-535.161.08/src/common/modeset/timing/nvt_dmt.c --- nvidia-open-gpu-kernel-modules-525.147.05/src/common/modeset/timing/nvt_dmt.c 2023-10-25 20:22:28.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/common/modeset/timing/nvt_dmt.c 2024-03-05 22:12:03.000000000 +0000 @@ -1,6 +1,6 @@ //***************************************************************************** // -// SPDX-FileCopyrightText: Copyright (c) 2021 NVIDIA CORPORATION & AFFILIATES. All rights reserved. +// SPDX-FileCopyrightText: Copyright (c) 2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. // SPDX-License-Identifier: MIT // // Permission is hereby granted, free of charge, to any person obtaining a @@ -34,7 +34,7 @@ PUSH_SEGMENTS -// DMT table +// DMT table 2-1 // Macro to declare a TIMING initializer for given parameters without border #define DMT_TIMING(hv,hfp,hsw,ht,hsp,vv,vfp,vsw,vt,vsp,rr,pclk,id) \ {hv,0,hfp,hsw,ht,(hsp)=='-',vv,0,vfp,vsw,vt,(vsp)=='-',NVT_PROGRESSIVE,pclk,{0,rr,set_rrx1k(pclk,ht,vt),0,0x1,{0},{0},{0},{0},NVT_DEF_TIMING_STATUS(NVT_TYPE_DMT,id),"VESA DMT"}} @@ -193,6 +193,43 @@ } CODE_SEGMENT(PAGE_DD_CODE) +NVT_STATUS NvTiming_EnumStdTwoBytesCode(NvU16 std2ByteCode, NVT_TIMING *pT) +{ + NvU32 aspect, width, height, rr; + + if ((pT == NULL) || (std2ByteCode == 0)) + { + return NVT_STATUS_ERR; + } + + // The value in the EDID = (Horizontal active pixels/8) - 31 + width = (std2ByteCode & 0x0FF) + 31; + width <<= 3; + rr = ((std2ByteCode >> 8) & 0x3F) + 60; // bits 5->0 + + // get the height + aspect = ((std2ByteCode >> 8) & 0xC0); // aspect ratio at bit 7:6 + + if (aspect == 0x00) height = width * 5 / 8; // 16:10 + else if (aspect == 0x40) height = width * 3 / 4; // 4:3 + else if (aspect == 0x80) height = width * 4 / 5; // 5:4 + else height = width * 9 / 16; // 16:9 + + // try to get the timing from DMT or DMT_RB + if (NvTiming_CalcDMT(width, height, rr, 0, pT) == NVT_STATUS_SUCCESS) + { + return NVT_STATUS_SUCCESS; + } + // try to get the timing from DMT_RB2 + else if (NvTiming_CalcDMT_RB2(width, height, rr, 0, pT) == NVT_STATUS_SUCCESS) + { + return NVT_STATUS_SUCCESS; + } + + return NVT_STATUS_ERR; +} + +CODE_SEGMENT(PAGE_DD_CODE) NVT_STATUS NvTiming_CalcDMT(NvU32 width, NvU32 height, NvU32 rr, NvU32 flag, NVT_TIMING *pT) { NVT_TIMING *p = (NVT_TIMING *)DMT; @@ -262,6 +299,44 @@ pT->etc.name[39] = '\0'; pT->etc.rgb444.bpc.bpc8 = 1; return NVT_STATUS_SUCCESS; + } + } + p ++; + } + return NVT_STATUS_ERR; +} + +CODE_SEGMENT(PAGE_DD_CODE) +NVT_STATUS NvTiming_CalcDMT_RB2(NvU32 width, NvU32 height, NvU32 rr, NvU32 flag, NVT_TIMING *pT) +{ + NVT_TIMING *p = (NVT_TIMING *)DMT; + + if (pT == NULL) + return NVT_STATUS_ERR; + + if (width == 0 || height == 0 || rr == 0) + return NVT_STATUS_ERR; + + // no interlaced DMT timing + if ((flag & NVT_PVT_INTERLACED_MASK) != 0) + return NVT_STATUS_ERR; + + while (p->HVisible != 0 && p->VVisible != 0) + { + // select only reduced-bandwidth timing. + if (NVT_GET_TIMING_STATUS_TYPE(p->etc.status) == NVT_TYPE_DMT_RB_2) + { + if ((NvU32)p->HVisible == width && + (NvU32)p->VVisible == height && + (NvU32)p->etc.rr == rr) + { + NVMISC_MEMSET(pT, 0, sizeof(NVT_TIMING)); + *pT = *p; + pT->etc.rrx1k = axb_div_c((NvU32)pT->pclk, (NvU32)10000*(NvU32)1000, (NvU32)pT->HTotal*(NvU32)pT->VTotal); + NVT_SNPRINTF((char *)pT->etc.name, 40, "DMT-RB2:%dx%dx%dHz",width, height, rr); + pT->etc.name[39] = '\0'; + pT->etc.rgb444.bpc.bpc8 = 1; + return NVT_STATUS_SUCCESS; } } p ++; diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/common/modeset/timing/nvt_dsc_pps.c nvidia-open-gpu-kernel-modules-535.161.08/src/common/modeset/timing/nvt_dsc_pps.c --- nvidia-open-gpu-kernel-modules-525.147.05/src/common/modeset/timing/nvt_dsc_pps.c 2023-10-25 20:22:28.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/common/modeset/timing/nvt_dsc_pps.c 2024-03-05 22:12:03.000000000 +0000 @@ -33,20 +33,19 @@ #include "nvt_dsc_pps.h" #include "nvmisc.h" #include "displayport/displayport.h" +#include "nvctassert.h" #include /* ------------------------ Macros ----------------------------------------- */ -#if defined (DEBUG) -#define DSC_Print(...) \ - do { \ - if (callbacks.dscPrint) { \ - callbacks.dscPrint("DSC: " __VA_ARGS__); \ - } \ - } while(0) -#else +// +// DSC_Print macro was for debugging purposes in early development of +// DSC PPS library. The print statements no longer get logged +// inside any client logger. But the lines of print in this file are useful +// for browsing code, hence this DSC_Print is left as a stub +// definition intentionally to help reader understand the PPS code. +// #define DSC_Print(...) do { } while(0) -#endif #define MIN_CHECK(s,a,b) { if((a)<(b)) { DSC_Print("%s (=%u) needs to be larger than %u",s,a,b); return (NVT_STATUS_ERR);} } #define RANGE_CHECK(s,a,b,c) { if((((NvS32)(a))<(NvS32)(b))||(((NvS32)(a))>(NvS32)(c))) { DSC_Print("%s (=%u) needs to be between %u and %u",s,a,b,c); return (NVT_STATUS_ERR);} } @@ -171,9 +170,21 @@ NvU32 flatness_det_thresh; } DSC_OUTPUT_PARAMS; -/* ------------------------ Global Variables ------------------------------- */ +// +// Opaque scratch space is passed by client for DSC calculation usage. +// Use an internal struct to cast the input buffer +// into in/out params for DSC PPS calculation functions to work with +// +typedef struct _DSC_GENERATE_PPS_WORKAREA +{ + DSC_INPUT_PARAMS in; + DSC_OUTPUT_PARAMS out; +} DSC_GENERATE_PPS_WORKAREA; + +// Compile time check to ensure Opaque workarea buffer size always covers required work area. +ct_assert(sizeof(DSC_GENERATE_PPS_OPAQUE_WORKAREA) >= sizeof(DSC_GENERATE_PPS_WORKAREA)); -DSC_CALLBACK callbacks; +/* ------------------------ Global Variables ------------------------------- */ static const NvU8 minqp444_8b[15][37]={ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0} @@ -396,8 +407,6 @@ /* ------------------------ Static Variables ------------------------------- */ /* ------------------------ Private Functions Prototype--------------------- */ -static void * DSC_Malloc(NvLength size); -static void DSC_Free(void * ptr); static NvU32 DSC_GetHigherSliceCount ( @@ -1586,19 +1595,11 @@ DSC_PpsDataGen ( const DSC_INPUT_PARAMS *in, - NvU32 out[DSC_MAX_PPS_SIZE_DWORD] + DSC_OUTPUT_PARAMS *pPpsOut, + NvU32 out[DSC_MAX_PPS_SIZE_DWORD] ) { NVT_STATUS ret; - DSC_OUTPUT_PARAMS *pPpsOut; - - pPpsOut = (DSC_OUTPUT_PARAMS *)DSC_Malloc(sizeof(DSC_OUTPUT_PARAMS)); - if (pPpsOut == NULL) - { - DSC_Print("ERROR - Memory allocation error."); - ret = NVT_STATUS_NO_MEMORY; - goto done; - } NVMISC_MEMSET(pPpsOut, 0, sizeof(DSC_OUTPUT_PARAMS)); ret = DSC_PpsCalc(in, pPpsOut); @@ -1612,45 +1613,10 @@ /* fall through */ done: - DSC_Free(pPpsOut); - return ret; } /* - * @brief Allocates memory for requested size - * - * @param[in] size Size to be allocated - * - * @returns Pointer to allocated memory - */ -static void * -DSC_Malloc(NvLength size) -{ -#if defined(DSC_CALLBACK_MODIFIED) - return (callbacks.dscMalloc)(callbacks.clientHandle, size); -#else - return (callbacks.dscMalloc)(size); -#endif // DSC_CALLBACK_MODIFIED -} - -/* - * @brief Frees dynamically allocated memory - * - * @param[in] ptr Pointer to a memory to be deallocated - * - */ -static void -DSC_Free(void * ptr) -{ -#if defined(DSC_CALLBACK_MODIFIED) - (callbacks.dscFree)(callbacks.clientHandle, ptr); -#else - (callbacks.dscFree)(ptr); -#endif // DSC_CALLBACK_MODIFIED -} - -/* * @brief Validate input parameter we got from caller of this function * * @param[in] pDscInfo Includes Sink and GPU DSC capabilities @@ -1992,19 +1958,26 @@ const WAR_DATA *pWARData, NvU64 availableBandwidthBitsPerSecond, NvU32 pps[DSC_MAX_PPS_SIZE_DWORD], - NvU32 *pBitsPerPixelX16 + NvU32 *pBitsPerPixelX16, + DSC_GENERATE_PPS_OPAQUE_WORKAREA *pOpaqueWorkarea ) { - DSC_INPUT_PARAMS *in = NULL; + DSC_INPUT_PARAMS *in = NULL; + DSC_OUTPUT_PARAMS *out = NULL; + DSC_GENERATE_PPS_WORKAREA *pWorkarea = NULL; NVT_STATUS ret = NVT_STATUS_ERR; - if ((!pDscInfo) || (!pModesetInfo) || (!pBitsPerPixelX16)) + if ((!pDscInfo) || (!pModesetInfo) || (!pBitsPerPixelX16) || (!pOpaqueWorkarea)) { DSC_Print("ERROR - Invalid parameter."); ret = NVT_STATUS_INVALID_PARAMETER; goto done; } + pWorkarea = (DSC_GENERATE_PPS_WORKAREA*)(pOpaqueWorkarea); + in = &pWorkarea->in; + out = &pWorkarea->out; + ret = _validateInput(pDscInfo, pModesetInfo, pWARData, availableBandwidthBitsPerSecond); if (ret != NVT_STATUS_SUCCESS) { @@ -2013,14 +1986,6 @@ goto done; } - in = (DSC_INPUT_PARAMS *)DSC_Malloc(sizeof(DSC_INPUT_PARAMS)); - if (in == NULL) - { - DSC_Print("ERROR - Memory allocation error."); - ret = NVT_STATUS_NO_MEMORY; - goto done; - } - NVMISC_MEMSET(in, 0, sizeof(DSC_INPUT_PARAMS)); in->bits_per_component = pModesetInfo->bitsPerComponent; @@ -2277,42 +2242,11 @@ } } - ret = DSC_PpsDataGen(in, pps); + ret = DSC_PpsDataGen(in, out, pps); *pBitsPerPixelX16 = in->bits_per_pixel; /* fall through */ done: - DSC_Free(in); - return ret; } - -/* - * @brief Initializes callbacks for print and assert - * - * @param[in] callback DSC callbacks - * - * @returns NVT_STATUS_SUCCESS if successful; - * NVT_STATUS_ERR if unsuccessful; - */ -NVT_STATUS DSC_InitializeCallback(DSC_CALLBACK callback) -{ - // if callbacks are initialized already, return nothing to do - if (callbacks.dscMalloc && callbacks.dscFree) - { - return NVT_STATUS_SUCCESS; - } - -#if defined(DSC_CALLBACK_MODIFIED) - callbacks.clientHandle = callback.clientHandle; -#endif // DSC_CALLBACK_MODIFIED - callbacks.dscPrint = NULL; - callbacks.dscMalloc = callback.dscMalloc; - callbacks.dscFree = callback.dscFree; -#if defined (DEBUG) - callbacks.dscPrint = callback.dscPrint; -#endif - - return NVT_STATUS_SUCCESS; -} diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/common/modeset/timing/nvt_dsc_pps.h nvidia-open-gpu-kernel-modules-535.161.08/src/common/modeset/timing/nvt_dsc_pps.h --- nvidia-open-gpu-kernel-modules-525.147.05/src/common/modeset/timing/nvt_dsc_pps.h 2023-10-25 20:22:28.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/common/modeset/timing/nvt_dsc_pps.h 2024-03-05 22:12:04.000000000 +0000 @@ -43,27 +43,6 @@ /* ------------------------ Datatypes -------------------------------------- */ -#define DSC_CALLBACK_MODIFIED 1 - -#if defined(DSC_CALLBACK_MODIFIED) -typedef struct -{ - // DSC - Callbacks - const void* clientHandle; // ClientHandle is only used when calling into HDMI lib's mallocCb/freeCb - void (*dscPrint) (const char* fmtstring, ...); - void *(*dscMalloc)(const void *clientHandle, NvLength size); - void (*dscFree) (const void *clientHandle, void * ptr); -} DSC_CALLBACK; -#else -typedef struct -{ - // DSC - Callbacks - void (*dscPrint) (const char* fmtstring, ...); - void *(*dscMalloc)(NvLength size); - void (*dscFree) (void * ptr); -} DSC_CALLBACK; -#endif // DSC_CALLBACK_MODIFIED - typedef struct { NvU32 versionMajor; @@ -278,6 +257,16 @@ }dpData; } WAR_DATA; +// +// DSC PPS calculations need large scratch buffer to work with, which can be too +// big for some platforms. These buffers need to be allocated on heap rather +// than local stack variable. Clients are expected to pre-allocate +// this buffer and pass it in to DSC PPS interface +// +typedef struct { + NvU8 data[512U]; // an upper bound of total size of DSC_IN/OUTPUT_PARAMS +} DSC_GENERATE_PPS_OPAQUE_WORKAREA; + /* * Windows testbed compiles are done with warnings as errors * with the maximum warning level. Here we turn off some @@ -293,16 +282,6 @@ extern "C" { #endif /* - * @brief Initializes callbacks for print and assert - * - * @param[in] callback DSC callbacks - * - * @returns NVT_STATUS_SUCCESS if successful; - * NVT_STATUS_ERR if unsuccessful; - */ -NVT_STATUS DSC_InitializeCallback(DSC_CALLBACK callback); - -/* * @brief Calculate PPS parameters based on passed down Sink, * GPU capability and modeset info * @@ -323,7 +302,8 @@ const WAR_DATA *pWARData, NvU64 availableBandwidthBitsPerSecond, NvU32 pps[DSC_MAX_PPS_SIZE_DWORD], - NvU32 *pBitsPerPixelX16); + NvU32 *pBitsPerPixelX16, + DSC_GENERATE_PPS_OPAQUE_WORKAREA *pOpaqueWorkarea); #ifdef __cplusplus } diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/common/modeset/timing/nvt_edid.c nvidia-open-gpu-kernel-modules-535.161.08/src/common/modeset/timing/nvt_edid.c --- nvidia-open-gpu-kernel-modules-525.147.05/src/common/modeset/timing/nvt_edid.c 2023-10-25 20:22:28.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/common/modeset/timing/nvt_edid.c 2024-03-05 22:12:04.000000000 +0000 @@ -1,6 +1,6 @@ //***************************************************************************** // -// SPDX-FileCopyrightText: Copyright (c) 2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. +// SPDX-FileCopyrightText: Copyright (c) 2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. // SPDX-License-Identifier: MIT // // Permission is hereby granted, free of charge, to any person obtaining a @@ -1079,10 +1079,17 @@ // add the detailed timings in 18-byte long display descriptor parse861ExtDetailedTiming(pExt, p861Info->basic_caps, pInfo); + if (p861Info->revision >= NVT_CTA861_REV_H) + { + if (p861Info->total_did_type7db != 0) parseCta861DIDType7VideoTimingDataBlock(p861Info, pInfo); + if (p861Info->total_did_type8db != 0) parseCta861DIDType8VideoTimingDataBlock(p861Info, pInfo); + if (p861Info->total_did_type10db != 0) parseCta861DIDType10VideoTimingDataBlock(p861Info, pInfo); + } + // CEA861-F at 7.5.12 section about VFPDB block. - if (p861Info->revision >= NVT_CEA861_REV_F && p861Info->total_vfpdb != 0) + if (p861Info->revision >= NVT_CEA861_REV_F && (p861Info->total_svr != 0 || p861Info->valid.NVRDB == 1)) { - parse861bShortPreferredTiming(p861Info, pInfo, FROM_CTA861_EXTENSION); + parseCta861NativeOrPreferredTiming(p861Info, pInfo, FROM_CTA861_EXTENSION); } k++; @@ -1170,6 +1177,27 @@ // find out the total established timings - base EDID and then the LDDs parseEdidEstablishedTiming(pInfo); + // remove the T8VTDB timing if it co-existed in standard or established timings + if (pInfo->ext861.revision >= NVT_CTA861_REV_H && pInfo->ext861.total_did_type8db != 0 && pInfo->total_timings > 1) + { + for (i = 0; i < pInfo->total_timings; i++) + { + if (NVT_GET_TIMING_STATUS_TYPE(pInfo->timing[i].etc.status) == NVT_TYPE_CTA861_DID_T8) + { + if (isMatchedStandardTiming(pInfo, &pInfo->timing[i]) || isMatchedEstablishedTiming(pInfo, &pInfo->timing[i])) + { + for (j = i; j < pInfo->total_timings - 1; j++) + { + // remove the entry by moving the next entry up. + pInfo->timing[j] = pInfo->timing[j+1]; + } + NVMISC_MEMSET(&pInfo->timing[pInfo->total_timings-1], 0, sizeof(NVT_TIMING)); + pInfo->total_timings--; i--; + } + } + } + } + getEdidHDM1_4bVsdbTiming(pInfo); // Assert if no timings were found (due to a bad EDID) or if we mistakenly @@ -1281,7 +1309,38 @@ } } } +} + +CODE_SEGMENT(PAGE_DD_CODE) +NvBool isMatchedStandardTiming(NVT_EDID_INFO *pInfo, NVT_TIMING *pT) +{ + NvU32 j; + for (j = 0; j < pInfo->total_timings; j++) + { + if (NVT_GET_TIMING_STATUS_TYPE(pInfo->timing[j].etc.status) == NVT_TYPE_EDID_STD && + NvTiming_IsTimingRelaxedEqual(&pInfo->timing[j], pT)) + { + return NV_TRUE; + } + } + return NV_FALSE; +} + +CODE_SEGMENT(PAGE_DD_CODE) +NvBool isMatchedEstablishedTiming(NVT_EDID_INFO *pInfo, NVT_TIMING *pT) +{ + NvU32 j; + + for (j = 0; j < pInfo->total_timings; j++) + { + if (NVT_GET_TIMING_STATUS_TYPE(pInfo->timing[j].etc.status) == NVT_TYPE_EDID_EST && + NvTiming_IsTimingRelaxedEqual(&pInfo->timing[j], pT)) + { + return NV_TRUE; + } + } + return NV_FALSE; } CODE_SEGMENT(PAGE_DD_CODE) @@ -1385,7 +1444,7 @@ NVT_STATUS NvTiming_GetEdidTimingEx(NvU32 width, NvU32 height, NvU32 rr, NvU32 flag, NVT_EDID_INFO *pEdidInfo, NVT_TIMING *pT, NvU32 rrx1k) { NvU32 i, j; - NvU32 preferred_cea, preferred_displayid_dtd, preferred_dtd1, dtd1, map0, map1, map2, map3, map4, ceaIndex, max, cvt; + NvU32 native_cta, preferred_cta, preferred_displayid_dtd, preferred_dtd1, dtd1, map0, map1, map2, map3, map4, ceaIndex, max, cvt; NVT_TIMING *pEdidTiming; NVT_EDID_DD_RANGE_CVT *pCVT = NULL; NVT_TIMING cvtTiming; @@ -1401,7 +1460,9 @@ // the timing mapping index : // - // preferred_cea - the "prefer SVD" in CEA-861-F (i.e. A Sink that prefers a Video Format that is not listed as an SVD in Video Data Block, but instead listed in YCBCR 4:2:0 VDB) + // native_cta - the "native resoluiotn of the sink" in the CTA861.6 A Source shall override any other native video resolution indicators + // if the Source supports NVRDB and the NVRDB was found in the E-EDID + // preferred_cta - the "prefer SVD" in CTA-861-F (i.e. A Sink that prefers a Video Format that is not listed as an SVD in Video Data Block, but instead listed in YCBCR 4:2:0 VDB) // preferred_displayid_dtd - the "prefer detailed timing of DispalyID" extension // preferred_dtd1 - the first deatiled timing and PTM flag is enable // dtd1 - the first detailed timing @@ -1411,7 +1472,7 @@ // map3 - the "closest" match to the panel's native timing (i.e. the first DTD timing or the short 861B/C/D timings with "native" flag). // map4 - the "closest" match with the same refresh rate // max - the timing with the max visible area - preferred_cea = preferred_displayid_dtd = preferred_dtd1 = dtd1 = map0 = map1 = map2 = map3 = map4 = ceaIndex = pEdidInfo->total_timings; + native_cta = preferred_cta = preferred_displayid_dtd = preferred_dtd1 = dtd1 = map0 = map1 = map2 = map3 = map4 = ceaIndex = pEdidInfo->total_timings; max = cvt = 0; for (i = 0; i < pEdidInfo->total_timings; i++) { @@ -1435,7 +1496,7 @@ map0 = i; } - if ( (NVT_PREFERRED_TIMING_IS_CEA(pEdidTiming[i].etc.flag)) || + if ( (NVT_PREFERRED_TIMING_IS_CTA(pEdidTiming[i].etc.flag)) || ((0 == (flag & NVT_FLAG_EDID_861_ST)) && NVT_PREFERRED_TIMING_IS_DTD1(pEdidTiming[i].etc.flag, pEdidTiming[i].etc.status)) || (NVT_PREFERRED_TIMING_IS_DISPLAYID(pEdidTiming[i].etc.flag)) || (NVT_IS_NATIVE_TIMING(pEdidTiming[i].etc.status))) @@ -1474,10 +1535,14 @@ } // find out the preferred timing just in case of cea_vfpdb is existed - if (preferred_cea == pEdidInfo->total_timings && - NVT_PREFERRED_TIMING_IS_CEA(pEdidTiming[i].etc.flag)) + if (native_cta == pEdidInfo->total_timings && NVT_NATIVE_TIMING_IS_CTA(pEdidTiming[i].etc.flag)) { - preferred_cea = i; + native_cta = i; + } + + if (preferred_cta == pEdidInfo->total_timings && NVT_PREFERRED_TIMING_IS_CTA(pEdidTiming[i].etc.flag)) + { + preferred_cta = i; } // find out the preferred timing just in case @@ -1736,7 +1801,8 @@ if (flag & NVT_FLAG_NV_PREFERRED_TIMING) { *pT = (preferred_displayid_dtd != pEdidInfo->total_timings) ? pEdidTiming[preferred_displayid_dtd] : - (preferred_cea != pEdidInfo->total_timings) ? pEdidTiming[preferred_cea] : + (native_cta != pEdidInfo->total_timings) ? pEdidTiming[native_cta] : + (preferred_cta != pEdidInfo->total_timings) ? pEdidTiming[preferred_cta] : (preferred_dtd1 != pEdidInfo->total_timings) ? pEdidTiming[preferred_dtd1] : pEdidTiming[dtd1]; // what if DTD1 itself is filtered out, in such case dtd1 index points to an invalid timing[]? @@ -1993,7 +2059,7 @@ { ret |= NVT_EDID_VALIDATION_ERR_MASK(NVT_EDID_VALIDATION_ERR_VERSION); return ret; - } + } // check block 0 checksum value if (!isChecksumValid(pEdid)) @@ -2169,9 +2235,8 @@ NvBool bAllZero = NV_TRUE; NvU32 ret = 0; - // check the EDID base size to avoid accessing beyond the EDID buffer, do not proceed with - // further validation. - if (length < sizeof(EDIDV1STRUC)) + // check the EDID base size to avoid accessing beyond the EDID buffer + if (length < sizeof(EDIDV1STRUC) || (length > sizeof(EDIDV1STRUC) && (length % sizeof(EDIDV1STRUC) != 0))) ret |= NVT_EDID_VALIDATION_ERR_MASK(NVT_EDID_VALIDATION_ERR_SIZE); // check the EDID version and signature @@ -2254,6 +2319,11 @@ ret |= NVT_EDID_VALIDATION_ERR_MASK(NVT_EDID_VALIDATION_ERR_EXTENSION_COUNT); } + // we shall not trust any extension blocks with wrong input EDID size + if (NVT_IS_EDID_VALIDATION_FLAGS(ret, NVT_EDID_VALIDATION_ERR_SIZE) || + NVT_IS_EDID_VALIDATION_FLAGS(ret, NVT_EDID_VALIDATION_ERR_EXTENSION_COUNT)) + return ret; + // validate extension blocks for (j = 1; j <= p->bExtensionFlag; j++) { @@ -2304,7 +2374,7 @@ } else if (ctaBlockTag == NVT_CEA861_TAG_EXTENDED_FLAG) { - if (*pData_collection == NVT_CEA861_EXT_TAG_HF_EEODB) + if (*pData_collection == NVT_CTA861_EXT_TAG_HF_EEODB) { if ((p->bVersionNumber != 0x01) || (p->bRevisionNumber != 0x03)) { @@ -2325,7 +2395,7 @@ else pData_collection += ctaPayload; } - else if (ctaBlockTag == NVT_CEA861_TAG_RSVD || ctaBlockTag == NVT_CEA861_TAG_RSVD1) + else if (ctaBlockTag == NVT_CEA861_TAG_RSVD) { ret |= NVT_EDID_VALIDATION_ERR_MASK(NVT_EDID_VALIDATION_ERR_EXT_CTA_TAG); pData_collection += ctaPayload; @@ -2415,7 +2485,7 @@ } // compare the remain 0 value are correct or not before meet checksum byte - for (i = 0; i <= (NvU32)(&pDisplayid->data[NVT_DID_MAX_EXT_PAYLOAD-1] - pData_collection); i++) + for (i = 0; i < (NvU32)(&pDisplayid->data[NVT_DID_MAX_EXT_PAYLOAD-1] - pData_collection); i++) { if (pData_collection[i] != 0) { @@ -2465,7 +2535,7 @@ } // compare the remain 0 value are correct or not before meet checksum byte - for (i = 0; i <= (NvU32)(&pDisplayid->data[NVT_DID_MAX_EXT_PAYLOAD-1] - pData_collection); i++) + for (i = 0; i < (NvU32)(&pDisplayid->data[NVT_DID_MAX_EXT_PAYLOAD-1] - pData_collection); i++) { if (pData_collection[i] != 0) { diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/common/modeset/timing/nvt_edidext_861.c nvidia-open-gpu-kernel-modules-535.161.08/src/common/modeset/timing/nvt_edidext_861.c --- nvidia-open-gpu-kernel-modules-525.147.05/src/common/modeset/timing/nvt_edidext_861.c 2023-10-25 20:22:28.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/common/modeset/timing/nvt_edidext_861.c 2024-03-05 22:12:04.000000000 +0000 @@ -1,6 +1,6 @@ //***************************************************************************** // -// SPDX-FileCopyrightText: Copyright (c) 2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. +// SPDX-FileCopyrightText: Copyright (c) 2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. // SPDX-License-Identifier: MIT // // Permission is hereby granted, free of charge, to any person obtaining a @@ -371,10 +371,36 @@ {20, NVT_HDMI_3D_SUPPORTED_SIDEBYSIDEHALF_MASK, NVT_HDMI_VS_BYTE_OPT1_HDMI_3DEX_SSH} // 1920 x 1080i @ 50 Hz }; static NvU32 MAX_HDMI_MANDATORY_3D_FORMAT = sizeof(HDMI_MANDATORY_3D_FORMATS) / sizeof(HDMI_MANDATORY_3D_FORMATS[0]); - static const NVT_VIDEO_INFOFRAME DEFAULT_VIDEO_INFOFRAME = {/*header*/2,2,13, /*byte1*/0, /*byte2*/0x8, /*byte3*/0, /*byte4*/0, /*byte5*/0, /*byte6~13*/0,0,0,0,0,0,0,0}; static const NVT_AUDIO_INFOFRAME DEFAULT_AUDIO_INFOFRAME = {/*header*/4,1,10, /*byte1*/0, /*byte2*/0, /*byte3*/0, /*byte*/0, /*byte5*/0, /*byte6~10*/0,0,0,0,0}; -static const NVT_VENDOR_SPECIFIC_INFOFRAME DEFAULT_VENDOR_SPECIFIC_INFOFRAME = {/*header*/{0x01,1,6}, {/*byte1*/3, /*byte2*/0x0c, /*byte3*/0, /*byte4*/0, /*byte5*/0, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0}}}; + +CODE_SEGMENT(PAGE_DD_CODE) +static NvU8 +getExistedCTATimingSeqNumber( + NVT_EDID_INFO *pInfo, + enum NVT_TIMING_TYPE timingType) +{ + NvU8 count = 0; + NvU8 i = 0; + + switch (timingType) + { + case NVT_TYPE_CTA861_DID_T7: + case NVT_TYPE_CTA861_DID_T8: + case NVT_TYPE_CTA861_DID_T10: + break; + default: + return count; + } + + for (i = 0; i< pInfo->total_timings; i++) + { + if (NVT_GET_TIMING_STATUS_TYPE(pInfo->timing[i].etc.status) == timingType) + ++count; + } + + return count; +} // parse the 861 detailed timing info CODE_SEGMENT(PAGE_DD_CODE) @@ -397,7 +423,7 @@ // Get all detailed timings in CEA ext block pDTD = (DETAILEDTIMINGDESCRIPTOR *)&pEdidExt[pEIA861->offset]; - while((NvU8 *)pDTD + sizeof(DETAILEDTIMINGDESCRIPTOR) < (pEdidExt + sizeof(EDIDV1STRUC) - 1) && + while((NvU8 *)pDTD + sizeof(DETAILEDTIMINGDESCRIPTOR) < (pEdidExt + sizeof(EDIDV1STRUC)) && pDTD->wDTPixelClock != 0) { NVMISC_MEMSET(&newTiming, 0, sizeof(newTiming)); @@ -687,25 +713,28 @@ } } -// Currently, we only focus on the particular application in CEA861-F spec described +// Currently, the SVR both used in the NVRDB and VFPDB. // "One particular application is a Sink that prefers a Video Format that is not listed as an SVD in a VDB // but instead listed in a YCBCR 4:2:0 Video Data Block" CODE_SEGMENT(PAGE_DD_CODE) -void parse861bShortPreferredTiming(NVT_EDID_CEA861_INFO *pExt861, - void *pRawInfo, - NVT_CTA861_ORIGIN flag) +void parseCta861NativeOrPreferredTiming(NVT_EDID_CEA861_INFO *pExt861, + void *pRawInfo, + NVT_CTA861_ORIGIN flag) { NvU32 isMatch,i,j = 0; NVT_TIMING preferTiming; NVT_EDID_INFO *pInfo = NULL; NVT_DISPLAYID_2_0_INFO *pDisplayID20 = NULL; + NvU8 nativeSvr = 0; NvU8 *pSvr = pExt861->svr_vfpdb; - NvU8 totalSvr = pExt861->total_vfpdb; + NvU8 totalSvr = pExt861->total_svr; NvU8 kth = 0; NvU8 extKth = 0; NvU8 DTDCount = 0; NvU8 extDTDCount = 0; + NvU8 DIDT7Count = 0; + NvU8 DIDT10Count = 0; if (flag == FROM_CTA861_EXTENSION || flag == FROM_DISPLAYID_13_DATA_BLOCK) { @@ -720,32 +749,41 @@ return; } - // finding all the DTD + // finding all the DTD in Base 0 or CTA861 if (flag == FROM_CTA861_EXTENSION) { + // get the NVRDB, from the spec this native resolution has more high priority than others + if (pExt861->valid.NVRDB == 1) + { + nativeSvr = pExt861->native_video_resolution_db.native_svr; + totalSvr = 1; + } + for (j = 0; j < pInfo->total_timings; j++) { - if (NVT_IS_DTD(pInfo->timing[j].etc.status)) - { - DTDCount++; - } - else if (NVT_IS_EXT_DTD(pInfo->timing[j].etc.status)) - { - extDTDCount++; - } + if (NVT_IS_DTD(pInfo->timing[j].etc.status)) DTDCount++; + else if (NVT_IS_EXT_DTD(pInfo->timing[j].etc.status)) extDTDCount++; + else if (NVT_IS_CTA861_DID_T7(pInfo->timing[j].etc.status)) DIDT7Count++; + else if (NVT_IS_CTA861_DID_T10(pInfo->timing[j].etc.status)) DIDT10Count++; } } - // TODO : this only handle single SVR right now + // this only handle single SVR right now for (i = 0; i < totalSvr; i++) { - NvU8 svr = pSvr[i]; + NvU8 svr = 0; NvU8 vic = 0; - if (svr == 0 || svr == 128 || (svr >= 161 && svr <= 192) || svr == 255) - continue; + if (pExt861->valid.NVRDB == 1) + svr = nativeSvr; + else + svr = pSvr[i]; + + // Reserved + if (svr == 0 || svr == 128 || (svr >= 176 && svr <= 192) || svr == 255) + continue; - // Kth 18bytes DTD in the EDID + // Interpret as the Kth 18-byte DTD, where K = SVR - 128 (for K = 1 to 16) in both base0 and CTA block if (svr >= 129 && svr <= 144) { kth = svr - 128; @@ -756,39 +794,81 @@ { if (kth <= DTDCount) { - if (NVT_IS_DTDn(pInfo->timing[j].etc.status, kth)) - { - pInfo->timing[j].etc.flag |= NVT_FLAG_CEA_PREFERRED_TIMING; + if (NVT_IS_DTDn(pInfo->timing[j].etc.status, kth)) break; - } } else { extKth = kth - DTDCount; - if (NVT_IS_EXT_DTDn(pInfo->timing[j].etc.status, extKth)) - { - pInfo->timing[j].etc.flag |= NVT_FLAG_CEA_PREFERRED_TIMING; + if (NVT_IS_EXT_DTDn(pInfo->timing[j].etc.status, extKth)) break; - } } } + + if (pExt861->valid.NVRDB == 1) + pInfo->timing[j].etc.flag |= NVT_FLAG_CTA_NATIVE_TIMING; + else + pInfo->timing[j].etc.flag |= NVT_FLAG_CTA_PREFERRED_TIMING; } } else if (svr >= 145 && svr <= 160) { - // TODO : Interpret as the Nth 20-byte DTD or 6- or 7-byte CVT-based descriptor, - // where N = SVR – 144 (for N = 1 to 16) + // Interpret as the Nth 20-byte DTD or 6- or 7-byte CVT-based descriptor + // where N = SVR – 144 (for N = 1 to 16) + kth = svr - 144; + + if (flag == FROM_CTA861_EXTENSION) + { + for (j = 0; j < pInfo->total_timings; j++) + { + if (kth <= DIDT7Count) // pick the Nth 20-byte first + { + if (NVT_IS_CTA861_DID_T7n(pInfo->timing[j].etc.status, kth)) + break; + } + else + { + extKth = kth - DIDT7Count; // pick the T10 CVT-based timing then + if (NVT_IS_CTA861_DID_T10n(pInfo->timing[j].etc.status, extKth)) + break; + } + } + + if (pExt861->valid.NVRDB == 1) + pInfo->timing[j].etc.flag |= NVT_FLAG_CTA_NATIVE_TIMING; + else + pInfo->timing[j].etc.flag |= NVT_FLAG_CTA_PREFERRED_TIMING; + } + } + else if (svr >= 161 && svr <= 175) + { + // Interpret as the video format indicated by the first VFD of the first VFDB with Frame Rates of Rate Index N + // where N = SVR - 160 (for N = 1 to 15) break; } else if (svr == 254) { - // TODO : Interpret as the timing format indicated by the first code of the first T8VTDB + // Interpret as the timing format indicated by the first code of the first T8VTDB + if (flag == FROM_CTA861_EXTENSION) + { + for (j = 0; j < pInfo->total_timings; j++) + { + if (NVT_IS_CTA861_DID_T8_1(pInfo->timing[j].etc.status)) + { + if (pExt861->valid.NVRDB == 1) + pInfo->timing[j].etc.flag |= NVT_FLAG_CTA_NATIVE_TIMING; + else + pInfo->timing[j].etc.flag |= NVT_FLAG_CTA_PREFERRED_TIMING; + break; + } + } + } break; } else // assign corresponding CEA format's timing from pre-defined CE timing table, EIA861B { // ( SVR >= 1 and SVR <= 127) and (SVR >= 193 and SVR <= 253) - vic = NVT_GET_CTA_8BIT_VIC(svr); + vic = NVT_GET_CTA_8BIT_VIC(svr); preferTiming = EIA861B[vic-1]; if (flag == FROM_CTA861_EXTENSION || flag == FROM_DISPLAYID_13_DATA_BLOCK) @@ -798,19 +878,25 @@ isMatch = NvTiming_IsTimingExactEqual(&pInfo->timing[j], &preferTiming); if (isMatch && (NVT_GET_TIMING_STATUS_TYPE(pInfo->timing[j].etc.status) == NVT_TYPE_EDID_861ST)) { - pInfo->timing[j].etc.flag |= NVT_FLAG_CEA_PREFERRED_TIMING; + if (pExt861->valid.NVRDB == 1) + pInfo->timing[j].etc.flag |= NVT_FLAG_CTA_NATIVE_TIMING; + else + pInfo->timing[j].etc.flag |= NVT_FLAG_CTA_PREFERRED_TIMING; break; } } } else if (flag == FROM_DISPLAYID_20_DATA_BLOCK) - { + { for (j = 0; j < pDisplayID20->total_timings; j++) { isMatch = NvTiming_IsTimingExactEqual(&pDisplayID20->timing[j], &preferTiming); if (isMatch && (NVT_GET_TIMING_STATUS_TYPE(pDisplayID20->timing[j].etc.status) == NVT_TYPE_EDID_861ST)) { - pDisplayID20->timing[j].etc.flag |= NVT_FLAG_CEA_PREFERRED_TIMING | NVT_FLAG_DISPLAYID_2_0_TIMING; + if (pExt861->valid.NVRDB == 1) + pDisplayID20->timing[j].etc.flag |= NVT_FLAG_CTA_NATIVE_TIMING | NVT_FLAG_DISPLAYID_2_0_TIMING; + else + pDisplayID20->timing[j].etc.flag |= NVT_FLAG_CTA_PREFERRED_TIMING | NVT_FLAG_DISPLAYID_2_0_TIMING; break; } } @@ -1294,6 +1380,9 @@ NvU32 vendor_index = 0; NvU32 yuv420vdb_index = 0; NvU32 yuv420cmdb_index = 0; + NvU8 didT7_index = 0; + NvU8 didT8_index = 0; + NvU8 didT10_index = 0; NvU8 svr_index = 0; NvU32 ieee_id = 0; NvU32 tag, ext_tag, payload; @@ -1308,7 +1397,7 @@ /*don't allow data colleciton totally size larger than [127 - 5 (tag, revision, offset, describing native video format, checksum)]*/ if ((i + payload > size) || (i + payload > 122)) { - return NVT_STATUS_ERR; + break; } // move the pointer to the payload section or extended Tag Code i++; @@ -1323,7 +1412,6 @@ case NVT_CEA861_TAG_SPEAKER_ALLOC: case NVT_CEA861_TAG_VESA_DTC: case NVT_CEA861_TAG_RSVD: - case NVT_CEA861_TAG_RSVD1: break; case NVT_CEA861_TAG_VENDOR: if (payload < 3) return NVT_STATUS_ERR; @@ -1340,7 +1428,36 @@ else if (ext_tag == NVT_CEA861_EXT_TAG_HDR_STATIC_METADATA && payload < 3) return NVT_STATUS_ERR; else if (ext_tag == NVT_CEA861_EXT_TAG_VENDOR_SPECIFIC_VIDEO && payload < 4) return NVT_STATUS_ERR; else if (ext_tag == NVT_CTA861_EXT_TAG_SCDB && payload < 7) return NVT_STATUS_ERR; - else if (ext_tag == NVT_CEA861_EXT_TAG_HF_EEODB && payload != 2) return NVT_STATUS_ERR; + else if (ext_tag == NVT_CTA861_EXT_TAG_HF_EEODB && payload != 2) return NVT_STATUS_ERR; + else if (ext_tag == NVT_CTA861_EXT_TAG_DID_TYPE_VII && payload <= 2) return NVT_STATUS_ERR; + else if (ext_tag == NVT_CTA861_EXT_TAG_DID_TYPE_VIII && payload <= 2) return NVT_STATUS_ERR; + else if (ext_tag == NVT_CTA861_EXT_TAG_DID_TYPE_X && payload <= 2) return NVT_STATUS_ERR; + else if (ext_tag == NVT_CTA861_EXT_TAG_NATIVE_VIDEO_RESOLUTION) + { + if (payload != 2 && payload != 3 && payload != 7) return NVT_STATUS_ERR; + } + + if (payload > 2) + { + if (ext_tag == NVT_CTA861_EXT_TAG_DID_TYPE_VII) + { + if ((payload-2) != 20) return NVT_STATUS_ERR; // only support 20-bytes + if ((p[i+1] & 0x7) != 2) return NVT_STATUS_ERR; // Block Revision shall be 2 + if ((p[i+1] & 0x70) >> 4 != 0) return NVT_STATUS_ERR; // Not allow extra byte + } + else if (ext_tag == NVT_CTA861_EXT_TAG_DID_TYPE_VIII) + { + if ((payload-2) < 1) return NVT_STATUS_ERR; // minimum one code supported + if ((p[i+1] & 0x7) != 1) return NVT_STATUS_ERR; // Block Revision shall be 1 + if ((p[i+1] & 0xC0) >> 6 != 0) return NVT_STATUS_ERR; // Not allow others than DMT Timing + } + else if (ext_tag == NVT_CTA861_EXT_TAG_DID_TYPE_X) + { + if ((p[i+1] & 0x7) != 0) return NVT_STATUS_ERR; // Block Revision shall be 0 + if (((p[i+1] & 0x70) >> 4 == 0) && (payload-2) % 6) return NVT_STATUS_ERR; // supported 6-bytes descriptors + if (((p[i+1] & 0x70) >> 4 == 1) && (payload-2) % 7) return NVT_STATUS_ERR; // supported 7-bytes descriptors + } + } } break; default: @@ -1453,7 +1570,7 @@ else if (ext_tag == NVT_CEA861_EXT_TAG_VIDEO_FORMAT_PREFERENCE && payload >= 2) { // when present, indicates the order of preference for selected Video Formats listed as DTDs and/or SVDs throughout Block 0 and the CTA Extensions of the - // order of SVD preferred modes shall take precedence over preferred modes defined elsewhere in the EDID/CEA861 blocks + // order of SVD preferred modes shall take precedence over preferred modes defined elsewhere in the EDID/CEA861 blocks // exclude the extended tag i++; payload--; @@ -1462,7 +1579,7 @@ { p861info->svr_vfpdb[svr_index] = p[i]; } - p861info->total_vfpdb = svr_index; + p861info->total_svr = svr_index; } else if (ext_tag == NVT_CEA861_EXT_TAG_YCBCR420_VIDEO && payload >= 2) { @@ -1560,6 +1677,100 @@ i += payload; } } + else if (ext_tag == NVT_CTA861_EXT_TAG_NATIVE_VIDEO_RESOLUTION) + { + if (payload != 2 && payload != 3 && payload != 7) break; + + i++; payload--; + p861info->native_video_resolution_db.native_svr = p[i]; + p861info->valid.NVRDB = 1; + + i++; payload--; + if (payload != 0) + { + p861info->native_video_resolution_db.option.img_size = p[i] & 0x01; + p861info->native_video_resolution_db.option.sz_prec = (p[i] & 0x80) >> 7; + + i++; payload--; + if (p861info->native_video_resolution_db.option.img_size == 1) + { + for (j = 0; j< payload; j++, i++) + { + p861info->native_video_resolution_db.image_size[j] = p[i]; + } + } + } + } + else if (ext_tag == NVT_CTA861_EXT_TAG_DID_TYPE_VII) + { + if( payload != 22) break; + + i++; payload--; + p861info->did_type7_data_block[didT7_index].version.revision = p[i] & 0x07; + p861info->did_type7_data_block[didT7_index].version.dsc_pt = (p[i] & 0x08) >> 3; + p861info->did_type7_data_block[didT7_index].version.t7_m = (p[i] & 0x70) >> 4; + + //do not consider Byte 3 + i++; payload--; + + p861info->did_type7_data_block[didT7_index].total_descriptors = + (NvU8)(payload / (NVT_CTA861_DID_TYPE7_DESCRIPTORS_LENGTH + p861info->did_type7_data_block[didT7_index].version.t7_m)); + + for (j = 0; j < payload; j++, i++) + { + p861info->did_type7_data_block[didT7_index].payload[j] = p[i]; + } + // next type7 data block if it exists + p861info->total_did_type7db = ++didT7_index; + } + else if (ext_tag == NVT_CTA861_EXT_TAG_DID_TYPE_VIII) + { + if (payload <= 2) break; + + i++; payload--; + p861info->did_type8_data_block[didT8_index].version.revision = p[i] & 0x07; + p861info->did_type8_data_block[didT8_index].version.tcs = (p[i] & 0x08) >> 3; + p861info->did_type8_data_block[didT8_index].version.t8y420 = (p[i] & 0x20) >> 5; + p861info->did_type8_data_block[didT8_index].version.code_type = (p[i] & 0xC0) >> 6; + + //do not consider Byte 3 + i++; payload--; + + if (p861info->did_type8_data_block[didT8_index].version.tcs == 0) + p861info->did_type8_data_block[didT8_index].total_descriptors = (NvU8)payload; + else if (p861info->did_type8_data_block[didT8_index].version.tcs == 1) + p861info->did_type8_data_block[didT8_index].total_descriptors = (NvU8)(payload / 2); + + for (j = 0; j < payload; j++, i++) + { + p861info->did_type8_data_block[didT8_index].payload[j] = p[i]; + } + // next type7 data block if it exists + p861info->total_did_type8db = ++didT8_index; + } + else if (ext_tag == NVT_CTA861_EXT_TAG_DID_TYPE_X) + { + if (payload < 8 || ((payload-2) % 6 != 0 && (payload-2) % 7 != 0)) break; + + i++; payload--; + p861info->did_type10_data_block[didT10_index].version.revision = p[i] & 0x07; + p861info->did_type10_data_block[didT10_index].version.t10_m = (p[i] & 0x70) >> 4; + + // do not consider Byte 3 + i++; payload--; + + if (p861info->did_type10_data_block[didT10_index].version.t10_m == 0) + p861info->did_type10_data_block[didT10_index].total_descriptors = (NvU8)(payload / 6); + else if (p861info->did_type10_data_block[didT10_index].version.t10_m == 1) + p861info->did_type10_data_block[didT10_index].total_descriptors = (NvU8)(payload / 7); + + for (j = 0; j < payload; j++, i++) + { + p861info->did_type10_data_block[didT10_index].payload[j] = p[i]; + } + // next type10 data block if it exists + p861info->total_did_type10db = ++didT10_index; + } else if(ext_tag == NVT_CTA861_EXT_TAG_SCDB && payload >= 7) // sizeof(HDMI Forum Sink Capability Data Block) ranges between 7 to 31 bytes { // As per HDMI2.1 A1 amendment Sink Capability Data Structure(SCDS) can alternatively be included in HDMI Forum Sink Capability Data Block(HF-SCDB), @@ -1572,12 +1783,12 @@ // Copy SCDS over to p861info->vsdb[vendor_index]. Parsing will later be handled in parseEdidHdmiForumVSDB(). for (j = 0; (j < payload - 3) && (j < NVT_CTA861_EXT_SCDB_PAYLOAD_MAX_LENGTH); j ++, i ++) { - p861info->hfscdb[j] = p[i]; + p861info->hfscdb[j] = p[i]; } p861info->hfscdbSize = MIN(payload - 3, NVT_CTA861_EXT_SCDB_PAYLOAD_MAX_LENGTH); p861info->valid.SCDB = 1; } - else if (ext_tag == NVT_CEA861_EXT_TAG_HF_EEODB && payload == 2) + else if (ext_tag == NVT_CTA861_EXT_TAG_HF_EEODB && payload == 2) { // Skip over extended tag i++; payload--; @@ -1600,7 +1811,10 @@ } } - p861info->total_vsdb = (NvU8)vendor_index; + if (p861info) + { + p861info->total_vsdb = (NvU8)vendor_index; + } return NVT_STATUS_SUCCESS; } @@ -1717,8 +1931,7 @@ // loop through the table for (i = 0; i < MAX_CEA861B_FORMAT; i ++) - { - + { if ((EIA861B[i].etc.rep & pixelRepeatMask) == 0) { continue; @@ -1867,8 +2080,9 @@ // "NVT_VIDEO_INFOFRAME" / "VIDEO_INFOFRAME" / "DEFAULT_VIDEO_INFOFRAME" / "NVM_DISP_STATE" etc.. // to accept the new ACE0-3 bits supported in the future. Right now no any sink to support this. // - // Based on the latest CTA-861-G-Errata.pdf file, we need to do following logic to get the correct CTA861 version - // When Y2 = 0, the following algorithm shall be used for AVI InfoFrame version selection: + // Based on the latest CTA-861-H.pdf file, we need to do following logic to get the correct CTA861 version + // When Y=7, the IDO defines the C, EC and ACE fields, it shall use AVI InfoFrame Version 4. + // When Y < 7, the following algorithm shall be used for AVI InfoFrame version selection: // if (C=3 and EC=7) // Sources shall use AVI InfoFrame Version 4. // Else if (VIC>=128) @@ -1879,7 +2093,11 @@ // if (pCtrl) { - if (nvt_get_bits(pInfoFrame->byte1, NVT_VIDEO_INFOFRAME_BYTE1_Y2Y1Y0_MASK, NVT_VIDEO_INFOFRAME_BYTE1_Y2Y1Y0_SHIFT) <= NVT_VIDEO_INFOFRAME_BYTE1_Y2Y1Y0_FUTURE) // this shall be as 0 always. + if (nvt_get_bits(pInfoFrame->byte1, NVT_VIDEO_INFOFRAME_BYTE1_Y2Y1Y0_MASK, NVT_VIDEO_INFOFRAME_BYTE1_Y2Y1Y0_SHIFT) == NVT_VIDEO_INFOFRAME_BYTE1_Y2Y1Y0_IDODEFINED) + { + pInfoFrame->version = NVT_VIDEO_INFOFRAME_VERSION_4; + } + else if (nvt_get_bits(pInfoFrame->byte1, NVT_VIDEO_INFOFRAME_BYTE1_Y2Y1Y0_MASK, NVT_VIDEO_INFOFRAME_BYTE1_Y2Y1Y0_SHIFT) < NVT_VIDEO_INFOFRAME_BYTE1_Y2Y1Y0_IDODEFINED) { if ((nvt_get_bits(pInfoFrame->byte2, NVT_VIDEO_INFOFRAME_BYTE2_C1C0_MASK, NVT_VIDEO_INFOFRAME_BYTE2_C1C0_SHIFT) == NVT_VIDEO_INFOFRAME_BYTE2_C1C0_EXT_COLORIMETRY) && //EC2-0 is based on the 7.5.5 at CTA861-G which DCI-P3 bit defined or notat byte4 @@ -1907,7 +2125,7 @@ if (pInfoFrame->version == NVT_VIDEO_INFOFRAME_VERSION_2) { - nvt_nvu8_set_bits(pInfoFrame->byte4, 0, NVT_VIDEO_INFOFRAME_BYTE4_RESERVED_V2_MASK, NVT_VIDEO_INFOFRAME_BYTE4_RESERVED_V2_SHIFT); + nvt_nvu8_set_bits(pInfoFrame->byte4, 0, NVT_VIDEO_INFOFRAME_BYTE4_RESERVED_V2_MASK, NVT_VIDEO_INFOFRAME_BYTE4_RESERVED_V2_SHIFT); } else if (pInfoFrame->version == NVT_VIDEO_INFOFRAME_VERSION_1) { @@ -2132,7 +2350,7 @@ NvU8 HDMIFormat; // parameter check - if (pEdidInfo == NULL || pInfoFrame == NULL) + if (pEdidInfo == NULL || pInfoFrame == NULL || pCtrl == NULL) { return NVT_STATUS_INVALID_PARAMETER; } @@ -2145,104 +2363,129 @@ // initialize the infoframe buffer - *pInfoFrame = DEFAULT_VENDOR_SPECIFIC_INFOFRAME; + nvt_nvu8_set_bits(pInfoFrame->Header.type, NVT_HDMI_VS_HB0_VALUE, NVT_HDMI_VS_HB0_MASK, NVT_HDMI_VS_HB0_SHIFT); + nvt_nvu8_set_bits(pInfoFrame->Header.version, NVT_HDMI_VS_HB1_VALUE, NVT_HDMI_VS_HB1_MASK, NVT_HDMI_VS_HB1_SHIFT); + nvt_nvu8_set_bits(pInfoFrame->Header.length, NVT_HDMI_VS_HB2_VALUE, NVT_HDMI_VS_HB2_MASK, NVT_HDMI_VS_HB2_SHIFT); + + if (pCtrl->HDMIRevision == 14) + { + nvt_nvu8_set_bits(pInfoFrame->Data.byte1, NVT_HDMI_VS_BYTE1_OUI_VER_1_4, NVT_HDMI_VS_BYTE1_OUI_MASK, NVT_HDMI_VS_BYTE1_OUI_SHIFT); + nvt_nvu8_set_bits(pInfoFrame->Data.byte2, NVT_HDMI_VS_BYTE2_OUI_VER_1_4, NVT_HDMI_VS_BYTE2_OUI_MASK, NVT_HDMI_VS_BYTE2_OUI_SHIFT); + nvt_nvu8_set_bits(pInfoFrame->Data.byte3, NVT_HDMI_VS_BYTE3_OUI_VER_1_4, NVT_HDMI_VS_BYTE3_OUI_MASK, NVT_HDMI_VS_BYTE3_OUI_SHIFT); + } + else if (pCtrl->HDMIRevision >= 20) + { + nvt_nvu8_set_bits(pInfoFrame->Data.byte1, NVT_HDMI_VS_BYTE1_OUI_VER_2_0, NVT_HDMI_VS_BYTE1_OUI_MASK, NVT_HDMI_VS_BYTE1_OUI_SHIFT); + nvt_nvu8_set_bits(pInfoFrame->Data.byte2, NVT_HDMI_VS_BYTE2_OUI_VER_2_0, NVT_HDMI_VS_BYTE2_OUI_MASK, NVT_HDMI_VS_BYTE2_OUI_SHIFT); + nvt_nvu8_set_bits(pInfoFrame->Data.byte3, NVT_HDMI_VS_BYTE3_OUI_VER_2_0, NVT_HDMI_VS_BYTE3_OUI_MASK, NVT_HDMI_VS_BYTE3_OUI_SHIFT); + } // init the header (mostly done in default Infoframe) pInfoFrame->Header.length = offsetof(NVT_VENDOR_SPECIFIC_INFOFRAME_PAYLOAD, optionalBytes); // construct the desired infoframe contents based on the control - if (pCtrl) - { - // clear all static reserved fields - nvt_nvu8_set_bits(pInfoFrame->Data.byte4, 0, NVT_HDMI_VS_BYTE4_RSVD_MASK, NVT_HDMI_VS_BYTE4_RSVD_SHIFT); + + // clear all static reserved fields + nvt_nvu8_set_bits(pInfoFrame->Data.byte4, 0, NVT_HDMI_VS_BYTE4_RSVD_MASK, NVT_HDMI_VS_BYTE4_RSVD_SHIFT); - // setup the parameters - nvt_nvu8_set_bits(pInfoFrame->Data.byte4, pCtrl->HDMIFormat, NVT_HDMI_VS_BYTE4_HDMI_VID_FMT_MASK, NVT_HDMI_VS_BYTE4_HDMI_VID_FMT_SHIFT); + // setup the parameters + nvt_nvu8_set_bits(pInfoFrame->Data.byte4, pCtrl->HDMIFormat, NVT_HDMI_VS_BYTE4_HDMI_VID_FMT_MASK, NVT_HDMI_VS_BYTE4_HDMI_VID_FMT_SHIFT); - // determine what the format is -- if disabled, force the format to NONE. - if (pCtrl->Enable) + // determine what the format is -- if disabled, force the format to NONE. + if (pCtrl->Enable) + { + HDMIFormat = pCtrl->HDMIFormat; + } + else + { + HDMIFormat = NVT_HDMI_VS_BYTE4_HDMI_VID_FMT_NONE; + } + + switch(HDMIFormat) + { + case NVT_HDMI_VS_BYTE4_HDMI_VID_FMT_NONE: { - HDMIFormat = pCtrl->HDMIFormat; + nvt_nvu8_set_bits(pInfoFrame->Data.byte5, 0, NVT_HDMI_VS_BYTENv_RSVD_MASK, NVT_HDMI_VS_BYTENv_RSVD_SHIFT); + break; } - else + case NVT_HDMI_VS_BYTE4_HDMI_VID_FMT_EXT: { - HDMIFormat = NVT_HDMI_VS_BYTE4_HDMI_VID_FMT_NONE; + // Note: extended resolution frames are not yet fully supported + nvt_nvu8_set_bits(pInfoFrame->Data.byte5, pCtrl->HDMI_VIC, NVT_HDMI_VS_BYTE5_HDMI_VIC_MASK, NVT_HDMI_VS_BYTE5_HDMI_VIC_SHIFT); + break; } - - switch(HDMIFormat) + case NVT_HDMI_VS_BYTE4_HDMI_VID_FMT_3D: { - case NVT_HDMI_VS_BYTE4_HDMI_VID_FMT_NONE: - { - nvt_nvu8_set_bits(pInfoFrame->Data.byte5, 0, NVT_HDMI_VS_BYTENv_RSVD_MASK, NVT_HDMI_VS_BYTENv_RSVD_SHIFT); - break; - } - case NVT_HDMI_VS_BYTE4_HDMI_VID_FMT_EXT: + nvt_nvu8_set_bits(pInfoFrame->Data.byte5, 0, NVT_HDMI_VS_BYTE5_HDMI_RSVD_MASK, NVT_HDMI_VS_BYTE5_HDMI_RSVD_SHIFT); + nvt_nvu8_set_bits(pInfoFrame->Data.byte5, pCtrl->ThreeDStruc, NVT_HDMI_VS_BYTE5_HDMI_3DS_MASK, NVT_HDMI_VS_BYTE5_HDMI_3DS_SHIFT); + + // side by side half requires additional format data in the infoframe. + if (NVT_HDMI_VS_BYTE5_HDMI_3DS_SIDEBYSIDEHALF == pCtrl->ThreeDStruc) { - // Note: extended resolution frames are not yet fully supported - nvt_nvu8_set_bits(pInfoFrame->Data.byte5, pCtrl->HDMI_VIC, NVT_HDMI_VS_BYTE5_HDMI_VIC_MASK, NVT_HDMI_VS_BYTE5_HDMI_VIC_SHIFT); - break; + nvt_nvu8_set_bits(pInfoFrame->Data.optionalBytes[optIdx], pCtrl->ThreeDDetail, NVT_HDMI_VS_BYTE_OPT1_HDMI_3DEX_MASK, NVT_HDMI_VS_BYTE_OPT1_HDMI_3DEX_SHIFT); + optIdx++; } - case NVT_HDMI_VS_BYTE4_HDMI_VID_FMT_3D: + if (pCtrl->MetadataPresent) { - nvt_nvu8_set_bits(pInfoFrame->Data.byte5, 0, NVT_HDMI_VS_BYTE5_HDMI_RSVD_MASK, NVT_HDMI_VS_BYTE5_HDMI_RSVD_SHIFT); - nvt_nvu8_set_bits(pInfoFrame->Data.byte5, pCtrl->ThreeDStruc, NVT_HDMI_VS_BYTE5_HDMI_3DS_MASK, NVT_HDMI_VS_BYTE5_HDMI_3DS_SHIFT); + nvt_nvu8_set_bits(pInfoFrame->Data.byte5, NVT_HDMI_VS_BYTE5_HDMI_META_PRESENT_PRES, NVT_HDMI_VS_BYTE5_3D_META_PRESENT_MASK, NVT_HDMI_VS_BYTE5_3D_META_PRESENT_SHIFT); - // side by side half requires additional format data in the infoframe. - if (NVT_HDMI_VS_BYTE5_HDMI_3DS_SIDEBYSIDEHALF == pCtrl->ThreeDStruc) - { - nvt_nvu8_set_bits(pInfoFrame->Data.optionalBytes[optIdx], pCtrl->ThreeDDetail, NVT_HDMI_VS_BYTE_OPT1_HDMI_3DEX_MASK, NVT_HDMI_VS_BYTE_OPT1_HDMI_3DEX_SHIFT); - optIdx++; - } - if (pCtrl->MetadataPresent) + switch(pCtrl->MetadataType) { - nvt_nvu8_set_bits(pInfoFrame->Data.byte5, NVT_HDMI_VS_BYTE5_HDMI_META_PRESENT_PRES, NVT_HDMI_VS_BYTE5_3D_META_PRESENT_MASK, NVT_HDMI_VS_BYTE5_3D_META_PRESENT_SHIFT); - - switch(pCtrl->MetadataType) + case NVT_HDMI_VS_BYTE_OPT2_HDMI_METADATA_TYPE_PARALLAX: { - case NVT_HDMI_VS_BYTE_OPT2_HDMI_METADATA_TYPE_PARALLAX: + if (sizeof(pCtrl->Metadata) >= NVT_HDMI_VS_BYTE_OPT2_HDMI_METADATA_LEN_PARALLAX && + sizeof(pInfoFrame->Data.optionalBytes) - (optIdx + 1) >= NVT_HDMI_VS_BYTE_OPT2_HDMI_METADATA_LEN_PARALLAX) { - if (sizeof(pCtrl->Metadata) >= NVT_HDMI_VS_BYTE_OPT2_HDMI_METADATA_LEN_PARALLAX && - sizeof(pInfoFrame->Data.optionalBytes) - (optIdx + 1) >= NVT_HDMI_VS_BYTE_OPT2_HDMI_METADATA_LEN_PARALLAX) - { - nvt_nvu8_set_bits(pInfoFrame->Data.optionalBytes[optIdx], NVT_HDMI_VS_BYTE_OPT2_HDMI_METADATA_LEN_PARALLAX, NVT_HDMI_VS_BYTE_OPT2_HDMI_METADATA_LEN_MASK, NVT_HDMI_VS_BYTE_OPT2_HDMI_METADATA_LEN_SHIFT); - nvt_nvu8_set_bits(pInfoFrame->Data.optionalBytes[optIdx], NVT_HDMI_VS_BYTE_OPT2_HDMI_METADATA_TYPE_PARALLAX, NVT_HDMI_VS_BYTE_OPT2_HDMI_METADATA_TYPE_MASK, NVT_HDMI_VS_BYTE_OPT2_HDMI_METADATA_TYPE_SHIFT); - ++optIdx; + nvt_nvu8_set_bits(pInfoFrame->Data.optionalBytes[optIdx], NVT_HDMI_VS_BYTE_OPT2_HDMI_METADATA_LEN_PARALLAX, NVT_HDMI_VS_BYTE_OPT2_HDMI_METADATA_LEN_MASK, NVT_HDMI_VS_BYTE_OPT2_HDMI_METADATA_LEN_SHIFT); + nvt_nvu8_set_bits(pInfoFrame->Data.optionalBytes[optIdx], NVT_HDMI_VS_BYTE_OPT2_HDMI_METADATA_TYPE_PARALLAX, NVT_HDMI_VS_BYTE_OPT2_HDMI_METADATA_TYPE_MASK, NVT_HDMI_VS_BYTE_OPT2_HDMI_METADATA_TYPE_SHIFT); + ++optIdx; - NVMISC_MEMCPY(pCtrl->Metadata, &pInfoFrame->Data.optionalBytes[optIdx], NVT_HDMI_VS_BYTE_OPT2_HDMI_METADATA_LEN_PARALLAX); - optIdx += NVT_HDMI_VS_BYTE_OPT2_HDMI_METADATA_LEN_PARALLAX; - } - else - { - // not enough data in the control struct or not enough room in the infoframe -- BOTH compile time issues!! - // ignore metadata. - nvt_nvu8_set_bits(pInfoFrame->Data.byte5, NVT_HDMI_VS_BYTE5_HDMI_META_PRESENT_NOTPRES, NVT_HDMI_VS_BYTE5_3D_META_PRESENT_MASK, NVT_HDMI_VS_BYTE5_3D_META_PRESENT_SHIFT); - } - break; + NVMISC_MEMCPY(pCtrl->Metadata, &pInfoFrame->Data.optionalBytes[optIdx], NVT_HDMI_VS_BYTE_OPT2_HDMI_METADATA_LEN_PARALLAX); + optIdx += NVT_HDMI_VS_BYTE_OPT2_HDMI_METADATA_LEN_PARALLAX; } - default: + else { - // unrecognised metadata, recover the best we can. - // note -- can not copy whatever is there because type implies length. + // not enough data in the control struct or not enough room in the infoframe -- BOTH compile time issues!! + // ignore metadata. nvt_nvu8_set_bits(pInfoFrame->Data.byte5, NVT_HDMI_VS_BYTE5_HDMI_META_PRESENT_NOTPRES, NVT_HDMI_VS_BYTE5_3D_META_PRESENT_MASK, NVT_HDMI_VS_BYTE5_3D_META_PRESENT_SHIFT); - RetCode = NVT_STATUS_ERR; } + break; + } + default: + { + // unrecognised metadata, recover the best we can. + // note -- can not copy whatever is there because type implies length. + nvt_nvu8_set_bits(pInfoFrame->Data.byte5, NVT_HDMI_VS_BYTE5_HDMI_META_PRESENT_NOTPRES, NVT_HDMI_VS_BYTE5_3D_META_PRESENT_MASK, NVT_HDMI_VS_BYTE5_3D_META_PRESENT_SHIFT); + RetCode = NVT_STATUS_ERR; } - - } - else - { - nvt_nvu8_set_bits(pInfoFrame->Data.byte5, NVT_HDMI_VS_BYTE5_HDMI_META_PRESENT_NOTPRES, NVT_HDMI_VS_BYTE5_3D_META_PRESENT_MASK, NVT_HDMI_VS_BYTE5_3D_META_PRESENT_SHIFT); } - break; + } + else + { + nvt_nvu8_set_bits(pInfoFrame->Data.byte5, NVT_HDMI_VS_BYTE5_HDMI_META_PRESENT_NOTPRES, NVT_HDMI_VS_BYTE5_3D_META_PRESENT_MASK, NVT_HDMI_VS_BYTE5_3D_META_PRESENT_SHIFT); + } + break; } - // clear last byte of infoframe (reserved per spec). - pInfoFrame->Header.length += optIdx + 1; - for (; optIdx < sizeof(pInfoFrame->Data.optionalBytes); ++optIdx) - { - nvt_nvu8_set_bits(pInfoFrame->Data.optionalBytes[optIdx], NVT_HDMI_VS_BYTENv_RSVD, NVT_HDMI_VS_BYTENv_RSVD_MASK, NVT_HDMI_VS_BYTENv_RSVD_SHIFT); - } + + } + + if (pCtrl->ALLMEnable == 1) + { + nvt_nvu8_set_bits(pInfoFrame->Data.byte5, NVT_HDMI_VS_BYTE5_ALLM_MODE_EN, NVT_HDMI_VS_BYTE5_ALLM_MODE_MASK, NVT_HDMI_VS_BYTE5_ALLM_MODE_SHIFT); + } + else if (pCtrl->ALLMEnable == 0) + { + nvt_nvu8_set_bits(pInfoFrame->Data.byte5, NVT_HDMI_VS_BYTE5_ALLM_MODE_DIS, NVT_HDMI_VS_BYTE5_ALLM_MODE_MASK, NVT_HDMI_VS_BYTE5_ALLM_MODE_SHIFT); } + + // clear last byte of infoframe (reserved per spec). + pInfoFrame->Header.length += optIdx + 1; + for (; optIdx < sizeof(pInfoFrame->Data.optionalBytes); ++optIdx) + { + nvt_nvu8_set_bits(pInfoFrame->Data.optionalBytes[optIdx], NVT_HDMI_VS_BYTENv_RSVD, NVT_HDMI_VS_BYTENv_RSVD_MASK, NVT_HDMI_VS_BYTENv_RSVD_SHIFT); + } + return RetCode; } @@ -2266,6 +2509,13 @@ pInfoFrame->Header.firstLast = NVT_EMP_HEADER_FIRST_LAST; pInfoFrame->Header.sequenceIndex = 0x00; + if (pCtrl->EnableQMS) + { + nvt_nvu8_set_bits(pInfoFrame->Data.byte1, NVT_HDMI_EMP_BYTE1_SYNC_ENABLE, + NVT_HDMI_EMP_BYTE1_SYNC_MASK, + NVT_HDMI_EMP_BYTE1_SYNC_SHIFT); + } + nvt_nvu8_set_bits(pInfoFrame->Data.byte1, NVT_HDMI_EMP_BYTE1_VFR_ENABLE, NVT_HDMI_EMP_BYTE1_VFR_MASK, NVT_HDMI_EMP_BYTE1_VFR_SHIFT); @@ -2274,7 +2524,7 @@ NVT_HDMI_EMP_BYTE1_NEW_MASK, NVT_HDMI_EMP_BYTE1_NEW_SHIFT); - if (!pCtrl->EnableVRR) + if (!pCtrl->EnableVRR && !pCtrl->EnableQMS) { nvt_nvu8_set_bits(pInfoFrame->Data.byte1, NVT_HDMI_EMP_BYTE1_END_ENABLE, NVT_HDMI_EMP_BYTE1_END_MASK, @@ -2290,7 +2540,7 @@ NVT_HDMI_EMP_BYTE5_DATA_SET_TAG_LSB_MASK, NVT_HDMI_EMP_BYTE5_DATA_SET_TAG_LSB_SHIFT); - nvt_nvu8_set_bits(pInfoFrame->Data.byte7, (pCtrl->EnableVRR ? 4 : 0), + nvt_nvu8_set_bits(pInfoFrame->Data.byte7, ((pCtrl->EnableVRR || pCtrl->EnableQMS) ? 4 : 0), NVT_HDMI_EMP_BYTE7_DATA_SET_LENGTH_LSB_MASK, NVT_HDMI_EMP_BYTE7_DATA_SET_LENGTH_LSB_SHIFT); @@ -2301,6 +2551,16 @@ NVT_HDMI_EMP_BYTE8_MD0_VRR_EN_MASK, NVT_HDMI_EMP_BYTE8_MD0_VRR_EN_SHIFT); } + else if (pCtrl->EnableQMS) + { + nvt_nvu8_set_bits(pInfoFrame->Data.metadataBytes[0], 1, + NVT_HDMI_EMP_BYTE8_MD0_M_CONST_MASK, + NVT_HDMI_EMP_BYTE8_MD0_M_CONST_SHIFT); + nvt_nvu8_set_bits(pInfoFrame->Data.metadataBytes[0], + NVT_HDMI_EMP_BYTE8_MD0_QMS_EN_ENABLE, + NVT_HDMI_EMP_BYTE8_MD0_QMS_EN_MASK, + NVT_HDMI_EMP_BYTE8_MD0_QMS_EN_SHIFT); + } if (pCtrl->ITTiming) { @@ -2335,6 +2595,67 @@ return RetCode; } +// Construct Adaptive Sync SDP +CODE_SEGMENT(PAGE_DD_CODE) +void NvTiming_ConstructAdaptiveSyncSDP( + const NVT_ADAPTIVE_SYNC_SDP_CTRL *pCtrl, + NVT_ADAPTIVE_SYNC_SDP *pSdp) +{ + if (!pCtrl || !pSdp) + { + return; + } + + // Initialize the infoframe + NVMISC_MEMSET(pSdp, 0, sizeof(*pSdp)); + + // Construct an infoframe to enable or disable Adaptive Sync SDP + pSdp->header.type = NVT_DP_ADAPTIVE_SYNC_SDP_PACKET_TYPE; + pSdp->header.version = NVT_DP_ADAPTIVE_SYNC_SDP_VERSION; + pSdp->header.length = NVT_DP_ADAPTIVE_SYNC_SDP_LENGTH; + + // Payload + if (pCtrl->bFixedVTotal) + { + nvt_nvu8_set_bits(pSdp->payload.db0, NVT_DP_ADAPTIVE_SYNC_SDP_DB0_VARIABLE_FRAME_RATE_FAVT_TARGET_REACHED, + NVT_DP_ADAPTIVE_SYNC_SDP_DB0_VARIABLE_FRAME_RATE_MASK, + NVT_DP_ADAPTIVE_SYNC_SDP_DB0_VARIABLE_FRAME_RATE_SHIFT); + if (pCtrl->targetRefreshRate) + { + nvt_nvu8_set_bits(pSdp->payload.db3, pCtrl->targetRefreshRate & 0xff, + NVT_DP_ADAPTIVE_SYNC_SDP_DB3_TARGET_RR_LSB_MASK, + NVT_DP_ADAPTIVE_SYNC_SDP_DB3_TARGET_RR_LSB_SHIFT); + + nvt_nvu8_set_bits(pSdp->payload.db4, pCtrl->targetRefreshRate & 0x1, + NVT_DP_ADAPTIVE_SYNC_SDP_DB4_TARGET_RR_MSB_MASK, + NVT_DP_ADAPTIVE_SYNC_SDP_DB4_TARGET_RR_MSB_SHIFT); + } + } + else + { + nvt_nvu8_set_bits(pSdp->payload.db0, NVT_DP_ADAPTIVE_SYNC_SDP_DB0_VARIABLE_FRAME_RATE_AVT_VARIABLE, + NVT_DP_ADAPTIVE_SYNC_SDP_DB0_VARIABLE_FRAME_RATE_MASK, + NVT_DP_ADAPTIVE_SYNC_SDP_DB0_VARIABLE_FRAME_RATE_SHIFT); + } + + if (pCtrl->minVTotal) + { + nvt_nvu8_set_bits(pSdp->payload.db1, pCtrl->minVTotal & 0xff, + NVT_DP_ADAPTIVE_SYNC_SDP_DB1_MIN_VTOTAL_LSB_MASK, + NVT_DP_ADAPTIVE_SYNC_SDP_DB1_MIN_VTOTAL_LSB_SHIFT); + nvt_nvu8_set_bits(pSdp->payload.db2, (pCtrl->minVTotal & 0xff00) >> 8, + NVT_DP_ADAPTIVE_SYNC_SDP_DB2_MIN_VTOTAL_MSB_MASK, + NVT_DP_ADAPTIVE_SYNC_SDP_DB2_MIN_VTOTAL_MSB_SHIFT); + } + + if (pCtrl->bRefreshRateDivider) + { + nvt_nvu8_set_bits(pSdp->payload.db4, NVT_DP_ADAPTIVE_SYNC_SDP_DB4_TARGET_RR_DIVIDER_ENABLE, + NVT_DP_ADAPTIVE_SYNC_SDP_DB4_TARGET_RR_DIVIDER_MASK, + NVT_DP_ADAPTIVE_SYNC_SDP_DB4_TARGET_RR_DIVIDER_SHIFT); + } +} + // Enumerate Psf Timing CODE_SEGMENT(PAGE_DD_CODE) NVT_STATUS NvTiming_EnumNvPsfTiming(NvU32 nvPsfFormat, NVT_TIMING *pT) @@ -2962,6 +3283,7 @@ pHdmiInfo->cnmvrr = pHdmiForum->CNMVRR; pHdmiInfo->cinemaVrr = pHdmiForum->CinemaVRR; pHdmiInfo->m_delta = pHdmiForum->M_delta; + pHdmiInfo->qms = pHdmiForum->QMS; pHdmiInfo->fapa_end_extended = pHdmiForum->FAPA_End_Extended; // sixth byte @@ -2990,7 +3312,9 @@ pHdmiInfo->dsc_All_bpp = pHdmiForum->DSC_All_bpp; pHdmiInfo->dsc_Native_420 = pHdmiForum->DSC_Native_420; pHdmiInfo->dsc_1p2 = pHdmiForum->DSC_1p2; - + pHdmiInfo->qms_tfr_min = pHdmiForum->QMS_TFR_min; + pHdmiInfo->qms_tfr_max = pHdmiForum->QMS_TFR_max; + // ninth byte if (!remainingSize--) { @@ -3037,9 +3361,10 @@ NVT_HDR10PLUS_INFO *pHdr10PlusInfo = NULL; if (pExt861 == NULL || pRawInfo == NULL) - { return; - } + + if(pExt861->vsvdb.ieee_id != NVT_CEA861_HDR10PLUS_IEEE_ID) + return; if (flag == FROM_CTA861_EXTENSION || flag == FROM_DISPLAYID_13_DATA_BLOCK) { @@ -3056,19 +3381,227 @@ return; } - if(pExt861->vsvdb.ieee_id != NVT_CEA861_HDR10PLUS_IEEE_ID) - { + NVMISC_MEMSET(pHdr10PlusInfo, 0, sizeof(NVT_HDR10PLUS_INFO)); + + if (pExt861->vsvdb.vendor_data_size < sizeof(NVT_HDR10PLUS_INFO)) return; + + NVMISC_MEMCPY(pHdr10PlusInfo, &pExt861->vsvdb.vendor_data, sizeof(NVT_HDR10PLUS_INFO)); +} + +CODE_SEGMENT(PAGE_DD_CODE) +void parseCta861DIDType7VideoTimingDataBlock(NVT_EDID_CEA861_INFO *pExt861, void *pRawInfo) +{ + NvU8 i = 0; + NvU8 t7db_idx = 0; + NvU8 startSeqNum = 0; + + NVT_TIMING newTiming; + NVT_EDID_INFO *pInfo = (NVT_EDID_INFO *)pRawInfo; + const DISPLAYID_2_0_TIMING_7_DESCRIPTOR *pT7Descriptor = NULL; + NvU8 eachOfDescSize = sizeof(DISPLAYID_2_0_TIMING_7_DESCRIPTOR); + + for (t7db_idx = 0; t7db_idx < pExt861->total_did_type7db; t7db_idx++) + { + // 20 bytes + eachOfDescSize += pExt861->did_type7_data_block[t7db_idx].version.t7_m; + + if (pExt861->did_type7_data_block[t7db_idx].total_descriptors != NVT_CTA861_DID_TYPE7_DESCRIPTORS_MAX) + { + nvt_assert(0 && "payload descriptor invalid. expect T7VTDB only 1 descriptor"); + continue; + } + + if (pExt861->did_type7_data_block[t7db_idx].version.revision != 2 ) + { + nvt_assert(0 && "The revision supported by CTA-861 is not 2"); + } + + startSeqNum = getExistedCTATimingSeqNumber(pInfo, NVT_TYPE_CTA861_DID_T7); + + for (i = 0; i < pExt861->did_type7_data_block[i].total_descriptors; i++) + { + NVMISC_MEMSET(&newTiming, 0, sizeof(newTiming)); + if (NVT_STATUS_SUCCESS == parseDisplayId20Timing7Descriptor(&pExt861->did_type7_data_block[t7db_idx].payload[i*eachOfDescSize], + &newTiming, + startSeqNum+i)) + { + // T7VTDB shall not be used with video timing that can be expressed in an 18-byte DTD + if (newTiming.HVisible < 4096 && newTiming.VVisible < 4096 && newTiming.pclk < 65536) + { + nvt_assert(0 && "The timing can be expressed in an 18-byte DTD"); + continue; + } + + pT7Descriptor = (const DISPLAYID_2_0_TIMING_7_DESCRIPTOR *) + &pExt861->did_type7_data_block[t7db_idx].payload[i*eachOfDescSize]; + + if (pT7Descriptor->options.is_preferred_or_ycc420 == 1 && newTiming.pclk > NVT_HDMI_YUV_420_PCLK_SUPPORTED_MIN) + { + newTiming.etc.yuv420.bpcs = 0; + UPDATE_BPC_FOR_COLORFORMAT(newTiming.etc.yuv420, 0, 1, + pInfo->hdmiForumInfo.dc_30bit_420, + pInfo->hdmiForumInfo.dc_36bit_420, 0, + pInfo->hdmiForumInfo.dc_48bit_420); + } + + NVT_SNPRINTF((char *)newTiming.etc.name, sizeof(newTiming.etc.name), "CTA861-T7:#%3d:%dx%dx%3d.%03dHz/%s", + (int)NVT_GET_TIMING_STATUS_SEQ(newTiming.etc.status), + (int)newTiming.HVisible, + (int)newTiming.VVisible, + (int)newTiming.etc.rrx1k/1000, + (int)newTiming.etc.rrx1k%1000, + (newTiming.interlaced ? "I":"P")); + newTiming.etc.status = NVT_STATUS_CTA861_DID_T7N(NVT_GET_TIMING_STATUS_SEQ(newTiming.etc.status)); + newTiming.etc.name[sizeof(newTiming.etc.name) - 1] = '\0'; + newTiming.etc.rep = 0x1; + + if (!assignNextAvailableTiming(pInfo, &newTiming)) + { + break; + } + } + } } +} - NVMISC_MEMSET(pHdr10PlusInfo, 0, sizeof(NVT_HDR10PLUS_INFO)); +CODE_SEGMENT(PAGE_DD_CODE) +void parseCta861DIDType8VideoTimingDataBlock(NVT_EDID_CEA861_INFO *pExt861, void *pRawInfo) +{ + NvU8 i = 0; + NvU8 t8db_idx = 0; + NvU8 startSeqNum = 0; + NvU8 codeSize = 0; + NvU8 codeType = 0; - if (pExt861->vsvdb.vendor_data_size < sizeof(NVT_HDR10PLUS_INFO)) + NVT_TIMING newTiming; + NVT_EDID_INFO *pInfo = (NVT_EDID_INFO *)pRawInfo; + + for (t8db_idx = 0; t8db_idx < pExt861->total_did_type8db; t8db_idx++) { - return; + codeType = pExt861->did_type8_data_block[t8db_idx].version.code_type; + codeSize = pExt861->did_type8_data_block[t8db_idx].version.tcs; + + if (codeType != 0 /*DMT*/) + { + nvt_assert(0 && "Not DMT code type!"); + continue; + } + + startSeqNum = getExistedCTATimingSeqNumber(pInfo, NVT_TYPE_CTA861_DID_T8); + + for (i=0; i < pExt861->did_type8_data_block[t8db_idx].total_descriptors; i++) + { + NVMISC_MEMSET(&newTiming, 0, sizeof(newTiming)); + + if (parseDisplayId20Timing8Descriptor(pExt861->did_type8_data_block[t8db_idx].payload, + &newTiming, codeType, codeSize, i, startSeqNum + i) == NVT_STATUS_SUCCESS) + { + if (pExt861->did_type8_data_block[t8db_idx].version.t8y420 == 1 && newTiming.pclk > NVT_HDMI_YUV_420_PCLK_SUPPORTED_MIN) + { + UPDATE_BPC_FOR_COLORFORMAT(newTiming.etc.yuv420, 0, 1, + pInfo->hdmiForumInfo.dc_30bit_420, + pInfo->hdmiForumInfo.dc_36bit_420, 0, + pInfo->hdmiForumInfo.dc_48bit_420); + } + NVT_SNPRINTF((char *)newTiming.etc.name, sizeof(newTiming.etc.name), "CTA861-T8:#%3d:%dx%dx%3d.%03dHz/%s", + (int)NVT_GET_TIMING_STATUS_SEQ(newTiming.etc.status), + (int)newTiming.HVisible, (int)newTiming.VVisible, + (int)newTiming.etc.rrx1k/1000, (int)newTiming.etc.rrx1k%1000, + (newTiming.interlaced ? "I":"P")); + newTiming.etc.status = NVT_STATUS_CTA861_DID_T8N(NVT_GET_TIMING_STATUS_SEQ(newTiming.etc.status)); + newTiming.etc.name[sizeof(newTiming.etc.name) - 1] = '\0'; + newTiming.etc.rep = 0x1; + + if (!assignNextAvailableTiming(pInfo, &newTiming)) + { + break; + } + } + } } +} - NVMISC_MEMCPY(pHdr10PlusInfo, &pExt861->vsvdb.vendor_data, sizeof(NVT_HDR10PLUS_INFO)); +CODE_SEGMENT(PAGE_DD_CODE) +void parseCta861DIDType10VideoTimingDataBlock(NVT_EDID_CEA861_INFO *pExt861, void *pRawInfo) +{ + NvU8 i = 0; + NvU8 t10db_idx = 0; + NvU8 startSeqNum = 0; + + NVT_TIMING newTiming; + NVT_EDID_INFO *pInfo = (NVT_EDID_INFO *)pRawInfo; + const DISPLAYID_2_0_TIMING_10_6BYTES_DESCRIPTOR *p6bytesDescriptor = NULL; + NvU8 eachOfDescriptorsSize = sizeof (DISPLAYID_2_0_TIMING_10_6BYTES_DESCRIPTOR); + + for (t10db_idx = 0; t10db_idx < pExt861->total_did_type10db; t10db_idx++) + { + startSeqNum = getExistedCTATimingSeqNumber(pInfo, NVT_TYPE_CTA861_DID_T10); + + // 6 or 7 bytes length + eachOfDescriptorsSize += pExt861->did_type10_data_block[t10db_idx].version.t10_m; + + for (i = 0; i < pExt861->did_type10_data_block[t10db_idx].total_descriptors; i++) + { + if (pExt861->did_type10_data_block[t10db_idx].total_descriptors < NVT_CTA861_DID_TYPE10_DESCRIPTORS_MIN || + pExt861->did_type10_data_block[t10db_idx].total_descriptors > NVT_CTA861_DID_TYPE10_DESCRIPTORS_MAX) + { + nvt_assert(0 && "payload descriptor invalid. expect T10VTDB has minimum 1 descriptor, maximum 4 descriptors"); + continue; + } + + NVMISC_MEMSET(&newTiming, 0, sizeof(newTiming)); + if (NVT_STATUS_SUCCESS == parseDisplayId20Timing10Descriptor(&pExt861->did_type10_data_block[t10db_idx].payload[i*eachOfDescriptorsSize], + &newTiming, + pExt861->did_type10_data_block[t10db_idx].version.t10_m, startSeqNum+i)) + { + p6bytesDescriptor = (const DISPLAYID_2_0_TIMING_10_6BYTES_DESCRIPTOR *) + &pExt861->did_type10_data_block[t10db_idx].payload[i*eachOfDescriptorsSize]; + + if (p6bytesDescriptor->options.ycc420_support && newTiming.pclk > NVT_HDMI_YUV_420_PCLK_SUPPORTED_MIN) + { + UPDATE_BPC_FOR_COLORFORMAT(newTiming.etc.yuv420, 0, 1, + pInfo->hdmiForumInfo.dc_30bit_420, + pInfo->hdmiForumInfo.dc_36bit_420, 0, + pInfo->hdmiForumInfo.dc_48bit_420); + } + + if (p6bytesDescriptor->options.timing_formula == DISPLAYID_2_0_TIMING_FORMULA_CVT_1_2_STANDARD) + { + NVT_SNPRINTF((char *)newTiming.etc.name, sizeof(newTiming.etc.name), "CTA861-T10:#%3d:%dx%dx%3d.%03dHz/%s", + (int)NVT_GET_TIMING_STATUS_SEQ(newTiming.etc.status), + (int)newTiming.HVisible, + (int)newTiming.VVisible, + (int)newTiming.etc.rrx1k/1000, + (int)newTiming.etc.rrx1k%1000, + (newTiming.interlaced ? "I":"P")); + } + else + { + NVT_SNPRINTF((char *)newTiming.etc.name, sizeof(newTiming.etc.name), "CTA861-T10RB%d:#%3d:%dx%dx%3d.%03dHz/%s", + p6bytesDescriptor->options.timing_formula, + (int)NVT_GET_TIMING_STATUS_SEQ(newTiming.etc.status), + (int)newTiming.HVisible, + (int)newTiming.VVisible, + (int)newTiming.etc.rrx1k/1000, + (int)newTiming.etc.rrx1k%1000, + (newTiming.interlaced ? "I":"P")); + } + newTiming.etc.status = NVT_STATUS_CTA861_DID_T10N(NVT_GET_TIMING_STATUS_SEQ(newTiming.etc.status)); + newTiming.etc.name[sizeof(newTiming.etc.name) - 1] = '\0'; + newTiming.etc.rep = 0x1; + + if (!assignNextAvailableTiming(pInfo, &newTiming)) + { + break; + } + } + else + { + continue; + } + } + } } POP_SEGMENTS diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/common/modeset/timing/nvt_edidext_displayid.c nvidia-open-gpu-kernel-modules-535.161.08/src/common/modeset/timing/nvt_edidext_displayid.c --- nvidia-open-gpu-kernel-modules-525.147.05/src/common/modeset/timing/nvt_edidext_displayid.c 2023-10-25 20:22:28.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/common/modeset/timing/nvt_edidext_displayid.c 2024-03-05 22:12:05.000000000 +0000 @@ -1,6 +1,6 @@ //***************************************************************************** // -// SPDX-FileCopyrightText: Copyright (c) 2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. +// SPDX-FileCopyrightText: Copyright (c) 2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. // SPDX-License-Identifier: MIT // // Permission is hereby granted, free of charge, to any person obtaining a @@ -1372,9 +1372,9 @@ // yuv420-only video parse861bShortYuv420Timing(p861info, pInfo, FROM_DISPLAYID_13_DATA_BLOCK); // CEA861-F at 7.5.12 section about VFPDB block. - if (p861info->total_vfpdb != 0) + if (p861info->total_svr != 0) { - parse861bShortPreferredTiming(p861info, pInfo, FROM_DISPLAYID_13_DATA_BLOCK); + parseCta861NativeOrPreferredTiming(p861info, pInfo, FROM_DISPLAYID_13_DATA_BLOCK); } return NVT_STATUS_SUCCESS; diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/common/modeset/timing/nvtiming.h nvidia-open-gpu-kernel-modules-535.161.08/src/common/modeset/timing/nvtiming.h --- nvidia-open-gpu-kernel-modules-525.147.05/src/common/modeset/timing/nvtiming.h 2023-10-25 20:22:29.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/common/modeset/timing/nvtiming.h 2024-03-05 22:12:05.000000000 +0000 @@ -1,6 +1,6 @@ //**************************************************************************** // -// SPDX-FileCopyrightText: Copyright (c) 2021 NVIDIA CORPORATION & AFFILIATES. All rights reserved. +// SPDX-FileCopyrightText: Copyright (c) 2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. // SPDX-License-Identifier: MIT // // Permission is hereby granted, free of charge, to any person obtaining a @@ -278,17 +278,17 @@ NVT_TYPE_CVT_RB, // CVT timing with reduced blanking NVT_TYPE_CUST, // Customized timing NVT_TYPE_EDID_DTD, // EDID detailed timing - NVT_TYPE_EDID_STD, // EDID standard timing + NVT_TYPE_EDID_STD, // = 10 EDID standard timing NVT_TYPE_EDID_EST, // EDID established timing NVT_TYPE_EDID_CVT, // EDID defined CVT timing (EDID 1.4) - NVT_TYPE_EDID_861ST, // EDID defined CEA/EIA 861 timing (in the EDID 861 extension) + NVT_TYPE_EDID_861ST, // EDID defined CEA/EIA 861 timing (in the CTA861 extension) NVT_TYPE_NV_PREDEFINED, // NV pre-defined timings (PsF timings) NVT_TYPE_DMT_RB, // DMT timing with reduced blanking NVT_TYPE_EDID_EXT_DTD, // EDID detailed timing in the extension NVT_TYPE_SDTV, // SDTV timing (including NTSC, PAL etc) NVT_TYPE_HDTV, // HDTV timing (480p,480i,720p, 1080i etc) NVT_TYPE_SMPTE, // deprecated ? still used by drivers\unix\nvkms\src\nvkms-dpy.c - NVT_TYPE_EDID_VTB_EXT, // EDID defined VTB extension timing + NVT_TYPE_EDID_VTB_EXT, // = 20 EDID defined VTB extension timing NVT_TYPE_EDID_VTB_EXT_STD, // EDID defined VTB extension standard timing NVT_TYPE_EDID_VTB_EXT_DTD, // EDID defined VTB extension detailed timing NVT_TYPE_EDID_VTB_EXT_CVT, // EDID defined VTB extension cvt timing @@ -298,13 +298,16 @@ NVT_TYPE_HDMI_EXT, // EDID defined HDMI extended resolution timing (UHDTV - 4k, 8k etc.) NVT_TYPE_CUST_AUTO, // Customized timing generated automatically by NVCPL NVT_TYPE_CUST_MANUAL, // Customized timing entered manually by user - NVT_TYPE_CVT_RB_2, // CVT timing with reduced blanking V2 + NVT_TYPE_CVT_RB_2, // = 30 CVT timing with reduced blanking V2 NVT_TYPE_DMT_RB_2, // DMT timing with reduced blanking V2 NVT_TYPE_DISPLAYID_7, // DisplayID 2.0 detailed timing - Type VII NVT_TYPE_DISPLAYID_8, // DisplayID 2.0 enumerated timing - Type VIII NVT_TYPE_DISPLAYID_9, // DisplayID 2.0 formula-based timing - Type IX NVT_TYPE_DISPLAYID_10, // DisplayID 2.0 formula-based timing - Type X NVT_TYPE_CVT_RB_3, // CVT timing with reduced blanking V3 + NVT_TYPE_CTA861_DID_T7, // EDID defined CTA861 DisplayID Type VII timing (in the CTA861 extension) + NVT_TYPE_CTA861_DID_T8, // EDID defined CTA861 DisplayID Type VIII timing (in the CTA861 extension) + NVT_TYPE_CTA861_DID_T10 // EDID defined CTA861 DisplayID Type X timing (in the CTA861 extension) }NVT_TIMING_TYPE; // // 5. the timing sequence number like the TV format and EIA861B predefined timing format @@ -424,7 +427,9 @@ #define NVT_STATUS_DISPLAYID_9N(n) NVT_DEF_TIMING_STATUS(NVT_TYPE_DISPLAYID_9, n) #define NVT_STATUS_DISPLAYID_10N(n) NVT_DEF_TIMING_STATUS(NVT_TYPE_DISPLAYID_10, n) #define NVT_STATUS_HDMI_EXTn(n) NVT_DEF_TIMING_STATUS(NVT_TYPE_HDMI_EXT, n) - +#define NVT_STATUS_CTA861_DID_T7N(n) NVT_DEF_TIMING_STATUS(NVT_TYPE_CTA861_DID_T7, n) +#define NVT_STATUS_CTA861_DID_T8N(n) NVT_DEF_TIMING_STATUS(NVT_TYPE_CTA861_DID_T8, n) +#define NVT_STATUS_CTA861_DID_T10N(n) NVT_DEF_TIMING_STATUS(NVT_TYPE_CTA861_DID_T10, n) //******************************** // CEA/EIA 861 related EDID info @@ -438,6 +443,7 @@ #define NVT_CEA861_REV_E 3 #define NVT_CEA861_REV_F 3 #define NVT_CTA861_REV_G 3 +#define NVT_CTA861_REV_H 3 // // max data after misc/basic_caps in EIA861EXTENSION #define NVT_CEA861_MAX_PAYLOAD 123 @@ -455,7 +461,7 @@ #define NVT_CEA861_SHORT_DESCRIPTOR_TAG_MASK 0xE0 #define NVT_CEA861_SHORT_DESCRIPTOR_TAG_SHIFT 5 // -// the descriptor type tags +// the CTA Tag Codes #define NVT_CEA861_TAG_RSVD 0 // reserved block #define NVT_CEA861_TAG_NONE 0 // reserved block #define NVT_CEA861_TAG_AUDIO 1 // Audio Data Block @@ -469,28 +475,40 @@ // the extended tag codes when NVT_CEA861_TAG_EXTENDED_FLAG #define NVT_CEA861_EXT_TAG_VIDEO_CAP 0 // Video Capability Data Block #define NVT_CEA861_EXT_TAG_VENDOR_SPECIFIC_VIDEO 1 // Vendor-Specific Video Data Block -#define NVT_CEA861_EXT_TAG_VESA_VIDEO_DISPLAY_DEVICE 2 // Reserved for VESA Video Display Device Information Data Block +#define NVT_CEA861_EXT_TAG_VESA_VIDEO_DISPLAY_DEVICE 2 // VESA Video Display Device Information Data Block #define NVT_CEA861_EXT_TAG_VESA_VIDEO 3 // Reserved for VESA Video Data BLock #define NVT_CEA861_EXT_TAG_HDMI_VIDEO 4 // Reserved for HDMI Video Data Block #define NVT_CEA861_EXT_TAG_COLORIMETRY 5 // Colorimetry Data Block #define NVT_CEA861_EXT_TAG_HDR_STATIC_METADATA 6 // HDR Static Metadata Data Block CEA861.3 HDR extension for HDMI 2.0a -#define NVT_CEA861_EXT_TAG_VIDEO_RSVD_MIN 7 // 7...12 : Reserved for video-related blocks -#define NVT_CEA861_EXT_TAG_VIDEO_RSVD_MAX 12 +#define NVT_CTA861_EXT_TAG_HDR_DYNAMIC_METADATA 7 // CTA861-H HDR Dynamic Metadata Data Block +#define NVT_CTA861_EXT_TAG_NATIVE_VIDEO_RESOLUTION 8 // CTA861.6 Native Video Resolution Data Block +#define NVT_CTA861_EXT_TAG_VIDEO_RSVD_MIN 9 // 9...12 : Reserved for video-related blocks +#define NVT_CTA861_EXT_TAG_VIDEO_RSVD_MAX 12 #define NVT_CEA861_EXT_TAG_VIDEO_FORMAT_PREFERENCE 13 // CEA861F Video Format Preference Data Block #define NVT_CEA861_EXT_TAG_YCBCR420_VIDEO 14 // CEA861F YCBCR 4:2:0 Video Data Block #define NVT_CEA861_EXT_TAG_YCBCR420_CAP 15 // CEA861F YCBCR 4:2:0 Capability Map Data Block #define NVT_CEA861_EXT_TAG_MISC_AUDIO 16 // CEA Miscellaneous Audio Fields #define NVT_CEA861_EXT_TAG_VENDOR_SPECIFIC_AUDIO 17 // Vendor-Specific Audio Data Block -#define NVT_CEA861_EXT_TAG_HDMI_AUDIO 18 // Reserved for HDMI Audio Data Block -#define NVT_CEA861_EXT_TAG_AUDIO_RSVD_MIN 19 // 19...31 : Reserved for audio-related blocks -#define NVT_CEA861_EXT_TAG_AUDIO_RSVD_MAX 31 +#define NVT_CTA861_EXT_TAG_HDMI_AUDIO 18 // Reserved for HDMI Audio Data Block +#define NVT_CTA861_EXT_TAG_ROOM_CONFIGURATION 19 // CTA861-H Room Configuration Data Block +#define NVT_CTA861_EXT_TAG_SPEACKER_LOCATION 20 // CTA861-H Speaker Location Data Block +#define NVT_CTA861_EXT_TAG_AUDIO_RSVD_MIN 21 // 21...31 : Reserved for audio-related blocks +#define NVT_CTA861_EXT_TAG_AUDIO_RSVD_MAX 31 #define NVT_CEA861_EXT_TAG_INFOFRAME 32 // Infoframe Data Block -#define NVT_CEA861_EXT_TAG_RSVD_MIN_1 33 // 33...120 : Reserved for general -#define NVT_CEA861_EXT_TAG_RSVD_MAX_1 119 -#define NVT_CEA861_EXT_TAG_HF_EEODB 120 // HDMI Forum Edid Extension Override Data Block +#define NVT_CTA861_EXT_TAG_RSVD 33 // Reserved +#define NVT_CTA861_EXT_TAG_DID_TYPE_VII 34 // DisplayID Type VII Video Timing Data Block +#define NVT_CTA861_EXT_TAG_DID_TYPE_VIII 35 // DisplayID Type VIII Video Timing Data Block +#define NVT_CTA861_EXT_TAG_RSVD_MIN_1 36 // 36...41 : Reserved for general +#define NVT_CTA861_EXT_TAG_RSVD_MAX_1 41 +#define NVT_CTA861_EXT_TAG_DID_TYPE_X 42 // DisplayID Type X Video Timing Data Block +#define NVT_CTA861_EXT_TAG_RSVD_MIN_2 43 // 43...119 : Reserved for general +#define NVT_CTA861_EXT_TAG_RSVD_MAX_2 119 +#define NVT_CTA861_EXT_TAG_HF_EEODB 120 // HDMI Forum Edid Extension Override Data Block #define NVT_CTA861_EXT_TAG_SCDB 121 // 0x79 == Tag for Sink Capability Data Block -#define NVT_CEA861_EXT_TAG_RSVD_MIN_2 122 // 122...255 : Reserved for general -#define NVT_CEA861_EXT_TAG_RSVD_MAX_2 255 +#define NVT_CTA861_EXT_TAG_HDMI_RSVD_MIN 122 // 122...127 : Reserved for HDMI +#define NVT_CTA861_EXT_TAG_HDMI_RSVD_MAX 127 +#define NVT_CTA861_EXT_TAG_RSVD_MIN_3 128 // 128...255 : Reserved for general +#define NVT_CTA861_EXT_TAG_RSVD_MAX_3 255 // //the extended tag payload size; the size includes the extended tag code #define NVT_CEA861_EXT_VIDEO_CAP_SD_SIZE 2 @@ -996,8 +1014,10 @@ #define NVT_CEA861_COLORIMETRY_BT2020YCC 0x40 // BT2020 Y'CbCr capable #define NVT_CEA861_COLORIMETRY_BT2020RGB 0x80 // BT2020 RGB capable // Colorimetry capabilities - byte 4 -#define NVT_CEA861_COLORIMETRY_DCI_P3 0x80 // DCI-P3 - +#define NVT_CEA861_COLORIMETRY_defaultRGB 0x10 // based on the default chromaticity in Basic Display Parameters and Feature Block +#define NVT_CEA861_COLORIMETRY_sRGB 0x20 // IEC 61966-2-1 +#define NVT_CEA861_COLORIMETRY_ICtCp 0x40 // ITU-R BT.2100 ICtCp +#define NVT_CEA861_COLORIMETRY_ST2113RGB 0x80 // SMPTE ST 2113 R'G'B' // // gamut-related metadata capabilities - byte 4 #define NVT_CEA861_GAMUT_METADATA_MASK 0x8F // the colorimetry or gamut-related metadata block mask @@ -1108,8 +1128,96 @@ NvU8 byte1; NvU8 byte2; } NVT_2BYTES; -// -// See CEA-861E, Table 42, 43 Extended Tags; indicates that the corresponding CEA extended data block value is valid, e.g. if colorimetry is set, then NVT_EDID_CEA861_INFO::colorimetry is valid + +#pragma pack(1) +#define NVT_CTA861_DID_MAX_DATA_BLOCK 4 +//*********************** +// DisplayID VII Video Timing Data Block (T7VDB) +//*********************** +#define NVT_CTA861_DID_TYPE7_DESCRIPTORS_MIN 1 +#define NVT_CTA861_DID_TYPE7_DESCRIPTORS_MAX 1 +#define NVT_CTA861_DID_TYPE7_DESCRIPTORS_LENGTH 20 + +typedef struct tagDID_TYPE7_DATA +{ + struct { + NvU8 revision : 3; + NvU8 dsc_pt : 1; + NvU8 t7_m : 3; + NvU8 F37 : 1; + } version; + + NvU8 total_descriptors; + NvU8 payload[29]; // t7_m=0 so only 20byte used +} DID_TYPE7_DATA; + +//*********************** +// DisplayID VIII Video Timing Data Block (T8VDB) +//*********************** +#define NVT_CTA861_DID_TYPE8_ONE_BYTE_DESCRIPTOR 1 +#define NVT_CTA861_DID_TYPE8_TWO_BYTE_DESCRIPTOR 2 +#define NVT_CTA861_DID_TYPE8_DESCRIPTORS_MIN 1 +#define NVT_CTA861_DID_TYPE8_ONE_BYTE_DESCRIPTORS_MAX 28 +#define NVT_CTA861_DID_TYPE8_TWO_BYTE_DESCRIPTORS_MAX 14 + +typedef struct tagDID_TYPE8_DATA +{ + struct { + NvU8 revision : 3; + NvU8 tcs : 1; + NvU8 F34 : 1; + NvU8 t8y420 : 1; + NvU8 code_type : 2; + } version; + + NvU8 total_descriptors; + NvU8 payload[NVT_CTA861_DID_TYPE8_ONE_BYTE_DESCRIPTORS_MAX]; // used one_byte descriptor length +} DID_TYPE8_DATA; + +//*********************** +// DisplayID X Video Timing Data Block (T10VDB) +//*********************** +#define NVT_CTA861_DID_TYPE10_DESCRIPTORS_MIN 1 +#define NVT_CTA861_DID_TYPE10_DESCRIPTORS_MAX 4 + +typedef struct tagDID_TYPE10_DATA +{ + struct { + NvU8 revision : 3; + NvU8 F33 : 1; + NvU8 t10_m : 3; + NvU8 F37 : 1; + } version; + + NvU8 total_descriptors; + NvU8 payload[28]; // given the 7bytes * 4 space +} DID_TYPE10_DATA; + +//*********************** +// Native Video Resolution Data Block (NVRDB) +//*********************** +typedef struct tagNATIVE_VIDEO_RESOLUTION_DATA +{ + NvU8 native_svr; + + struct { + NvU8 img_size : 1; + NvU8 f41 : 1; + NvU8 f42 : 1; + NvU8 f43 : 1; + NvU8 f44 : 1; + NvU8 f45 : 1; + NvU8 f46 : 1; + NvU8 sz_prec : 1; + } option; + + NvU8 image_size[4]; +} NATIVE_VIDEO_RESOLUTION_DATA; + +#pragma pack() + +// See CEA-861E, Table 42, 43 Extended Tags; indicates that the corresponding CEA extended data block value is valid, +// e.g. if colorimetry is set, then NVT_EDID_CEA861_INFO::colorimetry is valid typedef struct tagNVT_VALID_EXTENDED_BLOCKS { NvU32 VCDB : 1; @@ -1125,9 +1233,9 @@ NvU32 HF_EEODB : 1; NvU32 nvda_vsdb : 1; NvU32 msft_vsdb : 1; + NvU32 NVRDB : 1; } NVT_VALID_EXTENDED_BLOCKS; - //************************* // extended data blocks //************************* @@ -1191,9 +1299,12 @@ NVT_5BYTES hdr_static_metadata; // VFPDB extended block. See CEA861-H, Section 7.5.12 Video Format Preference Data Block - NvU8 total_vfpdb; + NvU8 total_svr; NvU8 svr_vfpdb[NVT_CEA861_VFPDB_MAX_DESCRIPTOR]; // svr of preferred video formats + // NVRDB extended block. see CTA861.6, Section 7.5.18 Native Video Resolution Data Block + NATIVE_VIDEO_RESOLUTION_DATA native_video_resolution_db; + // Y420VDB extended block. See CEA861-F, Section 7.5.10 YCBCR 4:2:0 Video Data Block NvU8 total_y420vdb; NvU8 svd_y420vdb[NVT_CEA861_Y420VDB_MAX_DESCRIPTOR]; // svd of video formats that only support YCbCr 4:2:0 @@ -1206,6 +1317,18 @@ NvU32 hfscdbSize; NvU8 hfscdb[NVT_CTA861_EXT_SCDB_PAYLOAD_MAX_LENGTH]; + // DID Type VII Video extended block, see 7.5.17.1 in CTA861-H + NvU8 total_did_type7db; + DID_TYPE7_DATA did_type7_data_block[NVT_CTA861_DID_MAX_DATA_BLOCK]; + + // DID Type VIII Video extended block, see 7.5.17.2 in CTA861-H + NvU8 total_did_type8db; + DID_TYPE8_DATA did_type8_data_block[NVT_CTA861_DID_MAX_DATA_BLOCK]; + + // DID Type X Video extended block, see 7.5.17.3 in CTA861-H + NvU8 total_did_type10db; + DID_TYPE10_DATA did_type10_data_block[NVT_CTA861_DID_MAX_DATA_BLOCK]; + NvU8 hfeeodb; // HDMI Forum Edid Extension Override Data Block. } NVT_EDID_CEA861_INFO; @@ -2117,12 +2240,14 @@ NvU8 cnmvrr : 1; NvU8 cinemaVrr : 1; NvU8 m_delta : 1; + NvU8 qms : 1; NvU8 fapa_end_extended : 1; - NvU8 rsvd : 1; NvU16 vrr_min : 6; NvU16 vrr_max : 10; + NvU8 qms_tfr_min : 1; + NvU8 qms_tfr_max : 1; NvU16 dsc_MaxSlices : 6; NvU16 dsc_MaxPclkPerSliceMHz : 10; @@ -2768,6 +2893,7 @@ NvU16 left_bar; NvU16 right_bar; }NVT_VIDEO_INFOFRAME_CTRL; + // typedef struct tagNVT_AUDIO_INFOFRAME_CTRL { @@ -2782,14 +2908,16 @@ typedef struct tagNVT_VENDOR_SPECIFIC_INFOFRAME_CTRL { - NvU32 Enable; - NvU8 HDMIFormat; - NvU8 HDMI_VIC; - NvU8 ThreeDStruc; - NvU8 ThreeDDetail; - NvU8 MetadataPresent; - NvU8 MetadataType; - NvU8 Metadata[8]; // type determines length + NvU32 Enable; + NvU8 HDMIRevision; + NvU8 HDMIFormat; + NvU8 HDMI_VIC; + NvBool ALLMEnable; + NvU8 ThreeDStruc; + NvU8 ThreeDDetail; + NvU8 MetadataPresent; + NvU8 MetadataType; + NvU8 Metadata[8]; // type determines length } NVT_VENDOR_SPECIFIC_INFOFRAME_CTRL; #define NVT_3D_METADTATA_TYPE_PARALAX 0x00 @@ -2805,8 +2933,17 @@ NvU32 BaseVFP; NvU32 ReducedBlanking; NvU32 BaseRefreshRate; + NvU32 EnableQMS; } NVT_EXTENDED_METADATA_PACKET_INFOFRAME_CTRL; +typedef struct tagNVT_ADAPTIVE_SYNC_SDP_CTRL +{ + NvU32 minVTotal; + NvU32 targetRefreshRate; + NvBool bFixedVTotal; + NvBool bRefreshRateDivider; +}NVT_ADAPTIVE_SYNC_SDP_CTRL; + //*********************************** // the actual Auido/Video Infoframe //*********************************** @@ -2879,7 +3016,6 @@ NvU8 left_bar_high; NvU8 right_bar_low; NvU8 right_bar_high; - }NVT_VIDEO_INFOFRAME; // #define NVT_VIDEO_INFOFRAME_VERSION_1 1 @@ -2913,8 +3049,9 @@ #define NVT_VIDEO_INFOFRAME_BYTE1_Y2Y1Y0_RGB 0 #define NVT_VIDEO_INFOFRAME_BYTE1_Y2Y1Y0_YCbCr422 1 #define NVT_VIDEO_INFOFRAME_BYTE1_Y2Y1Y0_YCbCr444 2 -#define NVT_VIDEO_INFOFRAME_BYTE1_Y2Y1Y0_YCbCr420 3 -#define NVT_VIDEO_INFOFRAME_BYTE1_Y2Y1Y0_FUTURE 3 // nvlEscape still uses this lline 4266 +#define NVT_VIDEO_INFOFRAME_BYTE1_Y2Y1Y0_YCbCr420 3 +#define NVT_VIDEO_INFOFRAME_BYTE1_Y2Y1Y0_FUTURE 3 // nvlEscape still uses this line 4266 +#define NVT_VIDEO_INFOFRAME_BYTE1_Y2Y1Y0_IDODEFINED 7 // CEA-861-F - Unix still used this one #define NVT_VIDEO_INFOFRAME_BYTE1_Y1Y0_MASK 0x60 #define NVT_VIDEO_INFOFRAME_BYTE1_Y1Y0_SHIFT 0x5 @@ -3033,14 +3170,17 @@ #define NVT_VIDEO_INFOFRAME_BYTE5_RESERVED_V1_MASK 0xFF #define NVT_VIDEO_INFOFRAME_BYTE5_RESERVED_V1_SHIFT 0 // -#define NVT_VIDEO_INFOFRAME_BYTE14_RESERVED_V4_MASK 0xF0 -#define NVT_VIDEO_INFOFRAME_BYTE14_RESERVED_V4_SHIFT 4 -#define NVT_VIDEO_INFOFRAME_BYTE14_ACE0_0 0 -#define NVT_VIDEO_INFOFRAME_BYTE14_ACE0_1 1 -// #define NVT_VIDEO_INFOFRAME_BYTE14_RESERVED_MASK 0x0F #define NVT_VIDEO_INFOFRAME_BYTE14_RESERVED_SHIFT 0 // +#define NVT_VIDEO_INFOFRAME_BYTE14_ACE0_3_MASK 0xF0 +#define NVT_VIDEO_INFOFRAME_BYTE14_ACE0_3_SHIFT 4 +#define NVT_VIDEO_INFOFRAME_BYTE14_ACE0_3_P3D65RGB 0 +#define NVT_VIDEO_INFOFRAME_BYTE14_ACE0_3_P3DCIRGB 1 +#define NVT_VIDEO_INFOFRAME_BYTE14_ACE0_3_BT2100_ICtCp 2 +#define NVT_VIDEO_INFOFRAME_BYTE14_ACE0_3_sRGB 3 +#define NVT_VIDEO_INFOFRAME_BYTE14_ACE0_3_defaultRGB 4 +// #define NVT_VIDEO_INFOFRAME_CONTENT_VIDEO 0 #define NVT_VIDEO_INFOFRAME_CONTENT_GRAPHICS 1 #define NVT_VIDEO_INFOFRAME_CONTENT_PHOTO 2 @@ -3438,6 +3578,33 @@ // #define NVT_HDMI_VS_INFOFRAME_VERSION_1 1 +#define NVT_HDMI_VS_HB0_MASK 0xFF +#define NVT_HDMI_VS_HB0_SHIFT 0x00 +#define NVT_HDMI_VS_HB0_VALUE 0x01 + +#define NVT_HDMI_VS_HB1_MASK 0xFF +#define NVT_HDMI_VS_HB1_SHIFT 0x00 +#define NVT_HDMI_VS_HB1_VALUE 0x01 + +#define NVT_HDMI_VS_HB2_MASK 0xFF +#define NVT_HDMI_VS_HB2_SHIFT 0x00 +#define NVT_HDMI_VS_HB2_VALUE 0x06 + +#define NVT_HDMI_VS_BYTE1_OUI_MASK 0xff +#define NVT_HDMI_VS_BYTE1_OUI_SHIFT 0x00 +#define NVT_HDMI_VS_BYTE1_OUI_VER_1_4 0x03 +#define NVT_HDMI_VS_BYTE1_OUI_VER_2_0 0xD8 + +#define NVT_HDMI_VS_BYTE2_OUI_MASK 0xff +#define NVT_HDMI_VS_BYTE2_OUI_SHIFT 0x00 +#define NVT_HDMI_VS_BYTE2_OUI_VER_1_4 0x0C +#define NVT_HDMI_VS_BYTE2_OUI_VER_2_0 0x5D + +#define NVT_HDMI_VS_BYTE3_OUI_MASK 0xff +#define NVT_HDMI_VS_BYTE3_OUI_SHIFT 0x00 +#define NVT_HDMI_VS_BYTE3_OUI_VER_1_4 0x00 +#define NVT_HDMI_VS_BYTE3_OUI_VER_2_0 0xC4 + // #define NVT_HDMI_VS_BYTE4_RSVD_MASK 0x1f #define NVT_HDMI_VS_BYTE4_RSVD_SHIFT 0x00 @@ -3464,6 +3631,10 @@ #define NVT_HDMI_VS_BYTE5_3D_META_PRESENT_SHIFT 0x03 #define NVT_HDMI_VS_BYTE5_HDMI_META_PRESENT_NOTPRES 0x00 // HDMI Metadata is not present #define NVT_HDMI_VS_BYTE5_HDMI_META_PRESENT_PRES 0x01 // HDMI Metadata is present +#define NVT_HDMI_VS_BYTE5_ALLM_MODE_MASK 0x02 // ALLM is field of length 1 bit at Bit Number 1 +#define NVT_HDMI_VS_BYTE5_ALLM_MODE_DIS 0x00 +#define NVT_HDMI_VS_BYTE5_ALLM_MODE_EN 0x01 +#define NVT_HDMI_VS_BYTE5_ALLM_MODE_SHIFT 0x01 // ALLM is byte5 bit position 1, so shift 1 bit #define NVT_HDMI_VS_BYTE5_HDMI_3DS_MASK 0xf0 #define NVT_HDMI_VS_BYTE5_HDMI_3DS_SHIFT 0x04 #define NVT_HDMI_VS_BYTE5_HDMI_3DS_NA 0xfe @@ -3530,83 +3701,184 @@ NVT_EXTENDED_METADATA_PACKET_INFOFRAME_PAYLOAD Data; } NVT_EXTENDED_METADATA_PACKET_INFOFRAME; -#define NVT_HDMI_EMP_BYTE1_RSVD_MASK 0x01 -#define NVT_HDMI_EMP_BYTE1_RSVD_SHIFT 0 +#define NVT_HDMI_EMP_BYTE1_RSVD_MASK 0x01 +#define NVT_HDMI_EMP_BYTE1_RSVD_SHIFT 0 -#define NVT_HDMI_EMP_BYTE1_SYNC_MASK 0x02 -#define NVT_HDMI_EMP_BYTE1_SYNC_SHIFT 1 -#define NVT_HDMI_EMP_BYTE1_SYNC_DISABLE 0 -#define NVT_HDMI_EMP_BYTE1_SYNC_ENABLE 1 - -#define NVT_HDMI_EMP_BYTE1_VFR_MASK 0x04 -#define NVT_HDMI_EMP_BYTE1_VFR_SHIFT 2 -#define NVT_HDMI_EMP_BYTE1_VFR_DISABLE 0 -#define NVT_HDMI_EMP_BYTE1_VFR_ENABLE 1 - -#define NVT_HDMI_EMP_BYTE1_AFR_MASK 0x08 -#define NVT_HDMI_EMP_BYTE1_AFR_SHIFT 3 -#define NVT_HDMI_EMP_BYTE1_AFR_DISABLE 0 -#define NVT_HDMI_EMP_BYTE1_AFR_ENABLE 1 - -#define NVT_HDMI_EMP_BYTE1_DS_TYPE_MASK 0x30 -#define NVT_HDMI_EMP_BYTE1_DS_TYPE_SHIFT 4 -#define NVT_HDMI_EMP_BYTE1_DS_TYPE_PERIODIC_PSEUDO_STATIC 0 -#define NVT_HDMI_EMP_BYTE1_DS_TYPE_PERIODIC_DYNAMIC 1 -#define NVT_HDMI_EMP_BYTE1_DS_TYPE_UNIQUE 2 -#define NVT_HDMI_EMP_BYTE1_DS_TYPE_RSVD 3 - -#define NVT_HDMI_EMP_BYTE1_END_MASK 0x40 -#define NVT_HDMI_EMP_BYTE1_END_SHIFT 6 -#define NVT_HDMI_EMP_BYTE1_END_DISABLE 0 -#define NVT_HDMI_EMP_BYTE1_END_ENABLE 1 - -#define NVT_HDMI_EMP_BYTE1_NEW_MASK 0x80 -#define NVT_HDMI_EMP_BYTE1_NEW_SHIFT 7 -#define NVT_HDMI_EMP_BYTE1_NEW_DISABLE 0 -#define NVT_HDMI_EMP_BYTE1_NEW_ENABLE 1 - -#define NVT_HDMI_EMP_BYTE2_RSVD_MASK 0xff -#define NVT_HDMI_EMP_BYTE2_RSVD_SHIFT 0 - -#define NVT_HDMI_EMP_BYTE3_ORGANIZATION_ID_MASK 0xff -#define NVT_HDMI_EMP_BYTE3_ORGANIZATION_ID_SHIFT 0 -#define NVT_HDMI_EMP_BYTE3_ORGANIZATION_ID_VENDOR_SPECIFIC 0 -#define NVT_HDMI_EMP_BYTE3_ORGANIZATION_ID_SPEC_DEFINED 1 -#define NVT_HDMI_EMP_BYTE3_ORGANIZATION_ID_CTA_DEFINED 2 -#define NVT_HDMI_EMP_BYTE3_ORGANIZATION_ID_VESA_DEFINED 3 - -#define NVT_HDMI_EMP_BYTE4_DATA_SET_TAG_MSB_MASK 0xff -#define NVT_HDMI_EMP_BYTE4_DATA_SET_TAG_MSB_SHIFT 0 - -#define NVT_HDMI_EMP_BYTE5_DATA_SET_TAG_LSB_MASK 0xff -#define NVT_HDMI_EMP_BYTE5_DATA_SET_TAG_LSB_SHIFT 0 - -#define NVT_HDMI_EMP_BYTE6_DATA_SET_LENGTH_MSB_MASK 0xff -#define NVT_HDMI_EMP_BYTE6_DATA_SET_LENGTH_MSB_SHIFT 0 - -#define NVT_HDMI_EMP_BYTE7_DATA_SET_LENGTH_LSB_MASK 0xff -#define NVT_HDMI_EMP_BYTE7_DATA_SET_LENGTH_LSB_SHIFT 0 - -#define NVT_HDMI_EMP_BYTE8_MD0_VRR_EN_MASK 0x01 -#define NVT_HDMI_EMP_BYTE8_MD0_VRR_EN_SHIFT 0 -#define NVT_HDMI_EMP_BYTE8_MD0_VRR_EN_DISABLE 0 -#define NVT_HDMI_EMP_BYTE8_MD0_VRR_EN_ENABLE 1 - -#define NVT_HDMI_EMP_BYTE8_MD1_BASE_VFRONT_MASK 0xff -#define NVT_HDMI_EMP_BYTE8_MD1_BASE_VFRONT_SHIFT 0 - -#define NVT_HDMI_EMP_BYTE8_MD2_RB_MASK 0x04 -#define NVT_HDMI_EMP_BYTE8_MD2_RB_SHIFT 2 -#define NVT_HDMI_EMP_BYTE8_MD2_RB_DISABLE 0 -#define NVT_HDMI_EMP_BYTE8_MD2_RB_ENABLE 1 +#define NVT_HDMI_EMP_BYTE1_SYNC_MASK 0x02 +#define NVT_HDMI_EMP_BYTE1_SYNC_SHIFT 1 +#define NVT_HDMI_EMP_BYTE1_SYNC_DISABLE 0 +#define NVT_HDMI_EMP_BYTE1_SYNC_ENABLE 1 + +#define NVT_HDMI_EMP_BYTE1_VFR_MASK 0x04 +#define NVT_HDMI_EMP_BYTE1_VFR_SHIFT 2 +#define NVT_HDMI_EMP_BYTE1_VFR_DISABLE 0 +#define NVT_HDMI_EMP_BYTE1_VFR_ENABLE 1 + +#define NVT_HDMI_EMP_BYTE1_AFR_MASK 0x08 +#define NVT_HDMI_EMP_BYTE1_AFR_SHIFT 3 +#define NVT_HDMI_EMP_BYTE1_AFR_DISABLE 0 +#define NVT_HDMI_EMP_BYTE1_AFR_ENABLE 1 + +#define NVT_HDMI_EMP_BYTE1_DS_TYPE_MASK 0x30 +#define NVT_HDMI_EMP_BYTE1_DS_TYPE_SHIFT 4 +#define NVT_HDMI_EMP_BYTE1_DS_TYPE_PERIODIC_PSEUDO_STATIC 0 +#define NVT_HDMI_EMP_BYTE1_DS_TYPE_PERIODIC_DYNAMIC 1 +#define NVT_HDMI_EMP_BYTE1_DS_TYPE_UNIQUE 2 +#define NVT_HDMI_EMP_BYTE1_DS_TYPE_RSVD 3 + +#define NVT_HDMI_EMP_BYTE1_END_MASK 0x40 +#define NVT_HDMI_EMP_BYTE1_END_SHIFT 6 +#define NVT_HDMI_EMP_BYTE1_END_DISABLE 0 +#define NVT_HDMI_EMP_BYTE1_END_ENABLE 1 + +#define NVT_HDMI_EMP_BYTE1_NEW_MASK 0x80 +#define NVT_HDMI_EMP_BYTE1_NEW_SHIFT 7 +#define NVT_HDMI_EMP_BYTE1_NEW_DISABLE 0 +#define NVT_HDMI_EMP_BYTE1_NEW_ENABLE 1 + +#define NVT_HDMI_EMP_BYTE2_RSVD_MASK 0xff +#define NVT_HDMI_EMP_BYTE2_RSVD_SHIFT 0 + +#define NVT_HDMI_EMP_BYTE3_ORGANIZATION_ID_MASK 0xff +#define NVT_HDMI_EMP_BYTE3_ORGANIZATION_ID_SHIFT 0 +#define NVT_HDMI_EMP_BYTE3_ORGANIZATION_ID_VENDOR_SPECIFIC 0 +#define NVT_HDMI_EMP_BYTE3_ORGANIZATION_ID_SPEC_DEFINED 1 +#define NVT_HDMI_EMP_BYTE3_ORGANIZATION_ID_CTA_DEFINED 2 +#define NVT_HDMI_EMP_BYTE3_ORGANIZATION_ID_VESA_DEFINED 3 + +#define NVT_HDMI_EMP_BYTE4_DATA_SET_TAG_MSB_MASK 0xff +#define NVT_HDMI_EMP_BYTE4_DATA_SET_TAG_MSB_SHIFT 0 + +#define NVT_HDMI_EMP_BYTE5_DATA_SET_TAG_LSB_MASK 0xff +#define NVT_HDMI_EMP_BYTE5_DATA_SET_TAG_LSB_SHIFT 0 + +#define NVT_HDMI_EMP_BYTE6_DATA_SET_LENGTH_MSB_MASK 0xff +#define NVT_HDMI_EMP_BYTE6_DATA_SET_LENGTH_MSB_SHIFT 0 + +#define NVT_HDMI_EMP_BYTE7_DATA_SET_LENGTH_LSB_MASK 0xff +#define NVT_HDMI_EMP_BYTE7_DATA_SET_LENGTH_LSB_SHIFT 0 + +#define NVT_HDMI_EMP_BYTE8_MD0_VRR_EN_MASK 0x01 +#define NVT_HDMI_EMP_BYTE8_MD0_VRR_EN_SHIFT 0 +#define NVT_HDMI_EMP_BYTE8_MD0_VRR_EN_DISABLE 0 +#define NVT_HDMI_EMP_BYTE8_MD0_VRR_EN_ENABLE 1 +#define NVT_HDMI_EMP_BYTE8_MD0_M_CONST_MASK 0x01 +#define NVT_HDMI_EMP_BYTE8_MD0_M_CONST_SHIFT 1 +#define NVT_HDMI_EMP_BYTE8_MD0_QMS_EN_MASK 0x01 +#define NVT_HDMI_EMP_BYTE8_MD0_QMS_EN_SHIFT 2 +#define NVT_HDMI_EMP_BYTE8_MD0_QMS_EN_DISABLE 0 +#define NVT_HDMI_EMP_BYTE8_MD0_QMS_EN_ENABLE 1 + +#define NVT_HDMI_EMP_BYTE8_MD1_BASE_VFRONT_MASK 0xff +#define NVT_HDMI_EMP_BYTE8_MD1_BASE_VFRONT_SHIFT 0 + +#define NVT_HDMI_EMP_BYTE8_MD2_RB_MASK 0x04 +#define NVT_HDMI_EMP_BYTE8_MD2_RB_SHIFT 2 +#define NVT_HDMI_EMP_BYTE8_MD2_RB_DISABLE 0 +#define NVT_HDMI_EMP_BYTE8_MD2_RB_ENABLE 1 + +#define NVT_HDMI_EMP_BYTE8_MD2_BASE_RR_MSB_MASK 0x03 +#define NVT_HDMI_EMP_BYTE8_MD2_BASE_RR_MSB_SHIFT 0 + +#define NVT_HDMI_EMP_BYTE8_MD3_BASE_RR_LSB_MASK 0xff +#define NVT_HDMI_EMP_BYTE8_MD3_BASE_RR_LSB_SHIFT 0 + +#define NVT_DP_ADAPTIVE_SYNC_SDP_PACKET_TYPE 0x22 +#define NVT_DP_ADAPTIVE_SYNC_SDP_VERSION 0x2 +#define NVT_DP_ADAPTIVE_SYNC_SDP_LENGTH 0x9 +#define NVT_DP_ADAPTIVE_SYNC_SDP_DB0_VARIABLE_FRAME_RATE_MASK 0x3 +#define NVT_DP_ADAPTIVE_SYNC_SDP_DB0_VARIABLE_FRAME_RATE_SHIFT 0 +#define NVT_DP_ADAPTIVE_SYNC_SDP_DB0_VARIABLE_FRAME_RATE_AVT_VARIABLE 0 +#define NVT_DP_ADAPTIVE_SYNC_SDP_DB0_VARIABLE_FRAME_RATE_AVT_FIXED 1 +#define NVT_DP_ADAPTIVE_SYNC_SDP_DB0_VARIABLE_FRAME_RATE_FAVT_TARGET_NOT_REACHED 2 +#define NVT_DP_ADAPTIVE_SYNC_SDP_DB0_VARIABLE_FRAME_RATE_FAVT_TARGET_REACHED 3 + +#define NVT_DP_ADAPTIVE_SYNC_SDP_DB0_DISABLE_PR_ACTIVE_MASK 0x4 +#define NVT_DP_ADAPTIVE_SYNC_SDP_DB0_DISABLE_PR_ACTIVE_SHIFT 2 +#define NVT_DP_ADAPTIVE_SYNC_SDP_DB0_DISABLE_PR_ACTIVE_SOURCE_SINK_SYNC_ENABLED 0 +#define NVT_DP_ADAPTIVE_SYNC_SDP_DB0_DISABLE_PR_ACTIVE_SOURCE_SINK_SYNC_DISABLED 1 + +#define NVT_DP_ADAPTIVE_SYNC_SDP_DB0_DISABLE_PR_ACTIVE_RFB_UPDATE_MASK 0x8 +#define NVT_DP_ADAPTIVE_SYNC_SDP_DB0_DISABLE_PR_ACTIVE_RFB_UPDATE_SHIFT 3 +#define NVT_DP_ADAPTIVE_SYNC_SDP_DB0_DISABLE_PR_ACTIVE_RFB_UPDATE_NO_UPDATE 0 +#define NVT_DP_ADAPTIVE_SYNC_SDP_DB0_DISABLE_PR_ACTIVE_RFB_UPDATE_UPDATE 1 + +#define NVT_DP_ADAPTIVE_SYNC_SDP_DB0_RSVD_MASK 0xf0 +#define NVT_DP_ADAPTIVE_SYNC_SDP_DB0_RSVD_SHIFT 4 + +#define NVT_DP_ADAPTIVE_SYNC_SDP_DB1_MIN_VTOTAL_LSB_MASK 0xff +#define NVT_DP_ADAPTIVE_SYNC_SDP_DB1_MIN_VTOTAL_LSB_SHIFT 0 + +#define NVT_DP_ADAPTIVE_SYNC_SDP_DB2_MIN_VTOTAL_MSB_MASK 0xff +#define NVT_DP_ADAPTIVE_SYNC_SDP_DB2_MIN_VTOTAL_MSB_SHIFT 0 + +#define NVT_DP_ADAPTIVE_SYNC_SDP_DB3_TARGET_RR_LSB_MASK 0xff +#define NVT_DP_ADAPTIVE_SYNC_SDP_DB3_TARGET_RR_LSB_SHIFT 0 + +#define NVT_DP_ADAPTIVE_SYNC_SDP_DB4_TARGET_RR_MSB_MASK 0x01 +#define NVT_DP_ADAPTIVE_SYNC_SDP_DB4_TARGET_RR_MSB_SHIFT 0 + +#define NVT_DP_ADAPTIVE_SYNC_SDP_DB4_RSVD_MASK 0x1c +#define NVT_DP_ADAPTIVE_SYNC_SDP_DB4_RSVD_SHIFT 2 + +#define NVT_DP_ADAPTIVE_SYNC_SDP_DB4_TARGET_RR_DIVIDER_MASK 0x20 +#define NVT_DP_ADAPTIVE_SYNC_SDP_DB4_TARGET_RR_DIVIDER_SHIFT 5 +#define NVT_DP_ADAPTIVE_SYNC_SDP_DB4_TARGET_RR_DIVIDER_DISABLE 0 +#define NVT_DP_ADAPTIVE_SYNC_SDP_DB4_TARGET_RR_DIVIDER_ENABLE 1 + +#define NVT_DP_ADAPTIVE_SYNC_SDP_DB4_SUCCESSIVE_FRAME_INC_MASK 0x40 +#define NVT_DP_ADAPTIVE_SYNC_SDP_DB4_SUCCESSIVE_FRAME_INC_SHIFT 6 +#define NVT_DP_ADAPTIVE_SYNC_SDP_DB4_SUCCESSIVE_FRAME_INC_DISABLE 0 +#define NVT_DP_ADAPTIVE_SYNC_SDP_DB4_SUCCESSIVE_FRAME_INC_ENABLE 1 + +#define NVT_DP_ADAPTIVE_SYNC_SDP_DB4_SUCCESSIVE_FRAME_DEC_MASK 0x80 +#define NVT_DP_ADAPTIVE_SYNC_SDP_DB4_SUCCESSIVE_FRAME_DEC_SHIFT 7 +#define NVT_DP_ADAPTIVE_SYNC_SDP_DB4_SUCCESSIVE_FRAME_DEC_DISABLE 0 +#define NVT_DP_ADAPTIVE_SYNC_SDP_DB4_SUCCESSIVE_FRAME_DEC_ENABLE 1 + +#define NVT_DP_ADAPTIVE_SYNC_SDP_DB5_DURATION_INCREASE_CONSTRAINT_LSB_MASK 0xff +#define NVT_DP_ADAPTIVE_SYNC_SDP_DB5_DURATION_INCREASE_CONSTRAINT_LSB_SHIFT 0 + +#define NVT_DP_ADAPTIVE_SYNC_SDP_DB6_DURATION_INCREASE_CONSTRAINT_MSB_MASK 0xff +#define NVT_DP_ADAPTIVE_SYNC_SDP_DB6_DURATION_INCREASE_CONSTRAINT_MSB_SHIFT 0 + +#define NVT_DP_ADAPTIVE_SYNC_SDP_DB7_PR_COASTING_VTOTAL_LSB_MASK 0xff +#define NVT_DP_ADAPTIVE_SYNC_SDP_DB7_PR_COASTING_VTOTAL_LSB_SHIFT 0 + +#define NVT_DP_ADAPTIVE_SYNC_SDP_DB8_PR_COASTING_VTOTAL_MSB_MASK 0xff +#define NVT_DP_ADAPTIVE_SYNC_SDP_DB8_PR_COASTING_VTOTAL_MSB_SHIFT 0 -#define NVT_HDMI_EMP_BYTE8_MD2_BASE_RR_MSB_MASK 0x03 -#define NVT_HDMI_EMP_BYTE8_MD2_BASE_RR_MSB_SHIFT 0 - -#define NVT_HDMI_EMP_BYTE8_MD3_BASE_RR_LSB_MASK 0xff -#define NVT_HDMI_EMP_BYTE8_MD3_BASE_RR_LSB_SHIFT 0 +#define NVT_DP_ADAPTIVE_SYNC_SDP_DB1_MIN_VTOTAL_BYTE2_MASK 0xff +#define NVT_DP_ADAPTIVE_SYNC_SDP_DB1_MIN_VTOTAL_BYTE2_SHIFT 0 +typedef struct tagNVT_ADAPTIVE_SYNC_SDP_HEADER +{ + NvU8 hb0; + NvU8 type; + NvU8 version; + NvU8 length; +}NVT_ADAPTIVE_SYNC_SDP_HEADER; +typedef struct tagNVT_ADAPTIVE_SYNC_SDP_PAYLOAD +{ + NvU8 db0; // operatingMode + NvU8 db1; // minVTotalLSB + NvU8 db2; // minVTotalMSB + NvU8 db3; // targetRefreshRateLSB + NvU8 db4; // targetRefreshRateMSB, rsvd, targetRRDivider, frameInc/Dec Config + NvU8 db5; // frameDurationIncMs + NvU8 db6; // frameDurationDecreaseMs + NvU8 db7; // coastingVTotalPrLSB + NvU8 db8; // coastingVTotalPrMSB + + NvU8 rsvd[23]; +}NVT_ADAPTIVE_SYNC_SDP_PAYLOAD; + +typedef struct tagADAPTIVE_SYNC_SDP +{ + NVT_ADAPTIVE_SYNC_SDP_HEADER header; + NVT_ADAPTIVE_SYNC_SDP_PAYLOAD payload; +}NVT_ADAPTIVE_SYNC_SDP; // the Vendor-Specific-Data-Block header typedef struct tagNVT_CEA861_VSDB_HEADER @@ -3778,7 +4050,7 @@ NvU8 CNMVRR : 1; NvU8 CinemaVRR : 1; NvU8 M_delta : 1; - NvU8 Rsvd_2 : 1; + NvU8 QMS : 1; NvU8 FAPA_End_Extended : 1; // sixth byte @@ -3791,7 +4063,8 @@ NvU8 DSC_12bpc : 1; NvU8 DSC_16bpc : 1; NvU8 DSC_All_bpp : 1; - NvU8 Rsvd_3 : 2; + NvU8 QMS_TFR_min : 1; + NvU8 QMS_TFR_max : 1; NvU8 DSC_Native_420 : 1; NvU8 DSC_1p2 : 1; // ninth byte @@ -5308,10 +5581,11 @@ #define NVT_FLAG_NV_PREFERRED_TIMING 0x00040000 #define NVT_FLAG_DTD1_PREFERRED_TIMING 0x00080000 #define NVT_FLAG_DISPLAYID_DTD_PREFERRED_TIMING 0x00100000 -#define NVT_FLAG_CEA_PREFERRED_TIMING 0x00200000 +#define NVT_FLAG_CTA_PREFERRED_TIMING 0x00200000 #define NVT_FLAG_DISPLAYID_T7_DSC_PASSTHRU 0x00400000 #define NVT_FLAG_DISPLAYID_2_0_TIMING 0x00800000 // this one for the CTA861 embedded in DID20 #define NVT_FLAG_DISPLAYID_T7_T8_EXPLICT_YUV420 0x01000000 // DID2 E7 spec. supported yuv420 indicated +#define NVT_FLAG_CTA_NATIVE_TIMING 0x02000000 // NVRDB defined #define NVT_FLAG_INTERLACED_MASK (NVT_FLAG_INTERLACED_TIMING | NVT_FLAG_INTERLACED_TIMING2) @@ -5338,8 +5612,10 @@ // DMT timing calculation NVT_STATUS NvTiming_EnumDMT(NvU32 dmtId, NVT_TIMING *pT); +NVT_STATUS NvTiming_EnumStdTwoBytesCode(NvU16 std2ByteCodes, NVT_TIMING *pT); NVT_STATUS NvTiming_CalcDMT(NvU32 width, NvU32 height, NvU32 rr, NvU32 flag, NVT_TIMING *pT); NVT_STATUS NvTiming_CalcDMT_RB(NvU32 width, NvU32 height, NvU32 rr, NvU32 flag, NVT_TIMING *pT); +NVT_STATUS NvTiming_CalcDMT_RB2(NvU32 width, NvU32 height, NvU32 rr, NvU32 flag, NVT_TIMING *pT); // CVT timing calculation NVT_STATUS NvTiming_CalcCVT(NvU32 width, NvU32 height, NvU32 rr, NvU32 flag, NVT_TIMING *pT); @@ -5388,9 +5664,7 @@ NVT_STATUS NvTiming_DisplayID2ValidationDataBlocks(NVT_DISPLAYID_2_0_INFO *pDisplayIdInfo, NvBool bIsStrongValidation); NVT_STATUS NvTiming_Get18ByteLongDescriptorIndex(NVT_EDID_INFO *pEdidInfo, NvU8 tag, NvU32 *dtdIndex); -NVT_STATUS NvTiming_GetProductName(const NVT_EDID_INFO *pEdidInfo, - NvU8 *pProductName, - const NvU32 productNameLength); +NVT_STATUS NvTiming_GetProductName(const NVT_EDID_INFO *pEdidInfo, NvU8 *pProductName, const NvU32 productNameLength); NvU32 NvTiming_CalculateEDIDCRC32(NvU8* pEDIDBuffer, NvU32 edidsize); NvU32 NvTiming_CalculateCommonEDIDCRC32(NvU8* pEDIDBuffer, NvU32 edidVersion); NVT_STATUS NvTiming_CalculateEDIDLimits(NVT_EDID_INFO *pEdidInfo, NVT_EDID_RANGE_LIMIT *pLimit); @@ -5403,17 +5677,18 @@ NvU32 calculateCRC32(NvU8* pBuf, NvU32 bufsize); void patchChecksum(NvU8* pBuf); NvBool isChecksumValid(NvU8* pBuf); - NvU32 RRx1kToPclk (NVT_TIMING *pT); NVT_STATUS NvTiming_ComposeCustTimingString(NVT_TIMING *pT); -// Infoframe composer -NVT_STATUS NvTiming_ConstructVideoInfoframeCtrl(const NVT_TIMING *pTiming, NVT_VIDEO_INFOFRAME_CTRL *pCtrl); -NVT_STATUS NvTiming_ConstructVideoInfoframe(NVT_EDID_INFO *pEdidInfo, NVT_VIDEO_INFOFRAME_CTRL *pCtrl, NVT_VIDEO_INFOFRAME *pContext, NVT_VIDEO_INFOFRAME *p); -NVT_STATUS NvTiming_ConstructAudioInfoframe(NVT_AUDIO_INFOFRAME_CTRL *pCtrl, NVT_AUDIO_INFOFRAME *pContext, NVT_AUDIO_INFOFRAME *p); -NVT_STATUS NvTiming_ConstructVendorSpecificInfoframe(NVT_EDID_INFO *pEdidInfo, NVT_VENDOR_SPECIFIC_INFOFRAME_CTRL *pCtrl, NVT_VENDOR_SPECIFIC_INFOFRAME *p); -NVT_STATUS NvTiming_ConstructExtendedMetadataPacketInfoframe(NVT_EXTENDED_METADATA_PACKET_INFOFRAME_CTRL *pCtrl, NVT_EXTENDED_METADATA_PACKET_INFOFRAME *p); +// Infoframe/SDP composer +NVT_STATUS NvTiming_ConstructVideoInfoframeCtrl(const NVT_TIMING *pTiming, NVT_VIDEO_INFOFRAME_CTRL *pCtrl); +NVT_STATUS NvTiming_ConstructVideoInfoframe(NVT_EDID_INFO *pEdidInfo, NVT_VIDEO_INFOFRAME_CTRL *pCtrl, NVT_VIDEO_INFOFRAME *pContext, NVT_VIDEO_INFOFRAME *p); +NVT_STATUS NvTiming_ConstructAudioInfoframe(NVT_AUDIO_INFOFRAME_CTRL *pCtrl, NVT_AUDIO_INFOFRAME *pContext, NVT_AUDIO_INFOFRAME *p); +NVT_STATUS NvTiming_ConstructVendorSpecificInfoframe(NVT_EDID_INFO *pEdidInfo, NVT_VENDOR_SPECIFIC_INFOFRAME_CTRL *pCtrl, NVT_VENDOR_SPECIFIC_INFOFRAME *p); +NVT_STATUS NvTiming_ConstructExtendedMetadataPacketInfoframe(NVT_EXTENDED_METADATA_PACKET_INFOFRAME_CTRL *pCtrl, NVT_EXTENDED_METADATA_PACKET_INFOFRAME *p); +void NvTiming_ConstructAdaptiveSyncSDP(const NVT_ADAPTIVE_SYNC_SDP_CTRL *pCtrl, NVT_ADAPTIVE_SYNC_SDP *p); + // Get specific timing from parsed EDID NVT_STATUS NvTiming_GetDTD1Timing (NVT_EDID_INFO * pEdidInfo, NVT_TIMING * pT); @@ -5421,15 +5696,22 @@ #define NVT_IS_DTD(d) (NVT_GET_TIMING_STATUS_TYPE((d)) == NVT_TYPE_EDID_DTD) #define NVT_IS_EXT_DTD(d) (NVT_GET_TIMING_STATUS_TYPE((d)) == NVT_TYPE_EDID_EXT_DTD) #define NVT_IS_CTA861(d) (NVT_GET_TIMING_STATUS_TYPE((d)) == NVT_TYPE_EDID_861ST) - -#define NVT_IS_DTD1(d) ((NVT_IS_DTD((d))) && (NVT_GET_TIMING_STATUS_SEQ((d)) == 1)) -#define NVT_IS_DTDn(d, n) ((NVT_IS_DTD((d))) && (NVT_GET_TIMING_STATUS_SEQ((d)) == n)) -#define NVT_IS_EXT_DTDn(d, n) ((NVT_IS_EXT_DTD((d))) && (NVT_GET_TIMING_STATUS_SEQ((d)) == n)) +#define NVT_IS_CTA861_DID_T7(d) (NVT_GET_TIMING_STATUS_TYPE((d)) == NVT_TYPE_CTA861_DID_T7) +#define NVT_IS_CTA861_DID_T8(d) (NVT_GET_TIMING_STATUS_TYPE((d)) == NVT_TYPE_CTA861_DID_T8) +#define NVT_IS_CTA861_DID_T10(d) (NVT_GET_TIMING_STATUS_TYPE((d)) == NVT_TYPE_CTA861_DID_T10) + +#define NVT_IS_DTD1(d) ((NVT_IS_DTD((d))) && (NVT_GET_TIMING_STATUS_SEQ((d)) == 1)) +#define NVT_IS_DTDn(d, n) ((NVT_IS_DTD((d))) && (NVT_GET_TIMING_STATUS_SEQ((d)) == n)) +#define NVT_IS_EXT_DTDn(d, n) ((NVT_IS_EXT_DTD((d))) && (NVT_GET_TIMING_STATUS_SEQ((d)) == n)) +#define NVT_IS_CTA861_DID_T7n(d, n) ((NVT_IS_CTA861_DID_T7((d))) && (NVT_GET_TIMING_STATUS_SEQ((d)) == n)) +#define NVT_IS_CTA861_DID_T8_1(d) ((NVT_IS_CTA861_DID_T8((d))) && (NVT_GET_TIMING_STATUS_SEQ((d)) == 1)) +#define NVT_IS_CTA861_DID_T10n(d, n) ((NVT_IS_CTA861_DID_T10((d))) && (NVT_GET_TIMING_STATUS_SEQ((d)) == n)) #define NVT_DID20_TIMING_IS_CTA861(flag, status) ((NVT_IS_CTA861((status))) && (0 != (NVT_FLAG_DISPLAYID_2_0_TIMING & (flag)))) #define NVT_PREFERRED_TIMING_IS_DTD1(flag, status) ((NVT_IS_DTD1((status))) && (0 != (NVT_FLAG_DTD1_PREFERRED_TIMING & (flag)))) #define NVT_PREFERRED_TIMING_IS_DISPLAYID(flag) (0 != (NVT_FLAG_DISPLAYID_DTD_PREFERRED_TIMING & flag)) -#define NVT_PREFERRED_TIMING_IS_CEA(flag) (0 != (NVT_FLAG_CEA_PREFERRED_TIMING & flag)) +#define NVT_PREFERRED_TIMING_IS_CTA(flag) (0 != (NVT_FLAG_CTA_PREFERRED_TIMING & flag)) +#define NVT_NATIVE_TIMING_IS_CTA(flag) (0 != (NVT_FLAG_CTA_NATIVE_TIMING & flag)) #ifdef __cplusplus } diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/common/modeset/timing/nvtiming_pvt.h nvidia-open-gpu-kernel-modules-535.161.08/src/common/modeset/timing/nvtiming_pvt.h --- nvidia-open-gpu-kernel-modules-525.147.05/src/common/modeset/timing/nvtiming_pvt.h 2023-10-25 20:22:29.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/common/modeset/timing/nvtiming_pvt.h 2024-03-05 22:12:05.000000000 +0000 @@ -1,6 +1,6 @@ //***************************************************************************** // -// SPDX-FileCopyrightText: Copyright (c) 2021 NVIDIA CORPORATION & AFFILIATES. All rights reserved. +// SPDX-FileCopyrightText: Copyright (c) 2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. // SPDX-License-Identifier: MIT // // Permission is hereby granted, free of charge, to any person obtaining a @@ -68,7 +68,7 @@ void parse861ExtDetailedTiming(NvU8 *pEdidExt, NvU8 basicCaps, NVT_EDID_INFO *pInfo); void parse861bShortTiming(NVT_EDID_CEA861_INFO *pExt861, void *pRawInfo, NVT_CTA861_ORIGIN flag); void parse861bShortYuv420Timing(NVT_EDID_CEA861_INFO *pExt861, void *pRawInfo, NVT_CTA861_ORIGIN flag); -void parse861bShortPreferredTiming(NVT_EDID_CEA861_INFO *pExt861, void *pRawInfo, NVT_CTA861_ORIGIN flag); +void parseCta861NativeOrPreferredTiming(NVT_EDID_CEA861_INFO *pExt861, void *pRawInfo, NVT_CTA861_ORIGIN flag); void parseCta861VsdbBlocks(NVT_EDID_CEA861_INFO *pExt861, void *pRawInfo, NVT_CTA861_ORIGIN flag); void parseCta861HfScdb(NVT_EDID_CEA861_INFO *pExt861, void *pRawInfo, NVT_CTA861_ORIGIN flag); void parseCta861HfEeodb(NVT_EDID_CEA861_INFO *pExt861, NvU32 *pTotalEdidExtensions); @@ -81,7 +81,12 @@ void parseCea861HdrStaticMetadataDataBlock(NVT_EDID_CEA861_INFO *pExt861, void *pRawInfo, NVT_CTA861_ORIGIN flag); void parseCea861DvStaticMetadataDataBlock(NVT_EDID_CEA861_INFO *pExt861, void *pRawInfo, NVT_CTA861_ORIGIN flag); void parseCea861Hdr10PlusDataBlock(NVT_EDID_CEA861_INFO *pExt861, void *pRawInfo, NVT_CTA861_ORIGIN flag); +void parseCta861DIDType7VideoTimingDataBlock(NVT_EDID_CEA861_INFO *pExt861, void *pRawInfo); +void parseCta861DIDType8VideoTimingDataBlock(NVT_EDID_CEA861_INFO *pExt861, void *pRawInfo); +void parseCta861DIDType10VideoTimingDataBlock(NVT_EDID_CEA861_INFO *pExt861, void *pRawInfo); NvBool isMatchedCTA861Timing(NVT_EDID_INFO *pInfo, NVT_TIMING *pT); +NvBool isMatchedStandardTiming(NVT_EDID_INFO *pInfo, NVT_TIMING *pT); +NvBool isMatchedEstablishedTiming(NVT_EDID_INFO *pInfo, NVT_TIMING *pT); NvU32 isHdmi3DStereoType(NvU8 StereoStructureType); NvU32 getCEA861TimingAspectRatio(NvU32 vic); void SetActiveSpaceForHDMI3DStereo(const NVT_TIMING *pTiming, NVT_EXT_TIMING *pExtTiming); @@ -95,6 +100,9 @@ NVT_STATUS parseDisplayIdBlock(NvU8* pBlock, NvU8 max_length, NvU8* pLength, NVT_EDID_INFO* pEdidInfo); NVT_STATUS getDisplayId20EDIDExtInfo(NvU8* pDisplayid, NvU32 edidSize, NVT_EDID_INFO* pEdidInfo); NVT_STATUS parseDisplayId20EDIDExtDataBlocks(NvU8* pDataBlock, NvU8 remainSectionLength, NvU8* pCurrentDBLength, NVT_EDID_INFO* pEdidInfo); +NVT_STATUS parseDisplayId20Timing7Descriptor(const void *pDescriptor, NVT_TIMING *pTiming, NvU8 count); +NVT_STATUS parseDisplayId20Timing8Descriptor(const void *pDescriptor, NVT_TIMING *pTiming, NvU8 codeType, NvU8 codeSize, NvU8 index, NvU8 count); +NVT_STATUS parseDisplayId20Timing10Descriptor(const void *pDescriptor, NVT_TIMING *pTiming, NvU8 payloadBytes, NvU8 count); void updateColorFormatForDisplayIdExtnTimings(NVT_EDID_INFO* pInfo, NvU32 timingIdx); void updateColorFormatForDisplayId20ExtnTimings(NVT_EDID_INFO* pInfo, NvU32 timingIdx); NvBool assignNextAvailableDisplayId20Timing(NVT_DISPLAYID_2_0_INFO *pDisplayIdInfo, const NVT_TIMING *pTiming); diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/common/nvlink/inband/interface/nvlink_inband_msg.h nvidia-open-gpu-kernel-modules-535.161.08/src/common/nvlink/inband/interface/nvlink_inband_msg.h --- nvidia-open-gpu-kernel-modules-525.147.05/src/common/nvlink/inband/interface/nvlink_inband_msg.h 2023-10-25 20:20:09.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/common/nvlink/inband/interface/nvlink_inband_msg.h 2024-03-05 22:12:22.000000000 +0000 @@ -76,6 +76,12 @@ /* Add more caps as need in the future */ +#define NVLINK_INBAND_BW_MODE_FULL 0 +#define NVLINK_INBAND_BW_MODE_OFF 1 +#define NVLINK_INBAND_BW_MODE_MIN 2 +#define NVLINK_INBAND_BW_MODE_HALF 3 +#define NVLINK_INBAND_BW_MODE_3QUARTER 4 + typedef struct { NvU64 pciInfo; /* Encoded as Domain(63:32):Bus(15:8):Device(0:7). (debug only) */ @@ -85,7 +91,8 @@ NvU64 enabledLinkMask; /* GPU's currently enabled NvLink mask info. (debug only) */ NvU32 gpuCapMask; /* GPU capabilities, one of NVLINK_INBAND_GPU_PROBE_CAPS */ - NvU8 reserved[32]; /* For future use. Must be initialized to zero */ + NvU8 bwMode; /* NVLink bandwidth mode, one of NVLINK_INBAND_BW_MODE */ + NvU8 reserved[31]; /* For future use. Must be initialized to zero */ } nvlink_inband_gpu_probe_req_t; typedef struct @@ -96,6 +103,9 @@ #define NVLINK_INBAND_FM_CAPS_MC_TEAM_SETUP_V1 NVBIT64(0) #define NVLINK_INBAND_FM_CAPS_MC_TEAM_RELEASE_V1 NVBIT64(1) +#define NVLINK_INBAND_FM_CAPS_BW_MODE_MIN NVBIT64(2) +#define NVLINK_INBAND_FM_CAPS_BW_MODE_HALF NVBIT64(3) +#define NVLINK_INBAND_FM_CAPS_BW_MODE_3QUARTER NVBIT64(4) typedef struct { @@ -108,7 +118,8 @@ NvU64 gpaAddressRange; /* GPU GPA address range */ NvU64 flaAddress; /* FLA starting address for the GPU */ NvU64 flaAddressRange; /* GPU FLA address range */ - NvU8 reserved[32]; /* For future use. Must be initialized to zero */ + NvU32 linkMaskToBeReduced; /* bit mask of unused NVLink ports for P2P */ + NvU8 reserved[28]; /* For future use. Must be initialized to zero */ } nvlink_inband_gpu_probe_rsp_t; typedef struct diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/common/nvlink/interface/nvlink.h nvidia-open-gpu-kernel-modules-535.161.08/src/common/nvlink/interface/nvlink.h --- nvidia-open-gpu-kernel-modules-525.147.05/src/common/nvlink/interface/nvlink.h 2023-10-25 20:20:09.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/common/nvlink/interface/nvlink.h 2024-03-05 22:12:22.000000000 +0000 @@ -1,24 +1,25 @@ -/******************************************************************************* - Copyright (c) 2014-2023 NVidia Corporation - - Permission is hereby granted, free of charge, to any person obtaining a copy - of this software and associated documentation files (the "Software"), to - deal in the Software without restriction, including without limitation the - rights to use, copy, modify, merge, publish, distribute, sublicense, and/or - sell copies of the Software, and to permit persons to whom the Software is - furnished to do so, subject to the following conditions: - - The above copyright notice and this permission notice shall be - included in all copies or substantial portions of the Software. - - THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER - DEALINGS IN THE SOFTWARE. -*******************************************************************************/ +/* + * SPDX-FileCopyrightText: Copyright (c) 2014-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ // // nvlink.h @@ -473,11 +474,6 @@ /* * Set the training state for the given link as non-ALI or ALI - */ -NvlStatus nvlink_lib_is_link_using_ALI(nvlink_link *link, NvBool *usingALI); - -/* - * Set the training state for the given link as non-ALI or ALI */ NvlStatus nvlink_lib_link_set_training_mode(nvlink_link *link, NvBool enableALI); diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/common/nvlink/interface/nvlink_lib_ctrl.h nvidia-open-gpu-kernel-modules-535.161.08/src/common/nvlink/interface/nvlink_lib_ctrl.h --- nvidia-open-gpu-kernel-modules-525.147.05/src/common/nvlink/interface/nvlink_lib_ctrl.h 2023-10-25 20:20:09.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/common/nvlink/interface/nvlink_lib_ctrl.h 2024-03-05 22:12:23.000000000 +0000 @@ -1,24 +1,25 @@ -/******************************************************************************* - Copyright (c) 2016-2022 NVidia Corporation - - Permission is hereby granted, free of charge, to any person obtaining a copy - of this software and associated documentation files (the "Software"), to - deal in the Software without restriction, including without limitation the - rights to use, copy, modify, merge, publish, distribute, sublicense, and/or - sell copies of the Software, and to permit persons to whom the Software is - furnished to do so, subject to the following conditions: - - The above copyright notice and this permission notice shall be - included in all copies or substantial portions of the Software. - - THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER - DEALINGS IN THE SOFTWARE. -*******************************************************************************/ +/* + * SPDX-FileCopyrightText: Copyright (c) 2016-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ #ifndef _NVLINK_LIB_CTRL_H_ #define _NVLINK_LIB_CTRL_H_ @@ -154,7 +155,7 @@ nvlink_link_mode_enable_pm, nvlink_link_mode_disable_pm, nvlink_link_mode_traffic_setup, - nvlink_link_mode_contain + nvlink_link_mode_contain, } nvlink_link_mode; /* sublink tx modes */ @@ -587,6 +588,8 @@ nvlink_train_conn_to_off, nvlink_train_conn_active_to_swcfg, nvlink_train_conn_swcfg_to_off, + nvlink_train_conn_off_to_active_ali_non_blocking, + nvlink_train_conn_off_to_active_ali_blocking, /* See enum modification guidelines at the top of this file */ } nvlink_conn_train_type; @@ -784,7 +787,10 @@ * * NVLink 3.0 onwards, connection detection is handled by Minion. After INITNEGOTIATE * completed, this interface needs to be queried to retrieve the local/remote SIDs - * and the local/remote link number of all links associated with a device + * and the local/remote link number of all links associated with a device. + * + * On NVLink 4.0 this needs to be queried after all links in the system have been + * trained. * * Parameters: * devInfo [IN] @@ -1079,7 +1085,7 @@ /* * CTRL_NVLINK_GET_DEVICE_LINK_STATES * - * Returns the link state of all enabled links on a given device. + * Returns the link state of all links on a given device. * * Parameters: * devInfo [IN] @@ -1096,7 +1102,7 @@ * will show the states as INVALID. * * endStatesCount [OUT] - * count of valid entries into the endStates array + * count of total entries in the endStates array * */ typedef struct @@ -1107,7 +1113,7 @@ /* output parameters */ NvlStatus status; - nvlink_link_state endStates[NVLINK_MAX_NVLINK_ENDPOINTS]; + nvlink_link_state endStates[NVLINK_MAX_DEVICE_CONN]; NvU32 endStatesCount; } nvlink_get_device_link_states; diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/common/nvlink/interface/nvlink_lock.h nvidia-open-gpu-kernel-modules-535.161.08/src/common/nvlink/interface/nvlink_lock.h --- nvidia-open-gpu-kernel-modules-525.147.05/src/common/nvlink/interface/nvlink_lock.h 2023-10-25 20:20:09.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/common/nvlink/interface/nvlink_lock.h 2024-03-05 22:12:23.000000000 +0000 @@ -1,21 +1,25 @@ -/******************************************************************************* - Copyright (c) 2020 NVidia Corporation - Permission is hereby granted, free of charge, to any person obtaining a copy - of this software and associated documentation files (the "Software"), to - deal in the Software without restriction, including without limitation the - rights to use, copy, modify, merge, publish, distribute, sublicense, and/or - sell copies of the Software, and to permit persons to whom the Software is - furnished to do so, subject to the following conditions: - The above copyright notice and this permission notice shall be - included in all copies or substantial portions of the Software. - THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER - DEALINGS IN THE SOFTWARE. -*******************************************************************************/ +/* + * SPDX-FileCopyrightText: Copyright (c) 2020 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ #ifndef _NVLINK_LOCK_H_ diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/common/nvlink/interface/nvlink_os.h nvidia-open-gpu-kernel-modules-535.161.08/src/common/nvlink/interface/nvlink_os.h --- nvidia-open-gpu-kernel-modules-525.147.05/src/common/nvlink/interface/nvlink_os.h 2023-10-25 20:20:09.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/common/nvlink/interface/nvlink_os.h 2024-03-05 22:12:23.000000000 +0000 @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 2019 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2019-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/common/nvlink/kernel/nvlink/core/nvlink_ioctl.c nvidia-open-gpu-kernel-modules-535.161.08/src/common/nvlink/kernel/nvlink/core/nvlink_ioctl.c --- nvidia-open-gpu-kernel-modules-525.147.05/src/common/nvlink/kernel/nvlink/core/nvlink_ioctl.c 2023-10-25 20:20:10.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/common/nvlink/kernel/nvlink/core/nvlink_ioctl.c 2024-03-05 22:12:24.000000000 +0000 @@ -1,5 +1,5 @@ /******************************************************************************* - Copyright (c) 2017-2020 NVidia Corporation + Copyright (c) 2017-2023 NVidia Corporation Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation files (the "Software"), to @@ -297,7 +297,6 @@ NvU64 state = NVLINK_LINKSTATE_INVALID; NvU64 dlState = NVLINK_LINKSTATE_INVALID; NvU64 tlState = NVLINK_LINKSTATE_INVALID; - if ((link == NULL) || (linkState == NULL)) { return; @@ -309,7 +308,7 @@ // unless the corresponding HAL/Callbacks are not registered, which can // happen during early development cycle. Adding an assert to catch that // in debug builds. - // + // status = link->link_handlers->get_dl_link_mode(link, &dlState); nvlink_assert(status == NVL_SUCCESS); diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/common/nvlink/kernel/nvlink/core/nvlink_link_mgmt.c nvidia-open-gpu-kernel-modules-535.161.08/src/common/nvlink/kernel/nvlink/core/nvlink_link_mgmt.c --- nvidia-open-gpu-kernel-modules-525.147.05/src/common/nvlink/kernel/nvlink/core/nvlink_link_mgmt.c 2023-10-25 20:20:10.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/common/nvlink/kernel/nvlink/core/nvlink_link_mgmt.c 2024-03-05 22:12:24.000000000 +0000 @@ -83,7 +83,18 @@ return NV_FALSE; } - if (crntTlLinkMode == NVLINK_LINKSTATE_HS) + status = link->link_handlers->get_dl_link_mode(link, &crntDlLinkMode); + if (status != NVL_SUCCESS) + { + NVLINK_PRINT((DBG_MODULE_NVLINK_CORE, NVLINK_DBG_LEVEL_ERRORS, + "%s: Unable to get DL link mode for %s:%s\n", + __FUNCTION__, link->dev->deviceName, link->linkName)); + return NV_FALSE; + } + + if (crntTlLinkMode == NVLINK_LINKSTATE_HS && + (crntDlLinkMode == NVLINK_LINKSTATE_HS || + crntDlLinkMode == NVLINK_LINKSTATE_SLEEP)) { return NV_TRUE; } diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/common/nvlink/kernel/nvlink/core/nvlink_shutdown.c nvidia-open-gpu-kernel-modules-535.161.08/src/common/nvlink/kernel/nvlink/core/nvlink_shutdown.c --- nvidia-open-gpu-kernel-modules-525.147.05/src/common/nvlink/kernel/nvlink/core/nvlink_shutdown.c 2023-10-25 20:20:10.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/common/nvlink/kernel/nvlink/core/nvlink_shutdown.c 2024-03-05 22:12:24.000000000 +0000 @@ -1,24 +1,25 @@ -/******************************************************************************* - Copyright (c) 2019-2022 NVidia Corporation - - Permission is hereby granted, free of charge, to any person obtaining a copy - of this software and associated documentation files (the "Software"), to - deal in the Software without restriction, including without limitation the - rights to use, copy, modify, merge, publish, distribute, sublicense, and/or - sell copies of the Software, and to permit persons to whom the Software is - furnished to do so, subject to the following conditions: - - The above copyright notice and this permission notice shall be - included in all copies or substantial portions of the Software. - - THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER - DEALINGS IN THE SOFTWARE. -*******************************************************************************/ +/* + * SPDX-FileCopyrightText: Copyright (c) 2019-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ #include "nvlink.h" #include "nvlink_export.h" @@ -841,7 +842,7 @@ { if (conns[i] == NULL) continue; - + // // Reset both ends of this connection. // This path should enable/init those link endpoints as well. @@ -995,12 +996,9 @@ conn = NULL; nvlink_core_get_intranode_conn(links[j], &(conn)); if (conn == NULL || - _nvlink_core_check_if_conn_in_array(visitedConns, connCount, conn) || + _nvlink_core_check_if_conn_in_array(visitedConns, connCount, conn) || (conn->end0 == NULL || conn->end1 == NULL)) { - NVLINK_PRINT((DBG_MODULE_NVLINK_CORE, NVLINK_DBG_LEVEL_ERRORS, - "%s: AC debug -- conn gotten: 0x%x\n", - __FUNCTION__, conn)); continue; } else if(nvlink_core_check_intranode_conn_state(conn, NVLINK_LINKSTATE_OFF) == diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/common/nvlink/kernel/nvlink/core/nvlink_training.c nvidia-open-gpu-kernel-modules-535.161.08/src/common/nvlink/kernel/nvlink/core/nvlink_training.c --- nvidia-open-gpu-kernel-modules-525.147.05/src/common/nvlink/kernel/nvlink/core/nvlink_training.c 2023-10-25 20:20:10.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/common/nvlink/kernel/nvlink/core/nvlink_training.c 2024-03-05 22:12:24.000000000 +0000 @@ -934,6 +934,53 @@ /** * Train intranode connections associated with a list of links to HS + * using non-ALI sequence + * + * @param[in] links Array of links to train + * @param[in] numLinks Number of links in the array + * + * return NVL_SUCCESS if the connections train successfully + */ +NvlStatus +nvlink_core_train_intranode_conns_from_off_to_active_ALI +( + nvlink_link **pLinks, + NvU32 numLinks +) +{ + NvlStatus status = NVL_SUCCESS; + NvlStatus returnStatus = NVL_SUCCESS; + NvU32 i; + + if ((pLinks == NULL) || (numLinks == 0)) + { + NVLINK_PRINT((DBG_MODULE_NVLINK_CORE, NVLINK_DBG_LEVEL_ERRORS, + "%s: No links to train to ACTIVE\n", + __FUNCTION__)); + + return NVL_ERR_GENERIC; + } + + for (i = 0; i < numLinks; ++i) + { + if (pLinks[i] == NULL) + continue; + + status = pLinks[i]->link_handlers->ali_training(pLinks[i]); + if (status != NVL_SUCCESS) + { + NVLINK_PRINT((DBG_MODULE_NVLINK_CORE, NVLINK_DBG_LEVEL_ERRORS, + "%s: failed to send ALI link training on link 0x%x\n", + __FUNCTION__, pLinks[i]->linkNumber)); + returnStatus = status; + } + } + + return returnStatus; +} + +/** + * Train intranode connections associated with a list of links to HS * using ALT sequence * * @param[in] conns Array of connections to train diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/common/nvlink/kernel/nvlink/interface/nvlink_ioctl_entry.c nvidia-open-gpu-kernel-modules-535.161.08/src/common/nvlink/kernel/nvlink/interface/nvlink_ioctl_entry.c --- nvidia-open-gpu-kernel-modules-525.147.05/src/common/nvlink/kernel/nvlink/interface/nvlink_ioctl_entry.c 2023-10-25 20:20:11.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/common/nvlink/kernel/nvlink/interface/nvlink_ioctl_entry.c 2024-03-05 22:12:24.000000000 +0000 @@ -1,24 +1,25 @@ -/******************************************************************************* - Copyright (c) 2017-2020 NVidia Corporation - - Permission is hereby granted, free of charge, to any person obtaining a copy - of this software and associated documentation files (the "Software"), to - deal in the Software without restriction, including without limitation the - rights to use, copy, modify, merge, publish, distribute, sublicense, and/or - sell copies of the Software, and to permit persons to whom the Software is - furnished to do so, subject to the following conditions: - - The above copyright notice and this permission notice shall be - included in all copies or substantial portions of the Software. - - THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER - DEALINGS IN THE SOFTWARE. -*******************************************************************************/ +/* + * SPDX-FileCopyrightText: Copyright (c) 2017-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ #include "nvlink.h" #include "nvVer.h" @@ -1445,6 +1446,54 @@ } /** + * Perform peer link discovery + * + * @param[in] readParams IOCTL params + * + * return NvlStatus + */ +static NvlStatus +_nvlink_lib_ctrl_device_discover_peer_link +( + nvlink_link *link +) +{ + NvlStatus status = NVL_SUCCESS; + + // + // If the link succeeds rxDet(link is in HS, SAFE, or SLEEP mode) then go through and find its + // peer link. What is important is not actually finding the link, but making sure the corelib + // goes through the discovery process and has endpoints cache the remote information in the corelib + // such that FM or endpoints can query the corelib for the topology of the system. + // + NvU64 linkMode = NVLINK_LINKSTATE_OFF; + status = link->link_handlers->get_dl_link_mode(link, &linkMode); + if (status != NVL_SUCCESS) + { + NVLINK_PRINT((DBG_MODULE_NVLINK_CORE, NVLINK_DBG_LEVEL_ERRORS, + "%s: Unable to get link mode for %s:%s\n", + __FUNCTION__, link->dev->deviceName, link->linkName)); + return status; + } + + if ((linkMode == NVLINK_LINKSTATE_SAFE) || + (linkMode == NVLINK_LINKSTATE_HS) || + (linkMode == NVLINK_LINKSTATE_SLEEP)) + { + nvlink_link *remoteLink = NULL; + nvlink_core_discover_and_get_remote_end(link, &remoteLink, 0); + if (remoteLink == NULL) + { + NVLINK_PRINT((DBG_MODULE_NVLINK_CORE, NVLINK_DBG_LEVEL_INFO, + "%s: link 0x%x: couldn't find link pair! Possible that other device queries need to finish before there is a found connection in the corelib\n", + __FUNCTION__, link->linkNumber)); + } + } + + return NVL_SUCCESS; +} + +/** * Read the SIDs for the the local and remote device * * @param[in] readParams IOCTL params @@ -1557,6 +1606,19 @@ for (i = 0; i < numLinks; i++) { + // ALI specific handling to update corelib structures and verify link status + if (dev->enableALI) + { + status = _nvlink_lib_ctrl_device_discover_peer_link(links[i]); + if (status != NVL_SUCCESS) + { + // Release the per-link locks and free links + nvlink_lib_link_locks_release(links, numLinks); + nvlink_free((void *)links); + return status; + } + } + // Fill-up the local/remote link numbers and SIDs readParams->sidInfo[numEntries].localLinkSid = links[i]->localSid; readParams->sidInfo[numEntries].remoteLinkSid = links[i]->remoteSid; @@ -1685,6 +1747,22 @@ continue; } + // ALI specific handling to update corelib structures and verify link status + if (dev->enableALI) + { + status = _nvlink_lib_ctrl_device_discover_peer_link(link); + if (status != NVL_SUCCESS) + { + // Release the per-link locks + nvlink_lib_link_locks_release(links, numLinks); + + // Release the top-level lock + nvlink_lib_top_lock_release(); + nvlink_free((void *)links); + return status; + } + } + writeToken = nvlink_core_get_link_discovery_token(link); if ((link->version < NVLINK_DEVICE_VERSION_30) || @@ -2006,6 +2084,7 @@ nvlink_intranode_conn *conn = NULL; NvlStatus status = NVL_SUCCESS; NvU32 count; + NvU32 i; // make sure that this call is for single node systems if (trainParams->srcEndPoint.nodeId != trainParams->dstEndPoint.nodeId) @@ -2174,6 +2253,44 @@ } break; } + case nvlink_train_conn_off_to_active_ali_non_blocking: + case nvlink_train_conn_off_to_active_ali_blocking: + { + if (srcLink->version >= NVLINK_DEVICE_VERSION_40 && + srcLink->dev->enableALI) + { + status = nvlink_core_train_intranode_conns_from_off_to_active_ALI(initLinks, count); + + if (trainParams->trainTo == nvlink_train_conn_off_to_active_ali_blocking) + { + NvU32 timeout = NVLINK_TRANSITION_HS_TIMEOUT; + do + { + nvlink_sleep(1); + status = nvlink_core_train_check_link_ready_ALI(initLinks, count); + if (status == NVL_SUCCESS) + { + break; + } + + timeout--; + } while(timeout > 0); + + if (status == NVL_SUCCESS) + { + for ( i = 0; i < count; ++i) + { + // + // NVLINK_LINKSTATE_TRAFFIC_SETUP will make sure a request to active completes before + // setting buffer ready so use the internal check to see if the request for ALI completed + // + (void)initLinks[i]->link_handlers->set_dl_link_mode(initLinks[i], NVLINK_LINKSTATE_TRAFFIC_SETUP, 0); + } + } + } + } + break; + } default: { status = NVL_BAD_ARGS; @@ -2476,6 +2593,45 @@ } break; } + case nvlink_train_conn_off_to_active_ali_non_blocking: + case nvlink_train_conn_off_to_active_ali_blocking: + { + if (srcLink->version >= NVLINK_DEVICE_VERSION_40 && + srcLink->dev->enableALI) + { + status = nvlink_core_train_intranode_conns_from_off_to_active_ALI( + initLinks, count); + + if (trainParams->trainTo == nvlink_train_conn_off_to_active_ali_blocking) + { + NvU32 timeout = NVLINK_TRANSITION_HS_TIMEOUT; + do + { + nvlink_sleep(1); + status = nvlink_core_train_check_link_ready_ALI(initLinks, count); + if (status == NVL_SUCCESS) + { + break; + } + + timeout--; + } while(timeout > 0); + + if (status == NVL_SUCCESS) + { + for ( i = 0; i < count; ++i) + { + // + // NVLINK_LINKSTATE_TRAFFIC_SETUP will make sure a request to active completes before + // setting buffer ready so use the internal check to see if the request for ALI completed + // + (void)initLinks[i]->link_handlers->set_dl_link_mode(initLinks[i], NVLINK_LINKSTATE_TRAFFIC_SETUP, 0); + } + } + } + } + break; + } default: { status = NVL_BAD_ARGS; @@ -3397,6 +3553,8 @@ NvU32 numLinks = 0; NvU32 i = 0; + ct_assert(NVLINK_MAX_SYSTEM_LINK_NUM == NVLINK_MAX_NVLINK_ENDPOINTS); + nvlink_link **links = (nvlink_link **)nvlink_malloc( sizeof(nvlink_link *) * NVLINK_MAX_SYSTEM_LINK_NUM); if (links == NULL) @@ -3531,16 +3689,17 @@ NvlStatus status = NVL_SUCCESS; NvU32 numLinks = 0; NvU32 i = 0; - - ct_assert(NVLINK_MAX_SYSTEM_LINK_NUM == NVLINK_MAX_NVLINK_ENDPOINTS); + NvU8 linkNumber; nvlink_link **links = (nvlink_link **)nvlink_malloc( - sizeof(nvlink_link *) * NVLINK_MAX_SYSTEM_LINK_NUM); + sizeof(nvlink_link *) * NVLINK_MAX_DEVICE_CONN); if (links == NULL) { return NVL_NO_MEM; } + nvlink_memset(params->endStates, 0x0, sizeof(params->endStates)); + // Acquire the top-level lock status = nvlink_lib_top_lock_acquire(); if (status != NVL_SUCCESS) @@ -3573,10 +3732,10 @@ // FOR_EACH_LINK_REGISTERED(endpoint, dev, node) { - if (numLinks >= NVLINK_MAX_SYSTEM_LINK_NUM) + if (numLinks >= NVLINK_MAX_DEVICE_CONN) { NVLINK_PRINT((DBG_MODULE_NVLINK_CORE, NVLINK_DBG_LEVEL_ERRORS, - "%s: numLinks >= NVLINK_MAX_SYSTEM_LINK_NUM", + "%s: numLinks >= NVLINK_MAX_DEVICE_CONN", __FUNCTION__)); nvlink_assert(0); @@ -3614,19 +3773,20 @@ for (i = 0; i < numLinks; ++i) { - // Check RxDet status of the link and repopulate as necessary - nvlink_core_get_rx_detect(&links[i], 1, 0); + linkNumber = links[i]->linkNumber; + + nvlink_assert(linkNumber < NVLINK_MAX_DEVICE_CONN); // Get the endpoint states of the link - nvlink_core_get_endpoint_state(links[i], &(params->endStates[i])); + nvlink_core_get_endpoint_state(links[i], &(params->endStates[linkNumber])); NVLINK_PRINT((DBG_MODULE_NVLINK_CORE, NVLINK_DBG_LEVEL_INFO, - "%s: link 0x%x -- rxDet status 0x%x, linkMode 0x%x,\n", - __FUNCTION__, i, links[i]->bRxDetected, params->endStates[i].linkMode)); - + "%s: link 0x%x -- linkMode 0x%x,\n", + __FUNCTION__, linkNumber, params->endStates[linkNumber].linkMode)); } - params->endStatesCount = numLinks; + // This is done to preserve client behavior that uses endStatesCount to iterate across endStates array + params->endStatesCount = NVLINK_MAX_DEVICE_CONN; // Release the per-link locks nvlink_lib_link_locks_release(links, numLinks); diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/common/nvlink/kernel/nvlink/interface/nvlink_kern_link_mgmt_entry.c nvidia-open-gpu-kernel-modules-535.161.08/src/common/nvlink/kernel/nvlink/interface/nvlink_kern_link_mgmt_entry.c --- nvidia-open-gpu-kernel-modules-525.147.05/src/common/nvlink/kernel/nvlink/interface/nvlink_kern_link_mgmt_entry.c 2023-10-25 20:20:11.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/common/nvlink/kernel/nvlink/interface/nvlink_kern_link_mgmt_entry.c 2024-03-05 22:12:24.000000000 +0000 @@ -384,70 +384,3 @@ return status; } - -/** - * Get whether the link is using ALI for training. - * - * @param[in] link NVLink Link pointer - * @param[out] usingAli Boolean on whether ALI training is being used - * - * return NVL_SUCCESS if getting the variable is successful - */ -NvlStatus -nvlink_lib_is_link_using_ALI -( - nvlink_link *link, - NvBool *usingALI -) -{ - NvlStatus status = NVL_SUCCESS; - usingALI = NV_FALSE; - - if (link == NULL) - { - NVLINK_PRINT((DBG_MODULE_NVLINK_CORE, NVLINK_DBG_LEVEL_ERRORS, - "%s: Bad link pointer specified.\n", - __FUNCTION__)); - return NVL_ERR_GENERIC; - } - - // Acquire the top-level lock - status = nvlink_lib_top_lock_acquire(); - if (status != NVL_SUCCESS) - { - NVLINK_PRINT((DBG_MODULE_NVLINK_CORE, NVLINK_DBG_LEVEL_ERRORS, - "%s: Failed to acquire top-level lock\n", - __FUNCTION__)); - - return status; - } - - // Acquire the per-link lock - status = nvlink_lib_link_locks_acquire(&link, 1); - if (status != NVL_SUCCESS) - { - NVLINK_PRINT((DBG_MODULE_NVLINK_CORE, NVLINK_DBG_LEVEL_ERRORS, - "%s: Failed to acquire per-link locks\n", - __FUNCTION__)); - - // Release the top-level lock - nvlink_lib_top_lock_release(); - - return status; - } - - // - // All the required per-link locks are successfully acquired - // The connection list traversal is also complete now - // Release the top level-lock - // - nvlink_lib_top_lock_release(); - - // TODO: Add Getter for per-link enableALI state variable - - // Release the per-link lock - nvlink_lib_link_locks_release(&link, 1); - - return status; -} - diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/common/nvlink/kernel/nvlink/nvlink_helper.h nvidia-open-gpu-kernel-modules-535.161.08/src/common/nvlink/kernel/nvlink/nvlink_helper.h --- nvidia-open-gpu-kernel-modules-525.147.05/src/common/nvlink/kernel/nvlink/nvlink_helper.h 2023-10-25 20:20:11.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/common/nvlink/kernel/nvlink/nvlink_helper.h 2024-03-05 22:12:25.000000000 +0000 @@ -139,6 +139,12 @@ */ NvlStatus nvlink_core_initnegotiate(nvlink_link **links, NvU32 numLinks, NvU32 flags); +/* + * Initialize all the endpoints from OFF to ACTIVE state for ALI sequence + * Used for nvlink 4.0+ + */ +NvlStatus nvlink_core_train_intranode_conns_from_off_to_active_ALI(nvlink_link **pLinks, + NvU32 numLinks); /************************************************************************************************/ /*************************** NVLink topology discovery functions ********************************/ /************************************************************************************************/ @@ -227,6 +233,12 @@ NvlStatus nvlink_core_train_check_link_ready_ALI(nvlink_link **links, NvU32 linkCount); +/** + * Initiate ALI training for nvlink 4.0+ + */ +NvlStatus nvlink_core_train_from_off_to_active_ALI(nvlink_link **links, + NvU32 linkCount); + /************************************************************************************************/ /********************************** NVLink shutdown functions ***********************************/ diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/common/nvlink/kernel/nvlink/nvlink_lib_mgmt.c nvidia-open-gpu-kernel-modules-535.161.08/src/common/nvlink/kernel/nvlink/nvlink_lib_mgmt.c --- nvidia-open-gpu-kernel-modules-525.147.05/src/common/nvlink/kernel/nvlink/nvlink_lib_mgmt.c 2023-10-25 20:20:11.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/common/nvlink/kernel/nvlink/nvlink_lib_mgmt.c 2024-03-05 22:12:25.000000000 +0000 @@ -171,6 +171,7 @@ { NvlStatus lock_status = NVL_SUCCESS; nvlink_device *dev = NULL; + NvBool bIsReducedConfg = NV_FALSE; // Acquire top-level lock lock_status = nvlink_lib_top_lock_acquire(); @@ -187,16 +188,15 @@ { if (dev->bReducedNvlinkConfig == NV_TRUE) { - // Release top-level lock - nvlink_lib_top_lock_release(); - return NV_TRUE; + bIsReducedConfg = NV_TRUE; + break; } } // Release top-level lock nvlink_lib_top_lock_release(); - return NV_FALSE; + return bIsReducedConfg; } /* diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/common/nvlink/kernel/nvlink/nvlink_lock.c nvidia-open-gpu-kernel-modules-535.161.08/src/common/nvlink/kernel/nvlink/nvlink_lock.c --- nvidia-open-gpu-kernel-modules-525.147.05/src/common/nvlink/kernel/nvlink/nvlink_lock.c 2023-10-25 20:20:11.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/common/nvlink/kernel/nvlink/nvlink_lock.c 2024-03-05 22:12:25.000000000 +0000 @@ -1,5 +1,5 @@ /******************************************************************************* - Copyright (c) 2020 NVidia Corporation + Copyright (c) 2020-2023 NVidia Corporation Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation files (the "Software"), to deal in the Software without restriction, including without limitation the @@ -213,10 +213,6 @@ // nvlink_acquireLock(nvlinkLibCtx.topLevelLock); - NVLINK_PRINT((DBG_MODULE_NVLINK_CORE, NVLINK_DBG_LEVEL_INFO, - "%s: Acquired top-level lock\n", - __FUNCTION__)); - return NVL_SUCCESS; } @@ -248,10 +244,6 @@ // nvlink_releaseLock(nvlinkLibCtx.topLevelLock); - NVLINK_PRINT((DBG_MODULE_NVLINK_CORE, NVLINK_DBG_LEVEL_INFO, - "%s: Released top-level lock\n", - __FUNCTION__)); - return NVL_SUCCESS; } diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/common/nvswitch/common/inc/soe/soeifcore.h nvidia-open-gpu-kernel-modules-535.161.08/src/common/nvswitch/common/inc/soe/soeifcore.h --- nvidia-open-gpu-kernel-modules-525.147.05/src/common/nvswitch/common/inc/soe/soeifcore.h 2023-10-25 20:20:12.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/common/nvswitch/common/inc/soe/soeifcore.h 2024-03-05 22:12:26.000000000 +0000 @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 2020-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2020-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -24,6 +24,8 @@ #ifndef _SOECORE_H_ #define _SOECORE_H_ +#define SOE_CORE_BIOS_SIZE_LS10 0x100000 // 1 MB + /*! * @file soeifutil.h * @brief SOE CORE Command Queue @@ -40,62 +42,62 @@ /*! * Read the BIOS Size */ - RM_SOE_CORE_CMD_READ_BIOS_SIZE = 0x0, + RM_SOE_CORE_CMD_READ_BIOS_SIZE, /*! * Read the BIOS */ - RM_SOE_CORE_CMD_READ_BIOS = 0x1, + RM_SOE_CORE_CMD_READ_BIOS, /*! * Run DMA self-test */ - RM_SOE_CORE_CMD_DMA_SELFTEST = 0x2, + RM_SOE_CORE_CMD_DMA_SELFTEST, /*! * Perform I2C transaction */ - RM_SOE_CORE_CMD_I2C_ACCESS = 0x3, + RM_SOE_CORE_CMD_I2C_ACCESS, /*! * Issue NPORT Reset */ - RM_SOE_CORE_CMD_ISSUE_NPORT_RESET = 0x4, + RM_SOE_CORE_CMD_ISSUE_NPORT_RESET, /*! * Restore NPORT state */ - RM_SOE_CORE_CMD_RESTORE_NPORT_STATE = 0x5, + RM_SOE_CORE_CMD_RESTORE_NPORT_STATE, /*! * Set NPORT TPROD state */ - RM_SOE_CORE_CMD_SET_NPORT_TPROD_STATE = 0x6, + RM_SOE_CORE_CMD_SET_NPORT_TPROD_STATE, /*! * Read VRs */ - RM_SOE_CORE_CMD_GET_VOLTAGE_VALUES = 0x7, + RM_SOE_CORE_CMD_GET_VOLTAGE_VALUES, /*! * Init PLM2 protected registers */ - RM_SOE_CORE_CMD_INIT_L2_STATE = 0x8, + RM_SOE_CORE_CMD_INIT_L2_STATE, /*! * Read Power */ - RM_SOE_CORE_CMD_GET_POWER_VALUES = 0x9, + RM_SOE_CORE_CMD_GET_POWER_VALUES, /*! * Set NPORT interrupts */ - RM_SOE_CORE_CMD_SET_NPORT_INTRS = 0xA, + RM_SOE_CORE_CMD_SET_NPORT_INTRS, /*! * Disable NPORT fatal interrupt */ - RM_SOE_CORE_CMD_DISABLE_NPORT_FATAL_INTR = 0xF, + RM_SOE_CORE_CMD_DISABLE_NPORT_FATAL_INTR, }; // Timeout for SOE reset callback function diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/common/nvswitch/interface/ctrl_dev_nvswitch.h nvidia-open-gpu-kernel-modules-535.161.08/src/common/nvswitch/interface/ctrl_dev_nvswitch.h --- nvidia-open-gpu-kernel-modules-525.147.05/src/common/nvswitch/interface/ctrl_dev_nvswitch.h 2023-10-25 20:20:13.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/common/nvswitch/interface/ctrl_dev_nvswitch.h 2024-03-05 22:12:27.000000000 +0000 @@ -1297,6 +1297,9 @@ NVSWITCH_PPRIV_WRITE_PRT } NVSWITCH_PRI_ERROR_INSTANCE; +#define NVSWITCH_ERROR_MAX_DESCRPTION_LEN 70 +#define NVSWITCH_RAW_ERROR_DATA_SIZE 16 + typedef struct nvswitch_error { NvU32 error_value; /* NVSWITCH_ERR_* */ @@ -1305,6 +1308,9 @@ NvU32 subinstance; /* Used for lane# or similar */ NV_DECLARE_ALIGNED(NvU64 time, 8); /* Platform time (nsec) */ NvBool error_resolved; /* If an error is correctable, set to true. */ + NvU32 error_data[NVSWITCH_RAW_ERROR_DATA_SIZE]; /* Data from NVSWITCH_REPORT_DATA */ + NvU32 error_data_size; /* Size of error_data */ + NvU8 error_description[NVSWITCH_ERROR_MAX_DESCRPTION_LEN]; /* Short description of error */ } NVSWITCH_ERROR; #define NVSWITCH_ERROR_COUNT_SIZE 64 @@ -4031,12 +4037,13 @@ #define CTRL_NVSWITCH_SET_NVLINK_ERROR_THRESHOLD 0x52 #define CTRL_NVSWITCH_GET_NVLINK_ERROR_THRESHOLD 0x53 #define CTRL_NVSWITCH_GET_VOLTAGE 0x54 -#define CTRL_NVSWITCH_GET_BOARD_PART_NUMBER 0x55 -#define CTRL_NVSWITCH_GET_POWER 0x56 -#define CTRL_NVSWITCH_GET_SYS_INFO 0x57 -#define CTRL_NVSWITCH_GET_TIME_INFO 0x58 -#define CTRL_NVSWITCH_GET_TEMP_DATA 0x59 -#define CTRL_NVSWITCH_GET_TEMP_SAMPLES 0x60 +#define CTRL_NVSWITCH_RESERVED_11 0x55 +#define CTRL_NVSWITCH_GET_BOARD_PART_NUMBER 0x56 +#define CTRL_NVSWITCH_GET_POWER 0x57 +#define CTRL_NVSWITCH_GET_SYS_INFO 0x58 +#define CTRL_NVSWITCH_GET_TIME_INFO 0x59 +#define CTRL_NVSWITCH_GET_TEMP_DATA 0x60 +#define CTRL_NVSWITCH_GET_TEMP_SAMPLES 0x61 #ifdef __cplusplus } diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/common/nvswitch/interface/export_nvswitch.h nvidia-open-gpu-kernel-modules-535.161.08/src/common/nvswitch/interface/export_nvswitch.h --- nvidia-open-gpu-kernel-modules-525.147.05/src/common/nvswitch/interface/export_nvswitch.h 2023-10-25 20:20:13.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/common/nvswitch/interface/export_nvswitch.h 2024-03-05 22:12:27.000000000 +0000 @@ -895,7 +895,6 @@ void nvswitch_os_assert_log ( - int cond, const char *pFormat, ... ); @@ -936,6 +935,12 @@ NvU32 *pBuildNum ); +NvlStatus +nvswitch_os_get_pid +( + NvU32 *pPid +); + void nvswitch_lib_smbpbi_log_sxid ( diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/common/nvswitch/kernel/bios_nvswitch.c nvidia-open-gpu-kernel-modules-535.161.08/src/common/nvswitch/kernel/bios_nvswitch.c --- nvidia-open-gpu-kernel-modules-525.147.05/src/common/nvswitch/kernel/bios_nvswitch.c 2023-10-25 20:20:13.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/common/nvswitch/kernel/bios_nvswitch.c 2024-03-05 22:12:27.000000000 +0000 @@ -29,6 +29,7 @@ #include "flcn/flcn_nvswitch.h" #include "rmflcncmdif_nvswitch.h" +#include "haldef_nvswitch.h" static NvlStatus _nvswitch_core_bios_read @@ -48,7 +49,6 @@ RM_SOE_CORE_CMD_BIOS *pParams = &cmd.cmd.core.bios; NvU64 dmaHandle = 0; NvU8 *pReadBuffer = NULL; - NvU32 spiReadCnt = 0; NvU32 offset = 0; NvU32 bufferSize = (reqSize < SOE_DMA_MAX_SIZE) ? SOE_DMA_MAX_SIZE : MAX_READ_SIZE; @@ -134,7 +134,6 @@ } offset += pParams->sizeInBytes; - spiReadCnt++; } nvswitch_os_unmap_dma_region(device->os_handle, pReadBuffer, dmaHandle, @@ -203,7 +202,7 @@ return NVL_SUCCESS; } - status = nvswitch_bios_read_size(device, &biosSize); + status = device->hal.nvswitch_get_bios_size(device, &biosSize); if (status != NVL_SUCCESS || biosSize == 0) { NVSWITCH_PRINT(device, ERROR, diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/common/nvswitch/kernel/error_nvswitch.c nvidia-open-gpu-kernel-modules-535.161.08/src/common/nvswitch/kernel/error_nvswitch.c --- nvidia-open-gpu-kernel-modules-525.147.05/src/common/nvswitch/kernel/error_nvswitch.c 2023-10-25 20:20:13.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/common/nvswitch/kernel/error_nvswitch.c 2024-03-05 22:12:27.000000000 +0000 @@ -153,14 +153,21 @@ NvBool error_resolved, void *data, NvU32 data_size, - NvU32 line + NvU32 line, + const char *description ) { NvU32 idx_error; + NvU32 description_len = (NvU32)nvswitch_os_strlen(description) - 2; //take out leading and trailing quotation NVSWITCH_ASSERT(errors != NULL); NVSWITCH_ASSERT(data_size <= sizeof(errors->error_log[idx_error].data)); + if (description_len > NVSWITCH_ERROR_MAX_DESCRPTION_LEN) + { + description_len = NVSWITCH_ERROR_MAX_DESCRPTION_LEN; + } + // If no error log has been created, don't log it. if ((errors->error_log_size != 0) && (errors->error_log != NULL)) { @@ -192,6 +199,8 @@ errors->error_log[idx_error].severity = severity; errors->error_log[idx_error].error_resolved = error_resolved; errors->error_log[idx_error].line = line; + errors->error_log[idx_error].data_size = data_size; + nvswitch_os_memcpy(&errors->error_log[idx_error].description, description + 1, description_len); // Log tracking info errors->error_log[idx_error].timer_count = nvswitch_hw_counter_read_counter(device); @@ -265,6 +274,7 @@ error_entry->timer_count = ((device == NULL) ? 0 : nvswitch_hw_counter_read_counter(device)); error_entry->time = nvswitch_os_get_platform_time(); + error_entry->data_size = 0; } else { @@ -545,6 +555,13 @@ p->error[p->errorCount].subinstance = error.subinstance; p->error[p->errorCount].time = error.time; p->error[p->errorCount].error_resolved = error.error_resolved; + p->error[p->errorCount].error_data_size = error.data_size; + if (error.data_size > 0) + { + nvswitch_os_memcpy(p->error[p->errorCount].error_data, error.data.raw.data, error.data_size); + } + nvswitch_os_memcpy(p->error[p->errorCount].error_description, error.description, sizeof(error.description)); + p->errorCount++; index++; } diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/common/nvswitch/kernel/flcn/flcnqueue_nvswitch.c nvidia-open-gpu-kernel-modules-535.161.08/src/common/nvswitch/kernel/flcn/flcnqueue_nvswitch.c --- nvidia-open-gpu-kernel-modules-525.147.05/src/common/nvswitch/kernel/flcn/flcnqueue_nvswitch.c 2023-10-25 20:20:14.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/common/nvswitch/kernel/flcn/flcnqueue_nvswitch.c 2024-03-05 22:12:28.000000000 +0000 @@ -1172,6 +1172,14 @@ NVSWITCH_ASSERT(pQueueInfo != NULL); + if (pMsgGen == NULL) + { + NVSWITCH_PRINT(device, ERROR, + "%s: NULL message\n", + __FUNCTION__); + return NV_ERR_GENERIC; + } + // get the sequence info data associated with this message pSeqInfo = flcnableQueueSeqInfoGet(device, pFlcn->pFlcnable, pMsgGen->hdr.seqNumId); if ((pSeqInfo == NULL) || @@ -1188,7 +1196,7 @@ } // If response was requested - if (pSeqInfo->pMsgResp != NULL && pMsgGen != NULL) + if (pSeqInfo->pMsgResp != NULL) { NVSWITCH_ASSERT(pSeqInfo->pMsgResp->hdr.size == pMsgGen->hdr.size); msgSize = pMsgGen->hdr.size - RM_FLCN_QUEUE_HDR_SIZE; diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/common/nvswitch/kernel/inc/common_nvswitch.h nvidia-open-gpu-kernel-modules-535.161.08/src/common/nvswitch/kernel/inc/common_nvswitch.h --- nvidia-open-gpu-kernel-modules-525.147.05/src/common/nvswitch/kernel/inc/common_nvswitch.h 2023-10-25 20:20:15.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/common/nvswitch/kernel/inc/common_nvswitch.h 2024-03-05 22:12:29.000000000 +0000 @@ -125,12 +125,21 @@ // This macro should be used to check assertion statements and print Error messages. // #if defined(DEVELOP) || defined(DEBUG) || defined(NV_MODS) +void nvswitch_assert_log +( + const char *function, + const char *file, + NvU32 line +); + #define NVSWITCH_ASSERT(_cond) \ - nvswitch_os_assert_log((_cond), "NVSwitch: Assertion failed in %s() at %s:%d\n", \ - __FUNCTION__ , __FILE__, __LINE__) + ((void)((!(_cond)) ? nvswitch_assert_log(__FUNCTION__, __FILE__, __LINE__) : 0)) + #else +void nvswitch_assert_log(void); + #define NVSWITCH_ASSERT(_cond) \ - nvswitch_os_assert_log((_cond), "NVSwitch: Assertion failed \n") + ((void)((!(_cond)) ? nvswitch_assert_log() : 0)) #endif #define NVSWITCH_ASSERT_ERROR_INFO(errorCategory, errorInfo) NVSWITCH_ASSERT(0x0) @@ -460,7 +469,8 @@ NvBool error_resolved, void *data, NvU32 data_size, - NvU32 line + NvU32 line, + const char *description ); void @@ -569,7 +579,7 @@ NvlStatus nvswitch_set_training_mode(nvswitch_device *device); NvBool nvswitch_is_link_in_reset(nvswitch_device *device, nvlink_link *link); void nvswitch_apply_recal_settings(nvswitch_device *device, nvlink_link *link); -void nvswitch_init_buffer_ready(nvswitch_device *device, nvlink_link *link, NvBool bNportBufferReady); +void nvswitch_init_buffer_ready(nvswitch_device *device, nvlink_link *link, NvBool bNportBufferReady); NvBool nvswitch_does_link_need_termination_enabled(nvswitch_device *device, nvlink_link *link); NvlStatus nvswitch_link_termination_setup(nvswitch_device *device, nvlink_link* link); #endif //_COMMON_NVSWITCH_H_ diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/common/nvswitch/kernel/inc/error_nvswitch.h nvidia-open-gpu-kernel-modules-535.161.08/src/common/nvswitch/kernel/inc/error_nvswitch.h --- nvidia-open-gpu-kernel-modules-525.147.05/src/common/nvswitch/kernel/inc/error_nvswitch.h 2023-10-25 20:20:15.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/common/nvswitch/kernel/inc/error_nvswitch.h 2024-03-05 22:12:29.000000000 +0000 @@ -99,6 +99,8 @@ NvU64 timer_count; // NvSwitch timer count NvU64 time; // Platform time, in ns NvU32 line; + NvU32 data_size; // Size of data + NvU8 description[NVSWITCH_ERROR_MAX_DESCRPTION_LEN]; // Short description of error type union { @@ -135,9 +137,9 @@ NVSWITCH_ERROR_SEVERITY_FATAL, \ _errresolved, \ NULL, 0, \ - __LINE__) + __LINE__, NULL) -#define NVSWITCH_LOG_FATAL_DATA(_device, _errsrc, _errtype, _instance, _subinstance, _errresolved, _errdata) \ +#define NVSWITCH_LOG_FATAL_DATA(_device, _errsrc, _errtype, _instance, _subinstance, _errresolved, _errdata, ...) \ nvswitch_record_error( \ _device, \ &(_device->log_FATAL_ERRORS), \ @@ -147,8 +149,7 @@ NVSWITCH_ERROR_SEVERITY_FATAL, \ _errresolved, \ _errdata, sizeof(*_errdata), \ - __LINE__) - + __LINE__, #__VA_ARGS__) #define NVSWITCH_LOG_NONFATAL(_device, _errsrc, _errtype, _instance, _subinstance, _errresolved) \ nvswitch_record_error( \ @@ -160,9 +161,9 @@ NVSWITCH_ERROR_SEVERITY_NONFATAL, \ _errresolved, \ NULL, 0, \ - __LINE__) + __LINE__, NULL) -#define NVSWITCH_LOG_NONFATAL_DATA(_device, _errsrc, _errtype, _instance, _subinstance, _errresolved, _errdata) \ +#define NVSWITCH_LOG_NONFATAL_DATA(_device, _errsrc, _errtype, _instance, _subinstance, _errresolved, _errdata, ...) \ nvswitch_record_error( \ _device, \ &(_device->log_NONFATAL_ERRORS), \ @@ -172,7 +173,7 @@ NVSWITCH_ERROR_SEVERITY_NONFATAL, \ _errresolved, \ _errdata, sizeof(*_errdata), \ - __LINE__) + __LINE__, #__VA_ARGS__) #define NVSWITCH_NVLINK_ARCH_ERROR_NONE 0 #define NVSWITCH_NVLINK_ARCH_ERROR_GENERIC 1 diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/common/nvswitch/kernel/inc/haldef_nvswitch.h nvidia-open-gpu-kernel-modules-535.161.08/src/common/nvswitch/kernel/inc/haldef_nvswitch.h --- nvidia-open-gpu-kernel-modules-525.147.05/src/common/nvswitch/kernel/inc/haldef_nvswitch.h 2023-10-25 20:20:16.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/common/nvswitch/kernel/inc/haldef_nvswitch.h 2024-03-05 22:12:30.000000000 +0000 @@ -120,9 +120,10 @@ _op(NvlStatus, nvswitch_deassert_link_reset, (nvswitch_device *device, nvlink_link *link), _arch) \ _op(NvBool, nvswitch_is_soe_supported, (nvswitch_device *device), _arch) \ _op(NvlStatus, nvswitch_init_soe, (nvswitch_device *device), _arch) \ - _op(void, nvswitch_soe_init_l2_state, (nvswitch_device *device), _arch) \ _op(NvBool, nvswitch_is_inforom_supported, (nvswitch_device *device), _arch) \ _op(NvBool, nvswitch_is_spi_supported, (nvswitch_device *device), _arch) \ + _op(NvBool, nvswitch_is_bios_supported, (nvswitch_device *device), _arch) \ + _op(NvlStatus, nvswitch_get_bios_size, (nvswitch_device *device, NvU32 *pSize), _arch) \ _op(NvBool, nvswitch_is_smbpbi_supported, (nvswitch_device *device), _arch) \ _op(NvlStatus, nvswitch_post_init_device_setup, (nvswitch_device *device), _arch) \ _op(void, nvswitch_post_init_blacklist_device_setup, (nvswitch_device *device), _arch) \ @@ -229,9 +230,10 @@ _op(NvlStatus, nvswitch_ctrl_clear_counters, (nvswitch_device *device, NVSWITCH_NVLINK_CLEAR_COUNTERS_PARAMS *ret), _arch) \ _op(NvlStatus, nvswitch_ctrl_set_nvlink_error_threshold, (nvswitch_device *device, NVSWITCH_SET_NVLINK_ERROR_THRESHOLD_PARAMS *pParams), _arch) \ _op(NvlStatus, nvswitch_ctrl_get_nvlink_error_threshold, (nvswitch_device *device, NVSWITCH_GET_NVLINK_ERROR_THRESHOLD_PARAMS *pParams), _arch) \ + _op(NvlStatus, nvswitch_ctrl_get_board_part_number, (nvswitch_device *device, NVSWITCH_GET_BOARD_PART_NUMBER_VECTOR *p), _arch) \ _op(NvlStatus, nvswitch_ctrl_therm_read_voltage, (nvswitch_device *device, NVSWITCH_CTRL_GET_VOLTAGE_PARAMS *info), _arch) \ + _op(void, nvswitch_soe_init_l2_state, (nvswitch_device *device), _arch) \ _op(NvlStatus, nvswitch_ctrl_therm_read_power, (nvswitch_device *device, NVSWITCH_GET_POWER_PARAMS *info), _arch) \ - _op(NvlStatus, nvswitch_ctrl_get_board_part_number, (nvswitch_device *device, NVSWITCH_GET_BOARD_PART_NUMBER_VECTOR *p), _arch) \ _op(NvBool, nvswitch_does_link_need_termination_enabled, (nvswitch_device *device, nvlink_link *link), _arch) \ _op(NvlStatus, nvswitch_link_termination_setup, (nvswitch_device *device, nvlink_link *link), _arch) \ _op(NvlStatus, nvswitch_check_io_sanity, (nvswitch_device *device), _arch) \ diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/common/nvswitch/kernel/inc/inforom/inforom_nvl_v3_nvswitch.h nvidia-open-gpu-kernel-modules-535.161.08/src/common/nvswitch/kernel/inc/inforom/inforom_nvl_v3_nvswitch.h --- nvidia-open-gpu-kernel-modules-525.147.05/src/common/nvswitch/kernel/inc/inforom/inforom_nvl_v3_nvswitch.h 2023-10-25 20:20:16.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/common/nvswitch/kernel/inc/inforom/inforom_nvl_v3_nvswitch.h 2024-03-05 22:12:30.000000000 +0000 @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 2019-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2019-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/common/nvswitch/kernel/inc/inforom/inforom_nvl_v4_nvswitch.h nvidia-open-gpu-kernel-modules-535.161.08/src/common/nvswitch/kernel/inc/inforom/inforom_nvl_v4_nvswitch.h --- nvidia-open-gpu-kernel-modules-525.147.05/src/common/nvswitch/kernel/inc/inforom/inforom_nvl_v4_nvswitch.h 2023-10-25 20:20:16.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/common/nvswitch/kernel/inc/inforom/inforom_nvl_v4_nvswitch.h 2024-03-05 22:12:31.000000000 +0000 @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 2019-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2019-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/common/nvswitch/kernel/inc/inforom/inforom_nvswitch.h nvidia-open-gpu-kernel-modules-535.161.08/src/common/nvswitch/kernel/inc/inforom/inforom_nvswitch.h --- nvidia-open-gpu-kernel-modules-525.147.05/src/common/nvswitch/kernel/inc/inforom/inforom_nvswitch.h 2023-10-25 20:20:16.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/common/nvswitch/kernel/inc/inforom/inforom_nvswitch.h 2024-03-05 22:12:31.000000000 +0000 @@ -118,23 +118,23 @@ // Generic InfoROM APIs NvlStatus nvswitch_initialize_inforom(nvswitch_device *device); NvlStatus nvswitch_inforom_read_object(nvswitch_device* device, - const char *objectName, const char *pObjectFormat, + const char objectName[3], const char *pObjectFormat, NvU8 *pPackedObject, void *pObject); NvlStatus nvswitch_inforom_write_object(nvswitch_device* device, - const char *objectName, const char *pObjectFormat, + const char objectName[3], const char *pObjectFormat, void *pObject, NvU8 *pOldPackedObject); void nvswitch_destroy_inforom(nvswitch_device *device); NvlStatus nvswitch_inforom_add_object(struct inforom *pInforom, INFOROM_OBJECT_HEADER_V1_00 *pHeader); NvlStatus nvswitch_inforom_get_object_version_info(nvswitch_device *device, - const char *objectName, NvU8 *pVersion, NvU8 *pSubVersion); + const char objectName[3], NvU8 *pVersion, NvU8 *pSubVersion); void *nvswitch_add_halinfo_node(NVListPtr head, int type, int size); void *nvswitch_get_halinfo_node(NVListPtr head, int type); void nvswitch_inforom_post_init(nvswitch_device *device); NvlStatus nvswitch_initialize_inforom_objects(nvswitch_device *device); void nvswitch_destroy_inforom_objects(nvswitch_device *device); NvlStatus nvswitch_inforom_load_object(nvswitch_device* device, - struct inforom *pInforom, const char *objectName, + struct inforom *pInforom, const char objectName[3], const char *pObjectFormat, NvU8 *pPackedObject, void *pObject); void nvswitch_inforom_read_static_data(nvswitch_device *device, struct inforom *pInforom, RM_SOE_SMBPBI_INFOROM_DATA *pData); diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/common/nvswitch/kernel/inc/intr_nvswitch.h nvidia-open-gpu-kernel-modules-535.161.08/src/common/nvswitch/kernel/inc/intr_nvswitch.h --- nvidia-open-gpu-kernel-modules-525.147.05/src/common/nvswitch/kernel/inc/intr_nvswitch.h 2023-10-25 20:20:16.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/common/nvswitch/kernel/inc/intr_nvswitch.h 2024-03-05 22:12:31.000000000 +0000 @@ -90,7 +90,7 @@ NVSWITCH_PRINT_SXID(device, NVSWITCH_ERR ## _logenum, \ "Non-fatal, Link %02d %s%s\n", link, _str, NVSWITCH_FIRST()); \ NVSWITCH_LOG_NONFATAL_DATA(device, _HW, _logenum, \ - link, 0, NV_FALSE, &report); \ + link, 0, NV_FALSE, &report, _str); \ if (nvswitch_lib_notify_client_events(device, \ NVSWITCH_DEVICE_EVENT_NONFATAL) != NVL_SUCCESS) \ { \ @@ -106,7 +106,7 @@ NVSWITCH_PRINT_SXID(device, NVSWITCH_ERR ## _logenum, \ "Fatal, Link %02d %s%s\n", link, _str, NVSWITCH_FIRST()); \ NVSWITCH_LOG_FATAL_DATA(device, _HW, _logenum, \ - link, 0, NV_FALSE, &report); \ + link, 0, NV_FALSE, &report, _str); \ nvswitch_set_fatal_error(device, device_fatal, link); \ if (nvswitch_lib_notify_client_events(device, \ NVSWITCH_DEVICE_EVENT_FATAL) != NVL_SUCCESS) \ @@ -122,7 +122,7 @@ NVSWITCH_PRINT_SXID(device, NVSWITCH_ERR ## _logenum, \ "Non-fatal, %s, instance=%d, chiplet=%d\n", _str, instance, chiplet); \ NVSWITCH_LOG_NONFATAL_DATA(device, _HW, _logenum, \ - instance, chiplet, NV_FALSE, &err_data); \ + instance, chiplet, NV_FALSE, &err_data, _str); \ if (nvswitch_lib_notify_client_events(device, \ NVSWITCH_DEVICE_EVENT_NONFATAL) != NVL_SUCCESS) \ { \ @@ -137,7 +137,7 @@ NVSWITCH_PRINT_SXID(device, NVSWITCH_ERR ## _logenum, \ "Fatal, %s, instance=%d, chiplet=%d\n", _str, instance, chiplet); \ NVSWITCH_LOG_FATAL_DATA(device, _HW, _logenum, \ - instance, chiplet, NV_FALSE, &err_data); \ + instance, chiplet, NV_FALSE, &err_data, _str); \ nvswitch_set_fatal_error(device, device_fatal, 0); \ if (nvswitch_lib_notify_client_events(device, \ NVSWITCH_DEVICE_EVENT_FATAL) != NVL_SUCCESS) \ diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/common/nvswitch/kernel/inc/ls10/ls10.h nvidia-open-gpu-kernel-modules-535.161.08/src/common/nvswitch/kernel/inc/ls10/ls10.h --- nvidia-open-gpu-kernel-modules-525.147.05/src/common/nvswitch/kernel/inc/ls10/ls10.h 2023-10-25 20:20:18.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/common/nvswitch/kernel/inc/ls10/ls10.h 2024-03-05 22:12:33.000000000 +0000 @@ -984,10 +984,10 @@ NvlStatus nvswitch_ctrl_i2c_indexed_ls10(nvswitch_device *device, NVSWITCH_CTRL_I2C_INDEXED_PARAMS *pParams); NvBool nvswitch_i2c_is_device_access_allowed_ls10(nvswitch_device *device, NvU32 port, NvU8 addr, NvBool bIsRead); NvlStatus nvswitch_minion_get_ali_debug_registers_ls10(nvswitch_device *device, nvlink_link *link, NVSWITCH_MINION_ALI_DEBUG_REGISTERS *params); +void nvswitch_execute_unilateral_link_shutdown_ls10(nvlink_link *link); void nvswitch_setup_link_system_registers_ls10(nvswitch_device *device, nvlink_link *link); void nvswitch_load_link_disable_settings_ls10(nvswitch_device *device, nvlink_link *link); void nvswitch_link_disable_interrupts_ls10(nvswitch_device *device, NvU32 link); -void nvswitch_execute_unilateral_link_shutdown_ls10(nvlink_link *link); void nvswitch_init_dlpl_interrupts_ls10(nvlink_link *link); void nvswitch_set_dlpl_interrupts_ls10(nvlink_link *link); @@ -1020,6 +1020,7 @@ NvBool nvswitch_are_link_clocks_on_ls10(nvswitch_device *device, nvlink_link *link, NvU32 clocksMask); NvBool nvswitch_does_link_need_termination_enabled_ls10(nvswitch_device *device, nvlink_link *link); NvlStatus nvswitch_link_termination_setup_ls10(nvswitch_device *device, nvlink_link* link); +void nvswitch_get_error_rate_threshold_ls10(nvlink_link *link); #endif //_LS10_H_ diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/common/nvswitch/kernel/inc/ls10/multicast_ls10.h nvidia-open-gpu-kernel-modules-535.161.08/src/common/nvswitch/kernel/inc/ls10/multicast_ls10.h --- nvidia-open-gpu-kernel-modules-525.147.05/src/common/nvswitch/kernel/inc/ls10/multicast_ls10.h 2023-10-25 20:20:18.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/common/nvswitch/kernel/inc/ls10/multicast_ls10.h 2024-03-05 22:12:33.000000000 +0000 @@ -111,10 +111,12 @@ NvU32 *entries_used); NvlStatus nvswitch_mc_unwind_directives_ls10(nvswitch_device *device, - NVSWITCH_TCP_DIRECTIVE_LS10* directives, - NvU32 *ports, NvU8 *vc_hop, - NvU32 *ports_per_spray_group, NvU32 *replica_offset, - NvBool *replica_valid); + NVSWITCH_TCP_DIRECTIVE_LS10 directives[NVSWITCH_MC_TCP_LIST_SIZE_LS10], + NvU32 ports[NVSWITCH_MC_MAX_PORTS], + NvU8 vc_hop[NVSWITCH_MC_MAX_PORTS], + NvU32 ports_per_spray_group[NVSWITCH_MC_MAX_SPRAYGROUPS], + NvU32 replica_offset[NVSWITCH_MC_MAX_SPRAYGROUPS], + NvBool replica_valid[NVSWITCH_MC_MAX_SPRAYGROUPS]); NvlStatus nvswitch_mc_invalidate_mc_rid_entry_ls10(nvswitch_device *device, NvU32 port, NvU32 index, NvBool use_extended_table, NvBool zero); diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/common/nvswitch/kernel/inc/ls10/soe_ls10.h nvidia-open-gpu-kernel-modules-535.161.08/src/common/nvswitch/kernel/inc/ls10/soe_ls10.h --- nvidia-open-gpu-kernel-modules-525.147.05/src/common/nvswitch/kernel/inc/ls10/soe_ls10.h 2023-10-25 20:20:18.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/common/nvswitch/kernel/inc/ls10/soe_ls10.h 2024-03-05 22:12:33.000000000 +0000 @@ -40,11 +40,13 @@ NvlStatus nvswitch_set_nport_tprod_state_ls10(nvswitch_device *device, NvU32 nport); void nvswitch_soe_unregister_events_ls10(nvswitch_device *device); void nvswitch_therm_soe_callback_ls10(nvswitch_device *device, union RM_FLCN_MSG *pMsg, - void *pParams, NvU32 seqDesc, NV_STATUS status); + void *pParams, NvU32 seqDesc, NV_STATUS status); NvlStatus nvswitch_soe_register_event_callbacks_ls10(nvswitch_device *device); NvlStatus nvswitch_soe_restore_nport_state_ls10(nvswitch_device *device, NvU32 nport); NvlStatus nvswitch_soe_issue_nport_reset_ls10(nvswitch_device *device, NvU32 nport); void nvswitch_soe_init_l2_state_ls10(nvswitch_device *device); +void nvswitch_heartbeat_soe_callback_ls10(nvswitch_device *device, RM_FLCN_MSG *pGenMsg, + void *pParams, NvU32 seqDesc, NV_STATUS status); NvlStatus nvswitch_soe_set_nport_interrupts_ls10(nvswitch_device *device, NvU32 nport, NvBool bEnable); void nvswitch_soe_disable_nport_fatal_interrupts_ls10(nvswitch_device *device, NvU32 nport, NvU32 nportIntrEnable, NvU8 nportIntrType); diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/common/nvswitch/kernel/inc/soe/bin/g_soeuc_lr10_dbg.h nvidia-open-gpu-kernel-modules-535.161.08/src/common/nvswitch/kernel/inc/soe/bin/g_soeuc_lr10_dbg.h --- nvidia-open-gpu-kernel-modules-525.147.05/src/common/nvswitch/kernel/inc/soe/bin/g_soeuc_lr10_dbg.h 2023-10-25 20:20:19.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/common/nvswitch/kernel/inc/soe/bin/g_soeuc_lr10_dbg.h 2024-03-05 22:12:34.000000000 +0000 @@ -116,8 +116,8 @@ 0x99bf000f, 0xf70fa3b2, 0x550094b3, 0x4b00a0b3, 0x0005987e, 0x000f9881, 0x000f8c82, 0x2abf10bf, 0x900030bc, 0x517e10aa, 0x29bf000c, 0xbf0490b5, 0xf409a619, 0x78890b18, 0x423e0010, 0x7c89000a, 0x9abf0010, 0xbb902bbf, 0x0c0f7e10, 0x092e7e00, 0xb3010f00, 0x7e0a00a4, 0x0f00000e, 0xfbfab201, - 0x00a0b331, 0x03a99811, 0x99b9afbf, 0xf0f9a600, 0x00f80bac, 0xf41032f4, 0x548f1132, 0xf9bf0005, - 0xa0019990, 0xf800f8f9, 0x10107e00, 0x7e00f800, 0xf8001842, 0x184a7e00, 0x8f00f800, 0xbf000554, + 0x00a0b331, 0x03a99811, 0x99b9afbf, 0xf0f9a600, 0x00f80bac, 0xf41032f4, 0x5c8f1132, 0xf9bf0005, + 0xa0019990, 0xf800f8f9, 0x10107e00, 0x7e00f800, 0xf8001842, 0x184a7e00, 0x8f00f800, 0xbf00055c, 0x0094b3f9, 0x1032f41a, 0xbd1132f4, 0x7eee0ba4, 0xf4000a95, 0x31f41031, 0xbf00f811, 0x019992f9, 0xf9bff9a0, 0x0a0094b3, 0xf41031f4, 0x00f81131, 0x0038a77e, 0xc9fe00f8, 0x1495b601, 0x3c089033, 0xf4089630, 0x9033130c, 0x90332002, 0x90333403, 0x1c3e1800, 0x9033000b, 0x9033280f, 0x94331810, @@ -179,7 +179,7 @@ 0x0a747eb1, 0xfe0ab200, 0x00900140, 0x7e0bb208, 0xbf000012, 0x18f43d00, 0x163e1d0d, 0xe9180012, 0x01ff1020, 0x2620ee90, 0x0d1bf491, 0x0100943d, 0x233ee920, 0xf9c40012, 0xe009bcff, 0x08f4fd26, 0x7e043de0, 0x32000a9b, 0x0415fb0a, 0x0011d87e, 0x0600a433, 0x00f802f8, 0xa4f082f9, 0x31008fff, - 0x31188e00, 0x58fa7c00, 0xb298ea3c, 0xbdc632b7, 0xff94f034, 0x00055888, 0x8120597c, 0x3e001104, + 0x31188e00, 0x58fa7c00, 0xb298ea3c, 0xbdc632b7, 0xff94f034, 0x00056088, 0x8120597c, 0x3e001104, 0x52001354, 0x29e40122, 0x9494ffff, 0x034ffe08, 0xb31ff995, 0xd0100190, 0x03000000, 0xf594f0ff, 0xbf00d51b, 0x01008e89, 0x089f9500, 0xfffff9e4, 0x18f59ea6, 0x99900010, 0x0894b601, 0x473e89a0, 0x1f580013, 0x02195801, 0x1bf4f966, 0x000b4945, 0x000093f1, 0x0031248f, 0x18909fbc, 0x19180190, @@ -208,7 +208,7 @@ 0x0c004d81, 0xcf0b004c, 0xcecf00df, 0x00d9cf00, 0x1bf4f9a6, 0xb5aea0f5, 0x00f801af, 0xcf0b0049, 0xaabf0099, 0xf8a29abc, 0xb242f900, 0xb2b3b2a0, 0x00c0b3c1, 0x0b004929, 0xb20092cf, 0x0000b394, 0xf93ab212, 0x00a03305, 0x3e010a0a, 0xcf0015e8, 0x92bb0049, 0xf491a602, 0x04b3e608, 0xa43d0a00, - 0x0015e83e, 0x05f93ab2, 0x000041fb, 0xd24e0041, 0x00000554, 0x90fc00f8, 0x0015ea7e, 0xf90188fe, + 0x0015e83e, 0x05f93ab2, 0x000041fb, 0xd24e0041, 0x0000055c, 0x90fc00f8, 0x0015ea7e, 0xf90188fe, 0x00289880, 0x8cd880f9, 0x9800000f, 0x47fe0088, 0xbd87a001, 0x0387b570, 0xfe0010f7, 0xb7b600a4, 0x1fb9f002, 0xf9001bf7, 0x7e00f890, 0x3e0015ea, 0xf9001647, 0x3550daf2, 0x50db0000, 0x7e000033, 0x7e0015f6, 0xf7000b68, 0x8cd80010, 0x9800000f, 0x87980088, 0x0074fe00, 0xb6028798, 0x79f00277, @@ -349,7 +349,7 @@ 0xf9cf01c0, 0x4c99c700, 0x220090b3, 0xf60190b3, 0x223e02f8, 0xf9cf0027, 0x4c99c700, 0x390090b3, 0xf60190b3, 0x363e02f8, 0xa48f0027, 0x008901ad, 0x9ff601c1, 0xb8f4bd00, 0x00010099, 0xdf009ff6, 0x800000f2, 0x020099b8, 0x009ff602, 0xb2009fcf, 0x27363e9f, 0xe400f800, 0xc7ff00bf, 0xaeb2f0b9, - 0xdfd59fff, 0x0000055c, 0x0027ab3e, 0x1bf49b26, 0x01f9581a, 0x1bf49d66, 0x3df97f12, 0x08e975a4, + 0xdfd59fff, 0x00000564, 0x0027ab3e, 0x1bf49b26, 0x01f9581a, 0x1bf49d66, 0x3df97f12, 0x08e975a4, 0x7501ff58, 0x00f809ef, 0x3f04ff90, 0x009433f9, 0xf8010adf, 0x0aa9b200, 0x00b0b302, 0x3db92008, 0xf900f8a4, 0xb3a0b202, 0x986500a0, 0x90b305a9, 0x0cd95e00, 0xbf000014, 0xe8aab89a, 0x277e0004, 0xa9e7001a, 0x9ab30168, 0xb34c0fff, 0xb6470090, 0xaab314a5, 0xb3400fff, 0x983b00a0, 0x94b6050e, @@ -463,7 +463,7 @@ 0xf9b5059d, 0x01087e2e, 0x3e143d00, 0x33003574, 0x01ab001d, 0xb2016b18, 0x0f817e3a, 0xfe020900, 0xff90014f, 0x3df92048, 0x02f93594, 0x09033318, 0xb2b4bd04, 0x03f335fa, 0x7e01f935, 0x3e000f71, 0xfe00371a, 0x41fe0140, 0x44009001, 0xfe401190, 0x0ab20142, 0xb23c2290, 0x3d2cb21b, 0x75b07ed4, - 0x02399800, 0x010a0fbf, 0x1bf4f9a6, 0x0524de3c, 0xe93f0000, 0x0e009033, 0x1e0a943d, 0x063ee920, + 0x02399800, 0x010a0fbf, 0x1bf4f9a6, 0x052cde3c, 0xe93f0000, 0x0e009033, 0x1e0a943d, 0x063ee920, 0xffd90036, 0xff200000, 0x94b394f9, 0x0ab2121c, 0x2cb21bb2, 0x0098b97e, 0x0036063e, 0x1bb20ab2, 0x3e7e2cb2, 0x4bfe008d, 0x44bb9001, 0xa9c4bebf, 0xffffdf1f, 0x94b6e0ff, 0x04effd18, 0xa0e59eff, 0x0000d9be, 0xe9ff4000, 0x6b0bf494, 0x681fa433, 0x900149fe, 0x9dbf4099, 0xbf049992, 0x1ee4339c, @@ -751,7 +751,7 @@ 0x00f0b305, 0x0a09584a, 0x90014afe, 0xafb508aa, 0x010f9801, 0xb60093f0, 0xa9b50294, 0x02afb503, 0xb2100918, 0x18a9351b, 0xb5020f98, 0x099804af, 0x05a9b503, 0xa0a000bf, 0x005b0b7e, 0xf001a6b0, 0x9a120b9c, 0x59ab3e01, 0xfb020a00, 0xe27e1c15, 0x943d0059, 0xf001a6b0, 0xa6f00bac, 0xa29a3c01, - 0x4c8900f8, 0x9ebf0005, 0xb5019f98, 0x9ea0019f, 0x005a267e, 0x0801a4b3, 0x00f8a43d, 0xff0a02f8, + 0x548900f8, 0x9ebf0005, 0xb5019f98, 0x9ea0019f, 0x005a267e, 0x0801a4b3, 0x00f8a43d, 0xff0a02f8, 0x12f900f8, 0x000f8c89, 0xf20a99bf, 0x380090b3, 0x000fa881, 0xf10a10bf, 0x2c0004b3, 0x000a747e, 0x19a00109, 0x000f9889, 0x948990a0, 0xff0f0010, 0x90899fa0, 0x90a0000f, 0x000f9489, 0x587e9fa0, 0x10a00037, 0x12f911fb, 0x000f8c89, 0xb4bd04bd, 0xb44c90a0, 0x0fac8a00, 0x0b947e00, 0x0cb4bd00, @@ -1159,7 +1159,7 @@ 0x000005dc, 0xffbf32f9, 0x900149fe, 0xa2b21899, 0xa9bf9fa0, 0xb39899c7, 0x00aa1d99, 0x00299cd9, 0x02999800, 0xb34299c7, 0x009a0099, 0x0a0140fe, 0x14009001, 0xef7e0bb2, 0xa4330094, 0x4bfe551f, 0x90020a01, 0xef7e10bb, 0xa4330094, 0x09bf451f, 0x04bd0103, 0xbc1493ff, 0x94f09530, 0x121bf401, - 0x0f0204b3, 0x009a457e, 0x0700a033, 0x900415f0, 0x04b30100, 0x49fee509, 0x14999001, 0x19a699bf, + 0x0f0204b3, 0x009a457e, 0x0700a033, 0x900415f0, 0x04b30100, 0x49fee50a, 0x14999001, 0x19a699bf, 0x0a150bf4, 0x7e1bb201, 0x3300950a, 0xf80a1fa0, 0x8d233e09, 0xfe2ebf00, 0x99900149, 0xdf99bf10, 0xbfffffff, 0xeffd1f0a, 0x0099b904, 0xf09419ff, 0x96f00b9c, 0x1e94b601, 0xa0059efd, 0x8d233e29, 0xfe1f0a00, 0x99900149, 0xd99fbf18, 0x000005dc, 0xf9a699bf, 0x7e070bf4, 0xfb003a31, 0x30f40c35, @@ -1198,7 +1198,7 @@ 0x0590ff10, 0x0069f07e, 0x94f119bf, 0x40a0ffff, 0x313e59a0, 0xfab20094, 0x0095f47e, 0x0094c83e, 0x0d00a033, 0x5c01ad33, 0x91ae3e03, 0x33b0bf00, 0x330c0190, 0x3e2f0294, 0xfe00919e, 0x010a0141, 0xb2181190, 0x94ef7e1b, 0x1fad3300, 0x1fbf033f, 0x09fffe09, 0x049fff95, 0xa23e10a0, 0x04f10091, - 0x2a3201ff, 0x0a7e0bb2, 0xc83e0095, 0x9a320094, 0x0094ef7e, 0x0094c83e, 0x237efab2, 0xc83e0095, + 0x2a3203ff, 0x0a7e0bb2, 0xc83e0095, 0x9a320094, 0x0094ef7e, 0x0094c83e, 0x237efab2, 0xc83e0095, 0x9cd30094, 0xbf000029, 0x0000df39, 0x080a2000, 0xf5049ffd, 0x0a02f50b, 0x001d3303, 0x40fe02ef, 0x014cfe01, 0x90280090, 0x0bb22ccc, 0x900142fe, 0x2ab22422, 0x0073477e, 0x9670097f, 0x0b9cf003, 0x7e079194, 0x1800010e, 0x087e5830, 0x00330001, 0x1fb20a00, 0x00924d3e, 0xa4732a7f, 0x19b20a00, @@ -1212,7 +1212,7 @@ 0x0093513e, 0xffc7ff49, 0x95f194f9, 0x1c3e0800, 0xff490093, 0x94f9ffc7, 0x100095f1, 0xfe3fff8f, 0xe5049ffd, 0x3ec0009f, 0x49009351, 0xf9ffc7ff, 0x0095f194, 0x93433e08, 0xc7ff4900, 0xf194f9ff, 0x8f100095, 0xfdfe3fff, 0x008f049f, 0x9fff0100, 0x299cd9f5, 0x99180000, 0x00903350, 0x0000890f, - 0x95f9ff02, 0x00936f3e, 0xfdffff89, 0xa094f9ff, 0x94313e49, 0x14a63000, 0x01480cf5, 0xd9ffafc4, + 0x95f9ff02, 0x00936f3e, 0xfdffff89, 0xa094f9ff, 0x94313e49, 0x16a63000, 0x01480cf5, 0xd9ffafc4, 0x000004d0, 0xd9e89fbc, 0x0000299c, 0xefc7080a, 0x989fbc3b, 0xbb96efc7, 0x94f0059f, 0x2b0bf501, 0xff29c401, 0x010defe7, 0x0a029b54, 0xf5bf6604, 0xf0011918, 0xb9e400f3, 0xf9bcffff, 0x04c6b0c2, 0x0c090df4, 0x93cb3e04, 0xe44da000, 0xc4ffffba, 0xebe703e9, 0x94330142, 0xbabc1200, 0x29bcd9b0, @@ -1248,7 +1248,7 @@ 0x94f0e0ef, 0xbcff0f1f, 0xf9bc909d, 0x05febb95, 0xfd049dbb, 0x99b904fc, 0x04fdbb00, 0xfd049afd, 0xb9a0059f, 0x900149fe, 0x9fbf2099, 0x0005dcd9, 0xa699bf00, 0x070bf4f9, 0x003a317e, 0xf41c15fb, 0xdcd9f430, 0xf9000005, 0xb299bf82, 0x014ffed1, 0xa02cff90, 0x92dd3ff9, 0x1f0003ff, 0xf0351709, - 0x02f03501, 0xb6b2f920, 0xa5b2e3b2, 0x1900d433, 0x000528db, 0x7e240c00, 0x09000b7e, 0x200a3209, + 0x02f03501, 0xb6b2f920, 0xa5b2e3b2, 0x1900d433, 0x000530db, 0x7e240c00, 0x09000b7e, 0x200a3209, 0x98823e19, 0x30030a00, 0x0cf409d6, 0x0147fe78, 0xb2ffc4c4, 0x90043df8, 0x793e2477, 0x09c40098, 0x947bb2ff, 0x040c0292, 0x3da026bc, 0x96d27ed4, 0x1fa43300, 0xc47fbf6b, 0x94a607f9, 0xc75e18f4, 0x991223f9, 0x01963001, 0xc7520cf4, 0xe9c42ffe, 0xc8893cff, 0xc78afdc7, 0xd93c85f9, 0xf49c2690, @@ -1570,11 +1570,11 @@ 0x00000000, 0x00000001, 0x0000000e, 0x00000000, 0x08000000, 0x08400000, 0x08800000, 0x08c300a7, 0x09000000, 0x09400000, 0x09800000, 0x09c00000, 0x0a01c000, 0x0a404038, 0x0a804040, 0x0ac04048, 0x0b004050, 0x0b420058, 0x0b8201ab, 0x11800000, 0x11c00000, 0x12000000, 0x12400000, 0x12800000, - 0x12c00000, 0x00000001, 0x00001c08, 0x00101c09, 0x00201c0a, 0x0000bd08, 0x00209d09, 0x00309d0a, - 0x00011f08, 0x00113e09, 0x00311e0a, 0x00010309, 0x00000000, 0x0000ffff, 0x00003b00, 0x46020f1f, - 0x43010f1f, 0x44020f1f, 0x45020f1f, 0x601207ef, 0x601307ef, 0x601407ef, 0x601507ef, 0x801607ef, - 0x253207c2, 0x25330fc2, 0x25340fc2, 0x25350fc2, 0x1152079d, 0x1253079d, 0x7014079d, 0x7015079d, - 0x601203c8, 0x601307c8, 0x601407c8, 0xbb150720, 0x02172701, 0x00000000, 0x00000000, 0x00000000, + 0x12c00000, 0x00000000, 0x00000000, 0x00000001, 0x00001c08, 0x00101c09, 0x00201c0a, 0x0000bd08, + 0x00209d09, 0x00309d0a, 0x00011f08, 0x00113e09, 0x00311e0a, 0x00010309, 0x00000000, 0x0000ffff, + 0x00003b00, 0x46020f1f, 0x43010f1f, 0x44020f1f, 0x45020f1f, 0x601207ef, 0x601307ef, 0x601407ef, + 0x601507ef, 0x801607ef, 0x253207c2, 0x25330fc2, 0x25340fc2, 0x25350fc2, 0x1152079d, 0x1253079d, + 0x7014079d, 0x7015079d, 0x601203c8, 0x601307c8, 0x601407c8, 0xbb150720, 0x02172701, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, @@ -2269,8 +2269,8 @@ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0xb32dc4cc, 0x58018cca, 0x7c52cad0, 0x4a5277fe, 0x59305452, 0xfe64d88a, 0xe474c23b, 0xfee62bd9, - 0x705ea2e7, 0x0577e70f, 0xcf75f41f, 0xfe6e071a, 0xd0954f7e, 0x7caea789, 0x40b32eb9, 0x80368ac3, + 0xf0cc97fc, 0xc5e27e17, 0x63cc4ffc, 0xc48564fa, 0x6073f3d9, 0x573ea3ef, 0xf0764322, 0xf8dacef7, + 0x956b7a40, 0x90bcaaf7, 0xdea25edb, 0x9aaef423, 0xe0830635, 0xb9c7326b, 0x27f96395, 0x7078f754, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/common/nvswitch/kernel/inc/soe/bin/g_soeuc_lr10_prd.h nvidia-open-gpu-kernel-modules-535.161.08/src/common/nvswitch/kernel/inc/soe/bin/g_soeuc_lr10_prd.h --- nvidia-open-gpu-kernel-modules-525.147.05/src/common/nvswitch/kernel/inc/soe/bin/g_soeuc_lr10_prd.h 2023-10-25 20:20:19.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/common/nvswitch/kernel/inc/soe/bin/g_soeuc_lr10_prd.h 2024-03-05 22:12:35.000000000 +0000 @@ -116,8 +116,8 @@ 0x99bf000f, 0xf70fa3b2, 0x550094b3, 0x4b00a0b3, 0x0005987e, 0x000f9881, 0x000f8c82, 0x2abf10bf, 0x900030bc, 0x517e10aa, 0x29bf000c, 0xbf0490b5, 0xf409a619, 0x78890b18, 0x423e0010, 0x7c89000a, 0x9abf0010, 0xbb902bbf, 0x0c0f7e10, 0x092e7e00, 0xb3010f00, 0x7e0a00a4, 0x0f00000e, 0xfbfab201, - 0x00a0b331, 0x03a99811, 0x99b9afbf, 0xf0f9a600, 0x00f80bac, 0xf41032f4, 0x548f1132, 0xf9bf0005, - 0xa0019990, 0xf800f8f9, 0x10107e00, 0x7e00f800, 0xf8001842, 0x184a7e00, 0x8f00f800, 0xbf000554, + 0x00a0b331, 0x03a99811, 0x99b9afbf, 0xf0f9a600, 0x00f80bac, 0xf41032f4, 0x5c8f1132, 0xf9bf0005, + 0xa0019990, 0xf800f8f9, 0x10107e00, 0x7e00f800, 0xf8001842, 0x184a7e00, 0x8f00f800, 0xbf00055c, 0x0094b3f9, 0x1032f41a, 0xbd1132f4, 0x7eee0ba4, 0xf4000a95, 0x31f41031, 0xbf00f811, 0x019992f9, 0xf9bff9a0, 0x0a0094b3, 0xf41031f4, 0x00f81131, 0x0038a77e, 0xc9fe00f8, 0x1495b601, 0x3c089033, 0xf4089630, 0x9033130c, 0x90332002, 0x90333403, 0x1c3e1800, 0x9033000b, 0x9033280f, 0x94331810, @@ -179,7 +179,7 @@ 0x0a747eb1, 0xfe0ab200, 0x00900140, 0x7e0bb208, 0xbf000012, 0x18f43d00, 0x163e1d0d, 0xe9180012, 0x01ff1020, 0x2620ee90, 0x0d1bf491, 0x0100943d, 0x233ee920, 0xf9c40012, 0xe009bcff, 0x08f4fd26, 0x7e043de0, 0x32000a9b, 0x0415fb0a, 0x0011d87e, 0x0600a433, 0x00f802f8, 0xa4f082f9, 0x31008fff, - 0x31188e00, 0x58fa7c00, 0xb298ea3c, 0xbdc632b7, 0xff94f034, 0x00055888, 0x8120597c, 0x3e001104, + 0x31188e00, 0x58fa7c00, 0xb298ea3c, 0xbdc632b7, 0xff94f034, 0x00056088, 0x8120597c, 0x3e001104, 0x52001354, 0x29e40122, 0x9494ffff, 0x034ffe08, 0xb31ff995, 0xd0100190, 0x03000000, 0xf594f0ff, 0xbf00d51b, 0x01008e89, 0x089f9500, 0xfffff9e4, 0x18f59ea6, 0x99900010, 0x0894b601, 0x473e89a0, 0x1f580013, 0x02195801, 0x1bf4f966, 0x000b4945, 0x000093f1, 0x0031248f, 0x18909fbc, 0x19180190, @@ -208,7 +208,7 @@ 0x0c004d81, 0xcf0b004c, 0xcecf00df, 0x00d9cf00, 0x1bf4f9a6, 0xb5aea0f5, 0x00f801af, 0xcf0b0049, 0xaabf0099, 0xf8a29abc, 0xb242f900, 0xb2b3b2a0, 0x00c0b3c1, 0x0b004929, 0xb20092cf, 0x0000b394, 0xf93ab212, 0x00a03305, 0x3e010a0a, 0xcf0015e8, 0x92bb0049, 0xf491a602, 0x04b3e608, 0xa43d0a00, - 0x0015e83e, 0x05f93ab2, 0x000041fb, 0xd24e0041, 0x00000554, 0x90fc00f8, 0x0015ea7e, 0xf90188fe, + 0x0015e83e, 0x05f93ab2, 0x000041fb, 0xd24e0041, 0x0000055c, 0x90fc00f8, 0x0015ea7e, 0xf90188fe, 0x00289880, 0x8cd880f9, 0x9800000f, 0x47fe0088, 0xbd87a001, 0x0387b570, 0xfe0010f7, 0xb7b600a4, 0x1fb9f002, 0xf9001bf7, 0x7e00f890, 0x3e0015ea, 0xf9001647, 0x3550daf2, 0x50db0000, 0x7e000033, 0x7e0015f6, 0xf7000b68, 0x8cd80010, 0x9800000f, 0x87980088, 0x0074fe00, 0xb6028798, 0x79f00277, @@ -349,7 +349,7 @@ 0xf9cf01c0, 0x4c99c700, 0x220090b3, 0xf60190b3, 0x223e02f8, 0xf9cf0027, 0x4c99c700, 0x390090b3, 0xf60190b3, 0x363e02f8, 0xa48f0027, 0x008901ad, 0x9ff601c1, 0xb8f4bd00, 0x00010099, 0xdf009ff6, 0x800000f2, 0x020099b8, 0x009ff602, 0xb2009fcf, 0x27363e9f, 0xe400f800, 0xc7ff00bf, 0xaeb2f0b9, - 0xdfd59fff, 0x0000055c, 0x0027ab3e, 0x1bf49b26, 0x01f9581a, 0x1bf49d66, 0x3df97f12, 0x08e975a4, + 0xdfd59fff, 0x00000564, 0x0027ab3e, 0x1bf49b26, 0x01f9581a, 0x1bf49d66, 0x3df97f12, 0x08e975a4, 0x7501ff58, 0x00f809ef, 0x3f04ff90, 0x009433f9, 0xf8010adf, 0x0aa9b200, 0x00b0b302, 0x3db92008, 0xf900f8a4, 0xb3a0b202, 0x986500a0, 0x90b305a9, 0x0cd95e00, 0xbf000014, 0xe8aab89a, 0x277e0004, 0xa9e7001a, 0x9ab30168, 0xb34c0fff, 0xb6470090, 0xaab314a5, 0xb3400fff, 0x983b00a0, 0x94b6050e, @@ -463,7 +463,7 @@ 0xf9b5059d, 0x01087e2e, 0x3e143d00, 0x33003574, 0x01ab001d, 0xb2016b18, 0x0f817e3a, 0xfe020900, 0xff90014f, 0x3df92048, 0x02f93594, 0x09033318, 0xb2b4bd04, 0x03f335fa, 0x7e01f935, 0x3e000f71, 0xfe00371a, 0x41fe0140, 0x44009001, 0xfe401190, 0x0ab20142, 0xb23c2290, 0x3d2cb21b, 0x75b07ed4, - 0x02399800, 0x010a0fbf, 0x1bf4f9a6, 0x0524de3c, 0xe93f0000, 0x0e009033, 0x1e0a943d, 0x063ee920, + 0x02399800, 0x010a0fbf, 0x1bf4f9a6, 0x052cde3c, 0xe93f0000, 0x0e009033, 0x1e0a943d, 0x063ee920, 0xffd90036, 0xff200000, 0x94b394f9, 0x0ab2121c, 0x2cb21bb2, 0x0098b97e, 0x0036063e, 0x1bb20ab2, 0x3e7e2cb2, 0x4bfe008d, 0x44bb9001, 0xa9c4bebf, 0xffffdf1f, 0x94b6e0ff, 0x04effd18, 0xa0e59eff, 0x0000d9be, 0xe9ff4000, 0x6b0bf494, 0x681fa433, 0x900149fe, 0x9dbf4099, 0xbf049992, 0x1ee4339c, @@ -751,7 +751,7 @@ 0x00f0b305, 0x0a09584a, 0x90014afe, 0xafb508aa, 0x010f9801, 0xb60093f0, 0xa9b50294, 0x02afb503, 0xb2100918, 0x18a9351b, 0xb5020f98, 0x099804af, 0x05a9b503, 0xa0a000bf, 0x005b0b7e, 0xf001a6b0, 0x9a120b9c, 0x59ab3e01, 0xfb020a00, 0xe27e1c15, 0x943d0059, 0xf001a6b0, 0xa6f00bac, 0xa29a3c01, - 0x4c8900f8, 0x9ebf0005, 0xb5019f98, 0x9ea0019f, 0x005a267e, 0x0801a4b3, 0x00f8a43d, 0xff0a02f8, + 0x548900f8, 0x9ebf0005, 0xb5019f98, 0x9ea0019f, 0x005a267e, 0x0801a4b3, 0x00f8a43d, 0xff0a02f8, 0x12f900f8, 0x000f8c89, 0xf20a99bf, 0x380090b3, 0x000fa881, 0xf10a10bf, 0x2c0004b3, 0x000a747e, 0x19a00109, 0x000f9889, 0x948990a0, 0xff0f0010, 0x90899fa0, 0x90a0000f, 0x000f9489, 0x587e9fa0, 0x10a00037, 0x12f911fb, 0x000f8c89, 0xb4bd04bd, 0xb44c90a0, 0x0fac8a00, 0x0b947e00, 0x0cb4bd00, @@ -1159,7 +1159,7 @@ 0x000005dc, 0xffbf32f9, 0x900149fe, 0xa2b21899, 0xa9bf9fa0, 0xb39899c7, 0x00aa1d99, 0x00299cd9, 0x02999800, 0xb34299c7, 0x009a0099, 0x0a0140fe, 0x14009001, 0xef7e0bb2, 0xa4330094, 0x4bfe551f, 0x90020a01, 0xef7e10bb, 0xa4330094, 0x09bf451f, 0x04bd0103, 0xbc1493ff, 0x94f09530, 0x121bf401, - 0x0f0204b3, 0x009a457e, 0x0700a033, 0x900415f0, 0x04b30100, 0x49fee509, 0x14999001, 0x19a699bf, + 0x0f0204b3, 0x009a457e, 0x0700a033, 0x900415f0, 0x04b30100, 0x49fee50a, 0x14999001, 0x19a699bf, 0x0a150bf4, 0x7e1bb201, 0x3300950a, 0xf80a1fa0, 0x8d233e09, 0xfe2ebf00, 0x99900149, 0xdf99bf10, 0xbfffffff, 0xeffd1f0a, 0x0099b904, 0xf09419ff, 0x96f00b9c, 0x1e94b601, 0xa0059efd, 0x8d233e29, 0xfe1f0a00, 0x99900149, 0xd99fbf18, 0x000005dc, 0xf9a699bf, 0x7e070bf4, 0xfb003a31, 0x30f40c35, @@ -1198,7 +1198,7 @@ 0x0590ff10, 0x0069f07e, 0x94f119bf, 0x40a0ffff, 0x313e59a0, 0xfab20094, 0x0095f47e, 0x0094c83e, 0x0d00a033, 0x5c01ad33, 0x91ae3e03, 0x33b0bf00, 0x330c0190, 0x3e2f0294, 0xfe00919e, 0x010a0141, 0xb2181190, 0x94ef7e1b, 0x1fad3300, 0x1fbf033f, 0x09fffe09, 0x049fff95, 0xa23e10a0, 0x04f10091, - 0x2a3201ff, 0x0a7e0bb2, 0xc83e0095, 0x9a320094, 0x0094ef7e, 0x0094c83e, 0x237efab2, 0xc83e0095, + 0x2a3203ff, 0x0a7e0bb2, 0xc83e0095, 0x9a320094, 0x0094ef7e, 0x0094c83e, 0x237efab2, 0xc83e0095, 0x9cd30094, 0xbf000029, 0x0000df39, 0x080a2000, 0xf5049ffd, 0x0a02f50b, 0x001d3303, 0x40fe02ef, 0x014cfe01, 0x90280090, 0x0bb22ccc, 0x900142fe, 0x2ab22422, 0x0073477e, 0x9670097f, 0x0b9cf003, 0x7e079194, 0x1800010e, 0x087e5830, 0x00330001, 0x1fb20a00, 0x00924d3e, 0xa4732a7f, 0x19b20a00, @@ -1212,7 +1212,7 @@ 0x0093513e, 0xffc7ff49, 0x95f194f9, 0x1c3e0800, 0xff490093, 0x94f9ffc7, 0x100095f1, 0xfe3fff8f, 0xe5049ffd, 0x3ec0009f, 0x49009351, 0xf9ffc7ff, 0x0095f194, 0x93433e08, 0xc7ff4900, 0xf194f9ff, 0x8f100095, 0xfdfe3fff, 0x008f049f, 0x9fff0100, 0x299cd9f5, 0x99180000, 0x00903350, 0x0000890f, - 0x95f9ff02, 0x00936f3e, 0xfdffff89, 0xa094f9ff, 0x94313e49, 0x14a63000, 0x01480cf5, 0xd9ffafc4, + 0x95f9ff02, 0x00936f3e, 0xfdffff89, 0xa094f9ff, 0x94313e49, 0x16a63000, 0x01480cf5, 0xd9ffafc4, 0x000004d0, 0xd9e89fbc, 0x0000299c, 0xefc7080a, 0x989fbc3b, 0xbb96efc7, 0x94f0059f, 0x2b0bf501, 0xff29c401, 0x010defe7, 0x0a029b54, 0xf5bf6604, 0xf0011918, 0xb9e400f3, 0xf9bcffff, 0x04c6b0c2, 0x0c090df4, 0x93cb3e04, 0xe44da000, 0xc4ffffba, 0xebe703e9, 0x94330142, 0xbabc1200, 0x29bcd9b0, @@ -1248,7 +1248,7 @@ 0x94f0e0ef, 0xbcff0f1f, 0xf9bc909d, 0x05febb95, 0xfd049dbb, 0x99b904fc, 0x04fdbb00, 0xfd049afd, 0xb9a0059f, 0x900149fe, 0x9fbf2099, 0x0005dcd9, 0xa699bf00, 0x070bf4f9, 0x003a317e, 0xf41c15fb, 0xdcd9f430, 0xf9000005, 0xb299bf82, 0x014ffed1, 0xa02cff90, 0x92dd3ff9, 0x1f0003ff, 0xf0351709, - 0x02f03501, 0xb6b2f920, 0xa5b2e3b2, 0x1900d433, 0x000528db, 0x7e240c00, 0x09000b7e, 0x200a3209, + 0x02f03501, 0xb6b2f920, 0xa5b2e3b2, 0x1900d433, 0x000530db, 0x7e240c00, 0x09000b7e, 0x200a3209, 0x98823e19, 0x30030a00, 0x0cf409d6, 0x0147fe78, 0xb2ffc4c4, 0x90043df8, 0x793e2477, 0x09c40098, 0x947bb2ff, 0x040c0292, 0x3da026bc, 0x96d27ed4, 0x1fa43300, 0xc47fbf6b, 0x94a607f9, 0xc75e18f4, 0x991223f9, 0x01963001, 0xc7520cf4, 0xe9c42ffe, 0xc8893cff, 0xc78afdc7, 0xd93c85f9, 0xf49c2690, @@ -1570,11 +1570,11 @@ 0x00000000, 0x00000001, 0x0000000e, 0x00000000, 0x08000000, 0x08400000, 0x08800000, 0x08c300a7, 0x09000000, 0x09400000, 0x09800000, 0x09c00000, 0x0a01c000, 0x0a404038, 0x0a804040, 0x0ac04048, 0x0b004050, 0x0b420058, 0x0b8201ab, 0x11800000, 0x11c00000, 0x12000000, 0x12400000, 0x12800000, - 0x12c00000, 0x00000001, 0x00001c08, 0x00101c09, 0x00201c0a, 0x0000bd08, 0x00209d09, 0x00309d0a, - 0x00011f08, 0x00113e09, 0x00311e0a, 0x00010309, 0x00000000, 0x0000ffff, 0x00003b00, 0x46020f1f, - 0x43010f1f, 0x44020f1f, 0x45020f1f, 0x601207ef, 0x601307ef, 0x601407ef, 0x601507ef, 0x801607ef, - 0x253207c2, 0x25330fc2, 0x25340fc2, 0x25350fc2, 0x1152079d, 0x1253079d, 0x7014079d, 0x7015079d, - 0x601203c8, 0x601307c8, 0x601407c8, 0xbb150720, 0x02172701, 0x00000000, 0x00000000, 0x00000000, + 0x12c00000, 0x00000000, 0x00000000, 0x00000001, 0x00001c08, 0x00101c09, 0x00201c0a, 0x0000bd08, + 0x00209d09, 0x00309d0a, 0x00011f08, 0x00113e09, 0x00311e0a, 0x00010309, 0x00000000, 0x0000ffff, + 0x00003b00, 0x46020f1f, 0x43010f1f, 0x44020f1f, 0x45020f1f, 0x601207ef, 0x601307ef, 0x601407ef, + 0x601507ef, 0x801607ef, 0x253207c2, 0x25330fc2, 0x25340fc2, 0x25350fc2, 0x1152079d, 0x1253079d, + 0x7014079d, 0x7015079d, 0x601203c8, 0x601307c8, 0x601407c8, 0xbb150720, 0x02172701, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, @@ -2269,8 +2269,8 @@ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0xb32dc4cc, 0x58018cca, 0x7c52cad0, 0x4a5277fe, 0x59305452, 0xfe64d88a, 0xe474c23b, 0xfee62bd9, - 0x705ea2e7, 0x0577e70f, 0xcf75f41f, 0xfe6e071a, 0xd0954f7e, 0x7caea789, 0x40b32eb9, 0x80368ac3, + 0xf0cc97fc, 0xc5e27e17, 0x63cc4ffc, 0xc48564fa, 0x6073f3d9, 0x573ea3ef, 0xf0764322, 0xf8dacef7, + 0x956b7a40, 0x90bcaaf7, 0xdea25edb, 0x9aaef423, 0xe0830635, 0xb9c7326b, 0x27f96395, 0x7078f754, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/common/nvswitch/kernel/inc/soe/soe_priv_nvswitch.h nvidia-open-gpu-kernel-modules-535.161.08/src/common/nvswitch/kernel/inc/soe/soe_priv_nvswitch.h --- nvidia-open-gpu-kernel-modules-525.147.05/src/common/nvswitch/kernel/inc/soe/soe_priv_nvswitch.h 2023-10-25 20:20:20.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/common/nvswitch/kernel/inc/soe/soe_priv_nvswitch.h 2024-03-05 22:12:35.000000000 +0000 @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 2018-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2018-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/common/nvswitch/kernel/inforom/ifrbbx_nvswitch.c nvidia-open-gpu-kernel-modules-535.161.08/src/common/nvswitch/kernel/inforom/ifrbbx_nvswitch.c --- nvidia-open-gpu-kernel-modules-525.147.05/src/common/nvswitch/kernel/inforom/ifrbbx_nvswitch.c 2023-10-25 20:20:20.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/common/nvswitch/kernel/inforom/ifrbbx_nvswitch.c 2024-03-05 22:12:36.000000000 +0000 @@ -124,7 +124,7 @@ status = device->hal.nvswitch_bbx_get_sxid(device, params); if (status != NVL_SUCCESS) { - NVSWITCH_PRINT(device, ERROR, "nvswitch_bbx_get_sxid failed, status=%d\n", status); + NVSWITCH_PRINT(device, ERROR, "nvswitch_inforom_bbx_load failed, status=%d\n", status); } return status; diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/common/nvswitch/kernel/inforom/ifrnvlink_nvswitch.c nvidia-open-gpu-kernel-modules-535.161.08/src/common/nvswitch/kernel/inforom/ifrnvlink_nvswitch.c --- nvidia-open-gpu-kernel-modules-525.147.05/src/common/nvswitch/kernel/inforom/ifrnvlink_nvswitch.c 2023-10-25 20:20:20.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/common/nvswitch/kernel/inforom/ifrnvlink_nvswitch.c 2024-03-05 22:12:36.000000000 +0000 @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 2019-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2019 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/common/nvswitch/kernel/inforom/inforom_nvl_v3_nvswitch.c nvidia-open-gpu-kernel-modules-535.161.08/src/common/nvswitch/kernel/inforom/inforom_nvl_v3_nvswitch.c --- nvidia-open-gpu-kernel-modules-525.147.05/src/common/nvswitch/kernel/inforom/inforom_nvl_v3_nvswitch.c 2023-10-25 20:20:20.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/common/nvswitch/kernel/inforom/inforom_nvl_v3_nvswitch.c 2024-03-05 22:12:37.000000000 +0000 @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 2019-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2019-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/common/nvswitch/kernel/inforom/inforom_nvl_v4_nvswitch.c nvidia-open-gpu-kernel-modules-535.161.08/src/common/nvswitch/kernel/inforom/inforom_nvl_v4_nvswitch.c --- nvidia-open-gpu-kernel-modules-525.147.05/src/common/nvswitch/kernel/inforom/inforom_nvl_v4_nvswitch.c 2023-10-25 20:20:20.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/common/nvswitch/kernel/inforom/inforom_nvl_v4_nvswitch.c 2024-03-05 22:12:37.000000000 +0000 @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 2019-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2019-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/common/nvswitch/kernel/inforom/inforom_nvswitch.c nvidia-open-gpu-kernel-modules-535.161.08/src/common/nvswitch/kernel/inforom/inforom_nvswitch.c --- nvidia-open-gpu-kernel-modules-525.147.05/src/common/nvswitch/kernel/inforom/inforom_nvswitch.c 2023-10-25 20:20:20.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/common/nvswitch/kernel/inforom/inforom_nvswitch.c 2024-03-05 22:12:37.000000000 +0000 @@ -516,6 +516,7 @@ fsRet = *(NvU32*)pDmaBuf; if (fsRet != NV_OK) { + status = -NVL_IO_ERROR; NVSWITCH_PRINT(device, ERROR, "%s: FS error %x. Filename: %3s\n", __FUNCTION__, fsRet, pParams->fileName); } @@ -613,6 +614,7 @@ fsRet = *(NvU32*)pDmaBuf; if (fsRet != NV_OK) { + status = -NVL_IO_ERROR; NVSWITCH_PRINT(device, ERROR, "%s: FS returned %x. Filename: %3s\n", __FUNCTION__, fsRet, pParams->fileName); } @@ -623,11 +625,6 @@ ifr_dma_free_and_exit: nvswitch_os_free_contig_memory(device->os_handle, pDmaBuf, transferSize); - if (status != NV_OK) - { - return status; - } - return status; } diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/common/nvswitch/kernel/lr10/intr_lr10.c nvidia-open-gpu-kernel-modules-535.161.08/src/common/nvswitch/kernel/lr10/intr_lr10.c --- nvidia-open-gpu-kernel-modules-525.147.05/src/common/nvswitch/kernel/lr10/intr_lr10.c 2023-10-25 20:20:21.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/common/nvswitch/kernel/lr10/intr_lr10.c 2024-03-05 22:12:38.000000000 +0000 @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 2018-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2018-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/common/nvswitch/kernel/lr10/link_lr10.c nvidia-open-gpu-kernel-modules-535.161.08/src/common/nvswitch/kernel/lr10/link_lr10.c --- nvidia-open-gpu-kernel-modules-525.147.05/src/common/nvswitch/kernel/lr10/link_lr10.c 2023-10-25 20:20:21.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/common/nvswitch/kernel/lr10/link_lr10.c 2024-03-05 22:12:38.000000000 +0000 @@ -2215,6 +2215,7 @@ NvU32 lineRate = 0; NVLINK_CONFIG_DATA_LINKENTRY *vbios_link_entry = NULL; NVSWITCH_BIOS_NVLINK_CONFIG *bios_config; + NvU32 base_entry; bios_config = nvswitch_get_bios_nvlink_config(device); if ((bios_config == NULL) || (bios_config->bit_address == 0)) @@ -2235,14 +2236,17 @@ } else { - vbios_link_entry = &bios_config->link_vbios_entry[bios_config->link_base_entry_assigned][link->linkNumber]; + base_entry = bios_config->link_base_entry_assigned; + + vbios_link_entry = &bios_config->link_vbios_entry[base_entry][link->linkNumber]; } + regval = NVSWITCH_LINK_RD32_LR10(device, link->linkNumber, NVLIPT_LNK, + _NVLIPT_LNK_CTRL_SYSTEM_LINK, _CLK_CTRL); + // LINE_RATE SYSTEM register if (device->regkeys.nvlink_speed_control != NV_SWITCH_REGKEY_SPEED_CONTROL_SPEED_DEFAULT) { - regval = NVSWITCH_LINK_RD32_LR10(device, link->linkNumber, NVLIPT_LNK, - _NVLIPT_LNK_CTRL_SYSTEM_LINK, _CLK_CTRL); lineRate = _nvswitch_get_nvlink_linerate_lr10(device, device->regkeys.nvlink_speed_control); regval = FLD_SET_DRF_NUM(_NVLIPT_LNK_CTRL_SYSTEM_LINK, _CLK_CTRL, _LINE_RATE, lineRate, regval); @@ -2580,6 +2584,7 @@ chip_device->bDisabledRemoteEndLinkMaskCached = NV_TRUE; } + // return NV_TRUE if the link is inside of disabledRemoteEndLinkMask return ((BIT64(link->linkNumber) & chip_device->disabledRemoteEndLinkMask) != 0); #else return NV_FALSE; diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/common/nvswitch/kernel/lr10/lr10.c nvidia-open-gpu-kernel-modules-535.161.08/src/common/nvswitch/kernel/lr10/lr10.c --- nvidia-open-gpu-kernel-modules-525.147.05/src/common/nvswitch/kernel/lr10/lr10.c 2023-10-25 20:20:22.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/common/nvswitch/kernel/lr10/lr10.c 2024-03-05 22:12:38.000000000 +0000 @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 2018-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2018-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -22,6 +22,7 @@ */ #include "common_nvswitch.h" +#include "bios_nvswitch.h" #include "error_nvswitch.h" #include "regkey_nvswitch.h" #include "haldef_nvswitch.h" @@ -3990,7 +3991,7 @@ nvlink_link *link; link = nvswitch_get_link(device, linkId); - if (nvswitch_is_link_in_reset(device, link)) + if ((link == NULL) || nvswitch_is_link_in_reset(device, link)) { return NV_FALSE; } @@ -6726,6 +6727,25 @@ } NvBool +nvswitch_is_bios_supported_lr10 +( + nvswitch_device *device +) +{ + return nvswitch_is_spi_supported(device); +} + +NvlStatus +nvswitch_get_bios_size_lr10 +( + nvswitch_device *device, + NvU32 *pSize +) +{ + return nvswitch_bios_read_size(device, pSize); +} + +NvBool nvswitch_is_smbpbi_supported_lr10 ( nvswitch_device *device @@ -7596,10 +7616,10 @@ NV_STATUS status = NV_OK; // check if spi is supported - if (!nvswitch_is_spi_supported(device)) + if (!nvswitch_is_bios_supported(device)) { NVSWITCH_PRINT(device, ERROR, - "%s: SPI is not supported\n", + "%s: BIOS is not supported\n", __FUNCTION__); return -NVL_ERR_NOT_SUPPORTED; } diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/common/nvswitch/kernel/ls10/flcn_ls10.c nvidia-open-gpu-kernel-modules-535.161.08/src/common/nvswitch/kernel/ls10/flcn_ls10.c --- nvidia-open-gpu-kernel-modules-525.147.05/src/common/nvswitch/kernel/ls10/flcn_ls10.c 2023-10-25 20:20:22.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/common/nvswitch/kernel/ls10/flcn_ls10.c 2024-03-05 22:12:39.000000000 +0000 @@ -279,7 +279,6 @@ { NvU32 ctl, ridx, widx, bufferSize; NvBool bWasFull; - NvU64 bios_version; // Only supported on riscv if (!UPROC_ENG_ARCH_FALCON_RISCV(pFlcn)) @@ -355,13 +354,8 @@ break; } - NVSWITCH_PRINT_SXID_NO_BBX(device, NVSWITCH_ERR_HW_SOE_HALT, "SOE HALT data[%d] = 0x%16llx\n", entry, pc); + NVSWITCH_PRINT(device, ERROR, "%s: TRACE[%d] = 0x%16llx\n", __FUNCTION__, entry, pc); } - - // Print VBIOS version at the end - nvswitch_lib_get_bios_version(device, &bios_version); - NVSWITCH_PRINT_SXID_NO_BBX(device, NVSWITCH_ERR_HW_SOE_HALT, - "SOE HALT data[%d] = 0x%16llx\n", entry, bios_version); } // reset trace buffer diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/common/nvswitch/kernel/ls10/intr_ls10.c nvidia-open-gpu-kernel-modules-535.161.08/src/common/nvswitch/kernel/ls10/intr_ls10.c --- nvidia-open-gpu-kernel-modules-525.147.05/src/common/nvswitch/kernel/ls10/intr_ls10.c 2023-10-25 20:20:23.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/common/nvswitch/kernel/ls10/intr_ls10.c 2024-03-05 22:12:39.000000000 +0000 @@ -24,6 +24,7 @@ #include "common_nvswitch.h" #include "intr_nvswitch.h" #include "regkey_nvswitch.h" +#include "soe/soe_nvswitch.h" #include "ls10/ls10.h" #include "ls10/minion_ls10.h" @@ -60,6 +61,8 @@ #include "nvswitch/ls10/dev_ctrl_ip_addendum.h" +static void _nvswitch_create_deferred_link_errors_task_ls10(nvswitch_device *device, NvU32 nvlipt_instance, NvU32 link); + static void _nvswitch_construct_ecc_error_event_ls10 ( @@ -5113,7 +5116,7 @@ // as the IP's registers are off // if (nvswitch_is_link_in_reset(device, link) || - !nvswitch_are_link_clocks_on_ls10(device, link,NVSWITCH_PER_LINK_CLOCK_SET(NCISOCCLK))); + !nvswitch_are_link_clocks_on_ls10(device, link,NVSWITCH_PER_LINK_CLOCK_SET(NCISOCCLK))) { continue; } @@ -5542,6 +5545,8 @@ if (nvswitch_test_flags(pending, bit)) { NVSWITCH_REPORT_FATAL(_HW_DLPL_LTSSM_FAULT_DOWN, "LTSSM Fault Down", NV_FALSE); + error_event.error = INFOROM_NVLINK_DL_LTSSM_FAULT_DOWN_FATAL; + nvswitch_inforom_nvlink_log_error_event(device, &error_event); } } @@ -5667,7 +5672,7 @@ { ls10_device *chip_device = NVSWITCH_GET_CHIP_DEVICE_LS10(device); NVSWITCH_INTERRUPT_LOG_TYPE report = { 0 }; - NvU32 pending, bit; + NvU32 pending, bit, reg; // Only enabled link errors are deffered pending = chip_device->deferredLinkErrors[link].data.nonFatalIntrMask.dl; @@ -5680,9 +5685,20 @@ { // Disable further interrupts nvlink_link *nvlink = nvswitch_get_link(device, link); - nvlink->errorThreshold.bInterruptTrigerred = NV_TRUE; - nvswitch_configure_error_rate_threshold_interrupt_ls10(nvlink, NV_FALSE); - NVSWITCH_REPORT_NONFATAL(_HW_DLPL_RX_SHORT_ERROR_RATE, "RX Short Error Rate"); + if (nvlink == NULL) + { + // If we get here, it is a bug. Disable interrupt and assert. + reg = NVSWITCH_LINK_RD32_LS10(device, link, NVLDL, _NVLDL_TOP, _INTR_NONSTALL_EN); + reg = FLD_SET_DRF_NUM(_NVLDL_TOP, _INTR_NONSTALL_EN, _RX_SHORT_ERROR_RATE, 0, reg); + NVSWITCH_LINK_WR32_LS10(device, link, NVLDL, _NVLDL_TOP, _INTR_NONSTALL_EN, reg); + NVSWITCH_ASSERT(nvlink != NULL); + } + else + { + nvlink->errorThreshold.bInterruptTrigerred = NV_TRUE; + nvswitch_configure_error_rate_threshold_interrupt_ls10(nvlink, NV_FALSE); + NVSWITCH_REPORT_NONFATAL(_HW_DLPL_RX_SHORT_ERROR_RATE, "RX Short Error Rate"); + } } bit = DRF_NUM(_NVLDL_TOP, _INTR, _RX_CRC_COUNTER, 1); @@ -6637,6 +6653,13 @@ bit = DRF_NUM(_NVLIPT_LNK, _INTR_STATUS, _LINKSTATEREQUESTREADYSET, 1); if (nvswitch_test_flags(pending, bit)) { + link = nvswitch_get_link(device, link_id); + if (link == NULL) + { + // If we get here, it's a bug. Assert, then let callers detect unhandled IRQ. + NVSWITCH_ASSERT(link != NULL); + } + nvswitch_clear_flags(&unhandled, bit); if(nvswitch_corelib_get_dl_link_mode_ls10(link, &mode) != NVL_SUCCESS) { @@ -6661,6 +6684,7 @@ // nvswitch_corelib_training_complete_ls10(link); nvswitch_init_buffer_ready(device, link, NV_TRUE); + link->bRxDetected = NV_TRUE; // // Clear out any cached interrupts for the link and update the last link up timestamp @@ -6993,7 +7017,6 @@ return NVL_SUCCESS; } -#if 0 static NvlStatus _nvswitch_service_soe_fatal_ls10 ( @@ -7001,14 +7024,13 @@ ) { // We only support 1 SOE as of LS10. - if (soeService_HAL(device, (PSOE)device->pSoe) != 0) + if (soeService_HAL(device, (PSOE)device->pSoe) != NVL_SUCCESS) { return -NVL_MORE_PROCESSING_REQUIRED; } return NVL_SUCCESS; } -#endif //0 static NvlStatus _nvswitch_service_nvlipt_lnk_fatal_ls10 @@ -7226,6 +7248,7 @@ DRF_NUM(_CTRL, _CPU_INTR_UNITS, _PMGR_HOST, 1) | DRF_NUM(_CTRL, _CPU_INTR_UNITS, _PTIMER, 1) | DRF_NUM(_CTRL, _CPU_INTR_UNITS, _PTIMER_ALARM, 1) | + DRF_NUM(_CTRL, _CPU_INTR_UNITS, _SEC0_INTR0_0, 1) | DRF_NUM(_CTRL, _CPU_INTR_UNITS, _XTL_CPU, 1) | DRF_NUM(_CTRL, _CPU_INTR_UNITS, _XAL_EP, 1) | DRF_NUM(_CTRL, _CPU_INTR_UNITS, _PRIV_RING, 1)); @@ -7260,6 +7283,7 @@ DRF_NUM(_CTRL, _CPU_INTR_UNITS, _PMGR_HOST, 1) | DRF_NUM(_CTRL, _CPU_INTR_UNITS, _PTIMER, 1) | DRF_NUM(_CTRL, _CPU_INTR_UNITS, _PTIMER_ALARM, 1) | + DRF_NUM(_CTRL, _CPU_INTR_UNITS, _SEC0_INTR0_0, 1) | DRF_NUM(_CTRL, _CPU_INTR_UNITS, _XTL_CPU, 1) | DRF_NUM(_CTRL, _CPU_INTR_UNITS, _XAL_EP, 1) | DRF_NUM(_CTRL, _CPU_INTR_UNITS, _PRIV_RING, 1)); @@ -7487,7 +7511,7 @@ val = NVSWITCH_ENG_RD32(device, GIN, , 0, _CTRL, _CPU_INTR_UNITS); if (val != 0) { - NVSWITCH_PRINT(device, INFO, "%s: UNIT interrupts pending = 0x%x\n", + NVSWITCH_PRINT(device, MMIO, "%s: UNIT interrupts pending = 0x%x\n", __FUNCTION__, val); NVSWITCH_ENG_WR32(device, GIN, , 0, _CTRL, _CPU_INTR_LEAF(NV_CTRL_CPU_INTR_UNITS_IDX), val); @@ -7531,6 +7555,19 @@ return_status = status; } } + if (!IS_RTLSIM(device) && !IS_FMODEL(device)) + { + if (FLD_TEST_DRF_NUM(_CTRL, _CPU_INTR_UNITS, _SEC0_INTR0_0, 1, val)) + { + status = _nvswitch_service_soe_fatal_ls10(device); + if (status != NVL_SUCCESS) + { + NVSWITCH_PRINT(device, ERROR, "%s: Problem servicing SOE", + __FUNCTION__); + return_status = status; + } + } + } } // step 4 -- retrigger engine interrupts @@ -7673,15 +7710,6 @@ nvswitch_inforom_nvlink_log_error_event(device, &error_event); } - bit = DRF_NUM(_NVLDL_TOP, _INTR, _LTSSM_FAULT_DOWN, 1); - if (nvswitch_test_flags(pending, bit)) - { - NVSWITCH_REPORT_FATAL(_HW_DLPL_LTSSM_FAULT_DOWN, "LTSSM Fault Down", NV_FALSE); - nvswitch_clear_flags(&unhandled, bit); - error_event.error = INFOROM_NVLINK_DL_LTSSM_FAULT_DOWN_FATAL; - nvswitch_inforom_nvlink_log_error_event(device, &error_event); - } - bit = DRF_NUM(_NVLDL_TOP, _INTR, _LTSSM_PROTOCOL, 1); if (nvswitch_test_flags(pending, bit)) { @@ -7730,8 +7758,8 @@ bit = DRF_NUM(_NVLDL_TOP, _INTR, _LTSSM_FAULT_DOWN, 1); if (nvswitch_test_flags(pending, bit)) { + { dlDeferredIntrLinkMask |= bit; - nvswitch_clear_flags(&unhandled, bit); // // Since reset and drain will reset the link, including clearing @@ -7741,12 +7769,14 @@ // bRequireResetAndDrain = NV_TRUE; } + nvswitch_clear_flags(&unhandled, bit); + } bit = DRF_NUM(_NVLDL_TOP, _INTR, _LTSSM_FAULT_UP, 1); if (nvswitch_test_flags(pending, bit)) { + { dlDeferredIntrLinkMask |= bit; - nvswitch_clear_flags(&unhandled, bit); // // Since reset and drain will reset the link, including clearing @@ -7756,6 +7786,8 @@ // bRequireResetAndDrain = NV_TRUE; } + nvswitch_clear_flags(&unhandled, bit); + } if (bRequireResetAndDrain) { @@ -7800,8 +7832,8 @@ NVSWITCH_INTERRUPT_LOG_TYPE report = { 0 }; NvU32 pending, unhandled, minionIntr, linkIntr, reg, enabledLinks, bit; NvU32 localLinkIdx, link; - ls10_device *chip_device = NVSWITCH_GET_CHIP_DEVICE_LS10(device); MINION_LINK_INTR minionLinkIntr = { 0 }; + ls10_device *chip_device = NVSWITCH_GET_CHIP_DEVICE_LS10(device); // // _MINION_MINION_INTR shows all interrupts currently at the host on this minion diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/common/nvswitch/kernel/ls10/link_ls10.c nvidia-open-gpu-kernel-modules-535.161.08/src/common/nvswitch/kernel/ls10/link_ls10.c --- nvidia-open-gpu-kernel-modules-525.147.05/src/common/nvswitch/kernel/ls10/link_ls10.c 2023-10-25 20:20:23.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/common/nvswitch/kernel/ls10/link_ls10.c 2024-03-05 22:12:40.000000000 +0000 @@ -41,6 +41,11 @@ #include "nvswitch/ls10/dev_minion_ip_addendum.h" #include "ls10/minion_nvlink_defines_public_ls10.h" +#define NV_NVLINK_TLREQ_TIMEOUT_ACTIVE 10000 +#define NV_NVLINK_TLREQ_TIMEOUT_SHUTDOWN 10 +#define NV_NVLINK_TLREQ_TIMEOUT_RESET 4 +#define NV_NVLINK_TLREQ_TIMEOUT_L2 5 + static void _nvswitch_configure_reserved_throughput_counters ( @@ -144,7 +149,7 @@ if (nvswitch_lib_get_bios_version(device, &biosVersion) != NVL_SUCCESS) { NVSWITCH_PRINT(device, WARN, "%s Get VBIOS version failed.\n", - __FUNCTION__); + __FUNCTION__); biosVersion = 0; } @@ -557,7 +562,7 @@ NvU32 clocksMask = NVSWITCH_PER_LINK_CLOCK_SET(RXCLK)|NVSWITCH_PER_LINK_CLOCK_SET(TXCLK)| NVSWITCH_PER_LINK_CLOCK_SET(NCISOCCLK); nvlink_link *link = nvswitch_get_link(device, linkNumber); - if (nvswitch_is_link_in_reset(device, link)) + if ((link == NULL) || nvswitch_is_link_in_reset(device, link)) { return; } @@ -1131,6 +1136,29 @@ } void +nvswitch_get_error_rate_threshold_ls10 +( + nvlink_link *link +) +{ + nvswitch_device *device = link->dev->pDevInfo; + NvU32 linkNumber = link->linkNumber; + NvU32 crcRegVal; + + crcRegVal = NVSWITCH_LINK_RD32_LS10(device, linkNumber, NVLDL, + _NVLDL_RX, _ERROR_RATE_CTRL); + + link->errorThreshold.thresholdMan = DRF_VAL(_NVLDL_RX, _ERROR_RATE_CTRL, _SHORT_THRESHOLD_MAN, + crcRegVal); + link->errorThreshold.thresholdExp = DRF_VAL(_NVLDL_RX, _ERROR_RATE_CTRL, _SHORT_THRESHOLD_EXP, + crcRegVal); + link->errorThreshold.timescaleMan = DRF_VAL(_NVLDL_RX, _ERROR_RATE_CTRL, _SHORT_TIMESCALE_MAN, + crcRegVal); + link->errorThreshold.timescaleExp = DRF_VAL(_NVLDL_RX, _ERROR_RATE_CTRL, _SHORT_TIMESCALE_EXP, + crcRegVal); +} + +void nvswitch_set_error_rate_threshold_ls10 ( nvlink_link *link, @@ -1183,7 +1211,6 @@ crcRegVal &= ~shortRateMask; crcRegVal |= crcShortRegkeyVal; - link->errorThreshold.bUserConfig = NV_FALSE; link->errorThreshold.bInterruptTrigerred = NV_FALSE; } @@ -1479,7 +1506,7 @@ NvU32 link_state_request; NvU32 link_state; NvU32 stat_data = 0; - NvU32 link_intr_subcode = 0; + NvU32 link_intr_subcode = MINION_OK; if (!NVSWITCH_IS_LINK_ENG_VALID_LS10(device, NVLDL, link->linkNumber)) { @@ -1516,25 +1543,31 @@ NV_NVLSTAT_MN00, 0, &stat_data) == NVL_SUCCESS) { link_intr_subcode = DRF_VAL(_NVLSTAT, _MN00, _LINK_INTR_SUBCODE, stat_data); - } - if ((link_state == NV_NVLIPT_LNK_CTRL_LINK_STATE_REQUEST_STATUS_MINION_REQUEST_FAIL) && - (link_intr_subcode == MINION_ALARM_BUSY)) - { - NVSWITCH_PRINT(device, INFO, - "%s: Retrying shutdown due to Minion DLCMD Fault subcode = 0x%x\n", - __FUNCTION__, link_intr_subcode); - // - // We retry the shutdown sequence 3 times when we see a MINION_REQUEST_FAIL - // or MINION_ALARM_BUSY - // - retry_count--; + if ((link_state == NV_NVLIPT_LNK_CTRL_LINK_STATE_REQUEST_STATUS_MINION_REQUEST_FAIL) && + (link_intr_subcode == MINION_ALARM_BUSY)) + { + NVSWITCH_PRINT(device, INFO, + "%s: Retrying shutdown due to Minion DLCMD Fault subcode = 0x%x\n", + __FUNCTION__, link_intr_subcode); + // + // We retry the shutdown sequence 3 times when we see a MINION_REQUEST_FAIL + // or MINION_ALARM_BUSY + // + retry_count--; + } + else + { + break; + } } else { - break; + // Querying MINION for link_intr_subcode failed so retry + retry_count--; } + } while (retry_count); NVSWITCH_PRINT(device, ERROR, @@ -1556,11 +1589,17 @@ NvU32 link_state_request; NvU32 link_state; NvU32 stat_data; - NvU32 link_intr_subcode; + NvU32 link_intr_subcode = MINION_OK; nvswitch_execute_unilateral_link_shutdown_ls10(link); nvswitch_corelib_clear_link_state_ls10(link); + // + // When a link faults there could be a race between the driver requesting + // reset and MINION processing Emergency Shutdown. Minion will notify if + // such a collision happens and will deny the reset request, so try the + // request up to 3 times + // do { status = nvswitch_request_tl_link_state_ls10(link, @@ -1583,24 +1622,29 @@ NV_NVLSTAT_MN00, 0, &stat_data) == NVL_SUCCESS) { link_intr_subcode = DRF_VAL(_NVLSTAT, _MN00, _LINK_INTR_SUBCODE, stat_data); - } - if ((link_state == NV_NVLIPT_LNK_CTRL_LINK_STATE_REQUEST_STATUS_MINION_REQUEST_FAIL) && - (link_intr_subcode == MINION_ALARM_BUSY)) - { + if ((link_state == NV_NVLIPT_LNK_CTRL_LINK_STATE_REQUEST_STATUS_MINION_REQUEST_FAIL) && + (link_intr_subcode == MINION_ALARM_BUSY)) + { - status = nvswitch_request_tl_link_state_ls10(link, - NV_NVLIPT_LNK_CTRL_LINK_STATE_REQUEST_REQUEST_RESET, NV_TRUE); + status = nvswitch_request_tl_link_state_ls10(link, + NV_NVLIPT_LNK_CTRL_LINK_STATE_REQUEST_REQUEST_RESET, NV_TRUE); - // - // We retry the shutdown sequence 3 times when we see a MINION_REQUEST_FAIL - // or MINION_ALARM_BUSY - // - retry_count--; + // + // We retry the shutdown sequence 3 times when we see a MINION_REQUEST_FAIL + // or MINION_ALARM_BUSY + // + retry_count--; + } + else + { + break; + } } else { - break; + // failed to query minion for the link_intr_subcode so retry + retry_count--; } } } while(retry_count); @@ -1611,15 +1655,18 @@ "%s: NvLink Reset has failed for link %d\n", __FUNCTION__, link->linkNumber); - // Re-register links. - status = nvlink_lib_register_link(device->nvlink_device, link); - if (status != NVL_SUCCESS) - { - nvswitch_destroy_link(link); - return status; - } return status; } + + status = nvswitch_launch_ALI_link_training(device, link, NV_FALSE); + if (status != NVL_SUCCESS) + { + NVSWITCH_PRINT(device, ERROR, + "%s: NvLink failed to request ACTIVE for link %d\n", + __FUNCTION__, link->linkNumber); + return status; + } + return NVL_SUCCESS; } @@ -1671,6 +1718,39 @@ return NV_TRUE; } +static +NvlStatus +_nvswitch_tl_request_get_timeout_value_ls10 +( + nvswitch_device *device, + NvU32 tlLinkState, + NvU32 *timeoutVal +) +{ + switch (tlLinkState) + { + case NV_NVLIPT_LNK_CTRL_LINK_STATE_REQUEST_REQUEST_ACTIVE: + *timeoutVal = NV_NVLINK_TLREQ_TIMEOUT_ACTIVE; + break; + case NV_NVLIPT_LNK_CTRL_LINK_STATE_REQUEST_REQUEST_RESET: + *timeoutVal = NV_NVLINK_TLREQ_TIMEOUT_RESET; + break; + case NV_NVLIPT_LNK_CTRL_LINK_STATE_REQUEST_REQUEST_SHUTDOWN: + *timeoutVal = NV_NVLINK_TLREQ_TIMEOUT_SHUTDOWN; + break; + case NV_NVLIPT_LNK_CTRL_LINK_STATE_REQUEST_REQUEST_L2: + *timeoutVal = NV_NVLINK_TLREQ_TIMEOUT_L2; + break; + default: + NVSWITCH_PRINT(device, ERROR, + "%s: Invalid tlLinkState %d provided!\n", + __FUNCTION__, tlLinkState); + return NVL_BAD_ARGS; + } + + return NVL_SUCCESS; +} + NvlStatus nvswitch_request_tl_link_state_ls10 ( @@ -1684,6 +1764,9 @@ NvU32 linkStatus; NvU32 lnkErrStatus; NvU32 bit; + NvU32 timeoutVal; + NVSWITCH_TIMEOUT timeout; + NvBool keepPolling; if (!NVSWITCH_IS_LINK_ENG_VALID_LS10(device, NVLIPT_LNK, link->linkNumber)) { @@ -1717,25 +1800,53 @@ if (bSync) { - // Wait for the TL link state register to complete - status = nvswitch_wait_for_tl_request_ready_lr10(link); + + // setup timeouts for the TL request + status = _nvswitch_tl_request_get_timeout_value_ls10(device, tlLinkState, &timeoutVal); if (status != NVL_SUCCESS) { - return status; + return NVL_ERR_INVALID_STATE; } - // Check for state requested - linkStatus = NVSWITCH_LINK_RD32_LS10(device, link->linkNumber, + nvswitch_timeout_create(NVSWITCH_INTERVAL_1MSEC_IN_NS * timeoutVal, &timeout); + status = NVL_MORE_PROCESSING_REQUIRED; + + do + { + keepPolling = (nvswitch_timeout_check(&timeout)) ? NV_FALSE : NV_TRUE; + + // Check for state requested + linkStatus = NVSWITCH_LINK_RD32_LS10(device, link->linkNumber, NVLIPT_LNK , _NVLIPT_LNK , _CTRL_LINK_STATE_STATUS); - if (DRF_VAL(_NVLIPT_LNK, _CTRL_LINK_STATE_STATUS, _CURRENTLINKSTATE, linkStatus) != - tlLinkState) + if (DRF_VAL(_NVLIPT_LNK, _CTRL_LINK_STATE_STATUS, _CURRENTLINKSTATE, linkStatus) == + tlLinkState) + { + status = NVL_SUCCESS; + break; + } + + nvswitch_os_sleep(1); + } + while(keepPolling); + + // Do one final check if the polling loop didn't see the target linkState + if (status == NVL_MORE_PROCESSING_REQUIRED) { - NVSWITCH_PRINT(device, ERROR, - "%s: TL link state request to state 0x%x for link #%d did not complete!\n", - __FUNCTION__, tlLinkState, link->linkNumber); - return -NVL_ERR_GENERIC; + // Check for state requested + linkStatus = NVSWITCH_LINK_RD32_LS10(device, link->linkNumber, + NVLIPT_LNK , _NVLIPT_LNK , _CTRL_LINK_STATE_STATUS); + + if (DRF_VAL(_NVLIPT_LNK, _CTRL_LINK_STATE_STATUS, _CURRENTLINKSTATE, linkStatus) != + tlLinkState) + { + NVSWITCH_PRINT(device, ERROR, + "%s: TL link state request to state 0x%x for link #%d did not complete!\n", + __FUNCTION__, tlLinkState, link->linkNumber); + return -NVL_ERR_GENERIC; + } } + } return status; diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/common/nvswitch/kernel/ls10/ls10.c nvidia-open-gpu-kernel-modules-535.161.08/src/common/nvswitch/kernel/ls10/ls10.c --- nvidia-open-gpu-kernel-modules-525.147.05/src/common/nvswitch/kernel/ls10/ls10.c 2023-10-25 20:20:23.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/common/nvswitch/kernel/ls10/ls10.c 2024-03-05 22:12:40.000000000 +0000 @@ -27,6 +27,7 @@ #include "regkey_nvswitch.h" #include "haldef_nvswitch.h" #include "nvlink_inband_msg.h" +#include "rmsoecmdif.h" #include "ls10/ls10.h" #include "lr10/lr10.h" @@ -64,6 +65,8 @@ #include "nvswitch/ls10/dev_multicasttstate_ip.h" #include "nvswitch/ls10/dev_reductiontstate_ip.h" #include "ls10/minion_nvlink_defines_public_ls10.h" +#include "nvswitch/ls10/dev_pmgr.h" +#include "nvswitch/ls10/dev_timer_ip.h" #define NVSWITCH_IFR_MIN_BIOS_VER_LS10 0x9610170000ull #define NVSWITCH_SMBPBI_MIN_BIOS_VER_LS10 0x9610220000ull @@ -1423,6 +1426,7 @@ NvBool bAreDlClocksOn; NVSWITCH_TIMEOUT timeout; + if (link_mask == 0) { NVSWITCH_PRINT(device, ERROR, "%s: Invalid link_mask 0\n", @@ -2784,6 +2788,7 @@ return NVSWITCH_LINKS_PER_NVLIPT_LS10; } + NvlStatus nvswitch_ctrl_get_fom_values_ls10 ( @@ -3015,6 +3020,41 @@ return NV_FALSE; } +NvBool +nvswitch_is_bios_supported_ls10 +( + nvswitch_device *device +) +{ + if (IS_RTLSIM(device) || IS_EMULATION(device) || IS_FMODEL(device)) + { + NVSWITCH_PRINT(device, INFO, + "BIOS is not supported on non-silicon platforms\n"); + return NV_FALSE; + } + + if (!nvswitch_is_soe_supported(device)) + { + NVSWITCH_PRINT(device, INFO, + "BIOS is not supported since SOE is not supported\n"); + return NV_FALSE; + } + + return NV_TRUE; +} + +NvlStatus +nvswitch_get_bios_size_ls10 +( + nvswitch_device *device, + NvU32 *pSize +) +{ + *pSize = SOE_CORE_BIOS_SIZE_LS10; + + return NVL_SUCCESS; +} + /* * @Brief : Check if SMBPBI is supported * @@ -5753,7 +5793,7 @@ // Configure the interrupt nvswitch_configure_error_rate_threshold_interrupt_ls10(link, - link->errorThreshold.bInterruptEn); + pParams->errorThreshold[link->linkNumber].bInterruptEn); } } FOR_EACH_INDEX_IN_MASK_END; @@ -5779,6 +5819,9 @@ continue; } + // Get the Error threshold + nvswitch_get_error_rate_threshold_ls10(link); + pParams->errorThreshold[link->linkNumber].thresholdMan = link->errorThreshold.thresholdMan; pParams->errorThreshold[link->linkNumber].thresholdExp = diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/common/nvswitch/kernel/ls10/minion_ls10.c nvidia-open-gpu-kernel-modules-535.161.08/src/common/nvswitch/kernel/ls10/minion_ls10.c --- nvidia-open-gpu-kernel-modules-525.147.05/src/common/nvswitch/kernel/ls10/minion_ls10.c 2023-10-25 20:20:23.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/common/nvswitch/kernel/ls10/minion_ls10.c 2024-03-05 22:12:40.000000000 +0000 @@ -954,14 +954,15 @@ ) { NvU32 localLinkNumber = link->linkNumber % NVSWITCH_LINKS_PER_MINION_LS10; - if (!nvswitch_minion_get_dl_status(device, link->linkNumber, - NV_NVLSTAT_MN00, 0, &(params->dlstatMn00)) == NVL_SUCCESS) + if (nvswitch_minion_get_dl_status(device, link->linkNumber, + NV_NVLSTAT_MN00, 0, &(params->dlstatMn00)) != NVL_SUCCESS) { NVSWITCH_PRINT(device, INFO,"%s : Failed to poll DLSTAT _MN00 register for (%s):(%d)\n", __FUNCTION__, device->name, link->linkNumber); } - if (!nvswitch_minion_get_dl_status(device, link->linkNumber, NV_NVLSTAT_UC01, 0, &(params->dlstatUc01))) + if (nvswitch_minion_get_dl_status(device, link->linkNumber, + NV_NVLSTAT_UC01, 0, &(params->dlstatUc01)) != NVL_SUCCESS) { NVSWITCH_PRINT(device, INFO,"%s : Failed to poll DLSTAT UC01 register for (%s):(%d)\n", __FUNCTION__, device->name, link->linkNumber); diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/common/nvswitch/kernel/ls10/soe_ls10.c nvidia-open-gpu-kernel-modules-535.161.08/src/common/nvswitch/kernel/ls10/soe_ls10.c --- nvidia-open-gpu-kernel-modules-525.147.05/src/common/nvswitch/kernel/ls10/soe_ls10.c 2023-10-25 20:20:23.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/common/nvswitch/kernel/ls10/soe_ls10.c 2024-03-05 22:12:40.000000000 +0000 @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 2020-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2020-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -39,9 +39,6 @@ #include "nvswitch/ls10/dev_nvlsaw_ip_addendum.h" #include "nvswitch/ls10/dev_riscv_pri.h" -#include "nvswitch/ls10/dev_nport_ip.h" -#include "nvswitch/ls10/dev_npg_ip.h" - #include "flcn/flcnable_nvswitch.h" #include "flcn/flcn_nvswitch.h" #include "rmflcncmdif_nvswitch.h" @@ -182,7 +179,7 @@ NVSWITCH_PRINT(device, ERROR, "RESET_PLM : 0x%08x\n", regRESET_PLM); NVSWITCH_PRINT(device, ERROR, "EXE_PLM : 0x%08x\n", regEXE_PLM); } -#endif // defined(DEVELOP) || defined(DEBUG) || defined(NV_MODS) +#endif // defined(DEVELOP) || defined(DEBUG) || defined(NV_MODS) /* * @Brief : Attach or Detach driver to SOE Queues @@ -226,13 +223,20 @@ ) { NvU32 val; + NvBool bSoeAttached; val = NVSWITCH_SAW_RD32_LS10(device, _NVLSAW, _SOE_ATTACH_DETACH); + bSoeAttached = FLD_TEST_DRF(_NVLSAW, _SOE_ATTACH_DETACH, _STATUS, _ATTACHED, val); - return FLD_TEST_DRF(_NVLSAW, _SOE_ATTACH_DETACH, _STATUS, _ATTACHED, val); + return bSoeAttached; } -// BACK UP Nport state and reset NPORT +/* + * @Brief : Backup NPORT state and issue NPORT reset + * + * @param[in] device + * @param[in] nport + */ NvlStatus nvswitch_soe_issue_nport_reset_ls10 ( @@ -240,7 +244,7 @@ NvU32 nport ) { - FLCN *pFlcn = device->pSoe->pFlcn; + FLCN *pFlcn = device->pSoe->pFlcn; NvU32 cmdSeqDesc = 0; NV_STATUS status; RM_FLCN_CMD_SOE cmd; @@ -256,7 +260,7 @@ pNportReset->nport = nport; pNportReset->cmdType = RM_SOE_CORE_CMD_ISSUE_NPORT_RESET; - nvswitch_timeout_create(NVSWITCH_INTERVAL_1SEC_IN_NS * 5, &timeout); + nvswitch_timeout_create(NVSWITCH_INTERVAL_5MSEC_IN_NS, &timeout); status = flcnQueueCmdPostBlocking(device, pFlcn, (PRM_FLCN_CMD)&cmd, NULL, // pMsg @@ -274,7 +278,12 @@ return NVL_SUCCESS; } -// De-reset NPORT and restore NPORT state +/* + * @Brief : De-Assert NPORT reset and restore NPORT state + * + * @param[in] device + * @param[in] nport + */ NvlStatus nvswitch_soe_restore_nport_state_ls10 ( @@ -292,13 +301,13 @@ nvswitch_os_memset(&cmd, 0, sizeof(cmd)); cmd.hdr.unitId = RM_SOE_UNIT_CORE; - cmd.hdr.size = sizeof(cmd); + cmd.hdr.size = RM_SOE_CMD_SIZE(CORE, NPORT_STATE); pNportState = &cmd.cmd.core.nportState; pNportState->nport = nport; pNportState->cmdType = RM_SOE_CORE_CMD_RESTORE_NPORT_STATE; - nvswitch_timeout_create(NVSWITCH_INTERVAL_1SEC_IN_NS * 5, &timeout); + nvswitch_timeout_create(NVSWITCH_INTERVAL_5MSEC_IN_NS, &timeout); status = flcnQueueCmdPostBlocking(device, pFlcn, (PRM_FLCN_CMD)&cmd, NULL, // pMsg @@ -346,7 +355,7 @@ nvswitch_os_memset(&cmd, 0, sizeof(cmd)); cmd.hdr.unitId = RM_SOE_UNIT_CORE; - cmd.hdr.size = RM_SOE_CMD_SIZE(CORE, NPORT_STATE); + cmd.hdr.size = RM_SOE_CMD_SIZE(CORE, NPORT_TPROD_STATE); nportTprodState = &cmd.cmd.core.nportTprodState; nportTprodState->nport = nport; @@ -391,7 +400,7 @@ if (!nvswitch_is_soe_supported(device)) { - NVSWITCH_PRINT(device, INFO, "%s: SOE is not supported. skipping!\n", + NVSWITCH_PRINT(device, INFO, "%s: SOE is not supported\n", __FUNCTION__); return; } @@ -504,8 +513,9 @@ RM_SOE_CORE_CMD_NPORT_FATAL_INTR *pNportIntrDisable; NVSWITCH_GET_BIOS_INFO_PARAMS p = { 0 }; NvlStatus stat; + stat = device->hal.nvswitch_ctrl_get_bios_info(device, &p); - if ((stat != NVL_SUCCESS) || ((p.version & SOE_VBIOS_VERSION_MASK) < + if ((stat != NVL_SUCCESS) || ((p.version & SOE_VBIOS_VERSION_MASK) < SOE_VBIOS_REVLOCK_DISABLE_NPORT_FATAL_INTR)) { NVSWITCH_PRINT(device, ERROR, @@ -515,21 +525,26 @@ SOE_VBIOS_REVLOCK_DISABLE_NPORT_FATAL_INTR); return; } + if (!nvswitch_is_soe_supported(device)) { NVSWITCH_PRINT(device, INFO, "%s: SOE is not supported\n", __FUNCTION__); return; } + pFlcn = device->pSoe->pFlcn; + nvswitch_os_memset(&cmd, 0, sizeof(cmd)); cmd.hdr.unitId = RM_SOE_UNIT_CORE; cmd.hdr.size = RM_SOE_CMD_SIZE(CORE, NPORT_FATAL_INTR); + pNportIntrDisable = &cmd.cmd.core.nportDisableIntr; pNportIntrDisable->cmdType = RM_SOE_CORE_CMD_DISABLE_NPORT_FATAL_INTR; pNportIntrDisable->nport = nport; pNportIntrDisable->nportIntrEnable = nportIntrEnable; pNportIntrDisable->nportIntrType = nportIntrType; + nvswitch_timeout_create(NVSWITCH_INTERVAL_5MSEC_IN_NS, &timeout); status = flcnQueueCmdPostBlocking(device, pFlcn, (PRM_FLCN_CMD)&cmd, @@ -646,7 +661,6 @@ // Detach driver from SOE Queues _nvswitch_soe_attach_detach_driver_ls10(device, NV_FALSE); - return NVL_SUCCESS; } @@ -1326,4 +1340,3 @@ pHal->waitForInitAck = _soeWaitForInitAck_LS10; pHal->i2cAccess = _soeI2CAccess_LS10; } - diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/common/nvswitch/kernel/ls10/therm_ls10.c nvidia-open-gpu-kernel-modules-535.161.08/src/common/nvswitch/kernel/ls10/therm_ls10.c --- nvidia-open-gpu-kernel-modules-525.147.05/src/common/nvswitch/kernel/ls10/therm_ls10.c 2023-10-25 20:20:24.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/common/nvswitch/kernel/ls10/therm_ls10.c 2024-03-05 22:12:40.000000000 +0000 @@ -28,7 +28,6 @@ #include "ls10/therm_ls10.h" #include "error_nvswitch.h" #include "soe/soeiftherm.h" -#include "rmflcncmdif_nvswitch.h" #include "flcn/flcnable_nvswitch.h" #include "flcn/flcn_nvswitch.h" @@ -460,7 +459,7 @@ } // -// nvswitch_ctrl_therm_read_voltage +// nvswitch_therm_read_voltage // // Temperature and voltage are only available on SKUs which have thermal and // voltage sensors. @@ -544,7 +543,7 @@ } // -// nvswitch_ctrl_therm_read_power +// nvswitch_therm_read_power // // Power is only available on SKUs which have thermal and // voltage sensors. diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/common/nvswitch/kernel/nvswitch.c nvidia-open-gpu-kernel-modules-535.161.08/src/common/nvswitch/kernel/nvswitch.c --- nvidia-open-gpu-kernel-modules-525.147.05/src/common/nvswitch/kernel/nvswitch.c 2023-10-25 20:20:24.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/common/nvswitch/kernel/nvswitch.c 2024-03-05 22:12:41.000000000 +0000 @@ -705,6 +705,15 @@ } NvBool +nvswitch_is_bios_supported +( + nvswitch_device *device +) +{ + return device->hal.nvswitch_is_bios_supported(device); +} + +NvBool nvswitch_is_smbpbi_supported ( nvswitch_device *device @@ -1337,7 +1346,6 @@ NvU8 link_num; nvlink_link *link = NULL; NvBool is_blacklisted_by_os = NV_FALSE; - NvU64 mode; if (!NVSWITCH_IS_DEVICE_ACCESSIBLE(device)) { @@ -1500,18 +1508,6 @@ nvswitch_reset_persistent_link_hw_state(device, link_num); - if(_nvswitch_corelib_get_dl_link_mode(link, &mode) != NVL_SUCCESS) - { - NVSWITCH_PRINT(device, ERROR, "%s: nvlipt_lnk_status: Failed to check link mode! LinkId %d\n", - __FUNCTION__, link_num); - } - else if(mode == NVLINK_LINKSTATE_FAULT) - { - NVSWITCH_PRINT(device, INFO, "%s: retraining LinkId %d\n", - __FUNCTION__, link_num); - nvswitch_reset_and_train_link(device, link); - } - // // During Nvswitch initialization, the default L1 thresholds are programmed by the // BIOS from the BIOS tables. Save these L1 Threshold Values in scratch registers @@ -1628,6 +1624,10 @@ ) { NvlStatus retval; + NvlStatus status; + NvU32 link_num; + NvU64 mode; + nvlink_link *link; if (!NVSWITCH_IS_DEVICE_INITIALIZED(device)) { @@ -1639,8 +1639,8 @@ { return retval; } - - if (nvswitch_is_spi_supported(device)) + + if (nvswitch_is_bios_supported(device)) { retval = nvswitch_bios_get_image(device); if (retval != NVL_SUCCESS) @@ -1657,7 +1657,7 @@ else { NVSWITCH_PRINT(device, ERROR, - "%s: Skipping BIOS parsing since SPI is unsupported.\n", + "%s: Skipping BIOS parsing since BIOS is unsupported.\n", __FUNCTION__); } @@ -1669,7 +1669,46 @@ nvswitch_smbpbi_post_init(device); - (void)nvswitch_launch_ALI(device); + // ALI launched by VBIOS on silicon + if (IS_RTLSIM(device) || IS_EMULATION(device) || IS_FMODEL(device)) + { + (void)nvswitch_launch_ALI(device); + } + + // + // There is an edge case where a hypervisor may not send same number + // of reset to switch and GPUs, so try to re-train links in fault + // if possible + // + for (link_num=0; link_num < nvswitch_get_num_links(device); link_num++) + { + // Sanity check + if (!nvswitch_is_link_valid(device, link_num)) + { + continue; + } + + status = nvlink_lib_get_link(device->nvlink_device, link_num, &link); + if (status != NVL_SUCCESS) + { + NVSWITCH_PRINT(device, ERROR, "%s: Failed to get link for LinkId %d\n", + __FUNCTION__, link_num); + continue; + } + + // If the link is in fault then re-train + if(_nvswitch_corelib_get_dl_link_mode(link, &mode) != NVL_SUCCESS) + { + NVSWITCH_PRINT(device, ERROR, "%s: nvlipt_lnk_status: Failed to check link mode! LinkId %d\n", + __FUNCTION__, link_num); + } + else if(mode == NVLINK_LINKSTATE_FAULT) + { + NVSWITCH_PRINT(device, INFO, "%s: retraining LinkId %d\n", + __FUNCTION__, link_num); + nvswitch_reset_and_train_link(device, link); + } + } return NVL_SUCCESS; } @@ -5083,6 +5122,8 @@ CTRL_NVSWITCH_RESERVED_9); NVSWITCH_DEV_CMD_DISPATCH_RESERVED( CTRL_NVSWITCH_RESERVED_10); + NVSWITCH_DEV_CMD_DISPATCH_RESERVED( + CTRL_NVSWITCH_RESERVED_11); NVSWITCH_DEV_CMD_DISPATCH( CTRL_NVSWITCH_GET_TEMPERATURE_LIMIT, _nvswitch_ctrl_therm_get_temperature_limit, @@ -5219,3 +5260,21 @@ return retval; } + +#if defined(DEVELOP) || defined(DEBUG) || defined(NV_MODS) +void nvswitch_assert_log +( + const char *function, + const char *file, + NvU32 line +) +{ + nvswitch_os_assert_log("NVSwitch: Assertion failed in %s() at %s:%d\n", + function, file, line); +} +#else +void nvswitch_assert_log(void) +{ + nvswitch_os_assert_log("NVSwitch: Assertion failed\n"); +} +#endif diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/common/sdk/nvidia/inc/alloc/alloc_access_counter_buffer.h nvidia-open-gpu-kernel-modules-535.161.08/src/common/sdk/nvidia/inc/alloc/alloc_access_counter_buffer.h --- nvidia-open-gpu-kernel-modules-525.147.05/src/common/sdk/nvidia/inc/alloc/alloc_access_counter_buffer.h 1970-01-01 00:00:00.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/common/sdk/nvidia/inc/alloc/alloc_access_counter_buffer.h 2024-03-05 22:14:24.000000000 +0000 @@ -0,0 +1,51 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#pragma once + +#include + +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: alloc/alloc_access_counter_buffer.finn +// + +#include "class/clc365.h" + + +/* + * NV_ACCESS_COUNTER_NOTIFY_BUFFER_ALLOC_PARAMS + * + * Allocation params for ACCESS_COUNTER_NOTIFY_BUFFER. + * This class provides an interface to access counter buffers. + + * accessCounterIndex [IN] + * This parameter specifies index of access counter to which the object should be assigned + * + */ +#define NV_ACCESS_COUNTER_NOTIFY_BUFFER_ALLOC_PARAMS_MESSAGE_ID (0xC365U) + +typedef struct NV_ACCESS_COUNTER_NOTIFY_BUFFER_ALLOC_PARAMS { + NvU32 accessCounterIndex; +} NV_ACCESS_COUNTER_NOTIFY_BUFFER_ALLOC_PARAMS; + diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/common/sdk/nvidia/inc/alloc/alloc_channel.h nvidia-open-gpu-kernel-modules-535.161.08/src/common/sdk/nvidia/inc/alloc/alloc_channel.h --- nvidia-open-gpu-kernel-modules-525.147.05/src/common/sdk/nvidia/inc/alloc/alloc_channel.h 2023-10-25 20:21:39.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/common/sdk/nvidia/inc/alloc/alloc_channel.h 2024-03-05 22:14:24.000000000 +0000 @@ -28,7 +28,7 @@ // // This file was generated with FINN, an NVIDIA coding tool. -// Source file: alloc/alloc_channel.finn +// Source file: alloc/alloc_channel.finn // #include "nvlimits.h" @@ -41,7 +41,6 @@ NvU32 cacheAttrib; } NV_MEMORY_DESC_PARAMS; - /* * NV_CHANNEL_ALLOC_PARAMS.flags values. * @@ -83,6 +82,25 @@ #define NVOS04_FLAGS_VPR_FALSE 0x00000000 #define NVOS04_FLAGS_VPR_TRUE 0x00000001 +/* + * NVOS04_FLAGS_CC_SECURE: + * This flag specifies if channel is intended to be used for + * encryption/decryption of data between SYSMEM <-> VIDMEM. Only CE + * & SEC2 Channels are capable of handling encrypted content and this + * flag will be ignored when CC is disabled or for chips that are not CC + * Capable. + * Reusing VPR index since VPR & CC are mutually exclusive. + * + * NVOS04_FLAGS_CC_SECURE_TRUE: + * The channel will support CC Encryption/Decryption + * + * NVOS04_FLAGS_CC_SECURE_FALSE: + * The channel will not support CC Encryption/Decryption + */ +#define NVOS04_FLAGS_CC_SECURE 2:2 +#define NVOS04_FLAGS_CC_SECURE_FALSE 0x00000000 +#define NVOS04_FLAGS_CC_SECURE_TRUE 0x00000001 + /* @@ -270,6 +288,8 @@ +#define CC_CHAN_ALLOC_IV_SIZE_DWORD 3U +#define CC_CHAN_ALLOC_NONCE_SIZE_DWORD 8U #define NV_CHANNEL_ALLOC_PARAMS_MESSAGE_ID (0x906fU) @@ -300,8 +320,6 @@ NvU32 subDeviceId; NvHandle hObjectEccError; // ECC error context DMA - - NV_DECLARE_ALIGNED(NV_MEMORY_DESC_PARAMS instanceMem, 8); NV_DECLARE_ALIGNED(NV_MEMORY_DESC_PARAMS userdMem, 8); NV_DECLARE_ALIGNED(NV_MEMORY_DESC_PARAMS ramfcMem, 8); @@ -313,6 +331,13 @@ NV_DECLARE_ALIGNED(NV_MEMORY_DESC_PARAMS eccErrorNotifierMem, 8); // reserved NvU32 ProcessID; // reserved NvU32 SubProcessID; // reserved + + // IV used for CPU-side encryption / GPU-side decryption. + NvU32 encryptIv[CC_CHAN_ALLOC_IV_SIZE_DWORD]; // reserved + // IV used for CPU-side decryption / GPU-side encryption. + NvU32 decryptIv[CC_CHAN_ALLOC_IV_SIZE_DWORD]; // reserved + // Nonce used CPU-side signing / GPU-side signature verification. + NvU32 hmacNonce[CC_CHAN_ALLOC_NONCE_SIZE_DWORD]; // reserved } NV_CHANNEL_ALLOC_PARAMS; typedef NV_CHANNEL_ALLOC_PARAMS NV_CHANNELGPFIFO_ALLOCATION_PARAMETERS; diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/common/sdk/nvidia/inc/cc_drv.h nvidia-open-gpu-kernel-modules-535.161.08/src/common/sdk/nvidia/inc/cc_drv.h --- nvidia-open-gpu-kernel-modules-525.147.05/src/common/sdk/nvidia/inc/cc_drv.h 1970-01-01 00:00:00.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/common/sdk/nvidia/inc/cc_drv.h 2024-03-05 22:14:25.000000000 +0000 @@ -0,0 +1,81 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2021-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#pragma once + +#include + +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: cc_drv.finn +// + + + +#include "nvtypes.h" +#include "nvcfg_sdk.h" + +// CLASS NV_CONF_COMPUTE +#define CC_AES_256_GCM_IV_SIZE_BYTES (0xcU) /* finn: Evaluated from "(96 / 8)" */ +#define CC_AES_256_GCM_IV_SIZE_DWORD (0x3U) /* finn: Evaluated from "(CC_AES_256_GCM_IV_SIZE_BYTES / 4)" */ +#define CC_AES_256_GCM_KEY_SIZE_BYTES (0x20U) /* finn: Evaluated from "(256 / 8)" */ +#define CC_AES_256_GCM_KEY_SIZE_DWORD (0x8U) /* finn: Evaluated from "(CC_AES_256_GCM_KEY_SIZE_BYTES / 4)" */ + +#define CC_HMAC_NONCE_SIZE_BYTES (0x20U) /* finn: Evaluated from "(256 / 8)" */ +#define CC_HMAC_NONCE_SIZE_DWORD (0x8U) /* finn: Evaluated from "(CC_HMAC_NONCE_SIZE_BYTES / 4)" */ +#define CC_HMAC_KEY_SIZE_BYTES (0x20U) /* finn: Evaluated from "(256 / 8)" */ +#define CC_HMAC_KEY_SIZE_DWORD (0x8U) /* finn: Evaluated from "(CC_HMAC_KEY_SIZE_BYTES / 4)" */ + + +// Type is shared between CC control calls and RMKeyStore +typedef enum ROTATE_IV_TYPE { + ROTATE_IV_ENCRYPT = 0, // Rotate the IV for encryptBundle + ROTATE_IV_DECRYPT = 1, // Rotate the IV for decryptBundle + ROTATE_IV_HMAC = 2, // Rotate the IV for hmacBundle + ROTATE_IV_ALL_VALID = 3, // Rotate the IV for all valid bundles in the KMB +} ROTATE_IV_TYPE; + +typedef struct CC_AES_CRYPTOBUNDLE { + NvU32 iv[CC_AES_256_GCM_IV_SIZE_DWORD]; + NvU32 key[CC_AES_256_GCM_KEY_SIZE_DWORD]; + NvU32 ivMask[CC_AES_256_GCM_IV_SIZE_DWORD]; +} CC_AES_CRYPTOBUNDLE; +typedef struct CC_AES_CRYPTOBUNDLE *PCC_AES_CRYPTOBUNDLE; + +typedef struct CC_HMAC_CRYPTOBUNDLE { + NvU32 nonce[CC_HMAC_NONCE_SIZE_DWORD]; + NvU32 key[CC_HMAC_KEY_SIZE_DWORD]; +} CC_HMAC_CRYPTOBUNDLE; +typedef struct CC_HMAC_CRYPTOBUNDLE *PCC_HMAC_CRYPTOBUNDLE; + +typedef struct CC_KMB { + CC_AES_CRYPTOBUNDLE encryptBundle; // Bundle of encyption material + + union { + CC_HMAC_CRYPTOBUNDLE hmacBundle; // HMAC bundle used for method stream authenticity + CC_AES_CRYPTOBUNDLE decryptBundle; // Bundle of decryption material + }; + NvBool bIsWorkLaunch; // False if decryption parameters are valid +} CC_KMB; +typedef struct CC_KMB *PCC_KMB; + diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/common/sdk/nvidia/inc/class/cl0000.h nvidia-open-gpu-kernel-modules-535.161.08/src/common/sdk/nvidia/inc/class/cl0000.h --- nvidia-open-gpu-kernel-modules-525.147.05/src/common/sdk/nvidia/inc/class/cl0000.h 2023-10-25 20:21:40.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/common/sdk/nvidia/inc/class/cl0000.h 2024-03-05 22:14:25.000000000 +0000 @@ -27,7 +27,7 @@ // // This file was generated with FINN, an NVIDIA coding tool. -// Source file: class/cl0000.finn +// Source file: class/cl0000.finn // #include "nvlimits.h" diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/common/sdk/nvidia/inc/class/cl0005.h nvidia-open-gpu-kernel-modules-535.161.08/src/common/sdk/nvidia/inc/class/cl0005.h --- nvidia-open-gpu-kernel-modules-525.147.05/src/common/sdk/nvidia/inc/class/cl0005.h 2023-10-25 20:21:40.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/common/sdk/nvidia/inc/class/cl0005.h 2024-03-05 22:14:25.000000000 +0000 @@ -27,7 +27,7 @@ // // This file was generated with FINN, an NVIDIA coding tool. -// Source file: class/cl0005.finn +// Source file: class/cl0005.finn // #include "cl0005_notification.h" diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/common/sdk/nvidia/inc/class/cl000f.h nvidia-open-gpu-kernel-modules-535.161.08/src/common/sdk/nvidia/inc/class/cl000f.h --- nvidia-open-gpu-kernel-modules-525.147.05/src/common/sdk/nvidia/inc/class/cl000f.h 2023-10-25 20:21:40.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/common/sdk/nvidia/inc/class/cl000f.h 2024-03-05 22:14:26.000000000 +0000 @@ -27,7 +27,7 @@ // // This file was generated with FINN, an NVIDIA coding tool. -// Source file: class/cl000f.finn +// Source file: class/cl000f.finn // #define FABRIC_MANAGER_SESSION (0xfU) /* finn: Evaluated from "NV000F_ALLOCATION_PARAMETERS_MESSAGE_ID" */ diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/common/sdk/nvidia/inc/class/cl0042.h nvidia-open-gpu-kernel-modules-535.161.08/src/common/sdk/nvidia/inc/class/cl0042.h --- nvidia-open-gpu-kernel-modules-525.147.05/src/common/sdk/nvidia/inc/class/cl0042.h 1970-01-01 00:00:00.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/common/sdk/nvidia/inc/class/cl0042.h 2024-03-05 22:14:26.000000000 +0000 @@ -0,0 +1,39 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2021-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef _cl0042_h_ +#define _cl0042_h_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include "nvtypes.h" + +#define NV_MEMORY_EXTENDED_USER (0x00000042) + +#ifdef __cplusplus +}; /* extern "C" */ +#endif + +#endif /* _cl0042_h_ */ diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/common/sdk/nvidia/inc/class/cl0050.h nvidia-open-gpu-kernel-modules-535.161.08/src/common/sdk/nvidia/inc/class/cl0050.h --- nvidia-open-gpu-kernel-modules-525.147.05/src/common/sdk/nvidia/inc/class/cl0050.h 1970-01-01 00:00:00.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/common/sdk/nvidia/inc/class/cl0050.h 2024-03-05 22:14:26.000000000 +0000 @@ -0,0 +1,56 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#pragma once + +#include + +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: class/cl0050.finn +// + +#define NV_CE_UTILS (0x50U) /* finn: Evaluated from "NV0050_ALLOCATION_PARAMETERS_MESSAGE_ID" */ + +#define NV0050_ALLOCATION_PARAMETERS_MESSAGE_ID (0x0050U) + +typedef struct NV0050_ALLOCATION_PARAMETERS { + NvHandle hVaspace; + NV_DECLARE_ALIGNED(NvU64 flags, 8); +} NV0050_ALLOCATION_PARAMETERS; + + +// Whether the CeUtils will allocate everything with RM client or external client +#define NV0050_CEUTILS_FLAGS_EXTERNAL 0:0 +#define NV0050_CEUTILS_FLAGS_EXTERNAL_FALSE (0x00000000) +#define NV0050_CEUTILS_FLAGS_EXTERNAL_TRUE (0x00000001) + +// Whether CeUtils will use virtual copy +#define NV0050_CEUTILS_FLAGS_VIRTUAL_MODE 1:1 +#define NV0050_CEUTILS_FLAGS_VIRTUAL_MODE_FALSE (0x00000000) +#define NV0050_CEUTILS_FLAGS_VIRTUAL_MODE_TRUE (0x00000001) + +// Whether the CeUtils is using fifo lite mode. Has to be internal +#define NV0050_CEUTILS_FLAGS_FIFO_LITE 2:2 +#define NV0050_CEUTILS_FLAGS_FIFO_LITE_FALSE (0x00000000) +#define NV0050_CEUTILS_FLAGS_FIFO_LITE_TRUE (0x00000001) diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/common/sdk/nvidia/inc/class/cl0060.h nvidia-open-gpu-kernel-modules-535.161.08/src/common/sdk/nvidia/inc/class/cl0060.h --- nvidia-open-gpu-kernel-modules-525.147.05/src/common/sdk/nvidia/inc/class/cl0060.h 2023-10-25 20:21:41.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/common/sdk/nvidia/inc/class/cl0060.h 2024-03-05 22:14:26.000000000 +0000 @@ -27,7 +27,7 @@ // // This file was generated with FINN, an NVIDIA coding tool. -// Source file: class/cl0060.finn +// Source file: class/cl0060.finn // #define NV0060_SYNC_GPU_BOOST (0x60U) /* finn: Evaluated from "NV0060_ALLOC_PARAMETERS_MESSAGE_ID" */ diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/common/sdk/nvidia/inc/class/cl0070.h nvidia-open-gpu-kernel-modules-535.161.08/src/common/sdk/nvidia/inc/class/cl0070.h --- nvidia-open-gpu-kernel-modules-525.147.05/src/common/sdk/nvidia/inc/class/cl0070.h 2023-10-25 20:21:41.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/common/sdk/nvidia/inc/class/cl0070.h 2024-03-05 22:14:27.000000000 +0000 @@ -26,7 +26,7 @@ // // This file was generated with FINN, an NVIDIA coding tool. -// Source file: class/cl0070.finn +// Source file: class/cl0070.finn // #define NV01_MEMORY_VIRTUAL (0x70U) /* finn: Evaluated from "NV_MEMORY_VIRTUAL_ALLOCATION_PARAMS_MESSAGE_ID" */ diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/common/sdk/nvidia/inc/class/cl0080.h nvidia-open-gpu-kernel-modules-535.161.08/src/common/sdk/nvidia/inc/class/cl0080.h --- nvidia-open-gpu-kernel-modules-525.147.05/src/common/sdk/nvidia/inc/class/cl0080.h 2023-10-25 20:21:42.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/common/sdk/nvidia/inc/class/cl0080.h 2024-03-05 22:14:27.000000000 +0000 @@ -27,7 +27,7 @@ // // This file was generated with FINN, an NVIDIA coding tool. -// Source file: class/cl0080.finn +// Source file: class/cl0080.finn // #include "nvlimits.h" diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/common/sdk/nvidia/inc/class/cl0092.h nvidia-open-gpu-kernel-modules-535.161.08/src/common/sdk/nvidia/inc/class/cl0092.h --- nvidia-open-gpu-kernel-modules-525.147.05/src/common/sdk/nvidia/inc/class/cl0092.h 2023-10-25 20:21:42.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/common/sdk/nvidia/inc/class/cl0092.h 2024-03-05 22:14:27.000000000 +0000 @@ -26,7 +26,7 @@ // // This file was generated with FINN, an NVIDIA coding tool. -// Source file: class/cl0092.finn +// Source file: class/cl0092.finn // #include "class/cl0092_callback.h" diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/common/sdk/nvidia/inc/class/cl00c1.h nvidia-open-gpu-kernel-modules-535.161.08/src/common/sdk/nvidia/inc/class/cl00c1.h --- nvidia-open-gpu-kernel-modules-525.147.05/src/common/sdk/nvidia/inc/class/cl00c1.h 2023-10-25 20:21:42.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/common/sdk/nvidia/inc/class/cl00c1.h 2024-03-05 22:14:28.000000000 +0000 @@ -26,7 +26,7 @@ // // This file was generated with FINN, an NVIDIA coding tool. -// Source file: class/cl00c1.finn +// Source file: class/cl00c1.finn // #include "nvlimits.h" diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/common/sdk/nvidia/inc/class/cl00c2.h nvidia-open-gpu-kernel-modules-535.161.08/src/common/sdk/nvidia/inc/class/cl00c2.h --- nvidia-open-gpu-kernel-modules-525.147.05/src/common/sdk/nvidia/inc/class/cl00c2.h 2023-10-25 20:21:43.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/common/sdk/nvidia/inc/class/cl00c2.h 2024-03-05 22:14:28.000000000 +0000 @@ -26,7 +26,7 @@ // // This file was generated with FINN, an NVIDIA coding tool. -// Source file: class/cl00c2.finn +// Source file: class/cl00c2.finn // #define NV01_MEMORY_LOCAL_PHYSICAL (0xc2U) /* finn: Evaluated from "NV_PHYSICAL_MEMORY_ALLOCATION_PARAMS_MESSAGE_ID" */ @@ -34,8 +34,8 @@ #define NV_PHYSICAL_MEMORY_ALLOCATION_PARAMS_MESSAGE_ID (0x00c2U) typedef struct NV_PHYSICAL_MEMORY_ALLOCATION_PARAMS { - NV_DECLARE_ALIGNED(NvU64 memSize, 8); // [OUT] + NV_DECLARE_ALIGNED(NvU64 memSize, 8); // [OUT] NvU32 format; // [IN] - PTE format to use - NvU32 pageSize; // [IN] - Page size to use + NV_DECLARE_ALIGNED(NvU64 pageSize, 8); // [IN] - Page size to use } NV_PHYSICAL_MEMORY_ALLOCATION_PARAMS; diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/common/sdk/nvidia/inc/class/cl00c3.h nvidia-open-gpu-kernel-modules-535.161.08/src/common/sdk/nvidia/inc/class/cl00c3.h --- nvidia-open-gpu-kernel-modules-525.147.05/src/common/sdk/nvidia/inc/class/cl00c3.h 2023-10-25 20:22:44.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/common/sdk/nvidia/inc/class/cl00c3.h 2024-03-05 22:12:27.000000000 +0000 @@ -26,7 +26,7 @@ // // This file was generated with FINN, an NVIDIA coding tool. -// Source file: class/cl00c3.finn +// Source file: class/cl00c3.finn // #define NV01_MEMORY_SYNCPOINT (0xc3U) /* finn: Evaluated from "NV_MEMORY_SYNCPOINT_ALLOCATION_PARAMS_MESSAGE_ID" */ diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/common/sdk/nvidia/inc/class/cl00da.h nvidia-open-gpu-kernel-modules-535.161.08/src/common/sdk/nvidia/inc/class/cl00da.h --- nvidia-open-gpu-kernel-modules-525.147.05/src/common/sdk/nvidia/inc/class/cl00da.h 1970-01-01 00:00:00.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/common/sdk/nvidia/inc/class/cl00da.h 2024-03-05 22:14:28.000000000 +0000 @@ -0,0 +1,85 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#pragma once + +#include + +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: class/cl00da.finn +// + + + +/* +* NV_SEMAPHORE_SURFACE +* A semaphore surface object contains a GPU-and-CPU-accessible memory region +* containing semaphores, associated monitored fence values, and any other +* related data necessary to implement a circular 32-bit or monotonic 64-bit +* incrementing semaphore primitive and associated event delivery. +*/ +#define NV_SEMAPHORE_SURFACE (0xdaU) /* finn: Evaluated from "NV_SEMAPHORE_SURFACE_ALLOC_PARAMETERS_MESSAGE_ID" */ + + /* + * NV_SEMAPHORE_SURFACE_WAIT_VALUE + * The notification index used when registering events with the RM event + * subsystem. RM clients should not need to use this value, as they don't + * allocate events against this class themselves. Rather, they specify an + * OS event when registering a CPU waiter, and semaphore surface takes care + * of creating event objects internally as necessary, similar to the event + * buffer record notification OS event mechanism. + */ +#define NV_SEMAPHORE_SURFACE_WAIT_VALUE (0x00000000) + +/* +* NV_SEMAPHORE_SURFACE_ALLOC_PARAMETERS +* +* hSemaphoreMem [IN] +* The handle to the memory used for the semaphore value and, when +* supported, the monitored fence/conditional interrupt value. Must be +* accessible by the GPU corresponding to the parent of the semaphore +* surface, as well as the CPU. +* +* hMaxSubmittedMem [IN] +* The handle to the memory used to track the maximum signal value +* submitted to the GPU for processing for a given semaphore slot in +* hSemaphoreMem. This memory is only accessed by the CPU, but must +* support a CPU mapping that allows the use of 64-bit atomic exchange +* operations. This may be the same memory object as hSemaphoreMem if it is +* possible to create one memory object that supports all the requirements +* for a given GPU and CPU. This handle may be omitted/set to zero on GPUs +* that do not require maximum submitted value tracking. +* +* flags [IN] +* Flags affecting the semaphore surface allocation. Currently, there are +* not valid flags, so this value must be set to zero. +*/ +#define NV_SEMAPHORE_SURFACE_ALLOC_PARAMETERS_MESSAGE_ID (0x00DAU) + +typedef struct NV_SEMAPHORE_SURFACE_ALLOC_PARAMETERS { + NvHandle hSemaphoreMem; + NvHandle hMaxSubmittedMem; + NV_DECLARE_ALIGNED(NvU64 flags, 8); +} NV_SEMAPHORE_SURFACE_ALLOC_PARAMETERS; + diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/common/sdk/nvidia/inc/class/cl00db.h nvidia-open-gpu-kernel-modules-535.161.08/src/common/sdk/nvidia/inc/class/cl00db.h --- nvidia-open-gpu-kernel-modules-525.147.05/src/common/sdk/nvidia/inc/class/cl00db.h 2023-10-25 20:21:43.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/common/sdk/nvidia/inc/class/cl00db.h 2024-03-05 22:14:28.000000000 +0000 @@ -28,7 +28,7 @@ // // This file was generated with FINN, an NVIDIA coding tool. -// Source file: class/cl00db.finn +// Source file: class/cl00db.finn // #define NV40_DEBUG_BUFFER (0xdbU) /* finn: Evaluated from "NV00DB_ALLOCATION_PARAMETERS_MESSAGE_ID" */ diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/common/sdk/nvidia/inc/class/cl00de.h nvidia-open-gpu-kernel-modules-535.161.08/src/common/sdk/nvidia/inc/class/cl00de.h --- nvidia-open-gpu-kernel-modules-525.147.05/src/common/sdk/nvidia/inc/class/cl00de.h 2023-10-25 20:21:43.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/common/sdk/nvidia/inc/class/cl00de.h 2024-03-05 22:14:28.000000000 +0000 @@ -35,6 +35,8 @@ NvU32 bar1Size; NvU32 bar1AvailSize; + + NvU32 gspAssertCount; // New data members always add to bottom } NV00DE_SHARED_DATA; diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/common/sdk/nvidia/inc/class/cl00f3.h nvidia-open-gpu-kernel-modules-535.161.08/src/common/sdk/nvidia/inc/class/cl00f3.h --- nvidia-open-gpu-kernel-modules-525.147.05/src/common/sdk/nvidia/inc/class/cl00f3.h 2023-10-25 20:21:43.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/common/sdk/nvidia/inc/class/cl00f3.h 2024-03-05 22:14:29.000000000 +0000 @@ -27,7 +27,7 @@ // // This file was generated with FINN, an NVIDIA coding tool. -// Source file: class/cl00f3.finn +// Source file: class/cl00f3.finn // diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/common/sdk/nvidia/inc/class/cl00f8.h nvidia-open-gpu-kernel-modules-535.161.08/src/common/sdk/nvidia/inc/class/cl00f8.h --- nvidia-open-gpu-kernel-modules-525.147.05/src/common/sdk/nvidia/inc/class/cl00f8.h 2023-10-25 20:21:43.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/common/sdk/nvidia/inc/class/cl00f8.h 2024-03-05 22:14:29.000000000 +0000 @@ -27,11 +27,14 @@ // // This file was generated with FINN, an NVIDIA coding tool. -// Source file: class/cl00f8.finn +// Source file: class/cl00f8.finn // +#include "nvcfg_sdk.h" + + /* * Class definition for allocating a contiguous or discontiguous FLA. */ @@ -93,6 +96,8 @@ #define NV_MEMORY_FABRIC_PAGE_SIZE_2M 0x200000 #define NV_MEMORY_FABRIC_PAGE_SIZE_512M 0x20000000 + + #define NV00F8_ALLOC_FLAGS_DEFAULT 0 #define NV00F8_ALLOC_FLAGS_FLEXIBLE_FLA NVBIT(0) #define NV00F8_ALLOC_FLAGS_FORCE_NONCONTIGUOUS NVBIT(1) @@ -106,7 +111,7 @@ NV_DECLARE_ALIGNED(NvU64 alignment, 8); NV_DECLARE_ALIGNED(NvU64 allocSize, 8); - NvU32 pageSize; + NV_DECLARE_ALIGNED(NvU64 pageSize, 8); NvU32 allocFlags; struct { diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/common/sdk/nvidia/inc/class/cl00fd.h nvidia-open-gpu-kernel-modules-535.161.08/src/common/sdk/nvidia/inc/class/cl00fd.h --- nvidia-open-gpu-kernel-modules-525.147.05/src/common/sdk/nvidia/inc/class/cl00fd.h 2023-10-25 20:21:43.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/common/sdk/nvidia/inc/class/cl00fd.h 2024-03-05 22:14:29.000000000 +0000 @@ -31,7 +31,7 @@ // // This file was generated with FINN, an NVIDIA coding tool. -// Source file: class/cl00fd.finn +// Source file: class/cl00fd.finn // #define NV_MEMORY_MULTICAST_FABRIC (0xfdU) /* finn: Evaluated from "NV00FD_ALLOCATION_PARAMETERS_MESSAGE_ID" */ diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/common/sdk/nvidia/inc/class/cl00fe.h nvidia-open-gpu-kernel-modules-535.161.08/src/common/sdk/nvidia/inc/class/cl00fe.h --- nvidia-open-gpu-kernel-modules-525.147.05/src/common/sdk/nvidia/inc/class/cl00fe.h 2023-10-25 20:21:43.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/common/sdk/nvidia/inc/class/cl00fe.h 2024-03-05 22:14:29.000000000 +0000 @@ -27,7 +27,7 @@ // // This file was generated with FINN, an NVIDIA coding tool. -// Source file: class/cl00fe.finn +// Source file: class/cl00fe.finn // #define NV_MEMORY_MAPPER (0xfeU) /* finn: Evaluated from "NV_MEMORY_MAPPER_ALLOCATION_PARAMS_MESSAGE_ID" */ diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/common/sdk/nvidia/inc/class/cl2080.h nvidia-open-gpu-kernel-modules-535.161.08/src/common/sdk/nvidia/inc/class/cl2080.h --- nvidia-open-gpu-kernel-modules-525.147.05/src/common/sdk/nvidia/inc/class/cl2080.h 2023-10-25 20:21:43.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/common/sdk/nvidia/inc/class/cl2080.h 2024-03-05 22:14:29.000000000 +0000 @@ -27,7 +27,7 @@ // // This file was generated with FINN, an NVIDIA coding tool. -// Source file: class/cl2080.finn +// Source file: class/cl2080.finn // #include "nvlimits.h" diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/common/sdk/nvidia/inc/class/cl2080_notification.h nvidia-open-gpu-kernel-modules-535.161.08/src/common/sdk/nvidia/inc/class/cl2080_notification.h --- nvidia-open-gpu-kernel-modules-525.147.05/src/common/sdk/nvidia/inc/class/cl2080_notification.h 2023-10-25 20:21:44.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/common/sdk/nvidia/inc/class/cl2080_notification.h 2024-03-05 22:14:29.000000000 +0000 @@ -200,9 +200,11 @@ #define NV2080_NOTIFIERS_POSSIBLE_ERROR (164) #define NV2080_NOTIFIERS_NVLINK_INFO_LINK_UP (165) #define NV2080_NOTIFIERS_NVLINK_INFO_LINK_DOWN (176) -#define NV2080_NOTIFIERS_HDMI_FRL_RETRAINING_REQUEST (177) -#define NV2080_NOTIFIERS_AUX_POWER_STATE_CHANGE (178) -#define NV2080_NOTIFIERS_MAXCOUNT (179) +#define NV2080_NOTIFIERS_NVPCF_EVENTS (177) +#define NV2080_NOTIFIERS_HDMI_FRL_RETRAINING_REQUEST (178) +#define NV2080_NOTIFIERS_VRR_SET_TIMEOUT (179) +#define NV2080_NOTIFIERS_AUX_POWER_STATE_CHANGE (180) +#define NV2080_NOTIFIERS_MAXCOUNT (181) // Indexed GR notifier reference #define NV2080_NOTIFIERS_GR(x) ((x == 0) ? (NV2080_NOTIFIERS_GR0) : (NV2080_NOTIFIERS_GR1 + (x - 1))) @@ -497,6 +499,10 @@ NvU32 linkId; } Nv2080NvlinkLnkChangeNotification; +typedef struct { + NvU32 head; +} Nv2080VrrSetTimeoutNotification; + #ifdef __cplusplus }; /* extern "C" */ #endif diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/common/sdk/nvidia/inc/class/cl2081.h nvidia-open-gpu-kernel-modules-535.161.08/src/common/sdk/nvidia/inc/class/cl2081.h --- nvidia-open-gpu-kernel-modules-525.147.05/src/common/sdk/nvidia/inc/class/cl2081.h 2023-10-25 20:21:44.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/common/sdk/nvidia/inc/class/cl2081.h 2024-03-05 22:14:29.000000000 +0000 @@ -27,7 +27,7 @@ // // This file was generated with FINN, an NVIDIA coding tool. -// Source file: class/cl2081.finn +// Source file: class/cl2081.finn // #define NV2081_BINAPI (0x2081U) /* finn: Evaluated from "NV2081_ALLOC_PARAMETERS_MESSAGE_ID" */ diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/common/sdk/nvidia/inc/class/cl2082.h nvidia-open-gpu-kernel-modules-535.161.08/src/common/sdk/nvidia/inc/class/cl2082.h --- nvidia-open-gpu-kernel-modules-525.147.05/src/common/sdk/nvidia/inc/class/cl2082.h 2023-10-25 20:21:44.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/common/sdk/nvidia/inc/class/cl2082.h 2024-03-05 22:14:30.000000000 +0000 @@ -27,7 +27,7 @@ // // This file was generated with FINN, an NVIDIA coding tool. -// Source file: class/cl2082.finn +// Source file: class/cl2082.finn // #define NV2082_BINAPI_PRIVILEGED (0x2082U) /* finn: Evaluated from "NV2082_ALLOC_PARAMETERS_MESSAGE_ID" */ diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/common/sdk/nvidia/inc/class/cl30f1.h nvidia-open-gpu-kernel-modules-535.161.08/src/common/sdk/nvidia/inc/class/cl30f1.h --- nvidia-open-gpu-kernel-modules-525.147.05/src/common/sdk/nvidia/inc/class/cl30f1.h 2023-10-25 20:21:44.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/common/sdk/nvidia/inc/class/cl30f1.h 2024-03-05 22:14:30.000000000 +0000 @@ -27,7 +27,7 @@ // // This file was generated with FINN, an NVIDIA coding tool. -// Source file: class/cl30f1.finn +// Source file: class/cl30f1.finn // #include "cl30f1_notification.h" diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/common/sdk/nvidia/inc/class/cl503b.h nvidia-open-gpu-kernel-modules-535.161.08/src/common/sdk/nvidia/inc/class/cl503b.h --- nvidia-open-gpu-kernel-modules-525.147.05/src/common/sdk/nvidia/inc/class/cl503b.h 2023-10-25 20:21:44.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/common/sdk/nvidia/inc/class/cl503b.h 2024-03-05 22:14:30.000000000 +0000 @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 2009-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2009-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -28,7 +28,7 @@ // // This file was generated with FINN, an NVIDIA coding tool. -// Source file: class/cl503b.finn +// Source file: class/cl503b.finn // #define NV50_P2P (0x503bU) /* finn: Evaluated from "NV503B_ALLOC_PARAMETERS_MESSAGE_ID" */ @@ -37,6 +37,19 @@ #define NV503B_FLAGS_P2P_TYPE_GPA 0 #define NV503B_FLAGS_P2P_TYPE_SPA 1 +/* + * NV503B_BAR1_P2P_DMA_INFO + * + * The DMA information for BAR1 P2P, it is only valid for BAR1 P2P. + * dma_address will be set to NV_U64_MAX and dma_size will be set to 0 + * when the DMA info is not available. + * + */ +typedef struct NV503B_BAR1_P2P_DMA_INFO { + NV_DECLARE_ALIGNED(NvU64 dma_address, 8); + NV_DECLARE_ALIGNED(NvU64 dma_size, 8); +} NV503B_BAR1_P2P_DMA_INFO; + /* NvRmAlloc parameters */ #define NV503B_ALLOC_PARAMETERS_MESSAGE_ID (0x503bU) @@ -54,4 +67,8 @@ NvU32 mailboxTotalSize; /* Size of the P2P Mailbox area * Must have the same value across the GPUs */ NvU32 flags; /* Flag to indicate types/attib of p2p */ + NvU32 subDeviceEgmPeerIdMask; /* Bit mask of EGM peer ID of SubDevice */ + NvU32 peerSubDeviceEgmPeerIdMask; /* Bit mask of EGM peer ID for PeerSubDevice */ + NV_DECLARE_ALIGNED(NV503B_BAR1_P2P_DMA_INFO l2pBar1P2PDmaInfo, 8); /* Bar1 DMA info from local GPU to peer GPU */ + NV_DECLARE_ALIGNED(NV503B_BAR1_P2P_DMA_INFO p2lBar1P2PDmaInfo, 8); /* Bar1 DMA info from peer GPU to local GPU */ } NV503B_ALLOC_PARAMETERS; diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/common/sdk/nvidia/inc/class/cl503c.h nvidia-open-gpu-kernel-modules-535.161.08/src/common/sdk/nvidia/inc/class/cl503c.h --- nvidia-open-gpu-kernel-modules-525.147.05/src/common/sdk/nvidia/inc/class/cl503c.h 2023-10-25 20:21:44.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/common/sdk/nvidia/inc/class/cl503c.h 2024-03-05 22:14:30.000000000 +0000 @@ -28,7 +28,7 @@ // // This file was generated with FINN, an NVIDIA coding tool. -// Source file: class/cl503c.finn +// Source file: class/cl503c.finn // #define NV50_THIRD_PARTY_P2P (0x503cU) /* finn: Evaluated from "NV503C_ALLOC_PARAMETERS_MESSAGE_ID" */ diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/common/sdk/nvidia/inc/class/cl5070.h nvidia-open-gpu-kernel-modules-535.161.08/src/common/sdk/nvidia/inc/class/cl5070.h --- nvidia-open-gpu-kernel-modules-525.147.05/src/common/sdk/nvidia/inc/class/cl5070.h 2023-10-25 20:21:45.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/common/sdk/nvidia/inc/class/cl5070.h 2024-03-05 22:14:31.000000000 +0000 @@ -27,7 +27,7 @@ // // This file was generated with FINN, an NVIDIA coding tool. -// Source file: class/cl5070.finn +// Source file: class/cl5070.finn // #include "cl5070_notification.h" diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/common/sdk/nvidia/inc/class/cl5080.h nvidia-open-gpu-kernel-modules-535.161.08/src/common/sdk/nvidia/inc/class/cl5080.h --- nvidia-open-gpu-kernel-modules-525.147.05/src/common/sdk/nvidia/inc/class/cl5080.h 2023-10-25 20:21:45.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/common/sdk/nvidia/inc/class/cl5080.h 2024-03-05 22:14:31.000000000 +0000 @@ -27,7 +27,7 @@ // // This file was generated with FINN, an NVIDIA coding tool. -// Source file: class/cl5080.finn +// Source file: class/cl5080.finn // #include "cl5080_notification.h" diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/common/sdk/nvidia/inc/class/cl83de.h nvidia-open-gpu-kernel-modules-535.161.08/src/common/sdk/nvidia/inc/class/cl83de.h --- nvidia-open-gpu-kernel-modules-525.147.05/src/common/sdk/nvidia/inc/class/cl83de.h 2023-10-25 20:21:45.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/common/sdk/nvidia/inc/class/cl83de.h 2024-03-05 22:14:31.000000000 +0000 @@ -27,7 +27,7 @@ // // This file was generated with FINN, an NVIDIA coding tool. -// Source file: class/cl83de.finn +// Source file: class/cl83de.finn // #define GT200_DEBUGGER (0x83deU) /* finn: Evaluated from "NV83DE_ALLOC_PARAMETERS_MESSAGE_ID" */ diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/common/sdk/nvidia/inc/class/cl84a0.h nvidia-open-gpu-kernel-modules-535.161.08/src/common/sdk/nvidia/inc/class/cl84a0.h --- nvidia-open-gpu-kernel-modules-525.147.05/src/common/sdk/nvidia/inc/class/cl84a0.h 2023-10-25 20:21:45.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/common/sdk/nvidia/inc/class/cl84a0.h 2024-03-05 22:14:31.000000000 +0000 @@ -27,7 +27,7 @@ // // This file was generated with FINN, an NVIDIA coding tool. -// Source file: class/cl84a0.finn +// Source file: class/cl84a0.finn // #include "cl84a0_deprecated.h" diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/common/sdk/nvidia/inc/class/cl85b5sw.h nvidia-open-gpu-kernel-modules-535.161.08/src/common/sdk/nvidia/inc/class/cl85b5sw.h --- nvidia-open-gpu-kernel-modules-525.147.05/src/common/sdk/nvidia/inc/class/cl85b5sw.h 2023-10-25 20:21:45.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/common/sdk/nvidia/inc/class/cl85b5sw.h 2024-03-05 22:14:32.000000000 +0000 @@ -27,7 +27,7 @@ // // This file was generated with FINN, an NVIDIA coding tool. -// Source file: class/cl85b5sw.finn +// Source file: class/cl85b5sw.finn // #define NV85B5_ALLOCATION_PARAMETERS_MESSAGE_ID (0x85b5U) diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/common/sdk/nvidia/inc/class/cl9010.h nvidia-open-gpu-kernel-modules-535.161.08/src/common/sdk/nvidia/inc/class/cl9010.h --- nvidia-open-gpu-kernel-modules-525.147.05/src/common/sdk/nvidia/inc/class/cl9010.h 2023-10-25 20:21:46.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/common/sdk/nvidia/inc/class/cl9010.h 2024-03-05 22:14:32.000000000 +0000 @@ -26,7 +26,7 @@ // // This file was generated with FINN, an NVIDIA coding tool. -// Source file: class/cl9010.finn +// Source file: class/cl9010.finn // #include "class/cl9010_callback.h" diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/common/sdk/nvidia/inc/class/cl9072.h nvidia-open-gpu-kernel-modules-535.161.08/src/common/sdk/nvidia/inc/class/cl9072.h --- nvidia-open-gpu-kernel-modules-525.147.05/src/common/sdk/nvidia/inc/class/cl9072.h 2023-10-25 20:21:46.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/common/sdk/nvidia/inc/class/cl9072.h 2024-03-05 22:14:32.000000000 +0000 @@ -27,7 +27,7 @@ // // This file was generated with FINN, an NVIDIA coding tool. -// Source file: class/cl9072.finn +// Source file: class/cl9072.finn // #include "cl9072_notification.h" diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/common/sdk/nvidia/inc/class/cl90cd.h nvidia-open-gpu-kernel-modules-535.161.08/src/common/sdk/nvidia/inc/class/cl90cd.h --- nvidia-open-gpu-kernel-modules-525.147.05/src/common/sdk/nvidia/inc/class/cl90cd.h 2023-10-25 20:21:47.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/common/sdk/nvidia/inc/class/cl90cd.h 2024-03-05 22:14:33.000000000 +0000 @@ -33,7 +33,7 @@ // // This file was generated with FINN, an NVIDIA coding tool. -// Source file: class/cl90cd.finn +// Source file: class/cl90cd.finn // #define NV_EVENT_BUFFER (0x90cdU) /* finn: Evaluated from "NV_EVENT_BUFFER_ALLOC_PARAMETERS_MESSAGE_ID" */ diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/common/sdk/nvidia/inc/class/cl90e7.h nvidia-open-gpu-kernel-modules-535.161.08/src/common/sdk/nvidia/inc/class/cl90e7.h --- nvidia-open-gpu-kernel-modules-525.147.05/src/common/sdk/nvidia/inc/class/cl90e7.h 1970-01-01 00:00:00.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/common/sdk/nvidia/inc/class/cl90e7.h 2024-03-05 22:14:33.000000000 +0000 @@ -0,0 +1,38 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2013-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef _cl90e7_h_ +#define _cl90e7_h_ + +#ifdef __cplusplus +extern "C" { +#endif + +#define GF100_SUBDEVICE_INFOROM (0x000090e7) + +#ifdef __cplusplus +}; /* extern "C" */ +#endif + +#endif // _cl90e7_h + diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/common/sdk/nvidia/inc/class/cl9170.h nvidia-open-gpu-kernel-modules-535.161.08/src/common/sdk/nvidia/inc/class/cl9170.h --- nvidia-open-gpu-kernel-modules-525.147.05/src/common/sdk/nvidia/inc/class/cl9170.h 2023-10-25 20:22:45.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/common/sdk/nvidia/inc/class/cl9170.h 2024-03-05 22:12:27.000000000 +0000 @@ -26,7 +26,7 @@ // // This file was generated with FINN, an NVIDIA coding tool. -// Source file: class/cl9170.finn +// Source file: class/cl9170.finn // #define NV9170_DISPLAY (0x9170U) /* finn: Evaluated from "NV9170_ALLOCATION_PARAMETERS_MESSAGE_ID" */ diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/common/sdk/nvidia/inc/class/cl9270.h nvidia-open-gpu-kernel-modules-535.161.08/src/common/sdk/nvidia/inc/class/cl9270.h --- nvidia-open-gpu-kernel-modules-525.147.05/src/common/sdk/nvidia/inc/class/cl9270.h 2023-10-25 20:22:45.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/common/sdk/nvidia/inc/class/cl9270.h 2024-03-05 22:12:28.000000000 +0000 @@ -26,7 +26,7 @@ // // This file was generated with FINN, an NVIDIA coding tool. -// Source file: class/cl9270.finn +// Source file: class/cl9270.finn // #define NV9270_DISPLAY (0x9270U) /* finn: Evaluated from "NV9270_ALLOCATION_PARAMETERS_MESSAGE_ID" */ diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/common/sdk/nvidia/inc/class/cl9470.h nvidia-open-gpu-kernel-modules-535.161.08/src/common/sdk/nvidia/inc/class/cl9470.h --- nvidia-open-gpu-kernel-modules-525.147.05/src/common/sdk/nvidia/inc/class/cl9470.h 2023-10-25 20:22:45.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/common/sdk/nvidia/inc/class/cl9470.h 2024-03-05 22:12:28.000000000 +0000 @@ -26,7 +26,7 @@ // // This file was generated with FINN, an NVIDIA coding tool. -// Source file: class/cl9470.finn +// Source file: class/cl9470.finn // #define NV9470_DISPLAY (0x9470U) /* finn: Evaluated from "NV9470_ALLOCATION_PARAMETERS_MESSAGE_ID" */ diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/common/sdk/nvidia/inc/class/cl9570.h nvidia-open-gpu-kernel-modules-535.161.08/src/common/sdk/nvidia/inc/class/cl9570.h --- nvidia-open-gpu-kernel-modules-525.147.05/src/common/sdk/nvidia/inc/class/cl9570.h 2023-10-25 20:22:45.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/common/sdk/nvidia/inc/class/cl9570.h 2024-03-05 22:12:28.000000000 +0000 @@ -26,7 +26,7 @@ // // This file was generated with FINN, an NVIDIA coding tool. -// Source file: class/cl9570.finn +// Source file: class/cl9570.finn // #define NV9570_DISPLAY (0x9570U) /* finn: Evaluated from "NV9570_ALLOCATION_PARAMETERS_MESSAGE_ID" */ diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/common/sdk/nvidia/inc/class/cl9770.h nvidia-open-gpu-kernel-modules-535.161.08/src/common/sdk/nvidia/inc/class/cl9770.h --- nvidia-open-gpu-kernel-modules-525.147.05/src/common/sdk/nvidia/inc/class/cl9770.h 2023-10-25 20:22:45.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/common/sdk/nvidia/inc/class/cl9770.h 2024-03-05 22:12:28.000000000 +0000 @@ -26,7 +26,7 @@ // // This file was generated with FINN, an NVIDIA coding tool. -// Source file: class/cl9770.finn +// Source file: class/cl9770.finn // #define NV9770_DISPLAY (0x9770U) /* finn: Evaluated from "NV9770_ALLOCATION_PARAMETERS_MESSAGE_ID" */ diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/common/sdk/nvidia/inc/class/cl9870.h nvidia-open-gpu-kernel-modules-535.161.08/src/common/sdk/nvidia/inc/class/cl9870.h --- nvidia-open-gpu-kernel-modules-525.147.05/src/common/sdk/nvidia/inc/class/cl9870.h 2023-10-25 20:22:45.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/common/sdk/nvidia/inc/class/cl9870.h 2024-03-05 22:12:28.000000000 +0000 @@ -26,7 +26,7 @@ // // This file was generated with FINN, an NVIDIA coding tool. -// Source file: class/cl9870.finn +// Source file: class/cl9870.finn // #define NV9870_DISPLAY (0x9870U) /* finn: Evaluated from "NV9870_ALLOCATION_PARAMETERS_MESSAGE_ID" */ diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/common/sdk/nvidia/inc/class/cla084.h nvidia-open-gpu-kernel-modules-535.161.08/src/common/sdk/nvidia/inc/class/cla084.h --- nvidia-open-gpu-kernel-modules-525.147.05/src/common/sdk/nvidia/inc/class/cla084.h 2023-10-25 20:21:48.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/common/sdk/nvidia/inc/class/cla084.h 2024-03-05 22:14:34.000000000 +0000 @@ -27,7 +27,7 @@ // // This file was generated with FINN, an NVIDIA coding tool. -// Source file: class/cla084.finn +// Source file: class/cla084.finn // #include "nv_vgpu_types.h" @@ -43,16 +43,17 @@ * This structure represents vGPU host device KERNEL object allocation parameters. * dbdf -> domain (31:16), bus (15:8), device (7:3), function (2:0) * gfid -> Used only when SRIOV is enabled otherwise set to 0. - * swizzId [IN/OUT] -> Used only when MIG mode is enabled otherwise set + * swizzId [IN] -> Used only when MIG mode is enabled otherwise set * to NV2080_CTRL_GPU_PARTITION_ID_INVALID. * numChannels -> Used only when SRIOV is enabled. Must be a power of 2. * bDisableDefaultSmcExecPartRestore - If set to true, SMC default execution partition * save/restore will not be done in host-RM * vgpuDeviceInstanceId -> Specifies the vGPU device instance per VM to be used * for supporting multiple vGPUs per VM. - * numGuestFbHandles -> number of guest memory handles + * hPluginClient -> handle to the plugin client + * numGuestFbHandles -> number of guest memory handles, the client handle is hPluginClient * guestFbHandleList -> handle list to guest memory - * hPluginHeapMemory -> plugin heap memory handle + * hPluginHeapMemory -> plugin heap memory handle, the client handle is hPluginClient * bDeviceProfilingEnabled -> If set to true, profiling is allowed */ #define NVA084_ALLOC_PARAMETERS_MESSAGE_ID (0xa084U) @@ -69,6 +70,7 @@ NV_DECLARE_ALIGNED(VM_ID guestVmId, 8); NvBool bDisableDefaultSmcExecPartRestore; NvU32 vgpuDeviceInstanceId; + NvHandle hPluginClient; NvU32 numGuestFbHandles; NvHandle guestFbHandleList[NVA084_MAX_VMMU_SEGMENTS]; NvHandle hPluginHeapMemory; diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/common/sdk/nvidia/inc/class/clb069sw.h nvidia-open-gpu-kernel-modules-535.161.08/src/common/sdk/nvidia/inc/class/clb069sw.h --- nvidia-open-gpu-kernel-modules-525.147.05/src/common/sdk/nvidia/inc/class/clb069sw.h 2023-10-25 20:21:48.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/common/sdk/nvidia/inc/class/clb069sw.h 2024-03-05 22:14:35.000000000 +0000 @@ -27,7 +27,7 @@ // // This file was generated with FINN, an NVIDIA coding tool. -// Source file: class/clb069sw.finn +// Source file: class/clb069sw.finn // #define NVB069_ALLOCATION_PARAMETERS_MESSAGE_ID (0xb069U) diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/common/sdk/nvidia/inc/class/clb0b5sw.h nvidia-open-gpu-kernel-modules-535.161.08/src/common/sdk/nvidia/inc/class/clb0b5sw.h --- nvidia-open-gpu-kernel-modules-525.147.05/src/common/sdk/nvidia/inc/class/clb0b5sw.h 2023-10-25 20:21:49.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/common/sdk/nvidia/inc/class/clb0b5sw.h 2024-03-05 22:14:35.000000000 +0000 @@ -27,7 +27,7 @@ // // This file was generated with FINN, an NVIDIA coding tool. -// Source file: class/clb0b5sw.finn +// Source file: class/clb0b5sw.finn // diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/common/sdk/nvidia/inc/class/clb2cc.h nvidia-open-gpu-kernel-modules-535.161.08/src/common/sdk/nvidia/inc/class/clb2cc.h --- nvidia-open-gpu-kernel-modules-525.147.05/src/common/sdk/nvidia/inc/class/clb2cc.h 2023-10-25 20:21:49.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/common/sdk/nvidia/inc/class/clb2cc.h 2024-03-05 22:14:35.000000000 +0000 @@ -27,7 +27,7 @@ // // This file was generated with FINN, an NVIDIA coding tool. -// Source file: class/clb2cc.finn +// Source file: class/clb2cc.finn // #include "clb0cc.h" diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/common/sdk/nvidia/inc/class/clc0b5sw.h nvidia-open-gpu-kernel-modules-535.161.08/src/common/sdk/nvidia/inc/class/clc0b5sw.h --- nvidia-open-gpu-kernel-modules-525.147.05/src/common/sdk/nvidia/inc/class/clc0b5sw.h 2023-10-25 20:21:49.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/common/sdk/nvidia/inc/class/clc0b5sw.h 2024-03-05 22:14:36.000000000 +0000 @@ -27,7 +27,7 @@ // // This file was generated with FINN, an NVIDIA coding tool. -// Source file: class/clc0b5sw.finn +// Source file: class/clc0b5sw.finn // diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/common/sdk/nvidia/inc/class/clc1b5sw.h nvidia-open-gpu-kernel-modules-535.161.08/src/common/sdk/nvidia/inc/class/clc1b5sw.h --- nvidia-open-gpu-kernel-modules-525.147.05/src/common/sdk/nvidia/inc/class/clc1b5sw.h 2023-10-25 20:21:50.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/common/sdk/nvidia/inc/class/clc1b5sw.h 2024-03-05 22:14:36.000000000 +0000 @@ -27,7 +27,7 @@ // // This file was generated with FINN, an NVIDIA coding tool. -// Source file: class/clc1b5sw.finn +// Source file: class/clc1b5sw.finn // diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/common/sdk/nvidia/inc/class/clc370.h nvidia-open-gpu-kernel-modules-535.161.08/src/common/sdk/nvidia/inc/class/clc370.h --- nvidia-open-gpu-kernel-modules-525.147.05/src/common/sdk/nvidia/inc/class/clc370.h 2023-10-25 20:21:50.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/common/sdk/nvidia/inc/class/clc370.h 2024-03-05 22:14:37.000000000 +0000 @@ -26,7 +26,7 @@ // // This file was generated with FINN, an NVIDIA coding tool. -// Source file: class/clc370.finn +// Source file: class/clc370.finn // #include "clc370_notification.h" diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/common/sdk/nvidia/inc/class/clc370_notification.h nvidia-open-gpu-kernel-modules-535.161.08/src/common/sdk/nvidia/inc/class/clc370_notification.h --- nvidia-open-gpu-kernel-modules-525.147.05/src/common/sdk/nvidia/inc/class/clc370_notification.h 2023-10-25 20:21:50.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/common/sdk/nvidia/inc/class/clc370_notification.h 2024-03-05 22:14:37.000000000 +0000 @@ -32,8 +32,7 @@ /* event values */ #define NVC370_NOTIFIERS_SW NV5070_NOTIFIERS_SW #define NVC370_NOTIFIERS_BEGIN NV5070_NOTIFIERS_MAXCOUNT -#define NVC370_NOTIFIERS_VPR NVC370_NOTIFIERS_BEGIN + (0) -#define NVC370_NOTIFIERS_RG_SEM_NOTIFICATION NVC370_NOTIFIERS_VPR + (1) +#define NVC370_NOTIFIERS_RG_SEM_NOTIFICATION NVC370_NOTIFIERS_BEGIN + (0) #define NVC370_NOTIFIERS_WIN_SEM_NOTIFICATION NVC370_NOTIFIERS_RG_SEM_NOTIFICATION + (1) #define NVC370_NOTIFIERS_MAXCOUNT NVC370_NOTIFIERS_WIN_SEM_NOTIFICATION + (1) diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/common/sdk/nvidia/inc/class/clc3b5sw.h nvidia-open-gpu-kernel-modules-535.161.08/src/common/sdk/nvidia/inc/class/clc3b5sw.h --- nvidia-open-gpu-kernel-modules-525.147.05/src/common/sdk/nvidia/inc/class/clc3b5sw.h 2023-10-25 20:21:51.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/common/sdk/nvidia/inc/class/clc3b5sw.h 2024-03-05 22:14:37.000000000 +0000 @@ -27,7 +27,7 @@ // // This file was generated with FINN, an NVIDIA coding tool. -// Source file: class/clc3b5sw.finn +// Source file: class/clc3b5sw.finn // diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/common/sdk/nvidia/inc/class/clc570.h nvidia-open-gpu-kernel-modules-535.161.08/src/common/sdk/nvidia/inc/class/clc570.h --- nvidia-open-gpu-kernel-modules-525.147.05/src/common/sdk/nvidia/inc/class/clc570.h 2023-10-25 20:21:51.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/common/sdk/nvidia/inc/class/clc570.h 2024-03-05 22:14:38.000000000 +0000 @@ -26,7 +26,7 @@ // // This file was generated with FINN, an NVIDIA coding tool. -// Source file: class/clc570.finn +// Source file: class/clc570.finn // #define NVC570_DISPLAY (0xc570U) /* finn: Evaluated from "NVC570_ALLOCATION_PARAMETERS_MESSAGE_ID" */ diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/common/sdk/nvidia/inc/class/clc574.h nvidia-open-gpu-kernel-modules-535.161.08/src/common/sdk/nvidia/inc/class/clc574.h --- nvidia-open-gpu-kernel-modules-525.147.05/src/common/sdk/nvidia/inc/class/clc574.h 2023-10-25 20:21:52.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/common/sdk/nvidia/inc/class/clc574.h 2024-03-05 22:14:38.000000000 +0000 @@ -27,7 +27,7 @@ // // This file was generated with FINN, an NVIDIA coding tool. -// Source file: class/clc574.finn +// Source file: class/clc574.finn // #define UVM_CHANNEL_RETAINER (0xc574U) /* finn: Evaluated from "NV_UVM_CHANNEL_RETAINER_ALLOC_PARAMS_MESSAGE_ID" */ diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/common/sdk/nvidia/inc/class/clc58b.h nvidia-open-gpu-kernel-modules-535.161.08/src/common/sdk/nvidia/inc/class/clc58b.h --- nvidia-open-gpu-kernel-modules-525.147.05/src/common/sdk/nvidia/inc/class/clc58b.h 2023-10-25 20:21:52.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/common/sdk/nvidia/inc/class/clc58b.h 2024-03-05 22:14:39.000000000 +0000 @@ -27,7 +27,7 @@ // // This file was generated with FINN, an NVIDIA coding tool. -// Source file: class/clc58b.finn +// Source file: class/clc58b.finn // #define TURING_VMMU_A (0xc58bU) /* finn: Evaluated from "TURING_VMMU_A_ALLOCATION_PARAMETERS_MESSAGE_ID" */ diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/common/sdk/nvidia/inc/class/clc5b5sw.h nvidia-open-gpu-kernel-modules-535.161.08/src/common/sdk/nvidia/inc/class/clc5b5sw.h --- nvidia-open-gpu-kernel-modules-525.147.05/src/common/sdk/nvidia/inc/class/clc5b5sw.h 2023-10-25 20:21:52.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/common/sdk/nvidia/inc/class/clc5b5sw.h 2024-03-05 22:14:39.000000000 +0000 @@ -27,7 +27,7 @@ // // This file was generated with FINN, an NVIDIA coding tool. -// Source file: class/clc5b5sw.finn +// Source file: class/clc5b5sw.finn // diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/common/sdk/nvidia/inc/class/clc637.h nvidia-open-gpu-kernel-modules-535.161.08/src/common/sdk/nvidia/inc/class/clc637.h --- nvidia-open-gpu-kernel-modules-525.147.05/src/common/sdk/nvidia/inc/class/clc637.h 2023-10-25 20:21:52.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/common/sdk/nvidia/inc/class/clc637.h 2024-03-05 22:14:39.000000000 +0000 @@ -27,7 +27,7 @@ // // This file was generated with FINN, an NVIDIA coding tool. -// Source file: class/clc637.finn +// Source file: class/clc637.finn // #define AMPERE_SMC_PARTITION_REF (0xc637U) /* finn: Evaluated from "NVC637_ALLOCATION_PARAMETERS_MESSAGE_ID" */ diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/common/sdk/nvidia/inc/class/clc638.h nvidia-open-gpu-kernel-modules-535.161.08/src/common/sdk/nvidia/inc/class/clc638.h --- nvidia-open-gpu-kernel-modules-525.147.05/src/common/sdk/nvidia/inc/class/clc638.h 2023-10-25 20:21:52.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/common/sdk/nvidia/inc/class/clc638.h 2024-03-05 22:14:39.000000000 +0000 @@ -27,7 +27,7 @@ // // This file was generated with FINN, an NVIDIA coding tool. -// Source file: class/clc638.finn +// Source file: class/clc638.finn // #define AMPERE_SMC_EXEC_PARTITION_REF (0xc638U) /* finn: Evaluated from "NVC638_ALLOCATION_PARAMETERS_MESSAGE_ID" */ diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/common/sdk/nvidia/inc/class/clc639.h nvidia-open-gpu-kernel-modules-535.161.08/src/common/sdk/nvidia/inc/class/clc639.h --- nvidia-open-gpu-kernel-modules-525.147.05/src/common/sdk/nvidia/inc/class/clc639.h 2023-10-25 20:21:52.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/common/sdk/nvidia/inc/class/clc639.h 2024-03-05 22:14:39.000000000 +0000 @@ -27,7 +27,7 @@ // // This file was generated with FINN, an NVIDIA coding tool. -// Source file: class/clc639.finn +// Source file: class/clc639.finn // #define AMPERE_SMC_CONFIG_SESSION (0xc639U) /* finn: Evaluated from "NVC639_ALLOCATION_PARAMETERS_MESSAGE_ID" */ diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/common/sdk/nvidia/inc/class/clc640.h nvidia-open-gpu-kernel-modules-535.161.08/src/common/sdk/nvidia/inc/class/clc640.h --- nvidia-open-gpu-kernel-modules-525.147.05/src/common/sdk/nvidia/inc/class/clc640.h 2023-10-25 20:21:52.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/common/sdk/nvidia/inc/class/clc640.h 2024-03-05 22:14:39.000000000 +0000 @@ -27,7 +27,7 @@ // // This file was generated with FINN, an NVIDIA coding tool. -// Source file: class/clc640.finn +// Source file: class/clc640.finn // #define AMPERE_SMC_MONITOR_SESSION (0xc640U) /* finn: Evaluated from "NVC640_ALLOCATION_PARAMETERS_MESSAGE_ID" */ diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/common/sdk/nvidia/inc/class/clc670.h nvidia-open-gpu-kernel-modules-535.161.08/src/common/sdk/nvidia/inc/class/clc670.h --- nvidia-open-gpu-kernel-modules-525.147.05/src/common/sdk/nvidia/inc/class/clc670.h 2023-10-25 20:21:53.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/common/sdk/nvidia/inc/class/clc670.h 2024-03-05 22:14:39.000000000 +0000 @@ -26,7 +26,7 @@ // // This file was generated with FINN, an NVIDIA coding tool. -// Source file: class/clc670.finn +// Source file: class/clc670.finn // #define NVC670_DISPLAY (0xc670U) /* finn: Evaluated from "NVC670_ALLOCATION_PARAMETERS_MESSAGE_ID" */ diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/common/sdk/nvidia/inc/class/clc6b5sw.h nvidia-open-gpu-kernel-modules-535.161.08/src/common/sdk/nvidia/inc/class/clc6b5sw.h --- nvidia-open-gpu-kernel-modules-525.147.05/src/common/sdk/nvidia/inc/class/clc6b5sw.h 2023-10-25 20:21:53.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/common/sdk/nvidia/inc/class/clc6b5sw.h 2024-03-05 22:14:39.000000000 +0000 @@ -27,7 +27,7 @@ // // This file was generated with FINN, an NVIDIA coding tool. -// Source file: class/clc6b5sw.finn +// Source file: class/clc6b5sw.finn // diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/common/sdk/nvidia/inc/class/clc763.h nvidia-open-gpu-kernel-modules-535.161.08/src/common/sdk/nvidia/inc/class/clc763.h --- nvidia-open-gpu-kernel-modules-525.147.05/src/common/sdk/nvidia/inc/class/clc763.h 1970-01-01 00:00:00.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/common/sdk/nvidia/inc/class/clc763.h 2024-03-05 22:14:52.000000000 +0000 @@ -0,0 +1,29 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef _clc763_h_ +#define _clc763_h_ + +#define MMU_VIDMEM_ACCESS_BIT_BUFFER (0xc763) + +#endif /* _clc763_h_ */ diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/common/sdk/nvidia/inc/class/clc770.h nvidia-open-gpu-kernel-modules-535.161.08/src/common/sdk/nvidia/inc/class/clc770.h --- nvidia-open-gpu-kernel-modules-525.147.05/src/common/sdk/nvidia/inc/class/clc770.h 2023-10-25 20:21:53.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/common/sdk/nvidia/inc/class/clc770.h 2024-03-05 22:14:40.000000000 +0000 @@ -26,7 +26,7 @@ // // This file was generated with FINN, an NVIDIA coding tool. -// Source file: class/clc770.finn +// Source file: class/clc770.finn // #define NVC770_DISPLAY (0xc770U) /* finn: Evaluated from "NVC770_ALLOCATION_PARAMETERS_MESSAGE_ID" */ diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/common/sdk/nvidia/inc/class/clcb33.h nvidia-open-gpu-kernel-modules-535.161.08/src/common/sdk/nvidia/inc/class/clcb33.h --- nvidia-open-gpu-kernel-modules-525.147.05/src/common/sdk/nvidia/inc/class/clcb33.h 1970-01-01 00:00:00.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/common/sdk/nvidia/inc/class/clcb33.h 2024-03-05 22:14:40.000000000 +0000 @@ -0,0 +1,40 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2022-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#pragma once + +#include + +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: class/clcb33.finn +// + +#define NV_CONFIDENTIAL_COMPUTE (0xcb33U) /* finn: Evaluated from "NV_CONFIDENTIAL_COMPUTE_ALLOC_PARAMS_MESSAGE_ID" */ + +#define NV_CONFIDENTIAL_COMPUTE_ALLOC_PARAMS_MESSAGE_ID (0xcb33U) + +typedef struct NV_CONFIDENTIAL_COMPUTE_ALLOC_PARAMS { + NvHandle hClient; +} NV_CONFIDENTIAL_COMPUTE_ALLOC_PARAMS; + diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/common/sdk/nvidia/inc/class/clcba2.h nvidia-open-gpu-kernel-modules-535.161.08/src/common/sdk/nvidia/inc/class/clcba2.h --- nvidia-open-gpu-kernel-modules-525.147.05/src/common/sdk/nvidia/inc/class/clcba2.h 1970-01-01 00:00:00.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/common/sdk/nvidia/inc/class/clcba2.h 2024-03-05 22:14:40.000000000 +0000 @@ -0,0 +1,158 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2022-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#include "nvtypes.h" + +#ifndef _clcba2_h_ +#define _clcba2_h_ + +#ifdef __cplusplus +extern "C" { +#endif + +#define HOPPER_SEC2_WORK_LAUNCH_A (0x0000CBA2) + +typedef volatile struct _clcba2_tag0 { + NvV32 Reserved00[0x100]; + NvV32 DecryptCopySrcAddrHi; // 0x00000400 - 0x00000403 + NvV32 DecryptCopySrcAddrLo; // 0x00000404 - 0x00000407 + NvV32 DecryptCopyDstAddrHi; // 0x00000408 - 0x0000040B + NvV32 DecryptCopyDstAddrLo; // 0x0000040c - 0x0000040F + NvU32 DecryptCopySize; // 0x00000410 - 0x00000413 + NvU32 DecryptCopyAuthTagAddrHi; // 0x00000414 - 0x00000417 + NvU32 DecryptCopyAuthTagAddrLo; // 0x00000418 - 0x0000041B + NvV32 DigestAddrHi; // 0x0000041C - 0x0000041F + NvV32 DigestAddrLo; // 0x00000420 - 0x00000423 + NvV32 Reserved01[0x7]; + NvV32 SemaphoreA; // 0x00000440 - 0x00000443 + NvV32 SemaphoreB; // 0x00000444 - 0x00000447 + NvV32 SemaphoreSetPayloadLower; // 0x00000448 - 0x0000044B + NvV32 SemaphoreSetPayloadUppper; // 0x0000044C - 0x0000044F + NvV32 SemaphoreD; // 0x00000450 - 0x00000453 + NvU32 Reserved02[0x7]; + NvV32 Execute; // 0x00000470 - 0x00000473 + NvV32 Reserved03[0x23]; +} NVCBA2_HOPPER_SEC2_WORK_LAUNCH_AControlPio; + +#define NVCBA2_DECRYPT_COPY_SRC_ADDR_HI (0x00000400) +#define NVCBA2_DECRYPT_COPY_SRC_ADDR_HI_DATA 24:0 +#define NVCBA2_DECRYPT_COPY_SRC_ADDR_LO (0x00000404) +#define NVCBA2_DECRYPT_COPY_SRC_ADDR_LO_DATA 31:4 +#define NVCBA2_DECRYPT_COPY_DST_ADDR_HI (0x00000408) +#define NVCBA2_DECRYPT_COPY_DST_ADDR_HI_DATA 24:0 +#define NVCBA2_DECRYPT_COPY_DST_ADDR_LO (0x0000040c) +#define NVCBA2_DECRYPT_COPY_DST_ADDR_LO_DATA 31:4 +#define NVCBA2_DECRYPT_COPY_SIZE (0x00000410) +#define NVCBA2_DECRYPT_COPY_SIZE_DATA 31:2 +#define NVCBA2_DECRYPT_COPY_AUTH_TAG_ADDR_HI (0x00000414) +#define NVCBA2_DECRYPT_COPY_AUTH_TAG_ADDR_HI_DATA 24:0 +#define NVCBA2_DECRYPT_COPY_AUTH_TAG_ADDR_LO (0x00000418) +#define NVCBA2_DECRYPT_COPY_AUTH_TAG_ADDR_LO_DATA 31:4 +#define NVCBA2_METHOD_STREAM_AUTH_TAG_ADDR_HI (0x0000041C) +#define NVCBA2_METHOD_STREAM_AUTH_TAG_ADDR_HI_DATA 24:0 +#define NVCBA2_METHOD_STREAM_AUTH_TAG_ADDR_LO (0x00000420) +#define NVCBA2_METHOD_STREAM_AUTH_TAG_ADDR_LO_DATA 31:4 +#define NVCBA2_SEMAPHORE_A (0x00000440) +#define NVCBA2_SEMAPHORE_A_UPPER 24:0 +#define NVCBA2_SEMAPHORE_B (0x00000444) +#define NVCBA2_SEMAPHORE_B_LOWER 31:2 +#define NVCBA2_SET_SEMAPHORE_PAYLOAD_LOWER (0x00000448) +#define NVCBA2_SET_SEMAPHORE_PAYLOAD_LOWER_DATA 31:0 +#define NVCBA2_SET_SEMAPHORE_PAYLOAD_UPPER (0x0000044C) +#define NVCBA2_SET_SEMAPHORE_PAYLOAD_UPPER_DATA 31:0 +#define NVCBA2_SEMAPHORE_D (0x00000450) +#define NVCBA2_SEMAPHORE_D_NOTIFY_INTR 0:0 +#define NVCBA2_SEMAPHORE_D_NOTIFY_INTR_DISABLE (0x00000000) +#define NVCBA2_SEMAPHORE_D_NOTIFY_INTR_ENABLE (0x00000001) +#define NVCBA2_SEMAPHORE_D_PAYLOAD_SIZE 1:1 +#define NVCBA2_SEMAPHORE_D_PAYLOAD_SIZE_32_BIT (0x00000000) +#define NVCBA2_SEMAPHORE_D_PAYLOAD_SIZE_64_BIT (0x00000001) +#define NVCBA2_SEMAPHORE_D_TIMESTAMP 2:2 +#define NVCBA2_SEMAPHORE_D_TIMESTAMP_DISABLE (0x00000000) +#define NVCBA2_SEMAPHORE_D_TIMESTAMP_ENABLE (0x00000001) +#define NVCBA2_SEMAPHORE_D_FLUSH_DISABLE 3:3 +#define NVCBA2_SEMAPHORE_D_FLUSH_DISABLE_FALSE (0x00000000) +#define NVCBA2_SEMAPHORE_D_FLUSH_DISABLE_TRUE (0x00000001) +#define NVCBA2_EXECUTE (0x00000470) +#define NVCBA2_EXECUTE_NOTIFY 0:0 +#define NVCBA2_EXECUTE_NOTIFY_DISABLE (0x00000000) +#define NVCBA2_EXECUTE_NOTIFY_ENABLE (0x00000001) +#define NVCBA2_EXECUTE_NOTIFY_ON 1:1 +#define NVCBA2_EXECUTE_NOTIFY_ON_END (0x00000000) +#define NVCBA2_EXECUTE_NOTIFY_ON_BEGIN (0x00000001) +#define NVCBA2_EXECUTE_FLUSH_DISABLE 2:2 +#define NVCBA2_EXECUTE_FLUSH_DISABLE_FALSE (0x00000000) +#define NVCBA2_EXECUTE_FLUSH_DISABLE_TRUE (0x00000001) +#define NVCBA2_EXECUTE_NOTIFY_INTR 3:3 +#define NVCBA2_EXECUTE_NOTIFY_INTR_DISABLE (0x00000000) +#define NVCBA2_EXECUTE_NOTIFY_INTR_ENABLE (0x00000001) +#define NVCBA2_EXECUTE_PAYLOAD_SIZE 4:4 +#define NVCBA2_EXECUTE_PAYLOAD_SIZE_32_BIT (0x00000000) +#define NVCBA2_EXECUTE_PAYLOAD_SIZE_64_BIT (0x00000001) +#define NVCBA2_EXECUTE_TIMESTAMP 5:5 +#define NVCBA2_EXECUTE_TIMESTAMP_DISABLE (0x00000000) +#define NVCBA2_EXECUTE_TIMESTAMP_ENABLE (0x00000001) +#define NVCBA2_EXECUTE_PHYSICAL_SCRUBBER 6:6 +#define NVCBA2_EXECUTE_PHYSICAL_SCRUBBER_DISABLE (0x00000000) +#define NVCBA2_EXECUTE_PHYSICAL_SCRUBBER_ENABLE (0x00000001) + +// Class definitions +#define NVCBA2_DECRYPT_COPY_SIZE_MAX_BYTES (2*1024*1024) +#define NVCBA2_DECRYPT_SCRUB_SIZE_MAX_BYTES (1024*1024*1024) + +// Errors +#define NVCBA2_ERROR_NONE (0x00000000) +#define NVCBA2_ERROR_DECRYPT_COPY_SRC_ADDR_MISALIGNED_POINTER (0x00000001) +#define NVCBA2_ERROR_DECRYPT_COPY_DEST_ADDR_MISALIGNED_POINTER (0x00000002) +#define NVCBA2_ERROR_DECRYPT_COPY_AUTH_TAG_ADDR_MISALIGNED_POINTER (0x00000003) +#define NVCBA2_ERROR_DECRYPT_COPY_DMA_NACK (0x00000004) +#define NVCBA2_ERROR_DECRYPT_COPY_AUTH_TAG_MISMATCH (0x00000005) +#define NVCBA2_ERROR_METHOD_STREAM_AUTH_TAG_ADDR_MISALIGNED_POINTER (0x00000006) +#define NVCBA2_ERROR_METHOD_STREAM_AUTH_TAG_ADDR_DMA_NACK (0x00000007) +#define NVCBA2_ERROR_METHOD_STREAM_AUTH_TAG_CHECK_FAILURE (0x00000008) +#define NVCBA2_ERROR_MISALIGNED_SIZE (0x00000009) +#define NVCBA2_ERROR_MISSING_METHODS (0x0000000A) +#define NVCBA2_ERROR_SEMAPHORE_RELEASE_DMA_NACK (0x0000000B) +#define NVCBA2_ERROR_DECRYPT_SIZE_MAX_EXCEEDED (0x0000000C) +#define NVCBA2_ERROR_OS_APPLICATION (0x0000000D) +#define NVCBA2_ERROR_INVALID_CTXSW_REQUEST (0x0000000E) +#define NVCBA2_ERROR_BUFFER_OVERFLOW (0x0000000F) +#define NVCBA2_ERROR_IV_OVERFLOW (0x00000010) +#define NVCBA2_ERROR_INTERNAL_SETUP_FAILURE (0x00000011) +#define NVCBA2_ERROR_DECRYPT_COPY_INTERNAL_DMA_FAILURE (0x00000012) +#define NVCBA2_ERROR_METHOD_STREAM_AUTH_TAG_ADDR_INTERNAL_DMA_FAILURE (0x00000013) +#define NVCBA2_ERROR_METHOD_STREAM_AUTH_TAG_HMAC_CALC_FAILURE (0x00000014) +#define NVCBA2_ERROR_NONCE_OVERFLOW (0x00000015) +#define NVCBA2_ERROR_AES_GCM_DECRYPTION_FAILURE (0x00000016) +#define NVCBA2_ERROR_SEMAPHORE_RELEASE_INTERNAL_DMA_FAILURE (0x00000017) +#define NVCBA2_ERROR_KEY_DERIVATION_FAILURE (0x00000018) +#define NVCBA2_ERROR_SCRUBBER_FAILURE (0x00000019) +#define NVCBA2_ERROR_SCRUBBER_INVALD_ADDRESS (0x0000001a) +#define NVCBA2_ERROR_SCRUBBER_INSUFFICIENT_PERMISSIONS (0x0000001b) +#define NVCBA2_ERROR_SCRUBBER_MUTEX_ACQUIRE_FAILURE (0x0000001c) +#define NVCBA2_ERROR_SCRUB_SIZE_MAX_EXCEEDED (0x0000001d) + +#ifdef __cplusplus +}; /* extern "C" */ +#endif +#endif // _clcba2_h diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/common/sdk/nvidia/inc/ctrl/ctrl0000/ctrl0000base.h nvidia-open-gpu-kernel-modules-535.161.08/src/common/sdk/nvidia/inc/ctrl/ctrl0000/ctrl0000base.h --- nvidia-open-gpu-kernel-modules-525.147.05/src/common/sdk/nvidia/inc/ctrl/ctrl0000/ctrl0000base.h 2023-10-25 20:22:05.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/common/sdk/nvidia/inc/ctrl/ctrl0000/ctrl0000base.h 2024-03-05 22:14:55.000000000 +0000 @@ -25,7 +25,7 @@ // // This file was generated with FINN, an NVIDIA coding tool. -// Source file: ctrl/ctrl0000/ctrl0000base.finn +// Source file: ctrl/ctrl0000/ctrl0000base.finn // #include "ctrl/ctrlxxxx.h" diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/common/sdk/nvidia/inc/ctrl/ctrl0000/ctrl0000client.h nvidia-open-gpu-kernel-modules-535.161.08/src/common/sdk/nvidia/inc/ctrl/ctrl0000/ctrl0000client.h --- nvidia-open-gpu-kernel-modules-525.147.05/src/common/sdk/nvidia/inc/ctrl/ctrl0000/ctrl0000client.h 2023-10-25 20:22:05.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/common/sdk/nvidia/inc/ctrl/ctrl0000/ctrl0000client.h 2024-03-05 22:14:55.000000000 +0000 @@ -26,7 +26,7 @@ // // This file was generated with FINN, an NVIDIA coding tool. -// Source file: ctrl/ctrl0000/ctrl0000client.finn +// Source file: ctrl/ctrl0000/ctrl0000client.finn // #include "ctrl/ctrl0000/ctrl0000base.h" diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/common/sdk/nvidia/inc/ctrl/ctrl0000/ctrl0000diag.h nvidia-open-gpu-kernel-modules-535.161.08/src/common/sdk/nvidia/inc/ctrl/ctrl0000/ctrl0000diag.h --- nvidia-open-gpu-kernel-modules-525.147.05/src/common/sdk/nvidia/inc/ctrl/ctrl0000/ctrl0000diag.h 2023-10-25 20:22:05.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/common/sdk/nvidia/inc/ctrl/ctrl0000/ctrl0000diag.h 2024-03-05 22:14:56.000000000 +0000 @@ -26,7 +26,7 @@ // // This file was generated with FINN, an NVIDIA coding tool. -// Source file: ctrl/ctrl0000/ctrl0000diag.finn +// Source file: ctrl/ctrl0000/ctrl0000diag.finn // #include "ctrl/ctrl0000/ctrl0000base.h" diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/common/sdk/nvidia/inc/ctrl/ctrl0000/ctrl0000event.h nvidia-open-gpu-kernel-modules-535.161.08/src/common/sdk/nvidia/inc/ctrl/ctrl0000/ctrl0000event.h --- nvidia-open-gpu-kernel-modules-525.147.05/src/common/sdk/nvidia/inc/ctrl/ctrl0000/ctrl0000event.h 2023-10-25 20:22:05.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/common/sdk/nvidia/inc/ctrl/ctrl0000/ctrl0000event.h 2024-03-05 22:14:56.000000000 +0000 @@ -27,7 +27,7 @@ // // This file was generated with FINN, an NVIDIA coding tool. -// Source file: ctrl/ctrl0000/ctrl0000event.finn +// Source file: ctrl/ctrl0000/ctrl0000event.finn // #include "ctrl/ctrl0000/ctrl0000base.h" diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/common/sdk/nvidia/inc/ctrl/ctrl0000/ctrl0000gpu.h nvidia-open-gpu-kernel-modules-535.161.08/src/common/sdk/nvidia/inc/ctrl/ctrl0000/ctrl0000gpu.h --- nvidia-open-gpu-kernel-modules-525.147.05/src/common/sdk/nvidia/inc/ctrl/ctrl0000/ctrl0000gpu.h 2023-10-25 20:22:05.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/common/sdk/nvidia/inc/ctrl/ctrl0000/ctrl0000gpu.h 2024-03-05 22:14:56.000000000 +0000 @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 2005-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2005-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -27,7 +27,7 @@ // // This file was generated with FINN, an NVIDIA coding tool. -// Source file: ctrl/ctrl0000/ctrl0000gpu.finn +// Source file: ctrl/ctrl0000/ctrl0000gpu.finn // #include "ctrl/ctrl0000/ctrl0000base.h" @@ -90,6 +90,11 @@ NvS32 numaId; } NV0000_CTRL_GPU_GET_ID_INFO_PARAMS; +#define NV0000_CTRL_SLI_STATUS_OK (0x00000000U) +#define NV0000_CTRL_SLI_STATUS_OS_NOT_SUPPORTED (0x00000002U) +#define NV0000_CTRL_SLI_STATUS_GPU_NOT_SUPPORTED (0x00000040U) +#define NV0000_CTRL_SLI_STATUS_INVALID_GPU_COUNT (0x00000001U) + /* * NV0000_CTRL_CMD_GPU_GET_ID_INFO_V2 * This command returns GPU instance information for the specified GPU. @@ -138,7 +143,8 @@ * GPU instance numbers are assigned in bus-probe order beginning with * zero and are limited to one less the number of GPUs in the system. * [out] numaId - * This parameter returns the ID of NUMA node for the specified GPU. + * This parameter returns the ID of NUMA node for the specified GPU or + * the subscribed MIG partition when MIG is enabled. * In case there is no NUMA node, NV0000_CTRL_NO_NUMA_NODE is returned. * * Possible status values returned are: @@ -149,7 +155,7 @@ -#define NV0000_CTRL_CMD_GPU_GET_ID_INFO_V2 (0x205U) /* finn: Evaluated from "(FINN_NV01_ROOT_GPU_INTERFACE_ID << 8) | NV0000_CTRL_GPU_GET_ID_INFO_V2_PARAMS_MESSAGE_ID" */ +#define NV0000_CTRL_CMD_GPU_GET_ID_INFO_V2 (0x205U) /* finn: Evaluated from "(FINN_NV01_ROOT_GPU_INTERFACE_ID << 8) | NV0000_CTRL_GPU_GET_ID_INFO_V2_PARAMS_MESSAGE_ID" */ #define NV0000_CTRL_GPU_GET_ID_INFO_V2_PARAMS_MESSAGE_ID (0x5U) @@ -437,6 +443,55 @@ /* + * NV0000_CTRL_CMD_GPU_GET_VIDEO_LINKS + * + * This command returns information about video bridge connections + * detected between GPUs in the system, organized as a table + * with one row per attached GPU and none, one or more peer GPUs + * listed in the columns of each row, if connected to the row head + * GPU via a video bridge. + * + * gpuId + * For each row, this field holds the GPU ID of the GPU + * whose connections are listed in the row. + * + * connectedGpuIds + * For each row, this table holds the GPU IDs of the + * GPUs connected to the GPU identified via the 'gpuId' + * field. + * + * links + * This table holds information about the video bridges + * connected between GPUs in the system. Each row + * represents connections to a single GPU. + * + * Please note: the table only reports video links between already + * attached GPUs. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_PARAM_STRUCT + * NV_ERR_INVALID_ARGUMENT + */ + +#define NV0000_CTRL_CMD_GPU_GET_VIDEO_LINKS (0x219U) /* finn: Evaluated from "(FINN_NV01_ROOT_GPU_INTERFACE_ID << 8) | NV0000_CTRL_GPU_GET_VIDEO_LINKS_PARAMS_MESSAGE_ID" */ + +#define NV0000_CTRL_GPU_MAX_VIDEO_LINKS 8U + +typedef struct NV0000_CTRL_GPU_VIDEO_LINKS { + NvU32 gpuId; + NvU32 connectedGpuIds[NV0000_CTRL_GPU_MAX_VIDEO_LINKS]; +} NV0000_CTRL_GPU_VIDEO_LINKS; + +#define NV0000_CTRL_GPU_GET_VIDEO_LINKS_PARAMS_MESSAGE_ID (0x19U) + +typedef struct NV0000_CTRL_GPU_GET_VIDEO_LINKS_PARAMS { + NV0000_CTRL_GPU_VIDEO_LINKS links[NV0000_CTRL_GPU_MAX_ATTACHED_GPUS]; +} NV0000_CTRL_GPU_GET_VIDEO_LINKS_PARAMS; + + + +/* * NV0000_CTRL_CMD_GPU_GET_SVM_SIZE * * This command is used to get the SVM size. @@ -869,5 +924,60 @@ NV_DECLARE_ALIGNED(NvU64 totalSize, 8); NV_DECLARE_ALIGNED(NvP64 pData, 8); } NV0000_CTRL_GPU_PUSH_GSP_UCODE_PARAMS; + +/* + * NV0000_CTRL_CMD_GPU_SET_NVLINK_BW_MODE + * + * This command is used to set NVLINK bandwidth for power saving + * + * The setting must be applied before the GPU is attached. + * NVLINK_BW_MODE is an NOP for non-NVLink GPUs. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_ARGUMENT + * NV_ERR_INVALID_DEVICE + * NV_ERR_INSUFFICIENT_PERMISSIONS + * NV_ERR_INVALID_STATE + * NV_ERR_IN_USE + */ + +#define NV0000_CTRL_CMD_GPU_NVLINK_BW_MODE_FULL (0x00U) +#define NV0000_CTRL_CMD_GPU_NVLINK_BW_MODE_OFF (0x01U) +#define NV0000_CTRL_CMD_GPU_NVLINK_BW_MODE_MIN (0x02U) +#define NV0000_CTRL_CMD_GPU_NVLINK_BW_MODE_HALF (0x03U) +#define NV0000_CTRL_CMD_GPU_NVLINK_BW_MODE_3QUARTER (0x04U) + +#define NV0000_CTRL_CMD_GPU_SET_NVLINK_BW_MODE (0x286U) /* finn: Evaluated from "(FINN_NV01_ROOT_GPU_INTERFACE_ID << 8) | NV0000_CTRL_GPU_SET_NVLINK_BW_MODE_PARAMS_MESSAGE_ID" */ +#define NV0000_CTRL_GPU_SET_NVLINK_BW_MODE_PARAMS_MESSAGE_ID (0x86U) + +typedef struct NV0000_CTRL_GPU_SET_NVLINK_BW_MODE_PARAMS { + NvU8 mode; +} NV0000_CTRL_GPU_SET_NVLINK_BW_MODE_PARAMS; + +/* + * NV0000_CTRL_CMD_GPU_GET_NVLINK_BW_MODE + * + * This command is used to get NVLINK bandwidth for power saving + * + * The setting must be applied before the GPU is attached. + * NVLINK_BW_MODE is an NOP for non-NVLink GPUs. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_ARGUMENT + * NV_ERR_INVALID_DEVICE + * NV_ERR_INSUFFICIENT_PERMISSIONS + * NV_ERR_INVALID_STATE + * NV_ERR_IN_USE + */ + +#define NV0000_CTRL_CMD_GPU_GET_NVLINK_BW_MODE (0x287U) /* finn: Evaluated from "(FINN_NV01_ROOT_GPU_INTERFACE_ID << 8) | NV0000_CTRL_GPU_GET_NVLINK_BW_MODE_PARAMS_MESSAGE_ID" */ +#define NV0000_CTRL_GPU_GET_NVLINK_BW_MODE_PARAMS_MESSAGE_ID (0x87U) + +typedef struct NV0000_CTRL_GPU_GET_NVLINK_BW_MODE_PARAMS { + NvU8 mode; +} NV0000_CTRL_GPU_GET_NVLINK_BW_MODE_PARAMS; + /* _ctrl0000gpu_h_ */ diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/common/sdk/nvidia/inc/ctrl/ctrl0000/ctrl0000gpuacct.h nvidia-open-gpu-kernel-modules-535.161.08/src/common/sdk/nvidia/inc/ctrl/ctrl0000/ctrl0000gpuacct.h --- nvidia-open-gpu-kernel-modules-525.147.05/src/common/sdk/nvidia/inc/ctrl/ctrl0000/ctrl0000gpuacct.h 2023-10-25 20:22:05.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/common/sdk/nvidia/inc/ctrl/ctrl0000/ctrl0000gpuacct.h 2024-03-05 22:14:57.000000000 +0000 @@ -26,7 +26,7 @@ // // This file was generated with FINN, an NVIDIA coding tool. -// Source file: ctrl/ctrl0000/ctrl0000gpuacct.finn +// Source file: ctrl/ctrl0000/ctrl0000gpuacct.finn // #include "ctrl/ctrl0000/ctrl0000base.h" diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/common/sdk/nvidia/inc/ctrl/ctrl0000/ctrl0000gsync.h nvidia-open-gpu-kernel-modules-535.161.08/src/common/sdk/nvidia/inc/ctrl/ctrl0000/ctrl0000gsync.h --- nvidia-open-gpu-kernel-modules-525.147.05/src/common/sdk/nvidia/inc/ctrl/ctrl0000/ctrl0000gsync.h 2023-10-25 20:22:05.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/common/sdk/nvidia/inc/ctrl/ctrl0000/ctrl0000gsync.h 2024-03-05 22:14:57.000000000 +0000 @@ -26,7 +26,7 @@ // // This file was generated with FINN, an NVIDIA coding tool. -// Source file: ctrl/ctrl0000/ctrl0000gsync.finn +// Source file: ctrl/ctrl0000/ctrl0000gsync.finn // #include "ctrl/ctrl0000/ctrl0000base.h" diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/common/sdk/nvidia/inc/ctrl/ctrl0000/ctrl0000nvd.h nvidia-open-gpu-kernel-modules-535.161.08/src/common/sdk/nvidia/inc/ctrl/ctrl0000/ctrl0000nvd.h --- nvidia-open-gpu-kernel-modules-525.147.05/src/common/sdk/nvidia/inc/ctrl/ctrl0000/ctrl0000nvd.h 2023-10-25 20:22:06.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/common/sdk/nvidia/inc/ctrl/ctrl0000/ctrl0000nvd.h 2024-03-05 22:14:57.000000000 +0000 @@ -27,7 +27,7 @@ // // This file was generated with FINN, an NVIDIA coding tool. -// Source file: ctrl/ctrl0000/ctrl0000nvd.finn +// Source file: ctrl/ctrl0000/ctrl0000nvd.finn // #include "ctrl/ctrl0000/ctrl0000base.h" diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/common/sdk/nvidia/inc/ctrl/ctrl0000/ctrl0000proc.h nvidia-open-gpu-kernel-modules-535.161.08/src/common/sdk/nvidia/inc/ctrl/ctrl0000/ctrl0000proc.h --- nvidia-open-gpu-kernel-modules-525.147.05/src/common/sdk/nvidia/inc/ctrl/ctrl0000/ctrl0000proc.h 2023-10-25 20:22:06.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/common/sdk/nvidia/inc/ctrl/ctrl0000/ctrl0000proc.h 2024-03-05 22:14:57.000000000 +0000 @@ -27,7 +27,7 @@ // // This file was generated with FINN, an NVIDIA coding tool. -// Source file: ctrl/ctrl0000/ctrl0000proc.finn +// Source file: ctrl/ctrl0000/ctrl0000proc.finn // #include "ctrl/ctrl0000/ctrl0000base.h" diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/common/sdk/nvidia/inc/ctrl/ctrl0000/ctrl0000syncgpuboost.h nvidia-open-gpu-kernel-modules-535.161.08/src/common/sdk/nvidia/inc/ctrl/ctrl0000/ctrl0000syncgpuboost.h --- nvidia-open-gpu-kernel-modules-525.147.05/src/common/sdk/nvidia/inc/ctrl/ctrl0000/ctrl0000syncgpuboost.h 2023-10-25 20:22:06.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/common/sdk/nvidia/inc/ctrl/ctrl0000/ctrl0000syncgpuboost.h 2024-03-05 22:14:57.000000000 +0000 @@ -26,7 +26,7 @@ // // This file was generated with FINN, an NVIDIA coding tool. -// Source file: ctrl/ctrl0000/ctrl0000syncgpuboost.finn +// Source file: ctrl/ctrl0000/ctrl0000syncgpuboost.finn // #include "ctrl/ctrl0000/ctrl0000base.h" diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/common/sdk/nvidia/inc/ctrl/ctrl0000/ctrl0000system.h nvidia-open-gpu-kernel-modules-535.161.08/src/common/sdk/nvidia/inc/ctrl/ctrl0000/ctrl0000system.h --- nvidia-open-gpu-kernel-modules-525.147.05/src/common/sdk/nvidia/inc/ctrl/ctrl0000/ctrl0000system.h 2023-10-25 20:22:06.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/common/sdk/nvidia/inc/ctrl/ctrl0000/ctrl0000system.h 2024-03-05 22:14:57.000000000 +0000 @@ -26,7 +26,7 @@ // // This file was generated with FINN, an NVIDIA coding tool. -// Source file: ctrl/ctrl0000/ctrl0000system.finn +// Source file: ctrl/ctrl0000/ctrl0000system.finn // #include "ctrl/ctrlxxxx.h" @@ -321,47 +321,6 @@ #define NV0000_CTRL_SYSTEM_CPU_CAP_AVX (0x00080000U) #define NV0000_CTRL_SYSTEM_CPU_CAP_ERMS (0x00100000U) -/* feature mask (as opposed to bugs, requirements, etc.) */ -#define NV0000_CTRL_SYSTEM_CPU_CAP_FEATURE_MASK (0x1f5e7fU) /* finn: Evaluated from "(NV0000_CTRL_SYSTEM_CPU_CAP_MMX | NV0000_CTRL_SYSTEM_CPU_CAP_SSE | NV0000_CTRL_SYSTEM_CPU_CAP_3DNOW | NV0000_CTRL_SYSTEM_CPU_CAP_SSE2 | NV0000_CTRL_SYSTEM_CPU_CAP_SFENCE | NV0000_CTRL_SYSTEM_CPU_CAP_WRITE_COMBINING | NV0000_CTRL_SYSTEM_CPU_CAP_ALTIVEC | NV0000_CTRL_SYSTEM_CPU_CAP_3DNOW_EXT | NV0000_CTRL_SYSTEM_CPU_CAP_MMX_EXT | NV0000_CTRL_SYSTEM_CPU_CAP_CMOV | NV0000_CTRL_SYSTEM_CPU_CAP_CLFLUSH | NV0000_CTRL_SYSTEM_CPU_CAP_SSE3 | NV0000_CTRL_SYSTEM_CPU_CAP_HT_CAPABLE | NV0000_CTRL_SYSTEM_CPU_CAP_SSE41 | NV0000_CTRL_SYSTEM_CPU_CAP_SSE42 | NV0000_CTRL_SYSTEM_CPU_CAP_AVX | NV0000_CTRL_SYSTEM_CPU_CAP_ERMS)" */ - -/* - * NV0000_CTRL_CMD_SYSTEM_GET_CAPS - * - * This command returns the set of system capabilities in the - * form of an array of unsigned bytes. System capabilities include - * supported features and required workarounds for the system, - * each represented by a byte offset into the table and a bit - * position within that byte. - * - * capsTblSize - * This parameter specifies the size in bytes of the caps table. - * This value should be set to NV0000_CTRL_SYSTEM_CAPS_TBL_SIZE. - * capsTbl - * This parameter specifies a pointer to the client's caps table buffer - * into which the system caps bits will be transferred by the RM. - * The caps table is an array of unsigned bytes. - * - * Possible status values returned are: - * NV_OK - * NV_ERR_INVALID_PARAM_STRUCT - * NV_ERR_INVALID_ARGUMENT - */ -#define NV0000_CTRL_CMD_SYSTEM_GET_CAPS (0x103U) /* finn: Evaluated from "(FINN_NV01_ROOT_SYSTEM_INTERFACE_ID << 8) | 0x3" */ - -typedef struct NV0000_CTRL_SYSTEM_GET_CAPS_PARAMS { - NvU32 capsTblSize; - NV_DECLARE_ALIGNED(NvP64 capsTbl, 8); -} NV0000_CTRL_SYSTEM_GET_CAPS_PARAMS; - -/* extract cap bit setting from tbl */ -#define NV0000_CTRL_SYSTEM_GET_CAP(tbl,c) (((NvU8)tbl[(1?c)]) & (0?c)) - -/* caps format is byte_index:bit_mask */ -#define NV0000_CTRL_SYSTEM_CAPS_POWER_SLI_SUPPORTED 0:0x01 - -/* size in bytes of system caps table */ -#define NV0000_CTRL_SYSTEM_CAPS_TBL_SIZE 1U - /* * NV0000_CTRL_CMD_SYSTEM_GET_CHIPSET_INFO * @@ -418,13 +377,13 @@ * NV_ERR_INVALID_ARGUMENT * NV_ERR_OPERATING_SYSTEM */ -#define NV0000_CTRL_CMD_SYSTEM_GET_CHIPSET_INFO (0x104U) /* finn: Evaluated from "(FINN_NV01_ROOT_SYSTEM_INTERFACE_ID << 8) | NV0000_CTRL_SYSTEM_GET_CHIPSET_INFO_PARAMS_MESSAGE_ID" */ +#define NV0000_CTRL_CMD_SYSTEM_GET_CHIPSET_INFO (0x104U) /* finn: Evaluated from "(FINN_NV01_ROOT_SYSTEM_INTERFACE_ID << 8) | NV0000_CTRL_SYSTEM_GET_CHIPSET_INFO_PARAMS_MESSAGE_ID" */ /* maximum name string length */ -#define NV0000_SYSTEM_MAX_CHIPSET_STRING_LENGTH (0x0000020U) +#define NV0000_SYSTEM_MAX_CHIPSET_STRING_LENGTH (0x0000020U) /* invalid id */ -#define NV0000_SYSTEM_CHIPSET_INVALID_ID (0xffffU) +#define NV0000_SYSTEM_CHIPSET_INVALID_ID (0xffffU) #define NV0000_CTRL_SYSTEM_GET_CHIPSET_INFO_PARAMS_MESSAGE_ID (0x4U) @@ -1571,9 +1530,11 @@ * Please note: as implied above, administrator privileges are * required to modify security settings. */ -#define NV0000_CTRL_CMD_SYSTEM_SET_SECURITY_SETTINGS (0x129U) /* finn: Evaluated from "(FINN_NV01_ROOT_SYSTEM_INTERFACE_ID << 8) | 0x29" */ +#define NV0000_CTRL_CMD_SYSTEM_SET_SECURITY_SETTINGS (0x129U) /* finn: Evaluated from "(FINN_NV01_ROOT_SYSTEM_INTERFACE_ID << 8) | NV0000_CTRL_SYSTEM_GPS_GET_PERF_SENSOR_COUNTERS_PARAMS_MESSAGE_ID" */ #define GPS_MAX_COUNTERS_PER_BLOCK 32U +#define NV0000_CTRL_SYSTEM_GPS_GET_PERF_SENSOR_COUNTERS_PARAMS_MESSAGE_ID (0x29U) + typedef struct NV0000_CTRL_SYSTEM_GPS_GET_PERF_SENSOR_COUNTERS_PARAMS { NvU32 objHndl; NvU32 blockId; @@ -1583,9 +1544,17 @@ NvU32 counterBlock[GPS_MAX_COUNTERS_PER_BLOCK]; } NV0000_CTRL_SYSTEM_GPS_GET_PERF_SENSOR_COUNTERS_PARAMS; -#define NV0000_CTRL_CMD_SYSTEM_GPS_GET_PERF_SENSORS (0x12cU) /* finn: Evaluated from "(FINN_NV01_ROOT_SYSTEM_INTERFACE_ID << 8) | 0x2C" */ +#define NV0000_CTRL_CMD_SYSTEM_GPS_GET_PERF_SENSORS (0x12cU) /* finn: Evaluated from "(FINN_NV01_ROOT_SYSTEM_INTERFACE_ID << 8) | NV0000_CTRL_SYSTEM_GPS_GET_PERF_SENSORS_PARAMS_MESSAGE_ID" */ + +#define NV0000_CTRL_SYSTEM_GPS_GET_PERF_SENSORS_PARAMS_MESSAGE_ID (0x2CU) + +typedef NV0000_CTRL_SYSTEM_GPS_GET_PERF_SENSOR_COUNTERS_PARAMS NV0000_CTRL_SYSTEM_GPS_GET_PERF_SENSORS_PARAMS; + +#define NV0000_CTRL_CMD_SYSTEM_GPS_GET_EXTENDED_PERF_SENSORS (0x12eU) /* finn: Evaluated from "(FINN_NV01_ROOT_SYSTEM_INTERFACE_ID << 8) | NV0000_CTRL_SYSTEM_GPS_GET_EXTENDED_PERF_SENSORS_PARAMS_MESSAGE_ID" */ -#define NV0000_CTRL_CMD_SYSTEM_GPS_GET_EXTENDED_PERF_SENSORS (0x12eU) /* finn: Evaluated from "(FINN_NV01_ROOT_SYSTEM_INTERFACE_ID << 8) | 0x2E" */ +#define NV0000_CTRL_SYSTEM_GPS_GET_EXTENDED_PERF_SENSORS_PARAMS_MESSAGE_ID (0x2EU) + +typedef NV0000_CTRL_SYSTEM_GPS_GET_PERF_SENSOR_COUNTERS_PARAMS NV0000_CTRL_SYSTEM_GPS_GET_EXTENDED_PERF_SENSORS_PARAMS; /* * NV0000_CTRL_CMD_SYSTEM_GPS_CALL_ACPI @@ -1621,7 +1590,7 @@ * NV_ERR_INSUFFICIENT_PERMISSIONS * */ -#define GPS_MAX_ACPI_OUTPUT_BUFFER_SIZE 288U +#define GPS_MAX_ACPI_OUTPUT_BUFFER_SIZE 288U #define NV0000_CTRL_SYSTEM_GPS_CALL_ACPI_PARAMS_MESSAGE_ID (0x2DU) typedef struct NV0000_CTRL_SYSTEM_GPS_CALL_ACPI_PARAMS { @@ -2855,9 +2824,17 @@ NvU32 counterBlock[PFM_REQ_HNDLR_MAX_COUNTERS_PER_BLOCK]; } NV0000_CTRL_SYSTEM_PFM_REQ_HNDLR_GET_PERF_SENSOR_COUNTERS_PARAMS; -#define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_GET_PERF_SENSORS (0x146U) /* finn: Evaluated from "(FINN_NV01_ROOT_SYSTEM_INTERFACE_ID << 8) | 0x46" */ +#define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_GET_PERF_SENSORS (0x146U) /* finn: Evaluated from "(FINN_NV01_ROOT_SYSTEM_INTERFACE_ID << 8) | NV0000_CTRL_SYSTEM_PFM_REQ_HNDLR_GET_PERF_SENSORS_PARAMS_MESSAGE_ID" */ + +#define NV0000_CTRL_SYSTEM_PFM_REQ_HNDLR_GET_PERF_SENSORS_PARAMS_MESSAGE_ID (0x46U) + +typedef NV0000_CTRL_SYSTEM_PFM_REQ_HNDLR_GET_PERF_SENSOR_COUNTERS_PARAMS NV0000_CTRL_SYSTEM_PFM_REQ_HNDLR_GET_PERF_SENSORS_PARAMS; + +#define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_GET_EXTENDED_PERF_SENSORS (0x147U) /* finn: Evaluated from "(FINN_NV01_ROOT_SYSTEM_INTERFACE_ID << 8) | NV0000_CTRL_SYSTEM_PFM_REQ_HNDLR_GET_EXTENDED_PERF_SENSORS_PARAMS_MESSAGE_ID" */ + +#define NV0000_CTRL_SYSTEM_PFM_REQ_HNDLR_GET_EXTENDED_PERF_SENSORS_PARAMS_MESSAGE_ID (0x47U) -#define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_GET_EXTENDED_PERF_SENSORS (0x147U) /* finn: Evaluated from "(FINN_NV01_ROOT_SYSTEM_INTERFACE_ID << 8) | 0x47" */ +typedef NV0000_CTRL_SYSTEM_PFM_REQ_HNDLR_GET_PERF_SENSOR_COUNTERS_PARAMS NV0000_CTRL_SYSTEM_PFM_REQ_HNDLR_GET_EXTENDED_PERF_SENSORS_PARAMS; /* * NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CALL_ACPI @@ -2893,7 +2870,7 @@ * NV_ERR_INSUFFICIENT_PERMISSIONS * */ -#define PFM_REQ_HNDLR_MAX_ACPI_OUTPUT_BUFFER_SIZE 288U +#define PFM_REQ_HNDLR_MAX_ACPI_OUTPUT_BUFFER_SIZE 288U #define NV0000_CTRL_SYSTEM_PFM_REQ_HNDLR_CALL_ACPI_PARAMS_MESSAGE_ID (0x43U) typedef struct NV0000_CTRL_SYSTEM_PFM_REQ_HNDLR_CALL_ACPI_PARAMS { diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/common/sdk/nvidia/inc/ctrl/ctrl0000/ctrl0000unix.h nvidia-open-gpu-kernel-modules-535.161.08/src/common/sdk/nvidia/inc/ctrl/ctrl0000/ctrl0000unix.h --- nvidia-open-gpu-kernel-modules-525.147.05/src/common/sdk/nvidia/inc/ctrl/ctrl0000/ctrl0000unix.h 2023-10-25 20:22:06.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/common/sdk/nvidia/inc/ctrl/ctrl0000/ctrl0000unix.h 2024-03-05 22:14:57.000000000 +0000 @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 2009-2021 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2009-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -27,7 +27,7 @@ // // This file was generated with FINN, an NVIDIA coding tool. -// Source file: ctrl/ctrl0000/ctrl0000unix.finn +// Source file: ctrl/ctrl0000/ctrl0000unix.finn // #include "ctrl/ctrl0000/ctrl0000base.h" @@ -418,8 +418,7 @@ #define NV0000_CTRL_CMD_OS_UNIX_IMPORT_OBJECT_TYPE_VIDMEM 1 #define NV0000_CTRL_CMD_OS_UNIX_IMPORT_OBJECT_TYPE_SYSMEM 2 #define NV0000_CTRL_CMD_OS_UNIX_IMPORT_OBJECT_TYPE_FABRIC 3 - - +#define NV0000_CTRL_CMD_OS_UNIX_IMPORT_OBJECT_TYPE_FABRIC_MC 4 #define NV0000_CTRL_OS_UNIX_IMPORT_OBJECTS_FROM_FD_PARAMS_MESSAGE_ID (0xCU) diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/common/sdk/nvidia/inc/ctrl/ctrl0000/ctrl0000vgpu.h nvidia-open-gpu-kernel-modules-535.161.08/src/common/sdk/nvidia/inc/ctrl/ctrl0000/ctrl0000vgpu.h --- nvidia-open-gpu-kernel-modules-525.147.05/src/common/sdk/nvidia/inc/ctrl/ctrl0000/ctrl0000vgpu.h 2023-10-25 20:22:06.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/common/sdk/nvidia/inc/ctrl/ctrl0000/ctrl0000vgpu.h 2024-03-05 22:14:57.000000000 +0000 @@ -27,7 +27,7 @@ // // This file was generated with FINN, an NVIDIA coding tool. -// Source file: ctrl/ctrl0000/ctrl0000vgpu.finn +// Source file: ctrl/ctrl0000/ctrl0000vgpu.finn // #include "ctrl/ctrl0000/ctrl0000base.h" diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/common/sdk/nvidia/inc/ctrl/ctrl0002.h nvidia-open-gpu-kernel-modules-535.161.08/src/common/sdk/nvidia/inc/ctrl/ctrl0002.h --- nvidia-open-gpu-kernel-modules-525.147.05/src/common/sdk/nvidia/inc/ctrl/ctrl0002.h 2023-10-25 20:22:06.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/common/sdk/nvidia/inc/ctrl/ctrl0002.h 2024-03-05 22:14:58.000000000 +0000 @@ -27,7 +27,7 @@ // // This file was generated with FINN, an NVIDIA coding tool. -// Source file: ctrl/ctrl0002.finn +// Source file: ctrl/ctrl0002.finn // #include "ctrl/ctrlxxxx.h" diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/common/sdk/nvidia/inc/ctrl/ctrl0004.h nvidia-open-gpu-kernel-modules-535.161.08/src/common/sdk/nvidia/inc/ctrl/ctrl0004.h --- nvidia-open-gpu-kernel-modules-525.147.05/src/common/sdk/nvidia/inc/ctrl/ctrl0004.h 2023-10-25 20:22:06.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/common/sdk/nvidia/inc/ctrl/ctrl0004.h 2024-03-05 22:14:58.000000000 +0000 @@ -27,7 +27,7 @@ // // This file was generated with FINN, an NVIDIA coding tool. -// Source file: ctrl/ctrl0004.finn +// Source file: ctrl/ctrl0004.finn // #include "ctrl/ctrlxxxx.h" diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/common/sdk/nvidia/inc/ctrl/ctrl000f.h nvidia-open-gpu-kernel-modules-535.161.08/src/common/sdk/nvidia/inc/ctrl/ctrl000f.h --- nvidia-open-gpu-kernel-modules-525.147.05/src/common/sdk/nvidia/inc/ctrl/ctrl000f.h 2023-10-25 20:22:06.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/common/sdk/nvidia/inc/ctrl/ctrl000f.h 2024-03-05 22:14:58.000000000 +0000 @@ -25,7 +25,7 @@ // // This file was generated with FINN, an NVIDIA coding tool. -// Source file: ctrl/ctrl000f.finn +// Source file: ctrl/ctrl000f.finn // #include "ctrl/ctrlxxxx.h" diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/common/sdk/nvidia/inc/ctrl/ctrl0020.h nvidia-open-gpu-kernel-modules-535.161.08/src/common/sdk/nvidia/inc/ctrl/ctrl0020.h --- nvidia-open-gpu-kernel-modules-525.147.05/src/common/sdk/nvidia/inc/ctrl/ctrl0020.h 2023-10-25 20:22:07.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/common/sdk/nvidia/inc/ctrl/ctrl0020.h 2024-03-05 22:14:58.000000000 +0000 @@ -27,7 +27,7 @@ // // This file was generated with FINN, an NVIDIA coding tool. -// Source file: ctrl/ctrl0020.finn +// Source file: ctrl/ctrl0020.finn // #include "ctrl/ctrlxxxx.h" diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/common/sdk/nvidia/inc/ctrl/ctrl003e.h nvidia-open-gpu-kernel-modules-535.161.08/src/common/sdk/nvidia/inc/ctrl/ctrl003e.h --- nvidia-open-gpu-kernel-modules-525.147.05/src/common/sdk/nvidia/inc/ctrl/ctrl003e.h 2023-10-25 20:22:07.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/common/sdk/nvidia/inc/ctrl/ctrl003e.h 2024-03-05 22:14:58.000000000 +0000 @@ -27,7 +27,7 @@ // // This file was generated with FINN, an NVIDIA coding tool. -// Source file: ctrl/ctrl003e.finn +// Source file: ctrl/ctrl003e.finn // #include "ctrl/ctrlxxxx.h" diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/common/sdk/nvidia/inc/ctrl/ctrl0041.h nvidia-open-gpu-kernel-modules-535.161.08/src/common/sdk/nvidia/inc/ctrl/ctrl0041.h --- nvidia-open-gpu-kernel-modules-525.147.05/src/common/sdk/nvidia/inc/ctrl/ctrl0041.h 2023-10-25 20:22:07.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/common/sdk/nvidia/inc/ctrl/ctrl0041.h 2024-03-05 22:14:58.000000000 +0000 @@ -27,7 +27,7 @@ // // This file was generated with FINN, an NVIDIA coding tool. -// Source file: ctrl/ctrl0041.finn +// Source file: ctrl/ctrl0041.finn // #include "nvos.h" @@ -201,10 +201,7 @@ * This index is used to request the surface address space type. * Returned values are described by NV0000_CTRL_CMD_CLIENT_GET_ADDR_SPACE_TYPE. */ -typedef struct NV0041_CTRL_SURFACE_INFO { - NvU32 index; - NvU32 data; -} NV0041_CTRL_SURFACE_INFO; +typedef NVXXXX_CTRL_XXX_INFO NV0041_CTRL_SURFACE_INFO; /* valid surface info index values */ #define NV0041_CTRL_SURFACE_INFO_INDEX_ATTRS (0x00000001) @@ -381,7 +378,7 @@ #define NV0041_CTRL_GET_MEM_PAGE_SIZE_PARAMS_MESSAGE_ID (0x18U) typedef struct NV0041_CTRL_GET_MEM_PAGE_SIZE_PARAMS { - NvU32 pageSize; /* [out] - page size */ + NV_DECLARE_ALIGNED(NvU64 pageSize, 8); /* [out] - page size */ } NV0041_CTRL_GET_MEM_PAGE_SIZE_PARAMS; /* diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/common/sdk/nvidia/inc/ctrl/ctrl0050.h nvidia-open-gpu-kernel-modules-535.161.08/src/common/sdk/nvidia/inc/ctrl/ctrl0050.h --- nvidia-open-gpu-kernel-modules-525.147.05/src/common/sdk/nvidia/inc/ctrl/ctrl0050.h 1970-01-01 00:00:00.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/common/sdk/nvidia/inc/ctrl/ctrl0050.h 2024-03-05 22:14:59.000000000 +0000 @@ -0,0 +1,208 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#pragma once + +#include + +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: ctrl/ctrl0050.finn +// + +#include "ctrl/ctrlxxxx.h" + +#define NV0050_CTRL_CMD(cat, idx) NVXXXX_CTRL_CMD(0x0050, NV0050_CTRL_##cat, idx) + +#define NV0050_CTRL_RESERVED (0x00U) +#define NV0050_CTRL_MEMORY (0x01U) + +#define NV0050_CTRL_CMD_NULL (0x5000U) /* finn: Evaluated from "(FINN_NV_CE_UTILS_RESERVED_INTERFACE_ID << 8) | 0x0" */ + + + +/* + * NV0050_CTRL_CMD_MEMSET + * + * Memsets a memory allocation and releases a semaphore on completion. + * + * hMemory [IN] + * Memory handle of the memory descriptor that needs to be memset. + * This is only available for verification purposes. + * + * offset [IN] + * Offset into the memory descriptor. + * + * length [IN] + * Length of physical memory to be memset. + * Must be less than or equal to memory size. + * + * pattern [IN] + * The pattern to memset to + * + * flags [IN] + * Can be any of the NV0050_CTRL_MEMSET_FLAGS_* + * DEFAULT + * By default, the memcopy operation will be synchronous and using + * physical copies + * ASYNC + * This flag forces this memset to be asynchronous. + * VIRTUAL + * This flag forces the memset to use Virtual addresses which are + * identity mapped. To use this feature, users need to pass in the + * hVaspace with identity mapped addresses for the entire memory during + * construct. + * PIPELINED + * This flag allows the copy/memset operation to be pipelined with previous dma operations on the same channel + * It means that its reads/writes are allowed happen before writes of preceding operations are tlb-acked + * The flag can be useful when dealing with non-inersecting async operations, + * but it can result in races when 2 async CE operations target the same allocation, and the second operation uses the flag + * Race example: + * 1. async copy A -> B + * 2. pipelined copy B -> C + * Here copy 2 can read B before copy finishes writing it, which will result in C containing invalid data + * Technical details: + * By default, first _LAUNCH_DMA method of a CE operation is marked has _TRANSFER_TYPE_NON_PIPELINED, which the flag overrides + * Subsequent _LAUNCH_DMA methods belonging to the same operation use _TRANSFER_TYPE_PIPELINED, as each of these methods should + * target different addresses + * + * submittedWorkId [OUT] + * The work submission token users can poll on to wait for work + * completed by CE. Only valid in case of ASYNC mode. + */ + +#define NV0050_CTRL_MEMSET_FLAGS_DEFAULT 0 +#define NV0050_CTRL_MEMSET_FLAGS_ASYNC NVBIT(0) +#define NV0050_CTRL_MEMSET_FLAGS_VIRTUAL NVBIT(1) +#define NV0050_CTRL_MEMSET_FLAGS_PIPELINED NVBIT(2) + +#define NV0050_CTRL_CMD_MEMSET (0x500101U) /* finn: Evaluated from "(FINN_NV_CE_UTILS_UTILS_INTERFACE_ID << 8) | NV0050_CTRL_MEMSET_PARAMS_MESSAGE_ID" */ + +#define NV0050_CTRL_MEMSET_PARAMS_MESSAGE_ID (0x1U) + +typedef struct NV0050_CTRL_MEMSET_PARAMS { + NvHandle hMemory; + NV_DECLARE_ALIGNED(NvU64 offset, 8); + NV_DECLARE_ALIGNED(NvU64 length, 8); + NvU32 pattern; + NV_DECLARE_ALIGNED(NvU64 flags, 8); + NV_DECLARE_ALIGNED(NvU64 submittedWorkId, 8); +} NV0050_CTRL_MEMSET_PARAMS; + +/* + * NV0050_CTRL_CMD_MEMCOPY + * + * Copies from a source memoryto ssdestination memory and releases a semaphore + * on completion + * + * hDstMemory [IN] + * Memory handle of the memory descriptor to which data will be copied. + * This is only available for verification purposes. + * + * hSrcMemory [IN] + * Memory handle of the memory descriptor from which data will be copied. + * This is only available for verification purposes. + * + * dstOfffset [IN] + * Offset into the destination memory descriptor. + * + * srcOffset [IN] + * Offset into the source memory descriptor. + * + * length [IN] + * Length of physical memory to be copied. + * Must be less than or equal to both destination and source memory size. + * + * flags [IN] + * Can be any of the NV0050_CTRL_MEMCOPY_FLAGS_* + * DEFAULT + * By default, the memcopy operation will be synchronous and using + * physical copies + * ASYNC + * This flag forces this memset to be asynchronous. + * VIRTUAL + * This flag forces the memset to use Virtual addresses which are + * identity mapped. To use this feature, users need to pass in the + * hVaspace with identity mapped addresses for the entire memory during + * construct. + * PIPELINED + * This flag allows the copy/memset operation to be pipelined with previous dma operations on the same channel + * It means that its reads/writes are allowed happen before writes of preceding operations are tlb-acked + * The flag can be useful when dealing with non-inersecting async operations, + * but it can result in races when 2 async CE operations target the same allocation, and the second operation uses the flag + * Race example: + * 1. async copy A -> B + * 2. pipelined copy B -> C + * Here copy 2 can read B before copy finishes writing it, which will result in C containing invalid data + * Technical details: + * By default, first _LAUNCH_DMA method of a CE operation is marked has _TRANSFER_TYPE_NON_PIPELINED, which the flag overrides + * Subsequent _LAUNCH_DMA methods belonging to the same operation use _TRANSFER_TYPE_PIPELINED, as each of these methods should + * target different addresses + * + * submittedWorkId [OUT] + * The work submission token users can poll on to wait for work + * completed by CE. Only valid in case of ASYNC mode. + */ + +#define NV0050_CTRL_MEMCOPY_FLAGS_DEFAULT 0 +#define NV0050_CTRL_MEMCOPY_FLAGS_ASYNC NVBIT(0) +#define NV0050_CTRL_MEMCOPY_FLAGS_VIRTUAL NVBIT(1) +#define NV0050_CTRL_MEMCOPY_FLAGS_PIPELINED NVBIT(2) + +#define NV0050_CTRL_CMD_MEMCOPY (0x500102U) /* finn: Evaluated from "(FINN_NV_CE_UTILS_UTILS_INTERFACE_ID << 8 | NV0050_CTRL_MEMCOPY_PARAMS_MESSAGE_ID)" */ + +#define NV0050_CTRL_MEMCOPY_PARAMS_MESSAGE_ID (0x2U) + +typedef struct NV0050_CTRL_MEMCOPY_PARAMS { + NvHandle hDstMemory; + NvHandle hSrcMemory; + NV_DECLARE_ALIGNED(NvU64 dstOffset, 8); + NV_DECLARE_ALIGNED(NvU64 srcOffset, 8); + NV_DECLARE_ALIGNED(NvU64 length, 8); + NV_DECLARE_ALIGNED(NvU64 flags, 8); + NV_DECLARE_ALIGNED(NvU64 submittedWorkId, 8); +} NV0050_CTRL_MEMCOPY_PARAMS; + +/* + * NV0050_CTRL_CMD_CHECK_PROGRESS + * + * Check if a previously submitted work item has been completed by HW. + * + * submittedWorkId [IN] + * The work submission token users can poll on to wait for work + * completed by CE. + * + */ +#define NV0050_CTRL_CHECK_PROGRESS_RESULT_DEFAULT 0 +#define NV0050_CTRL_CHECK_PROGRESS_RESULT_FINISHED NVBIT(1) + +#define NV0050_CTRL_CMD_CHECK_PROGRESS (0x500103U) /* finn: Evaluated from "(FINN_NV_CE_UTILS_UTILS_INTERFACE_ID << 8 | NV0050_CTRL_CHECK_PROGRESS_PARAMS_MESSAGE_ID)" */ + +#define NV0050_CTRL_CHECK_PROGRESS_PARAMS_MESSAGE_ID (0x3U) + +typedef struct NV0050_CTRL_CHECK_PROGRESS_PARAMS { + NV_DECLARE_ALIGNED(NvU64 submittedWorkId, 8); + NvU32 result; +} NV0050_CTRL_CHECK_PROGRESS_PARAMS; + +/* _ctrl0050_h_ */ diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/common/sdk/nvidia/inc/ctrl/ctrl0073/ctrl0073base.h nvidia-open-gpu-kernel-modules-535.161.08/src/common/sdk/nvidia/inc/ctrl/ctrl0073/ctrl0073base.h --- nvidia-open-gpu-kernel-modules-525.147.05/src/common/sdk/nvidia/inc/ctrl/ctrl0073/ctrl0073base.h 2023-10-25 20:22:07.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/common/sdk/nvidia/inc/ctrl/ctrl0073/ctrl0073base.h 2024-03-05 22:14:59.000000000 +0000 @@ -25,7 +25,7 @@ // // This file was generated with FINN, an NVIDIA coding tool. -// Source file: ctrl/ctrl0073/ctrl0073base.finn +// Source file: ctrl/ctrl0073/ctrl0073base.finn // #include "ctrl/ctrlxxxx.h" @@ -39,6 +39,7 @@ #define NV0073_CTRL_SPECIFIC (0x02U) #define NV0073_CTRL_EVENT (0x03U) #define NV0073_CTRL_INTERNAL (0x04U) +#define NV0073_CTRL_COMMON (0x05U) #define NV0073_CTRL_DFP (0x11U) #define NV0073_CTRL_DP (0x13U) #define NV0073_CTRL_SVP (0x14U) diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/common/sdk/nvidia/inc/ctrl/ctrl0073/ctrl0073common.h nvidia-open-gpu-kernel-modules-535.161.08/src/common/sdk/nvidia/inc/ctrl/ctrl0073/ctrl0073common.h --- nvidia-open-gpu-kernel-modules-525.147.05/src/common/sdk/nvidia/inc/ctrl/ctrl0073/ctrl0073common.h 1970-01-01 00:00:00.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/common/sdk/nvidia/inc/ctrl/ctrl0073/ctrl0073common.h 2024-03-05 22:14:59.000000000 +0000 @@ -0,0 +1,71 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#pragma once + +#include + +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: ctrl/ctrl0073/ctrl0073common.finn +// + + + +/* + * DSC caps - + * bDscSupported + * If GPU supports DSC or not + * + * encoderColorFormatMask + * Mask of all color formats for which DSC + * encoding is supported by GPU + * + * lineBufferSizeKB + * Size of line buffer. + * + * rateBufferSizeKB + * Size of rate buffer per slice. + * + * bitsPerPixelPrecision + * Bits per pixel precision for DSC e.g. 1/16, 1/8, 1/4, 1/2, 1bpp + * + * maxNumHztSlices + * Maximum number of horizontal slices supported by DSC encoder + * + * lineBufferBitDepth + * Bit depth used by the GPU to store the reconstructed pixels within + * the line buffer + */ +#define NV0073_CTRL_CMD_DSC_CAP_PARAMS_MESSAGE_ID (0x1U) + +typedef struct NV0073_CTRL_CMD_DSC_CAP_PARAMS { + NvBool bDscSupported; + NvU32 encoderColorFormatMask; + NvU32 lineBufferSizeKB; + NvU32 rateBufferSizeKB; + NvU32 bitsPerPixelPrecision; + NvU32 maxNumHztSlices; + NvU32 lineBufferBitDepth; +} NV0073_CTRL_CMD_DSC_CAP_PARAMS; +/* _ctrl0073common_h_ */ diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/common/sdk/nvidia/inc/ctrl/ctrl0073/ctrl0073dfp.h nvidia-open-gpu-kernel-modules-535.161.08/src/common/sdk/nvidia/inc/ctrl/ctrl0073/ctrl0073dfp.h --- nvidia-open-gpu-kernel-modules-525.147.05/src/common/sdk/nvidia/inc/ctrl/ctrl0073/ctrl0073dfp.h 2023-10-25 20:22:07.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/common/sdk/nvidia/inc/ctrl/ctrl0073/ctrl0073dfp.h 2024-03-05 22:14:59.000000000 +0000 @@ -27,10 +27,13 @@ // // This file was generated with FINN, an NVIDIA coding tool. -// Source file: ctrl/ctrl0073/ctrl0073dfp.finn +// Source file: ctrl/ctrl0073/ctrl0073dfp.finn // #include "ctrl/ctrl0073/ctrl0073base.h" +#include "ctrl/ctrl0073/ctrl0073common.h" + +#include "nvcfg_sdk.h" /* NV04_DISPLAY_COMMON dfp-display-specific control commands and parameters */ @@ -84,8 +87,7 @@ * This specifies whether the displayId is capable of sending * YCBCR444 color format out from the board. * NV0073_CTRL_DFP_FLAGS_DP_LINK_BANDWIDTH - * This specifies whether the displayId is capable of doing high - * bit-rate (2.7Gbps) or low bit-rate (1.62Gbps) if the DFP is + * This specifies max link rate supported by the displayId, if the DFP is * display port. * NV0073_CTRL_DFP_FLAGS_HDMI_ALLOWED * This specifies whether the DFP displayId is allowed to transmit HDMI @@ -105,6 +107,8 @@ * This indicates whether this SOR uses DSI-A, DSI-B or both (ganged mode). * NV0073_CTRL_DFP_FLAGS_DYNAMIC_MUX_CAPABLE * This indicates whether this DFP supports Dynamic MUX + * flags2 + * This parameter returns the extra information specific to this dfp. * * Possible status values returned are: * NV_OK @@ -119,76 +123,77 @@ NvU32 subDeviceInstance; NvU32 displayId; NvU32 flags; + NvU32 flags2; } NV0073_CTRL_DFP_GET_INFO_PARAMS; /* valid display types */ #define NV0073_CTRL_DFP_FLAGS_SIGNAL 2:0 -#define NV0073_CTRL_DFP_FLAGS_SIGNAL_TMDS (0x00000000U) -#define NV0073_CTRL_DFP_FLAGS_SIGNAL_LVDS (0x00000001U) -#define NV0073_CTRL_DFP_FLAGS_SIGNAL_SDI (0x00000002U) -#define NV0073_CTRL_DFP_FLAGS_SIGNAL_DISPLAYPORT (0x00000003U) -#define NV0073_CTRL_DFP_FLAGS_SIGNAL_DSI (0x00000004U) -#define NV0073_CTRL_DFP_FLAGS_SIGNAL_WRBK (0x00000005U) +#define NV0073_CTRL_DFP_FLAGS_SIGNAL_TMDS (0x00000000U) +#define NV0073_CTRL_DFP_FLAGS_SIGNAL_LVDS (0x00000001U) +#define NV0073_CTRL_DFP_FLAGS_SIGNAL_SDI (0x00000002U) +#define NV0073_CTRL_DFP_FLAGS_SIGNAL_DISPLAYPORT (0x00000003U) +#define NV0073_CTRL_DFP_FLAGS_SIGNAL_DSI (0x00000004U) +#define NV0073_CTRL_DFP_FLAGS_SIGNAL_WRBK (0x00000005U) #define NV0073_CTRL_DFP_FLAGS_LANE 5:3 -#define NV0073_CTRL_DFP_FLAGS_LANE_NONE (0x00000000U) -#define NV0073_CTRL_DFP_FLAGS_LANE_SINGLE (0x00000001U) -#define NV0073_CTRL_DFP_FLAGS_LANE_DUAL (0x00000002U) -#define NV0073_CTRL_DFP_FLAGS_LANE_QUAD (0x00000003U) -#define NV0073_CTRL_DFP_FLAGS_LANE_OCT (0x00000004U) +#define NV0073_CTRL_DFP_FLAGS_LANE_NONE (0x00000000U) +#define NV0073_CTRL_DFP_FLAGS_LANE_SINGLE (0x00000001U) +#define NV0073_CTRL_DFP_FLAGS_LANE_DUAL (0x00000002U) +#define NV0073_CTRL_DFP_FLAGS_LANE_QUAD (0x00000003U) +#define NV0073_CTRL_DFP_FLAGS_LANE_OCT (0x00000004U) #define NV0073_CTRL_DFP_FLAGS_LIMIT 6:6 -#define NV0073_CTRL_DFP_FLAGS_LIMIT_DISABLE (0x00000000U) -#define NV0073_CTRL_DFP_FLAGS_LIMIT_60HZ_RR (0x00000001U) +#define NV0073_CTRL_DFP_FLAGS_LIMIT_DISABLE (0x00000000U) +#define NV0073_CTRL_DFP_FLAGS_LIMIT_60HZ_RR (0x00000001U) #define NV0073_CTRL_DFP_FLAGS_SLI_SCALER 7:7 -#define NV0073_CTRL_DFP_FLAGS_SLI_SCALER_NORMAL (0x00000000U) -#define NV0073_CTRL_DFP_FLAGS_SLI_SCALER_DISABLE (0x00000001U) +#define NV0073_CTRL_DFP_FLAGS_SLI_SCALER_NORMAL (0x00000000U) +#define NV0073_CTRL_DFP_FLAGS_SLI_SCALER_DISABLE (0x00000001U) #define NV0073_CTRL_DFP_FLAGS_HDMI_CAPABLE 8:8 -#define NV0073_CTRL_DFP_FLAGS_HDMI_CAPABLE_FALSE (0x00000000U) -#define NV0073_CTRL_DFP_FLAGS_HDMI_CAPABLE_TRUE (0x00000001U) +#define NV0073_CTRL_DFP_FLAGS_HDMI_CAPABLE_FALSE (0x00000000U) +#define NV0073_CTRL_DFP_FLAGS_HDMI_CAPABLE_TRUE (0x00000001U) #define NV0073_CTRL_DFP_FLAGS_RANGE_LIMITED_CAPABLE 9:9 -#define NV0073_CTRL_DFP_FLAGS_RANGE_LIMITED_CAPABLE_FALSE (0x00000000U) -#define NV0073_CTRL_DFP_FLAGS_RANGE_LIMITED_CAPABLE_TRUE (0x00000001U) +#define NV0073_CTRL_DFP_FLAGS_RANGE_LIMITED_CAPABLE_FALSE (0x00000000U) +#define NV0073_CTRL_DFP_FLAGS_RANGE_LIMITED_CAPABLE_TRUE (0x00000001U) #define NV0073_CTRL_DFP_FLAGS_RANGE_AUTO_CAPABLE 10:10 -#define NV0073_CTRL_DFP_FLAGS_RANGE_AUTO_CAPABLE_FALSE (0x00000000U) -#define NV0073_CTRL_DFP_FLAGS_RANGE_AUTO_CAPABLE_TRUE (0x00000001U) +#define NV0073_CTRL_DFP_FLAGS_RANGE_AUTO_CAPABLE_FALSE (0x00000000U) +#define NV0073_CTRL_DFP_FLAGS_RANGE_AUTO_CAPABLE_TRUE (0x00000001U) #define NV0073_CTRL_DFP_FLAGS_FORMAT_YCBCR422_CAPABLE 11:11 -#define NV0073_CTRL_DFP_FLAGS_FORMAT_YCBCR422_CAPABLE_FALSE (0x00000000U) -#define NV0073_CTRL_DFP_FLAGS_FORMAT_YCBCR422_CAPABLE_TRUE (0x00000001U) +#define NV0073_CTRL_DFP_FLAGS_FORMAT_YCBCR422_CAPABLE_FALSE (0x00000000U) +#define NV0073_CTRL_DFP_FLAGS_FORMAT_YCBCR422_CAPABLE_TRUE (0x00000001U) #define NV0073_CTRL_DFP_FLAGS_FORMAT_YCBCR444_CAPABLE 12:12 -#define NV0073_CTRL_DFP_FLAGS_FORMAT_YCBCR444_CAPABLE_FALSE (0x00000000U) -#define NV0073_CTRL_DFP_FLAGS_FORMAT_YCBCR444_CAPABLE_TRUE (0x00000001U) +#define NV0073_CTRL_DFP_FLAGS_FORMAT_YCBCR444_CAPABLE_FALSE (0x00000000U) +#define NV0073_CTRL_DFP_FLAGS_FORMAT_YCBCR444_CAPABLE_TRUE (0x00000001U) #define NV0073_CTRL_DFP_FLAGS_HDMI_ALLOWED 14:14 -#define NV0073_CTRL_DFP_FLAGS_HDMI_ALLOWED_FALSE (0x00000000U) -#define NV0073_CTRL_DFP_FLAGS_HDMI_ALLOWED_TRUE (0x00000001U) +#define NV0073_CTRL_DFP_FLAGS_HDMI_ALLOWED_FALSE (0x00000000U) +#define NV0073_CTRL_DFP_FLAGS_HDMI_ALLOWED_TRUE (0x00000001U) #define NV0073_CTRL_DFP_FLAGS_EMBEDDED_DISPLAYPORT 15:15 -#define NV0073_CTRL_DFP_FLAGS_EMBEDDED_DISPLAYPORT_FALSE (0x00000000U) -#define NV0073_CTRL_DFP_FLAGS_EMBEDDED_DISPLAYPORT_TRUE (0x00000001U) +#define NV0073_CTRL_DFP_FLAGS_EMBEDDED_DISPLAYPORT_FALSE (0x00000000U) +#define NV0073_CTRL_DFP_FLAGS_EMBEDDED_DISPLAYPORT_TRUE (0x00000001U) #define NV0073_CTRL_DFP_FLAGS_DP_LINK_CONSTRAINT 16:16 -#define NV0073_CTRL_DFP_FLAGS_DP_LINK_CONSTRAINT_NONE (0x00000000U) -#define NV0073_CTRL_DFP_FLAGS_DP_LINK_CONSTRAINT_PREFER_RBR (0x00000001U) +#define NV0073_CTRL_DFP_FLAGS_DP_LINK_CONSTRAINT_NONE (0x00000000U) +#define NV0073_CTRL_DFP_FLAGS_DP_LINK_CONSTRAINT_PREFER_RBR (0x00000001U) #define NV0073_CTRL_DFP_FLAGS_DP_LINK_BW 19:17 -#define NV0073_CTRL_DFP_FLAGS_DP_LINK_BW_1_62GBPS (0x00000001U) -#define NV0073_CTRL_DFP_FLAGS_DP_LINK_BW_2_70GBPS (0x00000002U) -#define NV0073_CTRL_DFP_FLAGS_DP_LINK_BW_5_40GBPS (0x00000003U) -#define NV0073_CTRL_DFP_FLAGS_DP_LINK_BW_8_10GBPS (0x00000004U) +#define NV0073_CTRL_DFP_FLAGS_DP_LINK_BW_1_62GBPS (0x00000001U) +#define NV0073_CTRL_DFP_FLAGS_DP_LINK_BW_2_70GBPS (0x00000002U) +#define NV0073_CTRL_DFP_FLAGS_DP_LINK_BW_5_40GBPS (0x00000003U) +#define NV0073_CTRL_DFP_FLAGS_DP_LINK_BW_8_10GBPS (0x00000004U) #define NV0073_CTRL_DFP_FLAGS_LINK 21:20 -#define NV0073_CTRL_DFP_FLAGS_LINK_NONE (0x00000000U) -#define NV0073_CTRL_DFP_FLAGS_LINK_SINGLE (0x00000001U) -#define NV0073_CTRL_DFP_FLAGS_LINK_DUAL (0x00000002U) +#define NV0073_CTRL_DFP_FLAGS_LINK_NONE (0x00000000U) +#define NV0073_CTRL_DFP_FLAGS_LINK_SINGLE (0x00000001U) +#define NV0073_CTRL_DFP_FLAGS_LINK_DUAL (0x00000002U) #define NV0073_CTRL_DFP_FLAGS_DP_FORCE_RM_EDID 22:22 -#define NV0073_CTRL_DFP_FLAGS_DP_FORCE_RM_EDID_FALSE (0x00000000U) -#define NV0073_CTRL_DFP_FLAGS_DP_FORCE_RM_EDID_TRUE (0x00000001U) +#define NV0073_CTRL_DFP_FLAGS_DP_FORCE_RM_EDID_FALSE (0x00000000U) +#define NV0073_CTRL_DFP_FLAGS_DP_FORCE_RM_EDID_TRUE (0x00000001U) #define NV0073_CTRL_DFP_FLAGS_DSI_DEVICE_ID 24:23 -#define NV0073_CTRL_DFP_FLAGS_DSI_DEVICE_ID_DSI_NONE (0x00000000U) -#define NV0073_CTRL_DFP_FLAGS_DSI_DEVICE_ID_DSI_A (0x00000001U) -#define NV0073_CTRL_DFP_FLAGS_DSI_DEVICE_ID_DSI_B (0x00000002U) -#define NV0073_CTRL_DFP_FLAGS_DSI_DEVICE_ID_DSI_GANGED (0x00000003U) +#define NV0073_CTRL_DFP_FLAGS_DSI_DEVICE_ID_DSI_NONE (0x00000000U) +#define NV0073_CTRL_DFP_FLAGS_DSI_DEVICE_ID_DSI_A (0x00000001U) +#define NV0073_CTRL_DFP_FLAGS_DSI_DEVICE_ID_DSI_B (0x00000002U) +#define NV0073_CTRL_DFP_FLAGS_DSI_DEVICE_ID_DSI_GANGED (0x00000003U) #define NV0073_CTRL_DFP_FLAGS_DP_POST_CURSOR2_DISABLED 25:25 -#define NV0073_CTRL_DFP_FLAGS_DP_POST_CURSOR2_DISABLED_FALSE (0x00000000U) -#define NV0073_CTRL_DFP_FLAGS_DP_POST_CURSOR2_DISABLED_TRUE (0x00000001U) +#define NV0073_CTRL_DFP_FLAGS_DP_POST_CURSOR2_DISABLED_FALSE (0x00000000U) +#define NV0073_CTRL_DFP_FLAGS_DP_POST_CURSOR2_DISABLED_TRUE (0x00000001U) #define NV0073_CTRL_DFP_FLAGS_DP_PHY_REPEATER_COUNT 29:26 #define NV0073_CTRL_DFP_FLAGS_DYNAMIC_MUX_CAPABLE 30:30 -#define NV0073_CTRL_DFP_FLAGS_DYNAMIC_MUX_CAPABLE_FALSE (0x00000000U) -#define NV0073_CTRL_DFP_FLAGS_DYNAMIC_MUX_CAPABLE_TRUE (0x00000001U) +#define NV0073_CTRL_DFP_FLAGS_DYNAMIC_MUX_CAPABLE_FALSE (0x00000000U) +#define NV0073_CTRL_DFP_FLAGS_DYNAMIC_MUX_CAPABLE_TRUE (0x00000001U) @@ -465,7 +470,7 @@ /* * NV0073_CTRL_DFP_ASSIGN_SOR_LINKCONFIG * - * This enum defines default/primary/secondary sor sublinks to be configured. + * This variable specifies default/primary/secondary sor sublinks to be configured. * These access modes are: * * NV0073_CTRL_DFP_ASSIGN_SOR_FORCE_NONE @@ -475,11 +480,11 @@ * NV0073_CTRL_DFP_ASSIGN_SOR_FORCE_SECONDARY_SOR_LINK * Secondary sor sublink to be configured */ -typedef enum NV0073_CTRL_DFP_ASSIGN_SOR_LINKCONFIG { - NV0073_CTRL_DFP_ASSIGN_SOR_FORCE_NONE = 0, - NV0073_CTRL_DFP_ASSIGN_SOR_FORCE_PRIMARY_SOR_LINK = 1, - NV0073_CTRL_DFP_ASSIGN_SOR_FORCE_SECONDARY_SOR_LINK = 2, -} NV0073_CTRL_DFP_ASSIGN_SOR_LINKCONFIG; +typedef NvU32 NV0073_CTRL_DFP_ASSIGN_SOR_LINKCONFIG; + +#define NV0073_CTRL_DFP_ASSIGN_SOR_FORCE_NONE (0x0U) +#define NV0073_CTRL_DFP_ASSIGN_SOR_FORCE_PRIMARY_SOR_LINK (0x1U) +#define NV0073_CTRL_DFP_ASSIGN_SOR_FORCE_SECONDARY_SOR_LINK (0x2U) /* * NV0073_CTRL_DFP_ASSIGN_SOR_INFO @@ -569,7 +574,7 @@ * _ACTIVE_SOR_NOT_AUDIO_CAPABLE_YES : RM returns Active SOR which is not Audio capable. * _ACTIVE_SOR_NOT_AUDIO_CAPABLE_NO : RM is not returning 'Active non-audio capable SOR'. * - * Possible status values returned are: + * Possible status values returned are: * NV_OK * NV_ERR_INVALID_ARGUMENT * NV_ERR_NOT_SUPPORTED @@ -1157,40 +1162,31 @@ #define NV0073_CTRL_CMD_DFP_GET_DSI_MODE_TIMING_PARAMS_MESSAGE_ID (0x66U) typedef struct NV0073_CTRL_CMD_DFP_GET_DSI_MODE_TIMING_PARAMS { - NvU32 subDeviceInstance; - NvU32 displayId; - NvU32 hActive; - NvU32 vActive; - NvU32 hFrontPorch; - NvU32 vFrontPorch; - NvU32 hBackPorch; - NvU32 vBackPorch; - NvU32 hSyncWidth; - NvU32 vSyncWidth; - NvU32 bpp; - NvU32 refresh; - NvU32 pclkHz; - NvU32 numLanes; - NvU32 dscEnable; - NvU32 dscBpp; - NvU32 dscNumSlices; - NvU32 dscDualDsc; - NvU32 dscSliceHeight; - NvU32 dscBlockPrediction; - NvU32 dscDecoderVersionMajor; - NvU32 dscDecoderVersionMinor; - NvBool dscUseCustomPPS; - NvU32 dscCustomPPSData[NV0073_CTRL_CMD_DFP_DSI_CUSTOM_PPS_DATA_COUNT]; - - struct { - NvBool bDscSupported; - NvU32 encoderColorFormatMask; - NvU32 lineBufferSizeKB; - NvU32 rateBufferSizeKB; - NvU32 bitsPerPixelPrecision; - NvU32 maxNumHztSlices; - NvU32 lineBufferBitDepth; - } dscEncoderCaps; + NvU32 subDeviceInstance; + NvU32 displayId; + NvU32 hActive; + NvU32 vActive; + NvU32 hFrontPorch; + NvU32 vFrontPorch; + NvU32 hBackPorch; + NvU32 vBackPorch; + NvU32 hSyncWidth; + NvU32 vSyncWidth; + NvU32 bpp; + NvU32 refresh; + NvU32 pclkHz; + NvU32 numLanes; + NvU32 dscEnable; + NvU32 dscBpp; + NvU32 dscNumSlices; + NvU32 dscDualDsc; + NvU32 dscSliceHeight; + NvU32 dscBlockPrediction; + NvU32 dscDecoderVersionMajor; + NvU32 dscDecoderVersionMinor; + NvBool dscUseCustomPPS; + NvU32 dscCustomPPSData[NV0073_CTRL_CMD_DFP_DSI_CUSTOM_PPS_DATA_COUNT]; + NV0073_CTRL_CMD_DSC_CAP_PARAMS dscEncoderCaps; } NV0073_CTRL_CMD_DFP_GET_DSI_MODE_TIMING_PARAMS; diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/common/sdk/nvidia/inc/ctrl/ctrl0073/ctrl0073dp.h nvidia-open-gpu-kernel-modules-535.161.08/src/common/sdk/nvidia/inc/ctrl/ctrl0073/ctrl0073dp.h --- nvidia-open-gpu-kernel-modules-525.147.05/src/common/sdk/nvidia/inc/ctrl/ctrl0073/ctrl0073dp.h 2023-10-25 20:22:07.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/common/sdk/nvidia/inc/ctrl/ctrl0073/ctrl0073dp.h 2024-03-05 22:15:00.000000000 +0000 @@ -27,10 +27,13 @@ // // This file was generated with FINN, an NVIDIA coding tool. -// Source file: ctrl/ctrl0073/ctrl0073dp.finn +// Source file: ctrl/ctrl0073/ctrl0073dp.finn // #include "ctrl/ctrl0073/ctrl0073base.h" +#include "ctrl/ctrl0073/ctrl0073common.h" + +#include "nvcfg_sdk.h" /* NV04_DISPLAY_COMMON dfp-display-specific control commands and parameters */ @@ -728,7 +731,11 @@ * */ -#define NV0073_CTRL_CMD_DP_GET_LANE_DATA (0x731345U) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_DP_INTERFACE_ID << 8) | 0x45" */ +#define NV0073_CTRL_CMD_DP_GET_LANE_DATA (0x731345U) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_DP_INTERFACE_ID << 8) | NV0073_CTRL_DP_GET_LANE_DATA_PARAMS_MESSAGE_ID" */ + +#define NV0073_CTRL_DP_GET_LANE_DATA_PARAMS_MESSAGE_ID (0x45U) + +typedef NV0073_CTRL_DP_LANE_DATA_PARAMS NV0073_CTRL_DP_GET_LANE_DATA_PARAMS; /* @@ -755,7 +762,11 @@ * */ -#define NV0073_CTRL_CMD_DP_SET_LANE_DATA (0x731346U) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_DP_INTERFACE_ID << 8) | 0x46" */ +#define NV0073_CTRL_CMD_DP_SET_LANE_DATA (0x731346U) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_DP_INTERFACE_ID << 8) | NV0073_CTRL_DP_SET_LANE_DATA_PARAMS_MESSAGE_ID" */ + +#define NV0073_CTRL_DP_SET_LANE_DATA_PARAMS_MESSAGE_ID (0x46U) + +typedef NV0073_CTRL_DP_LANE_DATA_PARAMS NV0073_CTRL_DP_SET_LANE_DATA_PARAMS; /* * NV0073_CTRL_DP_CSTM @@ -1758,29 +1769,7 @@ * bOverrideLinkBw * Returns NV_TRUE if DFP limits defined in DCB have to be honored, else NV_FALSE * - * DSC caps - - * bDscSupported - * If GPU supports DSC or not - * - * encoderColorFormatMask - * Mask of all color formats for which DSC - * encoding is supported by GPU - * - * lineBufferSizeKB - * Size of line buffer. - * - * rateBufferSizeKB - * Size of rate buffer per slice. - * - * bitsPerPixelPrecision - * Bits per pixel precision for DSC e.g. 1/16, 1/8, 1/4, 1/2, 1bpp - * - * maxNumHztSlices - * Maximum number of horizontal slices supported by DSC encoder - * - * lineBufferBitDepth - * Bit depth used by the GPU to store the reconstructed pixels within - * the line buffer + * DSC caps * * Possible status values returned are: * NV_OK @@ -1794,28 +1783,20 @@ #define NV0073_CTRL_CMD_DP_GET_CAPS_PARAMS_MESSAGE_ID (0x69U) typedef struct NV0073_CTRL_CMD_DP_GET_CAPS_PARAMS { - NvU32 subDeviceInstance; - NvU32 sorIndex; - NvU32 maxLinkRate; - NvU32 dpVersionsSupported; - NvBool bIsMultistreamSupported; - NvBool bIsSCEnabled; - NvBool bHasIncreasedWatermarkLimits; - NvBool bIsPC2Disabled; - NvBool isSingleHeadMSTSupported; - NvBool bFECSupported; - NvBool bIsTrainPhyRepeater; - NvBool bOverrideLinkBw; - - struct { - NvBool bDscSupported; - NvU32 encoderColorFormatMask; - NvU32 lineBufferSizeKB; - NvU32 rateBufferSizeKB; - NvU32 bitsPerPixelPrecision; - NvU32 maxNumHztSlices; - NvU32 lineBufferBitDepth; - } DSC; + NvU32 subDeviceInstance; + NvU32 sorIndex; + NvU32 maxLinkRate; + NvU32 dpVersionsSupported; + NvU32 UHBRSupported; + NvBool bIsMultistreamSupported; + NvBool bIsSCEnabled; + NvBool bHasIncreasedWatermarkLimits; + NvBool bIsPC2Disabled; + NvBool isSingleHeadMSTSupported; + NvBool bFECSupported; + NvBool bIsTrainPhyRepeater; + NvBool bOverrideLinkBw; + NV0073_CTRL_CMD_DSC_CAP_PARAMS DSC; } NV0073_CTRL_CMD_DP_GET_CAPS_PARAMS; #define NV0073_CTRL_CMD_DP_GET_CAPS_DP_VERSIONS_SUPPORTED_DP1_2 0:0 @@ -1826,7 +1807,6 @@ #define NV0073_CTRL_CMD_DP_GET_CAPS_DP_VERSIONS_SUPPORTED_DP1_4_YES (0x00000001U) - #define NV0073_CTRL_CMD_DP_GET_CAPS_MAX_LINK_RATE 2:0 #define NV0073_CTRL_CMD_DP_GET_CAPS_MAX_LINK_RATE_NONE (0x00000000U) #define NV0073_CTRL_CMD_DP_GET_CAPS_MAX_LINK_RATE_1_62 (0x00000001U) @@ -1834,6 +1814,7 @@ #define NV0073_CTRL_CMD_DP_GET_CAPS_MAX_LINK_RATE_5_40 (0x00000003U) #define NV0073_CTRL_CMD_DP_GET_CAPS_MAX_LINK_RATE_8_10 (0x00000004U) + #define NV0073_CTRL_CMD_DP_GET_CAPS_DSC_ENCODER_COLOR_FORMAT_RGB (0x00000001U) #define NV0073_CTRL_CMD_DP_GET_CAPS_DSC_ENCODER_COLOR_FORMAT_Y_CB_CR_444 (0x00000002U) #define NV0073_CTRL_CMD_DP_GET_CAPS_DSC_ENCODER_COLOR_FORMAT_Y_CB_CR_NATIVE_422 (0x00000004U) @@ -2764,4 +2745,45 @@ NvBool bDebugValues; NV0073_CTRL_DP_MSA_PROPERTIES_VALUES featureDebugValues; } NV0073_CTRL_CMD_DP_SET_MSA_PROPERTIES_V2_PARAMS; + +/* + * NV0073_CTRL_CMD_DP_EXECUTE_OVERDRIVE_POLICY + * + * This command is used to execute RM Over Drive policy and decide if TCON Overdrive needs to be enabled + * or not based on the panel Overdrive grade determined using the panel manufId and prodId. + * + * subDeviceInstance [in] + * This parameter specifies the subdevice instance within the + * NV04_DISPLAY_COMMON parent device to which the operation should be + * directed. This parameter must specify a value between zero and the + * total number of subdevices within the parent device. This parameter + * should be set to zero for default behavior. + * displayId [in] + * This parameter specifies the ID of the eDP display which owns + * the Main Link to be adjusted. The display ID must a eDP display + * as determined with the NV0073_CTRL_CMD_SPECIFIC_GET_TYPE command. + * If more than one displayId bit is set or the displayId is not an eDP, + * this call will return NV_ERR_INVALID_ARGUMENT. + * manfId [in] + * This parameter is an input to this command which tells the + * Internal panel's manufacturer ID. + * prodId [in] + * This parameter is an input to this command which tells the + * Internal panel's product ID. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_ARGUMENT + * NV_ERR_NOT_SUPPORTED + */ +#define NV0073_CTRL_CMD_DP_EXECUTE_OVERDRIVE_POLICY (0x731382U) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_DP_INTERFACE_ID << 8) | NV0073_CTRL_DP_EXECUTE_OVERDRIVE_POLICY_PARAMS_MESSAGE_ID" */ + +#define NV0073_CTRL_DP_EXECUTE_OVERDRIVE_POLICY_PARAMS_MESSAGE_ID (0x82U) + +typedef struct NV0073_CTRL_DP_EXECUTE_OVERDRIVE_POLICY_PARAMS { + NvU32 subDeviceInstance; + NvU32 displayId; + NvU16 manfId; + NvU16 prodId; +} NV0073_CTRL_DP_EXECUTE_OVERDRIVE_POLICY_PARAMS; /* _ctrl0073dp_h_ */ diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/common/sdk/nvidia/inc/ctrl/ctrl0073/ctrl0073dpu.h nvidia-open-gpu-kernel-modules-535.161.08/src/common/sdk/nvidia/inc/ctrl/ctrl0073/ctrl0073dpu.h --- nvidia-open-gpu-kernel-modules-525.147.05/src/common/sdk/nvidia/inc/ctrl/ctrl0073/ctrl0073dpu.h 2023-10-25 20:22:07.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/common/sdk/nvidia/inc/ctrl/ctrl0073/ctrl0073dpu.h 2024-03-05 22:15:00.000000000 +0000 @@ -27,6 +27,6 @@ // // This file was generated with FINN, an NVIDIA coding tool. -// Source file: ctrl/ctrl0073/ctrl0073dpu.finn +// Source file: ctrl/ctrl0073/ctrl0073dpu.finn // diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/common/sdk/nvidia/inc/ctrl/ctrl0073/ctrl0073event.h nvidia-open-gpu-kernel-modules-535.161.08/src/common/sdk/nvidia/inc/ctrl/ctrl0073/ctrl0073event.h --- nvidia-open-gpu-kernel-modules-525.147.05/src/common/sdk/nvidia/inc/ctrl/ctrl0073/ctrl0073event.h 2023-10-25 20:22:08.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/common/sdk/nvidia/inc/ctrl/ctrl0073/ctrl0073event.h 2024-03-05 22:15:00.000000000 +0000 @@ -27,6 +27,104 @@ // // This file was generated with FINN, an NVIDIA coding tool. -// Source file: ctrl/ctrl0073/ctrl0073event.finn +// Source file: ctrl/ctrl0073/ctrl0073event.finn // +#include "ctrl/ctrl0073/ctrl0073base.h" + +/* NV04_DISPLAY_COMMON event-related control commands and parameters */ + +/* + * NV0073_CTRL_CMD_EVENT_SET_NOTIFICATION + * + * This command sets event notification state for the associated display + * object. This command requires that an instance of NV01_EVENT has been + * previously bound to the associated display object. + * + * subDeviceInstance + * This parameter specifies the subdevice instance within the + * NV04_DISPLAY_COMMON parent device to which the operation should be + * directed. This parameter must specify a value between zero and the + * total number of subdevices within the parent device. This parameter + * should be set to zero for default behavior. + * hEvent + * This parameter specifies the handle of the NV01_EVENT instance + * to be bound to the given subDeviceInstance. + * event + * This parameter specifies the type of event to which the specified + * action is to be applied. This parameter must specify a valid + * NV0073_NOTIFIERS value (see cl0073.h for more details) and should + * not exceed one less NV0073_NOTIFIERS_MAXCOUNT. + * action + * This parameter specifies the desired event notification action. + * Valid notification actions include: + * NV0073_CTRL_SET_EVENT_NOTIFICATION_DISABLE + * This action disables event notification for the specified + * event for the associated subdevice object. + * NV0073_CTRL_SET_EVENT_NOTIFICATION_SINGLE + * This action enables single-shot event notification for the + * specified event for the associated subdevice object. + * NV0073_CTRL_SET_EVENT_NOTIFICATION_REPEAT + * This action enables repeated event notification for the specified + * event for the associated system controller object. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_PARAM_STRUCT + * NV_ERR_INVALID_ARGUMENT + * NV_ERR_INVALID_STATE + */ +#define NV0073_CTRL_CMD_EVENT_SET_NOTIFICATION (0x730301U) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_EVENT_INTERFACE_ID << 8) | NV0073_CTRL_EVENT_SET_NOTIFICATION_PARAMS_MESSAGE_ID" */ + +#define NV0073_CTRL_EVENT_SET_NOTIFICATION_PARAMS_MESSAGE_ID (0x1U) + +typedef struct NV0073_CTRL_EVENT_SET_NOTIFICATION_PARAMS { + NvU32 subDeviceInstance; + NvHandle hEvent; + NvU32 event; + NvU32 action; +} NV0073_CTRL_EVENT_SET_NOTIFICATION_PARAMS; + +/* valid action values */ +#define NV0073_CTRL_EVENT_SET_NOTIFICATION_ACTION_DISABLE (0x00000000U) +#define NV0073_CTRL_EVENT_SET_NOTIFICATION_ACTION_SINGLE (0x00000001U) +#define NV0073_CTRL_EVENT_SET_NOTIFICATION_ACTION_REPEAT (0x00000002U) + +/* + * NV0073_CTRL_CMD_EVENT_SET_NOTIFIER_MEMORY + * + * hMemory + * This parameter specifies the handle of the memory object + * that identifies the memory address translation for this + * subdevice instance's notification(s). The beginning of the + * translation points to an array of notification data structures. + * The size of the translation must be at least large enough to hold the + * maximum number of notification data structures identified by + * the NV0073_MAX_NOTIFIERS value. + * Legal argument values must be instances of the following classes: + * NV01_NULL + * NV04_MEMORY + * When hMemory specifies the NV01_NULL_OBJECT value then any existing + * memory translation connection is cleared. There must not be any + * pending notifications when this command is issued. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_PARAM_STRUCT + * NV_ERR_INVALID_ARGUMENT + * NV_ERR_INVALID_STATE + */ +#define NV0073_CTRL_CMD_EVENT_SET_MEMORY_NOTIFIES (0x730303U) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_EVENT_INTERFACE_ID << 8) | NV0073_CTRL_EVENT_SET_MEMORY_NOTIFIES_PARAMS_MESSAGE_ID" */ + +#define NV0073_CTRL_EVENT_SET_MEMORY_NOTIFIES_PARAMS_MESSAGE_ID (0x3U) + +typedef struct NV0073_CTRL_EVENT_SET_MEMORY_NOTIFIES_PARAMS { + NvU32 subDeviceInstance; + NvHandle hMemory; +} NV0073_CTRL_EVENT_SET_MEMORY_NOTIFIES_PARAMS; + +#define NV0073_EVENT_MEMORY_NOTIFIES_STATUS_NOTIFIED 0U +#define NV0073_EVENT_MEMORY_NOTIFIES_STATUS_PENDING 1U +#define NV0073_EVENT_MEMORY_NOTIFIES_STATUS_ERROR 2U + +/* _ctrl0073event_h_ */ diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/common/sdk/nvidia/inc/ctrl/ctrl0073/ctrl0073internal.h nvidia-open-gpu-kernel-modules-535.161.08/src/common/sdk/nvidia/inc/ctrl/ctrl0073/ctrl0073internal.h --- nvidia-open-gpu-kernel-modules-525.147.05/src/common/sdk/nvidia/inc/ctrl/ctrl0073/ctrl0073internal.h 2023-10-25 20:22:08.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/common/sdk/nvidia/inc/ctrl/ctrl0073/ctrl0073internal.h 2024-03-05 22:15:00.000000000 +0000 @@ -25,23 +25,22 @@ // // This file was generated with FINN, an NVIDIA coding tool. -// Source file: ctrl/ctrl0073/ctrl0073internal.finn +// Source file: ctrl/ctrl0073/ctrl0073internal.finn // #include "ctrl/ctrl0073/ctrl0073base.h" #include "ctrl/ctrl0073/ctrl0073system.h" -#define NV0073_CTRL_CMD_INTERNAL_GET_HOTPLUG_UNPLUG_STATE (0x730401U) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_INTERNAL_INTERFACE_ID << 8) | NV0073_CTRL_CMD_INTERNAL_GET_HOTPLUG_UNPLUG_STATE_FINN_PARAMS_MESSAGE_ID" */ +#define NV0073_CTRL_CMD_INTERNAL_GET_HOTPLUG_UNPLUG_STATE (0x730401U) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_INTERNAL_INTERFACE_ID << 8) | NV0073_CTRL_INTERNAL_GET_HOTPLUG_UNPLUG_STATE_PARAMS_MESSAGE_ID" */ +#define NV0073_CTRL_INTERNAL_GET_HOTPLUG_UNPLUG_STATE_PARAMS_MESSAGE_ID (0x1U) -// FINN PORT: The below type was generated by the FINN port to -// ensure that all API's have a unique structure associated -// with them! -#define NV0073_CTRL_CMD_INTERNAL_GET_HOTPLUG_UNPLUG_STATE_FINN_PARAMS_MESSAGE_ID (0x1U) +typedef NV0073_CTRL_SYSTEM_GET_HOTPLUG_UNPLUG_STATE_PARAMS NV0073_CTRL_INTERNAL_GET_HOTPLUG_UNPLUG_STATE_PARAMS; -typedef struct NV0073_CTRL_CMD_INTERNAL_GET_HOTPLUG_UNPLUG_STATE_FINN_PARAMS { - NV0073_CTRL_SYSTEM_GET_HOTPLUG_UNPLUG_STATE_PARAMS params; -} NV0073_CTRL_CMD_INTERNAL_GET_HOTPLUG_UNPLUG_STATE_FINN_PARAMS; +#define NV0073_CTRL_CMD_INTERNAL_VRR_SET_RGLINE_ACTIVE (0x730402U) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_INTERNAL_INTERFACE_ID << 8) | NV0073_CTRL_CMD_INTERNAL_VRR_SET_RGLINE_ACTIVE_PARAMS_MESSAGE_ID" */ +#define NV0073_CTRL_CMD_INTERNAL_VRR_SET_RGLINE_ACTIVE_PARAMS_MESSAGE_ID (0x2U) + +typedef NV0073_CTRL_CMD_SYSTEM_VRR_SET_RGLINE_ACTIVE_PARAMS NV0073_CTRL_CMD_INTERNAL_VRR_SET_RGLINE_ACTIVE_PARAMS; /* ctrl0073internal_h */ diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/common/sdk/nvidia/inc/ctrl/ctrl0073/ctrl0073psr.h nvidia-open-gpu-kernel-modules-535.161.08/src/common/sdk/nvidia/inc/ctrl/ctrl0073/ctrl0073psr.h --- nvidia-open-gpu-kernel-modules-525.147.05/src/common/sdk/nvidia/inc/ctrl/ctrl0073/ctrl0073psr.h 2023-10-25 20:22:08.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/common/sdk/nvidia/inc/ctrl/ctrl0073/ctrl0073psr.h 2024-03-05 22:15:00.000000000 +0000 @@ -27,6 +27,44 @@ // // This file was generated with FINN, an NVIDIA coding tool. -// Source file: ctrl/ctrl0073/ctrl0073psr.finn +// Source file: ctrl/ctrl0073/ctrl0073psr.finn // +#include "ctrl/ctrl0073/ctrl0073base.h" + + + +/* + * NV0073_CTRL_CMD_PSR_GET_SR_PANEL_INFO + * + * displayId + * Display ID on which this information is being requested. + * frameLockPin + * Returns the frame lock pin of the panel. + * i2cAddress + * Returns the i2c address on which the SR panel is attached. + * NOTE: applies only to LVDS panels, otherwise this field + * should be ignored. + * bSelfRefreshEnabled + * Returns whether SR is enabled in RM. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_ARGUMENT + * NV_ERR_NOT_SUPPORTED + */ + +#define NV0073_CTRL_CMD_PSR_GET_SR_PANEL_INFO (0x731602U) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_PSR_INTERFACE_ID << 8) | NV0073_CTRL_PSR_GET_SR_PANEL_INFO_PARAMS_MESSAGE_ID" */ + +#define NV0073_CTRL_PSR_GET_SR_PANEL_INFO_PARAMS_MESSAGE_ID (0x2U) + +typedef struct NV0073_CTRL_PSR_GET_SR_PANEL_INFO_PARAMS { + NvU32 displayId; + NvU32 frameLockPin; + NvU8 i2cAddress; + NvBool bSelfRefreshEnabled; +} NV0073_CTRL_PSR_GET_SR_PANEL_INFO_PARAMS; + + + +/* _ctrl0073psr_h_ */ diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/common/sdk/nvidia/inc/ctrl/ctrl0073/ctrl0073specific.h nvidia-open-gpu-kernel-modules-535.161.08/src/common/sdk/nvidia/inc/ctrl/ctrl0073/ctrl0073specific.h --- nvidia-open-gpu-kernel-modules-525.147.05/src/common/sdk/nvidia/inc/ctrl/ctrl0073/ctrl0073specific.h 2023-10-25 20:22:08.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/common/sdk/nvidia/inc/ctrl/ctrl0073/ctrl0073specific.h 2024-03-05 22:15:00.000000000 +0000 @@ -27,7 +27,7 @@ // // This file was generated with FINN, an NVIDIA coding tool. -// Source file: ctrl/ctrl0073/ctrl0073specific.finn +// Source file: ctrl/ctrl0073/ctrl0073specific.finn // #include "ctrl/ctrl0073/ctrl0073base.h" @@ -546,6 +546,44 @@ #define NV0073_CTRL_SPECIFIC_CTRL_HDMI_DISABLE (0x00000000U) #define NV0073_CTRL_SPECIFIC_CTRL_HDMI_ENABLE (0x00000001U) +/* + * NV0073_CTRL_CMD_SPECIFIC_SET_HDMI_AUDIO_MUTESTREAM + * + * This command is used to signal the resource manager that the audio stream + * is to be mute off or on. + * subDeviceInstance + * This parameter specifies the subdevice instance within the + * NV04_DISPLAY_COMMON parent device to which operation should be directed. + * This parameter must specify a value between zero and the total number + * of subdevices within the parent device. This parameter should be set + * to zero for default behavior. + * displayId + * This parameter specifies the displayId of HDMI resource to configure. + * This comes as input to this command. + * mute + * This field specifies the legal values: + * NV0073_CTRL_SPECIFIC_SET_HDMI_AUDIO_MUTESTREAM_TRUE + * NV0073_CTRL_SPECIFIC_SET_HDMI_AUDIO_MUTESTREAM_FALSE + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_PARAM_STRUCT + * NV_ERR_INVALID_ARGUMENT + * NV_ERR_NOT_SUPPORTED + */ +#define NV0073_CTRL_CMD_SPECIFIC_SET_HDMI_AUDIO_MUTESTREAM (0x730275U) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_SPECIFIC_INTERFACE_ID << 8) | NV0073_CTRL_CMD_SPECIFIC_SET_HDMI_AUDIO_MUTESTREAM_PARAMS_MESSAGE_ID" */ + +#define NV0073_CTRL_CMD_SPECIFIC_SET_HDMI_AUDIO_MUTESTREAM_PARAMS_MESSAGE_ID (0x75U) + +typedef struct NV0073_CTRL_CMD_SPECIFIC_SET_HDMI_AUDIO_MUTESTREAM_PARAMS { + NvU8 subDeviceInstance; + NvU32 displayId; + NvU8 mute; +} NV0073_CTRL_CMD_SPECIFIC_SET_HDMI_AUDIO_MUTESTREAM_PARAMS; + +#define NV0073_CTRL_SPECIFIC_SET_HDMI_AUDIO_MUTESTREAM_FALSE (0x00000000U) +#define NV0073_CTRL_SPECIFIC_SET_HDMI_AUDIO_MUTESTREAM_TRUE (0x00000001U) + /* @@ -1132,19 +1170,28 @@ * NV_OK * NV_ERR_NOT_SUPPORTED */ -#define NV0073_CTRL_CMD_SPECIFIC_GET_BACKLIGHT_BRIGHTNESS (0x730291U) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_SPECIFIC_INTERFACE_ID << 8) | 0x91" */ - -#define NV0073_CTRL_CMD_SPECIFIC_SET_BACKLIGHT_BRIGHTNESS (0x730292U) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_SPECIFIC_INTERFACE_ID << 8) | 0x92" */ +#define NV0073_CTRL_CMD_SPECIFIC_GET_BACKLIGHT_BRIGHTNESS (0x730291U) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_SPECIFIC_INTERFACE_ID << 8) | NV0073_CTRL_SPECIFIC_GET_BACKLIGHT_BRIGHTNESS_PARAMS_MESSAGE_ID" */ #define NV0073_CTRL_BACKLIGHT_BRIGHTNESS_MIN_VALUE 0U #define NV0073_CTRL_BACKLIGHT_BRIGHTNESS_MAX_VALUE 100U typedef struct NV0073_CTRL_SPECIFIC_BACKLIGHT_BRIGHTNESS_PARAMS { - NvU32 subDeviceInstance; - NvU32 displayId; - NvU32 brightness; + NvU32 subDeviceInstance; + NvU32 displayId; + NvU32 brightness; + NvBool bUncalibrated; } NV0073_CTRL_SPECIFIC_BACKLIGHT_BRIGHTNESS_PARAMS; +#define NV0073_CTRL_SPECIFIC_GET_BACKLIGHT_BRIGHTNESS_PARAMS_MESSAGE_ID (0x91U) + +typedef NV0073_CTRL_SPECIFIC_BACKLIGHT_BRIGHTNESS_PARAMS NV0073_CTRL_SPECIFIC_GET_BACKLIGHT_BRIGHTNESS_PARAMS; + +#define NV0073_CTRL_CMD_SPECIFIC_SET_BACKLIGHT_BRIGHTNESS (0x730292U) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_SPECIFIC_INTERFACE_ID << 8) | NV0073_CTRL_SPECIFIC_SET_BACKLIGHT_BRIGHTNESS_PARAMS_MESSAGE_ID" */ + +#define NV0073_CTRL_SPECIFIC_SET_BACKLIGHT_BRIGHTNESS_PARAMS_MESSAGE_ID (0x92U) + +typedef NV0073_CTRL_SPECIFIC_BACKLIGHT_BRIGHTNESS_PARAMS NV0073_CTRL_SPECIFIC_SET_BACKLIGHT_BRIGHTNESS_PARAMS; + /* * NV0073_CTRL_CMD_SPECIFIC_SET_HDMI_SINK_CAPS * @@ -1227,6 +1274,10 @@ * powerState * This parameter should be one of the valid * NV0073_CTRL_SPECIFIC_SET_MONITOR_POWER_* values. + * headIdx + * The head id on which power operation needs to be done. + * bForceMonitorState + * Monitor power state that client wants to force in RM. * * Possible status values returned are: * NV_OK @@ -1238,9 +1289,11 @@ #define NV0073_CTRL_SPECIFIC_SET_MONITOR_POWER_PARAMS_MESSAGE_ID (0x95U) typedef struct NV0073_CTRL_SPECIFIC_SET_MONITOR_POWER_PARAMS { - NvU32 subDeviceInstance; - NvU32 displayId; - NvU32 powerState; + NvU32 subDeviceInstance; + NvU32 displayId; + NvU32 powerState; + NvU32 headIdx; + NvBool bForceMonitorState; } NV0073_CTRL_SPECIFIC_SET_MONITOR_POWER_PARAMS; #define NV0073_CTRL_SPECIFIC_SET_MONITOR_POWER_OFF (0x00000000U) @@ -1329,7 +1382,7 @@ -#define NV0073_CTRL_SPECIFIC_MAX_CRC_REGIONS 9U +#define NV0073_CTRL_SPECIFIC_MAX_CRC_REGIONS 9U #define NV0073_CTRL_CMD_SPECIFIC_GET_REGIONAL_CRCS_PARAMS_MESSAGE_ID (0xA0U) @@ -1906,4 +1959,30 @@ NvU8 windowHeadMask[NV0073_CTRL_SPECIFIC_MAX_WINDOWS]; } NV0073_CTRL_SPECIFIC_GET_VALID_HEAD_WINDOW_ASSIGNMENT_PARAMS; +/* + * NV0073_CTRL_CMD_SPECIFIC_DEFAULT_ADAPTIVESYNC_DISPLAY + * + * This command is used to query whether the specified monitor should default + * to adaptive sync. + * + * [in]manufacturerID + * This parameter specifies the 16-bit EDID Manufacturer ID. + * [in]productID + * This parameter specifies the 16-bit EDID Product ID. + * [out]bDefaultAdaptivesync; + * This indicates whether the monitor should default to adaptive sync. + * Possible return values: + * NV_OK + */ + +#define NV0073_CTRL_CMD_SPECIFIC_DEFAULT_ADAPTIVESYNC_DISPLAY (0x7302aeU) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_SPECIFIC_INTERFACE_ID << 8) | NV0073_CTRL_SPECIFIC_DEFAULT_ADAPTIVESYNC_DISPLAY_PARAMS_MESSAGE_ID" */ + +#define NV0073_CTRL_SPECIFIC_DEFAULT_ADAPTIVESYNC_DISPLAY_PARAMS_MESSAGE_ID (0xAEU) + +typedef struct NV0073_CTRL_SPECIFIC_DEFAULT_ADAPTIVESYNC_DISPLAY_PARAMS { + NvU16 manufacturerID; + NvU16 productID; + NvBool bDefaultAdaptivesync; +} NV0073_CTRL_SPECIFIC_DEFAULT_ADAPTIVESYNC_DISPLAY_PARAMS; + /* _ctrl0073specific_h_ */ diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/common/sdk/nvidia/inc/ctrl/ctrl0073/ctrl0073stereo.h nvidia-open-gpu-kernel-modules-535.161.08/src/common/sdk/nvidia/inc/ctrl/ctrl0073/ctrl0073stereo.h --- nvidia-open-gpu-kernel-modules-525.147.05/src/common/sdk/nvidia/inc/ctrl/ctrl0073/ctrl0073stereo.h 2023-10-25 20:22:08.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/common/sdk/nvidia/inc/ctrl/ctrl0073/ctrl0073stereo.h 2024-03-05 22:15:00.000000000 +0000 @@ -27,7 +27,7 @@ // // This file was generated with FINN, an NVIDIA coding tool. -// Source file: ctrl/ctrl0073/ctrl0073stereo.finn +// Source file: ctrl/ctrl0073/ctrl0073stereo.finn // #include "ctrl/ctrl0073/ctrl0073base.h" @@ -35,6 +35,41 @@ /* + * NV0073_CTRL_CMD_STEREO_DONGLE_SUPPORTED + * + * This command returns the support status of the NV stereo emitter + * (also known as the stereo dongle). It reports if the stereo dongle + * is present in terms of the USB interface initialized in Resman. + * This provides a RmControl interface to the STEREO_DONGLE_SUPPORTED + * command in stereoDongleControl. + * + * Parameters: + * [IN] subDeviceInstance - This parameter specifies the subdevice instance + * within the NV04_DISPLAY_COMMON parent device to which the operation + * should be directed. This parameter must specify a value between + * zero and the total number of subdevices within the parent device. + * This parameter should be set to zero for default behavior. + * [IN] head - head to be passed to stereoDongleControl + * [IN] bI2cEmitter - I2C driven DT embedded emitter + * [IN] bForcedSupported - GPIO23 driven emitter + * [OUT] support - the control word returned by stereoDongleControl + * + * Possible status values returned are: + * NV_ERR_NOT_SUPPORTED - stereo is not initialized on the GPU + */ +#define NV0073_CTRL_CMD_STEREO_DONGLE_SUPPORTED (0x731702U) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_STEREO_INTERFACE_ID << 8) | NV0073_CTRL_STEREO_DONGLE_SUPPORTED_PARAMS_MESSAGE_ID" */ + +#define NV0073_CTRL_STEREO_DONGLE_SUPPORTED_PARAMS_MESSAGE_ID (0x2U) + +typedef struct NV0073_CTRL_STEREO_DONGLE_SUPPORTED_PARAMS { + NvU32 subDeviceInstance; + NvU32 head; + NvBool bI2cEmitter; + NvBool bForcedSupported; + NvU32 support; +} NV0073_CTRL_STEREO_DONGLE_SUPPORTED_PARAMS; + +/* * NV0073_CTRL_CMD_STEREO_DONGLE_SET_TIMINGS * * Sets new video mode timings diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/common/sdk/nvidia/inc/ctrl/ctrl0073/ctrl0073svp.h nvidia-open-gpu-kernel-modules-535.161.08/src/common/sdk/nvidia/inc/ctrl/ctrl0073/ctrl0073svp.h --- nvidia-open-gpu-kernel-modules-525.147.05/src/common/sdk/nvidia/inc/ctrl/ctrl0073/ctrl0073svp.h 2023-10-25 20:22:08.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/common/sdk/nvidia/inc/ctrl/ctrl0073/ctrl0073svp.h 2024-03-05 22:15:00.000000000 +0000 @@ -27,6 +27,6 @@ // // This file was generated with FINN, an NVIDIA coding tool. -// Source file: ctrl/ctrl0073/ctrl0073svp.finn +// Source file: ctrl/ctrl0073/ctrl0073svp.finn // diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/common/sdk/nvidia/inc/ctrl/ctrl0073/ctrl0073system.h nvidia-open-gpu-kernel-modules-535.161.08/src/common/sdk/nvidia/inc/ctrl/ctrl0073/ctrl0073system.h --- nvidia-open-gpu-kernel-modules-525.147.05/src/common/sdk/nvidia/inc/ctrl/ctrl0073/ctrl0073system.h 2023-10-25 20:22:08.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/common/sdk/nvidia/inc/ctrl/ctrl0073/ctrl0073system.h 2024-03-05 22:15:01.000000000 +0000 @@ -27,7 +27,7 @@ // // This file was generated with FINN, an NVIDIA coding tool. -// Source file: ctrl/ctrl0073/ctrl0073system.finn +// Source file: ctrl/ctrl0073/ctrl0073system.finn // #include "ctrl/ctrl0073/ctrl0073base.h" @@ -468,7 +468,61 @@ NvU32 hotplugAlwaysAttached; } NV0073_CTRL_SYSTEM_GET_SET_HOTPLUG_CONFIG_PARAMS; +/* + * NV0073_CTRL_CMD_SYSTEM_GET_HOTPLUG_STATE + * + * This command can be used to retrieve dynamic hotplug state information that + * are currently recorded by the RM. This information can be used by the client + * to determine which displays to detect after a hotplug event occurs. Or if + * the client knows that this device generates a hot plug/unplug signal on all + * connectors, then this can be used to cull displays from detection. + * + * subDeviceInstance + * This parameter specifies the subdevice instance within the + * NV04_DISPLAY_COMMON parent device to which the operation should be + * directed. This parameter must specify a value between zero and the + * total number of subdevices within the parent device. This parameter + * should be set to zero for default behavior. + * flags + * This parameter specifies optional flags to be used while retrieving + * the hotplug state information. + * Here are the current defined fields: + * NV0073_CTRL_SYSTEM_GET_HOTPLUG_STATE_FLAGS_LID + * A client uses this field to determine the lid state. + * Possible values are: + * NV0073_CTRL_SYSTEM_GET_HOTPLUG_STATE_FLAGS_LID_OPEN + * The lid is open. + * NV0073_CTRL_SYSTEM_GET_HOTPLUG_STATE_FLAGS_LID_CLOSED + * The lid is closed. The client should remove devices as + * reported inside the + * NV0073_CTRL_SYSTEM_GET_CONNECT_POLICY_PARAMS.lidClosedMask. + * hotplugAfterEdidMask + * This display mask specifies an NV0073_DISPLAY_MASK value describing + * the set of displays that have seen a hotplug or hotunplug event + * sometime after the last valid EDID read. If the device never has + * a valid EDID read, then it will always be listed here. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_PARAM_STRUCT + * NV_ERR_INVALID_ARGUMENT + */ + +#define NV0073_CTRL_CMD_SYSTEM_GET_HOTPLUG_STATE (0x730124U) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_SYSTEM_INTERFACE_ID << 8) | NV0073_CTRL_SYSTEM_GET_HOTPLUG_STATE_PARAMS_MESSAGE_ID" */ + +#define NV0073_CTRL_SYSTEM_GET_HOTPLUG_STATE_PARAMS_MESSAGE_ID (0x24U) + +typedef struct NV0073_CTRL_SYSTEM_GET_HOTPLUG_STATE_PARAMS { + NvU32 subDeviceInstance; + NvU32 flags; + NvU32 hotplugAfterEdidMask; +} NV0073_CTRL_SYSTEM_GET_HOTPLUG_STATE_PARAMS; + +/* valid get hoplug state flags */ +#define NV0073_CTRL_SYSTEM_GET_HOTPLUG_STATE_FLAGS_LID 0:0 +#define NV0073_CTRL_SYSTEM_GET_HOTPLUG_STATE_FLAGS_LID_OPEN (0x00000000U) +#define NV0073_CTRL_SYSTEM_GET_HOTPLUG_STATE_FLAGS_LID_CLOSED (0x00000001U) /* * NV0073_CTRL_CMD_SYSTEM_GET_HEAD_ROUTING_MAP @@ -755,9 +809,175 @@ NvU32 availableInternalDisplaysMask; } NV0073_CTRL_SYSTEM_GET_INTERNAL_DISPLAYS_PARAMS; +/* + * NV0073_CTRL_CMD_SYSTEM_ACPI_SUBSYSTEM_ACTIVATED + * + * This command is used to notify RM that all subdevices are ready for ACPI + * calls. The caller must make sure that the OS is ready to handle the ACPI + * calls for each ACPI ID. So, this call must be done after the OS has + * initialized all the display ACPI IDs to this subdevice. + * Besides, the ACPI spec provides a function for the display drivers to read + * the EDID directly from the SBIOS for each display's ACPI ID. This function + * is used to override the EDID found from a I2C or DPAux based transaction. + * This command will also attempt to call the ACPI _DDC function to read the + * EDID from the SBIOS for all displayIDs. If an EDID is found from this call, + * the RM will store that new EDID in the EDID buffer of that OD. + * + * subDeviceInstance + * This parameter specifies the subdevice instance within the + * NV04_DISPLAY_COMMON parent device to which the operation should be + * directed. This parameter must specify a value between zero and the + * total number of subdevices within the parent device. This parameter + * should be set to zero for default behavior. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_PARAM_STRUCT + * NV_ERR_NOT_SUPPORTED + * + */ + +#define NV0073_CTRL_SYSTEM_ACPI_SUBSYSTEM_ACTIVATED_PARAMS_MESSAGE_ID (0x5CU) + +typedef struct NV0073_CTRL_SYSTEM_ACPI_SUBSYSTEM_ACTIVATED_PARAMS { + NvU32 subDeviceInstance; +} NV0073_CTRL_SYSTEM_ACPI_SUBSYSTEM_ACTIVATED_PARAMS; + +#define NV0073_CTRL_CMD_SYSTEM_ACPI_SUBSYSTEM_ACTIVATED (0x73015cU) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_SYSTEM_INTERFACE_ID << 8) | NV0073_CTRL_SYSTEM_ACPI_SUBSYSTEM_ACTIVATED_PARAMS_MESSAGE_ID" */ /* + * NV0073_CTRL_SYSTEM_CONNECTOR_INFO + * + * This structure describes a single connector table entry. + * + * type + * This field specifies the connector type. + * displayMask + * This field specifies the the displayMask to which the connector belongs. + * location + * This field specifies the placement of the connector on the platform. + * hotplug + * This field specifies hotplug capabilities (if any) for the connector. + */ +typedef struct NV0073_CTRL_SYSTEM_CONNECTOR_INFO { + NvU32 type; + NvU32 displayMask; + NvU32 location; + NvU32 hotplug; +} NV0073_CTRL_SYSTEM_CONNECTOR_INFO; + +/* valid type values */ +#define NV0073_CTRL_SYSTEM_CONNECTOR_INFO_TYPE_VGA_15_PIN (0x00000000U) +#define NV0073_CTRL_SYSTEM_CONNECTOR_INFO_TYPE_DVI_A (0x00000001U) +#define NV0073_CTRL_SYSTEM_CONNECTOR_INFO_TYPE_POD_VGA_15_PIN (0x00000002U) +#define NV0073_CTRL_SYSTEM_CONNECTOR_INFO_TYPE_TV_COMPOSITE (0x00000010U) +#define NV0073_CTRL_SYSTEM_CONNECTOR_INFO_TYPE_TV_SVIDEO (0x00000011U) +#define NV0073_CTRL_SYSTEM_CONNECTOR_INFO_TYPE_TV_SVIDEO_BO_COMPOSITE (0x00000012U) +#define NV0073_CTRL_SYSTEM_CONNECTOR_INFO_TYPE_TV_COMPONENT (0x00000013U) +#define NV0073_CTRL_SYSTEM_CONNECTOR_INFO_TYPE_TV_SCART (0x00000014U) +#define NV0073_CTRL_SYSTEM_CONNECTOR_INFO_TYPE_TV_SCART_EIAJ4120 (0x00000014U) +#define NV0073_CTRL_SYSTEM_CONNECTOR_INFO_TYPE_TV_EIAJ4120 (0x00000017U) +#define NV0073_CTRL_SYSTEM_CONNECTOR_INFO_TYPE_PC_POD_HDTV_YPRPB (0x00000018U) +#define NV0073_CTRL_SYSTEM_CONNECTOR_INFO_TYPE_PC_POD_SVIDEO (0x00000019U) +#define NV0073_CTRL_SYSTEM_CONNECTOR_INFO_TYPE_PC_POD_COMPOSITE (0x0000001AU) +#define NV0073_CTRL_SYSTEM_CONNECTOR_INFO_TYPE_DVI_I_TV_SVIDEO (0x00000020U) +#define NV0073_CTRL_SYSTEM_CONNECTOR_INFO_TYPE_DVI_I_TV_COMPOSITE (0x00000021U) +#define NV0073_CTRL_SYSTEM_CONNECTOR_INFO_TYPE_DVI_I_TV_SV_BO_COMPOSITE (0x00000022U) +#define NV0073_CTRL_SYSTEM_CONNECTOR_INFO_TYPE_DVI_I (0x00000030U) +#define NV0073_CTRL_SYSTEM_CONNECTOR_INFO_TYPE_DVI_D (0x00000031U) +#define NV0073_CTRL_SYSTEM_CONNECTOR_INFO_TYPE_ADC (0x00000032U) +#define NV0073_CTRL_SYSTEM_CONNECTOR_INFO_TYPE_LFH_DVI_I_1 (0x00000038U) +#define NV0073_CTRL_SYSTEM_CONNECTOR_INFO_TYPE_LFH_DVI_I_2 (0x00000039U) +#define NV0073_CTRL_SYSTEM_CONNECTOR_INFO_TYPE_LFH_SVIDEO (0x0000003AU) +#define NV0073_CTRL_SYSTEM_CONNECTOR_INFO_TYPE_BNC (0x0000003CU) +#define NV0073_CTRL_SYSTEM_CONNECTOR_INFO_TYPE_LVDS_SPWG (0x00000040U) +#define NV0073_CTRL_SYSTEM_CONNECTOR_INFO_TYPE_LVDS_OEM (0x00000041U) +#define NV0073_CTRL_SYSTEM_CONNECTOR_INFO_TYPE_LVDS_SPWG_DET (0x00000042U) +#define NV0073_CTRL_SYSTEM_CONNECTOR_INFO_TYPE_LVDS_OEM_DET (0x00000043U) +#define NV0073_CTRL_SYSTEM_CONNECTOR_INFO_TYPE_TVDS_OEM_ATT (0x00000045U) +#define NV0073_CTRL_SYSTEM_CONNECTOR_INFO_TYPE_VGA_15_PIN_UNDOCKED (0x00000050U) +#define NV0073_CTRL_SYSTEM_CONNECTOR_INFO_TYPE_VGA_15_PIN_DOCKED (0x00000051U) +#define NV0073_CTRL_SYSTEM_CONNECTOR_INFO_TYPE_DVI_I_UNDOCKED (0x00000052U) +#define NV0073_CTRL_SYSTEM_CONNECTOR_INFO_TYPE_DVI_I_DOCKED (0x00000053U) +#define NV0073_CTRL_SYSTEM_CONNECTOR_INFO_TYPE_DVI_D_UNDOCKED (0x00000052U) +#define NV0073_CTRL_SYSTEM_CONNECTOR_INFO_TYPE_DVI_D_DOCKED (0x00000053U) +#define NV0073_CTRL_SYSTEM_CONNECTOR_INFO_TYPE_DP_EXT (0x00000056U) +#define NV0073_CTRL_SYSTEM_CONNECTOR_INFO_TYPE_DP_INT (0x00000057U) +#define NV0073_CTRL_SYSTEM_CONNECTOR_INFO_TYPE_DP_EXT_UNDOCKED (0x00000058U) +#define NV0073_CTRL_SYSTEM_CONNECTOR_INFO_TYPE_DP_EXT_DOCKED (0x00000059U) +#define NV0073_CTRL_SYSTEM_CONNECTOR_INFO_TYPE_3PIN_DIN_STEREO (0x00000060U) +#define NV0073_CTRL_SYSTEM_CONNECTOR_INFO_TYPE_HDMI_A (0x00000061U) +#define NV0073_CTRL_SYSTEM_CONNECTOR_INFO_TYPE_AUDIO_SPDIF (0x00000062U) +#define NV0073_CTRL_SYSTEM_CONNECTOR_INFO_TYPE_HDMI_C_MINI (0x00000063U) +#define NV0073_CTRL_SYSTEM_CONNECTOR_INFO_TYPE_LFH_DP_1 (0x00000064U) +#define NV0073_CTRL_SYSTEM_CONNECTOR_INFO_TYPE_LFH_DP_2 (0x00000065U) +#define NV0073_CTRL_SYSTEM_CONNECTOR_INFO_TYPE_VIRTUAL_WFD (0x00000070U) + +/* valid hotplug values */ +#define NV0073_CTRL_SYSTEM_CONNECTOR_INFO_HOTPLUG_A_SUPPORTED (0x00000001U) +#define NV0073_CTRL_SYSTEM_CONNECTOR_INFO_HOTPLUG_B_SUPPORTED (0x00000002U) + +/* + * Nv0073_CTRL_CMD_SYSTEM_GET_CONNECTOR_TABLE + * + * This command can be used to retrieve display connector information. + * + * subDeviceInstance + * This parameter specifies the subdevice instance within the + * NV04_DISPLAY_COMMON parent device to which the operation should be + * directed. This parameter must specify a value between zero and the + * total number of subdevices within the parent device. This parameter + * should be set to zero for default behavior. + * version + * This parameter returns the version of the connector table. + * platform + * This parameter returns the type of platform of the associated subdevice. + * connectorTableEntries + * This parameter returns the number of valid entries in the connector + * table. + * connectorTable + * This parameter returns the connector information in the form of an + * array of NV0073_CTRL_SYSTEM_CONNECTOR_INFO structures. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_ARGUMENT + * + */ +#define NV0073_CTRL_CMD_SYSTEM_GET_CONNECTOR_TABLE (0x730165U) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_SYSTEM_INTERFACE_ID << 8) | NV0073_CTRL_SYSTEM_GET_CONNECTOR_TABLE_PARAMS_MESSAGE_ID" */ + +/* maximum number of connector table entries */ +#define NV0073_CTRL_SYSTEM_GET_CONNECTOR_TABLE_MAX_ENTRIES (16U) + +#define NV0073_CTRL_SYSTEM_GET_CONNECTOR_TABLE_PARAMS_MESSAGE_ID (0x65U) + +typedef struct NV0073_CTRL_SYSTEM_GET_CONNECTOR_TABLE_PARAMS { + NvU32 subDeviceInstance; + NvU32 version; + NvU32 platform; + NvU32 connectorTableEntries; + /* + * C form: + * NV0073_CTRL_SYSTEM_CONNECTOR_INFO connectorTable[NV0073_CTRL_SYSTEM_CONNECTOR_TABLE_MAX_ENTRIES]; + */ + NV0073_CTRL_SYSTEM_CONNECTOR_INFO connectorTable[NV0073_CTRL_SYSTEM_GET_CONNECTOR_TABLE_MAX_ENTRIES]; +} NV0073_CTRL_SYSTEM_GET_CONNECTOR_TABLE_PARAMS; + +/* valid version values */ +#define NV0073_CTRL_SYSTEM_CONNECTOR_INFO_VERSION_30 (0x00000030U) + +/* valid platform values */ +#define NV0073_CTRL_SYSTEM_CONNECTOR_INFO_PLATFORM_DEFAULT_ADD_IN_CARD (0x00000000U) +#define NV0073_CTRL_SYSTEM_CONNECTOR_INFO_PLATFORM_TWO_PLATE_ADD_IN_CARD (0x00000001U) +#define NV0073_CTRL_SYSTEM_CONNECTOR_INFO_PLATFORM_MOBILE_ADD_IN_CARD (0x00000008U) +#define NV0073_CTRL_SYSTEM_CONNECTOR_INFO_PLATFORM_MXM_MODULE (0x00000009U) +#define NV0073_CTRL_SYSTEM_CONNECTOR_INFO_PLATFORM_MOBILE_BACK (0x00000010U) +#define NV0073_CTRL_SYSTEM_CONNECTOR_INFO_PLATFORM_MOBILE_BACK_LEFT (0x00000011U) +#define NV0073_CTRL_SYSTEM_CONNECTOR_INFO_PLATFORM_MOBILE_BACK_DOCK (0x00000018U) +#define NV0073_CTRL_SYSTEM_CONNECTOR_INFO_PLATFORM_CRUSH_DEFAULT (0x00000020U) + +/* * NV0073_CTRL_CMD_SYSTEM_GET_BOOT_DISPLAYS * * This command returns a mask of boot display IDs. @@ -1046,6 +1266,36 @@ /* +* NV0073_CTRL_SYSTEM_VRR_DISPLAY_INFO_PARAMS +* +* This command is used to update information about VRR capable monitors +* subDeviceInstance +* This parameter specifies the subdevice instance within the +* NV04_DISPLAY_COMMON parent device to which the operation should be +* directed.This parameter must specify a value between zero and the +* total number of subdevices within the parent device.This parameter +* should be set to zero for default behavior. +* +* displayId +* DisplayId of the panel for which client wants to add or remove from VRR +* capable monitor list +* +* bAddition +* When set to NV_TRUE, signifies that the vrr monitor is to be added. +* When set to NV_FALSE, signifies that the vrr monitor is to be removed. +* +*/ +#define NV0073_CTRL_CMD_SYSTEM_VRR_DISPLAY_INFO (0x730185U) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_SYSTEM_INTERFACE_ID << 8) | NV0073_CTRL_SYSTEM_VRR_DISPLAY_INFO_PARAMS_MESSAGE_ID" */ + +#define NV0073_CTRL_SYSTEM_VRR_DISPLAY_INFO_PARAMS_MESSAGE_ID (0x85U) + +typedef struct NV0073_CTRL_SYSTEM_VRR_DISPLAY_INFO_PARAMS { + NvU32 subDeviceInstance; + NvU32 displayId; + NvBool bAddition; +} NV0073_CTRL_SYSTEM_VRR_DISPLAY_INFO_PARAMS; + +/* * NV0073_CTRL_CMD_SYSTEM_GET_HOTPLUG_UNPLUG_STATE * * This command can be used to retrieve hotplug and unplug state @@ -1090,7 +1340,9 @@ * NV_ERR_INVALID_ARGUMENT */ -#define NV0073_CTRL_CMD_SYSTEM_GET_HOTPLUG_UNPLUG_STATE (0x73017bU) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_SYSTEM_INTERFACE_ID << 8) | 0x7B" */ +#define NV0073_CTRL_CMD_SYSTEM_GET_HOTPLUG_UNPLUG_STATE (0x73017bU) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_SYSTEM_INTERFACE_ID << 8) | NV0073_CTRL_SYSTEM_GET_HOTPLUG_UNPLUG_STATE_PARAMS_MESSAGE_ID" */ + +#define NV0073_CTRL_SYSTEM_GET_HOTPLUG_UNPLUG_STATE_PARAMS_MESSAGE_ID (0x7BU) typedef struct NV0073_CTRL_SYSTEM_GET_HOTPLUG_UNPLUG_STATE_PARAMS { NvU32 subDeviceInstance; @@ -1367,7 +1619,11 @@ * the parameters. */ -#define NV0073_CTRL_CMD_SYSTEM_GET_HOTPLUG_EVENT_CONFIG (0x730197U) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_SYSTEM_INTERFACE_ID << 8) | 0x97" */ +#define NV0073_CTRL_CMD_SYSTEM_GET_HOTPLUG_EVENT_CONFIG (0x730197U) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_SYSTEM_INTERFACE_ID << 8) | NV0073_CTRL_SYSTEM_GET_HOTPLUG_EVENT_CONFIG_PARAMS_MESSAGE_ID" */ + +#define NV0073_CTRL_SYSTEM_GET_HOTPLUG_EVENT_CONFIG_PARAMS_MESSAGE_ID (0x97U) + +typedef NV0073_CTRL_SYSTEM_HOTPLUG_EVENT_CONFIG_PARAMS NV0073_CTRL_SYSTEM_GET_HOTPLUG_EVENT_CONFIG_PARAMS; /* * NV0073_CTRL_CMD_SYSTEM_SET_HOTPLUG_EVENT_CONFIG @@ -1378,7 +1634,11 @@ * the parameters. */ -#define NV0073_CTRL_CMD_SYSTEM_SET_HOTPLUG_EVENT_CONFIG (0x730198U) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_SYSTEM_INTERFACE_ID << 8) | 0x98" */ +#define NV0073_CTRL_CMD_SYSTEM_SET_HOTPLUG_EVENT_CONFIG (0x730198U) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_SYSTEM_INTERFACE_ID << 8) | NV0073_CTRL_SYSTEM_SET_HOTPLUG_EVENT_CONFIG_PARAMS_MESSAGE_ID" */ + +#define NV0073_CTRL_SYSTEM_SET_HOTPLUG_EVENT_CONFIG_PARAMS_MESSAGE_ID (0x98U) + +typedef NV0073_CTRL_SYSTEM_HOTPLUG_EVENT_CONFIG_PARAMS NV0073_CTRL_SYSTEM_SET_HOTPLUG_EVENT_CONFIG_PARAMS; @@ -1476,5 +1736,60 @@ NvBool bIsSidebandSrSupported; } NV0073_CTRL_CMD_SYSTEM_CHECK_SIDEBAND_SR_SUPPORT_PARAMS; +/* + * NV0073_CTRL_CMD_SYSTEM_VRR_SET_RGLINE_ACTIVE + * + * This command is used by client like nvkms to set up the VRR specific + * memory operation in RM such as mapping the client created shared memory + * into RM and reserving a RGline for processing of self-refresh timeout + * related calculations. + * + * Also the expectation is that the client which calls this command with parameter + * bEnable = TRUE, should also call this command with bEnable = FALSE on the + * same head when VRR needs to be disabled. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_ARGUMENT + * NV_ERR_OBJECT_NOT_FOUND + * NV_ERR_GENERIC + */ + +/* + * This is the shared structure that will be used to communicate between + * Physical RM and clients. As of now the access relies on single source of + * truth operation, i.e. only Physical RM writes into the shared location + * and client (nvkms) reads from the same location. + * + * "dataTimeStamp" field is added to capture the timestamp before and after + * updating the flip delay related data fields(all fields except "timeout"). + * This timestamp will be used by clients to determine if the data got updated + * in between by RM while clients were reading it. + * As of now "timeout" field does not have such protection, as access to + * this field is only in response to notification from RM. + */ +typedef struct NV0073_CTRL_RM_VRR_SHARED_DATA { + NvU32 expectedFrameNum; + NvU32 timeout; + NV_DECLARE_ALIGNED(NvU64 flipTimeStamp, 8); + NvBool bCheckFlipTime; + NvBool bFlipTimeAdjustment; + NV_DECLARE_ALIGNED(NvU64 dataTimeStamp, 8); +} NV0073_CTRL_RM_VRR_SHARED_DATA; + +#define NV0073_CTRL_CMD_SYSTEM_VRR_SET_RGLINE_ACTIVE (0x73019eU) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_SYSTEM_INTERFACE_ID << 8) | NV0073_CTRL_CMD_SYSTEM_VRR_SET_RGLINE_ACTIVE_PARAMS_MESSAGE_ID" */ + +#define NV0073_CTRL_CMD_SYSTEM_VRR_SET_RGLINE_ACTIVE_PARAMS_MESSAGE_ID (0x9EU) + +typedef struct NV0073_CTRL_CMD_SYSTEM_VRR_SET_RGLINE_ACTIVE_PARAMS { + NvU32 subDeviceInstance; + NvBool bEnable; + NvU32 head; + NvU32 height; + NvU32 maxFrameTime; + NvU32 minFrameTime; + NvHandle hMemory; +} NV0073_CTRL_CMD_SYSTEM_VRR_SET_RGLINE_ACTIVE_PARAMS; + /* _ctrl0073system_h_ */ diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/common/sdk/nvidia/inc/ctrl/ctrl0073.h nvidia-open-gpu-kernel-modules-535.161.08/src/common/sdk/nvidia/inc/ctrl/ctrl0073.h --- nvidia-open-gpu-kernel-modules-525.147.05/src/common/sdk/nvidia/inc/ctrl/ctrl0073.h 2023-10-25 20:22:07.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/common/sdk/nvidia/inc/ctrl/ctrl0073.h 2024-03-05 22:14:59.000000000 +0000 @@ -25,7 +25,7 @@ // // This file was generated with FINN, an NVIDIA coding tool. -// Source file: ctrl/ctrl0073.finn +// Source file: ctrl/ctrl0073.finn // @@ -43,3 +43,4 @@ #include "ctrl0073/ctrl0073svp.h" #include "ctrl0073/ctrl0073dpu.h" #include "ctrl0073/ctrl0073psr.h" +#include "ctrl0073/ctrl0073common.h" diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/common/sdk/nvidia/inc/ctrl/ctrl0080/ctrl0080base.h nvidia-open-gpu-kernel-modules-535.161.08/src/common/sdk/nvidia/inc/ctrl/ctrl0080/ctrl0080base.h --- nvidia-open-gpu-kernel-modules-525.147.05/src/common/sdk/nvidia/inc/ctrl/ctrl0080/ctrl0080base.h 2023-10-25 20:22:08.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/common/sdk/nvidia/inc/ctrl/ctrl0080/ctrl0080base.h 2024-03-05 22:15:01.000000000 +0000 @@ -25,7 +25,7 @@ // // This file was generated with FINN, an NVIDIA coding tool. -// Source file: ctrl/ctrl0080/ctrl0080base.finn +// Source file: ctrl/ctrl0080/ctrl0080base.finn // #include "ctrl/ctrlxxxx.h" diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/common/sdk/nvidia/inc/ctrl/ctrl0080/ctrl0080bif.h nvidia-open-gpu-kernel-modules-535.161.08/src/common/sdk/nvidia/inc/ctrl/ctrl0080/ctrl0080bif.h --- nvidia-open-gpu-kernel-modules-525.147.05/src/common/sdk/nvidia/inc/ctrl/ctrl0080/ctrl0080bif.h 2023-10-25 20:22:08.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/common/sdk/nvidia/inc/ctrl/ctrl0080/ctrl0080bif.h 2024-03-05 22:15:01.000000000 +0000 @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 2009-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2009-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -27,7 +27,7 @@ // // This file was generated with FINN, an NVIDIA coding tool. -// Source file: ctrl/ctrl0080/ctrl0080bif.finn +// Source file: ctrl/ctrl0080/ctrl0080bif.finn // #include "ctrl/ctrl0080/ctrl0080base.h" @@ -62,10 +62,14 @@ NvU32 flags; } NV0080_CTRL_BIF_RESET_PARAMS; -#define NV0080_CTRL_BIF_RESET_FLAGS_TYPE 2:0 -#define NV0080_CTRL_BIF_RESET_FLAGS_TYPE_SW_RESET (0x00000001) -#define NV0080_CTRL_BIF_RESET_FLAGS_TYPE_SBR (0x00000002) -#define NV0080_CTRL_BIF_RESET_FLAGS_TYPE_FUNDAMENTAL (0x00000003) +#define NV0080_CTRL_BIF_RESET_FLAGS_TYPE 3:0 +#define NV0080_CTRL_BIF_RESET_FLAGS_TYPE_SW_RESET 0x1 +#define NV0080_CTRL_BIF_RESET_FLAGS_TYPE_SBR 0x2 +#define NV0080_CTRL_BIF_RESET_FLAGS_TYPE_FUNDAMENTAL 0x3 +#define NV0080_CTRL_BIF_RESET_FLAGS_TYPE_BOOT_DEVICE_FUSE 0x4 +#define NV0080_CTRL_BIF_RESET_FLAGS_TYPE_BOOT_DEVICE 0x5 +#define NV0080_CTRL_BIF_RESET_FLAGS_TYPE_PEX 0x6 +#define NV0080_CTRL_BIF_RESET_FLAGS_TYPE_OOBHUB_TRIGGER 0x7 /* * NV0080_CTRL_BIF_GET_DMA_BASE_SYSMEM_ADDR @@ -81,7 +85,7 @@ * NV_ERR_INVALID_OBJECT_PARENT */ -#define NV0080_CTRL_CMD_BIF_GET_DMA_BASE_SYSMEM_ADDR (0x800103) /* finn: Evaluated from "(FINN_NV01_DEVICE_0_BIF_INTERFACE_ID << 8) | NV0080_CTRL_BIF_GET_DMA_BASE_SYSMEM_ADDR_PARAMS_MESSAGE_ID" */ +#define NV0080_CTRL_CMD_BIF_GET_DMA_BASE_SYSMEM_ADDR (0x800103) /* finn: Evaluated from "(FINN_NV01_DEVICE_0_BIF_INTERFACE_ID << 8) | NV0080_CTRL_BIF_GET_DMA_BASE_SYSMEM_ADDR_PARAMS_MESSAGE_ID" */ #define NV0080_CTRL_BIF_GET_DMA_BASE_SYSMEM_ADDR_PARAMS_MESSAGE_ID (0x3U) @@ -134,5 +138,27 @@ NvBool bL1Enable; } NV0080_CTRL_BIF_ASPM_CYA_UPDATE_PARAMS; +/* + * NV0080_CTRL_BIF_ASPM_FEATURE + * + * pciePowerControlMask + * pciePowerControlIdentifiedKeyOrder + * pciePowerControlIdentifiedKeyLocation + * ASPM and RTD3 enable/disable information + * + * Possible status values returned are: + * NV_OK + */ + +#define NV0080_CTRL_CMD_BIF_GET_PCIE_POWER_CONTROL_MASK (0x800106) /* finn: Evaluated from "(FINN_NV01_DEVICE_0_BIF_INTERFACE_ID << 8) | NV0080_CTRL_CMD_BIF_GET_PCIE_POWER_CONTROL_MASK_PARAMS_MESSAGE_ID" */ + +#define NV0080_CTRL_CMD_BIF_GET_PCIE_POWER_CONTROL_MASK_PARAMS_MESSAGE_ID (0x6U) + +typedef struct NV0080_CTRL_CMD_BIF_GET_PCIE_POWER_CONTROL_MASK_PARAMS { + NvU32 pciePowerControlMask; + NvU32 pciePowerControlIdentifiedKeyOrder; + NvU32 pciePowerControlIdentifiedKeyLocation; +} NV0080_CTRL_CMD_BIF_GET_PCIE_POWER_CONTROL_MASK_PARAMS; + /* _ctrl0080bif_h_ */ diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/common/sdk/nvidia/inc/ctrl/ctrl0080/ctrl0080bsp.h nvidia-open-gpu-kernel-modules-535.161.08/src/common/sdk/nvidia/inc/ctrl/ctrl0080/ctrl0080bsp.h --- nvidia-open-gpu-kernel-modules-525.147.05/src/common/sdk/nvidia/inc/ctrl/ctrl0080/ctrl0080bsp.h 2023-10-25 20:22:09.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/common/sdk/nvidia/inc/ctrl/ctrl0080/ctrl0080bsp.h 2024-03-05 22:15:01.000000000 +0000 @@ -26,7 +26,7 @@ // // This file was generated with FINN, an NVIDIA coding tool. -// Source file: ctrl/ctrl0080/ctrl0080bsp.finn +// Source file: ctrl/ctrl0080/ctrl0080bsp.finn // #include "ctrl/ctrl0080/ctrl0080base.h" diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/common/sdk/nvidia/inc/ctrl/ctrl0080/ctrl0080cipher.h nvidia-open-gpu-kernel-modules-535.161.08/src/common/sdk/nvidia/inc/ctrl/ctrl0080/ctrl0080cipher.h --- nvidia-open-gpu-kernel-modules-525.147.05/src/common/sdk/nvidia/inc/ctrl/ctrl0080/ctrl0080cipher.h 2023-10-25 20:22:09.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/common/sdk/nvidia/inc/ctrl/ctrl0080/ctrl0080cipher.h 2024-03-05 22:15:01.000000000 +0000 @@ -27,6 +27,6 @@ // // This file was generated with FINN, an NVIDIA coding tool. -// Source file: ctrl/ctrl0080/ctrl0080cipher.finn +// Source file: ctrl/ctrl0080/ctrl0080cipher.finn // diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/common/sdk/nvidia/inc/ctrl/ctrl0080/ctrl0080clk.h nvidia-open-gpu-kernel-modules-535.161.08/src/common/sdk/nvidia/inc/ctrl/ctrl0080/ctrl0080clk.h --- nvidia-open-gpu-kernel-modules-525.147.05/src/common/sdk/nvidia/inc/ctrl/ctrl0080/ctrl0080clk.h 2023-10-25 20:22:09.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/common/sdk/nvidia/inc/ctrl/ctrl0080/ctrl0080clk.h 2024-03-05 22:15:01.000000000 +0000 @@ -27,6 +27,6 @@ // // This file was generated with FINN, an NVIDIA coding tool. -// Source file: ctrl/ctrl0080/ctrl0080clk.finn +// Source file: ctrl/ctrl0080/ctrl0080clk.finn // diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/common/sdk/nvidia/inc/ctrl/ctrl0080/ctrl0080dma.h nvidia-open-gpu-kernel-modules-535.161.08/src/common/sdk/nvidia/inc/ctrl/ctrl0080/ctrl0080dma.h --- nvidia-open-gpu-kernel-modules-525.147.05/src/common/sdk/nvidia/inc/ctrl/ctrl0080/ctrl0080dma.h 2023-10-25 20:22:09.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/common/sdk/nvidia/inc/ctrl/ctrl0080/ctrl0080dma.h 2024-03-05 22:15:01.000000000 +0000 @@ -27,7 +27,7 @@ // // This file was generated with FINN, an NVIDIA coding tool. -// Source file: ctrl/ctrl0080/ctrl0080dma.finn +// Source file: ctrl/ctrl0080/ctrl0080dma.finn // #include "ctrl/ctrl0080/ctrl0080base.h" @@ -87,7 +87,7 @@ */ typedef struct NV0080_CTRL_DMA_PTE_INFO_PTE_BLOCK { - NvU32 pageSize; + NV_DECLARE_ALIGNED(NvU64 pageSize, 8); NV_DECLARE_ALIGNED(NvU64 pteEntrySize, 8); NvU32 comptagLine; NvU32 kind; @@ -160,7 +160,7 @@ #define NV0080_CTRL_CMD_DMA_GET_PTE_INFO (0x801801U) /* finn: Evaluated from "(FINN_NV01_DEVICE_0_DMA_INTERFACE_ID << 8) | NV0080_CTRL_DMA_GET_PTE_INFO_PARAMS_MESSAGE_ID" */ -#define NV0080_CTRL_DMA_GET_PTE_INFO_PTE_BLOCKS 4U +#define NV0080_CTRL_DMA_GET_PTE_INFO_PTE_BLOCKS 5U #define NV0080_CTRL_DMA_GET_PTE_INFO_PARAMS_MESSAGE_ID (0x1U) @@ -190,7 +190,7 @@ #define NV0080_CTRL_CMD_DMA_SET_PTE_INFO (0x80180aU) /* finn: Evaluated from "(FINN_NV01_DEVICE_0_DMA_INTERFACE_ID << 8) | NV0080_CTRL_DMA_SET_PTE_INFO_PARAMS_MESSAGE_ID" */ -#define NV0080_CTRL_DMA_SET_PTE_INFO_PTE_BLOCKS 4U +#define NV0080_CTRL_DMA_SET_PTE_INFO_PTE_BLOCKS 5U #define NV0080_CTRL_DMA_SET_PTE_INFO_PARAMS_MESSAGE_ID (0xAU) @@ -356,9 +356,8 @@ NV0080_CTRL_DMA_ADV_SCHED_GET_VA_CAPS_PAGE_TABLE_FORMAT pageTable4KFormat[NV0080_CTRL_DMA_ADV_SCHED_GET_VA_CAPS_MAX_NUM_PAGE_TABLE_FORMATS]; NvHandle hVASpace; NV_DECLARE_ALIGNED(NvU64 vaRangeLo, 8); - NvU32 hugePageSize; NvU32 vaSpaceId; - NvU32 pageSize512MB; + NV_DECLARE_ALIGNED(NvU64 supportedPageSizeMask, 8); } NV0080_CTRL_DMA_ADV_SCHED_GET_VA_CAPS_PARAMS; /* @@ -429,7 +428,7 @@ #define NV0080_CTRL_DMA_GET_PDE_INFO_PARAMS_PTE_ADDR_SPACE_SYSTEM_COHERENT_MEMORY (0x00000001U) #define NV0080_CTRL_DMA_GET_PDE_INFO_PARAMS_PTE_ADDR_SPACE_SYSTEM_NON_COHERENT_MEMORY (0x00000002U) -#define NV0080_CTRL_DMA_PDE_INFO_PTE_BLOCKS 4U +#define NV0080_CTRL_DMA_PDE_INFO_PTE_BLOCKS 5U #define NV0080_CTRL_DMA_GET_PDE_INFO_PARAMS_MESSAGE_ID (0x9U) @@ -454,23 +453,6 @@ #define NV0080_CTRL_DMA_GET_PDE_INFO_PARAMS_PDE_SIZE_EIGHTH 4U /* - * NV0080_CTRL_CMD_DMA_INVALIDATE_PDB_TARGET - * - * This command invalidates PDB target setting in hardware. - * After execeution of this command PDB target would be in undefined state. - * - * Returns error if the PDB target can not be invalidate. - * - * This call is only supported on chips fermi and later chips. - * - * Possible status values returned are: - * NV_OK - * NV_ERR_NOT_SUPPORTED - */ - -#define NV0080_CTRL_CMD_DMA_INVALIDATE_PDB_TARGET (0x80180bU) /* finn: Evaluated from "(FINN_NV01_DEVICE_0_DMA_INTERFACE_ID << 8) | 0xB" */ - -/* * NV0080_CTRL_CMD_DMA_INVALIDATE_TLB * * This command invalidates the GPU TLB. This is intended to be used diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/common/sdk/nvidia/inc/ctrl/ctrl0080/ctrl0080fb.h nvidia-open-gpu-kernel-modules-535.161.08/src/common/sdk/nvidia/inc/ctrl/ctrl0080/ctrl0080fb.h --- nvidia-open-gpu-kernel-modules-525.147.05/src/common/sdk/nvidia/inc/ctrl/ctrl0080/ctrl0080fb.h 2023-10-25 20:22:09.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/common/sdk/nvidia/inc/ctrl/ctrl0080/ctrl0080fb.h 2024-03-05 22:15:02.000000000 +0000 @@ -27,7 +27,7 @@ // // This file was generated with FINN, an NVIDIA coding tool. -// Source file: ctrl/ctrl0080/ctrl0080fb.finn +// Source file: ctrl/ctrl0080/ctrl0080fb.finn // #include "ctrl/ctrl0080/ctrl0080base.h" @@ -227,7 +227,36 @@ NvU8 capsTbl[NV0080_CTRL_FB_CAPS_TBL_SIZE]; } NV0080_CTRL_FB_GET_CAPS_V2_PARAMS; - +/** + * NV0080_CTRL_CMD_FB_SET_DEFAULT_VIDMEM_PHYSICALITY + * + * When clients allocate video memory specifying _DEFAULT (0) for + * NVOS32_ATTR_PHYSICALITY, RM will usually allocate contiguous memory. + * Clients can change that behavior with this command so that _DEFAULT maps to + * another value. + * + * The expectation is that clients currently implicitly rely on the default, + * but can be incrementally updated to explicitly specify _CONTIGUOUS where + * necessary and change the default for their allocations to _NONCONTIGUOUS or + * _ALLOW_NONCONTIGUOUS. + * + * In the future RM may be updated to globally default to _NONCONTIGUOUS or + * _ALLOW_NONCONTIGUOUS, and at that point this can be removed. + */ +#define NV0080_CTRL_CMD_FB_SET_DEFAULT_VIDMEM_PHYSICALITY (0x801308) /* finn: Evaluated from "(FINN_NV01_DEVICE_0_FB_INTERFACE_ID << 8) | NV0080_CTRL_FB_SET_DEFAULT_VIDMEM_PHYSICALITY_PARAMS_MESSAGE_ID" */ + +#define NV0080_CTRL_FB_SET_DEFAULT_VIDMEM_PHYSICALITY_PARAMS_MESSAGE_ID (0x8U) + +typedef struct NV0080_CTRL_FB_SET_DEFAULT_VIDMEM_PHYSICALITY_PARAMS { + NvU32 value; +} NV0080_CTRL_FB_SET_DEFAULT_VIDMEM_PHYSICALITY_PARAMS; + +typedef enum NV0080_CTRL_FB_DEFAULT_VIDMEM_PHYSICALITY { + NV0080_CTRL_FB_DEFAULT_VIDMEM_PHYSICALITY_DEFAULT = 0, + NV0080_CTRL_FB_DEFAULT_VIDMEM_PHYSICALITY_NONCONTIGUOUS = 1, + NV0080_CTRL_FB_DEFAULT_VIDMEM_PHYSICALITY_CONTIGUOUS = 2, + NV0080_CTRL_FB_DEFAULT_VIDMEM_PHYSICALITY_ALLOW_NONCONTIGUOUS = 3, +} NV0080_CTRL_FB_DEFAULT_VIDMEM_PHYSICALITY; /* _ctrl0080fb_h_ */ diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/common/sdk/nvidia/inc/ctrl/ctrl0080/ctrl0080fifo.h nvidia-open-gpu-kernel-modules-535.161.08/src/common/sdk/nvidia/inc/ctrl/ctrl0080/ctrl0080fifo.h --- nvidia-open-gpu-kernel-modules-525.147.05/src/common/sdk/nvidia/inc/ctrl/ctrl0080/ctrl0080fifo.h 2023-10-25 20:22:09.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/common/sdk/nvidia/inc/ctrl/ctrl0080/ctrl0080fifo.h 2024-03-05 22:15:02.000000000 +0000 @@ -27,7 +27,7 @@ // // This file was generated with FINN, an NVIDIA coding tool. -// Source file: ctrl/ctrl0080/ctrl0080fifo.finn +// Source file: ctrl/ctrl0080/ctrl0080fifo.finn // #include "ctrl/ctrl0080/ctrl0080base.h" @@ -91,72 +91,7 @@ #define NV0080_CTRL_FIFO_CAPS_SUPPORT_WDDM_INTERLEAVING 1:0x40 /* size in bytes of fifo caps table */ -#define NV0080_CTRL_FIFO_CAPS_TBL_SIZE 2 - -/* - * NV0080_CTRL_CMD_FIFO_ENABLE_SCHED_EVENTS - * - * This command enables the GPU to place various scheduling events in the - * off chip event buffer (with optional interrupt) for those GPUs that support - * it. - * - * record - * This parameter specifies a mask of event types to record. - * interrupt - * This parameter specifies a mask of event types for which to interrupt - * the CPU when the event occurs. - * - * Possible status values returned are: - * NV_OK - * NV_ERR_INVALID_PARAM_STRUCT - * NV_ERR_INVALID_ARGUMENT - */ -#define NV0080_CTRL_CMD_FIFO_ENABLE_SCHED_EVENTS (0x801703) /* finn: Evaluated from "(FINN_NV01_DEVICE_0_FIFO_INTERFACE_ID << 8) | 0x3" */ - -typedef struct NV0080_CTRL_FIFO_ENABLE_SCHED_EVENTS_PARAMS { - NvU32 record; - NvU32 interrupt; -} NV0080_CTRL_FIFO_ENABLE_SCHED_EVENTS_PARAMS; - -#define NV0080_CTRL_FIFO_ENABLE_SCHED_EVENTS_START_CTX 0:0 -#define NV0080_CTRL_FIFO_ENABLE_SCHED_EVENTS_START_CTX_DISABLE (0x00000000) -#define NV0080_CTRL_FIFO_ENABLE_SCHED_EVENTS_START_CTX_ENABLE (0x00000001) -#define NV0080_CTRL_FIFO_ENABLE_SCHED_EVENTS_END_CTX 1:1 -#define NV0080_CTRL_FIFO_ENABLE_SCHED_EVENTS_END_CTX_DISABLE (0x00000000) -#define NV0080_CTRL_FIFO_ENABLE_SCHED_EVENTS_END_CTX_ENABLE (0x00000001) -#define NV0080_CTRL_FIFO_ENABLE_SCHED_EVENTS_NEW_RUNLIST 2:2 -#define NV0080_CTRL_FIFO_ENABLE_SCHED_EVENTS_NEW_RUNLIST_DISABLE (0x00000000) -#define NV0080_CTRL_FIFO_ENABLE_SCHED_EVENTS_NEW_RUNLIST_ENABLE (0x00000001) -#define NV0080_CTRL_FIFO_ENABLE_SCHED_EVENTS_SEM_ACQUIRE 3:3 -#define NV0080_CTRL_FIFO_ENABLE_SCHED_EVENTS_SEM_ACQUIRE_DISABLE (0x00000000) -#define NV0080_CTRL_FIFO_ENABLE_SCHED_EVENTS_SEM_ACQUIRE_ENABLE (0x00000001) -#define NV0080_CTRL_FIFO_ENABLE_SCHED_EVENTS_PAGE_FAULT 4:4 -#define NV0080_CTRL_FIFO_ENABLE_SCHED_EVENTS_PAGE_FAULT_DISABLE (0x00000000) -#define NV0080_CTRL_FIFO_ENABLE_SCHED_EVENTS_PAGE_FAULT_ENABLE (0x00000001) -#define NV0080_CTRL_FIFO_ENABLE_SCHED_EVENTS_PREEMPT 5:5 -#define NV0080_CTRL_FIFO_ENABLE_SCHED_EVENTS_PREEMPT_DISABLE (0x00000000) -#define NV0080_CTRL_FIFO_ENABLE_SCHED_EVENTS_PREEMPT_ENABLE (0x00000001) -#define NV0080_CTRL_FIFO_ENABLE_SCHED_EVENTS_YIELD 6:6 -#define NV0080_CTRL_FIFO_ENABLE_SCHED_EVENTS_YIELD_DISABLE (0x00000000) -#define NV0080_CTRL_FIFO_ENABLE_SCHED_EVENTS_YIELD_ENABLE (0x00000001) -#define NV0080_CTRL_FIFO_ENABLE_SCHED_EVENTS_IDLE_CTX 7:7 -#define NV0080_CTRL_FIFO_ENABLE_SCHED_EVENTS_IDLE_CTX_DISABLE (0x00000000) -#define NV0080_CTRL_FIFO_ENABLE_SCHED_EVENTS_IDLE_CTX_ENABLE (0x00000001) -#define NV0080_CTRL_FIFO_ENABLE_SCHED_EVENTS_HI_PRI 8:8 -#define NV0080_CTRL_FIFO_ENABLE_SCHED_EVENTS_HI_PRI_DISABLE (0x00000000) -#define NV0080_CTRL_FIFO_ENABLE_SCHED_EVENTS_HI_PRI_ENABLE (0x00000001) -#define NV0080_CTRL_FIFO_ENABLE_SCHED_EVENTS_ENG_STALLED 9:9 -#define NV0080_CTRL_FIFO_ENABLE_SCHED_EVENTS_ENG_STALLED_DISABLE (0x00000000) -#define NV0080_CTRL_FIFO_ENABLE_SCHED_EVENTS_ENG_STALLED_ENABLE (0x00000001) -#define NV0080_CTRL_FIFO_ENABLE_SCHED_EVENTS_VSYNC 10:10 -#define NV0080_CTRL_FIFO_ENABLE_SCHED_EVENTS_VSYNC_DISABLE (0x00000000) -#define NV0080_CTRL_FIFO_ENABLE_SCHED_EVENTS_VSYNC_ENABLE (0x00000001) -#define NV0080_CTRL_FIFO_ENABLE_SCHED_EVENTS_FGCS_FAULT 11:11 -#define NV0080_CTRL_FIFO_ENABLE_SCHED_EVENTS_FGCS_FAULT_DISABLE (0x00000000) -#define NV0080_CTRL_FIFO_ENABLE_SCHED_EVENTS_FGCS_FAULT_ENABLE (0x00000001) -#define NV0080_CTRL_FIFO_ENABLE_SCHED_EVENTS_ALL 11:0 -#define NV0080_CTRL_FIFO_ENABLE_SCHED_EVENTS_ALL_DISABLE (0x00000000) -#define NV0080_CTRL_FIFO_ENABLE_SCHED_EVENTS_ALL_ENABLE (0x00000fff) +#define NV0080_CTRL_FIFO_CAPS_TBL_SIZE 2 /* * NV0080_CTRL_CMD_FIFO_START_SELECTED_CHANNELS diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/common/sdk/nvidia/inc/ctrl/ctrl0080/ctrl0080gpu.h nvidia-open-gpu-kernel-modules-535.161.08/src/common/sdk/nvidia/inc/ctrl/ctrl0080/ctrl0080gpu.h --- nvidia-open-gpu-kernel-modules-525.147.05/src/common/sdk/nvidia/inc/ctrl/ctrl0080/ctrl0080gpu.h 2023-10-25 20:22:09.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/common/sdk/nvidia/inc/ctrl/ctrl0080/ctrl0080gpu.h 2024-03-05 22:15:02.000000000 +0000 @@ -27,7 +27,7 @@ // // This file was generated with FINN, an NVIDIA coding tool. -// Source file: ctrl/ctrl0080/ctrl0080gpu.finn +// Source file: ctrl/ctrl0080/ctrl0080gpu.finn // #include "ctrl/ctrl0080/ctrl0080base.h" diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/common/sdk/nvidia/inc/ctrl/ctrl0080/ctrl0080gr.h nvidia-open-gpu-kernel-modules-535.161.08/src/common/sdk/nvidia/inc/ctrl/ctrl0080/ctrl0080gr.h --- nvidia-open-gpu-kernel-modules-525.147.05/src/common/sdk/nvidia/inc/ctrl/ctrl0080/ctrl0080gr.h 2023-10-25 20:22:09.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/common/sdk/nvidia/inc/ctrl/ctrl0080/ctrl0080gr.h 2024-03-05 22:15:02.000000000 +0000 @@ -27,10 +27,11 @@ // // This file was generated with FINN, an NVIDIA coding tool. -// Source file: ctrl/ctrl0080/ctrl0080gr.finn +// Source file: ctrl/ctrl0080/ctrl0080gr.finn // #include "ctrl/ctrl0080/ctrl0080base.h" +#include "nvcfg_sdk.h" typedef struct NV0080_CTRL_GR_ROUTE_INFO { NvU32 flags; @@ -95,10 +96,7 @@ * indicates that there is no minimum and the bug is not present on this * system. */ -typedef struct NV0080_CTRL_GR_INFO { - NvU32 index; - NvU32 data; -} NV0080_CTRL_GR_INFO; +typedef NVXXXX_CTRL_XXX_INFO NV0080_CTRL_GR_INFO; /* valid graphics info index values */ #define NV0080_CTRL_GR_INFO_INDEX_MAXCLIPS (0x00000000) @@ -152,12 +150,16 @@ #define NV0080_CTRL_GR_INFO_INDEX_LITTER_NUM_SLICES_PER_LTC (0x00000032) + +#define NV0080_CTRL_GR_INFO_INDEX_DUMMY (0x00000033) +#define NV0080_CTRL_GR_INFO_INDEX_GFX_CAPABILITIES (0x00000034) + /* When adding a new INDEX, please update MAX_SIZE accordingly * NOTE: 0080 functionality is merged with 2080 functionality, so this max size * reflects that. */ -#define NV0080_CTRL_GR_INFO_INDEX_MAX (0x00000032) -#define NV0080_CTRL_GR_INFO_MAX_SIZE (0x33) /* finn: Evaluated from "(NV0080_CTRL_GR_INFO_INDEX_MAX + 1)" */ +#define NV0080_CTRL_GR_INFO_INDEX_MAX (0x00000034) +#define NV0080_CTRL_GR_INFO_MAX_SIZE (0x35) /* finn: Evaluated from "(NV0080_CTRL_GR_INFO_INDEX_MAX + 1)" */ /* * NV0080_CTRL_CMD_GR_GET_INFO @@ -210,9 +212,9 @@ * disambiguate the target GR engine. * */ -#define NV0080_CTRL_CMD_GR_GET_TPC_PARTITION_MODE (0x801107) /* finn: Evaluated from "(FINN_NV01_DEVICE_0_GR_INTERFACE_ID << 8) | 0x7" */ +#define NV0080_CTRL_CMD_GR_GET_TPC_PARTITION_MODE (0x801107) /* finn: Evaluated from "(FINN_NV01_DEVICE_0_GR_INTERFACE_ID << 8) | NV0080_CTRL_GR_GET_TPC_PARTITION_MODE_PARAMS_MESSAGE_ID" */ -#define NV0080_CTRL_CMD_GR_SET_TPC_PARTITION_MODE (0x801108) /* finn: Evaluated from "(FINN_NV01_DEVICE_0_GR_INTERFACE_ID << 8) | 0x8" */ +#define NV0080_CTRL_CMD_GR_SET_TPC_PARTITION_MODE (0x801108) /* finn: Evaluated from "(FINN_NV01_DEVICE_0_GR_INTERFACE_ID << 8) | NV0080_CTRL_GR_SET_TPC_PARTITION_MODE_PARAMS_MESSAGE_ID" */ /* Enum for listing TPC partitioning modes */ typedef enum NV0080_CTRL_GR_TPC_PARTITION_MODE { @@ -228,6 +230,14 @@ NV_DECLARE_ALIGNED(NV0080_CTRL_GR_ROUTE_INFO grRouteInfo, 8); // [in] } NV0080_CTRL_GR_TPC_PARTITION_MODE_PARAMS; +#define NV0080_CTRL_GR_GET_TPC_PARTITION_MODE_PARAMS_MESSAGE_ID (0x7U) + +typedef NV0080_CTRL_GR_TPC_PARTITION_MODE_PARAMS NV0080_CTRL_GR_GET_TPC_PARTITION_MODE_PARAMS; + +#define NV0080_CTRL_GR_SET_TPC_PARTITION_MODE_PARAMS_MESSAGE_ID (0x8U) + +typedef NV0080_CTRL_GR_TPC_PARTITION_MODE_PARAMS NV0080_CTRL_GR_SET_TPC_PARTITION_MODE_PARAMS; + /** * NV0080_CTRL_CMD_GR_GET_CAPS_V2 * diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/common/sdk/nvidia/inc/ctrl/ctrl0080/ctrl0080host.h nvidia-open-gpu-kernel-modules-535.161.08/src/common/sdk/nvidia/inc/ctrl/ctrl0080/ctrl0080host.h --- nvidia-open-gpu-kernel-modules-525.147.05/src/common/sdk/nvidia/inc/ctrl/ctrl0080/ctrl0080host.h 2023-10-25 20:22:10.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/common/sdk/nvidia/inc/ctrl/ctrl0080/ctrl0080host.h 2024-03-05 22:15:02.000000000 +0000 @@ -27,7 +27,7 @@ // // This file was generated with FINN, an NVIDIA coding tool. -// Source file: ctrl/ctrl0080/ctrl0080host.finn +// Source file: ctrl/ctrl0080/ctrl0080host.finn // #include "ctrl/ctrl0080/ctrl0080base.h" @@ -88,7 +88,6 @@ #define NV0080_CTRL_HOST_CAPS_P2P_4_WAY 1:0x08 // Deprecated #define NV0080_CTRL_HOST_CAPS_P2P_8_WAY 1:0x10 // Deprecated #define NV0080_CTRL_HOST_CAPS_P2P_DEADLOCK_BUG_203825 1:0x20 // Deprecated -#define NV0080_CTRL_HOST_CAPS_VIRTUAL_P2P 1:0x40 #define NV0080_CTRL_HOST_CAPS_BUG_254580 1:0x80 #define NV0080_CTRL_HOST_CAPS_COMPRESSED_BL_P2P_BUG_257072 2:0x02 // Deprecated #define NV0080_CTRL_HOST_CAPS_CROSS_BLITS_BUG_270260 2:0x04 // Deprecated diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/common/sdk/nvidia/inc/ctrl/ctrl0080/ctrl0080internal.h nvidia-open-gpu-kernel-modules-535.161.08/src/common/sdk/nvidia/inc/ctrl/ctrl0080/ctrl0080internal.h --- nvidia-open-gpu-kernel-modules-525.147.05/src/common/sdk/nvidia/inc/ctrl/ctrl0080/ctrl0080internal.h 2023-10-25 20:22:10.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/common/sdk/nvidia/inc/ctrl/ctrl0080/ctrl0080internal.h 2024-03-05 22:15:02.000000000 +0000 @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 2020-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2020-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -27,11 +27,12 @@ // // This file was generated with FINN, an NVIDIA coding tool. -// Source file: ctrl/ctrl0080/ctrl0080internal.finn +// Source file: ctrl/ctrl0080/ctrl0080internal.finn // #include "nvlimits.h" #include "ctrl0080gr.h" +#include "ctrl0080fifo.h" #include "ctrl/ctrl0080/ctrl0080base.h" #include "ctrl/ctrl0080/ctrl0080perf.h" @@ -91,7 +92,7 @@ /*! * @ref NV0080_CTRL_CMD_INTERNAL_PERF_GET_UNDERPOWERED_GPU_COUNT */ -#define NV0080_CTRL_CMD_INTERNAL_PERF_GET_UNDERPOWERED_GPU_COUNT (0x802006) /* finn: Evaluated from "(FINN_NV01_DEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV0080_CTRL_INTERNAL_PERF_GET_UNDERPOWERED_GPU_COUNT_PARAMS_MESSAGE_ID" */ +#define NV0080_CTRL_CMD_INTERNAL_PERF_GET_UNDERPOWERED_GPU_COUNT (0x802006) /* finn: Evaluated from "(FINN_NV01_DEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV0080_CTRL_INTERNAL_PERF_GET_UNDERPOWERED_GPU_COUNT_PARAMS_MESSAGE_ID" */ #define NV0080_CTRL_INTERNAL_PERF_GET_UNDERPOWERED_GPU_COUNT_PARAMS_MESSAGE_ID (0x6U) @@ -100,4 +101,30 @@ NvU8 powerDisconnectedGpuCount; } NV0080_CTRL_INTERNAL_PERF_GET_UNDERPOWERED_GPU_COUNT_PARAMS; +/* + * NV0080_CTRL_CMD_INTERNAL_FIFO_RC_AND_PERMANENTLY_DISABLE_CHANNELS + * + * This command will RC and disable channels permanently for the given clients. + * + * numClients + * Number of clients + * clientHandles + * List of client handles + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_STATE + */ + +#define NV0080_CTRL_CMD_INTERNAL_FIFO_RC_AND_PERMANENTLY_DISABLE_CHANNELS (0x802008) /* finn: Evaluated from "(FINN_NV01_DEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV0080_CTRL_INTERNAL_FIFO_RC_AND_PERMANENTLY_DISABLE_CHANNELS_PARAMS_MESSAGE_ID" */ + +#define NV_FIFO_PERMANENTLY_DISABLE_CHANNELS_MAX_CLIENTS 200U + +#define NV0080_CTRL_INTERNAL_FIFO_RC_AND_PERMANENTLY_DISABLE_CHANNELS_PARAMS_MESSAGE_ID (0x08U) + +typedef struct NV0080_CTRL_INTERNAL_FIFO_RC_AND_PERMANENTLY_DISABLE_CHANNELS_PARAMS { + NvU32 numClients; + NvHandle clientHandles[NV_FIFO_PERMANENTLY_DISABLE_CHANNELS_MAX_CLIENTS]; +} NV0080_CTRL_INTERNAL_FIFO_RC_AND_PERMANENTLY_DISABLE_CHANNELS_PARAMS; + /* ctrl0080internal_h */ diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/common/sdk/nvidia/inc/ctrl/ctrl0080/ctrl0080msenc.h nvidia-open-gpu-kernel-modules-535.161.08/src/common/sdk/nvidia/inc/ctrl/ctrl0080/ctrl0080msenc.h --- nvidia-open-gpu-kernel-modules-525.147.05/src/common/sdk/nvidia/inc/ctrl/ctrl0080/ctrl0080msenc.h 2023-10-25 20:22:10.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/common/sdk/nvidia/inc/ctrl/ctrl0080/ctrl0080msenc.h 2024-03-05 22:15:02.000000000 +0000 @@ -27,7 +27,7 @@ // // This file was generated with FINN, an NVIDIA coding tool. -// Source file: ctrl/ctrl0080/ctrl0080msenc.finn +// Source file: ctrl/ctrl0080/ctrl0080msenc.finn // #include "ctrl/ctrl0080/ctrl0080base.h" diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/common/sdk/nvidia/inc/ctrl/ctrl0080/ctrl0080nvjpg.h nvidia-open-gpu-kernel-modules-535.161.08/src/common/sdk/nvidia/inc/ctrl/ctrl0080/ctrl0080nvjpg.h --- nvidia-open-gpu-kernel-modules-525.147.05/src/common/sdk/nvidia/inc/ctrl/ctrl0080/ctrl0080nvjpg.h 2023-10-25 20:22:10.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/common/sdk/nvidia/inc/ctrl/ctrl0080/ctrl0080nvjpg.h 2024-03-05 22:15:02.000000000 +0000 @@ -27,7 +27,7 @@ // // This file was generated with FINN, an NVIDIA coding tool. -// Source file: ctrl/ctrl0080/ctrl0080nvjpg.finn +// Source file: ctrl/ctrl0080/ctrl0080nvjpg.finn // #include "ctrl/ctrl0080/ctrl0080base.h" diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/common/sdk/nvidia/inc/ctrl/ctrl0080/ctrl0080perf.h nvidia-open-gpu-kernel-modules-535.161.08/src/common/sdk/nvidia/inc/ctrl/ctrl0080/ctrl0080perf.h --- nvidia-open-gpu-kernel-modules-525.147.05/src/common/sdk/nvidia/inc/ctrl/ctrl0080/ctrl0080perf.h 2023-10-25 20:22:10.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/common/sdk/nvidia/inc/ctrl/ctrl0080/ctrl0080perf.h 2024-03-05 22:15:02.000000000 +0000 @@ -27,7 +27,7 @@ // // This file was generated with FINN, an NVIDIA coding tool. -// Source file: ctrl/ctrl0080/ctrl0080perf.finn +// Source file: ctrl/ctrl0080/ctrl0080perf.finn // #define NV0080_CTRL_PERF_SLI_GPU_BOOST_SYNC_CONTROL_PARAMS_MESSAGE_ID (0x7U) diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/common/sdk/nvidia/inc/ctrl/ctrl0080/ctrl0080rc.h nvidia-open-gpu-kernel-modules-535.161.08/src/common/sdk/nvidia/inc/ctrl/ctrl0080/ctrl0080rc.h --- nvidia-open-gpu-kernel-modules-525.147.05/src/common/sdk/nvidia/inc/ctrl/ctrl0080/ctrl0080rc.h 2023-10-25 20:22:10.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/common/sdk/nvidia/inc/ctrl/ctrl0080/ctrl0080rc.h 1970-01-01 00:00:00.000000000 +0000 @@ -1,57 +0,0 @@ -/* - * SPDX-FileCopyrightText: Copyright (c) 2004-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. - * SPDX-License-Identifier: MIT - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER - * DEALINGS IN THE SOFTWARE. - */ - -#pragma once - -// -// This file was generated with FINN, an NVIDIA coding tool. -// Source file: ctrl/ctrl0080/ctrl0080rc.finn -// - -#include "ctrl/ctrl0080/ctrl0080base.h" - -/* NV01_DEVICE_XX/NV03_DEVICE gpu control commands and parameters */ - -/* - * NV0080_CTRL_CMD_RC_DISABLE_RESET_CHANNEL_CALLBACK - * - * This command prevents RM from using callbacks when resetting a channel due - * to a page fault. - * - * Possible status return values are: - * NV_OK - */ -#define NV0080_CTRL_CMD_RC_DISABLE_RESET_CHANNEL_CALLBACK (0x801d01) /* finn: Evaluated from "(FINN_NV01_DEVICE_0_RC_INTERFACE_ID << 8) | 0x1" */ - -/* - * NV0080_CTRL_CMD_RC_ENABLE_RESET_CHANNEL_CALLBACK - * - * This command permits RM to use callbacks when resetting a channel due - * to a page fault. - * - * Possible status return values are: - * NV_OK - */ -#define NV0080_CTRL_CMD_RC_ENABLE_RESET_CHANNEL_CALLBACK (0x801d02) /* finn: Evaluated from "(FINN_NV01_DEVICE_0_RC_INTERFACE_ID << 8) | 0x2" */ - -/* _ctrl0080rc_h_ */ diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/common/sdk/nvidia/inc/ctrl/ctrl0080/ctrl0080unix.h nvidia-open-gpu-kernel-modules-535.161.08/src/common/sdk/nvidia/inc/ctrl/ctrl0080/ctrl0080unix.h --- nvidia-open-gpu-kernel-modules-525.147.05/src/common/sdk/nvidia/inc/ctrl/ctrl0080/ctrl0080unix.h 2023-10-25 20:22:10.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/common/sdk/nvidia/inc/ctrl/ctrl0080/ctrl0080unix.h 2024-03-05 22:15:02.000000000 +0000 @@ -27,7 +27,7 @@ // // This file was generated with FINN, an NVIDIA coding tool. -// Source file: ctrl/ctrl0080/ctrl0080unix.finn +// Source file: ctrl/ctrl0080/ctrl0080unix.finn // #include "ctrl/ctrl0080/ctrl0080base.h" diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/common/sdk/nvidia/inc/ctrl/ctrl0080.h nvidia-open-gpu-kernel-modules-535.161.08/src/common/sdk/nvidia/inc/ctrl/ctrl0080.h --- nvidia-open-gpu-kernel-modules-525.147.05/src/common/sdk/nvidia/inc/ctrl/ctrl0080.h 2023-10-25 20:22:08.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/common/sdk/nvidia/inc/ctrl/ctrl0080.h 2024-03-05 22:15:01.000000000 +0000 @@ -25,7 +25,7 @@ // // This file was generated with FINN, an NVIDIA coding tool. -// Source file: ctrl/ctrl0080.finn +// Source file: ctrl/ctrl0080.finn // @@ -45,7 +45,6 @@ #include "ctrl0080/ctrl0080perf.h" #include "ctrl0080/ctrl0080msenc.h" #include "ctrl0080/ctrl0080bsp.h" -#include "ctrl0080/ctrl0080rc.h" #include "ctrl0080/ctrl0080nvjpg.h" #include "ctrl0080/ctrl0080unix.h" #include "ctrl0080/ctrl0080internal.h" diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/common/sdk/nvidia/inc/ctrl/ctrl0090.h nvidia-open-gpu-kernel-modules-535.161.08/src/common/sdk/nvidia/inc/ctrl/ctrl0090.h --- nvidia-open-gpu-kernel-modules-525.147.05/src/common/sdk/nvidia/inc/ctrl/ctrl0090.h 2023-10-25 20:22:10.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/common/sdk/nvidia/inc/ctrl/ctrl0090.h 2024-03-05 22:15:03.000000000 +0000 @@ -27,7 +27,7 @@ // // This file was generated with FINN, an NVIDIA coding tool. -// Source file: ctrl/ctrl0090.finn +// Source file: ctrl/ctrl0090.finn // diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/common/sdk/nvidia/inc/ctrl/ctrl00da.h nvidia-open-gpu-kernel-modules-535.161.08/src/common/sdk/nvidia/inc/ctrl/ctrl00da.h --- nvidia-open-gpu-kernel-modules-525.147.05/src/common/sdk/nvidia/inc/ctrl/ctrl00da.h 1970-01-01 00:00:00.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/common/sdk/nvidia/inc/ctrl/ctrl00da.h 2024-03-05 22:15:03.000000000 +0000 @@ -0,0 +1,199 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#pragma once + +#include + +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: ctrl/ctrl00da.finn +// + + + +/* NV_SEMAPHORE_SURFACE control commands and parameters */ + +#define NV_SEMAPHORE_SURFACE_CTRL_CMD(cat,idx) NVXXXX_CTRL_CMD(0x00DA, NV00DA_CTRL_##cat, idx) + +/* +* NV_SEMAPHORE_SURFACE_CTRL_CMD_REF_MEMORY +* Duplicate the memory object(s) bound to the semaphore surface into the RM +* client of the caller. +* +* The handle values are generated and returned by resource manager if the +* client specified a handle value of zero. +* +* If the semaphore surface has a valid max submitted value memory object, but +* the GPU + system do not require separate max submitted value and semaphore +* value surfaces, the handles provided by the client must be equal, and the +* handles returned by resource manager will also be equal. In such cases, the +* client must recognize that both handles correspond to a single reference to +* a single object, and hence the handle must be freed only once by the client. +* +* If the GPU does not require a max submitted value memory object, the handle +* value must be set to zero and the returned handle will always be zero as +* well. +* +* RETURNS: +* NVOS_STATUS_SUCCESS if the memory object(s) were successfully duplicated +* into the calling client. +* NVOS_STATUS_ERROR_INVALID_PARAMETER if any of the rules regarding the +* max submitted value handle value were violated. +* An error code forwarded from NvRmDupObject for any other failures. +*/ +#define NV_SEMAPHORE_SURFACE_CTRL_CMD_REF_MEMORY (0xda0001) /* finn: Evaluated from "(FINN_NV_SEMAPHORE_SURFACE_INTERFACE_ID << 8) | NV_SEMAPHORE_SURFACE_CTRL_REF_MEMORY_PARAMS_MESSAGE_ID" */ + +#define NV_SEMAPHORE_SURFACE_CTRL_REF_MEMORY_PARAMS_MESSAGE_ID (0x01U) + +typedef struct NV_SEMAPHORE_SURFACE_CTRL_REF_MEMORY_PARAMS { + NvHandle hSemaphoreMem; + NvHandle hMaxSubmittedMem; +} NV_SEMAPHORE_SURFACE_CTRL_REF_MEMORY_PARAMS; + +/* +* NV_SEMAPHORE_SURFACE_CTRL_CMD_BIND_CHANNEL +* Associates a channel with the semaphore surface. All channels which will +* wait on or signal semaphores in a semaphore surface should first register +* with it to ensure proper event delivery and error handling. +* +* engineMask is a bitfield whose contents should be defined by setting bit +* index to '1' if the corresponding engine index will be used. See +* cl2080.h for a list of engine indices. For example, this would indicate +* a channel making use of the engines GR0(graphics/compute), COPY0-COPY9, +* and host: +* +* NvU64 engineMask = (1ULL << NV2080_ENGINE_TYPE_GR0) | +* (1ULL << NV2080_ENGINE_TYPE_COPY0) | +* (1ULL << NV2080_ENGINE_TYPE_COPY1) | +* (1ULL << NV2080_ENGINE_TYPE_COPY2) | +* (1ULL << NV2080_ENGINE_TYPE_COPY3) | +* (1ULL << NV2080_ENGINE_TYPE_COPY4) | +* (1ULL << NV2080_ENGINE_TYPE_COPY5) | +* (1ULL << NV2080_ENGINE_TYPE_COPY6) | +* (1ULL << NV2080_ENGINE_TYPE_COPY7) | +* (1ULL << NV2080_ENGINE_TYPE_COPY8) | +* (1ULL << NV2080_ENGINE_TYPE_COPY9) | +* (1ULL << NV2080_ENGINE_TYPE_HOST); +*/ +#define NV_SEMAPHORE_SURFACE_CTRL_CMD_BIND_CHANNEL (0xda0002) /* finn: Evaluated from "(FINN_NV_SEMAPHORE_SURFACE_INTERFACE_ID << 8) | NV_SEMAPHORE_SURFACE_CTRL_BIND_CHANNEL_PARAMS_MESSAGE_ID" */ + +#define NV_SEMAPHORE_SURFACE_CTRL_BIND_CHANNEL_PARAMS_MESSAGE_ID (0x02U) + +typedef struct NV_SEMAPHORE_SURFACE_CTRL_BIND_CHANNEL_PARAMS { + NvHandle hClient; + NvHandle hDevice; + NvHandle hChannel; + NV_DECLARE_ALIGNED(NvU64 engineMask, 8); +} NV_SEMAPHORE_SURFACE_CTRL_BIND_CHANNEL_PARAMS; + +/* +* NV_SEMAPHORE_SURFACE_CTRL_CMD_REGISTER_WAITER +* Ask RM to signal the specified OS event and/or set the semaphore to a new +* value when the value at the specified index is >= a desired value. +* +* index - Specifies the semaphore slot within the surface to which the the wait +* applies. +* waitValue - The value to wait for. +* newValue - Specifies a value to set the semaphore to automatically when the +* specified semaphore slot reaches waitValue. "0" means the semaphore +* value is not altered by this waiter. +* notificationHandle - The OS event (kernel callback or userspace event +* handle) to notify when the value is reached, or 0 if no notification +* is required. +* +* The waiter must specify at least one action. +* +* RETURNS: +* NVOS_STATUS_SUCCESS if the waitValue has not been reached and a waiter was +* successfully registered +* NVOS_STATUS_SUCCESS if the waitValue has been reached, newValue was applied, +* and notificationHandle was 0 (No notification was requested). +* NVOS_STATUS_ERROR_ALREADY_SIGNALLED if the waitValue has been reached and +* newValue was applied if it was not 0, but no notification was registered +* or generated on notificationHandle. Other notifications generated as a +* side effect of newValue being applied, if any, were generated. +* NVOS_STATUS_ERROR_STATE_IN_USE if newValue is not 0 and the specified index +* already has an auto-update value registered. No waiter is registered. +* NVOS_STATUS_ERROR_STATE_IN_USE if the specified notification handle is +* already registered as a waiter for the specified wait_value at the +* specified index. +* already has an auto-update value registered. No waiter is registered. +* NVOS_STATUS_ERROR_* miscelaneous internal errors. No waiter is registered. +*/ +#define NV_SEMAPHORE_SURFACE_CTRL_CMD_REGISTER_WAITER (0xda0003) /* finn: Evaluated from "(FINN_NV_SEMAPHORE_SURFACE_INTERFACE_ID << 8) | NV_SEMAPHORE_SURFACE_CTRL_REGISTER_WAITER_PARAMS_MESSAGE_ID" */ + +#define NV_SEMAPHORE_SURFACE_CTRL_REGISTER_WAITER_PARAMS_MESSAGE_ID (0x03U) + +typedef struct NV_SEMAPHORE_SURFACE_CTRL_REGISTER_WAITER_PARAMS { + NV_DECLARE_ALIGNED(NvU64 index, 8); + NV_DECLARE_ALIGNED(NvU64 waitValue, 8); + NV_DECLARE_ALIGNED(NvU64 newValue, 8); + NV_DECLARE_ALIGNED(NvU64 notificationHandle, 8); +} NV_SEMAPHORE_SURFACE_CTRL_REGISTER_WAITER_PARAMS; + +/* +* NV_SEMAPHORE_SURFACE_CTRL_CMD_SET_VALUE +* Modify a semaphore surface semaphore value, awakening any CPU waiters in +* the process. newValue must be >= the current value at the specified index. +*/ +#define NV_SEMAPHORE_SURFACE_CTRL_CMD_SET_VALUE (0xda0004) /* finn: Evaluated from "(FINN_NV_SEMAPHORE_SURFACE_INTERFACE_ID << 8) | NV_SEMAPHORE_SURFACE_CTRL_SET_VALUE_PARAMS_MESSAGE_ID" */ + +#define NV_SEMAPHORE_SURFACE_CTRL_SET_VALUE_PARAMS_MESSAGE_ID (0x04U) + +typedef struct NV_SEMAPHORE_SURFACE_CTRL_SET_VALUE_PARAMS { + NV_DECLARE_ALIGNED(NvU64 index, 8); + NV_DECLARE_ALIGNED(NvU64 newValue, 8); +} NV_SEMAPHORE_SURFACE_CTRL_SET_VALUE_PARAMS; + +/* +* NV_SEMAPHORE_SURFACE_CTRL_CMD_UNREGISTER_WAITER +* Remove a previously registered notification handle from an index + value +* tuple's list of waiters. +* +* index - Specifies the semaphore slot within the surface on which the waiter +* was previously registered. +* waitValue - The value the wait was registered for. +* notificationHandle - The OS event (kernel callback or userspace event +* handle) registered as a waiter. +* +* RETURNS: +* NVOS_STATUS_SUCCESS the waiter was successfully removed from the list of +* pending waiters. +* NVOS_STATUS_ERROR_* miscelaneous internal errors, or the waiter was not +* found in the list of pending waiters. The waiter may have already been +* called, or may be in a list of imminent notifications the RM is +* processing. +*/ +#define NV_SEMAPHORE_SURFACE_CTRL_CMD_UNREGISTER_WAITER (0xda0005) /* finn: Evaluated from "(FINN_NV_SEMAPHORE_SURFACE_INTERFACE_ID << 8) | NV_SEMAPHORE_SURFACE_CTRL_UNREGISTER_WAITER_PARAMS_MESSAGE_ID" */ + +#define NV_SEMAPHORE_SURFACE_CTRL_UNREGISTER_WAITER_PARAMS_MESSAGE_ID (0x05U) + +typedef struct NV_SEMAPHORE_SURFACE_CTRL_UNREGISTER_WAITER_PARAMS { + NV_DECLARE_ALIGNED(NvU64 index, 8); + NV_DECLARE_ALIGNED(NvU64 waitValue, 8); + NV_DECLARE_ALIGNED(NvU64 notificationHandle, 8); +} NV_SEMAPHORE_SURFACE_CTRL_UNREGISTER_WAITER_PARAMS; + +/* _ctrl00da_h_ */ + diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/common/sdk/nvidia/inc/ctrl/ctrl00f8.h nvidia-open-gpu-kernel-modules-535.161.08/src/common/sdk/nvidia/inc/ctrl/ctrl00f8.h --- nvidia-open-gpu-kernel-modules-525.147.05/src/common/sdk/nvidia/inc/ctrl/ctrl00f8.h 2023-10-25 20:22:10.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/common/sdk/nvidia/inc/ctrl/ctrl00f8.h 2024-03-05 22:15:03.000000000 +0000 @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 2021 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2021-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -27,10 +27,12 @@ // // This file was generated with FINN, an NVIDIA coding tool. -// Source file: ctrl/ctrl00f8.finn +// Source file: ctrl/ctrl00f8.finn // #include "ctrl/ctrlxxxx.h" +#include "ctrl90f1.h" +#include "mmu_fmt_types.h" #define NV00F8_CTRL_CMD(cat,idx) NVXXXX_CTRL_CMD(0x00f8, NV00F8_CTRL_##cat, idx) @@ -88,7 +90,7 @@ typedef struct NV00F8_CTRL_GET_INFO_PARAMS { NV_DECLARE_ALIGNED(NvU64 size, 8); - NvU32 pageSize; + NV_DECLARE_ALIGNED(NvU64 pageSize, 8); NvU32 allocFlags; NV_PHYSICAL_MEMORY_ATTRS physAttrs; } NV00F8_CTRL_GET_INFO_PARAMS; @@ -127,18 +129,18 @@ } NV00F8_CTRL_DESCRIBE_PARAMS; /* - * hMemory [IN] + * hMemory * Physical memory handle to be attached. * - * offset [IN] + * offset * Offset into the fabric object. * Must be physical memory pagesize aligned (at least). * - * mapOffSet [IN] + * mapOffSet * Offset into the physical memory descriptor. * Must be physical memory pagesize aligned. * - * mapLength [IN] + * mapLength * Length of physical memory handle to be mapped. * Must be physical memory pagesize aligned and less than or equal to * fabric alloc size. @@ -215,4 +217,100 @@ NvU16 numDetached; } NV00F8_CTRL_DETACH_MEM_PARAMS; +/* + * NV00F8_CTRL_CMD_GET_NUM_ATTACHED_MEM + * + * Returns number of attached physical memory info to the fabric object in + * a given offset range. + * + * offsetStart [IN] + * Offsets at which memory was attached. + * + * offsetEnd [IN] + * Offsets at which memory was attached. + * + * numMemInfos [OUT] + * Number of memory infos. + */ +#define NV00F8_CTRL_CMD_GET_NUM_ATTACHED_MEM (0xf80105) /* finn: Evaluated from "(FINN_NV_MEMORY_FABRIC_FABRIC_INTERFACE_ID << 8) | NV00F8_CTRL_GET_NUM_ATTACHED_MEM_PARAMS_MESSAGE_ID" */ + +#define NV00F8_CTRL_GET_NUM_ATTACHED_MEM_PARAMS_MESSAGE_ID (0x5U) + +typedef struct NV00F8_CTRL_GET_NUM_ATTACHED_MEM_PARAMS { + NV_DECLARE_ALIGNED(NvU64 offsetStart, 8); + NV_DECLARE_ALIGNED(NvU64 offsetEnd, 8); + NvU16 numMemInfos; +} NV00F8_CTRL_GET_NUM_ATTACHED_MEM_PARAMS; + +/* + * NV00F8_CTRL_CMD_GET_ATTACHED_MEM + * + * Queries attached physical memory info to the fabric object. + * + * offsetStart [IN] + * Offsets at which memory was attached. + * + * numMemInfos [IN] + * Number of memory infos to be filled. + * + * memInfos [IN/OUT] + * Attached memory infos. + * Use must populate a non-zero `hMemory` handle. This handle will be used by + * RM for duping physical memory. + */ +#define NV00F8_CTRL_CMD_GET_ATTACHED_MEM (0xf80106) /* finn: Evaluated from "(FINN_NV_MEMORY_FABRIC_FABRIC_INTERFACE_ID << 8) | NV00F8_CTRL_GET_ATTACHED_MEM_PARAMS_MESSAGE_ID" */ + +#define NV00F8_MAX_ATTACHED_MEM_INFOS 64 + +#define NV00F8_CTRL_GET_ATTACHED_MEM_PARAMS_MESSAGE_ID (0x6U) + +typedef struct NV00F8_CTRL_GET_ATTACHED_MEM_PARAMS { + NV_DECLARE_ALIGNED(NvU64 offsetStart, 8); + NvU16 numMemInfos; + NV_DECLARE_ALIGNED(NV00F8_CTRL_ATTACH_MEM_INFO memInfos[NV00F8_MAX_ATTACHED_MEM_INFOS], 8); +} NV00F8_CTRL_GET_ATTACHED_MEM_PARAMS; + +/* + * NV00F8_CTRL_CMD_GET_PAGE_LEVEL_INFO + * + * Queries page table information for a specific memory fabric address. This + * call is only supported for Verif platforms. This will return the same info + * as NV90F1_CTRL_VASPACE_GET_PAGE_LEVEL_INFO_PARAMS. + * + * offset [IN] + * Memory fabric Offset from the base address for which page table + * information is queried. This offset should be aligned to physical page + * size. + * + * numLevels [OUT] + * Number of levels populated. + * + * levels [OUT] + * Per-level information. + * + * pFmt + * Same as NV90F1_CTRL_VASPACE_GET_PAGE_LEVEL_INFO_PARAMS. + * + * levelFmt + * Same as NV90F1_CTRL_VASPACE_GET_PAGE_LEVEL_INFO_PARAMS. + * + * sublevelFmt + * Same as NV90F1_CTRL_VASPACE_GET_PAGE_LEVEL_INFO_PARAMS. + * + * aperture + * Same as NV90F1_CTRL_VASPACE_GET_PAGE_LEVEL_INFO_PARAMS. + * + * size + * Same as NV90F1_CTRL_VASPACE_GET_PAGE_LEVEL_INFO_PARAMS. + */ +#define NV00F8_CTRL_CMD_GET_PAGE_LEVEL_INFO (0xf80107U) /* finn: Evaluated from "(FINN_NV_MEMORY_FABRIC_FABRIC_INTERFACE_ID << 8) | NV00F8_CTRL_GET_PAGE_LEVEL_INFO_PARAMS_MESSAGE_ID" */ + +#define NV00F8_CTRL_GET_PAGE_LEVEL_INFO_PARAMS_MESSAGE_ID (0x7U) + +typedef struct NV00F8_CTRL_GET_PAGE_LEVEL_INFO_PARAMS { + NV_DECLARE_ALIGNED(NvU64 offset, 8); + NvU32 numLevels; + NV_DECLARE_ALIGNED(NV_CTRL_VASPACE_PAGE_LEVEL levels[GMMU_FMT_MAX_LEVELS], 8); +} NV00F8_CTRL_GET_PAGE_LEVEL_INFO_PARAMS; + /* _ctrl00f8_h_ */ diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/common/sdk/nvidia/inc/ctrl/ctrl00fd.h nvidia-open-gpu-kernel-modules-535.161.08/src/common/sdk/nvidia/inc/ctrl/ctrl00fd.h --- nvidia-open-gpu-kernel-modules-525.147.05/src/common/sdk/nvidia/inc/ctrl/ctrl00fd.h 2023-10-25 20:22:11.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/common/sdk/nvidia/inc/ctrl/ctrl00fd.h 2024-03-05 22:15:03.000000000 +0000 @@ -27,7 +27,7 @@ // // This file was generated with FINN, an NVIDIA coding tool. -// Source file: ctrl/ctrl00fd.finn +// Source file: ctrl/ctrl00fd.finn // #include "ctrl/ctrlxxxx.h" @@ -97,8 +97,7 @@ * Physical memory handle to be attached. * * offset [IN] - * Offset into the MCFLA object. (Must be zero for now, maybe used in future) - * Must be MCFLA pagesize aligned. + * Offset into the MCFLA object. Must be at least physical pagesize aligned. * * mapOffSet [IN] * Offset into the physical memory descriptor. @@ -112,15 +111,10 @@ * flags [IN] * For future use only. Must be zero for now. * - * devDescriptor [IN] - * devDescriptor is a file descriptor for unix RM clients, but a void - * pointer for windows RM clients. It is transparent to RM clients i.e. RM's - * user-mode shim populates this field on behalf of clients. - * * Restrictions: * a. Memory belonging to only NVSwitch P2P supported GPUs * which can do multicast can be attached - * b. Physical memory with 2MB pagesize is allowed + * b. Physical memory with 2MB or 512MB pagesize is allowed * c. Memory of an already attached GPU should not be attached * d. Only vidmem physical memory handle can be attached * @@ -136,7 +130,6 @@ NV_DECLARE_ALIGNED(NvU64 mapOffset, 8); NV_DECLARE_ALIGNED(NvU64 mapLength, 8); NvU32 flags; - NV_DECLARE_ALIGNED(NvU64 devDescriptor, 8); } NV00FD_CTRL_ATTACH_MEM_PARAMS; /* @@ -157,4 +150,56 @@ NV_DECLARE_ALIGNED(NvP64 pOsEvent, 8); } NV00FD_CTRL_REGISTER_EVENT_PARAMS; +/* + * NV00FD_CTRL_CMD_ATTACH_GPU + * + * Attaches GPU to the Multicast FLA object. This step must be done before + * attaching memory to the Multicast FLA object. + * + * hSubdevice [IN] + * Subdevice handle of the owner GPU + * + * flags [IN] + * For future use only. Must be zero for now. + * + * devDescriptor [IN] + * devDescriptor is a file descriptor for unix RM clients, but a void + * pointer for windows RM clients. It is transparent to RM clients i.e. RM's + * user-mode shim populates this field on behalf of clients. + */ +#define NV00FD_CTRL_CMD_ATTACH_GPU (0xfd0104) /* finn: Evaluated from "(FINN_NV_MEMORY_MULTICAST_FABRIC_FABRIC_INTERFACE_ID << 8) | NV00FD_CTRL_ATTACH_GPU_PARAMS_MESSAGE_ID" */ + +#define NV00FD_CTRL_ATTACH_GPU_PARAMS_MESSAGE_ID (0x4U) + +typedef struct NV00FD_CTRL_ATTACH_GPU_PARAMS { + NvHandle hSubdevice; + NvU32 flags; + NV_DECLARE_ALIGNED(NvU64 devDescriptor, 8); +} NV00FD_CTRL_ATTACH_GPU_PARAMS; + +/* + * NV00FD_CTRL_CMD_DETACH_MEM + * + * Detaches the physical memory handle for a given GPU. + * + * hSubdevice [IN] + * Subdevice handle of the GPU for which memory to be detached. + * + * offset [IN] + * Offset into the MCFLA object at which memory to be detached. Same as + * NV00FD_CTRL_CMD_ATTACH_MEM. + * + * flags [IN] + * For future use only. Must be zero for now. + */ +#define NV00FD_CTRL_CMD_DETACH_MEM (0xfd0105) /* finn: Evaluated from "(FINN_NV_MEMORY_MULTICAST_FABRIC_FABRIC_INTERFACE_ID << 8) | NV00FD_CTRL_DETACH_MEM_PARAMS_MESSAGE_ID" */ + +#define NV00FD_CTRL_DETACH_MEM_PARAMS_MESSAGE_ID (0x5U) + +typedef struct NV00FD_CTRL_DETACH_MEM_PARAMS { + NvHandle hSubdevice; + NV_DECLARE_ALIGNED(NvU64 offset, 8); + NvU32 flags; +} NV00FD_CTRL_DETACH_MEM_PARAMS; + /* _ctrl00fd_h_ */ diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/common/sdk/nvidia/inc/ctrl/ctrl00fe.h nvidia-open-gpu-kernel-modules-535.161.08/src/common/sdk/nvidia/inc/ctrl/ctrl00fe.h --- nvidia-open-gpu-kernel-modules-525.147.05/src/common/sdk/nvidia/inc/ctrl/ctrl00fe.h 2023-10-25 20:22:11.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/common/sdk/nvidia/inc/ctrl/ctrl00fe.h 2024-03-05 22:15:03.000000000 +0000 @@ -27,7 +27,7 @@ // // This file was generated with FINN, an NVIDIA coding tool. -// Source file: ctrl/ctrl00fe.finn +// Source file: ctrl/ctrl00fe.finn // #define NV00FE_CTRL_SUBMIT_PAGING_OPERATIONS_FLAG_PAGE_KIND_SOURCE_ALLOCATION 0:0 diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080acr.h nvidia-open-gpu-kernel-modules-535.161.08/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080acr.h --- nvidia-open-gpu-kernel-modules-525.147.05/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080acr.h 2023-10-25 20:22:11.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080acr.h 2024-03-05 22:15:03.000000000 +0000 @@ -27,6 +27,6 @@ // // This file was generated with FINN, an NVIDIA coding tool. -// Source file: ctrl/ctrl2080/ctrl2080acr.finn +// Source file: ctrl/ctrl2080/ctrl2080acr.finn // diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080base.h nvidia-open-gpu-kernel-modules-535.161.08/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080base.h --- nvidia-open-gpu-kernel-modules-525.147.05/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080base.h 2023-10-25 20:22:11.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080base.h 2024-03-05 22:15:03.000000000 +0000 @@ -25,7 +25,7 @@ // // This file was generated with FINN, an NVIDIA coding tool. -// Source file: ctrl/ctrl2080/ctrl2080base.finn +// Source file: ctrl/ctrl2080/ctrl2080base.finn // #include "ctrl/ctrlxxxx.h" @@ -88,9 +88,11 @@ #define NV2080_CTRL_FLA (0x35) #define NV2080_CTRL_GSP (0x36) #define NV2080_CTRL_NNE (0x37) +#define NV2080_CTRL_NNE_LEGACY_NON_PRIVILEGED (0xb7) /* finn: Evaluated from "(NV2080_CTRL_NNE | NVxxxx_CTRL_LEGACY_NON_PRIVILEGED)" */ #define NV2080_CTRL_GRMGR (0x38) #define NV2080_CTRL_UCODE_FUZZER (0x39) #define NV2080_CTRL_DMABUF (0x3A) +#define NV2080_CTRL_BIF (0x3B) // per-OS categories start at highest category and work backwards #define NV2080_CTRL_OS_WINDOWS (0x3F) diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080bios.h nvidia-open-gpu-kernel-modules-535.161.08/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080bios.h --- nvidia-open-gpu-kernel-modules-525.147.05/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080bios.h 2023-10-25 20:22:11.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080bios.h 2024-03-05 22:15:03.000000000 +0000 @@ -27,7 +27,7 @@ // // This file was generated with FINN, an NVIDIA coding tool. -// Source file: ctrl/ctrl2080/ctrl2080bios.finn +// Source file: ctrl/ctrl2080/ctrl2080bios.finn // #include "ctrl/ctrl2080/ctrl2080base.h" @@ -36,10 +36,7 @@ -typedef struct NV2080_CTRL_BIOS_INFO { - NvU32 index; - NvU32 data; -} NV2080_CTRL_BIOS_INFO; +typedef NVXXXX_CTRL_XXX_INFO NV2080_CTRL_BIOS_INFO; /* Maximum number of bios infos that can be queried at once */ #define NV2080_CTRL_BIOS_INFO_MAX_SIZE (0x0000000F) diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080boardobj.h nvidia-open-gpu-kernel-modules-535.161.08/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080boardobj.h --- nvidia-open-gpu-kernel-modules-525.147.05/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080boardobj.h 2023-10-25 20:22:11.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080boardobj.h 2024-03-05 22:15:04.000000000 +0000 @@ -25,7 +25,7 @@ // // This file was generated with FINN, an NVIDIA coding tool. -// Source file: ctrl/ctrl2080/ctrl2080boardobj.finn +// Source file: ctrl/ctrl2080/ctrl2080boardobj.finn // diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080boardobjgrpclasses.h nvidia-open-gpu-kernel-modules-535.161.08/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080boardobjgrpclasses.h --- nvidia-open-gpu-kernel-modules-525.147.05/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080boardobjgrpclasses.h 2023-10-25 20:22:11.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080boardobjgrpclasses.h 2024-03-05 22:15:04.000000000 +0000 @@ -25,7 +25,7 @@ // // This file was generated with FINN, an NVIDIA coding tool. -// Source file: ctrl/ctrl2080/ctrl2080boardobjgrpclasses.finn +// Source file: ctrl/ctrl2080/ctrl2080boardobjgrpclasses.finn // diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080bus.h nvidia-open-gpu-kernel-modules-535.161.08/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080bus.h --- nvidia-open-gpu-kernel-modules-525.147.05/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080bus.h 2023-10-25 20:22:11.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080bus.h 2024-03-05 22:15:04.000000000 +0000 @@ -27,7 +27,7 @@ // // This file was generated with FINN, an NVIDIA coding tool. -// Source file: ctrl/ctrl2080/ctrl2080bus.finn +// Source file: ctrl/ctrl2080/ctrl2080bus.finn // #include "nvcfg_sdk.h" @@ -244,10 +244,7 @@ * */ -typedef struct NV2080_CTRL_BUS_INFO { - NvU32 index; - NvU32 data; -} NV2080_CTRL_BUS_INFO; +typedef NVXXXX_CTRL_XXX_INFO NV2080_CTRL_BUS_INFO; /* valid bus info index values */ @@ -1397,10 +1394,14 @@ * NV_OK and bIsLinkUp is NV_TRUE. * nrLinks[OUT] * Total number of C2C links that are up. + * maxNrLinks[OUT] + * Maximum number of C2C links that are supported. * linkMask[OUT] * Bitmask of the C2C links present and up. * perLinkBwMBps[OUT] * Theoretical per link bandwidth in MBps. + * perLinkLaneWidth[OUT] + * Lane width per link. * remoteType[OUT] * Type of the device connected to the remote end of the C2C link. * Valid values are : @@ -1418,6 +1419,11 @@ * NV2080_CTRL_BUS_GET_C2C_INFO_REMOTE_TYPE_CPU - connected to a CPU */ + /* + * in either self-hosted mode or + * externally-hostedmode. + */ + #define NV2080_CTRL_CMD_BUS_GET_C2C_INFO (0x2080182b) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_BUS_INTERFACE_ID << 8) | NV2080_CTRL_CMD_BUS_GET_C2C_INFO_PARAMS_MESSAGE_ID" */ @@ -1427,8 +1433,10 @@ typedef struct NV2080_CTRL_CMD_BUS_GET_C2C_INFO_PARAMS { NvBool bIsLinkUp; NvU32 nrLinks; + NvU32 maxNrLinks; NvU32 linkMask; NvU32 perLinkBwMBps; + NvU32 perLinkLaneWidth; NvU32 remoteType; } NV2080_CTRL_CMD_BUS_GET_C2C_INFO_PARAMS; @@ -1542,6 +1550,7 @@ typedef struct NV2080_CTRL_BUS_SET_P2P_MAPPING_PARAMS { NvU32 connectionType; NvU32 peerId; + NvBool bEgmPeer; NvBool bSpaAccessOnly; NvBool bUseUuid; NvU32 remoteGpuId; diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080ce.h nvidia-open-gpu-kernel-modules-535.161.08/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080ce.h --- nvidia-open-gpu-kernel-modules-525.147.05/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080ce.h 2023-10-25 20:22:12.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080ce.h 2024-03-05 22:15:04.000000000 +0000 @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 2014-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2014-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -27,7 +27,7 @@ // // This file was generated with FINN, an NVIDIA coding tool. -// Source file: ctrl/ctrl2080/ctrl2080ce.finn +// Source file: ctrl/ctrl2080/ctrl2080ce.finn // @@ -98,8 +98,7 @@ #define NV2080_CTRL_CE_CAPS_CE_BL_SIZE_GT_64K_SUPPORTED 0:0x80 #define NV2080_CTRL_CE_CAPS_CE_SUPPORTS_NONPIPELINED_BL 1:0x01 #define NV2080_CTRL_CE_CAPS_CE_SUPPORTS_PIPELINED_BL 1:0x02 - - +#define NV2080_CTRL_CE_CAPS_CE_CC_SECURE 1:0x04 /* * NV2080_CTRL_CE_CAPS_CE_GRCE @@ -133,10 +132,11 @@ * * NV2080_CTRL_CE_CAPS_CE_SUPPORTS_PIPELINED_BL * Set if the CE supports pipelined Block Linear + * + * NV2080_CTRL_CE_CAPS_CE_CC_SECURE + * Set if the CE is capable of encryption/decryption */ - - /* * NV2080_CTRL_CMD_CE_GET_CE_PCE_MASK * @@ -228,6 +228,8 @@ * NV_ERR_GENERIC */ + + #define NV2080_CTRL_CMD_CE_UPDATE_PCE_LCE_MAPPINGS (0x20802a05) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_CE_INTERFACE_ID << 8) | NV2080_CTRL_CE_UPDATE_PCE_LCE_MAPPINGS_PARAMS_MESSAGE_ID" */ #define NV2080_CTRL_CE_UPDATE_PCE_LCE_MAPPINGS_PARAMS_MESSAGE_ID (0x5U) @@ -269,7 +271,11 @@ * */ -#define NV2080_CTRL_CMD_CE_GET_PHYSICAL_CAPS (0x20802a07) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_CE_INTERFACE_ID << 8) | 0x7" */ +#define NV2080_CTRL_CMD_CE_GET_PHYSICAL_CAPS (0x20802a07) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_CE_INTERFACE_ID << 8) | NV2080_CTRL_CE_GET_PHYSICAL_CAPS_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_CE_GET_PHYSICAL_CAPS_PARAMS_MESSAGE_ID (0x7U) + +typedef NV2080_CTRL_CE_GET_CAPS_V2_PARAMS NV2080_CTRL_CE_GET_PHYSICAL_CAPS_PARAMS; #define NV2080_CTRL_CE_GET_FAULT_METHOD_BUFFER_SIZE_PARAMS_MESSAGE_ID (0x8U) @@ -292,7 +298,7 @@ #define NV2080_CTRL_CMD_CE_GET_HUB_PCE_MASK (0x20802a09) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_CE_INTERFACE_ID << 8) | NV2080_CTRL_CE_GET_HUB_PCE_MASK_PARAMS_MESSAGE_ID" */ -#define NV2080_CTRL_CE_MAX_HSHUBS 5 +#define NV2080_CTRL_CE_MAX_HSHUBS 32 #define NV2080_CTRL_CE_GET_HUB_PCE_MASK_PARAMS_MESSAGE_ID (0x9U) @@ -324,6 +330,12 @@ NvU32 present; } NV2080_CTRL_CE_GET_ALL_CAPS_PARAMS; -#define NV2080_CTRL_CMD_CE_GET_ALL_PHYSICAL_CAPS (0x20802a0b) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_CE_INTERFACE_ID << 8) | 0xb" */ +#define NV2080_CTRL_CMD_CE_GET_ALL_PHYSICAL_CAPS (0x20802a0b) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_CE_INTERFACE_ID << 8) | NV2080_CTRL_CE_GET_ALL_PHYSICAL_CAPS_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_CE_GET_ALL_PHYSICAL_CAPS_PARAMS_MESSAGE_ID (0xbU) + +typedef NV2080_CTRL_CE_GET_ALL_CAPS_PARAMS NV2080_CTRL_CE_GET_ALL_PHYSICAL_CAPS_PARAMS; + + /* _ctrl2080ce_h_ */ diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080cipher.h nvidia-open-gpu-kernel-modules-535.161.08/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080cipher.h --- nvidia-open-gpu-kernel-modules-525.147.05/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080cipher.h 2023-10-25 20:22:12.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080cipher.h 2024-03-05 22:15:04.000000000 +0000 @@ -27,6 +27,6 @@ // // This file was generated with FINN, an NVIDIA coding tool. -// Source file: ctrl/ctrl2080/ctrl2080cipher.finn +// Source file: ctrl/ctrl2080/ctrl2080cipher.finn // diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080clk.h nvidia-open-gpu-kernel-modules-535.161.08/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080clk.h --- nvidia-open-gpu-kernel-modules-525.147.05/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080clk.h 2023-10-25 20:22:12.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080clk.h 2024-03-05 22:15:04.000000000 +0000 @@ -25,7 +25,7 @@ // // This file was generated with FINN, an NVIDIA coding tool. -// Source file: ctrl/ctrl2080/ctrl2080clk.finn +// Source file: ctrl/ctrl2080/ctrl2080clk.finn // diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080clkavfs.h nvidia-open-gpu-kernel-modules-535.161.08/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080clkavfs.h --- nvidia-open-gpu-kernel-modules-525.147.05/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080clkavfs.h 2023-10-25 20:22:12.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080clkavfs.h 2024-03-05 22:15:04.000000000 +0000 @@ -25,7 +25,7 @@ // // This file was generated with FINN, an NVIDIA coding tool. -// Source file: ctrl/ctrl2080/ctrl2080clkavfs.finn +// Source file: ctrl/ctrl2080/ctrl2080clkavfs.finn // diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080dma.h nvidia-open-gpu-kernel-modules-535.161.08/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080dma.h --- nvidia-open-gpu-kernel-modules-525.147.05/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080dma.h 2023-10-25 20:22:12.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080dma.h 2024-03-05 22:15:04.000000000 +0000 @@ -27,7 +27,7 @@ // // This file was generated with FINN, an NVIDIA coding tool. -// Source file: ctrl/ctrl2080/ctrl2080dma.finn +// Source file: ctrl/ctrl2080/ctrl2080dma.finn // #include "ctrl/ctrl2080/ctrl2080base.h" @@ -114,10 +114,7 @@ * NV2080_CTRL_DMA_INFO_INDEX_SYSTEM_ADDRESS_SIZE * This index can be used to request the system address size in bits. */ -typedef struct NV2080_CTRL_DMA_INFO { - NvU32 index; - NvU32 data; -} NV2080_CTRL_DMA_INFO; +typedef NVXXXX_CTRL_XXX_INFO NV2080_CTRL_DMA_INFO; /* valid dma info index values */ #define NV2080_CTRL_DMA_INFO_INDEX_SYSTEM_ADDRESS_SIZE (0x000000000) diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080dmabuf.h nvidia-open-gpu-kernel-modules-535.161.08/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080dmabuf.h --- nvidia-open-gpu-kernel-modules-525.147.05/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080dmabuf.h 2023-10-25 20:22:12.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080dmabuf.h 2024-03-05 22:15:05.000000000 +0000 @@ -27,7 +27,7 @@ // // This file was generated with FINN, an NVIDIA coding tool. -// Source file: ctrl/ctrl2080/ctrl2080dmabuf.finn +// Source file: ctrl/ctrl2080/ctrl2080dmabuf.finn // diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080ecc.h nvidia-open-gpu-kernel-modules-535.161.08/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080ecc.h --- nvidia-open-gpu-kernel-modules-525.147.05/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080ecc.h 2023-10-25 20:22:12.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080ecc.h 2024-03-05 22:15:05.000000000 +0000 @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 2017-2021 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2017-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -27,7 +27,7 @@ // // This file was generated with FINN, an NVIDIA coding tool. -// Source file: ctrl/ctrl2080/ctrl2080ecc.finn +// Source file: ctrl/ctrl2080/ctrl2080ecc.finn // #include "ctrl/ctrl2080/ctrl2080base.h" @@ -60,4 +60,80 @@ NV_DECLARE_ALIGNED(NvU64 dramCorrectedTotalCounts, 8); NV_DECLARE_ALIGNED(NvU64 dramUncorrectedTotalCounts, 8); } NV2080_CTRL_ECC_GET_CLIENT_EXPOSED_COUNTERS_PARAMS; + +#define NV2080_CTRL_CMD_ECC_GET_ECI_COUNTERS (0x20803401U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_ECC_INTERFACE_ID << 8) | NV2080_CTRL_ECC_GET_ECI_COUNTERS_PARAMS_MESSAGE_ID" */ + +/* + * NV2080_CTRL_ECC_GET_ECI_COUNTERS_PARAMS + * + * sramParityUncorrectedUnique [out] + * sramSecDedUncorrectedUnique [out] + * sramCorrectedTotal [out] + * dramUncorrectedTotal [out] + * dramCorrectedTotal [out] + * Aggregate error counts for SRAM and DRAM. + * + * lastClearedTimestamp [out] + * unix-epoch based timestamp. These fields indicate when the error counters + * were last cleared by the user. + * + * sramBucketL2 [out] + * sramBucketSM [out] + * sramBucketPcie [out] + * sramBucketFirmware [out] + * sramBucketOther [out] + * Aggregate unique uncorrctable error counts for SRAM buckets. + * + * sramErrorThresholdExceeded [out] + * Boolean flag which is set if SRAM error threshold was exceeded + */ + +#define NV2080_CTRL_ECC_GET_ECI_COUNTERS_PARAMS_MESSAGE_ID (0x1U) + +typedef struct NV2080_CTRL_ECC_GET_ECI_COUNTERS_PARAMS { + NV_DECLARE_ALIGNED(NvU64 sramParityUncorrectedUnique, 8); + NV_DECLARE_ALIGNED(NvU64 sramSecDedUncorrectedUnique, 8); + NV_DECLARE_ALIGNED(NvU64 sramCorrectedTotal, 8); + NV_DECLARE_ALIGNED(NvU64 dramUncorrectedTotal, 8); + NV_DECLARE_ALIGNED(NvU64 dramCorrectedTotal, 8); + + NvU32 lastClearedTimestamp; + + NV_DECLARE_ALIGNED(NvU64 sramBucketL2, 8); + NV_DECLARE_ALIGNED(NvU64 sramBucketSM, 8); + NV_DECLARE_ALIGNED(NvU64 sramBucketPcie, 8); + NV_DECLARE_ALIGNED(NvU64 sramBucketFirmware, 8); + NV_DECLARE_ALIGNED(NvU64 sramBucketOther, 8); + + NvBool sramErrorThresholdExceeded; +} NV2080_CTRL_ECC_GET_ECI_COUNTERS_PARAMS; + +/* + * NV2080_CTRL_ECC_GET_VOLATILE_COUNTS_PARAMS + * + * Reports count of volatile errors + * + * sramCorUni [out]: + * Unique correctable SRAM error count + * sramUncParityUni [out]: + * Unique uncorrectable SRAM parity error count + * sramUncSecDedUni [out]: + * Unique uncorrectable SRAM SEC-DED error count + * dramCorTot [out]: + * Total correctable DRAM error count + * dramUncTot [out]: + * total uncorrectable DRAM error count + */ +#define NV2080_CTRL_CMD_ECC_GET_VOLATILE_COUNTS (0x20803402U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_ECC_INTERFACE_ID << 8) | NV2080_CTRL_ECC_GET_VOLATILE_COUNTS_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_ECC_GET_VOLATILE_COUNTS_PARAMS_MESSAGE_ID (0x2U) + +typedef struct NV2080_CTRL_ECC_GET_VOLATILE_COUNTS_PARAMS { + NV_DECLARE_ALIGNED(NvU64 sramCorUni, 8); + NV_DECLARE_ALIGNED(NvU64 sramUncParityUni, 8); + NV_DECLARE_ALIGNED(NvU64 sramUncSecDedUni, 8); + NV_DECLARE_ALIGNED(NvU64 dramCorTot, 8); + NV_DECLARE_ALIGNED(NvU64 dramUncTot, 8); +} NV2080_CTRL_ECC_GET_VOLATILE_COUNTS_PARAMS; + /* _ctrl2080ecc_h_ */ diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080event.h nvidia-open-gpu-kernel-modules-535.161.08/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080event.h --- nvidia-open-gpu-kernel-modules-525.147.05/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080event.h 2023-10-25 20:22:12.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080event.h 2024-03-05 22:15:05.000000000 +0000 @@ -27,7 +27,7 @@ // // This file was generated with FINN, an NVIDIA coding tool. -// Source file: ctrl/ctrl2080/ctrl2080event.finn +// Source file: ctrl/ctrl2080/ctrl2080event.finn // #include "ctrl/ctrl2080/ctrl2080base.h" @@ -266,6 +266,7 @@ NvBool isSemaMemValidationEnabled; } NV2080_CTRL_EVENT_SET_SEMA_MEM_VALIDATION_PARAMS; + /* * NV2080_CTRL_CMD_EVENT_SET_TRIGGER_FIFO * diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080fan.h nvidia-open-gpu-kernel-modules-535.161.08/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080fan.h --- nvidia-open-gpu-kernel-modules-525.147.05/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080fan.h 2023-10-25 20:22:12.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080fan.h 2024-03-05 22:15:05.000000000 +0000 @@ -27,6 +27,6 @@ // // This file was generated with FINN, an NVIDIA coding tool. -// Source file: ctrl/ctrl2080/ctrl2080fan.finn +// Source file: ctrl/ctrl2080/ctrl2080fan.finn // diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080fb.h nvidia-open-gpu-kernel-modules-535.161.08/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080fb.h --- nvidia-open-gpu-kernel-modules-525.147.05/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080fb.h 2023-10-25 20:22:13.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080fb.h 2024-03-05 22:15:05.000000000 +0000 @@ -27,7 +27,7 @@ // // This file was generated with FINN, an NVIDIA coding tool. -// Source file: ctrl/ctrl2080/ctrl2080fb.finn +// Source file: ctrl/ctrl2080/ctrl2080fb.finn // #include "ctrl/ctrl2080/ctrl2080base.h" @@ -267,10 +267,7 @@ * Returns the ECC status size (corresponds to subpartitions or channels * depending on architecture/memory type). */ -typedef struct NV2080_CTRL_FB_INFO { - NvU32 index; - NvU32 data; -} NV2080_CTRL_FB_INFO; +typedef NVXXXX_CTRL_XXX_INFO NV2080_CTRL_FB_INFO; /* valid fb info index values */ #define NV2080_CTRL_FB_INFO_INDEX_TILE_REGION_COUNT (0x00000000U) // Deprecated @@ -423,27 +420,6 @@ } NV2080_CTRL_FB_GET_INFO_V2_PARAMS; /* - * NV2080_CTRL_CMD_FB_GET_TILE_ADDRESS_INFO - * - * This command returns tile addressing information. - * - * StartAddr - * This parameter returns BAR1 plus the size of the local FB. - * SpaceSize - * This parameter returns the BAR1 aperture size less the size of the - * local FB. - * - * Note that both parameters will contain zero if there is no system tile - * address space. - */ -#define NV2080_CTRL_CMD_FB_GET_TILE_ADDRESS_INFO (0x20801302U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FB_INTERFACE_ID << 8) | 0x2" */ - -typedef struct NV2080_CTRL_FB_GET_SYSTEM_TILE_ADDRESS_SPACE_INFO { - NV_DECLARE_ALIGNED(NvU64 StartAddr, 8); - NV_DECLARE_ALIGNED(NvU64 SpaceSize, 8); -} NV2080_CTRL_FB_GET_SYSTEM_TILE_ADDRESS_SPACE_INFO; - -/* * NV2080_CTRL_CMD_FB_GET_BAR1_OFFSET * * This command returns the GPU virtual address of a bar1 @@ -540,53 +516,8 @@ } NV2080_CTRL_FB_GET_CALIBRATION_LOCK_FAILED_PARAMS; /* valid flags parameter values */ -#define NV2080_CTRL_CMD_FB_GET_CAL_FLAG_NONE (0x00000000U) -#define NV2080_CTRL_CMD_FB_GET_CAL_FLAG_RESET (0x00000001U) - -/* - * NV2080_CTRL_CMD_FB_SET_SCANOUT_COMPACTION_ALLOWED - * - * This command specifies to RM if scanout compaction feature is allowed or - * not in the current configuration. In hybrid mode when dGPU is rendering the - * image, the dGPU blit to the scanout surface happens without mGPU's - * knowledge (directly to system memory), which results in stale compacted - * data resulting in corruption. - * - * This control call can be used to disable the compaction whenever the KMD - * (client) is switching to the pref mode in Hybrid i.e., whenever there is a - * possibility of dGPU doing a blit to mGpu scanout surface. Compaction can - * be enabled when system is back in hybrid power mode as mGpu will be - * rendering the image. - * - * allowCompaction - * This parameter specifies if the display compaction feature is allowed - * or not allowed. - * immediate - * This parameter specifies whether compaction has to be enabled or - * disabled immediately (based on the value of allowCompaction field) or - * during the next modeset. - * - * Possible status values returned are: - * NV_OK - * NVOS_STATUS_INVALID_PARAM_STRUCT - * NVOS_STATUS_NOT_SUPPORTED - * NV_ERR_INVALID_ARGUMENT - */ - -#define NV2080_CTRL_CMD_FB_SET_SCANOUT_COMPACTION_ALLOWED (0x2080130dU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FB_INTERFACE_ID << 8) | 0xD" */ // Deprecated, removed form RM - -typedef struct NV2080_CTRL_FB_SET_SCANOUT_COMPACTION_ALLOWED_PARAMS { - NvU32 allowCompaction; - NvU32 immediate; -} NV2080_CTRL_FB_SET_SCANOUT_COMPACTION_ALLOWED_PARAMS; - -/* valid allowCompaction values */ -#define NV2080_CTRL_CMD_FB_SET_SCANOUT_COMPACTION_ALLOW (0x00000001U) -#define NV2080_CTRL_CMD_FB_SET_SCANOUT_COMPACTION_DISALLOW (0x00000000U) - -/* valid immediate values */ -#define NV2080_CTRL_CMD_FB_SET_SCANOUT_COMPACTION_IMMEDIATE (000000001U) -#define NV2080_CTRL_CMD_FB_SET_SCANOUT_COMPACTION_NOT_IMMEDIATE (000000000U) +#define NV2080_CTRL_CMD_FB_GET_CAL_FLAG_NONE (0x00000000U) +#define NV2080_CTRL_CMD_FB_GET_CAL_FLAG_RESET (0x00000001U) /* * NV2080_CTRL_CMD_FB_FLUSH_GPU_CACHE @@ -631,9 +562,9 @@ * supports it. Use this call if you want to flush a single allocation and * you have a memory object describing the physical memory. */ -#define NV2080_CTRL_CMD_FB_FLUSH_GPU_CACHE (0x2080130eU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FB_INTERFACE_ID << 8) | NV2080_CTRL_FB_FLUSH_GPU_CACHE_PARAMS_MESSAGE_ID" */ +#define NV2080_CTRL_CMD_FB_FLUSH_GPU_CACHE (0x2080130eU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FB_INTERFACE_ID << 8) | NV2080_CTRL_FB_FLUSH_GPU_CACHE_PARAMS_MESSAGE_ID" */ -#define NV2080_CTRL_FB_FLUSH_GPU_CACHE_MAX_ADDRESSES 500U +#define NV2080_CTRL_FB_FLUSH_GPU_CACHE_MAX_ADDRESSES 500U #define NV2080_CTRL_FB_FLUSH_GPU_CACHE_PARAMS_MESSAGE_ID (0xEU) @@ -686,11 +617,11 @@ /* valid values for allocPolicy */ #define NV2080_CTRL_FB_GPU_CACHE_ALLOC_POLICY_READS 0:0 -#define NV2080_CTRL_FB_GPU_CACHE_ALLOC_POLICY_READS_NO (0x00000000U) -#define NV2080_CTRL_FB_GPU_CACHE_ALLOC_POLICY_READS_YES (0x00000001U) +#define NV2080_CTRL_FB_GPU_CACHE_ALLOC_POLICY_READS_NO (0x00000000U) +#define NV2080_CTRL_FB_GPU_CACHE_ALLOC_POLICY_READS_YES (0x00000001U) #define NV2080_CTRL_FB_GPU_CACHE_ALLOC_POLICY_WRITES 1:1 -#define NV2080_CTRL_FB_GPU_CACHE_ALLOC_POLICY_WRITES_NO (0x00000000U) -#define NV2080_CTRL_FB_GPU_CACHE_ALLOC_POLICY_WRITES_YES (0x00000001U) +#define NV2080_CTRL_FB_GPU_CACHE_ALLOC_POLICY_WRITES_NO (0x00000000U) +#define NV2080_CTRL_FB_GPU_CACHE_ALLOC_POLICY_WRITES_YES (0x00000001U) /* @@ -707,7 +638,11 @@ * NV_ERR_NOT_SUPPORTED * NV_ERR_INVALID_ARGUMENT */ -#define NV2080_CTRL_CMD_FB_SET_GPU_CACHE_ALLOC_POLICY (0x2080130fU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FB_INTERFACE_ID << 8) | 0xF" */ +#define NV2080_CTRL_CMD_FB_SET_GPU_CACHE_ALLOC_POLICY (0x2080130fU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FB_INTERFACE_ID << 8) | NV2080_CTRL_FB_SET_GPU_CACHE_ALLOC_POLICY_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_FB_SET_GPU_CACHE_ALLOC_POLICY_PARAMS_MESSAGE_ID (0xFU) + +typedef NV2080_CTRL_FB_GPU_CACHE_ALLOC_POLICY_PARAMS NV2080_CTRL_FB_SET_GPU_CACHE_ALLOC_POLICY_PARAMS; /* * NV2080_CTRL_FB_GPU_CACHE_ALLOC_POLICY_V2_PARAM @@ -773,7 +708,11 @@ * NV_ERR_NOT_SUPPORTED * NV_ERR_INVALID_ARGUMENT */ -#define NV2080_CTRL_CMD_FB_SET_GPU_CACHE_ALLOC_POLICY_V2 (0x20801318U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FB_INTERFACE_ID << 8) | 0x18" */ +#define NV2080_CTRL_CMD_FB_SET_GPU_CACHE_ALLOC_POLICY_V2 (0x20801318U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FB_INTERFACE_ID << 8) | NV2080_CTRL_FB_SET_GPU_CACHE_ALLOC_POLICY_V2_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_FB_SET_GPU_CACHE_ALLOC_POLICY_V2_PARAMS_MESSAGE_ID (0x18U) + +typedef NV2080_CTRL_FB_GPU_CACHE_ALLOC_POLICY_V2_PARAMS NV2080_CTRL_FB_SET_GPU_CACHE_ALLOC_POLICY_V2_PARAMS; /* * NV2080_CTRL_CMD_FB_GET_GPU_CACHE_ALLOC_POLICY (deprecated; use NV2080_CTRL_CMD_FB_GET_GPU_CACHE_ALLOC_POLICY_V2 instead) @@ -786,7 +725,11 @@ * NV_ERR_NOT_SUPPORTED * NV_ERR_INVALID_ARGUMENT */ -#define NV2080_CTRL_CMD_FB_GET_GPU_CACHE_ALLOC_POLICY (0x20801312U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FB_INTERFACE_ID << 8) | 0x12" */ +#define NV2080_CTRL_CMD_FB_GET_GPU_CACHE_ALLOC_POLICY (0x20801312U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FB_INTERFACE_ID << 8) | NV2080_CTRL_FB_GET_GPU_CACHE_ALLOC_POLICY_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_FB_GET_GPU_CACHE_ALLOC_POLICY_PARAMS_MESSAGE_ID (0x12U) + +typedef NV2080_CTRL_FB_GPU_CACHE_ALLOC_POLICY_PARAMS NV2080_CTRL_FB_GET_GPU_CACHE_ALLOC_POLICY_PARAMS; /* * NV2080_CTRL_CMD_FB_GET_GPU_CACHE_ALLOC_POLICY_V2 @@ -799,7 +742,11 @@ * NV_ERR_NOT_SUPPORTED * NV_ERR_INVALID_ARGUMENT */ -#define NV2080_CTRL_CMD_FB_GET_GPU_CACHE_ALLOC_POLICY_V2 (0x20801319U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FB_INTERFACE_ID << 8) | 0x19" */ +#define NV2080_CTRL_CMD_FB_GET_GPU_CACHE_ALLOC_POLICY_V2 (0x20801319U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FB_INTERFACE_ID << 8) | NV2080_CTRL_FB_GET_GPU_CACHE_ALLOC_POLICY_V2_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_FB_GET_GPU_CACHE_ALLOC_POLICY_V2_PARAMS_MESSAGE_ID (0x19U) + +typedef NV2080_CTRL_FB_GPU_CACHE_ALLOC_POLICY_V2_PARAMS NV2080_CTRL_FB_GET_GPU_CACHE_ALLOC_POLICY_V2_PARAMS; /* @@ -875,7 +822,7 @@ * NV_OK * NV_ERR_INVALID_ARGUMENT */ -#define NV2080_CTRL_CMD_FB_IS_KIND (0x20801313U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FB_INTERFACE_ID << 8) | NV2080_CTRL_FB_IS_KIND_PARAMS_MESSAGE_ID" */ +#define NV2080_CTRL_CMD_FB_IS_KIND (0x20801313U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FB_INTERFACE_ID << 8) | NV2080_CTRL_FB_IS_KIND_PARAMS_MESSAGE_ID" */ #define NV2080_CTRL_FB_IS_KIND_PARAMS_MESSAGE_ID (0x13U) @@ -1603,239 +1550,6 @@ } NV2080_CTRL_CMD_FB_COMPBITCOPY_WRITE_COMPBITS64KB_PARAMS; /*! - * NV2080_CTRL_CMD_FB_COMPBITCOPY_GET_COMPBITSPS < Deprecated > - * - * The PS (Performance Path, or Optimized path, or Per Slice version) - * of PutCompBits. - * - * @params[out] NvU32 *fcbits; - * Buffer to receive Fast Clear Bits. - * @params[out] NvU32 *compbits; - * Buffer to receive Compression Bits. - * @params[out] NvU32 *compCacheLine; - * Buffer to receive Comp Cache Line data. - * @params[in] NvU64 dataPhysicalStart; - * Start Address of Data - * @params[in] NvU64 surfaceOffset; - * Offset in the surface - * @params[in] NvU32 comptagLine; - * Compression Tag Line Number - * @params[in] NvU32 ROPTile_offset; - * Offset in the surface of the ROP tile. - * @params[in] NvBool upper64KBCompbitSel; - * Selects Upper or Lower 64K - * @params[in] NvBool getFcBits; - * Indicates if fast clear bits should be returned. - * @params[in] NvP64 derivedParams - * Actually a CompBitDerivedParams structure. - * - * Possible status values returned are: - * NV_OK - * NV_ERR_NOT_SUPPORTED - */ -#define NV2080_CTRL_CMD_FB_COMPBITCOPY_GET_COMPBITSPS (0x2080132eU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FB_INTERFACE_ID << 8) | 0x2E" */ - -typedef struct NV2080_CTRL_CMD_FB_COMPBITCOPY_GET_COMPBITSPS_PARAMS { - NV_DECLARE_ALIGNED(NvU32 *fcbits, 8); - NV_DECLARE_ALIGNED(NvU32 *compbits, 8); - NV_DECLARE_ALIGNED(NvU32 *compCacheLine, 8); - NV_DECLARE_ALIGNED(NvU64 dataPhysicalStart, 8); - NV_DECLARE_ALIGNED(NvU64 surfaceOffset, 8); - NvU32 comptagLine; - NvU32 ROPTile_offset; - NvBool upper64KBCompbitSel; - NvBool getFcBits; - NV_DECLARE_ALIGNED(NvP64 derivedParams, 8); -} NV2080_CTRL_CMD_FB_COMPBITCOPY_GET_COMPBITSPS_PARAMS; - -/*! - * NV2080_CTRL_CMD_FB_COMPBITCOPY_PUT_COMPBITSPS < Deprecated > - * - * The PS (Performance Path, or Optimized path, or Per Slice version) - * of GetCompBits. - * - * @params[in] NvU32 fcbits; - * Buffer with Fast Clear Bits to write. - * @params[in] NvU32 compbits; - * Buffer to receive Compression Bits. - * @params[in] NvBool writeFc - * Indicates of Fast Clear Bits should be written. - * @params[in] NvU32 *compCacheLine; - * Buffer to receive Comp Cache Line data. - * @params[in] NvU64 dataPhysicalStart; - * Start Address of Data - * @params[in] NvU64 surfaceOffset; - * Offset in the surface - * @params[in] NvU32 comptagLine; - * Compression Tag Line Number - * @params[in] NvU32 ROPTile_offset; - * Offset in the surface of the ROP tile. - * @params[in] NvBool upper64KBCompbitSel; - * Selects Upper or Lower 64K - * @params[in] NvP64 derivedParams - * Actually a CompBitDerivedParams structure. - * - * Possible status values returned are: - * NV_OK - * NV_ERR_NOT_SUPPORTED - */ -#define NV2080_CTRL_CMD_FB_COMPBITCOPY_PUT_COMPBITSPS (0x2080132fU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FB_INTERFACE_ID << 8) | 0x2F" */ - -typedef struct NV2080_CTRL_CMD_FB_COMPBITCOPY_PUT_COMPBITSPS_PARAMS { - NvU32 fcbits; - NvU32 compbits; - NvBool writeFc; - NV_DECLARE_ALIGNED(NvU32 *compCacheLine, 8); - NV_DECLARE_ALIGNED(NvU64 dataPhysicalStart, 8); - NV_DECLARE_ALIGNED(NvU64 surfaceOffset, 8); - NvU32 comptagLine; - NvU32 ROPTile_offset; - NvBool upper64KBCompbitSel; - NV_DECLARE_ALIGNED(NvP64 derivedParams, 8); -} NV2080_CTRL_CMD_FB_COMPBITCOPY_PUT_COMPBITSPS_PARAMS; - -/*! - * NV2080_CTRL_CMD_FB_COMPBITCOPY_READ_COMPCACHELINEPS < Deprecated > - * - * The PS (Performance Path, or Optimized path, or Per Slice version) - * of ReadCompCacheLine. - * - * @paramsNvU32 *compCacheLine; - * Buffer for Comp Cache Line Read - * @paramsNvU32 comptagLine; - * Comp Tag Line Number to read - * @paramsNvU32 partition; - * FB Partition of the desired Comp Cache Line - * @paramsNvU32 slice; - * Slice of the desired Comp Cache Line - * - * Possible status values returned are: - * NV_OK - * NV_ERR_NOT_SUPPORTED - */ -#define NV2080_CTRL_CMD_FB_COMPBITCOPY_READ_COMPCACHELINEPS (0x20801330U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FB_INTERFACE_ID << 8) | 0x30" */ - -typedef struct NV2080_CTRL_CMD_FB_COMPBITCOPY_READ_COMPCACHELINEPS_PARAMS { - NV_DECLARE_ALIGNED(NvU32 *compCacheLine, 8); - NvU32 comptagLine; - NvU32 partition; - NvU32 slice; -} NV2080_CTRL_CMD_FB_COMPBITCOPY_READ_COMPCACHELINEPS_PARAMS; - -/*! - * NV2080_CTRL_CMD_FB_COMPBITCOPY_WRITE_COMPCACHELINEPS < Deprecated > - * - * The PS (Performance Path, or Optimized path, or Per Slice version) - * of WriteCompCacheLine. - * - * @params[in] NvU32 *compCacheLine; - * Buffer for Comp Cache Line to Write - * @params[in] NvU32 comptagLine; - * Comp Tag Line Number to Write - * @params[in] NvU32 partition; - * FB Partition of the desired Comp Cache Line - * @params[in] NvU32 slice; - * Slice of the desired Comp Cache Line - * - * Possible status values returned are: - * NV_OK - * NV_ERR_NOT_SUPPORTED - */ -#define NV2080_CTRL_CMD_FB_COMPBITCOPY_WRITE_COMPCACHELINEPS (0x20801331U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FB_INTERFACE_ID << 8) | 0x31" */ - -typedef struct NV2080_CTRL_CMD_FB_COMPBITCOPY_WRITE_COMPCACHELINEPS_PARAMS { - NV_DECLARE_ALIGNED(NvU32 *compCacheLine, 8); - NvU32 comptagLine; - NvU32 partition; - NvU32 slice; -} NV2080_CTRL_CMD_FB_COMPBITCOPY_WRITE_COMPCACHELINEPS_PARAMS; - -/*! - * NV2080_CTRL_CMD_FB_COMPBITCOPY_GET_COMPCACHELINE_BOUNDS < Deprecated > - * - * Used by PS (Performance Path, or Optimized path, or Per Slice version) - * to retrieve upper and lower Address of the CompCacheLine. - * - * @params[out] NvU64 *minCPUAddress; - * Minimum (lower bound) of the ComCacheLine. - * @params[out] NvU64 *minCPUAddress; - * Minimum (lower bound) of the ComCacheLine. - * @params[in] NvU32 comptagLine; - * CompTagLine to fetch the bounds of. - * - * Possible status values returned are: - * NV_OK - * NV_ERR_NOT_SUPPORTED - */ -#define NV2080_CTRL_CMD_FB_COMPBITCOPY_GET_COMPCACHELINE_BOUNDS (0x20801332U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FB_INTERFACE_ID << 8) | 0x32" */ - -typedef struct NV2080_CTRL_CMD_FB_COMPBITCOPY_GET_COMPCACHELINE_BOUNDS_PARAMS { - NV_DECLARE_ALIGNED(NvU64 *minCPUAddress, 8); - NV_DECLARE_ALIGNED(NvU64 *maxCPUAddress, 8); - NvU32 comptagLine; -} NV2080_CTRL_CMD_FB_COMPBITCOPY_GET_COMPCACHELINE_BOUNDS_PARAMS; - -/*! - * NV2080_CTRL_CMD_FB_COMPBITCOPY_GET_PART_SLICE_OFFSET < Deprecated > - * - * Used by PS (Performance Path, or Optimized path, or Per Slice version) - * to retrieve partition, slice and ROP Tile Offset of the passed in - * surface location. - * - * @params[out] NvU64 *part; - * Partition in which the target part of the surface resides. - * @params[out] NvU64 *slice; - * Slice in which the target part of the surface resides. - * @params[out] NvU64 *ropTileoffset; - * Offset to the start of the ROP Tile in which the target part of - * the surface resides. - * @params[in] NvU64 *dataPhysicalStart; - * Start address of data for which part/slice/offset is desired. - * @params[in] NvU64 surfaceOffset; - * Byte offset of data for which part/slice/offset is desired. - * - * Possible status values returned are: - * NV_OK - * NV_ERR_NOT_SUPPORTED - */ -#define NV2080_CTRL_CMD_FB_COMPBITCOPY_GET_PART_SLICE_OFFSET (0x20801333U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FB_INTERFACE_ID << 8) | 0x33" */ - -typedef struct NV2080_CTRL_CMD_FB_COMPBITCOPY_GET_PART_SLICE_OFFSET_PARAMS { - NV_DECLARE_ALIGNED(NvU64 *part, 8); - NV_DECLARE_ALIGNED(NvU64 *slice, 8); - NV_DECLARE_ALIGNED(NvU64 *ropTileoffset, 8); - NV_DECLARE_ALIGNED(NvU64 dataPhysicalStart, 8); - NV_DECLARE_ALIGNED(NvU64 surfaceOffset, 8); -} NV2080_CTRL_CMD_FB_COMPBITCOPY_GET_PART_SLICE_OFFSET_PARAMS; - -/*! - * NV2080_CTRL_CMD_FB_COMPBITCOPY_ALLOC_AND_INIT_DERIVEDPARAMS < Deprecated > - * - * Used by PS (Performance Path, or Optimized path, or Per Slice version) - * to create a CompBitCopy::CompBitDerivedParams object - * - * @params[out] NvP64 derivedParams - * Actually a CompBitDerivedParams structure. - * @params[in] NvU32 comptagLine; - * Compression Tag Line Number - * @params[in] NvU32 ROPTile_offset; - * Offset in the surface of the ROP tile. - * @params[in] NvBool upper64KBCompbitSel; - * Selects Upper or Lower 64K - * - * Possible status values returned are: - * NV_OK - * NV_ERR_NOT_SUPPORTED - */ -#define NV2080_CTRL_CMD_FB_COMPBITCOPY_ALLOC_AND_INIT_DERIVEDPARAMS (0x20801334U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FB_INTERFACE_ID << 8) | 0x34" */ - -typedef struct NV2080_CTRL_CMD_FB_COMPBITCOPY_ALLOC_AND_INIT_DERIVEDPARAMS_PARAMS { - NV_DECLARE_ALIGNED(NvP64 derivedParams, 8); - NvU32 comptagLine; - NvBool upper64KBCompbitSel; -} NV2080_CTRL_CMD_FB_COMPBITCOPY_ALLOC_AND_INIT_DERIVEDPARAMS_PARAMS; - -/*! * NV2080_CTRL_CMD_FB_COMPBITCOPY_SET_FORCE_BAR1 < Deprecated > * * Used by MODS (and possibly other clients) to have compbit code write @@ -2863,8 +2577,9 @@ /* * NV2080_CTRL_CMD_FB_GET_NUMA_INFO * - * This control command is used by clients to get per-subdevice NUMA memory - * information as assigned by the system. + * This control command is used by clients to get per-subdevice or + * subscribed MIG partition(when MIG is enabled) NUMA memory information as + * assigned by the system. * * numaNodeId[OUT] * - Specifies the NUMA node ID. @@ -2903,4 +2618,37 @@ NV_DECLARE_ALIGNED(NvU64 numaOfflineAddresses[NV2080_CTRL_FB_NUMA_INFO_MAX_OFFLINE_ADDRESSES], 8); } NV2080_CTRL_FB_GET_NUMA_INFO_PARAMS; +/* + * NV2080_CTRL_CMD_FB_GET_SEMAPHORE_SURFACE_LAYOUT + * + * This control command is used by clients to get NV_SEMAPHORE_SURFACE layout/caps before allocation. + * A semaphore surface can be viewed as an array of independent semaphore entries. + * + * maxSubmittedSemaphoreValueOffset[OUT] + * - An offset of the max submitted value, relative to the semaphore surface entry start, if used. + * Used to emulate 64-bit semaphore values on chips where 64-bit semaphores are not supported. + * + * monitoredFenceThresholdOffset[OUT] + * - An offset of the monitored fence memory, relative to the semaphore surface entry start, if supported. + * + * size[OUT] + * - A size of a single semaphore surface entry. + * + * caps[OUT] + * - A mask of NV2080_CTRL_FB_GET_SEMAPHORE_SURFACE_LAYOUT_CAPS_* values. + */ +#define NV2080_CTRL_CMD_FB_GET_SEMAPHORE_SURFACE_LAYOUT (0x20801352U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FB_INTERFACE_ID << 8) | NV2080_CTRL_FB_GET_SEMAPHORE_SURFACE_LAYOUT_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_FB_GET_SEMAPHORE_SURFACE_LAYOUT_CAPS_MONITORED_FENCE_SUPPORTED (0x00000001U) +#define NV2080_CTRL_FB_GET_SEMAPHORE_SURFACE_LAYOUT_CAPS_64BIT_SEMAPHORES_SUPPORTED (0x00000002U) + +#define NV2080_CTRL_FB_GET_SEMAPHORE_SURFACE_LAYOUT_PARAMS_MESSAGE_ID (0x52U) + +typedef struct NV2080_CTRL_FB_GET_SEMAPHORE_SURFACE_LAYOUT_PARAMS { + NV_DECLARE_ALIGNED(NvU64 maxSubmittedSemaphoreValueOffset, 8); + NV_DECLARE_ALIGNED(NvU64 monitoredFenceThresholdOffset, 8); + NV_DECLARE_ALIGNED(NvU64 size, 8); + NvU32 caps; +} NV2080_CTRL_FB_GET_SEMAPHORE_SURFACE_LAYOUT_PARAMS; + /* _ctrl2080fb_h_ */ diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080fifo.h nvidia-open-gpu-kernel-modules-535.161.08/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080fifo.h --- nvidia-open-gpu-kernel-modules-525.147.05/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080fifo.h 2023-10-25 20:22:13.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080fifo.h 2024-03-05 22:15:05.000000000 +0000 @@ -27,7 +27,7 @@ // // This file was generated with FINN, an NVIDIA coding tool. -// Source file: ctrl/ctrl2080/ctrl2080fifo.finn +// Source file: ctrl/ctrl2080/ctrl2080fifo.finn // #include "ctrl/ctrl2080/ctrl2080base.h" @@ -213,10 +213,7 @@ * This index can be used too get channel groups currently in use per engine/runlist. * */ -typedef struct NV2080_CTRL_FIFO_INFO { - NvU32 index; - NvU32 data; -} NV2080_CTRL_FIFO_INFO; +typedef NVXXXX_CTRL_XXX_INFO NV2080_CTRL_FIFO_INFO; /* valid fifo info index values */ #define NV2080_CTRL_FIFO_INFO_INDEX_INSTANCE_TOTAL (0x000000000) diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080fla.h nvidia-open-gpu-kernel-modules-535.161.08/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080fla.h --- nvidia-open-gpu-kernel-modules-525.147.05/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080fla.h 2023-10-25 20:22:13.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080fla.h 2024-03-05 22:15:05.000000000 +0000 @@ -27,7 +27,7 @@ // // This file was generated with FINN, an NVIDIA coding tool. -// Source file: ctrl/ctrl2080/ctrl2080fla.finn +// Source file: ctrl/ctrl2080/ctrl2080fla.finn // #include "ctrl/ctrl2080/ctrl2080base.h" diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080flcn.h nvidia-open-gpu-kernel-modules-535.161.08/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080flcn.h --- nvidia-open-gpu-kernel-modules-525.147.05/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080flcn.h 2023-10-25 20:22:13.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080flcn.h 2024-03-05 22:15:05.000000000 +0000 @@ -27,7 +27,7 @@ // // This file was generated with FINN, an NVIDIA coding tool. -// Source file: ctrl/ctrl2080/ctrl2080flcn.finn +// Source file: ctrl/ctrl2080/ctrl2080flcn.finn // #include "ctrl/ctrl2080/ctrl2080base.h" @@ -332,9 +332,9 @@ * * Get/set the event bitmask for the default queue. */ -#define NV2080_CTRL_CMD_FLCN_USTREAMER_CONTROL_GET (0x20803122) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FLCN_INTERFACE_ID << 8) | 0x22" */ +#define NV2080_CTRL_CMD_FLCN_USTREAMER_CONTROL_GET (0x20803122) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FLCN_INTERFACE_ID << 8) | NV2080_CTRL_FLCN_USTREAMER_CONTROL_GET_PARAMS_MESSAGE_ID" */ -#define NV2080_CTRL_CMD_FLCN_USTREAMER_CONTROL_SET (0x20803123) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FLCN_INTERFACE_ID << 8) | 0x23" */ +#define NV2080_CTRL_CMD_FLCN_USTREAMER_CONTROL_SET (0x20803123) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FLCN_INTERFACE_ID << 8) | NV2080_CTRL_FLCN_USTREAMER_CONTROL_SET_PARAMS_MESSAGE_ID" */ typedef struct NV2080_CTRL_FLCN_USTREAMER_CONTROL_PARAMS { //! The engine type, from NV2080_ENGINE_TYPE_* @@ -353,6 +353,14 @@ NvU8 queueId; } NV2080_CTRL_FLCN_USTREAMER_CONTROL_PARAMS; +#define NV2080_CTRL_FLCN_USTREAMER_CONTROL_GET_PARAMS_MESSAGE_ID (0x22U) + +typedef NV2080_CTRL_FLCN_USTREAMER_CONTROL_PARAMS NV2080_CTRL_FLCN_USTREAMER_CONTROL_GET_PARAMS; + +#define NV2080_CTRL_FLCN_USTREAMER_CONTROL_SET_PARAMS_MESSAGE_ID (0x23U) + +typedef NV2080_CTRL_FLCN_USTREAMER_CONTROL_PARAMS NV2080_CTRL_FLCN_USTREAMER_CONTROL_SET_PARAMS; + /* * NV2080_CTRL_CMD_FLCN_GET_CTX_BUFFER_INFO * diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080fuse.h nvidia-open-gpu-kernel-modules-535.161.08/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080fuse.h --- nvidia-open-gpu-kernel-modules-525.147.05/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080fuse.h 2023-10-25 20:22:13.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080fuse.h 2024-03-05 22:15:05.000000000 +0000 @@ -25,7 +25,7 @@ // // This file was generated with FINN, an NVIDIA coding tool. -// Source file: ctrl/ctrl2080/ctrl2080fuse.finn +// Source file: ctrl/ctrl2080/ctrl2080fuse.finn // diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080gpio.h nvidia-open-gpu-kernel-modules-535.161.08/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080gpio.h --- nvidia-open-gpu-kernel-modules-525.147.05/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080gpio.h 2023-10-25 20:22:13.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080gpio.h 2024-03-05 22:15:05.000000000 +0000 @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 2007-2015 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2007-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -23,14 +23,52 @@ #pragma once +#include + // // This file was generated with FINN, an NVIDIA coding tool. -// Source file: ctrl/ctrl2080/ctrl2080gpio.finn +// Source file: ctrl/ctrl2080/ctrl2080gpio.finn // +#include "ctrl/ctrl2080/ctrl2080base.h" -/* _ctrl2080gpio_h_ */ -#include "ctrl/ctrl2080/ctrl2080base.h" +#define NV2080_CTRL_CMD_INTERNAL_GPIO_PROGRAM_DIRECTION (0x20802300) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPIO_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_GPIO_PROGRAM_DIRECTION_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_INTERNAL_GPIO_PROGRAM_DIRECTION_PARAMS_MESSAGE_ID (0x00U) + +typedef struct NV2080_CTRL_INTERNAL_GPIO_PROGRAM_DIRECTION_PARAMS { + NvU32 gpioPin; // in + NvBool bInput; // in +} NV2080_CTRL_INTERNAL_GPIO_PROGRAM_DIRECTION_PARAMS; + +#define NV2080_CTRL_CMD_INTERNAL_GPIO_PROGRAM_OUTPUT (0x20802301) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPIO_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_GPIO_PROGRAM_OUTPUT_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_INTERNAL_GPIO_PROGRAM_OUTPUT_PARAMS_MESSAGE_ID (0x01U) + +typedef struct NV2080_CTRL_INTERNAL_GPIO_PROGRAM_OUTPUT_PARAMS { + NvU32 gpioPin; // in + NvU32 value; // in +} NV2080_CTRL_INTERNAL_GPIO_PROGRAM_OUTPUT_PARAMS; + +#define NV2080_CTRL_CMD_INTERNAL_GPIO_READ_INPUT (0x20802302) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPIO_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_GPIO_READ_INPUT_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_INTERNAL_GPIO_READ_INPUT_PARAMS_MESSAGE_ID (0x02U) + +typedef struct NV2080_CTRL_INTERNAL_GPIO_READ_INPUT_PARAMS { + NvU32 gpioPin; // in + NvU32 value; // out +} NV2080_CTRL_INTERNAL_GPIO_READ_INPUT_PARAMS; + +#define NV2080_CTRL_CMD_INTERNAL_GPIO_ACTIVATE_HW_FUNCTION (0x20802303) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPIO_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_GPIO_ACTIVATE_HW_FUNCTION_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_INTERNAL_GPIO_ACTIVATE_HW_FUNCTION_PARAMS_MESSAGE_ID (0x03U) + +typedef struct NV2080_CTRL_INTERNAL_GPIO_ACTIVATE_HW_FUNCTION_PARAMS { + NvU32 function; // in + NvU32 pin; // in +} NV2080_CTRL_INTERNAL_GPIO_ACTIVATE_HW_FUNCTION_PARAMS; + +/* _ctrl2080gpio_h_ */ diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080gpu.h nvidia-open-gpu-kernel-modules-535.161.08/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080gpu.h --- nvidia-open-gpu-kernel-modules-525.147.05/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080gpu.h 2023-10-25 20:22:13.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080gpu.h 2024-03-05 22:15:06.000000000 +0000 @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 2006-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2006-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -26,7 +26,7 @@ // // This file was generated with FINN, an NVIDIA coding tool. -// Source file: ctrl/ctrl2080/ctrl2080gpu.finn +// Source file: ctrl/ctrl2080/ctrl2080gpu.finn // #include "ctrl/ctrl2080/ctrl2080base.h" @@ -61,10 +61,7 @@ -typedef struct NV2080_CTRL_GPU_INFO { - NvU32 index; - NvU32 data; -} NV2080_CTRL_GPU_INFO; +typedef NVXXXX_CTRL_XXX_INFO NV2080_CTRL_GPU_INFO; /* valid gpu info index values */ @@ -106,9 +103,16 @@ #define NV2080_CTRL_GPU_INFO_INDEX_GPU_DEBUGGING_CAPABILITY (0x00000037U) +#define NV2080_CTRL_GPU_INFO_INDEX_GPU_LOCAL_EGM_CAPABILITY (0x0000003aU) +#define NV2080_CTRL_GPU_INFO_INDEX_GPU_SELF_HOSTED_CAPABILITY (0x0000003bU) + + #define NV2080_CTRL_GPU_INFO_INDEX_CMP_SKU (0x0000003cU) #define NV2080_CTRL_GPU_INFO_INDEX_DMABUF_CAPABILITY (0x0000003dU) -#define NV2080_CTRL_GPU_INFO_MAX_LIST_SIZE (0x0000003eU) + + +#define NV2080_CTRL_GPU_INFO_INDEX_IS_RESETLESS_MIG_SUPPORTED (0x0000003fU) +#define NV2080_CTRL_GPU_INFO_MAX_LIST_SIZE (0x00000040U) /* valid minor revision extended values */ #define NV2080_CTRL_GPU_INFO_MINOR_REVISION_EXT_NONE (0x00000000U) @@ -199,6 +203,16 @@ #define NV2080_CTRL_GPU_INFO_INDEX_GPU_DEBUGGING_CAPABILITY_ENABLED (0x00000001U) +/* valid local EGM supported values */ +#define NV2080_CTRL_GPU_INFO_INDEX_GPU_LOCAL_EGM_CAPABILITY_NO (0x00000000U) +#define NV2080_CTRL_GPU_INFO_INDEX_GPU_LOCAL_EGM_CAPABILITY_YES (0x00000001U) +#define NV2080_CTRL_GPU_INFO_INDEX_GPU_LOCAL_EGM_PEERID 31:1 + +/* valid self hosted values */ +#define NV2080_CTRL_GPU_INFO_INDEX_GPU_SELF_HOSTED_CAPABILITY_NO (0x00000000U) +#define NV2080_CTRL_GPU_INFO_INDEX_GPU_SELF_HOSTED_CAPABILITY_YES (0x00000001U) + + /* valid CMP (Crypto Mining Processor) SKU values */ #define NV2080_CTRL_GPU_INFO_INDEX_CMP_SKU_NO (0x00000000U) @@ -209,6 +223,10 @@ #define NV2080_CTRL_GPU_INFO_INDEX_DMABUF_CAPABILITY_NO (0x00000000U) #define NV2080_CTRL_GPU_INFO_INDEX_DMABUF_CAPABILITY_YES (0x00000001U) +/* valid resetless MIG device supported values */ +#define NV2080_CTRL_GPU_INFO_INDEX_IS_RESETLESS_MIG_SUPPORTED_NO (0x00000000U) +#define NV2080_CTRL_GPU_INFO_INDEX_IS_RESETLESS_MIG_SUPPORTED_YES (0x00000001U) + /* * NV2080_CTRL_CMD_GPU_GET_INFO * @@ -241,7 +259,9 @@ NV_DECLARE_ALIGNED(NvP64 gpuInfoList, 8); } NV2080_CTRL_GPU_GET_INFO_PARAMS; -#define NV2080_CTRL_CMD_GPU_GET_INFO_V2 (0x20800102U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | 0x2" */ +#define NV2080_CTRL_CMD_GPU_GET_INFO_V2 (0x20800102U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_GET_INFO_V2_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_GPU_GET_INFO_V2_PARAMS_MESSAGE_ID (0x2U) typedef struct NV2080_CTRL_GPU_GET_INFO_V2_PARAMS { NvU32 gpuInfoListSize; @@ -687,7 +707,9 @@ * NV_ERR_INVALID_ARGUMENT * NV_ERR_INVALID_PARAM_STRUCT */ -#define NV2080_CTRL_CMD_GPU_EXEC_REG_OPS (0x20800122U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | 0x22" */ +#define NV2080_CTRL_CMD_GPU_EXEC_REG_OPS (0x20800122U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_EXEC_REG_OPS_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_GPU_EXEC_REG_OPS_PARAMS_MESSAGE_ID (0x22U) typedef struct NV2080_CTRL_GPU_EXEC_REG_OPS_PARAMS { NvHandle hClientTarget; @@ -1516,6 +1538,10 @@ * The board's 699 product part number (LSB justified ASCII field with 0x00 * denoting empty space e.g. "699-21228-0208-200"). * + * board965PartNumber + * The board's 965 product part number (LSB justified ASCII field with 0x00 + * denoting empty space e.g. "965-21228-0208-200"). + * * Possible status return values are: * NV_OK * NV_ERR_NOT_SUPPORTED @@ -1541,6 +1567,7 @@ NvU8 boardRevision[3]; NvU8 boardType; NvU8 board699PartNumber[NV2080_GPU_MAX_PRODUCT_PART_NUMBER_LENGTH]; + NvU8 board965PartNumber[NV2080_GPU_MAX_PRODUCT_PART_NUMBER_LENGTH]; } NV2080_CTRL_GPU_GET_OEM_BOARD_INFO_PARAMS; @@ -1867,13 +1894,17 @@ * NV_OK * NV_ERR_NOT_SUPPORTED */ -#define NV2080_CTRL_CMD_GPU_GET_ILLUM (0x20800154U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | 0x54" */ +#define NV2080_CTRL_CMD_GPU_GET_ILLUM (0x20800154U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_GET_ILLUM_PARAMS_MESSAGE_ID" */ typedef struct NV2080_CTRL_CMD_GPU_ILLUM_PARAMS { NvU32 attribute; NvU32 value; } NV2080_CTRL_CMD_GPU_ILLUM_PARAMS; +#define NV2080_CTRL_GPU_GET_ILLUM_PARAMS_MESSAGE_ID (0x54U) + +typedef NV2080_CTRL_CMD_GPU_ILLUM_PARAMS NV2080_CTRL_GPU_GET_ILLUM_PARAMS; + /* * NV2080_CTRL_CMD_GPU_SET_ID_ILLUM * @@ -1883,7 +1914,11 @@ * NV_OK * NV_ERR_NOT_SUPPORTED */ -#define NV2080_CTRL_CMD_GPU_SET_ILLUM (0x20800155U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | 0x55" */ +#define NV2080_CTRL_CMD_GPU_SET_ILLUM (0x20800155U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_SET_ILLUM_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_GPU_SET_ILLUM_PARAMS_MESSAGE_ID (0x55U) + +typedef NV2080_CTRL_CMD_GPU_ILLUM_PARAMS NV2080_CTRL_GPU_SET_ILLUM_PARAMS; /* * NV2080_CTRL_CMD_GPU_GET_INFOROM_IMAGE_VERSION @@ -2569,7 +2604,7 @@ #define NV2080_CTRL_GPU_PARTITION_FLAG_COMPUTE_SIZE__SIZE 6U -#define NV2080_CTRL_GPU_PARTITION_MAX_TYPES 8U +#define NV2080_CTRL_GPU_PARTITION_MAX_TYPES 20U #define NV2080_CTRL_GPU_PARTITION_FLAG_REQ_DEC_JPG_OFA 30:30 #define NV2080_CTRL_GPU_PARTITION_FLAG_REQ_DEC_JPG_OFA_DISABLE 0U #define NV2080_CTRL_GPU_PARTITION_FLAG_REQ_DEC_JPG_OFA_ENABLE 1U @@ -2582,6 +2617,7 @@ #define NV2080_CTRL_GPU_PARTITION_FLAG_ONE_HALF_GPU (DRF_DEF(2080, _CTRL_GPU_PARTITION_FLAG, _MEMORY_SIZE, _HALF) | DRF_DEF(2080, _CTRL_GPU_PARTITION_FLAG, _COMPUTE_SIZE, _HALF)) #define NV2080_CTRL_GPU_PARTITION_FLAG_ONE_MINI_HALF_GPU (DRF_DEF(2080, _CTRL_GPU_PARTITION_FLAG, _MEMORY_SIZE, _HALF) | DRF_DEF(2080, _CTRL_GPU_PARTITION_FLAG, _COMPUTE_SIZE, _MINI_HALF)) #define NV2080_CTRL_GPU_PARTITION_FLAG_ONE_QUARTER_GPU (DRF_DEF(2080, _CTRL_GPU_PARTITION_FLAG, _MEMORY_SIZE, _QUARTER) | DRF_DEF(2080, _CTRL_GPU_PARTITION_FLAG, _COMPUTE_SIZE, _QUARTER)) +#define NV2080_CTRL_GPU_PARTITION_FLAG_ONE_MINI_QUARTER_GPU (DRF_DEF(2080, _CTRL_GPU_PARTITION_FLAG, _MEMORY_SIZE, _QUARTER) | DRF_DEF(2080, _CTRL_GPU_PARTITION_FLAG, _COMPUTE_SIZE, _MINI_QUARTER)) #define NV2080_CTRL_GPU_PARTITION_FLAG_ONE_EIGHTHED_GPU (DRF_DEF(2080, _CTRL_GPU_PARTITION_FLAG, _MEMORY_SIZE, _EIGHTH) | DRF_DEF(2080, _CTRL_GPU_PARTITION_FLAG, _COMPUTE_SIZE, _EIGHTH)) #define NV2080_CTRL_GPU_SET_PARTITIONS_PARAMS_MESSAGE_ID (0x74U) @@ -2817,7 +2853,11 @@ * See confluence page "vGPU UMED Security" for details. * */ -#define NV2080_CTRL_CMD_GPU_EXEC_REG_OPS_VGPU (0x20800178U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | 0x78" */ +#define NV2080_CTRL_CMD_GPU_EXEC_REG_OPS_VGPU (0x20800178U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_EXEC_REG_OPS_VGPU_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_GPU_EXEC_REG_OPS_VGPU_PARAMS_MESSAGE_ID (0x78U) + +typedef NV2080_CTRL_GPU_EXEC_REG_OPS_PARAMS NV2080_CTRL_GPU_EXEC_REG_OPS_VGPU_PARAMS; /* * NV2080_CTRL_CMD_GPU_GET_ENGINE_RUNLIST_PRI_BASE @@ -3120,12 +3160,11 @@ * NV_ERR_NOT_SUPPORTED * NV_ERR_OPERATING_SYSTEM */ -#define NV2080_CTRL_CMD_GPU_GET_CACHED_INFO (0x20800182U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | 0x82" */ +#define NV2080_CTRL_CMD_GPU_GET_CACHED_INFO (0x20800182U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_GET_CACHED_INFO_PARAMS_MESSAGE_ID" */ -typedef struct NV2080_CTRL_GPU_GET_CACHED_INFO_PARAMS { - NvU32 gpuInfoListSize; - NV2080_CTRL_GPU_INFO gpuInfoList[NV2080_CTRL_GPU_INFO_MAX_LIST_SIZE]; -} NV2080_CTRL_GPU_GET_CACHED_INFO_PARAMS; +#define NV2080_CTRL_GPU_GET_CACHED_INFO_PARAMS_MESSAGE_ID (0x82U) + +typedef NV2080_CTRL_GPU_GET_INFO_V2_PARAMS NV2080_CTRL_GPU_GET_CACHED_INFO_PARAMS; /* * NV2080_CTRL_GPU_SET_PARTITIONING_MODE @@ -3245,7 +3284,7 @@ NvU32 gfxGrCount; NvU32 gpcCount; NvU32 virtualGpcCount; - NvU32 grGpcCount; + NvU32 gfxGpcCount; NvU32 veidCount; NvU32 smCount; NvU32 ceCount; @@ -3303,7 +3342,7 @@ #define NV2080_CTRL_GPU_GET_MAX_SUPPORTED_PAGE_SIZE_PARAMS_MESSAGE_ID (0x88U) typedef struct NV2080_CTRL_GPU_GET_MAX_SUPPORTED_PAGE_SIZE_PARAMS { - NvU32 maxSupportedPageSize; + NV_DECLARE_ALIGNED(NvU64 maxSupportedPageSize, 8); } NV2080_CTRL_GPU_GET_MAX_SUPPORTED_PAGE_SIZE_PARAMS; @@ -3748,6 +3787,23 @@ NvU32 protection; } NV2080_CTRL_GPU_VALIDATE_MEM_MAP_REQUEST_PARAMS; +/* + * NV2080_CTRL_CMD_GPU_SET_EGM_GPA_FABRIC_BASE_ADDR + * + * @brief This command is similar to NV2080_CTRL_CMD_GPU_SET_FABRIC_BASE_ADDR + * but will be used to set the EGM fabric base addr associated with the gpu. + * Note: For EGM FLA, we will be making use of the existing control call i.e + * NV2080_CTRL_CMD_FLA_RANGE + * + */ +#define NV2080_CTRL_CMD_GPU_SET_EGM_GPA_FABRIC_BASE_ADDR (0x20800199U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_SET_EGM_GPA_FABRIC_BASE_ADDR_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_GPU_SET_EGM_GPA_FABRIC_BASE_ADDR_PARAMS_MESSAGE_ID (0x99U) + +typedef struct NV2080_CTRL_GPU_SET_EGM_GPA_FABRIC_BASE_ADDR_PARAMS { + NV_DECLARE_ALIGNED(NvU64 egmGpaFabricBaseAddr, 8); +} NV2080_CTRL_GPU_SET_EGM_GPA_FABRIC_BASE_ADDR_PARAMS; + /* @@ -3773,7 +3829,7 @@ */ #define NV2080_CTRL_CMD_GPU_GET_ENGINE_LOAD_TIMES (0x2080019bU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_GET_ENGINE_LOAD_TIMES_PARAMS_MESSAGE_ID" */ -#define NV2080_CTRL_GPU_MAX_ENGINE_OBJECTS 0xA0U +#define NV2080_CTRL_GPU_MAX_ENGINE_OBJECTS 0xC0U #define NV2080_CTRL_GPU_GET_ENGINE_LOAD_TIMES_PARAMS_MESSAGE_ID (0x9BU) @@ -3967,7 +4023,7 @@ * - Total Number of profiles filled * * profiles[OUT] - * - NV2080_CTRL_GPU_COMPUTE_PROFILE filled with valid compute instance profiles + * - NV2080_CTRL_GPU_COMPUTE_PROFILE filled with valid compute instance profiles */ #define NV2080_CTRL_GPU_GET_COMPUTE_PROFILES_PARAMS_MESSAGE_ID (0xA2U) @@ -4029,11 +4085,11 @@ /* * NV2080_CTRL_CMD_GPU_GET_CHIP_DETAILS - * + * * This command retrieves and constructs the GPU partnumber from the VBIOS. - * + * * The following data are currently supported: - * + * * pciDevId * The PCI device ID * @@ -4049,8 +4105,8 @@ */ #define NV2080_CTRL_CMD_GPU_GET_CHIP_DETAILS (0x208001a4U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_GET_CHIP_DETAILS_PARAMS_MESSAGE_ID" */ -/* - * The string format for a GPU part number +/* + * The string format for a GPU part number * The GPU part number is formatted with 4 hexadecimal digits for the PCI device ID, the chip SKU string, * the chip major number, and then the chip minor number. * Ordering of the fields for the string format must be synced with the NV2080_CTRL_GPU_GET_CHIP_DETAILS_PARAMS @@ -4118,6 +4174,98 @@ typedef NV2080_CTRL_GPU_MIGRATABLE_OPS_CMN_PARAMS NV2080_CTRL_GPU_MIGRATABLE_OPS_VGPU_PARAMS; /* + * NV2080_CTRL_CMD_GPU_MARK_DEVICE_FOR_RESET + * + * INTERNAL DEBUG/TESTING USE ONLY + * + * Marks the device for reset. + * + * Possible status return values are: + * NV_OK + * NV_ERR_NOT_SUPPORTED + */ +#define NV2080_CTRL_CMD_GPU_MARK_DEVICE_FOR_RESET (0x208001a9U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | 0xA9" */ + +/* + * NV2080_CTRL_CMD_GPU_UNMARK_DEVICE_FOR_RESET + * + * INTERNAL DEBUG/TESTING USE ONLY + * + * Unmarks the device for reset. + * + * Possible status return values are: + * NV_OK + * NV_ERR_NOT_SUPPORTED + */ +#define NV2080_CTRL_CMD_GPU_UNMARK_DEVICE_FOR_RESET (0x208001aaU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | 0xAA" */ + +/* + * NV2080_CTRL_CMD_GPU_GET_RESET_STATUS + * + * Gets the current reset status of the device. + * + * bResetNeeded + * Set to NV_TRUE if the device needs to be reset. + * + * Possible status return values are: + * NV_OK + * NV_ERR_NOT_SUPPORTED + */ +#define NV2080_CTRL_CMD_GPU_GET_RESET_STATUS (0x208001abU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_GET_RESET_STATUS_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_GPU_GET_RESET_STATUS_PARAMS_MESSAGE_ID (0xABU) + +typedef struct NV2080_CTRL_GPU_GET_RESET_STATUS_PARAMS { + NvBool bResetRequired; +} NV2080_CTRL_GPU_GET_RESET_STATUS_PARAMS; + +/* + * NV2080_CTRL_CMD_GPU_MARK_DEVICE_FOR_DRAIN_AND_RESET + * + * INTERNAL DEBUG/TESTING USE ONLY + * + * Marks the device for drain and reset. + * + * Possible status return values are: + * NV_OK + * NV_ERR_NOT_SUPPORTED + */ +#define NV2080_CTRL_CMD_GPU_MARK_DEVICE_FOR_DRAIN_AND_RESET (0x208001acU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | 0xAC" */ + +/* + * NV2080_CTRL_CMD_GPU_UNMARK_DEVICE_FOR_DRAIN_AND_RESET + * + * INTERNAL DEBUG/TESTING USE ONLY + * + * Unmarks the device for drain and reset. + * + * Possible status return values are: + * NV_OK + * NV_ERR_NOT_SUPPORTED + */ +#define NV2080_CTRL_CMD_GPU_UNMARK_DEVICE_FOR_DRAIN_AND_RESET (0x208001adU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | 0xAD" */ + +/* + * NV2080_CTRL_CMD_GPU_GET_DRAIN_AND_RESET_STATUS + * + * Gets the current drain and reset status of the device. Drain and reset is used only SMC configs. + * + * bDrainRecommended + * Set to NV_TRUE if a drain and reset is recommended for the device. + * + * Possible status return values are: + * NV_OK + * NV_ERR_NOT_SUPPORTED + */ +#define NV2080_CTRL_CMD_GPU_GET_DRAIN_AND_RESET_STATUS (0x208001aeU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_GET_DRAIN_AND_RESET_STATUS_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_GPU_GET_DRAIN_AND_RESET_STATUS_PARAMS_MESSAGE_ID (0xAEU) + +typedef struct NV2080_CTRL_GPU_GET_DRAIN_AND_RESET_STATUS_PARAMS { + NvBool bDrainRecommended; +} NV2080_CTRL_GPU_GET_DRAIN_AND_RESET_STATUS_PARAMS; + +/* * NV2080_CTRL_GPU_GET_NVENC_SW_SESSION_INFO_V2 * * This command returns NVENC software sessions information for the associate GPU. @@ -4127,13 +4275,13 @@ * Check NV2080_CTRL_GPU_GET_NVENC_SW_SESSION_INFO for detailed information. */ -#define NV2080_CTRL_GPU_GET_NVENC_SW_SESSION_INFO_V2_PARAMS_MESSAGE_ID (0xA9U) +#define NV2080_CTRL_GPU_GET_NVENC_SW_SESSION_INFO_V2_PARAMS_MESSAGE_ID (0xAFU) typedef struct NV2080_CTRL_GPU_GET_NVENC_SW_SESSION_INFO_V2_PARAMS { NvU32 sessionInfoTblEntry; NV2080_CTRL_NVENC_SW_SESSION_INFO sessionInfoTbl[NV2080_CTRL_GPU_NVENC_SESSION_INFO_MAX_COPYOUT_ENTRIES]; } NV2080_CTRL_GPU_GET_NVENC_SW_SESSION_INFO_V2_PARAMS; -#define NV2080_CTRL_GPU_GET_NVENC_SW_SESSION_INFO_V2 (0x208001a9U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_GET_NVENC_SW_SESSION_INFO_V2_PARAMS_MESSAGE_ID" */ +#define NV2080_CTRL_GPU_GET_NVENC_SW_SESSION_INFO_V2 (0x208001afU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_GET_NVENC_SW_SESSION_INFO_V2_PARAMS_MESSAGE_ID" */ /* _ctrl2080gpu_h_ */ diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080gpumon.h nvidia-open-gpu-kernel-modules-535.161.08/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080gpumon.h --- nvidia-open-gpu-kernel-modules-525.147.05/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080gpumon.h 2023-10-25 20:22:13.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080gpumon.h 2024-03-05 22:15:06.000000000 +0000 @@ -27,7 +27,7 @@ // // This file was generated with FINN, an NVIDIA coding tool. -// Source file: ctrl/ctrl2080/ctrl2080gpumon.finn +// Source file: ctrl/ctrl2080/ctrl2080gpumon.finn // diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080gr.h nvidia-open-gpu-kernel-modules-535.161.08/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080gr.h --- nvidia-open-gpu-kernel-modules-525.147.05/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080gr.h 2023-10-25 20:22:14.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080gr.h 2024-03-05 22:15:06.000000000 +0000 @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 2006-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2006-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -27,7 +27,7 @@ // // This file was generated with FINN, an NVIDIA coding tool. -// Source file: ctrl/ctrl2080/ctrl2080gr.finn +// Source file: ctrl/ctrl2080/ctrl2080gr.finn // #include "ctrl/ctrl2080/ctrl2080base.h" @@ -147,6 +147,9 @@ * NV2080_CTRL_GR_INFO_INDEX_TENSOR_CORE_COUNT * This index is used to return the number of "Tensor Cores" * supported by the graphics pipeline + * NV2080_CTRL_GR_INFO_INDEX_GFX_CAPABILITIES + * This index is used to return the Graphics capabilities + * supported by the graphics pipeline */ typedef NV0080_CTRL_GR_INFO NV2080_CTRL_GR_INFO; @@ -254,6 +257,10 @@ #define NV2080_CTRL_GR_INFO_INDEX_LITTER_NUM_GFXC_TPCS_PER_GFXC_GPC NV0080_CTRL_GR_INFO_INDEX_LITTER_NUM_GFXC_TPCS_PER_GFXC_GPC #define NV2080_CTRL_GR_INFO_INDEX_LITTER_NUM_SLICES_PER_LTC NV0080_CTRL_GR_INFO_INDEX_LITTER_NUM_SLICES_PER_LTC + +#define NV2080_CTRL_GR_INFO_INDEX_DUMMY NV0080_CTRL_GR_INFO_INDEX_DUMMY +#define NV2080_CTRL_GR_INFO_INDEX_GFX_CAPABILITIES NV0080_CTRL_GR_INFO_INDEX_GFX_CAPABILITIES + /* When adding a new INDEX, please update INDEX_MAX and MAX_SIZE accordingly * NOTE: 0080 functionality is merged with 2080 functionality, so this max size * reflects that. @@ -320,6 +327,19 @@ +#define NV2080_CTRL_GR_INFO_GFX_CAPABILITIES_2D 0:0 +#define NV2080_CTRL_GR_INFO_GFX_CAPABILITIES_2D_FALSE 0x0U +#define NV2080_CTRL_GR_INFO_GFX_CAPABILITIES_2D_TRUE 0x1U +#define NV2080_CTRL_GR_INFO_GFX_CAPABILITIES_3D 1:1 +#define NV2080_CTRL_GR_INFO_GFX_CAPABILITIES_3D_FALSE 0x0U +#define NV2080_CTRL_GR_INFO_GFX_CAPABILITIES_3D_TRUE 0x1U +#define NV2080_CTRL_GR_INFO_GFX_CAPABILITIES_COMPUTE 2:2 +#define NV2080_CTRL_GR_INFO_GFX_CAPABILITIES_COMPUTE_FALSE 0x0U +#define NV2080_CTRL_GR_INFO_GFX_CAPABILITIES_COMPUTE_TRUE 0x1U +#define NV2080_CTRL_GR_INFO_GFX_CAPABILITIES_I2M 3:3 +#define NV2080_CTRL_GR_INFO_GFX_CAPABILITIES_I2M_FALSE 0x0U +#define NV2080_CTRL_GR_INFO_GFX_CAPABILITIES_I2M_TRUE 0x1U + /** * NV2080_CTRL_CMD_GR_GET_INFO * @@ -389,7 +409,9 @@ * ID is given (shareChID), then the 2 channels will share * the zcull context buffers. */ -#define NV2080_CTRL_CMD_GR_CTXSW_ZCULL_MODE (0x20801205U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GR_INTERFACE_ID << 8) | 0x5" */ +#define NV2080_CTRL_CMD_GR_CTXSW_ZCULL_MODE (0x20801205U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GR_INTERFACE_ID << 8) | NV2080_CTRL_GR_CTXSW_ZCULL_MODE_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_GR_CTXSW_ZCULL_MODE_PARAMS_MESSAGE_ID (0x5U) typedef struct NV2080_CTRL_GR_CTXSW_ZCULL_MODE_PARAMS { NvHandle hChannel; @@ -494,7 +516,9 @@ * This parameter specifies the routing information used to * disambiguate the target GR engine. */ -#define NV2080_CTRL_CMD_GR_CTXSW_PM_MODE (0x20801207U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GR_INTERFACE_ID << 8) | 0x7" */ +#define NV2080_CTRL_CMD_GR_CTXSW_PM_MODE (0x20801207U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GR_INTERFACE_ID << 8) | NV2080_CTRL_GR_CTXSW_PM_MODE_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_GR_CTXSW_PM_MODE_PARAMS_MESSAGE_ID (0x7U) typedef struct NV2080_CTRL_GR_CTXSW_PM_MODE_PARAMS { NvHandle hChannel; @@ -542,7 +566,9 @@ * ID is given (shareChID), then the 2 channels will share * the zcull context buffers. */ -#define NV2080_CTRL_CMD_GR_CTXSW_ZCULL_BIND (0x20801208U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GR_INTERFACE_ID << 8) | 0x8" */ +#define NV2080_CTRL_CMD_GR_CTXSW_ZCULL_BIND (0x20801208U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GR_INTERFACE_ID << 8) | NV2080_CTRL_GR_CTXSW_ZCULL_BIND_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_GR_CTXSW_ZCULL_BIND_PARAMS_MESSAGE_ID (0x8U) typedef struct NV2080_CTRL_GR_CTXSW_ZCULL_BIND_PARAMS { NvHandle hClient; @@ -580,7 +606,9 @@ * This parameter specifies the routing information used to * disambiguate the target GR engine. */ -#define NV2080_CTRL_CMD_GR_CTXSW_PM_BIND (0x20801209U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GR_INTERFACE_ID << 8) | 0x9" */ +#define NV2080_CTRL_CMD_GR_CTXSW_PM_BIND (0x20801209U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GR_INTERFACE_ID << 8) | NV2080_CTRL_GR_CTXSW_PM_BIND_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_GR_CTXSW_PM_BIND_PARAMS_MESSAGE_ID (0x9U) typedef struct NV2080_CTRL_GR_CTXSW_PM_BIND_PARAMS { NvHandle hClient; @@ -607,7 +635,9 @@ * disambiguate the target GR engine. */ #define NV2080_CTRL_GR_SET_GPC_TILE_MAP_MAX_VALUES 128U -#define NV2080_CTRL_CMD_GR_SET_GPC_TILE_MAP (0x2080120aU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GR_INTERFACE_ID << 8) | 0xA" */ +#define NV2080_CTRL_CMD_GR_SET_GPC_TILE_MAP (0x2080120aU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GR_INTERFACE_ID << 8) | NV2080_CTRL_GR_SET_GPC_TILE_MAP_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_GR_SET_GPC_TILE_MAP_PARAMS_MESSAGE_ID (0xAU) typedef struct NV2080_CTRL_GR_SET_GPC_TILE_MAP_PARAMS { NvU32 mapValueCount; @@ -645,7 +675,9 @@ * This parameter specifies the routing information used to * disambiguate the target GR engine. */ -#define NV2080_CTRL_CMD_GR_CTXSW_SMPC_MODE (0x2080120eU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GR_INTERFACE_ID << 8) | 0xE" */ +#define NV2080_CTRL_CMD_GR_CTXSW_SMPC_MODE (0x2080120eU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GR_INTERFACE_ID << 8) | NV2080_CTRL_GR_CTXSW_SMPC_MODE_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_GR_CTXSW_SMPC_MODE_PARAMS_MESSAGE_ID (0xEU) typedef struct NV2080_CTRL_GR_CTXSW_SMPC_MODE_PARAMS { NvHandle hChannel; @@ -724,7 +756,9 @@ * This parameter specifies the routing information used to * disambiguate the target GR engine. */ -#define NV2080_CTRL_CMD_GR_SET_CTXSW_PREEMPTION_MODE (0x20801210U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GR_INTERFACE_ID << 8) | 0x10" */ +#define NV2080_CTRL_CMD_GR_SET_CTXSW_PREEMPTION_MODE (0x20801210U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GR_INTERFACE_ID << 8) | NV2080_CTRL_GR_SET_CTXSW_PREEMPTION_MODE_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_GR_SET_CTXSW_PREEMPTION_MODE_PARAMS_MESSAGE_ID (0x10U) typedef struct NV2080_CTRL_GR_SET_CTXSW_PREEMPTION_MODE_PARAMS { NvU32 flags; @@ -809,7 +843,9 @@ * This parameter specifies the routing information used to * disambiguate the target GR engine. */ -#define NV2080_CTRL_CMD_GR_CTXSW_PREEMPTION_BIND (0x20801211U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GR_INTERFACE_ID << 8) | 0x11" */ +#define NV2080_CTRL_CMD_GR_CTXSW_PREEMPTION_BIND (0x20801211U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GR_INTERFACE_ID << 8) | NV2080_CTRL_GR_CTXSW_PREEMPTION_BIND_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_GR_CTXSW_PREEMPTION_BIND_PARAMS_MESSAGE_ID (0x11U) typedef struct NV2080_CTRL_GR_CTXSW_PREEMPTION_BIND_PARAMS { NvU32 flags; @@ -842,7 +878,9 @@ * This parameter specifies the routing information used to * disambiguate the target GR engine. */ -#define NV2080_CTRL_CMD_GR_PC_SAMPLING_MODE (0x20801212U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GR_INTERFACE_ID << 8) | 0x12" */ +#define NV2080_CTRL_CMD_GR_PC_SAMPLING_MODE (0x20801212U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GR_INTERFACE_ID << 8) | NV2080_CTRL_GR_PC_SAMPLING_MODE_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_GR_PC_SAMPLING_MODE_PARAMS_MESSAGE_ID (0x12U) typedef struct NV2080_CTRL_GR_PC_SAMPLING_MODE_PARAMS { NvHandle hChannel; @@ -904,7 +942,9 @@ * gfxpSaveCnt * This parameter returns the number of GfxP saves on the channel. */ -#define NV2080_CTRL_CMD_GR_GET_CTXSW_STATS (0x20801215U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GR_INTERFACE_ID << 8) | 0x15" */ +#define NV2080_CTRL_CMD_GR_GET_CTXSW_STATS (0x20801215U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GR_INTERFACE_ID << 8) | NV2080_CTRL_GR_GET_CTXSW_STATS_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_GR_GET_CTXSW_STATS_PARAMS_MESSAGE_ID (0x15U) typedef struct NV2080_CTRL_GR_GET_CTXSW_STATS_PARAMS { NvHandle hChannel; @@ -1120,12 +1160,14 @@ * This parameter specifies the routing information used to * disambiguate the target GR engine. */ -#define NV2080_CTRL_CMD_GR_GET_CURRENT_RESIDENT_CHANNEL (0x2080121cU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GR_INTERFACE_ID << 8) | 0x1C" */ +#define NV2080_CTRL_CMD_GR_GET_CURRENT_RESIDENT_CHANNEL (0x2080121cU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GR_INTERFACE_ID << 8) | NV2080_CTRL_GR_GET_CURRENT_RESIDENT_CHANNEL_PARAMS_MESSAGE_ID" */ -typedef struct NV2080_CTRL_CMD_GR_GET_CURRENT_RESIDENT_CHANNEL_PARAMS { +#define NV2080_CTRL_GR_GET_CURRENT_RESIDENT_CHANNEL_PARAMS_MESSAGE_ID (0x1CU) + +typedef struct NV2080_CTRL_GR_GET_CURRENT_RESIDENT_CHANNEL_PARAMS { NvU32 chID; NV_DECLARE_ALIGNED(NV2080_CTRL_GR_ROUTE_INFO grRouteInfo, 8); -} NV2080_CTRL_CMD_GR_GET_CURRENT_RESIDENT_CHANNEL_PARAMS; +} NV2080_CTRL_GR_GET_CURRENT_RESIDENT_CHANNEL_PARAMS; /* * NV2080_CTRL_CMD_GR_GET_VAT_ALARM_DATA @@ -1144,7 +1186,7 @@ #define NV2080_CTRL_CMD_GR_GET_VAT_ALARM_MAX_GPC_COUNT 10U #define NV2080_CTRL_CMD_GR_GET_VAT_ALARM_MAX_TPC_PER_GPC_COUNT 10U -#define NV2080_CTRL_CMD_GR_GET_VAT_ALARM_DATA (0x2080121dU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GR_INTERFACE_ID << 8) | 0x1D" */ +#define NV2080_CTRL_CMD_GR_GET_VAT_ALARM_DATA (0x2080121dU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GR_INTERFACE_ID << 8) | NV2080_CTRL_GR_GET_VAT_ALARM_DATA_PARAMS_MESSAGE_ID" */ typedef struct NV2080_CTRL_GR_VAT_ALARM_DATA_PER_TPC { NV_DECLARE_ALIGNED(NvU64 errorCounter, 8); @@ -1161,6 +1203,8 @@ NV_DECLARE_ALIGNED(NV2080_CTRL_GR_VAT_ALARM_DATA_PER_GPC gpc[NV2080_CTRL_CMD_GR_GET_VAT_ALARM_MAX_GPC_COUNT], 8); } NV2080_CTRL_GR_VAT_ALARM_DATA; +#define NV2080_CTRL_GR_GET_VAT_ALARM_DATA_PARAMS_MESSAGE_ID (0x1DU) + typedef struct NV2080_CTRL_GR_GET_VAT_ALARM_DATA_PARAMS { NV_DECLARE_ALIGNED(NV2080_CTRL_GR_VAT_ALARM_DATA smVatAlarm, 8); NvU32 maxGpcCount; @@ -1209,7 +1253,9 @@ * The number of bytes in each slot, i * slotStride gives the offset from the * base of the pool to a given slot */ -#define NV2080_CTRL_CMD_GR_GFX_POOL_QUERY_SIZE (0x2080121fU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GR_INTERFACE_ID << 8) | 0x1F" */ +#define NV2080_CTRL_CMD_GR_GFX_POOL_QUERY_SIZE (0x2080121fU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GR_INTERFACE_ID << 8) | NV2080_CTRL_GR_GFX_POOL_QUERY_SIZE_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_GR_GFX_POOL_QUERY_SIZE_PARAMS_MESSAGE_ID (0x1FU) typedef struct NV2080_CTRL_GR_GFX_POOL_QUERY_SIZE_PARAMS { NvU32 maxSlots; @@ -1233,7 +1279,9 @@ * pControlStructure * This input is the kernel CPU pointer to the control structure. */ -#define NV2080_CTRL_CMD_GR_GFX_POOL_INITIALIZE (0x20801220U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GR_INTERFACE_ID << 8) | 0x20" */ +#define NV2080_CTRL_CMD_GR_GFX_POOL_INITIALIZE (0x20801220U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GR_INTERFACE_ID << 8) | NV2080_CTRL_GR_GFX_POOL_INITIALIZE_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_GR_GFX_POOL_INITIALIZE_PARAMS_MESSAGE_ID (0x20U) typedef struct NV2080_CTRL_GR_GFX_POOL_INITIALIZE_PARAMS { NV_DECLARE_ALIGNED(NvP64 pControlStructure, 8); @@ -1260,7 +1308,9 @@ * slots * This input contains an array of the slots to be added to the control structure */ -#define NV2080_CTRL_CMD_GR_GFX_POOL_ADD_SLOTS (0x20801221U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GR_INTERFACE_ID << 8) | 0x21" */ +#define NV2080_CTRL_CMD_GR_GFX_POOL_ADD_SLOTS (0x20801221U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GR_INTERFACE_ID << 8) | NV2080_CTRL_GR_GFX_POOL_ADD_SLOTS_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_GR_GFX_POOL_ADD_SLOTS_PARAMS_MESSAGE_ID (0x21U) typedef struct NV2080_CTRL_GR_GFX_POOL_ADD_SLOTS_PARAMS { NV_DECLARE_ALIGNED(NvP64 pControlStructure, 8); @@ -1299,7 +1349,9 @@ * many. If there are not enough slots on the freelist to remove the * requested amount, RM will return the number it was able to remove. */ -#define NV2080_CTRL_CMD_GR_GFX_POOL_REMOVE_SLOTS (0x20801222U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GR_INTERFACE_ID << 8) | 0x22" */ +#define NV2080_CTRL_CMD_GR_GFX_POOL_REMOVE_SLOTS (0x20801222U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GR_INTERFACE_ID << 8) | NV2080_CTRL_GR_GFX_POOL_REMOVE_SLOTS_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_GR_GFX_POOL_REMOVE_SLOTS_PARAMS_MESSAGE_ID (0x22U) typedef struct NV2080_CTRL_GR_GFX_POOL_REMOVE_SLOTS_PARAMS { NV_DECLARE_ALIGNED(NvP64 pControlStructure, 8); @@ -1375,20 +1427,11 @@ NvU32 tpcMask; } NV2080_CTRL_GR_GET_TPC_MASK_PARAMS; -#define NV2080_CTRL_CMD_GR_SET_TPC_PARTITION_MODE (0x2080122cU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GR_INTERFACE_ID << 8) | 0x2C" */ - -typedef NV0080_CTRL_GR_TPC_PARTITION_MODE_PARAMS NV2080_CTRL_GR_SET_TPC_PARTITION_MODE_PARAMS; - -// FINN PORT: The below type was generated by the FINN port to -// ensure that all API's have a unique structure associated -// with them! -#define NV2080_CTRL_CMD_GR_SET_TPC_PARTITION_MODE_FINN_PARAMS_MESSAGE_ID (0x2CU) - -typedef struct NV2080_CTRL_CMD_GR_SET_TPC_PARTITION_MODE_FINN_PARAMS { - NV_DECLARE_ALIGNED(NV2080_CTRL_GR_SET_TPC_PARTITION_MODE_PARAMS params, 8); -} NV2080_CTRL_CMD_GR_SET_TPC_PARTITION_MODE_FINN_PARAMS; +#define NV2080_CTRL_CMD_GR_SET_TPC_PARTITION_MODE (0x2080122cU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GR_INTERFACE_ID << 8) | NV2080_CTRL_GR_SET_TPC_PARTITION_MODE_PARAMS_MESSAGE_ID" */ +#define NV2080_CTRL_GR_SET_TPC_PARTITION_MODE_PARAMS_MESSAGE_ID (0x2CU) +typedef NV0080_CTRL_GR_TPC_PARTITION_MODE_PARAMS NV2080_CTRL_GR_SET_TPC_PARTITION_MODE_PARAMS; /* * NV2080_CTRL_CMD_GR_GET_ENGINE_CONTEXT_PROPERTIES @@ -1701,20 +1744,11 @@ * This parameter specifies the routing information used to * disambiguate the target GR engine. */ -#define NV2080_CTRL_CMD_GR_GET_GPC_TILE_MAP (0x20801236U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GR_INTERFACE_ID << 8) | 0x36" */ - -typedef NV2080_CTRL_GR_SET_GPC_TILE_MAP_PARAMS NV2080_CTRL_GR_GET_GPC_TILE_MAP_PARAMS; - -// FINN PORT: The below type was generated by the FINN port to -// ensure that all API's have a unique structure associated -// with them! -#define NV2080_CTRL_CMD_GR_GET_GPC_TILE_MAP_FINN_PARAMS_MESSAGE_ID (0x36U) - -typedef struct NV2080_CTRL_CMD_GR_GET_GPC_TILE_MAP_FINN_PARAMS { - NV_DECLARE_ALIGNED(NV2080_CTRL_GR_GET_GPC_TILE_MAP_PARAMS params, 8); -} NV2080_CTRL_CMD_GR_GET_GPC_TILE_MAP_FINN_PARAMS; +#define NV2080_CTRL_CMD_GR_GET_GPC_TILE_MAP (0x20801236U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GR_INTERFACE_ID << 8) | NV2080_CTRL_GR_GET_GPC_TILE_MAP_PARAMS_MESSAGE_ID" */ +#define NV2080_CTRL_GR_GET_GPC_TILE_MAP_PARAMS_MESSAGE_ID (0x36U) +typedef NV2080_CTRL_GR_SET_GPC_TILE_MAP_PARAMS NV2080_CTRL_GR_GET_GPC_TILE_MAP_PARAMS; /* * NV2080_CTRL_CMD_GR_GET_ZCULL_MASK diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080grmgr.h nvidia-open-gpu-kernel-modules-535.161.08/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080grmgr.h --- nvidia-open-gpu-kernel-modules-525.147.05/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080grmgr.h 2023-10-25 20:22:14.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080grmgr.h 2024-03-05 22:15:06.000000000 +0000 @@ -27,7 +27,7 @@ // // This file was generated with FINN, an NVIDIA coding tool. -// Source file: ctrl/ctrl2080/ctrl2080grmgr.finn +// Source file: ctrl/ctrl2080/ctrl2080grmgr.finn // #include "ctrl/ctrl2080/ctrl2080base.h" diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080gsp.h nvidia-open-gpu-kernel-modules-535.161.08/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080gsp.h --- nvidia-open-gpu-kernel-modules-525.147.05/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080gsp.h 2023-10-25 20:22:14.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080gsp.h 2024-03-05 22:15:06.000000000 +0000 @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 2018-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2018-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -27,7 +27,7 @@ // // This file was generated with FINN, an NVIDIA coding tool. -// Source file: ctrl/ctrl2080/ctrl2080gsp.finn +// Source file: ctrl/ctrl2080/ctrl2080gsp.finn // #include "ctrl/ctrl2080/ctrl2080base.h" @@ -79,4 +79,52 @@ #define NV2080_CTRL_GSP_GET_FEATURES_UVM_ENABLED_FALSE (0x00000000) #define NV2080_CTRL_GSP_GET_FEATURES_UVM_ENABLED_TRUE (0x00000001) +/* + * NV2080_CTRL_CMD_GSP_GET_RM_HEAP_STATS + * + * This command reports the current GSP-RM heap usage statistics. + * + * managedSize + * The total size in bytes of the underlying heap. Note that not all memory + * will be allocatable, due to fragmentation and memory allocator/tracking + * overhead. + * current + * An NV2080_CTRL_GSP_RM_HEAP_STATS_SNAPSHOT record corresponding to + * GSP-RM heap usage at the time this command is called. + * peak + * An NV2080_CTRL_GSP_RM_HEAP_STATS_SNAPSHOT record corresponding to + * the "high water mark" of heap usage since GSP-RM was started. + */ +#define NV2080_CTRL_CMD_GSP_GET_RM_HEAP_STATS (0x20803602) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GSP_INTERFACE_ID << 8) | NV2080_CTRL_GSP_GET_RM_HEAP_STATS_PARAMS_MESSAGE_ID" */ + +/* + * NV2080_CTRL_GSP_RM_HEAP_STATS_SNAPSHOT + * + * This record represents a set of heap measurements at a given point in time. + * + * allocatedSize + * Allocated memory size, in bytes. This value does not include overhead used + * by the underlying allocator for padding/metadata, but does include the + * NvPort memory tracking overhead. + * usableSize + * Allocated memory size excluding all metadata, in bytes. This value does + * not include the NvPort memory tracking overhead. + * memTrackOverhead + * Allocated memory size used for NvPort memory tracking. + */ +typedef struct NV2080_CTRL_GSP_RM_HEAP_STATS_SNAPSHOT { + NV_DECLARE_ALIGNED(NvU64 allocatedSize, 8); + NV_DECLARE_ALIGNED(NvU64 usableSize, 8); + NV_DECLARE_ALIGNED(NvU64 memTrackOverhead, 8); + NvU32 allocationCount; +} NV2080_CTRL_GSP_RM_HEAP_STATS_SNAPSHOT; + +#define NV2080_CTRL_GSP_GET_RM_HEAP_STATS_PARAMS_MESSAGE_ID (0x2U) + +typedef struct NV2080_CTRL_GSP_GET_RM_HEAP_STATS_PARAMS { + NV_DECLARE_ALIGNED(NvU64 managedSize, 8); + NV_DECLARE_ALIGNED(NV2080_CTRL_GSP_RM_HEAP_STATS_SNAPSHOT current, 8); + NV_DECLARE_ALIGNED(NV2080_CTRL_GSP_RM_HEAP_STATS_SNAPSHOT peak, 8); +} NV2080_CTRL_GSP_GET_RM_HEAP_STATS_PARAMS; + // _ctrl2080gsp_h_ diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080hshub.h nvidia-open-gpu-kernel-modules-535.161.08/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080hshub.h --- nvidia-open-gpu-kernel-modules-525.147.05/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080hshub.h 2023-10-25 20:22:14.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080hshub.h 2024-03-05 22:15:06.000000000 +0000 @@ -27,7 +27,7 @@ // // This file was generated with FINN, an NVIDIA coding tool. -// Source file: ctrl/ctrl2080/ctrl2080hshub.finn +// Source file: ctrl/ctrl2080/ctrl2080hshub.finn // #include "ctrl/ctrl2080/ctrl2080base.h" diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080i2c.h nvidia-open-gpu-kernel-modules-535.161.08/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080i2c.h --- nvidia-open-gpu-kernel-modules-525.147.05/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080i2c.h 2023-10-25 20:22:14.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080i2c.h 2024-03-05 22:15:06.000000000 +0000 @@ -27,7 +27,7 @@ // // This file was generated with FINN, an NVIDIA coding tool. -// Source file: ctrl/ctrl2080/ctrl2080i2c.finn +// Source file: ctrl/ctrl2080/ctrl2080i2c.finn // #include "ctrl/ctrl2080/ctrl2080base.h" @@ -228,11 +228,18 @@ NvU8 buffer[(NV2080_CTRL_I2C_MAX_ENTRIES - 1)]; } NV2080_CTRL_I2C_RW_REG_PARAMS; +#define NV2080_CTRL_CMD_I2C_READ_REG (0x20800603) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_I2C_INTERFACE_ID << 8) | NV2080_CTRL_I2C_READ_REG_PARAMS_MESSAGE_ID" */ + // provide NV2080_CTRL_I2C_READ_REG_PARAMS as the historical name +#define NV2080_CTRL_I2C_READ_REG_PARAMS_MESSAGE_ID (0x3U) + typedef NV2080_CTRL_I2C_RW_REG_PARAMS NV2080_CTRL_I2C_READ_REG_PARAMS; -#define NV2080_CTRL_CMD_I2C_READ_REG (0x20800603) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_I2C_INTERFACE_ID << 8) | 0x3" */ -#define NV2080_CTRL_CMD_I2C_WRITE_REG (0x20800604) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_I2C_INTERFACE_ID << 8) | 0x4" */ +#define NV2080_CTRL_CMD_I2C_WRITE_REG (0x20800604) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_I2C_INTERFACE_ID << 8) | NV2080_CTRL_I2C_WRITE_REG_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_I2C_WRITE_REG_PARAMS_MESSAGE_ID (0x4U) + +typedef NV2080_CTRL_I2C_RW_REG_PARAMS NV2080_CTRL_I2C_WRITE_REG_PARAMS; /* * NV006F_CTRL_CMD_SYSTEM_I2C_ACCESS @@ -273,7 +280,7 @@ * NV_ERR_INVALID_ARGUMENT */ -#define NV2080_CTRL_CMD_I2C_ACCESS (0x20800610) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_I2C_INTERFACE_ID << 8) | NV2080_CTRL_I2C_ACCESS_PARAMS_MESSAGE_ID" */ +#define NV2080_CTRL_CMD_I2C_ACCESS (0x20800610) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_I2C_INTERFACE_ID << 8) | NV2080_CTRL_I2C_ACCESS_PARAMS_MESSAGE_ID" */ #define NV2080_CTRL_I2C_ACCESS_PARAMS_MESSAGE_ID (0x10U) diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080illum.h nvidia-open-gpu-kernel-modules-535.161.08/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080illum.h --- nvidia-open-gpu-kernel-modules-525.147.05/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080illum.h 2023-10-25 20:22:14.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080illum.h 2024-03-05 22:15:06.000000000 +0000 @@ -25,7 +25,7 @@ // // This file was generated with FINN, an NVIDIA coding tool. -// Source file: ctrl/ctrl2080/ctrl2080illum.finn +// Source file: ctrl/ctrl2080/ctrl2080illum.finn // diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080internal.h nvidia-open-gpu-kernel-modules-535.161.08/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080internal.h --- nvidia-open-gpu-kernel-modules-525.147.05/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080internal.h 2023-10-25 20:22:14.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080internal.h 2024-03-05 22:15:07.000000000 +0000 @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 2020-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2020-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -27,7 +27,7 @@ // // This file was generated with FINN, an NVIDIA coding tool. -// Source file: ctrl/ctrl2080/ctrl2080internal.finn +// Source file: ctrl/ctrl2080/ctrl2080internal.finn // #include "nvimpshared.h" @@ -38,9 +38,11 @@ #include "ctrl/ctrl0080/ctrl0080msenc.h" /* NV0080_CTRL_MSENC_CAPS_TBL_SIZE */ #include "ctrl/ctrl0080/ctrl0080bsp.h" /* NV0080_CTRL_BSP_CAPS_TBL_SIZE */ #include "ctrl/ctrl2080/ctrl2080fifo.h" /* NV2080_CTRL_FIFO_UPDATE_CHANNEL_INFO */ +#include "ctrl/ctrl0073/ctrl0073system.h" /* NV0073_CTRL_SYSTEM_ACPI_ID_MAP_MAX_DISPLAYS */ #include "ctrl/ctrl0000/ctrl0000system.h" #include "ctrl/ctrl90f1.h" #include "ctrl/ctrl30f1.h" +#include "nvcfg_sdk.h" /*! * NV2080_CTRL_CMD_INTERNAL_DISPLAY_GET_STATIC_INFO @@ -135,6 +137,9 @@ /*! Ampere PLC bug */ NvBool bDisablePlcForCertainOffsetsBug3046774; + + /*! FB override Start KB */ + NV_DECLARE_ALIGNED(NvU64 fbOverrideStartKb, 8); } NV2080_CTRL_INTERNAL_MEMSYS_GET_STATIC_CONFIG_PARAMS; /*! @@ -148,6 +153,9 @@ * This command sends access counter buffer pages allocated by CPU-RM * to be setup and enabled in physical RM. * + * accessCounterIndex + * Index of access counter buffer to register. + * * bufferSize * Size of the access counter buffer to register. * @@ -163,6 +171,7 @@ #define NV2080_CTRL_INTERNAL_UVM_REGISTER_ACCESS_CNTR_BUFFER_PARAMS_MESSAGE_ID (0x1DU) typedef struct NV2080_CTRL_INTERNAL_UVM_REGISTER_ACCESS_CNTR_BUFFER_PARAMS { + NvU32 accessCounterIndex; NvU32 bufferSize; NV_DECLARE_ALIGNED(NvU64 bufferPteArray[NV2080_CTRL_INTERNAL_UVM_ACCESS_CNTR_BUFFER_MAX_PAGES], 8); } NV2080_CTRL_INTERNAL_UVM_REGISTER_ACCESS_CNTR_BUFFER_PARAMS; @@ -172,65 +181,52 @@ * * This command requests physical RM to disable the access counter buffer. * - * Possible status values returned are: - * NV_OK - */ -#define NV2080_CTRL_CMD_INTERNAL_UVM_UNREGISTER_ACCESS_CNTR_BUFFER (0x20800a1e) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | 0x1E" */ - -/* - * NV2080_CTRL_CMD_INTERNAL_UVM_SERVICE_ACCESS_CNTR_BUFFER - * - * This command requests physical RM to service the access counter buffer. + * accessCounterIndex + * Index of access counter buffer to unregister. * * Possible status values returned are: * NV_OK */ -#define NV2080_CTRL_CMD_INTERNAL_UVM_SERVICE_ACCESS_CNTR_BUFFER (0x20800a21) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | 0x21" */ +#define NV2080_CTRL_CMD_INTERNAL_UVM_UNREGISTER_ACCESS_CNTR_BUFFER (0x20800a1e) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_UVM_UNREGISTER_ACCESS_CNTR_BUFFER_PARAMS_MESSAGE_ID" */ -/* - * NV2080_CTRL_CMD_INTERNAL_UVM_GET_ACCESS_CNTR_BUFFER_SIZE - * - * This command retrieves the access counter buffer size from physical RM. - * - * bufferSize[OUT] - * Size of the access counter buffer. - * - * Possible status values returned are: - * NV_OK - */ -#define NV2080_CTRL_CMD_INTERNAL_UVM_GET_ACCESS_CNTR_BUFFER_SIZE (0x20800a29) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_UVM_GET_ACCESS_CNTR_BUFFER_SIZE_PARAMS_MESSAGE_ID" */ - -#define NV2080_CTRL_INTERNAL_UVM_GET_ACCESS_CNTR_BUFFER_SIZE_PARAMS_MESSAGE_ID (0x29U) +#define NV2080_CTRL_INTERNAL_UVM_UNREGISTER_ACCESS_CNTR_BUFFER_PARAMS_MESSAGE_ID (0x1EU) -typedef struct NV2080_CTRL_INTERNAL_UVM_GET_ACCESS_CNTR_BUFFER_SIZE_PARAMS { - NvU32 bufferSize; -} NV2080_CTRL_INTERNAL_UVM_GET_ACCESS_CNTR_BUFFER_SIZE_PARAMS; +typedef struct NV2080_CTRL_INTERNAL_UVM_UNREGISTER_ACCESS_CNTR_BUFFER_PARAMS { + NvU32 accessCounterIndex; +} NV2080_CTRL_INTERNAL_UVM_UNREGISTER_ACCESS_CNTR_BUFFER_PARAMS; -#define NV2080_CTRL_INTERNAL_GR_MAX_ENGINES 8 +#define NV2080_CTRL_INTERNAL_GR_MAX_ENGINES 8 /*! * @ref NV2080_CTRL_CMD_GR_GET_CAPS_V2 */ -#define NV2080_CTRL_CMD_INTERNAL_STATIC_KGR_GET_CAPS (0x20800a1f) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | 0x1F" */ typedef struct NV2080_CTRL_INTERNAL_STATIC_GR_CAPS { NvU8 capsTbl[NV0080_CTRL_GR_CAPS_TBL_SIZE]; } NV2080_CTRL_INTERNAL_STATIC_GR_CAPS; + +#define NV2080_CTRL_INTERNAL_STATIC_GR_GET_CAPS_PARAMS_MESSAGE_ID (0x20U) + typedef struct NV2080_CTRL_INTERNAL_STATIC_GR_GET_CAPS_PARAMS { NV2080_CTRL_INTERNAL_STATIC_GR_CAPS engineCaps[NV2080_CTRL_INTERNAL_GR_MAX_ENGINES]; } NV2080_CTRL_INTERNAL_STATIC_GR_GET_CAPS_PARAMS; +#define NV2080_CTRL_CMD_INTERNAL_STATIC_KGR_GET_CAPS (0x20800a1f) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_STATIC_KGR_GET_CAPS_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_INTERNAL_STATIC_KGR_GET_CAPS_PARAMS_MESSAGE_ID (0x1FU) + +typedef NV2080_CTRL_INTERNAL_STATIC_GR_GET_CAPS_PARAMS NV2080_CTRL_INTERNAL_STATIC_KGR_GET_CAPS_PARAMS; + /*! * @ref NV2080_CTRL_CMD_GR_GET_GLOBAL_SM_ORDER * @ref NV2080_CTRL_CMD_GR_GET_SM_TO_GPC_TPC_MAPPINGS */ -#define NV2080_CTRL_CMD_INTERNAL_STATIC_KGR_GET_GLOBAL_SM_ORDER (0x20800a22) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | 0x22" */ -#define NV2080_CTRL_INTERNAL_GR_MAX_SM 240 +#define NV2080_CTRL_INTERNAL_GR_MAX_SM 240 typedef struct NV2080_CTRL_INTERNAL_STATIC_GR_GLOBAL_SM_ORDER { struct { @@ -246,10 +242,17 @@ NvU16 numTpc; } NV2080_CTRL_INTERNAL_STATIC_GR_GLOBAL_SM_ORDER; +#define NV2080_CTRL_INTERNAL_STATIC_GR_GET_GLOBAL_SM_ORDER_PARAMS_MESSAGE_ID (0x23U) + typedef struct NV2080_CTRL_INTERNAL_STATIC_GR_GET_GLOBAL_SM_ORDER_PARAMS { NV2080_CTRL_INTERNAL_STATIC_GR_GLOBAL_SM_ORDER globalSmOrder[NV2080_CTRL_INTERNAL_GR_MAX_ENGINES]; } NV2080_CTRL_INTERNAL_STATIC_GR_GET_GLOBAL_SM_ORDER_PARAMS; +#define NV2080_CTRL_CMD_INTERNAL_STATIC_KGR_GET_GLOBAL_SM_ORDER (0x20800a22) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_STATIC_KGR_GET_GLOBAL_SM_ORDER_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_INTERNAL_STATIC_KGR_GET_GLOBAL_SM_ORDER_PARAMS_MESSAGE_ID (0x22U) + +typedef NV2080_CTRL_INTERNAL_STATIC_GR_GET_GLOBAL_SM_ORDER_PARAMS NV2080_CTRL_INTERNAL_STATIC_KGR_GET_GLOBAL_SM_ORDER_PARAMS; /*! * Retrieve BSP Static data. @@ -288,15 +291,14 @@ } NV2080_CTRL_INTERNAL_MSENC_GET_CAPS_PARAMS; -#define NV2080_CTRL_INTERNAL_GR_MAX_GPC 12 -#define NV2080_CTRL_INTERNAL_MAX_TPC_PER_GPC_COUNT 10 +#define NV2080_CTRL_INTERNAL_GR_MAX_GPC 12 +#define NV2080_CTRL_INTERNAL_MAX_TPC_PER_GPC_COUNT 10 /*! * @ref NV2080_CTRL_CMD_GR_GET_GPC_MASK * @ref NV2080_CTRL_CMD_GR_GET_TPC_MASK * @ref NV2080_CTRL_CMD_GR_GET_PHYS_GPC_MASK */ -#define NV2080_CTRL_CMD_INTERNAL_STATIC_KGR_GET_FLOORSWEEPING_MASKS (0x20800a26) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | 0x26" */ @@ -328,6 +330,8 @@ NvU32 numGfxTpc; } NV2080_CTRL_INTERNAL_STATIC_GR_FLOORSWEEPING_MASKS; +#define NV2080_CTRL_INTERNAL_STATIC_GR_GET_FLOORSWEEPING_MASKS_PARAMS_MESSAGE_ID (0x27U) + typedef struct NV2080_CTRL_INTERNAL_STATIC_GR_GET_FLOORSWEEPING_MASKS_PARAMS { /*! * floorsweeping masks which are indexed via local GR index @@ -335,6 +339,12 @@ NV2080_CTRL_INTERNAL_STATIC_GR_FLOORSWEEPING_MASKS floorsweepingMasks[NV2080_CTRL_INTERNAL_GR_MAX_ENGINES]; } NV2080_CTRL_INTERNAL_STATIC_GR_GET_FLOORSWEEPING_MASKS_PARAMS; +#define NV2080_CTRL_CMD_INTERNAL_STATIC_KGR_GET_FLOORSWEEPING_MASKS (0x20800a26) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_STATIC_KGR_GET_FLOORSWEEPING_MASKS_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_INTERNAL_STATIC_KGR_GET_FLOORSWEEPING_MASKS_PARAMS_MESSAGE_ID (0x26U) + +typedef NV2080_CTRL_INTERNAL_STATIC_GR_GET_FLOORSWEEPING_MASKS_PARAMS NV2080_CTRL_INTERNAL_STATIC_KGR_GET_FLOORSWEEPING_MASKS_PARAMS; + /* * NV2080_CTRL_CMD_KGR_GET_CTX_BUFFER_PTES * @@ -382,7 +392,6 @@ * @ref NV2080_CTRL_CMD_GR_GET_INFO * @ref NV2080_CTRL_CMD_GR_GET_INFO_V2 */ -#define NV2080_CTRL_CMD_INTERNAL_STATIC_KGR_GET_INFO (0x20800a2a) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | 0x2A" */ @@ -397,14 +406,21 @@ typedef struct NV2080_CTRL_INTERNAL_STATIC_GR_INFO { NV2080_CTRL_INTERNAL_GR_INFO infoList[NV0080_CTRL_GR_INFO_MAX_SIZE]; } NV2080_CTRL_INTERNAL_STATIC_GR_INFO; +#define NV2080_CTRL_INTERNAL_STATIC_GR_GET_INFO_PARAMS_MESSAGE_ID (0x2BU) + typedef struct NV2080_CTRL_INTERNAL_STATIC_GR_GET_INFO_PARAMS { NV2080_CTRL_INTERNAL_STATIC_GR_INFO engineInfo[NV2080_CTRL_INTERNAL_GR_MAX_ENGINES]; } NV2080_CTRL_INTERNAL_STATIC_GR_GET_INFO_PARAMS; +#define NV2080_CTRL_CMD_INTERNAL_STATIC_KGR_GET_INFO (0x20800a2a) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_STATIC_KGR_GET_INFO_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_INTERNAL_STATIC_KGR_GET_INFO_PARAMS_MESSAGE_ID (0x2AU) + +typedef NV2080_CTRL_INTERNAL_STATIC_GR_GET_INFO_PARAMS NV2080_CTRL_INTERNAL_STATIC_KGR_GET_INFO_PARAMS; + /*! * @ref NV2080_CTRL_CMD_GR_GET_ZCULL_INFO */ -#define NV2080_CTRL_CMD_INTERNAL_STATIC_KGR_GET_ZCULL_INFO (0x20800a2c) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | 0x2C" */ @@ -421,14 +437,21 @@ NvU32 subregionHeightAlignPixels; } NV2080_CTRL_INTERNAL_STATIC_GR_ZCULL_INFO; +#define NV2080_CTRL_INTERNAL_STATIC_GR_GET_ZCULL_INFO_PARAMS_MESSAGE_ID (0x2DU) + typedef struct NV2080_CTRL_INTERNAL_STATIC_GR_GET_ZCULL_INFO_PARAMS { NV2080_CTRL_INTERNAL_STATIC_GR_ZCULL_INFO engineZcullInfo[NV2080_CTRL_INTERNAL_GR_MAX_ENGINES]; } NV2080_CTRL_INTERNAL_STATIC_GR_GET_ZCULL_INFO_PARAMS; +#define NV2080_CTRL_CMD_INTERNAL_STATIC_KGR_GET_ZCULL_INFO (0x20800a2c) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_STATIC_KGR_GET_ZCULL_INFO_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_INTERNAL_STATIC_KGR_GET_ZCULL_INFO_PARAMS_MESSAGE_ID (0x2CU) + +typedef NV2080_CTRL_INTERNAL_STATIC_GR_GET_ZCULL_INFO_PARAMS NV2080_CTRL_INTERNAL_STATIC_KGR_GET_ZCULL_INFO_PARAMS; + /*! * @ref NV2080_CTRL_CMD_GR_GET_ROP_INFO */ -#define NV2080_CTRL_CMD_INTERNAL_STATIC_KGR_GET_ROP_INFO (0x20800a2e) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | 0x2E" */ @@ -438,14 +461,21 @@ NvU32 ropOperationsCount; } NV2080_CTRL_INTERNAL_STATIC_GR_ROP_INFO; +#define NV2080_CTRL_INTERNAL_STATIC_GR_GET_ROP_INFO_PARAMS_MESSAGE_ID (0x2FU) + typedef struct NV2080_CTRL_INTERNAL_STATIC_GR_GET_ROP_INFO_PARAMS { NV2080_CTRL_INTERNAL_STATIC_GR_ROP_INFO engineRopInfo[NV2080_CTRL_INTERNAL_GR_MAX_ENGINES]; } NV2080_CTRL_INTERNAL_STATIC_GR_GET_ROP_INFO_PARAMS; +#define NV2080_CTRL_CMD_INTERNAL_STATIC_KGR_GET_ROP_INFO (0x20800a2e) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_STATIC_KGR_GET_ROP_INFO_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_INTERNAL_STATIC_KGR_GET_ROP_INFO_PARAMS_MESSAGE_ID (0x2EU) + +typedef NV2080_CTRL_INTERNAL_STATIC_GR_GET_ROP_INFO_PARAMS NV2080_CTRL_INTERNAL_STATIC_KGR_GET_ROP_INFO_PARAMS; + /*! * @ref NV2080_CTRL_CMD_GR_GET_PPC_MASK */ -#define NV2080_CTRL_CMD_INTERNAL_STATIC_KGR_GET_PPC_MASKS (0x20800a30) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | 0x30" */ @@ -453,15 +483,22 @@ NvU32 mask[NV2080_CTRL_INTERNAL_GR_MAX_GPC]; } NV2080_CTRL_INTERNAL_STATIC_GR_PPC_MASKS; +#define NV2080_CTRL_INTERNAL_STATIC_GR_GET_PPC_MASKS_PARAMS_MESSAGE_ID (0x31U) + typedef struct NV2080_CTRL_INTERNAL_STATIC_GR_GET_PPC_MASKS_PARAMS { NV2080_CTRL_INTERNAL_STATIC_GR_PPC_MASKS enginePpcMasks[NV2080_CTRL_INTERNAL_GR_MAX_ENGINES]; } NV2080_CTRL_INTERNAL_STATIC_GR_GET_PPC_MASKS_PARAMS; +#define NV2080_CTRL_CMD_INTERNAL_STATIC_KGR_GET_PPC_MASKS (0x20800a30) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_STATIC_KGR_GET_PPC_MASKS_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_INTERNAL_STATIC_KGR_GET_PPC_MASKS_PARAMS_MESSAGE_ID (0x30U) + +typedef NV2080_CTRL_INTERNAL_STATIC_GR_GET_PPC_MASKS_PARAMS NV2080_CTRL_INTERNAL_STATIC_KGR_GET_PPC_MASKS_PARAMS; + /*! * @ref NV2080_CTRL_CMD_GR_GET_ENGINE_CONTEXT_PROPERTIES * @ref NV2080_CTRL_CMD_GR_GET_ATTRIBUTE_BUFFER_SIZE */ -#define NV2080_CTRL_CMD_INTERNAL_STATIC_KGR_GET_CONTEXT_BUFFERS_INFO (0x20800a32) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | 0x32" */ @@ -476,14 +513,21 @@ NV2080_CTRL_INTERNAL_ENGINE_CONTEXT_BUFFER_INFO engine[NV2080_CTRL_INTERNAL_ENGINE_CONTEXT_PROPERTIES_ENGINE_ID_COUNT]; } NV2080_CTRL_INTERNAL_STATIC_GR_CONTEXT_BUFFERS_INFO; +#define NV2080_CTRL_INTERNAL_STATIC_GR_GET_CONTEXT_BUFFERS_INFO_PARAMS_MESSAGE_ID (0x33U) + typedef struct NV2080_CTRL_INTERNAL_STATIC_GR_GET_CONTEXT_BUFFERS_INFO_PARAMS { NV2080_CTRL_INTERNAL_STATIC_GR_CONTEXT_BUFFERS_INFO engineContextBuffersInfo[NV2080_CTRL_INTERNAL_GR_MAX_ENGINES]; } NV2080_CTRL_INTERNAL_STATIC_GR_GET_CONTEXT_BUFFERS_INFO_PARAMS; +#define NV2080_CTRL_CMD_INTERNAL_STATIC_KGR_GET_CONTEXT_BUFFERS_INFO (0x20800a32) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_STATIC_KGR_GET_CONTEXT_BUFFERS_INFO_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_INTERNAL_STATIC_KGR_GET_CONTEXT_BUFFERS_INFO_PARAMS_MESSAGE_ID (0x32U) + +typedef NV2080_CTRL_INTERNAL_STATIC_GR_GET_CONTEXT_BUFFERS_INFO_PARAMS NV2080_CTRL_INTERNAL_STATIC_KGR_GET_CONTEXT_BUFFERS_INFO_PARAMS; + /*! * @ref NV2080_CTRL_CMD_GR_GET_SM_ISSUE_RATE_MODIFIER */ -#define NV2080_CTRL_CMD_INTERNAL_STATIC_KGR_GET_SM_ISSUE_RATE_MODIFIER (0x20800a34) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | 0x34" */ @@ -499,10 +543,18 @@ NvU8 imla4; } NV2080_CTRL_INTERNAL_STATIC_GR_SM_ISSUE_RATE_MODIFIER; +#define NV2080_CTRL_INTERNAL_STATIC_GR_GET_SM_ISSUE_RATE_MODIFIER_PARAMS_MESSAGE_ID (0x35U) + typedef struct NV2080_CTRL_INTERNAL_STATIC_GR_GET_SM_ISSUE_RATE_MODIFIER_PARAMS { NV2080_CTRL_INTERNAL_STATIC_GR_SM_ISSUE_RATE_MODIFIER smIssueRateModifier[NV2080_CTRL_INTERNAL_GR_MAX_ENGINES]; } NV2080_CTRL_INTERNAL_STATIC_GR_GET_SM_ISSUE_RATE_MODIFIER_PARAMS; +#define NV2080_CTRL_CMD_INTERNAL_STATIC_KGR_GET_SM_ISSUE_RATE_MODIFIER (0x20800a34) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_STATIC_KGR_GET_SM_ISSUE_RATE_MODIFIER_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_INTERNAL_STATIC_KGR_GET_SM_ISSUE_RATE_MODIFIER_PARAMS_MESSAGE_ID (0x34U) + +typedef NV2080_CTRL_INTERNAL_STATIC_GR_GET_SM_ISSUE_RATE_MODIFIER_PARAMS NV2080_CTRL_INTERNAL_STATIC_KGR_GET_SM_ISSUE_RATE_MODIFIER_PARAMS; + /* * NV2080_CTRL_INTERNAL_GPU_GET_CHIP_INFO_PARAMS * @@ -554,9 +606,11 @@ NV_DECLARE_ALIGNED(NV2080_CTRL_GR_ROUTE_INFO grRouteInfo, 8); NvBool bEnable; } NV2080_CTRL_INTERNAL_GR_FECS_TRACE_HW_ENABLE_PARAMS; + #define NV2080_CTRL_INTERNAL_GR_SET_FECS_TRACE_HW_ENABLE_PARAMS_MESSAGE_ID (0x37U) typedef NV2080_CTRL_INTERNAL_GR_FECS_TRACE_HW_ENABLE_PARAMS NV2080_CTRL_INTERNAL_GR_SET_FECS_TRACE_HW_ENABLE_PARAMS; + #define NV2080_CTRL_INTERNAL_GR_GET_FECS_TRACE_HW_ENABLE_PARAMS_MESSAGE_ID (0x38U) typedef NV2080_CTRL_INTERNAL_GR_FECS_TRACE_HW_ENABLE_PARAMS NV2080_CTRL_INTERNAL_GR_GET_FECS_TRACE_HW_ENABLE_PARAMS; @@ -600,9 +654,11 @@ #define NV2080_CTRL_INTERNAL_GR_SET_FECS_TRACE_RD_OFFSET_PARAMS_MESSAGE_ID (0x39U) typedef NV2080_CTRL_INTERNAL_GR_FECS_TRACE_OFFSET_PARAMS NV2080_CTRL_INTERNAL_GR_SET_FECS_TRACE_RD_OFFSET_PARAMS; + #define NV2080_CTRL_INTERNAL_GR_SET_FECS_TRACE_WR_OFFSET_PARAMS_MESSAGE_ID (0x3AU) typedef NV2080_CTRL_INTERNAL_GR_FECS_TRACE_OFFSET_PARAMS NV2080_CTRL_INTERNAL_GR_SET_FECS_TRACE_WR_OFFSET_PARAMS; + #define NV2080_CTRL_INTERNAL_GR_GET_FECS_TRACE_RD_OFFSET_PARAMS_MESSAGE_ID (0x3BU) typedef NV2080_CTRL_INTERNAL_GR_FECS_TRACE_OFFSET_PARAMS NV2080_CTRL_INTERNAL_GR_GET_FECS_TRACE_RD_OFFSET_PARAMS; @@ -629,6 +685,7 @@ typedef struct NV2080_CTRL_INTERNAL_STATIC_GR_GET_FECS_RECORD_SIZE_PARAMS { NV2080_CTRL_INTERNAL_STATIC_GR_GET_FECS_RECORD_SIZE fecsRecordSize[NV2080_CTRL_INTERNAL_GR_MAX_ENGINES]; } NV2080_CTRL_INTERNAL_STATIC_GR_GET_FECS_RECORD_SIZE_PARAMS; + #define NV2080_CTRL_CMD_INTERNAL_STATIC_KGR_GET_FECS_RECORD_SIZE_PARAMS_MESSAGE_ID (0x3DU) typedef NV2080_CTRL_INTERNAL_STATIC_GR_GET_FECS_RECORD_SIZE_PARAMS NV2080_CTRL_CMD_INTERNAL_STATIC_KGR_GET_FECS_RECORD_SIZE_PARAMS; @@ -656,8 +713,6 @@ -#define NV2080_CTRL_CMD_INTERNAL_STATIC_KGR_GET_FECS_TRACE_DEFINES (0x20800a3f) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | 0x3F" */ - typedef struct NV2080_CTRL_INTERNAL_STATIC_GR_GET_FECS_TRACE_DEFINES { NvU32 fecsRecordSize; NvU32 timestampHiTagMask; @@ -666,10 +721,18 @@ NvU8 numLowerBitsZeroShift; } NV2080_CTRL_INTERNAL_STATIC_GR_GET_FECS_TRACE_DEFINES; +#define NV2080_CTRL_INTERNAL_STATIC_GR_GET_FECS_TRACE_DEFINES_PARAMS_MESSAGE_ID (0x3EU) + typedef struct NV2080_CTRL_INTERNAL_STATIC_GR_GET_FECS_TRACE_DEFINES_PARAMS { NV_DECLARE_ALIGNED(NV2080_CTRL_INTERNAL_STATIC_GR_GET_FECS_TRACE_DEFINES fecsTraceDefines[NV2080_CTRL_INTERNAL_GR_MAX_ENGINES], 8); } NV2080_CTRL_INTERNAL_STATIC_GR_GET_FECS_TRACE_DEFINES_PARAMS; +#define NV2080_CTRL_CMD_INTERNAL_STATIC_KGR_GET_FECS_TRACE_DEFINES (0x20800a3f) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_STATIC_KGR_GET_FECS_TRACE_DEFINES_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_INTERNAL_STATIC_KGR_GET_FECS_TRACE_DEFINES_PARAMS_MESSAGE_ID (0x3FU) + +typedef NV2080_CTRL_INTERNAL_STATIC_GR_GET_FECS_TRACE_DEFINES_PARAMS NV2080_CTRL_INTERNAL_STATIC_KGR_GET_FECS_TRACE_DEFINES_PARAMS; + /** * NV2080_CTRL_CMD_INTERNAL_GET_DEVICE_INFO_TABLE * @@ -730,6 +793,37 @@ NV2080_CTRL_INTERNAL_CONSTRUCTED_FALCON_INFO constructedFalconsTable[NV2080_CTRL_CMD_INTERNAL_MAX_CONSTRUCTED_FALCONS]; } NV2080_CTRL_INTERNAL_GET_CONSTRUCTED_FALCON_INFO_PARAMS; +typedef struct NV2080_CTRL_INTERNAL_NV_RANGE { + NV_DECLARE_ALIGNED(NvU64 lo, 8); + NV_DECLARE_ALIGNED(NvU64 hi, 8); +} NV2080_CTRL_INTERNAL_NV_RANGE; + +/*! + * NV2080_CTRL_INTERNAL_MIGMGR_PROMOTE_GPU_INSTANCE_MEM_RANGE_PARAMS + * + * This structure specifies a target swizz-id and mem_range to update + * + * swizzId[IN] + * - Targeted swizz-id for which the memRange is being set + * + * memAddrRange[IN] + * - Memory Range for given GPU instance + */ +#define NV2080_CTRL_INTERNAL_MIGMGR_PROMOTE_GPU_INSTANCE_MEM_RANGE_PARAMS_MESSAGE_ID (0x43U) + +typedef struct NV2080_CTRL_INTERNAL_MIGMGR_PROMOTE_GPU_INSTANCE_MEM_RANGE_PARAMS { + NvU32 swizzId; + NV_DECLARE_ALIGNED(NV2080_CTRL_INTERNAL_NV_RANGE memAddrRange, 8); +} NV2080_CTRL_INTERNAL_MIGMGR_PROMOTE_GPU_INSTANCE_MEM_RANGE_PARAMS; + +#define NV2080_CTRL_CMD_INTERNAL_KMIGMGR_PROMOTE_GPU_INSTANCE_MEM_RANGE (0x20800a44) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_KMIGMGR_PROMOTE_GPU_INSTANCE_MEM_RANGE_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_INTERNAL_KMIGMGR_PROMOTE_GPU_INSTANCE_MEM_RANGE_PARAMS_MESSAGE_ID (0x44U) + +typedef NV2080_CTRL_INTERNAL_MIGMGR_PROMOTE_GPU_INSTANCE_MEM_RANGE_PARAMS NV2080_CTRL_INTERNAL_KMIGMGR_PROMOTE_GPU_INSTANCE_MEM_RANGE_PARAMS; + +#define NV2080_CTRL_CMD_INTERNAL_MIGMGR_PROMOTE_GPU_INSTANCE_MEM_RANGE (0x20800a43) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_MIGMGR_PROMOTE_GPU_INSTANCE_MEM_RANGE_PARAMS_MESSAGE_ID" */ + /** * Get GR PDB properties synchronized between Kernel and Physical * @@ -739,16 +833,22 @@ -#define NV2080_CTRL_CMD_INTERNAL_STATIC_KGR_GET_PDB_PROPERTIES (0x20800a48) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | 0x48" */ - typedef struct NV2080_CTRL_INTERNAL_STATIC_GR_PDB_PROPERTIES { NvBool bPerSubCtxheaderSupported; } NV2080_CTRL_INTERNAL_STATIC_GR_PDB_PROPERTIES; +#define NV2080_CTRL_INTERNAL_STATIC_GR_GET_PDB_PROPERTIES_PARAMS_MESSAGE_ID (0x47U) + typedef struct NV2080_CTRL_INTERNAL_STATIC_GR_GET_PDB_PROPERTIES_PARAMS { NV2080_CTRL_INTERNAL_STATIC_GR_PDB_PROPERTIES pdbTable[NV2080_CTRL_INTERNAL_GR_MAX_ENGINES]; } NV2080_CTRL_INTERNAL_STATIC_GR_GET_PDB_PROPERTIES_PARAMS; +#define NV2080_CTRL_CMD_INTERNAL_STATIC_KGR_GET_PDB_PROPERTIES (0x20800a48) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_STATIC_KGR_GET_PDB_PROPERTIES_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_INTERNAL_STATIC_KGR_GET_PDB_PROPERTIES_PARAMS_MESSAGE_ID (0x48U) + +typedef NV2080_CTRL_INTERNAL_STATIC_GR_GET_PDB_PROPERTIES_PARAMS NV2080_CTRL_INTERNAL_STATIC_KGR_GET_PDB_PROPERTIES_PARAMS; + /*! * NV2080_CTRL_CMD_INTERNAL_DISPLAY_WRITE_INST_MEM * @@ -933,6 +1033,8 @@ * table [OUT] * Supported profiles. */ +#define NV2080_CTRL_INTERNAL_STATIC_MIGMGR_GET_PROFILES_PARAMS_MESSAGE_ID (0x4FU) + typedef struct NV2080_CTRL_INTERNAL_STATIC_MIGMGR_GET_PROFILES_PARAMS { NvU32 count; NV_DECLARE_ALIGNED(NV2080_CTRL_INTERNAL_MIGMGR_PROFILE_INFO table[NV2080_CTRL_INTERNAL_GRMGR_PARTITION_MAX_TYPES], 8); @@ -973,6 +1075,8 @@ +#define NV2080_CTRL_INTERNAL_STATIC_MIGMGR_GET_PARTITIONABLE_ENGINES_PARAMS_MESSAGE_ID (0x52U) + typedef struct NV2080_CTRL_INTERNAL_STATIC_MIGMGR_GET_PARTITIONABLE_ENGINES_PARAMS { NV_DECLARE_ALIGNED(NvU64 engineMask, 8); } NV2080_CTRL_INTERNAL_STATIC_MIGMGR_GET_PARTITIONABLE_ENGINES_PARAMS; @@ -1274,13 +1378,19 @@ typedef struct NV2080_CTRL_INTERNAL_GMMU_GET_STATIC_INFO_PARAMS { NvU32 replayableFaultBufferSize; + NvU32 replayableShadowFaultBufferMetadataSize; NvU32 nonReplayableFaultBufferSize; + NvU32 nonReplayableShadowFaultBufferMetadataSize; } NV2080_CTRL_INTERNAL_GMMU_GET_STATIC_INFO_PARAMS; /*! * @ref NV2080_CTRL_CMD_GR_GET_CTXSW_MODES */ -#define NV2080_CTRL_CMD_INTERNAL_GR_GET_CTXSW_MODES (0x20800a5a) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | 0x5A" */ +#define NV2080_CTRL_CMD_INTERNAL_GR_GET_CTXSW_MODES (0x20800a5a) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_GR_GET_CTXSW_MODES_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_INTERNAL_GR_GET_CTXSW_MODES_PARAMS_MESSAGE_ID (0x5AU) + +typedef NV2080_CTRL_GR_GET_CTXSW_MODES_PARAMS NV2080_CTRL_INTERNAL_GR_GET_CTXSW_MODES_PARAMS; /*! * NV2080_CTRL_CMD_INTERNAL_FB_GET_HEAP_RESERVATION_SIZE @@ -1299,16 +1409,43 @@ /*! * NV2080_CTRL_CMD_INTERNAL_INTR_GET_KERNEL_TABLE * - * tableLen [OUT] + * tableLen [OUT] * Number of valid records in table field. * - * table [OUT] + * table [OUT] * Interrupt table for Kernel RM. + * + * subtreeMap [OUT] + * Subtree range for each NV2080_INTR_CATEGORY. */ #define NV2080_CTRL_CMD_INTERNAL_INTR_GET_KERNEL_TABLE (0x20800a5c) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_INTR_GET_KERNEL_TABLE_PARAMS_MESSAGE_ID" */ #define NV2080_CTRL_INTERNAL_INTR_MAX_TABLE_SIZE 128 +/*! + * Categories of interrupts. + * + * Each of these categories get a separate range of interrupt subtrees (top + * level bits). + */ +typedef enum NV2080_INTR_CATEGORY { + NV2080_INTR_CATEGORY_DEFAULT = 0, + NV2080_INTR_CATEGORY_ESCHED_DRIVEN_ENGINE = 1, + NV2080_INTR_CATEGORY_ESCHED_DRIVEN_ENGINE_NOTIFICATION = 2, + NV2080_INTR_CATEGORY_RUNLIST = 3, + NV2080_INTR_CATEGORY_RUNLIST_NOTIFICATION = 4, + NV2080_INTR_CATEGORY_UVM_OWNED = 5, + NV2080_INTR_CATEGORY_UVM_SHARED = 6, + NV2080_INTR_CATEGORY_ENUM_COUNT = 7, +} NV2080_INTR_CATEGORY; + +#define NV2080_INTR_INVALID_SUBTREE NV_U8_MAX + +typedef struct NV2080_INTR_CATEGORY_SUBTREE_MAP { + NvU8 subtreeStart; + NvU8 subtreeEnd; +} NV2080_INTR_CATEGORY_SUBTREE_MAP; + typedef struct NV2080_CTRL_INTERNAL_INTR_GET_KERNEL_TABLE_ENTRY { NvU16 engineIdx; NvU32 pmcIntrMask; @@ -1321,6 +1458,7 @@ typedef struct NV2080_CTRL_INTERNAL_INTR_GET_KERNEL_TABLE_PARAMS { NvU32 tableLen; NV2080_CTRL_INTERNAL_INTR_GET_KERNEL_TABLE_ENTRY table[NV2080_CTRL_INTERNAL_INTR_MAX_TABLE_SIZE]; + NV2080_INTR_CATEGORY_SUBTREE_MAP subtreeMap[NV2080_INTR_CATEGORY_ENUM_COUNT]; } NV2080_CTRL_INTERNAL_INTR_GET_KERNEL_TABLE_PARAMS; /* Index to retrieve the needed heap space for specific module */ @@ -1405,11 +1543,6 @@ #define NV2080_CTRL_INTERNAL_MAX_SWIZZ_ID 15 -typedef struct NV2080_CTRL_INTERNAL_NV_RANGE { - NV_DECLARE_ALIGNED(NvU64 lo, 8); - NV_DECLARE_ALIGNED(NvU64 hi, 8); -} NV2080_CTRL_INTERNAL_NV_RANGE; - #define NV2080_CTRL_INTERNAL_STATIC_MIGMGR_GET_SWIZZ_ID_FB_MEM_PAGE_RANGES_PARAMS_MESSAGE_ID (0x60U) typedef struct NV2080_CTRL_INTERNAL_STATIC_MIGMGR_GET_SWIZZ_ID_FB_MEM_PAGE_RANGES_PARAMS { @@ -1438,29 +1571,41 @@ * @ref NV2080_CTRL_CMD_INTERNAL_STATIC_KMIGMGR_GET_PROFILES * @ref NV2080_CTRL_CMD_INTERNAL_STATIC_MIGMGR_GET_PROFILES */ -#define NV2080_CTRL_CMD_INTERNAL_STATIC_KMIGMGR_GET_PROFILES (0x20800a63) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | 0x63" */ +#define NV2080_CTRL_CMD_INTERNAL_STATIC_KMIGMGR_GET_PROFILES (0x20800a63) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_STATIC_KMIGMGR_GET_PROFILES_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_INTERNAL_STATIC_KMIGMGR_GET_PROFILES_PARAMS_MESSAGE_ID (0x63U) + +typedef NV2080_CTRL_INTERNAL_STATIC_MIGMGR_GET_PROFILES_PARAMS NV2080_CTRL_INTERNAL_STATIC_KMIGMGR_GET_PROFILES_PARAMS; /*! * @ref NV2080_CTRL_CMD_INTERNAL_STATIC_KMIGMGR_GET_VALID_SWIZZID_MASK * @ref NV2080_CTRL_CMD_INTERNAL_STATIC_MIGMGR_GET_VALID_SWIZZID_MASK */ -#define NV2080_CTRL_CMD_INTERNAL_STATIC_KMIGMGR_GET_VALID_SWIZZID_MASK (0x20800a64) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | 0x64" */ +#define NV2080_CTRL_CMD_INTERNAL_STATIC_KMIGMGR_GET_VALID_SWIZZID_MASK (0x20800a64) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | 0x64" */ /*! * NV2080_CTRL_CMD_INTERNAL_STATIC_KMIGMGR_GET_PARTITIONABLE_ENGINES * NV2080_CTRL_CMD_INTERNAL_STATIC_MIGMGR_GET_PARTITIONABLE_ENGINES */ -#define NV2080_CTRL_CMD_INTERNAL_STATIC_KMIGMGR_GET_PARTITIONABLE_ENGINES (0x20800a65) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | 0x65" */ +#define NV2080_CTRL_CMD_INTERNAL_STATIC_KMIGMGR_GET_PARTITIONABLE_ENGINES (0x20800a65) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_STATIC_KMIGMGR_GET_PARTITIONABLE_ENGINES_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_INTERNAL_STATIC_KMIGMGR_GET_PARTITIONABLE_ENGINES_PARAMS_MESSAGE_ID (0x65U) + +typedef NV2080_CTRL_INTERNAL_STATIC_MIGMGR_GET_PARTITIONABLE_ENGINES_PARAMS NV2080_CTRL_INTERNAL_STATIC_KMIGMGR_GET_PARTITIONABLE_ENGINES_PARAMS; /*! * NV2080_CTRL_CMD_INTERNAL_STATIC_KMIGMGR_GET_SWIZZ_ID_FB_MEM_PAGE_RANGES * NV2080_CTRL_CMD_INTERNAL_STATIC_MIGMGR_GET_SWIZZ_ID_FB_MEM_PAGE_RANGES */ -#define NV2080_CTRL_CMD_INTERNAL_STATIC_KMIGMGR_GET_SWIZZ_ID_FB_MEM_PAGE_RANGES (0x20800a66) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | 0x66" */ +#define NV2080_CTRL_CMD_INTERNAL_STATIC_KMIGMGR_GET_SWIZZ_ID_FB_MEM_PAGE_RANGES (0x20800a66) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_STATIC_KMIGMGR_GET_SWIZZ_ID_FB_MEM_PAGE_RANGES_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_INTERNAL_STATIC_KMIGMGR_GET_SWIZZ_ID_FB_MEM_PAGE_RANGES_PARAMS_MESSAGE_ID (0x66U) + +typedef NV2080_CTRL_INTERNAL_STATIC_MIGMGR_GET_SWIZZ_ID_FB_MEM_PAGE_RANGES_PARAMS NV2080_CTRL_INTERNAL_STATIC_KMIGMGR_GET_SWIZZ_ID_FB_MEM_PAGE_RANGES_PARAMS; /*! - * NV2080_CTRL_CMD_INTERNAL_KMEMSYS_GET_MIG_MEMORY_CONFIG * NV2080_CTRL_CMD_INTERNAL_MEMSYS_GET_MIG_MEMORY_CONFIG + * NV2080_CTRL_CMD_INTERNAL_KMEMSYS_GET_MIG_MEMORY_CONFIG * * This command retrieves memory config from HW * @@ -1479,8 +1624,9 @@ * memBoundaryCfgValInit [OUT] * Memory boundary config initial value (64KB aligned) */ -#define NV2080_CTRL_CMD_INTERNAL_KMEMSYS_GET_MIG_MEMORY_CONFIG (0x20800a67) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | 0x67" */ -#define NV2080_CTRL_CMD_INTERNAL_MEMSYS_GET_MIG_MEMORY_CONFIG (0x20800a68) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | 0x68" */ +#define NV2080_CTRL_CMD_INTERNAL_MEMSYS_GET_MIG_MEMORY_CONFIG (0x20800a68) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_MEMSYS_GET_MIG_MEMORY_CONFIG_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_INTERNAL_MEMSYS_GET_MIG_MEMORY_CONFIG_PARAMS_MESSAGE_ID (0x68U) typedef struct NV2080_CTRL_INTERNAL_MEMSYS_GET_MIG_MEMORY_CONFIG_PARAMS { NV_DECLARE_ALIGNED(NvU64 memBoundaryCfgA, 8); @@ -1490,6 +1636,12 @@ NvU32 memBoundaryCfgValInit; } NV2080_CTRL_INTERNAL_MEMSYS_GET_MIG_MEMORY_CONFIG_PARAMS; +#define NV2080_CTRL_CMD_INTERNAL_KMEMSYS_GET_MIG_MEMORY_CONFIG (0x20800a67) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_KMEMSYS_GET_MIG_MEMORY_CONFIG_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_INTERNAL_KMEMSYS_GET_MIG_MEMORY_CONFIG_PARAMS_MESSAGE_ID (0x67U) + +typedef NV2080_CTRL_INTERNAL_MEMSYS_GET_MIG_MEMORY_CONFIG_PARAMS NV2080_CTRL_INTERNAL_KMEMSYS_GET_MIG_MEMORY_CONFIG_PARAMS; + #define NV2080_CTRL_CMD_INTERNAL_MEMSYS_GET_MIG_MEMORY_PARTITION_TABLE (0x20800a6b) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_MEMSYS_GET_MIG_MEMORY_PARTITION_TABLE_PARAMS_MESSAGE_ID" */ #define NV2080_CTRL_INTERNAL_MEMSYS_GET_MIG_MEMORY_PARTITION_TABLE_SIZE 8 @@ -1679,6 +1831,10 @@ */ #define NV2080_CTRL_CMD_INTERNAL_GMMU_UNREGISTER_FAULT_BUFFER (0x20800a9c) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | 0x9C" */ +// Valid fault buffer types +#define NV2080_CTRL_FAULT_BUFFER_NON_REPLAYABLE (0x00000000) +#define NV2080_CTRL_FAULT_BUFFER_REPLAYABLE (0x00000001) + /* * NV2080_CTRL_CMD_INTERNAL_GMMU_REGISTER_CLIENT_SHADOW_FAULT_BUFFER * @@ -1694,21 +1850,49 @@ * shadowFaultBufferPteArray * Pages of client shadow fault buffer. * + * shadowFaultBufferType + * Replayable or non-replayable fault buffer + * + * faultBufferSharedMemoryPhysAddr + * Fault buffer shared memory address. Used only by the Replayable fault buffer. + * * Possible status values returned are: * NV_OK */ #define NV2080_CTRL_CMD_INTERNAL_GMMU_REGISTER_CLIENT_SHADOW_FAULT_BUFFER (0x20800a9d) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_GMMU_REGISTER_CLIENT_SHADOW_FAULT_BUFFER_PARAMS_MESSAGE_ID" */ -#define NV2080_CTRL_INTERNAL_GMMU_CLIENT_SHADOW_FAULT_BUFFER_MAX_PAGES 1500 +#define NV2080_CTRL_INTERNAL_GMMU_CLIENT_SHADOW_FAULT_BUFFER_MAX_PAGES 3000 #define NV2080_CTRL_INTERNAL_GMMU_REGISTER_CLIENT_SHADOW_FAULT_BUFFER_PARAMS_MESSAGE_ID (0x9DU) typedef struct NV2080_CTRL_INTERNAL_GMMU_REGISTER_CLIENT_SHADOW_FAULT_BUFFER_PARAMS { NV_DECLARE_ALIGNED(NvU64 shadowFaultBufferQueuePhysAddr, 8); NvU32 shadowFaultBufferSize; + NvU32 shadowFaultBufferMetadataSize; NV_DECLARE_ALIGNED(NvU64 shadowFaultBufferPteArray[NV2080_CTRL_INTERNAL_GMMU_CLIENT_SHADOW_FAULT_BUFFER_MAX_PAGES], 8); + NvU32 shadowFaultBufferType; + NV_DECLARE_ALIGNED(NvU64 faultBufferSharedMemoryPhysAddr, 8); } NV2080_CTRL_INTERNAL_GMMU_REGISTER_CLIENT_SHADOW_FAULT_BUFFER_PARAMS; /* + * NV2080_CTRL_CMD_INTERNAL_GMMU_UNREGISTER_CLIENT_SHADOW_FAULT_BUFFER + * + * This command requests physical RM to disable the client shadow fault buffer. + * + * shadowFaultBufferType + * Replayable or non-replayable fault buffer + * + * Possible status values returned are: + * NV_OK + */ +#define NV2080_CTRL_CMD_INTERNAL_GMMU_UNREGISTER_CLIENT_SHADOW_FAULT_BUFFER (0x20800a9e) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_GMMU_UNREGISTER_CLIENT_SHADOW_FAULT_BUFFER_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_INTERNAL_GMMU_UNREGISTER_CLIENT_SHADOW_FAULT_BUFFER_PARAMS_MESSAGE_ID (0x9EU) + +typedef struct NV2080_CTRL_INTERNAL_GMMU_UNREGISTER_CLIENT_SHADOW_FAULT_BUFFER_PARAMS { + NvU32 shadowFaultBufferType; +} NV2080_CTRL_INTERNAL_GMMU_UNREGISTER_CLIENT_SHADOW_FAULT_BUFFER_PARAMS; + +/* * NV2080_CTRL_CMD_INTERNAL_GMMU_COPY_RESERVED_SPLIT_GVASPACE_PDES_TO_SERVER * * Pin PDEs for Global VA range on the server RM and then mirror the client's page @@ -1725,16 +1909,6 @@ NV_DECLARE_ALIGNED(NV90F1_CTRL_VASPACE_COPY_SERVER_RESERVED_PDES_PARAMS PdeCopyParams, 8); } NV2080_CTRL_INTERNAL_GMMU_COPY_RESERVED_SPLIT_GVASPACE_PDES_TO_SERVER_PARAMS; -/* - * NV2080_CTRL_CMD_INTERNAL_GMMU_UNREGISTER_CLIENT_SHADOW_FAULT_BUFFER - * - * This command requests physical RM to disable the client shadow fault buffer. - * - * Possible status values returned are: - * NV_OK - */ -#define NV2080_CTRL_CMD_INTERNAL_GMMU_UNREGISTER_CLIENT_SHADOW_FAULT_BUFFER (0x20800a9e) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | 0x9E" */ - /*! * NV2080_CTRL_CMD_INTERNAL_PERF_BOOST_SET_3X * @@ -1764,7 +1938,7 @@ * NV_ERR_INVALID_PARAM_STRUCT * NV_ERR_INVALID_ARGUMENT */ -#define NV2080_CTRL_CMD_INTERNAL_PERF_BOOST_SET_3X (0x20800aa0) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_PERF_BOOST_SET_PARAMS_3X_MESSAGE_ID" */ +#define NV2080_CTRL_CMD_INTERNAL_PERF_BOOST_SET_3X (0x20800aa0) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_PERF_BOOST_SET_PARAMS_3X_MESSAGE_ID" */ #define NV2080_CTRL_INTERNAL_PERF_BOOST_SET_PARAMS_3X_MESSAGE_ID (0xA0U) @@ -1850,22 +2024,38 @@ /*! * @ref NV2080_CTRL_CMD_GPU_SET_PARTITIONING_MODE */ -#define NV2080_CTRL_CMD_INTERNAL_MIGMGR_SET_PARTITIONING_MODE (0x20800aa3) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | 0xA3" */ +#define NV2080_CTRL_CMD_INTERNAL_MIGMGR_SET_PARTITIONING_MODE (0x20800aa3) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_MIGMGR_SET_PARTITIONING_MODE_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_INTERNAL_MIGMGR_SET_PARTITIONING_MODE_PARAMS_MESSAGE_ID (0xA3U) + +typedef NV2080_CTRL_GPU_SET_PARTITIONING_MODE_PARAMS NV2080_CTRL_INTERNAL_MIGMGR_SET_PARTITIONING_MODE_PARAMS; /*! * @ref NV2080_CTRL_CMD_GPU_CONFIGURE_PARTITION */ -#define NV2080_CTRL_CMD_INTERNAL_MIGMGR_CONFIGURE_GPU_INSTANCE (0x20800aa4) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | 0xA4" */ +#define NV2080_CTRL_CMD_INTERNAL_MIGMGR_CONFIGURE_GPU_INSTANCE (0x20800aa4) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_MIGMGR_CONFIGURE_GPU_INSTANCE_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_INTERNAL_MIGMGR_CONFIGURE_GPU_INSTANCE_PARAMS_MESSAGE_ID (0xA4U) + +typedef NV2080_CTRL_GPU_CONFIGURE_PARTITION_PARAMS NV2080_CTRL_INTERNAL_MIGMGR_CONFIGURE_GPU_INSTANCE_PARAMS; /*! * @ref NV2080_CTRL_CMD_GPU_SET_PARTITIONS */ -#define NV2080_CTRL_CMD_INTERNAL_MIGMGR_SET_GPU_INSTANCES (0x20800aa5) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | 0xA5" */ +#define NV2080_CTRL_CMD_INTERNAL_MIGMGR_SET_GPU_INSTANCES (0x20800aa5) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_MIGMGR_SET_GPU_INSTANCES_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_INTERNAL_MIGMGR_SET_GPU_INSTANCES_PARAMS_MESSAGE_ID (0xA5U) + +typedef NV2080_CTRL_GPU_SET_PARTITIONS_PARAMS NV2080_CTRL_INTERNAL_MIGMGR_SET_GPU_INSTANCES_PARAMS; /*! * @ref NV2080_CTRL_CMD_GPU_GET_PARTITIONS */ -#define NV2080_CTRL_CMD_INTERNAL_MIGMGR_GET_GPU_INSTANCES (0x20800aa6) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | 0xA6" */ +#define NV2080_CTRL_CMD_INTERNAL_MIGMGR_GET_GPU_INSTANCES (0x20800aa6) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_MIGMGR_GET_GPU_INSTANCES_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_INTERNAL_MIGMGR_GET_GPU_INSTANCES_PARAMS_MESSAGE_ID (0xA6U) + +typedef NV2080_CTRL_GPU_GET_PARTITIONS_PARAMS NV2080_CTRL_INTERNAL_MIGMGR_GET_GPU_INSTANCES_PARAMS; /*! * NV2080_CTRL_CMD_INTERNAL_MEMSYS_SET_ZBC_REFERENCED @@ -1877,7 +2067,7 @@ * NV_TRUE -> ZBC-kind (and no _SKIP_ZBCREFCOUNT flag) are allocated in Kernel RM * */ -#define NV2080_CTRL_CMD_INTERNAL_MEMSYS_SET_ZBC_REFERENCED (0x20800a69) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_MEMSYS_SET_ZBC_REFERENCED_PARAMS_MESSAGE_ID" */ +#define NV2080_CTRL_CMD_INTERNAL_MEMSYS_SET_ZBC_REFERENCED (0x20800a69) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_MEMSYS_SET_ZBC_REFERENCED_PARAMS_MESSAGE_ID" */ #define NV2080_CTRL_INTERNAL_MEMSYS_SET_ZBC_REFERENCED_PARAMS_MESSAGE_ID (0x69U) @@ -1896,8 +2086,9 @@ * gpu instance should behave identically with respect to fragmentation and * placement / span positioning. */ -#define NV2080_CTRL_CMD_INTERNAL_KMIGMGR_EXPORT_GPU_INSTANCE (0x20800aa7) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | 0xA7" */ -#define NV2080_CTRL_CMD_INTERNAL_MIGMGR_EXPORT_GPU_INSTANCE (0x20800aa8) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | 0xA8" */ +#define NV2080_CTRL_CMD_INTERNAL_KMIGMGR_EXPORT_GPU_INSTANCE (0x20800aa7) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_KMIGMGR_EXPORT_GPU_INSTANCE_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_CMD_INTERNAL_MIGMGR_EXPORT_GPU_INSTANCE (0x20800aa8) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_MIGMGR_EXPORT_GPU_INSTANCE_PARAMS_MESSAGE_ID" */ /*! * NV2080_CTRL_CMD_INTERNAL_KMIGMGR_IMPORT_GPU_INSTANCE @@ -1908,8 +2099,9 @@ * as the exported gpu instance, but the imported gpu instance should behave * identically with respect to fragmentation and placement / span positioning. */ -#define NV2080_CTRL_CMD_INTERNAL_KMIGMGR_IMPORT_GPU_INSTANCE (0x20800aa9) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | 0xA9" */ -#define NV2080_CTRL_CMD_INTERNAL_MIGMGR_IMPORT_GPU_INSTANCE (0x20800aaa) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | 0xAA" */ +#define NV2080_CTRL_CMD_INTERNAL_KMIGMGR_IMPORT_GPU_INSTANCE (0x20800aa9) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_KMIGMGR_IMPORT_GPU_INSTANCE_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_CMD_INTERNAL_MIGMGR_IMPORT_GPU_INSTANCE (0x20800aaa) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_MIGMGR_IMPORT_GPU_INSTANCE_PARAMS_MESSAGE_ID" */ #define NV2080_CTRL_INTERNAL_KMIGMGR_EXPORTED_GPU_INSTANCE_MAX_ENGINES_MASK_SIZE 4 typedef struct NV2080_CTRL_INTERNAL_KMIGMGR_EXPORTED_GPU_INSTANCE_INFO { @@ -1926,6 +2118,22 @@ NV_DECLARE_ALIGNED(NV2080_CTRL_INTERNAL_KMIGMGR_EXPORTED_GPU_INSTANCE_INFO info, 8); } NV2080_CTRL_INTERNAL_KMIGMGR_IMPORT_EXPORT_GPU_INSTANCE_PARAMS; +#define NV2080_CTRL_INTERNAL_KMIGMGR_EXPORT_GPU_INSTANCE_PARAMS_MESSAGE_ID (0xA7U) + +typedef NV2080_CTRL_INTERNAL_KMIGMGR_IMPORT_EXPORT_GPU_INSTANCE_PARAMS NV2080_CTRL_INTERNAL_KMIGMGR_EXPORT_GPU_INSTANCE_PARAMS; + +#define NV2080_CTRL_INTERNAL_MIGMGR_EXPORT_GPU_INSTANCE_PARAMS_MESSAGE_ID (0xA8U) + +typedef NV2080_CTRL_INTERNAL_KMIGMGR_IMPORT_EXPORT_GPU_INSTANCE_PARAMS NV2080_CTRL_INTERNAL_MIGMGR_EXPORT_GPU_INSTANCE_PARAMS; + +#define NV2080_CTRL_INTERNAL_KMIGMGR_IMPORT_GPU_INSTANCE_PARAMS_MESSAGE_ID (0xA9U) + +typedef NV2080_CTRL_INTERNAL_KMIGMGR_IMPORT_EXPORT_GPU_INSTANCE_PARAMS NV2080_CTRL_INTERNAL_KMIGMGR_IMPORT_GPU_INSTANCE_PARAMS; + +#define NV2080_CTRL_INTERNAL_MIGMGR_IMPORT_GPU_INSTANCE_PARAMS_MESSAGE_ID (0xAAU) + +typedef NV2080_CTRL_INTERNAL_KMIGMGR_IMPORT_EXPORT_GPU_INSTANCE_PARAMS NV2080_CTRL_INTERNAL_MIGMGR_IMPORT_GPU_INSTANCE_PARAMS; + /*! * NV2080_CTRL_CMD_INTERNAL_MEMSYS_L2_INVALIDATE_EVICT * @@ -2094,6 +2302,27 @@ NvU8 hshubId; } NV2080_CTRL_INTERNAL_HSHUB_NEXT_HSHUB_ID_PARAMS; +/*! + * NV2080_CTRL_CMD_INTERNAL_HSHUB_EGM_CONFIG + * + * Program HSHUB for EGM peer id. + * + * egmPeerId[IN] + * EGM peer id to program in the HSHUB registers. + * + * Possible status values returned are: + * NV_OK + */ +#define NV2080_CTRL_CMD_INTERNAL_HSHUB_EGM_CONFIG (0x20800a8d) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_HSHUB_EGM_CONFIG_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_INTERNAL_HSHUB_EGM_CONFIG_PARAMS_MESSAGE_ID (0x8dU) + +typedef struct NV2080_CTRL_INTERNAL_HSHUB_EGM_CONFIG_PARAMS { + NvU32 egmPeerId; +} NV2080_CTRL_INTERNAL_HSHUB_EGM_CONFIG_PARAMS; + + + /* * NV2080_CTRL_CMD_INTERNAL_NVLINK_ENABLE_COMPUTE_PEER_ADDR * @@ -2335,7 +2564,7 @@ * P2P Capability is disabled by a regkey. * NV0000_P2P_CAPS_STATUS_NOT_SUPPORTED * P2P Capability is not supported. - * + * * Possible status values returned are: * NV_OK * NV_ERR_INVALID_ARGUMENT @@ -2369,7 +2598,7 @@ /* * NV2080_CTRL_CMD_INTERNAL_DISPLAY_UNIX_CONSOLE * - * An internal call to invoke the sequence VGA register reads & writes to + * An internal call to invoke the sequence VGA register reads & writes to * perform save and restore of VGA * * [in] saveOrRestore @@ -2417,10 +2646,9 @@ } NV2080_CTRL_CMD_INTERNAL_DISPLAY_POST_RESTORE_PARAMS; /*! - * @ref NV2080_CTRL_CMD_INTERNAL_STATIC_KMIGMGR_GET_COMPUTE_PROFILES * @ref NV2080_CTRL_CMD_INTERNAL_STATIC_MIGMGR_GET_COMPUTE_PROFILES + * @ref NV2080_CTRL_CMD_INTERNAL_STATIC_KMIGMGR_GET_COMPUTE_PROFILES */ -#define NV2080_CTRL_CMD_INTERNAL_STATIC_KMIGMGR_GET_COMPUTE_PROFILES (0x20800aba) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | 0xba" */ /*! * NV2080_CTRL_INTERNAL_MIGMGR_COMPUTE_PROFILE @@ -2460,7 +2688,7 @@ * - Total Number of profiles filled * * profiles[OUT] - * - NV2080_CTRL_GPU_COMPUTE_PROFILE filled with valid compute instance profiles + * - NV2080_CTRL_GPU_COMPUTE_PROFILE filled with valid compute instance profiles */ #define NV2080_CTRL_INTERNAL_STATIC_MIGMGR_GET_COMPUTE_PROFILES_PARAMS_MESSAGE_ID (0xBBU) @@ -2469,6 +2697,12 @@ NV2080_CTRL_INTERNAL_MIGMGR_COMPUTE_PROFILE profiles[NV2080_CTRL_GPU_PARTITION_FLAG_COMPUTE_SIZE__SIZE]; } NV2080_CTRL_INTERNAL_STATIC_MIGMGR_GET_COMPUTE_PROFILES_PARAMS; +#define NV2080_CTRL_CMD_INTERNAL_STATIC_KMIGMGR_GET_COMPUTE_PROFILES (0x20800aba) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_STATIC_KMIGMGR_GET_COMPUTE_PROFILES_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_INTERNAL_STATIC_KMIGMGR_GET_COMPUTE_PROFILES_PARAMS_MESSAGE_ID (0xBAU) + +typedef NV2080_CTRL_INTERNAL_STATIC_MIGMGR_GET_COMPUTE_PROFILES_PARAMS NV2080_CTRL_INTERNAL_STATIC_KMIGMGR_GET_COMPUTE_PROFILES_PARAMS; + /* @@ -2637,7 +2871,7 @@ /*! * NV2080_CTRL_CMD_INTERNAL_GSYNC_SET_OR_RESTORE_RASTER_SYNC * - * Disable the raster sync gpio on the other P2060 GPU + * Disable the raster sync gpio on the other P2060 GPU * that's connected to master over Video bridge. * * [in] bEnableMaster @@ -2647,7 +2881,7 @@ * If raster sync GPIO direction is saved or not. * * [in/out] bRasterSyncGpioDirection - * During save it gets the direction. + * During save it gets the direction. * In restores it sets the direction. * * Possible status values returned are: @@ -2679,6 +2913,8 @@ * Handle to SYSMEM memlist object * [in] gspFbAllocsSysOffset * Offset in SYSMEM for GSP's FB Allocations + * [in] bEnteringGcoffState + * Value of PDB_PROP_GPU_GCOFF_STATE_ENTERING * * Possible status values returned are: * NV_OK @@ -2696,6 +2932,7 @@ NvHandle hClient; NvHandle hSysMem; NV_DECLARE_ALIGNED(NvU64 gspFbAllocsSysOffset, 8); + NvBool bEnteringGcoffState; } NV2080_CTRL_INTERNAL_FBSR_INIT_PARAMS; /*! @@ -2714,7 +2951,7 @@ * [in] sysOffset * Offset in SYSMEM region to save to/restore from * [in] size - * Size of region being saved/restored + * Size of region being saved/restored */ #define NV2080_CTRL_CMD_INTERNAL_FBSR_SEND_REGION_INFO (0x20800ac3) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_FBSR_SEND_REGION_INFO_PARAMS_MESSAGE_ID" */ @@ -2805,7 +3042,7 @@ /*! * NV2080_CTRL_CMD_INTERNAL_SMBPBI_PFM_REQ_HNDLR_CAP_UPDATE * - * Update the system control capability + * Update the system control capability * * bIsSysCtrlSupported [IN] If the system control is supported @@ -2843,7 +3080,7 @@ NvU32 sensorId; /*! - * PFM sensor limit value if required + * PFM sensor limit value if required */ NvU32 limit; } NV2080_CTRL_INTERNAL_PFM_REQ_HNDLR_STATE_SYNC_DATA_SMBPBI; @@ -2900,7 +3137,11 @@ * Sync payload data * */ -#define NV2080_CTRL_CMD_INTERNAL_PMGR_PFM_REQ_HNDLR_STATE_LOAD_SYNC (0x20800acc) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | 0xCC" */ +#define NV2080_CTRL_CMD_INTERNAL_PMGR_PFM_REQ_HNDLR_STATE_LOAD_SYNC (0x20800acc) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_PMGR_PFM_REQ_HNDLR_STATE_LOAD_SYNC_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_INTERNAL_PMGR_PFM_REQ_HNDLR_STATE_LOAD_SYNC_PARAMS_MESSAGE_ID (0xCCU) + +typedef NV2080_CTRL_INTERNAL_PFM_REQ_HNDLR_STATE_SYNC_PARAMS NV2080_CTRL_INTERNAL_PMGR_PFM_REQ_HNDLR_STATE_LOAD_SYNC_PARAMS; /*! * NV2080_CTRL_CMD_INTERNAL_THERM_PFM_REQ_HNDLR_STATE_INIT_SYNC @@ -2914,7 +3155,11 @@ * Sync payload data * */ -#define NV2080_CTRL_CMD_INTERNAL_THERM_PFM_REQ_HNDLR_STATE_INIT_SYNC (0x20800acd) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | 0xCD" */ +#define NV2080_CTRL_CMD_INTERNAL_THERM_PFM_REQ_HNDLR_STATE_INIT_SYNC (0x20800acd) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_THERM_PFM_REQ_HNDLR_STATE_INIT_SYNC_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_INTERNAL_THERM_PFM_REQ_HNDLR_STATE_INIT_SYNC_PARAMS_MESSAGE_ID (0xCDU) + +typedef NV2080_CTRL_INTERNAL_PFM_REQ_HNDLR_STATE_SYNC_PARAMS NV2080_CTRL_INTERNAL_THERM_PFM_REQ_HNDLR_STATE_INIT_SYNC_PARAMS; /*! * NV2080_CTRL_CMD_INTERNAL_GET_COHERENT_FB_APERTURE_SIZE @@ -2922,7 +3167,7 @@ * Query Coherent FB Aperture Size. * */ -#define NV2080_CTRL_CMD_INTERNAL_GET_COHERENT_FB_APERTURE_SIZE (0x20800ada) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_GET_COHERENT_FB_APERTURE_SIZE_PARAMS_MESSAGE_ID" */ +#define NV2080_CTRL_CMD_INTERNAL_GET_COHERENT_FB_APERTURE_SIZE (0x20800ada) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_GET_COHERENT_FB_APERTURE_SIZE_PARAMS_MESSAGE_ID" */ #define NV2080_CTRL_INTERNAL_GET_COHERENT_FB_APERTURE_SIZE_PARAMS_MESSAGE_ID (0xDAU) @@ -3002,6 +3247,8 @@ * * bEnable [IN] * Enable or Reset the settings + * clientLimit [IN] + * Client requested limit * * Possible status values returned are: * NV_OK @@ -3016,6 +3263,7 @@ typedef struct NV2080_CTRL_CMD_INTERNAL_PMGR_PFM_REQ_HNDLR_UPDATE_EDPP_LIMIT_PARAMS { NvBool bEnable; + NvU32 clientLimit; } NV2080_CTRL_CMD_INTERNAL_PMGR_PFM_REQ_HNDLR_UPDATE_EDPP_LIMIT_PARAMS; /*! @@ -3169,8 +3417,497 @@ } NV2080_CTRL_CMD_INTERNAL_PERF_PFM_REQ_HNDLR_SET_VPSTATE_PARAMS; /* + * NV2080_CTRL_CMD_INTERNAL_GC6_ENTRY_PREREQUISITE + * + * This command gets if GPU is in a proper state (P8 and engine idle) to be ready to enter RTD3 + * + * Possible status return values are: + * NV_OK Success + */ +#define NV2080_CTRL_CMD_INTERNAL_GC6_ENTRY_PREREQUISITE (0x2080a7d7) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_POWER_LEGACY_NON_PRIVILEGED_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_GC6_ENTRY_PREREQUISITE_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_INTERNAL_GC6_ENTRY_PREREQUISITE_PARAMS_MESSAGE_ID (0xD7U) + +typedef struct NV2080_CTRL_INTERNAL_GC6_ENTRY_PREREQUISITE_PARAMS { + NvBool bIsSatisfied; +} NV2080_CTRL_INTERNAL_GC6_ENTRY_PREREQUISITE_PARAMS; + +/* * This command unsets Dynamic Boost limit when nvidia-powerd is terminated unexpectedly. */ #define NV2080_CTRL_CMD_INTERNAL_PMGR_UNSET_DYNAMIC_BOOST_LIMIT (0x20800a7b) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | 0x7B" */ +/*! + * NV2080_CTRL_CMD_INTERNAL_FIFO_GET_NUM_SECURE_CHANNELS + * + * This command is an internal command sent from Kernel RM to Physical RM + * to get number of secure channels supported on SEC2 and CE + * + * maxSec2SecureChannels [OUT] + * maxCeSecureChannels [OUT] + */ +#define NV2080_CTRL_CMD_INTERNAL_FIFO_GET_NUM_SECURE_CHANNELS (0x20800ad8) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_FIFO_GET_NUM_SECURE_CHANNELS_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_INTERNAL_FIFO_GET_NUM_SECURE_CHANNELS_PARAMS_MESSAGE_ID (0xD8U) + +typedef struct NV2080_CTRL_INTERNAL_FIFO_GET_NUM_SECURE_CHANNELS_PARAMS { + NvU32 maxSec2SecureChannels; + NvU32 maxCeSecureChannels; +} NV2080_CTRL_INTERNAL_FIFO_GET_NUM_SECURE_CHANNELS_PARAMS; + +/* + * NV2080_CTRL_CMD_INTERNAL_BIF_DISABLE_SYSTEM_MEMORY_ACCESS + * + * This command is an internal command sent from Kernel RM to Physical RM + * to disable the GPU system memory access after quiescing the GPU or + * re-enable sysmem access. + * + * bDisable [IN] + * If NV_TRUE the GPU is quiesced and system memory access is disabled . + * If NV_FALSE the GPU system memory access is re-enabled and the GPU is resumed. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_PARAM_STRUCT + * NV_ERR_INVALID_ARGUMENT + * NV_ERR_NOT_SUPPORTED + */ +#define NV2080_CTRL_CMD_INTERNAL_BIF_DISABLE_SYSTEM_MEMORY_ACCESS (0x20800adb) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_BIF_DISABLE_SYSTEM_MEMORY_ACCESS_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_INTERNAL_BIF_DISABLE_SYSTEM_MEMORY_ACCESS_PARAMS_MESSAGE_ID (0xDBU) + +typedef struct NV2080_CTRL_INTERNAL_BIF_DISABLE_SYSTEM_MEMORY_ACCESS_PARAMS { + NvBool bDisable; +} NV2080_CTRL_INTERNAL_BIF_DISABLE_SYSTEM_MEMORY_ACCESS_PARAMS; + +#define NV2080_CTRL_CMD_INTERNAL_DISP_PINSETS_TO_LOCKPINS (0x20800adc) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_DISP_PINSETS_TO_LOCKPINS_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_INTERNAL_DISP_PINSETS_TO_LOCKPINS_PARAMS_MESSAGE_ID (0xDCU) + +typedef struct NV2080_CTRL_INTERNAL_DISP_PINSETS_TO_LOCKPINS_PARAMS { + NvU32 pinSetIn; // in + NvU32 pinSetOut; // in + NvBool bMasterScanLock; // out + NvU32 masterScanLockPin; // out + NvBool bSlaveScanLock; // out + NvU32 slaveScanLockPin; // out +} NV2080_CTRL_INTERNAL_DISP_PINSETS_TO_LOCKPINS_PARAMS; + +#define NV2080_CTRL_CMD_INTERNAL_DETECT_HS_VIDEO_BRIDGE (0x20800add) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | 0xDD" */ + +#define NV2080_CTRL_CMD_INTERNAL_DISP_SET_SLI_LINK_GPIO_SW_CONTROL (0x20800ade) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_DISP_SET_SLI_LINK_GPIO_SW_CONTROL_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_INTERNAL_DISP_SET_SLI_LINK_GPIO_SW_CONTROL_PARAMS_MESSAGE_ID (0xDEU) + +typedef struct NV2080_CTRL_INTERNAL_DISP_SET_SLI_LINK_GPIO_SW_CONTROL_PARAMS { + NvU32 pinSet; // in + NvU32 gpioFunction; // out + NvU32 gpioPin; // out + NvBool gpioDirection; // out +} NV2080_CTRL_INTERNAL_DISP_SET_SLI_LINK_GPIO_SW_CONTROL_PARAMS; + +/* NV2080_CTRL_CMD_INTERNAL_SET_STATIC_EDID_DATA + * + * This command sets up ACPI DDC Edid data. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_ARGUMENT + * NV_ERR_NOT_SUPPORTED + */ +#define NV2080_CTRL_CMD_INTERNAL_SET_STATIC_EDID_DATA (0x20800adf) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_CMD_INTERNAL_SET_STATIC_EDID_DATA_PARAMS_MESSAGE_ID" */ + +/* From ACPI6.5 spec., the max size of EDID data from SBIOS(_DDC) is 512B */ +#define MAX_EDID_SIZE_FROM_SBIOS 512U + +typedef struct NV2080_CTRL_INTERNAL_EDID_DATA { + NvU32 status; + NvU32 acpiId; + NvU32 bufferSize; + NvU8 edidBuffer[MAX_EDID_SIZE_FROM_SBIOS]; +} NV2080_CTRL_INTERNAL_EDID_DATA; + +#define NV2080_CTRL_CMD_INTERNAL_SET_STATIC_EDID_DATA_PARAMS_MESSAGE_ID (0xDFU) + +typedef struct NV2080_CTRL_CMD_INTERNAL_SET_STATIC_EDID_DATA_PARAMS { + NvU32 tableLen; + NV2080_CTRL_INTERNAL_EDID_DATA edidTable[NV0073_CTRL_SYSTEM_ACPI_ID_MAP_MAX_DISPLAYS]; +} NV2080_CTRL_CMD_INTERNAL_SET_STATIC_EDID_DATA_PARAMS; + +/*! + * NV2080_CTRL_CMD_INTERNAL_DISPLAY_ACPI_SUBSYSTEM_ACTIVATED + * + * This command intializes display ACPI child devices. + * This command accepts no parameters. + * + */ +#define NV2080_CTRL_CMD_INTERNAL_DISPLAY_ACPI_SUBSYSTEM_ACTIVATED (0x20800af0) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | 0xF0" */ + +/* NV2080_CTRL_CMD_INTERNAL_DISPLAY_PRE_MODESET */ +#define NV2080_CTRL_CMD_INTERNAL_DISPLAY_PRE_MODESET (0x20800af1) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | 0xF1" */ + +/* NV2080_CTRL_CMD_INTERNAL_DISPLAY_POST_MODESET */ +#define NV2080_CTRL_CMD_INTERNAL_DISPLAY_POST_MODESET (0x20800af2) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | 0xF2" */ + +/*! + * NV2080_CTRL_CMD_INTERNAL_GET_GPU_FABRIC_PROBE_INFO_PARAMS + * + * This structure provides the params for getting GPU Fabric Probe Internal + * Info from GSP to CPU RM + * + * numProbes[OUT] + * - Number of probe requests sent + */ +#define NV2080_CTRL_CMD_INTERNAL_GET_GPU_FABRIC_PROBE_INFO_PARAMS_MESSAGE_ID (0xF4U) + +typedef struct NV2080_CTRL_CMD_INTERNAL_GET_GPU_FABRIC_PROBE_INFO_PARAMS { + NV_DECLARE_ALIGNED(NvU64 numProbes, 8); +} NV2080_CTRL_CMD_INTERNAL_GET_GPU_FABRIC_PROBE_INFO_PARAMS; + +/*! + * NV2080_CTRL_CMD_INTERNAL_GPU_GET_FABRIC_PROBE_INFO + * + * This command is used to get NV2080_CTRL_CMD_INTERNAL_GPU_FABRIC_PROBE_INFO_PARAMS + * from GSP to CPU RM. + * This command accepts NV2080_CTRL_CMD_INTERNAL_GET_GPU_FABRIC_PROBE_INFO_PARAMS + * + */ +#define NV2080_CTRL_CMD_INTERNAL_GPU_GET_FABRIC_PROBE_INFO (0x208001f4) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_CMD_INTERNAL_GET_GPU_FABRIC_PROBE_INFO_PARAMS_MESSAGE_ID" */ + +/*! + * NV2080_CTRL_CMD_INTERNAL_START_GPU_FABRIC_PROBE_INFO_PARAMS + * + * This structure provides the params for starting GPU Fabric Probe + * + * bwMode[IN] + * - Nvlink Bandwidth mode + */ +#define NV2080_CTRL_CMD_INTERNAL_START_GPU_FABRIC_PROBE_INFO_PARAMS_MESSAGE_ID (0xF5U) + +typedef struct NV2080_CTRL_CMD_INTERNAL_START_GPU_FABRIC_PROBE_INFO_PARAMS { + NvU8 bwMode; +} NV2080_CTRL_CMD_INTERNAL_START_GPU_FABRIC_PROBE_INFO_PARAMS; + +/*! + * NV2080_CTRL_CMD_INTERNAL_GPU_START_FABRIC_PROBE + * + * This command is used to trigger start of GPU FABRIC PROBE PROCESS on GSP. + * This command accepts NV2080_CTRL_CMD_INTERNAL_START_GPU_FABRIC_PROBE_INFO_PARAMS + * + */ +#define NV2080_CTRL_CMD_INTERNAL_GPU_START_FABRIC_PROBE (0x208001f5) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_CMD_INTERNAL_START_GPU_FABRIC_PROBE_INFO_PARAMS_MESSAGE_ID" */ + +/*! + * NV2080_CTRL_CMD_INTERNAL_GPU_STOP_FABRIC_PROBE + * + * This command is used to trigger stop of GPU FABRIC PROBE PROCESS on GSP. + * This command accepts no parameters + * + */ +#define NV2080_CTRL_CMD_INTERNAL_GPU_STOP_FABRIC_PROBE (0x208001f6) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | 0xF6" */ + +/*! + * NV2080_CTRL_CMD_INTERNAL_GPU_SUSPEND_FABRIC_PROBE + * + * This command is used to trigger suspend of GPU FABRIC PROBE PROCESS on GSP. + * This command accepts no parameters + * + */ +#define NV2080_CTRL_CMD_INTERNAL_GPU_SUSPEND_FABRIC_PROBE (0x208001f7) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | 0xF7" */ + + +/*! + * NV2080_CTRL_CMD_INTERNAL_RESUME_GPU_FABRIC_PROBE_INFO_PARAMS + * + * This structure provides the params for resuming GPU Fabric Probe + * + * bwMode[IN] + * - Nvlink Bandwidth mode + */ +#define NV2080_CTRL_CMD_INTERNAL_RESUME_GPU_FABRIC_PROBE_INFO_PARAMS_MESSAGE_ID (0xF8U) + +typedef struct NV2080_CTRL_CMD_INTERNAL_RESUME_GPU_FABRIC_PROBE_INFO_PARAMS { + NvU8 bwMode; +} NV2080_CTRL_CMD_INTERNAL_RESUME_GPU_FABRIC_PROBE_INFO_PARAMS; + +/*! + * NV2080_CTRL_CMD_INTERNAL_GPU_RESUME_FABRIC_PROBE + * + * This command is used to trigger resume of GPU FABRIC PROBE PROCESS on GSP. + * This command accepts NV2080_CTRL_CMD_INTERNAL_RESUME_GPU_FABRIC_PROBE_INFO_PARAMS + * + */ +#define NV2080_CTRL_CMD_INTERNAL_GPU_RESUME_FABRIC_PROBE (0x208001f8) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_CMD_INTERNAL_RESUME_GPU_FABRIC_PROBE_INFO_PARAMS_MESSAGE_ID" */ + +/*! + * NV2080_CTRL_CMD_INTERNAL_GPU_INVALIDATE_FABRIC_PROBE + * + * This command is used to invalidate/reset GPU_FABRIC_PROBE_INFO on GSP. + * This command accepts no parameters + * + */ +#define NV2080_CTRL_CMD_INTERNAL_GPU_INVALIDATE_FABRIC_PROBE (0x208001f9) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | 0xF9" */ + +/*! + * NV2080_CTRL_CMD_INTERNAL_CONF_COMPUTE_GET_STATIC_INFO + * + * This command is an internal command sent from Kernel RM to Physical RM + * to get static conf compute info + * + * bIsBar1Trusted: [OUT] + * Is BAR1 trusted to access CPR + * bIsPcieTrusted: [OUT] + * Is PCIE trusted to access CPR + */ +#define NV2080_CTRL_CMD_INTERNAL_CONF_COMPUTE_GET_STATIC_INFO (0x20800af3) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_CONF_COMPUTE_GET_STATIC_INFO_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_INTERNAL_CONF_COMPUTE_GET_STATIC_INFO_PARAMS_MESSAGE_ID (0xF3U) + +typedef struct NV2080_CTRL_INTERNAL_CONF_COMPUTE_GET_STATIC_INFO_PARAMS { + NvBool bIsBar1Trusted; + NvBool bIsPcieTrusted; +} NV2080_CTRL_INTERNAL_CONF_COMPUTE_GET_STATIC_INFO_PARAMS; + +/*! + * NV2080_CTRL_CMD_INTERNAL_CONF_COMPUTE_ENCRYPTION_CONTROL + * + * This command is used to trigger the initialization / suspension of encrypted RPCs for Confidential Compute. + * bEncryptionControl : [IN] + * NV_TRUE indicates initialization. + * NV_FALSE indicates suspension. + */ +#define NV2080_CTRL_CMD_INTERNAL_CONF_COMPUTE_ENCRYPTION_CONTROL (0x208001b2) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_CMD_INTERNAL_CONF_COMPUTE_ENCRYPTION_CONTROL_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_CMD_INTERNAL_CONF_COMPUTE_ENCRYPTION_CONTROL_PARAMS_MESSAGE_ID (0xB2U) + +typedef struct NV2080_CTRL_CMD_INTERNAL_CONF_COMPUTE_ENCRYPTION_CONTROL_PARAMS { + NvBool bEncryptionControl; +} NV2080_CTRL_CMD_INTERNAL_CONF_COMPUTE_ENCRYPTION_CONTROL_PARAMS; + +/*! + * NV2080_CTRL_CMD_INTERNAL_CONF_COMPUTE_DERIVE_SWL_KEYS + * + * This command is an internal command sent from Kernel RM to Physical RM + * to derive SWL keys and IV masks for a given engine + * + * engineId: [IN] + * NV2080_ENGINE_TYPE_* for engine for which keys and IV mask should be derived + * ivMaskSet: [OUT] + * Set of IV masks for given engine + */ +#define NV2080_CTRL_CMD_INTERNAL_CONF_COMPUTE_DERIVE_SWL_KEYS (0x20800ae1) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_CONF_COMPUTE_DERIVE_SWL_KEYS_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_INTERNAL_CONF_COMPUTE_IVMASK_SIZE 3U +#define NV2080_CTRL_INTERNAL_CONF_COMPUTE_IVMASK_SWL_KERNEL 0U +#define NV2080_CTRL_INTERNAL_CONF_COMPUTE_IVMASK_SWL_USER 1U +#define NV2080_CTRL_INTERNAL_CONF_COMPUTE_IVMASK_SWL_COUNT 2U +#define NV2080_CTRL_INTERNAL_CONF_COMPUTE_IVMASK_LCE_COUNT 6U + +typedef struct NV2080_CTRL_INTERNAL_CONF_COMPUTE_IVMASK { + NvU32 ivMask[NV2080_CTRL_INTERNAL_CONF_COMPUTE_IVMASK_SIZE]; +} NV2080_CTRL_INTERNAL_CONF_COMPUTE_IVMASK; + +#define NV2080_CTRL_INTERNAL_CONF_COMPUTE_DERIVE_SWL_KEYS_PARAMS_MESSAGE_ID (0xE1U) + +typedef struct NV2080_CTRL_INTERNAL_CONF_COMPUTE_DERIVE_SWL_KEYS_PARAMS { + NvU32 engineId; + NV2080_CTRL_INTERNAL_CONF_COMPUTE_IVMASK ivMaskSet[NV2080_CTRL_INTERNAL_CONF_COMPUTE_IVMASK_SWL_COUNT]; +} NV2080_CTRL_INTERNAL_CONF_COMPUTE_DERIVE_SWL_KEYS_PARAMS; + +/*! + * NV2080_CTRL_CMD_INTERNAL_CONF_COMPUTE_DERIVE_LCE_KEYS + * + * This command is an internal command sent from Kernel RM to Physical RM + * to derive LCE keys and IV masks for a given engine + * + * engineId: [IN] + * NV2080_ENGINE_TYPE_* for engine for which keys and IV mask should be derived + * ivMaskSet: [OUT] + * Set of IV masks for given engine + */ +#define NV2080_CTRL_CMD_INTERNAL_CONF_COMPUTE_DERIVE_LCE_KEYS (0x20800ae2) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_CONF_COMPUTE_DERIVE_LCE_KEYS_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_INTERNAL_CONF_COMPUTE_DERIVE_LCE_KEYS_PARAMS_MESSAGE_ID (0xE2U) + +typedef struct NV2080_CTRL_INTERNAL_CONF_COMPUTE_DERIVE_LCE_KEYS_PARAMS { + NvU32 engineId; + NV2080_CTRL_INTERNAL_CONF_COMPUTE_IVMASK ivMaskSet[NV2080_CTRL_INTERNAL_CONF_COMPUTE_IVMASK_LCE_COUNT]; +} NV2080_CTRL_INTERNAL_CONF_COMPUTE_DERIVE_LCE_KEYS_PARAMS; + + + +/* + * NV2080_CTRL_CMD_INTERNAL_MEMMGR_MEMORY_TRANSFER_WITH_GSP + * + * This command is used by CPU-RM to perform memory operations using GSP + * + * + * Possible status values returned are: + * NV_OK + * NVOS_STATUS_TIMEOUT_RETRY + * NV_ERR_NOT_SUPPORTED + */ + +#define NV2080_CTRL_CMD_INTERNAL_MEMMGR_MEMORY_TRANSFER_WITH_GSP (0x20800afa) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_MEMMGR_MEMORY_TRANSFER_WITH_GSP_PARAMS_MESSAGE_ID" */ + +typedef enum NV2080_CTRL_MEMMGR_MEMORY_OP { + NV2080_CTRL_MEMMGR_MEMORY_OP_MEMCPY = 0, + NV2080_CTRL_MEMMGR_MEMORY_OP_MEMSET = 1, +} NV2080_CTRL_MEMMGR_MEMORY_OP; + +typedef struct NV2080_CTRL_INTERNAL_TRANSFER_SURFACE_INFO { + /*! + * Base physical address of the surface + */ + NV_DECLARE_ALIGNED(NvU64 baseAddr, 8); + + /*! + * Size of the surface in bytes + */ + NV_DECLARE_ALIGNED(NvU64 size, 8); + + /*! + * Offset in bytes into the surface where read/write must happen + */ + NV_DECLARE_ALIGNED(NvU64 offset, 8); + + /*! + * Aperture where the surface is allocated + */ + NvU32 aperture; + + /*! + * CPU caching attribute of the surface + */ + NvU32 cpuCacheAttrib; +} NV2080_CTRL_INTERNAL_TRANSFER_SURFACE_INFO; + +#define CC_AES_256_GCM_AUTH_TAG_SIZE_BYTES (0x10U) /* finn: Evaluated from "(128 / 8)" */ + +#define NV2080_CTRL_INTERNAL_MEMMGR_MEMORY_TRANSFER_WITH_GSP_PARAMS_MESSAGE_ID (0xFAU) + +typedef struct NV2080_CTRL_INTERNAL_MEMMGR_MEMORY_TRANSFER_WITH_GSP_PARAMS { + + /*! + * Source surface info + */ + NV_DECLARE_ALIGNED(NV2080_CTRL_INTERNAL_TRANSFER_SURFACE_INFO src, 8); + + /*! + * Authentication tag if data is encrypted + */ + NvU8 authTag[CC_AES_256_GCM_AUTH_TAG_SIZE_BYTES]; + + /*! + * Destination surface info + */ + NV_DECLARE_ALIGNED(NV2080_CTRL_INTERNAL_TRANSFER_SURFACE_INFO dst, 8); + + /*! + * Size of the data to be transferred + */ + NV_DECLARE_ALIGNED(NvU64 transferSize, 8); + + /*! + * To be set in case of memset + */ + NvU32 value; + + /*! + * Memory op to be performed + */ + NV2080_CTRL_MEMMGR_MEMORY_OP memop; +} NV2080_CTRL_INTERNAL_MEMMGR_MEMORY_TRANSFER_WITH_GSP_PARAMS; + +/*! + * NV2080_CTRL_CMD_INTERNAL_MEMSYS_GET_LOCAL_ATS_CONFIG + * + * This command is an internal command sent from Kernel RM to Physical RM + * to get local GPU's ATS config + * + * addrSysPhys : [OUT] + * System Physical Address + * addrWidth : [OUT] + * Address width value + * mask : [OUT] + * Mask value + * maskWidth : [OUT] + * Mask width value + */ +#define NV2080_CTRL_CMD_INTERNAL_MEMSYS_GET_LOCAL_ATS_CONFIG (0x20800afb) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_MEMSYS_GET_LOCAL_ATS_CONFIG_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_INTERNAL_MEMSYS_GET_LOCAL_ATS_CONFIG_PARAMS_MESSAGE_ID (0xFBU) + +typedef struct NV2080_CTRL_INTERNAL_MEMSYS_GET_LOCAL_ATS_CONFIG_PARAMS { + NV_DECLARE_ALIGNED(NvU64 addrSysPhys, 8); + NvU32 addrWidth; + NvU32 mask; + NvU32 maskWidth; +} NV2080_CTRL_INTERNAL_MEMSYS_GET_LOCAL_ATS_CONFIG_PARAMS; + +/*! + * NV2080_CTRL_CMD_INTERNAL_MEMSYS_SET_PEER_ATS_CONFIG + * + * This command is an internal command sent from Kernel RM to Physical RM + * to set peer ATS config using the parameters passed in. + * + * peerId : [IN] + * Peer Id of the peer for which ATS config is to be programmed + * addrSysPhys : [IN] + * System Physical Address + * addrWidth : [IN] + * Address width value + * mask : [IN] + * Mask value + * maskWidth : [IN] + * Mask width value + */ +#define NV2080_CTRL_CMD_INTERNAL_MEMSYS_SET_PEER_ATS_CONFIG (0x20800afc) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_MEMSYS_SET_PEER_ATS_CONFIG_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_INTERNAL_MEMSYS_SET_PEER_ATS_CONFIG_PARAMS_MESSAGE_ID (0xFCU) + +typedef struct NV2080_CTRL_INTERNAL_MEMSYS_SET_PEER_ATS_CONFIG_PARAMS { + NvU32 peerId; + NV_DECLARE_ALIGNED(NvU64 addrSysPhys, 8); + NvU32 addrWidth; + NvU32 mask; + NvU32 maskWidth; +} NV2080_CTRL_INTERNAL_MEMSYS_SET_PEER_ATS_CONFIG_PARAMS; + +/*! + * NV2080_CTRL_CMD_INTERNAL_PMGR_PFM_REQ_HNDLR_GET_EDPP_LIMIT_INFO + * + * Get GPU EDPpeak Limit information + * + * limitMin [OUT] + * Minimum allowed limit value on EDPp policy on both AC and DC + * limitRated [OUT] + * Rated/default allowed limit value on EDPp policy on AC + * limitMax [OUT] + * Maximum allowed limit value on EDPp policy on AC + * limitCurr [OUT] + * Current resultant limit effective on EDPp policy on AC and DC + * limitBattRated [OUT] + * Default/rated allowed limit on EDPp policy on DC + * limitBattMax [OUT] + * Maximum allowed limit on EDPp policy on DC + * + * Possible status values returned are: + * NV_OK + * NV_ERR_GENERIC + */ + +#define NV2080_CTRL_CMD_INTERNAL_PMGR_PFM_REQ_HNDLR_GET_EDPP_LIMIT_INFO (0x20800afd) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_CMD_INTERNAL_PMGR_PFM_REQ_HNDLR_GET_EDPP_LIMIT_INFO_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_CMD_INTERNAL_PMGR_PFM_REQ_HNDLR_GET_EDPP_LIMIT_INFO_PARAMS_MESSAGE_ID (0xFDU) + +typedef struct NV2080_CTRL_CMD_INTERNAL_PMGR_PFM_REQ_HNDLR_GET_EDPP_LIMIT_INFO_PARAMS { + NvU32 limitMin; + NvU32 limitRated; + NvU32 limitMax; + NvU32 limitCurr; + NvU32 limitBattRated; + NvU32 limitBattMax; +} NV2080_CTRL_CMD_INTERNAL_PMGR_PFM_REQ_HNDLR_GET_EDPP_LIMIT_INFO_PARAMS; + /* ctrl2080internal_h */ diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080lpwr.h nvidia-open-gpu-kernel-modules-535.161.08/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080lpwr.h --- nvidia-open-gpu-kernel-modules-525.147.05/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080lpwr.h 2023-10-25 20:22:14.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080lpwr.h 2024-03-05 22:15:07.000000000 +0000 @@ -27,7 +27,7 @@ // // This file was generated with FINN, an NVIDIA coding tool. -// Source file: ctrl/ctrl2080/ctrl2080lpwr.finn +// Source file: ctrl/ctrl2080/ctrl2080lpwr.finn // diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080mc.h nvidia-open-gpu-kernel-modules-535.161.08/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080mc.h --- nvidia-open-gpu-kernel-modules-525.147.05/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080mc.h 2023-10-25 20:22:14.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080mc.h 2024-03-05 22:15:07.000000000 +0000 @@ -27,7 +27,7 @@ // // This file was generated with FINN, an NVIDIA coding tool. -// Source file: ctrl/ctrl2080/ctrl2080mc.finn +// Source file: ctrl/ctrl2080/ctrl2080mc.finn // #include "ctrl/ctrl2080/ctrl2080base.h" @@ -79,7 +79,6 @@ #define NV2080_CTRL_MC_ARCH_INFO_ARCHITECTURE_GA100 (0x00000170) - /* valid ARCHITECTURE_T23X implementation values */ diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080nvd.h nvidia-open-gpu-kernel-modules-535.161.08/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080nvd.h --- nvidia-open-gpu-kernel-modules-525.147.05/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080nvd.h 2023-10-25 20:22:14.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080nvd.h 2024-03-05 22:15:07.000000000 +0000 @@ -27,7 +27,7 @@ // // This file was generated with FINN, an NVIDIA coding tool. -// Source file: ctrl/ctrl2080/ctrl2080nvd.finn +// Source file: ctrl/ctrl2080/ctrl2080nvd.finn // #include "ctrl/ctrl2080/ctrl2080base.h" diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080nvlink.h nvidia-open-gpu-kernel-modules-535.161.08/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080nvlink.h --- nvidia-open-gpu-kernel-modules-525.147.05/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080nvlink.h 2023-10-25 20:22:15.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080nvlink.h 2024-03-05 22:15:07.000000000 +0000 @@ -27,7 +27,7 @@ // // This file was generated with FINN, an NVIDIA coding tool. -// Source file: ctrl/ctrl2080/ctrl2080nvlink.finn +// Source file: ctrl/ctrl2080/ctrl2080nvlink.finn // #include "ctrl/ctrl2080/ctrl2080base.h" @@ -2098,6 +2098,7 @@ typedef struct NV2080_CTRL_NVLINK_PRE_SETUP_NVLINK_PEER_PARAMS { NvU32 peerId; NvU32 peerLinkMask; + NvBool bEgmPeer; NvBool bNvswitchConn; } NV2080_CTRL_NVLINK_PRE_SETUP_NVLINK_PEER_PARAMS; #define NV2080_CTRL_CMD_NVLINK_PRE_SETUP_NVLINK_PEER (0x2080301dU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_NVLINK_INTERFACE_ID << 8) | NV2080_CTRL_NVLINK_PRE_SETUP_NVLINK_PEER_PARAMS_MESSAGE_ID" */ diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080perf.h nvidia-open-gpu-kernel-modules-535.161.08/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080perf.h --- nvidia-open-gpu-kernel-modules-525.147.05/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080perf.h 2023-10-25 20:22:15.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080perf.h 2024-03-05 22:15:07.000000000 +0000 @@ -27,7 +27,7 @@ // // This file was generated with FINN, an NVIDIA coding tool. -// Source file: ctrl/ctrl2080/ctrl2080perf.finn +// Source file: ctrl/ctrl2080/ctrl2080perf.finn // #include "nvfixedtypes.h" @@ -347,7 +347,26 @@ * NV_OK * NV_ERR_NOT_SUPPORTED */ -#define NV2080_CTRL_CMD_PERF_RATED_TDP_GET_CONTROL (0x2080206e) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_PERF_INTERFACE_ID << 8) | 0x6E" */ +#define NV2080_CTRL_CMD_PERF_RATED_TDP_GET_CONTROL (0x2080206e) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_PERF_INTERFACE_ID << 8) | NV2080_CTRL_PERF_RATED_TDP_GET_CONTROL_PARAMS_MESSAGE_ID" */ + +/*! + * Structure containing the requested action for a RATED_TDP client (@ref + * NV2080_CTRL_PERF_RATED_TDP_CLIENT). + */ +typedef struct NV2080_CTRL_PERF_RATED_TDP_CONTROL_PARAMS { + /*! + * [in] - Specified client for request. + */ + NV2080_CTRL_PERF_RATED_TDP_CLIENT client; + /*! + * [in/out] - Client's requested action. + */ + NV2080_CTRL_PERF_RATED_TDP_ACTION input; +} NV2080_CTRL_PERF_RATED_TDP_CONTROL_PARAMS; + +#define NV2080_CTRL_PERF_RATED_TDP_GET_CONTROL_PARAMS_MESSAGE_ID (0x6EU) + +typedef NV2080_CTRL_PERF_RATED_TDP_CONTROL_PARAMS NV2080_CTRL_PERF_RATED_TDP_GET_CONTROL_PARAMS; /*! * NV2080_CTRL_CMD_PERF_RATED_TDP_SET_CONTROL @@ -363,22 +382,11 @@ * NV_OK * NV_ERR_NOT_SUPPORTED */ -#define NV2080_CTRL_CMD_PERF_RATED_TDP_SET_CONTROL (0x2080206f) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_PERF_INTERFACE_ID << 8) | 0x6F" */ +#define NV2080_CTRL_CMD_PERF_RATED_TDP_SET_CONTROL (0x2080206f) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_PERF_INTERFACE_ID << 8) | NV2080_CTRL_PERF_RATED_TDP_SET_CONTROL_PARAMS_MESSAGE_ID" */ -/*! - * Structure containing the requested action for a RATED_TDP client (@ref - * NV2080_CTRL_PERF_RATED_TDP_CLIENT). - */ -typedef struct NV2080_CTRL_PERF_RATED_TDP_CONTROL_PARAMS { - /*! - * [in] - Specified client for request. - */ - NV2080_CTRL_PERF_RATED_TDP_CLIENT client; - /*! - * [in/out] - Client's requested action. - */ - NV2080_CTRL_PERF_RATED_TDP_ACTION input; -} NV2080_CTRL_PERF_RATED_TDP_CONTROL_PARAMS; +#define NV2080_CTRL_PERF_RATED_TDP_SET_CONTROL_PARAMS_MESSAGE_ID (0x6FU) + +typedef NV2080_CTRL_PERF_RATED_TDP_CONTROL_PARAMS NV2080_CTRL_PERF_RATED_TDP_SET_CONTROL_PARAMS; /*! * This struct represents the GPU monitoring perfmon sample for an engine. @@ -452,7 +460,7 @@ #define NV2080_CTRL_PERF_GPUMON_SAMPLE_COUNT_PERFMON_UTIL 72 #define NV2080_CTRL_PERF_GPUMON_PERFMON_UTIL_BUFFER_SIZE \ - NV_SIZEOF32(NV2080_CTRL_PERF_GPUMON_PERFMON_UTIL_SAMPLE) * \ + sizeof(NV2080_CTRL_PERF_GPUMON_PERFMON_UTIL_SAMPLE) * \ NV2080_CTRL_PERF_GPUMON_SAMPLE_COUNT_PERFMON_UTIL /*! diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080perf_cf.h nvidia-open-gpu-kernel-modules-535.161.08/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080perf_cf.h --- nvidia-open-gpu-kernel-modules-525.147.05/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080perf_cf.h 2023-10-25 20:22:15.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080perf_cf.h 2024-03-05 22:15:07.000000000 +0000 @@ -25,7 +25,7 @@ // // This file was generated with FINN, an NVIDIA coding tool. -// Source file: ctrl/ctrl2080/ctrl2080perf_cf.finn +// Source file: ctrl/ctrl2080/ctrl2080perf_cf.finn // diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080perf_cf_pwr_model.h nvidia-open-gpu-kernel-modules-535.161.08/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080perf_cf_pwr_model.h --- nvidia-open-gpu-kernel-modules-525.147.05/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080perf_cf_pwr_model.h 2023-10-25 20:22:15.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080perf_cf_pwr_model.h 2024-03-05 22:15:07.000000000 +0000 @@ -25,7 +25,7 @@ // // This file was generated with FINN, an NVIDIA coding tool. -// Source file: ctrl/ctrl2080/ctrl2080perf_cf_pwr_model.finn +// Source file: ctrl/ctrl2080/ctrl2080perf_cf_pwr_model.finn // diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080pmgr.h nvidia-open-gpu-kernel-modules-535.161.08/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080pmgr.h --- nvidia-open-gpu-kernel-modules-525.147.05/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080pmgr.h 2023-10-25 20:22:15.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080pmgr.h 2024-03-05 22:15:08.000000000 +0000 @@ -27,7 +27,7 @@ // // This file was generated with FINN, an NVIDIA coding tool. -// Source file: ctrl/ctrl2080/ctrl2080pmgr.finn +// Source file: ctrl/ctrl2080/ctrl2080pmgr.finn // diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080pmu.h nvidia-open-gpu-kernel-modules-535.161.08/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080pmu.h --- nvidia-open-gpu-kernel-modules-525.147.05/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080pmu.h 1970-01-01 00:00:00.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080pmu.h 2024-03-05 22:15:08.000000000 +0000 @@ -0,0 +1,41 @@ + +/* + * SPDX-FileCopyrightText: Copyright (c) 2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#pragma once + +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: ctrl/ctrl2080/ctrl2080pmu.finn +// + + + +#include "nvtypes.h" + +/*! + * @file + * + * @brief Enumeration of all PMU RMCTRL identifiers. + */ + diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080pmumon.h nvidia-open-gpu-kernel-modules-535.161.08/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080pmumon.h --- nvidia-open-gpu-kernel-modules-525.147.05/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080pmumon.h 2023-10-25 20:22:15.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080pmumon.h 2024-03-05 22:15:08.000000000 +0000 @@ -27,7 +27,7 @@ // // This file was generated with FINN, an NVIDIA coding tool. -// Source file: ctrl/ctrl2080/ctrl2080pmumon.finn +// Source file: ctrl/ctrl2080/ctrl2080pmumon.finn // diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080power.h nvidia-open-gpu-kernel-modules-535.161.08/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080power.h --- nvidia-open-gpu-kernel-modules-525.147.05/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080power.h 2023-10-25 20:22:15.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080power.h 2024-03-05 22:15:08.000000000 +0000 @@ -27,6 +27,97 @@ // // This file was generated with FINN, an NVIDIA coding tool. -// Source file: ctrl/ctrl2080/ctrl2080power.finn +// Source file: ctrl/ctrl2080/ctrl2080power.finn // +#include "ctrl/ctrl2080/ctrl2080base.h" + + + +/*! + * @brief GC6 flavor ids + */ +typedef enum NV2080_CTRL_GC6_FLAVOR_ID { + NV2080_CTRL_GC6_FLAVOR_ID_MSHYBRID = 0, + NV2080_CTRL_GC6_FLAVOR_ID_OPTIMUS = 1, + + + NV2080_CTRL_GC6_FLAVOR_ID_MAX = 4, +} NV2080_CTRL_GC6_FLAVOR_ID; + +/* + * NV2080_CTRL_CMD_GC6_ENTRY + * + * This command executes the steps of GC6 entry sequence + * + * Possible status return values are: + * NV_OK + * NV_ERR_NOT_SUPPORTED (non-fatal) + * NV_ERR_INVALID_STATE (non-fatal) + * NV_ERR_INVALID_ARGUMENT (non-fatal) + * NV_ERR_NOT_READY (non-fatal) + * NV_ERR_TIMEOUT + * NV_ERR_GENERIC + */ +#define NV2080_CTRL_CMD_GC6_ENTRY (0x2080270d) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_POWER_INTERFACE_ID << 8) | NV2080_CTRL_GC6_ENTRY_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_GC6_ENTRY_PARAMS_MESSAGE_ID (0xDU) + +typedef struct NV2080_CTRL_GC6_ENTRY_PARAMS { + NV2080_CTRL_GC6_FLAVOR_ID flavorId; + NvU32 stepMask; + struct { + + + NvBool bIsRTD3Transition; + NvBool bIsRTD3CoreRailPowerCut; + + + NvBool bSkipPstateSanity; + } params; +} NV2080_CTRL_GC6_ENTRY_PARAMS; + +/* + * NV2080_CTRL_CMD_GC6_EXIT + * + * This command executes the steps of GC6 exit sequence + * + * Possible status return values are: + * NV_OK + * NV_ERR_GENERIC + */ +#define NV2080_CTRL_CMD_GC6_EXIT (0x2080270e) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_POWER_INTERFACE_ID << 8) | NV2080_CTRL_GC6_EXIT_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_GC6_EXIT_PARAMS_MESSAGE_ID (0xEU) + +typedef struct NV2080_CTRL_GC6_EXIT_PARAMS { + NV2080_CTRL_GC6_FLAVOR_ID flavorId; + struct { + NvBool bIsGpuSelfWake; + NvBool bIsRTD3Transition; + + + NvBool bIsRTD3HotTransition; //output + } params; +} NV2080_CTRL_GC6_EXIT_PARAMS; + +/*! + * @brief GC6 step ids + */ +typedef enum NV2080_CTRL_GC6_STEP_ID { + NV2080_CTRL_GC6_STEP_ID_SR_ENTRY = 0, + NV2080_CTRL_GC6_STEP_ID_GPU_OFF = 1, + NV2080_CTRL_GC6_STEP_ID_MAX = 2, +} NV2080_CTRL_GC6_STEP_ID; + +typedef struct NV2080_CTRL_GC6_FLAVOR_INFO { + NV2080_CTRL_GC6_FLAVOR_ID flavorId; + NvU32 stepMask; +} NV2080_CTRL_GC6_FLAVOR_INFO; + + + +/* _ctrl2080power_h_ */ + + + diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080rc.h nvidia-open-gpu-kernel-modules-535.161.08/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080rc.h --- nvidia-open-gpu-kernel-modules-525.147.05/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080rc.h 2023-10-25 20:22:15.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080rc.h 2024-03-05 22:15:08.000000000 +0000 @@ -27,7 +27,7 @@ // // This file was generated with FINN, an NVIDIA coding tool. -// Source file: ctrl/ctrl2080/ctrl2080rc.finn +// Source file: ctrl/ctrl2080/ctrl2080rc.finn // #include "ctrl/ctrl2080/ctrl2080base.h" @@ -252,9 +252,17 @@ NvU32 rcEnable; } NV2080_CTRL_CMD_RC_RECOVERY_PARAMS; -#define NV2080_CTRL_CMD_SET_RC_RECOVERY (0x2080220d) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_RC_INTERFACE_ID << 8) | 0xD" */ +#define NV2080_CTRL_CMD_SET_RC_RECOVERY (0x2080220d) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_RC_INTERFACE_ID << 8) | NV2080_CTRL_SET_RC_RECOVERY_PARAMS_MESSAGE_ID" */ -#define NV2080_CTRL_CMD_GET_RC_RECOVERY (0x2080220e) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_RC_INTERFACE_ID << 8) | 0xE" */ +#define NV2080_CTRL_SET_RC_RECOVERY_PARAMS_MESSAGE_ID (0xDU) + +typedef NV2080_CTRL_CMD_RC_RECOVERY_PARAMS NV2080_CTRL_SET_RC_RECOVERY_PARAMS; + +#define NV2080_CTRL_CMD_GET_RC_RECOVERY (0x2080220e) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_RC_INTERFACE_ID << 8) | NV2080_CTRL_GET_RC_RECOVERY_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_GET_RC_RECOVERY_PARAMS_MESSAGE_ID (0xEU) + +typedef NV2080_CTRL_CMD_RC_RECOVERY_PARAMS NV2080_CTRL_GET_RC_RECOVERY_PARAMS; /* valid values for rcEnable */ #define NV2080_CTRL_CMD_RC_RECOVERY_DISABLED (0x00000000) @@ -353,9 +361,17 @@ NvU32 rcBreak; } NV2080_CTRL_CMD_RC_INFO_PARAMS; -#define NV2080_CTRL_CMD_SET_RC_INFO (0x20802211) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_RC_INTERFACE_ID << 8) | 0x11" */ +#define NV2080_CTRL_CMD_SET_RC_INFO (0x20802211) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_RC_INTERFACE_ID << 8) | NV2080_CTRL_SET_RC_INFO_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_SET_RC_INFO_PARAMS_MESSAGE_ID (0x11U) + +typedef NV2080_CTRL_CMD_RC_INFO_PARAMS NV2080_CTRL_SET_RC_INFO_PARAMS; + +#define NV2080_CTRL_CMD_GET_RC_INFO (0x20802212) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_RC_INTERFACE_ID << 8) | NV2080_CTRL_GET_RC_INFO_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_GET_RC_INFO_PARAMS_MESSAGE_ID (0x12U) -#define NV2080_CTRL_CMD_GET_RC_INFO (0x20802212) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_RC_INTERFACE_ID << 8) | 0x12" */ +typedef NV2080_CTRL_CMD_RC_INFO_PARAMS NV2080_CTRL_GET_RC_INFO_PARAMS; /* valid rcMode values */ #define NV2080_CTRL_CMD_RC_INFO_MODE_DISABLE (0x00000000) diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080spdm.h nvidia-open-gpu-kernel-modules-535.161.08/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080spdm.h --- nvidia-open-gpu-kernel-modules-525.147.05/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080spdm.h 1970-01-01 00:00:00.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080spdm.h 2024-03-05 22:15:08.000000000 +0000 @@ -0,0 +1,245 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2022-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#pragma once + +#include + +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: ctrl/ctrl2080/ctrl2080spdm.finn +// + + + +/*************************** SPDM COMMANDS ************************************/ + +/*! + * @brief SPDM Command Types + * + */ +#define RM_GSP_SPDM_CMD_ID_CC_INIT (0x1) +#define RM_GSP_SPDM_CMD_ID_CC_DEINIT (0x2) +#define RM_GSP_SPDM_CMD_ID_CC_CTRL (0x3) +#define RM_GSP_SPDM_CMD_ID_CC_INIT_RM_DATA (0x4) + + +#define RM_GSP_SPDM_CMD_ID_INVALID_COMMAND (0xFF) + + + +#define RSVD7_SIZE 16 + +#define RSVD8_SIZE 2 + +/*! + * Guest RM must send RM_GSP_SPDM_CMD_ID_CC_INIT to GSP-RM before SPDM session start + */ +typedef struct RM_GSP_SPDM_CC_INIT_CTX { + NvU32 guestId; // To indicate CC guest Id, VM0, VM1 ... etc + + + NvU64_ALIGN32 dmaAddr; // The address RM allocate in SYS memory or FB memory. +} RM_GSP_SPDM_CC_INIT_CTX; +typedef struct RM_GSP_SPDM_CC_INIT_CTX *PRM_GSP_SPDM_CC_INIT_CTX; + +/*! + * Guest RM provides INIT context + */ +typedef struct RM_GSP_SPDM_CMD_CC_INIT { + // Command must be first as this struct is the part of union + NvU8 cmdType; + + RM_GSP_SPDM_CC_INIT_CTX ccInitCtx; +} RM_GSP_SPDM_CMD_CC_INIT; +typedef struct RM_GSP_SPDM_CMD_CC_INIT *PRM_GSP_SPDM_CMD_CC_INIT; + +#define DEINIT_FLAGS_FORCE_CLEAR (0x1) + +/*! + * Guest RM must send RM_GSP_SPDM_CMD_ID_CC_DEINIT to GSP-RM to end a session + */ +typedef struct RM_GSP_SPDM_CC_DEINIT_CTX { + NvU32 guestId; // To indicate CC guest Id, VM0, VM1 ... etc + + NvU32 endpointId; // To indicate SPDM endpoint Id + + NvU32 flags; +} RM_GSP_SPDM_CC_DEINIT_CTX; +typedef struct RM_GSP_SPDM_CC_DEINIT_CTX *PRM_GSP_SPDM_CC_DEINIT_CTX; + +/*! + * Guest RM provides INIT context + */ +typedef struct RM_GSP_SPDM_CMD_CC_DEINIT { + // Command must be first as this struct is the part of union + NvU8 cmdType; + + RM_GSP_SPDM_CC_DEINIT_CTX ccDeinitCtx; +} RM_GSP_SPDM_CMD_CC_DEINIT; +typedef struct RM_GSP_SPDM_CMD_CC_DEINIT *PRM_GSP_SPDM_CMD_CC_DEINIT; + +/*! + * RM provides SPDM message request context, include header + corresponding payload + */ + +typedef struct RM_GSP_SPDM_CC_CTRL_CTX { + + NvU32 version; + + NvU32 guestId; // To indicate CC client Id, VM0, VM1 ... etc + + NvU32 endpointId; // To indicate SPDM endpoint Id + +} RM_GSP_SPDM_CC_CTRL_CTX; +typedef struct RM_GSP_SPDM_CC_CTRL_CTX *PRM_GSP_SPDM_CC_CTRL_CTX; + +/*! + * RM provides the SPDM request info to GSP + */ +typedef struct RM_GSP_SPDM_CMD_CC_CTRL { + // Command must be first as this struct is the part of union + NvU8 cmdType; + + RM_GSP_SPDM_CC_CTRL_CTX ccCtrlCtx; +} RM_GSP_SPDM_CMD_CC_CTRL; +typedef struct RM_GSP_SPDM_CMD_CC_CTRL *PRM_GSP_SPDM_CMD_CC_CTRL; + +typedef struct RM_GSP_SPDM_CMD_CC_INIT_RM_DATA { + // Command must be first as this struct is the part of union + NvU8 cmdType; + + NvU32 rsvd0[2]; + + NvU32 rsvd1; + + char rsvd2[4]; + + char rsvd3[2]; + + char rsvd4[5]; + + char rsvd5[5]; + + char rsvd6[2]; + + char rsvd7[RSVD7_SIZE]; + + NvU32 rsvd8[RSVD8_SIZE]; +} RM_GSP_SPDM_CMD_CC_INIT_RM_DATA; +typedef struct RM_GSP_SPDM_CMD_CC_INIT_RM_DATA *PRM_GSP_SPDM_CMD_CC_INIT_RM_DATA; + + +/*! + * NOTE : Do not include structure members that have alignment requirement >= 8 to avoid alignment directives + * getting added in FINN generated structures / unions as RM_GSP_SPDM_CMD / RM_GSP_SPDM_MSG are pragma packed in + * other structures like RM_FLCN_CMD_GSP / RM_FLCN_MSG_GSP and pragma pack does not produce consistent behavior + * when paired with alignment directives on Linux and Windows. + */ + +/*! + * A union of all SPDM Commands. + */ +typedef union RM_GSP_SPDM_CMD { + NvU8 cmdType; + RM_GSP_SPDM_CMD_CC_INIT ccInit; + RM_GSP_SPDM_CMD_CC_DEINIT ccDeinit; + RM_GSP_SPDM_CMD_CC_CTRL ccCtrl; + RM_GSP_SPDM_CMD_CC_INIT_RM_DATA rmDataInitCmd; + +} RM_GSP_SPDM_CMD; +typedef union RM_GSP_SPDM_CMD *PRM_GSP_SPDM_CMD; + +/***************************** SPDM MESSAGES *********************************/ + +/*! + * SPDM Message Status + */ + +/*! + * Returns the status for program CE keys to RM + */ +#define RM_GSP_SPDM_MSG_ID_CC_INIT (0x1) +#define RM_GSP_SPDM_MSG_ID_CC_DEINIT (0x2) +#define RM_GSP_SPDM_MSG_ID_CC_CTRL (0x3) +#define RM_GSP_SPDM_MSG_ID_CC_INIT_RM_DATA (0x4) + + + +/*! + * Returns the Error Status for Invalid Command + */ +#define RM_GSP_SPDM_MSG_ID_INVALID_COMMAND (0xFF) + +/*! + * NOTE : Do not include structure members that have alignment requirement >= 8 to avoid alignment directives + * getting added in FINN generated structures / unions as RM_GSP_SPDM_CMD / RM_GSP_SPDM_MSG are pragma packed in + * other structures like RM_FLCN_CMD_GSP / RM_FLCN_MSG_GSP and pragma pack does not produce consistent behavior + * when paired with alignment directives on Linux and Windows. + */ + +/*! + * SPDM message structure. + */ +typedef struct RM_GSP_SPDM_MSG { + NvU8 msgType; + + NvU32 version; + + NvU32 guestId; + + NvU32 endpointId; + + // status returned from GSP message infrastructure. + NvU32 status; + + NvU32 rsvd1; + + NvU32 rsvd2; + + NvU32 rsvd3; + + NvU32 rsvd4; + + NvBool rsvd5; +} RM_GSP_SPDM_MSG; +typedef struct RM_GSP_SPDM_MSG *PRM_GSP_SPDM_MSG; + +/* + * NV2080_CTRL_CMD_INTERNAL_SPDM_PARTITION + * + * This command does a partition switch to SPDM partition + * + */ +#define NV2080_CTRL_INTERNAL_SPDM_PARTITION (0x20800ad9) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_SPDM_PARTITION_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_INTERNAL_SPDM_PARTITION_PARAMS_MESSAGE_ID (0xD9U) + +typedef struct NV2080_CTRL_INTERNAL_SPDM_PARTITION_PARAMS { + NvU8 index; + RM_GSP_SPDM_CMD cmd; + RM_GSP_SPDM_MSG msg; +} NV2080_CTRL_INTERNAL_SPDM_PARTITION_PARAMS; + + + diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080spi.h nvidia-open-gpu-kernel-modules-535.161.08/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080spi.h --- nvidia-open-gpu-kernel-modules-525.147.05/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080spi.h 2023-10-25 20:22:15.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080spi.h 2024-03-05 22:15:08.000000000 +0000 @@ -27,6 +27,6 @@ // // This file was generated with FINN, an NVIDIA coding tool. -// Source file: ctrl/ctrl2080/ctrl2080spi.finn +// Source file: ctrl/ctrl2080/ctrl2080spi.finn // diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080thermal.h nvidia-open-gpu-kernel-modules-535.161.08/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080thermal.h --- nvidia-open-gpu-kernel-modules-525.147.05/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080thermal.h 2023-10-25 20:22:16.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080thermal.h 2024-03-05 22:15:08.000000000 +0000 @@ -25,6 +25,6 @@ // // This file was generated with FINN, an NVIDIA coding tool. -// Source file: ctrl/ctrl2080/ctrl2080thermal.finn +// Source file: ctrl/ctrl2080/ctrl2080thermal.finn // diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080tmr.h nvidia-open-gpu-kernel-modules-535.161.08/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080tmr.h --- nvidia-open-gpu-kernel-modules-525.147.05/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080tmr.h 2023-10-25 20:22:16.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080tmr.h 2024-03-05 22:15:08.000000000 +0000 @@ -27,7 +27,7 @@ // // This file was generated with FINN, an NVIDIA coding tool. -// Source file: ctrl/ctrl2080/ctrl2080tmr.finn +// Source file: ctrl/ctrl2080/ctrl2080tmr.finn // #include "ctrl/ctrl2080/ctrl2080base.h" @@ -151,16 +151,32 @@ * for a given CPU clock type. * * cpuClkId - * This parameter specifies the source of the CPU clock. Legal values for - * this parameter include: - * NV2080_TIMER_GPU_CPU_TIME_CPU_CLK_ID_OSTIME - * This clock id will provide real time in microseconds since - * 00:00:00 UTC on January 1, 1970. - * NV2080_TIMER_GPU_CPU_TIME_CPU_CLK_ID_PLATFORM_API - * This clock id will provide time stamp that is constant-rate, high - * precision using platform API that is also available in the user mode. - * NV2080_TIMER_GPU_CPU_TIME_CPU_CLK_ID_TSC - * This clock id will provide time stamp using CPU's time stamp counter. + * This parameter specifies the source of the CPU clock. This parameter is + * composed of two fields: + * NV2080_TIMER_GPU_CPU_TIME_CPU_CLK_ID_SOURCE + * This field specifies source ID of the CPU clock in question. Legal + * values for this parameter include: + * NV2080_TIMER_GPU_CPU_TIME_CPU_CLK_ID_OSTIME + * This clock id will provide real time in microseconds since + * 00:00:00 UTC on January 1, 1970, as reported by the host OS. + * NV2080_TIMER_GPU_CPU_TIME_CPU_CLK_ID_PLATFORM_API + * This clock id will provide time stamp that is constant-rate, high + * precision using platform API that is also available in the user + * mode. + * NV2080_TIMER_GPU_CPU_TIME_CPU_CLK_ID_TSC + * This clock id will provide time stamp using CPU's time stamp + * counter. + * NV2080_TIMER_GPU_CPU_TIME_CPU_CLK_ID_PROCESSOR + * This field specifies the processor whose clock should be used for the + * source. The control call and cpuClkId parameter remain named for the + * CPU specifically for legacy reasons. Not all processors will support + * all clock sources. Legal values for this parameter include: + * NV2080_TIMER_GPU_CPU_TIME_CPU_CLK_ID_PROCESSOR_CPU + * The clock information will be fulfilled by the CPU. This value + * is defined to be 0 so that it is the default for backwards + * compatibility. + * NV2080_TIMER_GPU_CPU_TIME_CPU_CLK_ID_PROCESSOR_GSP + * The clock information will be fulfilled by the GSP. * * sampleCount * This field specifies the number of clock samples to be taken. @@ -188,10 +204,21 @@ NV_DECLARE_ALIGNED(NV2080_CTRL_TIMER_GPU_CPU_TIME_SAMPLE samples[NV2080_CTRL_TIMER_GPU_CPU_TIME_MAX_SAMPLES], 8); } NV2080_CTRL_TIMER_GET_GPU_CPU_TIME_CORRELATION_INFO_PARAMS; -/* Legal cpuClkId values */ -#define NV2080_TIMER_GPU_CPU_TIME_CPU_CLK_ID_OSTIME (0x00000001) -#define NV2080_TIMER_GPU_CPU_TIME_CPU_CLK_ID_TSC (0x00000002) -#define NV2080_TIMER_GPU_CPU_TIME_CPU_CLK_ID_PLATFORM_API (0x00000003) +#define NV2080_TIMER_GPU_CPU_TIME_CPU_CLK_ID_SOURCE 3:0 + +/* Legal NV2080_TIMER_GPU_CPU_TIME_CPU_CLK_ID_SOURCE values */ +#define NV2080_TIMER_GPU_CPU_TIME_CPU_CLK_ID_OSTIME (0x00000001) +#define NV2080_TIMER_GPU_CPU_TIME_CPU_CLK_ID_TSC (0x00000002) +#define NV2080_TIMER_GPU_CPU_TIME_CPU_CLK_ID_PLATFORM_API (0x00000003) +#define NV2080_TIMER_GPU_CPU_TIME_CPU_CLK_ID_GSP_OS (0x00000004) + +#define NV2080_TIMER_GPU_CPU_TIME_CPU_CLK_ID_PROCESSOR 7:4 + +/* Legal NV2080_TIMER_GPU_CPU_TIME_CPU_CLK_ID_PROCESSOR values */ +#define NV2080_TIMER_GPU_CPU_TIME_CPU_CLK_ID_PROCESSOR_CPU (0x00000000) +#define NV2080_TIMER_GPU_CPU_TIME_CPU_CLK_ID_PROCESSOR_GSP (0x00000001) + + /*! * NV2080_CTRL_CMD_TIMER_SET_GR_TICK_FREQ * @@ -219,7 +246,7 @@ * NV_ERR_INVALID_OPERATION * NV_ERR_INVALID_STATE */ -#define NV2080_CTRL_CMD_TIMER_SET_GR_TICK_FREQ (0x20800407) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_TIMER_INTERFACE_ID << 8) | NV2080_CTRL_CMD_TIMER_SET_GR_TICK_FREQ_PARAMS_MESSAGE_ID" */ +#define NV2080_CTRL_CMD_TIMER_SET_GR_TICK_FREQ (0x20800407) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_TIMER_INTERFACE_ID << 8) | NV2080_CTRL_CMD_TIMER_SET_GR_TICK_FREQ_PARAMS_MESSAGE_ID" */ /*! * This struct contains bSetMaxFreq flag. diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080ucodefuzzer.h nvidia-open-gpu-kernel-modules-535.161.08/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080ucodefuzzer.h --- nvidia-open-gpu-kernel-modules-525.147.05/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080ucodefuzzer.h 2023-10-25 20:22:16.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080ucodefuzzer.h 2024-03-05 22:15:09.000000000 +0000 @@ -27,6 +27,6 @@ // // This file was generated with FINN, an NVIDIA coding tool. -// Source file: ctrl/ctrl2080/ctrl2080ucodefuzzer.finn +// Source file: ctrl/ctrl2080/ctrl2080ucodefuzzer.finn // diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080unix.h nvidia-open-gpu-kernel-modules-535.161.08/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080unix.h --- nvidia-open-gpu-kernel-modules-525.147.05/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080unix.h 2023-10-25 20:22:16.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080unix.h 2024-03-05 22:15:09.000000000 +0000 @@ -27,7 +27,7 @@ // // This file was generated with FINN, an NVIDIA coding tool. -// Source file: ctrl/ctrl2080/ctrl2080unix.finn +// Source file: ctrl/ctrl2080/ctrl2080unix.finn // #include "ctrl/ctrl2080/ctrl2080base.h" diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080vfe.h nvidia-open-gpu-kernel-modules-535.161.08/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080vfe.h --- nvidia-open-gpu-kernel-modules-525.147.05/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080vfe.h 2023-10-25 20:22:16.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080vfe.h 2024-03-05 22:15:09.000000000 +0000 @@ -25,7 +25,7 @@ // // This file was generated with FINN, an NVIDIA coding tool. -// Source file: ctrl/ctrl2080/ctrl2080vfe.finn +// Source file: ctrl/ctrl2080/ctrl2080vfe.finn // diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080vgpumgrinternal.h nvidia-open-gpu-kernel-modules-535.161.08/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080vgpumgrinternal.h --- nvidia-open-gpu-kernel-modules-525.147.05/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080vgpumgrinternal.h 2023-10-25 20:22:16.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080vgpumgrinternal.h 2024-03-05 22:15:09.000000000 +0000 @@ -27,7 +27,7 @@ // // This file was generated with FINN, an NVIDIA coding tool. -// Source file: ctrl/ctrl2080/ctrl2080vgpumgrinternal.finn +// Source file: ctrl/ctrl2080/ctrl2080vgpumgrinternal.finn // #include "ctrl/ctrl2080/ctrl2080base.h" diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080volt.h nvidia-open-gpu-kernel-modules-535.161.08/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080volt.h --- nvidia-open-gpu-kernel-modules-525.147.05/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080volt.h 2023-10-25 20:22:16.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080volt.h 2024-03-05 22:15:09.000000000 +0000 @@ -25,7 +25,7 @@ // // This file was generated with FINN, an NVIDIA coding tool. -// Source file: ctrl/ctrl2080/ctrl2080volt.finn +// Source file: ctrl/ctrl2080/ctrl2080volt.finn // diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/common/sdk/nvidia/inc/ctrl/ctrl2080.h nvidia-open-gpu-kernel-modules-535.161.08/src/common/sdk/nvidia/inc/ctrl/ctrl2080.h --- nvidia-open-gpu-kernel-modules-525.147.05/src/common/sdk/nvidia/inc/ctrl/ctrl2080.h 2023-10-25 20:22:11.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/common/sdk/nvidia/inc/ctrl/ctrl2080.h 2024-03-05 22:15:03.000000000 +0000 @@ -25,7 +25,7 @@ // // This file was generated with FINN, an NVIDIA coding tool. -// Source file: ctrl/ctrl2080.finn +// Source file: ctrl/ctrl2080.finn // @@ -42,6 +42,8 @@ #include "ctrl2080/ctrl2080fb.h" + +#include "ctrl2080/ctrl2080spdm.h" #include "ctrl2080/ctrl2080gr.h" #include "ctrl2080/ctrl2080bus.h" #include "ctrl2080/ctrl2080thermal.h" @@ -72,6 +74,7 @@ #include "ctrl2080/ctrl2080cipher.h" #include "ctrl2080/ctrl2080fla.h" #include "ctrl2080/ctrl2080gsp.h" +#include "ctrl2080/ctrl2080pmu.h" #include "ctrl2080/ctrl2080grmgr.h" @@ -82,3 +85,4 @@ #include "ctrl2080/ctrl2080unix.h" + diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/common/sdk/nvidia/inc/ctrl/ctrl208f/ctrl208fbase.h nvidia-open-gpu-kernel-modules-535.161.08/src/common/sdk/nvidia/inc/ctrl/ctrl208f/ctrl208fbase.h --- nvidia-open-gpu-kernel-modules-525.147.05/src/common/sdk/nvidia/inc/ctrl/ctrl208f/ctrl208fbase.h 2023-10-25 20:22:16.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/common/sdk/nvidia/inc/ctrl/ctrl208f/ctrl208fbase.h 2024-03-05 22:15:09.000000000 +0000 @@ -25,7 +25,7 @@ // // This file was generated with FINN, an NVIDIA coding tool. -// Source file: ctrl/ctrl208f/ctrl208fbase.finn +// Source file: ctrl/ctrl208f/ctrl208fbase.finn // #include "ctrl/ctrlxxxx.h" diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/common/sdk/nvidia/inc/ctrl/ctrl208f/ctrl208fbif.h nvidia-open-gpu-kernel-modules-535.161.08/src/common/sdk/nvidia/inc/ctrl/ctrl208f/ctrl208fbif.h --- nvidia-open-gpu-kernel-modules-525.147.05/src/common/sdk/nvidia/inc/ctrl/ctrl208f/ctrl208fbif.h 2023-10-25 20:22:17.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/common/sdk/nvidia/inc/ctrl/ctrl208f/ctrl208fbif.h 2024-03-05 22:15:09.000000000 +0000 @@ -27,7 +27,7 @@ // // This file was generated with FINN, an NVIDIA coding tool. -// Source file: ctrl/ctrl208f/ctrl208fbif.finn +// Source file: ctrl/ctrl208f/ctrl208fbif.finn // #include "ctrl/ctrl208f/ctrl208fbase.h" diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/common/sdk/nvidia/inc/ctrl/ctrl208f/ctrl208fbus.h nvidia-open-gpu-kernel-modules-535.161.08/src/common/sdk/nvidia/inc/ctrl/ctrl208f/ctrl208fbus.h --- nvidia-open-gpu-kernel-modules-525.147.05/src/common/sdk/nvidia/inc/ctrl/ctrl208f/ctrl208fbus.h 2023-10-25 20:22:17.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/common/sdk/nvidia/inc/ctrl/ctrl208f/ctrl208fbus.h 2024-03-05 22:15:10.000000000 +0000 @@ -27,7 +27,7 @@ // // This file was generated with FINN, an NVIDIA coding tool. -// Source file: ctrl/ctrl208f/ctrl208fbus.finn +// Source file: ctrl/ctrl208f/ctrl208fbus.finn // #include "ctrl/ctrl208f/ctrl208fbase.h" diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/common/sdk/nvidia/inc/ctrl/ctrl208f/ctrl208fclk.h nvidia-open-gpu-kernel-modules-535.161.08/src/common/sdk/nvidia/inc/ctrl/ctrl208f/ctrl208fclk.h --- nvidia-open-gpu-kernel-modules-525.147.05/src/common/sdk/nvidia/inc/ctrl/ctrl208f/ctrl208fclk.h 2023-10-25 20:22:17.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/common/sdk/nvidia/inc/ctrl/ctrl208f/ctrl208fclk.h 2024-03-05 22:15:10.000000000 +0000 @@ -28,6 +28,6 @@ // // This file was generated with FINN, an NVIDIA coding tool. -// Source file: ctrl/ctrl208f/ctrl208fclk.finn +// Source file: ctrl/ctrl208f/ctrl208fclk.finn // diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/common/sdk/nvidia/inc/ctrl/ctrl208f/ctrl208fdma.h nvidia-open-gpu-kernel-modules-535.161.08/src/common/sdk/nvidia/inc/ctrl/ctrl208f/ctrl208fdma.h --- nvidia-open-gpu-kernel-modules-525.147.05/src/common/sdk/nvidia/inc/ctrl/ctrl208f/ctrl208fdma.h 2023-10-25 20:22:17.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/common/sdk/nvidia/inc/ctrl/ctrl208f/ctrl208fdma.h 2024-03-05 22:15:10.000000000 +0000 @@ -27,7 +27,7 @@ // // This file was generated with FINN, an NVIDIA coding tool. -// Source file: ctrl/ctrl208f/ctrl208fdma.finn +// Source file: ctrl/ctrl208f/ctrl208fdma.finn // #include "ctrl/ctrl208f/ctrl208fbase.h" diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/common/sdk/nvidia/inc/ctrl/ctrl208f/ctrl208fevent.h nvidia-open-gpu-kernel-modules-535.161.08/src/common/sdk/nvidia/inc/ctrl/ctrl208f/ctrl208fevent.h --- nvidia-open-gpu-kernel-modules-525.147.05/src/common/sdk/nvidia/inc/ctrl/ctrl208f/ctrl208fevent.h 2023-10-25 20:22:17.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/common/sdk/nvidia/inc/ctrl/ctrl208f/ctrl208fevent.h 2024-03-05 22:15:10.000000000 +0000 @@ -27,7 +27,7 @@ // // This file was generated with FINN, an NVIDIA coding tool. -// Source file: ctrl/ctrl208f/ctrl208fevent.finn +// Source file: ctrl/ctrl208f/ctrl208fevent.finn // #include "ctrl/ctrl208f/ctrl208fbase.h" diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/common/sdk/nvidia/inc/ctrl/ctrl208f/ctrl208ffb.h nvidia-open-gpu-kernel-modules-535.161.08/src/common/sdk/nvidia/inc/ctrl/ctrl208f/ctrl208ffb.h --- nvidia-open-gpu-kernel-modules-525.147.05/src/common/sdk/nvidia/inc/ctrl/ctrl208f/ctrl208ffb.h 2023-10-25 20:22:17.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/common/sdk/nvidia/inc/ctrl/ctrl208f/ctrl208ffb.h 2024-03-05 22:15:10.000000000 +0000 @@ -27,7 +27,7 @@ // // This file was generated with FINN, an NVIDIA coding tool. -// Source file: ctrl/ctrl208f/ctrl208ffb.finn +// Source file: ctrl/ctrl208f/ctrl208ffb.finn // #include "ctrl/ctrl208f/ctrl208fbase.h" @@ -575,6 +575,9 @@ * remapped from the specified sources will be cleared/removed from the * Inforom RRL object entries list. * + * bForcePurge + * This flag will force purge the RRL object and associated data structures + * * Possbile status values returned are: * NV_OK * NV_ERR_NOT_SUPPORTED @@ -584,7 +587,8 @@ #define NV208F_CTRL_FB_CLEAR_REMAPPED_ROWS_PARAMS_MESSAGE_ID (0x15U) typedef struct NV208F_CTRL_FB_CLEAR_REMAPPED_ROWS_PARAMS { - NvU32 sourceMask; + NvU32 sourceMask; + NvBool bForcePurge; } NV208F_CTRL_FB_CLEAR_REMAPPED_ROWS_PARAMS; /* diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/common/sdk/nvidia/inc/ctrl/ctrl208f/ctrl208ffbio.h nvidia-open-gpu-kernel-modules-535.161.08/src/common/sdk/nvidia/inc/ctrl/ctrl208f/ctrl208ffbio.h --- nvidia-open-gpu-kernel-modules-525.147.05/src/common/sdk/nvidia/inc/ctrl/ctrl208f/ctrl208ffbio.h 2023-10-25 20:22:17.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/common/sdk/nvidia/inc/ctrl/ctrl208f/ctrl208ffbio.h 2024-03-05 22:15:10.000000000 +0000 @@ -27,7 +27,7 @@ // // This file was generated with FINN, an NVIDIA coding tool. -// Source file: ctrl/ctrl208f/ctrl208ffbio.finn +// Source file: ctrl/ctrl208f/ctrl208ffbio.finn // #include "ctrl/ctrl208f/ctrl208fbase.h" diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/common/sdk/nvidia/inc/ctrl/ctrl208f/ctrl208ffifo.h nvidia-open-gpu-kernel-modules-535.161.08/src/common/sdk/nvidia/inc/ctrl/ctrl208f/ctrl208ffifo.h --- nvidia-open-gpu-kernel-modules-525.147.05/src/common/sdk/nvidia/inc/ctrl/ctrl208f/ctrl208ffifo.h 2023-10-25 20:22:17.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/common/sdk/nvidia/inc/ctrl/ctrl208f/ctrl208ffifo.h 2024-03-05 22:15:10.000000000 +0000 @@ -27,7 +27,7 @@ // // This file was generated with FINN, an NVIDIA coding tool. -// Source file: ctrl/ctrl208f/ctrl208ffifo.finn +// Source file: ctrl/ctrl208f/ctrl208ffifo.finn // #include "ctrl/ctrl208f/ctrl208fbase.h" diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/common/sdk/nvidia/inc/ctrl/ctrl208f/ctrl208fgpu.h nvidia-open-gpu-kernel-modules-535.161.08/src/common/sdk/nvidia/inc/ctrl/ctrl208f/ctrl208fgpu.h --- nvidia-open-gpu-kernel-modules-525.147.05/src/common/sdk/nvidia/inc/ctrl/ctrl208f/ctrl208fgpu.h 2023-10-25 20:22:17.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/common/sdk/nvidia/inc/ctrl/ctrl208f/ctrl208fgpu.h 2024-03-05 22:15:11.000000000 +0000 @@ -27,7 +27,7 @@ // // This file was generated with FINN, an NVIDIA coding tool. -// Source file: ctrl/ctrl208f/ctrl208fgpu.finn +// Source file: ctrl/ctrl208f/ctrl208fgpu.finn // #include "ctrl/ctrl2080/ctrl2080gr.h" /* 208F is partially derivative of 2080 */ @@ -53,7 +53,7 @@ * NV_ERR_INVALID_ARGUMENT */ -#define NV208F_CTRL_CMD_GPU_GET_RAM_SVOP_VALUES (0x208f1101) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_DIAG_GPU_INTERFACE_ID << 8) | 0x1" */ +#define NV208F_CTRL_CMD_GPU_GET_RAM_SVOP_VALUES (0x208f1101) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_DIAG_GPU_INTERFACE_ID << 8) | NV208F_CTRL_GPU_GET_RAM_SVOP_VALUES_PARAMS_MESSAGE_ID" */ typedef struct NV208F_CTRL_GPU_RAM_SVOP_VALUES_PARAMS { NvU32 sp; @@ -62,6 +62,10 @@ NvU32 dp; } NV208F_CTRL_GPU_RAM_SVOP_VALUES_PARAMS; +#define NV208F_CTRL_GPU_GET_RAM_SVOP_VALUES_PARAMS_MESSAGE_ID (0x1U) + +typedef NV208F_CTRL_GPU_RAM_SVOP_VALUES_PARAMS NV208F_CTRL_GPU_GET_RAM_SVOP_VALUES_PARAMS; + /* * NV208F_CTRL_CMD_GPU_SET_RAM_SVOP_VALUES * @@ -82,7 +86,11 @@ * NV_ERR_INVALID_ARGUMENT */ -#define NV208F_CTRL_CMD_GPU_SET_RAM_SVOP_VALUES (0x208f1102) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_DIAG_GPU_INTERFACE_ID << 8) | 0x2" */ +#define NV208F_CTRL_CMD_GPU_SET_RAM_SVOP_VALUES (0x208f1102) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_DIAG_GPU_INTERFACE_ID << 8) | NV208F_CTRL_GPU_SET_RAM_SVOP_VALUES_PARAMS_MESSAGE_ID" */ + +#define NV208F_CTRL_GPU_SET_RAM_SVOP_VALUES_PARAMS_MESSAGE_ID (0x2U) + +typedef NV208F_CTRL_GPU_RAM_SVOP_VALUES_PARAMS NV208F_CTRL_GPU_SET_RAM_SVOP_VALUES_PARAMS; diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/common/sdk/nvidia/inc/ctrl/ctrl208f/ctrl208fgr.h nvidia-open-gpu-kernel-modules-535.161.08/src/common/sdk/nvidia/inc/ctrl/ctrl208f/ctrl208fgr.h --- nvidia-open-gpu-kernel-modules-525.147.05/src/common/sdk/nvidia/inc/ctrl/ctrl208f/ctrl208fgr.h 2023-10-25 20:22:17.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/common/sdk/nvidia/inc/ctrl/ctrl208f/ctrl208fgr.h 2024-03-05 22:15:11.000000000 +0000 @@ -27,7 +27,7 @@ // // This file was generated with FINN, an NVIDIA coding tool. -// Source file: ctrl/ctrl208f/ctrl208fgr.finn +// Source file: ctrl/ctrl208f/ctrl208fgr.finn // #include "ctrl/ctrl208f/ctrl208fbase.h" diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/common/sdk/nvidia/inc/ctrl/ctrl208f/ctrl208fmmu.h nvidia-open-gpu-kernel-modules-535.161.08/src/common/sdk/nvidia/inc/ctrl/ctrl208f/ctrl208fmmu.h --- nvidia-open-gpu-kernel-modules-525.147.05/src/common/sdk/nvidia/inc/ctrl/ctrl208f/ctrl208fmmu.h 2023-10-25 20:22:18.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/common/sdk/nvidia/inc/ctrl/ctrl208f/ctrl208fmmu.h 2024-03-05 22:15:11.000000000 +0000 @@ -27,7 +27,7 @@ // // This file was generated with FINN, an NVIDIA coding tool. -// Source file: ctrl/ctrl208f/ctrl208fmmu.finn +// Source file: ctrl/ctrl208f/ctrl208fmmu.finn // #include "ctrl/ctrl208f/ctrl208fbase.h" diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/common/sdk/nvidia/inc/ctrl/ctrl208f/ctrl208fpmgr.h nvidia-open-gpu-kernel-modules-535.161.08/src/common/sdk/nvidia/inc/ctrl/ctrl208f/ctrl208fpmgr.h --- nvidia-open-gpu-kernel-modules-525.147.05/src/common/sdk/nvidia/inc/ctrl/ctrl208f/ctrl208fpmgr.h 2023-10-25 20:22:18.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/common/sdk/nvidia/inc/ctrl/ctrl208f/ctrl208fpmgr.h 2024-03-05 22:15:11.000000000 +0000 @@ -27,6 +27,6 @@ // // This file was generated with FINN, an NVIDIA coding tool. -// Source file: ctrl/ctrl208f/ctrl208fpmgr.finn +// Source file: ctrl/ctrl208f/ctrl208fpmgr.finn // diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/common/sdk/nvidia/inc/ctrl/ctrl208f/ctrl208fpower.h nvidia-open-gpu-kernel-modules-535.161.08/src/common/sdk/nvidia/inc/ctrl/ctrl208f/ctrl208fpower.h --- nvidia-open-gpu-kernel-modules-525.147.05/src/common/sdk/nvidia/inc/ctrl/ctrl208f/ctrl208fpower.h 2023-10-25 20:22:18.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/common/sdk/nvidia/inc/ctrl/ctrl208f/ctrl208fpower.h 2024-03-05 22:15:11.000000000 +0000 @@ -27,6 +27,6 @@ // // This file was generated with FINN, an NVIDIA coding tool. -// Source file: ctrl/ctrl208f/ctrl208fpower.finn +// Source file: ctrl/ctrl208f/ctrl208fpower.finn // diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/common/sdk/nvidia/inc/ctrl/ctrl208f.h nvidia-open-gpu-kernel-modules-535.161.08/src/common/sdk/nvidia/inc/ctrl/ctrl208f.h --- nvidia-open-gpu-kernel-modules-525.147.05/src/common/sdk/nvidia/inc/ctrl/ctrl208f.h 2023-10-25 20:22:16.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/common/sdk/nvidia/inc/ctrl/ctrl208f.h 2024-03-05 22:15:09.000000000 +0000 @@ -25,7 +25,7 @@ // // This file was generated with FINN, an NVIDIA coding tool. -// Source file: ctrl/ctrl208f.finn +// Source file: ctrl/ctrl208f.finn // diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/common/sdk/nvidia/inc/ctrl/ctrl30f1.h nvidia-open-gpu-kernel-modules-535.161.08/src/common/sdk/nvidia/inc/ctrl/ctrl30f1.h --- nvidia-open-gpu-kernel-modules-525.147.05/src/common/sdk/nvidia/inc/ctrl/ctrl30f1.h 2023-10-25 20:22:18.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/common/sdk/nvidia/inc/ctrl/ctrl30f1.h 2024-03-05 22:15:11.000000000 +0000 @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 2006-2017 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2006-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -27,7 +27,7 @@ // // This file was generated with FINN, an NVIDIA coding tool. -// Source file: ctrl/ctrl30f1.finn +// Source file: ctrl/ctrl30f1.finn // #include "ctrl/ctrlxxxx.h" @@ -199,6 +199,12 @@ * useHouseSync * When a house sync signal is detected, this parameter indicates that it * should be used as the reference to generate the frame sync signal. + * syncMulDiv + * Enables multiply/divide of the frequency of the house sync signal by an + * integer. Only supported if the + * NV30F1_CTRL_GSYNC_GET_CAPS_CAP_FLAGS_MULTIPLY_DIVIDE_SYNC bit is set. The + * maximum value of multiplyDivideValue is given by + * NV30F1_CTRL_GSYNC_GET_CAPS_PARAMS.maxMulDivValue. * * Possible status values returned are: * NV_OK @@ -210,48 +216,60 @@ #define NV30F1_CTRL_CMD_GSYNC_SET_CONTROL_PARAMS (0x30f10104) /* finn: Evaluated from "(FINN_NV30_GSYNC_GSYNC_INTERFACE_ID << 8) | NV30F1_CTRL_GSYNC_SET_CONTROL_PARAMS_PARAMS_MESSAGE_ID" */ +typedef struct NV30F1_CTRL_GSYNC_MULTIPLY_DIVIDE_SETTINGS { + NvU8 multiplyDivideValue; + NvU8 multiplyDivideMode; + NvU16 rsvd; +} NV30F1_CTRL_GSYNC_MULTIPLY_DIVIDE_SETTINGS; + +typedef struct NV30F1_CTRL_GSYNC_CONTROL_PARAMS_PARAMS { + NvU32 which; + NvU32 syncPolarity; + NvU32 syncVideoMode; + NvU32 nSync; + NvU32 syncSkew; + NvU32 syncStartDelay; + NvU32 useHouseSync; + NV30F1_CTRL_GSYNC_MULTIPLY_DIVIDE_SETTINGS syncMulDiv; +} NV30F1_CTRL_GSYNC_CONTROL_PARAMS_PARAMS; + #define NV30F1_CTRL_GSYNC_GET_CONTROL_PARAMS_PARAMS_MESSAGE_ID (0x3U) -typedef struct NV30F1_CTRL_GSYNC_GET_CONTROL_PARAMS_PARAMS { - NvU32 which; - NvU32 syncPolarity; - NvU32 syncVideoMode; - NvU32 nSync; - NvU32 syncSkew; - NvU32 syncStartDelay; - NvU32 useHouseSync; -} NV30F1_CTRL_GSYNC_GET_CONTROL_PARAMS_PARAMS; +typedef NV30F1_CTRL_GSYNC_CONTROL_PARAMS_PARAMS NV30F1_CTRL_GSYNC_GET_CONTROL_PARAMS_PARAMS; + #define NV30F1_CTRL_GSYNC_SET_CONTROL_PARAMS_PARAMS_MESSAGE_ID (0x4U) -typedef NV30F1_CTRL_GSYNC_GET_CONTROL_PARAMS_PARAMS NV30F1_CTRL_GSYNC_SET_CONTROL_PARAMS_PARAMS; +typedef NV30F1_CTRL_GSYNC_CONTROL_PARAMS_PARAMS NV30F1_CTRL_GSYNC_SET_CONTROL_PARAMS_PARAMS; /* * which values * */ -#define NV30F1_CTRL_GSYNC_SET_CONTROL_SYNC_POLARITY 0x0001 -#define NV30F1_CTRL_GSYNC_SET_CONTROL_VIDEO_MODE 0x0002 -#define NV30F1_CTRL_GSYNC_SET_CONTROL_NSYNC 0x0004 -#define NV30F1_CTRL_GSYNC_SET_CONTROL_SYNC_SKEW 0x0008 -#define NV30F1_CTRL_GSYNC_SET_CONTROL_SYNC_START_DELAY 0x0010 -#define NV30F1_CTRL_GSYNC_SET_CONTROL_SYNC_USE_HOUSE 0x0020 - -#define NV30F1_CTRL_GSYNC_GET_CONTROL_SYNC_POLARITY NV30F1_CTRL_GSYNC_SET_CONTROL_SYNC_POLARITY -#define NV30F1_CTRL_GSYNC_GET_CONTROL_VIDEO_MODE NV30F1_CTRL_GSYNC_SET_CONTROL_VIDEO_MODE -#define NV30F1_CTRL_GSYNC_GET_CONTROL_NSYNC NV30F1_CTRL_GSYNC_SET_CONTROL_NSYNC -#define NV30F1_CTRL_GSYNC_GET_CONTROL_SYNC_SKEW NV30F1_CTRL_GSYNC_SET_CONTROL_SYNC_SKEW -#define NV30F1_CTRL_GSYNC_GET_CONTROL_SYNC_START_DELAY NV30F1_CTRL_GSYNC_SET_CONTROL_SYNC_START_DELAY -#define NV30F1_CTRL_GSYNC_GET_CONTROL_SYNC_USE_HOUSE NV30F1_CTRL_GSYNC_SET_CONTROL_SYNC_USE_HOUSE +#define NV30F1_CTRL_GSYNC_SET_CONTROL_SYNC_POLARITY 0x0001 +#define NV30F1_CTRL_GSYNC_SET_CONTROL_VIDEO_MODE 0x0002 +#define NV30F1_CTRL_GSYNC_SET_CONTROL_NSYNC 0x0004 +#define NV30F1_CTRL_GSYNC_SET_CONTROL_SYNC_SKEW 0x0008 +#define NV30F1_CTRL_GSYNC_SET_CONTROL_SYNC_START_DELAY 0x0010 +#define NV30F1_CTRL_GSYNC_SET_CONTROL_SYNC_USE_HOUSE 0x0020 +#define NV30F1_CTRL_GSYNC_SET_CONTROL_SYNC_MULTIPLY_DIVIDE 0x0040 + +#define NV30F1_CTRL_GSYNC_GET_CONTROL_SYNC_POLARITY NV30F1_CTRL_GSYNC_SET_CONTROL_SYNC_POLARITY +#define NV30F1_CTRL_GSYNC_GET_CONTROL_VIDEO_MODE NV30F1_CTRL_GSYNC_SET_CONTROL_VIDEO_MODE +#define NV30F1_CTRL_GSYNC_GET_CONTROL_NSYNC NV30F1_CTRL_GSYNC_SET_CONTROL_NSYNC +#define NV30F1_CTRL_GSYNC_GET_CONTROL_SYNC_SKEW NV30F1_CTRL_GSYNC_SET_CONTROL_SYNC_SKEW +#define NV30F1_CTRL_GSYNC_GET_CONTROL_SYNC_START_DELAY NV30F1_CTRL_GSYNC_SET_CONTROL_SYNC_START_DELAY +#define NV30F1_CTRL_GSYNC_GET_CONTROL_SYNC_USE_HOUSE NV30F1_CTRL_GSYNC_SET_CONTROL_SYNC_USE_HOUSE +#define NV30F1_CTRL_GSYNC_GET_CONTROL_SYNC_MULTIPLY_DIVIDE NV30F1_CTRL_GSYNC_SET_CONTROL_SYNC_MULTIPLY_DIVIDE /* * syncPolarity values * */ -#define NV30F1_CTRL_GSYNC_SET_CONTROL_SYNC_POLARITY_RISING_EDGE 0 -#define NV30F1_CTRL_GSYNC_SET_CONTROL_SYNC_POLARITY_FALLING_EDGE 1 -#define NV30F1_CTRL_GSYNC_SET_CONTROL_SYNC_POLARITY_BOTH_EDGES 2 +#define NV30F1_CTRL_GSYNC_SET_CONTROL_SYNC_POLARITY_RISING_EDGE 0 +#define NV30F1_CTRL_GSYNC_SET_CONTROL_SYNC_POLARITY_FALLING_EDGE 1 +#define NV30F1_CTRL_GSYNC_SET_CONTROL_SYNC_POLARITY_BOTH_EDGES 2 /* * syncVideoMode values @@ -259,16 +277,23 @@ * */ -#define NV30F1_CTRL_GSYNC_SET_CONTROL_VIDEO_MODE_NONE 0 -#define NV30F1_CTRL_GSYNC_SET_CONTROL_VIDEO_MODE_TTL 1 -#define NV30F1_CTRL_GSYNC_SET_CONTROL_VIDEO_MODE_NTSCPALSECAM 2 -#define NV30F1_CTRL_GSYNC_SET_CONTROL_VIDEO_MODE_HDTV 3 - -#define NV30F1_CTRL_GSYNC_GET_CONTROL_VIDEO_MODE_NONE NV30F1_CTRL_GSYNC_SET_CONTROL_VIDEO_MODE_NONE -#define NV30F1_CTRL_GSYNC_GET_CONTROL_VIDEO_MODE_TTL NV30F1_CTRL_GSYNC_SET_CONTROL_VIDEO_MODE_TTL -#define NV30F1_CTRL_GSYNC_GET_CONTROL_VIDEO_MODE_NTSCPALSECAM NV30F1_CTRL_GSYNC_SET_CONTROL_VIDEO_MODE_NTSCPALSECAM -#define NV30F1_CTRL_GSYNC_GET_CONTROL_VIDEO_MODE_HDTV NV30F1_CTRL_GSYNC_SET_CONTROL_VIDEO_MODE_HDTV -#define NV30F1_CTRL_GSYNC_GET_CONTROL_VIDEO_MODE_COMPOSITE 4 +#define NV30F1_CTRL_GSYNC_SET_CONTROL_VIDEO_MODE_NONE 0 +#define NV30F1_CTRL_GSYNC_SET_CONTROL_VIDEO_MODE_TTL 1 +#define NV30F1_CTRL_GSYNC_SET_CONTROL_VIDEO_MODE_NTSCPALSECAM 2 +#define NV30F1_CTRL_GSYNC_SET_CONTROL_VIDEO_MODE_HDTV 3 + +#define NV30F1_CTRL_GSYNC_GET_CONTROL_VIDEO_MODE_NONE NV30F1_CTRL_GSYNC_SET_CONTROL_VIDEO_MODE_NONE +#define NV30F1_CTRL_GSYNC_GET_CONTROL_VIDEO_MODE_TTL NV30F1_CTRL_GSYNC_SET_CONTROL_VIDEO_MODE_TTL +#define NV30F1_CTRL_GSYNC_GET_CONTROL_VIDEO_MODE_NTSCPALSECAM NV30F1_CTRL_GSYNC_SET_CONTROL_VIDEO_MODE_NTSCPALSECAM +#define NV30F1_CTRL_GSYNC_GET_CONTROL_VIDEO_MODE_HDTV NV30F1_CTRL_GSYNC_SET_CONTROL_VIDEO_MODE_HDTV +#define NV30F1_CTRL_GSYNC_GET_CONTROL_VIDEO_MODE_COMPOSITE 4 + +/* + * multiplyDivide values + * + */ +#define NV30F1_CTRL_GSYNC_SET_CONTROL_MULTIPLY_DIVIDE_MODE_MULTIPLY 0 +#define NV30F1_CTRL_GSYNC_SET_CONTROL_MULTIPLY_DIVIDE_MODE_DIVIDE 1 /* * NV30F1_CTRL_CMD_GSYNC_GET_CAPS @@ -330,13 +355,18 @@ * programmed into the board has to be between 0 and maxSyncInterval, * inclusive. * + * maxMulDivValue + * This parameter returns the maximum possible value that can be + * programmed for multiplying / dividing house sync. Only valid if + * NV30F1_CTRL_GSYNC_GET_CAPS_CAP_FLAGS_MULTIPLY_DIVIDE_SYNC is set. + * * Possible status values returned are: * NV_OK * NV_ERR_GENERIC * NV_ERR_INVALID_ARGUMENT */ -#define NV30F1_CTRL_CMD_GSYNC_GET_CAPS (0x30f10105) /* finn: Evaluated from "(FINN_NV30_GSYNC_GSYNC_INTERFACE_ID << 8) | NV30F1_CTRL_GSYNC_GET_CAPS_PARAMS_MESSAGE_ID" */ +#define NV30F1_CTRL_CMD_GSYNC_GET_CAPS (0x30f10105) /* finn: Evaluated from "(FINN_NV30_GSYNC_GSYNC_INTERFACE_ID << 8) | NV30F1_CTRL_GSYNC_GET_CAPS_PARAMS_MESSAGE_ID" */ #define NV30F1_CTRL_GSYNC_GET_CAPS_PARAMS_MESSAGE_ID (0x5U) @@ -353,6 +383,7 @@ NvU32 maxStartDelay; NvU32 startDelayResolution; NvU32 maxSyncInterval; + NvU32 maxMulDivValue; } NV30F1_CTRL_GSYNC_GET_CAPS_PARAMS; #define NV30F1_CTRL_GSYNC_GET_CAPS_BOARD_ID_P2060 (0x00002060) @@ -363,6 +394,7 @@ #define NV30F1_CTRL_GSYNC_GET_CAPS_CAP_FLAGS_FREQ_ACCURACY_4DPS (0x00000004) #define NV30F1_CTRL_GSYNC_GET_CAPS_CAP_FLAGS_NEED_MASTER_BARRIER_WAR (0x00000010) +#define NV30F1_CTRL_GSYNC_GET_CAPS_CAP_FLAGS_MULTIPLY_DIVIDE_SYNC (0x00000020) #define NV30F1_CTRL_GSYNC_GET_CAPS_CAP_FLAGS_SYNC_LOCK_EVENT (0x10000000) #define NV30F1_CTRL_GSYNC_GET_CAPS_CAP_FLAGS_HOUSE_SYNC_EVENT (0x20000000) @@ -482,19 +514,22 @@ // If set the swapbarrier is not enable automatically when enablign a framelock master on fpga revs <= 5. #define NV30F1_CTRL_GSYNC_GET_CONTROL_SYNC_CONFIG_FLAGS_KEEP_MASTER_SWAPBARRIER_DISABLED (0x00000001) -#define NV30F1_CTRL_GSYNC_GET_CONTROL_SYNC_PARAMS_MESSAGE_ID (0x10U) - -typedef struct NV30F1_CTRL_GSYNC_GET_CONTROL_SYNC_PARAMS { +typedef struct NV30F1_CTRL_GSYNC_CONTROL_SYNC_PARAMS { NvU32 gpuId; NvU32 master; NvU32 displays; NvU32 validateExternal; NvU32 refresh; NvU32 configFlags; -} NV30F1_CTRL_GSYNC_GET_CONTROL_SYNC_PARAMS; +} NV30F1_CTRL_GSYNC_CONTROL_SYNC_PARAMS; + +#define NV30F1_CTRL_GSYNC_GET_CONTROL_SYNC_PARAMS_MESSAGE_ID (0x10U) + +typedef NV30F1_CTRL_GSYNC_CONTROL_SYNC_PARAMS NV30F1_CTRL_GSYNC_GET_CONTROL_SYNC_PARAMS; + #define NV30F1_CTRL_GSYNC_SET_CONTROL_SYNC_PARAMS_MESSAGE_ID (0x11U) -typedef NV30F1_CTRL_GSYNC_GET_CONTROL_SYNC_PARAMS NV30F1_CTRL_GSYNC_SET_CONTROL_SYNC_PARAMS; +typedef NV30F1_CTRL_GSYNC_CONTROL_SYNC_PARAMS NV30F1_CTRL_GSYNC_SET_CONTROL_SYNC_PARAMS; /* * NV30F1_CTRL_CMD_GSYNC_SET_CONTROL_UNSYNC @@ -705,14 +740,17 @@ #define NV30F1_CTRL_CMD_GSYNC_SET_CONTROL_TESTING (0x30f10121) /* finn: Evaluated from "(FINN_NV30_GSYNC_GSYNC_INTERFACE_ID << 8) | NV30F1_CTRL_GSYNC_SET_CONTROL_TESTING_PARAMS_MESSAGE_ID" */ -#define NV30F1_CTRL_GSYNC_SET_CONTROL_TESTING_PARAMS_MESSAGE_ID (0x21U) - -typedef struct NV30F1_CTRL_GSYNC_SET_CONTROL_TESTING_PARAMS { +typedef struct NV30F1_CTRL_GSYNC_CONTROL_TESTING_PARAMS { NvU32 bEmitTestSignal; -} NV30F1_CTRL_GSYNC_SET_CONTROL_TESTING_PARAMS; +} NV30F1_CTRL_GSYNC_CONTROL_TESTING_PARAMS; + #define NV30F1_CTRL_GSYNC_GET_CONTROL_TESTING_PARAMS_MESSAGE_ID (0x20U) -typedef NV30F1_CTRL_GSYNC_SET_CONTROL_TESTING_PARAMS NV30F1_CTRL_GSYNC_GET_CONTROL_TESTING_PARAMS; +typedef NV30F1_CTRL_GSYNC_CONTROL_TESTING_PARAMS NV30F1_CTRL_GSYNC_GET_CONTROL_TESTING_PARAMS; + +#define NV30F1_CTRL_GSYNC_SET_CONTROL_TESTING_PARAMS_MESSAGE_ID (0x21U) + +typedef NV30F1_CTRL_GSYNC_CONTROL_TESTING_PARAMS NV30F1_CTRL_GSYNC_SET_CONTROL_TESTING_PARAMS; /* * NV30F1_CTRL_CMD_GSYNC_SET_CONTROL_WATCHDOG @@ -756,14 +794,17 @@ #define NV30F1_CTRL_CMD_GSYNC_SET_CONTROL_INTERLACE_MODE (0x30f10141) /* finn: Evaluated from "(FINN_NV30_GSYNC_GSYNC_INTERFACE_ID << 8) | NV30F1_CTRL_GSYNC_SET_CONTROL_INTERLACE_MODE_PARAMS_MESSAGE_ID" */ -#define NV30F1_CTRL_GSYNC_SET_CONTROL_INTERLACE_MODE_PARAMS_MESSAGE_ID (0x41U) - -typedef struct NV30F1_CTRL_GSYNC_SET_CONTROL_INTERLACE_MODE_PARAMS { +typedef struct NV30F1_CTRL_GSYNC_CONTROL_INTERLACE_MODE_PARAMS { NvU32 enable; -} NV30F1_CTRL_GSYNC_SET_CONTROL_INTERLACE_MODE_PARAMS; +} NV30F1_CTRL_GSYNC_CONTROL_INTERLACE_MODE_PARAMS; + #define NV30F1_CTRL_GSYNC_GET_CONTROL_INTERLACE_MODE_PARAMS_MESSAGE_ID (0x40U) -typedef NV30F1_CTRL_GSYNC_SET_CONTROL_INTERLACE_MODE_PARAMS NV30F1_CTRL_GSYNC_GET_CONTROL_INTERLACE_MODE_PARAMS; +typedef NV30F1_CTRL_GSYNC_CONTROL_INTERLACE_MODE_PARAMS NV30F1_CTRL_GSYNC_GET_CONTROL_INTERLACE_MODE_PARAMS; + +#define NV30F1_CTRL_GSYNC_SET_CONTROL_INTERLACE_MODE_PARAMS_MESSAGE_ID (0x41U) + +typedef NV30F1_CTRL_GSYNC_CONTROL_INTERLACE_MODE_PARAMS NV30F1_CTRL_GSYNC_SET_CONTROL_INTERLACE_MODE_PARAMS; /* * @@ -795,15 +836,18 @@ #define NV30F1_CTRL_CMD_GSYNC_SET_CONTROL_SWAP_BARRIER (0x30f10151) /* finn: Evaluated from "(FINN_NV30_GSYNC_GSYNC_INTERFACE_ID << 8) | NV30F1_CTRL_GSYNC_SET_CONTROL_SWAP_BARRIER_PARAMS_MESSAGE_ID" */ -#define NV30F1_CTRL_GSYNC_SET_CONTROL_SWAP_BARRIER_PARAMS_MESSAGE_ID (0x51U) - -typedef struct NV30F1_CTRL_GSYNC_SET_CONTROL_SWAP_BARRIER_PARAMS { +typedef struct NV30F1_CTRL_GSYNC_CONTROL_SWAP_BARRIER_PARAMS { NvU32 gpuId; NvBool enable; -} NV30F1_CTRL_GSYNC_SET_CONTROL_SWAP_BARRIER_PARAMS; +} NV30F1_CTRL_GSYNC_CONTROL_SWAP_BARRIER_PARAMS; + #define NV30F1_CTRL_GSYNC_GET_CONTROL_SWAP_BARRIER_PARAMS_MESSAGE_ID (0x50U) -typedef NV30F1_CTRL_GSYNC_SET_CONTROL_SWAP_BARRIER_PARAMS NV30F1_CTRL_GSYNC_GET_CONTROL_SWAP_BARRIER_PARAMS; +typedef NV30F1_CTRL_GSYNC_CONTROL_SWAP_BARRIER_PARAMS NV30F1_CTRL_GSYNC_GET_CONTROL_SWAP_BARRIER_PARAMS; + +#define NV30F1_CTRL_GSYNC_SET_CONTROL_SWAP_BARRIER_PARAMS_MESSAGE_ID (0x51U) + +typedef NV30F1_CTRL_GSYNC_CONTROL_SWAP_BARRIER_PARAMS NV30F1_CTRL_GSYNC_SET_CONTROL_SWAP_BARRIER_PARAMS; /* * NV30F1_CTRL_CMD_GSYNC_GET_CONTROL_SWAP_LOCK_WINDOW @@ -843,10 +887,6 @@ * This parameter is set by the client to indicate the * gpuId of the GPU to which the display to be optimized * is attached. - * display - * This parameter is not used by RM currently. - * Clients can ignore this parameter. Note that this - * parameter will be removed in future. * output * This parameter is set by the client to indicate the * output resource type of the display to be optimized. @@ -989,6 +1029,12 @@ * optimal pixel clock to use with the adjusted mode, * in units of Hz. * + * + * bOptimized[out] + * This is set to NV_TRUE if the timings were successfully optimized, and + * NV_FALSE otherwise. + * + * * Progressive Raster Structure * * hSyncEnd hTotal @@ -1101,28 +1147,29 @@ #define NV30F1_CTRL_GSYNC_GET_OPTIMIZED_TIMING_PARAMS_MESSAGE_ID (0x60U) typedef struct NV30F1_CTRL_GSYNC_GET_OPTIMIZED_TIMING_PARAMS { - NvU32 gpuId; - NvU32 display; - NvU32 output; - NvU32 protocol; - NvU32 structure; - NvU32 adjust; - NvU32 hDeltaStep; - NvU32 hDeltaMax; - NvU32 vDeltaStep; - NvU32 vDeltaMax; - NvU32 hSyncEnd; - NvU32 hBlankEnd; - NvU32 hBlankStart; - NvU32 hTotal; - NvU32 vSyncEnd; - NvU32 vBlankEnd; - NvU32 vBlankStart; - NvU32 vInterlacedBlankEnd; - NvU32 vInterlacedBlankStart; - NvU32 vTotal; - NvU32 refreshX10K; - NvU32 pixelClockHz; + NvU32 gpuId; + NvU32 output; + NvU32 protocol; + NvU32 structure; + NvU32 adjust; + NvU32 hDeltaStep; + NvU32 hDeltaMax; + NvU32 vDeltaStep; + NvU32 vDeltaMax; + NvU32 hSyncEnd; + NvU32 hBlankEnd; + NvU32 hBlankStart; + NvU32 hTotal; + NvU32 vSyncEnd; + NvU32 vBlankEnd; + NvU32 vBlankStart; + NvU32 vInterlacedBlankEnd; + NvU32 vInterlacedBlankStart; + NvU32 vTotal; + NvU32 refreshX10K; + NvU32 pixelClockHz; + + NvBool bOptimized; } NV30F1_CTRL_GSYNC_GET_OPTIMIZED_TIMING_PARAMS; /* output values */ @@ -1285,15 +1332,18 @@ #define NV30F1_CTRL_CMD_GSYNC_GET_CONTROL_STEREO_LOCK_MODE (0x30f10173) /* finn: Evaluated from "(FINN_NV30_GSYNC_GSYNC_INTERFACE_ID << 8) | NV30F1_CTRL_CMD_GSYNC_GET_CONTROL_STEREO_LOCK_MODE_PARAMS_MESSAGE_ID" */ -#define NV30F1_CTRL_CMD_GSYNC_SET_CONTROL_STEREO_LOCK_MODE_PARAMS_MESSAGE_ID (0x72U) - -typedef struct NV30F1_CTRL_CMD_GSYNC_SET_CONTROL_STEREO_LOCK_MODE_PARAMS { +typedef struct NV30F1_CTRL_CMD_GSYNC_CONTROL_STEREO_LOCK_MODE_PARAMS { NvU32 gpuId; NvU32 enable; -} NV30F1_CTRL_CMD_GSYNC_SET_CONTROL_STEREO_LOCK_MODE_PARAMS; +} NV30F1_CTRL_CMD_GSYNC_CONTROL_STEREO_LOCK_MODE_PARAMS; + +#define NV30F1_CTRL_CMD_GSYNC_SET_CONTROL_STEREO_LOCK_MODE_PARAMS_MESSAGE_ID (0x72U) + +typedef NV30F1_CTRL_CMD_GSYNC_CONTROL_STEREO_LOCK_MODE_PARAMS NV30F1_CTRL_CMD_GSYNC_SET_CONTROL_STEREO_LOCK_MODE_PARAMS; + #define NV30F1_CTRL_CMD_GSYNC_GET_CONTROL_STEREO_LOCK_MODE_PARAMS_MESSAGE_ID (0x73U) -typedef NV30F1_CTRL_CMD_GSYNC_SET_CONTROL_STEREO_LOCK_MODE_PARAMS NV30F1_CTRL_CMD_GSYNC_GET_CONTROL_STEREO_LOCK_MODE_PARAMS; +typedef NV30F1_CTRL_CMD_GSYNC_CONTROL_STEREO_LOCK_MODE_PARAMS NV30F1_CTRL_CMD_GSYNC_GET_CONTROL_STEREO_LOCK_MODE_PARAMS; /* * NV30F1_CTRL_CMD_GSYNC_READ_REGISTER @@ -1478,14 +1528,21 @@ * NV_ERR_INVALID_STATE * */ -#define NV30F1_CTRL_CMD_GSYNC_GET_HOUSE_SYNC_MODE (0x30f10187) /* finn: Evaluated from "(FINN_NV30_GSYNC_GSYNC_INTERFACE_ID << 8) | 0x87" */ - -#define NV30F1_CTRL_CMD_GSYNC_SET_HOUSE_SYNC_MODE (0x30f10188) /* finn: Evaluated from "(FINN_NV30_GSYNC_GSYNC_INTERFACE_ID << 8) | 0x88" */ +#define NV30F1_CTRL_CMD_GSYNC_GET_HOUSE_SYNC_MODE (0x30f10187) /* finn: Evaluated from "(FINN_NV30_GSYNC_GSYNC_INTERFACE_ID << 8) | NV30F1_CTRL_GSYNC_GET_HOUSE_SYNC_MODE_PARAMS_MESSAGE_ID" */ typedef struct NV30F1_CTRL_GSYNC_HOUSE_SYNC_MODE_PARAMS { NvU8 houseSyncMode; } NV30F1_CTRL_GSYNC_HOUSE_SYNC_MODE_PARAMS; +#define NV30F1_CTRL_GSYNC_GET_HOUSE_SYNC_MODE_PARAMS_MESSAGE_ID (0x87U) + +typedef NV30F1_CTRL_GSYNC_HOUSE_SYNC_MODE_PARAMS NV30F1_CTRL_GSYNC_GET_HOUSE_SYNC_MODE_PARAMS; + +#define NV30F1_CTRL_CMD_GSYNC_SET_HOUSE_SYNC_MODE (0x30f10188) /* finn: Evaluated from "(FINN_NV30_GSYNC_GSYNC_INTERFACE_ID << 8) | NV30F1_CTRL_GSYNC_SET_HOUSE_SYNC_MODE_PARAMS_MESSAGE_ID" */ + +#define NV30F1_CTRL_GSYNC_SET_HOUSE_SYNC_MODE_PARAMS_MESSAGE_ID (0x88U) + +typedef NV30F1_CTRL_GSYNC_HOUSE_SYNC_MODE_PARAMS NV30F1_CTRL_GSYNC_SET_HOUSE_SYNC_MODE_PARAMS; #define NV30F1_CTRL_GSYNC_HOUSE_SYNC_MODE_INPUT (0x00) #define NV30F1_CTRL_GSYNC_HOUSE_SYNC_MODE_OUTPUT (0x01) diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/common/sdk/nvidia/inc/ctrl/ctrl402c.h nvidia-open-gpu-kernel-modules-535.161.08/src/common/sdk/nvidia/inc/ctrl/ctrl402c.h --- nvidia-open-gpu-kernel-modules-525.147.05/src/common/sdk/nvidia/inc/ctrl/ctrl402c.h 2023-10-25 20:22:18.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/common/sdk/nvidia/inc/ctrl/ctrl402c.h 2024-03-05 22:15:11.000000000 +0000 @@ -27,7 +27,7 @@ // // This file was generated with FINN, an NVIDIA coding tool. -// Source file: ctrl/ctrl402c.finn +// Source file: ctrl/ctrl402c.finn // #include "ctrl/ctrlxxxx.h" diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/common/sdk/nvidia/inc/ctrl/ctrl503c/ctrl503cbase.h nvidia-open-gpu-kernel-modules-535.161.08/src/common/sdk/nvidia/inc/ctrl/ctrl503c/ctrl503cbase.h --- nvidia-open-gpu-kernel-modules-525.147.05/src/common/sdk/nvidia/inc/ctrl/ctrl503c/ctrl503cbase.h 2023-10-25 20:22:18.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/common/sdk/nvidia/inc/ctrl/ctrl503c/ctrl503cbase.h 2024-03-05 22:15:11.000000000 +0000 @@ -25,7 +25,7 @@ // // This file was generated with FINN, an NVIDIA coding tool. -// Source file: ctrl/ctrl503c/ctrl503cbase.finn +// Source file: ctrl/ctrl503c/ctrl503cbase.finn // #include "ctrl/ctrlxxxx.h" diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/common/sdk/nvidia/inc/ctrl/ctrl503c.h nvidia-open-gpu-kernel-modules-535.161.08/src/common/sdk/nvidia/inc/ctrl/ctrl503c.h --- nvidia-open-gpu-kernel-modules-525.147.05/src/common/sdk/nvidia/inc/ctrl/ctrl503c.h 2023-10-25 20:22:18.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/common/sdk/nvidia/inc/ctrl/ctrl503c.h 2024-03-05 22:15:11.000000000 +0000 @@ -27,7 +27,7 @@ // // This file was generated with FINN, an NVIDIA coding tool. -// Source file: ctrl/ctrl503c.finn +// Source file: ctrl/ctrl503c.finn // #include "ctrl/ctrlxxxx.h" diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/common/sdk/nvidia/inc/ctrl/ctrl506f.h nvidia-open-gpu-kernel-modules-535.161.08/src/common/sdk/nvidia/inc/ctrl/ctrl506f.h --- nvidia-open-gpu-kernel-modules-525.147.05/src/common/sdk/nvidia/inc/ctrl/ctrl506f.h 2023-10-25 20:22:18.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/common/sdk/nvidia/inc/ctrl/ctrl506f.h 2024-03-05 22:15:12.000000000 +0000 @@ -27,7 +27,7 @@ // // This file was generated with FINN, an NVIDIA coding tool. -// Source file: ctrl/ctrl506f.finn +// Source file: ctrl/ctrl506f.finn // #include "ctrl/ctrlxxxx.h" diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/common/sdk/nvidia/inc/ctrl/ctrl5070/ctrl5070base.h nvidia-open-gpu-kernel-modules-535.161.08/src/common/sdk/nvidia/inc/ctrl/ctrl5070/ctrl5070base.h --- nvidia-open-gpu-kernel-modules-525.147.05/src/common/sdk/nvidia/inc/ctrl/ctrl5070/ctrl5070base.h 2023-10-25 20:22:18.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/common/sdk/nvidia/inc/ctrl/ctrl5070/ctrl5070base.h 2024-03-05 22:15:12.000000000 +0000 @@ -27,7 +27,7 @@ // // This file was generated with FINN, an NVIDIA coding tool. -// Source file: ctrl/ctrl5070/ctrl5070base.finn +// Source file: ctrl/ctrl5070/ctrl5070base.finn // #include "ctrl/ctrlxxxx.h" diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/common/sdk/nvidia/inc/ctrl/ctrl5070/ctrl5070chnc.h nvidia-open-gpu-kernel-modules-535.161.08/src/common/sdk/nvidia/inc/ctrl/ctrl5070/ctrl5070chnc.h --- nvidia-open-gpu-kernel-modules-525.147.05/src/common/sdk/nvidia/inc/ctrl/ctrl5070/ctrl5070chnc.h 2023-10-25 20:22:18.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/common/sdk/nvidia/inc/ctrl/ctrl5070/ctrl5070chnc.h 2024-03-05 22:15:12.000000000 +0000 @@ -27,7 +27,7 @@ // // This file was generated with FINN, an NVIDIA coding tool. -// Source file: ctrl/ctrl5070/ctrl5070chnc.finn +// Source file: ctrl/ctrl5070/ctrl5070chnc.finn // #include "ctrl/ctrl5070/ctrl5070base.h" diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/common/sdk/nvidia/inc/ctrl/ctrl5070/ctrl5070common.h nvidia-open-gpu-kernel-modules-535.161.08/src/common/sdk/nvidia/inc/ctrl/ctrl5070/ctrl5070common.h --- nvidia-open-gpu-kernel-modules-525.147.05/src/common/sdk/nvidia/inc/ctrl/ctrl5070/ctrl5070common.h 2023-10-25 20:22:19.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/common/sdk/nvidia/inc/ctrl/ctrl5070/ctrl5070common.h 2024-03-05 22:15:12.000000000 +0000 @@ -25,7 +25,7 @@ // // This file was generated with FINN, an NVIDIA coding tool. -// Source file: ctrl/ctrl5070/ctrl5070common.finn +// Source file: ctrl/ctrl5070/ctrl5070common.finn // diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/common/sdk/nvidia/inc/ctrl/ctrl5070/ctrl5070event.h nvidia-open-gpu-kernel-modules-535.161.08/src/common/sdk/nvidia/inc/ctrl/ctrl5070/ctrl5070event.h --- nvidia-open-gpu-kernel-modules-525.147.05/src/common/sdk/nvidia/inc/ctrl/ctrl5070/ctrl5070event.h 2023-10-25 20:22:19.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/common/sdk/nvidia/inc/ctrl/ctrl5070/ctrl5070event.h 2024-03-05 22:15:12.000000000 +0000 @@ -27,7 +27,7 @@ // // This file was generated with FINN, an NVIDIA coding tool. -// Source file: ctrl/ctrl5070/ctrl5070event.finn +// Source file: ctrl/ctrl5070/ctrl5070event.finn // #include "ctrl/ctrl5070/ctrl5070base.h" diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/common/sdk/nvidia/inc/ctrl/ctrl5070/ctrl5070impoverrides.h nvidia-open-gpu-kernel-modules-535.161.08/src/common/sdk/nvidia/inc/ctrl/ctrl5070/ctrl5070impoverrides.h --- nvidia-open-gpu-kernel-modules-525.147.05/src/common/sdk/nvidia/inc/ctrl/ctrl5070/ctrl5070impoverrides.h 2023-10-25 20:22:19.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/common/sdk/nvidia/inc/ctrl/ctrl5070/ctrl5070impoverrides.h 2024-03-05 22:15:12.000000000 +0000 @@ -25,7 +25,7 @@ // // This file was generated with FINN, an NVIDIA coding tool. -// Source file: ctrl/ctrl5070/ctrl5070impoverrides.finn +// Source file: ctrl/ctrl5070/ctrl5070impoverrides.finn // diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/common/sdk/nvidia/inc/ctrl/ctrl5070/ctrl5070or.h nvidia-open-gpu-kernel-modules-535.161.08/src/common/sdk/nvidia/inc/ctrl/ctrl5070/ctrl5070or.h --- nvidia-open-gpu-kernel-modules-525.147.05/src/common/sdk/nvidia/inc/ctrl/ctrl5070/ctrl5070or.h 2023-10-25 20:22:19.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/common/sdk/nvidia/inc/ctrl/ctrl5070/ctrl5070or.h 2024-03-05 22:15:13.000000000 +0000 @@ -27,7 +27,7 @@ // // This file was generated with FINN, an NVIDIA coding tool. -// Source file: ctrl/ctrl5070/ctrl5070or.finn +// Source file: ctrl/ctrl5070/ctrl5070or.finn // #include "ctrl5070common.h" diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/common/sdk/nvidia/inc/ctrl/ctrl5070/ctrl5070rg.h nvidia-open-gpu-kernel-modules-535.161.08/src/common/sdk/nvidia/inc/ctrl/ctrl5070/ctrl5070rg.h --- nvidia-open-gpu-kernel-modules-525.147.05/src/common/sdk/nvidia/inc/ctrl/ctrl5070/ctrl5070rg.h 2023-10-25 20:22:19.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/common/sdk/nvidia/inc/ctrl/ctrl5070/ctrl5070rg.h 2024-03-05 22:15:13.000000000 +0000 @@ -27,7 +27,7 @@ // // This file was generated with FINN, an NVIDIA coding tool. -// Source file: ctrl/ctrl5070/ctrl5070rg.finn +// Source file: ctrl/ctrl5070/ctrl5070rg.finn // #include "ctrl/ctrl5070/ctrl5070base.h" @@ -257,65 +257,6 @@ } NV5070_CTRL_CMD_SET_RG_FLIPLOCK_PROP_PARAMS; /* - * NV5070_CTRL_CMD_GET_RG_CONNECTED_LOCKPIN - * - * This command returns which lockpin has been connected for the specified - * subdevice in the current SLI and/or framelock configuration. - * - * head - * The head for which the locking is associated with - * - * masterScanLock - * Indicate the connection status and pin number of master scanlock - * - * slaveScanLock - * Indicate the connection status and pin number of slave scanlock - * - * flipLock - * Indicate the connection status and pin number of fliplock - * - * stereoLock - * Indicate the connection status and pin number of stereo lock - * - * Possible status values returned are: - * NV_OK - * NV_ERR_INVALID_ARGUMENT - */ -#define NV5070_CTRL_CMD_GET_RG_CONNECTED_LOCKPIN (0x50700207) /* finn: Evaluated from "(FINN_NV50_DISPLAY_RG_INTERFACE_ID << 8) | NV5070_CTRL_CMD_GET_RG_CONNECTED_LOCKPIN_PARAMS_MESSAGE_ID" */ - -#define NV5070_CTRL_CMD_GET_RG_CONNECTED_LOCKPIN_MASTER_SCAN_LOCK_CONNECTED 0:0 -#define NV5070_CTRL_CMD_GET_RG_CONNECTED_LOCKPIN_MASTER_SCAN_LOCK_CONNECTED_NO (0x00000000) -#define NV5070_CTRL_CMD_GET_RG_CONNECTED_LOCKPIN_MASTER_SCAN_LOCK_CONNECTED_YES (0x00000001) -#define NV5070_CTRL_CMD_GET_RG_CONNECTED_LOCKPIN_MASTER_SCAN_LOCK_PIN 3:1 - -#define NV5070_CTRL_CMD_GET_RG_CONNECTED_LOCKPIN_SLAVE_SCAN_LOCK_CONNECTED 0:0 -#define NV5070_CTRL_CMD_GET_RG_CONNECTED_LOCKPIN_SLAVE_SCAN_LOCK_CONNECTED_NO (0x00000000) -#define NV5070_CTRL_CMD_GET_RG_CONNECTED_LOCKPIN_SLAVE_SCAN_LOCK_CONNECTED_YES (0x00000001) -#define NV5070_CTRL_CMD_GET_RG_CONNECTED_LOCKPIN_SLAVE_SCAN_LOCK_PIN 3:1 - -#define NV5070_CTRL_CMD_GET_RG_CONNECTED_LOCKPIN_FLIP_LOCK_CONNECTED 0:0 -#define NV5070_CTRL_CMD_GET_RG_CONNECTED_LOCKPIN_FLIP_LOCK_CONNECTED_NO (0x00000000) -#define NV5070_CTRL_CMD_GET_RG_CONNECTED_LOCKPIN_FLIP_LOCK_CONNECTED_YES (0x00000001) -#define NV5070_CTRL_CMD_GET_RG_CONNECTED_LOCKPIN_FLIP_LOCK_PIN 3:1 - -#define NV5070_CTRL_CMD_GET_RG_CONNECTED_LOCKPIN_STEREO_LOCK_CONNECTED 0:0 -#define NV5070_CTRL_CMD_GET_RG_CONNECTED_LOCKPIN_STEREO_LOCK_CONNECTED_NO (0x00000000) -#define NV5070_CTRL_CMD_GET_RG_CONNECTED_LOCKPIN_STEREO_LOCK_CONNECTED_YES (0x00000001) -#define NV5070_CTRL_CMD_GET_RG_CONNECTED_LOCKPIN_STEREO_LOCK_PIN 3:1 - -#define NV5070_CTRL_CMD_GET_RG_CONNECTED_LOCKPIN_PARAMS_MESSAGE_ID (0x7U) - -typedef struct NV5070_CTRL_CMD_GET_RG_CONNECTED_LOCKPIN_PARAMS { - NV5070_CTRL_CMD_BASE_PARAMS base; - NvU32 head; - - NvU32 masterScanLock; - NvU32 slaveScanLock; - NvU32 flipLock; - NvU32 stereoLock; -} NV5070_CTRL_CMD_GET_RG_CONNECTED_LOCKPIN_PARAMS; - -/* * NV5070_CTRL_CMD_SET_VIDEO_STATUS * * This command is used to set the current video playback status for use diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/common/sdk/nvidia/inc/ctrl/ctrl5070/ctrl5070seq.h nvidia-open-gpu-kernel-modules-535.161.08/src/common/sdk/nvidia/inc/ctrl/ctrl5070/ctrl5070seq.h --- nvidia-open-gpu-kernel-modules-525.147.05/src/common/sdk/nvidia/inc/ctrl/ctrl5070/ctrl5070seq.h 2023-10-25 20:22:19.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/common/sdk/nvidia/inc/ctrl/ctrl5070/ctrl5070seq.h 2024-03-05 22:15:13.000000000 +0000 @@ -27,7 +27,7 @@ // // This file was generated with FINN, an NVIDIA coding tool. -// Source file: ctrl/ctrl5070/ctrl5070seq.finn +// Source file: ctrl/ctrl5070/ctrl5070seq.finn // #include "ctrl/ctrl5070/ctrl5070base.h" diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/common/sdk/nvidia/inc/ctrl/ctrl5070/ctrl5070system.h nvidia-open-gpu-kernel-modules-535.161.08/src/common/sdk/nvidia/inc/ctrl/ctrl5070/ctrl5070system.h --- nvidia-open-gpu-kernel-modules-525.147.05/src/common/sdk/nvidia/inc/ctrl/ctrl5070/ctrl5070system.h 2023-10-25 20:22:19.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/common/sdk/nvidia/inc/ctrl/ctrl5070/ctrl5070system.h 2024-03-05 22:15:13.000000000 +0000 @@ -27,7 +27,7 @@ // // This file was generated with FINN, an NVIDIA coding tool. -// Source file: ctrl/ctrl5070/ctrl5070system.finn +// Source file: ctrl/ctrl5070/ctrl5070system.finn // #include "ctrl/ctrl5070/ctrl5070base.h" diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/common/sdk/nvidia/inc/ctrl/ctrl5070/ctrl5070verif.h nvidia-open-gpu-kernel-modules-535.161.08/src/common/sdk/nvidia/inc/ctrl/ctrl5070/ctrl5070verif.h --- nvidia-open-gpu-kernel-modules-525.147.05/src/common/sdk/nvidia/inc/ctrl/ctrl5070/ctrl5070verif.h 2023-10-25 20:22:19.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/common/sdk/nvidia/inc/ctrl/ctrl5070/ctrl5070verif.h 2024-03-05 22:15:13.000000000 +0000 @@ -27,6 +27,6 @@ // // This file was generated with FINN, an NVIDIA coding tool. -// Source file: ctrl/ctrl5070/ctrl5070verif.finn +// Source file: ctrl/ctrl5070/ctrl5070verif.finn // diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/common/sdk/nvidia/inc/ctrl/ctrl5080.h nvidia-open-gpu-kernel-modules-535.161.08/src/common/sdk/nvidia/inc/ctrl/ctrl5080.h --- nvidia-open-gpu-kernel-modules-525.147.05/src/common/sdk/nvidia/inc/ctrl/ctrl5080.h 2023-10-25 20:22:19.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/common/sdk/nvidia/inc/ctrl/ctrl5080.h 2024-03-05 22:15:13.000000000 +0000 @@ -26,7 +26,7 @@ // // This file was generated with FINN, an NVIDIA coding tool. -// Source file: ctrl/ctrl5080.finn +// Source file: ctrl/ctrl5080.finn // #include "ctrl/ctrlxxxx.h" diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/common/sdk/nvidia/inc/ctrl/ctrl83de/ctrl83debase.h nvidia-open-gpu-kernel-modules-535.161.08/src/common/sdk/nvidia/inc/ctrl/ctrl83de/ctrl83debase.h --- nvidia-open-gpu-kernel-modules-525.147.05/src/common/sdk/nvidia/inc/ctrl/ctrl83de/ctrl83debase.h 2023-10-25 20:22:20.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/common/sdk/nvidia/inc/ctrl/ctrl83de/ctrl83debase.h 2024-03-05 22:15:13.000000000 +0000 @@ -25,7 +25,7 @@ // // This file was generated with FINN, an NVIDIA coding tool. -// Source file: ctrl/ctrl83de/ctrl83debase.finn +// Source file: ctrl/ctrl83de/ctrl83debase.finn // #include "ctrl/ctrlxxxx.h" diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/common/sdk/nvidia/inc/ctrl/ctrl83de/ctrl83dedebug.h nvidia-open-gpu-kernel-modules-535.161.08/src/common/sdk/nvidia/inc/ctrl/ctrl83de/ctrl83dedebug.h --- nvidia-open-gpu-kernel-modules-525.147.05/src/common/sdk/nvidia/inc/ctrl/ctrl83de/ctrl83dedebug.h 2023-10-25 20:22:20.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/common/sdk/nvidia/inc/ctrl/ctrl83de/ctrl83dedebug.h 2024-03-05 22:15:13.000000000 +0000 @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 2006-2021 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2006-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -28,7 +28,7 @@ // // This file was generated with FINN, an NVIDIA coding tool. -// Source file: ctrl/ctrl83de/ctrl83dedebug.finn +// Source file: ctrl/ctrl83de/ctrl83dedebug.finn // #include "ctrl/ctrl83de/ctrl83debase.h" @@ -36,7 +36,48 @@ #include "ctrl/ctrl2080/ctrl2080gpu.h" +/* + * NV83DE_CTRL_CMD_SM_DEBUG_MODE_ENABLE + * + * The RmCtrl enables the debug mode for a given context. + * When enabled: + * - The program execution on a SM stops at breakpoints. + * - It allows the user to handle the RC recovery process and + * exceptions. (Yet to be supported) + * - It allows the user to suspend, resume the context. (Yet to be supported) + * + * This command accepts no parameters. + * + * Possible return values: + * NV_OK + * NV_ERR_INVALID_ARGUMENT + * NV_ERR_INVALID_OBJECT_HANDLE + * NV_ERR_INVALID_CLIENT + * NV_ERR_OBJECT_NOT_FOUND + * + */ +#define NV83DE_CTRL_CMD_SM_DEBUG_MODE_ENABLE (0x83de0301) /* finn: Evaluated from "(FINN_GT200_DEBUGGER_DEBUG_INTERFACE_ID << 8) | 0x1" */ +/* + * NV83DE_CTRL_CMD_SM_DEBUG_MODE_DISABLE + * + * The RmCtrl disables the debug mode for a given context. + * When disabled: + * - The program execution on a SM ignores the breakpoints. + * - RC recovery process and exceptions are handled in the usual way. + * - A request to suspend, resume the context will return error + * NV_ERR_INVALID_COMMAND. + * + * This command accepts no parameters. + * + * Possible return values: + * NV_OK + * NV_ERR_INVALID_ARGUMENT + * NV_ERR_INVALID_OBJECT_HANDLE + * NV_ERR_INVALID_CLIENT + * NV_ERR_OBJECT_NOT_FOUND + */ +#define NV83DE_CTRL_CMD_SM_DEBUG_MODE_DISABLE (0x83de0302) /* finn: Evaluated from "(FINN_GT200_DEBUGGER_DEBUG_INTERFACE_ID << 8) | 0x2" */ /* * NV83DE_CTRL_CMD_DEBUG_SET_MODE_MMU_DEBUG diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/common/sdk/nvidia/inc/ctrl/ctrl83de.h nvidia-open-gpu-kernel-modules-535.161.08/src/common/sdk/nvidia/inc/ctrl/ctrl83de.h --- nvidia-open-gpu-kernel-modules-525.147.05/src/common/sdk/nvidia/inc/ctrl/ctrl83de.h 2023-10-25 20:22:20.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/common/sdk/nvidia/inc/ctrl/ctrl83de.h 2024-03-05 22:15:13.000000000 +0000 @@ -25,7 +25,7 @@ // // This file was generated with FINN, an NVIDIA coding tool. -// Source file: ctrl/ctrl83de.finn +// Source file: ctrl/ctrl83de.finn // diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/common/sdk/nvidia/inc/ctrl/ctrl9010.h nvidia-open-gpu-kernel-modules-535.161.08/src/common/sdk/nvidia/inc/ctrl/ctrl9010.h --- nvidia-open-gpu-kernel-modules-525.147.05/src/common/sdk/nvidia/inc/ctrl/ctrl9010.h 2023-10-25 20:22:20.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/common/sdk/nvidia/inc/ctrl/ctrl9010.h 2024-03-05 22:15:14.000000000 +0000 @@ -27,7 +27,7 @@ // // This file was generated with FINN, an NVIDIA coding tool. -// Source file: ctrl/ctrl9010.finn +// Source file: ctrl/ctrl9010.finn // #include "ctrl/ctrlxxxx.h" diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/common/sdk/nvidia/inc/ctrl/ctrl9067.h nvidia-open-gpu-kernel-modules-535.161.08/src/common/sdk/nvidia/inc/ctrl/ctrl9067.h --- nvidia-open-gpu-kernel-modules-525.147.05/src/common/sdk/nvidia/inc/ctrl/ctrl9067.h 2023-10-25 20:22:20.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/common/sdk/nvidia/inc/ctrl/ctrl9067.h 2024-03-05 22:15:14.000000000 +0000 @@ -27,7 +27,7 @@ // // This file was generated with FINN, an NVIDIA coding tool. -// Source file: ctrl/ctrl9067.finn +// Source file: ctrl/ctrl9067.finn // #include "ctrl/ctrlxxxx.h" @@ -134,9 +134,7 @@ * */ -#define NV9067_CTRL_CMD_GET_CWD_WATERMARK (0x90670201) /* finn: Evaluated from "(FINN_FERMI_CONTEXT_SHARE_A_CWD_WATERMARK_INTERFACE_ID << 8) | 0x1" */ - -#define NV9067_CTRL_CMD_SET_CWD_WATERMARK (0x90670202) /* finn: Evaluated from "(FINN_FERMI_CONTEXT_SHARE_A_CWD_WATERMARK_INTERFACE_ID << 8) | 0x2" */ +#define NV9067_CTRL_CMD_GET_CWD_WATERMARK (0x90670201) /* finn: Evaluated from "(FINN_FERMI_CONTEXT_SHARE_A_CWD_WATERMARK_INTERFACE_ID << 8) | NV9067_CTRL_GET_CWD_WATERMARK_PARAMS_MESSAGE_ID" */ #define NV9067_CTRL_CWD_WATERMARK_VALUE_MIN 1 #define NV9067_CTRL_CWD_WATERMARK_VALUE_DEFAULT 2 @@ -146,5 +144,14 @@ NvU32 watermarkValue; } NV9067_CTRL_CWD_WATERMARK_PARAMS; +#define NV9067_CTRL_GET_CWD_WATERMARK_PARAMS_MESSAGE_ID (0x1U) + +typedef NV9067_CTRL_CWD_WATERMARK_PARAMS NV9067_CTRL_GET_CWD_WATERMARK_PARAMS; + +#define NV9067_CTRL_CMD_SET_CWD_WATERMARK (0x90670202) /* finn: Evaluated from "(FINN_FERMI_CONTEXT_SHARE_A_CWD_WATERMARK_INTERFACE_ID << 8) | NV9067_CTRL_SET_CWD_WATERMARK_PARAMS_MESSAGE_ID" */ + +#define NV9067_CTRL_SET_CWD_WATERMARK_PARAMS_MESSAGE_ID (0x2U) + +typedef NV9067_CTRL_CWD_WATERMARK_PARAMS NV9067_CTRL_SET_CWD_WATERMARK_PARAMS; /* _ctrl9067_h_ */ diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/common/sdk/nvidia/inc/ctrl/ctrl906f.h nvidia-open-gpu-kernel-modules-535.161.08/src/common/sdk/nvidia/inc/ctrl/ctrl906f.h --- nvidia-open-gpu-kernel-modules-525.147.05/src/common/sdk/nvidia/inc/ctrl/ctrl906f.h 2023-10-25 20:22:20.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/common/sdk/nvidia/inc/ctrl/ctrl906f.h 2024-03-05 22:15:14.000000000 +0000 @@ -27,7 +27,7 @@ // // This file was generated with FINN, an NVIDIA coding tool. -// Source file: ctrl/ctrl906f.finn +// Source file: ctrl/ctrl906f.finn // diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/common/sdk/nvidia/inc/ctrl/ctrl9072.h nvidia-open-gpu-kernel-modules-535.161.08/src/common/sdk/nvidia/inc/ctrl/ctrl9072.h --- nvidia-open-gpu-kernel-modules-525.147.05/src/common/sdk/nvidia/inc/ctrl/ctrl9072.h 2023-10-25 20:22:20.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/common/sdk/nvidia/inc/ctrl/ctrl9072.h 2024-03-05 22:15:14.000000000 +0000 @@ -27,7 +27,7 @@ // // This file was generated with FINN, an NVIDIA coding tool. -// Source file: ctrl/ctrl9072.finn +// Source file: ctrl/ctrl9072.finn // #include "ctrl/ctrlxxxx.h" diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/common/sdk/nvidia/inc/ctrl/ctrl9074.h nvidia-open-gpu-kernel-modules-535.161.08/src/common/sdk/nvidia/inc/ctrl/ctrl9074.h --- nvidia-open-gpu-kernel-modules-525.147.05/src/common/sdk/nvidia/inc/ctrl/ctrl9074.h 2023-10-25 20:22:20.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/common/sdk/nvidia/inc/ctrl/ctrl9074.h 2024-03-05 22:15:14.000000000 +0000 @@ -27,7 +27,7 @@ // // This file was generated with FINN, an NVIDIA coding tool. -// Source file: ctrl/ctrl9074.finn +// Source file: ctrl/ctrl9074.finn // #include "ctrl/ctrlxxxx.h" diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/common/sdk/nvidia/inc/ctrl/ctrl9096.h nvidia-open-gpu-kernel-modules-535.161.08/src/common/sdk/nvidia/inc/ctrl/ctrl9096.h --- nvidia-open-gpu-kernel-modules-525.147.05/src/common/sdk/nvidia/inc/ctrl/ctrl9096.h 2023-10-25 20:22:20.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/common/sdk/nvidia/inc/ctrl/ctrl9096.h 2024-03-05 22:15:14.000000000 +0000 @@ -27,7 +27,7 @@ // // This file was generated with FINN, an NVIDIA coding tool. -// Source file: ctrl/ctrl9096.finn +// Source file: ctrl/ctrl9096.finn // #include "ctrl/ctrlxxxx.h" diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/common/sdk/nvidia/inc/ctrl/ctrl90cc/ctrl90ccbase.h nvidia-open-gpu-kernel-modules-535.161.08/src/common/sdk/nvidia/inc/ctrl/ctrl90cc/ctrl90ccbase.h --- nvidia-open-gpu-kernel-modules-525.147.05/src/common/sdk/nvidia/inc/ctrl/ctrl90cc/ctrl90ccbase.h 2023-10-25 20:22:21.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/common/sdk/nvidia/inc/ctrl/ctrl90cc/ctrl90ccbase.h 2024-03-05 22:15:14.000000000 +0000 @@ -25,7 +25,7 @@ // // This file was generated with FINN, an NVIDIA coding tool. -// Source file: ctrl/ctrl90cc/ctrl90ccbase.finn +// Source file: ctrl/ctrl90cc/ctrl90ccbase.finn // #include "ctrl/ctrlxxxx.h" diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/common/sdk/nvidia/inc/ctrl/ctrl90cc/ctrl90cchwpm.h nvidia-open-gpu-kernel-modules-535.161.08/src/common/sdk/nvidia/inc/ctrl/ctrl90cc/ctrl90cchwpm.h --- nvidia-open-gpu-kernel-modules-525.147.05/src/common/sdk/nvidia/inc/ctrl/ctrl90cc/ctrl90cchwpm.h 2023-10-25 20:22:21.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/common/sdk/nvidia/inc/ctrl/ctrl90cc/ctrl90cchwpm.h 2024-03-05 22:15:15.000000000 +0000 @@ -27,7 +27,7 @@ // // This file was generated with FINN, an NVIDIA coding tool. -// Source file: ctrl/ctrl90cc/ctrl90cchwpm.finn +// Source file: ctrl/ctrl90cc/ctrl90cchwpm.finn // #include "ctrl/ctrl90cc/ctrl90ccbase.h" diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/common/sdk/nvidia/inc/ctrl/ctrl90cc/ctrl90ccpower.h nvidia-open-gpu-kernel-modules-535.161.08/src/common/sdk/nvidia/inc/ctrl/ctrl90cc/ctrl90ccpower.h --- nvidia-open-gpu-kernel-modules-525.147.05/src/common/sdk/nvidia/inc/ctrl/ctrl90cc/ctrl90ccpower.h 2023-10-25 20:22:21.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/common/sdk/nvidia/inc/ctrl/ctrl90cc/ctrl90ccpower.h 2024-03-05 22:15:15.000000000 +0000 @@ -27,7 +27,7 @@ // // This file was generated with FINN, an NVIDIA coding tool. -// Source file: ctrl/ctrl90cc/ctrl90ccpower.finn +// Source file: ctrl/ctrl90cc/ctrl90ccpower.finn // #include "ctrl/ctrl90cc/ctrl90ccbase.h" diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/common/sdk/nvidia/inc/ctrl/ctrl90cc.h nvidia-open-gpu-kernel-modules-535.161.08/src/common/sdk/nvidia/inc/ctrl/ctrl90cc.h --- nvidia-open-gpu-kernel-modules-525.147.05/src/common/sdk/nvidia/inc/ctrl/ctrl90cc.h 2023-10-25 20:22:21.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/common/sdk/nvidia/inc/ctrl/ctrl90cc.h 2024-03-05 22:15:14.000000000 +0000 @@ -25,7 +25,7 @@ // // This file was generated with FINN, an NVIDIA coding tool. -// Source file: ctrl/ctrl90cc.finn +// Source file: ctrl/ctrl90cc.finn // diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/common/sdk/nvidia/inc/ctrl/ctrl90cd.h nvidia-open-gpu-kernel-modules-535.161.08/src/common/sdk/nvidia/inc/ctrl/ctrl90cd.h --- nvidia-open-gpu-kernel-modules-525.147.05/src/common/sdk/nvidia/inc/ctrl/ctrl90cd.h 2023-10-25 20:22:21.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/common/sdk/nvidia/inc/ctrl/ctrl90cd.h 2024-03-05 22:15:15.000000000 +0000 @@ -27,7 +27,7 @@ // // This file was generated with FINN, an NVIDIA coding tool. -// Source file: ctrl/ctrl90cd.finn +// Source file: ctrl/ctrl90cd.finn // #include "ctrl/ctrlxxxx.h" diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/common/sdk/nvidia/inc/ctrl/ctrl90e6.h nvidia-open-gpu-kernel-modules-535.161.08/src/common/sdk/nvidia/inc/ctrl/ctrl90e6.h --- nvidia-open-gpu-kernel-modules-525.147.05/src/common/sdk/nvidia/inc/ctrl/ctrl90e6.h 2023-10-25 20:22:21.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/common/sdk/nvidia/inc/ctrl/ctrl90e6.h 2024-03-05 22:15:15.000000000 +0000 @@ -27,7 +27,7 @@ // // This file was generated with FINN, an NVIDIA coding tool. -// Source file: ctrl/ctrl90e6.finn +// Source file: ctrl/ctrl90e6.finn // #include "ctrl/ctrlxxxx.h" diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/common/sdk/nvidia/inc/ctrl/ctrl90e7.h nvidia-open-gpu-kernel-modules-535.161.08/src/common/sdk/nvidia/inc/ctrl/ctrl90e7.h --- nvidia-open-gpu-kernel-modules-525.147.05/src/common/sdk/nvidia/inc/ctrl/ctrl90e7.h 1970-01-01 00:00:00.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/common/sdk/nvidia/inc/ctrl/ctrl90e7.h 2024-03-05 22:15:15.000000000 +0000 @@ -0,0 +1,72 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2013-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#pragma once + +#include + +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: ctrl/ctrl90e7.finn +// + +#include "nvfixedtypes.h" +#include "ctrl/ctrlxxxx.h" +/* GF100_SUBDEVICE_INFOROM control commands and parameters */ + +#define NV90E7_CTRL_CMD(cat,idx) NVXXXX_CTRL_CMD(0x90E7, NV90E7_CTRL_##cat, idx) + +/* Command categories (6 bits) */ +#define NV90E7_CTRL_RESERVED (0x00) +#define NV90E7_CTRL_BBX (0x01) + + + +/* + * NV90E7_CTRL_CMD_BBX_GET_LAST_FLUSH_TIME + * + * This command is used to query the last BBX flush timestamp and duration. If BBX has not yet + * been flushed, the status returned is NV_ERR_NOT_READY. + * + * timestamp + * This parameter specifies the start timestamp of the last BBX flush. + * + * durationUs + * This parameter specifies the duration (us) of the last BBX flush. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_NOT_READY + * NV_ERR_NOT_SUPPORTED + */ +#define NV90E7_CTRL_CMD_BBX_GET_LAST_FLUSH_TIME (0x90e70113) /* finn: Evaluated from "(FINN_GF100_SUBDEVICE_INFOROM_BBX_INTERFACE_ID << 8) | NV90E7_CTRL_BBX_GET_LAST_FLUSH_TIME_PARAMS_MESSAGE_ID" */ + +#define NV90E7_CTRL_BBX_GET_LAST_FLUSH_TIME_PARAMS_MESSAGE_ID (0x13U) + +typedef struct NV90E7_CTRL_BBX_GET_LAST_FLUSH_TIME_PARAMS { + NV_DECLARE_ALIGNED(NvU64 timestamp, 8); + NvU32 durationUs; +} NV90E7_CTRL_BBX_GET_LAST_FLUSH_TIME_PARAMS; + + + diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/common/sdk/nvidia/inc/ctrl/ctrl90ec.h nvidia-open-gpu-kernel-modules-535.161.08/src/common/sdk/nvidia/inc/ctrl/ctrl90ec.h --- nvidia-open-gpu-kernel-modules-525.147.05/src/common/sdk/nvidia/inc/ctrl/ctrl90ec.h 2023-10-25 20:22:21.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/common/sdk/nvidia/inc/ctrl/ctrl90ec.h 2024-03-05 22:15:15.000000000 +0000 @@ -27,7 +27,7 @@ // // This file was generated with FINN, an NVIDIA coding tool. -// Source file: ctrl/ctrl90ec.finn +// Source file: ctrl/ctrl90ec.finn // #include "ctrl/ctrlxxxx.h" diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/common/sdk/nvidia/inc/ctrl/ctrl90f1.h nvidia-open-gpu-kernel-modules-535.161.08/src/common/sdk/nvidia/inc/ctrl/ctrl90f1.h --- nvidia-open-gpu-kernel-modules-525.147.05/src/common/sdk/nvidia/inc/ctrl/ctrl90f1.h 2023-10-25 20:22:21.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/common/sdk/nvidia/inc/ctrl/ctrl90f1.h 2024-03-05 22:15:15.000000000 +0000 @@ -27,7 +27,7 @@ // // This file was generated with FINN, an NVIDIA coding tool. -// Source file: ctrl/ctrl90f1.finn +// Source file: ctrl/ctrl90f1.finn // #include "ctrl/ctrlxxxx.h" @@ -81,7 +81,37 @@ /*! * Get VAS page level information. */ -#define NV90F1_CTRL_CMD_VASPACE_GET_PAGE_LEVEL_INFO (0x90f10102U) /* finn: Evaluated from "(FINN_FERMI_VASPACE_A_VASPACE_INTERFACE_ID << 8) | 0x2" */ +#define NV90F1_CTRL_CMD_VASPACE_GET_PAGE_LEVEL_INFO (0x90f10102U) /* finn: Evaluated from "(FINN_FERMI_VASPACE_A_VASPACE_INTERFACE_ID << 8) | NV90F1_CTRL_VASPACE_GET_PAGE_LEVEL_INFO_PARAMS_MESSAGE_ID" */ + +typedef struct NV_CTRL_VASPACE_PAGE_LEVEL { + /*! + * Format of this level. + */ + NV_DECLARE_ALIGNED(struct MMU_FMT_LEVEL *pFmt, 8); + + /*! + * Level/Sublevel Formats flattened + */ + NV_DECLARE_ALIGNED(MMU_FMT_LEVEL levelFmt, 8); + NV_DECLARE_ALIGNED(MMU_FMT_LEVEL sublevelFmt[MMU_FMT_MAX_SUB_LEVELS], 8); + + /*! + * Physical address of this page level instance. + */ + NV_DECLARE_ALIGNED(NvU64 physAddress, 8); + + /*! + * Aperture in which this page level instance resides. + */ + NvU32 aperture; + + /*! + * Size in bytes allocated for this level instance. + */ + NV_DECLARE_ALIGNED(NvU64 size, 8); +} NV_CTRL_VASPACE_PAGE_LEVEL; + +#define NV90F1_CTRL_VASPACE_GET_PAGE_LEVEL_INFO_PARAMS_MESSAGE_ID (0x2U) typedef struct NV90F1_CTRL_VASPACE_GET_PAGE_LEVEL_INFO_PARAMS { /*! @@ -113,33 +143,7 @@ /*! * [out] Per-level information. */ - struct { - /*! - * Format of this level. - */ - NV_DECLARE_ALIGNED(struct MMU_FMT_LEVEL *pFmt, 8); - - /*! - * Level/Sublevel Formats flattened - */ - NV_DECLARE_ALIGNED(MMU_FMT_LEVEL levelFmt, 8); - NV_DECLARE_ALIGNED(MMU_FMT_LEVEL sublevelFmt[MMU_FMT_MAX_SUB_LEVELS], 8); - - /*! - * Physical address of this page level instance. - */ - NV_DECLARE_ALIGNED(NvU64 physAddress, 8); - - /*! - * Aperture in which this page level instance resides. - */ - NvU32 aperture; - - /*! - * Size in bytes allocated for this level instance. - */ - NV_DECLARE_ALIGNED(NvU64 size, 8); - } levels[GMMU_FMT_MAX_LEVELS]; + NV_DECLARE_ALIGNED(NV_CTRL_VASPACE_PAGE_LEVEL levels[GMMU_FMT_MAX_LEVELS], 8); } NV90F1_CTRL_VASPACE_GET_PAGE_LEVEL_INFO_PARAMS; /*! @@ -232,7 +236,11 @@ * Get VAS page level information without kernel priviledge. This will internally call * NV90F1_CTRL_CMD_VASPACE_GET_PAGE_LEVEL_INFO. */ -#define NV90F1_CTRL_CMD_VASPACE_GET_PAGE_LEVEL_INFO_VERIF (0x90f10105U) /* finn: Evaluated from "(FINN_FERMI_VASPACE_A_VASPACE_INTERFACE_ID << 8) | 0x5" */ +#define NV90F1_CTRL_CMD_VASPACE_GET_PAGE_LEVEL_INFO_VERIF (0x90f10105U) /* finn: Evaluated from "(FINN_FERMI_VASPACE_A_VASPACE_INTERFACE_ID << 8) | NV90F1_CTRL_VASPACE_GET_PAGE_LEVEL_INFO_VERIF_PARAMS_MESSAGE_ID" */ + +#define NV90F1_CTRL_VASPACE_GET_PAGE_LEVEL_INFO_VERIF_PARAMS_MESSAGE_ID (0x5U) + +typedef NV90F1_CTRL_VASPACE_GET_PAGE_LEVEL_INFO_PARAMS NV90F1_CTRL_VASPACE_GET_PAGE_LEVEL_INFO_VERIF_PARAMS; /*! * Pin PDEs for a given VA range on the server RM and then mirror the client's page diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/common/sdk/nvidia/inc/ctrl/ctrla06c.h nvidia-open-gpu-kernel-modules-535.161.08/src/common/sdk/nvidia/inc/ctrl/ctrla06c.h --- nvidia-open-gpu-kernel-modules-525.147.05/src/common/sdk/nvidia/inc/ctrl/ctrla06c.h 2023-10-25 20:22:21.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/common/sdk/nvidia/inc/ctrl/ctrla06c.h 2024-03-05 22:15:15.000000000 +0000 @@ -27,7 +27,7 @@ // // This file was generated with FINN, an NVIDIA coding tool. -// Source file: ctrl/ctrla06c.finn +// Source file: ctrl/ctrla06c.finn // @@ -94,20 +94,11 @@ * NV_ERR_INVALID_OPERATION * */ -#define NVA06C_CTRL_CMD_GPFIFO_SCHEDULE (0xa06c0101) /* finn: Evaluated from "(FINN_KEPLER_CHANNEL_GROUP_A_GPFIFO_INTERFACE_ID << 8) | 0x1" */ -typedef NVA06F_CTRL_GPFIFO_SCHEDULE_PARAMS NVA06C_CTRL_GPFIFO_SCHEDULE_PARAMS; - -// FINN PORT: The below type was generated by the FINN port to -// ensure that all API's have a unique structure associated -// with them! -#define NVA06C_CTRL_CMD_GPFIFO_SCHEDULE_FINN_PARAMS_MESSAGE_ID (0x1U) - -typedef struct NVA06C_CTRL_CMD_GPFIFO_SCHEDULE_FINN_PARAMS { - NVA06C_CTRL_GPFIFO_SCHEDULE_PARAMS params; -} NVA06C_CTRL_CMD_GPFIFO_SCHEDULE_FINN_PARAMS; - +#define NVA06C_CTRL_CMD_GPFIFO_SCHEDULE (0xa06c0101) /* finn: Evaluated from "(FINN_KEPLER_CHANNEL_GROUP_A_GPFIFO_INTERFACE_ID << 8) | NVA06C_CTRL_GPFIFO_SCHEDULE_PARAMS_MESSAGE_ID" */ +#define NVA06C_CTRL_GPFIFO_SCHEDULE_PARAMS_MESSAGE_ID (0x1U) +typedef NVA06F_CTRL_GPFIFO_SCHEDULE_PARAMS NVA06C_CTRL_GPFIFO_SCHEDULE_PARAMS; /* * NVA06C_CTRL_CMD_BIND @@ -152,7 +143,15 @@ * NV_ERR_INVALID_ARGUMENT * NV_ERR_INVALID_STATE */ -#define NVA06C_CTRL_CMD_SET_TIMESLICE (0xa06c0103) /* finn: Evaluated from "(FINN_KEPLER_CHANNEL_GROUP_A_GPFIFO_INTERFACE_ID << 8) | 0x3" */ +#define NVA06C_CTRL_CMD_SET_TIMESLICE (0xa06c0103) /* finn: Evaluated from "(FINN_KEPLER_CHANNEL_GROUP_A_GPFIFO_INTERFACE_ID << 8) | NVA06C_CTRL_SET_TIMESLICE_PARAMS_MESSAGE_ID" */ + +typedef struct NVA06C_CTRL_TIMESLICE_PARAMS { + NV_DECLARE_ALIGNED(NvU64 timesliceUs, 8); +} NVA06C_CTRL_TIMESLICE_PARAMS; + +#define NVA06C_CTRL_SET_TIMESLICE_PARAMS_MESSAGE_ID (0x3U) + +typedef NVA06C_CTRL_TIMESLICE_PARAMS NVA06C_CTRL_SET_TIMESLICE_PARAMS; /* * NVA06C_CTRL_CMD_GET_TIMESLICE @@ -170,11 +169,11 @@ * NV_ERR_INVALID_ARGUMENT * NV_ERR_INVALID_STATE */ -#define NVA06C_CTRL_CMD_GET_TIMESLICE (0xa06c0104) /* finn: Evaluated from "(FINN_KEPLER_CHANNEL_GROUP_A_GPFIFO_INTERFACE_ID << 8) | 0x4" */ +#define NVA06C_CTRL_CMD_GET_TIMESLICE (0xa06c0104) /* finn: Evaluated from "(FINN_KEPLER_CHANNEL_GROUP_A_GPFIFO_INTERFACE_ID << 8) | NVA06C_CTRL_GET_TIMESLICE_PARAMS_MESSAGE_ID" */ -typedef struct NVA06C_CTRL_TIMESLICE_PARAMS { - NV_DECLARE_ALIGNED(NvU64 timesliceUs, 8); -} NVA06C_CTRL_TIMESLICE_PARAMS; +#define NVA06C_CTRL_GET_TIMESLICE_PARAMS_MESSAGE_ID (0x4U) + +typedef NVA06C_CTRL_TIMESLICE_PARAMS NVA06C_CTRL_GET_TIMESLICE_PARAMS; /* * NVA06C_CTRL_CMD_PREEMPT @@ -266,7 +265,19 @@ * NV_ERR_INVALID_STATE * NV_ERR_INSUFFICIENT_PERMISSIONS */ -#define NVA06C_CTRL_CMD_SET_INTERLEAVE_LEVEL (0xa06c0107) /* finn: Evaluated from "(FINN_KEPLER_CHANNEL_GROUP_A_GPFIFO_INTERFACE_ID << 8) | 0x7" */ +#define NVA06C_CTRL_CMD_SET_INTERLEAVE_LEVEL (0xa06c0107) /* finn: Evaluated from "(FINN_KEPLER_CHANNEL_GROUP_A_GPFIFO_INTERFACE_ID << 8) | NVA06C_CTRL_SET_INTERLEAVE_LEVEL_PARAMS_MESSAGE_ID" */ + +typedef struct NVA06C_CTRL_INTERLEAVE_LEVEL_PARAMS { + NvU32 tsgInterleaveLevel; +} NVA06C_CTRL_INTERLEAVE_LEVEL_PARAMS; + +#define NVA06C_CTRL_INTERLEAVE_LEVEL_LOW (0x00000000) +#define NVA06C_CTRL_INTERLEAVE_LEVEL_MEDIUM (0x00000001) +#define NVA06C_CTRL_INTERLEAVE_LEVEL_HIGH (0x00000002) + +#define NVA06C_CTRL_SET_INTERLEAVE_LEVEL_PARAMS_MESSAGE_ID (0x7U) + +typedef NVA06C_CTRL_INTERLEAVE_LEVEL_PARAMS NVA06C_CTRL_SET_INTERLEAVE_LEVEL_PARAMS; /* * NVA06C_CTRL_CMD_GET_INTERLEAVE_LEVEL @@ -284,15 +295,11 @@ * NV_ERR_INVALID_ARGUMENT * NV_ERR_INVALID_STATE */ -#define NVA06C_CTRL_CMD_GET_INTERLEAVE_LEVEL (0xa06c0108) /* finn: Evaluated from "(FINN_KEPLER_CHANNEL_GROUP_A_GPFIFO_INTERFACE_ID << 8) | 0x8" */ +#define NVA06C_CTRL_CMD_GET_INTERLEAVE_LEVEL (0xa06c0108) /* finn: Evaluated from "(FINN_KEPLER_CHANNEL_GROUP_A_GPFIFO_INTERFACE_ID << 8) | NVA06C_CTRL_GET_INTERLEAVE_LEVEL_PARAMS_MESSAGE_ID" */ -typedef struct NVA06C_CTRL_INTERLEAVE_LEVEL_PARAMS { - NvU32 tsgInterleaveLevel; -} NVA06C_CTRL_INTERLEAVE_LEVEL_PARAMS; +#define NVA06C_CTRL_GET_INTERLEAVE_LEVEL_PARAMS_MESSAGE_ID (0x8U) -#define NVA06C_CTRL_INTERLEAVE_LEVEL_LOW (0x00000000) -#define NVA06C_CTRL_INTERLEAVE_LEVEL_MEDIUM (0x00000001) -#define NVA06C_CTRL_INTERLEAVE_LEVEL_HIGH (0x00000002) +typedef NVA06C_CTRL_INTERLEAVE_LEVEL_PARAMS NVA06C_CTRL_GET_INTERLEAVE_LEVEL_PARAMS; /* * NVA06C_CTRL_CMD_PROGRAM_VIDMEM_PROMOTE @@ -404,7 +411,11 @@ * Please see description of NVA06C_CTRL_CMD_GPFIFO_SCHEDULE for more information. * */ -#define NVA06C_CTRL_CMD_INTERNAL_GPFIFO_SCHEDULE (0xa06c0201) /* finn: Evaluated from "(FINN_KEPLER_CHANNEL_GROUP_A_INTERNAL_INTERFACE_ID << 8) | 0x1" */ +#define NVA06C_CTRL_CMD_INTERNAL_GPFIFO_SCHEDULE (0xa06c0201) /* finn: Evaluated from "(FINN_KEPLER_CHANNEL_GROUP_A_INTERNAL_INTERFACE_ID << 8) | NVA06C_CTRL_INTERNAL_GPFIFO_SCHEDULE_PARAMS_MESSAGE_ID" */ + +#define NVA06C_CTRL_INTERNAL_GPFIFO_SCHEDULE_PARAMS_MESSAGE_ID (0x1U) + +typedef NVA06C_CTRL_GPFIFO_SCHEDULE_PARAMS NVA06C_CTRL_INTERNAL_GPFIFO_SCHEDULE_PARAMS; /* * NVA06C_CTRL_CMD_INTERNAL_SET_TIMESLICE @@ -415,7 +426,11 @@ * Please see description of NVA06C_CTRL_CMD_SET_TIMESLICE for more information. * */ -#define NVA06C_CTRL_CMD_INTERNAL_SET_TIMESLICE (0xa06c0202) /* finn: Evaluated from "(FINN_KEPLER_CHANNEL_GROUP_A_INTERNAL_INTERFACE_ID << 8) | 0x2" */ +#define NVA06C_CTRL_CMD_INTERNAL_SET_TIMESLICE (0xa06c0202) /* finn: Evaluated from "(FINN_KEPLER_CHANNEL_GROUP_A_INTERNAL_INTERFACE_ID << 8) | NVA06C_CTRL_INTERNAL_SET_TIMESLICE_PARAMS_MESSAGE_ID" */ + +#define NVA06C_CTRL_INTERNAL_SET_TIMESLICE_PARAMS_MESSAGE_ID (0x2U) + +typedef NVA06C_CTRL_TIMESLICE_PARAMS NVA06C_CTRL_INTERNAL_SET_TIMESLICE_PARAMS; /* _ctrla06c.h_ */ diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/common/sdk/nvidia/inc/ctrl/ctrla06f/ctrla06fbase.h nvidia-open-gpu-kernel-modules-535.161.08/src/common/sdk/nvidia/inc/ctrl/ctrla06f/ctrla06fbase.h --- nvidia-open-gpu-kernel-modules-525.147.05/src/common/sdk/nvidia/inc/ctrl/ctrla06f/ctrla06fbase.h 2023-10-25 20:22:22.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/common/sdk/nvidia/inc/ctrl/ctrla06f/ctrla06fbase.h 2024-03-05 22:15:16.000000000 +0000 @@ -25,7 +25,7 @@ // // This file was generated with FINN, an NVIDIA coding tool. -// Source file: ctrl/ctrla06f/ctrla06fbase.finn +// Source file: ctrl/ctrla06f/ctrla06fbase.finn // diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/common/sdk/nvidia/inc/ctrl/ctrla06f/ctrla06fevent.h nvidia-open-gpu-kernel-modules-535.161.08/src/common/sdk/nvidia/inc/ctrl/ctrla06f/ctrla06fevent.h --- nvidia-open-gpu-kernel-modules-525.147.05/src/common/sdk/nvidia/inc/ctrl/ctrla06f/ctrla06fevent.h 2023-10-25 20:22:22.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/common/sdk/nvidia/inc/ctrl/ctrla06f/ctrla06fevent.h 2024-03-05 22:15:16.000000000 +0000 @@ -27,7 +27,7 @@ // // This file was generated with FINN, an NVIDIA coding tool. -// Source file: ctrl/ctrla06f/ctrla06fevent.finn +// Source file: ctrl/ctrla06f/ctrla06fevent.finn // #include "ctrl/ctrla06f/ctrla06fbase.h" diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/common/sdk/nvidia/inc/ctrl/ctrla06f/ctrla06fgpfifo.h nvidia-open-gpu-kernel-modules-535.161.08/src/common/sdk/nvidia/inc/ctrl/ctrla06f/ctrla06fgpfifo.h --- nvidia-open-gpu-kernel-modules-525.147.05/src/common/sdk/nvidia/inc/ctrl/ctrla06f/ctrla06fgpfifo.h 2023-10-25 20:22:22.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/common/sdk/nvidia/inc/ctrl/ctrla06f/ctrla06fgpfifo.h 2024-03-05 22:15:16.000000000 +0000 @@ -27,7 +27,7 @@ // // This file was generated with FINN, an NVIDIA coding tool. -// Source file: ctrl/ctrla06f/ctrla06fgpfifo.finn +// Source file: ctrl/ctrla06f/ctrla06fgpfifo.finn // #include "ctrl/ctrla06f/ctrla06fbase.h" @@ -38,40 +38,22 @@ * Please see description of NV906F_CTRL_GET_CLASS_ENGINEID for more information. * */ -#define NVA06F_CTRL_GET_CLASS_ENGINEID (0xa06f0101) /* finn: Evaluated from "(FINN_KEPLER_CHANNEL_GPFIFO_A_GPFIFO_INTERFACE_ID << 8) | 0x1" */ - -typedef NV906F_CTRL_GET_CLASS_ENGINEID_PARAMS NVA06F_CTRL_GET_CLASS_ENGINEID_PARAMS; - -// FINN PORT: The below type was generated by the FINN port to -// ensure that all API's have a unique structure associated -// with them! -#define NVA06F_CTRL_GET_CLASS_ENGINEID_FINN_PARAMS_MESSAGE_ID (0x1U) - -typedef struct NVA06F_CTRL_GET_CLASS_ENGINEID_FINN_PARAMS { - NVA06F_CTRL_GET_CLASS_ENGINEID_PARAMS params; -} NVA06F_CTRL_GET_CLASS_ENGINEID_FINN_PARAMS; +#define NVA06F_CTRL_GET_CLASS_ENGINEID (0xa06f0101) /* finn: Evaluated from "(FINN_KEPLER_CHANNEL_GPFIFO_A_GPFIFO_INTERFACE_ID << 8) | NVA06F_CTRL_GET_CLASS_ENGINEID_PARAMS_MESSAGE_ID" */ +#define NVA06F_CTRL_GET_CLASS_ENGINEID_PARAMS_MESSAGE_ID (0x1U) +typedef NV906F_CTRL_GET_CLASS_ENGINEID_PARAMS NVA06F_CTRL_GET_CLASS_ENGINEID_PARAMS; /* * NVA06F_CTRL_RESET_CHANNEL * * Please see description of NV906F_CTRL_RESET_CHANNEL for more information. */ -#define NVA06F_CTRL_CMD_RESET_CHANNEL (0xa06f0102) /* finn: Evaluated from "(FINN_KEPLER_CHANNEL_GPFIFO_A_GPFIFO_INTERFACE_ID << 8) | 0x2" */ - -typedef NV906F_CTRL_CMD_RESET_CHANNEL_PARAMS NVA06F_CTRL_CMD_RESET_CHANNEL_PARAMS; - -// FINN PORT: The below type was generated by the FINN port to -// ensure that all API's have a unique structure associated -// with them! -#define NVA06F_CTRL_CMD_RESET_CHANNEL_FINN_PARAMS_MESSAGE_ID (0x2U) - -typedef struct NVA06F_CTRL_CMD_RESET_CHANNEL_FINN_PARAMS { - NVA06F_CTRL_CMD_RESET_CHANNEL_PARAMS params; -} NVA06F_CTRL_CMD_RESET_CHANNEL_FINN_PARAMS; +#define NVA06F_CTRL_CMD_RESET_CHANNEL (0xa06f0102) /* finn: Evaluated from "(FINN_KEPLER_CHANNEL_GPFIFO_A_GPFIFO_INTERFACE_ID << 8) | NVA06F_CTRL_CMD_RESET_CHANNEL_PARAMS_MESSAGE_ID" */ +#define NVA06F_CTRL_CMD_RESET_CHANNEL_PARAMS_MESSAGE_ID (0x2U) +typedef NV906F_CTRL_CMD_RESET_CHANNEL_PARAMS NVA06F_CTRL_CMD_RESET_CHANNEL_PARAMS; /* * NVA06F_CTRL_CMD_GPFIFO_SCHEDULE @@ -137,20 +119,11 @@ * Please see description of NV906F_CTRL_CMD_GET_MMU_FAULT_INFO for more information. * */ -#define NVA06F_CTRL_CMD_GET_MMU_FAULT_INFO (0xa06f0107) /* finn: Evaluated from "(FINN_KEPLER_CHANNEL_GPFIFO_A_GPFIFO_INTERFACE_ID << 8) | 0x7" */ - -typedef NV906F_CTRL_GET_MMU_FAULT_INFO_PARAMS NVA06F_CTRL_GET_MMU_FAULT_INFO_PARAMS; - -// FINN PORT: The below type was generated by the FINN port to -// ensure that all API's have a unique structure associated -// with them! -#define NVA06F_CTRL_CMD_GET_MMU_FAULT_INFO_FINN_PARAMS_MESSAGE_ID (0x7U) - -typedef struct NVA06F_CTRL_CMD_GET_MMU_FAULT_INFO_FINN_PARAMS { - NV_DECLARE_ALIGNED(NVA06F_CTRL_GET_MMU_FAULT_INFO_PARAMS params, 8); -} NVA06F_CTRL_CMD_GET_MMU_FAULT_INFO_FINN_PARAMS; +#define NVA06F_CTRL_CMD_GET_MMU_FAULT_INFO (0xa06f0107) /* finn: Evaluated from "(FINN_KEPLER_CHANNEL_GPFIFO_A_GPFIFO_INTERFACE_ID << 8) | NVA06F_CTRL_GET_MMU_FAULT_INFO_PARAMS_MESSAGE_ID" */ +#define NVA06F_CTRL_GET_MMU_FAULT_INFO_PARAMS_MESSAGE_ID (0x7U) +typedef NV906F_CTRL_GET_MMU_FAULT_INFO_PARAMS NVA06F_CTRL_GET_MMU_FAULT_INFO_PARAMS; /* * NVA06F_CTRL_CMD_SET_ERROR_NOTIFIER @@ -192,7 +165,15 @@ * NV_ERR_INVALID_STATE * NV_ERR_INSUFFICIENT_PERMISSIONS */ -#define NVA06F_CTRL_CMD_SET_INTERLEAVE_LEVEL (0xa06f0109) /* finn: Evaluated from "(FINN_KEPLER_CHANNEL_GPFIFO_A_GPFIFO_INTERFACE_ID << 8) | 0x9" */ +#define NVA06F_CTRL_CMD_SET_INTERLEAVE_LEVEL (0xa06f0109) /* finn: Evaluated from "(FINN_KEPLER_CHANNEL_GPFIFO_A_GPFIFO_INTERFACE_ID << 8) | NVA06F_CTRL_SET_INTERLEAVE_LEVEL_PARAMS_MESSAGE_ID" */ + +typedef struct NVA06F_CTRL_INTERLEAVE_LEVEL_PARAMS { + NvU32 channelInterleaveLevel; +} NVA06F_CTRL_INTERLEAVE_LEVEL_PARAMS; + +#define NVA06F_CTRL_SET_INTERLEAVE_LEVEL_PARAMS_MESSAGE_ID (0x9U) + +typedef NVA06F_CTRL_INTERLEAVE_LEVEL_PARAMS NVA06F_CTRL_SET_INTERLEAVE_LEVEL_PARAMS; /* * NVA06F_CTRL_CMD_GET_INTERLEAVE_LEVEL @@ -210,11 +191,11 @@ * NV_ERR_INVALID_ARGUMENT * NV_ERR_INVALID_STATE */ -#define NVA06F_CTRL_CMD_GET_INTERLEAVE_LEVEL (0xa06f0110) /* finn: Evaluated from "(FINN_KEPLER_CHANNEL_GPFIFO_A_GPFIFO_INTERFACE_ID << 8) | 0x10" */ +#define NVA06F_CTRL_CMD_GET_INTERLEAVE_LEVEL (0xa06f0110) /* finn: Evaluated from "(FINN_KEPLER_CHANNEL_GPFIFO_A_GPFIFO_INTERFACE_ID << 8) | NVA06F_CTRL_GET_INTERLEAVE_LEVEL_PARAMS_MESSAGE_ID" */ -typedef struct NVA06F_CTRL_INTERLEAVE_LEVEL_PARAMS { - NvU32 channelInterleaveLevel; -} NVA06F_CTRL_INTERLEAVE_LEVEL_PARAMS; +#define NVA06F_CTRL_GET_INTERLEAVE_LEVEL_PARAMS_MESSAGE_ID (0x10U) + +typedef NVA06F_CTRL_INTERLEAVE_LEVEL_PARAMS NVA06F_CTRL_GET_INTERLEAVE_LEVEL_PARAMS; /* * NVA06F_CTRL_CMD_RESTART_RUNLIST diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/common/sdk/nvidia/inc/ctrl/ctrla06f/ctrla06finternal.h nvidia-open-gpu-kernel-modules-535.161.08/src/common/sdk/nvidia/inc/ctrl/ctrla06f/ctrla06finternal.h --- nvidia-open-gpu-kernel-modules-525.147.05/src/common/sdk/nvidia/inc/ctrl/ctrla06f/ctrla06finternal.h 2023-10-25 20:22:22.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/common/sdk/nvidia/inc/ctrl/ctrla06f/ctrla06finternal.h 2024-03-05 22:15:16.000000000 +0000 @@ -25,7 +25,7 @@ // // This file was generated with FINN, an NVIDIA coding tool. -// Source file: ctrl/ctrla06f/ctrla06finternal.finn +// Source file: ctrl/ctrla06f/ctrla06finternal.finn // #include "ctrl/ctrla06f/ctrla06fbase.h" @@ -40,7 +40,11 @@ * Please see description of NVA06F_CTRL_CMD_STOP_CHANNEL for more information. * */ -#define NVA06F_CTRL_CMD_INTERNAL_STOP_CHANNEL (0xa06f0301) /* finn: Evaluated from "(FINN_KEPLER_CHANNEL_GPFIFO_A_INTERNAL_INTERFACE_ID << 8) | 0x1" */ +#define NVA06F_CTRL_CMD_INTERNAL_STOP_CHANNEL (0xa06f0301) /* finn: Evaluated from "(FINN_KEPLER_CHANNEL_GPFIFO_A_INTERNAL_INTERFACE_ID << 8) | NVA06F_CTRL_INTERNAL_STOP_CHANNEL_PARAMS_MESSAGE_ID" */ + +#define NVA06F_CTRL_INTERNAL_STOP_CHANNEL_PARAMS_MESSAGE_ID (0x1U) + +typedef NVA06F_CTRL_STOP_CHANNEL_PARAMS NVA06F_CTRL_INTERNAL_STOP_CHANNEL_PARAMS; /* * NVA06F_CTRL_CMD_INTERNAL_RESET_CHANNEL @@ -51,7 +55,11 @@ * Please see description of NV906F_CTRL_CMD_RESET_CHANNEL for more information. * */ -#define NVA06F_CTRL_CMD_INTERNAL_RESET_CHANNEL (0xa06f0302) /* finn: Evaluated from "(FINN_KEPLER_CHANNEL_GPFIFO_A_INTERNAL_INTERFACE_ID << 8) | 0x2" */ +#define NVA06F_CTRL_CMD_INTERNAL_RESET_CHANNEL (0xa06f0302) /* finn: Evaluated from "(FINN_KEPLER_CHANNEL_GPFIFO_A_INTERNAL_INTERFACE_ID << 8) | NVA06F_CTRL_INTERNAL_RESET_CHANNEL_PARAMS_MESSAGE_ID" */ + +#define NVA06F_CTRL_INTERNAL_RESET_CHANNEL_PARAMS_MESSAGE_ID (0x2U) + +typedef NVA06F_CTRL_CMD_RESET_CHANNEL_PARAMS NVA06F_CTRL_INTERNAL_RESET_CHANNEL_PARAMS; /* * NVA06F_CTRL_CMD_INTERNAL_GPFIFO_SCHEDULE @@ -62,6 +70,10 @@ * Please see description of NVA06F_CTRL_CMD_GPFIFO_SCHEDULE for more information. * */ -#define NVA06F_CTRL_CMD_INTERNAL_GPFIFO_SCHEDULE (0xa06f0303) /* finn: Evaluated from "(FINN_KEPLER_CHANNEL_GPFIFO_A_INTERNAL_INTERFACE_ID << 8) | 0x3" */ +#define NVA06F_CTRL_CMD_INTERNAL_GPFIFO_SCHEDULE (0xa06f0303) /* finn: Evaluated from "(FINN_KEPLER_CHANNEL_GPFIFO_A_INTERNAL_INTERFACE_ID << 8) | NVA06F_CTRL_INTERNAL_GPFIFO_SCHEDULE_PARAMS_MESSAGE_ID" */ + +#define NVA06F_CTRL_INTERNAL_GPFIFO_SCHEDULE_PARAMS_MESSAGE_ID (0x3U) + +typedef NVA06F_CTRL_GPFIFO_SCHEDULE_PARAMS NVA06F_CTRL_INTERNAL_GPFIFO_SCHEDULE_PARAMS; /* ctrla06finternal_h */ diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/common/sdk/nvidia/inc/ctrl/ctrla06f.h nvidia-open-gpu-kernel-modules-535.161.08/src/common/sdk/nvidia/inc/ctrl/ctrla06f.h --- nvidia-open-gpu-kernel-modules-525.147.05/src/common/sdk/nvidia/inc/ctrl/ctrla06f.h 2023-10-25 20:22:21.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/common/sdk/nvidia/inc/ctrl/ctrla06f.h 2024-03-05 22:15:15.000000000 +0000 @@ -25,7 +25,7 @@ // // This file was generated with FINN, an NVIDIA coding tool. -// Source file: ctrl/ctrla06f.finn +// Source file: ctrl/ctrla06f.finn // diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/common/sdk/nvidia/inc/ctrl/ctrla080.h nvidia-open-gpu-kernel-modules-535.161.08/src/common/sdk/nvidia/inc/ctrl/ctrla080.h --- nvidia-open-gpu-kernel-modules-525.147.05/src/common/sdk/nvidia/inc/ctrl/ctrla080.h 2023-10-25 20:22:22.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/common/sdk/nvidia/inc/ctrl/ctrla080.h 2024-03-05 22:15:16.000000000 +0000 @@ -28,7 +28,7 @@ // // This file was generated with FINN, an NVIDIA coding tool. -// Source file: ctrl/ctrla080.finn +// Source file: ctrl/ctrla080.finn // @@ -280,15 +280,19 @@ * */ -#define NVA080_CTRL_CMD_MAP_SEMA_MEM (0xa0800202) /* finn: Evaluated from "(FINN_KEPLER_DEVICE_VGPU_VGPU_MEMORY_INTERFACE_ID << 8) | 0x2" */ +#define NVA080_CTRL_CMD_MAP_SEMA_MEM (0xa0800202) /* finn: Evaluated from "(FINN_KEPLER_DEVICE_VGPU_VGPU_MEMORY_INTERFACE_ID << 8) | NVA080_CTRL_MAP_SEMA_MEM_PARAMS_MESSAGE_ID" */ -typedef struct NVA080_CTRL_MAP_SEMA_MEM_PARAMS { +typedef struct NVA080_CTRL_SEMA_MEM_PARAMS { NvHandle hClient; NvHandle hDevice; NvHandle hMemory; NvHandle hCtxDma; NV_DECLARE_ALIGNED(NvU64 semaAddress, 8); -} NVA080_CTRL_MAP_SEMA_MEM_PARAMS; +} NVA080_CTRL_SEMA_MEM_PARAMS; + +#define NVA080_CTRL_MAP_SEMA_MEM_PARAMS_MESSAGE_ID (0x2U) + +typedef NVA080_CTRL_SEMA_MEM_PARAMS NVA080_CTRL_MAP_SEMA_MEM_PARAMS; /* * NVA080_CTRL_CMD_UNMAP_SEMA_MEM @@ -308,7 +312,11 @@ * */ -#define NVA080_CTRL_CMD_UNMAP_SEMA_MEM (0xa0800203) /* finn: Evaluated from "(FINN_KEPLER_DEVICE_VGPU_VGPU_MEMORY_INTERFACE_ID << 8) | 0x3" */ +#define NVA080_CTRL_CMD_UNMAP_SEMA_MEM (0xa0800203) /* finn: Evaluated from "(FINN_KEPLER_DEVICE_VGPU_VGPU_MEMORY_INTERFACE_ID << 8) | NVA080_CTRL_UNMAP_SEMA_MEM_PARAMS_MESSAGE_ID" */ + +#define NVA080_CTRL_UNMAP_SEMA_MEM_PARAMS_MESSAGE_ID (0x3U) + +typedef NVA080_CTRL_SEMA_MEM_PARAMS NVA080_CTRL_UNMAP_SEMA_MEM_PARAMS; /*! * NVA080_CTRL_CMD_SET_FB_USAGE @@ -322,7 +330,7 @@ * Possible status values returned are: * NV_OK */ -#define NVA080_CTRL_CMD_SET_FB_USAGE (0xa0800204) /* finn: Evaluated from "(FINN_KEPLER_DEVICE_VGPU_VGPU_MEMORY_INTERFACE_ID << 8) | NVA080_CTRL_SET_FB_USAGE_PARAMS_MESSAGE_ID" */ +#define NVA080_CTRL_CMD_SET_FB_USAGE (0xa0800204) /* finn: Evaluated from "(FINN_KEPLER_DEVICE_VGPU_VGPU_MEMORY_INTERFACE_ID << 8) | NVA080_CTRL_SET_FB_USAGE_PARAMS_MESSAGE_ID" */ #define NVA080_CTRL_SET_FB_USAGE_PARAMS_MESSAGE_ID (0x4U) @@ -364,16 +372,18 @@ #define NVA080_CTRL_CMD_MAP_PER_ENGINE_SEMA_MEM (0xa0800205) /* finn: Evaluated from "(FINN_KEPLER_DEVICE_VGPU_VGPU_MEMORY_INTERFACE_ID << 8) | NVA080_CTRL_MAP_PER_ENGINE_SEMA_MEM_PARAMS_MESSAGE_ID" */ -#define NVA080_CTRL_MAP_PER_ENGINE_SEMA_MEM_PARAMS_MESSAGE_ID (0x5U) - -typedef struct NVA080_CTRL_MAP_PER_ENGINE_SEMA_MEM_PARAMS { +typedef struct NVA080_CTRL_PER_ENGINE_SEMA_MEM_PARAMS { NvU32 hClient; NvU32 hDevice; NvHandle hMemory; NvU32 hCtxDma; NV_DECLARE_ALIGNED(NvU64 semaAddress, 8); NvU32 semaStride; -} NVA080_CTRL_MAP_PER_ENGINE_SEMA_MEM_PARAMS; +} NVA080_CTRL_PER_ENGINE_SEMA_MEM_PARAMS; + +#define NVA080_CTRL_MAP_PER_ENGINE_SEMA_MEM_PARAMS_MESSAGE_ID (0x5U) + +typedef NVA080_CTRL_PER_ENGINE_SEMA_MEM_PARAMS NVA080_CTRL_MAP_PER_ENGINE_SEMA_MEM_PARAMS; /*! * NVA080_CTRL_CMD_UNMAP_PER_ENGINE_SEMA_MEM @@ -392,7 +402,7 @@ #define NVA080_CTRL_UNMAP_PER_ENGINE_SEMA_MEM_PARAMS_MESSAGE_ID (0x6U) -typedef NVA080_CTRL_MAP_PER_ENGINE_SEMA_MEM_PARAMS NVA080_CTRL_UNMAP_PER_ENGINE_SEMA_MEM_PARAMS; +typedef NVA080_CTRL_PER_ENGINE_SEMA_MEM_PARAMS NVA080_CTRL_UNMAP_PER_ENGINE_SEMA_MEM_PARAMS; /* * NVA080_CTRL_CMD_UPDATE_SYSMEM_BITMAP @@ -633,6 +643,9 @@ #define NVA080_CTRL_CMD_VGPU_GET_CONFIG_PARAMS_VGPU_DEV_CAPS_GUEST_HIBERNATION_ENABLED 22:22 #define NVA080_CTRL_CMD_VGPU_GET_CONFIG_PARAMS_VGPU_DEV_CAPS_GUEST_HIBERNATION_ENABLED_FALSE (0x00000000) #define NVA080_CTRL_CMD_VGPU_GET_CONFIG_PARAMS_VGPU_DEV_CAPS_GUEST_HIBERNATION_ENABLED_TRUE (0x00000001) +#define NVA080_CTRL_CMD_VGPU_GET_CONFIG_PARAMS_VGPU_DEV_CAPS_VF_INVALIDATE_TLB_TRAP_ENABLED 23:23 +#define NVA080_CTRL_CMD_VGPU_GET_CONFIG_PARAMS_VGPU_DEV_CAPS_VF_INVALIDATE_TLB_TRAP_ENABLED_FALSE (0x00000000) +#define NVA080_CTRL_CMD_VGPU_GET_CONFIG_PARAMS_VGPU_DEV_CAPS_VF_INVALIDATE_TLB_TRAP_ENABLED_TRUE (0x00000001) /* UVM supported features */ #define NVA080_CTRL_CMD_VGPU_GET_CONFIG_PARAMS_UVM_FEATURES_REPLAYABLE_FAULTS_ENABLED 0:0 diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/common/sdk/nvidia/inc/ctrl/ctrla081.h nvidia-open-gpu-kernel-modules-535.161.08/src/common/sdk/nvidia/inc/ctrl/ctrla081.h --- nvidia-open-gpu-kernel-modules-525.147.05/src/common/sdk/nvidia/inc/ctrl/ctrla081.h 2023-10-25 20:22:22.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/common/sdk/nvidia/inc/ctrl/ctrla081.h 2024-03-05 22:15:16.000000000 +0000 @@ -27,7 +27,7 @@ // // This file was generated with FINN, an NVIDIA coding tool. -// Source file: ctrl/ctrla081.finn +// Source file: ctrl/ctrla081.finn // #include "ctrl/ctrlxxxx.h" @@ -349,7 +349,11 @@ * NV_ERR_NOT_SUPPORTED */ -#define NVA081_CTRL_CMD_VGPU_CONFIG_GET_SUPPORTED_VGPU_TYPES (0xa0810104) /* finn: Evaluated from "(FINN_NVA081_VGPU_CONFIG_VGPU_CONFIG_INTERFACE_ID << 8) | 0x4" */ +#define NVA081_CTRL_CMD_VGPU_CONFIG_GET_SUPPORTED_VGPU_TYPES (0xa0810104) /* finn: Evaluated from "(FINN_NVA081_VGPU_CONFIG_VGPU_CONFIG_INTERFACE_ID << 8) | NVA081_CTRL_VGPU_CONFIG_GET_SUPPORTED_VGPU_TYPES_PARAMS_MESSAGE_ID" */ + +#define NVA081_CTRL_VGPU_CONFIG_GET_SUPPORTED_VGPU_TYPES_PARAMS_MESSAGE_ID (0x4U) + +typedef NVA081_CTRL_VGPU_CONFIG_GET_VGPU_TYPES_PARAMS NVA081_CTRL_VGPU_CONFIG_GET_SUPPORTED_VGPU_TYPES_PARAMS; /* * NVA081_CTRL_CMD_VGPU_CONFIG_GET_CREATABLE_VGPU_TYPES @@ -370,7 +374,11 @@ * NV_ERR_NOT_SUPPORTED */ -#define NVA081_CTRL_CMD_VGPU_CONFIG_GET_CREATABLE_VGPU_TYPES (0xa0810105) /* finn: Evaluated from "(FINN_NVA081_VGPU_CONFIG_VGPU_CONFIG_INTERFACE_ID << 8) | 0x5" */ +#define NVA081_CTRL_CMD_VGPU_CONFIG_GET_CREATABLE_VGPU_TYPES (0xa0810105) /* finn: Evaluated from "(FINN_NVA081_VGPU_CONFIG_VGPU_CONFIG_INTERFACE_ID << 8) | NVA081_CTRL_VGPU_CONFIG_GET_CREATABLE_VGPU_TYPES_PARAMS_MESSAGE_ID" */ + +#define NVA081_CTRL_VGPU_CONFIG_GET_CREATABLE_VGPU_TYPES_PARAMS_MESSAGE_ID (0x5U) + +typedef NVA081_CTRL_VGPU_CONFIG_GET_VGPU_TYPES_PARAMS NVA081_CTRL_VGPU_CONFIG_GET_CREATABLE_VGPU_TYPES_PARAMS; /* * NVA081_CTRL_CMD_VGPU_CONFIG_EVENT_SET_NOTIFICATION @@ -403,7 +411,7 @@ * NV_ERR_INVALID_ARGUMENT * NV_ERR_INVALID_STATE */ -#define NVA081_CTRL_CMD_VGPU_CONFIG_EVENT_SET_NOTIFICATION (0xa0810106) /* finn: Evaluated from "(FINN_NVA081_VGPU_CONFIG_VGPU_CONFIG_INTERFACE_ID << 8) | NVA081_CTRL_VGPU_CONFIG_EVENT_SET_NOTIFICATION_PARAMS_MESSAGE_ID" */ +#define NVA081_CTRL_CMD_VGPU_CONFIG_EVENT_SET_NOTIFICATION (0xa0810106) /* finn: Evaluated from "(FINN_NVA081_VGPU_CONFIG_VGPU_CONFIG_INTERFACE_ID << 8) | NVA081_CTRL_VGPU_CONFIG_EVENT_SET_NOTIFICATION_PARAMS_MESSAGE_ID" */ #define NVA081_CTRL_VGPU_CONFIG_EVENT_SET_NOTIFICATION_PARAMS_MESSAGE_ID (0x6U) @@ -713,4 +721,30 @@ NvU32 fractionalMultiVgpu; } NVA081_CTRL_VGPU_CONFIG_SET_PGPU_INFO_PARAMS; +/* + * NVA081_CTRL_CMD_VGPU_CONFIG_VALIDATE_SWIZZID + * + * This command is used to vallidate input swizzid from RM + * + * vgpuTypeId [IN] + * This param specifies the Type ID for VGPU profile + * + * swizzId [IN] + * This param specifies the GPU Instance ID or Swizz ID + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_REQUEST + * NV_ERR_INVALID_STATE + * NV_ERR_INVALID_ARGUMENT + */ +#define NVA081_CTRL_CMD_VGPU_CONFIG_VALIDATE_SWIZZID (0xa081011a) /* finn: Evaluated from "(FINN_NVA081_VGPU_CONFIG_VGPU_CONFIG_INTERFACE_ID << 8) | NVA081_CTRL_VGPU_CONFIG_VALIDATE_SWIZZID_PARAMS_MESSAGE_ID" */ + +#define NVA081_CTRL_VGPU_CONFIG_VALIDATE_SWIZZID_PARAMS_MESSAGE_ID (0x1aU) + +typedef struct NVA081_CTRL_VGPU_CONFIG_VALIDATE_SWIZZID_PARAMS { + NvU32 vgpuTypeId; + NvU32 swizzId; +} NVA081_CTRL_VGPU_CONFIG_VALIDATE_SWIZZID_PARAMS; + /* _ctrlA081vgpuconfig_h_ */ diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/common/sdk/nvidia/inc/ctrl/ctrla084.h nvidia-open-gpu-kernel-modules-535.161.08/src/common/sdk/nvidia/inc/ctrl/ctrla084.h --- nvidia-open-gpu-kernel-modules-525.147.05/src/common/sdk/nvidia/inc/ctrl/ctrla084.h 2023-10-25 20:22:22.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/common/sdk/nvidia/inc/ctrl/ctrla084.h 2024-03-05 22:15:16.000000000 +0000 @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 2021-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2021-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -27,10 +27,9 @@ // // This file was generated with FINN, an NVIDIA coding tool. -// Source file: ctrl/ctrla084.finn +// Source file: ctrl/ctrla084.finn // -#include "nv_vgpu_types.h" #include "ctrl/ctrlxxxx.h" #include "ctrl/ctrl2080/ctrl2080gpu.h" // NV2080_GPU_MAX_GID_LENGTH #include "ctrl/ctrl2080/ctrl2080fb.h" // NV2080_CTRL_FB_OFFLINED_PAGES_MAX_PAGES @@ -63,8 +62,7 @@ #define NVA084_CTRL_KERNEL_HOST_VGPU_DEVICE_SET_VGPU_DEVICE_INFO_PARAMS_MESSAGE_ID (0x1U) typedef struct NVA084_CTRL_KERNEL_HOST_VGPU_DEVICE_SET_VGPU_DEVICE_INFO_PARAMS { - NvU8 vgpuUuid[NV2080_GPU_MAX_GID_LENGTH]; - NvU32 vgpuDeviceInstanceId; + NvU8 vgpuUuid[NV2080_GPU_MAX_GID_LENGTH]; } NVA084_CTRL_KERNEL_HOST_VGPU_DEVICE_SET_VGPU_DEVICE_INFO_PARAMS; /* NVA084_CTRL_CMD_KERNEL_HOST_VGPU_DEVICE_SET_VGPU_GUEST_LIFE_CYCLE_STATE @@ -238,65 +236,52 @@ NvBool bNotifyState; } NVA084_CTRL_KERNEL_HOST_VGPU_DEVICE_EVENT_SET_NOTIFICATION_PARAMS; -/* NVA084_CTRL_CMD_KERNEL_HOST_VGPU_DEVICE_SET_SRIOV_STATE +/* NVA084_CTRL_CMD_KERNEL_HOST_VGPU_DEVICE_GER_BAR_MAPPING_RANGES * - * This command is used to set SRIOV state parameters in RM. + * This command is used to get Bar mapping ranges in RM. * * Parameters: + * offsets [OUT] + * Offsets of the ranges + * sizes [OUT] + * Sizes of the ranges + * mitigated [OUT] + * Specifies whether it's mitigated range + * numRanges [OUT] + * Number of ranges * - * numPluginChannels [IN] - * Number of channels required by plugin + * osPageSize [IN] + * Page size. * * Possible status values returned are: * NV_OK - * NV_ERR_INVALID_ARGUMENT + * NV_ERR_INVALID_STATE */ -#define NVA084_CTRL_CMD_KERNEL_HOST_VGPU_DEVICE_SET_SRIOV_STATE (0xa0840108) /* finn: Evaluated from "(FINN_NVA084_KERNEL_HOST_VGPU_DEVICE_KERNEL_HOST_VGPU_DEVICE_INTERFACE_ID << 8) | NVA084_CTRL_KERNEL_HOST_VGPU_DEVICE_SET_SRIOV_STATE_PARAMS_MESSAGE_ID" */ +#define NVA084_CTRL_CMD_KERNEL_HOST_VGPU_DEVICE_GET_BAR_MAPPING_RANGES (0xa084010a) /* finn: Evaluated from "(FINN_NVA084_KERNEL_HOST_VGPU_DEVICE_KERNEL_HOST_VGPU_DEVICE_INTERFACE_ID << 8) | NVA084_CTRL_KERNEL_HOST_VGPU_DEVICE_GET_BAR_MAPPING_RANGES_PARAMS_MESSAGE_ID" */ -#define NVA084_CTRL_KERNEL_HOST_VGPU_DEVICE_SET_SRIOV_STATE_MAX_PLUGIN_CHANNELS 5 +#define NVA084_CTRL_KERNEL_HOST_VGPU_DEVICE_MAX_BAR_MAPPING_RANGES 10 -#define NVA084_CTRL_KERNEL_HOST_VGPU_DEVICE_SET_SRIOV_STATE_PARAMS_MESSAGE_ID (0x8U) +#define NVA084_CTRL_KERNEL_HOST_VGPU_DEVICE_GET_BAR_MAPPING_RANGES_PARAMS_MESSAGE_ID (0xAU) -typedef struct NVA084_CTRL_KERNEL_HOST_VGPU_DEVICE_SET_SRIOV_STATE_PARAMS { - NvU32 numPluginChannels; -} NVA084_CTRL_KERNEL_HOST_VGPU_DEVICE_SET_SRIOV_STATE_PARAMS; +typedef struct NVA084_CTRL_KERNEL_HOST_VGPU_DEVICE_GET_BAR_MAPPING_RANGES_PARAMS { + NV_DECLARE_ALIGNED(NvU64 offsets[NVA084_CTRL_KERNEL_HOST_VGPU_DEVICE_MAX_BAR_MAPPING_RANGES], 8); + NV_DECLARE_ALIGNED(NvU64 sizes[NVA084_CTRL_KERNEL_HOST_VGPU_DEVICE_MAX_BAR_MAPPING_RANGES], 8); + NvU32 numRanges; + NvU32 osPageSize; + NvBool mitigated[NVA084_CTRL_KERNEL_HOST_VGPU_DEVICE_MAX_BAR_MAPPING_RANGES]; +} NVA084_CTRL_KERNEL_HOST_VGPU_DEVICE_GET_BAR_MAPPING_RANGES_PARAMS; -/* NVA084_CTRL_CMD_KERNEL_HOST_VGPU_DEVICE_SET_GUEST_ID - * - * This command is used to set/unset VM ID parameters in host vgpu device in RM. - * - * Parameters: +/* + * NVA084_CTRL_CMD_KERNEL_HOST_VGPU_DEVICE_RESTORE_DEFAULT_EXEC_PARTITION * - * action - * This parameter specifies the desired set guest id action. - * Valid set guest id actions include: - * NVA084_CTRL_HOST_VGPU_DEVICE_KERNEL_SET_GUEST_ID_ACTION_SET - * This action sets the VM ID information in host vgpu device. - * NVA084_CTRL_HOST_VGPU_DEVICE_KERNEL_SET_GUEST_ID_ACTION_UNSET - * This action unsets the VM ID information in host vgpu device. - * vmPid [IN] - * VM process ID - * vmIdType[IN] - * VM ID type whether it's UUID or DOMAIN_ID - * guestVmId[IN] - * VM ID + * This command restores the vGPU device's default EXEC partition saved in + * KERNEL_HOST_VGPU_DEVICE. * * Possible status values returned are: * NV_OK - * NV_ERR_INVALID_ARGUMENT + * NV_ERR_OBJECT_NOT_FOUND + * NV_ERR_NOT_SUPPORTED */ -#define NVA084_CTRL_CMD_KERNEL_HOST_VGPU_DEVICE_SET_GUEST_ID (0xa0840109) /* finn: Evaluated from "(FINN_NVA084_KERNEL_HOST_VGPU_DEVICE_KERNEL_HOST_VGPU_DEVICE_INTERFACE_ID << 8) | NVA084_CTRL_KERNEL_HOST_VGPU_DEVICE_SET_GUEST_ID_PARAMS_MESSAGE_ID" */ - -#define NVA084_CTRL_KERNEL_HOST_VGPU_DEVICE_SET_GUEST_ID_PARAMS_MESSAGE_ID (0x9U) - -typedef struct NVA084_CTRL_KERNEL_HOST_VGPU_DEVICE_SET_GUEST_ID_PARAMS { - NvU8 action; - NvU32 vmPid; - VM_ID_TYPE vmIdType; - NV_DECLARE_ALIGNED(VM_ID guestVmId, 8); -} NVA084_CTRL_KERNEL_HOST_VGPU_DEVICE_SET_GUEST_ID_PARAMS; - -#define NVA084_CTRL_KERNEL_HOST_VGPU_DEVICE_SET_GUEST_ID_ACTION_SET (0x00000000) -#define NVA084_CTRL_KERNEL_HOST_VGPU_DEVICE_SET_GUEST_ID_ACTION_UNSET (0x00000001) +#define NVA084_CTRL_CMD_KERNEL_HOST_VGPU_DEVICE_RESTORE_DEFAULT_EXEC_PARTITION (0xa084010b) /* finn: Evaluated from "(FINN_NVA084_KERNEL_HOST_VGPU_DEVICE_KERNEL_HOST_VGPU_DEVICE_INTERFACE_ID << 8) | 0xB" */ /* _ctrla084_h_ */ diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/common/sdk/nvidia/inc/ctrl/ctrla16f.h nvidia-open-gpu-kernel-modules-535.161.08/src/common/sdk/nvidia/inc/ctrl/ctrla16f.h --- nvidia-open-gpu-kernel-modules-525.147.05/src/common/sdk/nvidia/inc/ctrl/ctrla16f.h 2023-10-25 20:22:22.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/common/sdk/nvidia/inc/ctrl/ctrla16f.h 2024-03-05 22:15:16.000000000 +0000 @@ -25,7 +25,7 @@ // // This file was generated with FINN, an NVIDIA coding tool. -// Source file: ctrl/ctrla16f.finn +// Source file: ctrl/ctrla16f.finn // @@ -65,20 +65,11 @@ * Please see description of NVA06F_CTRL_GET_CLASS_ENGINEID for more information. * */ -#define NVA16F_CTRL_GET_CLASS_ENGINEID (0xa16f0101) /* finn: Evaluated from "(FINN_KEPLER_CHANNEL_GPFIFO_B_GPFIFO_INTERFACE_ID << 8) | 0x1" */ - -typedef NVA06F_CTRL_GET_CLASS_ENGINEID_PARAMS NVA16F_CTRL_GET_CLASS_ENGINEID_PARAMS; - -// FINN PORT: The below type was generated by the FINN port to -// ensure that all API's have a unique structure associated -// with them! -#define NVA16F_CTRL_GET_CLASS_ENGINEID_FINN_PARAMS_MESSAGE_ID (0x1U) - -typedef struct NVA16F_CTRL_GET_CLASS_ENGINEID_FINN_PARAMS { - NVA16F_CTRL_GET_CLASS_ENGINEID_PARAMS params; -} NVA16F_CTRL_GET_CLASS_ENGINEID_FINN_PARAMS; +#define NVA16F_CTRL_GET_CLASS_ENGINEID (0xa16f0101) /* finn: Evaluated from "(FINN_KEPLER_CHANNEL_GPFIFO_B_GPFIFO_INTERFACE_ID << 8) | NVA16F_CTRL_GET_CLASS_ENGINEID_PARAMS_MESSAGE_ID" */ +#define NVA16F_CTRL_GET_CLASS_ENGINEID_PARAMS_MESSAGE_ID (0x1U) +typedef NVA06F_CTRL_GET_CLASS_ENGINEID_PARAMS NVA16F_CTRL_GET_CLASS_ENGINEID_PARAMS; /* * NVA16F_CTRL_RESET_CHANNEL @@ -86,19 +77,11 @@ * Please see description of NVA06F_CTRL_RESET_CHANNEL for more information. * */ -#define NVA16F_CTRL_CMD_RESET_CHANNEL (0xa16f0102) /* finn: Evaluated from "(FINN_KEPLER_CHANNEL_GPFIFO_B_GPFIFO_INTERFACE_ID << 8) | 0x2" */ -typedef NVA06F_CTRL_CMD_RESET_CHANNEL_PARAMS NVA16F_CTRL_CMD_RESET_CHANNEL_PARAMS; - -// FINN PORT: The below type was generated by the FINN port to -// ensure that all API's have a unique structure associated -// with them! -#define NVA16F_CTRL_CMD_RESET_CHANNEL_FINN_PARAMS_MESSAGE_ID (0x2U) - -typedef struct NVA16F_CTRL_CMD_RESET_CHANNEL_FINN_PARAMS { - NVA16F_CTRL_CMD_RESET_CHANNEL_PARAMS params; -} NVA16F_CTRL_CMD_RESET_CHANNEL_FINN_PARAMS; +#define NVA16F_CTRL_CMD_RESET_CHANNEL (0xa16f0102) /* finn: Evaluated from "(FINN_KEPLER_CHANNEL_GPFIFO_B_GPFIFO_INTERFACE_ID << 8) | NVA16F_CTRL_CMD_RESET_CHANNEL_PARAMS_MESSAGE_ID" */ +#define NVA16F_CTRL_CMD_RESET_CHANNEL_PARAMS_MESSAGE_ID (0x2U) +typedef NVA06F_CTRL_CMD_RESET_CHANNEL_PARAMS NVA16F_CTRL_CMD_RESET_CHANNEL_PARAMS; /* * NVA16F_CTRL_CMD_GPFIFO_SCHEDULE @@ -106,59 +89,33 @@ * Please see description of NVA06F_CTRL_CMD_GPFIFO_SCHEDULE for more information. * */ -#define NVA16F_CTRL_CMD_GPFIFO_SCHEDULE (0xa16f0103) /* finn: Evaluated from "(FINN_KEPLER_CHANNEL_GPFIFO_B_GPFIFO_INTERFACE_ID << 8) | 0x3" */ -typedef NVA06F_CTRL_GPFIFO_SCHEDULE_PARAMS NVA16F_CTRL_GPFIFO_SCHEDULE_PARAMS; - -// FINN PORT: The below type was generated by the FINN port to -// ensure that all API's have a unique structure associated -// with them! -#define NVA16F_CTRL_CMD_GPFIFO_SCHEDULE_FINN_PARAMS_MESSAGE_ID (0x3U) - -typedef struct NVA16F_CTRL_CMD_GPFIFO_SCHEDULE_FINN_PARAMS { - NVA16F_CTRL_GPFIFO_SCHEDULE_PARAMS params; -} NVA16F_CTRL_CMD_GPFIFO_SCHEDULE_FINN_PARAMS; +#define NVA16F_CTRL_CMD_GPFIFO_SCHEDULE (0xa16f0103) /* finn: Evaluated from "(FINN_KEPLER_CHANNEL_GPFIFO_B_GPFIFO_INTERFACE_ID << 8) | NVA16F_CTRL_GPFIFO_SCHEDULE_PARAMS_MESSAGE_ID" */ +#define NVA16F_CTRL_GPFIFO_SCHEDULE_PARAMS_MESSAGE_ID (0x3U) +typedef NVA06F_CTRL_GPFIFO_SCHEDULE_PARAMS NVA16F_CTRL_GPFIFO_SCHEDULE_PARAMS; /* * NVA16F_CTRL_CMD_BIND * * Please see description of NVA06F_CTRL_CMD_BIND for more information. */ -#define NVA16F_CTRL_CMD_BIND (0xa16f0104) /* finn: Evaluated from "(FINN_KEPLER_CHANNEL_GPFIFO_B_GPFIFO_INTERFACE_ID << 8) | 0x4" */ - -typedef NVA06F_CTRL_BIND_PARAMS NVA16F_CTRL_BIND_PARAMS; - -// FINN PORT: The below type was generated by the FINN port to -// ensure that all API's have a unique structure associated -// with them! -#define NVA16F_CTRL_CMD_BIND_FINN_PARAMS_MESSAGE_ID (0x4U) - -typedef struct NVA16F_CTRL_CMD_BIND_FINN_PARAMS { - NVA16F_CTRL_BIND_PARAMS params; -} NVA16F_CTRL_CMD_BIND_FINN_PARAMS; +#define NVA16F_CTRL_CMD_BIND (0xa16f0104) /* finn: Evaluated from "(FINN_KEPLER_CHANNEL_GPFIFO_B_GPFIFO_INTERFACE_ID << 8) | NVA16F_CTRL_BIND_PARAMS_MESSAGE_ID" */ +#define NVA16F_CTRL_BIND_PARAMS_MESSAGE_ID (0x4U) +typedef NVA06F_CTRL_BIND_PARAMS NVA16F_CTRL_BIND_PARAMS; /* * NVA16F_CTRL_CMD_EVENT_SET_NOTIFICATION * * Please see description of NVA06F_CTRL_CMD_EVENT_SET_NOTIFICATION for more information. */ -#define NVA16F_CTRL_CMD_EVENT_SET_NOTIFICATION (0xa16f0205) /* finn: Evaluated from "(FINN_KEPLER_CHANNEL_GPFIFO_B_EVENT_INTERFACE_ID << 8) | 0x5" */ - -typedef NVA06F_CTRL_EVENT_SET_NOTIFICATION_PARAMS NVA16F_CTRL_EVENT_SET_NOTIFICATION_PARAMS; - -// FINN PORT: The below type was generated by the FINN port to -// ensure that all API's have a unique structure associated -// with them! -#define NVA16F_CTRL_CMD_EVENT_SET_NOTIFICATION_FINN_PARAMS_MESSAGE_ID (0x5U) - -typedef struct NVA16F_CTRL_CMD_EVENT_SET_NOTIFICATION_FINN_PARAMS { - NVA16F_CTRL_EVENT_SET_NOTIFICATION_PARAMS params; -} NVA16F_CTRL_CMD_EVENT_SET_NOTIFICATION_FINN_PARAMS; +#define NVA16F_CTRL_CMD_EVENT_SET_NOTIFICATION (0xa16f0205) /* finn: Evaluated from "(FINN_KEPLER_CHANNEL_GPFIFO_B_EVENT_INTERFACE_ID << 8) | NVA16F_CTRL_EVENT_SET_NOTIFICATION_PARAMS_MESSAGE_ID" */ +#define NVA16F_CTRL_EVENT_SET_NOTIFICATION_PARAMS_MESSAGE_ID (0x5U) +typedef NVA06F_CTRL_EVENT_SET_NOTIFICATION_PARAMS NVA16F_CTRL_EVENT_SET_NOTIFICATION_PARAMS; /* valid action values */ #define NVA16F_CTRL_EVENT_SET_NOTIFICATION_ACTION_DISABLE NVA06F_CTRL_EVENT_SET_NOTIFICATION_ACTION_DISABLE @@ -182,19 +139,10 @@ * Please see description of NV906F_CTRL_CMD_GET_MMU_FAULT_INFO for more information. * */ -#define NVA16F_CTRL_CMD_GET_MMU_FAULT_INFO (0xa16f0107) /* finn: Evaluated from "(FINN_KEPLER_CHANNEL_GPFIFO_B_GPFIFO_INTERFACE_ID << 8) | 0x7" */ - -typedef NV906F_CTRL_GET_MMU_FAULT_INFO_PARAMS NVA16F_CTRL_GET_MMU_FAULT_INFO_PARAMS; - -// FINN PORT: The below type was generated by the FINN port to -// ensure that all API's have a unique structure associated -// with them! -#define NVA16F_CTRL_CMD_GET_MMU_FAULT_INFO_FINN_PARAMS_MESSAGE_ID (0x7U) - -typedef struct NVA16F_CTRL_CMD_GET_MMU_FAULT_INFO_FINN_PARAMS { - NV_DECLARE_ALIGNED(NVA16F_CTRL_GET_MMU_FAULT_INFO_PARAMS params, 8); -} NVA16F_CTRL_CMD_GET_MMU_FAULT_INFO_FINN_PARAMS; +#define NVA16F_CTRL_CMD_GET_MMU_FAULT_INFO (0xa16f0107) /* finn: Evaluated from "(FINN_KEPLER_CHANNEL_GPFIFO_B_GPFIFO_INTERFACE_ID << 8) | NVA16F_CTRL_GET_MMU_FAULT_INFO_PARAMS_MESSAGE_ID" */ +#define NVA16F_CTRL_GET_MMU_FAULT_INFO_PARAMS_MESSAGE_ID (0x7U) +typedef NV906F_CTRL_GET_MMU_FAULT_INFO_PARAMS NVA16F_CTRL_GET_MMU_FAULT_INFO_PARAMS; /* _ctrla16f.h_ */ diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/common/sdk/nvidia/inc/ctrl/ctrla26f.h nvidia-open-gpu-kernel-modules-535.161.08/src/common/sdk/nvidia/inc/ctrl/ctrla26f.h --- nvidia-open-gpu-kernel-modules-525.147.05/src/common/sdk/nvidia/inc/ctrl/ctrla26f.h 2023-10-25 20:22:22.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/common/sdk/nvidia/inc/ctrl/ctrla26f.h 2024-03-05 22:15:17.000000000 +0000 @@ -25,7 +25,7 @@ // // This file was generated with FINN, an NVIDIA coding tool. -// Source file: ctrl/ctrla26f.finn +// Source file: ctrl/ctrla26f.finn // @@ -65,20 +65,11 @@ * Please see description of NV906F_CTRL_GET_CLASS_ENGINEID for more information. * */ -#define NVA26F_CTRL_GET_CLASS_ENGINEID (0xa26f0101) /* finn: Evaluated from "(FINN_KEPLER_CHANNEL_GPFIFO_C_GPFIFO_INTERFACE_ID << 8) | 0x1" */ - -typedef NV906F_CTRL_GET_CLASS_ENGINEID_PARAMS NVA26F_CTRL_GET_CLASS_ENGINEID_PARAMS; - -// FINN PORT: The below type was generated by the FINN port to -// ensure that all API's have a unique structure associated -// with them! -#define NVA26F_CTRL_GET_CLASS_ENGINEID_FINN_PARAMS_MESSAGE_ID (0x1U) - -typedef struct NVA26F_CTRL_GET_CLASS_ENGINEID_FINN_PARAMS { - NVA26F_CTRL_GET_CLASS_ENGINEID_PARAMS params; -} NVA26F_CTRL_GET_CLASS_ENGINEID_FINN_PARAMS; +#define NVA26F_CTRL_GET_CLASS_ENGINEID (0xa26f0101) /* finn: Evaluated from "(FINN_KEPLER_CHANNEL_GPFIFO_C_GPFIFO_INTERFACE_ID << 8) | NVA26F_CTRL_GET_CLASS_ENGINEID_PARAMS_MESSAGE_ID" */ +#define NVA26F_CTRL_GET_CLASS_ENGINEID_PARAMS_MESSAGE_ID (0x1U) +typedef NV906F_CTRL_GET_CLASS_ENGINEID_PARAMS NVA26F_CTRL_GET_CLASS_ENGINEID_PARAMS; /* * NVA26F_CTRL_RESET_CHANNEL @@ -86,19 +77,11 @@ * Please see description of NVA06F_CTRL_CMD_RESET_CHANNEL for more information. * */ -#define NVA26F_CTRL_CMD_RESET_CHANNEL (0xa26f0102) /* finn: Evaluated from "(FINN_KEPLER_CHANNEL_GPFIFO_C_GPFIFO_INTERFACE_ID << 8) | 0x2" */ -typedef NVA06F_CTRL_CMD_RESET_CHANNEL_PARAMS NVA26F_CTRL_CMD_RESET_CHANNEL_PARAMS; - -// FINN PORT: The below type was generated by the FINN port to -// ensure that all API's have a unique structure associated -// with them! -#define NVA26F_CTRL_CMD_RESET_CHANNEL_FINN_PARAMS_MESSAGE_ID (0x2U) - -typedef struct NVA26F_CTRL_CMD_RESET_CHANNEL_FINN_PARAMS { - NVA26F_CTRL_CMD_RESET_CHANNEL_PARAMS params; -} NVA26F_CTRL_CMD_RESET_CHANNEL_FINN_PARAMS; +#define NVA26F_CTRL_CMD_RESET_CHANNEL (0xa26f0102) /* finn: Evaluated from "(FINN_KEPLER_CHANNEL_GPFIFO_C_GPFIFO_INTERFACE_ID << 8) | NVA26F_CTRL_CMD_RESET_CHANNEL_PARAMS_MESSAGE_ID" */ +#define NVA26F_CTRL_CMD_RESET_CHANNEL_PARAMS_MESSAGE_ID (0x2U) +typedef NVA06F_CTRL_CMD_RESET_CHANNEL_PARAMS NVA26F_CTRL_CMD_RESET_CHANNEL_PARAMS; /* * NVA26F_CTRL_CMD_GPFIFO_SCHEDULE @@ -106,59 +89,33 @@ * Please see description of NVA06F_CTRL_CMD_GPFIFO_SCHEDULE for more information. * */ -#define NVA26F_CTRL_CMD_GPFIFO_SCHEDULE (0xa26f0103) /* finn: Evaluated from "(FINN_KEPLER_CHANNEL_GPFIFO_C_GPFIFO_INTERFACE_ID << 8) | 0x3" */ -typedef NVA06F_CTRL_GPFIFO_SCHEDULE_PARAMS NVA26F_CTRL_GPFIFO_SCHEDULE_PARAMS; - -// FINN PORT: The below type was generated by the FINN port to -// ensure that all API's have a unique structure associated -// with them! -#define NVA26F_CTRL_CMD_GPFIFO_SCHEDULE_FINN_PARAMS_MESSAGE_ID (0x3U) - -typedef struct NVA26F_CTRL_CMD_GPFIFO_SCHEDULE_FINN_PARAMS { - NVA26F_CTRL_GPFIFO_SCHEDULE_PARAMS params; -} NVA26F_CTRL_CMD_GPFIFO_SCHEDULE_FINN_PARAMS; +#define NVA26F_CTRL_CMD_GPFIFO_SCHEDULE (0xa26f0103) /* finn: Evaluated from "(FINN_KEPLER_CHANNEL_GPFIFO_C_GPFIFO_INTERFACE_ID << 8) | NVA26F_CTRL_GPFIFO_SCHEDULE_PARAMS_MESSAGE_ID" */ +#define NVA26F_CTRL_GPFIFO_SCHEDULE_PARAMS_MESSAGE_ID (0x3U) +typedef NVA06F_CTRL_GPFIFO_SCHEDULE_PARAMS NVA26F_CTRL_GPFIFO_SCHEDULE_PARAMS; /* * NVA26F_CTRL_CMD_BIND * * Please see description of NVA06F_CTRL_CMD_BIND for more information. */ -#define NVA26F_CTRL_CMD_BIND (0xa26f0104) /* finn: Evaluated from "(FINN_KEPLER_CHANNEL_GPFIFO_C_GPFIFO_INTERFACE_ID << 8) | 0x4" */ - -typedef NVA06F_CTRL_BIND_PARAMS NVA26F_CTRL_BIND_PARAMS; - -// FINN PORT: The below type was generated by the FINN port to -// ensure that all API's have a unique structure associated -// with them! -#define NVA26F_CTRL_CMD_BIND_FINN_PARAMS_MESSAGE_ID (0x4U) - -typedef struct NVA26F_CTRL_CMD_BIND_FINN_PARAMS { - NVA26F_CTRL_BIND_PARAMS params; -} NVA26F_CTRL_CMD_BIND_FINN_PARAMS; +#define NVA26F_CTRL_CMD_BIND (0xa26f0104) /* finn: Evaluated from "(FINN_KEPLER_CHANNEL_GPFIFO_C_GPFIFO_INTERFACE_ID << 8) | NVA26F_CTRL_BIND_PARAMS_MESSAGE_ID" */ +#define NVA26F_CTRL_BIND_PARAMS_MESSAGE_ID (0x4U) +typedef NVA06F_CTRL_BIND_PARAMS NVA26F_CTRL_BIND_PARAMS; /* * NVA26F_CTRL_CMD_EVENT_SET_NOTIFICATION * * Please see description of NVA06F_CTRL_CMD_EVENT_SET_NOTIFICATION for more information. */ -#define NVA26F_CTRL_CMD_EVENT_SET_NOTIFICATION (0xa26f0205) /* finn: Evaluated from "(FINN_KEPLER_CHANNEL_GPFIFO_C_EVENT_INTERFACE_ID << 8) | 0x5" */ - -typedef NVA06F_CTRL_EVENT_SET_NOTIFICATION_PARAMS NVA26F_CTRL_EVENT_SET_NOTIFICATION_PARAMS; - -// FINN PORT: The below type was generated by the FINN port to -// ensure that all API's have a unique structure associated -// with them! -#define NVA26F_CTRL_CMD_EVENT_SET_NOTIFICATION_FINN_PARAMS_MESSAGE_ID (0x5U) - -typedef struct NVA26F_CTRL_CMD_EVENT_SET_NOTIFICATION_FINN_PARAMS { - NVA26F_CTRL_EVENT_SET_NOTIFICATION_PARAMS params; -} NVA26F_CTRL_CMD_EVENT_SET_NOTIFICATION_FINN_PARAMS; +#define NVA26F_CTRL_CMD_EVENT_SET_NOTIFICATION (0xa26f0205) /* finn: Evaluated from "(FINN_KEPLER_CHANNEL_GPFIFO_C_EVENT_INTERFACE_ID << 8) | NVA26F_CTRL_EVENT_SET_NOTIFICATION_PARAMS_MESSAGE_ID" */ +#define NVA26F_CTRL_EVENT_SET_NOTIFICATION_PARAMS_MESSAGE_ID (0x5U) +typedef NVA06F_CTRL_EVENT_SET_NOTIFICATION_PARAMS NVA26F_CTRL_EVENT_SET_NOTIFICATION_PARAMS; /* valid action values */ #define NVA26F_CTRL_EVENT_SET_NOTIFICATION_ACTION_DISABLE NVA06F_CTRL_EVENT_SET_NOTIFICATION_ACTION_DISABLE @@ -182,19 +139,10 @@ * Please see description of NV906F_CTRL_CMD_GET_MMU_FAULT_INFO for more information. * */ -#define NVA26F_CTRL_CMD_GET_MMU_FAULT_INFO (0xa26f0107) /* finn: Evaluated from "(FINN_KEPLER_CHANNEL_GPFIFO_C_GPFIFO_INTERFACE_ID << 8) | 0x7" */ - -typedef NV906F_CTRL_GET_MMU_FAULT_INFO_PARAMS NVA26F_CTRL_GET_MMU_FAULT_INFO_PARAMS; - -// FINN PORT: The below type was generated by the FINN port to -// ensure that all API's have a unique structure associated -// with them! -#define NVA26F_CTRL_CMD_GET_MMU_FAULT_INFO_FINN_PARAMS_MESSAGE_ID (0x7U) - -typedef struct NVA26F_CTRL_CMD_GET_MMU_FAULT_INFO_FINN_PARAMS { - NV_DECLARE_ALIGNED(NVA26F_CTRL_GET_MMU_FAULT_INFO_PARAMS params, 8); -} NVA26F_CTRL_CMD_GET_MMU_FAULT_INFO_FINN_PARAMS; +#define NVA26F_CTRL_CMD_GET_MMU_FAULT_INFO (0xa26f0107) /* finn: Evaluated from "(FINN_KEPLER_CHANNEL_GPFIFO_C_GPFIFO_INTERFACE_ID << 8) | NVA26F_CTRL_GET_MMU_FAULT_INFO_PARAMS_MESSAGE_ID" */ +#define NVA26F_CTRL_GET_MMU_FAULT_INFO_PARAMS_MESSAGE_ID (0x7U) +typedef NV906F_CTRL_GET_MMU_FAULT_INFO_PARAMS NVA26F_CTRL_GET_MMU_FAULT_INFO_PARAMS; /* _ctrla26f.h_ */ diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/common/sdk/nvidia/inc/ctrl/ctrlb069.h nvidia-open-gpu-kernel-modules-535.161.08/src/common/sdk/nvidia/inc/ctrl/ctrlb069.h --- nvidia-open-gpu-kernel-modules-525.147.05/src/common/sdk/nvidia/inc/ctrl/ctrlb069.h 2023-10-25 20:22:23.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/common/sdk/nvidia/inc/ctrl/ctrlb069.h 2024-03-05 22:15:17.000000000 +0000 @@ -27,7 +27,7 @@ // // This file was generated with FINN, an NVIDIA coding tool. -// Source file: ctrl/ctrlb069.finn +// Source file: ctrl/ctrlb069.finn // #include "ctrl/ctrlxxxx.h" @@ -161,6 +161,8 @@ * Mapping for PMC intr clear register - used to disable an intr (NV_PMC_INTR_EN_CLEAR(0)) * replayableFaultMask * Mask for the replayable fault bit(NV_PMC_INTR_REPLAYABLE_FAULT) + * faultBufferType + * This is an input param denoting replayable/non-replayable fault buffer */ #define NVB069_CTRL_CMD_FAULTBUFFER_GET_REGISTER_MAPPINGS (0xb0690106) /* finn: Evaluated from "(FINN_MAXWELL_FAULT_BUFFER_A_FAULTBUFFER_INTERFACE_ID << 8) | NVB069_CTRL_CMD_FAULTBUFFER_GET_REGISTER_MAPPINGS_PARAMS_MESSAGE_ID" */ @@ -175,6 +177,7 @@ NV_DECLARE_ALIGNED(NvP64 pPmcIntrEnClear, 8); NvU32 replayableFaultMask; NV_DECLARE_ALIGNED(NvP64 pPrefetchCtrl, 8); + NvU32 faultBufferType; } NVB069_CTRL_CMD_FAULTBUFFER_GET_REGISTER_MAPPINGS_PARAMS; /* _ctrlb069_h_ */ diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/common/sdk/nvidia/inc/ctrl/ctrlb06f.h nvidia-open-gpu-kernel-modules-535.161.08/src/common/sdk/nvidia/inc/ctrl/ctrlb06f.h --- nvidia-open-gpu-kernel-modules-525.147.05/src/common/sdk/nvidia/inc/ctrl/ctrlb06f.h 2023-10-25 20:22:23.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/common/sdk/nvidia/inc/ctrl/ctrlb06f.h 2024-03-05 22:15:17.000000000 +0000 @@ -27,7 +27,7 @@ // // This file was generated with FINN, an NVIDIA coding tool. -// Source file: ctrl/ctrlb06f.finn +// Source file: ctrl/ctrlb06f.finn // @@ -67,20 +67,11 @@ * Please see description of NV906F_CTRL_GET_CLASS_ENGINEID for more information. * */ -#define NVB06F_CTRL_GET_CLASS_ENGINEID (0xb06f0101) /* finn: Evaluated from "(FINN_MAXWELL_CHANNEL_GPFIFO_A_GPFIFO_INTERFACE_ID << 8) | 0x1" */ - -typedef NV906F_CTRL_GET_CLASS_ENGINEID_PARAMS NVB06F_CTRL_GET_CLASS_ENGINEID_PARAMS; - -// FINN PORT: The below type was generated by the FINN port to -// ensure that all API's have a unique structure associated -// with them! -#define NVB06F_CTRL_GET_CLASS_ENGINEID_FINN_PARAMS_MESSAGE_ID (0x1U) - -typedef struct NVB06F_CTRL_GET_CLASS_ENGINEID_FINN_PARAMS { - NVB06F_CTRL_GET_CLASS_ENGINEID_PARAMS params; -} NVB06F_CTRL_GET_CLASS_ENGINEID_FINN_PARAMS; +#define NVB06F_CTRL_GET_CLASS_ENGINEID (0xb06f0101) /* finn: Evaluated from "(FINN_MAXWELL_CHANNEL_GPFIFO_A_GPFIFO_INTERFACE_ID << 8) | NVB06F_CTRL_GET_CLASS_ENGINEID_PARAMS_MESSAGE_ID" */ +#define NVB06F_CTRL_GET_CLASS_ENGINEID_PARAMS_MESSAGE_ID (0x1U) +typedef NV906F_CTRL_GET_CLASS_ENGINEID_PARAMS NVB06F_CTRL_GET_CLASS_ENGINEID_PARAMS; /* * NVB06F_CTRL_RESET_CHANNEL @@ -88,20 +79,11 @@ * Please see description of NVA06F_CTRL_RESET_CHANNEL for more information. * */ -#define NVB06F_CTRL_CMD_RESET_CHANNEL (0xb06f0102) /* finn: Evaluated from "(FINN_MAXWELL_CHANNEL_GPFIFO_A_GPFIFO_INTERFACE_ID << 8) | 0x2" */ - -typedef NVA06F_CTRL_CMD_RESET_CHANNEL_PARAMS NVB06F_CTRL_CMD_RESET_CHANNEL_PARAMS; - -// FINN PORT: The below type was generated by the FINN port to -// ensure that all API's have a unique structure associated -// with them! -#define NVB06F_CTRL_CMD_RESET_CHANNEL_FINN_PARAMS_MESSAGE_ID (0x2U) - -typedef struct NVB06F_CTRL_CMD_RESET_CHANNEL_FINN_PARAMS { - NVB06F_CTRL_CMD_RESET_CHANNEL_PARAMS params; -} NVB06F_CTRL_CMD_RESET_CHANNEL_FINN_PARAMS; +#define NVB06F_CTRL_CMD_RESET_CHANNEL (0xb06f0102) /* finn: Evaluated from "(FINN_MAXWELL_CHANNEL_GPFIFO_A_GPFIFO_INTERFACE_ID << 8) | NVB06F_CTRL_CMD_RESET_CHANNEL_PARAMS_MESSAGE_ID" */ +#define NVB06F_CTRL_CMD_RESET_CHANNEL_PARAMS_MESSAGE_ID (0x2U) +typedef NVA06F_CTRL_CMD_RESET_CHANNEL_PARAMS NVB06F_CTRL_CMD_RESET_CHANNEL_PARAMS; /* * NVB06F_CTRL_CMD_GPFIFO_SCHEDULE @@ -109,60 +91,33 @@ * Please see description of NVA06F_CTRL_CMD_GPFIFO_SCHEDULE for more information. * */ -#define NVB06F_CTRL_CMD_GPFIFO_SCHEDULE (0xb06f0103) /* finn: Evaluated from "(FINN_MAXWELL_CHANNEL_GPFIFO_A_GPFIFO_INTERFACE_ID << 8) | 0x3" */ - -typedef NVA06F_CTRL_GPFIFO_SCHEDULE_PARAMS NVB06F_CTRL_GPFIFO_SCHEDULE_PARAMS; - -// FINN PORT: The below type was generated by the FINN port to -// ensure that all API's have a unique structure associated -// with them! -#define NVB06F_CTRL_CMD_GPFIFO_SCHEDULE_FINN_PARAMS_MESSAGE_ID (0x3U) - -typedef struct NVB06F_CTRL_CMD_GPFIFO_SCHEDULE_FINN_PARAMS { - NVB06F_CTRL_GPFIFO_SCHEDULE_PARAMS params; -} NVB06F_CTRL_CMD_GPFIFO_SCHEDULE_FINN_PARAMS; +#define NVB06F_CTRL_CMD_GPFIFO_SCHEDULE (0xb06f0103) /* finn: Evaluated from "(FINN_MAXWELL_CHANNEL_GPFIFO_A_GPFIFO_INTERFACE_ID << 8) | NVB06F_CTRL_GPFIFO_SCHEDULE_PARAMS_MESSAGE_ID" */ +#define NVB06F_CTRL_GPFIFO_SCHEDULE_PARAMS_MESSAGE_ID (0x3U) +typedef NVA06F_CTRL_GPFIFO_SCHEDULE_PARAMS NVB06F_CTRL_GPFIFO_SCHEDULE_PARAMS; /* * NVB06F_CTRL_CMD_BIND * * Please see description of NVA06F_CTRL_CMD_BIND for more information. */ -#define NVB06F_CTRL_CMD_BIND (0xb06f0104) /* finn: Evaluated from "(FINN_MAXWELL_CHANNEL_GPFIFO_A_GPFIFO_INTERFACE_ID << 8) | 0x4" */ - -typedef NVA06F_CTRL_BIND_PARAMS NVB06F_CTRL_BIND_PARAMS; - -// FINN PORT: The below type was generated by the FINN port to -// ensure that all API's have a unique structure associated -// with them! -#define NVB06F_CTRL_CMD_BIND_FINN_PARAMS_MESSAGE_ID (0x4U) - -typedef struct NVB06F_CTRL_CMD_BIND_FINN_PARAMS { - NVB06F_CTRL_BIND_PARAMS params; -} NVB06F_CTRL_CMD_BIND_FINN_PARAMS; +#define NVB06F_CTRL_CMD_BIND (0xb06f0104) /* finn: Evaluated from "(FINN_MAXWELL_CHANNEL_GPFIFO_A_GPFIFO_INTERFACE_ID << 8) | NVB06F_CTRL_BIND_PARAMS_MESSAGE_ID" */ +#define NVB06F_CTRL_BIND_PARAMS_MESSAGE_ID (0x4U) +typedef NVA06F_CTRL_BIND_PARAMS NVB06F_CTRL_BIND_PARAMS; /* * NVB06F_CTRL_CMD_EVENT_SET_NOTIFICATION * * Please see description of NVA06F_CTRL_CMD_EVENT_SET_NOTIFICATION for more information. */ -#define NVB06F_CTRL_CMD_EVENT_SET_NOTIFICATION (0xb06f0205) /* finn: Evaluated from "(FINN_MAXWELL_CHANNEL_GPFIFO_A_EVENT_INTERFACE_ID << 8) | 0x5" */ - -typedef NVA06F_CTRL_EVENT_SET_NOTIFICATION_PARAMS NVB06F_CTRL_EVENT_SET_NOTIFICATION_PARAMS; - -// FINN PORT: The below type was generated by the FINN port to -// ensure that all API's have a unique structure associated -// with them! -#define NVB06F_CTRL_CMD_EVENT_SET_NOTIFICATION_FINN_PARAMS_MESSAGE_ID (0x5U) - -typedef struct NVB06F_CTRL_CMD_EVENT_SET_NOTIFICATION_FINN_PARAMS { - NVB06F_CTRL_EVENT_SET_NOTIFICATION_PARAMS params; -} NVB06F_CTRL_CMD_EVENT_SET_NOTIFICATION_FINN_PARAMS; +#define NVB06F_CTRL_CMD_EVENT_SET_NOTIFICATION (0xb06f0205) /* finn: Evaluated from "(FINN_MAXWELL_CHANNEL_GPFIFO_A_EVENT_INTERFACE_ID << 8) | NVB06F_CTRL_EVENT_SET_NOTIFICATION_PARAMS_MESSAGE_ID" */ +#define NVB06F_CTRL_EVENT_SET_NOTIFICATION_PARAMS_MESSAGE_ID (0x5U) +typedef NVA06F_CTRL_EVENT_SET_NOTIFICATION_PARAMS NVB06F_CTRL_EVENT_SET_NOTIFICATION_PARAMS; /* valid action values */ #define NVB06F_CTRL_EVENT_SET_NOTIFICATION_ACTION_DISABLE NVA06F_CTRL_EVENT_SET_NOTIFICATION_ACTION_DISABLE @@ -186,20 +141,11 @@ * Please see description of NV906F_CTRL_CMD_GET_MMU_FAULT_INFO for more information. * */ -#define NVB06F_CTRL_CMD_GET_MMU_FAULT_INFO (0xb06f0107) /* finn: Evaluated from "(FINN_MAXWELL_CHANNEL_GPFIFO_A_GPFIFO_INTERFACE_ID << 8) | 0x7" */ - -typedef NV906F_CTRL_GET_MMU_FAULT_INFO_PARAMS NVB06F_CTRL_GET_MMU_FAULT_INFO_PARAMS; - -// FINN PORT: The below type was generated by the FINN port to -// ensure that all API's have a unique structure associated -// with them! -#define NVB06F_CTRL_CMD_GET_MMU_FAULT_INFO_FINN_PARAMS_MESSAGE_ID (0x7U) - -typedef struct NVB06F_CTRL_CMD_GET_MMU_FAULT_INFO_FINN_PARAMS { - NV_DECLARE_ALIGNED(NVB06F_CTRL_GET_MMU_FAULT_INFO_PARAMS params, 8); -} NVB06F_CTRL_CMD_GET_MMU_FAULT_INFO_FINN_PARAMS; +#define NVB06F_CTRL_CMD_GET_MMU_FAULT_INFO (0xb06f0107) /* finn: Evaluated from "(FINN_MAXWELL_CHANNEL_GPFIFO_A_GPFIFO_INTERFACE_ID << 8) | NVB06F_CTRL_GET_MMU_FAULT_INFO_PARAMS_MESSAGE_ID" */ +#define NVB06F_CTRL_GET_MMU_FAULT_INFO_PARAMS_MESSAGE_ID (0x7U) +typedef NV906F_CTRL_GET_MMU_FAULT_INFO_PARAMS NVB06F_CTRL_GET_MMU_FAULT_INFO_PARAMS; /* * NVB06F_CTRL_CMD_GET_ENGINE_CTX_SIZE @@ -288,20 +234,11 @@ * NV_ERR_INVALID_STATE */ -#define NVB06F_CTRL_CMD_MIGRATE_ENGINE_CTX_DATA (0xb06f010d) /* finn: Evaluated from "(FINN_MAXWELL_CHANNEL_GPFIFO_A_GPFIFO_INTERFACE_ID << 8) | NVB06F_CTRL_CMD_MIGRATE_ENGINE_CTX_DATA_FINN_PARAMS_MESSAGE_ID" */ - -typedef NVB06F_CTRL_GET_ENGINE_CTX_DATA_PARAMS NVB06F_CTRL_MIGRATE_ENGINE_CTX_DATA_PARAMS; - -// FINN PORT: The below type was generated by the FINN port to -// ensure that all API's have a unique structure associated -// with them! -#define NVB06F_CTRL_CMD_MIGRATE_ENGINE_CTX_DATA_FINN_PARAMS_MESSAGE_ID (0xDU) - -typedef struct NVB06F_CTRL_CMD_MIGRATE_ENGINE_CTX_DATA_FINN_PARAMS { - NV_DECLARE_ALIGNED(NVB06F_CTRL_MIGRATE_ENGINE_CTX_DATA_PARAMS params, 8); -} NVB06F_CTRL_CMD_MIGRATE_ENGINE_CTX_DATA_FINN_PARAMS; +#define NVB06F_CTRL_CMD_MIGRATE_ENGINE_CTX_DATA (0xb06f010d) /* finn: Evaluated from "(FINN_MAXWELL_CHANNEL_GPFIFO_A_GPFIFO_INTERFACE_ID << 8) | NVB06F_CTRL_MIGRATE_ENGINE_CTX_DATA_PARAMS_MESSAGE_ID" */ +#define NVB06F_CTRL_MIGRATE_ENGINE_CTX_DATA_PARAMS_MESSAGE_ID (0xDU) +typedef NVB06F_CTRL_GET_ENGINE_CTX_DATA_PARAMS NVB06F_CTRL_MIGRATE_ENGINE_CTX_DATA_PARAMS; /* * NVB06F_CTRL_CMD_GET_ENGINE_CTX_STATE @@ -399,11 +336,13 @@ #define NVB06F_CTRL_CMD_CHANNEL_HW_STATE_PBDMA_FAULTED 4:4 #define NVB06F_CTRL_CMD_CHANNEL_HW_STATE_ACQUIRE_FAIL 5:5 +typedef struct NVB06F_CTRL_CHANNEL_HW_STATE_PARAMS { + NvU32 state; +} NVB06F_CTRL_CHANNEL_HW_STATE_PARAMS; + #define NVB06F_CTRL_GET_CHANNEL_HW_STATE_PARAMS_MESSAGE_ID (0xFU) -typedef struct NVB06F_CTRL_GET_CHANNEL_HW_STATE_PARAMS { - NvU32 state; -} NVB06F_CTRL_GET_CHANNEL_HW_STATE_PARAMS; +typedef NVB06F_CTRL_CHANNEL_HW_STATE_PARAMS NVB06F_CTRL_GET_CHANNEL_HW_STATE_PARAMS; /* * NVB06F_CTRL_CMD_SET_CHANNEL_HW_STATE @@ -449,18 +388,11 @@ * NV_OK * NV_ERR_INVALID_STATE */ -#define NVB06F_CTRL_CMD_SET_CHANNEL_HW_STATE (0xb06f0110) /* finn: Evaluated from "(FINN_MAXWELL_CHANNEL_GPFIFO_A_GPFIFO_INTERFACE_ID << 8) | 0x10" */ +#define NVB06F_CTRL_CMD_SET_CHANNEL_HW_STATE (0xb06f0110) /* finn: Evaluated from "(FINN_MAXWELL_CHANNEL_GPFIFO_A_GPFIFO_INTERFACE_ID << 8) | NVB06F_CTRL_SET_CHANNEL_HW_STATE_PARAMS_MESSAGE_ID" */ -typedef NVB06F_CTRL_GET_CHANNEL_HW_STATE_PARAMS NVB06F_CTRL_SET_CHANNEL_HW_STATE_PARAMS; +#define NVB06F_CTRL_SET_CHANNEL_HW_STATE_PARAMS_MESSAGE_ID (0x10U) -// FINN PORT: The below type was generated by the FINN port to -// ensure that all API's have a unique structure associated -// with them! -#define NVB06F_CTRL_CMD_SET_CHANNEL_HW_STATE_FINN_PARAMS_MESSAGE_ID (0x10U) - -typedef struct NVB06F_CTRL_CMD_SET_CHANNEL_HW_STATE_FINN_PARAMS { - NVB06F_CTRL_SET_CHANNEL_HW_STATE_PARAMS params; -} NVB06F_CTRL_CMD_SET_CHANNEL_HW_STATE_FINN_PARAMS; +typedef NVB06F_CTRL_CHANNEL_HW_STATE_PARAMS NVB06F_CTRL_SET_CHANNEL_HW_STATE_PARAMS; /* * NVB06F_CTRL_CMD_SAVE_ENGINE_CTX_DATA diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/common/sdk/nvidia/inc/ctrl/ctrlb0cc/ctrlb0ccbase.h nvidia-open-gpu-kernel-modules-535.161.08/src/common/sdk/nvidia/inc/ctrl/ctrlb0cc/ctrlb0ccbase.h --- nvidia-open-gpu-kernel-modules-525.147.05/src/common/sdk/nvidia/inc/ctrl/ctrlb0cc/ctrlb0ccbase.h 2023-10-25 20:22:23.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/common/sdk/nvidia/inc/ctrl/ctrlb0cc/ctrlb0ccbase.h 2024-03-05 22:15:17.000000000 +0000 @@ -25,7 +25,7 @@ // // This file was generated with FINN, an NVIDIA coding tool. -// Source file: ctrl/ctrlb0cc/ctrlb0ccbase.finn +// Source file: ctrl/ctrlb0cc/ctrlb0ccbase.finn // #include "ctrl/ctrlxxxx.h" diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/common/sdk/nvidia/inc/ctrl/ctrlb0cc/ctrlb0ccinternal.h nvidia-open-gpu-kernel-modules-535.161.08/src/common/sdk/nvidia/inc/ctrl/ctrlb0cc/ctrlb0ccinternal.h --- nvidia-open-gpu-kernel-modules-525.147.05/src/common/sdk/nvidia/inc/ctrl/ctrlb0cc/ctrlb0ccinternal.h 2023-10-25 20:22:23.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/common/sdk/nvidia/inc/ctrl/ctrlb0cc/ctrlb0ccinternal.h 2024-03-05 22:15:17.000000000 +0000 @@ -27,7 +27,7 @@ // // This file was generated with FINN, an NVIDIA coding tool. -// Source file: ctrl/ctrlb0cc/ctrlb0ccinternal.finn +// Source file: ctrl/ctrlb0cc/ctrlb0ccinternal.finn // #include "ctrl/ctrlb0cc/ctrlb0ccbase.h" @@ -36,7 +36,7 @@ /*! * @ref NVB0CC_CTRL_CMD_ALLOC_PMA_STREAM */ -#define NVB0CC_CTRL_CMD_INTERNAL_ALLOC_PMA_STREAM (0xb0cc0200) /* finn: Evaluated from "(FINN_MAXWELL_PROFILER_INTERNAL_INTERFACE_ID << 8) | NVB0CC_CTRL_CMD_INTERNAL_ALLOC_PMA_STREAM_FINN_PARAMS_MESSAGE_ID" */ +#define NVB0CC_CTRL_CMD_INTERNAL_ALLOC_PMA_STREAM (0xb0cc0204) /* finn: Evaluated from "(FINN_MAXWELL_PROFILER_INTERNAL_INTERFACE_ID << 8) | NVB0CC_CTRL_INTERNAL_ALLOC_PMA_STREAM_PARAMS_MESSAGE_ID" */ // FINN PORT: The below type was generated by the FINN port to @@ -76,6 +76,62 @@ NvBool bMemoryProfilingPermitted; } NVB0CC_CTRL_INTERNAL_PERMISSIONS_INIT_PARAMS; +#define NVB0CC_CTRL_INTERNAL_ALLOC_PMA_STREAM_PARAMS_MESSAGE_ID (0x4U) + +typedef struct NVB0CC_CTRL_INTERNAL_ALLOC_PMA_STREAM_PARAMS { + /*! + * [in] Memory handle (RW memory) for streaming records. + * Size of this must be >= @ref pmaBufferOffset + @ref pmaBufferSize. + */ + NvHandle hMemPmaBuffer; + + /*! + * [in] Start offset of PMA buffer (offset in @ref hMemPmaBuffer). + */ + NV_DECLARE_ALIGNED(NvU64 pmaBufferOffset, 8); + + /*! + * [in] size of the buffer. This must be <= NVB0CC_PMA_BUFFER_SIZE_MAX. + */ + NV_DECLARE_ALIGNED(NvU64 pmaBufferSize, 8); + + /*! + * [in] Memory handle (RO memory) for streaming number of bytes available. + * Size of this must be of at least @ref pmaBytesAvailableOffset + + * @ref NVB0CC_PMA_BYTES_AVAILABLE_SIZE. + */ + NvHandle hMemPmaBytesAvailable; + + /*! + * [in] Start offset of PMA bytes available buffer (offset in @ref hMemPmaBytesAvailable). + */ + NV_DECLARE_ALIGNED(NvU64 pmaBytesAvailableOffset, 8); + + /*! + * [in] Enable ctxsw for PMA stream. + */ + NvBool ctxsw; + + /*! + * [in/out] The PMA Channel Index associated with a given PMA stream. + * This parameter is input when bInputPmaChIdx is true, else it's output parameter. + */ + NvU32 pmaChannelIdx; + + /*! + * [out] PMA buffer VA. Note that this is a HWPM Virtual address. + */ + NV_DECLARE_ALIGNED(NvU64 pmaBufferVA, 8); + + /*! + * [In] This field must be specified by the client to indicate whether the + * pmaChannelIdx is input parameter or output parameter. + */ + NvBool bInputPmaChIdx; +} NVB0CC_CTRL_INTERNAL_ALLOC_PMA_STREAM_PARAMS; + + + /*! * NVB0CC_CTRL_CMD_INTERNAL_FREE_PMA_STREAM * diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/common/sdk/nvidia/inc/ctrl/ctrlb0cc/ctrlb0ccpower.h nvidia-open-gpu-kernel-modules-535.161.08/src/common/sdk/nvidia/inc/ctrl/ctrlb0cc/ctrlb0ccpower.h --- nvidia-open-gpu-kernel-modules-525.147.05/src/common/sdk/nvidia/inc/ctrl/ctrlb0cc/ctrlb0ccpower.h 1970-01-01 00:00:00.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/common/sdk/nvidia/inc/ctrl/ctrlb0cc/ctrlb0ccpower.h 2024-03-05 22:15:17.000000000 +0000 @@ -0,0 +1,402 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#pragma once + +#include + +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: ctrl/ctrlb0cc/ctrlb0ccpower.finn +// + +#include "ctrl/ctrlb0cc/ctrlb0ccbase.h" + +/* + * NVB0CC_CTRL_CMD_POWER_REQUEST_FEATURES + * + * This command attempts to enable or disable various clock-gating features of + * the GPU on behalf of the profiler. If this command is unable to set the + * clock-gating feature state of any of the requested features, this command + * will fail and none of the requested features will be modified. If this + * command fails because one or more clock-gating feature requests were + * rejected, it will return NV_ERR_STATE_IN_USE in the globalStatus + * parameter and the fields in the statusMask parameter for the features for + * which the requests were rejected will have the value + * NVB0CC_CTRL_POWER_FEATURE_MASK_*_REQUEST_REJECTED. + * If a given feature is not supported on the GPU, the field for that clock- + * gating feature will have the value + * NVB0CC_CTRL_POWER_FEATURE_MASK_*_REQUEST_NOT_SUPPORTED in the + * statusMask parameter, but this condition by itself will not cause the + * command to fail. Even if this command fails, the field for clock-gating + * features which would have successfully changed will have the value + * NVB0CC_CTRL_POWER_FEATURE_MASK_*_FULFILLED in the statusMask + * parameter. + * + * Each of the clock-gating features is reference-counted individually, so + * that multiple MAXWELL_PROFILER objects may request and rely on the same + * settings for the features simultaneously. Each clock-gating feature is + * locked to the requested state until the MAXWELL_PROFILER object is freed or + * the NVB0CC_CTRL_CMD_POWER_RELEASE_FEATURES command is called for that + * feature. + * + * Currently, only MAXWELL_PROFILER requests for power features using this + * command are reference counted. Changes to the power feature settings made + * either by other control commands or the RM itself may interfere with the + * settings requested by MAXWELL_PROFILER instances. + * + * This command will always return NV_OK when given valid + * parameters. If there is any other failure that prevents the clock-gating + * features from being set appropriately, the globalStatus parameter will + * indicate this and the statusMask parameter will indicate which clock-gating + * feature requests failed and why. + * + * controlMask + * This parameter indicates which clock-gating features the request should + * apply to. This parameter has the following fields: + * NVB0CC_CTRL_POWER_FEATURE_MASK_ELCG + * The value of this field indicates whether this request should apply + * to engine-level clock-gating of the GR engine. Valid values for + * this field are: + * NVB0CC_CTRL_POWER_FEATURE_MASK_ELCG_IGNORE + * This value indicates that the GR engine-level clock-gating + * should be ignored. This will not affect the reference count for + * this feature. + * NVB0CC_CTRL_POWER_FEATURE_MASK_ELCG_DISABLE + * This value indicates that the GR engine-level clock-gating + * should be disabled. + * NVB0CC_CTRL_POWER_FEATURE_MASK_ELCG_ENABLE + * This value indicates that the GR engine-level clock-gating + * should be enabled. + * NVB0CC_CTRL_POWER_FEATURE_MASK_BLCG + * The value of this field indicates whether this request should apply + * to block-level clock-gating. Valid values for this field are: + * NVB0CC_CTRL_POWER_FEATURE_MASK_BLCG_IGNORE + * This value indicates that block-level clock-gating should be + * ignored. This will not affect the reference count for this + * feature. + * NVB0CC_CTRL_POWER_FEATURE_MASK_BLCG_DISABLE + * This value indicates that block-level clock-gating should be + * disabled. + * NVB0CC_CTRL_POWER_FEATURE_MASK_BLCG_ENABLE + * This value indicates that block-level clock-gating should be + * enabled. + * NVB0CC_CTRL_POWER_FEATURE_MASK_SLCG + * The value of this field indicates whether this request should apply + * to second-level clock-gating. Valid values for this field are: + * NVB0CC_CTRL_POWER_FEATURE_MASK_SLCG_IGNORE + * This value indicates that second-level clock-gating should be + * ignored. This will not affect the reference count for this + * feature. + * NVB0CC_CTRL_POWER_FEATURE_MASK_SLCG_DISABLE + * This value indicates that second-level clock-gating should be + * disabled. + * NVB0CC_CTRL_POWER_FEATURE_MASK_SLCG_ENABLE + * This value indicates that second-level clock-gating should be + * enabled. + * NVB0CC_CTRL_POWER_FEATURE_MASK_ELPG + * The value of this field indicates whether this request should apply + * to GR engine-level power-gating. Valid values for this field are: + * NVB0CC_CTRL_POWER_FEATURE_MASK_ELPG_IGNORE + * This value indicates that engine-level power-gating should be + * ignored. This will not affect the reference count for this + * feature. + * NVB0CC_CTRL_POWER_FEATURE_MASK_ELPG_DISABLE + * This value indicates that engine-level power-gating should be + * disabled. + * NVB0CC_CTRL_POWER_FEATURE_MASK_ELPG_ENABLE + * This value indicates that engine-level power-gating should be + * enabled. + * Note that this field is only temporary to allow reference counting + * restricted to MAXWELL_PROFILER instances, until the time when the + * existing controls for this power feature can be updated to support + * reference counting across all clients and the RM. + * NVB0CC_CTRL_POWER_FEATURE_MASK_IDLE_SLOWDOWN + * The value of this field indicates whether this request should apply + * to SM idle slowdown. Valid values for this field are: + * NVB0CC_CTRL_POWER_FEATURE_MASK_IDLE_SLOWDOWN_IGNORE + * This value indicates that SM idle slowdown should be ignored. + * This will not affect the reference count for this feature. + * NVB0CC_CTRL_POWER_FEATURE_MASK_IDLE_SLOWDOWN_DISABLE + * This value indicates that SM idle slowdown should be disabled. + * NVB0CC_CTRL_POWER_FEATURE_MASK_IDLE_SLOWDOWN_ENABLE + * This value indicates that SM idle slowdown should be enabled. + * Note that this field is only temporary to allow reference counting + * restricted to MAXWELL_PROFILER instances, until the time when the + * existing controls for this power feature can be updated to support + * reference counting across all clients and the RM. + * NVB0CC_CTRL_POWER_FEATURE_MASK_VAT + * The value of this field indicates whether this request should apply + * to VAT. Valid values for this field are: + * NVB0CC_CTRL_POWER_FEATURE_MASK_VAT_IGNORE + * This value indicates that VAT should be ignored. + * This will not affect the reference count for this feature. + * NVB0CC_CTRL_POWER_FEATURE_MASK_VAT_DISABLE + * This value indicates that VAT should be disabled. + * NVB0CC_CTRL_POWER_FEATURE_MASK_VAT_ENABLE + * This value indicates that VAT should be enabled. + * Note that this field is only temporary to allow reference counting + * restricted to MAXWELL_PROFILER instances, until the time when the + * existing controls for this power feature can be updated to support + * reference counting across all clients and the RM. + * globalStatus + * This parameter returns the overall status of the requests for all + * clock-gating controls. If the value of this parameter is not + * NV_OK, none of the clock-gating controls will be set as + * requested. Possible values for this parameter are: + * NV_OK + * This value indicates that all of the clock-gating control requests + * were either fulfilled or not supported on the hardware. + * NV_ERR_INVALID_REQUEST + * This value indicates that at least one of the clock-gating control + * requests were invalid given the MAXWELL_PROFILER instance's + * outstanding requests. + * NV_ERR_STATE_IN_USE + * This value indicates that at least one of the clock-gating controls + * has already been locked to a conflicting state by another + * MAXWELL_PROFILER instance or the RM itself. + * statusMask + * This parameter returns the status of the request to set each clock- + * gating control specified by the controlMask parameter. The fields are + * identical to those of the controlMask parameter. For each field for + * which the corresponding field in the controlMask parameter has the + * value NVB0CC_CTRL_POWER_FEATURE_MASK_*_IGNORE, the value is + * undefined. For each field for which the corresponding field in the + * controlMask parameter has the value + * NVB0CC_CTRL_POWER_FEATURE_MASK_*_REQUEST, the value will be + * one of the following: + * NVB0CC_CTRL_POWER_FEATURE_MASK_*_REQUEST_FULFILLED + * This value indicates that the clock-gating feature corresponding to + * the field in question was enabled or disabled according to the + * controlMask parameter, and the reference count for the feature was + * incremented accordingly. + * NVB0CC_CTRL_POWER_FEATURE_MASK_*_REQUEST_REJECTED + * This value indicates that the clock-gating feature corresponding to + * the field in question was not set to the expected state according + * to the controlMask parameter because another conflicting request is + * currently outstanding for the clock-gating feature. + * NVB0CC_CTRL_POWER_FEATURE_MASK_*_REQUEST_FAILED + * This value indicates that the clock-gating feature corresponding to + * the field in question was not set to the expected state according + * to the controlMask parameter because the attempt to do so failed + * with an error other than a conflicting request. + * NVB0CC_CTRL_POWER_FEATURE_MASK_*_REQUEST_NOT_SUPPORTED + * This value indicates that the clock-gating feature corresponding to + * the field in question is not supported on this GPU. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_ARGUMENT + */ +#define NVB0CC_CTRL_CMD_POWER_REQUEST_FEATURES (0xb0cc0301) /* finn: Evaluated from "(FINN_MAXWELL_PROFILER_POWER_INTERFACE_ID << 8) | NVB0CC_CTRL_POWER_REQUEST_FEATURES_PARAMS_MESSAGE_ID" */ + +#define NVB0CC_CTRL_POWER_REQUEST_FEATURES_PARAMS_MESSAGE_ID (0x1U) + +typedef struct NVB0CC_CTRL_POWER_REQUEST_FEATURES_PARAMS { + NvU32 globalStatus; + NvU32 controlMask; + NvU32 statusMask; +} NVB0CC_CTRL_POWER_REQUEST_FEATURES_PARAMS; + +/* valid fields for the controlMask and statusMask parameters */ +#define NVB0CC_CTRL_POWER_FEATURE_MASK_ELCG 1:0 +#define NVB0CC_CTRL_POWER_FEATURE_MASK_BLCG 3:2 +#define NVB0CC_CTRL_POWER_FEATURE_MASK_SLCG 5:4 + +/* + * The following are temporary fields for the controlMask and statusMask + * parameters. They are required to reference count their respective features + * until the existing RM controls can be safely updated, and the definitions + * for these features will be removed soon after that. + */ +#define NVB0CC_CTRL_POWER_FEATURE_MASK_ELPG 7:6 +#define NVB0CC_CTRL_POWER_FEATURE_MASK_IDLE_SLOWDOWN 9:8 +#define NVB0CC_CTRL_POWER_FEATURE_MASK_VAT 11:10 + +/* valid values for fields in the controlMask parameter */ +#define NVB0CC_CTRL_POWER_FEATURE_IGNORE (0x00000000) +#define NVB0CC_CTRL_POWER_FEATURE_DISABLE (0x00000001) +#define NVB0CC_CTRL_POWER_FEATURE_ENABLE (0x00000002) + +#define NVB0CC_CTRL_POWER_FEATURE_MASK_ELCG_IGNORE NVB0CC_CTRL_POWER_FEATURE_IGNORE +#define NVB0CC_CTRL_POWER_FEATURE_MASK_ELCG_DISABLE NVB0CC_CTRL_POWER_FEATURE_DISABLE +#define NVB0CC_CTRL_POWER_FEATURE_MASK_ELCG_ENABLE NVB0CC_CTRL_POWER_FEATURE_ENABLE +#define NVB0CC_CTRL_POWER_FEATURE_MASK_BLCG_IGNORE NVB0CC_CTRL_POWER_FEATURE_IGNORE +#define NVB0CC_CTRL_POWER_FEATURE_MASK_BLCG_DISABLE NVB0CC_CTRL_POWER_FEATURE_DISABLE +#define NVB0CC_CTRL_POWER_FEATURE_MASK_BLCG_ENABLE NVB0CC_CTRL_POWER_FEATURE_ENABLE +#define NVB0CC_CTRL_POWER_FEATURE_MASK_SLCG_IGNORE NVB0CC_CTRL_POWER_FEATURE_IGNORE +#define NVB0CC_CTRL_POWER_FEATURE_MASK_SLCG_DISABLE NVB0CC_CTRL_POWER_FEATURE_DISABLE +#define NVB0CC_CTRL_POWER_FEATURE_MASK_SLCG_ENABLE NVB0CC_CTRL_POWER_FEATURE_ENABLE +#define NVB0CC_CTRL_POWER_FEATURE_MASK_ELPG_IGNORE NVB0CC_CTRL_POWER_FEATURE_IGNORE +#define NVB0CC_CTRL_POWER_FEATURE_MASK_ELPG_DISABLE NVB0CC_CTRL_POWER_FEATURE_DISABLE +#define NVB0CC_CTRL_POWER_FEATURE_MASK_ELPG_ENABLE NVB0CC_CTRL_POWER_FEATURE_ENABLE +#define NVB0CC_CTRL_POWER_FEATURE_MASK_IDLE_SLOWDOWN_IGNORE NVB0CC_CTRL_POWER_FEATURE_IGNORE +#define NVB0CC_CTRL_POWER_FEATURE_MASK_IDLE_SLOWDOWN_DISABLE NVB0CC_CTRL_POWER_FEATURE_DISABLE +#define NVB0CC_CTRL_POWER_FEATURE_MASK_IDLE_SLOWDOWN_ENABLE NVB0CC_CTRL_POWER_FEATURE_ENABLE +#define NVB0CC_CTRL_POWER_FEATURE_MASK_VAT_IGNORE NVB0CC_CTRL_POWER_FEATURE_IGNORE +#define NVB0CC_CTRL_POWER_FEATURE_MASK_VAT_DISABLE NVB0CC_CTRL_POWER_FEATURE_DISABLE +#define NVB0CC_CTRL_POWER_FEATURE_MASK_VAT_ENABLE NVB0CC_CTRL_POWER_FEATURE_ENABLE +/* possible values for fields in the statusMask parameter */ +#define NVB0CC_CTRL_POWER_FEATURE_REQUEST_FULFILLED (0x00000000) +#define NVB0CC_CTRL_POWER_FEATURE_REQUEST_REJECTED (0x00000001) +#define NVB0CC_CTRL_POWER_FEATURE_REQUEST_NOT_SUPPORTED (0x00000002) +#define NVB0CC_CTRL_POWER_FEATURE_REQUEST_FAILED (0x00000003) + +#define NVB0CC_CTRL_POWER_FEATURE_MASK_BLCG_REQUEST_FULFILLED NVB0CC_CTRL_POWER_FEATURE_REQUEST_FULFILLED +#define NVB0CC_CTRL_POWER_FEATURE_MASK_BLCG_REQUEST_REJECTED NVB0CC_CTRL_POWER_FEATURE_REQUEST_REJECTED +#define NVB0CC_CTRL_POWER_FEATURE_MASK_BLCG_REQUEST_NOT_SUPPORTED NVB0CC_CTRL_POWER_FEATURE_REQUEST_NOT_SUPPORTED +#define NVB0CC_CTRL_POWER_FEATURE_MASK_BLCG_REQUEST_FAILED NVB0CC_CTRL_POWER_FEATURE_REQUEST_FAILED +#define NVB0CC_CTRL_POWER_FEATURE_MASK_ELCG_REQUEST_FULFILLED NVB0CC_CTRL_POWER_FEATURE_REQUEST_FULFILLED +#define NVB0CC_CTRL_POWER_FEATURE_MASK_ELCG_REQUEST_REJECTED NVB0CC_CTRL_POWER_FEATURE_REQUEST_REJECTED +#define NVB0CC_CTRL_POWER_FEATURE_MASK_ELCG_REQUEST_NOT_SUPPORTED NVB0CC_CTRL_POWER_FEATURE_REQUEST_NOT_SUPPORTED +#define NVB0CC_CTRL_POWER_FEATURE_MASK_ELCG_REQUEST_FAILED NVB0CC_CTRL_POWER_FEATURE_REQUEST_FAILED +#define NVB0CC_CTRL_POWER_FEATURE_MASK_SLCG_REQUEST_FULFILLED NVB0CC_CTRL_POWER_FEATURE_REQUEST_FULFILLED +#define NVB0CC_CTRL_POWER_FEATURE_MASK_SLCG_REQUEST_REJECTED NVB0CC_CTRL_POWER_FEATURE_REQUEST_REJECTED +#define NVB0CC_CTRL_POWER_FEATURE_MASK_SLCG_REQUEST_NOT_SUPPORTED NVB0CC_CTRL_POWER_FEATURE_REQUEST_NOT_SUPPORTED +#define NVB0CC_CTRL_POWER_FEATURE_MASK_SLCG_REQUEST_FAILED NVB0CC_CTRL_POWER_FEATURE_REQUEST_FAILED +#define NVB0CC_CTRL_POWER_FEATURE_MASK_ELPG_REQUEST_FULFILLED NVB0CC_CTRL_POWER_FEATURE_REQUEST_FULFILLED +#define NVB0CC_CTRL_POWER_FEATURE_MASK_ELPG_REQUEST_REJECTED NVB0CC_CTRL_POWER_FEATURE_REQUEST_REJECTED +#define NVB0CC_CTRL_POWER_FEATURE_MASK_ELPG_REQUEST_NOT_SUPPORTED NVB0CC_CTRL_POWER_FEATURE_REQUEST_NOT_SUPPORTED +#define NVB0CC_CTRL_POWER_FEATURE_MASK_ELPG_REQUEST_FAILED NVB0CC_CTRL_POWER_FEATURE_REQUEST_FAILED +#define NVB0CC_CTRL_POWER_FEATURE_MASK_IDLE_SLOWDOWN_REQUEST_FULFILLED NVB0CC_CTRL_POWER_FEATURE_REQUEST_FULFILLED +#define NVB0CC_CTRL_POWER_FEATURE_MASK_IDLE_SLOWDOWN_REQUEST_REJECTED NVB0CC_CTRL_POWER_FEATURE_REQUEST_REJECTED +#define NVB0CC_CTRL_POWER_FEATURE_MASK_IDLE_SLOWDOWN_REQUEST_NOT_SUPPORTED NVB0CC_CTRL_POWER_FEATURE_REQUEST_NOT_SUPPORTED +#define NVB0CC_CTRL_POWER_FEATURE_MASK_IDLE_SLOWDOWN_REQUEST_FAILED NVB0CC_CTRL_POWER_FEATURE_REQUEST_FAILED +#define NVB0CC_CTRL_POWER_FEATURE_MASK_VAT_REQUEST_FULFILLED NVB0CC_CTRL_POWER_FEATURE_REQUEST_FULFILLED +#define NVB0CC_CTRL_POWER_FEATURE_MASK_VAT_REQUEST_REJECTED NVB0CC_CTRL_POWER_FEATURE_REQUEST_REJECTED +#define NVB0CC_CTRL_POWER_FEATURE_MASK_VAT_REQUEST_NOT_SUPPORTED NVB0CC_CTRL_POWER_FEATURE_REQUEST_NOT_SUPPORTED +#define NVB0CC_CTRL_POWER_FEATURE_MASK_VAT_REQUEST_FAILED NVB0CC_CTRL_POWER_FEATURE_REQUEST_FAILED + +/* utility masks for the controlMask parameter for all controls */ +#define NVB0CC_CTRL_POWER_FEATURE_MASK_ALL \ + DRF_SHIFTMASK(NVB0CC_CTRL_POWER_FEATURE_MASK_ELCG) | \ + DRF_SHIFTMASK(NVB0CC_CTRL_POWER_FEATURE_MASK_BLCG) | \ + DRF_SHIFTMASK(NVB0CC_CTRL_POWER_FEATURE_MASK_SLCG) | \ + DRF_SHIFTMASK(NVB0CC_CTRL_POWER_FEATURE_MASK_ELPG) | \ + DRF_SHIFTMASK(NVB0CC_CTRL_POWER_FEATURE_MASK_IDLE_SLOWDOWN) | \ + DRF_SHIFTMASK(NVB0CC_CTRL_POWER_FEATURE_MASK_VAT) +#define NVB0CC_CTRL_POWER_FEATURE_MASK_ALL_IGNORE \ + DRF_DEF(B0CC, _CTRL_POWER_FEATURE_MASK, _ELCG, _IGNORE) | \ + DRF_DEF(B0CC, _CTRL_POWER_FEATURE_MASK, _BLCG, _IGNORE) | \ + DRF_DEF(B0CC, _CTRL_POWER_FEATURE_MASK, _SLCG, _IGNORE) | \ + DRF_DEF(B0CC, _CTRL_POWER_FEATURE_MASK, _ELPG, _IGNORE) | \ + DRF_DEF(B0CC, _CTRL_POWER_FEATURE_MASK, _IDLE_SLOWDOWN, _IGNORE) | \ + DRF_DEF(B0CC, _CTRL_POWER_FEATURE_MASK, _VAT, _IGNORE) +#define NVB0CC_CTRL_POWER_FEATURE_MASK_ALL_DISABLE \ + DRF_DEF(B0CC, _CTRL_POWER_FEATURE_MASK, _ELCG, _DISABLE) | \ + DRF_DEF(B0CC, _CTRL_POWER_FEATURE_MASK, _BLCG, _DISABLE) | \ + DRF_DEF(B0CC, _CTRL_POWER_FEATURE_MASK, _SLCG, _DISABLE) | \ + DRF_DEF(B0CC, _CTRL_POWER_FEATURE_MASK, _ELPG, _DISABLE) | \ + DRF_DEF(B0CC, _CTRL_POWER_FEATURE_MASK, _IDLE_SLOWDOWN, _DISABLE)| \ + DRF_DEF(B0CC, _CTRL_POWER_FEATURE_MASK, _VAT, _DISABLE) +#define NVB0CC_CTRL_POWER_FEATURE_MASK_ALL_ENABLE \ + DRF_DEF(B0CC, _CTRL_POWER_FEATURE_MASK, _ELCG, _ENABLE) | \ + DRF_DEF(B0CC, _CTRL_POWER_FEATURE_MASK, _BLCG, _ENABLE) | \ + DRF_DEF(B0CC, _CTRL_POWER_FEATURE_MASK, _SLCG, _ENABLE) | \ + DRF_DEF(B0CC, _CTRL_POWER_FEATURE_MASK, _ELPG, _ENABLE) | \ + DRF_DEF(B0CC, _CTRL_POWER_FEATURE_MASK, _IDLE_SLOWDOWN, _ENABLE) | \ + DRF_DEF(B0CC, _CTRL_POWER_FEATURE_MASK, _VAT, _ENABLE) + +/* + * NVB0CC_CTRL_CMD_POWER_RELEASE_FEATUERS + * + * This command releases the MAXWELL_PROFILER's request for the given clock- + * gating features that was previously created by the + * NVB0CC_CTRL_CMD_POWER_REQUEST_FEATURES command. If the MAXWELL_PROFILER + * object does not have an outstanding request to one or more of the given + * clock-gating features, those features will be ignored while the other + * feature requests will be released. + * + * After calling this command, the calling client may not rely on the current + * value of any of the released clock-gating features to remain, even if + * several identical requests for the given clock-gating features were made + * using NVB0CC_CTRL_CMD_POWER_REQUEST_FEATURES. The RM only reference- + * counts the settings requested by MAXWELL_PROFILER instances - it does not + * reference-count multiple identical requests made using the same + * MAXWELL_PROFILER instance. + * + * All outstanding requests made using this MAXWELL_PROFILER object are + * implicitly released when the MAXWELL_PROFILER is freed. + * + * controlMask + * This parameter indicates which clock-gating features the RM should + * release the MAXWELL_PROFILER's reference to. See + * NVB0CC_CTRL_CMD_POWER_REQUEST_FEATURES for valid fields. Valid + * values for each field are: + * NVB0CC_CTRL_POWER_FEATURE_MASK_ELCG_IGNORE + * NVB0CC_CTRL_POWER_FEATURE_MASK_BLCG_IGNORE + * NVB0CC_CTRL_POWER_FEATURE_MASK_SLCG_IGNORE + * NVB0CC_CTRL_POWER_FEATURE_MASK_ELPG_IGNORE + * NVB0CC_CTRL_POWER_FEATURE_MASK_IDLE_SLOWDOWN_IGNORE + * NVB0CC_CTRL_POWER_FEATURE_MASK_VAT_IGNORE + * This value indicates that the clock-gating feature associated with + * the field should not be released, even if the MAXWELL_PROFILER has an + * outstanding request for it. This will not affect the reference + * count for the feature. + * NVB0CC_CTRL_POWER_FEATURE_MASK_ELCG_RELEASE + * NVB0CC_CTRL_POWER_FEATURE_MASK_BLCG_RELEASE + * NVB0CC_CTRL_POWER_FEATURE_MASK_SLCG_RELEASE + * NVB0CC_CTRL_POWER_FEATURE_MASK_ELPG_RELEASE + * NVB0CC_CTRL_POWER_FEATURE_MASK_IDLE_SLOWDOWN_RELEASE + * NVB0CC_CTRL_POWER_FEATURE_MASK_VAT_RELEASE + * This value indicates that the MAXWELL_PROFILER's outstanding request + * for the clock-gating feature associated with the field should be + * released. This will decrement the reference count for the feature + * if the MAXWELL_PROFILER has an outstanding request for it. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_ARGUMENT + */ +#define NVB0CC_CTRL_CMD_POWER_RELEASE_FEATURES (0xb0cc0302) /* finn: Evaluated from "(FINN_MAXWELL_PROFILER_POWER_INTERFACE_ID << 8) | NVB0CC_CTRL_POWER_RELEASE_FEATURES_PARAMS_MESSAGE_ID" */ + +#define NVB0CC_CTRL_POWER_RELEASE_FEATURES_PARAMS_MESSAGE_ID (0x2U) + +typedef struct NVB0CC_CTRL_POWER_RELEASE_FEATURES_PARAMS { + NvU32 controlMask; +} NVB0CC_CTRL_POWER_RELEASE_FEATURES_PARAMS; + +/* + * valid values for the controlMask parameter in addition to + * NVB0CC_CTRL_POWER_FEATURE_MASK_*_IGNORE + */ +#define NVB0CC_CTRL_POWER_FEATURE_RELEASE (0x00000003) + +#define NVB0CC_CTRL_POWER_FEATURE_MASK_ELCG_RELEASE NVB0CC_CTRL_POWER_FEATURE_RELEASE +#define NVB0CC_CTRL_POWER_FEATURE_MASK_BLCG_RELEASE NVB0CC_CTRL_POWER_FEATURE_RELEASE +#define NVB0CC_CTRL_POWER_FEATURE_MASK_SLCG_RELEASE NVB0CC_CTRL_POWER_FEATURE_RELEASE +#define NVB0CC_CTRL_POWER_FEATURE_MASK_ELPG_RELEASE NVB0CC_CTRL_POWER_FEATURE_RELEASE +#define NVB0CC_CTRL_POWER_FEATURE_MASK_IDLE_SLOWDOWN_RELEASE NVB0CC_CTRL_POWER_FEATURE_RELEASE +#define NVB0CC_CTRL_POWER_FEATURE_MASK_VAT_RELEASE NVB0CC_CTRL_POWER_FEATURE_RELEASE + + +/* _ctrlb0ccpower_h_ */ + +/* utility mask for the controlMask parameter for all fields */ +#define NVB0CC_CTRL_POWER_FEATURE_MASK_ALL_RELEASE \ + DRF_DEF(B0CC, _CTRL_POWER_FEATURE_MASK, _ELCG, _RELEASE) | \ + DRF_DEF(B0CC, _CTRL_POWER_FEATURE_MASK, _BLCG, _RELEASE) | \ + DRF_DEF(B0CC, _CTRL_POWER_FEATURE_MASK, _SLCG, _RELEASE) | \ + DRF_DEF(B0CC, _CTRL_POWER_FEATURE_MASK, _ELPG, _RELEASE) | \ + DRF_DEF(B0CC, _CTRL_POWER_FEATURE_MASK, _IDLE_SLOWDOWN, _RELEASE)| \ + DRF_DEF(B0CC, _CTRL_POWER_FEATURE_MASK, _VAT, _RELEASE) diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/common/sdk/nvidia/inc/ctrl/ctrlb0cc/ctrlb0ccprofiler.h nvidia-open-gpu-kernel-modules-535.161.08/src/common/sdk/nvidia/inc/ctrl/ctrlb0cc/ctrlb0ccprofiler.h --- nvidia-open-gpu-kernel-modules-525.147.05/src/common/sdk/nvidia/inc/ctrl/ctrlb0cc/ctrlb0ccprofiler.h 2023-10-25 20:22:23.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/common/sdk/nvidia/inc/ctrl/ctrlb0cc/ctrlb0ccprofiler.h 2024-03-05 22:15:17.000000000 +0000 @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 2018-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2018-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -27,7 +27,7 @@ // // This file was generated with FINN, an NVIDIA coding tool. -// Source file: ctrl/ctrlb0cc/ctrlb0ccprofiler.finn +// Source file: ctrl/ctrlb0cc/ctrlb0ccprofiler.finn // #include "ctrl/ctrlb0cc/ctrlb0ccbase.h" @@ -109,7 +109,7 @@ * for streaming the updated bytes available in the buffer. * */ -#define NVB0CC_CTRL_CMD_ALLOC_PMA_STREAM (0xb0cc0105) /* finn: Evaluated from "(FINN_MAXWELL_PROFILER_PROFILER_INTERFACE_ID << 8) | 0x5" */ +#define NVB0CC_CTRL_CMD_ALLOC_PMA_STREAM (0xb0cc0105) /* finn: Evaluated from "(FINN_MAXWELL_PROFILER_PROFILER_INTERFACE_ID << 8) | NVB0CC_CTRL_ALLOC_PMA_STREAM_PARAMS_MESSAGE_ID" */ /*! * Defines the maximum size of PMA buffer for streamout. It can be up to 4GB minus one page @@ -118,6 +118,8 @@ #define NVB0CC_PMA_BUFFER_SIZE_MAX (0xffe00000ULL) /* finn: Evaluated from "(4 * 1024 * 1024 * 1024 - 2 * 1024 * 1024)" */ #define NVB0CC_PMA_BYTES_AVAILABLE_SIZE (0x1000) /* finn: Evaluated from "(4 * 1024)" */ +#define NVB0CC_CTRL_ALLOC_PMA_STREAM_PARAMS_MESSAGE_ID (0x5U) + typedef struct NVB0CC_CTRL_ALLOC_PMA_STREAM_PARAMS { /*! * [in] Memory handle (RW memory) for streaming records. @@ -181,6 +183,8 @@ NvU32 pmaChannelIdx; } NVB0CC_CTRL_FREE_PMA_STREAM_PARAMS; + + /*! * NVB0CC_CTRL_CMD_BIND_PM_RESOURCES * @@ -258,6 +262,11 @@ * [in] The PMA Channel Index associated with a given PMA stream. */ NvU32 pmaChannelIdx; + + /*! + * [out] Set to TRUE if PMA buffer has overflowed. + */ + NvBool bOverflowStatus; } NVB0CC_CTRL_PMA_STREAM_UPDATE_GET_PUT_PARAMS; /*! @@ -440,9 +449,7 @@ #define NVB0CC_MAX_CREDIT_INFO_ENTRIES (63) -#define NVB0CC_CTRL_SET_HS_CREDITS_PARAMS_MESSAGE_ID (0xEU) - -typedef struct NVB0CC_CTRL_SET_HS_CREDITS_PARAMS { +typedef struct NVB0CC_CTRL_HS_CREDITS_PARAMS { /*! * [in] The PMA Channel Index associated with a given PMA stream. */ @@ -462,7 +469,11 @@ * [in] Credit programming per chiplet */ NVB0CC_CTRL_PMA_STREAM_HS_CREDITS_INFO creditInfo[NVB0CC_MAX_CREDIT_INFO_ENTRIES]; -} NVB0CC_CTRL_SET_HS_CREDITS_PARAMS; +} NVB0CC_CTRL_HS_CREDITS_PARAMS; + +#define NVB0CC_CTRL_SET_HS_CREDITS_PARAMS_MESSAGE_ID (0xEU) + +typedef NVB0CC_CTRL_HS_CREDITS_PARAMS NVB0CC_CTRL_SET_HS_CREDITS_PARAMS; /*! * NVB0CC_CTRL_CMD_GET_HS_CREDITS @@ -470,10 +481,111 @@ * Gets per chiplet (pmm router) high speed streaming credits for a pma channel. * */ -#define NVB0CC_CTRL_CMD_GET_HS_CREDITS (0xb0cc010f) /* finn: Evaluated from "(FINN_MAXWELL_PROFILER_PROFILER_INTERFACE_ID << 8) | 0xF" */ +#define NVB0CC_CTRL_CMD_GET_HS_CREDITS (0xb0cc010f) /* finn: Evaluated from "(FINN_MAXWELL_PROFILER_PROFILER_INTERFACE_ID << 8) | NVB0CC_CTRL_GET_HS_CREDITS_PARAMS_MESSAGE_ID" */ + +#define NVB0CC_CTRL_GET_HS_CREDITS_PARAMS_MESSAGE_ID (0xFU) + +typedef NVB0CC_CTRL_HS_CREDITS_PARAMS NVB0CC_CTRL_GET_HS_CREDITS_PARAMS; + + + +typedef enum NVB0CC_CTRL_HES_TYPE { + NVB0CC_CTRL_HES_INVALID = 0, + NVB0CC_CTRL_HES_CWD = 1, +} NVB0CC_CTRL_HES_TYPE; + +typedef struct NVB0CC_CTRL_RESERVE_HES_CWD_PARAMS { + /*! + * [in] Enable ctxsw for HES_CWD. + */ + NvBool ctxsw; +} NVB0CC_CTRL_RESERVE_HES_CWD_PARAMS; + +/* + * NVB0CC_CTRL_HES_RESERVATION_UNION + * + * Union of all HES reservation params + * + */ +typedef union NVB0CC_CTRL_HES_RESERVATION_UNION { + NVB0CC_CTRL_RESERVE_HES_CWD_PARAMS cwd; +} NVB0CC_CTRL_HES_RESERVATION_UNION; + +/*! + * NVB0CC_CTRL_CMD_RESERVE_HES + * + * Reserves HES for use by the calling client. + * This PM system will only be accessible if this reservation is + * taken. + * + * This reservation can be released with @ref NVB0CC_CTRL_CMD_RELEASE_HES. + * + * Reservation scope and rules are same as for @ref NVB0CC_CTRL_CMD_RESERVE_HWPM_LEGACY. + * + */ +#define NVB0CC_CTRL_CMD_RESERVE_HES (0xb0cc0113) /* finn: Evaluated from "(FINN_MAXWELL_PROFILER_PROFILER_INTERFACE_ID << 8) | NVB0CC_CTRL_RESERVE_HES_PARAMS_MESSAGE_ID" */ + +#define NVB0CC_CTRL_RESERVE_HES_PARAMS_MESSAGE_ID (0x13U) + +typedef struct NVB0CC_CTRL_RESERVE_HES_PARAMS { + /*! + * [in] Denotes the HES reservation type. Choose from @NVB0CC_CTRL_HES_TYPE. + */ + NvU32 type; -typedef NVB0CC_CTRL_SET_HS_CREDITS_PARAMS NVB0CC_CTRL_GET_HS_CREDITS_PARAMS; + /*! + * [in] Union of all possible reserve param structs. Initialize the reserveParams corresponding to the chosen type. + */ + NVB0CC_CTRL_HES_RESERVATION_UNION reserveParams; +} NVB0CC_CTRL_RESERVE_HES_PARAMS; + +/*! + * NVB0CC_CTRL_CMD_RELEASE_HES + * + * Releases the reservation taken with @ref NVB0CC_CTRL_CMD_RESERVE_HES. + * + */ +#define NVB0CC_CTRL_CMD_RELEASE_HES (0xb0cc0114) /* finn: Evaluated from "(FINN_MAXWELL_PROFILER_PROFILER_INTERFACE_ID << 8) | NVB0CC_CTRL_RELEASE_HES_PARAMS_MESSAGE_ID" */ +#define NVB0CC_CTRL_RELEASE_HES_PARAMS_MESSAGE_ID (0x14U) +typedef struct NVB0CC_CTRL_RELEASE_HES_PARAMS { + /*! + * [in] type of @NVB0CC_CTRL_HES_TYPE needs to be released. + */ + NVB0CC_CTRL_HES_TYPE type; +} NVB0CC_CTRL_RELEASE_HES_PARAMS; + +/*! + * NVB0CC_CTRL_CMD_DISABLE_DYNAMIC_MMA_BOOST + * + * Disable the Dynamic MMA clock boost during profiler lifetime. + * + */ +#define NVB0CC_CTRL_CMD_DISABLE_DYNAMIC_MMA_BOOST (0xb0cc0117) /* finn: Evaluated from "(FINN_MAXWELL_PROFILER_PROFILER_INTERFACE_ID << 8) | NVB0CC_CTRL_DISABLE_DYNAMIC_MMA_BOOST_PARAMS_MESSAGE_ID" */ +#define NVB0CC_CTRL_DISABLE_DYNAMIC_MMA_BOOST_PARAMS_MESSAGE_ID (0x17U) + +typedef struct NVB0CC_CTRL_DISABLE_DYNAMIC_MMA_BOOST_PARAMS { + /*! + * [in]: En/Disable Dynamic MMA Boost. True = disable Boost; False = re-enable Boost. + */ + NvBool disable; +} NVB0CC_CTRL_DISABLE_DYNAMIC_MMA_BOOST_PARAMS; + +/*! + * NVB0CC_CTRL_CMD_GET_DYNAMIC_MMA_BOOST_STATUS + * + * Request the Dynamic MMA clock boost feature enablement status. + * + */ +#define NVB0CC_CTRL_CMD_GET_DYNAMIC_MMA_BOOST_STATUS (0xb0cc0118) /* finn: Evaluated from "(FINN_MAXWELL_PROFILER_PROFILER_INTERFACE_ID << 8) | NVB0CC_CTRL_GET_DYNAMIC_MMA_BOOST_STATUS_PARAMS_MESSAGE_ID" */ +#define NVB0CC_CTRL_GET_DYNAMIC_MMA_BOOST_STATUS_PARAMS_MESSAGE_ID (0x18U) + +typedef struct NVB0CC_CTRL_GET_DYNAMIC_MMA_BOOST_STATUS_PARAMS { + /*! + * [out]: Dynamic MMA Boost status: true = boost enabled/available; False = Boost disabled/unavailable. + */ + NvBool enabled; +} NVB0CC_CTRL_GET_DYNAMIC_MMA_BOOST_STATUS_PARAMS; /* _ctrlb0ccprofiler_h_ */ diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/common/sdk/nvidia/inc/ctrl/ctrlb0cc.h nvidia-open-gpu-kernel-modules-535.161.08/src/common/sdk/nvidia/inc/ctrl/ctrlb0cc.h --- nvidia-open-gpu-kernel-modules-525.147.05/src/common/sdk/nvidia/inc/ctrl/ctrlb0cc.h 2023-10-25 20:22:23.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/common/sdk/nvidia/inc/ctrl/ctrlb0cc.h 2024-03-05 22:15:17.000000000 +0000 @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 2018-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2018-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -25,7 +25,7 @@ // // This file was generated with FINN, an NVIDIA coding tool. -// Source file: ctrl/ctrlb0cc.finn +// Source file: ctrl/ctrlb0cc.finn // @@ -35,3 +35,363 @@ #include "ctrl/ctrl2080/ctrl2080gpu.h" // NV2080_CTRL_GPU_REG_OP #include "ctrlb0cc/ctrlb0ccprofiler.h" #include "ctrlb0cc/ctrlb0ccinternal.h" +#include "ctrlb0cc/ctrlb0ccpower.h" + +/* + * NVB0CC_CTRL_CMD_PROFILER_REQUEST_CG_CONTROLS + * + * This command attempts to enable or disable various clock-gating features of + * the GPU on behalf of the profiler. If this command is unable to set the + * clock-gating feature state of any of the requested features, this command + * will fail and none of the requested features will be modified. If this + * command fails because one or more clock-gating feature requests were + * rejected, it will return NV_ERR_STATE_IN_USE in the globalStatus + * parameter and the fields in the statusMask parameter for the features for + * which the requests were rejected will have the value + * NVB0CC_CTRL_PROFILER_CG_CONTROL_MASK_*_REQUEST_REJECTED. + * If a given feature is not supported on the GPU, the field for that clock- + * gating feature will have the value + * NVB0CC_CTRL_PROFILER_CG_CONTROL_MASK_*_REQUEST_NOT_SUPPORTED in the + * statusMask parameter, but this condition by itself will not cause the + * command to fail. Even if this command fails, the field for clock-gating + * features which would have successfully changed will have the value + * NVB0CC_CTRL_PROFILER_CG_CONTROL_MASK_*_FULFILLED in the statusMask + * parameter. + * + * Each of the clock-gating features is reference-counted individually, so + * that multiple MAXWELL_PROFILER objects may request and rely on the same + * settings for the features simultaneously. Each clock-gating feature is + * locked to the requested state until the MAXWELL_PROFILER object is freed or + * the NVB0CC_CTRL_CMD_PROFILER_RELEASE_CG_CONTROLS command is called for that + * feature. + * + * Currently, only MAXWELL_PROFILER requests for power features using this + * command are reference counted. Changes to the power feature settings made + * either by other control commands or the RM itself may interfere with the + * settings requested by MAXWELL_PROFILER instances. + * + * This command will always return NV_OK when given valid + * parameters. If there is any other failure that prevents the clock-gating + * features from being set appropriately, the globalStatus parameter will + * indicate this and the statusMask parameter will indicate which clock-gating + * feature requests failed and why. + * + * controlMask + * This parameter indicates which clock-gating features the request should + * apply to. This parameter has the following fields: + * NVB0CC_CTRL_PROFILER_CG_CONTROL_MASK_ELCG + * The value of this field indicates whether this request should apply + * to engine-level clock-gating of the GR engine. Valid values for + * this field are: + * NVB0CC_CTRL_PROFILER_CG_CONTROL_MASK_ELCG_IGNORE + * This value indicates that the GR engine-level clock-gating + * should be ignored. This will not affect the reference count for + * this feature. + * NVB0CC_CTRL_PROFILER_CG_CONTROL_MASK_ELCG_DISABLE + * This value indicates that the GR engine-level clock-gating + * should be disabled. + * NVB0CC_CTRL_PROFILER_CG_CONTROL_MASK_ELCG_ENABLE + * This value indicates that the GR engine-level clock-gating + * should be enabled. + * NVB0CC_CTRL_PROFILER_CG_CONTROL_MASK_BLCG + * The value of this field indicates whether this request should apply + * to block-level clock-gating. Valid values for this field are: + * NVB0CC_CTRL_PROFILER_CG_CONTROL_MASK_BLCG_IGNORE + * This value indicates that block-level clock-gating should be + * ignored. This will not affect the reference count for this + * feature. + * NVB0CC_CTRL_PROFILER_CG_CONTROL_MASK_BLCG_DISABLE + * This value indicates that block-level clock-gating should be + * disabled. + * NVB0CC_CTRL_PROFILER_CG_CONTROL_MASK_BLCG_ENABLE + * This value indicates that block-level clock-gating should be + * enabled. + * NVB0CC_CTRL_PROFILER_CG_CONTROL_MASK_SLCG + * The value of this field indicates whether this request should apply + * to second-level clock-gating. Valid values for this field are: + * NVB0CC_CTRL_PROFILER_CG_CONTROL_MASK_SLCG_IGNORE + * This value indicates that second-level clock-gating should be + * ignored. This will not affect the reference count for this + * feature. + * NVB0CC_CTRL_PROFILER_CG_CONTROL_MASK_SLCG_DISABLE + * This value indicates that second-level clock-gating should be + * disabled. + * NVB0CC_CTRL_PROFILER_CG_CONTROL_MASK_SLCG_ENABLE + * This value indicates that second-level clock-gating should be + * enabled. + * NVB0CC_CTRL_PROFILER_CG_CONTROL_MASK_ELPG + * The value of this field indicates whether this request should apply + * to GR engine-level power-gating. Valid values for this field are: + * NVB0CC_CTRL_PROFILER_CG_CONTROL_MASK_ELPG_IGNORE + * This value indicates that engine-level power-gating should be + * ignored. This will not affect the reference count for this + * feature. + * NVB0CC_CTRL_PROFILER_CG_CONTROL_MASK_ELPG_DISABLE + * This value indicates that engine-level power-gating should be + * disabled. + * NVB0CC_CTRL_PROFILER_CG_CONTROL_MASK_ELPG_ENABLE + * This value indicates that engine-level power-gating should be + * enabled. + * Note that this field is only temporary to allow reference counting + * restricted to MAXWELL_PROFILER instances, until the time when the + * existing controls for this power feature can be updated to support + * reference counting across all clients and the RM. + * NVB0CC_CTRL_PROFILER_CG_CONTROL_MASK_IDLE_SLOWDOWN + * The value of this field indicates whether this request should apply + * to SM idle slowdown. Valid values for this field are: + * NVB0CC_CTRL_PROFILER_CG_CONTROL_MASK_IDLE_SLOWDOWN_IGNORE + * This value indicates that SM idle slowdown should be ignored. + * This will not affect the reference count for this feature. + * NVB0CC_CTRL_PROFILER_CG_CONTROL_MASK_IDLE_SLOWDOWN_DISABLE + * This value indicates that SM idle slowdown should be disabled. + * NVB0CC_CTRL_PROFILER_CG_CONTROL_MASK_IDLE_SLOWDOWN_ENABLE + * This value indicates that SM idle slowdown should be enabled. + * Note that this field is only temporary to allow reference counting + * restricted to MAXWELL_PROFILER instances, until the time when the + * existing controls for this power feature can be updated to support + * reference counting across all clients and the RM. + * NVB0CC_CTRL_PROFILER_CG_CONTROL_MASK_VAT + * The value of this field indicates whether this request should apply + * to VAT. Valid values for this field are: + * NVB0CC_CTRL_PROFILER_CG_CONTROL_MASK_VAT_IGNORE + * This value indicates that VAT should be ignored. + * This will not affect the reference count for this feature. + * NVB0CC_CTRL_PROFILER_CG_CONTROL_MASK_VAT_DISABLE + * This value indicates that VAT should be disabled. + * NVB0CC_CTRL_PROFILER_CG_CONTROL_MASK_VAT_ENABLE + * This value indicates that VAT should be enabled. + * Note that this field is only temporary to allow reference counting + * restricted to MAXWELL_PROFILER instances, until the time when the + * existing controls for this power feature can be updated to support + * reference counting across all clients and the RM. + * globalStatus + * This parameter returns the overall status of the requests for all + * clock-gating controls. If the value of this parameter is not + * NV_OK, none of the clock-gating controls will be set as + * requested. Possible values for this parameter are: + * NV_OK + * This value indicates that all of the clock-gating control requests + * were either fulfilled or not supported on the hardware. + * NV_ERR_INVALID_REQUEST + * This value indicates that at least one of the clock-gating control + * requests were invalid given the MAXWELL_PROFILER instance's + * outstanding requests. + * NV_ERR_STATE_IN_USE + * This value indicates that at least one of the clock-gating controls + * has already been locked to a conflicting state by another + * MAXWELL_PROFILER instance or the RM itself. + * statusMask + * This parameter returns the status of the request to set each clock- + * gating control specified by the controlMask parameter. The fields are + * identical to those of the controlMask parameter. For each field for + * which the corresponding field in the controlMask parameter has the + * value NVB0CC_CTRL_PROFILER_CG_CONTROL_MASK_*_IGNORE, the value is + * undefined. For each field for which the corresponding field in the + * controlMask parameter has the value + * NVB0CC_CTRL_PROFILER_CG_CONTROL_MASK_*_REQUEST, the value will be + * one of the following: + * NVB0CC_CTRL_PROFILER_CG_CONTROL_MASK_*_REQUEST_FULFILLED + * This value indicates that the clock-gating feature corresponding to + * the field in question was enabled or disabled according to the + * controlMask parameter, and the reference count for the feature was + * incremented accordingly. + * NVB0CC_CTRL_PROFILER_CG_CONTROL_MASK_*_REQUEST_REJECTED + * This value indicates that the clock-gating feature corresponding to + * the field in question was not set to the expected state according + * to the controlMask parameter because another conflicting request is + * currently outstanding for the clock-gating feature. + * NVB0CC_CTRL_PROFILER_CG_CONTROL_MASK_*_REQUEST_FAILED + * This value indicates that the clock-gating feature corresponding to + * the field in question was not set to the expected state according + * to the controlMask parameter because the attempt to do so failed + * with an error other than a conflicting request. + * NVB0CC_CTRL_PROFILER_CG_CONTROL_MASK_*_REQUEST_NOT_SUPPORTED + * This value indicates that the clock-gating feature corresponding to + * the field in question is not supported on this GPU. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_ARGUMENT + */ +#define NVB0CC_CTRL_CMD_PROFILER_REQUEST_CG_CONTROLS NVB0CC_CTRL_CMD_POWER_REQUEST_FEATURES + +typedef NVB0CC_CTRL_POWER_REQUEST_FEATURES_PARAMS NVB0CC_CTRL_PROFILER_REQUEST_CG_CONTROLS_PARAMS; + +/* valid fields for the controlMask and statusMask parameters */ +#define NVB0CC_CTRL_PROFILER_CG_CONTROL_MASK_ELCG 1:0 +#define NVB0CC_CTRL_PROFILER_CG_CONTROL_MASK_BLCG 3:2 +#define NVB0CC_CTRL_PROFILER_CG_CONTROL_MASK_SLCG 5:4 + +/* + * The following are temporary fields for the controlMask and statusMask + * parameters. They are required to reference count their respective features + * until the existing RM controls can be safely updated, and the definitions + * for these features will be removed soon after that. + */ +#define NVB0CC_CTRL_PROFILER_CG_CONTROL_MASK_ELPG 7:6 +#define NVB0CC_CTRL_PROFILER_CG_CONTROL_MASK_IDLE_SLOWDOWN 9:8 +#define NVB0CC_CTRL_PROFILER_CG_CONTROL_MASK_VAT 11:10 + +/* valid values for fields in the controlMask parameter */ +#define NVB0CC_CTRL_PROFILER_CG_CONTROL_IGNORE (0x00000000) +#define NVB0CC_CTRL_PROFILER_CG_CONTROL_DISABLE (0x00000001) +#define NVB0CC_CTRL_PROFILER_CG_CONTROL_ENABLE (0x00000002) + +#define NVB0CC_CTRL_PROFILER_CG_CONTROL_MASK_ELCG_IGNORE NVB0CC_CTRL_PROFILER_CG_CONTROL_IGNORE +#define NVB0CC_CTRL_PROFILER_CG_CONTROL_MASK_ELCG_DISABLE NVB0CC_CTRL_PROFILER_CG_CONTROL_DISABLE +#define NVB0CC_CTRL_PROFILER_CG_CONTROL_MASK_ELCG_ENABLE NVB0CC_CTRL_PROFILER_CG_CONTROL_ENABLE +#define NVB0CC_CTRL_PROFILER_CG_CONTROL_MASK_BLCG_IGNORE NVB0CC_CTRL_PROFILER_CG_CONTROL_IGNORE +#define NVB0CC_CTRL_PROFILER_CG_CONTROL_MASK_BLCG_DISABLE NVB0CC_CTRL_PROFILER_CG_CONTROL_DISABLE +#define NVB0CC_CTRL_PROFILER_CG_CONTROL_MASK_BLCG_ENABLE NVB0CC_CTRL_PROFILER_CG_CONTROL_ENABLE +#define NVB0CC_CTRL_PROFILER_CG_CONTROL_MASK_SLCG_IGNORE NVB0CC_CTRL_PROFILER_CG_CONTROL_IGNORE +#define NVB0CC_CTRL_PROFILER_CG_CONTROL_MASK_SLCG_DISABLE NVB0CC_CTRL_PROFILER_CG_CONTROL_DISABLE +#define NVB0CC_CTRL_PROFILER_CG_CONTROL_MASK_SLCG_ENABLE NVB0CC_CTRL_PROFILER_CG_CONTROL_ENABLE +#define NVB0CC_CTRL_PROFILER_CG_CONTROL_MASK_ELPG_IGNORE NVB0CC_CTRL_PROFILER_CG_CONTROL_IGNORE +#define NVB0CC_CTRL_PROFILER_CG_CONTROL_MASK_ELPG_DISABLE NVB0CC_CTRL_PROFILER_CG_CONTROL_DISABLE +#define NVB0CC_CTRL_PROFILER_CG_CONTROL_MASK_ELPG_ENABLE NVB0CC_CTRL_PROFILER_CG_CONTROL_ENABLE +#define NVB0CC_CTRL_PROFILER_CG_CONTROL_MASK_IDLE_SLOWDOWN_IGNORE NVB0CC_CTRL_PROFILER_CG_CONTROL_IGNORE +#define NVB0CC_CTRL_PROFILER_CG_CONTROL_MASK_IDLE_SLOWDOWN_DISABLE NVB0CC_CTRL_PROFILER_CG_CONTROL_DISABLE +#define NVB0CC_CTRL_PROFILER_CG_CONTROL_MASK_IDLE_SLOWDOWN_ENABLE NVB0CC_CTRL_PROFILER_CG_CONTROL_ENABLE +#define NVB0CC_CTRL_PROFILER_CG_CONTROL_MASK_VAT_IGNORE NVB0CC_CTRL_PROFILER_CG_CONTROL_IGNORE +#define NVB0CC_CTRL_PROFILER_CG_CONTROL_MASK_VAT_DISABLE NVB0CC_CTRL_PROFILER_CG_CONTROL_DISABLE +#define NVB0CC_CTRL_PROFILER_CG_CONTROL_MASK_VAT_ENABLE NVB0CC_CTRL_PROFILER_CG_CONTROL_ENABLE +/* possible values for fields in the statusMask parameter */ +#define NVB0CC_CTRL_PROFILER_CG_CONTROL_REQUEST_FULFILLED (0x00000000) +#define NVB0CC_CTRL_PROFILER_CG_CONTROL_REQUEST_REJECTED (0x00000001) +#define NVB0CC_CTRL_PROFILER_CG_CONTROL_REQUEST_NOT_SUPPORTED (0x00000002) +#define NVB0CC_CTRL_PROFILER_CG_CONTROL_REQUEST_FAILED (0x00000003) + +#define NVB0CC_CTRL_PROFILER_CG_CONTROL_MASK_BLCG_REQUEST_FULFILLED NVB0CC_CTRL_PROFILER_CG_CONTROL_REQUEST_FULFILLED +#define NVB0CC_CTRL_PROFILER_CG_CONTROL_MASK_BLCG_REQUEST_REJECTED NVB0CC_CTRL_PROFILER_CG_CONTROL_REQUEST_REJECTED +#define NVB0CC_CTRL_PROFILER_CG_CONTROL_MASK_BLCG_REQUEST_NOT_SUPPORTED NVB0CC_CTRL_PROFILER_CG_CONTROL_REQUEST_NOT_SUPPORTED +#define NVB0CC_CTRL_PROFILER_CG_CONTROL_MASK_BLCG_REQUEST_FAILED NVB0CC_CTRL_PROFILER_CG_CONTROL_REQUEST_FAILED +#define NVB0CC_CTRL_PROFILER_CG_CONTROL_MASK_ELCG_REQUEST_FULFILLED NVB0CC_CTRL_PROFILER_CG_CONTROL_REQUEST_FULFILLED +#define NVB0CC_CTRL_PROFILER_CG_CONTROL_MASK_ELCG_REQUEST_REJECTED NVB0CC_CTRL_PROFILER_CG_CONTROL_REQUEST_REJECTED +#define NVB0CC_CTRL_PROFILER_CG_CONTROL_MASK_ELCG_REQUEST_NOT_SUPPORTED NVB0CC_CTRL_PROFILER_CG_CONTROL_REQUEST_NOT_SUPPORTED +#define NVB0CC_CTRL_PROFILER_CG_CONTROL_MASK_ELCG_REQUEST_FAILED NVB0CC_CTRL_PROFILER_CG_CONTROL_REQUEST_FAILED +#define NVB0CC_CTRL_PROFILER_CG_CONTROL_MASK_SLCG_REQUEST_FULFILLED NVB0CC_CTRL_PROFILER_CG_CONTROL_REQUEST_FULFILLED +#define NVB0CC_CTRL_PROFILER_CG_CONTROL_MASK_SLCG_REQUEST_REJECTED NVB0CC_CTRL_PROFILER_CG_CONTROL_REQUEST_REJECTED +#define NVB0CC_CTRL_PROFILER_CG_CONTROL_MASK_SLCG_REQUEST_NOT_SUPPORTED NVB0CC_CTRL_PROFILER_CG_CONTROL_REQUEST_NOT_SUPPORTED +#define NVB0CC_CTRL_PROFILER_CG_CONTROL_MASK_SLCG_REQUEST_FAILED NVB0CC_CTRL_PROFILER_CG_CONTROL_REQUEST_FAILED +#define NVB0CC_CTRL_PROFILER_CG_CONTROL_MASK_ELPG_REQUEST_FULFILLED NVB0CC_CTRL_PROFILER_CG_CONTROL_REQUEST_FULFILLED +#define NVB0CC_CTRL_PROFILER_CG_CONTROL_MASK_ELPG_REQUEST_REJECTED NVB0CC_CTRL_PROFILER_CG_CONTROL_REQUEST_REJECTED +#define NVB0CC_CTRL_PROFILER_CG_CONTROL_MASK_ELPG_REQUEST_NOT_SUPPORTED NVB0CC_CTRL_PROFILER_CG_CONTROL_REQUEST_NOT_SUPPORTED +#define NVB0CC_CTRL_PROFILER_CG_CONTROL_MASK_ELPG_REQUEST_FAILED NVB0CC_CTRL_PROFILER_CG_CONTROL_REQUEST_FAILED +#define NVB0CC_CTRL_PROFILER_CG_CONTROL_MASK_IDLE_SLOWDOWN_REQUEST_FULFILLED NVB0CC_CTRL_PROFILER_CG_CONTROL_REQUEST_FULFILLED +#define NVB0CC_CTRL_PROFILER_CG_CONTROL_MASK_IDLE_SLOWDOWN_REQUEST_REJECTED NVB0CC_CTRL_PROFILER_CG_CONTROL_REQUEST_REJECTED +#define NVB0CC_CTRL_PROFILER_CG_CONTROL_MASK_IDLE_SLOWDOWN_REQUEST_NOT_SUPPORTED NVB0CC_CTRL_PROFILER_CG_CONTROL_REQUEST_NOT_SUPPORTED +#define NVB0CC_CTRL_PROFILER_CG_CONTROL_MASK_IDLE_SLOWDOWN_REQUEST_FAILED NVB0CC_CTRL_PROFILER_CG_CONTROL_REQUEST_FAILED +#define NVB0CC_CTRL_PROFILER_CG_CONTROL_MASK_VAT_REQUEST_FULFILLED NVB0CC_CTRL_PROFILER_CG_CONTROL_REQUEST_FULFILLED +#define NVB0CC_CTRL_PROFILER_CG_CONTROL_MASK_VAT_REQUEST_REJECTED NVB0CC_CTRL_PROFILER_CG_CONTROL_REQUEST_REJECTED +#define NVB0CC_CTRL_PROFILER_CG_CONTROL_MASK_VAT_REQUEST_NOT_SUPPORTED NVB0CC_CTRL_PROFILER_CG_CONTROL_REQUEST_NOT_SUPPORTED +#define NVB0CC_CTRL_PROFILER_CG_CONTROL_MASK_VAT_REQUEST_FAILED NVB0CC_CTRL_PROFILER_CG_CONTROL_REQUEST_FAILED + +/* utility masks for the controlMask parameter for all controls */ +#define NVB0CC_CTRL_PROFILER_CG_CONTROL_MASK_ALL \ + DRF_SHIFTMASK(NVB0CC_CTRL_PROFILER_CG_CONTROL_MASK_ELCG) | \ + DRF_SHIFTMASK(NVB0CC_CTRL_PROFILER_CG_CONTROL_MASK_BLCG) | \ + DRF_SHIFTMASK(NVB0CC_CTRL_PROFILER_CG_CONTROL_MASK_SLCG) | \ + DRF_SHIFTMASK(NVB0CC_CTRL_PROFILER_CG_CONTROL_MASK_ELPG) | \ + DRF_SHIFTMASK(NVB0CC_CTRL_PROFILER_CG_CONTROL_MASK_IDLE_SLOWDOWN) | \ + DRF_SHIFTMASK(NVB0CC_CTRL_PROFILER_CG_CONTROL_MASK_VAT) +#define NVB0CC_CTRL_PROFILER_CG_CONTROL_MASK_ALL_IGNORE \ + DRF_DEF(B0CC, _CTRL_PROFILER_CG_CONTROL_MASK, _ELCG, _IGNORE) | \ + DRF_DEF(B0CC, _CTRL_PROFILER_CG_CONTROL_MASK, _BLCG, _IGNORE) | \ + DRF_DEF(B0CC, _CTRL_PROFILER_CG_CONTROL_MASK, _SLCG, _IGNORE) | \ + DRF_DEF(B0CC, _CTRL_PROFILER_CG_CONTROL_MASK, _ELPG, _IGNORE) | \ + DRF_DEF(B0CC, _CTRL_PROFILER_CG_CONTROL_MASK, _IDLE_SLOWDOWN, _IGNORE) | \ + DRF_DEF(B0CC, _CTRL_PROFILER_CG_CONTROL_MASK, _VAT, _IGNORE) +#define NVB0CC_CTRL_PROFILER_CG_CONTROL_MASK_ALL_DISABLE \ + DRF_DEF(B0CC, _CTRL_PROFILER_CG_CONTROL_MASK, _ELCG, _DISABLE) | \ + DRF_DEF(B0CC, _CTRL_PROFILER_CG_CONTROL_MASK, _BLCG, _DISABLE) | \ + DRF_DEF(B0CC, _CTRL_PROFILER_CG_CONTROL_MASK, _SLCG, _DISABLE) | \ + DRF_DEF(B0CC, _CTRL_PROFILER_CG_CONTROL_MASK, _ELPG, _DISABLE) | \ + DRF_DEF(B0CC, _CTRL_PROFILER_CG_CONTROL_MASK, _IDLE_SLOWDOWN, _DISABLE)| \ + DRF_DEF(B0CC, _CTRL_PROFILER_CG_CONTROL_MASK, _VAT, _DISABLE) +#define NVB0CC_CTRL_PROFILER_CG_CONTROL_MASK_ALL_ENABLE \ + DRF_DEF(B0CC, _CTRL_PROFILER_CG_CONTROL_MASK, _ELCG, _ENABLE) | \ + DRF_DEF(B0CC, _CTRL_PROFILER_CG_CONTROL_MASK, _BLCG, _ENABLE) | \ + DRF_DEF(B0CC, _CTRL_PROFILER_CG_CONTROL_MASK, _SLCG, _ENABLE) | \ + DRF_DEF(B0CC, _CTRL_PROFILER_CG_CONTROL_MASK, _ELPG, _ENABLE) | \ + DRF_DEF(B0CC, _CTRL_PROFILER_CG_CONTROL_MASK, _IDLE_SLOWDOWN, _ENABLE) | \ + DRF_DEF(B0CC, _CTRL_PROFILER_CG_CONTROL_MASK, _VAT, _ENABLE) + +/* + * NVB0CC_CTRL_CMD_PROFILER_RELEASE_CG_CONTROLS + * + * This command is deprecated; please us + * NVB0CC_CTRL_CMD_POWER_RELEASE_FEATURES. + * + * This command releases the MAXWELL_PROFILER's request for the given clock- + * gating features that was previously created by the + * NVB0CC_CTRL_CMD_PROFILER_REQUEST_CG_CONTROLS command. If the MAXWELL_PROFILER + * object does not have an outstanding request to one or more of the given + * clock-gating features, those features will be ignored while the other + * feature requests will be released. + * + * After calling this command, the calling client may not rely on the current + * value of any of the released clock-gating features to remain, even if + * several identical requests for the given clock-gating features were made + * using NVB0CC_CTRL_CMD_PROFILER_REQUEST_CG_CONTROLS. The RM only reference- + * counts the settings requested by MAXWELL_PROFILER instances - it does not + * reference-count multiple identical requests made using the same + * MAXWELL_PROFILER instance. + * + * All outstanding requests made using this MAXWELL_PROFILER object are + * implicitly released when the MAXWELL_PROFILER is freed. + * + * controlMask + * This parameter indicates which clock-gating features the RM should + * release the MAXWELL_PROFILER's reference to. See + * NVB0CC_CTRL_CMD_PROFILER_REQUEST_CG_CONTROLS for valid fields. Valid + * values for each field are: + * NVB0CC_CTRL_PROFILER_CG_CONTROL_MASK_ELCG_IGNORE + * NVB0CC_CTRL_PROFILER_CG_CONTROL_MASK_BLCG_IGNORE + * NVB0CC_CTRL_PROFILER_CG_CONTROL_MASK_SLCG_IGNORE + * NVB0CC_CTRL_PROFILER_CG_CONTROL_MASK_ELPG_IGNORE + * NVB0CC_CTRL_PROFILER_CG_CONTROL_MASK_IDLE_SLOWDOWN_IGNORE + * NVB0CC_CTRL_PROFILER_CG_CONTROL_MASK_VAT_IGNORE + * This value indicates that the clock-gating feature associated with + * the field should not be released, even if the MAXWELL_PROFILER has an + * outstanding request for it. This will not affect the reference + * count for the feature. + * NVB0CC_CTRL_PROFILER_CG_CONTROL_MASK_ELCG_RELEASE + * NVB0CC_CTRL_PROFILER_CG_CONTROL_MASK_BLCG_RELEASE + * NVB0CC_CTRL_PROFILER_CG_CONTROL_MASK_SLCG_RELEASE + * NVB0CC_CTRL_PROFILER_CG_CONTROL_MASK_ELPG_RELEASE + * NVB0CC_CTRL_PROFILER_CG_CONTROL_MASK_IDLE_SLOWDOWN_RELEASE + * NVB0CC_CTRL_PROFILER_CG_CONTROL_MASK_VAT_RELEASE + * This value indicates that the MAXWELL_PROFILER's outstanding request + * for the clock-gating feature associated with the field should be + * released. This will decrement the reference count for the feature + * if the MAXWELL_PROFILER has an outstanding request for it. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_ARGUMENT + */ +#define NVB0CC_CTRL_CMD_PROFILER_RELEASE_CG_CONTROLS NVB0CC_CTRL_CMD_POWER_RELEASE_FEATURES + +typedef NVB0CC_CTRL_POWER_RELEASE_FEATURES_PARAMS NVB0CC_CTRL_PROFILER_RELEASE_CG_CONTROLS_PARAMS; + +/* + * valid values for the controlMask parameter in addition to + * NVB0CC_CTRL_PROFILER_CG_CONTROL_MASK_*_IGNORE + */ +#define NVB0CC_CTRL_PROFILER_CG_CONTROL_RELEASE (0x00000003) + +#define NVB0CC_CTRL_PROFILER_CG_CONTROL_MASK_ELCG_RELEASE NVB0CC_CTRL_PROFILER_CG_CONTROL_RELEASE +#define NVB0CC_CTRL_PROFILER_CG_CONTROL_MASK_BLCG_RELEASE NVB0CC_CTRL_PROFILER_CG_CONTROL_RELEASE +#define NVB0CC_CTRL_PROFILER_CG_CONTROL_MASK_SLCG_RELEASE NVB0CC_CTRL_PROFILER_CG_CONTROL_RELEASE +#define NVB0CC_CTRL_PROFILER_CG_CONTROL_MASK_ELPG_RELEASE NVB0CC_CTRL_PROFILER_CG_CONTROL_RELEASE +#define NVB0CC_CTRL_PROFILER_CG_CONTROL_MASK_IDLE_SLOWDOWN_RELEASE NVB0CC_CTRL_PROFILER_CG_CONTROL_RELEASE +#define NVB0CC_CTRL_PROFILER_CG_CONTROL_MASK_VAT_RELEASE NVB0CC_CTRL_PROFILER_CG_CONTROL_RELEASE + +/* utility mask for the controlMask parameter for all fields */ +#define NVB0CC_CTRL_PROFILER_CG_CONTROL_MASK_ALL_RELEASE \ + DRF_DEF(B0CC, _CTRL_PROFILER_CG_CONTROL_MASK, _ELCG, _RELEASE) | \ + DRF_DEF(B0CC, _CTRL_PROFILER_CG_CONTROL_MASK, _BLCG, _RELEASE) | \ + DRF_DEF(B0CC, _CTRL_PROFILER_CG_CONTROL_MASK, _SLCG, _RELEASE) | \ + DRF_DEF(B0CC, _CTRL_PROFILER_CG_CONTROL_MASK, _ELPG, _RELEASE) | \ + DRF_DEF(B0CC, _CTRL_PROFILER_CG_CONTROL_MASK, _IDLE_SLOWDOWN, _RELEASE)| \ + DRF_DEF(B0CC, _CTRL_PROFILER_CG_CONTROL_MASK, _VAT, _RELEASE) diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/common/sdk/nvidia/inc/ctrl/ctrlc06f.h nvidia-open-gpu-kernel-modules-535.161.08/src/common/sdk/nvidia/inc/ctrl/ctrlc06f.h --- nvidia-open-gpu-kernel-modules-525.147.05/src/common/sdk/nvidia/inc/ctrl/ctrlc06f.h 2023-10-25 20:22:23.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/common/sdk/nvidia/inc/ctrl/ctrlc06f.h 2024-03-05 22:15:18.000000000 +0000 @@ -25,7 +25,7 @@ // // This file was generated with FINN, an NVIDIA coding tool. -// Source file: ctrl/ctrlc06f.finn +// Source file: ctrl/ctrlc06f.finn // @@ -65,20 +65,11 @@ * Please see description of NV906F_CTRL_GET_CLASS_ENGINEID for more information. * */ -#define NVC06F_CTRL_GET_CLASS_ENGINEID (0xc06f0101) /* finn: Evaluated from "(FINN_PASCAL_CHANNEL_GPFIFO_A_GPFIFO_INTERFACE_ID << 8) | 0x1" */ - -typedef NV906F_CTRL_GET_CLASS_ENGINEID_PARAMS NVC06F_CTRL_GET_CLASS_ENGINEID_PARAMS; - -// FINN PORT: The below type was generated by the FINN port to -// ensure that all API's have a unique structure associated -// with them! -#define NVC06F_CTRL_GET_CLASS_ENGINEID_FINN_PARAMS_MESSAGE_ID (0x1U) - -typedef struct NVC06F_CTRL_GET_CLASS_ENGINEID_FINN_PARAMS { - NVC06F_CTRL_GET_CLASS_ENGINEID_PARAMS params; -} NVC06F_CTRL_GET_CLASS_ENGINEID_FINN_PARAMS; +#define NVC06F_CTRL_GET_CLASS_ENGINEID (0xc06f0101) /* finn: Evaluated from "(FINN_PASCAL_CHANNEL_GPFIFO_A_GPFIFO_INTERFACE_ID << 8) | NVC06F_CTRL_GET_CLASS_ENGINEID_PARAMS_MESSAGE_ID" */ +#define NVC06F_CTRL_GET_CLASS_ENGINEID_PARAMS_MESSAGE_ID (0x1U) +typedef NV906F_CTRL_GET_CLASS_ENGINEID_PARAMS NVC06F_CTRL_GET_CLASS_ENGINEID_PARAMS; /* * NVC06F_CTRL_RESET_CHANNEL @@ -86,19 +77,11 @@ * Please see description of NVA06F_CTRL_RESET_CHANNEL for more information. * */ -#define NVC06F_CTRL_CMD_RESET_CHANNEL (0xc06f0102) /* finn: Evaluated from "(FINN_PASCAL_CHANNEL_GPFIFO_A_GPFIFO_INTERFACE_ID << 8) | 0x2" */ -typedef NVA06F_CTRL_CMD_RESET_CHANNEL_PARAMS NVC06F_CTRL_CMD_RESET_CHANNEL_PARAMS; - -// FINN PORT: The below type was generated by the FINN port to -// ensure that all API's have a unique structure associated -// with them! -#define NVC06F_CTRL_CMD_RESET_CHANNEL_FINN_PARAMS_MESSAGE_ID (0x2U) - -typedef struct NVC06F_CTRL_CMD_RESET_CHANNEL_FINN_PARAMS { - NVC06F_CTRL_CMD_RESET_CHANNEL_PARAMS params; -} NVC06F_CTRL_CMD_RESET_CHANNEL_FINN_PARAMS; +#define NVC06F_CTRL_CMD_RESET_CHANNEL (0xc06f0102) /* finn: Evaluated from "(FINN_PASCAL_CHANNEL_GPFIFO_A_GPFIFO_INTERFACE_ID << 8) | NVC06F_CTRL_CMD_RESET_CHANNEL_PARAMS_MESSAGE_ID" */ +#define NVC06F_CTRL_CMD_RESET_CHANNEL_PARAMS_MESSAGE_ID (0x2U) +typedef NVA06F_CTRL_CMD_RESET_CHANNEL_PARAMS NVC06F_CTRL_CMD_RESET_CHANNEL_PARAMS; /* * NVC06F_CTRL_CMD_GPFIFO_SCHEDULE @@ -106,59 +89,33 @@ * Please see description of NVA06F_CTRL_CMD_GPFIFO_SCHEDULE for more information. * */ -#define NVC06F_CTRL_CMD_GPFIFO_SCHEDULE (0xc06f0103) /* finn: Evaluated from "(FINN_PASCAL_CHANNEL_GPFIFO_A_GPFIFO_INTERFACE_ID << 8) | 0x3" */ -typedef NVA06F_CTRL_GPFIFO_SCHEDULE_PARAMS NVC06F_CTRL_GPFIFO_SCHEDULE_PARAMS; - -// FINN PORT: The below type was generated by the FINN port to -// ensure that all API's have a unique structure associated -// with them! -#define NVC06F_CTRL_CMD_GPFIFO_SCHEDULE_FINN_PARAMS_MESSAGE_ID (0x3U) - -typedef struct NVC06F_CTRL_CMD_GPFIFO_SCHEDULE_FINN_PARAMS { - NVC06F_CTRL_GPFIFO_SCHEDULE_PARAMS params; -} NVC06F_CTRL_CMD_GPFIFO_SCHEDULE_FINN_PARAMS; +#define NVC06F_CTRL_CMD_GPFIFO_SCHEDULE (0xc06f0103) /* finn: Evaluated from "(FINN_PASCAL_CHANNEL_GPFIFO_A_GPFIFO_INTERFACE_ID << 8) | NVC06F_CTRL_GPFIFO_SCHEDULE_PARAMS_MESSAGE_ID" */ +#define NVC06F_CTRL_GPFIFO_SCHEDULE_PARAMS_MESSAGE_ID (0x3U) +typedef NVA06F_CTRL_GPFIFO_SCHEDULE_PARAMS NVC06F_CTRL_GPFIFO_SCHEDULE_PARAMS; /* * NVC06F_CTRL_CMD_BIND * * Please see description of NVA06F_CTRL_CMD_BIND for more information. */ -#define NVC06F_CTRL_CMD_BIND (0xc06f0104) /* finn: Evaluated from "(FINN_PASCAL_CHANNEL_GPFIFO_A_GPFIFO_INTERFACE_ID << 8) | 0x4" */ - -typedef NVA06F_CTRL_BIND_PARAMS NVC06F_CTRL_BIND_PARAMS; - -// FINN PORT: The below type was generated by the FINN port to -// ensure that all API's have a unique structure associated -// with them! -#define NVC06F_CTRL_CMD_BIND_FINN_PARAMS_MESSAGE_ID (0x4U) - -typedef struct NVC06F_CTRL_CMD_BIND_FINN_PARAMS { - NVC06F_CTRL_BIND_PARAMS params; -} NVC06F_CTRL_CMD_BIND_FINN_PARAMS; +#define NVC06F_CTRL_CMD_BIND (0xc06f0104) /* finn: Evaluated from "(FINN_PASCAL_CHANNEL_GPFIFO_A_GPFIFO_INTERFACE_ID << 8) | NVC06F_CTRL_BIND_PARAMS_MESSAGE_ID" */ +#define NVC06F_CTRL_BIND_PARAMS_MESSAGE_ID (0x4U) +typedef NVA06F_CTRL_BIND_PARAMS NVC06F_CTRL_BIND_PARAMS; /* * NVC06F_CTRL_CMD_EVENT_SET_NOTIFICATION * * Please see description of NVA06F_CTRL_CMD_EVENT_SET_NOTIFICATION for more information. */ -#define NVC06F_CTRL_CMD_EVENT_SET_NOTIFICATION (0xc06f0205) /* finn: Evaluated from "(FINN_PASCAL_CHANNEL_GPFIFO_A_EVENT_INTERFACE_ID << 8) | 0x5" */ - -typedef NVA06F_CTRL_EVENT_SET_NOTIFICATION_PARAMS NVC06F_CTRL_EVENT_SET_NOTIFICATION_PARAMS; - -// FINN PORT: The below type was generated by the FINN port to -// ensure that all API's have a unique structure associated -// with them! -#define NVC06F_CTRL_CMD_EVENT_SET_NOTIFICATION_FINN_PARAMS_MESSAGE_ID (0x5U) - -typedef struct NVC06F_CTRL_CMD_EVENT_SET_NOTIFICATION_FINN_PARAMS { - NVC06F_CTRL_EVENT_SET_NOTIFICATION_PARAMS params; -} NVC06F_CTRL_CMD_EVENT_SET_NOTIFICATION_FINN_PARAMS; +#define NVC06F_CTRL_CMD_EVENT_SET_NOTIFICATION (0xc06f0205) /* finn: Evaluated from "(FINN_PASCAL_CHANNEL_GPFIFO_A_EVENT_INTERFACE_ID << 8) | NVC06F_CTRL_EVENT_SET_NOTIFICATION_PARAMS_MESSAGE_ID" */ +#define NVC06F_CTRL_EVENT_SET_NOTIFICATION_PARAMS_MESSAGE_ID (0x5U) +typedef NVA06F_CTRL_EVENT_SET_NOTIFICATION_PARAMS NVC06F_CTRL_EVENT_SET_NOTIFICATION_PARAMS; /* valid action values */ #define NVC06F_CTRL_EVENT_SET_NOTIFICATION_ACTION_DISABLE NVA06F_CTRL_EVENT_SET_NOTIFICATION_ACTION_DISABLE @@ -182,19 +139,10 @@ * Please see description of NV906F_CTRL_CMD_GET_MMU_FAULT_INFO for more information. * */ -#define NVC06F_CTRL_CMD_GET_MMU_FAULT_INFO (0xc06f0107) /* finn: Evaluated from "(FINN_PASCAL_CHANNEL_GPFIFO_A_GPFIFO_INTERFACE_ID << 8) | 0x7" */ - -typedef NV906F_CTRL_GET_MMU_FAULT_INFO_PARAMS NVC06F_CTRL_GET_MMU_FAULT_INFO_PARAMS; - -// FINN PORT: The below type was generated by the FINN port to -// ensure that all API's have a unique structure associated -// with them! -#define NVC06F_CTRL_CMD_GET_MMU_FAULT_INFO_FINN_PARAMS_MESSAGE_ID (0x7U) - -typedef struct NVC06F_CTRL_CMD_GET_MMU_FAULT_INFO_FINN_PARAMS { - NV_DECLARE_ALIGNED(NVC06F_CTRL_GET_MMU_FAULT_INFO_PARAMS params, 8); -} NVC06F_CTRL_CMD_GET_MMU_FAULT_INFO_FINN_PARAMS; +#define NVC06F_CTRL_CMD_GET_MMU_FAULT_INFO (0xc06f0107) /* finn: Evaluated from "(FINN_PASCAL_CHANNEL_GPFIFO_A_GPFIFO_INTERFACE_ID << 8) | NVC06F_CTRL_GET_MMU_FAULT_INFO_PARAMS_MESSAGE_ID" */ +#define NVC06F_CTRL_GET_MMU_FAULT_INFO_PARAMS_MESSAGE_ID (0x7U) +typedef NV906F_CTRL_GET_MMU_FAULT_INFO_PARAMS NVC06F_CTRL_GET_MMU_FAULT_INFO_PARAMS; /* _ctrlc06f.h_ */ diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/common/sdk/nvidia/inc/ctrl/ctrlc365.h nvidia-open-gpu-kernel-modules-535.161.08/src/common/sdk/nvidia/inc/ctrl/ctrlc365.h --- nvidia-open-gpu-kernel-modules-525.147.05/src/common/sdk/nvidia/inc/ctrl/ctrlc365.h 2023-10-25 20:22:23.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/common/sdk/nvidia/inc/ctrl/ctrlc365.h 2024-03-05 22:15:18.000000000 +0000 @@ -27,7 +27,7 @@ // // This file was generated with FINN, an NVIDIA coding tool. -// Source file: ctrl/ctrlc365.finn +// Source file: ctrl/ctrlc365.finn // #include "ctrl/ctrlxxxx.h" diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/common/sdk/nvidia/inc/ctrl/ctrlc369.h nvidia-open-gpu-kernel-modules-535.161.08/src/common/sdk/nvidia/inc/ctrl/ctrlc369.h --- nvidia-open-gpu-kernel-modules-525.147.05/src/common/sdk/nvidia/inc/ctrl/ctrlc369.h 2023-10-25 20:22:23.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/common/sdk/nvidia/inc/ctrl/ctrlc369.h 2024-03-05 22:15:19.000000000 +0000 @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 2015-2020 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2015-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -27,7 +27,7 @@ // // This file was generated with FINN, an NVIDIA coding tool. -// Source file: ctrl/ctrlc369.finn +// Source file: ctrl/ctrlc369.finn // #include "ctrl/ctrlxxxx.h" @@ -80,6 +80,7 @@ typedef struct NVC369_CTRL_MMU_FAULT_BUFFER_REGISTER_NON_REPLAY_BUF_PARAMS { NV_DECLARE_ALIGNED(NvP64 pShadowBuffer, 8); NV_DECLARE_ALIGNED(NvP64 pShadowBufferContext, 8); + NV_DECLARE_ALIGNED(NvP64 pShadowBufferMetadata, 8); NvU32 bufferSize; } NVC369_CTRL_MMU_FAULT_BUFFER_REGISTER_NON_REPLAY_BUF_PARAMS; @@ -106,4 +107,51 @@ NV_DECLARE_ALIGNED(NvP64 pShadowBuffer, 8); } NVC369_CTRL_MMU_FAULT_BUFFER_UNREGISTER_NON_REPLAY_BUF_PARAMS; +/* + * NVC369_CTRL_CMD_MMU_FAULT_BUFFER_REGISTER_REPLAY_BUFFER + * + * This call creates and registers a client buffer for the replayable faults + * + * pShadowBuffer [OUT] + * This parameter represents the pointer to the shadow buffer + * + * bufferSize [OUT] + * Size in bytes of the shadow buffer for non replayable faults + * + * Possible status values returned are: + * NV_OK + */ + +#define NVC369_CTRL_CMD_MMU_FAULT_BUFFER_REGISTER_REPLAY_BUF (0xc3690103) /* finn: Evaluated from "(FINN_MMU_FAULT_BUFFER_MMU_FAULT_BUFFER_INTERFACE_ID << 8) | NVC369_CTRL_MMU_FAULT_BUFFER_REGISTER_REPLAY_BUF_PARAMS_MESSAGE_ID" */ + +#define NVC369_CTRL_MMU_FAULT_BUFFER_REGISTER_REPLAY_BUF_PARAMS_MESSAGE_ID (0x3U) + +typedef struct NVC369_CTRL_MMU_FAULT_BUFFER_REGISTER_REPLAY_BUF_PARAMS { + NV_DECLARE_ALIGNED(NvP64 pShadowBuffer, 8); + NV_DECLARE_ALIGNED(NvP64 pShadowBufferMetadata, 8); + NvU32 bufferSize; +} NVC369_CTRL_MMU_FAULT_BUFFER_REGISTER_REPLAY_BUF_PARAMS; + +/* + * NVC369_CTRL_CMD_MMU_FAULT_BUFFER_UNREGISTER_REPLAY_BUFFER + * + * This call unregisters and destroys a client buffer for the replayable + * faults + * + * pShadowBuffer [IN] + * This parameter represents the pointer to the shadow buffer + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_ARGUMENT + */ + +#define NVC369_CTRL_CMD_MMU_FAULT_BUFFER_UNREGISTER_REPLAY_BUF (0xc3690104) /* finn: Evaluated from "(FINN_MMU_FAULT_BUFFER_MMU_FAULT_BUFFER_INTERFACE_ID << 8) | NVC369_CTRL_MMU_FAULT_BUFFER_UNREGISTER_REPLAY_BUF_PARAMS_MESSAGE_ID" */ + +#define NVC369_CTRL_MMU_FAULT_BUFFER_UNREGISTER_REPLAY_BUF_PARAMS_MESSAGE_ID (0x4U) + +typedef struct NVC369_CTRL_MMU_FAULT_BUFFER_UNREGISTER_REPLAY_BUF_PARAMS { + NV_DECLARE_ALIGNED(NvP64 pShadowBuffer, 8); +} NVC369_CTRL_MMU_FAULT_BUFFER_UNREGISTER_REPLAY_BUF_PARAMS; + /* _ctrlc369_h_ */ diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/common/sdk/nvidia/inc/ctrl/ctrlc36f.h nvidia-open-gpu-kernel-modules-535.161.08/src/common/sdk/nvidia/inc/ctrl/ctrlc36f.h --- nvidia-open-gpu-kernel-modules-525.147.05/src/common/sdk/nvidia/inc/ctrl/ctrlc36f.h 2023-10-25 20:22:24.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/common/sdk/nvidia/inc/ctrl/ctrlc36f.h 2024-03-05 22:15:19.000000000 +0000 @@ -27,7 +27,7 @@ // // This file was generated with FINN, an NVIDIA coding tool. -// Source file: ctrl/ctrlc36f.finn +// Source file: ctrl/ctrlc36f.finn // @@ -67,20 +67,11 @@ * Please see description of NV906F_CTRL_GET_CLASS_ENGINEID for more information. * */ -#define NVC36F_CTRL_GET_CLASS_ENGINEID (0xc36f0101) /* finn: Evaluated from "(FINN_VOLTA_CHANNEL_GPFIFO_A_GPFIFO_INTERFACE_ID << 8) | 0x1" */ - -typedef NV906F_CTRL_GET_CLASS_ENGINEID_PARAMS NVC36F_CTRL_GET_CLASS_ENGINEID_PARAMS; - -// FINN PORT: The below type was generated by the FINN port to -// ensure that all API's have a unique structure associated -// with them! -#define NVC36F_CTRL_GET_CLASS_ENGINEID_FINN_PARAMS_MESSAGE_ID (0x1U) - -typedef struct NVC36F_CTRL_GET_CLASS_ENGINEID_FINN_PARAMS { - NVC36F_CTRL_GET_CLASS_ENGINEID_PARAMS params; -} NVC36F_CTRL_GET_CLASS_ENGINEID_FINN_PARAMS; +#define NVC36F_CTRL_GET_CLASS_ENGINEID (0xc36f0101) /* finn: Evaluated from "(FINN_VOLTA_CHANNEL_GPFIFO_A_GPFIFO_INTERFACE_ID << 8) | NVC36F_CTRL_GET_CLASS_ENGINEID_PARAMS_MESSAGE_ID" */ +#define NVC36F_CTRL_GET_CLASS_ENGINEID_PARAMS_MESSAGE_ID (0x1U) +typedef NV906F_CTRL_GET_CLASS_ENGINEID_PARAMS NVC36F_CTRL_GET_CLASS_ENGINEID_PARAMS; /* * NVC36F_CTRL_RESET_CHANNEL @@ -88,20 +79,11 @@ * Please see description of NV906F_CTRL_CMD_RESET_CHANNEL for more information. * */ -#define NVC36F_CTRL_CMD_RESET_CHANNEL (0xc36f0102) /* finn: Evaluated from "(FINN_VOLTA_CHANNEL_GPFIFO_A_GPFIFO_INTERFACE_ID << 8) | 0x2" */ - -typedef NV906F_CTRL_CMD_RESET_CHANNEL_PARAMS NVC36F_CTRL_CMD_RESET_CHANNEL_PARAMS; - -// FINN PORT: The below type was generated by the FINN port to -// ensure that all API's have a unique structure associated -// with them! -#define NVC36F_CTRL_CMD_RESET_CHANNEL_FINN_PARAMS_MESSAGE_ID (0x2U) - -typedef struct NVC36F_CTRL_CMD_RESET_CHANNEL_FINN_PARAMS { - NVC36F_CTRL_CMD_RESET_CHANNEL_PARAMS params; -} NVC36F_CTRL_CMD_RESET_CHANNEL_FINN_PARAMS; +#define NVC36F_CTRL_CMD_RESET_CHANNEL (0xc36f0102) /* finn: Evaluated from "(FINN_VOLTA_CHANNEL_GPFIFO_A_GPFIFO_INTERFACE_ID << 8) | NVC36F_CTRL_CMD_RESET_CHANNEL_PARAMS_MESSAGE_ID" */ +#define NVC36F_CTRL_CMD_RESET_CHANNEL_PARAMS_MESSAGE_ID (0x2U) +typedef NV906F_CTRL_CMD_RESET_CHANNEL_PARAMS NVC36F_CTRL_CMD_RESET_CHANNEL_PARAMS; /* * NVC36F_CTRL_CMD_GPFIFO_SCHEDULE @@ -109,40 +91,22 @@ * Please see description of NVA06F_CTRL_CMD_GPFIFO_SCHEDULE for more information. * */ -#define NVC36F_CTRL_CMD_GPFIFO_SCHEDULE (0xc36f0103) /* finn: Evaluated from "(FINN_VOLTA_CHANNEL_GPFIFO_A_GPFIFO_INTERFACE_ID << 8) | 0x3" */ - -typedef NVA06F_CTRL_GPFIFO_SCHEDULE_PARAMS NVC36F_CTRL_GPFIFO_SCHEDULE_PARAMS; - -// FINN PORT: The below type was generated by the FINN port to -// ensure that all API's have a unique structure associated -// with them! -#define NVC36F_CTRL_CMD_GPFIFO_SCHEDULE_FINN_PARAMS_MESSAGE_ID (0x3U) - -typedef struct NVC36F_CTRL_CMD_GPFIFO_SCHEDULE_FINN_PARAMS { - NVC36F_CTRL_GPFIFO_SCHEDULE_PARAMS params; -} NVC36F_CTRL_CMD_GPFIFO_SCHEDULE_FINN_PARAMS; +#define NVC36F_CTRL_CMD_GPFIFO_SCHEDULE (0xc36f0103) /* finn: Evaluated from "(FINN_VOLTA_CHANNEL_GPFIFO_A_GPFIFO_INTERFACE_ID << 8) | NVC36F_CTRL_GPFIFO_SCHEDULE_PARAMS_MESSAGE_ID" */ +#define NVC36F_CTRL_GPFIFO_SCHEDULE_PARAMS_MESSAGE_ID (0x3U) +typedef NVA06F_CTRL_GPFIFO_SCHEDULE_PARAMS NVC36F_CTRL_GPFIFO_SCHEDULE_PARAMS; /* * NVC36F_CTRL_CMD_BIND * * Please see description of NVA06F_CTRL_CMD_BIND for more information. */ -#define NVC36F_CTRL_CMD_BIND (0xc36f0104) /* finn: Evaluated from "(FINN_VOLTA_CHANNEL_GPFIFO_A_GPFIFO_INTERFACE_ID << 8) | 0x4" */ - -typedef NVA06F_CTRL_BIND_PARAMS NVC36F_CTRL_BIND_PARAMS; - -// FINN PORT: The below type was generated by the FINN port to -// ensure that all API's have a unique structure associated -// with them! -#define NVC36F_CTRL_CMD_BIND_FINN_PARAMS_MESSAGE_ID (0x4U) - -typedef struct NVC36F_CTRL_CMD_BIND_FINN_PARAMS { - NVC36F_CTRL_BIND_PARAMS params; -} NVC36F_CTRL_CMD_BIND_FINN_PARAMS; +#define NVC36F_CTRL_CMD_BIND (0xc36f0104) /* finn: Evaluated from "(FINN_VOLTA_CHANNEL_GPFIFO_A_GPFIFO_INTERFACE_ID << 8) | NVC36F_CTRL_BIND_PARAMS_MESSAGE_ID" */ +#define NVC36F_CTRL_BIND_PARAMS_MESSAGE_ID (0x4U) +typedef NVA06F_CTRL_BIND_PARAMS NVC36F_CTRL_BIND_PARAMS; /* * NVC36F_CTRL_CMD_EVENT_SET_NOTIFICATION @@ -175,20 +139,11 @@ * Please see description of NV906F_CTRL_CMD_GET_MMU_FAULT_INFO for more information. * */ -#define NVC36F_CTRL_CMD_GET_MMU_FAULT_INFO (0xc36f0107) /* finn: Evaluated from "(FINN_VOLTA_CHANNEL_GPFIFO_A_GPFIFO_INTERFACE_ID << 8) | 0x7" */ - -typedef NV906F_CTRL_GET_MMU_FAULT_INFO_PARAMS NVC36F_CTRL_GET_MMU_FAULT_INFO_PARAMS; - -// FINN PORT: The below type was generated by the FINN port to -// ensure that all API's have a unique structure associated -// with them! -#define NVC36F_CTRL_CMD_GET_MMU_FAULT_INFO_FINN_PARAMS_MESSAGE_ID (0x7U) - -typedef struct NVC36F_CTRL_CMD_GET_MMU_FAULT_INFO_FINN_PARAMS { - NV_DECLARE_ALIGNED(NVC36F_CTRL_GET_MMU_FAULT_INFO_PARAMS params, 8); -} NVC36F_CTRL_CMD_GET_MMU_FAULT_INFO_FINN_PARAMS; +#define NVC36F_CTRL_CMD_GET_MMU_FAULT_INFO (0xc36f0107) /* finn: Evaluated from "(FINN_VOLTA_CHANNEL_GPFIFO_A_GPFIFO_INTERFACE_ID << 8) | NVC36F_CTRL_GET_MMU_FAULT_INFO_PARAMS_MESSAGE_ID" */ +#define NVC36F_CTRL_GET_MMU_FAULT_INFO_PARAMS_MESSAGE_ID (0x7U) +typedef NV906F_CTRL_GET_MMU_FAULT_INFO_PARAMS NVC36F_CTRL_GET_MMU_FAULT_INFO_PARAMS; /* * NVC36F_CTRL_CMD_GPFIFO_GET_WORK_SUBMIT_TOKEN diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/common/sdk/nvidia/inc/ctrl/ctrlc370/ctrlc370base.h nvidia-open-gpu-kernel-modules-535.161.08/src/common/sdk/nvidia/inc/ctrl/ctrlc370/ctrlc370base.h --- nvidia-open-gpu-kernel-modules-525.147.05/src/common/sdk/nvidia/inc/ctrl/ctrlc370/ctrlc370base.h 2023-10-25 20:22:24.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/common/sdk/nvidia/inc/ctrl/ctrlc370/ctrlc370base.h 2024-03-05 22:15:19.000000000 +0000 @@ -27,7 +27,7 @@ // // This file was generated with FINN, an NVIDIA coding tool. -// Source file: ctrl/ctrlc370/ctrlc370base.finn +// Source file: ctrl/ctrlc370/ctrlc370base.finn // #include "ctrl/ctrlxxxx.h" diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/common/sdk/nvidia/inc/ctrl/ctrlc370/ctrlc370chnc.h nvidia-open-gpu-kernel-modules-535.161.08/src/common/sdk/nvidia/inc/ctrl/ctrlc370/ctrlc370chnc.h --- nvidia-open-gpu-kernel-modules-525.147.05/src/common/sdk/nvidia/inc/ctrl/ctrlc370/ctrlc370chnc.h 2023-10-25 20:22:24.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/common/sdk/nvidia/inc/ctrl/ctrlc370/ctrlc370chnc.h 2024-03-05 22:15:19.000000000 +0000 @@ -27,7 +27,7 @@ // // This file was generated with FINN, an NVIDIA coding tool. -// Source file: ctrl/ctrlc370/ctrlc370chnc.finn +// Source file: ctrl/ctrlc370/ctrlc370chnc.finn // #include "ctrl/ctrlc370/ctrlc370base.h" @@ -185,7 +185,7 @@ #define NVC370_CTRL_CMD_SET_ACCL (0xc3700102) /* finn: Evaluated from "(FINN_NVC370_DISPLAY_CHNCTL_INTERFACE_ID << 8) | NVC370_CTRL_SET_ACCL_PARAMS_MESSAGE_ID" */ -#define NVC370_CTRL_CMD_GET_ACCL (0xc3700103) /* finn: Evaluated from "(FINN_NVC370_DISPLAY_CHNCTL_INTERFACE_ID << 8) | 0x3" */ +#define NVC370_CTRL_CMD_GET_ACCL (0xc3700103) /* finn: Evaluated from "(FINN_NVC370_DISPLAY_CHNCTL_INTERFACE_ID << 8) | NVC370_CTRL_GET_ACCL_PARAMS_MESSAGE_ID" */ #define NVC370_CTRL_ACCL_MAX_INSTANCE_CORE NVC370_CTRL_CMD_MAX_CHANNEL_INSTANCE_CORE #define NVC370_CTRL_ACCL_MAX_INSTANCE_WINDOW NVC370_CTRL_CMD_MAX_CHANNEL_INSTANCE_WINDOW @@ -204,28 +204,21 @@ #define NVC370_CTRL_ACCL_SKIP_SYNCPOINT NVC370_CTRL_IDLE_CHANNEL_ACCL_SKIP_SYNCPOINT #define NVC370_CTRL_ACCL_IGNORE_TIMESTAMP NVC370_CTRL_IDLE_CHANNEL_ACCL_IGNORE_TIMESTAMP #define NVC370_CTRL_ACCL_IGNORE_MGI NVC370_CTRL_IDLE_CHANNEL_ACCL_IGNORE_MGI -#define NVC370_CTRL_SET_ACCL_PARAMS_MESSAGE_ID (0x2U) - -typedef struct NVC370_CTRL_SET_ACCL_PARAMS { +typedef struct NVC370_CTRL_ACCL_PARAMS { NVC370_CTRL_CMD_BASE_PARAMS base; NvU32 channelClass; NvU32 channelInstance; NvU32 accelerators; NvU32 accelMask; -} NVC370_CTRL_SET_ACCL_PARAMS; -typedef NVC370_CTRL_SET_ACCL_PARAMS NVC370_CTRL_GET_ACCL_PARAMS; +} NVC370_CTRL_ACCL_PARAMS; -// FINN PORT: The below type was generated by the FINN port to -// ensure that all API's have a unique structure associated -// with them! -#define NVC370_CTRL_CMD_GET_ACCL_FINN_PARAMS_MESSAGE_ID (0x3U) - -typedef struct NVC370_CTRL_CMD_GET_ACCL_FINN_PARAMS { - NVC370_CTRL_GET_ACCL_PARAMS params; -} NVC370_CTRL_CMD_GET_ACCL_FINN_PARAMS; +#define NVC370_CTRL_SET_ACCL_PARAMS_MESSAGE_ID (0x2U) +typedef NVC370_CTRL_ACCL_PARAMS NVC370_CTRL_SET_ACCL_PARAMS; +#define NVC370_CTRL_GET_ACCL_PARAMS_MESSAGE_ID (0x3U) +typedef NVC370_CTRL_ACCL_PARAMS NVC370_CTRL_GET_ACCL_PARAMS; /* * NVC370_CTRL_CMD_GET_CHANNEL_INFO diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/common/sdk/nvidia/inc/ctrl/ctrlc370/ctrlc370event.h nvidia-open-gpu-kernel-modules-535.161.08/src/common/sdk/nvidia/inc/ctrl/ctrlc370/ctrlc370event.h --- nvidia-open-gpu-kernel-modules-525.147.05/src/common/sdk/nvidia/inc/ctrl/ctrlc370/ctrlc370event.h 2023-10-25 20:22:24.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/common/sdk/nvidia/inc/ctrl/ctrlc370/ctrlc370event.h 2024-03-05 22:15:19.000000000 +0000 @@ -27,7 +27,7 @@ // // This file was generated with FINN, an NVIDIA coding tool. -// Source file: ctrl/ctrlc370/ctrlc370event.finn +// Source file: ctrl/ctrlc370/ctrlc370event.finn // #include "ctrl/ctrlc370/ctrlc370base.h" diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/common/sdk/nvidia/inc/ctrl/ctrlc370/ctrlc370rg.h nvidia-open-gpu-kernel-modules-535.161.08/src/common/sdk/nvidia/inc/ctrl/ctrlc370/ctrlc370rg.h --- nvidia-open-gpu-kernel-modules-525.147.05/src/common/sdk/nvidia/inc/ctrl/ctrlc370/ctrlc370rg.h 2023-10-25 20:22:24.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/common/sdk/nvidia/inc/ctrl/ctrlc370/ctrlc370rg.h 2024-03-05 22:15:19.000000000 +0000 @@ -27,7 +27,7 @@ // // This file was generated with FINN, an NVIDIA coding tool. -// Source file: ctrl/ctrlc370/ctrlc370rg.finn +// Source file: ctrl/ctrlc370/ctrlc370rg.finn // #include "ctrl/ctrlc370/ctrlc370base.h" diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/common/sdk/nvidia/inc/ctrl/ctrlc370/ctrlc370verif.h nvidia-open-gpu-kernel-modules-535.161.08/src/common/sdk/nvidia/inc/ctrl/ctrlc370/ctrlc370verif.h --- nvidia-open-gpu-kernel-modules-525.147.05/src/common/sdk/nvidia/inc/ctrl/ctrlc370/ctrlc370verif.h 2023-10-25 20:22:24.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/common/sdk/nvidia/inc/ctrl/ctrlc370/ctrlc370verif.h 2024-03-05 22:15:19.000000000 +0000 @@ -27,7 +27,7 @@ // // This file was generated with FINN, an NVIDIA coding tool. -// Source file: ctrl/ctrlc370/ctrlc370verif.finn +// Source file: ctrl/ctrlc370/ctrlc370verif.finn // #include "ctrl/ctrlc370/ctrlc370base.h" diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/common/sdk/nvidia/inc/ctrl/ctrlc372/ctrlc372base.h nvidia-open-gpu-kernel-modules-535.161.08/src/common/sdk/nvidia/inc/ctrl/ctrlc372/ctrlc372base.h --- nvidia-open-gpu-kernel-modules-525.147.05/src/common/sdk/nvidia/inc/ctrl/ctrlc372/ctrlc372base.h 2023-10-25 20:22:24.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/common/sdk/nvidia/inc/ctrl/ctrlc372/ctrlc372base.h 2024-03-05 22:15:19.000000000 +0000 @@ -27,7 +27,7 @@ // // This file was generated with FINN, an NVIDIA coding tool. -// Source file: ctrl/ctrlc372/ctrlc372base.finn +// Source file: ctrl/ctrlc372/ctrlc372base.finn // #include "ctrl/ctrlxxxx.h" diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/common/sdk/nvidia/inc/ctrl/ctrlc372/ctrlc372chnc.h nvidia-open-gpu-kernel-modules-535.161.08/src/common/sdk/nvidia/inc/ctrl/ctrlc372/ctrlc372chnc.h --- nvidia-open-gpu-kernel-modules-525.147.05/src/common/sdk/nvidia/inc/ctrl/ctrlc372/ctrlc372chnc.h 2023-10-25 20:22:24.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/common/sdk/nvidia/inc/ctrl/ctrlc372/ctrlc372chnc.h 2024-03-05 22:15:19.000000000 +0000 @@ -27,7 +27,7 @@ // // This file was generated with FINN, an NVIDIA coding tool. -// Source file: ctrl/ctrlc372/ctrlc372chnc.finn +// Source file: ctrl/ctrlc372/ctrlc372chnc.finn // #include "nvdisptypes.h" diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/common/sdk/nvidia/inc/ctrl/ctrlc46f.h nvidia-open-gpu-kernel-modules-535.161.08/src/common/sdk/nvidia/inc/ctrl/ctrlc46f.h --- nvidia-open-gpu-kernel-modules-525.147.05/src/common/sdk/nvidia/inc/ctrl/ctrlc46f.h 2023-10-25 20:22:24.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/common/sdk/nvidia/inc/ctrl/ctrlc46f.h 2024-03-05 22:15:20.000000000 +0000 @@ -27,7 +27,7 @@ // // This file was generated with FINN, an NVIDIA coding tool. -// Source file: ctrl/ctrlc46f.finn +// Source file: ctrl/ctrlc46f.finn // diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/common/sdk/nvidia/inc/ctrl/ctrlc56f.h nvidia-open-gpu-kernel-modules-535.161.08/src/common/sdk/nvidia/inc/ctrl/ctrlc56f.h --- nvidia-open-gpu-kernel-modules-525.147.05/src/common/sdk/nvidia/inc/ctrl/ctrlc56f.h 2023-10-25 20:22:24.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/common/sdk/nvidia/inc/ctrl/ctrlc56f.h 2024-03-05 22:15:20.000000000 +0000 @@ -27,7 +27,7 @@ // // This file was generated with FINN, an NVIDIA coding tool. -// Source file: ctrl/ctrlc56f.finn +// Source file: ctrl/ctrlc56f.finn // @@ -40,6 +40,8 @@ #include "ctrl/ctrla06f.h" /* C36F is partially derived from a06F */ #include "ctrl/ctrlc36f.h" // This control call interface is an ALIAS of C36F +#include "cc_drv.h" + #define NVC56F_CTRL_CMD(cat,idx) \ @@ -160,6 +162,50 @@ NvU32 workSubmitToken; } NVC56F_CTRL_CMD_GPFIFO_GET_WORK_SUBMIT_TOKEN_PARAMS; +/* + * NVC56F_CTRL_CMD_GET_KMB + * + * This command returns the Key Material Bundle (KMB) for the current channel. + * + * kmb [OUT] The KMB for the channel. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_OBJECT_HANDLE + * NV_ERR_INVALID_ARGUMENT + * NV_ERR_NOT_SUPPORTED + */ +#define NVC56F_CTRL_CMD_GET_KMB (0xc56f010b) /* finn: Evaluated from "(FINN_AMPERE_CHANNEL_GPFIFO_A_GPFIFO_INTERFACE_ID << 8) | NVC56F_CTRL_CMD_GET_KMB_PARAMS_MESSAGE_ID" */ + +#define NVC56F_CTRL_CMD_GET_KMB_PARAMS_MESSAGE_ID (0xBU) + +typedef struct NVC56F_CTRL_CMD_GET_KMB_PARAMS { + CC_KMB kmb; +} NVC56F_CTRL_CMD_GET_KMB_PARAMS; + +/* + * NVC56F_CTRL_ROTATE_SECURE_CHANNEL_IV + * + * This command rotates the IVs for secure channels. + * + * rotateIvType [IN] Which IVs to rotate. + * updatedKmb [OUT] Updated KMB after the IV rotation. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_OBJECT_HANDLE + * NV_ERR_INVALID_ARGUMENT + * NV_ERR_NOT_SUPPORTED + */ +#define NVC56F_CTRL_ROTATE_SECURE_CHANNEL_IV (0xc56f010c) /* finn: Evaluated from "(FINN_AMPERE_CHANNEL_GPFIFO_A_GPFIFO_INTERFACE_ID << 8) | NVC56F_CTRL_ROTATE_SECURE_CHANNEL_IV_PARAMS_MESSAGE_ID" */ + +#define NVC56F_CTRL_ROTATE_SECURE_CHANNEL_IV_PARAMS_MESSAGE_ID (0xCU) + +typedef struct NVC56F_CTRL_ROTATE_SECURE_CHANNEL_IV_PARAMS { + ROTATE_IV_TYPE rotateIvType; + CC_KMB updatedKmb; +} NVC56F_CTRL_ROTATE_SECURE_CHANNEL_IV_PARAMS; + /* _ctrlc56f.h_ */ diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/common/sdk/nvidia/inc/ctrl/ctrlc637.h nvidia-open-gpu-kernel-modules-535.161.08/src/common/sdk/nvidia/inc/ctrl/ctrlc637.h --- nvidia-open-gpu-kernel-modules-525.147.05/src/common/sdk/nvidia/inc/ctrl/ctrlc637.h 2023-10-25 20:22:25.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/common/sdk/nvidia/inc/ctrl/ctrlc637.h 2024-03-05 22:15:20.000000000 +0000 @@ -27,7 +27,7 @@ // // This file was generated with FINN, an NVIDIA coding tool. -// Source file: ctrl/ctrlc637.finn +// Source file: ctrl/ctrlc637.finn // #include "ctrl/ctrlxxxx.h" @@ -302,6 +302,7 @@ NvU8 uuid[NVC637_UUID_LEN]; NvU32 sharedEngFlags; NvU32 gpcMask; + NvU32 gfxGpcCount; NvU32 veidOffset; NvU32 veidCount; NvU32 smCount; @@ -310,8 +311,9 @@ } NVC637_CTRL_EXEC_PARTITIONS_EXPORTED_INFO; typedef struct NVC637_CTRL_EXEC_PARTITIONS_IMPORT_EXPORT_PARAMS { - NvU32 id; + NvU32 id; NV_DECLARE_ALIGNED(NVC637_CTRL_EXEC_PARTITIONS_EXPORTED_INFO info, 8); + NvBool bCreateCap; } NVC637_CTRL_EXEC_PARTITIONS_IMPORT_EXPORT_PARAMS; /* diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/common/sdk/nvidia/inc/ctrl/ctrlc638.h nvidia-open-gpu-kernel-modules-535.161.08/src/common/sdk/nvidia/inc/ctrl/ctrlc638.h --- nvidia-open-gpu-kernel-modules-525.147.05/src/common/sdk/nvidia/inc/ctrl/ctrlc638.h 2023-10-25 20:22:25.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/common/sdk/nvidia/inc/ctrl/ctrlc638.h 2024-03-05 22:15:20.000000000 +0000 @@ -27,7 +27,7 @@ // // This file was generated with FINN, an NVIDIA coding tool. -// Source file: ctrl/ctrlc638.finn +// Source file: ctrl/ctrlc638.finn // #include "ctrl/ctrlxxxx.h" diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/common/sdk/nvidia/inc/ctrl/ctrlc763.h nvidia-open-gpu-kernel-modules-535.161.08/src/common/sdk/nvidia/inc/ctrl/ctrlc763.h --- nvidia-open-gpu-kernel-modules-525.147.05/src/common/sdk/nvidia/inc/ctrl/ctrlc763.h 1970-01-01 00:00:00.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/common/sdk/nvidia/inc/ctrl/ctrlc763.h 2024-03-05 22:15:20.000000000 +0000 @@ -0,0 +1,242 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2019-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#pragma once + +#include + +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: ctrl/ctrlc763.finn +// + +#include "ctrl/ctrlxxxx.h" +/* Vidmem Access bit buffer control commands and parameters */ + +#define NVC763_CTRL_CMD(cat,idx) NVXXXX_CTRL_CMD(0xC763, NVC763_CTRL_##cat, idx) + +/* MMU_VIDMEM_ACCESS_BIT_BUFFER command categories (6bits) */ +#define NVC763_CTRL_RESERVED (0x00) +#define NVC763_CTRL_VIDMEM_ACCESS_BIT_BUFFER (0x01) + +/* + * SW def for number of range checkers. Current value taken from + * NV_PFB_PRI_MMU_VIDMEM_ACCESS_BIT_START_ADDR_LO__SIZE_1 + * on GA102. Compile time assert to check that the below + * definition is consistent with HW manuals is included in + * each gmmu HAL where this is relevant. + */ +#define NV_VIDMEM_ACCESS_BIT_BUFFER_NUM_CHECKERS 8 + +/* + * NVC763_CTRL_CMD_NULL + * + * This command does nothing. + * This command does not take any parameters. + * + * Possible status values returned are: + * NV_OK + */ +#define NVC763_CTRL_CMD_NULL (0xc7630000) /* finn: Evaluated from "(FINN_MMU_VIDMEM_ACCESS_BIT_BUFFER_RESERVED_INTERFACE_ID << 8) | 0x0" */ + +#define NVC763_CTRL_CMD_VIDMEM_ACCESS_BIT_ENABLE_LOGGING (0xc7630101) /* finn: Evaluated from "(FINN_MMU_VIDMEM_ACCESS_BIT_BUFFER_VIDMEM_ACCESS_BIT_BUFFER_INTERFACE_ID << 8) | NVC763_CTRL_VIDMEM_ACCESS_BIT_BUFFER_ENABLE_LOGGING_PARAMS_MESSAGE_ID" */ + +// Supported granularities for the vidmem access bit buffer logging +typedef enum NVC763_CTRL_VIDMEM_ACCESS_BIT_BUFFER_GRANULARITY { + NVC763_CTRL_VIDMEM_ACCESS_BIT_BUFFER_GRANULARITY_64KB = 0, + NVC763_CTRL_VIDMEM_ACCESS_BIT_BUFFER_GRANULARITY_128KB = 1, + NVC763_CTRL_VIDMEM_ACCESS_BIT_BUFFER_GRANULARITY_256KB = 2, + NVC763_CTRL_VIDMEM_ACCESS_BIT_BUFFER_GRANULARITY_512KB = 3, + NVC763_CTRL_VIDMEM_ACCESS_BIT_BUFFER_GRANULARITY_1MB = 4, + NVC763_CTRL_VIDMEM_ACCESS_BIT_BUFFER_GRANULARITY_2MB = 5, + NVC763_CTRL_VIDMEM_ACCESS_BIT_BUFFER_GRANULARITY_4MB = 6, + NVC763_CTRL_VIDMEM_ACCESS_BIT_BUFFER_GRANULARITY_8MB = 7, + NVC763_CTRL_VIDMEM_ACCESS_BIT_BUFFER_GRANULARITY_16MB = 8, + NVC763_CTRL_VIDMEM_ACCESS_BIT_BUFFER_GRANULARITY_32MB = 9, + NVC763_CTRL_VIDMEM_ACCESS_BIT_BUFFER_GRANULARITY_64MB = 10, + NVC763_CTRL_VIDMEM_ACCESS_BIT_BUFFER_GRANULARITY_128MB = 11, + NVC763_CTRL_VIDMEM_ACCESS_BIT_BUFFER_GRANULARITY_256MB = 12, + NVC763_CTRL_VIDMEM_ACCESS_BIT_BUFFER_GRANULARITY_512MB = 13, + NVC763_CTRL_VIDMEM_ACCESS_BIT_BUFFER_GRANULARITY_1GB = 14, + NVC763_CTRL_VIDMEM_ACCESS_BIT_BUFFER_GRANULARITY_2GB = 15, +} NVC763_CTRL_VIDMEM_ACCESS_BIT_BUFFER_GRANULARITY; + +/** + * enum of disable mode to be used when the MMU enters protected mode + */ +typedef enum NVC763_CTRL_VIDMEM_ACCESS_BIT_BUFFER_DISABLE_MODE { + /*! + * Disable mode will set all the access/dirty bits as '0' + */ + NVC763_CTRL_VIDMEM_ACCESS_BIT_BUFFER_DISABLE_MODE_CLEAR = 0, + /*! + * Disable mode will set all the access/dirty bits as '1' + */ + NVC763_CTRL_VIDMEM_ACCESS_BIT_BUFFER_DISABLE_MODE_SET = 1, +} NVC763_CTRL_VIDMEM_ACCESS_BIT_BUFFER_DISABLE_MODE; + + +// +// If clients want to enable logging specifically for some MMU, clients need to +// do it in a loop +// +typedef enum NV_VIDMEM_ACCESS_BIT_BUFFER_MMU_TYPE { + /*! + * Read/Write Attrs only for HUBMMU registers + */ + NV_VIDMEM_ACCESS_BIT_BUFFER_HUBMMU = 0, + /*! + * Read/Write Attrs only for GPCMMU registers + */ + NV_VIDMEM_ACCESS_BIT_BUFFER_GPCMMU = 1, + /*! + * Read/Write Attrs only for HSHUBMMU registers + */ + NV_VIDMEM_ACCESS_BIT_BUFFER_HSHUBMMU = 2, + /*! + * Default will enable for all MMU possible + */ + NV_VIDMEM_ACCESS_BIT_BUFFER_DEFAULT = 3, +} NV_VIDMEM_ACCESS_BIT_BUFFER_MMU_TYPE; + +typedef enum NVC763_CTRL_VIDMEM_ACCESS_BIT_BUFFER_TRACK_MODE { + /*! + Mode to track access bits + */ + NVC763_CTRL_VIDMEM_ACCESS_BIT_BUFFER_TRACK_MODE_ACCESS = 0, + /*! + Mode to track dirty bits + */ + NVC763_CTRL_VIDMEM_ACCESS_BIT_BUFFER_TRACK_MODE_DIRTY = 1, +} NVC763_CTRL_VIDMEM_ACCESS_BIT_BUFFER_TRACK_MODE; + +/* + * NVC763_CTRL_VIDMEM_ACCESS_BIT_BUFFER_ENABLE_LOGGING_PARAMS + * + * This structure is used to enable logging of the VAB and specifies + * the requested configuration for the 8 independent range checkers. + * The tracking mode and disable mode are the same for all range checkers. + */ +#define NVC763_CTRL_VIDMEM_ACCESS_BIT_BUFFER_ENABLE_LOGGING_PARAMS_MESSAGE_ID (0x1U) + +typedef struct NVC763_CTRL_VIDMEM_ACCESS_BIT_BUFFER_ENABLE_LOGGING_PARAMS { + NVC763_CTRL_VIDMEM_ACCESS_BIT_BUFFER_GRANULARITY granularity[NV_VIDMEM_ACCESS_BIT_BUFFER_NUM_CHECKERS]; + NVC763_CTRL_VIDMEM_ACCESS_BIT_BUFFER_TRACK_MODE trackMode; + NVC763_CTRL_VIDMEM_ACCESS_BIT_BUFFER_DISABLE_MODE disableMode; + NV_DECLARE_ALIGNED(NvU64 startAddress[NV_VIDMEM_ACCESS_BIT_BUFFER_NUM_CHECKERS], 8); + NvU8 rangeCount; + NV_VIDMEM_ACCESS_BIT_BUFFER_MMU_TYPE mmuType; +} NVC763_CTRL_VIDMEM_ACCESS_BIT_BUFFER_ENABLE_LOGGING_PARAMS; + + +#define NVC763_CTRL_CMD_VIDMEM_ACCESS_BIT_DISABLE_LOGGING (0xc7630102) /* finn: Evaluated from "(FINN_MMU_VIDMEM_ACCESS_BIT_BUFFER_VIDMEM_ACCESS_BIT_BUFFER_INTERFACE_ID << 8) | 0x2" */ + +/* + * NVC763_CTRL_CMD_VIDMEM_ACCESS_BIT_BUFFER_DUMP + * + * This call initiates the dump request with the properties set using enable + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_ARGUMENT + */ + +#define NVC763_CTRL_CMD_VIDMEM_ACCESS_BIT_DUMP (0xc7630103) /* finn: Evaluated from "(FINN_MMU_VIDMEM_ACCESS_BIT_BUFFER_VIDMEM_ACCESS_BIT_BUFFER_INTERFACE_ID << 8) | NVC763_CTRL_VIDMEM_ACCESS_BIT_BUFFER_DUMP_PARAMS_MESSAGE_ID" */ + +/* + * NV_VAB_OP enumerates the types of dumps supported + * + * The options are: + * + * AGGREGATE + * Collects access buffer bits over multiple dumps using a bitwise OR. + * + * DIFF + * Sets a bit to 1 if it changed from 0 to 1 with this dump. If a bit was + * cleared since the last dump it will be 0. If a bit does not change + * with this dump it will be 0. + * + * CURRENT + * Copies the current access bit buffer state as is from HW. This operation + * clears any underlying aggregation from previous dumps with the other + * two operations. + * + * INVALID + * Should be unused and otherwise indicates error + */ +typedef enum NVC763_CTRL_VIDMEM_ACCESS_BIT_BUFFER_OP { + NVC763_CTRL_VIDMEM_ACCESS_BIT_BUFFER_OP_AGGREGATE = 0, + NVC763_CTRL_VIDMEM_ACCESS_BIT_BUFFER_OP_DIFF = 1, + NVC763_CTRL_VIDMEM_ACCESS_BIT_BUFFER_OP_CURRENT = 2, + NVC763_CTRL_VIDMEM_ACCESS_BIT_BUFFER_OP_INVALID = 3, +} NVC763_CTRL_VIDMEM_ACCESS_BIT_BUFFER_OP; + +/* + * NVC763_CTRL_VIDMEM_ACCESS_BIT_DUMP_PARAMS + * + * This structure records the dumped bits for the client + * masked by the client's access bit mask determined + * during VidmemAccessBitBuffer construction. + * + * bMetadata [IN] + * Whether or not clients want disable data. + * + * op_enum [IN] + * A member of NVC763_CTRL_VIDMEM_ACCESS_BIT_BUFFER_OP controlling the type of dump. + * + * accessBits [OUT] + * The client's access bits masked according to the client's access bit mask. + * + * gpcDisable [OUT] + * The GPC disable data from the VAB dump. See GPC_DISABLE in the Ampere-801 FD. + * + * hubDisable [OUT] + * The HUB disable data from the VAB dump. See HUB_DISABLE in the Ampere-801 FD. + * + * hsceDisable [OUT] + * The HSCE disable data from the VAB dump. See HSCE_DIS in the Ampere-801 FD. + * + * linkDisable [OUT] + * The LINK disable data from the VAB dump. See LINK_DIS in the Ampere-801 FD. + */ +#define NVC763_CTRL_VIDMEM_ACCESS_BIT_BUFFER_DUMP_PARAMS_MESSAGE_ID (0x3U) + +typedef struct NVC763_CTRL_VIDMEM_ACCESS_BIT_BUFFER_DUMP_PARAMS { + NvBool bMetadata; + NVC763_CTRL_VIDMEM_ACCESS_BIT_BUFFER_OP op_enum; + NV_DECLARE_ALIGNED(NvU64 accessBits[64], 8); + NV_DECLARE_ALIGNED(NvU64 gpcDisable, 8); + NvU32 hubDisable; + NvU16 hsceDisable; + NvU8 linkDisable; +} NVC763_CTRL_VIDMEM_ACCESS_BIT_BUFFER_DUMP_PARAMS; + + +#define NVC763_CTRL_CMD_VIDMEM_ACCESS_BIT_PUT_OFFSET (0xc7630104) /* finn: Evaluated from "(FINN_MMU_VIDMEM_ACCESS_BIT_BUFFER_VIDMEM_ACCESS_BIT_BUFFER_INTERFACE_ID << 8) | NVC763_CTRL_VIDMEM_ACCESS_BIT_PUT_OFFSET_PARAMS_MESSAGE_ID" */ + +#define NVC763_CTRL_VIDMEM_ACCESS_BIT_PUT_OFFSET_PARAMS_MESSAGE_ID (0x4U) + +typedef struct NVC763_CTRL_VIDMEM_ACCESS_BIT_PUT_OFFSET_PARAMS { + NvU32 vidmemAccessBitPutOffset; +} NVC763_CTRL_VIDMEM_ACCESS_BIT_PUT_OFFSET_PARAMS; +/* _ctrlc763_h_ */ diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/common/sdk/nvidia/inc/ctrl/ctrlc86f.h nvidia-open-gpu-kernel-modules-535.161.08/src/common/sdk/nvidia/inc/ctrl/ctrlc86f.h --- nvidia-open-gpu-kernel-modules-525.147.05/src/common/sdk/nvidia/inc/ctrl/ctrlc86f.h 2023-10-25 20:22:25.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/common/sdk/nvidia/inc/ctrl/ctrlc86f.h 2024-03-05 22:15:20.000000000 +0000 @@ -27,7 +27,7 @@ // // This file was generated with FINN, an NVIDIA coding tool. -// Source file: ctrl/ctrlc86f.finn +// Source file: ctrl/ctrlc86f.finn // diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/common/sdk/nvidia/inc/ctrl/ctrlcb33.h nvidia-open-gpu-kernel-modules-535.161.08/src/common/sdk/nvidia/inc/ctrl/ctrlcb33.h --- nvidia-open-gpu-kernel-modules-525.147.05/src/common/sdk/nvidia/inc/ctrl/ctrlcb33.h 1970-01-01 00:00:00.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/common/sdk/nvidia/inc/ctrl/ctrlcb33.h 2024-03-05 22:15:20.000000000 +0000 @@ -0,0 +1,385 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2021-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#pragma once + +#include + +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: ctrl/ctrlcb33.finn +// + + + +#include "nvcfg_sdk.h" +#include "ctrl/ctrlxxxx.h" +/* NV_CONF_COMPUTE control commands and parameters */ + +#define NV_CONF_COMPUTE_CTRL_CMD(cat,idx) NVXXXX_CTRL_CMD(0xCB33, NVCB33_CTRL_##cat, idx) + +#define NVCB33_CTRL_RESERVED (0x00) +#define NVCB33_CTRL_CONF_COMPUTE (0x01) + +/* + * NV_CONF_COMPUTE_CTRL_CMD_NULL + * + * This command does nothing. + * This command does not take any parameters. + * + * Possible return values: + * NV_OK + */ +#define NV_CONF_COMPUTE_CTRL_CMD_NULL (0xcb330000) /* finn: Evaluated from "(FINN_NV_CONFIDENTIAL_COMPUTE_RESERVED_INTERFACE_ID << 8) | 0x0" */ + + + + + +/* + * NV_CONF_COMPUTE_CTRL_CMD_SYSTEM_GET_CAPABILITIES + * This control call returns overall system and gpu capabilities + * + * Final operating environment depends on a lot of factors: + * APM: Ampere Protected Memory + * HCC: Hopper Confidential Compute + * --------------------------------------------------------------------------- + * SrNo CPU TEE GPU TEE GPU Platform GPU mode SW Status System Env + * --------------------------------------------------------------------------- + * 1 AMD SEV APM/HCC Silicon Production Production Production + * 2 AMD SEV APM/HCC Silicon Production Development Simulation + * 3 APM/HCC Debug Simulation + * 4 Non SEV APM/HCC Simulation + * 5 APM/HCC FMOD/EMU/RTL Simulation + * --------------------------------------------------------------------------- + * + * Prameters: + * cpuCapability: [OUT] + * This indicates if cpu is capable of AMD SEV + * gpusCapability: [OUT] + * This indicates if all gpus in the system support APM/HCC. + * This field doesn't mean APM/HCC is enabled. + * environment: [OUT] + * System environment can be production or simulation + * ccFeature: [OUT] + * Specifies if all gpus in the system have APM/HCC feature enabled + * CC feature can be enabled/disabled using this control call: + * NV_CONF_COMPUTE_CTRL_CMD_SYSTEM_SET_CC_FEATURE + * devToolsMode: [OUT] + * Dev tools mode is used for debugging/profiling + * Dev tools mode is set at system level and implies that all GPUs in + * the system have this mode enabled/disabled + * + * cpuCapability, gpusCapability & environment are determined by the + * driver and cannot be modified later on + * + * Possible return values: + * NV_OK + * NV_ERR_NOT_SUPPORTED + * NV_ERR_INVALID_ARGUMENT + * NV_ERR_INVALID_OBJECT_HANDLE + * NV_ERR_INVALID_CLIENT + * NV_ERR_OBJECT_NOT_FOUND + */ +#define NV_CONF_COMPUTE_CTRL_CMD_SYSTEM_GET_CAPABILITIES (0xcb330101) /* finn: Evaluated from "(FINN_NV_CONFIDENTIAL_COMPUTE_CONF_COMPUTE_INTERFACE_ID << 8) | 0x1" */ + +#define NV_CONF_COMPUTE_SYSTEM_CPU_CAPABILITY_NONE 0 +#define NV_CONF_COMPUTE_SYSTEM_CPU_CAPABILITY_AMD_SEV 1 +#define NV_CONF_COMPUTE_SYSTEM_CPU_CAPABILITY_INTEL_TDX 2 + +#define NV_CONF_COMPUTE_SYSTEM_GPUS_CAPABILITY_NONE 0 +#define NV_CONF_COMPUTE_SYSTEM_GPUS_CAPABILITY_APM 1 +#define NV_CONF_COMPUTE_SYSTEM_GPUS_CAPABILITY_HCC 2 + +#define NV_CONF_COMPUTE_SYSTEM_ENVIRONMENT_UNAVAILABLE 0 +#define NV_CONF_COMPUTE_SYSTEM_ENVIRONMENT_SIM 1 +#define NV_CONF_COMPUTE_SYSTEM_ENVIRONMENT_PROD 2 + +#define NV_CONF_COMPUTE_SYSTEM_FEATURE_DISABLED 0 +#define NV_CONF_COMPUTE_SYSTEM_FEATURE_APM_ENABLED 1 +#define NV_CONF_COMPUTE_SYSTEM_FEATURE_HCC_ENABLED 2 + +#define NV_CONF_COMPUTE_SYSTEM_DEVTOOLS_MODE_DISABLED 0 +#define NV_CONF_COMPUTE_SYSTEM_DEVTOOLS_MODE_ENABLED 1 + +typedef struct NV_CONF_COMPUTE_CTRL_CMD_SYSTEM_GET_CAPABILITIES_PARAMS { + NvU8 cpuCapability; + NvU8 gpusCapability; + NvU8 environment; + NvU8 ccFeature; + NvU8 devToolsMode; +} NV_CONF_COMPUTE_CTRL_CMD_SYSTEM_GET_CAPABILITIES_PARAMS; + +/* + * NV_CONF_COMPUTE_CTRL_CMD_SYSTEM_GET_GPUS_STATE + * This control call can be used to determine if all GPUs are ready to accept + * work form clients. + * + * bAcceptClientRequest: [OUT] + * NV_TRUE: all gpus accepting client work requests + * NV_FALSE: all gpus blocking client work requests + * + * Possible return values: + * NV_OK + * NV_ERR_NOT_SUPPORTED + * NV_ERR_INVALID_ARGUMENT + * NV_ERR_INVALID_OBJECT_HANDLE + * NV_ERR_INVALID_CLIENT + * NV_ERR_OBJECT_NOT_FOUND + */ +#define NV_CONF_COMPUTE_CTRL_CMD_SYSTEM_GET_GPUS_STATE (0xcb330104) /* finn: Evaluated from "(FINN_NV_CONFIDENTIAL_COMPUTE_CONF_COMPUTE_INTERFACE_ID << 8) | 0x4" */ + +typedef struct NV_CONF_COMPUTE_CTRL_CMD_SYSTEM_GET_GPUS_STATE_PARAMS { + NvBool bAcceptClientRequest; +} NV_CONF_COMPUTE_CTRL_CMD_SYSTEM_GET_GPUS_STATE_PARAMS; + +/* + * NV_CONF_COMPUTE_CTRL_CMD_SYSTEM_SET_GPUS_STATE + * This control call can be used to set gpu state to accept client requests + * or to block client requests + * This is a PRIVILEGED control call and can be set via admin tools + * + * bAcceptClientRequest:[IN] + * NV_TRUE: set all gpus state to accept client work requests + * NV_FALSE: set all gpus state to block client work requests + * + * Possible return values: + * NV_OK + * NV_ERR_NOT_SUPPORTED + * NV_ERR_INVALID_ARGUMENT + * NV_ERR_INVALID_OBJECT_HANDLE + * NV_ERR_INVALID_CLIENT + * NV_ERR_OBJECT_NOT_FOUND + * NV_ERR_INSUFFICIENT_PERMISSIONS + */ +#define NV_CONF_COMPUTE_CTRL_CMD_SYSTEM_SET_GPUS_STATE (0xcb330105) /* finn: Evaluated from "(FINN_NV_CONFIDENTIAL_COMPUTE_CONF_COMPUTE_INTERFACE_ID << 8) | 0x5" */ + +typedef struct NV_CONF_COMPUTE_CTRL_CMD_SYSTEM_SET_GPUS_STATE_PARAMS { + NvBool bAcceptClientRequest; +} NV_CONF_COMPUTE_CTRL_CMD_SYSTEM_SET_GPUS_STATE_PARAMS; + +/* + * NV_CONF_COMPUTE_CTRL_CMD_GPU_GET_VIDMEM_SIZE + * This control call returns protected and unprotected vidmem size + * + * hSubDevice: [IN] + * subdevice handle for the gpu whose vidmem size is requested + * protectedMemSizeInKb: [OUT] + * total protected memory size in kB + * unprotectedMemSizeInKb: [OUT] + * total unprotected memory size in kB + * + * Possible return values: + * NV_OK + * NV_ERR_NOT_SUPPORTED + * NV_ERR_INVALID_ARGUMENT + * NV_ERR_INVALID_OBJECT_HANDLE + * NV_ERR_INVALID_CLIENT + * NV_ERR_OBJECT_NOT_FOUND + */ +#define NV_CONF_COMPUTE_CTRL_CMD_GPU_GET_VIDMEM_SIZE (0xcb330106) /* finn: Evaluated from "(FINN_NV_CONFIDENTIAL_COMPUTE_CONF_COMPUTE_INTERFACE_ID << 8) | 0x6" */ + +typedef struct NV_CONF_COMPUTE_CTRL_CMD_GPU_GET_VIDMEM_SIZE_PARAMS { + NvHandle hSubDevice; + NV_DECLARE_ALIGNED(NvU64 protectedMemSizeInKb, 8); + NV_DECLARE_ALIGNED(NvU64 unprotectedMemSizeInKb, 8); +} NV_CONF_COMPUTE_CTRL_CMD_GPU_GET_VIDMEM_SIZE_PARAMS; + +/* + * NV_CONF_COMPUTE_CTRL_CMD_GPU_SET_VIDMEM_SIZE + * This control call updates protected and unprotected vidmem size. + * All memory is protected if APM/HCC is enabled. User can override + * unprotectedMemSizeInKb and that will adjust protectedMemSizeInKb accordingly. + * This is a PRIVILEGED control call and can be set via tools like nvidia-smi. + * Vidmem size can be updated after driver load and before any client FB + * allocations are made. + * + * hSubDevice: [IN] + * subdevice handle for the gpu whose vidmem size is requested + * protectedMemSizeInKb: [OUT] + * total protected memory size in kB + * unprotectedMemSizeInKb: [IN/OUT] + * total unprotected memory size in kB + * + * Possible return values: + * NV_OK + * NV_ERR_NOT_SUPPORTED + * NV_ERR_INVALID_ARGUMENT + * NV_ERR_INVALID_OBJECT_HANDLE + * NV_ERR_INVALID_CLIENT + * NV_ERR_OBJECT_NOT_FOUND + * NV_ERR_INSUFFICIENT_PERMISSIONS + */ +#define NV_CONF_COMPUTE_CTRL_CMD_GPU_SET_VIDMEM_SIZE (0xcb330107) /* finn: Evaluated from "(FINN_NV_CONFIDENTIAL_COMPUTE_CONF_COMPUTE_INTERFACE_ID << 8) | 0x7" */ + +typedef struct NV_CONF_COMPUTE_CTRL_CMD_GPU_SET_VIDMEM_SIZE_PARAMS { + NvHandle hSubDevice; + NV_DECLARE_ALIGNED(NvU64 protectedMemSizeInKb, 8); + NV_DECLARE_ALIGNED(NvU64 unprotectedMemSizeInKb, 8); +} NV_CONF_COMPUTE_CTRL_CMD_GPU_SET_VIDMEM_SIZE_PARAMS; + +/* + * NV_CONF_COMPUTE_CTRL_CMD_GET_NUM_SUPPORTED_CC_SECURE_CHANNELS + * This control call returns the max number of AES capable channels SEC2 and CE support. + * + * hSubDevice: [IN] + * subdevice handle for the GPU queried + * numSupportedSec2CCSecureChannels: [OUT] + * Max number of AES capable channels SEC2 supports + * numSupportedCeCCSecureChannels: [OUT] + * Max number of channels CE supports with encrypt/decrypt + * + * Possible return values: + * NV_OK + * NV_ERR_NOT_SUPPORTED + * NV_ERR_INVALID_ARGUMENT + * NV_ERR_INVALID_OBJECT_HANDLE + * NV_ERR_INVALID_CLIENT + * NV_ERR_OBJECT_NOT_FOUND + */ +#define NV_CONF_COMPUTE_CTRL_CMD_GET_NUM_SUPPORTED_CC_SECURE_CHANNELS (0xcb330108) /* finn: Evaluated from "(FINN_NV_CONFIDENTIAL_COMPUTE_CONF_COMPUTE_INTERFACE_ID << 8) | 0x8" */ + +#define NV_CONF_COMPUTE_CTRL_CMD_GET_NUM_SUPPORTED_CC_SECURE_CHANNELS_PARAMS_MESSAGE_ID (0x8U) + +typedef struct NV_CONF_COMPUTE_CTRL_CMD_GET_NUM_SUPPORTED_CC_SECURE_CHANNELS_PARAMS { + NvHandle hSubDevice; + NvU32 numSupportedSec2CCSecureChannels; + NvU32 numSupportedCeCCSecureChannels; +} NV_CONF_COMPUTE_CTRL_CMD_GET_NUM_SUPPORTED_CC_SECURE_CHANNELS_PARAMS; + +/* + * NV_CONF_COMPUTE_CTRL_CMD_GET_GPU_CERTIFICATE + * This control call returns the GPU session certificate for the specified GPU. + * The certificate size is the maximum of the certificate size of APM and CC. + * + * hSubDevice: [IN] + * Subdevice handle for the GPU queried + * certChain: [OUT] + * Certificate chain for the GPU queried + * certChainSize: [OUT] + * Actual size of certChain data + * attestationCertChain: [OUT] + * Attestation certificate chain for the GPU queried + * attestationCertChainSize: [OUT] + * Actual size of attestationCertChain data + * + * Possible return values: + * NV_OK + * NV_ERR_NOT_SUPPORTED + * NV_ERR_INVALID_ARGUMENT + * NV_ERR_INVALID_OBJECT_HANDLE + * NV_ERR_INVALID_CLIENT + * NV_ERR_OBJECT_NOT_FOUND + */ +#define NV_CONF_COMPUTE_CTRL_CMD_GET_GPU_CERTIFICATE (0xcb330109) /* finn: Evaluated from "(FINN_NV_CONFIDENTIAL_COMPUTE_CONF_COMPUTE_INTERFACE_ID << 8) | 0x9" */ + +#define NV_CONF_COMPUTE_CERT_CHAIN_MAX_SIZE 0x1000 +#define NV_CONF_COMPUTE_ATTESTATION_CERT_CHAIN_MAX_SIZE 0x1400 + +#define NV_CONF_COMPUTE_CTRL_CMD_GET_GPU_CERTIFICATE_PARAMS_MESSAGE_ID (0x9U) + +typedef struct NV_CONF_COMPUTE_CTRL_CMD_GET_GPU_CERTIFICATE_PARAMS { + NvHandle hSubDevice; + NvU8 certChain[NV_CONF_COMPUTE_CERT_CHAIN_MAX_SIZE]; + NvU32 certChainSize; + NvU8 attestationCertChain[NV_CONF_COMPUTE_ATTESTATION_CERT_CHAIN_MAX_SIZE]; + NvU32 attestationCertChainSize; +} NV_CONF_COMPUTE_CTRL_CMD_GET_GPU_CERTIFICATE_PARAMS; + + /* + * NV_CONF_COMPUTE_CTRL_CMD_GET_GPU_ATTESTATION + * This control call returns the GPU attestation report for the specified GPU. + * The attestation report size is the maximum of the attestation report size of APM and CC. + * + * hSubDevice: [IN] + * Subdevice handle for the GPU queried + * nonce: [IN] + * spdm supports 32 bytes on nonce + * attestationReport: [OUT] + * Attestation report of the GPU queried + * attestationReportSize: [OUT] + * Actual size of the report + * isCecAttestationReportPresent : [OUT] + * Indicates if the next 2 feilds are valid + * cecAttestationReport: [OUT] + * Cec attestation report for the gpu queried + * cecAttestationReportSize: [OUT] + * Actual size of the cec attestation report + * + * Possible return values: + * NV_OK + * NV_ERR_NOT_SUPPORTED + * NV_ERR_INVALID_ARGUMENT + * NV_ERR_INVALID_OBJECT_HANDLE + * NV_ERR_INVALID_CLIENT + * NV_ERR_OBJECT_NOT_FOUND + */ +#define NV_CONF_COMPUTE_CTRL_CMD_GET_GPU_ATTESTATION_REPORT (0xcb33010a) /* finn: Evaluated from "(FINN_NV_CONFIDENTIAL_COMPUTE_CONF_COMPUTE_INTERFACE_ID << 8) | 0xA" */ + +#define NV_CONF_COMPUTE_GPU_ATTESTATION_REPORT_MAX_SIZE 0x2000 +#define NV_CONF_COMPUTE_GPU_CEC_ATTESTATION_REPORT_MAX_SIZE 0x1000 +#define NV_CONF_COMPUTE_NONCE_SIZE 0x20 + +#define NV_CONF_COMPUTE_CTRL_CMD_GET_GPU_ATTESTATION_REPORT_PARAMS_MESSAGE_ID (0xAU) + +typedef struct NV_CONF_COMPUTE_CTRL_CMD_GET_GPU_ATTESTATION_REPORT_PARAMS { + NvHandle hSubDevice; + NvU8 nonce[NV_CONF_COMPUTE_NONCE_SIZE]; + NvU8 attestationReport[NV_CONF_COMPUTE_GPU_ATTESTATION_REPORT_MAX_SIZE]; + NvU32 attestationReportSize; + NvBool isCecAttestationReportPresent; + NvU8 cecAttestationReport[NV_CONF_COMPUTE_GPU_CEC_ATTESTATION_REPORT_MAX_SIZE]; + NvU32 cecAttestationReportSize; +} NV_CONF_COMPUTE_CTRL_CMD_GET_GPU_ATTESTATION_REPORT_PARAMS; + +/* + * NV_CONF_COMPUTE_CTRL_CMD_GPU_GET_NUM_SECURE_CHANNELS + * This control call returns the max number of Conf Compute capable channels SEC2 and CE support. + * + * hSubDevice: [IN] + * subdevice handle for the GPU queried + * maxSec2Channels: [OUT] + * Max number of conf compute capable channels SEC2 supports + * maxCeChannels: [OUT] + * Max number of channels CE supports with encrypt/decrypt + * + * Possible return values: + * NV_OK + * NV_ERR_NOT_SUPPORTED + * NV_ERR_INVALID_ARGUMENT + * NV_ERR_INVALID_OBJECT_HANDLE + * NV_ERR_INVALID_CLIENT + * NV_ERR_OBJECT_NOT_FOUND + */ +#define NV_CONF_COMPUTE_CTRL_CMD_GPU_GET_NUM_SECURE_CHANNELS (0xcb33010b) /* finn: Evaluated from "(FINN_NV_CONFIDENTIAL_COMPUTE_CONF_COMPUTE_INTERFACE_ID << 8) | 0xB" */ + +#define NV_CONF_COMPUTE_CTRL_CMD_GPU_GET_NUM_SECURE_CHANNELS_PARAMS_MESSAGE_ID (0xBU) + +typedef struct NV_CONF_COMPUTE_CTRL_CMD_GPU_GET_NUM_SECURE_CHANNELS_PARAMS { + NvHandle hSubDevice; + NvU32 maxSec2Channels; + NvU32 maxCeChannels; +} NV_CONF_COMPUTE_CTRL_CMD_GPU_GET_NUM_SECURE_CHANNELS_PARAMS; + +/* _ctrlcb33_h_ */ + diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/common/sdk/nvidia/inc/ctrl/ctrlcbca.h nvidia-open-gpu-kernel-modules-535.161.08/src/common/sdk/nvidia/inc/ctrl/ctrlcbca.h --- nvidia-open-gpu-kernel-modules-525.147.05/src/common/sdk/nvidia/inc/ctrl/ctrlcbca.h 2023-10-25 20:22:25.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/common/sdk/nvidia/inc/ctrl/ctrlcbca.h 2024-03-05 22:15:20.000000000 +0000 @@ -27,7 +27,7 @@ // // This file was generated with FINN, an NVIDIA coding tool. -// Source file: ctrl/ctrlcbca.finn +// Source file: ctrl/ctrlcbca.finn // #include "ctrl/ctrlxxxx.h" diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/common/sdk/nvidia/inc/ctrl/ctrlxxxx.h nvidia-open-gpu-kernel-modules-535.161.08/src/common/sdk/nvidia/inc/ctrl/ctrlxxxx.h --- nvidia-open-gpu-kernel-modules-525.147.05/src/common/sdk/nvidia/inc/ctrl/ctrlxxxx.h 2023-10-25 20:22:25.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/common/sdk/nvidia/inc/ctrl/ctrlxxxx.h 2024-03-05 22:15:20.000000000 +0000 @@ -23,9 +23,11 @@ #pragma once +#include + // // This file was generated with FINN, an NVIDIA coding tool. -// Source file: ctrl/ctrlxxxx.finn +// Source file: ctrl/ctrlxxxx.finn // @@ -65,3 +67,8 @@ #define NVxxxx_CTRL_LEGACY_PRIVILEGED (0xC0) #define NVxxxx_CTRL_LEGACY_NON_PRIVILEGED (0x80) + +typedef struct NVXXXX_CTRL_XXX_INFO { + NvU32 index; + NvU32 data; +} NVXXXX_CTRL_XXX_INFO; diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/common/sdk/nvidia/inc/finn_rm_api.h nvidia-open-gpu-kernel-modules-535.161.08/src/common/sdk/nvidia/inc/finn_rm_api.h --- nvidia-open-gpu-kernel-modules-525.147.05/src/common/sdk/nvidia/inc/finn_rm_api.h 2023-10-25 20:22:25.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/common/sdk/nvidia/inc/finn_rm_api.h 1970-01-01 00:00:00.000000000 +0000 @@ -1,709 +0,0 @@ -#pragma once - -// -// This file was generated with FINN, an NVIDIA coding tool. -// - - -#include - - -#include -#include - -#define FINN_INTERFACE_ID(T) (T ## _INTERFACE_ID) -#define FINN_MESSAGE_ID(T) (T ## _MESSAGE_ID) - -#if (defined(__cplusplus) && __cplusplus >= 201103L) || (defined(_MSVC_LANG) && _MSVC_LANG >= 201103L) -#define FINN_OFFSETOF(T,f) (offsetof(T, f)) -#else -#define FINN_OFFSETOF(T,f) ((NvU64)&((T*)0)->f) -#endif - -#if !defined(_MSC_VER) && (defined(__STDC_VERSION__) && __STDC_VERSION__ >= 201112L) && !defined(__arm) -#define FINN_PACK_COMPOSITE(b) b __attribute__ ((packed)) -#else -#define FINN_PACK_COMPOSITE(b) b -#endif - -/* - * FINN serialization version. A version mismatch indicates incompatibility - * between the serializer and the deserializer. - * - * WARNING: Current serialization version is 0. This is a pre-release version of - * serialization and is only intended to be used in a driver and client compiled - * together. DO NOT use this in firmware or versioned clients. - */ -#define FINN_SERIALIZATION_VERSION 0 - -/* - * FINN compiler version - */ -#define FINN_VERSION_MAJOR 1 -#define FINN_VERSION_MINOR 15 -#define FINN_VERSION_PATCH 0 - -typedef struct FINN_RM_API -{ - NV_DECLARE_ALIGNED(NvU64 version, 8); - NV_DECLARE_ALIGNED(NvU64 payloadSize, 8); - NV_DECLARE_ALIGNED(NvU64 interface, 8); - NV_DECLARE_ALIGNED(NvU64 message, 8); -} FINN_RM_API; - - -/*! - * @brief Serializes an RM API control params struct and copies it into the - * serialization buffer as a FINN message. - * - * @note FinnRmApiSerializeDown is for serializing down the call stack. - * - * FinnRmApiSerializeUp is for serializing up the call stack. It - * frees memory allocated by FinnRmApiDeserializeDown. Use only - * when handling RM API control requests. - * - * @warning One of these may be unimplemented depending on platform. If both - * are implemented, misuse causes memory corruption and memory leaks. - * - * @param[in] interface FINN interface ID of the param struct. - * @param[in] message FINN message ID of the param struct. - * @param[in] src Pointer to the source param struct from which to - * copy the data. - * @param[in, out] dst Double pointer to the destination buffer into - * which to copy the data. *dst will be set to - * *dst + serialized size on success and to the - * location of failed serialization on failure. - * @param[in] dst_size Maximum size of the destination buffer measured in - * `NvU8` units. - * - * @retval NV_OK Serialization successful. - * @retval NV_ERR_INVALID_ARGUMENT Bad function arguments, invalid union - * selector, or invalid enum value. - * @retval NV_ERR_NOT_SUPPORTED Unserializable or nonexistent ID. - * @retval NV_ERR_NOT_COMPATIBLE Container count too large. - * @retval NV_ERR_OUT_OF_RANGE Ranged field exceeded bounds. - * @retval NV_ERR_BUFFER_TOO_SMALL Destination buffer size too small. - */ -/**@{*/ -NV_STATUS FinnRmApiSerializeUp(NvU64 interface, NvU64 message, const void *src, NvU8 **dst, NvLength dst_size); -NV_STATUS FinnRmApiSerializeDown(NvU64 interface, NvU64 message, const void *src, NvU8 **dst, NvLength dst_size); -/**@}*/ - - -/*! - * @brief The following APIs deserialize a FINN message from the serialization - * buffer and copy it into an RM API control params struct. - * - * @note FinnRmApiDeserializeDown is for deserializing down the call stack. It - * allocates deep buffers for primitive pointers in the serialization - * buffer, assuming that it remains in memory. Use only when handling - * RM API control requests. - * - * FinnRmApiDeserializeUp is for deserializing up the call stack. It - * copies deep buffers of primitive pointers into the params struct, - * assuming that memory is already allocated for them. Use only when - * receiving RM API control results. - * - * @warning One of these may be unimplemented depending on platform. If both - * are implemented, misuse causes memory corruption and memory leaks. - * - * @param[in, out] src Double pointer to the source buffer from which to - * copy the data. *src is set to *src + serialized - * size on success and to the location of failed - * deserialization on failure. - * @param[in] src_size Maximum size of the source buffer measured in - * `NvU8` units. - * @param[in, out] dst Pointer to the destination param struct into which - * to copy the data. - * @param[in] dst_size Size of the destination param struct measured in - * `char` units per `sizeof` operator. - * - * @retval NV_OK Deserialization successful. - * @retval NV_ERR_INVALID_ARGUMENT Bad function arguments, invalid union - * selector, invalid enum value, or - * mismatch between expected and actual - * serialized size. - * @retval NV_ERR_NOT_SUPPORTED Unserializable or nonexistent ID. - * @retval NV_ERR_OUT_OF_RANGE Ranged field exceeded bounds. - * @retval NV_ERR_BUFFER_TOO_SMALL Source/destination buffer too small. - * @retval NV_ERR_LIB_RM_VERSION_MISMATCH Version mismatch. - */ -/**@{*/ -NV_STATUS FinnRmApiDeserializeDown(NvU8 **src, NvLength src_size, void *dst, NvLength dst_size); -NV_STATUS FinnRmApiDeserializeUp(NvU8 **src, NvLength src_size, void *dst, NvLength dst_size); -/**@}*/ - -/*! - * @brief Calculates the serialized size of an RM API param struct. - * - * @param[in] interface FINN interface ID of the param struct. - * @param[in] message FINN message ID of the param struct. - * @param[in] src Pointer to the param struct. - * - * @retval Non-zero serialized size of param struct on success. - * @retval 0 if the API is unsupported by serialization or src is NULL. - */ -NvU64 FinnRmApiGetSerializedSize(NvU64 interface, NvU64 message, const NvP64 src); - -/*! - * @brief Fetches the unserialized size of an API param struct. - * - * @note The size is measured in `char` units like the `sizeof` operator. - * - * @param[in] interface FINN interface ID of the param struct. - * @param[in] message FINN message ID of the param struct. - * - * @retval Non-zero sizeof param struct on success. - * @retval 0 if the API is unsupported by serialization. - */ -NvU64 FinnRmApiGetUnserializedSize(NvU64 interface, NvU64 message); - -#define NV_RM_ALLOC_INTERFACE_INTERFACE_ID (0xA000U) -typedef FINN_RM_API NV_RM_ALLOC_INTERFACE; -#define FINN_NV01_ROOT_RESERVED_INTERFACE_ID (0x0U) -typedef FINN_RM_API FINN_NV01_ROOT_RESERVED; -#define FINN_NV01_ROOT_CLIENT_INTERFACE_ID (0xdU) -typedef FINN_RM_API FINN_NV01_ROOT_CLIENT; -#define FINN_NV01_ROOT_DIAG_INTERFACE_ID (0x4U) -typedef FINN_RM_API FINN_NV01_ROOT_DIAG; -#define FINN_NV01_ROOT_EVENT_INTERFACE_ID (0x5U) -typedef FINN_RM_API FINN_NV01_ROOT_EVENT; -#define FINN_NV01_ROOT_GPU_INTERFACE_ID (0x2U) -typedef FINN_RM_API FINN_NV01_ROOT_GPU; -#define FINN_NV01_ROOT_GPUACCT_INTERFACE_ID (0xbU) -typedef FINN_RM_API FINN_NV01_ROOT_GPUACCT; -#define FINN_NV01_ROOT_GSYNC_INTERFACE_ID (0x3U) -typedef FINN_RM_API FINN_NV01_ROOT_GSYNC; -#define FINN_NV01_ROOT_NVD_INTERFACE_ID (0x6U) -typedef FINN_RM_API FINN_NV01_ROOT_NVD; -#define FINN_NV01_ROOT_PROC_INTERFACE_ID (0x9U) -typedef FINN_RM_API FINN_NV01_ROOT_PROC; - -#define FINN_NV01_ROOT_SYNC_GPU_BOOST_INTERFACE_ID (0xaU) -typedef FINN_RM_API FINN_NV01_ROOT_SYNC_GPU_BOOST; -#define FINN_NV01_ROOT_SYSTEM_INTERFACE_ID (0x1U) -typedef FINN_RM_API FINN_NV01_ROOT_SYSTEM; -#define FINN_NV01_ROOT_OS_UNIX_INTERFACE_ID (0x3dU) -typedef FINN_RM_API FINN_NV01_ROOT_OS_UNIX; -#define FINN_NV01_ROOT_VGPU_INTERFACE_ID (0xcU) -typedef FINN_RM_API FINN_NV01_ROOT_VGPU; -#define FINN_NV01_ROOT_OS_WINDOWS_INTERFACE_ID (0x3fU) -typedef FINN_RM_API FINN_NV01_ROOT_OS_WINDOWS; -#define FINN_NV01_CONTEXT_DMA_RESERVED_INTERFACE_ID (0x200U) -typedef FINN_RM_API FINN_NV01_CONTEXT_DMA_RESERVED; -#define FINN_NV01_CONTEXT_DMA_DMA_INTERFACE_ID (0x201U) -typedef FINN_RM_API FINN_NV01_CONTEXT_DMA_DMA; -#define FINN_NV01_TIMER_RESERVED_INTERFACE_ID (0x400U) -typedef FINN_RM_API FINN_NV01_TIMER_RESERVED; -#define FINN_NV01_TIMER_TMR_INTERFACE_ID (0x401U) -typedef FINN_RM_API FINN_NV01_TIMER_TMR; -#define FINN_FABRIC_MANAGER_SESSION_RESERVED_INTERFACE_ID (0xf00U) -typedef FINN_RM_API FINN_FABRIC_MANAGER_SESSION_RESERVED; -#define FINN_FABRIC_MANAGER_SESSION_FM_INTERFACE_ID (0xf01U) -typedef FINN_RM_API FINN_FABRIC_MANAGER_SESSION_FM; -#define FINN_FABRIC_MANAGER_SESSION_IMEX_INTERFACE_ID (0xf02U) -typedef FINN_RM_API FINN_FABRIC_MANAGER_SESSION_IMEX; -#define FINN_NV0020_GPU_MANAGEMENT_RESERVED_INTERFACE_ID (0x2000U) -typedef FINN_RM_API FINN_NV0020_GPU_MANAGEMENT_RESERVED; -#define FINN_NV0020_GPU_MANAGEMENT_GPU_MGMT_INTERFACE_ID (0x2001U) -typedef FINN_RM_API FINN_NV0020_GPU_MANAGEMENT_GPU_MGMT; -#define FINN_NV01_MEMORY_SYSTEM_RESERVED_INTERFACE_ID (0x3e00U) -typedef FINN_RM_API FINN_NV01_MEMORY_SYSTEM_RESERVED; -#define FINN_NV01_MEMORY_SYSTEM_MEMORY_INTERFACE_ID (0x3e01U) -typedef FINN_RM_API FINN_NV01_MEMORY_SYSTEM_MEMORY; -#define FINN_NV01_ROOT_USER_RESERVED_INTERFACE_ID (0x4100U) -typedef FINN_RM_API FINN_NV01_ROOT_USER_RESERVED; -#define FINN_NV01_ROOT_USER_MEMORY_INTERFACE_ID (0x4101U) -typedef FINN_RM_API FINN_NV01_ROOT_USER_MEMORY; -#define FINN_NV04_DISPLAY_COMMON_RESERVED_INTERFACE_ID (0x7300U) -typedef FINN_RM_API FINN_NV04_DISPLAY_COMMON_RESERVED; -#define FINN_NV04_DISPLAY_COMMON_DFP_INTERFACE_ID (0x7311U) -typedef FINN_RM_API FINN_NV04_DISPLAY_COMMON_DFP; -#define FINN_NV04_DISPLAY_COMMON_DP_INTERFACE_ID (0x7313U) -typedef FINN_RM_API FINN_NV04_DISPLAY_COMMON_DP; - -#define FINN_NV04_DISPLAY_COMMON_INTERNAL_INTERFACE_ID (0x7304U) -typedef FINN_RM_API FINN_NV04_DISPLAY_COMMON_INTERNAL; - -#define FINN_NV04_DISPLAY_COMMON_SPECIFIC_INTERFACE_ID (0x7302U) -typedef FINN_RM_API FINN_NV04_DISPLAY_COMMON_SPECIFIC; -#define FINN_NV04_DISPLAY_COMMON_STEREO_INTERFACE_ID (0x7317U) -typedef FINN_RM_API FINN_NV04_DISPLAY_COMMON_STEREO; - -#define FINN_NV04_DISPLAY_COMMON_SYSTEM_INTERFACE_ID (0x7301U) -typedef FINN_RM_API FINN_NV04_DISPLAY_COMMON_SYSTEM; -#define FINN_NV01_DEVICE_0_RESERVED_INTERFACE_ID (0x8000U) -typedef FINN_RM_API FINN_NV01_DEVICE_0_RESERVED; -#define FINN_NV01_DEVICE_0_BIF_INTERFACE_ID (0x8001U) -typedef FINN_RM_API FINN_NV01_DEVICE_0_BIF; -#define FINN_NV01_DEVICE_0_BSP_INTERFACE_ID (0x801cU) -typedef FINN_RM_API FINN_NV01_DEVICE_0_BSP; - -#define FINN_NV01_DEVICE_0_DMA_INTERFACE_ID (0x8018U) -typedef FINN_RM_API FINN_NV01_DEVICE_0_DMA; -#define FINN_NV01_DEVICE_0_FB_INTERFACE_ID (0x8013U) -typedef FINN_RM_API FINN_NV01_DEVICE_0_FB; -#define FINN_NV01_DEVICE_0_FIFO_INTERFACE_ID (0x8017U) -typedef FINN_RM_API FINN_NV01_DEVICE_0_FIFO; -#define FINN_NV01_DEVICE_0_GPU_INTERFACE_ID (0x8002U) -typedef FINN_RM_API FINN_NV01_DEVICE_0_GPU; -#define FINN_NV01_DEVICE_0_GR_INTERFACE_ID (0x8011U) -typedef FINN_RM_API FINN_NV01_DEVICE_0_GR; -#define FINN_NV01_DEVICE_0_HOST_INTERFACE_ID (0x8014U) -typedef FINN_RM_API FINN_NV01_DEVICE_0_HOST; -#define FINN_NV01_DEVICE_0_INTERNAL_INTERFACE_ID (0x8020U) -typedef FINN_RM_API FINN_NV01_DEVICE_0_INTERNAL; -#define FINN_NV01_DEVICE_0_MSENC_INTERFACE_ID (0x801bU) -typedef FINN_RM_API FINN_NV01_DEVICE_0_MSENC; -#define FINN_NV01_DEVICE_0_NVJPG_INTERFACE_ID (0x801fU) -typedef FINN_RM_API FINN_NV01_DEVICE_0_NVJPG; -#define FINN_NV01_DEVICE_0_PERF_INTERFACE_ID (0x8019U) -typedef FINN_RM_API FINN_NV01_DEVICE_0_PERF; - -#define FINN_NV01_DEVICE_0_RC_INTERFACE_ID (0x801dU) -typedef FINN_RM_API FINN_NV01_DEVICE_0_RC; -#define FINN_NV01_DEVICE_0_OS_UNIX_INTERFACE_ID (0x801eU) -typedef FINN_RM_API FINN_NV01_DEVICE_0_OS_UNIX; - -#define FINN_NV0090_KERNEL_GRAPHICS_CONTEXT_INTERFACE_ID (0x9001U) -typedef FINN_RM_API FINN_NV0090_KERNEL_GRAPHICS_CONTEXT; -#define FINN_IMEX_SESSION_INTERFACE_ID (0xf100U) -typedef FINN_RM_API FINN_IMEX_SESSION; -#define FINN_NV01_MEMORY_FABRIC_EXPORT_RESERVED_INTERFACE_ID (0xf400U) -typedef FINN_RM_API FINN_NV01_MEMORY_FABRIC_EXPORT_RESERVED; -#define FINN_NV01_MEMORY_FABRIC_EXPORT_EXPORT_INTERFACE_ID (0xf401U) -typedef FINN_RM_API FINN_NV01_MEMORY_FABRIC_EXPORT_EXPORT; -#define FINN_NV01_MEMORY_FABRIC_IMPORT_RESERVED_INTERFACE_ID (0xf500U) -typedef FINN_RM_API FINN_NV01_MEMORY_FABRIC_IMPORT_RESERVED; -#define FINN_NV01_MEMORY_FABRIC_IMPORT_IMPORT_INTERFACE_ID (0xf501U) -typedef FINN_RM_API FINN_NV01_MEMORY_FABRIC_IMPORT_IMPORT; -#define FINN_NV_MEMORY_FABRIC_EXPORT_RESERVED_INTERFACE_ID (0xf700U) -typedef FINN_RM_API FINN_NV_MEMORY_FABRIC_EXPORT_RESERVED; -#define FINN_NV_MEMORY_FABRIC_EXPORT_INTERFACE_ID (0xf701U) -typedef FINN_RM_API FINN_NV_MEMORY_FABRIC_EXPORT; -#define FINN_NV_MEMORY_FABRIC_RESERVED_INTERFACE_ID (0xf800U) -typedef FINN_RM_API FINN_NV_MEMORY_FABRIC_RESERVED; -#define FINN_NV_MEMORY_FABRIC_FABRIC_INTERFACE_ID (0xf801U) -typedef FINN_RM_API FINN_NV_MEMORY_FABRIC_FABRIC; -#define FINN_NV_MEMORY_FABRIC_IMPORT_V2_RESERVED_INTERFACE_ID (0xf900U) -typedef FINN_RM_API FINN_NV_MEMORY_FABRIC_IMPORT_V2_RESERVED; -#define FINN_NV_MEMORY_FABRIC_IMPORT_V2_IMPORT_INTERFACE_ID (0xf901U) -typedef FINN_RM_API FINN_NV_MEMORY_FABRIC_IMPORT_V2_IMPORT; -#define FINN_NV_MEMORY_FABRIC_EXPORTED_REF_RESERVED_INTERFACE_ID (0xfa00U) -typedef FINN_RM_API FINN_NV_MEMORY_FABRIC_EXPORTED_REF_RESERVED; -#define FINN_NV_MEMORY_FABRIC_EXPORTED_REF_EXPORT_REF_INTERFACE_ID (0xfa01U) -typedef FINN_RM_API FINN_NV_MEMORY_FABRIC_EXPORTED_REF_EXPORT_REF; -#define FINN_NV_MEMORY_FABRIC_IMPORTED_REF_RESERVED_INTERFACE_ID (0xfb00U) -typedef FINN_RM_API FINN_NV_MEMORY_FABRIC_IMPORTED_REF_RESERVED; -#define FINN_NV_MEMORY_FABRIC_IMPORTED_REF_IMPORT_REF_INTERFACE_ID (0xfb01U) -typedef FINN_RM_API FINN_NV_MEMORY_FABRIC_IMPORTED_REF_IMPORT_REF; -#define FINN_NV_MEMORY_MULTICAST_FABRIC_RESERVED_INTERFACE_ID (0xfd00U) -typedef FINN_RM_API FINN_NV_MEMORY_MULTICAST_FABRIC_RESERVED; -#define FINN_NV_MEMORY_MULTICAST_FABRIC_FABRIC_INTERFACE_ID (0xfd01U) -typedef FINN_RM_API FINN_NV_MEMORY_MULTICAST_FABRIC_FABRIC; -#define FINN_NV_MEMORY_MAPPER_INTERFACE_ID (0x00FE00U) -typedef FINN_RM_API FINN_NV_MEMORY_MAPPER; - -#define FINN_NV20_SUBDEVICE_0_RESERVED_INTERFACE_ID (0x208000U) -typedef FINN_RM_API FINN_NV20_SUBDEVICE_0_RESERVED; -#define FINN_NV20_SUBDEVICE_0_BIOS_INTERFACE_ID (0x208008U) -typedef FINN_RM_API FINN_NV20_SUBDEVICE_0_BIOS; -#define FINN_NV20_SUBDEVICE_0_BUS_INTERFACE_ID (0x208018U) -typedef FINN_RM_API FINN_NV20_SUBDEVICE_0_BUS; -#define FINN_NV20_SUBDEVICE_0_CE_INTERFACE_ID (0x20802aU) -typedef FINN_RM_API FINN_NV20_SUBDEVICE_0_CE; - -#define FINN_NV20_SUBDEVICE_0_CLK_INTERFACE_ID (0x208010U) -typedef FINN_RM_API FINN_NV20_SUBDEVICE_0_CLK; - -#define FINN_NV20_SUBDEVICE_0_DMA_INTERFACE_ID (0x208025U) -typedef FINN_RM_API FINN_NV20_SUBDEVICE_0_DMA; -#define FINN_NV20_SUBDEVICE_0_DMABUF_INTERFACE_ID (0x20803AU) -typedef FINN_RM_API FINN_NV20_SUBDEVICE_0_DMABUF; -#define FINN_NV20_SUBDEVICE_0_ECC_INTERFACE_ID (0x208034U) -typedef FINN_RM_API FINN_NV20_SUBDEVICE_0_ECC; - -#define FINN_NV20_SUBDEVICE_0_EVENT_INTERFACE_ID (0x208003U) -typedef FINN_RM_API FINN_NV20_SUBDEVICE_0_EVENT; - -#define FINN_NV20_SUBDEVICE_0_FB_INTERFACE_ID (0x208013U) -typedef FINN_RM_API FINN_NV20_SUBDEVICE_0_FB; -#define FINN_NV20_SUBDEVICE_0_FIFO_INTERFACE_ID (0x208011U) -typedef FINN_RM_API FINN_NV20_SUBDEVICE_0_FIFO; -#define FINN_NV20_SUBDEVICE_0_FLA_INTERFACE_ID (0x208035U) -typedef FINN_RM_API FINN_NV20_SUBDEVICE_0_FLA; -#define FINN_NV20_SUBDEVICE_0_FLCN_INTERFACE_ID (0x208031U) -typedef FINN_RM_API FINN_NV20_SUBDEVICE_0_FLCN; -#define FINN_NV20_SUBDEVICE_0_FUSE_INTERFACE_ID (0x208002U) -typedef FINN_RM_API FINN_NV20_SUBDEVICE_0_FUSE; - -#define FINN_NV20_SUBDEVICE_0_GPIO_INTERFACE_ID (0x208023U) -typedef FINN_RM_API FINN_NV20_SUBDEVICE_0_GPIO; - -#define FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID (0x208001U) -typedef FINN_RM_API FINN_NV20_SUBDEVICE_0_GPU; - -#define FINN_NV20_SUBDEVICE_0_GR_INTERFACE_ID (0x208012U) -typedef FINN_RM_API FINN_NV20_SUBDEVICE_0_GR; -#define FINN_NV20_SUBDEVICE_0_GRMGR_INTERFACE_ID (0x208038U) -typedef FINN_RM_API FINN_NV20_SUBDEVICE_0_GRMGR; -#define FINN_NV20_SUBDEVICE_0_GSP_INTERFACE_ID (0x208036U) -typedef FINN_RM_API FINN_NV20_SUBDEVICE_0_GSP; -#define FINN_NV20_SUBDEVICE_0_HSHUB_INTERFACE_ID (0x208041U) -typedef FINN_RM_API FINN_NV20_SUBDEVICE_0_HSHUB; -#define FINN_NV20_SUBDEVICE_0_I2C_INTERFACE_ID (0x208006U) -typedef FINN_RM_API FINN_NV20_SUBDEVICE_0_I2C; -#define FINN_NV20_SUBDEVICE_0_PMGR_INTERFACE_ID (0x208026U) -typedef FINN_RM_API FINN_NV20_SUBDEVICE_0_PMGR; - -#define FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID (0x20800aU) -typedef FINN_RM_API FINN_NV20_SUBDEVICE_0_INTERNAL; -#define FINN_NV20_SUBDEVICE_0_LPWR_INTERFACE_ID (0x208028U) -typedef FINN_RM_API FINN_NV20_SUBDEVICE_0_LPWR; - -#define FINN_NV20_SUBDEVICE_0_MC_INTERFACE_ID (0x208017U) -typedef FINN_RM_API FINN_NV20_SUBDEVICE_0_MC; - -#define FINN_NV20_SUBDEVICE_0_NVD_INTERFACE_ID (0x208024U) -typedef FINN_RM_API FINN_NV20_SUBDEVICE_0_NVD; - -#define FINN_NV20_SUBDEVICE_0_NVLINK_INTERFACE_ID (0x208030U) -typedef FINN_RM_API FINN_NV20_SUBDEVICE_0_NVLINK; - -#define FINN_NV20_SUBDEVICE_0_PERF_INTERFACE_ID (0x208020U) -typedef FINN_RM_API FINN_NV20_SUBDEVICE_0_PERF; - -#define FINN_NV20_SUBDEVICE_0_RC_INTERFACE_ID (0x208022U) -typedef FINN_RM_API FINN_NV20_SUBDEVICE_0_RC; -#define FINN_NV20_SUBDEVICE_0_SEC2_INTERFACE_ID (0x208042U) -typedef FINN_RM_API FINN_NV20_SUBDEVICE_0_SEC2; - -#define FINN_NV20_SUBDEVICE_0_TIMER_INTERFACE_ID (0x208004U) -typedef FINN_RM_API FINN_NV20_SUBDEVICE_0_TIMER; - -#define FINN_NV20_SUBDEVICE_0_OS_UNIX_INTERFACE_ID (0x20803dU) -typedef FINN_RM_API FINN_NV20_SUBDEVICE_0_OS_UNIX; -#define FINN_NV20_SUBDEVICE_0_VGPU_MGR_INTERNAL_INTERFACE_ID (0x208040U) -typedef FINN_RM_API FINN_NV20_SUBDEVICE_0_VGPU_MGR_INTERNAL; -#define FINN_NV20_SUBDEVICE_0_VOLT_INTERFACE_ID (0x208032U) -typedef FINN_RM_API FINN_NV20_SUBDEVICE_0_VOLT; - -#define FINN_NV2081_BINAPI_RESERVED_INTERFACE_ID (0x208100U) -typedef FINN_RM_API FINN_NV2081_BINAPI_RESERVED; -#define FINN_NV2081_BINAPI_INTERFACE_ID (0x208101U) -typedef FINN_RM_API FINN_NV2081_BINAPI; -#define FINN_NV2082_BINAPI_RESERVED_INTERFACE_ID (0x208200U) -typedef FINN_RM_API FINN_NV2082_BINAPI_RESERVED; -#define FINN_NV2082_BINAPI_INTERFACE_ID (0x208201U) -typedef FINN_RM_API FINN_NV2082_BINAPI; -#define FINN_NV20_SUBDEVICE_DIAG_RESERVED_INTERFACE_ID (0x208f00U) -typedef FINN_RM_API FINN_NV20_SUBDEVICE_DIAG_RESERVED; -#define FINN_NV20_SUBDEVICE_DIAG_BIF_INTERFACE_ID (0x208f07U) -typedef FINN_RM_API FINN_NV20_SUBDEVICE_DIAG_BIF; -#define FINN_NV20_SUBDEVICE_DIAG_BUS_INTERFACE_ID (0x208f18U) -typedef FINN_RM_API FINN_NV20_SUBDEVICE_DIAG_BUS; - -#define FINN_NV20_SUBDEVICE_DIAG_DMA_INTERFACE_ID (0x208f14U) -typedef FINN_RM_API FINN_NV20_SUBDEVICE_DIAG_DMA; -#define FINN_NV20_SUBDEVICE_DIAG_EVENT_INTERFACE_ID (0x208f10U) -typedef FINN_RM_API FINN_NV20_SUBDEVICE_DIAG_EVENT; -#define FINN_NV20_SUBDEVICE_DIAG_FB_INTERFACE_ID (0x208f05U) -typedef FINN_RM_API FINN_NV20_SUBDEVICE_DIAG_FB; -#define FINN_NV20_SUBDEVICE_DIAG_FBIO_INTERFACE_ID (0x208f0aU) -typedef FINN_RM_API FINN_NV20_SUBDEVICE_DIAG_FBIO; -#define FINN_NV20_SUBDEVICE_DIAG_FIFO_INTERFACE_ID (0x208f04U) -typedef FINN_RM_API FINN_NV20_SUBDEVICE_DIAG_FIFO; -#define FINN_NV20_SUBDEVICE_DIAG_GPU_INTERFACE_ID (0x208f11U) -typedef FINN_RM_API FINN_NV20_SUBDEVICE_DIAG_GPU; -#define FINN_NV20_SUBDEVICE_DIAG_GR_INTERFACE_ID (0x208f12U) -typedef FINN_RM_API FINN_NV20_SUBDEVICE_DIAG_GR; - -#define FINN_NV20_SUBDEVICE_DIAG_MMU_INTERFACE_ID (0x208f0bU) -typedef FINN_RM_API FINN_NV20_SUBDEVICE_DIAG_MMU; - -#define FINN_NV30_GSYNC_RESERVED_INTERFACE_ID (0x30f100U) -typedef FINN_RM_API FINN_NV30_GSYNC_RESERVED; -#define FINN_NV30_GSYNC_GSYNC_INTERFACE_ID (0x30f101U) -typedef FINN_RM_API FINN_NV30_GSYNC_GSYNC; -#define FINN_NV40_I2C_RESERVED_INTERFACE_ID (0x402c00U) -typedef FINN_RM_API FINN_NV40_I2C_RESERVED; -#define FINN_NV40_I2C_I2C_INTERFACE_ID (0x402c01U) -typedef FINN_RM_API FINN_NV40_I2C_I2C; -#define FINN_NV50_THIRD_PARTY_P2P_P2P_INTERFACE_ID (0x503c01U) -typedef FINN_RM_API FINN_NV50_THIRD_PARTY_P2P_P2P; -#define FINN_NV50_THIRD_PARTY_P2P_RESERVED_INTERFACE_ID (0x503c00U) -typedef FINN_RM_API FINN_NV50_THIRD_PARTY_P2P_RESERVED; -#define FINN_NV50_CHANNEL_GPFIFO_RESERVED_INTERFACE_ID (0x506f00U) -typedef FINN_RM_API FINN_NV50_CHANNEL_GPFIFO_RESERVED; -#define FINN_NV50_CHANNEL_GPFIFO_GPFIFO_INTERFACE_ID (0x506f01U) -typedef FINN_RM_API FINN_NV50_CHANNEL_GPFIFO_GPFIFO; -#define FINN_NV50_DISPLAY_RESERVED_INTERFACE_ID (0x507000U) -typedef FINN_RM_API FINN_NV50_DISPLAY_RESERVED; -#define FINN_NV50_DISPLAY_CHNCTL_INTERFACE_ID (0x507001U) -typedef FINN_RM_API FINN_NV50_DISPLAY_CHNCTL; -#define FINN_NV50_DISPLAY_EVENT_INTERFACE_ID (0x507009U) -typedef FINN_RM_API FINN_NV50_DISPLAY_EVENT; -#define FINN_NV50_DISPLAY_OR_INTERFACE_ID (0x507004U) -typedef FINN_RM_API FINN_NV50_DISPLAY_OR; -#define FINN_NV50_DISPLAY_RG_INTERFACE_ID (0x507002U) -typedef FINN_RM_API FINN_NV50_DISPLAY_RG; -#define FINN_NV50_DISPLAY_SEQ_INTERFACE_ID (0x507003U) -typedef FINN_RM_API FINN_NV50_DISPLAY_SEQ; -#define FINN_NV50_DISPLAY_SYSTEM_INTERFACE_ID (0x507007U) -typedef FINN_RM_API FINN_NV50_DISPLAY_SYSTEM; - -#define FINN_NV50_DEFERRED_API_CLASS_RESERVED_INTERFACE_ID (0x508000U) -typedef FINN_RM_API FINN_NV50_DEFERRED_API_CLASS_RESERVED; -#define FINN_NV50_DEFERRED_API_CLASS_DEFERRED_INTERFACE_ID (0x508001U) -typedef FINN_RM_API FINN_NV50_DEFERRED_API_CLASS_DEFERRED; -#define FINN_GT200_DEBUGGER_RESERVED_INTERFACE_ID (0x83de00U) -typedef FINN_RM_API FINN_GT200_DEBUGGER_RESERVED; -#define FINN_GT200_DEBUGGER_DEBUG_INTERFACE_ID (0x83de03U) -typedef FINN_RM_API FINN_GT200_DEBUGGER_DEBUG; -#define FINN_GT200_DEBUGGER_FIFO_INTERFACE_ID (0x83de02U) -typedef FINN_RM_API FINN_GT200_DEBUGGER_FIFO; -#define FINN_GT200_DEBUGGER_INTERNAL_INTERFACE_ID (0x83de04U) -typedef FINN_RM_API FINN_GT200_DEBUGGER_INTERNAL; - -#define FINN_NV9010_VBLANK_CALLBACK_RESERVED_INTERFACE_ID (0x901000U) -typedef FINN_RM_API FINN_NV9010_VBLANK_CALLBACK_RESERVED; -#define FINN_NV9010_VBLANK_CALLBACK_INTERFACE_ID (0x901001U) -typedef FINN_RM_API FINN_NV9010_VBLANK_CALLBACK; -#define FINN_FERMI_CONTEXT_SHARE_A_RESERVED_INTERFACE_ID (0x906700U) -typedef FINN_RM_API FINN_FERMI_CONTEXT_SHARE_A_RESERVED; -#define FINN_FERMI_CONTEXT_SHARE_A_TPC_PARTITION_INTERFACE_ID (0x906701U) -typedef FINN_RM_API FINN_FERMI_CONTEXT_SHARE_A_TPC_PARTITION; -#define FINN_FERMI_CONTEXT_SHARE_A_CWD_WATERMARK_INTERFACE_ID (0x906702U) -typedef FINN_RM_API FINN_FERMI_CONTEXT_SHARE_A_CWD_WATERMARK; -#define FINN_GF100_CHANNEL_GPFIFO_RESERVED_INTERFACE_ID (0x906f00U) -typedef FINN_RM_API FINN_GF100_CHANNEL_GPFIFO_RESERVED; -#define FINN_GF100_CHANNEL_GPFIFO_GPFIFO_INTERFACE_ID (0x906f01U) -typedef FINN_RM_API FINN_GF100_CHANNEL_GPFIFO_GPFIFO; -#define FINN_GF100_CHANNEL_GPFIFO_EVENT_INTERFACE_ID (0x906f02U) -typedef FINN_RM_API FINN_GF100_CHANNEL_GPFIFO_EVENT; -#define FINN_GF100_DISP_SW_RESERVED_INTERFACE_ID (0x907200U) -typedef FINN_RM_API FINN_GF100_DISP_SW_RESERVED; -#define FINN_GF100_DISP_SW_DISP_SW_INTERFACE_ID (0x907201U) -typedef FINN_RM_API FINN_GF100_DISP_SW_DISP_SW; -#define FINN_GF100_TIMED_SEMAPHORE_SW_RESERVED_INTERFACE_ID (0x907400U) -typedef FINN_RM_API FINN_GF100_TIMED_SEMAPHORE_SW_RESERVED; -#define FINN_GF100_TIMED_SEMAPHORE_SW_SEM_INTERFACE_ID (0x907401U) -typedef FINN_RM_API FINN_GF100_TIMED_SEMAPHORE_SW_SEM; -#define FINN_GF100_REMAPPER_RESERVED_INTERFACE_ID (0x907f00U) -typedef FINN_RM_API FINN_GF100_REMAPPER_RESERVED; -#define FINN_GF100_REMAPPER_REMAPPER_INTERFACE_ID (0x907f01U) -typedef FINN_RM_API FINN_GF100_REMAPPER_REMAPPER; -#define FINN_GF100_ZBC_CLEAR_RESERVED_INTERFACE_ID (0x909600U) -typedef FINN_RM_API FINN_GF100_ZBC_CLEAR_RESERVED; -#define FINN_GF100_ZBC_CLEAR_ZBC_INTERFACE_ID (0x909601U) -typedef FINN_RM_API FINN_GF100_ZBC_CLEAR_ZBC; -#define FINN_GF100_PROFILER_RESERVED_INTERFACE_ID (0x90cc00U) -typedef FINN_RM_API FINN_GF100_PROFILER_RESERVED; -#define FINN_GF100_PROFILER_HWPM_INTERFACE_ID (0x90cc01U) -typedef FINN_RM_API FINN_GF100_PROFILER_HWPM; -#define FINN_GF100_PROFILER_NVLINK_INTERFACE_ID (0x90cc02U) -typedef FINN_RM_API FINN_GF100_PROFILER_NVLINK; -#define FINN_GF100_PROFILER_POWER_INTERFACE_ID (0x90cc03U) -typedef FINN_RM_API FINN_GF100_PROFILER_POWER; -#define FINN_NV_EVENT_BUFFER_RESERVED_INTERFACE_ID (0x90cd00U) -typedef FINN_RM_API FINN_NV_EVENT_BUFFER_RESERVED; -#define FINN_NV_EVENT_BUFFER_EVENT_INTERFACE_ID (0x90cd01U) -typedef FINN_RM_API FINN_NV_EVENT_BUFFER_EVENT; -#define FINN_GF100_SUBDEVICE_GRAPHICS_RESERVED_INTERFACE_ID (0x90e000U) -typedef FINN_RM_API FINN_GF100_SUBDEVICE_GRAPHICS_RESERVED; -#define FINN_GF100_SUBDEVICE_GRAPHICS_GRAPHICS_INTERFACE_ID (0x90e001U) -typedef FINN_RM_API FINN_GF100_SUBDEVICE_GRAPHICS_GRAPHICS; -#define FINN_GF100_SUBDEVICE_FB_RESERVED_INTERFACE_ID (0x90e100U) -typedef FINN_RM_API FINN_GF100_SUBDEVICE_FB_RESERVED; -#define FINN_GF100_SUBDEVICE_FB_FB_INTERFACE_ID (0x90e101U) -typedef FINN_RM_API FINN_GF100_SUBDEVICE_FB_FB; -#define FINN_GF100_SUBDEVICE_MASTER_RESERVED_INTERFACE_ID (0x90e600U) -typedef FINN_RM_API FINN_GF100_SUBDEVICE_MASTER_RESERVED; -#define FINN_GF100_SUBDEVICE_MASTER_MASTER_INTERFACE_ID (0x90e601U) -typedef FINN_RM_API FINN_GF100_SUBDEVICE_MASTER_MASTER; -#define FINN_GF100_SUBDEVICE_INFOROM_RESERVED_INTERFACE_ID (0x90e700U) -typedef FINN_RM_API FINN_GF100_SUBDEVICE_INFOROM_RESERVED; -#define FINN_GF100_SUBDEVICE_INFOROM_BBX_INTERFACE_ID (0x90e701U) -typedef FINN_RM_API FINN_GF100_SUBDEVICE_INFOROM_BBX; -#define FINN_GF100_SUBDEVICE_INFOROM_RPR_INTERFACE_ID (0x90e702U) -typedef FINN_RM_API FINN_GF100_SUBDEVICE_INFOROM_RPR; - -#define FINN_GF100_HDACODEC_RESERVED_INTERFACE_ID (0x90ec00U) -typedef FINN_RM_API FINN_GF100_HDACODEC_RESERVED; -#define FINN_GF100_HDACODEC_HDACODEC_INTERFACE_ID (0x90ec01U) -typedef FINN_RM_API FINN_GF100_HDACODEC_HDACODEC; -#define FINN_FERMI_VASPACE_A_RESERVED_INTERFACE_ID (0x90f100U) -typedef FINN_RM_API FINN_FERMI_VASPACE_A_RESERVED; -#define FINN_FERMI_VASPACE_A_VASPACE_INTERFACE_ID (0x90f101U) -typedef FINN_RM_API FINN_FERMI_VASPACE_A_VASPACE; -#define FINN_KEPLER_CHANNEL_GROUP_A_RESERVED_INTERFACE_ID (0xa06c00U) -typedef FINN_RM_API FINN_KEPLER_CHANNEL_GROUP_A_RESERVED; -#define FINN_KEPLER_CHANNEL_GROUP_A_GPFIFO_INTERFACE_ID (0xa06c01U) -typedef FINN_RM_API FINN_KEPLER_CHANNEL_GROUP_A_GPFIFO; -#define FINN_KEPLER_CHANNEL_GROUP_A_INTERNAL_INTERFACE_ID (0xa06c02U) -typedef FINN_RM_API FINN_KEPLER_CHANNEL_GROUP_A_INTERNAL; -#define FINN_KEPLER_CHANNEL_GPFIFO_A_RESERVED_INTERFACE_ID (0xa06f00U) -typedef FINN_RM_API FINN_KEPLER_CHANNEL_GPFIFO_A_RESERVED; -#define FINN_KEPLER_CHANNEL_GPFIFO_A_EVENT_INTERFACE_ID (0xa06f02U) -typedef FINN_RM_API FINN_KEPLER_CHANNEL_GPFIFO_A_EVENT; -#define FINN_KEPLER_CHANNEL_GPFIFO_A_GPFIFO_INTERFACE_ID (0xa06f01U) -typedef FINN_RM_API FINN_KEPLER_CHANNEL_GPFIFO_A_GPFIFO; -#define FINN_KEPLER_CHANNEL_GPFIFO_A_INTERNAL_INTERFACE_ID (0xa06f03U) -typedef FINN_RM_API FINN_KEPLER_CHANNEL_GPFIFO_A_INTERNAL; - -#define FINN_KEPLER_DEVICE_VGPU_VGPU_DISPLAY_INTERFACE_ID (0xa08001U) -typedef FINN_RM_API FINN_KEPLER_DEVICE_VGPU_VGPU_DISPLAY; -#define FINN_KEPLER_DEVICE_VGPU_VGPU_MEMORY_INTERFACE_ID (0xa08002U) -typedef FINN_RM_API FINN_KEPLER_DEVICE_VGPU_VGPU_MEMORY; -#define FINN_KEPLER_DEVICE_VGPU_VGPU_OTHERS_INTERFACE_ID (0xa08003U) -typedef FINN_RM_API FINN_KEPLER_DEVICE_VGPU_VGPU_OTHERS; -#define FINN_NVA081_VGPU_CONFIG_VGPU_CONFIG_INTERFACE_ID (0xa08101U) -typedef FINN_RM_API FINN_NVA081_VGPU_CONFIG_VGPU_CONFIG; - -#define FINN_NVA083_GRID_DISPLAYLESS_RESERVED_INTERFACE_ID (0xa08300U) -typedef FINN_RM_API FINN_NVA083_GRID_DISPLAYLESS_RESERVED; -#define FINN_NVA083_GRID_DISPLAYLESS_VIRTUAL_DISPLAY_INTERFACE_ID (0xa08301U) -typedef FINN_RM_API FINN_NVA083_GRID_DISPLAYLESS_VIRTUAL_DISPLAY; -#define FINN_NVA084_KERNEL_HOST_VGPU_DEVICE_KERNEL_HOST_VGPU_DEVICE_INTERFACE_ID (0xa08401U) -typedef FINN_RM_API FINN_NVA084_KERNEL_HOST_VGPU_DEVICE_KERNEL_HOST_VGPU_DEVICE; -#define FINN_NVENC_SW_SESSION_NVENC_SW_SESSION_INTERFACE_ID (0xa0bc01U) -typedef FINN_RM_API FINN_NVENC_SW_SESSION_NVENC_SW_SESSION; -#define FINN_NVFBC_SW_SESSION_NVFBC_SW_SESSION_INTERFACE_ID (0xa0bd01U) -typedef FINN_RM_API FINN_NVFBC_SW_SESSION_NVFBC_SW_SESSION; -#define FINN_GK110_SUBDEVICE_GRAPHICS_RESERVED_INTERFACE_ID (0xa0e000U) -typedef FINN_RM_API FINN_GK110_SUBDEVICE_GRAPHICS_RESERVED; -#define FINN_GK110_SUBDEVICE_GRAPHICS_GRAPHICS_INTERFACE_ID (0xa0e001U) -typedef FINN_RM_API FINN_GK110_SUBDEVICE_GRAPHICS_GRAPHICS; -#define FINN_GK110_SUBDEVICE_FB_RESERVED_INTERFACE_ID (0xa0e100U) -typedef FINN_RM_API FINN_GK110_SUBDEVICE_FB_RESERVED; -#define FINN_GK110_SUBDEVICE_FB_FB_INTERFACE_ID (0xa0e101U) -typedef FINN_RM_API FINN_GK110_SUBDEVICE_FB_FB; -#define FINN_KEPLER_CHANNEL_GPFIFO_B_RESERVED_INTERFACE_ID (0xa16f00U) -typedef FINN_RM_API FINN_KEPLER_CHANNEL_GPFIFO_B_RESERVED; -#define FINN_KEPLER_CHANNEL_GPFIFO_B_GPFIFO_INTERFACE_ID (0xa16f01U) -typedef FINN_RM_API FINN_KEPLER_CHANNEL_GPFIFO_B_GPFIFO; -#define FINN_KEPLER_CHANNEL_GPFIFO_B_EVENT_INTERFACE_ID (0xa16f02U) -typedef FINN_RM_API FINN_KEPLER_CHANNEL_GPFIFO_B_EVENT; -#define FINN_KEPLER_CHANNEL_GPFIFO_C_RESERVED_INTERFACE_ID (0xa26f00U) -typedef FINN_RM_API FINN_KEPLER_CHANNEL_GPFIFO_C_RESERVED; -#define FINN_KEPLER_CHANNEL_GPFIFO_C_GPFIFO_INTERFACE_ID (0xa26f01U) -typedef FINN_RM_API FINN_KEPLER_CHANNEL_GPFIFO_C_GPFIFO; -#define FINN_KEPLER_CHANNEL_GPFIFO_C_EVENT_INTERFACE_ID (0xa26f02U) -typedef FINN_RM_API FINN_KEPLER_CHANNEL_GPFIFO_C_EVENT; -#define FINN_MAXWELL_FAULT_BUFFER_A_RESERVED_INTERFACE_ID (0xb06900U) -typedef FINN_RM_API FINN_MAXWELL_FAULT_BUFFER_A_RESERVED; -#define FINN_MAXWELL_FAULT_BUFFER_A_FAULTBUFFER_INTERFACE_ID (0xb06901U) -typedef FINN_RM_API FINN_MAXWELL_FAULT_BUFFER_A_FAULTBUFFER; -#define FINN_MAXWELL_CHANNEL_GPFIFO_A_RESERVED_INTERFACE_ID (0xb06f00U) -typedef FINN_RM_API FINN_MAXWELL_CHANNEL_GPFIFO_A_RESERVED; -#define FINN_MAXWELL_CHANNEL_GPFIFO_A_GPFIFO_INTERFACE_ID (0xb06f01U) -typedef FINN_RM_API FINN_MAXWELL_CHANNEL_GPFIFO_A_GPFIFO; -#define FINN_MAXWELL_CHANNEL_GPFIFO_A_EVENT_INTERFACE_ID (0xb06f02U) -typedef FINN_RM_API FINN_MAXWELL_CHANNEL_GPFIFO_A_EVENT; -#define FINN_MAXWELL_PROFILER_RESERVED_INTERFACE_ID (0xb0cc00U) -typedef FINN_RM_API FINN_MAXWELL_PROFILER_RESERVED; -#define FINN_MAXWELL_PROFILER_INTERNAL_INTERFACE_ID (0xb0cc02U) -typedef FINN_RM_API FINN_MAXWELL_PROFILER_INTERNAL; -#define FINN_MAXWELL_PROFILER_PROFILER_INTERFACE_ID (0xb0cc01U) -typedef FINN_RM_API FINN_MAXWELL_PROFILER_PROFILER; -#define FINN_MAXWELL_PROFILER_CONTEXT_RESERVED_INTERFACE_ID (0xb1cc00U) -typedef FINN_RM_API FINN_MAXWELL_PROFILER_CONTEXT_RESERVED; -#define FINN_MAXWELL_PROFILER_CONTEXT_PROFILER_INTERFACE_ID (0xb1cc01U) -typedef FINN_RM_API FINN_MAXWELL_PROFILER_CONTEXT_PROFILER; -#define FINN_MAXWELL_PROFILER_DEVICE_RESERVED_INTERFACE_ID (0xb2cc00U) -typedef FINN_RM_API FINN_MAXWELL_PROFILER_DEVICE_RESERVED; - -#define FINN_MAXWELL_SEC2_SEC2_INTERFACE_ID (0xb6b901U) -typedef FINN_RM_API FINN_MAXWELL_SEC2_SEC2; -#define FINN_PASCAL_CHANNEL_GPFIFO_A_RESERVED_INTERFACE_ID (0xc06f00U) -typedef FINN_RM_API FINN_PASCAL_CHANNEL_GPFIFO_A_RESERVED; -#define FINN_PASCAL_CHANNEL_GPFIFO_A_GPFIFO_INTERFACE_ID (0xc06f01U) -typedef FINN_RM_API FINN_PASCAL_CHANNEL_GPFIFO_A_GPFIFO; -#define FINN_PASCAL_CHANNEL_GPFIFO_A_EVENT_INTERFACE_ID (0xc06f02U) -typedef FINN_RM_API FINN_PASCAL_CHANNEL_GPFIFO_A_EVENT; -#define FINN_GP100_SUBDEVICE_GRAPHICS_RESERVED_INTERFACE_ID (0xc0e000U) -typedef FINN_RM_API FINN_GP100_SUBDEVICE_GRAPHICS_RESERVED; -#define FINN_GP100_SUBDEVICE_GRAPHICS_GRAPHICS_INTERFACE_ID (0xc0e001U) -typedef FINN_RM_API FINN_GP100_SUBDEVICE_GRAPHICS_GRAPHICS; -#define FINN_GP100_SUBDEVICE_FB_RESERVED_INTERFACE_ID (0xc0e100U) -typedef FINN_RM_API FINN_GP100_SUBDEVICE_FB_RESERVED; -#define FINN_GP100_SUBDEVICE_FB_FB_INTERFACE_ID (0xc0e101U) -typedef FINN_RM_API FINN_GP100_SUBDEVICE_FB_FB; -#define FINN_VOLTA_GSP_GSP_INTERFACE_ID (0xc31001U) -typedef FINN_RM_API FINN_VOLTA_GSP_GSP; -#define FINN_ACCESS_COUNTER_NOTIFY_BUFFER_RESERVED_INTERFACE_ID (0xc36500U) -typedef FINN_RM_API FINN_ACCESS_COUNTER_NOTIFY_BUFFER_RESERVED; -#define FINN_ACCESS_COUNTER_NOTIFY_BUFFER_ACCESS_CNTR_BUFFER_INTERFACE_ID (0xc36501U) -typedef FINN_RM_API FINN_ACCESS_COUNTER_NOTIFY_BUFFER_ACCESS_CNTR_BUFFER; -#define FINN_MMU_FAULT_BUFFER_RESERVED_INTERFACE_ID (0xc36900U) -typedef FINN_RM_API FINN_MMU_FAULT_BUFFER_RESERVED; -#define FINN_MMU_FAULT_BUFFER_MMU_FAULT_BUFFER_INTERFACE_ID (0xc36901U) -typedef FINN_RM_API FINN_MMU_FAULT_BUFFER_MMU_FAULT_BUFFER; -#define FINN_VOLTA_CHANNEL_GPFIFO_A_RESERVED_INTERFACE_ID (0xc36f00U) -typedef FINN_RM_API FINN_VOLTA_CHANNEL_GPFIFO_A_RESERVED; -#define FINN_VOLTA_CHANNEL_GPFIFO_A_GPFIFO_INTERFACE_ID (0xc36f01U) -typedef FINN_RM_API FINN_VOLTA_CHANNEL_GPFIFO_A_GPFIFO; -#define FINN_VOLTA_CHANNEL_GPFIFO_A_EVENT_INTERFACE_ID (0xc36f02U) -typedef FINN_RM_API FINN_VOLTA_CHANNEL_GPFIFO_A_EVENT; -#define FINN_NVC370_DISPLAY_RESERVED_INTERFACE_ID (0xc37000U) -typedef FINN_RM_API FINN_NVC370_DISPLAY_RESERVED; -#define FINN_NVC370_DISPLAY_CHNCTL_INTERFACE_ID (0xc37001U) -typedef FINN_RM_API FINN_NVC370_DISPLAY_CHNCTL; -#define FINN_NVC370_DISPLAY_EVENT_INTERFACE_ID (0xc37009U) -typedef FINN_RM_API FINN_NVC370_DISPLAY_EVENT; -#define FINN_NVC370_DISPLAY_RG_INTERFACE_ID (0xc37002U) -typedef FINN_RM_API FINN_NVC370_DISPLAY_RG; -#define FINN_NVC370_DISPLAY_VERIF_INTERFACE_ID (0xc37006U) -typedef FINN_RM_API FINN_NVC370_DISPLAY_VERIF; -#define FINN_NVC372_DISPLAY_SW_RESERVED_INTERFACE_ID (0xc37200U) -typedef FINN_RM_API FINN_NVC372_DISPLAY_SW_RESERVED; -#define FINN_NVC372_DISPLAY_SW_CHNCTL_INTERFACE_ID (0xc37201U) -typedef FINN_RM_API FINN_NVC372_DISPLAY_SW_CHNCTL; - -#define FINN_GV100_SUBDEVICE_GRAPHICS_RESERVED_INTERFACE_ID (0xc3e000U) -typedef FINN_RM_API FINN_GV100_SUBDEVICE_GRAPHICS_RESERVED; -#define FINN_GV100_SUBDEVICE_GRAPHICS_GRAPHICS_INTERFACE_ID (0xc3e001U) -typedef FINN_RM_API FINN_GV100_SUBDEVICE_GRAPHICS_GRAPHICS; -#define FINN_GV100_SUBDEVICE_FB_RESERVED_INTERFACE_ID (0xc3e100U) -typedef FINN_RM_API FINN_GV100_SUBDEVICE_FB_RESERVED; -#define FINN_GV100_SUBDEVICE_FB_FB_INTERFACE_ID (0xc3e101U) -typedef FINN_RM_API FINN_GV100_SUBDEVICE_FB_FB; -#define FINN_TURING_CHANNEL_GPFIFO_A_RESERVED_INTERFACE_ID (0xc46f00U) -typedef FINN_RM_API FINN_TURING_CHANNEL_GPFIFO_A_RESERVED; -#define FINN_TURING_CHANNEL_GPFIFO_A_GPFIFO_INTERFACE_ID (0xc46f01U) -typedef FINN_RM_API FINN_TURING_CHANNEL_GPFIFO_A_GPFIFO; -#define FINN_TURING_CHANNEL_GPFIFO_A_EVENT_INTERFACE_ID (0xc46f02U) -typedef FINN_RM_API FINN_TURING_CHANNEL_GPFIFO_A_EVENT; -#define FINN_AMPERE_CHANNEL_GPFIFO_A_RESERVED_INTERFACE_ID (0xc56f00U) -typedef FINN_RM_API FINN_AMPERE_CHANNEL_GPFIFO_A_RESERVED; -#define FINN_AMPERE_CHANNEL_GPFIFO_A_GPFIFO_INTERFACE_ID (0xc56f01U) -typedef FINN_RM_API FINN_AMPERE_CHANNEL_GPFIFO_A_GPFIFO; -#define FINN_AMPERE_CHANNEL_GPFIFO_A_EVENT_INTERFACE_ID (0xc56f02U) -typedef FINN_RM_API FINN_AMPERE_CHANNEL_GPFIFO_A_EVENT; -#define FINN_AMPERE_SMC_PARTITION_REF_RESERVED_INTERFACE_ID (0xc63700U) -typedef FINN_RM_API FINN_AMPERE_SMC_PARTITION_REF_RESERVED; -#define FINN_AMPERE_SMC_PARTITION_REF_EXEC_PARTITIONS_INTERFACE_ID (0xc63701U) -typedef FINN_RM_API FINN_AMPERE_SMC_PARTITION_REF_EXEC_PARTITIONS; -#define FINN_AMPERE_SMC_EXEC_PARTITION_REF_RESERVED_INTERFACE_ID (0xc63800U) -typedef FINN_RM_API FINN_AMPERE_SMC_EXEC_PARTITION_REF_RESERVED; -#define FINN_AMPERE_SMC_EXEC_PARTITION_REF_EXEC_PARTITION_INTERFACE_ID (0xc63801U) -typedef FINN_RM_API FINN_AMPERE_SMC_EXEC_PARTITION_REF_EXEC_PARTITION; -#define FINN_MMU_VIDMEM_ACCESS_BIT_BUFFER_RESERVED_INTERFACE_ID (0xc76300U) -typedef FINN_RM_API FINN_MMU_VIDMEM_ACCESS_BIT_BUFFER_RESERVED; -#define FINN_MMU_VIDMEM_ACCESS_BIT_BUFFER_VIDMEM_ACCESS_BIT_BUFFER_INTERFACE_ID (0xc76301U) -typedef FINN_RM_API FINN_MMU_VIDMEM_ACCESS_BIT_BUFFER_VIDMEM_ACCESS_BIT_BUFFER; -#define FINN_HOPPER_CHANNEL_GPFIFO_A_RESERVED_INTERFACE_ID (0xc86f00U) -typedef FINN_RM_API FINN_HOPPER_CHANNEL_GPFIFO_A_RESERVED; -#define FINN_HOPPER_CHANNEL_GPFIFO_A_GPFIFO_INTERFACE_ID (0xc86f01U) -typedef FINN_RM_API FINN_HOPPER_CHANNEL_GPFIFO_A_GPFIFO; -#define FINN_HOPPER_CHANNEL_GPFIFO_A_EVENT_INTERFACE_ID (0xc86f02U) -typedef FINN_RM_API FINN_HOPPER_CHANNEL_GPFIFO_A_EVENT; - -#define FINN_NV_COUNTER_COLLECTION_UNIT_RESERVED_INTERFACE_ID (0xcbca00U) -typedef FINN_RM_API FINN_NV_COUNTER_COLLECTION_UNIT_RESERVED; -#define FINN_NV_COUNTER_COLLECTION_UNIT_CCU_INTERFACE_ID (0xcbca01U) -typedef FINN_RM_API FINN_NV_COUNTER_COLLECTION_UNIT_CCU; -#define FINN_NVE2_SYNCPOINT_BASE_RESERVED_INTERFACE_ID (0xe2ad00U) -typedef FINN_RM_API FINN_NVE2_SYNCPOINT_BASE_RESERVED; -#define FINN_NVE2_SYNCPOINT_BASE_SYNCPOINT_BASE_INTERFACE_ID (0xe2ad01U) -typedef FINN_RM_API FINN_NVE2_SYNCPOINT_BASE_SYNCPOINT_BASE; diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/common/sdk/nvidia/inc/g_finn_rm_api.h nvidia-open-gpu-kernel-modules-535.161.08/src/common/sdk/nvidia/inc/g_finn_rm_api.h --- nvidia-open-gpu-kernel-modules-525.147.05/src/common/sdk/nvidia/inc/g_finn_rm_api.h 1970-01-01 00:00:00.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/common/sdk/nvidia/inc/g_finn_rm_api.h 2024-03-05 22:15:21.000000000 +0000 @@ -0,0 +1,747 @@ +#pragma once + +// +// This file was generated with FINN, an NVIDIA coding tool. +// + + +#include + + +#include +#include + +#define FINN_INTERFACE_ID(T) (T ## _INTERFACE_ID) +#define FINN_MESSAGE_ID(T) (T ## _MESSAGE_ID) + +#if (defined(__cplusplus) && __cplusplus >= 201103L) || (defined(_MSVC_LANG) && _MSVC_LANG >= 201103L) +#define FINN_OFFSETOF(T,f) (offsetof(T, f)) +#else +#define FINN_OFFSETOF(T,f) ((NvU64)&((T*)0)->f) +#endif + +#if !defined(_MSC_VER) && (defined(__STDC_VERSION__) && __STDC_VERSION__ >= 201112L) && !defined(__arm) +#define FINN_PACK_COMPOSITE(b) b __attribute__ ((packed)) +#else +#define FINN_PACK_COMPOSITE(b) b +#endif + +/* + * FINN serialization version. A version mismatch indicates incompatibility + * between the serializer and the deserializer. + * + * WARNING: Current serialization version is 0. This is a pre-release version of + * serialization and is only intended to be used in a driver and client compiled + * together. DO NOT use this in firmware or versioned clients. + */ +#define FINN_SERIALIZATION_VERSION 0 + +/* + * FINN compiler version + */ +#define FINN_VERSION_MAJOR 1 +#define FINN_VERSION_MINOR 21 +#define FINN_VERSION_PATCH 0 + +typedef struct FINN_RM_API +{ + NV_DECLARE_ALIGNED(NvU64 version, 8); + NV_DECLARE_ALIGNED(NvU64 payloadSize, 8); + NV_DECLARE_ALIGNED(NvU64 interface, 8); + NV_DECLARE_ALIGNED(NvU64 message, 8); +} FINN_RM_API; + + + + +/*! + * @brief Private functions not to be called directly + */ +/**@{*/ +NV_STATUS finnSerializeInternal_FINN_RM_API(NvU64 interface, NvU64 message, const char *api, char *dst, NvLength dst_size, NvBool seri_up); +NV_STATUS finnDeserializeInternal_FINN_RM_API(const char *src, NvLength src_size, char *api, NvLength api_size, NvBool deser_up); +/**@}*/ + + +/*! + * @brief Serializes an RM API control params struct and copies it into the + * serialization buffer as a FINN message. + * + * @note FinnRmApiSerializeDown is for serializing down the call stack. + * + * FinnRmApiSerializeUp is for serializing up the call stack. It + * frees memory allocated by FinnRmApiDeserializeDown. Use only + * when handling RM API control requests. + * + * @warning One of these may be unimplemented depending on platform. If both + * are implemented, misuse causes memory corruption and memory leaks. + * + * @param[in] interface FINN interface ID of the param struct. + * @param[in] message FINN message ID of the param struct. + * @param[in] api Source param struct from which to copy the data. + * @param[in] dst Destination buffer into which to copy the data. + * @param[in] dst_size Maximum size of the destination buffer measured in + * `NvU8` units. + * + * @retval NV_OK Serialization successful. + * @retval NV_ERR_INVALID_ARGUMENT Bad function arguments, invalid union + * selector, or invalid enum value. + * @retval NV_ERR_NOT_SUPPORTED Unserializable or nonexistent ID. + * @retval NV_ERR_NOT_COMPATIBLE Container count too large. + * @retval NV_ERR_OUT_OF_RANGE Ranged field exceeded bounds. + * @retval NV_ERR_BUFFER_TOO_SMALL Destination buffer size too small. + */ +/**@{*/ +static NV_INLINE NV_STATUS FinnRmApiSerializeUp(NvU64 interface, NvU64 message, const void *api, NvU8 *dst, NvLength dst_size) +{ + return finnSerializeInternal_FINN_RM_API(interface, message, (const char *) api, (char *) dst, dst_size, NV_TRUE); +} +static NV_INLINE NV_STATUS FinnRmApiSerializeDown(NvU64 interface, NvU64 message, const void *api, NvU8 *dst, NvLength dst_size) +{ + return finnSerializeInternal_FINN_RM_API(interface, message, (const char *) api, (char *) dst, dst_size, NV_FALSE); +} +/**@}*/ + + +/*! + * @brief The following APIs deserialize a FINN message from the serialization + * buffer and copy it into an RM API control params struct. + * + * @note FinnRmApiDeserializeDown is for deserializing down the call stack. It + * allocates deep buffers for primitive pointers in the serialization + * buffer, assuming that it remains in memory. Use only when handling + * RM API control requests. + * + * FinnRmApiDeserializeUp is for deserializing up the call stack. It + * copies deep buffers of primitive pointers into the params struct, + * assuming that memory is already allocated for them. Use only when + * receiving RM API control results. + * + * @warning One of these may be unimplemented depending on platform. If both + * are implemented, misuse causes memory corruption and memory leaks. + * + * @param[in] src Source buffer from which to copy the data. + * @param[in] src_size Maximum size of the source buffer measured in + * `NvU8` units. + * @param[in, out] api Destination param struct into which to copy the data. + * @param[in] api_size Size of the destination param struct measured in + * `char` units per `sizeof` operator. + * + * @retval NV_OK Deserialization successful. + * @retval NV_ERR_INVALID_ARGUMENT Bad function arguments, invalid union + * selector, invalid enum value, or + * mismatch between expected and actual + * serialized size. + * @retval NV_ERR_NOT_SUPPORTED Unserializable or nonexistent ID. + * @retval NV_ERR_OUT_OF_RANGE Ranged field exceeded bounds. + * @retval NV_ERR_BUFFER_TOO_SMALL Source/destination buffer too small. + * @retval NV_ERR_LIB_RM_VERSION_MISMATCH Version mismatch. + */ +/**@{*/ +static NV_INLINE NV_STATUS FinnRmApiDeserializeDown(NvU8 *src, NvLength src_size, void *api, NvLength api_size) +{ + return finnDeserializeInternal_FINN_RM_API((const char *) src, src_size / sizeof(NvU8), (char *) api, api_size, NV_FALSE); +} +static NV_INLINE NV_STATUS FinnRmApiDeserializeUp(NvU8 *src, NvLength src_size, void *api, NvLength api_size) +{ + return finnDeserializeInternal_FINN_RM_API((const char *) src, src_size / sizeof(NvU8), (char *) api, api_size, NV_TRUE); +} +/**@}*/ + + +/*! + * @brief Calculates the serialized size of an RM API param struct. + * + * @param[in] interface FINN interface ID of the param struct. + * @param[in] message FINN message ID of the param struct. + * @param[in] src Pointer to the param struct. + * + * @retval Non-zero serialized size of param struct on success. + * @retval 0 if the API is unsupported by serialization or src is NULL. + */ +NvU64 FinnRmApiGetSerializedSize(NvU64 interface, NvU64 message, const NvP64 src); + + +/*! + * @brief Fetches the unserialized size of an API param struct. + * + * @note The size is measured in `char` units like the `sizeof` operator. + * + * @param[in] interface FINN interface ID of the param struct. + * @param[in] message FINN message ID of the param struct. + * + * @retval Non-zero sizeof param struct on success. + * @retval 0 if the API is unsupported by serialization. + */ +NvU64 FinnRmApiGetUnserializedSize(NvU64 interface, NvU64 message); + + +#define NV_RM_ALLOC_INTERFACE_INTERFACE_ID (0xA000U) +typedef FINN_RM_API NV_RM_ALLOC_INTERFACE; +#define FINN_NV01_ROOT_RESERVED_INTERFACE_ID (0x0U) +typedef FINN_RM_API FINN_NV01_ROOT_RESERVED; +#define FINN_NV01_ROOT_CLIENT_INTERFACE_ID (0xdU) +typedef FINN_RM_API FINN_NV01_ROOT_CLIENT; +#define FINN_NV01_ROOT_DIAG_INTERFACE_ID (0x4U) +typedef FINN_RM_API FINN_NV01_ROOT_DIAG; +#define FINN_NV01_ROOT_EVENT_INTERFACE_ID (0x5U) +typedef FINN_RM_API FINN_NV01_ROOT_EVENT; +#define FINN_NV01_ROOT_GPU_INTERFACE_ID (0x2U) +typedef FINN_RM_API FINN_NV01_ROOT_GPU; +#define FINN_NV01_ROOT_GPUACCT_INTERFACE_ID (0xbU) +typedef FINN_RM_API FINN_NV01_ROOT_GPUACCT; +#define FINN_NV01_ROOT_GSYNC_INTERFACE_ID (0x3U) +typedef FINN_RM_API FINN_NV01_ROOT_GSYNC; +#define FINN_NV01_ROOT_NVD_INTERFACE_ID (0x6U) +typedef FINN_RM_API FINN_NV01_ROOT_NVD; +#define FINN_NV01_ROOT_PROC_INTERFACE_ID (0x9U) +typedef FINN_RM_API FINN_NV01_ROOT_PROC; + +#define FINN_NV01_ROOT_SYNC_GPU_BOOST_INTERFACE_ID (0xaU) +typedef FINN_RM_API FINN_NV01_ROOT_SYNC_GPU_BOOST; +#define FINN_NV01_ROOT_SYSTEM_INTERFACE_ID (0x1U) +typedef FINN_RM_API FINN_NV01_ROOT_SYSTEM; +#define FINN_NV01_ROOT_OS_UNIX_INTERFACE_ID (0x3dU) +typedef FINN_RM_API FINN_NV01_ROOT_OS_UNIX; +#define FINN_NV01_ROOT_VGPU_INTERFACE_ID (0xcU) +typedef FINN_RM_API FINN_NV01_ROOT_VGPU; +#define FINN_NV01_ROOT_OS_WINDOWS_INTERFACE_ID (0x3fU) +typedef FINN_RM_API FINN_NV01_ROOT_OS_WINDOWS; +#define FINN_NV01_CONTEXT_DMA_RESERVED_INTERFACE_ID (0x200U) +typedef FINN_RM_API FINN_NV01_CONTEXT_DMA_RESERVED; +#define FINN_NV01_CONTEXT_DMA_DMA_INTERFACE_ID (0x201U) +typedef FINN_RM_API FINN_NV01_CONTEXT_DMA_DMA; +#define FINN_NV01_TIMER_RESERVED_INTERFACE_ID (0x400U) +typedef FINN_RM_API FINN_NV01_TIMER_RESERVED; +#define FINN_NV01_TIMER_TMR_INTERFACE_ID (0x401U) +typedef FINN_RM_API FINN_NV01_TIMER_TMR; +#define FINN_FABRIC_MANAGER_SESSION_RESERVED_INTERFACE_ID (0xf00U) +typedef FINN_RM_API FINN_FABRIC_MANAGER_SESSION_RESERVED; +#define FINN_FABRIC_MANAGER_SESSION_FM_INTERFACE_ID (0xf01U) +typedef FINN_RM_API FINN_FABRIC_MANAGER_SESSION_FM; +#define FINN_FABRIC_MANAGER_SESSION_IMEX_INTERFACE_ID (0xf02U) +typedef FINN_RM_API FINN_FABRIC_MANAGER_SESSION_IMEX; +#define FINN_NV0020_GPU_MANAGEMENT_RESERVED_INTERFACE_ID (0x2000U) +typedef FINN_RM_API FINN_NV0020_GPU_MANAGEMENT_RESERVED; +#define FINN_NV0020_GPU_MANAGEMENT_GPU_MGMT_INTERFACE_ID (0x2001U) +typedef FINN_RM_API FINN_NV0020_GPU_MANAGEMENT_GPU_MGMT; +#define FINN_NV01_MEMORY_SYSTEM_RESERVED_INTERFACE_ID (0x3e00U) +typedef FINN_RM_API FINN_NV01_MEMORY_SYSTEM_RESERVED; +#define FINN_NV01_MEMORY_SYSTEM_MEMORY_INTERFACE_ID (0x3e01U) +typedef FINN_RM_API FINN_NV01_MEMORY_SYSTEM_MEMORY; +#define FINN_NV01_ROOT_USER_RESERVED_INTERFACE_ID (0x4100U) +typedef FINN_RM_API FINN_NV01_ROOT_USER_RESERVED; +#define FINN_NV01_ROOT_USER_MEMORY_INTERFACE_ID (0x4101U) +typedef FINN_RM_API FINN_NV01_ROOT_USER_MEMORY; +#define FINN_NV_CE_UTILS_RESERVED_INTERFACE_ID (0x0050U) +typedef FINN_RM_API FINN_NV_CE_UTILS_RESERVED; +#define FINN_NV_CE_UTILS_UTILS_INTERFACE_ID (0x5001U) +typedef FINN_RM_API FINN_NV_CE_UTILS_UTILS; +#define FINN_NV04_DISPLAY_COMMON_RESERVED_INTERFACE_ID (0x7300U) +typedef FINN_RM_API FINN_NV04_DISPLAY_COMMON_RESERVED; +#define FINN_NV04_DISPLAY_COMMON_COMMON_INTERFACE_ID (0x7305U) +typedef FINN_RM_API FINN_NV04_DISPLAY_COMMON_COMMON; +#define FINN_NV04_DISPLAY_COMMON_DFP_INTERFACE_ID (0x7311U) +typedef FINN_RM_API FINN_NV04_DISPLAY_COMMON_DFP; +#define FINN_NV04_DISPLAY_COMMON_DP_INTERFACE_ID (0x7313U) +typedef FINN_RM_API FINN_NV04_DISPLAY_COMMON_DP; + +#define FINN_NV04_DISPLAY_COMMON_EVENT_INTERFACE_ID (0x7303U) +typedef FINN_RM_API FINN_NV04_DISPLAY_COMMON_EVENT; +#define FINN_NV04_DISPLAY_COMMON_INTERNAL_INTERFACE_ID (0x7304U) +typedef FINN_RM_API FINN_NV04_DISPLAY_COMMON_INTERNAL; +#define FINN_NV04_DISPLAY_COMMON_PSR_INTERFACE_ID (0x7316U) +typedef FINN_RM_API FINN_NV04_DISPLAY_COMMON_PSR; +#define FINN_NV04_DISPLAY_COMMON_SPECIFIC_INTERFACE_ID (0x7302U) +typedef FINN_RM_API FINN_NV04_DISPLAY_COMMON_SPECIFIC; +#define FINN_NV04_DISPLAY_COMMON_STEREO_INTERFACE_ID (0x7317U) +typedef FINN_RM_API FINN_NV04_DISPLAY_COMMON_STEREO; + +#define FINN_NV04_DISPLAY_COMMON_SYSTEM_INTERFACE_ID (0x7301U) +typedef FINN_RM_API FINN_NV04_DISPLAY_COMMON_SYSTEM; +#define FINN_NV01_DEVICE_0_RESERVED_INTERFACE_ID (0x8000U) +typedef FINN_RM_API FINN_NV01_DEVICE_0_RESERVED; +#define FINN_NV01_DEVICE_0_BIF_INTERFACE_ID (0x8001U) +typedef FINN_RM_API FINN_NV01_DEVICE_0_BIF; +#define FINN_NV01_DEVICE_0_BSP_INTERFACE_ID (0x801cU) +typedef FINN_RM_API FINN_NV01_DEVICE_0_BSP; + +#define FINN_NV01_DEVICE_0_DMA_INTERFACE_ID (0x8018U) +typedef FINN_RM_API FINN_NV01_DEVICE_0_DMA; +#define FINN_NV01_DEVICE_0_FB_INTERFACE_ID (0x8013U) +typedef FINN_RM_API FINN_NV01_DEVICE_0_FB; +#define FINN_NV01_DEVICE_0_FIFO_INTERFACE_ID (0x8017U) +typedef FINN_RM_API FINN_NV01_DEVICE_0_FIFO; +#define FINN_NV01_DEVICE_0_GPU_INTERFACE_ID (0x8002U) +typedef FINN_RM_API FINN_NV01_DEVICE_0_GPU; +#define FINN_NV01_DEVICE_0_GR_INTERFACE_ID (0x8011U) +typedef FINN_RM_API FINN_NV01_DEVICE_0_GR; +#define FINN_NV01_DEVICE_0_HOST_INTERFACE_ID (0x8014U) +typedef FINN_RM_API FINN_NV01_DEVICE_0_HOST; +#define FINN_NV01_DEVICE_0_INTERNAL_INTERFACE_ID (0x8020U) +typedef FINN_RM_API FINN_NV01_DEVICE_0_INTERNAL; +#define FINN_NV01_DEVICE_0_MSENC_INTERFACE_ID (0x801bU) +typedef FINN_RM_API FINN_NV01_DEVICE_0_MSENC; +#define FINN_NV01_DEVICE_0_NVJPG_INTERFACE_ID (0x801fU) +typedef FINN_RM_API FINN_NV01_DEVICE_0_NVJPG; +#define FINN_NV01_DEVICE_0_PERF_INTERFACE_ID (0x8019U) +typedef FINN_RM_API FINN_NV01_DEVICE_0_PERF; + +#define FINN_NV01_DEVICE_0_OS_UNIX_INTERFACE_ID (0x801eU) +typedef FINN_RM_API FINN_NV01_DEVICE_0_OS_UNIX; + +#define FINN_NV0090_KERNEL_GRAPHICS_CONTEXT_INTERFACE_ID (0x9001U) +typedef FINN_RM_API FINN_NV0090_KERNEL_GRAPHICS_CONTEXT; +#define FINN_NV_SEMAPHORE_SURFACE_INTERFACE_ID (0x00da00U) +typedef FINN_RM_API FINN_NV_SEMAPHORE_SURFACE; +#define FINN_IMEX_SESSION_INTERFACE_ID (0xf100U) +typedef FINN_RM_API FINN_IMEX_SESSION; +#define FINN_NV01_MEMORY_FABRIC_EXPORT_RESERVED_INTERFACE_ID (0xf400U) +typedef FINN_RM_API FINN_NV01_MEMORY_FABRIC_EXPORT_RESERVED; +#define FINN_NV01_MEMORY_FABRIC_EXPORT_EXPORT_INTERFACE_ID (0xf401U) +typedef FINN_RM_API FINN_NV01_MEMORY_FABRIC_EXPORT_EXPORT; +#define FINN_NV01_MEMORY_FABRIC_IMPORT_RESERVED_INTERFACE_ID (0xf500U) +typedef FINN_RM_API FINN_NV01_MEMORY_FABRIC_IMPORT_RESERVED; +#define FINN_NV01_MEMORY_FABRIC_IMPORT_IMPORT_INTERFACE_ID (0xf501U) +typedef FINN_RM_API FINN_NV01_MEMORY_FABRIC_IMPORT_IMPORT; +#define FINN_NV_MEMORY_FABRIC_EXPORT_RESERVED_INTERFACE_ID (0xf700U) +typedef FINN_RM_API FINN_NV_MEMORY_FABRIC_EXPORT_RESERVED; +#define FINN_NV_MEMORY_FABRIC_EXPORT_INTERFACE_ID (0xf701U) +typedef FINN_RM_API FINN_NV_MEMORY_FABRIC_EXPORT; +#define FINN_NV_MEMORY_FABRIC_RESERVED_INTERFACE_ID (0xf800U) +typedef FINN_RM_API FINN_NV_MEMORY_FABRIC_RESERVED; +#define FINN_NV_MEMORY_FABRIC_FABRIC_INTERFACE_ID (0xf801U) +typedef FINN_RM_API FINN_NV_MEMORY_FABRIC_FABRIC; +#define FINN_NV_MEMORY_FABRIC_IMPORT_V2_RESERVED_INTERFACE_ID (0xf900U) +typedef FINN_RM_API FINN_NV_MEMORY_FABRIC_IMPORT_V2_RESERVED; +#define FINN_NV_MEMORY_FABRIC_IMPORT_V2_IMPORT_INTERFACE_ID (0xf901U) +typedef FINN_RM_API FINN_NV_MEMORY_FABRIC_IMPORT_V2_IMPORT; +#define FINN_NV_MEMORY_FABRIC_EXPORTED_REF_RESERVED_INTERFACE_ID (0xfa00U) +typedef FINN_RM_API FINN_NV_MEMORY_FABRIC_EXPORTED_REF_RESERVED; +#define FINN_NV_MEMORY_FABRIC_EXPORTED_REF_EXPORT_REF_INTERFACE_ID (0xfa01U) +typedef FINN_RM_API FINN_NV_MEMORY_FABRIC_EXPORTED_REF_EXPORT_REF; +#define FINN_NV_MEMORY_FABRIC_IMPORTED_REF_RESERVED_INTERFACE_ID (0xfb00U) +typedef FINN_RM_API FINN_NV_MEMORY_FABRIC_IMPORTED_REF_RESERVED; +#define FINN_NV_MEMORY_FABRIC_IMPORTED_REF_IMPORT_REF_INTERFACE_ID (0xfb01U) +typedef FINN_RM_API FINN_NV_MEMORY_FABRIC_IMPORTED_REF_IMPORT_REF; +#define FINN_NV_MEMORY_MULTICAST_FABRIC_RESERVED_INTERFACE_ID (0xfd00U) +typedef FINN_RM_API FINN_NV_MEMORY_MULTICAST_FABRIC_RESERVED; +#define FINN_NV_MEMORY_MULTICAST_FABRIC_FABRIC_INTERFACE_ID (0xfd01U) +typedef FINN_RM_API FINN_NV_MEMORY_MULTICAST_FABRIC_FABRIC; +#define FINN_NV_MEMORY_MAPPER_INTERFACE_ID (0x00FE00U) +typedef FINN_RM_API FINN_NV_MEMORY_MAPPER; + +#define FINN_NV20_SUBDEVICE_0_RESERVED_INTERFACE_ID (0x208000U) +typedef FINN_RM_API FINN_NV20_SUBDEVICE_0_RESERVED; + +#define FINN_NV20_SUBDEVICE_0_BIOS_INTERFACE_ID (0x208008U) +typedef FINN_RM_API FINN_NV20_SUBDEVICE_0_BIOS; +#define FINN_NV20_SUBDEVICE_0_BUS_INTERFACE_ID (0x208018U) +typedef FINN_RM_API FINN_NV20_SUBDEVICE_0_BUS; +#define FINN_NV20_SUBDEVICE_0_CE_INTERFACE_ID (0x20802aU) +typedef FINN_RM_API FINN_NV20_SUBDEVICE_0_CE; + +#define FINN_NV20_SUBDEVICE_0_CLK_INTERFACE_ID (0x208010U) +typedef FINN_RM_API FINN_NV20_SUBDEVICE_0_CLK; + +#define FINN_NV20_SUBDEVICE_0_DMA_INTERFACE_ID (0x208025U) +typedef FINN_RM_API FINN_NV20_SUBDEVICE_0_DMA; +#define FINN_NV20_SUBDEVICE_0_DMABUF_INTERFACE_ID (0x20803AU) +typedef FINN_RM_API FINN_NV20_SUBDEVICE_0_DMABUF; +#define FINN_NV20_SUBDEVICE_0_ECC_INTERFACE_ID (0x208034U) +typedef FINN_RM_API FINN_NV20_SUBDEVICE_0_ECC; + +#define FINN_NV20_SUBDEVICE_0_EVENT_INTERFACE_ID (0x208003U) +typedef FINN_RM_API FINN_NV20_SUBDEVICE_0_EVENT; + +#define FINN_NV20_SUBDEVICE_0_FB_INTERFACE_ID (0x208013U) +typedef FINN_RM_API FINN_NV20_SUBDEVICE_0_FB; +#define FINN_NV20_SUBDEVICE_0_FIFO_INTERFACE_ID (0x208011U) +typedef FINN_RM_API FINN_NV20_SUBDEVICE_0_FIFO; +#define FINN_NV20_SUBDEVICE_0_FLA_INTERFACE_ID (0x208035U) +typedef FINN_RM_API FINN_NV20_SUBDEVICE_0_FLA; +#define FINN_NV20_SUBDEVICE_0_FLCN_INTERFACE_ID (0x208031U) +typedef FINN_RM_API FINN_NV20_SUBDEVICE_0_FLCN; +#define FINN_NV20_SUBDEVICE_0_FUSE_INTERFACE_ID (0x208002U) +typedef FINN_RM_API FINN_NV20_SUBDEVICE_0_FUSE; + +#define FINN_NV20_SUBDEVICE_0_GPIO_INTERFACE_ID (0x208023U) +typedef FINN_RM_API FINN_NV20_SUBDEVICE_0_GPIO; + +#define FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID (0x208001U) +typedef FINN_RM_API FINN_NV20_SUBDEVICE_0_GPU; + +#define FINN_NV20_SUBDEVICE_0_GR_INTERFACE_ID (0x208012U) +typedef FINN_RM_API FINN_NV20_SUBDEVICE_0_GR; +#define FINN_NV20_SUBDEVICE_0_GRMGR_INTERFACE_ID (0x208038U) +typedef FINN_RM_API FINN_NV20_SUBDEVICE_0_GRMGR; +#define FINN_NV20_SUBDEVICE_0_GSP_INTERFACE_ID (0x208036U) +typedef FINN_RM_API FINN_NV20_SUBDEVICE_0_GSP; +#define FINN_NV20_SUBDEVICE_0_HSHUB_INTERFACE_ID (0x208041U) +typedef FINN_RM_API FINN_NV20_SUBDEVICE_0_HSHUB; +#define FINN_NV20_SUBDEVICE_0_I2C_INTERFACE_ID (0x208006U) +typedef FINN_RM_API FINN_NV20_SUBDEVICE_0_I2C; +#define FINN_NV20_SUBDEVICE_0_PMGR_INTERFACE_ID (0x208026U) +typedef FINN_RM_API FINN_NV20_SUBDEVICE_0_PMGR; + +#define FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID (0x20800aU) +typedef FINN_RM_API FINN_NV20_SUBDEVICE_0_INTERNAL; +#define FINN_NV20_SUBDEVICE_0_LPWR_INTERFACE_ID (0x208028U) +typedef FINN_RM_API FINN_NV20_SUBDEVICE_0_LPWR; + +#define FINN_NV20_SUBDEVICE_0_MC_INTERFACE_ID (0x208017U) +typedef FINN_RM_API FINN_NV20_SUBDEVICE_0_MC; +#define FINN_NV20_SUBDEVICE_0_NNE_INTERFACE_ID (0x208037U) +typedef FINN_RM_API FINN_NV20_SUBDEVICE_0_NNE; + +#define FINN_NV20_SUBDEVICE_0_NVD_INTERFACE_ID (0x208024U) +typedef FINN_RM_API FINN_NV20_SUBDEVICE_0_NVD; + +#define FINN_NV20_SUBDEVICE_0_NVLINK_INTERFACE_ID (0x208030U) +typedef FINN_RM_API FINN_NV20_SUBDEVICE_0_NVLINK; + +#define FINN_NV20_SUBDEVICE_0_PERF_INTERFACE_ID (0x208020U) +typedef FINN_RM_API FINN_NV20_SUBDEVICE_0_PERF; + +#define FINN_NV20_SUBDEVICE_0_POWER_INTERFACE_ID (0x208027U) +typedef FINN_RM_API FINN_NV20_SUBDEVICE_0_POWER; + +#define FINN_NV20_SUBDEVICE_0_RC_INTERFACE_ID (0x208022U) +typedef FINN_RM_API FINN_NV20_SUBDEVICE_0_RC; +#define FINN_NV20_SUBDEVICE_0_SEC2_INTERFACE_ID (0x208042U) +typedef FINN_RM_API FINN_NV20_SUBDEVICE_0_SEC2; + +#define FINN_NV20_SUBDEVICE_0_TIMER_INTERFACE_ID (0x208004U) +typedef FINN_RM_API FINN_NV20_SUBDEVICE_0_TIMER; + +#define FINN_NV20_SUBDEVICE_0_OS_UNIX_INTERFACE_ID (0x20803dU) +typedef FINN_RM_API FINN_NV20_SUBDEVICE_0_OS_UNIX; +#define FINN_NV20_SUBDEVICE_0_VGPU_MGR_INTERNAL_INTERFACE_ID (0x208040U) +typedef FINN_RM_API FINN_NV20_SUBDEVICE_0_VGPU_MGR_INTERNAL; +#define FINN_NV20_SUBDEVICE_0_VOLT_INTERFACE_ID (0x208032U) +typedef FINN_RM_API FINN_NV20_SUBDEVICE_0_VOLT; + +#define FINN_NV2081_BINAPI_RESERVED_INTERFACE_ID (0x208100U) +typedef FINN_RM_API FINN_NV2081_BINAPI_RESERVED; +#define FINN_NV2081_BINAPI_INTERFACE_ID (0x208101U) +typedef FINN_RM_API FINN_NV2081_BINAPI; +#define FINN_NV2082_BINAPI_RESERVED_INTERFACE_ID (0x208200U) +typedef FINN_RM_API FINN_NV2082_BINAPI_RESERVED; +#define FINN_NV2082_BINAPI_INTERFACE_ID (0x208201U) +typedef FINN_RM_API FINN_NV2082_BINAPI; +#define FINN_NV20_SUBDEVICE_DIAG_RESERVED_INTERFACE_ID (0x208f00U) +typedef FINN_RM_API FINN_NV20_SUBDEVICE_DIAG_RESERVED; +#define FINN_NV20_SUBDEVICE_DIAG_BIF_INTERFACE_ID (0x208f07U) +typedef FINN_RM_API FINN_NV20_SUBDEVICE_DIAG_BIF; +#define FINN_NV20_SUBDEVICE_DIAG_BUS_INTERFACE_ID (0x208f18U) +typedef FINN_RM_API FINN_NV20_SUBDEVICE_DIAG_BUS; + +#define FINN_NV20_SUBDEVICE_DIAG_DMA_INTERFACE_ID (0x208f14U) +typedef FINN_RM_API FINN_NV20_SUBDEVICE_DIAG_DMA; +#define FINN_NV20_SUBDEVICE_DIAG_EVENT_INTERFACE_ID (0x208f10U) +typedef FINN_RM_API FINN_NV20_SUBDEVICE_DIAG_EVENT; +#define FINN_NV20_SUBDEVICE_DIAG_FB_INTERFACE_ID (0x208f05U) +typedef FINN_RM_API FINN_NV20_SUBDEVICE_DIAG_FB; +#define FINN_NV20_SUBDEVICE_DIAG_FBIO_INTERFACE_ID (0x208f0aU) +typedef FINN_RM_API FINN_NV20_SUBDEVICE_DIAG_FBIO; +#define FINN_NV20_SUBDEVICE_DIAG_FIFO_INTERFACE_ID (0x208f04U) +typedef FINN_RM_API FINN_NV20_SUBDEVICE_DIAG_FIFO; +#define FINN_NV20_SUBDEVICE_DIAG_GPU_INTERFACE_ID (0x208f11U) +typedef FINN_RM_API FINN_NV20_SUBDEVICE_DIAG_GPU; +#define FINN_NV20_SUBDEVICE_DIAG_GR_INTERFACE_ID (0x208f12U) +typedef FINN_RM_API FINN_NV20_SUBDEVICE_DIAG_GR; + +#define FINN_NV20_SUBDEVICE_DIAG_MMU_INTERFACE_ID (0x208f0bU) +typedef FINN_RM_API FINN_NV20_SUBDEVICE_DIAG_MMU; + +#define FINN_NV30_GSYNC_RESERVED_INTERFACE_ID (0x30f100U) +typedef FINN_RM_API FINN_NV30_GSYNC_RESERVED; +#define FINN_NV30_GSYNC_GSYNC_INTERFACE_ID (0x30f101U) +typedef FINN_RM_API FINN_NV30_GSYNC_GSYNC; +#define FINN_NV40_I2C_RESERVED_INTERFACE_ID (0x402c00U) +typedef FINN_RM_API FINN_NV40_I2C_RESERVED; +#define FINN_NV40_I2C_I2C_INTERFACE_ID (0x402c01U) +typedef FINN_RM_API FINN_NV40_I2C_I2C; +#define FINN_NV50_THIRD_PARTY_P2P_P2P_INTERFACE_ID (0x503c01U) +typedef FINN_RM_API FINN_NV50_THIRD_PARTY_P2P_P2P; +#define FINN_NV50_THIRD_PARTY_P2P_RESERVED_INTERFACE_ID (0x503c00U) +typedef FINN_RM_API FINN_NV50_THIRD_PARTY_P2P_RESERVED; +#define FINN_NV50_CHANNEL_GPFIFO_RESERVED_INTERFACE_ID (0x506f00U) +typedef FINN_RM_API FINN_NV50_CHANNEL_GPFIFO_RESERVED; +#define FINN_NV50_CHANNEL_GPFIFO_GPFIFO_INTERFACE_ID (0x506f01U) +typedef FINN_RM_API FINN_NV50_CHANNEL_GPFIFO_GPFIFO; +#define FINN_NV50_DISPLAY_RESERVED_INTERFACE_ID (0x507000U) +typedef FINN_RM_API FINN_NV50_DISPLAY_RESERVED; +#define FINN_NV50_DISPLAY_CHNCTL_INTERFACE_ID (0x507001U) +typedef FINN_RM_API FINN_NV50_DISPLAY_CHNCTL; +#define FINN_NV50_DISPLAY_EVENT_INTERFACE_ID (0x507009U) +typedef FINN_RM_API FINN_NV50_DISPLAY_EVENT; +#define FINN_NV50_DISPLAY_OR_INTERFACE_ID (0x507004U) +typedef FINN_RM_API FINN_NV50_DISPLAY_OR; +#define FINN_NV50_DISPLAY_RG_INTERFACE_ID (0x507002U) +typedef FINN_RM_API FINN_NV50_DISPLAY_RG; +#define FINN_NV50_DISPLAY_SEQ_INTERFACE_ID (0x507003U) +typedef FINN_RM_API FINN_NV50_DISPLAY_SEQ; +#define FINN_NV50_DISPLAY_SYSTEM_INTERFACE_ID (0x507007U) +typedef FINN_RM_API FINN_NV50_DISPLAY_SYSTEM; + +#define FINN_NV50_DEFERRED_API_CLASS_RESERVED_INTERFACE_ID (0x508000U) +typedef FINN_RM_API FINN_NV50_DEFERRED_API_CLASS_RESERVED; +#define FINN_NV50_DEFERRED_API_CLASS_DEFERRED_INTERFACE_ID (0x508001U) +typedef FINN_RM_API FINN_NV50_DEFERRED_API_CLASS_DEFERRED; +#define FINN_GT200_DEBUGGER_RESERVED_INTERFACE_ID (0x83de00U) +typedef FINN_RM_API FINN_GT200_DEBUGGER_RESERVED; +#define FINN_GT200_DEBUGGER_DEBUG_INTERFACE_ID (0x83de03U) +typedef FINN_RM_API FINN_GT200_DEBUGGER_DEBUG; +#define FINN_GT200_DEBUGGER_FIFO_INTERFACE_ID (0x83de02U) +typedef FINN_RM_API FINN_GT200_DEBUGGER_FIFO; +#define FINN_GT200_DEBUGGER_INTERNAL_INTERFACE_ID (0x83de04U) +typedef FINN_RM_API FINN_GT200_DEBUGGER_INTERNAL; + +#define FINN_NV9010_VBLANK_CALLBACK_RESERVED_INTERFACE_ID (0x901000U) +typedef FINN_RM_API FINN_NV9010_VBLANK_CALLBACK_RESERVED; +#define FINN_NV9010_VBLANK_CALLBACK_INTERFACE_ID (0x901001U) +typedef FINN_RM_API FINN_NV9010_VBLANK_CALLBACK; +#define FINN_FERMI_CONTEXT_SHARE_A_RESERVED_INTERFACE_ID (0x906700U) +typedef FINN_RM_API FINN_FERMI_CONTEXT_SHARE_A_RESERVED; +#define FINN_FERMI_CONTEXT_SHARE_A_TPC_PARTITION_INTERFACE_ID (0x906701U) +typedef FINN_RM_API FINN_FERMI_CONTEXT_SHARE_A_TPC_PARTITION; +#define FINN_FERMI_CONTEXT_SHARE_A_CWD_WATERMARK_INTERFACE_ID (0x906702U) +typedef FINN_RM_API FINN_FERMI_CONTEXT_SHARE_A_CWD_WATERMARK; +#define FINN_GF100_CHANNEL_GPFIFO_RESERVED_INTERFACE_ID (0x906f00U) +typedef FINN_RM_API FINN_GF100_CHANNEL_GPFIFO_RESERVED; +#define FINN_GF100_CHANNEL_GPFIFO_GPFIFO_INTERFACE_ID (0x906f01U) +typedef FINN_RM_API FINN_GF100_CHANNEL_GPFIFO_GPFIFO; +#define FINN_GF100_CHANNEL_GPFIFO_EVENT_INTERFACE_ID (0x906f02U) +typedef FINN_RM_API FINN_GF100_CHANNEL_GPFIFO_EVENT; +#define FINN_GF100_DISP_SW_RESERVED_INTERFACE_ID (0x907200U) +typedef FINN_RM_API FINN_GF100_DISP_SW_RESERVED; +#define FINN_GF100_DISP_SW_DISP_SW_INTERFACE_ID (0x907201U) +typedef FINN_RM_API FINN_GF100_DISP_SW_DISP_SW; +#define FINN_GF100_TIMED_SEMAPHORE_SW_RESERVED_INTERFACE_ID (0x907400U) +typedef FINN_RM_API FINN_GF100_TIMED_SEMAPHORE_SW_RESERVED; +#define FINN_GF100_TIMED_SEMAPHORE_SW_SEM_INTERFACE_ID (0x907401U) +typedef FINN_RM_API FINN_GF100_TIMED_SEMAPHORE_SW_SEM; +#define FINN_GF100_REMAPPER_RESERVED_INTERFACE_ID (0x907f00U) +typedef FINN_RM_API FINN_GF100_REMAPPER_RESERVED; +#define FINN_GF100_REMAPPER_REMAPPER_INTERFACE_ID (0x907f01U) +typedef FINN_RM_API FINN_GF100_REMAPPER_REMAPPER; +#define FINN_GF100_ZBC_CLEAR_RESERVED_INTERFACE_ID (0x909600U) +typedef FINN_RM_API FINN_GF100_ZBC_CLEAR_RESERVED; +#define FINN_GF100_ZBC_CLEAR_ZBC_INTERFACE_ID (0x909601U) +typedef FINN_RM_API FINN_GF100_ZBC_CLEAR_ZBC; +#define FINN_GF100_PROFILER_RESERVED_INTERFACE_ID (0x90cc00U) +typedef FINN_RM_API FINN_GF100_PROFILER_RESERVED; +#define FINN_GF100_PROFILER_HWPM_INTERFACE_ID (0x90cc01U) +typedef FINN_RM_API FINN_GF100_PROFILER_HWPM; +#define FINN_GF100_PROFILER_NVLINK_INTERFACE_ID (0x90cc02U) +typedef FINN_RM_API FINN_GF100_PROFILER_NVLINK; +#define FINN_GF100_PROFILER_POWER_INTERFACE_ID (0x90cc03U) +typedef FINN_RM_API FINN_GF100_PROFILER_POWER; +#define FINN_NV_EVENT_BUFFER_RESERVED_INTERFACE_ID (0x90cd00U) +typedef FINN_RM_API FINN_NV_EVENT_BUFFER_RESERVED; +#define FINN_NV_EVENT_BUFFER_EVENT_INTERFACE_ID (0x90cd01U) +typedef FINN_RM_API FINN_NV_EVENT_BUFFER_EVENT; +#define FINN_GF100_SUBDEVICE_GRAPHICS_RESERVED_INTERFACE_ID (0x90e000U) +typedef FINN_RM_API FINN_GF100_SUBDEVICE_GRAPHICS_RESERVED; +#define FINN_GF100_SUBDEVICE_GRAPHICS_GRAPHICS_INTERFACE_ID (0x90e001U) +typedef FINN_RM_API FINN_GF100_SUBDEVICE_GRAPHICS_GRAPHICS; +#define FINN_GF100_SUBDEVICE_FB_RESERVED_INTERFACE_ID (0x90e100U) +typedef FINN_RM_API FINN_GF100_SUBDEVICE_FB_RESERVED; +#define FINN_GF100_SUBDEVICE_FB_FB_INTERFACE_ID (0x90e101U) +typedef FINN_RM_API FINN_GF100_SUBDEVICE_FB_FB; +#define FINN_GF100_SUBDEVICE_MASTER_RESERVED_INTERFACE_ID (0x90e600U) +typedef FINN_RM_API FINN_GF100_SUBDEVICE_MASTER_RESERVED; +#define FINN_GF100_SUBDEVICE_MASTER_MASTER_INTERFACE_ID (0x90e601U) +typedef FINN_RM_API FINN_GF100_SUBDEVICE_MASTER_MASTER; +#define FINN_GF100_SUBDEVICE_INFOROM_RESERVED_INTERFACE_ID (0x90e700U) +typedef FINN_RM_API FINN_GF100_SUBDEVICE_INFOROM_RESERVED; +#define FINN_GF100_SUBDEVICE_INFOROM_BBX_INTERFACE_ID (0x90e701U) +typedef FINN_RM_API FINN_GF100_SUBDEVICE_INFOROM_BBX; + +#define FINN_GF100_HDACODEC_RESERVED_INTERFACE_ID (0x90ec00U) +typedef FINN_RM_API FINN_GF100_HDACODEC_RESERVED; +#define FINN_GF100_HDACODEC_HDACODEC_INTERFACE_ID (0x90ec01U) +typedef FINN_RM_API FINN_GF100_HDACODEC_HDACODEC; +#define FINN_FERMI_VASPACE_A_RESERVED_INTERFACE_ID (0x90f100U) +typedef FINN_RM_API FINN_FERMI_VASPACE_A_RESERVED; +#define FINN_FERMI_VASPACE_A_VASPACE_INTERFACE_ID (0x90f101U) +typedef FINN_RM_API FINN_FERMI_VASPACE_A_VASPACE; +#define FINN_KEPLER_CHANNEL_GROUP_A_RESERVED_INTERFACE_ID (0xa06c00U) +typedef FINN_RM_API FINN_KEPLER_CHANNEL_GROUP_A_RESERVED; +#define FINN_KEPLER_CHANNEL_GROUP_A_GPFIFO_INTERFACE_ID (0xa06c01U) +typedef FINN_RM_API FINN_KEPLER_CHANNEL_GROUP_A_GPFIFO; +#define FINN_KEPLER_CHANNEL_GROUP_A_INTERNAL_INTERFACE_ID (0xa06c02U) +typedef FINN_RM_API FINN_KEPLER_CHANNEL_GROUP_A_INTERNAL; +#define FINN_KEPLER_CHANNEL_GPFIFO_A_RESERVED_INTERFACE_ID (0xa06f00U) +typedef FINN_RM_API FINN_KEPLER_CHANNEL_GPFIFO_A_RESERVED; +#define FINN_KEPLER_CHANNEL_GPFIFO_A_EVENT_INTERFACE_ID (0xa06f02U) +typedef FINN_RM_API FINN_KEPLER_CHANNEL_GPFIFO_A_EVENT; +#define FINN_KEPLER_CHANNEL_GPFIFO_A_GPFIFO_INTERFACE_ID (0xa06f01U) +typedef FINN_RM_API FINN_KEPLER_CHANNEL_GPFIFO_A_GPFIFO; +#define FINN_KEPLER_CHANNEL_GPFIFO_A_INTERNAL_INTERFACE_ID (0xa06f03U) +typedef FINN_RM_API FINN_KEPLER_CHANNEL_GPFIFO_A_INTERNAL; + +#define FINN_KEPLER_DEVICE_VGPU_VGPU_DISPLAY_INTERFACE_ID (0xa08001U) +typedef FINN_RM_API FINN_KEPLER_DEVICE_VGPU_VGPU_DISPLAY; +#define FINN_KEPLER_DEVICE_VGPU_VGPU_MEMORY_INTERFACE_ID (0xa08002U) +typedef FINN_RM_API FINN_KEPLER_DEVICE_VGPU_VGPU_MEMORY; +#define FINN_KEPLER_DEVICE_VGPU_VGPU_OTHERS_INTERFACE_ID (0xa08003U) +typedef FINN_RM_API FINN_KEPLER_DEVICE_VGPU_VGPU_OTHERS; +#define FINN_NVA081_VGPU_CONFIG_VGPU_CONFIG_INTERFACE_ID (0xa08101U) +typedef FINN_RM_API FINN_NVA081_VGPU_CONFIG_VGPU_CONFIG; + +#define FINN_NVA083_GRID_DISPLAYLESS_RESERVED_INTERFACE_ID (0xa08300U) +typedef FINN_RM_API FINN_NVA083_GRID_DISPLAYLESS_RESERVED; +#define FINN_NVA083_GRID_DISPLAYLESS_VIRTUAL_DISPLAY_INTERFACE_ID (0xa08301U) +typedef FINN_RM_API FINN_NVA083_GRID_DISPLAYLESS_VIRTUAL_DISPLAY; +#define FINN_NVA084_KERNEL_HOST_VGPU_DEVICE_KERNEL_HOST_VGPU_DEVICE_INTERFACE_ID (0xa08401U) +typedef FINN_RM_API FINN_NVA084_KERNEL_HOST_VGPU_DEVICE_KERNEL_HOST_VGPU_DEVICE; +#define FINN_NVENC_SW_SESSION_NVENC_SW_SESSION_INTERFACE_ID (0xa0bc01U) +typedef FINN_RM_API FINN_NVENC_SW_SESSION_NVENC_SW_SESSION; +#define FINN_NVFBC_SW_SESSION_NVFBC_SW_SESSION_INTERFACE_ID (0xa0bd01U) +typedef FINN_RM_API FINN_NVFBC_SW_SESSION_NVFBC_SW_SESSION; +#define FINN_GK110_SUBDEVICE_GRAPHICS_RESERVED_INTERFACE_ID (0xa0e000U) +typedef FINN_RM_API FINN_GK110_SUBDEVICE_GRAPHICS_RESERVED; +#define FINN_GK110_SUBDEVICE_GRAPHICS_GRAPHICS_INTERFACE_ID (0xa0e001U) +typedef FINN_RM_API FINN_GK110_SUBDEVICE_GRAPHICS_GRAPHICS; +#define FINN_GK110_SUBDEVICE_FB_RESERVED_INTERFACE_ID (0xa0e100U) +typedef FINN_RM_API FINN_GK110_SUBDEVICE_FB_RESERVED; +#define FINN_GK110_SUBDEVICE_FB_FB_INTERFACE_ID (0xa0e101U) +typedef FINN_RM_API FINN_GK110_SUBDEVICE_FB_FB; +#define FINN_KEPLER_CHANNEL_GPFIFO_B_RESERVED_INTERFACE_ID (0xa16f00U) +typedef FINN_RM_API FINN_KEPLER_CHANNEL_GPFIFO_B_RESERVED; +#define FINN_KEPLER_CHANNEL_GPFIFO_B_GPFIFO_INTERFACE_ID (0xa16f01U) +typedef FINN_RM_API FINN_KEPLER_CHANNEL_GPFIFO_B_GPFIFO; +#define FINN_KEPLER_CHANNEL_GPFIFO_B_EVENT_INTERFACE_ID (0xa16f02U) +typedef FINN_RM_API FINN_KEPLER_CHANNEL_GPFIFO_B_EVENT; +#define FINN_KEPLER_CHANNEL_GPFIFO_C_RESERVED_INTERFACE_ID (0xa26f00U) +typedef FINN_RM_API FINN_KEPLER_CHANNEL_GPFIFO_C_RESERVED; +#define FINN_KEPLER_CHANNEL_GPFIFO_C_GPFIFO_INTERFACE_ID (0xa26f01U) +typedef FINN_RM_API FINN_KEPLER_CHANNEL_GPFIFO_C_GPFIFO; +#define FINN_KEPLER_CHANNEL_GPFIFO_C_EVENT_INTERFACE_ID (0xa26f02U) +typedef FINN_RM_API FINN_KEPLER_CHANNEL_GPFIFO_C_EVENT; +#define FINN_MAXWELL_FAULT_BUFFER_A_RESERVED_INTERFACE_ID (0xb06900U) +typedef FINN_RM_API FINN_MAXWELL_FAULT_BUFFER_A_RESERVED; +#define FINN_MAXWELL_FAULT_BUFFER_A_FAULTBUFFER_INTERFACE_ID (0xb06901U) +typedef FINN_RM_API FINN_MAXWELL_FAULT_BUFFER_A_FAULTBUFFER; +#define FINN_MAXWELL_CHANNEL_GPFIFO_A_RESERVED_INTERFACE_ID (0xb06f00U) +typedef FINN_RM_API FINN_MAXWELL_CHANNEL_GPFIFO_A_RESERVED; +#define FINN_MAXWELL_CHANNEL_GPFIFO_A_GPFIFO_INTERFACE_ID (0xb06f01U) +typedef FINN_RM_API FINN_MAXWELL_CHANNEL_GPFIFO_A_GPFIFO; +#define FINN_MAXWELL_CHANNEL_GPFIFO_A_EVENT_INTERFACE_ID (0xb06f02U) +typedef FINN_RM_API FINN_MAXWELL_CHANNEL_GPFIFO_A_EVENT; +#define FINN_MAXWELL_PROFILER_RESERVED_INTERFACE_ID (0xb0cc00U) +typedef FINN_RM_API FINN_MAXWELL_PROFILER_RESERVED; +#define FINN_MAXWELL_PROFILER_INTERNAL_INTERFACE_ID (0xb0cc02U) +typedef FINN_RM_API FINN_MAXWELL_PROFILER_INTERNAL; +#define FINN_MAXWELL_PROFILER_POWER_INTERFACE_ID (0xb0cc03U) +typedef FINN_RM_API FINN_MAXWELL_PROFILER_POWER; +#define FINN_MAXWELL_PROFILER_PROFILER_INTERFACE_ID (0xb0cc01U) +typedef FINN_RM_API FINN_MAXWELL_PROFILER_PROFILER; +#define FINN_MAXWELL_PROFILER_CONTEXT_RESERVED_INTERFACE_ID (0xb1cc00U) +typedef FINN_RM_API FINN_MAXWELL_PROFILER_CONTEXT_RESERVED; +#define FINN_MAXWELL_PROFILER_CONTEXT_PROFILER_INTERFACE_ID (0xb1cc01U) +typedef FINN_RM_API FINN_MAXWELL_PROFILER_CONTEXT_PROFILER; +#define FINN_MAXWELL_PROFILER_DEVICE_RESERVED_INTERFACE_ID (0xb2cc00U) +typedef FINN_RM_API FINN_MAXWELL_PROFILER_DEVICE_RESERVED; + +#define FINN_MAXWELL_SEC2_SEC2_INTERFACE_ID (0xb6b901U) +typedef FINN_RM_API FINN_MAXWELL_SEC2_SEC2; +#define FINN_PASCAL_CHANNEL_GPFIFO_A_RESERVED_INTERFACE_ID (0xc06f00U) +typedef FINN_RM_API FINN_PASCAL_CHANNEL_GPFIFO_A_RESERVED; +#define FINN_PASCAL_CHANNEL_GPFIFO_A_GPFIFO_INTERFACE_ID (0xc06f01U) +typedef FINN_RM_API FINN_PASCAL_CHANNEL_GPFIFO_A_GPFIFO; +#define FINN_PASCAL_CHANNEL_GPFIFO_A_EVENT_INTERFACE_ID (0xc06f02U) +typedef FINN_RM_API FINN_PASCAL_CHANNEL_GPFIFO_A_EVENT; +#define FINN_GP100_SUBDEVICE_GRAPHICS_RESERVED_INTERFACE_ID (0xc0e000U) +typedef FINN_RM_API FINN_GP100_SUBDEVICE_GRAPHICS_RESERVED; +#define FINN_GP100_SUBDEVICE_GRAPHICS_GRAPHICS_INTERFACE_ID (0xc0e001U) +typedef FINN_RM_API FINN_GP100_SUBDEVICE_GRAPHICS_GRAPHICS; +#define FINN_GP100_SUBDEVICE_FB_RESERVED_INTERFACE_ID (0xc0e100U) +typedef FINN_RM_API FINN_GP100_SUBDEVICE_FB_RESERVED; +#define FINN_GP100_SUBDEVICE_FB_FB_INTERFACE_ID (0xc0e101U) +typedef FINN_RM_API FINN_GP100_SUBDEVICE_FB_FB; +#define FINN_VOLTA_GSP_GSP_INTERFACE_ID (0xc31001U) +typedef FINN_RM_API FINN_VOLTA_GSP_GSP; +#define FINN_ACCESS_COUNTER_NOTIFY_BUFFER_RESERVED_INTERFACE_ID (0xc36500U) +typedef FINN_RM_API FINN_ACCESS_COUNTER_NOTIFY_BUFFER_RESERVED; +#define FINN_ACCESS_COUNTER_NOTIFY_BUFFER_ACCESS_CNTR_BUFFER_INTERFACE_ID (0xc36501U) +typedef FINN_RM_API FINN_ACCESS_COUNTER_NOTIFY_BUFFER_ACCESS_CNTR_BUFFER; +#define FINN_MMU_FAULT_BUFFER_RESERVED_INTERFACE_ID (0xc36900U) +typedef FINN_RM_API FINN_MMU_FAULT_BUFFER_RESERVED; +#define FINN_MMU_FAULT_BUFFER_MMU_FAULT_BUFFER_INTERFACE_ID (0xc36901U) +typedef FINN_RM_API FINN_MMU_FAULT_BUFFER_MMU_FAULT_BUFFER; +#define FINN_VOLTA_CHANNEL_GPFIFO_A_RESERVED_INTERFACE_ID (0xc36f00U) +typedef FINN_RM_API FINN_VOLTA_CHANNEL_GPFIFO_A_RESERVED; +#define FINN_VOLTA_CHANNEL_GPFIFO_A_GPFIFO_INTERFACE_ID (0xc36f01U) +typedef FINN_RM_API FINN_VOLTA_CHANNEL_GPFIFO_A_GPFIFO; +#define FINN_VOLTA_CHANNEL_GPFIFO_A_EVENT_INTERFACE_ID (0xc36f02U) +typedef FINN_RM_API FINN_VOLTA_CHANNEL_GPFIFO_A_EVENT; +#define FINN_NVC370_DISPLAY_RESERVED_INTERFACE_ID (0xc37000U) +typedef FINN_RM_API FINN_NVC370_DISPLAY_RESERVED; +#define FINN_NVC370_DISPLAY_CHNCTL_INTERFACE_ID (0xc37001U) +typedef FINN_RM_API FINN_NVC370_DISPLAY_CHNCTL; +#define FINN_NVC370_DISPLAY_EVENT_INTERFACE_ID (0xc37009U) +typedef FINN_RM_API FINN_NVC370_DISPLAY_EVENT; +#define FINN_NVC370_DISPLAY_RG_INTERFACE_ID (0xc37002U) +typedef FINN_RM_API FINN_NVC370_DISPLAY_RG; +#define FINN_NVC370_DISPLAY_VERIF_INTERFACE_ID (0xc37006U) +typedef FINN_RM_API FINN_NVC370_DISPLAY_VERIF; +#define FINN_NVC372_DISPLAY_SW_RESERVED_INTERFACE_ID (0xc37200U) +typedef FINN_RM_API FINN_NVC372_DISPLAY_SW_RESERVED; +#define FINN_NVC372_DISPLAY_SW_CHNCTL_INTERFACE_ID (0xc37201U) +typedef FINN_RM_API FINN_NVC372_DISPLAY_SW_CHNCTL; + +#define FINN_GV100_SUBDEVICE_GRAPHICS_RESERVED_INTERFACE_ID (0xc3e000U) +typedef FINN_RM_API FINN_GV100_SUBDEVICE_GRAPHICS_RESERVED; +#define FINN_GV100_SUBDEVICE_GRAPHICS_GRAPHICS_INTERFACE_ID (0xc3e001U) +typedef FINN_RM_API FINN_GV100_SUBDEVICE_GRAPHICS_GRAPHICS; +#define FINN_GV100_SUBDEVICE_FB_RESERVED_INTERFACE_ID (0xc3e100U) +typedef FINN_RM_API FINN_GV100_SUBDEVICE_FB_RESERVED; +#define FINN_GV100_SUBDEVICE_FB_FB_INTERFACE_ID (0xc3e101U) +typedef FINN_RM_API FINN_GV100_SUBDEVICE_FB_FB; +#define FINN_TURING_CHANNEL_GPFIFO_A_RESERVED_INTERFACE_ID (0xc46f00U) +typedef FINN_RM_API FINN_TURING_CHANNEL_GPFIFO_A_RESERVED; +#define FINN_TURING_CHANNEL_GPFIFO_A_GPFIFO_INTERFACE_ID (0xc46f01U) +typedef FINN_RM_API FINN_TURING_CHANNEL_GPFIFO_A_GPFIFO; +#define FINN_TURING_CHANNEL_GPFIFO_A_EVENT_INTERFACE_ID (0xc46f02U) +typedef FINN_RM_API FINN_TURING_CHANNEL_GPFIFO_A_EVENT; +#define FINN_AMPERE_CHANNEL_GPFIFO_A_RESERVED_INTERFACE_ID (0xc56f00U) +typedef FINN_RM_API FINN_AMPERE_CHANNEL_GPFIFO_A_RESERVED; +#define FINN_AMPERE_CHANNEL_GPFIFO_A_GPFIFO_INTERFACE_ID (0xc56f01U) +typedef FINN_RM_API FINN_AMPERE_CHANNEL_GPFIFO_A_GPFIFO; +#define FINN_AMPERE_CHANNEL_GPFIFO_A_EVENT_INTERFACE_ID (0xc56f02U) +typedef FINN_RM_API FINN_AMPERE_CHANNEL_GPFIFO_A_EVENT; +#define FINN_AMPERE_SMC_PARTITION_REF_RESERVED_INTERFACE_ID (0xc63700U) +typedef FINN_RM_API FINN_AMPERE_SMC_PARTITION_REF_RESERVED; +#define FINN_AMPERE_SMC_PARTITION_REF_EXEC_PARTITIONS_INTERFACE_ID (0xc63701U) +typedef FINN_RM_API FINN_AMPERE_SMC_PARTITION_REF_EXEC_PARTITIONS; +#define FINN_AMPERE_SMC_EXEC_PARTITION_REF_RESERVED_INTERFACE_ID (0xc63800U) +typedef FINN_RM_API FINN_AMPERE_SMC_EXEC_PARTITION_REF_RESERVED; +#define FINN_AMPERE_SMC_EXEC_PARTITION_REF_EXEC_PARTITION_INTERFACE_ID (0xc63801U) +typedef FINN_RM_API FINN_AMPERE_SMC_EXEC_PARTITION_REF_EXEC_PARTITION; +#define FINN_MMU_VIDMEM_ACCESS_BIT_BUFFER_RESERVED_INTERFACE_ID (0xc76300U) +typedef FINN_RM_API FINN_MMU_VIDMEM_ACCESS_BIT_BUFFER_RESERVED; +#define FINN_MMU_VIDMEM_ACCESS_BIT_BUFFER_VIDMEM_ACCESS_BIT_BUFFER_INTERFACE_ID (0xc76301U) +typedef FINN_RM_API FINN_MMU_VIDMEM_ACCESS_BIT_BUFFER_VIDMEM_ACCESS_BIT_BUFFER; +#define FINN_HOPPER_CHANNEL_GPFIFO_A_RESERVED_INTERFACE_ID (0xc86f00U) +typedef FINN_RM_API FINN_HOPPER_CHANNEL_GPFIFO_A_RESERVED; +#define FINN_HOPPER_CHANNEL_GPFIFO_A_GPFIFO_INTERFACE_ID (0xc86f01U) +typedef FINN_RM_API FINN_HOPPER_CHANNEL_GPFIFO_A_GPFIFO; +#define FINN_HOPPER_CHANNEL_GPFIFO_A_EVENT_INTERFACE_ID (0xc86f02U) +typedef FINN_RM_API FINN_HOPPER_CHANNEL_GPFIFO_A_EVENT; + +#define FINN_NV_CONFIDENTIAL_COMPUTE_RESERVED_INTERFACE_ID (0xcb3300U) +typedef FINN_RM_API FINN_NV_CONFIDENTIAL_COMPUTE_RESERVED; +#define FINN_NV_CONFIDENTIAL_COMPUTE_CONF_COMPUTE_INTERFACE_ID (0xcb3301U) +typedef FINN_RM_API FINN_NV_CONFIDENTIAL_COMPUTE_CONF_COMPUTE; + +#define FINN_NV_COUNTER_COLLECTION_UNIT_RESERVED_INTERFACE_ID (0xcbca00U) +typedef FINN_RM_API FINN_NV_COUNTER_COLLECTION_UNIT_RESERVED; +#define FINN_NV_COUNTER_COLLECTION_UNIT_CCU_INTERFACE_ID (0xcbca01U) +typedef FINN_RM_API FINN_NV_COUNTER_COLLECTION_UNIT_CCU; +#define FINN_NVE2_SYNCPOINT_BASE_RESERVED_INTERFACE_ID (0xe2ad00U) +typedef FINN_RM_API FINN_NVE2_SYNCPOINT_BASE_RESERVED; +#define FINN_NVE2_SYNCPOINT_BASE_SYNCPOINT_BASE_INTERFACE_ID (0xe2ad01U) +typedef FINN_RM_API FINN_NVE2_SYNCPOINT_BASE_SYNCPOINT_BASE; diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/common/sdk/nvidia/inc/mmu_fmt_types.h nvidia-open-gpu-kernel-modules-535.161.08/src/common/sdk/nvidia/inc/mmu_fmt_types.h --- nvidia-open-gpu-kernel-modules-525.147.05/src/common/sdk/nvidia/inc/mmu_fmt_types.h 2023-10-25 20:22:25.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/common/sdk/nvidia/inc/mmu_fmt_types.h 2024-03-05 22:15:21.000000000 +0000 @@ -26,7 +26,7 @@ // // This file was generated with FINN, an NVIDIA coding tool. -// Source file: mmu_fmt_types.finn +// Source file: mmu_fmt_types.finn // diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/common/sdk/nvidia/inc/nv-hypervisor.h nvidia-open-gpu-kernel-modules-535.161.08/src/common/sdk/nvidia/inc/nv-hypervisor.h --- nvidia-open-gpu-kernel-modules-525.147.05/src/common/sdk/nvidia/inc/nv-hypervisor.h 2023-10-25 20:22:25.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/common/sdk/nvidia/inc/nv-hypervisor.h 2024-03-05 22:15:21.000000000 +0000 @@ -41,6 +41,7 @@ #define CMD_VGPU_VFIO_INJECT_INTERRUPT 1 #define CMD_VGPU_VFIO_REGISTER_MDEV 2 #define CMD_VGPU_VFIO_PRESENT 3 +#define CMD_VFIO_PCI_CORE_PRESENT 4 #define MAX_VF_COUNT_PER_GPU 64 @@ -91,30 +92,6 @@ NV_VGPU_DEV_IN_USE = 2 } VGPU_DEVICE_STATE; -typedef enum _VMBUS_CMD_TYPE -{ - VMBUS_CMD_TYPE_INVALID = 0, - VMBUS_CMD_TYPE_SETUP = 1, - VMBUS_CMD_TYPE_SENDPACKET = 2, - VMBUS_CMD_TYPE_CLEANUP = 3, -} VMBUS_CMD_TYPE; - -typedef struct -{ - NvU32 request_id; - NvU32 page_count; - NvU64 *pPfns; - void *buffer; - NvU32 bufferlen; -} vmbus_send_packet_cmd_params; - - -typedef struct -{ - NvU32 override_sint; - NvU8 *nv_guid; -} vmbus_setup_cmd_params; - /* * Function prototypes */ diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/common/sdk/nvidia/inc/nv_vgpu_types.h nvidia-open-gpu-kernel-modules-535.161.08/src/common/sdk/nvidia/inc/nv_vgpu_types.h --- nvidia-open-gpu-kernel-modules-525.147.05/src/common/sdk/nvidia/inc/nv_vgpu_types.h 2023-10-25 20:22:26.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/common/sdk/nvidia/inc/nv_vgpu_types.h 2024-03-05 22:15:21.000000000 +0000 @@ -26,7 +26,7 @@ // // This file was generated with FINN, an NVIDIA coding tool. -// Source file: nv_vgpu_types.finn +// Source file: nv_vgpu_types.finn // diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/common/sdk/nvidia/inc/nvdisptypes.h nvidia-open-gpu-kernel-modules-535.161.08/src/common/sdk/nvidia/inc/nvdisptypes.h --- nvidia-open-gpu-kernel-modules-525.147.05/src/common/sdk/nvidia/inc/nvdisptypes.h 2023-10-25 20:22:26.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/common/sdk/nvidia/inc/nvdisptypes.h 2024-03-05 22:15:22.000000000 +0000 @@ -35,7 +35,7 @@ // // This file was generated with FINN, an NVIDIA coding tool. -// Source file: nvdisptypes.finn +// Source file: nvdisptypes.finn // diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/common/sdk/nvidia/inc/nverror.h nvidia-open-gpu-kernel-modules-535.161.08/src/common/sdk/nvidia/inc/nverror.h --- nvidia-open-gpu-kernel-modules-525.147.05/src/common/sdk/nvidia/inc/nverror.h 2023-10-25 20:22:26.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/common/sdk/nvidia/inc/nverror.h 2024-03-05 22:15:22.000000000 +0000 @@ -1,5 +1,5 @@ /* - * Copyright (c) 1993-2022, NVIDIA CORPORATION. All rights reserved. + * Copyright (c) 1993-2023, NVIDIA CORPORATION. All rights reserved. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), @@ -118,12 +118,14 @@ #define SPI_PMU_RPC_ERASE_FAIL (124) #define INFOROM_FS_ERROR (125) #define ALI_TRAINING_FAIL (136) +#define NVLINK_FLA_PRIV_ERR (137) +#define ROBUST_CHANNEL_DLA_ERROR (138) +#define ROBUST_CHANNEL_FAST_PATH_ERROR (139) #define UNRECOVERABLE_ECC_ERROR_ESCAPE (140) #define GPU_INIT_ERROR (143) #define ROBUST_CHANNEL_LAST_ERROR (GPU_INIT_ERROR) - // Indexed CE reference #define ROBUST_CHANNEL_CE_ERROR(x) \ ((x < 3) ? \ diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/common/sdk/nvidia/inc/nvimpshared.h nvidia-open-gpu-kernel-modules-535.161.08/src/common/sdk/nvidia/inc/nvimpshared.h --- nvidia-open-gpu-kernel-modules-525.147.05/src/common/sdk/nvidia/inc/nvimpshared.h 2023-10-25 20:22:27.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/common/sdk/nvidia/inc/nvimpshared.h 2024-03-05 22:15:22.000000000 +0000 @@ -35,7 +35,7 @@ // // This file was generated with FINN, an NVIDIA coding tool. -// Source file: nvimpshared.finn +// Source file: nvimpshared.finn // diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/common/sdk/nvidia/inc/nvlimits.h nvidia-open-gpu-kernel-modules-535.161.08/src/common/sdk/nvidia/inc/nvlimits.h --- nvidia-open-gpu-kernel-modules-525.147.05/src/common/sdk/nvidia/inc/nvlimits.h 2023-10-25 20:22:27.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/common/sdk/nvidia/inc/nvlimits.h 2024-03-05 22:15:22.000000000 +0000 @@ -25,7 +25,7 @@ // // This file was generated with FINN, an NVIDIA coding tool. -// Source file: nvlimits.finn +// Source file: nvlimits.finn // diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/common/sdk/nvidia/inc/nvos.h nvidia-open-gpu-kernel-modules-535.161.08/src/common/sdk/nvidia/inc/nvos.h --- nvidia-open-gpu-kernel-modules-525.147.05/src/common/sdk/nvidia/inc/nvos.h 2023-10-25 20:22:27.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/common/sdk/nvidia/inc/nvos.h 2024-03-05 22:15:23.000000000 +0000 @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 1993-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 1993-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -142,6 +142,7 @@ #define NVOS_STATUS_ERROR_PRIV_SEC_VIOLATION NV_ERR_PRIV_SEC_VIOLATION #define NVOS_STATUS_ERROR_GPU_IN_DEBUG_MODE NV_ERR_GPU_IN_DEBUG_MODE +#define NVOS_STATUS_ERROR_ALREADY_SIGNALLED NV_ERR_ALREADY_SIGNALLED /* Note: @@ -244,6 +245,19 @@ #define NVOS02_FLAGS_ALLOC_TYPE_SYNCPOINT_APERTURE (0x00000001) // +// Allow client allocations to go to protected/unprotected video/system memory. +// When Ampere Protected Model aka APM or Confidential Compute is enabled and +// DEFAULT flag is set by client, allocations go to protected memory. When +// protected memory is not enabled, allocations go to unprotected memory. +// If APM or CC is not enabled, it is a bug for a client to set the PROTECTED +// flag to YES +// +#define NVOS02_FLAGS_MEMORY_PROTECTION 26:25 +#define NVOS02_FLAGS_MEMORY_PROTECTION_DEFAULT (0x00000000) +#define NVOS02_FLAGS_MEMORY_PROTECTION_PROTECTED (0x00000001) +#define NVOS02_FLAGS_MEMORY_PROTECTION_UNPROTECTED (0x00000002) + +// // If _NO_MAP is requested, the RM in supported platforms will not map the // allocated system or IO memory into user space. The client can later map // memory through the RmMapMemory() interface. @@ -444,6 +458,7 @@ NvHandle hObjectNew; NvV32 hClass; NvP64 pAllocParms NV_ALIGN_BYTES(8); + NvU32 paramsSize; NvV32 status; } NVOS21_PARAMETERS; @@ -459,6 +474,7 @@ NvV32 hClass; // [in] class num of new object NvP64 pAllocParms NV_ALIGN_BYTES(8); // [IN] class-specific alloc parameters NvP64 pRightsRequested NV_ALIGN_BYTES(8); // [IN] RS_ACCESS_MASK to request rights, or NULL + NvU32 paramsSize; // [IN] Size of alloc params NvU32 flags; // [IN] flags for FINN serialization NvV32 status; // [OUT] status } NVOS64_PARAMETERS; @@ -607,7 +623,6 @@ #define NVOS32_DESCRIPTOR_TYPE_OS_SGT_PTR 6 #define NVOS32_DESCRIPTOR_TYPE_KERNEL_VIRTUAL_ADDRESS 7 // NVOS32 function -#define NVOS32_FUNCTION_ALLOC_DEPTH_WIDTH_HEIGHT 1 #define NVOS32_FUNCTION_ALLOC_SIZE 2 #define NVOS32_FUNCTION_FREE 3 // #define NVOS32_FUNCTION_HEAP_PURGE 4 @@ -684,32 +699,6 @@ union { - // NVOS32_FUNCTION_ALLOC_DEPTH_WIDTH_HEIGHT - struct - { - NvU32 owner; // [IN] - memory owner ID - NvHandle hMemory; // [IN/OUT] - unique memory handle - IN only if MEMORY_HANDLE_PROVIDED is set (otherwise generated) - NvU32 type; // [IN] - surface type, see below TYPE* defines - NvU32 flags; // [IN] - allocation modifier flags, see below ALLOC_FLAGS* defines - NvU32 depth; // [IN] - depth of surface in bits - NvU32 width; // [IN] - width of surface in pixels - NvU32 height; // [IN] - height of surface in pixels - NvU32 attr; // [IN/OUT] - surface attributes requested, and surface attributes allocated - NvU32 format; // [IN/OUT] - format requested, and format allocated - NvU32 comprCovg; // [IN/OUT] - compr covg requested, and allocated - NvU32 zcullCovg; // [OUT] - zcull covg allocated - NvU32 partitionStride; // [IN/OUT] - 0 means "RM" chooses - NvU64 size NV_ALIGN_BYTES(8); // [IN/OUT] - size of allocation - also returns the actual size allocated - NvU64 alignment NV_ALIGN_BYTES(8); // [IN] - requested alignment - NVOS32_ALLOC_FLAGS_ALIGNMENT* must be on - NvU64 offset NV_ALIGN_BYTES(8); // [IN/OUT] - desired offset if NVOS32_ALLOC_FLAGS_FIXED_ADDRESS_ALLOCATE is on AND returned offset - NvU64 limit NV_ALIGN_BYTES(8); // [OUT] - returned surface limit - NvP64 address NV_ALIGN_BYTES(8);// [OUT] - returned address - NvU64 rangeBegin NV_ALIGN_BYTES(8); // [IN] - allocated memory will be limited to the range - NvU64 rangeEnd NV_ALIGN_BYTES(8); // [IN] - from rangeBegin to rangeEnd, inclusive. - NvU32 attr2; // [IN/OUT] - surface attributes requested, and surface attributes allocated - NvU32 ctagOffset; // [IN] - comptag offset for this surface (see NVOS32_ALLOC_COMPTAG_OFFSET) - } AllocDepthWidthHeight; - // NVOS32_FUNCTION_ALLOC_SIZE struct { @@ -1308,6 +1297,18 @@ #define NVOS32_ATTR2_PROTECTION_DEVICE_READ_ONLY 0x00000001 // +// Allow client allocations to go to protected/unprotected video/system memory. +// When Ampere Protected Model aka APM or Confidential Compute is enabled and +// DEFAULT flag is set by client, allocations go to protected memory. When +// protected memory is not enabled, allocations go to unprotected memory. +// If APM or CC is not enabled, it is a bug for a client to set the PROTECTED +// flag to YES +// +#define NVOS32_ATTR2_MEMORY_PROTECTION 26:25 +#define NVOS32_ATTR2_MEMORY_PROTECTION_DEFAULT 0x00000000 +#define NVOS32_ATTR2_MEMORY_PROTECTION_PROTECTED 0x00000001 +#define NVOS32_ATTR2_MEMORY_PROTECTION_UNPROTECTED 0x00000002 +// // Force the allocation to go to guest subheap. // This flag is used by vmiop plugin to allocate from GPA // @@ -1800,15 +1801,6 @@ #define NVOS33_FLAGS_RESERVE_ON_UNMAP_DISABLE (0x00000000) #define NVOS33_FLAGS_RESERVE_ON_UNMAP_ENABLE (0x00000001) -// Systems with a coherent NVLINK2 connection between the CPU and GPU -// have the option of directly mapping video memory over that connection. -// During mapping you may specify a preference. -// -#define NVOS33_FLAGS_BUS 21:20 -#define NVOS33_FLAGS_BUS_ANY 0 -#define NVOS33_FLAGS_BUS_NVLINK_COHERENT 1 -#define NVOS33_FLAGS_BUS_PCIE 2 - // Internal use only #define NVOS33_FLAGS_OS_DESCRIPTOR 22:22 #define NVOS33_FLAGS_OS_DESCRIPTOR_DISABLE (0x00000000) @@ -2885,6 +2877,43 @@ NvV32 status; // [OUT] status of call } NV_GSP_TEST_SEND_EVENT_NOTIFICATION_PARAMETERS; +/* + * NV_VIDMEM_ACCESS_BIT_BUFFER_ADDR_SPACE_COH + * NV_VIDMEM_ACCESS_BIT_BUFFER_ADDR_SPACE_DEFAULT + * Location is Coherent System memory (also the default option) + * NV_VIDMEM_ACCESS_BIT_BUFFER_ADDR_SPACE_NCOH + * Location is Non-Coherent System memory + * NV_VIDMEM_ACCESS_BIT_BUFFER_ADDR_SPACE_VID + * Location is FB + * + * Currently only used by MODS for the V1 VAB interface. To be deleted. + */ +typedef enum +{ + NV_VIDMEM_ACCESS_BIT_BUFFER_ADDR_SPACE_DEFAULT = 0, + NV_VIDMEM_ACCESS_BIT_BUFFER_ADDR_SPACE_COH, + NV_VIDMEM_ACCESS_BIT_BUFFER_ADDR_SPACE_NCOH, + NV_VIDMEM_ACCESS_BIT_BUFFER_ADDR_SPACE_VID +} NV_VIDMEM_ACCESS_BIT_ALLOCATION_PARAMS_ADDR_SPACE; + +/** + * @brief Multiclient vidmem access bit allocation params + */ +typedef struct +{ + /* [OUT] Dirty/Access tracking */ + NvBool bDirtyTracking; + /* [OUT] Current tracking granularity */ + NvU32 granularity; + /* [OUT] 512B Access bit mask with 1s set on + bits that are reserved for this client */ + NV_DECLARE_ALIGNED(NvU64 accessBitMask[64], 8); + /* Number of entries of vidmem access buffer. Used by VAB v1 - to be deleted */ + NvU32 noOfEntries; + /* Address space of the vidmem access bit buffer. Used by VAB v1 - to be deleted */ + NV_VIDMEM_ACCESS_BIT_ALLOCATION_PARAMS_ADDR_SPACE addrSpace; +} NV_VIDMEM_ACCESS_BIT_ALLOCATION_PARAMS; + /** * @brief HopperUsermodeAParams * This set of optionalparameters is passed in on allocation of diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/common/sdk/nvidia/inc/nvstatuscodes.h nvidia-open-gpu-kernel-modules-535.161.08/src/common/sdk/nvidia/inc/nvstatuscodes.h --- nvidia-open-gpu-kernel-modules-525.147.05/src/common/sdk/nvidia/inc/nvstatuscodes.h 2023-10-25 20:22:27.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/common/sdk/nvidia/inc/nvstatuscodes.h 2024-03-05 22:15:23.000000000 +0000 @@ -149,6 +149,7 @@ NV_STATUS_CODE(NV_ERR_NVLINK_CONFIGURATION_ERROR, 0x00000078, "Nvlink Configuration Error") NV_STATUS_CODE(NV_ERR_RISCV_ERROR, 0x00000079, "Generic RISC-V assert or halt") NV_STATUS_CODE(NV_ERR_FABRIC_MANAGER_NOT_PRESENT, 0x0000007A, "Fabric Manager is not loaded") +NV_STATUS_CODE(NV_ERR_ALREADY_SIGNALLED, 0x0000007B, "Semaphore Surface value already >= requested wait value") // Warnings: NV_STATUS_CODE(NV_WARN_HOT_SWITCH, 0x00010001, "WARNING Hot switch") diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/common/sdk/nvidia/inc/nvtypes.h nvidia-open-gpu-kernel-modules-535.161.08/src/common/sdk/nvidia/inc/nvtypes.h --- nvidia-open-gpu-kernel-modules-525.147.05/src/common/sdk/nvidia/inc/nvtypes.h 2023-10-25 20:22:28.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/common/sdk/nvidia/inc/nvtypes.h 2024-03-05 22:15:23.000000000 +0000 @@ -507,6 +507,12 @@ // place to re-locate these from nvos.h which cannot be included by a number // of builds that need them +#if defined(__GNUC__) || defined(__clang__) || defined(__INTEL_COMPILER) + #define NV_ATTRIBUTE_UNUSED __attribute__((__unused__)) +#else + #define NV_ATTRIBUTE_UNUSED +#endif + #if defined(__GNUC__) #if (__GNUC__ > 3) || \ ((__GNUC__ == 3) && (__GNUC_MINOR__ >= 1) && (__GNUC_PATCHLEVEL__ >= 1)) @@ -600,12 +606,6 @@ #define NV_FORCERESULTCHECK #endif - #if defined(__GNUC__) || defined(__clang__) || defined(__INTEL_COMPILER) - #define NV_ATTRIBUTE_UNUSED __attribute__((__unused__)) - #else - #define NV_ATTRIBUTE_UNUSED - #endif - /* * Functions decorated with NV_FORMAT_PRINTF(f, a) have a format string at * parameter number 'f' and variadic arguments start at parameter number 'a'. diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/common/sdk/nvidia/inc/rs_access.h nvidia-open-gpu-kernel-modules-535.161.08/src/common/sdk/nvidia/inc/rs_access.h --- nvidia-open-gpu-kernel-modules-525.147.05/src/common/sdk/nvidia/inc/rs_access.h 2023-10-25 20:22:28.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/common/sdk/nvidia/inc/rs_access.h 2024-03-05 22:15:23.000000000 +0000 @@ -26,7 +26,7 @@ // // This file was generated with FINN, an NVIDIA coding tool. -// Source file: rs_access.finn +// Source file: rs_access.finn // diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/common/shared/inc/g_vgpu_resman_specific.h nvidia-open-gpu-kernel-modules-535.161.08/src/common/shared/inc/g_vgpu_resman_specific.h --- nvidia-open-gpu-kernel-modules-525.147.05/src/common/shared/inc/g_vgpu_resman_specific.h 2023-10-25 20:20:08.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/common/shared/inc/g_vgpu_resman_specific.h 2024-03-05 22:12:21.000000000 +0000 @@ -14,7 +14,10 @@ } vgpu_aliases[] = { { 0x20B5, 0x1642, 0x20B5, 0x1533 }, { 0x20B8, 0x1581, 0x20B5, 0x1533 }, + { 0x20B7, 0x1804, 0x20B7, 0x1532 }, { 0x20B9, 0x157F, 0x20B7, 0x1532 }, + { 0x20FD, 0x17F8, 0x20F5, 0x0 }, + { 0x2330, 0x16C0, 0x2330, 0x16C1 }, }; for (NvU32 i = 0; i < (sizeof(vgpu_aliases) / sizeof(struct vgpu_alias_details)); ++i) { @@ -28,3 +31,5 @@ return; } #endif //__VGPU_ALIAS_PGPU_LIST__ + + diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/common/shared/inc/nvdevid.h nvidia-open-gpu-kernel-modules-535.161.08/src/common/shared/inc/nvdevid.h --- nvidia-open-gpu-kernel-modules-525.147.05/src/common/shared/inc/nvdevid.h 1970-01-01 00:00:00.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/common/shared/inc/nvdevid.h 2024-03-05 22:12:22.000000000 +0000 @@ -0,0 +1,683 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 200-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef NVDEVID_H +#define NVDEVID_H + + + +/**************** Resource Manager Defines and Structures ******************\ +* * +* Private device ids defines - only defines ! * +* * +\***************************************************************************/ + +/////////////////////////////////////////////////////////////////////////////////////////// +// +// VENDOR/SUBVENDOR IDS +// XXX Cleanup to do: change PCI_VENDOR_* to NV_PCI_SUBID_VENDOR_* +// +/////////////////////////////////////////////////////////////////////////////////////////// +#define NV_PCI_SUBID_VENDOR 15:0 /* RW--F */ +#define NV_PCI_SUBID_VENDOR_AMD 0x1022 +#define NV_PCI_SUBID_VENDOR_ALI 0x10B9 +#define NV_PCI_SUBID_VENDOR_NVIDIA 0x10DE +#define NV_PCI_SUBID_VENDOR_INTEL 0x8086 +#define NV_PCI_SUBID_VENDOR_VIA 0x1106 +#define NV_PCI_SUBID_VENDOR_RCC 0x1166 +#define NV_PCI_SUBID_VENDOR_MICRON_1 0x1042 +#define NV_PCI_SUBID_VENDOR_MICRON_2 0x1344 +#define NV_PCI_SUBID_VENDOR_APPLE 0x106B +#define NV_PCI_SUBID_VENDOR_SIS 0x1039 +#define NV_PCI_SUBID_VENDOR_ATI 0x1002 +#define NV_PCI_SUBID_VENDOR_TRANSMETA 0x1279 +#define NV_PCI_SUBID_VENDOR_HP 0x103C +#define NV_PCI_SUBID_VENDOR_DELL 0x1028 +#define NV_PCI_SUBID_VENDOR_FUJITSU 0x10cf +#define NV_PCI_SUBID_VENDOR_ASUS 0x1043 +#define NV_PCI_SUBID_VENDOR_MSI 0x1462 +#define NV_PCI_SUBID_VENDOR_FOXCONN 0x105B +#define NV_PCI_SUBID_VENDOR_ECS 0x1019 +#define NV_PCI_SUBID_VENDOR_DFI_1 0x106E +#define NV_PCI_SUBID_VENDOR_TOSHIBA 0x1179 +#define NV_PCI_SUBID_VENDOR_DFI_2 0x15BD +#define NV_PCI_SUBID_VENDOR_ACER 0x1025 +#define NV_PCI_SUBID_VENDOR_GIGABYTE 0x1458 +#define NV_PCI_SUBID_VENDOR_EVGA 0x3842 +#define NV_PCI_SUBID_VENDOR_BROADCOM 0x1166 +#define NV_PCI_SUBID_VENDOR_SUPERMICRO 0x15D9 +#define NV_PCI_SUBID_VENDOR_BIOSTAR 0x1565 +#define NV_PCI_SUBID_VENDOR_XFX 0x1682 +#define NV_PCI_SUBID_VENDOR_PCPARTNER 0x19DA +#define NV_PCI_SUBID_VENDOR_LENOVO 0x17AA +#define NV_PCI_SUBID_VENDOR_FSC 0x1734 +#define NV_PCI_SUBID_VENDOR_FTS 0x1734 +#define NV_PCI_SUBID_VENDOR_COLORFUL 0x7377 +#define NV_PCI_SUBID_VENDOR_ASROCK 0x1849 +#define NV_PCI_SUBID_VENDOR_SHUTTLE 0x1297 +#define NV_PCI_SUBID_VENDOR_CLEVO 0x1558 +#define NV_PCI_SUBID_VENDOR_PEGATRON 0x1B0A +#define NV_PCI_SUBID_VENDOR_JETWAY 0x16F3 +#define NV_PCI_SUBID_VENDOR_HIGHGRADE 0x1C6C +#define NV_PCI_SUBID_VENDOR_GALAXY 0x1B4C +#define NV_PCI_SUBID_VENDOR_ZOTAC 0x19DA +#define NV_PCI_SUBID_VENDOR_ARIMA 0x161F +#define NV_PCI_SUBID_VENDOR_BFG 0x19F1 +#define NV_PCI_SUBID_VENDOR_SONY 0x104D +#define NV_PCI_SUBID_VENDOR_BITLAND 0x1642 +#define NV_PCI_SUBID_VENDOR_PC_PARTNER 0x174B +#define NV_PCI_SUBID_VENDOR_NZXT 0x1D96 + +// XXX CKEANUP TO REMOVE IN FAVOR OF NV_PCI_SUBID_VENDOR_* +#define PCI_VENDOR_ID_AMD 0x1022 +#define PCI_VENDOR_ID_ALI 0x10B9 +#define PCI_VENDOR_ID_NVIDIA 0x10DE +#define PCI_VENDOR_ID_INTEL 0x8086 +#define PCI_VENDOR_ID_VIA 0x1106 +#define PCI_VENDOR_ID_RCC 0x1166 +#define PCI_VENDOR_ID_MICRON_1 0x1042 +#define PCI_VENDOR_ID_MICRON_2 0x1344 +#define PCI_VENDOR_ID_APPLE 0x106B +#define PCI_VENDOR_ID_SIS 0x1039 +#define PCI_VENDOR_ID_ATI 0x1002 +#define PCI_VENDOR_ID_TRANSMETA 0x1279 +#define PCI_VENDOR_ID_HP 0x103C +#define PCI_VENDOR_ID_DELL 0x1028 +#define PCI_VENDOR_ID_FUJITSU 0x10cf +#define PCI_VENDOR_ID_ASUS 0x1043 +#define PCI_VENDOR_ID_MSI 0x1462 +#define PCI_VENDOR_ID_FOXCONN 0x105B +#define PCI_VENDOR_ID_ECS 0x1019 +#define PCI_VENDOR_ID_DFI_1 0x106E +#define PCI_VENDOR_ID_TOSHIBA 0x1179 +#define PCI_VENDOR_ID_DFI_2 0x15BD +#define PCI_VENDOR_ID_ACER 0x1025 +#define PCI_VENDOR_ID_GIGABYTE 0x1458 +#define PCI_VENDOR_ID_EVGA 0x3842 +#define PCI_VENDOR_ID_BROADCOM 0x1166 +#define PCI_VENDOR_ID_SUPERMICRO 0x15D9 +#define PCI_VENDOR_ID_BIOSTAR 0x1565 +#define PCI_VENDOR_ID_XFX 0x1682 +#define PCI_VENDOR_ID_PCPARTNER 0x19DA +#define PCI_VENDOR_ID_LENOVO 0x17AA +#define PCI_VENDOR_ID_FSC 0x1734 +#define PCI_VENDOR_ID_FTS 0x1734 +#define PCI_VENDOR_ID_COLORFUL 0x7377 +#define PCI_VENDOR_ID_ASROCK 0x1849 +#define PCI_VENDOR_ID_SHUTTLE 0x1297 +#define PCI_VENDOR_ID_CLEVO 0x1558 +#define PCI_VENDOR_ID_PEGATRON 0x1B0A +#define PCI_VENDOR_ID_JETWAY 0x16F3 +#define PCI_VENDOR_ID_HIGHGRADE 0x1C6C +#define PCI_VENDOR_ID_GALAXY 0x1B4C +#define PCI_VENDOR_ID_ZOTAC 0x19DA +#define PCI_VENDOR_ID_ARIMA 0x161F +#define PCI_VENDOR_ID_PC_PARTNER 0x174B +#define PCI_VENDOR_ID_APM 0x10E8 +#define PCI_VENDOR_ID_IBM 0x1014 +#define PCI_VENDOR_ID_NZXT 0x1D96 +#define PCI_VENDOR_ID_MARVELL 0x177D +#define PCI_VENDOR_ID_REDHAT 0x1B36 +#define PCI_VENDOR_ID_AMPERE 0x1DEF +#define PCI_VENDOR_ID_HUAWEI 0x19E5 +#define PCI_VENDOR_ID_MELLANOX 0x15B3 +#define PCI_VENDOR_ID_AMAZON 0x1D0F +#define PCI_VENDOR_ID_CADENCE 0x17CD +#define PCI_VENDOR_ID_ARM 0x13B5 +#define PCI_VENDOR_ID_HYGON 0x1D94 +#define PCI_VENDOR_ID_ALIBABA 0x1DED + +#define NV_PCI_DEVID_DEVICE 31:16 /* RW--F */ +#define NV_PCI_SUBID_DEVICE 31:16 /* RW--F */ + +/////////////////////////////////////////////////////////////////////////////////////////// +// +// GPU DEVICE IDS +// +/////////////////////////////////////////////////////////////////////////////////////////// + +#define NV_PCI_DEVID_DEVICE_PG171_SKU200_PG179_SKU220 0x25B6 /* NVIDIA A16 / NVIDIA A2 */ +#define NV_PCI_DEVID_DEVICE_PG189_SKU600 0x1EBA + +/////////////////////////////////////////////////////////////////////////////////////////// +// +// SUBDEVICE IDs +// +/////////////////////////////////////////////////////////////////////////////////////////// + +// A16 +#define NV_PCI_SUBID_DEVICE_PG171_SKU200 0x14A9 + +/////////////////////////////////////////////////////////////////////////////////////////// +// +// CHIPSET IDs +// +/////////////////////////////////////////////////////////////////////////////////////////// +// Desktop flavor of X58 +#define X58_DESKTOP_DEVIDS 0x3400, 0x3405 +// Mobile version of X58 +#define X58_MOBILE_DEVID 0x3405 +#define X58_MOBILE_CLEVO_7200_SSDEVID 0x7200 + +// Sandy bridge CLEVO platform +#define SANDYBRIDGE_P180HM_SSDEVID 0x8000 +#define SandyBridge_E_X79_P270WM_SSDEVID 0x270 +#define IvyBridge_Z75_P370EM_SSDEVID 0x371 + +// Device ID's of Devices present on Patsburg's PCIE bus. +#define PATSBURG_PCIE_DEVICE_MIN_DEVID 0x1D10 +#define PATSBURG_PCIE_DEVICE_MAX_DEVID 0x1D1F +#define PATSBURG_PCIE_DEVICE_DEVID 0x244E + +//Tylersburg Congurations +#define TYLERSBURG_DEVID 0x3406 + +// Intel Grantsdale definitions +#define DEVICE_ID_INTEL_2580_HOST_BRIDGE 0x2580 +#define DEVICE_ID_INTEL_2581_ROOT_PORT 0x2581 + +// Intel Alderwood definitions +#define DEVICE_ID_INTEL_2584_HOST_BRIDGE 0x2584 +#define DEVICE_ID_INTEL_2585_ROOT_PORT 0x2585 + +// Intel Alviso definitions +#define DEVICE_ID_INTEL_2590_HOST_BRIDGE 0x2590 +#define DEVICE_ID_INTEL_2591_ROOT_PORT 0x2591 + +// Intel Tumwater definitions +#define DEVICE_ID_INTEL_359E_HOST_BRIDGE 0x359E +#define DEVICE_ID_INTEL_3597_ROOT_PORT 0x3597 + +// Intel Stoakley definitions +#define INTEL_4000_SUBDEVICE_ID 0x021D + +// Intel SkullTrail definitions +#define INTEL_4003_SUBDEVICE_ID 0x5358 + +// Intel Core I7 CPU +#define INTEL_QUICKPATH_SYSTEM_ADDRESS_DECODER_I7 0x2C01 + +// Intel Core I5 CPU Lynnfield +#define INTEL_QUICKPATH_SYSTEM_ADDRESS_DECODER_I5_L 0x2C81 +#define INTEL_LYNNFIELD_ROOTPORT_CPU1 0xD138 +#define INTEL_LYNNFIELD_ROOTPORT_CPU2 0xD13A + +// Intel Core I5 CPU Auburndale +#define INTEL_QUICKPATH_SYSTEM_ADDRESS_DECODER_I5_A 0x2D41 + +// Intel Core I5 CPU 650 +#define INTEL_QUICKPATH_SYSTEM_ADDRESS_DECODER_I5_6 0x2D01 + +// Intel Poulsbo definitions +#define DEVICE_ID_INTEL_8100_HOST_BRIDGE 0x8100 +#define DEVICE_ID_INTEL_8110_ROOT_PORT 0x8110 +#define DEVICE_ID_INTEL_8112_ROOT_PORT 0x8112 + +// Intel TunnelCreek definitions +#define DEVICE_ID_INTEL_8180_ROOT_PORT 0x8180 +#define DEVICE_ID_INTEL_8181_ROOT_PORT 0x8181 +#define DEVICE_ID_INTEL_8184_ROOT_PORT 0x8184 +#define DEVICE_ID_INTEL_8185_ROOT_PORT 0x8185 + +// Intel I/O Hub definitions +#define DEVICE_ID_INTEL_3408_ROOT_PORT 0x3408 +#define DEVICE_ID_INTEL_3411_ROOT_PORT 0x3411 +#define DEVICE_ID_INTEL_3420_ROOT_PORT 0x3420 +#define DEVICE_ID_INTEL_3421_ROOT_PORT 0x3421 + +// Intel SandyBridge IIO definitions +#define DEVICE_ID_INTEL_3C02_ROOT_PORT 0x3c02 +#define DEVICE_ID_INTEL_3C03_ROOT_PORT 0x3c03 +#define DEVICE_ID_INTEL_3C04_ROOT_PORT 0x3c04 +#define DEVICE_ID_INTEL_3C05_ROOT_PORT 0x3c05 +#define DEVICE_ID_INTEL_3C06_ROOT_PORT 0x3c06 +#define DEVICE_ID_INTEL_3C07_ROOT_PORT 0x3c07 +#define DEVICE_ID_INTEL_3C08_ROOT_PORT 0x3c08 +#define DEVICE_ID_INTEL_3C09_ROOT_PORT 0x3c09 +#define DEVICE_ID_INTEL_3C0A_ROOT_PORT 0x3c0a +#define DEVICE_ID_INTEL_3C0B_ROOT_PORT 0x3c0b + +// Intel Haswell-E definitions +#define DEVICE_ID_INTEL_2F00_HOST_BRIDGE 0x2f00 +#define DEVICE_ID_INTEL_2F01_ROOT_PORT 0x2f01 +#define DEVICE_ID_INTEL_2F02_ROOT_PORT 0x2f02 +#define DEVICE_ID_INTEL_2F03_ROOT_PORT 0x2f03 +#define DEVICE_ID_INTEL_2F04_ROOT_PORT 0x2f04 +#define DEVICE_ID_INTEL_2F05_ROOT_PORT 0x2f05 +#define DEVICE_ID_INTEL_2F06_ROOT_PORT 0x2f06 +#define DEVICE_ID_INTEL_2F07_ROOT_PORT 0x2f07 +#define DEVICE_ID_INTEL_2F08_ROOT_PORT 0x2f08 +#define DEVICE_ID_INTEL_2F09_ROOT_PORT 0x2f09 +#define DEVICE_ID_INTEL_2F0A_ROOT_PORT 0x2f0a +#define DEVICE_ID_INTEL_2F0B_ROOT_PORT 0x2f0b + +#define DEVICE_ID_INTEL_0C01_ROOT_PORT 0x0c01 + +// Intel IvyTown definitions + +#define DEVICE_ID_INTEL_0E02_ROOT_PORT 0x0e02 +#define DEVICE_ID_INTEL_0E03_ROOT_PORT 0x0e03 +#define DEVICE_ID_INTEL_0E04_ROOT_PORT 0x0e04 +#define DEVICE_ID_INTEL_0E05_ROOT_PORT 0x0e05 +#define DEVICE_ID_INTEL_0E06_ROOT_PORT 0x0e06 +#define DEVICE_ID_INTEL_0E07_ROOT_PORT 0x0e07 +#define DEVICE_ID_INTEL_0E08_ROOT_PORT 0x0e08 +#define DEVICE_ID_INTEL_0E09_ROOT_PORT 0x0e09 +#define DEVICE_ID_INTEL_0E0A_ROOT_PORT 0x0e0a +#define DEVICE_ID_INTEL_0E0B_ROOT_PORT 0x0e0b +// Intel Ivy Bridge E definitions +#define DEVICE_ID_INTEL_0E00_HOST_BRIDGE 0x0E00 + +// Intel Haswell definitions +#define DEVICE_ID_INTEL_0C00_HASWELL_HOST_BRIDGE 0x0C00 +#define DEVICE_ID_INTEL_0C04_HASWELL_HOST_BRIDGE 0x0C04 + +// Intel PCH definitions +#define DEVICE_ID_INTEL_9D10_PCH_BRIDGE 0x9d10 +#define DEVICE_ID_INTEL_9D18_PCH_BRIDGE 0x9d18 +#define DEVICE_ID_INTEL_A117_PCH_BRIDGE 0xa117 +#define DEVICE_ID_INTEL_A118_PCH_BRIDGE 0xa118 +#define DEVICE_ID_INTEL_9C98_PCH_BRIDGE 0x9c98 + +// Intel Broadwell definitions +#define DEVICE_ID_INTEL_6F00_HOST_BRIDGE 0x6f00 +#define DEVICE_ID_INTEL_6F01_ROOT_PORT 0x6f01 +#define DEVICE_ID_INTEL_6F02_ROOT_PORT 0x6f02 +#define DEVICE_ID_INTEL_6F03_ROOT_PORT 0x6f03 +#define DEVICE_ID_INTEL_6F04_ROOT_PORT 0x6f04 +#define DEVICE_ID_INTEL_6F05_ROOT_PORT 0x6f05 +#define DEVICE_ID_INTEL_6F06_ROOT_PORT 0x6f06 +#define DEVICE_ID_INTEL_6F07_ROOT_PORT 0x6f07 +#define DEVICE_ID_INTEL_6F08_ROOT_PORT 0x6f08 +#define DEVICE_ID_INTEL_6F09_ROOT_PORT 0x6f09 +#define DEVICE_ID_INTEL_6F0A_ROOT_PORT 0x6f0A +#define DEVICE_ID_INTEL_6F0B_ROOT_PORT 0x6f0B +#define DEVICE_ID_INTEL_1601_ROOT_PORT 0x1601 +#define DEVICE_ID_INTEL_1605_ROOT_PORT 0x1605 +#define DEVICE_ID_INTEL_1609_ROOT_PORT 0x1609 +#define DEVICE_ID_INTEL_BROADWELL_U_HOST_BRIDGE 0x1604 +#define DEVICE_ID_INTEL_BROADWELL_H_HOST_BRIDGE 0x1614 + +// Intel Skylake definitions +#define DEVICE_ID_INTEL_1901_ROOT_PORT 0x1901 +#define DEVICE_ID_INTEL_1905_ROOT_PORT 0x1905 +#define DEVICE_ID_INTEL_1909_ROOT_PORT 0x1909 +#define DEVICE_ID_INTEL_SKYLAKE_U_HOST_BRIDGE 0x1904 +#define DEVICE_ID_INTEL_SKYLAKE_S_HOST_BRIDGE 0x191F +#define DEVICE_ID_INTEL_SKYLAKE_H_HOST_BRIDGE 0x1910 + +// Intel Skylake-E definitions +#define DEVICE_ID_INTEL_2030_ROOT_PORT 0x2030 +#define DEVICE_ID_INTEL_2033_ROOT_PORT 0x2033 + +// Intel Kabylake definitions +#define DEVICE_ID_INTEL_KABYLAKE_U_HOST_BRIDGE 0x5904 +#define DEVICE_ID_INTEL_KABYLAKE_H_HOST_BRIDGE 0x5910 + +// AMD Matisse, Rome definitions +#define DEVICE_ID_AMD_1483_ROOT_PORT 0x1483 +// AMD Castle Peak definition +#define DEVICE_ID_AMD_1480_ROOT_PORT 0x1480 +// AMD Renoir-H definition +#define DEVICE_ID_AMD_1630_ROOT_PORT 0x1630 + +// Dell SkullTrail definitions +#define DELL_4003_SUBDEVICE_ID 0x021D + +// Dell Quicksilver MLK definitions +#define DELL_0040_SUBDEVICE_ID 0x043a + +// HP Tylersburg definitions +#define TYLERSBURG_Z800_SSDEVID 0x130B + +// HP Romley definitions +#define ROMLEY_Z820_SSDEVID 0x158B +#define ROMLEY_Z620_SSDEVID 0x158A +#define ROMLEY_Z420_SSDEVID 0x1589 + +// HP Grantley definitions +#define GRANTLEY_Z840_SSDEVID 0x2129 +#define GRANTLEY_Z640_SSDEVID 0x212A +#define GRANTLEY_Z440_SSDEVID 0x212B + +// HP PURELY definitions +#define HP_QUADRO_Z4GEN4_DEVID 0xA2D2 +#define PURLEY_Z8GEN4_SSDEVID 0x81C7 +#define PURLEY_Z6GEN4_SSDEVID 0x81C6 +#define PURLEY_Z4GEN4_SSDEVID 0x81C5 + +// Lenovo Romley definitions +#define ROMLEY_C30_SSDEVID 0x1028 +#define ROMLEY_D30_SSDEVID 0x1027 +#define ROMLEY_S30_SSDEVID 0x1026 + +// Dell Romley definitions +#define ROMLEY_T7600_SSDEVID 0x0495 +#define ROMLEY_T5600_SSDEVID 0x0496 +#define ROMLEY_T3600_SSDEVID 0x0497 + +// Dell Romley + IVB-EP CPU Refresh +#define IVYTOWN_T7610_SSDEVID 0x05D4 +#define IVYTOWN_T5610_SSDEVID 0x05D3 + +// Dell Romley (Ipanema) +#define ROMLEY_R7610_SSDEVID 0x05A1 + +// FTS Romley definitions +#define ROMLEY_R920_SSDEVID 0x11B6 + +// Lenovo Grantley (Messi, Pele, Ronaldo) +#define GRANTLEY_V40_SSDEVID 0x1031 +#define GRANTLEY_D40_SSDEVID 0x1030 +#define GRANTLEY_S40_SSDEVID 0x102F + +// Dell Grantley (Avalon) +#define GRANTLEY_T7810_SSDEVID 0x0618 +#define GRANTLEY_T7910_SSDEVID 0x0619 + +// Lenovo Purley (Nile, Volga) +#define PURLEY_P920_SSDEVID 0x1038 +#define PURLEY_P720_SSDEVID 0x1037 +#define PURLEY_P520_SSDEVID 0x1036 + +// Dell Purley(Matira) +#define PURLEY_MATIRA3X_DEVID 0xA2D2 +#define PURLEY_MATIRA3X_SSDEVID 0x08B1 +#define PURLEY_MATIRA3_SSDEVID 0x0738 +#define PURLEY_MATIRA5_SSDEVID 0x0739 +#define PURLEY_MATIRA7_SSDEVID 0x073A + +//FTS Purley +#define PURLEY_R970_SSDEVID 0x1230 +#define PURLEY_M770_SSDEVID 0x1231 + +// HP Arrandale, Clarksfield, X58 workstation definitions +#define ARRANDALE_Z200SFF_SSDEVID 0x304A +#define CLARKSFIELD_Z200_SSDEVID 0x170B +#define X58_Z400_SSDEVID 0x1309 + +// GIGABYTE Sniper 3 (Z77) +#define GIGABYTE_SNIPER_3_SSDEVID_1 0x5000 +#define GIGABYTE_SNIPER_3_SSDEVID_2 0x5001 + +// Supermicro Quadro VCA definitions +#define SUPERMICRO_QUADRO_VCA_DEVID 0x8D44 +#define SUPERMICRO_QUADRO_VCA_SSDEVID 0x7270 + +// Asus Quadro BOXX definitions +#define ASUS_QUADRO_BOXX_DEVID 0x8D44 +#define ASUS_QUADRO_BOXX_SSDEVID 0x85F6 + +// APEXX8 Quadro BOXX definitions +#define APEXX8_QUADRO_BOXX_DEVID 0xA2D3 +#define APEXX8_QUADRO_BOXX_SSDEVID 0x098e + +// APEXX5 Quadro BOXX definitions +#define APEXX5_QUADRO_BOXX_DEVID 0xA2D3 +#define APEXX5_QUADRO_BOXX_SSDEVID 0x1000 + +// ASUS X99-E-10G +#define ASUS_X99_E_10G_SSDEVID 0x8600 + +// VIA definitions +#define DEVICE_ID_VIA_VT8369B_HOST_BRIDGE 0x0308 + +// Foxconn Einstein 64 [8086:a1c1][105b:7270] +#define FOXCONN_EINSTEIN_64_DEVID 0xA1C1 +#define FOXCONN_EINSTEIN_64_SSDEVID 0x7270 + +// Lenovo Tomcat/Falcon/Hornet Workstations +#define LENOVO_TOMCAT_DEVID 0x1B81 +#define LENOVO_TOMCAT_SSDEVID 0x104e +#define LENOVO_FALCON_DEVID 0x7A8A +#define LENOVO_FALCON_SSDEVID 0x1055 +#define LENOVO_HORNET_DEVID 0x7A8A +#define LENOVO_HORNET_SSDEVID 0x1056 + +// NVIDIA C51 +#define NVIDIA_C51_DEVICE_ID_MIN 0x2F0 +#define NVIDIA_C51_ULDT_CFG_0_DEVICE_ID_0 0x2F0 +#define NVIDIA_C51_ULDT_CFG_0_DEVICE_ID_1 0x2F1 +#define NVIDIA_C51_ULDT_CFG_0_DEVICE_ID_2 0x2F2 +#define NVIDIA_C51_ULDT_CFG_0_DEVICE_ID_3 0x2F3 +#define NVIDIA_C51_ULDT_CFG_0_DEVICE_ID_IGPU_DISABLE_0 0x2F4 +#define NVIDIA_C51_ULDT_CFG_0_DEVICE_ID_IGPU_DISABLE_1 0x2F5 +#define NVIDIA_C51_ULDT_CFG_0_DEVICE_ID_IGPU_DISABLE_2 0x2F6 +#define NVIDIA_C51_ULDT_CFG_0_DEVICE_ID_IGPU_DISABLE_3 0x2F7 +#define NVIDIA_C51_DEVICE_ID_MAX 0x2F7 + +// NVIDIA MCP55 +#define NVIDIA_MCP55_ULDT_CFG_0_DEVICE_ID_DEFAULT 0x0369 + +// NVIDIA MCP61 +#define NVIDIA_MCP61_ULDT_CFG_0_DEVICE_ID_DEFAULT 0x03EA +#define NVIDIA_MCP61_ULDT_CFG_0_DEVICE_ID_PA 0x03E2 + +// NVIDIA C55 +#define NVIDIA_C55_CPU_PCI_0_DEVICE_ID_PRO 0x03A0 +#define NVIDIA_C55_CPU_PCI_0_DEVICE_ID_PRO 0x03A0 +#define NVIDIA_C55_CPU_PCI_0_DEVICE_ID_SLIX16 0x03A1 +#define NVIDIA_C55_CPU_PCI_0_DEVICE_ID_SLI 0x03A3 +#define NVIDIA_C55_CPU_PCI_0_DEVICE_ID_U 0x03A2 + +// NVIDIA MCP65 +#define NVIDIA_MCP65_ULDT_CFG_0_DEVICE_ID_DEFAULT 0x0444 + +// NVIDIA MCP67/MCP68 +#define NVIDIA_MCP67_ULDT_CFG_0_DEVICE_ID_DEFAULT 0x0547 + +// NVIDIA MCP73 +#define NVIDIA_MCP73_CPU_PCI_0_DEVICE_ID_PV 0x07C0 +#define NVIDIA_MCP73_CPU_PCI_0_DEVICE_ID_O 0x07C1 +#define NVIDIA_MCP73_CPU_PCI_0_DEVICE_ID_S 0x07C2 +#define NVIDIA_MCP73_CPU_PCI_0_DEVICE_ID_V 0x07C3 +#define NVIDIA_MCP73_CPU_PCI_0_DEVICE_ID_RSVD_0 0x07C4 +#define NVIDIA_MCP73_CPU_PCI_0_DEVICE_ID_RSVD_1 0x07C5 +#define NVIDIA_MCP73_CPU_PCI_0_DEVICE_ID_RSVD_2 0x07C6 +#define NVIDIA_MCP73_CPU_PCI_0_DEVICE_ID_D 0x07C7 + +// NVIDIA C73 +#define NVIDIA_C73_CPU_PCI_0_DEVICE_ID_SLI2 0x0800 +#define NVIDIA_C73_CPU_PCI_0_DEVICE_ID_SLI_ALL 0x0801 +#define NVIDIA_C73_CPU_PCI_0_DEVICE_ID_SLIX8 0x0802 +#define NVIDIA_C73_CPU_PCI_0_DEVICE_ID_U 0x0803 +#define NVIDIA_C73_CPU_PCI_0_DEVICE_ID_RESERVED_0 0x0804 +#define NVIDIA_C73_CPU_PCI_0_DEVICE_ID_RESERVED_1 0x0805 +#define NVIDIA_C73_CPU_PCI_0_DEVICE_ID_RESERVED_2 0x0806 +#define NVIDIA_C73_CPU_PCI_0_DEVICE_ID_RESERVED_3 0x0807 + +// NVIDIA MCP77/78 +#define NVIDIA_MCP77_ULDT_CFG_0_DEVICE_ID_DEFAULT 0x0754 +#define NVIDIA_MCP77_ULDT_CFG_0_DEVICE_ID_1 0x0755 +#define NVIDIA_MCP77_ULDT_CFG_0_DEVICE_ID_2 0x0756 +#define NVIDIA_MCP77_ULDT_CFG_0_DEVICE_ID_3 0x0757 +#define NVIDIA_MCP77_MCP_SM_CFG_0_DEVICE_ID_UNIT_SM 0x0752 + +// NVIDIA MCP79/7A +#define NVIDIA_MCP79_CPU_PCI_0_DEVICE_ID_DEFAULT 0x0A80 +#define NVIDIA_MCP79_CPU_PCI_0_DEVICE_ID_SLIX16 0x0A81 +#define NVIDIA_MCP79_CPU_PCI_0_DEVICE_ID_SLI 0x0A82 +#define NVIDIA_MCP79_CPU_PCI_0_DEVICE_ID_U 0x0A83 +#define NVIDIA_MCP79_CPU_PCI_0_DEVICE_ID_GM 0x0A84 +#define NVIDIA_MCP79_CPU_PCI_0_DEVICE_ID_GVM 0x0A85 +#define NVIDIA_MCP79_MCP_SM_CFG_0_DEVICE_ID_UNIT_SM 0x0AA2 + +// NVIDIA MCP89/P83 +#define NVIDIA_MCP89_CPU_PCI_0_DEVICE_ID_DEFAULT 0x00000D60 + +/////////////////////////////////////////////////////////////////////////////////////////// +// +// enumeration of chipset families +// +/////////////////////////////////////////////////////////////////////////////////////////// + +enum { + CS_UNKNOWN = 0x0000, + CS_UNKNOWN_PCIE = 0x1000 +, CS_INTEL_2580 +, CS_INTEL_2584 +, CS_INTEL_2588 +, CS_INTEL_2590 +, CS_INTEL_25E0 +, CS_INTEL_29X0 +, CS_INTEL_29E0 +, CS_INTEL_359E +, CS_INTEL_4000 +, CS_INTEL_4003 +, CS_INTEL_3400 +, CS_INTEL_3B42 +, CS_INTEL_2770 +, CS_INTEL_2774 +, CS_INTEL_277C +, CS_INTEL_2A40 +, CS_INTEL_2E00 +, CS_INTEL_0040 +, CS_INTEL_1C10 +, CS_INTEL_1C46 +, CS_INTEL_1C49 +, CS_INTEL_1D40 +, CS_INTEL_8D47 +, CS_INTEL_1E10 +, CS_INTEL_8C4B +, CS_INTEL_8CC4 +, CS_INTEL_A145 +, CS_INTEL_A2C5 +, CS_INTEL_A242 +, CS_INTEL_A2D2 +, CS_INTEL_A2C9 +, CS_INTEL_A301 +, CS_INTEL_0685 +, CS_INTEL_4381 +, CS_INTEL_7A82 +, CS_NVIDIA_CK804 +, CS_NVIDIA_C19 +, CS_NVIDIA_C51 +, CS_NVIDIA_MCP55 +, CS_NVIDIA_MCP61 +, CS_NVIDIA_C55 +, CS_NVIDIA_MCP65 +, CS_NVIDIA_MCP67 +, CS_NVIDIA_MCP73 +, CS_NVIDIA_C73 +, CS_NVIDIA_MCP77 +, CS_NVIDIA_MCP79 +, CS_NVIDIA_MCP89 +, CS_NVIDIA_TEGRA3 +, CS_SIS_649 +, CS_SIS_656 +, CS_ATI_RS400 +, CS_ATI_RS400_A21 +, CS_ATI_RS480 +, CS_ATI_RS480_A21 +, CS_AMD_RS780 +, CS_VIA_VT8369B +, CS_ATI_FX790 +, CS_ATI_RD850 +, CS_ATI_RD870 +, CS_ATI_RD890 +, CS_ATI_FX890 +, CS_ATI_RX780 +, CS_ATI_FX990 +, CS_AMD_GX890 +, CS_AMD_X370 +, CS_VIA_VX900 +, CS_APM_STORM +, CS_IBM_VENICE +, CS_NVIDIA_T124 +, CS_NVIDIA_T210 +, CS_NVIDIA_T186 +, CS_NVIDIA_T194 +, CS_NVIDIA_T234 +, CS_NVIDIA_T23x +, CS_NVIDIA_TH500 +, CS_MARVELL_THUNDERX2 +, CS_REDHAT_QEMU +, CS_AMPERE_EMAG +, CS_HUAWEI_KUNPENG920 +, CS_MELLANOX_BLUEFIELD +, CS_AMAZON_GRAVITRON2 +, CS_FUJITSU_A64FX +, CS_AMPERE_ALTRA +, CS_ARM_NEOVERSEN1 +, CS_MARVELL_OCTEON_CN96XX +, CS_MARVELL_OCTEON_CN98XX +, CS_INTEL_C620 +, CS_HYGON_C86 +, CS_PHYTIUM_S2500 +, CS_MELLANOX_BLUEFIELD2 +, CS_MELLANOX_BLUEFIELD3 +, CS_ALIBABA_YITIAN +, CS_INTEL_1B81 +, CS_INTEL_18DC +, CS_INTEL_7A04 +, CS_AMPERE_AMPEREONE +, CS_MAX_PCIE +}; + +enum { + RP_UNKNOWN = 0 +, RP_BROADCOM_HT2100 +, RP_INTEL_2581 +, RP_INTEL_2585 +, RP_INTEL_2589 +, RP_INTEL_2591 +, RP_INTEL_3597 +, RP_INTEL_2775 +, RP_INTEL_2771 +, RP_INTEL_8110 +, RP_INTEL_8112 +, RP_INTEL_8180 +, RP_INTEL_8181 +, RP_INTEL_8184 +, RP_INTEL_8185 +, RP_INTEL_3C02 +, RP_INTEL_3C03 +, RP_INTEL_3C04 +, RP_INTEL_3C05 +, RP_INTEL_3C06 +, RP_INTEL_3C07 +, RP_INTEL_3C08 +, RP_INTEL_3C09 +, RP_INTEL_3C0A +, RP_INTEL_3C0B +, RP_INTEL_2F04 +, RP_INTEL_2F08 +, RP_INTEL_0C01 +, RP_INTEL_1601 +, RP_INTEL_1605 +, RP_INTEL_1609 +, RP_INTEL_1901 +, RP_INTEL_1905 +, RP_INTEL_1909 +, RP_INTEL_5904 +, RP_NVIDIA_CK804 +, RP_NVIDIA_C19 +, RP_NVIDIA_C51 +, RP_NVIDIA_MCP55 +, RP_NVIDIA_MCP61 +, RP_NVIDIA_C55 +, RP_NVIDIA_MCP65 +}; + +#endif //NVDEVID_H + diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/common/softfloat/source/f64_to_i64_r_minMag.c nvidia-open-gpu-kernel-modules-535.161.08/src/common/softfloat/source/f64_to_i64_r_minMag.c --- nvidia-open-gpu-kernel-modules-525.147.05/src/common/softfloat/source/f64_to_i64_r_minMag.c 2023-10-25 20:22:19.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/common/softfloat/source/f64_to_i64_r_minMag.c 2024-03-05 22:11:49.000000000 +0000 @@ -90,7 +90,7 @@ *--------------------------------------------------------------------*/ sig |= UINT64_C( 0x0010000000000000 ); absZ = sig>>shiftDist; - if ( exact && (absZ<pPushChannel; NvPushDevicePtr pPushDevice = pPushChannel->pDevice; const NvU32 classNumber = p3dChannel->p3dDevice->classNumber; + const NvU32 numChannels = + pPushDevice->clientSli ? pPushDevice->numSubDevices : 1; int sd; /* @@ -44,15 +46,13 @@ nvAssert(p3dChannel->p3dDevice->pPushDevice == pParams->pPushChannel->pDevice); - for (sd = 0; - sd < ARRAY_LEN(pPushChannel->channelHandle) && - pPushChannel->channelHandle[sd] != 0; - sd++) { + for (sd = 0; sd < numChannels; sd++) { if (nvPushIsAModel(pPushDevice)) { nvAssert(sd == 0); } else { const NvPushImports *pImports = pPushDevice->pImports; + nvAssert(pPushChannel->channelHandle[sd] != 0); nvAssert(pParams->handle[sd] != 0); NvU32 ret = pImports->rmApiAlloc(pPushDevice, pPushChannel->channelHandle[sd], diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/common/unix/nvidia-3d/src/nvidia-3d-init.c nvidia-open-gpu-kernel-modules-535.161.08/src/common/unix/nvidia-3d/src/nvidia-3d-init.c --- nvidia-open-gpu-kernel-modules-525.147.05/src/common/unix/nvidia-3d/src/nvidia-3d-init.c 2023-10-25 20:22:32.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/common/unix/nvidia-3d/src/nvidia-3d-init.c 2024-03-05 22:12:08.000000000 +0000 @@ -285,10 +285,13 @@ { NV2080_CTRL_GR_INFO_SM_VERSION_8_6, { 8,6 } }, { NV2080_CTRL_GR_INFO_SM_VERSION_8_7, { 8,6 } }, { NV2080_CTRL_GR_INFO_SM_VERSION_8_8, { 8,6 } }, + /* Ada */ { NV2080_CTRL_GR_INFO_SM_VERSION_8_9, { 8,9 } }, + /* Hopper */ { NV2080_CTRL_GR_INFO_SM_VERSION_9_0, { 9,0 } }, + }; const NvU32 smVersion = GetSmVersion(pPushDevice); diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/common/unix/nvidia-3d/src/nvidia-3d-kepler.c nvidia-open-gpu-kernel-modules-535.161.08/src/common/unix/nvidia-3d/src/nvidia-3d-kepler.c --- nvidia-open-gpu-kernel-modules-525.147.05/src/common/unix/nvidia-3d/src/nvidia-3d-kepler.c 2023-10-25 20:22:32.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/common/unix/nvidia-3d/src/nvidia-3d-kepler.c 2024-03-05 22:12:09.000000000 +0000 @@ -102,10 +102,6 @@ nvPushSetMethodDataU64(p, gpuBaseAddress + offset + bytesSoFar); nvPushSetMethodData(p, bytesThisChunk); // NVA097_PITCH_OUT - nvPushMethod(p, NVA06F_SUBCHANNEL_3D, NVA097_SET_DST_WIDTH, 2); - nvPushSetMethodData(p, bytesThisChunk); - nvPushSetMethodData(p, 1); // NVA097_SET_DST_HEIGHT - nvPushMethodOneIncr(p, NVA06F_SUBCHANNEL_3D, NVA097_LAUNCH_DMA, 1 + dwordsThisChunk); nvPushSetMethodData(p, diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/common/unix/nvidia-push/interface/nvidia-push-init.h nvidia-open-gpu-kernel-modules-535.161.08/src/common/unix/nvidia-push/interface/nvidia-push-init.h --- nvidia-open-gpu-kernel-modules-525.147.05/src/common/unix/nvidia-push/interface/nvidia-push-init.h 2023-10-25 20:22:32.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/common/unix/nvidia-push/interface/nvidia-push-init.h 2024-03-05 22:12:10.000000000 +0000 @@ -131,6 +131,7 @@ NvU32 numClasses; const NvU32 *supportedClasses; + NvPushConfidentialComputeMode confidentialComputeMode; } NvPushAllocDeviceParams; NvBool nvPushAllocDevice( @@ -174,6 +175,13 @@ NvBool ignoreChannelErrors; /* + * This flag specifies if channel is intended to be used for + * encryption/decryption of data between SYSMEM <-> VIDMEM. Only CE + * & SEC2 Channels are capable of handling encrypted content. + */ + NvBool secureChannel; + + /* * DIFR stands for Display Idle Frame Refresh in which a CE is used to * prefetch framebuffer pixels into the GPU's L2 cache. The prefetch * operation requires the channel to be specifically configured for DIFR diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/common/unix/nvidia-push/interface/nvidia-push-types.h nvidia-open-gpu-kernel-modules-535.161.08/src/common/unix/nvidia-push/interface/nvidia-push-types.h --- nvidia-open-gpu-kernel-modules-525.147.05/src/common/unix/nvidia-push/interface/nvidia-push-types.h 2023-10-25 20:22:33.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/common/unix/nvidia-push/interface/nvidia-push-types.h 2024-03-05 22:12:10.000000000 +0000 @@ -69,6 +69,17 @@ #endif } NvPushChannelUnion; +typedef enum _NvPushConfidentialComputeMode { + /* Confidential computing is not in use. */ + NV_PUSH_CONFIDENTIAL_COMPUTE_MODE_NONE, + + /* + * The confidential compute mode of operation is Hopper Confidential + * Compute (HCC). + */ + NV_PUSH_CONFIDENTIAL_COMPUTE_MODE_HCC, +} NvPushConfidentialComputeMode; + typedef struct _NvPushChannelRec NvPushChannelRec; typedef struct _NvPushChannelRec *NvPushChannelPtr; @@ -121,6 +132,8 @@ NvPushHal hal; const struct _NvPushImports *pImports; + /* Provided by the host driver */ + NvPushConfidentialComputeMode confidentialComputeMode; } NvPushDeviceRec, *NvPushDevicePtr; diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/common/unix/nvidia-push/src/nvidia-push-init.c nvidia-open-gpu-kernel-modules-535.161.08/src/common/unix/nvidia-push/src/nvidia-push-init.c --- nvidia-open-gpu-kernel-modules-525.147.05/src/common/unix/nvidia-push/src/nvidia-push-init.c 2023-10-25 20:22:33.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/common/unix/nvidia-push/src/nvidia-push-init.c 2024-03-05 22:12:10.000000000 +0000 @@ -412,6 +412,9 @@ } params.flags = 0; + if (pParams->secureChannel) { + params.flags |= DRF_DEF(OS04, _FLAGS, _CC_SECURE, _TRUE); + } if (pParams->difrPrefetch) { params.flags |= DRF_DEF(OS04, _FLAGS, @@ -1482,6 +1485,8 @@ pDevice->numClasses = pParams->numClasses; pDevice->supportedClasses = pParams->supportedClasses; + pDevice->confidentialComputeMode = pParams->confidentialComputeMode; + for (sd = 0; sd < pParams->numSubDevices; sd++) { pDevice->subDevice[sd].handle = pParams->subDevice[sd].handle; pDevice->subDevice[sd].deviceHandle = pParams->subDevice[sd].deviceHandle; diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/common/unix/nvidia-push/src/nvidia-push.c nvidia-open-gpu-kernel-modules-535.161.08/src/common/unix/nvidia-push/src/nvidia-push.c --- nvidia-open-gpu-kernel-modules-525.147.05/src/common/unix/nvidia-push/src/nvidia-push.c 2023-10-25 20:22:33.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/common/unix/nvidia-push/src/nvidia-push.c 2024-03-05 22:12:10.000000000 +0000 @@ -1014,7 +1014,7 @@ // Must be done before submitting the semaphore release to ensure the maximum // known-submitted value is never less than the semaphore's current value. - NvTimeSemFermiSetMaxSubmitted(report, val); + NvTimeSemFermiSetMaxSubmittedVal(&report->timer, val); nvPushMethod(p, 0, NVA16F_SEMAPHOREA, 4); nvPushSetMethodDataU64(p, gpuAddress); // NVA16F_SEMAPHOREB @@ -1106,13 +1106,6 @@ pHal->caps.extendedBase = TRUE; // otherwise backwards compatible with the Volta DMA HAL // fall through -#if defined(__GNUC__) && __GNUC__ >= 7 - // GCC apparently doesn't think the comment above is sufficient to - // quiet -Wimplicit-fallthrough, when there are preprocessor - // directives between it and the next case. - // This attribute is only supported on gcc 7 and later. - __attribute__ ((fallthrough)); -#endif case AMPERE_CHANNEL_GPFIFO_A: // backwards compatible with the Volta DMA HAL // fall through diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/common/uproc/os/common/include/libos_v2_crashcat.h nvidia-open-gpu-kernel-modules-535.161.08/src/common/uproc/os/common/include/libos_v2_crashcat.h --- nvidia-open-gpu-kernel-modules-525.147.05/src/common/uproc/os/common/include/libos_v2_crashcat.h 1970-01-01 00:00:00.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/common/uproc/os/common/include/libos_v2_crashcat.h 2024-03-05 22:15:24.000000000 +0000 @@ -0,0 +1,147 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ +#ifndef LIBOS_V2_CRASHCAT_H +#define LIBOS_V2_CRASHCAT_H + +#include "nv-crashcat.h" +#include "nv-crashcat-decoder.h" + +// libosv2 implements the CrashCat V1 protocol with the following implementation-defined bits + +typedef enum +{ + LibosPanicReasonUnspecified = 0x00, + LibosPanicReasonUnrecoverableTaskCrash = 0x01, + LibosPanicReasonUnhandledState = 0x02, + LibosPanicReasonInvalidConfiguration = 0x03, + LibosPanicReasonFatalHardwareError = 0x04, + LibosPanicReasonInsufficientResources = 0x05, + LibosPanicReasonTimeout = 0x06, + LibosPanicReasonEnvCallFailed = 0x07, + LibosPanicReasonSspStackCheckFailed = 0x08, + LibosPanicReasonAsanMemoryError = 0x09, + LibosPanicReasonTest = 0x0a, + LibosPanicReasonProgrammingError = 0x0b, + LibosPanicReasonDebugAssertionFailed = 0x0c, + LibosPanicReasonCount +} LibosPanicReason; + +// NV_CRASHCAT_REPORT_IMPLEMENTER_SIGNATURE (bits 63:0) - "LIBOS2.0" +#define NV_CRASHCAT_REPORT_IMPLEMENTER_SIGNATURE_LIBOS2 (0x4C49424F53322E30ull) + +// NV_CRASHCAT_REPORT_V1_REPORTER_ID_IMPL_DEF (bits 63:24) +#define NV_CRASHCAT_REPORT_V1_REPORTER_ID_LIBOS2_TASK_ID 31:24 +#define NV_CRASHCAT_REPORT_V1_REPORTER_ID_LIBOS2_TASK_ID_UNSPECIFIED 0xFF +#define NV_CRASHCAT_REPORT_V1_REPORTER_ID_LIBOS2_RESERVED 63:32 + +static NV_INLINE +void crashcatReportV1SetReporterLibos2TaskId(NvCrashCatReport_V1 *pReport, NvU8 task_id) +{ + pReport->reporterId = FLD_SET_DRF_NUM64(_CRASHCAT, _REPORT_V1_REPORTER_ID, _LIBOS2_TASK_ID, + task_id, pReport->reporterId); +} + +static NV_INLINE +NvU8 crashcatReportV1ReporterLibos2TaskId(NvCrashCatReport_V1 *pReport) +{ + return (NvU8)DRF_VAL64(_CRASHCAT, _REPORT_V1_REPORTER_ID, _LIBOS2_TASK_ID, pReport->reporterId); +} + +// NV_CRASHCAT_REPORT_V1_REPORTER_DATA_VERSION (bits 31:0) +#define NV_CRASHCAT_REPORT_V1_REPORTER_DATA_VERSION_LIBOS2_CL 23:0 +#define NV_CRASHCAT_REPORT_V1_REPORTER_DATA_VERSION_LIBOS2_MINOR 27:24 +#define NV_CRASHCAT_REPORT_V1_REPORTER_DATA_VERSION_LIBOS2_MAJOR 31:28 + +static NV_INLINE +void crashcatReportV1SetReporterVersionLibos2(NvCrashCatReport_V1 *pReport, NvU32 cl) +{ + pReport->reporterData = FLD_SET_DRF_NUM64(_CRASHCAT, _REPORT_V1_REPORTER_DATA, + _VERSION_LIBOS2_MAJOR, 2, pReport->reporterData); + pReport->reporterData = FLD_SET_DRF_NUM64(_CRASHCAT, _REPORT_V1_REPORTER_DATA, + _VERSION_LIBOS2_MINOR, 0, pReport->reporterData); + pReport->reporterData = FLD_SET_DRF_NUM64(_CRASHCAT, _REPORT_V1_REPORTER_DATA, + _VERSION_LIBOS2_CL, cl, pReport->reporterData); +} + +static NV_INLINE +NvU32 crashcatReportV1ReporterVersionLibos2Cl(NvCrashCatReport_V1 *pReport) +{ + return DRF_VAL(_CRASHCAT, _REPORT_V1_REPORTER_DATA_VERSION, _LIBOS2_CL, + crashcatReportV1ReporterVersion(pReport)); +} + +static NV_INLINE +NvU8 crashcatReportV1ReporterVersionLibos2Minor(NvCrashCatReport_V1 *pReport) +{ + return (NvU8)DRF_VAL(_CRASHCAT, _REPORT_V1_REPORTER_DATA_VERSION, _LIBOS2_MINOR, + crashcatReportV1ReporterVersion(pReport)); +} + +static NV_INLINE +NvU8 crashcatReportV1ReporterVersionLibos2Major(NvCrashCatReport_V1 *pReport) +{ + return (NvU8)DRF_VAL(_CRASHCAT, _REPORT_V1_REPORTER_DATA_VERSION, _LIBOS2_MAJOR, + crashcatReportV1ReporterVersion(pReport)); +} + +// NV_CRASHCAT_REPORT_V1_SOURCE_ID_IMPL_DEF (63:24) +#define NV_CRASHCAT_REPORT_V1_SOURCE_ID_LIBOS2_TASK_ID 31:24 +#define NV_CRASHCAT_REPORT_V1_SOURCE_ID_LIBOS2_TASK_ID_UNSPECIFIED 0xFF +#define NV_CRASHCAT_REPORT_V1_SOURCE_ID_LIBOS2_RESERVED 63:32 + +static NV_INLINE +void crashcatReportV1SetSourceLibos2TaskId(NvCrashCatReport_V1 *pReport, NvU8 task_id) +{ + pReport->sourceId = FLD_SET_DRF_NUM64(_CRASHCAT, _REPORT_V1_SOURCE_ID, _LIBOS2_TASK_ID, task_id, + pReport->sourceId); +} + +static NV_INLINE +NvU8 crashcatReportV1SourceLibos2TaskId(NvCrashCatReport_V1 *pReport) +{ + return (NvU8)DRF_VAL64(_CRASHCAT, _REPORT_V1_SOURCE_ID, _LIBOS2_TASK_ID, pReport->sourceId); +} + +// NV_CRASHCAT_REPORT_V1_SOURCE_CAUSE_IMPL_DEF (63:32) +#define NV_CRASHCAT_REPORT_V1_SOURCE_CAUSE_LIBOS2_REASON 39:32 +#define NV_CRASHCAT_REPORT_V1_SOURCE_CAUSE_LIBOS2_RESERVED 63:40 + +ct_assert(LibosPanicReasonCount <= + NVBIT(DRF_SIZE(NV_CRASHCAT_REPORT_V1_SOURCE_CAUSE_LIBOS2_REASON))); + +static NV_INLINE +void crashcatReportV1SetSourceCauseLibos2Reason(NvCrashCatReport_V1 *pReport, + LibosPanicReason reason) +{ + pReport->sourceCause = FLD_SET_DRF_NUM64(_CRASHCAT, _REPORT_V1_SOURCE_CAUSE, _LIBOS2_REASON, + reason, pReport->sourceCause); +} + +static NV_INLINE +LibosPanicReason crashcatReportV1SourceCauseLibos2Reason(NvCrashCatReport_V1 *pReport) +{ + return (LibosPanicReason)DRF_VAL64(_CRASHCAT, _REPORT_V1_SOURCE_CAUSE, _LIBOS2_REASON, + pReport->sourceCause); +} + +#endif // LIBOS_V2_CRASHCAT_H diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/common/uproc/os/common/include/libos_v3_crashcat.h nvidia-open-gpu-kernel-modules-535.161.08/src/common/uproc/os/common/include/libos_v3_crashcat.h --- nvidia-open-gpu-kernel-modules-525.147.05/src/common/uproc/os/common/include/libos_v3_crashcat.h 1970-01-01 00:00:00.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/common/uproc/os/common/include/libos_v3_crashcat.h 2024-03-05 22:15:25.000000000 +0000 @@ -0,0 +1,174 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ +#ifndef LIBOS_V3_CRASH_CAT_H +#define LIBOS_V3_CRASH_CAT_H + +#include "nv-crashcat.h" +#include "nv-crashcat-decoder.h" + +// libosv3 implements the CrashCat V1 protocol with the following implementation-defined bits + +typedef enum +{ + LibosPanicReasonUnspecified = 0x00, + LibosPanicReasonUnhandledState = 0x01, + LibosPanicReasonInvalidConfiguration = 0x02, + LibosPanicReasonFatalHardwareError = 0x03, + LibosPanicReasonInsufficientResources = 0x04, + LibosPanicReasonTimeout = 0x05, + LibosPanicReasonEnvCallFailed = 0x06, + LibosPanicReasonAsanMemoryError = 0x08, + LibosPanicReasonProgrammingError = 0x0a, + LibosPanicReasonAssertionFailed = 0x0b, + LibosPanicReasonTrapKernelPanic = 0x0c, + LibosPanicReasonTrapInstruction = 0x0d, + LibosPanicReasonCount +} LibosPanicReason; + +typedef enum{ + LibosKernelModuleInit = 0x00, + LibosKernelModuleIpi = 0x01, + LibosKernelModuleLoader = 0x02, + LibosKernelModulePartition = 0x03, + LibosKernelModuleSbi = 0x04, + LibosKernelModulePagetable = 0x05, + LibosKernelModuleAddressSpace = 0x06, + LibosKernelModuleIdentity = 0x07, + LibosKernelModuleObjectPool = 0x08, + LibosKernelModulePageState = 0x09, + LibosKernelModuleMemoryPool = 0x10, + LibosKernelModuleBuddyState = 0x11, + LibosKernelModuleServer = 0x12, + LibosKernelModuleDmaDriver = 0x13, + LibosKernelModuleExtIntrDriver = 0x14, + LibosKernelModuleSoftMmuCore = 0x15, + LibosKernelModulePagestream = 0x16, + LibosKernelModuleTask = 0x17, + LibosKernelModuleGdmaDriver = 0x18, + LibosKernelModuleCacheDriver = 0x19, + LibosKernelModuleMinTree = 0x20, + LibosKernelModuleList = 0x21, + LibosKernelModuleSpinlock = 0x22, + LibosKernelModuleScheduler = 0x23, + LibosKernelModulePort = 0x24, + LibosKernelModuleGlobalPort = 0x25, + LibosKernelModuleProxyPort = 0x26, + LibosKernelModuleTimer = 0x27, +} LibosKernelModule; + +// NV_CRASHCAT_REPORT_IMPLEMENTER_SIGNATURE (bits 63:0) - "LIBOS3.1" +#define NV_CRASHCAT_REPORT_IMPLEMENTER_SIGNATURE_LIBOS3 (0x4C49424F53332E31ull) + +// NV_CRASHCAT_REPORT_V1_REPORTER_ID_IMPL_DEF (bits 63:18) +#define NV_CRASHCAT_REPORT_V1_REPORTER_ID_LIBOS3_TASK_ID 31:24 +#define NV_CRASHCAT_REPORT_V1_REPORTER_ID_LIBOS3_RESERVED 63:32 +#define NV_CRASHCAT_REPORT_V1_REPORTER_ID_LIBOS3_TASK_ID_UNSPECIFIED (0xFF) + +static NV_INLINE +void crashcatReportV1SetReporterLibos3TaskId(NvCrashCatReport_V1 *pReport, NvU8 task_id) +{ + pReport->reporterId = FLD_SET_DRF_NUM64(_CRASHCAT, _REPORT_V1_REPORTER_ID, _LIBOS3_TASK_ID, + task_id, pReport->reporterId); +} + +static NV_INLINE +NvU8 crashcatReportV1ReporterLibos3TaskId(NvCrashCatReport_V1 *pReport) +{ + return (NvU8)DRF_VAL64(_CRASHCAT, _REPORT_V1_REPORTER_ID, _LIBOS3_TASK_ID, pReport->reporterId); +} + +// NV_CRASHCAT_REPORT_V1_REPORTER_DATA_VERSION (bits 31:0) +#define NV_CRASHCAT_REPORT_V1_REPORTER_DATA_VERSION_LIBOS3_CL 23:0 +#define NV_CRASHCAT_REPORT_V1_REPORTER_DATA_VERSION_LIBOS3_MINOR 27:24 +#define NV_CRASHCAT_REPORT_V1_REPORTER_DATA_VERSION_LIBOS3_MAJOR 31:28 + +static NV_INLINE +void crashcatReportV1SetReporterVersionLibos3(NvCrashCatReport_V1 *pReport, NvU32 cl) +{ + pReport->reporterData = FLD_SET_DRF_NUM64(_CRASHCAT, _REPORT_V1_REPORTER_DATA, + _VERSION_LIBOS3_MAJOR, 3, pReport->reporterData); + pReport->reporterData = FLD_SET_DRF_NUM64(_CRASHCAT, _REPORT_V1_REPORTER_DATA, + _VERSION_LIBOS3_MINOR, 1, pReport->reporterData); + pReport->reporterData = FLD_SET_DRF_NUM64(_CRASHCAT, _REPORT_V1_REPORTER_DATA, + _VERSION_LIBOS3_CL, cl, pReport->reporterData); +} + +static NV_INLINE +NvU32 crashcatReportV1ReporterVersionLibos3Cl(NvCrashCatReport_V1 *pReport) +{ + return DRF_VAL(_CRASHCAT, _REPORT_V1_REPORTER_DATA_VERSION, _LIBOS3_CL, + crashcatReportV1ReporterVersion(pReport)); +} + +static NV_INLINE +NvU8 crashcatReportV1ReporterVersionLibos3Minor(NvCrashCatReport_V1 *pReport) +{ + return (NvU8)DRF_VAL(_CRASHCAT, _REPORT_V1_REPORTER_DATA_VERSION, _LIBOS3_MINOR, + crashcatReportV1ReporterVersion(pReport)); +} + +static NV_INLINE +NvU8 crashcatReportV1ReporterVersionLibos3Major(NvCrashCatReport_V1 *pReport) +{ + return (NvU8)DRF_VAL(_CRASHCAT, _REPORT_V1_REPORTER_DATA_VERSION, _LIBOS3_MAJOR, + crashcatReportV1ReporterVersion(pReport)); +} + +// NV_CRASHCAT_REPORT_V1_SOURCE_ID_IMPL_DEF (63:18) +#define NV_CRASHCAT_REPORT_V1_SOURCE_ID_LIBOS3_TASK_ID 31:24 +#define NV_CRASHCAT_REPORT_V1_SOURCE_ID_LIBOS3_RESERVED 63:32 +#define NV_CRASHCAT_REPORT_V1_SOURCE_ID_LIBOS3_TASK_ID_UNSPECIFIED (0xFF) + +static NV_INLINE +void crashcatReportV1SetSourceLibos3TaskId(NvCrashCatReport_V1 *pReport, NvU8 task_id) +{ + pReport->sourceId = FLD_SET_DRF_NUM64(_CRASHCAT, _REPORT_V1_SOURCE_ID, _LIBOS3_TASK_ID, task_id, + pReport->sourceId); +} + +static NV_INLINE +NvU8 crashcatReportV1SourceLibos3TaskId(NvCrashCatReport_V1 *pReport) +{ + return (NvU8)DRF_VAL64(_CRASHCAT, _REPORT_V1_SOURCE_ID, _LIBOS3_TASK_ID, pReport->sourceId); +} + +// NV_CRASHCAT_REPORT_V1_SOURCE_CAUSE_IMPL_DEF (63:32) +#define NV_CRASHCAT_REPORT_V1_SOURCE_CAUSE_LIBOS3_REASON 39:32 +#define NV_CRASHCAT_REPORT_V1_SOURCE_CAUSE_LIBOS3_RESERVED 63:40 + +static NV_INLINE +void crashcatReportV1SetSourceCauseLibos3Reason(NvCrashCatReport_V1 *pReport, + LibosPanicReason reason) +{ + pReport->sourceCause = FLD_SET_DRF_NUM64(_CRASHCAT, _REPORT_V1_SOURCE_CAUSE, _LIBOS3_REASON, + reason, pReport->sourceCause); +} + +static NV_INLINE +LibosPanicReason crashcatReportV1SourceCauseLibos3Reason(NvCrashCatReport_V1 *pReport) +{ + return (LibosPanicReason)DRF_VAL64(_CRASHCAT, _REPORT_V1_SOURCE_CAUSE, _LIBOS3_REASON, + pReport->sourceCause); +} + +#endif // LIBOS_V3_CRASH_CAT_H diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/common/uproc/os/common/include/nv-crashcat-decoder.h nvidia-open-gpu-kernel-modules-535.161.08/src/common/uproc/os/common/include/nv-crashcat-decoder.h --- nvidia-open-gpu-kernel-modules-525.147.05/src/common/uproc/os/common/include/nv-crashcat-decoder.h 1970-01-01 00:00:00.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/common/uproc/os/common/include/nv-crashcat-decoder.h 2024-03-05 22:15:25.000000000 +0000 @@ -0,0 +1,243 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef NV_CRASHCAT_DECODER_H +#define NV_CRASHCAT_DECODER_H + +#include "nv-crashcat.h" + +// This header defines decoder/consumer-side implementation helpers for the CrashCat protocol + +// +// Wayfinder L0 Bitfield Accessors +// +static NV_INLINE +NvBool crashcatWayfinderL0Valid(NvCrashCatWayfinderL0_V1 wfl0) +{ + return FLD_TEST_DRF(_CRASHCAT, _WAYFINDER_L0, _SIGNATURE, _VALID, wfl0); +} + +static NV_INLINE +NV_CRASHCAT_WAYFINDER_VERSION crashcatWayfinderL0Version(NvCrashCatWayfinderL0_V1 wfl0) +{ + return (NV_CRASHCAT_WAYFINDER_VERSION)DRF_VAL(_CRASHCAT, _WAYFINDER_L0, _VERSION, wfl0); +} + +static NV_INLINE +NV_CRASHCAT_SCRATCH_GROUP_ID crashcatWayfinderL0V1Wfl1Location(NvCrashCatWayfinderL0_V1 wfl0) +{ + return (NV_CRASHCAT_SCRATCH_GROUP_ID)DRF_VAL(_CRASHCAT, _WAYFINDER_L0_V1, _WFL1_LOCATION, wfl0); +} + +// +// Wayfinder L1 Bitfield Accessors +// +static NV_INLINE +NV_CRASHCAT_MEM_APERTURE crashcatWayfinderL1V1QueueAperture(NvCrashCatWayfinderL1_V1 wfl1) +{ + return (NV_CRASHCAT_MEM_APERTURE)DRF_VAL64(_CRASHCAT, _WAYFINDER_L1_V1, _QUEUE_APERTURE, wfl1); +} + +static NV_INLINE +NvLength crashcatWayfinderL1V1QueueSize(NvCrashCatWayfinderL1_V1 wfl1) +{ + NvU8 unitShift; + NV_CRASHCAT_MEM_UNIT_SIZE unitSize = + (NV_CRASHCAT_MEM_UNIT_SIZE)DRF_VAL64(_CRASHCAT, _WAYFINDER_L1_V1, _QUEUE_UNIT_SIZE, wfl1); + switch (unitSize) + { + case NV_CRASHCAT_MEM_UNIT_SIZE_1KB: unitShift = 10; break; + case NV_CRASHCAT_MEM_UNIT_SIZE_4KB: unitShift = 12; break; + case NV_CRASHCAT_MEM_UNIT_SIZE_64KB: unitShift = 16; break; + default: return 0; + } + + // Increment size, since the size in the header is size - 1 (queue of 0 size is not encodable) + return (NvLength)((DRF_VAL64(_CRASHCAT, _WAYFINDER_L1_V1, _QUEUE_SIZE, wfl1) + 1) << unitShift); +} + +static NV_INLINE +NvU64 crashcatWayfinderL1V1QueueOffset(NvCrashCatWayfinderL1_V1 wfl1) +{ + return DRF_VAL64(_CRASHCAT, _WAYFINDER_L1_V1, _QUEUE_OFFSET_1KB, wfl1) << 10; +} + +// +// CrashCat Packet Header (Unversioned) Bitfield Accessors +// +static NV_INLINE +NV_CRASHCAT_PACKET_FORMAT_VERSION crashcatPacketHeaderFormatVersion(NvCrashCatPacketHeader hdr) +{ + return (NV_CRASHCAT_PACKET_FORMAT_VERSION)DRF_VAL64(_CRASHCAT, _PACKET_HEADER, _FORMAT_VERSION, + hdr); +} + +static NV_INLINE +NvLength crashcatPacketHeaderPayloadSize(NvCrashCatPacketHeader hdr) +{ + NvU8 unitShift = 0; + NV_CRASHCAT_MEM_UNIT_SIZE unitSize = + (NV_CRASHCAT_MEM_UNIT_SIZE)DRF_VAL64(_CRASHCAT, _PACKET_HEADER, _PAYLOAD_UNIT_SIZE, hdr); + switch (unitSize) + { + case NV_CRASHCAT_MEM_UNIT_SIZE_8B: unitShift = 3; break; + case NV_CRASHCAT_MEM_UNIT_SIZE_1KB: unitShift = 10; break; + case NV_CRASHCAT_MEM_UNIT_SIZE_4KB: unitShift = 12; break; + case NV_CRASHCAT_MEM_UNIT_SIZE_64KB: unitShift = 16; break; + } + + // Increment size, since the size in the header is size - 1 (payload of 0 size is not encodable) + return (NvLength)((DRF_VAL64(_CRASHCAT, _PACKET_HEADER, _PAYLOAD_SIZE, hdr) + 1) << unitShift); +} + +static NV_INLINE +NvBool crashcatPacketHeaderValid(NvCrashCatPacketHeader hdr) +{ + return (FLD_TEST_DRF64(_CRASHCAT, _PACKET_HEADER, _SIGNATURE, _VALID, hdr) && + (crashcatPacketHeaderFormatVersion(hdr) > 0) && + (crashcatPacketHeaderFormatVersion(hdr) <= NV_CRASHCAT_PACKET_FORMAT_VERSION_LAST) && + (crashcatPacketHeaderPayloadSize(hdr) > 0)); +} + +// +// CrashCat Packet Header (V1) Bitfield Accessors +// +static NV_INLINE +NV_CRASHCAT_PACKET_TYPE crashcatPacketHeaderV1Type(NvCrashCatPacketHeader_V1 hdr) +{ + return (NV_CRASHCAT_PACKET_TYPE)DRF_VAL64(_CRASHCAT, _PACKET_HEADER, _V1_TYPE, hdr); +} + +// +// CrashCat Report V1 Bitfield Accessors +// +static NV_INLINE +NvCrashCatNvriscvPartition crashcatReportV1ReporterPartition(NvCrashCatReport_V1 *pReport) +{ + return (NvCrashCatNvriscvPartition)DRF_VAL64(_CRASHCAT, _REPORT_V1_REPORTER_ID, + _NVRISCV_PARTITION, pReport->reporterId); +} + +static NV_INLINE +NvCrashCatNvriscvUcodeId crashcatReportV1ReporterUcodeId(NvCrashCatReport_V1 *pReport) +{ + return (NvCrashCatNvriscvUcodeId)DRF_VAL64(_CRASHCAT, _REPORT_V1_REPORTER_ID, _NVRISCV_UCODE_ID, + pReport->reporterId); +} + +static NV_INLINE +NV_CRASHCAT_RISCV_MODE crashcatReportV1ReporterMode(NvCrashCatReport_V1 *pReport) +{ + return (NV_CRASHCAT_RISCV_MODE)DRF_VAL64(_CRASHCAT, _REPORT_V1_REPORTER_ID, _RISCV_MODE, + pReport->reporterId); +} + +static NV_INLINE +NvU32 crashcatReportV1ReporterVersion(NvCrashCatReport_V1 *pReport) +{ + return (NvU32)DRF_VAL64(_CRASHCAT, _REPORT_V1_REPORTER_DATA, _VERSION, pReport->reporterData); +} + +static NV_INLINE +NvU32 crashcatReportV1ReporterTimestamp(NvCrashCatReport_V1 *pReport) +{ + return (NvU32)DRF_VAL64(_CRASHCAT, _REPORT_V1_REPORTER_DATA, _TIMESTAMP, pReport->reporterData); +} + + +static NV_INLINE +NvCrashCatNvriscvPartition crashcatReportV1SourcePartition(NvCrashCatReport_V1 *pReport) +{ + return (NvCrashCatNvriscvPartition)DRF_VAL64(_CRASHCAT, _REPORT_V1_SOURCE_ID, + _NVRISCV_PARTITION, pReport->sourceId); +} + +static NV_INLINE +NvCrashCatNvriscvUcodeId crashcatReportV1SourceUcodeId(NvCrashCatReport_V1 *pReport) +{ + return (NvCrashCatNvriscvUcodeId)DRF_VAL64(_CRASHCAT, _REPORT_V1_SOURCE_ID, _NVRISCV_UCODE_ID, + pReport->sourceId); +} + +static NV_INLINE +NV_CRASHCAT_RISCV_MODE crashcatReportV1SourceMode(NvCrashCatReport_V1 *pReport) +{ + return (NV_CRASHCAT_RISCV_MODE)DRF_VAL64(_CRASHCAT, _REPORT_V1_SOURCE_ID, _RISCV_MODE, + pReport->sourceId); +} + +static NV_INLINE +NV_CRASHCAT_CAUSE_TYPE crashcatReportV1SourceCauseType(NvCrashCatReport_V1 *pReport) +{ + return (NV_CRASHCAT_CAUSE_TYPE)DRF_VAL64(_CRASHCAT, _REPORT_V1_SOURCE_CAUSE, _TYPE, + pReport->sourceCause); +} + +// +// CrashCat RISC-V 64-bit CSR State V1 Bitfield Accessors +// +static NV_INLINE +NV_CRASHCAT_RISCV_MODE crashcatRiscv64CsrStateV1Mode(NvCrashCatRiscv64CsrState_V1 *pRiscv64CsrState) +{ + return (NV_CRASHCAT_RISCV_MODE)DRF_VAL64(_CRASHCAT, _RISCV64_CSR_STATE_V1_HEADER, _RISCV_MODE, + pRiscv64CsrState->header); +} + +// +// CrashCat RISC-V 64-bit GPR State V1 Bitfield Accessors +// +static NV_INLINE +NV_CRASHCAT_RISCV_MODE crashcatRiscv64GprStateV1Mode(NvCrashCatRiscv64GprState_V1 *pRiscv64GprState) +{ + return (NV_CRASHCAT_RISCV_MODE)DRF_VAL64(_CRASHCAT, _RISCV64_GPR_STATE_V1_HEADER, _RISCV_MODE, + pRiscv64GprState->header); +} + +// +// CrashCat RISC-V 64-bit Trace V1 Bitfield Accessors +// +static NV_INLINE +NV_CRASHCAT_RISCV_MODE crashcatRiscv64TraceV1Mode(NvCrashCatRiscv64Trace_V1 *pRiscv64Trace) +{ + return (NV_CRASHCAT_RISCV_MODE)DRF_VAL64(_CRASHCAT, _RISCV64_TRACE_V1_HEADER, _RISCV_MODE, + pRiscv64Trace->header); +} + +static NV_INLINE +NV_CRASHCAT_TRACE_TYPE crashcatRiscv64TraceV1Type(NvCrashCatRiscv64Trace_V1 *pRiscv64Trace) +{ + return (NV_CRASHCAT_TRACE_TYPE)DRF_VAL64(_CRASHCAT, _RISCV64_TRACE_V1_HEADER, _TRACE_TYPE, + pRiscv64Trace->header); +} + +// +// CrashCat 32-bit I/O State V1 Bitfield Accessors +// +static NV_INLINE +NV_CRASHCAT_IO_APERTURE crashcatIo32StateV1Aperture(NvCrashCatIo32State_V1 *pIo32State) +{ + return (NV_CRASHCAT_IO_APERTURE)DRF_VAL64(_CRASHCAT, _IO32_STATE_V1_HEADER, _APERTURE, + pIo32State->header); +} + +#endif // NV_CRASHCAT_DECODER_H diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/common/uproc/os/common/include/nv-crashcat.h nvidia-open-gpu-kernel-modules-535.161.08/src/common/uproc/os/common/include/nv-crashcat.h --- nvidia-open-gpu-kernel-modules-525.147.05/src/common/uproc/os/common/include/nv-crashcat.h 1970-01-01 00:00:00.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/common/uproc/os/common/include/nv-crashcat.h 2024-03-05 22:15:25.000000000 +0000 @@ -0,0 +1,861 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef NV_CRASHCAT_H +#define NV_CRASHCAT_H + +#include "nvtypes.h" +#include "nvmisc.h" +#include "nvctassert.h" + +// +// NVIDIA CrashCat - Crash Reporting And Signaling Helpers for Peregrine +// +// When a crash occurs on a Peregrine core, NVIDIA firmware may report additional data for post- +// mortem analysis of the crash. The protocol is described in greater detail elsewhere, but in +// general is defined to be a multi-producer/single-consumer flow as follows: +// +// 1. Peregrine writes a wayfinder to a set of predefined registers to indicate a crash report is +// in progress, and its general location (first crash only) +// 2. Peregrine writes crash report data in a tagged format to a circular queue accessible to both +// reporter and consumer of the crash reports. +// 3. Peregrine completes the wayfinder by updating a put pointer to indicate the crash report is +// complete. +// 4. Peregrine raises a beacon interrupt to the consumer to signal the presence of a crash report. +// +// This header contains the shared type and bitfield definitions that are common to both producer +// and consumer sides of the CrashCat protocol. +// + +#define NV_CRASHCAT_SIGNATURE 0xdead + +// +// CrashCat Wayfinder Protocol Versions +// A new version is created when backward-incompatible changes are made (the wayfinders and queue +// control cannot be handled by software written for a prior version). +// +// This version indicates the handling sequence and format of the wayfinder registers, except for +// the 16-bit signature and (this) 4-bit version number in the L0 wayfinder. +// +typedef enum { + NV_CRASHCAT_WAYFINDER_VERSION_1 = 0x01, + NV_CRASHCAT_WAYFINDER_VERSION_LAST = 0x01, +} NV_CRASHCAT_WAYFINDER_VERSION; + +// +// CrashCat Packet Format Versions +// A new version is created when backward-incompatible changes are made (packets cannot be handled +// by software written for a prior version). +// +// This version indicates the format of the upper 32 bits of the packet header, and, along with the +// NV_CRASHCAT_PACKET_TYPE, the format of the payload. +// +// The lower 32 bits of the packet header, which include the 16-bit signature, (this) 4-bit +// version number, and 2-bit payload size unit and 10-bit payload size, are not covered by this +// version number and their format must not change. +// +typedef enum { + NV_CRASHCAT_PACKET_FORMAT_VERSION_1 = 0x01, + NV_CRASHCAT_PACKET_FORMAT_VERSION_LAST = 0x01 +} NV_CRASHCAT_PACKET_FORMAT_VERSION; + +// Utility macro for ensuring the maximum enum value will fit in a DRF bitfield +#define STATIC_ASSERT_ENUM_FITS_IN_BITFIELD(e, bf) \ + ct_assert(e ## _LAST < NVBIT(DRF_SIZE(bf))) + +// +// The below enum definitions are generally unversioned, and so new values must only be added to +// the end, and existing values cannot be changed or removed (except for the _LAST values). +// Note that adding a new value may require a new version of the wayfinder protocol or packet +// formats that use the enum to accommodate a new maximum value. +// + +// +// CrashCat Scratch Group Identifier +// Each enum value represents an ordered set of one or more scratch registers in the Peregrine IP. +// See NV_CRASHCAT_DEF_SCRATCH_GROUP_V1_REGMAP_TABLE for the canonical list of registers in each +// scratch group for version 1 of the wayfinder protocol. +// +// This enum is used by the wayfinder protocol (version 1). +// +typedef enum { + NV_CRASHCAT_SCRATCH_GROUP_ID_NONE = 0x0, + NV_CRASHCAT_SCRATCH_GROUP_ID_A = 0x1, + NV_CRASHCAT_SCRATCH_GROUP_ID_B = 0x2, + NV_CRASHCAT_SCRATCH_GROUP_ID_C = 0x3, + NV_CRASHCAT_SCRATCH_GROUP_ID_D = 0x4, + NV_CRASHCAT_SCRATCH_GROUP_ID_E = 0x5, + NV_CRASHCAT_SCRATCH_GROUP_ID_F = 0x6, + + // + // Note: NV_CRASHCAT_SCRATCH_GROUP_ID_IMPL_DEF represents a set of registers which are defined + // by the implementer instead of the protocol specification - producer and consumer must + // agree on this set definition. + // + NV_CRASHCAT_SCRATCH_GROUP_ID_IMPL_DEF = 0x7, + NV_CRASHCAT_SCRATCH_GROUP_ID_LAST = 0x7 +} NV_CRASHCAT_SCRATCH_GROUP_ID; + +// +// Canonical CrashCat Scratch Group Register Mappings (V1) +// This macro defines a designated-initializer table mapping NV_CRASHCAT_SCRATCH_GROUP_ID values to +// 0-terminated arrays of register offsets (relative to the NV_PFALCON register space base offset). +// This mapping is defined for version 1 of the wayfinder protocol; future versions may use a +// different mapping. +// +// This header does not define, or include any header that defines, the register offset macros used +// in the table entries. The caller should include the appropriate header defining these register +// offsets before invoking this macro. +// +// If the implementation intends to use the NV_CRASCHCAT_SCRATCH_GROUP_ID_IMPL_DEF group, it can +// invoke NV_CRASHCAT_DEF_SCRATCH_GROUP_V1_REGMAP_TABLE_WITH_IMPL_DEF() macro with the list of +// registers to be used for the IMPL_DEF group (up to 4). Example: +// +// NV_CRASHCAT_DEF_SCRATCH_GROUP_V1_REGMAP_TABLE_WITH_IMPL_DEF(scratchOffsetTable, +// NV_PUNIT_REG0, NV_PUNIT_REG1, NV_PUNIT_REG2, NV_PUNIT_REG3); +// + +// Maximum number of registers in a scratch group for now +#define NV_CRASHCAT_SCRATCH_GROUP_V1_MAX_NUM_REGISTERS 4 + +#define NV_CRASHCAT_DEF_SCRATCH_GROUP_V1_REGMAP_TABLE(tblName) \ + NV_CRASHCAT_DEF_SCRATCH_GROUP_V1_REGMAP_TABLE_WITH_IMPL_DEF(tblName, 0) + +#define NV_CRASHCAT_DEF_SCRATCH_GROUP_V1_REGMAP_TABLE_WITH_IMPL_DEF(tblName, ...) \ + static const NvU32 tblName[][NV_CRASHCAT_SCRATCH_GROUP_V1_MAX_NUM_REGISTERS + 1] = { \ + [NV_CRASHCAT_SCRATCH_GROUP_ID_NONE] = {0}, \ + [NV_CRASHCAT_SCRATCH_GROUP_ID_A] = { \ + NV_PFALCON_FALCON_MAILBOX0, NV_PFALCON_FALCON_MAILBOX1, 0 }, \ + [NV_CRASHCAT_SCRATCH_GROUP_ID_B] = { \ + NV_PFALCON_FALCON_COMMON_SCRATCH_GROUP_0(0), \ + NV_PFALCON_FALCON_COMMON_SCRATCH_GROUP_0(1), \ + NV_PFALCON_FALCON_COMMON_SCRATCH_GROUP_0(2), \ + NV_PFALCON_FALCON_COMMON_SCRATCH_GROUP_0(3), 0}, \ + [NV_CRASHCAT_SCRATCH_GROUP_ID_C] = { \ + NV_PFALCON_FALCON_COMMON_SCRATCH_GROUP_1(0), \ + NV_PFALCON_FALCON_COMMON_SCRATCH_GROUP_1(1), \ + NV_PFALCON_FALCON_COMMON_SCRATCH_GROUP_1(2), \ + NV_PFALCON_FALCON_COMMON_SCRATCH_GROUP_1(3), 0}, \ + [NV_CRASHCAT_SCRATCH_GROUP_ID_D] = { \ + NV_PFALCON_FALCON_COMMON_SCRATCH_GROUP_2(0), \ + NV_PFALCON_FALCON_COMMON_SCRATCH_GROUP_2(1), \ + NV_PFALCON_FALCON_COMMON_SCRATCH_GROUP_2(2), \ + NV_PFALCON_FALCON_COMMON_SCRATCH_GROUP_2(3), 0}, \ + [NV_CRASHCAT_SCRATCH_GROUP_ID_E] = { \ + NV_PFALCON_FALCON_COMMON_SCRATCH_GROUP_3(0), \ + NV_PFALCON_FALCON_COMMON_SCRATCH_GROUP_3(1), \ + NV_PFALCON_FALCON_COMMON_SCRATCH_GROUP_3(2), \ + NV_PFALCON_FALCON_COMMON_SCRATCH_GROUP_3(3), 0}, \ + [NV_CRASHCAT_SCRATCH_GROUP_ID_F] = {0}, \ + [NV_CRASHCAT_SCRATCH_GROUP_ID_IMPL_DEF] = { __VA_ARGS__, 0 } \ + } + +// +// CrashCat Memory Aperture Identifier +// Each enum value represents a target aperture through which a CrashCat memory buffer can be +// accessed. +// +typedef enum { + NV_CRASHCAT_MEM_APERTURE_SYSGPA = 0x0, + NV_CRASHCAT_MEM_APERTURE_FBGPA = 0x1, + NV_CRASHCAT_MEM_APERTURE_DMEM = 0x2, + NV_CRASHCAT_MEM_APERTURE_EMEM = 0x3, + NV_CRASHCAT_MEM_APERTURE_LAST = 0x3, + NV_CRASHCAT_MEM_APERTURE_UNKNOWN = 0xFF, // Used for error checking/translation failures +} NV_CRASHCAT_MEM_APERTURE; + +// +// CrashCat Memory Unit Size +// Each enum value represents a fixed unit size for a corresponding size field. This is used to +// encode buffer sizes in compact register space. +// +typedef enum { + NV_CRASHCAT_MEM_UNIT_SIZE_8B = 0, // 8-byte units + NV_CRASHCAT_MEM_UNIT_SIZE_1KB = 1, // 1-kilobyte units + NV_CRASHCAT_MEM_UNIT_SIZE_4KB = 2, // 4-kilobyte units + NV_CRASHCAT_MEM_UNIT_SIZE_64KB = 3, // 64-kilobyte units + NV_CRASHCAT_MEM_UNIT_SIZE_LAST = 3, +} NV_CRASHCAT_MEM_UNIT_SIZE; + +// +// CrashCat Packet Type +// Encoded in the CrashCat packet header to indicate the format of the data. +// +typedef enum { + NV_CRASHCAT_PACKET_TYPE_REPORT = 0x00, // Base CrashCat report packet (required) + NV_CRASHCAT_PACKET_TYPE_RISCV64_CSR_STATE = 0x01, // Each 8-byte value is a RISC-V 64-bit CSR + NV_CRASHCAT_PACKET_TYPE_RISCV64_GPR_STATE = 0x02, // Each 8-byte value is a RISC-V 64-bit GPR + NV_CRASHCAT_PACKET_TYPE_RISCV64_TRACE = 0x03, // Each 8-byte value is a program counter/ + // virtual address from a RISC-V 64-bit trace + NV_CRASHCAT_PACKET_TYPE_IO32_STATE = 0x04, // Each 8-byte value is a 32-bit register + // address in the upper bytes combined with + // a 32-bit value in the lower bytes + NV_CRASHCAT_PACKET_TYPE_LAST = 0x04 +} NV_CRASHCAT_PACKET_TYPE; + +// +// CrashCat RISC-V Mode +// Indicates the execution mode of the Peregrine core. +// Note: this does not include all RISC-V standard modes, only the ones supported by NVRISC-V. +// +typedef enum { + NV_CRASHCAT_RISCV_MODE_UNSPECIFIED = 0x0, + NV_CRASHCAT_RISCV_MODE_M = 0x1, // Machine Mode + NV_CRASHCAT_RISCV_MODE_S = 0x2, // Supervisor Mode + NV_CRASHCAT_RISCV_MODE_U = 0x3, // User Mode + NV_CRASHCAT_RISCV_MODE_LAST = 0x3, +} NV_CRASHCAT_RISCV_MODE; + +// +// CrashCat Partition +// Represents a NVRISC-V microcode partition index +// +typedef NvU8 NvCrashCatNvriscvPartition; +#define NV_CRASHCAT_NVRISCV_PARTITION_UNSPECIFIED NV_U8_MAX + +// +// CrashCat Ucode ID +// Represents an NVRISC-V microcode ID +// +typedef NvU8 NvCrashCatNvriscvUcodeId; +#define NV_CRASHCAT_NVRISCV_UCODE_ID_UNSPECIFIED NV_U8_MAX + +// +// CrashCat Crash Cause Type +// Indicates the general nature of the crash cause. +// +typedef enum { + NV_CRASHCAT_CAUSE_TYPE_EXCEPTION = 0x0, // Crash observed via Peregrine trap (exception or + // unhandled interrupt) + NV_CRASHCAT_CAUSE_TYPE_TIMEOUT = 0x1, // Crash observed via timeout or hang condition + NV_CRASHCAT_CAUSE_TYPE_PANIC = 0x2, // Crash observed via direct panic condition + NV_CRASHCAT_CAUSE_TYPE_LAST = 0x2 +} NV_CRASHCAT_CAUSE_TYPE; + +// +// CrashCat I/O Aperture Identifier +// Indicates the Peregrine MMIO aperture through which register offsets are accessed. +// +typedef enum { + NV_CRASHCAT_IO_APERTURE_NONE = 0x00, // Register offsets are not relative + NV_CRASHCAT_IO_APERTURE_INTIO = 0x01, // Register offsets are relative to local I/O base + NV_CRASHCAT_IO_APERTURE_EXTIO = 0x02, // Register offsets are relative to external I/O base + NV_CRASHCAT_IO_APERTURE_LAST = 0x02 +} NV_CRASHCAT_IO_APERTURE; + +// +// CrashCat Trace Type +// Indicates the source of trace data (PC values) +// +typedef enum { + NV_CRASHCAT_TRACE_TYPE_STACK = 0x00, // The PC values are return addresses on a stack, walked + // by CrashCat implementation + NV_CRASHCAT_TRACE_TYPE_NVRVTB = 0x01, // The PC values are entries from the NVRISC-V PC trace + // buffer + NV_CRASHCAT_TRACE_TYPE_LAST = 0x01 +} NV_CRASHCAT_TRACE_TYPE; + +// +// CrashCat Wayfinder Protocol is a mechanism for locating crash-reports in a programmatic way, +// since available memory for reports may vary across different Peregrines. In V1, the wayfinder +// protocol uses a single common scratch register (level 0, A.K.A. WFL0) to point to a secondary +// group of scratch registers (level 1, A.K.A. WFL1), which point to the full crash report queue. +// The queue is implemented as a circular buffer with classic put/get semantics, controlled through +// the wayfinder L1 registers. +// +// Crash Report Wayfinder Level 0 (NV_CRASHCAT_WAYFINDER_L0) +// _SIGNATURE : Initialized to NV_CRASHCAT_SIGNATURE after the level 1 wayfinder is +// initialized. +// _VERSION : NV_CRASHCAT_WAYFINDER_VERSION value of the protocol implemented for the +// crash report wayfinder on this Peregrine (must be consistent with all +// implementers on a Peregrine). +// +// Version 1 Fields: +// _V1_WFL1_LOCATION : Contains an NV_CRASHCAT_SCRATCH_GROUP_ID identifying the registers +// containing the level 1 wayfinder +// _V1_RESERVED : Reserved for future use (currently 0). +// +typedef NvU32 NvCrashCatWayfinderL0_V1; +#define NV_CRASHCAT_WAYFINDER_L0_SIGNATURE 15:0 +#define NV_CRASHCAT_WAYFINDER_L0_SIGNATURE_VALID NV_CRASHCAT_SIGNATURE +#define NV_CRASHCAT_WAYFINDER_L0_VERSION 19:16 +#define NV_CRASHCAT_WAYFINDER_L0_VERSION_1 NV_CRASHCAT_WAYFINDER_VERSION_1 +#define NV_CRASHCAT_WAYFINDER_L0_V1_WFL1_LOCATION 22:20 +#define NV_CRASHCAT_WAYFINDER_L0_V1_WFL1_LOCATION_NONE NV_CRASHCAT_SCRATCH_GROUP_ID_NONE +#define NV_CRASHCAT_WAYFINDER_L0_V1_WFL1_LOCATION_A NV_CRASHCAT_SCRATCH_GROUP_ID_A +#define NV_CRASHCAT_WAYFINDER_L0_V1_WFL1_LOCATION_B NV_CRASHCAT_SCRATCH_GROUP_ID_B +#define NV_CRASHCAT_WAYFINDER_L0_V1_WFL1_LOCATION_C NV_CRASHCAT_SCRATCH_GROUP_ID_C +#define NV_CRASHCAT_WAYFINDER_L0_V1_WFL1_LOCATION_D NV_CRASHCAT_SCRATCH_GROUP_ID_D +#define NV_CRASHCAT_WAYFINDER_L0_V1_WFL1_LOCATION_E NV_CRASHCAT_SCRATCH_GROUP_ID_E +#define NV_CRASHCAT_WAYFINDER_L0_V1_WFL1_LOCATION_F NV_CRASHCAT_SCRATCH_GROUP_ID_F +#define NV_CRASHCAT_WAYFINDER_L0_V1_WFL1_LOCATION_IMPL_DEF NV_CRASHCAT_SCRATCH_GROUP_ID_IMPL_DEF +#define NV_CRASHCAT_WAYFINDER_L0_V1_RESERVED 31:23 + +STATIC_ASSERT_ENUM_FITS_IN_BITFIELD(NV_CRASHCAT_WAYFINDER_VERSION, + NV_CRASHCAT_WAYFINDER_L0_VERSION); +STATIC_ASSERT_ENUM_FITS_IN_BITFIELD(NV_CRASHCAT_SCRATCH_GROUP_ID, + NV_CRASHCAT_WAYFINDER_L0_V1_WFL1_LOCATION); + +// +// Crash Report Wayfinder Level 1 and Queue Control Notes +// Depending on how many scratch registers are in the set specified by the level 0 wayfinder, the +// registers used for the level 1 wayfinder may need to be reused for the queue control registers. +// +// The first two scratch registers in the set are used to compose the NvCrashCatWayfinderL1_V1 +// value, with the register with the lower address providing the bottom 32 bits and the register +// with the higher address providing the upper 32 bits. +// +// If four scratch registers are available, the last two are used for the queue put and get +// control, respectively. The producer implementation should ensure these are initialized to zero, +// and may update the put pointer without any synchronization with the consumer. +// +// If only two scratch registers are available, the WFL1 registers are reclaimed after they are +// decoded by the consumer and used for the queue put and get points. The producer must wait for +// the consumer to set the NV_CRASHCAT_WAYFINDER_L0_V1_WFL1_LOCATION bits of the level 0 wayfinder +// to _NONE before writing the put pointer. It is the responsibility of the consumer to clear the +// WFL1 registers before updating the level 0 wayfinder - after the producer sees the +// NV_CRASHCAT_WAYFINDER_L0_V1_WFL1_LOCATION change to _NONE, it may update the put pointer. +// +// CrashCat Wayfinder Locking Notes for Implementers +// Due to the multi-producer nature of the crash report buffer, accesses to the following registers +// must be synchronized when writing to avoid stomping other crash reports or otherwise corrupting +// the queue: +// - NV_CRASHCAT_WAYFINDER_L0 +// If the signature is already present when the reporter initializes, the reporter should panic +// if the wayfinder protocol version is not the same as what the reporter implements. +// Where possible, it is recommended to compile-time assert reporter version consistency. +// - NV_CRASHCAT_WAYFINDER_L1 +// Writes to these registers must be synchronized during initialization by the reporter, to +// ensure that only one chooses the value and writes it. If they are already initialized, the +// reporter should not need to update them, and should instead queue its crash reports in the +// buffer pointed to by these registers. +// - NV_CRASHCAT_QUEUE_PUT +// This register must be synchronized on during initialization and update by the reporter. The +// interface should be locked before the start of writing the crash report and released after +// this register is updated. +// - NV_CRASHCAT_QUEUE_GET +// The (single) consumer controls this register, so no explicit synchronization is needed. +// The implementation should initialize to 0 when the level 0 wayfinder is initialized, and not +// touch it afterward. +// +// If no preemption is possible, then it is sufficient for a producer to push packets into the +// queue one by one, and only update the put pointer once all packets from the report have been +// queued. If the producer can be preempted while queuing report packets, it must hold a lock +// synchronizing access to the CrashCat queue while it it pushes all report packets in the queue, +// to prevent potential interleaving with packets from other reports. +// +// It may be advantageous for the Peregrine FMC to receive the report queue location as a boot +// argument and initialize the wayfinders accordingly during boot, rather than when a crash is +// observed. +// + +// +// Crash Report Wayfinder Level 1 (NV_CRASHCAT_WAYFINDER_L1) V1 +// _QUEUE_APERTURE : NV_CRASHCAT_MEM_APERTURE value of the aperture through which the queue can +// be accessed +// _QUEUE_UNIT_SIZE : NV_CRASHCAT_MEM_UNIT_SIZE value indicating the units of the _SIZE field +// (1KB or greater) +// _RESERVED : Reserved for future use (currently 0) +// _QUEUE_SIZE : Size of the queue in _UNIT_SIZE minus 1 (_SIZE = 0 -> queue size is 1 unit) +// _QUEUE_OFFSET_1KB : 1KB-aligned offset of the start of the queue in _QUEUE_APERTURE +// +typedef NvU64 NvCrashCatWayfinderL1_V1; +#define NV_CRASHCAT_WAYFINDER_L1_V1_QUEUE_APERTURE 2:0 +#define NV_CRASHCAT_WAYFINDER_L1_V1_QUEUE_APERTURE_SYSGPA NV_CRASHCAT_MEM_APERTURE_SYSGPA +#define NV_CRASHCAT_WAYFINDER_L1_V1_QUEUE_APERTURE_FBGPA NV_CRASHCAT_MEM_APERTURE_FBGPA +#define NV_CRASHCAT_WAYFINDER_L1_V1_QUEUE_APERTURE_DMEM NV_CRASHCAT_MEM_APERTURE_DMEM +#define NV_CRASHCAT_WAYFINDER_L1_V1_QUEUE_APERTURE_EMEM NV_CRASHCAT_MEM_APERTURE_EMEM +#define NV_CRASHCAT_WAYFINDER_L1_V1_QUEUE_UNIT_SIZE 4:3 +#define NV_CRASHCAT_WAYFINDER_L1_V1_QUEUE_UNIT_SIZE_1KB NV_CRASHCAT_MEM_UNIT_SIZE_1KB +#define NV_CRASHCAT_WAYFINDER_L1_V1_QUEUE_UNIT_SIZE_4KB NV_CRASHCAT_MEM_UNIT_SIZE_4KB +#define NV_CRASHCAT_WAYFINDER_L1_V1_QUEUE_UNIT_SIZE_64KB NV_CRASHCAT_MEM_UNIT_SIZE_64KB +#define NV_CRASHCAT_WAYFINDER_L1_V1_QUEUE_RESERVED 5:5 +#define NV_CRASHCAT_WAYFINDER_L1_V1_QUEUE_SIZE 9:6 +#define NV_CRASHCAT_WAYFINDER_L1_V1_QUEUE_OFFSET_1KB 63:10 + +STATIC_ASSERT_ENUM_FITS_IN_BITFIELD(NV_CRASHCAT_MEM_APERTURE, + NV_CRASHCAT_WAYFINDER_L1_V1_QUEUE_APERTURE); +STATIC_ASSERT_ENUM_FITS_IN_BITFIELD(NV_CRASHCAT_MEM_UNIT_SIZE, + NV_CRASHCAT_WAYFINDER_L1_V1_QUEUE_UNIT_SIZE); + +// +// CrashCat Queue Put Pointer +// Offset in bytes into the CrashCat circular queue at which the next crash report will be written. +// Reports may wrap around the end of the buffer to the start. +// +// The implementation should only update the put pointer once all packets from the report have been +// queued. This simplifies the consumer implementation, as it can assume that the report is +// complete once the put pointer is updated. +// + +// +// CrashCat Queue Get Pointer +// Offset in bytes into the CrashCat circular queue at which the next crash report will be read by +// the consumer (when get is behind put). The consumer advances this pointer to allow queue memory +// to be reused by subsequent reports. +// + +static NV_INLINE NvU32 crashcatQueueFreeBytes(NvU32 put, NvU32 get, NvU32 size) +{ + return (put >= get) ? (size - (put - get)) : (get - put); +} + +static NV_INLINE NvU32 crashcatQueueBytesToRead(NvU32 put, NvU32 get, NvU32 size) +{ + return (put >= get) ? (put - get) : (size - (get - put)); +} + +// +// CrashCat Packet Header (NV_CRASHCAT_PACKET_HEADER) +// _SIGNATURE : NV_CRASHCAT_SIGNATURE value to indicate the start of a new data value +// _FORMAT_VERSION : NV_CRASHCAT_PACKET_FORMAT_VERSION value +// _PAYLOAD_UNIT_SIZE : NV_CRASHCAT_MEM_UNIT_SIZE value indicating the units of the +// _PAYLOAD_SIZE field +// _PAYLOAD_SIZE : Size of the packet payload (excluding header) in _PAYLOAD_UNIT_SIZE +// minus 1 (_PAYLOAD_SIZE = 0 -> payload size is 1 unit) +// _V1_TYPE : NV_CRASHCAT_PACKET_TYPE value +// _V1_META : Additional packet metadata bits specific to the packet type +// +typedef NvU64 NvCrashCatPacketHeader; +typedef NvU64 NvCrashCatPacketHeader_V1; +#define NV_CRASHCAT_PACKET_HEADER_SIGNATURE 15:0 +#define NV_CRASHCAT_PACKET_HEADER_SIGNATURE_VALID NV_CRASHCAT_SIGNATURE +#define NV_CRASHCAT_PACKET_HEADER_FORMAT_VERSION 19:16 +#define NV_CRASHCAT_PACKET_HEADER_FORMAT_VERSION_1 NV_CRASHCAT_PACKET_FORMAT_VERSION_1 +#define NV_CRASHCAT_PACKET_HEADER_PAYLOAD_UNIT_SIZE 21:20 +#define NV_CRASHCAT_PACKET_HEADER_PAYLOAD_UNIT_SIZE_8B NV_CRASHCAT_MEM_UNIT_SIZE_8B +#define NV_CRASHCAT_PACKET_HEADER_PAYLOAD_UNIT_SIZE_1KB NV_CRASHCAT_MEM_UNIT_SIZE_1KB +#define NV_CRASHCAT_PACKET_HEADER_PAYLOAD_UNIT_SIZE_4KB NV_CRASHCAT_MEM_UNIT_SIZE_4KB +#define NV_CRASHCAT_PACKET_HEADER_PAYLOAD_UNIT_SIZE_64PKB NV_CRASHCAT_MEM_UNIT_SIZE_64KB +#define NV_CRASHCAT_PACKET_HEADER_PAYLOAD_SIZE 31:22 +#define NV_CRASHCAT_PACKET_HEADER_V1_TYPE 39:32 +#define NV_CRASHCAT_PACKET_HEADER_V1_TYPE_REPORT NV_CRASHCAT_PACKET_TYPE_REPORT +#define NV_CRASHCAT_PACKET_HEADER_V1_TYPE_RISCV64_CSR_STATE \ + NV_CRASHCAT_PACKET_TYPE_RISCV64_CSR_STATE +#define NV_CRASHCAT_PACKET_HEADER_V1_TYPE_RISCV64_GPR_STATE \ + NV_CRASHCAT_PACKET_TYPE_RISCV64_GPR_STATE +#define NV_CRASHCAT_PACKET_HEADER_V1_TYPE_IO32_STATE NV_CRASHCAT_PACKET_TYPE_IO32_STATE +#define NV_CRASHCAT_PACKET_HEADER_V1_TYPE_RISCV64_TRACE NV_CRASHCAT_PACKET_TYPE_RISCV64_TRACE +#define NV_CRASHCAT_PACKET_HEADER_V1_META 63:40 + +STATIC_ASSERT_ENUM_FITS_IN_BITFIELD(NV_CRASHCAT_PACKET_FORMAT_VERSION, + NV_CRASHCAT_PACKET_HEADER_FORMAT_VERSION); +STATIC_ASSERT_ENUM_FITS_IN_BITFIELD(NV_CRASHCAT_MEM_UNIT_SIZE, + NV_CRASHCAT_PACKET_HEADER_PAYLOAD_UNIT_SIZE); +STATIC_ASSERT_ENUM_FITS_IN_BITFIELD(NV_CRASHCAT_PACKET_TYPE, + NV_CRASHCAT_PACKET_HEADER_V1_TYPE); + +// +// CrashCat Report (NV_CRASHCAT_PACKET_TYPE_REPORT) V1 +// A fixed-size packet including +// 8 bytes: packet header (see NV_CRASHCAT_PACKET_HEADER) +// 8 bytes: implementer signature +// 16 bytes: reporter information +// 32 bytes: crash source information +// +// A report packet sets the context for the remaining packets that come after it (until the next +// NV_CRASHCAT_PACKET_TYPE_REPORT packet). +// +typedef struct NvCrashCatReport_V1 { + // + // CrashCat Report V1 Header (NV_CRASHCAT_REPORT_V1_HEADER) + // _SIGNATURE : NV_CRASHCAT_SIGNATURE value to indicate the start of a new packet + // _FORMAT_VERSION : NV_CRASHCAT_PACKET_FORMAT_VERSION_1 + // _PAYLOAD_UNIT_SIZE : NV_CRASHCAT_PACKET_HEADER_PAYLOAD_UNIT_SIZE_8B + // _PAYLOAD_SIZE : 6 (56 bytes) + // _TYPE : NV_CRASHCAT_PACKET_TYPE_REPORT value + // _RESERVED : Reserved for future use (currently 0) + // + NvCrashCatPacketHeader_V1 header; + #define NV_CRASHCAT_REPORT_V1_HEADER_SIGNATURE \ + NV_CRASHCAT_PACKET_HEADER_SIGNATURE + #define NV_CRASHCAT_REPORT_V1_HEADER_SIGNATURE_VALID \ + NV_CRASHCAT_PACKET_HEADER_SIGNATURE_VALID + #define NV_CRASHCAT_REPORT_V1_HEADER_FORMAT_VERSION \ + NV_CRASHCAT_PACKET_HEADER_FORMAT_VERSION + #define NV_CRASHCAT_REPORT_V1_HEADER_FORMAT_VERSION_VALID \ + NV_CRASHCAT_PACKET_FORMAT_VERSION_1 + #define NV_CRASHCAT_REPORT_V1_HEADER_PAYLOAD_UNIT_SIZE \ + NV_CRASHCAT_PACKET_HEADER_PAYLOAD_UNIT_SIZE + #define NV_CRASHCAT_REPORT_V1_HEADER_PAYLOAD_UNIT_SIZE_VALID \ + NV_CRASHCAT_MEM_UNIT_SIZE_8B + #define NV_CRASHCAT_REPORT_V1_HEADER_PAYLOAD_SIZE \ + NV_CRASHCAT_PACKET_HEADER_PAYLOAD_SIZE + #define NV_CRASHCAT_REPORT_V1_HEADER_PAYLOAD_SIZE_VALID \ + (((sizeof(NvCrashCatReport_V1) - sizeof(NvCrashCatPacketHeader_V1)) >> 3) - 1) + #define NV_CRASHCAT_REPORT_V1_HEADER_PACKET_TYPE \ + NV_CRASHCAT_PACKET_HEADER_V1_TYPE + #define NV_CRASHCAT_REPORT_V1_HEADER_PACKET_TYPE_VALID \ + NV_CRASHCAT_PACKET_TYPE_REPORT + #define NV_CRASHCAT_REPORT_V1_HEADER_RESERVED 63:40 + + // + // CrashCat Report V1 Implementer Signature + // Provides a unique 64-bit identifier for the decoder to use to interpret the + // implementation-defined bits + // + NvU64 implementerSignature; + + // + // CrashCat Report V1 Reporter ID (NV_CRASHCAT_REPORT_V1_REPORTER_ID) + // _NVRISCV_PARTITION : Partition index of the crash reporter (depends on FMC configuration) + // _NVRISCV_UCODE_ID : Ucode ID of the crash reporter (read from the relevant curruid + // CSR/field) + // _RISCV_MODE : Current RISC-V mode of the crash reporter + // _IMPL_DEF : Implementation-defined identifier + // + NvU64 reporterId; + #define NV_CRASHCAT_REPORT_V1_REPORTER_ID_NVRISCV_PARTITION 7:0 + #define NV_CRASHCAT_REPORT_V1_REPORTER_ID_NVRISCV_PARTITION_UNSPECIFIED \ + NV_CRASHCAT_NVRISCV_PARTITION_UNSPECIFIED + #define NV_CRASHCAT_REPORT_V1_REPORTER_ID_NVRISCV_UCODE_ID 15:8 + #define NV_CRASHCAT_REPORT_V1_REPORTER_ID_NVRISCV_UCODE_ID_UNSPECIFIED \ + NV_CRASHCAT_NVRISCV_UCODE_ID_UNSPECIFIED + #define NV_CRASHCAT_REPORT_V1_REPORTER_ID_RISCV_MODE 18:16 + #define NV_CRASHCAT_REPORT_V1_REPORTER_ID_RISCV_MODE_M \ + NV_CRASHCAT_RISCV_MODE_M + #define NV_CRASHCAT_REPORT_V1_REPORTER_ID_RISCV_MODE_S \ + NV_CRASHCAT_RISCV_MODE_S + #define NV_CRASHCAT_REPORT_V1_REPORTER_ID_RISCV_MODE_U \ + NV_CRASHCAT_RISCV_MODE_U + #define NV_CRASHCAT_REPORT_V1_REPORTER_ID_RISCV_MODE_UNSPECIFIED \ + NV_CRASHCAT_RISCV_MODE_UNSPECIFIED + #define NV_CRASHCAT_REPORT_V1_REPORTER_ID_RESERVED 23:19 + #define NV_CRASHCAT_REPORT_V1_REPORTER_ID_IMPL_DEF 63:24 + + // + // CrashCat Report V1 Reporter Data (NV_CRASHCAT_REPORT_V1_REPORTER_DATA) + // _VERSION : Implementation-defined version identifier (recommend CL number) + // _TIMESTAMP : Seconds since epoch (Jan 1, 1970) or cold reset of when the crash report was + // generated. Since this value is read from a local clock source, the consumer + // is responsible for adjusting this value to a relevant reference point. + // + NvU64 reporterData; + #define NV_CRASHCAT_REPORT_V1_REPORTER_DATA_VERSION 31:0 + #define NV_CRASHCAT_REPORT_V1_REPORTER_DATA_TIMESTAMP 63:32 + + // + // CrashCat Report V1 Source ID (NV_CRASHCAT_REPORT_V1_SOURCE_ID) + // _NVRISCV_PARTITION : Partition ID of the crashing code (depends on FMC configuration) + // _NVRISCV_UCODE_ID : Ucode ID of the crashing code (read from the relevant curruid + // CSR/field) + // _RISCV_MODE : RISC-V mode of the crashing code + // _IMPL_DEF : Implementation-defined identifier + // + NvU64 sourceId; + #define NV_CRASHCAT_REPORT_V1_SOURCE_ID_NVRISCV_PARTITION 7:0 + #define NV_CRASHCAT_REPORT_V1_SOURCE_ID_NVRISCV_PARTITION_UNSPECIFIED \ + NV_CRASHCAT_NVRISCV_PARTITION_UNSPECIFIED + #define NV_CRASHCAT_REPORT_V1_SOURCE_ID_NVRISCV_UCODE_ID 15:8 + #define NV_CRASHCAT_REPORT_V1_SOURCE_ID_NVRISCV_UCODE_ID_UNSPECIFIED \ + NV_CRASHCAT_NVRISCV_UCODE_ID_UNSPECIFIED + #define NV_CRASHCAT_REPORT_V1_SOURCE_ID_RISCV_MODE 18:16 + #define NV_CRASHCAT_REPORT_V1_SOURCE_ID_RISCV_MODE_M NV_CRASHCAT_RISCV_MODE_M + #define NV_CRASHCAT_REPORT_V1_SOURCE_ID_RISCV_MODE_S NV_CRASHCAT_RISCV_MODE_S + #define NV_CRASHCAT_REPORT_V1_SOURCE_ID_RISCV_MODE_U NV_CRASHCAT_RISCV_MODE_U + #define NV_CRASHCAT_REPORT_V1_SOURCE_ID_RISCV_MODE_UNSPECIFIED \ + NV_CRASHCAT_RISCV_MODE_UNSPECIFIED + #define NV_CRASHCAT_REPORT_V1_SOURCE_ID_RESERVED 23:19 + #define NV_CRASHCAT_REPORT_V1_SOURCE_ID_IMPL_DEF 63:24 + + // + // CrashCat Report V1 Source Cause (NV_CRASHCAT_REPORT_V1_SOURCE_CAUSE) + // _TYPE : CrashCat general failure type for the crash (i.e., how the crash was observed) + // _RESERVED: Reserved for future use (currently 0) + // _IMPL_DEF: Implementation-defined reason code for the crash + // + NvU64 sourceCause; + #define NV_CRASHCAT_REPORT_V1_SOURCE_CAUSE_TYPE 3:0 + #define NV_CRASHCAT_REPORT_V1_SOURCE_CAUSE_TYPE_EXCEPTION NV_CRASHCAT_CAUSE_TYPE_EXCEPTION + #define NV_CRASHCAT_REPORT_V1_SOURCE_CAUSE_TYPE_TIMEOUT NV_CRASHCAT_CAUSE_TYPE_TIMEOUT + #define NV_CRASHCAT_REPORT_V1_SOURCE_CAUSE_TYPE_PANIC NV_CRASHCAT_CAUSE_TYPE_PANIC + #define NV_CRASHCAT_REPORT_V1_SOURCE_CAUSE_RESERVED 31:4 + #define NV_CRASHCAT_REPORT_V1_SOURCE_CAUSE_IMPL_DEF 63:32 + + // + // CrashCat Report V1 Source PC + // Program counter of the instruction where the crash occurred + // + NvU64 sourcePc; + + // + // CrashCat Report V1 Source Data + // Additional crash source data (implementation-defined) + // + NvU64 sourceData; +} NvCrashCatReport_V1; + +STATIC_ASSERT_ENUM_FITS_IN_BITFIELD(NV_CRASHCAT_RISCV_MODE, + NV_CRASHCAT_REPORT_V1_REPORTER_ID_RISCV_MODE); +STATIC_ASSERT_ENUM_FITS_IN_BITFIELD(NV_CRASHCAT_RISCV_MODE, + NV_CRASHCAT_REPORT_V1_SOURCE_ID_RISCV_MODE); +STATIC_ASSERT_ENUM_FITS_IN_BITFIELD(NV_CRASHCAT_CAUSE_TYPE, + NV_CRASHCAT_REPORT_V1_SOURCE_CAUSE_TYPE); + +// +// CrashCat RISC-V CSR State (NV_CRASHCAT_PACKET_TYPE_RISCV64_CSR_STATE) V1 +// A fixed-size packet containing values for RISC-V Control and Status Registers (CSRs) that are +// commonly relevant in debugging crashes. +// +// Note: all CSRs in this structure must be defined in the standard RISC-V specification. +// Do not add NVRISC-V-specific CSRs to this packet. +// +typedef struct NvCrashCatRiscv64CsrState_V1 { + // + // CrashCat RISC-V CSR State Header (NV_CRASHCAT_RISCV64_CSR_STATE_V1_HEADER) + // _SIGNATURE : NV_CRASHCAT_SIGNATURE value to indicate the start of a new packet + // _FORMAT_VERSION : NV_CRASHCAT_PACKET_FORMAT_VERSION_1 + // _PAYLOAD_UNIT_SIZE : NV_CRASHCAT_PACKET_HEADER_PAYLOAD_UNIT_SIZE_8B + // _PAYLOAD_SIZE : 6 (56 bytes) + // _TYPE : NV_CRASHCAT_PACKET_TYPE_RISCV64_CSR_STATE + // _RISCV_MODE : NV_CRASHCAT_RISCV_MODE that indicates the RISC-V mode in which the + // CSR values are captured from + // _RESERVED : Reserved for future use (currently 0) + // + NvCrashCatPacketHeader_V1 header; + #define NV_CRASHCAT_RISCV64_CSR_STATE_V1_HEADER_SIGNATURE \ + NV_CRASHCAT_PACKET_HEADER_SIGNATURE + #define NV_CRASHCAT_RISCV64_CSR_STATE_V1_HEADER_SIGNATURE_VALID \ + NV_CRASHCAT_PACKET_HEADER_SIGNATURE_VALID + #define NV_CRASHCAT_RISCV64_CSR_STATE_V1_HEADER_FORMAT_VERSION \ + NV_CRASHCAT_PACKET_HEADER_FORMAT_VERSION + #define NV_CRASHCAT_RISCV64_CSR_STATE_V1_HEADER_FORMAT_VERSION_VALID \ + NV_CRASHCAT_PACKET_FORMAT_VERSION_1 + #define NV_CRASHCAT_RISCV64_CSR_STATE_V1_HEADER_PAYLOAD_UNIT_SIZE \ + NV_CRASHCAT_PACKET_HEADER_PAYLOAD_UNIT_SIZE + #define NV_CRASHCAT_RISCV64_CSR_STATE_V1_HEADER_PAYLOAD_UNIT_SIZE_VALID \ + NV_CRASHCAT_MEM_UNIT_SIZE_8B + #define NV_CRASHCAT_RISCV64_CSR_STATE_V1_HEADER_PAYLOAD_SIZE \ + NV_CRASHCAT_PACKET_HEADER_PAYLOAD_SIZE + #define NV_CRASHCAT_RISCV64_CSR_STATE_V1_HEADER_PAYLOAD_SIZE_VALID \ + (((sizeof(NvCrashCatRiscv64CsrState_V1) - sizeof(NvCrashCatPacketHeader_V1)) >> 3) \ + - 1) + #define NV_CRASHCAT_RISCV64_CSR_STATE_V1_HEADER_PACKET_TYPE \ + NV_CRASHCAT_PACKET_HEADER_V1_TYPE + #define NV_CRASHCAT_RISCV64_CSR_STATE_V1_HEADER_PACKET_TYPE_VALID \ + NV_CRASHCAT_PACKET_TYPE_RISCV64_CSR_STATE + #define NV_CRASHCAT_RISCV64_CSR_STATE_V1_HEADER_RISCV_MODE 42:40 + #define NV_CRASHCAT_RISCV64_CSR_STATE_V1_HEADER_RISCV_MODE_M NV_CRASHCAT_RISCV_MODE_M + #define NV_CRASHCAT_RISCV64_CSR_STATE_V1_HEADER_RISCV_MODE_S NV_CRASHCAT_RISCV_MODE_S + #define NV_CRASHCAT_RISCV64_CSR_STATE_V1_HEADER_RISCV_MODE_U NV_CRASHCAT_RISCV_MODE_U + #define NV_CRASHCAT_RISCV64_CSR_STATE_V1_HEADER_RISCV_MODE_UNSPECIFIED \ + NV_CRASHCAT_RISCV_MODE_UNSPECIFIED + #define NV_CRASHCAT_RISCV64_CSR_STATE_V1_HEADER_RESERVED 63:43 + + NvU64 xstatus; // mstatus or sstatus + NvU64 xie; // mie or sie + NvU64 xip; // mip or sip + NvU64 xepc; // mepc or sepc + NvU64 xtval; // mbadaddr, mtval or stval + NvU64 xcause; // mcause or scause + NvU64 xscratch; // mscratch or sscratch +} NvCrashCatRiscv64CsrState_V1; + +STATIC_ASSERT_ENUM_FITS_IN_BITFIELD(NV_CRASHCAT_RISCV_MODE, + NV_CRASHCAT_RISCV64_CSR_STATE_V1_HEADER_RISCV_MODE); + +// +// CrashCat RISC-V GPR State (NV_CRASHCAT_PACKET_TYPE_RISCV64_GPR_STATE) V1 +// A fixed-size packet containing values for RISC-V general purpose registers (GPRs). +// +// These are defined to match the RISC-V standard calling convention for x1-x31. +// x0 is hardwired to 0, so we don't include it in dumps, and the packet header takes its place. +// +typedef struct NvCrashCatRiscv64GprState_V1 { + // + // CrashCat RISC-V GPR State Header (NV_CRASHCAT_RISCV64_GPR_STATE_V1_HEADER) + // _SIGNATURE : NV_CRASHCAT_SIGNATURE value to indicate the start of a new packet + // _FORMAT_VERSION : NV_CRASHCAT_PACKET_FORMAT_VERSION_1 + // _PAYLOAD_UNIT_SIZE : NV_CRASHCAT_PACKET_HEADER_PAYLOAD_UNIT_SIZE_8B + // _PAYLOAD_SIZE : 30 (188 bytes) + // _TYPE : NV_CRASHCAT_PACKET_TYPE_RISCV64_GPR_STATE + // _RESERVED : Reserved for future use (currently 0) + // + NvCrashCatPacketHeader_V1 header; + #define NV_CRASHCAT_RISCV64_GPR_STATE_V1_HEADER_SIGNATURE \ + NV_CRASHCAT_PACKET_HEADER_SIGNATURE + #define NV_CRASHCAT_RISCV64_GPR_STATE_V1_HEADER_SIGNATURE_VALID \ + NV_CRASHCAT_PACKET_HEADER_SIGNATURE_VALID + #define NV_CRASHCAT_RISCV64_GPR_STATE_V1_HEADER_FORMAT_VERSION \ + NV_CRASHCAT_PACKET_HEADER_FORMAT_VERSION + #define NV_CRASHCAT_RISCV64_GPR_STATE_V1_HEADER_FORMAT_VERSION_VALID \ + NV_CRASHCAT_PACKET_FORMAT_VERSION_1 + #define NV_CRASHCAT_RISCV64_GPR_STATE_V1_HEADER_PAYLOAD_UNIT_SIZE \ + NV_CRASHCAT_PACKET_HEADER_PAYLOAD_UNIT_SIZE + #define NV_CRASHCAT_RISCV64_GPR_STATE_V1_HEADER_PAYLOAD_UNIT_SIZE_VALID \ + NV_CRASHCAT_MEM_UNIT_SIZE_8B + #define NV_CRASHCAT_RISCV64_GPR_STATE_V1_HEADER_PAYLOAD_SIZE \ + NV_CRASHCAT_PACKET_HEADER_PAYLOAD_SIZE + #define NV_CRASHCAT_RISCV64_GPR_STATE_V1_HEADER_PAYLOAD_SIZE_VALID \ + (((sizeof(NvCrashCatRiscv64GprState_V1) - sizeof(NvCrashCatPacketHeader_V1)) >> 3) \ + - 1) + #define NV_CRASHCAT_RISCV64_GPR_STATE_V1_HEADER_PACKET_TYPE \ + NV_CRASHCAT_PACKET_HEADER_V1_TYPE + #define NV_CRASHCAT_RISCV64_GPR_STATE_V1_HEADER_PACKET_TYPE_VALID \ + NV_CRASHCAT_PACKET_TYPE_RISCV64_GPR_STATE + #define NV_CRASHCAT_RISCV64_GPR_STATE_V1_HEADER_RISCV_MODE 42:40 + #define NV_CRASHCAT_RISCV64_GPR_STATE_V1_HEADER_RISCV_MODE_M NV_CRASHCAT_RISCV_MODE_M + #define NV_CRASHCAT_RISCV64_GPR_STATE_V1_HEADER_RISCV_MODE_S NV_CRASHCAT_RISCV_MODE_S + #define NV_CRASHCAT_RISCV64_GPR_STATE_V1_HEADER_RISCV_MODE_U NV_CRASHCAT_RISCV_MODE_U + #define NV_CRASHCAT_RISCV64_GPR_STATE_V1_HEADER_RISCV_MODE_UNSPECIFIED \ + NV_CRASHCAT_RISCV_MODE_UNSPECIFIED + #define NV_CRASHCAT_RISCV64_GPR_STATE_V1_HEADER_RESERVED 63:40 + + NvU64 ra; // Return address + NvU64 sp; // Stack pointer + NvU64 gp; // Global pointer + NvU64 tp; // Thread pointer + NvU64 t0; // Temporary register 0 + NvU64 t1; // Temporary register 1 + NvU64 t2; // Temporary register 2 + NvU64 s0; // Saved register 0 + NvU64 s1; // Saved register 1 + NvU64 a0; // Argument/return value register 0 + NvU64 a1; // Argument/return value register 1 + NvU64 a2; // Argument register 2 + NvU64 a3; // Argument register 3 + NvU64 a4; // Argument register 4 + NvU64 a5; // Argument register 5 + NvU64 a6; // Argument register 6 + NvU64 a7; // Argument register 7 + NvU64 s2; // Saved register 2 + NvU64 s3; // Saved register 3 + NvU64 s4; // Saved register 4 + NvU64 s5; // Saved register 5 + NvU64 s6; // Saved register 6 + NvU64 s7; // Saved register 7 + NvU64 s8; // Saved register 8 + NvU64 s9; // Saved register 9 + NvU64 s10; // Saved register 10 + NvU64 s11; // Saved register 11 + NvU64 t3; // Temporary register 3 + NvU64 t4; // Temporary register 4 + NvU64 t5; // Temporary register 5 + NvU64 t6; // Temporary register 6 +} NvCrashCatRiscv64GprState_V1; + +STATIC_ASSERT_ENUM_FITS_IN_BITFIELD(NV_CRASHCAT_RISCV_MODE, + NV_CRASHCAT_RISCV64_GPR_STATE_V1_HEADER_RISCV_MODE); + +// +// CrashCat Trace (NV_CRASHCAT_PACKET_TYPE_RISCV64_TRACE) V1 +// A variable-size packet in which each 64-bit payload value is a virtual address from a trace +// (such as from a stack or PC trace buffer). The packet header metadata includes details to help +// differentiate types of traces. +// +typedef struct NvCrashCatRiscv64Trace_V1 { + // + // CrashCat Stack Trace Header (NV_CRASHCAT_RISCV64_TRACE_V1_HEADER) + // _SIGNATURE : NV_CRASHCAT_SIGNATURE value to indicate the start of a new packet + // _FORMAT_VERSION : NV_CRASHCAT_PACKET_FORMAT_VERSION_1 + // _PAYLOAD_UNIT_SIZE : NV_CRASHCAT_PACKET_HEADER_PAYLOAD_UNIT_SIZE_8B + // _PAYLOAD_SIZE : Variable + // _TYPE : NV_CRASHCAT_PACKET_TYPE_RISCV64_TRACE + // _RISCV_MODE : The NV_CRASHCAT_RISCV_MODE context of the trace (e.g., the RISC-V + // mode in which the trace addresses are relevant in) + // _RESERVED : Reserved for future use (currently 0) + // + NvCrashCatPacketHeader_V1 header; + #define NV_CRASHCAT_RISCV64_TRACE_V1_HEADER_SIGNATURE \ + NV_CRASHCAT_PACKET_HEADER_SIGNATURE + #define NV_CRASHCAT_RISCV64_TRACE_V1_HEADER_SIGNATURE_VALID \ + NV_CRASHCAT_PACKET_HEADER_SIGNATURE_VALID + #define NV_CRASHCAT_RISCV64_TRACE_V1_HEADER_FORMAT_VERSION \ + NV_CRASHCAT_PACKET_HEADER_FORMAT_VERSION + #define NV_CRASHCAT_RISCV64_TRACE_V1_HEADER_FORMAT_VERSION_VALID \ + NV_CRASHCAT_PACKET_FORMAT_VERSION_1 + #define NV_CRASHCAT_RISCV64_TRACE_V1_HEADER_PAYLOAD_UNIT_SIZE \ + NV_CRASHCAT_PACKET_HEADER_PAYLOAD_UNIT_SIZE + #define NV_CRASHCAT_RISCV64_TRACE_V1_HEADER_PAYLOAD_SIZE \ + NV_CRASHCAT_PACKET_HEADER_PAYLOAD_SIZE + #define NV_CRASHCAT_RISCV64_TRACE_V1_HEADER_PACKET_TYPE \ + NV_CRASHCAT_PACKET_HEADER_V1_TYPE + #define NV_CRASHCAT_RISCV64_TRACE_V1_HEADER_PACKET_TYPE_VALID \ + NV_CRASHCAT_PACKET_TYPE_RISCV64_TRACE + #define NV_CRASHCAT_RISCV64_TRACE_V1_HEADER_RISCV_MODE 42:40 + #define NV_CRASHCAT_RISCV64_TRACE_V1_HEADER_RISCV_MODE_M NV_CRASHCAT_RISCV_MODE_M + #define NV_CRASHCAT_RISCV64_TRACE_V1_HEADER_RISCV_MODE_S NV_CRASHCAT_RISCV_MODE_S + #define NV_CRASHCAT_RISCV64_TRACE_V1_HEADER_RISCV_MODE_U NV_CRASHCAT_RISCV_MODE_U + #define NV_CRASHCAT_RISCV64_TRACE_V1_HEADER_RISCV_MODE_UNSPECIFIED \ + NV_CRASHCAT_RISCV_MODE_UNSPECIFIED + #define NV_CRASHCAT_RISCV64_TRACE_V1_HEADER_TRACE_TYPE 43:43 + #define NV_CRASHCAT_RISCV64_TRACE_V1_HEADER_TRACE_TYPE_STACK NV_CRASHCAT_TRACE_TYPE_STACK + #define NV_CRASHCAT_RISCV64_TRACE_V1_HEADER_TRACE_TYPE_NVRVTB NV_CRASHCAT_TRACE_TYPE_NVRVTB + #define NV_CRASHCAT_RISCV64_TRACE_V1_HEADER_RESERVED 63:44 + + NvU64 addr[]; +} NvCrashCatRiscv64Trace_V1; + +STATIC_ASSERT_ENUM_FITS_IN_BITFIELD(NV_CRASHCAT_RISCV_MODE, + NV_CRASHCAT_RISCV64_TRACE_V1_HEADER_RISCV_MODE); + +// +// CrashCat 32-bit I/O State (NV_CRASHCAT_PACKET_TYPE_IO32_STATE) V1 +// A variable-size packet in which a 32-bit address and a 32-bit value are encoded into each 64-bit +// payload value. +// +typedef struct NvCrashCatIo32State_V1 { + // + // CrashCat 32-bit I/O Trace Header (NV_CRASHCAT_IO32_STATE_V1_HEADER) + // _SIGNATURE : NV_CRASHCAT_SIGNATURE value to indicate the start of a new packet + // _FORMAT_VERSION : NV_CRASHCAT_PACKET_FORMAT_VERSION_1 + // _PAYLOAD_UNIT_SIZE : NV_CRASHCAT_PACKET_HEADER_PAYLOAD_UNIT_SIZE_8B + // _PAYLOAD_SIZE : Variable + // _TYPE : NV_CRASHCAT_PACKET_TYPE_IO32_STATE + // _APERTURE : NV_CRASHCAT_IO_APERTURE value identifying the aperture that the + // offset is relative to + // _RESERVED : Reserved for future use (currently 0) + // + NvCrashCatPacketHeader_V1 header; + #define NV_CRASHCAT_IO32_STATE_V1_HEADER_SIGNATURE \ + NV_CRASHCAT_PACKET_HEADER_SIGNATURE + #define NV_CRASHCAT_IO32_STATE_V1_HEADER_SIGNATURE_VALID \ + NV_CRASHCAT_PACKET_HEADER_SIGNATURE_VALID + #define NV_CRASHCAT_IO32_STATE_V1_HEADER_FORMAT_VERSION \ + NV_CRASHCAT_PACKET_HEADER_FORMAT_VERSION + #define NV_CRASHCAT_IO32_STATE_V1_HEADER_FORMAT_VERSION_VALID \ + NV_CRASHCAT_PACKET_FORMAT_VERSION_1 + #define NV_CRASHCAT_IO32_STATE_V1_HEADER_PAYLOAD_UNIT_SIZE \ + NV_CRASHCAT_PACKET_HEADER_PAYLOAD_UNIT_SIZE + #define NV_CRASHCAT_IO32_STATE_V1_HEADER_PAYLOAD_SIZE \ + NV_CRASHCAT_PACKET_HEADER_PAYLOAD_SIZE + #define NV_CRASHCAT_IO32_STATE_V1_HEADER_PACKET_TYPE \ + NV_CRASHCAT_PACKET_HEADER_V1_TYPE + #define NV_CRASHCAT_IO32_STATE_V1_HEADER_PACKET_TYPE_VALID \ + NV_CRASHCAT_PACKET_TYPE_IO32_STATE + #define NV_CRASHCAT_IO32_STATE_V1_HEADER_APERTURE 41:40 + #define NV_CRASHCAT_IO32_STATE_V1_HEADER_APERTURE_NONE NV_CRASHCAT_IO_APERTURE_NONE + #define NV_CRASHCAT_IO32_STATE_V1_HEADER_APERTURE_INTIO NV_CRASHCAT_IO_APERTURE_INTIO + #define NV_CRASHCAT_IO32_STATE_V1_HEADER_APERTURE_EXTIO NV_CRASHCAT_IO_APERTURE_EXTIO + #define NV_CRASHCAT_IO32_STATE_V1_HEADER_RESERVED 63:42 + + struct { + NvU32 value; + NvU32 offset; + } regs[]; +} NvCrashCatIo32State_V1; + +STATIC_ASSERT_ENUM_FITS_IN_BITFIELD(NV_CRASHCAT_IO_APERTURE, + NV_CRASHCAT_IO32_STATE_V1_HEADER_APERTURE); + +#endif // NV_CRASHCAT_H diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/common/uproc/os/libos-v3.1.0/lib/libdwarf.c nvidia-open-gpu-kernel-modules-535.161.08/src/common/uproc/os/libos-v3.1.0/lib/libdwarf.c --- nvidia-open-gpu-kernel-modules-525.147.05/src/common/uproc/os/libos-v3.1.0/lib/libdwarf.c 2023-10-25 20:22:29.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/common/uproc/os/libos-v3.1.0/lib/libdwarf.c 2024-03-05 22:15:25.000000000 +0000 @@ -755,11 +755,10 @@ DwarfStream debugLines = {pThis->debugLineStart, 0, pThis->debugLineEnd - pThis->debugLineStart}; DwarfStream unit; - NvU32 currentUnit = 1; NvU32 unitSize; // Run through the .debug_line elf section to match units to the arange table. - for (currentUnit = 1;; currentUnit++) + while (NV_TRUE) { if (!DWARF_READ(&debugLines, &unitSize) || unitSize >= 0xfffffff0) { @@ -829,11 +828,10 @@ // Pad to natural alignment unit.offset = (unit.offset + 15) & ~15; - NvU32 nUnitTupples; NvU64 combAddress = 0; NvU64 combLength = 0; - for (nUnitTupples = 0;; nUnitTupples++) + while (NV_TRUE) { NvU64 address; NvU64 length; @@ -918,7 +916,7 @@ } // Walk forwards setting the line unit info for all entries with the same arange unit. - for (; (foundUnit == pThis->arangeTable[i].arangeUnit); i++) + for (; foundUnit == pThis->arangeTable[i].arangeUnit; i++) { pThis->arangeTable[i].lineUnitBuffer = unit.buffer; pThis->arangeTable[i].lineUnitSize = unit.size; diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/common/uproc/os/libos-v3.1.0/lib/liblogdecode.c nvidia-open-gpu-kernel-modules-535.161.08/src/common/uproc/os/libos-v3.1.0/lib/liblogdecode.c --- nvidia-open-gpu-kernel-modules-525.147.05/src/common/uproc/os/libos-v3.1.0/lib/liblogdecode.c 2023-10-25 20:22:29.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/common/uproc/os/libos-v3.1.0/lib/liblogdecode.c 2024-03-05 22:15:25.000000000 +0000 @@ -34,6 +34,10 @@ #else // NVRM +#if defined(NVSYM_STANDALONE) +#include "time.h" +#endif + # include # include # include @@ -66,6 +70,8 @@ #endif // NVRM +#include + #include "nvtypes.h" #include "liblogdecode.h" @@ -471,10 +477,10 @@ # if defined(NVRM) if (logDecode->curLineBufPtr == logDecode->lineBuffer) { - // Prefix every line with NVRM GPUn Ucode-task: filename(lineNumber): + // Prefix every line with NVRM: GPUn Ucode-task: filename(lineNumber): snprintf( logDecode->curLineBufPtr, LIBOS_LOG_LINE_BUFFER_SIZE - 1, - "NVRM GPU%u %s-%s: %s(%u): ", pRec->log->gpuInstance, + NV_PRINTF_ADD_PREFIX("GPU%u %s-%s: %s(%u): "), pRec->log->gpuInstance, logDecode->sourceName, pRec->log->taskPrefix, filename, pRec->meta->lineNumber); logDecode->curLineBufPtr += portStringLength(logDecode->curLineBufPtr); } @@ -484,7 +490,39 @@ // Prefix every line with GPUn Ucode-task: filename(lineNumber): snprintf( logDecode->curLineBufPtr, LIBOS_LOG_LINE_BUFFER_SIZE - 1, - "T:%llu GPU%u %s-%s: %s(%u): ", pRec->timeStamp, + "T:%llu ", pRec->timeStamp); + logDecode->curLineBufPtr += portStringLength(logDecode->curLineBufPtr); + +#if defined(NVSYM_STANDALONE) + { + struct tm tmStruct; + // Libos timestamp is a PTIMER value, which is UNIX time in ns + time_t timeSec = pRec->timeStamp / 1000000000; +#if NVOS_IS_WINDOWS + // "The implementation of localtime_s in Microsoft CRT is incompatible with the + // C standard since it has reversed parameter order and returns errno_t." + errno_t err = localtime_s(&tmStruct, &timeSec); +#else + int err = (localtime_r(&timeSec, &tmStruct) == NULL); +#endif + if (err == 0) + { + snprintf(logDecode->curLineBufPtr, LIBOS_LOG_LINE_BUFFER_SIZE - 1, + "%04d-%02d-%02d %d:%02d:%02d ", + tmStruct.tm_year + 1900, // years since 1900 + tmStruct.tm_mon + 1, // months since January - [0,11] + tmStruct.tm_mday, // day of the month - [1,31] + tmStruct.tm_hour, // hours since midnight - [0,23] + tmStruct.tm_min, // minutes after the hour - [0,59] + tmStruct.tm_sec); // seconds after the minute - [0,59] + logDecode->curLineBufPtr += portStringLength(logDecode->curLineBufPtr); + } + } +#endif + + snprintf( + logDecode->curLineBufPtr, LIBOS_LOG_LINE_BUFFER_SIZE - 1, + "GPU%u %s-%s: %s(%u): ", pRec->log->gpuInstance, logDecode->sourceName, pRec->log->taskPrefix, filename, pRec->meta->lineNumber); logDecode->curLineBufPtr += portStringLength(logDecode->curLineBufPtr); @@ -1068,10 +1106,14 @@ // Copy records with highest timestamp. recSize = pLog->record.meta->argumentCount + LIBOS_LOG_DECODE_RECORD_BASE; + // // Skip duplicate records. The same record can be in both wrap and nowrap buffers. + // memcmp LIBOS_LOG_DECODE_RECORD + args starting at LIBOS_LOG_DECODE_RECORD::meta. + // + NvU64 compareSz = recSize - offsetof(LIBOS_LOG_DECODE_RECORD, meta) / sizeof(NvU64); if ((pPrevRec == NULL) || (pPrevRec->log->gpuInstance != pLog->gpuInstance) || - (portMemCmp(&pPrevRec->meta, &pLog->record.meta, (recSize - 1) * sizeof(NvU64)) != 0)) + (portMemCmp(&pPrevRec->meta, &pLog->record.meta, sizeof(NvU64) * compareSz) != 0)) { // Record is not identical to previous record. if (dst < recSize) diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/Makefile nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/Makefile --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/Makefile 2023-10-25 20:22:29.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/Makefile 2024-03-05 22:15:25.000000000 +0000 @@ -59,10 +59,23 @@ CFLAGS += -I src/libraries CFLAGS += -I inc/kernel +# Libspdm source requires additional include paths and build flags. +include src/libraries/libspdm/nvidia/openspdm.mk +$(call BUILD_OBJECT_LIST,$(LIBSPDM_SOURCES)): CFLAGS += $(addprefix -I ,$(LIBSPDM_INCLUDES)) +$(call BUILD_OBJECT_LIST,$(LIBSPDM_SOURCES)): CFLAGS += $(addprefix -D,$(LIBSPDM_DEFINES)) + +#if NV_USE_MBEDTLS +CFLAGS += -I $(SRC_COMMON)/mbedtls/include +CFLAGS += -I $(SRC_COMMON)/mbedtls/nvidia +CFLAGS += -DMBEDTLS_USER_CONFIG_FILE=\"nvrm_mbedtls_config.h\" +#endif + CFLAGS += -Werror-implicit-function-declaration CFLAGS += -Wwrite-strings +CFLAGS += -Wundef CFLAGS += -fno-common CFLAGS += -ffreestanding +CFLAGS += -fno-stack-protector ifeq ($(TARGET_ARCH),x86_64) CFLAGS += -msoft-float diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/arch/nvalloc/common/inc/conf_compute/cc_keystore.h nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/arch/nvalloc/common/inc/conf_compute/cc_keystore.h --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/arch/nvalloc/common/inc/conf_compute/cc_keystore.h 1970-01-01 00:00:00.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/arch/nvalloc/common/inc/conf_compute/cc_keystore.h 2024-03-05 22:12:42.000000000 +0000 @@ -0,0 +1,293 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef CC_KEYSTORE_H +#define CC_KEYSTORE_H + +// +// Keys are typically grouped in two's so that the first key is used for CPU-to-GPU encryption +// and the second key is used for GPU-to-CPU encryption. +// + +// Keyspace identifiers. +enum +{ + CC_KEYSPACE_GSP, + CC_KEYSPACE_SEC2, + CC_KEYSPACE_LCE0, + CC_KEYSPACE_LCE1, + CC_KEYSPACE_LCE2, + CC_KEYSPACE_LCE3, + CC_KEYSPACE_LCE4, + CC_KEYSPACE_LCE5, + CC_KEYSPACE_LCE6, + CC_KEYSPACE_LCE7, + CC_KEYSPACE_SIZE // This is always the last element. +}; + +enum +{ + CC_LKEYID_CPU_GSP_LOCKED_RPC, + CC_LKEYID_GSP_CPU_LOCKED_RPC, + CC_LKEYID_CPU_GSP_DMA, + CC_LKEYID_GSP_CPU_DMA, + CC_LKEYID_CPU_GSP_RESERVED1, + CC_LKEYID_GSP_CPU_REPLAYABLE_FAULT, + CC_LKEYID_CPU_GSP_RESERVED2, + CC_LKEYID_GSP_CPU_NON_REPLAYABLE_FAULT, + CC_KEYSPACE_GSP_SIZE // This is always the last element. +}; +// The fault buffers only support GPU-to-CPU encryption, so the CPU-to-GPU encryption slot +// is left reserved. + +#define CC_LKEYID_GSP_CPU_LOCKED_RPC_STR "gsp_cpu_locked_rpc" +#define CC_LKEYID_CPU_GSP_LOCKED_RPC_STR "cpu_gsp_locked_rpc" +#define CC_LKEYID_GSP_CPU_DMA_STR "gsp_cpu_dma" +#define CC_LKEYID_CPU_GSP_DMA_STR "cpu_gsp_dma" +#define CC_LKEYID_GSP_CPU_REPLAYABLE_FAULT_STR "gsp_cpu_replayable_fault" +#define CC_LKEYID_GSP_CPU_NON_REPLAYABLE_FAULT_STR "gsp_cpu_non_replayable_fault" + +enum +{ + CC_LKEYID_CPU_SEC2_DATA_USER, + CC_LKEYID_CPU_SEC2_HMAC_USER, + CC_LKEYID_CPU_SEC2_DATA_KERN, + CC_LKEYID_CPU_SEC2_HMAC_KERN, + CC_KEYSPACE_SEC2_SIZE // This is always the last element. +}; + +#define CC_LKEYID_CPU_SEC2_DATA_USER_STR "cpu_sec2_data_user" +#define CC_LKEYID_CPU_SEC2_HMAC_USER_STR "cpu_sec2_hmac_user" +#define CC_LKEYID_CPU_SEC2_DATA_KERN_STR "cpu_sec2_data_kernel" +#define CC_LKEYID_CPU_SEC2_HMAC_KERN_STR "cpu_sec2_hmac_kernel" + +enum +{ + CC_LKEYID_LCE_H2D_USER, + CC_LKEYID_LCE_D2H_USER, + CC_LKEYID_LCE_H2D_KERN, + CC_LKEYID_LCE_D2H_KERN, + CC_LKEYID_LCE_H2D_P2P, + CC_LKEYID_LCE_D2H_P2P, + CC_KEYSPACE_LCE_SIZE // This is always the last element. +}; + +#define CC_KEYSPACE_TOTAL_SIZE (CC_KEYSPACE_GSP_SIZE + CC_KEYSPACE_SEC2_SIZE + (8 * CC_KEYSPACE_LCE_SIZE)) + +#define CC_LKEYID_LCE0_H2D_USER_STR "Lce0_h2d_user" +#define CC_LKEYID_LCE0_D2H_USER_STR "Lce0_d2h_user" +#define CC_LKEYID_LCE0_H2D_KERN_STR "Lce0_h2d_kernel" +#define CC_LKEYID_LCE0_D2H_KERN_STR "Lce0_d2h_kernel" +#define CC_LKEYID_LCE0_H2D_P2P_STR "Lce0_h2d_p2p" +#define CC_LKEYID_LCE0_D2H_P2P_STR "Lce0_d2h_p2p" + +#define CC_LKEYID_LCE1_H2D_USER_STR "Lce1_h2d_user" +#define CC_LKEYID_LCE1_D2H_USER_STR "Lce1_d2h_user" +#define CC_LKEYID_LCE1_H2D_KERN_STR "Lce1_h2d_kernel" +#define CC_LKEYID_LCE1_D2H_KERN_STR "Lce1_d2h_kernel" +#define CC_LKEYID_LCE1_H2D_P2P_STR "Lce1_h2d_p2p" +#define CC_LKEYID_LCE1_D2H_P2P_STR "Lce1_d2h_p2p" + +#define CC_LKEYID_LCE2_H2D_USER_STR "Lce2_h2d_user" +#define CC_LKEYID_LCE2_D2H_USER_STR "Lce2_d2h_user" +#define CC_LKEYID_LCE2_H2D_KERN_STR "Lce2_h2d_kernel" +#define CC_LKEYID_LCE2_D2H_KERN_STR "Lce2_d2h_kernel" +#define CC_LKEYID_LCE2_H2D_P2P_STR "Lce2_h2d_p2p" +#define CC_LKEYID_LCE2_D2H_P2P_STR "Lce2_d2h_p2p" + +#define CC_LKEYID_LCE3_H2D_USER_STR "Lce3_h2d_user" +#define CC_LKEYID_LCE3_D2H_USER_STR "Lce3_d2h_user" +#define CC_LKEYID_LCE3_H2D_KERN_STR "Lce3_h2d_kernel" +#define CC_LKEYID_LCE3_D2H_KERN_STR "Lce3_d2h_kernel" +#define CC_LKEYID_LCE3_H2D_P2P_STR "Lce3_h2d_p2p" +#define CC_LKEYID_LCE3_D2H_P2P_STR "Lce3_d2h_p2p" + +#define CC_LKEYID_LCE4_H2D_USER_STR "Lce4_h2d_user" +#define CC_LKEYID_LCE4_D2H_USER_STR "Lce4_d2h_user" +#define CC_LKEYID_LCE4_H2D_KERN_STR "Lce4_h2d_kernel" +#define CC_LKEYID_LCE4_D2H_KERN_STR "Lce4_d2h_kernel" +#define CC_LKEYID_LCE4_H2D_P2P_STR "Lce4_h2d_p2p" +#define CC_LKEYID_LCE4_D2H_P2P_STR "Lce4_d2h_p2p" + +#define CC_LKEYID_LCE5_H2D_USER_STR "Lce5_h2d_user" +#define CC_LKEYID_LCE5_D2H_USER_STR "Lce5_d2h_user" +#define CC_LKEYID_LCE5_H2D_KERN_STR "Lce5_h2d_kernel" +#define CC_LKEYID_LCE5_D2H_KERN_STR "Lce5_d2h_kernel" +#define CC_LKEYID_LCE5_H2D_P2P_STR "Lce5_h2d_p2p" +#define CC_LKEYID_LCE5_D2H_P2P_STR "Lce5_d2h_p2p" + +#define CC_LKEYID_LCE6_H2D_USER_STR "Lce6_h2d_user" +#define CC_LKEYID_LCE6_D2H_USER_STR "Lce6_d2h_user" +#define CC_LKEYID_LCE6_H2D_KERN_STR "Lce6_h2d_kernel" +#define CC_LKEYID_LCE6_D2H_KERN_STR "Lce6_d2h_kernel" +#define CC_LKEYID_LCE6_H2D_P2P_STR "Lce6_h2d_p2p" +#define CC_LKEYID_LCE6_D2H_P2P_STR "Lce6_d2h_p2p" + +#define CC_LKEYID_LCE7_H2D_USER_STR "Lce7_h2d_user" +#define CC_LKEYID_LCE7_D2H_USER_STR "Lce7_d2h_user" +#define CC_LKEYID_LCE7_H2D_KERN_STR "Lce7_h2d_kernel" +#define CC_LKEYID_LCE7_D2H_KERN_STR "Lce7_d2h_kernel" +#define CC_LKEYID_LCE7_H2D_P2P_STR "Lce7_h2d_p2p" +#define CC_LKEYID_LCE7_D2H_P2P_STR "Lce7_d2h_p2p" + +// Generate a global key ID from a keyspace (a) and local key ID (b). +#define CC_GKEYID_GEN(a, b) (NvU32)(((a) << 16) | (b)) + +// Get the keyspace component from a global key ID. +#define CC_GKEYID_GET_KEYSPACE(a) (NvU16)((a) >> 16) + +// Get the local key ID from a global key ID. +#define CC_GKEYID_GET_LKEYID(a) (NvU16)((a) & 0xffff) + +// Get the unqiue string from a global key ID. +#define CC_GKEYID_GET_STR(a) \ + (CC_GKEYID_GET_KEYSPACE(a) == CC_KEYSPACE_GSP) ? \ + (CC_GKEYID_GET_LKEYID(a) == CC_LKEYID_GSP_CPU_LOCKED_RPC) ? \ + CC_LKEYID_GSP_CPU_LOCKED_RPC_STR : \ + (CC_GKEYID_GET_LKEYID(a) == CC_LKEYID_CPU_GSP_LOCKED_RPC) ? \ + CC_LKEYID_CPU_GSP_LOCKED_RPC_STR : \ + (CC_GKEYID_GET_LKEYID(a) == CC_LKEYID_GSP_CPU_DMA) ? \ + CC_LKEYID_GSP_CPU_DMA_STR : \ + (CC_GKEYID_GET_LKEYID(a) == CC_LKEYID_CPU_GSP_DMA) ? \ + CC_LKEYID_CPU_GSP_DMA_STR : \ + (CC_GKEYID_GET_LKEYID(a) == CC_LKEYID_GSP_CPU_REPLAYABLE_FAULT) ? \ + CC_LKEYID_GSP_CPU_REPLAYABLE_FAULT_STR : \ + (CC_GKEYID_GET_LKEYID(a) == CC_LKEYID_GSP_CPU_NON_REPLAYABLE_FAULT) ? \ + CC_LKEYID_GSP_CPU_NON_REPLAYABLE_FAULT_STR : NULL : \ + (CC_GKEYID_GET_KEYSPACE(a) == CC_KEYSPACE_SEC2) ? \ + (CC_GKEYID_GET_LKEYID(a) == CC_LKEYID_CPU_SEC2_DATA_USER) ? \ + CC_LKEYID_CPU_SEC2_DATA_USER_STR : \ + (CC_GKEYID_GET_LKEYID(a) == CC_LKEYID_CPU_SEC2_HMAC_USER) ? \ + CC_LKEYID_CPU_SEC2_HMAC_USER_STR : \ + (CC_GKEYID_GET_LKEYID(a) == CC_LKEYID_CPU_SEC2_DATA_KERN) ? \ + CC_LKEYID_CPU_SEC2_DATA_KERN_STR : \ + (CC_GKEYID_GET_LKEYID(a) == CC_LKEYID_CPU_SEC2_HMAC_KERN) ? \ + CC_LKEYID_CPU_SEC2_HMAC_KERN_STR : NULL : \ + (CC_GKEYID_GET_KEYSPACE(a) == CC_KEYSPACE_LCE0) ? \ + (CC_GKEYID_GET_LKEYID(a) == CC_LKEYID_LCE_H2D_USER) ? \ + CC_LKEYID_LCE0_H2D_USER_STR : \ + (CC_GKEYID_GET_LKEYID(a) == CC_LKEYID_LCE_D2H_USER) ? \ + CC_LKEYID_LCE0_D2H_USER_STR : \ + (CC_GKEYID_GET_LKEYID(a) == CC_LKEYID_LCE_H2D_KERN) ? \ + CC_LKEYID_LCE0_H2D_KERN_STR : \ + (CC_GKEYID_GET_LKEYID(a) == CC_LKEYID_LCE_D2H_KERN) ? \ + CC_LKEYID_LCE0_D2H_KERN_STR : \ + (CC_GKEYID_GET_LKEYID(a) == CC_LKEYID_LCE_H2D_P2P) ? \ + CC_LKEYID_LCE0_H2D_P2P_STR : \ + (CC_GKEYID_GET_LKEYID(a) == CC_LKEYID_LCE_D2H_P2P) ? \ + CC_LKEYID_LCE0_D2H_P2P_STR : NULL : \ + (CC_GKEYID_GET_KEYSPACE(a) == CC_KEYSPACE_LCE1) ? \ + (CC_GKEYID_GET_LKEYID(a) == CC_LKEYID_LCE_H2D_USER) ? \ + CC_LKEYID_LCE1_H2D_USER_STR : \ + (CC_GKEYID_GET_LKEYID(a) == CC_LKEYID_LCE_D2H_USER) ? \ + CC_LKEYID_LCE1_D2H_USER_STR : \ + (CC_GKEYID_GET_LKEYID(a) == CC_LKEYID_LCE_H2D_KERN) ? \ + CC_LKEYID_LCE1_H2D_KERN_STR : \ + (CC_GKEYID_GET_LKEYID(a) == CC_LKEYID_LCE_D2H_KERN) ? \ + CC_LKEYID_LCE1_D2H_KERN_STR : \ + (CC_GKEYID_GET_LKEYID(a) == CC_LKEYID_LCE_H2D_P2P) ? \ + CC_LKEYID_LCE1_H2D_P2P_STR : \ + (CC_GKEYID_GET_LKEYID(a) == CC_LKEYID_LCE_D2H_P2P) ? \ + CC_LKEYID_LCE1_D2H_P2P_STR : NULL : \ + (CC_GKEYID_GET_KEYSPACE(a) == CC_KEYSPACE_LCE2) ? \ + (CC_GKEYID_GET_LKEYID(a) == CC_LKEYID_LCE_H2D_USER) ? \ + CC_LKEYID_LCE2_H2D_USER_STR : \ + (CC_GKEYID_GET_LKEYID(a) == CC_LKEYID_LCE_D2H_USER) ? \ + CC_LKEYID_LCE2_D2H_USER_STR : \ + (CC_GKEYID_GET_LKEYID(a) == CC_LKEYID_LCE_H2D_KERN) ? \ + CC_LKEYID_LCE2_H2D_KERN_STR : \ + (CC_GKEYID_GET_LKEYID(a) == CC_LKEYID_LCE_D2H_KERN) ? \ + CC_LKEYID_LCE2_D2H_KERN_STR : \ + (CC_GKEYID_GET_LKEYID(a) == CC_LKEYID_LCE_H2D_P2P) ? \ + CC_LKEYID_LCE2_H2D_P2P_STR : \ + (CC_GKEYID_GET_LKEYID(a) == CC_LKEYID_LCE_D2H_P2P) ? \ + CC_LKEYID_LCE2_D2H_P2P_STR : NULL : \ + (CC_GKEYID_GET_KEYSPACE(a) == CC_KEYSPACE_LCE3) ? \ + (CC_GKEYID_GET_LKEYID(a) == CC_LKEYID_LCE_H2D_USER) ? \ + CC_LKEYID_LCE3_H2D_USER_STR : \ + (CC_GKEYID_GET_LKEYID(a) == CC_LKEYID_LCE_D2H_USER) ? \ + CC_LKEYID_LCE3_D2H_USER_STR : \ + (CC_GKEYID_GET_LKEYID(a) == CC_LKEYID_LCE_H2D_KERN) ? \ + CC_LKEYID_LCE3_H2D_KERN_STR : \ + (CC_GKEYID_GET_LKEYID(a) == CC_LKEYID_LCE_D2H_KERN) ? \ + CC_LKEYID_LCE3_D2H_KERN_STR : \ + (CC_GKEYID_GET_LKEYID(a) == CC_LKEYID_LCE_H2D_P2P) ? \ + CC_LKEYID_LCE3_H2D_P2P_STR : \ + (CC_GKEYID_GET_LKEYID(a) == CC_LKEYID_LCE_D2H_P2P) ? \ + CC_LKEYID_LCE3_D2H_P2P_STR : NULL : \ + (CC_GKEYID_GET_KEYSPACE(a) == CC_KEYSPACE_LCE4) ? \ + (CC_GKEYID_GET_LKEYID(a) == CC_LKEYID_LCE_H2D_USER) ? \ + CC_LKEYID_LCE4_H2D_USER_STR : \ + (CC_GKEYID_GET_LKEYID(a) == CC_LKEYID_LCE_D2H_USER) ? \ + CC_LKEYID_LCE4_D2H_USER_STR : \ + (CC_GKEYID_GET_LKEYID(a) == CC_LKEYID_LCE_H2D_KERN) ? \ + CC_LKEYID_LCE4_H2D_KERN_STR : \ + (CC_GKEYID_GET_LKEYID(a) == CC_LKEYID_LCE_D2H_KERN) ? \ + CC_LKEYID_LCE4_D2H_KERN_STR : \ + (CC_GKEYID_GET_LKEYID(a) == CC_LKEYID_LCE_H2D_P2P) ? \ + CC_LKEYID_LCE4_H2D_P2P_STR : \ + (CC_GKEYID_GET_LKEYID(a) == CC_LKEYID_LCE_D2H_P2P) ? \ + CC_LKEYID_LCE4_D2H_P2P_STR : NULL : \ + (CC_GKEYID_GET_KEYSPACE(a) == CC_KEYSPACE_LCE5) ? \ + (CC_GKEYID_GET_LKEYID(a) == CC_LKEYID_LCE_H2D_USER) ? \ + CC_LKEYID_LCE5_H2D_USER_STR : \ + (CC_GKEYID_GET_LKEYID(a) == CC_LKEYID_LCE_D2H_USER) ? \ + CC_LKEYID_LCE5_D2H_USER_STR : \ + (CC_GKEYID_GET_LKEYID(a) == CC_LKEYID_LCE_H2D_KERN) ? \ + CC_LKEYID_LCE5_H2D_KERN_STR : \ + (CC_GKEYID_GET_LKEYID(a) == CC_LKEYID_LCE_D2H_KERN) ? \ + CC_LKEYID_LCE5_D2H_KERN_STR : \ + (CC_GKEYID_GET_LKEYID(a) == CC_LKEYID_LCE_H2D_P2P) ? \ + CC_LKEYID_LCE5_H2D_P2P_STR : \ + (CC_GKEYID_GET_LKEYID(a) == CC_LKEYID_LCE_D2H_P2P) ? \ + CC_LKEYID_LCE5_D2H_P2P_STR : NULL : \ + (CC_GKEYID_GET_KEYSPACE(a) == CC_KEYSPACE_LCE6) ? \ + (CC_GKEYID_GET_LKEYID(a) == CC_LKEYID_LCE_H2D_USER) ? \ + CC_LKEYID_LCE6_H2D_USER_STR : \ + (CC_GKEYID_GET_LKEYID(a) == CC_LKEYID_LCE_D2H_USER) ? \ + CC_LKEYID_LCE6_D2H_USER_STR : \ + (CC_GKEYID_GET_LKEYID(a) == CC_LKEYID_LCE_H2D_KERN) ? \ + CC_LKEYID_LCE6_H2D_KERN_STR : \ + (CC_GKEYID_GET_LKEYID(a) == CC_LKEYID_LCE_D2H_KERN) ? \ + CC_LKEYID_LCE6_D2H_KERN_STR : \ + (CC_GKEYID_GET_LKEYID(a) == CC_LKEYID_LCE_H2D_P2P) ? \ + CC_LKEYID_LCE6_H2D_P2P_STR : \ + (CC_GKEYID_GET_LKEYID(a) == CC_LKEYID_LCE_D2H_P2P) ? \ + CC_LKEYID_LCE6_D2H_P2P_STR : NULL : \ + (CC_GKEYID_GET_KEYSPACE(a) == CC_KEYSPACE_LCE7) ? \ + (CC_GKEYID_GET_LKEYID(a) == CC_LKEYID_LCE_H2D_USER) ? \ + CC_LKEYID_LCE7_H2D_USER_STR : \ + (CC_GKEYID_GET_LKEYID(a) == CC_LKEYID_LCE_D2H_USER) ? \ + CC_LKEYID_LCE7_D2H_USER_STR : \ + (CC_GKEYID_GET_LKEYID(a) == CC_LKEYID_LCE_H2D_KERN) ? \ + CC_LKEYID_LCE7_H2D_KERN_STR : \ + (CC_GKEYID_GET_LKEYID(a) == CC_LKEYID_LCE_D2H_KERN) ? \ + CC_LKEYID_LCE7_D2H_KERN_STR : \ + (CC_GKEYID_GET_LKEYID(a) == CC_LKEYID_LCE_H2D_P2P) ? \ + CC_LKEYID_LCE7_H2D_P2P_STR : \ + (CC_GKEYID_GET_LKEYID(a) == CC_LKEYID_LCE_D2H_P2P) ? \ + CC_LKEYID_LCE7_D2H_P2P_STR : NULL : NULL + +#define CC_EXPORT_MASTER_KEY_SIZE_BYTES 32 + +#endif // CC_KEYSTORE_H diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/arch/nvalloc/common/inc/dev_ctrl_defines.h nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/arch/nvalloc/common/inc/dev_ctrl_defines.h --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/arch/nvalloc/common/inc/dev_ctrl_defines.h 2023-10-25 20:20:24.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/arch/nvalloc/common/inc/dev_ctrl_defines.h 2024-03-05 22:12:42.000000000 +0000 @@ -36,53 +36,49 @@ // giving us a total of 128 LEAF registers. // GPU vector: The 128 LEAF registers give us a total of (128*32) GPU vectors // giving us a total of 4096 GPU vectors -// +// // // Given a subtree index, the below macros give us the index of the TOP level // register and the bit within the TOP level register to program for that // subtree. // -#define NV_CTRL_INTR_SUBTREE_TO_TOP_IDX(i) ((i) / 32) -#define NV_CTRL_INTR_SUBTREE_TO_TOP_BIT(i) ((i) % 32) +#define NV_CTRL_INTR_SUBTREE_TO_TOP_IDX(i) (((NvU32)(i)) / 32) +#define NV_CTRL_INTR_SUBTREE_TO_TOP_BIT(i) (((NvU32)(i)) % 32) // // Given a subtree index, the below macros give us the two LEAF register indices // that correspond to that subtree. // -#define NV_CTRL_INTR_SUBTREE_TO_LEAF_IDX_START(i) ((i)*2) -#define NV_CTRL_INTR_SUBTREE_TO_LEAF_IDX_END(i) (((i)*2) + 1) +#define NV_CTRL_INTR_SUBTREE_TO_LEAF_IDX_START(i) (((NvU32)(i)) * 2) +#define NV_CTRL_INTR_SUBTREE_TO_LEAF_IDX_END(i) ((((NvU32)(i)) * 2) + 1) -#define NV_CTRL_INTR_LEAF_IDX_TO_SUBTREE(i) ((i)/2) +#define NV_CTRL_INTR_LEAF_IDX_TO_SUBTREE(i) (((NvU32)(i)) / 2) // // Given a LEAF register index, the below macros give us the range of GPU // interrupt vectors that correspond to those leafs. // -#define NV_CTRL_INTR_LEAF_IDX_TO_GPU_VECTOR_START(i) ((i)*32) -#define NV_CTRL_INTR_LEAF_IDX_TO_GPU_VECTOR_END(i) (((i)*32) + 31) +#define NV_CTRL_INTR_LEAF_IDX_TO_GPU_VECTOR_START(i) (((NvU32)(i)) * 32) +#define NV_CTRL_INTR_LEAF_IDX_TO_GPU_VECTOR_END(i) ((((NvU32)(i)) * 32) + 31) // // Given a GPU interrupt vector, the below macros give us the index of the // LEAF register and the bit within the LEAF register to program for that // GPU interrupt vector. // -#define NV_CTRL_INTR_GPU_VECTOR_TO_LEAF_REG(i) ((i) / 32) -#define NV_CTRL_INTR_GPU_VECTOR_TO_LEAF_BIT(i) ((i) % 32) +#define NV_CTRL_INTR_GPU_VECTOR_TO_LEAF_REG(i) (((NvU32)(i)) / 32) +#define NV_CTRL_INTR_GPU_VECTOR_TO_LEAF_BIT(i) (((NvU32)(i)) % 32) // // Given a GPU interrupt vector, the below macro gives us the subtree in which // it belongs. // -#define NV_CTRL_INTR_GPU_VECTOR_TO_SUBTREE(i) ((NV_CTRL_INTR_GPU_VECTOR_TO_LEAF_REG(i)) / 2) +#define NV_CTRL_INTR_GPU_VECTOR_TO_SUBTREE(i) \ + ((NV_CTRL_INTR_GPU_VECTOR_TO_LEAF_REG(i)) / 2) -// // The max number of leaf registers we expect -// This is enforced to be greater than or equal to -// (NV_CTRL_INTR_SUBTREE_TO_LEAF_IDX_END(NV_CPU_INTR_STALL_SUBTREE_LAST) + 1) -// for the largest NV_CPU_INTR_STALL_SUBTREE_LAST -// -#define NV_MAX_INTR_LEAVES 12 +#define NV_MAX_INTR_LEAVES 16 // In SW, this specifies an invalid interrupt vector #define NV_INTR_VECTOR_INVALID (NV_U32_MAX) diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/arch/nvalloc/common/inc/flcnifcmn.h nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/arch/nvalloc/common/inc/flcnifcmn.h --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/arch/nvalloc/common/inc/flcnifcmn.h 2023-10-25 20:20:25.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/arch/nvalloc/common/inc/flcnifcmn.h 2024-03-05 22:12:42.000000000 +0000 @@ -31,10 +31,6 @@ #include "nvtypes.h" #include "flcnretval.h" -#ifndef NV_SIZEOF32 -#define NV_SIZEOF32(v) (sizeof(v)) -#endif - #ifndef NV_ARRAY_ELEMENTS #define NV_ARRAY_ELEMENTS(x) ((sizeof(x)/sizeof((x)[0]))) #endif diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/arch/nvalloc/common/inc/flcnretval.h nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/arch/nvalloc/common/inc/flcnretval.h --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/arch/nvalloc/common/inc/flcnretval.h 2023-10-25 20:20:25.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/arch/nvalloc/common/inc/flcnretval.h 2024-03-05 22:12:42.000000000 +0000 @@ -290,4 +290,7 @@ // Arithmetic errors #define FLCN_ERR_ARITHMETIC_OVERFLOW (0xFAU) +// Pri errros +#define FLCN_ERR_OUTSTANDING_PRI_ERROR (0xFBU) + #endif // FLCNRETVAL_H diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/arch/nvalloc/common/inc/fsp/fsp_emem_channels.h nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/arch/nvalloc/common/inc/fsp/fsp_emem_channels.h --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/arch/nvalloc/common/inc/fsp/fsp_emem_channels.h 2023-10-25 20:20:25.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/arch/nvalloc/common/inc/fsp/fsp_emem_channels.h 2024-03-05 22:12:42.000000000 +0000 @@ -33,15 +33,7 @@ // RM uses channel 0 for FSP EMEM. #define FSP_EMEM_CHANNEL_RM 0x0 -// PMU/SOE use channel 4 for FSP EMEM. -#define FSP_EMEM_CHANNEL_PMU_SOE 0x4 -#define FSP_EMEM_CHANNEL_MAX 0x8 - // EMEM channel 0 (RM) is allocated 1K bytes. #define FSP_EMEM_CHANNEL_RM_SIZE 1024 -// EMEM channel 4 (PMU/SOE) is allocated 1K bytes. -#define FSP_EMEM_CHANNEL_PMU_SOE_SIZE 1024 -#define FSP_EMEM_CHANNEL_PMU_SOE_OFFSET 4096 - #endif // _FSP_EMEM_CHANNELS_H_ diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/arch/nvalloc/common/inc/fsp/fsp_nvdm_format.h nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/arch/nvalloc/common/inc/fsp/fsp_nvdm_format.h --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/arch/nvalloc/common/inc/fsp/fsp_nvdm_format.h 2023-10-25 20:20:25.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/arch/nvalloc/common/inc/fsp/fsp_nvdm_format.h 2024-03-05 22:12:42.000000000 +0000 @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 2022 NVIDIA CORPORATION & AFFILIATES + * SPDX-FileCopyrightText: Copyright (c) 2022-2023 NVIDIA CORPORATION & AFFILIATES * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -39,5 +39,8 @@ #define NVDM_TYPE_FSP_RESPONSE 0x15 #define NVDM_TYPE_INFOROM 0x17 #define NVDM_TYPE_SMBPBI 0x18 +#define NVDM_TYPE_ROMREAD 0x1A +#define NVDM_TYPE_UEFI_RM 0x1C +#define NVDM_TYPE_UEFI_XTL_DEBUG_INTR 0x1D #endif // _FSP_NVDM_FORMAT_H_ diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/arch/nvalloc/common/inc/gsp/gsp_fw_sr_meta.h nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/arch/nvalloc/common/inc/gsp/gsp_fw_sr_meta.h --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/arch/nvalloc/common/inc/gsp/gsp_fw_sr_meta.h 1970-01-01 00:00:00.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/arch/nvalloc/common/inc/gsp/gsp_fw_sr_meta.h 2024-03-05 22:12:43.000000000 +0000 @@ -0,0 +1,86 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2022-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#pragma once + +#ifndef GSP_FW_SR_META_H_ +#define GSP_FW_SR_META_H_ + +#define GSP_FW_SR_META_MAGIC 0x8a3bb9e6c6c39d93ULL +#define GSP_FW_SR_META_REVISION 2 + +/*! + * GSP firmware SR metadata + * + * Initialized by CPU-RM and kept in Sysmem. + * Verified by Booter. + * + */ +typedef struct +{ + // + // Magic + // Use for verification by Booter + // + NvU64 magic; // = GSP_FW_SR_META_MAGIC; + + // + // Revision number + // Bumped up when we change this interface so it is not backward compatible. + // Bumped up when we revoke GSP-RM ucode + // + NvU64 revision; // = GSP_FW_SR_META_MAGIC_REVISION; + + // + // ---- Members regarding data in SYSMEM ---------------------------- + // Consumed by Booter for DMA + // + NvU64 sysmemAddrOfSuspendResumeData; + NvU64 sizeOfSuspendResumeData; + + // ---- Members for crypto ops across S/R --------------------------- + + // + // HMAC over the entire GspFwSRMeta structure (including padding) + // with the hmac field itself zeroed. + // + NvU8 hmac[32]; + + // Hash over GspFwWprMeta structure + NvU8 wprMetaHash[32]; + + // Hash over GspFwHeapFreeList structure. All zeros signifies no free list. + NvU8 heapFreeListHash[32]; + + // Hash over data in WPR2 (skipping over free heap chunks; see Booter for details) + NvU8 dataHash[32]; + + // + // Pad structure to exactly 256 bytes (1 DMA chunk). + // Padding initialized to zero. + // + NvU32 padding[24]; + +} GspFwSRMeta; + +#endif // GSP_FW_SR_META_H_ diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/arch/nvalloc/common/inc/gsp/gsp_fw_wpr_meta.h nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/arch/nvalloc/common/inc/gsp/gsp_fw_wpr_meta.h --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/arch/nvalloc/common/inc/gsp/gsp_fw_wpr_meta.h 2023-10-25 20:20:25.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/arch/nvalloc/common/inc/gsp/gsp_fw_wpr_meta.h 2024-03-05 22:12:43.000000000 +0000 @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 2021-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2021-2024 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -80,8 +80,26 @@ NvU64 bootloaderDataOffset; NvU64 bootloaderManifestOffset; - NvU64 sysmemAddrOfSignature; - NvU64 sizeOfSignature; + union + { + // Used only at initial boot + struct + { + NvU64 sysmemAddrOfSignature; + NvU64 sizeOfSignature; + }; + + // + // Used at suspend/resume to read GspFwHeapFreeList + // Offset relative to GspFwWprMeta FBMEM PA (gspFwWprStart) + // + struct + { + NvU32 gspFwHeapFreeListWprOffset; + NvU32 unused0; + NvU64 unused1; + }; + }; // ---- Members describing FB layout -------------------------------- NvU64 gspFwRsvdStart; @@ -119,32 +137,62 @@ // Boot count. Used to determine whether to load the firmware image. NvU64 bootCount; - // TODO: the partitionRpc* fields below do not really belong in this - // structure. The values are patched in by the partition bootstrapper - // when GSP-RM is booted in a partition, and this structure was a - // convenient place for the bootstrapper to access them. These should - // be moved to a different comm. mechanism between the bootstrapper - // and the GSP-RM tasks. - - // Shared partition RPC memory (physical address) - NvU64 partitionRpcAddr; - - // Offsets relative to partitionRpcAddr - NvU16 partitionRpcRequestOffset; - NvU16 partitionRpcReplyOffset; - - // Code section and dataSection offset and size. - NvU32 elfCodeOffset; - NvU32 elfDataOffset; - NvU32 elfCodeSize; - NvU32 elfDataSize; + // This union is organized the way it is to start at an 8-byte boundary and achieve natural + // packing of the internal struct fields. + union + { + struct + { + // TODO: the partitionRpc* fields below do not really belong in this + // structure. The values are patched in by the partition bootstrapper + // when GSP-RM is booted in a partition, and this structure was a + // convenient place for the bootstrapper to access them. These should + // be moved to a different comm. mechanism between the bootstrapper + // and the GSP-RM tasks. + + // Shared partition RPC memory (physical address) + NvU64 partitionRpcAddr; + + // Offsets relative to partitionRpcAddr + NvU16 partitionRpcRequestOffset; + NvU16 partitionRpcReplyOffset; + + // Code section and dataSection offset and size. + NvU32 elfCodeOffset; + NvU32 elfDataOffset; + NvU32 elfCodeSize; + NvU32 elfDataSize; + + // Used during GSP-RM resume to check for revocation + NvU32 lsUcodeVersion; + }; + + struct + { + // Pad for the partitionRpc* fields, plus 4 bytes + NvU32 partitionRpcPadding[4]; + + // CrashCat (contiguous) buffer size/location - occupies same bytes as the + // elf(Code|Data)(Offset|Size) fields above. + // TODO: move to GSP_FMC_INIT_PARAMS + NvU64 sysmemAddrOfCrashReportQueue; + NvU32 sizeOfCrashReportQueue; + + // Pad for the lsUcodeVersion field + NvU32 lsUcodeVersionPadding[1]; + }; + }; + + // Number of VF partitions allocating sub-heaps from the WPR heap + // Used during boot to ensure the heap is adequately sized + NvU8 gspFwHeapVfPartitionCount; - // Bit 0 is used to check if [VGPU-GSP] mode is active in init partition - NvU8 driverModel; + // Flags to help decide GSP-FW flow. + NvU8 flags; // Pad structure to exactly 256 bytes. Can replace padding with additional // fields without incrementing revision. Padding initialized to 0. - NvU8 padding[11]; + NvU8 padding[6]; // BL to use for verification (i.e. Booter says OK to boot) NvU64 verified; // 0x0 -> unverified, 0xa0a0a0a0a0a0a0a0 -> verified @@ -154,7 +202,29 @@ #define GSP_FW_WPR_META_REVISION 1 #define GSP_FW_WPR_META_MAGIC 0xdc3aae21371a60b3ULL -// Bit 0 is used to check if [VGPU-GSP] mode is active in init partition -#define DRIVERMODEL_VGPU 0 +#define GSP_FW_WPR_HEAP_FREE_REGION_COUNT 128 + +typedef struct +{ + // + // offset relative to GspFwWprMeta FBMEM PA + // describes a region at [offs, offs + length) + // + NvU32 offs; // start, inclusive + NvU32 length; +} GspFwHeapFreeRegion; + +typedef struct +{ + NvU64 magic; + NvU32 nregions; + GspFwHeapFreeRegion regions[GSP_FW_WPR_HEAP_FREE_REGION_COUNT]; +} GspFwHeapFreeList; + +#define GSP_FW_HEAP_FREE_LIST_MAGIC 0x4845415046524545ULL + +#define GSP_FW_FLAGS 8:0 +#define GSP_FW_FLAGS_CLOCK_BOOST NVBIT(0) +#define GSP_FW_FLAGS_RECOVERY_MARGIN_PRESENT NVBIT(1) #endif // GSP_FW_WPR_META_H_ diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/arch/nvalloc/common/inc/gsp/gsp_proxy_reg.h nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/arch/nvalloc/common/inc/gsp/gsp_proxy_reg.h --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/arch/nvalloc/common/inc/gsp/gsp_proxy_reg.h 1970-01-01 00:00:00.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/arch/nvalloc/common/inc/gsp/gsp_proxy_reg.h 2024-03-05 22:12:43.000000000 +0000 @@ -0,0 +1,39 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2021-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef NVGSP_PROXY_REG_H +#define NVGSP_PROXY_REG_H + +#define NVGSP_PROXY_REG_CONFIDENTIAL_COMPUTE 0:0 +#define NVGSP_PROXY_REG_CONFIDENTIAL_COMPUTE_DISABLE 0x00000000 +#define NVGSP_PROXY_REG_CONFIDENTIAL_COMPUTE_ENABLE 0x00000001 + +#define NVGSP_PROXY_REG_CONF_COMPUTE_EARLY_INIT 1:1 +#define NVGSP_PROXY_REG_CONF_COMPUTE_EARLY_INIT_DISABLE 0x00000000 +#define NVGSP_PROXY_REG_CONF_COMPUTE_EARLY_INIT_ENABLE 0x00000001 + +#define NVGSP_PROXY_REG_CONF_COMPUTE_DEV_MODE 2:2 +#define NVGSP_PROXY_REG_CONF_COMPUTE_DEV_MODE_DISABLE 0x00000000 +#define NVGSP_PROXY_REG_CONF_COMPUTE_DEV_MODE_ENABLE 0x00000001 + +#endif // NVGSP_PROXY_REG_H diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/arch/nvalloc/common/inc/gsp/gspifpub.h nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/arch/nvalloc/common/inc/gsp/gspifpub.h --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/arch/nvalloc/common/inc/gsp/gspifpub.h 2023-10-25 20:20:25.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/arch/nvalloc/common/inc/gsp/gspifpub.h 2024-03-05 22:12:43.000000000 +0000 @@ -77,9 +77,9 @@ */ typedef struct GSP_RM_PARAMS { - // Physical memory aperture through which bootArgsPa is accessed + // Physical memory aperture through which bootArgsOffset is accessed GSP_DMA_TARGET target; - // Physical address that will be stuffed in NV_PGSP_FALCON_MAILBOX(0|1) + // Physical offset in the memory aperture that will be passed to GSP-RM NvU64 bootArgsOffset; } GSP_RM_PARAMS; diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/arch/nvalloc/common/inc/inforom/ifrnvl.h nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/arch/nvalloc/common/inc/inforom/ifrnvl.h --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/arch/nvalloc/common/inc/inforom/ifrnvl.h 2023-10-25 20:20:26.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/arch/nvalloc/common/inc/inforom/ifrnvl.h 2024-03-05 22:12:43.000000000 +0000 @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 2017-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2017-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/arch/nvalloc/common/inc/inforom/ifrstruct.h nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/arch/nvalloc/common/inc/inforom/ifrstruct.h --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/arch/nvalloc/common/inc/inforom/ifrstruct.h 2023-10-25 20:20:26.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/arch/nvalloc/common/inc/inforom/ifrstruct.h 2024-03-05 22:12:43.000000000 +0000 @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 1999-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 1999-2024 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -69,7 +69,9 @@ inforom_U032 productLength; inforom_U032 productWidth; inforom_U032 productHeight; - inforom_U008 reserved[89]; + inforom_U008 vbiosFactoryVersion[5]; + inforom_U008 board965PartNumber[20]; + inforom_U008 reserved[64]; }; #define INFOROM_OBD_OBJECT_V2_XX_FMT INFOROM_OBJECT_HEADER_V1_00_FMT "d111b3d89b" typedef struct INFOROM_OBD_OBJECT_V2_XX INFOROM_OBD_OBJECT_V2_XX; diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/arch/nvalloc/common/inc/nv-firmware-chip-family-select.h nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/arch/nvalloc/common/inc/nv-firmware-chip-family-select.h --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/arch/nvalloc/common/inc/nv-firmware-chip-family-select.h 2023-10-25 20:20:26.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/arch/nvalloc/common/inc/nv-firmware-chip-family-select.h 2024-03-05 22:12:44.000000000 +0000 @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2022-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -52,8 +52,8 @@ return NV_FIRMWARE_CHIP_FAMILY_AD10X; case GPU_ARCHITECTURE_HOPPER: - if (gpuImpl == GPU_IMPLEMENTATION_GH100) - return NV_FIRMWARE_CHIP_FAMILY_GH100; + return NV_FIRMWARE_CHIP_FAMILY_GH100; + } return NV_FIRMWARE_CHIP_FAMILY_NULL; diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/arch/nvalloc/common/inc/nv-firmware.h nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/arch/nvalloc/common/inc/nv-firmware.h --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/arch/nvalloc/common/inc/nv-firmware.h 2023-10-25 20:20:26.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/arch/nvalloc/common/inc/nv-firmware.h 2024-03-05 22:12:44.000000000 +0000 @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2022-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -81,12 +81,12 @@ { switch (fw_chip_family) { - case NV_FIRMWARE_CHIP_FAMILY_AD10X: - return NV_FIRMWARE_PATH_FOR_FILENAME("gsp_ad10x.bin"); - case NV_FIRMWARE_CHIP_FAMILY_GH100: // fall through + case NV_FIRMWARE_CHIP_FAMILY_AD10X: // fall through + case NV_FIRMWARE_CHIP_FAMILY_GA10X: + return NV_FIRMWARE_PATH_FOR_FILENAME("gsp_ga10x.bin"); + case NV_FIRMWARE_CHIP_FAMILY_GA100: // fall through - case NV_FIRMWARE_CHIP_FAMILY_GA10X: // fall through case NV_FIRMWARE_CHIP_FAMILY_TU11X: // fall through case NV_FIRMWARE_CHIP_FAMILY_TU10X: return NV_FIRMWARE_PATH_FOR_FILENAME("gsp_tu10x.bin"); @@ -100,12 +100,12 @@ { switch (fw_chip_family) { - case NV_FIRMWARE_CHIP_FAMILY_AD10X: - return NV_FIRMWARE_PATH_FOR_FILENAME("gsp_log_ad10x.bin"); - case NV_FIRMWARE_CHIP_FAMILY_GH100: // fall through + case NV_FIRMWARE_CHIP_FAMILY_AD10X: // fall through + case NV_FIRMWARE_CHIP_FAMILY_GA10X: + return NV_FIRMWARE_PATH_FOR_FILENAME("gsp_log_ga10x.bin"); + case NV_FIRMWARE_CHIP_FAMILY_GA100: // fall through - case NV_FIRMWARE_CHIP_FAMILY_GA10X: // fall through case NV_FIRMWARE_CHIP_FAMILY_TU11X: // fall through case NV_FIRMWARE_CHIP_FAMILY_TU10X: return NV_FIRMWARE_PATH_FOR_FILENAME("gsp_log_tu10x.bin"); @@ -125,7 +125,7 @@ // which will then be invoked (at the top-level) for each // gsp_*.bin (but not gsp_log_*.bin) #if defined(NV_FIRMWARE_DECLARE_GSP_FILENAME) -NV_FIRMWARE_DECLARE_GSP_FILENAME("gsp_ad10x.bin") +NV_FIRMWARE_DECLARE_GSP_FILENAME("gsp_ga10x.bin") NV_FIRMWARE_DECLARE_GSP_FILENAME("gsp_tu10x.bin") #endif // defined(NV_FIRMWARE_DECLARE_GSP_FILENAME) diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/arch/nvalloc/common/inc/nvcst.h nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/arch/nvalloc/common/inc/nvcst.h --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/arch/nvalloc/common/inc/nvcst.h 2023-10-25 20:20:26.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/arch/nvalloc/common/inc/nvcst.h 2024-03-05 22:12:44.000000000 +0000 @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 2004-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2004-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -84,12 +84,15 @@ CHIPSET_SETUP_FUNC(Ampere_eMag_setupFunc) CHIPSET_SETUP_FUNC(Huawei_Kunpeng920_setupFunc) CHIPSET_SETUP_FUNC(Mellanox_BlueField_setupFunc) +CHIPSET_SETUP_FUNC(Mellanox_BlueField3_setupFunc) CHIPSET_SETUP_FUNC(Amazon_Gravitron2_setupFunc) CHIPSET_SETUP_FUNC(Fujitsu_A64FX_setupFunc) CHIPSET_SETUP_FUNC(Ampere_Altra_setupFunc) CHIPSET_SETUP_FUNC(Arm_NeoverseN1_setupFunc) +CHIPSET_SETUP_FUNC(Ampere_AmpereOne_setupFunc) CHIPSET_SETUP_FUNC(Nvidia_T210_setupFunc) CHIPSET_SETUP_FUNC(Nvidia_T194_setupFunc) +CHIPSET_SETUP_FUNC(Nvidia_TH500_setupFunc) // Keep string length <=32 (including termination) to avoid string copy overflow @@ -184,6 +187,7 @@ {PCI_VENDOR_ID_INTEL, 0x7A82, CS_INTEL_7A82, "Intel-AlderLake", Intel_7A82_setupFunc}, {PCI_VENDOR_ID_INTEL, 0x7A84, CS_INTEL_7A82, "Intel-AlderLake", Intel_7A82_setupFunc}, {PCI_VENDOR_ID_INTEL, 0x1B81, CS_INTEL_1B81, "Intel-SapphireRapids", NULL}, + {PCI_VENDOR_ID_INTEL, 0x7A8A, CS_INTEL_1B81, "Intel-SapphireRapids", NULL}, {PCI_VENDOR_ID_INTEL, 0x18DC, CS_INTEL_18DC, "Intel-IceLake", NULL}, {PCI_VENDOR_ID_INTEL, 0x7A04, CS_INTEL_7A04, "Intel-RaptorLake", Intel_7A04_setupFunc}, @@ -199,6 +203,12 @@ {PCI_VENDOR_ID_NVIDIA, 0x229E, CS_NVIDIA_T234, "T234", Nvidia_T194_setupFunc}, {PCI_VENDOR_ID_NVIDIA, 0x22C2, CS_NVIDIA_T23x, "T23x", Nvidia_T194_setupFunc}, {PCI_VENDOR_ID_NVIDIA, 0x22C3, CS_NVIDIA_T23x, "T23x", Nvidia_T194_setupFunc}, + {PCI_VENDOR_ID_NVIDIA, 0x22B1, CS_NVIDIA_TH500, "TH500", Nvidia_TH500_setupFunc}, + {PCI_VENDOR_ID_NVIDIA, 0x22B2, CS_NVIDIA_TH500, "TH500", Nvidia_TH500_setupFunc}, + {PCI_VENDOR_ID_NVIDIA, 0x22B3, CS_NVIDIA_TH500, "TH500", Nvidia_TH500_setupFunc}, + {PCI_VENDOR_ID_NVIDIA, 0x22B4, CS_NVIDIA_TH500, "TH500", Nvidia_TH500_setupFunc}, + {PCI_VENDOR_ID_NVIDIA, 0x22B8, CS_NVIDIA_TH500, "TH500", Nvidia_TH500_setupFunc}, + {PCI_VENDOR_ID_NVIDIA, 0x22B9, CS_NVIDIA_TH500, "TH500", Nvidia_TH500_setupFunc}, {PCI_VENDOR_ID_SIS, 0x0649, CS_SIS_649, "649", SiS_656_setupFunc}, {PCI_VENDOR_ID_SIS, 0x0656, CS_SIS_656, "656", SiS_656_setupFunc}, @@ -237,6 +247,7 @@ {PCI_VENDOR_ID_MELLANOX, 0xA2D0, CS_MELLANOX_BLUEFIELD, "Mellanox BlueField", Mellanox_BlueField_setupFunc}, {PCI_VENDOR_ID_MELLANOX, 0xA2D4, CS_MELLANOX_BLUEFIELD2, "Mellanox BlueField 2", NULL}, {PCI_VENDOR_ID_MELLANOX, 0xA2D5, CS_MELLANOX_BLUEFIELD2, "Mellanox BlueField 2 Crypto disabled", NULL}, + {PCI_VENDOR_ID_MELLANOX, 0xA2DB, CS_MELLANOX_BLUEFIELD3, "Mellanox BlueField 3", Mellanox_BlueField3_setupFunc}, {PCI_VENDOR_ID_AMAZON, 0x0200, CS_AMAZON_GRAVITRON2, "Amazon Gravitron2", Amazon_Gravitron2_setupFunc}, {PCI_VENDOR_ID_FUJITSU, 0x1952, CS_FUJITSU_A64FX, "Fujitsu A64FX", Fujitsu_A64FX_setupFunc}, {PCI_VENDOR_ID_CADENCE, 0xDC01, CS_PHYTIUM_S2500, "Phytium S2500", NULL}, @@ -255,6 +266,14 @@ {PCI_VENDOR_ID_HYGON, 0x790E, CS_HYGON_C86, "Hygon-C86-7151", NULL}, {PCI_VENDOR_ID_MARVELL, 0xA02D, CS_MARVELL_OCTEON_CN96XX, "Marvell Octeon CN96xx", ARMV8_generic_setupFunc}, {PCI_VENDOR_ID_MARVELL, 0xA02D, CS_MARVELL_OCTEON_CN98XX, "Marvell Octeon CN98xx", ARMV8_generic_setupFunc}, + {PCI_VENDOR_ID_AMPERE, 0xE200, CS_AMPERE_AMPEREONE, "Ampere AmpereOne", Ampere_AmpereOne_setupFunc}, + {PCI_VENDOR_ID_AMPERE, 0xE201, CS_AMPERE_AMPEREONE, "Ampere AmpereOne", Ampere_AmpereOne_setupFunc}, + {PCI_VENDOR_ID_AMPERE, 0xE202, CS_AMPERE_AMPEREONE, "Ampere AmpereOne", Ampere_AmpereOne_setupFunc}, + {PCI_VENDOR_ID_AMPERE, 0xE203, CS_AMPERE_AMPEREONE, "Ampere AmpereOne", Ampere_AmpereOne_setupFunc}, + {PCI_VENDOR_ID_AMPERE, 0xE204, CS_AMPERE_AMPEREONE, "Ampere AmpereOne", Ampere_AmpereOne_setupFunc}, + {PCI_VENDOR_ID_AMPERE, 0xE205, CS_AMPERE_AMPEREONE, "Ampere AmpereOne", Ampere_AmpereOne_setupFunc}, + {PCI_VENDOR_ID_AMPERE, 0xE206, CS_AMPERE_AMPEREONE, "Ampere AmpereOne", Ampere_AmpereOne_setupFunc}, + {PCI_VENDOR_ID_AMPERE, 0xE207, CS_AMPERE_AMPEREONE, "Ampere AmpereOne", Ampere_AmpereOne_setupFunc}, /////////////////////////////////////////////////////////////////////////////////////////////////// @@ -312,6 +331,12 @@ {PCI_VENDOR_ID_NVIDIA, 0x229E, CS_NVIDIA_T234}, // NVIDIA Tegra Orin RP2 {PCI_VENDOR_ID_NVIDIA, 0x22C2, CS_NVIDIA_T23x}, // NVIDIA Tegra RP0 {PCI_VENDOR_ID_NVIDIA, 0x22C3, CS_NVIDIA_T23x}, // NVIDIA Tegra RP1 + {PCI_VENDOR_ID_NVIDIA, 0x22B1, CS_NVIDIA_TH500}, // NVIDIA TH500 RP for GH100 GPU in GH180. + {PCI_VENDOR_ID_NVIDIA, 0x22B2, CS_NVIDIA_TH500}, // NVIDIA TH500 RP x16 + {PCI_VENDOR_ID_NVIDIA, 0x22B3, CS_NVIDIA_TH500}, // NVIDIA TH500 RP x4 + {PCI_VENDOR_ID_NVIDIA, 0x22B4, CS_NVIDIA_TH500}, // NVIDIA TH500 RP x1 + {PCI_VENDOR_ID_NVIDIA, 0x22B8, CS_NVIDIA_TH500}, // NVIDIA TH500 RP x8 + {PCI_VENDOR_ID_NVIDIA, 0x22B9, CS_NVIDIA_TH500}, // NVIDIA TH500 RP x2 {PCI_VENDOR_ID_APM, 0xe004, CS_APM_STORM}, // Applied Micro X-Gene "Storm" {PCI_VENDOR_ID_MARVELL, 0xAF00, CS_MARVELL_THUNDERX2}, // Marvell ThunderX2 @@ -328,6 +353,7 @@ {PCI_VENDOR_ID_MELLANOX, 0xA2D0, CS_MELLANOX_BLUEFIELD}, // Mellanox BlueField {PCI_VENDOR_ID_MELLANOX, 0xA2D4, CS_MELLANOX_BLUEFIELD2},// Mellanox BlueField 2 {PCI_VENDOR_ID_MELLANOX, 0xA2D5, CS_MELLANOX_BLUEFIELD2},// Mellanox BlueField 2 Crypto disabled + {PCI_VENDOR_ID_MELLANOX, 0xA2DB, CS_MELLANOX_BLUEFIELD3},// Mellanox BlueField 3 {PCI_VENDOR_ID_AMAZON, 0x0200, CS_AMAZON_GRAVITRON2}, // Amazon Gravitron2 {PCI_VENDOR_ID_FUJITSU, 0x1952, CS_FUJITSU_A64FX}, // Fujitsu A64FX {PCI_VENDOR_ID_CADENCE, 0xDC01, CS_PHYTIUM_S2500}, // Phytium S2500 @@ -346,6 +372,14 @@ {PCI_VENDOR_ID_MARVELL, 0xA02D, CS_MARVELL_OCTEON_CN96XX}, // Marvell OCTEON CN96xx {PCI_VENDOR_ID_MARVELL, 0xA02D, CS_MARVELL_OCTEON_CN98XX}, // Marvell OCTEON CN98xx {PCI_VENDOR_ID_ALIBABA, 0x8000, CS_ALIBABA_YITIAN}, // Alibaba Yitian + {PCI_VENDOR_ID_AMPERE, 0xE200, CS_AMPERE_AMPEREONE}, // Ampere AmpereOne + {PCI_VENDOR_ID_AMPERE, 0xE201, CS_AMPERE_AMPEREONE}, // Ampere AmpereOne + {PCI_VENDOR_ID_AMPERE, 0xE202, CS_AMPERE_AMPEREONE}, // Ampere AmpereOne + {PCI_VENDOR_ID_AMPERE, 0xE203, CS_AMPERE_AMPEREONE}, // Ampere AmpereOne + {PCI_VENDOR_ID_AMPERE, 0xE204, CS_AMPERE_AMPEREONE}, // Ampere AmpereOne + {PCI_VENDOR_ID_AMPERE, 0xE205, CS_AMPERE_AMPEREONE}, // Ampere AmpereOne + {PCI_VENDOR_ID_AMPERE, 0xE206, CS_AMPERE_AMPEREONE}, // Ampere AmpereOne + {PCI_VENDOR_ID_AMPERE, 0xE207, CS_AMPERE_AMPEREONE}, // Ampere AmpereOne // last element must have chipset CS_UNKNOWN (zero) {0, 0, CS_UNKNOWN} diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/arch/nvalloc/common/inc/nvdevid.h nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/arch/nvalloc/common/inc/nvdevid.h --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/arch/nvalloc/common/inc/nvdevid.h 2023-10-25 20:20:26.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/arch/nvalloc/common/inc/nvdevid.h 1970-01-01 00:00:00.000000000 +0000 @@ -1,702 +0,0 @@ -/* - * SPDX-FileCopyrightText: Copyright (c) 200-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. - * SPDX-License-Identifier: MIT - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER - * DEALINGS IN THE SOFTWARE. - */ - -#ifndef NVDEVID_H -#define NVDEVID_H - - - -/**************** Resource Manager Defines and Structures ******************\ -* * -* Private device ids defines - only defines ! * -* * -\***************************************************************************/ - -/////////////////////////////////////////////////////////////////////////////////////////// -// -// VENDOR/SUBVENDOR IDS -// XXX Cleanup to do: change PCI_VENDOR_* to NV_PCI_SUBID_VENDOR_* -// -/////////////////////////////////////////////////////////////////////////////////////////// -#define NV_PCI_SUBID_VENDOR 15:0 /* RW--F */ -#define NV_PCI_SUBID_VENDOR_AMD 0x1022 -#define NV_PCI_SUBID_VENDOR_ALI 0x10B9 -#define NV_PCI_SUBID_VENDOR_NVIDIA 0x10DE -#define NV_PCI_SUBID_VENDOR_INTEL 0x8086 -#define NV_PCI_SUBID_VENDOR_VIA 0x1106 -#define NV_PCI_SUBID_VENDOR_RCC 0x1166 -#define NV_PCI_SUBID_VENDOR_MICRON_1 0x1042 -#define NV_PCI_SUBID_VENDOR_MICRON_2 0x1344 -#define NV_PCI_SUBID_VENDOR_APPLE 0x106B -#define NV_PCI_SUBID_VENDOR_SIS 0x1039 -#define NV_PCI_SUBID_VENDOR_ATI 0x1002 -#define NV_PCI_SUBID_VENDOR_TRANSMETA 0x1279 -#define NV_PCI_SUBID_VENDOR_HP 0x103C -#define NV_PCI_SUBID_VENDOR_DELL 0x1028 -#define NV_PCI_SUBID_VENDOR_FUJITSU 0x10cf -#define NV_PCI_SUBID_VENDOR_ASUS 0x1043 -#define NV_PCI_SUBID_VENDOR_MSI 0x1462 -#define NV_PCI_SUBID_VENDOR_FOXCONN 0x105B -#define NV_PCI_SUBID_VENDOR_ECS 0x1019 -#define NV_PCI_SUBID_VENDOR_DFI_1 0x106E -#define NV_PCI_SUBID_VENDOR_TOSHIBA 0x1179 -#define NV_PCI_SUBID_VENDOR_DFI_2 0x15BD -#define NV_PCI_SUBID_VENDOR_ACER 0x1025 -#define NV_PCI_SUBID_VENDOR_GIGABYTE 0x1458 -#define NV_PCI_SUBID_VENDOR_EVGA 0x3842 -#define NV_PCI_SUBID_VENDOR_BROADCOM 0x1166 -#define NV_PCI_SUBID_VENDOR_SUPERMICRO 0x15D9 -#define NV_PCI_SUBID_VENDOR_BIOSTAR 0x1565 -#define NV_PCI_SUBID_VENDOR_XFX 0x1682 -#define NV_PCI_SUBID_VENDOR_PCPARTNER 0x19DA -#define NV_PCI_SUBID_VENDOR_LENOVO 0x17AA -#define NV_PCI_SUBID_VENDOR_FSC 0x1734 -#define NV_PCI_SUBID_VENDOR_FTS 0x1734 -#define NV_PCI_SUBID_VENDOR_COLORFUL 0x7377 -#define NV_PCI_SUBID_VENDOR_ASROCK 0x1849 -#define NV_PCI_SUBID_VENDOR_SHUTTLE 0x1297 -#define NV_PCI_SUBID_VENDOR_CLEVO 0x1558 -#define NV_PCI_SUBID_VENDOR_PEGATRON 0x1B0A -#define NV_PCI_SUBID_VENDOR_JETWAY 0x16F3 -#define NV_PCI_SUBID_VENDOR_HIGHGRADE 0x1C6C -#define NV_PCI_SUBID_VENDOR_GALAXY 0x1B4C -#define NV_PCI_SUBID_VENDOR_ZOTAC 0x19DA -#define NV_PCI_SUBID_VENDOR_ARIMA 0x161F -#define NV_PCI_SUBID_VENDOR_BFG 0x19F1 -#define NV_PCI_SUBID_VENDOR_SONY 0x104D -#define NV_PCI_SUBID_VENDOR_BITLAND 0x1642 -#define NV_PCI_SUBID_VENDOR_PC_PARTNER 0x174B -#define NV_PCI_SUBID_VENDOR_NZXT 0x1D96 - -// XXX CKEANUP TO REMOVE IN FAVOR OF NV_PCI_SUBID_VENDOR_* -#define PCI_VENDOR_ID_AMD 0x1022 -#define PCI_VENDOR_ID_ALI 0x10B9 -#define PCI_VENDOR_ID_NVIDIA 0x10DE -#define PCI_VENDOR_ID_INTEL 0x8086 -#define PCI_VENDOR_ID_VIA 0x1106 -#define PCI_VENDOR_ID_RCC 0x1166 -#define PCI_VENDOR_ID_MICRON_1 0x1042 -#define PCI_VENDOR_ID_MICRON_2 0x1344 -#define PCI_VENDOR_ID_APPLE 0x106B -#define PCI_VENDOR_ID_SIS 0x1039 -#define PCI_VENDOR_ID_ATI 0x1002 -#define PCI_VENDOR_ID_TRANSMETA 0x1279 -#define PCI_VENDOR_ID_HP 0x103C -#define PCI_VENDOR_ID_DELL 0x1028 -#define PCI_VENDOR_ID_FUJITSU 0x10cf -#define PCI_VENDOR_ID_ASUS 0x1043 -#define PCI_VENDOR_ID_MSI 0x1462 -#define PCI_VENDOR_ID_FOXCONN 0x105B -#define PCI_VENDOR_ID_ECS 0x1019 -#define PCI_VENDOR_ID_DFI_1 0x106E -#define PCI_VENDOR_ID_TOSHIBA 0x1179 -#define PCI_VENDOR_ID_DFI_2 0x15BD -#define PCI_VENDOR_ID_ACER 0x1025 -#define PCI_VENDOR_ID_GIGABYTE 0x1458 -#define PCI_VENDOR_ID_EVGA 0x3842 -#define PCI_VENDOR_ID_BROADCOM 0x1166 -#define PCI_VENDOR_ID_SUPERMICRO 0x15D9 -#define PCI_VENDOR_ID_BIOSTAR 0x1565 -#define PCI_VENDOR_ID_XFX 0x1682 -#define PCI_VENDOR_ID_PCPARTNER 0x19DA -#define PCI_VENDOR_ID_LENOVO 0x17AA -#define PCI_VENDOR_ID_FSC 0x1734 -#define PCI_VENDOR_ID_FTS 0x1734 -#define PCI_VENDOR_ID_COLORFUL 0x7377 -#define PCI_VENDOR_ID_ASROCK 0x1849 -#define PCI_VENDOR_ID_SHUTTLE 0x1297 -#define PCI_VENDOR_ID_CLEVO 0x1558 -#define PCI_VENDOR_ID_PEGATRON 0x1B0A -#define PCI_VENDOR_ID_JETWAY 0x16F3 -#define PCI_VENDOR_ID_HIGHGRADE 0x1C6C -#define PCI_VENDOR_ID_GALAXY 0x1B4C -#define PCI_VENDOR_ID_ZOTAC 0x19DA -#define PCI_VENDOR_ID_ARIMA 0x161F -#define PCI_VENDOR_ID_PC_PARTNER 0x174B -#define PCI_VENDOR_ID_APM 0x10E8 -#define PCI_VENDOR_ID_IBM 0x1014 -#define PCI_VENDOR_ID_NZXT 0x1D96 -#define PCI_VENDOR_ID_MARVELL 0x177D -#define PCI_VENDOR_ID_REDHAT 0x1B36 -#define PCI_VENDOR_ID_AMPERE 0x1DEF -#define PCI_VENDOR_ID_HUAWEI 0x19E5 -#define PCI_VENDOR_ID_MELLANOX 0x15B3 -#define PCI_VENDOR_ID_AMAZON 0x1D0F -#define PCI_VENDOR_ID_CADENCE 0x17CD -#define PCI_VENDOR_ID_ARM 0x13B5 -#define PCI_VENDOR_ID_HYGON 0x1D94 -#define PCI_VENDOR_ID_ALIBABA 0x1DED - -#define NV_PCI_DEVID_DEVICE 31:16 /* RW--F */ -#define NV_PCI_SUBID_DEVICE 31:16 /* RW--F */ - -/////////////////////////////////////////////////////////////////////////////////////////// -// -// GPU DEVICE IDS -// -/////////////////////////////////////////////////////////////////////////////////////////// - -#define NV_PCI_DEVID_DEVICE_PG171_SKU200_PG179_SKU220 0x25B6 /* NVIDIA A16 / NVIDIA A2 */ -#define NV_PCI_DEVID_DEVICE_PG189_SKU600 0x1EBA - -/////////////////////////////////////////////////////////////////////////////////////////// -// -// SUBDEVICE IDs -// -/////////////////////////////////////////////////////////////////////////////////////////// - -// A16 -#define NV_PCI_SUBID_DEVICE_PG171_SKU200 0x14A9 - -/////////////////////////////////////////////////////////////////////////////////////////// -// -// CHIPSET IDs -// -/////////////////////////////////////////////////////////////////////////////////////////// -// Desktop flavor of X58 -#define X58_DESKTOP_DEVIDS 0x3400, 0x3405 -// Mobile version of X58 -#define X58_MOBILE_DEVID 0x3405 -#define X58_MOBILE_CLEVO_7200_SSDEVID 0x7200 - -// Sandy bridge CLEVO platform -#define SANDYBRIDGE_P180HM_SSDEVID 0x8000 -#define SandyBridge_E_X79_P270WM_SSDEVID 0x270 -#define IvyBridge_Z75_P370EM_SSDEVID 0x371 - -// Device ID's of Devices present on Patsburg's PCIE bus. -#define PATSBURG_PCIE_DEVICE_MIN_DEVID 0x1D10 -#define PATSBURG_PCIE_DEVICE_MAX_DEVID 0x1D1F -#define PATSBURG_PCIE_DEVICE_DEVID 0x244E - -//Tylersburg Congurations -#define TYLERSBURG_DEVID 0x3406 - -// Intel Grantsdale definitions -#define DEVICE_ID_INTEL_2580_HOST_BRIDGE 0x2580 -#define DEVICE_ID_INTEL_2581_ROOT_PORT 0x2581 - -// Intel Alderwood definitions -#define DEVICE_ID_INTEL_2584_HOST_BRIDGE 0x2584 -#define DEVICE_ID_INTEL_2585_ROOT_PORT 0x2585 - -// Intel Alviso definitions -#define DEVICE_ID_INTEL_2590_HOST_BRIDGE 0x2590 -#define DEVICE_ID_INTEL_2591_ROOT_PORT 0x2591 - -// Intel Tumwater definitions -#define DEVICE_ID_INTEL_359E_HOST_BRIDGE 0x359E -#define DEVICE_ID_INTEL_3597_ROOT_PORT 0x3597 - -// Intel Stoakley definitions -#define INTEL_4000_SUBDEVICE_ID 0x021D - -// Intel SkullTrail definitions -#define INTEL_4003_SUBDEVICE_ID 0x5358 - -// Intel Core I7 CPU -#define INTEL_QUICKPATH_SYSTEM_ADDRESS_DECODER_I7 0x2C01 - -// Intel Core I5 CPU Lynnfield -#define INTEL_QUICKPATH_SYSTEM_ADDRESS_DECODER_I5_L 0x2C81 -#define INTEL_LYNNFIELD_ROOTPORT_CPU1 0xD138 -#define INTEL_LYNNFIELD_ROOTPORT_CPU2 0xD13A - -// Intel Core I5 CPU Auburndale -#define INTEL_QUICKPATH_SYSTEM_ADDRESS_DECODER_I5_A 0x2D41 - -// Intel Core I5 CPU 650 -#define INTEL_QUICKPATH_SYSTEM_ADDRESS_DECODER_I5_6 0x2D01 - -// Intel Poulsbo definitions -#define DEVICE_ID_INTEL_8100_HOST_BRIDGE 0x8100 -#define DEVICE_ID_INTEL_8110_ROOT_PORT 0x8110 -#define DEVICE_ID_INTEL_8112_ROOT_PORT 0x8112 - -// Intel TunnelCreek definitions -#define DEVICE_ID_INTEL_8180_ROOT_PORT 0x8180 -#define DEVICE_ID_INTEL_8181_ROOT_PORT 0x8181 -#define DEVICE_ID_INTEL_8184_ROOT_PORT 0x8184 -#define DEVICE_ID_INTEL_8185_ROOT_PORT 0x8185 - -// Intel I/O Hub definitions -#define DEVICE_ID_INTEL_3408_ROOT_PORT 0x3408 -#define DEVICE_ID_INTEL_3411_ROOT_PORT 0x3411 -#define DEVICE_ID_INTEL_3420_ROOT_PORT 0x3420 -#define DEVICE_ID_INTEL_3421_ROOT_PORT 0x3421 - -// Intel SandyBridge IIO definitions -#define DEVICE_ID_INTEL_3C02_ROOT_PORT 0x3c02 -#define DEVICE_ID_INTEL_3C03_ROOT_PORT 0x3c03 -#define DEVICE_ID_INTEL_3C04_ROOT_PORT 0x3c04 -#define DEVICE_ID_INTEL_3C05_ROOT_PORT 0x3c05 -#define DEVICE_ID_INTEL_3C06_ROOT_PORT 0x3c06 -#define DEVICE_ID_INTEL_3C07_ROOT_PORT 0x3c07 -#define DEVICE_ID_INTEL_3C08_ROOT_PORT 0x3c08 -#define DEVICE_ID_INTEL_3C09_ROOT_PORT 0x3c09 -#define DEVICE_ID_INTEL_3C0A_ROOT_PORT 0x3c0a -#define DEVICE_ID_INTEL_3C0B_ROOT_PORT 0x3c0b - -// Intel Haswell-E definitions -#define DEVICE_ID_INTEL_2F00_HOST_BRIDGE 0x2f00 -#define DEVICE_ID_INTEL_2F01_ROOT_PORT 0x2f01 -#define DEVICE_ID_INTEL_2F02_ROOT_PORT 0x2f02 -#define DEVICE_ID_INTEL_2F03_ROOT_PORT 0x2f03 -#define DEVICE_ID_INTEL_2F04_ROOT_PORT 0x2f04 -#define DEVICE_ID_INTEL_2F05_ROOT_PORT 0x2f05 -#define DEVICE_ID_INTEL_2F06_ROOT_PORT 0x2f06 -#define DEVICE_ID_INTEL_2F07_ROOT_PORT 0x2f07 -#define DEVICE_ID_INTEL_2F08_ROOT_PORT 0x2f08 -#define DEVICE_ID_INTEL_2F09_ROOT_PORT 0x2f09 -#define DEVICE_ID_INTEL_2F0A_ROOT_PORT 0x2f0a -#define DEVICE_ID_INTEL_2F0B_ROOT_PORT 0x2f0b - -#define DEVICE_ID_INTEL_0C01_ROOT_PORT 0x0c01 - -// Intel IvyTown definitions - -#define DEVICE_ID_INTEL_0E02_ROOT_PORT 0x0e02 -#define DEVICE_ID_INTEL_0E03_ROOT_PORT 0x0e03 -#define DEVICE_ID_INTEL_0E04_ROOT_PORT 0x0e04 -#define DEVICE_ID_INTEL_0E05_ROOT_PORT 0x0e05 -#define DEVICE_ID_INTEL_0E06_ROOT_PORT 0x0e06 -#define DEVICE_ID_INTEL_0E07_ROOT_PORT 0x0e07 -#define DEVICE_ID_INTEL_0E08_ROOT_PORT 0x0e08 -#define DEVICE_ID_INTEL_0E09_ROOT_PORT 0x0e09 -#define DEVICE_ID_INTEL_0E0A_ROOT_PORT 0x0e0a -#define DEVICE_ID_INTEL_0E0B_ROOT_PORT 0x0e0b -// Intel Ivy Bridge E definitions -#define DEVICE_ID_INTEL_0E00_HOST_BRIDGE 0x0E00 - -// Intel Haswell definitions -#define DEVICE_ID_INTEL_0C00_HASWELL_HOST_BRIDGE 0x0C00 -#define DEVICE_ID_INTEL_0C04_HASWELL_HOST_BRIDGE 0x0C04 - -// Intel PCH definitions -#define DEVICE_ID_INTEL_9D10_PCH_BRIDGE 0x9d10 -#define DEVICE_ID_INTEL_9D18_PCH_BRIDGE 0x9d18 -#define DEVICE_ID_INTEL_A117_PCH_BRIDGE 0xa117 -#define DEVICE_ID_INTEL_A118_PCH_BRIDGE 0xa118 -#define DEVICE_ID_INTEL_9C98_PCH_BRIDGE 0x9c98 - -// Intel Broadwell definitions -#define DEVICE_ID_INTEL_6F00_HOST_BRIDGE 0x6f00 -#define DEVICE_ID_INTEL_6F01_ROOT_PORT 0x6f01 -#define DEVICE_ID_INTEL_6F02_ROOT_PORT 0x6f02 -#define DEVICE_ID_INTEL_6F03_ROOT_PORT 0x6f03 -#define DEVICE_ID_INTEL_6F04_ROOT_PORT 0x6f04 -#define DEVICE_ID_INTEL_6F05_ROOT_PORT 0x6f05 -#define DEVICE_ID_INTEL_6F06_ROOT_PORT 0x6f06 -#define DEVICE_ID_INTEL_6F07_ROOT_PORT 0x6f07 -#define DEVICE_ID_INTEL_6F08_ROOT_PORT 0x6f08 -#define DEVICE_ID_INTEL_6F09_ROOT_PORT 0x6f09 -#define DEVICE_ID_INTEL_6F0A_ROOT_PORT 0x6f0A -#define DEVICE_ID_INTEL_6F0B_ROOT_PORT 0x6f0B -#define DEVICE_ID_INTEL_1601_ROOT_PORT 0x1601 -#define DEVICE_ID_INTEL_1605_ROOT_PORT 0x1605 -#define DEVICE_ID_INTEL_1609_ROOT_PORT 0x1609 -#define DEVICE_ID_INTEL_BROADWELL_U_HOST_BRIDGE 0x1604 -#define DEVICE_ID_INTEL_BROADWELL_H_HOST_BRIDGE 0x1614 - -// Intel Skylake definitions -#define DEVICE_ID_INTEL_1901_ROOT_PORT 0x1901 -#define DEVICE_ID_INTEL_1905_ROOT_PORT 0x1905 -#define DEVICE_ID_INTEL_1909_ROOT_PORT 0x1909 -#define DEVICE_ID_INTEL_SKYLAKE_U_HOST_BRIDGE 0x1904 -#define DEVICE_ID_INTEL_SKYLAKE_S_HOST_BRIDGE 0x191F -#define DEVICE_ID_INTEL_SKYLAKE_H_HOST_BRIDGE 0x1910 - -// Intel Skylake-E definitions -#define DEVICE_ID_INTEL_2030_ROOT_PORT 0x2030 -#define DEVICE_ID_INTEL_2033_ROOT_PORT 0x2033 - -// Intel Kabylake definitions -#define DEVICE_ID_INTEL_KABYLAKE_U_HOST_BRIDGE 0x5904 -#define DEVICE_ID_INTEL_KABYLAKE_H_HOST_BRIDGE 0x5910 - -// AMD Matisse, Rome definitions -#define DEVICE_ID_AMD_1483_ROOT_PORT 0x1483 -// AMD Castle Peak definition -#define DEVICE_ID_AMD_1480_ROOT_PORT 0x1480 -// AMD Renoir-H definition -#define DEVICE_ID_AMD_1630_ROOT_PORT 0x1630 - -// Dell SkullTrail definitions -#define DELL_4003_SUBDEVICE_ID 0x021D - -// Dell Quicksilver MLK definitions -#define DELL_0040_SUBDEVICE_ID 0x043a - -// HP Tylersburg definitions -#define TYLERSBURG_Z800_SSDEVID 0x130B - -// HP Romley definitions -#define ROMLEY_Z820_SSDEVID 0x158B -#define ROMLEY_Z620_SSDEVID 0x158A -#define ROMLEY_Z420_SSDEVID 0x1589 - -// HP Grantley definitions -#define GRANTLEY_Z840_SSDEVID 0x2129 -#define GRANTLEY_Z640_SSDEVID 0x212A -#define GRANTLEY_Z440_SSDEVID 0x212B - -// HP PURELY definitions -#define HP_QUADRO_Z4GEN4_DEVID 0xA2D2 -#define PURLEY_Z8GEN4_SSDEVID 0x81C7 -#define PURLEY_Z6GEN4_SSDEVID 0x81C6 -#define PURLEY_Z4GEN4_SSDEVID 0x81C5 - -// Lenovo Romley definitions -#define ROMLEY_C30_SSDEVID 0x1028 -#define ROMLEY_D30_SSDEVID 0x1027 -#define ROMLEY_S30_SSDEVID 0x1026 - -// Dell Romley definitions -#define ROMLEY_T7600_SSDEVID 0x0495 -#define ROMLEY_T5600_SSDEVID 0x0496 -#define ROMLEY_T3600_SSDEVID 0x0497 - -// Dell Romley + IVB-EP CPU Refresh -#define IVYTOWN_T7610_SSDEVID 0x05D4 -#define IVYTOWN_T5610_SSDEVID 0x05D3 - -// Dell Romley (Ipanema) -#define ROMLEY_R7610_SSDEVID 0x05A1 - -// FTS Romley definitions -#define ROMLEY_R920_SSDEVID 0x11B6 - -// Lenovo Grantley (Messi, Pele, Ronaldo) -#define GRANTLEY_V40_SSDEVID 0x1031 -#define GRANTLEY_D40_SSDEVID 0x1030 -#define GRANTLEY_S40_SSDEVID 0x102F - -// Dell Grantley (Avalon) -#define GRANTLEY_T7810_SSDEVID 0x0618 -#define GRANTLEY_T7910_SSDEVID 0x0619 - -// Lenovo Purley (Nile, Volga) -#define PURLEY_P920_SSDEVID 0x1038 -#define PURLEY_P720_SSDEVID 0x1037 -#define PURLEY_P520_SSDEVID 0x1036 - -// Lenovo P520c -#define LENOVO_P520C_SSDEVID 0x103C - -// Dell Purley(Matira) -#define PURLEY_MATIRA3X_DEVID 0xA2D2 -#define PURLEY_MATIRA3X_SSDEVID 0x08B1 -#define PURLEY_MATIRA3_SSDEVID 0x0738 -#define PURLEY_MATIRA5_SSDEVID 0x0739 -#define PURLEY_MATIRA7_SSDEVID 0x073A - -//FTS Grantley -#define GRANTLEY_R940_SSDEVID 0x1201 - -//FTS Purley -#define PURLEY_R970_SSDEVID 0x1230 -#define PURLEY_M770_SSDEVID 0x1231 - -// HP Arrandale, Clarksfield, X58 workstation definitions -#define ARRANDALE_Z200SFF_SSDEVID 0x304A -#define CLARKSFIELD_Z200_SSDEVID 0x170B -#define X58_Z400_SSDEVID 0x1309 - -// GIGABYTE Sniper 3 (Z77) -#define GIGABYTE_SNIPER_3_SSDEVID_1 0x5000 -#define GIGABYTE_SNIPER_3_SSDEVID_2 0x5001 - -// Supermicro Quadro VCA definitions -#define SUPERMICRO_QUADRO_VCA_DEVID 0x8D44 -#define SUPERMICRO_QUADRO_VCA_SSDEVID 0x7270 - -// Supermicro SYS-4027GR-TRT -#define SUPERMICRO_SYS_4027GR_TRT_DEVID 0x1D41 -#define SUPERMICRO_SYS_4027GR_TRT_SSDEVID 0x0732 - -// Supermicro SYS-4029GP-TRT2 -#define SUPERMICRO_SYS_4029GP_TRT2_DEVID 0xA1C2 -#define SUPERMICRO_SYS_4029GP_TRT2_SSDEVID 0x7270 - -// Asus Quadro BOXX definitions -#define ASUS_QUADRO_BOXX_DEVID 0x8D44 -#define ASUS_QUADRO_BOXX_SSDEVID 0x85F6 - -// APEXX8 Quadro BOXX definitions -#define APEXX8_QUADRO_BOXX_DEVID 0xA2D3 -#define APEXX8_QUADRO_BOXX_SSDEVID 0x098e - -// APEXX5 Quadro BOXX definitions -#define APEXX5_QUADRO_BOXX_DEVID 0xA2D3 -#define APEXX5_QUADRO_BOXX_SSDEVID 0x1000 - -// ASUS X99-E-10G -#define ASUS_X99_E_10G_SSDEVID 0x8600 - -// VIA definitions -#define DEVICE_ID_VIA_VT8369B_HOST_BRIDGE 0x0308 - -// Foxconn Einstein 64 [8086:a1c1][105b:7270] -#define FOXCONN_EINSTEIN_64_DEVID 0xA1C1 -#define FOXCONN_EINSTEIN_64_SSDEVID 0x7270 - -// Tyan Workstation -#define TYAN_B7100_DEVID 0xA1C1 -#define TYAN_B7100_SSDEVID 0x7270 - -// ESC 4000 Series Workstation -#define ESC_4000_G4_DEVID 0xA1C1 -#define ESC_4000_G4_SSDEVID 0x871E - -// Lenovo Tomcat Workstation -#define LENOVO_TOMCAT_DEVID 0x1B81 -#define LENOVO_TOMCAT_SSDEVID 0x104e - -// NVIDIA C51 -#define NVIDIA_C51_DEVICE_ID_MIN 0x2F0 -#define NVIDIA_C51_ULDT_CFG_0_DEVICE_ID_0 0x2F0 -#define NVIDIA_C51_ULDT_CFG_0_DEVICE_ID_1 0x2F1 -#define NVIDIA_C51_ULDT_CFG_0_DEVICE_ID_2 0x2F2 -#define NVIDIA_C51_ULDT_CFG_0_DEVICE_ID_3 0x2F3 -#define NVIDIA_C51_ULDT_CFG_0_DEVICE_ID_IGPU_DISABLE_0 0x2F4 -#define NVIDIA_C51_ULDT_CFG_0_DEVICE_ID_IGPU_DISABLE_1 0x2F5 -#define NVIDIA_C51_ULDT_CFG_0_DEVICE_ID_IGPU_DISABLE_2 0x2F6 -#define NVIDIA_C51_ULDT_CFG_0_DEVICE_ID_IGPU_DISABLE_3 0x2F7 -#define NVIDIA_C51_DEVICE_ID_MAX 0x2F7 - -// NVIDIA MCP55 -#define NVIDIA_MCP55_ULDT_CFG_0_DEVICE_ID_DEFAULT 0x0369 - -// NVIDIA MCP61 -#define NVIDIA_MCP61_ULDT_CFG_0_DEVICE_ID_DEFAULT 0x03EA -#define NVIDIA_MCP61_ULDT_CFG_0_DEVICE_ID_PA 0x03E2 - -// NVIDIA C55 -#define NVIDIA_C55_CPU_PCI_0_DEVICE_ID_PRO 0x03A0 -#define NVIDIA_C55_CPU_PCI_0_DEVICE_ID_PRO 0x03A0 -#define NVIDIA_C55_CPU_PCI_0_DEVICE_ID_SLIX16 0x03A1 -#define NVIDIA_C55_CPU_PCI_0_DEVICE_ID_SLI 0x03A3 -#define NVIDIA_C55_CPU_PCI_0_DEVICE_ID_U 0x03A2 - -// NVIDIA MCP65 -#define NVIDIA_MCP65_ULDT_CFG_0_DEVICE_ID_DEFAULT 0x0444 - -// NVIDIA MCP67/MCP68 -#define NVIDIA_MCP67_ULDT_CFG_0_DEVICE_ID_DEFAULT 0x0547 - -// NVIDIA MCP73 -#define NVIDIA_MCP73_CPU_PCI_0_DEVICE_ID_PV 0x07C0 -#define NVIDIA_MCP73_CPU_PCI_0_DEVICE_ID_O 0x07C1 -#define NVIDIA_MCP73_CPU_PCI_0_DEVICE_ID_S 0x07C2 -#define NVIDIA_MCP73_CPU_PCI_0_DEVICE_ID_V 0x07C3 -#define NVIDIA_MCP73_CPU_PCI_0_DEVICE_ID_RSVD_0 0x07C4 -#define NVIDIA_MCP73_CPU_PCI_0_DEVICE_ID_RSVD_1 0x07C5 -#define NVIDIA_MCP73_CPU_PCI_0_DEVICE_ID_RSVD_2 0x07C6 -#define NVIDIA_MCP73_CPU_PCI_0_DEVICE_ID_D 0x07C7 - -// NVIDIA C73 -#define NVIDIA_C73_CPU_PCI_0_DEVICE_ID_SLI2 0x0800 -#define NVIDIA_C73_CPU_PCI_0_DEVICE_ID_SLI_ALL 0x0801 -#define NVIDIA_C73_CPU_PCI_0_DEVICE_ID_SLIX8 0x0802 -#define NVIDIA_C73_CPU_PCI_0_DEVICE_ID_U 0x0803 -#define NVIDIA_C73_CPU_PCI_0_DEVICE_ID_RESERVED_0 0x0804 -#define NVIDIA_C73_CPU_PCI_0_DEVICE_ID_RESERVED_1 0x0805 -#define NVIDIA_C73_CPU_PCI_0_DEVICE_ID_RESERVED_2 0x0806 -#define NVIDIA_C73_CPU_PCI_0_DEVICE_ID_RESERVED_3 0x0807 - -// NVIDIA MCP77/78 -#define NVIDIA_MCP77_ULDT_CFG_0_DEVICE_ID_DEFAULT 0x0754 -#define NVIDIA_MCP77_ULDT_CFG_0_DEVICE_ID_1 0x0755 -#define NVIDIA_MCP77_ULDT_CFG_0_DEVICE_ID_2 0x0756 -#define NVIDIA_MCP77_ULDT_CFG_0_DEVICE_ID_3 0x0757 -#define NVIDIA_MCP77_MCP_SM_CFG_0_DEVICE_ID_UNIT_SM 0x0752 - -// NVIDIA MCP79/7A -#define NVIDIA_MCP79_CPU_PCI_0_DEVICE_ID_DEFAULT 0x0A80 -#define NVIDIA_MCP79_CPU_PCI_0_DEVICE_ID_SLIX16 0x0A81 -#define NVIDIA_MCP79_CPU_PCI_0_DEVICE_ID_SLI 0x0A82 -#define NVIDIA_MCP79_CPU_PCI_0_DEVICE_ID_U 0x0A83 -#define NVIDIA_MCP79_CPU_PCI_0_DEVICE_ID_GM 0x0A84 -#define NVIDIA_MCP79_CPU_PCI_0_DEVICE_ID_GVM 0x0A85 -#define NVIDIA_MCP79_MCP_SM_CFG_0_DEVICE_ID_UNIT_SM 0x0AA2 - -// NVIDIA MCP89/P83 -#define NVIDIA_MCP89_CPU_PCI_0_DEVICE_ID_DEFAULT 0x00000D60 - -/////////////////////////////////////////////////////////////////////////////////////////// -// -// enumeration of chipset families -// -/////////////////////////////////////////////////////////////////////////////////////////// - -// -// When adding a variable to the following enum, please -// add it also to the following chipset_names[]. -// -enum { - CS_UNKNOWN = 0x0000, - CS_UNKNOWN_PCIE = 0x1000 -, CS_INTEL_2580 -, CS_INTEL_2584 -, CS_INTEL_2588 -, CS_INTEL_2590 -, CS_INTEL_25E0 -, CS_INTEL_29X0 -, CS_INTEL_29E0 -, CS_INTEL_359E -, CS_INTEL_4000 -, CS_INTEL_4003 -, CS_INTEL_3400 -, CS_INTEL_3B42 -, CS_INTEL_2770 -, CS_INTEL_2774 -, CS_INTEL_277C -, CS_INTEL_2A40 -, CS_INTEL_2E00 -, CS_INTEL_0040 -, CS_INTEL_1C10 -, CS_INTEL_1C46 -, CS_INTEL_1C49 -, CS_INTEL_1D40 -, CS_INTEL_8D47 -, CS_INTEL_1E10 -, CS_INTEL_8C4B -, CS_INTEL_8CC4 -, CS_INTEL_A145 -, CS_INTEL_A2C5 -, CS_INTEL_A242 -, CS_INTEL_A2D2 -, CS_INTEL_A2C9 -, CS_INTEL_A301 -, CS_INTEL_0685 -, CS_INTEL_4381 -, CS_INTEL_7A82 -, CS_NVIDIA_CK804 -, CS_NVIDIA_C19 -, CS_NVIDIA_C51 -, CS_NVIDIA_MCP55 -, CS_NVIDIA_MCP61 -, CS_NVIDIA_C55 -, CS_NVIDIA_MCP65 -, CS_NVIDIA_MCP67 -, CS_NVIDIA_MCP73 -, CS_NVIDIA_C73 -, CS_NVIDIA_MCP77 -, CS_NVIDIA_MCP79 -, CS_NVIDIA_MCP89 -, CS_NVIDIA_TEGRA3 -, CS_SIS_649 -, CS_SIS_656 -, CS_ATI_RS400 -, CS_ATI_RS400_A21 -, CS_ATI_RS480 -, CS_ATI_RS480_A21 -, CS_AMD_RS780 -, CS_VIA_VT8369B -, CS_ATI_FX790 -, CS_ATI_RD850 -, CS_ATI_RD870 -, CS_ATI_RD890 -, CS_ATI_FX890 -, CS_ATI_RX780 -, CS_ATI_FX990 -, CS_AMD_GX890 -, CS_AMD_X370 -, CS_VIA_VX900 -, CS_APM_STORM -, CS_IBM_VENICE -, CS_NVIDIA_T124 -, CS_NVIDIA_T210 -, CS_NVIDIA_T186 -, CS_NVIDIA_T194 -, CS_NVIDIA_T234 -, CS_NVIDIA_T23x -, CS_MARVELL_THUNDERX2 -, CS_REDHAT_QEMU -, CS_AMPERE_EMAG -, CS_HUAWEI_KUNPENG920 -, CS_MELLANOX_BLUEFIELD -, CS_AMAZON_GRAVITRON2 -, CS_FUJITSU_A64FX -, CS_AMPERE_ALTRA -, CS_ARM_NEOVERSEN1 -, CS_MARVELL_OCTEON_CN96XX -, CS_MARVELL_OCTEON_CN98XX -, CS_INTEL_C620 -, CS_HYGON_C86 -, CS_PHYTIUM_S2500 -, CS_MELLANOX_BLUEFIELD2 -, CS_ALIBABA_YITIAN -, CS_INTEL_1B81 -, CS_INTEL_18DC -, CS_INTEL_7A04 -, CS_MAX_PCIE -}; - -enum { - RP_UNKNOWN = 0 -, RP_BROADCOM_HT2100 -, RP_INTEL_2581 -, RP_INTEL_2585 -, RP_INTEL_2589 -, RP_INTEL_2591 -, RP_INTEL_3597 -, RP_INTEL_2775 -, RP_INTEL_2771 -, RP_INTEL_8110 -, RP_INTEL_8112 -, RP_INTEL_8180 -, RP_INTEL_8181 -, RP_INTEL_8184 -, RP_INTEL_8185 -, RP_INTEL_3C02 -, RP_INTEL_3C03 -, RP_INTEL_3C04 -, RP_INTEL_3C05 -, RP_INTEL_3C06 -, RP_INTEL_3C07 -, RP_INTEL_3C08 -, RP_INTEL_3C09 -, RP_INTEL_3C0A -, RP_INTEL_3C0B -, RP_INTEL_2F04 -, RP_INTEL_2F08 -, RP_INTEL_0C01 -, RP_INTEL_1601 -, RP_INTEL_1605 -, RP_INTEL_1609 -, RP_INTEL_1901 -, RP_INTEL_1905 -, RP_INTEL_1909 -, RP_INTEL_5904 -, RP_NVIDIA_CK804 -, RP_NVIDIA_C19 -, RP_NVIDIA_C51 -, RP_NVIDIA_MCP55 -, RP_NVIDIA_MCP61 -, RP_NVIDIA_C55 -, RP_NVIDIA_MCP65 -}; - -#endif //NVDEVID_H - diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/arch/nvalloc/common/inc/nvpcie.h nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/arch/nvalloc/common/inc/nvpcie.h --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/arch/nvalloc/common/inc/nvpcie.h 2023-10-25 20:20:26.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/arch/nvalloc/common/inc/nvpcie.h 2024-03-05 22:12:44.000000000 +0000 @@ -24,6 +24,8 @@ #ifndef NVPCIE_H #define NVPCIE_H + + /**************** Resource Manager Defines and Structures ******************\ * * * Private PCI Express related defines and structures. * @@ -53,6 +55,8 @@ #define PCI_INVALID_SUBVENDORID 0xFFFF #define PCI_INVALID_SUBDEVICEID 0xFFFF +#define PCI_IS_VENDORID_VALID(id) (((id) != 0x0000) && ((id) != 0xFFFF)) + #define PCI_CLASS_BRIDGE_DEV 0x06 #define PCI_SUBCLASS_BR_HOST 0x00 #define PCI_MULTIFUNCTION 0x80 @@ -470,7 +474,8 @@ CL_PCIE_DC_CAPABILITY_MAP_ENTRY entries[PCI_MAX_CAPS]; } CL_PCIE_DC_CAPABILITY_MAP; -struct OBJCL; +typedef struct OBJCL OBJCL; +typedef struct OBJGPU OBJGPU; // root port setup functions NV_STATUS Broadcom_HT2100_setupFunc(OBJGPU *, OBJCL*); @@ -494,6 +499,6 @@ NV_STATUS AMD_RP1483_setupFunc(OBJGPU *, OBJCL*); // Determines if the GPU is in a multi-GPU board based on devid checks -NvBool gpuIsMultiGpuBoard(OBJGPU *, NvBool *); +NvBool gpuIsMultiGpuBoard(OBJGPU *); #endif // NVPCIE_H diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/arch/nvalloc/common/inc/oob/smbpbi.h nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/arch/nvalloc/common/inc/oob/smbpbi.h --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/arch/nvalloc/common/inc/oob/smbpbi.h 2023-10-25 20:20:27.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/arch/nvalloc/common/inc/oob/smbpbi.h 2024-03-05 22:12:44.000000000 +0000 @@ -112,6 +112,7 @@ #define NV_MSGBOX_CMD_ARG1_POWER_TOTAL 0x00000000 #define NV_MSGBOX_CMD_ARG1_SMBPBI_POWER 0x00000001 #define NV_MSGBOX_CMD_ARG1_POWER_FB 0x00000002 +#define NV_MSGBOX_CMD_ARG1_POWER_MODULE 0x00000003 /* SysId info type encodings for opcode NV_MSGBOX_CMD_OPCODE_GET_SYS_ID_DATA (0x05) */ #define NV_MSGBOX_CMD_ARG1_BOARD_PART_NUM_V1 0x00000000 #define NV_MSGBOX_CMD_ARG1_OEM_INFO_V1 0x00000001 @@ -134,7 +135,8 @@ #define NV_MSGBOX_CMD_ARG1_PCIE_SPEED_V1 0x00000012 #define NV_MSGBOX_CMD_ARG1_PCIE_WIDTH_V1 0x00000013 #define NV_MSGBOX_CMD_ARG1_TGP_LIMIT_V1 0x00000014 -#define NV_MSGBOX_CMD_ARG1_SYS_ID_DATA_TYPE_MAX 0x00000014 /* Adjust, when adding new types */ +#define NV_MSGBOX_CMD_ARG1_MODULE_POWER_LIMIT_V1 0x00000016 +#define NV_MSGBOX_CMD_ARG1_SYS_ID_DATA_TYPE_MAX 0x00000016 /* Adjust, when adding new types */ #define NV_MSGBOX_CMD_ARG1_REGISTER_ACCESS_WRITE 0x00000000 #define NV_MSGBOX_CMD_ARG1_REGISTER_ACCESS_READ 0x00000001 #define NV_MSGBOX_CMD_ARG1_THERM_PARAM_TEMP_TARGET 0x00000000 @@ -186,6 +188,10 @@ #define NV_MSGBOX_CMD_ARG1_GET_PCIE_LINK_INFO_PAGE_1 0x00000001 #define NV_MSGBOX_CMD_ARG1_GET_PCIE_LINK_INFO_PAGE_2 0x00000002 #define NV_MSGBOX_CMD_ARG1_GET_PCIE_LINK_INFO_PAGE_3 0x00000003 +#define NV_MSGBOX_CMD_ARG1_GET_PCIE_LINK_INFO_PAGE_4 0x00000004 +#define NV_MSGBOX_CMD_ARG1_GET_PCIE_LINK_INFO_PAGE_6 0x00000006 +#define NV_MSGBOX_CMD_ARG1_GET_PCIE_LINK_INFO_PAGE_8 0x00000008 +#define NV_MSGBOX_CMD_ARG1_GET_PCIE_LINK_INFO_PAGE_9 0x00000009 /* Async requests */ #define NV_MSGBOX_CMD_ARG1_ASYNC_REQUEST_PMGR_PWR_TGP_LIMIT_CONTROL_GET \ @@ -224,6 +230,12 @@ 0x00000010 #define NV_MSGBOX_CMD_ARG1_ASYNC_REQUEST_CONFIGURE_PROGRAMMABLE_EDPP \ 0x00000011 +#define NV_MSGBOX_CMD_ARG1_ASYNC_REQUEST_PMGR_PWR_MODULE_LIMIT_CONTROL_GET \ + 0x00000012 +#define NV_MSGBOX_CMD_ARG1_ASYNC_REQUEST_PMGR_PWR_MODULE_LIMIT_CONTROL_SET \ + 0x00000013 +#define NV_MSGBOX_CMD_ARG1_ASYNC_REQUEST_PMGR_PWR_MODULE_LIMIT_INFO_GET \ + 0x00000014 #define NV_MSGBOX_CMD_ARG1_ASYNC_REQUEST_POLL 0x000000ff @@ -329,6 +341,9 @@ #define NV_MSGBOX_CMD_ARG1_ECC_V6_ERROR_TYPE_CORRECTABLE_ERROR 0 #define NV_MSGBOX_CMD_ARG1_ECC_V6_ERROR_TYPE_UNCORRECTABLE_ERROR 1 +#define NV_MSGBOX_CMD_ARG1_ENERGY_COUNTER_GPU 0x00000000 +#define NV_MSGBOX_CMD_ARG1_ENERGY_COUNTER_MODULE 0x00000003 + // Query type of _GET_POWER_HINT_INFO #define NV_MSGBOX_CMD_ARG1_GET_POWER_HINT_INFO_CLK 0x00000000 #define NV_MSGBOX_CMD_ARG1_GET_POWER_HINT_INFO_TEMP 0x00000001 @@ -445,6 +460,34 @@ #define NV_MSGBOX_CMD_ARG2_REMAP_ROWS_STATE_FLAGS_PAGE0 0x00000000 /*! + * Arg2 for _GET_PCIE_LINK_INFO + * Arg1 == _GET_PCIE_LINK_INFO_PAGE_8 + * Return TX EQ parameters + */ +#define NV_MSGBOX_CMD_ARG2_GET_PCIE_LINK_INFO_PAGE_8_LANE_IDX 3:0 +#define NV_MSGBOX_CMD_ARG2_GET_PCIE_LINK_INFO_PAGE_8_SPEED_SELECT 5:4 +#define NV_MSGBOX_CMD_ARG2_GET_PCIE_LINK_INFO_PAGE_8_SPEED_SELECT_GEN_3 \ + 0x00000000 +#define NV_MSGBOX_CMD_ARG2_GET_PCIE_LINK_INFO_PAGE_8_SPEED_SELECT_GEN_4 \ + 0x00000001 +#define NV_MSGBOX_CMD_ARG2_GET_PCIE_LINK_INFO_PAGE_8_SPEED_SELECT_GEN_5 \ + 0x00000002 + +/*! + * Arg2 for _GET_PCIE_LINK_INFO + * Arg1 == _GET_PCIE_LINK_INFO_PAGE_9 + * Return RX EQ parameters + */ +#define NV_MSGBOX_CMD_ARG2_GET_PCIE_LINK_INFO_PAGE_9_LANE_IDX 3:0 +#define NV_MSGBOX_CMD_ARG2_GET_PCIE_LINK_INFO_PAGE_9_SPEED_SELECT 5:4 +#define NV_MSGBOX_CMD_ARG2_GET_PCIE_LINK_INFO_PAGE_9_SPEED_SELECT_GEN_3 \ + 0x00000000 +#define NV_MSGBOX_CMD_ARG2_GET_PCIE_LINK_INFO_PAGE_9_SPEED_SELECT_GEN_4 \ + 0x00000001 +#define NV_MSGBOX_CMD_ARG2_GET_PCIE_LINK_INFO_PAGE_9_SPEED_SELECT_GEN_5 \ + 0x00000002 + +/*! * Arg2 for _GET_POWER_HINT_INFO * ARG1 == _GET_POWER_HINT_INFO_CLK * Return Min/Max frequency in MHz @@ -619,6 +662,18 @@ #define NV_MSGBOX_DATA_CAP_0_EXT_TEMP_BITS_ADT7473 0x00000002 #define NV_MSGBOX_DATA_CAP_0_EXT_TEMP_BITS_SFXP11_5 0x00000005 #define NV_MSGBOX_DATA_CAP_0_EXT_TEMP_BITS_SFXP24_8 0x00000008 +#define NV_MSGBOX_DATA_CAP_0_GET_ENERGY_COUNTER_MODULE 12:12 +#define NV_MSGBOX_DATA_CAP_0_GET_ENERGY_COUNTER_MODULE_NOT_AVAILABLE 0x00000000 +#define NV_MSGBOX_DATA_CAP_0_GET_ENERGY_COUNTER_MODULE_AVAILABLE 0x00000001 +#define NV_MSGBOX_DATA_CAP_0_MODULE_LIMIT_CONTROL_GET 13:13 +#define NV_MSGBOX_DATA_CAP_0_MODULE_LIMIT_CONTROL_GET_NOT_AVAILABLE 0x00000000 +#define NV_MSGBOX_DATA_CAP_0_MODULE_LIMIT_CONTROL_GET_AVAILABLE 0x00000001 +#define NV_MSGBOX_DATA_CAP_0_MODULE_LIMIT_CONTROL_SET 14:14 +#define NV_MSGBOX_DATA_CAP_0_MODULE_LIMIT_CONTROL_SET_NOT_AVAILABLE 0x00000000 +#define NV_MSGBOX_DATA_CAP_0_MODULE_LIMIT_CONTROL_SET_AVAILABLE 0x00000001 +#define NV_MSGBOX_DATA_CAP_0_MODULE_LIMIT_INFO_GET 15:15 +#define NV_MSGBOX_DATA_CAP_0_MODULE_LIMIT_INFO_GET_NOT_AVAILABLE 0x00000000 +#define NV_MSGBOX_DATA_CAP_0_MODULE_LIMIT_INFO_GET_AVAILABLE 0x00000001 #define NV_MSGBOX_DATA_CAP_0_POWER_TOTAL 16:16 #define NV_MSGBOX_DATA_CAP_0_POWER_TOTAL_NOT_AVAILABLE 0x00000000 #define NV_MSGBOX_DATA_CAP_0_POWER_TOTAL_AVAILABLE 0x00000001 @@ -667,6 +722,9 @@ #define NV_MSGBOX_DATA_CAP_0_POWER_FB 30:30 #define NV_MSGBOX_DATA_CAP_0_POWER_FB_NOT_AVAILABLE 0x00000000 #define NV_MSGBOX_DATA_CAP_0_POWER_FB_AVAILABLE 0x00000001 +#define NV_MSGBOX_DATA_CAP_0_POWER_MODULE 31:31 +#define NV_MSGBOX_DATA_CAP_0_POWER_MODULE_NOT_AVAILABLE 0x00000000 +#define NV_MSGBOX_DATA_CAP_0_POWER_MODULE_AVAILABLE 0x00000001 #define NV_MSGBOX_DATA_CAP_1 1 #define NV_MSGBOX_DATA_CAP_1_BOARD_PART_NUM_V1 0:0 @@ -714,6 +772,9 @@ #define NV_MSGBOX_DATA_CAP_1_INFOROM_VER_V1 14:14 #define NV_MSGBOX_DATA_CAP_1_INFOROM_VER_V1_NOT_AVAILABLE 0x00000000 #define NV_MSGBOX_DATA_CAP_1_INFOROM_VER_V1_AVAILABLE 0x00000001 +#define NV_MSGBOX_DATA_CAP_1_MODULE_LIMIT_V1 15:15 +#define NV_MSGBOX_DATA_CAP_1_MODULE_LIMIT_V1_NOT_AVAILABLE 0x00000000 +#define NV_MSGBOX_DATA_CAP_1_MODULE_LIMIT_V1_AVAILABLE 0x00000001 #define NV_MSGBOX_DATA_CAP_1_ECC_V1 16:16 #define NV_MSGBOX_DATA_CAP_1_ECC_V1_NOT_AVAILABLE 0x00000000 #define NV_MSGBOX_DATA_CAP_1_ECC_V1_AVAILABLE 0x00000001 @@ -1193,7 +1254,7 @@ #define NV_MSGBOX_DATA_REMAP_ROW_HISTOGRAM_LOW_AVAILABILITY 15:0 #define NV_MSGBOX_DATA_REMAP_ROW_HISTOGRAM_PARTIAL_AVAILABILITY 31:16 -/* Respones to NV_MSGBOX_CMD_ARG1_GET_PCIE_LINK_INFO_PAGE_0 */ +/* Response to NV_MSGBOX_CMD_ARG1_GET_PCIE_LINK_INFO_PAGE_0 */ #define NV_MSGBOX_DATA_PCIE_LINK_INFO_PAGE_0_LINK_SPEED 2:0 #define NV_MSGBOX_DATA_PCIE_LINK_INFO_PAGE_0_LINK_SPEED_UNKNOWN 0x00000000 #define NV_MSGBOX_DATA_PCIE_LINK_INFO_PAGE_0_LINK_SPEED_2500_MTPS 0x00000001 @@ -1213,13 +1274,61 @@ #define NV_MSGBOX_DATA_PCIE_LINK_INFO_PAGE_0_FATAL_ERROR_COUNT 23:16 #define NV_MSGBOX_DATA_PCIE_LINK_INFO_PAGE_0_UNSUPP_REQ_COUNT 31:24 -/* Respones to NV_MSGBOX_CMD_ARG1_GET_PCIE_LINK_INFO_PAGE_1 */ +/* Response to NV_MSGBOX_CMD_ARG1_GET_PCIE_LINK_INFO_PAGE_1 */ #define NV_MSGBOX_DATA_PCIE_LINK_INFO_PAGE_1_L0_TO_RECOVERY_COUNT 31:0 -/* Respones to NV_MSGBOX_CMD_ARG1_GET_PCIE_LINK_INFO_PAGE_2 */ +/* Response to NV_MSGBOX_CMD_ARG1_GET_PCIE_LINK_INFO_PAGE_2 */ #define NV_MSGBOX_DATA_PCIE_LINK_INFO_PAGE_2_REPLAY_ROLLOVER_COUNT 15:0 #define NV_MSGBOX_DATA_PCIE_LINK_INFO_PAGE_2_NAKS_RCVD_COUNT 31:16 +/* Response to NV_MSGBOX_CMD_ARG1_GET_PCIE_LINK_INFO_PAGE_3 */ +#define NV_MSGBOX_DATA_PCIE_LINK_INFO_PAGE_3_TARGET_LINK_SPEED 2:0 +#define NV_MSGBOX_DATA_PCIE_LINK_INFO_PAGE_3_TARGET_LINK_SPEED_UNKNOWN 0x00000000 +#define NV_MSGBOX_DATA_PCIE_LINK_INFO_PAGE_3_TARGET_LINK_SPEED_2500_MTPS 0x00000001 +#define NV_MSGBOX_DATA_PCIE_LINK_INFO_PAGE_3_TARGET_LINK_SPEED_5000_MTPS 0x00000002 +#define NV_MSGBOX_DATA_PCIE_LINK_INFO_PAGE_3_TARGET_LINK_SPEED_8000_MTPS 0x00000003 +#define NV_MSGBOX_DATA_PCIE_LINK_INFO_PAGE_3_TARGET_LINK_SPEED_16000_MTPS 0x00000004 +#define NV_MSGBOX_DATA_PCIE_LINK_INFO_PAGE_3_TARGET_LINK_SPEED_32000_MTPS 0x00000005 +#define NV_MSGBOX_DATA_PCIE_LINK_INFO_PAGE_3_TARGET_LINK_SPEED_RESERVED 2:0 + +/* Response to NV_MSGBOX_CMD_ARG1_GET_PCIE_LINK_INFO_PAGE_4 */ +#define NV_MSGBOX_DATA_PCIE_LINK_INFO_PAGE_4_TX_COUNT 31:0 + +/* Response to NV_MSGBOX_CMD_ARG1_GET_PCIE_LINK_INFO_PAGE_6 */ +#define NV_MSGBOX_DATA_PCIE_LINK_INFO_PAGE_6_LTSSM_STATE 4:0 +#define NV_MSGBOX_DATA_PCIE_LINK_INFO_PAGE_6_LTSSM_STATE_DETECT 0x00000000 +#define NV_MSGBOX_DATA_PCIE_LINK_INFO_PAGE_6_LTSSM_STATE_POLLING 0x00000001 +#define NV_MSGBOX_DATA_PCIE_LINK_INFO_PAGE_6_LTSSM_STATE_CONFIGURATION 0x00000002 +#define NV_MSGBOX_DATA_PCIE_LINK_INFO_PAGE_6_LTSSM_STATE_RECOVERY 0x00000003 +#define NV_MSGBOX_DATA_PCIE_LINK_INFO_PAGE_6_LTSSM_STATE_RECOVERY_EQZN 0x00000004 +#define NV_MSGBOX_DATA_PCIE_LINK_INFO_PAGE_6_LTSSM_STATE_L0 0x00000005 +#define NV_MSGBOX_DATA_PCIE_LINK_INFO_PAGE_6_LTSSM_STATE_L0S 0x00000006 +#define NV_MSGBOX_DATA_PCIE_LINK_INFO_PAGE_6_LTSSM_STATE_L1 0x00000007 +#define NV_MSGBOX_DATA_PCIE_LINK_INFO_PAGE_6_LTSSM_STATE_L1_PLL_PD 0x00000008 +#define NV_MSGBOX_DATA_PCIE_LINK_INFO_PAGE_6_LTSSM_STATE_L2 0x00000009 +#define NV_MSGBOX_DATA_PCIE_LINK_INFO_PAGE_6_LTSSM_STATE_L1_CPM 0x0000000a +#define NV_MSGBOX_DATA_PCIE_LINK_INFO_PAGE_6_LTSSM_STATE_L1_1 0x0000000b +#define NV_MSGBOX_DATA_PCIE_LINK_INFO_PAGE_6_LTSSM_STATE_L1_2 0x0000000c +#define NV_MSGBOX_DATA_PCIE_LINK_INFO_PAGE_6_LTSSM_STATE_HOT_RESET 0x0000000d +#define NV_MSGBOX_DATA_PCIE_LINK_INFO_PAGE_6_LTSSM_STATE_LOOPBACK 0x0000000e +#define NV_MSGBOX_DATA_PCIE_LINK_INFO_PAGE_6_LTSSM_STATE_DISABLED 0x0000000f +#define NV_MSGBOX_DATA_PCIE_LINK_INFO_PAGE_6_LTSSM_STATE_LINK_DOWN 0x00000010 +#define NV_MSGBOX_DATA_PCIE_LINK_INFO_PAGE_6_LTSSM_STATE_LINK_READY 0x00000011 +#define NV_MSGBOX_DATA_PCIE_LINK_INFO_PAGE_6_LTSSM_STATE_LANES_IN_SLEEP 0x00000012 +#define NV_MSGBOX_DATA_PCIE_LINK_INFO_PAGE_6_LTSSM_STATE_ILLEGAL 0x0000001f + +/* Response to NV_MSGBOX_CMD_ARG1_GET_PCIE_LINK_INFO_PAGE_8 */ +#define NV_MSGBOX_DATA_PCIE_LINK_INFO_PAGE_8_EQ_TX_LOCAL_PRESET 3:0 +#define NV_MSGBOX_DATA_PCIE_LINK_INFO_PAGE_8_EQ_TX_LOCAL_USE_PRESET 4:4 +#define NV_MSGBOX_DATA_PCIE_LINK_INFO_PAGE_8_EQ_TX_LOCAL_FS 10:5 +#define NV_MSGBOX_DATA_PCIE_LINK_INFO_PAGE_8_EQ_TX_LOCAL_LF 16:11 + +/* Response to NV_MSGBOX_CMD_ARG1_GET_PCIE_LINK_INFO_PAGE_9 */ +#define NV_MSGBOX_DATA_PCIE_LINK_INFO_PAGE_9_EQ_RX_REMOTE_PRESET 3:0 +#define NV_MSGBOX_DATA_PCIE_LINK_INFO_PAGE_9_EQ_RX_REMOTE_USE_PRESET 4:4 +#define NV_MSGBOX_DATA_PCIE_LINK_INFO_PAGE_9_EQ_RX_REMOTE_FS 10:5 +#define NV_MSGBOX_DATA_PCIE_LINK_INFO_PAGE_9_EQ_RX_REMOTE_LF 16:11 + /* * Input for NV_MSGBOX_CMD_OPCODE_GPU_PERFORMANCE_MONITORING. Value is valid * only if Arg2 != GPM_PARTITION_AGGREGATE and Arg2.Bit7 == 1 @@ -1246,15 +1355,18 @@ /* Respones to NV_MSGBOX_CMD_ARG1_GET_PCIE_LINK_INFO_PAGE_2 */ #define NV_MSGBOX_EXT_DATA_PCIE_LINK_INFO_PAGE_2_NAKS_SENT_COUNT 15:0 -/* Respones to NV_MSGBOX_CMD_ARG1_GET_PCIE_LINK_INFO_PAGE_3 */ -#define NV_MSGBOX_DATA_PCIE_LINK_INFO_PAGE_3_TARGET_LINK_SPEED 2:0 -#define NV_MSGBOX_DATA_PCIE_LINK_INFO_PAGE_3_TARGET_LINK_SPEED_UNKNOWN 0x00000000 -#define NV_MSGBOX_DATA_PCIE_LINK_INFO_PAGE_3_TARGET_LINK_SPEED_2500_MTPS 0x00000001 -#define NV_MSGBOX_DATA_PCIE_LINK_INFO_PAGE_3_TARGET_LINK_SPEED_5000_MTPS 0x00000002 -#define NV_MSGBOX_DATA_PCIE_LINK_INFO_PAGE_3_TARGET_LINK_SPEED_8000_MTPS 0x00000003 -#define NV_MSGBOX_DATA_PCIE_LINK_INFO_PAGE_3_TARGET_LINK_SPEED_16000_MTPS 0x00000004 -#define NV_MSGBOX_DATA_PCIE_LINK_INFO_PAGE_3_TARGET_LINK_SPEED_32000_MTPS 0x00000005 -#define NV_MSGBOX_DATA_PCIE_LINK_INFO_PAGE_3_TARGET_LINK_SPEED_RESERVED 2:0 +/* Response to NV_MSGBOX_CMD_ARG1_GET_PCIE_LINK_INFO_PAGE_4 */ +#define NV_MSGBOX_EXT_DATA_PCIE_LINK_INFO_PAGE_4_RX_COUNT 31:0 + +/* Response to NV_MSGBOX_CMD_ARG1_GET_PCIE_LINK_INFO_PAGE_8 */ +#define NV_MSGBOX_EXT_DATA_PCIE_LINK_INFO_PAGE_8_EQ_TX_LOCAL_PRECUR 5:0 +#define NV_MSGBOX_EXT_DATA_PCIE_LINK_INFO_PAGE_8_EQ_TX_LOCAL_MAINCUR 11:6 +#define NV_MSGBOX_EXT_DATA_PCIE_LINK_INFO_PAGE_8_EQ_TX_LOCAL_POSTCUR 17:12 + +/* Response to NV_MSGBOX_CMD_ARG1_GET_PCIE_LINK_INFO_PAGE_9 */ +#define NV_MSGBOX_EXT_DATA_PCIE_LINK_INFO_PAGE_9_EQ_RX_REMOTE_PRECUR 5:0 +#define NV_MSGBOX_EXT_DATA_PCIE_LINK_INFO_PAGE_9_EQ_RX_REMOTE_MAINCUR 11:6 +#define NV_MSGBOX_EXT_DATA_PCIE_LINK_INFO_PAGE_9_EQ_RX_REMOTE_POSTCUR 17:12 /* Response to NV_MSGBOX_CMD_ARG1_REMAP_ROWS_HISTOGRAM */ #define NV_MSGBOX_EXT_DATA_REMAP_ROW_HISTOGRAM_MAX_AVAILABILITY 31:16 @@ -1363,6 +1475,7 @@ NV_MSGBOX_EVENT_TYPE_MIG_TOGGLE_SUCCESS, NV_MSGBOX_EVENT_TYPE_SERVER_RESTART_WARM, NV_MSGBOX_EVENT_TYPE_DRIVER_ERROR_MESSAGE_NEW, + NV_MSGBOX_EVENT_TYPE_MODULE_LIMIT_SET_SUCCESS, NV_MSGBOX_NUM_EVENTS, /* insert new event types before this line */ } NvMsgboxEventType; @@ -1702,8 +1815,10 @@ /*! * This structure is used to hold parameters for - * NV_MSGBOX_CMD_ARG1_ASYNC_REQUEST_PMGR_PWR_TGP_LIMIT_CONTROL_GET and - * NV_MSGBOX_CMD_ARG1_ASYNC_REQUEST_PMGR_PWR_TGP_LIMIT_CONTROL_SET + * NV_MSGBOX_CMD_ARG1_ASYNC_REQUEST_PMGR_PWR_TGP_LIMIT_CONTROL_GET, + * NV_MSGBOX_CMD_ARG1_ASYNC_REQUEST_PMGR_PWR_TGP_LIMIT_CONTROL_SET, + * NV_MSGBOX_CMD_ARG1_ASYNC_REQUEST_PMGR_PWR_MODULE_LIMIT_CONTROL_GET and + * NV_MSGBOX_CMD_ARG1_ASYNC_REQUEST_PMGR_PWR_MODULE_LIMIT_CONTROL_SET */ typedef struct { @@ -1715,12 +1830,12 @@ * If flags:_CLEAR is _ON, it will clear the TGP limit. The * persistence still depends on persist flag. */ -#define NV_MSGBOX_PMGR_PWR_TGP_LIMIT_CONTROL_PARAMS_FLAGS_PERSIST 0:0 -#define NV_MSGBOX_PMGR_PWR_TGP_LIMIT_CONTROL_PARAMS_FLAGS_PERSIST_OFF 0x00000000 -#define NV_MSGBOX_PMGR_PWR_TGP_LIMIT_CONTROL_PARAMS_FLAGS_PERSIST_ON 0x00000001 -#define NV_MSGBOX_PMGR_PWR_TGP_LIMIT_CONTROL_PARAMS_FLAGS_CLEAR 1:1 -#define NV_MSGBOX_PMGR_PWR_TGP_LIMIT_CONTROL_PARAMS_FLAGS_CLEAR_OFF 0x00000000 -#define NV_MSGBOX_PMGR_PWR_TGP_LIMIT_CONTROL_PARAMS_FLAGS_CLEAR_ON 0x00000001 +#define NV_MSGBOX_PMGR_PWR_POWER_LIMIT_CONTROL_PARAMS_FLAGS_PERSIST 0:0 +#define NV_MSGBOX_PMGR_PWR_POWER_LIMIT_CONTROL_PARAMS_FLAGS_PERSIST_OFF 0x00000000 +#define NV_MSGBOX_PMGR_PWR_POWER_LIMIT_CONTROL_PARAMS_FLAGS_PERSIST_ON 0x00000001 +#define NV_MSGBOX_PMGR_PWR_POWER_LIMIT_CONTROL_PARAMS_FLAGS_CLEAR 1:1 +#define NV_MSGBOX_PMGR_PWR_POWER_LIMIT_CONTROL_PARAMS_FLAGS_CLEAR_OFF 0x00000000 +#define NV_MSGBOX_PMGR_PWR_POWER_LIMIT_CONTROL_PARAMS_FLAGS_CLEAR_ON 0x00000001 /*! * Current total GPU power limit value to enforce, requested by the @@ -1736,11 +1851,12 @@ * in milliwatts. */ NvU32 limitCurrOutput; -} NV_MSGBOX_PMGR_PWR_TGP_LIMIT_CONTROL_PARAMS; +} NV_MSGBOX_PMGR_PWR_POWER_LIMIT_CONTROL_PARAMS; /*! * This structure is used to hold parameters for - * NV_MSGBOX_CMD_ARG1_ASYNC_REQUEST_PMGR_PWR_TGP_LIMIT_INFO_GET + * NV_MSGBOX_CMD_ARG1_ASYNC_REQUEST_PMGR_PWR_TGP_LIMIT_INFO_GET and + * NV_MSGBOX_CMD_ARG1_ASYNC_REQUEST_PMGR_PWR_MODULE_LIMIT_INFO_GET */ typedef struct { @@ -1748,13 +1864,14 @@ * Current total GPU power limit lower and upper bounds and the * default setting, expressed in milliwatts. * These constraints must be observed, when the limit - * is being set with - * NV_MSGBOX_CMD_ARG1_ASYNC_REQUEST_PMGR_PWR_TGP_LIMIT_CONTROL_SET. + * is being set with either + * NV_MSGBOX_CMD_ARG1_ASYNC_REQUEST_PMGR_PWR_TGP_LIMIT_CONTROL_SET or + * NV_MSGBOX_CMD_ARG1_ASYNC_REQUEST_PMGR_PWR_MODULE_LIMIT_CONTROL_SET. */ NvU32 limitMin; NvU32 limitMax; NvU32 limitDefault; -} NV_MSGBOX_PMGR_PWR_TGP_LIMIT_INFO_PARAMS; +} NV_MSGBOX_PMGR_PWR_POWER_LIMIT_INFO_PARAMS; /*! * This structure is used to hold parameters for @@ -1939,6 +2056,7 @@ // + +/*! + * Defines structures and interfaces for any SPDM Vendor-defined behavior. + */ + +/* ------------------------- NVIDIA Export Secrets -------------------------- */ + + +/* ------------------------- Macros ----------------------------------------- */ +#define SPDM_ATTESTATION_REPORT_MAX_SIZE (0x2000) +#define SPDM_MAX_MESSAGE_BUFFER_SIZE (0x1000) +#define SPDM_MAX_EXCHANGE_BUFFER_SIZE (2 * SPDM_MAX_MESSAGE_BUFFER_SIZE) +#define SPDM_MAX_CERT_CHAIN_SIZE (SPDM_MAX_MESSAGE_BUFFER_SIZE) +#define SPDM_CERT_DEFAULT_SLOT_ID (0) +#define SPDM_CAPABILITIES_CT_EXPONENT_MAX (0xFF) +#define BIN_STR_CONCAT_BUFFER_MAX_BYTES (128) + +#define NV_BYTE_TO_BIT_OVERFLOW_MASK_UINT32 (0xE0000000) +#define IS_BYTE_TO_BIT_OVERFLOW_UINT32(a) \ + ((a & NV_BYTE_TO_BIT_OVERFLOW_MASK_UINT32) != 0) + +#endif // _RMSPDMVENDORDEF_H_ diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/arch/nvalloc/unix/include/nv-ioctl.h nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/arch/nvalloc/unix/include/nv-ioctl.h --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/arch/nvalloc/unix/include/nv-ioctl.h 2023-10-25 20:20:28.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/arch/nvalloc/unix/include/nv-ioctl.h 2024-03-05 22:12:46.000000000 +0000 @@ -104,7 +104,7 @@ #define NV_RM_API_VERSION_CMD_STRICT 0 #define NV_RM_API_VERSION_CMD_RELAXED '1' -#define NV_RM_API_VERSION_CMD_OVERRIDE '2' +#define NV_RM_API_VERSION_CMD_QUERY '2' #define NV_RM_API_VERSION_REPLY_UNRECOGNIZED 0 #define NV_RM_API_VERSION_REPLY_RECOGNIZED 1 diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/arch/nvalloc/unix/include/nv-priv.h nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/arch/nvalloc/unix/include/nv-priv.h --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/arch/nvalloc/unix/include/nv-priv.h 2023-10-25 20:20:28.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/arch/nvalloc/unix/include/nv-priv.h 2024-03-05 22:12:46.000000000 +0000 @@ -358,6 +358,7 @@ */ NvU64 s0ix_gcoff_max_fb_size; + NvU32 pmc_boot_1; NvU32 pmc_boot_42; } nv_priv_t; diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/arch/nvalloc/unix/include/nv-reg.h nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/arch/nvalloc/unix/include/nv-reg.h --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/arch/nvalloc/unix/include/nv-reg.h 2023-10-25 20:20:28.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/arch/nvalloc/unix/include/nv-reg.h 2024-03-05 22:12:46.000000000 +0000 @@ -21,10 +21,15 @@ * DEALINGS IN THE SOFTWARE. */ +// +// This file holds Unix-specific NVIDIA driver options +// + #ifndef _RM_REG_H_ #define _RM_REG_H_ #include "nvtypes.h" +#include "nv-firmware-registry.h" /* * use NV_REG_STRING to stringify a registry key when using that registry key @@ -700,6 +705,22 @@ NV_REG_STRING(__NV_ENABLE_PCIE_RELAXED_ORDERING_MODE) /* + * Option: EnableResizableBar + * + * Description: + * + * When this option is enabled, the NVIDIA driver will attempt to resize + * BAR1 to match framebuffer size, or the next largest available size on + * supported machines. This is currently only implemented for Linux. + * + * Possible values: + * 0 - Do not enable PCI BAR resizing + * 1 - Enable PCI BAR resizing + */ +#define __NV_ENABLE_RESIZABLE_BAR EnableResizableBar +#define NV_REG_ENABLE_RESIZABLE_BAR NV_REG_STRING(__NV_ENABLE_RESIZABLE_BAR) + +/* * Option: EnableGpuFirmware * * Description: @@ -707,72 +728,33 @@ * When this option is enabled, the NVIDIA driver will enable use of GPU * firmware. * - * Possible mode values: - * 0 - Do not enable GPU firmware - * 1 - Enable GPU firmware - * 2 - (Default) Use the default enablement policy for GPU firmware - * - * Setting this to anything other than 2 will alter driver firmware- - * enablement policies, possibly disabling GPU firmware where it would - * have otherwise been enabled by default. - * * If this key is set globally to the system, the driver may still attempt * to apply some policies to maintain uniform firmware modes across all * GPUS. This may result in the driver failing initialization on some GPUs * to maintain such a policy. - * + * * If this key is set using NVreg_RegistryDwordsPerDevice, then the driver * will attempt to honor whatever configuration is specified without applying * additional policies. This may also result in failed GPU initialzations if * the configuration is not possible (for example if the firmware is missing - * from the filesystem, or the GPU is not capable). - * - * Policy bits: - * - * POLICY_ALLOW_FALLBACK: - * As the normal behavior is to fail GPU initialization if this registry - * entry is set in such a way that results in an invalid configuration, if - * instead the user would like the driver to automatically try to fallback - * to initializing the failing GPU with firmware disabled, then this bit can - * be set (ex: 0x11 means try to enable GPU firmware but fall back if needed). - * Note that this can result in a mixed mode configuration (ex: GPU0 has - * firmware enabled, but GPU1 does not). + * from the filesystem, or the GPU is not capable). * + * NOTE: More details for this regkey can be found in nv-firmware-registry.h */ - #define __NV_ENABLE_GPU_FIRMWARE EnableGpuFirmware #define NV_REG_ENABLE_GPU_FIRMWARE NV_REG_STRING(__NV_ENABLE_GPU_FIRMWARE) -#define NV_REG_ENABLE_GPU_FIRMWARE_MODE_MASK 0x0000000F -#define NV_REG_ENABLE_GPU_FIRMWARE_MODE_DISABLED 0x00000000 -#define NV_REG_ENABLE_GPU_FIRMWARE_MODE_ENABLED 0x00000001 -#define NV_REG_ENABLE_GPU_FIRMWARE_MODE_DEFAULT 0x00000002 - -#define NV_REG_ENABLE_GPU_FIRMWARE_POLICY_MASK 0x000000F0 -#define NV_REG_ENABLE_GPU_FIRMWARE_POLICY_ALLOW_FALLBACK 0x00000010 - -#define NV_REG_ENABLE_GPU_FIRMWARE_DEFAULT_VALUE 0x00000012 -#define NV_REG_ENABLE_GPU_FIRMWARE_INVALID_VALUE 0xFFFFFFFF - /* * Option: EnableGpuFirmwareLogs * * When this option is enabled, the NVIDIA driver will send GPU firmware logs * to the system log, when possible. * - * Possible values: - * 0 - Do not send GPU firmware logs to the system log - * 1 - Enable sending of GPU firmware logs to the system log - * 2 - (Default) Enable sending of GPU firmware logs to the system log for - * the debug kernel driver build only + * NOTE: More details for this regkey can be found in nv-firmware-registry.h */ #define __NV_ENABLE_GPU_FIRMWARE_LOGS EnableGpuFirmwareLogs #define NV_REG_ENABLE_GPU_FIRMWARE_LOGS NV_REG_STRING(__NV_ENABLE_GPU_FIRMWARE_LOGS) -#define NV_REG_ENABLE_GPU_FIRMWARE_LOGS_DISABLE 0x00000000 -#define NV_REG_ENABLE_GPU_FIRMWARE_LOGS_ENABLE 0x00000001 -#define NV_REG_ENABLE_GPU_FIRMWARE_LOGS_ENABLE_ON_DEBUG 0x00000002 - /* * Option: EnableDbgBreakpoint * @@ -825,6 +807,26 @@ #define NV_DMA_REMAP_PEER_MMIO_DISABLE 0x00000000 #define NV_DMA_REMAP_PEER_MMIO_ENABLE 0x00000001 +/* + * Option: NVreg_RmNvlinkBandwidth + * + * Description: + * + * This option allows user to reduce the NVLINK P2P bandwidth to save power. + * The option is in the string format. + * + * Possible string values: + * OFF: 0% bandwidth + * MIN: 15%-25% bandwidth depending on the system's NVLink topology + * HALF: 50% bandwidth + * 3QUARTER: 75% bandwidth + * FULL: 100% bandwidth (default) + * + * This option is only for Hopper+ GPU with NVLINK version 4.0. + */ +#define __NV_RM_NVLINK_BW RmNvlinkBandwidth +#define NV_RM_NVLINK_BW NV_REG_STRING(__NV_RM_NVLINK_BW) + #if defined(NV_DEFINE_REGISTRY_KEY_TABLE) /* @@ -861,6 +863,7 @@ NV_DEFINE_REG_ENTRY_GLOBAL(__NV_NVLINK_DISABLE, 0); NV_DEFINE_REG_ENTRY_GLOBAL(__NV_ENABLE_PCIE_RELAXED_ORDERING_MODE, 0); NV_DEFINE_REG_ENTRY_GLOBAL(__NV_REGISTER_PCI_DRIVER, 1); +NV_DEFINE_REG_ENTRY_GLOBAL(__NV_ENABLE_RESIZABLE_BAR, 0); NV_DEFINE_REG_ENTRY_GLOBAL(__NV_ENABLE_DBG_BREAKPOINT, 0); NV_DEFINE_REG_STRING_ENTRY(__NV_REGISTRY_DWORDS, NULL); @@ -870,6 +873,7 @@ NV_DEFINE_REG_STRING_ENTRY(__NV_TEMPORARY_FILE_PATH, NULL); NV_DEFINE_REG_STRING_ENTRY(__NV_EXCLUDED_GPUS, NULL); NV_DEFINE_REG_ENTRY(__NV_DMA_REMAP_PEER_MMIO, NV_DMA_REMAP_PEER_MMIO_ENABLE); +NV_DEFINE_REG_STRING_ENTRY(__NV_RM_NVLINK_BW, NULL); /* *----------------registry database definition---------------------- @@ -910,6 +914,7 @@ NV_DEFINE_PARAMS_TABLE_ENTRY(__NV_DYNAMIC_POWER_MANAGEMENT_VIDEO_MEMORY_THRESHOLD), NV_DEFINE_PARAMS_TABLE_ENTRY(__NV_REGISTER_PCI_DRIVER), NV_DEFINE_PARAMS_TABLE_ENTRY(__NV_ENABLE_PCIE_RELAXED_ORDERING_MODE), + NV_DEFINE_PARAMS_TABLE_ENTRY(__NV_ENABLE_RESIZABLE_BAR), NV_DEFINE_PARAMS_TABLE_ENTRY(__NV_ENABLE_GPU_FIRMWARE), NV_DEFINE_PARAMS_TABLE_ENTRY(__NV_ENABLE_GPU_FIRMWARE_LOGS), NV_DEFINE_PARAMS_TABLE_ENTRY(__NV_ENABLE_DBG_BREAKPOINT), diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/arch/nvalloc/unix/include/nv.h nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/arch/nvalloc/unix/include/nv.h --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/arch/nvalloc/unix/include/nv.h 2023-10-25 20:20:28.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/arch/nvalloc/unix/include/nv.h 2024-03-05 22:12:46.000000000 +0000 @@ -315,6 +315,7 @@ NV_SOC_IRQ_DPAUX_TYPE, NV_SOC_IRQ_GPIO_TYPE, NV_SOC_IRQ_HDACODEC_TYPE, + NV_SOC_IRQ_TCPC2DISP_TYPE, NV_SOC_IRQ_INVALID_TYPE } nv_soc_irq_type_t; @@ -329,6 +330,7 @@ NvU32 gpio_num; NvU32 dpaux_instance; } irq_data; + NvS32 ref_count; } nv_soc_irq_info_t; #define NV_MAX_SOC_IRQS 6 @@ -345,6 +347,12 @@ /* DMA-capable device data, defined by kernel interface layer */ typedef struct nv_dma_device nv_dma_device_t; +typedef struct nv_phys_addr_range +{ + NvU64 addr; + NvU64 len; +} nv_phys_addr_range_t; + typedef struct nv_state_t { void *priv; /* private data */ @@ -384,9 +392,11 @@ NvS32 current_soc_irq; NvU32 num_soc_irqs; NvU32 hdacodec_irq; + NvU32 tcpc2disp_irq; NvU8 *soc_dcb_blob; NvU32 soc_dcb_size; NvU32 disp_sw_soc_chip_id; + NvBool soc_is_dpalt_mode_supported; NvU32 igpu_stall_irq[NV_IGPU_MAX_STALL_IRQS]; NvU32 igpu_nonstall_irq; @@ -462,6 +472,9 @@ /* Bool to check if ISO iommu enabled */ NvBool iso_iommu_present; + /* Bool to check if NISO iommu enabled */ + NvBool niso_iommu_present; + /* Bool to check if dma-buf is supported */ NvBool dma_buf_supported; @@ -473,6 +486,8 @@ /* Bool to check if the device received a shutdown notification */ NvBool is_shutdown; + /* Bool to check if the GPU has a coherent sysmem link */ + NvBool coherent; } nv_state_t; // These define need to be in sync with defines in system.h @@ -507,6 +522,8 @@ typedef struct gpuSession *nvgpuSessionHandle_t; typedef struct gpuDevice *nvgpuDeviceHandle_t; typedef struct gpuAddressSpace *nvgpuAddressSpaceHandle_t; +typedef struct gpuTsg *nvgpuTsgHandle_t; +typedef struct UvmGpuTsgAllocParams_tag nvgpuTsgAllocParams_t; typedef struct gpuChannel *nvgpuChannelHandle_t; typedef struct UvmGpuChannelInfo_tag *nvgpuChannelInfo_t; typedef struct UvmGpuChannelAllocParams_tag nvgpuChannelAllocParams_t; @@ -533,7 +550,7 @@ typedef struct UvmGpuPagingChannel_tag *nvgpuPagingChannelHandle_t; typedef struct UvmGpuPagingChannelInfo_tag *nvgpuPagingChannelInfo_t; typedef enum UvmPmaGpuMemoryType_tag nvgpuGpuMemoryType_t; -typedef NV_STATUS (*nvPmaEvictPagesCallback)(void *, NvU32, NvU64 *, NvU32, NvU64, NvU64, nvgpuGpuMemoryType_t); +typedef NV_STATUS (*nvPmaEvictPagesCallback)(void *, NvU64, NvU64 *, NvU32, NvU64, NvU64, nvgpuGpuMemoryType_t); typedef NV_STATUS (*nvPmaEvictRangeCallback)(void *, NvU64, NvU64, nvgpuGpuMemoryType_t); /* @@ -598,9 +615,19 @@ #define NV_IS_DEVICE_IN_SURPRISE_REMOVAL(nv) \ (((nv)->flags & NV_FLAG_IN_SURPRISE_REMOVAL) != 0) +/* + * For console setup by EFI GOP, the base address is BAR1. + * For console setup by VBIOS, the base address is BAR2 + 16MB. + */ +#define NV_IS_CONSOLE_MAPPED(nv, addr) \ + (((addr) == (nv)->bars[NV_GPU_BAR_INDEX_FB].cpu_address) || \ + ((addr) == ((nv)->bars[NV_GPU_BAR_INDEX_IMEM].cpu_address + 0x1000000))) + #define NV_SOC_IS_ISO_IOMMU_PRESENT(nv) \ ((nv)->iso_iommu_present) +#define NV_SOC_IS_NISO_IOMMU_PRESENT(nv) \ + ((nv)->niso_iommu_present) /* * GPU add/remove events */ @@ -655,7 +682,8 @@ static inline NvBool IS_FB_OFFSET(nv_state_t *nv, NvU64 offset, NvU64 length) { - return ((nv->fb) && (offset >= nv->fb->cpu_address) && + return ((nv->fb) && (nv->fb->size != 0) && + (offset >= nv->fb->cpu_address) && ((offset + (length - 1)) >= offset) && ((offset + (length - 1)) <= (nv->fb->cpu_address + (nv->fb->size - 1)))); } @@ -745,7 +773,7 @@ void NV_API_CALL nv_set_dma_address_size (nv_state_t *, NvU32 ); NV_STATUS NV_API_CALL nv_alias_pages (nv_state_t *, NvU32, NvU32, NvU32, NvU64, NvU64 *, void **); -NV_STATUS NV_API_CALL nv_alloc_pages (nv_state_t *, NvU32, NvBool, NvU32, NvBool, NvBool, NvU64 *, void **); +NV_STATUS NV_API_CALL nv_alloc_pages (nv_state_t *, NvU32, NvBool, NvU32, NvBool, NvBool, NvS32, NvU64 *, void **); NV_STATUS NV_API_CALL nv_free_pages (nv_state_t *, NvU32, NvBool, NvU32, void *); NV_STATUS NV_API_CALL nv_register_user_pages (nv_state_t *, NvU64, NvU64 *, void *, void **); @@ -814,6 +842,7 @@ void NV_API_CALL nv_put_file_private(void *); NV_STATUS NV_API_CALL nv_get_device_memory_config(nv_state_t *, NvU64 *, NvU64 *, NvU32 *, NvS32 *); +NV_STATUS NV_API_CALL nv_get_egm_info(nv_state_t *, NvU64 *, NvU64 *, NvS32 *); NV_STATUS NV_API_CALL nv_get_ibmnpu_genreg_info(nv_state_t *, NvU64 *, NvU64 *, void**); NV_STATUS NV_API_CALL nv_get_ibmnpu_relaxed_ordering_mode(nv_state_t *nv, NvBool *mode); @@ -853,6 +882,8 @@ NvU32 NV_API_CALL nv_get_os_type(void); void NV_API_CALL nv_get_updated_emu_seg(NvU32 *start, NvU32 *end); +void NV_API_CALL nv_get_screen_info(nv_state_t *, NvU64 *, NvU16 *, NvU16 *, NvU16 *, NvU16 *, NvU64 *); + struct dma_buf; typedef struct nv_dma_buf nv_dma_buf_t; struct drm_gem_object; @@ -903,6 +934,7 @@ NvBool NV_API_CALL rm_isr (nvidia_stack_t *, nv_state_t *, NvU32 *); void NV_API_CALL rm_isr_bh (nvidia_stack_t *, nv_state_t *); void NV_API_CALL rm_isr_bh_unlocked (nvidia_stack_t *, nv_state_t *); +NvBool NV_API_CALL rm_is_msix_allowed (nvidia_stack_t *, nv_state_t *); NV_STATUS NV_API_CALL rm_power_management (nvidia_stack_t *, nv_state_t *, nv_pm_action_t); NV_STATUS NV_API_CALL rm_stop_user_channels (nvidia_stack_t *, nv_state_t *); NV_STATUS NV_API_CALL rm_restart_user_channels (nvidia_stack_t *, nv_state_t *); @@ -944,6 +976,8 @@ void NV_API_CALL rm_power_source_change_event (nvidia_stack_t *, NvU32); +void NV_API_CALL rm_request_dnotifier_state (nvidia_stack_t *, nv_state_t *); + void NV_API_CALL rm_disable_gpu_state_persistence (nvidia_stack_t *sp, nv_state_t *); NV_STATUS NV_API_CALL rm_p2p_init_mapping (nvidia_stack_t *, NvU64, NvU64 *, NvU64 *, NvU64 *, NvU64 *, NvU64, NvU64, NvU64, NvU64, void (*)(void *), void *); NV_STATUS NV_API_CALL rm_p2p_destroy_mapping (nvidia_stack_t *, NvU64); @@ -953,12 +987,12 @@ NV_STATUS NV_API_CALL rm_p2p_register_callback (nvidia_stack_t *, NvU64, NvU64, NvU64, void *, void (*)(void *), void *); NV_STATUS NV_API_CALL rm_p2p_put_pages (nvidia_stack_t *, NvU64, NvU32, NvU64, void *); NV_STATUS NV_API_CALL rm_p2p_put_pages_persistent(nvidia_stack_t *, void *, void *); -NV_STATUS NV_API_CALL rm_p2p_dma_map_pages (nvidia_stack_t *, nv_dma_device_t *, NvU8 *, NvU32, NvU32, NvU64 *, void **); -NV_STATUS NV_API_CALL rm_dma_buf_dup_mem_handle (nvidia_stack_t *, nv_state_t *, NvHandle, NvHandle, NvHandle, NvHandle, void *, NvHandle, NvU64, NvU64, NvHandle *); +NV_STATUS NV_API_CALL rm_p2p_dma_map_pages (nvidia_stack_t *, nv_dma_device_t *, NvU8 *, NvU64, NvU32, NvU64 *, void **); +NV_STATUS NV_API_CALL rm_dma_buf_dup_mem_handle (nvidia_stack_t *, nv_state_t *, NvHandle, NvHandle, NvHandle, NvHandle, void *, NvHandle, NvU64, NvU64, NvHandle *, void **); void NV_API_CALL rm_dma_buf_undup_mem_handle(nvidia_stack_t *, nv_state_t *, NvHandle, NvHandle); -NV_STATUS NV_API_CALL rm_dma_buf_map_mem_handle (nvidia_stack_t *, nv_state_t *, NvHandle, NvHandle, NvU64, NvU64, NvU64 *); -NV_STATUS NV_API_CALL rm_dma_buf_unmap_mem_handle(nvidia_stack_t *, nv_state_t *, NvHandle, NvHandle, NvU64, NvU64); -NV_STATUS NV_API_CALL rm_dma_buf_get_client_and_device(nvidia_stack_t *, nv_state_t *, NvHandle, NvHandle *, NvHandle *, NvHandle *, void **); +NV_STATUS NV_API_CALL rm_dma_buf_map_mem_handle (nvidia_stack_t *, nv_state_t *, NvHandle, NvHandle, NvU64, NvU64, void *, nv_phys_addr_range_t **, NvU32 *); +void NV_API_CALL rm_dma_buf_unmap_mem_handle(nvidia_stack_t *, nv_state_t *, NvHandle, NvHandle, NvU64, nv_phys_addr_range_t **, NvU32); +NV_STATUS NV_API_CALL rm_dma_buf_get_client_and_device(nvidia_stack_t *, nv_state_t *, NvHandle, NvHandle *, NvHandle *, NvHandle *, void **, NvBool *); void NV_API_CALL rm_dma_buf_put_client_and_device(nvidia_stack_t *, nv_state_t *, NvHandle, NvHandle, NvHandle, void *); NV_STATUS NV_API_CALL rm_log_gpu_crash (nv_stack_t *, nv_state_t *); @@ -991,6 +1025,7 @@ const char* NV_API_CALL rm_get_gpu_gcx_support(nvidia_stack_t *, nv_state_t *, NvBool); void NV_API_CALL rm_acpi_notify(nvidia_stack_t *, nv_state_t *, NvU32); +void NV_API_CALL rm_acpi_nvpcf_notify(nvidia_stack_t *); NvBool NV_API_CALL rm_is_altstack_in_use(void); diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/arch/nvalloc/unix/include/os-interface.h nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/arch/nvalloc/unix/include/os-interface.h --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/arch/nvalloc/unix/include/os-interface.h 2023-10-25 20:20:29.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/arch/nvalloc/unix/include/os-interface.h 2024-03-05 22:12:47.000000000 +0000 @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 1999-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 1999-2024 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -162,10 +162,9 @@ NV_STATUS NV_API_CALL os_inject_vgx_msi (NvU16, NvU64, NvU32); NvBool NV_API_CALL os_is_grid_supported (void); NvU32 NV_API_CALL os_get_grid_csp_support (void); -void NV_API_CALL os_get_screen_info (NvU64 *, NvU16 *, NvU16 *, NvU16 *, NvU16 *, NvU64, NvU64); void NV_API_CALL os_bug_check (NvU32, const char *); NV_STATUS NV_API_CALL os_lock_user_pages (void *, NvU64, void **, NvU32); -NV_STATUS NV_API_CALL os_lookup_user_io_memory (void *, NvU64, NvU64 **, void**); +NV_STATUS NV_API_CALL os_lookup_user_io_memory (void *, NvU64, NvU64 **); NV_STATUS NV_API_CALL os_unlock_user_pages (NvU64, void *); NV_STATUS NV_API_CALL os_match_mmap_offset (void *, NvU64, NvU64 *); NV_STATUS NV_API_CALL os_get_euid (NvU32 *); @@ -181,7 +180,6 @@ NvU32 NV_API_CALL os_get_page_refcount (NvU64 address); NvU32 NV_API_CALL os_count_tail_pages (NvU64 address); void NV_API_CALL os_free_pages_phys (NvU64, NvU32); -NV_STATUS NV_API_CALL os_call_nv_vmbus (NvU32, void *); NV_STATUS NV_API_CALL os_open_temporary_file (void **); void NV_API_CALL os_close_file (void *); NV_STATUS NV_API_CALL os_write_file (void *, NvU8 *, NvU64, NvU64); @@ -189,7 +187,7 @@ NV_STATUS NV_API_CALL os_open_readonly_file (const char *, void **); NV_STATUS NV_API_CALL os_open_and_read_file (const char *, NvU8 *, NvU64); NvBool NV_API_CALL os_is_nvswitch_present (void); -void NV_API_CALL os_get_random_bytes (NvU8 *, NvU16); +NV_STATUS NV_API_CALL os_get_random_bytes (NvU8 *, NvU16); NV_STATUS NV_API_CALL os_alloc_wait_queue (os_wait_queue **); void NV_API_CALL os_free_wait_queue (os_wait_queue *); void NV_API_CALL os_wait_uninterruptible (os_wait_queue *); @@ -208,12 +206,19 @@ OS_INTF_PCIE_REQ_ATOMICS_128BIT }; NV_STATUS NV_API_CALL os_enable_pci_req_atomics (void *, enum os_pci_req_atomics_type); +NV_STATUS NV_API_CALL os_get_numa_node_memory_usage (NvS32, NvU64 *, NvU64 *); +NV_STATUS NV_API_CALL os_numa_add_gpu_memory (void *, NvU64, NvU64, NvU32 *); +NV_STATUS NV_API_CALL os_numa_remove_gpu_memory (void *, NvU64, NvU64, NvU32); +NV_STATUS NV_API_CALL os_offline_page_at_address(NvU64 address); +void* NV_API_CALL os_get_pid_info(void); +void NV_API_CALL os_put_pid_info(void *pid_info); +NV_STATUS NV_API_CALL os_find_ns_pid(void *pid_info, NvU32 *ns_pid); extern NvU32 os_page_size; extern NvU64 os_page_mask; extern NvU8 os_page_shift; -extern NvU32 os_sev_status; -extern NvBool os_sev_enabled; +extern NvBool os_cc_enabled; +extern NvBool os_cc_tdx_enabled; extern NvBool os_dma_buf_enabled; /* diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/arch/nvalloc/unix/include/osapi.h nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/arch/nvalloc/unix/include/osapi.h --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/arch/nvalloc/unix/include/osapi.h 2023-10-25 20:20:29.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/arch/nvalloc/unix/include/osapi.h 2024-03-05 22:12:47.000000000 +0000 @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 1999-2021 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 1999-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -130,6 +130,8 @@ void RmFreeX86EmuState(OBJGPU *); NV_STATUS RmPowerSourceChangeEvent(nv_state_t *, NvU32); +void RmRequestDNotifierState(nv_state_t *); + const NvU8 *RmGetGpuUuidRaw(nv_state_t *); NV_STATUS nv_vbios_call(OBJGPU *, NvU32 *, NvU32 *); diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/arch/nvalloc/unix/include/osfuncs.h nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/arch/nvalloc/unix/include/osfuncs.h --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/arch/nvalloc/unix/include/osfuncs.h 2023-10-25 20:20:29.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/arch/nvalloc/unix/include/osfuncs.h 2024-03-05 22:12:47.000000000 +0000 @@ -39,13 +39,6 @@ void* osGetStereoDongleInterface(void); -OSCallACPI_DSM osCallACPI_DSM; -OSCallACPI_DDC osCallACPI_DDC; -OSCallACPI_NVHG_ROM osCallACPI_NVHG_ROM; -OSCallACPI_DOD osCallACPI_DOD; -OSCallACPI_MXDS osCallACPI_MXDS; -OSCallACPI_MXDM osCallACPI_MXDM; - #if defined(NVCPU_X86_64) OSnv_rdcr4 nv_rdcr4; NvU64 nv_rdcr3(OBJOS *); diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/arch/nvalloc/unix/include/x86emu/debug.h nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/arch/nvalloc/unix/include/x86emu/debug.h --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/arch/nvalloc/unix/include/x86emu/debug.h 1970-01-01 00:00:00.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/arch/nvalloc/unix/include/x86emu/debug.h 2024-03-05 22:12:47.000000000 +0000 @@ -0,0 +1,211 @@ +/**************************************************************************** +* +* Realmode X86 Emulator Library +* +* Copyright (C) 1996-1999 SciTech Software, Inc. +* Copyright (C) David Mosberger-Tang +* Copyright (C) 1999 Egbert Eich +* +* ======================================================================== +* +* Permission to use, copy, modify, distribute, and sell this software and +* its documentation for any purpose is hereby granted without fee, +* provided that the above copyright notice appear in all copies and that +* both that copyright notice and this permission notice appear in +* supporting documentation, and that the name of the authors not be used +* in advertising or publicity pertaining to distribution of the software +* without specific, written prior permission. The authors makes no +* representations about the suitability of this software for any purpose. +* It is provided "as is" without express or implied warranty. +* +* THE AUTHORS DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOFTWARE, +* INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO +* EVENT SHALL THE AUTHORS BE LIABLE FOR ANY SPECIAL, INDIRECT OR +* CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF +* USE, DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR +* OTHER TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR +* PERFORMANCE OF THIS SOFTWARE. +* +* ======================================================================== +* +* Language: ANSI C +* Environment: Any +* Developer: Kendall Bennett +* +* Description: Header file for debug definitions. +* +****************************************************************************/ + +#ifndef __X86EMU_DEBUG_H +#define __X86EMU_DEBUG_H + +/*---------------------- Macros and type definitions ----------------------*/ + +/* checks to be enabled for "runtime" */ + +#define CHECK_IP_FETCH_F 0x1 +#define CHECK_SP_ACCESS_F 0x2 +#define CHECK_MEM_ACCESS_F 0x4 /*using regular linear pointer */ +#define CHECK_DATA_ACCESS_F 0x8 /*using segment:offset*/ + +#ifdef X86EMU_DEBUG +# define CHECK_IP_FETCH() (M.x86.check & CHECK_IP_FETCH_F) +# define CHECK_SP_ACCESS() (M.x86.check & CHECK_SP_ACCESS_F) +# define CHECK_MEM_ACCESS() (M.x86.check & CHECK_MEM_ACCESS_F) +# define CHECK_DATA_ACCESS() (M.x86.check & CHECK_DATA_ACCESS_F) +#else +# define CHECK_IP_FETCH() 0 +# define CHECK_SP_ACCESS() 0 +# define CHECK_MEM_ACCESS() 0 +# define CHECK_DATA_ACCESS() 0 +#endif + +#ifdef X86EMU_DEBUG +# define DEBUG_INSTRUMENT() (M.x86.debug & DEBUG_INSTRUMENT_F) +# define DEBUG_DECODE() (M.x86.debug & DEBUG_DECODE_F) +# define DEBUG_TRACE() (M.x86.debug & DEBUG_TRACE_F) +# define DEBUG_STEP() (M.x86.debug & DEBUG_STEP_F) +# define DEBUG_DISASSEMBLE() (M.x86.debug & DEBUG_DISASSEMBLE_F) +# define DEBUG_BREAK() (M.x86.debug & DEBUG_BREAK_F) +# define DEBUG_SVC() (M.x86.debug & DEBUG_SVC_F) +# define DEBUG_SAVE_IP_CS() (M.x86.debug & DEBUG_SAVE_IP_CS_F) + +# define DEBUG_FS() (M.x86.debug & DEBUG_FS_F) +# define DEBUG_PROC() (M.x86.debug & DEBUG_PROC_F) +# define DEBUG_SYSINT() (M.x86.debug & DEBUG_SYSINT_F) +# define DEBUG_TRACECALL() (M.x86.debug & DEBUG_TRACECALL_F) +# define DEBUG_TRACECALLREGS() (M.x86.debug & DEBUG_TRACECALL_REGS_F) +# define DEBUG_SYS() (M.x86.debug & DEBUG_SYS_F) +# define DEBUG_MEM_TRACE() (M.x86.debug & DEBUG_MEM_TRACE_F) +# define DEBUG_IO_TRACE() (M.x86.debug & DEBUG_IO_TRACE_F) +# define DEBUG_DECODE_NOPRINT() (M.x86.debug & DEBUG_DECODE_NOPRINT_F) +#else +# define DEBUG_INSTRUMENT() 0 +# define DEBUG_DECODE() 0 +# define DEBUG_TRACE() 0 +# define DEBUG_STEP() 0 +# define DEBUG_DISASSEMBLE() 0 +# define DEBUG_BREAK() 0 +# define DEBUG_SVC() 0 +# define DEBUG_SAVE_IP_CS() 0 +# define DEBUG_FS() 0 +# define DEBUG_PROC() 0 +# define DEBUG_SYSINT() 0 +# define DEBUG_TRACECALL() 0 +# define DEBUG_TRACECALLREGS() 0 +# define DEBUG_SYS() 0 +# define DEBUG_MEM_TRACE() 0 +# define DEBUG_IO_TRACE() 0 +# define DEBUG_DECODE_NOPRINT() 0 +#endif + +#ifdef X86EMU_DEBUG + +# define DECODE_PRINTF(x) if (DEBUG_DECODE()) \ + x86emu_decode_printf(x) +# define DECODE_PRINTF2(x,y) if (DEBUG_DECODE()) \ + x86emu_decode_printf2(x,y) + +/* + * The following allow us to look at the bytes of an instruction. The + * first INCR_INSTRN_LEN, is called everytime bytes are consumed in + * the decoding process. The SAVE_IP_CS is called initially when the + * major opcode of the instruction is accessed. + */ +#define INC_DECODED_INST_LEN(x) \ + if (DEBUG_DECODE()) \ + x86emu_inc_decoded_inst_len(x) + +#define SAVE_IP_CS(x,y) \ + if (DEBUG_DECODE() | DEBUG_TRACECALL() | DEBUG_BREAK() \ + | DEBUG_IO_TRACE() | DEBUG_SAVE_IP_CS()) { \ + M.x86.saved_cs = x; \ + M.x86.saved_ip = y; \ + } +#else +# define INC_DECODED_INST_LEN(x) +# define DECODE_PRINTF(x) +# define DECODE_PRINTF2(x,y) +# define SAVE_IP_CS(x,y) +#endif + +#ifdef X86EMU_DEBUG +#define TRACE_REGS() \ + if (DEBUG_DISASSEMBLE()) { \ + x86emu_just_disassemble(); \ + goto EndOfTheInstructionProcedure; \ + } \ + if (DEBUG_TRACE() || DEBUG_DECODE()) X86EMU_trace_regs() +#else +# define TRACE_REGS() +#endif + +#ifdef X86EMU_DEBUG +# define SINGLE_STEP() if (DEBUG_STEP()) x86emu_single_step() +#else +# define SINGLE_STEP() +#endif + +#define TRACE_AND_STEP() \ + TRACE_REGS(); \ + SINGLE_STEP() + +#ifdef X86EMU_DEBUG +# define START_OF_INSTR() +# define END_OF_INSTR() EndOfTheInstructionProcedure: x86emu_end_instr(); +# define END_OF_INSTR_NO_TRACE() x86emu_end_instr(); +#else +# define START_OF_INSTR() +# define END_OF_INSTR() +# define END_OF_INSTR_NO_TRACE() +#endif + +#ifdef X86EMU_DEBUG +#include +# define CALL_TRACE(u,v,w,x,s) \ + if (DEBUG_TRACECALLREGS()) \ + x86emu_dump_regs(); \ + if (DEBUG_TRACECALL()) \ + NV_PRINTF(LEVEL_INFO, "%04x:%04x: CALL %s%04x:%04x\n", u , v, s, w, x); +# define RETURN_TRACE(n,u,v) \ + if (DEBUG_TRACECALLREGS()) \ + x86emu_dump_regs(); \ + if (DEBUG_TRACECALL()) \ + NV_PRINTF(LEVEL_INFO, "%04x:%04x: %s\n",u,v,n); +#else +# define CALL_TRACE(u,v,w,x,s) +# define RETURN_TRACE(n,u,v) +#endif + +#ifdef X86EMU_DEBUG +#define DB(x) x +#else +#define DB(x) +#endif + +/*-------------------------- Function Prototypes --------------------------*/ + +#ifdef __cplusplus +extern "C" { /* Use "C" linkage when in C++ mode */ +#endif + +extern void x86emu_inc_decoded_inst_len (int x); +extern void x86emu_decode_printf (const char *x); +extern void x86emu_decode_printf2 (const char *x, int y); +extern void x86emu_just_disassemble (void); +extern void x86emu_single_step (void); +extern void x86emu_end_instr (void); +extern void x86emu_dump_regs (void); +extern void x86emu_dump_xregs (void); +extern void x86emu_print_int_vect (u16 iv); +extern void x86emu_instrument_instruction (void); +extern void x86emu_check_ip_access (void); +extern void x86emu_check_sp_access (void); +extern void x86emu_check_mem_access (u32 p); +extern void x86emu_check_data_access (uint s, uint o); + +#ifdef __cplusplus +} /* End of "C" linkage for C++ */ +#endif + +#endif /* __X86EMU_DEBUG_H */ diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/arch/nvalloc/unix/include/x86emu/decode.h nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/arch/nvalloc/unix/include/x86emu/decode.h --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/arch/nvalloc/unix/include/x86emu/decode.h 1970-01-01 00:00:00.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/arch/nvalloc/unix/include/x86emu/decode.h 2024-03-05 22:12:47.000000000 +0000 @@ -0,0 +1,88 @@ +/**************************************************************************** +* +* Realmode X86 Emulator Library +* +* Copyright (C) 1996-1999 SciTech Software, Inc. +* Copyright (C) David Mosberger-Tang +* Copyright (C) 1999 Egbert Eich +* +* ======================================================================== +* +* Permission to use, copy, modify, distribute, and sell this software and +* its documentation for any purpose is hereby granted without fee, +* provided that the above copyright notice appear in all copies and that +* both that copyright notice and this permission notice appear in +* supporting documentation, and that the name of the authors not be used +* in advertising or publicity pertaining to distribution of the software +* without specific, written prior permission. The authors makes no +* representations about the suitability of this software for any purpose. +* It is provided "as is" without express or implied warranty. +* +* THE AUTHORS DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOFTWARE, +* INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO +* EVENT SHALL THE AUTHORS BE LIABLE FOR ANY SPECIAL, INDIRECT OR +* CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF +* USE, DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR +* OTHER TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR +* PERFORMANCE OF THIS SOFTWARE. +* +* ======================================================================== +* +* Language: ANSI C +* Environment: Any +* Developer: Kendall Bennett +* +* Description: Header file for instruction decoding logic. +* +****************************************************************************/ + +#ifndef __X86EMU_DECODE_H +#define __X86EMU_DECODE_H + +/*---------------------- Macros and type definitions ----------------------*/ + +/* Instruction Decoding Stuff */ + +#define FETCH_DECODE_MODRM(mod,rh,rl) fetch_decode_modrm(&mod,&rh,&rl) +#define DECODE_RM_BYTE_REGISTER(r) decode_rm_byte_register(r) +#define DECODE_RM_WORD_REGISTER(r) decode_rm_word_register(r) +#define DECODE_RM_LONG_REGISTER(r) decode_rm_long_register(r) +#define DECODE_CLEAR_SEGOVR() M.x86.mode &= ~SYSMODE_CLRMASK + +/*-------------------------- Function Prototypes --------------------------*/ + +#ifdef __cplusplus +extern "C" { /* Use "C" linkage when in C++ mode */ +#endif + +void x86emu_intr_raise (u8 type); +void fetch_decode_modrm (int *mod,int *regh,int *regl); +u8 fetch_byte_imm (void); +u16 fetch_word_imm (void); +u32 fetch_long_imm (void); +u8 fetch_data_byte (uint offset); +u8 fetch_data_byte_abs (uint segment, uint offset); +u16 fetch_data_word (uint offset); +u16 fetch_data_word_abs (uint segment, uint offset); +u32 fetch_data_long (uint offset); +u32 fetch_data_long_abs (uint segment, uint offset); +void store_data_byte (uint offset, u8 val); +void store_data_byte_abs (uint segment, uint offset, u8 val); +void store_data_word (uint offset, u16 val); +void store_data_word_abs (uint segment, uint offset, u16 val); +void store_data_long (uint offset, u32 val); +void store_data_long_abs (uint segment, uint offset, u32 val); +u8* decode_rm_byte_register(int reg); +u16* decode_rm_word_register(int reg); +u32* decode_rm_long_register(int reg); +u16* decode_rm_seg_register(int reg); +u32 decode_rm00_address(int rm); +u32 decode_rm01_address(int rm); +u32 decode_rm10_address(int rm); +u32 decode_sib_address(int sib, int mod); + +#ifdef __cplusplus +} /* End of "C" linkage for C++ */ +#endif + +#endif /* __X86EMU_DECODE_H */ diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/arch/nvalloc/unix/include/x86emu/fpu.h nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/arch/nvalloc/unix/include/x86emu/fpu.h --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/arch/nvalloc/unix/include/x86emu/fpu.h 1970-01-01 00:00:00.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/arch/nvalloc/unix/include/x86emu/fpu.h 2024-03-05 22:12:47.000000000 +0000 @@ -0,0 +1,61 @@ +/**************************************************************************** +* +* Realmode X86 Emulator Library +* +* Copyright (C) 1996-1999 SciTech Software, Inc. +* Copyright (C) David Mosberger-Tang +* Copyright (C) 1999 Egbert Eich +* +* ======================================================================== +* +* Permission to use, copy, modify, distribute, and sell this software and +* its documentation for any purpose is hereby granted without fee, +* provided that the above copyright notice appear in all copies and that +* both that copyright notice and this permission notice appear in +* supporting documentation, and that the name of the authors not be used +* in advertising or publicity pertaining to distribution of the software +* without specific, written prior permission. The authors makes no +* representations about the suitability of this software for any purpose. +* It is provided "as is" without express or implied warranty. +* +* THE AUTHORS DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOFTWARE, +* INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO +* EVENT SHALL THE AUTHORS BE LIABLE FOR ANY SPECIAL, INDIRECT OR +* CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF +* USE, DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR +* OTHER TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR +* PERFORMANCE OF THIS SOFTWARE. +* +* ======================================================================== +* +* Language: ANSI C +* Environment: Any +* Developer: Kendall Bennett +* +* Description: Header file for FPU instruction decoding. +* +****************************************************************************/ + +#ifndef __X86EMU_FPU_H +#define __X86EMU_FPU_H + +#ifdef __cplusplus +extern "C" { /* Use "C" linkage when in C++ mode */ +#endif + +/* these have to be defined, whether 8087 support compiled in or not. */ + +extern void x86emuOp_esc_coprocess_d8 (u8 op1); +extern void x86emuOp_esc_coprocess_d9 (u8 op1); +extern void x86emuOp_esc_coprocess_da (u8 op1); +extern void x86emuOp_esc_coprocess_db (u8 op1); +extern void x86emuOp_esc_coprocess_dc (u8 op1); +extern void x86emuOp_esc_coprocess_dd (u8 op1); +extern void x86emuOp_esc_coprocess_de (u8 op1); +extern void x86emuOp_esc_coprocess_df (u8 op1); + +#ifdef __cplusplus +} /* End of "C" linkage for C++ */ +#endif + +#endif /* __X86EMU_FPU_H */ diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/arch/nvalloc/unix/include/x86emu/fpu_regs.h nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/arch/nvalloc/unix/include/x86emu/fpu_regs.h --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/arch/nvalloc/unix/include/x86emu/fpu_regs.h 1970-01-01 00:00:00.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/arch/nvalloc/unix/include/x86emu/fpu_regs.h 2024-03-05 22:12:47.000000000 +0000 @@ -0,0 +1,119 @@ +/**************************************************************************** +* +* Realmode X86 Emulator Library +* +* Copyright (C) 1996-1999 SciTech Software, Inc. +* Copyright (C) David Mosberger-Tang +* Copyright (C) 1999 Egbert Eich +* +* ======================================================================== +* +* Permission to use, copy, modify, distribute, and sell this software and +* its documentation for any purpose is hereby granted without fee, +* provided that the above copyright notice appear in all copies and that +* both that copyright notice and this permission notice appear in +* supporting documentation, and that the name of the authors not be used +* in advertising or publicity pertaining to distribution of the software +* without specific, written prior permission. The authors makes no +* representations about the suitability of this software for any purpose. +* It is provided "as is" without express or implied warranty. +* +* THE AUTHORS DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOFTWARE, +* INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO +* EVENT SHALL THE AUTHORS BE LIABLE FOR ANY SPECIAL, INDIRECT OR +* CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF +* USE, DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR +* OTHER TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR +* PERFORMANCE OF THIS SOFTWARE. +* +* ======================================================================== +* +* Language: ANSI C +* Environment: Any +* Developer: Kendall Bennett +* +* Description: Header file for FPU register definitions. +* +****************************************************************************/ + +#ifndef __X86EMU_FPU_REGS_H +#define __X86EMU_FPU_REGS_H + +#ifdef X86_FPU_SUPPORT + +#ifdef PACK +# pragma PACK +#endif + +/* Basic 8087 register can hold any of the following values: */ + +union x86_fpu_reg_u { + s8 tenbytes[10]; + double dval; + float fval; + s16 sval; + s32 lval; + }; + +struct x86_fpu_reg { + union x86_fpu_reg_u reg; + char tag; + }; + +/* + * Since we are not going to worry about the problems of aliasing + * registers, every time a register is modified, its result type is + * set in the tag fields for that register. If some operation + * attempts to access the type in a way inconsistent with its current + * storage format, then we flag the operation. If common, we'll + * attempt the conversion. + */ + +#define X86_FPU_VALID 0x80 +#define X86_FPU_REGTYP(r) ((r) & 0x7F) + +#define X86_FPU_WORD 0x0 +#define X86_FPU_SHORT 0x1 +#define X86_FPU_LONG 0x2 +#define X86_FPU_FLOAT 0x3 +#define X86_FPU_DOUBLE 0x4 +#define X86_FPU_LDBL 0x5 +#define X86_FPU_BSD 0x6 + +#define X86_FPU_STKTOP 0 + +struct x86_fpu_registers { + struct x86_fpu_reg x86_fpu_stack[8]; + int x86_fpu_flags; + int x86_fpu_config; /* rounding modes, etc. */ + short x86_fpu_tos, x86_fpu_bos; + }; + +#ifdef END_PACK +# pragma END_PACK +#endif + +/* + * There are two versions of the following macro. + * + * One version is for opcode D9, for which there are more than 32 + * instructions encoded in the second byte of the opcode. + * + * The other version, deals with all the other 7 i87 opcodes, for + * which there are only 32 strings needed to describe the + * instructions. + */ + +#endif /* X86_FPU_SUPPORT */ + +#ifdef X86EMU_DEBUG +# define DECODE_PRINTINSTR32(t,mod,rh,rl) \ + DECODE_PRINTF(t[(mod<<3)+(rh)]); +# define DECODE_PRINTINSTR256(t,mod,rh,rl) \ + DECODE_PRINTF(t[(mod<<6)+(rh<<3)+(rl)]); +#else +# define DECODE_PRINTINSTR32(t,mod,rh,rl) +# define DECODE_PRINTINSTR256(t,mod,rh,rl) +#endif + +#endif /* __X86EMU_FPU_REGS_H */ diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/arch/nvalloc/unix/include/x86emu/ops.h nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/arch/nvalloc/unix/include/x86emu/ops.h --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/arch/nvalloc/unix/include/x86emu/ops.h 1970-01-01 00:00:00.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/arch/nvalloc/unix/include/x86emu/ops.h 2024-03-05 22:12:47.000000000 +0000 @@ -0,0 +1,45 @@ +/**************************************************************************** +* +* Realmode X86 Emulator Library +* +* Copyright (C) 1996-1999 SciTech Software, Inc. +* Copyright (C) David Mosberger-Tang +* Copyright (C) 1999 Egbert Eich +* +* ======================================================================== +* +* Permission to use, copy, modify, distribute, and sell this software and +* its documentation for any purpose is hereby granted without fee, +* provided that the above copyright notice appear in all copies and that +* both that copyright notice and this permission notice appear in +* supporting documentation, and that the name of the authors not be used +* in advertising or publicity pertaining to distribution of the software +* without specific, written prior permission. The authors makes no +* representations about the suitability of this software for any purpose. +* It is provided "as is" without express or implied warranty. +* +* THE AUTHORS DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOFTWARE, +* INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO +* EVENT SHALL THE AUTHORS BE LIABLE FOR ANY SPECIAL, INDIRECT OR +* CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF +* USE, DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR +* OTHER TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR +* PERFORMANCE OF THIS SOFTWARE. +* +* ======================================================================== +* +* Language: ANSI C +* Environment: Any +* Developer: Kendall Bennett +* +* Description: Header file for operand decoding functions. +* +****************************************************************************/ + +#ifndef __X86EMU_OPS_H +#define __X86EMU_OPS_H + +extern void (*x86emu_optab[0x100])(u8 op1); +extern void (*x86emu_optab2[0x100])(u8 op2); + +#endif /* __X86EMU_OPS_H */ diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/arch/nvalloc/unix/include/x86emu/prim_ops.h nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/arch/nvalloc/unix/include/x86emu/prim_ops.h --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/arch/nvalloc/unix/include/x86emu/prim_ops.h 1970-01-01 00:00:00.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/arch/nvalloc/unix/include/x86emu/prim_ops.h 2024-03-05 22:12:48.000000000 +0000 @@ -0,0 +1,141 @@ +/**************************************************************************** +* +* Realmode X86 Emulator Library +* +* Copyright (C) 1996-1999 SciTech Software, Inc. +* Copyright (C) David Mosberger-Tang +* Copyright (C) 1999 Egbert Eich +* +* ======================================================================== +* +* Permission to use, copy, modify, distribute, and sell this software and +* its documentation for any purpose is hereby granted without fee, +* provided that the above copyright notice appear in all copies and that +* both that copyright notice and this permission notice appear in +* supporting documentation, and that the name of the authors not be used +* in advertising or publicity pertaining to distribution of the software +* without specific, written prior permission. The authors makes no +* representations about the suitability of this software for any purpose. +* It is provided "as is" without express or implied warranty. +* +* THE AUTHORS DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOFTWARE, +* INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO +* EVENT SHALL THE AUTHORS BE LIABLE FOR ANY SPECIAL, INDIRECT OR +* CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF +* USE, DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR +* OTHER TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR +* PERFORMANCE OF THIS SOFTWARE. +* +* ======================================================================== +* +* Language: ANSI C +* Environment: Any +* Developer: Kendall Bennett +* +* Description: Header file for primitive operation functions. +* +****************************************************************************/ + +#ifndef __X86EMU_PRIM_OPS_H +#define __X86EMU_PRIM_OPS_H + +#ifdef __cplusplus +extern "C" { /* Use "C" linkage when in C++ mode */ +#endif + +u16 aaa_word (u16 d); +u16 aas_word (u16 d); +u16 aad_word (u16 d); +u16 aam_word (u8 d); +u8 adc_byte (u8 d, u8 s); +u16 adc_word (u16 d, u16 s); +u32 adc_long (u32 d, u32 s); +u8 add_byte (u8 d, u8 s); +u16 add_word (u16 d, u16 s); +u32 add_long (u32 d, u32 s); +u8 and_byte (u8 d, u8 s); +u16 and_word (u16 d, u16 s); +u32 and_long (u32 d, u32 s); +u8 cmp_byte (u8 d, u8 s); +u16 cmp_word (u16 d, u16 s); +u32 cmp_long (u32 d, u32 s); +u8 daa_byte (u8 d); +u8 das_byte (u8 d); +u8 dec_byte (u8 d); +u16 dec_word (u16 d); +u32 dec_long (u32 d); +u8 inc_byte (u8 d); +u16 inc_word (u16 d); +u32 inc_long (u32 d); +u8 or_byte (u8 d, u8 s); +u16 or_word (u16 d, u16 s); +u32 or_long (u32 d, u32 s); +u8 neg_byte (u8 s); +u16 neg_word (u16 s); +u32 neg_long (u32 s); +u8 not_byte (u8 s); +u16 not_word (u16 s); +u32 not_long (u32 s); +u8 rcl_byte (u8 d, u8 s); +u16 rcl_word (u16 d, u8 s); +u32 rcl_long (u32 d, u8 s); +u8 rcr_byte (u8 d, u8 s); +u16 rcr_word (u16 d, u8 s); +u32 rcr_long (u32 d, u8 s); +u8 rol_byte (u8 d, u8 s); +u16 rol_word (u16 d, u8 s); +u32 rol_long (u32 d, u8 s); +u8 ror_byte (u8 d, u8 s); +u16 ror_word (u16 d, u8 s); +u32 ror_long (u32 d, u8 s); +u8 shl_byte (u8 d, u8 s); +u16 shl_word (u16 d, u8 s); +u32 shl_long (u32 d, u8 s); +u8 shr_byte (u8 d, u8 s); +u16 shr_word (u16 d, u8 s); +u32 shr_long (u32 d, u8 s); +u8 sar_byte (u8 d, u8 s); +u16 sar_word (u16 d, u8 s); +u32 sar_long (u32 d, u8 s); +u16 shld_word (u16 d, u16 fill, u8 s); +u32 shld_long (u32 d, u32 fill, u8 s); +u16 shrd_word (u16 d, u16 fill, u8 s); +u32 shrd_long (u32 d, u32 fill, u8 s); +u8 sbb_byte (u8 d, u8 s); +u16 sbb_word (u16 d, u16 s); +u32 sbb_long (u32 d, u32 s); +u8 sub_byte (u8 d, u8 s); +u16 sub_word (u16 d, u16 s); +u32 sub_long (u32 d, u32 s); +void test_byte (u8 d, u8 s); +void test_word (u16 d, u16 s); +void test_long (u32 d, u32 s); +u8 xor_byte (u8 d, u8 s); +u16 xor_word (u16 d, u16 s); +u32 xor_long (u32 d, u32 s); +void imul_byte (u8 s); +void imul_word (u16 s); +void imul_long (u32 s); +void imul_long_direct(u32 *res_lo, u32* res_hi,u32 d, u32 s); +void mul_byte (u8 s); +void mul_word (u16 s); +void mul_long (u32 s); +void idiv_byte (u8 s); +void idiv_word (u16 s); +void idiv_long (u32 s); +void div_byte (u8 s); +void div_word (u16 s); +void div_long (u32 s); +void ins (int size); +void outs (int size); +u16 mem_access_word (int addr); +void push_word (u16 w); +void push_long (u32 w); +u16 pop_word (void); +u32 pop_long (void); + +#ifdef __cplusplus +} /* End of "C" linkage for C++ */ +#endif + +#endif /* __X86EMU_PRIM_OPS_H */ diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/arch/nvalloc/unix/include/x86emu/regs.h nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/arch/nvalloc/unix/include/x86emu/regs.h --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/arch/nvalloc/unix/include/x86emu/regs.h 1970-01-01 00:00:00.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/arch/nvalloc/unix/include/x86emu/regs.h 2024-03-05 22:12:48.000000000 +0000 @@ -0,0 +1,340 @@ +/**************************************************************************** +* +* Realmode X86 Emulator Library +* +* Copyright (C) 1996-1999 SciTech Software, Inc. +* Copyright (C) David Mosberger-Tang +* Copyright (C) 1999 Egbert Eich +* +* ======================================================================== +* +* Permission to use, copy, modify, distribute, and sell this software and +* its documentation for any purpose is hereby granted without fee, +* provided that the above copyright notice appear in all copies and that +* both that copyright notice and this permission notice appear in +* supporting documentation, and that the name of the authors not be used +* in advertising or publicity pertaining to distribution of the software +* without specific, written prior permission. The authors makes no +* representations about the suitability of this software for any purpose. +* It is provided "as is" without express or implied warranty. +* +* THE AUTHORS DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOFTWARE, +* INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO +* EVENT SHALL THE AUTHORS BE LIABLE FOR ANY SPECIAL, INDIRECT OR +* CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF +* USE, DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR +* OTHER TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR +* PERFORMANCE OF THIS SOFTWARE. +* +* ======================================================================== +* +* Language: ANSI C +* Environment: Any +* Developer: Kendall Bennett +* +* Description: Header file for x86 register definitions. +* +****************************************************************************/ + +#ifndef __X86EMU_REGS_H +#define __X86EMU_REGS_H + +#include "x86emu/debug.h" + +/*---------------------- Macros and type definitions ----------------------*/ + +#ifdef PACK +# pragma PACK +#endif + +/* + * General EAX, EBX, ECX, EDX type registers. Note that for + * portability, and speed, the issue of byte swapping is not addressed + * in the registers. All registers are stored in the default format + * available on the host machine. The only critical issue is that the + * registers should line up EXACTLY in the same manner as they do in + * the 386. That is: + * + * EAX & 0xff === AL + * EAX & 0xffff == AX + * + * etc. The result is that alot of the calculations can then be + * done using the native instruction set fully. + */ + +#ifdef __BIG_ENDIAN__ + +typedef struct { + u32 e_reg; + } I32_reg_t; + +typedef struct { + u16 filler0, x_reg; + } I16_reg_t; + +typedef struct { + u8 filler0, filler1, h_reg, l_reg; + } I8_reg_t; + +#else /* !__BIG_ENDIAN__ */ + +typedef struct { + u32 e_reg; + } I32_reg_t; + +typedef struct { + u16 x_reg; + } I16_reg_t; + +typedef struct { + u8 l_reg, h_reg; + } I8_reg_t; + +#endif /* __BIG_ENDIAN__ */ + +typedef union { + I32_reg_t I32_reg; + I16_reg_t I16_reg; + I8_reg_t I8_reg; + } i386_general_register; + +struct i386_general_regs { + i386_general_register A, B, C, D; + }; + +typedef struct i386_general_regs Gen_reg_t; + +struct i386_special_regs { + i386_general_register SP, BP, SI, DI, IP; + u32 FLAGS; + }; + +/* + * Segment registers here represent the 16 bit quantities + * CS, DS, ES, SS. + */ + +struct i386_segment_regs { + u16 CS, DS, SS, ES, FS, GS; + }; + +/* 8 bit registers */ +#define R_AH gen.A.I8_reg.h_reg +#define R_AL gen.A.I8_reg.l_reg +#define R_BH gen.B.I8_reg.h_reg +#define R_BL gen.B.I8_reg.l_reg +#define R_CH gen.C.I8_reg.h_reg +#define R_CL gen.C.I8_reg.l_reg +#define R_DH gen.D.I8_reg.h_reg +#define R_DL gen.D.I8_reg.l_reg + +/* 16 bit registers */ +#define R_AX gen.A.I16_reg.x_reg +#define R_BX gen.B.I16_reg.x_reg +#define R_CX gen.C.I16_reg.x_reg +#define R_DX gen.D.I16_reg.x_reg + +/* 32 bit extended registers */ +#define R_EAX gen.A.I32_reg.e_reg +#define R_EBX gen.B.I32_reg.e_reg +#define R_ECX gen.C.I32_reg.e_reg +#define R_EDX gen.D.I32_reg.e_reg + +/* special registers */ +#define R_SP spc.SP.I16_reg.x_reg +#define R_BP spc.BP.I16_reg.x_reg +#define R_SI spc.SI.I16_reg.x_reg +#define R_DI spc.DI.I16_reg.x_reg +#define R_IP spc.IP.I16_reg.x_reg +#define R_FLG spc.FLAGS + +/* special registers */ +#define R_SP spc.SP.I16_reg.x_reg +#define R_BP spc.BP.I16_reg.x_reg +#define R_SI spc.SI.I16_reg.x_reg +#define R_DI spc.DI.I16_reg.x_reg +#define R_IP spc.IP.I16_reg.x_reg +#define R_FLG spc.FLAGS + +/* special registers */ +#define R_ESP spc.SP.I32_reg.e_reg +#define R_EBP spc.BP.I32_reg.e_reg +#define R_ESI spc.SI.I32_reg.e_reg +#define R_EDI spc.DI.I32_reg.e_reg +#define R_EIP spc.IP.I32_reg.e_reg +#define R_EFLG spc.FLAGS + +/* segment registers */ +#define R_CS seg.CS +#define R_DS seg.DS +#define R_SS seg.SS +#define R_ES seg.ES +#define R_FS seg.FS +#define R_GS seg.GS + +/* flag conditions */ +#define FB_CF 0x0001 /* CARRY flag */ +#define FB_PF 0x0004 /* PARITY flag */ +#define FB_AF 0x0010 /* AUX flag */ +#define FB_ZF 0x0040 /* ZERO flag */ +#define FB_SF 0x0080 /* SIGN flag */ +#define FB_TF 0x0100 /* TRAP flag */ +#define FB_IF 0x0200 /* INTERRUPT ENABLE flag */ +#define FB_DF 0x0400 /* DIR flag */ +#define FB_OF 0x0800 /* OVERFLOW flag */ + +/* 80286 and above always have bit#1 set */ +#define F_ALWAYS_ON (0x0002) /* flag bits always on */ + +/* + * Define a mask for only those flag bits we will ever pass back + * (via PUSHF) + */ +#define F_MSK (FB_CF|FB_PF|FB_AF|FB_ZF|FB_SF|FB_TF|FB_IF|FB_DF|FB_OF) + +/* following bits masked in to a 16bit quantity */ + +#define F_CF 0x0001 /* CARRY flag */ +#define F_PF 0x0004 /* PARITY flag */ +#define F_AF 0x0010 /* AUX flag */ +#define F_ZF 0x0040 /* ZERO flag */ +#define F_SF 0x0080 /* SIGN flag */ +#define F_TF 0x0100 /* TRAP flag */ +#define F_IF 0x0200 /* INTERRUPT ENABLE flag */ +#define F_DF 0x0400 /* DIR flag */ +#define F_OF 0x0800 /* OVERFLOW flag */ + +#define TOGGLE_FLAG(flag) (M.x86.R_FLG ^= (flag)) +#define SET_FLAG(flag) (M.x86.R_FLG |= (flag)) +#define CLEAR_FLAG(flag) (M.x86.R_FLG &= ~(flag)) +#define ACCESS_FLAG(flag) (M.x86.R_FLG & (flag)) +#define CLEARALL_FLAG(m) (M.x86.R_FLG = 0) + +#define CONDITIONAL_SET_FLAG(COND,FLAG) \ + if (COND) SET_FLAG(FLAG); else CLEAR_FLAG(FLAG) + +#define F_PF_CALC 0x010000 /* PARITY flag has been calced */ +#define F_ZF_CALC 0x020000 /* ZERO flag has been calced */ +#define F_SF_CALC 0x040000 /* SIGN flag has been calced */ + +#define F_ALL_CALC 0xff0000 /* All have been calced */ + +/* + * Emulator machine state. + * Segment usage control. + */ +#define SYSMODE_SEG_DS_SS 0x00000001 +#define SYSMODE_SEGOVR_CS 0x00000002 +#define SYSMODE_SEGOVR_DS 0x00000004 +#define SYSMODE_SEGOVR_ES 0x00000008 +#define SYSMODE_SEGOVR_FS 0x00000010 +#define SYSMODE_SEGOVR_GS 0x00000020 +#define SYSMODE_SEGOVR_SS 0x00000040 +#define SYSMODE_PREFIX_REPE 0x00000080 +#define SYSMODE_PREFIX_REPNE 0x00000100 +#define SYSMODE_PREFIX_DATA 0x00000200 +#define SYSMODE_PREFIX_ADDR 0x00000400 +#define SYSMODE_INTR_PENDING 0x10000000 +#define SYSMODE_EXTRN_INTR 0x20000000 +#define SYSMODE_HALTED 0x40000000 + +#define SYSMODE_SEGMASK (SYSMODE_SEG_DS_SS | \ + SYSMODE_SEGOVR_CS | \ + SYSMODE_SEGOVR_DS | \ + SYSMODE_SEGOVR_ES | \ + SYSMODE_SEGOVR_FS | \ + SYSMODE_SEGOVR_GS | \ + SYSMODE_SEGOVR_SS) +#define SYSMODE_CLRMASK (SYSMODE_SEG_DS_SS | \ + SYSMODE_SEGOVR_CS | \ + SYSMODE_SEGOVR_DS | \ + SYSMODE_SEGOVR_ES | \ + SYSMODE_SEGOVR_FS | \ + SYSMODE_SEGOVR_GS | \ + SYSMODE_SEGOVR_SS | \ + SYSMODE_PREFIX_DATA | \ + SYSMODE_PREFIX_ADDR) + +#define INTR_SYNCH 0x1 +#define INTR_ASYNCH 0x2 +#define INTR_HALTED 0x4 + +typedef struct { + struct i386_general_regs gen; + struct i386_special_regs spc; + struct i386_segment_regs seg; + /* + * MODE contains information on: + * REPE prefix 2 bits repe,repne + * SEGMENT overrides 5 bits normal,DS,SS,CS,ES + * Delayed flag set 3 bits (zero, signed, parity) + * reserved 6 bits + * interrupt # 8 bits instruction raised interrupt + * BIOS video segregs 4 bits + * Interrupt Pending 1 bits + * Extern interrupt 1 bits + * Halted 1 bits + */ + u32 mode; + volatile int intr; /* mask of pending interrupts */ + int debug; +#ifdef X86EMU_DEBUG + int check; + u16 saved_ip; + u16 saved_cs; + int enc_pos; + int enc_str_pos; + char decode_buf[32]; /* encoded byte stream */ + char decoded_buf[256]; /* disassembled strings */ + char debug_cmd[64]; /* input for x86emu_single_step */ +#endif + u8 intno; + u8 __pad[3]; + } X86EMU_regs; + +/**************************************************************************** +REMARKS: +Structure maintaining the emulator machine state. + +MEMBERS: +mem_base - Base real mode memory for the emulator +mem_size - Size of the real mode memory block for the emulator +private - private data pointer +x86 - X86 registers +****************************************************************************/ +typedef struct { + unsigned long mem_base; + unsigned long mem_size; + void* private; + X86EMU_regs x86; + } X86EMU_sysEnv; + +#ifdef END_PACK +# pragma END_PACK +#endif + +/*----------------------------- Global Variables --------------------------*/ + +#ifdef __cplusplus +extern "C" { /* Use "C" linkage when in C++ mode */ +#endif + +/* Global emulator machine state. + * + * We keep it global to avoid pointer dereferences in the code for speed. + */ + +extern X86EMU_sysEnv _X86EMU_env; +#define M _X86EMU_env + +/*-------------------------- Function Prototypes --------------------------*/ + +/* Function to log information at runtime */ + +void printk(const char *fmt, ...); + +#ifdef __cplusplus +} /* End of "C" linkage for C++ */ +#endif + +#endif /* __X86EMU_REGS_H */ diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/arch/nvalloc/unix/include/x86emu/types.h nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/arch/nvalloc/unix/include/x86emu/types.h --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/arch/nvalloc/unix/include/x86emu/types.h 1970-01-01 00:00:00.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/arch/nvalloc/unix/include/x86emu/types.h 2024-03-05 22:12:48.000000000 +0000 @@ -0,0 +1,93 @@ +/**************************************************************************** +* +* Realmode X86 Emulator Library +* +* Copyright (C) 1996-1999 SciTech Software, Inc. +* Copyright (C) David Mosberger-Tang +* Copyright (C) 1999 Egbert Eich +* +* ======================================================================== +* +* Permission to use, copy, modify, distribute, and sell this software and +* its documentation for any purpose is hereby granted without fee, +* provided that the above copyright notice appear in all copies and that +* both that copyright notice and this permission notice appear in +* supporting documentation, and that the name of the authors not be used +* in advertising or publicity pertaining to distribution of the software +* without specific, written prior permission. The authors makes no +* representations about the suitability of this software for any purpose. +* It is provided "as is" without express or implied warranty. +* +* THE AUTHORS DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOFTWARE, +* INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO +* EVENT SHALL THE AUTHORS BE LIABLE FOR ANY SPECIAL, INDIRECT OR +* CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF +* USE, DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR +* OTHER TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR +* PERFORMANCE OF THIS SOFTWARE. +* +* ======================================================================== +* +* Language: ANSI C +* Environment: Any +* Developer: Kendall Bennett +* +* Description: Header file for x86 emulator type definitions. +* +****************************************************************************/ + + +#ifndef __X86EMU_TYPES_H +#define __X86EMU_TYPES_H + +#ifndef NO_SYS_HEADERS +#include +#endif + +/* + * The following kludge is an attempt to work around typedef conflicts with + * . + */ +#define u8 x86emuu8 +#define u16 x86emuu16 +#define u32 x86emuu32 +#define u64 x86emuu64 +#define s8 x86emus8 +#define s16 x86emus16 +#define s32 x86emus32 +#define s64 x86emus64 +#define uint x86emuuint +#define sint x86emusint + +/*---------------------- Macros and type definitions ----------------------*/ + +/* Currently only for Linux/32bit */ +#undef __HAS_LONG_LONG__ +#if defined(__GNUC__) && !defined(NO_LONG_LONG) +#define __HAS_LONG_LONG__ +#endif + +#define NUM32 int + +typedef unsigned char u8; +typedef unsigned short u16; +typedef unsigned NUM32 u32; +#ifdef __HAS_LONG_LONG__ +typedef unsigned long long u64; +#endif + +typedef char s8; +typedef short s16; +typedef NUM32 s32; +#ifdef __HAS_LONG_LONG__ +typedef long long s64; +#endif + +typedef unsigned int uint; +typedef int sint; + +typedef u16 X86EMU_pioAddr; + +#undef NUM32 + +#endif /* __X86EMU_TYPES_H */ diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/arch/nvalloc/unix/include/x86emu/x86emu.h nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/arch/nvalloc/unix/include/x86emu/x86emu.h --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/arch/nvalloc/unix/include/x86emu/x86emu.h 1970-01-01 00:00:00.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/arch/nvalloc/unix/include/x86emu/x86emu.h 2024-03-05 22:12:48.000000000 +0000 @@ -0,0 +1,205 @@ +/**************************************************************************** +* +* Realmode X86 Emulator Library +* +* Copyright (C) 1996-1999 SciTech Software, Inc. +* Copyright (C) David Mosberger-Tang +* Copyright (C) 1999 Egbert Eich +* +* ======================================================================== +* +* Permission to use, copy, modify, distribute, and sell this software and +* its documentation for any purpose is hereby granted without fee, +* provided that the above copyright notice appear in all copies and that +* both that copyright notice and this permission notice appear in +* supporting documentation, and that the name of the authors not be used +* in advertising or publicity pertaining to distribution of the software +* without specific, written prior permission. The authors makes no +* representations about the suitability of this software for any purpose. +* It is provided "as is" without express or implied warranty. +* +* THE AUTHORS DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOFTWARE, +* INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO +* EVENT SHALL THE AUTHORS BE LIABLE FOR ANY SPECIAL, INDIRECT OR +* CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF +* USE, DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR +* OTHER TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR +* PERFORMANCE OF THIS SOFTWARE. +* +* ======================================================================== +* +* Language: ANSI C +* Environment: Any +* Developer: Kendall Bennett +* +* Description: Header file for public specific functions. +* Any application linking against us should only +* include this header +* +****************************************************************************/ + +#ifndef __X86EMU_X86EMU_H +#define __X86EMU_X86EMU_H + +// NV +#ifndef NO_SYS_HEADERS +#define NO_SYS_HEADERS +#endif + +#ifdef SCITECH +#include "scitech.h" +#define X86API _ASMAPI +#define X86APIP _ASMAPIP +typedef int X86EMU_pioAddr; +#else +#include "x86emu/types.h" +#define X86API +#define X86APIP * +#endif +#include "x86emu/regs.h" +#include "x86emu/debug.h" + +/*---------------------- Macros and type definitions ----------------------*/ + +#ifdef PACK +# pragma PACK /* Don't pack structs with function pointers! */ +#endif + +/**************************************************************************** +REMARKS: +Data structure containing ponters to programmed I/O functions used by the +emulator. This is used so that the user program can hook all programmed +I/O for the emulator to handled as necessary by the user program. By +default the emulator contains simple functions that do not do access the +hardware in any way. To allow the emualtor access the hardware, you will +need to override the programmed I/O functions using the X86EMU_setupPioFuncs +function. + +HEADER: +x86emu.h + +MEMBERS: +inb - Function to read a byte from an I/O port +inw - Function to read a word from an I/O port +inl - Function to read a dword from an I/O port +outb - Function to write a byte to an I/O port +outw - Function to write a word to an I/O port +outl - Function to write a dword to an I/O port +****************************************************************************/ +typedef struct { + u8 (X86APIP inb)(X86EMU_pioAddr addr); + u16 (X86APIP inw)(X86EMU_pioAddr addr); + u32 (X86APIP inl)(X86EMU_pioAddr addr); + void (X86APIP outb)(X86EMU_pioAddr addr, u8 val); + void (X86APIP outw)(X86EMU_pioAddr addr, u16 val); + void (X86APIP outl)(X86EMU_pioAddr addr, u32 val); + } X86EMU_pioFuncs; + +/**************************************************************************** +REMARKS: +Data structure containing ponters to memory access functions used by the +emulator. This is used so that the user program can hook all memory +access functions as necessary for the emulator. By default the emulator +contains simple functions that only access the internal memory of the +emulator. If you need specialised functions to handle access to different +types of memory (ie: hardware framebuffer accesses and BIOS memory access +etc), you will need to override this using the X86EMU_setupMemFuncs +function. + +HEADER: +x86emu.h + +MEMBERS: +rdb - Function to read a byte from an address +rdw - Function to read a word from an address +rdl - Function to read a dword from an address +wrb - Function to write a byte to an address +wrw - Function to write a word to an address +wrl - Function to write a dword to an address +****************************************************************************/ +typedef struct { + u8 (X86APIP rdb)(u32 addr); + u16 (X86APIP rdw)(u32 addr); + u32 (X86APIP rdl)(u32 addr); + void (X86APIP wrb)(u32 addr, u8 val); + void (X86APIP wrw)(u32 addr, u16 val); + void (X86APIP wrl)(u32 addr, u32 val); + } X86EMU_memFuncs; + +/**************************************************************************** + Here are the default memory read and write + function in case they are needed as fallbacks. +***************************************************************************/ +extern u8 X86API rdb(u32 addr); +extern u16 X86API rdw(u32 addr); +extern u32 X86API rdl(u32 addr); +extern void X86API wrb(u32 addr, u8 val); +extern void X86API wrw(u32 addr, u16 val); +extern void X86API wrl(u32 addr, u32 val); + +#ifdef END_PACK +# pragma END_PACK +#endif + +/*--------------------- type definitions -----------------------------------*/ + +typedef void (X86APIP X86EMU_intrFuncs)(int num); +extern X86EMU_intrFuncs _X86EMU_intrTab[256]; + +/*-------------------------- Function Prototypes --------------------------*/ + +#ifdef __cplusplus +extern "C" { /* Use "C" linkage when in C++ mode */ +#endif + +void X86EMU_setupMemFuncs(X86EMU_memFuncs *funcs); +void X86EMU_setupPioFuncs(X86EMU_pioFuncs *funcs); +void X86EMU_setupIntrFuncs(X86EMU_intrFuncs funcs[]); +void X86EMU_prepareForInt(int num); + +/* decode.c */ + +void X86EMU_exec(void); +void X86EMU_halt_sys(void); + +#ifdef X86EMU_DEBUG +#define HALT_SYS() do { \ + NV_PRINTF(LEVEL_INFO, "halt_sys: file %s, line %d\n", __FILE__, __LINE__); \ + X86EMU_halt_sys(); \ + } while (0) +#else +#define HALT_SYS() X86EMU_halt_sys() +#endif + +/* Debug options */ + +#define DEBUG_DECODE_F 0x000001 /* print decoded instruction */ +#define DEBUG_TRACE_F 0x000002 /* dump regs before/after execution */ +#define DEBUG_STEP_F 0x000004 +#define DEBUG_DISASSEMBLE_F 0x000008 +#define DEBUG_BREAK_F 0x000010 +#define DEBUG_SVC_F 0x000020 +#define DEBUG_SAVE_IP_CS_F 0x000040 +#define DEBUG_FS_F 0x000080 +#define DEBUG_PROC_F 0x000100 +#define DEBUG_SYSINT_F 0x000200 /* bios system interrupts. */ +#define DEBUG_TRACECALL_F 0x000400 +#define DEBUG_INSTRUMENT_F 0x000800 +#define DEBUG_MEM_TRACE_F 0x001000 +#define DEBUG_IO_TRACE_F 0x002000 +#define DEBUG_TRACECALL_REGS_F 0x004000 +#define DEBUG_DECODE_NOPRINT_F 0x008000 +#define DEBUG_EXIT 0x010000 +#define DEBUG_SYS_F (DEBUG_SVC_F|DEBUG_FS_F|DEBUG_PROC_F) + +void X86EMU_trace_regs(void); +void X86EMU_trace_xregs(void); +void X86EMU_dump_memory(u16 seg, u16 off, u32 amt); +int X86EMU_trace_on(void); +int X86EMU_trace_off(void); + +#ifdef __cplusplus +} /* End of "C" linkage for C++ */ +#endif + +#endif /* __X86EMU_X86EMU_H */ diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/arch/nvalloc/unix/include/x86emu/x86emui.h nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/arch/nvalloc/unix/include/x86emu/x86emui.h --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/arch/nvalloc/unix/include/x86emu/x86emui.h 1970-01-01 00:00:00.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/arch/nvalloc/unix/include/x86emu/x86emui.h 2024-03-05 22:12:48.000000000 +0000 @@ -0,0 +1,113 @@ +/**************************************************************************** +* +* Realmode X86 Emulator Library +* +* Copyright (C) 1996-1999 SciTech Software, Inc. +* Copyright (C) David Mosberger-Tang +* Copyright (C) 1999 Egbert Eich +* +* ======================================================================== +* +* Permission to use, copy, modify, distribute, and sell this software and +* its documentation for any purpose is hereby granted without fee, +* provided that the above copyright notice appear in all copies and that +* both that copyright notice and this permission notice appear in +* supporting documentation, and that the name of the authors not be used +* in advertising or publicity pertaining to distribution of the software +* without specific, written prior permission. The authors makes no +* representations about the suitability of this software for any purpose. +* It is provided "as is" without express or implied warranty. +* +* THE AUTHORS DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOFTWARE, +* INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO +* EVENT SHALL THE AUTHORS BE LIABLE FOR ANY SPECIAL, INDIRECT OR +* CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF +* USE, DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR +* OTHER TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR +* PERFORMANCE OF THIS SOFTWARE. +* +* ======================================================================== +* +* Language: ANSI C +* Environment: Any +* Developer: Kendall Bennett +* +* Description: Header file for system specific functions. These functions +* are always compiled and linked in the OS depedent libraries, +* and never in a binary portable driver. +* +****************************************************************************/ + + +#ifndef __X86EMU_X86EMUI_H +#define __X86EMU_X86EMUI_H + +/* If we are compiling in C++ mode, we can compile some functions as + * inline to increase performance (however the code size increases quite + * dramatically in this case). + */ + +// NV +#ifndef NO_SYS_HEADERS +#define NO_SYS_HEADERS +#endif +#include /* NULL */ +#if defined(__cplusplus) && !defined(_NO_INLINE) +#define _INLINE inline +#else +#define _INLINE static +#endif + +/* Get rid of unused parameters in C++ compilation mode */ + +#ifdef __cplusplus +#define X86EMU_UNUSED(v) +#else +#define X86EMU_UNUSED(v) v +#endif + +#include "x86emu.h" +#include "x86emu/regs.h" +#include "x86emu/debug.h" +#include "x86emu/decode.h" +#include "x86emu/ops.h" +#include "x86emu/prim_ops.h" +#include "x86emu/fpu.h" +#include "x86emu/fpu_regs.h" + +#ifndef NO_SYS_HEADERS +#include +#include +#include +#endif + +// On x86_64 abs() is not recognized. I don't understand why. +#ifndef abs +#define abs(i) __builtin_abs(i) +#endif + +/*--------------------------- Inline Functions ----------------------------*/ + +#ifdef __cplusplus +extern "C" { /* Use "C" linkage when in C++ mode */ +#endif + +extern u8 (X86APIP sys_rdb)(u32 addr); +extern u16 (X86APIP sys_rdw)(u32 addr); +extern u32 (X86APIP sys_rdl)(u32 addr); +extern void (X86APIP sys_wrb)(u32 addr,u8 val); +extern void (X86APIP sys_wrw)(u32 addr,u16 val); +extern void (X86APIP sys_wrl)(u32 addr,u32 val); + +extern u8 (X86APIP sys_inb)(X86EMU_pioAddr addr); +extern u16 (X86APIP sys_inw)(X86EMU_pioAddr addr); +extern u32 (X86APIP sys_inl)(X86EMU_pioAddr addr); +extern void (X86APIP sys_outb)(X86EMU_pioAddr addr,u8 val); +extern void (X86APIP sys_outw)(X86EMU_pioAddr addr,u16 val); +extern void (X86APIP sys_outl)(X86EMU_pioAddr addr,u32 val); + +#ifdef __cplusplus +} /* End of "C" linkage for C++ */ +#endif + +#endif /* __X86EMU_X86EMUI_H */ diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/arch/nvalloc/unix/src/dynamic-power.c nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/arch/nvalloc/unix/src/dynamic-power.c --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/arch/nvalloc/unix/src/dynamic-power.c 1970-01-01 00:00:00.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/arch/nvalloc/unix/src/dynamic-power.c 2024-03-05 22:12:48.000000000 +0000 @@ -0,0 +1,2742 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2019-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#include + +/* + * NOTE: + * The driver disables dynamic power management by effectively setting + * nv_dynamic_power_t::mode to NV_DYNAMIC_PM_NEVER at two places: + * 1) During module probe, when the _PRx methods are not supported + * by the SBIOS or when the kernel does not support runtime PM. + * 2) During RM Init, when the GPU is not Turing+ or when the system is not + * a laptop or when the VBIOS does not support RTD3/GC6. + * + * Thus, after RMInit, if the nv_dynamic_power_t::mode is still + * NV_DYNAMIC_PM_FINE, then we know for sure that the fine grained power + * control is active and running. In this case, the runtime D3 status is + * shown as "Enabled (fine-grained)". + * + * If the nv_dynamic_power_t::mode is NV_DYNAMIC_PM_NEVER, we have to + * distinguish between four cases: + * 1) The driver disabled dynamic power management due to lack of kernel/SBIOS + * support. + * 2) The driver disabled dynamic power management because the GPU does not + * support it or the system is not a laptop. + * 3) The user has explicitly disabled the feature. + * 4) Configuration is not supported by default. + * + * In order to differentiate between these four cases, + * we use the value of regkey NVreg_DynamicPowerManagement. If this value is + * set to 0, then we know that the user has explicitly disabled the + * feature. In this case we show the runtime D3 status as "Disabled". This + * handles case (3) above. + * + * For case (4), we look at the combination of nv_dynamic_power_t::mode and + * NVreg_DynamicPowerManagement value. If mode is never and regkey value is + * default, then status is shown as "Disabled by default". + * + * For remaining cases, (case (1) and (2)) we show status as "Not Supported". + * + * When the regkey is set to 0 and the driver disables the feature due to lack + * of some support, then precedence will be given to regkey value. Thus, when + * both "Not supported" and "Disabled" are possible values, precedence will be + * given to "Disabled" over "Not Supported". + * + * For coarse-grain power control, we show runtime D3 status as + * "Enabled (coarse-grained)". + * + * The runtime D3 status is shown as "?" when RM has not been initialized. + * This is because we do not have full knowledge regarding driver triggered + * disablement until RM is initialized. + */ + +#include +#include +#include +#include +#include + +#include + +#include +#include +#include +#include "kernel/gpu/intr/intr.h" + +#include +#include +#include +#include + +// +// Schedule timer based callback, to check for the complete GPU Idleness. +// Windows has idle time from 70msec to 10sec, we opted for present duration +// considering windows limit. Duration is not much aggressive or slow, hence +// less thrashing. +// +#define GC6_PRECONDITION_CHECK_TIME ((NvU64)5 * 1000 * 1000 * 1000) + +// +// Timeout needed for back to back GC6 cycles. +// Timeout is kept same as the timeout selected for GC6 precondition check. +// There are cases where GPU is in GC6 and then kernel wakes GPU out of GC6 +// as part of say accessing pci tree through lspci and then again ask driver +// to put GPU in GC6 state after access to device info is done. +// Below are the reasons for having timeout limit for back to back GC6 cycle. +// 1> Less chip life cycle. +// 2> P-state is not reached to GC6 supported P-state, in some cycles. +// P-state case returns error to kernel, resulting in corrupted sysfs entry +// and then kernel never calls driver to put device in low power state. +// +#define GC6_CYCLE_IDLE_HOLDOFF_CHECK_TIME GC6_PRECONDITION_CHECK_TIME + +// +// Once GPU is found to be idle, driver will schedule another callback of +// smaller duration. Driver needs to be sure that methods that are present +// in host pipeline are flushed to the respective engines and engines become +// idle upon consumption. +// +#define GC6_BAR1_BLOCKER_CHECK_AND_METHOD_FLUSH_TIME (200 * 1000 * 1000) + +// +// Cap Maximum FB allocation size for GCOFF. If regkey value is greater +// than this value then it will be capped to this value. +// +#define GCOFF_DYNAMIC_PM_MAX_FB_SIZE_MB 1024 + +static void RmScheduleCallbackForIdlePreConditions(OBJGPU *); +static void RmScheduleCallbackForIdlePreConditionsUnderGpuLock(OBJGPU *); +static void RmScheduleCallbackToIndicateIdle(OBJGPU *); +static NvBool RmCheckForGc6SupportOnCurrentState(OBJGPU *); +static void RmScheduleCallbackToRemoveIdleHoldoff(OBJGPU *); +static void RmQueueIdleSustainedWorkitem(OBJGPU *); + +/*! + * @brief Wrapper that checks lock order for the dynamic power mutex. Locking + * order dictates that the GPU lock must not be taken before taking the dynamic + * power mutex. + * + * The GPU lock must not be held when calling this function. + * + * @param[in] nvp nv_priv_t pointer. + */ +static void acquireDynamicPowerMutex(nv_priv_t *nvp) +{ + /* + * Note that this may be called before nvp->pGpu has been initialized, for + * example at the very beginning of nv_start_device. + */ + NV_ASSERT_CHECKED(!nvp->pGpu || !rmDeviceGpuLockIsOwner(nvp->pGpu->gpuInstance)); + + portSyncMutexAcquire(nvp->dynamic_power.mutex); +} + +/*! + * @brief Wrapper to release the mutex, just for consistency with + * acquireDynamicPowerMutex() above. + * + * @param[in] nvp nv_priv_t pointer. + */ +static void releaseDynamicPowerMutex(nv_priv_t *nvp) +{ + portSyncMutexRelease(nvp->dynamic_power.mutex); +} + +/*! + * @brief: Helper function to get a string for the given state. + * + * @param[in] state Dynamic power state. + * + * @return String for the given state. + */ +const char *nv_dynamic_power_state_string( + nv_dynamic_power_state_t state +) +{ + switch (state) + { +#define DPCASE(_case) \ + case NV_DYNAMIC_POWER_STATE_ ## _case: return # _case; + + DPCASE(IN_USE); + DPCASE(IDLE_INSTANT); + DPCASE(IDLE_SUSTAINED); + DPCASE(IDLE_INDICATED); + DPCASE(UNKNOWN); +#undef DPCASE + } + NV_ASSERT(0); + return "UNEXPECTED"; +} + +/*! + * @brief: Helper function to transition the GPU represented by the 'nv' + * pointer from the power state 'old_state' to the power state 'new_state'. + * + * An atomic compare-and-swap is used; the function returns true if the + * operation was successful. If the function returns false, the state is + * unchanged. + * + * @param[in] nv nv_state_t pointer. + * @param[in] old_state Previous (current) state. + * @param[in] new_state New (requested) state. + * + * @return TRUE if the operation was successful; FALSE otherwise. + */ +NvBool nv_dynamic_power_state_transition( + nv_state_t *nv, + nv_dynamic_power_state_t old_state, + nv_dynamic_power_state_t new_state +) +{ + nv_priv_t *nvp = NV_GET_NV_PRIV(nv); + + NV_ASSERT(old_state != new_state); + + ct_assert(sizeof(nv_dynamic_power_state_t) == sizeof(NvS32)); + NvBool ret = portAtomicCompareAndSwapS32((NvS32*)&nvp->dynamic_power.state, + new_state, old_state); + + if (ret) + { + NV_PRINTF(LEVEL_INFO, "%s: state transition %s -> %s\n", + __FUNCTION__, + nv_dynamic_power_state_string(old_state), + nv_dynamic_power_state_string(new_state)); + } + else + { + NV_PRINTF(LEVEL_INFO, "%s: FAILED state transition %s -> %s\n", + __FUNCTION__, + nv_dynamic_power_state_string(old_state), + nv_dynamic_power_state_string(new_state)); + } + + return ret; + +} + +/*! + * @brief: Check if the GPU hardware appears to be idle. + * + * Assumes the GPU lock is held. + * + * @param[in] pGpu OBJGPU pointer. + * + * @return TRUE if the GPU appears to be currently idle; FALSE otherwise. + */ +static NvBool RmCheckForGpuIdlenessUnderGpuLock( + OBJGPU *pGpu +) +{ + NV_ASSERT(rmDeviceGpuLockIsOwner(pGpu->gpuInstance)); + + // Check the instantaneous engine level idleness. + return RmCheckForGc6SupportOnCurrentState(pGpu); +} + +/*! + * @brief: Check if the GPU hardware appears to be idle. + * + * Takes the GPU lock. + * + * @param[in] pGpu OBJGPU pointer. + * + * @return TRUE if the GPU appears to be currently idle; FALSE otherwise. + */ +static NvBool RmCheckForGpuIdleness( + OBJGPU *pGpu +) +{ + NvBool result = NV_FALSE; + NV_STATUS status; + GPU_MASK gpuMask; + + // LOCK: acquire per device lock + status = rmGpuGroupLockAcquire(pGpu->gpuInstance, GPU_LOCK_GRP_SUBDEVICE, + GPUS_LOCK_FLAGS_NONE, RM_LOCK_MODULES_DYN_POWER, + &gpuMask); + if (status == NV_OK) + { + result = RmCheckForGpuIdlenessUnderGpuLock(pGpu); + // UNLOCK: release per device lock + rmGpuGroupLockRelease(gpuMask, GPUS_LOCK_FLAGS_NONE); + } + + return result; +} + +/*! + * @brief: Force the GPU to be "not idle", if it had previously been indicated + * idle. This is triggered by GPU usage (i.e., writing through a revoked + * mapping), not tracked through the refcount maintained through + * os_{ref,unref}_dynamic_power. So, if we'd previously indicated the GPU was + * idle, we transition to the IDLE_INSTANT state. + * + * @param[in] gpuInstance GPU instance ID. + * @param[in] pArgs Unused callback closure. + */ +static void RmForceGpuNotIdle( + NvU32 gpuInstance, + void *pArgs +) +{ + OBJGPU *pGpu = gpumgrGetGpu(gpuInstance); + nv_state_t *nv = NV_GET_NV_STATE(pGpu); + nv_priv_t *nvp = NV_GET_NV_PRIV(nv); + nv_dynamic_power_state_t old_state; + NvBool ret; + + acquireDynamicPowerMutex(nvp); + + old_state = nvp->dynamic_power.state; + + switch (old_state) + { + case NV_DYNAMIC_POWER_STATE_IDLE_INDICATED: + nv_indicate_not_idle(nv); + NV_ASSERT(nvp->dynamic_power.deferred_idle_enabled); + RmScheduleCallbackForIdlePreConditions(pGpu); + /* fallthrough */ + case NV_DYNAMIC_POWER_STATE_IDLE_SUSTAINED: + ret = nv_dynamic_power_state_transition(nv, old_state, NV_DYNAMIC_POWER_STATE_IDLE_INSTANT); + NV_ASSERT(ret); + break; + case NV_DYNAMIC_POWER_STATE_IDLE_INSTANT: + case NV_DYNAMIC_POWER_STATE_IN_USE: + break; + case NV_DYNAMIC_POWER_STATE_UNKNOWN: + NV_ASSERT(0); + break; + } + + /* + * Now that the GPU is guaranteed to not be powered off, we can resume + * servicing mmap requests as usual. + */ + nv_acquire_mmap_lock(nv); + nv_set_safe_to_mmap_locked(nv, NV_TRUE); + nv_release_mmap_lock(nv); + + releaseDynamicPowerMutex(nvp); +} + +/*! + * @brief: Work item to actually indicate the GPU is idle. This rechecks the + * preconditions one last time and verifies nothing has attempted to write + * through any mappings which were revoked. + * + * @param[in] gpuInstance GPU instance ID. + * @param[in] pArgs Unused callback closure. + */ +static void RmIndicateIdle( + NvU32 gpuInstance, + void *pArgs +) +{ + OBJGPU *pGpu = gpumgrGetGpu(gpuInstance); + nv_state_t *nv = NV_GET_NV_STATE(pGpu); + nv_priv_t *nvp = NV_GET_NV_PRIV(nv); + + acquireDynamicPowerMutex(nvp); + + nv_acquire_mmap_lock(nv); + + if (nv_get_all_mappings_revoked_locked(nv) && + nvp->dynamic_power.state == NV_DYNAMIC_POWER_STATE_IDLE_SUSTAINED && + RmCheckForGpuIdleness(pGpu)) + { + nv_set_safe_to_mmap_locked(nv, NV_FALSE); + nv_dynamic_power_state_transition(nv, NV_DYNAMIC_POWER_STATE_IDLE_SUSTAINED, + NV_DYNAMIC_POWER_STATE_IDLE_INDICATED); + nv_indicate_idle(nv); + } + else + { + RmScheduleCallbackForIdlePreConditions(pGpu); + } + + nv_release_mmap_lock(nv); + + releaseDynamicPowerMutex(nvp); +} + +/*! + * @brief: Helper function to trigger the GPU to be forced indicated + * "non-idle", which powers it on if it had been previously powered off, and + * allows mmap processing to continue. + * + * Triggered when a revoked mapping is accessed. + * + * @param[in] sp nvidia_stack_t pointer. + * @param[in] nv nv_state_t pointer. + */ +NV_STATUS NV_API_CALL rm_schedule_gpu_wakeup( + nvidia_stack_t *sp, + nv_state_t *nv +) +{ + void *fp; + NV_STATUS ret; + OBJGPU *pGpu = NV_GET_NV_PRIV_PGPU(nv); + OBJOS *pOS = GPU_GET_OS(pGpu); + + NV_ENTER_RM_RUNTIME(sp, fp); + + ret = pOS->osQueueWorkItem(pGpu, RmForceGpuNotIdle, NULL); + + NV_EXIT_RM_RUNTIME(sp, fp); + + return ret; +} + +/*! + * @brief Function to increment/decrement refcount for GPU driving console. + * + * @params[in] nv nv_state_t pointer. + * @params[in] bIncrease If true, increase refcount else decrease. + */ +void +RmUpdateGc6ConsoleRefCount +( + nv_state_t *nv, + NvBool bIncrease +) +{ + nv_priv_t *nvp = NV_GET_NV_PRIV(nv); + + if (nv->console_device == NV_FALSE) + { + return; + } + + acquireDynamicPowerMutex(nvp); + + if (bIncrease) + { + /* + * Here refcount value should atleast be 2 due to below: + * 1> Refcount increased by NV2080_CTRL_CMD_OS_UNIX_GC6_BLOCKER_REFCNT. + * 2> Refcount increased by the Rm entry points for current thread. + */ + if (nvp->dynamic_power.refcount <= 1) + { + NV_PRINTF(LEVEL_INFO, + "%s: Unexpected dynamic power refcount value\n", __FUNCTION__); + } + else + { + nvp->dynamic_power.refcount++; + } + } + else + { + /* + * Here refcount value should atleast be 3 due to below: + * 1> Refcount set by RM at the probe time for console device. + * 2> Refcount increased by NV2080_CTRL_CMD_OS_UNIX_GC6_BLOCKER_REFCNT. + * 3> Refcount increased by the Rm entry points for current thread. + */ + if (nvp->dynamic_power.refcount <= 2) + { + NV_PRINTF(LEVEL_INFO, + "%s: Unexpected dynamic power refcount value\n", __FUNCTION__); + } + else + { + nvp->dynamic_power.refcount--; + } + } + + releaseDynamicPowerMutex(nvp); +} + +/*! + * @brief Implements the NV2080_CTRL_CMD_OS_UNIX_GC6_BLOCKER_REFCNT RmControl + * request. + * + * @param[in] pSubdevice + * @param[in,out] pParams + * + * @return + * NV_OK Success + * NV_ERR_INVALID_ARGUMENT Invalid pParams->action + */ +NV_STATUS +subdeviceCtrlCmdOsUnixGc6BlockerRefCnt_IMPL +( + Subdevice *pSubdevice, + NV2080_CTRL_OS_UNIX_GC6_BLOCKER_REFCNT_PARAMS *pParams +) +{ + OBJGPU *pGpu = GPU_RES_GET_GPU(pSubdevice); + + /* TODO: keep track of inc/dec on a per-client basis, clean up after + * clients which are unbalanced. */ + if (pParams->action == NV2080_CTRL_OS_UNIX_GC6_BLOCKER_REFCNT_INC) + { + return osRefGpuAccessNeeded(pGpu->pOsGpuInfo); + } + else if (pParams->action == NV2080_CTRL_OS_UNIX_GC6_BLOCKER_REFCNT_DEC) + { + osUnrefGpuAccessNeeded(pGpu->pOsGpuInfo); + } + else + { + return NV_ERR_INVALID_ARGUMENT; + } + + return NV_OK; +} + +/*! + * @brief Implements the NV2080_CTRL_CMD_OS_UNIX_AUDIO_DYNAMIC_POWER RmControl + * request. It will perform dynamic power management for GPU + * HDA contoller. + * + * @param[in] pSubdevice + * @param[in,out] pParams + * + * @return + * NV_OK Success + */ +NV_STATUS +subdeviceCtrlCmdOsUnixAudioDynamicPower_IMPL +( + Subdevice *pSubdevice, + NV2080_CTRL_OS_UNIX_AUDIO_DYNAMIC_POWER_PARAMS *pParams +) +{ + OBJGPU *pGpu = GPU_RES_GET_GPU(pSubdevice); + + /* + * Ideally, we need to honor pParams->bEnter. If it is true, then send the + * request for suspending the HDA controller and if is false, then send the + * request for waking up the HDA controller. Currently, for unix based OS, + * we don't have any proper way to do this and it is implemented with + * workaround. This workaround will wake up the HDA controller for few + * seconds and then bring it back to suspended state. We are using this + * workaround for both the cases (bEnter is true or false). It will help + * in keeping HDA controller active for the duration, when GPU is + * processing HDA controller commands (like writing ELD data). + */ + nv_audio_dynamic_power(NV_GET_NV_STATE(pGpu)); + + return NV_OK; +} + +/*! + * @brief: Function to indicate if Video Memory is powered off or not by + * checking if GPU is in GCOFF state. + * + * @param[in] sp nvidia_stack_t pointer. + * @param[in] pNv nv_state_t pointer. + * + * @return String indicating Video Memory power status. + */ + +const char* NV_API_CALL rm_get_vidmem_power_status( + nvidia_stack_t *sp, + nv_state_t *pNv +) +{ + THREAD_STATE_NODE threadState; + void *fp; + GPU_MASK gpuMask; + const char *pVidmemPowerStatus = "?"; + + NV_ENTER_RM_RUNTIME(sp,fp); + threadStateInit(&threadState, THREAD_STATE_FLAGS_NONE); + + // LOCK: acquire API lock + if ((rmapiLockAcquire(API_LOCK_FLAGS_NONE, RM_LOCK_MODULES_DYN_POWER)) == NV_OK) + { + OBJGPU *pGpu = NV_GET_NV_PRIV_PGPU(pNv); + + // LOCK: acquire per device lock + if ((pGpu != NULL) && + ((rmGpuGroupLockAcquire(pGpu->gpuInstance, GPU_LOCK_GRP_SUBDEVICE, + GPUS_LOCK_FLAGS_NONE, RM_LOCK_MODULES_DYN_POWER, + &gpuMask)) == NV_OK)) + { + if (pGpu->getProperty(pGpu, PDB_PROP_GPU_GCOFF_STATE_ENTERED)) + { + pVidmemPowerStatus = "Off"; + } + else + { + pVidmemPowerStatus = "Active"; + } + + // UNLOCK: release per device lock + rmGpuGroupLockRelease(gpuMask, GPUS_LOCK_FLAGS_NONE); + } + + // UNLOCK: release API lock + rmapiLockRelease(); + } + + threadStateFree(&threadState, THREAD_STATE_FLAGS_NONE); + NV_EXIT_RM_RUNTIME(sp,fp); + + return pVidmemPowerStatus; +} + +/*! + * @brief: Function to indicate if GC6/GC-OFF is supported + * or not on the SKU. + * + * @param[in] sp nvidia_stack_t pointer. + * @param[in] pNv nv_state_t pointer. + * @param[in] bGcxTypeGc6 If true, returns string indicating GC6 support + * otherwise returns GC-OFF support. + * + * @return String indicating GC6/GC-OFF support status. + */ +const char* NV_API_CALL rm_get_gpu_gcx_support( + nvidia_stack_t *sp, + nv_state_t *pNv, + NvBool bGcxTypeGC6 +) +{ + THREAD_STATE_NODE threadState; + void *fp; + GPU_MASK gpuMask; + const char *pSupported = "?"; + + NV_ENTER_RM_RUNTIME(sp,fp); + threadStateInit(&threadState, THREAD_STATE_FLAGS_NONE); + + // LOCK: acquire API lock + if ((rmapiLockAcquire(API_LOCK_FLAGS_NONE, RM_LOCK_MODULES_DYN_POWER)) == NV_OK) + { + OBJGPU *pGpu = NV_GET_NV_PRIV_PGPU(pNv); + + // LOCK: acquire per device lock + if ((pGpu != NULL) && + ((rmGpuGroupLockAcquire(pGpu->gpuInstance, GPU_LOCK_GRP_SUBDEVICE, + GPUS_LOCK_FLAGS_NONE, RM_LOCK_MODULES_DYN_POWER, + &gpuMask)) == NV_OK)) + { + pSupported = "Not Supported"; + + if (!pGpu->getProperty(pGpu, PDB_PROP_GPU_UNIX_DYNAMIC_POWER_SUPPORTED)) + { + goto done; + } + + if (bGcxTypeGC6) + { + if (pGpu->getProperty(pGpu, PDB_PROP_GPU_RTD3_GC6_SUPPORTED)) + { + pSupported = "Supported"; + } + } + else + { + if ((pGpu->getProperty(pGpu, PDB_PROP_GPU_RTD3_GCOFF_SUPPORTED)) || + (pGpu->getProperty(pGpu, PDB_PROP_GPU_LEGACY_GCOFF_SUPPORTED))) + { + pSupported = "Supported"; + } + } + +done: + // UNLOCK: release per device lock + rmGpuGroupLockRelease(gpuMask, GPUS_LOCK_FLAGS_NONE); + } + + //UNLOCK: release API lock + rmapiLockRelease(); + } + + threadStateFree(&threadState, THREAD_STATE_FLAGS_NONE); + NV_EXIT_RM_RUNTIME(sp,fp); + + return pSupported; +} + +/*! + * @brief Function to increment/decrement global Gcoff disallow refcount. + * + * @params[in] pOsGpuInfo OS specific GPU information pointer. + * @params[in] bIsGcoffDisallow If true, increase refcount else decrease. + */ +void osClientGcoffDisallowRefcount( + OS_GPU_INFO *pOsGpuInfo, + NvBool bIsGcoffDisallow +) +{ + nv_priv_t *nvp = NV_GET_NV_PRIV(pOsGpuInfo); + + if (nvp->dynamic_power.mode == NV_DYNAMIC_PM_NEVER) + { + return; + } + + acquireDynamicPowerMutex(nvp); + + if (bIsGcoffDisallow) + { + nvp->dynamic_power.clients_gcoff_disallow_refcount++; + } + else + { + nvp->dynamic_power.clients_gcoff_disallow_refcount--; + } + + releaseDynamicPowerMutex(nvp); +} + +/*! + * @brief Implements the NV2080_CTRL_CMD_OS_UNIX_ALLOW_DISALLOW_GCOFF RmControl + * request. + * + * @param[in] pSubdevice + * @param[in,out] pParams + * + * @return + * NV_OK Success + * NV_ERR_INVALID_ARGUMENT Invalid pParams->action + * NV_ERR_INVALID_OBJECT_HANDLE Invalid Object handle + * NV_ERR_OBJECT_NOT_FOUND Object not found + */ +NV_STATUS +subdeviceCtrlCmdOsUnixAllowDisallowGcoff_IMPL +( + Subdevice *pSubdevice, + NV2080_CTRL_OS_UNIX_ALLOW_DISALLOW_GCOFF_PARAMS *pParams +) +{ + NV_STATUS status; + OBJGPU *pGpu = GPU_RES_GET_GPU(pSubdevice); + + if (pParams->action == NV2080_CTRL_OS_UNIX_ALLOW_DISALLOW_GCOFF_ALLOW) + { + if (pSubdevice->bGcoffDisallowed) + { + pSubdevice->bGcoffDisallowed = NV_FALSE; + osClientGcoffDisallowRefcount(pGpu->pOsGpuInfo, NV_FALSE); + status = NV_OK; + } + else + { + NV_ASSERT(0); + status = NV_ERR_INVALID_ARGUMENT; + } + } + else if (pParams->action == NV2080_CTRL_OS_UNIX_ALLOW_DISALLOW_GCOFF_DISALLOW) + { + if (!pSubdevice->bGcoffDisallowed) + { + pSubdevice->bGcoffDisallowed = NV_TRUE; + osClientGcoffDisallowRefcount(pGpu->pOsGpuInfo, NV_TRUE); + status = NV_OK; + } + else + { + NV_ASSERT(0); + status = NV_ERR_INVALID_ARGUMENT; + } + } + else + { + status = NV_ERR_INVALID_ARGUMENT; + } + + return status; +} + +/*! + * @brief Read and Parse the Dynamic Power Management regkey. + * This function modifies the default value of regkey to either enable + * or disable RTD3 as per System form factor and GPU architecture. + * + * @param[in] pNv nv_state_t pointer. + * @param[out] pRegkeyValue Original value of regkey. + * @param[out] pOption Modified value of regkey. + * + * @return NV_STATUS code. + */ + +#define NV_PMC_BOOT_42_CHIP_ID_GA102 0x00000172 + +static NV_STATUS +rmReadAndParseDynamicPowerRegkey +( + nv_state_t *pNv, + NvU32 *pRegkeyValue, + NvU32 *pOption +) +{ + NV_STATUS status; + NvU32 chipId; + nv_priv_t *pNvp = NV_GET_NV_PRIV(pNv); + + status = osReadRegistryDword(NULL, NV_REG_DYNAMIC_POWER_MANAGEMENT, pRegkeyValue); + + if (status != NV_OK) + return status; + + // If User has set some value, honor that value + if (*pRegkeyValue != NV_REG_DYNAMIC_POWER_MANAGEMENT_DEFAULT) + { + *pOption = *pRegkeyValue; + return NV_OK; + } + + chipId = DRF_VAL(_PMC, _BOOT_42, _CHIP_ID, pNvp->pmc_boot_42); + + // From GA102+, we enable RTD3 only if system is found to be Notebook + if ((chipId >= NV_PMC_BOOT_42_CHIP_ID_GA102) && + (rm_is_system_notebook())) + { + *pOption = NV_REG_DYNAMIC_POWER_MANAGEMENT_FINE; + return NV_OK; + } + + *pOption = NV_REG_DYNAMIC_POWER_MANAGEMENT_NEVER; + return NV_OK; +} +#undef NV_PMC_BOOT_42_CHIP_ID_GA102 + +/*! + * @brief Initialize state related to dynamic power management. + * Called once per GPU during driver initialization. + * + * @param[in] sp nvidia_stack_t pointer. + * @param[in] nv nv_state_t pointer. + */ +void NV_API_CALL rm_init_dynamic_power_management( + nvidia_stack_t *sp, + nv_state_t *nv, + NvBool bPr3AcpiMethodPresent +) +{ + nv_priv_t *nvp = NV_GET_NV_PRIV(nv); + NvU32 option = NV_REG_DYNAMIC_POWER_MANAGEMENT_NEVER; + NvU32 gcOffMaxFbSizeMb; + void *fp; + NvBool bUefiConsole; + NvU32 status; + NvU32 regkeyValue; + + NV_ENTER_RM_RUNTIME(sp,fp); + + portMemSet(&nvp->dynamic_power, 0, sizeof(nvp->dynamic_power)); + + /* + * Program an impossible value so that we show correct status + * during procfs read of runtime D3 status. + */ + nvp->dynamic_power.dynamic_power_regkey = 0xFFFFFFFFu; + + /* + * Dynamic power management will be disabled in either of + * following 3 cases: + * 1. The driver does not support dynamic PM for this + * distro/kernel version. + * 2. _PR3 ACPI method is not supported by upstream port of GPU. + * 3. This feature is not enabled by regkey. + * Also see NOTE + */ + status = rmReadAndParseDynamicPowerRegkey(nv, ®keyValue, &option); + + if (status == NV_OK) + { + nvp->dynamic_power.dynamic_power_regkey = regkeyValue; + } + + if (!nv_dynamic_power_available(nv) || !bPr3AcpiMethodPresent || + (status != NV_OK)) + { + NV_PRINTF(LEVEL_NOTICE, + "%s: Disabling dynamic power management either due to lack" + " of system support or due to error (%d) in reading regkey." + "\n", __FUNCTION__, status); + option = NV_REG_DYNAMIC_POWER_MANAGEMENT_NEVER; + } + + /* + * Read the OS registry for Maximum FB size during GCOFF based dynamic PM. + * This will be capped to GCOFF_DYNAMIC_PM_MAX_FB_SIZE_MB. + */ + if (osReadRegistryDword(NULL, + NV_REG_DYNAMIC_POWER_MANAGEMENT_VIDEO_MEMORY_THRESHOLD, + &gcOffMaxFbSizeMb) == NV_OK) + { + if (gcOffMaxFbSizeMb > GCOFF_DYNAMIC_PM_MAX_FB_SIZE_MB) + gcOffMaxFbSizeMb = GCOFF_DYNAMIC_PM_MAX_FB_SIZE_MB; + } + else + { + gcOffMaxFbSizeMb = GCOFF_DYNAMIC_PM_MAX_FB_SIZE_MB; + } + + nvp->dynamic_power.gcoff_max_fb_size = + (NvU64)gcOffMaxFbSizeMb * 1024 * 1024; + + nvp->dynamic_power.mutex = portSyncMutexCreate(portMemAllocatorGetGlobalNonPaged()); + if (nvp->dynamic_power.mutex == NULL) + { + NV_PRINTF(LEVEL_ERROR, + "%s: failed to create power mutex\n", __FUNCTION__); + nvp->dynamic_power.mode = NV_DYNAMIC_PM_NEVER; + goto done; + } + + switch (option) + { + case NV_REG_DYNAMIC_POWER_MANAGEMENT_FINE: + nvp->dynamic_power.mode = NV_DYNAMIC_PM_FINE; + break; + case NV_REG_DYNAMIC_POWER_MANAGEMENT_COARSE: + nvp->dynamic_power.mode = NV_DYNAMIC_PM_COARSE; + break; + default: + nv_printf(LEVEL_ERROR, + "NVRM: Unknown DynamicPowerManagement value '%u' specified; " + "disabling dynamic power management.\n", option); + // fallthrough + case NV_REG_DYNAMIC_POWER_MANAGEMENT_NEVER: + nvp->dynamic_power.mode = NV_DYNAMIC_PM_NEVER; + break; + } + + // Enable RTD3 infrastructure from OS side. + if ((nvp->dynamic_power.mode == NV_DYNAMIC_PM_FINE) && + (nvp->dynamic_power.dynamic_power_regkey == NV_REG_DYNAMIC_POWER_MANAGEMENT_DEFAULT)) + { + nv_allow_runtime_suspend(nv); + } + + // Legacy case: check if device is primary and driven by VBIOS or fb driver. + nv->primary_vga = NV_FALSE; + + // + // Below function always return NV_OK and depends upon kernel flags + // IORESOURCE_ROM_SHADOW & PCI_ROM_RESOURCE for Primary VGA detection. + // + nv_set_primary_vga_status(nv); + + // UEFI case: where console is driven by GOP driver. + bUefiConsole = rm_get_uefi_console_status(nv); + + nv->console_device = bUefiConsole || nv->primary_vga; + + // + // Initialize refcount as 1 and state as IN_USE. + // rm_enable_dynamic_power_management() will decrease the refcount + // and change state to IDLE_INDICATED, if all prerequisites are met. + // + nvp->dynamic_power.refcount = 1; + nv_dynamic_power_state_transition(nv, NV_DYNAMIC_POWER_STATE_UNKNOWN, + NV_DYNAMIC_POWER_STATE_IN_USE); +done: + NV_EXIT_RM_RUNTIME(sp,fp); +} + +/*! + * @brief Clean up state related to dynamic power management. + * Called during driver removal. + * + * @param[in] sp nvidia_stack_t pointer. + * @param[in] nv nv_state_t pointer. + */ +void NV_API_CALL rm_cleanup_dynamic_power_management( + nvidia_stack_t *sp, + nv_state_t *nv +) +{ + nv_priv_t *nvp = NV_GET_NV_PRIV(nv); + void *fp; + NvBool ret; + + NV_ENTER_RM_RUNTIME(sp,fp); + + // Disable RTD3 infrastructure from OS side. + if ((nvp->dynamic_power.mode == NV_DYNAMIC_PM_FINE) && + (nvp->dynamic_power.dynamic_power_regkey == NV_REG_DYNAMIC_POWER_MANAGEMENT_DEFAULT)) + { + nv_disallow_runtime_suspend(nv); + } + + nv_dynamic_power_state_t old_state = nvp->dynamic_power.state; + + switch (old_state) + { + case NV_DYNAMIC_POWER_STATE_IDLE_INDICATED: + nv_indicate_not_idle(nv); + /* fallthrough */ + case NV_DYNAMIC_POWER_STATE_IDLE_SUSTAINED: + case NV_DYNAMIC_POWER_STATE_IDLE_INSTANT: + ret = nv_dynamic_power_state_transition(nv, old_state, + NV_DYNAMIC_POWER_STATE_IN_USE); + /* + * Nothing else should be running asynchronous to teardown that could + * change the state so this should always succeed. + */ + NV_ASSERT(ret); + break; + case NV_DYNAMIC_POWER_STATE_IN_USE: + break; + case NV_DYNAMIC_POWER_STATE_UNKNOWN: + NV_ASSERT(0); + break; + } + + if (nvp->dynamic_power.mutex) + { + portSyncMutexDestroy(nvp->dynamic_power.mutex); + nvp->dynamic_power.mutex = NULL; + } + + NV_EXIT_RM_RUNTIME(sp,fp); +} + +/*! + * @brief Initialize the dynamic power management refcount and enable GPUOFF, + * if all prerequisites are met. + * Called once per GPU during driver initialization. + * + * @param[in] sp nvidia_stack_t pointer. + * @param[in] nv nv_state_t pointer. + */ +void NV_API_CALL rm_enable_dynamic_power_management( + nvidia_stack_t *sp, + nv_state_t *nv +) +{ + nv_priv_t *nvp = NV_GET_NV_PRIV(nv); + void *fp; + + NV_ENTER_RM_RUNTIME(sp,fp); + + /* + * If dynamic power management is enabled and device is not driving console, + * then dynamic power management can be engaged (since we're not + * using the GPU yet, so it's okay to power it off). + */ + if ((nvp->dynamic_power.mode != NV_DYNAMIC_PM_NEVER) && !nv->console_device) + { + os_unref_dynamic_power(nv, NV_DYNAMIC_PM_COARSE); + } + + NV_EXIT_RM_RUNTIME(sp,fp); +} + +/* + * @brief Increment the dynamic power refcount to prevent the GPU from being + * powered off until a corresponding os_unref_dynamic_power() call is made. + * These two calls must always be balanced in pairs. + * + * This call may block until the GPU is powered on. + * + * The caller must not be holding the GPU lock, but may be holding the API + * lock. + * + * @param[in] sp nvidia_stack_t pointer. + * @param[in] mode Dynamic power mode this refcount bump is used for. + */ +NV_STATUS +os_ref_dynamic_power( + nv_state_t *nv, + nv_dynamic_power_mode_t mode +) +{ + nv_priv_t *nvp = NV_GET_NV_PRIV(nv); + NV_STATUS status = NV_OK; + NvS32 ref; + + if (nvp == NULL) + { + NV_ASSERT(nv->removed); + return NV_OK; + } + + if (mode > nvp->dynamic_power.mode) + { + return NV_OK; + } + + acquireDynamicPowerMutex(nvp); + + ref = nvp->dynamic_power.refcount++; + + NV_ASSERT(ref >= 0); + + if (ref > 0) + { + NV_ASSERT(nvp->dynamic_power.state == NV_DYNAMIC_POWER_STATE_IN_USE); + } + else + { + /* + * Just transitioned from 0 -> 1. + * The current dynamic power state could be any of: + * + * - IDLE_INDICATED: call nv_indicate_not_idle() to ensure + * the GPU is at full power and ready to be used. + * + * - IDLE_INSTANT/IDLE_SUSTAINED: transition to IN_USE. + * Note that in these states, callbacks may be operating + * asynchronously, so care has to be taken to retry the write if it + * fails. + */ + + nv_dynamic_power_state_t old_state = nvp->dynamic_power.state; + NvBool ret; + + switch (old_state) + { + default: + case NV_DYNAMIC_POWER_STATE_IN_USE: + NV_PRINTF(LEVEL_ERROR, "NVRM: %s: Unexpected dynamic power state 0x%x\n", + __FUNCTION__, old_state); + /* fallthrough */ + case NV_DYNAMIC_POWER_STATE_IDLE_INDICATED: + status = nv_indicate_not_idle(nv); + if (status != NV_OK) + { + nvp->dynamic_power.refcount--; + break; + } + if (nvp->dynamic_power.deferred_idle_enabled) + { + RmScheduleCallbackForIdlePreConditions(NV_GET_NV_PRIV_PGPU(nv)); + } + /* fallthrough */ + case NV_DYNAMIC_POWER_STATE_IDLE_SUSTAINED: + case NV_DYNAMIC_POWER_STATE_IDLE_INSTANT: + do { + ret = nv_dynamic_power_state_transition(nv, old_state, NV_DYNAMIC_POWER_STATE_IN_USE); + if (!ret) + { + old_state = nvp->dynamic_power.state; + NV_ASSERT(old_state == NV_DYNAMIC_POWER_STATE_IDLE_INSTANT || + old_state == NV_DYNAMIC_POWER_STATE_IDLE_SUSTAINED); + } + } while (!ret); + break; + } + } + + releaseDynamicPowerMutex(nvp); + + return status; +} + +/*! + * @brief Wrapper around os_ref_dynamic_power() suitable for use from the + * per-OS layers. + * + * @param[in] sp nvidia_stack_t pointer. + * @param[in] nv nv_state_t pointer. + * @param[in] mode Dynamic power mode this refcount bump is used for. + */ +NV_STATUS NV_API_CALL rm_ref_dynamic_power( + nvidia_stack_t *sp, + nv_state_t *nv, + nv_dynamic_power_mode_t mode +) +{ + NV_STATUS status; + void *fp; + + NV_ENTER_RM_RUNTIME(sp,fp); + + status = os_ref_dynamic_power(nv, mode); + + NV_EXIT_RM_RUNTIME(sp,fp); + + return status; +} + +/*! + * @brief Decrement the dynamic power refcount to release an earlier + * requirement that the GPU be powered on made by calling + * os_ref_dynamic_power(). + * These two calls must always be balanced in pairs. + * + * This call may block until the GPU is powered on. + * + * The caller must not be holding the GPU lock, but may be holding the API + * lock. + * + * @param[in] sp nvidia_stack_t pointer. + * @param[in] mode Dynamic power mode this refcount bump is used for. + */ +void +os_unref_dynamic_power( + nv_state_t *nv, + nv_dynamic_power_mode_t mode +) +{ + nv_priv_t *nvp = NV_GET_NV_PRIV(nv); + NvS32 ref; + + if (nvp == NULL) + { + NV_ASSERT(nv->removed); + return; + } + + if (mode > nvp->dynamic_power.mode) + { + return; + } + + acquireDynamicPowerMutex(nvp); + + ref = --nvp->dynamic_power.refcount; + + NV_ASSERT(ref >= 0); + + if (ref == 0) { + NvBool ret; + + /* + * Just transitioned from 1 -> 0. We should have been in the IN_USE + * state previously; now we transition to an idle state: "instant" idle + * if deferred idle is enabled; otherwise indicate idle immediately. + * + * Nothing should be asynchronously changing the state from IN_USE, + * so the state transitions are not expected to fail. + */ + + NV_ASSERT(nvp->dynamic_power.state == NV_DYNAMIC_POWER_STATE_IN_USE); + + if (nvp->dynamic_power.deferred_idle_enabled) + { + ret = nv_dynamic_power_state_transition(nv, NV_DYNAMIC_POWER_STATE_IN_USE, + NV_DYNAMIC_POWER_STATE_IDLE_INSTANT); + NV_ASSERT(ret); + } + else + { + nv_indicate_idle(nv); + ret = nv_dynamic_power_state_transition(nv, NV_DYNAMIC_POWER_STATE_IN_USE, + NV_DYNAMIC_POWER_STATE_IDLE_INDICATED); + NV_ASSERT(ret); + } + } + + releaseDynamicPowerMutex(nvp); +} + +/*! + * @brief Wrapper around os_unref_dynamic_power() suitable for use from the + * per-OS layers. + * + * @param[in] sp nvidia_stack_t pointer. + * @param[in] nv nv_state_t pointer. + * @param[in] mode Dynamic power mode this refcount bump is used for. + */ +void NV_API_CALL rm_unref_dynamic_power( + nvidia_stack_t *sp, + nv_state_t *nv, + nv_dynamic_power_mode_t mode +) +{ + void *fp; + + NV_ENTER_RM_RUNTIME(sp,fp); + + os_unref_dynamic_power(nv, mode); + + NV_EXIT_RM_RUNTIME(sp,fp); +} + +/*! + * @brief Wrapper around os_ref_dynamic_power() suitable for use from core RM. + * + * @params[in] pOsGpuInfo OS specific GPU information pointer + */ +NV_STATUS osRefGpuAccessNeeded( + OS_GPU_INFO *pOsGpuInfo +) +{ + return os_ref_dynamic_power(pOsGpuInfo, NV_DYNAMIC_PM_FINE); +} + +/*! + * @brief Wrapper around os_unref_dynamic_power() suitable for use from core RM. + * + * @params[in] pOsGpuInfo OS specific GPU information pointer + */ +void osUnrefGpuAccessNeeded( + OS_GPU_INFO *pOsGpuInfo +) +{ + os_unref_dynamic_power(pOsGpuInfo, NV_DYNAMIC_PM_FINE); +} + +/*! + * @brief Check if GC6 is supported on current pstate and if engines are idle. + * + * @param[in] pGpu OBJGPU pointer. + */ +static NvBool RmCheckForGc6SupportOnCurrentState( + OBJGPU *pGpu +) +{ + NV_STATUS status = NV_OK; + nv_state_t *nv = NV_GET_NV_STATE(pGpu); + RM_API *pRmApi = rmapiGetInterface(RMAPI_GPU_LOCK_INTERNAL); + NV2080_CTRL_INTERNAL_GC6_ENTRY_PREREQUISITE_PARAMS entryPrerequisiteParams; + + portMemSet(&entryPrerequisiteParams, 0, sizeof(entryPrerequisiteParams)); + + status = pRmApi->Control(pRmApi, + nv->rmapi.hClient, + nv->rmapi.hSubDevice, + NV2080_CTRL_CMD_INTERNAL_GC6_ENTRY_PREREQUISITE, + (void*)&entryPrerequisiteParams, + sizeof(entryPrerequisiteParams)); + + if (status != NV_OK) + { + NV_PRINTF(LEVEL_ERROR, "NVRM, Failed to get GC6 pre-requisite, status=0x%x\n", + status); + return NV_FALSE; + } + + return entryPrerequisiteParams.bIsSatisfied; +} + +/*! + * @brief: Work item to actually remove the idle holdoff which was applied + * on GC6 exit. + * This workitem is scheduled after the timeout limit for idle holdoff is + * finished. + * + * Queue with lock flags: + * OS_QUEUE_WORKITEM_FLAGS_LOCK_GPU_GROUP_SUBDEVICE_RW + * + * @param[in] gpuInstance GPU instance ID. + * @param[in] pArgs Unused callback closure. + */ +static void RmRemoveIdleHoldoff( + NvU32 gpuInstance, + void *pArgs +) +{ + OBJGPU *pGpu = gpumgrGetGpu(gpuInstance); + nv_state_t *nv = NV_GET_NV_STATE(pGpu); + nv_priv_t *nvp = NV_GET_NV_PRIV(nv); + + if (nvp->dynamic_power.b_idle_holdoff == NV_TRUE) + { + if ((RmCheckForGc6SupportOnCurrentState(pGpu) == NV_TRUE) || + (nvp->dynamic_power.idle_precondition_check_callback_scheduled)) + { + nv_indicate_idle(nv); + nvp->dynamic_power.b_idle_holdoff = NV_FALSE; + } + else + { + RmScheduleCallbackToRemoveIdleHoldoff(pGpu); + } + } +} + +/*! + * @brief Timer callback to schedule a work item to remove idle hold off + * that was applied after GC6 exit. + * + * @param[in] pCallbackData OBJGPU pointer (with void pointer type). + */ +static void timerCallbackToRemoveIdleHoldoff( + void *pCallbackData +) +{ + OBJGPU *pGpu = reinterpretCast(pCallbackData, OBJGPU *); + OBJOS *pOS = GPU_GET_OS(pGpu); + + pOS->osQueueWorkItemWithFlags(pGpu, + RmRemoveIdleHoldoff, + NULL, + OS_QUEUE_WORKITEM_FLAGS_LOCK_GPU_GROUP_SUBDEVICE_RW); +} + +/*! + * @brief Timer callback to check if all idle conditions remain met and + * if so schedule a work item to indicate the GPU is idle. + * + * @param[in] pCallbackData OBJGPU pointer (with void pointer type). + */ +static void timerCallbackToIndicateIdle( + void *pCallbackData +) +{ + OBJGPU *pGpu = reinterpretCast(pCallbackData, OBJGPU *); + nv_state_t *nv = NV_GET_NV_STATE(pGpu); + nv_priv_t *nvp = NV_GET_NV_PRIV(nv); + OBJOS *pOS = GPU_GET_OS(pGpu); + + nv_acquire_mmap_lock(nv); + + if (nv_get_all_mappings_revoked_locked(nv) && + nvp->dynamic_power.state == NV_DYNAMIC_POWER_STATE_IDLE_SUSTAINED && + RmCheckForGpuIdlenessUnderGpuLock(pGpu)) + { + pOS->osQueueWorkItem(pGpu, RmIndicateIdle, NULL); + } + else + { + if (nvp->dynamic_power.state == NV_DYNAMIC_POWER_STATE_IDLE_SUSTAINED) + { + /* + * Something used the GPU between when we last sampled and now. + * Go back to the "instant" state to start waiting from scratch. + */ + nv_dynamic_power_state_transition(nv, NV_DYNAMIC_POWER_STATE_IDLE_SUSTAINED, + NV_DYNAMIC_POWER_STATE_IDLE_INSTANT); + } + + RmScheduleCallbackForIdlePreConditionsUnderGpuLock(pGpu); + } + + nv_release_mmap_lock(nv); +} + +/*! + * @brief Timer callback to periodically check if all idle preconditions are + * met. If so, the dynamic power state is advanced from IDLE_INSTANT to + * IDLE_SUSTAINED, or (if already in the IDLE_SUSTAINED state) mappings are + * revoked and timerCallbackToIndicateIdle() is scheduled. + * + * @param[in] pCallbackData OBJGPU pointer (with void pointer type). + */ +static void timerCallbackForIdlePreConditions( + void *pCallbackData +) +{ + OBJGPU *pGpu = reinterpretCast(pCallbackData, OBJGPU *); + nv_state_t *nv = NV_GET_NV_STATE(pGpu); + nv_priv_t *nvp = NV_GET_NV_PRIV(nv); + + nvp->dynamic_power.idle_precondition_check_callback_scheduled = NV_FALSE; + + /* + * Note: It is not safe to take the dynamic power mutex here. + * Lock ordering dictates that the dynamic power mutex must be taken before + * the GPU lock, and this function is called with the GPU lock held. + * + * Therefore, this function is careful about *only* triggering specific + * transitions: + * NV_DYNAMIC_POWER_STATE_IDLE_INSTANT -> NV_DYNAMIC_POWER_STATE_IDLE_SUSTAINED + * NV_DYNAMIC_POWER_STATE_IDLE_SUSTAINED -> NV_DYNAMIC_POWER_STATE_IDLE_INSTANT + * + * Other codepaths are resilient to these state transitions occurring + * asynchronously. The state transition itself is done with an atomic + * compare and swap, so there should be no danger of inadvertently + * triggering a transition from a different state due to a + * read-modify-write or "time of check to time of use" (TOCTTOU) race + * condition. + */ + + if (nvp->dynamic_power.state != NV_DYNAMIC_POWER_STATE_IN_USE) + { + if (RmCheckForGpuIdlenessUnderGpuLock(pGpu)) + { + switch (nvp->dynamic_power.state) + { + case NV_DYNAMIC_POWER_STATE_UNKNOWN: + NV_ASSERT(0); + /* fallthrough */ + case NV_DYNAMIC_POWER_STATE_IDLE_INDICATED: + NV_PRINTF(LEVEL_ERROR, "NVRM: %s: unexpected dynamic power state 0x%x\n", + __FUNCTION__, nvp->dynamic_power.state); + /* fallthrough */ + case NV_DYNAMIC_POWER_STATE_IN_USE: + break; + case NV_DYNAMIC_POWER_STATE_IDLE_INSTANT: + nv_dynamic_power_state_transition(nv, NV_DYNAMIC_POWER_STATE_IDLE_INSTANT, + NV_DYNAMIC_POWER_STATE_IDLE_SUSTAINED); + break; + case NV_DYNAMIC_POWER_STATE_IDLE_SUSTAINED: + RmQueueIdleSustainedWorkitem(pGpu); + return; + } + + } + else + { + if (nvp->dynamic_power.state == NV_DYNAMIC_POWER_STATE_IDLE_SUSTAINED) + { + /* + * Something used the GPU between when we last sampled and now. + * Go back to the "instant" state to start waiting from scratch. + */ + nv_dynamic_power_state_transition(nv, NV_DYNAMIC_POWER_STATE_IDLE_SUSTAINED, + NV_DYNAMIC_POWER_STATE_IDLE_INSTANT); + } + } + } + RmScheduleCallbackForIdlePreConditionsUnderGpuLock(pGpu); +} + +/*! + * @brief Cancel any in-flight callback to remove idle holdoff. + * + * @param[in] pGpu OBJGPU pointer. + */ +static void RmCancelCallbackToRemoveIdleHoldoff( + OBJGPU *pGpu +) +{ + nv_state_t *nv = NV_GET_NV_STATE(pGpu); + nv_priv_t *nvp = NV_GET_NV_PRIV(nv); + TMR_EVENT_GENERAL_PARAMS cancelParams; + + if (NvP64_VALUE(nvp->dynamic_power.remove_idle_holdoff) != NULL) + { + portMemSet(&cancelParams, 0, sizeof(cancelParams)); + + cancelParams.pEvent = nvp->dynamic_power.remove_idle_holdoff; + + tmrCtrlCmdEventCancel(pGpu, &cancelParams); + } +} + +/*! + * @brief Cancel any in-flight timer callbacks. + * + * @param[in] pGpu OBJGPU pointer. + */ +static void RmCancelDynamicPowerCallbacks( + OBJGPU *pGpu +) +{ + nv_state_t *nv = NV_GET_NV_STATE(pGpu); + nv_priv_t *nvp = NV_GET_NV_PRIV(nv); + TMR_EVENT_GENERAL_PARAMS cancelParams; + + if (NvP64_VALUE(nvp->dynamic_power.idle_precondition_check_event) != NULL) + { + // Cancel precondition check callback. + portMemSet(&cancelParams, 0, sizeof(cancelParams)); + + cancelParams.pEvent = nvp->dynamic_power.idle_precondition_check_event; + + tmrCtrlCmdEventCancel(pGpu, &cancelParams); + } + + if (NvP64_VALUE(nvp->dynamic_power.indicate_idle_event) != NULL) + { + // Cancel callback to indicate idle + portMemSet(&cancelParams, 0, sizeof(cancelParams)); + + cancelParams.pEvent = nvp->dynamic_power.indicate_idle_event; + + tmrCtrlCmdEventCancel(pGpu, &cancelParams); + } + + RmCancelCallbackToRemoveIdleHoldoff(pGpu); + + nvp->dynamic_power.idle_precondition_check_callback_scheduled = NV_FALSE; +} + +/*! + * @brief Free timer events allocated by CreateDynamicPowerCallbacks() + * + * @param[in] pGpu OBJGPU pointer. + */ +static void RmDestroyDynamicPowerCallbacks( + OBJGPU *pGpu +) +{ + nv_state_t *nv = NV_GET_NV_STATE(pGpu); + nv_priv_t *nvp = NV_GET_NV_PRIV(nv); + TMR_EVENT_GENERAL_PARAMS destroyParams; + + if (NvP64_VALUE(nvp->dynamic_power.idle_precondition_check_event) != NULL) + { + // Destroy precondition check callback. + portMemSet(&destroyParams, 0, sizeof(destroyParams)); + + destroyParams.pEvent = nvp->dynamic_power.idle_precondition_check_event; + + tmrCtrlCmdEventDestroy(pGpu, &destroyParams); + nvp->dynamic_power.idle_precondition_check_event = NvP64_NULL; + } + + if (NvP64_VALUE(nvp->dynamic_power.indicate_idle_event) != NULL) + { + // Destroy callback to indicate idle + portMemSet(&destroyParams, 0, sizeof(destroyParams)); + + destroyParams.pEvent = nvp->dynamic_power.indicate_idle_event; + + tmrCtrlCmdEventDestroy(pGpu, &destroyParams); + nvp->dynamic_power.indicate_idle_event = NvP64_NULL; + } + + if (NvP64_VALUE(nvp->dynamic_power.remove_idle_holdoff) != NULL) + { + // Destroy callback to decrease kernel refcount + portMemSet(&destroyParams, 0, sizeof(destroyParams)); + + destroyParams.pEvent = nvp->dynamic_power.remove_idle_holdoff; + + tmrCtrlCmdEventDestroy(pGpu, &destroyParams); + nvp->dynamic_power.remove_idle_holdoff = NvP64_NULL; + } + + nvp->dynamic_power.deferred_idle_enabled = NV_FALSE; +} + +/* + * @brief Adds a GPU to OBJOS::dynamicPowerSupportGpuMask + * + * @param[in] instance + */ +void osAddGpuDynPwrSupported +( + NvU32 instance +) +{ + OBJSYS *pSys = SYS_GET_INSTANCE(); + OBJOS *pOS = SYS_GET_OS(pSys); + + pOS->dynamicPowerSupportGpuMask |= (1 << instance); +} + +/* + * @brief Removes a GPU from OBJOS::dynamicPowerSupportGpuMask + * + * @param[in] instance + */ +void osRemoveGpuDynPwrSupported +( + NvU32 instance +) +{ + OBJSYS *pSys = SYS_GET_INSTANCE(); + OBJOS *pOS = SYS_GET_OS(pSys); + + pOS->dynamicPowerSupportGpuMask &= ~(1 << instance); +} + +/* + * @brief queries OBJOS::dynamicPowerSupportGpuMask + * + * @param[in] void + */ +NvU32 osGetDynamicPowerSupportMask +( + void +) +{ + OBJSYS *pSys = SYS_GET_INSTANCE(); + OBJOS *pOS = SYS_GET_OS(pSys); + + return pOS->dynamicPowerSupportGpuMask; +} + +/*! + * @brief Cancel any outstanding callbacks, and free RM resources allocated by + * RmInitDeferredDynamicPowerManagement(). + * + * @param[in] nv nv_state_t pointer. + */ +void RmDestroyDeferredDynamicPowerManagement( + nv_state_t *nv +) +{ + nv_priv_t *nvp = NV_GET_NV_PRIV(nv); + OBJGPU *pGpu = NV_GET_NV_PRIV_PGPU(nv); + + // + // Re-instate the dynamic power mode to fine if it was + // disabled due to lack of platform support + // + if (nvp->dynamic_power.b_fine_not_supported == NV_TRUE) + { + nvp->dynamic_power.mode = NV_DYNAMIC_PM_FINE; + nvp->dynamic_power.b_fine_not_supported = NV_FALSE; + } + + // + // Before cancelling and destroying the callbacks, make sure to + // remove the idle holfoff that was applied during gc6 exit. + // + if (nvp->dynamic_power.b_idle_holdoff == NV_TRUE) + { + nv_indicate_idle(nv); + nvp->dynamic_power.b_idle_holdoff = NV_FALSE; + } + + RmCancelDynamicPowerCallbacks(pGpu); + RmDestroyDynamicPowerCallbacks(pGpu); + osRemoveGpuDynPwrSupported(gpuGetInstance(pGpu)); +} + +/*! + * @brief Allocate timer events to call the functions: + * timerCallbackForIdlePreConditions() + * timerCallbackToIndicateIdle() + * + * The callbacks must be scheduled separately. + * + * @param[in] pGpu OBJGPU pointer. + */ +static NV_STATUS CreateDynamicPowerCallbacks( + OBJGPU *pGpu +) +{ + nv_state_t *nv = NV_GET_NV_STATE(pGpu); + nv_priv_t *nvp = NV_GET_NV_PRIV(nv); + TMR_EVENT_SET_PARAMS createEventParams; + NV_STATUS status; + + // Creating PreCondition check callback. + portMemSet(&createEventParams, 0, sizeof(createEventParams)); + + createEventParams.ppEvent = &(nvp->dynamic_power.idle_precondition_check_event); + createEventParams.pTimeProc = NV_PTR_TO_NvP64(timerCallbackForIdlePreConditions); + createEventParams.pCallbackData = NV_PTR_TO_NvP64(pGpu); + createEventParams.flags = TMR_FLAG_USE_OS_TIMER; + + status = tmrCtrlCmdEventCreate(pGpu, &createEventParams); + + if (status != NV_OK) + { + NV_PRINTF(LEVEL_ERROR, + "NVRM: Error creating dynamic power precondition check callback\n"); + nvp->dynamic_power.idle_precondition_check_event = NvP64_NULL; + nvp->dynamic_power.indicate_idle_event = NvP64_NULL; + nvp->dynamic_power.remove_idle_holdoff = NvP64_NULL; + return status; + } + + // Create callback to indicate idle.. + portMemSet(&createEventParams, 0, sizeof(createEventParams)); + + createEventParams.ppEvent = &(nvp->dynamic_power.indicate_idle_event); + createEventParams.pTimeProc = NV_PTR_TO_NvP64(timerCallbackToIndicateIdle); + createEventParams.pCallbackData = NV_PTR_TO_NvP64(pGpu); + createEventParams.flags = TMR_FLAG_USE_OS_TIMER; + + status = tmrCtrlCmdEventCreate(pGpu, &createEventParams); + + if (status != NV_OK) + { + NV_PRINTF(LEVEL_ERROR, + "NVRM: Error creating callback to indicate GPU idle\n"); + nvp->dynamic_power.idle_precondition_check_event = NvP64_NULL; + nvp->dynamic_power.indicate_idle_event = NvP64_NULL; + nvp->dynamic_power.remove_idle_holdoff = NvP64_NULL; + return status; + } + + // Create callback to remove idle holdoff + portMemSet(&createEventParams, 0, sizeof(createEventParams)); + + createEventParams.ppEvent = &(nvp->dynamic_power.remove_idle_holdoff); + createEventParams.pTimeProc = NV_PTR_TO_NvP64(timerCallbackToRemoveIdleHoldoff); + createEventParams.pCallbackData = NV_PTR_TO_NvP64(pGpu); + createEventParams.flags = TMR_FLAG_USE_OS_TIMER; + + status = tmrCtrlCmdEventCreate(pGpu, &createEventParams); + + if (status != NV_OK) + { + NV_PRINTF(LEVEL_ERROR, + "NVRM: Error creating callback to decrease kernel refcount\n"); + nvp->dynamic_power.idle_precondition_check_event = NvP64_NULL; + nvp->dynamic_power.indicate_idle_event = NvP64_NULL; + nvp->dynamic_power.remove_idle_holdoff = NvP64_NULL; + return status; + } + + return NV_OK; +} + +/*! + * @brief Schedule the timerCallbackForIdlePreConditions() function to be called. + * + * If it is already scheduled, the function is a noop. + * + * The GPU lock must be held when calling this function. + * + * @param[in] pGpu OBJGPU pointer. + */ +static void RmScheduleCallbackForIdlePreConditionsUnderGpuLock( + OBJGPU *pGpu +) +{ + nv_state_t *nv = NV_GET_NV_STATE(pGpu); + nv_priv_t *nvp = NV_GET_NV_PRIV(nv); + TMR_EVENT_SCHEDULE_PARAMS scheduleEventParams; + NV_STATUS status; + + NV_ASSERT(rmDeviceGpuLockIsOwner(pGpu->gpuInstance)); + + if (nvp->dynamic_power.idle_precondition_check_callback_scheduled) + { + return; + } + + if (NvP64_VALUE(nvp->dynamic_power.idle_precondition_check_event) != NULL) + { + portMemSet(&scheduleEventParams, 0, sizeof(scheduleEventParams)); + + scheduleEventParams.pEvent = nvp->dynamic_power.idle_precondition_check_event; + scheduleEventParams.timeNs = GC6_PRECONDITION_CHECK_TIME; + scheduleEventParams.bUseTimeAbs = NV_FALSE; + + status = tmrCtrlCmdEventSchedule(pGpu, &scheduleEventParams); + + if (status == NV_OK) + { + nvp->dynamic_power.idle_precondition_check_callback_scheduled = NV_TRUE; + } + else + { + NV_PRINTF(LEVEL_ERROR, "NVRM: Error scheduling precondition callback\n"); + } + } +} + +/*! + * @brief Schedule the timerCallbackForIdlePreConditions() function to be called. + * + * If it is already scheduled, the function is a noop. + * + * This function takes the GPU lock. + * + * @param[in] pGpu OBJGPU pointer. + */ +static void RmScheduleCallbackForIdlePreConditions( + OBJGPU *pGpu +) +{ + NV_STATUS status; + GPU_MASK gpuMask; + + // LOCK: acquire per device lock + status = rmGpuGroupLockAcquire(pGpu->gpuInstance, GPU_LOCK_GRP_SUBDEVICE, + GPUS_LOCK_FLAGS_NONE, RM_LOCK_MODULES_DYN_POWER, + &gpuMask); + if (status == NV_OK) + { + RmScheduleCallbackForIdlePreConditionsUnderGpuLock(pGpu); + // UNLOCK: release per device lock + rmGpuGroupLockRelease(gpuMask, GPUS_LOCK_FLAGS_NONE); + } +} + +/*! + * @brief Schedule the timerCallbackToIndicateIdle() function to be called. + * + * The GPU lock must be held when calling this function. + * + * @param[in] pGpu OBJGPU pointer. + */ +static void RmScheduleCallbackToIndicateIdle( + OBJGPU *pGpu +) +{ + nv_state_t *nv = NV_GET_NV_STATE(pGpu); + nv_priv_t *nvp = NV_GET_NV_PRIV(nv); + TMR_EVENT_SCHEDULE_PARAMS scheduleEventParams; + NV_STATUS status; + + NV_ASSERT(rmDeviceGpuLockIsOwner(pGpu->gpuInstance)); + + if (NvP64_VALUE(nvp->dynamic_power.indicate_idle_event) != NULL) + { + portMemSet(&scheduleEventParams, 0, sizeof(scheduleEventParams)); + + scheduleEventParams.pEvent = nvp->dynamic_power.indicate_idle_event; + scheduleEventParams.timeNs = GC6_BAR1_BLOCKER_CHECK_AND_METHOD_FLUSH_TIME; + scheduleEventParams.bUseTimeAbs = NV_FALSE; + + status = tmrCtrlCmdEventSchedule(pGpu, &scheduleEventParams); + + if (status != NV_OK) + NV_PRINTF(LEVEL_ERROR, "NVRM: Error scheduling indicate idle callback\n"); + } +} + +/*! + * @brief Schedule the timerCallbackToRemoveIdleHoldoff() function. + * + * The GPU lock must be held when calling this function. + * + * @param[in] pGpu OBJGPU pointer. + */ +static void RmScheduleCallbackToRemoveIdleHoldoff( + OBJGPU *pGpu +) +{ + nv_state_t *nv = NV_GET_NV_STATE(pGpu); + nv_priv_t *nvp = NV_GET_NV_PRIV(nv); + TMR_EVENT_SCHEDULE_PARAMS scheduleEventParams; + NV_STATUS status; + + NV_ASSERT(rmDeviceGpuLockIsOwner(pGpu->gpuInstance)); + + if (NvP64_VALUE(nvp->dynamic_power.remove_idle_holdoff) != NULL) + { + portMemSet(&scheduleEventParams, 0, sizeof(scheduleEventParams)); + + scheduleEventParams.pEvent = nvp->dynamic_power.remove_idle_holdoff; + scheduleEventParams.timeNs = GC6_CYCLE_IDLE_HOLDOFF_CHECK_TIME; + scheduleEventParams.bUseTimeAbs = NV_FALSE; + + status = tmrCtrlCmdEventSchedule(pGpu, &scheduleEventParams); + + if (status != NV_OK) + { + NV_PRINTF(LEVEL_ERROR, + "NVRM: Error scheduling kernel refcount decrement callback\n"); + } + else + { + nvp->dynamic_power.b_idle_holdoff = NV_TRUE; + } + } +} + +/*! + * @brief Check if the system supports RTD3-GC6. + * + * @param[in] pGpu OBJGPU pointer. + */ +static NvBool RmCheckRtd3Gc6Support( + nv_state_t *pNv +) +{ + nv_priv_t *nvp = NV_GET_NV_PRIV(pNv); + OBJGPU *pGpu = NV_GET_NV_PRIV_PGPU(pNv); + RM_API *pRmApi = rmapiGetInterface(RMAPI_GPU_LOCK_INTERNAL); + NV_STATUS status; + NV0080_CTRL_GPU_GET_VIRTUALIZATION_MODE_PARAMS virtModeParams = { 0 }; + + if (!pGpu->getProperty(pGpu, PDB_PROP_GPU_UNIX_DYNAMIC_POWER_SUPPORTED)) + { + NV_PRINTF(LEVEL_NOTICE, "NVRM: RTD3/GC6 is not supported for this arch\n"); + return NV_FALSE; + } + + if (!pGpu->getProperty(pGpu, PDB_PROP_GPU_RTD3_GC6_SUPPORTED)) + { + NV_PRINTF(LEVEL_NOTICE, "NVRM: RTD3/GC6 is not supported in Vbios\n"); + return NV_FALSE; + } + + if (!nvp->b_mobile_config_enabled) + { + NV_PRINTF(LEVEL_NOTICE, "NVRM: Disabling RTD3/GC6, as it is only supported on Notebook SKU\n"); + return NV_FALSE; + } + + status = pRmApi->Control(pRmApi, pNv->rmapi.hClient, pNv->rmapi.hDevice, + NV0080_CTRL_CMD_GPU_GET_VIRTUALIZATION_MODE, + &virtModeParams, sizeof(virtModeParams)); + + if (status != NV_OK) + { + NV_PRINTF(LEVEL_ERROR, + "NVRM: Failed to get Virtualization mode, status=0x%x\n", + status); + return NV_FALSE; + } + + if ((virtModeParams.virtualizationMode != NV0080_CTRL_GPU_VIRTUALIZATION_MODE_NONE) && + (virtModeParams.virtualizationMode != NV0080_CTRL_GPU_VIRTUALIZATION_MODE_NMOS)) + { + NV_PRINTF(LEVEL_NOTICE, "NVRM: RTD3/GC6 is not supported on VM\n"); + return NV_FALSE; + } + + return NV_TRUE; +} + +/*! + * @brief Allocate resources needed to track deferred power management, and + * schedule the initial periodic callbacks. + * + * @param[in] nv nv_state_t pointer. + */ +void RmInitDeferredDynamicPowerManagement( + nv_state_t *nv +) +{ + NV_STATUS status; + nv_priv_t *nvp = NV_GET_NV_PRIV(nv); + + // LOCK: acquire GPUs lock + if ((status = rmGpuLocksAcquire(GPUS_LOCK_FLAGS_NONE, RM_LOCK_MODULES_DYN_POWER)) == NV_OK) + { + if (nvp->dynamic_power.mode == NV_DYNAMIC_PM_FINE) + { + OBJGPU *pGpu = NV_GET_NV_PRIV_PGPU(nv); + + if (!RmCheckRtd3Gc6Support(nv)) + { + nvp->dynamic_power.mode = NV_DYNAMIC_PM_NEVER; + nvp->dynamic_power.b_fine_not_supported = NV_TRUE; + NV_PRINTF(LEVEL_NOTICE, "NVRM: RTD3/GC6 is not supported\n"); + goto unlock; + } + osAddGpuDynPwrSupported(gpuGetInstance(pGpu)); + nvp->dynamic_power.b_fine_not_supported = NV_FALSE; + status = CreateDynamicPowerCallbacks(pGpu); + + if (status == NV_OK) + { + RmScheduleCallbackForIdlePreConditionsUnderGpuLock(pGpu); + + nvp->dynamic_power.deferred_idle_enabled = NV_TRUE; + // RM's default is GCOFF allow + nvp->dynamic_power.clients_gcoff_disallow_refcount = 0; + } + } +unlock: + // UNLOCK: release GPUs lock + rmGpuLocksRelease(GPUS_LOCK_FLAGS_NONE, NULL); + } + + if (status != NV_OK) + NV_PRINTF(LEVEL_ERROR, "NVRM: Failed to register for dynamic power callbacks\n"); +} + +/*! + * @brief Check if GCOFF state can be used for Power Management. + * + * @param[in] pGpu OBJGPU pointer. + * @param[in] usedFbSize Used FB Allocation size. + * @param[in] bIsDynamicPM If true, check for dynamic PM; otherwise, check + * for system PM (suspend/resume). + * + * returns NV_TRUE if GCOFF state can be used, otherwise NV_FALSE. + * + */ +static NvBool RmCheckForGcOffPM( + OBJGPU *pGpu, + NvU64 usedFbSize, + NvBool bIsDynamicPM +) +{ + nv_state_t *nv = NV_GET_NV_STATE(pGpu); + nv_priv_t *nvp = NV_GET_NV_PRIV(nv); + NvU64 gcoff_max_fb_size; + + if (bIsDynamicPM) + { + /* + * GCOFF won't be enaged for Dynamic PM if X server does not allow. + * The dynamic_power.clients_gcoff_disallow_refcount is being accessed + * without acquiring dynamic power mutex since this value can be + * modified only when GPU is in active state. The os_ref_dynamic_power() + * function will be called to hold a reference to the GPU whenever + * RM is processing osClientGcoffDisallowRefcount() calls. This either + * prevents the GPU from going into a low power state or will wait for + * it to be resumed before proceeding. + */ + if (nvp->dynamic_power.clients_gcoff_disallow_refcount != 0) + return NV_FALSE; + + gcoff_max_fb_size = nvp->dynamic_power.gcoff_max_fb_size; + } + else + { + gcoff_max_fb_size = nvp->s0ix_gcoff_max_fb_size; + } + + /* + * GCOFF will be engaged whenever the following necessary preconditions + * are met: + * + * 1. The GCOFF has not been disabled with regkey by setting it to zero. + * 2. Used FB allocation size are within limits. + */ + return (gcoff_max_fb_size > 0) && + (usedFbSize <= gcoff_max_fb_size); +} + +// +// Function to update fixed fbsr modes to support multiple vairants such as +// GCOFF and cuda S3/resume. +// +static void +RmUpdateFixedFbsrModes(OBJGPU *pGpu) +{ + MemoryManager *pMemoryManager = GPU_GET_MEMORY_MANAGER(pGpu); + nv_state_t *nv = NV_GET_NV_STATE(pGpu); + + if (pGpu->getProperty(pGpu, PDB_PROP_GPU_GCOFF_STATE_ENTERING)) + { + pMemoryManager->fixedFbsrModesMask = NVBIT(FBSR_TYPE_DMA); + } + else if (nv->preserve_vidmem_allocations) + { + pMemoryManager->fixedFbsrModesMask = NVBIT(FBSR_TYPE_FILE); + } +} + +static NV_STATUS +RmPowerManagementInternal( + OBJGPU *pGpu, + nv_pm_action_t pmAction +) +{ + // default to NV_OK. there may cases where resman is loaded, but + // no devices are allocated (we're still at the console). in these + // cases, it's fine to let the system do whatever it wants. + NV_STATUS rmStatus = NV_OK; + + if (pGpu) + { + nv_state_t *nv = NV_GET_NV_STATE(pGpu); + nv_priv_t *nvp = NV_GET_NV_PRIV(nv); + NvBool bcState = gpumgrGetBcEnabledStatus(pGpu); + Intr *pIntr = GPU_GET_INTR(pGpu); + + MemoryManager *pMemoryManager = GPU_GET_MEMORY_MANAGER(pGpu); + if ((pmAction == NV_PM_ACTION_HIBERNATE) || (pmAction == NV_PM_ACTION_STANDBY)) + { + // + // pFb object store the FBSR mode through which FB state unload has happened, + // so os layer doesn't need to set FBSR mode on resume. + // + RmUpdateFixedFbsrModes(pGpu); + } + + switch (pmAction) + { + case NV_PM_ACTION_HIBERNATE: + nvp->pm_state.InHibernate = NV_TRUE; + nvp->pm_state.IntrEn = intrGetIntrEn(pIntr); + intrSetIntrEn(pIntr, INTERRUPT_TYPE_DISABLED); + gpumgrSetBcEnabledStatus(pGpu, NV_FALSE); + + rmStatus = gpuEnterHibernate(pGpu); + gpumgrSetBcEnabledStatus(pGpu, bcState); + + break; + + case NV_PM_ACTION_STANDBY: + nvp->pm_state.InHibernate = NV_FALSE; + nvp->pm_state.IntrEn = intrGetIntrEn(pIntr); + intrSetIntrEn(pIntr, INTERRUPT_TYPE_DISABLED); + gpumgrSetBcEnabledStatus(pGpu, NV_FALSE); + + rmStatus = gpuEnterStandby(pGpu); + gpumgrSetBcEnabledStatus(pGpu, bcState); + + break; + + case NV_PM_ACTION_RESUME: + gpumgrSetBcEnabledStatus(pGpu, NV_FALSE); + + if (nvp->pm_state.InHibernate) + { + gpuResumeFromHibernate(pGpu); + } + else + { + gpuResumeFromStandby(pGpu); + } + intrSetIntrEn(pIntr, nvp->pm_state.IntrEn); + gpumgrSetBcEnabledStatus(pGpu, bcState); + NvU32 ac_plugged = 0; + + if (IsMobile(pGpu)) + { + if (nv_acpi_get_powersource(&ac_plugged) == NV_OK) + { + // + // As we have already acquired API and GPU lock here, we are + // directly calling RmPowerSourceChangeEvent. + // + RmPowerSourceChangeEvent(nv, !ac_plugged); + } + RmRequestDNotifierState(nv); + } + break; + + default: + rmStatus = NV_ERR_INVALID_ARGUMENT; + break; + } + pMemoryManager->fixedFbsrModesMask = 0; + } + + return rmStatus; +} + +static NV_STATUS +RmPowerManagement( + OBJGPU *pGpu, + nv_pm_action_t pmAction +) +{ + NV_STATUS rmStatus; + + rmStatus = RmPowerManagementInternal(pGpu, pmAction); + + return rmStatus; +} + +/*! + * @brief Call core RM to perform the GCx (GC6/GCOF) entry sequence (before + * powering off the GPU) or exit sequence (after powering the GPU back on). + * + * The GPU lock should be held when calling this function. + * + * @param[in] pGpu OBJGPU pointer. + * @param[in] bEnter If true, perform entry sequence; exit sequence + * otherwise. + * @param[in] bIsDynamicPM If true, it is for dynamic PM; otherwise, it is + * for system PM (suspend/resume). + * + * @return NV_STATUS code indicating if the operation was successful. + */ +NV_STATUS RmGcxPowerManagement( + OBJGPU *pGpu, + NvBool bEnter, + NvBool bIsDynamicPM +) +{ + KernelMemorySystem *pKernelMemorySystem = GPU_GET_KERNEL_MEMORY_SYSTEM(pGpu); + nv_state_t *nv = NV_GET_NV_STATE(pGpu); + NV_STATUS status = NV_OK; + + if (pGpu->acpiMethodData.jtMethodData.bSBIOSCaps && + !pGpu->getProperty(pGpu, PDB_PROP_GPU_IS_MOBILE)) + { + // + // AML override is expected only on NB platforms to support GCOFF-1.0( + // which is legacy GCOFF) and GC6-3.0 + // GC6 3.0 is possible without AML override but due to changes required + // for GCOFF-1.0 in SBIOS & HW, AML override is needed for GC6-3.0 also. + // + NV_PRINTF(LEVEL_INFO,"NVRM: AML overrides present in Desktop"); + } + + nv->d0_state_in_suspend = NV_FALSE; + + if (bEnter) + { + MemoryManager *pMemoryManager = GPU_GET_MEMORY_MANAGER(pGpu); + NvU64 usedFbSize; + NvBool bCanUseGc6; + + // + // Check if GC6 can be used for current power management request. + // For dynamic PM, it can be used always. + // For system PM, it can be used only if current system suspend + // happened with s2idle. + // + bCanUseGc6 = bIsDynamicPM ? NV_TRUE : nv_s2idle_pm_configured(); + + // + // If GC6 cannot be used, then no need to compare the used FB size with + // threshold value and select GCOFF irrespective of FB size. + // + if ((memmgrGetUsedRamSize(pGpu, pMemoryManager, &usedFbSize) == NV_OK) && + (!bCanUseGc6 || RmCheckForGcOffPM(pGpu, usedFbSize, bIsDynamicPM)) && + (fbsrReserveSysMemoryForPowerMgmt(pGpu, pMemoryManager->pFbsr[FBSR_TYPE_DMA], + usedFbSize) == NV_OK)) + { + pGpu->setProperty(pGpu, PDB_PROP_GPU_GCOFF_STATE_ENTERING, NV_TRUE); + + // + // Set 'bPreserveComptagBackingStoreOnSuspendDef' so that comptag + // related handling can be done during state unload/load. + // + pKernelMemorySystem->bPreserveComptagBackingStoreOnSuspend = NV_TRUE; + status = RmPowerManagement(pGpu, NV_PM_ACTION_STANDBY); + pGpu->setProperty(pGpu, PDB_PROP_GPU_GCOFF_STATE_ENTERING, NV_FALSE); + + if (status == NV_OK) + { + pGpu->setProperty(pGpu, PDB_PROP_GPU_GCOFF_STATE_ENTERED, NV_TRUE); + } + else + { + /* + * Normally the NV_PM_ACTION_RESUME resume should free the + * the reserved memory while doing FB state load. But if the + * failure has happened at very early stage in FB state unload + * while doing NV_PM_ACTION_STANDBY, then reserved system memory + * might not be freed. + */ + fbsrFreeReservedSysMemoryForPowerMgmt(pMemoryManager->pFbsr[FBSR_TYPE_DMA]); + pKernelMemorySystem->bPreserveComptagBackingStoreOnSuspend = NV_FALSE; + } + } + else if (bCanUseGc6) + { + NV2080_CTRL_GC6_ENTRY_PARAMS entryParams; + portMemSet(&entryParams, 0, sizeof(entryParams)); + + entryParams.flavorId = NV2080_CTRL_GC6_FLAVOR_ID_MSHYBRID; + entryParams.stepMask = NVBIT(NV2080_CTRL_GC6_STEP_ID_GPU_OFF); + entryParams.params.bIsRTD3Transition = NV_TRUE; + + // + // Currently if the GPU is not in the Lowest P-State, then the + // GC6 entry will fail in its internal sanity check. The system + // suspend can be triggered in any P-State, so sanity check + // for the lowest P-State needs to be skipped. In this case, during + // Perf state unload time, the forceful P-State switch will + // happen which will bring the GPU into lowest P-State. + // + entryParams.params.bSkipPstateSanity = !bIsDynamicPM; + + status = gpuGc6Entry(pGpu, &entryParams); + + // + // The GC6 state requires SW involvement before each transition + // from D0 to D3cold. In case of system suspend with pass-through + // mode, the VM suspend should happen before host suspend. During + // VM suspend, the NVIDIA driver running in the VM side will be + // involved in D3cold transition, but in the host side, it will + // go through D3cold->D0->D3cold transition and will make the + // second D3cold transition without NVIDIA driver. To handle this + // use-case, during VM suspend, use the D0 state and the host linux + // kernel will put the device into D3cold state. + // + if ((status == NV_OK) && ((nv->flags & NV_FLAG_PASSTHRU) != 0)) + { + nv->d0_state_in_suspend = NV_TRUE; + } + } + // + // This condition will hit only for systems which support s2idle but + // are currently configured for deep sleep based system power + // management, and that too when sufficient system memory + // is not available. For this case, the suspend request will fail + // and the system will remain in S0. + // + else + { + status = NV_ERR_NOT_SUPPORTED; + NV_PRINTF(LEVEL_ERROR, + "NVRM: %s: System suspend failed with current system suspend configuration. " + "Please change the system suspend configuration to s2idle in /sys/power/mem_sleep.\n", + __FUNCTION__); + } + } + else + { + if (pGpu->getProperty(pGpu, PDB_PROP_GPU_GCOFF_STATE_ENTERED)) + { + status = RmPowerManagement(pGpu, NV_PM_ACTION_RESUME); + pGpu->setProperty(pGpu, PDB_PROP_GPU_GCOFF_STATE_ENTERED, NV_FALSE); + pKernelMemorySystem->bPreserveComptagBackingStoreOnSuspend = NV_FALSE; + } + else + { + NV2080_CTRL_GC6_EXIT_PARAMS exitParams; + portMemSet(&exitParams, 0, sizeof(exitParams)); + + exitParams.flavorId = NV2080_CTRL_GC6_FLAVOR_ID_MSHYBRID; + exitParams.params.bIsRTD3Transition = NV_TRUE; + + status = gpuGc6Exit(pGpu, &exitParams); + } + } + + return status; +} + +NV_STATUS NV_API_CALL rm_power_management( + nvidia_stack_t *sp, + nv_state_t *pNv, + nv_pm_action_t pmAction +) +{ + THREAD_STATE_NODE threadState; + NV_STATUS rmStatus = NV_OK; + void *fp; + + NV_ENTER_RM_RUNTIME(sp,fp); + threadStateInit(&threadState, THREAD_STATE_FLAGS_NONE); + + NV_ASSERT_OK(os_flush_work_queue(pNv->queue)); + + // LOCK: acquire API lock + if ((rmStatus = rmapiLockAcquire(API_LOCK_FLAGS_NONE, RM_LOCK_MODULES_DYN_POWER)) == NV_OK) + { + OBJGPU *pGpu = NV_GET_NV_PRIV_PGPU(pNv); + + if (pGpu != NULL) + { + if ((rmStatus = os_ref_dynamic_power(pNv, NV_DYNAMIC_PM_FINE)) == NV_OK) + { + // LOCK: acquire GPUs lock + if ((rmStatus = rmGpuLocksAcquire(GPUS_LOCK_FLAGS_NONE, RM_LOCK_MODULES_DYN_POWER)) == NV_OK) + { + nv_priv_t *nvp = NV_GET_NV_PRIV(pNv); + + // + // Before going to S3 or S4, remove idle holdoff which was + // applied during gc6 exit. + // + if ((pmAction != NV_PM_ACTION_RESUME) && + (nvp->dynamic_power.b_idle_holdoff == NV_TRUE)) + { + nv_indicate_idle(pNv); + RmCancelCallbackToRemoveIdleHoldoff(pGpu); + nvp->dynamic_power.b_idle_holdoff = NV_FALSE; + } + + // + // Use GCx (GCOFF/GC6) power management if S0ix-based PM is + // enabled and the request is for system suspend/resume. + // Otherwise, use the existing mechanism. + // + if (nvp->s0ix_pm_enabled && + (pmAction == NV_PM_ACTION_STANDBY || + (pmAction == NV_PM_ACTION_RESUME && + !nvp->pm_state.InHibernate))) + { + rmStatus = RmGcxPowerManagement(pGpu, + pmAction == NV_PM_ACTION_STANDBY, + NV_FALSE); + + } + else + { + rmStatus = RmPowerManagement(pGpu, pmAction); + } + + // UNLOCK: release GPUs lock + rmGpuLocksRelease(GPUS_LOCK_FLAGS_NONE, NULL); + } + os_unref_dynamic_power(pNv, NV_DYNAMIC_PM_FINE); + } + } + // UNLOCK: release API lock + rmapiLockRelease(); + } + + NV_ASSERT_OK(os_flush_work_queue(pNv->queue)); + + threadStateFree(&threadState, THREAD_STATE_FLAGS_NONE); + NV_EXIT_RM_RUNTIME(sp,fp); + + return rmStatus; +} + +/*! + * @brief Wrapper around RmGcxPowerManagement() and removes the Idle holdoff + * during exit sequence. + * + * The GPU lock should be held when calling this function. + * + * @param[in] pGpu OBJGPU pointer. + * @param[in] bEnter If true, perform entry sequence; exit sequence + * otherwise. + * + * @return NV_STATUS code indicating if the operation was successful. + */ +static NV_STATUS RmTransitionDynamicPower( + OBJGPU *pGpu, + NvBool bEnter +) +{ + nv_state_t *nv = NV_GET_NV_STATE(pGpu); + NV_STATUS status; + + status = RmGcxPowerManagement(pGpu, bEnter, NV_TRUE); + + if (!bEnter && status == NV_OK) + { + nv_idle_holdoff(nv); + RmScheduleCallbackToRemoveIdleHoldoff(pGpu); + } + + return status; +} + +/*! + * @brief Wrapper around RmTransitionDynamicPower() which sets up the RM + * runtime (thread state and altstack), and takes the GPU lock for the duration + * of the operation. + * + * @param[in] sp nvidia_stack_t pointer. + * @param[in] nv nv_state_t pointer. + * @param[in] bEnter If true, perform entry sequence; exit sequence + * otherwise. + * + * @return NV_STATUS code indicating if the operation was successful. + */ +NV_STATUS NV_API_CALL rm_transition_dynamic_power( + nvidia_stack_t *sp, + nv_state_t *nv, + NvBool bEnter +) +{ + OBJGPU *pGpu = NV_GET_NV_PRIV_PGPU(nv); + NV_STATUS status = NV_OK; + THREAD_STATE_NODE threadState; + void *fp; + + NV_ENTER_RM_RUNTIME(sp,fp); + + threadStateInit(&threadState, THREAD_STATE_FLAGS_NONE); + + // LOCK: acquire GPUs lock + status = rmGpuLocksAcquire(GPUS_LOCK_FLAGS_NONE, RM_LOCK_MODULES_DYN_POWER); + if (status == NV_OK) + { + status = RmTransitionDynamicPower(pGpu, bEnter); + + // UNLOCK: release GPUs lock + rmGpuLocksRelease(GPUS_LOCK_FLAGS_NONE, NULL); + } + + threadStateFree(&threadState, THREAD_STATE_FLAGS_NONE); + + NV_EXIT_RM_RUNTIME(sp,fp); + + return status; +} + +/*! + * @brief: Notify client about hot-plugged/unplugged displays. + * Called after GPU exits GC6 because of display hot-plug/unplug. + * + * @param[in] nv nv_state_t pointer. + */ +static void RmNotifyClientAboutHotplug( + nv_state_t *nv +) +{ + NV_STATUS status; + GPU_MASK gpuMask; + OBJGPU *pGpu = NV_GET_NV_PRIV_PGPU(nv); + + Nv2080HotplugNotification hotplugNotificationParams; + + portMemSet(&hotplugNotificationParams, 0, sizeof(hotplugNotificationParams)); + + // LOCK: acquire per device lock + status = rmGpuGroupLockAcquire(pGpu->gpuInstance, GPU_LOCK_GRP_SUBDEVICE, + GPUS_LOCK_FLAGS_NONE, RM_LOCK_MODULES_HOTPLUG, + &gpuMask); + if (status == NV_OK) + { + gpuNotifySubDeviceEvent(pGpu, NV2080_NOTIFIERS_HOTPLUG, + &hotplugNotificationParams, + sizeof(hotplugNotificationParams), 0, 0); + // UNLOCK: release per device lock + rmGpuGroupLockRelease(gpuMask, GPUS_LOCK_FLAGS_NONE); + } +} + +/*! + * @brief If GPU is in GC6, exit GC6 state and + * notify client about display hot-plug/unplug. + * + * @param[in] sp nvidia_stack_t pointer. + * @param[in] nv nv_state_t pointer. + */ +void RmHandleDisplayChange( + nvidia_stack_t *sp, + nv_state_t *nv +) +{ + OBJGPU *pGpu = NV_GET_NV_PRIV_PGPU(nv); + + if (pGpu && + (IS_GPU_GC6_STATE_ENTERED(pGpu) || + pGpu->getProperty(pGpu, PDB_PROP_GPU_GCOFF_STATE_ENTERED))) + { + if (rm_ref_dynamic_power(sp, nv, NV_DYNAMIC_PM_FINE) == NV_OK) + { + RmNotifyClientAboutHotplug(nv); + rm_unref_dynamic_power(sp, nv, NV_DYNAMIC_PM_FINE); + } + else + NV_PRINTF(LEVEL_ERROR, + "NVRM: %s: Failed to increment dynamic power refcount\n", + __FUNCTION__); + } +} + +/*! + * @brief: Function to query Dynamic Power Management + * + * @param[in] sp nvidia_stack_t pointer. + * @param[in] pNv nv_state_t pointer. + * + * @return String indicating Dynamic Power Management status. + */ +const char* NV_API_CALL rm_get_dynamic_power_management_status( + nvidia_stack_t *sp, + nv_state_t *pNv +) +{ + void *fp; + nv_priv_t *nvp = NV_GET_NV_PRIV(pNv); + const char *returnString = "?"; + + NV_ENTER_RM_RUNTIME(sp,fp); + + // LOCK: acquire API lock + if ((rmapiLockAcquire(API_LOCK_FLAGS_NONE, RM_LOCK_MODULES_DYN_POWER)) == NV_OK) + { + OBJGPU *pGpu = NV_GET_NV_PRIV_PGPU(pNv); + + // Check if RM is inited + if (pGpu != NULL) + { + /* + * If the platform/driver does not support Dynamic Power Management, + * we set mode as NV_DYNAMIC_PM_NEVER. Hence, after RmInit if the + * mode is still NV_DYNAMIC_PM_FINE, we are sure that it is + * supported and enabled. Also see NOTE. + */ + if (nvp->dynamic_power.mode == NV_DYNAMIC_PM_FINE) + { + returnString = "Enabled (fine-grained)"; + } + else if (nvp->dynamic_power.mode == NV_DYNAMIC_PM_COARSE) + { + returnString = "Enabled (coarse-grained)"; + } + else if (nvp->dynamic_power.mode == NV_DYNAMIC_PM_NEVER) + { + + if (nvp->dynamic_power.dynamic_power_regkey == + NV_REG_DYNAMIC_POWER_MANAGEMENT_NEVER) + returnString = "Disabled"; + else if (nvp->dynamic_power.dynamic_power_regkey == + NV_REG_DYNAMIC_POWER_MANAGEMENT_DEFAULT) + returnString = "Disabled by default"; + else + returnString = "Not supported"; + } + } + //UNLOCK: release API lock + rmapiLockRelease(); + } + + NV_EXIT_RM_RUNTIME(sp,fp); + + return returnString; +} + +static void RmHandleIdleSustained( + NvU32 gpuInstance, + void *pArgs +) +{ + OBJGPU *pGpu = gpumgrGetGpu(gpuInstance); + nv_state_t *nv = NV_GET_NV_STATE(pGpu); + nv_priv_t *nvp = NV_GET_NV_PRIV(nv); + + nv_revoke_gpu_mappings(NV_GET_NV_STATE(pGpu)); + RmScheduleCallbackToIndicateIdle(pGpu); + nvp->dynamic_power.b_idle_sustained_workitem_queued = NV_FALSE; +} + +/* + * Queue a workitem for revoking GPU mappings, and scheduling a callback to indicate idle. + */ +static void RmQueueIdleSustainedWorkitem( + OBJGPU *pGpu +) +{ + nv_state_t *nv = NV_GET_NV_STATE(pGpu); + nv_priv_t *nvp = NV_GET_NV_PRIV(nv); + OBJOS *pOS = GPU_GET_OS(pGpu); + NV_STATUS status = NV_OK; + + if (!nvp->dynamic_power.b_idle_sustained_workitem_queued) + { + status = pOS->osQueueWorkItemWithFlags(pGpu, + RmHandleIdleSustained, + NULL, + OS_QUEUE_WORKITEM_FLAGS_LOCK_GPU_GROUP_SUBDEVICE_RW); + if (status != NV_OK) + { + NV_PRINTF(LEVEL_WARNING, + "NVRM: %s: Failed to queue RmHandleIdleSustained() workitem.\n", + __FUNCTION__); + RmScheduleCallbackForIdlePreConditionsUnderGpuLock(pGpu); + return; + } + nvp->dynamic_power.b_idle_sustained_workitem_queued = NV_TRUE; + } +} + +/* + * Allocate resources needed for S0ix-based system power management. + */ +void +RmInitS0ixPowerManagement( + nv_state_t *nv +) +{ + nv_priv_t *nvp = NV_GET_NV_PRIV(nv); + NvU32 data; + NvBool bRtd3Gc6Support = NV_FALSE; + + // LOCK: acquire GPUs lock + if (rmGpuLocksAcquire(GPUS_LOCK_FLAGS_NONE, RM_LOCK_MODULES_INIT) == NV_OK) + { + bRtd3Gc6Support = RmCheckRtd3Gc6Support(nv); + + // UNLOCK: release GPUs lock + rmGpuLocksRelease(GPUS_LOCK_FLAGS_NONE, NULL); + } + + /* + * The GPU S0ix-based system power management will be enabled + * only if all the following necessary requirements are met: + * + * 1. The GPU has RTD3 support. + * 2. The platform has support for s0ix. + * 3. Feature regkey EnableS0ixPowerManagement is enabled. + */ + if (bRtd3Gc6Support && + nv_platform_supports_s0ix() && + (osReadRegistryDword(NULL, NV_REG_ENABLE_S0IX_POWER_MANAGEMENT, + &data) == NV_OK) && (data == 1)) + { + nvp->s0ix_pm_enabled = NV_TRUE; + + /* + * Read the OS registry for Maximum FB size for S0ix-based PM + * which will be expressed in Megabytes (1048576 bytes) and + * convert it into bytes. + */ + if ((osReadRegistryDword(NULL, + NV_REG_S0IX_POWER_MANAGEMENT_VIDEO_MEMORY_THRESHOLD, + &data) == NV_OK)) + { + nvp->s0ix_gcoff_max_fb_size = (NvU64)data * 1024 * 1024; + } + } +} diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/arch/nvalloc/unix/src/escape.c nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/arch/nvalloc/unix/src/escape.c --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/arch/nvalloc/unix/src/escape.c 2023-10-25 20:20:29.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/arch/nvalloc/unix/src/escape.c 2024-03-05 22:12:48.000000000 +0000 @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 1999-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 1999-2024 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -74,7 +74,7 @@ { switch(pApi->cmd) { - case NV00FD_CTRL_CMD_ATTACH_MEM: + case NV00FD_CTRL_CMD_ATTACH_GPU: return NV_TRUE; default: return NV_FALSE; @@ -92,8 +92,8 @@ switch(pApi->cmd) { - case NV00FD_CTRL_CMD_ATTACH_MEM: - paramSize = sizeof(NV00FD_CTRL_ATTACH_MEM_PARAMS); + case NV00FD_CTRL_CMD_ATTACH_GPU: + paramSize = sizeof(NV00FD_CTRL_ATTACH_GPU_PARAMS); break; default: return NV_ERR_INVALID_ARGUMENT; @@ -107,8 +107,8 @@ switch(pApi->cmd) { - case NV00FD_CTRL_CMD_ATTACH_MEM: - *pFd = (NvS32)((NV00FD_CTRL_ATTACH_MEM_PARAMS *)pKernelParams)->devDescriptor; + case NV00FD_CTRL_CMD_ATTACH_GPU: + *pFd = (NvS32)((NV00FD_CTRL_ATTACH_GPU_PARAMS *)pKernelParams)->devDescriptor; break; default: NV_ASSERT(0); @@ -157,25 +157,11 @@ } else if (rmStatus == NV_ERR_INVALID_ADDRESS) { - rmStatus = os_lookup_user_io_memory(pDescriptor, pageCount, - &pPteArray, &pPageArray); + rmStatus = os_lookup_user_io_memory(pDescriptor, pageCount, &pPteArray); if (rmStatus == NV_OK) { - if (pPageArray != NULL) - { - pApi->data.AllocOsDesc.descriptor = (NvP64)(NvUPtr)pPageArray; - pApi->data.AllocOsDesc.descriptorType = NVOS32_DESCRIPTOR_TYPE_OS_PAGE_ARRAY; - } - else if (pPteArray != NULL) - { - pApi->data.AllocOsDesc.descriptor = (NvP64)(NvUPtr)pPteArray; - pApi->data.AllocOsDesc.descriptorType = NVOS32_DESCRIPTOR_TYPE_OS_IO_MEMORY; - } - else - { - NV_ASSERT_FAILED("unknown memory import type"); - rmStatus = NV_ERR_NOT_SUPPORTED; - } + pApi->data.AllocOsDesc.descriptor = (NvP64)(NvUPtr)pPteArray; + pApi->data.AllocOsDesc.descriptorType = NVOS32_DESCRIPTOR_TYPE_OS_IO_MEMORY; } } if (rmStatus != NV_OK) diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/arch/nvalloc/unix/src/exports-stubs.c nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/arch/nvalloc/unix/src/exports-stubs.c --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/arch/nvalloc/unix/src/exports-stubs.c 2023-10-25 20:20:29.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/arch/nvalloc/unix/src/exports-stubs.c 2024-03-05 22:12:48.000000000 +0000 @@ -22,214 +22,9 @@ */ #include +#include "os/os.h" #include #include #include #include -NV_STATUS NV_API_CALL rm_schedule_gpu_wakeup( - nvidia_stack_t *sp, - nv_state_t *nv -) -{ - return NV_OK; -} - -void NV_API_CALL rm_init_dynamic_power_management( - nvidia_stack_t *sp, - nv_state_t *nv, - NvBool bPr3AcpiMethodPresent -) -{ -} - -void NV_API_CALL rm_cleanup_dynamic_power_management( - nvidia_stack_t *sp, - nv_state_t *nv -) -{ -} - -void NV_API_CALL rm_enable_dynamic_power_management( - nvidia_stack_t *sp, - nv_state_t *nv -) -{ -} - -NV_STATUS NV_API_CALL rm_ref_dynamic_power( - nvidia_stack_t *sp, - nv_state_t *nv, - nv_dynamic_power_mode_t mode -) -{ - return NV_OK; -} - -void NV_API_CALL rm_unref_dynamic_power( - nvidia_stack_t *sp, - nv_state_t *nv, - nv_dynamic_power_mode_t mode -) -{ -} - -NV_STATUS NV_API_CALL rm_transition_dynamic_power( - nvidia_stack_t *sp, - nv_state_t *nv, - NvBool bEnter -) -{ - return NV_OK; -} - -NV_STATUS NV_API_CALL rm_power_management( - nvidia_stack_t *sp, - nv_state_t *pNv, - nv_pm_action_t pmAction -) -{ - return NV_OK; -} - -const char* NV_API_CALL rm_get_vidmem_power_status( - nvidia_stack_t *sp, - nv_state_t *pNv -) -{ - return "?"; -} - -const char* NV_API_CALL rm_get_dynamic_power_management_status( - nvidia_stack_t *sp, - nv_state_t *pNv -) -{ - return "?"; -} - -const char* NV_API_CALL rm_get_gpu_gcx_support( - nvidia_stack_t *sp, - nv_state_t *pNv, - NvBool bGcxTypeGC6 -) -{ - return "?"; -} - -NV_STATUS -subdeviceCtrlCmdOsUnixGc6BlockerRefCnt_IMPL -( - Subdevice *pSubdevice, - NV2080_CTRL_OS_UNIX_GC6_BLOCKER_REFCNT_PARAMS *pParams -) -{ - return NV_OK; -} - -NV_STATUS -subdeviceCtrlCmdOsUnixAllowDisallowGcoff_IMPL -( - Subdevice *pSubdevice, - NV2080_CTRL_OS_UNIX_ALLOW_DISALLOW_GCOFF_PARAMS *pParams -) -{ - return NV_OK; -} - -NV_STATUS -subdeviceCtrlCmdOsUnixAudioDynamicPower_IMPL -( - Subdevice *pSubdevice, - NV2080_CTRL_OS_UNIX_AUDIO_DYNAMIC_POWER_PARAMS *pParams -) -{ - return NV_OK; -} - -void -RmUpdateGc6ConsoleRefCount -( - nv_state_t *nv, - NvBool bIncrease -) -{ -} - -void -RmInitS0ixPowerManagement -( - nv_state_t *nv -) -{ -} - -void -RmInitDeferredDynamicPowerManagement -( - nv_state_t *nv -) -{ -} - -void -RmDestroyDeferredDynamicPowerManagement -( - nv_state_t *nv -) -{ -} - -void RmHandleDisplayChange -( - nvidia_stack_t *sp, - nv_state_t *nv -) -{ -} - -NV_STATUS -os_ref_dynamic_power -( - nv_state_t *nv, - nv_dynamic_power_mode_t mode -) -{ - return NV_OK; -} - -void -os_unref_dynamic_power -( - nv_state_t *nv, - nv_dynamic_power_mode_t mode -) -{ -} - -NV_STATUS -deviceCtrlCmdOsUnixVTSwitch_IMPL -( - Device *pDevice, - NV0080_CTRL_OS_UNIX_VT_SWITCH_PARAMS *pParams -) -{ - return NV_OK; -} - -NV_STATUS NV_API_CALL rm_save_low_res_mode( - nvidia_stack_t *sp, - nv_state_t *pNv -) -{ - return NV_ERR_NOT_SUPPORTED; -} - -NV_STATUS RmInitX86EmuState(OBJGPU *pGpu) -{ - return NV_OK; -} - -void RmFreeX86EmuState(OBJGPU *pGpu) -{ -} diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/arch/nvalloc/unix/src/os-hypervisor.c nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/arch/nvalloc/unix/src/os-hypervisor.c --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/arch/nvalloc/unix/src/os-hypervisor.c 2023-10-25 20:20:29.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/arch/nvalloc/unix/src/os-hypervisor.c 2024-03-05 22:12:49.000000000 +0000 @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 2014-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2014-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -62,6 +62,16 @@ return os_is_vgx_hyper(); } +NvBool hypervisorIsAC_IMPL(void) +{ + return NV_FALSE; +} + +void hypervisorSetACSupported_IMPL(POBJHYPERVISOR pHypervisor) +{ + pHypervisor->bIsACSupported = NV_TRUE; +} + NV_STATUS hypervisorInjectInterrupt_IMPL ( POBJHYPERVISOR pHypervisor, @@ -711,7 +721,8 @@ { if (pKernelHostVgpuDevice->gfid != 0) { - rmStatus = kbifGetNumVFSparseMmapRegions_HAL(pGpu, pKernelBif, pKernelHostVgpuDevice, numAreas); + rmStatus = kbifGetVFSparseMmapRegions_HAL(pGpu, pKernelBif, pKernelHostVgpuDevice, os_page_size, + numAreas, NULL, NULL); if (rmStatus == NV_OK) { os_alloc_mem((void **)&vfRegionOffsets, sizeof(NvU64) * (*numAreas)); @@ -719,7 +730,7 @@ if (vfRegionOffsets && vfRegionSizes) { rmStatus = kbifGetVFSparseMmapRegions_HAL(pGpu, pKernelBif, pKernelHostVgpuDevice, os_page_size, - vfRegionOffsets, vfRegionSizes); + numAreas, vfRegionOffsets, vfRegionSizes); if (rmStatus == NV_OK) { *offsets = vfRegionOffsets; @@ -992,12 +1003,20 @@ return os_call_vgpu_vfio((void *) &vgpu_info, CMD_VGPU_VFIO_PRESENT); } +NV_STATUS osIsVfioPciCorePresent(void) +{ + vgpu_vfio_info vgpu_info; + + return os_call_vgpu_vfio((void *) &vgpu_info, CMD_VFIO_PCI_CORE_PRESENT); +} + + void initVGXSpecificRegistry(OBJGPU *pGpu) { NvU32 data32; -#if !defined(NVCPU_X86_64) - osWriteRegistryDword(pGpu, NV_REG_STR_RM_BAR2_APERTURE_SIZE_MB, 4); -#endif + osWriteRegistryDword(pGpu, NV_REG_STR_RM_POWER_FEATURES, 0x55455555); + osWriteRegistryDword(pGpu, NV_REG_STR_RM_INFOROM_DISABLE_BBX, + NV_REG_STR_RM_INFOROM_DISABLE_BBX_YES); osWriteRegistryDword(pGpu, NV_REG_PROCESS_NONSTALL_INTR_IN_LOCKLESS_ISR, NV_REG_PROCESS_NONSTALL_INTR_IN_LOCKLESS_ISR_ENABLE); if ((osReadRegistryDword(pGpu, NV_REG_STR_RM_DUMP_NVLOG, &data32) != NV_OK)) diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/arch/nvalloc/unix/src/os.c nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/arch/nvalloc/unix/src/os.c --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/arch/nvalloc/unix/src/os.c 2023-10-25 20:20:30.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/arch/nvalloc/unix/src/os.c 2024-03-05 22:12:49.000000000 +0000 @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 1999-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 1999-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -45,6 +45,7 @@ #include "mem_mgr/io_vaspace.h" #include #include "gpu/mem_mgr/mem_desc.h" +#include "gpu/mem_mgr/mem_mgr.h" #include "core/thread_state.h" #include #include @@ -299,7 +300,13 @@ offset = (Start & ~os_page_mask); Start &= os_page_mask; - Size = ((Size + offset + ~os_page_mask) & os_page_mask); + + if (!portSafeAddU64(Size, offset, &Size) || + !portSafeAddU64(Size, ~os_page_mask, &Size)) + { + return NULL; + } + Size &= os_page_mask; ptr = os_map_kernel_space(Start, Size, Mode); if (ptr != NULL) @@ -397,36 +404,33 @@ NV_STATUS rmStatus = NV_OK; void *pAllocPrivate = NULL; NvU64 *addrArray = NULL; - NvU64 numOsPages = pMemDesc->PageCount; - - addrArray = pMemDesc->_pteArray; + NvU64 numPages = pMemDesc->PageCount; + NvU64 i; - if (NV_RM_PAGE_SIZE < os_page_size) + addrArray = portMemAllocNonPaged(numPages * sizeof(NvU64)); + if (addrArray == NULL) { - NvU64 numPages; - NvU64 i; + return NV_ERR_NO_MEMORY; + } - numPages = pMemDesc->PageCount; - addrArray = portMemAllocNonPaged(numPages * sizeof(NvU64)); - if (addrArray == NULL) - { - return NV_ERR_NO_MEMORY; - } + portMemCopy((void*)addrArray, + (numPages * sizeof(NvU64)), + (void*)memdescGetPteArray(pMemDesc, AT_CPU), + (numPages * sizeof(NvU64))); - portMemCopy((void*)addrArray, - (numPages * sizeof(NvU64)), (void*)pMemDesc->_pteArray, - (numPages * sizeof(NvU64))); + if (NV_RM_PAGE_SIZE < os_page_size) + { RmDeflateRmToOsPageArray(addrArray, numPages); - numOsPages = NV_RM_PAGES_TO_OS_PAGES(numPages); + numPages = NV_RM_PAGES_TO_OS_PAGES(numPages); + } - for (i = 0; i < numOsPages; i++) - { - // Update GPA to system physical address - addrArray[i] += pKernelMemorySystem->coherentCpuFbBase; - } + for (i = 0; i < numPages; i++) + { + // Update GPA to system physical address + addrArray[i] += pKernelMemorySystem->coherentCpuFbBase; } - rmStatus = nv_register_phys_pages(nv, addrArray, numOsPages, NV_MEMORY_CACHED, &pAllocPrivate); + rmStatus = nv_register_phys_pages(nv, addrArray, numPages, NV_MEMORY_CACHED, &pAllocPrivate); if (rmStatus != NV_OK) { goto errors; @@ -435,10 +439,7 @@ memdescSetMemData(pMemDesc, pAllocPrivate, NULL); errors: - if (NV_RM_PAGE_SIZE < os_page_size) - { - portMemFree(addrArray); - } + portMemFree(addrArray); return rmStatus; } @@ -677,6 +678,21 @@ return rmStatus; } +void* osGetPidInfo(void) +{ + return os_get_pid_info(); +} + +void osPutPidInfo(void *pOsPidInfo) +{ + os_put_pid_info(pOsPidInfo); +} + +NV_STATUS osFindNsPid(void *pOsPidInfo, NvU32 *pNsPid) +{ + return os_find_ns_pid(pOsPidInfo, pNsPid); +} + NV_STATUS osAttachToProcess(void** ppProcessInfo, NvU32 ProcessId) { // @@ -892,6 +908,7 @@ nv_state_t *nv = NV_GET_NV_STATE(pGpu); void *pMemData = NULL; NV_STATUS status; + NvS32 nodeId = -1; memdescSetAddress(pMemDesc, NvP64_NULL); memdescSetMemData(pMemDesc, NULL, NULL); @@ -923,6 +940,20 @@ if (nv && (memdescGetFlag(pMemDesc, MEMDESC_FLAGS_ALLOC_32BIT_ADDRESSABLE))) nv->force_dma32_alloc = NV_TRUE; + // + // If AMD SEV is enabled but APM(Ampere protected) or CC(Confidential + // Compute) mode is not enabled on the GPU, all RM and client + // allocations must be an unprotected sysmem. If APM is enabled and RM + // is allocating sysmem for its internal use, then it has to be + // unprotected as protected sysmem is not accessible to GPU. + // + unencrypted = memdescGetFlag(pMemDesc, MEMDESC_FLAGS_ALLOC_IN_UNPROTECTED_MEMORY); + + if (pMemDesc->_addressSpace == ADDR_EGM) + { + nodeId = GPU_GET_MEMORY_MANAGER(pGpu)->localEgmNodeId; + } + if (NV_RM_PAGES_TO_OS_PAGES(pMemDesc->PageCount) > NV_U32_MAX) { status = NV_ERR_INVALID_LIMIT; @@ -937,6 +968,7 @@ pSys->getProperty(pSys, PDB_PROP_SYS_INITIALIZE_SYSTEM_MEMORY_ALLOCATIONS), unencrypted, + nodeId, memdescGetPteArray(pMemDesc, AT_CPU), &pMemData); } @@ -1211,14 +1243,6 @@ } } -NV_STATUS osDeviceClassToDeviceName( - NvU32 deviceInstance, - NvU8 *szName -) -{ - return NV_ERR_GENERIC; -} - static void postEvent( nv_event_t *event, NvU32 hEvent, @@ -1809,12 +1833,25 @@ if (hypervisorIsVgxHyper()) { - // - // 1.8 seconds is chosen because it is 90% of the overall hard limit of 2.0 - // seconds, imposed by WDDM driver rules. - // Currently primary use case of VGX is Windows, so setting 1.8 as default - // - *pTimeoutUs = 1.8 * 1000000; + if (IS_GSP_CLIENT(pGpu) && pGpu->getProperty(pGpu, PDB_PROP_GPU_EXTENDED_GSP_RM_INITIALIZATION_TIMEOUT_FOR_VGX) && + !pGpu->gspRmInitialized) + { + // + // For Hopper, 1.8 seconds is not enough to boot GSP-RM. + // To avoid this issue, 4 seconds timeout is set on initialization, + // and then it's going to be changed 1.8 seconds after GSP initialization. + // + *pTimeoutUs = 4 * 1000000; + } + else + { + // + // 1.8 seconds is chosen because it is 90% of the overall hard limit of 2.0 + // seconds, imposed by WDDM driver rules. + // Currently primary use case of VGX is Windows, so setting 1.8 as default + // + *pTimeoutUs = 1.8 * 1000000; + } } else { @@ -2518,6 +2555,26 @@ pAcpiDsmGuid = (NvU8 *) &PCFG_DSM_GUID; acpiDsmRev = PCFG_REVISION_ID; break; + case ACPI_DSM_FUNCTION_GPS_2X: + pAcpiDsmGuid = (NvU8 *) &GPS_DSM_GUID; + acpiDsmRev = GPS_2X_REVISION_ID; + acpiDsmInArgSize = (*pSize); + break; + case ACPI_DSM_FUNCTION_GPS: + if ((IsTU10X(pGpu)) || + ((gpuIsACPIPatchRequiredForBug2473619_HAL(pGpu)) && + ((acpiDsmSubFunction == GPS_FUNC_SUPPORT) || + (acpiDsmSubFunction == GPS_FUNC_GETCALLBACKS)))) + { + pAcpiDsmGuid = (NvU8 *) &GPS_DSM_GUID; + acpiDsmRev = GPS_REVISION_ID; + acpiDsmInArgSize = (*pSize); + } + else + { + return NV_ERR_NOT_SUPPORTED; + } + break; case ACPI_DSM_FUNCTION_PEX: pAcpiDsmGuid = (NvU8 *) &PEX_DSM_GUID; acpiDsmRev = PEX_REVISION_ID; @@ -2664,8 +2721,8 @@ { pConfig->bIsNotebook = rm_is_system_notebook(); pConfig->osType = nv_get_os_type(); - pConfig->osSevStatus = os_sev_status; - pConfig->bOsSevEnabled = os_sev_enabled; + pConfig->bOsCCEnabled = os_cc_enabled; + pConfig->bOsCCTdxEnabled = os_cc_tdx_enabled; } NvU32 osApiLockAcquireConfigureFlags(NvU32 flags) @@ -3029,7 +3086,32 @@ NvU32 *pOut ) { - return NV_ERR_NOT_SUPPORTED; + NV_STATUS status; + NvU32 inOut = cmd; + NvU16 rtnSize = sizeof(inOut); + + if (FLD_TEST_DRF(_JT_FUNC, _POWERCONTROL, _GPU_POWER_CONTROL, _GSS, inOut)) + { + if (!pOut) + { + return NV_ERR_INVALID_ARGUMENT; + } + } + + status = osCallACPI_DSM(pGpu, + ACPI_DSM_FUNCTION_JT, + JT_FUNC_POWERCONTROL, + &inOut, + &rtnSize); + + if ((status != NV_OK) || !pOut) + { + return status; + } + + *pOut = inOut; + + return NV_OK; } NvBool osTestPcieExtendedConfigAccess(void *handle, NvU32 offset) @@ -3584,8 +3666,8 @@ PTOKEN_USER pClientTokenUser = (PTOKEN_USER)pClientSecurityToken; PTOKEN_USER pCurrentTokenUser = (PTOKEN_USER)pCurrentSecurityToken; - NV_ASSERT_OR_RETURN((pClientTokenUser != NULL), NV_ERR_INVALID_POINTER); - NV_ASSERT_OR_RETURN((pCurrentTokenUser != NULL), NV_ERR_INVALID_POINTER); + if (pClientTokenUser == NULL || pCurrentTokenUser == NULL) + return NV_ERR_INVALID_POINTER; if ((pClientTokenUser->euid != pCurrentTokenUser->euid) && (pClientTokenUser->pid != pCurrentTokenUser->pid)) @@ -3902,7 +3984,7 @@ void *pMappedAddr = NULL; NvU64 basePAddr = 0; - if (!NVCPU_IS_X86_64) + if (!NVCPU_IS_X86_64 && !NVCPU_IS_AARCH64) { return NV_ERR_NOT_SUPPORTED; } @@ -4088,24 +4170,34 @@ return status; } -NV_STATUS +void osAllocAcquirePage ( - NvU64 pAddress + NvU64 pAddress, + NvU32 pageCount ) { - os_get_page(pAddress); - return NV_OK; + NvU32 i; + + for (i = 0; i < pageCount; i++) + { + os_get_page(pAddress + (i << os_page_shift)); + } } -NV_STATUS +void osAllocReleasePage ( - NvU64 pAddress + NvU64 pAddress, + NvU32 pageCount ) { - os_put_page(pAddress); - return NV_OK; + NvU32 i; + + for (i = 0; i < pageCount; i++) + { + os_put_page(pAddress + (i << os_page_shift)); + } } /* @@ -4183,12 +4275,18 @@ nv_wait_for_ibmnpu_rsync(pOsGpuInfo); } -NvU32 +NvU64 osGetPageSize(void) { return os_page_size; } +NvU8 +osGetPageShift(void) +{ + return os_page_shift; +} + /* @@ -4775,6 +4873,8 @@ * @brief Generates random bytes which can be used as a universally unique * identifier. * + * This function may sleep (interruptible). + * * @param[out] pBytes Array of random bytes * @param[in] numBytes Size of the array */ @@ -4785,9 +4885,7 @@ NvU16 numBytes ) { - os_get_random_bytes(pBytes, numBytes); - - return NV_OK; + return os_get_random_bytes(pBytes, numBytes); } /* @@ -4871,6 +4969,46 @@ } /*! + * @brief Sends an MRQ (message-request) to BPMP + * + * The request, response, and ret parameters of this function correspond to the + * components of the tegra_bpmp_message struct, which BPMP uses to receive + * MRQs. + * + * @param[in] pOsGpuInfo OS specific GPU information pointer + * @param[in] mrq MRQ_xxx ID specifying what is requested + * @param[in] pRequestData Pointer to request input data + * @param[in] requestDataSize Size of structure pointed to by pRequestData + * @param[out] pResponseData Pointer to response output data + * @param[in] responseDataSize Size of structure pointed to by pResponseData + * @param[out] ret MRQ return code (from "ret" element of + * tegra_bpmp_message struct) + * @param[out] apiRet Return code from tegra_bpmp_transfer call + * + * @returns NV_OK if successful, + * NV_ERR_NOT_SUPPORTED if the functionality is not available, + * NV_ERR_INVALID_POINTER if the tegra_bpmp struct pointer could not + * be obtained from nv, or + * NV_ERR_GENERIC if the tegra_bpmp_transfer call failed (see apiRet + * for Linux error code). + */ +NV_STATUS +osTegraSocBpmpSendMrq +( + OS_GPU_INFO *pOsGpuInfo, + NvU32 mrq, + const void *pRequestData, + NvU32 requestDataSize, + void *pResponseData, + NvU32 responseDataSize, + NvS32 *pRet, + NvS32 *pApiRet +) +{ + return NV_ERR_NOT_SUPPORTED; +} + +/*! * @brief Returns IMP-relevant data collected from other modules * * This function is basically a wrapper to call the unix/linux layer. @@ -4979,7 +5117,7 @@ * * @param[in] pOsGpuInfo OS specific GPU information pointer * @param[in] pTimer pointer to high resolution timer object - * @param[in] timens time in nano seconds + * @param[in] timeNs Relative time in nano seconds */ NV_STATUS osStartNanoTimer @@ -5242,6 +5380,82 @@ nv_put_file_private(pOsInfo); } +/*! + * @brief Get free, total memory of a NUMA node by NUMA node ID from kernel. + * + * @param[in] numaId NUMA node ID. + * @param[out] free_memory_bytes free memory in bytes. + * @param[out] total_memory_bytes total memory in bytes. + * + */ +void +osGetNumaMemoryUsage +( + NvS32 numaId, + NvU64 *free_memory_bytes, + NvU64 *total_memory_bytes +) +{ + NV_STATUS status = os_get_numa_node_memory_usage(numaId, + free_memory_bytes, + total_memory_bytes); + NV_ASSERT(status == NV_OK); +} + +/*! + * @brief Add GPU memory as a NUMA node. + * + * @param[in/out] pOsGpuInfo OS specific GPU information pointer + * @param[in] offset start offset of the partition within FB + * @param[in] size size of the partition + * @param[out] pNumaNodeId OS NUMA node id for the added memory. + * + * @returns NV_OK if all is okay. Otherwise an error-specific value. + * + */ +NV_STATUS +osNumaAddGpuMemory +( + OS_GPU_INFO *pOsGpuInfo, + NvU64 offset, + NvU64 size, + NvU32 *pNumaNodeId +) +{ + nv_state_t *nv = pOsGpuInfo; + + return os_numa_add_gpu_memory(nv->handle, offset, size, pNumaNodeId); +} + +/*! + * @brief Remove a particular SMC partition's GPU memory from OS kernel. + * + * Remove GPU memory from the OS kernel that is earlier added as a NUMA node + * to the kernel in platforms where GPU is coherently connected to the CPU. + * + * @param[in/out] pOsGpuInfo OS_GPU_INFO OS specific GPU information pointer + * @param[in] offset start offset of the partition within FB + * @param[in] size size of the partition + * @param[in] numaNodeId OS NUMA node id of the memory to be removed. + * + */ +void +osNumaRemoveGpuMemory +( + OS_GPU_INFO *pOsGpuInfo, + NvU64 offset, + NvU64 size, + NvU32 numaNodeId +) +{ + nv_state_t *nv = pOsGpuInfo; + + NV_STATUS status = os_numa_remove_gpu_memory(nv->handle, offset, size, numaNodeId); + NV_ASSERT(status == NV_OK); + + return; +} + NvBool osDmabufIsSupported(void) { @@ -5255,3 +5469,30 @@ if (nvfp != NULL) nvfp->bCleanupRmapi = NV_TRUE; } + +NV_STATUS +osGetEgmInfo +( + OBJGPU *pGpu, + NvU64 *pPhysAddr, + NvU64 *pSize, + NvS32 *pNodeId +) +{ + return nv_get_egm_info(NV_GET_NV_STATE(pGpu), pPhysAddr, pSize, pNodeId); +} + +/*! + * @brief Offline (i.e., blacklist) the page containing a given address from OS kernel. + * + * @param[in] address Address (SPA) of the page to be offlined + * + */ +NV_STATUS +osOfflinePageAtAddress +( + NvU64 address +) +{ + return os_offline_page_at_address(address); +} diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/arch/nvalloc/unix/src/osapi.c nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/arch/nvalloc/unix/src/osapi.c --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/arch/nvalloc/unix/src/osapi.c 2023-10-25 20:20:30.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/arch/nvalloc/unix/src/osapi.c 2024-03-05 22:12:49.000000000 +0000 @@ -31,6 +31,7 @@ #include #include // Declares RmInitRm(). #include "gpu/gpu.h" +#include "gps.h" #include #include @@ -59,6 +60,7 @@ #include #include #include "nv-reg.h" +#include "nv-firmware-registry.h" #include "core/hal_mgr.h" #include "gpu/device/device.h" @@ -86,6 +88,13 @@ #include "gpu/bus/kern_bus.h" // +// If timer callback comes when PM resume is in progress, then it can't be +// serviced. The timer needs to be rescheduled in this case. This time controls +// the duration of rescheduling. +// +#define TIMER_RESCHED_TIME_DURING_PM_RESUME_NS (100 * 1000 * 1000) + +// // Helper function which can be called before doing any RM control // This function: // @@ -412,7 +421,7 @@ NvU32 *pClientList; NvU32 numClients, i; NV_STATUS status; - RM_API *pRmApi = rmapiGetInterface(RMAPI_GPU_LOCK_INTERNAL); + RM_API *pRmApi = rmapiGetInterface(RMAPI_API_LOCK_INTERNAL); // // The 'nvfp' pointer uniquely identifies an open instance in kernel space @@ -435,7 +444,7 @@ if (numClients != 0) { - pRmApi->FreeClientList(pRmApi, pClientList, numClients); + pRmApi->DisableClients(pRmApi, pClientList, numClients); portMemFree(pClientList); } @@ -1018,6 +1027,16 @@ NvBool relaxed = NV_FALSE; NvU32 i; + // + // rmStr (i.e., NV_VERSION_STRING) must be null-terminated and fit within + // NV_RM_API_VERSION_STRING_LENGTH, so that: + // + // (1) If the versions don't match, we can return rmStr in + // pParams->versionString. + // (2) The below loop is guaranteed to not overrun rmStr. + // + ct_assert(sizeof(NV_VERSION_STRING) <= NV_RM_API_VERSION_STRING_LENGTH); + if (dataSize != sizeof(nv_ioctl_rm_api_version_t)) return NV_ERR_INVALID_ARGUMENT; @@ -1030,11 +1049,11 @@ pParams->reply = NV_RM_API_VERSION_REPLY_RECOGNIZED; // - // the client requested to override the version check; just return - // success. + // the client is just querying the version, not verifying against expected. // - if (pParams->cmd == NV_RM_API_VERSION_CMD_OVERRIDE) + if (pParams->cmd == NV_RM_API_VERSION_CMD_QUERY) { + os_string_copy(pParams->versionString, rmStr); return NV_OK; } @@ -1047,19 +1066,6 @@ relaxed = NV_TRUE; } - // - // rmStr (i.e., NV_VERSION_STRING) must be null-terminated and fit within - // NV_RM_API_VERSION_STRING_LENGTH, so that: - // - // (1) If the versions don't match, we can return rmStr in - // pParams->versionString. - // (2) The below loop is guaranteed to not overrun rmStr. - // - if ((os_string_length(rmStr) + 1) > NV_RM_API_VERSION_STRING_LENGTH) - { - return NV_ERR_BUFFER_TOO_SMALL; - } - for (i = 0; i < NV_RM_API_VERSION_STRING_LENGTH; i++) { clientCh = pParams->versionString[i]; @@ -1163,11 +1169,46 @@ } /*! + * @brief Function to request latest D-Notifier status from SBIOS. + * + * Handle certain scenarios (like a fresh boot or suspend/resume + * of the system) when RM is not available to receive the Dx notifiers. + * This function gets the latest D-Notifier status from SBIOS + * when RM is ready to receive and handle those events. + * Use GPS_FUNC_REQUESTDXSTATE subfunction to invoke current Dx state. + * + * @param[in] pNv nv_state_t pointer. + */ +void RmRequestDNotifierState( + nv_state_t *pNv +) +{ + OBJGPU *pGpu = NV_GET_NV_PRIV_PGPU(pNv); + NvU32 supportedFuncs = 0; + NvU16 dsmDataSize = sizeof(supportedFuncs); + NV_STATUS status = NV_OK; + + status = osCallACPI_DSM(pGpu, ACPI_DSM_FUNCTION_GPS_2X, + GPS_FUNC_REQUESTDXSTATE, &supportedFuncs, + &dsmDataSize); + if (status != NV_OK) + { + // + // Call for 'GPS_FUNC_REQUESTDXSTATE' subfunction may fail if the + // SBIOS/EC does not have the corresponding implementation. + // + NV_PRINTF(LEVEL_INFO, + "%s: Failed to request Dx event update, status 0x%x\n", + __FUNCTION__, status); + } +} + +/*! * @brief Deal with D-notifier events to apply a performance * level based on the requested auxiliary power-state. * Read confluence page "D-Notifiers on Linux" for more details. * - * @param[in] pGpu OBJGPU pointer. + * @param[in] pNv nv_state_t pointer. * @param[in] event_type NvU32 Event type. */ static void RmHandleDNotifierEvent( @@ -1224,12 +1265,13 @@ static NV_STATUS RmDmabufVerifyMemHandle( - OBJGPU *pGpu, - NvHandle hSrcClient, - NvHandle hMemory, - NvU64 offset, - NvU64 size, - void *pGpuInstanceInfo + OBJGPU *pGpu, + NvHandle hSrcClient, + NvHandle hMemory, + NvU64 offset, + NvU64 size, + void *pGpuInstanceInfo, + MEMORY_DESCRIPTOR **ppMemDesc ) { NV_STATUS status; @@ -1292,6 +1334,8 @@ return NV_ERR_INVALID_ARGUMENT; } + *ppMemDesc = pMemDesc; + return NV_OK; } @@ -1363,6 +1407,24 @@ NV_ASSERT_OK(kmigmgrDecRefCount(pKernelMIGGpuInstance->pShare)); } +static void +RmHandleNvpcfEvents( + nv_state_t *pNv +) +{ + OBJGPU *pGpu = NV_GET_NV_PRIV_PGPU(pNv); + THREAD_STATE_NODE threadState; + + if (RmUnixRmApiPrologue(pNv, &threadState, RM_LOCK_MODULES_ACPI) == NULL) + { + return; + } + + gpuNotifySubDeviceEvent(pGpu, NV2080_NOTIFIERS_NVPCF_EVENTS, NULL, 0, 0, 0); + + RmUnixRmApiEpilogue(pNv, &threadState); +} + /* * --------------------------------------------------------------------------- * @@ -1654,6 +1716,43 @@ nv_state_t *pNv ) { + NV_STATUS rmStatus; + RM_API *pRmApi; + THREAD_STATE_NODE threadState; + NV0000_CTRL_SYSTEM_GPS_CONTROL_PARAMS gpsControl = { 0 }; + + pRmApi = RmUnixRmApiPrologue(pNv, &threadState, RM_LOCK_MODULES_ACPI); + if (pRmApi == NULL) + { + return; + } + + gpsControl.command = NV0000_CTRL_CMD_SYSTEM_GPS_DATA_INIT_USING_SBIOS_AND_ACK; + gpsControl.locale = NV0000_CTRL_CMD_SYSTEM_GPS_LOCALE_SYSTEM; + + // + // NV0000_CTRL_CMD_SYSTEM_GPS_CONTROL is not a subdevice command. + // But, Inside GPS module, the first GPU, which has GPS + // enabled will be grabbed with GPU manager. The RMAPI_API_LOCK_INTERNAL + // will internally grab the GPU locks and wake-up all the GPUs. Ideally + // this control call should be GPU specific command, if internally + // it uses the GPU. + // + rmStatus = pRmApi->Control(pRmApi, + pNv->rmapi.hClient, + pNv->rmapi.hClient, + NV0000_CTRL_CMD_SYSTEM_GPS_CONTROL, + (void *)&gpsControl, + sizeof(NV0000_CTRL_SYSTEM_GPS_CONTROL_PARAMS)); + + RmUnixRmApiEpilogue(pNv, &threadState); + + if (rmStatus != NV_OK) + { + NV_PRINTF(LEVEL_ERROR, + "%s: Failed to handle ACPI GPS status change event, status=0x%x\n", + __FUNCTION__, rmStatus); + } } /*! @@ -1910,15 +2009,20 @@ { if (CliSetGpuContext(hClient, hDevice, &pGpu, NULL) != NV_OK) { - NvU32 tmp; - if (CliSetSubDeviceContext(hClient, hDevice, &tmp, &pGpu) != NV_OK) - { - // - // If this mapping isn't for a GPU then we don't need to - // create a context for it. - // + RsClient *pClient; + Subdevice *pSubdevice; + + status = serverGetClientUnderLock(&g_resServ, hClient, &pClient); + if (status != NV_OK) return status; - } + + status = subdeviceGetByHandle(pClient, hDevice, &pSubdevice); + if (status != NV_OK) + return status; + + pGpu = GPU_RES_GET_GPU(pSubdevice); + + GPU_RES_SET_THREAD_BC_STATE(pSubdevice); } } @@ -2117,6 +2221,7 @@ switch (memdescGetAddressSpace(pMemDesc)) { case ADDR_SYSMEM: + case ADDR_EGM: break; default: rmStatus = NV_ERR_OBJECT_NOT_FOUND; @@ -2456,6 +2561,27 @@ return rmStatus; } +static void _deferredClientListFreeCallback(void *unused) +{ + OBJSYS *pSys = SYS_GET_INSTANCE(); + NV_STATUS status = serverFreeDisabledClients(&g_resServ, 0, pSys->clientListDeferredFreeLimit); + // + // Possible return values: + // NV_WARN_MORE_PROCESSING_REQUIRED - Iteration limit reached, need to call again + // NV_ERR_IN_USE - Already running on another thread, try again later + // In both cases, schedule a worker to clean up anything that remains + // + if (status != NV_OK) + { + status = osQueueSystemWorkItem(_deferredClientListFreeCallback, unused); + if (status != NV_OK) + { + NV_PRINTF(LEVEL_NOTICE, "Failed to schedule deferred free callback. Freeing immediately.\n"); + serverFreeDisabledClients(&g_resServ, 0, 0); + } + } +} + void NV_API_CALL rm_cleanup_file_private( nvidia_stack_t *sp, nv_state_t *pNv, @@ -2467,6 +2593,7 @@ RM_API *pRmApi; RM_API_CONTEXT rmApiContext = {0}; NvU32 i; + OBJSYS *pSys = SYS_GET_INSTANCE(); NV_ENTER_RM_RUNTIME(sp,fp); @@ -2488,8 +2615,8 @@ return; } - // LOCK: acquire API lock - if (rmapiLockAcquire(API_LOCK_FLAGS_NONE, RM_LOCK_MODULES_OSAPI) == NV_OK) + // LOCK: acquire API lock. Low priority so cleanup doesn't block active threads + if (rmapiLockAcquire(RMAPI_LOCK_FLAGS_LOW_PRIORITY, RM_LOCK_MODULES_OSAPI) == NV_OK) { // Unref any object which was exported on this file. if (nvfp->handles != NULL) @@ -2510,13 +2637,21 @@ nvfp->maxHandles = 0; } - // Free any RM clients associated with this file. + // Disable any RM clients associated with this file. RmFreeUnusedClients(pNv, nvfp); + // Unless configured otherwise, immediately free all disabled clients + if (!pSys->bUseDeferredClientListFree) + serverFreeDisabledClients(&g_resServ, RM_LOCK_STATES_API_LOCK_ACQUIRED, 0); + // UNLOCK: release API lock rmapiLockRelease(); } + // Start the deferred free callback if necessary + if (pSys->bUseDeferredClientListFree) + _deferredClientListFreeCallback(NULL); + rmapiEpilogue(pRmApi, &rmApiContext); threadStateFree(&threadState, THREAD_STATE_FLAGS_NONE); @@ -2939,21 +3074,23 @@ if ((status = rmGpuLocksAcquire(GPU_LOCK_FLAGS_COND_ACQUIRE, RM_LOCK_MODULES_TMR)) != NV_OK) { TMR_EVENT *pEvent = (TMR_EVENT *)pTmrEvent; + NvU64 timeNs = pGpu->getProperty(pGpu, PDB_PROP_GPU_IN_PM_RESUME_CODEPATH) ? + TIMER_RESCHED_TIME_DURING_PM_RESUME_NS : + osGetTickResolution(); // // We failed to acquire the lock - depending on what's holding it, // the lock could be held for a while, so try again soon, but not too // soon to prevent the owner from making forward progress indefinitely. // - return osStartNanoTimer(pGpu->pOsGpuInfo, pEvent->pOSTmrCBdata, - osGetTickResolution()); + return osStartNanoTimer(pGpu->pOsGpuInfo, pEvent->pOSTmrCBdata, timeNs); } threadStateInitISRAndDeferredIntHandler(&threadState, pGpu, THREAD_STATE_FLAGS_IS_DEFERRED_INT_HANDLER); // Call timer event service - status = tmrEventServiceOSTimerCallback_HAL(pGpu, pTmr, (PTMR_EVENT)pTmrEvent); + status = tmrEventServiceTimer(pGpu, pTmr, (PTMR_EVENT)pTmrEvent); // Out of conflicting thread threadStateFreeISRAndDeferredIntHandler(&threadState, @@ -2983,7 +3120,7 @@ if (pGpu == NULL) return NV_ERR_GENERIC; - if (!FULL_GPU_SANITY_CHECK(pGpu)) + if (!FULL_GPU_SANITY_FOR_PM_RESUME(pGpu)) { return NV_ERR_GENERIC; } @@ -3120,37 +3257,6 @@ return RmStatus; } -static void rm_is_device_rm_firmware_capable( - nv_state_t *pNv, - NvU32 pmcBoot42, - NvBool *pbIsFirmwareCapable, - NvBool *pbEnableByDefault -) -{ - NvBool bIsFirmwareCapable = NV_FALSE; - NvBool bEnableByDefault = NV_FALSE; - - if (NV_IS_SOC_DISPLAY_DEVICE(pNv)) - { - bIsFirmwareCapable = NV_TRUE; - } - else - { - bIsFirmwareCapable = gpumgrIsDeviceRmFirmwareCapable(pNv->pci_info.device_id, - pmcBoot42, - &bEnableByDefault); - } - - if (pbIsFirmwareCapable != NULL) - { - *pbIsFirmwareCapable = bIsFirmwareCapable; - } - if (pbEnableByDefault != NULL) - { - *pbEnableByDefault = bEnableByDefault; - } -} - static NvBool NV_API_CALL rm_is_legacy_device( NvU16 device_id, NvU16 subsystem_vendor, @@ -3241,10 +3347,10 @@ { NvBool bIsFirmwareCapable; - rm_is_device_rm_firmware_capable(pNv, - pmc_boot_42, - &bIsFirmwareCapable, - NULL); + bIsFirmwareCapable = gpumgrIsDeviceRmFirmwareCapable(pNv->pci_info.device_id, + pmc_boot_42, + NV_IS_SOC_DISPLAY_DEVICE(pNv), + NULL); if (!bIsFirmwareCapable) { nv_printf(NV_DBG_ERRORS, @@ -4011,11 +4117,53 @@ NV_EXIT_RM_RUNTIME(sp,fp); } +void NV_API_CALL rm_request_dnotifier_state( + nv_stack_t *sp, + nv_state_t *pNv +) +{ + nv_priv_t *nvp = NV_GET_NV_PRIV(pNv); + + if (nvp->b_mobile_config_enabled) + { + THREAD_STATE_NODE threadState; + void *fp; + GPU_MASK gpuMask; + + NV_ENTER_RM_RUNTIME(sp,fp); + threadStateInit(&threadState, THREAD_STATE_FLAGS_NONE); + + // LOCK: acquire API lock + if ((rmapiLockAcquire(API_LOCK_FLAGS_NONE, RM_LOCK_MODULES_ACPI)) == NV_OK) + { + OBJGPU *pGpu = NV_GET_NV_PRIV_PGPU(pNv); + + // LOCK: acquire per device lock + if ((pGpu != NULL) && + ((rmGpuGroupLockAcquire(pGpu->gpuInstance, GPU_LOCK_GRP_SUBDEVICE, + GPUS_LOCK_FLAGS_NONE, RM_LOCK_MODULES_ACPI, + &gpuMask)) == NV_OK)) + { + RmRequestDNotifierState(pNv); + + // UNLOCK: release per device lock + rmGpuGroupLockRelease(gpuMask, GPUS_LOCK_FLAGS_NONE); + } + + // UNLOCK: release API lock + rmapiLockRelease(); + } + + threadStateFree(&threadState, THREAD_STATE_FLAGS_NONE); + NV_EXIT_RM_RUNTIME(sp,fp); + } +} + NV_STATUS NV_API_CALL rm_p2p_dma_map_pages( nvidia_stack_t *sp, nv_dma_device_t *peer, NvU8 *pGpuUuid, - NvU32 pageSize, + NvU64 pageSize, NvU32 pageCount, NvU64 *pDmaAddresses, void **ppPriv @@ -4417,25 +4565,14 @@ nv_state_t *nv ) { - NV_STATUS status; - NvU32 data; void *fp; + NvU32 enableFirmwareLogsRegVal = NV_REG_ENABLE_GPU_FIRMWARE_LOGS_ENABLE_ON_DEBUG; NV_ENTER_RM_RUNTIME(sp,fp); - status = RmReadRegistryDword(nv, NV_REG_ENABLE_GPU_FIRMWARE_LOGS, &data); - if (status == NV_OK) - { - if ((data == NV_REG_ENABLE_GPU_FIRMWARE_LOGS_ENABLE) -#if defined(DEBUG) || defined(DEVELOP) - || (data == NV_REG_ENABLE_GPU_FIRMWARE_LOGS_ENABLE_ON_DEBUG) -#endif - ) - { - nv->enable_firmware_logs = NV_TRUE; - } - } - + (void) RmReadRegistryDword(nv, NV_REG_ENABLE_GPU_FIRMWARE_LOGS, + &enableFirmwareLogsRegVal); + nv->enable_firmware_logs = gpumgrGetRmFirmwareLogsEnabled(enableFirmwareLogsRegVal); NV_EXIT_RM_RUNTIME(sp,fp); } @@ -4650,7 +4787,6 @@ // Check if NVPCF _DSM functions are implemented under NVPCF or GPU device scope. RmCheckNvpcfDsmScope(pGpu); acpiDsmInit(pGpu); - } // @@ -4995,16 +5131,11 @@ NvU64 fbBaseAddress = 0; NvBool bConsoleDevice = NV_FALSE; - // os_get_screen_info() will return dimensions and an address for - // any fbdev driver (e.g., efifb, vesafb, etc). To find if this is a - // UEFI console check the fbBaseAddress: if it was set up by the EFI GOP - // driver, it will point into BAR1 (FB); if it was set up by the VBIOS, - // it will point to BAR2 + 16MB. - os_get_screen_info(&fbBaseAddress, &fbWidth, &fbHeight, &fbDepth, &fbPitch, - nv->bars[NV_GPU_BAR_INDEX_FB].cpu_address, - nv->bars[NV_GPU_BAR_INDEX_IMEM].cpu_address + 0x1000000); - - fbSize = fbHeight * fbPitch; + // + // nv_get_screen_info() will return dimensions and an address for + // any fbdev driver (e.g., efifb, vesafb, etc). + // + nv_get_screen_info(nv, &fbBaseAddress, &fbWidth, &fbHeight, &fbDepth, &fbPitch, &fbSize); bConsoleDevice = (fbSize != 0); @@ -5021,16 +5152,11 @@ fbSize = fbWidth = fbHeight = fbDepth = fbPitch = 0; - // os_get_screen_info() will return dimensions and an address for - // any fbdev driver (e.g., efifb, vesafb, etc). To find if this is a - // UEFI console check the fbBaseAddress: if it was set up by the EFI GOP - // driver, it will point into BAR1 (FB); if it was set up by the VBIOS, - // it will point to BAR2 + 16MB. - os_get_screen_info(pFbBaseAddress, &fbWidth, &fbHeight, &fbDepth, &fbPitch, - nv->bars[NV_GPU_BAR_INDEX_FB].cpu_address, - nv->bars[NV_GPU_BAR_INDEX_IMEM].cpu_address + 0x1000000); - - fbSize = fbHeight * fbPitch; + // + // nv_get_screen_info() will return dimensions and an address for + // any fbdev driver (e.g., efifb, vesafb, etc). + // + nv_get_screen_info(nv, pFbBaseAddress, &fbWidth, &fbHeight, &fbDepth, &fbPitch, &fbSize); return fbSize; } @@ -5067,7 +5193,8 @@ NvBool NV_API_CALL rm_disable_iomap_wc(void) { OBJSYS *pSys = SYS_GET_INSTANCE(); - return pSys->pCl->getProperty(pSys, PDB_PROP_CL_DISABLE_IOMAP_WC) == NV_TRUE; + OBJCL *pCl = pSys->pCl; + return pCl->getProperty(pCl, PDB_PROP_CL_DISABLE_IOMAP_WC) == NV_TRUE; } // @@ -5085,9 +5212,11 @@ NvHandle hMemory, NvU64 offset, NvU64 size, - NvHandle *phMemoryDuped + NvHandle *phMemoryDuped, + void **ppStaticMemInfo ) { + MEMORY_DESCRIPTOR *pMemDesc; THREAD_STATE_NODE threadState; NV_STATUS rmStatus; OBJGPU *pGpu; @@ -5103,7 +5232,8 @@ NV_ASSERT(rmDeviceGpuLockIsOwner(gpuGetInstance(pGpu))); rmStatus = RmDmabufVerifyMemHandle(pGpu, hSrcClient, hMemory, - offset, size, pGpuInstanceInfo); + offset, size, pGpuInstanceInfo, + &pMemDesc); if (rmStatus == NV_OK) { RM_API *pRmApi = rmapiGetInterface(RMAPI_GPU_LOCK_INTERNAL); @@ -5137,6 +5267,7 @@ *phMemoryDuped = hMemoryDuped; } } + *ppStaticMemInfo = (void *) pMemDesc; } threadStateFree(&threadState, THREAD_STATE_FLAGS_NONE); @@ -5178,39 +5309,170 @@ NV_EXIT_RM_RUNTIME(sp,fp); } -// -// Maps a handle to BAR1. -// Must be called with API lock and GPU lock held. -// NV_STATUS NV_API_CALL rm_dma_buf_map_mem_handle( - nvidia_stack_t *sp, - nv_state_t *nv, - NvHandle hClient, - NvHandle hMemory, - NvU64 offset, - NvU64 size, - NvU64 *pBar1Va + nvidia_stack_t *sp, + nv_state_t *nv, + NvHandle hClient, + NvHandle hMemory, + NvU64 offset, + NvU64 size, + void *pStaticMemInfo, + nv_phys_addr_range_t **ppRanges, + NvU32 *pRangeCount ) { THREAD_STATE_NODE threadState; - NV_STATUS rmStatus; + NV_STATUS rmStatus = NV_ERR_INVALID_ARGUMENT; OBJGPU *pGpu; - KernelBus *pKernelBus; void *fp; NV_ENTER_RM_RUNTIME(sp,fp); threadStateInit(&threadState, THREAD_STATE_FLAGS_NONE); + NV_ASSERT_OR_GOTO(((ppRanges != NULL) && + (pRangeCount != NULL) && + (pStaticMemInfo != NULL)), Done); + pGpu = NV_GET_NV_PRIV_PGPU(nv); - pKernelBus = GPU_GET_KERNEL_BUS(pGpu); - NV_ASSERT(rmapiLockIsOwner()); + if (pGpu->getProperty(pGpu, PDB_PROP_GPU_COHERENT_CPU_MAPPING)) + { + KernelMemorySystem *pKernelMemorySystem = GPU_GET_KERNEL_MEMORY_SYSTEM(pGpu); + MEMORY_DESCRIPTOR *pMemDesc = (MEMORY_DESCRIPTOR *) pStaticMemInfo; + NvU32 memdescPageSize = memdescGetPageSize(pMemDesc, AT_GPU); + NvU64 prologueOffset = offset; + NvU64 prologueSize = 0; + NvU64 epilogueOffset = offset; + NvU64 epilogueSize = 0; + NvU64 mainOffset = offset; + NvU64 mainSize = 0; + NvU32 mainPageCount = 0; + NvU64 alignedOffset; + NvU32 pageCount = 0; + NvU32 index = 0; - NV_ASSERT(rmDeviceGpuLockIsOwner(gpuGetInstance(pGpu))); + alignedOffset = NV_ALIGN_UP64(offset, memdescPageSize); + + if ((size > 0) && offset != alignedOffset) + { + prologueOffset = offset; + prologueSize = NV_MIN(alignedOffset - offset, size); + pageCount++; + + size -= prologueSize; + } + + if (size > 0) + { + mainOffset = prologueOffset + prologueSize; + mainSize = NV_ALIGN_DOWN64(size, memdescPageSize); + mainPageCount = mainSize / memdescPageSize; + pageCount += mainPageCount; + + size -= mainSize; + } + + if (size > 0) + { + epilogueOffset = mainOffset + mainSize; + epilogueSize = size; + pageCount++; + + size -= epilogueSize; + } + + if ((pageCount == 0) || (size != 0)) + { + NV_ASSERT(0); + rmStatus = NV_ERR_INVALID_STATE; + goto Done; + } - rmStatus = kbusMapFbApertureByHandle(pGpu, pKernelBus, hClient, - hMemory, offset, size, pBar1Va); + rmStatus = os_alloc_mem((void **) ppRanges, + pageCount * sizeof(nv_phys_addr_range_t)); + if (rmStatus != NV_OK) + { + goto Done; + } + + // Fill the first unaligned segment + if (prologueSize > 0) + { + NvU64 physAddr = memdescGetPhysAddr(pMemDesc, AT_CPU, prologueOffset); + (*ppRanges)[0].addr = pKernelMemorySystem->coherentCpuFbBase + physAddr; + (*ppRanges)[0].len = prologueSize; + + index = 1; + } + + // Fill the aligned segments between first and last entries + while (mainPageCount != 0) + { + NvU64 physAddr = memdescGetPhysAddr(pMemDesc, AT_CPU, alignedOffset); + (*ppRanges)[index].addr = pKernelMemorySystem->coherentCpuFbBase + physAddr; + (*ppRanges)[index].len = memdescPageSize; + index++; + + alignedOffset += memdescPageSize; + mainPageCount--; + } + + // Fill the last unaligned segment + if (epilogueSize > 0) + { + NvU64 physAddr = memdescGetPhysAddr(pMemDesc, AT_CPU, epilogueOffset); + (*ppRanges)[index].addr = pKernelMemorySystem->coherentCpuFbBase + physAddr; + (*ppRanges)[index].len = epilogueSize; + index++; + } + + NV_ASSERT(index == pageCount); + + *pRangeCount = pageCount; + } + else + { + Device *pDevice; + RsClient *pClient; + KernelBus *pKernelBus; + NvU64 bar1Va; + + NV_ASSERT(rmapiLockIsOwner()); + NV_ASSERT(rmDeviceGpuLockIsOwner(gpuGetInstance(pGpu))); + + NV_ASSERT_OK_OR_GOTO(rmStatus, + serverGetClientUnderLock(&g_resServ, hClient, &pClient), + Done); + + NV_ASSERT_OK_OR_GOTO(rmStatus, + deviceGetByGpu(pClient, pGpu, NV_TRUE, &pDevice), + Done); + + pKernelBus = GPU_GET_KERNEL_BUS(pGpu); + + rmStatus = kbusMapFbApertureByHandle(pGpu, pKernelBus, hClient, + hMemory, offset, size, &bar1Va, + pDevice); + if (rmStatus != NV_OK) + { + goto Done; + } + + // Adjust this alloc when discontiguous BAR1 is supported + rmStatus = os_alloc_mem((void **) ppRanges, + sizeof(nv_phys_addr_range_t)); + if (rmStatus != NV_OK) + { + kbusUnmapFbApertureByHandle(pGpu, pKernelBus, hClient, + hMemory, bar1Va); + goto Done; + } + (*ppRanges)[0].addr = bar1Va; + (*ppRanges)[0].len = size; + *pRangeCount = 1; + } +Done: threadStateFree(&threadState, THREAD_STATE_FLAGS_NONE); NV_EXIT_RM_RUNTIME(sp,fp); @@ -5221,38 +5483,52 @@ // Unmaps a handle from BAR1. // Must be called with API lock and GPU lock held. // -NV_STATUS NV_API_CALL rm_dma_buf_unmap_mem_handle( - nvidia_stack_t *sp, - nv_state_t *nv, - NvHandle hClient, - NvHandle hMemory, - NvU64 size, - NvU64 bar1Va +void NV_API_CALL rm_dma_buf_unmap_mem_handle( + nvidia_stack_t *sp, + nv_state_t *nv, + NvHandle hClient, + NvHandle hMemory, + NvU64 size, + nv_phys_addr_range_t **ppRanges, + NvU32 rangeCount ) { THREAD_STATE_NODE threadState; - NV_STATUS rmStatus; + NV_STATUS rmStatus = NV_OK; OBJGPU *pGpu; - KernelBus *pKernelBus; + NvU32 i; void *fp; NV_ENTER_RM_RUNTIME(sp,fp); threadStateInit(&threadState, THREAD_STATE_FLAGS_NONE); + NV_ASSERT_OR_GOTO(((ppRanges != NULL) && (rangeCount != 0)), Done); + pGpu = NV_GET_NV_PRIV_PGPU(nv); - pKernelBus = GPU_GET_KERNEL_BUS(pGpu); - NV_ASSERT(rmapiLockIsOwner()); + if (!pGpu->getProperty(pGpu, PDB_PROP_GPU_COHERENT_CPU_MAPPING)) + { + KernelBus *pKernelBus; - NV_ASSERT(rmDeviceGpuLockIsOwner(gpuGetInstance(pGpu))); + NV_ASSERT(rmapiLockIsOwner()); + NV_ASSERT(rmDeviceGpuLockIsOwner(gpuGetInstance(pGpu))); + + pKernelBus = GPU_GET_KERNEL_BUS(pGpu); - rmStatus = kbusUnmapFbApertureByHandle(pGpu, pKernelBus, hClient, - hMemory, bar1Va); + for (i = 0; i < rangeCount; i++) + { + rmStatus = kbusUnmapFbApertureByHandle(pGpu, pKernelBus, hClient, + hMemory, (*ppRanges)[i].addr); + NV_ASSERT_OK(rmStatus); + } + } + + os_free_mem(*ppRanges); + *ppRanges = NULL; +Done: threadStateFree(&threadState, THREAD_STATE_FLAGS_NONE); NV_EXIT_RM_RUNTIME(sp,fp); - - return rmStatus; } NV_STATUS NV_API_CALL rm_dma_buf_get_client_and_device( @@ -5262,7 +5538,8 @@ NvHandle *phClient, NvHandle *phDevice, NvHandle *phSubdevice, - void **ppGpuInstanceInfo + void **ppGpuInstanceInfo, + NvBool *pbStaticPhysAddrs ) { THREAD_STATE_NODE threadState; @@ -5283,6 +5560,12 @@ { rmStatus = RmDmabufGetClientAndDevice(pGpu, hClient, phClient, phDevice, phSubdevice, ppGpuInstanceInfo); + if (rmStatus == NV_OK) + { + // Note: revisit this when BAR1 static map is supported. + *pbStaticPhysAddrs = pGpu->getProperty(pGpu, + PDB_PROP_GPU_COHERENT_CPU_MAPPING); + } rmDeviceGpuLocksRelease(pGpu, GPUS_LOCK_FLAGS_NONE, NULL); } @@ -5369,3 +5652,21 @@ return NV_FALSE; #endif } + +void NV_API_CALL rm_acpi_nvpcf_notify( + nvidia_stack_t *sp +) +{ + void *fp; + OBJGPU *pGpu = gpumgrGetGpu(0); + + NV_ENTER_RM_RUNTIME(sp,fp); + + if (pGpu != NULL) + { + nv_state_t *nv = NV_GET_NV_STATE(pGpu); + RmHandleNvpcfEvents(nv); + } + + NV_EXIT_RM_RUNTIME(sp,fp); +} diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/arch/nvalloc/unix/src/osinit.c nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/arch/nvalloc/unix/src/osinit.c --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/arch/nvalloc/unix/src/osinit.c 2023-10-25 20:20:30.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/arch/nvalloc/unix/src/osinit.c 2024-03-05 22:12:49.000000000 +0000 @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 1999-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 1999-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -80,6 +80,8 @@ #include #include +#include + #include // RMCONFIG: need definition of REGISTER_ALL_HALS() #include "g_hal_register.h" @@ -476,6 +478,8 @@ NV2080_CTRL_GPU_INFO_INDEX_DMABUF_CAPABILITY_YES); } + nv->coherent = pGpu->getProperty(pGpu, PDB_PROP_GPU_COHERENT_CPU_MAPPING); + portMemFree(pGpuInfoParams); // UNLOCK: release GPUs lock @@ -665,14 +669,14 @@ "NV fb using linear address : 0x%p\n", pGpu->registerAccess.gpuFbAddr); pGpu->setProperty(pGpu, PDB_PROP_GPU_ALTERNATE_TREE_ENABLED, NV_TRUE); - pGpu->setProperty(pGpu, PDB_PROP_GPU_ALTERNATE_TREE_HANDLE_LOCKLESS, NV_FALSE); + pGpu->setProperty(pGpu, PDB_PROP_GPU_ALTERNATE_TREE_HANDLE_LOCKLESS, NV_TRUE); if (osReadRegistryDword(pGpu, NV_REG_PROCESS_NONSTALL_INTR_IN_LOCKLESS_ISR, &data) == NV_OK) { - if (data == NV_REG_PROCESS_NONSTALL_INTR_IN_LOCKLESS_ISR_ENABLE) + if (data == NV_REG_PROCESS_NONSTALL_INTR_IN_LOCKLESS_ISR_DISABLE) { - pGpu->setProperty(pGpu, PDB_PROP_GPU_ALTERNATE_TREE_HANDLE_LOCKLESS, NV_TRUE); + pGpu->setProperty(pGpu, PDB_PROP_GPU_ALTERNATE_TREE_HANDLE_LOCKLESS, NV_FALSE); } } @@ -680,6 +684,12 @@ { pGpu->setProperty(pGpu, PDB_PROP_GPU_ALLOW_PAGE_RETIREMENT, NV_TRUE); } + else + { + { + pGpu->setProperty(pGpu, PDB_PROP_GPU_ALLOW_PAGE_RETIREMENT, NV_TRUE); + } + } if ((osReadRegistryDword(NULL, NV_REG_PRESERVE_VIDEO_MEMORY_ALLOCATIONS, @@ -766,6 +776,11 @@ if (os_is_vgx_hyper() || IS_VIRTUAL(pGpu)) return; + if (!gpuFuseSupportsDisplay_HAL(pGpu)) + { + return; + } + // // Check the OS layer for any video memory used by a console // driver that should be reserved. @@ -885,14 +900,12 @@ return; } - os_disable_console_access(); status->rmStatus = gpumgrStateInitGpu(pGpu); if (status->rmStatus != NV_OK) { NV_PRINTF(LEVEL_ERROR, "*** Cannot initialize the device\n"); RM_SET_ERROR(*status, RM_INIT_GPU_STATE_INIT_FAILED); - os_enable_console_access(); return; } nvp->flags |= NV_INIT_FLAG_GPU_STATE; @@ -922,13 +935,10 @@ NV_PRINTF(LEVEL_ERROR, "*** Cannot load state into the device\n"); RM_SET_ERROR(*status, RM_INIT_GPU_LOAD_FAILED); - os_enable_console_access(); return; } nvp->flags |= NV_INIT_FLAG_GPU_STATE_LOAD; - os_enable_console_access(); - status->rmStatus = gpuPerformUniversalValidation_HAL(pGpu); if (status->rmStatus != NV_OK) { @@ -937,6 +947,9 @@ return; } + // Setup GPU scalability + (void) RmInitScalability(pGpu); + return; } @@ -1142,6 +1155,7 @@ nv_priv_t *nvp; NvU32 gpuId; NvU32 pmc_boot_0 = 0; + NvU32 pmc_boot_1 = 0; NvU32 pmc_boot_42 = 0; NV_SET_NV_PRIV(pNv, NULL); @@ -1159,6 +1173,7 @@ } pmc_boot_0 = NV_PRIV_REG_RD32(pNv->regs->map_u, NV_PMC_BOOT_0); + pmc_boot_1 = NV_PRIV_REG_RD32(pNv->regs->map_u, NV_PMC_BOOT_1); pmc_boot_42 = NV_PRIV_REG_RD32(pNv->regs->map_u, NV_PMC_BOOT_42); os_unmap_kernel_space(pNv->regs->map_u, os_page_size); @@ -1198,6 +1213,7 @@ os_mem_set(nvp, 0, sizeof(*nvp)); nvp->status = NV_ERR_INVALID_STATE; nvp->pmc_boot_0 = pmc_boot_0; + nvp->pmc_boot_1 = pmc_boot_1; nvp->pmc_boot_42 = pmc_boot_42; NV_SET_NV_PRIV(pNv, nvp); @@ -1216,7 +1232,7 @@ nv_i2c_adapter_entry_t i2c_adapters[MAX_I2C_ADAPTERS]; nv_dynamic_power_t dynamicPowerCopy; NvU32 x = 0; - NvU32 pmc_boot_0, pmc_boot_42; + NvU32 pmc_boot_0, pmc_boot_1, pmc_boot_42; // // Do not clear private state after GPU resets, it is used while @@ -1234,6 +1250,7 @@ pRegistryCopy = nvp->pRegistry; dynamicPowerCopy = nvp->dynamic_power; pmc_boot_0 = nvp->pmc_boot_0; + pmc_boot_1 = nvp->pmc_boot_1; pmc_boot_42 = nvp->pmc_boot_42; for (x = 0; x < MAX_I2C_ADAPTERS; x++) @@ -1249,6 +1266,7 @@ nvp->pRegistry = pRegistryCopy; nvp->dynamic_power = dynamicPowerCopy; nvp->pmc_boot_0 = pmc_boot_0; + nvp->pmc_boot_1 = pmc_boot_1; nvp->pmc_boot_42 = pmc_boot_42; for (x = 0; x < MAX_I2C_ADAPTERS; x++) @@ -1367,7 +1385,8 @@ NV01_NULL_OBJECT, NV01_NULL_OBJECT, NV01_ROOT, - &nv->rmapi.hClient) != NV_OK) + &nv->rmapi.hClient, + sizeof(nv->rmapi.hClient)) != NV_OK) { goto fail; } @@ -1391,7 +1410,8 @@ nv->rmapi.hClient, &nv->rmapi.hDevice, NV01_DEVICE_0, - &deviceParams) != NV_OK) + &deviceParams, + sizeof(deviceParams)) != NV_OK) { goto fail; } @@ -1404,7 +1424,8 @@ nv->rmapi.hDevice, &nv->rmapi.hSubDevice, NV20_SUBDEVICE_0, - &subDeviceParams) != NV_OK) + &subDeviceParams, + sizeof(subDeviceParams)) != NV_OK) { goto fail; } @@ -1419,7 +1440,8 @@ nv->rmapi.hSubDevice, &nv->rmapi.hI2C, NV40_I2C, - NULL) != NV_OK) + NULL, + 0) != NV_OK) { nv->rmapi.hI2C = 0; } @@ -1435,7 +1457,8 @@ nv->rmapi.hDevice, &nv->rmapi.hDisp, NV04_DISPLAY_COMMON, - NULL) != NV_OK) + NULL, + 0) != NV_OK) { nv->rmapi.hDisp = 0; } @@ -1447,6 +1470,59 @@ return NV_FALSE; } +static NV_STATUS RmFetchGspRmImages +( + nv_state_t *nv, + GSP_FIRMWARE *pGspFw, + const void **gspFwHandle, + const void **gspFwLogHandle +) +{ + nv_firmware_chip_family_t chipFamily; + nv_priv_t *nvp = NV_GET_NV_PRIV(nv); + NvU32 gpuArch = (DRF_VAL(_PMC, _BOOT_42, _ARCHITECTURE, nvp->pmc_boot_42) << + GPU_ARCH_SHIFT); + NvU32 gpuImpl = DRF_VAL(_PMC, _BOOT_42, _IMPLEMENTATION, nvp->pmc_boot_42); + + chipFamily = nv_firmware_get_chip_family(gpuArch, gpuImpl); + + portMemSet(pGspFw, 0, sizeof(*pGspFw)); + + *gspFwHandle = nv_get_firmware(nv, NV_FIRMWARE_TYPE_GSP, + chipFamily, + &pGspFw->pBuf, + &pGspFw->size); + if (*gspFwHandle == NULL && + !nv->allow_fallback_to_monolithic_rm) + { + NV_PRINTF(LEVEL_ERROR, "No firmware image found\n"); + return NV_ERR_NOT_SUPPORTED; + } + else if (*gspFwHandle != NULL) + { +#if LIBOS_LOG_DECODE_ENABLE + if (nv->enable_firmware_logs) + { + *gspFwLogHandle = nv_get_firmware(nv, NV_FIRMWARE_TYPE_GSP_LOG, + chipFamily, + &pGspFw->pLogElf, + &pGspFw->logElfSize); + if (*gspFwLogHandle == NULL) + { + NV_PRINTF(LEVEL_ERROR, "Failed to load gsp_log_*.bin, no GSP-RM logs will be printed (non-fatal)\n"); + } + } +#endif + nv->request_fw_client_rm = NV_TRUE; + } + else + { + nv->request_fw_client_rm = NV_FALSE; + } + + return NV_OK; +} + NvBool RmInitAdapter( nv_state_t *nv ) @@ -1461,6 +1537,7 @@ KernelDisplay *pKernelDisplay; const void *gspFwHandle = NULL; const void *gspFwLogHandle = NULL; + NvBool consoleDisabled = NV_FALSE; GSP_FIRMWARE gspFw = {0}; PORT_UNREFERENCED_VARIABLE(gspFw); @@ -1510,46 +1587,14 @@ // if (nv->request_firmware) { - NvU32 gpuArch = (DRF_VAL(_PMC, _BOOT_42, _ARCHITECTURE, nvp->pmc_boot_42) << - GPU_ARCH_SHIFT); - NvU32 gpuImpl = DRF_VAL(_PMC, _BOOT_42, _IMPLEMENTATION, nvp->pmc_boot_42); - - nv_firmware_chip_family_t chipFamily = nv_firmware_get_chip_family(gpuArch, gpuImpl); - nv_set_dma_address_size(nv, NV_GSP_GPU_MIN_SUPPORTED_DMA_ADDR_WIDTH); - gspFwHandle = nv_get_firmware(nv, NV_FIRMWARE_TYPE_GSP, - chipFamily, - &gspFw.pBuf, - &gspFw.size); - if (gspFwHandle == NULL && - !nv->allow_fallback_to_monolithic_rm) + status.rmStatus = RmFetchGspRmImages(nv, &gspFw, &gspFwHandle, &gspFwLogHandle); + if (status.rmStatus != NV_OK) { RM_SET_ERROR(status, RM_INIT_FIRMWARE_FETCH_FAILED); goto shutdown; } - else if (gspFwHandle != NULL) - { -#if LIBOS_LOG_DECODE_ENABLE - if (nv->enable_firmware_logs) - { - gspFwLogHandle = nv_get_firmware(nv, NV_FIRMWARE_TYPE_GSP_LOG, - chipFamily, - &gspFw.pLogElf, - &gspFw.logElfSize); - if (gspFwLogHandle == NULL) - { - NV_PRINTF(LEVEL_ERROR, "Failed to load gsp_log_*.bin, no GSP-RM logs will be printed (non-fatal)\n"); - } - } -#endif - - nv->request_fw_client_rm = NV_TRUE; - } - else - { - nv->request_fw_client_rm = NV_FALSE; - } } // initialize the RM device register mapping @@ -1592,6 +1637,7 @@ if (status.rmStatus != NV_OK) { NV_PRINTF(LEVEL_ERROR, "FSP boot command failed.\n"); + RM_SET_ERROR(status, RM_INIT_FIRMWARE_INIT_FAILED); goto shutdown; } } @@ -1601,6 +1647,16 @@ RmInitAcpiMethods(pOS, pSys, pGpu); // + // For GPU driving console, disable console access here, to ensure no console + // writes through BAR1 can interfere with physical RM's setup of BAR1 + // + if (rm_get_uefi_console_status(nv)) + { + os_disable_console_access(); + consoleDisabled = NV_TRUE; + } + + // // If GSP fw RM support is enabled then start the GSP microcode // (including the task running the full instance of the RM) and // exchange the necessary initial RPC messages before continuing @@ -1647,6 +1703,17 @@ initNbsiTable(pGpu); } + // + // Load GSP proxy if early init is required. We need to do this + // before we trigger a full gpuStateInit and gpuStateLoad in + // RmInitNvDevice + // TODO: Check bug 200744430 + // + if (gpuIsCCFeatureEnabled(pGpu)) + { + confComputeEarlyInit(pGpu, GPU_GET_CONF_COMPUTE(pGpu)); + } + // finally, initialize the device RmInitNvDevice(devicereference, &status); if (! RM_INIT_SUCCESS(status.initStatus) ) @@ -1664,6 +1731,12 @@ goto shutdown; } + if (consoleDisabled) + { + os_enable_console_access(); + consoleDisabled = NV_FALSE; + } + // LOCK: acquire GPUs lock status.rmStatus = rmGpuLocksAcquire(GPUS_LOCK_FLAGS_NONE, RM_LOCK_MODULES_INIT); @@ -1696,6 +1769,14 @@ intrSetIntrEn(pIntr, INTERRUPT_TYPE_HARDWARE); } + // LOCK: acquire GPUs lock + status.rmStatus = rmGpuLocksAcquire(GPUS_LOCK_FLAGS_NONE, + RM_LOCK_MODULES_INIT); + if (status.rmStatus != NV_OK) + { + goto shutdown; + } + KernelRc *pKernelRc = GPU_GET_KERNEL_RC(pGpu); // initialize the watchdog (disabled by default) status.rmStatus = pKernelRc != NULL ? krcWatchdogInit_HAL(pGpu, pKernelRc) : @@ -1715,8 +1796,13 @@ RM_SET_ERROR(status, RM_INIT_WATCHDOG_FAILED); NV_PRINTF(LEVEL_ERROR, "krcWatchdogInit failed, bailing out of RmInitAdapter\n"); + // UNLOCK: release GPUs lock + rmGpuLocksRelease(GPUS_LOCK_FLAGS_NONE, NULL); goto shutdown; } + + // UNLOCK: release GPUs lock + rmGpuLocksRelease(GPUS_LOCK_FLAGS_NONE, NULL); nv_start_rc_timer(nv); nvp->status = NV_OK; @@ -1846,6 +1932,11 @@ shutdown: nv->flags &= ~NV_FLAG_IN_RECOVERY; + if (consoleDisabled) + { + os_enable_console_access(); + } + // call ShutdownAdapter to undo anything we've done above RmShutdownAdapter(nv); diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/arch/nvalloc/unix/src/osmemdesc.c nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/arch/nvalloc/unix/src/osmemdesc.c --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/arch/nvalloc/unix/src/osmemdesc.c 2023-10-25 20:20:30.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/arch/nvalloc/unix/src/osmemdesc.c 2024-03-05 22:12:49.000000000 +0000 @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 2012-2021 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2012-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -71,9 +71,11 @@ NV_STATUS rmStatus; void *pPrivate; + pClient = serverutilGetClientUnderLock(hClient); + if ((pDescriptor == NvP64_NULL) || (*pLimit == 0) || - (serverutilGetClientUnderLock(hClient, &pClient) != NV_OK)) + (pClient == NULL)) { return NV_ERR_INVALID_PARAM_STRUCT; } @@ -361,6 +363,23 @@ return NV_OK; } +static NvU64 +_doWarBug4040336 +( + OBJGPU *pGpu, + NvU64 addr +) +{ + if (gpuIsWarBug4040336Enabled(pGpu)) + { + if ((addr & 0xffffffff00000000ULL) == 0x7fff00000000ULL) + { + addr = addr & 0xffffffffULL; + } + } + return addr; +} + static NV_STATUS osCreateOsDescriptorFromIoMemory ( @@ -439,6 +458,14 @@ return rmStatus; } + // + // BF3's PCIe MMIO bus address at 0x800000000000(CPU PA 0x7fff00000000) is + // too high for Ampere to address. As a result, BF3's bus address is + // moved to < 4GB. Now, the CPU PA and the bus address are no longer 1:1 + // and needs to be adjusted. + // + *base = _doWarBug4040336(pGpu, *base); + rmStatus = memdescCreate(ppMemDesc, pGpu, (*pLimit + 1), 0, NV_MEMORY_CONTIGUOUS, ADDR_SYSMEM, NV_MEMORY_UNCACHED, MEMDESC_FLAGS_NONE); diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/arch/nvalloc/unix/src/osnvlink.c nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/arch/nvalloc/unix/src/osnvlink.c --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/arch/nvalloc/unix/src/osnvlink.c 2023-10-25 20:20:30.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/arch/nvalloc/unix/src/osnvlink.c 2024-03-05 22:12:49.000000000 +0000 @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 1015-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2015-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/arch/nvalloc/unix/src/osunix.c nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/arch/nvalloc/unix/src/osunix.c --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/arch/nvalloc/unix/src/osunix.c 2023-10-25 20:20:30.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/arch/nvalloc/unix/src/osunix.c 2024-03-05 22:12:49.000000000 +0000 @@ -66,13 +66,6 @@ pOS->osNv_cpuid = nv_cpuid; #endif - pOS->osCallACPI_DSM = osCallACPI_DSM; - pOS->osCallACPI_DDC = osCallACPI_DDC; - pOS->osCallACPI_NVHG_ROM = osCallACPI_NVHG_ROM; - pOS->osCallACPI_DOD = osCallACPI_DOD; - pOS->osCallACPI_MXDM = osCallACPI_MXDM; - pOS->osCallACPI_MXDS = osCallACPI_MXDS; - pOS->osDbgBreakpointEnabled = osDbgBreakpointEnabled; } diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/arch/nvalloc/unix/src/rm-gpu-ops.c nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/arch/nvalloc/unix/src/rm-gpu-ops.c --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/arch/nvalloc/unix/src/rm-gpu-ops.c 2023-10-25 20:20:30.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/arch/nvalloc/unix/src/rm-gpu-ops.c 2024-03-05 22:12:50.000000000 +0000 @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 2020-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2020-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -214,7 +214,7 @@ NV_STATUS NV_API_CALL rm_gpu_ops_pma_alloc_pages( nvidia_stack_t *sp, void *pPma, - NvLength pageCount, NvU32 pageSize, + NvLength pageCount, NvU64 pageSize, nvgpuPmaAllocationOptions_t pPmaAllocOptions, NvU64 *pPages) { @@ -229,7 +229,7 @@ NV_STATUS NV_API_CALL rm_gpu_ops_pma_pin_pages( nvidia_stack_t *sp, void *pPma, - NvU64 *pPages, NvLength pageCount, NvU32 pageSize, NvU32 flags) + NvU64 *pPages, NvLength pageCount, NvU64 pageSize, NvU32 flags) { NV_STATUS rmStatus; void *fp; @@ -241,7 +241,7 @@ NV_STATUS NV_API_CALL rm_gpu_ops_pma_unpin_pages( nvidia_stack_t *sp, void *pPma, - NvU64 *pPages, NvLength pageCount, NvU32 pageSize) + NvU64 *pPages, NvLength pageCount, NvU64 pageSize) { NV_STATUS rmStatus; void *fp; @@ -253,7 +253,7 @@ NV_STATUS NV_API_CALL rm_gpu_ops_memory_cpu_map( nvidia_stack_t *sp, gpuAddressSpaceHandle vaspace, - NvU64 gpuOffset, NvLength length, void **cpuPtr, NvU32 pageSize) + NvU64 gpuOffset, NvLength length, void **cpuPtr, NvU64 pageSize) { NV_STATUS rmStatus; void *fp; @@ -274,8 +274,31 @@ return NV_OK; } +NV_STATUS NV_API_CALL rm_gpu_ops_tsg_allocate(nvidia_stack_t *sp, + gpuAddressSpaceHandle vaspace, + const gpuTsgAllocParams *allocParams, + gpuTsgHandle *tsg) +{ + NV_STATUS rmStatus; + void *fp; + NV_ENTER_RM_RUNTIME(sp,fp); + rmStatus = nvGpuOpsTsgAllocate(vaspace, allocParams, tsg); + NV_EXIT_RM_RUNTIME(sp,fp); + return rmStatus; +} + +NV_STATUS NV_API_CALL rm_gpu_ops_tsg_destroy(nvidia_stack_t * sp, + nvgpuTsgHandle_t tsg) +{ + void *fp; + NV_ENTER_RM_RUNTIME(sp,fp); + nvGpuOpsTsgDestroy(tsg); + NV_EXIT_RM_RUNTIME(sp,fp); + return NV_OK; +} + NV_STATUS NV_API_CALL rm_gpu_ops_channel_allocate(nvidia_stack_t *sp, - gpuAddressSpaceHandle vaspace, + const gpuTsgHandle tsg, const gpuChannelAllocParams *allocParams, gpuChannelHandle *channel, gpuChannelInfo *channelInfo) @@ -283,7 +306,7 @@ NV_STATUS rmStatus; void *fp; NV_ENTER_RM_RUNTIME(sp,fp); - rmStatus = nvGpuOpsChannelAllocate(vaspace, allocParams, channel, + rmStatus = nvGpuOpsChannelAllocate(tsg, allocParams, channel, channelInfo); NV_EXIT_RM_RUNTIME(sp,fp); return rmStatus; @@ -300,7 +323,7 @@ } NV_STATUS NV_API_CALL rm_gpu_ops_pma_free_pages(nvidia_stack_t *sp, - void *pPma, NvU64 *pPages, NvLength pageCount, NvU32 pageSize, NvU32 flags) + void *pPma, NvU64 *pPages, NvLength pageCount, NvU64 pageSize, NvU32 flags) { void *fp; NV_ENTER_RM_RUNTIME(sp,fp); @@ -570,14 +593,26 @@ return rmStatus; } +NV_STATUS NV_API_CALL rm_gpu_ops_flush_replayable_fault_buffer(nvidia_stack_t *sp, + gpuDeviceHandle device) +{ + NV_STATUS rmStatus; + void *fp; + NV_ENTER_RM_RUNTIME(sp,fp); + rmStatus = nvGpuOpsFlushReplayableFaultBuffer(device); + NV_EXIT_RM_RUNTIME(sp,fp); + return rmStatus; +} + NV_STATUS NV_API_CALL rm_gpu_ops_init_access_cntr_info(nvidia_stack_t *sp, gpuDeviceHandle device, - gpuAccessCntrInfo *accessCntrInfo) + gpuAccessCntrInfo *accessCntrInfo, + NvU32 accessCntrIndex) { NV_STATUS rmStatus; void *fp; NV_ENTER_RM_RUNTIME(sp,fp); - rmStatus = nvGpuOpsInitAccessCntrInfo(device, accessCntrInfo); + rmStatus = nvGpuOpsInitAccessCntrInfo(device, accessCntrInfo, accessCntrIndex); NV_EXIT_RM_RUNTIME(sp,fp); return rmStatus; } @@ -811,3 +846,129 @@ return rmStatus; } +NV_STATUS NV_API_CALL rm_gpu_ops_ccsl_context_init(nvidia_stack_t *sp, + struct ccslContext_t **ctx, + gpuChannelHandle channel) +{ + NV_STATUS rmStatus; + void *fp; + NV_ENTER_RM_RUNTIME(sp,fp); + rmStatus = nvGpuOpsCcslContextInit(ctx, channel); + NV_EXIT_RM_RUNTIME(sp,fp); + return rmStatus; +} + +NV_STATUS NV_API_CALL rm_gpu_ops_ccsl_context_clear(nvidia_stack_t *sp, + struct ccslContext_t *ctx) +{ + NV_STATUS rmStatus; + void *fp; + NV_ENTER_RM_RUNTIME(sp,fp); + rmStatus = nvGpuOpsCcslContextClear(ctx); + NV_EXIT_RM_RUNTIME(sp,fp); + return rmStatus; +} + +NV_STATUS NV_API_CALL rm_gpu_ops_ccsl_rotate_iv(nvidia_stack_t *sp, + struct ccslContext_t *ctx, + NvU8 direction) +{ + NV_STATUS rmStatus; + void *fp; + NV_ENTER_RM_RUNTIME(sp,fp); + rmStatus = nvGpuOpsCcslRotateIv(ctx, direction); + NV_EXIT_RM_RUNTIME(sp,fp); + return rmStatus; +} + +NV_STATUS NV_API_CALL rm_gpu_ops_ccsl_encrypt_with_iv(nvidia_stack_t *sp, + struct ccslContext_t *ctx, + NvU32 bufferSize, + NvU8 const *inputBuffer, + NvU8 *encryptIv, + NvU8 *outputBuffer, + NvU8 *authTagData) +{ + NV_STATUS rmStatus; + void *fp; + NV_ENTER_RM_RUNTIME(sp,fp); + rmStatus = nvGpuOpsCcslEncryptWithIv(ctx, bufferSize, inputBuffer, encryptIv, outputBuffer, authTagData); + NV_EXIT_RM_RUNTIME(sp,fp); + return rmStatus; +} + +NV_STATUS NV_API_CALL rm_gpu_ops_ccsl_encrypt(nvidia_stack_t *sp, + struct ccslContext_t *ctx, + NvU32 bufferSize, + NvU8 const *inputBuffer, + NvU8 *outputBuffer, + NvU8 *authTagData) +{ + NV_STATUS rmStatus; + void *fp; + NV_ENTER_RM_RUNTIME(sp,fp); + rmStatus = nvGpuOpsCcslEncrypt(ctx, bufferSize, inputBuffer, outputBuffer, authTagData); + NV_EXIT_RM_RUNTIME(sp,fp); + return rmStatus; +} + +NV_STATUS NV_API_CALL rm_gpu_ops_ccsl_decrypt(nvidia_stack_t *sp, + struct ccslContext_t *ctx, + NvU32 bufferSize, + NvU8 const *inputBuffer, + NvU8 const *decryptIv, + NvU8 *outputBuffer, + NvU8 const *addAuthData, + NvU32 addAuthDataSize, + NvU8 const *authTagData) +{ + NV_STATUS rmStatus; + void *fp; + NV_ENTER_RM_RUNTIME(sp,fp); + rmStatus = nvGpuOpsCcslDecrypt(ctx, bufferSize, inputBuffer, decryptIv, outputBuffer, + addAuthData, addAuthDataSize, authTagData); + NV_EXIT_RM_RUNTIME(sp,fp); + return rmStatus; +} + +NV_STATUS NV_API_CALL rm_gpu_ops_ccsl_sign(nvidia_stack_t *sp, + struct ccslContext_t *ctx, + NvU32 bufferSize, + NvU8 const *inputBuffer, + NvU8 *authTagData) + +{ + NV_STATUS rmStatus; + void *fp; + NV_ENTER_RM_RUNTIME(sp,fp); + rmStatus = nvGpuOpsCcslSign(ctx, bufferSize, inputBuffer, authTagData); + NV_EXIT_RM_RUNTIME(sp,fp); + return rmStatus; +} + +NV_STATUS NV_API_CALL rm_gpu_ops_ccsl_query_message_pool(nvidia_stack_t *sp, + struct ccslContext_t *ctx, + NvU8 direction, + NvU64 *messageNum) +{ + NV_STATUS rmStatus; + void *fp; + NV_ENTER_RM_RUNTIME(sp,fp); + rmStatus = nvGpuOpsQueryMessagePool(ctx, direction, messageNum); + NV_EXIT_RM_RUNTIME(sp,fp); + return rmStatus; +} + +NV_STATUS NV_API_CALL rm_gpu_ops_ccsl_increment_iv(nvidia_stack_t *sp, + struct ccslContext_t *ctx, + NvU8 direction, + NvU64 increment, + NvU8 *iv) +{ + NV_STATUS rmStatus; + void *fp; + NV_ENTER_RM_RUNTIME(sp,fp); + rmStatus = nvGpuOpsIncrementIv(ctx, direction, increment, iv); + NV_EXIT_RM_RUNTIME(sp,fp); + return rmStatus; +} diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/arch/nvalloc/unix/src/rmobjexportimport.c nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/arch/nvalloc/unix/src/rmobjexportimport.c --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/arch/nvalloc/unix/src/rmobjexportimport.c 2023-10-25 20:20:30.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/arch/nvalloc/unix/src/rmobjexportimport.c 2024-03-05 22:12:50.000000000 +0000 @@ -262,7 +262,8 @@ NV01_NULL_OBJECT, NV01_NULL_OBJECT, NV01_ROOT, - &hObjExportRmClient); + &hObjExportRmClient, + sizeof(hObjExportRmClient)); if (rmStatus != NV_OK) { NV_PRINTF(LEVEL_ERROR, "Unable to alloc root in %s\n", __FUNCTION__); @@ -426,7 +427,8 @@ hObjExportRmClient, objExportDevice[deviceInstance].hRmDevice, NV01_DEVICE_0, - ¶ms); + ¶ms, + sizeof(params)); if (status != NV_OK) { NV_PRINTF(LEVEL_ERROR, "Unable to alloc device in %s\n", @@ -443,7 +445,8 @@ objExportDevice[deviceInstance].hRmDevice, objExportDevice[deviceInstance].hRmSubDevice, NV20_SUBDEVICE_0, - &subdevParams); + &subdevParams, + sizeof(subdevParams)); if (status != NV_OK) { NV_PRINTF(LEVEL_ERROR, "Unable to alloc subdevice in %s\n", diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/arch/nvalloc/unix/src/unix_console.c nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/arch/nvalloc/unix/src/unix_console.c --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/arch/nvalloc/unix/src/unix_console.c 2023-10-25 20:20:31.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/arch/nvalloc/unix/src/unix_console.c 2024-03-05 22:12:50.000000000 +0000 @@ -30,6 +30,291 @@ #include #include +#include +#include "vgpu/vgpu_events.h" + +static NV_STATUS +unixCallVideoBIOS +( + OBJGPU *pGpu, + NvU32 *eax, + NvU32 *ebx +) +{ + NV_STATUS status = NV_ERR_NOT_SUPPORTED; + + if (NVCPU_IS_X86_64) + { + NvU32 eax_in = *eax; + NvU32 ebx_in = *ebx; + + if (pGpu->getProperty(pGpu, PDB_PROP_GPU_IS_UEFI)) + { + return NV_ERR_NOT_SUPPORTED; + } + + NV_PRINTF(LEVEL_INFO, "unixCallVideoBIOS: 0x%x 0x%x, vga_satus = %d\n", *eax, *ebx, NV_PRIMARY_VGA(NV_GET_NV_STATE(pGpu))); + + status = nv_vbios_call(pGpu, eax, ebx); + + // this was originally changed for nt in changelist 644223 + if (*eax != 0x4f) + { + NV_PRINTF(LEVEL_ERROR, + "int10h(%04x, %04x) vesa call failed! (%04x, %04x)\n", + eax_in, ebx_in, *eax, *ebx); + status = NV_ERR_GENERIC; + } + } + + return status; +} + +static void +RmSaveDisplayState +( + OBJGPU *pGpu +) +{ + nv_state_t *nv = NV_GET_NV_STATE(pGpu); + nv_priv_t *nvp = NV_GET_NV_PRIV(nv); + RM_API *pRmApi = rmapiGetInterface(RMAPI_GPU_LOCK_INTERNAL); + KernelDisplay *pKernelDisplay = GPU_GET_KERNEL_DISPLAY(pGpu); + NvBool use_vbios = NV_PRIMARY_VGA(nv) && RmGpuHasIOSpaceEnabled(nv); + NvU32 eax, ebx; + NV_STATUS status; + NV2080_CTRL_CMD_INTERNAL_DISPLAY_UNIX_CONSOLE_PARAMS unixConsoleParams = {0}; + + + if (IS_VIRTUAL(pGpu) || pKernelDisplay == NULL) + { + return; + } + + os_disable_console_access(); + + if (pGpu->getProperty(pGpu, PDB_PROP_GPU_IS_UEFI)) + { + NV_PRINTF(LEVEL_INFO, "RM fallback doesn't support saving of efifb console\n"); + goto done; + } + + unixConsoleParams.bSaveOrRestore = NV_TRUE; + unixConsoleParams.bUseVbios = use_vbios; + + NV_CHECK_OK_OR_GOTO(status, LEVEL_ERROR,pRmApi->Control(pRmApi, nv->rmapi.hClient, nv->rmapi.hSubDevice, + NV2080_CTRL_CMD_INTERNAL_DISPLAY_UNIX_CONSOLE, + &unixConsoleParams, sizeof(unixConsoleParams)), done); + + if (use_vbios) + { + // + // Attempt to identify the currently set VESA mode; assume + // vanilla VGA text if the VBIOS call fails. + // + eax = 0x4f03; + ebx = 0; + if (NV_OK == unixCallVideoBIOS(pGpu, &eax, &ebx)) + { + nvp->vga.vesaMode = (ebx & 0x3fff); + } + else + { + nvp->vga.vesaMode = 3; + } + } + +done: + os_enable_console_access(); +} + +static void RmRestoreDisplayState +( + OBJGPU *pGpu +) +{ + nv_state_t *nv = NV_GET_NV_STATE(pGpu); + nv_priv_t *nvp = NV_GET_NV_PRIV(nv); + RM_API *pRmApi = rmapiGetInterface(RMAPI_GPU_LOCK_INTERNAL); + NvBool use_vbios = NV_PRIMARY_VGA(nv) && RmGpuHasIOSpaceEnabled(nv);; + KernelDisplay *pKernelDisplay = GPU_GET_KERNEL_DISPLAY(pGpu); + NV_STATUS status; + NvU32 eax, ebx; + NV2080_CTRL_CMD_INTERNAL_DISPLAY_UNIX_CONSOLE_PARAMS unixConsoleParams = {0}; + NV2080_CTRL_CMD_INTERNAL_DISPLAY_POST_RESTORE_PARAMS restoreParams = {0}; + + NV_ASSERT_OR_RETURN_VOID(pKernelDisplay != NULL); + + // + // vGPU: + // + // Since vGPU does all real hardware management in the + // host, there is nothing to do at this point in the + // guest OS (where IS_VIRTUAL(pGpu) is true). + // + if (IS_VIRTUAL(pGpu)) + { + // we don't have VGA state that's needing to be restored. + NV_PRINTF(LEVEL_INFO, "skipping RestoreDisplayState on VGPU (0x%x)\n", + pGpu->gpuId); + return; + } + + os_disable_console_access(); + + // + // Fix up DCB index VBIOS scratch registers. + // The strategies employed are: + // + // SBIOS/VBIOS: + // Clear the DCB index, and set the previous DCB index to the original + // value. This allows the VBIOS (during the int10h mode-set) to + // determine which display to enable, and to set the head-enabled bit + // as needed (see bugs #264873 and #944398). + // + if (pGpu->getProperty(pGpu, PDB_PROP_GPU_IS_UEFI)) + { + NV_PRINTF(LEVEL_INFO, "RM fallback doesn't support efifb console restore\n"); + goto done; + } + + unixConsoleParams.bUseVbios = use_vbios; + unixConsoleParams.bSaveOrRestore = NV_FALSE; + + NV_CHECK_OK_OR_GOTO(status, LEVEL_ERROR, pRmApi->Control(pRmApi, nv->rmapi.hClient, + nv->rmapi.hSubDevice, + NV2080_CTRL_CMD_INTERNAL_DISPLAY_UNIX_CONSOLE, + &unixConsoleParams, sizeof(unixConsoleParams)), done); + + eax = 0x4f02; + ebx = nvp->vga.vesaMode; + + if (NV_OK == unixCallVideoBIOS(pGpu, &eax, &ebx)) + { + restoreParams.bWriteCr = NV_TRUE; + } + + NV_CHECK_OK_OR_GOTO(status, LEVEL_ERROR, pRmApi->Control(pRmApi, nv->rmapi.hClient, + nv->rmapi.hSubDevice, + NV2080_CTRL_CMD_INTERNAL_DISPLAY_POST_RESTORE, + &restoreParams, sizeof(restoreParams)), done); + +done: + if (pGpu->getProperty(pGpu, PDB_PROP_GPU_IS_UEFI)) + { + } + os_enable_console_access(); +} + +static void +RmChangeResMode +( + OBJGPU *pGpu, + NvBool hires +) +{ + if (hires) + { + SLI_LOOP_START(SLI_LOOP_FLAGS_NONE) + + RmSaveDisplayState(pGpu); + + SLI_LOOP_END + } + else + { + SLI_LOOP_START(SLI_LOOP_FLAGS_NONE) + + RmRestoreDisplayState(pGpu); + // + // vGPU: + // + // Since vGPU does all real hardware management in the host, if we + // are in guest OS (where IS_VIRTUAL(pGpu) is true), do an RPC to + // the host to trigger switch from HIRES to (LORES)VGA. + // + if (IS_VIRTUAL(pGpu)) + { + NV_STATUS status = NV_OK; + NV_RM_RPC_SWITCH_TO_VGA(pGpu, status); + } + + SLI_LOOP_END + } +} + +NV_STATUS NV_API_CALL +rm_save_low_res_mode +( + nvidia_stack_t *sp, + nv_state_t *pNv +) +{ + THREAD_STATE_NODE threadState; + OBJGPU *pGpu = NV_GET_NV_PRIV_PGPU(pNv); + void *fp; + + NV_ENTER_RM_RUNTIME(sp,fp); + threadStateInit(&threadState, THREAD_STATE_FLAGS_NONE); + + RmSaveDisplayState(pGpu); + + threadStateFree(&threadState, THREAD_STATE_FLAGS_NONE); + NV_EXIT_RM_RUNTIME(sp,fp); + + return NV_OK; +} + +NV_STATUS +deviceCtrlCmdOsUnixVTSwitch_IMPL +( + Device *pDevice, + NV0080_CTRL_OS_UNIX_VT_SWITCH_PARAMS *pParams +) +{ + OBJGPU *pGpu = GPU_RES_GET_GPU(pDevice); + nv_state_t *nv = NV_GET_NV_STATE(pGpu); + NvBool hires; + NvBool bChangeResMode = NV_TRUE; + + switch (pParams->cmd) + { + case NV0080_CTRL_OS_UNIX_VT_SWITCH_CMD_SAVE_VT_STATE: + hires = NV_TRUE; + break; + + case NV0080_CTRL_OS_UNIX_VT_SWITCH_CMD_RESTORE_VT_STATE: + hires = NV_FALSE; + break; + + case NV0080_CTRL_OS_UNIX_VT_SWITCH_CMD_CONSOLE_RESTORED: + bChangeResMode = NV_FALSE; + break; + + default: + return NV_ERR_INVALID_ARGUMENT; + } + + RmUpdateGc6ConsoleRefCount(nv, + pParams->cmd != NV0080_CTRL_OS_UNIX_VT_SWITCH_CMD_SAVE_VT_STATE); + + if (!bChangeResMode) + { + return NV_OK; + } + + if (rmGpuLocksAcquire(GPUS_LOCK_FLAGS_NONE, RM_LOCK_MODULES_FB) == NV_OK) + { + RmChangeResMode(pGpu, hires); + rmGpuLocksRelease(GPUS_LOCK_FLAGS_NONE, NULL); + } + else + { + NV_PRINTF(LEVEL_INFO,"%s: Failed to acquire GPU lock", __FUNCTION__); + } + return NV_OK; +} + NV_STATUS deviceCtrlCmdOsUnixVTGetFBInfo_IMPL ( Device *pDevice, @@ -51,7 +336,7 @@ if ((memmgrGetReservedConsoleMemDesc(pGpu, pMemoryManager) != NULL) && bContinue) { - NvU64 baseAddr; + NvU64 baseAddr, size; // There should only be one. NV_ASSERT(pParams->width == 0); @@ -59,11 +344,9 @@ pParams->subDeviceInstance = gpumgrGetSubDeviceInstanceFromGpu(pGpu); // Console is either mapped to BAR1 or BAR2 + 16 MB - os_get_screen_info(&baseAddr, &pParams->width, + nv_get_screen_info(nv, &baseAddr, &pParams->width, &pParams->height, &pParams->depth, - &pParams->pitch, - nv->bars[NV_GPU_BAR_INDEX_FB].cpu_address, - nv->bars[NV_GPU_BAR_INDEX_IMEM].cpu_address + 0x1000000); + &pParams->pitch, &size); if (baseAddr != 0) { diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/arch/nvalloc/unix/src/unix_intr.c nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/arch/nvalloc/unix/src/unix_intr.c --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/arch/nvalloc/unix/src/unix_intr.c 2023-10-25 20:20:31.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/arch/nvalloc/unix/src/unix_intr.c 2024-03-05 22:12:50.000000000 +0000 @@ -174,6 +174,18 @@ } } + if (IS_VGPU_GSP_PLUGIN_OFFLOAD_ENABLED(pGpu) && + !IS_VIRTUAL(pGpu) && bitVectorTest(&intr0Pending, MC_ENGINE_IDX_TMR)) + { + // We have to clear the top level interrupt bit here since otherwise + // the bottom half will attempt to service the interrupt on the CPU + // side before GSP receives the notification and services it + intrClearLeafVector_HAL(pGpu, pIntr, MC_ENGINE_IDX_TMR, &threadState); + bitVectorClr(&intr0Pending, MC_ENGINE_IDX_TMR); + + NV_ASSERT_OK(intrTriggerPrivDoorbell_HAL(pGpu, pIntr, NV_DOORBELL_NOTIFY_LEAF_SERVICE_TMR_HANDLE)); + } + if (pGpu->getProperty(pGpu, PDB_PROP_GPU_ALTERNATE_TREE_ENABLED) && !pGpu->getProperty(pGpu, PDB_PROP_GPU_ALTERNATE_TREE_HANDLE_LOCKLESS)) { @@ -303,9 +315,6 @@ */ NvBool osLockShouldToggleInterrupts(OBJGPU *pGpu) { - if (pGpu->getProperty(pGpu, PDB_PROP_GPU_TEGRA_SOC_NVDISPLAY)) - return NV_TRUE; - return (!pGpu->getProperty(pGpu, PDB_PROP_GPU_IN_PM_CODEPATH) && gpuIsStateLoaded(pGpu) && !pGpu->getProperty(pGpu, PDB_PROP_GPU_IN_SLI_LINK_CODEPATH)); @@ -591,10 +600,10 @@ goto done; } - // Non-replayable faults are copied to the client shadow buffer by GSP-RM. if (IS_GSP_CLIENT(pGpu)) { - status = NV_ERR_NOT_SUPPORTED; + // Non-replayable faults are copied to the client shadow buffer by GSP-RM. + status = NV_OK; goto done; } @@ -614,11 +623,6 @@ THREAD_STATE_NODE *pThreadState ) { - // Non-replayable faults are copied to the client shadow buffer by GSP-RM. - if (IS_GSP_CLIENT(pGpu)) - { - return NV_ERR_NOT_SUPPORTED; - } return NV_OK; } @@ -667,7 +671,7 @@ { // We have to clear the top level interrupt bit here since otherwise // the bottom half will attempt to service the interrupt on the CPU - // side before GSP recieves the notification and services it + // side before GSP receives the notification and services it kgmmuClearNonReplayableFaultIntr_HAL(pGpu, pKernelGmmu, &threadState); status = intrTriggerPrivDoorbell_HAL(pGpu, pIntr, NV_DOORBELL_NOTIFY_LEAF_SERVICE_NON_REPLAYABLE_FAULT_HANDLE); @@ -682,7 +686,15 @@ } else { - status = _rm_gpu_copy_mmu_faults_unlocked(pGpu, faultsCopied, &threadState); + if (IS_GSP_CLIENT(pGpu)) + { + // Non-replayable faults are copied to the client shadow buffer by GSP-RM. + status = NV_OK; + } + else + { + status = _rm_gpu_copy_mmu_faults_unlocked(pGpu, faultsCopied, &threadState); + } } threadStateFreeISRLockless(&threadState, pGpu, THREAD_STATE_FLAGS_IS_ISR_LOCKLESS); @@ -694,3 +706,27 @@ return status; } +NvBool NV_API_CALL rm_is_msix_allowed( + nvidia_stack_t *sp, + nv_state_t *nv +) +{ + nv_priv_t *pNvp = NV_GET_NV_PRIV(nv); + THREAD_STATE_NODE threadState; + void *fp; + NvBool ret = NV_FALSE; + + NV_ENTER_RM_RUNTIME(sp,fp); + threadStateInit(&threadState, THREAD_STATE_FLAGS_NONE); + + if (rmapiLockAcquire(API_LOCK_FLAGS_NONE, RM_LOCK_MODULES_INIT) == NV_OK) + { + ret = gpumgrIsDeviceMsixAllowed(nv->regs->cpu_address, + pNvp->pmc_boot_1, pNvp->pmc_boot_42); + rmapiLockRelease(); + } + + threadStateFree(&threadState, THREAD_STATE_FLAGS_NONE); + NV_EXIT_RM_RUNTIME(sp,fp); + return ret; +} diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/arch/nvalloc/unix/src/vbioscall.c nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/arch/nvalloc/unix/src/vbioscall.c --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/arch/nvalloc/unix/src/vbioscall.c 1970-01-01 00:00:00.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/arch/nvalloc/unix/src/vbioscall.c 2024-03-05 22:12:50.000000000 +0000 @@ -0,0 +1,457 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 1999-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + + +/****************************************************************************** +* +* Description: +* This file provides the glue layer between the RM's OS object +* unixCallVideoBIOS() method and the x86 real mode emulator +* +******************************************************************************/ + + +#include +#include +#include +#include + +#include + +#include + +#define IO_LOG(port, val) + +#define NV_ROMLEY_VGA_PHYS_ADDR 0x9d000 +#define NV_VGA_PHYS_ADDR 0xa0000 +#define NV_VIDEO_ROM_PHYS_ADDR 0xc0000 +#define NV_EXPANSION_VIDEO_ROM_PHYS_ADDR 0xc8000 +#define NV_SYSTEM_ROM_PHYS_ADDR 0xf0000 + +#define X86EMU_LOWMEM 0x600 // Interrupt vectors, BIOS data size +#define X86EMU_STACK_ADDR 0x10000 +#define X86EMU_STACK_SIZE 0x1000 +#define X86EMU_BUF_ADDR 0x20000 // EDID buffer for VESA int10 0x4f15 +#define X86EMU_BUF_SIZE 128 + +#define OP_HLT 0xf4 // HLT instruction - causes the emulator to return + +// This is where IRET from int10 will take us +#define X86EMU_IRET_SEG (X86EMU_STACK_ADDR >> 4) +#define X86EMU_IRET_OFF 0 + +#define X86EMU_DFLT_FLAGS (F_IF) + +static NvBool x86emuReady; +static void *x86emuStack; + +static struct x86emu_mem_seg { + NvU32 start; + NvU32 end; + void *vaddr; +} x86emu_mem_map[] = { + {NV_ROMLEY_VGA_PHYS_ADDR, NV_VGA_PHYS_ADDR - 1}, + {NV_VGA_PHYS_ADDR, NV_VIDEO_ROM_PHYS_ADDR - 1}, // vga + {NV_VIDEO_ROM_PHYS_ADDR, NV_EXPANSION_VIDEO_ROM_PHYS_ADDR -1}, // vbios, sbios + {NV_EXPANSION_VIDEO_ROM_PHYS_ADDR, NV_SYSTEM_ROM_PHYS_ADDR -1}, // vbios, sbios + {NV_SYSTEM_ROM_PHYS_ADDR, 0xFFFFF}, // Motherboard BIOS + {X86EMU_STACK_ADDR, X86EMU_STACK_ADDR + X86EMU_STACK_SIZE - 1}, // emulator stack + {0, X86EMU_LOWMEM - 1}, // Interrupt vectors, BIOS data + {X86EMU_BUF_ADDR, X86EMU_BUF_ADDR + X86EMU_BUF_SIZE - 1}, +}; + +enum { + X86EMU_SEG_ROMLEY_VGA = 0, + X86EMU_SEG_VGA, + X86EMU_SEG_ROM, + X86EMU_SEG_ROM_EXPANSION, + X86EMU_SEG_ROM_MOTHERBOARD_BIOS, + X86EMU_SEG_EMULATOR_STACK, + X86EMU_SEG_BIOS_DATA, + X86EMU_SEG_EDID_BUFFER, + X86EMU_NUM_SEGS +}; + +ct_assert(X86EMU_NUM_SEGS == NV_ARRAY_ELEMENTS(x86emu_mem_map)); + +static NvU8 +x_inb(NvU16 port) +{ + NvU8 val; + + val = os_io_read_byte(port); + IO_LOG(port, val); + return val; +} + +static void +x_outb(NvU16 port, NvU8 val) +{ + IO_LOG(port, val); + os_io_write_byte(port, val); +} + +static NvU16 +x_inw(NvU16 port) +{ + NvU16 val; + + val = os_io_read_word(port); + IO_LOG(port, val); + return val; +} + +static void +x_outw(NvU16 port, NvU16 val) +{ + IO_LOG(port, val); + os_io_write_word(port, val); +} + +static u32 +x_inl(X86EMU_pioAddr port) +{ + NvU32 val; + + val = os_io_read_dword(port); + IO_LOG(port, val); + return val; +} + +static void +x_outl(X86EMU_pioAddr port, u32 val) +{ + IO_LOG(port, val); + os_io_write_dword(port, val); +} + +static void * +Mem_addr_xlat(NvU32 addr, NvU32 sz) +{ + int i; + struct x86emu_mem_seg *pseg; + + for (i = 0; i < X86EMU_NUM_SEGS; ++i) + { + pseg = x86emu_mem_map + i; + if (pseg->vaddr != 0 && addr >= pseg->start && addr + sz - 1 <= pseg->end) + return (void *)((char *)pseg->vaddr + addr - pseg->start); + } + + X86EMU_halt_sys(); + + return 0; +} + +static NvU8 +Mem_rb(u32 addr) +{ + NvU8 *va = Mem_addr_xlat(addr, 1); + + return va != 0 ? *va : 0; +} + +static NvU16 +Mem_rw(u32 addr) +{ + NvU16 *va = Mem_addr_xlat(addr, 2); + + return va != 0 ? *va : 0; +} + +static u32 +Mem_rl(u32 addr) +{ + NvU32 *va = Mem_addr_xlat(addr, 4); + + return va != 0 ? *va : 0; +} + +static void +Mem_wb(u32 addr, NvU8 val) +{ + NvU8 *va = Mem_addr_xlat(addr, 1); + + if (va != 0) + *va = val; +} + +static void +Mem_ww(u32 addr, NvU16 val) +{ + NvU16 *va = Mem_addr_xlat(addr, 2); + + if (va != 0) + *va = val; +} + +static void +Mem_wl(u32 addr, u32 val) +{ + NvU32 *va = Mem_addr_xlat(addr, 4); + + if (va != 0) + *va = val; +} + +static NvU16 +get_int_seg(int i) +{ + return Mem_rw(i * 4 + 2); +} + + +static NvU16 +get_int_off(int i) +{ + return Mem_rw(i * 4); +} + + +static void +pushw(NvU16 i) +{ + M.x86.R_ESP -= 2; + Mem_ww((M.x86.R_SS << 4) + M.x86.R_ESP, i); +} + +static void +x86emu_do_int(int num) +{ +#if 0 + Int10Current->num = num; + + if (!int_handler(Int10Current)) { + X86EMU_halt_sys(); + } +#else + if ((num == 0x15) && (M.x86.R_AX == 0x5f80)) + { + // + // Handle the MXM_SYS_INFO_CALLBACK_NUM int 15h SBIOS + // callback: disclaim support by returning a value + // other than 005fh (MXM_SYS_INFO_CALLBACK_FUNC_SUPPORTED) + // to the caller. + // + M.x86.R_AX = 0; + } + else + { + NV_PRINTF(LEVEL_ERROR, "x86emu: int $%d (eax = %08x)\n", + num, M.x86.R_EAX); + DBG_BREAKPOINT(); + X86EMU_halt_sys(); + } +#endif +} + +NV_STATUS +RmInitX86EmuState(OBJGPU *pGpu) { + int i; + struct x86emu_mem_seg *pseg; + X86EMU_intrFuncs *intFuncs; + X86EMU_pioFuncs pioFuncs = { + (&x_inb), + (&x_inw), + (&x_inl), + (&x_outb), + (&x_outw), + (&x_outl) + }; + + X86EMU_memFuncs memFuncs = { + (&Mem_rb), + (&Mem_rw), + (&Mem_rl), + (&Mem_wb), + (&Mem_ww), + (&Mem_wl) + }; + + if (!NV_PRIMARY_VGA(NV_GET_NV_STATE(pGpu))) // not the primary GPU + return NV_OK; + + NV_ASSERT(!x86emuReady); + + x86emuStack = portMemAllocNonPaged( + X86EMU_STACK_SIZE + sizeof(X86EMU_intrFuncs*) * 256); + if (x86emuStack == NULL) + return NV_ERR_NO_MEMORY; + + // Interrupt dispatch table + intFuncs = (void *)((NvU8 *)x86emuStack + X86EMU_STACK_SIZE); + + // Fill virtual addresses in the memory map + for (i = 0; i < X86EMU_NUM_SEGS; ++i) + { + pseg = x86emu_mem_map + i; + switch (i) + { + case X86EMU_SEG_ROM: + case X86EMU_SEG_ROM_EXPANSION: + case X86EMU_SEG_ROM_MOTHERBOARD_BIOS: + nv_get_updated_emu_seg(&pseg->start, &pseg->end); + /* fallthrough */ + case X86EMU_SEG_VGA: + case X86EMU_SEG_BIOS_DATA: + pseg->vaddr = os_map_kernel_space(pseg->start, + pseg->end - pseg->start + 1, + NV_MEMORY_CACHED); + if (pseg->vaddr == 0) + { + NV_PRINTF(LEVEL_ERROR, "x86emu can't map phys addr 0x%05x\n", + pseg->start); + return NV_ERR_GENERIC; + } + break; + case X86EMU_SEG_EMULATOR_STACK: + pseg->vaddr = x86emuStack; + break; + default: + pseg->vaddr = 0; + break; + } + } + X86EMU_setupMemFuncs(&memFuncs); + + M.mem_base = 0; + M.mem_size = 1024*1024; + X86EMU_setupPioFuncs(&pioFuncs); + + for (i=0;i<256;i++) + intFuncs[i] = x86emu_do_int; + X86EMU_setupIntrFuncs(intFuncs); + + x86emuReady = NV_TRUE; + + return NV_OK; +} + +void +RmFreeX86EmuState(OBJGPU *pGpu) +{ + int i; + struct x86emu_mem_seg *pseg; + + if (! x86emuReady || !NV_PRIMARY_VGA(NV_GET_NV_STATE(pGpu))) // not the primary GPU + return; + + portMemFree(x86emuStack); + x86emuStack = 0; + + for (i = 0; i < X86EMU_NUM_SEGS; ++i) + { + pseg = x86emu_mem_map + i; + switch (i) + { + case X86EMU_SEG_ROMLEY_VGA: + case X86EMU_SEG_VGA: + case X86EMU_SEG_ROM: + case X86EMU_SEG_ROM_EXPANSION: + case X86EMU_SEG_ROM_MOTHERBOARD_BIOS: + case X86EMU_SEG_BIOS_DATA: + if (pseg->vaddr != 0) + os_unmap_kernel_space(pseg->vaddr, pseg->end - pseg->start + 1); + } + pseg->vaddr = 0; + } + + x86emuReady = NV_FALSE; +} + +NV_STATUS +nv_vbios_call( + OBJGPU *pGpu, + NvU32 *eax, + NvU32 *ebx) +{ + NvU16 seg; + NvU16 off; + struct x86emu_mem_seg *pseg; + + if (!NV_PRIMARY_VGA(NV_GET_NV_STATE(pGpu))) + return NV_ERR_GENERIC; + + seg = get_int_seg(0x10); + off = get_int_off(0x10); + + pseg = &x86emu_mem_map[X86EMU_SEG_VGA]; + if (seg < (pseg->start >> 4)) + { + pseg = &x86emu_mem_map[X86EMU_SEG_ROMLEY_VGA]; + if (seg < (pseg->start >> 4)) + { + NV_PRINTF(LEVEL_ERROR, + "cannot call the VBIOS. INT10 vector not in ROM: %04x:%04x\n", + seg, off); + return NV_ERR_GENERIC; + } + else if (pseg->vaddr == NULL) + { + pseg->vaddr = os_map_kernel_space(pseg->start, + (pseg->end - pseg->start + 1), + NV_MEMORY_CACHED); + if (pseg->vaddr == NULL) + { + NV_PRINTF(LEVEL_ERROR, "x86emu can't map phys addr 0x%05x\n", + pseg->start); + return NV_ERR_GENERIC; + } + } + } + + // Reset the CPU + portMemSet(&M, 0, sizeof(M)); + + M.x86.R_SS = X86EMU_STACK_ADDR >> 4; + M.x86.R_ESP = X86EMU_STACK_SIZE; + M.x86.R_CS = seg; + M.x86.R_EIP = off; + M.x86.R_EFLG = X86EMU_DFLT_FLAGS; + M.x86.R_EAX = *eax; + M.x86.R_EBX = *ebx; + M.x86.R_ECX = 0; + M.x86.R_EDX = 0; + M.x86.R_ES = X86EMU_BUF_ADDR >> 4; + + X86EMU_trace_on(); + + // Map ES:EDI to buffer. Used by vesa intr 4f15 - read EDID + pseg = &x86emu_mem_map[X86EMU_SEG_EDID_BUFFER]; + pseg->vaddr = NULL; + + // Prepare the code for IRET to jump to + Mem_wb((X86EMU_IRET_SEG << 4) + X86EMU_IRET_OFF, OP_HLT); + + pushw(X86EMU_DFLT_FLAGS); + pushw(X86EMU_IRET_SEG); + pushw(X86EMU_IRET_OFF); + + // Run the emulator + X86EMU_exec(); + + *eax = M.x86.R_EAX; + *ebx = M.x86.R_EBX; + + return NV_OK; +} diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/arch/nvalloc/unix/x86emu/debug.c nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/arch/nvalloc/unix/x86emu/debug.c --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/arch/nvalloc/unix/x86emu/debug.c 1970-01-01 00:00:00.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/arch/nvalloc/unix/x86emu/debug.c 2024-03-05 22:12:50.000000000 +0000 @@ -0,0 +1,547 @@ +/**************************************************************************** +* +* Realmode X86 Emulator Library +* +* Copyright (C) 1996-1999 SciTech Software, Inc. +* Copyright (C) David Mosberger-Tang +* Copyright (C) 1999 Egbert Eich +* +* ======================================================================== +* +* Permission to use, copy, modify, distribute, and sell this software and +* its documentation for any purpose is hereby granted without fee, +* provided that the above copyright notice appear in all copies and that +* both that copyright notice and this permission notice appear in +* supporting documentation, and that the name of the authors not be used +* in advertising or publicity pertaining to distribution of the software +* without specific, written prior permission. The authors makes no +* representations about the suitability of this software for any purpose. +* It is provided "as is" without express or implied warranty. +* +* THE AUTHORS DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOFTWARE, +* INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO +* EVENT SHALL THE AUTHORS BE LIABLE FOR ANY SPECIAL, INDIRECT OR +* CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF +* USE, DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR +* OTHER TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR +* PERFORMANCE OF THIS SOFTWARE. +* +* ======================================================================== +* +* Language: ANSI C +* Environment: Any +* Developer: Kendall Bennett +* +* Description: This file contains the code to handle debugging of the +* emulator. +* +****************************************************************************/ + +#include "x86emu/x86emui.h" +#ifndef NO_SYS_HEADERS +#include +#include +#endif + +/*----------------------------- Implementation ----------------------------*/ + +#ifdef X86EMU_DEBUG + +static void print_encoded_bytes (u16 s, u16 o); +static void print_decoded_instruction (void); +static int parse_line (char *s, int *ps, int *n); + +/* should look something like debug's output. */ +void X86EMU_trace_regs (void) +{ + if (DEBUG_TRACE()) { + x86emu_dump_regs(); + } + if (DEBUG_DECODE() && ! DEBUG_DECODE_NOPRINT()) { + NV_PRINTF(LEVEL_INFO, "%04x:%04x ", M.x86.saved_cs, + M.x86.saved_ip); + print_encoded_bytes( M.x86.saved_cs, M.x86.saved_ip); + print_decoded_instruction(); + } +} + +void X86EMU_trace_xregs (void) +{ + if (DEBUG_TRACE()) { + x86emu_dump_xregs(); + } +} + +void x86emu_just_disassemble (void) +{ + /* + * This routine called if the flag DEBUG_DISASSEMBLE is set kind + * of a hack! + */ + NV_PRINTF(LEVEL_INFO, "%04x:%04x ", M.x86.saved_cs, + M.x86.saved_ip); + print_encoded_bytes( M.x86.saved_cs, M.x86.saved_ip); + print_decoded_instruction(); +} + +static void disassemble_forward (u16 seg, u16 off, int n) +{ + X86EMU_sysEnv tregs; + int i; + u8 op1; + /* + * hack, hack, hack. What we do is use the exact machinery set up + * for execution, except that now there is an additional state + * flag associated with the "execution", and we are using a copy + * of the register struct. All the major opcodes, once fully + * decoded, have the following two steps: TRACE_REGS(r,m); + * SINGLE_STEP(r,m); which disappear if DEBUG is not defined to + * the preprocessor. The TRACE_REGS macro expands to: + * + * if (debug&DEBUG_DISASSEMBLE) + * {just_disassemble(); goto EndOfInstruction;} + * if (debug&DEBUG_TRACE) trace_regs(r,m); + * + * ...... and at the last line of the routine. + * + * EndOfInstruction: end_instr(); + * + * Up to the point where TRACE_REG is expanded, NO modifications + * are done to any register EXCEPT the IP register, for fetch and + * decoding purposes. + * + * This was done for an entirely different reason, but makes a + * nice way to get the system to help debug codes. + */ + tregs = M; + tregs.x86.R_IP = off; + tregs.x86.R_CS = seg; + + /* reset the decoding buffers */ + tregs.x86.enc_str_pos = 0; + tregs.x86.enc_pos = 0; + + /* turn on the "disassemble only, no execute" flag */ + tregs.x86.debug |= DEBUG_DISASSEMBLE_F; + + /* DUMP NEXT n instructions to screen in straight_line fashion */ + /* + * This looks like the regular instruction fetch stream, except + * that when this occurs, each fetched opcode, upon seeing the + * DEBUG_DISASSEMBLE flag set, exits immediately after decoding + * the instruction. XXX --- CHECK THAT MEM IS NOT AFFECTED!!! + * Note the use of a copy of the register structure... + */ + for (i=0; i 256) return; + seg = fetch_data_word_abs(0,iv*4); + off = fetch_data_word_abs(0,iv*4+2); + NV_PRINTF_EX(NV_PRINTF_MODULE, LEVEL_INFO, "%04x:%04x ", seg, off); +} + +void X86EMU_dump_memory (u16 seg, u16 off, u32 amt) +{ + u32 start = off & 0xfffffff0; + u32 end = (off+16) & 0xfffffff0; + u32 i; + + while (end <= off + amt) { + NV_PRINTF(LEVEL_INFO, "%04x:%04x ", seg, start); + for (i=start; i< off; i++) + NV_PRINTF_EX(NV_PRINTF_MODULE, LEVEL_INFO, " "); + for ( ; i< end; i++) + NV_PRINTF_EX(NV_PRINTF_MODULE, LEVEL_INFO, "%02x ", fetch_data_byte_abs(seg, i)); + NV_PRINTF_EX(NV_PRINTF_MODULE, LEVEL_INFO, "\n"); + start = end; + end = start + 16; + } +} + +void x86emu_single_step (void) +{ + int ps[10]; + int ntok; + int cmd; + int done; + int segment; + int offset; + static int breakpoint; + static int noDecode = 1; + + if (DEBUG_BREAK()) { + if (M.x86.saved_ip != breakpoint) { + return; + } else { + M.x86.debug &= ~DEBUG_DECODE_NOPRINT_F; + M.x86.debug |= DEBUG_TRACE_F; + M.x86.debug &= ~DEBUG_BREAK_F; + print_decoded_instruction (); + X86EMU_trace_regs(); + } + } + done=0; + offset = M.x86.saved_ip; + while (!done) { + NV_PRINTF(LEVEL_INFO, "-"); + + /* + * Set _X86EMU_env.x86.debug_cmd from a kernel debugger to a command to + * control the emulator debugger + */ + if (M.x86.debug_cmd[0] == '\0') + { + DBG_BREAKPOINT(); + } + + cmd = parse_line(M.x86.debug_cmd, ps, &ntok); + switch(cmd) { + case 'u': + disassemble_forward(M.x86.saved_cs,(u16)offset,10); + break; + case 'd': + if (ntok == 2) { + segment = M.x86.saved_cs; + offset = ps[1]; + X86EMU_dump_memory(segment,(u16)offset,16); + offset += 16; + } else if (ntok == 3) { + segment = ps[1]; + offset = ps[2]; + X86EMU_dump_memory(segment,(u16)offset,16); + offset += 16; + } else { + segment = M.x86.saved_cs; + X86EMU_dump_memory(segment,(u16)offset,16); + offset += 16; + } + break; + case 'c': + M.x86.debug ^= DEBUG_TRACECALL_F; + break; + case 's': + M.x86.debug ^= DEBUG_SVC_F | DEBUG_SYS_F | DEBUG_SYSINT_F; + break; + case 'r': + X86EMU_trace_regs(); + break; + case 'x': + X86EMU_trace_xregs(); + break; + case 'g': + if (ntok == 2) { + breakpoint = ps[1]; + if (noDecode) { + M.x86.debug |= DEBUG_DECODE_NOPRINT_F; + } else { + M.x86.debug &= ~DEBUG_DECODE_NOPRINT_F; + } + M.x86.debug &= ~DEBUG_TRACE_F; + M.x86.debug |= DEBUG_BREAK_F; + done = 1; + } + break; + case 'q': + M.x86.debug |= DEBUG_EXIT; + return; + case 'P': + noDecode = (noDecode)?0:1; + NV_PRINTF(LEVEL_INFO, "Toggled decoding to %s\n", + (noDecode) ? "FALSE" : "TRUE"); + break; + case 'a': + X86EMU_trace_off(); + /* fall thru */ + case 't': + case 0: + done = 1; + break; + } + portMemSet(&M.x86.debug_cmd, 0, sizeof(M.x86.debug_cmd)); + } +} + +int X86EMU_trace_on(void) +{ + return M.x86.debug |= DEBUG_STEP_F | DEBUG_DECODE_F | DEBUG_TRACE_F; +} + +int X86EMU_trace_off(void) +{ + return M.x86.debug &= ~(DEBUG_STEP_F | DEBUG_DECODE_F | DEBUG_TRACE_F); +} + +static void parse_hex (char *s, int *pval) +{ + unsigned int val = 0; + unsigned char c; + + if (s[0] == '0' && s[1] == 'x') + s += 2; + + while ((c = *(s++))) + { + if (c >= '0' && c <= '9') + { + val <<= 4; + val |= c - '0'; + continue; + } + else if (c >= 'a' && c <= 'f') + { + val <<= 4; + val |= c - 'a'; + continue; + } + else if (c >= 'A' && c <= 'F') + { + val <<= 4; + val |= c - 'A'; + continue; + } + break; + } + + *pval = val; +} + +static int parse_line (char *s, int *ps, int *n) +{ + int cmd; + + *n = 0; + while(*s == ' ' || *s == '\t') s++; + ps[*n] = *s; + switch (*s) { + case '\n': + *n += 1; + return 0; + default: + cmd = *s; + *n += 1; + } + + while (1) + { + while (*s != ' ' && *s != '\t' && *s != '\n' && *s != '\0') + s++; + + if (*s == '\n' || *s == '\0') + return cmd; + + while(*s == ' ' || *s == '\t') + s++; + + parse_hex(s, &ps[*n]); + *n += 1; + } +} + +void x86emu_dump_regs (void) +{ + NV_PRINTF(LEVEL_INFO, "\tAX=%04x ", M.x86.R_AX); + NV_PRINTF_EX(NV_PRINTF_MODULE, LEVEL_INFO, "BX=%04x ", M.x86.R_BX); + NV_PRINTF_EX(NV_PRINTF_MODULE, LEVEL_INFO, "CX=%04x ", M.x86.R_CX); + NV_PRINTF_EX(NV_PRINTF_MODULE, LEVEL_INFO, "DX=%04x ", M.x86.R_DX); + NV_PRINTF_EX(NV_PRINTF_MODULE, LEVEL_INFO, "SP=%04x ", M.x86.R_SP); + NV_PRINTF_EX(NV_PRINTF_MODULE, LEVEL_INFO, "BP=%04x ", M.x86.R_BP); + NV_PRINTF_EX(NV_PRINTF_MODULE, LEVEL_INFO, "SI=%04x ", M.x86.R_SI); + NV_PRINTF_EX(NV_PRINTF_MODULE, LEVEL_INFO, "DI=%04x\n", M.x86.R_DI); + NV_PRINTF_EX(NV_PRINTF_MODULE, LEVEL_INFO, "\tDS=%04x ", M.x86.R_DS); + NV_PRINTF_EX(NV_PRINTF_MODULE, LEVEL_INFO, "ES=%04x ", M.x86.R_ES); + NV_PRINTF_EX(NV_PRINTF_MODULE, LEVEL_INFO, "SS=%04x ", M.x86.R_SS); + NV_PRINTF_EX(NV_PRINTF_MODULE, LEVEL_INFO, "CS=%04x ", M.x86.R_CS); + NV_PRINTF_EX(NV_PRINTF_MODULE, LEVEL_INFO, "IP=%04x ", M.x86.R_IP); + if (ACCESS_FLAG(F_OF)) { + NV_PRINTF_EX(NV_PRINTF_MODULE, LEVEL_INFO, "OV "); + } else { + NV_PRINTF_EX(NV_PRINTF_MODULE, LEVEL_INFO, "NV "); + } + if (ACCESS_FLAG(F_DF)) { + NV_PRINTF_EX(NV_PRINTF_MODULE, LEVEL_INFO, "DN "); + } else { + NV_PRINTF_EX(NV_PRINTF_MODULE, LEVEL_INFO, "UP "); + } + if (ACCESS_FLAG(F_IF)) { + NV_PRINTF_EX(NV_PRINTF_MODULE, LEVEL_INFO, "EI "); + } else { + NV_PRINTF_EX(NV_PRINTF_MODULE, LEVEL_INFO, "DI "); + } + if (ACCESS_FLAG(F_SF)) { + NV_PRINTF_EX(NV_PRINTF_MODULE, LEVEL_INFO, "NG "); + } else { + NV_PRINTF_EX(NV_PRINTF_MODULE, LEVEL_INFO, "PL "); + } + if (ACCESS_FLAG(F_ZF)) { + NV_PRINTF_EX(NV_PRINTF_MODULE, LEVEL_INFO, "ZR "); + } else { + NV_PRINTF_EX(NV_PRINTF_MODULE, LEVEL_INFO, "NZ "); + } + if (ACCESS_FLAG(F_AF)) { + NV_PRINTF_EX(NV_PRINTF_MODULE, LEVEL_INFO, "AC "); + } else { + NV_PRINTF_EX(NV_PRINTF_MODULE, LEVEL_INFO, "NA "); + } + if (ACCESS_FLAG(F_PF)) { + NV_PRINTF_EX(NV_PRINTF_MODULE, LEVEL_INFO, "PE "); + } else { + NV_PRINTF_EX(NV_PRINTF_MODULE, LEVEL_INFO, "PO "); + } + if (ACCESS_FLAG(F_CF)) { + NV_PRINTF_EX(NV_PRINTF_MODULE, LEVEL_INFO, "CY "); + } else { + NV_PRINTF_EX(NV_PRINTF_MODULE, LEVEL_INFO, "NC "); + } + NV_PRINTF_EX(NV_PRINTF_MODULE, LEVEL_INFO, "\n"); +} + +void x86emu_dump_xregs (void) +{ + NV_PRINTF(LEVEL_INFO, "\tEAX=%08x ", M.x86.R_EAX); + NV_PRINTF_EX(NV_PRINTF_MODULE, LEVEL_INFO, "EBX=%08x ", M.x86.R_EBX); + NV_PRINTF_EX(NV_PRINTF_MODULE, LEVEL_INFO, "ECX=%08x ", M.x86.R_ECX); + NV_PRINTF_EX(NV_PRINTF_MODULE, LEVEL_INFO, "EDX=%08x \n", M.x86.R_EDX); + NV_PRINTF_EX(NV_PRINTF_MODULE, LEVEL_INFO, "\tESP=%08x ", M.x86.R_ESP); + NV_PRINTF_EX(NV_PRINTF_MODULE, LEVEL_INFO, "EBP=%08x ", M.x86.R_EBP); + NV_PRINTF_EX(NV_PRINTF_MODULE, LEVEL_INFO, "ESI=%08x ", M.x86.R_ESI); + NV_PRINTF_EX(NV_PRINTF_MODULE, LEVEL_INFO, "EDI=%08x\n", M.x86.R_EDI); + NV_PRINTF_EX(NV_PRINTF_MODULE, LEVEL_INFO, "\tDS=%04x ", M.x86.R_DS); + NV_PRINTF_EX(NV_PRINTF_MODULE, LEVEL_INFO, "ES=%04x ", M.x86.R_ES); + NV_PRINTF_EX(NV_PRINTF_MODULE, LEVEL_INFO, "SS=%04x ", M.x86.R_SS); + NV_PRINTF_EX(NV_PRINTF_MODULE, LEVEL_INFO, "CS=%04x ", M.x86.R_CS); + NV_PRINTF_EX(NV_PRINTF_MODULE, LEVEL_INFO, "EIP=%08x\n\t", M.x86.R_EIP); + if (ACCESS_FLAG(F_OF)) { + NV_PRINTF_EX(NV_PRINTF_MODULE, LEVEL_INFO, "OV "); + } else { + NV_PRINTF_EX(NV_PRINTF_MODULE, LEVEL_INFO, "NV "); + } + if (ACCESS_FLAG(F_DF)) { + NV_PRINTF_EX(NV_PRINTF_MODULE, LEVEL_INFO, "DN "); + } else { + NV_PRINTF_EX(NV_PRINTF_MODULE, LEVEL_INFO, "UP "); + } + if (ACCESS_FLAG(F_IF)) { + NV_PRINTF_EX(NV_PRINTF_MODULE, LEVEL_INFO, "EI "); + } else { + NV_PRINTF_EX(NV_PRINTF_MODULE, LEVEL_INFO, "DI "); + } + if (ACCESS_FLAG(F_SF)) { + NV_PRINTF_EX(NV_PRINTF_MODULE, LEVEL_INFO, "NG "); + } else { + NV_PRINTF_EX(NV_PRINTF_MODULE, LEVEL_INFO, "PL "); + } + if (ACCESS_FLAG(F_ZF)) { + NV_PRINTF_EX(NV_PRINTF_MODULE, LEVEL_INFO, "ZR "); + } else { + NV_PRINTF_EX(NV_PRINTF_MODULE, LEVEL_INFO, "NZ "); + } + if (ACCESS_FLAG(F_AF)) { + NV_PRINTF_EX(NV_PRINTF_MODULE, LEVEL_INFO, "AC "); + } else { + NV_PRINTF_EX(NV_PRINTF_MODULE, LEVEL_INFO, "NA "); + } + if (ACCESS_FLAG(F_PF)) { + NV_PRINTF_EX(NV_PRINTF_MODULE, LEVEL_INFO, "PE "); + } else { + NV_PRINTF_EX(NV_PRINTF_MODULE, LEVEL_INFO, "PO "); + } + if (ACCESS_FLAG(F_CF)) { + NV_PRINTF_EX(NV_PRINTF_MODULE, LEVEL_INFO, "CY "); + } else { + NV_PRINTF_EX(NV_PRINTF_MODULE, LEVEL_INFO, "NC "); + } + NV_PRINTF_EX(NV_PRINTF_MODULE, LEVEL_INFO, "\n"); +} + +#else + +void x86emu_dump_regs (void) +{ +} + +void x86emu_dump_xregs (void) +{ +} + +int X86EMU_trace_on(void) +{ + return 0; +} + +int X86EMU_trace_off(void) +{ + return 0; +} + +#endif /* X86EMU_DEBUG */ + diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/arch/nvalloc/unix/x86emu/decode.c nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/arch/nvalloc/unix/x86emu/decode.c --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/arch/nvalloc/unix/x86emu/decode.c 1970-01-01 00:00:00.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/arch/nvalloc/unix/x86emu/decode.c 2024-03-05 22:12:50.000000000 +0000 @@ -0,0 +1,1094 @@ +/**************************************************************************** +* +* Realmode X86 Emulator Library +* +* Copyright (C) 1996-1999 SciTech Software, Inc. +* Copyright (C) David Mosberger-Tang +* Copyright (C) 1999 Egbert Eich +* +* ======================================================================== +* +* Permission to use, copy, modify, distribute, and sell this software and +* its documentation for any purpose is hereby granted without fee, +* provided that the above copyright notice appear in all copies and that +* both that copyright notice and this permission notice appear in +* supporting documentation, and that the name of the authors not be used +* in advertising or publicity pertaining to distribution of the software +* without specific, written prior permission. The authors makes no +* representations about the suitability of this software for any purpose. +* It is provided "as is" without express or implied warranty. +* +* THE AUTHORS DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOFTWARE, +* INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO +* EVENT SHALL THE AUTHORS BE LIABLE FOR ANY SPECIAL, INDIRECT OR +* CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF +* USE, DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR +* OTHER TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR +* PERFORMANCE OF THIS SOFTWARE. +* +* ======================================================================== +* +* Language: ANSI C +* Environment: Any +* Developer: Kendall Bennett +* +* Description: This file includes subroutines which are related to +* instruction decoding and accessess of immediate data via IP. etc. +* +****************************************************************************/ + + +#include "x86emu/x86emui.h" + +/*----------------------------- Implementation ----------------------------*/ + +/**************************************************************************** +REMARKS: +Handles any pending asychronous interrupts. +****************************************************************************/ +static void x86emu_intr_handle(void) +{ + u8 intno; + + if (M.x86.intr & INTR_SYNCH) { + intno = M.x86.intno; + if (_X86EMU_intrTab[intno]) { + (*_X86EMU_intrTab[intno])(intno); + } else { + push_word((u16)M.x86.R_FLG); + CLEAR_FLAG(F_IF); + CLEAR_FLAG(F_TF); + push_word(M.x86.R_CS); + M.x86.R_CS = mem_access_word(intno * 4 + 2); + push_word(M.x86.R_IP); + M.x86.R_IP = mem_access_word(intno * 4); + M.x86.intr = 0; + } + } +} + +/**************************************************************************** +PARAMETERS: +intrnum - Interrupt number to raise + +REMARKS: +Raise the specified interrupt to be handled before the execution of the +next instruction. +****************************************************************************/ +void x86emu_intr_raise( + u8 intrnum) +{ + M.x86.intno = intrnum; + M.x86.intr |= INTR_SYNCH; +} + +/**************************************************************************** +REMARKS: +Main execution loop for the emulator. We return from here when the system +halts, which is normally caused by a stack fault when we return from the +original real mode call. +****************************************************************************/ +void X86EMU_exec(void) +{ + u8 op1; + + M.x86.intr = 0; + DB(x86emu_end_instr();) + + for (;;) { +DB( if (CHECK_IP_FETCH()) + x86emu_check_ip_access();) + /* If debugging, save the IP and CS values. */ + SAVE_IP_CS(M.x86.R_CS, M.x86.R_IP); + INC_DECODED_INST_LEN(1); + if (M.x86.intr) { + if (M.x86.intr & INTR_HALTED) { +DB( if (M.x86.R_SP != 0) { + NV_PRINTF(LEVEL_INFO, "halted\n"); + X86EMU_trace_regs(); + } + else { + if (M.x86.debug) + NV_PRINTF(LEVEL_INFO, + "Service completed successfully\n"); + }) + return; + } + if (((M.x86.intr & INTR_SYNCH) && (M.x86.intno == 0 || M.x86.intno == 2)) || + !ACCESS_FLAG(F_IF)) { + x86emu_intr_handle(); + } + } + op1 = (*sys_rdb)(((u32)M.x86.R_CS << 4) + (M.x86.R_IP++)); + (*x86emu_optab[op1])(op1); + if (M.x86.debug & DEBUG_EXIT) { + M.x86.debug &= ~DEBUG_EXIT; + return; + } + } +} + +/**************************************************************************** +REMARKS: +Halts the system by setting the halted system flag. +****************************************************************************/ +void X86EMU_halt_sys(void) +{ + M.x86.intr |= INTR_HALTED; +} + +/**************************************************************************** +PARAMETERS: +mod - Mod value from decoded byte +regh - Reg h value from decoded byte +regl - Reg l value from decoded byte + +REMARKS: +Raise the specified interrupt to be handled before the execution of the +next instruction. + +NOTE: Do not inline this function, as (*sys_rdb) is already inline! +****************************************************************************/ +void fetch_decode_modrm( + int *mod, + int *regh, + int *regl) +{ + int fetched; + +DB( if (CHECK_IP_FETCH()) + x86emu_check_ip_access();) + fetched = (*sys_rdb)(((u32)M.x86.R_CS << 4) + (M.x86.R_IP++)); + INC_DECODED_INST_LEN(1); + *mod = (fetched >> 6) & 0x03; + *regh = (fetched >> 3) & 0x07; + *regl = (fetched >> 0) & 0x07; +} + +/**************************************************************************** +RETURNS: +Immediate byte value read from instruction queue + +REMARKS: +This function returns the immediate byte from the instruction queue, and +moves the instruction pointer to the next value. + +NOTE: Do not inline this function, as (*sys_rdb) is already inline! +****************************************************************************/ +u8 fetch_byte_imm(void) +{ + u8 fetched; + +DB( if (CHECK_IP_FETCH()) + x86emu_check_ip_access();) + fetched = (*sys_rdb)(((u32)M.x86.R_CS << 4) + (M.x86.R_IP++)); + INC_DECODED_INST_LEN(1); + return fetched; +} + +/**************************************************************************** +RETURNS: +Immediate word value read from instruction queue + +REMARKS: +This function returns the immediate byte from the instruction queue, and +moves the instruction pointer to the next value. + +NOTE: Do not inline this function, as (*sys_rdw) is already inline! +****************************************************************************/ +u16 fetch_word_imm(void) +{ + u16 fetched; + +DB( if (CHECK_IP_FETCH()) + x86emu_check_ip_access();) + fetched = (*sys_rdw)(((u32)M.x86.R_CS << 4) + (M.x86.R_IP)); + M.x86.R_IP += 2; + INC_DECODED_INST_LEN(2); + return fetched; +} + +/**************************************************************************** +RETURNS: +Immediate lone value read from instruction queue + +REMARKS: +This function returns the immediate byte from the instruction queue, and +moves the instruction pointer to the next value. + +NOTE: Do not inline this function, as (*sys_rdw) is already inline! +****************************************************************************/ +u32 fetch_long_imm(void) +{ + u32 fetched; + +DB( if (CHECK_IP_FETCH()) + x86emu_check_ip_access();) + fetched = (*sys_rdl)(((u32)M.x86.R_CS << 4) + (M.x86.R_IP)); + M.x86.R_IP += 4; + INC_DECODED_INST_LEN(4); + return fetched; +} + +/**************************************************************************** +RETURNS: +Value of the default data segment + +REMARKS: +Inline function that returns the default data segment for the current +instruction. + +On the x86 processor, the default segment is not always DS if there is +no segment override. Address modes such as -3[BP] or 10[BP+SI] all refer to +addresses relative to SS (ie: on the stack). So, at the minimum, all +decodings of addressing modes would have to set/clear a bit describing +whether the access is relative to DS or SS. That is the function of the +cpu-state-varible M.x86.mode. There are several potential states: + + repe prefix seen (handled elsewhere) + repne prefix seen (ditto) + + cs segment override + ds segment override + es segment override + fs segment override + gs segment override + ss segment override + + ds/ss select (in absense of override) + +Each of the above 7 items are handled with a bit in the mode field. +****************************************************************************/ +_INLINE u32 get_data_segment(void) +{ +#define GET_SEGMENT(segment) + switch (M.x86.mode & SYSMODE_SEGMASK) { + case 0: /* default case: use ds register */ + case SYSMODE_SEGOVR_DS: + case SYSMODE_SEGOVR_DS | SYSMODE_SEG_DS_SS: + return M.x86.R_DS; + case SYSMODE_SEG_DS_SS: /* non-overridden, use ss register */ + return M.x86.R_SS; + case SYSMODE_SEGOVR_CS: + case SYSMODE_SEGOVR_CS | SYSMODE_SEG_DS_SS: + return M.x86.R_CS; + case SYSMODE_SEGOVR_ES: + case SYSMODE_SEGOVR_ES | SYSMODE_SEG_DS_SS: + return M.x86.R_ES; + case SYSMODE_SEGOVR_FS: + case SYSMODE_SEGOVR_FS | SYSMODE_SEG_DS_SS: + return M.x86.R_FS; + case SYSMODE_SEGOVR_GS: + case SYSMODE_SEGOVR_GS | SYSMODE_SEG_DS_SS: + return M.x86.R_GS; + case SYSMODE_SEGOVR_SS: + case SYSMODE_SEGOVR_SS | SYSMODE_SEG_DS_SS: + return M.x86.R_SS; + default: +#ifdef X86EMU_DEBUG + NV_PRINTF(LEVEL_INFO, + "error: should not happen: multiple overrides.\n"); +#endif + HALT_SYS(); + return 0; + } +} + +/**************************************************************************** +PARAMETERS: +offset - Offset to load data from + +RETURNS: +Byte value read from the absolute memory location. + +NOTE: Do not inline this function as (*sys_rdX) is already inline! +****************************************************************************/ +u8 fetch_data_byte( + uint offset) +{ +#ifdef X86EMU_DEBUG + if (CHECK_DATA_ACCESS()) + x86emu_check_data_access((u16)get_data_segment(), offset); +#endif + return (*sys_rdb)((get_data_segment() << 4) + offset); +} + +/**************************************************************************** +PARAMETERS: +offset - Offset to load data from + +RETURNS: +Word value read from the absolute memory location. + +NOTE: Do not inline this function as (*sys_rdX) is already inline! +****************************************************************************/ +u16 fetch_data_word( + uint offset) +{ +#ifdef X86EMU_DEBUG + if (CHECK_DATA_ACCESS()) + x86emu_check_data_access((u16)get_data_segment(), offset); +#endif + return (*sys_rdw)((get_data_segment() << 4) + offset); +} + +/**************************************************************************** +PARAMETERS: +offset - Offset to load data from + +RETURNS: +Long value read from the absolute memory location. + +NOTE: Do not inline this function as (*sys_rdX) is already inline! +****************************************************************************/ +u32 fetch_data_long( + uint offset) +{ +#ifdef X86EMU_DEBUG + if (CHECK_DATA_ACCESS()) + x86emu_check_data_access((u16)get_data_segment(), offset); +#endif + return (*sys_rdl)((get_data_segment() << 4) + offset); +} + +/**************************************************************************** +PARAMETERS: +segment - Segment to load data from +offset - Offset to load data from + +RETURNS: +Byte value read from the absolute memory location. + +NOTE: Do not inline this function as (*sys_rdX) is already inline! +****************************************************************************/ +u8 fetch_data_byte_abs( + uint segment, + uint offset) +{ +#ifdef X86EMU_DEBUG + if (CHECK_DATA_ACCESS()) + x86emu_check_data_access(segment, offset); +#endif + return (*sys_rdb)(((u32)segment << 4) + offset); +} + +/**************************************************************************** +PARAMETERS: +segment - Segment to load data from +offset - Offset to load data from + +RETURNS: +Word value read from the absolute memory location. + +NOTE: Do not inline this function as (*sys_rdX) is already inline! +****************************************************************************/ +u16 fetch_data_word_abs( + uint segment, + uint offset) +{ +#ifdef X86EMU_DEBUG + if (CHECK_DATA_ACCESS()) + x86emu_check_data_access(segment, offset); +#endif + return (*sys_rdw)(((u32)segment << 4) + offset); +} + +/**************************************************************************** +PARAMETERS: +segment - Segment to load data from +offset - Offset to load data from + +RETURNS: +Long value read from the absolute memory location. + +NOTE: Do not inline this function as (*sys_rdX) is already inline! +****************************************************************************/ +u32 fetch_data_long_abs( + uint segment, + uint offset) +{ +#ifdef X86EMU_DEBUG + if (CHECK_DATA_ACCESS()) + x86emu_check_data_access(segment, offset); +#endif + return (*sys_rdl)(((u32)segment << 4) + offset); +} + +/**************************************************************************** +PARAMETERS: +offset - Offset to store data at +val - Value to store + +REMARKS: +Writes a word value to an segmented memory location. The segment used is +the current 'default' segment, which may have been overridden. + +NOTE: Do not inline this function as (*sys_wrX) is already inline! +****************************************************************************/ +void store_data_byte( + uint offset, + u8 val) +{ +#ifdef X86EMU_DEBUG + if (CHECK_DATA_ACCESS()) + x86emu_check_data_access((u16)get_data_segment(), offset); +#endif + (*sys_wrb)((get_data_segment() << 4) + offset, val); +} + +/**************************************************************************** +PARAMETERS: +offset - Offset to store data at +val - Value to store + +REMARKS: +Writes a word value to an segmented memory location. The segment used is +the current 'default' segment, which may have been overridden. + +NOTE: Do not inline this function as (*sys_wrX) is already inline! +****************************************************************************/ +void store_data_word( + uint offset, + u16 val) +{ +#ifdef X86EMU_DEBUG + if (CHECK_DATA_ACCESS()) + x86emu_check_data_access((u16)get_data_segment(), offset); +#endif + (*sys_wrw)((get_data_segment() << 4) + offset, val); +} + +/**************************************************************************** +PARAMETERS: +offset - Offset to store data at +val - Value to store + +REMARKS: +Writes a long value to an segmented memory location. The segment used is +the current 'default' segment, which may have been overridden. + +NOTE: Do not inline this function as (*sys_wrX) is already inline! +****************************************************************************/ +void store_data_long( + uint offset, + u32 val) +{ +#ifdef X86EMU_DEBUG + if (CHECK_DATA_ACCESS()) + x86emu_check_data_access((u16)get_data_segment(), offset); +#endif + (*sys_wrl)((get_data_segment() << 4) + offset, val); +} + +/**************************************************************************** +PARAMETERS: +segment - Segment to store data at +offset - Offset to store data at +val - Value to store + +REMARKS: +Writes a byte value to an absolute memory location. + +NOTE: Do not inline this function as (*sys_wrX) is already inline! +****************************************************************************/ +void store_data_byte_abs( + uint segment, + uint offset, + u8 val) +{ +#ifdef X86EMU_DEBUG + if (CHECK_DATA_ACCESS()) + x86emu_check_data_access(segment, offset); +#endif + (*sys_wrb)(((u32)segment << 4) + offset, val); +} + +/**************************************************************************** +PARAMETERS: +segment - Segment to store data at +offset - Offset to store data at +val - Value to store + +REMARKS: +Writes a word value to an absolute memory location. + +NOTE: Do not inline this function as (*sys_wrX) is already inline! +****************************************************************************/ +void store_data_word_abs( + uint segment, + uint offset, + u16 val) +{ +#ifdef X86EMU_DEBUG + if (CHECK_DATA_ACCESS()) + x86emu_check_data_access(segment, offset); +#endif + (*sys_wrw)(((u32)segment << 4) + offset, val); +} + +/**************************************************************************** +PARAMETERS: +segment - Segment to store data at +offset - Offset to store data at +val - Value to store + +REMARKS: +Writes a long value to an absolute memory location. + +NOTE: Do not inline this function as (*sys_wrX) is already inline! +****************************************************************************/ +void store_data_long_abs( + uint segment, + uint offset, + u32 val) +{ +#ifdef X86EMU_DEBUG + if (CHECK_DATA_ACCESS()) + x86emu_check_data_access(segment, offset); +#endif + (*sys_wrl)(((u32)segment << 4) + offset, val); +} + +/**************************************************************************** +PARAMETERS: +reg - Register to decode + +RETURNS: +Pointer to the appropriate register + +REMARKS: +Return a pointer to the register given by the R/RM field of the +modrm byte, for byte operands. Also enables the decoding of instructions. +****************************************************************************/ +u8* decode_rm_byte_register( + int reg) +{ + switch (reg) { + case 0: + DECODE_PRINTF("AL"); + return &M.x86.R_AL; + case 1: + DECODE_PRINTF("CL"); + return &M.x86.R_CL; + case 2: + DECODE_PRINTF("DL"); + return &M.x86.R_DL; + case 3: + DECODE_PRINTF("BL"); + return &M.x86.R_BL; + case 4: + DECODE_PRINTF("AH"); + return &M.x86.R_AH; + case 5: + DECODE_PRINTF("CH"); + return &M.x86.R_CH; + case 6: + DECODE_PRINTF("DH"); + return &M.x86.R_DH; + case 7: + DECODE_PRINTF("BH"); + return &M.x86.R_BH; + } + HALT_SYS(); + return NULL; /* NOT REACHED OR REACHED ON ERROR */ +} + +/**************************************************************************** +PARAMETERS: +reg - Register to decode + +RETURNS: +Pointer to the appropriate register + +REMARKS: +Return a pointer to the register given by the R/RM field of the +modrm byte, for word operands. Also enables the decoding of instructions. +****************************************************************************/ +u16* decode_rm_word_register( + int reg) +{ + switch (reg) { + case 0: + DECODE_PRINTF("AX"); + return &M.x86.R_AX; + case 1: + DECODE_PRINTF("CX"); + return &M.x86.R_CX; + case 2: + DECODE_PRINTF("DX"); + return &M.x86.R_DX; + case 3: + DECODE_PRINTF("BX"); + return &M.x86.R_BX; + case 4: + DECODE_PRINTF("SP"); + return &M.x86.R_SP; + case 5: + DECODE_PRINTF("BP"); + return &M.x86.R_BP; + case 6: + DECODE_PRINTF("SI"); + return &M.x86.R_SI; + case 7: + DECODE_PRINTF("DI"); + return &M.x86.R_DI; + } + HALT_SYS(); + return NULL; /* NOTREACHED OR REACHED ON ERROR */ +} + +/**************************************************************************** +PARAMETERS: +reg - Register to decode + +RETURNS: +Pointer to the appropriate register + +REMARKS: +Return a pointer to the register given by the R/RM field of the +modrm byte, for dword operands. Also enables the decoding of instructions. +****************************************************************************/ +u32* decode_rm_long_register( + int reg) +{ + switch (reg) { + case 0: + DECODE_PRINTF("EAX"); + return &M.x86.R_EAX; + case 1: + DECODE_PRINTF("ECX"); + return &M.x86.R_ECX; + case 2: + DECODE_PRINTF("EDX"); + return &M.x86.R_EDX; + case 3: + DECODE_PRINTF("EBX"); + return &M.x86.R_EBX; + case 4: + DECODE_PRINTF("ESP"); + return &M.x86.R_ESP; + case 5: + DECODE_PRINTF("EBP"); + return &M.x86.R_EBP; + case 6: + DECODE_PRINTF("ESI"); + return &M.x86.R_ESI; + case 7: + DECODE_PRINTF("EDI"); + return &M.x86.R_EDI; + } + HALT_SYS(); + return NULL; /* NOTREACHED OR REACHED ON ERROR */ +} + +/**************************************************************************** +PARAMETERS: +reg - Register to decode + +RETURNS: +Pointer to the appropriate register + +REMARKS: +Return a pointer to the register given by the R/RM field of the +modrm byte, for word operands, modified from above for the weirdo +special case of segreg operands. Also enables the decoding of instructions. +****************************************************************************/ +u16* decode_rm_seg_register( + int reg) +{ + switch (reg) { + case 0: + DECODE_PRINTF("ES"); + return &M.x86.R_ES; + case 1: + DECODE_PRINTF("CS"); + return &M.x86.R_CS; + case 2: + DECODE_PRINTF("SS"); + return &M.x86.R_SS; + case 3: + DECODE_PRINTF("DS"); + return &M.x86.R_DS; + case 4: + DECODE_PRINTF("FS"); + return &M.x86.R_FS; + case 5: + DECODE_PRINTF("GS"); + return &M.x86.R_GS; + case 6: + case 7: + DECODE_PRINTF("ILLEGAL SEGREG"); + break; + } + HALT_SYS(); + return NULL; /* NOT REACHED OR REACHED ON ERROR */ +} + +/* + * + * return offset from the SIB Byte + */ +u32 decode_sib_address(int sib, int mod) +{ + u32 base = 0, i = 0, scale = 1; + + switch(sib & 0x07) { + case 0: + DECODE_PRINTF("[EAX]"); + base = M.x86.R_EAX; + break; + case 1: + DECODE_PRINTF("[ECX]"); + base = M.x86.R_ECX; + break; + case 2: + DECODE_PRINTF("[EDX]"); + base = M.x86.R_EDX; + break; + case 3: + DECODE_PRINTF("[EBX]"); + base = M.x86.R_EBX; + break; + case 4: + DECODE_PRINTF("[ESP]"); + base = M.x86.R_ESP; + M.x86.mode |= SYSMODE_SEG_DS_SS; + break; + case 5: + if (mod == 0) { + base = fetch_long_imm(); + DECODE_PRINTF2("%08x", base); + } else { + DECODE_PRINTF("[EBP]"); + base = M.x86.R_ESP; + M.x86.mode |= SYSMODE_SEG_DS_SS; + } + break; + case 6: + DECODE_PRINTF("[ESI]"); + base = M.x86.R_ESI; + break; + case 7: + DECODE_PRINTF("[EDI]"); + base = M.x86.R_EDI; + break; + } + switch ((sib >> 3) & 0x07) { + case 0: + DECODE_PRINTF("[EAX"); + i = M.x86.R_EAX; + break; + case 1: + DECODE_PRINTF("[ECX"); + i = M.x86.R_ECX; + break; + case 2: + DECODE_PRINTF("[EDX"); + i = M.x86.R_EDX; + break; + case 3: + DECODE_PRINTF("[EBX"); + i = M.x86.R_EBX; + break; + case 4: + i = 0; + break; + case 5: + DECODE_PRINTF("[EBP"); + i = M.x86.R_EBP; + break; + case 6: + DECODE_PRINTF("[ESI"); + i = M.x86.R_ESI; + break; + case 7: + DECODE_PRINTF("[EDI"); + i = M.x86.R_EDI; + break; + } + scale = 1 << ((sib >> 6) & 0x03); + if (((sib >> 3) & 0x07) != 4) { + if (scale == 1) { + DECODE_PRINTF("]"); + } else { + DECODE_PRINTF2("*%d]", scale); + } + } + return base + (i * scale); +} + +/**************************************************************************** +PARAMETERS: +rm - RM value to decode + +RETURNS: +Offset in memory for the address decoding + +REMARKS: +Return the offset given by mod=00 addressing. Also enables the +decoding of instructions. + +NOTE: The code which specifies the corresponding segment (ds vs ss) + below in the case of [BP+..]. The assumption here is that at the + point that this subroutine is called, the bit corresponding to + SYSMODE_SEG_DS_SS will be zero. After every instruction + except the segment override instructions, this bit (as well + as any bits indicating segment overrides) will be clear. So + if a SS access is needed, set this bit. Otherwise, DS access + occurs (unless any of the segment override bits are set). +****************************************************************************/ +u32 decode_rm00_address( + int rm) +{ + u32 offset; + int sib; + + if (M.x86.mode & SYSMODE_PREFIX_ADDR) { + /* 32-bit addressing */ + switch (rm) { + case 0: + DECODE_PRINTF("[EAX]"); + return M.x86.R_EAX; + case 1: + DECODE_PRINTF("[ECX]"); + return M.x86.R_ECX; + case 2: + DECODE_PRINTF("[EDX]"); + return M.x86.R_EDX; + case 3: + DECODE_PRINTF("[EBX]"); + return M.x86.R_EBX; + case 4: + sib = fetch_byte_imm(); + return decode_sib_address(sib, 0); + case 5: + offset = fetch_long_imm(); + DECODE_PRINTF2("[%08x]", offset); + return offset; + case 6: + DECODE_PRINTF("[ESI]"); + return M.x86.R_ESI; + case 7: + DECODE_PRINTF("[EDI]"); + return M.x86.R_EDI; + } + HALT_SYS(); + } else { + /* 16-bit addressing */ + switch (rm) { + case 0: + DECODE_PRINTF("[BX+SI]"); + return (M.x86.R_BX + M.x86.R_SI) & 0xffff; + case 1: + DECODE_PRINTF("[BX+DI]"); + return (M.x86.R_BX + M.x86.R_DI) & 0xffff; + case 2: + DECODE_PRINTF("[BP+SI]"); + M.x86.mode |= SYSMODE_SEG_DS_SS; + return (M.x86.R_BP + M.x86.R_SI) & 0xffff; + case 3: + DECODE_PRINTF("[BP+DI]"); + M.x86.mode |= SYSMODE_SEG_DS_SS; + return (M.x86.R_BP + M.x86.R_DI) & 0xffff; + case 4: + DECODE_PRINTF("[SI]"); + return M.x86.R_SI; + case 5: + DECODE_PRINTF("[DI]"); + return M.x86.R_DI; + case 6: + offset = fetch_word_imm(); + DECODE_PRINTF2("[%04x]", offset); + return offset; + case 7: + DECODE_PRINTF("[BX]"); + return M.x86.R_BX; + } + HALT_SYS(); + } + return 0; +} + +/**************************************************************************** +PARAMETERS: +rm - RM value to decode + +RETURNS: +Offset in memory for the address decoding + +REMARKS: +Return the offset given by mod=01 addressing. Also enables the +decoding of instructions. +****************************************************************************/ +u32 decode_rm01_address( + int rm) +{ + int displacement = 0; + int sib; + + /* Fetch disp8 if no SIB byte */ + if (!((M.x86.mode & SYSMODE_PREFIX_ADDR) && (rm == 4))) + displacement = (s8)fetch_byte_imm(); + + if (M.x86.mode & SYSMODE_PREFIX_ADDR) { + /* 32-bit addressing */ + switch (rm) { + case 0: + DECODE_PRINTF2("%d[EAX]", displacement); + return M.x86.R_EAX + displacement; + case 1: + DECODE_PRINTF2("%d[ECX]", displacement); + return M.x86.R_ECX + displacement; + case 2: + DECODE_PRINTF2("%d[EDX]", displacement); + return M.x86.R_EDX + displacement; + case 3: + DECODE_PRINTF2("%d[EBX]", displacement); + return M.x86.R_EBX + displacement; + case 4: + sib = fetch_byte_imm(); + displacement = (s8)fetch_byte_imm(); + DECODE_PRINTF2("%d", displacement); + return decode_sib_address(sib, 1) + displacement; + case 5: + DECODE_PRINTF2("%d[EBP]", displacement); + return M.x86.R_EBP + displacement; + case 6: + DECODE_PRINTF2("%d[ESI]", displacement); + return M.x86.R_ESI + displacement; + case 7: + DECODE_PRINTF2("%d[EDI]", displacement); + return M.x86.R_EDI + displacement; + } + HALT_SYS(); + } else { + /* 16-bit addressing */ + switch (rm) { + case 0: + DECODE_PRINTF2("%d[BX+SI]", displacement); + return (M.x86.R_BX + M.x86.R_SI + displacement) & 0xffff; + case 1: + DECODE_PRINTF2("%d[BX+DI]", displacement); + return (M.x86.R_BX + M.x86.R_DI + displacement) & 0xffff; + case 2: + DECODE_PRINTF2("%d[BP+SI]", displacement); + M.x86.mode |= SYSMODE_SEG_DS_SS; + return (M.x86.R_BP + M.x86.R_SI + displacement) & 0xffff; + case 3: + DECODE_PRINTF2("%d[BP+DI]", displacement); + M.x86.mode |= SYSMODE_SEG_DS_SS; + return (M.x86.R_BP + M.x86.R_DI + displacement) & 0xffff; + case 4: + DECODE_PRINTF2("%d[SI]", displacement); + return (M.x86.R_SI + displacement) & 0xffff; + case 5: + DECODE_PRINTF2("%d[DI]", displacement); + return (M.x86.R_DI + displacement) & 0xffff; + case 6: + DECODE_PRINTF2("%d[BP]", displacement); + M.x86.mode |= SYSMODE_SEG_DS_SS; + return (M.x86.R_BP + displacement) & 0xffff; + case 7: + DECODE_PRINTF2("%d[BX]", displacement); + return (M.x86.R_BX + displacement) & 0xffff; + } + HALT_SYS(); + } + return 0; /* SHOULD NOT HAPPEN */ +} + +/**************************************************************************** +PARAMETERS: +rm - RM value to decode + +RETURNS: +Offset in memory for the address decoding + +REMARKS: +Return the offset given by mod=10 addressing. Also enables the +decoding of instructions. +****************************************************************************/ +u32 decode_rm10_address( + int rm) +{ + u32 displacement = 0; + int sib; + + /* Fetch disp16 if 16-bit addr mode */ + if (!(M.x86.mode & SYSMODE_PREFIX_ADDR)) + displacement = (u16)fetch_word_imm(); + else { + /* Fetch disp32 if no SIB byte */ + if (rm != 4) + displacement = (u32)fetch_long_imm(); + } + + if (M.x86.mode & SYSMODE_PREFIX_ADDR) { + /* 32-bit addressing */ + switch (rm) { + case 0: + DECODE_PRINTF2("%08x[EAX]", displacement); + return M.x86.R_EAX + displacement; + case 1: + DECODE_PRINTF2("%08x[ECX]", displacement); + return M.x86.R_ECX + displacement; + case 2: + DECODE_PRINTF2("%08x[EDX]", displacement); + M.x86.mode |= SYSMODE_SEG_DS_SS; + return M.x86.R_EDX + displacement; + case 3: + DECODE_PRINTF2("%08x[EBX]", displacement); + return M.x86.R_EBX + displacement; + case 4: + sib = fetch_byte_imm(); + displacement = (u32)fetch_long_imm(); + DECODE_PRINTF2("%08x", displacement); + return decode_sib_address(sib, 2) + displacement; + break; + case 5: + DECODE_PRINTF2("%08x[EBP]", displacement); + return M.x86.R_EBP + displacement; + case 6: + DECODE_PRINTF2("%08x[ESI]", displacement); + return M.x86.R_ESI + displacement; + case 7: + DECODE_PRINTF2("%08x[EDI]", displacement); + return M.x86.R_EDI + displacement; + } + HALT_SYS(); + } else { + /* 16-bit addressing */ + switch (rm) { + case 0: + DECODE_PRINTF2("%04x[BX+SI]", displacement); + return (M.x86.R_BX + M.x86.R_SI + displacement) & 0xffff; + case 1: + DECODE_PRINTF2("%04x[BX+DI]", displacement); + return (M.x86.R_BX + M.x86.R_DI + displacement) & 0xffff; + case 2: + DECODE_PRINTF2("%04x[BP+SI]", displacement); + M.x86.mode |= SYSMODE_SEG_DS_SS; + return (M.x86.R_BP + M.x86.R_SI + displacement) & 0xffff; + case 3: + DECODE_PRINTF2("%04x[BP+DI]", displacement); + M.x86.mode |= SYSMODE_SEG_DS_SS; + return (M.x86.R_BP + M.x86.R_DI + displacement) & 0xffff; + case 4: + DECODE_PRINTF2("%04x[SI]", displacement); + return (M.x86.R_SI + displacement) & 0xffff; + case 5: + DECODE_PRINTF2("%04x[DI]", displacement); + return (M.x86.R_DI + displacement) & 0xffff; + case 6: + DECODE_PRINTF2("%04x[BP]", displacement); + M.x86.mode |= SYSMODE_SEG_DS_SS; + return (M.x86.R_BP + displacement) & 0xffff; + case 7: + DECODE_PRINTF2("%04x[BX]", displacement); + return (M.x86.R_BX + displacement) & 0xffff; + } + HALT_SYS(); + } + return 0; + /*NOTREACHED */ +} diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/arch/nvalloc/unix/x86emu/fpu.c nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/arch/nvalloc/unix/x86emu/fpu.c --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/arch/nvalloc/unix/x86emu/fpu.c 1970-01-01 00:00:00.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/arch/nvalloc/unix/x86emu/fpu.c 2024-03-05 22:12:50.000000000 +0000 @@ -0,0 +1,965 @@ +/**************************************************************************** +* +* Realmode X86 Emulator Library +* +* Copyright (C) 1996-1999 SciTech Software, Inc. +* Copyright (C) David Mosberger-Tang +* Copyright (C) 1999 Egbert Eich +* +* ======================================================================== +* +* Permission to use, copy, modify, distribute, and sell this software and +* its documentation for any purpose is hereby granted without fee, +* provided that the above copyright notice appear in all copies and that +* both that copyright notice and this permission notice appear in +* supporting documentation, and that the name of the authors not be used +* in advertising or publicity pertaining to distribution of the software +* without specific, written prior permission. The authors makes no +* representations about the suitability of this software for any purpose. +* It is provided "as is" without express or implied warranty. +* +* THE AUTHORS DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOFTWARE, +* INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO +* EVENT SHALL THE AUTHORS BE LIABLE FOR ANY SPECIAL, INDIRECT OR +* CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF +* USE, DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR +* OTHER TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR +* PERFORMANCE OF THIS SOFTWARE. +* +* ======================================================================== +* +* Language: ANSI C +* Environment: Any +* Developer: Kendall Bennett +* +* Description: This file contains the code to implement the decoding and +* emulation of the FPU instructions. +* +****************************************************************************/ + +#include "x86emu/x86emui.h" + +/*----------------------------- Implementation ----------------------------*/ + +/* opcode=0xd8 */ +void x86emuOp_esc_coprocess_d8(u8 X86EMU_UNUSED(op1)) +{ + START_OF_INSTR(); + DECODE_PRINTF("ESC D8\n"); + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR_NO_TRACE(); +} + +#ifdef X86EMU_DEBUG + +static char *x86emu_fpu_op_d9_tab[] = { + "FLD\tDWORD PTR ", "ESC_D9\t", "FST\tDWORD PTR ", "FSTP\tDWORD PTR ", + "FLDENV\t", "FLDCW\t", "FSTENV\t", "FSTCW\t", + + "FLD\tDWORD PTR ", "ESC_D9\t", "FST\tDWORD PTR ", "FSTP\tDWORD PTR ", + "FLDENV\t", "FLDCW\t", "FSTENV\t", "FSTCW\t", + + "FLD\tDWORD PTR ", "ESC_D9\t", "FST\tDWORD PTR ", "FSTP\tDWORD PTR ", + "FLDENV\t", "FLDCW\t", "FSTENV\t", "FSTCW\t", +}; + +static char *x86emu_fpu_op_d9_tab1[] = { + "FLD\t", "FLD\t", "FLD\t", "FLD\t", + "FLD\t", "FLD\t", "FLD\t", "FLD\t", + + "FXCH\t", "FXCH\t", "FXCH\t", "FXCH\t", + "FXCH\t", "FXCH\t", "FXCH\t", "FXCH\t", + + "FNOP", "ESC_D9", "ESC_D9", "ESC_D9", + "ESC_D9", "ESC_D9", "ESC_D9", "ESC_D9", + + "FSTP\t", "FSTP\t", "FSTP\t", "FSTP\t", + "FSTP\t", "FSTP\t", "FSTP\t", "FSTP\t", + + "FCHS", "FABS", "ESC_D9", "ESC_D9", + "FTST", "FXAM", "ESC_D9", "ESC_D9", + + "FLD1", "FLDL2T", "FLDL2E", "FLDPI", + "FLDLG2", "FLDLN2", "FLDZ", "ESC_D9", + + "F2XM1", "FYL2X", "FPTAN", "FPATAN", + "FXTRACT", "ESC_D9", "FDECSTP", "FINCSTP", + + "FPREM", "FYL2XP1", "FSQRT", "ESC_D9", + "FRNDINT", "FSCALE", "ESC_D9", "ESC_D9", +}; + +#endif /* X86EMU_DEBUG */ + +/* opcode=0xd9 */ +void x86emuOp_esc_coprocess_d9(u8 X86EMU_UNUSED(op1)) +{ + int mod, rl, rh; + uint destoffset = 0; + u8 stkelem = 0; + + START_OF_INSTR(); + FETCH_DECODE_MODRM(mod, rh, rl); +#ifdef X86EMU_DEBUG + if (mod != 3) { + DECODE_PRINTINSTR32(x86emu_fpu_op_d9_tab, mod, rh, rl); + } else { + DECODE_PRINTF(x86emu_fpu_op_d9_tab1[(rh << 3) + rl]); + } +#endif + switch (mod) { + case 0: + destoffset = decode_rm00_address(rl); + DECODE_PRINTF("\n"); + break; + case 1: + destoffset = decode_rm01_address(rl); + DECODE_PRINTF("\n"); + break; + case 2: + destoffset = decode_rm10_address(rl); + DECODE_PRINTF("\n"); + break; + case 3: /* register to register */ + stkelem = (u8)rl; + if (rh < 4) { + DECODE_PRINTF2("ST(%d)\n", stkelem); + } else { + DECODE_PRINTF("\n"); + } + break; + } +#ifdef X86EMU_FPU_PRESENT + /* execute */ + switch (mod) { + case 3: + switch (rh) { + case 0: + x86emu_fpu_R_fld(X86EMU_FPU_STKTOP, stkelem); + break; + case 1: + x86emu_fpu_R_fxch(X86EMU_FPU_STKTOP, stkelem); + break; + case 2: + switch (rl) { + case 0: + x86emu_fpu_R_nop(); + break; + default: + x86emu_fpu_illegal(); + break; + } + case 3: + x86emu_fpu_R_fstp(X86EMU_FPU_STKTOP, stkelem); + break; + case 4: + switch (rl) { + case 0: + x86emu_fpu_R_fchs(X86EMU_FPU_STKTOP); + break; + case 1: + x86emu_fpu_R_fabs(X86EMU_FPU_STKTOP); + break; + case 4: + x86emu_fpu_R_ftst(X86EMU_FPU_STKTOP); + break; + case 5: + x86emu_fpu_R_fxam(X86EMU_FPU_STKTOP); + break; + default: + /* 2,3,6,7 */ + x86emu_fpu_illegal(); + break; + } + break; + + case 5: + switch (rl) { + case 0: + x86emu_fpu_R_fld1(X86EMU_FPU_STKTOP); + break; + case 1: + x86emu_fpu_R_fldl2t(X86EMU_FPU_STKTOP); + break; + case 2: + x86emu_fpu_R_fldl2e(X86EMU_FPU_STKTOP); + break; + case 3: + x86emu_fpu_R_fldpi(X86EMU_FPU_STKTOP); + break; + case 4: + x86emu_fpu_R_fldlg2(X86EMU_FPU_STKTOP); + break; + case 5: + x86emu_fpu_R_fldln2(X86EMU_FPU_STKTOP); + break; + case 6: + x86emu_fpu_R_fldz(X86EMU_FPU_STKTOP); + break; + default: + /* 7 */ + x86emu_fpu_illegal(); + break; + } + break; + + case 6: + switch (rl) { + case 0: + x86emu_fpu_R_f2xm1(X86EMU_FPU_STKTOP); + break; + case 1: + x86emu_fpu_R_fyl2x(X86EMU_FPU_STKTOP); + break; + case 2: + x86emu_fpu_R_fptan(X86EMU_FPU_STKTOP); + break; + case 3: + x86emu_fpu_R_fpatan(X86EMU_FPU_STKTOP); + break; + case 4: + x86emu_fpu_R_fxtract(X86EMU_FPU_STKTOP); + break; + case 5: + x86emu_fpu_illegal(); + break; + case 6: + x86emu_fpu_R_decstp(); + break; + case 7: + x86emu_fpu_R_incstp(); + break; + } + break; + + case 7: + switch (rl) { + case 0: + x86emu_fpu_R_fprem(X86EMU_FPU_STKTOP); + break; + case 1: + x86emu_fpu_R_fyl2xp1(X86EMU_FPU_STKTOP); + break; + case 2: + x86emu_fpu_R_fsqrt(X86EMU_FPU_STKTOP); + break; + case 3: + x86emu_fpu_illegal(); + break; + case 4: + x86emu_fpu_R_frndint(X86EMU_FPU_STKTOP); + break; + case 5: + x86emu_fpu_R_fscale(X86EMU_FPU_STKTOP); + break; + case 6: + case 7: + default: + x86emu_fpu_illegal(); + break; + } + break; + + default: + switch (rh) { + case 0: + x86emu_fpu_M_fld(X86EMU_FPU_FLOAT, destoffset); + break; + case 1: + x86emu_fpu_illegal(); + break; + case 2: + x86emu_fpu_M_fst(X86EMU_FPU_FLOAT, destoffset); + break; + case 3: + x86emu_fpu_M_fstp(X86EMU_FPU_FLOAT, destoffset); + break; + case 4: + x86emu_fpu_M_fldenv(X86EMU_FPU_WORD, destoffset); + break; + case 5: + x86emu_fpu_M_fldcw(X86EMU_FPU_WORD, destoffset); + break; + case 6: + x86emu_fpu_M_fstenv(X86EMU_FPU_WORD, destoffset); + break; + case 7: + x86emu_fpu_M_fstcw(X86EMU_FPU_WORD, destoffset); + break; + } + } + } +#else + (void)destoffset; + (void)stkelem; +#endif /* X86EMU_FPU_PRESENT */ + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR_NO_TRACE(); +} + +#ifdef X86EMU_DEBUG + +char *x86emu_fpu_op_da_tab[] = { + "FIADD\tDWORD PTR ", "FIMUL\tDWORD PTR ", "FICOM\tDWORD PTR ", + "FICOMP\tDWORD PTR ", + "FISUB\tDWORD PTR ", "FISUBR\tDWORD PTR ", "FIDIV\tDWORD PTR ", + "FIDIVR\tDWORD PTR ", + + "FIADD\tDWORD PTR ", "FIMUL\tDWORD PTR ", "FICOM\tDWORD PTR ", + "FICOMP\tDWORD PTR ", + "FISUB\tDWORD PTR ", "FISUBR\tDWORD PTR ", "FIDIV\tDWORD PTR ", + "FIDIVR\tDWORD PTR ", + + "FIADD\tDWORD PTR ", "FIMUL\tDWORD PTR ", "FICOM\tDWORD PTR ", + "FICOMP\tDWORD PTR ", + "FISUB\tDWORD PTR ", "FISUBR\tDWORD PTR ", "FIDIV\tDWORD PTR ", + "FIDIVR\tDWORD PTR ", + + "ESC_DA ", "ESC_DA ", "ESC_DA ", "ESC_DA ", + "ESC_DA ", "ESC_DA ", "ESC_DA ", "ESC_DA ", +}; + +#endif /* X86EMU_DEBUG */ + +/* opcode=0xda */ +void x86emuOp_esc_coprocess_da(u8 X86EMU_UNUSED(op1)) +{ + int mod, rl, rh; + uint destoffset = 0; + u8 stkelem = 0; + + START_OF_INSTR(); + FETCH_DECODE_MODRM(mod, rh, rl); + DECODE_PRINTINSTR32(x86emu_fpu_op_da_tab, mod, rh, rl); + switch (mod) { + case 0: + destoffset = decode_rm00_address(rl); + DECODE_PRINTF("\n"); + break; + case 1: + destoffset = decode_rm01_address(rl); + DECODE_PRINTF("\n"); + break; + case 2: + destoffset = decode_rm10_address(rl); + DECODE_PRINTF("\n"); + break; + case 3: /* register to register */ + stkelem = (u8)rl; + DECODE_PRINTF2("\tST(%d),ST\n", stkelem); + break; + } +#ifdef X86EMU_FPU_PRESENT + switch (mod) { + case 3: + x86emu_fpu_illegal(); + break; + default: + switch (rh) { + case 0: + x86emu_fpu_M_iadd(X86EMU_FPU_SHORT, destoffset); + break; + case 1: + x86emu_fpu_M_imul(X86EMU_FPU_SHORT, destoffset); + break; + case 2: + x86emu_fpu_M_icom(X86EMU_FPU_SHORT, destoffset); + break; + case 3: + x86emu_fpu_M_icomp(X86EMU_FPU_SHORT, destoffset); + break; + case 4: + x86emu_fpu_M_isub(X86EMU_FPU_SHORT, destoffset); + break; + case 5: + x86emu_fpu_M_isubr(X86EMU_FPU_SHORT, destoffset); + break; + case 6: + x86emu_fpu_M_idiv(X86EMU_FPU_SHORT, destoffset); + break; + case 7: + x86emu_fpu_M_idivr(X86EMU_FPU_SHORT, destoffset); + break; + } + } +#else + (void)destoffset; + (void)stkelem; +#endif + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR_NO_TRACE(); +} + +#ifdef X86EMU_DEBUG + +char *x86emu_fpu_op_db_tab[] = { + "FILD\tDWORD PTR ", "ESC_DB\t19", "FIST\tDWORD PTR ", "FISTP\tDWORD PTR ", + "ESC_DB\t1C", "FLD\tTBYTE PTR ", "ESC_DB\t1E", "FSTP\tTBYTE PTR ", + + "FILD\tDWORD PTR ", "ESC_DB\t19", "FIST\tDWORD PTR ", "FISTP\tDWORD PTR ", + "ESC_DB\t1C", "FLD\tTBYTE PTR ", "ESC_DB\t1E", "FSTP\tTBYTE PTR ", + + "FILD\tDWORD PTR ", "ESC_DB\t19", "FIST\tDWORD PTR ", "FISTP\tDWORD PTR ", + "ESC_DB\t1C", "FLD\tTBYTE PTR ", "ESC_DB\t1E", "FSTP\tTBYTE PTR ", +}; + +#endif /* X86EMU_DEBUG */ + +/* opcode=0xdb */ +void x86emuOp_esc_coprocess_db(u8 X86EMU_UNUSED(op1)) +{ + int mod, rl, rh; + uint destoffset = 0; + + START_OF_INSTR(); + FETCH_DECODE_MODRM(mod, rh, rl); +#ifdef X86EMU_DEBUG + if (mod != 3) { + DECODE_PRINTINSTR32(x86emu_fpu_op_db_tab, mod, rh, rl); + } else if (rh == 4) { /* === 11 10 0 nnn */ + switch (rl) { + case 0: + DECODE_PRINTF("FENI\n"); + break; + case 1: + DECODE_PRINTF("FDISI\n"); + break; + case 2: + DECODE_PRINTF("FCLEX\n"); + break; + case 3: + DECODE_PRINTF("FINIT\n"); + break; + } + } else { + DECODE_PRINTF2("ESC_DB %0x\n", (mod << 6) + (rh << 3) + (rl)); + } +#endif /* X86EMU_DEBUG */ + switch (mod) { + case 0: + destoffset = decode_rm00_address(rl); + break; + case 1: + destoffset = decode_rm01_address(rl); + break; + case 2: + destoffset = decode_rm10_address(rl); + break; + case 3: /* register to register */ + break; + } +#ifdef X86EMU_FPU_PRESENT + /* execute */ + switch (mod) { + case 3: + switch (rh) { + case 4: + switch (rl) { + case 0: + x86emu_fpu_R_feni(); + break; + case 1: + x86emu_fpu_R_fdisi(); + break; + case 2: + x86emu_fpu_R_fclex(); + break; + case 3: + x86emu_fpu_R_finit(); + break; + default: + x86emu_fpu_illegal(); + break; + } + break; + default: + x86emu_fpu_illegal(); + break; + } + break; + default: + switch (rh) { + case 0: + x86emu_fpu_M_fild(X86EMU_FPU_SHORT, destoffset); + break; + case 1: + x86emu_fpu_illegal(); + break; + case 2: + x86emu_fpu_M_fist(X86EMU_FPU_SHORT, destoffset); + break; + case 3: + x86emu_fpu_M_fistp(X86EMU_FPU_SHORT, destoffset); + break; + case 4: + x86emu_fpu_illegal(); + break; + case 5: + x86emu_fpu_M_fld(X86EMU_FPU_LDBL, destoffset); + break; + case 6: + x86emu_fpu_illegal(); + break; + case 7: + x86emu_fpu_M_fstp(X86EMU_FPU_LDBL, destoffset); + break; + } + } +#else + (void)destoffset; +#endif + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR_NO_TRACE(); +} + +#ifdef X86EMU_DEBUG +char *x86emu_fpu_op_dc_tab[] = { + "FADD\tQWORD PTR ", "FMUL\tQWORD PTR ", "FCOM\tQWORD PTR ", + "FCOMP\tQWORD PTR ", + "FSUB\tQWORD PTR ", "FSUBR\tQWORD PTR ", "FDIV\tQWORD PTR ", + "FDIVR\tQWORD PTR ", + + "FADD\tQWORD PTR ", "FMUL\tQWORD PTR ", "FCOM\tQWORD PTR ", + "FCOMP\tQWORD PTR ", + "FSUB\tQWORD PTR ", "FSUBR\tQWORD PTR ", "FDIV\tQWORD PTR ", + "FDIVR\tQWORD PTR ", + + "FADD\tQWORD PTR ", "FMUL\tQWORD PTR ", "FCOM\tQWORD PTR ", + "FCOMP\tQWORD PTR ", + "FSUB\tQWORD PTR ", "FSUBR\tQWORD PTR ", "FDIV\tQWORD PTR ", + "FDIVR\tQWORD PTR ", + + "FADD\t", "FMUL\t", "FCOM\t", "FCOMP\t", + "FSUBR\t", "FSUB\t", "FDIVR\t", "FDIV\t", +}; +#endif /* X86EMU_DEBUG */ + +/* opcode=0xdc */ +void x86emuOp_esc_coprocess_dc(u8 X86EMU_UNUSED(op1)) +{ + int mod, rl, rh; + uint destoffset = 0; + u8 stkelem = 0; + + START_OF_INSTR(); + FETCH_DECODE_MODRM(mod, rh, rl); + DECODE_PRINTINSTR32(x86emu_fpu_op_dc_tab, mod, rh, rl); + switch (mod) { + case 0: + destoffset = decode_rm00_address(rl); + DECODE_PRINTF("\n"); + break; + case 1: + destoffset = decode_rm01_address(rl); + DECODE_PRINTF("\n"); + break; + case 2: + destoffset = decode_rm10_address(rl); + DECODE_PRINTF("\n"); + break; + case 3: /* register to register */ + stkelem = (u8)rl; + DECODE_PRINTF2("\tST(%d),ST\n", stkelem); + break; + } +#ifdef X86EMU_FPU_PRESENT + /* execute */ + switch (mod) { + case 3: + switch (rh) { + case 0: + x86emu_fpu_R_fadd(stkelem, X86EMU_FPU_STKTOP); + break; + case 1: + x86emu_fpu_R_fmul(stkelem, X86EMU_FPU_STKTOP); + break; + case 2: + x86emu_fpu_R_fcom(stkelem, X86EMU_FPU_STKTOP); + break; + case 3: + x86emu_fpu_R_fcomp(stkelem, X86EMU_FPU_STKTOP); + break; + case 4: + x86emu_fpu_R_fsubr(stkelem, X86EMU_FPU_STKTOP); + break; + case 5: + x86emu_fpu_R_fsub(stkelem, X86EMU_FPU_STKTOP); + break; + case 6: + x86emu_fpu_R_fdivr(stkelem, X86EMU_FPU_STKTOP); + break; + case 7: + x86emu_fpu_R_fdiv(stkelem, X86EMU_FPU_STKTOP); + break; + } + break; + default: + switch (rh) { + case 0: + x86emu_fpu_M_fadd(X86EMU_FPU_DOUBLE, destoffset); + break; + case 1: + x86emu_fpu_M_fmul(X86EMU_FPU_DOUBLE, destoffset); + break; + case 2: + x86emu_fpu_M_fcom(X86EMU_FPU_DOUBLE, destoffset); + break; + case 3: + x86emu_fpu_M_fcomp(X86EMU_FPU_DOUBLE, destoffset); + break; + case 4: + x86emu_fpu_M_fsub(X86EMU_FPU_DOUBLE, destoffset); + break; + case 5: + x86emu_fpu_M_fsubr(X86EMU_FPU_DOUBLE, destoffset); + break; + case 6: + x86emu_fpu_M_fdiv(X86EMU_FPU_DOUBLE, destoffset); + break; + case 7: + x86emu_fpu_M_fdivr(X86EMU_FPU_DOUBLE, destoffset); + break; + } + } +#else + (void)destoffset; + (void)stkelem; +#endif + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR_NO_TRACE(); +} + +#ifdef X86EMU_DEBUG + +static char *x86emu_fpu_op_dd_tab[] = { + "FLD\tQWORD PTR ", "ESC_DD\t29,", "FST\tQWORD PTR ", "FSTP\tQWORD PTR ", + "FRSTOR\t", "ESC_DD\t2D,", "FSAVE\t", "FSTSW\t", + + "FLD\tQWORD PTR ", "ESC_DD\t29,", "FST\tQWORD PTR ", "FSTP\tQWORD PTR ", + "FRSTOR\t", "ESC_DD\t2D,", "FSAVE\t", "FSTSW\t", + + "FLD\tQWORD PTR ", "ESC_DD\t29,", "FST\tQWORD PTR ", "FSTP\tQWORD PTR ", + "FRSTOR\t", "ESC_DD\t2D,", "FSAVE\t", "FSTSW\t", + + "FFREE\t", "FXCH\t", "FST\t", "FSTP\t", + "ESC_DD\t2C,", "ESC_DD\t2D,", "ESC_DD\t2E,", "ESC_DD\t2F,", +}; + +#endif /* X86EMU_DEBUG */ + +/* opcode=0xdd */ +void x86emuOp_esc_coprocess_dd(u8 X86EMU_UNUSED(op1)) +{ + int mod, rl, rh; + uint destoffset = 0; + u8 stkelem = 0; + + START_OF_INSTR(); + FETCH_DECODE_MODRM(mod, rh, rl); + DECODE_PRINTINSTR32(x86emu_fpu_op_dd_tab, mod, rh, rl); + switch (mod) { + case 0: + destoffset = decode_rm00_address(rl); + DECODE_PRINTF("\n"); + break; + case 1: + destoffset = decode_rm01_address(rl); + DECODE_PRINTF("\n"); + break; + case 2: + destoffset = decode_rm10_address(rl); + DECODE_PRINTF("\n"); + break; + case 3: /* register to register */ + stkelem = (u8)rl; + DECODE_PRINTF2("\tST(%d),ST\n", stkelem); + break; + } +#ifdef X86EMU_FPU_PRESENT + switch (mod) { + case 3: + switch (rh) { + case 0: + x86emu_fpu_R_ffree(stkelem); + break; + case 1: + x86emu_fpu_R_fxch(stkelem); + break; + case 2: + x86emu_fpu_R_fst(stkelem); /* register version */ + break; + case 3: + x86emu_fpu_R_fstp(stkelem); /* register version */ + break; + default: + x86emu_fpu_illegal(); + break; + } + break; + default: + switch (rh) { + case 0: + x86emu_fpu_M_fld(X86EMU_FPU_DOUBLE, destoffset); + break; + case 1: + x86emu_fpu_illegal(); + break; + case 2: + x86emu_fpu_M_fst(X86EMU_FPU_DOUBLE, destoffset); + break; + case 3: + x86emu_fpu_M_fstp(X86EMU_FPU_DOUBLE, destoffset); + break; + case 4: + x86emu_fpu_M_frstor(X86EMU_FPU_WORD, destoffset); + break; + case 5: + x86emu_fpu_illegal(); + break; + case 6: + x86emu_fpu_M_fsave(X86EMU_FPU_WORD, destoffset); + break; + case 7: + x86emu_fpu_M_fstsw(X86EMU_FPU_WORD, destoffset); + break; + } + } +#else + (void)destoffset; + (void)stkelem; +#endif + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR_NO_TRACE(); +} + +#ifdef X86EMU_DEBUG + +static char *x86emu_fpu_op_de_tab[] = +{ + "FIADD\tWORD PTR ", "FIMUL\tWORD PTR ", "FICOM\tWORD PTR ", + "FICOMP\tWORD PTR ", + "FISUB\tWORD PTR ", "FISUBR\tWORD PTR ", "FIDIV\tWORD PTR ", + "FIDIVR\tWORD PTR ", + + "FIADD\tWORD PTR ", "FIMUL\tWORD PTR ", "FICOM\tWORD PTR ", + "FICOMP\tWORD PTR ", + "FISUB\tWORD PTR ", "FISUBR\tWORD PTR ", "FIDIV\tWORD PTR ", + "FIDIVR\tWORD PTR ", + + "FIADD\tWORD PTR ", "FIMUL\tWORD PTR ", "FICOM\tWORD PTR ", + "FICOMP\tWORD PTR ", + "FISUB\tWORD PTR ", "FISUBR\tWORD PTR ", "FIDIV\tWORD PTR ", + "FIDIVR\tWORD PTR ", + + "FADDP\t", "FMULP\t", "FCOMP\t", "FCOMPP\t", + "FSUBRP\t", "FSUBP\t", "FDIVRP\t", "FDIVP\t", +}; + +#endif /* X86EMU_DEBUG */ + +/* opcode=0xde */ +void x86emuOp_esc_coprocess_de(u8 X86EMU_UNUSED(op1)) +{ + int mod, rl, rh; + uint destoffset = 0; + u8 stkelem = 0; + + START_OF_INSTR(); + FETCH_DECODE_MODRM(mod, rh, rl); + DECODE_PRINTINSTR32(x86emu_fpu_op_de_tab, mod, rh, rl); + switch (mod) { + case 0: + destoffset = decode_rm00_address(rl); + DECODE_PRINTF("\n"); + break; + case 1: + destoffset = decode_rm01_address(rl); + DECODE_PRINTF("\n"); + break; + case 2: + destoffset = decode_rm10_address(rl); + DECODE_PRINTF("\n"); + break; + case 3: /* register to register */ + stkelem = (u8)rl; + DECODE_PRINTF2("\tST(%d),ST\n", stkelem); + break; + } +#ifdef X86EMU_FPU_PRESENT + switch (mod) { + case 3: + switch (rh) { + case 0: + x86emu_fpu_R_faddp(stkelem, X86EMU_FPU_STKTOP); + break; + case 1: + x86emu_fpu_R_fmulp(stkelem, X86EMU_FPU_STKTOP); + break; + case 2: + x86emu_fpu_R_fcomp(stkelem, X86EMU_FPU_STKTOP); + break; + case 3: + if (stkelem == 1) + x86emu_fpu_R_fcompp(stkelem, X86EMU_FPU_STKTOP); + else + x86emu_fpu_illegal(); + break; + case 4: + x86emu_fpu_R_fsubrp(stkelem, X86EMU_FPU_STKTOP); + break; + case 5: + x86emu_fpu_R_fsubp(stkelem, X86EMU_FPU_STKTOP); + break; + case 6: + x86emu_fpu_R_fdivrp(stkelem, X86EMU_FPU_STKTOP); + break; + case 7: + x86emu_fpu_R_fdivp(stkelem, X86EMU_FPU_STKTOP); + break; + } + break; + default: + switch (rh) { + case 0: + x86emu_fpu_M_fiadd(X86EMU_FPU_WORD, destoffset); + break; + case 1: + x86emu_fpu_M_fimul(X86EMU_FPU_WORD, destoffset); + break; + case 2: + x86emu_fpu_M_ficom(X86EMU_FPU_WORD, destoffset); + break; + case 3: + x86emu_fpu_M_ficomp(X86EMU_FPU_WORD, destoffset); + break; + case 4: + x86emu_fpu_M_fisub(X86EMU_FPU_WORD, destoffset); + break; + case 5: + x86emu_fpu_M_fisubr(X86EMU_FPU_WORD, destoffset); + break; + case 6: + x86emu_fpu_M_fidiv(X86EMU_FPU_WORD, destoffset); + break; + case 7: + x86emu_fpu_M_fidivr(X86EMU_FPU_WORD, destoffset); + break; + } + } +#else + (void)destoffset; + (void)stkelem; +#endif + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR_NO_TRACE(); +} + +#ifdef X86EMU_DEBUG + +static char *x86emu_fpu_op_df_tab[] = { + /* mod == 00 */ + "FILD\tWORD PTR ", "ESC_DF\t39\n", "FIST\tWORD PTR ", "FISTP\tWORD PTR ", + "FBLD\tTBYTE PTR ", "FILD\tQWORD PTR ", "FBSTP\tTBYTE PTR ", + "FISTP\tQWORD PTR ", + + /* mod == 01 */ + "FILD\tWORD PTR ", "ESC_DF\t39 ", "FIST\tWORD PTR ", "FISTP\tWORD PTR ", + "FBLD\tTBYTE PTR ", "FILD\tQWORD PTR ", "FBSTP\tTBYTE PTR ", + "FISTP\tQWORD PTR ", + + /* mod == 10 */ + "FILD\tWORD PTR ", "ESC_DF\t39 ", "FIST\tWORD PTR ", "FISTP\tWORD PTR ", + "FBLD\tTBYTE PTR ", "FILD\tQWORD PTR ", "FBSTP\tTBYTE PTR ", + "FISTP\tQWORD PTR ", + + /* mod == 11 */ + "FFREE\t", "FXCH\t", "FST\t", "FSTP\t", + "ESC_DF\t3C,", "ESC_DF\t3D,", "ESC_DF\t3E,", "ESC_DF\t3F," +}; + +#endif /* X86EMU_DEBUG */ + +/* opcode=0xdf */ +void x86emuOp_esc_coprocess_df(u8 X86EMU_UNUSED(op1)) +{ + int mod, rl, rh; + uint destoffset = 0; + u8 stkelem = 0; + + START_OF_INSTR(); + FETCH_DECODE_MODRM(mod, rh, rl); + DECODE_PRINTINSTR32(x86emu_fpu_op_df_tab, mod, rh, rl); + switch (mod) { + case 0: + destoffset = decode_rm00_address(rl); + DECODE_PRINTF("\n"); + break; + case 1: + destoffset = decode_rm01_address(rl); + DECODE_PRINTF("\n"); + break; + case 2: + destoffset = decode_rm10_address(rl); + DECODE_PRINTF("\n"); + break; + case 3: /* register to register */ + stkelem = (u8)rl; + DECODE_PRINTF2("\tST(%d)\n", stkelem); + break; + } +#ifdef X86EMU_FPU_PRESENT + switch (mod) { + case 3: + switch (rh) { + case 0: + x86emu_fpu_R_ffree(stkelem); + break; + case 1: + x86emu_fpu_R_fxch(stkelem); + break; + case 2: + x86emu_fpu_R_fst(stkelem); /* register version */ + break; + case 3: + x86emu_fpu_R_fstp(stkelem); /* register version */ + break; + default: + x86emu_fpu_illegal(); + break; + } + break; + default: + switch (rh) { + case 0: + x86emu_fpu_M_fild(X86EMU_FPU_WORD, destoffset); + break; + case 1: + x86emu_fpu_illegal(); + break; + case 2: + x86emu_fpu_M_fist(X86EMU_FPU_WORD, destoffset); + break; + case 3: + x86emu_fpu_M_fistp(X86EMU_FPU_WORD, destoffset); + break; + case 4: + x86emu_fpu_M_fbld(X86EMU_FPU_BSD, destoffset); + break; + case 5: + x86emu_fpu_M_fild(X86EMU_FPU_LONG, destoffset); + break; + case 6: + x86emu_fpu_M_fbstp(X86EMU_FPU_BSD, destoffset); + break; + case 7: + x86emu_fpu_M_fistp(X86EMU_FPU_LONG, destoffset); + break; + } + } +#else + (void)destoffset; + (void)stkelem; +#endif + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR_NO_TRACE(); +} diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/arch/nvalloc/unix/x86emu/ops.c nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/arch/nvalloc/unix/x86emu/ops.c --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/arch/nvalloc/unix/x86emu/ops.c 1970-01-01 00:00:00.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/arch/nvalloc/unix/x86emu/ops.c 2024-03-05 22:12:51.000000000 +0000 @@ -0,0 +1,11761 @@ +/**************************************************************************** +* +* Realmode X86 Emulator Library +* +* Copyright (C) 1996-1999 SciTech Software, Inc. +* Copyright (C) David Mosberger-Tang +* Copyright (C) 1999 Egbert Eich +* +* ======================================================================== +* +* Permission to use, copy, modify, distribute, and sell this software and +* its documentation for any purpose is hereby granted without fee, +* provided that the above copyright notice appear in all copies and that +* both that copyright notice and this permission notice appear in +* supporting documentation, and that the name of the authors not be used +* in advertising or publicity pertaining to distribution of the software +* without specific, written prior permission. The authors makes no +* representations about the suitability of this software for any purpose. +* It is provided "as is" without express or implied warranty. +* +* THE AUTHORS DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOFTWARE, +* INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO +* EVENT SHALL THE AUTHORS BE LIABLE FOR ANY SPECIAL, INDIRECT OR +* CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF +* USE, DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR +* OTHER TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR +* PERFORMANCE OF THIS SOFTWARE. +* +* ======================================================================== +* +* Language: ANSI C +* Environment: Any +* Developer: Kendall Bennett +* +* Description: This file includes subroutines to implement the decoding +* and emulation of all the x86 processor instructions. +* +* There are approximately 250 subroutines in here, which correspond +* to the 256 byte-"opcodes" found on the 8086. The table which +* dispatches this is found in the files optab.[ch]. +* +* Each opcode proc has a comment preceeding it which gives it's table +* address. Several opcodes are missing (undefined) in the table. +* +* Each proc includes information for decoding (DECODE_PRINTF and +* DECODE_PRINTF2), debugging (TRACE_REGS, SINGLE_STEP), and misc +* functions (START_OF_INSTR, END_OF_INSTR). +* +* Many of the procedures are *VERY* similar in coding. This has +* allowed for a very large amount of code to be generated in a fairly +* short amount of time (i.e. cut, paste, and modify). The result is +* that much of the code below could have been folded into subroutines +* for a large reduction in size of this file. The downside would be +* that there would be a penalty in execution speed. The file could +* also have been *MUCH* larger by inlining certain functions which +* were called. This could have resulted even faster execution. The +* prime directive I used to decide whether to inline the code or to +* modularize it, was basically: 1) no unnecessary subroutine calls, +* 2) no routines more than about 200 lines in size, and 3) modularize +* any code that I might not get right the first time. The fetch_* +* subroutines fall into the latter category. The The decode_* fall +* into the second category. The coding of the "switch(mod){ .... }" +* in many of the subroutines below falls into the first category. +* Especially, the coding of {add,and,or,sub,...}_{byte,word} +* subroutines are an especially glaring case of the third guideline. +* Since so much of the code is cloned from other modules (compare +* opcode #00 to opcode #01), making the basic operations subroutine +* calls is especially important; otherwise mistakes in coding an +* "add" would represent a nightmare in maintenance. +* +****************************************************************************/ + +#include "x86emu/x86emui.h" + +/*----------------------------- Implementation ----------------------------*/ + +/**************************************************************************** +PARAMETERS: +op1 - Instruction op code + +REMARKS: +Handles illegal opcodes. +****************************************************************************/ +static void x86emuOp_illegal_op( + u8 op1) +{ + START_OF_INSTR(); + if (M.x86.R_SP != 0) { + DECODE_PRINTF("ILLEGAL X86 OPCODE\n"); + TRACE_REGS(); + DB( NV_PRINTF(LEVEL_INFO, "%04x:%04x: %02X ILLEGAL X86 OPCODE!\n", + M.x86.R_CS, M.x86.R_IP - 1, op1);) + HALT_SYS(); + } + else { + /* If we get here, it means the stack pointer is back to zero + * so we are just returning from an emulator service call + * so therte is no need to display an error message. We trap + * the emulator with an 0xF1 opcode to finish the service + * call. + */ + X86EMU_halt_sys(); + } + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x00 +****************************************************************************/ +static void x86emuOp_add_byte_RM_R(u8 X86EMU_UNUSED(op1)) +{ + int mod, rl, rh; + uint destoffset; + u8 *destreg, *srcreg; + u8 destval; + + START_OF_INSTR(); + DECODE_PRINTF("ADD\t"); + FETCH_DECODE_MODRM(mod, rh, rl); + switch (mod) { + case 0: + destoffset = decode_rm00_address(rl); + DECODE_PRINTF(","); + destval = fetch_data_byte(destoffset); + srcreg = DECODE_RM_BYTE_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + destval = add_byte(destval, *srcreg); + store_data_byte(destoffset, destval); + break; + case 1: + destoffset = decode_rm01_address(rl); + DECODE_PRINTF(","); + destval = fetch_data_byte(destoffset); + srcreg = DECODE_RM_BYTE_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + destval = add_byte(destval, *srcreg); + store_data_byte(destoffset, destval); + break; + case 2: + destoffset = decode_rm10_address(rl); + DECODE_PRINTF(","); + destval = fetch_data_byte(destoffset); + srcreg = DECODE_RM_BYTE_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + destval = add_byte(destval, *srcreg); + store_data_byte(destoffset, destval); + break; + case 3: /* register to register */ + destreg = DECODE_RM_BYTE_REGISTER(rl); + DECODE_PRINTF(","); + srcreg = DECODE_RM_BYTE_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = add_byte(*destreg, *srcreg); + break; + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x01 +****************************************************************************/ +static void x86emuOp_add_word_RM_R(u8 X86EMU_UNUSED(op1)) +{ + int mod, rl, rh; + uint destoffset; + + START_OF_INSTR(); + DECODE_PRINTF("ADD\t"); + FETCH_DECODE_MODRM(mod, rh, rl); + switch (mod) { + case 0: + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 destval; + u32 *srcreg; + + destoffset = decode_rm00_address(rl); + DECODE_PRINTF(","); + destval = fetch_data_long(destoffset); + srcreg = DECODE_RM_LONG_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + destval = add_long(destval, *srcreg); + store_data_long(destoffset, destval); + } else { + u16 destval; + u16 *srcreg; + + destoffset = decode_rm00_address(rl); + DECODE_PRINTF(","); + destval = fetch_data_word(destoffset); + srcreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + destval = add_word(destval, *srcreg); + store_data_word(destoffset, destval); + } + break; + case 1: + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 destval; + u32 *srcreg; + + destoffset = decode_rm01_address(rl); + DECODE_PRINTF(","); + destval = fetch_data_long(destoffset); + srcreg = DECODE_RM_LONG_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + destval = add_long(destval, *srcreg); + store_data_long(destoffset, destval); + } else { + u16 destval; + u16 *srcreg; + + destoffset = decode_rm01_address(rl); + DECODE_PRINTF(","); + destval = fetch_data_word(destoffset); + srcreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + destval = add_word(destval, *srcreg); + store_data_word(destoffset, destval); + } + break; + case 2: + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 destval; + u32 *srcreg; + + destoffset = decode_rm10_address(rl); + DECODE_PRINTF(","); + destval = fetch_data_long(destoffset); + srcreg = DECODE_RM_LONG_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + destval = add_long(destval, *srcreg); + store_data_long(destoffset, destval); + } else { + u16 destval; + u16 *srcreg; + + destoffset = decode_rm10_address(rl); + DECODE_PRINTF(","); + destval = fetch_data_word(destoffset); + srcreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + destval = add_word(destval, *srcreg); + store_data_word(destoffset, destval); + } + break; + case 3: /* register to register */ + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 *destreg,*srcreg; + + destreg = DECODE_RM_LONG_REGISTER(rl); + DECODE_PRINTF(","); + srcreg = DECODE_RM_LONG_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = add_long(*destreg, *srcreg); + } else { + u16 *destreg,*srcreg; + + destreg = DECODE_RM_WORD_REGISTER(rl); + DECODE_PRINTF(","); + srcreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = add_word(*destreg, *srcreg); + } + break; + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x02 +****************************************************************************/ +static void x86emuOp_add_byte_R_RM(u8 X86EMU_UNUSED(op1)) +{ + int mod, rl, rh; + u8 *destreg, *srcreg; + uint srcoffset; + u8 srcval; + + START_OF_INSTR(); + DECODE_PRINTF("ADD\t"); + FETCH_DECODE_MODRM(mod, rh, rl); + switch (mod) { + case 0: + destreg = DECODE_RM_BYTE_REGISTER(rh); + DECODE_PRINTF(","); + srcoffset = decode_rm00_address(rl); + srcval = fetch_data_byte(srcoffset); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = add_byte(*destreg, srcval); + break; + case 1: + destreg = DECODE_RM_BYTE_REGISTER(rh); + DECODE_PRINTF(","); + srcoffset = decode_rm01_address(rl); + srcval = fetch_data_byte(srcoffset); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = add_byte(*destreg, srcval); + break; + case 2: + destreg = DECODE_RM_BYTE_REGISTER(rh); + DECODE_PRINTF(","); + srcoffset = decode_rm10_address(rl); + srcval = fetch_data_byte(srcoffset); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = add_byte(*destreg, srcval); + break; + case 3: /* register to register */ + destreg = DECODE_RM_BYTE_REGISTER(rh); + DECODE_PRINTF(","); + srcreg = DECODE_RM_BYTE_REGISTER(rl); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = add_byte(*destreg, *srcreg); + break; + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x03 +****************************************************************************/ +static void x86emuOp_add_word_R_RM(u8 X86EMU_UNUSED(op1)) +{ + int mod, rl, rh; + uint srcoffset; + + START_OF_INSTR(); + DECODE_PRINTF("ADD\t"); + FETCH_DECODE_MODRM(mod, rh, rl); + switch (mod) { + case 0: + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 *destreg; + u32 srcval; + + destreg = DECODE_RM_LONG_REGISTER(rh); + DECODE_PRINTF(","); + srcoffset = decode_rm00_address(rl); + srcval = fetch_data_long(srcoffset); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = add_long(*destreg, srcval); + } else { + u16 *destreg; + u16 srcval; + + destreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF(","); + srcoffset = decode_rm00_address(rl); + srcval = fetch_data_word(srcoffset); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = add_word(*destreg, srcval); + } + break; + case 1: + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 *destreg; + u32 srcval; + + destreg = DECODE_RM_LONG_REGISTER(rh); + DECODE_PRINTF(","); + srcoffset = decode_rm01_address(rl); + srcval = fetch_data_long(srcoffset); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = add_long(*destreg, srcval); + } else { + u16 *destreg; + u16 srcval; + + destreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF(","); + srcoffset = decode_rm01_address(rl); + srcval = fetch_data_word(srcoffset); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = add_word(*destreg, srcval); + } + break; + case 2: + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 *destreg; + u32 srcval; + + destreg = DECODE_RM_LONG_REGISTER(rh); + DECODE_PRINTF(","); + srcoffset = decode_rm10_address(rl); + srcval = fetch_data_long(srcoffset); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = add_long(*destreg, srcval); + } else { + u16 *destreg; + u16 srcval; + + destreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF(","); + srcoffset = decode_rm10_address(rl); + srcval = fetch_data_word(srcoffset); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = add_word(*destreg, srcval); + } + break; + case 3: /* register to register */ + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 *destreg,*srcreg; + + destreg = DECODE_RM_LONG_REGISTER(rh); + DECODE_PRINTF(","); + srcreg = DECODE_RM_LONG_REGISTER(rl); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = add_long(*destreg, *srcreg); + } else { + u16 *destreg,*srcreg; + + destreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF(","); + srcreg = DECODE_RM_WORD_REGISTER(rl); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = add_word(*destreg, *srcreg); + } + break; + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x04 +****************************************************************************/ +static void x86emuOp_add_byte_AL_IMM(u8 X86EMU_UNUSED(op1)) +{ + u8 srcval; + + START_OF_INSTR(); + DECODE_PRINTF("ADD\tAL,"); + srcval = fetch_byte_imm(); + DECODE_PRINTF2("%x\n", srcval); + TRACE_AND_STEP(); + M.x86.R_AL = add_byte(M.x86.R_AL, srcval); + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x05 +****************************************************************************/ +static void x86emuOp_add_word_AX_IMM(u8 X86EMU_UNUSED(op1)) +{ + u32 srcval; + + START_OF_INSTR(); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + DECODE_PRINTF("ADD\tEAX,"); + srcval = fetch_long_imm(); + } else { + DECODE_PRINTF("ADD\tAX,"); + srcval = fetch_word_imm(); + } + DECODE_PRINTF2("%x\n", srcval); + TRACE_AND_STEP(); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + M.x86.R_EAX = add_long(M.x86.R_EAX, srcval); + } else { + M.x86.R_AX = add_word(M.x86.R_AX, (u16)srcval); + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x06 +****************************************************************************/ +static void x86emuOp_push_ES(u8 X86EMU_UNUSED(op1)) +{ + START_OF_INSTR(); + DECODE_PRINTF("PUSH\tES\n"); + TRACE_AND_STEP(); + push_word(M.x86.R_ES); + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x07 +****************************************************************************/ +static void x86emuOp_pop_ES(u8 X86EMU_UNUSED(op1)) +{ + START_OF_INSTR(); + DECODE_PRINTF("POP\tES\n"); + TRACE_AND_STEP(); + M.x86.R_ES = pop_word(); + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x08 +****************************************************************************/ +static void x86emuOp_or_byte_RM_R(u8 X86EMU_UNUSED(op1)) +{ + int mod, rl, rh; + u8 *destreg, *srcreg; + uint destoffset; + u8 destval; + + START_OF_INSTR(); + DECODE_PRINTF("OR\t"); + FETCH_DECODE_MODRM(mod, rh, rl); + switch (mod) { + case 0: + destoffset = decode_rm00_address(rl); + DECODE_PRINTF(","); + destval = fetch_data_byte(destoffset); + srcreg = DECODE_RM_BYTE_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + destval = or_byte(destval, *srcreg); + store_data_byte(destoffset, destval); + break; + case 1: + destoffset = decode_rm01_address(rl); + DECODE_PRINTF(","); + destval = fetch_data_byte(destoffset); + srcreg = DECODE_RM_BYTE_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + destval = or_byte(destval, *srcreg); + store_data_byte(destoffset, destval); + break; + case 2: + destoffset = decode_rm10_address(rl); + DECODE_PRINTF(","); + destval = fetch_data_byte(destoffset); + srcreg = DECODE_RM_BYTE_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + destval = or_byte(destval, *srcreg); + store_data_byte(destoffset, destval); + break; + case 3: /* register to register */ + destreg = DECODE_RM_BYTE_REGISTER(rl); + DECODE_PRINTF(","); + srcreg = DECODE_RM_BYTE_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = or_byte(*destreg, *srcreg); + break; + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x09 +****************************************************************************/ +static void x86emuOp_or_word_RM_R(u8 X86EMU_UNUSED(op1)) +{ + int mod, rl, rh; + uint destoffset; + + START_OF_INSTR(); + DECODE_PRINTF("OR\t"); + FETCH_DECODE_MODRM(mod, rh, rl); + switch (mod) { + case 0: + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 destval; + u32 *srcreg; + + destoffset = decode_rm00_address(rl); + DECODE_PRINTF(","); + destval = fetch_data_long(destoffset); + srcreg = DECODE_RM_LONG_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + destval = or_long(destval, *srcreg); + store_data_long(destoffset, destval); + } else { + u16 destval; + u16 *srcreg; + + destoffset = decode_rm00_address(rl); + DECODE_PRINTF(","); + destval = fetch_data_word(destoffset); + srcreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + destval = or_word(destval, *srcreg); + store_data_word(destoffset, destval); + } + break; + case 1: + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 destval; + u32 *srcreg; + + destoffset = decode_rm01_address(rl); + DECODE_PRINTF(","); + destval = fetch_data_long(destoffset); + srcreg = DECODE_RM_LONG_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + destval = or_long(destval, *srcreg); + store_data_long(destoffset, destval); + } else { + u16 destval; + u16 *srcreg; + + destoffset = decode_rm01_address(rl); + DECODE_PRINTF(","); + destval = fetch_data_word(destoffset); + srcreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + destval = or_word(destval, *srcreg); + store_data_word(destoffset, destval); + } + break; + case 2: + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 destval; + u32 *srcreg; + + destoffset = decode_rm10_address(rl); + DECODE_PRINTF(","); + destval = fetch_data_long(destoffset); + srcreg = DECODE_RM_LONG_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + destval = or_long(destval, *srcreg); + store_data_long(destoffset, destval); + } else { + u16 destval; + u16 *srcreg; + + destoffset = decode_rm10_address(rl); + DECODE_PRINTF(","); + destval = fetch_data_word(destoffset); + srcreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + destval = or_word(destval, *srcreg); + store_data_word(destoffset, destval); + } + break; + case 3: /* register to register */ + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 *destreg,*srcreg; + + destreg = DECODE_RM_LONG_REGISTER(rl); + DECODE_PRINTF(","); + srcreg = DECODE_RM_LONG_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = or_long(*destreg, *srcreg); + } else { + u16 *destreg,*srcreg; + + destreg = DECODE_RM_WORD_REGISTER(rl); + DECODE_PRINTF(","); + srcreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = or_word(*destreg, *srcreg); + } + break; + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x0a +****************************************************************************/ +static void x86emuOp_or_byte_R_RM(u8 X86EMU_UNUSED(op1)) +{ + int mod, rl, rh; + u8 *destreg, *srcreg; + uint srcoffset; + u8 srcval; + + START_OF_INSTR(); + DECODE_PRINTF("OR\t"); + FETCH_DECODE_MODRM(mod, rh, rl); + switch (mod) { + case 0: + destreg = DECODE_RM_BYTE_REGISTER(rh); + DECODE_PRINTF(","); + srcoffset = decode_rm00_address(rl); + srcval = fetch_data_byte(srcoffset); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = or_byte(*destreg, srcval); + break; + case 1: + destreg = DECODE_RM_BYTE_REGISTER(rh); + DECODE_PRINTF(","); + srcoffset = decode_rm01_address(rl); + srcval = fetch_data_byte(srcoffset); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = or_byte(*destreg, srcval); + break; + case 2: + destreg = DECODE_RM_BYTE_REGISTER(rh); + DECODE_PRINTF(","); + srcoffset = decode_rm10_address(rl); + srcval = fetch_data_byte(srcoffset); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = or_byte(*destreg, srcval); + break; + case 3: /* register to register */ + destreg = DECODE_RM_BYTE_REGISTER(rh); + DECODE_PRINTF(","); + srcreg = DECODE_RM_BYTE_REGISTER(rl); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = or_byte(*destreg, *srcreg); + break; + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x0b +****************************************************************************/ +static void x86emuOp_or_word_R_RM(u8 X86EMU_UNUSED(op1)) +{ + int mod, rl, rh; + uint srcoffset; + + START_OF_INSTR(); + DECODE_PRINTF("OR\t"); + FETCH_DECODE_MODRM(mod, rh, rl); + switch (mod) { + case 0: + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 *destreg; + u32 srcval; + + destreg = DECODE_RM_LONG_REGISTER(rh); + DECODE_PRINTF(","); + srcoffset = decode_rm00_address(rl); + srcval = fetch_data_long(srcoffset); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = or_long(*destreg, srcval); + } else { + u16 *destreg; + u16 srcval; + + destreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF(","); + srcoffset = decode_rm00_address(rl); + srcval = fetch_data_word(srcoffset); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = or_word(*destreg, srcval); + } + break; + case 1: + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 *destreg; + u32 srcval; + + destreg = DECODE_RM_LONG_REGISTER(rh); + DECODE_PRINTF(","); + srcoffset = decode_rm01_address(rl); + srcval = fetch_data_long(srcoffset); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = or_long(*destreg, srcval); + } else { + u16 *destreg; + u16 srcval; + + destreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF(","); + srcoffset = decode_rm01_address(rl); + srcval = fetch_data_word(srcoffset); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = or_word(*destreg, srcval); + } + break; + case 2: + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 *destreg; + u32 srcval; + + destreg = DECODE_RM_LONG_REGISTER(rh); + DECODE_PRINTF(","); + srcoffset = decode_rm10_address(rl); + srcval = fetch_data_long(srcoffset); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = or_long(*destreg, srcval); + } else { + u16 *destreg; + u16 srcval; + + destreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF(","); + srcoffset = decode_rm10_address(rl); + srcval = fetch_data_word(srcoffset); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = or_word(*destreg, srcval); + } + break; + case 3: /* register to register */ + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 *destreg,*srcreg; + + destreg = DECODE_RM_LONG_REGISTER(rh); + DECODE_PRINTF(","); + srcreg = DECODE_RM_LONG_REGISTER(rl); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = or_long(*destreg, *srcreg); + } else { + u16 *destreg,*srcreg; + + destreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF(","); + srcreg = DECODE_RM_WORD_REGISTER(rl); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = or_word(*destreg, *srcreg); + } + break; + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x0c +****************************************************************************/ +static void x86emuOp_or_byte_AL_IMM(u8 X86EMU_UNUSED(op1)) +{ + u8 srcval; + + START_OF_INSTR(); + DECODE_PRINTF("OR\tAL,"); + srcval = fetch_byte_imm(); + DECODE_PRINTF2("%x\n", srcval); + TRACE_AND_STEP(); + M.x86.R_AL = or_byte(M.x86.R_AL, srcval); + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x0d +****************************************************************************/ +static void x86emuOp_or_word_AX_IMM(u8 X86EMU_UNUSED(op1)) +{ + u32 srcval; + + START_OF_INSTR(); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + DECODE_PRINTF("OR\tEAX,"); + srcval = fetch_long_imm(); + } else { + DECODE_PRINTF("OR\tAX,"); + srcval = fetch_word_imm(); + } + DECODE_PRINTF2("%x\n", srcval); + TRACE_AND_STEP(); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + M.x86.R_EAX = or_long(M.x86.R_EAX, srcval); + } else { + M.x86.R_AX = or_word(M.x86.R_AX, (u16)srcval); + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x0e +****************************************************************************/ +static void x86emuOp_push_CS(u8 X86EMU_UNUSED(op1)) +{ + START_OF_INSTR(); + DECODE_PRINTF("PUSH\tCS\n"); + TRACE_AND_STEP(); + push_word(M.x86.R_CS); + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x0f. Escape for two-byte opcode (286 or better) +****************************************************************************/ +static void x86emuOp_two_byte(u8 X86EMU_UNUSED(op1)) +{ + u8 op2 = (*sys_rdb)(((u32)M.x86.R_CS << 4) + (M.x86.R_IP++)); + INC_DECODED_INST_LEN(1); + (*x86emu_optab2[op2])(op2); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x10 +****************************************************************************/ +static void x86emuOp_adc_byte_RM_R(u8 X86EMU_UNUSED(op1)) +{ + int mod, rl, rh; + u8 *destreg, *srcreg; + uint destoffset; + u8 destval; + + START_OF_INSTR(); + DECODE_PRINTF("ADC\t"); + FETCH_DECODE_MODRM(mod, rh, rl); + switch (mod) { + case 0: + destoffset = decode_rm00_address(rl); + DECODE_PRINTF(","); + destval = fetch_data_byte(destoffset); + srcreg = DECODE_RM_BYTE_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + destval = adc_byte(destval, *srcreg); + store_data_byte(destoffset, destval); + break; + case 1: + destoffset = decode_rm01_address(rl); + DECODE_PRINTF(","); + destval = fetch_data_byte(destoffset); + srcreg = DECODE_RM_BYTE_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + destval = adc_byte(destval, *srcreg); + store_data_byte(destoffset, destval); + break; + case 2: + destoffset = decode_rm10_address(rl); + DECODE_PRINTF(","); + destval = fetch_data_byte(destoffset); + srcreg = DECODE_RM_BYTE_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + destval = adc_byte(destval, *srcreg); + store_data_byte(destoffset, destval); + break; + case 3: /* register to register */ + destreg = DECODE_RM_BYTE_REGISTER(rl); + DECODE_PRINTF(","); + srcreg = DECODE_RM_BYTE_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = adc_byte(*destreg, *srcreg); + break; + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x11 +****************************************************************************/ +static void x86emuOp_adc_word_RM_R(u8 X86EMU_UNUSED(op1)) +{ + int mod, rl, rh; + uint destoffset; + + START_OF_INSTR(); + DECODE_PRINTF("ADC\t"); + FETCH_DECODE_MODRM(mod, rh, rl); + switch (mod) { + case 0: + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 destval; + u32 *srcreg; + + destoffset = decode_rm00_address(rl); + DECODE_PRINTF(","); + destval = fetch_data_long(destoffset); + srcreg = DECODE_RM_LONG_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + destval = adc_long(destval, *srcreg); + store_data_long(destoffset, destval); + } else { + u16 destval; + u16 *srcreg; + + destoffset = decode_rm00_address(rl); + DECODE_PRINTF(","); + destval = fetch_data_word(destoffset); + srcreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + destval = adc_word(destval, *srcreg); + store_data_word(destoffset, destval); + } + break; + case 1: + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 destval; + u32 *srcreg; + + destoffset = decode_rm01_address(rl); + DECODE_PRINTF(","); + destval = fetch_data_long(destoffset); + srcreg = DECODE_RM_LONG_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + destval = adc_long(destval, *srcreg); + store_data_long(destoffset, destval); + } else { + u16 destval; + u16 *srcreg; + + destoffset = decode_rm01_address(rl); + DECODE_PRINTF(","); + destval = fetch_data_word(destoffset); + srcreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + destval = adc_word(destval, *srcreg); + store_data_word(destoffset, destval); + } + break; + case 2: + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 destval; + u32 *srcreg; + + destoffset = decode_rm10_address(rl); + DECODE_PRINTF(","); + destval = fetch_data_long(destoffset); + srcreg = DECODE_RM_LONG_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + destval = adc_long(destval, *srcreg); + store_data_long(destoffset, destval); + } else { + u16 destval; + u16 *srcreg; + + destoffset = decode_rm10_address(rl); + DECODE_PRINTF(","); + destval = fetch_data_word(destoffset); + srcreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + destval = adc_word(destval, *srcreg); + store_data_word(destoffset, destval); + } + break; + case 3: /* register to register */ + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 *destreg,*srcreg; + + destreg = DECODE_RM_LONG_REGISTER(rl); + DECODE_PRINTF(","); + srcreg = DECODE_RM_LONG_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = adc_long(*destreg, *srcreg); + } else { + u16 *destreg,*srcreg; + + destreg = DECODE_RM_WORD_REGISTER(rl); + DECODE_PRINTF(","); + srcreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = adc_word(*destreg, *srcreg); + } + break; + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x12 +****************************************************************************/ +static void x86emuOp_adc_byte_R_RM(u8 X86EMU_UNUSED(op1)) +{ + int mod, rl, rh; + u8 *destreg, *srcreg; + uint srcoffset; + u8 srcval; + + START_OF_INSTR(); + DECODE_PRINTF("ADC\t"); + FETCH_DECODE_MODRM(mod, rh, rl); + switch (mod) { + case 0: + destreg = DECODE_RM_BYTE_REGISTER(rh); + DECODE_PRINTF(","); + srcoffset = decode_rm00_address(rl); + srcval = fetch_data_byte(srcoffset); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = adc_byte(*destreg, srcval); + break; + case 1: + destreg = DECODE_RM_BYTE_REGISTER(rh); + DECODE_PRINTF(","); + srcoffset = decode_rm01_address(rl); + srcval = fetch_data_byte(srcoffset); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = adc_byte(*destreg, srcval); + break; + case 2: + destreg = DECODE_RM_BYTE_REGISTER(rh); + DECODE_PRINTF(","); + srcoffset = decode_rm10_address(rl); + srcval = fetch_data_byte(srcoffset); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = adc_byte(*destreg, srcval); + break; + case 3: /* register to register */ + destreg = DECODE_RM_BYTE_REGISTER(rh); + DECODE_PRINTF(","); + srcreg = DECODE_RM_BYTE_REGISTER(rl); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = adc_byte(*destreg, *srcreg); + break; + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x13 +****************************************************************************/ +static void x86emuOp_adc_word_R_RM(u8 X86EMU_UNUSED(op1)) +{ + int mod, rl, rh; + uint srcoffset; + + START_OF_INSTR(); + DECODE_PRINTF("ADC\t"); + FETCH_DECODE_MODRM(mod, rh, rl); + switch (mod) { + case 0: + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 *destreg; + u32 srcval; + + destreg = DECODE_RM_LONG_REGISTER(rh); + DECODE_PRINTF(","); + srcoffset = decode_rm00_address(rl); + srcval = fetch_data_long(srcoffset); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = adc_long(*destreg, srcval); + } else { + u16 *destreg; + u16 srcval; + + destreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF(","); + srcoffset = decode_rm00_address(rl); + srcval = fetch_data_word(srcoffset); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = adc_word(*destreg, srcval); + } + break; + case 1: + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 *destreg; + u32 srcval; + + destreg = DECODE_RM_LONG_REGISTER(rh); + DECODE_PRINTF(","); + srcoffset = decode_rm01_address(rl); + srcval = fetch_data_long(srcoffset); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = adc_long(*destreg, srcval); + } else { + u16 *destreg; + u16 srcval; + + destreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF(","); + srcoffset = decode_rm01_address(rl); + srcval = fetch_data_word(srcoffset); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = adc_word(*destreg, srcval); + } + break; + case 2: + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 *destreg; + u32 srcval; + + destreg = DECODE_RM_LONG_REGISTER(rh); + DECODE_PRINTF(","); + srcoffset = decode_rm10_address(rl); + srcval = fetch_data_long(srcoffset); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = adc_long(*destreg, srcval); + } else { + u16 *destreg; + u16 srcval; + + destreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF(","); + srcoffset = decode_rm10_address(rl); + srcval = fetch_data_word(srcoffset); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = adc_word(*destreg, srcval); + } + break; + case 3: /* register to register */ + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 *destreg,*srcreg; + + destreg = DECODE_RM_LONG_REGISTER(rh); + DECODE_PRINTF(","); + srcreg = DECODE_RM_LONG_REGISTER(rl); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = adc_long(*destreg, *srcreg); + } else { + u16 *destreg,*srcreg; + + destreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF(","); + srcreg = DECODE_RM_WORD_REGISTER(rl); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = adc_word(*destreg, *srcreg); + } + break; + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x14 +****************************************************************************/ +static void x86emuOp_adc_byte_AL_IMM(u8 X86EMU_UNUSED(op1)) +{ + u8 srcval; + + START_OF_INSTR(); + DECODE_PRINTF("ADC\tAL,"); + srcval = fetch_byte_imm(); + DECODE_PRINTF2("%x\n", srcval); + TRACE_AND_STEP(); + M.x86.R_AL = adc_byte(M.x86.R_AL, srcval); + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x15 +****************************************************************************/ +static void x86emuOp_adc_word_AX_IMM(u8 X86EMU_UNUSED(op1)) +{ + u32 srcval; + + START_OF_INSTR(); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + DECODE_PRINTF("ADC\tEAX,"); + srcval = fetch_long_imm(); + } else { + DECODE_PRINTF("ADC\tAX,"); + srcval = fetch_word_imm(); + } + DECODE_PRINTF2("%x\n", srcval); + TRACE_AND_STEP(); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + M.x86.R_EAX = adc_long(M.x86.R_EAX, srcval); + } else { + M.x86.R_AX = adc_word(M.x86.R_AX, (u16)srcval); + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x16 +****************************************************************************/ +static void x86emuOp_push_SS(u8 X86EMU_UNUSED(op1)) +{ + START_OF_INSTR(); + DECODE_PRINTF("PUSH\tSS\n"); + TRACE_AND_STEP(); + push_word(M.x86.R_SS); + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x17 +****************************************************************************/ +static void x86emuOp_pop_SS(u8 X86EMU_UNUSED(op1)) +{ + START_OF_INSTR(); + DECODE_PRINTF("POP\tSS\n"); + TRACE_AND_STEP(); + M.x86.R_SS = pop_word(); + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x18 +****************************************************************************/ +static void x86emuOp_sbb_byte_RM_R(u8 X86EMU_UNUSED(op1)) +{ + int mod, rl, rh; + u8 *destreg, *srcreg; + uint destoffset; + u8 destval; + + START_OF_INSTR(); + DECODE_PRINTF("SBB\t"); + FETCH_DECODE_MODRM(mod, rh, rl); + switch (mod) { + case 0: + destoffset = decode_rm00_address(rl); + DECODE_PRINTF(","); + destval = fetch_data_byte(destoffset); + srcreg = DECODE_RM_BYTE_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + destval = sbb_byte(destval, *srcreg); + store_data_byte(destoffset, destval); + break; + case 1: + destoffset = decode_rm01_address(rl); + DECODE_PRINTF(","); + destval = fetch_data_byte(destoffset); + srcreg = DECODE_RM_BYTE_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + destval = sbb_byte(destval, *srcreg); + store_data_byte(destoffset, destval); + break; + case 2: + destoffset = decode_rm10_address(rl); + DECODE_PRINTF(","); + destval = fetch_data_byte(destoffset); + srcreg = DECODE_RM_BYTE_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + destval = sbb_byte(destval, *srcreg); + store_data_byte(destoffset, destval); + break; + case 3: /* register to register */ + destreg = DECODE_RM_BYTE_REGISTER(rl); + DECODE_PRINTF(","); + srcreg = DECODE_RM_BYTE_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = sbb_byte(*destreg, *srcreg); + break; + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x19 +****************************************************************************/ +static void x86emuOp_sbb_word_RM_R(u8 X86EMU_UNUSED(op1)) +{ + int mod, rl, rh; + uint destoffset; + + START_OF_INSTR(); + DECODE_PRINTF("SBB\t"); + FETCH_DECODE_MODRM(mod, rh, rl); + switch (mod) { + case 0: + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 destval; + u32 *srcreg; + + destoffset = decode_rm00_address(rl); + DECODE_PRINTF(","); + destval = fetch_data_long(destoffset); + srcreg = DECODE_RM_LONG_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + destval = sbb_long(destval, *srcreg); + store_data_long(destoffset, destval); + } else { + u16 destval; + u16 *srcreg; + + destoffset = decode_rm00_address(rl); + DECODE_PRINTF(","); + destval = fetch_data_word(destoffset); + srcreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + destval = sbb_word(destval, *srcreg); + store_data_word(destoffset, destval); + } + break; + case 1: + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 destval; + u32 *srcreg; + + destoffset = decode_rm01_address(rl); + DECODE_PRINTF(","); + destval = fetch_data_long(destoffset); + srcreg = DECODE_RM_LONG_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + destval = sbb_long(destval, *srcreg); + store_data_long(destoffset, destval); + } else { + u16 destval; + u16 *srcreg; + + destoffset = decode_rm01_address(rl); + DECODE_PRINTF(","); + destval = fetch_data_word(destoffset); + srcreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + destval = sbb_word(destval, *srcreg); + store_data_word(destoffset, destval); + } + break; + case 2: + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 destval; + u32 *srcreg; + + destoffset = decode_rm10_address(rl); + DECODE_PRINTF(","); + destval = fetch_data_long(destoffset); + srcreg = DECODE_RM_LONG_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + destval = sbb_long(destval, *srcreg); + store_data_long(destoffset, destval); + } else { + u16 destval; + u16 *srcreg; + + destoffset = decode_rm10_address(rl); + DECODE_PRINTF(","); + destval = fetch_data_word(destoffset); + srcreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + destval = sbb_word(destval, *srcreg); + store_data_word(destoffset, destval); + } + break; + case 3: /* register to register */ + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 *destreg,*srcreg; + + destreg = DECODE_RM_LONG_REGISTER(rl); + DECODE_PRINTF(","); + srcreg = DECODE_RM_LONG_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = sbb_long(*destreg, *srcreg); + } else { + u16 *destreg,*srcreg; + + destreg = DECODE_RM_WORD_REGISTER(rl); + DECODE_PRINTF(","); + srcreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = sbb_word(*destreg, *srcreg); + } + break; + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x1a +****************************************************************************/ +static void x86emuOp_sbb_byte_R_RM(u8 X86EMU_UNUSED(op1)) +{ + int mod, rl, rh; + u8 *destreg, *srcreg; + uint srcoffset; + u8 srcval; + + START_OF_INSTR(); + DECODE_PRINTF("SBB\t"); + FETCH_DECODE_MODRM(mod, rh, rl); + switch (mod) { + case 0: + destreg = DECODE_RM_BYTE_REGISTER(rh); + DECODE_PRINTF(","); + srcoffset = decode_rm00_address(rl); + srcval = fetch_data_byte(srcoffset); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = sbb_byte(*destreg, srcval); + break; + case 1: + destreg = DECODE_RM_BYTE_REGISTER(rh); + DECODE_PRINTF(","); + srcoffset = decode_rm01_address(rl); + srcval = fetch_data_byte(srcoffset); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = sbb_byte(*destreg, srcval); + break; + case 2: + destreg = DECODE_RM_BYTE_REGISTER(rh); + DECODE_PRINTF(","); + srcoffset = decode_rm10_address(rl); + srcval = fetch_data_byte(srcoffset); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = sbb_byte(*destreg, srcval); + break; + case 3: /* register to register */ + destreg = DECODE_RM_BYTE_REGISTER(rh); + DECODE_PRINTF(","); + srcreg = DECODE_RM_BYTE_REGISTER(rl); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = sbb_byte(*destreg, *srcreg); + break; + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x1b +****************************************************************************/ +static void x86emuOp_sbb_word_R_RM(u8 X86EMU_UNUSED(op1)) +{ + int mod, rl, rh; + uint srcoffset; + + START_OF_INSTR(); + DECODE_PRINTF("SBB\t"); + FETCH_DECODE_MODRM(mod, rh, rl); + switch (mod) { + case 0: + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 *destreg; + u32 srcval; + + destreg = DECODE_RM_LONG_REGISTER(rh); + DECODE_PRINTF(","); + srcoffset = decode_rm00_address(rl); + srcval = fetch_data_long(srcoffset); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = sbb_long(*destreg, srcval); + } else { + u16 *destreg; + u16 srcval; + + destreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF(","); + srcoffset = decode_rm00_address(rl); + srcval = fetch_data_word(srcoffset); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = sbb_word(*destreg, srcval); + } + break; + case 1: + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 *destreg; + u32 srcval; + + destreg = DECODE_RM_LONG_REGISTER(rh); + DECODE_PRINTF(","); + srcoffset = decode_rm01_address(rl); + srcval = fetch_data_long(srcoffset); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = sbb_long(*destreg, srcval); + } else { + u16 *destreg; + u16 srcval; + + destreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF(","); + srcoffset = decode_rm01_address(rl); + srcval = fetch_data_word(srcoffset); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = sbb_word(*destreg, srcval); + } + break; + case 2: + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 *destreg; + u32 srcval; + + destreg = DECODE_RM_LONG_REGISTER(rh); + DECODE_PRINTF(","); + srcoffset = decode_rm10_address(rl); + srcval = fetch_data_long(srcoffset); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = sbb_long(*destreg, srcval); + } else { + u16 *destreg; + u16 srcval; + + destreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF(","); + srcoffset = decode_rm10_address(rl); + srcval = fetch_data_word(srcoffset); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = sbb_word(*destreg, srcval); + } + break; + case 3: /* register to register */ + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 *destreg,*srcreg; + + destreg = DECODE_RM_LONG_REGISTER(rh); + DECODE_PRINTF(","); + srcreg = DECODE_RM_LONG_REGISTER(rl); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = sbb_long(*destreg, *srcreg); + } else { + u16 *destreg,*srcreg; + + destreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF(","); + srcreg = DECODE_RM_WORD_REGISTER(rl); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = sbb_word(*destreg, *srcreg); + } + break; + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x1c +****************************************************************************/ +static void x86emuOp_sbb_byte_AL_IMM(u8 X86EMU_UNUSED(op1)) +{ + u8 srcval; + + START_OF_INSTR(); + DECODE_PRINTF("SBB\tAL,"); + srcval = fetch_byte_imm(); + DECODE_PRINTF2("%x\n", srcval); + TRACE_AND_STEP(); + M.x86.R_AL = sbb_byte(M.x86.R_AL, srcval); + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x1d +****************************************************************************/ +static void x86emuOp_sbb_word_AX_IMM(u8 X86EMU_UNUSED(op1)) +{ + u32 srcval; + + START_OF_INSTR(); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + DECODE_PRINTF("SBB\tEAX,"); + srcval = fetch_long_imm(); + } else { + DECODE_PRINTF("SBB\tAX,"); + srcval = fetch_word_imm(); + } + DECODE_PRINTF2("%x\n", srcval); + TRACE_AND_STEP(); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + M.x86.R_EAX = sbb_long(M.x86.R_EAX, srcval); + } else { + M.x86.R_AX = sbb_word(M.x86.R_AX, (u16)srcval); + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x1e +****************************************************************************/ +static void x86emuOp_push_DS(u8 X86EMU_UNUSED(op1)) +{ + START_OF_INSTR(); + DECODE_PRINTF("PUSH\tDS\n"); + TRACE_AND_STEP(); + push_word(M.x86.R_DS); + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x1f +****************************************************************************/ +static void x86emuOp_pop_DS(u8 X86EMU_UNUSED(op1)) +{ + START_OF_INSTR(); + DECODE_PRINTF("POP\tDS\n"); + TRACE_AND_STEP(); + M.x86.R_DS = pop_word(); + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x20 +****************************************************************************/ +static void x86emuOp_and_byte_RM_R(u8 X86EMU_UNUSED(op1)) +{ + int mod, rl, rh; + u8 *destreg, *srcreg; + uint destoffset; + u8 destval; + + START_OF_INSTR(); + DECODE_PRINTF("AND\t"); + FETCH_DECODE_MODRM(mod, rh, rl); + + switch (mod) { + case 0: + destoffset = decode_rm00_address(rl); + DECODE_PRINTF(","); + destval = fetch_data_byte(destoffset); + srcreg = DECODE_RM_BYTE_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + destval = and_byte(destval, *srcreg); + store_data_byte(destoffset, destval); + break; + + case 1: + destoffset = decode_rm01_address(rl); + DECODE_PRINTF(","); + destval = fetch_data_byte(destoffset); + srcreg = DECODE_RM_BYTE_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + destval = and_byte(destval, *srcreg); + store_data_byte(destoffset, destval); + break; + + case 2: + destoffset = decode_rm10_address(rl); + DECODE_PRINTF(","); + destval = fetch_data_byte(destoffset); + srcreg = DECODE_RM_BYTE_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + destval = and_byte(destval, *srcreg); + store_data_byte(destoffset, destval); + break; + + case 3: /* register to register */ + destreg = DECODE_RM_BYTE_REGISTER(rl); + DECODE_PRINTF(","); + srcreg = DECODE_RM_BYTE_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = and_byte(*destreg, *srcreg); + break; + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x21 +****************************************************************************/ +static void x86emuOp_and_word_RM_R(u8 X86EMU_UNUSED(op1)) +{ + int mod, rl, rh; + uint destoffset; + + START_OF_INSTR(); + DECODE_PRINTF("AND\t"); + FETCH_DECODE_MODRM(mod, rh, rl); + switch (mod) { + case 0: + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 destval; + u32 *srcreg; + + destoffset = decode_rm00_address(rl); + DECODE_PRINTF(","); + destval = fetch_data_long(destoffset); + srcreg = DECODE_RM_LONG_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + destval = and_long(destval, *srcreg); + store_data_long(destoffset, destval); + } else { + u16 destval; + u16 *srcreg; + + destoffset = decode_rm00_address(rl); + DECODE_PRINTF(","); + destval = fetch_data_word(destoffset); + srcreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + destval = and_word(destval, *srcreg); + store_data_word(destoffset, destval); + } + break; + case 1: + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 destval; + u32 *srcreg; + + destoffset = decode_rm01_address(rl); + DECODE_PRINTF(","); + destval = fetch_data_long(destoffset); + srcreg = DECODE_RM_LONG_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + destval = and_long(destval, *srcreg); + store_data_long(destoffset, destval); + } else { + u16 destval; + u16 *srcreg; + + destoffset = decode_rm01_address(rl); + DECODE_PRINTF(","); + destval = fetch_data_word(destoffset); + srcreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + destval = and_word(destval, *srcreg); + store_data_word(destoffset, destval); + } + break; + case 2: + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 destval; + u32 *srcreg; + + destoffset = decode_rm10_address(rl); + DECODE_PRINTF(","); + destval = fetch_data_long(destoffset); + srcreg = DECODE_RM_LONG_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + destval = and_long(destval, *srcreg); + store_data_long(destoffset, destval); + } else { + u16 destval; + u16 *srcreg; + + destoffset = decode_rm10_address(rl); + DECODE_PRINTF(","); + destval = fetch_data_word(destoffset); + srcreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + destval = and_word(destval, *srcreg); + store_data_word(destoffset, destval); + } + break; + case 3: /* register to register */ + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 *destreg,*srcreg; + + destreg = DECODE_RM_LONG_REGISTER(rl); + DECODE_PRINTF(","); + srcreg = DECODE_RM_LONG_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = and_long(*destreg, *srcreg); + } else { + u16 *destreg,*srcreg; + + destreg = DECODE_RM_WORD_REGISTER(rl); + DECODE_PRINTF(","); + srcreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = and_word(*destreg, *srcreg); + } + break; + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x22 +****************************************************************************/ +static void x86emuOp_and_byte_R_RM(u8 X86EMU_UNUSED(op1)) +{ + int mod, rl, rh; + u8 *destreg, *srcreg; + uint srcoffset; + u8 srcval; + + START_OF_INSTR(); + DECODE_PRINTF("AND\t"); + FETCH_DECODE_MODRM(mod, rh, rl); + switch (mod) { + case 0: + destreg = DECODE_RM_BYTE_REGISTER(rh); + DECODE_PRINTF(","); + srcoffset = decode_rm00_address(rl); + srcval = fetch_data_byte(srcoffset); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = and_byte(*destreg, srcval); + break; + case 1: + destreg = DECODE_RM_BYTE_REGISTER(rh); + DECODE_PRINTF(","); + srcoffset = decode_rm01_address(rl); + srcval = fetch_data_byte(srcoffset); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = and_byte(*destreg, srcval); + break; + case 2: + destreg = DECODE_RM_BYTE_REGISTER(rh); + DECODE_PRINTF(","); + srcoffset = decode_rm10_address(rl); + srcval = fetch_data_byte(srcoffset); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = and_byte(*destreg, srcval); + break; + case 3: /* register to register */ + destreg = DECODE_RM_BYTE_REGISTER(rh); + DECODE_PRINTF(","); + srcreg = DECODE_RM_BYTE_REGISTER(rl); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = and_byte(*destreg, *srcreg); + break; + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x23 +****************************************************************************/ +static void x86emuOp_and_word_R_RM(u8 X86EMU_UNUSED(op1)) +{ + int mod, rl, rh; + uint srcoffset; + + START_OF_INSTR(); + DECODE_PRINTF("AND\t"); + FETCH_DECODE_MODRM(mod, rh, rl); + switch (mod) { + case 0: + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 *destreg; + u32 srcval; + + destreg = DECODE_RM_LONG_REGISTER(rh); + DECODE_PRINTF(","); + srcoffset = decode_rm00_address(rl); + srcval = fetch_data_long(srcoffset); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = and_long(*destreg, srcval); + } else { + u16 *destreg; + u16 srcval; + + destreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF(","); + srcoffset = decode_rm00_address(rl); + srcval = fetch_data_word(srcoffset); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = and_word(*destreg, srcval); + } + break; + case 1: + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 *destreg; + u32 srcval; + + destreg = DECODE_RM_LONG_REGISTER(rh); + DECODE_PRINTF(","); + srcoffset = decode_rm01_address(rl); + srcval = fetch_data_long(srcoffset); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = and_long(*destreg, srcval); + break; + } else { + u16 *destreg; + u16 srcval; + + destreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF(","); + srcoffset = decode_rm01_address(rl); + srcval = fetch_data_word(srcoffset); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = and_word(*destreg, srcval); + break; + } + case 2: + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 *destreg; + u32 srcval; + + destreg = DECODE_RM_LONG_REGISTER(rh); + DECODE_PRINTF(","); + srcoffset = decode_rm10_address(rl); + srcval = fetch_data_long(srcoffset); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = and_long(*destreg, srcval); + } else { + u16 *destreg; + u16 srcval; + + destreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF(","); + srcoffset = decode_rm10_address(rl); + srcval = fetch_data_word(srcoffset); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = and_word(*destreg, srcval); + } + break; + case 3: /* register to register */ + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 *destreg,*srcreg; + + destreg = DECODE_RM_LONG_REGISTER(rh); + DECODE_PRINTF(","); + srcreg = DECODE_RM_LONG_REGISTER(rl); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = and_long(*destreg, *srcreg); + } else { + u16 *destreg,*srcreg; + + destreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF(","); + srcreg = DECODE_RM_WORD_REGISTER(rl); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = and_word(*destreg, *srcreg); + } + break; + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x24 +****************************************************************************/ +static void x86emuOp_and_byte_AL_IMM(u8 X86EMU_UNUSED(op1)) +{ + u8 srcval; + + START_OF_INSTR(); + DECODE_PRINTF("AND\tAL,"); + srcval = fetch_byte_imm(); + DECODE_PRINTF2("%x\n", srcval); + TRACE_AND_STEP(); + M.x86.R_AL = and_byte(M.x86.R_AL, srcval); + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x25 +****************************************************************************/ +static void x86emuOp_and_word_AX_IMM(u8 X86EMU_UNUSED(op1)) +{ + u32 srcval; + + START_OF_INSTR(); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + DECODE_PRINTF("AND\tEAX,"); + srcval = fetch_long_imm(); + } else { + DECODE_PRINTF("AND\tAX,"); + srcval = fetch_word_imm(); + } + DECODE_PRINTF2("%x\n", srcval); + TRACE_AND_STEP(); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + M.x86.R_EAX = and_long(M.x86.R_EAX, srcval); + } else { + M.x86.R_AX = and_word(M.x86.R_AX, (u16)srcval); + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x26 +****************************************************************************/ +static void x86emuOp_segovr_ES(u8 X86EMU_UNUSED(op1)) +{ + START_OF_INSTR(); + DECODE_PRINTF("ES:\n"); + TRACE_AND_STEP(); + M.x86.mode |= SYSMODE_SEGOVR_ES; + /* + * note the lack of DECODE_CLEAR_SEGOVR(r) since, here is one of 4 + * opcode subroutines we do not want to do this. + */ + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x27 +****************************************************************************/ +static void x86emuOp_daa(u8 X86EMU_UNUSED(op1)) +{ + START_OF_INSTR(); + DECODE_PRINTF("DAA\n"); + TRACE_AND_STEP(); + M.x86.R_AL = daa_byte(M.x86.R_AL); + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x28 +****************************************************************************/ +static void x86emuOp_sub_byte_RM_R(u8 X86EMU_UNUSED(op1)) +{ + int mod, rl, rh; + u8 *destreg, *srcreg; + uint destoffset; + u8 destval; + + START_OF_INSTR(); + DECODE_PRINTF("SUB\t"); + FETCH_DECODE_MODRM(mod, rh, rl); + switch (mod) { + case 0: + destoffset = decode_rm00_address(rl); + DECODE_PRINTF(","); + destval = fetch_data_byte(destoffset); + srcreg = DECODE_RM_BYTE_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + destval = sub_byte(destval, *srcreg); + store_data_byte(destoffset, destval); + break; + case 1: + destoffset = decode_rm01_address(rl); + DECODE_PRINTF(","); + destval = fetch_data_byte(destoffset); + srcreg = DECODE_RM_BYTE_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + destval = sub_byte(destval, *srcreg); + store_data_byte(destoffset, destval); + break; + case 2: + destoffset = decode_rm10_address(rl); + DECODE_PRINTF(","); + destval = fetch_data_byte(destoffset); + srcreg = DECODE_RM_BYTE_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + destval = sub_byte(destval, *srcreg); + store_data_byte(destoffset, destval); + break; + case 3: /* register to register */ + destreg = DECODE_RM_BYTE_REGISTER(rl); + DECODE_PRINTF(","); + srcreg = DECODE_RM_BYTE_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = sub_byte(*destreg, *srcreg); + break; + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x29 +****************************************************************************/ +static void x86emuOp_sub_word_RM_R(u8 X86EMU_UNUSED(op1)) +{ + int mod, rl, rh; + uint destoffset; + + START_OF_INSTR(); + DECODE_PRINTF("SUB\t"); + FETCH_DECODE_MODRM(mod, rh, rl); + switch (mod) { + case 0: + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 destval; + u32 *srcreg; + + destoffset = decode_rm00_address(rl); + DECODE_PRINTF(","); + destval = fetch_data_long(destoffset); + srcreg = DECODE_RM_LONG_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + destval = sub_long(destval, *srcreg); + store_data_long(destoffset, destval); + } else { + u16 destval; + u16 *srcreg; + + destoffset = decode_rm00_address(rl); + DECODE_PRINTF(","); + destval = fetch_data_word(destoffset); + srcreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + destval = sub_word(destval, *srcreg); + store_data_word(destoffset, destval); + } + break; + case 1: + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 destval; + u32 *srcreg; + + destoffset = decode_rm01_address(rl); + DECODE_PRINTF(","); + destval = fetch_data_long(destoffset); + srcreg = DECODE_RM_LONG_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + destval = sub_long(destval, *srcreg); + store_data_long(destoffset, destval); + } else { + u16 destval; + u16 *srcreg; + + destoffset = decode_rm01_address(rl); + DECODE_PRINTF(","); + destval = fetch_data_word(destoffset); + srcreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + destval = sub_word(destval, *srcreg); + store_data_word(destoffset, destval); + } + break; + case 2: + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 destval; + u32 *srcreg; + + destoffset = decode_rm10_address(rl); + DECODE_PRINTF(","); + destval = fetch_data_long(destoffset); + srcreg = DECODE_RM_LONG_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + destval = sub_long(destval, *srcreg); + store_data_long(destoffset, destval); + } else { + u16 destval; + u16 *srcreg; + + destoffset = decode_rm10_address(rl); + DECODE_PRINTF(","); + destval = fetch_data_word(destoffset); + srcreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + destval = sub_word(destval, *srcreg); + store_data_word(destoffset, destval); + } + break; + case 3: /* register to register */ + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 *destreg,*srcreg; + + destreg = DECODE_RM_LONG_REGISTER(rl); + DECODE_PRINTF(","); + srcreg = DECODE_RM_LONG_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = sub_long(*destreg, *srcreg); + } else { + u16 *destreg,*srcreg; + + destreg = DECODE_RM_WORD_REGISTER(rl); + DECODE_PRINTF(","); + srcreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = sub_word(*destreg, *srcreg); + } + break; + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x2a +****************************************************************************/ +static void x86emuOp_sub_byte_R_RM(u8 X86EMU_UNUSED(op1)) +{ + int mod, rl, rh; + u8 *destreg, *srcreg; + uint srcoffset; + u8 srcval; + + START_OF_INSTR(); + DECODE_PRINTF("SUB\t"); + FETCH_DECODE_MODRM(mod, rh, rl); + switch (mod) { + case 0: + destreg = DECODE_RM_BYTE_REGISTER(rh); + DECODE_PRINTF(","); + srcoffset = decode_rm00_address(rl); + srcval = fetch_data_byte(srcoffset); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = sub_byte(*destreg, srcval); + break; + case 1: + destreg = DECODE_RM_BYTE_REGISTER(rh); + DECODE_PRINTF(","); + srcoffset = decode_rm01_address(rl); + srcval = fetch_data_byte(srcoffset); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = sub_byte(*destreg, srcval); + break; + case 2: + destreg = DECODE_RM_BYTE_REGISTER(rh); + DECODE_PRINTF(","); + srcoffset = decode_rm10_address(rl); + srcval = fetch_data_byte(srcoffset); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = sub_byte(*destreg, srcval); + break; + case 3: /* register to register */ + destreg = DECODE_RM_BYTE_REGISTER(rh); + DECODE_PRINTF(","); + srcreg = DECODE_RM_BYTE_REGISTER(rl); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = sub_byte(*destreg, *srcreg); + break; + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x2b +****************************************************************************/ +static void x86emuOp_sub_word_R_RM(u8 X86EMU_UNUSED(op1)) +{ + int mod, rl, rh; + uint srcoffset; + + START_OF_INSTR(); + DECODE_PRINTF("SUB\t"); + FETCH_DECODE_MODRM(mod, rh, rl); + switch (mod) { + case 0: + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 *destreg; + u32 srcval; + + destreg = DECODE_RM_LONG_REGISTER(rh); + DECODE_PRINTF(","); + srcoffset = decode_rm00_address(rl); + srcval = fetch_data_long(srcoffset); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = sub_long(*destreg, srcval); + } else { + u16 *destreg; + u16 srcval; + + destreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF(","); + srcoffset = decode_rm00_address(rl); + srcval = fetch_data_word(srcoffset); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = sub_word(*destreg, srcval); + } + break; + case 1: + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 *destreg; + u32 srcval; + + destreg = DECODE_RM_LONG_REGISTER(rh); + DECODE_PRINTF(","); + srcoffset = decode_rm01_address(rl); + srcval = fetch_data_long(srcoffset); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = sub_long(*destreg, srcval); + } else { + u16 *destreg; + u16 srcval; + + destreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF(","); + srcoffset = decode_rm01_address(rl); + srcval = fetch_data_word(srcoffset); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = sub_word(*destreg, srcval); + } + break; + case 2: + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 *destreg; + u32 srcval; + + destreg = DECODE_RM_LONG_REGISTER(rh); + DECODE_PRINTF(","); + srcoffset = decode_rm10_address(rl); + srcval = fetch_data_long(srcoffset); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = sub_long(*destreg, srcval); + } else { + u16 *destreg; + u16 srcval; + + destreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF(","); + srcoffset = decode_rm10_address(rl); + srcval = fetch_data_word(srcoffset); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = sub_word(*destreg, srcval); + } + break; + case 3: /* register to register */ + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 *destreg,*srcreg; + + destreg = DECODE_RM_LONG_REGISTER(rh); + DECODE_PRINTF(","); + srcreg = DECODE_RM_LONG_REGISTER(rl); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = sub_long(*destreg, *srcreg); + } else { + u16 *destreg,*srcreg; + + destreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF(","); + srcreg = DECODE_RM_WORD_REGISTER(rl); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = sub_word(*destreg, *srcreg); + } + break; + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x2c +****************************************************************************/ +static void x86emuOp_sub_byte_AL_IMM(u8 X86EMU_UNUSED(op1)) +{ + u8 srcval; + + START_OF_INSTR(); + DECODE_PRINTF("SUB\tAL,"); + srcval = fetch_byte_imm(); + DECODE_PRINTF2("%x\n", srcval); + TRACE_AND_STEP(); + M.x86.R_AL = sub_byte(M.x86.R_AL, srcval); + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x2d +****************************************************************************/ +static void x86emuOp_sub_word_AX_IMM(u8 X86EMU_UNUSED(op1)) +{ + u32 srcval; + + START_OF_INSTR(); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + DECODE_PRINTF("SUB\tEAX,"); + srcval = fetch_long_imm(); + } else { + DECODE_PRINTF("SUB\tAX,"); + srcval = fetch_word_imm(); + } + DECODE_PRINTF2("%x\n", srcval); + TRACE_AND_STEP(); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + M.x86.R_EAX = sub_long(M.x86.R_EAX, srcval); + } else { + M.x86.R_AX = sub_word(M.x86.R_AX, (u16)srcval); + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x2e +****************************************************************************/ +static void x86emuOp_segovr_CS(u8 X86EMU_UNUSED(op1)) +{ + START_OF_INSTR(); + DECODE_PRINTF("CS:\n"); + TRACE_AND_STEP(); + M.x86.mode |= SYSMODE_SEGOVR_CS; + /* note no DECODE_CLEAR_SEGOVR here. */ + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x2f +****************************************************************************/ +static void x86emuOp_das(u8 X86EMU_UNUSED(op1)) +{ + START_OF_INSTR(); + DECODE_PRINTF("DAS\n"); + TRACE_AND_STEP(); + M.x86.R_AL = das_byte(M.x86.R_AL); + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x30 +****************************************************************************/ +static void x86emuOp_xor_byte_RM_R(u8 X86EMU_UNUSED(op1)) +{ + int mod, rl, rh; + u8 *destreg, *srcreg; + uint destoffset; + u8 destval; + + START_OF_INSTR(); + DECODE_PRINTF("XOR\t"); + FETCH_DECODE_MODRM(mod, rh, rl); + switch (mod) { + case 0: + destoffset = decode_rm00_address(rl); + DECODE_PRINTF(","); + destval = fetch_data_byte(destoffset); + srcreg = DECODE_RM_BYTE_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + destval = xor_byte(destval, *srcreg); + store_data_byte(destoffset, destval); + break; + case 1: + destoffset = decode_rm01_address(rl); + DECODE_PRINTF(","); + destval = fetch_data_byte(destoffset); + srcreg = DECODE_RM_BYTE_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + destval = xor_byte(destval, *srcreg); + store_data_byte(destoffset, destval); + break; + case 2: + destoffset = decode_rm10_address(rl); + DECODE_PRINTF(","); + destval = fetch_data_byte(destoffset); + srcreg = DECODE_RM_BYTE_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + destval = xor_byte(destval, *srcreg); + store_data_byte(destoffset, destval); + break; + case 3: /* register to register */ + destreg = DECODE_RM_BYTE_REGISTER(rl); + DECODE_PRINTF(","); + srcreg = DECODE_RM_BYTE_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = xor_byte(*destreg, *srcreg); + break; + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x31 +****************************************************************************/ +static void x86emuOp_xor_word_RM_R(u8 X86EMU_UNUSED(op1)) +{ + int mod, rl, rh; + uint destoffset; + + START_OF_INSTR(); + DECODE_PRINTF("XOR\t"); + FETCH_DECODE_MODRM(mod, rh, rl); + switch (mod) { + case 0: + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 destval; + u32 *srcreg; + + destoffset = decode_rm00_address(rl); + DECODE_PRINTF(","); + destval = fetch_data_long(destoffset); + srcreg = DECODE_RM_LONG_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + destval = xor_long(destval, *srcreg); + store_data_long(destoffset, destval); + } else { + u16 destval; + u16 *srcreg; + + destoffset = decode_rm00_address(rl); + DECODE_PRINTF(","); + destval = fetch_data_word(destoffset); + srcreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + destval = xor_word(destval, *srcreg); + store_data_word(destoffset, destval); + } + break; + case 1: + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 destval; + u32 *srcreg; + + destoffset = decode_rm01_address(rl); + DECODE_PRINTF(","); + destval = fetch_data_long(destoffset); + srcreg = DECODE_RM_LONG_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + destval = xor_long(destval, *srcreg); + store_data_long(destoffset, destval); + } else { + u16 destval; + u16 *srcreg; + + destoffset = decode_rm01_address(rl); + DECODE_PRINTF(","); + destval = fetch_data_word(destoffset); + srcreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + destval = xor_word(destval, *srcreg); + store_data_word(destoffset, destval); + } + break; + case 2: + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 destval; + u32 *srcreg; + + destoffset = decode_rm10_address(rl); + DECODE_PRINTF(","); + destval = fetch_data_long(destoffset); + srcreg = DECODE_RM_LONG_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + destval = xor_long(destval, *srcreg); + store_data_long(destoffset, destval); + } else { + u16 destval; + u16 *srcreg; + + destoffset = decode_rm10_address(rl); + DECODE_PRINTF(","); + destval = fetch_data_word(destoffset); + srcreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + destval = xor_word(destval, *srcreg); + store_data_word(destoffset, destval); + } + break; + case 3: /* register to register */ + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 *destreg,*srcreg; + + destreg = DECODE_RM_LONG_REGISTER(rl); + DECODE_PRINTF(","); + srcreg = DECODE_RM_LONG_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = xor_long(*destreg, *srcreg); + } else { + u16 *destreg,*srcreg; + + destreg = DECODE_RM_WORD_REGISTER(rl); + DECODE_PRINTF(","); + srcreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = xor_word(*destreg, *srcreg); + } + break; + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x32 +****************************************************************************/ +static void x86emuOp_xor_byte_R_RM(u8 X86EMU_UNUSED(op1)) +{ + int mod, rl, rh; + u8 *destreg, *srcreg; + uint srcoffset; + u8 srcval; + + START_OF_INSTR(); + DECODE_PRINTF("XOR\t"); + FETCH_DECODE_MODRM(mod, rh, rl); + switch (mod) { + case 0: + destreg = DECODE_RM_BYTE_REGISTER(rh); + DECODE_PRINTF(","); + srcoffset = decode_rm00_address(rl); + srcval = fetch_data_byte(srcoffset); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = xor_byte(*destreg, srcval); + break; + case 1: + destreg = DECODE_RM_BYTE_REGISTER(rh); + DECODE_PRINTF(","); + srcoffset = decode_rm01_address(rl); + srcval = fetch_data_byte(srcoffset); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = xor_byte(*destreg, srcval); + break; + case 2: + destreg = DECODE_RM_BYTE_REGISTER(rh); + DECODE_PRINTF(","); + srcoffset = decode_rm10_address(rl); + srcval = fetch_data_byte(srcoffset); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = xor_byte(*destreg, srcval); + break; + case 3: /* register to register */ + destreg = DECODE_RM_BYTE_REGISTER(rh); + DECODE_PRINTF(","); + srcreg = DECODE_RM_BYTE_REGISTER(rl); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = xor_byte(*destreg, *srcreg); + break; + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x33 +****************************************************************************/ +static void x86emuOp_xor_word_R_RM(u8 X86EMU_UNUSED(op1)) +{ + int mod, rl, rh; + uint srcoffset; + + START_OF_INSTR(); + DECODE_PRINTF("XOR\t"); + FETCH_DECODE_MODRM(mod, rh, rl); + switch (mod) { + case 0: + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 *destreg; + u32 srcval; + + destreg = DECODE_RM_LONG_REGISTER(rh); + DECODE_PRINTF(","); + srcoffset = decode_rm00_address(rl); + srcval = fetch_data_long(srcoffset); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = xor_long(*destreg, srcval); + } else { + u16 *destreg; + u16 srcval; + + destreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF(","); + srcoffset = decode_rm00_address(rl); + srcval = fetch_data_word(srcoffset); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = xor_word(*destreg, srcval); + } + break; + case 1: + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 *destreg; + u32 srcval; + + destreg = DECODE_RM_LONG_REGISTER(rh); + DECODE_PRINTF(","); + srcoffset = decode_rm01_address(rl); + srcval = fetch_data_long(srcoffset); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = xor_long(*destreg, srcval); + } else { + u16 *destreg; + u16 srcval; + + destreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF(","); + srcoffset = decode_rm01_address(rl); + srcval = fetch_data_word(srcoffset); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = xor_word(*destreg, srcval); + } + break; + case 2: + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 *destreg; + u32 srcval; + + destreg = DECODE_RM_LONG_REGISTER(rh); + DECODE_PRINTF(","); + srcoffset = decode_rm10_address(rl); + srcval = fetch_data_long(srcoffset); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = xor_long(*destreg, srcval); + } else { + u16 *destreg; + u16 srcval; + + destreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF(","); + srcoffset = decode_rm10_address(rl); + srcval = fetch_data_word(srcoffset); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = xor_word(*destreg, srcval); + } + break; + case 3: /* register to register */ + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 *destreg,*srcreg; + + destreg = DECODE_RM_LONG_REGISTER(rh); + DECODE_PRINTF(","); + srcreg = DECODE_RM_LONG_REGISTER(rl); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = xor_long(*destreg, *srcreg); + } else { + u16 *destreg,*srcreg; + + destreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF(","); + srcreg = DECODE_RM_WORD_REGISTER(rl); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = xor_word(*destreg, *srcreg); + } + break; + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x34 +****************************************************************************/ +static void x86emuOp_xor_byte_AL_IMM(u8 X86EMU_UNUSED(op1)) +{ + u8 srcval; + + START_OF_INSTR(); + DECODE_PRINTF("XOR\tAL,"); + srcval = fetch_byte_imm(); + DECODE_PRINTF2("%x\n", srcval); + TRACE_AND_STEP(); + M.x86.R_AL = xor_byte(M.x86.R_AL, srcval); + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x35 +****************************************************************************/ +static void x86emuOp_xor_word_AX_IMM(u8 X86EMU_UNUSED(op1)) +{ + u32 srcval; + + START_OF_INSTR(); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + DECODE_PRINTF("XOR\tEAX,"); + srcval = fetch_long_imm(); + } else { + DECODE_PRINTF("XOR\tAX,"); + srcval = fetch_word_imm(); + } + DECODE_PRINTF2("%x\n", srcval); + TRACE_AND_STEP(); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + M.x86.R_EAX = xor_long(M.x86.R_EAX, srcval); + } else { + M.x86.R_AX = xor_word(M.x86.R_AX, (u16)srcval); + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x36 +****************************************************************************/ +static void x86emuOp_segovr_SS(u8 X86EMU_UNUSED(op1)) +{ + START_OF_INSTR(); + DECODE_PRINTF("SS:\n"); + TRACE_AND_STEP(); + M.x86.mode |= SYSMODE_SEGOVR_SS; + /* no DECODE_CLEAR_SEGOVR ! */ + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x37 +****************************************************************************/ +static void x86emuOp_aaa(u8 X86EMU_UNUSED(op1)) +{ + START_OF_INSTR(); + DECODE_PRINTF("AAA\n"); + TRACE_AND_STEP(); + M.x86.R_AX = aaa_word(M.x86.R_AX); + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x38 +****************************************************************************/ +static void x86emuOp_cmp_byte_RM_R(u8 X86EMU_UNUSED(op1)) +{ + int mod, rl, rh; + uint destoffset; + u8 *destreg, *srcreg; + u8 destval; + + START_OF_INSTR(); + DECODE_PRINTF("CMP\t"); + FETCH_DECODE_MODRM(mod, rh, rl); + switch (mod) { + case 0: + destoffset = decode_rm00_address(rl); + DECODE_PRINTF(","); + destval = fetch_data_byte(destoffset); + srcreg = DECODE_RM_BYTE_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + cmp_byte(destval, *srcreg); + break; + case 1: + destoffset = decode_rm01_address(rl); + DECODE_PRINTF(","); + destval = fetch_data_byte(destoffset); + srcreg = DECODE_RM_BYTE_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + cmp_byte(destval, *srcreg); + break; + case 2: + destoffset = decode_rm10_address(rl); + DECODE_PRINTF(","); + destval = fetch_data_byte(destoffset); + srcreg = DECODE_RM_BYTE_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + cmp_byte(destval, *srcreg); + break; + case 3: /* register to register */ + destreg = DECODE_RM_BYTE_REGISTER(rl); + DECODE_PRINTF(","); + srcreg = DECODE_RM_BYTE_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + cmp_byte(*destreg, *srcreg); + break; + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x39 +****************************************************************************/ +static void x86emuOp_cmp_word_RM_R(u8 X86EMU_UNUSED(op1)) +{ + int mod, rl, rh; + uint destoffset; + + START_OF_INSTR(); + DECODE_PRINTF("CMP\t"); + FETCH_DECODE_MODRM(mod, rh, rl); + switch (mod) { + case 0: + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 destval; + u32 *srcreg; + + destoffset = decode_rm00_address(rl); + DECODE_PRINTF(","); + destval = fetch_data_long(destoffset); + srcreg = DECODE_RM_LONG_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + cmp_long(destval, *srcreg); + } else { + u16 destval; + u16 *srcreg; + + destoffset = decode_rm00_address(rl); + DECODE_PRINTF(","); + destval = fetch_data_word(destoffset); + srcreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + cmp_word(destval, *srcreg); + } + break; + case 1: + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 destval; + u32 *srcreg; + + destoffset = decode_rm01_address(rl); + DECODE_PRINTF(","); + destval = fetch_data_long(destoffset); + srcreg = DECODE_RM_LONG_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + cmp_long(destval, *srcreg); + } else { + u16 destval; + u16 *srcreg; + + destoffset = decode_rm01_address(rl); + DECODE_PRINTF(","); + destval = fetch_data_word(destoffset); + srcreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + cmp_word(destval, *srcreg); + } + break; + case 2: + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 destval; + u32 *srcreg; + + destoffset = decode_rm10_address(rl); + DECODE_PRINTF(","); + destval = fetch_data_long(destoffset); + srcreg = DECODE_RM_LONG_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + cmp_long(destval, *srcreg); + } else { + u16 destval; + u16 *srcreg; + + destoffset = decode_rm10_address(rl); + DECODE_PRINTF(","); + destval = fetch_data_word(destoffset); + srcreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + cmp_word(destval, *srcreg); + } + break; + case 3: /* register to register */ + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 *destreg,*srcreg; + + destreg = DECODE_RM_LONG_REGISTER(rl); + DECODE_PRINTF(","); + srcreg = DECODE_RM_LONG_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + cmp_long(*destreg, *srcreg); + } else { + u16 *destreg,*srcreg; + + destreg = DECODE_RM_WORD_REGISTER(rl); + DECODE_PRINTF(","); + srcreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + cmp_word(*destreg, *srcreg); + } + break; + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x3a +****************************************************************************/ +static void x86emuOp_cmp_byte_R_RM(u8 X86EMU_UNUSED(op1)) +{ + int mod, rl, rh; + u8 *destreg, *srcreg; + uint srcoffset; + u8 srcval; + + START_OF_INSTR(); + DECODE_PRINTF("CMP\t"); + FETCH_DECODE_MODRM(mod, rh, rl); + switch (mod) { + case 0: + destreg = DECODE_RM_BYTE_REGISTER(rh); + DECODE_PRINTF(","); + srcoffset = decode_rm00_address(rl); + srcval = fetch_data_byte(srcoffset); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + cmp_byte(*destreg, srcval); + break; + case 1: + destreg = DECODE_RM_BYTE_REGISTER(rh); + DECODE_PRINTF(","); + srcoffset = decode_rm01_address(rl); + srcval = fetch_data_byte(srcoffset); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + cmp_byte(*destreg, srcval); + break; + case 2: + destreg = DECODE_RM_BYTE_REGISTER(rh); + DECODE_PRINTF(","); + srcoffset = decode_rm10_address(rl); + srcval = fetch_data_byte(srcoffset); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + cmp_byte(*destreg, srcval); + break; + case 3: /* register to register */ + destreg = DECODE_RM_BYTE_REGISTER(rh); + DECODE_PRINTF(","); + srcreg = DECODE_RM_BYTE_REGISTER(rl); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + cmp_byte(*destreg, *srcreg); + break; + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x3b +****************************************************************************/ +static void x86emuOp_cmp_word_R_RM(u8 X86EMU_UNUSED(op1)) +{ + int mod, rl, rh; + uint srcoffset; + + START_OF_INSTR(); + DECODE_PRINTF("CMP\t"); + FETCH_DECODE_MODRM(mod, rh, rl); + switch (mod) { + case 0: + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 *destreg; + u32 srcval; + + destreg = DECODE_RM_LONG_REGISTER(rh); + DECODE_PRINTF(","); + srcoffset = decode_rm00_address(rl); + srcval = fetch_data_long(srcoffset); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + cmp_long(*destreg, srcval); + } else { + u16 *destreg; + u16 srcval; + + destreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF(","); + srcoffset = decode_rm00_address(rl); + srcval = fetch_data_word(srcoffset); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + cmp_word(*destreg, srcval); + } + break; + case 1: + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 *destreg; + u32 srcval; + + destreg = DECODE_RM_LONG_REGISTER(rh); + DECODE_PRINTF(","); + srcoffset = decode_rm01_address(rl); + srcval = fetch_data_long(srcoffset); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + cmp_long(*destreg, srcval); + } else { + u16 *destreg; + u16 srcval; + + destreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF(","); + srcoffset = decode_rm01_address(rl); + srcval = fetch_data_word(srcoffset); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + cmp_word(*destreg, srcval); + } + break; + case 2: + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 *destreg; + u32 srcval; + + destreg = DECODE_RM_LONG_REGISTER(rh); + DECODE_PRINTF(","); + srcoffset = decode_rm10_address(rl); + srcval = fetch_data_long(srcoffset); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + cmp_long(*destreg, srcval); + } else { + u16 *destreg; + u16 srcval; + + destreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF(","); + srcoffset = decode_rm10_address(rl); + srcval = fetch_data_word(srcoffset); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + cmp_word(*destreg, srcval); + } + break; + case 3: /* register to register */ + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 *destreg,*srcreg; + + destreg = DECODE_RM_LONG_REGISTER(rh); + DECODE_PRINTF(","); + srcreg = DECODE_RM_LONG_REGISTER(rl); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + cmp_long(*destreg, *srcreg); + } else { + u16 *destreg,*srcreg; + + destreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF(","); + srcreg = DECODE_RM_WORD_REGISTER(rl); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + cmp_word(*destreg, *srcreg); + } + break; + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x3c +****************************************************************************/ +static void x86emuOp_cmp_byte_AL_IMM(u8 X86EMU_UNUSED(op1)) +{ + u8 srcval; + + START_OF_INSTR(); + DECODE_PRINTF("CMP\tAL,"); + srcval = fetch_byte_imm(); + DECODE_PRINTF2("%x\n", srcval); + TRACE_AND_STEP(); + cmp_byte(M.x86.R_AL, srcval); + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x3d +****************************************************************************/ +static void x86emuOp_cmp_word_AX_IMM(u8 X86EMU_UNUSED(op1)) +{ + u32 srcval; + + START_OF_INSTR(); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + DECODE_PRINTF("CMP\tEAX,"); + srcval = fetch_long_imm(); + } else { + DECODE_PRINTF("CMP\tAX,"); + srcval = fetch_word_imm(); + } + DECODE_PRINTF2("%x\n", srcval); + TRACE_AND_STEP(); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + cmp_long(M.x86.R_EAX, srcval); + } else { + cmp_word(M.x86.R_AX, (u16)srcval); + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x3e +****************************************************************************/ +static void x86emuOp_segovr_DS(u8 X86EMU_UNUSED(op1)) +{ + START_OF_INSTR(); + DECODE_PRINTF("DS:\n"); + TRACE_AND_STEP(); + M.x86.mode |= SYSMODE_SEGOVR_DS; + /* NO DECODE_CLEAR_SEGOVR! */ + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x3f +****************************************************************************/ +static void x86emuOp_aas(u8 X86EMU_UNUSED(op1)) +{ + START_OF_INSTR(); + DECODE_PRINTF("AAS\n"); + TRACE_AND_STEP(); + M.x86.R_AX = aas_word(M.x86.R_AX); + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x40 +****************************************************************************/ +static void x86emuOp_inc_AX(u8 X86EMU_UNUSED(op1)) +{ + START_OF_INSTR(); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + DECODE_PRINTF("INC\tEAX\n"); + } else { + DECODE_PRINTF("INC\tAX\n"); + } + TRACE_AND_STEP(); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + M.x86.R_EAX = inc_long(M.x86.R_EAX); + } else { + M.x86.R_AX = inc_word(M.x86.R_AX); + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x41 +****************************************************************************/ +static void x86emuOp_inc_CX(u8 X86EMU_UNUSED(op1)) +{ + START_OF_INSTR(); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + DECODE_PRINTF("INC\tECX\n"); + } else { + DECODE_PRINTF("INC\tCX\n"); + } + TRACE_AND_STEP(); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + M.x86.R_ECX = inc_long(M.x86.R_ECX); + } else { + M.x86.R_CX = inc_word(M.x86.R_CX); + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x42 +****************************************************************************/ +static void x86emuOp_inc_DX(u8 X86EMU_UNUSED(op1)) +{ + START_OF_INSTR(); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + DECODE_PRINTF("INC\tEDX\n"); + } else { + DECODE_PRINTF("INC\tDX\n"); + } + TRACE_AND_STEP(); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + M.x86.R_EDX = inc_long(M.x86.R_EDX); + } else { + M.x86.R_DX = inc_word(M.x86.R_DX); + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x43 +****************************************************************************/ +static void x86emuOp_inc_BX(u8 X86EMU_UNUSED(op1)) +{ + START_OF_INSTR(); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + DECODE_PRINTF("INC\tEBX\n"); + } else { + DECODE_PRINTF("INC\tBX\n"); + } + TRACE_AND_STEP(); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + M.x86.R_EBX = inc_long(M.x86.R_EBX); + } else { + M.x86.R_BX = inc_word(M.x86.R_BX); + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x44 +****************************************************************************/ +static void x86emuOp_inc_SP(u8 X86EMU_UNUSED(op1)) +{ + START_OF_INSTR(); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + DECODE_PRINTF("INC\tESP\n"); + } else { + DECODE_PRINTF("INC\tSP\n"); + } + TRACE_AND_STEP(); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + M.x86.R_ESP = inc_long(M.x86.R_ESP); + } else { + M.x86.R_SP = inc_word(M.x86.R_SP); + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x45 +****************************************************************************/ +static void x86emuOp_inc_BP(u8 X86EMU_UNUSED(op1)) +{ + START_OF_INSTR(); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + DECODE_PRINTF("INC\tEBP\n"); + } else { + DECODE_PRINTF("INC\tBP\n"); + } + TRACE_AND_STEP(); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + M.x86.R_EBP = inc_long(M.x86.R_EBP); + } else { + M.x86.R_BP = inc_word(M.x86.R_BP); + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x46 +****************************************************************************/ +static void x86emuOp_inc_SI(u8 X86EMU_UNUSED(op1)) +{ + START_OF_INSTR(); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + DECODE_PRINTF("INC\tESI\n"); + } else { + DECODE_PRINTF("INC\tSI\n"); + } + TRACE_AND_STEP(); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + M.x86.R_ESI = inc_long(M.x86.R_ESI); + } else { + M.x86.R_SI = inc_word(M.x86.R_SI); + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x47 +****************************************************************************/ +static void x86emuOp_inc_DI(u8 X86EMU_UNUSED(op1)) +{ + START_OF_INSTR(); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + DECODE_PRINTF("INC\tEDI\n"); + } else { + DECODE_PRINTF("INC\tDI\n"); + } + TRACE_AND_STEP(); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + M.x86.R_EDI = inc_long(M.x86.R_EDI); + } else { + M.x86.R_DI = inc_word(M.x86.R_DI); + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x48 +****************************************************************************/ +static void x86emuOp_dec_AX(u8 X86EMU_UNUSED(op1)) +{ + START_OF_INSTR(); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + DECODE_PRINTF("DEC\tEAX\n"); + } else { + DECODE_PRINTF("DEC\tAX\n"); + } + TRACE_AND_STEP(); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + M.x86.R_EAX = dec_long(M.x86.R_EAX); + } else { + M.x86.R_AX = dec_word(M.x86.R_AX); + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x49 +****************************************************************************/ +static void x86emuOp_dec_CX(u8 X86EMU_UNUSED(op1)) +{ + START_OF_INSTR(); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + DECODE_PRINTF("DEC\tECX\n"); + } else { + DECODE_PRINTF("DEC\tCX\n"); + } + TRACE_AND_STEP(); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + M.x86.R_ECX = dec_long(M.x86.R_ECX); + } else { + M.x86.R_CX = dec_word(M.x86.R_CX); + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x4a +****************************************************************************/ +static void x86emuOp_dec_DX(u8 X86EMU_UNUSED(op1)) +{ + START_OF_INSTR(); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + DECODE_PRINTF("DEC\tEDX\n"); + } else { + DECODE_PRINTF("DEC\tDX\n"); + } + TRACE_AND_STEP(); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + M.x86.R_EDX = dec_long(M.x86.R_EDX); + } else { + M.x86.R_DX = dec_word(M.x86.R_DX); + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x4b +****************************************************************************/ +static void x86emuOp_dec_BX(u8 X86EMU_UNUSED(op1)) +{ + START_OF_INSTR(); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + DECODE_PRINTF("DEC\tEBX\n"); + } else { + DECODE_PRINTF("DEC\tBX\n"); + } + TRACE_AND_STEP(); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + M.x86.R_EBX = dec_long(M.x86.R_EBX); + } else { + M.x86.R_BX = dec_word(M.x86.R_BX); + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x4c +****************************************************************************/ +static void x86emuOp_dec_SP(u8 X86EMU_UNUSED(op1)) +{ + START_OF_INSTR(); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + DECODE_PRINTF("DEC\tESP\n"); + } else { + DECODE_PRINTF("DEC\tSP\n"); + } + TRACE_AND_STEP(); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + M.x86.R_ESP = dec_long(M.x86.R_ESP); + } else { + M.x86.R_SP = dec_word(M.x86.R_SP); + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x4d +****************************************************************************/ +static void x86emuOp_dec_BP(u8 X86EMU_UNUSED(op1)) +{ + START_OF_INSTR(); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + DECODE_PRINTF("DEC\tEBP\n"); + } else { + DECODE_PRINTF("DEC\tBP\n"); + } + TRACE_AND_STEP(); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + M.x86.R_EBP = dec_long(M.x86.R_EBP); + } else { + M.x86.R_BP = dec_word(M.x86.R_BP); + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x4e +****************************************************************************/ +static void x86emuOp_dec_SI(u8 X86EMU_UNUSED(op1)) +{ + START_OF_INSTR(); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + DECODE_PRINTF("DEC\tESI\n"); + } else { + DECODE_PRINTF("DEC\tSI\n"); + } + TRACE_AND_STEP(); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + M.x86.R_ESI = dec_long(M.x86.R_ESI); + } else { + M.x86.R_SI = dec_word(M.x86.R_SI); + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x4f +****************************************************************************/ +static void x86emuOp_dec_DI(u8 X86EMU_UNUSED(op1)) +{ + START_OF_INSTR(); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + DECODE_PRINTF("DEC\tEDI\n"); + } else { + DECODE_PRINTF("DEC\tDI\n"); + } + TRACE_AND_STEP(); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + M.x86.R_EDI = dec_long(M.x86.R_EDI); + } else { + M.x86.R_DI = dec_word(M.x86.R_DI); + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x50 +****************************************************************************/ +static void x86emuOp_push_AX(u8 X86EMU_UNUSED(op1)) +{ + START_OF_INSTR(); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + DECODE_PRINTF("PUSH\tEAX\n"); + } else { + DECODE_PRINTF("PUSH\tAX\n"); + } + TRACE_AND_STEP(); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + push_long(M.x86.R_EAX); + } else { + push_word(M.x86.R_AX); + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x51 +****************************************************************************/ +static void x86emuOp_push_CX(u8 X86EMU_UNUSED(op1)) +{ + START_OF_INSTR(); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + DECODE_PRINTF("PUSH\tECX\n"); + } else { + DECODE_PRINTF("PUSH\tCX\n"); + } + TRACE_AND_STEP(); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + push_long(M.x86.R_ECX); + } else { + push_word(M.x86.R_CX); + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x52 +****************************************************************************/ +static void x86emuOp_push_DX(u8 X86EMU_UNUSED(op1)) +{ + START_OF_INSTR(); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + DECODE_PRINTF("PUSH\tEDX\n"); + } else { + DECODE_PRINTF("PUSH\tDX\n"); + } + TRACE_AND_STEP(); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + push_long(M.x86.R_EDX); + } else { + push_word(M.x86.R_DX); + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x53 +****************************************************************************/ +static void x86emuOp_push_BX(u8 X86EMU_UNUSED(op1)) +{ + START_OF_INSTR(); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + DECODE_PRINTF("PUSH\tEBX\n"); + } else { + DECODE_PRINTF("PUSH\tBX\n"); + } + TRACE_AND_STEP(); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + push_long(M.x86.R_EBX); + } else { + push_word(M.x86.R_BX); + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x54 +****************************************************************************/ +static void x86emuOp_push_SP(u8 X86EMU_UNUSED(op1)) +{ + START_OF_INSTR(); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + DECODE_PRINTF("PUSH\tESP\n"); + } else { + DECODE_PRINTF("PUSH\tSP\n"); + } + TRACE_AND_STEP(); + /* Always push (E)SP, since we are emulating an i386 and above + * processor. This is necessary as some BIOS'es use this to check + * what type of processor is in the system. + */ + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + push_long(M.x86.R_ESP); + } else { + push_word((u16)(M.x86.R_SP)); + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x55 +****************************************************************************/ +static void x86emuOp_push_BP(u8 X86EMU_UNUSED(op1)) +{ + START_OF_INSTR(); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + DECODE_PRINTF("PUSH\tEBP\n"); + } else { + DECODE_PRINTF("PUSH\tBP\n"); + } + TRACE_AND_STEP(); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + push_long(M.x86.R_EBP); + } else { + push_word(M.x86.R_BP); + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x56 +****************************************************************************/ +static void x86emuOp_push_SI(u8 X86EMU_UNUSED(op1)) +{ + START_OF_INSTR(); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + DECODE_PRINTF("PUSH\tESI\n"); + } else { + DECODE_PRINTF("PUSH\tSI\n"); + } + TRACE_AND_STEP(); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + push_long(M.x86.R_ESI); + } else { + push_word(M.x86.R_SI); + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x57 +****************************************************************************/ +static void x86emuOp_push_DI(u8 X86EMU_UNUSED(op1)) +{ + START_OF_INSTR(); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + DECODE_PRINTF("PUSH\tEDI\n"); + } else { + DECODE_PRINTF("PUSH\tDI\n"); + } + TRACE_AND_STEP(); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + push_long(M.x86.R_EDI); + } else { + push_word(M.x86.R_DI); + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x58 +****************************************************************************/ +static void x86emuOp_pop_AX(u8 X86EMU_UNUSED(op1)) +{ + START_OF_INSTR(); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + DECODE_PRINTF("POP\tEAX\n"); + } else { + DECODE_PRINTF("POP\tAX\n"); + } + TRACE_AND_STEP(); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + M.x86.R_EAX = pop_long(); + } else { + M.x86.R_AX = pop_word(); + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x59 +****************************************************************************/ +static void x86emuOp_pop_CX(u8 X86EMU_UNUSED(op1)) +{ + START_OF_INSTR(); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + DECODE_PRINTF("POP\tECX\n"); + } else { + DECODE_PRINTF("POP\tCX\n"); + } + TRACE_AND_STEP(); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + M.x86.R_ECX = pop_long(); + } else { + M.x86.R_CX = pop_word(); + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x5a +****************************************************************************/ +static void x86emuOp_pop_DX(u8 X86EMU_UNUSED(op1)) +{ + START_OF_INSTR(); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + DECODE_PRINTF("POP\tEDX\n"); + } else { + DECODE_PRINTF("POP\tDX\n"); + } + TRACE_AND_STEP(); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + M.x86.R_EDX = pop_long(); + } else { + M.x86.R_DX = pop_word(); + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x5b +****************************************************************************/ +static void x86emuOp_pop_BX(u8 X86EMU_UNUSED(op1)) +{ + START_OF_INSTR(); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + DECODE_PRINTF("POP\tEBX\n"); + } else { + DECODE_PRINTF("POP\tBX\n"); + } + TRACE_AND_STEP(); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + M.x86.R_EBX = pop_long(); + } else { + M.x86.R_BX = pop_word(); + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x5c +****************************************************************************/ +static void x86emuOp_pop_SP(u8 X86EMU_UNUSED(op1)) +{ + START_OF_INSTR(); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + DECODE_PRINTF("POP\tESP\n"); + } else { + DECODE_PRINTF("POP\tSP\n"); + } + TRACE_AND_STEP(); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + M.x86.R_ESP = pop_long(); + } else { + M.x86.R_SP = pop_word(); + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x5d +****************************************************************************/ +static void x86emuOp_pop_BP(u8 X86EMU_UNUSED(op1)) +{ + START_OF_INSTR(); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + DECODE_PRINTF("POP\tEBP\n"); + } else { + DECODE_PRINTF("POP\tBP\n"); + } + TRACE_AND_STEP(); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + M.x86.R_EBP = pop_long(); + } else { + M.x86.R_BP = pop_word(); + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x5e +****************************************************************************/ +static void x86emuOp_pop_SI(u8 X86EMU_UNUSED(op1)) +{ + START_OF_INSTR(); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + DECODE_PRINTF("POP\tESI\n"); + } else { + DECODE_PRINTF("POP\tSI\n"); + } + TRACE_AND_STEP(); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + M.x86.R_ESI = pop_long(); + } else { + M.x86.R_SI = pop_word(); + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x5f +****************************************************************************/ +static void x86emuOp_pop_DI(u8 X86EMU_UNUSED(op1)) +{ + START_OF_INSTR(); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + DECODE_PRINTF("POP\tEDI\n"); + } else { + DECODE_PRINTF("POP\tDI\n"); + } + TRACE_AND_STEP(); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + M.x86.R_EDI = pop_long(); + } else { + M.x86.R_DI = pop_word(); + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x60 +****************************************************************************/ +static void x86emuOp_push_all(u8 X86EMU_UNUSED(op1)) +{ + START_OF_INSTR(); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + DECODE_PRINTF("PUSHAD\n"); + } else { + DECODE_PRINTF("PUSHA\n"); + } + TRACE_AND_STEP(); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 old_sp = M.x86.R_ESP; + + push_long(M.x86.R_EAX); + push_long(M.x86.R_ECX); + push_long(M.x86.R_EDX); + push_long(M.x86.R_EBX); + push_long(old_sp); + push_long(M.x86.R_EBP); + push_long(M.x86.R_ESI); + push_long(M.x86.R_EDI); + } else { + u16 old_sp = M.x86.R_SP; + + push_word(M.x86.R_AX); + push_word(M.x86.R_CX); + push_word(M.x86.R_DX); + push_word(M.x86.R_BX); + push_word(old_sp); + push_word(M.x86.R_BP); + push_word(M.x86.R_SI); + push_word(M.x86.R_DI); + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x61 +****************************************************************************/ +static void x86emuOp_pop_all(u8 X86EMU_UNUSED(op1)) +{ + START_OF_INSTR(); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + DECODE_PRINTF("POPAD\n"); + } else { + DECODE_PRINTF("POPA\n"); + } + TRACE_AND_STEP(); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + M.x86.R_EDI = pop_long(); + M.x86.R_ESI = pop_long(); + M.x86.R_EBP = pop_long(); + M.x86.R_ESP += 4; /* skip ESP */ + M.x86.R_EBX = pop_long(); + M.x86.R_EDX = pop_long(); + M.x86.R_ECX = pop_long(); + M.x86.R_EAX = pop_long(); + } else { + M.x86.R_DI = pop_word(); + M.x86.R_SI = pop_word(); + M.x86.R_BP = pop_word(); + M.x86.R_SP += 2; /* skip SP */ + M.x86.R_BX = pop_word(); + M.x86.R_DX = pop_word(); + M.x86.R_CX = pop_word(); + M.x86.R_AX = pop_word(); + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/*opcode 0x62 ILLEGAL OP, calls x86emuOp_illegal_op() */ +/*opcode 0x63 ILLEGAL OP, calls x86emuOp_illegal_op() */ + +/**************************************************************************** +REMARKS: +Handles opcode 0x64 +****************************************************************************/ +static void x86emuOp_segovr_FS(u8 X86EMU_UNUSED(op1)) +{ + START_OF_INSTR(); + DECODE_PRINTF("FS:\n"); + TRACE_AND_STEP(); + M.x86.mode |= SYSMODE_SEGOVR_FS; + /* + * note the lack of DECODE_CLEAR_SEGOVR(r) since, here is one of 4 + * opcode subroutines we do not want to do this. + */ + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x65 +****************************************************************************/ +static void x86emuOp_segovr_GS(u8 X86EMU_UNUSED(op1)) +{ + START_OF_INSTR(); + DECODE_PRINTF("GS:\n"); + TRACE_AND_STEP(); + M.x86.mode |= SYSMODE_SEGOVR_GS; + /* + * note the lack of DECODE_CLEAR_SEGOVR(r) since, here is one of 4 + * opcode subroutines we do not want to do this. + */ + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x66 - prefix for 32-bit register +****************************************************************************/ +static void x86emuOp_prefix_data(u8 X86EMU_UNUSED(op1)) +{ + START_OF_INSTR(); + DECODE_PRINTF("DATA:\n"); + TRACE_AND_STEP(); + M.x86.mode |= SYSMODE_PREFIX_DATA; + /* note no DECODE_CLEAR_SEGOVR here. */ + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x67 - prefix for 32-bit address +****************************************************************************/ +static void x86emuOp_prefix_addr(u8 X86EMU_UNUSED(op1)) +{ + START_OF_INSTR(); + DECODE_PRINTF("ADDR:\n"); + TRACE_AND_STEP(); + M.x86.mode |= SYSMODE_PREFIX_ADDR; + /* note no DECODE_CLEAR_SEGOVR here. */ + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x68 +****************************************************************************/ +static void x86emuOp_push_word_IMM(u8 X86EMU_UNUSED(op1)) +{ + u32 imm; + + START_OF_INSTR(); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + imm = fetch_long_imm(); + } else { + imm = fetch_word_imm(); + } + DECODE_PRINTF2("PUSH\t%x\n", imm); + TRACE_AND_STEP(); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + push_long(imm); + } else { + push_word((u16)imm); + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x69 +****************************************************************************/ +static void x86emuOp_imul_word_IMM(u8 X86EMU_UNUSED(op1)) +{ + int mod, rl, rh; + uint srcoffset; + + START_OF_INSTR(); + DECODE_PRINTF("IMUL\t"); + FETCH_DECODE_MODRM(mod, rh, rl); + switch (mod) { + case 0: + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 *destreg; + u32 srcval; + u32 res_lo,res_hi; + s32 imm; + + destreg = DECODE_RM_LONG_REGISTER(rh); + DECODE_PRINTF(","); + srcoffset = decode_rm00_address(rl); + srcval = fetch_data_long(srcoffset); + imm = fetch_long_imm(); + DECODE_PRINTF2(",%d\n", (s32)imm); + TRACE_AND_STEP(); + imul_long_direct(&res_lo,&res_hi,(s32)srcval,(s32)imm); + if (res_hi != 0) { + SET_FLAG(F_CF); + SET_FLAG(F_OF); + } else { + CLEAR_FLAG(F_CF); + CLEAR_FLAG(F_OF); + } + *destreg = (u32)res_lo; + } else { + u16 *destreg; + u16 srcval; + u32 res; + s16 imm; + + destreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF(","); + srcoffset = decode_rm00_address(rl); + srcval = fetch_data_word(srcoffset); + imm = fetch_word_imm(); + DECODE_PRINTF2(",%d\n", (s32)imm); + TRACE_AND_STEP(); + res = (s16)srcval * (s16)imm; + if (res > 0xFFFF) { + SET_FLAG(F_CF); + SET_FLAG(F_OF); + } else { + CLEAR_FLAG(F_CF); + CLEAR_FLAG(F_OF); + } + *destreg = (u16)res; + } + break; + case 1: + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 *destreg; + u32 srcval; + u32 res_lo,res_hi; + s32 imm; + + destreg = DECODE_RM_LONG_REGISTER(rh); + DECODE_PRINTF(","); + srcoffset = decode_rm01_address(rl); + srcval = fetch_data_long(srcoffset); + imm = fetch_long_imm(); + DECODE_PRINTF2(",%d\n", (s32)imm); + TRACE_AND_STEP(); + imul_long_direct(&res_lo,&res_hi,(s32)srcval,(s32)imm); + if (res_hi != 0) { + SET_FLAG(F_CF); + SET_FLAG(F_OF); + } else { + CLEAR_FLAG(F_CF); + CLEAR_FLAG(F_OF); + } + *destreg = (u32)res_lo; + } else { + u16 *destreg; + u16 srcval; + u32 res; + s16 imm; + + destreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF(","); + srcoffset = decode_rm01_address(rl); + srcval = fetch_data_word(srcoffset); + imm = fetch_word_imm(); + DECODE_PRINTF2(",%d\n", (s32)imm); + TRACE_AND_STEP(); + res = (s16)srcval * (s16)imm; + if (res > 0xFFFF) { + SET_FLAG(F_CF); + SET_FLAG(F_OF); + } else { + CLEAR_FLAG(F_CF); + CLEAR_FLAG(F_OF); + } + *destreg = (u16)res; + } + break; + case 2: + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 *destreg; + u32 srcval; + u32 res_lo,res_hi; + s32 imm; + + destreg = DECODE_RM_LONG_REGISTER(rh); + DECODE_PRINTF(","); + srcoffset = decode_rm10_address(rl); + srcval = fetch_data_long(srcoffset); + imm = fetch_long_imm(); + DECODE_PRINTF2(",%d\n", (s32)imm); + TRACE_AND_STEP(); + imul_long_direct(&res_lo,&res_hi,(s32)srcval,(s32)imm); + if (res_hi != 0) { + SET_FLAG(F_CF); + SET_FLAG(F_OF); + } else { + CLEAR_FLAG(F_CF); + CLEAR_FLAG(F_OF); + } + *destreg = (u32)res_lo; + } else { + u16 *destreg; + u16 srcval; + u32 res; + s16 imm; + + destreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF(","); + srcoffset = decode_rm10_address(rl); + srcval = fetch_data_word(srcoffset); + imm = fetch_word_imm(); + DECODE_PRINTF2(",%d\n", (s32)imm); + TRACE_AND_STEP(); + res = (s16)srcval * (s16)imm; + if (res > 0xFFFF) { + SET_FLAG(F_CF); + SET_FLAG(F_OF); + } else { + CLEAR_FLAG(F_CF); + CLEAR_FLAG(F_OF); + } + *destreg = (u16)res; + } + break; + case 3: /* register to register */ + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 *destreg,*srcreg; + u32 res_lo,res_hi; + s32 imm; + + destreg = DECODE_RM_LONG_REGISTER(rh); + DECODE_PRINTF(","); + srcreg = DECODE_RM_LONG_REGISTER(rl); + imm = fetch_long_imm(); + DECODE_PRINTF2(",%d\n", (s32)imm); + TRACE_AND_STEP(); + imul_long_direct(&res_lo,&res_hi,(s32)*srcreg,(s32)imm); + if (res_hi != 0) { + SET_FLAG(F_CF); + SET_FLAG(F_OF); + } else { + CLEAR_FLAG(F_CF); + CLEAR_FLAG(F_OF); + } + *destreg = (u32)res_lo; + } else { + u16 *destreg,*srcreg; + u32 res; + s16 imm; + + destreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF(","); + srcreg = DECODE_RM_WORD_REGISTER(rl); + imm = fetch_word_imm(); + DECODE_PRINTF2(",%d\n", (s32)imm); + res = (s16)*srcreg * (s16)imm; + if (res > 0xFFFF) { + SET_FLAG(F_CF); + SET_FLAG(F_OF); + } else { + CLEAR_FLAG(F_CF); + CLEAR_FLAG(F_OF); + } + *destreg = (u16)res; + } + break; + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x6a +****************************************************************************/ +static void x86emuOp_push_byte_IMM(u8 X86EMU_UNUSED(op1)) +{ + s16 imm; + + START_OF_INSTR(); + imm = (s8)fetch_byte_imm(); + DECODE_PRINTF2("PUSH\t%d\n", imm); + TRACE_AND_STEP(); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + push_long((s32)imm); + } else { + push_word(imm); + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x6b +****************************************************************************/ +static void x86emuOp_imul_byte_IMM(u8 X86EMU_UNUSED(op1)) +{ + int mod, rl, rh; + uint srcoffset; + s8 imm; + + START_OF_INSTR(); + DECODE_PRINTF("IMUL\t"); + FETCH_DECODE_MODRM(mod, rh, rl); + switch (mod) { + case 0: + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 *destreg; + u32 srcval; + u32 res_lo,res_hi; + + destreg = DECODE_RM_LONG_REGISTER(rh); + DECODE_PRINTF(","); + srcoffset = decode_rm00_address(rl); + srcval = fetch_data_long(srcoffset); + imm = fetch_byte_imm(); + DECODE_PRINTF2(",%d\n", (s32)imm); + TRACE_AND_STEP(); + imul_long_direct(&res_lo,&res_hi,(s32)srcval,(s32)imm); + if (res_hi != 0) { + SET_FLAG(F_CF); + SET_FLAG(F_OF); + } else { + CLEAR_FLAG(F_CF); + CLEAR_FLAG(F_OF); + } + *destreg = (u32)res_lo; + } else { + u16 *destreg; + u16 srcval; + u32 res; + + destreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF(","); + srcoffset = decode_rm00_address(rl); + srcval = fetch_data_word(srcoffset); + imm = fetch_byte_imm(); + DECODE_PRINTF2(",%d\n", (s32)imm); + TRACE_AND_STEP(); + res = (s16)srcval * (s16)imm; + if (res > 0xFFFF) { + SET_FLAG(F_CF); + SET_FLAG(F_OF); + } else { + CLEAR_FLAG(F_CF); + CLEAR_FLAG(F_OF); + } + *destreg = (u16)res; + } + break; + case 1: + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 *destreg; + u32 srcval; + u32 res_lo,res_hi; + + destreg = DECODE_RM_LONG_REGISTER(rh); + DECODE_PRINTF(","); + srcoffset = decode_rm01_address(rl); + srcval = fetch_data_long(srcoffset); + imm = fetch_byte_imm(); + DECODE_PRINTF2(",%d\n", (s32)imm); + TRACE_AND_STEP(); + imul_long_direct(&res_lo,&res_hi,(s32)srcval,(s32)imm); + if (res_hi != 0) { + SET_FLAG(F_CF); + SET_FLAG(F_OF); + } else { + CLEAR_FLAG(F_CF); + CLEAR_FLAG(F_OF); + } + *destreg = (u32)res_lo; + } else { + u16 *destreg; + u16 srcval; + u32 res; + + destreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF(","); + srcoffset = decode_rm01_address(rl); + srcval = fetch_data_word(srcoffset); + imm = fetch_byte_imm(); + DECODE_PRINTF2(",%d\n", (s32)imm); + TRACE_AND_STEP(); + res = (s16)srcval * (s16)imm; + if (res > 0xFFFF) { + SET_FLAG(F_CF); + SET_FLAG(F_OF); + } else { + CLEAR_FLAG(F_CF); + CLEAR_FLAG(F_OF); + } + *destreg = (u16)res; + } + break; + case 2: + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 *destreg; + u32 srcval; + u32 res_lo,res_hi; + + destreg = DECODE_RM_LONG_REGISTER(rh); + DECODE_PRINTF(","); + srcoffset = decode_rm10_address(rl); + srcval = fetch_data_long(srcoffset); + imm = fetch_byte_imm(); + DECODE_PRINTF2(",%d\n", (s32)imm); + TRACE_AND_STEP(); + imul_long_direct(&res_lo,&res_hi,(s32)srcval,(s32)imm); + if (res_hi != 0) { + SET_FLAG(F_CF); + SET_FLAG(F_OF); + } else { + CLEAR_FLAG(F_CF); + CLEAR_FLAG(F_OF); + } + *destreg = (u32)res_lo; + } else { + u16 *destreg; + u16 srcval; + u32 res; + + destreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF(","); + srcoffset = decode_rm10_address(rl); + srcval = fetch_data_word(srcoffset); + imm = fetch_byte_imm(); + DECODE_PRINTF2(",%d\n", (s32)imm); + TRACE_AND_STEP(); + res = (s16)srcval * (s16)imm; + if (res > 0xFFFF) { + SET_FLAG(F_CF); + SET_FLAG(F_OF); + } else { + CLEAR_FLAG(F_CF); + CLEAR_FLAG(F_OF); + } + *destreg = (u16)res; + } + break; + case 3: /* register to register */ + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 *destreg,*srcreg; + u32 res_lo,res_hi; + + destreg = DECODE_RM_LONG_REGISTER(rh); + DECODE_PRINTF(","); + srcreg = DECODE_RM_LONG_REGISTER(rl); + imm = fetch_byte_imm(); + DECODE_PRINTF2(",%d\n", (s32)imm); + TRACE_AND_STEP(); + imul_long_direct(&res_lo,&res_hi,(s32)*srcreg,(s32)imm); + if (res_hi != 0) { + SET_FLAG(F_CF); + SET_FLAG(F_OF); + } else { + CLEAR_FLAG(F_CF); + CLEAR_FLAG(F_OF); + } + *destreg = (u32)res_lo; + } else { + u16 *destreg,*srcreg; + u32 res; + + destreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF(","); + srcreg = DECODE_RM_WORD_REGISTER(rl); + imm = fetch_byte_imm(); + DECODE_PRINTF2(",%d\n", (s32)imm); + res = (s16)*srcreg * (s16)imm; + if (res > 0xFFFF) { + SET_FLAG(F_CF); + SET_FLAG(F_OF); + } else { + CLEAR_FLAG(F_CF); + CLEAR_FLAG(F_OF); + } + *destreg = (u16)res; + } + break; + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x6c +****************************************************************************/ +static void x86emuOp_ins_byte(u8 X86EMU_UNUSED(op1)) +{ + START_OF_INSTR(); + DECODE_PRINTF("INSB\n"); + ins(1); + TRACE_AND_STEP(); + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x6d +****************************************************************************/ +static void x86emuOp_ins_word(u8 X86EMU_UNUSED(op1)) +{ + START_OF_INSTR(); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + DECODE_PRINTF("INSD\n"); + ins(4); + } else { + DECODE_PRINTF("INSW\n"); + ins(2); + } + TRACE_AND_STEP(); + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x6e +****************************************************************************/ +static void x86emuOp_outs_byte(u8 X86EMU_UNUSED(op1)) +{ + START_OF_INSTR(); + DECODE_PRINTF("OUTSB\n"); + outs(1); + TRACE_AND_STEP(); + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x6f +****************************************************************************/ +static void x86emuOp_outs_word(u8 X86EMU_UNUSED(op1)) +{ + START_OF_INSTR(); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + DECODE_PRINTF("OUTSD\n"); + outs(4); + } else { + DECODE_PRINTF("OUTSW\n"); + outs(2); + } + TRACE_AND_STEP(); + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x70 +****************************************************************************/ +static void x86emuOp_jump_near_O(u8 X86EMU_UNUSED(op1)) +{ + s8 offset; + u16 target; + + /* jump to byte offset if overflow flag is set */ + START_OF_INSTR(); + DECODE_PRINTF("JO\t"); + offset = (s8)fetch_byte_imm(); + target = (u16)(M.x86.R_IP + (s16)offset); + DECODE_PRINTF2("%x\n", target); + TRACE_AND_STEP(); + if (ACCESS_FLAG(F_OF)) + M.x86.R_IP = target; + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x71 +****************************************************************************/ +static void x86emuOp_jump_near_NO(u8 X86EMU_UNUSED(op1)) +{ + s8 offset; + u16 target; + + /* jump to byte offset if overflow is not set */ + START_OF_INSTR(); + DECODE_PRINTF("JNO\t"); + offset = (s8)fetch_byte_imm(); + target = (u16)(M.x86.R_IP + (s16)offset); + DECODE_PRINTF2("%x\n", target); + TRACE_AND_STEP(); + if (!ACCESS_FLAG(F_OF)) + M.x86.R_IP = target; + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x72 +****************************************************************************/ +static void x86emuOp_jump_near_B(u8 X86EMU_UNUSED(op1)) +{ + s8 offset; + u16 target; + + /* jump to byte offset if carry flag is set. */ + START_OF_INSTR(); + DECODE_PRINTF("JB\t"); + offset = (s8)fetch_byte_imm(); + target = (u16)(M.x86.R_IP + (s16)offset); + DECODE_PRINTF2("%x\n", target); + TRACE_AND_STEP(); + if (ACCESS_FLAG(F_CF)) + M.x86.R_IP = target; + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x73 +****************************************************************************/ +static void x86emuOp_jump_near_NB(u8 X86EMU_UNUSED(op1)) +{ + s8 offset; + u16 target; + + /* jump to byte offset if carry flag is clear. */ + START_OF_INSTR(); + DECODE_PRINTF("JNB\t"); + offset = (s8)fetch_byte_imm(); + target = (u16)(M.x86.R_IP + (s16)offset); + DECODE_PRINTF2("%x\n", target); + TRACE_AND_STEP(); + if (!ACCESS_FLAG(F_CF)) + M.x86.R_IP = target; + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x74 +****************************************************************************/ +static void x86emuOp_jump_near_Z(u8 X86EMU_UNUSED(op1)) +{ + s8 offset; + u16 target; + + /* jump to byte offset if zero flag is set. */ + START_OF_INSTR(); + DECODE_PRINTF("JZ\t"); + offset = (s8)fetch_byte_imm(); + target = (u16)(M.x86.R_IP + (s16)offset); + DECODE_PRINTF2("%x\n", target); + TRACE_AND_STEP(); + if (ACCESS_FLAG(F_ZF)) + M.x86.R_IP = target; + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x75 +****************************************************************************/ +static void x86emuOp_jump_near_NZ(u8 X86EMU_UNUSED(op1)) +{ + s8 offset; + u16 target; + + /* jump to byte offset if zero flag is clear. */ + START_OF_INSTR(); + DECODE_PRINTF("JNZ\t"); + offset = (s8)fetch_byte_imm(); + target = (u16)(M.x86.R_IP + (s16)offset); + DECODE_PRINTF2("%x\n", target); + TRACE_AND_STEP(); + if (!ACCESS_FLAG(F_ZF)) + M.x86.R_IP = target; + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x76 +****************************************************************************/ +static void x86emuOp_jump_near_BE(u8 X86EMU_UNUSED(op1)) +{ + s8 offset; + u16 target; + + /* jump to byte offset if carry flag is set or if the zero + flag is set. */ + START_OF_INSTR(); + DECODE_PRINTF("JBE\t"); + offset = (s8)fetch_byte_imm(); + target = (u16)(M.x86.R_IP + (s16)offset); + DECODE_PRINTF2("%x\n", target); + TRACE_AND_STEP(); + if (ACCESS_FLAG(F_CF) || ACCESS_FLAG(F_ZF)) + M.x86.R_IP = target; + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x77 +****************************************************************************/ +static void x86emuOp_jump_near_NBE(u8 X86EMU_UNUSED(op1)) +{ + s8 offset; + u16 target; + + /* jump to byte offset if carry flag is clear and if the zero + flag is clear */ + START_OF_INSTR(); + DECODE_PRINTF("JNBE\t"); + offset = (s8)fetch_byte_imm(); + target = (u16)(M.x86.R_IP + (s16)offset); + DECODE_PRINTF2("%x\n", target); + TRACE_AND_STEP(); + if (!(ACCESS_FLAG(F_CF) || ACCESS_FLAG(F_ZF))) + M.x86.R_IP = target; + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x78 +****************************************************************************/ +static void x86emuOp_jump_near_S(u8 X86EMU_UNUSED(op1)) +{ + s8 offset; + u16 target; + + /* jump to byte offset if sign flag is set */ + START_OF_INSTR(); + DECODE_PRINTF("JS\t"); + offset = (s8)fetch_byte_imm(); + target = (u16)(M.x86.R_IP + (s16)offset); + DECODE_PRINTF2("%x\n", target); + TRACE_AND_STEP(); + if (ACCESS_FLAG(F_SF)) + M.x86.R_IP = target; + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x79 +****************************************************************************/ +static void x86emuOp_jump_near_NS(u8 X86EMU_UNUSED(op1)) +{ + s8 offset; + u16 target; + + /* jump to byte offset if sign flag is clear */ + START_OF_INSTR(); + DECODE_PRINTF("JNS\t"); + offset = (s8)fetch_byte_imm(); + target = (u16)(M.x86.R_IP + (s16)offset); + DECODE_PRINTF2("%x\n", target); + TRACE_AND_STEP(); + if (!ACCESS_FLAG(F_SF)) + M.x86.R_IP = target; + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x7a +****************************************************************************/ +static void x86emuOp_jump_near_P(u8 X86EMU_UNUSED(op1)) +{ + s8 offset; + u16 target; + + /* jump to byte offset if parity flag is set (even parity) */ + START_OF_INSTR(); + DECODE_PRINTF("JP\t"); + offset = (s8)fetch_byte_imm(); + target = (u16)(M.x86.R_IP + (s16)offset); + DECODE_PRINTF2("%x\n", target); + TRACE_AND_STEP(); + if (ACCESS_FLAG(F_PF)) + M.x86.R_IP = target; + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x7b +****************************************************************************/ +static void x86emuOp_jump_near_NP(u8 X86EMU_UNUSED(op1)) +{ + s8 offset; + u16 target; + + /* jump to byte offset if parity flag is clear (odd parity) */ + START_OF_INSTR(); + DECODE_PRINTF("JNP\t"); + offset = (s8)fetch_byte_imm(); + target = (u16)(M.x86.R_IP + (s16)offset); + DECODE_PRINTF2("%x\n", target); + TRACE_AND_STEP(); + if (!ACCESS_FLAG(F_PF)) + M.x86.R_IP = target; + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x7c +****************************************************************************/ +static void x86emuOp_jump_near_L(u8 X86EMU_UNUSED(op1)) +{ + s8 offset; + u16 target; + int sf, of; + + /* jump to byte offset if sign flag not equal to overflow flag. */ + START_OF_INSTR(); + DECODE_PRINTF("JL\t"); + offset = (s8)fetch_byte_imm(); + target = (u16)(M.x86.R_IP + (s16)offset); + DECODE_PRINTF2("%x\n", target); + TRACE_AND_STEP(); + sf = ACCESS_FLAG(F_SF) != 0; + of = ACCESS_FLAG(F_OF) != 0; + if (sf ^ of) + M.x86.R_IP = target; + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x7d +****************************************************************************/ +static void x86emuOp_jump_near_NL(u8 X86EMU_UNUSED(op1)) +{ + s8 offset; + u16 target; + int sf, of; + + /* jump to byte offset if sign flag not equal to overflow flag. */ + START_OF_INSTR(); + DECODE_PRINTF("JNL\t"); + offset = (s8)fetch_byte_imm(); + target = (u16)(M.x86.R_IP + (s16)offset); + DECODE_PRINTF2("%x\n", target); + TRACE_AND_STEP(); + sf = ACCESS_FLAG(F_SF) != 0; + of = ACCESS_FLAG(F_OF) != 0; + /* note: inverse of above, but using == instead of xor. */ + if (sf == of) + M.x86.R_IP = target; + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x7e +****************************************************************************/ +static void x86emuOp_jump_near_LE(u8 X86EMU_UNUSED(op1)) +{ + s8 offset; + u16 target; + int sf, of; + + /* jump to byte offset if sign flag not equal to overflow flag + or the zero flag is set */ + START_OF_INSTR(); + DECODE_PRINTF("JLE\t"); + offset = (s8)fetch_byte_imm(); + target = (u16)(M.x86.R_IP + (s16)offset); + DECODE_PRINTF2("%x\n", target); + TRACE_AND_STEP(); + sf = ACCESS_FLAG(F_SF) != 0; + of = ACCESS_FLAG(F_OF) != 0; + if ((sf ^ of) || ACCESS_FLAG(F_ZF)) + M.x86.R_IP = target; + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x7f +****************************************************************************/ +static void x86emuOp_jump_near_NLE(u8 X86EMU_UNUSED(op1)) +{ + s8 offset; + u16 target; + int sf, of; + + /* jump to byte offset if sign flag equal to overflow flag. + and the zero flag is clear */ + START_OF_INSTR(); + DECODE_PRINTF("JNLE\t"); + offset = (s8)fetch_byte_imm(); + target = (u16)(M.x86.R_IP + (s16)offset); + DECODE_PRINTF2("%x\n", target); + TRACE_AND_STEP(); + sf = ACCESS_FLAG(F_SF) != 0; + of = ACCESS_FLAG(F_OF) != 0; + if ((sf == of) && !ACCESS_FLAG(F_ZF)) + M.x86.R_IP = target; + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +static u8 (*opc80_byte_operation[])(u8 d, u8 s) = +{ + add_byte, /* 00 */ + or_byte, /* 01 */ + adc_byte, /* 02 */ + sbb_byte, /* 03 */ + and_byte, /* 04 */ + sub_byte, /* 05 */ + xor_byte, /* 06 */ + cmp_byte, /* 07 */ +}; + +/**************************************************************************** +REMARKS: +Handles opcode 0x80 +****************************************************************************/ +static void x86emuOp_opc80_byte_RM_IMM(u8 X86EMU_UNUSED(op1)) +{ + int mod, rl, rh; + u8 *destreg; + uint destoffset; + u8 imm; + u8 destval; + + /* + * Weirdo special case instruction format. Part of the opcode + * held below in "RH". Doubly nested case would result, except + * that the decoded instruction + */ + START_OF_INSTR(); + FETCH_DECODE_MODRM(mod, rh, rl); +#ifdef X86EMU_DEBUG + if (DEBUG_DECODE()) { + /* XXX DECODE_PRINTF may be changed to something more + general, so that it is important to leave the strings + in the same format, even though the result is that the + above test is done twice. */ + + switch (rh) { + case 0: + DECODE_PRINTF("ADD\t"); + break; + case 1: + DECODE_PRINTF("OR\t"); + break; + case 2: + DECODE_PRINTF("ADC\t"); + break; + case 3: + DECODE_PRINTF("SBB\t"); + break; + case 4: + DECODE_PRINTF("AND\t"); + break; + case 5: + DECODE_PRINTF("SUB\t"); + break; + case 6: + DECODE_PRINTF("XOR\t"); + break; + case 7: + DECODE_PRINTF("CMP\t"); + break; + } + } +#endif + /* know operation, decode the mod byte to find the addressing + mode. */ + switch (mod) { + case 0: + DECODE_PRINTF("BYTE PTR "); + destoffset = decode_rm00_address(rl); + DECODE_PRINTF(","); + destval = fetch_data_byte(destoffset); + imm = fetch_byte_imm(); + DECODE_PRINTF2("%x\n", imm); + TRACE_AND_STEP(); + destval = (*opc80_byte_operation[rh]) (destval, imm); + if (rh != 7) + store_data_byte(destoffset, destval); + break; + case 1: + DECODE_PRINTF("BYTE PTR "); + destoffset = decode_rm01_address(rl); + DECODE_PRINTF(","); + destval = fetch_data_byte(destoffset); + imm = fetch_byte_imm(); + DECODE_PRINTF2("%x\n", imm); + TRACE_AND_STEP(); + destval = (*opc80_byte_operation[rh]) (destval, imm); + if (rh != 7) + store_data_byte(destoffset, destval); + break; + case 2: + DECODE_PRINTF("BYTE PTR "); + destoffset = decode_rm10_address(rl); + DECODE_PRINTF(","); + destval = fetch_data_byte(destoffset); + imm = fetch_byte_imm(); + DECODE_PRINTF2("%x\n", imm); + TRACE_AND_STEP(); + destval = (*opc80_byte_operation[rh]) (destval, imm); + if (rh != 7) + store_data_byte(destoffset, destval); + break; + case 3: /* register to register */ + destreg = DECODE_RM_BYTE_REGISTER(rl); + DECODE_PRINTF(","); + imm = fetch_byte_imm(); + DECODE_PRINTF2("%x\n", imm); + TRACE_AND_STEP(); + destval = (*opc80_byte_operation[rh]) (*destreg, imm); + if (rh != 7) + *destreg = destval; + break; + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +static u16 (*opc81_word_operation[])(u16 d, u16 s) = +{ + add_word, /*00 */ + or_word, /*01 */ + adc_word, /*02 */ + sbb_word, /*03 */ + and_word, /*04 */ + sub_word, /*05 */ + xor_word, /*06 */ + cmp_word, /*07 */ +}; + +static u32 (*opc81_long_operation[])(u32 d, u32 s) = +{ + add_long, /*00 */ + or_long, /*01 */ + adc_long, /*02 */ + sbb_long, /*03 */ + and_long, /*04 */ + sub_long, /*05 */ + xor_long, /*06 */ + cmp_long, /*07 */ +}; + +/**************************************************************************** +REMARKS: +Handles opcode 0x81 +****************************************************************************/ +static void x86emuOp_opc81_word_RM_IMM(u8 X86EMU_UNUSED(op1)) +{ + int mod, rl, rh; + uint destoffset; + + /* + * Weirdo special case instruction format. Part of the opcode + * held below in "RH". Doubly nested case would result, except + * that the decoded instruction + */ + START_OF_INSTR(); + FETCH_DECODE_MODRM(mod, rh, rl); +#ifdef X86EMU_DEBUG + if (DEBUG_DECODE()) { + /* XXX DECODE_PRINTF may be changed to something more + general, so that it is important to leave the strings + in the same format, even though the result is that the + above test is done twice. */ + + switch (rh) { + case 0: + DECODE_PRINTF("ADD\t"); + break; + case 1: + DECODE_PRINTF("OR\t"); + break; + case 2: + DECODE_PRINTF("ADC\t"); + break; + case 3: + DECODE_PRINTF("SBB\t"); + break; + case 4: + DECODE_PRINTF("AND\t"); + break; + case 5: + DECODE_PRINTF("SUB\t"); + break; + case 6: + DECODE_PRINTF("XOR\t"); + break; + case 7: + DECODE_PRINTF("CMP\t"); + break; + } + } +#endif + /* + * Know operation, decode the mod byte to find the addressing + * mode. + */ + switch (mod) { + case 0: + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 destval,imm; + + DECODE_PRINTF("DWORD PTR "); + destoffset = decode_rm00_address(rl); + DECODE_PRINTF(","); + destval = fetch_data_long(destoffset); + imm = fetch_long_imm(); + DECODE_PRINTF2("%x\n", imm); + TRACE_AND_STEP(); + destval = (*opc81_long_operation[rh]) (destval, imm); + if (rh != 7) + store_data_long(destoffset, destval); + } else { + u16 destval,imm; + + DECODE_PRINTF("WORD PTR "); + destoffset = decode_rm00_address(rl); + DECODE_PRINTF(","); + destval = fetch_data_word(destoffset); + imm = fetch_word_imm(); + DECODE_PRINTF2("%x\n", imm); + TRACE_AND_STEP(); + destval = (*opc81_word_operation[rh]) (destval, imm); + if (rh != 7) + store_data_word(destoffset, destval); + } + break; + case 1: + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 destval,imm; + + DECODE_PRINTF("DWORD PTR "); + destoffset = decode_rm01_address(rl); + DECODE_PRINTF(","); + destval = fetch_data_long(destoffset); + imm = fetch_long_imm(); + DECODE_PRINTF2("%x\n", imm); + TRACE_AND_STEP(); + destval = (*opc81_long_operation[rh]) (destval, imm); + if (rh != 7) + store_data_long(destoffset, destval); + } else { + u16 destval,imm; + + DECODE_PRINTF("WORD PTR "); + destoffset = decode_rm01_address(rl); + DECODE_PRINTF(","); + destval = fetch_data_word(destoffset); + imm = fetch_word_imm(); + DECODE_PRINTF2("%x\n", imm); + TRACE_AND_STEP(); + destval = (*opc81_word_operation[rh]) (destval, imm); + if (rh != 7) + store_data_word(destoffset, destval); + } + break; + case 2: + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 destval,imm; + + DECODE_PRINTF("DWORD PTR "); + destoffset = decode_rm10_address(rl); + DECODE_PRINTF(","); + destval = fetch_data_long(destoffset); + imm = fetch_long_imm(); + DECODE_PRINTF2("%x\n", imm); + TRACE_AND_STEP(); + destval = (*opc81_long_operation[rh]) (destval, imm); + if (rh != 7) + store_data_long(destoffset, destval); + } else { + u16 destval,imm; + + DECODE_PRINTF("WORD PTR "); + destoffset = decode_rm10_address(rl); + DECODE_PRINTF(","); + destval = fetch_data_word(destoffset); + imm = fetch_word_imm(); + DECODE_PRINTF2("%x\n", imm); + TRACE_AND_STEP(); + destval = (*opc81_word_operation[rh]) (destval, imm); + if (rh != 7) + store_data_word(destoffset, destval); + } + break; + case 3: /* register to register */ + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 *destreg; + u32 destval,imm; + + destreg = DECODE_RM_LONG_REGISTER(rl); + DECODE_PRINTF(","); + imm = fetch_long_imm(); + DECODE_PRINTF2("%x\n", imm); + TRACE_AND_STEP(); + destval = (*opc81_long_operation[rh]) (*destreg, imm); + if (rh != 7) + *destreg = destval; + } else { + u16 *destreg; + u16 destval,imm; + + destreg = DECODE_RM_WORD_REGISTER(rl); + DECODE_PRINTF(","); + imm = fetch_word_imm(); + DECODE_PRINTF2("%x\n", imm); + TRACE_AND_STEP(); + destval = (*opc81_word_operation[rh]) (*destreg, imm); + if (rh != 7) + *destreg = destval; + } + break; + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +static u8 (*opc82_byte_operation[])(u8 s, u8 d) = +{ + add_byte, /*00 */ + or_byte, /*01 *//*YYY UNUSED ???? */ + adc_byte, /*02 */ + sbb_byte, /*03 */ + and_byte, /*04 *//*YYY UNUSED ???? */ + sub_byte, /*05 */ + xor_byte, /*06 *//*YYY UNUSED ???? */ + cmp_byte, /*07 */ +}; + +/**************************************************************************** +REMARKS: +Handles opcode 0x82 +****************************************************************************/ +static void x86emuOp_opc82_byte_RM_IMM(u8 X86EMU_UNUSED(op1)) +{ + int mod, rl, rh; + u8 *destreg; + uint destoffset; + u8 imm; + u8 destval; + + /* + * Weirdo special case instruction format. Part of the opcode + * held below in "RH". Doubly nested case would result, except + * that the decoded instruction Similar to opcode 81, except that + * the immediate byte is sign extended to a word length. + */ + START_OF_INSTR(); + FETCH_DECODE_MODRM(mod, rh, rl); +#ifdef X86EMU_DEBUG + if (DEBUG_DECODE()) { + /* XXX DECODE_PRINTF may be changed to something more + general, so that it is important to leave the strings + in the same format, even though the result is that the + above test is done twice. */ + switch (rh) { + case 0: + DECODE_PRINTF("ADD\t"); + break; + case 1: + DECODE_PRINTF("OR\t"); + break; + case 2: + DECODE_PRINTF("ADC\t"); + break; + case 3: + DECODE_PRINTF("SBB\t"); + break; + case 4: + DECODE_PRINTF("AND\t"); + break; + case 5: + DECODE_PRINTF("SUB\t"); + break; + case 6: + DECODE_PRINTF("XOR\t"); + break; + case 7: + DECODE_PRINTF("CMP\t"); + break; + } + } +#endif + /* know operation, decode the mod byte to find the addressing + mode. */ + switch (mod) { + case 0: + DECODE_PRINTF("BYTE PTR "); + destoffset = decode_rm00_address(rl); + destval = fetch_data_byte(destoffset); + imm = fetch_byte_imm(); + DECODE_PRINTF2(",%x\n", imm); + TRACE_AND_STEP(); + destval = (*opc82_byte_operation[rh]) (destval, imm); + if (rh != 7) + store_data_byte(destoffset, destval); + break; + case 1: + DECODE_PRINTF("BYTE PTR "); + destoffset = decode_rm01_address(rl); + destval = fetch_data_byte(destoffset); + imm = fetch_byte_imm(); + DECODE_PRINTF2(",%x\n", imm); + TRACE_AND_STEP(); + destval = (*opc82_byte_operation[rh]) (destval, imm); + if (rh != 7) + store_data_byte(destoffset, destval); + break; + case 2: + DECODE_PRINTF("BYTE PTR "); + destoffset = decode_rm10_address(rl); + destval = fetch_data_byte(destoffset); + imm = fetch_byte_imm(); + DECODE_PRINTF2(",%x\n", imm); + TRACE_AND_STEP(); + destval = (*opc82_byte_operation[rh]) (destval, imm); + if (rh != 7) + store_data_byte(destoffset, destval); + break; + case 3: /* register to register */ + destreg = DECODE_RM_BYTE_REGISTER(rl); + imm = fetch_byte_imm(); + DECODE_PRINTF2(",%x\n", imm); + TRACE_AND_STEP(); + destval = (*opc82_byte_operation[rh]) (*destreg, imm); + if (rh != 7) + *destreg = destval; + break; + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +static u16 (*opc83_word_operation[])(u16 s, u16 d) = +{ + add_word, /*00 */ + or_word, /*01 *//*YYY UNUSED ???? */ + adc_word, /*02 */ + sbb_word, /*03 */ + and_word, /*04 *//*YYY UNUSED ???? */ + sub_word, /*05 */ + xor_word, /*06 *//*YYY UNUSED ???? */ + cmp_word, /*07 */ +}; + +static u32 (*opc83_long_operation[])(u32 s, u32 d) = +{ + add_long, /*00 */ + or_long, /*01 *//*YYY UNUSED ???? */ + adc_long, /*02 */ + sbb_long, /*03 */ + and_long, /*04 *//*YYY UNUSED ???? */ + sub_long, /*05 */ + xor_long, /*06 *//*YYY UNUSED ???? */ + cmp_long, /*07 */ +}; + +/**************************************************************************** +REMARKS: +Handles opcode 0x83 +****************************************************************************/ +static void x86emuOp_opc83_word_RM_IMM(u8 X86EMU_UNUSED(op1)) +{ + int mod, rl, rh; + uint destoffset; + + /* + * Weirdo special case instruction format. Part of the opcode + * held below in "RH". Doubly nested case would result, except + * that the decoded instruction Similar to opcode 81, except that + * the immediate byte is sign extended to a word length. + */ + START_OF_INSTR(); + FETCH_DECODE_MODRM(mod, rh, rl); +#ifdef X86EMU_DEBUG + if (DEBUG_DECODE()) { + /* XXX DECODE_PRINTF may be changed to something more + general, so that it is important to leave the strings + in the same format, even though the result is that the + above test is done twice. */ + switch (rh) { + case 0: + DECODE_PRINTF("ADD\t"); + break; + case 1: + DECODE_PRINTF("OR\t"); + break; + case 2: + DECODE_PRINTF("ADC\t"); + break; + case 3: + DECODE_PRINTF("SBB\t"); + break; + case 4: + DECODE_PRINTF("AND\t"); + break; + case 5: + DECODE_PRINTF("SUB\t"); + break; + case 6: + DECODE_PRINTF("XOR\t"); + break; + case 7: + DECODE_PRINTF("CMP\t"); + break; + } + } +#endif + /* know operation, decode the mod byte to find the addressing + mode. */ + switch (mod) { + case 0: + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 destval,imm; + + DECODE_PRINTF("DWORD PTR "); + destoffset = decode_rm00_address(rl); + destval = fetch_data_long(destoffset); + imm = (s8) fetch_byte_imm(); + DECODE_PRINTF2(",%x\n", imm); + TRACE_AND_STEP(); + destval = (*opc83_long_operation[rh]) (destval, imm); + if (rh != 7) + store_data_long(destoffset, destval); + } else { + u16 destval,imm; + + DECODE_PRINTF("WORD PTR "); + destoffset = decode_rm00_address(rl); + destval = fetch_data_word(destoffset); + imm = (s8) fetch_byte_imm(); + DECODE_PRINTF2(",%x\n", imm); + TRACE_AND_STEP(); + destval = (*opc83_word_operation[rh]) (destval, imm); + if (rh != 7) + store_data_word(destoffset, destval); + } + break; + case 1: + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 destval,imm; + + DECODE_PRINTF("DWORD PTR "); + destoffset = decode_rm01_address(rl); + destval = fetch_data_long(destoffset); + imm = (s8) fetch_byte_imm(); + DECODE_PRINTF2(",%x\n", imm); + TRACE_AND_STEP(); + destval = (*opc83_long_operation[rh]) (destval, imm); + if (rh != 7) + store_data_long(destoffset, destval); + } else { + u16 destval,imm; + + DECODE_PRINTF("WORD PTR "); + destoffset = decode_rm01_address(rl); + destval = fetch_data_word(destoffset); + imm = (s8) fetch_byte_imm(); + DECODE_PRINTF2(",%x\n", imm); + TRACE_AND_STEP(); + destval = (*opc83_word_operation[rh]) (destval, imm); + if (rh != 7) + store_data_word(destoffset, destval); + } + break; + case 2: + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 destval,imm; + + DECODE_PRINTF("DWORD PTR "); + destoffset = decode_rm10_address(rl); + destval = fetch_data_long(destoffset); + imm = (s8) fetch_byte_imm(); + DECODE_PRINTF2(",%x\n", imm); + TRACE_AND_STEP(); + destval = (*opc83_long_operation[rh]) (destval, imm); + if (rh != 7) + store_data_long(destoffset, destval); + } else { + u16 destval,imm; + + DECODE_PRINTF("WORD PTR "); + destoffset = decode_rm10_address(rl); + destval = fetch_data_word(destoffset); + imm = (s8) fetch_byte_imm(); + DECODE_PRINTF2(",%x\n", imm); + TRACE_AND_STEP(); + destval = (*opc83_word_operation[rh]) (destval, imm); + if (rh != 7) + store_data_word(destoffset, destval); + } + break; + case 3: /* register to register */ + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 *destreg; + u32 destval,imm; + + destreg = DECODE_RM_LONG_REGISTER(rl); + imm = (s8) fetch_byte_imm(); + DECODE_PRINTF2(",%x\n", imm); + TRACE_AND_STEP(); + destval = (*opc83_long_operation[rh]) (*destreg, imm); + if (rh != 7) + *destreg = destval; + } else { + u16 *destreg; + u16 destval,imm; + + destreg = DECODE_RM_WORD_REGISTER(rl); + imm = (s8) fetch_byte_imm(); + DECODE_PRINTF2(",%x\n", imm); + TRACE_AND_STEP(); + destval = (*opc83_word_operation[rh]) (*destreg, imm); + if (rh != 7) + *destreg = destval; + } + break; + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x84 +****************************************************************************/ +static void x86emuOp_test_byte_RM_R(u8 X86EMU_UNUSED(op1)) +{ + int mod, rl, rh; + u8 *destreg, *srcreg; + uint destoffset; + u8 destval; + + START_OF_INSTR(); + DECODE_PRINTF("TEST\t"); + FETCH_DECODE_MODRM(mod, rh, rl); + switch (mod) { + case 0: + destoffset = decode_rm00_address(rl); + DECODE_PRINTF(","); + destval = fetch_data_byte(destoffset); + srcreg = DECODE_RM_BYTE_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + test_byte(destval, *srcreg); + break; + case 1: + destoffset = decode_rm01_address(rl); + DECODE_PRINTF(","); + destval = fetch_data_byte(destoffset); + srcreg = DECODE_RM_BYTE_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + test_byte(destval, *srcreg); + break; + case 2: + destoffset = decode_rm10_address(rl); + DECODE_PRINTF(","); + destval = fetch_data_byte(destoffset); + srcreg = DECODE_RM_BYTE_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + test_byte(destval, *srcreg); + break; + case 3: /* register to register */ + destreg = DECODE_RM_BYTE_REGISTER(rl); + DECODE_PRINTF(","); + srcreg = DECODE_RM_BYTE_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + test_byte(*destreg, *srcreg); + break; + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x85 +****************************************************************************/ +static void x86emuOp_test_word_RM_R(u8 X86EMU_UNUSED(op1)) +{ + int mod, rl, rh; + uint destoffset; + + START_OF_INSTR(); + DECODE_PRINTF("TEST\t"); + FETCH_DECODE_MODRM(mod, rh, rl); + switch (mod) { + case 0: + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 destval; + u32 *srcreg; + + destoffset = decode_rm00_address(rl); + DECODE_PRINTF(","); + destval = fetch_data_long(destoffset); + srcreg = DECODE_RM_LONG_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + test_long(destval, *srcreg); + } else { + u16 destval; + u16 *srcreg; + + destoffset = decode_rm00_address(rl); + DECODE_PRINTF(","); + destval = fetch_data_word(destoffset); + srcreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + test_word(destval, *srcreg); + } + break; + case 1: + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 destval; + u32 *srcreg; + + destoffset = decode_rm01_address(rl); + DECODE_PRINTF(","); + destval = fetch_data_long(destoffset); + srcreg = DECODE_RM_LONG_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + test_long(destval, *srcreg); + } else { + u16 destval; + u16 *srcreg; + + destoffset = decode_rm01_address(rl); + DECODE_PRINTF(","); + destval = fetch_data_word(destoffset); + srcreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + test_word(destval, *srcreg); + } + break; + case 2: + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 destval; + u32 *srcreg; + + destoffset = decode_rm10_address(rl); + DECODE_PRINTF(","); + destval = fetch_data_long(destoffset); + srcreg = DECODE_RM_LONG_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + test_long(destval, *srcreg); + } else { + u16 destval; + u16 *srcreg; + + destoffset = decode_rm10_address(rl); + DECODE_PRINTF(","); + destval = fetch_data_word(destoffset); + srcreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + test_word(destval, *srcreg); + } + break; + case 3: /* register to register */ + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 *destreg,*srcreg; + + destreg = DECODE_RM_LONG_REGISTER(rl); + DECODE_PRINTF(","); + srcreg = DECODE_RM_LONG_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + test_long(*destreg, *srcreg); + } else { + u16 *destreg,*srcreg; + + destreg = DECODE_RM_WORD_REGISTER(rl); + DECODE_PRINTF(","); + srcreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + test_word(*destreg, *srcreg); + } + break; + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x86 +****************************************************************************/ +static void x86emuOp_xchg_byte_RM_R(u8 X86EMU_UNUSED(op1)) +{ + int mod, rl, rh; + u8 *destreg, *srcreg; + uint destoffset; + u8 destval; + u8 tmp; + + START_OF_INSTR(); + DECODE_PRINTF("XCHG\t"); + FETCH_DECODE_MODRM(mod, rh, rl); + switch (mod) { + case 0: + destoffset = decode_rm00_address(rl); + DECODE_PRINTF(","); + destval = fetch_data_byte(destoffset); + srcreg = DECODE_RM_BYTE_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + tmp = *srcreg; + *srcreg = destval; + destval = tmp; + store_data_byte(destoffset, destval); + break; + case 1: + destoffset = decode_rm01_address(rl); + DECODE_PRINTF(","); + destval = fetch_data_byte(destoffset); + srcreg = DECODE_RM_BYTE_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + tmp = *srcreg; + *srcreg = destval; + destval = tmp; + store_data_byte(destoffset, destval); + break; + case 2: + destoffset = decode_rm10_address(rl); + DECODE_PRINTF(","); + destval = fetch_data_byte(destoffset); + srcreg = DECODE_RM_BYTE_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + tmp = *srcreg; + *srcreg = destval; + destval = tmp; + store_data_byte(destoffset, destval); + break; + case 3: /* register to register */ + destreg = DECODE_RM_BYTE_REGISTER(rl); + DECODE_PRINTF(","); + srcreg = DECODE_RM_BYTE_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + tmp = *srcreg; + *srcreg = *destreg; + *destreg = tmp; + break; + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x87 +****************************************************************************/ +static void x86emuOp_xchg_word_RM_R(u8 X86EMU_UNUSED(op1)) +{ + int mod, rl, rh; + uint destoffset; + + START_OF_INSTR(); + DECODE_PRINTF("XCHG\t"); + FETCH_DECODE_MODRM(mod, rh, rl); + switch (mod) { + case 0: + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 *srcreg; + u32 destval,tmp; + + destoffset = decode_rm00_address(rl); + DECODE_PRINTF(","); + destval = fetch_data_long(destoffset); + srcreg = DECODE_RM_LONG_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + tmp = *srcreg; + *srcreg = destval; + destval = tmp; + store_data_long(destoffset, destval); + } else { + u16 *srcreg; + u16 destval,tmp; + + destoffset = decode_rm00_address(rl); + DECODE_PRINTF(","); + destval = fetch_data_word(destoffset); + srcreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + tmp = *srcreg; + *srcreg = destval; + destval = tmp; + store_data_word(destoffset, destval); + } + break; + case 1: + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 *srcreg; + u32 destval,tmp; + + destoffset = decode_rm01_address(rl); + DECODE_PRINTF(","); + destval = fetch_data_long(destoffset); + srcreg = DECODE_RM_LONG_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + tmp = *srcreg; + *srcreg = destval; + destval = tmp; + store_data_long(destoffset, destval); + } else { + u16 *srcreg; + u16 destval,tmp; + + destoffset = decode_rm01_address(rl); + DECODE_PRINTF(","); + destval = fetch_data_word(destoffset); + srcreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + tmp = *srcreg; + *srcreg = destval; + destval = tmp; + store_data_word(destoffset, destval); + } + break; + case 2: + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 *srcreg; + u32 destval,tmp; + + destoffset = decode_rm10_address(rl); + DECODE_PRINTF(","); + destval = fetch_data_long(destoffset); + srcreg = DECODE_RM_LONG_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + tmp = *srcreg; + *srcreg = destval; + destval = tmp; + store_data_long(destoffset, destval); + } else { + u16 *srcreg; + u16 destval,tmp; + + destoffset = decode_rm10_address(rl); + DECODE_PRINTF(","); + destval = fetch_data_word(destoffset); + srcreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + tmp = *srcreg; + *srcreg = destval; + destval = tmp; + store_data_word(destoffset, destval); + } + break; + case 3: /* register to register */ + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 *destreg,*srcreg; + u32 tmp; + + destreg = DECODE_RM_LONG_REGISTER(rl); + DECODE_PRINTF(","); + srcreg = DECODE_RM_LONG_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + tmp = *srcreg; + *srcreg = *destreg; + *destreg = tmp; + } else { + u16 *destreg,*srcreg; + u16 tmp; + + destreg = DECODE_RM_WORD_REGISTER(rl); + DECODE_PRINTF(","); + srcreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + tmp = *srcreg; + *srcreg = *destreg; + *destreg = tmp; + } + break; + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x88 +****************************************************************************/ +static void x86emuOp_mov_byte_RM_R(u8 X86EMU_UNUSED(op1)) +{ + int mod, rl, rh; + u8 *destreg, *srcreg; + uint destoffset; + + START_OF_INSTR(); + DECODE_PRINTF("MOV\t"); + FETCH_DECODE_MODRM(mod, rh, rl); + switch (mod) { + case 0: + destoffset = decode_rm00_address(rl); + DECODE_PRINTF(","); + srcreg = DECODE_RM_BYTE_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + store_data_byte(destoffset, *srcreg); + break; + case 1: + destoffset = decode_rm01_address(rl); + DECODE_PRINTF(","); + srcreg = DECODE_RM_BYTE_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + store_data_byte(destoffset, *srcreg); + break; + case 2: + destoffset = decode_rm10_address(rl); + DECODE_PRINTF(","); + srcreg = DECODE_RM_BYTE_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + store_data_byte(destoffset, *srcreg); + break; + case 3: /* register to register */ + destreg = DECODE_RM_BYTE_REGISTER(rl); + DECODE_PRINTF(","); + srcreg = DECODE_RM_BYTE_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = *srcreg; + break; + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x89 +****************************************************************************/ +static void x86emuOp_mov_word_RM_R(u8 X86EMU_UNUSED(op1)) +{ + int mod, rl, rh; + u32 destoffset; + + START_OF_INSTR(); + DECODE_PRINTF("MOV\t"); + FETCH_DECODE_MODRM(mod, rh, rl); + switch (mod) { + case 0: + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 *srcreg; + + destoffset = decode_rm00_address(rl); + DECODE_PRINTF(","); + srcreg = DECODE_RM_LONG_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + store_data_long(destoffset, *srcreg); + } else { + u16 *srcreg; + + destoffset = decode_rm00_address(rl); + DECODE_PRINTF(","); + srcreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + store_data_word(destoffset, *srcreg); + } + break; + case 1: + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 *srcreg; + + destoffset = decode_rm01_address(rl); + DECODE_PRINTF(","); + srcreg = DECODE_RM_LONG_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + store_data_long(destoffset, *srcreg); + } else { + u16 *srcreg; + + destoffset = decode_rm01_address(rl); + DECODE_PRINTF(","); + srcreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + store_data_word(destoffset, *srcreg); + } + break; + case 2: + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 *srcreg; + + destoffset = decode_rm10_address(rl); + DECODE_PRINTF(","); + srcreg = DECODE_RM_LONG_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + store_data_long(destoffset, *srcreg); + } else { + u16 *srcreg; + + destoffset = decode_rm10_address(rl); + DECODE_PRINTF(","); + srcreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + store_data_word(destoffset, *srcreg); + } + break; + case 3: /* register to register */ + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 *destreg,*srcreg; + + destreg = DECODE_RM_LONG_REGISTER(rl); + DECODE_PRINTF(","); + srcreg = DECODE_RM_LONG_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = *srcreg; + } else { + u16 *destreg,*srcreg; + + destreg = DECODE_RM_WORD_REGISTER(rl); + DECODE_PRINTF(","); + srcreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = *srcreg; + } + break; + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x8a +****************************************************************************/ +static void x86emuOp_mov_byte_R_RM(u8 X86EMU_UNUSED(op1)) +{ + int mod, rl, rh; + u8 *destreg, *srcreg; + uint srcoffset; + u8 srcval; + + START_OF_INSTR(); + DECODE_PRINTF("MOV\t"); + FETCH_DECODE_MODRM(mod, rh, rl); + switch (mod) { + case 0: + destreg = DECODE_RM_BYTE_REGISTER(rh); + DECODE_PRINTF(","); + srcoffset = decode_rm00_address(rl); + srcval = fetch_data_byte(srcoffset); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = srcval; + break; + case 1: + destreg = DECODE_RM_BYTE_REGISTER(rh); + DECODE_PRINTF(","); + srcoffset = decode_rm01_address(rl); + srcval = fetch_data_byte(srcoffset); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = srcval; + break; + case 2: + destreg = DECODE_RM_BYTE_REGISTER(rh); + DECODE_PRINTF(","); + srcoffset = decode_rm10_address(rl); + srcval = fetch_data_byte(srcoffset); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = srcval; + break; + case 3: /* register to register */ + destreg = DECODE_RM_BYTE_REGISTER(rh); + DECODE_PRINTF(","); + srcreg = DECODE_RM_BYTE_REGISTER(rl); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = *srcreg; + break; + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x8b +****************************************************************************/ +static void x86emuOp_mov_word_R_RM(u8 X86EMU_UNUSED(op1)) +{ + int mod, rl, rh; + uint srcoffset; + + START_OF_INSTR(); + DECODE_PRINTF("MOV\t"); + FETCH_DECODE_MODRM(mod, rh, rl); + switch (mod) { + case 0: + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 *destreg; + u32 srcval; + + destreg = DECODE_RM_LONG_REGISTER(rh); + DECODE_PRINTF(","); + srcoffset = decode_rm00_address(rl); + srcval = fetch_data_long(srcoffset); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = srcval; + } else { + u16 *destreg; + u16 srcval; + + destreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF(","); + srcoffset = decode_rm00_address(rl); + srcval = fetch_data_word(srcoffset); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = srcval; + } + break; + case 1: + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 *destreg; + u32 srcval; + + destreg = DECODE_RM_LONG_REGISTER(rh); + DECODE_PRINTF(","); + srcoffset = decode_rm01_address(rl); + srcval = fetch_data_long(srcoffset); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = srcval; + } else { + u16 *destreg; + u16 srcval; + + destreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF(","); + srcoffset = decode_rm01_address(rl); + srcval = fetch_data_word(srcoffset); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = srcval; + } + break; + case 2: + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 *destreg; + u32 srcval; + + destreg = DECODE_RM_LONG_REGISTER(rh); + DECODE_PRINTF(","); + srcoffset = decode_rm10_address(rl); + srcval = fetch_data_long(srcoffset); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = srcval; + } else { + u16 *destreg; + u16 srcval; + + destreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF(","); + srcoffset = decode_rm10_address(rl); + srcval = fetch_data_word(srcoffset); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = srcval; + } + break; + case 3: /* register to register */ + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 *destreg, *srcreg; + + destreg = DECODE_RM_LONG_REGISTER(rh); + DECODE_PRINTF(","); + srcreg = DECODE_RM_LONG_REGISTER(rl); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = *srcreg; + } else { + u16 *destreg, *srcreg; + + destreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF(","); + srcreg = DECODE_RM_WORD_REGISTER(rl); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = *srcreg; + } + break; + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x8c +****************************************************************************/ +static void x86emuOp_mov_word_RM_SR(u8 X86EMU_UNUSED(op1)) +{ + int mod, rl, rh; + u16 *destreg, *srcreg; + uint destoffset; + u16 destval; + + START_OF_INSTR(); + DECODE_PRINTF("MOV\t"); + FETCH_DECODE_MODRM(mod, rh, rl); + switch (mod) { + case 0: + destoffset = decode_rm00_address(rl); + DECODE_PRINTF(","); + srcreg = decode_rm_seg_register(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + destval = *srcreg; + store_data_word(destoffset, destval); + break; + case 1: + destoffset = decode_rm01_address(rl); + DECODE_PRINTF(","); + srcreg = decode_rm_seg_register(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + destval = *srcreg; + store_data_word(destoffset, destval); + break; + case 2: + destoffset = decode_rm10_address(rl); + DECODE_PRINTF(","); + srcreg = decode_rm_seg_register(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + destval = *srcreg; + store_data_word(destoffset, destval); + break; + case 3: /* register to register */ + destreg = DECODE_RM_WORD_REGISTER(rl); + DECODE_PRINTF(","); + srcreg = decode_rm_seg_register(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = *srcreg; + break; + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x8d +****************************************************************************/ +static void x86emuOp_lea_word_R_M(u8 X86EMU_UNUSED(op1)) +{ + int mod, rl, rh; + uint destoffset; + + START_OF_INSTR(); + DECODE_PRINTF("LEA\t"); + FETCH_DECODE_MODRM(mod, rh, rl); + switch (mod) { + case 0: + if (M.x86.mode & SYSMODE_PREFIX_ADDR) { + u32 *srcreg = DECODE_RM_LONG_REGISTER(rh); + DECODE_PRINTF(","); + destoffset = decode_rm00_address(rl); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *srcreg = (u32)destoffset; + } else { + u16 *srcreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF(","); + destoffset = decode_rm00_address(rl); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *srcreg = (u16)destoffset; + } + break; + case 1: + if (M.x86.mode & SYSMODE_PREFIX_ADDR) { + u32 *srcreg = DECODE_RM_LONG_REGISTER(rh); + DECODE_PRINTF(","); + destoffset = decode_rm01_address(rl); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *srcreg = (u32)destoffset; + } else { + u16 *srcreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF(","); + destoffset = decode_rm01_address(rl); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *srcreg = (u16)destoffset; + } + break; + case 2: + if (M.x86.mode & SYSMODE_PREFIX_ADDR) { + u32 *srcreg = DECODE_RM_LONG_REGISTER(rh); + DECODE_PRINTF(","); + destoffset = decode_rm10_address(rl); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *srcreg = (u32)destoffset; + } else { + u16 *srcreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF(","); + destoffset = decode_rm10_address(rl); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *srcreg = (u16)destoffset; + } + break; + case 3: /* register to register */ + /* undefined. Do nothing. */ + break; + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x8e +****************************************************************************/ +static void x86emuOp_mov_word_SR_RM(u8 X86EMU_UNUSED(op1)) +{ + int mod, rl, rh; + u16 *destreg, *srcreg; + uint srcoffset; + u16 srcval; + + START_OF_INSTR(); + DECODE_PRINTF("MOV\t"); + FETCH_DECODE_MODRM(mod, rh, rl); + switch (mod) { + case 0: + destreg = decode_rm_seg_register(rh); + DECODE_PRINTF(","); + srcoffset = decode_rm00_address(rl); + srcval = fetch_data_word(srcoffset); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = srcval; + break; + case 1: + destreg = decode_rm_seg_register(rh); + DECODE_PRINTF(","); + srcoffset = decode_rm01_address(rl); + srcval = fetch_data_word(srcoffset); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = srcval; + break; + case 2: + destreg = decode_rm_seg_register(rh); + DECODE_PRINTF(","); + srcoffset = decode_rm10_address(rl); + srcval = fetch_data_word(srcoffset); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = srcval; + break; + case 3: /* register to register */ + destreg = decode_rm_seg_register(rh); + DECODE_PRINTF(","); + srcreg = DECODE_RM_WORD_REGISTER(rl); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = *srcreg; + break; + } + /* + * Clean up, and reset all the R_xSP pointers to the correct + * locations. This is about 3x too much overhead (doing all the + * segreg ptrs when only one is needed, but this instruction + * *cannot* be that common, and this isn't too much work anyway. + */ + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x8f +****************************************************************************/ +static void x86emuOp_pop_RM(u8 X86EMU_UNUSED(op1)) +{ + int mod, rl, rh; + uint destoffset; + + START_OF_INSTR(); + DECODE_PRINTF("POP\t"); + FETCH_DECODE_MODRM(mod, rh, rl); + if (rh != 0) { + DECODE_PRINTF("ILLEGAL DECODE OF OPCODE 8F\n"); + HALT_SYS(); + } + switch (mod) { + case 0: + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 destval; + + destoffset = decode_rm00_address(rl); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + destval = pop_long(); + store_data_long(destoffset, destval); + } else { + u16 destval; + + destoffset = decode_rm00_address(rl); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + destval = pop_word(); + store_data_word(destoffset, destval); + } + break; + case 1: + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 destval; + + destoffset = decode_rm01_address(rl); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + destval = pop_long(); + store_data_long(destoffset, destval); + } else { + u16 destval; + + destoffset = decode_rm01_address(rl); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + destval = pop_word(); + store_data_word(destoffset, destval); + } + break; + case 2: + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 destval; + + destoffset = decode_rm10_address(rl); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + destval = pop_long(); + store_data_long(destoffset, destval); + } else { + u16 destval; + + destoffset = decode_rm10_address(rl); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + destval = pop_word(); + store_data_word(destoffset, destval); + } + break; + case 3: /* register to register */ + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 *destreg; + + destreg = DECODE_RM_LONG_REGISTER(rl); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = pop_long(); + } else { + u16 *destreg; + + destreg = DECODE_RM_WORD_REGISTER(rl); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = pop_word(); + } + break; + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x90 +****************************************************************************/ +static void x86emuOp_nop(u8 X86EMU_UNUSED(op1)) +{ + START_OF_INSTR(); + DECODE_PRINTF("NOP\n"); + TRACE_AND_STEP(); + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x91 +****************************************************************************/ +static void x86emuOp_xchg_word_AX_CX(u8 X86EMU_UNUSED(op1)) +{ + u32 tmp; + + START_OF_INSTR(); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + DECODE_PRINTF("XCHG\tEAX,ECX\n"); + } else { + DECODE_PRINTF("XCHG\tAX,CX\n"); + } + TRACE_AND_STEP(); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + tmp = M.x86.R_EAX; + M.x86.R_EAX = M.x86.R_ECX; + M.x86.R_ECX = tmp; + } else { + tmp = M.x86.R_AX; + M.x86.R_AX = M.x86.R_CX; + M.x86.R_CX = (u16)tmp; + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x92 +****************************************************************************/ +static void x86emuOp_xchg_word_AX_DX(u8 X86EMU_UNUSED(op1)) +{ + u32 tmp; + + START_OF_INSTR(); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + DECODE_PRINTF("XCHG\tEAX,EDX\n"); + } else { + DECODE_PRINTF("XCHG\tAX,DX\n"); + } + TRACE_AND_STEP(); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + tmp = M.x86.R_EAX; + M.x86.R_EAX = M.x86.R_EDX; + M.x86.R_EDX = tmp; + } else { + tmp = M.x86.R_AX; + M.x86.R_AX = M.x86.R_DX; + M.x86.R_DX = (u16)tmp; + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x93 +****************************************************************************/ +static void x86emuOp_xchg_word_AX_BX(u8 X86EMU_UNUSED(op1)) +{ + u32 tmp; + + START_OF_INSTR(); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + DECODE_PRINTF("XCHG\tEAX,EBX\n"); + } else { + DECODE_PRINTF("XCHG\tAX,BX\n"); + } + TRACE_AND_STEP(); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + tmp = M.x86.R_EAX; + M.x86.R_EAX = M.x86.R_EBX; + M.x86.R_EBX = tmp; + } else { + tmp = M.x86.R_AX; + M.x86.R_AX = M.x86.R_BX; + M.x86.R_BX = (u16)tmp; + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x94 +****************************************************************************/ +static void x86emuOp_xchg_word_AX_SP(u8 X86EMU_UNUSED(op1)) +{ + u32 tmp; + + START_OF_INSTR(); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + DECODE_PRINTF("XCHG\tEAX,ESP\n"); + } else { + DECODE_PRINTF("XCHG\tAX,SP\n"); + } + TRACE_AND_STEP(); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + tmp = M.x86.R_EAX; + M.x86.R_EAX = M.x86.R_ESP; + M.x86.R_ESP = tmp; + } else { + tmp = M.x86.R_AX; + M.x86.R_AX = M.x86.R_SP; + M.x86.R_SP = (u16)tmp; + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x95 +****************************************************************************/ +static void x86emuOp_xchg_word_AX_BP(u8 X86EMU_UNUSED(op1)) +{ + u32 tmp; + + START_OF_INSTR(); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + DECODE_PRINTF("XCHG\tEAX,EBP\n"); + } else { + DECODE_PRINTF("XCHG\tAX,BP\n"); + } + TRACE_AND_STEP(); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + tmp = M.x86.R_EAX; + M.x86.R_EAX = M.x86.R_EBP; + M.x86.R_EBP = tmp; + } else { + tmp = M.x86.R_AX; + M.x86.R_AX = M.x86.R_BP; + M.x86.R_BP = (u16)tmp; + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x96 +****************************************************************************/ +static void x86emuOp_xchg_word_AX_SI(u8 X86EMU_UNUSED(op1)) +{ + u32 tmp; + + START_OF_INSTR(); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + DECODE_PRINTF("XCHG\tEAX,ESI\n"); + } else { + DECODE_PRINTF("XCHG\tAX,SI\n"); + } + TRACE_AND_STEP(); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + tmp = M.x86.R_EAX; + M.x86.R_EAX = M.x86.R_ESI; + M.x86.R_ESI = tmp; + } else { + tmp = M.x86.R_AX; + M.x86.R_AX = M.x86.R_SI; + M.x86.R_SI = (u16)tmp; + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x97 +****************************************************************************/ +static void x86emuOp_xchg_word_AX_DI(u8 X86EMU_UNUSED(op1)) +{ + u32 tmp; + + START_OF_INSTR(); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + DECODE_PRINTF("XCHG\tEAX,EDI\n"); + } else { + DECODE_PRINTF("XCHG\tAX,DI\n"); + } + TRACE_AND_STEP(); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + tmp = M.x86.R_EAX; + M.x86.R_EAX = M.x86.R_EDI; + M.x86.R_EDI = tmp; + } else { + tmp = M.x86.R_AX; + M.x86.R_AX = M.x86.R_DI; + M.x86.R_DI = (u16)tmp; + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x98 +****************************************************************************/ +static void x86emuOp_cbw(u8 X86EMU_UNUSED(op1)) +{ + START_OF_INSTR(); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + DECODE_PRINTF("CWDE\n"); + } else { + DECODE_PRINTF("CBW\n"); + } + TRACE_AND_STEP(); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + if (M.x86.R_AX & 0x8000) { + M.x86.R_EAX |= 0xffff0000; + } else { + M.x86.R_EAX &= 0x0000ffff; + } + } else { + if (M.x86.R_AL & 0x80) { + M.x86.R_AH = 0xff; + } else { + M.x86.R_AH = 0x0; + } + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x99 +****************************************************************************/ +static void x86emuOp_cwd(u8 X86EMU_UNUSED(op1)) +{ + START_OF_INSTR(); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + DECODE_PRINTF("CDQ\n"); + } else { + DECODE_PRINTF("CWD\n"); + } + DECODE_PRINTF("CWD\n"); + TRACE_AND_STEP(); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + if (M.x86.R_EAX & 0x80000000) { + M.x86.R_EDX = 0xffffffff; + } else { + M.x86.R_EDX = 0x0; + } + } else { + if (M.x86.R_AX & 0x8000) { + M.x86.R_DX = 0xffff; + } else { + M.x86.R_DX = 0x0; + } + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x9a +****************************************************************************/ +static void x86emuOp_call_far_IMM(u8 X86EMU_UNUSED(op1)) +{ + u32 farseg, faroff; + + START_OF_INSTR(); + DECODE_PRINTF("CALL\t"); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + faroff = fetch_long_imm(); + farseg = fetch_word_imm(); + } else { + faroff = fetch_word_imm(); + farseg = fetch_word_imm(); + } + DECODE_PRINTF2("%04x:", farseg); + DECODE_PRINTF2("%04x\n", faroff); + CALL_TRACE(M.x86.saved_cs, M.x86.saved_ip, farseg, faroff, "FAR "); + + /* XXX + * + * Hooked interrupt vectors calling into our "BIOS" will cause + * problems unless all intersegment stuff is checked for BIOS + * access. Check needed here. For moment, let it alone. + */ + TRACE_AND_STEP(); + push_word(M.x86.R_CS); + M.x86.R_CS = farseg; + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + push_long(M.x86.R_EIP); + } else { + push_word(M.x86.R_IP); + } + M.x86.R_EIP = faroff & 0xffff; + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x9b +****************************************************************************/ +static void x86emuOp_wait(u8 X86EMU_UNUSED(op1)) +{ + START_OF_INSTR(); + DECODE_PRINTF("WAIT"); + TRACE_AND_STEP(); + /* NADA. */ + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x9c +****************************************************************************/ +static void x86emuOp_pushf_word(u8 X86EMU_UNUSED(op1)) +{ + u32 flags; + + START_OF_INSTR(); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + DECODE_PRINTF("PUSHFD\n"); + } else { + DECODE_PRINTF("PUSHF\n"); + } + TRACE_AND_STEP(); + + /* clear out *all* bits not representing flags, and turn on real bits */ + flags = (M.x86.R_EFLG & F_MSK) | F_ALWAYS_ON; + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + push_long(flags); + } else { + push_word((u16)flags); + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x9d +****************************************************************************/ +static void x86emuOp_popf_word(u8 X86EMU_UNUSED(op1)) +{ + START_OF_INSTR(); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + DECODE_PRINTF("POPFD\n"); + } else { + DECODE_PRINTF("POPF\n"); + } + TRACE_AND_STEP(); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + M.x86.R_EFLG = pop_long(); + } else { + M.x86.R_FLG = pop_word(); + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x9e +****************************************************************************/ +static void x86emuOp_sahf(u8 X86EMU_UNUSED(op1)) +{ + START_OF_INSTR(); + DECODE_PRINTF("SAHF\n"); + TRACE_AND_STEP(); + /* clear the lower bits of the flag register */ + M.x86.R_FLG &= 0xffffff00; + /* or in the AH register into the flags register */ + M.x86.R_FLG |= M.x86.R_AH; + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x9f +****************************************************************************/ +static void x86emuOp_lahf(u8 X86EMU_UNUSED(op1)) +{ + START_OF_INSTR(); + DECODE_PRINTF("LAHF\n"); + TRACE_AND_STEP(); + M.x86.R_AH = (u8)(M.x86.R_FLG & 0xff); + /*undocumented TC++ behavior??? Nope. It's documented, but + you have too look real hard to notice it. */ + M.x86.R_AH |= 0x2; + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0xa0 +****************************************************************************/ +static void x86emuOp_mov_AL_M_IMM(u8 X86EMU_UNUSED(op1)) +{ + u16 offset; + + START_OF_INSTR(); + DECODE_PRINTF("MOV\tAL,"); + offset = fetch_word_imm(); + DECODE_PRINTF2("[%04x]\n", offset); + TRACE_AND_STEP(); + M.x86.R_AL = fetch_data_byte(offset); + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0xa1 +****************************************************************************/ +static void x86emuOp_mov_AX_M_IMM(u8 X86EMU_UNUSED(op1)) +{ + u16 offset; + + START_OF_INSTR(); + offset = fetch_word_imm(); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + DECODE_PRINTF2("MOV\tEAX,[%04x]\n", offset); + } else { + DECODE_PRINTF2("MOV\tAX,[%04x]\n", offset); + } + TRACE_AND_STEP(); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + M.x86.R_EAX = fetch_data_long(offset); + } else { + M.x86.R_AX = fetch_data_word(offset); + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0xa2 +****************************************************************************/ +static void x86emuOp_mov_M_AL_IMM(u8 X86EMU_UNUSED(op1)) +{ + u16 offset; + + START_OF_INSTR(); + DECODE_PRINTF("MOV\t"); + offset = fetch_word_imm(); + DECODE_PRINTF2("[%04x],AL\n", offset); + TRACE_AND_STEP(); + store_data_byte(offset, M.x86.R_AL); + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0xa3 +****************************************************************************/ +static void x86emuOp_mov_M_AX_IMM(u8 X86EMU_UNUSED(op1)) +{ + u16 offset; + + START_OF_INSTR(); + offset = fetch_word_imm(); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + DECODE_PRINTF2("MOV\t[%04x],EAX\n", offset); + } else { + DECODE_PRINTF2("MOV\t[%04x],AX\n", offset); + } + TRACE_AND_STEP(); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + store_data_long(offset, M.x86.R_EAX); + } else { + store_data_word(offset, M.x86.R_AX); + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0xa4 +****************************************************************************/ +static void x86emuOp_movs_byte(u8 X86EMU_UNUSED(op1)) +{ + u8 val; + u32 count; + int inc; + + START_OF_INSTR(); + DECODE_PRINTF("MOVS\tBYTE\n"); + if (ACCESS_FLAG(F_DF)) /* down */ + inc = -1; + else + inc = 1; + TRACE_AND_STEP(); + count = 1; + if (M.x86.mode & (SYSMODE_PREFIX_REPE | SYSMODE_PREFIX_REPNE)) { + /* dont care whether REPE or REPNE */ + /* move them until CX is ZERO. */ + count = M.x86.R_CX; + M.x86.R_CX = 0; + M.x86.mode &= ~(SYSMODE_PREFIX_REPE | SYSMODE_PREFIX_REPNE); + } + while (count--) { + val = fetch_data_byte(M.x86.R_SI); + store_data_byte_abs(M.x86.R_ES, M.x86.R_DI, val); + M.x86.R_SI += inc; + M.x86.R_DI += inc; + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0xa5 +****************************************************************************/ +static void x86emuOp_movs_word(u8 X86EMU_UNUSED(op1)) +{ + u32 val; + int inc; + u32 count; + + START_OF_INSTR(); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + DECODE_PRINTF("MOVS\tDWORD\n"); + if (ACCESS_FLAG(F_DF)) /* down */ + inc = -4; + else + inc = 4; + } else { + DECODE_PRINTF("MOVS\tWORD\n"); + if (ACCESS_FLAG(F_DF)) /* down */ + inc = -2; + else + inc = 2; + } + TRACE_AND_STEP(); + count = 1; + if (M.x86.mode & (SYSMODE_PREFIX_REPE | SYSMODE_PREFIX_REPNE)) { + /* dont care whether REPE or REPNE */ + /* move them until CX is ZERO. */ + count = M.x86.R_CX; + M.x86.R_CX = 0; + M.x86.mode &= ~(SYSMODE_PREFIX_REPE | SYSMODE_PREFIX_REPNE); + } + while (count--) { + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + val = fetch_data_long(M.x86.R_SI); + store_data_long_abs(M.x86.R_ES, M.x86.R_DI, val); + } else { + val = fetch_data_word(M.x86.R_SI); + store_data_word_abs(M.x86.R_ES, M.x86.R_DI, (u16)val); + } + M.x86.R_SI += inc; + M.x86.R_DI += inc; + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0xa6 +****************************************************************************/ +static void x86emuOp_cmps_byte(u8 X86EMU_UNUSED(op1)) +{ + s8 val1, val2; + int inc; + + START_OF_INSTR(); + DECODE_PRINTF("CMPS\tBYTE\n"); + TRACE_AND_STEP(); + if (ACCESS_FLAG(F_DF)) /* down */ + inc = -1; + else + inc = 1; + + if (M.x86.mode & SYSMODE_PREFIX_REPE) { + /* REPE */ + /* move them until CX is ZERO. */ + while (M.x86.R_CX != 0) { + val1 = fetch_data_byte(M.x86.R_SI); + val2 = fetch_data_byte_abs(M.x86.R_ES, M.x86.R_DI); + cmp_byte(val1, val2); + M.x86.R_CX -= 1; + M.x86.R_SI += inc; + M.x86.R_DI += inc; + if (ACCESS_FLAG(F_ZF) == 0) + break; + } + M.x86.mode &= ~SYSMODE_PREFIX_REPE; + } else if (M.x86.mode & SYSMODE_PREFIX_REPNE) { + /* REPNE */ + /* move them until CX is ZERO. */ + while (M.x86.R_CX != 0) { + val1 = fetch_data_byte(M.x86.R_SI); + val2 = fetch_data_byte_abs(M.x86.R_ES, M.x86.R_DI); + cmp_byte(val1, val2); + M.x86.R_CX -= 1; + M.x86.R_SI += inc; + M.x86.R_DI += inc; + if (ACCESS_FLAG(F_ZF)) + break; /* zero flag set means equal */ + } + M.x86.mode &= ~SYSMODE_PREFIX_REPNE; + } else { + val1 = fetch_data_byte(M.x86.R_SI); + val2 = fetch_data_byte_abs(M.x86.R_ES, M.x86.R_DI); + cmp_byte(val1, val2); + M.x86.R_SI += inc; + M.x86.R_DI += inc; + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0xa7 +****************************************************************************/ +static void x86emuOp_cmps_word(u8 X86EMU_UNUSED(op1)) +{ + u32 val1,val2; + int inc; + + START_OF_INSTR(); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + DECODE_PRINTF("CMPS\tDWORD\n"); + if (ACCESS_FLAG(F_DF)) /* down */ + inc = -4; + else + inc = 4; + } else { + DECODE_PRINTF("CMPS\tWORD\n"); + if (ACCESS_FLAG(F_DF)) /* down */ + inc = -2; + else + inc = 2; + } + TRACE_AND_STEP(); + if (M.x86.mode & SYSMODE_PREFIX_REPE) { + /* REPE */ + /* move them until CX is ZERO. */ + while (M.x86.R_CX != 0) { + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + val1 = fetch_data_long(M.x86.R_SI); + val2 = fetch_data_long_abs(M.x86.R_ES, M.x86.R_DI); + cmp_long(val1, val2); + } else { + val1 = fetch_data_word(M.x86.R_SI); + val2 = fetch_data_word_abs(M.x86.R_ES, M.x86.R_DI); + cmp_word((u16)val1, (u16)val2); + } + M.x86.R_CX -= 1; + M.x86.R_SI += inc; + M.x86.R_DI += inc; + if (ACCESS_FLAG(F_ZF) == 0) + break; + } + M.x86.mode &= ~SYSMODE_PREFIX_REPE; + } else if (M.x86.mode & SYSMODE_PREFIX_REPNE) { + /* REPNE */ + /* move them until CX is ZERO. */ + while (M.x86.R_CX != 0) { + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + val1 = fetch_data_long(M.x86.R_SI); + val2 = fetch_data_long_abs(M.x86.R_ES, M.x86.R_DI); + cmp_long(val1, val2); + } else { + val1 = fetch_data_word(M.x86.R_SI); + val2 = fetch_data_word_abs(M.x86.R_ES, M.x86.R_DI); + cmp_word((u16)val1, (u16)val2); + } + M.x86.R_CX -= 1; + M.x86.R_SI += inc; + M.x86.R_DI += inc; + if (ACCESS_FLAG(F_ZF)) + break; /* zero flag set means equal */ + } + M.x86.mode &= ~SYSMODE_PREFIX_REPNE; + } else { + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + val1 = fetch_data_long(M.x86.R_SI); + val2 = fetch_data_long_abs(M.x86.R_ES, M.x86.R_DI); + cmp_long(val1, val2); + } else { + val1 = fetch_data_word(M.x86.R_SI); + val2 = fetch_data_word_abs(M.x86.R_ES, M.x86.R_DI); + cmp_word((u16)val1, (u16)val2); + } + M.x86.R_SI += inc; + M.x86.R_DI += inc; + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0xa8 +****************************************************************************/ +static void x86emuOp_test_AL_IMM(u8 X86EMU_UNUSED(op1)) +{ + int imm; + + START_OF_INSTR(); + DECODE_PRINTF("TEST\tAL,"); + imm = fetch_byte_imm(); + DECODE_PRINTF2("%04x\n", imm); + TRACE_AND_STEP(); + test_byte(M.x86.R_AL, (u8)imm); + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0xa9 +****************************************************************************/ +static void x86emuOp_test_AX_IMM(u8 X86EMU_UNUSED(op1)) +{ + u32 srcval; + + START_OF_INSTR(); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + DECODE_PRINTF("TEST\tEAX,"); + srcval = fetch_long_imm(); + } else { + DECODE_PRINTF("TEST\tAX,"); + srcval = fetch_word_imm(); + } + DECODE_PRINTF2("%x\n", srcval); + TRACE_AND_STEP(); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + test_long(M.x86.R_EAX, srcval); + } else { + test_word(M.x86.R_AX, (u16)srcval); + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0xaa +****************************************************************************/ +static void x86emuOp_stos_byte(u8 X86EMU_UNUSED(op1)) +{ + int inc; + + START_OF_INSTR(); + DECODE_PRINTF("STOS\tBYTE\n"); + if (ACCESS_FLAG(F_DF)) /* down */ + inc = -1; + else + inc = 1; + TRACE_AND_STEP(); + if (M.x86.mode & (SYSMODE_PREFIX_REPE | SYSMODE_PREFIX_REPNE)) { + /* dont care whether REPE or REPNE */ + /* move them until CX is ZERO. */ + while (M.x86.R_CX != 0) { + store_data_byte_abs(M.x86.R_ES, M.x86.R_DI, M.x86.R_AL); + M.x86.R_CX -= 1; + M.x86.R_DI += inc; + } + M.x86.mode &= ~(SYSMODE_PREFIX_REPE | SYSMODE_PREFIX_REPNE); + } else { + store_data_byte_abs(M.x86.R_ES, M.x86.R_DI, M.x86.R_AL); + M.x86.R_DI += inc; + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0xab +****************************************************************************/ +static void x86emuOp_stos_word(u8 X86EMU_UNUSED(op1)) +{ + int inc; + u32 count; + + START_OF_INSTR(); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + DECODE_PRINTF("STOS\tDWORD\n"); + if (ACCESS_FLAG(F_DF)) /* down */ + inc = -4; + else + inc = 4; + } else { + DECODE_PRINTF("STOS\tWORD\n"); + if (ACCESS_FLAG(F_DF)) /* down */ + inc = -2; + else + inc = 2; + } + TRACE_AND_STEP(); + count = 1; + if (M.x86.mode & (SYSMODE_PREFIX_REPE | SYSMODE_PREFIX_REPNE)) { + /* dont care whether REPE or REPNE */ + /* move them until CX is ZERO. */ + count = M.x86.R_CX; + M.x86.R_CX = 0; + M.x86.mode &= ~(SYSMODE_PREFIX_REPE | SYSMODE_PREFIX_REPNE); + } + while (count--) { + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + store_data_long_abs(M.x86.R_ES, M.x86.R_DI, M.x86.R_EAX); + } else { + store_data_word_abs(M.x86.R_ES, M.x86.R_DI, M.x86.R_AX); + } + M.x86.R_DI += inc; + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0xac +****************************************************************************/ +static void x86emuOp_lods_byte(u8 X86EMU_UNUSED(op1)) +{ + int inc; + + START_OF_INSTR(); + DECODE_PRINTF("LODS\tBYTE\n"); + TRACE_AND_STEP(); + if (ACCESS_FLAG(F_DF)) /* down */ + inc = -1; + else + inc = 1; + if (M.x86.mode & (SYSMODE_PREFIX_REPE | SYSMODE_PREFIX_REPNE)) { + /* dont care whether REPE or REPNE */ + /* move them until CX is ZERO. */ + while (M.x86.R_CX != 0) { + M.x86.R_AL = fetch_data_byte(M.x86.R_SI); + M.x86.R_CX -= 1; + M.x86.R_SI += inc; + } + M.x86.mode &= ~(SYSMODE_PREFIX_REPE | SYSMODE_PREFIX_REPNE); + } else { + M.x86.R_AL = fetch_data_byte(M.x86.R_SI); + M.x86.R_SI += inc; + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0xad +****************************************************************************/ +static void x86emuOp_lods_word(u8 X86EMU_UNUSED(op1)) +{ + int inc; + u32 count; + + START_OF_INSTR(); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + DECODE_PRINTF("LODS\tDWORD\n"); + if (ACCESS_FLAG(F_DF)) /* down */ + inc = -4; + else + inc = 4; + } else { + DECODE_PRINTF("LODS\tWORD\n"); + if (ACCESS_FLAG(F_DF)) /* down */ + inc = -2; + else + inc = 2; + } + TRACE_AND_STEP(); + count = 1; + if (M.x86.mode & (SYSMODE_PREFIX_REPE | SYSMODE_PREFIX_REPNE)) { + /* dont care whether REPE or REPNE */ + /* move them until CX is ZERO. */ + count = M.x86.R_CX; + M.x86.R_CX = 0; + M.x86.mode &= ~(SYSMODE_PREFIX_REPE | SYSMODE_PREFIX_REPNE); + } + while (count--) { + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + M.x86.R_EAX = fetch_data_long(M.x86.R_SI); + } else { + M.x86.R_AX = fetch_data_word(M.x86.R_SI); + } + M.x86.R_SI += inc; + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0xae +****************************************************************************/ +static void x86emuOp_scas_byte(u8 X86EMU_UNUSED(op1)) +{ + s8 val2; + int inc; + + START_OF_INSTR(); + DECODE_PRINTF("SCAS\tBYTE\n"); + TRACE_AND_STEP(); + if (ACCESS_FLAG(F_DF)) /* down */ + inc = -1; + else + inc = 1; + if (M.x86.mode & SYSMODE_PREFIX_REPE) { + /* REPE */ + /* move them until CX is ZERO. */ + while (M.x86.R_CX != 0) { + val2 = fetch_data_byte_abs(M.x86.R_ES, M.x86.R_DI); + cmp_byte(M.x86.R_AL, val2); + M.x86.R_CX -= 1; + M.x86.R_DI += inc; + if (ACCESS_FLAG(F_ZF) == 0) + break; + } + M.x86.mode &= ~SYSMODE_PREFIX_REPE; + } else if (M.x86.mode & SYSMODE_PREFIX_REPNE) { + /* REPNE */ + /* move them until CX is ZERO. */ + while (M.x86.R_CX != 0) { + val2 = fetch_data_byte_abs(M.x86.R_ES, M.x86.R_DI); + cmp_byte(M.x86.R_AL, val2); + M.x86.R_CX -= 1; + M.x86.R_DI += inc; + if (ACCESS_FLAG(F_ZF)) + break; /* zero flag set means equal */ + } + M.x86.mode &= ~SYSMODE_PREFIX_REPNE; + } else { + val2 = fetch_data_byte_abs(M.x86.R_ES, M.x86.R_DI); + cmp_byte(M.x86.R_AL, val2); + M.x86.R_DI += inc; + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0xaf +****************************************************************************/ +static void x86emuOp_scas_word(u8 X86EMU_UNUSED(op1)) +{ + int inc; + u32 val; + + START_OF_INSTR(); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + DECODE_PRINTF("SCAS\tDWORD\n"); + if (ACCESS_FLAG(F_DF)) /* down */ + inc = -4; + else + inc = 4; + } else { + DECODE_PRINTF("SCAS\tWORD\n"); + if (ACCESS_FLAG(F_DF)) /* down */ + inc = -2; + else + inc = 2; + } + TRACE_AND_STEP(); + if (M.x86.mode & SYSMODE_PREFIX_REPE) { + /* REPE */ + /* move them until CX is ZERO. */ + while (M.x86.R_CX != 0) { + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + val = fetch_data_long_abs(M.x86.R_ES, M.x86.R_DI); + cmp_long(M.x86.R_EAX, val); + } else { + val = fetch_data_word_abs(M.x86.R_ES, M.x86.R_DI); + cmp_word(M.x86.R_AX, (u16)val); + } + M.x86.R_CX -= 1; + M.x86.R_DI += inc; + if (ACCESS_FLAG(F_ZF) == 0) + break; + } + M.x86.mode &= ~SYSMODE_PREFIX_REPE; + } else if (M.x86.mode & SYSMODE_PREFIX_REPNE) { + /* REPNE */ + /* move them until CX is ZERO. */ + while (M.x86.R_CX != 0) { + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + val = fetch_data_long_abs(M.x86.R_ES, M.x86.R_DI); + cmp_long(M.x86.R_EAX, val); + } else { + val = fetch_data_word_abs(M.x86.R_ES, M.x86.R_DI); + cmp_word(M.x86.R_AX, (u16)val); + } + M.x86.R_CX -= 1; + M.x86.R_DI += inc; + if (ACCESS_FLAG(F_ZF)) + break; /* zero flag set means equal */ + } + M.x86.mode &= ~SYSMODE_PREFIX_REPNE; + } else { + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + val = fetch_data_long_abs(M.x86.R_ES, M.x86.R_DI); + cmp_long(M.x86.R_EAX, val); + } else { + val = fetch_data_word_abs(M.x86.R_ES, M.x86.R_DI); + cmp_word(M.x86.R_AX, (u16)val); + } + M.x86.R_DI += inc; + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0xb0 +****************************************************************************/ +static void x86emuOp_mov_byte_AL_IMM(u8 X86EMU_UNUSED(op1)) +{ + u8 imm; + + START_OF_INSTR(); + DECODE_PRINTF("MOV\tAL,"); + imm = fetch_byte_imm(); + DECODE_PRINTF2("%x\n", imm); + TRACE_AND_STEP(); + M.x86.R_AL = imm; + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0xb1 +****************************************************************************/ +static void x86emuOp_mov_byte_CL_IMM(u8 X86EMU_UNUSED(op1)) +{ + u8 imm; + + START_OF_INSTR(); + DECODE_PRINTF("MOV\tCL,"); + imm = fetch_byte_imm(); + DECODE_PRINTF2("%x\n", imm); + TRACE_AND_STEP(); + M.x86.R_CL = imm; + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0xb2 +****************************************************************************/ +static void x86emuOp_mov_byte_DL_IMM(u8 X86EMU_UNUSED(op1)) +{ + u8 imm; + + START_OF_INSTR(); + DECODE_PRINTF("MOV\tDL,"); + imm = fetch_byte_imm(); + DECODE_PRINTF2("%x\n", imm); + TRACE_AND_STEP(); + M.x86.R_DL = imm; + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0xb3 +****************************************************************************/ +static void x86emuOp_mov_byte_BL_IMM(u8 X86EMU_UNUSED(op1)) +{ + u8 imm; + + START_OF_INSTR(); + DECODE_PRINTF("MOV\tBL,"); + imm = fetch_byte_imm(); + DECODE_PRINTF2("%x\n", imm); + TRACE_AND_STEP(); + M.x86.R_BL = imm; + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0xb4 +****************************************************************************/ +static void x86emuOp_mov_byte_AH_IMM(u8 X86EMU_UNUSED(op1)) +{ + u8 imm; + + START_OF_INSTR(); + DECODE_PRINTF("MOV\tAH,"); + imm = fetch_byte_imm(); + DECODE_PRINTF2("%x\n", imm); + TRACE_AND_STEP(); + M.x86.R_AH = imm; + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0xb5 +****************************************************************************/ +static void x86emuOp_mov_byte_CH_IMM(u8 X86EMU_UNUSED(op1)) +{ + u8 imm; + + START_OF_INSTR(); + DECODE_PRINTF("MOV\tCH,"); + imm = fetch_byte_imm(); + DECODE_PRINTF2("%x\n", imm); + TRACE_AND_STEP(); + M.x86.R_CH = imm; + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0xb6 +****************************************************************************/ +static void x86emuOp_mov_byte_DH_IMM(u8 X86EMU_UNUSED(op1)) +{ + u8 imm; + + START_OF_INSTR(); + DECODE_PRINTF("MOV\tDH,"); + imm = fetch_byte_imm(); + DECODE_PRINTF2("%x\n", imm); + TRACE_AND_STEP(); + M.x86.R_DH = imm; + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0xb7 +****************************************************************************/ +static void x86emuOp_mov_byte_BH_IMM(u8 X86EMU_UNUSED(op1)) +{ + u8 imm; + + START_OF_INSTR(); + DECODE_PRINTF("MOV\tBH,"); + imm = fetch_byte_imm(); + DECODE_PRINTF2("%x\n", imm); + TRACE_AND_STEP(); + M.x86.R_BH = imm; + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0xb8 +****************************************************************************/ +static void x86emuOp_mov_word_AX_IMM(u8 X86EMU_UNUSED(op1)) +{ + u32 srcval; + + START_OF_INSTR(); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + DECODE_PRINTF("MOV\tEAX,"); + srcval = fetch_long_imm(); + } else { + DECODE_PRINTF("MOV\tAX,"); + srcval = fetch_word_imm(); + } + DECODE_PRINTF2("%x\n", srcval); + TRACE_AND_STEP(); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + M.x86.R_EAX = srcval; + } else { + M.x86.R_AX = (u16)srcval; + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0xb9 +****************************************************************************/ +static void x86emuOp_mov_word_CX_IMM(u8 X86EMU_UNUSED(op1)) +{ + u32 srcval; + + START_OF_INSTR(); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + DECODE_PRINTF("MOV\tECX,"); + srcval = fetch_long_imm(); + } else { + DECODE_PRINTF("MOV\tCX,"); + srcval = fetch_word_imm(); + } + DECODE_PRINTF2("%x\n", srcval); + TRACE_AND_STEP(); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + M.x86.R_ECX = srcval; + } else { + M.x86.R_CX = (u16)srcval; + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0xba +****************************************************************************/ +static void x86emuOp_mov_word_DX_IMM(u8 X86EMU_UNUSED(op1)) +{ + u32 srcval; + + START_OF_INSTR(); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + DECODE_PRINTF("MOV\tEDX,"); + srcval = fetch_long_imm(); + } else { + DECODE_PRINTF("MOV\tDX,"); + srcval = fetch_word_imm(); + } + DECODE_PRINTF2("%x\n", srcval); + TRACE_AND_STEP(); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + M.x86.R_EDX = srcval; + } else { + M.x86.R_DX = (u16)srcval; + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0xbb +****************************************************************************/ +static void x86emuOp_mov_word_BX_IMM(u8 X86EMU_UNUSED(op1)) +{ + u32 srcval; + + START_OF_INSTR(); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + DECODE_PRINTF("MOV\tEBX,"); + srcval = fetch_long_imm(); + } else { + DECODE_PRINTF("MOV\tBX,"); + srcval = fetch_word_imm(); + } + DECODE_PRINTF2("%x\n", srcval); + TRACE_AND_STEP(); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + M.x86.R_EBX = srcval; + } else { + M.x86.R_BX = (u16)srcval; + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0xbc +****************************************************************************/ +static void x86emuOp_mov_word_SP_IMM(u8 X86EMU_UNUSED(op1)) +{ + u32 srcval; + + START_OF_INSTR(); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + DECODE_PRINTF("MOV\tESP,"); + srcval = fetch_long_imm(); + } else { + DECODE_PRINTF("MOV\tSP,"); + srcval = fetch_word_imm(); + } + DECODE_PRINTF2("%x\n", srcval); + TRACE_AND_STEP(); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + M.x86.R_ESP = srcval; + } else { + M.x86.R_SP = (u16)srcval; + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0xbd +****************************************************************************/ +static void x86emuOp_mov_word_BP_IMM(u8 X86EMU_UNUSED(op1)) +{ + u32 srcval; + + START_OF_INSTR(); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + DECODE_PRINTF("MOV\tEBP,"); + srcval = fetch_long_imm(); + } else { + DECODE_PRINTF("MOV\tBP,"); + srcval = fetch_word_imm(); + } + DECODE_PRINTF2("%x\n", srcval); + TRACE_AND_STEP(); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + M.x86.R_EBP = srcval; + } else { + M.x86.R_BP = (u16)srcval; + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0xbe +****************************************************************************/ +static void x86emuOp_mov_word_SI_IMM(u8 X86EMU_UNUSED(op1)) +{ + u32 srcval; + + START_OF_INSTR(); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + DECODE_PRINTF("MOV\tESI,"); + srcval = fetch_long_imm(); + } else { + DECODE_PRINTF("MOV\tSI,"); + srcval = fetch_word_imm(); + } + DECODE_PRINTF2("%x\n", srcval); + TRACE_AND_STEP(); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + M.x86.R_ESI = srcval; + } else { + M.x86.R_SI = (u16)srcval; + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0xbf +****************************************************************************/ +static void x86emuOp_mov_word_DI_IMM(u8 X86EMU_UNUSED(op1)) +{ + u32 srcval; + + START_OF_INSTR(); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + DECODE_PRINTF("MOV\tEDI,"); + srcval = fetch_long_imm(); + } else { + DECODE_PRINTF("MOV\tDI,"); + srcval = fetch_word_imm(); + } + DECODE_PRINTF2("%x\n", srcval); + TRACE_AND_STEP(); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + M.x86.R_EDI = srcval; + } else { + M.x86.R_DI = (u16)srcval; + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/* used by opcodes c0, d0, and d2. */ +static u8(*opcD0_byte_operation[])(u8 d, u8 s) = +{ + rol_byte, + ror_byte, + rcl_byte, + rcr_byte, + shl_byte, + shr_byte, + shl_byte, /* sal_byte === shl_byte by definition */ + sar_byte, +}; + +/**************************************************************************** +REMARKS: +Handles opcode 0xc0 +****************************************************************************/ +static void x86emuOp_opcC0_byte_RM_MEM(u8 X86EMU_UNUSED(op1)) +{ + int mod, rl, rh; + u8 *destreg; + uint destoffset; + u8 destval; + u8 amt; + + /* + * Yet another weirdo special case instruction format. Part of + * the opcode held below in "RH". Doubly nested case would + * result, except that the decoded instruction + */ + START_OF_INSTR(); + FETCH_DECODE_MODRM(mod, rh, rl); +#ifdef X86EMU_DEBUG + if (DEBUG_DECODE()) { + /* XXX DECODE_PRINTF may be changed to something more + general, so that it is important to leave the strings + in the same format, even though the result is that the + above test is done twice. */ + + switch (rh) { + case 0: + DECODE_PRINTF("ROL\t"); + break; + case 1: + DECODE_PRINTF("ROR\t"); + break; + case 2: + DECODE_PRINTF("RCL\t"); + break; + case 3: + DECODE_PRINTF("RCR\t"); + break; + case 4: + DECODE_PRINTF("SHL\t"); + break; + case 5: + DECODE_PRINTF("SHR\t"); + break; + case 6: + DECODE_PRINTF("SAL\t"); + break; + case 7: + DECODE_PRINTF("SAR\t"); + break; + } + } +#endif + /* know operation, decode the mod byte to find the addressing + mode. */ + switch (mod) { + case 0: + DECODE_PRINTF("BYTE PTR "); + destoffset = decode_rm00_address(rl); + amt = fetch_byte_imm(); + DECODE_PRINTF2(",%x\n", amt); + destval = fetch_data_byte(destoffset); + TRACE_AND_STEP(); + destval = (*opcD0_byte_operation[rh]) (destval, amt); + store_data_byte(destoffset, destval); + break; + case 1: + DECODE_PRINTF("BYTE PTR "); + destoffset = decode_rm01_address(rl); + amt = fetch_byte_imm(); + DECODE_PRINTF2(",%x\n", amt); + destval = fetch_data_byte(destoffset); + TRACE_AND_STEP(); + destval = (*opcD0_byte_operation[rh]) (destval, amt); + store_data_byte(destoffset, destval); + break; + case 2: + DECODE_PRINTF("BYTE PTR "); + destoffset = decode_rm10_address(rl); + amt = fetch_byte_imm(); + DECODE_PRINTF2(",%x\n", amt); + destval = fetch_data_byte(destoffset); + TRACE_AND_STEP(); + destval = (*opcD0_byte_operation[rh]) (destval, amt); + store_data_byte(destoffset, destval); + break; + case 3: /* register to register */ + destreg = DECODE_RM_BYTE_REGISTER(rl); + amt = fetch_byte_imm(); + DECODE_PRINTF2(",%x\n", amt); + TRACE_AND_STEP(); + destval = (*opcD0_byte_operation[rh]) (*destreg, amt); + *destreg = destval; + break; + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/* used by opcodes c1, d1, and d3. */ +static u16(*opcD1_word_operation[])(u16 s, u8 d) = +{ + rol_word, + ror_word, + rcl_word, + rcr_word, + shl_word, + shr_word, + shl_word, /* sal_byte === shl_byte by definition */ + sar_word, +}; + +/* used by opcodes c1, d1, and d3. */ +static u32 (*opcD1_long_operation[])(u32 s, u8 d) = +{ + rol_long, + ror_long, + rcl_long, + rcr_long, + shl_long, + shr_long, + shl_long, /* sal_byte === shl_byte by definition */ + sar_long, +}; + +/**************************************************************************** +REMARKS: +Handles opcode 0xc1 +****************************************************************************/ +static void x86emuOp_opcC1_word_RM_MEM(u8 X86EMU_UNUSED(op1)) +{ + int mod, rl, rh; + uint destoffset; + u8 amt; + + /* + * Yet another weirdo special case instruction format. Part of + * the opcode held below in "RH". Doubly nested case would + * result, except that the decoded instruction + */ + START_OF_INSTR(); + FETCH_DECODE_MODRM(mod, rh, rl); +#ifdef X86EMU_DEBUG + if (DEBUG_DECODE()) { + /* XXX DECODE_PRINTF may be changed to something more + general, so that it is important to leave the strings + in the same format, even though the result is that the + above test is done twice. */ + + switch (rh) { + case 0: + DECODE_PRINTF("ROL\t"); + break; + case 1: + DECODE_PRINTF("ROR\t"); + break; + case 2: + DECODE_PRINTF("RCL\t"); + break; + case 3: + DECODE_PRINTF("RCR\t"); + break; + case 4: + DECODE_PRINTF("SHL\t"); + break; + case 5: + DECODE_PRINTF("SHR\t"); + break; + case 6: + DECODE_PRINTF("SAL\t"); + break; + case 7: + DECODE_PRINTF("SAR\t"); + break; + } + } +#endif + /* know operation, decode the mod byte to find the addressing + mode. */ + switch (mod) { + case 0: + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 destval; + + DECODE_PRINTF("DWORD PTR "); + destoffset = decode_rm00_address(rl); + amt = fetch_byte_imm(); + DECODE_PRINTF2(",%x\n", amt); + destval = fetch_data_long(destoffset); + TRACE_AND_STEP(); + destval = (*opcD1_long_operation[rh]) (destval, amt); + store_data_long(destoffset, destval); + } else { + u16 destval; + + DECODE_PRINTF("WORD PTR "); + destoffset = decode_rm00_address(rl); + amt = fetch_byte_imm(); + DECODE_PRINTF2(",%x\n", amt); + destval = fetch_data_word(destoffset); + TRACE_AND_STEP(); + destval = (*opcD1_word_operation[rh]) (destval, amt); + store_data_word(destoffset, destval); + } + break; + case 1: + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 destval; + + DECODE_PRINTF("DWORD PTR "); + destoffset = decode_rm01_address(rl); + amt = fetch_byte_imm(); + DECODE_PRINTF2(",%x\n", amt); + destval = fetch_data_long(destoffset); + TRACE_AND_STEP(); + destval = (*opcD1_long_operation[rh]) (destval, amt); + store_data_long(destoffset, destval); + } else { + u16 destval; + + DECODE_PRINTF("WORD PTR "); + destoffset = decode_rm01_address(rl); + amt = fetch_byte_imm(); + DECODE_PRINTF2(",%x\n", amt); + destval = fetch_data_word(destoffset); + TRACE_AND_STEP(); + destval = (*opcD1_word_operation[rh]) (destval, amt); + store_data_word(destoffset, destval); + } + break; + case 2: + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 destval; + + DECODE_PRINTF("DWORD PTR "); + destoffset = decode_rm10_address(rl); + amt = fetch_byte_imm(); + DECODE_PRINTF2(",%x\n", amt); + destval = fetch_data_long(destoffset); + TRACE_AND_STEP(); + destval = (*opcD1_long_operation[rh]) (destval, amt); + store_data_long(destoffset, destval); + } else { + u16 destval; + + DECODE_PRINTF("WORD PTR "); + destoffset = decode_rm10_address(rl); + amt = fetch_byte_imm(); + DECODE_PRINTF2(",%x\n", amt); + destval = fetch_data_word(destoffset); + TRACE_AND_STEP(); + destval = (*opcD1_word_operation[rh]) (destval, amt); + store_data_word(destoffset, destval); + } + break; + case 3: /* register to register */ + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 *destreg; + + destreg = DECODE_RM_LONG_REGISTER(rl); + amt = fetch_byte_imm(); + DECODE_PRINTF2(",%x\n", amt); + TRACE_AND_STEP(); + *destreg = (*opcD1_long_operation[rh]) (*destreg, amt); + } else { + u16 *destreg; + + destreg = DECODE_RM_WORD_REGISTER(rl); + amt = fetch_byte_imm(); + DECODE_PRINTF2(",%x\n", amt); + TRACE_AND_STEP(); + *destreg = (*opcD1_word_operation[rh]) (*destreg, amt); + } + break; + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0xc2 +****************************************************************************/ +static void x86emuOp_ret_near_IMM(u8 X86EMU_UNUSED(op1)) +{ + u16 imm; + + START_OF_INSTR(); + DECODE_PRINTF("RET\t"); + imm = fetch_word_imm(); + DECODE_PRINTF2("%x\n", imm); + RETURN_TRACE("RET",M.x86.saved_cs,M.x86.saved_ip); + TRACE_AND_STEP(); + M.x86.R_IP = pop_word(); + M.x86.R_SP += imm; + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0xc3 +****************************************************************************/ +static void x86emuOp_ret_near(u8 X86EMU_UNUSED(op1)) +{ + START_OF_INSTR(); + DECODE_PRINTF("RET\n"); + RETURN_TRACE("RET",M.x86.saved_cs,M.x86.saved_ip); + TRACE_AND_STEP(); + M.x86.R_IP = pop_word(); + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0xc4 +****************************************************************************/ +static void x86emuOp_les_R_IMM(u8 X86EMU_UNUSED(op1)) +{ + int mod, rh, rl; + u16 *dstreg; + uint srcoffset; + + START_OF_INSTR(); + DECODE_PRINTF("LES\t"); + FETCH_DECODE_MODRM(mod, rh, rl); + switch (mod) { + case 0: + dstreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF(","); + srcoffset = decode_rm00_address(rl); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *dstreg = fetch_data_word(srcoffset); + M.x86.R_ES = fetch_data_word(srcoffset + 2); + break; + case 1: + dstreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF(","); + srcoffset = decode_rm01_address(rl); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *dstreg = fetch_data_word(srcoffset); + M.x86.R_ES = fetch_data_word(srcoffset + 2); + break; + case 2: + dstreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF(","); + srcoffset = decode_rm10_address(rl); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *dstreg = fetch_data_word(srcoffset); + M.x86.R_ES = fetch_data_word(srcoffset + 2); + break; + case 3: /* register to register */ + /* UNDEFINED! */ + TRACE_AND_STEP(); + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0xc5 +****************************************************************************/ +static void x86emuOp_lds_R_IMM(u8 X86EMU_UNUSED(op1)) +{ + int mod, rh, rl; + u16 *dstreg; + uint srcoffset; + + START_OF_INSTR(); + DECODE_PRINTF("LDS\t"); + FETCH_DECODE_MODRM(mod, rh, rl); + switch (mod) { + case 0: + dstreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF(","); + srcoffset = decode_rm00_address(rl); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *dstreg = fetch_data_word(srcoffset); + M.x86.R_DS = fetch_data_word(srcoffset + 2); + break; + case 1: + dstreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF(","); + srcoffset = decode_rm01_address(rl); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *dstreg = fetch_data_word(srcoffset); + M.x86.R_DS = fetch_data_word(srcoffset + 2); + break; + case 2: + dstreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF(","); + srcoffset = decode_rm10_address(rl); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *dstreg = fetch_data_word(srcoffset); + M.x86.R_DS = fetch_data_word(srcoffset + 2); + break; + case 3: /* register to register */ + /* UNDEFINED! */ + TRACE_AND_STEP(); + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0xc6 +****************************************************************************/ +static void x86emuOp_mov_byte_RM_IMM(u8 X86EMU_UNUSED(op1)) +{ + int mod, rl, rh; + u8 *destreg; + uint destoffset; + u8 imm; + + START_OF_INSTR(); + DECODE_PRINTF("MOV\t"); + FETCH_DECODE_MODRM(mod, rh, rl); + if (rh != 0) { + DECODE_PRINTF("ILLEGAL DECODE OF OPCODE c6\n"); + HALT_SYS(); + } + switch (mod) { + case 0: + DECODE_PRINTF("BYTE PTR "); + destoffset = decode_rm00_address(rl); + imm = fetch_byte_imm(); + DECODE_PRINTF2(",%2x\n", imm); + TRACE_AND_STEP(); + store_data_byte(destoffset, imm); + break; + case 1: + DECODE_PRINTF("BYTE PTR "); + destoffset = decode_rm01_address(rl); + imm = fetch_byte_imm(); + DECODE_PRINTF2(",%2x\n", imm); + TRACE_AND_STEP(); + store_data_byte(destoffset, imm); + break; + case 2: + DECODE_PRINTF("BYTE PTR "); + destoffset = decode_rm10_address(rl); + imm = fetch_byte_imm(); + DECODE_PRINTF2(",%2x\n", imm); + TRACE_AND_STEP(); + store_data_byte(destoffset, imm); + break; + case 3: /* register to register */ + destreg = DECODE_RM_BYTE_REGISTER(rl); + imm = fetch_byte_imm(); + DECODE_PRINTF2(",%2x\n", imm); + TRACE_AND_STEP(); + *destreg = imm; + break; + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0xc7 +****************************************************************************/ +static void x86emuOp_mov_word_RM_IMM(u8 X86EMU_UNUSED(op1)) +{ + int mod, rl, rh; + uint destoffset; + + START_OF_INSTR(); + DECODE_PRINTF("MOV\t"); + FETCH_DECODE_MODRM(mod, rh, rl); + if (rh != 0) { + DECODE_PRINTF("ILLEGAL DECODE OF OPCODE 8F\n"); + HALT_SYS(); + } + switch (mod) { + case 0: + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 imm; + + DECODE_PRINTF("DWORD PTR "); + destoffset = decode_rm00_address(rl); + imm = fetch_long_imm(); + DECODE_PRINTF2(",%x\n", imm); + TRACE_AND_STEP(); + store_data_long(destoffset, imm); + } else { + u16 imm; + + DECODE_PRINTF("WORD PTR "); + destoffset = decode_rm00_address(rl); + imm = fetch_word_imm(); + DECODE_PRINTF2(",%x\n", imm); + TRACE_AND_STEP(); + store_data_word(destoffset, imm); + } + break; + case 1: + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 imm; + + DECODE_PRINTF("DWORD PTR "); + destoffset = decode_rm01_address(rl); + imm = fetch_long_imm(); + DECODE_PRINTF2(",%x\n", imm); + TRACE_AND_STEP(); + store_data_long(destoffset, imm); + } else { + u16 imm; + + DECODE_PRINTF("WORD PTR "); + destoffset = decode_rm01_address(rl); + imm = fetch_word_imm(); + DECODE_PRINTF2(",%x\n", imm); + TRACE_AND_STEP(); + store_data_word(destoffset, imm); + } + break; + case 2: + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 imm; + + DECODE_PRINTF("DWORD PTR "); + destoffset = decode_rm10_address(rl); + imm = fetch_long_imm(); + DECODE_PRINTF2(",%x\n", imm); + TRACE_AND_STEP(); + store_data_long(destoffset, imm); + } else { + u16 imm; + + DECODE_PRINTF("WORD PTR "); + destoffset = decode_rm10_address(rl); + imm = fetch_word_imm(); + DECODE_PRINTF2(",%x\n", imm); + TRACE_AND_STEP(); + store_data_word(destoffset, imm); + } + break; + case 3: /* register to register */ + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 *destreg; + u32 imm; + + destreg = DECODE_RM_LONG_REGISTER(rl); + imm = fetch_long_imm(); + DECODE_PRINTF2(",%x\n", imm); + TRACE_AND_STEP(); + *destreg = imm; + } else { + u16 *destreg; + u16 imm; + + destreg = DECODE_RM_WORD_REGISTER(rl); + imm = fetch_word_imm(); + DECODE_PRINTF2(",%x\n", imm); + TRACE_AND_STEP(); + *destreg = imm; + } + break; + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0xc8 +****************************************************************************/ +static void x86emuOp_enter(u8 X86EMU_UNUSED(op1)) +{ + u16 local,frame_pointer; + u8 nesting; + int i; + + START_OF_INSTR(); + local = fetch_word_imm(); + nesting = fetch_byte_imm(); + DECODE_PRINTF2("ENTER %x\n", local); + DECODE_PRINTF2(",%x\n", nesting); + TRACE_AND_STEP(); + push_word(M.x86.R_BP); + frame_pointer = M.x86.R_SP; + if (nesting > 0) { + for (i = 1; i < nesting; i++) { + M.x86.R_BP -= 2; + push_word(fetch_data_word_abs(M.x86.R_SS, M.x86.R_BP)); + } + push_word(frame_pointer); + } + M.x86.R_BP = frame_pointer; + M.x86.R_SP = (u16)(M.x86.R_SP - local); + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0xc9 +****************************************************************************/ +static void x86emuOp_leave(u8 X86EMU_UNUSED(op1)) +{ + START_OF_INSTR(); + DECODE_PRINTF("LEAVE\n"); + TRACE_AND_STEP(); + M.x86.R_SP = M.x86.R_BP; + M.x86.R_BP = pop_word(); + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0xca +****************************************************************************/ +static void x86emuOp_ret_far_IMM(u8 X86EMU_UNUSED(op1)) +{ + u16 imm; + + START_OF_INSTR(); + DECODE_PRINTF("RETF\t"); + imm = fetch_word_imm(); + DECODE_PRINTF2("%x\n", imm); + RETURN_TRACE("RETF",M.x86.saved_cs,M.x86.saved_ip); + TRACE_AND_STEP(); + M.x86.R_IP = pop_word(); + M.x86.R_CS = pop_word(); + M.x86.R_SP += imm; + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0xcb +****************************************************************************/ +static void x86emuOp_ret_far(u8 X86EMU_UNUSED(op1)) +{ + START_OF_INSTR(); + DECODE_PRINTF("RETF\n"); + RETURN_TRACE("RETF",M.x86.saved_cs,M.x86.saved_ip); + TRACE_AND_STEP(); + M.x86.R_IP = pop_word(); + M.x86.R_CS = pop_word(); + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0xcc +****************************************************************************/ +static void x86emuOp_int3(u8 X86EMU_UNUSED(op1)) +{ + START_OF_INSTR(); + DECODE_PRINTF("INT 3\n"); + TRACE_AND_STEP(); + if (_X86EMU_intrTab[3]) { + (*_X86EMU_intrTab[3])(3); + } else { + push_word((u16)M.x86.R_FLG); + CLEAR_FLAG(F_IF); + CLEAR_FLAG(F_TF); + push_word(M.x86.R_CS); + M.x86.R_CS = mem_access_word(3 * 4 + 2); + push_word(M.x86.R_IP); + M.x86.R_IP = mem_access_word(3 * 4); + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0xcd +****************************************************************************/ +static void x86emuOp_int_IMM(u8 X86EMU_UNUSED(op1)) +{ + u8 intnum; + + START_OF_INSTR(); + DECODE_PRINTF("INT\t"); + intnum = fetch_byte_imm(); + DECODE_PRINTF2("%x\n", intnum); + TRACE_AND_STEP(); + if (_X86EMU_intrTab[intnum]) { + (*_X86EMU_intrTab[intnum])(intnum); + } else { + push_word((u16)M.x86.R_FLG); + CLEAR_FLAG(F_IF); + CLEAR_FLAG(F_TF); + push_word(M.x86.R_CS); + M.x86.R_CS = mem_access_word(intnum * 4 + 2); + push_word(M.x86.R_IP); + M.x86.R_IP = mem_access_word(intnum * 4); + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0xce +****************************************************************************/ +static void x86emuOp_into(u8 X86EMU_UNUSED(op1)) +{ + START_OF_INSTR(); + DECODE_PRINTF("INTO\n"); + TRACE_AND_STEP(); + if (ACCESS_FLAG(F_OF)) { + if (_X86EMU_intrTab[4]) { + (*_X86EMU_intrTab[4])(4); + } else { + push_word((u16)M.x86.R_FLG); + CLEAR_FLAG(F_IF); + CLEAR_FLAG(F_TF); + push_word(M.x86.R_CS); + M.x86.R_CS = mem_access_word(4 * 4 + 2); + push_word(M.x86.R_IP); + M.x86.R_IP = mem_access_word(4 * 4); + } + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0xcf +****************************************************************************/ +static void x86emuOp_iret(u8 X86EMU_UNUSED(op1)) +{ + START_OF_INSTR(); + DECODE_PRINTF("IRET\n"); + + TRACE_AND_STEP(); + + M.x86.R_IP = pop_word(); + M.x86.R_CS = pop_word(); + M.x86.R_FLG = pop_word(); + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0xd0 +****************************************************************************/ +static void x86emuOp_opcD0_byte_RM_1(u8 X86EMU_UNUSED(op1)) +{ + int mod, rl, rh; + u8 *destreg; + uint destoffset; + u8 destval; + + /* + * Yet another weirdo special case instruction format. Part of + * the opcode held below in "RH". Doubly nested case would + * result, except that the decoded instruction + */ + START_OF_INSTR(); + FETCH_DECODE_MODRM(mod, rh, rl); +#ifdef X86EMU_DEBUG + if (DEBUG_DECODE()) { + /* XXX DECODE_PRINTF may be changed to something more + general, so that it is important to leave the strings + in the same format, even though the result is that the + above test is done twice. */ + switch (rh) { + case 0: + DECODE_PRINTF("ROL\t"); + break; + case 1: + DECODE_PRINTF("ROR\t"); + break; + case 2: + DECODE_PRINTF("RCL\t"); + break; + case 3: + DECODE_PRINTF("RCR\t"); + break; + case 4: + DECODE_PRINTF("SHL\t"); + break; + case 5: + DECODE_PRINTF("SHR\t"); + break; + case 6: + DECODE_PRINTF("SAL\t"); + break; + case 7: + DECODE_PRINTF("SAR\t"); + break; + } + } +#endif + /* know operation, decode the mod byte to find the addressing + mode. */ + switch (mod) { + case 0: + DECODE_PRINTF("BYTE PTR "); + destoffset = decode_rm00_address(rl); + DECODE_PRINTF(",1\n"); + destval = fetch_data_byte(destoffset); + TRACE_AND_STEP(); + destval = (*opcD0_byte_operation[rh]) (destval, 1); + store_data_byte(destoffset, destval); + break; + case 1: + DECODE_PRINTF("BYTE PTR "); + destoffset = decode_rm01_address(rl); + DECODE_PRINTF(",1\n"); + destval = fetch_data_byte(destoffset); + TRACE_AND_STEP(); + destval = (*opcD0_byte_operation[rh]) (destval, 1); + store_data_byte(destoffset, destval); + break; + case 2: + DECODE_PRINTF("BYTE PTR "); + destoffset = decode_rm10_address(rl); + DECODE_PRINTF(",1\n"); + destval = fetch_data_byte(destoffset); + TRACE_AND_STEP(); + destval = (*opcD0_byte_operation[rh]) (destval, 1); + store_data_byte(destoffset, destval); + break; + case 3: /* register to register */ + destreg = DECODE_RM_BYTE_REGISTER(rl); + DECODE_PRINTF(",1\n"); + TRACE_AND_STEP(); + destval = (*opcD0_byte_operation[rh]) (*destreg, 1); + *destreg = destval; + break; + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0xd1 +****************************************************************************/ +static void x86emuOp_opcD1_word_RM_1(u8 X86EMU_UNUSED(op1)) +{ + int mod, rl, rh; + uint destoffset; + + /* + * Yet another weirdo special case instruction format. Part of + * the opcode held below in "RH". Doubly nested case would + * result, except that the decoded instruction + */ + START_OF_INSTR(); + FETCH_DECODE_MODRM(mod, rh, rl); +#ifdef X86EMU_DEBUG + if (DEBUG_DECODE()) { + /* XXX DECODE_PRINTF may be changed to something more + general, so that it is important to leave the strings + in the same format, even though the result is that the + above test is done twice. */ + switch (rh) { + case 0: + DECODE_PRINTF("ROL\t"); + break; + case 1: + DECODE_PRINTF("ROR\t"); + break; + case 2: + DECODE_PRINTF("RCL\t"); + break; + case 3: + DECODE_PRINTF("RCR\t"); + break; + case 4: + DECODE_PRINTF("SHL\t"); + break; + case 5: + DECODE_PRINTF("SHR\t"); + break; + case 6: + DECODE_PRINTF("SAL\t"); + break; + case 7: + DECODE_PRINTF("SAR\t"); + break; + } + } +#endif + /* know operation, decode the mod byte to find the addressing + mode. */ + switch (mod) { + case 0: + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 destval; + + DECODE_PRINTF("DWORD PTR "); + destoffset = decode_rm00_address(rl); + DECODE_PRINTF(",1\n"); + destval = fetch_data_long(destoffset); + TRACE_AND_STEP(); + destval = (*opcD1_long_operation[rh]) (destval, 1); + store_data_long(destoffset, destval); + } else { + u16 destval; + + DECODE_PRINTF("WORD PTR "); + destoffset = decode_rm00_address(rl); + DECODE_PRINTF(",1\n"); + destval = fetch_data_word(destoffset); + TRACE_AND_STEP(); + destval = (*opcD1_word_operation[rh]) (destval, 1); + store_data_word(destoffset, destval); + } + break; + case 1: + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 destval; + + DECODE_PRINTF("DWORD PTR "); + destoffset = decode_rm01_address(rl); + DECODE_PRINTF(",1\n"); + destval = fetch_data_long(destoffset); + TRACE_AND_STEP(); + destval = (*opcD1_long_operation[rh]) (destval, 1); + store_data_long(destoffset, destval); + } else { + u16 destval; + + DECODE_PRINTF("WORD PTR "); + destoffset = decode_rm01_address(rl); + DECODE_PRINTF(",1\n"); + destval = fetch_data_word(destoffset); + TRACE_AND_STEP(); + destval = (*opcD1_word_operation[rh]) (destval, 1); + store_data_word(destoffset, destval); + } + break; + case 2: + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 destval; + + DECODE_PRINTF("DWORD PTR "); + destoffset = decode_rm10_address(rl); + DECODE_PRINTF(",1\n"); + destval = fetch_data_long(destoffset); + TRACE_AND_STEP(); + destval = (*opcD1_long_operation[rh]) (destval, 1); + store_data_long(destoffset, destval); + } else { + u16 destval; + + DECODE_PRINTF("BYTE PTR "); + destoffset = decode_rm10_address(rl); + DECODE_PRINTF(",1\n"); + destval = fetch_data_word(destoffset); + TRACE_AND_STEP(); + destval = (*opcD1_word_operation[rh]) (destval, 1); + store_data_word(destoffset, destval); + } + break; + case 3: /* register to register */ + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 destval; + u32 *destreg; + + destreg = DECODE_RM_LONG_REGISTER(rl); + DECODE_PRINTF(",1\n"); + TRACE_AND_STEP(); + destval = (*opcD1_long_operation[rh]) (*destreg, 1); + *destreg = destval; + } else { + u16 destval; + u16 *destreg; + + destreg = DECODE_RM_WORD_REGISTER(rl); + DECODE_PRINTF(",1\n"); + TRACE_AND_STEP(); + destval = (*opcD1_word_operation[rh]) (*destreg, 1); + *destreg = destval; + } + break; + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0xd2 +****************************************************************************/ +static void x86emuOp_opcD2_byte_RM_CL(u8 X86EMU_UNUSED(op1)) +{ + int mod, rl, rh; + u8 *destreg; + uint destoffset; + u8 destval; + u8 amt; + + /* + * Yet another weirdo special case instruction format. Part of + * the opcode held below in "RH". Doubly nested case would + * result, except that the decoded instruction + */ + START_OF_INSTR(); + FETCH_DECODE_MODRM(mod, rh, rl); +#ifdef X86EMU_DEBUG + if (DEBUG_DECODE()) { + /* XXX DECODE_PRINTF may be changed to something more + general, so that it is important to leave the strings + in the same format, even though the result is that the + above test is done twice. */ + switch (rh) { + case 0: + DECODE_PRINTF("ROL\t"); + break; + case 1: + DECODE_PRINTF("ROR\t"); + break; + case 2: + DECODE_PRINTF("RCL\t"); + break; + case 3: + DECODE_PRINTF("RCR\t"); + break; + case 4: + DECODE_PRINTF("SHL\t"); + break; + case 5: + DECODE_PRINTF("SHR\t"); + break; + case 6: + DECODE_PRINTF("SAL\t"); + break; + case 7: + DECODE_PRINTF("SAR\t"); + break; + } + } +#endif + /* know operation, decode the mod byte to find the addressing + mode. */ + amt = M.x86.R_CL; + switch (mod) { + case 0: + DECODE_PRINTF("BYTE PTR "); + destoffset = decode_rm00_address(rl); + DECODE_PRINTF(",CL\n"); + destval = fetch_data_byte(destoffset); + TRACE_AND_STEP(); + destval = (*opcD0_byte_operation[rh]) (destval, amt); + store_data_byte(destoffset, destval); + break; + case 1: + DECODE_PRINTF("BYTE PTR "); + destoffset = decode_rm01_address(rl); + DECODE_PRINTF(",CL\n"); + destval = fetch_data_byte(destoffset); + TRACE_AND_STEP(); + destval = (*opcD0_byte_operation[rh]) (destval, amt); + store_data_byte(destoffset, destval); + break; + case 2: + DECODE_PRINTF("BYTE PTR "); + destoffset = decode_rm10_address(rl); + DECODE_PRINTF(",CL\n"); + destval = fetch_data_byte(destoffset); + TRACE_AND_STEP(); + destval = (*opcD0_byte_operation[rh]) (destval, amt); + store_data_byte(destoffset, destval); + break; + case 3: /* register to register */ + destreg = DECODE_RM_BYTE_REGISTER(rl); + DECODE_PRINTF(",CL\n"); + TRACE_AND_STEP(); + destval = (*opcD0_byte_operation[rh]) (*destreg, amt); + *destreg = destval; + break; + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0xd3 +****************************************************************************/ +static void x86emuOp_opcD3_word_RM_CL(u8 X86EMU_UNUSED(op1)) +{ + int mod, rl, rh; + uint destoffset; + u8 amt; + + /* + * Yet another weirdo special case instruction format. Part of + * the opcode held below in "RH". Doubly nested case would + * result, except that the decoded instruction + */ + START_OF_INSTR(); + FETCH_DECODE_MODRM(mod, rh, rl); +#ifdef X86EMU_DEBUG + if (DEBUG_DECODE()) { + /* XXX DECODE_PRINTF may be changed to something more + general, so that it is important to leave the strings + in the same format, even though the result is that the + above test is done twice. */ + switch (rh) { + case 0: + DECODE_PRINTF("ROL\t"); + break; + case 1: + DECODE_PRINTF("ROR\t"); + break; + case 2: + DECODE_PRINTF("RCL\t"); + break; + case 3: + DECODE_PRINTF("RCR\t"); + break; + case 4: + DECODE_PRINTF("SHL\t"); + break; + case 5: + DECODE_PRINTF("SHR\t"); + break; + case 6: + DECODE_PRINTF("SAL\t"); + break; + case 7: + DECODE_PRINTF("SAR\t"); + break; + } + } +#endif + /* know operation, decode the mod byte to find the addressing + mode. */ + amt = M.x86.R_CL; + switch (mod) { + case 0: + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 destval; + + DECODE_PRINTF("DWORD PTR "); + destoffset = decode_rm00_address(rl); + DECODE_PRINTF(",CL\n"); + destval = fetch_data_long(destoffset); + TRACE_AND_STEP(); + destval = (*opcD1_long_operation[rh]) (destval, amt); + store_data_long(destoffset, destval); + } else { + u16 destval; + + DECODE_PRINTF("WORD PTR "); + destoffset = decode_rm00_address(rl); + DECODE_PRINTF(",CL\n"); + destval = fetch_data_word(destoffset); + TRACE_AND_STEP(); + destval = (*opcD1_word_operation[rh]) (destval, amt); + store_data_word(destoffset, destval); + } + break; + case 1: + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 destval; + + DECODE_PRINTF("DWORD PTR "); + destoffset = decode_rm01_address(rl); + DECODE_PRINTF(",CL\n"); + destval = fetch_data_long(destoffset); + TRACE_AND_STEP(); + destval = (*opcD1_long_operation[rh]) (destval, amt); + store_data_long(destoffset, destval); + } else { + u16 destval; + + DECODE_PRINTF("WORD PTR "); + destoffset = decode_rm01_address(rl); + DECODE_PRINTF(",CL\n"); + destval = fetch_data_word(destoffset); + TRACE_AND_STEP(); + destval = (*opcD1_word_operation[rh]) (destval, amt); + store_data_word(destoffset, destval); + } + break; + case 2: + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 destval; + + DECODE_PRINTF("DWORD PTR "); + destoffset = decode_rm10_address(rl); + DECODE_PRINTF(",CL\n"); + destval = fetch_data_long(destoffset); + TRACE_AND_STEP(); + destval = (*opcD1_long_operation[rh]) (destval, amt); + store_data_long(destoffset, destval); + } else { + u16 destval; + + DECODE_PRINTF("WORD PTR "); + destoffset = decode_rm10_address(rl); + DECODE_PRINTF(",CL\n"); + destval = fetch_data_word(destoffset); + TRACE_AND_STEP(); + destval = (*opcD1_word_operation[rh]) (destval, amt); + store_data_word(destoffset, destval); + } + break; + case 3: /* register to register */ + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 *destreg; + + destreg = DECODE_RM_LONG_REGISTER(rl); + DECODE_PRINTF(",CL\n"); + TRACE_AND_STEP(); + *destreg = (*opcD1_long_operation[rh]) (*destreg, amt); + } else { + u16 *destreg; + + destreg = DECODE_RM_WORD_REGISTER(rl); + DECODE_PRINTF(",CL\n"); + TRACE_AND_STEP(); + *destreg = (*opcD1_word_operation[rh]) (*destreg, amt); + } + break; + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0xd4 +****************************************************************************/ +static void x86emuOp_aam(u8 X86EMU_UNUSED(op1)) +{ + u8 a; + + START_OF_INSTR(); + DECODE_PRINTF("AAM\n"); + a = fetch_byte_imm(); /* this is a stupid encoding. */ + if (a != 10) { + /* fix: add base decoding + aam_word(u8 val, int base a) */ + DECODE_PRINTF("ERROR DECODING AAM\n"); + TRACE_REGS(); + HALT_SYS(); + } + TRACE_AND_STEP(); + /* note the type change here --- returning AL and AH in AX. */ + M.x86.R_AX = aam_word(M.x86.R_AL); + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0xd5 +****************************************************************************/ +static void x86emuOp_aad(u8 X86EMU_UNUSED(op1)) +{ + u8 a; + + START_OF_INSTR(); + DECODE_PRINTF("AAD\n"); + a = fetch_byte_imm(); + if (a != 10) { + /* fix: add base decoding + aad_word(u16 val, int base a) */ + DECODE_PRINTF("ERROR DECODING AAM\n"); + TRACE_REGS(); + HALT_SYS(); + } + TRACE_AND_STEP(); + M.x86.R_AX = aad_word(M.x86.R_AX); + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/* opcode 0xd6 ILLEGAL OPCODE */ + +/**************************************************************************** +REMARKS: +Handles opcode 0xd7 +****************************************************************************/ +static void x86emuOp_xlat(u8 X86EMU_UNUSED(op1)) +{ + u16 addr; + + START_OF_INSTR(); + DECODE_PRINTF("XLAT\n"); + TRACE_AND_STEP(); + addr = (u16)(M.x86.R_BX + (u8)M.x86.R_AL); + M.x86.R_AL = fetch_data_byte(addr); + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/* instuctions D8 .. DF are in i87_ops.c */ + +/**************************************************************************** +REMARKS: +Handles opcode 0xe0 +****************************************************************************/ +static void x86emuOp_loopne(u8 X86EMU_UNUSED(op1)) +{ + s16 ip; + + START_OF_INSTR(); + DECODE_PRINTF("LOOPNE\t"); + ip = (s8) fetch_byte_imm(); + ip += (s16) M.x86.R_IP; + DECODE_PRINTF2("%04x\n", ip); + TRACE_AND_STEP(); + M.x86.R_CX -= 1; + if (M.x86.R_CX != 0 && !ACCESS_FLAG(F_ZF)) /* CX != 0 and !ZF */ + M.x86.R_IP = ip; + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0xe1 +****************************************************************************/ +static void x86emuOp_loope(u8 X86EMU_UNUSED(op1)) +{ + s16 ip; + + START_OF_INSTR(); + DECODE_PRINTF("LOOPE\t"); + ip = (s8) fetch_byte_imm(); + ip += (s16) M.x86.R_IP; + DECODE_PRINTF2("%04x\n", ip); + TRACE_AND_STEP(); + M.x86.R_CX -= 1; + if (M.x86.R_CX != 0 && ACCESS_FLAG(F_ZF)) /* CX != 0 and ZF */ + M.x86.R_IP = ip; + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0xe2 +****************************************************************************/ +static void x86emuOp_loop(u8 X86EMU_UNUSED(op1)) +{ + s16 ip; + + START_OF_INSTR(); + DECODE_PRINTF("LOOP\t"); + ip = (s8) fetch_byte_imm(); + ip += (s16) M.x86.R_IP; + DECODE_PRINTF2("%04x\n", ip); + TRACE_AND_STEP(); + M.x86.R_CX -= 1; + if (M.x86.R_CX != 0) + M.x86.R_IP = ip; + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0xe3 +****************************************************************************/ +static void x86emuOp_jcxz(u8 X86EMU_UNUSED(op1)) +{ + u16 target; + s8 offset; + + /* jump to byte offset if overflow flag is set */ + START_OF_INSTR(); + DECODE_PRINTF("JCXZ\t"); + offset = (s8)fetch_byte_imm(); + target = (u16)(M.x86.R_IP + offset); + DECODE_PRINTF2("%x\n", target); + TRACE_AND_STEP(); + if (M.x86.R_CX == 0) + M.x86.R_IP = target; + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0xe4 +****************************************************************************/ +static void x86emuOp_in_byte_AL_IMM(u8 X86EMU_UNUSED(op1)) +{ + u8 port; + + START_OF_INSTR(); + DECODE_PRINTF("IN\t"); + port = (u8) fetch_byte_imm(); + DECODE_PRINTF2("%x,AL\n", port); + TRACE_AND_STEP(); + M.x86.R_AL = (*sys_inb)(port); + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0xe5 +****************************************************************************/ +static void x86emuOp_in_word_AX_IMM(u8 X86EMU_UNUSED(op1)) +{ + u8 port; + + START_OF_INSTR(); + DECODE_PRINTF("IN\t"); + port = (u8) fetch_byte_imm(); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + DECODE_PRINTF2("EAX,%x\n", port); + } else { + DECODE_PRINTF2("AX,%x\n", port); + } + TRACE_AND_STEP(); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + M.x86.R_EAX = (*sys_inl)(port); + } else { + M.x86.R_AX = (*sys_inw)(port); + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0xe6 +****************************************************************************/ +static void x86emuOp_out_byte_IMM_AL(u8 X86EMU_UNUSED(op1)) +{ + u8 port; + + START_OF_INSTR(); + DECODE_PRINTF("OUT\t"); + port = (u8) fetch_byte_imm(); + DECODE_PRINTF2("%x,AL\n", port); + TRACE_AND_STEP(); + (*sys_outb)(port, M.x86.R_AL); + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0xe7 +****************************************************************************/ +static void x86emuOp_out_word_IMM_AX(u8 X86EMU_UNUSED(op1)) +{ + u8 port; + + START_OF_INSTR(); + DECODE_PRINTF("OUT\t"); + port = (u8) fetch_byte_imm(); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + DECODE_PRINTF2("%x,EAX\n", port); + } else { + DECODE_PRINTF2("%x,AX\n", port); + } + TRACE_AND_STEP(); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + (*sys_outl)(port, M.x86.R_EAX); + } else { + (*sys_outw)(port, M.x86.R_AX); + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0xe8 +****************************************************************************/ +static void x86emuOp_call_near_IMM(u8 X86EMU_UNUSED(op1)) +{ + s16 ip16 = 0; + s32 ip32 = 0; + + START_OF_INSTR(); + DECODE_PRINTF("CALL\t"); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + ip32 = (s32) fetch_long_imm(); + ip32 += (s16) M.x86.R_IP; /* CHECK SIGN */ + DECODE_PRINTF2("%04x\n", (u16)ip32); + CALL_TRACE(M.x86.saved_cs, M.x86.saved_ip, M.x86.R_CS, ip32, ""); + } else { + ip16 = (s16) fetch_word_imm(); + ip16 += (s16) M.x86.R_IP; /* CHECK SIGN */ + DECODE_PRINTF2("%04x\n", (u16)ip16); + CALL_TRACE(M.x86.saved_cs, M.x86.saved_ip, M.x86.R_CS, ip16, ""); + } + TRACE_AND_STEP(); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + push_long(M.x86.R_EIP); + M.x86.R_EIP = ip32 & 0xffff; + } else { + push_word(M.x86.R_IP); + M.x86.R_EIP = ip16; + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0xe9 +****************************************************************************/ +static void x86emuOp_jump_near_IMM(u8 X86EMU_UNUSED(op1)) +{ + s32 ip; + + START_OF_INSTR(); + DECODE_PRINTF("JMP\t"); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + ip = (s32)fetch_long_imm(); + ip += (s32)M.x86.R_EIP; + DECODE_PRINTF2("%08x\n", (u32)ip); + TRACE_AND_STEP(); + M.x86.R_EIP = (u32)ip; + } else { + ip = (s16)fetch_word_imm(); + ip += (s16)M.x86.R_IP; + DECODE_PRINTF2("%04x\n", (u16)ip); + TRACE_AND_STEP(); + M.x86.R_IP = (u16)ip; + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0xea +****************************************************************************/ +static void x86emuOp_jump_far_IMM(u8 X86EMU_UNUSED(op1)) +{ + u16 cs; + u32 ip; + + START_OF_INSTR(); + DECODE_PRINTF("JMP\tFAR "); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + ip = fetch_long_imm(); + } else { + ip = fetch_word_imm(); + } + cs = fetch_word_imm(); + DECODE_PRINTF2("%04x:", cs); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + DECODE_PRINTF2("%08x\n", ip); + } else { + DECODE_PRINTF2("%04x\n", (u16)ip); + } + TRACE_AND_STEP(); + M.x86.R_EIP = ip & 0xffff; + M.x86.R_CS = cs; + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0xeb +****************************************************************************/ +static void x86emuOp_jump_byte_IMM(u8 X86EMU_UNUSED(op1)) +{ + u16 target; + s8 offset; + + START_OF_INSTR(); + DECODE_PRINTF("JMP\t"); + offset = (s8)fetch_byte_imm(); + target = (u16)(M.x86.R_IP + offset); + DECODE_PRINTF2("%x\n", target); + TRACE_AND_STEP(); + M.x86.R_IP = target; + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0xec +****************************************************************************/ +static void x86emuOp_in_byte_AL_DX(u8 X86EMU_UNUSED(op1)) +{ + START_OF_INSTR(); + DECODE_PRINTF("IN\tAL,DX\n"); + TRACE_AND_STEP(); + M.x86.R_AL = (*sys_inb)(M.x86.R_DX); + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0xed +****************************************************************************/ +static void x86emuOp_in_word_AX_DX(u8 X86EMU_UNUSED(op1)) +{ + START_OF_INSTR(); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + DECODE_PRINTF("IN\tEAX,DX\n"); + } else { + DECODE_PRINTF("IN\tAX,DX\n"); + } + TRACE_AND_STEP(); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + M.x86.R_EAX = (*sys_inl)(M.x86.R_DX); + } else { + M.x86.R_AX = (*sys_inw)(M.x86.R_DX); + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0xee +****************************************************************************/ +static void x86emuOp_out_byte_DX_AL(u8 X86EMU_UNUSED(op1)) +{ + START_OF_INSTR(); + DECODE_PRINTF("OUT\tDX,AL\n"); + TRACE_AND_STEP(); + (*sys_outb)(M.x86.R_DX, M.x86.R_AL); + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0xef +****************************************************************************/ +static void x86emuOp_out_word_DX_AX(u8 X86EMU_UNUSED(op1)) +{ + START_OF_INSTR(); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + DECODE_PRINTF("OUT\tDX,EAX\n"); + } else { + DECODE_PRINTF("OUT\tDX,AX\n"); + } + TRACE_AND_STEP(); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + (*sys_outl)(M.x86.R_DX, M.x86.R_EAX); + } else { + (*sys_outw)(M.x86.R_DX, M.x86.R_AX); + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0xf0 +****************************************************************************/ +static void x86emuOp_lock(u8 X86EMU_UNUSED(op1)) +{ + START_OF_INSTR(); + DECODE_PRINTF("LOCK:\n"); + TRACE_AND_STEP(); + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/*opcode 0xf1 ILLEGAL OPERATION */ + +/**************************************************************************** +REMARKS: +Handles opcode 0xf2 +****************************************************************************/ +static void x86emuOp_repne(u8 X86EMU_UNUSED(op1)) +{ + START_OF_INSTR(); + DECODE_PRINTF("REPNE\n"); + TRACE_AND_STEP(); + M.x86.mode |= SYSMODE_PREFIX_REPNE; + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0xf3 +****************************************************************************/ +static void x86emuOp_repe(u8 X86EMU_UNUSED(op1)) +{ + START_OF_INSTR(); + DECODE_PRINTF("REPE\n"); + TRACE_AND_STEP(); + M.x86.mode |= SYSMODE_PREFIX_REPE; + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0xf4 +****************************************************************************/ +static void x86emuOp_halt(u8 X86EMU_UNUSED(op1)) +{ + START_OF_INSTR(); + DECODE_PRINTF("HALT\n"); + TRACE_AND_STEP(); + HALT_SYS(); + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0xf5 +****************************************************************************/ +static void x86emuOp_cmc(u8 X86EMU_UNUSED(op1)) +{ + /* complement the carry flag. */ + START_OF_INSTR(); + DECODE_PRINTF("CMC\n"); + TRACE_AND_STEP(); + TOGGLE_FLAG(F_CF); + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0xf6 +****************************************************************************/ +static void x86emuOp_opcF6_byte_RM(u8 X86EMU_UNUSED(op1)) +{ + int mod, rl, rh; + u8 *destreg; + uint destoffset; + u8 destval, srcval; + + /* long, drawn out code follows. Double switch for a total + of 32 cases. */ + START_OF_INSTR(); + FETCH_DECODE_MODRM(mod, rh, rl); + switch (mod) { + case 0: /* mod=00 */ + switch (rh) { + case 0: /* test byte imm */ + DECODE_PRINTF("TEST\tBYTE PTR "); + destoffset = decode_rm00_address(rl); + DECODE_PRINTF(","); + srcval = fetch_byte_imm(); + DECODE_PRINTF2("%02x\n", srcval); + destval = fetch_data_byte(destoffset); + TRACE_AND_STEP(); + test_byte(destval, srcval); + break; + case 1: + DECODE_PRINTF("ILLEGAL OP MOD=00 RH=01 OP=F6\n"); + HALT_SYS(); + break; + case 2: + DECODE_PRINTF("NOT\tBYTE PTR "); + destoffset = decode_rm00_address(rl); + DECODE_PRINTF("\n"); + destval = fetch_data_byte(destoffset); + TRACE_AND_STEP(); + destval = not_byte(destval); + store_data_byte(destoffset, destval); + break; + case 3: + DECODE_PRINTF("NEG\tBYTE PTR "); + destoffset = decode_rm00_address(rl); + DECODE_PRINTF("\n"); + destval = fetch_data_byte(destoffset); + TRACE_AND_STEP(); + destval = neg_byte(destval); + store_data_byte(destoffset, destval); + break; + case 4: + DECODE_PRINTF("MUL\tBYTE PTR "); + destoffset = decode_rm00_address(rl); + DECODE_PRINTF("\n"); + destval = fetch_data_byte(destoffset); + TRACE_AND_STEP(); + mul_byte(destval); + break; + case 5: + DECODE_PRINTF("IMUL\tBYTE PTR "); + destoffset = decode_rm00_address(rl); + DECODE_PRINTF("\n"); + destval = fetch_data_byte(destoffset); + TRACE_AND_STEP(); + imul_byte(destval); + break; + case 6: + DECODE_PRINTF("DIV\tBYTE PTR "); + destoffset = decode_rm00_address(rl); + DECODE_PRINTF("\n"); + destval = fetch_data_byte(destoffset); + TRACE_AND_STEP(); + div_byte(destval); + break; + case 7: + DECODE_PRINTF("IDIV\tBYTE PTR "); + destoffset = decode_rm00_address(rl); + DECODE_PRINTF("\n"); + destval = fetch_data_byte(destoffset); + TRACE_AND_STEP(); + idiv_byte(destval); + break; + } + break; /* end mod==00 */ + case 1: /* mod=01 */ + switch (rh) { + case 0: /* test byte imm */ + DECODE_PRINTF("TEST\tBYTE PTR "); + destoffset = decode_rm01_address(rl); + DECODE_PRINTF(","); + srcval = fetch_byte_imm(); + DECODE_PRINTF2("%02x\n", srcval); + destval = fetch_data_byte(destoffset); + TRACE_AND_STEP(); + test_byte(destval, srcval); + break; + case 1: + DECODE_PRINTF("ILLEGAL OP MOD=01 RH=01 OP=F6\n"); + HALT_SYS(); + break; + case 2: + DECODE_PRINTF("NOT\tBYTE PTR "); + destoffset = decode_rm01_address(rl); + DECODE_PRINTF("\n"); + destval = fetch_data_byte(destoffset); + TRACE_AND_STEP(); + destval = not_byte(destval); + store_data_byte(destoffset, destval); + break; + case 3: + DECODE_PRINTF("NEG\tBYTE PTR "); + destoffset = decode_rm01_address(rl); + DECODE_PRINTF("\n"); + destval = fetch_data_byte(destoffset); + TRACE_AND_STEP(); + destval = neg_byte(destval); + store_data_byte(destoffset, destval); + break; + case 4: + DECODE_PRINTF("MUL\tBYTE PTR "); + destoffset = decode_rm01_address(rl); + DECODE_PRINTF("\n"); + destval = fetch_data_byte(destoffset); + TRACE_AND_STEP(); + mul_byte(destval); + break; + case 5: + DECODE_PRINTF("IMUL\tBYTE PTR "); + destoffset = decode_rm01_address(rl); + DECODE_PRINTF("\n"); + destval = fetch_data_byte(destoffset); + TRACE_AND_STEP(); + imul_byte(destval); + break; + case 6: + DECODE_PRINTF("DIV\tBYTE PTR "); + destoffset = decode_rm01_address(rl); + DECODE_PRINTF("\n"); + destval = fetch_data_byte(destoffset); + TRACE_AND_STEP(); + div_byte(destval); + break; + case 7: + DECODE_PRINTF("IDIV\tBYTE PTR "); + destoffset = decode_rm01_address(rl); + DECODE_PRINTF("\n"); + destval = fetch_data_byte(destoffset); + TRACE_AND_STEP(); + idiv_byte(destval); + break; + } + break; /* end mod==01 */ + case 2: /* mod=10 */ + switch (rh) { + case 0: /* test byte imm */ + DECODE_PRINTF("TEST\tBYTE PTR "); + destoffset = decode_rm10_address(rl); + DECODE_PRINTF(","); + srcval = fetch_byte_imm(); + DECODE_PRINTF2("%02x\n", srcval); + destval = fetch_data_byte(destoffset); + TRACE_AND_STEP(); + test_byte(destval, srcval); + break; + case 1: + DECODE_PRINTF("ILLEGAL OP MOD=10 RH=01 OP=F6\n"); + HALT_SYS(); + break; + case 2: + DECODE_PRINTF("NOT\tBYTE PTR "); + destoffset = decode_rm10_address(rl); + DECODE_PRINTF("\n"); + destval = fetch_data_byte(destoffset); + TRACE_AND_STEP(); + destval = not_byte(destval); + store_data_byte(destoffset, destval); + break; + case 3: + DECODE_PRINTF("NEG\tBYTE PTR "); + destoffset = decode_rm10_address(rl); + DECODE_PRINTF("\n"); + destval = fetch_data_byte(destoffset); + TRACE_AND_STEP(); + destval = neg_byte(destval); + store_data_byte(destoffset, destval); + break; + case 4: + DECODE_PRINTF("MUL\tBYTE PTR "); + destoffset = decode_rm10_address(rl); + DECODE_PRINTF("\n"); + destval = fetch_data_byte(destoffset); + TRACE_AND_STEP(); + mul_byte(destval); + break; + case 5: + DECODE_PRINTF("IMUL\tBYTE PTR "); + destoffset = decode_rm10_address(rl); + DECODE_PRINTF("\n"); + destval = fetch_data_byte(destoffset); + TRACE_AND_STEP(); + imul_byte(destval); + break; + case 6: + DECODE_PRINTF("DIV\tBYTE PTR "); + destoffset = decode_rm10_address(rl); + DECODE_PRINTF("\n"); + destval = fetch_data_byte(destoffset); + TRACE_AND_STEP(); + div_byte(destval); + break; + case 7: + DECODE_PRINTF("IDIV\tBYTE PTR "); + destoffset = decode_rm10_address(rl); + DECODE_PRINTF("\n"); + destval = fetch_data_byte(destoffset); + TRACE_AND_STEP(); + idiv_byte(destval); + break; + } + break; /* end mod==10 */ + case 3: /* mod=11 */ + switch (rh) { + case 0: /* test byte imm */ + DECODE_PRINTF("TEST\t"); + destreg = DECODE_RM_BYTE_REGISTER(rl); + DECODE_PRINTF(","); + srcval = fetch_byte_imm(); + DECODE_PRINTF2("%02x\n", srcval); + TRACE_AND_STEP(); + test_byte(*destreg, srcval); + break; + case 1: + DECODE_PRINTF("ILLEGAL OP MOD=00 RH=01 OP=F6\n"); + HALT_SYS(); + break; + case 2: + DECODE_PRINTF("NOT\t"); + destreg = DECODE_RM_BYTE_REGISTER(rl); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = not_byte(*destreg); + break; + case 3: + DECODE_PRINTF("NEG\t"); + destreg = DECODE_RM_BYTE_REGISTER(rl); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = neg_byte(*destreg); + break; + case 4: + DECODE_PRINTF("MUL\t"); + destreg = DECODE_RM_BYTE_REGISTER(rl); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + mul_byte(*destreg); /*!!! */ + break; + case 5: + DECODE_PRINTF("IMUL\t"); + destreg = DECODE_RM_BYTE_REGISTER(rl); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + imul_byte(*destreg); + break; + case 6: + DECODE_PRINTF("DIV\t"); + destreg = DECODE_RM_BYTE_REGISTER(rl); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + div_byte(*destreg); + break; + case 7: + DECODE_PRINTF("IDIV\t"); + destreg = DECODE_RM_BYTE_REGISTER(rl); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + idiv_byte(*destreg); + break; + } + break; /* end mod==11 */ + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0xf7 +****************************************************************************/ +static void x86emuOp_opcF7_word_RM(u8 X86EMU_UNUSED(op1)) +{ + int mod, rl, rh; + uint destoffset; + + /* long, drawn out code follows. Double switch for a total + of 32 cases. */ + START_OF_INSTR(); + FETCH_DECODE_MODRM(mod, rh, rl); + switch (mod) { + case 0: /* mod=00 */ + switch (rh) { + case 0: /* test word imm */ + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 destval,srcval; + + DECODE_PRINTF("TEST\tDWORD PTR "); + destoffset = decode_rm00_address(rl); + DECODE_PRINTF(","); + srcval = fetch_long_imm(); + DECODE_PRINTF2("%x\n", srcval); + destval = fetch_data_long(destoffset); + TRACE_AND_STEP(); + test_long(destval, srcval); + } else { + u16 destval,srcval; + + DECODE_PRINTF("TEST\tWORD PTR "); + destoffset = decode_rm00_address(rl); + DECODE_PRINTF(","); + srcval = fetch_word_imm(); + DECODE_PRINTF2("%x\n", srcval); + destval = fetch_data_word(destoffset); + TRACE_AND_STEP(); + test_word(destval, srcval); + } + break; + case 1: + DECODE_PRINTF("ILLEGAL OP MOD=00 RH=01 OP=F7\n"); + HALT_SYS(); + break; + case 2: + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 destval; + + DECODE_PRINTF("NOT\tDWORD PTR "); + destoffset = decode_rm00_address(rl); + DECODE_PRINTF("\n"); + destval = fetch_data_long(destoffset); + TRACE_AND_STEP(); + destval = not_long(destval); + store_data_long(destoffset, destval); + } else { + u16 destval; + + DECODE_PRINTF("NOT\tWORD PTR "); + destoffset = decode_rm00_address(rl); + DECODE_PRINTF("\n"); + destval = fetch_data_word(destoffset); + TRACE_AND_STEP(); + destval = not_word(destval); + store_data_word(destoffset, destval); + } + break; + case 3: + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 destval; + + DECODE_PRINTF("NEG\tDWORD PTR "); + destoffset = decode_rm00_address(rl); + DECODE_PRINTF("\n"); + destval = fetch_data_long(destoffset); + TRACE_AND_STEP(); + destval = neg_long(destval); + store_data_long(destoffset, destval); + } else { + u16 destval; + + DECODE_PRINTF("NEG\tWORD PTR "); + destoffset = decode_rm00_address(rl); + DECODE_PRINTF("\n"); + destval = fetch_data_word(destoffset); + TRACE_AND_STEP(); + destval = neg_word(destval); + store_data_word(destoffset, destval); + } + break; + case 4: + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 destval; + + DECODE_PRINTF("MUL\tDWORD PTR "); + destoffset = decode_rm00_address(rl); + DECODE_PRINTF("\n"); + destval = fetch_data_long(destoffset); + TRACE_AND_STEP(); + mul_long(destval); + } else { + u16 destval; + + DECODE_PRINTF("MUL\tWORD PTR "); + destoffset = decode_rm00_address(rl); + DECODE_PRINTF("\n"); + destval = fetch_data_word(destoffset); + TRACE_AND_STEP(); + mul_word(destval); + } + break; + case 5: + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 destval; + + DECODE_PRINTF("IMUL\tDWORD PTR "); + destoffset = decode_rm00_address(rl); + DECODE_PRINTF("\n"); + destval = fetch_data_long(destoffset); + TRACE_AND_STEP(); + imul_long(destval); + } else { + u16 destval; + + DECODE_PRINTF("IMUL\tWORD PTR "); + destoffset = decode_rm00_address(rl); + DECODE_PRINTF("\n"); + destval = fetch_data_word(destoffset); + TRACE_AND_STEP(); + imul_word(destval); + } + break; + case 6: + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 destval; + + DECODE_PRINTF("DIV\tDWORD PTR "); + destoffset = decode_rm00_address(rl); + DECODE_PRINTF("\n"); + destval = fetch_data_long(destoffset); + TRACE_AND_STEP(); + div_long(destval); + } else { + u16 destval; + + DECODE_PRINTF("DIV\tWORD PTR "); + destoffset = decode_rm00_address(rl); + DECODE_PRINTF("\n"); + destval = fetch_data_word(destoffset); + TRACE_AND_STEP(); + div_word(destval); + } + break; + case 7: + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 destval; + + DECODE_PRINTF("IDIV\tDWORD PTR "); + destoffset = decode_rm00_address(rl); + DECODE_PRINTF("\n"); + destval = fetch_data_long(destoffset); + TRACE_AND_STEP(); + idiv_long(destval); + } else { + u16 destval; + + DECODE_PRINTF("IDIV\tWORD PTR "); + destoffset = decode_rm00_address(rl); + DECODE_PRINTF("\n"); + destval = fetch_data_word(destoffset); + TRACE_AND_STEP(); + idiv_word(destval); + } + break; + } + break; /* end mod==00 */ + case 1: /* mod=01 */ + switch (rh) { + case 0: /* test word imm */ + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 destval,srcval; + + DECODE_PRINTF("TEST\tDWORD PTR "); + destoffset = decode_rm01_address(rl); + DECODE_PRINTF(","); + srcval = fetch_long_imm(); + DECODE_PRINTF2("%x\n", srcval); + destval = fetch_data_long(destoffset); + TRACE_AND_STEP(); + test_long(destval, srcval); + } else { + u16 destval,srcval; + + DECODE_PRINTF("TEST\tWORD PTR "); + destoffset = decode_rm01_address(rl); + DECODE_PRINTF(","); + srcval = fetch_word_imm(); + DECODE_PRINTF2("%x\n", srcval); + destval = fetch_data_word(destoffset); + TRACE_AND_STEP(); + test_word(destval, srcval); + } + break; + case 1: + DECODE_PRINTF("ILLEGAL OP MOD=01 RH=01 OP=F6\n"); + HALT_SYS(); + break; + case 2: + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 destval; + + DECODE_PRINTF("NOT\tDWORD PTR "); + destoffset = decode_rm01_address(rl); + DECODE_PRINTF("\n"); + destval = fetch_data_long(destoffset); + TRACE_AND_STEP(); + destval = not_long(destval); + store_data_long(destoffset, destval); + } else { + u16 destval; + + DECODE_PRINTF("NOT\tWORD PTR "); + destoffset = decode_rm01_address(rl); + DECODE_PRINTF("\n"); + destval = fetch_data_word(destoffset); + TRACE_AND_STEP(); + destval = not_word(destval); + store_data_word(destoffset, destval); + } + break; + case 3: + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 destval; + + DECODE_PRINTF("NEG\tDWORD PTR "); + destoffset = decode_rm01_address(rl); + DECODE_PRINTF("\n"); + destval = fetch_data_long(destoffset); + TRACE_AND_STEP(); + destval = neg_long(destval); + store_data_long(destoffset, destval); + } else { + u16 destval; + + DECODE_PRINTF("NEG\tWORD PTR "); + destoffset = decode_rm01_address(rl); + DECODE_PRINTF("\n"); + destval = fetch_data_word(destoffset); + TRACE_AND_STEP(); + destval = neg_word(destval); + store_data_word(destoffset, destval); + } + break; + case 4: + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 destval; + + DECODE_PRINTF("MUL\tDWORD PTR "); + destoffset = decode_rm01_address(rl); + DECODE_PRINTF("\n"); + destval = fetch_data_long(destoffset); + TRACE_AND_STEP(); + mul_long(destval); + } else { + u16 destval; + + DECODE_PRINTF("MUL\tWORD PTR "); + destoffset = decode_rm01_address(rl); + DECODE_PRINTF("\n"); + destval = fetch_data_word(destoffset); + TRACE_AND_STEP(); + mul_word(destval); + } + break; + case 5: + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 destval; + + DECODE_PRINTF("IMUL\tDWORD PTR "); + destoffset = decode_rm01_address(rl); + DECODE_PRINTF("\n"); + destval = fetch_data_long(destoffset); + TRACE_AND_STEP(); + imul_long(destval); + } else { + u16 destval; + + DECODE_PRINTF("IMUL\tWORD PTR "); + destoffset = decode_rm01_address(rl); + DECODE_PRINTF("\n"); + destval = fetch_data_word(destoffset); + TRACE_AND_STEP(); + imul_word(destval); + } + break; + case 6: + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 destval; + + DECODE_PRINTF("DIV\tDWORD PTR "); + destoffset = decode_rm01_address(rl); + DECODE_PRINTF("\n"); + destval = fetch_data_long(destoffset); + TRACE_AND_STEP(); + div_long(destval); + } else { + u16 destval; + + DECODE_PRINTF("DIV\tWORD PTR "); + destoffset = decode_rm01_address(rl); + DECODE_PRINTF("\n"); + destval = fetch_data_word(destoffset); + TRACE_AND_STEP(); + div_word(destval); + } + break; + case 7: + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 destval; + + DECODE_PRINTF("IDIV\tDWORD PTR "); + destoffset = decode_rm01_address(rl); + DECODE_PRINTF("\n"); + destval = fetch_data_long(destoffset); + TRACE_AND_STEP(); + idiv_long(destval); + } else { + u16 destval; + + DECODE_PRINTF("IDIV\tWORD PTR "); + destoffset = decode_rm01_address(rl); + DECODE_PRINTF("\n"); + destval = fetch_data_word(destoffset); + TRACE_AND_STEP(); + idiv_word(destval); + } + break; + } + break; /* end mod==01 */ + case 2: /* mod=10 */ + switch (rh) { + case 0: /* test word imm */ + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 destval,srcval; + + DECODE_PRINTF("TEST\tDWORD PTR "); + destoffset = decode_rm10_address(rl); + DECODE_PRINTF(","); + srcval = fetch_long_imm(); + DECODE_PRINTF2("%x\n", srcval); + destval = fetch_data_long(destoffset); + TRACE_AND_STEP(); + test_long(destval, srcval); + } else { + u16 destval,srcval; + + DECODE_PRINTF("TEST\tWORD PTR "); + destoffset = decode_rm10_address(rl); + DECODE_PRINTF(","); + srcval = fetch_word_imm(); + DECODE_PRINTF2("%x\n", srcval); + destval = fetch_data_word(destoffset); + TRACE_AND_STEP(); + test_word(destval, srcval); + } + break; + case 1: + DECODE_PRINTF("ILLEGAL OP MOD=10 RH=01 OP=F6\n"); + HALT_SYS(); + break; + case 2: + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 destval; + + DECODE_PRINTF("NOT\tDWORD PTR "); + destoffset = decode_rm10_address(rl); + DECODE_PRINTF("\n"); + destval = fetch_data_long(destoffset); + TRACE_AND_STEP(); + destval = not_long(destval); + store_data_long(destoffset, destval); + } else { + u16 destval; + + DECODE_PRINTF("NOT\tWORD PTR "); + destoffset = decode_rm10_address(rl); + DECODE_PRINTF("\n"); + destval = fetch_data_word(destoffset); + TRACE_AND_STEP(); + destval = not_word(destval); + store_data_word(destoffset, destval); + } + break; + case 3: + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 destval; + + DECODE_PRINTF("NEG\tDWORD PTR "); + destoffset = decode_rm10_address(rl); + DECODE_PRINTF("\n"); + destval = fetch_data_long(destoffset); + TRACE_AND_STEP(); + destval = neg_long(destval); + store_data_long(destoffset, destval); + } else { + u16 destval; + + DECODE_PRINTF("NEG\tWORD PTR "); + destoffset = decode_rm10_address(rl); + DECODE_PRINTF("\n"); + destval = fetch_data_word(destoffset); + TRACE_AND_STEP(); + destval = neg_word(destval); + store_data_word(destoffset, destval); + } + break; + case 4: + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 destval; + + DECODE_PRINTF("MUL\tDWORD PTR "); + destoffset = decode_rm10_address(rl); + DECODE_PRINTF("\n"); + destval = fetch_data_long(destoffset); + TRACE_AND_STEP(); + mul_long(destval); + } else { + u16 destval; + + DECODE_PRINTF("MUL\tWORD PTR "); + destoffset = decode_rm10_address(rl); + DECODE_PRINTF("\n"); + destval = fetch_data_word(destoffset); + TRACE_AND_STEP(); + mul_word(destval); + } + break; + case 5: + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 destval; + + DECODE_PRINTF("IMUL\tDWORD PTR "); + destoffset = decode_rm10_address(rl); + DECODE_PRINTF("\n"); + destval = fetch_data_long(destoffset); + TRACE_AND_STEP(); + imul_long(destval); + } else { + u16 destval; + + DECODE_PRINTF("IMUL\tWORD PTR "); + destoffset = decode_rm10_address(rl); + DECODE_PRINTF("\n"); + destval = fetch_data_word(destoffset); + TRACE_AND_STEP(); + imul_word(destval); + } + break; + case 6: + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 destval; + + DECODE_PRINTF("DIV\tDWORD PTR "); + destoffset = decode_rm10_address(rl); + DECODE_PRINTF("\n"); + destval = fetch_data_long(destoffset); + TRACE_AND_STEP(); + div_long(destval); + } else { + u16 destval; + + DECODE_PRINTF("DIV\tWORD PTR "); + destoffset = decode_rm10_address(rl); + DECODE_PRINTF("\n"); + destval = fetch_data_word(destoffset); + TRACE_AND_STEP(); + div_word(destval); + } + break; + case 7: + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 destval; + + DECODE_PRINTF("IDIV\tDWORD PTR "); + destoffset = decode_rm10_address(rl); + DECODE_PRINTF("\n"); + destval = fetch_data_long(destoffset); + TRACE_AND_STEP(); + idiv_long(destval); + } else { + u16 destval; + + DECODE_PRINTF("IDIV\tWORD PTR "); + destoffset = decode_rm10_address(rl); + DECODE_PRINTF("\n"); + destval = fetch_data_word(destoffset); + TRACE_AND_STEP(); + idiv_word(destval); + } + break; + } + break; /* end mod==10 */ + case 3: /* mod=11 */ + switch (rh) { + case 0: /* test word imm */ + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 *destreg; + u32 srcval; + + DECODE_PRINTF("TEST\t"); + destreg = DECODE_RM_LONG_REGISTER(rl); + DECODE_PRINTF(","); + srcval = fetch_long_imm(); + DECODE_PRINTF2("%x\n", srcval); + TRACE_AND_STEP(); + test_long(*destreg, srcval); + } else { + u16 *destreg; + u16 srcval; + + DECODE_PRINTF("TEST\t"); + destreg = DECODE_RM_WORD_REGISTER(rl); + DECODE_PRINTF(","); + srcval = fetch_word_imm(); + DECODE_PRINTF2("%x\n", srcval); + TRACE_AND_STEP(); + test_word(*destreg, srcval); + } + break; + case 1: + DECODE_PRINTF("ILLEGAL OP MOD=00 RH=01 OP=F6\n"); + HALT_SYS(); + break; + case 2: + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 *destreg; + + DECODE_PRINTF("NOT\t"); + destreg = DECODE_RM_LONG_REGISTER(rl); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = not_long(*destreg); + } else { + u16 *destreg; + + DECODE_PRINTF("NOT\t"); + destreg = DECODE_RM_WORD_REGISTER(rl); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = not_word(*destreg); + } + break; + case 3: + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 *destreg; + + DECODE_PRINTF("NEG\t"); + destreg = DECODE_RM_LONG_REGISTER(rl); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = neg_long(*destreg); + } else { + u16 *destreg; + + DECODE_PRINTF("NEG\t"); + destreg = DECODE_RM_WORD_REGISTER(rl); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = neg_word(*destreg); + } + break; + case 4: + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 *destreg; + + DECODE_PRINTF("MUL\t"); + destreg = DECODE_RM_LONG_REGISTER(rl); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + mul_long(*destreg); /*!!! */ + } else { + u16 *destreg; + + DECODE_PRINTF("MUL\t"); + destreg = DECODE_RM_WORD_REGISTER(rl); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + mul_word(*destreg); /*!!! */ + } + break; + case 5: + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 *destreg; + + DECODE_PRINTF("IMUL\t"); + destreg = DECODE_RM_LONG_REGISTER(rl); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + imul_long(*destreg); + } else { + u16 *destreg; + + DECODE_PRINTF("IMUL\t"); + destreg = DECODE_RM_WORD_REGISTER(rl); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + imul_word(*destreg); + } + break; + case 6: + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 *destreg; + + DECODE_PRINTF("DIV\t"); + destreg = DECODE_RM_LONG_REGISTER(rl); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + div_long(*destreg); + } else { + u16 *destreg; + + DECODE_PRINTF("DIV\t"); + destreg = DECODE_RM_WORD_REGISTER(rl); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + div_word(*destreg); + } + break; + case 7: + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 *destreg; + + DECODE_PRINTF("IDIV\t"); + destreg = DECODE_RM_LONG_REGISTER(rl); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + idiv_long(*destreg); + } else { + u16 *destreg; + + DECODE_PRINTF("IDIV\t"); + destreg = DECODE_RM_WORD_REGISTER(rl); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + idiv_word(*destreg); + } + break; + } + break; /* end mod==11 */ + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0xf8 +****************************************************************************/ +static void x86emuOp_clc(u8 X86EMU_UNUSED(op1)) +{ + /* clear the carry flag. */ + START_OF_INSTR(); + DECODE_PRINTF("CLC\n"); + TRACE_AND_STEP(); + CLEAR_FLAG(F_CF); + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0xf9 +****************************************************************************/ +static void x86emuOp_stc(u8 X86EMU_UNUSED(op1)) +{ + /* set the carry flag. */ + START_OF_INSTR(); + DECODE_PRINTF("STC\n"); + TRACE_AND_STEP(); + SET_FLAG(F_CF); + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0xfa +****************************************************************************/ +static void x86emuOp_cli(u8 X86EMU_UNUSED(op1)) +{ + /* clear interrupts. */ + START_OF_INSTR(); + DECODE_PRINTF("CLI\n"); + TRACE_AND_STEP(); + CLEAR_FLAG(F_IF); + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0xfb +****************************************************************************/ +static void x86emuOp_sti(u8 X86EMU_UNUSED(op1)) +{ + /* enable interrupts. */ + START_OF_INSTR(); + DECODE_PRINTF("STI\n"); + TRACE_AND_STEP(); + SET_FLAG(F_IF); + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0xfc +****************************************************************************/ +static void x86emuOp_cld(u8 X86EMU_UNUSED(op1)) +{ + /* clear interrupts. */ + START_OF_INSTR(); + DECODE_PRINTF("CLD\n"); + TRACE_AND_STEP(); + CLEAR_FLAG(F_DF); + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0xfd +****************************************************************************/ +static void x86emuOp_std(u8 X86EMU_UNUSED(op1)) +{ + /* clear interrupts. */ + START_OF_INSTR(); + DECODE_PRINTF("STD\n"); + TRACE_AND_STEP(); + SET_FLAG(F_DF); + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0xfe +****************************************************************************/ +static void x86emuOp_opcFE_byte_RM(u8 X86EMU_UNUSED(op1)) +{ + int mod, rh, rl; + u8 destval; + uint destoffset; + u8 *destreg; + + /* Yet another special case instruction. */ + START_OF_INSTR(); + FETCH_DECODE_MODRM(mod, rh, rl); +#ifdef X86EMU_DEBUG + if (DEBUG_DECODE()) { + /* XXX DECODE_PRINTF may be changed to something more + general, so that it is important to leave the strings + in the same format, even though the result is that the + above test is done twice. */ + + switch (rh) { + case 0: + DECODE_PRINTF("INC\t"); + break; + case 1: + DECODE_PRINTF("DEC\t"); + break; + case 2: + case 3: + case 4: + case 5: + case 6: + case 7: + DECODE_PRINTF2("ILLEGAL OP MAJOR OP 0xFE MINOR OP %x \n", mod); + HALT_SYS(); + break; + } + } +#endif + switch (mod) { + case 0: + DECODE_PRINTF("BYTE PTR "); + destoffset = decode_rm00_address(rl); + DECODE_PRINTF("\n"); + switch (rh) { + case 0: /* inc word ptr ... */ + destval = fetch_data_byte(destoffset); + TRACE_AND_STEP(); + destval = inc_byte(destval); + store_data_byte(destoffset, destval); + break; + case 1: /* dec word ptr ... */ + destval = fetch_data_byte(destoffset); + TRACE_AND_STEP(); + destval = dec_byte(destval); + store_data_byte(destoffset, destval); + break; + } + break; + case 1: + DECODE_PRINTF("BYTE PTR "); + destoffset = decode_rm01_address(rl); + DECODE_PRINTF("\n"); + switch (rh) { + case 0: + destval = fetch_data_byte(destoffset); + TRACE_AND_STEP(); + destval = inc_byte(destval); + store_data_byte(destoffset, destval); + break; + case 1: + destval = fetch_data_byte(destoffset); + TRACE_AND_STEP(); + destval = dec_byte(destval); + store_data_byte(destoffset, destval); + break; + } + break; + case 2: + DECODE_PRINTF("BYTE PTR "); + destoffset = decode_rm10_address(rl); + DECODE_PRINTF("\n"); + switch (rh) { + case 0: + destval = fetch_data_byte(destoffset); + TRACE_AND_STEP(); + destval = inc_byte(destval); + store_data_byte(destoffset, destval); + break; + case 1: + destval = fetch_data_byte(destoffset); + TRACE_AND_STEP(); + destval = dec_byte(destval); + store_data_byte(destoffset, destval); + break; + } + break; + case 3: + destreg = DECODE_RM_BYTE_REGISTER(rl); + DECODE_PRINTF("\n"); + switch (rh) { + case 0: + TRACE_AND_STEP(); + *destreg = inc_byte(*destreg); + break; + case 1: + TRACE_AND_STEP(); + *destreg = dec_byte(*destreg); + break; + } + break; + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0xff +****************************************************************************/ +static void x86emuOp_opcFF_word_RM(u8 X86EMU_UNUSED(op1)) +{ + int mod, rh, rl; + uint destoffset = 0; + u16 *destreg; + u16 destval,destval2; + + /* Yet another special case instruction. */ + START_OF_INSTR(); + FETCH_DECODE_MODRM(mod, rh, rl); +#ifdef X86EMU_DEBUG + if (DEBUG_DECODE()) { + /* XXX DECODE_PRINTF may be changed to something more + general, so that it is important to leave the strings + in the same format, even though the result is that the + above test is done twice. */ + + switch (rh) { + case 0: + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + DECODE_PRINTF("INC\tDWORD PTR "); + } else { + DECODE_PRINTF("INC\tWORD PTR "); + } + break; + case 1: + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + DECODE_PRINTF("DEC\tDWORD PTR "); + } else { + DECODE_PRINTF("DEC\tWORD PTR "); + } + break; + case 2: + DECODE_PRINTF("CALL\t"); + break; + case 3: + DECODE_PRINTF("CALL\tFAR "); + break; + case 4: + DECODE_PRINTF("JMP\t"); + break; + case 5: + DECODE_PRINTF("JMP\tFAR "); + break; + case 6: + DECODE_PRINTF("PUSH\t"); + break; + case 7: + DECODE_PRINTF("ILLEGAL DECODING OF OPCODE FF\t"); + HALT_SYS(); + break; + } + } +#endif + switch (mod) { + case 0: + destoffset = decode_rm00_address(rl); + DECODE_PRINTF("\n"); + switch (rh) { + case 0: /* inc word ptr ... */ + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 destval; + + destval = fetch_data_long(destoffset); + TRACE_AND_STEP(); + destval = inc_long(destval); + store_data_long(destoffset, destval); + } else { + u16 destval; + + destval = fetch_data_word(destoffset); + TRACE_AND_STEP(); + destval = inc_word(destval); + store_data_word(destoffset, destval); + } + break; + case 1: /* dec word ptr ... */ + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 destval; + + destval = fetch_data_long(destoffset); + TRACE_AND_STEP(); + destval = dec_long(destval); + store_data_long(destoffset, destval); + } else { + u16 destval; + + destval = fetch_data_word(destoffset); + TRACE_AND_STEP(); + destval = dec_word(destval); + store_data_word(destoffset, destval); + } + break; + case 2: /* call word ptr ... */ + destval = fetch_data_word(destoffset); + TRACE_AND_STEP(); + push_word(M.x86.R_IP); + M.x86.R_IP = destval; + break; + case 3: /* call far ptr ... */ + destval = fetch_data_word(destoffset); + destval2 = fetch_data_word(destoffset + 2); + TRACE_AND_STEP(); + push_word(M.x86.R_CS); + M.x86.R_CS = destval2; + push_word(M.x86.R_IP); + M.x86.R_IP = destval; + break; + case 4: /* jmp word ptr ... */ + destval = fetch_data_word(destoffset); + TRACE_AND_STEP(); + M.x86.R_IP = destval; + break; + case 5: /* jmp far ptr ... */ + destval = fetch_data_word(destoffset); + destval2 = fetch_data_word(destoffset + 2); + TRACE_AND_STEP(); + M.x86.R_IP = destval; + M.x86.R_CS = destval2; + break; + case 6: /* push word ptr ... */ + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 destval; + + destval = fetch_data_long(destoffset); + TRACE_AND_STEP(); + push_long(destval); + } else { + u16 destval; + + destval = fetch_data_word(destoffset); + TRACE_AND_STEP(); + push_word(destval); + } + break; + } + break; + case 1: + destoffset = decode_rm01_address(rl); + DECODE_PRINTF("\n"); + switch (rh) { + case 0: + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 destval; + + destval = fetch_data_long(destoffset); + TRACE_AND_STEP(); + destval = inc_long(destval); + store_data_long(destoffset, destval); + } else { + u16 destval; + + destval = fetch_data_word(destoffset); + TRACE_AND_STEP(); + destval = inc_word(destval); + store_data_word(destoffset, destval); + } + break; + case 1: + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 destval; + + destval = fetch_data_long(destoffset); + TRACE_AND_STEP(); + destval = dec_long(destval); + store_data_long(destoffset, destval); + } else { + u16 destval; + + destval = fetch_data_word(destoffset); + TRACE_AND_STEP(); + destval = dec_word(destval); + store_data_word(destoffset, destval); + } + break; + case 2: /* call word ptr ... */ + destval = fetch_data_word(destoffset); + TRACE_AND_STEP(); + push_word(M.x86.R_IP); + M.x86.R_IP = destval; + break; + case 3: /* call far ptr ... */ + destval = fetch_data_word(destoffset); + destval2 = fetch_data_word(destoffset + 2); + TRACE_AND_STEP(); + push_word(M.x86.R_CS); + M.x86.R_CS = destval2; + push_word(M.x86.R_IP); + M.x86.R_IP = destval; + break; + case 4: /* jmp word ptr ... */ + destval = fetch_data_word(destoffset); + TRACE_AND_STEP(); + M.x86.R_IP = destval; + break; + case 5: /* jmp far ptr ... */ + destval = fetch_data_word(destoffset); + destval2 = fetch_data_word(destoffset + 2); + TRACE_AND_STEP(); + M.x86.R_IP = destval; + M.x86.R_CS = destval2; + break; + case 6: /* push word ptr ... */ + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 destval; + + destval = fetch_data_long(destoffset); + TRACE_AND_STEP(); + push_long(destval); + } else { + u16 destval; + + destval = fetch_data_word(destoffset); + TRACE_AND_STEP(); + push_word(destval); + } + break; + } + break; + case 2: + destoffset = decode_rm10_address(rl); + DECODE_PRINTF("\n"); + switch (rh) { + case 0: + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 destval; + + destval = fetch_data_long(destoffset); + TRACE_AND_STEP(); + destval = inc_long(destval); + store_data_long(destoffset, destval); + } else { + u16 destval; + + destval = fetch_data_word(destoffset); + TRACE_AND_STEP(); + destval = inc_word(destval); + store_data_word(destoffset, destval); + } + break; + case 1: + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 destval; + + destval = fetch_data_long(destoffset); + TRACE_AND_STEP(); + destval = dec_long(destval); + store_data_long(destoffset, destval); + } else { + u16 destval; + + destval = fetch_data_word(destoffset); + TRACE_AND_STEP(); + destval = dec_word(destval); + store_data_word(destoffset, destval); + } + break; + case 2: /* call word ptr ... */ + destval = fetch_data_word(destoffset); + TRACE_AND_STEP(); + push_word(M.x86.R_IP); + M.x86.R_IP = destval; + break; + case 3: /* call far ptr ... */ + destval = fetch_data_word(destoffset); + destval2 = fetch_data_word(destoffset + 2); + TRACE_AND_STEP(); + push_word(M.x86.R_CS); + M.x86.R_CS = destval2; + push_word(M.x86.R_IP); + M.x86.R_IP = destval; + break; + case 4: /* jmp word ptr ... */ + destval = fetch_data_word(destoffset); + TRACE_AND_STEP(); + M.x86.R_IP = destval; + break; + case 5: /* jmp far ptr ... */ + destval = fetch_data_word(destoffset); + destval2 = fetch_data_word(destoffset + 2); + TRACE_AND_STEP(); + M.x86.R_IP = destval; + M.x86.R_CS = destval2; + break; + case 6: /* push word ptr ... */ + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 destval; + + destval = fetch_data_long(destoffset); + TRACE_AND_STEP(); + push_long(destval); + } else { + u16 destval; + + destval = fetch_data_word(destoffset); + TRACE_AND_STEP(); + push_word(destval); + } + break; + } + break; + case 3: + switch (rh) { + case 0: + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 *destreg; + + destreg = DECODE_RM_LONG_REGISTER(rl); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = inc_long(*destreg); + } else { + u16 *destreg; + + destreg = DECODE_RM_WORD_REGISTER(rl); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = inc_word(*destreg); + } + break; + case 1: + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 *destreg; + + destreg = DECODE_RM_LONG_REGISTER(rl); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = dec_long(*destreg); + } else { + u16 *destreg; + + destreg = DECODE_RM_WORD_REGISTER(rl); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = dec_word(*destreg); + } + break; + case 2: /* call word ptr ... */ + destreg = DECODE_RM_WORD_REGISTER(rl); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + push_word(M.x86.R_IP); + M.x86.R_IP = *destreg; + break; + case 3: /* jmp far ptr ... */ + DECODE_PRINTF("OPERATION UNDEFINED 0XFF \n"); + TRACE_AND_STEP(); + HALT_SYS(); + break; + + case 4: /* jmp ... */ + destreg = DECODE_RM_WORD_REGISTER(rl); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + M.x86.R_IP = (u16) (*destreg); + break; + case 5: /* jmp far ptr ... */ + DECODE_PRINTF("OPERATION UNDEFINED 0XFF \n"); + TRACE_AND_STEP(); + HALT_SYS(); + break; + case 6: + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 *destreg; + + destreg = DECODE_RM_LONG_REGISTER(rl); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + push_long(*destreg); + } else { + u16 *destreg; + + destreg = DECODE_RM_WORD_REGISTER(rl); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + push_word(*destreg); + } + break; + case 7: + DECODE_PRINTF("OPERATION UNDEFINED 0XFF \n"); + TRACE_AND_STEP(); + HALT_SYS(); + break; + } + break; + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/*************************************************************************** + * Single byte operation code table: + **************************************************************************/ +void (*x86emu_optab[256])(u8) = +{ +/* 0x00 */ x86emuOp_add_byte_RM_R, +/* 0x01 */ x86emuOp_add_word_RM_R, +/* 0x02 */ x86emuOp_add_byte_R_RM, +/* 0x03 */ x86emuOp_add_word_R_RM, +/* 0x04 */ x86emuOp_add_byte_AL_IMM, +/* 0x05 */ x86emuOp_add_word_AX_IMM, +/* 0x06 */ x86emuOp_push_ES, +/* 0x07 */ x86emuOp_pop_ES, + +/* 0x08 */ x86emuOp_or_byte_RM_R, +/* 0x09 */ x86emuOp_or_word_RM_R, +/* 0x0a */ x86emuOp_or_byte_R_RM, +/* 0x0b */ x86emuOp_or_word_R_RM, +/* 0x0c */ x86emuOp_or_byte_AL_IMM, +/* 0x0d */ x86emuOp_or_word_AX_IMM, +/* 0x0e */ x86emuOp_push_CS, +/* 0x0f */ x86emuOp_two_byte, + +/* 0x10 */ x86emuOp_adc_byte_RM_R, +/* 0x11 */ x86emuOp_adc_word_RM_R, +/* 0x12 */ x86emuOp_adc_byte_R_RM, +/* 0x13 */ x86emuOp_adc_word_R_RM, +/* 0x14 */ x86emuOp_adc_byte_AL_IMM, +/* 0x15 */ x86emuOp_adc_word_AX_IMM, +/* 0x16 */ x86emuOp_push_SS, +/* 0x17 */ x86emuOp_pop_SS, + +/* 0x18 */ x86emuOp_sbb_byte_RM_R, +/* 0x19 */ x86emuOp_sbb_word_RM_R, +/* 0x1a */ x86emuOp_sbb_byte_R_RM, +/* 0x1b */ x86emuOp_sbb_word_R_RM, +/* 0x1c */ x86emuOp_sbb_byte_AL_IMM, +/* 0x1d */ x86emuOp_sbb_word_AX_IMM, +/* 0x1e */ x86emuOp_push_DS, +/* 0x1f */ x86emuOp_pop_DS, + +/* 0x20 */ x86emuOp_and_byte_RM_R, +/* 0x21 */ x86emuOp_and_word_RM_R, +/* 0x22 */ x86emuOp_and_byte_R_RM, +/* 0x23 */ x86emuOp_and_word_R_RM, +/* 0x24 */ x86emuOp_and_byte_AL_IMM, +/* 0x25 */ x86emuOp_and_word_AX_IMM, +/* 0x26 */ x86emuOp_segovr_ES, +/* 0x27 */ x86emuOp_daa, + +/* 0x28 */ x86emuOp_sub_byte_RM_R, +/* 0x29 */ x86emuOp_sub_word_RM_R, +/* 0x2a */ x86emuOp_sub_byte_R_RM, +/* 0x2b */ x86emuOp_sub_word_R_RM, +/* 0x2c */ x86emuOp_sub_byte_AL_IMM, +/* 0x2d */ x86emuOp_sub_word_AX_IMM, +/* 0x2e */ x86emuOp_segovr_CS, +/* 0x2f */ x86emuOp_das, + +/* 0x30 */ x86emuOp_xor_byte_RM_R, +/* 0x31 */ x86emuOp_xor_word_RM_R, +/* 0x32 */ x86emuOp_xor_byte_R_RM, +/* 0x33 */ x86emuOp_xor_word_R_RM, +/* 0x34 */ x86emuOp_xor_byte_AL_IMM, +/* 0x35 */ x86emuOp_xor_word_AX_IMM, +/* 0x36 */ x86emuOp_segovr_SS, +/* 0x37 */ x86emuOp_aaa, + +/* 0x38 */ x86emuOp_cmp_byte_RM_R, +/* 0x39 */ x86emuOp_cmp_word_RM_R, +/* 0x3a */ x86emuOp_cmp_byte_R_RM, +/* 0x3b */ x86emuOp_cmp_word_R_RM, +/* 0x3c */ x86emuOp_cmp_byte_AL_IMM, +/* 0x3d */ x86emuOp_cmp_word_AX_IMM, +/* 0x3e */ x86emuOp_segovr_DS, +/* 0x3f */ x86emuOp_aas, + +/* 0x40 */ x86emuOp_inc_AX, +/* 0x41 */ x86emuOp_inc_CX, +/* 0x42 */ x86emuOp_inc_DX, +/* 0x43 */ x86emuOp_inc_BX, +/* 0x44 */ x86emuOp_inc_SP, +/* 0x45 */ x86emuOp_inc_BP, +/* 0x46 */ x86emuOp_inc_SI, +/* 0x47 */ x86emuOp_inc_DI, + +/* 0x48 */ x86emuOp_dec_AX, +/* 0x49 */ x86emuOp_dec_CX, +/* 0x4a */ x86emuOp_dec_DX, +/* 0x4b */ x86emuOp_dec_BX, +/* 0x4c */ x86emuOp_dec_SP, +/* 0x4d */ x86emuOp_dec_BP, +/* 0x4e */ x86emuOp_dec_SI, +/* 0x4f */ x86emuOp_dec_DI, + +/* 0x50 */ x86emuOp_push_AX, +/* 0x51 */ x86emuOp_push_CX, +/* 0x52 */ x86emuOp_push_DX, +/* 0x53 */ x86emuOp_push_BX, +/* 0x54 */ x86emuOp_push_SP, +/* 0x55 */ x86emuOp_push_BP, +/* 0x56 */ x86emuOp_push_SI, +/* 0x57 */ x86emuOp_push_DI, + +/* 0x58 */ x86emuOp_pop_AX, +/* 0x59 */ x86emuOp_pop_CX, +/* 0x5a */ x86emuOp_pop_DX, +/* 0x5b */ x86emuOp_pop_BX, +/* 0x5c */ x86emuOp_pop_SP, +/* 0x5d */ x86emuOp_pop_BP, +/* 0x5e */ x86emuOp_pop_SI, +/* 0x5f */ x86emuOp_pop_DI, + +/* 0x60 */ x86emuOp_push_all, +/* 0x61 */ x86emuOp_pop_all, +/* 0x62 */ x86emuOp_illegal_op, /* bound */ +/* 0x63 */ x86emuOp_illegal_op, /* arpl */ +/* 0x64 */ x86emuOp_segovr_FS, +/* 0x65 */ x86emuOp_segovr_GS, +/* 0x66 */ x86emuOp_prefix_data, +/* 0x67 */ x86emuOp_prefix_addr, + +/* 0x68 */ x86emuOp_push_word_IMM, +/* 0x69 */ x86emuOp_imul_word_IMM, +/* 0x6a */ x86emuOp_push_byte_IMM, +/* 0x6b */ x86emuOp_imul_byte_IMM, +/* 0x6c */ x86emuOp_ins_byte, +/* 0x6d */ x86emuOp_ins_word, +/* 0x6e */ x86emuOp_outs_byte, +/* 0x6f */ x86emuOp_outs_word, + +/* 0x70 */ x86emuOp_jump_near_O, +/* 0x71 */ x86emuOp_jump_near_NO, +/* 0x72 */ x86emuOp_jump_near_B, +/* 0x73 */ x86emuOp_jump_near_NB, +/* 0x74 */ x86emuOp_jump_near_Z, +/* 0x75 */ x86emuOp_jump_near_NZ, +/* 0x76 */ x86emuOp_jump_near_BE, +/* 0x77 */ x86emuOp_jump_near_NBE, + +/* 0x78 */ x86emuOp_jump_near_S, +/* 0x79 */ x86emuOp_jump_near_NS, +/* 0x7a */ x86emuOp_jump_near_P, +/* 0x7b */ x86emuOp_jump_near_NP, +/* 0x7c */ x86emuOp_jump_near_L, +/* 0x7d */ x86emuOp_jump_near_NL, +/* 0x7e */ x86emuOp_jump_near_LE, +/* 0x7f */ x86emuOp_jump_near_NLE, + +/* 0x80 */ x86emuOp_opc80_byte_RM_IMM, +/* 0x81 */ x86emuOp_opc81_word_RM_IMM, +/* 0x82 */ x86emuOp_opc82_byte_RM_IMM, +/* 0x83 */ x86emuOp_opc83_word_RM_IMM, +/* 0x84 */ x86emuOp_test_byte_RM_R, +/* 0x85 */ x86emuOp_test_word_RM_R, +/* 0x86 */ x86emuOp_xchg_byte_RM_R, +/* 0x87 */ x86emuOp_xchg_word_RM_R, + +/* 0x88 */ x86emuOp_mov_byte_RM_R, +/* 0x89 */ x86emuOp_mov_word_RM_R, +/* 0x8a */ x86emuOp_mov_byte_R_RM, +/* 0x8b */ x86emuOp_mov_word_R_RM, +/* 0x8c */ x86emuOp_mov_word_RM_SR, +/* 0x8d */ x86emuOp_lea_word_R_M, +/* 0x8e */ x86emuOp_mov_word_SR_RM, +/* 0x8f */ x86emuOp_pop_RM, + +/* 0x90 */ x86emuOp_nop, +/* 0x91 */ x86emuOp_xchg_word_AX_CX, +/* 0x92 */ x86emuOp_xchg_word_AX_DX, +/* 0x93 */ x86emuOp_xchg_word_AX_BX, +/* 0x94 */ x86emuOp_xchg_word_AX_SP, +/* 0x95 */ x86emuOp_xchg_word_AX_BP, +/* 0x96 */ x86emuOp_xchg_word_AX_SI, +/* 0x97 */ x86emuOp_xchg_word_AX_DI, + +/* 0x98 */ x86emuOp_cbw, +/* 0x99 */ x86emuOp_cwd, +/* 0x9a */ x86emuOp_call_far_IMM, +/* 0x9b */ x86emuOp_wait, +/* 0x9c */ x86emuOp_pushf_word, +/* 0x9d */ x86emuOp_popf_word, +/* 0x9e */ x86emuOp_sahf, +/* 0x9f */ x86emuOp_lahf, + +/* 0xa0 */ x86emuOp_mov_AL_M_IMM, +/* 0xa1 */ x86emuOp_mov_AX_M_IMM, +/* 0xa2 */ x86emuOp_mov_M_AL_IMM, +/* 0xa3 */ x86emuOp_mov_M_AX_IMM, +/* 0xa4 */ x86emuOp_movs_byte, +/* 0xa5 */ x86emuOp_movs_word, +/* 0xa6 */ x86emuOp_cmps_byte, +/* 0xa7 */ x86emuOp_cmps_word, +/* 0xa8 */ x86emuOp_test_AL_IMM, +/* 0xa9 */ x86emuOp_test_AX_IMM, +/* 0xaa */ x86emuOp_stos_byte, +/* 0xab */ x86emuOp_stos_word, +/* 0xac */ x86emuOp_lods_byte, +/* 0xad */ x86emuOp_lods_word, +/* 0xac */ x86emuOp_scas_byte, +/* 0xad */ x86emuOp_scas_word, + + +/* 0xb0 */ x86emuOp_mov_byte_AL_IMM, +/* 0xb1 */ x86emuOp_mov_byte_CL_IMM, +/* 0xb2 */ x86emuOp_mov_byte_DL_IMM, +/* 0xb3 */ x86emuOp_mov_byte_BL_IMM, +/* 0xb4 */ x86emuOp_mov_byte_AH_IMM, +/* 0xb5 */ x86emuOp_mov_byte_CH_IMM, +/* 0xb6 */ x86emuOp_mov_byte_DH_IMM, +/* 0xb7 */ x86emuOp_mov_byte_BH_IMM, + +/* 0xb8 */ x86emuOp_mov_word_AX_IMM, +/* 0xb9 */ x86emuOp_mov_word_CX_IMM, +/* 0xba */ x86emuOp_mov_word_DX_IMM, +/* 0xbb */ x86emuOp_mov_word_BX_IMM, +/* 0xbc */ x86emuOp_mov_word_SP_IMM, +/* 0xbd */ x86emuOp_mov_word_BP_IMM, +/* 0xbe */ x86emuOp_mov_word_SI_IMM, +/* 0xbf */ x86emuOp_mov_word_DI_IMM, + +/* 0xc0 */ x86emuOp_opcC0_byte_RM_MEM, +/* 0xc1 */ x86emuOp_opcC1_word_RM_MEM, +/* 0xc2 */ x86emuOp_ret_near_IMM, +/* 0xc3 */ x86emuOp_ret_near, +/* 0xc4 */ x86emuOp_les_R_IMM, +/* 0xc5 */ x86emuOp_lds_R_IMM, +/* 0xc6 */ x86emuOp_mov_byte_RM_IMM, +/* 0xc7 */ x86emuOp_mov_word_RM_IMM, +/* 0xc8 */ x86emuOp_enter, +/* 0xc9 */ x86emuOp_leave, +/* 0xca */ x86emuOp_ret_far_IMM, +/* 0xcb */ x86emuOp_ret_far, +/* 0xcc */ x86emuOp_int3, +/* 0xcd */ x86emuOp_int_IMM, +/* 0xce */ x86emuOp_into, +/* 0xcf */ x86emuOp_iret, + +/* 0xd0 */ x86emuOp_opcD0_byte_RM_1, +/* 0xd1 */ x86emuOp_opcD1_word_RM_1, +/* 0xd2 */ x86emuOp_opcD2_byte_RM_CL, +/* 0xd3 */ x86emuOp_opcD3_word_RM_CL, +/* 0xd4 */ x86emuOp_aam, +/* 0xd5 */ x86emuOp_aad, +/* 0xd6 */ x86emuOp_illegal_op, /* Undocumented SETALC instruction */ +/* 0xd7 */ x86emuOp_xlat, +/* 0xd8 */ x86emuOp_esc_coprocess_d8, +/* 0xd9 */ x86emuOp_esc_coprocess_d9, +/* 0xda */ x86emuOp_esc_coprocess_da, +/* 0xdb */ x86emuOp_esc_coprocess_db, +/* 0xdc */ x86emuOp_esc_coprocess_dc, +/* 0xdd */ x86emuOp_esc_coprocess_dd, +/* 0xde */ x86emuOp_esc_coprocess_de, +/* 0xdf */ x86emuOp_esc_coprocess_df, + +/* 0xe0 */ x86emuOp_loopne, +/* 0xe1 */ x86emuOp_loope, +/* 0xe2 */ x86emuOp_loop, +/* 0xe3 */ x86emuOp_jcxz, +/* 0xe4 */ x86emuOp_in_byte_AL_IMM, +/* 0xe5 */ x86emuOp_in_word_AX_IMM, +/* 0xe6 */ x86emuOp_out_byte_IMM_AL, +/* 0xe7 */ x86emuOp_out_word_IMM_AX, + +/* 0xe8 */ x86emuOp_call_near_IMM, +/* 0xe9 */ x86emuOp_jump_near_IMM, +/* 0xea */ x86emuOp_jump_far_IMM, +/* 0xeb */ x86emuOp_jump_byte_IMM, +/* 0xec */ x86emuOp_in_byte_AL_DX, +/* 0xed */ x86emuOp_in_word_AX_DX, +/* 0xee */ x86emuOp_out_byte_DX_AL, +/* 0xef */ x86emuOp_out_word_DX_AX, + +/* 0xf0 */ x86emuOp_lock, +/* 0xf1 */ x86emuOp_illegal_op, +/* 0xf2 */ x86emuOp_repne, +/* 0xf3 */ x86emuOp_repe, +/* 0xf4 */ x86emuOp_halt, +/* 0xf5 */ x86emuOp_cmc, +/* 0xf6 */ x86emuOp_opcF6_byte_RM, +/* 0xf7 */ x86emuOp_opcF7_word_RM, + +/* 0xf8 */ x86emuOp_clc, +/* 0xf9 */ x86emuOp_stc, +/* 0xfa */ x86emuOp_cli, +/* 0xfb */ x86emuOp_sti, +/* 0xfc */ x86emuOp_cld, +/* 0xfd */ x86emuOp_std, +/* 0xfe */ x86emuOp_opcFE_byte_RM, +/* 0xff */ x86emuOp_opcFF_word_RM, +}; diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/arch/nvalloc/unix/x86emu/ops2.c nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/arch/nvalloc/unix/x86emu/ops2.c --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/arch/nvalloc/unix/x86emu/ops2.c 1970-01-01 00:00:00.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/arch/nvalloc/unix/x86emu/ops2.c 2024-03-05 22:12:51.000000000 +0000 @@ -0,0 +1,2877 @@ +/**************************************************************************** +* +* Realmode X86 Emulator Library +* +* Copyright (C) 1996-1999 SciTech Software, Inc. +* Copyright (C) David Mosberger-Tang +* Copyright (C) 1999 Egbert Eich +* +* ======================================================================== +* +* Permission to use, copy, modify, distribute, and sell this software and +* its documentation for any purpose is hereby granted without fee, +* provided that the above copyright notice appear in all copies and that +* both that copyright notice and this permission notice appear in +* supporting documentation, and that the name of the authors not be used +* in advertising or publicity pertaining to distribution of the software +* without specific, written prior permission. The authors makes no +* representations about the suitability of this software for any purpose. +* It is provided "as is" without express or implied warranty. +* +* THE AUTHORS DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOFTWARE, +* INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO +* EVENT SHALL THE AUTHORS BE LIABLE FOR ANY SPECIAL, INDIRECT OR +* CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF +* USE, DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR +* OTHER TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR +* PERFORMANCE OF THIS SOFTWARE. +* +* ======================================================================== +* +* Language: ANSI C +* Environment: Any +* Developer: Kendall Bennett +* +* Description: This file includes subroutines to implement the decoding +* and emulation of all the x86 extended two-byte processor +* instructions. +* +****************************************************************************/ + +#include "x86emu/x86emui.h" + +/*----------------------------- Implementation ----------------------------*/ + +/**************************************************************************** +PARAMETERS: +op1 - Instruction op code + +REMARKS: +Handles illegal opcodes. +****************************************************************************/ +static void x86emuOp2_illegal_op( + u8 op2) +{ + START_OF_INSTR(); + DECODE_PRINTF("ILLEGAL EXTENDED X86 OPCODE\n"); + TRACE_REGS(); +DB( NV_PRINTF(LEVEL_INFO, + "%04x:%04x: %02X ILLEGAL EXTENDED X86 OPCODE!\n", + M.x86.R_CS, M.x86.R_IP - 2, op2);) + HALT_SYS(); + END_OF_INSTR(); +} + +#define xorl(a,b) ((a) && !(b)) || (!(a) && (b)) + +/**************************************************************************** +REMARKS: +Handles opcode 0x0f,0x80-0x8F +****************************************************************************/ +static void x86emuOp2_long_jump(u8 op2) +{ + s32 target; + const char *name = 0; + int cond = 0; + + /* conditional jump to word offset. */ + START_OF_INSTR(); + switch (op2) { + case 0x80: + name = "JO\t"; + cond = ACCESS_FLAG(F_OF); + break; + case 0x81: + name = "JNO\t"; + cond = !ACCESS_FLAG(F_OF); + break; + case 0x82: + name = "JB\t"; + cond = ACCESS_FLAG(F_CF); + break; + case 0x83: + name = "JNB\t"; + cond = !ACCESS_FLAG(F_CF); + break; + case 0x84: + name = "JZ\t"; + cond = ACCESS_FLAG(F_ZF); + break; + case 0x85: + name = "JNZ\t"; + cond = !ACCESS_FLAG(F_ZF); + break; + case 0x86: + name = "JBE\t"; + cond = ACCESS_FLAG(F_CF) || ACCESS_FLAG(F_ZF); + break; + case 0x87: + name = "JNBE\t"; + cond = !(ACCESS_FLAG(F_CF) || ACCESS_FLAG(F_ZF)); + break; + case 0x88: + name = "JS\t"; + cond = ACCESS_FLAG(F_SF); + break; + case 0x89: + name = "JNS\t"; + cond = !ACCESS_FLAG(F_SF); + break; + case 0x8a: + name = "JP\t"; + cond = ACCESS_FLAG(F_PF); + break; + case 0x8b: + name = "JNP\t"; + cond = !ACCESS_FLAG(F_PF); + break; + case 0x8c: + name = "JL\t"; + cond = xorl(ACCESS_FLAG(F_SF), ACCESS_FLAG(F_OF)); + break; + case 0x8d: + name = "JNL\t"; + cond = !xorl(ACCESS_FLAG(F_SF), ACCESS_FLAG(F_OF)); + break; + case 0x8e: + name = "JLE\t"; + cond = (xorl(ACCESS_FLAG(F_SF), ACCESS_FLAG(F_OF)) || + ACCESS_FLAG(F_ZF)); + break; + case 0x8f: + name = "JNLE\t"; + cond = !(xorl(ACCESS_FLAG(F_SF), ACCESS_FLAG(F_OF)) || + ACCESS_FLAG(F_ZF)); + break; + } + DECODE_PRINTF(name); + (void)name; + target = (s16) fetch_word_imm(); + target += (s16) M.x86.R_IP; + DECODE_PRINTF2("%04x\n", target); + TRACE_AND_STEP(); + if (cond) + M.x86.R_IP = (u16)target; + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x0f,0x90-0x9F +****************************************************************************/ +static void x86emuOp2_set_byte(u8 op2) +{ + int mod, rl, rh; + uint destoffset; + u8 *destreg; + const char *name = 0; + int cond = 0; + + START_OF_INSTR(); + switch (op2) { + case 0x90: + name = "SETO\t"; + cond = ACCESS_FLAG(F_OF); + break; + case 0x91: + name = "SETNO\t"; + cond = !ACCESS_FLAG(F_OF); + break; + case 0x92: + name = "SETB\t"; + cond = ACCESS_FLAG(F_CF); + break; + case 0x93: + name = "SETNB\t"; + cond = !ACCESS_FLAG(F_CF); + break; + case 0x94: + name = "SETZ\t"; + cond = ACCESS_FLAG(F_ZF); + break; + case 0x95: + name = "SETNZ\t"; + cond = !ACCESS_FLAG(F_ZF); + break; + case 0x96: + name = "SETBE\t"; + cond = ACCESS_FLAG(F_CF) || ACCESS_FLAG(F_ZF); + break; + case 0x97: + name = "SETNBE\t"; + cond = !(ACCESS_FLAG(F_CF) || ACCESS_FLAG(F_ZF)); + break; + case 0x98: + name = "SETS\t"; + cond = ACCESS_FLAG(F_SF); + break; + case 0x99: + name = "SETNS\t"; + cond = !ACCESS_FLAG(F_SF); + break; + case 0x9a: + name = "SETP\t"; + cond = ACCESS_FLAG(F_PF); + break; + case 0x9b: + name = "SETNP\t"; + cond = !ACCESS_FLAG(F_PF); + break; + case 0x9c: + name = "SETL\t"; + cond = xorl(ACCESS_FLAG(F_SF), ACCESS_FLAG(F_OF)); + break; + case 0x9d: + name = "SETNL\t"; + cond = xorl(ACCESS_FLAG(F_SF), ACCESS_FLAG(F_OF)); + break; + case 0x9e: + name = "SETLE\t"; + cond = (xorl(ACCESS_FLAG(F_SF), ACCESS_FLAG(F_OF)) || + ACCESS_FLAG(F_ZF)); + break; + case 0x9f: + name = "SETNLE\t"; + cond = !(xorl(ACCESS_FLAG(F_SF), ACCESS_FLAG(F_OF)) || + ACCESS_FLAG(F_ZF)); + break; + } + DECODE_PRINTF(name); + (void)name; + FETCH_DECODE_MODRM(mod, rh, rl); + switch (mod) { + case 0: + destoffset = decode_rm00_address(rl); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + store_data_byte(destoffset, cond ? 0x01 : 0x00); + break; + case 1: + destoffset = decode_rm01_address(rl); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + store_data_byte(destoffset, cond ? 0x01 : 0x00); + break; + case 2: + destoffset = decode_rm10_address(rl); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + store_data_byte(destoffset, cond ? 0x01 : 0x00); + break; + case 3: /* register to register */ + destreg = DECODE_RM_BYTE_REGISTER(rl); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = cond ? 0x01 : 0x00; + break; + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x0f,0xa0 +****************************************************************************/ +static void x86emuOp2_push_FS(u8 X86EMU_UNUSED(op2)) +{ + START_OF_INSTR(); + DECODE_PRINTF("PUSH\tFS\n"); + TRACE_AND_STEP(); + push_word(M.x86.R_FS); + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x0f,0xa1 +****************************************************************************/ +static void x86emuOp2_pop_FS(u8 X86EMU_UNUSED(op2)) +{ + START_OF_INSTR(); + DECODE_PRINTF("POP\tFS\n"); + TRACE_AND_STEP(); + M.x86.R_FS = pop_word(); + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x0f,0xa3 +****************************************************************************/ +static void x86emuOp2_bt_R(u8 X86EMU_UNUSED(op2)) +{ + int mod, rl, rh; + uint srcoffset; + int bit,disp; + + START_OF_INSTR(); + DECODE_PRINTF("BT\t"); + FETCH_DECODE_MODRM(mod, rh, rl); + switch (mod) { + case 0: + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 srcval; + u32 *shiftreg; + + srcoffset = decode_rm00_address(rl); + DECODE_PRINTF(","); + shiftreg = DECODE_RM_LONG_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + bit = *shiftreg & 0x1F; + disp = (s16)*shiftreg >> 5; + srcval = fetch_data_long(srcoffset+disp); + CONDITIONAL_SET_FLAG(srcval & (0x1 << bit),F_CF); + } else { + u16 srcval; + u16 *shiftreg; + + srcoffset = decode_rm00_address(rl); + DECODE_PRINTF(","); + shiftreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + bit = *shiftreg & 0xF; + disp = (s16)*shiftreg >> 4; + srcval = fetch_data_word(srcoffset+disp); + CONDITIONAL_SET_FLAG(srcval & (0x1 << bit),F_CF); + } + break; + case 1: + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 srcval; + u32 *shiftreg; + + srcoffset = decode_rm01_address(rl); + DECODE_PRINTF(","); + shiftreg = DECODE_RM_LONG_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + bit = *shiftreg & 0x1F; + disp = (s16)*shiftreg >> 5; + srcval = fetch_data_long(srcoffset+disp); + CONDITIONAL_SET_FLAG(srcval & (0x1 << bit),F_CF); + } else { + u16 srcval; + u16 *shiftreg; + + srcoffset = decode_rm01_address(rl); + DECODE_PRINTF(","); + shiftreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + bit = *shiftreg & 0xF; + disp = (s16)*shiftreg >> 4; + srcval = fetch_data_word(srcoffset+disp); + CONDITIONAL_SET_FLAG(srcval & (0x1 << bit),F_CF); + } + break; + case 2: + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 srcval; + u32 *shiftreg; + + srcoffset = decode_rm10_address(rl); + DECODE_PRINTF(","); + shiftreg = DECODE_RM_LONG_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + bit = *shiftreg & 0x1F; + disp = (s16)*shiftreg >> 5; + srcval = fetch_data_long(srcoffset+disp); + CONDITIONAL_SET_FLAG(srcval & (0x1 << bit),F_CF); + } else { + u16 srcval; + u16 *shiftreg; + + srcoffset = decode_rm10_address(rl); + DECODE_PRINTF(","); + shiftreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + bit = *shiftreg & 0xF; + disp = (s16)*shiftreg >> 4; + srcval = fetch_data_word(srcoffset+disp); + CONDITIONAL_SET_FLAG(srcval & (0x1 << bit),F_CF); + } + break; + case 3: /* register to register */ + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 *srcreg,*shiftreg; + + srcreg = DECODE_RM_LONG_REGISTER(rl); + DECODE_PRINTF(","); + shiftreg = DECODE_RM_LONG_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + bit = *shiftreg & 0x1F; + CONDITIONAL_SET_FLAG(*srcreg & (0x1 << bit),F_CF); + } else { + u16 *srcreg,*shiftreg; + + srcreg = DECODE_RM_WORD_REGISTER(rl); + DECODE_PRINTF(","); + shiftreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + bit = *shiftreg & 0xF; + CONDITIONAL_SET_FLAG(*srcreg & (0x1 << bit),F_CF); + } + break; + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x0f,0xa4 +****************************************************************************/ +static void x86emuOp2_shld_IMM(u8 X86EMU_UNUSED(op2)) +{ + int mod, rl, rh; + uint destoffset; + u8 shift; + + START_OF_INSTR(); + DECODE_PRINTF("SHLD\t"); + FETCH_DECODE_MODRM(mod, rh, rl); + switch (mod) { + case 0: + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 destval; + u32 *shiftreg; + + destoffset = decode_rm00_address(rl); + DECODE_PRINTF(","); + shiftreg = DECODE_RM_LONG_REGISTER(rh); + DECODE_PRINTF(","); + shift = fetch_byte_imm(); + DECODE_PRINTF2("%d\n", shift); + TRACE_AND_STEP(); + destval = fetch_data_long(destoffset); + destval = shld_long(destval,*shiftreg,shift); + store_data_long(destoffset, destval); + } else { + u16 destval; + u16 *shiftreg; + + destoffset = decode_rm00_address(rl); + DECODE_PRINTF(","); + shiftreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF(","); + shift = fetch_byte_imm(); + DECODE_PRINTF2("%d\n", shift); + TRACE_AND_STEP(); + destval = fetch_data_word(destoffset); + destval = shld_word(destval,*shiftreg,shift); + store_data_word(destoffset, destval); + } + break; + case 1: + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 destval; + u32 *shiftreg; + + destoffset = decode_rm01_address(rl); + DECODE_PRINTF(","); + shiftreg = DECODE_RM_LONG_REGISTER(rh); + DECODE_PRINTF(","); + shift = fetch_byte_imm(); + DECODE_PRINTF2("%d\n", shift); + TRACE_AND_STEP(); + destval = fetch_data_long(destoffset); + destval = shld_long(destval,*shiftreg,shift); + store_data_long(destoffset, destval); + } else { + u16 destval; + u16 *shiftreg; + + destoffset = decode_rm01_address(rl); + DECODE_PRINTF(","); + shiftreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF(","); + shift = fetch_byte_imm(); + DECODE_PRINTF2("%d\n", shift); + TRACE_AND_STEP(); + destval = fetch_data_word(destoffset); + destval = shld_word(destval,*shiftreg,shift); + store_data_word(destoffset, destval); + } + break; + case 2: + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 destval; + u32 *shiftreg; + + destoffset = decode_rm10_address(rl); + DECODE_PRINTF(","); + shiftreg = DECODE_RM_LONG_REGISTER(rh); + DECODE_PRINTF(","); + shift = fetch_byte_imm(); + DECODE_PRINTF2("%d\n", shift); + TRACE_AND_STEP(); + destval = fetch_data_long(destoffset); + destval = shld_long(destval,*shiftreg,shift); + store_data_long(destoffset, destval); + } else { + u16 destval; + u16 *shiftreg; + + destoffset = decode_rm10_address(rl); + DECODE_PRINTF(","); + shiftreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF(","); + shift = fetch_byte_imm(); + DECODE_PRINTF2("%d\n", shift); + TRACE_AND_STEP(); + destval = fetch_data_word(destoffset); + destval = shld_word(destval,*shiftreg,shift); + store_data_word(destoffset, destval); + } + break; + case 3: /* register to register */ + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 *destreg,*shiftreg; + + destreg = DECODE_RM_LONG_REGISTER(rl); + DECODE_PRINTF(","); + shiftreg = DECODE_RM_LONG_REGISTER(rh); + DECODE_PRINTF(","); + shift = fetch_byte_imm(); + DECODE_PRINTF2("%d\n", shift); + TRACE_AND_STEP(); + *destreg = shld_long(*destreg,*shiftreg,shift); + } else { + u16 *destreg,*shiftreg; + + destreg = DECODE_RM_WORD_REGISTER(rl); + DECODE_PRINTF(","); + shiftreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF(","); + shift = fetch_byte_imm(); + DECODE_PRINTF2("%d\n", shift); + TRACE_AND_STEP(); + *destreg = shld_word(*destreg,*shiftreg,shift); + } + break; + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x0f,0xa5 +****************************************************************************/ +static void x86emuOp2_shld_CL(u8 X86EMU_UNUSED(op2)) +{ + int mod, rl, rh; + uint destoffset; + + START_OF_INSTR(); + DECODE_PRINTF("SHLD\t"); + FETCH_DECODE_MODRM(mod, rh, rl); + switch (mod) { + case 0: + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 destval; + u32 *shiftreg; + + destoffset = decode_rm00_address(rl); + DECODE_PRINTF(","); + shiftreg = DECODE_RM_LONG_REGISTER(rh); + DECODE_PRINTF(",CL\n"); + TRACE_AND_STEP(); + destval = fetch_data_long(destoffset); + destval = shld_long(destval,*shiftreg,M.x86.R_CL); + store_data_long(destoffset, destval); + } else { + u16 destval; + u16 *shiftreg; + + destoffset = decode_rm00_address(rl); + DECODE_PRINTF(","); + shiftreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF(",CL\n"); + TRACE_AND_STEP(); + destval = fetch_data_word(destoffset); + destval = shld_word(destval,*shiftreg,M.x86.R_CL); + store_data_word(destoffset, destval); + } + break; + case 1: + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 destval; + u32 *shiftreg; + + destoffset = decode_rm01_address(rl); + DECODE_PRINTF(","); + shiftreg = DECODE_RM_LONG_REGISTER(rh); + DECODE_PRINTF(",CL\n"); + TRACE_AND_STEP(); + destval = fetch_data_long(destoffset); + destval = shld_long(destval,*shiftreg,M.x86.R_CL); + store_data_long(destoffset, destval); + } else { + u16 destval; + u16 *shiftreg; + + destoffset = decode_rm01_address(rl); + DECODE_PRINTF(","); + shiftreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF(",CL\n"); + TRACE_AND_STEP(); + destval = fetch_data_word(destoffset); + destval = shld_word(destval,*shiftreg,M.x86.R_CL); + store_data_word(destoffset, destval); + } + break; + case 2: + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 destval; + u32 *shiftreg; + + destoffset = decode_rm10_address(rl); + DECODE_PRINTF(","); + shiftreg = DECODE_RM_LONG_REGISTER(rh); + DECODE_PRINTF(",CL\n"); + TRACE_AND_STEP(); + destval = fetch_data_long(destoffset); + destval = shld_long(destval,*shiftreg,M.x86.R_CL); + store_data_long(destoffset, destval); + } else { + u16 destval; + u16 *shiftreg; + + destoffset = decode_rm10_address(rl); + DECODE_PRINTF(","); + shiftreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF(",CL\n"); + TRACE_AND_STEP(); + destval = fetch_data_word(destoffset); + destval = shld_word(destval,*shiftreg,M.x86.R_CL); + store_data_word(destoffset, destval); + } + break; + case 3: /* register to register */ + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 *destreg,*shiftreg; + + destreg = DECODE_RM_LONG_REGISTER(rl); + DECODE_PRINTF(","); + shiftreg = DECODE_RM_LONG_REGISTER(rh); + DECODE_PRINTF(",CL\n"); + TRACE_AND_STEP(); + *destreg = shld_long(*destreg,*shiftreg,M.x86.R_CL); + } else { + u16 *destreg,*shiftreg; + + destreg = DECODE_RM_WORD_REGISTER(rl); + DECODE_PRINTF(","); + shiftreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF(",CL\n"); + TRACE_AND_STEP(); + *destreg = shld_word(*destreg,*shiftreg,M.x86.R_CL); + } + break; + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x0f,0xa8 +****************************************************************************/ +static void x86emuOp2_push_GS(u8 X86EMU_UNUSED(op2)) +{ + START_OF_INSTR(); + DECODE_PRINTF("PUSH\tGS\n"); + TRACE_AND_STEP(); + push_word(M.x86.R_GS); + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x0f,0xa9 +****************************************************************************/ +static void x86emuOp2_pop_GS(u8 X86EMU_UNUSED(op2)) +{ + START_OF_INSTR(); + DECODE_PRINTF("POP\tGS\n"); + TRACE_AND_STEP(); + M.x86.R_GS = pop_word(); + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +#if 1 +/**************************************************************************** +REMARKS: +Handles opcode 0x0f,0xab +****************************************************************************/ +static void x86emuOp2_bts_R(u8 X86EMU_UNUSED(op2)) +{ + int mod, rl, rh; + uint srcoffset; + int bit,disp; + + START_OF_INSTR(); + DECODE_PRINTF("BTS\t"); + FETCH_DECODE_MODRM(mod, rh, rl); + switch (mod) { + case 0: + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 srcval,mask; + u32 *shiftreg; + + srcoffset = decode_rm00_address(rl); + DECODE_PRINTF(","); + shiftreg = DECODE_RM_LONG_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + bit = *shiftreg & 0x1F; + disp = (s16)*shiftreg >> 5; + srcval = fetch_data_long(srcoffset+disp); + mask = (0x1 << bit); + CONDITIONAL_SET_FLAG(srcval & mask,F_CF); + store_data_long(srcoffset+disp, srcval | mask); + } else { + u16 srcval,mask; + u16 *shiftreg; + + srcoffset = decode_rm00_address(rl); + DECODE_PRINTF(","); + shiftreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + bit = *shiftreg & 0xF; + disp = (s16)*shiftreg >> 4; + srcval = fetch_data_word(srcoffset+disp); + mask = (u16)(0x1 << bit); + CONDITIONAL_SET_FLAG(srcval & mask,F_CF); + store_data_word(srcoffset+disp, srcval | mask); + } + break; + case 1: + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 srcval,mask; + u32 *shiftreg; + + srcoffset = decode_rm01_address(rl); + DECODE_PRINTF(","); + shiftreg = DECODE_RM_LONG_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + bit = *shiftreg & 0x1F; + disp = (s16)*shiftreg >> 5; + srcval = fetch_data_long(srcoffset+disp); + mask = (0x1 << bit); + CONDITIONAL_SET_FLAG(srcval & mask,F_CF); + store_data_long(srcoffset+disp, srcval | mask); + } else { + u16 srcval,mask; + u16 *shiftreg; + + srcoffset = decode_rm01_address(rl); + DECODE_PRINTF(","); + shiftreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + bit = *shiftreg & 0xF; + disp = (s16)*shiftreg >> 4; + srcval = fetch_data_word(srcoffset+disp); + mask = (u16)(0x1 << bit); + CONDITIONAL_SET_FLAG(srcval & mask,F_CF); + store_data_word(srcoffset+disp, srcval | mask); + } + break; + case 2: + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 srcval,mask; + u32 *shiftreg; + + srcoffset = decode_rm10_address(rl); + DECODE_PRINTF(","); + shiftreg = DECODE_RM_LONG_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + bit = *shiftreg & 0x1F; + disp = (s16)*shiftreg >> 5; + srcval = fetch_data_long(srcoffset+disp); + mask = (0x1 << bit); + CONDITIONAL_SET_FLAG(srcval & mask,F_CF); + store_data_long(srcoffset+disp, srcval | mask); + } else { + u16 srcval,mask; + u16 *shiftreg; + + srcoffset = decode_rm10_address(rl); + DECODE_PRINTF(","); + shiftreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + bit = *shiftreg & 0xF; + disp = (s16)*shiftreg >> 4; + srcval = fetch_data_word(srcoffset+disp); + mask = (u16)(0x1 << bit); + CONDITIONAL_SET_FLAG(srcval & mask,F_CF); + store_data_word(srcoffset+disp, srcval | mask); + } + break; + case 3: /* register to register */ + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 *srcreg,*shiftreg; + u32 mask; + + srcreg = DECODE_RM_LONG_REGISTER(rl); + DECODE_PRINTF(","); + shiftreg = DECODE_RM_LONG_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + bit = *shiftreg & 0x1F; + mask = (0x1 << bit); + CONDITIONAL_SET_FLAG(*srcreg & mask,F_CF); + *srcreg |= mask; + } else { + u16 *srcreg,*shiftreg; + u16 mask; + + srcreg = DECODE_RM_WORD_REGISTER(rl); + DECODE_PRINTF(","); + shiftreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + bit = *shiftreg & 0xF; + mask = (u16)(0x1 << bit); + CONDITIONAL_SET_FLAG(*srcreg & mask,F_CF); + *srcreg |= mask; + } + break; + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} +#endif + +/**************************************************************************** +REMARKS: +Handles opcode 0x0f,0xac +****************************************************************************/ +static void x86emuOp2_shrd_IMM(u8 X86EMU_UNUSED(op2)) +{ + int mod, rl, rh; + uint destoffset; + u8 shift; + + START_OF_INSTR(); + DECODE_PRINTF("SHLD\t"); + FETCH_DECODE_MODRM(mod, rh, rl); + switch (mod) { + case 0: + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 destval; + u32 *shiftreg; + + destoffset = decode_rm00_address(rl); + DECODE_PRINTF(","); + shiftreg = DECODE_RM_LONG_REGISTER(rh); + DECODE_PRINTF(","); + shift = fetch_byte_imm(); + DECODE_PRINTF2("%d\n", shift); + TRACE_AND_STEP(); + destval = fetch_data_long(destoffset); + destval = shrd_long(destval,*shiftreg,shift); + store_data_long(destoffset, destval); + } else { + u16 destval; + u16 *shiftreg; + + destoffset = decode_rm00_address(rl); + DECODE_PRINTF(","); + shiftreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF(","); + shift = fetch_byte_imm(); + DECODE_PRINTF2("%d\n", shift); + TRACE_AND_STEP(); + destval = fetch_data_word(destoffset); + destval = shrd_word(destval,*shiftreg,shift); + store_data_word(destoffset, destval); + } + break; + case 1: + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 destval; + u32 *shiftreg; + + destoffset = decode_rm01_address(rl); + DECODE_PRINTF(","); + shiftreg = DECODE_RM_LONG_REGISTER(rh); + DECODE_PRINTF(","); + shift = fetch_byte_imm(); + DECODE_PRINTF2("%d\n", shift); + TRACE_AND_STEP(); + destval = fetch_data_long(destoffset); + destval = shrd_long(destval,*shiftreg,shift); + store_data_long(destoffset, destval); + } else { + u16 destval; + u16 *shiftreg; + + destoffset = decode_rm01_address(rl); + DECODE_PRINTF(","); + shiftreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF(","); + shift = fetch_byte_imm(); + DECODE_PRINTF2("%d\n", shift); + TRACE_AND_STEP(); + destval = fetch_data_word(destoffset); + destval = shrd_word(destval,*shiftreg,shift); + store_data_word(destoffset, destval); + } + break; + case 2: + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 destval; + u32 *shiftreg; + + destoffset = decode_rm10_address(rl); + DECODE_PRINTF(","); + shiftreg = DECODE_RM_LONG_REGISTER(rh); + DECODE_PRINTF(","); + shift = fetch_byte_imm(); + DECODE_PRINTF2("%d\n", shift); + TRACE_AND_STEP(); + destval = fetch_data_long(destoffset); + destval = shrd_long(destval,*shiftreg,shift); + store_data_long(destoffset, destval); + } else { + u16 destval; + u16 *shiftreg; + + destoffset = decode_rm10_address(rl); + DECODE_PRINTF(","); + shiftreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF(","); + shift = fetch_byte_imm(); + DECODE_PRINTF2("%d\n", shift); + TRACE_AND_STEP(); + destval = fetch_data_word(destoffset); + destval = shrd_word(destval,*shiftreg,shift); + store_data_word(destoffset, destval); + } + break; + case 3: /* register to register */ + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 *destreg,*shiftreg; + + destreg = DECODE_RM_LONG_REGISTER(rl); + DECODE_PRINTF(","); + shiftreg = DECODE_RM_LONG_REGISTER(rh); + DECODE_PRINTF(","); + shift = fetch_byte_imm(); + DECODE_PRINTF2("%d\n", shift); + TRACE_AND_STEP(); + *destreg = shrd_long(*destreg,*shiftreg,shift); + } else { + u16 *destreg,*shiftreg; + + destreg = DECODE_RM_WORD_REGISTER(rl); + DECODE_PRINTF(","); + shiftreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF(","); + shift = fetch_byte_imm(); + DECODE_PRINTF2("%d\n", shift); + TRACE_AND_STEP(); + *destreg = shrd_word(*destreg,*shiftreg,shift); + } + break; + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x0f,0xad +****************************************************************************/ +static void x86emuOp2_shrd_CL(u8 X86EMU_UNUSED(op2)) +{ + int mod, rl, rh; + uint destoffset; + + START_OF_INSTR(); + DECODE_PRINTF("SHLD\t"); + FETCH_DECODE_MODRM(mod, rh, rl); + switch (mod) { + case 0: + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 destval; + u32 *shiftreg; + + destoffset = decode_rm00_address(rl); + DECODE_PRINTF(","); + shiftreg = DECODE_RM_LONG_REGISTER(rh); + DECODE_PRINTF(",CL\n"); + TRACE_AND_STEP(); + destval = fetch_data_long(destoffset); + destval = shrd_long(destval,*shiftreg,M.x86.R_CL); + store_data_long(destoffset, destval); + } else { + u16 destval; + u16 *shiftreg; + + destoffset = decode_rm00_address(rl); + DECODE_PRINTF(","); + shiftreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF(",CL\n"); + TRACE_AND_STEP(); + destval = fetch_data_word(destoffset); + destval = shrd_word(destval,*shiftreg,M.x86.R_CL); + store_data_word(destoffset, destval); + } + break; + case 1: + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 destval; + u32 *shiftreg; + + destoffset = decode_rm01_address(rl); + DECODE_PRINTF(","); + shiftreg = DECODE_RM_LONG_REGISTER(rh); + DECODE_PRINTF(",CL\n"); + TRACE_AND_STEP(); + destval = fetch_data_long(destoffset); + destval = shrd_long(destval,*shiftreg,M.x86.R_CL); + store_data_long(destoffset, destval); + } else { + u16 destval; + u16 *shiftreg; + + destoffset = decode_rm01_address(rl); + DECODE_PRINTF(","); + shiftreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF(",CL\n"); + TRACE_AND_STEP(); + destval = fetch_data_word(destoffset); + destval = shrd_word(destval,*shiftreg,M.x86.R_CL); + store_data_word(destoffset, destval); + } + break; + case 2: + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 destval; + u32 *shiftreg; + + destoffset = decode_rm10_address(rl); + DECODE_PRINTF(","); + shiftreg = DECODE_RM_LONG_REGISTER(rh); + DECODE_PRINTF(",CL\n"); + TRACE_AND_STEP(); + destval = fetch_data_long(destoffset); + destval = shrd_long(destval,*shiftreg,M.x86.R_CL); + store_data_long(destoffset, destval); + } else { + u16 destval; + u16 *shiftreg; + + destoffset = decode_rm10_address(rl); + DECODE_PRINTF(","); + shiftreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF(",CL\n"); + TRACE_AND_STEP(); + destval = fetch_data_word(destoffset); + destval = shrd_word(destval,*shiftreg,M.x86.R_CL); + store_data_word(destoffset, destval); + } + break; + case 3: /* register to register */ + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 *destreg,*shiftreg; + + destreg = DECODE_RM_LONG_REGISTER(rl); + DECODE_PRINTF(","); + shiftreg = DECODE_RM_LONG_REGISTER(rh); + DECODE_PRINTF(",CL\n"); + TRACE_AND_STEP(); + *destreg = shrd_long(*destreg,*shiftreg,M.x86.R_CL); + } else { + u16 *destreg,*shiftreg; + + destreg = DECODE_RM_WORD_REGISTER(rl); + DECODE_PRINTF(","); + shiftreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF(",CL\n"); + TRACE_AND_STEP(); + *destreg = shrd_word(*destreg,*shiftreg,M.x86.R_CL); + } + break; + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x0f,0xaf +****************************************************************************/ +static void x86emuOp2_imul_R_RM(u8 X86EMU_UNUSED(op2)) +{ + int mod, rl, rh; + uint srcoffset; + + START_OF_INSTR(); + DECODE_PRINTF("IMUL\t"); + FETCH_DECODE_MODRM(mod, rh, rl); + switch (mod) { + case 0: + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 *destreg; + u32 srcval; + u32 res_lo,res_hi; + + destreg = DECODE_RM_LONG_REGISTER(rh); + DECODE_PRINTF(","); + srcoffset = decode_rm00_address(rl); + srcval = fetch_data_long(srcoffset); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + imul_long_direct(&res_lo,&res_hi,(s32)*destreg,(s32)srcval); + if (res_hi != 0) { + SET_FLAG(F_CF); + SET_FLAG(F_OF); + } else { + CLEAR_FLAG(F_CF); + CLEAR_FLAG(F_OF); + } + *destreg = (u32)res_lo; + } else { + u16 *destreg; + u16 srcval; + u32 res; + + destreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF(","); + srcoffset = decode_rm00_address(rl); + srcval = fetch_data_word(srcoffset); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + res = (s16)*destreg * (s16)srcval; + if (res > 0xFFFF) { + SET_FLAG(F_CF); + SET_FLAG(F_OF); + } else { + CLEAR_FLAG(F_CF); + CLEAR_FLAG(F_OF); + } + *destreg = (u16)res; + } + break; + case 1: + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 *destreg; + u32 srcval; + u32 res_lo,res_hi; + + destreg = DECODE_RM_LONG_REGISTER(rh); + DECODE_PRINTF(","); + srcoffset = decode_rm01_address(rl); + srcval = fetch_data_long(srcoffset); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + imul_long_direct(&res_lo,&res_hi,(s32)*destreg,(s32)srcval); + if (res_hi != 0) { + SET_FLAG(F_CF); + SET_FLAG(F_OF); + } else { + CLEAR_FLAG(F_CF); + CLEAR_FLAG(F_OF); + } + *destreg = (u32)res_lo; + } else { + u16 *destreg; + u16 srcval; + u32 res; + + destreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF(","); + srcoffset = decode_rm01_address(rl); + srcval = fetch_data_word(srcoffset); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + res = (s16)*destreg * (s16)srcval; + if (res > 0xFFFF) { + SET_FLAG(F_CF); + SET_FLAG(F_OF); + } else { + CLEAR_FLAG(F_CF); + CLEAR_FLAG(F_OF); + } + *destreg = (u16)res; + } + break; + case 2: + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 *destreg; + u32 srcval; + u32 res_lo,res_hi; + + destreg = DECODE_RM_LONG_REGISTER(rh); + DECODE_PRINTF(","); + srcoffset = decode_rm10_address(rl); + srcval = fetch_data_long(srcoffset); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + imul_long_direct(&res_lo,&res_hi,(s32)*destreg,(s32)srcval); + if (res_hi != 0) { + SET_FLAG(F_CF); + SET_FLAG(F_OF); + } else { + CLEAR_FLAG(F_CF); + CLEAR_FLAG(F_OF); + } + *destreg = (u32)res_lo; + } else { + u16 *destreg; + u16 srcval; + u32 res; + + destreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF(","); + srcoffset = decode_rm10_address(rl); + srcval = fetch_data_word(srcoffset); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + res = (s16)*destreg * (s16)srcval; + if (res > 0xFFFF) { + SET_FLAG(F_CF); + SET_FLAG(F_OF); + } else { + CLEAR_FLAG(F_CF); + CLEAR_FLAG(F_OF); + } + *destreg = (u16)res; + } + break; + case 3: /* register to register */ + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 *destreg,*srcreg; + u32 res_lo,res_hi; + + destreg = DECODE_RM_LONG_REGISTER(rh); + DECODE_PRINTF(","); + srcreg = DECODE_RM_LONG_REGISTER(rl); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + imul_long_direct(&res_lo,&res_hi,(s32)*destreg,(s32)*srcreg); + if (res_hi != 0) { + SET_FLAG(F_CF); + SET_FLAG(F_OF); + } else { + CLEAR_FLAG(F_CF); + CLEAR_FLAG(F_OF); + } + *destreg = (u32)res_lo; + } else { + u16 *destreg,*srcreg; + u32 res; + + destreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF(","); + srcreg = DECODE_RM_WORD_REGISTER(rl); + res = (s16)*destreg * (s16)*srcreg; + if (res > 0xFFFF) { + SET_FLAG(F_CF); + SET_FLAG(F_OF); + } else { + CLEAR_FLAG(F_CF); + CLEAR_FLAG(F_OF); + } + *destreg = (u16)res; + } + break; + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x0f,0xb2 +****************************************************************************/ +static void x86emuOp2_lss_R_IMM(u8 X86EMU_UNUSED(op2)) +{ + int mod, rh, rl; + u16 *dstreg; + uint srcoffset; + + START_OF_INSTR(); + DECODE_PRINTF("LSS\t"); + FETCH_DECODE_MODRM(mod, rh, rl); + switch (mod) { + case 0: + dstreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF(","); + srcoffset = decode_rm00_address(rl); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *dstreg = fetch_data_word(srcoffset); + M.x86.R_SS = fetch_data_word(srcoffset + 2); + break; + case 1: + dstreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF(","); + srcoffset = decode_rm01_address(rl); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *dstreg = fetch_data_word(srcoffset); + M.x86.R_SS = fetch_data_word(srcoffset + 2); + break; + case 2: + dstreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF(","); + srcoffset = decode_rm10_address(rl); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *dstreg = fetch_data_word(srcoffset); + M.x86.R_SS = fetch_data_word(srcoffset + 2); + break; + case 3: /* register to register */ + /* UNDEFINED! */ + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x0f,0xb3 +****************************************************************************/ +static void x86emuOp2_btr_R(u8 X86EMU_UNUSED(op2)) +{ + int mod, rl, rh; + uint srcoffset; + int bit,disp; + + START_OF_INSTR(); + DECODE_PRINTF("BTR\t"); + FETCH_DECODE_MODRM(mod, rh, rl); + switch (mod) { + case 0: + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 srcval,mask; + u32 *shiftreg; + + srcoffset = decode_rm00_address(rl); + DECODE_PRINTF(","); + shiftreg = DECODE_RM_LONG_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + bit = *shiftreg & 0x1F; + disp = (s16)*shiftreg >> 5; + srcval = fetch_data_long(srcoffset+disp); + mask = (0x1 << bit); + CONDITIONAL_SET_FLAG(srcval & mask,F_CF); + store_data_long(srcoffset+disp, srcval & ~mask); + } else { + u16 srcval,mask; + u16 *shiftreg; + + srcoffset = decode_rm00_address(rl); + DECODE_PRINTF(","); + shiftreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + bit = *shiftreg & 0xF; + disp = (s16)*shiftreg >> 4; + srcval = fetch_data_word(srcoffset+disp); + mask = (u16)(0x1 << bit); + CONDITIONAL_SET_FLAG(srcval & mask,F_CF); + store_data_word(srcoffset+disp, (u16)(srcval & ~mask)); + } + break; + case 1: + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 srcval,mask; + u32 *shiftreg; + + srcoffset = decode_rm01_address(rl); + DECODE_PRINTF(","); + shiftreg = DECODE_RM_LONG_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + bit = *shiftreg & 0x1F; + disp = (s16)*shiftreg >> 5; + srcval = fetch_data_long(srcoffset+disp); + mask = (0x1 << bit); + CONDITIONAL_SET_FLAG(srcval & mask,F_CF); + store_data_long(srcoffset+disp, srcval & ~mask); + } else { + u16 srcval,mask; + u16 *shiftreg; + + srcoffset = decode_rm01_address(rl); + DECODE_PRINTF(","); + shiftreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + bit = *shiftreg & 0xF; + disp = (s16)*shiftreg >> 4; + srcval = fetch_data_word(srcoffset+disp); + mask = (u16)(0x1 << bit); + CONDITIONAL_SET_FLAG(srcval & mask,F_CF); + store_data_word(srcoffset+disp, (u16)(srcval & ~mask)); + } + break; + case 2: + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 srcval,mask; + u32 *shiftreg; + + srcoffset = decode_rm10_address(rl); + DECODE_PRINTF(","); + shiftreg = DECODE_RM_LONG_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + bit = *shiftreg & 0x1F; + disp = (s16)*shiftreg >> 5; + srcval = fetch_data_long(srcoffset+disp); + mask = (0x1 << bit); + CONDITIONAL_SET_FLAG(srcval & mask,F_CF); + store_data_long(srcoffset+disp, srcval & ~mask); + } else { + u16 srcval,mask; + u16 *shiftreg; + + srcoffset = decode_rm10_address(rl); + DECODE_PRINTF(","); + shiftreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + bit = *shiftreg & 0xF; + disp = (s16)*shiftreg >> 4; + srcval = fetch_data_word(srcoffset+disp); + mask = (u16)(0x1 << bit); + CONDITIONAL_SET_FLAG(srcval & mask,F_CF); + store_data_word(srcoffset+disp, (u16)(srcval & ~mask)); + } + break; + case 3: /* register to register */ + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 *srcreg,*shiftreg; + u32 mask; + + srcreg = DECODE_RM_LONG_REGISTER(rl); + DECODE_PRINTF(","); + shiftreg = DECODE_RM_LONG_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + bit = *shiftreg & 0x1F; + mask = (0x1 << bit); + CONDITIONAL_SET_FLAG(*srcreg & mask,F_CF); + *srcreg &= ~mask; + } else { + u16 *srcreg,*shiftreg; + u16 mask; + + srcreg = DECODE_RM_WORD_REGISTER(rl); + DECODE_PRINTF(","); + shiftreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + bit = *shiftreg & 0xF; + mask = (u16)(0x1 << bit); + CONDITIONAL_SET_FLAG(*srcreg & mask,F_CF); + *srcreg &= ~mask; + } + break; + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x0f,0xb4 +****************************************************************************/ +static void x86emuOp2_lfs_R_IMM(u8 X86EMU_UNUSED(op2)) +{ + int mod, rh, rl; + u16 *dstreg; + uint srcoffset; + + START_OF_INSTR(); + DECODE_PRINTF("LFS\t"); + FETCH_DECODE_MODRM(mod, rh, rl); + switch (mod) { + case 0: + dstreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF(","); + srcoffset = decode_rm00_address(rl); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *dstreg = fetch_data_word(srcoffset); + M.x86.R_FS = fetch_data_word(srcoffset + 2); + break; + case 1: + dstreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF(","); + srcoffset = decode_rm01_address(rl); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *dstreg = fetch_data_word(srcoffset); + M.x86.R_FS = fetch_data_word(srcoffset + 2); + break; + case 2: + dstreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF(","); + srcoffset = decode_rm10_address(rl); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *dstreg = fetch_data_word(srcoffset); + M.x86.R_FS = fetch_data_word(srcoffset + 2); + break; + case 3: /* register to register */ + /* UNDEFINED! */ + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x0f,0xb5 +****************************************************************************/ +static void x86emuOp2_lgs_R_IMM(u8 X86EMU_UNUSED(op2)) +{ + int mod, rh, rl; + u16 *dstreg; + uint srcoffset; + + START_OF_INSTR(); + DECODE_PRINTF("LGS\t"); + FETCH_DECODE_MODRM(mod, rh, rl); + switch (mod) { + case 0: + dstreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF(","); + srcoffset = decode_rm00_address(rl); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *dstreg = fetch_data_word(srcoffset); + M.x86.R_GS = fetch_data_word(srcoffset + 2); + break; + case 1: + dstreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF(","); + srcoffset = decode_rm01_address(rl); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *dstreg = fetch_data_word(srcoffset); + M.x86.R_GS = fetch_data_word(srcoffset + 2); + break; + case 2: + dstreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF(","); + srcoffset = decode_rm10_address(rl); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *dstreg = fetch_data_word(srcoffset); + M.x86.R_GS = fetch_data_word(srcoffset + 2); + break; + case 3: /* register to register */ + /* UNDEFINED! */ + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x0f,0xb6 +****************************************************************************/ +static void x86emuOp2_movzx_byte_R_RM(u8 X86EMU_UNUSED(op2)) +{ + int mod, rl, rh; + uint srcoffset; + + START_OF_INSTR(); + DECODE_PRINTF("MOVZX\t"); + FETCH_DECODE_MODRM(mod, rh, rl); + switch (mod) { + case 0: + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 *destreg; + u32 srcval; + + destreg = DECODE_RM_LONG_REGISTER(rh); + DECODE_PRINTF(","); + srcoffset = decode_rm00_address(rl); + srcval = fetch_data_byte(srcoffset); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = srcval; + } else { + u16 *destreg; + u16 srcval; + + destreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF(","); + srcoffset = decode_rm00_address(rl); + srcval = fetch_data_byte(srcoffset); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = srcval; + } + break; + case 1: + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 *destreg; + u32 srcval; + + destreg = DECODE_RM_LONG_REGISTER(rh); + DECODE_PRINTF(","); + srcoffset = decode_rm01_address(rl); + srcval = fetch_data_byte(srcoffset); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = srcval; + } else { + u16 *destreg; + u16 srcval; + + destreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF(","); + srcoffset = decode_rm01_address(rl); + srcval = fetch_data_byte(srcoffset); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = srcval; + } + break; + case 2: + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 *destreg; + u32 srcval; + + destreg = DECODE_RM_LONG_REGISTER(rh); + DECODE_PRINTF(","); + srcoffset = decode_rm10_address(rl); + srcval = fetch_data_byte(srcoffset); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = srcval; + } else { + u16 *destreg; + u16 srcval; + + destreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF(","); + srcoffset = decode_rm10_address(rl); + srcval = fetch_data_byte(srcoffset); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = srcval; + } + break; + case 3: /* register to register */ + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 *destreg; + u8 *srcreg; + + destreg = DECODE_RM_LONG_REGISTER(rh); + DECODE_PRINTF(","); + srcreg = DECODE_RM_BYTE_REGISTER(rl); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = *srcreg; + } else { + u16 *destreg; + u8 *srcreg; + + destreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF(","); + srcreg = DECODE_RM_BYTE_REGISTER(rl); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = *srcreg; + } + break; + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x0f,0xb7 +****************************************************************************/ +static void x86emuOp2_movzx_word_R_RM(u8 X86EMU_UNUSED(op2)) +{ + int mod, rl, rh; + uint srcoffset; + u32 *destreg; + u32 srcval; + u16 *srcreg; + + START_OF_INSTR(); + DECODE_PRINTF("MOVZX\t"); + FETCH_DECODE_MODRM(mod, rh, rl); + switch (mod) { + case 0: + destreg = DECODE_RM_LONG_REGISTER(rh); + DECODE_PRINTF(","); + srcoffset = decode_rm00_address(rl); + srcval = fetch_data_word(srcoffset); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = srcval; + break; + case 1: + destreg = DECODE_RM_LONG_REGISTER(rh); + DECODE_PRINTF(","); + srcoffset = decode_rm01_address(rl); + srcval = fetch_data_word(srcoffset); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = srcval; + break; + case 2: + destreg = DECODE_RM_LONG_REGISTER(rh); + DECODE_PRINTF(","); + srcoffset = decode_rm10_address(rl); + srcval = fetch_data_word(srcoffset); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = srcval; + break; + case 3: /* register to register */ + destreg = DECODE_RM_LONG_REGISTER(rh); + DECODE_PRINTF(","); + srcreg = DECODE_RM_WORD_REGISTER(rl); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = *srcreg; + break; + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x0f,0xba +****************************************************************************/ +static void x86emuOp2_btX_I(u8 X86EMU_UNUSED(op2)) +{ + int mod, rl, rh; + uint srcoffset; + int bit; + + START_OF_INSTR(); + FETCH_DECODE_MODRM(mod, rh, rl); + switch (rh) { + case 4: + DECODE_PRINTF("BT\t"); + break; + case 5: + DECODE_PRINTF("BTS\t"); + break; + case 6: + DECODE_PRINTF("BTR\t"); + break; + case 7: + DECODE_PRINTF("BTC\t"); + break; + default: + DECODE_PRINTF("ILLEGAL EXTENDED X86 OPCODE\n"); + TRACE_REGS(); +DB( NV_PRINTF(LEVEL_INFO, + "%04x:%04x: %02X%02X ILLEGAL EXTENDED X86 OPCODE EXTENSION!\n", + M.x86.R_CS, M.x86.R_IP - 3, op2, + (mod << 6) | (rh << 3) | rl);) + HALT_SYS(); + } + switch (mod) { + case 0: + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 srcval, mask; + u8 shift; + + srcoffset = decode_rm00_address(rl); + DECODE_PRINTF(","); + shift = fetch_byte_imm(); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + bit = shift & 0x1F; + srcval = fetch_data_long(srcoffset); + mask = (0x1 << bit); + CONDITIONAL_SET_FLAG(srcval & mask,F_CF); + switch (rh) { + case 5: + store_data_long(srcoffset, srcval | mask); + break; + case 6: + store_data_long(srcoffset, srcval & ~mask); + break; + case 7: + store_data_long(srcoffset, srcval ^ mask); + break; + default: + break; + } + } else { + u16 srcval, mask; + u8 shift; + + srcoffset = decode_rm00_address(rl); + DECODE_PRINTF(","); + shift = fetch_byte_imm(); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + bit = shift & 0xF; + srcval = fetch_data_word(srcoffset); + mask = (0x1 << bit); + CONDITIONAL_SET_FLAG(srcval & mask,F_CF); + switch (rh) { + case 5: + store_data_word(srcoffset, srcval | mask); + break; + case 6: + store_data_word(srcoffset, srcval & ~mask); + break; + case 7: + store_data_word(srcoffset, srcval ^ mask); + break; + default: + break; + } + } + break; + case 1: + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 srcval, mask; + u8 shift; + + srcoffset = decode_rm01_address(rl); + DECODE_PRINTF(","); + shift = fetch_byte_imm(); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + bit = shift & 0x1F; + srcval = fetch_data_long(srcoffset); + mask = (0x1 << bit); + CONDITIONAL_SET_FLAG(srcval & mask,F_CF); + switch (rh) { + case 5: + store_data_long(srcoffset, srcval | mask); + break; + case 6: + store_data_long(srcoffset, srcval & ~mask); + break; + case 7: + store_data_long(srcoffset, srcval ^ mask); + break; + default: + break; + } + } else { + u16 srcval, mask; + u8 shift; + + srcoffset = decode_rm01_address(rl); + DECODE_PRINTF(","); + shift = fetch_byte_imm(); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + bit = shift & 0xF; + srcval = fetch_data_word(srcoffset); + mask = (0x1 << bit); + CONDITIONAL_SET_FLAG(srcval & mask,F_CF); + switch (rh) { + case 5: + store_data_word(srcoffset, srcval | mask); + break; + case 6: + store_data_word(srcoffset, srcval & ~mask); + break; + case 7: + store_data_word(srcoffset, srcval ^ mask); + break; + default: + break; + } + } + break; + case 2: + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 srcval, mask; + u8 shift; + + srcoffset = decode_rm10_address(rl); + DECODE_PRINTF(","); + shift = fetch_byte_imm(); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + bit = shift & 0x1F; + srcval = fetch_data_long(srcoffset); + mask = (0x1 << bit); + CONDITIONAL_SET_FLAG(srcval & mask,F_CF); + switch (rh) { + case 5: + store_data_long(srcoffset, srcval | mask); + break; + case 6: + store_data_long(srcoffset, srcval & ~mask); + break; + case 7: + store_data_long(srcoffset, srcval ^ mask); + break; + default: + break; + } + } else { + u16 srcval, mask; + u8 shift; + + srcoffset = decode_rm10_address(rl); + DECODE_PRINTF(","); + shift = fetch_byte_imm(); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + bit = shift & 0xF; + srcval = fetch_data_word(srcoffset); + mask = (0x1 << bit); + CONDITIONAL_SET_FLAG(srcval & mask,F_CF); + switch (rh) { + case 5: + store_data_word(srcoffset, srcval | mask); + break; + case 6: + store_data_word(srcoffset, srcval & ~mask); + break; + case 7: + store_data_word(srcoffset, srcval ^ mask); + break; + default: + break; + } + } + break; + case 3: /* register to register */ + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 *srcreg; + u32 mask; + u8 shift; + + srcreg = DECODE_RM_LONG_REGISTER(rl); + DECODE_PRINTF(","); + shift = fetch_byte_imm(); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + bit = shift & 0x1F; + mask = (0x1 << bit); + CONDITIONAL_SET_FLAG(*srcreg & mask,F_CF); + switch (rh) { + case 5: + *srcreg |= mask; + break; + case 6: + *srcreg &= ~mask; + break; + case 7: + *srcreg ^= mask; + break; + default: + break; + } + } else { + u16 *srcreg; + u16 mask; + u8 shift; + + srcreg = DECODE_RM_WORD_REGISTER(rl); + DECODE_PRINTF(","); + shift = fetch_byte_imm(); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + bit = shift & 0xF; + mask = (0x1 << bit); + CONDITIONAL_SET_FLAG(*srcreg & mask,F_CF); + switch (rh) { + case 5: + *srcreg |= mask; + break; + case 6: + *srcreg &= ~mask; + break; + case 7: + *srcreg ^= mask; + break; + default: + break; + } + } + break; + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x0f,0xbb +****************************************************************************/ +static void x86emuOp2_btc_R(u8 X86EMU_UNUSED(op2)) +{ + int mod, rl, rh; + uint srcoffset; + int bit,disp; + + START_OF_INSTR(); + DECODE_PRINTF("BTC\t"); + FETCH_DECODE_MODRM(mod, rh, rl); + switch (mod) { + case 0: + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 srcval,mask; + u32 *shiftreg; + + srcoffset = decode_rm00_address(rl); + DECODE_PRINTF(","); + shiftreg = DECODE_RM_LONG_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + bit = *shiftreg & 0x1F; + disp = (s16)*shiftreg >> 5; + srcval = fetch_data_long(srcoffset+disp); + mask = (0x1 << bit); + CONDITIONAL_SET_FLAG(srcval & mask,F_CF); + store_data_long(srcoffset+disp, srcval ^ mask); + } else { + u16 srcval,mask; + u16 *shiftreg; + + srcoffset = decode_rm00_address(rl); + DECODE_PRINTF(","); + shiftreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + bit = *shiftreg & 0xF; + disp = (s16)*shiftreg >> 4; + srcval = fetch_data_word(srcoffset+disp); + mask = (u16)(0x1 << bit); + CONDITIONAL_SET_FLAG(srcval & mask,F_CF); + store_data_word(srcoffset+disp, (u16)(srcval ^ mask)); + } + break; + case 1: + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 srcval,mask; + u32 *shiftreg; + + srcoffset = decode_rm01_address(rl); + DECODE_PRINTF(","); + shiftreg = DECODE_RM_LONG_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + bit = *shiftreg & 0x1F; + disp = (s16)*shiftreg >> 5; + srcval = fetch_data_long(srcoffset+disp); + mask = (0x1 << bit); + CONDITIONAL_SET_FLAG(srcval & mask,F_CF); + store_data_long(srcoffset+disp, srcval ^ mask); + } else { + u16 srcval,mask; + u16 *shiftreg; + + srcoffset = decode_rm01_address(rl); + DECODE_PRINTF(","); + shiftreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + bit = *shiftreg & 0xF; + disp = (s16)*shiftreg >> 4; + srcval = fetch_data_word(srcoffset+disp); + mask = (u16)(0x1 << bit); + CONDITIONAL_SET_FLAG(srcval & mask,F_CF); + store_data_word(srcoffset+disp, (u16)(srcval ^ mask)); + } + break; + case 2: + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 srcval,mask; + u32 *shiftreg; + + srcoffset = decode_rm10_address(rl); + DECODE_PRINTF(","); + shiftreg = DECODE_RM_LONG_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + bit = *shiftreg & 0x1F; + disp = (s16)*shiftreg >> 5; + srcval = fetch_data_long(srcoffset+disp); + mask = (0x1 << bit); + CONDITIONAL_SET_FLAG(srcval & mask,F_CF); + store_data_long(srcoffset+disp, srcval ^ mask); + } else { + u16 srcval,mask; + u16 *shiftreg; + + srcoffset = decode_rm10_address(rl); + DECODE_PRINTF(","); + shiftreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + bit = *shiftreg & 0xF; + disp = (s16)*shiftreg >> 4; + srcval = fetch_data_word(srcoffset+disp); + mask = (u16)(0x1 << bit); + CONDITIONAL_SET_FLAG(srcval & mask,F_CF); + store_data_word(srcoffset+disp, (u16)(srcval ^ mask)); + } + break; + case 3: /* register to register */ + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 *srcreg,*shiftreg; + u32 mask; + + srcreg = DECODE_RM_LONG_REGISTER(rl); + DECODE_PRINTF(","); + shiftreg = DECODE_RM_LONG_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + bit = *shiftreg & 0x1F; + mask = (0x1 << bit); + CONDITIONAL_SET_FLAG(*srcreg & mask,F_CF); + *srcreg ^= mask; + } else { + u16 *srcreg,*shiftreg; + u16 mask; + + srcreg = DECODE_RM_WORD_REGISTER(rl); + DECODE_PRINTF(","); + shiftreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + bit = *shiftreg & 0xF; + mask = (u16)(0x1 << bit); + CONDITIONAL_SET_FLAG(*srcreg & mask,F_CF); + *srcreg ^= mask; + } + break; + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x0f,0xbc +****************************************************************************/ +static void x86emuOp2_bsf(u8 X86EMU_UNUSED(op2)) +{ + int mod, rl, rh; + uint srcoffset; + + START_OF_INSTR(); + DECODE_PRINTF("BSF\t"); + FETCH_DECODE_MODRM(mod, rh, rl); + switch(mod) { + case 0: + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 srcval, *dstreg; + + srcoffset = decode_rm00_address(rl); + DECODE_PRINTF(","); + dstreg = DECODE_RM_LONG_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + srcval = fetch_data_long(srcoffset); + CONDITIONAL_SET_FLAG(srcval == 0, F_ZF); + for(*dstreg = 0; *dstreg < 32; (*dstreg)++) + if ((srcval >> *dstreg) & 1) break; + } else { + u16 srcval, *dstreg; + + srcoffset = decode_rm00_address(rl); + DECODE_PRINTF(","); + dstreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + srcval = fetch_data_word(srcoffset); + CONDITIONAL_SET_FLAG(srcval == 0, F_ZF); + for(*dstreg = 0; *dstreg < 16; (*dstreg)++) + if ((srcval >> *dstreg) & 1) break; + } + break; + case 1: + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 srcval, *dstreg; + + srcoffset = decode_rm01_address(rl); + DECODE_PRINTF(","); + dstreg = DECODE_RM_LONG_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + srcval = fetch_data_long(srcoffset); + CONDITIONAL_SET_FLAG(srcval == 0, F_ZF); + for(*dstreg = 0; *dstreg < 32; (*dstreg)++) + if ((srcval >> *dstreg) & 1) break; + } else { + u16 srcval, *dstreg; + + srcoffset = decode_rm01_address(rl); + DECODE_PRINTF(","); + dstreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + srcval = fetch_data_word(srcoffset); + CONDITIONAL_SET_FLAG(srcval == 0, F_ZF); + for(*dstreg = 0; *dstreg < 16; (*dstreg)++) + if ((srcval >> *dstreg) & 1) break; + } + break; + case 2: + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 srcval, *dstreg; + + srcoffset = decode_rm10_address(rl); + DECODE_PRINTF(","); + dstreg = DECODE_RM_LONG_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + srcval = fetch_data_long(srcoffset); + CONDITIONAL_SET_FLAG(srcval == 0, F_ZF); + for(*dstreg = 0; *dstreg < 32; (*dstreg)++) + if ((srcval >> *dstreg) & 1) break; + } else { + u16 srcval, *dstreg; + + srcoffset = decode_rm10_address(rl); + DECODE_PRINTF(","); + dstreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + srcval = fetch_data_word(srcoffset); + CONDITIONAL_SET_FLAG(srcval == 0, F_ZF); + for(*dstreg = 0; *dstreg < 16; (*dstreg)++) + if ((srcval >> *dstreg) & 1) break; + } + break; + case 3: /* register to register */ + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 srcval, *dstreg; + + srcval = *DECODE_RM_LONG_REGISTER(rl); + DECODE_PRINTF(","); + dstreg = DECODE_RM_LONG_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + CONDITIONAL_SET_FLAG(srcval == 0, F_ZF); + for(*dstreg = 0; *dstreg < 32; (*dstreg)++) + if ((srcval >> *dstreg) & 1) break; + } else { + u16 srcval, *dstreg; + + srcval = *DECODE_RM_WORD_REGISTER(rl); + DECODE_PRINTF(","); + dstreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + CONDITIONAL_SET_FLAG(srcval == 0, F_ZF); + for(*dstreg = 0; *dstreg < 16; (*dstreg)++) + if ((srcval >> *dstreg) & 1) break; + } + break; + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x0f,0xbd +****************************************************************************/ +static void x86emuOp2_bsr(u8 X86EMU_UNUSED(op2)) +{ + int mod, rl, rh; + uint srcoffset; + + START_OF_INSTR(); + DECODE_PRINTF("BSR\t"); + FETCH_DECODE_MODRM(mod, rh, rl); + switch(mod) { + case 0: + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 srcval, *dstreg; + + srcoffset = decode_rm00_address(rl); + DECODE_PRINTF(","); + dstreg = DECODE_RM_LONG_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + srcval = fetch_data_long(srcoffset); + CONDITIONAL_SET_FLAG(srcval == 0, F_ZF); + for(*dstreg = 31; *dstreg > 0; (*dstreg)--) + if ((srcval >> *dstreg) & 1) break; + } else { + u16 srcval, *dstreg; + + srcoffset = decode_rm00_address(rl); + DECODE_PRINTF(","); + dstreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + srcval = fetch_data_word(srcoffset); + CONDITIONAL_SET_FLAG(srcval == 0, F_ZF); + for(*dstreg = 15; *dstreg > 0; (*dstreg)--) + if ((srcval >> *dstreg) & 1) break; + } + break; + case 1: + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 srcval, *dstreg; + + srcoffset = decode_rm01_address(rl); + DECODE_PRINTF(","); + dstreg = DECODE_RM_LONG_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + srcval = fetch_data_long(srcoffset); + CONDITIONAL_SET_FLAG(srcval == 0, F_ZF); + for(*dstreg = 31; *dstreg > 0; (*dstreg)--) + if ((srcval >> *dstreg) & 1) break; + } else { + u16 srcval, *dstreg; + + srcoffset = decode_rm01_address(rl); + DECODE_PRINTF(","); + dstreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + srcval = fetch_data_word(srcoffset); + CONDITIONAL_SET_FLAG(srcval == 0, F_ZF); + for(*dstreg = 15; *dstreg > 0; (*dstreg)--) + if ((srcval >> *dstreg) & 1) break; + } + break; + case 2: + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 srcval, *dstreg; + + srcoffset = decode_rm10_address(rl); + DECODE_PRINTF(","); + dstreg = DECODE_RM_LONG_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + srcval = fetch_data_long(srcoffset); + CONDITIONAL_SET_FLAG(srcval == 0, F_ZF); + for(*dstreg = 31; *dstreg > 0; (*dstreg)--) + if ((srcval >> *dstreg) & 1) break; + } else { + u16 srcval, *dstreg; + + srcoffset = decode_rm10_address(rl); + DECODE_PRINTF(","); + dstreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + srcval = fetch_data_word(srcoffset); + CONDITIONAL_SET_FLAG(srcval == 0, F_ZF); + for(*dstreg = 15; *dstreg > 0; (*dstreg)--) + if ((srcval >> *dstreg) & 1) break; + } + break; + case 3: /* register to register */ + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 srcval, *dstreg; + + srcval = *DECODE_RM_LONG_REGISTER(rl); + DECODE_PRINTF(","); + dstreg = DECODE_RM_LONG_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + CONDITIONAL_SET_FLAG(srcval == 0, F_ZF); + for(*dstreg = 31; *dstreg > 0; (*dstreg)--) + if ((srcval >> *dstreg) & 1) break; + } else { + u16 srcval, *dstreg; + + srcval = *DECODE_RM_WORD_REGISTER(rl); + DECODE_PRINTF(","); + dstreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + CONDITIONAL_SET_FLAG(srcval == 0, F_ZF); + for(*dstreg = 15; *dstreg > 0; (*dstreg)--) + if ((srcval >> *dstreg) & 1) break; + } + break; + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x0f,0xbe +****************************************************************************/ +static void x86emuOp2_movsx_byte_R_RM(u8 X86EMU_UNUSED(op2)) +{ + int mod, rl, rh; + uint srcoffset; + + START_OF_INSTR(); + DECODE_PRINTF("MOVSX\t"); + FETCH_DECODE_MODRM(mod, rh, rl); + switch (mod) { + case 0: + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 *destreg; + u32 srcval; + + destreg = DECODE_RM_LONG_REGISTER(rh); + DECODE_PRINTF(","); + srcoffset = decode_rm00_address(rl); + srcval = (s32)((s8)fetch_data_byte(srcoffset)); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = srcval; + } else { + u16 *destreg; + u16 srcval; + + destreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF(","); + srcoffset = decode_rm00_address(rl); + srcval = (s16)((s8)fetch_data_byte(srcoffset)); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = srcval; + } + break; + case 1: + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 *destreg; + u32 srcval; + + destreg = DECODE_RM_LONG_REGISTER(rh); + DECODE_PRINTF(","); + srcoffset = decode_rm01_address(rl); + srcval = (s32)((s8)fetch_data_byte(srcoffset)); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = srcval; + } else { + u16 *destreg; + u16 srcval; + + destreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF(","); + srcoffset = decode_rm01_address(rl); + srcval = (s16)((s8)fetch_data_byte(srcoffset)); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = srcval; + } + break; + case 2: + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 *destreg; + u32 srcval; + + destreg = DECODE_RM_LONG_REGISTER(rh); + DECODE_PRINTF(","); + srcoffset = decode_rm10_address(rl); + srcval = (s32)((s8)fetch_data_byte(srcoffset)); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = srcval; + } else { + u16 *destreg; + u16 srcval; + + destreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF(","); + srcoffset = decode_rm10_address(rl); + srcval = (s16)((s8)fetch_data_byte(srcoffset)); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = srcval; + } + break; + case 3: /* register to register */ + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 *destreg; + u8 *srcreg; + + destreg = DECODE_RM_LONG_REGISTER(rh); + DECODE_PRINTF(","); + srcreg = DECODE_RM_BYTE_REGISTER(rl); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = (s32)((s8)*srcreg); + } else { + u16 *destreg; + u8 *srcreg; + + destreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF(","); + srcreg = DECODE_RM_BYTE_REGISTER(rl); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = (s16)((s8)*srcreg); + } + break; + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x0f,0xbf +****************************************************************************/ +static void x86emuOp2_movsx_word_R_RM(u8 X86EMU_UNUSED(op2)) +{ + int mod, rl, rh; + uint srcoffset; + u32 *destreg; + u32 srcval; + u16 *srcreg; + + START_OF_INSTR(); + DECODE_PRINTF("MOVSX\t"); + FETCH_DECODE_MODRM(mod, rh, rl); + switch (mod) { + case 0: + destreg = DECODE_RM_LONG_REGISTER(rh); + DECODE_PRINTF(","); + srcoffset = decode_rm00_address(rl); + srcval = (s32)((s16)fetch_data_word(srcoffset)); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = srcval; + break; + case 1: + destreg = DECODE_RM_LONG_REGISTER(rh); + DECODE_PRINTF(","); + srcoffset = decode_rm01_address(rl); + srcval = (s32)((s16)fetch_data_word(srcoffset)); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = srcval; + break; + case 2: + destreg = DECODE_RM_LONG_REGISTER(rh); + DECODE_PRINTF(","); + srcoffset = decode_rm10_address(rl); + srcval = (s32)((s16)fetch_data_word(srcoffset)); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = srcval; + break; + case 3: /* register to register */ + destreg = DECODE_RM_LONG_REGISTER(rh); + DECODE_PRINTF(","); + srcreg = DECODE_RM_WORD_REGISTER(rl); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = (s32)((s16)*srcreg); + break; + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/*************************************************************************** + * Double byte operation code table: + **************************************************************************/ +void (*x86emu_optab2[256])(u8) = +{ +/* 0x00 */ x86emuOp2_illegal_op, /* Group F (ring 0 PM) */ +/* 0x01 */ x86emuOp2_illegal_op, /* Group G (ring 0 PM) */ +/* 0x02 */ x86emuOp2_illegal_op, /* lar (ring 0 PM) */ +/* 0x03 */ x86emuOp2_illegal_op, /* lsl (ring 0 PM) */ +/* 0x04 */ x86emuOp2_illegal_op, +/* 0x05 */ x86emuOp2_illegal_op, /* loadall (undocumented) */ +/* 0x06 */ x86emuOp2_illegal_op, /* clts (ring 0 PM) */ +/* 0x07 */ x86emuOp2_illegal_op, /* loadall (undocumented) */ +/* 0x08 */ x86emuOp2_illegal_op, /* invd (ring 0 PM) */ +/* 0x09 */ x86emuOp2_illegal_op, /* wbinvd (ring 0 PM) */ +/* 0x0a */ x86emuOp2_illegal_op, +/* 0x0b */ x86emuOp2_illegal_op, +/* 0x0c */ x86emuOp2_illegal_op, +/* 0x0d */ x86emuOp2_illegal_op, +/* 0x0e */ x86emuOp2_illegal_op, +/* 0x0f */ x86emuOp2_illegal_op, + +/* 0x10 */ x86emuOp2_illegal_op, +/* 0x11 */ x86emuOp2_illegal_op, +/* 0x12 */ x86emuOp2_illegal_op, +/* 0x13 */ x86emuOp2_illegal_op, +/* 0x14 */ x86emuOp2_illegal_op, +/* 0x15 */ x86emuOp2_illegal_op, +/* 0x16 */ x86emuOp2_illegal_op, +/* 0x17 */ x86emuOp2_illegal_op, +/* 0x18 */ x86emuOp2_illegal_op, +/* 0x19 */ x86emuOp2_illegal_op, +/* 0x1a */ x86emuOp2_illegal_op, +/* 0x1b */ x86emuOp2_illegal_op, +/* 0x1c */ x86emuOp2_illegal_op, +/* 0x1d */ x86emuOp2_illegal_op, +/* 0x1e */ x86emuOp2_illegal_op, +/* 0x1f */ x86emuOp2_illegal_op, + +/* 0x20 */ x86emuOp2_illegal_op, /* mov reg32,creg (ring 0 PM) */ +/* 0x21 */ x86emuOp2_illegal_op, /* mov reg32,dreg (ring 0 PM) */ +/* 0x22 */ x86emuOp2_illegal_op, /* mov creg,reg32 (ring 0 PM) */ +/* 0x23 */ x86emuOp2_illegal_op, /* mov dreg,reg32 (ring 0 PM) */ +/* 0x24 */ x86emuOp2_illegal_op, /* mov reg32,treg (ring 0 PM) */ +/* 0x25 */ x86emuOp2_illegal_op, +/* 0x26 */ x86emuOp2_illegal_op, /* mov treg,reg32 (ring 0 PM) */ +/* 0x27 */ x86emuOp2_illegal_op, +/* 0x28 */ x86emuOp2_illegal_op, +/* 0x29 */ x86emuOp2_illegal_op, +/* 0x2a */ x86emuOp2_illegal_op, +/* 0x2b */ x86emuOp2_illegal_op, +/* 0x2c */ x86emuOp2_illegal_op, +/* 0x2d */ x86emuOp2_illegal_op, +/* 0x2e */ x86emuOp2_illegal_op, +/* 0x2f */ x86emuOp2_illegal_op, + +/* 0x30 */ x86emuOp2_illegal_op, +/* 0x31 */ x86emuOp2_illegal_op, +/* 0x32 */ x86emuOp2_illegal_op, +/* 0x33 */ x86emuOp2_illegal_op, +/* 0x34 */ x86emuOp2_illegal_op, +/* 0x35 */ x86emuOp2_illegal_op, +/* 0x36 */ x86emuOp2_illegal_op, +/* 0x37 */ x86emuOp2_illegal_op, +/* 0x38 */ x86emuOp2_illegal_op, +/* 0x39 */ x86emuOp2_illegal_op, +/* 0x3a */ x86emuOp2_illegal_op, +/* 0x3b */ x86emuOp2_illegal_op, +/* 0x3c */ x86emuOp2_illegal_op, +/* 0x3d */ x86emuOp2_illegal_op, +/* 0x3e */ x86emuOp2_illegal_op, +/* 0x3f */ x86emuOp2_illegal_op, + +/* 0x40 */ x86emuOp2_illegal_op, +/* 0x41 */ x86emuOp2_illegal_op, +/* 0x42 */ x86emuOp2_illegal_op, +/* 0x43 */ x86emuOp2_illegal_op, +/* 0x44 */ x86emuOp2_illegal_op, +/* 0x45 */ x86emuOp2_illegal_op, +/* 0x46 */ x86emuOp2_illegal_op, +/* 0x47 */ x86emuOp2_illegal_op, +/* 0x48 */ x86emuOp2_illegal_op, +/* 0x49 */ x86emuOp2_illegal_op, +/* 0x4a */ x86emuOp2_illegal_op, +/* 0x4b */ x86emuOp2_illegal_op, +/* 0x4c */ x86emuOp2_illegal_op, +/* 0x4d */ x86emuOp2_illegal_op, +/* 0x4e */ x86emuOp2_illegal_op, +/* 0x4f */ x86emuOp2_illegal_op, + +/* 0x50 */ x86emuOp2_illegal_op, +/* 0x51 */ x86emuOp2_illegal_op, +/* 0x52 */ x86emuOp2_illegal_op, +/* 0x53 */ x86emuOp2_illegal_op, +/* 0x54 */ x86emuOp2_illegal_op, +/* 0x55 */ x86emuOp2_illegal_op, +/* 0x56 */ x86emuOp2_illegal_op, +/* 0x57 */ x86emuOp2_illegal_op, +/* 0x58 */ x86emuOp2_illegal_op, +/* 0x59 */ x86emuOp2_illegal_op, +/* 0x5a */ x86emuOp2_illegal_op, +/* 0x5b */ x86emuOp2_illegal_op, +/* 0x5c */ x86emuOp2_illegal_op, +/* 0x5d */ x86emuOp2_illegal_op, +/* 0x5e */ x86emuOp2_illegal_op, +/* 0x5f */ x86emuOp2_illegal_op, + +/* 0x60 */ x86emuOp2_illegal_op, +/* 0x61 */ x86emuOp2_illegal_op, +/* 0x62 */ x86emuOp2_illegal_op, +/* 0x63 */ x86emuOp2_illegal_op, +/* 0x64 */ x86emuOp2_illegal_op, +/* 0x65 */ x86emuOp2_illegal_op, +/* 0x66 */ x86emuOp2_illegal_op, +/* 0x67 */ x86emuOp2_illegal_op, +/* 0x68 */ x86emuOp2_illegal_op, +/* 0x69 */ x86emuOp2_illegal_op, +/* 0x6a */ x86emuOp2_illegal_op, +/* 0x6b */ x86emuOp2_illegal_op, +/* 0x6c */ x86emuOp2_illegal_op, +/* 0x6d */ x86emuOp2_illegal_op, +/* 0x6e */ x86emuOp2_illegal_op, +/* 0x6f */ x86emuOp2_illegal_op, + +/* 0x70 */ x86emuOp2_illegal_op, +/* 0x71 */ x86emuOp2_illegal_op, +/* 0x72 */ x86emuOp2_illegal_op, +/* 0x73 */ x86emuOp2_illegal_op, +/* 0x74 */ x86emuOp2_illegal_op, +/* 0x75 */ x86emuOp2_illegal_op, +/* 0x76 */ x86emuOp2_illegal_op, +/* 0x77 */ x86emuOp2_illegal_op, +/* 0x78 */ x86emuOp2_illegal_op, +/* 0x79 */ x86emuOp2_illegal_op, +/* 0x7a */ x86emuOp2_illegal_op, +/* 0x7b */ x86emuOp2_illegal_op, +/* 0x7c */ x86emuOp2_illegal_op, +/* 0x7d */ x86emuOp2_illegal_op, +/* 0x7e */ x86emuOp2_illegal_op, +/* 0x7f */ x86emuOp2_illegal_op, + +/* 0x80 */ x86emuOp2_long_jump, +/* 0x81 */ x86emuOp2_long_jump, +/* 0x82 */ x86emuOp2_long_jump, +/* 0x83 */ x86emuOp2_long_jump, +/* 0x84 */ x86emuOp2_long_jump, +/* 0x85 */ x86emuOp2_long_jump, +/* 0x86 */ x86emuOp2_long_jump, +/* 0x87 */ x86emuOp2_long_jump, +/* 0x88 */ x86emuOp2_long_jump, +/* 0x89 */ x86emuOp2_long_jump, +/* 0x8a */ x86emuOp2_long_jump, +/* 0x8b */ x86emuOp2_long_jump, +/* 0x8c */ x86emuOp2_long_jump, +/* 0x8d */ x86emuOp2_long_jump, +/* 0x8e */ x86emuOp2_long_jump, +/* 0x8f */ x86emuOp2_long_jump, + +/* 0x90 */ x86emuOp2_set_byte, +/* 0x91 */ x86emuOp2_set_byte, +/* 0x92 */ x86emuOp2_set_byte, +/* 0x93 */ x86emuOp2_set_byte, +/* 0x94 */ x86emuOp2_set_byte, +/* 0x95 */ x86emuOp2_set_byte, +/* 0x96 */ x86emuOp2_set_byte, +/* 0x97 */ x86emuOp2_set_byte, +/* 0x98 */ x86emuOp2_set_byte, +/* 0x99 */ x86emuOp2_set_byte, +/* 0x9a */ x86emuOp2_set_byte, +/* 0x9b */ x86emuOp2_set_byte, +/* 0x9c */ x86emuOp2_set_byte, +/* 0x9d */ x86emuOp2_set_byte, +/* 0x9e */ x86emuOp2_set_byte, +/* 0x9f */ x86emuOp2_set_byte, + +/* 0xa0 */ x86emuOp2_push_FS, +/* 0xa1 */ x86emuOp2_pop_FS, +/* 0xa2 */ x86emuOp2_illegal_op, +/* 0xa3 */ x86emuOp2_bt_R, +/* 0xa4 */ x86emuOp2_shld_IMM, +/* 0xa5 */ x86emuOp2_shld_CL, +/* 0xa6 */ x86emuOp2_illegal_op, +/* 0xa7 */ x86emuOp2_illegal_op, +/* 0xa8 */ x86emuOp2_push_GS, +/* 0xa9 */ x86emuOp2_pop_GS, +/* 0xaa */ x86emuOp2_illegal_op, +/* 0xab */ x86emuOp2_bts_R, +/* 0xac */ x86emuOp2_shrd_IMM, +/* 0xad */ x86emuOp2_shrd_CL, +/* 0xae */ x86emuOp2_illegal_op, +/* 0xaf */ x86emuOp2_imul_R_RM, + +/* 0xb0 */ x86emuOp2_illegal_op, /* TODO: cmpxchg */ +/* 0xb1 */ x86emuOp2_illegal_op, /* TODO: cmpxchg */ +/* 0xb2 */ x86emuOp2_lss_R_IMM, +/* 0xb3 */ x86emuOp2_btr_R, +/* 0xb4 */ x86emuOp2_lfs_R_IMM, +/* 0xb5 */ x86emuOp2_lgs_R_IMM, +/* 0xb6 */ x86emuOp2_movzx_byte_R_RM, +/* 0xb7 */ x86emuOp2_movzx_word_R_RM, +/* 0xb8 */ x86emuOp2_illegal_op, +/* 0xb9 */ x86emuOp2_illegal_op, +/* 0xba */ x86emuOp2_btX_I, +/* 0xbb */ x86emuOp2_btc_R, +/* 0xbc */ x86emuOp2_bsf, +/* 0xbd */ x86emuOp2_bsr, +/* 0xbe */ x86emuOp2_movsx_byte_R_RM, +/* 0xbf */ x86emuOp2_movsx_word_R_RM, + +/* 0xc0 */ x86emuOp2_illegal_op, /* TODO: xadd */ +/* 0xc1 */ x86emuOp2_illegal_op, /* TODO: xadd */ +/* 0xc2 */ x86emuOp2_illegal_op, +/* 0xc3 */ x86emuOp2_illegal_op, +/* 0xc4 */ x86emuOp2_illegal_op, +/* 0xc5 */ x86emuOp2_illegal_op, +/* 0xc6 */ x86emuOp2_illegal_op, +/* 0xc7 */ x86emuOp2_illegal_op, +/* 0xc8 */ x86emuOp2_illegal_op, /* TODO: bswap */ +/* 0xc9 */ x86emuOp2_illegal_op, /* TODO: bswap */ +/* 0xca */ x86emuOp2_illegal_op, /* TODO: bswap */ +/* 0xcb */ x86emuOp2_illegal_op, /* TODO: bswap */ +/* 0xcc */ x86emuOp2_illegal_op, /* TODO: bswap */ +/* 0xcd */ x86emuOp2_illegal_op, /* TODO: bswap */ +/* 0xce */ x86emuOp2_illegal_op, /* TODO: bswap */ +/* 0xcf */ x86emuOp2_illegal_op, /* TODO: bswap */ + +/* 0xd0 */ x86emuOp2_illegal_op, +/* 0xd1 */ x86emuOp2_illegal_op, +/* 0xd2 */ x86emuOp2_illegal_op, +/* 0xd3 */ x86emuOp2_illegal_op, +/* 0xd4 */ x86emuOp2_illegal_op, +/* 0xd5 */ x86emuOp2_illegal_op, +/* 0xd6 */ x86emuOp2_illegal_op, +/* 0xd7 */ x86emuOp2_illegal_op, +/* 0xd8 */ x86emuOp2_illegal_op, +/* 0xd9 */ x86emuOp2_illegal_op, +/* 0xda */ x86emuOp2_illegal_op, +/* 0xdb */ x86emuOp2_illegal_op, +/* 0xdc */ x86emuOp2_illegal_op, +/* 0xdd */ x86emuOp2_illegal_op, +/* 0xde */ x86emuOp2_illegal_op, +/* 0xdf */ x86emuOp2_illegal_op, + +/* 0xe0 */ x86emuOp2_illegal_op, +/* 0xe1 */ x86emuOp2_illegal_op, +/* 0xe2 */ x86emuOp2_illegal_op, +/* 0xe3 */ x86emuOp2_illegal_op, +/* 0xe4 */ x86emuOp2_illegal_op, +/* 0xe5 */ x86emuOp2_illegal_op, +/* 0xe6 */ x86emuOp2_illegal_op, +/* 0xe7 */ x86emuOp2_illegal_op, +/* 0xe8 */ x86emuOp2_illegal_op, +/* 0xe9 */ x86emuOp2_illegal_op, +/* 0xea */ x86emuOp2_illegal_op, +/* 0xeb */ x86emuOp2_illegal_op, +/* 0xec */ x86emuOp2_illegal_op, +/* 0xed */ x86emuOp2_illegal_op, +/* 0xee */ x86emuOp2_illegal_op, +/* 0xef */ x86emuOp2_illegal_op, + +/* 0xf0 */ x86emuOp2_illegal_op, +/* 0xf1 */ x86emuOp2_illegal_op, +/* 0xf2 */ x86emuOp2_illegal_op, +/* 0xf3 */ x86emuOp2_illegal_op, +/* 0xf4 */ x86emuOp2_illegal_op, +/* 0xf5 */ x86emuOp2_illegal_op, +/* 0xf6 */ x86emuOp2_illegal_op, +/* 0xf7 */ x86emuOp2_illegal_op, +/* 0xf8 */ x86emuOp2_illegal_op, +/* 0xf9 */ x86emuOp2_illegal_op, +/* 0xfa */ x86emuOp2_illegal_op, +/* 0xfb */ x86emuOp2_illegal_op, +/* 0xfc */ x86emuOp2_illegal_op, +/* 0xfd */ x86emuOp2_illegal_op, +/* 0xfe */ x86emuOp2_illegal_op, +/* 0xff */ x86emuOp2_illegal_op, +}; diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/arch/nvalloc/unix/x86emu/prim_ops.c nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/arch/nvalloc/unix/x86emu/prim_ops.c --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/arch/nvalloc/unix/x86emu/prim_ops.c 1970-01-01 00:00:00.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/arch/nvalloc/unix/x86emu/prim_ops.c 2024-03-05 22:12:51.000000000 +0000 @@ -0,0 +1,2655 @@ +/**************************************************************************** +* +* Realmode X86 Emulator Library +* +* Copyright (C) 1996-1999 SciTech Software, Inc. +* Copyright (C) David Mosberger-Tang +* Copyright (C) 1999 Egbert Eich +* +* ======================================================================== +* +* Permission to use, copy, modify, distribute, and sell this software and +* its documentation for any purpose is hereby granted without fee, +* provided that the above copyright notice appear in all copies and that +* both that copyright notice and this permission notice appear in +* supporting documentation, and that the name of the authors not be used +* in advertising or publicity pertaining to distribution of the software +* without specific, written prior permission. The authors makes no +* representations about the suitability of this software for any purpose. +* It is provided "as is" without express or implied warranty. +* +* THE AUTHORS DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOFTWARE, +* INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO +* EVENT SHALL THE AUTHORS BE LIABLE FOR ANY SPECIAL, INDIRECT OR +* CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF +* USE, DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR +* OTHER TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR +* PERFORMANCE OF THIS SOFTWARE. +* +* ======================================================================== +* +* Language: ANSI C +* Environment: Any +* Developer: Kendall Bennett +* +* Description: This file contains the code to implement the primitive +* machine operations used by the emulation code in ops.c +* +* Carry Chain Calculation +* +* This represents a somewhat expensive calculation which is +* apparently required to emulate the setting of the OF and AF flag. +* The latter is not so important, but the former is. The overflow +* flag is the XOR of the top two bits of the carry chain for an +* addition (similar for subtraction). Since we do not want to +* simulate the addition in a bitwise manner, we try to calculate the +* carry chain given the two operands and the result. +* +* So, given the following table, which represents the addition of two +* bits, we can derive a formula for the carry chain. +* +* a b cin r cout +* 0 0 0 0 0 +* 0 0 1 1 0 +* 0 1 0 1 0 +* 0 1 1 0 1 +* 1 0 0 1 0 +* 1 0 1 0 1 +* 1 1 0 0 1 +* 1 1 1 1 1 +* +* Construction of table for cout: +* +* ab +* r \ 00 01 11 10 +* |------------------ +* 0 | 0 1 1 1 +* 1 | 0 0 1 0 +* +* By inspection, one gets: cc = ab + r'(a + b) +* +* That represents alot of operations, but NO CHOICE.... +* +* Borrow Chain Calculation. +* +* The following table represents the subtraction of two bits, from +* which we can derive a formula for the borrow chain. +* +* a b bin r bout +* 0 0 0 0 0 +* 0 0 1 1 1 +* 0 1 0 1 1 +* 0 1 1 0 1 +* 1 0 0 1 0 +* 1 0 1 0 0 +* 1 1 0 0 0 +* 1 1 1 1 1 +* +* Construction of table for cout: +* +* ab +* r \ 00 01 11 10 +* |------------------ +* 0 | 0 1 0 0 +* 1 | 1 1 1 0 +* +* By inspection, one gets: bc = a'b + r(a' + b) +* +****************************************************************************/ + +#define PRIM_OPS_NO_REDEFINE_ASM +#include "x86emu/x86emui.h" + +/*------------------------- Global Variables ------------------------------*/ + +static u32 x86emu_parity_tab[8] = +{ + 0x96696996, + 0x69969669, + 0x69969669, + 0x96696996, + 0x69969669, + 0x96696996, + 0x96696996, + 0x69969669, +}; + +#define PARITY(x) (((x86emu_parity_tab[(x) / 32] >> ((x) % 32)) & 1) == 0) +#define XOR2(x) (((x) ^ ((x)>>1)) & 0x1) + +/*----------------------------- Implementation ----------------------------*/ + +/**************************************************************************** +REMARKS: +Implements the AAA instruction and side effects. +****************************************************************************/ +u16 aaa_word(u16 d) +{ + u16 res; + if ((d & 0xf) > 0x9 || ACCESS_FLAG(F_AF)) { + d += 0x6; + d += 0x100; + SET_FLAG(F_AF); + SET_FLAG(F_CF); + } else { + CLEAR_FLAG(F_CF); + CLEAR_FLAG(F_AF); + } + res = (u16)(d & 0xFF0F); + CLEAR_FLAG(F_SF); + CONDITIONAL_SET_FLAG(res == 0, F_ZF); + CONDITIONAL_SET_FLAG(PARITY(res & 0xff), F_PF); + return res; +} + +/**************************************************************************** +REMARKS: +Implements the AAA instruction and side effects. +****************************************************************************/ +u16 aas_word(u16 d) +{ + u16 res; + if ((d & 0xf) > 0x9 || ACCESS_FLAG(F_AF)) { + d -= 0x6; + d -= 0x100; + SET_FLAG(F_AF); + SET_FLAG(F_CF); + } else { + CLEAR_FLAG(F_CF); + CLEAR_FLAG(F_AF); + } + res = (u16)(d & 0xFF0F); + CLEAR_FLAG(F_SF); + CONDITIONAL_SET_FLAG(res == 0, F_ZF); + CONDITIONAL_SET_FLAG(PARITY(res & 0xff), F_PF); + return res; +} + +/**************************************************************************** +REMARKS: +Implements the AAD instruction and side effects. +****************************************************************************/ +u16 aad_word(u16 d) +{ + u16 l; + u8 hb, lb; + + hb = (u8)((d >> 8) & 0xff); + lb = (u8)((d & 0xff)); + l = (u16)((lb + 10 * hb) & 0xFF); + + CLEAR_FLAG(F_CF); + CLEAR_FLAG(F_AF); + CLEAR_FLAG(F_OF); + CONDITIONAL_SET_FLAG(l & 0x80, F_SF); + CONDITIONAL_SET_FLAG(l == 0, F_ZF); + CONDITIONAL_SET_FLAG(PARITY(l & 0xff), F_PF); + return l; +} + +/**************************************************************************** +REMARKS: +Implements the AAM instruction and side effects. +****************************************************************************/ +u16 aam_word(u8 d) +{ + u16 h, l; + + h = (u16)(d / 10); + l = (u16)(d % 10); + l |= (u16)(h << 8); + + CLEAR_FLAG(F_CF); + CLEAR_FLAG(F_AF); + CLEAR_FLAG(F_OF); + CONDITIONAL_SET_FLAG(l & 0x80, F_SF); + CONDITIONAL_SET_FLAG(l == 0, F_ZF); + CONDITIONAL_SET_FLAG(PARITY(l & 0xff), F_PF); + return l; +} + +/**************************************************************************** +REMARKS: +Implements the ADC instruction and side effects. +****************************************************************************/ +u8 adc_byte(u8 d, u8 s) +{ + register u32 res; /* all operands in native machine order */ + register u32 cc; + + if (ACCESS_FLAG(F_CF)) + res = 1 + d + s; + else + res = d + s; + + CONDITIONAL_SET_FLAG(res & 0x100, F_CF); + CONDITIONAL_SET_FLAG((res & 0xff) == 0, F_ZF); + CONDITIONAL_SET_FLAG(res & 0x80, F_SF); + CONDITIONAL_SET_FLAG(PARITY(res & 0xff), F_PF); + + /* calculate the carry chain SEE NOTE AT TOP. */ + cc = (s & d) | ((~res) & (s | d)); + CONDITIONAL_SET_FLAG(XOR2(cc >> 6), F_OF); + CONDITIONAL_SET_FLAG(cc & 0x8, F_AF); + return (u8)res; +} + +/**************************************************************************** +REMARKS: +Implements the ADC instruction and side effects. +****************************************************************************/ +u16 adc_word(u16 d, u16 s) +{ + register u32 res; /* all operands in native machine order */ + register u32 cc; + + if (ACCESS_FLAG(F_CF)) + res = 1 + d + s; + else + res = d + s; + + CONDITIONAL_SET_FLAG(res & 0x10000, F_CF); + CONDITIONAL_SET_FLAG((res & 0xffff) == 0, F_ZF); + CONDITIONAL_SET_FLAG(res & 0x8000, F_SF); + CONDITIONAL_SET_FLAG(PARITY(res & 0xff), F_PF); + + /* calculate the carry chain SEE NOTE AT TOP. */ + cc = (s & d) | ((~res) & (s | d)); + CONDITIONAL_SET_FLAG(XOR2(cc >> 14), F_OF); + CONDITIONAL_SET_FLAG(cc & 0x8, F_AF); + return (u16)res; +} + +/**************************************************************************** +REMARKS: +Implements the ADC instruction and side effects. +****************************************************************************/ +u32 adc_long(u32 d, u32 s) +{ + register u32 lo; /* all operands in native machine order */ + register u32 hi; + register u32 res; + register u32 cc; + + if (ACCESS_FLAG(F_CF)) { + lo = 1 + (d & 0xFFFF) + (s & 0xFFFF); + res = 1 + d + s; + } + else { + lo = (d & 0xFFFF) + (s & 0xFFFF); + res = d + s; + } + hi = (lo >> 16) + (d >> 16) + (s >> 16); + + CONDITIONAL_SET_FLAG(hi & 0x10000, F_CF); + CONDITIONAL_SET_FLAG((res & 0xffffffff) == 0, F_ZF); + CONDITIONAL_SET_FLAG(res & 0x80000000, F_SF); + CONDITIONAL_SET_FLAG(PARITY(res & 0xff), F_PF); + + /* calculate the carry chain SEE NOTE AT TOP. */ + cc = (s & d) | ((~res) & (s | d)); + CONDITIONAL_SET_FLAG(XOR2(cc >> 30), F_OF); + CONDITIONAL_SET_FLAG(cc & 0x8, F_AF); + return res; +} + +/**************************************************************************** +REMARKS: +Implements the ADD instruction and side effects. +****************************************************************************/ +u8 add_byte(u8 d, u8 s) +{ + register u32 res; /* all operands in native machine order */ + register u32 cc; + + res = d + s; + CONDITIONAL_SET_FLAG(res & 0x100, F_CF); + CONDITIONAL_SET_FLAG((res & 0xff) == 0, F_ZF); + CONDITIONAL_SET_FLAG(res & 0x80, F_SF); + CONDITIONAL_SET_FLAG(PARITY(res & 0xff), F_PF); + + /* calculate the carry chain SEE NOTE AT TOP. */ + cc = (s & d) | ((~res) & (s | d)); + CONDITIONAL_SET_FLAG(XOR2(cc >> 6), F_OF); + CONDITIONAL_SET_FLAG(cc & 0x8, F_AF); + return (u8)res; +} + +/**************************************************************************** +REMARKS: +Implements the ADD instruction and side effects. +****************************************************************************/ +u16 add_word(u16 d, u16 s) +{ + register u32 res; /* all operands in native machine order */ + register u32 cc; + + res = d + s; + CONDITIONAL_SET_FLAG(res & 0x10000, F_CF); + CONDITIONAL_SET_FLAG((res & 0xffff) == 0, F_ZF); + CONDITIONAL_SET_FLAG(res & 0x8000, F_SF); + CONDITIONAL_SET_FLAG(PARITY(res & 0xff), F_PF); + + /* calculate the carry chain SEE NOTE AT TOP. */ + cc = (s & d) | ((~res) & (s | d)); + CONDITIONAL_SET_FLAG(XOR2(cc >> 14), F_OF); + CONDITIONAL_SET_FLAG(cc & 0x8, F_AF); + return (u16)res; +} + +/**************************************************************************** +REMARKS: +Implements the ADD instruction and side effects. +****************************************************************************/ +u32 add_long(u32 d, u32 s) +{ + register u32 lo; /* all operands in native machine order */ + register u32 hi; + register u32 res; + register u32 cc; + + lo = (d & 0xFFFF) + (s & 0xFFFF); + res = d + s; + hi = (lo >> 16) + (d >> 16) + (s >> 16); + + CONDITIONAL_SET_FLAG(hi & 0x10000, F_CF); + CONDITIONAL_SET_FLAG((res & 0xffffffff) == 0, F_ZF); + CONDITIONAL_SET_FLAG(res & 0x80000000, F_SF); + CONDITIONAL_SET_FLAG(PARITY(res & 0xff), F_PF); + + /* calculate the carry chain SEE NOTE AT TOP. */ + cc = (s & d) | ((~res) & (s | d)); + CONDITIONAL_SET_FLAG(XOR2(cc >> 30), F_OF); + CONDITIONAL_SET_FLAG(cc & 0x8, F_AF); + + return res; +} + +/**************************************************************************** +REMARKS: +Implements the AND instruction and side effects. +****************************************************************************/ +u8 and_byte(u8 d, u8 s) +{ + register u8 res; /* all operands in native machine order */ + + res = d & s; + + /* set the flags */ + CLEAR_FLAG(F_OF); + CLEAR_FLAG(F_CF); + CLEAR_FLAG(F_AF); + CONDITIONAL_SET_FLAG(res & 0x80, F_SF); + CONDITIONAL_SET_FLAG(res == 0, F_ZF); + CONDITIONAL_SET_FLAG(PARITY(res), F_PF); + return res; +} + +/**************************************************************************** +REMARKS: +Implements the AND instruction and side effects. +****************************************************************************/ +u16 and_word(u16 d, u16 s) +{ + register u16 res; /* all operands in native machine order */ + + res = d & s; + + /* set the flags */ + CLEAR_FLAG(F_OF); + CLEAR_FLAG(F_CF); + CLEAR_FLAG(F_AF); + CONDITIONAL_SET_FLAG(res & 0x8000, F_SF); + CONDITIONAL_SET_FLAG(res == 0, F_ZF); + CONDITIONAL_SET_FLAG(PARITY(res & 0xff), F_PF); + return res; +} + +/**************************************************************************** +REMARKS: +Implements the AND instruction and side effects. +****************************************************************************/ +u32 and_long(u32 d, u32 s) +{ + register u32 res; /* all operands in native machine order */ + + res = d & s; + + /* set the flags */ + CLEAR_FLAG(F_OF); + CLEAR_FLAG(F_CF); + CLEAR_FLAG(F_AF); + CONDITIONAL_SET_FLAG(res & 0x80000000, F_SF); + CONDITIONAL_SET_FLAG(res == 0, F_ZF); + CONDITIONAL_SET_FLAG(PARITY(res & 0xff), F_PF); + return res; +} + +/**************************************************************************** +REMARKS: +Implements the CMP instruction and side effects. +****************************************************************************/ +u8 cmp_byte(u8 d, u8 s) +{ + register u32 res; /* all operands in native machine order */ + register u32 bc; + + res = d - s; + CLEAR_FLAG(F_CF); + CONDITIONAL_SET_FLAG(res & 0x80, F_SF); + CONDITIONAL_SET_FLAG((res & 0xff) == 0, F_ZF); + CONDITIONAL_SET_FLAG(PARITY(res & 0xff), F_PF); + + /* calculate the borrow chain. See note at top */ + bc = (res & (~d | s)) | (~d & s); + CONDITIONAL_SET_FLAG(bc & 0x80, F_CF); + CONDITIONAL_SET_FLAG(XOR2(bc >> 6), F_OF); + CONDITIONAL_SET_FLAG(bc & 0x8, F_AF); + return d; +} + +/**************************************************************************** +REMARKS: +Implements the CMP instruction and side effects. +****************************************************************************/ +u16 cmp_word(u16 d, u16 s) +{ + register u32 res; /* all operands in native machine order */ + register u32 bc; + + res = d - s; + CONDITIONAL_SET_FLAG(res & 0x8000, F_SF); + CONDITIONAL_SET_FLAG((res & 0xffff) == 0, F_ZF); + CONDITIONAL_SET_FLAG(PARITY(res & 0xff), F_PF); + + /* calculate the borrow chain. See note at top */ + bc = (res & (~d | s)) | (~d & s); + CONDITIONAL_SET_FLAG(bc & 0x8000, F_CF); + CONDITIONAL_SET_FLAG(XOR2(bc >> 14), F_OF); + CONDITIONAL_SET_FLAG(bc & 0x8, F_AF); + return d; +} + +/**************************************************************************** +REMARKS: +Implements the CMP instruction and side effects. +****************************************************************************/ +u32 cmp_long(u32 d, u32 s) +{ + register u32 res; /* all operands in native machine order */ + register u32 bc; + + res = d - s; + CONDITIONAL_SET_FLAG(res & 0x80000000, F_SF); + CONDITIONAL_SET_FLAG((res & 0xffffffff) == 0, F_ZF); + CONDITIONAL_SET_FLAG(PARITY(res & 0xff), F_PF); + + /* calculate the borrow chain. See note at top */ + bc = (res & (~d | s)) | (~d & s); + CONDITIONAL_SET_FLAG(bc & 0x80000000, F_CF); + CONDITIONAL_SET_FLAG(XOR2(bc >> 30), F_OF); + CONDITIONAL_SET_FLAG(bc & 0x8, F_AF); + return d; +} + +/**************************************************************************** +REMARKS: +Implements the DAA instruction and side effects. +****************************************************************************/ +u8 daa_byte(u8 d) +{ + u32 res = d; + if ((d & 0xf) > 9 || ACCESS_FLAG(F_AF)) { + res += 6; + SET_FLAG(F_AF); + } + if (res > 0x9F || ACCESS_FLAG(F_CF)) { + res += 0x60; + SET_FLAG(F_CF); + } + CONDITIONAL_SET_FLAG(res & 0x80, F_SF); + CONDITIONAL_SET_FLAG((res & 0xFF) == 0, F_ZF); + CONDITIONAL_SET_FLAG(PARITY(res & 0xff), F_PF); + return (u8)res; +} + +/**************************************************************************** +REMARKS: +Implements the DAS instruction and side effects. +****************************************************************************/ +u8 das_byte(u8 d) +{ + if ((d & 0xf) > 9 || ACCESS_FLAG(F_AF)) { + d -= 6; + SET_FLAG(F_AF); + } + if (d > 0x9F || ACCESS_FLAG(F_CF)) { + d -= 0x60; + SET_FLAG(F_CF); + } + CONDITIONAL_SET_FLAG(d & 0x80, F_SF); + CONDITIONAL_SET_FLAG(d == 0, F_ZF); + CONDITIONAL_SET_FLAG(PARITY(d & 0xff), F_PF); + return d; +} + +/**************************************************************************** +REMARKS: +Implements the DEC instruction and side effects. +****************************************************************************/ +u8 dec_byte(u8 d) +{ + register u32 res; /* all operands in native machine order */ + register u32 bc; + + res = d - 1; + CONDITIONAL_SET_FLAG(res & 0x80, F_SF); + CONDITIONAL_SET_FLAG((res & 0xff) == 0, F_ZF); + CONDITIONAL_SET_FLAG(PARITY(res & 0xff), F_PF); + + /* calculate the borrow chain. See note at top */ + /* based on sub_byte, uses s==1. */ + bc = (res & (~d | 1)) | (~d & 1); + /* carry flag unchanged */ + CONDITIONAL_SET_FLAG(XOR2(bc >> 6), F_OF); + CONDITIONAL_SET_FLAG(bc & 0x8, F_AF); + return (u8)res; +} + +/**************************************************************************** +REMARKS: +Implements the DEC instruction and side effects. +****************************************************************************/ +u16 dec_word(u16 d) +{ + register u32 res; /* all operands in native machine order */ + register u32 bc; + + res = d - 1; + CONDITIONAL_SET_FLAG(res & 0x8000, F_SF); + CONDITIONAL_SET_FLAG((res & 0xffff) == 0, F_ZF); + CONDITIONAL_SET_FLAG(PARITY(res & 0xff), F_PF); + + /* calculate the borrow chain. See note at top */ + /* based on the sub_byte routine, with s==1 */ + bc = (res & (~d | 1)) | (~d & 1); + /* carry flag unchanged */ + CONDITIONAL_SET_FLAG(XOR2(bc >> 14), F_OF); + CONDITIONAL_SET_FLAG(bc & 0x8, F_AF); + return (u16)res; +} + +/**************************************************************************** +REMARKS: +Implements the DEC instruction and side effects. +****************************************************************************/ +u32 dec_long(u32 d) +{ + register u32 res; /* all operands in native machine order */ + register u32 bc; + + res = d - 1; + + CONDITIONAL_SET_FLAG(res & 0x80000000, F_SF); + CONDITIONAL_SET_FLAG((res & 0xffffffff) == 0, F_ZF); + CONDITIONAL_SET_FLAG(PARITY(res & 0xff), F_PF); + + /* calculate the borrow chain. See note at top */ + bc = (res & (~d | 1)) | (~d & 1); + /* carry flag unchanged */ + CONDITIONAL_SET_FLAG(XOR2(bc >> 30), F_OF); + CONDITIONAL_SET_FLAG(bc & 0x8, F_AF); + return res; +} + +/**************************************************************************** +REMARKS: +Implements the INC instruction and side effects. +****************************************************************************/ +u8 inc_byte(u8 d) +{ + register u32 res; /* all operands in native machine order */ + register u32 cc; + + res = d + 1; + CONDITIONAL_SET_FLAG((res & 0xff) == 0, F_ZF); + CONDITIONAL_SET_FLAG(res & 0x80, F_SF); + CONDITIONAL_SET_FLAG(PARITY(res & 0xff), F_PF); + + /* calculate the carry chain SEE NOTE AT TOP. */ + cc = ((1 & d) | (~res)) & (1 | d); + CONDITIONAL_SET_FLAG(XOR2(cc >> 6), F_OF); + CONDITIONAL_SET_FLAG(cc & 0x8, F_AF); + return (u8)res; +} + +/**************************************************************************** +REMARKS: +Implements the INC instruction and side effects. +****************************************************************************/ +u16 inc_word(u16 d) +{ + register u32 res; /* all operands in native machine order */ + register u32 cc; + + res = d + 1; + CONDITIONAL_SET_FLAG((res & 0xffff) == 0, F_ZF); + CONDITIONAL_SET_FLAG(res & 0x8000, F_SF); + CONDITIONAL_SET_FLAG(PARITY(res & 0xff), F_PF); + + /* calculate the carry chain SEE NOTE AT TOP. */ + cc = (1 & d) | ((~res) & (1 | d)); + CONDITIONAL_SET_FLAG(XOR2(cc >> 14), F_OF); + CONDITIONAL_SET_FLAG(cc & 0x8, F_AF); + return (u16)res; +} + +/**************************************************************************** +REMARKS: +Implements the INC instruction and side effects. +****************************************************************************/ +u32 inc_long(u32 d) +{ + register u32 res; /* all operands in native machine order */ + register u32 cc; + + res = d + 1; + CONDITIONAL_SET_FLAG((res & 0xffffffff) == 0, F_ZF); + CONDITIONAL_SET_FLAG(res & 0x80000000, F_SF); + CONDITIONAL_SET_FLAG(PARITY(res & 0xff), F_PF); + + /* calculate the carry chain SEE NOTE AT TOP. */ + cc = (1 & d) | ((~res) & (1 | d)); + CONDITIONAL_SET_FLAG(XOR2(cc >> 30), F_OF); + CONDITIONAL_SET_FLAG(cc & 0x8, F_AF); + return res; +} + +/**************************************************************************** +REMARKS: +Implements the OR instruction and side effects. +****************************************************************************/ +u8 or_byte(u8 d, u8 s) +{ + register u8 res; /* all operands in native machine order */ + + res = d | s; + CLEAR_FLAG(F_OF); + CLEAR_FLAG(F_CF); + CLEAR_FLAG(F_AF); + CONDITIONAL_SET_FLAG(res & 0x80, F_SF); + CONDITIONAL_SET_FLAG(res == 0, F_ZF); + CONDITIONAL_SET_FLAG(PARITY(res), F_PF); + return res; +} + +/**************************************************************************** +REMARKS: +Implements the OR instruction and side effects. +****************************************************************************/ +u16 or_word(u16 d, u16 s) +{ + register u16 res; /* all operands in native machine order */ + + res = d | s; + /* set the carry flag to be bit 8 */ + CLEAR_FLAG(F_OF); + CLEAR_FLAG(F_CF); + CLEAR_FLAG(F_AF); + CONDITIONAL_SET_FLAG(res & 0x8000, F_SF); + CONDITIONAL_SET_FLAG(res == 0, F_ZF); + CONDITIONAL_SET_FLAG(PARITY(res & 0xff), F_PF); + return res; +} + +/**************************************************************************** +REMARKS: +Implements the OR instruction and side effects. +****************************************************************************/ +u32 or_long(u32 d, u32 s) +{ + register u32 res; /* all operands in native machine order */ + + res = d | s; + + /* set the carry flag to be bit 8 */ + CLEAR_FLAG(F_OF); + CLEAR_FLAG(F_CF); + CLEAR_FLAG(F_AF); + CONDITIONAL_SET_FLAG(res & 0x80000000, F_SF); + CONDITIONAL_SET_FLAG(res == 0, F_ZF); + CONDITIONAL_SET_FLAG(PARITY(res & 0xff), F_PF); + return res; +} + +/**************************************************************************** +REMARKS: +Implements the OR instruction and side effects. +****************************************************************************/ +u8 neg_byte(u8 s) +{ + register u8 res; + register u8 bc; + + CONDITIONAL_SET_FLAG(s != 0, F_CF); + res = (u8)-s; + CONDITIONAL_SET_FLAG((res & 0xff) == 0, F_ZF); + CONDITIONAL_SET_FLAG(res & 0x80, F_SF); + CONDITIONAL_SET_FLAG(PARITY(res), F_PF); + /* calculate the borrow chain --- modified such that d=0. + substitutiing d=0 into bc= res&(~d|s)|(~d&s); + (the one used for sub) and simplifying, since ~d=0xff..., + ~d|s == 0xffff..., and res&0xfff... == res. Similarly + ~d&s == s. So the simplified result is: */ + bc = res | s; + CONDITIONAL_SET_FLAG(XOR2(bc >> 6), F_OF); + CONDITIONAL_SET_FLAG(bc & 0x8, F_AF); + return res; +} + +/**************************************************************************** +REMARKS: +Implements the OR instruction and side effects. +****************************************************************************/ +u16 neg_word(u16 s) +{ + register u16 res; + register u16 bc; + + CONDITIONAL_SET_FLAG(s != 0, F_CF); + res = (u16)-s; + CONDITIONAL_SET_FLAG((res & 0xffff) == 0, F_ZF); + CONDITIONAL_SET_FLAG(res & 0x8000, F_SF); + CONDITIONAL_SET_FLAG(PARITY(res & 0xff), F_PF); + + /* calculate the borrow chain --- modified such that d=0. + substitutiing d=0 into bc= res&(~d|s)|(~d&s); + (the one used for sub) and simplifying, since ~d=0xff..., + ~d|s == 0xffff..., and res&0xfff... == res. Similarly + ~d&s == s. So the simplified result is: */ + bc = res | s; + CONDITIONAL_SET_FLAG(XOR2(bc >> 14), F_OF); + CONDITIONAL_SET_FLAG(bc & 0x8, F_AF); + return res; +} + +/**************************************************************************** +REMARKS: +Implements the OR instruction and side effects. +****************************************************************************/ +u32 neg_long(u32 s) +{ + register u32 res; + register u32 bc; + + CONDITIONAL_SET_FLAG(s != 0, F_CF); + res = (u32)-s; + CONDITIONAL_SET_FLAG((res & 0xffffffff) == 0, F_ZF); + CONDITIONAL_SET_FLAG(res & 0x80000000, F_SF); + CONDITIONAL_SET_FLAG(PARITY(res & 0xff), F_PF); + + /* calculate the borrow chain --- modified such that d=0. + substitutiing d=0 into bc= res&(~d|s)|(~d&s); + (the one used for sub) and simplifying, since ~d=0xff..., + ~d|s == 0xffff..., and res&0xfff... == res. Similarly + ~d&s == s. So the simplified result is: */ + bc = res | s; + CONDITIONAL_SET_FLAG(XOR2(bc >> 30), F_OF); + CONDITIONAL_SET_FLAG(bc & 0x8, F_AF); + return res; +} + +/**************************************************************************** +REMARKS: +Implements the NOT instruction and side effects. +****************************************************************************/ +u8 not_byte(u8 s) +{ + return ~s; +} + +/**************************************************************************** +REMARKS: +Implements the NOT instruction and side effects. +****************************************************************************/ +u16 not_word(u16 s) +{ + return ~s; +} + +/**************************************************************************** +REMARKS: +Implements the NOT instruction and side effects. +****************************************************************************/ +u32 not_long(u32 s) +{ + return ~s; +} + +/**************************************************************************** +REMARKS: +Implements the RCL instruction and side effects. +****************************************************************************/ +u8 rcl_byte(u8 d, u8 s) +{ + register unsigned int res, cnt, mask, cf; + + /* s is the rotate distance. It varies from 0 - 8. */ + /* have + + CF B_7 B_6 B_5 B_4 B_3 B_2 B_1 B_0 + + want to rotate through the carry by "s" bits. We could + loop, but that's inefficient. So the width is 9, + and we split into three parts: + + The new carry flag (was B_n) + the stuff in B_n-1 .. B_0 + the stuff in B_7 .. B_n+1 + + The new rotate is done mod 9, and given this, + for a rotation of n bits (mod 9) the new carry flag is + then located n bits from the MSB. The low part is + then shifted up cnt bits, and the high part is or'd + in. Using CAPS for new values, and lowercase for the + original values, this can be expressed as: + + IF n > 0 + 1) CF <- b_(8-n) + 2) B_(7) .. B_(n) <- b_(8-(n+1)) .. b_0 + 3) B_(n-1) <- cf + 4) B_(n-2) .. B_0 <- b_7 .. b_(8-(n-1)) + */ + res = d; + if ((cnt = s % 9) != 0) { + /* extract the new CARRY FLAG. */ + /* CF <- b_(8-n) */ + cf = (d >> (8 - cnt)) & 0x1; + + /* get the low stuff which rotated + into the range B_7 .. B_cnt */ + /* B_(7) .. B_(n) <- b_(8-(n+1)) .. b_0 */ + /* note that the right hand side done by the mask */ + res = (d << cnt) & 0xff; + + /* now the high stuff which rotated around + into the positions B_cnt-2 .. B_0 */ + /* B_(n-2) .. B_0 <- b_7 .. b_(8-(n-1)) */ + /* shift it downward, 7-(n-2) = 9-n positions. + and mask off the result before or'ing in. + */ + mask = (1 << (cnt - 1)) - 1; + res |= (d >> (9 - cnt)) & mask; + + /* if the carry flag was set, or it in. */ + if (ACCESS_FLAG(F_CF)) { /* carry flag is set */ + /* B_(n-1) <- cf */ + res |= 1 << (cnt - 1); + } + /* set the new carry flag, based on the variable "cf" */ + CONDITIONAL_SET_FLAG(cf, F_CF); + /* OVERFLOW is set *IFF* cnt==1, then it is the + xor of CF and the most significant bit. Blecck. */ + /* parenthesized this expression since it appears to + be causing OF to be misset */ + CONDITIONAL_SET_FLAG(cnt == 1 && XOR2(cf + ((res >> 6) & 0x2)), + F_OF); + + } + return (u8)res; +} + +/**************************************************************************** +REMARKS: +Implements the RCL instruction and side effects. +****************************************************************************/ +u16 rcl_word(u16 d, u8 s) +{ + register unsigned int res, cnt, mask, cf; + + res = d; + if ((cnt = s % 17) != 0) { + cf = (d >> (16 - cnt)) & 0x1; + res = (d << cnt) & 0xffff; + mask = (1 << (cnt - 1)) - 1; + res |= (d >> (17 - cnt)) & mask; + if (ACCESS_FLAG(F_CF)) { + res |= 1 << (cnt - 1); + } + CONDITIONAL_SET_FLAG(cf, F_CF); + CONDITIONAL_SET_FLAG(cnt == 1 && XOR2(cf + ((res >> 14) & 0x2)), + F_OF); + } + return (u16)res; +} + +/**************************************************************************** +REMARKS: +Implements the RCL instruction and side effects. +****************************************************************************/ +u32 rcl_long(u32 d, u8 s) +{ + register u32 res, cnt, mask, cf; + + res = d; + if ((cnt = s % 33) != 0) { + cf = (d >> (32 - cnt)) & 0x1; + res = (d << cnt) & 0xffffffff; + mask = (1 << (cnt - 1)) - 1; + res |= (d >> (33 - cnt)) & mask; + if (ACCESS_FLAG(F_CF)) { /* carry flag is set */ + res |= 1 << (cnt - 1); + } + CONDITIONAL_SET_FLAG(cf, F_CF); + CONDITIONAL_SET_FLAG(cnt == 1 && XOR2(cf + ((res >> 30) & 0x2)), + F_OF); + } + return res; +} + +/**************************************************************************** +REMARKS: +Implements the RCR instruction and side effects. +****************************************************************************/ +u8 rcr_byte(u8 d, u8 s) +{ + u32 res, cnt; + u32 mask, cf, ocf = 0; + + /* rotate right through carry */ + /* + s is the rotate distance. It varies from 0 - 8. + d is the byte object rotated. + + have + + CF B_7 B_6 B_5 B_4 B_3 B_2 B_1 B_0 + + The new rotate is done mod 9, and given this, + for a rotation of n bits (mod 9) the new carry flag is + then located n bits from the LSB. The low part is + then shifted up cnt bits, and the high part is or'd + in. Using CAPS for new values, and lowercase for the + original values, this can be expressed as: + + IF n > 0 + 1) CF <- b_(n-1) + 2) B_(8-(n+1)) .. B_(0) <- b_(7) .. b_(n) + 3) B_(8-n) <- cf + 4) B_(7) .. B_(8-(n-1)) <- b_(n-2) .. b_(0) + */ + res = d; + if ((cnt = s % 9) != 0) { + /* extract the new CARRY FLAG. */ + /* CF <- b_(n-1) */ + if (cnt == 1) { + cf = d & 0x1; + /* note hackery here. Access_flag(..) evaluates to either + 0 if flag not set + non-zero if flag is set. + doing access_flag(..) != 0 casts that into either + 0..1 in any representation of the flags register + (i.e. packed bit array or unpacked.) + */ + ocf = ACCESS_FLAG(F_CF) != 0; + } else + cf = (d >> (cnt - 1)) & 0x1; + + /* B_(8-(n+1)) .. B_(0) <- b_(7) .. b_n */ + /* note that the right hand side done by the mask + This is effectively done by shifting the + object to the right. The result must be masked, + in case the object came in and was treated + as a negative number. Needed??? */ + + mask = (1 << (8 - cnt)) - 1; + res = (d >> cnt) & mask; + + /* now the high stuff which rotated around + into the positions B_cnt-2 .. B_0 */ + /* B_(7) .. B_(8-(n-1)) <- b_(n-2) .. b_(0) */ + /* shift it downward, 7-(n-2) = 9-n positions. + and mask off the result before or'ing in. + */ + res |= (d << (9 - cnt)); + + /* if the carry flag was set, or it in. */ + if (ACCESS_FLAG(F_CF)) { /* carry flag is set */ + /* B_(8-n) <- cf */ + res |= 1 << (8 - cnt); + } + /* set the new carry flag, based on the variable "cf" */ + CONDITIONAL_SET_FLAG(cf, F_CF); + /* OVERFLOW is set *IFF* cnt==1, then it is the + xor of CF and the most significant bit. Blecck. */ + /* parenthesized... */ + if (cnt == 1) { + CONDITIONAL_SET_FLAG(XOR2(ocf + ((d >> 6) & 0x2)), + F_OF); + } + } + return (u8)res; +} + +/**************************************************************************** +REMARKS: +Implements the RCR instruction and side effects. +****************************************************************************/ +u16 rcr_word(u16 d, u8 s) +{ + u32 res, cnt; + u32 mask, cf, ocf = 0; + + /* rotate right through carry */ + res = d; + if ((cnt = s % 17) != 0) { + if (cnt == 1) { + cf = d & 0x1; + ocf = ACCESS_FLAG(F_CF) != 0; + } else + cf = (d >> (cnt - 1)) & 0x1; + mask = (1 << (16 - cnt)) - 1; + res = (d >> cnt) & mask; + res |= (d << (17 - cnt)); + if (ACCESS_FLAG(F_CF)) { + res |= 1 << (16 - cnt); + } + CONDITIONAL_SET_FLAG(cf, F_CF); + if (cnt == 1) { + CONDITIONAL_SET_FLAG(XOR2(ocf + ((d >> 14) & 0x2)), + F_OF); + } + } + return (u16)res; +} + +/**************************************************************************** +REMARKS: +Implements the RCR instruction and side effects. +****************************************************************************/ +u32 rcr_long(u32 d, u8 s) +{ + u32 res, cnt; + u32 mask, cf, ocf = 0; + + /* rotate right through carry */ + res = d; + if ((cnt = s % 33) != 0) { + if (cnt == 1) { + cf = d & 0x1; + ocf = ACCESS_FLAG(F_CF) != 0; + } else + cf = (d >> (cnt - 1)) & 0x1; + mask = (1 << (32 - cnt)) - 1; + res = (d >> cnt) & mask; + if (cnt != 1) + res |= (d << (33 - cnt)); + if (ACCESS_FLAG(F_CF)) { /* carry flag is set */ + res |= 1 << (32 - cnt); + } + CONDITIONAL_SET_FLAG(cf, F_CF); + if (cnt == 1) { + CONDITIONAL_SET_FLAG(XOR2(ocf + ((d >> 30) & 0x2)), + F_OF); + } + } + return res; +} + +/**************************************************************************** +REMARKS: +Implements the ROL instruction and side effects. +****************************************************************************/ +u8 rol_byte(u8 d, u8 s) +{ + register unsigned int res, cnt, mask; + + /* rotate left */ + /* + s is the rotate distance. It varies from 0 - 8. + d is the byte object rotated. + + have + + CF B_7 ... B_0 + + The new rotate is done mod 8. + Much simpler than the "rcl" or "rcr" operations. + + IF n > 0 + 1) B_(7) .. B_(n) <- b_(8-(n+1)) .. b_(0) + 2) B_(n-1) .. B_(0) <- b_(7) .. b_(8-n) + */ + res = d; + if ((cnt = s % 8) != 0) { + /* B_(7) .. B_(n) <- b_(8-(n+1)) .. b_(0) */ + res = (d << cnt); + + /* B_(n-1) .. B_(0) <- b_(7) .. b_(8-n) */ + mask = (1 << cnt) - 1; + res |= (d >> (8 - cnt)) & mask; + + /* set the new carry flag, Note that it is the low order + bit of the result!!! */ + CONDITIONAL_SET_FLAG(res & 0x1, F_CF); + /* OVERFLOW is set *IFF* s==1, then it is the + xor of CF and the most significant bit. Blecck. */ + CONDITIONAL_SET_FLAG(s == 1 && + XOR2((res & 0x1) + ((res >> 6) & 0x2)), + F_OF); + } if (s != 0) { + /* set the new carry flag, Note that it is the low order + bit of the result!!! */ + CONDITIONAL_SET_FLAG(res & 0x1, F_CF); + } + return (u8)res; +} + +/**************************************************************************** +REMARKS: +Implements the ROL instruction and side effects. +****************************************************************************/ +u16 rol_word(u16 d, u8 s) +{ + register unsigned int res, cnt, mask; + + res = d; + if ((cnt = s % 16) != 0) { + res = (d << cnt); + mask = (1 << cnt) - 1; + res |= (d >> (16 - cnt)) & mask; + CONDITIONAL_SET_FLAG(res & 0x1, F_CF); + CONDITIONAL_SET_FLAG(s == 1 && + XOR2((res & 0x1) + ((res >> 14) & 0x2)), + F_OF); + } if (s != 0) { + /* set the new carry flag, Note that it is the low order + bit of the result!!! */ + CONDITIONAL_SET_FLAG(res & 0x1, F_CF); + } + return (u16)res; +} + +/**************************************************************************** +REMARKS: +Implements the ROL instruction and side effects. +****************************************************************************/ +u32 rol_long(u32 d, u8 s) +{ + register u32 res, cnt, mask; + + res = d; + if ((cnt = s % 32) != 0) { + res = (d << cnt); + mask = (1 << cnt) - 1; + res |= (d >> (32 - cnt)) & mask; + CONDITIONAL_SET_FLAG(res & 0x1, F_CF); + CONDITIONAL_SET_FLAG(s == 1 && + XOR2((res & 0x1) + ((res >> 30) & 0x2)), + F_OF); + } if (s != 0) { + /* set the new carry flag, Note that it is the low order + bit of the result!!! */ + CONDITIONAL_SET_FLAG(res & 0x1, F_CF); + } + return res; +} + +/**************************************************************************** +REMARKS: +Implements the ROR instruction and side effects. +****************************************************************************/ +u8 ror_byte(u8 d, u8 s) +{ + register unsigned int res, cnt, mask; + + /* rotate right */ + /* + s is the rotate distance. It varies from 0 - 8. + d is the byte object rotated. + + have + + B_7 ... B_0 + + The rotate is done mod 8. + + IF n > 0 + 1) B_(8-(n+1)) .. B_(0) <- b_(7) .. b_(n) + 2) B_(7) .. B_(8-n) <- b_(n-1) .. b_(0) + */ + res = d; + if ((cnt = s % 8) != 0) { /* not a typo, do nada if cnt==0 */ + /* B_(7) .. B_(8-n) <- b_(n-1) .. b_(0) */ + res = (d << (8 - cnt)); + + /* B_(8-(n+1)) .. B_(0) <- b_(7) .. b_(n) */ + mask = (1 << (8 - cnt)) - 1; + res |= (d >> (cnt)) & mask; + + /* set the new carry flag, Note that it is the low order + bit of the result!!! */ + CONDITIONAL_SET_FLAG(res & 0x80, F_CF); + /* OVERFLOW is set *IFF* s==1, then it is the + xor of the two most significant bits. Blecck. */ + CONDITIONAL_SET_FLAG(s == 1 && XOR2(res >> 6), F_OF); + } else if (s != 0) { + /* set the new carry flag, Note that it is the low order + bit of the result!!! */ + CONDITIONAL_SET_FLAG(res & 0x80, F_CF); + } + return (u8)res; +} + +/**************************************************************************** +REMARKS: +Implements the ROR instruction and side effects. +****************************************************************************/ +u16 ror_word(u16 d, u8 s) +{ + register unsigned int res, cnt, mask; + + res = d; + if ((cnt = s % 16) != 0) { + res = (d << (16 - cnt)); + mask = (1 << (16 - cnt)) - 1; + res |= (d >> (cnt)) & mask; + CONDITIONAL_SET_FLAG(res & 0x8000, F_CF); + CONDITIONAL_SET_FLAG(s == 1 && XOR2(res >> 14), F_OF); + } else if (s != 0) { + /* set the new carry flag, Note that it is the low order + bit of the result!!! */ + CONDITIONAL_SET_FLAG(res & 0x8000, F_CF); + } + return (u16)res; +} + +/**************************************************************************** +REMARKS: +Implements the ROR instruction and side effects. +****************************************************************************/ +u32 ror_long(u32 d, u8 s) +{ + register u32 res, cnt, mask; + + res = d; + if ((cnt = s % 32) != 0) { + res = (d << (32 - cnt)); + mask = (1 << (32 - cnt)) - 1; + res |= (d >> (cnt)) & mask; + CONDITIONAL_SET_FLAG(res & 0x80000000, F_CF); + CONDITIONAL_SET_FLAG(s == 1 && XOR2(res >> 30), F_OF); + } else if (s != 0) { + /* set the new carry flag, Note that it is the low order + bit of the result!!! */ + CONDITIONAL_SET_FLAG(res & 0x80000000, F_CF); + } + return res; +} + +/**************************************************************************** +REMARKS: +Implements the SHL instruction and side effects. +****************************************************************************/ +u8 shl_byte(u8 d, u8 s) +{ + unsigned int cnt, res, cf; + + if (s < 8) { + cnt = s % 8; + + /* last bit shifted out goes into carry flag */ + if (cnt > 0) { + res = d << cnt; + cf = d & (1 << (8 - cnt)); + CONDITIONAL_SET_FLAG(cf, F_CF); + CONDITIONAL_SET_FLAG((res & 0xff) == 0, F_ZF); + CONDITIONAL_SET_FLAG(res & 0x80, F_SF); + CONDITIONAL_SET_FLAG(PARITY(res & 0xff), F_PF); + } else { + res = (u8) d; + } + + if (cnt == 1) { + /* Needs simplification. */ + CONDITIONAL_SET_FLAG( + (((res & 0x80) == 0x80) ^ + (ACCESS_FLAG(F_CF) != 0)), + /* was (M.x86.R_FLG&F_CF)==F_CF)), */ + F_OF); + } else { + CLEAR_FLAG(F_OF); + } + } else { + res = 0; + CONDITIONAL_SET_FLAG((d << (s-1)) & 0x80, F_CF); + CLEAR_FLAG(F_OF); + CLEAR_FLAG(F_SF); + SET_FLAG(F_PF); + SET_FLAG(F_ZF); + } + return (u8)res; +} + +/**************************************************************************** +REMARKS: +Implements the SHL instruction and side effects. +****************************************************************************/ +u16 shl_word(u16 d, u8 s) +{ + unsigned int cnt, res, cf; + + if (s < 16) { + cnt = s % 16; + if (cnt > 0) { + res = d << cnt; + cf = d & (1 << (16 - cnt)); + CONDITIONAL_SET_FLAG(cf, F_CF); + CONDITIONAL_SET_FLAG((res & 0xffff) == 0, F_ZF); + CONDITIONAL_SET_FLAG(res & 0x8000, F_SF); + CONDITIONAL_SET_FLAG(PARITY(res & 0xff), F_PF); + } else { + res = (u16) d; + } + + if (cnt == 1) { + CONDITIONAL_SET_FLAG( + (((res & 0x8000) == 0x8000) ^ + (ACCESS_FLAG(F_CF) != 0)), + F_OF); + } else { + CLEAR_FLAG(F_OF); + } + } else { + res = 0; + CONDITIONAL_SET_FLAG((d << (s-1)) & 0x8000, F_CF); + CLEAR_FLAG(F_OF); + CLEAR_FLAG(F_SF); + SET_FLAG(F_PF); + SET_FLAG(F_ZF); + } + return (u16)res; +} + +/**************************************************************************** +REMARKS: +Implements the SHL instruction and side effects. +****************************************************************************/ +u32 shl_long(u32 d, u8 s) +{ + unsigned int cnt, res, cf; + + if (s < 32) { + cnt = s % 32; + if (cnt > 0) { + res = d << cnt; + cf = d & (1 << (32 - cnt)); + CONDITIONAL_SET_FLAG(cf, F_CF); + CONDITIONAL_SET_FLAG((res & 0xffffffff) == 0, F_ZF); + CONDITIONAL_SET_FLAG(res & 0x80000000, F_SF); + CONDITIONAL_SET_FLAG(PARITY(res & 0xff), F_PF); + } else { + res = d; + } + if (cnt == 1) { + CONDITIONAL_SET_FLAG((((res & 0x80000000) == 0x80000000) ^ + (ACCESS_FLAG(F_CF) != 0)), F_OF); + } else { + CLEAR_FLAG(F_OF); + } + } else { + res = 0; + CONDITIONAL_SET_FLAG((d << (s-1)) & 0x80000000, F_CF); + CLEAR_FLAG(F_OF); + CLEAR_FLAG(F_SF); + SET_FLAG(F_PF); + SET_FLAG(F_ZF); + } + return res; +} + +/**************************************************************************** +REMARKS: +Implements the SHR instruction and side effects. +****************************************************************************/ +u8 shr_byte(u8 d, u8 s) +{ + unsigned int cnt, res, cf; + + if (s < 8) { + cnt = s % 8; + if (cnt > 0) { + cf = d & (1 << (cnt - 1)); + res = d >> cnt; + CONDITIONAL_SET_FLAG(cf, F_CF); + CONDITIONAL_SET_FLAG((res & 0xff) == 0, F_ZF); + CONDITIONAL_SET_FLAG(res & 0x80, F_SF); + CONDITIONAL_SET_FLAG(PARITY(res & 0xff), F_PF); + } else { + res = (u8) d; + } + + if (cnt == 1) { + CONDITIONAL_SET_FLAG(XOR2(res >> 6), F_OF); + } else { + CLEAR_FLAG(F_OF); + } + } else { + res = 0; + CONDITIONAL_SET_FLAG((d >> (s-1)) & 0x1, F_CF); + CLEAR_FLAG(F_OF); + CLEAR_FLAG(F_SF); + SET_FLAG(F_PF); + SET_FLAG(F_ZF); + } + return (u8)res; +} + +/**************************************************************************** +REMARKS: +Implements the SHR instruction and side effects. +****************************************************************************/ +u16 shr_word(u16 d, u8 s) +{ + unsigned int cnt, res, cf; + + if (s < 16) { + cnt = s % 16; + if (cnt > 0) { + cf = d & (1 << (cnt - 1)); + res = d >> cnt; + CONDITIONAL_SET_FLAG(cf, F_CF); + CONDITIONAL_SET_FLAG((res & 0xffff) == 0, F_ZF); + CONDITIONAL_SET_FLAG(res & 0x8000, F_SF); + CONDITIONAL_SET_FLAG(PARITY(res & 0xff), F_PF); + } else { + res = d; + } + + if (cnt == 1) { + CONDITIONAL_SET_FLAG(XOR2(res >> 14), F_OF); + } else { + CLEAR_FLAG(F_OF); + } + } else { + res = 0; + CLEAR_FLAG(F_CF); + CLEAR_FLAG(F_OF); + SET_FLAG(F_ZF); + CLEAR_FLAG(F_SF); + CLEAR_FLAG(F_PF); + } + return (u16)res; +} + +/**************************************************************************** +REMARKS: +Implements the SHR instruction and side effects. +****************************************************************************/ +u32 shr_long(u32 d, u8 s) +{ + unsigned int cnt, res, cf; + + if (s < 32) { + cnt = s % 32; + if (cnt > 0) { + cf = d & (1 << (cnt - 1)); + res = d >> cnt; + CONDITIONAL_SET_FLAG(cf, F_CF); + CONDITIONAL_SET_FLAG((res & 0xffffffff) == 0, F_ZF); + CONDITIONAL_SET_FLAG(res & 0x80000000, F_SF); + CONDITIONAL_SET_FLAG(PARITY(res & 0xff), F_PF); + } else { + res = d; + } + if (cnt == 1) { + CONDITIONAL_SET_FLAG(XOR2(res >> 30), F_OF); + } else { + CLEAR_FLAG(F_OF); + } + } else { + res = 0; + CLEAR_FLAG(F_CF); + CLEAR_FLAG(F_OF); + SET_FLAG(F_ZF); + CLEAR_FLAG(F_SF); + CLEAR_FLAG(F_PF); + } + return res; +} + +/**************************************************************************** +REMARKS: +Implements the SAR instruction and side effects. +****************************************************************************/ +u8 sar_byte(u8 d, u8 s) +{ + unsigned int cnt, res, cf, mask, sf; + + res = d; + sf = d & 0x80; + cnt = s % 8; + if (cnt > 0 && cnt < 8) { + mask = (1 << (8 - cnt)) - 1; + cf = d & (1 << (cnt - 1)); + res = (d >> cnt) & mask; + CONDITIONAL_SET_FLAG(cf, F_CF); + if (sf) { + res |= ~mask; + } + CONDITIONAL_SET_FLAG((res & 0xff) == 0, F_ZF); + CONDITIONAL_SET_FLAG(PARITY(res & 0xff), F_PF); + CONDITIONAL_SET_FLAG(res & 0x80, F_SF); + } else if (cnt >= 8) { + if (sf) { + res = 0xff; + SET_FLAG(F_CF); + CLEAR_FLAG(F_ZF); + SET_FLAG(F_SF); + SET_FLAG(F_PF); + } else { + res = 0; + CLEAR_FLAG(F_CF); + SET_FLAG(F_ZF); + CLEAR_FLAG(F_SF); + CLEAR_FLAG(F_PF); + } + } + return (u8)res; +} + +/**************************************************************************** +REMARKS: +Implements the SAR instruction and side effects. +****************************************************************************/ +u16 sar_word(u16 d, u8 s) +{ + unsigned int cnt, res, cf, mask, sf; + + sf = d & 0x8000; + cnt = s % 16; + res = d; + if (cnt > 0 && cnt < 16) { + mask = (1 << (16 - cnt)) - 1; + cf = d & (1 << (cnt - 1)); + res = (d >> cnt) & mask; + CONDITIONAL_SET_FLAG(cf, F_CF); + if (sf) { + res |= ~mask; + } + CONDITIONAL_SET_FLAG((res & 0xffff) == 0, F_ZF); + CONDITIONAL_SET_FLAG(res & 0x8000, F_SF); + CONDITIONAL_SET_FLAG(PARITY(res & 0xff), F_PF); + } else if (cnt >= 16) { + if (sf) { + res = 0xffff; + SET_FLAG(F_CF); + CLEAR_FLAG(F_ZF); + SET_FLAG(F_SF); + SET_FLAG(F_PF); + } else { + res = 0; + CLEAR_FLAG(F_CF); + SET_FLAG(F_ZF); + CLEAR_FLAG(F_SF); + CLEAR_FLAG(F_PF); + } + } + return (u16)res; +} + +/**************************************************************************** +REMARKS: +Implements the SAR instruction and side effects. +****************************************************************************/ +u32 sar_long(u32 d, u8 s) +{ + u32 cnt, res, cf, mask, sf; + + sf = d & 0x80000000; + cnt = s % 32; + res = d; + if (cnt > 0 && cnt < 32) { + mask = (1 << (32 - cnt)) - 1; + cf = d & (1 << (cnt - 1)); + res = (d >> cnt) & mask; + CONDITIONAL_SET_FLAG(cf, F_CF); + if (sf) { + res |= ~mask; + } + CONDITIONAL_SET_FLAG((res & 0xffffffff) == 0, F_ZF); + CONDITIONAL_SET_FLAG(res & 0x80000000, F_SF); + CONDITIONAL_SET_FLAG(PARITY(res & 0xff), F_PF); + } else if (cnt >= 32) { + if (sf) { + res = 0xffffffff; + SET_FLAG(F_CF); + CLEAR_FLAG(F_ZF); + SET_FLAG(F_SF); + SET_FLAG(F_PF); + } else { + res = 0; + CLEAR_FLAG(F_CF); + SET_FLAG(F_ZF); + CLEAR_FLAG(F_SF); + CLEAR_FLAG(F_PF); + } + } + return res; +} + +/**************************************************************************** +REMARKS: +Implements the SHLD instruction and side effects. +****************************************************************************/ +u16 shld_word (u16 d, u16 fill, u8 s) +{ + unsigned int cnt, res, cf; + + if (s < 16) { + cnt = s % 16; + if (cnt > 0) { + res = (d << cnt) | (fill >> (16-cnt)); + cf = d & (1 << (16 - cnt)); + CONDITIONAL_SET_FLAG(cf, F_CF); + CONDITIONAL_SET_FLAG((res & 0xffff) == 0, F_ZF); + CONDITIONAL_SET_FLAG(res & 0x8000, F_SF); + CONDITIONAL_SET_FLAG(PARITY(res & 0xff), F_PF); + } else { + res = d; + } + if (cnt == 1) { + CONDITIONAL_SET_FLAG((((res & 0x8000) == 0x8000) ^ + (ACCESS_FLAG(F_CF) != 0)), F_OF); + } else { + CLEAR_FLAG(F_OF); + } + } else { + res = 0; + CONDITIONAL_SET_FLAG((d << (s-1)) & 0x8000, F_CF); + CLEAR_FLAG(F_OF); + CLEAR_FLAG(F_SF); + SET_FLAG(F_PF); + SET_FLAG(F_ZF); + } + return (u16)res; +} + +/**************************************************************************** +REMARKS: +Implements the SHLD instruction and side effects. +****************************************************************************/ +u32 shld_long (u32 d, u32 fill, u8 s) +{ + unsigned int cnt, res, cf; + + if (s < 32) { + cnt = s % 32; + if (cnt > 0) { + res = (d << cnt) | (fill >> (32-cnt)); + cf = d & (1 << (32 - cnt)); + CONDITIONAL_SET_FLAG(cf, F_CF); + CONDITIONAL_SET_FLAG((res & 0xffffffff) == 0, F_ZF); + CONDITIONAL_SET_FLAG(res & 0x80000000, F_SF); + CONDITIONAL_SET_FLAG(PARITY(res & 0xff), F_PF); + } else { + res = d; + } + if (cnt == 1) { + CONDITIONAL_SET_FLAG((((res & 0x80000000) == 0x80000000) ^ + (ACCESS_FLAG(F_CF) != 0)), F_OF); + } else { + CLEAR_FLAG(F_OF); + } + } else { + res = 0; + CONDITIONAL_SET_FLAG((d << (s-1)) & 0x80000000, F_CF); + CLEAR_FLAG(F_OF); + CLEAR_FLAG(F_SF); + SET_FLAG(F_PF); + SET_FLAG(F_ZF); + } + return res; +} + +/**************************************************************************** +REMARKS: +Implements the SHRD instruction and side effects. +****************************************************************************/ +u16 shrd_word (u16 d, u16 fill, u8 s) +{ + unsigned int cnt, res, cf; + + if (s < 16) { + cnt = s % 16; + if (cnt > 0) { + cf = d & (1 << (cnt - 1)); + res = (d >> cnt) | (fill << (16 - cnt)); + CONDITIONAL_SET_FLAG(cf, F_CF); + CONDITIONAL_SET_FLAG((res & 0xffff) == 0, F_ZF); + CONDITIONAL_SET_FLAG(res & 0x8000, F_SF); + CONDITIONAL_SET_FLAG(PARITY(res & 0xff), F_PF); + } else { + res = d; + } + + if (cnt == 1) { + CONDITIONAL_SET_FLAG(XOR2(res >> 14), F_OF); + } else { + CLEAR_FLAG(F_OF); + } + } else { + res = 0; + CLEAR_FLAG(F_CF); + CLEAR_FLAG(F_OF); + SET_FLAG(F_ZF); + CLEAR_FLAG(F_SF); + CLEAR_FLAG(F_PF); + } + return (u16)res; +} + +/**************************************************************************** +REMARKS: +Implements the SHRD instruction and side effects. +****************************************************************************/ +u32 shrd_long (u32 d, u32 fill, u8 s) +{ + unsigned int cnt, res, cf; + + if (s < 32) { + cnt = s % 32; + if (cnt > 0) { + cf = d & (1 << (cnt - 1)); + res = (d >> cnt) | (fill << (32 - cnt)); + CONDITIONAL_SET_FLAG(cf, F_CF); + CONDITIONAL_SET_FLAG((res & 0xffffffff) == 0, F_ZF); + CONDITIONAL_SET_FLAG(res & 0x80000000, F_SF); + CONDITIONAL_SET_FLAG(PARITY(res & 0xff), F_PF); + } else { + res = d; + } + if (cnt == 1) { + CONDITIONAL_SET_FLAG(XOR2(res >> 30), F_OF); + } else { + CLEAR_FLAG(F_OF); + } + } else { + res = 0; + CLEAR_FLAG(F_CF); + CLEAR_FLAG(F_OF); + SET_FLAG(F_ZF); + CLEAR_FLAG(F_SF); + CLEAR_FLAG(F_PF); + } + return res; +} + +/**************************************************************************** +REMARKS: +Implements the SBB instruction and side effects. +****************************************************************************/ +u8 sbb_byte(u8 d, u8 s) +{ + register u32 res; /* all operands in native machine order */ + register u32 bc; + + if (ACCESS_FLAG(F_CF)) + res = d - s - 1; + else + res = d - s; + CONDITIONAL_SET_FLAG(res & 0x80, F_SF); + CONDITIONAL_SET_FLAG((res & 0xff) == 0, F_ZF); + CONDITIONAL_SET_FLAG(PARITY(res & 0xff), F_PF); + + /* calculate the borrow chain. See note at top */ + bc = (res & (~d | s)) | (~d & s); + CONDITIONAL_SET_FLAG(bc & 0x80, F_CF); + CONDITIONAL_SET_FLAG(XOR2(bc >> 6), F_OF); + CONDITIONAL_SET_FLAG(bc & 0x8, F_AF); + return (u8)res; +} + +/**************************************************************************** +REMARKS: +Implements the SBB instruction and side effects. +****************************************************************************/ +u16 sbb_word(u16 d, u16 s) +{ + register u32 res; /* all operands in native machine order */ + register u32 bc; + + if (ACCESS_FLAG(F_CF)) + res = d - s - 1; + else + res = d - s; + CONDITIONAL_SET_FLAG(res & 0x8000, F_SF); + CONDITIONAL_SET_FLAG((res & 0xffff) == 0, F_ZF); + CONDITIONAL_SET_FLAG(PARITY(res & 0xff), F_PF); + + /* calculate the borrow chain. See note at top */ + bc = (res & (~d | s)) | (~d & s); + CONDITIONAL_SET_FLAG(bc & 0x8000, F_CF); + CONDITIONAL_SET_FLAG(XOR2(bc >> 14), F_OF); + CONDITIONAL_SET_FLAG(bc & 0x8, F_AF); + return (u16)res; +} + +/**************************************************************************** +REMARKS: +Implements the SBB instruction and side effects. +****************************************************************************/ +u32 sbb_long(u32 d, u32 s) +{ + register u32 res; /* all operands in native machine order */ + register u32 bc; + + if (ACCESS_FLAG(F_CF)) + res = d - s - 1; + else + res = d - s; + CONDITIONAL_SET_FLAG(res & 0x80000000, F_SF); + CONDITIONAL_SET_FLAG((res & 0xffffffff) == 0, F_ZF); + CONDITIONAL_SET_FLAG(PARITY(res & 0xff), F_PF); + + /* calculate the borrow chain. See note at top */ + bc = (res & (~d | s)) | (~d & s); + CONDITIONAL_SET_FLAG(bc & 0x80000000, F_CF); + CONDITIONAL_SET_FLAG(XOR2(bc >> 30), F_OF); + CONDITIONAL_SET_FLAG(bc & 0x8, F_AF); + return res; +} + +/**************************************************************************** +REMARKS: +Implements the SUB instruction and side effects. +****************************************************************************/ +u8 sub_byte(u8 d, u8 s) +{ + register u32 res; /* all operands in native machine order */ + register u32 bc; + + res = d - s; + CONDITIONAL_SET_FLAG(res & 0x80, F_SF); + CONDITIONAL_SET_FLAG((res & 0xff) == 0, F_ZF); + CONDITIONAL_SET_FLAG(PARITY(res & 0xff), F_PF); + + /* calculate the borrow chain. See note at top */ + bc = (res & (~d | s)) | (~d & s); + CONDITIONAL_SET_FLAG(bc & 0x80, F_CF); + CONDITIONAL_SET_FLAG(XOR2(bc >> 6), F_OF); + CONDITIONAL_SET_FLAG(bc & 0x8, F_AF); + return (u8)res; +} + +/**************************************************************************** +REMARKS: +Implements the SUB instruction and side effects. +****************************************************************************/ +u16 sub_word(u16 d, u16 s) +{ + register u32 res; /* all operands in native machine order */ + register u32 bc; + + res = d - s; + CONDITIONAL_SET_FLAG(res & 0x8000, F_SF); + CONDITIONAL_SET_FLAG((res & 0xffff) == 0, F_ZF); + CONDITIONAL_SET_FLAG(PARITY(res & 0xff), F_PF); + + /* calculate the borrow chain. See note at top */ + bc = (res & (~d | s)) | (~d & s); + CONDITIONAL_SET_FLAG(bc & 0x8000, F_CF); + CONDITIONAL_SET_FLAG(XOR2(bc >> 14), F_OF); + CONDITIONAL_SET_FLAG(bc & 0x8, F_AF); + return (u16)res; +} + +/**************************************************************************** +REMARKS: +Implements the SUB instruction and side effects. +****************************************************************************/ +u32 sub_long(u32 d, u32 s) +{ + register u32 res; /* all operands in native machine order */ + register u32 bc; + + res = d - s; + CONDITIONAL_SET_FLAG(res & 0x80000000, F_SF); + CONDITIONAL_SET_FLAG((res & 0xffffffff) == 0, F_ZF); + CONDITIONAL_SET_FLAG(PARITY(res & 0xff), F_PF); + + /* calculate the borrow chain. See note at top */ + bc = (res & (~d | s)) | (~d & s); + CONDITIONAL_SET_FLAG(bc & 0x80000000, F_CF); + CONDITIONAL_SET_FLAG(XOR2(bc >> 30), F_OF); + CONDITIONAL_SET_FLAG(bc & 0x8, F_AF); + return res; +} + +/**************************************************************************** +REMARKS: +Implements the TEST instruction and side effects. +****************************************************************************/ +void test_byte(u8 d, u8 s) +{ + register u32 res; /* all operands in native machine order */ + + res = d & s; + + CLEAR_FLAG(F_OF); + CONDITIONAL_SET_FLAG(res & 0x80, F_SF); + CONDITIONAL_SET_FLAG(res == 0, F_ZF); + CONDITIONAL_SET_FLAG(PARITY(res & 0xff), F_PF); + /* AF == dont care */ + CLEAR_FLAG(F_CF); +} + +/**************************************************************************** +REMARKS: +Implements the TEST instruction and side effects. +****************************************************************************/ +void test_word(u16 d, u16 s) +{ + register u32 res; /* all operands in native machine order */ + + res = d & s; + + CLEAR_FLAG(F_OF); + CONDITIONAL_SET_FLAG(res & 0x8000, F_SF); + CONDITIONAL_SET_FLAG(res == 0, F_ZF); + CONDITIONAL_SET_FLAG(PARITY(res & 0xff), F_PF); + /* AF == dont care */ + CLEAR_FLAG(F_CF); +} + +/**************************************************************************** +REMARKS: +Implements the TEST instruction and side effects. +****************************************************************************/ +void test_long(u32 d, u32 s) +{ + register u32 res; /* all operands in native machine order */ + + res = d & s; + + CLEAR_FLAG(F_OF); + CONDITIONAL_SET_FLAG(res & 0x80000000, F_SF); + CONDITIONAL_SET_FLAG(res == 0, F_ZF); + CONDITIONAL_SET_FLAG(PARITY(res & 0xff), F_PF); + /* AF == dont care */ + CLEAR_FLAG(F_CF); +} + +/**************************************************************************** +REMARKS: +Implements the XOR instruction and side effects. +****************************************************************************/ +u8 xor_byte(u8 d, u8 s) +{ + register u8 res; /* all operands in native machine order */ + + res = d ^ s; + CLEAR_FLAG(F_OF); + CONDITIONAL_SET_FLAG(res & 0x80, F_SF); + CONDITIONAL_SET_FLAG(res == 0, F_ZF); + CONDITIONAL_SET_FLAG(PARITY(res), F_PF); + CLEAR_FLAG(F_CF); + CLEAR_FLAG(F_AF); + return res; +} + +/**************************************************************************** +REMARKS: +Implements the XOR instruction and side effects. +****************************************************************************/ +u16 xor_word(u16 d, u16 s) +{ + register u16 res; /* all operands in native machine order */ + + res = d ^ s; + CLEAR_FLAG(F_OF); + CONDITIONAL_SET_FLAG(res & 0x8000, F_SF); + CONDITIONAL_SET_FLAG(res == 0, F_ZF); + CONDITIONAL_SET_FLAG(PARITY(res & 0xff), F_PF); + CLEAR_FLAG(F_CF); + CLEAR_FLAG(F_AF); + return res; +} + +/**************************************************************************** +REMARKS: +Implements the XOR instruction and side effects. +****************************************************************************/ +u32 xor_long(u32 d, u32 s) +{ + register u32 res; /* all operands in native machine order */ + + res = d ^ s; + CLEAR_FLAG(F_OF); + CONDITIONAL_SET_FLAG(res & 0x80000000, F_SF); + CONDITIONAL_SET_FLAG(res == 0, F_ZF); + CONDITIONAL_SET_FLAG(PARITY(res & 0xff), F_PF); + CLEAR_FLAG(F_CF); + CLEAR_FLAG(F_AF); + return res; +} + +/**************************************************************************** +REMARKS: +Implements the IMUL instruction and side effects. +****************************************************************************/ +void imul_byte(u8 s) +{ + s16 res = (s16)((s8)M.x86.R_AL * (s8)s); + + M.x86.R_AX = res; + if (((M.x86.R_AL & 0x80) == 0 && M.x86.R_AH == 0x00) || + ((M.x86.R_AL & 0x80) != 0 && M.x86.R_AH == 0xFF)) { + CLEAR_FLAG(F_CF); + CLEAR_FLAG(F_OF); + } else { + SET_FLAG(F_CF); + SET_FLAG(F_OF); + } +} + +/**************************************************************************** +REMARKS: +Implements the IMUL instruction and side effects. +****************************************************************************/ +void imul_word(u16 s) +{ + s32 res = (s16)M.x86.R_AX * (s16)s; + + M.x86.R_AX = (u16)res; + M.x86.R_DX = (u16)(res >> 16); + if (((M.x86.R_AX & 0x8000) == 0 && M.x86.R_DX == 0x00) || + ((M.x86.R_AX & 0x8000) != 0 && M.x86.R_DX == 0xFF)) { + CLEAR_FLAG(F_CF); + CLEAR_FLAG(F_OF); + } else { + SET_FLAG(F_CF); + SET_FLAG(F_OF); + } +} + +/**************************************************************************** +REMARKS: +Implements the IMUL instruction and side effects. +****************************************************************************/ +void imul_long_direct(u32 *res_lo, u32* res_hi,u32 d, u32 s) +{ +#ifdef __HAS_LONG_LONG__ + s64 res = (s64)(s32)d * (s32)s; + + *res_lo = (u32)res; + *res_hi = (u32)(res >> 32); +#else + u32 d_lo,d_hi,d_sign; + u32 s_lo,s_hi,s_sign; + u32 rlo_lo,rlo_hi,rhi_lo; + + if ((d_sign = d & 0x80000000) != 0) + d = -d; + d_lo = d & 0xFFFF; + d_hi = d >> 16; + if ((s_sign = s & 0x80000000) != 0) + s = -s; + s_lo = s & 0xFFFF; + s_hi = s >> 16; + rlo_lo = d_lo * s_lo; + rlo_hi = (d_hi * s_lo + d_lo * s_hi) + (rlo_lo >> 16); + rhi_lo = d_hi * s_hi + (rlo_hi >> 16); + *res_lo = (rlo_hi << 16) | (rlo_lo & 0xFFFF); + *res_hi = rhi_lo; + if (d_sign != s_sign) { + d = ~*res_lo; + s = (((d & 0xFFFF) + 1) >> 16) + (d >> 16); + *res_lo = ~*res_lo+1; + *res_hi = ~*res_hi+(s >> 16); + } +#endif +} + +/**************************************************************************** +REMARKS: +Implements the IMUL instruction and side effects. +****************************************************************************/ +void imul_long(u32 s) +{ + imul_long_direct(&M.x86.R_EAX,&M.x86.R_EDX,M.x86.R_EAX,s); + if (((M.x86.R_EAX & 0x80000000) == 0 && M.x86.R_EDX == 0x00) || + ((M.x86.R_EAX & 0x80000000) != 0 && M.x86.R_EDX == 0xFF)) { + CLEAR_FLAG(F_CF); + CLEAR_FLAG(F_OF); + } else { + SET_FLAG(F_CF); + SET_FLAG(F_OF); + } +} + +/**************************************************************************** +REMARKS: +Implements the MUL instruction and side effects. +****************************************************************************/ +void mul_byte(u8 s) +{ + u16 res = (u16)(M.x86.R_AL * s); + + M.x86.R_AX = res; + if (M.x86.R_AH == 0) { + CLEAR_FLAG(F_CF); + CLEAR_FLAG(F_OF); + } else { + SET_FLAG(F_CF); + SET_FLAG(F_OF); + } +} + +/**************************************************************************** +REMARKS: +Implements the MUL instruction and side effects. +****************************************************************************/ +void mul_word(u16 s) +{ + u32 res = M.x86.R_AX * s; + + M.x86.R_AX = (u16)res; + M.x86.R_DX = (u16)(res >> 16); + if (M.x86.R_DX == 0) { + CLEAR_FLAG(F_CF); + CLEAR_FLAG(F_OF); + } else { + SET_FLAG(F_CF); + SET_FLAG(F_OF); + } +} + +/**************************************************************************** +REMARKS: +Implements the MUL instruction and side effects. +****************************************************************************/ +void mul_long(u32 s) +{ +#ifdef __HAS_LONG_LONG__ + u64 res = (u64)M.x86.R_EAX * s; + + M.x86.R_EAX = (u32)res; + M.x86.R_EDX = (u32)(res >> 32); +#else + u32 a,a_lo,a_hi; + u32 s_lo,s_hi; + u32 rlo_lo,rlo_hi,rhi_lo; + + a = M.x86.R_EAX; + a_lo = a & 0xFFFF; + a_hi = a >> 16; + s_lo = s & 0xFFFF; + s_hi = s >> 16; + rlo_lo = a_lo * s_lo; + rlo_hi = (a_hi * s_lo + a_lo * s_hi) + (rlo_lo >> 16); + rhi_lo = a_hi * s_hi + (rlo_hi >> 16); + M.x86.R_EAX = (rlo_hi << 16) | (rlo_lo & 0xFFFF); + M.x86.R_EDX = rhi_lo; +#endif + + if (M.x86.R_EDX == 0) { + CLEAR_FLAG(F_CF); + CLEAR_FLAG(F_OF); + } else { + SET_FLAG(F_CF); + SET_FLAG(F_OF); + } +} + +/**************************************************************************** +REMARKS: +Implements the IDIV instruction and side effects. +****************************************************************************/ +void idiv_byte(u8 s) +{ + s32 dvd, div, mod; + + dvd = (s16)M.x86.R_AX; + if (s == 0) { + x86emu_intr_raise(0); + return; + } + div = dvd / (s8)s; + mod = dvd % (s8)s; + if (abs(div) > 0x7f) { + x86emu_intr_raise(0); + return; + } + M.x86.R_AL = (s8) div; + M.x86.R_AH = (s8) mod; +} + +/**************************************************************************** +REMARKS: +Implements the IDIV instruction and side effects. +****************************************************************************/ +void idiv_word(u16 s) +{ + s32 dvd, div, mod; + + dvd = (((s32)M.x86.R_DX) << 16) | M.x86.R_AX; + if (s == 0) { + x86emu_intr_raise(0); + return; + } + div = dvd / (s16)s; + mod = dvd % (s16)s; + if (abs(div) > 0x7fff) { + x86emu_intr_raise(0); + return; + } + CLEAR_FLAG(F_CF); + CLEAR_FLAG(F_SF); + CONDITIONAL_SET_FLAG(div == 0, F_ZF); + CONDITIONAL_SET_FLAG(PARITY(mod & 0xff), F_PF); + + M.x86.R_AX = (u16)div; + M.x86.R_DX = (u16)mod; +} + +/**************************************************************************** +REMARKS: +Implements the IDIV instruction and side effects. +****************************************************************************/ +void idiv_long(u32 s) +{ +#ifdef __HAS_LONG_LONG__ + s64 dvd, div, mod; + + dvd = (((s64)M.x86.R_EDX) << 32) | M.x86.R_EAX; + if (s == 0) { + x86emu_intr_raise(0); + return; + } + div = dvd / (s32)s; + mod = dvd % (s32)s; + if (((u64)div >> 32) != 0 && + ((u64)div >> 32) != 0xFFFFFFFFUL) { + x86emu_intr_raise(0); + return; + } +#else + s32 div = 0, mod; + s32 h_dvd = M.x86.R_EDX; + u32 l_dvd = M.x86.R_EAX; + u32 abs_s = s & 0x7FFFFFFF; + u32 abs_h_dvd = h_dvd & 0x7FFFFFFF; + u32 h_s = abs_s >> 1; + u32 l_s = abs_s << 31; + int counter = 31; + int carry; + + if (s == 0) { + x86emu_intr_raise(0); + return; + } + do { + div <<= 1; + carry = (l_dvd >= l_s) ? 0 : 1; + + if (abs_h_dvd < (h_s + carry)) { + h_s >>= 1; + l_s = abs_s << (--counter); + continue; + } else { + abs_h_dvd -= (h_s + carry); + l_dvd = carry ? ((0xFFFFFFFF - l_s) + l_dvd + 1) + : (l_dvd - l_s); + h_s >>= 1; + l_s = abs_s << (--counter); + div |= 1; + continue; + } + + } while (counter > -1); + /* overflow */ + if (abs_h_dvd || (l_dvd > abs_s)) { + x86emu_intr_raise(0); + return; + } + /* sign */ + div |= ((h_dvd & 0x10000000) ^ (s & 0x10000000)); + mod = l_dvd; + +#endif + CLEAR_FLAG(F_CF); + CLEAR_FLAG(F_AF); + CLEAR_FLAG(F_SF); + SET_FLAG(F_ZF); + CONDITIONAL_SET_FLAG(PARITY(mod & 0xff), F_PF); + + M.x86.R_EAX = (u32)div; + M.x86.R_EDX = (u32)mod; +} + +/**************************************************************************** +REMARKS: +Implements the DIV instruction and side effects. +****************************************************************************/ +void div_byte(u8 s) +{ + u32 dvd, div, mod; + + dvd = M.x86.R_AX; + if (s == 0) { + x86emu_intr_raise(0); + return; + } + div = dvd / (u8)s; + mod = dvd % (u8)s; + if (div > 0xff) { + x86emu_intr_raise(0); + return; + } + M.x86.R_AL = (u8)div; + M.x86.R_AH = (u8)mod; +} + +/**************************************************************************** +REMARKS: +Implements the DIV instruction and side effects. +****************************************************************************/ +void div_word(u16 s) +{ + u32 dvd, div, mod; + + dvd = (((u32)M.x86.R_DX) << 16) | M.x86.R_AX; + if (s == 0) { + x86emu_intr_raise(0); + return; + } + div = dvd / (u16)s; + mod = dvd % (u16)s; + if (div > 0xffff) { + x86emu_intr_raise(0); + return; + } + CLEAR_FLAG(F_CF); + CLEAR_FLAG(F_SF); + CONDITIONAL_SET_FLAG(div == 0, F_ZF); + CONDITIONAL_SET_FLAG(PARITY(mod & 0xff), F_PF); + + M.x86.R_AX = (u16)div; + M.x86.R_DX = (u16)mod; +} + +/**************************************************************************** +REMARKS: +Implements the DIV instruction and side effects. +****************************************************************************/ +void div_long(u32 s) +{ +#ifdef __HAS_LONG_LONG__ + u64 dvd, div, mod; + + dvd = (((u64)M.x86.R_EDX) << 32) | M.x86.R_EAX; + if (s == 0) { + x86emu_intr_raise(0); + return; + } + div = dvd / (u32)s; + mod = dvd % (u32)s; + if (div > 0xffffffffULL) { + x86emu_intr_raise(0); + return; + } +#else + s32 div = 0, mod; + s32 h_dvd = M.x86.R_EDX; + u32 l_dvd = M.x86.R_EAX; + + u32 h_s = s; + u32 l_s = 0; + int counter = 32; + int carry; + + if (s == 0) { + x86emu_intr_raise(0); + return; + } + do { + div <<= 1; + carry = (l_dvd >= l_s) ? 0 : 1; + + if (h_dvd < (h_s + carry)) { + h_s >>= 1; + l_s = s << (--counter); + continue; + } else { + h_dvd -= (h_s + carry); + l_dvd = carry ? ((0xFFFFFFFF - l_s) + l_dvd + 1) + : (l_dvd - l_s); + h_s >>= 1; + l_s = s << (--counter); + div |= 1; + continue; + } + + } while (counter > -1); + /* overflow */ + if (h_dvd || (l_dvd > s)) { + x86emu_intr_raise(0); + return; + } + mod = l_dvd; +#endif + CLEAR_FLAG(F_CF); + CLEAR_FLAG(F_AF); + CLEAR_FLAG(F_SF); + SET_FLAG(F_ZF); + CONDITIONAL_SET_FLAG(PARITY(mod & 0xff), F_PF); + + M.x86.R_EAX = (u32)div; + M.x86.R_EDX = (u32)mod; +} + +/**************************************************************************** +REMARKS: +Implements the IN string instruction and side effects. +****************************************************************************/ +void ins(int size) +{ + int inc = size; + + if (ACCESS_FLAG(F_DF)) { + inc = -size; + } + if (M.x86.mode & (SYSMODE_PREFIX_REPE | SYSMODE_PREFIX_REPNE)) { + /* dont care whether REPE or REPNE */ + /* in until CX is ZERO. */ + u32 count = ((M.x86.mode & SYSMODE_PREFIX_DATA) ? + M.x86.R_ECX : M.x86.R_CX); + switch (size) { + case 1: + while (count--) { + store_data_byte_abs(M.x86.R_ES, M.x86.R_DI, + (*sys_inb)(M.x86.R_DX)); + M.x86.R_DI += inc; + } + break; + + case 2: + while (count--) { + store_data_word_abs(M.x86.R_ES, M.x86.R_DI, + (*sys_inw)(M.x86.R_DX)); + M.x86.R_DI += inc; + } + break; + case 4: + while (count--) { + store_data_long_abs(M.x86.R_ES, M.x86.R_DI, + (*sys_inl)(M.x86.R_DX)); + M.x86.R_DI += inc; + break; + } + } + M.x86.R_CX = 0; + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + M.x86.R_ECX = 0; + } + M.x86.mode &= ~(SYSMODE_PREFIX_REPE | SYSMODE_PREFIX_REPNE); + } else { + switch (size) { + case 1: + store_data_byte_abs(M.x86.R_ES, M.x86.R_DI, + (*sys_inb)(M.x86.R_DX)); + break; + case 2: + store_data_word_abs(M.x86.R_ES, M.x86.R_DI, + (*sys_inw)(M.x86.R_DX)); + break; + case 4: + store_data_long_abs(M.x86.R_ES, M.x86.R_DI, + (*sys_inl)(M.x86.R_DX)); + break; + } + M.x86.R_DI += inc; + } +} + +/**************************************************************************** +REMARKS: +Implements the OUT string instruction and side effects. +****************************************************************************/ +void outs(int size) +{ + int inc = size; + + if (ACCESS_FLAG(F_DF)) { + inc = -size; + } + if (M.x86.mode & (SYSMODE_PREFIX_REPE | SYSMODE_PREFIX_REPNE)) { + /* dont care whether REPE or REPNE */ + /* out until CX is ZERO. */ + u32 count = ((M.x86.mode & SYSMODE_PREFIX_DATA) ? + M.x86.R_ECX : M.x86.R_CX); + switch (size) { + case 1: + while (count--) { + (*sys_outb)(M.x86.R_DX, + fetch_data_byte_abs(M.x86.R_ES, M.x86.R_SI)); + M.x86.R_SI += inc; + } + break; + + case 2: + while (count--) { + (*sys_outw)(M.x86.R_DX, + fetch_data_word_abs(M.x86.R_ES, M.x86.R_SI)); + M.x86.R_SI += inc; + } + break; + case 4: + while (count--) { + (*sys_outl)(M.x86.R_DX, + fetch_data_long_abs(M.x86.R_ES, M.x86.R_SI)); + M.x86.R_SI += inc; + break; + } + } + M.x86.R_CX = 0; + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + M.x86.R_ECX = 0; + } + M.x86.mode &= ~(SYSMODE_PREFIX_REPE | SYSMODE_PREFIX_REPNE); + } else { + switch (size) { + case 1: + (*sys_outb)(M.x86.R_DX, + fetch_data_byte_abs(M.x86.R_ES, M.x86.R_SI)); + break; + case 2: + (*sys_outw)(M.x86.R_DX, + fetch_data_word_abs(M.x86.R_ES, M.x86.R_SI)); + break; + case 4: + (*sys_outl)(M.x86.R_DX, + fetch_data_long_abs(M.x86.R_ES, M.x86.R_SI)); + break; + } + M.x86.R_SI += inc; + } +} + +/**************************************************************************** +PARAMETERS: +addr - Address to fetch word from + +REMARKS: +Fetches a word from emulator memory using an absolute address. +****************************************************************************/ +u16 mem_access_word(int addr) +{ +DB( if (CHECK_MEM_ACCESS()) + x86emu_check_mem_access(addr);) + return (*sys_rdw)(addr); +} + +/**************************************************************************** +REMARKS: +Pushes a word onto the stack. + +NOTE: Do not inline this, as (*sys_wrX) is already inline! +****************************************************************************/ +void push_word(u16 w) +{ +DB( if (CHECK_SP_ACCESS()) + x86emu_check_sp_access();) + M.x86.R_SP -= 2; + (*sys_wrw)(((u32)M.x86.R_SS << 4) + M.x86.R_SP, w); +} + +/**************************************************************************** +REMARKS: +Pushes a long onto the stack. + +NOTE: Do not inline this, as (*sys_wrX) is already inline! +****************************************************************************/ +void push_long(u32 w) +{ +DB( if (CHECK_SP_ACCESS()) + x86emu_check_sp_access();) + M.x86.R_SP -= 4; + (*sys_wrl)(((u32)M.x86.R_SS << 4) + M.x86.R_SP, w); +} + +/**************************************************************************** +REMARKS: +Pops a word from the stack. + +NOTE: Do not inline this, as (*sys_rdX) is already inline! +****************************************************************************/ +u16 pop_word(void) +{ + register u16 res; + +DB( if (CHECK_SP_ACCESS()) + x86emu_check_sp_access();) + res = (*sys_rdw)(((u32)M.x86.R_SS << 4) + M.x86.R_SP); + M.x86.R_SP += 2; + return res; +} + +/**************************************************************************** +REMARKS: +Pops a long from the stack. + +NOTE: Do not inline this, as (*sys_rdX) is already inline! +****************************************************************************/ +u32 pop_long(void) +{ + register u32 res; + +DB( if (CHECK_SP_ACCESS()) + x86emu_check_sp_access();) + res = (*sys_rdl)(((u32)M.x86.R_SS << 4) + M.x86.R_SP); + M.x86.R_SP += 4; + return res; +} + diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/arch/nvalloc/unix/x86emu/sys.c nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/arch/nvalloc/unix/x86emu/sys.c --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/arch/nvalloc/unix/x86emu/sys.c 1970-01-01 00:00:00.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/arch/nvalloc/unix/x86emu/sys.c 2024-03-05 22:12:51.000000000 +0000 @@ -0,0 +1,663 @@ +/**************************************************************************** +* +* Realmode X86 Emulator Library +* +* Copyright (C) 1996-1999 SciTech Software, Inc. +* Copyright (C) David Mosberger-Tang +* Copyright (C) 1999 Egbert Eich +* +* ======================================================================== +* +* Permission to use, copy, modify, distribute, and sell this software and +* its documentation for any purpose is hereby granted without fee, +* provided that the above copyright notice appear in all copies and that +* both that copyright notice and this permission notice appear in +* supporting documentation, and that the name of the authors not be used +* in advertising or publicity pertaining to distribution of the software +* without specific, written prior permission. The authors makes no +* representations about the suitability of this software for any purpose. +* It is provided "as is" without express or implied warranty. +* +* THE AUTHORS DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOFTWARE, +* INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO +* EVENT SHALL THE AUTHORS BE LIABLE FOR ANY SPECIAL, INDIRECT OR +* CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF +* USE, DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR +* OTHER TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR +* PERFORMANCE OF THIS SOFTWARE. +* +* ======================================================================== +* +* Language: ANSI C +* Environment: Any +* Developer: Kendall Bennett +* +* Description: This file includes subroutines which are related to +* programmed I/O and memory access. Included in this module +* are default functions with limited usefulness. For real +* uses these functions will most likely be overriden by the +* user library. +* +****************************************************************************/ + +#include "x86emu/x86emu.h" +#include "x86emu/x86emui.h" +#include "x86emu/regs.h" +#include "x86emu/debug.h" +#include "x86emu/prim_ops.h" +#ifndef NO_SYS_HEADERS +#include +#endif +/*------------------------- Global Variables ------------------------------*/ + +X86EMU_sysEnv _X86EMU_env; /* Global emulator machine state */ +X86EMU_intrFuncs _X86EMU_intrTab[256]; + +/*----------------------------- Implementation ----------------------------*/ +#if defined(__alpha__) || defined(__alpha) +/* to cope with broken egcs-1.1.2 :-(((( */ + +#define ALPHA_UALOADS +/* + * inline functions to do unaligned accesses + * from linux/include/asm-alpha/unaligned.h + */ + +/* + * EGCS 1.1 knows about arbitrary unaligned loads. Define some + * packed structures to talk about such things with. + */ + +#if defined(__GNUC__) && ((__GNUC__ > 2) || (__GNUC_MINOR__ >= 91)) +struct __una_u64 { unsigned long x __attribute__((packed)); }; +struct __una_u32 { unsigned int x __attribute__((packed)); }; +struct __una_u16 { unsigned short x __attribute__((packed)); }; +#endif + +static __inline__ unsigned long ldq_u(unsigned long * r11) +{ +#if defined(__GNUC__) && ((__GNUC__ > 2) || (__GNUC_MINOR__ >= 91)) + const struct __una_u64 *ptr = (const struct __una_u64 *) r11; + return ptr->x; +#else + unsigned long r1,r2; + __asm__("ldq_u %0,%3\n\t" + "ldq_u %1,%4\n\t" + "extql %0,%2,%0\n\t" + "extqh %1,%2,%1" + :"=&r" (r1), "=&r" (r2) + :"r" (r11), + "m" (*r11), + "m" (*(const unsigned long *)(7+(char *) r11))); + return r1 | r2; +#endif +} + +static __inline__ unsigned long ldl_u(unsigned int * r11) +{ +#if defined(__GNUC__) && ((__GNUC__ > 2) || (__GNUC_MINOR__ >= 91)) + const struct __una_u32 *ptr = (const struct __una_u32 *) r11; + return ptr->x; +#else + unsigned long r1,r2; + __asm__("ldq_u %0,%3\n\t" + "ldq_u %1,%4\n\t" + "extll %0,%2,%0\n\t" + "extlh %1,%2,%1" + :"=&r" (r1), "=&r" (r2) + :"r" (r11), + "m" (*r11), + "m" (*(const unsigned long *)(3+(char *) r11))); + return r1 | r2; +#endif +} + +static __inline__ unsigned long ldw_u(unsigned short * r11) +{ +#if defined(__GNUC__) && ((__GNUC__ > 2) || (__GNUC_MINOR__ >= 91)) + const struct __una_u16 *ptr = (const struct __una_u16 *) r11; + return ptr->x; +#else + unsigned long r1,r2; + __asm__("ldq_u %0,%3\n\t" + "ldq_u %1,%4\n\t" + "extwl %0,%2,%0\n\t" + "extwh %1,%2,%1" + :"=&r" (r1), "=&r" (r2) + :"r" (r11), + "m" (*r11), + "m" (*(const unsigned long *)(1+(char *) r11))); + return r1 | r2; +#endif +} + +/* + * Elemental unaligned stores + */ + +static __inline__ void stq_u(unsigned long r5, unsigned long * r11) +{ +#if defined(__GNUC__) && ((__GNUC__ > 2) || (__GNUC_MINOR__ >= 91)) + struct __una_u64 *ptr = (struct __una_u64 *) r11; + ptr->x = r5; +#else + unsigned long r1,r2,r3,r4; + + __asm__("ldq_u %3,%1\n\t" + "ldq_u %2,%0\n\t" + "insqh %6,%7,%5\n\t" + "insql %6,%7,%4\n\t" + "mskqh %3,%7,%3\n\t" + "mskql %2,%7,%2\n\t" + "bis %3,%5,%3\n\t" + "bis %2,%4,%2\n\t" + "stq_u %3,%1\n\t" + "stq_u %2,%0" + :"=m" (*r11), + "=m" (*(unsigned long *)(7+(char *) r11)), + "=&r" (r1), "=&r" (r2), "=&r" (r3), "=&r" (r4) + :"r" (r5), "r" (r11)); +#endif +} + +static __inline__ void stl_u(unsigned long r5, unsigned int * r11) +{ +#if defined(__GNUC__) && ((__GNUC__ > 2) || (__GNUC_MINOR__ >= 91)) + struct __una_u32 *ptr = (struct __una_u32 *) r11; + ptr->x = r5; +#else + unsigned long r1,r2,r3,r4; + + __asm__("ldq_u %3,%1\n\t" + "ldq_u %2,%0\n\t" + "inslh %6,%7,%5\n\t" + "insll %6,%7,%4\n\t" + "msklh %3,%7,%3\n\t" + "mskll %2,%7,%2\n\t" + "bis %3,%5,%3\n\t" + "bis %2,%4,%2\n\t" + "stq_u %3,%1\n\t" + "stq_u %2,%0" + :"=m" (*r11), + "=m" (*(unsigned long *)(3+(char *) r11)), + "=&r" (r1), "=&r" (r2), "=&r" (r3), "=&r" (r4) + :"r" (r5), "r" (r11)); +#endif +} + +static __inline__ void stw_u(unsigned long r5, unsigned short * r11) +{ +#if defined(__GNUC__) && ((__GNUC__ > 2) || (__GNUC_MINOR__ >= 91)) + struct __una_u16 *ptr = (struct __una_u16 *) r11; + ptr->x = r5; +#else + unsigned long r1,r2,r3,r4; + + __asm__("ldq_u %3,%1\n\t" + "ldq_u %2,%0\n\t" + "inswh %6,%7,%5\n\t" + "inswl %6,%7,%4\n\t" + "mskwh %3,%7,%3\n\t" + "mskwl %2,%7,%2\n\t" + "bis %3,%5,%3\n\t" + "bis %2,%4,%2\n\t" + "stq_u %3,%1\n\t" + "stq_u %2,%0" + :"=m" (*r11), + "=m" (*(unsigned long *)(1+(char *) r11)), + "=&r" (r1), "=&r" (r2), "=&r" (r3), "=&r" (r4) + :"r" (r5), "r" (r11)); +#endif +} + +#elif defined(__GNUC__) && ((__GNUC__ < 3)) && \ + (defined (__ia64__) || defined (ia64__)) +#define IA64_UALOADS +/* + * EGCS 1.1 knows about arbitrary unaligned loads. Define some + * packed structures to talk about such things with. + */ +struct __una_u64 { unsigned long x __attribute__((packed)); }; +struct __una_u32 { unsigned int x __attribute__((packed)); }; +struct __una_u16 { unsigned short x __attribute__((packed)); }; + +static __inline__ unsigned long +__uldq (const unsigned long * r11) +{ + const struct __una_u64 *ptr = (const struct __una_u64 *) r11; + return ptr->x; +} + +static __inline__ unsigned long +uldl (const unsigned int * r11) +{ + const struct __una_u32 *ptr = (const struct __una_u32 *) r11; + return ptr->x; +} + +static __inline__ unsigned long +uldw (const unsigned short * r11) +{ + const struct __una_u16 *ptr = (const struct __una_u16 *) r11; + return ptr->x; +} + +static __inline__ void +ustq (unsigned long r5, unsigned long * r11) +{ + struct __una_u64 *ptr = (struct __una_u64 *) r11; + ptr->x = r5; +} + +static __inline__ void +ustl (unsigned long r5, unsigned int * r11) +{ + struct __una_u32 *ptr = (struct __una_u32 *) r11; + ptr->x = r5; +} + +static __inline__ void +ustw (unsigned long r5, unsigned short * r11) +{ + struct __una_u16 *ptr = (struct __una_u16 *) r11; + ptr->x = r5; +} + +#endif + +/**************************************************************************** +PARAMETERS: +addr - Emulator memory address to read + +RETURNS: +Byte value read from emulator memory. + +REMARKS: +Reads a byte value from the emulator memory. +****************************************************************************/ +u8 X86API rdb( + u32 addr) +{ + u8 val; + + if (addr > M.mem_size - 1) { + DB(NV_PRINTF(LEVEL_INFO, "mem_read: address %#x out of range!\n", addr);) + HALT_SYS(); + } + val = *(u8*)(M.mem_base + addr); +DB( if (DEBUG_MEM_TRACE()) + NV_PRINTF(LEVEL_INFO, "%#08x 1 -> %#x\n", addr, val);) + return val; +} + +/**************************************************************************** +PARAMETERS: +addr - Emulator memory address to read + +RETURNS: +Word value read from emulator memory. + +REMARKS: +Reads a word value from the emulator memory. +****************************************************************************/ +u16 X86API rdw( + u32 addr) +{ + u16 val = 0; + + if (addr > M.mem_size - 2) { + DB(NV_PRINTF(LEVEL_INFO, "mem_read: address %#x out of range!\n", addr);) + HALT_SYS(); + } +#ifdef __BIG_ENDIAN__ + if (addr & 0x1) { + val = (*(u8*)(M.mem_base + addr) | + (*(u8*)(M.mem_base + addr + 1) << 8)); + } + else +#endif +#if defined(ALPHA_UALOADS) + val = ldw_u((u16*)(M.mem_base + addr)); +#elif defined(IA64_UALOADS) + val = uldw((u16*)(M.mem_base + addr)); +#else + val = *(u16*)(M.mem_base + addr); +#endif +DB( if (DEBUG_MEM_TRACE()) + NV_PRINTF(LEVEL_INFO, "%#08x 2 -> %#x\n", addr, val);) + return val; +} + +/**************************************************************************** +PARAMETERS: +addr - Emulator memory address to read + +RETURNS: +Long value read from emulator memory. +REMARKS: +Reads a long value from the emulator memory. +****************************************************************************/ +u32 X86API rdl( + u32 addr) +{ + u32 val = 0; + + if (addr > M.mem_size - 4) { + DB(NV_PRINTF(LEVEL_INFO, "mem_read: address %#x out of range!\n", addr);) + HALT_SYS(); + } +#ifdef __BIG_ENDIAN__ + if (addr & 0x3) { + val = (*(u8*)(M.mem_base + addr + 0) | + (*(u8*)(M.mem_base + addr + 1) << 8) | + (*(u8*)(M.mem_base + addr + 2) << 16) | + (*(u8*)(M.mem_base + addr + 3) << 24)); + } + else +#endif +#if defined(ALPHA_UALOADS) + val = ldl_u((u32*)(M.mem_base + addr)); +#elif defined(IA64_UALOADS) + val = uldl((u32*)(M.mem_base + addr)); +#else + val = *(u32*)(M.mem_base + addr); +#endif +DB( if (DEBUG_MEM_TRACE()) + NV_PRINTF(LEVEL_INFO, "%#08x 4 -> %#x\n", addr, val);) + return val; +} + +/**************************************************************************** +PARAMETERS: +addr - Emulator memory address to read +val - Value to store + +REMARKS: +Writes a byte value to emulator memory. +****************************************************************************/ +void X86API wrb( + u32 addr, + u8 val) +{ +DB( if (DEBUG_MEM_TRACE()) + NV_PRINTF(LEVEL_INFO, "%#08x 1 <- %#x\n", addr, val);) + if (addr > M.mem_size - 1) { + DB(NV_PRINTF(LEVEL_INFO, "mem_write: address %#x out of range!\n", addr);) + HALT_SYS(); + } + *(u8*)(M.mem_base + addr) = val; +} + +/**************************************************************************** +PARAMETERS: +addr - Emulator memory address to read +val - Value to store + +REMARKS: +Writes a word value to emulator memory. +****************************************************************************/ +void X86API wrw( + u32 addr, + u16 val) +{ +DB( if (DEBUG_MEM_TRACE()) + NV_PRINTF(LEVEL_INFO, "%#08x 2 <- %#x\n", addr, val);) + if (addr > M.mem_size - 2) { + DB(NV_PRINTF(LEVEL_INFO, "mem_write: address %#x out of range!\n", addr);) + HALT_SYS(); + } +#ifdef __BIG_ENDIAN__ + if (addr & 0x1) { + *(u8*)(M.mem_base + addr + 0) = (val >> 0) & 0xff; + *(u8*)(M.mem_base + addr + 1) = (val >> 8) & 0xff; + } + else +#endif +#if defined(ALPHA_UALOADS) + stw_u(val,(u16*)(M.mem_base + addr)); +#elif defined(IA64_UALOADS) + ustw(val,(u16*)(M.mem_base + addr)); +#else + *(u16*)(M.mem_base + addr) = val; +#endif +} + +/**************************************************************************** +PARAMETERS: +addr - Emulator memory address to read +val - Value to store + +REMARKS: +Writes a long value to emulator memory. +****************************************************************************/ +void X86API wrl( + u32 addr, + u32 val) +{ +DB( if (DEBUG_MEM_TRACE()) + NV_PRINTF(LEVEL_INFO, "%#08x 4 <- %#x\n", addr, val);) + if (addr > M.mem_size - 4) { + DB(NV_PRINTF(LEVEL_INFO, "mem_write: address %#x out of range!\n", addr);) + HALT_SYS(); + } +#ifdef __BIG_ENDIAN__ + if (addr & 0x1) { + *(u8*)(M.mem_base + addr + 0) = (val >> 0) & 0xff; + *(u8*)(M.mem_base + addr + 1) = (val >> 8) & 0xff; + *(u8*)(M.mem_base + addr + 2) = (val >> 16) & 0xff; + *(u8*)(M.mem_base + addr + 3) = (val >> 24) & 0xff; + } + else +#endif +#if defined(ALPHA_UALOADS) + stl_u(val,(u32*)(M.mem_base + addr)); +#elif defined(IA64_UALOADS) + ustl(val,(u32*)(M.mem_base + addr)); +#else + *(u32*)(M.mem_base + addr) = val; +#endif +} + +/**************************************************************************** +PARAMETERS: +addr - PIO address to read +RETURN: +0 +REMARKS: +Default PIO byte read function. Doesn't perform real inb. +****************************************************************************/ +static u8 X86API p_inb( + X86EMU_pioAddr addr) +{ +DB( if (DEBUG_IO_TRACE()) + NV_PRINTF(LEVEL_INFO, "inb %#04x \n", addr);) + return 0; +} + +/**************************************************************************** +PARAMETERS: +addr - PIO address to read +RETURN: +0 +REMARKS: +Default PIO word read function. Doesn't perform real inw. +****************************************************************************/ +static u16 X86API p_inw( + X86EMU_pioAddr addr) +{ +DB( if (DEBUG_IO_TRACE()) + NV_PRINTF(LEVEL_INFO, "inw %#04x \n", addr);) + return 0; +} + +/**************************************************************************** +PARAMETERS: +addr - PIO address to read +RETURN: +0 +REMARKS: +Default PIO long read function. Doesn't perform real inl. +****************************************************************************/ +static u32 X86API p_inl( + X86EMU_pioAddr addr) +{ +DB( if (DEBUG_IO_TRACE()) + NV_PRINTF(LEVEL_INFO, "inl %#04x \n", addr);) + return 0; +} + +/**************************************************************************** +PARAMETERS: +addr - PIO address to write +val - Value to store +REMARKS: +Default PIO byte write function. Doesn't perform real outb. +****************************************************************************/ +static void X86API p_outb( + X86EMU_pioAddr addr, + u8 val) +{ +DB( if (DEBUG_IO_TRACE()) + NV_PRINTF(LEVEL_INFO, "outb %#02x -> %#04x \n", val, addr);) + return; +} + +/**************************************************************************** +PARAMETERS: +addr - PIO address to write +val - Value to store +REMARKS: +Default PIO word write function. Doesn't perform real outw. +****************************************************************************/ +static void X86API p_outw( + X86EMU_pioAddr addr, + u16 val) +{ +DB( if (DEBUG_IO_TRACE()) + NV_PRINTF(LEVEL_INFO, "outw %#04x -> %#04x \n", val, addr);) + return; +} + +/**************************************************************************** +PARAMETERS: +addr - PIO address to write +val - Value to store +REMARKS: +Default PIO ;ong write function. Doesn't perform real outl. +****************************************************************************/ +static void X86API p_outl( + X86EMU_pioAddr addr, + u32 val) +{ +DB( if (DEBUG_IO_TRACE()) + NV_PRINTF(LEVEL_INFO, "outl %#08x -> %#04x \n", val, addr);) + return; +} + +/*------------------------- Global Variables ------------------------------*/ + +u8 (X86APIP sys_rdb)(u32 addr) = rdb; +u16 (X86APIP sys_rdw)(u32 addr) = rdw; +u32 (X86APIP sys_rdl)(u32 addr) = rdl; +void (X86APIP sys_wrb)(u32 addr,u8 val) = wrb; +void (X86APIP sys_wrw)(u32 addr,u16 val) = wrw; +void (X86APIP sys_wrl)(u32 addr,u32 val) = wrl; +u8 (X86APIP sys_inb)(X86EMU_pioAddr addr) = p_inb; +u16 (X86APIP sys_inw)(X86EMU_pioAddr addr) = p_inw; +u32 (X86APIP sys_inl)(X86EMU_pioAddr addr) = p_inl; +void (X86APIP sys_outb)(X86EMU_pioAddr addr, u8 val) = p_outb; +void (X86APIP sys_outw)(X86EMU_pioAddr addr, u16 val) = p_outw; +void (X86APIP sys_outl)(X86EMU_pioAddr addr, u32 val) = p_outl; + +/*----------------------------- Setup -------------------------------------*/ + +/**************************************************************************** +PARAMETERS: +funcs - New memory function pointers to make active + +REMARKS: +This function is used to set the pointers to functions which access +memory space, allowing the user application to override these functions +and hook them out as necessary for their application. +****************************************************************************/ +void X86EMU_setupMemFuncs( + X86EMU_memFuncs *funcs) +{ + sys_rdb = funcs->rdb; + sys_rdw = funcs->rdw; + sys_rdl = funcs->rdl; + sys_wrb = funcs->wrb; + sys_wrw = funcs->wrw; + sys_wrl = funcs->wrl; +} + +/**************************************************************************** +PARAMETERS: +funcs - New programmed I/O function pointers to make active + +REMARKS: +This function is used to set the pointers to functions which access +I/O space, allowing the user application to override these functions +and hook them out as necessary for their application. +****************************************************************************/ +void X86EMU_setupPioFuncs( + X86EMU_pioFuncs *funcs) +{ + sys_inb = funcs->inb; + sys_inw = funcs->inw; + sys_inl = funcs->inl; + sys_outb = funcs->outb; + sys_outw = funcs->outw; + sys_outl = funcs->outl; +} + +/**************************************************************************** +PARAMETERS: +funcs - New interrupt vector table to make active + +REMARKS: +This function is used to set the pointers to functions which handle +interrupt processing in the emulator, allowing the user application to +hook interrupts as necessary for their application. Any interrupts that +are not hooked by the user application, and reflected and handled internally +in the emulator via the interrupt vector table. This allows the application +to get control when the code being emulated executes specific software +interrupts. +****************************************************************************/ +void X86EMU_setupIntrFuncs( + X86EMU_intrFuncs funcs[]) +{ + int i; + + for (i=0; i < 256; i++) + _X86EMU_intrTab[i] = NULL; + if (funcs) { + for (i = 0; i < 256; i++) + _X86EMU_intrTab[i] = funcs[i]; + } +} + +/**************************************************************************** +PARAMETERS: +int - New software interrupt to prepare for + +REMARKS: +This function is used to set up the emulator state to exceute a software +interrupt. This can be used by the user application code to allow an +interrupt to be hooked, examined and then reflected back to the emulator +so that the code in the emulator will continue processing the software +interrupt as per normal. This essentially allows system code to actively +hook and handle certain software interrupts as necessary. +****************************************************************************/ +void X86EMU_prepareForInt( + int num) +{ + push_word((u16)M.x86.R_FLG); + CLEAR_FLAG(F_IF); + CLEAR_FLAG(F_TF); + push_word(M.x86.R_CS); + M.x86.R_CS = mem_access_word(num * 4 + 2); + push_word(M.x86.R_IP); + M.x86.R_IP = mem_access_word(num * 4); + M.x86.intr = 0; +} diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/exports_link_command.txt nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/exports_link_command.txt --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/exports_link_command.txt 2023-10-25 20:24:13.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/exports_link_command.txt 2024-03-05 22:15:58.000000000 +0000 @@ -23,6 +23,7 @@ --undefined=rm_isr --undefined=rm_isr_bh --undefined=rm_isr_bh_unlocked +--undefined=rm_is_msix_allowed --undefined=rm_perform_version_check --undefined=rm_power_management --undefined=rm_stop_user_channels @@ -41,6 +42,7 @@ --undefined=rm_release_all_gpus_lock --undefined=rm_shutdown_rm --undefined=rm_power_source_change_event +--undefined=rm_request_dnotifier_state --undefined=rm_write_registry_binary --undefined=rm_write_registry_dword --undefined=rm_write_registry_string @@ -64,11 +66,13 @@ --undefined=rm_dma_buf_put_client_and_device --undefined=rm_gpu_ops_address_space_destroy --undefined=rm_gpu_ops_memory_cpu_ummap +--undefined=rm_gpu_ops_tsg_destroy --undefined=rm_gpu_ops_channel_destroy --undefined=rm_gpu_ops_memory_free --undefined=rm_gpu_ops_create_session --undefined=rm_gpu_ops_memory_alloc_sys --undefined=rm_gpu_ops_address_space_create +--undefined=rm_gpu_ops_tsg_allocate --undefined=rm_gpu_ops_channel_allocate --undefined=rm_gpu_ops_memory_alloc_fb --undefined=rm_gpu_ops_memory_cpu_map @@ -85,6 +89,7 @@ --undefined=rm_gpu_ops_destroy_fault_info --undefined=rm_gpu_ops_has_pending_non_replayable_faults --undefined=rm_gpu_ops_get_non_replayable_faults +--undefined=rm_gpu_ops_flush_replayable_fault_buffer --undefined=rm_gpu_ops_init_access_cntr_info --undefined=rm_gpu_ops_destroy_access_cntr_info --undefined=rm_gpu_ops_enable_access_cntr @@ -118,6 +123,15 @@ --undefined=rm_gpu_ops_paging_channel_push_stream --undefined=rm_gpu_ops_device_create --undefined=rm_gpu_ops_device_destroy +--undefined=rm_gpu_ops_ccsl_sign +--undefined=rm_gpu_ops_ccsl_encrypt +--undefined=rm_gpu_ops_ccsl_encrypt_with_iv +--undefined=rm_gpu_ops_ccsl_context_init +--undefined=rm_gpu_ops_ccsl_context_clear +--undefined=rm_gpu_ops_ccsl_rotate_iv +--undefined=rm_gpu_ops_ccsl_decrypt +--undefined=rm_gpu_ops_ccsl_query_message_pool +--undefined=rm_gpu_ops_ccsl_increment_iv --undefined=rm_log_gpu_crash --undefined=rm_kernel_rmapi_op --undefined=nv_get_hypervisor_type @@ -190,3 +204,4 @@ --undefined=rm_is_iommu_needed_for_sriov --undefined=rm_disable_iomap_wc --undefined=rm_is_altstack_in_use +--undefined=rm_acpi_nvpcf_notify diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/generated/g_access_cntr_buffer_nvoc.c nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_access_cntr_buffer_nvoc.c --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/generated/g_access_cntr_buffer_nvoc.c 2023-10-25 20:26:51.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_access_cntr_buffer_nvoc.c 2024-03-05 22:18:06.000000000 +0000 @@ -127,16 +127,16 @@ return gpuresShareCallback((struct GpuResource *)(((unsigned char *)pGpuResource) + __nvoc_rtti_AccessCounterBuffer_GpuResource.offset), pInvokingClient, pParentRef, pSharePolicy); } -static NV_STATUS __nvoc_thunk_RsResource_accesscntrMapTo(struct AccessCounterBuffer *pResource, RS_RES_MAP_TO_PARAMS *pParams) { - return resMapTo((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_AccessCounterBuffer_RsResource.offset), pParams); +static NV_STATUS __nvoc_thunk_RmResource_accesscntrCheckMemInterUnmap(struct AccessCounterBuffer *pRmResource, NvBool bSubdeviceHandleProvided) { + return rmresCheckMemInterUnmap((struct RmResource *)(((unsigned char *)pRmResource) + __nvoc_rtti_AccessCounterBuffer_RmResource.offset), bSubdeviceHandleProvided); } static NV_STATUS __nvoc_thunk_Notifier_accesscntrGetOrAllocNotifShare(struct AccessCounterBuffer *pNotifier, NvHandle hNotifierClient, NvHandle hNotifierResource, struct NotifShare **ppNotifShare) { return notifyGetOrAllocNotifShare((struct Notifier *)(((unsigned char *)pNotifier) + __nvoc_rtti_AccessCounterBuffer_Notifier.offset), hNotifierClient, hNotifierResource, ppNotifShare); } -static NV_STATUS __nvoc_thunk_RmResource_accesscntrCheckMemInterUnmap(struct AccessCounterBuffer *pRmResource, NvBool bSubdeviceHandleProvided) { - return rmresCheckMemInterUnmap((struct RmResource *)(((unsigned char *)pRmResource) + __nvoc_rtti_AccessCounterBuffer_RmResource.offset), bSubdeviceHandleProvided); +static NV_STATUS __nvoc_thunk_RsResource_accesscntrMapTo(struct AccessCounterBuffer *pResource, RS_RES_MAP_TO_PARAMS *pParams) { + return resMapTo((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_AccessCounterBuffer_RsResource.offset), pParams); } static void __nvoc_thunk_Notifier_accesscntrSetNotificationShare(struct AccessCounterBuffer *pNotifier, struct NotifShare *pNotifShare) { @@ -199,6 +199,10 @@ return notifyUnregisterEvent((struct Notifier *)(((unsigned char *)pNotifier) + __nvoc_rtti_AccessCounterBuffer_Notifier.offset), hNotifierClient, hNotifierResource, hEventClient, hEvent); } +static NV_STATUS __nvoc_thunk_RmResource_accesscntrControlSerialization_Prologue(struct AccessCounterBuffer *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return rmresControlSerialization_Prologue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_AccessCounterBuffer_RmResource.offset), pCallContext, pParams); +} + static NvBool __nvoc_thunk_RsResource_accesscntrCanCopy(struct AccessCounterBuffer *pResource) { return resCanCopy((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_AccessCounterBuffer_RsResource.offset)); } @@ -211,6 +215,10 @@ return resIsDuplicate((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_AccessCounterBuffer_RsResource.offset), hMemory, pDuplicate); } +static void __nvoc_thunk_RmResource_accesscntrControlSerialization_Epilogue(struct AccessCounterBuffer *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + rmresControlSerialization_Epilogue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_AccessCounterBuffer_RmResource.offset), pCallContext, pParams); +} + static PEVENTNOTIFICATION *__nvoc_thunk_Notifier_accesscntrGetNotificationListPtr(struct AccessCounterBuffer *pNotifier) { return notifyGetNotificationListPtr((struct Notifier *)(((unsigned char *)pNotifier) + __nvoc_rtti_AccessCounterBuffer_Notifier.offset)); } @@ -482,11 +490,11 @@ pThis->__accesscntrShareCallback__ = &__nvoc_thunk_GpuResource_accesscntrShareCallback; - pThis->__accesscntrMapTo__ = &__nvoc_thunk_RsResource_accesscntrMapTo; + pThis->__accesscntrCheckMemInterUnmap__ = &__nvoc_thunk_RmResource_accesscntrCheckMemInterUnmap; pThis->__accesscntrGetOrAllocNotifShare__ = &__nvoc_thunk_Notifier_accesscntrGetOrAllocNotifShare; - pThis->__accesscntrCheckMemInterUnmap__ = &__nvoc_thunk_RmResource_accesscntrCheckMemInterUnmap; + pThis->__accesscntrMapTo__ = &__nvoc_thunk_RsResource_accesscntrMapTo; pThis->__accesscntrSetNotificationShare__ = &__nvoc_thunk_Notifier_accesscntrSetNotificationShare; @@ -518,12 +526,16 @@ pThis->__accesscntrUnregisterEvent__ = &__nvoc_thunk_Notifier_accesscntrUnregisterEvent; + pThis->__accesscntrControlSerialization_Prologue__ = &__nvoc_thunk_RmResource_accesscntrControlSerialization_Prologue; + pThis->__accesscntrCanCopy__ = &__nvoc_thunk_RsResource_accesscntrCanCopy; pThis->__accesscntrPreDestruct__ = &__nvoc_thunk_RsResource_accesscntrPreDestruct; pThis->__accesscntrIsDuplicate__ = &__nvoc_thunk_RsResource_accesscntrIsDuplicate; + pThis->__accesscntrControlSerialization_Epilogue__ = &__nvoc_thunk_RmResource_accesscntrControlSerialization_Epilogue; + pThis->__accesscntrGetNotificationListPtr__ = &__nvoc_thunk_Notifier_accesscntrGetNotificationListPtr; pThis->__accesscntrGetNotificationShare__ = &__nvoc_thunk_Notifier_accesscntrGetNotificationShare; @@ -556,13 +568,16 @@ Object *pParentObj; AccessCounterBuffer *pThis; - pThis = portMemAllocNonPaged(sizeof(AccessCounterBuffer)); - if (pThis == NULL) return NV_ERR_NO_MEMORY; + status = __nvoc_handleObjCreateMemAlloc(createFlags, sizeof(AccessCounterBuffer), (void**)&pThis, (void**)ppThis); + if (status != NV_OK) + return status; portMemSet(pThis, 0, sizeof(AccessCounterBuffer)); __nvoc_initRtti(staticCast(pThis, Dynamic), &__nvoc_class_def_AccessCounterBuffer); + pThis->__nvoc_base_GpuResource.__nvoc_base_RmResource.__nvoc_base_RsResource.__nvoc_base_Object.createFlags = createFlags; + if (pParent != NULL && !(createFlags & NVOC_OBJ_CREATE_FLAGS_PARENT_HALSPEC_ONLY)) { pParentObj = dynamicCast(pParent, Object); @@ -578,11 +593,17 @@ if (status != NV_OK) goto __nvoc_objCreate_AccessCounterBuffer_cleanup; *ppThis = pThis; + return NV_OK; __nvoc_objCreate_AccessCounterBuffer_cleanup: // do not call destructors here since the constructor already called them - portMemFree(pThis); + if (createFlags & NVOC_OBJ_CREATE_FLAGS_IN_PLACE_CONSTRUCT) + portMemSet(pThis, 0, sizeof(AccessCounterBuffer)); + else + portMemFree(pThis); + + // coverity[leaked_storage:FALSE] return status; } diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/generated/g_access_cntr_buffer_nvoc.h nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_access_cntr_buffer_nvoc.h --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/generated/g_access_cntr_buffer_nvoc.h 2023-10-25 20:26:51.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_access_cntr_buffer_nvoc.h 2024-03-05 22:18:06.000000000 +0000 @@ -73,9 +73,9 @@ NV_STATUS (*__accesscntrCtrlCmdAccessCntrSetConfig__)(struct AccessCounterBuffer *, NVC365_CTRL_ACCESS_CNTR_SET_CONFIG_PARAMS *); NV_STATUS (*__accesscntrCtrlCmdAccessCntrBufferEnableIntr__)(struct AccessCounterBuffer *, NVC365_CTRL_ACCESS_CNTR_BUFFER_ENABLE_INTR_PARAMS *); NvBool (*__accesscntrShareCallback__)(struct AccessCounterBuffer *, struct RsClient *, struct RsResourceRef *, RS_SHARE_POLICY *); - NV_STATUS (*__accesscntrMapTo__)(struct AccessCounterBuffer *, RS_RES_MAP_TO_PARAMS *); - NV_STATUS (*__accesscntrGetOrAllocNotifShare__)(struct AccessCounterBuffer *, NvHandle, NvHandle, struct NotifShare **); NV_STATUS (*__accesscntrCheckMemInterUnmap__)(struct AccessCounterBuffer *, NvBool); + NV_STATUS (*__accesscntrGetOrAllocNotifShare__)(struct AccessCounterBuffer *, NvHandle, NvHandle, struct NotifShare **); + NV_STATUS (*__accesscntrMapTo__)(struct AccessCounterBuffer *, RS_RES_MAP_TO_PARAMS *); void (*__accesscntrSetNotificationShare__)(struct AccessCounterBuffer *, struct NotifShare *); NvU32 (*__accesscntrGetRefCount__)(struct AccessCounterBuffer *); void (*__accesscntrAddAdditionalDependants__)(struct RsClient *, struct AccessCounterBuffer *, RsResourceRef *); @@ -91,12 +91,16 @@ NV_STATUS (*__accesscntrGetMemoryMappingDescriptor__)(struct AccessCounterBuffer *, struct MEMORY_DESCRIPTOR **); NV_STATUS (*__accesscntrControlFilter__)(struct AccessCounterBuffer *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); NV_STATUS (*__accesscntrUnregisterEvent__)(struct AccessCounterBuffer *, NvHandle, NvHandle, NvHandle, NvHandle); + NV_STATUS (*__accesscntrControlSerialization_Prologue__)(struct AccessCounterBuffer *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); NvBool (*__accesscntrCanCopy__)(struct AccessCounterBuffer *); void (*__accesscntrPreDestruct__)(struct AccessCounterBuffer *); NV_STATUS (*__accesscntrIsDuplicate__)(struct AccessCounterBuffer *, NvHandle, NvBool *); + void (*__accesscntrControlSerialization_Epilogue__)(struct AccessCounterBuffer *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); PEVENTNOTIFICATION *(*__accesscntrGetNotificationListPtr__)(struct AccessCounterBuffer *); struct NotifShare *(*__accesscntrGetNotificationShare__)(struct AccessCounterBuffer *); NvBool (*__accesscntrAccessCallback__)(struct AccessCounterBuffer *, struct RsClient *, void *, RsAccessRight); + struct MEMORY_DESCRIPTOR *pUvmAccessCntrAllocMemDesc; + NvU32 accessCounterIndex; }; #ifndef __NVOC_CLASS_AccessCounterBuffer_TYPEDEF__ @@ -141,9 +145,9 @@ #define accesscntrCtrlCmdAccessCntrSetConfig(pAccessCounterBuffer, pParams) accesscntrCtrlCmdAccessCntrSetConfig_DISPATCH(pAccessCounterBuffer, pParams) #define accesscntrCtrlCmdAccessCntrBufferEnableIntr(pAccessCounterBuffer, pGetParams) accesscntrCtrlCmdAccessCntrBufferEnableIntr_DISPATCH(pAccessCounterBuffer, pGetParams) #define accesscntrShareCallback(pGpuResource, pInvokingClient, pParentRef, pSharePolicy) accesscntrShareCallback_DISPATCH(pGpuResource, pInvokingClient, pParentRef, pSharePolicy) -#define accesscntrMapTo(pResource, pParams) accesscntrMapTo_DISPATCH(pResource, pParams) -#define accesscntrGetOrAllocNotifShare(pNotifier, hNotifierClient, hNotifierResource, ppNotifShare) accesscntrGetOrAllocNotifShare_DISPATCH(pNotifier, hNotifierClient, hNotifierResource, ppNotifShare) #define accesscntrCheckMemInterUnmap(pRmResource, bSubdeviceHandleProvided) accesscntrCheckMemInterUnmap_DISPATCH(pRmResource, bSubdeviceHandleProvided) +#define accesscntrGetOrAllocNotifShare(pNotifier, hNotifierClient, hNotifierResource, ppNotifShare) accesscntrGetOrAllocNotifShare_DISPATCH(pNotifier, hNotifierClient, hNotifierResource, ppNotifShare) +#define accesscntrMapTo(pResource, pParams) accesscntrMapTo_DISPATCH(pResource, pParams) #define accesscntrSetNotificationShare(pNotifier, pNotifShare) accesscntrSetNotificationShare_DISPATCH(pNotifier, pNotifShare) #define accesscntrGetRefCount(pResource) accesscntrGetRefCount_DISPATCH(pResource) #define accesscntrAddAdditionalDependants(pClient, pResource, pReference) accesscntrAddAdditionalDependants_DISPATCH(pClient, pResource, pReference) @@ -159,9 +163,11 @@ #define accesscntrGetMemoryMappingDescriptor(pRmResource, ppMemDesc) accesscntrGetMemoryMappingDescriptor_DISPATCH(pRmResource, ppMemDesc) #define accesscntrControlFilter(pResource, pCallContext, pParams) accesscntrControlFilter_DISPATCH(pResource, pCallContext, pParams) #define accesscntrUnregisterEvent(pNotifier, hNotifierClient, hNotifierResource, hEventClient, hEvent) accesscntrUnregisterEvent_DISPATCH(pNotifier, hNotifierClient, hNotifierResource, hEventClient, hEvent) +#define accesscntrControlSerialization_Prologue(pResource, pCallContext, pParams) accesscntrControlSerialization_Prologue_DISPATCH(pResource, pCallContext, pParams) #define accesscntrCanCopy(pResource) accesscntrCanCopy_DISPATCH(pResource) #define accesscntrPreDestruct(pResource) accesscntrPreDestruct_DISPATCH(pResource) #define accesscntrIsDuplicate(pResource, hMemory, pDuplicate) accesscntrIsDuplicate_DISPATCH(pResource, hMemory, pDuplicate) +#define accesscntrControlSerialization_Epilogue(pResource, pCallContext, pParams) accesscntrControlSerialization_Epilogue_DISPATCH(pResource, pCallContext, pParams) #define accesscntrGetNotificationListPtr(pNotifier) accesscntrGetNotificationListPtr_DISPATCH(pNotifier) #define accesscntrGetNotificationShare(pNotifier) accesscntrGetNotificationShare_DISPATCH(pNotifier) #define accesscntrAccessCallback(pResource, pInvokingClient, pAllocParams, accessRight) accesscntrAccessCallback_DISPATCH(pResource, pInvokingClient, pAllocParams, accessRight) @@ -247,16 +253,16 @@ return pGpuResource->__accesscntrShareCallback__(pGpuResource, pInvokingClient, pParentRef, pSharePolicy); } -static inline NV_STATUS accesscntrMapTo_DISPATCH(struct AccessCounterBuffer *pResource, RS_RES_MAP_TO_PARAMS *pParams) { - return pResource->__accesscntrMapTo__(pResource, pParams); +static inline NV_STATUS accesscntrCheckMemInterUnmap_DISPATCH(struct AccessCounterBuffer *pRmResource, NvBool bSubdeviceHandleProvided) { + return pRmResource->__accesscntrCheckMemInterUnmap__(pRmResource, bSubdeviceHandleProvided); } static inline NV_STATUS accesscntrGetOrAllocNotifShare_DISPATCH(struct AccessCounterBuffer *pNotifier, NvHandle hNotifierClient, NvHandle hNotifierResource, struct NotifShare **ppNotifShare) { return pNotifier->__accesscntrGetOrAllocNotifShare__(pNotifier, hNotifierClient, hNotifierResource, ppNotifShare); } -static inline NV_STATUS accesscntrCheckMemInterUnmap_DISPATCH(struct AccessCounterBuffer *pRmResource, NvBool bSubdeviceHandleProvided) { - return pRmResource->__accesscntrCheckMemInterUnmap__(pRmResource, bSubdeviceHandleProvided); +static inline NV_STATUS accesscntrMapTo_DISPATCH(struct AccessCounterBuffer *pResource, RS_RES_MAP_TO_PARAMS *pParams) { + return pResource->__accesscntrMapTo__(pResource, pParams); } static inline void accesscntrSetNotificationShare_DISPATCH(struct AccessCounterBuffer *pNotifier, struct NotifShare *pNotifShare) { @@ -319,6 +325,10 @@ return pNotifier->__accesscntrUnregisterEvent__(pNotifier, hNotifierClient, hNotifierResource, hEventClient, hEvent); } +static inline NV_STATUS accesscntrControlSerialization_Prologue_DISPATCH(struct AccessCounterBuffer *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return pResource->__accesscntrControlSerialization_Prologue__(pResource, pCallContext, pParams); +} + static inline NvBool accesscntrCanCopy_DISPATCH(struct AccessCounterBuffer *pResource) { return pResource->__accesscntrCanCopy__(pResource); } @@ -331,6 +341,10 @@ return pResource->__accesscntrIsDuplicate__(pResource, hMemory, pDuplicate); } +static inline void accesscntrControlSerialization_Epilogue_DISPATCH(struct AccessCounterBuffer *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + pResource->__accesscntrControlSerialization_Epilogue__(pResource, pCallContext, pParams); +} + static inline PEVENTNOTIFICATION *accesscntrGetNotificationListPtr_DISPATCH(struct AccessCounterBuffer *pNotifier) { return pNotifier->__accesscntrGetNotificationListPtr__(pNotifier); } diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/generated/g_allclasses.h nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_allclasses.h --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/generated/g_allclasses.h 2023-10-25 20:22:58.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_allclasses.h 2024-03-05 22:15:56.000000000 +0000 @@ -47,6 +47,7 @@ #include // NV01_MEMORY_SYSTEM #include // NV01_MEMORY_LOCAL_PRIVILEGED #include // NV01_MEMORY_LOCAL_USER +#include // NV_MEMORY_EXTENDED_USER #include // NV01_MEMORY_VIRTUAL #include // NV_MEMORY_MAPPER #include // NV01_MEMORY_LOCAL_PHYSICAL @@ -58,6 +59,7 @@ #include // NV01_MEMORY_LIST_FBMEM #include // NV01_MEMORY_LIST_OBJECT #include // NV01_MEMORY_FLA +#include // NV_CE_UTILS #include // NV_MEMORY_FABRIC #include // FABRIC_VASPACE_A #include // NV_MEMORY_MULTICAST_FABRIC @@ -114,6 +116,7 @@ #include // MAXWELL_PROFILER #include // MAXWELL_PROFILER_DEVICE #include // GF100_SUBDEVICE_MASTER +#include // GF100_SUBDEVICE_INFOROM #include // GF100_ZBC_CLEAR #include // GF100_DISP_SW #include // GF100_TIMED_SEMAPHORE_SW @@ -123,6 +126,7 @@ #include // NV50_THIRD_PARTY_P2P #include // FERMI_TWOD_A #include // FERMI_VASPACE_A +#include // HOPPER_SEC2_WORK_LAUNCH_A #include // GF100_HDACODEC #include // NVB8B0_VIDEO_DECODER #include // NVC4B0_VIDEO_DECODER @@ -151,6 +155,7 @@ #include // MAXWELL_DMA_COPY_A #include // ACCESS_COUNTER_NOTIFY_BUFFER #include // MMU_FAULT_BUFFER +#include // MMU_VIDMEM_ACCESS_BIT_BUFFER #include // TURING_A #include // TURING_COMPUTE_A #include // AMPERE_A @@ -175,7 +180,9 @@ #include // NV0060_SYNC_GPU_BOOST #include // GP100_UVM_SW #include // NV_EVENT_BUFFER +#include // NV_CONFIDENTIAL_COMPUTE #include // NV_COUNTER_COLLECTION_UNIT +#include // NV_SEMAPHORE_SURFACE #else // defined(SDK_ALL_CLASSES_INCLUDE_FULL_HEADER) @@ -270,6 +277,10 @@ #define NV1_MEMORY_USER (0x00000040) // alias #endif +#ifndef NV_MEMORY_EXTENDED_USER +#define NV_MEMORY_EXTENDED_USER (0x00000042) +#endif + #ifndef NV01_MEMORY_VIRTUAL #define NV01_MEMORY_VIRTUAL (0x00000070) #endif @@ -320,6 +331,10 @@ #define NV01_MEMORY_FLA (0x000000f3) #endif +#ifndef NV_CE_UTILS +#define NV_CE_UTILS (0x00000050) +#endif + #ifndef NV_MEMORY_FABRIC #define NV_MEMORY_FABRIC (0x000000f8) #endif @@ -571,6 +586,10 @@ #define GF100_SUBDEVICE_MASTER (0x000090e6) #endif +#ifndef GF100_SUBDEVICE_INFOROM +#define GF100_SUBDEVICE_INFOROM (0x000090e7) +#endif + #ifndef GF100_ZBC_CLEAR #define GF100_ZBC_CLEAR (0x00009096) #endif @@ -607,6 +626,10 @@ #define FERMI_VASPACE_A (0x000090f1) #endif +#ifndef HOPPER_SEC2_WORK_LAUNCH_A +#define HOPPER_SEC2_WORK_LAUNCH_A (0x0000cba2) +#endif + #ifndef GF100_HDACODEC #define GF100_HDACODEC (0x000090ec) #endif @@ -719,6 +742,10 @@ #define MMU_FAULT_BUFFER (0x0000c369) #endif +#ifndef MMU_VIDMEM_ACCESS_BIT_BUFFER +#define MMU_VIDMEM_ACCESS_BIT_BUFFER (0x0000c763) +#endif + #ifndef TURING_A #define TURING_A (0x0000c597) #endif @@ -815,9 +842,17 @@ #define NV_EVENT_BUFFER (0x000090cd) #endif +#ifndef NV_CONFIDENTIAL_COMPUTE +#define NV_CONFIDENTIAL_COMPUTE (0x0000cb33) +#endif + #ifndef NV_COUNTER_COLLECTION_UNIT #define NV_COUNTER_COLLECTION_UNIT (0x0000cbca) #endif +#ifndef NV_SEMAPHORE_SURFACE +#define NV_SEMAPHORE_SURFACE (0x000000da) +#endif + #endif // defined(SDK_ALL_CLASSES_INCLUDE_FULL_HEADER) diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/generated/g_binary_api_nvoc.c nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_binary_api_nvoc.c --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/generated/g_binary_api_nvoc.c 2023-10-25 20:26:51.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_binary_api_nvoc.c 2024-03-05 22:18:06.000000000 +0000 @@ -101,44 +101,24 @@ return gpuresShareCallback((struct GpuResource *)(((unsigned char *)pGpuResource) + __nvoc_rtti_BinaryApi_GpuResource.offset), pInvokingClient, pParentRef, pSharePolicy); } -static NV_STATUS __nvoc_thunk_GpuResource_binapiUnmap(struct BinaryApi *pGpuResource, struct CALL_CONTEXT *pCallContext, struct RsCpuMapping *pCpuMapping) { - return gpuresUnmap((struct GpuResource *)(((unsigned char *)pGpuResource) + __nvoc_rtti_BinaryApi_GpuResource.offset), pCallContext, pCpuMapping); -} - -static NV_STATUS __nvoc_thunk_RmResource_binapiGetMemInterMapParams(struct BinaryApi *pRmResource, RMRES_MEM_INTER_MAP_PARAMS *pParams) { - return rmresGetMemInterMapParams((struct RmResource *)(((unsigned char *)pRmResource) + __nvoc_rtti_BinaryApi_RmResource.offset), pParams); +static NV_STATUS __nvoc_thunk_RmResource_binapiCheckMemInterUnmap(struct BinaryApi *pRmResource, NvBool bSubdeviceHandleProvided) { + return rmresCheckMemInterUnmap((struct RmResource *)(((unsigned char *)pRmResource) + __nvoc_rtti_BinaryApi_RmResource.offset), bSubdeviceHandleProvided); } -static NV_STATUS __nvoc_thunk_RmResource_binapiGetMemoryMappingDescriptor(struct BinaryApi *pRmResource, struct MEMORY_DESCRIPTOR **ppMemDesc) { - return rmresGetMemoryMappingDescriptor((struct RmResource *)(((unsigned char *)pRmResource) + __nvoc_rtti_BinaryApi_RmResource.offset), ppMemDesc); +static NV_STATUS __nvoc_thunk_RsResource_binapiMapTo(struct BinaryApi *pResource, RS_RES_MAP_TO_PARAMS *pParams) { + return resMapTo((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_BinaryApi_RsResource.offset), pParams); } static NV_STATUS __nvoc_thunk_GpuResource_binapiGetMapAddrSpace(struct BinaryApi *pGpuResource, struct CALL_CONTEXT *pCallContext, NvU32 mapFlags, NV_ADDRESS_SPACE *pAddrSpace) { return gpuresGetMapAddrSpace((struct GpuResource *)(((unsigned char *)pGpuResource) + __nvoc_rtti_BinaryApi_GpuResource.offset), pCallContext, mapFlags, pAddrSpace); } -static NvHandle __nvoc_thunk_GpuResource_binapiGetInternalObjectHandle(struct BinaryApi *pGpuResource) { - return gpuresGetInternalObjectHandle((struct GpuResource *)(((unsigned char *)pGpuResource) + __nvoc_rtti_BinaryApi_GpuResource.offset)); -} - -static NV_STATUS __nvoc_thunk_RsResource_binapiControlFilter(struct BinaryApi *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { - return resControlFilter((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_BinaryApi_RsResource.offset), pCallContext, pParams); -} - -static void __nvoc_thunk_RsResource_binapiAddAdditionalDependants(struct RsClient *pClient, struct BinaryApi *pResource, RsResourceRef *pReference) { - resAddAdditionalDependants(pClient, (struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_BinaryApi_RsResource.offset), pReference); -} - static NvU32 __nvoc_thunk_RsResource_binapiGetRefCount(struct BinaryApi *pResource) { return resGetRefCount((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_BinaryApi_RsResource.offset)); } -static NV_STATUS __nvoc_thunk_RmResource_binapiCheckMemInterUnmap(struct BinaryApi *pRmResource, NvBool bSubdeviceHandleProvided) { - return rmresCheckMemInterUnmap((struct RmResource *)(((unsigned char *)pRmResource) + __nvoc_rtti_BinaryApi_RmResource.offset), bSubdeviceHandleProvided); -} - -static NV_STATUS __nvoc_thunk_RsResource_binapiMapTo(struct BinaryApi *pResource, RS_RES_MAP_TO_PARAMS *pParams) { - return resMapTo((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_BinaryApi_RsResource.offset), pParams); +static void __nvoc_thunk_RsResource_binapiAddAdditionalDependants(struct RsClient *pClient, struct BinaryApi *pResource, RsResourceRef *pReference) { + resAddAdditionalDependants(pClient, (struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_BinaryApi_RsResource.offset), pReference); } static NV_STATUS __nvoc_thunk_RmResource_binapiControl_Prologue(struct BinaryApi *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { @@ -149,26 +129,14 @@ return gpuresGetRegBaseOffsetAndSize((struct GpuResource *)(((unsigned char *)pGpuResource) + __nvoc_rtti_BinaryApi_GpuResource.offset), pGpu, pOffset, pSize); } -static NvBool __nvoc_thunk_RsResource_binapiCanCopy(struct BinaryApi *pResource) { - return resCanCopy((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_BinaryApi_RsResource.offset)); -} - static NV_STATUS __nvoc_thunk_GpuResource_binapiInternalControlForward(struct BinaryApi *pGpuResource, NvU32 command, void *pParams, NvU32 size) { return gpuresInternalControlForward((struct GpuResource *)(((unsigned char *)pGpuResource) + __nvoc_rtti_BinaryApi_GpuResource.offset), command, pParams, size); } -static void __nvoc_thunk_RsResource_binapiPreDestruct(struct BinaryApi *pResource) { - resPreDestruct((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_BinaryApi_RsResource.offset)); -} - static NV_STATUS __nvoc_thunk_RsResource_binapiUnmapFrom(struct BinaryApi *pResource, RS_RES_UNMAP_FROM_PARAMS *pParams) { return resUnmapFrom((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_BinaryApi_RsResource.offset), pParams); } -static NV_STATUS __nvoc_thunk_RsResource_binapiIsDuplicate(struct BinaryApi *pResource, NvHandle hMemory, NvBool *pDuplicate) { - return resIsDuplicate((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_BinaryApi_RsResource.offset), hMemory, pDuplicate); -} - static void __nvoc_thunk_RmResource_binapiControl_Epilogue(struct BinaryApi *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { rmresControl_Epilogue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_BinaryApi_RmResource.offset), pCallContext, pParams); } @@ -177,6 +145,46 @@ return resControlLookup((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_BinaryApi_RsResource.offset), pParams, ppEntry); } +static NvHandle __nvoc_thunk_GpuResource_binapiGetInternalObjectHandle(struct BinaryApi *pGpuResource) { + return gpuresGetInternalObjectHandle((struct GpuResource *)(((unsigned char *)pGpuResource) + __nvoc_rtti_BinaryApi_GpuResource.offset)); +} + +static NV_STATUS __nvoc_thunk_GpuResource_binapiUnmap(struct BinaryApi *pGpuResource, struct CALL_CONTEXT *pCallContext, struct RsCpuMapping *pCpuMapping) { + return gpuresUnmap((struct GpuResource *)(((unsigned char *)pGpuResource) + __nvoc_rtti_BinaryApi_GpuResource.offset), pCallContext, pCpuMapping); +} + +static NV_STATUS __nvoc_thunk_RmResource_binapiGetMemInterMapParams(struct BinaryApi *pRmResource, RMRES_MEM_INTER_MAP_PARAMS *pParams) { + return rmresGetMemInterMapParams((struct RmResource *)(((unsigned char *)pRmResource) + __nvoc_rtti_BinaryApi_RmResource.offset), pParams); +} + +static NV_STATUS __nvoc_thunk_RmResource_binapiGetMemoryMappingDescriptor(struct BinaryApi *pRmResource, struct MEMORY_DESCRIPTOR **ppMemDesc) { + return rmresGetMemoryMappingDescriptor((struct RmResource *)(((unsigned char *)pRmResource) + __nvoc_rtti_BinaryApi_RmResource.offset), ppMemDesc); +} + +static NV_STATUS __nvoc_thunk_RsResource_binapiControlFilter(struct BinaryApi *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return resControlFilter((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_BinaryApi_RsResource.offset), pCallContext, pParams); +} + +static NV_STATUS __nvoc_thunk_RmResource_binapiControlSerialization_Prologue(struct BinaryApi *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return rmresControlSerialization_Prologue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_BinaryApi_RmResource.offset), pCallContext, pParams); +} + +static NvBool __nvoc_thunk_RsResource_binapiCanCopy(struct BinaryApi *pResource) { + return resCanCopy((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_BinaryApi_RsResource.offset)); +} + +static void __nvoc_thunk_RsResource_binapiPreDestruct(struct BinaryApi *pResource) { + resPreDestruct((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_BinaryApi_RsResource.offset)); +} + +static NV_STATUS __nvoc_thunk_RsResource_binapiIsDuplicate(struct BinaryApi *pResource, NvHandle hMemory, NvBool *pDuplicate) { + return resIsDuplicate((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_BinaryApi_RsResource.offset), hMemory, pDuplicate); +} + +static void __nvoc_thunk_RmResource_binapiControlSerialization_Epilogue(struct BinaryApi *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + rmresControlSerialization_Epilogue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_BinaryApi_RmResource.offset), pCallContext, pParams); +} + static NV_STATUS __nvoc_thunk_GpuResource_binapiMap(struct BinaryApi *pGpuResource, struct CALL_CONTEXT *pCallContext, struct RS_CPU_MAP_PARAMS *pParams, struct RsCpuMapping *pCpuMapping) { return gpuresMap((struct GpuResource *)(((unsigned char *)pGpuResource) + __nvoc_rtti_BinaryApi_GpuResource.offset), pCallContext, pParams, pCpuMapping); } @@ -229,44 +237,48 @@ pThis->__binapiShareCallback__ = &__nvoc_thunk_GpuResource_binapiShareCallback; - pThis->__binapiUnmap__ = &__nvoc_thunk_GpuResource_binapiUnmap; - - pThis->__binapiGetMemInterMapParams__ = &__nvoc_thunk_RmResource_binapiGetMemInterMapParams; + pThis->__binapiCheckMemInterUnmap__ = &__nvoc_thunk_RmResource_binapiCheckMemInterUnmap; - pThis->__binapiGetMemoryMappingDescriptor__ = &__nvoc_thunk_RmResource_binapiGetMemoryMappingDescriptor; + pThis->__binapiMapTo__ = &__nvoc_thunk_RsResource_binapiMapTo; pThis->__binapiGetMapAddrSpace__ = &__nvoc_thunk_GpuResource_binapiGetMapAddrSpace; - pThis->__binapiGetInternalObjectHandle__ = &__nvoc_thunk_GpuResource_binapiGetInternalObjectHandle; - - pThis->__binapiControlFilter__ = &__nvoc_thunk_RsResource_binapiControlFilter; - - pThis->__binapiAddAdditionalDependants__ = &__nvoc_thunk_RsResource_binapiAddAdditionalDependants; - pThis->__binapiGetRefCount__ = &__nvoc_thunk_RsResource_binapiGetRefCount; - pThis->__binapiCheckMemInterUnmap__ = &__nvoc_thunk_RmResource_binapiCheckMemInterUnmap; - - pThis->__binapiMapTo__ = &__nvoc_thunk_RsResource_binapiMapTo; + pThis->__binapiAddAdditionalDependants__ = &__nvoc_thunk_RsResource_binapiAddAdditionalDependants; pThis->__binapiControl_Prologue__ = &__nvoc_thunk_RmResource_binapiControl_Prologue; pThis->__binapiGetRegBaseOffsetAndSize__ = &__nvoc_thunk_GpuResource_binapiGetRegBaseOffsetAndSize; - pThis->__binapiCanCopy__ = &__nvoc_thunk_RsResource_binapiCanCopy; - pThis->__binapiInternalControlForward__ = &__nvoc_thunk_GpuResource_binapiInternalControlForward; - pThis->__binapiPreDestruct__ = &__nvoc_thunk_RsResource_binapiPreDestruct; - pThis->__binapiUnmapFrom__ = &__nvoc_thunk_RsResource_binapiUnmapFrom; - pThis->__binapiIsDuplicate__ = &__nvoc_thunk_RsResource_binapiIsDuplicate; - pThis->__binapiControl_Epilogue__ = &__nvoc_thunk_RmResource_binapiControl_Epilogue; pThis->__binapiControlLookup__ = &__nvoc_thunk_RsResource_binapiControlLookup; + pThis->__binapiGetInternalObjectHandle__ = &__nvoc_thunk_GpuResource_binapiGetInternalObjectHandle; + + pThis->__binapiUnmap__ = &__nvoc_thunk_GpuResource_binapiUnmap; + + pThis->__binapiGetMemInterMapParams__ = &__nvoc_thunk_RmResource_binapiGetMemInterMapParams; + + pThis->__binapiGetMemoryMappingDescriptor__ = &__nvoc_thunk_RmResource_binapiGetMemoryMappingDescriptor; + + pThis->__binapiControlFilter__ = &__nvoc_thunk_RsResource_binapiControlFilter; + + pThis->__binapiControlSerialization_Prologue__ = &__nvoc_thunk_RmResource_binapiControlSerialization_Prologue; + + pThis->__binapiCanCopy__ = &__nvoc_thunk_RsResource_binapiCanCopy; + + pThis->__binapiPreDestruct__ = &__nvoc_thunk_RsResource_binapiPreDestruct; + + pThis->__binapiIsDuplicate__ = &__nvoc_thunk_RsResource_binapiIsDuplicate; + + pThis->__binapiControlSerialization_Epilogue__ = &__nvoc_thunk_RmResource_binapiControlSerialization_Epilogue; + pThis->__binapiMap__ = &__nvoc_thunk_GpuResource_binapiMap; pThis->__binapiAccessCallback__ = &__nvoc_thunk_RmResource_binapiAccessCallback; @@ -293,13 +305,16 @@ Object *pParentObj; BinaryApi *pThis; - pThis = portMemAllocNonPaged(sizeof(BinaryApi)); - if (pThis == NULL) return NV_ERR_NO_MEMORY; + status = __nvoc_handleObjCreateMemAlloc(createFlags, sizeof(BinaryApi), (void**)&pThis, (void**)ppThis); + if (status != NV_OK) + return status; portMemSet(pThis, 0, sizeof(BinaryApi)); __nvoc_initRtti(staticCast(pThis, Dynamic), &__nvoc_class_def_BinaryApi); + pThis->__nvoc_base_GpuResource.__nvoc_base_RmResource.__nvoc_base_RsResource.__nvoc_base_Object.createFlags = createFlags; + if (pParent != NULL && !(createFlags & NVOC_OBJ_CREATE_FLAGS_PARENT_HALSPEC_ONLY)) { pParentObj = dynamicCast(pParent, Object); @@ -315,11 +330,17 @@ if (status != NV_OK) goto __nvoc_objCreate_BinaryApi_cleanup; *ppThis = pThis; + return NV_OK; __nvoc_objCreate_BinaryApi_cleanup: // do not call destructors here since the constructor already called them - portMemFree(pThis); + if (createFlags & NVOC_OBJ_CREATE_FLAGS_IN_PLACE_CONSTRUCT) + portMemSet(pThis, 0, sizeof(BinaryApi)); + else + portMemFree(pThis); + + // coverity[leaked_storage:FALSE] return status; } @@ -436,44 +457,24 @@ return gpuresShareCallback((struct GpuResource *)(((unsigned char *)pGpuResource) + __nvoc_rtti_BinaryApiPrivileged_GpuResource.offset), pInvokingClient, pParentRef, pSharePolicy); } -static NV_STATUS __nvoc_thunk_GpuResource_binapiprivUnmap(struct BinaryApiPrivileged *pGpuResource, struct CALL_CONTEXT *pCallContext, struct RsCpuMapping *pCpuMapping) { - return gpuresUnmap((struct GpuResource *)(((unsigned char *)pGpuResource) + __nvoc_rtti_BinaryApiPrivileged_GpuResource.offset), pCallContext, pCpuMapping); -} - -static NV_STATUS __nvoc_thunk_RmResource_binapiprivGetMemInterMapParams(struct BinaryApiPrivileged *pRmResource, RMRES_MEM_INTER_MAP_PARAMS *pParams) { - return rmresGetMemInterMapParams((struct RmResource *)(((unsigned char *)pRmResource) + __nvoc_rtti_BinaryApiPrivileged_RmResource.offset), pParams); +static NV_STATUS __nvoc_thunk_RmResource_binapiprivCheckMemInterUnmap(struct BinaryApiPrivileged *pRmResource, NvBool bSubdeviceHandleProvided) { + return rmresCheckMemInterUnmap((struct RmResource *)(((unsigned char *)pRmResource) + __nvoc_rtti_BinaryApiPrivileged_RmResource.offset), bSubdeviceHandleProvided); } -static NV_STATUS __nvoc_thunk_RmResource_binapiprivGetMemoryMappingDescriptor(struct BinaryApiPrivileged *pRmResource, struct MEMORY_DESCRIPTOR **ppMemDesc) { - return rmresGetMemoryMappingDescriptor((struct RmResource *)(((unsigned char *)pRmResource) + __nvoc_rtti_BinaryApiPrivileged_RmResource.offset), ppMemDesc); +static NV_STATUS __nvoc_thunk_RsResource_binapiprivMapTo(struct BinaryApiPrivileged *pResource, RS_RES_MAP_TO_PARAMS *pParams) { + return resMapTo((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_BinaryApiPrivileged_RsResource.offset), pParams); } static NV_STATUS __nvoc_thunk_GpuResource_binapiprivGetMapAddrSpace(struct BinaryApiPrivileged *pGpuResource, struct CALL_CONTEXT *pCallContext, NvU32 mapFlags, NV_ADDRESS_SPACE *pAddrSpace) { return gpuresGetMapAddrSpace((struct GpuResource *)(((unsigned char *)pGpuResource) + __nvoc_rtti_BinaryApiPrivileged_GpuResource.offset), pCallContext, mapFlags, pAddrSpace); } -static NvHandle __nvoc_thunk_GpuResource_binapiprivGetInternalObjectHandle(struct BinaryApiPrivileged *pGpuResource) { - return gpuresGetInternalObjectHandle((struct GpuResource *)(((unsigned char *)pGpuResource) + __nvoc_rtti_BinaryApiPrivileged_GpuResource.offset)); -} - -static NV_STATUS __nvoc_thunk_RsResource_binapiprivControlFilter(struct BinaryApiPrivileged *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { - return resControlFilter((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_BinaryApiPrivileged_RsResource.offset), pCallContext, pParams); -} - -static void __nvoc_thunk_RsResource_binapiprivAddAdditionalDependants(struct RsClient *pClient, struct BinaryApiPrivileged *pResource, RsResourceRef *pReference) { - resAddAdditionalDependants(pClient, (struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_BinaryApiPrivileged_RsResource.offset), pReference); -} - static NvU32 __nvoc_thunk_RsResource_binapiprivGetRefCount(struct BinaryApiPrivileged *pResource) { return resGetRefCount((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_BinaryApiPrivileged_RsResource.offset)); } -static NV_STATUS __nvoc_thunk_RmResource_binapiprivCheckMemInterUnmap(struct BinaryApiPrivileged *pRmResource, NvBool bSubdeviceHandleProvided) { - return rmresCheckMemInterUnmap((struct RmResource *)(((unsigned char *)pRmResource) + __nvoc_rtti_BinaryApiPrivileged_RmResource.offset), bSubdeviceHandleProvided); -} - -static NV_STATUS __nvoc_thunk_RsResource_binapiprivMapTo(struct BinaryApiPrivileged *pResource, RS_RES_MAP_TO_PARAMS *pParams) { - return resMapTo((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_BinaryApiPrivileged_RsResource.offset), pParams); +static void __nvoc_thunk_RsResource_binapiprivAddAdditionalDependants(struct RsClient *pClient, struct BinaryApiPrivileged *pResource, RsResourceRef *pReference) { + resAddAdditionalDependants(pClient, (struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_BinaryApiPrivileged_RsResource.offset), pReference); } static NV_STATUS __nvoc_thunk_RmResource_binapiprivControl_Prologue(struct BinaryApiPrivileged *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { @@ -484,26 +485,14 @@ return gpuresGetRegBaseOffsetAndSize((struct GpuResource *)(((unsigned char *)pGpuResource) + __nvoc_rtti_BinaryApiPrivileged_GpuResource.offset), pGpu, pOffset, pSize); } -static NvBool __nvoc_thunk_RsResource_binapiprivCanCopy(struct BinaryApiPrivileged *pResource) { - return resCanCopy((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_BinaryApiPrivileged_RsResource.offset)); -} - static NV_STATUS __nvoc_thunk_GpuResource_binapiprivInternalControlForward(struct BinaryApiPrivileged *pGpuResource, NvU32 command, void *pParams, NvU32 size) { return gpuresInternalControlForward((struct GpuResource *)(((unsigned char *)pGpuResource) + __nvoc_rtti_BinaryApiPrivileged_GpuResource.offset), command, pParams, size); } -static void __nvoc_thunk_RsResource_binapiprivPreDestruct(struct BinaryApiPrivileged *pResource) { - resPreDestruct((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_BinaryApiPrivileged_RsResource.offset)); -} - static NV_STATUS __nvoc_thunk_RsResource_binapiprivUnmapFrom(struct BinaryApiPrivileged *pResource, RS_RES_UNMAP_FROM_PARAMS *pParams) { return resUnmapFrom((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_BinaryApiPrivileged_RsResource.offset), pParams); } -static NV_STATUS __nvoc_thunk_RsResource_binapiprivIsDuplicate(struct BinaryApiPrivileged *pResource, NvHandle hMemory, NvBool *pDuplicate) { - return resIsDuplicate((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_BinaryApiPrivileged_RsResource.offset), hMemory, pDuplicate); -} - static void __nvoc_thunk_RmResource_binapiprivControl_Epilogue(struct BinaryApiPrivileged *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { rmresControl_Epilogue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_BinaryApiPrivileged_RmResource.offset), pCallContext, pParams); } @@ -512,6 +501,46 @@ return resControlLookup((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_BinaryApiPrivileged_RsResource.offset), pParams, ppEntry); } +static NvHandle __nvoc_thunk_GpuResource_binapiprivGetInternalObjectHandle(struct BinaryApiPrivileged *pGpuResource) { + return gpuresGetInternalObjectHandle((struct GpuResource *)(((unsigned char *)pGpuResource) + __nvoc_rtti_BinaryApiPrivileged_GpuResource.offset)); +} + +static NV_STATUS __nvoc_thunk_GpuResource_binapiprivUnmap(struct BinaryApiPrivileged *pGpuResource, struct CALL_CONTEXT *pCallContext, struct RsCpuMapping *pCpuMapping) { + return gpuresUnmap((struct GpuResource *)(((unsigned char *)pGpuResource) + __nvoc_rtti_BinaryApiPrivileged_GpuResource.offset), pCallContext, pCpuMapping); +} + +static NV_STATUS __nvoc_thunk_RmResource_binapiprivGetMemInterMapParams(struct BinaryApiPrivileged *pRmResource, RMRES_MEM_INTER_MAP_PARAMS *pParams) { + return rmresGetMemInterMapParams((struct RmResource *)(((unsigned char *)pRmResource) + __nvoc_rtti_BinaryApiPrivileged_RmResource.offset), pParams); +} + +static NV_STATUS __nvoc_thunk_RmResource_binapiprivGetMemoryMappingDescriptor(struct BinaryApiPrivileged *pRmResource, struct MEMORY_DESCRIPTOR **ppMemDesc) { + return rmresGetMemoryMappingDescriptor((struct RmResource *)(((unsigned char *)pRmResource) + __nvoc_rtti_BinaryApiPrivileged_RmResource.offset), ppMemDesc); +} + +static NV_STATUS __nvoc_thunk_RsResource_binapiprivControlFilter(struct BinaryApiPrivileged *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return resControlFilter((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_BinaryApiPrivileged_RsResource.offset), pCallContext, pParams); +} + +static NV_STATUS __nvoc_thunk_RmResource_binapiprivControlSerialization_Prologue(struct BinaryApiPrivileged *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return rmresControlSerialization_Prologue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_BinaryApiPrivileged_RmResource.offset), pCallContext, pParams); +} + +static NvBool __nvoc_thunk_RsResource_binapiprivCanCopy(struct BinaryApiPrivileged *pResource) { + return resCanCopy((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_BinaryApiPrivileged_RsResource.offset)); +} + +static void __nvoc_thunk_RsResource_binapiprivPreDestruct(struct BinaryApiPrivileged *pResource) { + resPreDestruct((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_BinaryApiPrivileged_RsResource.offset)); +} + +static NV_STATUS __nvoc_thunk_RsResource_binapiprivIsDuplicate(struct BinaryApiPrivileged *pResource, NvHandle hMemory, NvBool *pDuplicate) { + return resIsDuplicate((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_BinaryApiPrivileged_RsResource.offset), hMemory, pDuplicate); +} + +static void __nvoc_thunk_RmResource_binapiprivControlSerialization_Epilogue(struct BinaryApiPrivileged *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + rmresControlSerialization_Epilogue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_BinaryApiPrivileged_RmResource.offset), pCallContext, pParams); +} + static NV_STATUS __nvoc_thunk_GpuResource_binapiprivMap(struct BinaryApiPrivileged *pGpuResource, struct CALL_CONTEXT *pCallContext, struct RS_CPU_MAP_PARAMS *pParams, struct RsCpuMapping *pCpuMapping) { return gpuresMap((struct GpuResource *)(((unsigned char *)pGpuResource) + __nvoc_rtti_BinaryApiPrivileged_GpuResource.offset), pCallContext, pParams, pCpuMapping); } @@ -564,44 +593,48 @@ pThis->__binapiprivShareCallback__ = &__nvoc_thunk_GpuResource_binapiprivShareCallback; - pThis->__binapiprivUnmap__ = &__nvoc_thunk_GpuResource_binapiprivUnmap; - - pThis->__binapiprivGetMemInterMapParams__ = &__nvoc_thunk_RmResource_binapiprivGetMemInterMapParams; + pThis->__binapiprivCheckMemInterUnmap__ = &__nvoc_thunk_RmResource_binapiprivCheckMemInterUnmap; - pThis->__binapiprivGetMemoryMappingDescriptor__ = &__nvoc_thunk_RmResource_binapiprivGetMemoryMappingDescriptor; + pThis->__binapiprivMapTo__ = &__nvoc_thunk_RsResource_binapiprivMapTo; pThis->__binapiprivGetMapAddrSpace__ = &__nvoc_thunk_GpuResource_binapiprivGetMapAddrSpace; - pThis->__binapiprivGetInternalObjectHandle__ = &__nvoc_thunk_GpuResource_binapiprivGetInternalObjectHandle; - - pThis->__binapiprivControlFilter__ = &__nvoc_thunk_RsResource_binapiprivControlFilter; - - pThis->__binapiprivAddAdditionalDependants__ = &__nvoc_thunk_RsResource_binapiprivAddAdditionalDependants; - pThis->__binapiprivGetRefCount__ = &__nvoc_thunk_RsResource_binapiprivGetRefCount; - pThis->__binapiprivCheckMemInterUnmap__ = &__nvoc_thunk_RmResource_binapiprivCheckMemInterUnmap; - - pThis->__binapiprivMapTo__ = &__nvoc_thunk_RsResource_binapiprivMapTo; + pThis->__binapiprivAddAdditionalDependants__ = &__nvoc_thunk_RsResource_binapiprivAddAdditionalDependants; pThis->__binapiprivControl_Prologue__ = &__nvoc_thunk_RmResource_binapiprivControl_Prologue; pThis->__binapiprivGetRegBaseOffsetAndSize__ = &__nvoc_thunk_GpuResource_binapiprivGetRegBaseOffsetAndSize; - pThis->__binapiprivCanCopy__ = &__nvoc_thunk_RsResource_binapiprivCanCopy; - pThis->__binapiprivInternalControlForward__ = &__nvoc_thunk_GpuResource_binapiprivInternalControlForward; - pThis->__binapiprivPreDestruct__ = &__nvoc_thunk_RsResource_binapiprivPreDestruct; - pThis->__binapiprivUnmapFrom__ = &__nvoc_thunk_RsResource_binapiprivUnmapFrom; - pThis->__binapiprivIsDuplicate__ = &__nvoc_thunk_RsResource_binapiprivIsDuplicate; - pThis->__binapiprivControl_Epilogue__ = &__nvoc_thunk_RmResource_binapiprivControl_Epilogue; pThis->__binapiprivControlLookup__ = &__nvoc_thunk_RsResource_binapiprivControlLookup; + pThis->__binapiprivGetInternalObjectHandle__ = &__nvoc_thunk_GpuResource_binapiprivGetInternalObjectHandle; + + pThis->__binapiprivUnmap__ = &__nvoc_thunk_GpuResource_binapiprivUnmap; + + pThis->__binapiprivGetMemInterMapParams__ = &__nvoc_thunk_RmResource_binapiprivGetMemInterMapParams; + + pThis->__binapiprivGetMemoryMappingDescriptor__ = &__nvoc_thunk_RmResource_binapiprivGetMemoryMappingDescriptor; + + pThis->__binapiprivControlFilter__ = &__nvoc_thunk_RsResource_binapiprivControlFilter; + + pThis->__binapiprivControlSerialization_Prologue__ = &__nvoc_thunk_RmResource_binapiprivControlSerialization_Prologue; + + pThis->__binapiprivCanCopy__ = &__nvoc_thunk_RsResource_binapiprivCanCopy; + + pThis->__binapiprivPreDestruct__ = &__nvoc_thunk_RsResource_binapiprivPreDestruct; + + pThis->__binapiprivIsDuplicate__ = &__nvoc_thunk_RsResource_binapiprivIsDuplicate; + + pThis->__binapiprivControlSerialization_Epilogue__ = &__nvoc_thunk_RmResource_binapiprivControlSerialization_Epilogue; + pThis->__binapiprivMap__ = &__nvoc_thunk_GpuResource_binapiprivMap; pThis->__binapiprivAccessCallback__ = &__nvoc_thunk_RmResource_binapiprivAccessCallback; @@ -629,13 +662,16 @@ Object *pParentObj; BinaryApiPrivileged *pThis; - pThis = portMemAllocNonPaged(sizeof(BinaryApiPrivileged)); - if (pThis == NULL) return NV_ERR_NO_MEMORY; + status = __nvoc_handleObjCreateMemAlloc(createFlags, sizeof(BinaryApiPrivileged), (void**)&pThis, (void**)ppThis); + if (status != NV_OK) + return status; portMemSet(pThis, 0, sizeof(BinaryApiPrivileged)); __nvoc_initRtti(staticCast(pThis, Dynamic), &__nvoc_class_def_BinaryApiPrivileged); + pThis->__nvoc_base_BinaryApi.__nvoc_base_GpuResource.__nvoc_base_RmResource.__nvoc_base_RsResource.__nvoc_base_Object.createFlags = createFlags; + if (pParent != NULL && !(createFlags & NVOC_OBJ_CREATE_FLAGS_PARENT_HALSPEC_ONLY)) { pParentObj = dynamicCast(pParent, Object); @@ -651,11 +687,17 @@ if (status != NV_OK) goto __nvoc_objCreate_BinaryApiPrivileged_cleanup; *ppThis = pThis; + return NV_OK; __nvoc_objCreate_BinaryApiPrivileged_cleanup: // do not call destructors here since the constructor already called them - portMemFree(pThis); + if (createFlags & NVOC_OBJ_CREATE_FLAGS_IN_PLACE_CONSTRUCT) + portMemSet(pThis, 0, sizeof(BinaryApiPrivileged)); + else + portMemFree(pThis); + + // coverity[leaked_storage:FALSE] return status; } diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/generated/g_binary_api_nvoc.h nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_binary_api_nvoc.h --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/generated/g_binary_api_nvoc.h 2023-10-25 20:26:51.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_binary_api_nvoc.h 2024-03-05 22:18:06.000000000 +0000 @@ -56,25 +56,27 @@ struct BinaryApi *__nvoc_pbase_BinaryApi; NV_STATUS (*__binapiControl__)(struct BinaryApi *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); NvBool (*__binapiShareCallback__)(struct BinaryApi *, struct RsClient *, struct RsResourceRef *, RS_SHARE_POLICY *); - NV_STATUS (*__binapiUnmap__)(struct BinaryApi *, struct CALL_CONTEXT *, struct RsCpuMapping *); - NV_STATUS (*__binapiGetMemInterMapParams__)(struct BinaryApi *, RMRES_MEM_INTER_MAP_PARAMS *); - NV_STATUS (*__binapiGetMemoryMappingDescriptor__)(struct BinaryApi *, struct MEMORY_DESCRIPTOR **); - NV_STATUS (*__binapiGetMapAddrSpace__)(struct BinaryApi *, struct CALL_CONTEXT *, NvU32, NV_ADDRESS_SPACE *); - NvHandle (*__binapiGetInternalObjectHandle__)(struct BinaryApi *); - NV_STATUS (*__binapiControlFilter__)(struct BinaryApi *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); - void (*__binapiAddAdditionalDependants__)(struct RsClient *, struct BinaryApi *, RsResourceRef *); - NvU32 (*__binapiGetRefCount__)(struct BinaryApi *); NV_STATUS (*__binapiCheckMemInterUnmap__)(struct BinaryApi *, NvBool); NV_STATUS (*__binapiMapTo__)(struct BinaryApi *, RS_RES_MAP_TO_PARAMS *); + NV_STATUS (*__binapiGetMapAddrSpace__)(struct BinaryApi *, struct CALL_CONTEXT *, NvU32, NV_ADDRESS_SPACE *); + NvU32 (*__binapiGetRefCount__)(struct BinaryApi *); + void (*__binapiAddAdditionalDependants__)(struct RsClient *, struct BinaryApi *, RsResourceRef *); NV_STATUS (*__binapiControl_Prologue__)(struct BinaryApi *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); NV_STATUS (*__binapiGetRegBaseOffsetAndSize__)(struct BinaryApi *, struct OBJGPU *, NvU32 *, NvU32 *); - NvBool (*__binapiCanCopy__)(struct BinaryApi *); NV_STATUS (*__binapiInternalControlForward__)(struct BinaryApi *, NvU32, void *, NvU32); - void (*__binapiPreDestruct__)(struct BinaryApi *); NV_STATUS (*__binapiUnmapFrom__)(struct BinaryApi *, RS_RES_UNMAP_FROM_PARAMS *); - NV_STATUS (*__binapiIsDuplicate__)(struct BinaryApi *, NvHandle, NvBool *); void (*__binapiControl_Epilogue__)(struct BinaryApi *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); NV_STATUS (*__binapiControlLookup__)(struct BinaryApi *, struct RS_RES_CONTROL_PARAMS_INTERNAL *, const struct NVOC_EXPORTED_METHOD_DEF **); + NvHandle (*__binapiGetInternalObjectHandle__)(struct BinaryApi *); + NV_STATUS (*__binapiUnmap__)(struct BinaryApi *, struct CALL_CONTEXT *, struct RsCpuMapping *); + NV_STATUS (*__binapiGetMemInterMapParams__)(struct BinaryApi *, RMRES_MEM_INTER_MAP_PARAMS *); + NV_STATUS (*__binapiGetMemoryMappingDescriptor__)(struct BinaryApi *, struct MEMORY_DESCRIPTOR **); + NV_STATUS (*__binapiControlFilter__)(struct BinaryApi *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); + NV_STATUS (*__binapiControlSerialization_Prologue__)(struct BinaryApi *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); + NvBool (*__binapiCanCopy__)(struct BinaryApi *); + void (*__binapiPreDestruct__)(struct BinaryApi *); + NV_STATUS (*__binapiIsDuplicate__)(struct BinaryApi *, NvHandle, NvBool *); + void (*__binapiControlSerialization_Epilogue__)(struct BinaryApi *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); NV_STATUS (*__binapiMap__)(struct BinaryApi *, struct CALL_CONTEXT *, struct RS_CPU_MAP_PARAMS *, struct RsCpuMapping *); NvBool (*__binapiAccessCallback__)(struct BinaryApi *, struct RsClient *, void *, RsAccessRight); }; @@ -109,25 +111,27 @@ #define binapiControl(pResource, pCallContext, pParams) binapiControl_DISPATCH(pResource, pCallContext, pParams) #define binapiShareCallback(pGpuResource, pInvokingClient, pParentRef, pSharePolicy) binapiShareCallback_DISPATCH(pGpuResource, pInvokingClient, pParentRef, pSharePolicy) -#define binapiUnmap(pGpuResource, pCallContext, pCpuMapping) binapiUnmap_DISPATCH(pGpuResource, pCallContext, pCpuMapping) -#define binapiGetMemInterMapParams(pRmResource, pParams) binapiGetMemInterMapParams_DISPATCH(pRmResource, pParams) -#define binapiGetMemoryMappingDescriptor(pRmResource, ppMemDesc) binapiGetMemoryMappingDescriptor_DISPATCH(pRmResource, ppMemDesc) -#define binapiGetMapAddrSpace(pGpuResource, pCallContext, mapFlags, pAddrSpace) binapiGetMapAddrSpace_DISPATCH(pGpuResource, pCallContext, mapFlags, pAddrSpace) -#define binapiGetInternalObjectHandle(pGpuResource) binapiGetInternalObjectHandle_DISPATCH(pGpuResource) -#define binapiControlFilter(pResource, pCallContext, pParams) binapiControlFilter_DISPATCH(pResource, pCallContext, pParams) -#define binapiAddAdditionalDependants(pClient, pResource, pReference) binapiAddAdditionalDependants_DISPATCH(pClient, pResource, pReference) -#define binapiGetRefCount(pResource) binapiGetRefCount_DISPATCH(pResource) #define binapiCheckMemInterUnmap(pRmResource, bSubdeviceHandleProvided) binapiCheckMemInterUnmap_DISPATCH(pRmResource, bSubdeviceHandleProvided) #define binapiMapTo(pResource, pParams) binapiMapTo_DISPATCH(pResource, pParams) +#define binapiGetMapAddrSpace(pGpuResource, pCallContext, mapFlags, pAddrSpace) binapiGetMapAddrSpace_DISPATCH(pGpuResource, pCallContext, mapFlags, pAddrSpace) +#define binapiGetRefCount(pResource) binapiGetRefCount_DISPATCH(pResource) +#define binapiAddAdditionalDependants(pClient, pResource, pReference) binapiAddAdditionalDependants_DISPATCH(pClient, pResource, pReference) #define binapiControl_Prologue(pResource, pCallContext, pParams) binapiControl_Prologue_DISPATCH(pResource, pCallContext, pParams) #define binapiGetRegBaseOffsetAndSize(pGpuResource, pGpu, pOffset, pSize) binapiGetRegBaseOffsetAndSize_DISPATCH(pGpuResource, pGpu, pOffset, pSize) -#define binapiCanCopy(pResource) binapiCanCopy_DISPATCH(pResource) #define binapiInternalControlForward(pGpuResource, command, pParams, size) binapiInternalControlForward_DISPATCH(pGpuResource, command, pParams, size) -#define binapiPreDestruct(pResource) binapiPreDestruct_DISPATCH(pResource) #define binapiUnmapFrom(pResource, pParams) binapiUnmapFrom_DISPATCH(pResource, pParams) -#define binapiIsDuplicate(pResource, hMemory, pDuplicate) binapiIsDuplicate_DISPATCH(pResource, hMemory, pDuplicate) #define binapiControl_Epilogue(pResource, pCallContext, pParams) binapiControl_Epilogue_DISPATCH(pResource, pCallContext, pParams) #define binapiControlLookup(pResource, pParams, ppEntry) binapiControlLookup_DISPATCH(pResource, pParams, ppEntry) +#define binapiGetInternalObjectHandle(pGpuResource) binapiGetInternalObjectHandle_DISPATCH(pGpuResource) +#define binapiUnmap(pGpuResource, pCallContext, pCpuMapping) binapiUnmap_DISPATCH(pGpuResource, pCallContext, pCpuMapping) +#define binapiGetMemInterMapParams(pRmResource, pParams) binapiGetMemInterMapParams_DISPATCH(pRmResource, pParams) +#define binapiGetMemoryMappingDescriptor(pRmResource, ppMemDesc) binapiGetMemoryMappingDescriptor_DISPATCH(pRmResource, ppMemDesc) +#define binapiControlFilter(pResource, pCallContext, pParams) binapiControlFilter_DISPATCH(pResource, pCallContext, pParams) +#define binapiControlSerialization_Prologue(pResource, pCallContext, pParams) binapiControlSerialization_Prologue_DISPATCH(pResource, pCallContext, pParams) +#define binapiCanCopy(pResource) binapiCanCopy_DISPATCH(pResource) +#define binapiPreDestruct(pResource) binapiPreDestruct_DISPATCH(pResource) +#define binapiIsDuplicate(pResource, hMemory, pDuplicate) binapiIsDuplicate_DISPATCH(pResource, hMemory, pDuplicate) +#define binapiControlSerialization_Epilogue(pResource, pCallContext, pParams) binapiControlSerialization_Epilogue_DISPATCH(pResource, pCallContext, pParams) #define binapiMap(pGpuResource, pCallContext, pParams, pCpuMapping) binapiMap_DISPATCH(pGpuResource, pCallContext, pParams, pCpuMapping) #define binapiAccessCallback(pResource, pInvokingClient, pAllocParams, accessRight) binapiAccessCallback_DISPATCH(pResource, pInvokingClient, pAllocParams, accessRight) NV_STATUS binapiControl_IMPL(struct BinaryApi *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams); @@ -140,44 +144,24 @@ return pGpuResource->__binapiShareCallback__(pGpuResource, pInvokingClient, pParentRef, pSharePolicy); } -static inline NV_STATUS binapiUnmap_DISPATCH(struct BinaryApi *pGpuResource, struct CALL_CONTEXT *pCallContext, struct RsCpuMapping *pCpuMapping) { - return pGpuResource->__binapiUnmap__(pGpuResource, pCallContext, pCpuMapping); -} - -static inline NV_STATUS binapiGetMemInterMapParams_DISPATCH(struct BinaryApi *pRmResource, RMRES_MEM_INTER_MAP_PARAMS *pParams) { - return pRmResource->__binapiGetMemInterMapParams__(pRmResource, pParams); +static inline NV_STATUS binapiCheckMemInterUnmap_DISPATCH(struct BinaryApi *pRmResource, NvBool bSubdeviceHandleProvided) { + return pRmResource->__binapiCheckMemInterUnmap__(pRmResource, bSubdeviceHandleProvided); } -static inline NV_STATUS binapiGetMemoryMappingDescriptor_DISPATCH(struct BinaryApi *pRmResource, struct MEMORY_DESCRIPTOR **ppMemDesc) { - return pRmResource->__binapiGetMemoryMappingDescriptor__(pRmResource, ppMemDesc); +static inline NV_STATUS binapiMapTo_DISPATCH(struct BinaryApi *pResource, RS_RES_MAP_TO_PARAMS *pParams) { + return pResource->__binapiMapTo__(pResource, pParams); } static inline NV_STATUS binapiGetMapAddrSpace_DISPATCH(struct BinaryApi *pGpuResource, struct CALL_CONTEXT *pCallContext, NvU32 mapFlags, NV_ADDRESS_SPACE *pAddrSpace) { return pGpuResource->__binapiGetMapAddrSpace__(pGpuResource, pCallContext, mapFlags, pAddrSpace); } -static inline NvHandle binapiGetInternalObjectHandle_DISPATCH(struct BinaryApi *pGpuResource) { - return pGpuResource->__binapiGetInternalObjectHandle__(pGpuResource); -} - -static inline NV_STATUS binapiControlFilter_DISPATCH(struct BinaryApi *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { - return pResource->__binapiControlFilter__(pResource, pCallContext, pParams); -} - -static inline void binapiAddAdditionalDependants_DISPATCH(struct RsClient *pClient, struct BinaryApi *pResource, RsResourceRef *pReference) { - pResource->__binapiAddAdditionalDependants__(pClient, pResource, pReference); -} - static inline NvU32 binapiGetRefCount_DISPATCH(struct BinaryApi *pResource) { return pResource->__binapiGetRefCount__(pResource); } -static inline NV_STATUS binapiCheckMemInterUnmap_DISPATCH(struct BinaryApi *pRmResource, NvBool bSubdeviceHandleProvided) { - return pRmResource->__binapiCheckMemInterUnmap__(pRmResource, bSubdeviceHandleProvided); -} - -static inline NV_STATUS binapiMapTo_DISPATCH(struct BinaryApi *pResource, RS_RES_MAP_TO_PARAMS *pParams) { - return pResource->__binapiMapTo__(pResource, pParams); +static inline void binapiAddAdditionalDependants_DISPATCH(struct RsClient *pClient, struct BinaryApi *pResource, RsResourceRef *pReference) { + pResource->__binapiAddAdditionalDependants__(pClient, pResource, pReference); } static inline NV_STATUS binapiControl_Prologue_DISPATCH(struct BinaryApi *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { @@ -188,26 +172,14 @@ return pGpuResource->__binapiGetRegBaseOffsetAndSize__(pGpuResource, pGpu, pOffset, pSize); } -static inline NvBool binapiCanCopy_DISPATCH(struct BinaryApi *pResource) { - return pResource->__binapiCanCopy__(pResource); -} - static inline NV_STATUS binapiInternalControlForward_DISPATCH(struct BinaryApi *pGpuResource, NvU32 command, void *pParams, NvU32 size) { return pGpuResource->__binapiInternalControlForward__(pGpuResource, command, pParams, size); } -static inline void binapiPreDestruct_DISPATCH(struct BinaryApi *pResource) { - pResource->__binapiPreDestruct__(pResource); -} - static inline NV_STATUS binapiUnmapFrom_DISPATCH(struct BinaryApi *pResource, RS_RES_UNMAP_FROM_PARAMS *pParams) { return pResource->__binapiUnmapFrom__(pResource, pParams); } -static inline NV_STATUS binapiIsDuplicate_DISPATCH(struct BinaryApi *pResource, NvHandle hMemory, NvBool *pDuplicate) { - return pResource->__binapiIsDuplicate__(pResource, hMemory, pDuplicate); -} - static inline void binapiControl_Epilogue_DISPATCH(struct BinaryApi *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { pResource->__binapiControl_Epilogue__(pResource, pCallContext, pParams); } @@ -216,6 +188,46 @@ return pResource->__binapiControlLookup__(pResource, pParams, ppEntry); } +static inline NvHandle binapiGetInternalObjectHandle_DISPATCH(struct BinaryApi *pGpuResource) { + return pGpuResource->__binapiGetInternalObjectHandle__(pGpuResource); +} + +static inline NV_STATUS binapiUnmap_DISPATCH(struct BinaryApi *pGpuResource, struct CALL_CONTEXT *pCallContext, struct RsCpuMapping *pCpuMapping) { + return pGpuResource->__binapiUnmap__(pGpuResource, pCallContext, pCpuMapping); +} + +static inline NV_STATUS binapiGetMemInterMapParams_DISPATCH(struct BinaryApi *pRmResource, RMRES_MEM_INTER_MAP_PARAMS *pParams) { + return pRmResource->__binapiGetMemInterMapParams__(pRmResource, pParams); +} + +static inline NV_STATUS binapiGetMemoryMappingDescriptor_DISPATCH(struct BinaryApi *pRmResource, struct MEMORY_DESCRIPTOR **ppMemDesc) { + return pRmResource->__binapiGetMemoryMappingDescriptor__(pRmResource, ppMemDesc); +} + +static inline NV_STATUS binapiControlFilter_DISPATCH(struct BinaryApi *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return pResource->__binapiControlFilter__(pResource, pCallContext, pParams); +} + +static inline NV_STATUS binapiControlSerialization_Prologue_DISPATCH(struct BinaryApi *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return pResource->__binapiControlSerialization_Prologue__(pResource, pCallContext, pParams); +} + +static inline NvBool binapiCanCopy_DISPATCH(struct BinaryApi *pResource) { + return pResource->__binapiCanCopy__(pResource); +} + +static inline void binapiPreDestruct_DISPATCH(struct BinaryApi *pResource) { + pResource->__binapiPreDestruct__(pResource); +} + +static inline NV_STATUS binapiIsDuplicate_DISPATCH(struct BinaryApi *pResource, NvHandle hMemory, NvBool *pDuplicate) { + return pResource->__binapiIsDuplicate__(pResource, hMemory, pDuplicate); +} + +static inline void binapiControlSerialization_Epilogue_DISPATCH(struct BinaryApi *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + pResource->__binapiControlSerialization_Epilogue__(pResource, pCallContext, pParams); +} + static inline NV_STATUS binapiMap_DISPATCH(struct BinaryApi *pGpuResource, struct CALL_CONTEXT *pCallContext, struct RS_CPU_MAP_PARAMS *pParams, struct RsCpuMapping *pCpuMapping) { return pGpuResource->__binapiMap__(pGpuResource, pCallContext, pParams, pCpuMapping); } @@ -247,25 +259,27 @@ struct BinaryApiPrivileged *__nvoc_pbase_BinaryApiPrivileged; NV_STATUS (*__binapiprivControl__)(struct BinaryApiPrivileged *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); NvBool (*__binapiprivShareCallback__)(struct BinaryApiPrivileged *, struct RsClient *, struct RsResourceRef *, RS_SHARE_POLICY *); - NV_STATUS (*__binapiprivUnmap__)(struct BinaryApiPrivileged *, struct CALL_CONTEXT *, struct RsCpuMapping *); - NV_STATUS (*__binapiprivGetMemInterMapParams__)(struct BinaryApiPrivileged *, RMRES_MEM_INTER_MAP_PARAMS *); - NV_STATUS (*__binapiprivGetMemoryMappingDescriptor__)(struct BinaryApiPrivileged *, struct MEMORY_DESCRIPTOR **); - NV_STATUS (*__binapiprivGetMapAddrSpace__)(struct BinaryApiPrivileged *, struct CALL_CONTEXT *, NvU32, NV_ADDRESS_SPACE *); - NvHandle (*__binapiprivGetInternalObjectHandle__)(struct BinaryApiPrivileged *); - NV_STATUS (*__binapiprivControlFilter__)(struct BinaryApiPrivileged *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); - void (*__binapiprivAddAdditionalDependants__)(struct RsClient *, struct BinaryApiPrivileged *, RsResourceRef *); - NvU32 (*__binapiprivGetRefCount__)(struct BinaryApiPrivileged *); NV_STATUS (*__binapiprivCheckMemInterUnmap__)(struct BinaryApiPrivileged *, NvBool); NV_STATUS (*__binapiprivMapTo__)(struct BinaryApiPrivileged *, RS_RES_MAP_TO_PARAMS *); + NV_STATUS (*__binapiprivGetMapAddrSpace__)(struct BinaryApiPrivileged *, struct CALL_CONTEXT *, NvU32, NV_ADDRESS_SPACE *); + NvU32 (*__binapiprivGetRefCount__)(struct BinaryApiPrivileged *); + void (*__binapiprivAddAdditionalDependants__)(struct RsClient *, struct BinaryApiPrivileged *, RsResourceRef *); NV_STATUS (*__binapiprivControl_Prologue__)(struct BinaryApiPrivileged *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); NV_STATUS (*__binapiprivGetRegBaseOffsetAndSize__)(struct BinaryApiPrivileged *, struct OBJGPU *, NvU32 *, NvU32 *); - NvBool (*__binapiprivCanCopy__)(struct BinaryApiPrivileged *); NV_STATUS (*__binapiprivInternalControlForward__)(struct BinaryApiPrivileged *, NvU32, void *, NvU32); - void (*__binapiprivPreDestruct__)(struct BinaryApiPrivileged *); NV_STATUS (*__binapiprivUnmapFrom__)(struct BinaryApiPrivileged *, RS_RES_UNMAP_FROM_PARAMS *); - NV_STATUS (*__binapiprivIsDuplicate__)(struct BinaryApiPrivileged *, NvHandle, NvBool *); void (*__binapiprivControl_Epilogue__)(struct BinaryApiPrivileged *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); NV_STATUS (*__binapiprivControlLookup__)(struct BinaryApiPrivileged *, struct RS_RES_CONTROL_PARAMS_INTERNAL *, const struct NVOC_EXPORTED_METHOD_DEF **); + NvHandle (*__binapiprivGetInternalObjectHandle__)(struct BinaryApiPrivileged *); + NV_STATUS (*__binapiprivUnmap__)(struct BinaryApiPrivileged *, struct CALL_CONTEXT *, struct RsCpuMapping *); + NV_STATUS (*__binapiprivGetMemInterMapParams__)(struct BinaryApiPrivileged *, RMRES_MEM_INTER_MAP_PARAMS *); + NV_STATUS (*__binapiprivGetMemoryMappingDescriptor__)(struct BinaryApiPrivileged *, struct MEMORY_DESCRIPTOR **); + NV_STATUS (*__binapiprivControlFilter__)(struct BinaryApiPrivileged *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); + NV_STATUS (*__binapiprivControlSerialization_Prologue__)(struct BinaryApiPrivileged *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); + NvBool (*__binapiprivCanCopy__)(struct BinaryApiPrivileged *); + void (*__binapiprivPreDestruct__)(struct BinaryApiPrivileged *); + NV_STATUS (*__binapiprivIsDuplicate__)(struct BinaryApiPrivileged *, NvHandle, NvBool *); + void (*__binapiprivControlSerialization_Epilogue__)(struct BinaryApiPrivileged *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); NV_STATUS (*__binapiprivMap__)(struct BinaryApiPrivileged *, struct CALL_CONTEXT *, struct RS_CPU_MAP_PARAMS *, struct RsCpuMapping *); NvBool (*__binapiprivAccessCallback__)(struct BinaryApiPrivileged *, struct RsClient *, void *, RsAccessRight); }; @@ -300,25 +314,27 @@ #define binapiprivControl(pResource, pCallContext, pParams) binapiprivControl_DISPATCH(pResource, pCallContext, pParams) #define binapiprivShareCallback(pGpuResource, pInvokingClient, pParentRef, pSharePolicy) binapiprivShareCallback_DISPATCH(pGpuResource, pInvokingClient, pParentRef, pSharePolicy) -#define binapiprivUnmap(pGpuResource, pCallContext, pCpuMapping) binapiprivUnmap_DISPATCH(pGpuResource, pCallContext, pCpuMapping) -#define binapiprivGetMemInterMapParams(pRmResource, pParams) binapiprivGetMemInterMapParams_DISPATCH(pRmResource, pParams) -#define binapiprivGetMemoryMappingDescriptor(pRmResource, ppMemDesc) binapiprivGetMemoryMappingDescriptor_DISPATCH(pRmResource, ppMemDesc) -#define binapiprivGetMapAddrSpace(pGpuResource, pCallContext, mapFlags, pAddrSpace) binapiprivGetMapAddrSpace_DISPATCH(pGpuResource, pCallContext, mapFlags, pAddrSpace) -#define binapiprivGetInternalObjectHandle(pGpuResource) binapiprivGetInternalObjectHandle_DISPATCH(pGpuResource) -#define binapiprivControlFilter(pResource, pCallContext, pParams) binapiprivControlFilter_DISPATCH(pResource, pCallContext, pParams) -#define binapiprivAddAdditionalDependants(pClient, pResource, pReference) binapiprivAddAdditionalDependants_DISPATCH(pClient, pResource, pReference) -#define binapiprivGetRefCount(pResource) binapiprivGetRefCount_DISPATCH(pResource) #define binapiprivCheckMemInterUnmap(pRmResource, bSubdeviceHandleProvided) binapiprivCheckMemInterUnmap_DISPATCH(pRmResource, bSubdeviceHandleProvided) #define binapiprivMapTo(pResource, pParams) binapiprivMapTo_DISPATCH(pResource, pParams) +#define binapiprivGetMapAddrSpace(pGpuResource, pCallContext, mapFlags, pAddrSpace) binapiprivGetMapAddrSpace_DISPATCH(pGpuResource, pCallContext, mapFlags, pAddrSpace) +#define binapiprivGetRefCount(pResource) binapiprivGetRefCount_DISPATCH(pResource) +#define binapiprivAddAdditionalDependants(pClient, pResource, pReference) binapiprivAddAdditionalDependants_DISPATCH(pClient, pResource, pReference) #define binapiprivControl_Prologue(pResource, pCallContext, pParams) binapiprivControl_Prologue_DISPATCH(pResource, pCallContext, pParams) #define binapiprivGetRegBaseOffsetAndSize(pGpuResource, pGpu, pOffset, pSize) binapiprivGetRegBaseOffsetAndSize_DISPATCH(pGpuResource, pGpu, pOffset, pSize) -#define binapiprivCanCopy(pResource) binapiprivCanCopy_DISPATCH(pResource) #define binapiprivInternalControlForward(pGpuResource, command, pParams, size) binapiprivInternalControlForward_DISPATCH(pGpuResource, command, pParams, size) -#define binapiprivPreDestruct(pResource) binapiprivPreDestruct_DISPATCH(pResource) #define binapiprivUnmapFrom(pResource, pParams) binapiprivUnmapFrom_DISPATCH(pResource, pParams) -#define binapiprivIsDuplicate(pResource, hMemory, pDuplicate) binapiprivIsDuplicate_DISPATCH(pResource, hMemory, pDuplicate) #define binapiprivControl_Epilogue(pResource, pCallContext, pParams) binapiprivControl_Epilogue_DISPATCH(pResource, pCallContext, pParams) #define binapiprivControlLookup(pResource, pParams, ppEntry) binapiprivControlLookup_DISPATCH(pResource, pParams, ppEntry) +#define binapiprivGetInternalObjectHandle(pGpuResource) binapiprivGetInternalObjectHandle_DISPATCH(pGpuResource) +#define binapiprivUnmap(pGpuResource, pCallContext, pCpuMapping) binapiprivUnmap_DISPATCH(pGpuResource, pCallContext, pCpuMapping) +#define binapiprivGetMemInterMapParams(pRmResource, pParams) binapiprivGetMemInterMapParams_DISPATCH(pRmResource, pParams) +#define binapiprivGetMemoryMappingDescriptor(pRmResource, ppMemDesc) binapiprivGetMemoryMappingDescriptor_DISPATCH(pRmResource, ppMemDesc) +#define binapiprivControlFilter(pResource, pCallContext, pParams) binapiprivControlFilter_DISPATCH(pResource, pCallContext, pParams) +#define binapiprivControlSerialization_Prologue(pResource, pCallContext, pParams) binapiprivControlSerialization_Prologue_DISPATCH(pResource, pCallContext, pParams) +#define binapiprivCanCopy(pResource) binapiprivCanCopy_DISPATCH(pResource) +#define binapiprivPreDestruct(pResource) binapiprivPreDestruct_DISPATCH(pResource) +#define binapiprivIsDuplicate(pResource, hMemory, pDuplicate) binapiprivIsDuplicate_DISPATCH(pResource, hMemory, pDuplicate) +#define binapiprivControlSerialization_Epilogue(pResource, pCallContext, pParams) binapiprivControlSerialization_Epilogue_DISPATCH(pResource, pCallContext, pParams) #define binapiprivMap(pGpuResource, pCallContext, pParams, pCpuMapping) binapiprivMap_DISPATCH(pGpuResource, pCallContext, pParams, pCpuMapping) #define binapiprivAccessCallback(pResource, pInvokingClient, pAllocParams, accessRight) binapiprivAccessCallback_DISPATCH(pResource, pInvokingClient, pAllocParams, accessRight) NV_STATUS binapiprivControl_IMPL(struct BinaryApiPrivileged *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams); @@ -331,44 +347,24 @@ return pGpuResource->__binapiprivShareCallback__(pGpuResource, pInvokingClient, pParentRef, pSharePolicy); } -static inline NV_STATUS binapiprivUnmap_DISPATCH(struct BinaryApiPrivileged *pGpuResource, struct CALL_CONTEXT *pCallContext, struct RsCpuMapping *pCpuMapping) { - return pGpuResource->__binapiprivUnmap__(pGpuResource, pCallContext, pCpuMapping); -} - -static inline NV_STATUS binapiprivGetMemInterMapParams_DISPATCH(struct BinaryApiPrivileged *pRmResource, RMRES_MEM_INTER_MAP_PARAMS *pParams) { - return pRmResource->__binapiprivGetMemInterMapParams__(pRmResource, pParams); +static inline NV_STATUS binapiprivCheckMemInterUnmap_DISPATCH(struct BinaryApiPrivileged *pRmResource, NvBool bSubdeviceHandleProvided) { + return pRmResource->__binapiprivCheckMemInterUnmap__(pRmResource, bSubdeviceHandleProvided); } -static inline NV_STATUS binapiprivGetMemoryMappingDescriptor_DISPATCH(struct BinaryApiPrivileged *pRmResource, struct MEMORY_DESCRIPTOR **ppMemDesc) { - return pRmResource->__binapiprivGetMemoryMappingDescriptor__(pRmResource, ppMemDesc); +static inline NV_STATUS binapiprivMapTo_DISPATCH(struct BinaryApiPrivileged *pResource, RS_RES_MAP_TO_PARAMS *pParams) { + return pResource->__binapiprivMapTo__(pResource, pParams); } static inline NV_STATUS binapiprivGetMapAddrSpace_DISPATCH(struct BinaryApiPrivileged *pGpuResource, struct CALL_CONTEXT *pCallContext, NvU32 mapFlags, NV_ADDRESS_SPACE *pAddrSpace) { return pGpuResource->__binapiprivGetMapAddrSpace__(pGpuResource, pCallContext, mapFlags, pAddrSpace); } -static inline NvHandle binapiprivGetInternalObjectHandle_DISPATCH(struct BinaryApiPrivileged *pGpuResource) { - return pGpuResource->__binapiprivGetInternalObjectHandle__(pGpuResource); -} - -static inline NV_STATUS binapiprivControlFilter_DISPATCH(struct BinaryApiPrivileged *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { - return pResource->__binapiprivControlFilter__(pResource, pCallContext, pParams); -} - -static inline void binapiprivAddAdditionalDependants_DISPATCH(struct RsClient *pClient, struct BinaryApiPrivileged *pResource, RsResourceRef *pReference) { - pResource->__binapiprivAddAdditionalDependants__(pClient, pResource, pReference); -} - static inline NvU32 binapiprivGetRefCount_DISPATCH(struct BinaryApiPrivileged *pResource) { return pResource->__binapiprivGetRefCount__(pResource); } -static inline NV_STATUS binapiprivCheckMemInterUnmap_DISPATCH(struct BinaryApiPrivileged *pRmResource, NvBool bSubdeviceHandleProvided) { - return pRmResource->__binapiprivCheckMemInterUnmap__(pRmResource, bSubdeviceHandleProvided); -} - -static inline NV_STATUS binapiprivMapTo_DISPATCH(struct BinaryApiPrivileged *pResource, RS_RES_MAP_TO_PARAMS *pParams) { - return pResource->__binapiprivMapTo__(pResource, pParams); +static inline void binapiprivAddAdditionalDependants_DISPATCH(struct RsClient *pClient, struct BinaryApiPrivileged *pResource, RsResourceRef *pReference) { + pResource->__binapiprivAddAdditionalDependants__(pClient, pResource, pReference); } static inline NV_STATUS binapiprivControl_Prologue_DISPATCH(struct BinaryApiPrivileged *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { @@ -379,26 +375,14 @@ return pGpuResource->__binapiprivGetRegBaseOffsetAndSize__(pGpuResource, pGpu, pOffset, pSize); } -static inline NvBool binapiprivCanCopy_DISPATCH(struct BinaryApiPrivileged *pResource) { - return pResource->__binapiprivCanCopy__(pResource); -} - static inline NV_STATUS binapiprivInternalControlForward_DISPATCH(struct BinaryApiPrivileged *pGpuResource, NvU32 command, void *pParams, NvU32 size) { return pGpuResource->__binapiprivInternalControlForward__(pGpuResource, command, pParams, size); } -static inline void binapiprivPreDestruct_DISPATCH(struct BinaryApiPrivileged *pResource) { - pResource->__binapiprivPreDestruct__(pResource); -} - static inline NV_STATUS binapiprivUnmapFrom_DISPATCH(struct BinaryApiPrivileged *pResource, RS_RES_UNMAP_FROM_PARAMS *pParams) { return pResource->__binapiprivUnmapFrom__(pResource, pParams); } -static inline NV_STATUS binapiprivIsDuplicate_DISPATCH(struct BinaryApiPrivileged *pResource, NvHandle hMemory, NvBool *pDuplicate) { - return pResource->__binapiprivIsDuplicate__(pResource, hMemory, pDuplicate); -} - static inline void binapiprivControl_Epilogue_DISPATCH(struct BinaryApiPrivileged *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { pResource->__binapiprivControl_Epilogue__(pResource, pCallContext, pParams); } @@ -407,6 +391,46 @@ return pResource->__binapiprivControlLookup__(pResource, pParams, ppEntry); } +static inline NvHandle binapiprivGetInternalObjectHandle_DISPATCH(struct BinaryApiPrivileged *pGpuResource) { + return pGpuResource->__binapiprivGetInternalObjectHandle__(pGpuResource); +} + +static inline NV_STATUS binapiprivUnmap_DISPATCH(struct BinaryApiPrivileged *pGpuResource, struct CALL_CONTEXT *pCallContext, struct RsCpuMapping *pCpuMapping) { + return pGpuResource->__binapiprivUnmap__(pGpuResource, pCallContext, pCpuMapping); +} + +static inline NV_STATUS binapiprivGetMemInterMapParams_DISPATCH(struct BinaryApiPrivileged *pRmResource, RMRES_MEM_INTER_MAP_PARAMS *pParams) { + return pRmResource->__binapiprivGetMemInterMapParams__(pRmResource, pParams); +} + +static inline NV_STATUS binapiprivGetMemoryMappingDescriptor_DISPATCH(struct BinaryApiPrivileged *pRmResource, struct MEMORY_DESCRIPTOR **ppMemDesc) { + return pRmResource->__binapiprivGetMemoryMappingDescriptor__(pRmResource, ppMemDesc); +} + +static inline NV_STATUS binapiprivControlFilter_DISPATCH(struct BinaryApiPrivileged *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return pResource->__binapiprivControlFilter__(pResource, pCallContext, pParams); +} + +static inline NV_STATUS binapiprivControlSerialization_Prologue_DISPATCH(struct BinaryApiPrivileged *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return pResource->__binapiprivControlSerialization_Prologue__(pResource, pCallContext, pParams); +} + +static inline NvBool binapiprivCanCopy_DISPATCH(struct BinaryApiPrivileged *pResource) { + return pResource->__binapiprivCanCopy__(pResource); +} + +static inline void binapiprivPreDestruct_DISPATCH(struct BinaryApiPrivileged *pResource) { + pResource->__binapiprivPreDestruct__(pResource); +} + +static inline NV_STATUS binapiprivIsDuplicate_DISPATCH(struct BinaryApiPrivileged *pResource, NvHandle hMemory, NvBool *pDuplicate) { + return pResource->__binapiprivIsDuplicate__(pResource, hMemory, pDuplicate); +} + +static inline void binapiprivControlSerialization_Epilogue_DISPATCH(struct BinaryApiPrivileged *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + pResource->__binapiprivControlSerialization_Epilogue__(pResource, pCallContext, pParams); +} + static inline NV_STATUS binapiprivMap_DISPATCH(struct BinaryApiPrivileged *pGpuResource, struct CALL_CONTEXT *pCallContext, struct RS_CPU_MAP_PARAMS *pParams, struct RsCpuMapping *pCpuMapping) { return pGpuResource->__binapiprivMap__(pGpuResource, pCallContext, pParams, pCpuMapping); } diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/generated/g_bindata.c nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_bindata.c --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/generated/g_bindata.c 2023-10-25 20:22:58.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_bindata.c 2024-03-05 22:15:56.000000000 +0000 @@ -56,8 +56,11 @@ #include "g_bindata_kgspGetBinArchiveGspRmBoot_GA102.c" #include "g_bindata_kgspGetBinArchiveGspRmBoot_AD102.c" #include "g_bindata_kgspGetBinArchiveGspRmBoot_GH100.c" +#include "g_bindata_kgspGetBinArchiveConcatenatedFMCDesc_GH100.c" +#include "g_bindata_kgspGetBinArchiveConcatenatedFMC_GH100.c" #include "g_bindata_kgspGetBinArchiveGspRmFmcGfwDebugSigned_GH100.c" #include "g_bindata_kgspGetBinArchiveGspRmFmcGfwProdSigned_GH100.c" +#include "g_bindata_kgspGetBinArchiveGspRmCcFmcGfwProdSigned_GH100.c" #include "g_bindata_kgspGetBinArchiveBooterLoadUcode_TU102.c" #include "g_bindata_kgspGetBinArchiveBooterLoadUcode_TU116.c" #include "g_bindata_kgspGetBinArchiveBooterLoadUcode_GA100.c" @@ -85,8 +88,11 @@ #include "g_bindata_kgspGetBinArchiveGspRmBoot_GA102.c" #include "g_bindata_kgspGetBinArchiveGspRmBoot_AD102.c" #include "g_bindata_kgspGetBinArchiveGspRmBoot_GH100.c" +#include "g_bindata_kgspGetBinArchiveConcatenatedFMCDesc_GH100.c" +#include "g_bindata_kgspGetBinArchiveConcatenatedFMC_GH100.c" #include "g_bindata_kgspGetBinArchiveGspRmFmcGfwDebugSigned_GH100.c" #include "g_bindata_kgspGetBinArchiveGspRmFmcGfwProdSigned_GH100.c" +#include "g_bindata_kgspGetBinArchiveGspRmCcFmcGfwProdSigned_GH100.c" #include "g_bindata_kgspGetBinArchiveBooterLoadUcode_TU102.c" #include "g_bindata_kgspGetBinArchiveBooterLoadUcode_TU116.c" #include "g_bindata_kgspGetBinArchiveBooterLoadUcode_GA100.c" @@ -112,8 +118,11 @@ #include "g_bindata_kgspGetBinArchiveGspRmBoot_GA102.c" #include "g_bindata_kgspGetBinArchiveGspRmBoot_AD102.c" #include "g_bindata_kgspGetBinArchiveGspRmBoot_GH100.c" +#include "g_bindata_kgspGetBinArchiveConcatenatedFMCDesc_GH100.c" +#include "g_bindata_kgspGetBinArchiveConcatenatedFMC_GH100.c" #include "g_bindata_kgspGetBinArchiveGspRmFmcGfwDebugSigned_GH100.c" #include "g_bindata_kgspGetBinArchiveGspRmFmcGfwProdSigned_GH100.c" +#include "g_bindata_kgspGetBinArchiveGspRmCcFmcGfwProdSigned_GH100.c" #include "g_bindata_kgspGetBinArchiveBooterLoadUcode_TU102.c" #include "g_bindata_kgspGetBinArchiveBooterLoadUcode_TU116.c" #include "g_bindata_kgspGetBinArchiveBooterLoadUcode_GA100.c" @@ -142,8 +151,11 @@ #include "g_bindata_kgspGetBinArchiveGspRmBoot_GA102.c" #include "g_bindata_kgspGetBinArchiveGspRmBoot_AD102.c" #include "g_bindata_kgspGetBinArchiveGspRmBoot_GH100.c" +#include "g_bindata_kgspGetBinArchiveConcatenatedFMCDesc_GH100.c" +#include "g_bindata_kgspGetBinArchiveConcatenatedFMC_GH100.c" #include "g_bindata_kgspGetBinArchiveGspRmFmcGfwDebugSigned_GH100.c" #include "g_bindata_kgspGetBinArchiveGspRmFmcGfwProdSigned_GH100.c" +#include "g_bindata_kgspGetBinArchiveGspRmCcFmcGfwProdSigned_GH100.c" #include "g_bindata_kgspGetBinArchiveBooterLoadUcode_TU102.c" #include "g_bindata_kgspGetBinArchiveBooterLoadUcode_TU116.c" #include "g_bindata_kgspGetBinArchiveBooterLoadUcode_GA100.c" diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/generated/g_bindata_kgspGetBinArchiveBooterLoadUcode_AD102.c nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_bindata_kgspGetBinArchiveBooterLoadUcode_AD102.c --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/generated/g_bindata_kgspGetBinArchiveBooterLoadUcode_AD102.c 2023-10-25 20:19:24.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_bindata_kgspGetBinArchiveBooterLoadUcode_AD102.c 2024-03-05 22:11:15.000000000 +0000 @@ -34,1387 +34,1906 @@ // VAR NAME: booter_ucode_data_ad10x // COMPRESSION: YES // COMPLEX_STRUCT: NO -// DATA SIZE (bytes): 33024 -// COMPRESSED SIZE (bytes): 22004 +// DATA SIZE (bytes): 55040 +// COMPRESSED SIZE (bytes): 30314 // static BINDATA_CONST NvU8 kgspBinArchiveBooterLoadUcode_AD102_image_dbg_data[] = { - 0xed, 0xdc, 0x73, 0xac, 0xac, 0xcd, 0x03, 0x27, 0xf8, 0x63, 0xdb, 0xbe, 0xc7, 0xb6, 0x6d, 0xdb, - 0xb6, 0x6d, 0xdb, 0xb6, 0xcf, 0x3d, 0xb6, 0x6d, 0xdb, 0xb6, 0xee, 0xb1, 0x6d, 0x6b, 0xde, 0x99, - 0xf9, 0x4d, 0x66, 0xf2, 0xee, 0xce, 0x3f, 0xbb, 0x9b, 0x6c, 0xb2, 0x7b, 0x3f, 0xc9, 0xb7, 0xeb, - 0xa9, 0xea, 0x4a, 0xaa, 0xbb, 0xba, 0xeb, 0x49, 0x9e, 0xee, 0xea, 0x06, 0x00, 0xf8, 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0xe0, 0x7f, 0x7b, 0xfd, 0x31, 0xff, + 0x87, 0x76, 0x40, 0x20, 0xfe, 0xcf, 0xeb, 0xa7, 0xfd, 0x1f, 0xf2, 0xe9, 0xff, 0x89, 0x8c, 0xff, + 0x84, 0xd8, 0x7f, 0x42, 0xfc, 0x3f, 0x21, 0xf1, 0x9f, 0x90, 0xfc, 0x9f, 0xe7, 0xa4, 0xff, 0x27, + 0x95, 0xf9, 0xaf, 0x76, 0xe4, 0xff, 0xf7, 0x76, 0x74, 0xfe, 0xe7, 0x3d, 0x00, 0xf8, 0x4f, 0x17, + 0x03, 0x28, 0x89, 0x30, 0x00, 0x08, 0xfd, 0xa7, 0x7b, 0x0d, 0x1c, 0x2d, 0x9c, 0xcd, 0x6d, 0x4c, + 0x9c, 0x2d, 0x8c, 0x08, 0x4c, 0x1c, 0x1d, 0xed, 0x1c, 0xa1, 0xfe, 0x4f, 0x96, 0xfe, 0xff, 0xaf, + 0xff, 0x05, 0xd4, 0x7b, 0xc1, 0x37, 0x00, 0xd7, 0x00, 0x00, }; #endif // defined(BINDATA_INCLUDE_DATA) @@ -1424,8 +1943,8 @@ #if defined(BINDATA_INCLUDE_STORAGE_PVT_DEFN) { - 33024, // uncompressed data size (bytes) - 22004, // compressed data size (bytes) + 55040, // uncompressed data size (bytes) + 30314, // compressed data size (bytes) kgspBinArchiveBooterLoadUcode_AD102_image_dbg_data, // compressed data pointer NV_TRUE, // is pData compressed? NV_TRUE, // contain information for file overriding? @@ -1447,8 +1966,8 @@ // static BINDATA_CONST NvU8 kgspBinArchiveBooterLoadUcode_AD102_header_dbg_data[] = { - 0x63, 0x60, 0x00, 0x02, 0x46, 0x20, 0x0e, 0x07, 0x62, 0x4d, 0x08, 0x13, 0x4c, 0x84, 0x41, 0x69, - 0x20, 0x00, 0x00, 0xd5, 0x45, 0x9c, 0x39, 0x24, 0x00, 0x00, 0x00, + 0x63, 0x60, 0x00, 0x02, 0x46, 0x20, 0x2e, 0x07, 0xe2, 0x04, 0x08, 0x13, 0x4c, 0x94, 0x41, 0x69, + 0x20, 0x00, 0x00, 0x6a, 0x2c, 0xe9, 0x9d, 0x24, 0x00, 0x00, 0x00, }; #endif // defined(BINDATA_INCLUDE_DATA) @@ -1476,1386 +1995,1906 @@ // VAR NAME: booter_ucode_data_ad10x // COMPRESSION: YES // COMPLEX_STRUCT: NO -// DATA SIZE (bytes): 33024 -// COMPRESSED SIZE (bytes): 22000 +// DATA SIZE (bytes): 55040 +// COMPRESSED SIZE (bytes): 30315 // static BINDATA_CONST NvU8 kgspBinArchiveBooterLoadUcode_AD102_image_prod_data[] = { - 0xed, 0xfc, 0x73, 0xac, 0xec, 0x41, 0xc3, 0x07, 0x78, 0x1e, 0xdb, 0xb6, 0x6d, 0xdb, 0xb6, 0xcd, - 0x7b, 0x6c, 0xdb, 0xb6, 0x6d, 0xdb, 0xb6, 0x6d, 0xdb, 0xf6, 0x3d, 0xb6, 0xe7, 0x99, 0x99, 0x77, - 0x32, 0x93, 0x67, 0x77, 0xfe, 0xd9, 0xdd, 0x64, 0x93, 0xdd, 0xfb, 0x49, 0xbe, 0x5d, 0xe8, 0x4a, - 0xaa, 0xbb, 0x3a, 0xbf, 0x4a, 0xba, 0xbb, 0xba, 0x01, 0x00, 0xfe, 0xff, 0x9b, 0xf0, 0xc5, 0x07, - 0x5c, 0x24, 0x76, 0xe4, 0xac, 0x50, 0x78, 0x29, 0x30, 0xa3, 0x4f, 0xe6, 0x5f, 0x91, 0x59, 0x6d, - 0xb3, 0xa6, 0xe7, 0x27, 0x21, 0x17, 0xa2, 0xd8, 0xb8, 0x9d, 0x78, 0xae, 0x0b, 0x5d, 0x33, 0xe2, - 0x76, 0x05, 0x5e, 0x3a, 0xf0, 0x9f, 0x1f, 0x11, 0x4e, 0x3d, 0x62, 0x19, 0xc9, 0xeb, 0x66, 0x9b, - 0xaa, 0xd9, 0xd7, 0xe1, 0xe1, 0x44, 0x85, 0xd8, 0x33, 0x9d, 0x1d, 0x65, 0x7f, 0x45, 0x62, 0x5a, - 0xd0, 0x29, 0x39, 0x25, 0x25, 0x83, 0x15, 0x93, 0xec, 0x4f, 0xbd, 0x89, 0xa5, 0x83, 0x90, 0x82, - 0x16, 0x49, 0xc8, 0x0d, 0xdd, 0x38, 0xf7, 0xa9, 0xd7, 0xbe, 0x21, 0xa3, 0x86, 0x68, 0xf7, 0xc8, - 0xdd, 0xb4, 0x3b, 0x47, 0x13, 0xc2, 0x27, 0xb5, 0xdf, 0xd4, 0x6d, 0x30, 0xd8, 0x6f, 0xf0, 0x63, - 0xa4, 0xe0, 0x12, 0xf4, 0x87, 0x54, 0x76, 0xbc, 0x4d, 0xa3, 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0x13, 0x7d, 0xa1, 0x02, 0xfc, 0xaf, 0x9f, 0x3f, 0xfa, + 0x7f, 0xd7, 0x0f, 0xc8, 0x9f, 0xff, 0xe3, 0xf6, 0xa9, 0xff, 0xbb, 0x7c, 0xda, 0x7f, 0x22, 0xfd, + 0x3f, 0x21, 0xf6, 0x9f, 0x10, 0xff, 0x4f, 0x48, 0xfc, 0x27, 0x24, 0xff, 0xe7, 0x3d, 0xe9, 0xff, + 0x49, 0x65, 0xfe, 0xab, 0x1f, 0xf9, 0xff, 0xad, 0x1f, 0x9d, 0xff, 0xf9, 0x0e, 0x00, 0xfe, 0x33, + 0xc4, 0x00, 0x4a, 0x22, 0xf4, 0x00, 0x42, 0xff, 0x19, 0x5e, 0x03, 0x47, 0x0b, 0x67, 0x73, 0x1b, + 0x13, 0x67, 0x0b, 0x23, 0x7c, 0x13, 0x47, 0x47, 0x3b, 0x47, 0xc8, 0xff, 0x83, 0xda, 0xff, 0xfb, + 0xfa, 0x7f, 0x01, 0x70, 0x4a, 0xaf, 0xb7, 0x00, 0xd7, 0x00, 0x00, }; #endif // defined(BINDATA_INCLUDE_DATA) @@ -2865,8 +3904,8 @@ #if defined(BINDATA_INCLUDE_STORAGE_PVT_DEFN) { - 33024, // uncompressed data size (bytes) - 22000, // compressed data size (bytes) + 55040, // uncompressed data size (bytes) + 30315, // compressed data size (bytes) kgspBinArchiveBooterLoadUcode_AD102_image_prod_data, // compressed data pointer NV_TRUE, // is pData compressed? NV_TRUE, // contain information for file overriding? @@ -2888,8 +3927,8 @@ // static BINDATA_CONST NvU8 kgspBinArchiveBooterLoadUcode_AD102_header_prod_data[] = { - 0x63, 0x60, 0x00, 0x02, 0x46, 0x20, 0x0e, 0x07, 0x62, 0x4d, 0x08, 0x13, 0x4c, 0x84, 0x41, 0x69, - 0x20, 0x00, 0x00, 0xd5, 0x45, 0x9c, 0x39, 0x24, 0x00, 0x00, 0x00, + 0x63, 0x60, 0x00, 0x02, 0x46, 0x20, 0x2e, 0x07, 0xe2, 0x04, 0x08, 0x13, 0x4c, 0x94, 0x41, 0x69, + 0x20, 0x00, 0x00, 0x6a, 0x2c, 0xe9, 0x9d, 0x24, 0x00, 0x00, 0x00, }; #endif // defined(BINDATA_INCLUDE_DATA) @@ -2922,55 +3961,55 @@ // static BINDATA_CONST NvU8 kgspBinArchiveBooterLoadUcode_AD102_sig_dbg_data[] = { - 0x01, 0x00, 0x03, 0xff, 0xfc, 0x6c, 0x0e, 0x43, 0x32, 0x75, 0x20, 0x86, 0x2c, 0x6c, 0xe5, 0x3a, - 0xeb, 0xc9, 0x91, 0x96, 0xd9, 0x07, 0x15, 0x0b, 0xd1, 0xea, 0xb6, 0xce, 0xa1, 0xf1, 0xb5, 0x86, - 0xa3, 0xed, 0x0f, 0x98, 0x17, 0x94, 0x87, 0x76, 0x53, 0x4d, 0x75, 0x04, 0x00, 0xb3, 0xa7, 0x66, - 0xfe, 0x50, 0x95, 0xdb, 0x32, 0xed, 0x05, 0x04, 0x50, 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0x07, 0xcf, 0xda, 0x1c, 0xf5, 0xb3, 0x78, 0x2e, 0xb4, + 0xe9, 0x99, 0x10, 0x3e, 0xce, 0xc7, 0x1e, 0x74, 0xb7, 0xe8, 0x96, 0xa4, 0x8b, 0x82, 0x6f, 0xea, + 0xd6, 0x23, 0xca, 0x10, 0x91, 0x8b, 0x59, 0xdd, 0x03, 0x00, 0x03, 0x00, 0x00, }; #endif // defined(BINDATA_INCLUDE_DATA) @@ -3003,55 +4042,55 @@ // static BINDATA_CONST NvU8 kgspBinArchiveBooterLoadUcode_AD102_sig_prod_data[] = { - 0x01, 0x00, 0x03, 0xff, 0xfc, 0x42, 0x8e, 0xfe, 0xf5, 0x06, 0x4e, 0x98, 0x04, 0x7e, 0xc3, 0x2b, - 0x83, 0x4d, 0x9a, 0x9a, 0xfc, 0x98, 0x38, 0x19, 0x41, 0xa2, 0xe1, 0xb4, 0x9d, 0x76, 0xf9, 0x77, - 0x55, 0xf5, 0x76, 0x2d, 0x31, 0xdd, 0xd6, 0xff, 0xf8, 0x06, 0xf5, 0xe2, 0xc2, 0xb1, 0xb7, 0x3b, - 0xc7, 0x78, 0x7f, 0x99, 0x52, 0xfb, 0x94, 0x6d, 0x20, 0x6a, 0x21, 0x36, 0x67, 0x7c, 0x0e, 0x16, - 0xb3, 0x8e, 0x7d, 0x49, 0xf8, 0x18, 0x07, 0x82, 0x4b, 0x9a, 0xf4, 0x3a, 0xa1, 0x44, 0x1c, 0x00, - 0x66, 0x14, 0x93, 0x68, 0xc0, 0x29, 0x7f, 0x43, 0x3c, 0xa8, 0x0e, 0x81, 0xba, 0x79, 0xda, 0x91, - 0x4f, 0x59, 0x42, 0xec, 0x10, 0xcd, 0xd1, 0x3a, 0x4d, 0x5d, 0xd7, 0xdb, 0x37, 0x82, 0x78, 0x01, - 0x1b, 0xb3, 0xcc, 0x85, 0xff, 0x75, 0x92, 0xb3, 0x52, 0xa3, 0x53, 0xa5, 0x62, 0x52, 0x38, 0x55, - 0xec, 0x63, 0x27, 0x10, 0x0d, 0xf4, 0xed, 0x0b, 0x0c, 0xf1, 0x9b, 0x2b, 0xee, 0xb3, 0x81, 0x42, - 0x80, 0x2b, 0xd4, 0xd9, 0x3c, 0xdf, 0x6b, 0x72, 0x7c, 0xaf, 0xf8, 0xfa, 0x84, 0xdd, 0x6a, 0xc5, - 0xed, 0x0f, 0x16, 0x66, 0xe5, 0x53, 0xc8, 0x31, 0xd3, 0xa6, 0xa8, 0x4d, 0xd1, 0xa1, 0x6b, 0xf4, - 0x43, 0xae, 0x72, 0x5f, 0x99, 0x64, 0xde, 0x07, 0x78, 0xcc, 0x5e, 0xb6, 0x32, 0x24, 0x90, 0xf6, - 0xff, 0x1b, 0x2f, 0x10, 0x1c, 0x72, 0x0d, 0x60, 0x72, 0xde, 0x7d, 0xbd, 0x42, 0x82, 0x24, 0x77, - 0x58, 0x36, 0x68, 0xa2, 0x46, 0x2c, 0x35, 0x5c, 0x8f, 0x40, 0x2c, 0xb2, 0x15, 0xd8, 0xf5, 0xef, - 0x4b, 0xe3, 0xd7, 0x8d, 0x4b, 0xf2, 0xe7, 0x42, 0xb2, 0x87, 0xfc, 0x58, 0x0f, 0x13, 0xf7, 0xc3, - 0x26, 0x5b, 0x2a, 0xfc, 0x36, 0x6c, 0xca, 0xbc, 0x20, 0xa7, 0x75, 0x50, 0x3e, 0xce, 0x07, 0x2a, - 0xeb, 0x53, 0xf7, 0x66, 0x2e, 0xdc, 0xb3, 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defined(BINDATA_INCLUDE_DATA) @@ -3084,7 +4123,7 @@ // static BINDATA_CONST NvU8 kgspBinArchiveBooterLoadUcode_AD102_patch_loc_data[] = { - 0x10, 0x57, 0x00, 0x00, + 0x10, 0x77, 0x00, 0x00, }; #endif // defined(BINDATA_INCLUDE_DATA) diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/generated/g_bindata_kgspGetBinArchiveBooterLoadUcode_GA100.c nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_bindata_kgspGetBinArchiveBooterLoadUcode_GA100.c --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/generated/g_bindata_kgspGetBinArchiveBooterLoadUcode_GA100.c 2023-10-25 20:19:25.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_bindata_kgspGetBinArchiveBooterLoadUcode_GA100.c 2024-03-05 22:11:15.000000000 +0000 @@ -34,1501 +34,2063 @@ // VAR NAME: booter_ucode_data_ga100 // COMPRESSION: YES // COMPLEX_STRUCT: NO -// DATA SIZE (bytes): 36352 -// COMPRESSED SIZE (bytes): 23832 +// DATA SIZE (bytes): 58624 +// COMPRESSED SIZE (bytes): 32824 // static BINDATA_CONST NvU8 kgspBinArchiveBooterLoadUcode_GA100_image_dbg_data[] = { - 0xed, 0xfc, 0x43, 0x90, 0x28, 0x4d, 0xc3, 0x06, 0x6c, 0xb6, 0x6d, 0xdb, 0xb6, 0x4f, 0xdb, 0xc6, - 0x69, 0xdb, 0xb6, 0x6d, 0xdb, 0xb6, 0x6d, 0xdb, 0xb6, 0x6d, 0xdb, 0x76, 0xf7, 0xff, 0x7e, 0x13, - 0x31, 0x9b, 0x67, 0x37, 0xbb, 0x99, 0x89, 0x73, 0x6d, 0x12, 0x11, 0x95, 0x95, 0x8b, 0xaa, 0x8c, - 0x8a, 0xb8, 0x33, 0x4b, 0x02, 0x00, 0x61, 0x26, 0x1d, 0x20, 0x16, 0x00, 0x1c, 0xa0, 0xfb, 0x28, - 0xef, 0xbd, 0xf9, 0x07, 0x50, 0x02, 0x00, 0xf1, 0xff, 0x3a, 0x20, 0xc0, 0x01, 0xfe, 0x5f, 0xcd, - 0x70, 0x00, 0x00, 0xc0, 0x9f, 0x24, 0x00, 0x1f, 0x7a, 0x00, 0x80, 0x37, 0xa0, 0x37, 0x80, 0x77, - 0xa0, 0x68, 0x00, 0x20, 0x80, 0xde, 0x9d, 0xdd, 0xdf, 0xdf, 0x5f, 0xf8, 0x70, 0x00, 0x40, 0x80, - 0xdf, 0x5c, 0x90, 0xc6, 0x23, 0x00, 0xe6, 0xb4, 0x75, 0xc0, 0xc6, 0x24, 0x00, 0x9a, 0xb4, 0x75, - 0xa0, 0xff, 0x15, 0xa4, 0x69, 0xeb, 0xc0, 0xff, 0x2b, 0xf0, 0xfe, 0x77, 0x2d, 0x40, 0x5a, 0x2e, - 0x70, 0xf3, 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0xd2, 0xe5, 0x3f, 0xaa, 0x00, 0x8e, 0x00, 0x00, + 0xf9, 0xe7, 0x9f, 0x7f, 0xfe, 0xf9, 0xe7, 0x9f, 0x7f, 0xfe, 0xf9, 0xe7, 0x9f, 0x7f, 0xfe, 0xf9, + 0xe7, 0x9f, 0x7f, 0xfe, 0xf9, 0xe7, 0x9f, 0x7f, 0xfe, 0xf9, 0xe7, 0x9f, 0x7f, 0xfe, 0xf9, 0xe7, + 0x9f, 0x7f, 0xfe, 0xf9, 0xe7, 0x9f, 0x7f, 0xfe, 0xf9, 0xe7, 0x9f, 0x7f, 0xfe, 0xf9, 0xe7, 0x9f, + 0x7f, 0xfe, 0xf9, 0xe7, 0x9f, 0x7f, 0xfe, 0xf9, 0xe7, 0x9f, 0x7f, 0xfe, 0xff, 0xf6, 0xff, 0x00, + 0x49, 0xa8, 0xf4, 0xd1, 0x00, 0xe5, 0x00, 0x00, }; #endif // defined(BINDATA_INCLUDE_DATA) @@ -1538,8 +2100,8 @@ #if defined(BINDATA_INCLUDE_STORAGE_PVT_DEFN) { - 36352, // uncompressed data size (bytes) - 23832, // compressed data size (bytes) + 58624, // uncompressed data size (bytes) + 32824, // compressed data size (bytes) kgspBinArchiveBooterLoadUcode_GA100_image_dbg_data, // compressed data pointer NV_TRUE, // is pData compressed? NV_TRUE, // contain information for file overriding? @@ -1561,8 +2123,8 @@ // static BINDATA_CONST NvU8 kgspBinArchiveBooterLoadUcode_GA100_header_dbg_data[] = { - 0x63, 0x60, 0x00, 0x02, 0x46, 0x20, 0x4e, 0x00, 0x62, 0x3d, 0x08, 0x13, 0x4c, 0xc4, 0x43, 0x69, - 0x20, 0x00, 0x00, 0x87, 0x58, 0x20, 0x04, 0x24, 0x00, 0x00, 0x00, + 0x63, 0x60, 0x00, 0x02, 0x46, 0x20, 0x6e, 0x04, 0xe2, 0x14, 0x08, 0x13, 0x4c, 0x34, 0x40, 0x69, + 0x20, 0x00, 0x00, 0x90, 0x7b, 0x92, 0x9e, 0x24, 0x00, 0x00, 0x00, }; #endif // defined(BINDATA_INCLUDE_DATA) @@ -1590,1501 +2152,2063 @@ // VAR NAME: booter_ucode_data_ga100 // COMPRESSION: YES // COMPLEX_STRUCT: NO -// DATA SIZE (bytes): 36352 -// COMPRESSED SIZE (bytes): 23828 +// DATA SIZE (bytes): 58624 +// COMPRESSED SIZE (bytes): 32824 // static BINDATA_CONST NvU8 kgspBinArchiveBooterLoadUcode_GA100_image_prod_data[] = { - 0xed, 0xfc, 0x43, 0xb0, 0x68, 0x4d, 0xdb, 0x06, 0xe0, 0x6d, 0xdb, 0xb6, 0x6d, 0xdb, 0xb6, 0x6d, - 0xdb, 0xb6, 0x6d, 0xfb, 0x6c, 0xdb, 0xb6, 0xed, 0xb3, 0x6d, 0xdb, 0x36, 0xf3, 0xfd, 0xa9, 0xca, - 0xe4, 0xcd, 0x28, 0xb3, 0x24, 0x75, 0xae, 0x49, 0xa3, 0x6a, 0xad, 0xd5, 0x93, 0xee, 0xc9, 0xdd, - 0xcf, 0x92, 0x04, 0x40, 0x98, 0xcd, 0x04, 0x88, 0x07, 0x00, 0x07, 0xe8, 0x39, 0xca, 0x7f, 0x6f, - 0xf9, 0x01, 0x94, 0x04, 0x40, 0xfc, 0xbf, 0x09, 0x08, 0x70, 0x80, 0xff, 0xe7, 0x30, 0x12, 0x00, - 0x00, 0xf0, 0x27, 0x05, 0xc0, 0x8f, 0x1e, 0x00, 0xe0, 0x0d, 0xe8, 0x0d, 0xe0, 0x1d, 0x28, 0x16, - 0x00, 0x08, 0xa0, 0x6f, 0x67, 0xf7, 0xf7, 0xf7, 0x17, 0x3e, 0x12, 0x00, 0x10, 0xe0, 0x37, 0x0f, - 0xa4, 0xe9, 0x08, 0x80, 0x39, 0x63, 0x1d, 0xb0, 0x29, 0x05, 0x80, 0x26, 0x63, 0x1d, 0xe8, 0x7f, - 0x0d, 0x69, 0xc6, 0x3a, 0xf0, 0xff, 0x1a, 0xbc, 0xff, 0x3d, 0x0b, 0x90, 0x91, 0x07, 0xdc, 0xb2, - 0x0b, 0xdc, 0x97, 0x97, 0xbf, 0x9b, 0x91, 0x07, 0x98, 0x91, 0x09, 0xd4, 0xb2, 0x0b, 0xd8, 0xb2, - 0x0e, 0xe4, 0xb7, 0x0b, 0x00, 0x00, 0xcf, 0x28, 0x09, 0x80, 0xf0, 0x9a, 0x07, 0xd0, 0x93, 0x12, - 0xff, 0xbf, 0x57, 0xb6, 0xbc, 0x07, 0xb6, 0xbc, 0x07, 0x44, 0x02, 0x84, 0x80, 0xfc, 0x6f, 0x0a, - 0x1e, 0xb0, 0x3d, 0x13, 0x00, 0x17, 0xe8, 0xff, 0x7a, 0xc0, 0xff, 0xeb, 0x01, 0x02, 0xfd, 0xbf, - 0xe6, 0xc0, 0xfe, 0xaf, 0xf7, 0xbf, 0xd7, 0x02, 0xa5, 0xc2, 0x43, 0xec, 0xfc, 0xdf, 0x12, 0xbe, - 0xdf, 0x41, 0x23, 0x01, 0x0c, 0x00, 0xbe, 0x73, 0x41, 0xba, 0x12, 0x80, 0x5a, 0x53, 0x10, 0xfe, - 0x37, 0xfe, 0xf9, 0x00, 0xf0, 0xfb, 0xdf, 0xc2, 0xde, 0x80, 0x7a, 0x8a, 0x3f, 0x01, 0xe3, 0x67, - 0xc7, 0x20, 0x22, 0x09, 0x68, 0x01, 0xf2, 0xf3, 0xde, 0x00, 0xe2, 0xff, 0xd7, 0xf6, 0xfd, 0x3e, - 0x31, 0x7c, 0xfd, 0x48, 0x02, 0xe6, 0xe7, 0xf1, 0xbd, 0x03, 0xfc, 0x9f, 0x9e, 0x07, 0x33, 0xf2, - 0x7c, 0x50, 0xcf, 0xae, 0x82, 0x1e, 0x95, 0xd4, 0x4d, 0xf8, 0x44, 0x23, 0x81, 0x96, 0xd6, 0x65, - 0x9c, 0x30, 0xa6, 0xc2, 0x6f, 0x98, 0x9f, 0xe4, 0xd2, 0x86, 0x61, 0xd1, 0x04, 0x3b, 0x6d, 0x07, - 0x6f, 0xc1, 0x91, 0x18, 0xaa, 0x45, 0x73, 0x78, 0xc7, 0x8b, 0x42, 0x6d, 0x79, 0x85, 0xd4, 0xf4, - 0x5d, 0xd4, 0x7e, 0x08, 0xc7, 0xa0, 0x8c, 0x97, 0x8b, 0x8f, 0x54, 0x72, 0xd2, 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0x15, 0x0f, 0x26, 0xe6, 0x74, 0xab, 0xb5, 0xbd, 0xdf, 0x3f, 0x5f, 0x03, 0x3e, 0x35, 0x12, 0x4f, - 0x88, 0x62, 0xb2, 0x0e, 0x38, 0x0b, 0x87, 0xee, 0x14, 0x1e, 0x69, 0x2b, 0x11, 0xb3, 0x52, 0x7b, - 0x1c, 0x77, 0x7d, 0xe0, 0x05, 0xe4, 0x9d, 0xa0, 0x7b, 0xbe, 0x85, 0x40, 0x4c, 0x3c, 0x9f, 0x9b, - 0xd3, 0x21, 0x53, 0xd5, 0xfd, 0x55, 0x5f, 0xa2, 0xfd, 0x5b, 0x9b, 0x21, 0x1a, 0x79, 0xfd, 0xee, - 0xaf, 0x11, 0xed, 0xde, 0x7e, 0xcd, 0xaa, 0xdf, 0x06, 0xfe, 0x15, 0x67, 0xde, 0xbd, 0x15, 0x76, - 0xd5, 0x7f, 0x13, 0xae, 0x2a, 0x91, 0x89, 0x32, 0x1b, 0xe3, 0xda, 0x66, 0x2f, 0xac, 0xf0, 0x77, - 0x8c, 0x9b, 0x32, 0x5d, 0xee, 0xcf, 0x48, 0x29, 0x34, 0x25, 0xea, 0xe9, 0x92, 0x6a, 0x48, 0x68, - 0x5f, 0x10, 0x9d, 0xe0, 0x14, 0x3f, 0x92, 0x2f, 0x4b, 0x39, 0x6a, 0xdb, 0x16, 0x6d, 0x4c, 0xc1, - 0x98, 0xbd, 0xe4, 0x58, 0xaa, 0x77, 0x94, 0xc9, 0x77, 0xbf, 0xae, 0x1a, 0xbc, 0x0b, 0xbe, 0xab, - 0x1d, 0xe4, 0x0e, 0x27, 0x52, 0xba, 0xfb, 0x94, 0x19, 0x14, 0x00, 0x69, 0x17, 0x5a, 0x2d, 0xca, - 0xb5, 0x95, 0x11, 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0xfa, 0xf5, 0xeb, 0xd7, 0xaf, 0x5f, 0xbf, 0x7e, 0xfd, 0xfa, 0xf5, 0xeb, + 0xd7, 0xaf, 0x5f, 0xbf, 0x7e, 0xfd, 0xfa, 0xf5, 0xeb, 0xd7, 0xaf, 0x5f, 0xbf, 0x7e, 0xfd, 0xfa, + 0xf5, 0xeb, 0xd7, 0xaf, 0x5f, 0xbf, 0x7e, 0xfd, 0xfa, 0xf5, 0xeb, 0xd7, 0xaf, 0x5f, 0xbf, 0x7e, + 0xfd, 0xfa, 0xf5, 0xeb, 0xd7, 0xaf, 0x5f, 0xbf, 0x7e, 0xfd, 0xfa, 0xf5, 0xff, 0xda, 0xff, 0x07, + 0x59, 0xf2, 0x2e, 0xba, 0x00, 0xe5, 0x00, 0x00, }; #endif // defined(BINDATA_INCLUDE_DATA) @@ -3094,8 +4218,8 @@ #if defined(BINDATA_INCLUDE_STORAGE_PVT_DEFN) { - 36352, // uncompressed data size (bytes) - 23828, // compressed data size (bytes) + 58624, // uncompressed data size (bytes) + 32824, // compressed data size (bytes) kgspBinArchiveBooterLoadUcode_GA100_image_prod_data, // compressed data pointer NV_TRUE, // is pData compressed? NV_TRUE, // contain information for file overriding? @@ -3117,8 +4241,8 @@ // static BINDATA_CONST NvU8 kgspBinArchiveBooterLoadUcode_GA100_header_prod_data[] = { - 0x63, 0x60, 0x00, 0x02, 0x46, 0x20, 0x4e, 0x00, 0x62, 0x3d, 0x08, 0x13, 0x4c, 0xc4, 0x43, 0x69, - 0x20, 0x00, 0x00, 0x87, 0x58, 0x20, 0x04, 0x24, 0x00, 0x00, 0x00, + 0x63, 0x60, 0x00, 0x02, 0x46, 0x20, 0x6e, 0x04, 0xe2, 0x14, 0x08, 0x13, 0x4c, 0x34, 0x40, 0x69, + 0x20, 0x00, 0x00, 0x90, 0x7b, 0x92, 0x9e, 0x24, 0x00, 0x00, 0x00, }; #endif // defined(BINDATA_INCLUDE_DATA) @@ -3151,31 +4275,31 @@ // static BINDATA_CONST NvU8 kgspBinArchiveBooterLoadUcode_GA100_sig_dbg_data[] = { - 0x01, 0x80, 0x01, 0x7f, 0xfe, 0x40, 0x07, 0xac, 0x9b, 0x5d, 0xf4, 0x1d, 0xdd, 0x6b, 0xd5, 0x5a, - 0xf1, 0xef, 0x4c, 0x4b, 0x38, 0x51, 0x2c, 0x5e, 0x3e, 0xed, 0x96, 0x68, 0xad, 0xda, 0x7e, 0xf0, - 0x11, 0xa2, 0x77, 0x1a, 0xf0, 0xe6, 0x27, 0x8e, 0xaf, 0xd1, 0xa3, 0x5c, 0x1b, 0xbb, 0x3b, 0x7e, - 0xf7, 0xd7, 0x80, 0x80, 0x71, 0x9d, 0x4b, 0xa5, 0xdf, 0x9e, 0x82, 0x18, 0xa1, 0x1a, 0x5b, 0x6c, - 0xc8, 0x7c, 0x07, 0x09, 0xa8, 0xfd, 0xc6, 0x46, 0x6d, 0x00, 0xeb, 0xc3, 0x82, 0x94, 0xb5, 0x54, - 0x6f, 0xbc, 0x65, 0xbd, 0xb8, 0xcc, 0x4a, 0xde, 0xca, 0x33, 0xf9, 0xfd, 0x47, 0xb6, 0x77, 0x54, - 0xf4, 0xec, 0xfc, 0x3a, 0xa2, 0xf9, 0x2d, 0x9c, 0xd5, 0x89, 0x90, 0x79, 0xb7, 0x52, 0xc2, 0x61, - 0x8f, 0x07, 0x41, 0xc7, 0x1f, 0x2e, 0x5c, 0xf2, 0xe5, 0xd3, 0x80, 0x9d, 0x28, 0x89, 0x37, 0xab, - 0xdd, 0xc0, 0x63, 0xc6, 0x21, 0x29, 0x84, 0x7a, 0x71, 0x23, 0x82, 0x92, 0x81, 0xb2, 0x38, 0x36, - 0xa7, 0xe9, 0xef, 0xa9, 0x60, 0x09, 0x32, 0x8a, 0x68, 0xac, 0x5e, 0x20, 0x7d, 0x9c, 0xe8, 0x0c, - 0xea, 0xb9, 0x6c, 0x17, 0x10, 0xae, 0x75, 0x0f, 0x8e, 0xd1, 0x5c, 0xe4, 0x98, 0x34, 0xf5, 0x40, - 0xdb, 0x1c, 0x9e, 0xe7, 0x19, 0xd6, 0x2f, 0x8e, 0x88, 0xfc, 0x51, 0x12, 0x80, 0x57, 0x83, 0xca, - 0x56, 0x83, 0xc7, 0x68, 0xf5, 0xe4, 0x63, 0xcb, 0x98, 0xc3, 0x4d, 0x29, 0x56, 0x68, 0x7f, 0xad, - 0xa5, 0xe6, 0x01, 0x5a, 0x03, 0xdb, 0x95, 0xaa, 0xec, 0x32, 0x78, 0x3a, 0xeb, 0x24, 0x6d, 0x41, - 0x61, 0xd5, 0x3d, 0x7f, 0x56, 0xe6, 0x37, 0x8a, 0x00, 0x9e, 0x62, 0x18, 0x1d, 0xca, 0x0b, 0x7e, - 0x9a, 0x15, 0xcf, 0x6a, 0xf2, 0xb1, 0x6b, 0x4d, 0xf4, 0xdb, 0xf7, 0xe0, 0x96, 0xa6, 0xbf, 0x1d, - 0x31, 0x7d, 0x21, 0xdc, 0xbb, 0x1a, 0xe4, 0x45, 0xf8, 0xa1, 0xaa, 0x91, 0xfb, 0xc8, 0x07, 0x4d, - 0xb4, 0x36, 0x7d, 0xaa, 0x2a, 0x3e, 0x19, 0xdf, 0x59, 0x77, 0xab, 0xbc, 0xf7, 0x44, 0x89, 0xcc, - 0xe4, 0x4d, 0x3f, 0xc6, 0x5f, 0x82, 0xf0, 0xde, 0x6b, 0x83, 0xdd, 0x5b, 0xe9, 0x15, 0x89, 0x0d, - 0x56, 0x1f, 0x83, 0xc4, 0x10, 0xc5, 0xe6, 0xbe, 0xcb, 0x24, 0x6d, 0x66, 0x2b, 0xdd, 0xdf, 0xc5, - 0xa6, 0x03, 0x90, 0xe4, 0xb7, 0xc3, 0x33, 0x28, 0x59, 0xa6, 0x62, 0x45, 0xf3, 0x97, 0xbd, 0xd2, - 0x99, 0x3f, 0x82, 0x69, 0xa2, 0xcb, 0xe7, 0x2a, 0xe9, 0x51, 0xe7, 0x3d, 0x41, 0x52, 0x74, 0x7b, - 0xfd, 0x02, 0x0f, 0x74, 0xa0, 0xfe, 0xc5, 0x37, 0x51, 0x97, 0xe7, 0x1d, 0xd4, 0x9d, 0xe1, 0xe2, - 0x1e, 0xb1, 0x24, 0x88, 0xe1, 0xd6, 0x29, 0x14, 0xaf, 0xba, 0x9f, 0xd3, 0x93, 0x4a, 0x97, 0x79, - 0x82, 0xaf, 0x03, 0xa7, 0x12, 0xa2, 0x10, 0xd8, 0x8b, 0x80, 0x01, 0x00, 0x00, + 0x01, 0x80, 0x01, 0x7f, 0xfe, 0x7b, 0xff, 0x6d, 0xfb, 0x28, 0x8d, 0x38, 0xe2, 0x29, 0x9b, 0xdc, + 0x72, 0xcc, 0xcb, 0x2b, 0xc7, 0x08, 0x50, 0x40, 0x65, 0xa8, 0xff, 0x6f, 0x6a, 0x21, 0xe2, 0x14, + 0xef, 0xea, 0x9f, 0xa2, 0x97, 0xa5, 0x15, 0x11, 0x72, 0x9d, 0xe8, 0x24, 0xee, 0x29, 0xf0, 0x19, + 0xd0, 0x07, 0x1f, 0x0a, 0x33, 0x8b, 0xdc, 0x2e, 0x2e, 0x72, 0xb9, 0x67, 0x79, 0x48, 0xb0, 0xe7, + 0x23, 0xef, 0xb9, 0xe7, 0x15, 0xbf, 0x50, 0xe3, 0x56, 0xc9, 0x26, 0x28, 0x8a, 0x66, 0xbf, 0xf0, + 0xac, 0xe1, 0x07, 0x39, 0xfd, 0x97, 0x40, 0x2e, 0xb5, 0xa1, 0x49, 0x0c, 0xdf, 0x6a, 0xae, 0x52, + 0x99, 0x20, 0x5f, 0xd9, 0xf1, 0xbc, 0xee, 0x40, 0xc0, 0x04, 0x35, 0x6a, 0x63, 0x6c, 0x97, 0x53, + 0x5c, 0x64, 0x0f, 0x91, 0xa0, 0xac, 0x59, 0x6c, 0xdf, 0x93, 0x31, 0xd4, 0x93, 0xdb, 0xe0, 0x2b, + 0x17, 0x9a, 0x9e, 0x62, 0xb0, 0xf7, 0xbc, 0x62, 0xfe, 0x83, 0x71, 0x86, 0x7c, 0xed, 0x92, 0x67, + 0xba, 0x3c, 0xdf, 0xb6, 0x2e, 0x53, 0x67, 0x6e, 0x81, 0x89, 0xf4, 0xb6, 0xac, 0x2b, 0x74, 0xaa, + 0xad, 0x10, 0x0f, 0x8b, 0xa8, 0xf1, 0x5d, 0x32, 0x42, 0x72, 0xf8, 0xef, 0xbf, 0xb7, 0xcd, 0x7e, + 0xe8, 0x5f, 0xdc, 0xb8, 0xfa, 0x48, 0xb7, 0x71, 0xe7, 0x83, 0x63, 0x35, 0xe2, 0x59, 0xbb, 0x5d, + 0x09, 0x78, 0x9e, 0x18, 0x0b, 0xac, 0xec, 0x58, 0x05, 0xbe, 0x44, 0x0e, 0xc5, 0xf2, 0x4d, 0xc3, + 0x1e, 0x49, 0x52, 0x43, 0x22, 0x63, 0x2d, 0x1c, 0x7b, 0xe3, 0xb1, 0x2e, 0xff, 0x5c, 0x50, 0xe4, + 0xe6, 0x58, 0x9e, 0x00, 0xb6, 0x56, 0xb7, 0xe8, 0xd7, 0xe4, 0x5c, 0xe1, 0x1a, 0x46, 0xe8, 0xbf, + 0x52, 0xe1, 0x27, 0x36, 0x9b, 0x1b, 0x7c, 0xe3, 0xc7, 0x61, 0x5d, 0xbe, 0x03, 0x3a, 0xde, 0xeb, + 0x17, 0xe5, 0x6b, 0xe3, 0x9c, 0x8d, 0x75, 0xeb, 0xed, 0x01, 0xf6, 0xb7, 0x46, 0xb0, 0xd0, 0x4b, + 0xd8, 0x51, 0x6c, 0x80, 0xfe, 0xf6, 0x7a, 0x95, 0x1f, 0x97, 0x35, 0x67, 0x22, 0x6f, 0x21, 0xd6, + 0xbf, 0x3b, 0x12, 0xa6, 0xbb, 0x1f, 0x24, 0x1a, 0x32, 0x36, 0x60, 0xbb, 0xda, 0x2c, 0xf1, 0x6f, + 0x8a, 0xf5, 0x78, 0x02, 0x39, 0x9f, 0xf3, 0x38, 0x38, 0x55, 0x2b, 0x3c, 0x26, 0x39, 0x0d, 0x2b, + 0xb6, 0x8e, 0xd0, 0xdc, 0xa7, 0xf5, 0x6c, 0x00, 0x39, 0xbf, 0x5e, 0xc8, 0x1f, 0x28, 0xbb, 0xe4, + 0x5a, 0xd3, 0x9a, 0x5f, 0x2c, 0xf1, 0xc5, 0x88, 0x2e, 0x79, 0x31, 0x88, 0x12, 0x40, 0xec, 0x0f, + 0xf1, 0x94, 0x78, 0x9e, 0xf4, 0x8e, 0x65, 0x56, 0x0f, 0xd1, 0x0a, 0x89, 0x5a, 0xb8, 0x8e, 0x10, + 0x21, 0x96, 0x37, 0xa9, 0xd4, 0x7b, 0x4b, 0xad, 0x6c, 0x55, 0xcc, 0x8b, 0xc1, 0xb8, 0xb0, 0x93, + 0x6e, 0xda, 0x6c, 0xc8, 0x7f, 0x44, 0x50, 0xac, 0xb1, 0x80, 0x01, 0x00, 0x00, }; #endif // defined(BINDATA_INCLUDE_DATA) @@ -3208,31 +4332,31 @@ // static BINDATA_CONST NvU8 kgspBinArchiveBooterLoadUcode_GA100_sig_prod_data[] = { - 0x01, 0x80, 0x01, 0x7f, 0xfe, 0xab, 0xf2, 0xff, 0xd7, 0x03, 0x58, 0xb3, 0xc7, 0xdb, 0xb5, 0xc8, - 0xcf, 0xde, 0xf4, 0x3d, 0xe1, 0x67, 0x8a, 0x76, 0x59, 0x3b, 0xa2, 0x10, 0x91, 0x47, 0xa6, 0x27, - 0x0c, 0xbb, 0xb3, 0x7f, 0x16, 0xc0, 0xa8, 0x89, 0x4b, 0x32, 0xdc, 0xe9, 0x85, 0x24, 0xde, 0x32, - 0x79, 0x68, 0x16, 0xf6, 0xb3, 0xbd, 0xbe, 0x9f, 0xc5, 0x2b, 0xd7, 0x57, 0xaf, 0x35, 0x5d, 0x37, - 0xda, 0x5a, 0xe1, 0x04, 0xa4, 0xac, 0x6c, 0x7b, 0x12, 0x09, 0x29, 0xaf, 0x70, 0x2f, 0xbb, 0x41, - 0x13, 0x91, 0xe3, 0xaf, 0x8c, 0xd5, 0xa3, 0x38, 0x0a, 0xb0, 0x7d, 0x15, 0x00, 0xd9, 0x07, 0x69, - 0x3c, 0xe9, 0x9d, 0xad, 0xc6, 0x34, 0x4b, 0x63, 0xfb, 0x91, 0x1d, 0x93, 0xd9, 0x6d, 0x44, 0x89, - 0xa1, 0xc5, 0x9c, 0x50, 0x0a, 0xdc, 0xd1, 0x02, 0xc3, 0x9a, 0x0a, 0x53, 0xf2, 0x2e, 0x40, 0xc8, - 0xdb, 0x75, 0xc8, 0xf4, 0xa9, 0x16, 0xee, 0x81, 0x03, 0x7f, 0x62, 0xfe, 0x98, 0x5f, 0x87, 0x0c, - 0xed, 0xa9, 0xd5, 0x04, 0x7e, 0xa7, 0x33, 0x28, 0x4c, 0xe4, 0xfc, 0x2d, 0x35, 0x76, 0x85, 0xc1, - 0xb2, 0x54, 0xb7, 0xbd, 0x5d, 0xde, 0x9c, 0xc0, 0x44, 0xc8, 0xbc, 0xa2, 0xb7, 0x6a, 0xa1, 0x42, - 0x71, 0x4a, 0x09, 0x9b, 0x19, 0x80, 0x44, 0xe3, 0x82, 0x38, 0xc0, 0xc8, 0x95, 0xd8, 0x80, 0xe5, - 0x47, 0xf2, 0xd4, 0x1b, 0xc7, 0x74, 0xb7, 0x67, 0xa5, 0x07, 0x19, 0x65, 0xb2, 0x2f, 0xaa, 0x62, - 0x99, 0xfc, 0x74, 0xc6, 0x83, 0x91, 0x9a, 0x49, 0x0a, 0x64, 0x84, 0xc7, 0x06, 0x5e, 0xe3, 0xde, - 0x32, 0xbe, 0xd4, 0x6d, 0x8e, 0x71, 0x0f, 0x57, 0xd8, 0x51, 0xda, 0xc0, 0x69, 0xa7, 0x90, 0x9e, - 0xfd, 0x32, 0xea, 0x85, 0x3d, 0x07, 0x60, 0xe3, 0x2a, 0x60, 0x0f, 0xe1, 0x77, 0x38, 0xa7, 0x45, - 0x05, 0x70, 0x23, 0x44, 0xae, 0x89, 0x02, 0x87, 0xd9, 0x54, 0x0b, 0xd6, 0x97, 0xb5, 0x0d, 0xc5, - 0x12, 0xd3, 0x91, 0x52, 0x9f, 0x37, 0xcf, 0xdf, 0x7e, 0x08, 0x79, 0x35, 0xad, 0x4a, 0xfa, 0xa5, - 0x2b, 0x34, 0xad, 0x87, 0x8a, 0xa8, 0x0b, 0x34, 0x47, 0x12, 0x1b, 0x78, 0xc3, 0x55, 0x91, 0x5a, - 0xb2, 0xdd, 0x9e, 0xc0, 0x25, 0xe7, 0x86, 0x93, 0x1a, 0xdb, 0x71, 0xea, 0xf6, 0xb8, 0xcf, 0x79, - 0x12, 0x1c, 0xf5, 0xbd, 0x5b, 0xa5, 0x0f, 0x84, 0x33, 0xba, 0x18, 0xa2, 0xdb, 0x74, 0xad, 0x3e, - 0x39, 0xe9, 0x89, 0xd7, 0xb9, 0xdf, 0x8c, 0xba, 0x3d, 0x55, 0xb6, 0x32, 0xb3, 0x8b, 0x23, 0x8c, - 0x52, 0x57, 0x66, 0x26, 0x56, 0xbf, 0x8f, 0xae, 0xf9, 0x90, 0xfd, 0xf4, 0xc3, 0x1a, 0x38, 0x77, - 0x6c, 0xf1, 0xc3, 0x61, 0xd5, 0x73, 0x11, 0x7d, 0x9c, 0x38, 0xdb, 0x75, 0x98, 0x37, 0x06, 0x99, - 0xee, 0x33, 0xfe, 0xd0, 0x9b, 0x7f, 0x80, 0x20, 0xcf, 0x80, 0x01, 0x00, 0x00, + 0x01, 0x80, 0x01, 0x7f, 0xfe, 0x7e, 0x88, 0x43, 0xf1, 0xcc, 0x3a, 0x3f, 0x99, 0x2c, 0x9b, 0x79, + 0x47, 0xd9, 0x1a, 0x17, 0x13, 0xd8, 0x75, 0x94, 0x97, 0x3e, 0xfe, 0x09, 0x8c, 0xa5, 0x1c, 0x48, + 0x0e, 0x0d, 0xed, 0xd4, 0xd9, 0xd4, 0xfa, 0x99, 0xc5, 0x4f, 0xbd, 0x91, 0x48, 0x78, 0x2b, 0x71, + 0xac, 0x51, 0xc5, 0x86, 0x3b, 0xb3, 0xdd, 0xfd, 0x03, 0xc0, 0x44, 0xf3, 0xa1, 0xaf, 0x0e, 0xe8, + 0xff, 0x40, 0x0e, 0x9c, 0x1b, 0x5f, 0xe6, 0xa4, 0x32, 0xe6, 0x3e, 0xe7, 0x52, 0x53, 0xb2, 0x6a, + 0x7b, 0xf2, 0xdc, 0x63, 0xb8, 0x98, 0x03, 0x0b, 0x3f, 0xb5, 0x86, 0xc9, 0xc7, 0xbb, 0xec, 0x12, + 0xd1, 0xf1, 0x5d, 0x20, 0xb6, 0xd7, 0x0e, 0xd3, 0x4a, 0xd2, 0x74, 0xb5, 0x23, 0x3f, 0xca, 0xe2, + 0x49, 0xb0, 0xd7, 0x52, 0x16, 0x73, 0xca, 0x98, 0xc9, 0x99, 0x22, 0x4a, 0x98, 0xe5, 0xc1, 0xa6, + 0xd3, 0xf8, 0x01, 0x0a, 0x42, 0x94, 0xc5, 0x94, 0x67, 0xce, 0x58, 0x66, 0x34, 0xb3, 0x48, 0x99, + 0xc7, 0x11, 0xe8, 0x5a, 0x7a, 0xed, 0x4a, 0x7b, 0x3f, 0xa2, 0xe8, 0x68, 0x52, 0xd9, 0x73, 0x9f, + 0x20, 0xce, 0x0c, 0xd4, 0xc4, 0x19, 0x95, 0xaf, 0x73, 0x4e, 0xa9, 0xc8, 0x3d, 0x9f, 0x58, 0x1d, + 0xcf, 0xb6, 0x9f, 0xe1, 0x0a, 0xe0, 0xb5, 0x56, 0xc2, 0xb1, 0x73, 0x77, 0xb2, 0xb0, 0x93, 0x95, + 0x9f, 0x9f, 0xe2, 0xb4, 0xab, 0xc8, 0xbb, 0xb3, 0xc7, 0x3c, 0xac, 0x66, 0xc3, 0x07, 0xf5, 0x90, + 0x7b, 0x26, 0x1e, 0x94, 0x3c, 0xe2, 0x87, 0xea, 0x1e, 0xc6, 0x92, 0x2b, 0xcf, 0xdd, 0x2e, 0xb4, + 0xfb, 0x60, 0x6f, 0xee, 0x9a, 0x31, 0x8e, 0xa7, 0x0e, 0x90, 0x69, 0xe6, 0xa9, 0xd2, 0x1c, 0x8d, + 0x88, 0x05, 0xb6, 0xa6, 0xdf, 0x89, 0xe1, 0x18, 0x10, 0x93, 0x40, 0x17, 0x9c, 0x4e, 0xd6, 0x1b, + 0x0c, 0x62, 0x3c, 0x32, 0x07, 0xbc, 0x12, 0xd3, 0x5e, 0x2a, 0xe3, 0xbb, 0x5d, 0x8b, 0x23, 0xf9, + 0x3e, 0x67, 0x5b, 0x1d, 0xf0, 0x6a, 0x20, 0x37, 0x03, 0xe4, 0x37, 0x6c, 0x9f, 0x19, 0xd6, 0x36, + 0xd4, 0xc3, 0xcf, 0xef, 0x82, 0x4b, 0x06, 0xf5, 0xd5, 0x8e, 0x62, 0xa2, 0x3a, 0x46, 0xf5, 0xc5, + 0x6c, 0x77, 0x35, 0xb0, 0x18, 0x17, 0x2e, 0xe9, 0xfe, 0xfc, 0x20, 0x60, 0x95, 0x24, 0x93, 0x22, + 0x1e, 0xf3, 0xb8, 0x0a, 0x28, 0x0d, 0xea, 0xc5, 0x26, 0x91, 0x50, 0x66, 0x85, 0x31, 0xf2, 0x06, + 0x67, 0x68, 0x9c, 0x16, 0xbe, 0x44, 0x59, 0x84, 0x7d, 0x5e, 0xe5, 0xfb, 0x34, 0x25, 0xb1, 0xfe, + 0x49, 0x7f, 0x41, 0x3a, 0x0b, 0x54, 0x76, 0x3f, 0x22, 0xa8, 0xcb, 0xf0, 0x92, 0x8b, 0x45, 0x24, + 0x08, 0xa2, 0x5d, 0x0d, 0x4f, 0x49, 0xb2, 0x06, 0xad, 0x27, 0x6e, 0x52, 0xf1, 0xcd, 0xbc, 0x50, + 0x81, 0xbf, 0x61, 0x0b, 0x9f, 0x5c, 0xb9, 0xf1, 0xd2, 0x80, 0x01, 0x00, 0x00, }; #endif // defined(BINDATA_INCLUDE_DATA) @@ -3265,7 +4389,7 @@ // static BINDATA_CONST NvU8 kgspBinArchiveBooterLoadUcode_GA100_patch_loc_data[] = { - 0x00, 0x62, 0x00, 0x00, + 0x00, 0x83, 0x00, 0x00, }; #endif // defined(BINDATA_INCLUDE_DATA) diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/generated/g_bindata_kgspGetBinArchiveBooterLoadUcode_GA102.c nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_bindata_kgspGetBinArchiveBooterLoadUcode_GA102.c --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/generated/g_bindata_kgspGetBinArchiveBooterLoadUcode_GA102.c 2023-10-25 20:19:25.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_bindata_kgspGetBinArchiveBooterLoadUcode_GA102.c 2024-03-05 22:11:15.000000000 +0000 @@ -34,1586 +34,2062 @@ // VAR NAME: booter_ucode_data_ga10x // COMPRESSION: YES // COMPLEX_STRUCT: NO -// DATA SIZE (bytes): 36864 -// COMPRESSED SIZE (bytes): 25193 +// DATA SIZE (bytes): 58880 +// COMPRESSED SIZE (bytes): 32804 // static BINDATA_CONST NvU8 kgspBinArchiveBooterLoadUcode_GA102_image_dbg_data[] = { - 0xed, 0xfd, 0x43, 0xb0, 0x30, 0x4b, 0xd7, 0x00, 0x6a, 0x6e, 0xdb, 0xb6, 0x6d, 0xdb, 0xb6, 0x6d, - 0xdb, 0xf6, 0xbb, 0x6d, 0xdb, 0xb6, 0x6d, 0xdb, 0xb6, 0x6d, 0xdb, 0xbb, 0xff, 0xf1, 0x37, 0xe9, - 0x8e, 0xe8, 0xc1, 0x1d, 0xdc, 0xf3, 0xcc, 0x72, 0x54, 0x51, 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0xaf, 0x5f, 0xbf, 0x7e, 0xfd, 0xfa, + 0xf5, 0xeb, 0xd7, 0xaf, 0x5f, 0xbf, 0x7e, 0xfd, 0xfa, 0xf5, 0xeb, 0xd7, 0xaf, 0x5f, 0xbf, 0x7e, + 0xfd, 0xfa, 0xf5, 0xeb, 0xd7, 0xaf, 0x5f, 0xbf, 0x7e, 0xfd, 0xfa, 0xf5, 0xeb, 0xd7, 0xaf, 0x5f, + 0xbf, 0x7e, 0xfd, 0xfa, 0xf5, 0xeb, 0xd7, 0xaf, 0x5f, 0xbf, 0x7e, 0xfd, 0xfa, 0xf5, 0xeb, 0xd7, + 0xaf, 0x5f, 0xbf, 0x7e, 0xfd, 0xfa, 0xf5, 0xeb, 0xd7, 0xaf, 0x5f, 0xbf, 0x7e, 0xfd, 0xfa, 0xf5, + 0xeb, 0xd7, 0xaf, 0x5f, 0xbf, 0x7e, 0xfd, 0xfa, 0x7f, 0xe5, 0xff, 0x00, 0x98, 0x47, 0xd3, 0x3e, + 0x00, 0xe6, 0x00, 0x00, }; #endif // defined(BINDATA_INCLUDE_DATA) @@ -1623,8 +2099,8 @@ #if defined(BINDATA_INCLUDE_STORAGE_PVT_DEFN) { - 36864, // uncompressed data size (bytes) - 25193, // compressed data size (bytes) + 58880, // uncompressed data size (bytes) + 32804, // compressed data size (bytes) kgspBinArchiveBooterLoadUcode_GA102_image_dbg_data, // compressed data pointer NV_TRUE, // is pData compressed? NV_TRUE, // contain information for file overriding? @@ -1646,8 +2122,8 @@ // static BINDATA_CONST NvU8 kgspBinArchiveBooterLoadUcode_GA102_header_dbg_data[] = { - 0x63, 0x60, 0x00, 0x02, 0x46, 0x20, 0x4e, 0x01, 0x62, 0x6d, 0x08, 0x13, 0x4c, 0x24, 0x43, 0x69, - 0x20, 0x00, 0x00, 0x5e, 0xa1, 0x3e, 0xdc, 0x24, 0x00, 0x00, 0x00, + 0x63, 0x60, 0x00, 0x02, 0x46, 0x20, 0x6e, 0x01, 0xe2, 0x24, 0x08, 0x13, 0x4c, 0x34, 0x43, 0x69, + 0x20, 0x00, 0x00, 0xef, 0x1f, 0x77, 0xe5, 0x24, 0x00, 0x00, 0x00, }; #endif // defined(BINDATA_INCLUDE_DATA) @@ -1675,1586 +2151,2062 @@ // VAR NAME: booter_ucode_data_ga10x // COMPRESSION: YES // COMPLEX_STRUCT: NO -// DATA SIZE (bytes): 36864 -// COMPRESSED SIZE (bytes): 25188 +// DATA SIZE (bytes): 58880 +// COMPRESSED SIZE (bytes): 32802 // static BINDATA_CONST NvU8 kgspBinArchiveBooterLoadUcode_GA102_image_prod_data[] = { - 0xed, 0xfd, 0x33, 0xb0, 0x30, 0xcc, 0x16, 0x30, 0xe8, 0x6e, 0xdb, 0xb6, 0x6d, 0xdb, 0xb6, 0x6d, - 0xdb, 0xb6, 0x6d, 0xdb, 0xb6, 0x6d, 0xdb, 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0x9f, 0x7f, 0xfe, 0xf9, + 0xe7, 0x9f, 0x7f, 0xfe, 0xf9, 0xe7, 0x9f, 0x7f, 0xfe, 0xf9, 0xe7, 0x9f, 0x7f, 0xfe, 0xf9, 0xe7, + 0x9f, 0x7f, 0xfe, 0xf9, 0xe7, 0x9f, 0x7f, 0xfe, 0xf9, 0xe7, 0x9f, 0x7f, 0xfe, 0xf9, 0xe7, 0x9f, + 0x7f, 0xfe, 0xf9, 0xe7, 0x9f, 0x7f, 0xfe, 0xf9, 0xe7, 0x9f, 0x7f, 0xfe, 0xf9, 0xe7, 0x9f, 0x7f, + 0xfe, 0xf9, 0xe7, 0x9f, 0x7f, 0xfe, 0xf9, 0xe7, 0x9f, 0x7f, 0xfe, 0xf9, 0xe7, 0x9f, 0x7f, 0xfe, + 0xf9, 0xe7, 0x9f, 0x7f, 0xfe, 0xf9, 0xe7, 0x9f, 0x7f, 0xfe, 0xf9, 0xe7, 0x9f, 0x7f, 0xfe, 0xf9, + 0xe7, 0x9f, 0x7f, 0xfe, 0xf9, 0xe7, 0xff, 0x95, 0xff, 0x03, 0xb1, 0x6f, 0xa6, 0x8e, 0x00, 0xe6, + 0x00, 0x00, }; #endif // defined(BINDATA_INCLUDE_DATA) @@ -3264,8 +4216,8 @@ #if defined(BINDATA_INCLUDE_STORAGE_PVT_DEFN) { - 36864, // uncompressed data size (bytes) - 25188, // compressed data size (bytes) + 58880, // uncompressed data size (bytes) + 32802, // compressed data size (bytes) kgspBinArchiveBooterLoadUcode_GA102_image_prod_data, // compressed data pointer NV_TRUE, // is pData compressed? NV_TRUE, // contain information for file overriding? @@ -3287,8 +4239,8 @@ // static BINDATA_CONST NvU8 kgspBinArchiveBooterLoadUcode_GA102_header_prod_data[] = { - 0x63, 0x60, 0x00, 0x02, 0x46, 0x20, 0x4e, 0x01, 0x62, 0x6d, 0x08, 0x13, 0x4c, 0x24, 0x43, 0x69, - 0x20, 0x00, 0x00, 0x5e, 0xa1, 0x3e, 0xdc, 0x24, 0x00, 0x00, 0x00, + 0x63, 0x60, 0x00, 0x02, 0x46, 0x20, 0x6e, 0x01, 0xe2, 0x24, 0x08, 0x13, 0x4c, 0x34, 0x43, 0x69, + 0x20, 0x00, 0x00, 0xef, 0x1f, 0x77, 0xe5, 0x24, 0x00, 0x00, 0x00, }; #endif // defined(BINDATA_INCLUDE_DATA) @@ -3321,55 +4273,55 @@ // static BINDATA_CONST NvU8 kgspBinArchiveBooterLoadUcode_GA102_sig_dbg_data[] = { - 0x01, 0x00, 0x03, 0xff, 0xfc, 0x52, 0xe7, 0x80, 0x9b, 0x63, 0x0f, 0x4d, 0xf8, 0x07, 0x6a, 0x53, - 0x35, 0x16, 0xc8, 0x42, 0x3e, 0xd3, 0x9c, 0xca, 0xb5, 0xe2, 0x18, 0xc6, 0x1e, 0x1a, 0x66, 0xb8, - 0x76, 0x04, 0xa0, 0x2e, 0x6a, 0x38, 0xd3, 0x14, 0x3e, 0x08, 0xc5, 0x63, 0x97, 0xde, 0x42, 0x0e, - 0x53, 0xc3, 0x19, 0x95, 0x2a, 0x13, 0x80, 0xf0, 0x52, 0xda, 0x31, 0xd1, 0xb8, 0xe7, 0xb8, 0xa1, - 0xea, 0x77, 0xd8, 0xc2, 0x0a, 0x2f, 0xa6, 0xbe, 0x22, 0x92, 0x89, 0xe7, 0x49, 0xd5, 0xf9, 0xb8, - 0x16, 0xd8, 0xa8, 0xdc, 0x99, 0x8c, 0xa6, 0x65, 0xb2, 0x62, 0x04, 0x1e, 0xf2, 0x91, 0x8b, 0x42, - 0x40, 0x92, 0xaa, 0xc5, 0x4a, 0x33, 0xf8, 0xc4, 0xad, 0x66, 0x5d, 0x8d, 0x94, 0xd7, 0x55, 0x81, - 0xbb, 0x48, 0xa3, 0x9a, 0x39, 0x1a, 0xc6, 0xa3, 0x5f, 0xb7, 0x6a, 0x56, 0x4a, 0x84, 0x8c, 0x0b, - 0x01, 0x9f, 0x14, 0xbc, 0x32, 0x13, 0x82, 0xa8, 0x47, 0xa8, 0x34, 0xde, 0xa3, 0x32, 0xeb, 0xb9, - 0x3a, 0xc0, 0x16, 0xe7, 0xd3, 0x17, 0xb8, 0xeb, 0x1d, 0x8a, 0x53, 0x62, 0x97, 0x46, 0x10, 0xba, - 0x35, 0x9d, 0x92, 0xdc, 0xa7, 0xfe, 0xf7, 0x16, 0x26, 0x3a, 0x4d, 0x24, 0x03, 0x57, 0x99, 0x0e, - 0x14, 0x3e, 0xd7, 0x48, 0x1a, 0xdc, 0x80, 0xe0, 0x26, 0xe0, 0x2f, 0x87, 0xd4, 0x13, 0xe3, 0x14, - 0xd6, 0x3c, 0xeb, 0x59, 0x90, 0xcd, 0x1c, 0x31, 0xcc, 0x60, 0x38, 0x13, 0x43, 0x76, 0xe5, 0xe1, - 0xc4, 0xb6, 0xbb, 0xe3, 0x7b, 0x06, 0xde, 0x6d, 0xf0, 0xbb, 0xde, 0xaa, 0x30, 0x17, 0x8b, 0x3c, - 0x94, 0x95, 0x8e, 0xac, 0xb2, 0x41, 0x29, 0x84, 0xe6, 0xee, 0x9f, 0x5e, 0xdf, 0x73, 0xc8, 0xce, - 0xca, 0xb9, 0x1f, 0x2b, 0xf7, 0x2d, 0xf1, 0x8d, 0xfe, 0xeb, 0x51, 0x6e, 0xe2, 0xda, 0x4e, 0xba, - 0xb0, 0x37, 0x8f, 0xf1, 0x71, 0x38, 0x97, 0xb3, 0x23, 0x65, 0xfd, 0xf5, 0xf9, 0xb5, 0xb5, 0xd0, - 0xf0, 0x85, 0x1c, 0x94, 0x97, 0xbe, 0x2c, 0xd4, 0x05, 0xee, 0xcf, 0xc8, 0xa6, 0xaf, 0xcc, 0x77, - 0xac, 0x5e, 0x01, 0x4f, 0x10, 0xd1, 0x21, 0x53, 0x15, 0xa3, 0x76, 0x82, 0x31, 0x69, 0x63, 0x95, - 0x7c, 0x8d, 0xf6, 0x7e, 0x9b, 0x9e, 0x15, 0xfd, 0xb7, 0x3c, 0xc9, 0xb5, 0xc1, 0xaa, 0xfe, 0x27, - 0xb7, 0x4f, 0xf9, 0xf2, 0x08, 0x36, 0x0b, 0x14, 0x62, 0x8f, 0xe0, 0x47, 0xb9, 0xf0, 0x80, 0x79, - 0x54, 0x10, 0x09, 0x5e, 0x9f, 0xd1, 0x46, 0x32, 0xca, 0xe5, 0x6e, 0x4d, 0xf8, 0x92, 0x0b, 0xd9, - 0x4d, 0xe2, 0x71, 0xac, 0xd6, 0x63, 0x34, 0x69, 0x57, 0x93, 0xf5, 0xfd, 0x6a, 0x98, 0xe5, 0xb4, - 0xa2, 0xee, 0xa7, 0xd1, 0x86, 0x69, 0x0c, 0x9c, 0xc6, 0xd7, 0x04, 0x82, 0x3a, 0x9f, 0x41, 0x0c, - 0xaf, 0x1d, 0xa8, 0x7c, 0x07, 0x60, 0x2f, 0x80, 0x40, 0xc2, 0x6b, 0xc6, 0x33, 0x35, 0x6f, 0xa5, - 0x94, 0xdd, 0xd8, 0xae, 0x58, 0x98, 0xaa, 0x53, 0x29, 0xe3, 0x1e, 0x37, 0x52, 0xc5, 0x63, 0x1d, - 0xe3, 0x81, 0x5b, 0x80, 0x0c, 0x45, 0x27, 0x85, 0x9f, 0xb3, 0x87, 0x62, 0xb9, 0x7b, 0xc7, 0x40, - 0xe2, 0x45, 0xf0, 0xc2, 0xaf, 0x3f, 0x19, 0x6b, 0xf0, 0x31, 0xf3, 0x24, 0x5e, 0xab, 0x6f, 0x8f, - 0xea, 0x9b, 0x61, 0x89, 0xba, 0x2f, 0x51, 0xad, 0x89, 0xc7, 0x1b, 0x3e, 0x6a, 0x87, 0xb4, 0xd8, - 0x70, 0x09, 0x34, 0xc6, 0x6c, 0xb4, 0x95, 0x27, 0x81, 0xa3, 0xd3, 0xd3, 0xcf, 0x6a, 0xc7, 0x1f, - 0xa3, 0xd8, 0xc7, 0x6c, 0x18, 0xe5, 0x65, 0xfa, 0x0d, 0x43, 0xcb, 0x74, 0xce, 0x59, 0x2d, 0x58, - 0xfa, 0x02, 0x99, 0xdd, 0x63, 0x1b, 0x1f, 0x48, 0x8f, 0xd8, 0x22, 0xb1, 0x6d, 0xea, 0x79, 0xa9, - 0x6a, 0xbc, 0xdd, 0xe3, 0xc5, 0x82, 0xaa, 0x92, 0x75, 0xb9, 0x0e, 0x6a, 0xf1, 0xd9, 0xbe, 0x80, - 0xae, 0xc9, 0x03, 0x13, 0x18, 0xf1, 0x13, 0xc0, 0x77, 0x01, 0xc3, 0x32, 0x17, 0xcc, 0xab, 0xcf, - 0x0d, 0xca, 0x45, 0x07, 0x47, 0xe4, 0xb8, 0xf4, 0x95, 0x9b, 0xec, 0xca, 0x6a, 0x62, 0x79, 0x64, - 0xd6, 0xdd, 0x01, 0x5a, 0x19, 0xbc, 0x86, 0xb3, 0x90, 0x88, 0x68, 0xcc, 0xdc, 0x21, 0x1c, 0xb2, - 0xd0, 0x87, 0x1e, 0x1d, 0x98, 0xaf, 0x94, 0x3b, 0xbb, 0xc5, 0x9e, 0x6e, 0xe4, 0x00, 0xf7, 0x72, - 0x63, 0x74, 0xf1, 0x45, 0xee, 0x4a, 0x9c, 0x0a, 0x8e, 0x44, 0x5a, 0x9c, 0x77, 0x92, 0x51, 0x05, - 0xf7, 0x1c, 0xb0, 0x7d, 0x8d, 0x38, 0xf6, 0x7c, 0xe7, 0x57, 0xba, 0x60, 0xf6, 0xf7, 0xec, 0x81, - 0xb2, 0x1d, 0xe7, 0x55, 0x62, 0x6a, 0xd9, 0x5b, 0x7a, 0xd5, 0x4f, 0xc8, 0x2c, 0x9d, 0x36, 0x8a, - 0xfb, 0xcc, 0x4e, 0xad, 0x32, 0xbc, 0xa7, 0x60, 0x7b, 0x4f, 0x8c, 0x57, 0xf5, 0xa2, 0x72, 0x48, - 0x9b, 0x45, 0x8f, 0xd6, 0x55, 0x0f, 0xdb, 0x7f, 0x6e, 0x1d, 0xc2, 0x20, 0x7d, 0x78, 0xd4, 0xde, - 0xff, 0x6a, 0x31, 0x75, 0xa0, 0x36, 0x39, 0xd4, 0x6f, 0xd7, 0xa5, 0x1d, 0x7d, 0xb9, 0xa2, 0x23, - 0xff, 0xb8, 0x8e, 0x75, 0x62, 0x2e, 0x8d, 0x55, 0xb1, 0xf1, 0x02, 0x66, 0x1a, 0xcd, 0xc6, 0xcf, - 0x06, 0xf0, 0xca, 0xcd, 0x76, 0x36, 0xb7, 0xbb, 0xfc, 0xe1, 0x1e, 0x42, 0x32, 0x91, 0x79, 0x9a, - 0x36, 0xa0, 0x2a, 0x69, 0xd3, 0x86, 0x7d, 0x14, 0x09, 0xb0, 0x0a, 0xba, 0x5d, 0xa9, 0x05, 0x13, - 0xb5, 0x58, 0x44, 0x0f, 0x70, 0x75, 0x8f, 0x74, 0x93, 0xb0, 0x20, 0xc7, 0xda, 0xa2, 0x6d, 0xb2, - 0x47, 0x91, 0x96, 0x64, 0xf1, 0x30, 0x07, 0x06, 0xe1, 0xdd, 0xe9, 0x50, 0xe7, 0x52, 0x4a, 0x1b, - 0x69, 0xdf, 0xf1, 0x5e, 0x66, 0x44, 0x75, 0xbd, 0xbd, 0x00, 0x03, 0x00, 0x00, + 0x01, 0x00, 0x03, 0xff, 0xfc, 0x20, 0x63, 0x89, 0xa9, 0x68, 0x99, 0x1d, 0xc9, 0x2c, 0x56, 0xcd, + 0xe3, 0x7f, 0xe1, 0x40, 0x26, 0x97, 0x42, 0xf6, 0x0d, 0x36, 0x34, 0x9b, 0xb8, 0x0d, 0x23, 0x15, + 0x9c, 0x4c, 0x9e, 0x49, 0x98, 0x32, 0xe2, 0xfc, 0x8f, 0x01, 0x07, 0xf4, 0x54, 0xad, 0x08, 0x8a, + 0x0a, 0xf0, 0x65, 0xea, 0xbd, 0x07, 0x4b, 0xbf, 0xe3, 0xfd, 0xaa, 0xfd, 0x97, 0x26, 0xc6, 0x7c, + 0x59, 0xb3, 0xef, 0x03, 0xab, 0xb5, 0x1f, 0x2d, 0x86, 0x79, 0x57, 0x22, 0xfd, 0xf0, 0xe1, 0x68, + 0x43, 0x83, 0xa4, 0x0d, 0xf8, 0xce, 0xe5, 0x43, 0x79, 0xa4, 0xaa, 0x4c, 0xad, 0xc9, 0x3b, 0xd1, + 0x39, 0xf8, 0xe7, 0x03, 0xdf, 0xaa, 0x6e, 0x2e, 0xb8, 0x77, 0x4b, 0x2d, 0x31, 0xcf, 0x59, 0x15, + 0x70, 0x66, 0x91, 0xa0, 0xeb, 0x08, 0xad, 0xcd, 0x69, 0x12, 0x7d, 0xf0, 0xdc, 0x01, 0x51, 0x47, + 0x8c, 0xdb, 0xaf, 0xf1, 0xe2, 0x85, 0x01, 0x4b, 0x96, 0x42, 0xf9, 0x48, 0xd4, 0x1d, 0x04, 0x05, + 0x7e, 0x5b, 0xc8, 0x6d, 0x1f, 0x91, 0x0c, 0x3c, 0xd3, 0xda, 0x2b, 0x75, 0x7a, 0x52, 0x30, 0x4a, + 0x19, 0xb2, 0xce, 0x2c, 0x2b, 0x2c, 0xa5, 0xfd, 0x96, 0xa1, 0xfd, 0x54, 0x86, 0xa2, 0x33, 0x22, + 0x43, 0x72, 0xec, 0x37, 0x67, 0xb2, 0x38, 0xe1, 0xfd, 0x51, 0xd3, 0x0c, 0x4e, 0x23, 0xfd, 0x2f, + 0x5d, 0xca, 0x0d, 0xc3, 0x85, 0xa5, 0x92, 0x65, 0x4a, 0xcf, 0x97, 0x71, 0x82, 0x9f, 0x3f, 0xb1, + 0x0e, 0x55, 0xfc, 0x6b, 0x11, 0xb5, 0x1f, 0xbb, 0x61, 0xba, 0x92, 0x3d, 0x08, 0x14, 0x45, 0x65, + 0xa1, 0xcc, 0xae, 0xdc, 0x18, 0xc3, 0x42, 0x06, 0xe0, 0x99, 0x93, 0x88, 0x2e, 0x28, 0x8e, 0xa6, + 0xac, 0x22, 0xee, 0x90, 0x04, 0xb6, 0xc0, 0xfb, 0x5b, 0x0c, 0xf7, 0x55, 0xca, 0x4f, 0x45, 0x6b, + 0xb1, 0xd3, 0x38, 0x49, 0xc0, 0x3a, 0xd8, 0x9b, 0xf9, 0x24, 0xc6, 0x63, 0xc5, 0x19, 0x2d, 0x17, + 0xe5, 0x23, 0x4c, 0xce, 0x6d, 0xa4, 0x40, 0xb8, 0x5e, 0x57, 0x46, 0x35, 0x00, 0x5d, 0xcd, 0x42, + 0xf4, 0xbd, 0x31, 0x74, 0x8e, 0x9e, 0xb5, 0xb8, 0x10, 0xfe, 0xbf, 0xeb, 0xc4, 0xef, 0xb4, 0xfc, + 0x49, 0x98, 0x12, 0x29, 0x97, 0xf3, 0xa4, 0x1b, 0xcf, 0xcd, 0xfd, 0xc0, 0x7c, 0x7e, 0x44, 0x4c, + 0x7b, 0x8c, 0x1c, 0xef, 0x25, 0xf6, 0x12, 0x7e, 0x6f, 0xe5, 0xb1, 0x24, 0xac, 0x83, 0x36, 0x3a, + 0x95, 0xea, 0x28, 0x99, 0x2d, 0x50, 0x94, 0xcb, 0x96, 0x31, 0xa4, 0x4f, 0x07, 0x24, 0xf0, 0xea, + 0x37, 0x55, 0x9e, 0x0f, 0x86, 0x51, 0x05, 0xd7, 0xa0, 0x17, 0x97, 0x6a, 0x42, 0x72, 0x7b, 0x69, + 0x5b, 0x21, 0xef, 0xa6, 0x2f, 0xbf, 0x34, 0x3e, 0xfa, 0xcd, 0x25, 0xb5, 0xa0, 0x68, 0x9d, 0xcb, + 0x01, 0x5e, 0x6b, 0x41, 0xb1, 0xdd, 0x99, 0x82, 0xd7, 0xe6, 0xef, 0x52, 0x12, 0xca, 0x36, 0x8b, + 0xda, 0x4d, 0x29, 0x04, 0x9c, 0xf2, 0x8e, 0xcc, 0xbe, 0x31, 0xf0, 0x73, 0x48, 0x61, 0x72, 0x4f, + 0xa7, 0xd5, 0x19, 0xd1, 0x9e, 0xf7, 0x89, 0x78, 0xed, 0x31, 0x99, 0x2c, 0xd2, 0x52, 0xf0, 0x5f, + 0x75, 0xf5, 0x29, 0xc4, 0xfd, 0x91, 0x1a, 0x01, 0xe1, 0xf4, 0x38, 0x11, 0xb0, 0x2b, 0xa7, 0x8d, + 0x67, 0x83, 0x5d, 0xbe, 0x59, 0x8d, 0xa5, 0xec, 0xf9, 0x64, 0x6b, 0xf9, 0x06, 0x36, 0x08, 0x25, + 0xbd, 0x76, 0x22, 0xf5, 0x0c, 0xda, 0xd4, 0x60, 0x7b, 0x46, 0x8c, 0xe0, 0x54, 0x31, 0x39, 0xa5, + 0x08, 0xb2, 0x26, 0xc1, 0x27, 0x0f, 0xc3, 0x46, 0x78, 0x51, 0x6e, 0x35, 0x0a, 0xae, 0xd0, 0x8d, + 0x15, 0x4b, 0x5c, 0x51, 0x47, 0x5b, 0x9c, 0xee, 0xce, 0xf9, 0x02, 0x22, 0x4d, 0x91, 0xef, 0x6c, + 0x40, 0x44, 0xc5, 0x73, 0xe0, 0x35, 0xa6, 0xbd, 0x04, 0x03, 0xa9, 0xb4, 0x18, 0x94, 0xfb, 0x55, + 0x12, 0xd2, 0xc0, 0xf6, 0x44, 0x39, 0x88, 0x59, 0x67, 0x25, 0xa2, 0x32, 0x8f, 0xe1, 0xd8, 0x1a, + 0xcc, 0x66, 0xc9, 0x35, 0x47, 0x86, 0x48, 0x69, 0x2f, 0xe7, 0x19, 0x0c, 0xbe, 0x15, 0x9c, 0x09, + 0xcd, 0x8e, 0x9b, 0xe0, 0xc7, 0x96, 0x14, 0x6a, 0x8e, 0xd2, 0x28, 0x89, 0xb6, 0x7f, 0x57, 0x66, + 0x42, 0x1e, 0xe9, 0x06, 0xcf, 0x1b, 0xba, 0xde, 0xb8, 0xd6, 0xd7, 0x3f, 0x86, 0xc9, 0x85, 0x8a, + 0xf2, 0x01, 0xf1, 0xde, 0x55, 0xcd, 0x26, 0x0a, 0x96, 0x67, 0x95, 0x2a, 0x91, 0xd3, 0x8b, 0x66, + 0x42, 0x4d, 0xc6, 0xf8, 0x69, 0xf4, 0x26, 0x51, 0x10, 0x82, 0xb6, 0x46, 0x1f, 0xb7, 0x39, 0xca, + 0xce, 0x91, 0x52, 0x8b, 0x25, 0xc4, 0x27, 0x97, 0xb2, 0x7c, 0x75, 0xc0, 0x7d, 0x7f, 0x08, 0x58, + 0xe8, 0xe8, 0x5b, 0x53, 0x4d, 0xd1, 0x83, 0xdc, 0x9e, 0x40, 0x6b, 0x89, 0x32, 0xaa, 0x17, 0xcd, + 0x29, 0x3d, 0x28, 0x72, 0xe7, 0x0f, 0xfe, 0xf2, 0xfd, 0x1c, 0xc0, 0xbd, 0x11, 0x61, 0xec, 0x03, + 0xa2, 0xdb, 0x59, 0x5b, 0xc2, 0x4b, 0x2d, 0x58, 0x4c, 0xb7, 0x8a, 0xcd, 0x97, 0x64, 0xc9, 0xa9, + 0xe7, 0x1d, 0xe6, 0x13, 0x06, 0x5d, 0xeb, 0x3a, 0x0d, 0xa3, 0x6b, 0x7f, 0x1e, 0xb0, 0x10, 0x4f, + 0xfe, 0x46, 0xd5, 0x12, 0xad, 0xba, 0x79, 0x6a, 0x43, 0x8f, 0xa8, 0x0f, 0x8b, 0x84, 0x6a, 0x28, + 0xc4, 0x82, 0xbf, 0x5d, 0xf6, 0x3d, 0x95, 0x06, 0x66, 0x3a, 0x60, 0x7b, 0x6c, 0x7b, 0xec, 0xe7, + 0xfd, 0x76, 0xf0, 0x67, 0xa0, 0x44, 0x78, 0xf5, 0x02, 0x73, 0x20, 0x10, 0x06, 0x2e, 0x0b, 0xdc, + 0xc3, 0x0a, 0x2d, 0xb2, 0x04, 0xef, 0x02, 0xd4, 0xef, 0x95, 0xdb, 0x3e, 0x99, 0xff, 0xf1, 0x0d, + 0xaa, 0x33, 0x38, 0xf5, 0x51, 0x8d, 0x09, 0x0a, 0xc3, 0x00, 0x03, 0x00, 0x00, }; #endif // defined(BINDATA_INCLUDE_DATA) @@ -3398,37 +4350,37 @@ // COMPRESSION: YES // COMPLEX_STRUCT: NO // DATA SIZE (bytes): 768 -// COMPRESSED SIZE (bytes): 419 +// COMPRESSED SIZE (bytes): 421 // static BINDATA_CONST NvU8 kgspBinArchiveBooterLoadUcode_GA102_sig_prod_data[] = { - 0xfb, 0xa7, 0x7c, 0xf3, 0xdb, 0xf4, 0xff, 0xcc, 0x0b, 0x6f, 0x7d, 0x9b, 0x6d, 0xcd, 0xb5, 0x6e, - 0x5b, 0xfe, 0xe5, 0xc0, 0xff, 0xd7, 0xea, 0xc2, 0xb7, 0x76, 0x88, 0x6d, 0xae, 0xcc, 0xda, 0xbe, - 0x77, 0xe9, 0xcb, 0xe5, 0xdf, 0x02, 0x05, 0xf7, 0xff, 0x9f, 0x11, 0x24, 0x19, 0x5a, 0xe5, 0xd8, - 0x37, 0x57, 0xc4, 0x53, 0xe9, 0xe2, 0x83, 0x44, 0xd1, 0x15, 0x8f, 0x0e, 0xeb, 0x4b, 0xbc, 0x28, - 0xde, 0xd1, 0x7f, 0x75, 0xab, 0x48, 0xae, 0x47, 0xc9, 0x2e, 0x01, 0x19, 0xaf, 0xd7, 0xf9, 0x47, - 0x14, 0x5e, 0x73, 0x9e, 0x59, 0xb6, 0xf9, 0xe2, 0xfc, 0x9f, 0x2e, 0x1a, 0x85, 0x6c, 0x6a, 0xdb, - 0xc4, 0xa7, 0x1b, 0xcf, 0xde, 0xfc, 0x6c, 0xde, 0x51, 0x2b, 0xfd, 0xe6, 0xc6, 0x92, 0xdf, 0xde, - 0x9e, 0xe9, 0x29, 0xba, 0x2c, 0x45, 0xd7, 0xbd, 0x5a, 0x8f, 0x5b, 0x3d, 0xf1, 0xb7, 0x34, 0x59, - 0x57, 0x2f, 0xd6, 0x74, 0xdf, 0x53, 0x52, 0x7c, 0xe1, 0x1c, 0xa6, 0xbb, 0x2c, 0xf9, 0xb9, 0x97, - 0x4f, 0xc4, 0xa6, 0x17, 0xcf, 0xca, 0xf9, 0x68, 0x9d, 0xeb, 0x37, 0xf1, 0xb0, 0xcf, 0xd5, 0x24, - 0xa9, 0xe2, 0x5b, 0xbc, 0x65, 0x57, 0x5f, 0xc6, 0x7d, 0xd8, 0x76, 0x6a, 0x33, 0xb7, 0x6a, 0xeb, - 0x8d, 0x14, 0xcf, 0xf4, 0x32, 0x5b, 0x81, 0xf0, 0xb8, 0xcc, 0xdc, 0xe3, 0x45, 0xd9, 0x4b, 0x6f, - 0xce, 0x9c, 0x7b, 0xcc, 0xb8, 0x68, 0x55, 0xd8, 0x1f, 0xab, 0xe3, 0x89, 0x7f, 0x83, 0xc4, 0xcd, - 0x77, 0xad, 0x72, 0x11, 0x91, 0xae, 0x0f, 0x3a, 0xac, 0x7d, 0x26, 0x61, 0xc5, 0xf7, 0xef, 0xda, - 0xfa, 0x57, 0xee, 0x99, 0xc4, 0x4e, 0x9a, 0xfa, 0x2c, 0x40, 0xad, 0xf1, 0xff, 0x64, 0x9b, 0xbd, - 0x85, 0xe6, 0xf6, 0xe6, 0x8b, 0x9e, 0x0b, 0xd4, 0xfc, 0x10, 0xe2, 0xd9, 0x5d, 0x10, 0x2b, 0x9e, - 0xb4, 0xe6, 0x94, 0xf3, 0x5c, 0x39, 0xbb, 0x6b, 0x3c, 0xc5, 0x91, 0xa5, 0xcf, 0xbf, 0xbc, 0x99, - 0x7f, 0x3a, 0xef, 0xfb, 0x71, 0x5f, 0x71, 0xe6, 0xf3, 0xd6, 0xac, 0x71, 0xbb, 0x5e, 0x5f, 0xfe, - 0xe8, 0x2f, 0xae, 0x24, 0xbb, 0xc8, 0x98, 0xbf, 0xb9, 0x40, 0x27, 0x70, 0xc5, 0x87, 0xfe, 0x63, - 0x1e, 0xa5, 0x0f, 0x3f, 0xd8, 0xec, 0xd6, 0x68, 0x4d, 0xce, 0x0d, 0x9f, 0x71, 0x85, 0x7b, 0xa2, - 0xc9, 0x05, 0x8d, 0xf6, 0xe4, 0x8b, 0x9d, 0x8d, 0xd1, 0x61, 0x42, 0x1f, 0xf5, 0xda, 0x83, 0x8f, - 0x36, 0x4c, 0xab, 0xab, 0x9b, 0xd5, 0xe0, 0xcc, 0xdb, 0x77, 0x3a, 0xe8, 0x6b, 0xb3, 0xa8, 0xe0, - 0x3b, 0x11, 0xcb, 0x3d, 0xb3, 0xd5, 0x1f, 0xf8, 0xcd, 0xf5, 0xf8, 0x1c, 0xc0, 0x76, 0xec, 0xca, - 0xcf, 0xbd, 0x6f, 0xaf, 0x64, 0xfd, 0x5c, 0xf9, 0xd7, 0xd1, 0x3c, 0xa3, 0xd4, 0x33, 0x39, 0x44, - 0x61, 0xfd, 0x15, 0xad, 0x1b, 0xca, 0x27, 0xeb, 0x82, 0x43, 0x2d, 0x2c, 0x9a, 0x32, 0x2e, 0xaf, - 0x76, 0xd0, 0x29, 0xd8, 0xce, 0x30, 0x0a, 0x06, 0x14, 0x00, 0x00, 0xaa, 0xd8, 0x3f, 0xfe, 0x00, - 0x03, 0x00, 0x00, + 0x5b, 0x25, 0xa4, 0xae, 0xba, 0xac, 0x71, 0x5e, 0xc4, 0x86, 0x83, 0xfd, 0xdb, 0x67, 0x74, 0x9e, + 0xe0, 0xda, 0x2b, 0x7e, 0xf9, 0xca, 0x82, 0xdf, 0x6b, 0x1f, 0x68, 0x78, 0x5d, 0xf4, 0x3d, 0x1b, + 0xec, 0x6f, 0xeb, 0xed, 0x16, 0x54, 0x77, 0x30, 0xda, 0x6a, 0x7d, 0x44, 0xf6, 0xca, 0xe7, 0x4b, + 0x67, 0xe8, 0xe6, 0xd9, 0xdd, 0x88, 0xfd, 0x1c, 0x1a, 0x10, 0x7b, 0xda, 0xb1, 0xf9, 0x92, 0x8d, + 0xa4, 0x5e, 0xdf, 0x86, 0xff, 0xaa, 0x72, 0xf3, 0xf8, 0x3d, 0x72, 0x03, 0x56, 0x67, 0x64, 0x65, + 0x4c, 0xfe, 0x6a, 0x3f, 0xbd, 0xe4, 0x6b, 0x64, 0xeb, 0xf5, 0x3b, 0xef, 0xfc, 0xa7, 0x9c, 0x3f, + 0xce, 0xdd, 0x34, 0xed, 0xee, 0xa9, 0xf9, 0x27, 0xaf, 0x3d, 0x5e, 0x10, 0xae, 0x50, 0x57, 0xf6, + 0xef, 0xe8, 0xdf, 0xed, 0x75, 0x4e, 0x0f, 0x57, 0xad, 0x58, 0x14, 0xbf, 0x6c, 0xf9, 0x54, 0xbd, + 0x27, 0x37, 0x0e, 0xbd, 0x9a, 0x29, 0x91, 0x58, 0xa2, 0x37, 0x61, 0xea, 0xee, 0x53, 0xeb, 0xb7, + 0x5c, 0x29, 0x6d, 0xf4, 0x2f, 0x14, 0xef, 0xf7, 0xdd, 0x7d, 0x78, 0x09, 0xa7, 0xc6, 0x89, 0x1d, + 0x2e, 0x27, 0x83, 0x15, 0x8a, 0x17, 0x58, 0xae, 0x9a, 0xf7, 0xe7, 0xf7, 0x9b, 0xf0, 0x76, 0xb1, + 0xb5, 0xdb, 0x97, 0xfc, 0xb0, 0xe3, 0x6d, 0xba, 0x28, 0xe3, 0xdd, 0x94, 0xd1, 0xf5, 0x67, 0x4b, + 0x88, 0x78, 0x85, 0xf0, 0x64, 0x03, 0xe3, 0x9f, 0x9c, 0xc7, 0xf3, 0xae, 0xac, 0xfd, 0xb5, 0xee, + 0xf7, 0xec, 0xd2, 0x75, 0x65, 0x1e, 0xce, 0xdf, 0xff, 0xb4, 0x9f, 0xbf, 0x59, 0xc9, 0x25, 0x76, + 0xe0, 0x89, 0xb9, 0x7c, 0xe1, 0x5d, 0xe7, 0xdb, 0xe1, 0x6d, 0x09, 0x1e, 0x2b, 0xae, 0x55, 0xb9, + 0x99, 0x4e, 0x35, 0x4e, 0xee, 0xd8, 0xb7, 0x22, 0x97, 0xd3, 0xf2, 0x57, 0x87, 0x4a, 0x5f, 0x68, + 0xc2, 0x97, 0x0b, 0xea, 0xcf, 0xd7, 0x85, 0x9f, 0x99, 0xf3, 0xac, 0xc1, 0xe1, 0x77, 0xab, 0xed, + 0xad, 0xac, 0xac, 0x29, 0xb9, 0x12, 0x45, 0x97, 0x2b, 0x9f, 0x19, 0x6d, 0xff, 0xe2, 0x2f, 0x73, + 0xb7, 0x65, 0xfe, 0xaf, 0x17, 0x3d, 0x2e, 0x07, 0xcd, 0x16, 0xe8, 0x06, 0x48, 0xdf, 0x5e, 0xa5, + 0xea, 0xf7, 0x76, 0x97, 0x7f, 0xa5, 0xf6, 0xae, 0x0d, 0xaa, 0xa9, 0x7a, 0xc5, 0x7d, 0xdf, 0x13, + 0x0c, 0xe2, 0x2f, 0x4e, 0x12, 0xbf, 0xfa, 0x31, 0xb3, 0x54, 0x2f, 0xec, 0x5b, 0xe6, 0xd4, 0x85, + 0x3a, 0xef, 0x2f, 0x99, 0xb7, 0xac, 0xcf, 0x2b, 0x99, 0xf0, 0x6b, 0xc9, 0x07, 0x9f, 0x64, 0x79, + 0xd1, 0x69, 0xab, 0xc3, 0x8f, 0x14, 0x73, 0xf8, 0x99, 0x94, 0x5a, 0x47, 0x5d, 0x9e, 0x16, 0xb4, + 0x70, 0xb7, 0x39, 0xcb, 0x91, 0x03, 0xcc, 0xa2, 0xff, 0x6a, 0x5e, 0x7c, 0xee, 0x4b, 0x9d, 0xa2, + 0xfc, 0xaa, 0xe7, 0xc1, 0xea, 0x6d, 0x0b, 0x2a, 0xfa, 0x35, 0x94, 0xb7, 0xca, 0x9a, 0xde, 0xbe, + 0x27, 0x18, 0x3a, 0x31, 0x49, 0x87, 0x95, 0x61, 0x14, 0x0c, 0x28, 0x00, 0x00, 0x28, 0xef, 0x46, + 0x84, 0x00, 0x03, 0x00, 0x00, }; #endif // defined(BINDATA_INCLUDE_DATA) @@ -3439,7 +4391,7 @@ #if defined(BINDATA_INCLUDE_STORAGE_PVT_DEFN) { 768, // uncompressed data size (bytes) - 419, // compressed data size (bytes) + 421, // compressed data size (bytes) kgspBinArchiveBooterLoadUcode_GA102_sig_prod_data, // compressed data pointer NV_TRUE, // is pData compressed? NV_TRUE, // contain information for file overriding? @@ -3461,7 +4413,7 @@ // static BINDATA_CONST NvU8 kgspBinArchiveBooterLoadUcode_GA102_patch_loc_data[] = { - 0x10, 0x64, 0x00, 0x00, + 0x10, 0x84, 0x00, 0x00, }; #endif // defined(BINDATA_INCLUDE_DATA) diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/generated/g_bindata_kgspGetBinArchiveBooterLoadUcode_TU102.c nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_bindata_kgspGetBinArchiveBooterLoadUcode_TU102.c --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/generated/g_bindata_kgspGetBinArchiveBooterLoadUcode_TU102.c 2023-10-25 20:19:25.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_bindata_kgspGetBinArchiveBooterLoadUcode_TU102.c 2024-03-05 22:11:15.000000000 +0000 @@ -34,1526 +34,2046 @@ // VAR NAME: booter_ucode_data_tu10x // COMPRESSION: YES // COMPLEX_STRUCT: NO -// DATA SIZE (bytes): 35584 -// COMPRESSED SIZE (bytes): 24227 +// DATA SIZE (bytes): 57856 +// COMPRESSED SIZE (bytes): 32546 // static BINDATA_CONST NvU8 kgspBinArchiveBooterLoadUcode_TU102_image_dbg_data[] = { - 0xed, 0xdc, 0x53, 0x93, 0x28, 0x4d, 0x17, 0x28, 0xe8, 0xb6, 0x6d, 0xdb, 0xb6, 0xcd, 0xdd, 0xb6, - 0x6d, 0x6b, 0xb7, 0x6d, 0xdb, 0xb6, 0x6d, 0xdb, 0xb6, 0x6d, 0xdb, 0xee, 0x3e, 0xdf, 0x99, 0xbb, - 0x79, 0xe7, 0x17, 0x4c, 0xc4, 0x7e, 0x6e, 0x32, 0xb3, 0x22, 0xaa, 0x56, 0xde, 0x54, 0x46, 0xad, - 0x8a, 0x58, 0x4b, 0x02, 0x00, 0x61, 0x26, 0x1d, 0x20, 0x16, 0x00, 0x14, 0xa0, 0xfb, 0x28, 0xef, - 0xbd, 0xf9, 0x07, 0x50, 0x02, 0x00, 0xf1, 0xff, 0x5e, 0x80, 0x00, 0x05, 0xf8, 0x7f, 0x96, 0xe1, - 0x00, 0x00, 0x80, 0x3f, 0x49, 0x00, 0x3e, 0xf4, 0x00, 0x00, 0x6f, 0x40, 0x6f, 0x00, 0xef, 0x40, - 0xd1, 0x00, 0x40, 0x00, 0xbd, 0x3b, 0xbb, 0xbf, 0xbf, 0xbf, 0xf0, 0xe1, 0x00, 0x80, 0x00, 0xbf, - 0xb9, 0x20, 0x8d, 0x47, 0x00, 0xcc, 0x69, 0xeb, 0x80, 0x8d, 0x49, 0x00, 0x34, 0x69, 0xeb, 0x40, - 0xff, 0x1b, 0x48, 0xd3, 0xd6, 0x81, 0xff, 0x37, 0xe0, 0xfd, 0xef, 0x5e, 0x80, 0xb4, 0x5c, 0xe0, - 0xe6, 0x5d, 0xe0, 0xde, 0xdc, 0xbc, 0xdd, 0xb4, 0x5c, 0xc0, 0xb4, 0x74, 0xa0, 0xe6, 0x5d, 0xc0, - 0xe6, 0x75, 0x20, 0x9f, 0x15, 0x00, 0x00, 0x78, 0x46, 0x09, 0x00, 0x84, 0xd7, 0x5c, 0x00, 0xf8, - 0xff, 0xc5, 0x30, 0x03, 0xf9, 0xbf, 0x13, 0xd8, 0xb6, 0x74, 0x00, 0x40, 0xa0, 0xff, 0xcd, 0x9e, - 0x78, 0x80, 0x62, 0x01, 0x00, 0xc0, 0xc2, 0xff, 0x17, 0xea, 0x3b, 0x17, 0xb4, 0xfb, 0xe9, 0xe3, - 0x1d, 0xec, 0x0d, 0xf8, 0x7f, 0x4f, 0x03, 0x4a, 0x86, 0x87, 0xd8, 0xf9, 0xbf, 0x91, 0xbf, 0xdf, - 0x41, 0xc3, 0x01, 0xf4, 0x00, 0xbe, 0x73, 0x40, 0x3a, 0xe3, 0x80, 0x5a, 0x92, 0x10, 0xfe, 0xb7, - 0xfe, 0xf9, 0x00, 0xf0, 0xf9, 0xdf, 0x7e, 0xde, 0x80, 0xba, 0x8b, 0x3e, 0x01, 0x63, 0xb9, 0x98, - 0xc0, 0xc2, 0x09, 0xa8, 0x01, 0xf2, 0x72, 0xdf, 0x00, 0x62, 0xff, 0x37, 0xf6, 0xfe, 0x3e, 0x31, - 0x7c, 0xfd, 0x48, 0x00, 0xe6, 0xe5, 0xf2, 0xdd, 0x01, 0xfc, 0xbf, 0x40, 0xae, 0xe9, 0x90, 0x2d, - 0x8e, 0x16, 0x97, 0x25, 0xac, 0xab, 0xb0, 0x5f, 0x93, 0x89, 0xe2, 0xe6, 0x08, 0x68, 0xb5, 0xe8, - 0x4a, 0xe8, 0x97, 0xda, 0x46, 0x9e, 0x60, 0x1f, 0x12, 0x9a, 0xe6, 0xff, 0x38, 0xab, 0xcf, 0x79, - 0x5a, 0xeb, 0xd8, 0x0f, 0xac, 0x6d, 0x6d, 0xa2, 0x52, 0xd2, 0x12, 0x6a, 0x6c, 0xe4, 0x22, 0x04, - 0xf7, 0x60, 0xd2, 0x91, 0x96, 0x5e, 0x3b, 0xaa, 0x45, 0xa2, 0x1f, 0x8a, 0xcd, 0x00, 0x22, 0x72, - 0xe8, 0x12, 0xcd, 0xb8, 0x91, 0xd5, 0xdd, 0x0d, 0x17, 0xe7, 0xd3, 0x67, 0x07, 0xa4, 0x50, 0x7d, - 0x1b, 0xf6, 0xf1, 0xc4, 0x2c, 0xd5, 0xe2, 0xf4, 0x19, 0xbd, 0xe1, 0xf9, 0xf9, 0x93, 0xdb, 0x62, - 0x2f, 0xe4, 0xe7, 0x75, 0xf3, 0x78, 0xed, 0x45, 0x6c, 0x90, 0x1c, 0xb9, 0x97, 0x41, 0x4a, 0x5b, - 0x16, 0x85, 0x4e, 0x5e, 0x1f, 0x0d, 0x30, 0x72, 0x4c, 0x9a, 0xb2, 0x9f, 0x6c, 0x41, 0xc4, 0xe5, - 0x85, 0xd7, 0x52, 0x0e, 0x88, 0x00, 0x45, 0x7c, 0x8c, 0x5c, 0xef, 0x75, 0x55, 0x27, 0xdb, 0x3d, - 0x41, 0x1a, 0x8e, 0xf4, 0x67, 0xa8, 0x26, 0x7b, 0xf7, 0x9d, 0x8e, 0xcb, 0x6e, 0xee, 0x19, 0x4a, - 0x6f, 0x8b, 0x8d, 0x61, 0xb4, 0x7d, 0x49, 0xad, 0xcd, 0x43, 0xc8, 0xbf, 0x7b, 0xad, 0x74, 0x97, - 0x37, 0x8f, 0x91, 0xfa, 0x1b, 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0x0f, 0xcf, 0xb2, + 0x18, 0xf5, 0x4e, 0x61, 0x69, 0xed, 0x4a, 0xa9, 0xa2, 0x93, 0x43, 0x18, 0xc0, 0xf8, 0x3a, 0x62, + 0x91, 0xaa, 0x7a, 0xc9, 0xa4, 0xa9, 0x52, 0x4d, 0x24, 0x67, 0x49, 0xc8, 0xdb, 0x3d, 0x14, 0x50, + 0x65, 0x58, 0xe0, 0xd8, 0xd7, 0x71, 0xca, 0x03, 0xff, 0x7f, 0xd7, 0x01, 0xfe, 0xf9, 0xe7, 0x9f, + 0x7f, 0xfe, 0xf9, 0xe7, 0x9f, 0x7f, 0xfe, 0xf9, 0xe7, 0x9f, 0x7f, 0xfe, 0xf9, 0xe7, 0x9f, 0x7f, + 0xfe, 0xf9, 0xe7, 0x9f, 0x7f, 0xfe, 0xf9, 0xe7, 0x9f, 0x7f, 0xfe, 0xf9, 0xe7, 0x9f, 0x7f, 0xfe, + 0xf9, 0xe7, 0x9f, 0x7f, 0xfe, 0xf9, 0xe7, 0x9f, 0x7f, 0xfe, 0xf9, 0xe7, 0x9f, 0x7f, 0xfe, 0xf9, + 0xe7, 0x9f, 0x7f, 0xfe, 0xf9, 0xe7, 0x9f, 0x7f, 0xfe, 0xf9, 0xe7, 0x9f, 0x7f, 0xfe, 0xf9, 0xe7, 0x9f, 0x7f, 0xfe, 0xf9, 0xe7, 0x9f, 0x7f, 0xfe, 0xf9, 0xe7, 0x9f, 0x7f, 0xfe, 0xf9, 0xe7, 0x9f, 0x7f, 0xfe, 0xf9, 0xe7, 0x9f, 0x7f, 0xfe, 0xf9, 0xe7, 0x9f, 0x7f, 0xfe, 0xf9, 0xe7, 0x9f, 0x7f, - 0xfe, 0xf9, 0xe7, 0x9f, 0x7f, 0xfe, 0xf9, 0xff, 0x8d, 0xff, 0x03, 0x51, 0x65, 0x33, 0x53, 0x00, - 0x8b, 0x00, 0x00, + 0xfe, 0xf9, 0xe7, 0x9f, 0x7f, 0xfe, 0xf9, 0xe7, 0x9f, 0x7f, 0xfe, 0xf9, 0xe7, 0x9f, 0x7f, 0xfe, + 0xf9, 0xe7, 0x9f, 0x7f, 0xfe, 0xf9, 0xff, 0xe4, 0xff, 0x02, 0x6b, 0x7d, 0x85, 0x8b, 0x00, 0xe2, + 0x00, 0x00, }; #endif // defined(BINDATA_INCLUDE_DATA) @@ -1563,8 +2083,8 @@ #if defined(BINDATA_INCLUDE_STORAGE_PVT_DEFN) { - 35584, // uncompressed data size (bytes) - 24227, // compressed data size (bytes) + 57856, // uncompressed data size (bytes) + 32546, // compressed data size (bytes) kgspBinArchiveBooterLoadUcode_TU102_image_dbg_data, // compressed data pointer NV_TRUE, // is pData compressed? NV_TRUE, // contain information for file overriding? @@ -1586,8 +2106,8 @@ // static BINDATA_CONST NvU8 kgspBinArchiveBooterLoadUcode_TU102_header_dbg_data[] = { - 0x63, 0x60, 0x00, 0x02, 0x46, 0x20, 0x8e, 0x07, 0x62, 0x1d, 0x08, 0x13, 0x4c, 0xc4, 0x41, 0x69, - 0x20, 0x00, 0x00, 0x5d, 0x39, 0xf2, 0xda, 0x24, 0x00, 0x00, 0x00, + 0x63, 0x60, 0x00, 0x02, 0x46, 0x20, 0x6e, 0x00, 0xe2, 0x24, 0x08, 0x13, 0x4c, 0xd4, 0x43, 0x69, + 0x20, 0x00, 0x00, 0x01, 0x81, 0xef, 0x07, 0x24, 0x00, 0x00, 0x00, }; #endif // defined(BINDATA_INCLUDE_DATA) @@ -1615,1526 +2135,2045 @@ // VAR NAME: booter_ucode_data_tu10x // COMPRESSION: YES // COMPLEX_STRUCT: NO -// DATA SIZE (bytes): 35584 -// COMPRESSED SIZE (bytes): 24227 +// DATA SIZE (bytes): 57856 +// COMPRESSED SIZE (bytes): 32543 // static BINDATA_CONST NvU8 kgspBinArchiveBooterLoadUcode_TU102_image_prod_data[] = { - 0xed, 0xdc, 0x53, 0xaf, 0x28, 0xcd, 0xf7, 0x00, 0xe8, 0x6d, 0xdb, 0xb6, 0x6d, 0xe3, 0x6c, 0xdb, - 0xb6, 0x6d, 0xdb, 0xb6, 0x6d, 0xdb, 0xb6, 0x6d, 0xf3, 0x6c, 0xdb, 0x36, 0xe6, 0xf7, 0x9f, 0xbb, - 0x79, 0xbf, 0xc1, 0x24, 0xe7, 0xb9, 0xa9, 0xaa, 0x4e, 0xba, 0x57, 0x5d, 0x74, 0xaf, 0x64, 0x75, - 0xb2, 0x4a, 0x02, 0x00, 0x61, 0x36, 0x03, 0x20, 0x0e, 0x00, 0x14, 0xa0, 0xe7, 0x28, 0xff, 0xbd, - 0xe5, 0x07, 0x50, 0x02, 0x00, 0xf1, 0xff, 0x2e, 0x40, 0x80, 0x02, 0xfc, 0xbf, 0xcb, 0x08, 0x00, - 0x00, 0xc0, 0x9f, 0x64, 0x00, 0x5f, 0x7a, 0x00, 0x80, 0x37, 0xa0, 0x37, 0x80, 0x77, 0xa0, 0x18, - 0x00, 0x20, 0x80, 0xbe, 0x9d, 0xdd, 0xdf, 0xdf, 0x5f, 0xf8, 0x08, 0x00, 0x40, 0x80, 0xdf, 0x3c, - 0x90, 0xa6, 0x23, 0x00, 0xe6, 0xf4, 0x0d, 0xc0, 0xa6, 0x64, 0x00, 0x9a, 0xf4, 0x0d, 0xa0, 0xff, - 0x0d, 0xa4, 0xe9, 0x1b, 0xc0, 0xff, 0x1b, 0xf0, 0xfe, 0x77, 0x2f, 0x40, 0x7a, 0x1e, 0x70, 0xcb, - 0x2e, 0x70, 0x5f, 0x5e, 0xfe, 0x6e, 0x7a, 0x1e, 0x60, 0x7a, 0x06, 0x50, 0xcb, 0x2e, 0x60, 0xcb, - 0x06, 0x90, 0xef, 0x2a, 0x00, 0x00, 0x3c, 0xa3, 0x04, 0x00, 0xc2, 0x6b, 0x1e, 0x00, 0xfc, 0xff, - 0x62, 0x98, 0x81, 0xfc, 0xdf, 0x04, 0xb6, 0x3d, 0x03, 0x00, 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0x9f, 0x7f, 0xfe, 0xf9, 0xe7, 0x9f, 0x7f, 0xfe, + 0xf9, 0xe7, 0x9f, 0xff, 0x4f, 0xfe, 0x2f, 0xe1, 0x71, 0x88, 0x8e, 0x00, 0xe2, 0x00, 0x00, }; #endif // defined(BINDATA_INCLUDE_DATA) @@ -3144,8 +4183,8 @@ #if defined(BINDATA_INCLUDE_STORAGE_PVT_DEFN) { - 35584, // uncompressed data size (bytes) - 24227, // compressed data size (bytes) + 57856, // uncompressed data size (bytes) + 32543, // compressed data size (bytes) kgspBinArchiveBooterLoadUcode_TU102_image_prod_data, // compressed data pointer NV_TRUE, // is pData compressed? NV_TRUE, // contain information for file overriding? @@ -3167,8 +4206,8 @@ // static BINDATA_CONST NvU8 kgspBinArchiveBooterLoadUcode_TU102_header_prod_data[] = { - 0x63, 0x60, 0x00, 0x02, 0x46, 0x20, 0x8e, 0x07, 0x62, 0x1d, 0x08, 0x13, 0x4c, 0xc4, 0x41, 0x69, - 0x20, 0x00, 0x00, 0x5d, 0x39, 0xf2, 0xda, 0x24, 0x00, 0x00, 0x00, + 0x63, 0x60, 0x00, 0x02, 0x46, 0x20, 0x6e, 0x00, 0xe2, 0x24, 0x08, 0x13, 0x4c, 0xd4, 0x43, 0x69, + 0x20, 0x00, 0x00, 0x01, 0x81, 0xef, 0x07, 0x24, 0x00, 0x00, 0x00, }; #endif // defined(BINDATA_INCLUDE_DATA) @@ -3201,7 +4240,7 @@ // static BINDATA_CONST NvU8 kgspBinArchiveBooterLoadUcode_TU102_sig_dbg_data[] = { - 0xdc, 0x0b, 0xc1, 0x59, 0x91, 0xe1, 0x5d, 0xf2, 0x54, 0x06, 0x0d, 0xa3, 0x71, 0xb0, 0xc7, 0x52, + 0x35, 0xf3, 0x0d, 0xc6, 0x2e, 0xd9, 0x46, 0x85, 0x11, 0x15, 0x02, 0xf4, 0x79, 0x66, 0x8c, 0x7f, }; #endif // defined(BINDATA_INCLUDE_DATA) @@ -3234,7 +4273,7 @@ // static BINDATA_CONST NvU8 kgspBinArchiveBooterLoadUcode_TU102_sig_prod_data[] = { - 0xcc, 0x26, 0x2d, 0xb0, 0xb0, 0x5c, 0x1f, 0xb1, 0x57, 0x5e, 0x05, 0x8a, 0xa1, 0x2d, 0x2b, 0x6c, + 0x6f, 0xd9, 0x1c, 0x5f, 0x93, 0x33, 0x88, 0x10, 0x6f, 0x5d, 0xa8, 0x9b, 0xf4, 0xf6, 0x32, 0xdc, }; #endif // defined(BINDATA_INCLUDE_DATA) @@ -3267,7 +4306,7 @@ // static BINDATA_CONST NvU8 kgspBinArchiveBooterLoadUcode_TU102_patch_loc_data[] = { - 0x00, 0x61, 0x00, 0x00, + 0x00, 0x82, 0x00, 0x00, }; #endif // defined(BINDATA_INCLUDE_DATA) diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/generated/g_bindata_kgspGetBinArchiveBooterLoadUcode_TU116.c nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_bindata_kgspGetBinArchiveBooterLoadUcode_TU116.c --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/generated/g_bindata_kgspGetBinArchiveBooterLoadUcode_TU116.c 2023-10-25 20:19:25.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_bindata_kgspGetBinArchiveBooterLoadUcode_TU116.c 2024-03-05 22:11:15.000000000 +0000 @@ -34,1520 +34,2046 @@ // VAR NAME: booter_ucode_data_tu11x // COMPRESSION: YES // COMPLEX_STRUCT: NO -// DATA SIZE (bytes): 35584 -// COMPRESSED SIZE (bytes): 24132 +// DATA SIZE (bytes): 57856 +// COMPRESSED SIZE (bytes): 32550 // static BINDATA_CONST NvU8 kgspBinArchiveBooterLoadUcode_TU116_image_dbg_data[] = { - 0xed, 0xdc, 0x53, 0x90, 0xe8, 0xce, 0x1b, 0x30, 0xe8, 0xb1, 0x6d, 0xdb, 0xb6, 0x6d, 0xdb, 0xd6, - 0x19, 0xdb, 0xb6, 0x6d, 0xdb, 0x9e, 0x39, 0x63, 0xdb, 0xb6, 0x6d, 0xdb, 0xdc, 0xff, 0xb7, 0x77, - 0xfb, 0xbb, 0xd9, 0xda, 0xcb, 0xad, 0x3a, 0xcf, 0x4d, 0xa7, 0x53, 0x95, 0xbc, 0xa9, 0xa4, 0xd2, - 0xd5, 0x6f, 0xd2, 0xdd, 0x92, 0x00, 0x08, 0x33, 0x19, 0x00, 0x71, 0x00, 0xa0, 0x00, 0xdd, 0x47, - 0xf9, 0xef, 0xcd, 0x3f, 0x80, 0x92, 0x00, 0x88, 0xff, 0x67, 0x07, 0x04, 0x28, 0xc0, 0xff, 0x5d, - 0x8d, 0x00, 0x00, 0x00, 0xfc, 0x49, 0x06, 0xf0, 0xa5, 0x07, 0x00, 0x78, 0x03, 0x7a, 0x03, 0x78, - 0x07, 0x8a, 0x01, 0x00, 0x02, 0xe8, 0xdd, 0xd9, 0xfd, 0xfd, 0xfd, 0x85, 0x8f, 0x00, 0x00, 0x04, - 0xf8, 0xcd, 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0xad, 0x4f, 0xde, 0xa1, + 0x02, 0x9e, 0x75, 0x97, 0x00, 0x59, 0x45, 0xbc, 0x5f, 0xb4, 0x23, 0x97, 0x21, 0x39, 0x4b, 0x42, + 0xde, 0xea, 0xa6, 0x80, 0x2a, 0xc3, 0x02, 0xc7, 0xbe, 0x8e, 0x53, 0xee, 0xff, 0xff, 0x3b, 0x0f, + 0xf0, 0xcf, 0x3f, 0xff, 0xfc, 0xf3, 0xcf, 0x3f, 0xff, 0xfc, 0xf3, 0xcf, 0x3f, 0xff, 0xfc, 0xf3, + 0xcf, 0x3f, 0xff, 0xfc, 0xf3, 0xcf, 0x3f, 0xff, 0xfc, 0xf3, 0xcf, 0x3f, 0xff, 0xfc, 0xf3, 0xcf, + 0x3f, 0xff, 0xfc, 0xf3, 0xcf, 0x3f, 0xff, 0xfc, 0xf3, 0xcf, 0x3f, 0xff, 0xfc, 0xf3, 0xcf, 0x3f, + 0xff, 0xfc, 0xf3, 0xcf, 0x3f, 0xff, 0xfc, 0xf3, 0xcf, 0x3f, 0xff, 0xfc, 0xf3, 0xcf, 0x3f, 0xff, + 0xfc, 0xf3, 0xcf, 0x3f, 0xff, 0xfc, 0xf3, 0xcf, 0x3f, 0xff, 0xfc, 0xf3, 0xcf, 0x3f, 0xff, 0xfc, + 0xf3, 0xcf, 0x3f, 0xff, 0xfc, 0xf3, 0xcf, 0x3f, 0xff, 0xfc, 0xf3, 0xcf, 0x3f, 0xff, 0xfc, 0xf3, + 0xcf, 0x3f, 0xff, 0xfc, 0xf3, 0xcf, 0x3f, 0xff, 0xfc, 0xf3, 0xcf, 0x3f, 0xff, 0xfc, 0xf3, 0xcf, + 0x3f, 0xff, 0xfc, 0xf3, 0xcf, 0x3f, 0xff, 0xfc, 0xf3, 0xcf, 0xff, 0x27, 0xff, 0x07, 0x41, 0x24, + 0xaf, 0x62, 0x00, 0xe2, 0x00, 0x00, }; #endif // defined(BINDATA_INCLUDE_DATA) @@ -1557,8 +2083,8 @@ #if defined(BINDATA_INCLUDE_STORAGE_PVT_DEFN) { - 35584, // uncompressed data size (bytes) - 24132, // compressed data size (bytes) + 57856, // uncompressed data size (bytes) + 32550, // compressed data size (bytes) kgspBinArchiveBooterLoadUcode_TU116_image_dbg_data, // compressed data pointer NV_TRUE, // is pData compressed? NV_TRUE, // contain information for file overriding? @@ -1580,8 +2106,8 @@ // static BINDATA_CONST NvU8 kgspBinArchiveBooterLoadUcode_TU116_header_dbg_data[] = { - 0x63, 0x60, 0x00, 0x02, 0x46, 0x20, 0x8e, 0x07, 0x62, 0x1d, 0x08, 0x13, 0x4c, 0xc4, 0x41, 0x69, - 0x20, 0x00, 0x00, 0x5d, 0x39, 0xf2, 0xda, 0x24, 0x00, 0x00, 0x00, + 0x63, 0x60, 0x00, 0x02, 0x46, 0x20, 0x6e, 0x00, 0xe2, 0x24, 0x08, 0x13, 0x4c, 0xd4, 0x43, 0x69, + 0x20, 0x00, 0x00, 0x01, 0x81, 0xef, 0x07, 0x24, 0x00, 0x00, 0x00, }; #endif // defined(BINDATA_INCLUDE_DATA) @@ -1609,1520 +2135,2046 @@ // VAR NAME: booter_ucode_data_tu11x // COMPRESSION: YES // COMPLEX_STRUCT: NO -// DATA SIZE (bytes): 35584 -// COMPRESSED SIZE (bytes): 24135 +// DATA SIZE (bytes): 57856 +// COMPRESSED SIZE (bytes): 32550 // static BINDATA_CONST NvU8 kgspBinArchiveBooterLoadUcode_TU116_image_prod_data[] = { - 0xed, 0xfc, 0x53, 0x8c, 0x28, 0xcf, 0x1b, 0x38, 0x78, 0x8f, 0x6d, 0xdb, 0xf6, 0xcc, 0x19, 0xdb, - 0xb6, 0x6d, 0xdb, 0xb6, 0x6d, 0xdb, 0xb6, 0x71, 0xc6, 0xb6, 0x6d, 0xdb, 0xf6, 0xfe, 0xfe, 0xef, - 0xdd, 0xfb, 0xdd, 0x8b, 0xcd, 0x5e, 0x6e, 0x72, 0x3e, 0x37, 0xd5, 0xd5, 0x49, 0xf7, 0xd3, 0x49, - 0xa7, 0x2a, 0x55, 0xdd, 0xf5, 0x94, 0x04, 0x00, 0xc2, 0x4c, 0x06, 0x40, 0x1c, 0x00, 0x28, 0x40, - 0xf7, 0x51, 0xfe, 0x7b, 0xcb, 0x0f, 0xa0, 0x04, 0x00, 0xe2, 0xff, 0x39, 0x01, 0x01, 0x0a, 0xf0, - 0xff, 0xab, 0x46, 0x00, 0x00, 0x00, 0xfe, 0x24, 0x03, 0xf8, 0xd2, 0x03, 0x00, 0xbc, 0x01, 0xbd, - 0x01, 0xbc, 0x03, 0xc5, 0x00, 0x00, 0x01, 0xf4, 0xee, 0xec, 0xfe, 0xfe, 0xfe, 0xc2, 0x47, 0x00, - 0x00, 0x02, 0xfc, 0xe6, 0x81, 0x34, 0x1d, 0x01, 0xfc, 0x49, 0x5f, 0x07, 0x6c, 0x4a, 0x06, 0xa0, - 0x49, 0x5f, 0x07, 0xfa, 0x5f, 0x41, 0x9a, 0xbe, 0x0e, 0xfc, 0xbf, 0x02, 0xef, 0x7f, 0xd7, 0x02, - 0xa4, 0xe7, 0x01, 0xb7, 0xec, 0x02, 0xf7, 0xe6, 0xe5, 0xef, 0xa6, 0xe7, 0x01, 0xa6, 0x67, 0x00, - 0xb5, 0xec, 0x02, 0xb6, 0xac, 0x03, 0xf9, 0xae, 0x00, 0x00, 0xc0, 0x33, 0x4a, 0x00, 0x20, 0xbc, - 0xe6, 0x01, 0xc0, 0xff, 0x2f, 0x86, 0x19, 0xc8, 0xff, 0x39, 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0xfe, 0xf9, 0xe7, 0x9f, 0x7f, 0xfe, 0xf9, 0xe7, 0x9f, 0x7f, 0xfe, 0xf9, 0xe7, 0x9f, 0x7f, + 0xfe, 0xf9, 0xe7, 0x9f, 0x7f, 0xfe, 0xf9, 0xe7, 0x9f, 0x7f, 0xfe, 0xf9, 0xe7, 0x9f, 0x7f, 0xfe, + 0xf9, 0xe7, 0x9f, 0x7f, 0xfe, 0xf9, 0xe7, 0x9f, 0x7f, 0xfe, 0xf9, 0xe7, 0x9f, 0x7f, 0xfe, 0xf9, + 0xe7, 0x9f, 0x7f, 0xfe, 0xf9, 0xe7, 0x9f, 0x7f, 0xfe, 0xf9, 0xe7, 0x9f, 0x7f, 0xfe, 0xf9, 0xe7, + 0x9f, 0x7f, 0xfe, 0xf9, 0xe7, 0x9f, 0x7f, 0xfe, 0xf9, 0xe7, 0x9f, 0x7f, 0xfe, 0xf9, 0xe7, 0x9f, + 0x7f, 0xfe, 0xf9, 0xe7, 0x9f, 0x7f, 0xfe, 0xf9, 0xe7, 0x9f, 0xff, 0x4f, 0xfe, 0x0f, 0xcd, 0x85, + 0x6d, 0x82, 0x00, 0xe2, 0x00, 0x00, }; #endif // defined(BINDATA_INCLUDE_DATA) @@ -3132,8 +4184,8 @@ #if defined(BINDATA_INCLUDE_STORAGE_PVT_DEFN) { - 35584, // uncompressed data size (bytes) - 24135, // compressed data size (bytes) + 57856, // uncompressed data size (bytes) + 32550, // compressed data size (bytes) kgspBinArchiveBooterLoadUcode_TU116_image_prod_data, // compressed data pointer NV_TRUE, // is pData compressed? NV_TRUE, // contain information for file overriding? @@ -3155,8 +4207,8 @@ // static BINDATA_CONST NvU8 kgspBinArchiveBooterLoadUcode_TU116_header_prod_data[] = { - 0x63, 0x60, 0x00, 0x02, 0x46, 0x20, 0x8e, 0x07, 0x62, 0x1d, 0x08, 0x13, 0x4c, 0xc4, 0x41, 0x69, - 0x20, 0x00, 0x00, 0x5d, 0x39, 0xf2, 0xda, 0x24, 0x00, 0x00, 0x00, + 0x63, 0x60, 0x00, 0x02, 0x46, 0x20, 0x6e, 0x00, 0xe2, 0x24, 0x08, 0x13, 0x4c, 0xd4, 0x43, 0x69, + 0x20, 0x00, 0x00, 0x01, 0x81, 0xef, 0x07, 0x24, 0x00, 0x00, 0x00, }; #endif // defined(BINDATA_INCLUDE_DATA) @@ -3189,7 +4241,7 @@ // static BINDATA_CONST NvU8 kgspBinArchiveBooterLoadUcode_TU116_sig_dbg_data[] = { - 0xa0, 0x36, 0x85, 0x48, 0xdb, 0x21, 0x06, 0x83, 0x93, 0x8c, 0xb1, 0xa2, 0xe3, 0xef, 0x78, 0x7e, + 0x75, 0xab, 0xe0, 0xf9, 0x23, 0xd4, 0x29, 0xe5, 0xd5, 0xf8, 0x2f, 0xb6, 0x1f, 0x26, 0x78, 0x4e, }; #endif // defined(BINDATA_INCLUDE_DATA) @@ -3222,7 +4274,7 @@ // static BINDATA_CONST NvU8 kgspBinArchiveBooterLoadUcode_TU116_sig_prod_data[] = { - 0xec, 0x58, 0xd9, 0x1f, 0x66, 0x9d, 0xcc, 0xa0, 0x7d, 0xa7, 0xec, 0xee, 0x64, 0xab, 0xcd, 0xd9, + 0x8a, 0x45, 0xae, 0x9f, 0x1d, 0xc7, 0x75, 0xef, 0x43, 0x34, 0x5e, 0xb0, 0x34, 0xdd, 0xd2, 0x82, }; #endif // defined(BINDATA_INCLUDE_DATA) @@ -3255,7 +4307,7 @@ // static BINDATA_CONST NvU8 kgspBinArchiveBooterLoadUcode_TU116_patch_loc_data[] = { - 0x00, 0x61, 0x00, 0x00, + 0x00, 0x82, 0x00, 0x00, }; #endif // defined(BINDATA_INCLUDE_DATA) diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/generated/g_bindata_kgspGetBinArchiveBooterUnloadUcode_AD102.c nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_bindata_kgspGetBinArchiveBooterUnloadUcode_AD102.c --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/generated/g_bindata_kgspGetBinArchiveBooterUnloadUcode_AD102.c 2023-10-25 20:19:25.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_bindata_kgspGetBinArchiveBooterUnloadUcode_AD102.c 2024-03-05 22:11:15.000000000 +0000 @@ -34,450 +34,1169 @@ // VAR NAME: booter_ucode_data_ad10x // COMPRESSION: YES // COMPLEX_STRUCT: NO -// DATA SIZE (bytes): 8960 -// COMPRESSED SIZE (bytes): 7012 +// DATA SIZE (bytes): 38912 +// COMPRESSED SIZE (bytes): 18517 // static BINDATA_CONST NvU8 kgspBinArchiveBooterUnloadUcode_AD102_image_dbg_data[] = { - 0xed, 0x99, 0x65, 0x50, 0x5d, 0xdd, 0x96, 0xae, 0x91, 0x04, 0x77, 0x77, 0x87, 0x8d, 0xbb, 0xbb, - 0xbb, 0x07, 0x77, 0xdf, 0xc1, 0x09, 0x6e, 0xc1, 0xdd, 0xdd, 0x82, 0xbb, 0xbb, 0x06, 0x0b, 0x12, - 0x3c, 0xb8, 0x67, 0xe3, 0xbe, 0x71, 0x87, 0x60, 0xcd, 0xe9, 0xfe, 0x6e, 0xdd, 0xae, 0xaf, 0xee, - 0xfd, 0xd3, 0xdd, 0x55, 0xe7, 0x47, 0x9f, 0xb7, 0xea, 0x59, 0x63, 0x8c, 0xb9, 0x46, 0xd5, 0xbb, - 0xe6, 0x9c, 0x7f, 0xd6, 0x5c, 0x0b, 0x02, 0xe2, 0x7f, 0xb7, 0x04, 0xc8, 0x73, 0x46, 0x6b, 0xbf, - 0xba, 0xc4, 0x84, 0x3a, 0x44, 0x68, 0xc4, 0xc9, 0x5f, 0x74, 0x04, 0x14, 0xdd, 0x38, 0x91, 0x74, - 0xfa, 0x31, 0x9c, 0x98, 0xf5, 0xcb, 0x3c, 0x7c, 0x7b, 0xec, 0xdc, 0xef, 0x4c, 0x1d, 0x8e, 0x65, - 0x08, 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defined(BINDATA_INCLUDE_STORAGE_PVT_DEFN) { - 8960, // uncompressed data size (bytes) - 7012, // compressed data size (bytes) + 38912, // uncompressed data size (bytes) + 18517, // compressed data size (bytes) kgspBinArchiveBooterUnloadUcode_AD102_image_dbg_data, // compressed data pointer NV_TRUE, // is pData compressed? NV_TRUE, // contain information for file overriding? @@ -510,8 +1229,8 @@ // static BINDATA_CONST NvU8 kgspBinArchiveBooterUnloadUcode_AD102_header_dbg_data[] = { - 0x63, 0x60, 0x00, 0x02, 0x46, 0x20, 0x96, 0x01, 0x62, 0x76, 0x08, 0x13, 0x4c, 0x48, 0x43, 0x69, - 0x20, 0x00, 0x00, 0xa5, 0x7c, 0x63, 0x18, 0x24, 0x00, 0x00, 0x00, + 0x63, 0x60, 0x00, 0x02, 0x46, 0x20, 0xf6, 0x04, 0x62, 0x3f, 0x08, 0x13, 0x4c, 0x78, 0x40, 0x69, + 0x20, 0x00, 0x00, 0x06, 0x07, 0x25, 0x94, 0x24, 0x00, 0x00, 0x00, }; #endif // defined(BINDATA_INCLUDE_DATA) @@ -539,450 +1258,1169 @@ // VAR NAME: booter_ucode_data_ad10x // COMPRESSION: YES // COMPLEX_STRUCT: NO -// DATA SIZE (bytes): 8960 -// COMPRESSED SIZE (bytes): 7010 +// DATA SIZE (bytes): 38912 +// COMPRESSED SIZE (bytes): 18515 // static BINDATA_CONST NvU8 kgspBinArchiveBooterUnloadUcode_AD102_image_prod_data[] = { - 0xed, 0x99, 0x55, 0x70, 0x1d, 0xcb, 0x92, 0xae, 0xc5, 0x6c, 0x31, 0x33, 0x33, 0x93, 0x85, 0x16, - 0xb3, 0x96, 0xd8, 0x62, 0x66, 0x66, 0x8b, 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0x17, 0x1a, 0xc0, 0x7f, 0x1d, 0x7f, 0xd4, + 0xff, 0x90, 0x07, 0x04, 0xe2, 0x7f, 0xdd, 0x3f, 0xe5, 0x7f, 0xa8, 0xa7, 0xfe, 0x13, 0x69, 0xff, + 0x84, 0xe8, 0x3f, 0x21, 0xf6, 0x4f, 0x88, 0xff, 0x13, 0x12, 0xff, 0x79, 0x4d, 0xea, 0x3f, 0xa5, + 0xf4, 0xbf, 0xf2, 0xc8, 0xfe, 0xb7, 0x3c, 0x52, 0xff, 0xb9, 0x06, 0x00, 0xff, 0x9c, 0x62, 0x00, + 0x05, 0x61, 0xfa, 0xff, 0x8d, 0x39, 0xfc, 0x7f, 0xc9, 0xff, 0x03, 0xf4, 0x8a, 0xfa, 0xdc, 0x00, + 0x98, 0x00, 0x00, }; #endif // defined(BINDATA_INCLUDE_DATA) @@ -992,8 +2430,8 @@ #if defined(BINDATA_INCLUDE_STORAGE_PVT_DEFN) { - 8960, // uncompressed data size (bytes) - 7010, // compressed data size (bytes) + 38912, // uncompressed data size (bytes) + 18515, // compressed data size (bytes) kgspBinArchiveBooterUnloadUcode_AD102_image_prod_data, // compressed data pointer NV_TRUE, // is pData compressed? NV_TRUE, // contain information for file overriding? @@ -1015,8 +2453,8 @@ // static BINDATA_CONST NvU8 kgspBinArchiveBooterUnloadUcode_AD102_header_prod_data[] = { - 0x63, 0x60, 0x00, 0x02, 0x46, 0x20, 0x96, 0x01, 0x62, 0x76, 0x08, 0x13, 0x4c, 0x48, 0x43, 0x69, - 0x20, 0x00, 0x00, 0xa5, 0x7c, 0x63, 0x18, 0x24, 0x00, 0x00, 0x00, + 0x63, 0x60, 0x00, 0x02, 0x46, 0x20, 0xf6, 0x04, 0x62, 0x3f, 0x08, 0x13, 0x4c, 0x78, 0x40, 0x69, + 0x20, 0x00, 0x00, 0x06, 0x07, 0x25, 0x94, 0x24, 0x00, 0x00, 0x00, }; #endif // defined(BINDATA_INCLUDE_DATA) @@ -1049,55 +2487,55 @@ // static BINDATA_CONST NvU8 kgspBinArchiveBooterUnloadUcode_AD102_sig_dbg_data[] = { - 0x01, 0x00, 0x03, 0xff, 0xfc, 0x05, 0xc8, 0x8d, 0x0a, 0x2d, 0x7a, 0xb2, 0x85, 0x54, 0x06, 0xb2, - 0x6c, 0x83, 0x69, 0x50, 0x0e, 0xd3, 0xf1, 0x2a, 0xc6, 0x07, 0xfc, 0xae, 0x72, 0x6e, 0x18, 0x6c, - 0x3c, 0x00, 0x84, 0x54, 0xfb, 0xa8, 0x65, 0x12, 0xb8, 0x5e, 0xfd, 0xe9, 0x49, 0xea, 0x94, 0x46, - 0x40, 0xed, 0x54, 0x94, 0x74, 0x28, 0x78, 0x68, 0x96, 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0x3d, 0x9b, 0xb9, 0x96, 0x71, 0x28, 0x8e, 0x77, 0x80, + 0x9e, 0x77, 0x34, 0x70, 0xb0, 0xe2, 0xbf, 0xe7, 0x33, 0xd6, 0xb4, 0xdf, 0x4f, 0x1b, 0xa0, 0xed, + 0xa8, 0xf0, 0x9b, 0x60, 0x78, 0x5f, 0x6f, 0x17, 0x04, 0x00, 0x03, 0x00, 0x00, }; #endif // defined(BINDATA_INCLUDE_DATA) @@ -1130,55 +2568,55 @@ // static BINDATA_CONST NvU8 kgspBinArchiveBooterUnloadUcode_AD102_sig_prod_data[] = { - 0x01, 0x00, 0x03, 0xff, 0xfc, 0x2c, 0x46, 0x0f, 0x69, 0x91, 0xb0, 0xb3, 0x3e, 0x62, 0xfc, 0xd8, - 0x7f, 0x3b, 0x5e, 0x6c, 0xb8, 0xe2, 0x16, 0x00, 0x63, 0x7e, 0xb1, 0x99, 0xc7, 0xb7, 0x61, 0x47, - 0x04, 0x4b, 0xd6, 0x2d, 0x9d, 0x7f, 0x4f, 0x86, 0xe8, 0x83, 0x65, 0x9e, 0x62, 0x46, 0xb7, 0x0a, - 0x47, 0x1d, 0x36, 0xed, 0x40, 0x32, 0xfa, 0x35, 0xcc, 0x54, 0x96, 0x5e, 0x61, 0x5a, 0xcb, 0xb4, - 0x13, 0xc7, 0x10, 0xb5, 0xf6, 0xba, 0xf8, 0xde, 0xf5, 0xbc, 0x41, 0x52, 0x41, 0x11, 0xce, 0xb8, - 0x17, 0xcf, 0x31, 0x69, 0x12, 0x6f, 0x66, 0x33, 0x18, 0x38, 0xbb, 0xfc, 0xfd, 0xa8, 0x68, 0x12, - 0xbe, 0xae, 0x10, 0x18, 0xe1, 0x86, 0xd3, 0x92, 0x4b, 0x81, 0x68, 0x44, 0xf1, 0x0a, 0xc6, 0x90, - 0xe1, 0x12, 0x0b, 0xe8, 0x52, 0x73, 0x0d, 0x9a, 0x7d, 0x66, 0x4a, 0xf9, 0x16, 0x4f, 0x2b, 0xc3, - 0x24, 0x51, 0xd4, 0x48, 0xf8, 0x1d, 0x81, 0x30, 0xd4, 0x9b, 0xd4, 0x02, 0xad, 0x9b, 0x12, 0x9f, - 0x23, 0x8b, 0x83, 0x8f, 0x10, 0x56, 0x79, 0x74, 0x3a, 0xaa, 0xbc, 0x05, 0x6e, 0x85, 0x0e, 0xc0, - 0xe4, 0x87, 0xa3, 0xab, 0x03, 0xa3, 0x13, 0x67, 0x60, 0x68, 0xda, 0xca, 0xb9, 0xb8, 0x4c, 0xba, - 0x96, 0x86, 0xbd, 0x1b, 0x93, 0xf6, 0xe3, 0xfa, 0xc7, 0xbb, 0xde, 0x26, 0x67, 0x56, 0x95, 0x36, - 0xc1, 0x34, 0x2a, 0x9a, 0xc8, 0x42, 0x23, 0xa8, 0xbc, 0xbd, 0x8d, 0x16, 0x09, 0x95, 0xdd, 0x55, - 0x79, 0xff, 0xec, 0xae, 0x73, 0x27, 0x36, 0x77, 0x53, 0x00, 0xa7, 0xa4, 0x3f, 0x7c, 0x1c, 0xd5, - 0x9e, 0x00, 0x0d, 0x52, 0x26, 0x9e, 0x4f, 0x63, 0x49, 0xbc, 0x26, 0x8a, 0x36, 0x93, 0x31, 0xe7, - 0xcf, 0x77, 0xd0, 0xb5, 0xe8, 0x2a, 0xac, 0xd8, 0x4c, 0x76, 0xa5, 0x43, 0x2e, 0x05, 0xbc, 0x16, - 0x7b, 0x3c, 0x59, 0x0f, 0x98, 0xcb, 0xa2, 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defined(BINDATA_INCLUDE_DATA) @@ -1211,7 +2649,7 @@ // static BINDATA_CONST NvU8 kgspBinArchiveBooterUnloadUcode_AD102_patch_loc_data[] = { - 0x10, 0x1c, 0x00, 0x00, + 0x10, 0x49, 0x00, 0x00, }; #endif // defined(BINDATA_INCLUDE_DATA) diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/generated/g_bindata_kgspGetBinArchiveBooterUnloadUcode_GA100.c nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_bindata_kgspGetBinArchiveBooterUnloadUcode_GA100.c --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/generated/g_bindata_kgspGetBinArchiveBooterUnloadUcode_GA100.c 2023-10-25 20:19:26.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_bindata_kgspGetBinArchiveBooterUnloadUcode_GA100.c 2024-03-05 22:11:16.000000000 +0000 @@ -34,427 +34,1141 @@ // VAR NAME: booter_ucode_data_ga100 // COMPRESSION: YES // COMPLEX_STRUCT: NO -// DATA SIZE (bytes): 8704 -// COMPRESSED SIZE (bytes): 6655 +// DATA SIZE (bytes): 38400 +// COMPRESSED SIZE (bytes): 18066 // static BINDATA_CONST NvU8 kgspBinArchiveBooterUnloadUcode_GA100_image_dbg_data[] = { - 0xed, 0x99, 0x45, 0x50, 0x1c, 0x6a, 0xb3, 0x86, 0x87, 0x21, 0x58, 0x20, 0x38, 0x04, 0x87, 0xe0, - 0x12, 0xdc, 0xdd, 0xdd, 0x82, 0x43, 0x70, 0x77, 0x27, 0x38, 0x03, 0x83, 0xbb, 0x0e, 0x30, 0xb8, - 0xbb, 0x07, 0x0b, 0x41, 0x43, 0x70, 0x38, 0x40, 0x82, 0xeb, 0xe0, 0x04, 0x87, 0x00, 0x81, 0xc1, - 0xe6, 0xe6, 0x5f, 0xdc, 0xcd, 0xbf, 0xba, 0xeb, 0x5b, 0xe7, 0xd9, 0xbc, 0x6f, 0xf7, 0xa2, 0xab, - 0x7b, 0xd1, 0xd5, 0xf5, 0xd5, 0x17, 0x07, 0x00, 0x20, 0xbd, 0x40, 0x00, 0x20, 0x1c, 0x00, 0xe0, - 0x1e, 0x78, 0x0f, 0x80, 0x03, 0x93, 0x00, 0x40, 0x40, 0xff, 0x26, 0x0c, 0x81, 0x40, 0xe0, 0xc4, - 0x01, 0x90, 0x00, 0x88, 0xa2, 0x57, 0xad, 0x7b, 0x00, 0x5e, 0xe8, 0x0a, 0x52, 0x2b, 0x04, 0xf0, - 0x1e, 0xba, 0x02, 0xfc, 0x2b, 0x0c, 0xd0, 0x15, 0xe4, 0xbf, 0x42, 0x15, 0x07, 0x00, 0x00, 0xa0, - 0x45, 0xc8, 0xed, 0x30, 0xe4, 0xfe, 0xa2, 0x62, 0x18, 0xb4, 0x08, 0x09, 0x9a, 0x03, 0x6c, 0x87, - 0x21, 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0x55, 0xe7, 0x4c, 0x8c, 0x8f, 0xa9, 0x67, 0x3e, 0xb6, 0xf7, 0x42, 0x49, + 0x3c, 0x1f, 0x67, 0xf4, 0xb9, 0x03, 0xc3, 0x54, 0x50, 0x6b, 0x08, 0x70, 0x05, 0xf8, 0xf5, 0xeb, + 0xd7, 0xaf, 0x5f, 0xbf, 0x7e, 0xfd, 0xfa, 0xf5, 0xeb, 0xd7, 0xaf, 0x5f, 0xbf, 0x7e, 0xfd, 0xfa, + 0xf5, 0xeb, 0xd7, 0xaf, 0x5f, 0xbf, 0x7e, 0xfd, 0xfa, 0xf5, 0xeb, 0xd7, 0xaf, 0x5f, 0xbf, 0x7e, + 0xfd, 0xfa, 0xf5, 0xeb, 0xd7, 0xaf, 0x5f, 0xbf, 0x7e, 0xfd, 0xfa, 0xf5, 0xeb, 0xd7, 0xaf, 0x5f, + 0xbf, 0x7e, 0xfd, 0xfa, 0xf5, 0xeb, 0xd7, 0xaf, 0x5f, 0xbf, 0x7e, 0xfd, 0xfa, 0xf5, 0xeb, 0xd7, + 0xaf, 0x5f, 0xbf, 0x7e, 0xfd, 0xfa, 0xf5, 0xeb, 0xd7, 0xaf, 0x5f, 0xbf, 0x7e, 0xfd, 0xfa, 0xf5, + 0xeb, 0xd7, 0xaf, 0x5f, 0xbf, 0xfe, 0x5f, 0xf0, 0xff, 0x01, 0x9d, 0x80, 0x5b, 0x46, 0x00, 0x96, + 0x00, 0x00, }; #endif // defined(BINDATA_INCLUDE_DATA) @@ -464,8 +1178,8 @@ #if defined(BINDATA_INCLUDE_STORAGE_PVT_DEFN) { - 8704, // uncompressed data size (bytes) - 6655, // compressed data size (bytes) + 38400, // uncompressed data size (bytes) + 18066, // compressed data size (bytes) kgspBinArchiveBooterUnloadUcode_GA100_image_dbg_data, // compressed data pointer NV_TRUE, // is pData compressed? NV_TRUE, // contain information for file overriding? @@ -487,8 +1201,8 @@ // static BINDATA_CONST NvU8 kgspBinArchiveBooterUnloadUcode_GA100_header_dbg_data[] = { - 0x63, 0x60, 0x00, 0x02, 0x46, 0x20, 0x96, 0x02, 0x62, 0x0e, 0x08, 0x13, 0x4c, 0x48, 0x42, 0x69, - 0x20, 0x00, 0x00, 0x2b, 0x43, 0x56, 0x8a, 0x24, 0x00, 0x00, 0x00, + 0x63, 0x60, 0x00, 0x02, 0x46, 0x20, 0x76, 0x07, 0x62, 0x7f, 0x08, 0x13, 0x4c, 0xb8, 0x41, 0x69, + 0x20, 0x00, 0x00, 0x99, 0x4d, 0xfb, 0x23, 0x24, 0x00, 0x00, 0x00, }; #endif // defined(BINDATA_INCLUDE_DATA) @@ -516,427 +1230,1141 @@ // VAR NAME: booter_ucode_data_ga100 // COMPRESSION: YES // COMPLEX_STRUCT: NO -// DATA SIZE (bytes): 8704 -// COMPRESSED SIZE (bytes): 6649 +// DATA SIZE (bytes): 38400 +// COMPRESSED SIZE (bytes): 18068 // static BINDATA_CONST NvU8 kgspBinArchiveBooterUnloadUcode_GA100_image_prod_data[] = { - 0xed, 0x99, 0x45, 0x50, 0x1c, 0x8a, 0xb2, 0x86, 0x87, 0xc1, 0x06, 0xf7, 0xe0, 0x0e, 0x21, 0x68, - 0x90, 0x10, 0xdc, 0x09, 0xae, 0x41, 0x83, 0xbb, 0x4b, 0x70, 0xb7, 0xa0, 0x83, 0xbb, 0xc3, 0xe0, - 0x2e, 0x83, 0x5b, 0x70, 0xd7, 0xe0, 0xee, 0x04, 0xb7, 0x10, 0x5c, 0x06, 0xde, 0xb9, 0x8b, 0xb7, - 0xb9, 0xab, 0xb7, 0x7e, 0x75, 0xbe, 0xcd, 0xff, 0x77, 0x2f, 0xba, 0x7a, 0xd3, 0xd5, 0xd5, 0xd5, - 0x60, 0x00, 0x00, 0xee, 0x35, 0x19, 0xe0, 0x8f, 0x05, 0x00, 0x3c, 0x00, 0x1f, 0x00, 0x8f, 0xc0, - 0x18, 0x00, 0x10, 0xd0, 0xbd, 0xb9, 0xf5, 0xf6, 0xf6, 0x86, 0x05, 0x06, 0xc0, 0x01, 0xde, 0x20, - 0x08, 0x0d, 0xbf, 0x01, 0x5c, 0xe9, 0x2b, 0x70, 0x0d, 0xc9, 0x00, 0x96, 0xf4, 0x15, 0xe0, 0x3f, - 0x42, 0x9f, 0xbe, 0x02, 0xff, 0x8f, 0x50, 0x80, 0x01, 0x00, 0x40, 0x3a, 0x04, 0xbe, 0x69, 0x0b, - 0xbe, 0x1b, 0x92, 0xb7, 0x95, 0x0e, 0x81, 0x4b, 0xcf, 0x00, 0x36, 0x6d, 0xc1, 0x35, 0xad, 0x00, - 0xfd, 0xbb, 0x01, 0x00, 0x2c, 0x0e, 0x59, 0x00, 0xf6, 0x3d, 0x04, 0xd0, 0x99, 0x1c, 0xf7, 0x4f, - 0xc9, 0xa6, 0xc7, 0xa0, 0xa6, 0xc7, 0x40, 0x30, 0x20, 0x04, 0xe1, 0x9f, 0x14, 0x16, 0x5c, 0x6b, - 0x06, 0x80, 0x1c, 0xf8, 0x1f, 0x07, 0xff, 0x8f, 0x83, 0x03, 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0xd4, 0xe6, 0xec, + 0x25, 0xda, 0x6a, 0xab, 0x66, 0x64, 0xb3, 0x50, 0x07, 0x53, 0x8f, 0x86, 0x30, 0xc9, 0xfe, 0x56, + 0x70, 0x67, 0xc1, 0xb7, 0x55, 0x87, 0x29, 0xb8, 0xeb, 0x05, 0x83, 0x76, 0x1c, 0x43, 0x46, 0xf8, + 0x8f, 0xac, 0xd2, 0xfd, 0xdf, 0x27, 0x0b, 0x46, 0x06, 0x06, 0x2d, 0xf0, 0xda, 0xf8, 0x6b, 0x1a, + 0xf5, 0xce, 0xc0, 0x1b, 0xb2, 0x7f, 0x7a, 0xa4, 0x6f, 0xbb, 0x56, 0x3a, 0xc0, 0x1e, 0xb8, 0x28, + 0x7c, 0x73, 0x7f, 0xb4, 0xbe, 0x5a, 0xe4, 0xf8, 0x3a, 0xeb, 0x93, 0x0e, 0x71, 0x5b, 0x54, 0x0d, + 0xd5, 0x26, 0x34, 0x81, 0x4a, 0x3e, 0xc1, 0xd3, 0x53, 0x8e, 0x3a, 0xaf, 0x98, 0x67, 0x16, 0xb8, + 0x28, 0x7f, 0x87, 0xb8, 0x4a, 0xc7, 0xef, 0x74, 0x80, 0x96, 0xeb, 0x11, 0xd1, 0xcd, 0xa3, 0x0a, + 0xc8, 0xbe, 0x72, 0x76, 0x26, 0xc2, 0xd3, 0xc9, 0x37, 0x6e, 0x65, 0x8a, 0x89, 0x47, 0x8b, 0x8e, + 0x57, 0x8e, 0x2b, 0xf5, 0x77, 0x35, 0xe1, 0x08, 0x4c, 0xb1, 0xae, 0xf9, 0x3c, 0xab, 0x36, 0x4c, + 0x16, 0xc8, 0xc5, 0x90, 0xdb, 0xc4, 0x4e, 0xd0, 0x74, 0xbb, 0xbe, 0x2b, 0xc1, 0x39, 0x51, 0x6d, + 0x47, 0x62, 0x7c, 0x6a, 0x9a, 0x7b, 0xc7, 0x81, 0xc7, 0xe2, 0xaf, 0x69, 0x16, 0x09, 0x1d, 0xe4, + 0xdf, 0x6a, 0xcd, 0x3e, 0xc8, 0x50, 0x72, 0x19, 0xd7, 0xc8, 0x57, 0xb8, 0xbb, 0x27, 0x17, 0x93, + 0x78, 0xfb, 0x8c, 0x57, 0x11, 0x9b, 0x34, 0x35, 0x4a, 0x90, 0xc9, 0x26, 0x96, 0xb7, 0xc0, 0xa4, + 0x3e, 0xb6, 0xfc, 0xd5, 0x55, 0x01, 0xc9, 0x77, 0x8e, 0x7d, 0x40, 0x2e, 0x8f, 0xa3, 0xbf, 0xf8, + 0x6e, 0x4f, 0x1a, 0xfb, 0xc7, 0x32, 0x91, 0x0a, 0xfd, 0xd2, 0x0f, 0x87, 0x72, 0xd2, 0x7b, 0xa6, + 0x1c, 0xd2, 0xd9, 0x29, 0xca, 0xdc, 0xde, 0xe8, 0x8d, 0x65, 0xc8, 0xdb, 0xd4, 0xbb, 0x4c, 0x47, + 0x23, 0xf0, 0xc2, 0x0c, 0x4b, 0x3e, 0x2f, 0xc3, 0x68, 0xc3, 0x43, 0x8b, 0x60, 0xce, 0xe3, 0xff, + 0x0f, 0x65, 0x23, 0x91, 0x1d, 0x79, 0xc1, 0x36, 0x1d, 0xa9, 0xc8, 0xdc, 0x8d, 0x00, 0x2a, 0xa5, + 0x88, 0xe9, 0xcc, 0xa9, 0xbd, 0x99, 0xf2, 0xd6, 0x12, 0x5c, 0xeb, 0xac, 0x37, 0xba, 0x00, 0xf0, + 0xe3, 0xc7, 0x8f, 0x1f, 0x3f, 0x7e, 0xfc, 0xf8, 0xf1, 0xe3, 0xc7, 0x8f, 0x1f, 0x3f, 0x7e, 0xfc, + 0xf8, 0xf1, 0xe3, 0xc7, 0x8f, 0x1f, 0x3f, 0x7e, 0xfc, 0xf8, 0xf1, 0xe3, 0xc7, 0x8f, 0x1f, 0x3f, + 0x7e, 0xfc, 0xf8, 0xf1, 0xe3, 0xc7, 0x8f, 0x1f, 0x3f, 0x7e, 0xfc, 0xf8, 0xf1, 0xe3, 0xc7, 0x8f, + 0x1f, 0x3f, 0x7e, 0xfc, 0xf8, 0xf1, 0xe3, 0xc7, 0x8f, 0x1f, 0x3f, 0x7e, 0xfc, 0xf8, 0xf1, 0xe3, + 0xc7, 0x8f, 0x1f, 0x3f, 0x7e, 0xfc, 0xf8, 0xf1, 0xe3, 0xc7, 0x8f, 0x1f, 0x3f, 0x7e, 0xfc, 0xf8, + 0xf1, 0xe3, 0xc7, 0x8f, 0x1f, 0x3f, 0x7e, 0xfc, 0xbf, 0xe0, 0xff, 0x03, 0x55, 0x5d, 0xfa, 0xfb, + 0x00, 0x96, 0x00, 0x00, }; #endif // defined(BINDATA_INCLUDE_DATA) @@ -946,8 +2374,8 @@ #if defined(BINDATA_INCLUDE_STORAGE_PVT_DEFN) { - 8704, // uncompressed data size (bytes) - 6649, // compressed data size (bytes) + 38400, // uncompressed data size (bytes) + 18068, // compressed data size (bytes) kgspBinArchiveBooterUnloadUcode_GA100_image_prod_data, // compressed data pointer NV_TRUE, // is pData compressed? NV_TRUE, // contain information for file overriding? @@ -969,8 +2397,8 @@ // static BINDATA_CONST NvU8 kgspBinArchiveBooterUnloadUcode_GA100_header_prod_data[] = { - 0x63, 0x60, 0x00, 0x02, 0x46, 0x20, 0x96, 0x02, 0x62, 0x0e, 0x08, 0x13, 0x4c, 0x48, 0x42, 0x69, - 0x20, 0x00, 0x00, 0x2b, 0x43, 0x56, 0x8a, 0x24, 0x00, 0x00, 0x00, + 0x63, 0x60, 0x00, 0x02, 0x46, 0x20, 0x76, 0x07, 0x62, 0x7f, 0x08, 0x13, 0x4c, 0xb8, 0x41, 0x69, + 0x20, 0x00, 0x00, 0x99, 0x4d, 0xfb, 0x23, 0x24, 0x00, 0x00, 0x00, }; #endif // defined(BINDATA_INCLUDE_DATA) @@ -1003,31 +2431,31 @@ // static BINDATA_CONST NvU8 kgspBinArchiveBooterUnloadUcode_GA100_sig_dbg_data[] = { - 0x01, 0x80, 0x01, 0x7f, 0xfe, 0x27, 0x14, 0x82, 0xed, 0x50, 0xb4, 0xad, 0x04, 0xb4, 0x65, 0xe6, - 0xa2, 0x91, 0x3f, 0x4a, 0xc1, 0x55, 0x7a, 0xb0, 0x08, 0x78, 0x5f, 0x32, 0xe9, 0x8f, 0x54, 0xf1, - 0xcd, 0xa2, 0x05, 0x16, 0xaf, 0xbf, 0xfc, 0xc0, 0xa4, 0x96, 0x83, 0xd7, 0xfe, 0xaa, 0x9d, 0x7a, - 0x82, 0x5a, 0x78, 0x44, 0x26, 0xa6, 0xc4, 0x6c, 0xdc, 0x17, 0x98, 0x90, 0x55, 0xe2, 0x39, 0x8d, - 0xb4, 0xfa, 0xb2, 0x0b, 0x45, 0x0b, 0x2d, 0xd5, 0x2b, 0xb5, 0x63, 0x8d, 0x31, 0x20, 0xde, 0x12, - 0x8f, 0xe8, 0x7c, 0x24, 0xe4, 0xfe, 0xe7, 0x29, 0x37, 0xc3, 0xcf, 0x3f, 0x2d, 0xff, 0x50, 0x69, - 0x62, 0xf3, 0xd2, 0xc2, 0x77, 0x1c, 0x85, 0x3a, 0xbb, 0x5b, 0x93, 0x61, 0x8b, 0x46, 0xd4, 0xca, - 0x55, 0xc1, 0x1b, 0x58, 0x95, 0x38, 0x70, 0xb0, 0x02, 0x85, 0x6c, 0x21, 0x1d, 0x4b, 0x5b, 0xd6, - 0x94, 0xa8, 0xf0, 0xb5, 0xba, 0x5e, 0xfa, 0x75, 0x16, 0x7a, 0xec, 0x27, 0xfd, 0x9f, 0x0d, 0x42, - 0xc0, 0xcd, 0x50, 0x38, 0x8e, 0x56, 0x09, 0xbf, 0x3f, 0x31, 0x19, 0xa8, 0xd5, 0xe9, 0x5c, 0x84, - 0x66, 0xcc, 0xf6, 0x79, 0x2c, 0x5e, 0x02, 0x6a, 0xb1, 0x51, 0x94, 0xaa, 0x16, 0xe7, 0xed, 0xd0, - 0xca, 0x69, 0x13, 0xab, 0x50, 0xac, 0x82, 0xcb, 0x8e, 0x92, 0x35, 0xcd, 0xb1, 0x77, 0x4d, 0xe4, - 0xe4, 0x1d, 0x58, 0xea, 0x59, 0x2d, 0x34, 0x09, 0x9b, 0xe9, 0x2a, 0x6c, 0xf5, 0x84, 0xe8, 0x9d, - 0x9a, 0x99, 0xea, 0x6c, 0xab, 0x90, 0xb7, 0xa8, 0xa8, 0x01, 0x9b, 0x46, 0xd9, 0x86, 0x5d, 0xc5, - 0x1b, 0x9b, 0x5e, 0x11, 0x9e, 0x1a, 0x6f, 0x4d, 0x45, 0x5c, 0x87, 0x26, 0x92, 0x7e, 0xaf, 0x04, - 0x56, 0x3e, 0xe6, 0x09, 0x8e, 0x13, 0xac, 0x13, 0x77, 0x0a, 0xb2, 0xcd, 0x4f, 0xa1, 0x61, 0xba, - 0x43, 0x92, 0x8d, 0x60, 0x5e, 0x23, 0x40, 0x57, 0x29, 0x43, 0x26, 0x6e, 0xb8, 0x5d, 0xfe, 0x9e, - 0x93, 0x7f, 0x62, 0x04, 0x76, 0xa9, 0xb5, 0xd3, 0x8d, 0xa9, 0x6f, 0xe9, 0x60, 0x67, 0xe9, 0xd9, - 0xf6, 0x80, 0x1b, 0x89, 0x9f, 0xa9, 0x26, 0x00, 0x1f, 0x63, 0x99, 0x68, 0xf1, 0xe9, 0x64, 0x5c, - 0x7e, 0xd0, 0x47, 0xe2, 0xcc, 0x03, 0x1a, 0xaf, 0xb6, 0xb8, 0xa4, 0xc1, 0x31, 0xf5, 0x27, 0xe5, - 0x21, 0x45, 0x56, 0xfb, 0xc4, 0xfd, 0xec, 0x65, 0x79, 0x0b, 0x86, 0x76, 0xcc, 0x21, 0x8c, 0x62, - 0xce, 0xd3, 0x6a, 0x09, 0xfe, 0x34, 0xec, 0x4d, 0xba, 0xe3, 0x6e, 0x11, 0x0b, 0x4e, 0x70, 0x6d, - 0xe7, 0xc4, 0x47, 0xa0, 0xee, 0xc3, 0x66, 0x1d, 0xfc, 0xec, 0x1c, 0xf7, 0x2f, 0x3b, 0xbc, 0xda, - 0xc2, 0x63, 0x68, 0x0d, 0xfc, 0xe1, 0x92, 0xbb, 0x56, 0xae, 0x8c, 0x14, 0xf9, 0x98, 0x30, 0x4f, - 0x03, 0x56, 0x61, 0xd5, 0x8b, 0x30, 0x5c, 0xb1, 0xb3, 0x80, 0x01, 0x00, 0x00, + 0x01, 0x80, 0x01, 0x7f, 0xfe, 0x18, 0x64, 0x52, 0x7b, 0xaa, 0x8d, 0x42, 0x0c, 0xcf, 0x2f, 0x64, + 0x41, 0x47, 0xd7, 0x8b, 0x35, 0x79, 0x4b, 0xb0, 0xdd, 0x7e, 0xea, 0x7c, 0x47, 0x1a, 0x7e, 0x54, + 0x0b, 0x24, 0x81, 0x6b, 0x26, 0x04, 0x51, 0x31, 0x33, 0x44, 0x6a, 0x1a, 0x5a, 0x69, 0x5b, 0x2c, + 0x7d, 0x0b, 0xe3, 0x21, 0x4a, 0x75, 0xd9, 0x3d, 0x79, 0x20, 0xe9, 0x46, 0xee, 0x8f, 0x06, 0x82, + 0x70, 0x1f, 0x2c, 0xeb, 0x2f, 0x2c, 0xbd, 0x49, 0xcb, 0x3f, 0x5a, 0x75, 0x2f, 0xe8, 0x95, 0xde, + 0x09, 0x19, 0x6e, 0xea, 0x7d, 0xfb, 0x98, 0xcd, 0x42, 0xba, 0x0d, 0xe1, 0xef, 0x8a, 0xfd, 0xdb, + 0x66, 0xa7, 0x5d, 0x77, 0x90, 0xb2, 0xa2, 0x3f, 0x6a, 0x6c, 0x07, 0x64, 0x03, 0x6b, 0xec, 0xd1, + 0xd3, 0x33, 0x32, 0xce, 0x2b, 0xaf, 0x28, 0x62, 0xb9, 0x8d, 0x4f, 0x4e, 0x2f, 0x99, 0x8a, 0xd8, + 0x66, 0x49, 0xca, 0x43, 0x47, 0x31, 0x5c, 0x7b, 0x5b, 0x67, 0x75, 0x5b, 0xd7, 0x1e, 0x6e, 0x2c, + 0x5f, 0x30, 0x6f, 0xf2, 0xcd, 0xc4, 0x6e, 0x15, 0xc6, 0x78, 0x55, 0x1b, 0x24, 0x55, 0x87, 0x62, + 0x59, 0xbb, 0xfb, 0xf2, 0x3c, 0xc3, 0x38, 0xe8, 0x47, 0x22, 0xa9, 0xcf, 0xbf, 0x39, 0x65, 0x96, + 0x9a, 0x19, 0xb7, 0xb7, 0xdc, 0xc2, 0x54, 0x74, 0x9b, 0x8e, 0xe3, 0x15, 0xc4, 0xd9, 0x47, 0x05, + 0x39, 0x36, 0xdb, 0x8e, 0x0d, 0x82, 0x0c, 0xe4, 0x1a, 0xb1, 0x4f, 0xef, 0x18, 0x16, 0xa6, 0xad, + 0x44, 0xeb, 0x5f, 0x85, 0x91, 0x0b, 0xf7, 0x52, 0x95, 0xae, 0xee, 0x42, 0x1b, 0x85, 0x54, 0xb4, + 0xce, 0x69, 0x98, 0x52, 0x7a, 0x65, 0xfd, 0x0f, 0xa3, 0x42, 0x39, 0x16, 0xe0, 0xf0, 0x1f, 0xb8, + 0x24, 0x94, 0x30, 0xed, 0x2a, 0x8b, 0x8f, 0x3f, 0x91, 0xde, 0xec, 0xdd, 0xd8, 0x79, 0x3c, 0x33, + 0xdb, 0xd4, 0xed, 0x7f, 0x60, 0xe3, 0x18, 0x34, 0xef, 0xc1, 0xfa, 0x6d, 0x9e, 0xcd, 0x71, 0xd5, + 0x82, 0xc5, 0xe4, 0x9f, 0x18, 0xda, 0xb7, 0xc0, 0xd4, 0xde, 0x09, 0xf5, 0x8b, 0x69, 0x4d, 0xa8, + 0x60, 0xe4, 0x5a, 0xb1, 0x8b, 0x6a, 0xcf, 0x66, 0xf5, 0x57, 0x0a, 0x0c, 0x26, 0xfd, 0x5d, 0xb2, + 0xdf, 0xe7, 0xe3, 0x88, 0x1b, 0xfc, 0x74, 0x6a, 0x66, 0x38, 0x6b, 0xf0, 0x5f, 0xad, 0x32, 0x9c, + 0x91, 0x32, 0x7e, 0x36, 0xbb, 0x9b, 0x21, 0x75, 0xd8, 0x38, 0x48, 0x19, 0xe5, 0xf3, 0x55, 0xae, + 0x76, 0x13, 0xa5, 0x0d, 0x55, 0xe1, 0x65, 0xb0, 0xa3, 0x3f, 0xc2, 0x5c, 0xd5, 0x47, 0x6d, 0x58, + 0xd0, 0x3b, 0xa4, 0xc1, 0xd8, 0xe1, 0xd2, 0x3b, 0xab, 0x14, 0x64, 0xe1, 0x74, 0x5c, 0x38, 0x9a, + 0x8f, 0xdb, 0x74, 0x48, 0x4a, 0x54, 0xfc, 0xaf, 0x5b, 0x09, 0x32, 0x2e, 0xe7, 0xf2, 0xc7, 0x70, + 0x2a, 0xa9, 0x63, 0x37, 0xbf, 0x4c, 0x1e, 0xdc, 0x67, 0x80, 0x01, 0x00, 0x00, }; #endif // defined(BINDATA_INCLUDE_DATA) @@ -1060,31 +2488,31 @@ // static BINDATA_CONST NvU8 kgspBinArchiveBooterUnloadUcode_GA100_sig_prod_data[] = { - 0x01, 0x80, 0x01, 0x7f, 0xfe, 0x99, 0x28, 0x07, 0xb5, 0xce, 0x8e, 0x09, 0x5c, 0x30, 0x2a, 0x9c, - 0xdc, 0x66, 0x84, 0xa4, 0x0d, 0x33, 0x44, 0x87, 0xa2, 0xd7, 0x17, 0xb5, 0x14, 0x15, 0x12, 0x82, - 0x3e, 0xd3, 0x74, 0xc9, 0xac, 0xb1, 0x92, 0xcc, 0x85, 0x88, 0xcb, 0x87, 0x9f, 0xdc, 0x1e, 0x72, - 0xf8, 0x0a, 0x44, 0xec, 0x86, 0x0d, 0x4b, 0xbf, 0x04, 0x19, 0x73, 0x45, 0x5e, 0x1b, 0x90, 0x90, - 0xb8, 0xad, 0x94, 0x67, 0x14, 0x60, 0xee, 0xc2, 0x86, 0x37, 0xd1, 0x02, 0x54, 0xbe, 0x7c, 0x01, - 0x7f, 0xae, 0x40, 0x03, 0x88, 0x0e, 0x45, 0x84, 0x5e, 0x52, 0x33, 0x2b, 0x2c, 0x5b, 0x00, 0x85, - 0xfe, 0x78, 0xb8, 0xf2, 0x5d, 0x43, 0xa1, 0xa0, 0xbb, 0xc0, 0x6b, 0xa7, 0x83, 0xa8, 0xbc, 0xf9, - 0xa3, 0x83, 0xd4, 0x0f, 0x9f, 0xc9, 0x88, 0x4f, 0x4c, 0x6a, 0xfa, 0x90, 0x39, 0x86, 0xc5, 0xe4, - 0x79, 0x20, 0xf3, 0x1e, 0x76, 0x6d, 0x59, 0x1d, 0x27, 0x1b, 0x47, 0x55, 0x3c, 0x49, 0xe6, 0xdf, - 0xa8, 0x63, 0xb4, 0xbd, 0x8c, 0x66, 0xc8, 0x9c, 0x43, 0x9d, 0x49, 0xc5, 0x20, 0xdc, 0x71, 0x0b, - 0xf6, 0xac, 0x49, 0x9a, 0xe0, 0x4f, 0xa9, 0x3a, 0x00, 0x0c, 0x01, 0x5e, 0xfd, 0xbc, 0xdc, 0xbc, - 0x3f, 0x4b, 0xd6, 0xf6, 0x59, 0x48, 0x57, 0xdd, 0xbe, 0xa3, 0xbf, 0x6e, 0x9c, 0x52, 0x3c, 0xa8, - 0xde, 0x49, 0x56, 0x9a, 0x69, 0x01, 0x86, 0xf5, 0x48, 0x2f, 0xe8, 0xe6, 0xf2, 0x16, 0xf0, 0xee, - 0xe3, 0xf9, 0xce, 0x42, 0x13, 0x7d, 0x8e, 0xa5, 0xb2, 0xb4, 0x04, 0xc2, 0x82, 0xe2, 0x1e, 0xaf, - 0xc9, 0xa0, 0x2c, 0x68, 0x01, 0xde, 0xbf, 0x4f, 0x56, 0x55, 0x3d, 0x8f, 0xf4, 0x6b, 0x77, 0x32, - 0x0c, 0xaf, 0x9b, 0x5c, 0x5e, 0x8f, 0x52, 0x6a, 0xcb, 0x91, 0xa2, 0xa3, 0x63, 0x36, 0x9f, 0xea, - 0x35, 0x75, 0x6f, 0x17, 0xcc, 0xd2, 0x24, 0x21, 0x74, 0xcc, 0x32, 0x72, 0x2e, 0x99, 0x8d, 0x01, - 0xcf, 0x96, 0xf7, 0xaa, 0xaa, 0xb7, 0x13, 0xd1, 0x2e, 0xf0, 0x7d, 0x8f, 0x7c, 0xa8, 0xfe, 0x42, - 0x18, 0x7a, 0x46, 0xec, 0x46, 0x2a, 0x1f, 0xf3, 0xef, 0x2e, 0xc7, 0x74, 0x7f, 0x60, 0x46, 0xf1, - 0x9b, 0xb8, 0x45, 0x6e, 0x88, 0x3f, 0x71, 0xd8, 0xea, 0x43, 0x9e, 0x4b, 0xd9, 0x7b, 0xa9, 0xac, - 0x86, 0xf8, 0x20, 0x71, 0xf4, 0x81, 0xfa, 0xed, 0x4a, 0x46, 0xb7, 0xe6, 0xdd, 0x62, 0x2c, 0xcf, - 0x92, 0xcc, 0xb4, 0x4f, 0x5e, 0x33, 0xa0, 0xfe, 0xea, 0xcd, 0x41, 0x68, 0x1f, 0x7e, 0xc4, 0xc3, - 0x38, 0x67, 0x65, 0x37, 0xad, 0xc5, 0x88, 0xac, 0x51, 0x71, 0xfa, 0xec, 0x5a, 0x6d, 0x6b, 0x20, - 0x64, 0x81, 0xbc, 0x75, 0x7c, 0x2e, 0xf4, 0xb3, 0xfb, 0x5e, 0x0c, 0xbf, 0x14, 0x0f, 0x7d, 0x94, - 0x1a, 0x20, 0x11, 0xd4, 0x25, 0x4f, 0x24, 0x10, 0xe0, 0x80, 0x01, 0x00, 0x00, + 0x01, 0x80, 0x01, 0x7f, 0xfe, 0x15, 0x28, 0xc1, 0x99, 0x80, 0xc0, 0x3e, 0x31, 0xcb, 0x3e, 0xed, + 0x38, 0x17, 0xa4, 0x3c, 0x15, 0x69, 0x05, 0xe6, 0xa8, 0xb3, 0xe3, 0x7a, 0x10, 0xef, 0x32, 0xb9, + 0xa6, 0xb0, 0x3f, 0x12, 0x12, 0xad, 0xf8, 0x93, 0xf9, 0x04, 0x55, 0x0e, 0x42, 0xe6, 0xaa, 0xaf, + 0x0e, 0x06, 0x41, 0x3b, 0x4a, 0x51, 0xb2, 0x89, 0x63, 0xb9, 0x6e, 0x08, 0x5b, 0x4a, 0xa4, 0xbf, + 0x97, 0xe6, 0x64, 0xd4, 0x19, 0x5e, 0xd5, 0x3d, 0xb1, 0xec, 0xb8, 0x23, 0x2c, 0x4c, 0xf6, 0x53, + 0xaf, 0xa1, 0xc1, 0xc0, 0xb9, 0xea, 0x6f, 0x56, 0xfe, 0x0d, 0xa1, 0xcb, 0x2b, 0x84, 0x20, 0xeb, + 0xa4, 0x5b, 0x23, 0x51, 0xa6, 0xac, 0x54, 0x6e, 0x10, 0xa5, 0x8c, 0x7f, 0x76, 0xfa, 0x1f, 0x01, + 0x8c, 0xea, 0x0e, 0x46, 0x18, 0x16, 0xba, 0x41, 0xd8, 0x2c, 0x31, 0x83, 0xa3, 0xe5, 0x3e, 0x0f, + 0x81, 0xb1, 0x31, 0x6d, 0x22, 0x08, 0x8b, 0xf5, 0x01, 0x5d, 0xdf, 0xf6, 0xf6, 0x62, 0x26, 0xaa, + 0xf2, 0x7d, 0x40, 0xd9, 0xf5, 0x70, 0x6d, 0x95, 0x3d, 0xf2, 0x8d, 0x7d, 0x93, 0x85, 0x04, 0x25, + 0xbe, 0xf9, 0xe5, 0x47, 0x6e, 0x80, 0xaf, 0xc0, 0x6a, 0xd4, 0xba, 0x62, 0x94, 0xc3, 0x6b, 0xa8, + 0x58, 0x9b, 0x49, 0xae, 0xaf, 0xf5, 0xaa, 0xd3, 0x52, 0x67, 0xde, 0x9a, 0x64, 0x84, 0xcb, 0x98, + 0x12, 0x53, 0xab, 0x4c, 0xe2, 0xed, 0x6e, 0xce, 0xc1, 0x76, 0x4a, 0xe7, 0x2a, 0x1d, 0x81, 0x60, + 0x2d, 0xb0, 0xdd, 0x8a, 0x91, 0x10, 0x25, 0x60, 0x00, 0x35, 0xe0, 0x40, 0x3c, 0xb1, 0xff, 0x8b, + 0x3a, 0xc7, 0xba, 0x4b, 0xf8, 0xac, 0xfd, 0x2e, 0x76, 0x85, 0xeb, 0x7a, 0xc8, 0x61, 0x58, 0x3e, + 0xc3, 0xfc, 0x2e, 0xf0, 0x50, 0xa4, 0x79, 0x5d, 0x6c, 0xb7, 0xfc, 0xb5, 0x0a, 0x69, 0xfb, 0x5c, + 0xc9, 0x17, 0x17, 0x0c, 0xf1, 0x5e, 0xc1, 0xd4, 0x16, 0xf7, 0x14, 0x38, 0xb7, 0x7f, 0xf7, 0x7c, + 0xc0, 0xf2, 0x0d, 0x70, 0xfd, 0x8f, 0xf2, 0x7d, 0x7b, 0xbb, 0x12, 0x94, 0x0b, 0x2d, 0x43, 0xf2, + 0x3f, 0x46, 0xc7, 0x02, 0x3b, 0x5f, 0xfa, 0x04, 0x20, 0x5a, 0x01, 0x91, 0x4a, 0x5d, 0xc0, 0x02, + 0xc2, 0x12, 0x4d, 0x83, 0xe7, 0x02, 0x27, 0xbb, 0x0d, 0x77, 0x2b, 0xc8, 0x21, 0x69, 0xed, 0x96, + 0xfe, 0x64, 0xbc, 0xa6, 0x64, 0x5c, 0xba, 0x1b, 0xcb, 0xeb, 0x0b, 0x1a, 0xd7, 0x83, 0xb8, 0xb1, + 0xbf, 0x20, 0x21, 0x01, 0x89, 0xfa, 0x53, 0x72, 0x21, 0xe9, 0x50, 0xd9, 0xc6, 0xac, 0x81, 0x8e, + 0xc2, 0x8a, 0x61, 0xe4, 0x4c, 0x3f, 0x85, 0xa4, 0xb3, 0x27, 0x00, 0x3c, 0xbe, 0x76, 0x4a, 0x64, + 0xd1, 0xf9, 0x9a, 0x13, 0xfc, 0xc2, 0x57, 0x39, 0x67, 0x5d, 0xec, 0x58, 0x83, 0xa2, 0x37, 0x9d, + 0x3c, 0xa6, 0xcf, 0xdb, 0x72, 0x5f, 0x2e, 0x4f, 0xa5, 0x80, 0x01, 0x00, 0x00, }; #endif // defined(BINDATA_INCLUDE_DATA) @@ -1117,7 +2545,7 @@ // static BINDATA_CONST NvU8 kgspBinArchiveBooterUnloadUcode_GA100_patch_loc_data[] = { - 0x00, 0x1c, 0x00, 0x00, + 0x00, 0x49, 0x00, 0x00, }; #endif // defined(BINDATA_INCLUDE_DATA) diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/generated/g_bindata_kgspGetBinArchiveBooterUnloadUcode_GA102.c nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_bindata_kgspGetBinArchiveBooterUnloadUcode_GA102.c --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/generated/g_bindata_kgspGetBinArchiveBooterUnloadUcode_GA102.c 2023-10-25 20:19:26.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_bindata_kgspGetBinArchiveBooterUnloadUcode_GA102.c 2024-03-05 22:11:16.000000000 +0000 @@ -34,459 +34,1171 @@ // VAR NAME: booter_ucode_data_ga10x // COMPRESSION: YES // COMPLEX_STRUCT: NO -// DATA SIZE (bytes): 8960 -// COMPRESSED SIZE (bytes): 7153 +// DATA SIZE (bytes): 38656 +// COMPRESSED SIZE (bytes): 18553 // static BINDATA_CONST NvU8 kgspBinArchiveBooterUnloadUcode_GA102_image_dbg_data[] = { - 0xed, 0xd9, 0x43, 0x5c, 0x25, 0x80, 0xb7, 0xc0, 0xf1, 0x6c, 0xdb, 0xc6, 0x64, 0x4d, 0xb6, 0x8d, - 0x9b, 0xed, 0x9a, 0xdc, 0xe4, 0x26, 0xdb, 0x9a, 0xcc, 0xc9, 0x35, 0x75, 0xb3, 0x6e, 0xbe, 0xb9, - 0xc9, 0xf6, 0xcd, 0x36, 0xa6, 0xc9, 0x78, 0xfb, 0xff, 0xe6, 0x2d, 0xdf, 0xe2, 0xfd, 0xbf, 0xbb, - 0xb3, 0x3e, 0xe7, 0xf3, 0xdb, 0x1c, 0x28, 0xa8, 0xff, 0xdf, 0x84, 0xa9, 0x0b, 0xc6, 0xea, 0x02, - 0x3d, 0x12, 0x22, 0x5d, 0x62, 0xb4, 0x93, 0x94, 0x6e, 0x3a, 0x42, 0x4a, 0xef, 0xbf, 0x53, 0x74, - 0x05, 0xb1, 0x5c, 0x58, 0x0e, 0xc8, 0x3f, 0xe5, 0x3d, 0x77, 0x1d, 0x75, 0x65, 0x8c, 0x26, 0xb2, - 0x44, 0x76, 0x20, 0xd7, 0x04, 0x64, 0x3a, 0x5d, 0x7e, 0x59, 0x07, 0xad, 0x4b, 0xdb, 0x93, 0xa6, - 0x7d, 0x0d, 0x45, 0x6e, 0x88, 0x12, 0x6b, 0xac, 0x25, 0xf5, 0x5b, 0xab, 0x2c, 0x01, 0x9c, 0x0d, - 0xd5, 0x1c, 0xed, 0x5f, 0x18, 0x4b, 0x0b, 0xa7, 0x12, 0x9a, 0x39, 0x0e, 0x77, 0x1d, 0x21, 0x1b, - 0xdc, 0x48, 0x22, 0x08, 0xaa, 0x0c, 0xc4, 0xcd, 0x2c, 0x04, 0xa9, 0xed, 0xd1, 0x61, 0xca, 0x7a, - 0xa3, 0x7c, 0x41, 0xb3, 0x98, 0x16, 0x30, 0x20, 0x6a, 0x08, 0x6e, 0x36, 0x5e, 0xd3, 0x75, 0xa7, - 0xf6, 0x24, 0x81, 0x01, 0x20, 0x65, 0x10, 0x77, 0xa2, 0x89, 0xed, 0xb5, 0x56, 0xdc, 0xdd, 0xe3, - 0x94, 0xd9, 0x8d, 0xa9, 0xcf, 0xde, 0x21, 0x98, 0x95, 0x75, 0x9d, 0x87, 0x66, 0x7e, 0x5a, 0x23, - 0xa3, 0xe7, 0x79, 0xfc, 0xde, 0xbf, 0x0f, 0x28, 0x0f, 0xbe, 0xfd, 0xd9, 0x5f, 0xcb, 0x19, 0x32, - 0x37, 0xb2, 0x0a, 0x6b, 0xec, 0x54, 0x7c, 0xe2, 0x4d, 0x14, 0xbb, 0xbb, 0x2e, 0x09, 0x21, 0x8d, - 0x53, 0x82, 0xb9, 0x9a, 0x18, 0x2a, 0x7a, 0x78, 0x94, 0x91, 0x56, 0xa9, 0xd1, 0x54, 0x4c, 0x46, - 0x9c, 0xd0, 0xc9, 0x30, 0xa8, 0x80, 0x45, 0x20, 0xb4, 0x62, 0x6a, 0x5d, 0x91, 0xd4, 0x1e, 0x4d, - 0x68, 0x5c, 0xf0, 0x5b, 0x7e, 0x76, 0x4a, 0xbf, 0x8a, 0xe4, 0x71, 0x4b, 0x09, 0x5d, 0x1d, 0x2d, - 0x16, 0xaa, 0x8b, 0xcb, 0x2f, 0x64, 0x62, 0x03, 0x6a, 0xbc, 0x3c, 0xb3, 0x90, 0xda, 0x14, 0x5d, - 0x5c, 0xfe, 0xcb, 0x9a, 0xfc, 0xd6, 0xee, 0xaf, 0x0d, 0x7a, 0x34, 0xe9, 0xa1, 0x97, 0x3c, 0xfe, - 0xca, 0x2d, 0x80, 0x50, 0xe1, 0x1d, 0x9f, 0x7b, 0xf3, 0xd5, 0xc8, 0x24, 0xf7, 0x60, 0x52, 0x8b, - 0x77, 0x2c, 0xd4, 0x1b, 0x66, 0x65, 0x19, 0xf7, 0xd0, 0x4f, 0x8e, 0xc7, 0x2d, 0xad, 0x79, 0x8e, - 0x8f, 0xc1, 0x89, 0x83, 0x9e, 0x62, 0xb5, 0x56, 0x31, 0x28, 0x68, 0x3b, 0x72, 0x64, 0x0e, 0xf2, - 0xbc, 0x40, 0x01, 0xde, 0x19, 0x61, 0x0a, 0x7b, 0x97, 0xaa, 0xa0, 0x05, 0xa3, 0x9a, 0xf3, 0x86, - 0xa4, 0x75, 0x4b, 0x3f, 0xea, 0xb4, 0x95, 0xb6, 0x29, 0xad, 0xc8, 0x93, 0x9b, 0x8b, 0x0f, 0x5e, - 0xee, 0x22, 0x19, 0x50, 0x4d, 0x3f, 0x8a, 0x73, 0x22, 0x9b, 0x1b, 0x8e, 0x55, 0x1b, 0x1d, 0x29, - 0x0a, 0xe8, 0x45, 0xcd, 0xc3, 0xd4, 0xaa, 0x2b, 0x3f, 0x66, 0x55, 0x14, 0xeb, 0xa3, 0x02, 0xbe, - 0xd4, 0x23, 0x86, 0xf8, 0x16, 0x80, 0xcc, 0xf6, 0x95, 0x80, 0xf5, 0x1b, 0x0b, 0x1b, 0xbe, 0xde, - 0x51, 0x20, 0x51, 0x10, 0x0b, 0xd6, 0x69, 0x35, 0xb9, 0x25, 0x3b, 0x1e, 0xbc, 0x3c, 0x39, 0xb7, - 0xb0, 0x6c, 0x7a, 0x89, 0x11, 0xf8, 0x5e, 0xb5, 0x2a, 0xbe, 0xb5, 0x81, 0x93, 0x0f, 0xa7, 0x88, - 0xb1, 0x60, 0x82, 0x3c, 0x91, 0x98, 0xfd, 0x6c, 0x19, 0x1e, 0xdc, 0xff, 0x2f, 0x6c, 0xd0, 0x24, - 0x02, 0x45, 0xc4, 0x66, 0x2f, 0x9d, 0xb7, 0xfb, 0x93, 0xf1, 0x4f, 0x8c, 0x95, 0xb3, 0xae, 0xbe, - 0xaf, 0xf4, 0x2c, 0x1a, 0xeb, 0xab, 0x27, 0x01, 0x92, 0x6f, 0xf2, 0xee, 0xa2, 0x98, 0xbf, 0x9a, - 0xbb, 0xc7, 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0x5f, + 0xbf, 0x7e, 0xfd, 0xfa, 0xf5, 0xeb, 0xd7, 0xaf, 0x5f, 0xbf, 0x7e, 0xfd, 0xfa, 0xf5, 0xeb, 0xd7, + 0xaf, 0x5f, 0xbf, 0x7e, 0xfd, 0xfa, 0xf5, 0xeb, 0xd7, 0xaf, 0x5f, 0xbf, 0x7e, 0xfd, 0xfa, 0xf5, + 0xeb, 0xd7, 0xaf, 0x5f, 0xbf, 0x7e, 0xfd, 0xfa, 0xf5, 0xeb, 0xd7, 0xaf, 0x5f, 0xbf, 0x7e, 0xfd, + 0xfa, 0xf5, 0xeb, 0xd7, 0xaf, 0x5f, 0xbf, 0x7e, 0xfd, 0xfa, 0xf5, 0xeb, 0xd7, 0xff, 0x1d, 0xff, + 0x0f, 0x07, 0x7b, 0x00, 0x77, 0x00, 0x97, 0x00, 0x00, }; #endif // defined(BINDATA_INCLUDE_DATA) @@ -496,8 +1208,8 @@ #if defined(BINDATA_INCLUDE_STORAGE_PVT_DEFN) { - 8960, // uncompressed data size (bytes) - 7153, // compressed data size (bytes) + 38656, // uncompressed data size (bytes) + 18553, // compressed data size (bytes) kgspBinArchiveBooterUnloadUcode_GA102_image_dbg_data, // compressed data pointer NV_TRUE, // is pData compressed? NV_TRUE, // contain information for file overriding? @@ -519,8 +1231,8 @@ // static BINDATA_CONST NvU8 kgspBinArchiveBooterUnloadUcode_GA102_header_dbg_data[] = { - 0x63, 0x60, 0x00, 0x02, 0x46, 0x20, 0x96, 0x05, 0x62, 0x56, 0x08, 0x13, 0x4c, 0xc8, 0x40, 0x69, - 0x20, 0x00, 0x00, 0x8e, 0xa1, 0x42, 0xb2, 0x24, 0x00, 0x00, 0x00, + 0x63, 0x60, 0x00, 0x02, 0x46, 0x20, 0xf6, 0x02, 0x62, 0x5f, 0x08, 0x13, 0x4c, 0x78, 0x42, 0x69, + 0x20, 0x00, 0x00, 0x38, 0xcc, 0xda, 0x90, 0x24, 0x00, 0x00, 0x00, }; #endif // defined(BINDATA_INCLUDE_DATA) @@ -548,458 +1260,1171 @@ // VAR NAME: booter_ucode_data_ga10x // COMPRESSION: YES // COMPLEX_STRUCT: NO -// DATA SIZE (bytes): 8960 -// COMPRESSED SIZE (bytes): 7151 +// DATA SIZE (bytes): 38656 +// COMPRESSED SIZE (bytes): 18557 // static BINDATA_CONST NvU8 kgspBinArchiveBooterUnloadUcode_GA102_image_prod_data[] = { - 0xed, 0xd9, 0x43, 0x5c, 0x25, 0x80, 0xb7, 0xc0, 0xf1, 0xec, 0xc9, 0x9a, 0xcc, 0x9b, 0xad, 0xc9, - 0x9e, 0x78, 0xb3, 0xed, 0x9b, 0xed, 0x9a, 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0xfd, + 0xfa, 0xf5, 0xeb, 0xd7, 0xaf, 0x5f, 0xbf, 0x7e, 0xfd, 0xfa, 0xf5, 0xeb, 0xd7, 0xaf, 0x5f, 0xbf, + 0x7e, 0xfd, 0xfa, 0xf5, 0xeb, 0xd7, 0xaf, 0x5f, 0xbf, 0x7e, 0xfd, 0xfa, 0xf5, 0xeb, 0xd7, 0xaf, + 0x5f, 0xbf, 0x7e, 0xfd, 0xfa, 0xf5, 0xeb, 0xd7, 0xaf, 0x5f, 0xbf, 0x7e, 0xfd, 0xfa, 0xf5, 0xeb, + 0xd7, 0xaf, 0x5f, 0xbf, 0x7e, 0xfd, 0xfa, 0xf5, 0xeb, 0xd7, 0xaf, 0x5f, 0xbf, 0x7e, 0xfd, 0xfa, + 0xf5, 0xeb, 0xd7, 0xaf, 0x5f, 0xbf, 0x7e, 0xfd, 0xfa, 0xf5, 0xeb, 0xd7, 0xaf, 0x5f, 0xbf, 0x7e, + 0xfd, 0xdf, 0xe3, 0xff, 0x00, 0x10, 0xc2, 0x19, 0x87, 0x00, 0x97, 0x00, 0x00, }; #endif // defined(BINDATA_INCLUDE_DATA) @@ -1009,8 +2434,8 @@ #if defined(BINDATA_INCLUDE_STORAGE_PVT_DEFN) { - 8960, // uncompressed data size (bytes) - 7151, // compressed data size (bytes) + 38656, // uncompressed data size (bytes) + 18557, // compressed data size (bytes) kgspBinArchiveBooterUnloadUcode_GA102_image_prod_data, // compressed data pointer NV_TRUE, // is pData compressed? NV_TRUE, // contain information for file overriding? @@ -1032,8 +2457,8 @@ // static BINDATA_CONST NvU8 kgspBinArchiveBooterUnloadUcode_GA102_header_prod_data[] = { - 0x63, 0x60, 0x00, 0x02, 0x46, 0x20, 0x96, 0x05, 0x62, 0x56, 0x08, 0x13, 0x4c, 0xc8, 0x40, 0x69, - 0x20, 0x00, 0x00, 0x8e, 0xa1, 0x42, 0xb2, 0x24, 0x00, 0x00, 0x00, + 0x63, 0x60, 0x00, 0x02, 0x46, 0x20, 0xf6, 0x02, 0x62, 0x5f, 0x08, 0x13, 0x4c, 0x78, 0x42, 0x69, + 0x20, 0x00, 0x00, 0x38, 0xcc, 0xda, 0x90, 0x24, 0x00, 0x00, 0x00, }; #endif // defined(BINDATA_INCLUDE_DATA) @@ -1066,55 +2491,55 @@ // static BINDATA_CONST NvU8 kgspBinArchiveBooterUnloadUcode_GA102_sig_dbg_data[] = { - 0x01, 0x00, 0x03, 0xff, 0xfc, 0x77, 0x3d, 0x96, 0x96, 0xa6, 0xde, 0x8a, 0x3f, 0xda, 0x60, 0x62, - 0x3b, 0xf6, 0x5f, 0x56, 0x8d, 0xe8, 0xda, 0x1e, 0xdb, 0x7a, 0x29, 0xd6, 0xfd, 0x83, 0xeb, 0x43, - 0x65, 0x5b, 0x94, 0x0e, 0x90, 0x5e, 0x09, 0x1e, 0x7b, 0xd1, 0xdc, 0x70, 0xf1, 0x21, 0x7e, 0x26, - 0x2c, 0x0a, 0x9e, 0x13, 0x4e, 0xdf, 0xe9, 0x05, 0xec, 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0xe4, 0xf0, 0xf0, 0xd2, 0xf3, 0xf2, 0xff, 0xe1, 0xdf, 0x8f, 0xc4, + 0x4f, 0x2e, 0x9a, 0xcd, 0xd4, 0x77, 0x3b, 0x2c, 0xeb, 0xb1, 0xe5, 0xd6, 0x9a, 0x6b, 0xf6, 0x07, + 0xb9, 0xe4, 0x54, 0xb3, 0x2e, 0xf1, 0xf2, 0xb3, 0xc9, 0xcf, 0x53, 0xb9, 0xfa, 0xa0, 0x2a, 0x4d, + 0xae, 0x37, 0x73, 0xe3, 0x2f, 0x31, 0xcd, 0x87, 0x81, 0x9a, 0xbc, 0x5f, 0x03, 0x7f, 0x3d, 0x4d, + 0xaa, 0x36, 0xd0, 0x8d, 0x7a, 0x77, 0xfe, 0x0d, 0x53, 0x1e, 0xc7, 0xf3, 0x05, 0xef, 0xed, 0x7f, + 0x33, 0x3d, 0x60, 0x09, 0xf9, 0xb1, 0x63, 0x63, 0x99, 0x28, 0x9b, 0x7f, 0xd7, 0xea, 0x2b, 0xd2, + 0x19, 0x36, 0x4b, 0x36, 0x3c, 0x62, 0x18, 0x05, 0x03, 0x0a, 0x00, 0x9b, 0xe7, 0x55, 0xd9, 0x00, + 0x03, 0x00, 0x00, }; #endif // defined(BINDATA_INCLUDE_DATA) @@ -1184,7 +2609,7 @@ #if defined(BINDATA_INCLUDE_STORAGE_PVT_DEFN) { 768, // uncompressed data size (bytes) - 421, // compressed data size (bytes) + 419, // compressed data size (bytes) kgspBinArchiveBooterUnloadUcode_GA102_sig_prod_data, // compressed data pointer NV_TRUE, // is pData compressed? NV_TRUE, // contain information for file overriding? @@ -1206,7 +2631,7 @@ // static BINDATA_CONST NvU8 kgspBinArchiveBooterUnloadUcode_GA102_patch_loc_data[] = { - 0x10, 0x1d, 0x00, 0x00, + 0x10, 0x4a, 0x00, 0x00, }; #endif // defined(BINDATA_INCLUDE_DATA) diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/generated/g_bindata_kgspGetBinArchiveBooterUnloadUcode_TU102.c nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_bindata_kgspGetBinArchiveBooterUnloadUcode_TU102.c --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/generated/g_bindata_kgspGetBinArchiveBooterUnloadUcode_TU102.c 2023-10-25 20:19:26.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_bindata_kgspGetBinArchiveBooterUnloadUcode_TU102.c 2024-03-05 22:11:16.000000000 +0000 @@ -34,424 +34,1141 @@ // VAR NAME: booter_ucode_data_tu10x // COMPRESSION: YES // COMPLEX_STRUCT: NO -// DATA SIZE (bytes): 8192 -// COMPRESSED SIZE (bytes): 6600 +// DATA SIZE (bytes): 37888 +// COMPRESSED SIZE (bytes): 18073 // static BINDATA_CONST NvU8 kgspBinArchiveBooterUnloadUcode_TU102_image_dbg_data[] = { - 0xed, 0x99, 0x45, 0x50, 0x1c, 0x80, 0xd2, 0xad, 0x67, 0x06, 0x27, 0x78, 0x20, 0x78, 0x70, 0xf7, - 0x10, 0x5c, 0x43, 0x70, 0x77, 0x08, 0xee, 0x04, 0x08, 0x1e, 0x24, 0x10, 0x1c, 0x82, 0x4e, 0x70, - 0x97, 0x81, 0xe0, 0xee, 0xee, 0xee, 0x83, 0xcb, 0xe0, 0xee, 0x12, 0xdc, 0x06, 0x78, 0xf9, 0xb7, - 0x77, 0x77, 0xb7, 0xaf, 0xee, 0xb7, 0x39, 0xdd, 0x9b, 0xee, 0x5e, 0x74, 0x57, 0x9d, 0xaa, 0x0e, - 0x07, 0x00, 0x80, 0x2f, 0x09, 0x00, 0x5f, 0x6c, 0x00, 0xe0, 0x1e, 0x74, 0x0f, 0x78, 0x00, 0x81, - 0x01, 0x20, 0x40, 0xe7, 0xda, 0xfa, 0xeb, 0xeb, 0x2b, 0x76, 0x38, 0x00, 0x08, 0x78, 0x85, 0x20, - 0xd6, 0xee, 0x00, 0xb8, 0x53, 0x60, 0xc0, 0xda, 0x04, 0x00, 0x6b, 0x0a, 0x0c, 0xf4, 0x4f, 0xe8, - 0x52, 0x60, 0x08, 0xff, 0xe4, 0x7d, 0x38, 0x00, 0x00, 0x48, 0x81, 0x20, 0xd4, 0xaf, 0x23, 0x74, - 0x42, 0xb2, 0xd7, 0x53, 0x20, 0xc0, 0x94, 0x54, 0x50, 0xfd, 0x3a, 0xb0, 0x1e, 0x06, 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0x7e, 0xfd, 0xfa, 0xf5, 0xeb, 0xd7, 0xaf, 0x5f, + 0xbf, 0x7e, 0xfd, 0xfa, 0xf5, 0xeb, 0xd7, 0xaf, 0x5f, 0xbf, 0x7e, 0xfd, 0xfa, 0xf5, 0xeb, 0xd7, + 0xaf, 0x5f, 0xbf, 0x7e, 0xfd, 0xfa, 0xf5, 0xeb, 0xd7, 0xaf, 0x5f, 0xbf, 0x7e, 0xfd, 0xfa, 0xf5, + 0xeb, 0xd7, 0xaf, 0x5f, 0xbf, 0x7e, 0xfd, 0xfa, 0xf5, 0xeb, 0xd7, 0xaf, 0x5f, 0xbf, 0x7e, 0xfd, + 0xfa, 0xf5, 0xeb, 0xd7, 0xaf, 0x5f, 0xbf, 0x7e, 0xfd, 0xfa, 0xf5, 0xeb, 0xd7, 0xff, 0x4f, 0xfe, + 0x1f, 0x98, 0x1e, 0x1e, 0x2e, 0x00, 0x94, 0x00, 0x00, }; #endif // defined(BINDATA_INCLUDE_DATA) @@ -461,8 +1178,8 @@ #if defined(BINDATA_INCLUDE_STORAGE_PVT_DEFN) { - 8192, // uncompressed data size (bytes) - 6600, // compressed data size (bytes) + 37888, // uncompressed data size (bytes) + 18073, // compressed data size (bytes) kgspBinArchiveBooterUnloadUcode_TU102_image_dbg_data, // compressed data pointer NV_TRUE, // is pData compressed? NV_TRUE, // contain information for file overriding? @@ -484,8 +1201,8 @@ // static BINDATA_CONST NvU8 kgspBinArchiveBooterUnloadUcode_TU102_header_dbg_data[] = { - 0x63, 0x60, 0x00, 0x02, 0x46, 0x20, 0x96, 0x02, 0x62, 0x36, 0x08, 0x13, 0x4c, 0x48, 0x42, 0x69, - 0x20, 0x00, 0x00, 0x77, 0x72, 0x25, 0x67, 0x24, 0x00, 0x00, 0x00, + 0x63, 0x60, 0x00, 0x02, 0x46, 0x20, 0x76, 0x07, 0x62, 0x5f, 0x08, 0x13, 0x4c, 0xb8, 0x41, 0x69, + 0x20, 0x00, 0x00, 0x70, 0x9e, 0x6d, 0xce, 0x24, 0x00, 0x00, 0x00, }; #endif // defined(BINDATA_INCLUDE_DATA) @@ -513,424 +1230,1141 @@ // VAR NAME: booter_ucode_data_tu10x // COMPRESSION: YES // COMPLEX_STRUCT: NO -// DATA SIZE (bytes): 8192 -// COMPRESSED SIZE (bytes): 6599 +// DATA SIZE (bytes): 37888 +// COMPRESSED SIZE (bytes): 18074 // static BINDATA_CONST NvU8 kgspBinArchiveBooterUnloadUcode_TU102_image_prod_data[] = { - 0xed, 0x99, 0x45, 0x54, 0x1c, 0x8c, 0xce, 0x86, 0x87, 0xc1, 0x07, 0xca, 0xe0, 0x5a, 0x8a, 0x15, - 0x8a, 0xbb, 0xbb, 0x6b, 0x29, 0x32, 0x1d, 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0xbf, 0x7e, 0xfd, 0xfa, 0xf5, 0xeb, 0xd7, 0xaf, 0x5f, 0xbf, 0x7e, + 0xfd, 0xfa, 0xf5, 0xeb, 0xd7, 0xaf, 0x5f, 0xbf, 0x7e, 0xfd, 0xfa, 0xf5, 0xeb, 0xd7, 0xff, 0x4f, + 0xfe, 0x1f, 0x37, 0x09, 0x78, 0xe4, 0x00, 0x94, 0x00, 0x00, }; #endif // defined(BINDATA_INCLUDE_DATA) @@ -940,8 +2374,8 @@ #if defined(BINDATA_INCLUDE_STORAGE_PVT_DEFN) { - 8192, // uncompressed data size (bytes) - 6599, // compressed data size (bytes) + 37888, // uncompressed data size (bytes) + 18074, // compressed data size (bytes) kgspBinArchiveBooterUnloadUcode_TU102_image_prod_data, // compressed data pointer NV_TRUE, // is pData compressed? NV_TRUE, // contain information for file overriding? @@ -963,8 +2397,8 @@ // static BINDATA_CONST NvU8 kgspBinArchiveBooterUnloadUcode_TU102_header_prod_data[] = { - 0x63, 0x60, 0x00, 0x02, 0x46, 0x20, 0x96, 0x02, 0x62, 0x36, 0x08, 0x13, 0x4c, 0x48, 0x42, 0x69, - 0x20, 0x00, 0x00, 0x77, 0x72, 0x25, 0x67, 0x24, 0x00, 0x00, 0x00, + 0x63, 0x60, 0x00, 0x02, 0x46, 0x20, 0x76, 0x07, 0x62, 0x5f, 0x08, 0x13, 0x4c, 0xb8, 0x41, 0x69, + 0x20, 0x00, 0x00, 0x70, 0x9e, 0x6d, 0xce, 0x24, 0x00, 0x00, 0x00, }; #endif // defined(BINDATA_INCLUDE_DATA) @@ -997,7 +2431,7 @@ // static BINDATA_CONST NvU8 kgspBinArchiveBooterUnloadUcode_TU102_sig_dbg_data[] = { - 0x8d, 0xf3, 0xbb, 0x29, 0x1d, 0x0d, 0xac, 0xa0, 0xce, 0x43, 0xd8, 0xc5, 0x51, 0xb0, 0xd0, 0x9d, + 0xaa, 0x97, 0x88, 0x63, 0x77, 0x3e, 0x00, 0x58, 0xef, 0x0c, 0xd6, 0x33, 0x73, 0xda, 0xe5, 0x37, }; #endif // defined(BINDATA_INCLUDE_DATA) @@ -1030,7 +2464,7 @@ // static BINDATA_CONST NvU8 kgspBinArchiveBooterUnloadUcode_TU102_sig_prod_data[] = { - 0x5b, 0xe8, 0xcf, 0xaa, 0x40, 0x4a, 0x12, 0xff, 0xf0, 0xe8, 0x39, 0x5b, 0x2e, 0x44, 0x7a, 0x64, + 0x30, 0x82, 0x5a, 0x25, 0xb5, 0x02, 0xb7, 0x76, 0x45, 0xe1, 0xd6, 0x57, 0xb8, 0x1c, 0x3a, 0x7c, }; #endif // defined(BINDATA_INCLUDE_DATA) @@ -1063,7 +2497,7 @@ // static BINDATA_CONST NvU8 kgspBinArchiveBooterUnloadUcode_TU102_patch_loc_data[] = { - 0x00, 0x1c, 0x00, 0x00, + 0x00, 0x49, 0x00, 0x00, }; #endif // defined(BINDATA_INCLUDE_DATA) diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/generated/g_bindata_kgspGetBinArchiveBooterUnloadUcode_TU116.c nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_bindata_kgspGetBinArchiveBooterUnloadUcode_TU116.c --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/generated/g_bindata_kgspGetBinArchiveBooterUnloadUcode_TU116.c 2023-10-25 20:19:26.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_bindata_kgspGetBinArchiveBooterUnloadUcode_TU116.c 2024-03-05 22:11:16.000000000 +0000 @@ -34,424 +34,1140 @@ // VAR NAME: booter_ucode_data_tu11x // COMPRESSION: YES // COMPLEX_STRUCT: NO -// DATA SIZE (bytes): 8192 -// COMPRESSED SIZE (bytes): 6602 +// DATA SIZE (bytes): 37888 +// COMPRESSED SIZE (bytes): 18059 // static BINDATA_CONST NvU8 kgspBinArchiveBooterUnloadUcode_TU116_image_dbg_data[] = { - 0xed, 0x99, 0x45, 0x54, 0x1c, 0xd0, 0xd2, 0xad, 0x1b, 0x97, 0xe0, 0x2e, 0xc1, 0x82, 0x5b, 0x63, - 0xc1, 0xdd, 0x25, 0xb8, 0xbb, 0x06, 0x08, 0xee, 0x12, 0x5c, 0x83, 0x76, 0x70, 0x77, 0x68, 0xbc, - 0x71, 0x77, 0x97, 0x20, 0x8d, 0x5b, 0x90, 0xe0, 0x16, 0xdc, 0x9d, 0x97, 0x7f, 0x7a, 0x67, 0x77, - 0xfa, 0xd6, 0xfd, 0x26, 0xbb, 0xf6, 0xe4, 0xd4, 0x19, 0x54, 0xad, 0xb5, 0xcf, 0x3a, 0x51, 0x00, - 0x00, 0xcc, 0x5b, 0x32, 0x20, 0x00, 0x13, 0x00, 0x78, 0x80, 0x7d, 0x00, 0x3c, 0xc2, 0x82, 0x00, - 0xb0, 0x80, 0x9e, 0x8d, 0x3f, 0xef, 0xef, 0xef, 0x98, 0x51, 0x00, 0x18, 0xc0, 0x7b, 0x1e, 0x7c, - 0xc3, 0x2e, 0x80, 0x2b, 0x7d, 0x05, 0xa6, 0x21, 0x19, 0xc0, 0x92, 0xbe, 0x02, 0xfb, 0x4f, 0x68, - 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0xe0, 0xc7, 0x8f, 0x1f, 0x3f, 0x7e, 0xfc, 0xf8, + 0xf1, 0xe3, 0xc7, 0x8f, 0x1f, 0x3f, 0x7e, 0xfc, 0xf8, 0xf1, 0xe3, 0xc7, 0x8f, 0x1f, 0x3f, 0x7e, + 0xfc, 0xf8, 0xf1, 0xe3, 0xc7, 0x8f, 0x1f, 0x3f, 0x7e, 0xfc, 0xf8, 0xf1, 0xe3, 0xc7, 0x8f, 0x1f, + 0x3f, 0x7e, 0xfc, 0xf8, 0xf1, 0xe3, 0xc7, 0x8f, 0x1f, 0x3f, 0x7e, 0xfc, 0xf8, 0xf1, 0xe3, 0xc7, + 0x8f, 0x1f, 0x3f, 0x7e, 0xfc, 0xf8, 0xf1, 0xe3, 0xc7, 0x8f, 0x1f, 0x3f, 0x7e, 0xfc, 0xf8, 0xf1, + 0xe3, 0xc7, 0x8f, 0x1f, 0x3f, 0x7e, 0xfc, 0xf8, 0xf1, 0xe3, 0xc7, 0x8f, 0x1f, 0x3f, 0xfe, 0x7f, + 0xf2, 0x7f, 0x01, 0x06, 0x0a, 0xf9, 0x87, 0x00, 0x94, 0x00, 0x00, }; #endif // defined(BINDATA_INCLUDE_DATA) @@ -461,8 +1177,8 @@ #if defined(BINDATA_INCLUDE_STORAGE_PVT_DEFN) { - 8192, // uncompressed data size (bytes) - 6602, // compressed data size (bytes) + 37888, // uncompressed data size (bytes) + 18059, // compressed data size (bytes) kgspBinArchiveBooterUnloadUcode_TU116_image_dbg_data, // compressed data pointer NV_TRUE, // is pData compressed? NV_TRUE, // contain information for file overriding? @@ -484,8 +1200,8 @@ // static BINDATA_CONST NvU8 kgspBinArchiveBooterUnloadUcode_TU116_header_dbg_data[] = { - 0x63, 0x60, 0x00, 0x02, 0x46, 0x20, 0x96, 0x02, 0x62, 0x36, 0x08, 0x13, 0x4c, 0x48, 0x42, 0x69, - 0x20, 0x00, 0x00, 0x77, 0x72, 0x25, 0x67, 0x24, 0x00, 0x00, 0x00, + 0x63, 0x60, 0x00, 0x02, 0x46, 0x20, 0x76, 0x07, 0x62, 0x5f, 0x08, 0x13, 0x4c, 0xb8, 0x41, 0x69, + 0x20, 0x00, 0x00, 0x70, 0x9e, 0x6d, 0xce, 0x24, 0x00, 0x00, 0x00, }; #endif // defined(BINDATA_INCLUDE_DATA) @@ -513,424 +1229,1140 @@ // VAR NAME: booter_ucode_data_tu11x // COMPRESSION: YES // COMPLEX_STRUCT: NO -// DATA SIZE (bytes): 8192 -// COMPRESSED SIZE (bytes): 6594 +// DATA SIZE (bytes): 37888 +// COMPRESSED SIZE (bytes): 18059 // static BINDATA_CONST NvU8 kgspBinArchiveBooterUnloadUcode_TU116_image_prod_data[] = { - 0xed, 0x99, 0x45, 0x50, 0x1e, 0x8a, 0xce, 0x86, 0x3f, 0x83, 0xe2, 0x56, 0xa0, 0xb8, 0x7e, 0xb8, - 0xbb, 0x6b, 0x81, 0x22, 0xc5, 0xdd, 0xdd, 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0xdf, 0x7a, + 0xfa, 0xe6, 0x16, 0x07, 0xc2, 0x7a, 0xf3, 0x0a, 0x52, 0x43, 0xeb, 0xd4, 0xe3, 0xb4, 0xa8, 0x67, + 0x7e, 0x80, 0x2c, 0x80, 0xd4, 0x46, 0xf4, 0x4e, 0x40, 0x34, 0x7c, 0x80, 0xfd, 0xef, 0xa1, 0xb1, + 0x86, 0xf6, 0x42, 0x4b, 0xbf, 0x71, 0x2e, 0x59, 0x9a, 0x69, 0x32, 0xcc, 0xea, 0x33, 0xee, 0xf4, + 0x23, 0xfe, 0xc9, 0xee, 0xf6, 0x7a, 0xfe, 0x62, 0x56, 0xaa, 0x14, 0x5c, 0xd5, 0xa6, 0x01, 0xb4, + 0xf0, 0xc2, 0x06, 0xf1, 0x3b, 0x5e, 0x3f, 0x71, 0x14, 0xeb, 0x05, 0xe8, 0x60, 0xe8, 0x05, 0x02, + 0xbd, 0x16, 0x77, 0x6e, 0xd1, 0x4d, 0xb9, 0x2b, 0xac, 0xb7, 0x9c, 0xbb, 0x36, 0x99, 0x71, 0x11, + 0x11, 0x26, 0xe8, 0xb9, 0xca, 0x8a, 0x22, 0xed, 0xf6, 0x7c, 0x81, 0xda, 0x4e, 0x33, 0x45, 0x60, + 0x41, 0x0e, 0x90, 0x35, 0x3a, 0x09, 0x47, 0x40, 0xd0, 0x9d, 0x26, 0x05, 0x44, 0x4f, 0xed, 0x16, + 0x37, 0xa4, 0xec, 0x7a, 0x6a, 0x05, 0xf8, 0x8b, 0x1f, 0x93, 0x0f, 0x63, 0x00, 0x4a, 0x80, 0xbc, + 0x6f, 0xfb, 0x62, 0x3e, 0x19, 0x85, 0xa9, 0xe6, 0x0c, 0x63, 0xd8, 0x2d, 0xea, 0x7a, 0xb0, 0xc2, + 0x9c, 0x5a, 0x94, 0xf2, 0xbd, 0x5d, 0x9f, 0xca, 0x97, 0xbd, 0x02, 0xe2, 0x57, 0x51, 0xb6, 0x84, + 0xc6, 0x2b, 0xe6, 0xe6, 0xfc, 0x39, 0x11, 0x9a, 0x18, 0xe0, 0x76, 0x3f, 0x63, 0x6b, 0x16, 0xf2, + 0xea, 0xc1, 0xea, 0x7b, 0xa9, 0xcc, 0x88, 0x73, 0x58, 0x32, 0x54, 0x0a, 0x4c, 0x30, 0x05, 0xe4, + 0xae, 0x40, 0xa9, 0xef, 0x3f, 0x76, 0x32, 0x2f, 0x3a, 0xaf, 0x23, 0x75, 0x8d, 0x16, 0x12, 0xd3, + 0x7d, 0xff, 0x3d, 0xff, 0x78, 0x3d, 0x00, 0x94, 0xae, 0xc4, 0xa4, 0x1d, 0x0b, 0xff, 0x4e, 0x84, + 0x4b, 0xd5, 0x17, 0x0c, 0x7c, 0x3a, 0x61, 0x84, 0x75, 0xab, 0x8c, 0xfa, 0x79, 0x28, 0xc4, 0x1b, + 0xf4, 0x51, 0x52, 0xf9, 0x28, 0xd3, 0x3a, 0x0f, 0x0b, 0x22, 0x6a, 0x8a, 0x65, 0x50, 0xf9, 0x17, + 0x23, 0xce, 0x6a, 0x34, 0x7f, 0xe5, 0x26, 0xdf, 0xfc, 0xde, 0x1a, 0x02, 0xab, 0x81, 0x21, 0xe4, + 0x62, 0x92, 0xf2, 0x43, 0x0a, 0x7e, 0x66, 0x1f, 0x73, 0x1a, 0xbf, 0xa5, 0x61, 0x66, 0x15, 0x97, + 0xe2, 0x21, 0x99, 0x75, 0xd9, 0x96, 0x8c, 0xad, 0x6c, 0xa3, 0x71, 0xc1, 0xd8, 0x63, 0x31, 0x5a, + 0x3c, 0x18, 0xa6, 0xb5, 0x8e, 0x23, 0xf1, 0x06, 0x88, 0xb8, 0xf0, 0x01, 0xdc, 0x0c, 0x2f, 0xe1, + 0xbb, 0x07, 0x6d, 0x3a, 0xe9, 0xb6, 0x44, 0xf2, 0xe7, 0xf2, 0x30, 0x13, 0x40, 0x69, 0xcb, 0xa0, + 0x81, 0xdc, 0xe1, 0xa3, 0x81, 0xe2, 0x90, 0x91, 0x74, 0x29, 0x29, 0x25, 0x06, 0x29, 0xfc, 0x27, + 0x5e, 0x50, 0x0f, 0xab, 0xcd, 0x77, 0x35, 0xe5, 0x35, 0x0d, 0x6f, 0x79, 0x8b, 0xd5, 0x78, 0xe5, + 0x5e, 0x2e, 0xeb, 0xe1, 0x59, 0xac, 0x8e, 0x48, 0x93, 0x3c, 0x42, 0x4d, 0xaf, 0xde, 0xfa, 0x6a, + 0x21, 0x44, 0xad, 0x1b, 0xc0, 0xbc, 0x45, 0x70, 0x34, 0x18, 0x32, 0xcf, 0xcc, 0xbc, 0x01, 0x6f, + 0x00, 0xba, 0xf7, 0x40, 0xc0, 0xf1, 0x00, 0x43, 0xb9, 0x11, 0xbe, 0x1d, 0xce, 0x16, 0xb0, 0x4d, + 0x69, 0x74, 0x08, 0x60, 0x68, 0xd7, 0xf4, 0xdf, 0x61, 0xc3, 0x10, 0x79, 0xa8, 0xce, 0xe3, 0xfc, + 0x87, 0x00, 0xdf, 0xdd, 0x01, 0xf7, 0x37, 0x92, 0x3e, 0xe1, 0x48, 0xb7, 0x7b, 0x88, 0x07, 0x73, + 0x5a, 0xa8, 0x6e, 0x22, 0x34, 0xb8, 0x20, 0xf3, 0x82, 0x11, 0x0b, 0x09, 0x1e, 0xb1, 0xa1, 0xcc, + 0xdc, 0xe7, 0xd6, 0x64, 0x84, 0x6a, 0x63, 0x08, 0x40, 0xb7, 0x3f, 0x38, 0x9c, 0xf6, 0x2d, 0x95, + 0x4f, 0xb1, 0x6a, 0xc8, 0xf0, 0x6e, 0xc8, 0x27, 0xf9, 0x9b, 0x23, 0xd5, 0x58, 0x5a, 0x03, 0x50, + 0x7d, 0xfc, 0x96, 0x8f, 0xad, 0xa1, 0xc1, 0xca, 0x67, 0x7b, 0xce, 0x4b, 0xf0, 0x74, 0xb6, 0xe4, + 0x07, 0x4c, 0xf4, 0xa0, 0x28, 0x26, 0x56, 0x13, 0x0b, 0x87, 0x2f, 0x37, 0xe9, 0x3b, 0x1d, 0x39, + 0x82, 0xb5, 0xe6, 0x95, 0x78, 0x62, 0x88, 0xdd, 0xee, 0x44, 0xa4, 0xb3, 0x1b, 0xc1, 0xc8, 0x3f, + 0x9b, 0xfa, 0x87, 0x88, 0x82, 0xff, 0xaf, 0x63, 0x80, 0x5f, 0xbf, 0x7e, 0xfd, 0xfa, 0xf5, 0xeb, + 0xd7, 0xaf, 0x5f, 0xbf, 0x7e, 0xfd, 0xfa, 0xf5, 0xeb, 0xd7, 0xaf, 0x5f, 0xbf, 0x7e, 0xfd, 0xfa, + 0xf5, 0xeb, 0xd7, 0xaf, 0x5f, 0xbf, 0x7e, 0xfd, 0xfa, 0xf5, 0xeb, 0xd7, 0xaf, 0x5f, 0xbf, 0x7e, + 0xfd, 0xfa, 0xf5, 0xeb, 0xd7, 0xaf, 0x5f, 0xbf, 0x7e, 0xfd, 0xfa, 0xf5, 0xeb, 0xd7, 0xaf, 0x5f, + 0xbf, 0x7e, 0xfd, 0xfa, 0xf5, 0xeb, 0xd7, 0xaf, 0x5f, 0xbf, 0x7e, 0xfd, 0xfa, 0xf5, 0xeb, 0xd7, + 0xaf, 0x5f, 0xbf, 0x7e, 0xfd, 0xfa, 0xf5, 0xeb, 0xd7, 0xaf, 0x5f, 0xbf, 0x7e, 0xfd, 0xfa, 0xff, + 0xc9, 0xff, 0x05, 0x5a, 0x8d, 0x9f, 0x19, 0x00, 0x94, 0x00, 0x00, }; #endif // defined(BINDATA_INCLUDE_DATA) @@ -940,8 +2372,8 @@ #if defined(BINDATA_INCLUDE_STORAGE_PVT_DEFN) { - 8192, // uncompressed data size (bytes) - 6594, // compressed data size (bytes) + 37888, // uncompressed data size (bytes) + 18059, // compressed data size (bytes) kgspBinArchiveBooterUnloadUcode_TU116_image_prod_data, // compressed data pointer NV_TRUE, // is pData compressed? NV_TRUE, // contain information for file overriding? @@ -963,8 +2395,8 @@ // static BINDATA_CONST NvU8 kgspBinArchiveBooterUnloadUcode_TU116_header_prod_data[] = { - 0x63, 0x60, 0x00, 0x02, 0x46, 0x20, 0x96, 0x02, 0x62, 0x36, 0x08, 0x13, 0x4c, 0x48, 0x42, 0x69, - 0x20, 0x00, 0x00, 0x77, 0x72, 0x25, 0x67, 0x24, 0x00, 0x00, 0x00, + 0x63, 0x60, 0x00, 0x02, 0x46, 0x20, 0x76, 0x07, 0x62, 0x5f, 0x08, 0x13, 0x4c, 0xb8, 0x41, 0x69, + 0x20, 0x00, 0x00, 0x70, 0x9e, 0x6d, 0xce, 0x24, 0x00, 0x00, 0x00, }; #endif // defined(BINDATA_INCLUDE_DATA) @@ -997,7 +2429,7 @@ // static BINDATA_CONST NvU8 kgspBinArchiveBooterUnloadUcode_TU116_sig_dbg_data[] = { - 0xd2, 0xd7, 0x61, 0x5d, 0x7e, 0x54, 0x57, 0xef, 0xa8, 0xba, 0xb0, 0x6c, 0x4b, 0xf1, 0x2b, 0xbc, + 0x90, 0x8b, 0x47, 0x3e, 0x0f, 0xe9, 0xcf, 0x24, 0x6d, 0x88, 0xa2, 0x9d, 0x66, 0x30, 0x83, 0x68, }; #endif // defined(BINDATA_INCLUDE_DATA) @@ -1030,7 +2462,7 @@ // static BINDATA_CONST NvU8 kgspBinArchiveBooterUnloadUcode_TU116_sig_prod_data[] = { - 0x6b, 0x77, 0x25, 0x37, 0xf0, 0xfe, 0x01, 0x30, 0x26, 0xef, 0xb5, 0x87, 0x87, 0xff, 0x2c, 0x57, + 0x72, 0xcd, 0xc4, 0x54, 0x9c, 0xb0, 0x49, 0xf1, 0xb5, 0x5c, 0xb9, 0x11, 0xfd, 0x56, 0x92, 0xeb, }; #endif // defined(BINDATA_INCLUDE_DATA) @@ -1063,7 +2495,7 @@ // static BINDATA_CONST NvU8 kgspBinArchiveBooterUnloadUcode_TU116_patch_loc_data[] = { - 0x00, 0x1c, 0x00, 0x00, + 0x00, 0x49, 0x00, 0x00, }; #endif // defined(BINDATA_INCLUDE_DATA) diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/generated/g_bindata_kgspGetBinArchiveConcatenatedFMCDesc_GH100.c nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_bindata_kgspGetBinArchiveConcatenatedFMCDesc_GH100.c --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/generated/g_bindata_kgspGetBinArchiveConcatenatedFMCDesc_GH100.c 1970-01-01 00:00:00.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_bindata_kgspGetBinArchiveConcatenatedFMCDesc_GH100.c 2024-03-05 22:11:16.000000000 +0000 @@ -0,0 +1,98 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2016-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + + +/* THIS FILE IS AUTOMATICALLY GENERATED, DO NOT EDIT! */ + + + +#if defined(BINDATA_INCLUDE_DATA) +// +// FUNCTION: kgspGetBinArchiveConcatenatedFMCDesc_GH100("ucode_desc_prod") +// FILE NAME: kernel/inc/gspcc/bin/g_gsp_gh100_dyn_cc_prd_desc.bin +// FILE TYPE: BINARY +// VAR NAME: N/A +// COMPRESSION: YES +// COMPLEX_STRUCT: NO +// DATA SIZE (bytes): 84 +// COMPRESSED SIZE (bytes): 28 +// +static BINDATA_CONST NvU8 kgspBinArchiveConcatenatedFMCDesc_GH100_ucode_desc_prod_data[] = +{ + 0x63, 0x65, 0x20, 0x02, 0x70, 0x41, 0xf1, 0x32, 0x20, 0xde, 0x00, 0xc4, 0x37, 0x19, 0x19, 0x18, + 0xf1, 0xe8, 0x03, 0x00, 0x7f, 0x51, 0xb9, 0x4d, 0x54, 0x00, 0x00, 0x00, +}; +#endif // defined(BINDATA_INCLUDE_DATA) + +#if defined(BINDATA_INCLUDE_STORAGE_PVT_DECL) +BINDATA_STORAGE_PVT kgspBinArchiveConcatenatedFMCDesc_GH100_ucode_desc_prod_storage_pvt; +#endif // defined(BINDATA_INCLUDE_STORAGE_PVT_DECL) + +#if defined(BINDATA_INCLUDE_STORAGE_PVT_DEFN) +{ + 84, // uncompressed data size (bytes) + 28, // compressed data size (bytes) + kgspBinArchiveConcatenatedFMCDesc_GH100_ucode_desc_prod_data, // compressed data pointer + NV_TRUE, // is pData compressed? + NV_TRUE, // contain information for file overriding? + NV_FALSE, // is the data referenced during load? (Only valid when BINDATA_IS_MUTABLE is true) +}, +#endif // defined(BINDATA_INCLUDE_STORAGE_PVT_DEFN) + + +#if defined(BINDATA_INCLUDE_ARCHIVE) +// +// Bindata Archive structure +// +static const BINDATA_ARCHIVE __kgspGetBinArchiveConcatenatedFMCDesc_GH100 = +{ + 1, // entryNum + { + // entries[] : { "name", pBinStorage } + { "ucode_desc_prod" , (const PBINDATA_STORAGE) &g_bindata_pvt.kgspBinArchiveConcatenatedFMCDesc_GH100_ucode_desc_prod_storage_pvt }, + } +}; + +#endif // defined(BINDATA_INCLUDE_ARCHIVE) + + + +#if defined(BINDATA_INCLUDE_FUNCTION) +const BINDATA_ARCHIVE *kgspGetBinArchiveConcatenatedFMCDesc_GH100(struct KernelGsp *pKernelGsp) +{ + return &__kgspGetBinArchiveConcatenatedFMCDesc_GH100; +} +#endif // defined(BINDATA_INCLUDE_FUNCTION) + + +#if defined(BINDATA_INCLUDE_FUNCTION_STUB) +const BINDATA_ARCHIVE *kgspGetBinArchiveConcatenatedFMCDesc_GH100(struct KernelGsp *pKernelGsp) +{ + return NULL; +} +#endif // defined(BINDATA_INCLUDE_FUNCTION_STUB) + + + + + diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/generated/g_bindata_kgspGetBinArchiveConcatenatedFMC_GH100.c nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_bindata_kgspGetBinArchiveConcatenatedFMC_GH100.c --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/generated/g_bindata_kgspGetBinArchiveConcatenatedFMC_GH100.c 1970-01-01 00:00:00.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_bindata_kgspGetBinArchiveConcatenatedFMC_GH100.c 2024-03-05 22:11:17.000000000 +0000 @@ -0,0 +1,22776 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2016-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + + +/* THIS FILE IS AUTOMATICALLY GENERATED, DO NOT EDIT! */ + + + +#if defined(BINDATA_INCLUDE_DATA) +// +// FUNCTION: kgspGetBinArchiveConcatenatedFMC_GH100("ucode_image_prod") +// FILE NAME: kernel/inc/gspcc/bin/g_gsp_gh100_dyn_cc_concatenated_fmc_prod_image.bin +// FILE TYPE: BINARY +// VAR NAME: N/A +// COMPRESSION: YES +// COMPLEX_STRUCT: NO +// DATA SIZE (bytes): 368640 +// COMPRESSED SIZE (bytes): 362875 +// +static BINDATA_CONST NvU8 kgspBinArchiveConcatenatedFMC_GH100_ucode_image_prod_data[] = +{ + 0x9c, 0x97, 0xc3, 0x82, 0x28, 0x0a, 0x60, 0x43, 0xc7, 0xb6, 0x6d, 0xdb, 0xb6, 0x6d, 0xdb, 0xb6, + 0x6d, 0x5b, 0x77, 0x6c, 0xdb, 0xb6, 0x6d, 0xdb, 0xb6, 0x8d, 0xbe, 0x1f, 0x68, 0x17, 0xcd, 0x3a, + 0xdb, 0x9c, 0x24, 0xf3, 0x56, 0x0a, 0xa8, 0x28, 0x64, 0x8e, 0x5b, 0xeb, 0x9f, 0x25, 0x47, 0x28, + 0xc6, 0x16, 0x6f, 0xb6, 0x98, 0xd6, 0x71, 0x15, 0xb9, 0x4e, 0xed, 0x2c, 0x33, 0x49, 0x48, 0xd6, + 0x7d, 0x67, 0x49, 0xdd, 0x16, 0x7d, 0xaf, 0x65, 0xc8, 0xbf, 0x5d, 0x40, 0x68, 0xc4, 0x4c, 0x94, + 0x1c, 0x48, 0xc6, 0x8e, 0x43, 0x51, 0xd6, 0xc9, 0x47, 0x9b, 0x9d, 0xbe, 0xf6, 0x4c, 0xdc, 0xd4, + 0x9a, 0xba, 0xde, 0x39, 0x4b, 0x5e, 0xd8, 0x69, 0x92, 0xef, 0xc7, 0xbe, 0xbe, 0x49, 0x3b, 0x37, + 0xe7, 0xb3, 0x4c, 0x4d, 0xbe, 0x3f, 0x3f, 0x84, 0x81, 0xc0, 0xd0, 0x55, 0x8a, 0x35, 0xa8, 0x91, + 0x4a, 0xbe, 0x35, 0x8a, 0x67, 0xe8, 0xa5, 0x84, 0xcb, 0xf6, 0x3f, 0x8b, 0xa9, 0x5b, 0xd6, 0xd4, + 0x35, 0x9a, 0x72, 0xcc, 0xd1, 0x1b, 0xf3, 0x7e, 0x31, 0xe9, 0x56, 0xd5, 0x6c, 0x77, 0x2a, 0xfc, + 0x18, 0xcc, 0xa4, 0x94, 0xb0, 0xab, 0x95, 0x97, 0xd4, 0xc4, 0xa1, 0xab, 0xe6, 0x88, 0x30, 0x38, + 0xac, 0x8f, 0x87, 0x49, 0x47, 0x73, 0x36, 0xe0, 0x47, 0xd9, 0xe6, 0x91, 0xec, 0x73, 0x56, 0x1b, + 0x4f, 0xf8, 0x09, 0x44, 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0xe6, 0xaf, 0x20, 0x81, 0x11, 0x95, 0xb6, 0xd3, 0x48, 0x9d, 0xda, 0xd6, + 0x39, 0x90, 0xfa, 0x19, 0x57, 0x72, 0xee, 0x31, 0xda, 0xec, 0xcf, 0xf5, 0xbc, 0x93, 0xd7, 0xc6, + 0x75, 0xe1, 0x8e, 0x28, 0xbe, 0x0f, 0x55, 0x6e, 0x76, 0x74, 0x8f, 0x4f, 0x85, 0xc1, 0x20, 0x74, + 0xc5, 0x74, 0xcd, 0xa3, 0xe5, 0xc0, 0x12, 0x76, 0x8e, 0xa2, 0x6c, 0x8a, 0xa0, 0x79, 0x2a, 0xb6, + 0x6b, 0xb7, 0xfa, 0xbe, 0xc2, 0x69, 0x84, 0x40, 0x73, 0xbb, 0xd0, 0x3b, 0x38, 0x2c, 0x48, 0xe6, + 0xd4, 0x1a, 0xb2, 0xbb, 0xca, 0xb8, 0x43, 0x09, 0xcf, 0x04, 0xcf, 0x85, 0xd4, 0x25, 0xff, 0x5f, + 0x3a, 0x47, 0x2e, 0xe1, 0xb5, 0x9f, 0xfa, 0x65, 0xc2, 0xed, 0xb6, 0x90, 0xb6, 0x5a, 0xfc, 0xd7, + 0xec, 0xa6, 0xde, 0x43, 0x01, 0xd4, 0xa6, 0x72, 0x6c, 0x90, 0x89, 0x1d, 0xbe, 0x1d, 0x72, 0x34, + 0x26, 0x32, 0x0a, 0xaa, 0xac, 0xac, 0x7b, 0xa9, 0x1c, 0x61, 0x95, 0x97, 0xa1, 0xac, 0x67, 0xc9, + 0x0c, 0x0f, 0x9d, 0xec, 0x09, 0xac, 0x21, 0xfb, 0x08, 0x21, 0x8a, 0xf0, 0x1c, 0x33, 0x1c, 0x87, + 0x85, 0x4c, 0xfb, 0x8c, 0x73, 0x68, 0x5a, 0x00, 0xa0, 0x05, 0x00, +}; +#endif // defined(BINDATA_INCLUDE_DATA) + +#if defined(BINDATA_INCLUDE_STORAGE_PVT_DECL) +BINDATA_STORAGE_PVT kgspBinArchiveConcatenatedFMC_GH100_ucode_image_prod_storage_pvt; +#endif // defined(BINDATA_INCLUDE_STORAGE_PVT_DECL) + +#if defined(BINDATA_INCLUDE_STORAGE_PVT_DEFN) +{ + 368640, // uncompressed data size (bytes) + 362875, // compressed data size (bytes) + kgspBinArchiveConcatenatedFMC_GH100_ucode_image_prod_data, // compressed data pointer + NV_TRUE, // is pData compressed? + NV_TRUE, // contain information for file overriding? + NV_FALSE, // is the data referenced during load? (Only valid when BINDATA_IS_MUTABLE is true) +}, +#endif // defined(BINDATA_INCLUDE_STORAGE_PVT_DEFN) + + +#if defined(BINDATA_INCLUDE_ARCHIVE) +// +// Bindata Archive structure +// +static const BINDATA_ARCHIVE __kgspGetBinArchiveConcatenatedFMC_GH100 = +{ + 1, // entryNum + { + // entries[] : { "name", pBinStorage } + { "ucode_image_prod" , (const PBINDATA_STORAGE) &g_bindata_pvt.kgspBinArchiveConcatenatedFMC_GH100_ucode_image_prod_storage_pvt }, + } +}; + +#endif // defined(BINDATA_INCLUDE_ARCHIVE) + + + +#if defined(BINDATA_INCLUDE_FUNCTION) +const BINDATA_ARCHIVE *kgspGetBinArchiveConcatenatedFMC_GH100(struct KernelGsp *pKernelGsp) +{ + return &__kgspGetBinArchiveConcatenatedFMC_GH100; +} +#endif // defined(BINDATA_INCLUDE_FUNCTION) + + +#if defined(BINDATA_INCLUDE_FUNCTION_STUB) +const BINDATA_ARCHIVE *kgspGetBinArchiveConcatenatedFMC_GH100(struct KernelGsp *pKernelGsp) +{ + return NULL; +} +#endif // defined(BINDATA_INCLUDE_FUNCTION_STUB) + + + + + diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/generated/g_bindata_kgspGetBinArchiveGspRmBoot_AD102.c nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_bindata_kgspGetBinArchiveGspRmBoot_AD102.c --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/generated/g_bindata_kgspGetBinArchiveGspRmBoot_AD102.c 2023-10-25 20:19:26.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_bindata_kgspGetBinArchiveGspRmBoot_AD102.c 2024-03-05 22:11:17.000000000 +0000 @@ -34,1812 +34,1901 @@ // VAR NAME: N/A // COMPRESSION: YES // COMPLEX_STRUCT: NO -// DATA SIZE (bytes): 32768 -// COMPRESSED SIZE (bytes): 28813 +// DATA SIZE (bytes): 36864 +// COMPRESSED SIZE (bytes): 30240 // static BINDATA_CONST NvU8 kgspBinArchiveGspRmBoot_AD102_ucode_image_dbg_data[] = { - 0xed, 0xf7, 0x53, 0xb4, 0x6d, 0x4d, 0xd6, 0x2d, 0x8a, 0x4e, 0xdb, 0xb6, 0x6d, 0xdb, 0xb6, 0x6d, - 0xdb, 0xb6, 0x6d, 0xdb, 0x5c, 0xd3, 0xc6, 0x9a, 0xb6, 0x6d, 0xdb, 0xb6, 0x71, 0x32, 0xff, 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0xc1, 0x00, 0xd0, 0x12, 0x86, 0xd8, + 0xc3, 0x40, 0x10, 0xfe, 0x73, 0x05, 0xfe, 0xeb, 0xfa, 0xcf, 0xf3, 0x2f, 0xf8, 0xf7, 0xf3, 0x7f, + 0xf5, 0xf1, 0xcf, 0x3c, 0x81, 0xbf, 0xbc, 0x85, 0xa9, 0xd0, 0xfc, 0xd7, 0x58, 0x91, 0xff, 0x5c, + 0x99, 0x15, 0x12, 0x86, 0xd0, 0xff, 0xaa, 0x11, 0x64, 0x30, 0x32, 0x3e, 0x04, 0x23, 0x8c, 0x41, + 0x64, 0x70, 0x00, 0x98, 0xff, 0xb6, 0x0c, 0xce, 0xf7, 0x3f, 0x67, 0x87, 0x73, 0xe7, 0x18, 0x13, + 0x17, 0x80, 0x03, 0x44, 0x18, 0x11, 0xb9, 0xff, 0xb3, 0xdf, 0x3c, 0xff, 0xac, 0xdc, 0x81, 0xf0, + 0x7f, 0x3f, 0xbf, 0xff, 0x47, 0x26, 0x4f, 0xb8, 0xfe, 0xeb, 0x84, 0xfa, 0x7b, 0x47, 0x86, 0x00, + 0x00, 0x54, 0xe0, 0x2e, 0x45, 0x69, 0x50, 0xf2, 0x95, 0x00, 0xff, 0xbf, 0x9c, 0x73, 0x40, 0xff, + 0x77, 0x1e, 0xa2, 0xff, 0x05, 0x84, 0xbf, 0xc9, 0xe0, 0xbf, 0x23, 0xc0, 0xf8, 0x87, 0xff, 0xbb, + 0x4f, 0xf0, 0x77, 0x83, 0xe0, 0xff, 0x9c, 0x63, 0x60, 0x00, 0xf0, 0x3f, 0x44, 0x83, 0x80, 0xff, + 0xd9, 0xff, 0xaf, 0x06, 0xc8, 0xdf, 0x4d, 0x8a, 0x7f, 0x0c, 0x41, 0xfc, 0xff, 0x16, 0xdf, 0x7f, + 0xcf, 0x07, 0xff, 0x6f, 0x1d, 0xe3, 0x7f, 0xe8, 0x80, 0xc0, 0xff, 0x23, 0xbe, 0xff, 0x15, 0x0f, + 0xc8, 0xff, 0xd4, 0x0d, 0xfe, 0x5b, 0x07, 0x06, 0xff, 0x3f, 0xf5, 0xff, 0x1d, 0x2f, 0xe8, 0xff, + 0x1a, 0x4f, 0xf0, 0x3f, 0xe2, 0x06, 0xfa, 0x1f, 0x76, 0xfe, 0x1f, 0x04, 0x40, 0xa0, 0x9f, 0x9f, + 0x1f, 0x60, 0xa2, 0x9f, 0x7f, 0xf0, 0xff, 0x6f, 0xf3, 0x10, 0x20, 0x88, 0xff, 0x21, 0x02, 0x16, + 0x90, 0xa0, 0xff, 0x62, 0x00, 0xa8, 0xff, 0x92, 0x09, 0x0c, 0xd0, 0xfe, 0xd6, 0x5f, 0x03, 0xfe, + 0x66, 0x11, 0x80, 0xbf, 0x59, 0xe0, 0x1f, 0x26, 0xa9, 0xc0, 0xff, 0x2f, 0xa6, 0xf8, 0x87, 0x0b, + 0xfe, 0x41, 0xb3, 0x01, 0x16, 0x3b, 0x61, 0x1d, 0xd7, 0x26, 0x00, 0xe8, 0xdf, 0xe3, 0x40, 0xfe, + 0x61, 0x9a, 0xff, 0xee, 0xff, 0xe3, 0xcf, 0x01, 0xf5, 0x6f, 0x76, 0xf9, 0x87, 0x3d, 0xfe, 0xe1, + 0xff, 0x15, 0x98, 0xc8, 0xdf, 0xf5, 0x05, 0x01, 0xf8, 0x77, 0xfd, 0xfd, 0xbf, 0xad, 0x3f, 0xe1, + 0x9f, 0xdf, 0x5f, 0x70, 0xf8, 0x9f, 0xb5, 0xf4, 0x2f, 0xfe, 0xc5, 0xbf, 0xf8, 0x17, 0xff, 0xe2, + 0x5f, 0xfc, 0x8b, 0xff, 0x9b, 0xf0, 0x7f, 0x01, 0xae, 0xaa, 0xb4, 0x20, 0x00, 0x90, 0x00, 0x00, }; #endif // defined(BINDATA_INCLUDE_DATA) @@ -1849,8 +1938,8 @@ #if defined(BINDATA_INCLUDE_STORAGE_PVT_DEFN) { - 32768, // uncompressed data size (bytes) - 28813, // compressed data size (bytes) + 36864, // uncompressed data size (bytes) + 30240, // compressed data size (bytes) kgspBinArchiveGspRmBoot_AD102_ucode_image_dbg_data, // compressed data pointer NV_TRUE, // is pData compressed? NV_TRUE, // contain information for file overriding? @@ -1868,13 +1957,13 @@ // COMPRESSION: YES // COMPLEX_STRUCT: NO // DATA SIZE (bytes): 84 -// COMPRESSED SIZE (bytes): 43 +// COMPRESSED SIZE (bytes): 42 // static BINDATA_CONST NvU8 kgspBinArchiveGspRmBoot_AD102_ucode_desc_dbg_data[] = { - 0x63, 0x65, 0x00, 0x82, 0x02, 0x06, 0x86, 0x08, 0x16, 0x20, 0x2e, 0x61, 0x60, 0x10, 0x60, 0xc0, - 0x02, 0x38, 0xa0, 0xd8, 0x01, 0x88, 0x3d, 0x80, 0x58, 0x95, 0x81, 0x81, 0x11, 0x9b, 0xba, 0x06, - 0x88, 0x20, 0x00, 0x06, 0x3c, 0x73, 0x3c, 0x54, 0x00, 0x00, 0x00, + 0x63, 0x65, 0x00, 0x82, 0x06, 0x20, 0xe2, 0x00, 0xe2, 0x0e, 0x06, 0x06, 0x01, 0x06, 0x2c, 0x80, + 0x03, 0x8a, 0x1d, 0x80, 0xd8, 0x03, 0x88, 0x35, 0x19, 0x18, 0x18, 0xb1, 0xa9, 0x9b, 0x00, 0x11, + 0x04, 0x00, 0x6d, 0xde, 0x74, 0xe4, 0x54, 0x00, 0x00, 0x00, }; #endif // defined(BINDATA_INCLUDE_DATA) @@ -1885,7 +1974,7 @@ #if defined(BINDATA_INCLUDE_STORAGE_PVT_DEFN) { 84, // uncompressed data size (bytes) - 43, // compressed data size (bytes) + 42, // compressed data size (bytes) kgspBinArchiveGspRmBoot_AD102_ucode_desc_dbg_data, // compressed data pointer NV_TRUE, // is pData compressed? NV_TRUE, // contain information for file overriding? @@ -1902,1812 +1991,1901 @@ // VAR NAME: N/A // COMPRESSION: YES // COMPLEX_STRUCT: NO -// DATA SIZE (bytes): 32768 -// COMPRESSED SIZE (bytes): 28812 +// DATA SIZE (bytes): 36864 +// COMPRESSED SIZE (bytes): 30239 // static BINDATA_CONST NvU8 kgspBinArchiveGspRmBoot_AD102_ucode_image_prod_data[] = { - 0xed, 0xf7, 0x53, 0xb4, 0x70, 0xbb, 0xd6, 0x2d, 0x00, 0x2e, 0xdb, 0xb6, 0x6d, 0xdb, 0xf6, 0xfa, - 0x96, 0x6d, 0xdb, 0xb6, 0xf5, 0x2d, 0xdb, 0xb6, 0x6d, 0xdb, 0xb6, 0x6d, 0xdb, 0xb5, 0xff, 0xbb, - 0xcf, 0xbd, 0xb7, 0xaa, 0x5a, 0xbd, 0x55, 0xbd, 0xd5, 0xe9, 0xad, 0xcd, 0xf4, 0x64, 0x64, 0x20, - 0xc9, 0x98, 0x99, 0x33, 0x39, 0xbb, 0xb1, 0xa3, 0x4f, 0xe1, 0xbe, 0xb7, 0x03, 0x83, 0x3f, 0x00, - 0x6d, 0x76, 0x68, 0xf1, 0xbb, 0x1c, 0x29, 0xe2, 0xc3, 0x74, 0x08, 0xde, 0xdc, 0xef, 0xd7, 0x9d, - 0x4a, 0x30, 0x2f, 0xb0, 0xed, 0x62, 0x38, 0x6a, 0x92, 0x97, 0x56, 0x34, 0x86, 0x7f, 0x78, 0xcc, - 0xf2, 0xd4, 0xda, 0x72, 0x4e, 0xe5, 0x9a, 0x2a, 0xd4, 0x00, 0x60, 0x45, 0xd0, 0xdb, 0x42, 0x79, - 0x7e, 0x58, 0x0f, 0x01, 0xfe, 0x28, 0x08, 0xa2, 0x77, 0x6d, 0x62, 0x04, 0x6d, 0xe3, 0x74, 0x9d, - 0x10, 0x61, 0x03, 0x0c, 0x1b, 0x6d, 0x12, 0xd9, 0xd3, 0x4d, 0x9d, 0x59, 0x98, 0x72, 0x3a, 0x96, - 0xe0, 0x6d, 0x06, 0x2b, 0xce, 0x1a, 0x0f, 0x6c, 0xff, 0x8b, 0x38, 0xbc, 0x19, 0x6d, 0x89, 0x06, - 0x1c, 0xe3, 0x75, 0xd8, 0xab, 0x52, 0x6c, 0x42, 0xd0, 0x1d, 0x7b, 0x79, 0xcb, 0xff, 0x48, 0x13, - 0x7e, 0xf9, 0xb6, 0x08, 0x8a, 0x3e, 0xca, 0x65, 0x79, 0x39, 0x9f, 0xd0, 0xab, 0xd5, 0xcd, 0xe7, - 0x20, 0x76, 0xe1, 0xaa, 0x39, 0xa3, 0xd6, 0x05, 0x52, 0x14, 0x2b, 0xce, 0xc1, 0xfb, 0xd2, 0xab, - 0x98, 0x68, 0xd3, 0x8c, 0x15, 0x8c, 0x92, 0xc5, 0x3f, 0x6b, 0x85, 0xb3, 0xa2, 0x6d, 0xc3, 0x70, - 0x6b, 0x17, 0xca, 0xf7, 0x6b, 0xd6, 0x53, 0x14, 0x63, 0x46, 0x2e, 0xe5, 0x35, 0x9d, 0xf5, 0x34, - 0xc3, 0xf0, 0xf6, 0xc9, 0x99, 0xe4, 0xc7, 0x1a, 0x06, 0xca, 0xee, 0x88, 0x4f, 0xc0, 0x91, 0x06, - 0x0a, 0x0b, 0x8a, 0xfe, 0xb8, 0xa0, 0xf3, 0x2e, 0xd1, 0xf2, 0xdb, 0x59, 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0x30, 0x40, 0xfb, 0x5b, 0x7f, 0xf5, 0xff, 0x9b, + 0x45, 0x00, 0xfe, 0x66, 0x81, 0x7f, 0x98, 0xa4, 0x1c, 0xff, 0xbf, 0x98, 0xe2, 0x1f, 0xce, 0xff, + 0x07, 0x4d, 0x06, 0x58, 0xec, 0x84, 0xb5, 0x5c, 0x5b, 0x00, 0xa0, 0x7f, 0xcf, 0x03, 0xf9, 0x87, + 0x69, 0xfe, 0xdb, 0xfe, 0x27, 0x9f, 0x3d, 0xea, 0xdf, 0xec, 0xfc, 0x0f, 0xbb, 0xff, 0xc3, 0xff, + 0xab, 0x30, 0x91, 0xbf, 0xfb, 0x0b, 0x02, 0xf0, 0xef, 0xfe, 0xfb, 0x7f, 0x5b, 0x7f, 0xfc, 0x3f, + 0xbf, 0xbf, 0x60, 0xff, 0x3f, 0x7b, 0xe9, 0x5f, 0xfc, 0x8b, 0x7f, 0xf1, 0x2f, 0xfe, 0xc5, 0xbf, + 0xf8, 0x17, 0xff, 0x37, 0xe1, 0xff, 0x02, 0x26, 0x6a, 0xed, 0xd5, 0x00, 0x90, 0x00, 0x00, }; #endif // defined(BINDATA_INCLUDE_DATA) @@ -3717,8 +3895,8 @@ #if defined(BINDATA_INCLUDE_STORAGE_PVT_DEFN) { - 32768, // uncompressed data size (bytes) - 28812, // compressed data size (bytes) + 36864, // uncompressed data size (bytes) + 30239, // compressed data size (bytes) kgspBinArchiveGspRmBoot_AD102_ucode_image_prod_data, // compressed data pointer NV_TRUE, // is pData compressed? NV_TRUE, // contain information for file overriding? @@ -3736,13 +3914,13 @@ // COMPRESSION: YES // COMPLEX_STRUCT: NO // DATA SIZE (bytes): 84 -// COMPRESSED SIZE (bytes): 43 +// COMPRESSED SIZE (bytes): 42 // static BINDATA_CONST NvU8 kgspBinArchiveGspRmBoot_AD102_ucode_desc_prod_data[] = { - 0x63, 0x65, 0x00, 0x82, 0x02, 0x06, 0x86, 0x08, 0x16, 0x20, 0x2e, 0x61, 0x60, 0x10, 0x60, 0xc0, - 0x02, 0x38, 0xa0, 0xd8, 0x01, 0x88, 0x3d, 0x80, 0x58, 0x95, 0x81, 0x81, 0x11, 0x9b, 0xba, 0x06, - 0x88, 0x20, 0x00, 0x06, 0x3c, 0x73, 0x3c, 0x54, 0x00, 0x00, 0x00, + 0x63, 0x65, 0x00, 0x82, 0x06, 0x20, 0xe2, 0x00, 0xe2, 0x0e, 0x06, 0x06, 0x01, 0x06, 0x2c, 0x80, + 0x03, 0x8a, 0x1d, 0x80, 0xd8, 0x03, 0x88, 0x35, 0x19, 0x18, 0x18, 0xb1, 0xa9, 0x9b, 0x00, 0x11, + 0x04, 0x00, 0x6d, 0xde, 0x74, 0xe4, 0x54, 0x00, 0x00, 0x00, }; #endif // defined(BINDATA_INCLUDE_DATA) @@ -3753,7 +3931,7 @@ #if defined(BINDATA_INCLUDE_STORAGE_PVT_DEFN) { 84, // uncompressed data size (bytes) - 43, // compressed data size (bytes) + 42, // compressed data size (bytes) kgspBinArchiveGspRmBoot_AD102_ucode_desc_prod_data, // compressed data pointer NV_TRUE, // is pData compressed? NV_TRUE, // contain information for file overriding? diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/generated/g_bindata_kgspGetBinArchiveGspRmBoot_GA102.c nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_bindata_kgspGetBinArchiveGspRmBoot_GA102.c --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/generated/g_bindata_kgspGetBinArchiveGspRmBoot_GA102.c 2023-10-25 20:19:26.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_bindata_kgspGetBinArchiveGspRmBoot_GA102.c 2024-03-05 22:11:17.000000000 +0000 @@ -29,476 +29,1137 @@ #if defined(BINDATA_INCLUDE_DATA) // // FUNCTION: kgspGetBinArchiveGspRmBoot_GA102("ucode_image_dbg") -// FILE NAME: kernel/inc/gsprm/bin/g_gsprm_skbl_dbg_ga102_riscv_image.bin +// FILE NAME: kernel/inc/gsprm/bin/g_gsprm_skbl_dbg_libos3_ga102_riscv_image.bin // FILE TYPE: BINARY // VAR NAME: N/A // COMPRESSION: YES // COMPLEX_STRUCT: NO -// DATA SIZE (bytes): 12288 -// COMPRESSED SIZE (bytes): 7350 +// DATA SIZE (bytes): 24576 +// COMPRESSED SIZE (bytes): 17932 // static BINDATA_CONST NvU8 kgspBinArchiveGspRmBoot_GA102_ucode_image_dbg_data[] = { - 0xed, 0x97, 0x67, 0x54, 0x53, 0x5d, 0xb3, 0xc7, 0x13, 0x02, 0x24, 0x14, 0x21, 0x74, 0xa4, 0x28, - 0x84, 0x0e, 0x2a, 0xa8, 0xf4, 0x5e, 0xa4, 0x89, 0x34, 0x41, 0x40, 0x41, 0x5a, 0x68, 0x02, 0xd2, - 0x3b, 0x48, 0x0f, 0xa1, 0xb7, 0x00, 0x01, 0x69, 0x52, 0x05, 0xa4, 0xf7, 0x26, 0x2d, 0x34, 0x95, - 0xa6, 0x34, 0x41, 0x7a, 0x47, 0x40, 0x3a, 0x12, 0x9a, 0x57, 0x1f, 0x78, 0xde, 0xfb, 0x7e, 0xbc, - 0xdf, 0xaf, 0xff, 0xb5, 0xb2, 0x7e, 0x39, 0x33, 0x73, 0xf6, 0xec, 0x99, 0x35, 0x7b, 0xaf, 0x75, - 0x94, 0xfa, 0xef, 0x8f, 0x04, 0x25, 0x01, 0x88, 0x92, 0x2a, 0xdc, 0x96, 0x22, 0xc1, 0x35, 0xf6, - 0x13, 0xcf, 0x78, 0x89, 0x13, 0xe2, 0x79, 0x96, 0xd0, 0xaa, 0x9d, 0x1c, 0x77, 0x8a, 0x19, 0x8b, - 0x1d, 0xd6, 0x6a, 0xb0, 0x2f, 0xf2, 0x88, 0x72, 0xf2, 0x97, 0x7a, 0x0a, 0xf1, 0x35, 0x86, 0xa1, - 0x3e, 0x64, 0xc4, 0x04, 0xb1, 0x3a, 0x5f, 0x6b, 0xc5, 0x6f, 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0x18, + 0x7f, 0xf8, 0xdf, 0x36, 0xc1, 0xef, 0x01, 0xc1, 0xff, 0xf4, 0xd1, 0xd3, 0x03, 0xf8, 0x0f, 0x51, + 0xcf, 0xef, 0x3f, 0xed, 0x7f, 0x0d, 0x40, 0x7e, 0x0f, 0x29, 0xfe, 0x04, 0x82, 0xf8, 0xff, 0x56, + 0xdf, 0xbf, 0xfd, 0xc1, 0xff, 0xad, 0x63, 0xfc, 0x87, 0x0e, 0x08, 0xfc, 0x1f, 0xf5, 0xfd, 0x57, + 0x3d, 0x20, 0xff, 0xa9, 0xeb, 0xfd, 0x5b, 0x07, 0x06, 0xff, 0x9f, 0xfa, 0x7f, 0xd7, 0x0b, 0xfa, + 0x5f, 0xf3, 0x09, 0xfe, 0xa3, 0x6e, 0xa0, 0xff, 0x88, 0xf3, 0x7f, 0x10, 0x00, 0x81, 0xbe, 0xbe, + 0xbe, 0x80, 0x89, 0xbe, 0xfe, 0xe0, 0xff, 0xef, 0xf0, 0x10, 0x20, 0x88, 0x7f, 0x13, 0x01, 0x33, + 0x48, 0xc0, 0xbf, 0x18, 0x00, 0xea, 0x5f, 0x32, 0x81, 0x1e, 0xda, 0x6f, 0xfd, 0xd9, 0xef, 0x37, + 0x0b, 0x03, 0xfc, 0x66, 0xfe, 0x3f, 0x4c, 0x52, 0x8a, 0xff, 0x2f, 0xa6, 0xf8, 0xc3, 0x79, 0x7f, + 0xd0, 0xa0, 0x87, 0xc5, 0x46, 0x58, 0xcd, 0xb9, 0x0e, 0x00, 0xfa, 0x7b, 0x1e, 0xc8, 0x1f, 0xa6, + 0xfe, 0xb7, 0xfd, 0x27, 0x9f, 0x1d, 0xea, 0x6f, 0x76, 0xfa, 0xc3, 0x6e, 0x7f, 0xf8, 0xbf, 0x0a, + 0x43, 0xf9, 0xdd, 0x5f, 0x10, 0x80, 0xbf, 0xfb, 0xef, 0xff, 0xb6, 0x7e, 0xbd, 0x3f, 0xbf, 0xbf, + 0x60, 0xf7, 0x9f, 0xbd, 0xf4, 0x0f, 0xfe, 0xc1, 0x3f, 0xf8, 0x07, 0xff, 0xe0, 0x1f, 0xfc, 0x83, + 0xff, 0x4d, 0xf8, 0x5f, 0x03, 0xac, 0xbc, 0x95, 0x00, 0x60, 0x00, 0x00, }; #endif // defined(BINDATA_INCLUDE_DATA) @@ -508,8 +1169,8 @@ #if defined(BINDATA_INCLUDE_STORAGE_PVT_DEFN) { - 12288, // uncompressed data size (bytes) - 7350, // compressed data size (bytes) + 24576, // uncompressed data size (bytes) + 17932, // compressed data size (bytes) kgspBinArchiveGspRmBoot_GA102_ucode_image_dbg_data, // compressed data pointer NV_TRUE, // is pData compressed? NV_TRUE, // contain information for file overriding? @@ -521,19 +1182,19 @@ #if defined(BINDATA_INCLUDE_DATA) // // FUNCTION: kgspGetBinArchiveGspRmBoot_GA102("ucode_desc_dbg") -// FILE NAME: kernel/inc/gsprm/bin/g_gsprm_skbl_dbg_ga102_riscv_desc.bin +// FILE NAME: kernel/inc/gsprm/bin/g_gsprm_skbl_dbg_libos3_ga102_riscv_desc.bin // FILE TYPE: BINARY // VAR NAME: N/A // COMPRESSION: YES // COMPLEX_STRUCT: NO -// DATA SIZE (bytes): 76 -// COMPRESSED SIZE (bytes): 40 +// DATA SIZE (bytes): 84 +// COMPRESSED SIZE (bytes): 42 // static BINDATA_CONST NvU8 kgspBinArchiveGspRmBoot_GA102_ucode_desc_dbg_data[] = { - 0x63, 0x61, 0x00, 0x02, 0x05, 0x06, 0x86, 0x0d, 0xac, 0x40, 0xac, 0xca, 0xc0, 0x20, 0xc0, 0x80, - 0x05, 0x70, 0x40, 0x31, 0x33, 0x10, 0x73, 0x03, 0x31, 0x2f, 0x03, 0x03, 0x23, 0x16, 0x75, 0x00, - 0x8d, 0x26, 0xa8, 0x4f, 0x4c, 0x00, 0x00, 0x00, + 0x63, 0x65, 0x00, 0x82, 0x00, 0x06, 0x86, 0x06, 0x0e, 0x20, 0x8e, 0x60, 0x60, 0x10, 0x60, 0xc0, + 0x02, 0x38, 0xa0, 0x18, 0x24, 0x29, 0x01, 0xc4, 0x9a, 0x0c, 0x0c, 0x8c, 0xd8, 0xd4, 0x25, 0x40, + 0x04, 0x01, 0xd4, 0x4b, 0xa9, 0xea, 0x54, 0x00, 0x00, 0x00, }; #endif // defined(BINDATA_INCLUDE_DATA) @@ -543,8 +1204,8 @@ #if defined(BINDATA_INCLUDE_STORAGE_PVT_DEFN) { - 76, // uncompressed data size (bytes) - 40, // compressed data size (bytes) + 84, // uncompressed data size (bytes) + 42, // compressed data size (bytes) kgspBinArchiveGspRmBoot_GA102_ucode_desc_dbg_data, // compressed data pointer NV_TRUE, // is pData compressed? NV_TRUE, // contain information for file overriding? @@ -556,475 +1217,1137 @@ #if defined(BINDATA_INCLUDE_DATA) // // FUNCTION: kgspGetBinArchiveGspRmBoot_GA102("ucode_image_prod") -// FILE NAME: kernel/inc/gsprm/bin/g_gsprm_skbl_prod_ga102_riscv_image.bin +// FILE NAME: kernel/inc/gsprm/bin/g_gsprm_skbl_prod_libos3_ga102_riscv_image.bin // FILE TYPE: BINARY // VAR NAME: N/A // COMPRESSION: YES // COMPLEX_STRUCT: NO -// DATA SIZE (bytes): 12288 -// COMPRESSED SIZE (bytes): 7340 +// DATA SIZE (bytes): 24576 +// COMPRESSED SIZE (bytes): 17934 // static BINDATA_CONST NvU8 kgspBinArchiveGspRmBoot_GA102_ucode_image_prod_data[] = { - 0xed, 0x94, 0x75, 0x54, 0xd4, 0x5d, 0xb7, 0xc7, 0x27, 0x80, 0x01, 0xa4, 0xbb, 0x5b, 0x1a, 0xa4, - 0xbb, 0x5b, 0x1a, 0x41, 0x42, 0x9a, 0x01, 0x86, 0x52, 0x4a, 0xba, 0x73, 0xe8, 0x8e, 0x91, 0x50, - 0xba, 0x41, 0x1a, 0x29, 0x69, 0x09, 0x01, 0x25, 0xa4, 0xa4, 0x5b, 0x4a, 0x52, 0x42, 0x81, 0xab, - 0x0f, 0x3c, 0xef, 0x7d, 0xff, 0xbc, 0xff, 0x5f, 0xbf, 0x6b, 0xcd, 0xfa, 0xcc, 0xd9, 0x7b, 0xff, - 0xce, 0x3e, 0x7b, 0xaf, 0x7d, 0x8e, 0x12, 0xcd, 0x1b, 0xbf, 0xa8, 0x92, 0x66, 0x03, 0xcd, 0xf8, - 0x8a, 0x67, 0xc8, 0x5b, 0x74, 0xb8, 0xad, 0x3c, 0x82, 0xb9, 0xd4, 0x2b, 0x3c, 0xde, 0xd4, 0xfb, - 0xc2, 0x0b, 0x2d, 0x92, 0x07, 0x6f, 0x2a, 0xf3, 0x59, 0x91, 0xe8, 0x62, 0x9d, 0xf7, 0x7b, 0x6e, - 0x6f, 0xce, 0x21, 0xce, 0x2b, 0xfe, 0xe7, 0xb2, 0xd9, 0x2f, 0xc0, 0x53, 0x59, 0x61, 0x3d, 0x8c, - 0x97, 0x25, 0x0f, 0x20, 0x06, 0x4f, 0xa8, 0xd0, 0x08, 0x65, 0x2a, 0x9d, 0x78, 0xce, 0x15, 0x11, - 0x7b, 0x2a, 0x56, 0xc7, 0x0d, 0x27, 0xc0, 0x6e, 0x75, 0x92, 0x5a, 0x63, 0x1a, 0x59, 0xd5, 0x87, - 0xcd, 0x51, 0xf6, 0x0d, 0x2a, 0x79, 0xc8, 0xdb, 0x39, 0xda, 0x01, 0x18, 0x8a, 0x95, 0x21, 0x2c, - 0x30, 0xb8, 0x4a, 0x85, 0x1f, 0xcb, 0x3b, 0xaf, 0x51, 0xb5, 0x78, 0xa3, 0x97, 0x1a, 0xd0, 0xa3, - 0xcc, 0x89, 0x14, 0x74, 0x0a, 0x9d, 0x12, 0x52, 0xd4, 0xef, 0x92, 0x1f, 0x56, 0xd4, 0x50, 0xd8, - 0x0f, 0xd3, 0x84, 0x14, 0x7e, 0x6e, 0x99, 0xe0, 0x38, 0xfa, 0xef, 0x6d, 0x83, 0x0a, 0xa3, 0xc0, - 0xbd, 0x7c, 0x55, 0x15, 0xf2, 0x1f, 0x9c, 0x6c, 0x48, 0x58, 0xdd, 0x93, 0x64, 0x53, 0x7a, 0x34, - 0x9a, 0xd6, 0xd5, 0x71, 0x95, 0x91, 0x74, 0x84, 0xac, 0x2c, 0xc7, 0x28, 0x30, 0xc6, 0x02, 0xb6, - 0x57, 0x52, 0xdd, 0x7e, 0x0c, 0x8c, 0xde, 0xf6, 0xcc, 0x3d, 0xcf, 0x0c, 0xa6, 0x0e, 0x00, 0x92, - 0x65, 0x88, 0x5c, 0xaa, 0x8f, 0x68, 0x6d, 0x71, 0x1c, 0x0a, 0x14, 0x0a, 0x82, 0x8f, 0x64, 0xc8, - 0xe7, 0x93, 0x95, 0x08, 0x52, 0x5a, 0x9f, 0x26, 0x4d, 0x3d, 0x80, 0x93, 0x85, 0xd8, 0x4f, 0x7e, - 0x0b, 0x54, 0xd0, 0xb4, 0x77, 0x73, 0x2d, 0x3d, 0xd6, 0xb6, 0xcd, 0x59, 0xa3, 0xb1, 0xab, 0xdb, - 0xf3, 0x38, 0x8f, 0xb1, 0x7b, 0xfc, 0xa3, 0xa3, 0x2d, 0x38, 0xd9, 0xe3, 0x4b, 0xfe, 0xe5, 0x34, - 0xb1, 0x53, 0xfc, 0x2b, 0x78, 0xd5, 0x29, 0x6c, 0x47, 0xf0, 0x08, 0x69, 0x23, 0x34, 0x9a, 0x1c, - 0xf6, 0x79, 0x7b, 0xf6, 0x81, 0xb1, 0xf5, 0xc7, 0x86, 0x29, 0xb2, 0xa4, 0x4f, 0x23, 0xb4, 0x82, - 0x32, 0x65, 0x92, 0x92, 0xae, 0xe7, 0x6c, 0x8c, 0x75, 0x4c, 0xb9, 0x2e, 0xa6, 0xf9, 0x85, 0x33, - 0x20, 0xc2, 0xf3, 0x4b, 0xb9, 0x24, 0xd7, 0xb8, 0xc5, 0x93, 0x95, 0x26, 0x99, 0xae, 0xbc, 0x51, - 0x8f, 0x21, 0x5f, 0x98, 0x6c, 0x66, 0x94, 0xa6, 0xc5, 0xd7, 0x0e, 0xb0, 0xba, 0x9b, 0x03, 0x2c, - 0x27, 0x41, 0xd7, 0xa4, 0x33, 0xb2, 0xdd, 0xd3, 0xdc, 0xa4, 0xd9, 0xe2, 0xe1, 0x31, 0x8e, 0x15, - 0x25, 0x53, 0xbc, 0xec, 0x18, 0x06, 0x62, 0xb3, 0xdb, 0xaa, 0x0d, 0x65, 0x7e, 0x8d, 0x79, 0x66, - 0x42, 0x0c, 0xd4, 0x9d, 0xe3, 0x6a, 0xc8, 0xec, 0x18, 0x51, 0xbf, 0xd8, 0xc1, 0x59, 0x19, 0x12, - 0xd7, 0xfd, 0x15, 0xc8, 0xf9, 0x42, 0x5c, 0x99, 0xed, 0x0b, 0xed, 0x07, 0xc2, 0x46, 0xb0, 0xe3, - 0x46, 0xa0, 0xd9, 0x7e, 0x25, 0xed, 0x3a, 0xfb, 0xd4, 0x27, 0xf2, 0x79, 0x24, 0x18, 0x8b, 0xba, - 0xc0, 0xcb, 0xd5, 0xe5, 0xa6, 0x6f, 0x23, 0x5f, 0x97, 0x2c, 0x93, 0x0a, 0x75, 0x5d, 0x60, 0xe9, - 0xc5, 0x3e, 0x40, 0x21, 0xe5, 0xc1, 0xf1, 0xd1, 0xae, 0xca, 0x79, 0x6c, 0xb4, 0xe3, 0x43, 0x33, - 0xe6, 0x5b, 0x75, 0x9b, 0x57, 0xee, 0x93, 0x32, 0x33, 0x1f, 0x5b, 0x7e, 0x85, 0xd1, 0x1b, 0xe5, - 0xcf, 0xda, 0xce, 0xb7, 0xf5, 0x32, 0x1b, 0x87, 0xc5, 0xc8, 0xf8, 0xe2, 0x2f, 0xf7, 0x55, 0x30, - 0xa7, 0x60, 0x09, 0xb2, 0xed, 0x7d, 0x56, 0x36, 0x6c, 0xa1, 0x1d, 0xb0, 0x7b, 0x56, 0xa1, 0x0a, - 0xaa, 0x4a, 0xf5, 0x7a, 0xc6, 0x5b, 0x4e, 0x8d, 0x60, 0x3a, 0x20, 0x6e, 0x35, 0x6d, 0x6e, 0xa9, - 0xeb, 0x56, 0xe6, 0x99, 0xcf, 0x2e, 0xc1, 0x63, 0xda, 0xb8, 0xd1, 0x05, 0x31, 0xf1, 0xe3, 0xf4, - 0x14, 0x40, 0x14, 0x3e, 0xa6, 0x7c, 0x08, 0xf6, 0x9e, 0x95, 0xc4, 0x51, 0xc1, 0xb3, 0xe5, 0x6b, - 0x9c, 0x59, 0xa6, 0x56, 0xfe, 0x96, 0xa1, 0xa4, 0x64, 0x2f, 0x6e, 0xbb, 0xd2, 0x50, 0x8f, 0x4a, - 0x7f, 0xda, 0x23, 0xdc, 0x7b, 0xb3, 0x32, 0x0b, 0x43, 0x9e, 0xec, 0x7c, 0xdc, 0xeb, 0xf2, 0xb6, - 0xfd, 0xc1, 0x73, 0x01, 0x5f, 0x30, 0xe2, 0xfc, 0x63, 0x69, 0xd9, 0xdb, 0x94, 0x5d, 0x6f, 0xba, - 0xb6, 0xde, 0x48, 0xf1, 0xb1, 0xfd, 0x52, 0xf1, 0x0a, 0xbc, 0x02, 0x8e, 0x25, 0xd0, 0xe6, 0x14, - 0x27, 0x55, 0xed, 0x4b, 0xdb, 0x2d, 0x7c, 0x52, 0xa2, 0x2c, 0xc7, 0x5f, 0xbc, 0x2f, 0xd3, 0x9e, - 0xdf, 0xa2, 0xf9, 0x61, 0xe6, 0xb1, 0x01, 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0xc8, 0x7f, 0x13, + 0x11, 0x1b, 0x78, 0xe0, 0xbf, 0x18, 0x00, 0xfb, 0x2f, 0x99, 0xc8, 0x10, 0xe3, 0xb7, 0xfe, 0xe8, + 0xff, 0x9b, 0xc5, 0x00, 0xbf, 0x59, 0xe8, 0x0f, 0x93, 0x95, 0x12, 0xfe, 0x8b, 0xa9, 0xfe, 0x70, + 0xee, 0x1f, 0xd4, 0x19, 0xe2, 0x70, 0x12, 0x57, 0xf1, 0xac, 0x01, 0x20, 0x7e, 0xcf, 0x03, 0xff, + 0xc3, 0x74, 0xff, 0xb6, 0xff, 0xe4, 0xb3, 0x47, 0xff, 0xcd, 0xce, 0x7f, 0xd8, 0xfd, 0x0f, 0xff, + 0x57, 0x61, 0x68, 0xbf, 0xfb, 0x0b, 0x1a, 0xe4, 0x77, 0xff, 0xfd, 0xdf, 0xd6, 0x6f, 0xf8, 0xe7, + 0xf7, 0x17, 0xec, 0xff, 0xb3, 0x97, 0xfe, 0xc1, 0x3f, 0xf8, 0x07, 0xff, 0xe0, 0x1f, 0xfc, 0x83, + 0x7f, 0xf0, 0xbf, 0x09, 0xff, 0x0b, 0x48, 0xe1, 0x8a, 0xe3, 0x00, 0x60, 0x00, 0x00, }; #endif // defined(BINDATA_INCLUDE_DATA) @@ -1034,8 +2357,8 @@ #if defined(BINDATA_INCLUDE_STORAGE_PVT_DEFN) { - 12288, // uncompressed data size (bytes) - 7340, // compressed data size (bytes) + 24576, // uncompressed data size (bytes) + 17934, // compressed data size (bytes) kgspBinArchiveGspRmBoot_GA102_ucode_image_prod_data, // compressed data pointer NV_TRUE, // is pData compressed? NV_TRUE, // contain information for file overriding? @@ -1047,19 +2370,19 @@ #if defined(BINDATA_INCLUDE_DATA) // // FUNCTION: kgspGetBinArchiveGspRmBoot_GA102("ucode_desc_prod") -// FILE NAME: kernel/inc/gsprm/bin/g_gsprm_skbl_prod_ga102_riscv_desc.bin +// FILE NAME: kernel/inc/gsprm/bin/g_gsprm_skbl_prod_libos3_ga102_riscv_desc.bin // FILE TYPE: BINARY // VAR NAME: N/A // COMPRESSION: YES // COMPLEX_STRUCT: NO -// DATA SIZE (bytes): 76 -// COMPRESSED SIZE (bytes): 40 +// DATA SIZE (bytes): 84 +// COMPRESSED SIZE (bytes): 42 // static BINDATA_CONST NvU8 kgspBinArchiveGspRmBoot_GA102_ucode_desc_prod_data[] = { - 0x63, 0x61, 0x00, 0x02, 0x05, 0x06, 0x86, 0x0d, 0xac, 0x40, 0xac, 0xca, 0xc0, 0x20, 0xc0, 0x80, - 0x05, 0x70, 0x40, 0x31, 0x33, 0x10, 0x73, 0x03, 0x31, 0x2f, 0x03, 0x03, 0x23, 0x16, 0x75, 0x00, - 0x8d, 0x26, 0xa8, 0x4f, 0x4c, 0x00, 0x00, 0x00, + 0x63, 0x65, 0x00, 0x82, 0x00, 0x06, 0x86, 0x06, 0x0e, 0x20, 0x8e, 0x60, 0x60, 0x10, 0x60, 0xc0, + 0x02, 0x38, 0xa0, 0x18, 0x24, 0x29, 0x01, 0xc4, 0x9a, 0x0c, 0x0c, 0x8c, 0xd8, 0xd4, 0x25, 0x40, + 0x04, 0x01, 0xd4, 0x4b, 0xa9, 0xea, 0x54, 0x00, 0x00, 0x00, }; #endif // defined(BINDATA_INCLUDE_DATA) @@ -1069,8 +2392,8 @@ #if defined(BINDATA_INCLUDE_STORAGE_PVT_DEFN) { - 76, // uncompressed data size (bytes) - 40, // compressed data size (bytes) + 84, // uncompressed data size (bytes) + 42, // compressed data size (bytes) kgspBinArchiveGspRmBoot_GA102_ucode_desc_prod_data, // compressed data pointer NV_TRUE, // is pData compressed? NV_TRUE, // contain information for file overriding? diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/generated/g_bindata_kgspGetBinArchiveGspRmBoot_GH100.c nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_bindata_kgspGetBinArchiveGspRmBoot_GH100.c --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/generated/g_bindata_kgspGetBinArchiveGspRmBoot_GH100.c 2023-10-25 20:19:27.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_bindata_kgspGetBinArchiveGspRmBoot_GH100.c 2024-03-05 22:11:18.000000000 +0000 @@ -29,7755 +29,10332 @@ #if defined(BINDATA_INCLUDE_DATA) // // FUNCTION: kgspGetBinArchiveGspRmBoot_GH100("ucode_image_dbg") -// FILE NAME: kernel/inc/gspcc/bin/g_gsp_gh100_dbg_image.bin +// FILE NAME: kernel/inc/gspcc/bin/g_gsp_gh100_dyn_dbg_image.bin // FILE TYPE: BINARY // VAR NAME: N/A // COMPRESSION: YES // COMPLEX_STRUCT: NO -// DATA SIZE (bytes): 126976 -// COMPRESSED SIZE (bytes): 123814 +// DATA SIZE (bytes): 167936 +// COMPRESSED SIZE (bytes): 165045 // static BINDATA_CONST NvU8 kgspBinArchiveGspRmBoot_GH100_ucode_image_dbg_data[] = { - 0xec, 0x97, 0xc3, 0x92, 0x28, 0x0a, 0x90, 0x6d, 0xcb, 0xb6, 0x6d, 0xd7, 0x29, 0xdb, 0xb6, 0x6d, - 0xdb, 0xb6, 0x6d, 0xdb, 0xb6, 0x6d, 0xdb, 0xb6, 0x6d, 0xdb, 0x7d, 0xbf, 0xe0, 0x8d, 0x5e, 0x44, - 0x4f, 0x7a, 0x0f, 0x73, 0x96, 0xb1, 0x32, 0x22, 0xd7, 0x06, 0x00, 0xf8, 0xbf, 0xfc, 0x6f, 0x66, - 0x6d, 0x03, 0xc8, 0xfe, 0x61, 0x6d, 0x9c, 0x81, 0x7e, 0xb1, 0xb4, 0xd0, 0xfe, 0x96, 0xb3, 0x94, - 0x06, 0x45, 0x34, 0x5e, 0xd7, 0x0f, 0xb4, 0xfd, 0x04, 0xc7, 0x03, 0xcc, 0x19, 0x3b, 0x5a, 0xae, - 0x03, 0x29, 0xd9, 0x54, 0x4b, 0xdb, 0xb5, 0x36, 0x02, 0x19, 0x3d, 0x32, 0x0d, 0x8b, 0x58, 0x1d, - 0xf2, 0x60, 0xb6, 0x99, 0x12, 0xb1, 0x1d, 0xd6, 0xb4, 0x2d, 0x5c, 0xec, 0xbb, 0x7b, 0x78, 0xa2, - 0xb2, 0x5f, 0x15, 0x93, 0x00, 0x0d, 0x4e, 0xf5, 0x69, 0x73, 0x26, 0x57, 0x96, 0xa7, 0x16, 0x11, - 0x75, 0x20, 0x14, 0xd0, 0x7c, 0xf0, 0x96, 0x08, 0xac, 0x1f, 0x0d, 0xd1, 0x87, 0xd7, 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0x74, 0xae, 0x55, 0x0e, 0xe5, 0xa5, 0x9d, 0xf9, 0xd7, 0x1a, + 0x84, 0x66, 0x41, 0x6f, 0xb7, 0x93, 0x80, 0x5b, 0x5a, 0x96, 0xe1, 0x61, 0x05, 0x4c, 0x9e, 0x88, + 0xc0, 0x29, 0x97, 0xb1, 0xd8, 0xb5, 0x0e, 0x87, 0x82, 0x89, 0xe7, 0x04, 0x3f, 0x80, 0xf9, 0xab, + 0xc9, 0xe2, 0x59, 0x12, 0x2a, 0xc2, 0x1c, 0xfa, 0xe2, 0xf2, 0x71, 0x0e, 0x4a, 0xde, 0xc0, 0xa2, + 0x15, 0xac, 0xcd, 0x2e, 0xfa, 0xf0, 0x53, 0xb2, 0xf6, 0xe0, 0xb0, 0x67, 0xfb, 0x96, 0xb3, 0x51, + 0x3a, 0x05, 0x1a, 0xb4, 0x86, 0xa1, 0x85, 0xc1, 0x2f, 0x8d, 0x0e, 0xab, 0xef, 0xef, 0x39, 0xf3, + 0x1e, 0xb7, 0xc0, 0x96, 0xf1, 0x57, 0x03, 0x52, 0x4c, 0x3d, 0x6c, 0x02, 0x90, 0x1f, 0x12, 0x94, + 0xd5, 0x22, 0xd8, 0x53, 0xe7, 0x7d, 0xb8, 0x82, 0xb3, 0xe5, 0x96, 0x27, 0xc4, 0xb4, 0x6e, 0xf6, + 0x6a, 0xda, 0xb4, 0xc8, 0xcb, 0x2b, 0xef, 0x87, 0x69, 0x09, 0xab, 0x32, 0xe4, 0x42, 0x49, 0xc1, + 0x70, 0xb9, 0x6c, 0x43, 0x00, 0x82, 0x3c, 0x91, 0x4b, 0xc8, 0x90, 0x2a, 0xa4, 0x0c, 0x72, 0x83, + 0x9b, 0x11, 0x5a, 0x4f, 0xa7, 0x71, 0xa8, 0x3a, 0xb7, 0x8e, 0x28, 0x03, 0x72, 0xb0, 0xac, 0xdf, + 0x96, 0xbb, 0x93, 0x87, 0x25, 0x01, 0x0d, 0xa8, 0x71, 0x18, 0x99, 0x91, 0x2b, 0x80, 0xff, 0x8d, + 0x92, 0x82, 0x82, 0x82, 0x82, 0x82, 0x82, 0x82, 0x82, 0xc2, 0xff, 0xca, 0x7f, 0x68, 0xc3, 0x8a, + 0x94, 0x00, 0x90, 0x02, 0x00, }; #endif // defined(BINDATA_INCLUDE_DATA) @@ -7787,8 +10364,8 @@ #if defined(BINDATA_INCLUDE_STORAGE_PVT_DEFN) { - 126976, // uncompressed data size (bytes) - 123814, // compressed data size (bytes) + 167936, // uncompressed data size (bytes) + 165045, // compressed data size (bytes) kgspBinArchiveGspRmBoot_GH100_ucode_image_dbg_data, // compressed data pointer NV_TRUE, // is pData compressed? NV_TRUE, // contain information for file overriding? @@ -7800,18 +10377,18 @@ #if defined(BINDATA_INCLUDE_DATA) // // FUNCTION: kgspGetBinArchiveGspRmBoot_GH100("ucode_desc_dbg") -// FILE NAME: kernel/inc/gspcc/bin/g_gsp_gh100_dbg_desc.bin +// FILE NAME: kernel/inc/gspcc/bin/g_gsp_gh100_dyn_dbg_desc.bin // FILE TYPE: BINARY // VAR NAME: N/A // COMPRESSION: YES // COMPLEX_STRUCT: NO // DATA SIZE (bytes): 84 -// COMPRESSED SIZE (bytes): 27 +// COMPRESSED SIZE (bytes): 28 // static BINDATA_CONST NvU8 kgspBinArchiveGspRmBoot_GH100_ucode_desc_dbg_data[] = { - 0x63, 0x65, 0x20, 0x02, 0x70, 0x41, 0x71, 0x25, 0x10, 0x37, 0x03, 0x71, 0x12, 0x23, 0x03, 0x23, - 0x1e, 0x7d, 0x00, 0x9f, 0x32, 0x0c, 0x15, 0x54, 0x00, 0x00, 0x00, + 0x63, 0x65, 0x20, 0x02, 0x70, 0x41, 0xf1, 0x72, 0x20, 0xde, 0x08, 0xc4, 0x57, 0x19, 0x19, 0x18, + 0xf1, 0xe8, 0x03, 0x00, 0xd2, 0xa8, 0x0e, 0x80, 0x54, 0x00, 0x00, 0x00, }; #endif // defined(BINDATA_INCLUDE_DATA) @@ -7822,7 +10399,7 @@ #if defined(BINDATA_INCLUDE_STORAGE_PVT_DEFN) { 84, // uncompressed data size (bytes) - 27, // compressed data size (bytes) + 28, // compressed data size (bytes) kgspBinArchiveGspRmBoot_GH100_ucode_desc_dbg_data, // compressed data pointer NV_TRUE, // is pData compressed? NV_TRUE, // contain information for file overriding? @@ -7834,7778 +10411,10355 @@ #if defined(BINDATA_INCLUDE_DATA) // // FUNCTION: kgspGetBinArchiveGspRmBoot_GH100("ucode_image_prod") -// FILE NAME: kernel/inc/gspcc/bin/g_gsp_gh100_prd_image.bin +// FILE NAME: kernel/inc/gspcc/bin/g_gsp_gh100_dyn_prd_image.bin // FILE TYPE: BINARY // VAR NAME: N/A // COMPRESSION: YES // COMPLEX_STRUCT: NO -// DATA SIZE (bytes): 126976 -// COMPRESSED SIZE (bytes): 124189 +// DATA SIZE (bytes): 167936 +// COMPRESSED SIZE (bytes): 165420 // static BINDATA_CONST NvU8 kgspBinArchiveGspRmBoot_GH100_ucode_image_prod_data[] = { - 0x9c, 0x97, 0xc3, 0x96, 0x28, 0x0a, 0x80, 0x24, 0xcb, 0xb6, 0x6d, 0xdb, 0xb6, 0x6d, 0xdb, 0x55, - 0xb7, 0x6c, 0xdb, 0xb6, 0x6d, 0xdb, 0xb6, 0x6d, 0xdb, 0xb6, 0xd9, 0x6f, 0x3e, 0x60, 0x7a, 0xd1, - 0xb1, 0xce, 0x5d, 0x2e, 0xe2, 0x44, 0x80, 0x0b, 0xfc, 0xb3, 0x06, 0xd5, 0x00, 0x29, 0x49, 0x87, - 0xf3, 0x14, 0x29, 0xf7, 0xdc, 0xb0, 0x8e, 0xa3, 0x7f, 0x3d, 0x76, 0x7f, 0xfa, 0x2b, 0xcd, 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0x45, + 0x4e, 0x65, 0x82, 0xf2, 0xb6, 0x49, 0x2e, 0x11, 0xea, 0xa2, 0xdd, 0xbf, 0xf1, 0xee, 0xd5, 0xb5, + 0x94, 0x31, 0xae, 0x92, 0x3e, 0x5f, 0x2a, 0xc0, 0xd4, 0xfa, 0x8e, 0xc6, 0xb8, 0x3c, 0x10, 0xd6, + 0x28, 0x91, 0x3c, 0xf0, 0x00, 0x2b, 0x6b, 0x17, 0x3a, 0x14, 0x9a, 0x9b, 0xf4, 0xae, 0x58, 0x8b, + 0xc1, 0xb0, 0x98, 0xcb, 0x57, 0x91, 0xae, 0xd0, 0xe2, 0x95, 0x25, 0x8a, 0x70, 0xea, 0x19, 0x5c, + 0xcc, 0x59, 0xa1, 0x4f, 0x4b, 0x95, 0xfe, 0x9d, 0x0f, 0xfa, 0x09, 0x49, 0x3a, 0xaa, 0x67, 0xe7, + 0x05, 0xfb, 0x1c, 0xba, 0x58, 0x25, 0xe1, 0x3a, 0x9f, 0x4f, 0x28, 0x93, 0xab, 0x3f, 0xaf, 0x75, + 0x02, 0x86, 0x60, 0x8b, 0x5e, 0x6a, 0x4f, 0x89, 0x85, 0x2d, 0x40, 0xc2, 0xf1, 0x8f, 0xc9, 0xa9, + 0x58, 0x63, 0xf1, 0x0c, 0xef, 0x19, 0xba, 0x3d, 0x89, 0x20, 0x38, 0x46, 0x09, 0x3b, 0xde, 0xac, + 0xb4, 0x25, 0xd8, 0x5d, 0x2e, 0x9b, 0x8a, 0xd2, 0xed, 0xbe, 0x9d, 0xc2, 0xc1, 0x1d, 0x3d, 0xe9, + 0xd5, 0x65, 0x6c, 0x69, 0xca, 0x58, 0x90, 0xbe, 0xf2, 0x8d, 0xab, 0x76, 0xae, 0xbe, 0xab, 0xeb, + 0xf0, 0xb6, 0xad, 0x01, 0x16, 0x78, 0x7e, 0x80, 0xa3, 0x43, 0xa8, 0xe3, 0xaf, 0x0c, 0x77, 0x8b, + 0x79, 0x82, 0x32, 0x94, 0x08, 0xdf, 0x6a, 0x8a, 0x0f, 0xce, 0x82, 0x7e, 0xc9, 0x98, 0xea, 0x11, + 0x66, 0x87, 0xf2, 0x5c, 0xde, 0xab, 0xf0, 0x70, 0x71, 0x71, 0x71, 0x71, 0x71, 0x71, 0x71, 0x71, + 0xfd, 0xaf, 0xfc, 0x0b, 0x8d, 0x25, 0xe9, 0x05, 0x00, 0x90, 0x02, 0x00, }; #endif // defined(BINDATA_INCLUDE_DATA) @@ -15615,8 +20769,8 @@ #if defined(BINDATA_INCLUDE_STORAGE_PVT_DEFN) { - 126976, // uncompressed data size (bytes) - 124189, // compressed data size (bytes) + 167936, // uncompressed data size (bytes) + 165420, // compressed data size (bytes) kgspBinArchiveGspRmBoot_GH100_ucode_image_prod_data, // compressed data pointer NV_TRUE, // is pData compressed? NV_TRUE, // contain information for file overriding? @@ -15628,18 +20782,18 @@ #if defined(BINDATA_INCLUDE_DATA) // // FUNCTION: kgspGetBinArchiveGspRmBoot_GH100("ucode_desc_prod") -// FILE NAME: kernel/inc/gspcc/bin/g_gsp_gh100_prd_desc.bin +// FILE NAME: kernel/inc/gspcc/bin/g_gsp_gh100_dyn_prd_desc.bin // FILE TYPE: BINARY // VAR NAME: N/A // COMPRESSION: YES // COMPLEX_STRUCT: NO // DATA SIZE (bytes): 84 -// COMPRESSED SIZE (bytes): 27 +// COMPRESSED SIZE (bytes): 28 // static BINDATA_CONST NvU8 kgspBinArchiveGspRmBoot_GH100_ucode_desc_prod_data[] = { - 0x63, 0x65, 0x20, 0x02, 0x70, 0x41, 0x71, 0x25, 0x10, 0x37, 0x03, 0x71, 0x12, 0x23, 0x03, 0x23, - 0x1e, 0x7d, 0x00, 0x9f, 0x32, 0x0c, 0x15, 0x54, 0x00, 0x00, 0x00, + 0x63, 0x65, 0x20, 0x02, 0x70, 0x41, 0xf1, 0x72, 0x20, 0xde, 0x08, 0xc4, 0x57, 0x19, 0x19, 0x18, + 0xf1, 0xe8, 0x03, 0x00, 0xd2, 0xa8, 0x0e, 0x80, 0x54, 0x00, 0x00, 0x00, }; #endif // defined(BINDATA_INCLUDE_DATA) @@ -15650,7 +20804,7 @@ #if defined(BINDATA_INCLUDE_STORAGE_PVT_DEFN) { 84, // uncompressed data size (bytes) - 27, // compressed data size (bytes) + 28, // compressed data size (bytes) kgspBinArchiveGspRmBoot_GH100_ucode_desc_prod_data, // compressed data pointer NV_TRUE, // is pData compressed? NV_TRUE, // contain information for file overriding? diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/generated/g_bindata_kgspGetBinArchiveGspRmCcFmcGfwProdSigned_GH100.c nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_bindata_kgspGetBinArchiveGspRmCcFmcGfwProdSigned_GH100.c --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/generated/g_bindata_kgspGetBinArchiveGspRmCcFmcGfwProdSigned_GH100.c 1970-01-01 00:00:00.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_bindata_kgspGetBinArchiveGspRmCcFmcGfwProdSigned_GH100.c 2024-03-05 22:11:18.000000000 +0000 @@ -0,0 +1,10637 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2016-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + + +/* THIS FILE IS AUTOMATICALLY GENERATED, DO NOT EDIT! */ + + + +#if defined(BINDATA_INCLUDE_DATA) +// +// FUNCTION: kgspGetBinArchiveGspRmCcFmcGfwProdSigned_GH100("ucode_image") +// FILE NAME: kernel/inc/gspcc/bin/g_gsp_gh100_dyn_cc_prd_gfw_image.bin +// FILE TYPE: BINARY +// VAR NAME: N/A +// COMPRESSION: YES +// COMPLEX_STRUCT: NO +// DATA SIZE (bytes): 166216 +// COMPRESSED SIZE (bytes): 166198 +// +static BINDATA_CONST NvU8 kgspBinArchiveGspRmCcFmcGfwProdSigned_GH100_ucode_image_data[] = +{ + 0x8c, 0xd7, 0xd3, 0x96, 0x28, 0x0a, 0x90, 0x24, 0xd0, 0xb2, 0x6d, 0xdb, 0xb6, 0x6d, 0xdb, 0xb6, + 0x6d, 0xdb, 0xb6, 0x4e, 0xd9, 0xb6, 0x6d, 0xdb, 0xb6, 0x6d, 0xa3, 0xef, 0x9a, 0xe9, 0x0f, 0xe8, + 0x78, 0xc9, 0xfc, 0x83, 0x88, 0x0d, 0x0c, 0x22, 0x01, 0x00, 0x10, 0x09, 0x04, 0xf0, 0xff, 0xb2, + 0x01, 0xf8, 0xff, 0x6f, 0x29, 0x00, 0x00, 0xc8, 0xff, 0xbe, 0x80, 0x14, 0x00, 0xff, 0xa7, 0xfc, + 0xa3, 0x32, 0x3a, 0x99, 0x18, 0x27, 0x74, 0x12, 0xd7, 0x92, 0x9e, 0x49, 0xc1, 0x1a, 0x38, 0x52, + 0xe1, 0x5c, 0xa3, 0xae, 0x72, 0x9d, 0x02, 0x5b, 0x02, 0xed, 0xd4, 0xa8, 0x21, 0xf1, 0x03, 0x71, + 0xf2, 0xfc, 0x9a, 0xf8, 0x21, 0x1a, 0x68, 0x65, 0x1e, 0x59, 0xf2, 0x02, 0x80, 0x60, 0xfe, 0x43, + 0x56, 0x1e, 0xbf, 0xfb, 0x45, 0x77, 0x1d, 0xce, 0x7c, 0xb2, 0xeb, 0x06, 0xdf, 0xfb, 0x72, 0x16, + 0xc9, 0x08, 0xc2, 0x64, 0x56, 0xa6, 0xde, 0xcb, 0x37, 0x86, 0x62, 0x15, 0xb5, 0xee, 0x9e, 0xfc, + 0xaa, 0x32, 0xab, 0x3f, 0x42, 0xc1, 0xdf, 0xf4, 0x63, 0x82, 0x2e, 0xd5, 0xd6, 0x81, 0x43, 0x73, + 0x55, 0x2e, 0x39, 0x7a, 0xb0, 0x14, 0x9a, 0xde, 0xd5, 0x67, 0x40, 0x22, 0x91, 0x22, 0xe9, 0x0e, + 0x74, 0xf8, 0x06, 0xae, 0x20, 0x6b, 0x40, 0x34, 0xad, 0x69, 0x94, 0x54, 0x66, 0x81, 0xb8, 0x18, + 0x96, 0x33, 0xaf, 0xa4, 0x8b, 0x92, 0xb3, 0xe8, 0x57, 0x0a, 0x8d, 0x36, 0xde, 0x44, 0x65, 0x93, + 0x99, 0xc8, 0x29, 0x7d, 0xba, 0x88, 0xfc, 0xc1, 0x9d, 0xd5, 0xec, 0x7a, 0xd4, 0x2b, 0x24, 0xa4, + 0x31, 0x0e, 0x12, 0xa3, 0x03, 0x41, 0xdf, 0x93, 0xe9, 0xa1, 0xb5, 0x0e, 0x62, 0xad, 0x99, 0x45, + 0xab, 0x3a, 0xdb, 0x16, 0x29, 0xdd, 0xc1, 0xd9, 0x50, 0x00, 0xf7, 0x52, 0x95, 0xd2, 0xd2, 0x5a, + 0x79, 0x6f, 0x86, 0x9a, 0x5b, 0x85, 0x8c, 0x3b, 0x03, 0xcd, 0x5e, 0x7b, 0xc2, 0x90, 0xdc, 0x8c, + 0x30, 0xe4, 0xcb, 0xc8, 0xb2, 0x7c, 0x10, 0x1e, 0x9d, 0x6a, 0x5f, 0xfd, 0x05, 0xb5, 0x24, 0x9d, + 0x96, 0x45, 0x3a, 0x88, 0x5b, 0x74, 0x5f, 0x8a, 0x8a, 0x81, 0xae, 0xef, 0x02, 0x70, 0x93, 0x1c, + 0xea, 0x8c, 0x83, 0x6a, 0xe3, 0xf2, 0x14, 0x5d, 0x20, 0x62, 0x11, 0xaa, 0x36, 0x1c, 0x09, 0x53, + 0xf6, 0x76, 0x96, 0x3e, 0xfe, 0x47, 0x4c, 0xb4, 0x00, 0xbb, 0xe8, 0x93, 0x3b, 0xe6, 0x0c, 0xa1, + 0x99, 0x52, 0x23, 0x0b, 0x54, 0x16, 0xf4, 0x9d, 0x2c, 0xa4, 0x78, 0x85, 0x93, 0xed, 0xbe, 0x88, + 0xee, 0x82, 0x01, 0x76, 0xa7, 0xe9, 0x69, 0x73, 0x06, 0xe6, 0x91, 0x31, 0x03, 0xdf, 0x42, 0xab, + 0x00, 0x44, 0x21, 0x31, 0x50, 0xdd, 0xa8, 0x86, 0x73, 0x6c, 0xda, 0x79, 0x60, 0x25, 0xcd, 0x67, + 0xbc, 0x4e, 0xb8, 0xbd, 0x7c, 0x4f, 0x09, 0x21, 0xae, 0x06, 0x2b, 0xbe, 0x8d, 0xac, 0xea, 0x37, + 0xad, 0x66, 0xa8, 0x90, 0xb7, 0xf3, 0x4a, 0x2c, 0x12, 0x0a, 0x23, 0x96, 0xf4, 0x1e, 0x35, 0xd7, + 0x89, 0xaf, 0x2c, 0xad, 0xd4, 0x7d, 0xbe, 0xf1, 0x3e, 0x4f, 0xcc, 0xc8, 0x30, 0xfb, 0x7e, 0x50, + 0x47, 0x15, 0xf4, 0x1e, 0x85, 0x56, 0x73, 0x9a, 0x4b, 0x0b, 0xed, 0xff, 0xd4, 0x7a, 0xdb, 0x37, + 0xf4, 0xef, 0x7c, 0x21, 0x37, 0xec, 0xc3, 0x9a, 0x93, 0x16, 0xdf, 0x81, 0x60, 0x7f, 0x55, 0x94, + 0xe5, 0x9f, 0x84, 0xf4, 0x26, 0xf9, 0x30, 0xe1, 0xde, 0x17, 0x62, 0xf2, 0x87, 0x11, 0x87, 0x62, + 0x6b, 0x4b, 0xb5, 0xe4, 0x0c, 0x40, 0x50, 0x61, 0x8c, 0xc0, 0x83, 0xe0, 0xa3, 0x80, 0xf5, 0x3f, + 0x95, 0x78, 0x56, 0xea, 0xc6, 0xed, 0xda, 0xf1, 0xee, 0x2a, 0xb2, 0x3c, 0x32, 0x5e, 0xa5, 0xef, + 0x24, 0xf8, 0x07, 0x6b, 0xd0, 0x41, 0x20, 0x60, 0x4b, 0x2f, 0xc8, 0x8d, 0x54, 0x6a, 0x04, 0x07, + 0xcc, 0xf2, 0x41, 0xc0, 0x8e, 0xc0, 0xf4, 0x7a, 0x71, 0x5f, 0x2d, 0xf5, 0x99, 0x4d, 0x57, 0xd4, + 0x5b, 0x59, 0xf3, 0xc8, 0x14, 0xb2, 0xca, 0xb4, 0x07, 0xa4, 0x2d, 0x25, 0xa9, 0xae, 0xad, 0x25, + 0x8d, 0x12, 0x54, 0x7a, 0xf3, 0x24, 0x21, 0xa8, 0x9e, 0xcf, 0x35, 0xcf, 0x22, 0x0c, 0x67, 0xb3, + 0x18, 0x82, 0x98, 0xa8, 0x84, 0xcd, 0x36, 0x11, 0xc4, 0x56, 0xc9, 0x4a, 0x6c, 0x22, 0x87, 0x3d, + 0x33, 0x36, 0x94, 0x30, 0x3d, 0x77, 0x81, 0x35, 0x2f, 0x98, 0xa2, 0xc3, 0x34, 0xdb, 0xec, 0xd1, + 0xb5, 0x88, 0x41, 0x26, 0xa0, 0x25, 0xa3, 0x78, 0x21, 0x4d, 0x0a, 0x9d, 0x0e, 0xa3, 0x6a, 0x1c, + 0xac, 0xaf, 0xb0, 0x46, 0xa8, 0x0d, 0xf0, 0x04, 0xe6, 0x31, 0x95, 0x90, 0xf8, 0xf2, 0x90, 0xb1, + 0x88, 0xac, 0xc4, 0xc8, 0x77, 0x86, 0x1a, 0xb6, 0xcc, 0x93, 0x65, 0xff, 0xb3, 0xad, 0x6c, 0x39, + 0x91, 0x88, 0x3e, 0x52, 0x72, 0xb5, 0x04, 0x1e, 0xd0, 0x4f, 0x40, 0x20, 0xa8, 0x72, 0x46, 0x84, + 0x2c, 0x6d, 0x2b, 0x23, 0xe3, 0x4e, 0xbf, 0x48, 0xcc, 0x55, 0xed, 0xc7, 0x8c, 0xa8, 0x78, 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0xd8, 0xc2, 0x0c, 0x78, 0xa2, 0x81, 0x67, 0xfb, 0xeb, 0x86, 0x17, 0xec, + 0xd8, 0x7d, 0xb9, 0x09, 0x10, 0xb3, 0x9c, 0xa1, 0x81, 0x71, 0x39, 0x72, 0x73, 0x8d, 0x65, 0x73, + 0xc7, 0x46, 0xcf, 0x05, 0x31, 0x03, 0x2d, 0xe2, 0xf4, 0x58, 0xb4, 0xf2, 0x77, 0xd7, 0xc7, 0xfd, + 0xed, 0x46, 0xed, 0xce, 0x31, 0xb3, 0x96, 0x20, 0x1a, 0x45, 0xa5, 0x39, 0xff, 0x05, 0x40, 0x72, + 0x43, 0xb2, 0x48, 0x89, 0x02, 0x00, +}; +#endif // defined(BINDATA_INCLUDE_DATA) + +#if defined(BINDATA_INCLUDE_STORAGE_PVT_DECL) +BINDATA_STORAGE_PVT kgspBinArchiveGspRmCcFmcGfwProdSigned_GH100_ucode_image_storage_pvt; +#endif // defined(BINDATA_INCLUDE_STORAGE_PVT_DECL) + +#if defined(BINDATA_INCLUDE_STORAGE_PVT_DEFN) +{ + 166216, // uncompressed data size (bytes) + 166198, // compressed data size (bytes) + kgspBinArchiveGspRmCcFmcGfwProdSigned_GH100_ucode_image_data, // compressed data pointer + NV_TRUE, // is pData compressed? + NV_TRUE, // contain information for file overriding? + NV_FALSE, // is the data referenced during load? (Only valid when BINDATA_IS_MUTABLE is true) +}, +#endif // defined(BINDATA_INCLUDE_STORAGE_PVT_DEFN) + + +#if defined(BINDATA_INCLUDE_DATA) +// +// FUNCTION: kgspGetBinArchiveGspRmCcFmcGfwProdSigned_GH100("ucode_hash") +// FILE NAME: kernel/inc/gspcc/bin/g_gsp_gh100_dyn_cc_prd_gfw_hash.bin +// FILE TYPE: BINARY +// VAR NAME: N/A +// COMPRESSION: YES +// COMPLEX_STRUCT: NO +// DATA SIZE (bytes): 48 +// COMPRESSED SIZE (bytes): 61 +// +static BINDATA_CONST NvU8 kgspBinArchiveGspRmCcFmcGfwProdSigned_GH100_ucode_hash_data[] = +{ + 0x01, 0x30, 0x00, 0xcf, 0xff, 0xb8, 0x3e, 0x10, 0x76, 0xdd, 0x70, 0x1c, 0xd3, 0x96, 0xbe, 0x3c, + 0xd4, 0xbb, 0x6a, 0x5a, 0x0a, 0x93, 0x88, 0x65, 0x6e, 0xb0, 0x81, 0x40, 0xd1, 0xb1, 0x21, 0xe1, + 0x47, 0x27, 0xae, 0xb6, 0x71, 0xfe, 0xcb, 0x12, 0x1e, 0xd7, 0xf7, 0x8c, 0xfc, 0x8d, 0x1f, 0x97, + 0x3b, 0x0f, 0x73, 0x35, 0x01, 0xd1, 0xcb, 0xbc, 0x8a, 0x30, 0x00, 0x00, 0x00, +}; +#endif // defined(BINDATA_INCLUDE_DATA) + +#if defined(BINDATA_INCLUDE_STORAGE_PVT_DECL) +BINDATA_STORAGE_PVT kgspBinArchiveGspRmCcFmcGfwProdSigned_GH100_ucode_hash_storage_pvt; +#endif // defined(BINDATA_INCLUDE_STORAGE_PVT_DECL) + +#if defined(BINDATA_INCLUDE_STORAGE_PVT_DEFN) +{ + 48, // uncompressed data size (bytes) + 61, // compressed data size (bytes) + kgspBinArchiveGspRmCcFmcGfwProdSigned_GH100_ucode_hash_data, // compressed data pointer + NV_TRUE, // is pData compressed? + NV_TRUE, // contain information for file overriding? + NV_FALSE, // is the data referenced during load? (Only valid when BINDATA_IS_MUTABLE is true) +}, +#endif // defined(BINDATA_INCLUDE_STORAGE_PVT_DEFN) + + +#if defined(BINDATA_INCLUDE_DATA) +// +// FUNCTION: kgspGetBinArchiveGspRmCcFmcGfwProdSigned_GH100("ucode_sig") +// FILE NAME: kernel/inc/gspcc/bin/g_gsp_gh100_dyn_cc_prd_gfw_sig.bin +// FILE TYPE: BINARY +// VAR NAME: N/A +// COMPRESSION: YES +// COMPLEX_STRUCT: NO +// DATA SIZE (bytes): 384 +// COMPRESSED SIZE (bytes): 397 +// +static BINDATA_CONST NvU8 kgspBinArchiveGspRmCcFmcGfwProdSigned_GH100_ucode_sig_data[] = +{ + 0x01, 0x80, 0x01, 0x7f, 0xfe, 0x48, 0x11, 0x1d, 0x85, 0xc1, 0xae, 0xd8, 0x0b, 0x5f, 0xa8, 0x76, + 0xa8, 0x26, 0x1d, 0x51, 0xc3, 0xb4, 0x93, 0x5d, 0x59, 0x4e, 0xc7, 0x73, 0x30, 0x54, 0x84, 0x30, + 0xfc, 0xad, 0x42, 0x0f, 0xc7, 0x3f, 0xd5, 0xce, 0x2a, 0xe3, 0x91, 0x00, 0xc0, 0x17, 0xe9, 0x96, + 0xda, 0xcc, 0x2c, 0x3d, 0xe3, 0x7e, 0x77, 0xf8, 0x60, 0xe9, 0x78, 0xad, 0x06, 0x19, 0x29, 0x6e, + 0x13, 0xe8, 0xce, 0x0f, 0x8f, 0x2d, 0x68, 0xab, 0x1e, 0x57, 0xc9, 0x94, 0x42, 0xbf, 0x84, 0x0a, + 0x1e, 0x8d, 0xbd, 0x27, 0x18, 0xed, 0x6c, 0x9b, 0xcb, 0x2b, 0x92, 0x0a, 0x76, 0x28, 0x77, 0x5c, + 0x41, 0xdb, 0x0d, 0x8b, 0xbe, 0xca, 0x71, 0x73, 0x72, 0x6f, 0x33, 0x11, 0xc2, 0xb1, 0xe2, 0x6e, + 0x8c, 0x40, 0x95, 0x82, 0x90, 0x83, 0x50, 0x67, 0x62, 0x3c, 0xa1, 0x2f, 0x48, 0x34, 0x37, 0x20, + 0x55, 0x4d, 0x33, 0x43, 0x80, 0xc6, 0xcc, 0xcd, 0x60, 0xf5, 0xed, 0x6b, 0x12, 0x69, 0x73, 0xc7, + 0x1d, 0x14, 0x7b, 0x6d, 0xdb, 0x20, 0x05, 0x59, 0xef, 0x5d, 0xf2, 0x55, 0xd7, 0x3a, 0xc7, 0xbf, + 0x5a, 0xee, 0x46, 0x72, 0xe5, 0xfd, 0x4c, 0xd3, 0x62, 0x07, 0x8f, 0xc2, 0xda, 0xf5, 0xab, 0x22, + 0x1e, 0x43, 0xda, 0xdb, 0x91, 0x93, 0x4d, 0xec, 0xaa, 0xfb, 0x41, 0xca, 0xc5, 0x43, 0x93, 0xc1, + 0x62, 0xae, 0x53, 0xfd, 0x09, 0x6c, 0x82, 0xac, 0x42, 0x38, 0xb4, 0xa0, 0x0d, 0xf1, 0x90, 0x55, + 0xa6, 0x3e, 0x4b, 0x22, 0x47, 0xb2, 0x79, 0x05, 0xb7, 0x23, 0x09, 0x6d, 0x22, 0x65, 0xd1, 0x2f, + 0x26, 0x70, 0xce, 0x28, 0xa9, 0xdb, 0xff, 0x63, 0x5f, 0x63, 0x59, 0x2d, 0x2a, 0x03, 0xdf, 0xdd, + 0x95, 0x89, 0xf0, 0xce, 0xdd, 0x28, 0x81, 0x4f, 0xd7, 0x2c, 0x43, 0x0c, 0xf6, 0x99, 0xb2, 0xc3, + 0xef, 0x32, 0xe5, 0xe1, 0xae, 0x42, 0x0c, 0xba, 0xbf, 0xb6, 0x61, 0xe0, 0x36, 0x75, 0x43, 0xef, + 0x4e, 0xa2, 0x22, 0x44, 0x60, 0x5c, 0xfa, 0xe6, 0x26, 0x52, 0x86, 0xb8, 0x2d, 0x84, 0xa6, 0xf7, + 0x4f, 0xfa, 0x04, 0x97, 0x26, 0x7f, 0xc4, 0xc1, 0xa9, 0x6c, 0x72, 0x08, 0x9c, 0x04, 0x06, 0x22, + 0x10, 0x13, 0x5b, 0x92, 0xd0, 0x39, 0x4f, 0xc3, 0x20, 0x0f, 0xd3, 0xda, 0x54, 0x9d, 0x21, 0x3e, + 0x8d, 0xd1, 0x23, 0x65, 0xf1, 0xee, 0xed, 0x42, 0xa7, 0xfe, 0x51, 0xe6, 0x49, 0x7b, 0x2d, 0x4c, + 0x76, 0x6a, 0xdb, 0x11, 0x0e, 0xbb, 0x2d, 0xf4, 0xea, 0xc4, 0xb8, 0x2c, 0x5b, 0x74, 0xf8, 0xfa, + 0x5d, 0x51, 0xdb, 0x1a, 0x7a, 0x00, 0xc0, 0xfa, 0x2f, 0xf7, 0x3b, 0xb7, 0x87, 0xa5, 0x7c, 0x1a, + 0x57, 0x28, 0x52, 0xe3, 0xf5, 0x26, 0x74, 0xc3, 0x03, 0x87, 0x0b, 0x91, 0x5b, 0x61, 0xae, 0x3b, + 0xbe, 0xa2, 0x27, 0xe3, 0x42, 0x3f, 0x63, 0xa8, 0x92, 0x80, 0x01, 0x00, 0x00, +}; +#endif // defined(BINDATA_INCLUDE_DATA) + +#if defined(BINDATA_INCLUDE_STORAGE_PVT_DECL) +BINDATA_STORAGE_PVT kgspBinArchiveGspRmCcFmcGfwProdSigned_GH100_ucode_sig_storage_pvt; +#endif // defined(BINDATA_INCLUDE_STORAGE_PVT_DECL) + +#if defined(BINDATA_INCLUDE_STORAGE_PVT_DEFN) +{ + 384, // uncompressed data size (bytes) + 397, // compressed data size (bytes) + kgspBinArchiveGspRmCcFmcGfwProdSigned_GH100_ucode_sig_data, // compressed data pointer + NV_TRUE, // is pData compressed? + NV_TRUE, // contain information for file overriding? + NV_FALSE, // is the data referenced during load? (Only valid when BINDATA_IS_MUTABLE is true) +}, +#endif // defined(BINDATA_INCLUDE_STORAGE_PVT_DEFN) + + +#if defined(BINDATA_INCLUDE_DATA) +// +// FUNCTION: kgspGetBinArchiveGspRmCcFmcGfwProdSigned_GH100("ucode_pkey") +// FILE NAME: kernel/inc/gspcc/bin/g_gsp_gh100_dyn_cc_prd_gfw_pub_key.bin +// FILE TYPE: BINARY +// VAR NAME: N/A +// COMPRESSION: YES +// COMPLEX_STRUCT: NO +// DATA SIZE (bytes): 384 +// COMPRESSED SIZE (bytes): 397 +// +static BINDATA_CONST NvU8 kgspBinArchiveGspRmCcFmcGfwProdSigned_GH100_ucode_pkey_data[] = +{ + 0x01, 0x80, 0x01, 0x7f, 0xfe, 0xb6, 0x61, 0x74, 0x8c, 0x50, 0xfd, 0x5d, 0x6b, 0xbc, 0x71, 0xe9, + 0xcf, 0x5e, 0xf6, 0x8b, 0x5d, 0xd5, 0x36, 0xe8, 0xaf, 0xca, 0x7a, 0x14, 0x6a, 0x3d, 0x1f, 0xa6, + 0x8b, 0x37, 0xf9, 0x3e, 0x5a, 0x44, 0xec, 0xb6, 0x6a, 0x39, 0x25, 0x78, 0xce, 0xd6, 0xf0, 0xe2, + 0xa1, 0x40, 0xae, 0x82, 0x22, 0x60, 0xaa, 0xf3, 0x6a, 0xd3, 0x4d, 0xe6, 0xc1, 0x38, 0x18, 0x4e, + 0xfc, 0xd6, 0x6c, 0x61, 0x38, 0x73, 0x13, 0x26, 0x71, 0xa8, 0xb8, 0x9c, 0xeb, 0x07, 0x28, 0x4e, + 0x86, 0x2b, 0xe2, 0x5e, 0xf8, 0xfd, 0x2c, 0x01, 0x51, 0x6f, 0x1c, 0xf9, 0x47, 0x36, 0x62, 0xcc, + 0x59, 0x24, 0x67, 0xf8, 0x5d, 0x13, 0x39, 0x52, 0xd9, 0x0b, 0xbf, 0x92, 0x98, 0xad, 0x98, 0x2b, + 0x53, 0x4d, 0x35, 0xda, 0x06, 0x7e, 0x89, 0x07, 0x2f, 0xb0, 0x0f, 0x12, 0x44, 0x1d, 0xe8, 0xa8, + 0xed, 0x40, 0x9c, 0x84, 0x8a, 0x99, 0x7e, 0x09, 0x05, 0xee, 0x9c, 0x62, 0x2a, 0x6e, 0xdb, 0xe3, + 0xc2, 0x7c, 0x39, 0x7c, 0xdb, 0x30, 0x49, 0x26, 0x58, 0xf1, 0x94, 0xa6, 0xd1, 0x8b, 0xda, 0x79, + 0x18, 0xed, 0x12, 0xdf, 0x72, 0xfd, 0x5b, 0x3d, 0x13, 0xab, 0xcc, 0xce, 0x20, 0x80, 0xd8, 0xe7, + 0x5d, 0x6c, 0xcf, 0x3e, 0x3a, 0x7c, 0x29, 0xda, 0xf4, 0xdb, 0x7a, 0xc0, 0x2a, 0x4d, 0xc7, 0xdc, + 0xe8, 0x09, 0xe6, 0x2a, 0xca, 0x6c, 0x33, 0xed, 0xf1, 0x96, 0xe5, 0x26, 0xb0, 0xc6, 0xcc, 0x22, + 0x15, 0xd2, 0x42, 0x47, 0x71, 0xe5, 0x6d, 0x2e, 0xda, 0xcd, 0x1d, 0x28, 0x59, 0xe9, 0x4d, 0x48, + 0xca, 0x36, 0xd4, 0x85, 0x6a, 0x26, 0x8e, 0x3e, 0xc7, 0xd7, 0x14, 0x77, 0x5e, 0x54, 0xda, 0x98, + 0xf8, 0x65, 0xaf, 0xea, 0x63, 0x46, 0xcd, 0xca, 0xd0, 0xbf, 0x9e, 0x31, 0xb2, 0x24, 0x7f, 0x4e, + 0xe5, 0xa3, 0x32, 0x5e, 0x22, 0x3a, 0xed, 0xed, 0xbe, 0xad, 0x5e, 0xa2, 0x36, 0x07, 0x41, 0x7f, + 0x94, 0x7b, 0x6f, 0x77, 0xea, 0xf6, 0xf3, 0x4e, 0xd3, 0x47, 0x39, 0x9c, 0xd0, 0x96, 0x70, 0x78, + 0x0c, 0x30, 0x9a, 0xa7, 0xe7, 0x85, 0x7e, 0xa6, 0xce, 0x00, 0x86, 0xfb, 0x91, 0xef, 0xe3, 0x31, + 0x1f, 0xc1, 0x5e, 0xda, 0xf3, 0x59, 0xdd, 0x36, 0xfe, 0x19, 0x2b, 0xca, 0xa4, 0x46, 0x5a, 0x52, + 0xaa, 0x65, 0x31, 0x00, 0x0b, 0x61, 0x57, 0x30, 0x8b, 0x0d, 0x13, 0xe6, 0xdc, 0xb3, 0x64, 0x61, + 0x98, 0x07, 0x52, 0xbc, 0x3e, 0x05, 0x26, 0x84, 0x96, 0xd0, 0x85, 0x62, 0x72, 0xd3, 0x9f, 0x60, + 0xf9, 0xc1, 0x33, 0x69, 0x1b, 0x49, 0x3e, 0x74, 0x08, 0x51, 0x2e, 0x97, 0x1b, 0x45, 0x54, 0x7c, + 0x4b, 0xd1, 0x51, 0x83, 0xaa, 0xf0, 0x9b, 0xff, 0x0c, 0xfb, 0x2f, 0x33, 0xcd, 0xe5, 0x1b, 0xcf, + 0x4f, 0x02, 0x0d, 0xf6, 0x1b, 0xdb, 0x48, 0x80, 0x58, 0x80, 0x01, 0x00, 0x00, +}; +#endif // defined(BINDATA_INCLUDE_DATA) + +#if defined(BINDATA_INCLUDE_STORAGE_PVT_DECL) +BINDATA_STORAGE_PVT kgspBinArchiveGspRmCcFmcGfwProdSigned_GH100_ucode_pkey_storage_pvt; +#endif // defined(BINDATA_INCLUDE_STORAGE_PVT_DECL) + +#if defined(BINDATA_INCLUDE_STORAGE_PVT_DEFN) +{ + 384, // uncompressed data size (bytes) + 397, // compressed data size (bytes) + kgspBinArchiveGspRmCcFmcGfwProdSigned_GH100_ucode_pkey_data, // compressed data pointer + NV_TRUE, // is pData compressed? + NV_TRUE, // contain information for file overriding? + NV_FALSE, // is the data referenced during load? (Only valid when BINDATA_IS_MUTABLE is true) +}, +#endif // defined(BINDATA_INCLUDE_STORAGE_PVT_DEFN) + + +#if defined(BINDATA_INCLUDE_ARCHIVE) +// +// Bindata Archive structure +// +static const BINDATA_ARCHIVE __kgspGetBinArchiveGspRmCcFmcGfwProdSigned_GH100 = +{ + 4, // entryNum + { + // entries[] : { "name", pBinStorage } + { "ucode_image" , (const PBINDATA_STORAGE) &g_bindata_pvt.kgspBinArchiveGspRmCcFmcGfwProdSigned_GH100_ucode_image_storage_pvt }, + { "ucode_hash" , (const PBINDATA_STORAGE) &g_bindata_pvt.kgspBinArchiveGspRmCcFmcGfwProdSigned_GH100_ucode_hash_storage_pvt }, + { "ucode_sig" , (const PBINDATA_STORAGE) &g_bindata_pvt.kgspBinArchiveGspRmCcFmcGfwProdSigned_GH100_ucode_sig_storage_pvt }, + { "ucode_pkey" , (const PBINDATA_STORAGE) &g_bindata_pvt.kgspBinArchiveGspRmCcFmcGfwProdSigned_GH100_ucode_pkey_storage_pvt }, + } +}; + +#endif // defined(BINDATA_INCLUDE_ARCHIVE) + + + +#if defined(BINDATA_INCLUDE_FUNCTION) +const BINDATA_ARCHIVE *kgspGetBinArchiveGspRmCcFmcGfwProdSigned_GH100(struct KernelGsp *pKernelGsp) +{ + return &__kgspGetBinArchiveGspRmCcFmcGfwProdSigned_GH100; +} +#endif // defined(BINDATA_INCLUDE_FUNCTION) + + +#if defined(BINDATA_INCLUDE_FUNCTION_STUB) +const BINDATA_ARCHIVE *kgspGetBinArchiveGspRmCcFmcGfwProdSigned_GH100(struct KernelGsp *pKernelGsp) +{ + return NULL; +} +#endif // defined(BINDATA_INCLUDE_FUNCTION_STUB) + + + + + diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/generated/g_bindata_kgspGetBinArchiveGspRmFmcGfwDebugSigned_GH100.c nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_bindata_kgspGetBinArchiveGspRmFmcGfwDebugSigned_GH100.c --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/generated/g_bindata_kgspGetBinArchiveGspRmFmcGfwDebugSigned_GH100.c 2023-10-25 20:19:27.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_bindata_kgspGetBinArchiveGspRmFmcGfwDebugSigned_GH100.c 2024-03-05 22:11:19.000000000 +0000 @@ -29,7755 +29,10332 @@ #if defined(BINDATA_INCLUDE_DATA) // // FUNCTION: kgspGetBinArchiveGspRmFmcGfwDebugSigned_GH100("ucode_image") -// FILE NAME: kernel/inc/gspcc/bin/g_gsp_gh100_dbg_gfw_image.bin +// FILE NAME: kernel/inc/gspcc/bin/g_gsp_gh100_dyn_dbg_gfw_image.bin // FILE TYPE: BINARY // VAR NAME: N/A // COMPRESSION: YES // COMPLEX_STRUCT: NO -// DATA SIZE (bytes): 124232 -// COMPRESSED SIZE (bytes): 123818 +// DATA SIZE (bytes): 165448 +// COMPRESSED SIZE (bytes): 165050 // static BINDATA_CONST NvU8 kgspBinArchiveGspRmFmcGfwDebugSigned_GH100_ucode_image_data[] = { - 0x8c, 0x97, 0xc3, 0x96, 0x28, 0x0a, 0x90, 0x04, 0xdb, 0xb6, 0x6d, 0xdb, 0xb6, 0x6d, 0xdb, 0xb6, - 0x6d, 0xdb, 0xb6, 0x6d, 0xdb, 0xee, 0xdb, 0xb6, 0x6d, 0xdb, 0xf3, 0xce, 0x9c, 0xf9, 0x80, 0xc9, - 0x4d, 0xd5, 0x2e, 0x97, 0x19, 0x01, 0x0c, 0x22, 0x01, 0x00, 0x70, 0x02, 0x08, 0xf0, 0xbf, 0x31, - 0xfa, 0xbf, 0xeb, 0x09, 0x00, 0x00, 0xf2, 0x7f, 0x2f, 0x20, 0x05, 0xc0, 0xff, 0x2b, 0xe9, 0x0a, - 0xac, 0xdf, 0xfd, 0x3d, 0x65, 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0xb1, 0x7a, 0x7b, 0x99, + 0x1d, 0x35, 0x1e, 0xd5, 0x94, 0x82, 0x19, 0x9e, 0x15, 0x5f, 0xa3, 0x71, 0x49, 0xb9, 0x33, 0x13, + 0xf4, 0x5c, 0x0c, 0x46, 0xbc, 0xf1, 0x00, 0x27, 0x88, 0xb8, 0xba, 0xcf, 0x44, 0x0d, 0xc3, 0xbd, + 0xb7, 0x0b, 0x19, 0x22, 0x99, 0xe9, 0xba, 0xe9, 0x09, 0xdc, 0x73, 0x1b, 0xbb, 0x3a, 0x8c, 0xb5, + 0xf0, 0x3a, 0xaf, 0xb0, 0x36, 0xad, 0x0a, 0x12, 0xbe, 0x50, 0xaf, 0x71, 0xde, 0x62, 0xdc, 0x90, + 0x70, 0xe9, 0x32, 0x13, 0xe4, 0x35, 0xc2, 0x51, 0x8b, 0xa2, 0xc8, 0xea, 0x95, 0xd9, 0x98, 0xae, + 0xe2, 0x02, 0x55, 0x70, 0x75, 0x3a, 0x6d, 0x06, 0xbe, 0xe3, 0x0d, 0x50, 0xb7, 0x30, 0xd2, 0x71, + 0xfa, 0x20, 0x3a, 0x87, 0x53, 0xd6, 0x83, 0x96, 0x26, 0xb1, 0xc9, 0xe9, 0x7f, 0x5c, 0x75, 0x5c, + 0x8c, 0xc2, 0xc6, 0x9b, 0x5a, 0x7e, 0x48, 0x86, 0x02, 0x00, }; #endif // defined(BINDATA_INCLUDE_DATA) @@ -7787,8 +10364,8 @@ #if defined(BINDATA_INCLUDE_STORAGE_PVT_DEFN) { - 124232, // uncompressed data size (bytes) - 123818, // compressed data size (bytes) + 165448, // uncompressed data size (bytes) + 165050, // compressed data size (bytes) kgspBinArchiveGspRmFmcGfwDebugSigned_GH100_ucode_image_data, // compressed data pointer NV_TRUE, // is pData compressed? NV_TRUE, // contain information for file overriding? @@ -7800,7 +10377,7 @@ #if defined(BINDATA_INCLUDE_DATA) // // FUNCTION: kgspGetBinArchiveGspRmFmcGfwDebugSigned_GH100("ucode_hash") -// FILE NAME: kernel/inc/gspcc/bin/g_gsp_gh100_dbg_gfw_hash.bin +// FILE NAME: kernel/inc/gspcc/bin/g_gsp_gh100_dyn_dbg_gfw_hash.bin // FILE TYPE: BINARY // VAR NAME: N/A // COMPRESSION: YES @@ -7810,10 +10387,10 @@ // static BINDATA_CONST NvU8 kgspBinArchiveGspRmFmcGfwDebugSigned_GH100_ucode_hash_data[] = { - 0x01, 0x30, 0x00, 0xcf, 0xff, 0x2b, 0x75, 0x8a, 0x60, 0x87, 0x0c, 0xd1, 0xbb, 0x32, 0x64, 0x8a, - 0xeb, 0x3f, 0xbe, 0xd4, 0x9f, 0xa8, 0xc9, 0x29, 0x0b, 0xdf, 0xb3, 0xc3, 0x97, 0x17, 0x8f, 0x35, - 0x37, 0x4d, 0x72, 0x6f, 0x0e, 0xff, 0x41, 0x07, 0x21, 0x37, 0x13, 0x19, 0x1d, 0x11, 0x09, 0xe4, - 0xda, 0x06, 0xc3, 0x6b, 0x3b, 0x91, 0x02, 0xde, 0xbd, 0x30, 0x00, 0x00, 0x00, + 0x01, 0x30, 0x00, 0xcf, 0xff, 0xf8, 0x40, 0x36, 0xc7, 0x8d, 0x10, 0xfa, 0x35, 0x86, 0x87, 0xb1, + 0x1a, 0x5f, 0x14, 0xde, 0x4c, 0x24, 0x02, 0xb4, 0x52, 0x04, 0x5d, 0x12, 0x27, 0xb2, 0x45, 0x3f, + 0xaf, 0xdb, 0x08, 0x0f, 0xdb, 0x66, 0xc3, 0xbd, 0x04, 0x8e, 0xa5, 0x43, 0x12, 0xd0, 0x35, 0x10, + 0x8c, 0x54, 0x9b, 0x7e, 0x23, 0x3d, 0xd2, 0x87, 0x5a, 0x30, 0x00, 0x00, 0x00, }; #endif // defined(BINDATA_INCLUDE_DATA) @@ -7836,7 +10413,7 @@ #if defined(BINDATA_INCLUDE_DATA) // // FUNCTION: kgspGetBinArchiveGspRmFmcGfwDebugSigned_GH100("ucode_sig") -// FILE NAME: kernel/inc/gspcc/bin/g_gsp_gh100_dbg_gfw_sig.bin +// FILE NAME: kernel/inc/gspcc/bin/g_gsp_gh100_dyn_dbg_gfw_sig.bin // FILE TYPE: BINARY // VAR NAME: N/A // COMPRESSION: YES @@ -7846,31 +10423,31 @@ // static BINDATA_CONST NvU8 kgspBinArchiveGspRmFmcGfwDebugSigned_GH100_ucode_sig_data[] = { - 0x01, 0x80, 0x01, 0x7f, 0xfe, 0x5e, 0xf8, 0x92, 0xc4, 0x6a, 0x05, 0xe2, 0x40, 0xce, 0x41, 0x1e, - 0x9c, 0x35, 0xcd, 0x6b, 0xa0, 0xe1, 0x8c, 0x7c, 0xb9, 0x78, 0xbd, 0x3d, 0x47, 0x32, 0x1d, 0xa0, - 0x2a, 0xa7, 0x32, 0x0a, 0x69, 0x69, 0x91, 0xd4, 0x8c, 0xa6, 0xb3, 0x8f, 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0x68, 0x2b, 0x39, 0x2e, 0x91, + 0x6d, 0x0a, 0x85, 0xf6, 0x01, 0x84, 0x49, 0xd8, 0x78, 0x76, 0x68, 0xa1, 0x9b, 0xf4, 0x22, 0x11, + 0xaa, 0x97, 0xc5, 0x37, 0x61, 0xe4, 0x8a, 0xdd, 0xfd, 0xe5, 0x1d, 0xa9, 0xd4, 0xc0, 0x2b, 0x5c, + 0x6b, 0x91, 0x8e, 0x59, 0x1d, 0x7b, 0x36, 0x29, 0xb4, 0xb0, 0x94, 0xc1, 0xca, 0xbd, 0xcd, 0x1a, + 0x2f, 0x96, 0xc6, 0xa9, 0x12, 0x5b, 0x72, 0x57, 0xf4, 0x3e, 0xf5, 0x14, 0x6b, 0x3f, 0x0a, 0x47, + 0x30, 0x56, 0x4a, 0x49, 0xc5, 0x0b, 0xb8, 0x6f, 0xbb, 0x70, 0x0d, 0x29, 0x60, 0xe6, 0x8c, 0x33, + 0x86, 0xc9, 0x81, 0xbf, 0x3e, 0xd0, 0x5f, 0x74, 0x8c, 0x80, 0x01, 0x00, 0x00, }; #endif // defined(BINDATA_INCLUDE_DATA) @@ -7893,7 +10470,7 @@ #if defined(BINDATA_INCLUDE_DATA) // // FUNCTION: kgspGetBinArchiveGspRmFmcGfwDebugSigned_GH100("ucode_pkey") -// FILE NAME: kernel/inc/gspcc/bin/g_gsp_gh100_dbg_gfw_pub_key.bin +// FILE NAME: kernel/inc/gspcc/bin/g_gsp_gh100_dyn_dbg_gfw_pub_key.bin // FILE TYPE: BINARY // VAR NAME: N/A // COMPRESSION: YES diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/generated/g_bindata_kgspGetBinArchiveGspRmFmcGfwProdSigned_GH100.c nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_bindata_kgspGetBinArchiveGspRmFmcGfwProdSigned_GH100.c --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/generated/g_bindata_kgspGetBinArchiveGspRmFmcGfwProdSigned_GH100.c 2023-10-25 20:19:27.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_bindata_kgspGetBinArchiveGspRmFmcGfwProdSigned_GH100.c 2024-03-05 22:11:19.000000000 +0000 @@ -29,7779 +29,10356 @@ #if defined(BINDATA_INCLUDE_DATA) // // FUNCTION: kgspGetBinArchiveGspRmFmcGfwProdSigned_GH100("ucode_image") -// FILE NAME: kernel/inc/gspcc/bin/g_gsp_gh100_prd_gfw_image.bin +// FILE NAME: kernel/inc/gspcc/bin/g_gsp_gh100_dyn_prd_gfw_image.bin // FILE TYPE: BINARY // VAR NAME: N/A // COMPRESSION: YES // COMPLEX_STRUCT: NO -// DATA SIZE (bytes): 124232 -// COMPRESSED SIZE (bytes): 124201 +// DATA SIZE (bytes): 165448 +// COMPRESSED SIZE (bytes): 165429 // static BINDATA_CONST NvU8 kgspBinArchiveGspRmFmcGfwProdSigned_GH100_ucode_image_data[] = { - 0x00, 0x4c, 0x80, 0xb3, 0x7f, 0x03, 0x04, 0x48, 0x00, 0x00, 0xe5, 0x01, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x62, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x79, 0x00, 0x00, 0x04, 0x01, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x28, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xa4, 0xed, 0x6f, - 0x66, 0x9c, 0x74, 0x5c, 0xac, 0xbb, 0xb9, 0xfb, 0x0a, 0x46, 0xe2, 0x3e, 0x88, 0x73, 0xa6, 0xc8, - 0x6a, 0x11, 0x66, 0x1f, 0xe5, 0x88, 0x0b, 0x40, 0x92, 0x29, 0x92, 0x0e, 0x18, 0xee, 0xc3, 0x8c, - 0xc6, 0xf8, 0xc6, 0xbd, 0xa3, 0x41, 0x72, 0x34, 0x62, 0x93, 0xc9, 0x40, 0xea, 0x0d, 0x03, 0x1a, - 0x04, 0x73, 0x3b, 0x68, 0x17, 0x33, 0x67, 0x75, 0xe6, 0xe5, 0x13, 0xc5, 0x7f, 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0x00, }; #endif // defined(BINDATA_INCLUDE_DATA) @@ -7811,8 +10388,8 @@ #if defined(BINDATA_INCLUDE_STORAGE_PVT_DEFN) { - 124232, // uncompressed data size (bytes) - 124201, // compressed data size (bytes) + 165448, // uncompressed data size (bytes) + 165429, // compressed data size (bytes) kgspBinArchiveGspRmFmcGfwProdSigned_GH100_ucode_image_data, // compressed data pointer NV_TRUE, // is pData compressed? NV_TRUE, // contain information for file overriding? @@ -7824,7 +10401,7 @@ #if defined(BINDATA_INCLUDE_DATA) // // FUNCTION: kgspGetBinArchiveGspRmFmcGfwProdSigned_GH100("ucode_hash") -// FILE NAME: kernel/inc/gspcc/bin/g_gsp_gh100_prd_gfw_hash.bin +// FILE NAME: kernel/inc/gspcc/bin/g_gsp_gh100_dyn_prd_gfw_hash.bin // FILE TYPE: BINARY // VAR NAME: N/A // COMPRESSION: YES @@ -7834,10 +10411,10 @@ // static BINDATA_CONST NvU8 kgspBinArchiveGspRmFmcGfwProdSigned_GH100_ucode_hash_data[] = { - 0x01, 0x30, 0x00, 0xcf, 0xff, 0x3a, 0x5c, 0x79, 0x51, 0x33, 0xff, 0xd2, 0xd0, 0xdf, 0xa9, 0x6f, - 0x62, 0x3e, 0xd3, 0xa9, 0x0c, 0x87, 0x97, 0x2e, 0x70, 0x62, 0x43, 0xb1, 0x89, 0xf5, 0x67, 0x58, - 0xaa, 0xa9, 0xc4, 0xd5, 0x68, 0x03, 0x39, 0xaa, 0xfb, 0x3c, 0xeb, 0x11, 0x81, 0xc6, 0xc8, 0xc7, - 0x34, 0xc4, 0x85, 0x59, 0xf0, 0x0f, 0xcb, 0x74, 0x60, 0x30, 0x00, 0x00, 0x00, + 0x01, 0x30, 0x00, 0xcf, 0xff, 0x39, 0xe1, 0x88, 0x6d, 0xa6, 0xcd, 0x3c, 0xe5, 0x12, 0x1d, 0xbf, + 0x58, 0xcb, 0xc1, 0x88, 0xc8, 0x3f, 0xcc, 0x2a, 0x0e, 0x57, 0x6c, 0xb7, 0xf7, 0x1a, 0xfa, 0xd2, + 0xb9, 0x97, 0x93, 0x0a, 0x02, 0xcb, 0x30, 0xac, 0xef, 0x7d, 0x0a, 0x7e, 0xe0, 0x6b, 0x91, 0x65, + 0xd9, 0x68, 0xad, 0x74, 0xad, 0xcd, 0xa1, 0x33, 0x19, 0x30, 0x00, 0x00, 0x00, }; #endif // defined(BINDATA_INCLUDE_DATA) @@ -7860,7 +10437,7 @@ #if defined(BINDATA_INCLUDE_DATA) // // FUNCTION: kgspGetBinArchiveGspRmFmcGfwProdSigned_GH100("ucode_sig") -// FILE NAME: kernel/inc/gspcc/bin/g_gsp_gh100_prd_gfw_sig.bin +// FILE NAME: kernel/inc/gspcc/bin/g_gsp_gh100_dyn_prd_gfw_sig.bin // FILE TYPE: BINARY // VAR NAME: N/A // COMPRESSION: YES @@ -7870,31 +10447,31 @@ // static BINDATA_CONST NvU8 kgspBinArchiveGspRmFmcGfwProdSigned_GH100_ucode_sig_data[] = { - 0x01, 0x80, 0x01, 0x7f, 0xfe, 0x2b, 0xe3, 0x35, 0xee, 0x18, 0xdf, 0xca, 0x3f, 0x66, 0x20, 0xb4, - 0x53, 0x84, 0x89, 0xed, 0xc2, 0x25, 0x72, 0x05, 0xb2, 0xd8, 0x19, 0x8e, 0xab, 0xe0, 0x90, 0xc8, - 0x7c, 0x2e, 0x9c, 0xbc, 0x6a, 0x37, 0x8b, 0xdc, 0x43, 0x37, 0xaf, 0x0c, 0x43, 0xc3, 0xd2, 0xbf, - 0xb2, 0xc7, 0xef, 0xea, 0x90, 0x17, 0x89, 0x2d, 0x3f, 0xca, 0x9f, 0xb8, 0xe8, 0xe7, 0xad, 0xf9, - 0x50, 0xe9, 0xa3, 0xc9, 0x92, 0x94, 0xd8, 0x2b, 0x21, 0x75, 0x67, 0xad, 0x34, 0xae, 0x5b, 0xbf, - 0x91, 0x5d, 0x15, 0x96, 0x15, 0x45, 0xf8, 0xfd, 0xf7, 0x2f, 0xcd, 0x0e, 0xb4, 0x18, 0x46, 0x82, - 0x08, 0x96, 0xa2, 0x6a, 0x2f, 0x1a, 0x6e, 0x6a, 0xfa, 0xcb, 0x56, 0x90, 0x29, 0x68, 0x9a, 0xff, - 0xec, 0x05, 0x60, 0x12, 0x6d, 0x0c, 0x0e, 0x87, 0xff, 0xb0, 0x3f, 0xd6, 0xdf, 0xaa, 0xf9, 0x5f, - 0x63, 0x32, 0xef, 0x76, 0x90, 0x18, 0x0a, 0xac, 0x36, 0x2a, 0xc9, 0xe1, 0x5a, 0x52, 0xe6, 0x00, - 0x2a, 0x41, 0x07, 0x9d, 0x7d, 0x62, 0x28, 0x90, 0x4f, 0x4a, 0x36, 0x8d, 0xec, 0xa4, 0x30, 0xeb, - 0x1f, 0x26, 0xe6, 0x28, 0xa7, 0x1d, 0xa9, 0x72, 0x30, 0xa9, 0x24, 0x05, 0x7c, 0x03, 0xd2, 0x6d, - 0x34, 0x1f, 0x4d, 0x1c, 0xdb, 0xb8, 0xd4, 0x61, 0x72, 0x05, 0xc9, 0xa5, 0xc2, 0xed, 0xda, 0xdc, - 0x37, 0xd1, 0x2f, 0x14, 0x34, 0xe9, 0x2a, 0xb5, 0xc1, 0x2d, 0xb4, 0x3d, 0x6e, 0xbf, 0x88, 0x8b, - 0x1a, 0x6f, 0xb2, 0xd2, 0xd7, 0x5d, 0xe3, 0x29, 0x32, 0xd8, 0xed, 0x38, 0x67, 0x2c, 0x58, 0x28, - 0x4f, 0x8a, 0x29, 0x82, 0xfb, 0x08, 0x7b, 0x4b, 0xa9, 0x45, 0xb8, 0x44, 0x00, 0x3a, 0x0e, 0xb2, - 0xc4, 0xca, 0x23, 0xea, 0x40, 0x8e, 0xe9, 0xb4, 0x28, 0xfb, 0x40, 0x91, 0x40, 0x51, 0xa2, 0xdd, - 0x16, 0xfb, 0x26, 0xd4, 0x92, 0x57, 0x17, 0xe9, 0xaf, 0x66, 0xc9, 0xfe, 0xd5, 0xc9, 0x7c, 0xf5, - 0x66, 0x4c, 0x54, 0x6f, 0x9d, 0x0b, 0x64, 0x55, 0x5c, 0x20, 0xc7, 0x83, 0x77, 0xd4, 0x01, 0x70, - 0x1c, 0xe1, 0x0b, 0xe2, 0xd8, 0x23, 0xfa, 0x31, 0x5a, 0xd1, 0xa5, 0x67, 0x50, 0x96, 0x8f, 0x02, - 0x83, 0xa8, 0x07, 0x8c, 0xef, 0xba, 0x3e, 0x4d, 0x88, 0xe4, 0x54, 0xeb, 0x0c, 0xca, 0x31, 0x8d, - 0xfd, 0x26, 0xcd, 0x31, 0x02, 0xbc, 0x81, 0x6b, 0x51, 0x21, 0x60, 0x11, 0x69, 0xeb, 0x35, 0x9f, - 0xa1, 0x1d, 0x8c, 0x10, 0xfa, 0xb8, 0xd6, 0x1f, 0xe8, 0x41, 0x32, 0xdc, 0x9e, 0xfb, 0x9e, 0xc4, - 0x3b, 0x80, 0xd9, 0x11, 0x71, 0x98, 0x39, 0x6c, 0xbb, 0x35, 0xa2, 0xbe, 0xab, 0xef, 0x57, 0xf8, - 0xd0, 0x1d, 0x47, 0x62, 0xdc, 0x0b, 0x54, 0xdd, 0x50, 0x12, 0x1a, 0x1f, 0x01, 0xba, 0x1d, 0xf0, - 0x30, 0x62, 0xd3, 0xa4, 0xd9, 0xf5, 0xdd, 0xce, 0x1d, 0x80, 0x01, 0x00, 0x00, + 0x01, 0x80, 0x01, 0x7f, 0xfe, 0xa3, 0xd1, 0xed, 0xc9, 0x71, 0x13, 0xe0, 0xd9, 0x9c, 0x39, 0x9d, + 0x14, 0xd4, 0xbd, 0xef, 0x38, 0xdc, 0xe4, 0x9b, 0xd9, 0xf0, 0xd8, 0xce, 0x00, 0xfe, 0x9d, 0x33, + 0x4f, 0x05, 0xd7, 0xf9, 0xdd, 0xf9, 0x37, 0x00, 0x46, 0xe2, 0xf0, 0x39, 0xf5, 0x81, 0x3f, 0x79, + 0x90, 0xef, 0xd3, 0x15, 0x4e, 0xbe, 0xe8, 0x4b, 0x98, 0x20, 0xaa, 0xf2, 0xce, 0xc2, 0x2e, 0x0c, + 0x78, 0x2a, 0x04, 0xf4, 0x30, 0xa6, 0xda, 0xaf, 0x1b, 0xb9, 0xa0, 0x12, 0xa0, 0x4c, 0xb7, 0x49, + 0x6e, 0xd6, 0x4d, 0xac, 0xfa, 0x08, 0x7f, 0x8f, 0xdf, 0x83, 0xff, 0xa9, 0x3e, 0xf4, 0x4e, 0x29, + 0x31, 0x51, 0x15, 0x7c, 0xf0, 0x27, 0x22, 0x81, 0x58, 0x42, 0x79, 0xf6, 0x8d, 0x87, 0x13, 0x48, + 0x54, 0x82, 0x14, 0xac, 0xf1, 0x7e, 0xf5, 0x7c, 0x51, 0xc5, 0xa7, 0xac, 0x4a, 0x38, 0x34, 0x61, + 0xd6, 0xaf, 0xa5, 0x4d, 0xa3, 0x55, 0x60, 0x05, 0x17, 0xda, 0x47, 0x8f, 0xd7, 0x1c, 0x8e, 0x50, + 0x69, 0xaa, 0xa3, 0x1e, 0xfd, 0x10, 0xd8, 0xe1, 0xda, 0xc2, 0x54, 0x8d, 0x48, 0xfd, 0xfc, 0xf8, + 0x66, 0x98, 0x86, 0x99, 0x19, 0xa5, 0x38, 0x3e, 0xcf, 0x95, 0x39, 0x79, 0x26, 0xc8, 0x37, 0x7d, + 0x6c, 0x82, 0x6f, 0x55, 0xa3, 0xb5, 0xf7, 0xf3, 0xb7, 0xa9, 0x0e, 0xb4, 0x9a, 0x99, 0x18, 0x3f, + 0x06, 0x4e, 0x9c, 0x90, 0xe7, 0x61, 0xb1, 0x64, 0xe0, 0x8b, 0x50, 0x49, 0x54, 0xb0, 0xc9, 0xd5, + 0x1b, 0x4c, 0x8f, 0x29, 0x05, 0x6f, 0xe6, 0x90, 0xe7, 0xb5, 0xc4, 0x93, 0x53, 0x27, 0x20, 0x61, + 0xa7, 0x35, 0x0d, 0x12, 0x98, 0xd3, 0x9a, 0x47, 0x20, 0xed, 0xcf, 0x2c, 0x51, 0x00, 0x28, 0xdc, + 0xc7, 0x75, 0x0f, 0x62, 0x19, 0x12, 0xca, 0x1f, 0x3f, 0x9c, 0x0c, 0x1e, 0x2f, 0xf5, 0x15, 0xbc, + 0x2c, 0x78, 0x5b, 0xbd, 0x08, 0x4c, 0xaf, 0x79, 0xf0, 0x75, 0x1b, 0x95, 0x97, 0x19, 0xda, 0x5b, + 0x95, 0x14, 0x9f, 0x50, 0x68, 0x42, 0x83, 0x4e, 0x35, 0x04, 0xec, 0x32, 0x04, 0x9a, 0xe9, 0x83, + 0x5c, 0xde, 0xbc, 0xdd, 0x69, 0xe5, 0xd1, 0x0f, 0xcb, 0x8d, 0xa8, 0xd2, 0x59, 0xf4, 0x04, 0x65, + 0xb1, 0x64, 0xe5, 0xba, 0x99, 0x15, 0x18, 0x3e, 0x14, 0x00, 0x13, 0xfc, 0x38, 0x8e, 0x8c, 0x7f, + 0xb3, 0x06, 0x67, 0xd0, 0x59, 0x34, 0x75, 0x3f, 0x7f, 0x2c, 0x2a, 0xb1, 0xdf, 0x3b, 0x72, 0xd2, + 0xe2, 0x7a, 0xd1, 0x82, 0x7d, 0x2a, 0xef, 0xa5, 0x19, 0x56, 0x50, 0x0a, 0x7b, 0x7c, 0xdc, 0x02, + 0x59, 0x6a, 0xac, 0x30, 0xf2, 0xd6, 0xd5, 0x24, 0x18, 0xae, 0xb2, 0x04, 0x17, 0xce, 0x52, 0x95, + 0x97, 0xe7, 0x38, 0x60, 0xd6, 0x74, 0x5b, 0xb3, 0x5f, 0xd2, 0xee, 0x82, 0xc2, 0xf1, 0x99, 0xe7, + 0x4e, 0x65, 0x9a, 0xf4, 0x86, 0x77, 0x29, 0x5e, 0xfa, 0x80, 0x01, 0x00, 0x00, }; #endif // defined(BINDATA_INCLUDE_DATA) @@ -7917,7 +10494,7 @@ #if defined(BINDATA_INCLUDE_DATA) // // FUNCTION: kgspGetBinArchiveGspRmFmcGfwProdSigned_GH100("ucode_pkey") -// FILE NAME: kernel/inc/gspcc/bin/g_gsp_gh100_prd_gfw_pub_key.bin +// FILE NAME: kernel/inc/gspcc/bin/g_gsp_gh100_dyn_prd_gfw_pub_key.bin // FILE TYPE: BINARY // VAR NAME: N/A // COMPRESSION: YES diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/generated/g_ccsl_nvoc.c nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_ccsl_nvoc.c --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/generated/g_ccsl_nvoc.c 1970-01-01 00:00:00.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_ccsl_nvoc.c 2024-03-05 22:18:06.000000000 +0000 @@ -0,0 +1,88 @@ +#define NVOC_CCSL_H_PRIVATE_ACCESS_ALLOWED +#include "nvoc/runtime.h" +#include "nvoc/rtti.h" +#include "nvtypes.h" +#include "nvport/nvport.h" +#include "nvport/inline/util_valist.h" +#include "utils/nvassert.h" +#include "g_ccsl_nvoc.h" + +#ifdef DEBUG +char __nvoc_class_id_uniqueness_check_0x9bf1a1 = 1; +#endif + +extern const struct NVOC_CLASS_DEF __nvoc_class_def_Ccsl; + +void __nvoc_init_Ccsl(Ccsl*); +void __nvoc_init_funcTable_Ccsl(Ccsl*); +NV_STATUS __nvoc_ctor_Ccsl(Ccsl*); +void __nvoc_init_dataField_Ccsl(Ccsl*); +void __nvoc_dtor_Ccsl(Ccsl*); +extern const struct NVOC_EXPORT_INFO __nvoc_export_info_Ccsl; + +static const struct NVOC_RTTI __nvoc_rtti_Ccsl_Ccsl = { + /*pClassDef=*/ &__nvoc_class_def_Ccsl, + /*dtor=*/ (NVOC_DYNAMIC_DTOR) &__nvoc_dtor_Ccsl, + /*offset=*/ 0, +}; + +static const struct NVOC_CASTINFO __nvoc_castinfo_Ccsl = { + /*numRelatives=*/ 1, + /*relatives=*/ { + &__nvoc_rtti_Ccsl_Ccsl, + }, +}; + +// Not instantiable because it's not derived from class "Object" +const struct NVOC_CLASS_DEF __nvoc_class_def_Ccsl = +{ + /*classInfo=*/ { + /*size=*/ sizeof(Ccsl), + /*classId=*/ classId(Ccsl), + /*providerId=*/ &__nvoc_rtti_provider, +#if NV_PRINTF_STRINGS_ALLOWED + /*name=*/ "Ccsl", +#endif + }, + /*objCreatefn=*/ (NVOC_DYNAMIC_OBJ_CREATE) NULL, + /*pCastInfo=*/ &__nvoc_castinfo_Ccsl, + /*pExportInfo=*/ &__nvoc_export_info_Ccsl +}; + +const struct NVOC_EXPORT_INFO __nvoc_export_info_Ccsl = +{ + /*numEntries=*/ 0, + /*pExportEntries=*/ 0 +}; + +void __nvoc_dtor_Ccsl(Ccsl *pThis) { + PORT_UNREFERENCED_VARIABLE(pThis); +} + +void __nvoc_init_dataField_Ccsl(Ccsl *pThis) { + PORT_UNREFERENCED_VARIABLE(pThis); +} + +NV_STATUS __nvoc_ctor_Ccsl(Ccsl *pThis) { + NV_STATUS status = NV_OK; + __nvoc_init_dataField_Ccsl(pThis); + goto __nvoc_ctor_Ccsl_exit; // Success + +__nvoc_ctor_Ccsl_exit: + + return status; +} + +static void __nvoc_init_funcTable_Ccsl_1(Ccsl *pThis) { + PORT_UNREFERENCED_VARIABLE(pThis); +} + +void __nvoc_init_funcTable_Ccsl(Ccsl *pThis) { + __nvoc_init_funcTable_Ccsl_1(pThis); +} + +void __nvoc_init_Ccsl(Ccsl *pThis) { + pThis->__nvoc_pbase_Ccsl = pThis; + __nvoc_init_funcTable_Ccsl(pThis); +} + diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/generated/g_ccsl_nvoc.h nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_ccsl_nvoc.h --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/generated/g_ccsl_nvoc.h 1970-01-01 00:00:00.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_ccsl_nvoc.h 2024-03-05 22:18:06.000000000 +0000 @@ -0,0 +1,162 @@ +#ifndef _G_CCSL_NVOC_H_ +#define _G_CCSL_NVOC_H_ +#include "nvoc/runtime.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/* + * SPDX-FileCopyrightText: Copyright (c) 2021-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#include "g_ccsl_nvoc.h" + +#ifndef CCSL_H +#define CCSL_H + +#include "nvstatus.h" +#include "nvmisc.h" +#include "kernel/gpu/conf_compute/conf_compute.h" +#include "kernel/gpu/conf_compute/ccsl_context.h" + +#define CCSL_DIR_HOST_TO_DEVICE 0 +#define CCSL_DIR_DEVICE_TO_HOST 1 + +/****************************************************************************\ + * * + * CCSL module header. * + * * + ****************************************************************************/ +#ifdef NVOC_CCSL_H_PRIVATE_ACCESS_ALLOWED +#define PRIVATE_FIELD(x) x +#else +#define PRIVATE_FIELD(x) NVOC_PRIVATE_FIELD(x) +#endif +struct Ccsl { + const struct NVOC_RTTI *__nvoc_rtti; + struct Ccsl *__nvoc_pbase_Ccsl; +}; + +#ifndef __NVOC_CLASS_Ccsl_TYPEDEF__ +#define __NVOC_CLASS_Ccsl_TYPEDEF__ +typedef struct Ccsl Ccsl; +#endif /* __NVOC_CLASS_Ccsl_TYPEDEF__ */ + +#ifndef __nvoc_class_id_Ccsl +#define __nvoc_class_id_Ccsl 0x9bf1a1 +#endif /* __nvoc_class_id_Ccsl */ + +extern const struct NVOC_CLASS_DEF __nvoc_class_def_Ccsl; + +#define __staticCast_Ccsl(pThis) \ + ((pThis)->__nvoc_pbase_Ccsl) + +#ifdef __nvoc_ccsl_h_disabled +#define __dynamicCast_Ccsl(pThis) ((Ccsl*)NULL) +#else //__nvoc_ccsl_h_disabled +#define __dynamicCast_Ccsl(pThis) \ + ((Ccsl*)__nvoc_dynamicCast(staticCast((pThis), Dynamic), classInfo(Ccsl))) +#endif //__nvoc_ccsl_h_disabled + + +NV_STATUS __nvoc_objCreateDynamic_Ccsl(Ccsl**, Dynamic*, NvU32, va_list); + +NV_STATUS __nvoc_objCreate_Ccsl(Ccsl**, Dynamic*, NvU32); +#define __objCreate_Ccsl(ppNewObj, pParent, createFlags) \ + __nvoc_objCreate_Ccsl((ppNewObj), staticCast((pParent), Dynamic), (createFlags)) + +NV_STATUS ccslContextInitViaChannel_IMPL(pCcslContext *ppCtx, NvHandle hClient, NvHandle hChannel); + + +#define ccslContextInitViaChannel(ppCtx, hClient, hChannel) ccslContextInitViaChannel_IMPL(ppCtx, hClient, hChannel) +#define ccslContextInitViaChannel_HAL(ppCtx, hClient, hChannel) ccslContextInitViaChannel(ppCtx, hClient, hChannel) + +NV_STATUS ccslContextInitViaKeyId_KERNEL(struct ConfidentialCompute *pConfCompute, pCcslContext *ppCtx, NvU32 globalKeyId); + + +#define ccslContextInitViaKeyId(pConfCompute, ppCtx, globalKeyId) ccslContextInitViaKeyId_KERNEL(pConfCompute, ppCtx, globalKeyId) +#define ccslContextInitViaKeyId_HAL(pConfCompute, ppCtx, globalKeyId) ccslContextInitViaKeyId(pConfCompute, ppCtx, globalKeyId) + +NV_STATUS ccslRotateIv_IMPL(pCcslContext ctx, NvU8 direction); + + +#define ccslRotateIv(ctx, direction) ccslRotateIv_IMPL(ctx, direction) +#define ccslRotateIv_HAL(ctx, direction) ccslRotateIv(ctx, direction) + +NV_STATUS ccslEncryptWithIv_IMPL(pCcslContext ctx, NvU32 bufferSize, const NvU8 *inputBuffer, NvU8 *encryptIv, const NvU8 *aadBuffer, NvU32 aadSize, NvU8 *outputBuffer, NvU8 *authTagBuffer); + + +#define ccslEncryptWithIv(ctx, bufferSize, inputBuffer, encryptIv, aadBuffer, aadSize, outputBuffer, authTagBuffer) ccslEncryptWithIv_IMPL(ctx, bufferSize, inputBuffer, encryptIv, aadBuffer, aadSize, outputBuffer, authTagBuffer) +#define ccslEncryptWithIv_HAL(ctx, bufferSize, inputBuffer, encryptIv, aadBuffer, aadSize, outputBuffer, authTagBuffer) ccslEncryptWithIv(ctx, bufferSize, inputBuffer, encryptIv, aadBuffer, aadSize, outputBuffer, authTagBuffer) + +NV_STATUS ccslEncrypt_KERNEL(pCcslContext ctx, NvU32 bufferSize, const NvU8 *inputBuffer, const NvU8 *aadBuffer, NvU32 aadSize, NvU8 *outputBuffer, NvU8 *authTagBuffer); + + +#define ccslEncrypt(ctx, bufferSize, inputBuffer, aadBuffer, aadSize, outputBuffer, authTagBuffer) ccslEncrypt_KERNEL(ctx, bufferSize, inputBuffer, aadBuffer, aadSize, outputBuffer, authTagBuffer) +#define ccslEncrypt_HAL(ctx, bufferSize, inputBuffer, aadBuffer, aadSize, outputBuffer, authTagBuffer) ccslEncrypt(ctx, bufferSize, inputBuffer, aadBuffer, aadSize, outputBuffer, authTagBuffer) + +NV_STATUS ccslDecrypt_KERNEL(pCcslContext ctx, NvU32 bufferSize, const NvU8 *inputBuffer, const NvU8 *decryptIv, const NvU8 *aadBuffer, NvU32 aadSize, NvU8 *outputBuffer, const NvU8 *authTagBuffer); + + +#define ccslDecrypt(ctx, bufferSize, inputBuffer, decryptIv, aadBuffer, aadSize, outputBuffer, authTagBuffer) ccslDecrypt_KERNEL(ctx, bufferSize, inputBuffer, decryptIv, aadBuffer, aadSize, outputBuffer, authTagBuffer) +#define ccslDecrypt_HAL(ctx, bufferSize, inputBuffer, decryptIv, aadBuffer, aadSize, outputBuffer, authTagBuffer) ccslDecrypt(ctx, bufferSize, inputBuffer, decryptIv, aadBuffer, aadSize, outputBuffer, authTagBuffer) + +NV_STATUS ccslSign_IMPL(pCcslContext ctx, NvU32 bufferSize, const NvU8 *inputBuffer, NvU8 *authTagBuffer); + + +#define ccslSign(ctx, bufferSize, inputBuffer, authTagBuffer) ccslSign_IMPL(ctx, bufferSize, inputBuffer, authTagBuffer) +#define ccslSign_HAL(ctx, bufferSize, inputBuffer, authTagBuffer) ccslSign(ctx, bufferSize, inputBuffer, authTagBuffer) + +NV_STATUS ccslQueryMessagePool_IMPL(pCcslContext ctx, NvU8 direction, NvU64 *messageNum); + + +#define ccslQueryMessagePool(ctx, direction, messageNum) ccslQueryMessagePool_IMPL(ctx, direction, messageNum) +#define ccslQueryMessagePool_HAL(ctx, direction, messageNum) ccslQueryMessagePool(ctx, direction, messageNum) + +NV_STATUS ccslIncrementIv_IMPL(pCcslContext pCtx, NvU8 direction, NvU64 increment, NvU8 *iv); + + +#define ccslIncrementIv(pCtx, direction, increment, iv) ccslIncrementIv_IMPL(pCtx, direction, increment, iv) +#define ccslIncrementIv_HAL(pCtx, direction, increment, iv) ccslIncrementIv(pCtx, direction, increment, iv) + +void ccslContextClear_IMPL(pCcslContext ctx); + +#define ccslContextClear(ctx) ccslContextClear_IMPL(ctx) +NV_STATUS ccslIncrementCounter_IMPL(pCcslContext pCtx, NvU8 *ctr, NvU64 increment); + +#define ccslIncrementCounter(pCtx, ctr, increment) ccslIncrementCounter_IMPL(pCtx, ctr, increment) +#undef PRIVATE_FIELD + +#ifndef NVOC_CCSL_H_PRIVATE_ACCESS_ALLOWED +#undef ccslIncrementCounter +NV_STATUS NVOC_PRIVATE_FUNCTION(ccslIncrementCounter)(pCcslContext pCtx, NvU8 *ctr, NvU64 increment); + +#endif // NVOC_CCSL_H_PRIVATE_ACCESS_ALLOWED + + +#endif // CCSL_H + +#ifdef __cplusplus +} // extern "C" +#endif +#endif // _G_CCSL_NVOC_H_ diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/generated/g_ce_utils_nvoc.c nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_ce_utils_nvoc.c --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/generated/g_ce_utils_nvoc.c 1970-01-01 00:00:00.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_ce_utils_nvoc.c 2024-03-05 22:18:06.000000000 +0000 @@ -0,0 +1,166 @@ +#define NVOC_CE_UTILS_H_PRIVATE_ACCESS_ALLOWED +#include "nvoc/runtime.h" +#include "nvoc/rtti.h" +#include "nvtypes.h" +#include "nvport/nvport.h" +#include "nvport/inline/util_valist.h" +#include "utils/nvassert.h" +#include "g_ce_utils_nvoc.h" + +#ifdef DEBUG +char __nvoc_class_id_uniqueness_check_0x8b8bae = 1; +#endif + +extern const struct NVOC_CLASS_DEF __nvoc_class_def_CeUtils; + +extern const struct NVOC_CLASS_DEF __nvoc_class_def_Object; + +void __nvoc_init_CeUtils(CeUtils*); +void __nvoc_init_funcTable_CeUtils(CeUtils*); +NV_STATUS __nvoc_ctor_CeUtils(CeUtils*, struct OBJGPU * arg_pGpu, KERNEL_MIG_GPU_INSTANCE * arg_pKernelMIGGPUInstance, NV0050_ALLOCATION_PARAMETERS * arg_pAllocParams); +void __nvoc_init_dataField_CeUtils(CeUtils*); +void __nvoc_dtor_CeUtils(CeUtils*); +extern const struct NVOC_EXPORT_INFO __nvoc_export_info_CeUtils; + +static const struct NVOC_RTTI __nvoc_rtti_CeUtils_CeUtils = { + /*pClassDef=*/ &__nvoc_class_def_CeUtils, + /*dtor=*/ (NVOC_DYNAMIC_DTOR) &__nvoc_dtor_CeUtils, + /*offset=*/ 0, +}; + +static const struct NVOC_RTTI __nvoc_rtti_CeUtils_Object = { + /*pClassDef=*/ &__nvoc_class_def_Object, + /*dtor=*/ &__nvoc_destructFromBase, + /*offset=*/ NV_OFFSETOF(CeUtils, __nvoc_base_Object), +}; + +static const struct NVOC_CASTINFO __nvoc_castinfo_CeUtils = { + /*numRelatives=*/ 2, + /*relatives=*/ { + &__nvoc_rtti_CeUtils_CeUtils, + &__nvoc_rtti_CeUtils_Object, + }, +}; + +const struct NVOC_CLASS_DEF __nvoc_class_def_CeUtils = +{ + /*classInfo=*/ { + /*size=*/ sizeof(CeUtils), + /*classId=*/ classId(CeUtils), + /*providerId=*/ &__nvoc_rtti_provider, +#if NV_PRINTF_STRINGS_ALLOWED + /*name=*/ "CeUtils", +#endif + }, + /*objCreatefn=*/ (NVOC_DYNAMIC_OBJ_CREATE) &__nvoc_objCreateDynamic_CeUtils, + /*pCastInfo=*/ &__nvoc_castinfo_CeUtils, + /*pExportInfo=*/ &__nvoc_export_info_CeUtils +}; + +const struct NVOC_EXPORT_INFO __nvoc_export_info_CeUtils = +{ + /*numEntries=*/ 0, + /*pExportEntries=*/ 0 +}; + +void __nvoc_dtor_Object(Object*); +void __nvoc_dtor_CeUtils(CeUtils *pThis) { + __nvoc_ceutilsDestruct(pThis); + __nvoc_dtor_Object(&pThis->__nvoc_base_Object); + PORT_UNREFERENCED_VARIABLE(pThis); +} + +void __nvoc_init_dataField_CeUtils(CeUtils *pThis) { + PORT_UNREFERENCED_VARIABLE(pThis); +} + +NV_STATUS __nvoc_ctor_Object(Object* ); +NV_STATUS __nvoc_ctor_CeUtils(CeUtils *pThis, struct OBJGPU * arg_pGpu, KERNEL_MIG_GPU_INSTANCE * arg_pKernelMIGGPUInstance, NV0050_ALLOCATION_PARAMETERS * arg_pAllocParams) { + NV_STATUS status = NV_OK; + status = __nvoc_ctor_Object(&pThis->__nvoc_base_Object); + if (status != NV_OK) goto __nvoc_ctor_CeUtils_fail_Object; + __nvoc_init_dataField_CeUtils(pThis); + + status = __nvoc_ceutilsConstruct(pThis, arg_pGpu, arg_pKernelMIGGPUInstance, arg_pAllocParams); + if (status != NV_OK) goto __nvoc_ctor_CeUtils_fail__init; + goto __nvoc_ctor_CeUtils_exit; // Success + +__nvoc_ctor_CeUtils_fail__init: + __nvoc_dtor_Object(&pThis->__nvoc_base_Object); +__nvoc_ctor_CeUtils_fail_Object: +__nvoc_ctor_CeUtils_exit: + + return status; +} + +static void __nvoc_init_funcTable_CeUtils_1(CeUtils *pThis) { + PORT_UNREFERENCED_VARIABLE(pThis); +} + +void __nvoc_init_funcTable_CeUtils(CeUtils *pThis) { + __nvoc_init_funcTable_CeUtils_1(pThis); +} + +void __nvoc_init_Object(Object*); +void __nvoc_init_CeUtils(CeUtils *pThis) { + pThis->__nvoc_pbase_CeUtils = pThis; + pThis->__nvoc_pbase_Object = &pThis->__nvoc_base_Object; + __nvoc_init_Object(&pThis->__nvoc_base_Object); + __nvoc_init_funcTable_CeUtils(pThis); +} + +NV_STATUS __nvoc_objCreate_CeUtils(CeUtils **ppThis, Dynamic *pParent, NvU32 createFlags, struct OBJGPU * arg_pGpu, KERNEL_MIG_GPU_INSTANCE * arg_pKernelMIGGPUInstance, NV0050_ALLOCATION_PARAMETERS * arg_pAllocParams) { + NV_STATUS status; + Object *pParentObj; + CeUtils *pThis; + + status = __nvoc_handleObjCreateMemAlloc(createFlags, sizeof(CeUtils), (void**)&pThis, (void**)ppThis); + if (status != NV_OK) + return status; + + portMemSet(pThis, 0, sizeof(CeUtils)); + + __nvoc_initRtti(staticCast(pThis, Dynamic), &__nvoc_class_def_CeUtils); + + pThis->__nvoc_base_Object.createFlags = createFlags; + + if (pParent != NULL && !(createFlags & NVOC_OBJ_CREATE_FLAGS_PARENT_HALSPEC_ONLY)) + { + pParentObj = dynamicCast(pParent, Object); + objAddChild(pParentObj, &pThis->__nvoc_base_Object); + } + else + { + pThis->__nvoc_base_Object.pParent = NULL; + } + + __nvoc_init_CeUtils(pThis); + status = __nvoc_ctor_CeUtils(pThis, arg_pGpu, arg_pKernelMIGGPUInstance, arg_pAllocParams); + if (status != NV_OK) goto __nvoc_objCreate_CeUtils_cleanup; + + *ppThis = pThis; + + return NV_OK; + +__nvoc_objCreate_CeUtils_cleanup: + // do not call destructors here since the constructor already called them + if (createFlags & NVOC_OBJ_CREATE_FLAGS_IN_PLACE_CONSTRUCT) + portMemSet(pThis, 0, sizeof(CeUtils)); + else + portMemFree(pThis); + + // coverity[leaked_storage:FALSE] + return status; +} + +NV_STATUS __nvoc_objCreateDynamic_CeUtils(CeUtils **ppThis, Dynamic *pParent, NvU32 createFlags, va_list args) { + NV_STATUS status; + struct OBJGPU * arg_pGpu = va_arg(args, struct OBJGPU *); + KERNEL_MIG_GPU_INSTANCE * arg_pKernelMIGGPUInstance = va_arg(args, KERNEL_MIG_GPU_INSTANCE *); + NV0050_ALLOCATION_PARAMETERS * arg_pAllocParams = va_arg(args, NV0050_ALLOCATION_PARAMETERS *); + + status = __nvoc_objCreate_CeUtils(ppThis, pParent, createFlags, arg_pGpu, arg_pKernelMIGGPUInstance, arg_pAllocParams); + + return status; +} + diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/generated/g_ce_utils_nvoc.h nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_ce_utils_nvoc.h --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/generated/g_ce_utils_nvoc.h 1970-01-01 00:00:00.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_ce_utils_nvoc.h 2024-03-05 22:18:06.000000000 +0000 @@ -0,0 +1,201 @@ +#ifndef _G_CE_UTILS_NVOC_H_ +#define _G_CE_UTILS_NVOC_H_ +#include "nvoc/runtime.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/* + * SPDX-FileCopyrightText: Copyright (c) 2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#include "g_ce_utils_nvoc.h" + +#ifndef CE_UTILS_H +#define CE_UTILS_H + +#include "gpu/gpu_resource.h" // GpuResource +#include "class/cl0050.h" +#include "ctrl/ctrl0050.h" + +#include "kernel/gpu/mem_mgr/channel_utils.h" + +typedef struct +{ + MEMORY_DESCRIPTOR *pMemDesc; + NvU64 offset; + NvU64 length; + NvU32 pattern; + NvU64 flags; + NvU64 submittedWorkId; // Payload to poll for async completion +} CEUTILS_MEMSET_PARAMS; + +typedef struct +{ + MEMORY_DESCRIPTOR *pSrcMemDesc; + MEMORY_DESCRIPTOR *pDstMemDesc; + NvU64 dstOffset; + NvU64 srcOffset; + NvU64 length; + NvU64 flags; + NvU64 submittedWorkId; // Payload to poll for async completion +} CEUTILS_MEMCOPY_PARAMS; + + +#ifdef NVOC_CE_UTILS_H_PRIVATE_ACCESS_ALLOWED +#define PRIVATE_FIELD(x) x +#else +#define PRIVATE_FIELD(x) NVOC_PRIVATE_FIELD(x) +#endif +struct CeUtils { + const struct NVOC_RTTI *__nvoc_rtti; + struct Object __nvoc_base_Object; + struct Object *__nvoc_pbase_Object; + struct CeUtils *__nvoc_pbase_CeUtils; + NvHandle hClient; + NvHandle hDevice; + NvHandle hSubdevice; + OBJCHANNEL *pChannel; + struct OBJGPU *pGpu; + struct KernelCE *pKCe; + NvBool bUseVasForCeCopy; + NvU32 hTdCopyClass; + NvU64 lastSubmittedPayload; + NvU64 lastCompletedPayload; +}; + +#ifndef __NVOC_CLASS_CeUtils_TYPEDEF__ +#define __NVOC_CLASS_CeUtils_TYPEDEF__ +typedef struct CeUtils CeUtils; +#endif /* __NVOC_CLASS_CeUtils_TYPEDEF__ */ + +#ifndef __nvoc_class_id_CeUtils +#define __nvoc_class_id_CeUtils 0x8b8bae +#endif /* __nvoc_class_id_CeUtils */ + +extern const struct NVOC_CLASS_DEF __nvoc_class_def_CeUtils; + +#define __staticCast_CeUtils(pThis) \ + ((pThis)->__nvoc_pbase_CeUtils) + +#ifdef __nvoc_ce_utils_h_disabled +#define __dynamicCast_CeUtils(pThis) ((CeUtils*)NULL) +#else //__nvoc_ce_utils_h_disabled +#define __dynamicCast_CeUtils(pThis) \ + ((CeUtils*)__nvoc_dynamicCast(staticCast((pThis), Dynamic), classInfo(CeUtils))) +#endif //__nvoc_ce_utils_h_disabled + + +NV_STATUS __nvoc_objCreateDynamic_CeUtils(CeUtils**, Dynamic*, NvU32, va_list); + +NV_STATUS __nvoc_objCreate_CeUtils(CeUtils**, Dynamic*, NvU32, struct OBJGPU * arg_pGpu, KERNEL_MIG_GPU_INSTANCE * arg_pKernelMIGGPUInstance, NV0050_ALLOCATION_PARAMETERS * arg_pAllocParams); +#define __objCreate_CeUtils(ppNewObj, pParent, createFlags, arg_pGpu, arg_pKernelMIGGPUInstance, arg_pAllocParams) \ + __nvoc_objCreate_CeUtils((ppNewObj), staticCast((pParent), Dynamic), (createFlags), arg_pGpu, arg_pKernelMIGGPUInstance, arg_pAllocParams) + +NV_STATUS ceutilsConstruct_IMPL(struct CeUtils *arg_pCeUtils, struct OBJGPU *arg_pGpu, KERNEL_MIG_GPU_INSTANCE *arg_pKernelMIGGPUInstance, NV0050_ALLOCATION_PARAMETERS *arg_pAllocParams); + +#define __nvoc_ceutilsConstruct(arg_pCeUtils, arg_pGpu, arg_pKernelMIGGPUInstance, arg_pAllocParams) ceutilsConstruct_IMPL(arg_pCeUtils, arg_pGpu, arg_pKernelMIGGPUInstance, arg_pAllocParams) +void ceutilsDestruct_IMPL(struct CeUtils *pCeUtils); + +#define __nvoc_ceutilsDestruct(pCeUtils) ceutilsDestruct_IMPL(pCeUtils) +NV_STATUS ceutilsMemset_IMPL(struct CeUtils *pCeUtils, CEUTILS_MEMSET_PARAMS *pParams); + +#ifdef __nvoc_ce_utils_h_disabled +static inline NV_STATUS ceutilsMemset(struct CeUtils *pCeUtils, CEUTILS_MEMSET_PARAMS *pParams) { + NV_ASSERT_FAILED_PRECOMP("CeUtils was disabled!"); + return NV_ERR_NOT_SUPPORTED; +} +#else //__nvoc_ce_utils_h_disabled +#define ceutilsMemset(pCeUtils, pParams) ceutilsMemset_IMPL(pCeUtils, pParams) +#endif //__nvoc_ce_utils_h_disabled + +NV_STATUS ceutilsMemcopy_IMPL(struct CeUtils *pCeUtils, CEUTILS_MEMCOPY_PARAMS *pParams); + +#ifdef __nvoc_ce_utils_h_disabled +static inline NV_STATUS ceutilsMemcopy(struct CeUtils *pCeUtils, CEUTILS_MEMCOPY_PARAMS *pParams) { + NV_ASSERT_FAILED_PRECOMP("CeUtils was disabled!"); + return NV_ERR_NOT_SUPPORTED; +} +#else //__nvoc_ce_utils_h_disabled +#define ceutilsMemcopy(pCeUtils, pParams) ceutilsMemcopy_IMPL(pCeUtils, pParams) +#endif //__nvoc_ce_utils_h_disabled + +NvU64 ceutilsUpdateProgress_IMPL(struct CeUtils *pCeUtils); + +#ifdef __nvoc_ce_utils_h_disabled +static inline NvU64 ceutilsUpdateProgress(struct CeUtils *pCeUtils) { + NV_ASSERT_FAILED_PRECOMP("CeUtils was disabled!"); + return 0; +} +#else //__nvoc_ce_utils_h_disabled +#define ceutilsUpdateProgress(pCeUtils) ceutilsUpdateProgress_IMPL(pCeUtils) +#endif //__nvoc_ce_utils_h_disabled + +void ceutilsServiceInterrupts_IMPL(struct CeUtils *pCeUtils); + +#ifdef __nvoc_ce_utils_h_disabled +static inline void ceutilsServiceInterrupts(struct CeUtils *pCeUtils) { + NV_ASSERT_FAILED_PRECOMP("CeUtils was disabled!"); +} +#else //__nvoc_ce_utils_h_disabled +#define ceutilsServiceInterrupts(pCeUtils) ceutilsServiceInterrupts_IMPL(pCeUtils) +#endif //__nvoc_ce_utils_h_disabled + +#undef PRIVATE_FIELD + + + +#if defined(DEBUG) || defined (DEVELOP) +NVOC_PREFIX(ceutilsapi) class CeUtilsApi : GpuResource +{ +public: + NV_STATUS ceutilsapiConstruct(CeUtilsApi *pCeUtilsApi, CALL_CONTEXT *pCallContext, + RS_RES_ALLOC_PARAMS_INTERNAL *pParams) + : GpuResource(pCallContext, pParams); + + void ceutilsapiDestruct(CeUtilsApi *pCeUtilsApi); + + // + // Below APIs are only provided for SRT testing, thus only available for debug or + // develop driver builds + // + // + RMCTRL_EXPORT(NV0050_CTRL_CMD_MEMSET, RMCTRL_FLAGS(PRIVILEGED, API_LOCK_READONLY)) + NV_STATUS ceutilsapiCtrlCmdMemset(CeUtilsApi *pCeUtilsApi, NV0050_CTRL_MEMSET_PARAMS *pParams); + + RMCTRL_EXPORT(NV0050_CTRL_CMD_MEMCOPY, RMCTRL_FLAGS(PRIVILEGED, API_LOCK_READONLY)) + NV_STATUS ceutilsapiCtrlCmdMemcopy(CeUtilsApi *pCeUtilsApi, NV0050_CTRL_MEMCOPY_PARAMS *pParams); + + RMCTRL_EXPORT(NV0050_CTRL_CMD_CHECK_PROGRESS, RMCTRL_FLAGS(PRIVILEGED, API_LOCK_READONLY)) + NV_STATUS ceutilsapiCtrlCmdCheckProgress(CeUtilsApi *pCeUtilsApi, NV0050_CTRL_CHECK_PROGRESS_PARAMS *pParams); + + CeUtils *pCeUtils; +}; +#endif + +#endif // CE_UTILS_H + +#ifdef __cplusplus +} // extern "C" +#endif +#endif // _G_CE_UTILS_NVOC_H_ diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/generated/g_channel_descendant_nvoc.c nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_channel_descendant_nvoc.c --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/generated/g_channel_descendant_nvoc.c 2023-10-25 20:26:52.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_channel_descendant_nvoc.c 2024-03-05 22:18:07.000000000 +0000 @@ -119,14 +119,14 @@ return gpuresShareCallback((struct GpuResource *)(((unsigned char *)pGpuResource) + __nvoc_rtti_ChannelDescendant_GpuResource.offset), pInvokingClient, pParentRef, pSharePolicy); } -static NV_STATUS __nvoc_thunk_RsResource_chandesMapTo(struct ChannelDescendant *pResource, RS_RES_MAP_TO_PARAMS *pParams) { - return resMapTo((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_ChannelDescendant_RsResource.offset), pParams); -} - static NV_STATUS __nvoc_thunk_Notifier_chandesGetOrAllocNotifShare(struct ChannelDescendant *pNotifier, NvHandle hNotifierClient, NvHandle hNotifierResource, struct NotifShare **ppNotifShare) { return notifyGetOrAllocNotifShare((struct Notifier *)(((unsigned char *)pNotifier) + __nvoc_rtti_ChannelDescendant_Notifier.offset), hNotifierClient, hNotifierResource, ppNotifShare); } +static NV_STATUS __nvoc_thunk_RsResource_chandesMapTo(struct ChannelDescendant *pResource, RS_RES_MAP_TO_PARAMS *pParams) { + return resMapTo((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_ChannelDescendant_RsResource.offset), pParams); +} + static NV_STATUS __nvoc_thunk_GpuResource_chandesGetMapAddrSpace(struct ChannelDescendant *pGpuResource, struct CALL_CONTEXT *pCallContext, NvU32 mapFlags, NV_ADDRESS_SPACE *pAddrSpace) { return gpuresGetMapAddrSpace((struct GpuResource *)(((unsigned char *)pGpuResource) + __nvoc_rtti_ChannelDescendant_GpuResource.offset), pCallContext, mapFlags, pAddrSpace); } @@ -195,6 +195,10 @@ return notifyUnregisterEvent((struct Notifier *)(((unsigned char *)pNotifier) + __nvoc_rtti_ChannelDescendant_Notifier.offset), hNotifierClient, hNotifierResource, hEventClient, hEvent); } +static NV_STATUS __nvoc_thunk_RmResource_chandesControlSerialization_Prologue(struct ChannelDescendant *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return rmresControlSerialization_Prologue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_ChannelDescendant_RmResource.offset), pCallContext, pParams); +} + static NvBool __nvoc_thunk_RsResource_chandesCanCopy(struct ChannelDescendant *pResource) { return resCanCopy((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_ChannelDescendant_RsResource.offset)); } @@ -207,6 +211,10 @@ return resIsDuplicate((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_ChannelDescendant_RsResource.offset), hMemory, pDuplicate); } +static void __nvoc_thunk_RmResource_chandesControlSerialization_Epilogue(struct ChannelDescendant *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + rmresControlSerialization_Epilogue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_ChannelDescendant_RmResource.offset), pCallContext, pParams); +} + static PEVENTNOTIFICATION *__nvoc_thunk_Notifier_chandesGetNotificationListPtr(struct ChannelDescendant *pNotifier) { return notifyGetNotificationListPtr((struct Notifier *)(((unsigned char *)pNotifier) + __nvoc_rtti_ChannelDescendant_Notifier.offset)); } @@ -289,10 +297,10 @@ pThis->__chandesShareCallback__ = &__nvoc_thunk_GpuResource_chandesShareCallback; - pThis->__chandesMapTo__ = &__nvoc_thunk_RsResource_chandesMapTo; - pThis->__chandesGetOrAllocNotifShare__ = &__nvoc_thunk_Notifier_chandesGetOrAllocNotifShare; + pThis->__chandesMapTo__ = &__nvoc_thunk_RsResource_chandesMapTo; + pThis->__chandesGetMapAddrSpace__ = &__nvoc_thunk_GpuResource_chandesGetMapAddrSpace; pThis->__chandesSetNotificationShare__ = &__nvoc_thunk_Notifier_chandesSetNotificationShare; @@ -327,12 +335,16 @@ pThis->__chandesUnregisterEvent__ = &__nvoc_thunk_Notifier_chandesUnregisterEvent; + pThis->__chandesControlSerialization_Prologue__ = &__nvoc_thunk_RmResource_chandesControlSerialization_Prologue; + pThis->__chandesCanCopy__ = &__nvoc_thunk_RsResource_chandesCanCopy; pThis->__chandesPreDestruct__ = &__nvoc_thunk_RsResource_chandesPreDestruct; pThis->__chandesIsDuplicate__ = &__nvoc_thunk_RsResource_chandesIsDuplicate; + pThis->__chandesControlSerialization_Epilogue__ = &__nvoc_thunk_RmResource_chandesControlSerialization_Epilogue; + pThis->__chandesGetNotificationListPtr__ = &__nvoc_thunk_Notifier_chandesGetNotificationListPtr; pThis->__chandesGetNotificationShare__ = &__nvoc_thunk_Notifier_chandesGetNotificationShare; @@ -368,13 +380,16 @@ ChannelDescendant *pThis; RmHalspecOwner *pRmhalspecowner; - pThis = portMemAllocNonPaged(sizeof(ChannelDescendant)); - if (pThis == NULL) return NV_ERR_NO_MEMORY; + status = __nvoc_handleObjCreateMemAlloc(createFlags, sizeof(ChannelDescendant), (void**)&pThis, (void**)ppThis); + if (status != NV_OK) + return status; portMemSet(pThis, 0, sizeof(ChannelDescendant)); __nvoc_initRtti(staticCast(pThis, Dynamic), &__nvoc_class_def_ChannelDescendant); + pThis->__nvoc_base_GpuResource.__nvoc_base_RmResource.__nvoc_base_RsResource.__nvoc_base_Object.createFlags = createFlags; + if (pParent != NULL && !(createFlags & NVOC_OBJ_CREATE_FLAGS_PARENT_HALSPEC_ONLY)) { pParentObj = dynamicCast(pParent, Object); @@ -394,11 +409,17 @@ if (status != NV_OK) goto __nvoc_objCreate_ChannelDescendant_cleanup; *ppThis = pThis; + return NV_OK; __nvoc_objCreate_ChannelDescendant_cleanup: // do not call destructors here since the constructor already called them - portMemFree(pThis); + if (createFlags & NVOC_OBJ_CREATE_FLAGS_IN_PLACE_CONSTRUCT) + portMemSet(pThis, 0, sizeof(ChannelDescendant)); + else + portMemFree(pThis); + + // coverity[leaked_storage:FALSE] return status; } diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/generated/g_channel_descendant_nvoc.h nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_channel_descendant_nvoc.h --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/generated/g_channel_descendant_nvoc.h 2023-10-25 20:26:52.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_channel_descendant_nvoc.h 2024-03-05 22:18:07.000000000 +0000 @@ -85,7 +85,7 @@ */ typedef struct _METHOD METHOD, *PMETHOD; -typedef NV_STATUS (*METHODPROC)(OBJGPU *, struct ChannelDescendant *, PMETHOD, NvU32, NvV32); +typedef NV_STATUS (*METHODPROC)(OBJGPU *, struct ChannelDescendant *, NvU32, NvV32); struct _METHOD { @@ -122,12 +122,12 @@ struct INotifier *__nvoc_pbase_INotifier; struct Notifier *__nvoc_pbase_Notifier; struct ChannelDescendant *__nvoc_pbase_ChannelDescendant; - NV_STATUS (*__chandesGetSwMethods__)(struct ChannelDescendant *, METHOD **, NvU32 *); + NV_STATUS (*__chandesGetSwMethods__)(struct ChannelDescendant *, const METHOD **, NvU32 *); NvBool (*__chandesIsSwMethodStalling__)(struct ChannelDescendant *, NvU32); NV_STATUS (*__chandesCheckMemInterUnmap__)(struct ChannelDescendant *, NvBool); NvBool (*__chandesShareCallback__)(struct ChannelDescendant *, struct RsClient *, struct RsResourceRef *, RS_SHARE_POLICY *); - NV_STATUS (*__chandesMapTo__)(struct ChannelDescendant *, RS_RES_MAP_TO_PARAMS *); NV_STATUS (*__chandesGetOrAllocNotifShare__)(struct ChannelDescendant *, NvHandle, NvHandle, struct NotifShare **); + NV_STATUS (*__chandesMapTo__)(struct ChannelDescendant *, RS_RES_MAP_TO_PARAMS *); NV_STATUS (*__chandesGetMapAddrSpace__)(struct ChannelDescendant *, struct CALL_CONTEXT *, NvU32, NV_ADDRESS_SPACE *); void (*__chandesSetNotificationShare__)(struct ChannelDescendant *, struct NotifShare *); NvU32 (*__chandesGetRefCount__)(struct ChannelDescendant *); @@ -145,9 +145,11 @@ NV_STATUS (*__chandesGetMemoryMappingDescriptor__)(struct ChannelDescendant *, struct MEMORY_DESCRIPTOR **); NV_STATUS (*__chandesControlFilter__)(struct ChannelDescendant *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); NV_STATUS (*__chandesUnregisterEvent__)(struct ChannelDescendant *, NvHandle, NvHandle, NvHandle, NvHandle); + NV_STATUS (*__chandesControlSerialization_Prologue__)(struct ChannelDescendant *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); NvBool (*__chandesCanCopy__)(struct ChannelDescendant *); void (*__chandesPreDestruct__)(struct ChannelDescendant *); NV_STATUS (*__chandesIsDuplicate__)(struct ChannelDescendant *, NvHandle, NvBool *); + void (*__chandesControlSerialization_Epilogue__)(struct ChannelDescendant *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); PEVENTNOTIFICATION *(*__chandesGetNotificationListPtr__)(struct ChannelDescendant *); struct NotifShare *(*__chandesGetNotificationShare__)(struct ChannelDescendant *); NV_STATUS (*__chandesMap__)(struct ChannelDescendant *, struct CALL_CONTEXT *, struct RS_CPU_MAP_PARAMS *, struct RsCpuMapping *); @@ -191,8 +193,8 @@ #define chandesIsSwMethodStalling(pChannelDescendant, hHandle) chandesIsSwMethodStalling_DISPATCH(pChannelDescendant, hHandle) #define chandesCheckMemInterUnmap(pChannelDescendant, bSubdeviceHandleProvided) chandesCheckMemInterUnmap_DISPATCH(pChannelDescendant, bSubdeviceHandleProvided) #define chandesShareCallback(pGpuResource, pInvokingClient, pParentRef, pSharePolicy) chandesShareCallback_DISPATCH(pGpuResource, pInvokingClient, pParentRef, pSharePolicy) -#define chandesMapTo(pResource, pParams) chandesMapTo_DISPATCH(pResource, pParams) #define chandesGetOrAllocNotifShare(pNotifier, hNotifierClient, hNotifierResource, ppNotifShare) chandesGetOrAllocNotifShare_DISPATCH(pNotifier, hNotifierClient, hNotifierResource, ppNotifShare) +#define chandesMapTo(pResource, pParams) chandesMapTo_DISPATCH(pResource, pParams) #define chandesGetMapAddrSpace(pGpuResource, pCallContext, mapFlags, pAddrSpace) chandesGetMapAddrSpace_DISPATCH(pGpuResource, pCallContext, mapFlags, pAddrSpace) #define chandesSetNotificationShare(pNotifier, pNotifShare) chandesSetNotificationShare_DISPATCH(pNotifier, pNotifShare) #define chandesGetRefCount(pResource) chandesGetRefCount_DISPATCH(pResource) @@ -210,9 +212,11 @@ #define chandesGetMemoryMappingDescriptor(pRmResource, ppMemDesc) chandesGetMemoryMappingDescriptor_DISPATCH(pRmResource, ppMemDesc) #define chandesControlFilter(pResource, pCallContext, pParams) chandesControlFilter_DISPATCH(pResource, pCallContext, pParams) #define chandesUnregisterEvent(pNotifier, hNotifierClient, hNotifierResource, hEventClient, hEvent) chandesUnregisterEvent_DISPATCH(pNotifier, hNotifierClient, hNotifierResource, hEventClient, hEvent) +#define chandesControlSerialization_Prologue(pResource, pCallContext, pParams) chandesControlSerialization_Prologue_DISPATCH(pResource, pCallContext, pParams) #define chandesCanCopy(pResource) chandesCanCopy_DISPATCH(pResource) #define chandesPreDestruct(pResource) chandesPreDestruct_DISPATCH(pResource) #define chandesIsDuplicate(pResource, hMemory, pDuplicate) chandesIsDuplicate_DISPATCH(pResource, hMemory, pDuplicate) +#define chandesControlSerialization_Epilogue(pResource, pCallContext, pParams) chandesControlSerialization_Epilogue_DISPATCH(pResource, pCallContext, pParams) #define chandesGetNotificationListPtr(pNotifier) chandesGetNotificationListPtr_DISPATCH(pNotifier) #define chandesGetNotificationShare(pNotifier) chandesGetNotificationShare_DISPATCH(pNotifier) #define chandesMap(pGpuResource, pCallContext, pParams, pCpuMapping) chandesMap_DISPATCH(pGpuResource, pCallContext, pParams, pCpuMapping) @@ -247,9 +251,9 @@ #define chandesDestroy_HAL(pChannelDescendant) chandesDestroy(pChannelDescendant) -NV_STATUS chandesGetSwMethods_IMPL(struct ChannelDescendant *pChannelDescendant, METHOD **ppMethods, NvU32 *pNumMethods); +NV_STATUS chandesGetSwMethods_IMPL(struct ChannelDescendant *pChannelDescendant, const METHOD **ppMethods, NvU32 *pNumMethods); -static inline NV_STATUS chandesGetSwMethods_DISPATCH(struct ChannelDescendant *pChannelDescendant, METHOD **ppMethods, NvU32 *pNumMethods) { +static inline NV_STATUS chandesGetSwMethods_DISPATCH(struct ChannelDescendant *pChannelDescendant, const METHOD **ppMethods, NvU32 *pNumMethods) { return pChannelDescendant->__chandesGetSwMethods__(pChannelDescendant, ppMethods, pNumMethods); } @@ -269,14 +273,14 @@ return pGpuResource->__chandesShareCallback__(pGpuResource, pInvokingClient, pParentRef, pSharePolicy); } -static inline NV_STATUS chandesMapTo_DISPATCH(struct ChannelDescendant *pResource, RS_RES_MAP_TO_PARAMS *pParams) { - return pResource->__chandesMapTo__(pResource, pParams); -} - static inline NV_STATUS chandesGetOrAllocNotifShare_DISPATCH(struct ChannelDescendant *pNotifier, NvHandle hNotifierClient, NvHandle hNotifierResource, struct NotifShare **ppNotifShare) { return pNotifier->__chandesGetOrAllocNotifShare__(pNotifier, hNotifierClient, hNotifierResource, ppNotifShare); } +static inline NV_STATUS chandesMapTo_DISPATCH(struct ChannelDescendant *pResource, RS_RES_MAP_TO_PARAMS *pParams) { + return pResource->__chandesMapTo__(pResource, pParams); +} + static inline NV_STATUS chandesGetMapAddrSpace_DISPATCH(struct ChannelDescendant *pGpuResource, struct CALL_CONTEXT *pCallContext, NvU32 mapFlags, NV_ADDRESS_SPACE *pAddrSpace) { return pGpuResource->__chandesGetMapAddrSpace__(pGpuResource, pCallContext, mapFlags, pAddrSpace); } @@ -345,6 +349,10 @@ return pNotifier->__chandesUnregisterEvent__(pNotifier, hNotifierClient, hNotifierResource, hEventClient, hEvent); } +static inline NV_STATUS chandesControlSerialization_Prologue_DISPATCH(struct ChannelDescendant *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return pResource->__chandesControlSerialization_Prologue__(pResource, pCallContext, pParams); +} + static inline NvBool chandesCanCopy_DISPATCH(struct ChannelDescendant *pResource) { return pResource->__chandesCanCopy__(pResource); } @@ -357,6 +365,10 @@ return pResource->__chandesIsDuplicate__(pResource, hMemory, pDuplicate); } +static inline void chandesControlSerialization_Epilogue_DISPATCH(struct ChannelDescendant *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + pResource->__chandesControlSerialization_Epilogue__(pResource, pCallContext, pParams); +} + static inline PEVENTNOTIFICATION *chandesGetNotificationListPtr_DISPATCH(struct ChannelDescendant *pNotifier) { return pNotifier->__chandesGetNotificationListPtr__(pNotifier); } @@ -388,7 +400,7 @@ // //--------------------------------------------------------------------------- -NV_STATUS mthdNoOperation(OBJGPU *, struct ChannelDescendant *, PMETHOD, NvU32, NvU32); +NV_STATUS mthdNoOperation(OBJGPU *, struct ChannelDescendant *, NvU32, NvU32); #endif // _CHANNEL_DESCENDANT_H_ diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/generated/g_chips2halspec_nvoc.c nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_chips2halspec_nvoc.c --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/generated/g_chips2halspec_nvoc.c 2023-10-25 20:26:52.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_chips2halspec_nvoc.c 2024-03-05 22:18:07.000000000 +0000 @@ -125,7 +125,7 @@ // DISPv0000 else if(ipver == 0x0) { - pDispIpHal->__nvoc_HalVarIdx = 15; + pDispIpHal->__nvoc_HalVarIdx = 17; } } diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/generated/g_chipset_nvoc.c nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_chipset_nvoc.c --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/generated/g_chipset_nvoc.c 2023-10-25 20:26:52.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_chipset_nvoc.c 2024-03-05 22:18:07.000000000 +0000 @@ -116,13 +116,16 @@ Object *pParentObj; OBJCL *pThis; - pThis = portMemAllocNonPaged(sizeof(OBJCL)); - if (pThis == NULL) return NV_ERR_NO_MEMORY; + status = __nvoc_handleObjCreateMemAlloc(createFlags, sizeof(OBJCL), (void**)&pThis, (void**)ppThis); + if (status != NV_OK) + return status; portMemSet(pThis, 0, sizeof(OBJCL)); __nvoc_initRtti(staticCast(pThis, Dynamic), &__nvoc_class_def_OBJCL); + pThis->__nvoc_base_Object.createFlags = createFlags; + if (pParent != NULL && !(createFlags & NVOC_OBJ_CREATE_FLAGS_PARENT_HALSPEC_ONLY)) { pParentObj = dynamicCast(pParent, Object); @@ -138,11 +141,17 @@ if (status != NV_OK) goto __nvoc_objCreate_OBJCL_cleanup; *ppThis = pThis; + return NV_OK; __nvoc_objCreate_OBJCL_cleanup: // do not call destructors here since the constructor already called them - portMemFree(pThis); + if (createFlags & NVOC_OBJ_CREATE_FLAGS_IN_PLACE_CONSTRUCT) + portMemSet(pThis, 0, sizeof(OBJCL)); + else + portMemFree(pThis); + + // coverity[leaked_storage:FALSE] return status; } diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/generated/g_chipset_nvoc.h nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_chipset_nvoc.h --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/generated/g_chipset_nvoc.h 2023-10-25 20:26:52.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_chipset_nvoc.h 2024-03-05 22:18:07.000000000 +0000 @@ -114,6 +114,7 @@ // PCI Express Link control ASPM capability Bits #define CL_PCIE_LINK_CAP_ASPM_L0S_BIT NVBIT(10) #define CL_PCIE_LINK_CAP_ASPM_L1_BIT NVBIT(11) +#define CL_PCIE_LINK_CAP_CLOCK_PM_BIT NVBIT(18) // PCI Express Slot Capabilities #define CL_PCIE_SLOT_CAP_HOTPLUG_SURPRISE NVBIT(5) @@ -266,6 +267,7 @@ NvBool PDB_PROP_CL_ASPM_L1_CHIPSET_DISABLED; NvBool PDB_PROP_CL_ASPM_L0S_CHIPSET_ENABLED_MOBILE_ONLY; NvBool PDB_PROP_CL_ASPM_L1_CHIPSET_ENABLED_MOBILE_ONLY; + NvBool PDB_PROP_CL_ASPM_UPSTREAM_PORT_L1_MASK_ENABLED; NvBool PDB_PROP_CL_PCIE_GEN1_GEN2_SWITCH_CHIPSET_DISABLED; NvBool PDB_PROP_CL_PCIE_GEN1_GEN2_SWITCH_CHIPSET_DISABLED_GEFORCE; NvBool PDB_PROP_CL_EXTENDED_TAG_FIELD_NOT_CAPABLE; @@ -347,10 +349,10 @@ #define PDB_PROP_CL_ASPM_L1_CHIPSET_DISABLED_BASE_NAME PDB_PROP_CL_ASPM_L1_CHIPSET_DISABLED #define PDB_PROP_CL_RELAXED_ORDERING_NOT_CAPABLE_BASE_CAST #define PDB_PROP_CL_RELAXED_ORDERING_NOT_CAPABLE_BASE_NAME PDB_PROP_CL_RELAXED_ORDERING_NOT_CAPABLE +#define PDB_PROP_CL_ASPM_UPSTREAM_PORT_L1_MASK_ENABLED_BASE_CAST +#define PDB_PROP_CL_ASPM_UPSTREAM_PORT_L1_MASK_ENABLED_BASE_NAME PDB_PROP_CL_ASPM_UPSTREAM_PORT_L1_MASK_ENABLED #define PDB_PROP_CL_PCIE_GEN2_AT_LESS_THAN_X16_DISABLED_BASE_CAST #define PDB_PROP_CL_PCIE_GEN2_AT_LESS_THAN_X16_DISABLED_BASE_NAME PDB_PROP_CL_PCIE_GEN2_AT_LESS_THAN_X16_DISABLED -#define PDB_PROP_CL_ALLOW_PCIE_GEN3_ON_PATSBURG_WITH_IVBE_CPU_BASE_CAST -#define PDB_PROP_CL_ALLOW_PCIE_GEN3_ON_PATSBURG_WITH_IVBE_CPU_BASE_NAME PDB_PROP_CL_ALLOW_PCIE_GEN3_ON_PATSBURG_WITH_IVBE_CPU #define PDB_PROP_CL_UNSUPPORTED_CHIPSET_BASE_CAST #define PDB_PROP_CL_UNSUPPORTED_CHIPSET_BASE_NAME PDB_PROP_CL_UNSUPPORTED_CHIPSET #define PDB_PROP_CL_ASLM_SUPPORTS_GEN2_LINK_UPGRADE_BASE_CAST @@ -361,6 +363,8 @@ #define PDB_PROP_CL_BUG_999673_P2P_ARBITRARY_SPLIT_WAR_BASE_NAME PDB_PROP_CL_BUG_999673_P2P_ARBITRARY_SPLIT_WAR #define PDB_PROP_CL_ASPM_L1_CHIPSET_ENABLED_MOBILE_ONLY_BASE_CAST #define PDB_PROP_CL_ASPM_L1_CHIPSET_ENABLED_MOBILE_ONLY_BASE_NAME PDB_PROP_CL_ASPM_L1_CHIPSET_ENABLED_MOBILE_ONLY +#define PDB_PROP_CL_ALLOW_PCIE_GEN3_ON_PATSBURG_WITH_IVBE_CPU_BASE_CAST +#define PDB_PROP_CL_ALLOW_PCIE_GEN3_ON_PATSBURG_WITH_IVBE_CPU_BASE_NAME PDB_PROP_CL_ALLOW_PCIE_GEN3_ON_PATSBURG_WITH_IVBE_CPU #define PDB_PROP_CL_PCIE_FORCE_GEN2_ENABLE_BASE_CAST #define PDB_PROP_CL_PCIE_FORCE_GEN2_ENABLE_BASE_NAME PDB_PROP_CL_PCIE_FORCE_GEN2_ENABLE #define PDB_PROP_CL_DISABLE_BR03_FLOW_CONTROL_BASE_CAST @@ -462,20 +466,6 @@ #define clInitPropertiesFromRegistry_HAL(arg0, pCl) clInitPropertiesFromRegistry(arg0, pCl) -NV_STATUS clGetFHBHandle_IMPL(struct OBJCL *arg0, void **arg1, NvU16 *arg2, NvU16 *arg3); - - -#ifdef __nvoc_chipset_h_disabled -static inline NV_STATUS clGetFHBHandle(struct OBJCL *arg0, void **arg1, NvU16 *arg2, NvU16 *arg3) { - NV_ASSERT_FAILED_PRECOMP("OBJCL was disabled!"); - return NV_ERR_NOT_SUPPORTED; -} -#else //__nvoc_chipset_h_disabled -#define clGetFHBHandle(arg0, arg1, arg2, arg3) clGetFHBHandle_IMPL(arg0, arg1, arg2, arg3) -#endif //__nvoc_chipset_h_disabled - -#define clGetFHBHandle_HAL(arg0, arg1, arg2, arg3) clGetFHBHandle(arg0, arg1, arg2, arg3) - NvU32 clInitMappingPciBusDevice_IMPL(struct OBJGPU *arg0, struct OBJCL *arg1); @@ -908,31 +898,31 @@ #define clInitDeviceInfo_HAL(arg0, arg1) clInitDeviceInfo(arg0, arg1) -void clCountBR_IMPL(struct OBJGPU *arg0, struct OBJCL *arg1, NvU8 *arg2, NvU8 *arg3, NvU8 *arg4); +void clCountBR_IMPL(struct OBJGPU *arg0, struct OBJCL *arg1, NvU8 *arg2); #ifdef __nvoc_chipset_h_disabled -static inline void clCountBR(struct OBJGPU *arg0, struct OBJCL *arg1, NvU8 *arg2, NvU8 *arg3, NvU8 *arg4) { +static inline void clCountBR(struct OBJGPU *arg0, struct OBJCL *arg1, NvU8 *arg2) { NV_ASSERT_FAILED_PRECOMP("OBJCL was disabled!"); } #else //__nvoc_chipset_h_disabled -#define clCountBR(arg0, arg1, arg2, arg3, arg4) clCountBR_IMPL(arg0, arg1, arg2, arg3, arg4) +#define clCountBR(arg0, arg1, arg2) clCountBR_IMPL(arg0, arg1, arg2) #endif //__nvoc_chipset_h_disabled -#define clCountBR_HAL(arg0, arg1, arg2, arg3, arg4) clCountBR(arg0, arg1, arg2, arg3, arg4) +#define clCountBR_HAL(arg0, arg1, arg2) clCountBR(arg0, arg1, arg2) -void clFindCommonBR_IMPL(struct OBJGPU *pGpu1, struct OBJGPU *pGpu2, struct OBJCL *pCl, NvU8 *pBR03Bus, NvU8 *pBR04Bus, NvU8 *pPLXBus, NvBool bScanAll); +void clFindCommonBR_IMPL(struct OBJGPU *pGpu1, struct OBJGPU *pGpu2, struct OBJCL *pCl, NvU8 *pBR04Bus, NvBool bScanAll); #ifdef __nvoc_chipset_h_disabled -static inline void clFindCommonBR(struct OBJGPU *pGpu1, struct OBJGPU *pGpu2, struct OBJCL *pCl, NvU8 *pBR03Bus, NvU8 *pBR04Bus, NvU8 *pPLXBus, NvBool bScanAll) { +static inline void clFindCommonBR(struct OBJGPU *pGpu1, struct OBJGPU *pGpu2, struct OBJCL *pCl, NvU8 *pBR04Bus, NvBool bScanAll) { NV_ASSERT_FAILED_PRECOMP("OBJCL was disabled!"); } #else //__nvoc_chipset_h_disabled -#define clFindCommonBR(pGpu1, pGpu2, pCl, pBR03Bus, pBR04Bus, pPLXBus, bScanAll) clFindCommonBR_IMPL(pGpu1, pGpu2, pCl, pBR03Bus, pBR04Bus, pPLXBus, bScanAll) +#define clFindCommonBR(pGpu1, pGpu2, pCl, pBR04Bus, bScanAll) clFindCommonBR_IMPL(pGpu1, pGpu2, pCl, pBR04Bus, bScanAll) #endif //__nvoc_chipset_h_disabled -#define clFindCommonBR_HAL(pGpu1, pGpu2, pCl, pBR03Bus, pBR04Bus, pPLXBus, bScanAll) clFindCommonBR(pGpu1, pGpu2, pCl, pBR03Bus, pBR04Bus, pPLXBus, bScanAll) +#define clFindCommonBR_HAL(pGpu1, pGpu2, pCl, pBR04Bus, bScanAll) clFindCommonBR(pGpu1, pGpu2, pCl, pBR04Bus, bScanAll) void clFindCommonDownstreamBR_IMPL(struct OBJGPU *pGpu1, struct OBJGPU *pGpu2, struct OBJCL *pCl, NvU8 *pPciSwitchBus); @@ -947,18 +937,18 @@ #define clFindCommonDownstreamBR_HAL(pGpu1, pGpu2, pCl, pPciSwitchBus) clFindCommonDownstreamBR(pGpu1, pGpu2, pCl, pPciSwitchBus) -void clFindBR_IMPL(struct OBJGPU *pGpu, struct OBJCL *pCl, NvU8 *pBR03Bus, NvU8 *pBR04Bus, NvBool *pBRNotBR04A03, NvBool *pNoUnsupportedBRFound, NvBool *pNoOnboardBR04, NvU8 *pPLXBus); +void clFindBR_IMPL(struct OBJGPU *pGpu, struct OBJCL *pCl, NvU8 *pBR03Bus, NvU8 *pBR04Bus, NvBool *pBRNotBR04A03, NvBool *pNoUnsupportedBRFound, NvBool *pNoOnboardBR04); #ifdef __nvoc_chipset_h_disabled -static inline void clFindBR(struct OBJGPU *pGpu, struct OBJCL *pCl, NvU8 *pBR03Bus, NvU8 *pBR04Bus, NvBool *pBRNotBR04A03, NvBool *pNoUnsupportedBRFound, NvBool *pNoOnboardBR04, NvU8 *pPLXBus) { +static inline void clFindBR(struct OBJGPU *pGpu, struct OBJCL *pCl, NvU8 *pBR03Bus, NvU8 *pBR04Bus, NvBool *pBRNotBR04A03, NvBool *pNoUnsupportedBRFound, NvBool *pNoOnboardBR04) { NV_ASSERT_FAILED_PRECOMP("OBJCL was disabled!"); } #else //__nvoc_chipset_h_disabled -#define clFindBR(pGpu, pCl, pBR03Bus, pBR04Bus, pBRNotBR04A03, pNoUnsupportedBRFound, pNoOnboardBR04, pPLXBus) clFindBR_IMPL(pGpu, pCl, pBR03Bus, pBR04Bus, pBRNotBR04A03, pNoUnsupportedBRFound, pNoOnboardBR04, pPLXBus) +#define clFindBR(pGpu, pCl, pBR03Bus, pBR04Bus, pBRNotBR04A03, pNoUnsupportedBRFound, pNoOnboardBR04) clFindBR_IMPL(pGpu, pCl, pBR03Bus, pBR04Bus, pBRNotBR04A03, pNoUnsupportedBRFound, pNoOnboardBR04) #endif //__nvoc_chipset_h_disabled -#define clFindBR_HAL(pGpu, pCl, pBR03Bus, pBR04Bus, pBRNotBR04A03, pNoUnsupportedBRFound, pNoOnboardBR04, pPLXBus) clFindBR(pGpu, pCl, pBR03Bus, pBR04Bus, pBRNotBR04A03, pNoUnsupportedBRFound, pNoOnboardBR04, pPLXBus) +#define clFindBR_HAL(pGpu, pCl, pBR03Bus, pBR04Bus, pBRNotBR04A03, pNoUnsupportedBRFound, pNoOnboardBR04) clFindBR(pGpu, pCl, pBR03Bus, pBR04Bus, pBRNotBR04A03, pNoUnsupportedBRFound, pNoOnboardBR04) void clSearchBR04_IMPL(struct OBJCL *pCl, NvU8 *pBR04BusArray, NvU8 *pBR04RevArray, NvU8 *pBR04Count); @@ -1028,33 +1018,33 @@ #define clFreeBusTopologyCache_HAL(pCl) clFreeBusTopologyCache(pCl) -NvBool clAreGpusBehindSameBridge_IMPL(struct OBJCL *pCl, struct OBJGPU *pGpu1, struct OBJGPU *pGpu2); +NvBool clIsL1MaskEnabledForUpstreamPort_IMPL(struct OBJGPU *arg0, struct OBJCL *arg1); #ifdef __nvoc_chipset_h_disabled -static inline NvBool clAreGpusBehindSameBridge(struct OBJCL *pCl, struct OBJGPU *pGpu1, struct OBJGPU *pGpu2) { +static inline NvBool clIsL1MaskEnabledForUpstreamPort(struct OBJGPU *arg0, struct OBJCL *arg1) { NV_ASSERT_FAILED_PRECOMP("OBJCL was disabled!"); return NV_FALSE; } #else //__nvoc_chipset_h_disabled -#define clAreGpusBehindSameBridge(pCl, pGpu1, pGpu2) clAreGpusBehindSameBridge_IMPL(pCl, pGpu1, pGpu2) +#define clIsL1MaskEnabledForUpstreamPort(arg0, arg1) clIsL1MaskEnabledForUpstreamPort_IMPL(arg0, arg1) #endif //__nvoc_chipset_h_disabled -#define clAreGpusBehindSameBridge_HAL(pCl, pGpu1, pGpu2) clAreGpusBehindSameBridge(pCl, pGpu1, pGpu2) +#define clIsL1MaskEnabledForUpstreamPort_HAL(arg0, arg1) clIsL1MaskEnabledForUpstreamPort(arg0, arg1) -NvBool clIsL1MaskEnabledForUpstreamPort_IMPL(struct OBJGPU *arg0, struct OBJCL *arg1); +NvBool clIsL0sMaskEnabledForUpstreamPort_IMPL(struct OBJGPU *arg0, struct OBJCL *arg1); #ifdef __nvoc_chipset_h_disabled -static inline NvBool clIsL1MaskEnabledForUpstreamPort(struct OBJGPU *arg0, struct OBJCL *arg1) { +static inline NvBool clIsL0sMaskEnabledForUpstreamPort(struct OBJGPU *arg0, struct OBJCL *arg1) { NV_ASSERT_FAILED_PRECOMP("OBJCL was disabled!"); return NV_FALSE; } #else //__nvoc_chipset_h_disabled -#define clIsL1MaskEnabledForUpstreamPort(arg0, arg1) clIsL1MaskEnabledForUpstreamPort_IMPL(arg0, arg1) +#define clIsL0sMaskEnabledForUpstreamPort(arg0, arg1) clIsL0sMaskEnabledForUpstreamPort_IMPL(arg0, arg1) #endif //__nvoc_chipset_h_disabled -#define clIsL1MaskEnabledForUpstreamPort_HAL(arg0, arg1) clIsL1MaskEnabledForUpstreamPort(arg0, arg1) +#define clIsL0sMaskEnabledForUpstreamPort_HAL(arg0, arg1) clIsL0sMaskEnabledForUpstreamPort(arg0, arg1) NV_STATUS clControlL0sL1LinkControlUpstreamPort_IMPL(struct OBJGPU *arg0, struct OBJCL *arg1, NvBool arg2); @@ -1112,6 +1102,20 @@ #define clPcieGetGpuLostDiagnosticData_HAL(pGpu, arg0, pBuffer, size) clPcieGetGpuLostDiagnosticData(pGpu, arg0, pBuffer, size) +NvU32 clGetChipsetL1ClockPMSupport_IMPL(struct OBJGPU *arg0, struct OBJCL *arg1); + + +#ifdef __nvoc_chipset_h_disabled +static inline NvU32 clGetChipsetL1ClockPMSupport(struct OBJGPU *arg0, struct OBJCL *arg1) { + NV_ASSERT_FAILED_PRECOMP("OBJCL was disabled!"); + return 0; +} +#else //__nvoc_chipset_h_disabled +#define clGetChipsetL1ClockPMSupport(arg0, arg1) clGetChipsetL1ClockPMSupport_IMPL(arg0, arg1) +#endif //__nvoc_chipset_h_disabled + +#define clGetChipsetL1ClockPMSupport_HAL(arg0, arg1) clGetChipsetL1ClockPMSupport(arg0, arg1) + NV_STATUS clConstruct_IMPL(struct OBJCL *arg_pCl); #define __nvoc_clConstruct(arg_pCl) clConstruct_IMPL(arg_pCl) diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/generated/g_client_nvoc.c nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_client_nvoc.c --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/generated/g_client_nvoc.c 2023-10-25 20:26:52.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_client_nvoc.c 2024-03-05 22:18:07.000000000 +0000 @@ -124,13 +124,16 @@ Object *pParentObj; UserInfo *pThis; - pThis = portMemAllocNonPaged(sizeof(UserInfo)); - if (pThis == NULL) return NV_ERR_NO_MEMORY; + status = __nvoc_handleObjCreateMemAlloc(createFlags, sizeof(UserInfo), (void**)&pThis, (void**)ppThis); + if (status != NV_OK) + return status; portMemSet(pThis, 0, sizeof(UserInfo)); __nvoc_initRtti(staticCast(pThis, Dynamic), &__nvoc_class_def_UserInfo); + pThis->__nvoc_base_RsShared.__nvoc_base_Object.createFlags = createFlags; + if (pParent != NULL && !(createFlags & NVOC_OBJ_CREATE_FLAGS_PARENT_HALSPEC_ONLY)) { pParentObj = dynamicCast(pParent, Object); @@ -146,11 +149,17 @@ if (status != NV_OK) goto __nvoc_objCreate_UserInfo_cleanup; *ppThis = pThis; + return NV_OK; __nvoc_objCreate_UserInfo_cleanup: // do not call destructors here since the constructor already called them - portMemFree(pThis); + if (createFlags & NVOC_OBJ_CREATE_FLAGS_IN_PLACE_CONSTRUCT) + portMemSet(pThis, 0, sizeof(UserInfo)); + else + portMemFree(pThis); + + // coverity[leaked_storage:FALSE] return status; } @@ -359,13 +368,16 @@ Object *pParentObj; RmClient *pThis; - pThis = portMemAllocNonPaged(sizeof(RmClient)); - if (pThis == NULL) return NV_ERR_NO_MEMORY; + status = __nvoc_handleObjCreateMemAlloc(createFlags, sizeof(RmClient), (void**)&pThis, (void**)ppThis); + if (status != NV_OK) + return status; portMemSet(pThis, 0, sizeof(RmClient)); __nvoc_initRtti(staticCast(pThis, Dynamic), &__nvoc_class_def_RmClient); + pThis->__nvoc_base_RsClient.__nvoc_base_Object.createFlags = createFlags; + if (pParent != NULL && !(createFlags & NVOC_OBJ_CREATE_FLAGS_PARENT_HALSPEC_ONLY)) { pParentObj = dynamicCast(pParent, Object); @@ -381,11 +393,17 @@ if (status != NV_OK) goto __nvoc_objCreate_RmClient_cleanup; *ppThis = pThis; + return NV_OK; __nvoc_objCreate_RmClient_cleanup: // do not call destructors here since the constructor already called them - portMemFree(pThis); + if (createFlags & NVOC_OBJ_CREATE_FLAGS_IN_PLACE_CONSTRUCT) + portMemSet(pThis, 0, sizeof(RmClient)); + else + portMemFree(pThis); + + // coverity[leaked_storage:FALSE] return status; } diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/generated/g_client_nvoc.h nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_client_nvoc.h --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/generated/g_client_nvoc.h 2023-10-25 20:26:52.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_client_nvoc.h 2024-03-05 22:18:07.000000000 +0000 @@ -140,6 +140,7 @@ NvU32 Flags; NvU32 ClientDebuggerState; void *pOSInfo; + void *pOsPidInfo; char name[100]; CLI_SYSTEM_EVENT_INFO CliSysEventInfo; PSECURITY_TOKEN pSecurityToken; diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/generated/g_client_resource_nvoc.c nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_client_resource_nvoc.c --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/generated/g_client_resource_nvoc.c 2023-10-25 20:26:52.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_client_resource_nvoc.c 2024-03-05 22:18:08.000000000 +0000 @@ -110,6 +110,14 @@ return cliresShareCallback((struct RmClientResource *)(((unsigned char *)pRmCliRes) - __nvoc_rtti_RmClientResource_RsResource.offset), pInvokingClient, pParentRef, pSharePolicy); } +static NV_STATUS __nvoc_thunk_RmClientResource_resControl_Prologue(struct RsResource *pRmCliRes, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return cliresControl_Prologue((struct RmClientResource *)(((unsigned char *)pRmCliRes) - __nvoc_rtti_RmClientResource_RsResource.offset), pCallContext, pParams); +} + +static void __nvoc_thunk_RmClientResource_resControl_Epilogue(struct RsResource *pRmCliRes, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + cliresControl_Epilogue((struct RmClientResource *)(((unsigned char *)pRmCliRes) - __nvoc_rtti_RmClientResource_RsResource.offset), pCallContext, pParams); +} + static NV_STATUS __nvoc_thunk_RsResource_cliresControl(struct RmClientResource *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { return resControl((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_RmClientResource_RsResource.offset), pCallContext, pParams); } @@ -142,12 +150,12 @@ return notifyUnregisterEvent((struct Notifier *)(((unsigned char *)pNotifier) + __nvoc_rtti_RmClientResource_Notifier.offset), hNotifierClient, hNotifierResource, hEventClient, hEvent); } -static NvBool __nvoc_thunk_RsResource_cliresCanCopy(struct RmClientResource *pResource) { - return resCanCopy((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_RmClientResource_RsResource.offset)); +static NV_STATUS __nvoc_thunk_RsResource_cliresControlSerialization_Prologue(struct RmClientResource *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return resControlSerialization_Prologue((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_RmClientResource_RsResource.offset), pCallContext, pParams); } -static NV_STATUS __nvoc_thunk_RsResource_cliresControl_Prologue(struct RmClientResource *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { - return resControl_Prologue((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_RmClientResource_RsResource.offset), pCallContext, pParams); +static NvBool __nvoc_thunk_RsResource_cliresCanCopy(struct RmClientResource *pResource) { + return resCanCopy((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_RmClientResource_RsResource.offset)); } static void __nvoc_thunk_RsResource_cliresPreDestruct(struct RmClientResource *pResource) { @@ -162,12 +170,12 @@ return resIsDuplicate((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_RmClientResource_RsResource.offset), hMemory, pDuplicate); } -static PEVENTNOTIFICATION *__nvoc_thunk_Notifier_cliresGetNotificationListPtr(struct RmClientResource *pNotifier) { - return notifyGetNotificationListPtr((struct Notifier *)(((unsigned char *)pNotifier) + __nvoc_rtti_RmClientResource_Notifier.offset)); +static void __nvoc_thunk_RsResource_cliresControlSerialization_Epilogue(struct RmClientResource *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + resControlSerialization_Epilogue((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_RmClientResource_RsResource.offset), pCallContext, pParams); } -static void __nvoc_thunk_RsResource_cliresControl_Epilogue(struct RmClientResource *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { - resControl_Epilogue((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_RmClientResource_RsResource.offset), pCallContext, pParams); +static PEVENTNOTIFICATION *__nvoc_thunk_Notifier_cliresGetNotificationListPtr(struct RmClientResource *pNotifier) { + return notifyGetNotificationListPtr((struct Notifier *)(((unsigned char *)pNotifier) + __nvoc_rtti_RmClientResource_Notifier.offset)); } static struct NotifShare *__nvoc_thunk_Notifier_cliresGetNotificationShare(struct RmClientResource *pNotifier) { @@ -301,6 +309,36 @@ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) /*pFunc=*/ (void (*)(void)) NULL, #else + /*pFunc=*/ (void (*)(void)) cliresCtrlCmdSystemGpsControl_IMPL, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) + /*flags=*/ 0x10u, + /*accessRight=*/0x0u, + /*methodId=*/ 0x122u, + /*paramSize=*/ sizeof(NV0000_CTRL_SYSTEM_GPS_CONTROL_PARAMS), + /*pClassInfo=*/ &(__nvoc_class_def_RmClientResource.classInfo), +#if NV_PRINTF_STRINGS_ALLOWED + /*func=*/ "cliresCtrlCmdSystemGpsControl" +#endif + }, + { /* [8] */ +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) + /*pFunc=*/ (void (*)(void)) NULL, +#else + /*pFunc=*/ (void (*)(void)) cliresCtrlCmdSystemGpsBatchControl_IMPL, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) + /*flags=*/ 0x10u, + /*accessRight=*/0x0u, + /*methodId=*/ 0x123u, + /*paramSize=*/ sizeof(NV0000_CTRL_SYSTEM_GPS_BATCH_CONTROL_PARAMS), + /*pClassInfo=*/ &(__nvoc_class_def_RmClientResource.classInfo), +#if NV_PRINTF_STRINGS_ALLOWED + /*func=*/ "cliresCtrlCmdSystemGpsBatchControl" +#endif + }, + { /* [9] */ +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) + /*pFunc=*/ (void (*)(void)) NULL, +#else /*pFunc=*/ (void (*)(void)) cliresCtrlCmdSystemGetHwbcInfo_IMPL, #endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) /*flags=*/ 0x10u, @@ -312,7 +350,7 @@ /*func=*/ "cliresCtrlCmdSystemGetHwbcInfo" #endif }, - { /* [8] */ + { /* [10] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x810u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -327,7 +365,22 @@ /*func=*/ "cliresCtrlCmdSystemGetP2pCaps" #endif }, - { /* [9] */ + { /* [11] */ +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) + /*pFunc=*/ (void (*)(void)) NULL, +#else + /*pFunc=*/ (void (*)(void)) cliresCtrlCmdSystemGpsCtrl_IMPL, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) + /*flags=*/ 0x10u, + /*accessRight=*/0x0u, + /*methodId=*/ 0x12au, + /*paramSize=*/ sizeof(NV0000_CTRL_SYSTEM_GPS_CTRL_PARAMS), + /*pClassInfo=*/ &(__nvoc_class_def_RmClientResource.classInfo), +#if NV_PRINTF_STRINGS_ALLOWED + /*func=*/ "cliresCtrlCmdSystemGpsCtrl" +#endif + }, + { /* [12] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x810u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -342,7 +395,7 @@ /*func=*/ "cliresCtrlCmdSystemGetP2pCapsV2" #endif }, - { /* [10] */ + { /* [13] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -357,7 +410,22 @@ /*func=*/ "cliresCtrlCmdSystemGetPerfSensorCounters" #endif }, - { /* [11] */ + { /* [14] */ +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) + /*pFunc=*/ (void (*)(void)) NULL, +#else + /*pFunc=*/ (void (*)(void)) cliresCtrlCmdSystemGpsCallAcpi_IMPL, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) + /*flags=*/ 0x10u, + /*accessRight=*/0x0u, + /*methodId=*/ 0x12du, + /*paramSize=*/ sizeof(NV0000_CTRL_SYSTEM_GPS_CALL_ACPI_PARAMS), + /*pClassInfo=*/ &(__nvoc_class_def_RmClientResource.classInfo), +#if NV_PRINTF_STRINGS_ALLOWED + /*func=*/ "cliresCtrlCmdSystemGpsCallAcpi" +#endif + }, + { /* [15] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -372,7 +440,22 @@ /*func=*/ "cliresCtrlCmdSystemGetExtendedPerfSensorCounters" #endif }, - { /* [12] */ + { /* [16] */ +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) + /*pFunc=*/ (void (*)(void)) NULL, +#else + /*pFunc=*/ (void (*)(void)) cliresCtrlCmdSystemGpsGetFrmData_IMPL, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) + /*flags=*/ 0x10u, + /*accessRight=*/0x0u, + /*methodId=*/ 0x12fu, + /*paramSize=*/ sizeof(NV0000_CTRL_SYSTEM_GPS_GET_FRM_DATA_PARAMS), + /*pClassInfo=*/ &(__nvoc_class_def_RmClientResource.classInfo), +#if NV_PRINTF_STRINGS_ALLOWED + /*func=*/ "cliresCtrlCmdSystemGpsGetFrmData" +#endif + }, + { /* [17] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -387,7 +470,22 @@ /*func=*/ "cliresCtrlCmdSystemExecuteAcpiMethod" #endif }, - { /* [13] */ + { /* [18] */ +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) + /*pFunc=*/ (void (*)(void)) NULL, +#else + /*pFunc=*/ (void (*)(void)) cliresCtrlCmdSystemGpsSetFrmData_IMPL, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) + /*flags=*/ 0x10u, + /*accessRight=*/0x0u, + /*methodId=*/ 0x132u, + /*paramSize=*/ sizeof(NV0000_CTRL_SYSTEM_GPS_SET_FRM_DATA_PARAMS), + /*pClassInfo=*/ &(__nvoc_class_def_RmClientResource.classInfo), +#if NV_PRINTF_STRINGS_ALLOWED + /*func=*/ "cliresCtrlCmdSystemGpsSetFrmData" +#endif + }, + { /* [19] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x11u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -402,13 +500,13 @@ /*func=*/ "cliresCtrlCmdSystemGetGpusPowerStatus" #endif }, - { /* [14] */ -#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) + { /* [20] */ +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x811u) /*pFunc=*/ (void (*)(void)) NULL, #else /*pFunc=*/ (void (*)(void)) cliresCtrlCmdSystemGetPrivilegedStatus_IMPL, -#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) - /*flags=*/ 0x10u, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x811u) + /*flags=*/ 0x811u, /*accessRight=*/0x0u, /*methodId=*/ 0x135u, /*paramSize=*/ sizeof(NV0000_CTRL_SYSTEM_GET_PRIVILEGED_STATUS_PARAMS), @@ -417,13 +515,13 @@ /*func=*/ "cliresCtrlCmdSystemGetPrivilegedStatus" #endif }, - { /* [15] */ -#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x810u) + { /* [21] */ +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x811u) /*pFunc=*/ (void (*)(void)) NULL, #else /*pFunc=*/ (void (*)(void)) cliresCtrlCmdSystemGetFabricStatus_IMPL, -#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x810u) - /*flags=*/ 0x810u, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x811u) + /*flags=*/ 0x811u, /*accessRight=*/0x0u, /*methodId=*/ 0x136u, /*paramSize=*/ sizeof(NV0000_CTRL_SYSTEM_GET_FABRIC_STATUS_PARAMS), @@ -432,7 +530,7 @@ /*func=*/ "cliresCtrlCmdSystemGetFabricStatus" #endif }, - { /* [16] */ + { /* [22] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -447,7 +545,7 @@ /*func=*/ "cliresCtrlCmdVgpuGetVgpuVersion" #endif }, - { /* [17] */ + { /* [23] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -462,13 +560,13 @@ /*func=*/ "cliresCtrlCmdVgpuSetVgpuVersion" #endif }, - { /* [18] */ -#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x13u) + { /* [24] */ +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x813u) /*pFunc=*/ (void (*)(void)) NULL, #else /*pFunc=*/ (void (*)(void)) cliresCtrlCmdSystemGetRmInstanceId_IMPL, -#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x13u) - /*flags=*/ 0x13u, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x813u) + /*flags=*/ 0x813u, /*accessRight=*/0x0u, /*methodId=*/ 0x139u, /*paramSize=*/ sizeof(NV0000_CTRL_SYSTEM_GET_RM_INSTANCE_ID_PARAMS), @@ -477,7 +575,7 @@ /*func=*/ "cliresCtrlCmdSystemGetRmInstanceId" #endif }, - { /* [19] */ + { /* [25] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x810u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -492,7 +590,7 @@ /*func=*/ "cliresCtrlCmdSystemGetP2pCapsMatrix" #endif }, - { /* [20] */ + { /* [26] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -507,7 +605,7 @@ /*func=*/ "cliresCtrlCmdSystemNVPCFGetPowerModeInfo" #endif }, - { /* [21] */ + { /* [27] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x4u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -522,13 +620,13 @@ /*func=*/ "cliresCtrlCmdSystemSyncExternalFabricMgmt" #endif }, - { /* [22] */ -#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x7u) + { /* [28] */ +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x807u) /*pFunc=*/ (void (*)(void)) NULL, #else /*pFunc=*/ (void (*)(void)) cliresCtrlCmdSystemGetClientDatabaseInfo_IMPL, -#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x7u) - /*flags=*/ 0x7u, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x807u) + /*flags=*/ 0x807u, /*accessRight=*/0x0u, /*methodId=*/ 0x13du, /*paramSize=*/ sizeof(NV0000_CTRL_SYSTEM_GET_CLIENT_DATABASE_INFO_PARAMS), @@ -537,13 +635,13 @@ /*func=*/ "cliresCtrlCmdSystemGetClientDatabaseInfo" #endif }, - { /* [23] */ -#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x811u) + { /* [29] */ +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x4811u) /*pFunc=*/ (void (*)(void)) NULL, #else /*pFunc=*/ (void (*)(void)) cliresCtrlCmdSystemGetBuildVersionV2_IMPL, -#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x811u) - /*flags=*/ 0x811u, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x4811u) + /*flags=*/ 0x4811u, /*accessRight=*/0x0u, /*methodId=*/ 0x13eu, /*paramSize=*/ sizeof(NV0000_CTRL_SYSTEM_GET_BUILD_VERSION_V2_PARAMS), @@ -552,13 +650,13 @@ /*func=*/ "cliresCtrlCmdSystemGetBuildVersionV2" #endif }, - { /* [24] */ -#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x807u) + { /* [30] */ +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x7u) /*pFunc=*/ (void (*)(void)) NULL, #else /*pFunc=*/ (void (*)(void)) cliresCtrlCmdSystemRmctrlCacheModeCtrl_IMPL, -#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x807u) - /*flags=*/ 0x807u, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x7u) + /*flags=*/ 0x7u, /*accessRight=*/0x0u, /*methodId=*/ 0x13fu, /*paramSize=*/ sizeof(NV0000_CTRL_SYSTEM_RMCTRL_CACHE_MODE_CTRL_PARAMS), @@ -567,7 +665,97 @@ /*func=*/ "cliresCtrlCmdSystemRmctrlCacheModeCtrl" #endif }, - { /* [25] */ + { /* [31] */ +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) + /*pFunc=*/ (void (*)(void)) NULL, +#else + /*pFunc=*/ (void (*)(void)) cliresCtrlCmdSystemPfmreqhndlrControl_IMPL, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) + /*flags=*/ 0x10u, + /*accessRight=*/0x0u, + /*methodId=*/ 0x140u, + /*paramSize=*/ sizeof(NV0000_CTRL_SYSTEM_PFM_REQ_HNDLR_CONTROL_PARAMS), + /*pClassInfo=*/ &(__nvoc_class_def_RmClientResource.classInfo), +#if NV_PRINTF_STRINGS_ALLOWED + /*func=*/ "cliresCtrlCmdSystemPfmreqhndlrControl" +#endif + }, + { /* [32] */ +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) + /*pFunc=*/ (void (*)(void)) NULL, +#else + /*pFunc=*/ (void (*)(void)) cliresCtrlCmdSystemPfmreqhndlrBatchControl_IMPL, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) + /*flags=*/ 0x10u, + /*accessRight=*/0x0u, + /*methodId=*/ 0x141u, + /*paramSize=*/ sizeof(NV0000_CTRL_SYSTEM_PFM_REQ_HNDLR_BATCH_CONTROL_PARAMS), + /*pClassInfo=*/ &(__nvoc_class_def_RmClientResource.classInfo), +#if NV_PRINTF_STRINGS_ALLOWED + /*func=*/ "cliresCtrlCmdSystemPfmreqhndlrBatchControl" +#endif + }, + { /* [33] */ +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) + /*pFunc=*/ (void (*)(void)) NULL, +#else + /*pFunc=*/ (void (*)(void)) cliresCtrlCmdSystemPfmreqhndlrCtrl_IMPL, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) + /*flags=*/ 0x10u, + /*accessRight=*/0x0u, + /*methodId=*/ 0x142u, + /*paramSize=*/ sizeof(NV0000_CTRL_SYSTEM_PFM_REQ_HNDLR_CTRL_PARAMS), + /*pClassInfo=*/ &(__nvoc_class_def_RmClientResource.classInfo), +#if NV_PRINTF_STRINGS_ALLOWED + /*func=*/ "cliresCtrlCmdSystemPfmreqhndlrCtrl" +#endif + }, + { /* [34] */ +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) + /*pFunc=*/ (void (*)(void)) NULL, +#else + /*pFunc=*/ (void (*)(void)) cliresCtrlCmdSystemPfmreqhndlrCallAcpi_IMPL, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) + /*flags=*/ 0x10u, + /*accessRight=*/0x0u, + /*methodId=*/ 0x143u, + /*paramSize=*/ sizeof(NV0000_CTRL_SYSTEM_PFM_REQ_HNDLR_CALL_ACPI_PARAMS), + /*pClassInfo=*/ &(__nvoc_class_def_RmClientResource.classInfo), +#if NV_PRINTF_STRINGS_ALLOWED + /*func=*/ "cliresCtrlCmdSystemPfmreqhndlrCallAcpi" +#endif + }, + { /* [35] */ +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) + /*pFunc=*/ (void (*)(void)) NULL, +#else + /*pFunc=*/ (void (*)(void)) cliresCtrlCmdSystemPfmreqhndlrGetFrmData_IMPL, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) + /*flags=*/ 0x10u, + /*accessRight=*/0x0u, + /*methodId=*/ 0x144u, + /*paramSize=*/ sizeof(NV0000_CTRL_SYSTEM_PFM_REQ_HNDLR_GET_FRM_DATA_PARAMS), + /*pClassInfo=*/ &(__nvoc_class_def_RmClientResource.classInfo), +#if NV_PRINTF_STRINGS_ALLOWED + /*func=*/ "cliresCtrlCmdSystemPfmreqhndlrGetFrmData" +#endif + }, + { /* [36] */ +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) + /*pFunc=*/ (void (*)(void)) NULL, +#else + /*pFunc=*/ (void (*)(void)) cliresCtrlCmdSystemPfmreqhndlrSetFrmData_IMPL, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) + /*flags=*/ 0x10u, + /*accessRight=*/0x0u, + /*methodId=*/ 0x145u, + /*paramSize=*/ sizeof(NV0000_CTRL_SYSTEM_PFM_REQ_HNDLR_SET_FRM_DATA_PARAMS), + /*pClassInfo=*/ &(__nvoc_class_def_RmClientResource.classInfo), +#if NV_PRINTF_STRINGS_ALLOWED + /*func=*/ "cliresCtrlCmdSystemPfmreqhndlrSetFrmData" +#endif + }, + { /* [37] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -582,7 +770,7 @@ /*func=*/ "cliresCtrlCmdSystemPfmreqhndlrGetPerfSensorCounters" #endif }, - { /* [26] */ + { /* [38] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -597,7 +785,7 @@ /*func=*/ "cliresCtrlCmdSystemPfmreqhndlrGetExtendedPerfSensorCounters" #endif }, - { /* [27] */ + { /* [39] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -612,7 +800,7 @@ /*func=*/ "cliresCtrlCmdSystemGetFeatures" #endif }, - { /* [28] */ + { /* [40] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x813u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -627,13 +815,13 @@ /*func=*/ "cliresCtrlCmdGpuGetAttachedIds" #endif }, - { /* [29] */ -#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x810u) + { /* [41] */ +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x811u) /*pFunc=*/ (void (*)(void)) NULL, #else /*pFunc=*/ (void (*)(void)) cliresCtrlCmdGpuGetIdInfo_IMPL, -#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x810u) - /*flags=*/ 0x810u, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x811u) + /*flags=*/ 0x811u, /*accessRight=*/0x0u, /*methodId=*/ 0x202u, /*paramSize=*/ sizeof(NV0000_CTRL_GPU_GET_ID_INFO_PARAMS), @@ -642,13 +830,13 @@ /*func=*/ "cliresCtrlCmdGpuGetIdInfo" #endif }, - { /* [30] */ -#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x11u) + { /* [42] */ +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x811u) /*pFunc=*/ (void (*)(void)) NULL, #else /*pFunc=*/ (void (*)(void)) cliresCtrlCmdGpuGetInitStatus_IMPL, -#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x11u) - /*flags=*/ 0x11u, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x811u) + /*flags=*/ 0x811u, /*accessRight=*/0x0u, /*methodId=*/ 0x203u, /*paramSize=*/ sizeof(NV0000_CTRL_GPU_GET_INIT_STATUS_PARAMS), @@ -657,13 +845,13 @@ /*func=*/ "cliresCtrlCmdGpuGetInitStatus" #endif }, - { /* [31] */ -#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x13u) + { /* [43] */ +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x813u) /*pFunc=*/ (void (*)(void)) NULL, #else /*pFunc=*/ (void (*)(void)) cliresCtrlCmdGpuGetDeviceIds_IMPL, -#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x13u) - /*flags=*/ 0x13u, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x813u) + /*flags=*/ 0x813u, /*accessRight=*/0x0u, /*methodId=*/ 0x204u, /*paramSize=*/ sizeof(NV0000_CTRL_GPU_GET_DEVICE_IDS_PARAMS), @@ -672,13 +860,13 @@ /*func=*/ "cliresCtrlCmdGpuGetDeviceIds" #endif }, - { /* [32] */ -#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x810u) + { /* [44] */ +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x811u) /*pFunc=*/ (void (*)(void)) NULL, #else /*pFunc=*/ (void (*)(void)) cliresCtrlCmdGpuGetIdInfoV2_IMPL, -#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x810u) - /*flags=*/ 0x810u, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x811u) + /*flags=*/ 0x811u, /*accessRight=*/0x0u, /*methodId=*/ 0x205u, /*paramSize=*/ sizeof(NV0000_CTRL_GPU_GET_ID_INFO_V2_PARAMS), @@ -687,7 +875,7 @@ /*func=*/ "cliresCtrlCmdGpuGetIdInfoV2" #endif }, - { /* [33] */ + { /* [45] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x811u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -702,13 +890,13 @@ /*func=*/ "cliresCtrlCmdGpuGetProbedIds" #endif }, - { /* [34] */ -#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x11u) + { /* [46] */ +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x811u) /*pFunc=*/ (void (*)(void)) NULL, #else /*pFunc=*/ (void (*)(void)) cliresCtrlCmdGpuAttachIds_IMPL, -#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x11u) - /*flags=*/ 0x11u, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x811u) + /*flags=*/ 0x811u, /*accessRight=*/0x0u, /*methodId=*/ 0x215u, /*paramSize=*/ sizeof(NV0000_CTRL_GPU_ATTACH_IDS_PARAMS), @@ -717,13 +905,13 @@ /*func=*/ "cliresCtrlCmdGpuAttachIds" #endif }, - { /* [35] */ -#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x11u) + { /* [47] */ +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x811u) /*pFunc=*/ (void (*)(void)) NULL, #else /*pFunc=*/ (void (*)(void)) cliresCtrlCmdGpuDetachIds_IMPL, -#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x11u) - /*flags=*/ 0x11u, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x811u) + /*flags=*/ 0x811u, /*accessRight=*/0x0u, /*methodId=*/ 0x216u, /*paramSize=*/ sizeof(NV0000_CTRL_GPU_DETACH_IDS_PARAMS), @@ -732,13 +920,28 @@ /*func=*/ "cliresCtrlCmdGpuDetachIds" #endif }, - { /* [36] */ -#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x810u) + { /* [48] */ +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x11u) + /*pFunc=*/ (void (*)(void)) NULL, +#else + /*pFunc=*/ (void (*)(void)) cliresCtrlCmdGpuGetVideoLinks_IMPL, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x11u) + /*flags=*/ 0x11u, + /*accessRight=*/0x0u, + /*methodId=*/ 0x219u, + /*paramSize=*/ sizeof(NV0000_CTRL_GPU_GET_VIDEO_LINKS_PARAMS), + /*pClassInfo=*/ &(__nvoc_class_def_RmClientResource.classInfo), +#if NV_PRINTF_STRINGS_ALLOWED + /*func=*/ "cliresCtrlCmdGpuGetVideoLinks" +#endif + }, + { /* [49] */ +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x811u) /*pFunc=*/ (void (*)(void)) NULL, #else /*pFunc=*/ (void (*)(void)) cliresCtrlCmdGpuGetPciInfo_IMPL, -#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x810u) - /*flags=*/ 0x810u, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x811u) + /*flags=*/ 0x811u, /*accessRight=*/0x0u, /*methodId=*/ 0x21bu, /*paramSize=*/ sizeof(NV0000_CTRL_GPU_GET_PCI_INFO_PARAMS), @@ -747,13 +950,13 @@ /*func=*/ "cliresCtrlCmdGpuGetPciInfo" #endif }, - { /* [37] */ -#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) + { /* [50] */ +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x811u) /*pFunc=*/ (void (*)(void)) NULL, #else /*pFunc=*/ (void (*)(void)) cliresCtrlCmdGpuGetSvmSize_IMPL, -#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) - /*flags=*/ 0x10u, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x811u) + /*flags=*/ 0x811u, /*accessRight=*/0x0u, /*methodId=*/ 0x240u, /*paramSize=*/ sizeof(NV0000_CTRL_GPU_GET_SVM_SIZE_PARAMS), @@ -762,7 +965,7 @@ /*func=*/ "cliresCtrlCmdGpuGetSvmSize" #endif }, - { /* [38] */ + { /* [51] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -777,13 +980,13 @@ /*func=*/ "cliresCtrlCmdGpuGetUuidInfo" #endif }, - { /* [39] */ -#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) + { /* [52] */ +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x811u) /*pFunc=*/ (void (*)(void)) NULL, #else /*pFunc=*/ (void (*)(void)) cliresCtrlCmdGpuGetUuidFromGpuId_IMPL, -#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) - /*flags=*/ 0x10u, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x811u) + /*flags=*/ 0x811u, /*accessRight=*/0x0u, /*methodId=*/ 0x275u, /*paramSize=*/ sizeof(NV0000_CTRL_GPU_GET_UUID_FROM_GPU_ID_PARAMS), @@ -792,7 +995,7 @@ /*func=*/ "cliresCtrlCmdGpuGetUuidFromGpuId" #endif }, - { /* [40] */ + { /* [53] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x4u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -807,13 +1010,13 @@ /*func=*/ "cliresCtrlCmdGpuModifyGpuDrainState" #endif }, - { /* [41] */ -#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x11u) + { /* [54] */ +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x811u) /*pFunc=*/ (void (*)(void)) NULL, #else /*pFunc=*/ (void (*)(void)) cliresCtrlCmdGpuQueryGpuDrainState_IMPL, -#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x11u) - /*flags=*/ 0x11u, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x811u) + /*flags=*/ 0x811u, /*accessRight=*/0x0u, /*methodId=*/ 0x279u, /*paramSize=*/ sizeof(NV0000_CTRL_GPU_QUERY_DRAIN_STATE_PARAMS), @@ -822,13 +1025,13 @@ /*func=*/ "cliresCtrlCmdGpuQueryGpuDrainState" #endif }, - { /* [42] */ -#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x811u) + { /* [55] */ +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x4811u) /*pFunc=*/ (void (*)(void)) NULL, #else /*pFunc=*/ (void (*)(void)) cliresCtrlCmdGpuGetMemOpEnable_IMPL, -#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x811u) - /*flags=*/ 0x811u, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x4811u) + /*flags=*/ 0x4811u, /*accessRight=*/0x0u, /*methodId=*/ 0x27bu, /*paramSize=*/ sizeof(NV0000_CTRL_GPU_GET_MEMOP_ENABLE_PARAMS), @@ -837,7 +1040,7 @@ /*func=*/ "cliresCtrlCmdGpuGetMemOpEnable" #endif }, - { /* [43] */ + { /* [56] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x13u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -852,7 +1055,7 @@ /*func=*/ "cliresCtrlCmdGpuDisableNvlinkInit" #endif }, - { /* [44] */ + { /* [57] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -867,7 +1070,7 @@ /*func=*/ "cliresCtrlCmdLegacyConfig" #endif }, - { /* [45] */ + { /* [58] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x11u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -882,7 +1085,7 @@ /*func=*/ "cliresCtrlCmdIdleChannels" #endif }, - { /* [46] */ + { /* [59] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -897,7 +1100,37 @@ /*func=*/ "cliresCtrlCmdPushGspUcode" #endif }, - { /* [47] */ + { /* [60] */ +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x4u) + /*pFunc=*/ (void (*)(void)) NULL, +#else + /*pFunc=*/ (void (*)(void)) cliresCtrlCmdGpuSetNvlinkBwMode_IMPL, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x4u) + /*flags=*/ 0x4u, + /*accessRight=*/0x0u, + /*methodId=*/ 0x286u, + /*paramSize=*/ sizeof(NV0000_CTRL_GPU_SET_NVLINK_BW_MODE_PARAMS), + /*pClassInfo=*/ &(__nvoc_class_def_RmClientResource.classInfo), +#if NV_PRINTF_STRINGS_ALLOWED + /*func=*/ "cliresCtrlCmdGpuSetNvlinkBwMode" +#endif + }, + { /* [61] */ +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x813u) + /*pFunc=*/ (void (*)(void)) NULL, +#else + /*pFunc=*/ (void (*)(void)) cliresCtrlCmdGpuGetNvlinkBwMode_IMPL, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x813u) + /*flags=*/ 0x813u, + /*accessRight=*/0x0u, + /*methodId=*/ 0x287u, + /*paramSize=*/ sizeof(NV0000_CTRL_GPU_GET_NVLINK_BW_MODE_PARAMS), + /*pClassInfo=*/ &(__nvoc_class_def_RmClientResource.classInfo), +#if NV_PRINTF_STRINGS_ALLOWED + /*func=*/ "cliresCtrlCmdGpuGetNvlinkBwMode" +#endif + }, + { /* [62] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -912,7 +1145,7 @@ /*func=*/ "cliresCtrlCmdGsyncGetAttachedIds" #endif }, - { /* [48] */ + { /* [63] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -927,7 +1160,7 @@ /*func=*/ "cliresCtrlCmdGsyncGetIdInfo" #endif }, - { /* [49] */ + { /* [64] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -942,7 +1175,7 @@ /*func=*/ "cliresCtrlCmdEventSetNotification" #endif }, - { /* [50] */ + { /* [65] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -957,7 +1190,7 @@ /*func=*/ "cliresCtrlCmdEventGetSystemEventStatus" #endif }, - { /* [51] */ + { /* [66] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -972,13 +1205,13 @@ /*func=*/ "cliresCtrlCmdNvdGetDumpSize" #endif }, - { /* [52] */ -#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) + { /* [67] */ +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x4u) /*pFunc=*/ (void (*)(void)) NULL, #else /*pFunc=*/ (void (*)(void)) cliresCtrlCmdNvdGetDump_IMPL, -#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) - /*flags=*/ 0x10u, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x4u) + /*flags=*/ 0x4u, /*accessRight=*/0x0u, /*methodId=*/ 0x602u, /*paramSize=*/ sizeof(NV0000_CTRL_NVD_GET_DUMP_PARAMS), @@ -987,7 +1220,7 @@ /*func=*/ "cliresCtrlCmdNvdGetDump" #endif }, - { /* [53] */ + { /* [68] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x813u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -1002,7 +1235,7 @@ /*func=*/ "cliresCtrlCmdNvdGetTimestamp" #endif }, - { /* [54] */ + { /* [69] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x7u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -1017,7 +1250,7 @@ /*func=*/ "cliresCtrlCmdNvdGetNvlogInfo" #endif }, - { /* [55] */ + { /* [70] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x7u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -1032,7 +1265,7 @@ /*func=*/ "cliresCtrlCmdNvdGetNvlogBufferInfo" #endif }, - { /* [56] */ + { /* [71] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x7u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -1047,7 +1280,7 @@ /*func=*/ "cliresCtrlCmdNvdGetNvlog" #endif }, - { /* [57] */ + { /* [72] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -1062,13 +1295,13 @@ /*func=*/ "cliresCtrlCmdNvdGetRcerrRpt" #endif }, - { /* [58] */ -#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) + { /* [73] */ +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x811u) /*pFunc=*/ (void (*)(void)) NULL, #else /*pFunc=*/ (void (*)(void)) cliresCtrlCmdSetSubProcessID_IMPL, -#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) - /*flags=*/ 0x10u, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x811u) + /*flags=*/ 0x811u, /*accessRight=*/0x0u, /*methodId=*/ 0x901u, /*paramSize=*/ sizeof(NV0000_CTRL_SET_SUB_PROCESS_ID_PARAMS), @@ -1077,13 +1310,13 @@ /*func=*/ "cliresCtrlCmdSetSubProcessID" #endif }, - { /* [59] */ -#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) + { /* [74] */ +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x811u) /*pFunc=*/ (void (*)(void)) NULL, #else /*pFunc=*/ (void (*)(void)) cliresCtrlCmdDisableSubProcessUserdIsolation_IMPL, -#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) - /*flags=*/ 0x10u, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x811u) + /*flags=*/ 0x811u, /*accessRight=*/0x0u, /*methodId=*/ 0x902u, /*paramSize=*/ sizeof(NV0000_CTRL_DISABLE_SUB_PROCESS_USERD_ISOLATION_PARAMS), @@ -1092,7 +1325,7 @@ /*func=*/ "cliresCtrlCmdDisableSubProcessUserdIsolation" #endif }, - { /* [60] */ + { /* [75] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x811u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -1107,7 +1340,7 @@ /*func=*/ "cliresCtrlCmdSyncGpuBoostInfo" #endif }, - { /* [61] */ + { /* [76] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x5u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -1122,7 +1355,7 @@ /*func=*/ "cliresCtrlCmdSyncGpuBoostGroupCreate" #endif }, - { /* [62] */ + { /* [77] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x5u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -1137,7 +1370,7 @@ /*func=*/ "cliresCtrlCmdSyncGpuBoostGroupDestroy" #endif }, - { /* [63] */ + { /* [78] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x811u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -1152,7 +1385,7 @@ /*func=*/ "cliresCtrlCmdSyncGpuBoostGroupInfo" #endif }, - { /* [64] */ + { /* [79] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x140004u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -1167,7 +1400,7 @@ /*func=*/ "cliresCtrlCmdGpuAcctSetAccountingState" #endif }, - { /* [65] */ + { /* [80] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -1182,7 +1415,7 @@ /*func=*/ "cliresCtrlCmdGpuAcctGetAccountingState" #endif }, - { /* [66] */ + { /* [81] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -1197,7 +1430,7 @@ /*func=*/ "cliresCtrlCmdGpuAcctGetProcAccountingInfo" #endif }, - { /* [67] */ + { /* [82] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -1212,7 +1445,7 @@ /*func=*/ "cliresCtrlCmdGpuAcctGetAccountingPids" #endif }, - { /* [68] */ + { /* [83] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x140004u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -1227,7 +1460,7 @@ /*func=*/ "cliresCtrlCmdGpuAcctClearAccountingData" #endif }, - { /* [69] */ + { /* [84] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -1242,13 +1475,13 @@ /*func=*/ "cliresCtrlCmdVgpuGetStartData" #endif }, - { /* [70] */ -#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x810u) + { /* [85] */ +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x811u) /*pFunc=*/ (void (*)(void)) NULL, #else /*pFunc=*/ (void (*)(void)) cliresCtrlCmdClientGetAddrSpaceType_IMPL, -#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x810u) - /*flags=*/ 0x810u, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x811u) + /*flags=*/ 0x811u, /*accessRight=*/0x0u, /*methodId=*/ 0xd01u, /*paramSize=*/ sizeof(NV0000_CTRL_CLIENT_GET_ADDR_SPACE_TYPE_PARAMS), @@ -1257,13 +1490,13 @@ /*func=*/ "cliresCtrlCmdClientGetAddrSpaceType" #endif }, - { /* [71] */ -#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x11u) + { /* [86] */ +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x811u) /*pFunc=*/ (void (*)(void)) NULL, #else /*pFunc=*/ (void (*)(void)) cliresCtrlCmdClientGetHandleInfo_IMPL, -#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x11u) - /*flags=*/ 0x11u, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x811u) + /*flags=*/ 0x811u, /*accessRight=*/0x0u, /*methodId=*/ 0xd02u, /*paramSize=*/ sizeof(NV0000_CTRL_CLIENT_GET_HANDLE_INFO_PARAMS), @@ -1272,7 +1505,7 @@ /*func=*/ "cliresCtrlCmdClientGetHandleInfo" #endif }, - { /* [72] */ + { /* [87] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x11u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -1287,7 +1520,7 @@ /*func=*/ "cliresCtrlCmdClientGetAccessRights" #endif }, - { /* [73] */ + { /* [88] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x11u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -1302,7 +1535,7 @@ /*func=*/ "cliresCtrlCmdClientSetInheritedSharePolicy" #endif }, - { /* [74] */ + { /* [89] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x11u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -1317,7 +1550,7 @@ /*func=*/ "cliresCtrlCmdClientGetChildHandle" #endif }, - { /* [75] */ + { /* [90] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x11u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -1332,7 +1565,7 @@ /*func=*/ "cliresCtrlCmdClientShareObject" #endif }, - { /* [76] */ + { /* [91] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x811u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -1347,7 +1580,7 @@ /*func=*/ "cliresCtrlCmdObjectsAreDuplicates" #endif }, - { /* [77] */ + { /* [92] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -1362,7 +1595,7 @@ /*func=*/ "cliresCtrlCmdOsUnixFlushUserCache" #endif }, - { /* [78] */ + { /* [93] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x11u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -1377,7 +1610,7 @@ /*func=*/ "cliresCtrlCmdOsUnixExportObjectToFd" #endif }, - { /* [79] */ + { /* [94] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x11u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -1392,13 +1625,13 @@ /*func=*/ "cliresCtrlCmdOsUnixImportObjectFromFd" #endif }, - { /* [80] */ -#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x11u) + { /* [95] */ +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x813u) /*pFunc=*/ (void (*)(void)) NULL, #else /*pFunc=*/ (void (*)(void)) cliresCtrlCmdOsUnixGetExportObjectInfo_IMPL, -#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x11u) - /*flags=*/ 0x11u, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x813u) + /*flags=*/ 0x813u, /*accessRight=*/0x0u, /*methodId=*/ 0x3d08u, /*paramSize=*/ sizeof(NV0000_CTRL_OS_UNIX_GET_EXPORT_OBJECT_INFO_PARAMS), @@ -1407,7 +1640,7 @@ /*func=*/ "cliresCtrlCmdOsUnixGetExportObjectInfo" #endif }, - { /* [81] */ + { /* [96] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x11u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -1422,7 +1655,7 @@ /*func=*/ "cliresCtrlCmdOsUnixCreateExportObjectFd" #endif }, - { /* [82] */ + { /* [97] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x11u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -1437,7 +1670,7 @@ /*func=*/ "cliresCtrlCmdOsUnixExportObjectsToFd" #endif }, - { /* [83] */ + { /* [98] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x11u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -1457,7 +1690,7 @@ const struct NVOC_EXPORT_INFO __nvoc_export_info_RmClientResource = { - /*numEntries=*/ 84, + /*numEntries=*/ 99, /*pExportEntries=*/ __nvoc_exported_method_def_RmClientResource }; @@ -1512,6 +1745,10 @@ pThis->__cliresShareCallback__ = &cliresShareCallback_IMPL; + pThis->__cliresControl_Prologue__ = &cliresControl_Prologue_IMPL; + + pThis->__cliresControl_Epilogue__ = &cliresControl_Epilogue_IMPL; + #if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x13u) pThis->__cliresCtrlCmdSystemGetCpuInfo__ = &cliresCtrlCmdSystemGetCpuInfo_IMPL; #endif @@ -1520,7 +1757,7 @@ pThis->__cliresCtrlCmdSystemGetFeatures__ = &cliresCtrlCmdSystemGetFeatures_IMPL; #endif -#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x811u) +#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x4811u) pThis->__cliresCtrlCmdSystemGetBuildVersionV2__ = &cliresCtrlCmdSystemGetBuildVersionV2_IMPL; #endif @@ -1553,6 +1790,14 @@ #endif #if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) + pThis->__cliresCtrlCmdSystemGpsControl__ = &cliresCtrlCmdSystemGpsControl_IMPL; +#endif + +#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) + pThis->__cliresCtrlCmdSystemGpsBatchControl__ = &cliresCtrlCmdSystemGpsBatchControl_IMPL; +#endif + +#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) pThis->__cliresCtrlCmdSystemGetHwbcInfo__ = &cliresCtrlCmdSystemGetHwbcInfo_IMPL; #endif @@ -1569,6 +1814,22 @@ #endif #if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) + pThis->__cliresCtrlCmdSystemGpsCtrl__ = &cliresCtrlCmdSystemGpsCtrl_IMPL; +#endif + +#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) + pThis->__cliresCtrlCmdSystemGpsGetFrmData__ = &cliresCtrlCmdSystemGpsGetFrmData_IMPL; +#endif + +#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) + pThis->__cliresCtrlCmdSystemGpsSetFrmData__ = &cliresCtrlCmdSystemGpsSetFrmData_IMPL; +#endif + +#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) + pThis->__cliresCtrlCmdSystemGpsCallAcpi__ = &cliresCtrlCmdSystemGpsCallAcpi_IMPL; +#endif + +#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) pThis->__cliresCtrlCmdSystemGetPerfSensorCounters__ = &cliresCtrlCmdSystemGetPerfSensorCounters_IMPL; #endif @@ -1580,23 +1841,23 @@ pThis->__cliresCtrlCmdSystemGetGpusPowerStatus__ = &cliresCtrlCmdSystemGetGpusPowerStatus_IMPL; #endif -#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) +#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x811u) pThis->__cliresCtrlCmdSystemGetPrivilegedStatus__ = &cliresCtrlCmdSystemGetPrivilegedStatus_IMPL; #endif -#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x810u) +#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x811u) pThis->__cliresCtrlCmdSystemGetFabricStatus__ = &cliresCtrlCmdSystemGetFabricStatus_IMPL; #endif -#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x13u) +#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x813u) pThis->__cliresCtrlCmdSystemGetRmInstanceId__ = &cliresCtrlCmdSystemGetRmInstanceId_IMPL; #endif -#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x7u) +#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x807u) pThis->__cliresCtrlCmdSystemGetClientDatabaseInfo__ = &cliresCtrlCmdSystemGetClientDatabaseInfo_IMPL; #endif -#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x807u) +#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x7u) pThis->__cliresCtrlCmdSystemRmctrlCacheModeCtrl__ = &cliresCtrlCmdSystemRmctrlCacheModeCtrl_IMPL; #endif @@ -1604,7 +1865,7 @@ pThis->__cliresCtrlCmdNvdGetDumpSize__ = &cliresCtrlCmdNvdGetDumpSize_IMPL; #endif -#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) +#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x4u) pThis->__cliresCtrlCmdNvdGetDump__ = &cliresCtrlCmdNvdGetDump_IMPL; #endif @@ -1628,11 +1889,11 @@ pThis->__cliresCtrlCmdNvdGetRcerrRpt__ = &cliresCtrlCmdNvdGetRcerrRpt_IMPL; #endif -#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x810u) +#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x811u) pThis->__cliresCtrlCmdClientGetAddrSpaceType__ = &cliresCtrlCmdClientGetAddrSpaceType_IMPL; #endif -#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x11u) +#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x811u) pThis->__cliresCtrlCmdClientGetHandleInfo__ = &cliresCtrlCmdClientGetHandleInfo_IMPL; #endif @@ -1660,19 +1921,19 @@ pThis->__cliresCtrlCmdGpuGetAttachedIds__ = &cliresCtrlCmdGpuGetAttachedIds_IMPL; #endif -#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x810u) +#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x811u) pThis->__cliresCtrlCmdGpuGetIdInfo__ = &cliresCtrlCmdGpuGetIdInfo_IMPL; #endif -#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x810u) +#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x811u) pThis->__cliresCtrlCmdGpuGetIdInfoV2__ = &cliresCtrlCmdGpuGetIdInfoV2_IMPL; #endif -#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x11u) +#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x811u) pThis->__cliresCtrlCmdGpuGetInitStatus__ = &cliresCtrlCmdGpuGetInitStatus_IMPL; #endif -#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x13u) +#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x813u) pThis->__cliresCtrlCmdGpuGetDeviceIds__ = &cliresCtrlCmdGpuGetDeviceIds_IMPL; #endif @@ -1680,19 +1941,19 @@ pThis->__cliresCtrlCmdGpuGetProbedIds__ = &cliresCtrlCmdGpuGetProbedIds_IMPL; #endif -#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x11u) +#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x811u) pThis->__cliresCtrlCmdGpuAttachIds__ = &cliresCtrlCmdGpuAttachIds_IMPL; #endif -#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x11u) +#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x811u) pThis->__cliresCtrlCmdGpuDetachIds__ = &cliresCtrlCmdGpuDetachIds_IMPL; #endif -#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) +#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x811u) pThis->__cliresCtrlCmdGpuGetSvmSize__ = &cliresCtrlCmdGpuGetSvmSize_IMPL; #endif -#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x810u) +#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x811u) pThis->__cliresCtrlCmdGpuGetPciInfo__ = &cliresCtrlCmdGpuGetPciInfo_IMPL; #endif @@ -1700,7 +1961,7 @@ pThis->__cliresCtrlCmdGpuGetUuidInfo__ = &cliresCtrlCmdGpuGetUuidInfo_IMPL; #endif -#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) +#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x811u) pThis->__cliresCtrlCmdGpuGetUuidFromGpuId__ = &cliresCtrlCmdGpuGetUuidFromGpuId_IMPL; #endif @@ -1708,11 +1969,11 @@ pThis->__cliresCtrlCmdGpuModifyGpuDrainState__ = &cliresCtrlCmdGpuModifyGpuDrainState_IMPL; #endif -#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x11u) +#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x811u) pThis->__cliresCtrlCmdGpuQueryGpuDrainState__ = &cliresCtrlCmdGpuQueryGpuDrainState_IMPL; #endif -#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x811u) +#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x4811u) pThis->__cliresCtrlCmdGpuGetMemOpEnable__ = &cliresCtrlCmdGpuGetMemOpEnable_IMPL; #endif @@ -1720,6 +1981,14 @@ pThis->__cliresCtrlCmdGpuDisableNvlinkInit__ = &cliresCtrlCmdGpuDisableNvlinkInit_IMPL; #endif +#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x4u) + pThis->__cliresCtrlCmdGpuSetNvlinkBwMode__ = &cliresCtrlCmdGpuSetNvlinkBwMode_IMPL; +#endif + +#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x813u) + pThis->__cliresCtrlCmdGpuGetNvlinkBwMode__ = &cliresCtrlCmdGpuGetNvlinkBwMode_IMPL; +#endif + #if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) pThis->__cliresCtrlCmdLegacyConfig__ = &cliresCtrlCmdLegacyConfig_IMPL; #endif @@ -1732,6 +2001,10 @@ pThis->__cliresCtrlCmdPushGspUcode__ = &cliresCtrlCmdPushGspUcode_IMPL; #endif +#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x11u) + pThis->__cliresCtrlCmdGpuGetVideoLinks__ = &cliresCtrlCmdGpuGetVideoLinks_IMPL; +#endif + #if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) pThis->__cliresCtrlCmdGsyncGetAttachedIds__ = &cliresCtrlCmdGsyncGetAttachedIds_IMPL; #endif @@ -1756,7 +2029,7 @@ pThis->__cliresCtrlCmdOsUnixImportObjectFromFd__ = &cliresCtrlCmdOsUnixImportObjectFromFd_IMPL; #endif -#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x11u) +#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x813u) pThis->__cliresCtrlCmdOsUnixGetExportObjectInfo__ = &cliresCtrlCmdOsUnixGetExportObjectInfo_IMPL; #endif @@ -1796,11 +2069,11 @@ pThis->__cliresCtrlCmdGpuAcctClearAccountingData__ = &cliresCtrlCmdGpuAcctClearAccountingData_IMPL; #endif -#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) +#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x811u) pThis->__cliresCtrlCmdSetSubProcessID__ = &cliresCtrlCmdSetSubProcessID_IMPL; #endif -#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) +#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x811u) pThis->__cliresCtrlCmdDisableSubProcessUserdIsolation__ = &cliresCtrlCmdDisableSubProcessUserdIsolation_IMPL; #endif @@ -1841,6 +2114,30 @@ #endif #if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) + pThis->__cliresCtrlCmdSystemPfmreqhndlrCtrl__ = &cliresCtrlCmdSystemPfmreqhndlrCtrl_IMPL; +#endif + +#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) + pThis->__cliresCtrlCmdSystemPfmreqhndlrGetFrmData__ = &cliresCtrlCmdSystemPfmreqhndlrGetFrmData_IMPL; +#endif + +#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) + pThis->__cliresCtrlCmdSystemPfmreqhndlrSetFrmData__ = &cliresCtrlCmdSystemPfmreqhndlrSetFrmData_IMPL; +#endif + +#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) + pThis->__cliresCtrlCmdSystemPfmreqhndlrCallAcpi__ = &cliresCtrlCmdSystemPfmreqhndlrCallAcpi_IMPL; +#endif + +#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) + pThis->__cliresCtrlCmdSystemPfmreqhndlrControl__ = &cliresCtrlCmdSystemPfmreqhndlrControl_IMPL; +#endif + +#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) + pThis->__cliresCtrlCmdSystemPfmreqhndlrBatchControl__ = &cliresCtrlCmdSystemPfmreqhndlrBatchControl_IMPL; +#endif + +#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) pThis->__cliresCtrlCmdSystemPfmreqhndlrGetPerfSensorCounters__ = &cliresCtrlCmdSystemPfmreqhndlrGetPerfSensorCounters_IMPL; #endif @@ -1852,6 +2149,10 @@ pThis->__nvoc_base_RsClientResource.__nvoc_base_RsResource.__resShareCallback__ = &__nvoc_thunk_RmClientResource_resShareCallback; + pThis->__nvoc_base_RsClientResource.__nvoc_base_RsResource.__resControl_Prologue__ = &__nvoc_thunk_RmClientResource_resControl_Prologue; + + pThis->__nvoc_base_RsClientResource.__nvoc_base_RsResource.__resControl_Epilogue__ = &__nvoc_thunk_RmClientResource_resControl_Epilogue; + pThis->__cliresControl__ = &__nvoc_thunk_RsResource_cliresControl; pThis->__cliresUnmap__ = &__nvoc_thunk_RsResource_cliresUnmap; @@ -1868,9 +2169,9 @@ pThis->__cliresUnregisterEvent__ = &__nvoc_thunk_Notifier_cliresUnregisterEvent; - pThis->__cliresCanCopy__ = &__nvoc_thunk_RsResource_cliresCanCopy; + pThis->__cliresControlSerialization_Prologue__ = &__nvoc_thunk_RsResource_cliresControlSerialization_Prologue; - pThis->__cliresControl_Prologue__ = &__nvoc_thunk_RsResource_cliresControl_Prologue; + pThis->__cliresCanCopy__ = &__nvoc_thunk_RsResource_cliresCanCopy; pThis->__cliresPreDestruct__ = &__nvoc_thunk_RsResource_cliresPreDestruct; @@ -1878,9 +2179,9 @@ pThis->__cliresIsDuplicate__ = &__nvoc_thunk_RsResource_cliresIsDuplicate; - pThis->__cliresGetNotificationListPtr__ = &__nvoc_thunk_Notifier_cliresGetNotificationListPtr; + pThis->__cliresControlSerialization_Epilogue__ = &__nvoc_thunk_RsResource_cliresControlSerialization_Epilogue; - pThis->__cliresControl_Epilogue__ = &__nvoc_thunk_RsResource_cliresControl_Epilogue; + pThis->__cliresGetNotificationListPtr__ = &__nvoc_thunk_Notifier_cliresGetNotificationListPtr; pThis->__cliresGetNotificationShare__ = &__nvoc_thunk_Notifier_cliresGetNotificationShare; @@ -1917,13 +2218,16 @@ Object *pParentObj; RmClientResource *pThis; - pThis = portMemAllocNonPaged(sizeof(RmClientResource)); - if (pThis == NULL) return NV_ERR_NO_MEMORY; + status = __nvoc_handleObjCreateMemAlloc(createFlags, sizeof(RmClientResource), (void**)&pThis, (void**)ppThis); + if (status != NV_OK) + return status; portMemSet(pThis, 0, sizeof(RmClientResource)); __nvoc_initRtti(staticCast(pThis, Dynamic), &__nvoc_class_def_RmClientResource); + pThis->__nvoc_base_RsClientResource.__nvoc_base_RsResource.__nvoc_base_Object.createFlags = createFlags; + if (pParent != NULL && !(createFlags & NVOC_OBJ_CREATE_FLAGS_PARENT_HALSPEC_ONLY)) { pParentObj = dynamicCast(pParent, Object); @@ -1939,11 +2243,17 @@ if (status != NV_OK) goto __nvoc_objCreate_RmClientResource_cleanup; *ppThis = pThis; + return NV_OK; __nvoc_objCreate_RmClientResource_cleanup: // do not call destructors here since the constructor already called them - portMemFree(pThis); + if (createFlags & NVOC_OBJ_CREATE_FLAGS_IN_PLACE_CONSTRUCT) + portMemSet(pThis, 0, sizeof(RmClientResource)); + else + portMemFree(pThis); + + // coverity[leaked_storage:FALSE] return status; } diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/generated/g_client_resource_nvoc.h nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_client_resource_nvoc.h --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/generated/g_client_resource_nvoc.h 2023-10-25 20:26:53.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_client_resource_nvoc.h 2024-03-05 22:18:08.000000000 +0000 @@ -30,6 +30,7 @@ */ #include "g_client_resource_nvoc.h" + #ifndef _CLIENT_RESOURCE_H_ #define _CLIENT_RESOURCE_H_ @@ -75,6 +76,8 @@ struct RmClientResource *__nvoc_pbase_RmClientResource; NvBool (*__cliresAccessCallback__)(struct RmClientResource *, struct RsClient *, void *, RsAccessRight); NvBool (*__cliresShareCallback__)(struct RmClientResource *, struct RsClient *, struct RsResourceRef *, RS_SHARE_POLICY *); + NV_STATUS (*__cliresControl_Prologue__)(struct RmClientResource *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); + void (*__cliresControl_Epilogue__)(struct RmClientResource *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); NV_STATUS (*__cliresCtrlCmdSystemGetCpuInfo__)(struct RmClientResource *, NV0000_CTRL_SYSTEM_GET_CPU_INFO_PARAMS *); NV_STATUS (*__cliresCtrlCmdSystemGetFeatures__)(struct RmClientResource *, NV0000_CTRL_SYSTEM_GET_FEATURES_PARAMS *); NV_STATUS (*__cliresCtrlCmdSystemGetBuildVersionV2__)(struct RmClientResource *, NV0000_CTRL_SYSTEM_GET_BUILD_VERSION_V2_PARAMS *); @@ -85,10 +88,16 @@ NV_STATUS (*__cliresCtrlCmdSystemNotifyEvent__)(struct RmClientResource *, NV0000_CTRL_SYSTEM_NOTIFY_EVENT_PARAMS *); NV_STATUS (*__cliresCtrlCmdSystemGetPlatformType__)(struct RmClientResource *, NV0000_CTRL_CMD_SYSTEM_GET_PLATFORM_TYPE_PARAMS *); NV_STATUS (*__cliresCtrlCmdSystemDebugCtrlRmMsg__)(struct RmClientResource *, NV0000_CTRL_SYSTEM_DEBUG_RMMSG_CTRL_PARAMS *); + NV_STATUS (*__cliresCtrlCmdSystemGpsControl__)(struct RmClientResource *, NV0000_CTRL_SYSTEM_GPS_CONTROL_PARAMS *); + NV_STATUS (*__cliresCtrlCmdSystemGpsBatchControl__)(struct RmClientResource *, NV0000_CTRL_SYSTEM_GPS_BATCH_CONTROL_PARAMS *); NV_STATUS (*__cliresCtrlCmdSystemGetHwbcInfo__)(struct RmClientResource *, NV0000_CTRL_SYSTEM_GET_HWBC_INFO_PARAMS *); NV_STATUS (*__cliresCtrlCmdSystemGetP2pCaps__)(struct RmClientResource *, NV0000_CTRL_SYSTEM_GET_P2P_CAPS_PARAMS *); NV_STATUS (*__cliresCtrlCmdSystemGetP2pCapsV2__)(struct RmClientResource *, NV0000_CTRL_SYSTEM_GET_P2P_CAPS_V2_PARAMS *); NV_STATUS (*__cliresCtrlCmdSystemGetP2pCapsMatrix__)(struct RmClientResource *, NV0000_CTRL_SYSTEM_GET_P2P_CAPS_MATRIX_PARAMS *); + NV_STATUS (*__cliresCtrlCmdSystemGpsCtrl__)(struct RmClientResource *, NV0000_CTRL_SYSTEM_GPS_CTRL_PARAMS *); + NV_STATUS (*__cliresCtrlCmdSystemGpsGetFrmData__)(struct RmClientResource *, NV0000_CTRL_SYSTEM_GPS_GET_FRM_DATA_PARAMS *); + NV_STATUS (*__cliresCtrlCmdSystemGpsSetFrmData__)(struct RmClientResource *, NV0000_CTRL_SYSTEM_GPS_SET_FRM_DATA_PARAMS *); + NV_STATUS (*__cliresCtrlCmdSystemGpsCallAcpi__)(struct RmClientResource *, NV0000_CTRL_SYSTEM_GPS_CALL_ACPI_PARAMS *); NV_STATUS (*__cliresCtrlCmdSystemGetPerfSensorCounters__)(struct RmClientResource *, NV0000_CTRL_SYSTEM_GPS_GET_PERF_SENSOR_COUNTERS_PARAMS *); NV_STATUS (*__cliresCtrlCmdSystemGetExtendedPerfSensorCounters__)(struct RmClientResource *, NV0000_CTRL_SYSTEM_GPS_GET_PERF_SENSOR_COUNTERS_PARAMS *); NV_STATUS (*__cliresCtrlCmdSystemGetGpusPowerStatus__)(struct RmClientResource *, NV0000_CTRL_SYSTEM_GET_GPUS_POWER_STATUS_PARAMS *); @@ -127,9 +136,12 @@ NV_STATUS (*__cliresCtrlCmdGpuQueryGpuDrainState__)(struct RmClientResource *, NV0000_CTRL_GPU_QUERY_DRAIN_STATE_PARAMS *); NV_STATUS (*__cliresCtrlCmdGpuGetMemOpEnable__)(struct RmClientResource *, NV0000_CTRL_GPU_GET_MEMOP_ENABLE_PARAMS *); NV_STATUS (*__cliresCtrlCmdGpuDisableNvlinkInit__)(struct RmClientResource *, NV0000_CTRL_GPU_DISABLE_NVLINK_INIT_PARAMS *); + NV_STATUS (*__cliresCtrlCmdGpuSetNvlinkBwMode__)(struct RmClientResource *, NV0000_CTRL_GPU_SET_NVLINK_BW_MODE_PARAMS *); + NV_STATUS (*__cliresCtrlCmdGpuGetNvlinkBwMode__)(struct RmClientResource *, NV0000_CTRL_GPU_GET_NVLINK_BW_MODE_PARAMS *); NV_STATUS (*__cliresCtrlCmdLegacyConfig__)(struct RmClientResource *, NV0000_CTRL_GPU_LEGACY_CONFIG_PARAMS *); NV_STATUS (*__cliresCtrlCmdIdleChannels__)(struct RmClientResource *, NV0000_CTRL_GPU_IDLE_CHANNELS_PARAMS *); NV_STATUS (*__cliresCtrlCmdPushGspUcode__)(struct RmClientResource *, NV0000_CTRL_GPU_PUSH_GSP_UCODE_PARAMS *); + NV_STATUS (*__cliresCtrlCmdGpuGetVideoLinks__)(struct RmClientResource *, NV0000_CTRL_GPU_GET_VIDEO_LINKS_PARAMS *); NV_STATUS (*__cliresCtrlCmdGsyncGetAttachedIds__)(struct RmClientResource *, NV0000_CTRL_GSYNC_GET_ATTACHED_IDS_PARAMS *); NV_STATUS (*__cliresCtrlCmdGsyncGetIdInfo__)(struct RmClientResource *, NV0000_CTRL_GSYNC_GET_ID_INFO_PARAMS *); NV_STATUS (*__cliresCtrlCmdEventSetNotification__)(struct RmClientResource *, NV0000_CTRL_EVENT_SET_NOTIFICATION_PARAMS *); @@ -157,6 +169,12 @@ NV_STATUS (*__cliresCtrlCmdVgpuSetVgpuVersion__)(struct RmClientResource *, NV0000_CTRL_VGPU_SET_VGPU_VERSION_PARAMS *); NV_STATUS (*__cliresCtrlCmdSystemNVPCFGetPowerModeInfo__)(struct RmClientResource *, NV0000_CTRL_CMD_SYSTEM_NVPCF_GET_POWER_MODE_INFO_PARAMS *); NV_STATUS (*__cliresCtrlCmdSystemSyncExternalFabricMgmt__)(struct RmClientResource *, NV0000_CTRL_CMD_SYSTEM_SYNC_EXTERNAL_FABRIC_MGMT_PARAMS *); + NV_STATUS (*__cliresCtrlCmdSystemPfmreqhndlrCtrl__)(struct RmClientResource *, NV0000_CTRL_SYSTEM_PFM_REQ_HNDLR_CTRL_PARAMS *); + NV_STATUS (*__cliresCtrlCmdSystemPfmreqhndlrGetFrmData__)(struct RmClientResource *, NV0000_CTRL_SYSTEM_PFM_REQ_HNDLR_GET_FRM_DATA_PARAMS *); + NV_STATUS (*__cliresCtrlCmdSystemPfmreqhndlrSetFrmData__)(struct RmClientResource *, NV0000_CTRL_SYSTEM_PFM_REQ_HNDLR_SET_FRM_DATA_PARAMS *); + NV_STATUS (*__cliresCtrlCmdSystemPfmreqhndlrCallAcpi__)(struct RmClientResource *, NV0000_CTRL_SYSTEM_PFM_REQ_HNDLR_CALL_ACPI_PARAMS *); + NV_STATUS (*__cliresCtrlCmdSystemPfmreqhndlrControl__)(struct RmClientResource *, NV0000_CTRL_SYSTEM_PFM_REQ_HNDLR_CONTROL_PARAMS *); + NV_STATUS (*__cliresCtrlCmdSystemPfmreqhndlrBatchControl__)(struct RmClientResource *, NV0000_CTRL_SYSTEM_PFM_REQ_HNDLR_BATCH_CONTROL_PARAMS *); NV_STATUS (*__cliresCtrlCmdSystemPfmreqhndlrGetPerfSensorCounters__)(struct RmClientResource *, NV0000_CTRL_SYSTEM_PFM_REQ_HNDLR_GET_PERF_SENSOR_COUNTERS_PARAMS *); NV_STATUS (*__cliresCtrlCmdSystemPfmreqhndlrGetExtendedPerfSensorCounters__)(struct RmClientResource *, NV0000_CTRL_SYSTEM_PFM_REQ_HNDLR_GET_PERF_SENSOR_COUNTERS_PARAMS *); NV_STATUS (*__cliresControl__)(struct RmClientResource *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); @@ -167,13 +185,13 @@ void (*__cliresAddAdditionalDependants__)(struct RsClient *, struct RmClientResource *, RsResourceRef *); NvU32 (*__cliresGetRefCount__)(struct RmClientResource *); NV_STATUS (*__cliresUnregisterEvent__)(struct RmClientResource *, NvHandle, NvHandle, NvHandle, NvHandle); + NV_STATUS (*__cliresControlSerialization_Prologue__)(struct RmClientResource *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); NvBool (*__cliresCanCopy__)(struct RmClientResource *); - NV_STATUS (*__cliresControl_Prologue__)(struct RmClientResource *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); void (*__cliresPreDestruct__)(struct RmClientResource *); NV_STATUS (*__cliresUnmapFrom__)(struct RmClientResource *, RS_RES_UNMAP_FROM_PARAMS *); NV_STATUS (*__cliresIsDuplicate__)(struct RmClientResource *, NvHandle, NvBool *); + void (*__cliresControlSerialization_Epilogue__)(struct RmClientResource *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); PEVENTNOTIFICATION *(*__cliresGetNotificationListPtr__)(struct RmClientResource *); - void (*__cliresControl_Epilogue__)(struct RmClientResource *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); struct NotifShare *(*__cliresGetNotificationShare__)(struct RmClientResource *); NV_STATUS (*__cliresControlLookup__)(struct RmClientResource *, struct RS_RES_CONTROL_PARAMS_INTERNAL *, const struct NVOC_EXPORTED_METHOD_DEF **); NV_STATUS (*__cliresMap__)(struct RmClientResource *, struct CALL_CONTEXT *, RS_CPU_MAP_PARAMS *, RsCpuMapping *); @@ -210,6 +228,8 @@ #define cliresAccessCallback(pRmCliRes, pInvokingClient, pAllocParams, accessRight) cliresAccessCallback_DISPATCH(pRmCliRes, pInvokingClient, pAllocParams, accessRight) #define cliresShareCallback(pRmCliRes, pInvokingClient, pParentRef, pSharePolicy) cliresShareCallback_DISPATCH(pRmCliRes, pInvokingClient, pParentRef, pSharePolicy) +#define cliresControl_Prologue(pRmCliRes, pCallContext, pParams) cliresControl_Prologue_DISPATCH(pRmCliRes, pCallContext, pParams) +#define cliresControl_Epilogue(pRmCliRes, pCallContext, pParams) cliresControl_Epilogue_DISPATCH(pRmCliRes, pCallContext, pParams) #define cliresCtrlCmdSystemGetCpuInfo(pRmCliRes, pCpuInfoParams) cliresCtrlCmdSystemGetCpuInfo_DISPATCH(pRmCliRes, pCpuInfoParams) #define cliresCtrlCmdSystemGetFeatures(pRmCliRes, pParams) cliresCtrlCmdSystemGetFeatures_DISPATCH(pRmCliRes, pParams) #define cliresCtrlCmdSystemGetBuildVersionV2(pRmCliRes, pParams) cliresCtrlCmdSystemGetBuildVersionV2_DISPATCH(pRmCliRes, pParams) @@ -220,10 +240,16 @@ #define cliresCtrlCmdSystemNotifyEvent(pRmCliRes, pParams) cliresCtrlCmdSystemNotifyEvent_DISPATCH(pRmCliRes, pParams) #define cliresCtrlCmdSystemGetPlatformType(pRmCliRes, pSysParams) cliresCtrlCmdSystemGetPlatformType_DISPATCH(pRmCliRes, pSysParams) #define cliresCtrlCmdSystemDebugCtrlRmMsg(pRmCliRes, pParams) cliresCtrlCmdSystemDebugCtrlRmMsg_DISPATCH(pRmCliRes, pParams) +#define cliresCtrlCmdSystemGpsControl(pRmCliRes, controlParams) cliresCtrlCmdSystemGpsControl_DISPATCH(pRmCliRes, controlParams) +#define cliresCtrlCmdSystemGpsBatchControl(pRmCliRes, controlParams) cliresCtrlCmdSystemGpsBatchControl_DISPATCH(pRmCliRes, controlParams) #define cliresCtrlCmdSystemGetHwbcInfo(pRmCliRes, pParams) cliresCtrlCmdSystemGetHwbcInfo_DISPATCH(pRmCliRes, pParams) #define cliresCtrlCmdSystemGetP2pCaps(pRmCliRes, pP2PParams) cliresCtrlCmdSystemGetP2pCaps_DISPATCH(pRmCliRes, pP2PParams) #define cliresCtrlCmdSystemGetP2pCapsV2(pRmCliRes, pP2PParams) cliresCtrlCmdSystemGetP2pCapsV2_DISPATCH(pRmCliRes, pP2PParams) #define cliresCtrlCmdSystemGetP2pCapsMatrix(pRmCliRes, pP2PParams) cliresCtrlCmdSystemGetP2pCapsMatrix_DISPATCH(pRmCliRes, pP2PParams) +#define cliresCtrlCmdSystemGpsCtrl(pRmCliRes, pParams) cliresCtrlCmdSystemGpsCtrl_DISPATCH(pRmCliRes, pParams) +#define cliresCtrlCmdSystemGpsGetFrmData(pRmCliRes, pParams) cliresCtrlCmdSystemGpsGetFrmData_DISPATCH(pRmCliRes, pParams) +#define cliresCtrlCmdSystemGpsSetFrmData(pRmCliRes, pParams) cliresCtrlCmdSystemGpsSetFrmData_DISPATCH(pRmCliRes, pParams) +#define cliresCtrlCmdSystemGpsCallAcpi(pRmCliRes, pParams) cliresCtrlCmdSystemGpsCallAcpi_DISPATCH(pRmCliRes, pParams) #define cliresCtrlCmdSystemGetPerfSensorCounters(pRmCliRes, pParams) cliresCtrlCmdSystemGetPerfSensorCounters_DISPATCH(pRmCliRes, pParams) #define cliresCtrlCmdSystemGetExtendedPerfSensorCounters(pRmCliRes, pParams) cliresCtrlCmdSystemGetExtendedPerfSensorCounters_DISPATCH(pRmCliRes, pParams) #define cliresCtrlCmdSystemGetGpusPowerStatus(pRmCliRes, pGpusPowerStatus) cliresCtrlCmdSystemGetGpusPowerStatus_DISPATCH(pRmCliRes, pGpusPowerStatus) @@ -262,9 +288,12 @@ #define cliresCtrlCmdGpuQueryGpuDrainState(pRmCliRes, pParams) cliresCtrlCmdGpuQueryGpuDrainState_DISPATCH(pRmCliRes, pParams) #define cliresCtrlCmdGpuGetMemOpEnable(pRmCliRes, pMemOpEnableParams) cliresCtrlCmdGpuGetMemOpEnable_DISPATCH(pRmCliRes, pMemOpEnableParams) #define cliresCtrlCmdGpuDisableNvlinkInit(pRmCliRes, pParams) cliresCtrlCmdGpuDisableNvlinkInit_DISPATCH(pRmCliRes, pParams) +#define cliresCtrlCmdGpuSetNvlinkBwMode(pRmCliRes, pParams) cliresCtrlCmdGpuSetNvlinkBwMode_DISPATCH(pRmCliRes, pParams) +#define cliresCtrlCmdGpuGetNvlinkBwMode(pRmCliRes, pParams) cliresCtrlCmdGpuGetNvlinkBwMode_DISPATCH(pRmCliRes, pParams) #define cliresCtrlCmdLegacyConfig(pRmCliRes, pParams) cliresCtrlCmdLegacyConfig_DISPATCH(pRmCliRes, pParams) #define cliresCtrlCmdIdleChannels(pRmCliRes, pParams) cliresCtrlCmdIdleChannels_DISPATCH(pRmCliRes, pParams) #define cliresCtrlCmdPushGspUcode(pRmCliRes, pParams) cliresCtrlCmdPushGspUcode_DISPATCH(pRmCliRes, pParams) +#define cliresCtrlCmdGpuGetVideoLinks(pRmCliRes, pParams) cliresCtrlCmdGpuGetVideoLinks_DISPATCH(pRmCliRes, pParams) #define cliresCtrlCmdGsyncGetAttachedIds(pRmCliRes, pGsyncAttachedIds) cliresCtrlCmdGsyncGetAttachedIds_DISPATCH(pRmCliRes, pGsyncAttachedIds) #define cliresCtrlCmdGsyncGetIdInfo(pRmCliRes, pGsyncIdInfoParams) cliresCtrlCmdGsyncGetIdInfo_DISPATCH(pRmCliRes, pGsyncIdInfoParams) #define cliresCtrlCmdEventSetNotification(pRmCliRes, pEventSetNotificationParams) cliresCtrlCmdEventSetNotification_DISPATCH(pRmCliRes, pEventSetNotificationParams) @@ -292,6 +321,12 @@ #define cliresCtrlCmdVgpuSetVgpuVersion(pRmCliRes, vgpuVersionInfo) cliresCtrlCmdVgpuSetVgpuVersion_DISPATCH(pRmCliRes, vgpuVersionInfo) #define cliresCtrlCmdSystemNVPCFGetPowerModeInfo(pRmCliRes, pParams) cliresCtrlCmdSystemNVPCFGetPowerModeInfo_DISPATCH(pRmCliRes, pParams) #define cliresCtrlCmdSystemSyncExternalFabricMgmt(pRmCliRes, pExtFabricMgmtParams) cliresCtrlCmdSystemSyncExternalFabricMgmt_DISPATCH(pRmCliRes, pExtFabricMgmtParams) +#define cliresCtrlCmdSystemPfmreqhndlrCtrl(pRmCliRes, pParams) cliresCtrlCmdSystemPfmreqhndlrCtrl_DISPATCH(pRmCliRes, pParams) +#define cliresCtrlCmdSystemPfmreqhndlrGetFrmData(pRmCliRes, pParams) cliresCtrlCmdSystemPfmreqhndlrGetFrmData_DISPATCH(pRmCliRes, pParams) +#define cliresCtrlCmdSystemPfmreqhndlrSetFrmData(pRmCliRes, pParams) cliresCtrlCmdSystemPfmreqhndlrSetFrmData_DISPATCH(pRmCliRes, pParams) +#define cliresCtrlCmdSystemPfmreqhndlrCallAcpi(pRmCliRes, pParams) cliresCtrlCmdSystemPfmreqhndlrCallAcpi_DISPATCH(pRmCliRes, pParams) +#define cliresCtrlCmdSystemPfmreqhndlrControl(pRmCliRes, controlParams) cliresCtrlCmdSystemPfmreqhndlrControl_DISPATCH(pRmCliRes, controlParams) +#define cliresCtrlCmdSystemPfmreqhndlrBatchControl(pRmCliRes, controlParams) cliresCtrlCmdSystemPfmreqhndlrBatchControl_DISPATCH(pRmCliRes, controlParams) #define cliresCtrlCmdSystemPfmreqhndlrGetPerfSensorCounters(pRmCliRes, pParams) cliresCtrlCmdSystemPfmreqhndlrGetPerfSensorCounters_DISPATCH(pRmCliRes, pParams) #define cliresCtrlCmdSystemPfmreqhndlrGetExtendedPerfSensorCounters(pRmCliRes, pParams) cliresCtrlCmdSystemPfmreqhndlrGetExtendedPerfSensorCounters_DISPATCH(pRmCliRes, pParams) #define cliresControl(pResource, pCallContext, pParams) cliresControl_DISPATCH(pResource, pCallContext, pParams) @@ -302,13 +337,13 @@ #define cliresAddAdditionalDependants(pClient, pResource, pReference) cliresAddAdditionalDependants_DISPATCH(pClient, pResource, pReference) #define cliresGetRefCount(pResource) cliresGetRefCount_DISPATCH(pResource) #define cliresUnregisterEvent(pNotifier, hNotifierClient, hNotifierResource, hEventClient, hEvent) cliresUnregisterEvent_DISPATCH(pNotifier, hNotifierClient, hNotifierResource, hEventClient, hEvent) +#define cliresControlSerialization_Prologue(pResource, pCallContext, pParams) cliresControlSerialization_Prologue_DISPATCH(pResource, pCallContext, pParams) #define cliresCanCopy(pResource) cliresCanCopy_DISPATCH(pResource) -#define cliresControl_Prologue(pResource, pCallContext, pParams) cliresControl_Prologue_DISPATCH(pResource, pCallContext, pParams) #define cliresPreDestruct(pResource) cliresPreDestruct_DISPATCH(pResource) #define cliresUnmapFrom(pResource, pParams) cliresUnmapFrom_DISPATCH(pResource, pParams) #define cliresIsDuplicate(pResource, hMemory, pDuplicate) cliresIsDuplicate_DISPATCH(pResource, hMemory, pDuplicate) +#define cliresControlSerialization_Epilogue(pResource, pCallContext, pParams) cliresControlSerialization_Epilogue_DISPATCH(pResource, pCallContext, pParams) #define cliresGetNotificationListPtr(pNotifier) cliresGetNotificationListPtr_DISPATCH(pNotifier) -#define cliresControl_Epilogue(pResource, pCallContext, pParams) cliresControl_Epilogue_DISPATCH(pResource, pCallContext, pParams) #define cliresGetNotificationShare(pNotifier) cliresGetNotificationShare_DISPATCH(pNotifier) #define cliresControlLookup(pResource, pParams, ppEntry) cliresControlLookup_DISPATCH(pResource, pParams, ppEntry) #define cliresMap(pResource, pCallContext, pParams, pCpuMapping) cliresMap_DISPATCH(pResource, pCallContext, pParams, pCpuMapping) @@ -325,6 +360,18 @@ return pRmCliRes->__cliresShareCallback__(pRmCliRes, pInvokingClient, pParentRef, pSharePolicy); } +NV_STATUS cliresControl_Prologue_IMPL(struct RmClientResource *pRmCliRes, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams); + +static inline NV_STATUS cliresControl_Prologue_DISPATCH(struct RmClientResource *pRmCliRes, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return pRmCliRes->__cliresControl_Prologue__(pRmCliRes, pCallContext, pParams); +} + +void cliresControl_Epilogue_IMPL(struct RmClientResource *pRmCliRes, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams); + +static inline void cliresControl_Epilogue_DISPATCH(struct RmClientResource *pRmCliRes, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + pRmCliRes->__cliresControl_Epilogue__(pRmCliRes, pCallContext, pParams); +} + NV_STATUS cliresCtrlCmdSystemGetCpuInfo_IMPL(struct RmClientResource *pRmCliRes, NV0000_CTRL_SYSTEM_GET_CPU_INFO_PARAMS *pCpuInfoParams); static inline NV_STATUS cliresCtrlCmdSystemGetCpuInfo_DISPATCH(struct RmClientResource *pRmCliRes, NV0000_CTRL_SYSTEM_GET_CPU_INFO_PARAMS *pCpuInfoParams) { @@ -385,6 +432,18 @@ return pRmCliRes->__cliresCtrlCmdSystemDebugCtrlRmMsg__(pRmCliRes, pParams); } +NV_STATUS cliresCtrlCmdSystemGpsControl_IMPL(struct RmClientResource *pRmCliRes, NV0000_CTRL_SYSTEM_GPS_CONTROL_PARAMS *controlParams); + +static inline NV_STATUS cliresCtrlCmdSystemGpsControl_DISPATCH(struct RmClientResource *pRmCliRes, NV0000_CTRL_SYSTEM_GPS_CONTROL_PARAMS *controlParams) { + return pRmCliRes->__cliresCtrlCmdSystemGpsControl__(pRmCliRes, controlParams); +} + +NV_STATUS cliresCtrlCmdSystemGpsBatchControl_IMPL(struct RmClientResource *pRmCliRes, NV0000_CTRL_SYSTEM_GPS_BATCH_CONTROL_PARAMS *controlParams); + +static inline NV_STATUS cliresCtrlCmdSystemGpsBatchControl_DISPATCH(struct RmClientResource *pRmCliRes, NV0000_CTRL_SYSTEM_GPS_BATCH_CONTROL_PARAMS *controlParams) { + return pRmCliRes->__cliresCtrlCmdSystemGpsBatchControl__(pRmCliRes, controlParams); +} + NV_STATUS cliresCtrlCmdSystemGetHwbcInfo_IMPL(struct RmClientResource *pRmCliRes, NV0000_CTRL_SYSTEM_GET_HWBC_INFO_PARAMS *pParams); static inline NV_STATUS cliresCtrlCmdSystemGetHwbcInfo_DISPATCH(struct RmClientResource *pRmCliRes, NV0000_CTRL_SYSTEM_GET_HWBC_INFO_PARAMS *pParams) { @@ -409,6 +468,30 @@ return pRmCliRes->__cliresCtrlCmdSystemGetP2pCapsMatrix__(pRmCliRes, pP2PParams); } +NV_STATUS cliresCtrlCmdSystemGpsCtrl_IMPL(struct RmClientResource *pRmCliRes, NV0000_CTRL_SYSTEM_GPS_CTRL_PARAMS *pParams); + +static inline NV_STATUS cliresCtrlCmdSystemGpsCtrl_DISPATCH(struct RmClientResource *pRmCliRes, NV0000_CTRL_SYSTEM_GPS_CTRL_PARAMS *pParams) { + return pRmCliRes->__cliresCtrlCmdSystemGpsCtrl__(pRmCliRes, pParams); +} + +NV_STATUS cliresCtrlCmdSystemGpsGetFrmData_IMPL(struct RmClientResource *pRmCliRes, NV0000_CTRL_SYSTEM_GPS_GET_FRM_DATA_PARAMS *pParams); + +static inline NV_STATUS cliresCtrlCmdSystemGpsGetFrmData_DISPATCH(struct RmClientResource *pRmCliRes, NV0000_CTRL_SYSTEM_GPS_GET_FRM_DATA_PARAMS *pParams) { + return pRmCliRes->__cliresCtrlCmdSystemGpsGetFrmData__(pRmCliRes, pParams); +} + +NV_STATUS cliresCtrlCmdSystemGpsSetFrmData_IMPL(struct RmClientResource *pRmCliRes, NV0000_CTRL_SYSTEM_GPS_SET_FRM_DATA_PARAMS *pParams); + +static inline NV_STATUS cliresCtrlCmdSystemGpsSetFrmData_DISPATCH(struct RmClientResource *pRmCliRes, NV0000_CTRL_SYSTEM_GPS_SET_FRM_DATA_PARAMS *pParams) { + return pRmCliRes->__cliresCtrlCmdSystemGpsSetFrmData__(pRmCliRes, pParams); +} + +NV_STATUS cliresCtrlCmdSystemGpsCallAcpi_IMPL(struct RmClientResource *pRmCliRes, NV0000_CTRL_SYSTEM_GPS_CALL_ACPI_PARAMS *pParams); + +static inline NV_STATUS cliresCtrlCmdSystemGpsCallAcpi_DISPATCH(struct RmClientResource *pRmCliRes, NV0000_CTRL_SYSTEM_GPS_CALL_ACPI_PARAMS *pParams) { + return pRmCliRes->__cliresCtrlCmdSystemGpsCallAcpi__(pRmCliRes, pParams); +} + NV_STATUS cliresCtrlCmdSystemGetPerfSensorCounters_IMPL(struct RmClientResource *pRmCliRes, NV0000_CTRL_SYSTEM_GPS_GET_PERF_SENSOR_COUNTERS_PARAMS *pParams); static inline NV_STATUS cliresCtrlCmdSystemGetPerfSensorCounters_DISPATCH(struct RmClientResource *pRmCliRes, NV0000_CTRL_SYSTEM_GPS_GET_PERF_SENSOR_COUNTERS_PARAMS *pParams) { @@ -637,6 +720,18 @@ return pRmCliRes->__cliresCtrlCmdGpuDisableNvlinkInit__(pRmCliRes, pParams); } +NV_STATUS cliresCtrlCmdGpuSetNvlinkBwMode_IMPL(struct RmClientResource *pRmCliRes, NV0000_CTRL_GPU_SET_NVLINK_BW_MODE_PARAMS *pParams); + +static inline NV_STATUS cliresCtrlCmdGpuSetNvlinkBwMode_DISPATCH(struct RmClientResource *pRmCliRes, NV0000_CTRL_GPU_SET_NVLINK_BW_MODE_PARAMS *pParams) { + return pRmCliRes->__cliresCtrlCmdGpuSetNvlinkBwMode__(pRmCliRes, pParams); +} + +NV_STATUS cliresCtrlCmdGpuGetNvlinkBwMode_IMPL(struct RmClientResource *pRmCliRes, NV0000_CTRL_GPU_GET_NVLINK_BW_MODE_PARAMS *pParams); + +static inline NV_STATUS cliresCtrlCmdGpuGetNvlinkBwMode_DISPATCH(struct RmClientResource *pRmCliRes, NV0000_CTRL_GPU_GET_NVLINK_BW_MODE_PARAMS *pParams) { + return pRmCliRes->__cliresCtrlCmdGpuGetNvlinkBwMode__(pRmCliRes, pParams); +} + NV_STATUS cliresCtrlCmdLegacyConfig_IMPL(struct RmClientResource *pRmCliRes, NV0000_CTRL_GPU_LEGACY_CONFIG_PARAMS *pParams); static inline NV_STATUS cliresCtrlCmdLegacyConfig_DISPATCH(struct RmClientResource *pRmCliRes, NV0000_CTRL_GPU_LEGACY_CONFIG_PARAMS *pParams) { @@ -655,6 +750,12 @@ return pRmCliRes->__cliresCtrlCmdPushGspUcode__(pRmCliRes, pParams); } +NV_STATUS cliresCtrlCmdGpuGetVideoLinks_IMPL(struct RmClientResource *pRmCliRes, NV0000_CTRL_GPU_GET_VIDEO_LINKS_PARAMS *pParams); + +static inline NV_STATUS cliresCtrlCmdGpuGetVideoLinks_DISPATCH(struct RmClientResource *pRmCliRes, NV0000_CTRL_GPU_GET_VIDEO_LINKS_PARAMS *pParams) { + return pRmCliRes->__cliresCtrlCmdGpuGetVideoLinks__(pRmCliRes, pParams); +} + NV_STATUS cliresCtrlCmdGsyncGetAttachedIds_IMPL(struct RmClientResource *pRmCliRes, NV0000_CTRL_GSYNC_GET_ATTACHED_IDS_PARAMS *pGsyncAttachedIds); static inline NV_STATUS cliresCtrlCmdGsyncGetAttachedIds_DISPATCH(struct RmClientResource *pRmCliRes, NV0000_CTRL_GSYNC_GET_ATTACHED_IDS_PARAMS *pGsyncAttachedIds) { @@ -817,6 +918,42 @@ return pRmCliRes->__cliresCtrlCmdSystemSyncExternalFabricMgmt__(pRmCliRes, pExtFabricMgmtParams); } +NV_STATUS cliresCtrlCmdSystemPfmreqhndlrCtrl_IMPL(struct RmClientResource *pRmCliRes, NV0000_CTRL_SYSTEM_PFM_REQ_HNDLR_CTRL_PARAMS *pParams); + +static inline NV_STATUS cliresCtrlCmdSystemPfmreqhndlrCtrl_DISPATCH(struct RmClientResource *pRmCliRes, NV0000_CTRL_SYSTEM_PFM_REQ_HNDLR_CTRL_PARAMS *pParams) { + return pRmCliRes->__cliresCtrlCmdSystemPfmreqhndlrCtrl__(pRmCliRes, pParams); +} + +NV_STATUS cliresCtrlCmdSystemPfmreqhndlrGetFrmData_IMPL(struct RmClientResource *pRmCliRes, NV0000_CTRL_SYSTEM_PFM_REQ_HNDLR_GET_FRM_DATA_PARAMS *pParams); + +static inline NV_STATUS cliresCtrlCmdSystemPfmreqhndlrGetFrmData_DISPATCH(struct RmClientResource *pRmCliRes, NV0000_CTRL_SYSTEM_PFM_REQ_HNDLR_GET_FRM_DATA_PARAMS *pParams) { + return pRmCliRes->__cliresCtrlCmdSystemPfmreqhndlrGetFrmData__(pRmCliRes, pParams); +} + +NV_STATUS cliresCtrlCmdSystemPfmreqhndlrSetFrmData_IMPL(struct RmClientResource *pRmCliRes, NV0000_CTRL_SYSTEM_PFM_REQ_HNDLR_SET_FRM_DATA_PARAMS *pParams); + +static inline NV_STATUS cliresCtrlCmdSystemPfmreqhndlrSetFrmData_DISPATCH(struct RmClientResource *pRmCliRes, NV0000_CTRL_SYSTEM_PFM_REQ_HNDLR_SET_FRM_DATA_PARAMS *pParams) { + return pRmCliRes->__cliresCtrlCmdSystemPfmreqhndlrSetFrmData__(pRmCliRes, pParams); +} + +NV_STATUS cliresCtrlCmdSystemPfmreqhndlrCallAcpi_IMPL(struct RmClientResource *pRmCliRes, NV0000_CTRL_SYSTEM_PFM_REQ_HNDLR_CALL_ACPI_PARAMS *pParams); + +static inline NV_STATUS cliresCtrlCmdSystemPfmreqhndlrCallAcpi_DISPATCH(struct RmClientResource *pRmCliRes, NV0000_CTRL_SYSTEM_PFM_REQ_HNDLR_CALL_ACPI_PARAMS *pParams) { + return pRmCliRes->__cliresCtrlCmdSystemPfmreqhndlrCallAcpi__(pRmCliRes, pParams); +} + +NV_STATUS cliresCtrlCmdSystemPfmreqhndlrControl_IMPL(struct RmClientResource *pRmCliRes, NV0000_CTRL_SYSTEM_PFM_REQ_HNDLR_CONTROL_PARAMS *controlParams); + +static inline NV_STATUS cliresCtrlCmdSystemPfmreqhndlrControl_DISPATCH(struct RmClientResource *pRmCliRes, NV0000_CTRL_SYSTEM_PFM_REQ_HNDLR_CONTROL_PARAMS *controlParams) { + return pRmCliRes->__cliresCtrlCmdSystemPfmreqhndlrControl__(pRmCliRes, controlParams); +} + +NV_STATUS cliresCtrlCmdSystemPfmreqhndlrBatchControl_IMPL(struct RmClientResource *pRmCliRes, NV0000_CTRL_SYSTEM_PFM_REQ_HNDLR_BATCH_CONTROL_PARAMS *controlParams); + +static inline NV_STATUS cliresCtrlCmdSystemPfmreqhndlrBatchControl_DISPATCH(struct RmClientResource *pRmCliRes, NV0000_CTRL_SYSTEM_PFM_REQ_HNDLR_BATCH_CONTROL_PARAMS *controlParams) { + return pRmCliRes->__cliresCtrlCmdSystemPfmreqhndlrBatchControl__(pRmCliRes, controlParams); +} + NV_STATUS cliresCtrlCmdSystemPfmreqhndlrGetPerfSensorCounters_IMPL(struct RmClientResource *pRmCliRes, NV0000_CTRL_SYSTEM_PFM_REQ_HNDLR_GET_PERF_SENSOR_COUNTERS_PARAMS *pParams); static inline NV_STATUS cliresCtrlCmdSystemPfmreqhndlrGetPerfSensorCounters_DISPATCH(struct RmClientResource *pRmCliRes, NV0000_CTRL_SYSTEM_PFM_REQ_HNDLR_GET_PERF_SENSOR_COUNTERS_PARAMS *pParams) { @@ -861,12 +998,12 @@ return pNotifier->__cliresUnregisterEvent__(pNotifier, hNotifierClient, hNotifierResource, hEventClient, hEvent); } -static inline NvBool cliresCanCopy_DISPATCH(struct RmClientResource *pResource) { - return pResource->__cliresCanCopy__(pResource); +static inline NV_STATUS cliresControlSerialization_Prologue_DISPATCH(struct RmClientResource *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return pResource->__cliresControlSerialization_Prologue__(pResource, pCallContext, pParams); } -static inline NV_STATUS cliresControl_Prologue_DISPATCH(struct RmClientResource *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { - return pResource->__cliresControl_Prologue__(pResource, pCallContext, pParams); +static inline NvBool cliresCanCopy_DISPATCH(struct RmClientResource *pResource) { + return pResource->__cliresCanCopy__(pResource); } static inline void cliresPreDestruct_DISPATCH(struct RmClientResource *pResource) { @@ -881,12 +1018,12 @@ return pResource->__cliresIsDuplicate__(pResource, hMemory, pDuplicate); } -static inline PEVENTNOTIFICATION *cliresGetNotificationListPtr_DISPATCH(struct RmClientResource *pNotifier) { - return pNotifier->__cliresGetNotificationListPtr__(pNotifier); +static inline void cliresControlSerialization_Epilogue_DISPATCH(struct RmClientResource *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + pResource->__cliresControlSerialization_Epilogue__(pResource, pCallContext, pParams); } -static inline void cliresControl_Epilogue_DISPATCH(struct RmClientResource *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { - pResource->__cliresControl_Epilogue__(pResource, pCallContext, pParams); +static inline PEVENTNOTIFICATION *cliresGetNotificationListPtr_DISPATCH(struct RmClientResource *pNotifier) { + return pNotifier->__cliresGetNotificationListPtr__(pNotifier); } static inline struct NotifShare *cliresGetNotificationShare_DISPATCH(struct RmClientResource *pNotifier) { diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/generated/g_compute_instance_subscription_nvoc.c nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_compute_instance_subscription_nvoc.c --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/generated/g_compute_instance_subscription_nvoc.c 2023-10-25 20:26:53.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_compute_instance_subscription_nvoc.c 2024-03-05 22:18:08.000000000 +0000 @@ -101,48 +101,24 @@ return gpuresShareCallback((struct GpuResource *)(((unsigned char *)pGpuResource) + __nvoc_rtti_ComputeInstanceSubscription_GpuResource.offset), pInvokingClient, pParentRef, pSharePolicy); } -static NV_STATUS __nvoc_thunk_GpuResource_cisubscriptionControl(struct ComputeInstanceSubscription *pGpuResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { - return gpuresControl((struct GpuResource *)(((unsigned char *)pGpuResource) + __nvoc_rtti_ComputeInstanceSubscription_GpuResource.offset), pCallContext, pParams); -} - -static NV_STATUS __nvoc_thunk_GpuResource_cisubscriptionUnmap(struct ComputeInstanceSubscription *pGpuResource, struct CALL_CONTEXT *pCallContext, struct RsCpuMapping *pCpuMapping) { - return gpuresUnmap((struct GpuResource *)(((unsigned char *)pGpuResource) + __nvoc_rtti_ComputeInstanceSubscription_GpuResource.offset), pCallContext, pCpuMapping); -} - -static NV_STATUS __nvoc_thunk_RmResource_cisubscriptionGetMemInterMapParams(struct ComputeInstanceSubscription *pRmResource, RMRES_MEM_INTER_MAP_PARAMS *pParams) { - return rmresGetMemInterMapParams((struct RmResource *)(((unsigned char *)pRmResource) + __nvoc_rtti_ComputeInstanceSubscription_RmResource.offset), pParams); +static NV_STATUS __nvoc_thunk_RmResource_cisubscriptionCheckMemInterUnmap(struct ComputeInstanceSubscription *pRmResource, NvBool bSubdeviceHandleProvided) { + return rmresCheckMemInterUnmap((struct RmResource *)(((unsigned char *)pRmResource) + __nvoc_rtti_ComputeInstanceSubscription_RmResource.offset), bSubdeviceHandleProvided); } -static NV_STATUS __nvoc_thunk_RmResource_cisubscriptionGetMemoryMappingDescriptor(struct ComputeInstanceSubscription *pRmResource, struct MEMORY_DESCRIPTOR **ppMemDesc) { - return rmresGetMemoryMappingDescriptor((struct RmResource *)(((unsigned char *)pRmResource) + __nvoc_rtti_ComputeInstanceSubscription_RmResource.offset), ppMemDesc); +static NV_STATUS __nvoc_thunk_RsResource_cisubscriptionMapTo(struct ComputeInstanceSubscription *pResource, RS_RES_MAP_TO_PARAMS *pParams) { + return resMapTo((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_ComputeInstanceSubscription_RsResource.offset), pParams); } static NV_STATUS __nvoc_thunk_GpuResource_cisubscriptionGetMapAddrSpace(struct ComputeInstanceSubscription *pGpuResource, struct CALL_CONTEXT *pCallContext, NvU32 mapFlags, NV_ADDRESS_SPACE *pAddrSpace) { return gpuresGetMapAddrSpace((struct GpuResource *)(((unsigned char *)pGpuResource) + __nvoc_rtti_ComputeInstanceSubscription_GpuResource.offset), pCallContext, mapFlags, pAddrSpace); } -static NvHandle __nvoc_thunk_GpuResource_cisubscriptionGetInternalObjectHandle(struct ComputeInstanceSubscription *pGpuResource) { - return gpuresGetInternalObjectHandle((struct GpuResource *)(((unsigned char *)pGpuResource) + __nvoc_rtti_ComputeInstanceSubscription_GpuResource.offset)); -} - -static NV_STATUS __nvoc_thunk_RsResource_cisubscriptionControlFilter(struct ComputeInstanceSubscription *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { - return resControlFilter((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_ComputeInstanceSubscription_RsResource.offset), pCallContext, pParams); -} - -static void __nvoc_thunk_RsResource_cisubscriptionAddAdditionalDependants(struct RsClient *pClient, struct ComputeInstanceSubscription *pResource, RsResourceRef *pReference) { - resAddAdditionalDependants(pClient, (struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_ComputeInstanceSubscription_RsResource.offset), pReference); -} - static NvU32 __nvoc_thunk_RsResource_cisubscriptionGetRefCount(struct ComputeInstanceSubscription *pResource) { return resGetRefCount((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_ComputeInstanceSubscription_RsResource.offset)); } -static NV_STATUS __nvoc_thunk_RmResource_cisubscriptionCheckMemInterUnmap(struct ComputeInstanceSubscription *pRmResource, NvBool bSubdeviceHandleProvided) { - return rmresCheckMemInterUnmap((struct RmResource *)(((unsigned char *)pRmResource) + __nvoc_rtti_ComputeInstanceSubscription_RmResource.offset), bSubdeviceHandleProvided); -} - -static NV_STATUS __nvoc_thunk_RsResource_cisubscriptionMapTo(struct ComputeInstanceSubscription *pResource, RS_RES_MAP_TO_PARAMS *pParams) { - return resMapTo((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_ComputeInstanceSubscription_RsResource.offset), pParams); +static void __nvoc_thunk_RsResource_cisubscriptionAddAdditionalDependants(struct RsClient *pClient, struct ComputeInstanceSubscription *pResource, RsResourceRef *pReference) { + resAddAdditionalDependants(pClient, (struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_ComputeInstanceSubscription_RsResource.offset), pReference); } static NV_STATUS __nvoc_thunk_RmResource_cisubscriptionControl_Prologue(struct ComputeInstanceSubscription *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { @@ -157,18 +133,10 @@ return gpuresInternalControlForward((struct GpuResource *)(((unsigned char *)pGpuResource) + __nvoc_rtti_ComputeInstanceSubscription_GpuResource.offset), command, pParams, size); } -static void __nvoc_thunk_RsResource_cisubscriptionPreDestruct(struct ComputeInstanceSubscription *pResource) { - resPreDestruct((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_ComputeInstanceSubscription_RsResource.offset)); -} - static NV_STATUS __nvoc_thunk_RsResource_cisubscriptionUnmapFrom(struct ComputeInstanceSubscription *pResource, RS_RES_UNMAP_FROM_PARAMS *pParams) { return resUnmapFrom((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_ComputeInstanceSubscription_RsResource.offset), pParams); } -static NV_STATUS __nvoc_thunk_RsResource_cisubscriptionIsDuplicate(struct ComputeInstanceSubscription *pResource, NvHandle hMemory, NvBool *pDuplicate) { - return resIsDuplicate((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_ComputeInstanceSubscription_RsResource.offset), hMemory, pDuplicate); -} - static void __nvoc_thunk_RmResource_cisubscriptionControl_Epilogue(struct ComputeInstanceSubscription *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { rmresControl_Epilogue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_ComputeInstanceSubscription_RmResource.offset), pCallContext, pParams); } @@ -177,6 +145,46 @@ return resControlLookup((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_ComputeInstanceSubscription_RsResource.offset), pParams, ppEntry); } +static NvHandle __nvoc_thunk_GpuResource_cisubscriptionGetInternalObjectHandle(struct ComputeInstanceSubscription *pGpuResource) { + return gpuresGetInternalObjectHandle((struct GpuResource *)(((unsigned char *)pGpuResource) + __nvoc_rtti_ComputeInstanceSubscription_GpuResource.offset)); +} + +static NV_STATUS __nvoc_thunk_GpuResource_cisubscriptionControl(struct ComputeInstanceSubscription *pGpuResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return gpuresControl((struct GpuResource *)(((unsigned char *)pGpuResource) + __nvoc_rtti_ComputeInstanceSubscription_GpuResource.offset), pCallContext, pParams); +} + +static NV_STATUS __nvoc_thunk_GpuResource_cisubscriptionUnmap(struct ComputeInstanceSubscription *pGpuResource, struct CALL_CONTEXT *pCallContext, struct RsCpuMapping *pCpuMapping) { + return gpuresUnmap((struct GpuResource *)(((unsigned char *)pGpuResource) + __nvoc_rtti_ComputeInstanceSubscription_GpuResource.offset), pCallContext, pCpuMapping); +} + +static NV_STATUS __nvoc_thunk_RmResource_cisubscriptionGetMemInterMapParams(struct ComputeInstanceSubscription *pRmResource, RMRES_MEM_INTER_MAP_PARAMS *pParams) { + return rmresGetMemInterMapParams((struct RmResource *)(((unsigned char *)pRmResource) + __nvoc_rtti_ComputeInstanceSubscription_RmResource.offset), pParams); +} + +static NV_STATUS __nvoc_thunk_RmResource_cisubscriptionGetMemoryMappingDescriptor(struct ComputeInstanceSubscription *pRmResource, struct MEMORY_DESCRIPTOR **ppMemDesc) { + return rmresGetMemoryMappingDescriptor((struct RmResource *)(((unsigned char *)pRmResource) + __nvoc_rtti_ComputeInstanceSubscription_RmResource.offset), ppMemDesc); +} + +static NV_STATUS __nvoc_thunk_RsResource_cisubscriptionControlFilter(struct ComputeInstanceSubscription *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return resControlFilter((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_ComputeInstanceSubscription_RsResource.offset), pCallContext, pParams); +} + +static NV_STATUS __nvoc_thunk_RmResource_cisubscriptionControlSerialization_Prologue(struct ComputeInstanceSubscription *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return rmresControlSerialization_Prologue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_ComputeInstanceSubscription_RmResource.offset), pCallContext, pParams); +} + +static void __nvoc_thunk_RsResource_cisubscriptionPreDestruct(struct ComputeInstanceSubscription *pResource) { + resPreDestruct((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_ComputeInstanceSubscription_RsResource.offset)); +} + +static NV_STATUS __nvoc_thunk_RsResource_cisubscriptionIsDuplicate(struct ComputeInstanceSubscription *pResource, NvHandle hMemory, NvBool *pDuplicate) { + return resIsDuplicate((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_ComputeInstanceSubscription_RsResource.offset), hMemory, pDuplicate); +} + +static void __nvoc_thunk_RmResource_cisubscriptionControlSerialization_Epilogue(struct ComputeInstanceSubscription *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + rmresControlSerialization_Epilogue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_ComputeInstanceSubscription_RmResource.offset), pCallContext, pParams); +} + static NV_STATUS __nvoc_thunk_GpuResource_cisubscriptionMap(struct ComputeInstanceSubscription *pGpuResource, struct CALL_CONTEXT *pCallContext, struct RS_CPU_MAP_PARAMS *pParams, struct RsCpuMapping *pCpuMapping) { return gpuresMap((struct GpuResource *)(((unsigned char *)pGpuResource) + __nvoc_rtti_ComputeInstanceSubscription_GpuResource.offset), pCallContext, pParams, pCpuMapping); } @@ -258,27 +266,15 @@ pThis->__cisubscriptionShareCallback__ = &__nvoc_thunk_GpuResource_cisubscriptionShareCallback; - pThis->__cisubscriptionControl__ = &__nvoc_thunk_GpuResource_cisubscriptionControl; - - pThis->__cisubscriptionUnmap__ = &__nvoc_thunk_GpuResource_cisubscriptionUnmap; - - pThis->__cisubscriptionGetMemInterMapParams__ = &__nvoc_thunk_RmResource_cisubscriptionGetMemInterMapParams; + pThis->__cisubscriptionCheckMemInterUnmap__ = &__nvoc_thunk_RmResource_cisubscriptionCheckMemInterUnmap; - pThis->__cisubscriptionGetMemoryMappingDescriptor__ = &__nvoc_thunk_RmResource_cisubscriptionGetMemoryMappingDescriptor; + pThis->__cisubscriptionMapTo__ = &__nvoc_thunk_RsResource_cisubscriptionMapTo; pThis->__cisubscriptionGetMapAddrSpace__ = &__nvoc_thunk_GpuResource_cisubscriptionGetMapAddrSpace; - pThis->__cisubscriptionGetInternalObjectHandle__ = &__nvoc_thunk_GpuResource_cisubscriptionGetInternalObjectHandle; - - pThis->__cisubscriptionControlFilter__ = &__nvoc_thunk_RsResource_cisubscriptionControlFilter; - - pThis->__cisubscriptionAddAdditionalDependants__ = &__nvoc_thunk_RsResource_cisubscriptionAddAdditionalDependants; - pThis->__cisubscriptionGetRefCount__ = &__nvoc_thunk_RsResource_cisubscriptionGetRefCount; - pThis->__cisubscriptionCheckMemInterUnmap__ = &__nvoc_thunk_RmResource_cisubscriptionCheckMemInterUnmap; - - pThis->__cisubscriptionMapTo__ = &__nvoc_thunk_RsResource_cisubscriptionMapTo; + pThis->__cisubscriptionAddAdditionalDependants__ = &__nvoc_thunk_RsResource_cisubscriptionAddAdditionalDependants; pThis->__cisubscriptionControl_Prologue__ = &__nvoc_thunk_RmResource_cisubscriptionControl_Prologue; @@ -286,16 +282,32 @@ pThis->__cisubscriptionInternalControlForward__ = &__nvoc_thunk_GpuResource_cisubscriptionInternalControlForward; - pThis->__cisubscriptionPreDestruct__ = &__nvoc_thunk_RsResource_cisubscriptionPreDestruct; - pThis->__cisubscriptionUnmapFrom__ = &__nvoc_thunk_RsResource_cisubscriptionUnmapFrom; - pThis->__cisubscriptionIsDuplicate__ = &__nvoc_thunk_RsResource_cisubscriptionIsDuplicate; - pThis->__cisubscriptionControl_Epilogue__ = &__nvoc_thunk_RmResource_cisubscriptionControl_Epilogue; pThis->__cisubscriptionControlLookup__ = &__nvoc_thunk_RsResource_cisubscriptionControlLookup; + pThis->__cisubscriptionGetInternalObjectHandle__ = &__nvoc_thunk_GpuResource_cisubscriptionGetInternalObjectHandle; + + pThis->__cisubscriptionControl__ = &__nvoc_thunk_GpuResource_cisubscriptionControl; + + pThis->__cisubscriptionUnmap__ = &__nvoc_thunk_GpuResource_cisubscriptionUnmap; + + pThis->__cisubscriptionGetMemInterMapParams__ = &__nvoc_thunk_RmResource_cisubscriptionGetMemInterMapParams; + + pThis->__cisubscriptionGetMemoryMappingDescriptor__ = &__nvoc_thunk_RmResource_cisubscriptionGetMemoryMappingDescriptor; + + pThis->__cisubscriptionControlFilter__ = &__nvoc_thunk_RsResource_cisubscriptionControlFilter; + + pThis->__cisubscriptionControlSerialization_Prologue__ = &__nvoc_thunk_RmResource_cisubscriptionControlSerialization_Prologue; + + pThis->__cisubscriptionPreDestruct__ = &__nvoc_thunk_RsResource_cisubscriptionPreDestruct; + + pThis->__cisubscriptionIsDuplicate__ = &__nvoc_thunk_RsResource_cisubscriptionIsDuplicate; + + pThis->__cisubscriptionControlSerialization_Epilogue__ = &__nvoc_thunk_RmResource_cisubscriptionControlSerialization_Epilogue; + pThis->__cisubscriptionMap__ = &__nvoc_thunk_GpuResource_cisubscriptionMap; pThis->__cisubscriptionAccessCallback__ = &__nvoc_thunk_RmResource_cisubscriptionAccessCallback; @@ -322,13 +334,16 @@ Object *pParentObj; ComputeInstanceSubscription *pThis; - pThis = portMemAllocNonPaged(sizeof(ComputeInstanceSubscription)); - if (pThis == NULL) return NV_ERR_NO_MEMORY; + status = __nvoc_handleObjCreateMemAlloc(createFlags, sizeof(ComputeInstanceSubscription), (void**)&pThis, (void**)ppThis); + if (status != NV_OK) + return status; portMemSet(pThis, 0, sizeof(ComputeInstanceSubscription)); __nvoc_initRtti(staticCast(pThis, Dynamic), &__nvoc_class_def_ComputeInstanceSubscription); + pThis->__nvoc_base_GpuResource.__nvoc_base_RmResource.__nvoc_base_RsResource.__nvoc_base_Object.createFlags = createFlags; + if (pParent != NULL && !(createFlags & NVOC_OBJ_CREATE_FLAGS_PARENT_HALSPEC_ONLY)) { pParentObj = dynamicCast(pParent, Object); @@ -344,11 +359,17 @@ if (status != NV_OK) goto __nvoc_objCreate_ComputeInstanceSubscription_cleanup; *ppThis = pThis; + return NV_OK; __nvoc_objCreate_ComputeInstanceSubscription_cleanup: // do not call destructors here since the constructor already called them - portMemFree(pThis); + if (createFlags & NVOC_OBJ_CREATE_FLAGS_IN_PLACE_CONSTRUCT) + portMemSet(pThis, 0, sizeof(ComputeInstanceSubscription)); + else + portMemFree(pThis); + + // coverity[leaked_storage:FALSE] return status; } diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/generated/g_compute_instance_subscription_nvoc.h nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_compute_instance_subscription_nvoc.h --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/generated/g_compute_instance_subscription_nvoc.h 2023-10-25 20:26:53.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_compute_instance_subscription_nvoc.h 2024-03-05 22:18:08.000000000 +0000 @@ -7,7 +7,7 @@ #endif /* - * SPDX-FileCopyrightText: Copyright (c) 2019-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2019-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -67,29 +67,31 @@ NvBool (*__cisubscriptionCanCopy__)(struct ComputeInstanceSubscription *); NV_STATUS (*__cisubscriptionCtrlCmdGetUuid__)(struct ComputeInstanceSubscription *, NVC638_CTRL_GET_UUID_PARAMS *); NvBool (*__cisubscriptionShareCallback__)(struct ComputeInstanceSubscription *, struct RsClient *, struct RsResourceRef *, RS_SHARE_POLICY *); - NV_STATUS (*__cisubscriptionControl__)(struct ComputeInstanceSubscription *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); - NV_STATUS (*__cisubscriptionUnmap__)(struct ComputeInstanceSubscription *, struct CALL_CONTEXT *, struct RsCpuMapping *); - NV_STATUS (*__cisubscriptionGetMemInterMapParams__)(struct ComputeInstanceSubscription *, RMRES_MEM_INTER_MAP_PARAMS *); - NV_STATUS (*__cisubscriptionGetMemoryMappingDescriptor__)(struct ComputeInstanceSubscription *, struct MEMORY_DESCRIPTOR **); - NV_STATUS (*__cisubscriptionGetMapAddrSpace__)(struct ComputeInstanceSubscription *, struct CALL_CONTEXT *, NvU32, NV_ADDRESS_SPACE *); - NvHandle (*__cisubscriptionGetInternalObjectHandle__)(struct ComputeInstanceSubscription *); - NV_STATUS (*__cisubscriptionControlFilter__)(struct ComputeInstanceSubscription *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); - void (*__cisubscriptionAddAdditionalDependants__)(struct RsClient *, struct ComputeInstanceSubscription *, RsResourceRef *); - NvU32 (*__cisubscriptionGetRefCount__)(struct ComputeInstanceSubscription *); NV_STATUS (*__cisubscriptionCheckMemInterUnmap__)(struct ComputeInstanceSubscription *, NvBool); NV_STATUS (*__cisubscriptionMapTo__)(struct ComputeInstanceSubscription *, RS_RES_MAP_TO_PARAMS *); + NV_STATUS (*__cisubscriptionGetMapAddrSpace__)(struct ComputeInstanceSubscription *, struct CALL_CONTEXT *, NvU32, NV_ADDRESS_SPACE *); + NvU32 (*__cisubscriptionGetRefCount__)(struct ComputeInstanceSubscription *); + void (*__cisubscriptionAddAdditionalDependants__)(struct RsClient *, struct ComputeInstanceSubscription *, RsResourceRef *); NV_STATUS (*__cisubscriptionControl_Prologue__)(struct ComputeInstanceSubscription *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); NV_STATUS (*__cisubscriptionGetRegBaseOffsetAndSize__)(struct ComputeInstanceSubscription *, struct OBJGPU *, NvU32 *, NvU32 *); NV_STATUS (*__cisubscriptionInternalControlForward__)(struct ComputeInstanceSubscription *, NvU32, void *, NvU32); - void (*__cisubscriptionPreDestruct__)(struct ComputeInstanceSubscription *); NV_STATUS (*__cisubscriptionUnmapFrom__)(struct ComputeInstanceSubscription *, RS_RES_UNMAP_FROM_PARAMS *); - NV_STATUS (*__cisubscriptionIsDuplicate__)(struct ComputeInstanceSubscription *, NvHandle, NvBool *); void (*__cisubscriptionControl_Epilogue__)(struct ComputeInstanceSubscription *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); NV_STATUS (*__cisubscriptionControlLookup__)(struct ComputeInstanceSubscription *, struct RS_RES_CONTROL_PARAMS_INTERNAL *, const struct NVOC_EXPORTED_METHOD_DEF **); + NvHandle (*__cisubscriptionGetInternalObjectHandle__)(struct ComputeInstanceSubscription *); + NV_STATUS (*__cisubscriptionControl__)(struct ComputeInstanceSubscription *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); + NV_STATUS (*__cisubscriptionUnmap__)(struct ComputeInstanceSubscription *, struct CALL_CONTEXT *, struct RsCpuMapping *); + NV_STATUS (*__cisubscriptionGetMemInterMapParams__)(struct ComputeInstanceSubscription *, RMRES_MEM_INTER_MAP_PARAMS *); + NV_STATUS (*__cisubscriptionGetMemoryMappingDescriptor__)(struct ComputeInstanceSubscription *, struct MEMORY_DESCRIPTOR **); + NV_STATUS (*__cisubscriptionControlFilter__)(struct ComputeInstanceSubscription *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); + NV_STATUS (*__cisubscriptionControlSerialization_Prologue__)(struct ComputeInstanceSubscription *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); + void (*__cisubscriptionPreDestruct__)(struct ComputeInstanceSubscription *); + NV_STATUS (*__cisubscriptionIsDuplicate__)(struct ComputeInstanceSubscription *, NvHandle, NvBool *); + void (*__cisubscriptionControlSerialization_Epilogue__)(struct ComputeInstanceSubscription *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); NV_STATUS (*__cisubscriptionMap__)(struct ComputeInstanceSubscription *, struct CALL_CONTEXT *, struct RS_CPU_MAP_PARAMS *, struct RsCpuMapping *); NvBool (*__cisubscriptionAccessCallback__)(struct ComputeInstanceSubscription *, struct RsClient *, void *, RsAccessRight); - MIG_COMPUTE_INSTANCE *pMIGComputeInstance; - NvU64 dupedCapDescriptor; + MIG_COMPUTE_INSTANCE *PRIVATE_FIELD(pMIGComputeInstance); + NvU64 PRIVATE_FIELD(dupedCapDescriptor); }; #ifndef __NVOC_CLASS_ComputeInstanceSubscription_TYPEDEF__ @@ -123,25 +125,27 @@ #define cisubscriptionCanCopy(arg0) cisubscriptionCanCopy_DISPATCH(arg0) #define cisubscriptionCtrlCmdGetUuid(arg0, arg1) cisubscriptionCtrlCmdGetUuid_DISPATCH(arg0, arg1) #define cisubscriptionShareCallback(pGpuResource, pInvokingClient, pParentRef, pSharePolicy) cisubscriptionShareCallback_DISPATCH(pGpuResource, pInvokingClient, pParentRef, pSharePolicy) -#define cisubscriptionControl(pGpuResource, pCallContext, pParams) cisubscriptionControl_DISPATCH(pGpuResource, pCallContext, pParams) -#define cisubscriptionUnmap(pGpuResource, pCallContext, pCpuMapping) cisubscriptionUnmap_DISPATCH(pGpuResource, pCallContext, pCpuMapping) -#define cisubscriptionGetMemInterMapParams(pRmResource, pParams) cisubscriptionGetMemInterMapParams_DISPATCH(pRmResource, pParams) -#define cisubscriptionGetMemoryMappingDescriptor(pRmResource, ppMemDesc) cisubscriptionGetMemoryMappingDescriptor_DISPATCH(pRmResource, ppMemDesc) -#define cisubscriptionGetMapAddrSpace(pGpuResource, pCallContext, mapFlags, pAddrSpace) cisubscriptionGetMapAddrSpace_DISPATCH(pGpuResource, pCallContext, mapFlags, pAddrSpace) -#define cisubscriptionGetInternalObjectHandle(pGpuResource) cisubscriptionGetInternalObjectHandle_DISPATCH(pGpuResource) -#define cisubscriptionControlFilter(pResource, pCallContext, pParams) cisubscriptionControlFilter_DISPATCH(pResource, pCallContext, pParams) -#define cisubscriptionAddAdditionalDependants(pClient, pResource, pReference) cisubscriptionAddAdditionalDependants_DISPATCH(pClient, pResource, pReference) -#define cisubscriptionGetRefCount(pResource) cisubscriptionGetRefCount_DISPATCH(pResource) #define cisubscriptionCheckMemInterUnmap(pRmResource, bSubdeviceHandleProvided) cisubscriptionCheckMemInterUnmap_DISPATCH(pRmResource, bSubdeviceHandleProvided) #define cisubscriptionMapTo(pResource, pParams) cisubscriptionMapTo_DISPATCH(pResource, pParams) +#define cisubscriptionGetMapAddrSpace(pGpuResource, pCallContext, mapFlags, pAddrSpace) cisubscriptionGetMapAddrSpace_DISPATCH(pGpuResource, pCallContext, mapFlags, pAddrSpace) +#define cisubscriptionGetRefCount(pResource) cisubscriptionGetRefCount_DISPATCH(pResource) +#define cisubscriptionAddAdditionalDependants(pClient, pResource, pReference) cisubscriptionAddAdditionalDependants_DISPATCH(pClient, pResource, pReference) #define cisubscriptionControl_Prologue(pResource, pCallContext, pParams) cisubscriptionControl_Prologue_DISPATCH(pResource, pCallContext, pParams) #define cisubscriptionGetRegBaseOffsetAndSize(pGpuResource, pGpu, pOffset, pSize) cisubscriptionGetRegBaseOffsetAndSize_DISPATCH(pGpuResource, pGpu, pOffset, pSize) #define cisubscriptionInternalControlForward(pGpuResource, command, pParams, size) cisubscriptionInternalControlForward_DISPATCH(pGpuResource, command, pParams, size) -#define cisubscriptionPreDestruct(pResource) cisubscriptionPreDestruct_DISPATCH(pResource) #define cisubscriptionUnmapFrom(pResource, pParams) cisubscriptionUnmapFrom_DISPATCH(pResource, pParams) -#define cisubscriptionIsDuplicate(pResource, hMemory, pDuplicate) cisubscriptionIsDuplicate_DISPATCH(pResource, hMemory, pDuplicate) #define cisubscriptionControl_Epilogue(pResource, pCallContext, pParams) cisubscriptionControl_Epilogue_DISPATCH(pResource, pCallContext, pParams) #define cisubscriptionControlLookup(pResource, pParams, ppEntry) cisubscriptionControlLookup_DISPATCH(pResource, pParams, ppEntry) +#define cisubscriptionGetInternalObjectHandle(pGpuResource) cisubscriptionGetInternalObjectHandle_DISPATCH(pGpuResource) +#define cisubscriptionControl(pGpuResource, pCallContext, pParams) cisubscriptionControl_DISPATCH(pGpuResource, pCallContext, pParams) +#define cisubscriptionUnmap(pGpuResource, pCallContext, pCpuMapping) cisubscriptionUnmap_DISPATCH(pGpuResource, pCallContext, pCpuMapping) +#define cisubscriptionGetMemInterMapParams(pRmResource, pParams) cisubscriptionGetMemInterMapParams_DISPATCH(pRmResource, pParams) +#define cisubscriptionGetMemoryMappingDescriptor(pRmResource, ppMemDesc) cisubscriptionGetMemoryMappingDescriptor_DISPATCH(pRmResource, ppMemDesc) +#define cisubscriptionControlFilter(pResource, pCallContext, pParams) cisubscriptionControlFilter_DISPATCH(pResource, pCallContext, pParams) +#define cisubscriptionControlSerialization_Prologue(pResource, pCallContext, pParams) cisubscriptionControlSerialization_Prologue_DISPATCH(pResource, pCallContext, pParams) +#define cisubscriptionPreDestruct(pResource) cisubscriptionPreDestruct_DISPATCH(pResource) +#define cisubscriptionIsDuplicate(pResource, hMemory, pDuplicate) cisubscriptionIsDuplicate_DISPATCH(pResource, hMemory, pDuplicate) +#define cisubscriptionControlSerialization_Epilogue(pResource, pCallContext, pParams) cisubscriptionControlSerialization_Epilogue_DISPATCH(pResource, pCallContext, pParams) #define cisubscriptionMap(pGpuResource, pCallContext, pParams, pCpuMapping) cisubscriptionMap_DISPATCH(pGpuResource, pCallContext, pParams, pCpuMapping) #define cisubscriptionAccessCallback(pResource, pInvokingClient, pAllocParams, accessRight) cisubscriptionAccessCallback_DISPATCH(pResource, pInvokingClient, pAllocParams, accessRight) NvBool cisubscriptionCanCopy_IMPL(struct ComputeInstanceSubscription *arg0); @@ -160,48 +164,24 @@ return pGpuResource->__cisubscriptionShareCallback__(pGpuResource, pInvokingClient, pParentRef, pSharePolicy); } -static inline NV_STATUS cisubscriptionControl_DISPATCH(struct ComputeInstanceSubscription *pGpuResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { - return pGpuResource->__cisubscriptionControl__(pGpuResource, pCallContext, pParams); -} - -static inline NV_STATUS cisubscriptionUnmap_DISPATCH(struct ComputeInstanceSubscription *pGpuResource, struct CALL_CONTEXT *pCallContext, struct RsCpuMapping *pCpuMapping) { - return pGpuResource->__cisubscriptionUnmap__(pGpuResource, pCallContext, pCpuMapping); -} - -static inline NV_STATUS cisubscriptionGetMemInterMapParams_DISPATCH(struct ComputeInstanceSubscription *pRmResource, RMRES_MEM_INTER_MAP_PARAMS *pParams) { - return pRmResource->__cisubscriptionGetMemInterMapParams__(pRmResource, pParams); +static inline NV_STATUS cisubscriptionCheckMemInterUnmap_DISPATCH(struct ComputeInstanceSubscription *pRmResource, NvBool bSubdeviceHandleProvided) { + return pRmResource->__cisubscriptionCheckMemInterUnmap__(pRmResource, bSubdeviceHandleProvided); } -static inline NV_STATUS cisubscriptionGetMemoryMappingDescriptor_DISPATCH(struct ComputeInstanceSubscription *pRmResource, struct MEMORY_DESCRIPTOR **ppMemDesc) { - return pRmResource->__cisubscriptionGetMemoryMappingDescriptor__(pRmResource, ppMemDesc); +static inline NV_STATUS cisubscriptionMapTo_DISPATCH(struct ComputeInstanceSubscription *pResource, RS_RES_MAP_TO_PARAMS *pParams) { + return pResource->__cisubscriptionMapTo__(pResource, pParams); } static inline NV_STATUS cisubscriptionGetMapAddrSpace_DISPATCH(struct ComputeInstanceSubscription *pGpuResource, struct CALL_CONTEXT *pCallContext, NvU32 mapFlags, NV_ADDRESS_SPACE *pAddrSpace) { return pGpuResource->__cisubscriptionGetMapAddrSpace__(pGpuResource, pCallContext, mapFlags, pAddrSpace); } -static inline NvHandle cisubscriptionGetInternalObjectHandle_DISPATCH(struct ComputeInstanceSubscription *pGpuResource) { - return pGpuResource->__cisubscriptionGetInternalObjectHandle__(pGpuResource); -} - -static inline NV_STATUS cisubscriptionControlFilter_DISPATCH(struct ComputeInstanceSubscription *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { - return pResource->__cisubscriptionControlFilter__(pResource, pCallContext, pParams); -} - -static inline void cisubscriptionAddAdditionalDependants_DISPATCH(struct RsClient *pClient, struct ComputeInstanceSubscription *pResource, RsResourceRef *pReference) { - pResource->__cisubscriptionAddAdditionalDependants__(pClient, pResource, pReference); -} - static inline NvU32 cisubscriptionGetRefCount_DISPATCH(struct ComputeInstanceSubscription *pResource) { return pResource->__cisubscriptionGetRefCount__(pResource); } -static inline NV_STATUS cisubscriptionCheckMemInterUnmap_DISPATCH(struct ComputeInstanceSubscription *pRmResource, NvBool bSubdeviceHandleProvided) { - return pRmResource->__cisubscriptionCheckMemInterUnmap__(pRmResource, bSubdeviceHandleProvided); -} - -static inline NV_STATUS cisubscriptionMapTo_DISPATCH(struct ComputeInstanceSubscription *pResource, RS_RES_MAP_TO_PARAMS *pParams) { - return pResource->__cisubscriptionMapTo__(pResource, pParams); +static inline void cisubscriptionAddAdditionalDependants_DISPATCH(struct RsClient *pClient, struct ComputeInstanceSubscription *pResource, RsResourceRef *pReference) { + pResource->__cisubscriptionAddAdditionalDependants__(pClient, pResource, pReference); } static inline NV_STATUS cisubscriptionControl_Prologue_DISPATCH(struct ComputeInstanceSubscription *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { @@ -216,18 +196,10 @@ return pGpuResource->__cisubscriptionInternalControlForward__(pGpuResource, command, pParams, size); } -static inline void cisubscriptionPreDestruct_DISPATCH(struct ComputeInstanceSubscription *pResource) { - pResource->__cisubscriptionPreDestruct__(pResource); -} - static inline NV_STATUS cisubscriptionUnmapFrom_DISPATCH(struct ComputeInstanceSubscription *pResource, RS_RES_UNMAP_FROM_PARAMS *pParams) { return pResource->__cisubscriptionUnmapFrom__(pResource, pParams); } -static inline NV_STATUS cisubscriptionIsDuplicate_DISPATCH(struct ComputeInstanceSubscription *pResource, NvHandle hMemory, NvBool *pDuplicate) { - return pResource->__cisubscriptionIsDuplicate__(pResource, hMemory, pDuplicate); -} - static inline void cisubscriptionControl_Epilogue_DISPATCH(struct ComputeInstanceSubscription *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { pResource->__cisubscriptionControl_Epilogue__(pResource, pCallContext, pParams); } @@ -236,6 +208,46 @@ return pResource->__cisubscriptionControlLookup__(pResource, pParams, ppEntry); } +static inline NvHandle cisubscriptionGetInternalObjectHandle_DISPATCH(struct ComputeInstanceSubscription *pGpuResource) { + return pGpuResource->__cisubscriptionGetInternalObjectHandle__(pGpuResource); +} + +static inline NV_STATUS cisubscriptionControl_DISPATCH(struct ComputeInstanceSubscription *pGpuResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return pGpuResource->__cisubscriptionControl__(pGpuResource, pCallContext, pParams); +} + +static inline NV_STATUS cisubscriptionUnmap_DISPATCH(struct ComputeInstanceSubscription *pGpuResource, struct CALL_CONTEXT *pCallContext, struct RsCpuMapping *pCpuMapping) { + return pGpuResource->__cisubscriptionUnmap__(pGpuResource, pCallContext, pCpuMapping); +} + +static inline NV_STATUS cisubscriptionGetMemInterMapParams_DISPATCH(struct ComputeInstanceSubscription *pRmResource, RMRES_MEM_INTER_MAP_PARAMS *pParams) { + return pRmResource->__cisubscriptionGetMemInterMapParams__(pRmResource, pParams); +} + +static inline NV_STATUS cisubscriptionGetMemoryMappingDescriptor_DISPATCH(struct ComputeInstanceSubscription *pRmResource, struct MEMORY_DESCRIPTOR **ppMemDesc) { + return pRmResource->__cisubscriptionGetMemoryMappingDescriptor__(pRmResource, ppMemDesc); +} + +static inline NV_STATUS cisubscriptionControlFilter_DISPATCH(struct ComputeInstanceSubscription *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return pResource->__cisubscriptionControlFilter__(pResource, pCallContext, pParams); +} + +static inline NV_STATUS cisubscriptionControlSerialization_Prologue_DISPATCH(struct ComputeInstanceSubscription *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return pResource->__cisubscriptionControlSerialization_Prologue__(pResource, pCallContext, pParams); +} + +static inline void cisubscriptionPreDestruct_DISPATCH(struct ComputeInstanceSubscription *pResource) { + pResource->__cisubscriptionPreDestruct__(pResource); +} + +static inline NV_STATUS cisubscriptionIsDuplicate_DISPATCH(struct ComputeInstanceSubscription *pResource, NvHandle hMemory, NvBool *pDuplicate) { + return pResource->__cisubscriptionIsDuplicate__(pResource, hMemory, pDuplicate); +} + +static inline void cisubscriptionControlSerialization_Epilogue_DISPATCH(struct ComputeInstanceSubscription *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + pResource->__cisubscriptionControlSerialization_Epilogue__(pResource, pCallContext, pParams); +} + static inline NV_STATUS cisubscriptionMap_DISPATCH(struct ComputeInstanceSubscription *pGpuResource, struct CALL_CONTEXT *pCallContext, struct RS_CPU_MAP_PARAMS *pParams, struct RsCpuMapping *pCpuMapping) { return pGpuResource->__cisubscriptionMap__(pGpuResource, pCallContext, pParams, pCpuMapping); } diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/generated/g_conf_compute_api_nvoc.c nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_conf_compute_api_nvoc.c --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/generated/g_conf_compute_api_nvoc.c 1970-01-01 00:00:00.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_conf_compute_api_nvoc.c 2024-03-05 22:18:08.000000000 +0000 @@ -0,0 +1,482 @@ +#define NVOC_CONF_COMPUTE_API_H_PRIVATE_ACCESS_ALLOWED +#include "nvoc/runtime.h" +#include "nvoc/rtti.h" +#include "nvtypes.h" +#include "nvport/nvport.h" +#include "nvport/inline/util_valist.h" +#include "utils/nvassert.h" +#include "g_conf_compute_api_nvoc.h" + +#ifdef DEBUG +char __nvoc_class_id_uniqueness_check_0xea5cb0 = 1; +#endif + +extern const struct NVOC_CLASS_DEF __nvoc_class_def_ConfidentialComputeApi; + +extern const struct NVOC_CLASS_DEF __nvoc_class_def_Object; + +extern const struct NVOC_CLASS_DEF __nvoc_class_def_RsResource; + +extern const struct NVOC_CLASS_DEF __nvoc_class_def_RmResourceCommon; + +extern const struct NVOC_CLASS_DEF __nvoc_class_def_RmResource; + +void __nvoc_init_ConfidentialComputeApi(ConfidentialComputeApi*); +void __nvoc_init_funcTable_ConfidentialComputeApi(ConfidentialComputeApi*); +NV_STATUS __nvoc_ctor_ConfidentialComputeApi(ConfidentialComputeApi*, CALL_CONTEXT * arg_pCallContext, struct RS_RES_ALLOC_PARAMS_INTERNAL * arg_pParams); +void __nvoc_init_dataField_ConfidentialComputeApi(ConfidentialComputeApi*); +void __nvoc_dtor_ConfidentialComputeApi(ConfidentialComputeApi*); +extern const struct NVOC_EXPORT_INFO __nvoc_export_info_ConfidentialComputeApi; + +static const struct NVOC_RTTI __nvoc_rtti_ConfidentialComputeApi_ConfidentialComputeApi = { + /*pClassDef=*/ &__nvoc_class_def_ConfidentialComputeApi, + /*dtor=*/ (NVOC_DYNAMIC_DTOR) &__nvoc_dtor_ConfidentialComputeApi, + /*offset=*/ 0, +}; + +static const struct NVOC_RTTI __nvoc_rtti_ConfidentialComputeApi_Object = { + /*pClassDef=*/ &__nvoc_class_def_Object, + /*dtor=*/ &__nvoc_destructFromBase, + /*offset=*/ NV_OFFSETOF(ConfidentialComputeApi, __nvoc_base_RmResource.__nvoc_base_RsResource.__nvoc_base_Object), +}; + +static const struct NVOC_RTTI __nvoc_rtti_ConfidentialComputeApi_RsResource = { + /*pClassDef=*/ &__nvoc_class_def_RsResource, + /*dtor=*/ &__nvoc_destructFromBase, + /*offset=*/ NV_OFFSETOF(ConfidentialComputeApi, __nvoc_base_RmResource.__nvoc_base_RsResource), +}; + +static const struct NVOC_RTTI __nvoc_rtti_ConfidentialComputeApi_RmResourceCommon = { + /*pClassDef=*/ &__nvoc_class_def_RmResourceCommon, + /*dtor=*/ &__nvoc_destructFromBase, + /*offset=*/ NV_OFFSETOF(ConfidentialComputeApi, __nvoc_base_RmResource.__nvoc_base_RmResourceCommon), +}; + +static const struct NVOC_RTTI __nvoc_rtti_ConfidentialComputeApi_RmResource = { + /*pClassDef=*/ &__nvoc_class_def_RmResource, + /*dtor=*/ &__nvoc_destructFromBase, + /*offset=*/ NV_OFFSETOF(ConfidentialComputeApi, __nvoc_base_RmResource), +}; + +static const struct NVOC_CASTINFO __nvoc_castinfo_ConfidentialComputeApi = { + /*numRelatives=*/ 5, + /*relatives=*/ { + &__nvoc_rtti_ConfidentialComputeApi_ConfidentialComputeApi, + &__nvoc_rtti_ConfidentialComputeApi_RmResource, + &__nvoc_rtti_ConfidentialComputeApi_RmResourceCommon, + &__nvoc_rtti_ConfidentialComputeApi_RsResource, + &__nvoc_rtti_ConfidentialComputeApi_Object, + }, +}; + +const struct NVOC_CLASS_DEF __nvoc_class_def_ConfidentialComputeApi = +{ + /*classInfo=*/ { + /*size=*/ sizeof(ConfidentialComputeApi), + /*classId=*/ classId(ConfidentialComputeApi), + /*providerId=*/ &__nvoc_rtti_provider, +#if NV_PRINTF_STRINGS_ALLOWED + /*name=*/ "ConfidentialComputeApi", +#endif + }, + /*objCreatefn=*/ (NVOC_DYNAMIC_OBJ_CREATE) &__nvoc_objCreateDynamic_ConfidentialComputeApi, + /*pCastInfo=*/ &__nvoc_castinfo_ConfidentialComputeApi, + /*pExportInfo=*/ &__nvoc_export_info_ConfidentialComputeApi +}; + +static NvBool __nvoc_thunk_RmResource_confComputeApiShareCallback(struct ConfidentialComputeApi *pResource, struct RsClient *pInvokingClient, struct RsResourceRef *pParentRef, RS_SHARE_POLICY *pSharePolicy) { + return rmresShareCallback((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_ConfidentialComputeApi_RmResource.offset), pInvokingClient, pParentRef, pSharePolicy); +} + +static NV_STATUS __nvoc_thunk_RmResource_confComputeApiCheckMemInterUnmap(struct ConfidentialComputeApi *pRmResource, NvBool bSubdeviceHandleProvided) { + return rmresCheckMemInterUnmap((struct RmResource *)(((unsigned char *)pRmResource) + __nvoc_rtti_ConfidentialComputeApi_RmResource.offset), bSubdeviceHandleProvided); +} + +static NV_STATUS __nvoc_thunk_RsResource_confComputeApiControl(struct ConfidentialComputeApi *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return resControl((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_ConfidentialComputeApi_RsResource.offset), pCallContext, pParams); +} + +static NV_STATUS __nvoc_thunk_RmResource_confComputeApiGetMemInterMapParams(struct ConfidentialComputeApi *pRmResource, RMRES_MEM_INTER_MAP_PARAMS *pParams) { + return rmresGetMemInterMapParams((struct RmResource *)(((unsigned char *)pRmResource) + __nvoc_rtti_ConfidentialComputeApi_RmResource.offset), pParams); +} + +static NV_STATUS __nvoc_thunk_RmResource_confComputeApiGetMemoryMappingDescriptor(struct ConfidentialComputeApi *pRmResource, struct MEMORY_DESCRIPTOR **ppMemDesc) { + return rmresGetMemoryMappingDescriptor((struct RmResource *)(((unsigned char *)pRmResource) + __nvoc_rtti_ConfidentialComputeApi_RmResource.offset), ppMemDesc); +} + +static NvU32 __nvoc_thunk_RsResource_confComputeApiGetRefCount(struct ConfidentialComputeApi *pResource) { + return resGetRefCount((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_ConfidentialComputeApi_RsResource.offset)); +} + +static NV_STATUS __nvoc_thunk_RsResource_confComputeApiControlFilter(struct ConfidentialComputeApi *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return resControlFilter((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_ConfidentialComputeApi_RsResource.offset), pCallContext, pParams); +} + +static void __nvoc_thunk_RsResource_confComputeApiAddAdditionalDependants(struct RsClient *pClient, struct ConfidentialComputeApi *pResource, RsResourceRef *pReference) { + resAddAdditionalDependants(pClient, (struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_ConfidentialComputeApi_RsResource.offset), pReference); +} + +static NV_STATUS __nvoc_thunk_RsResource_confComputeApiUnmapFrom(struct ConfidentialComputeApi *pResource, RS_RES_UNMAP_FROM_PARAMS *pParams) { + return resUnmapFrom((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_ConfidentialComputeApi_RsResource.offset), pParams); +} + +static NV_STATUS __nvoc_thunk_RmResource_confComputeApiControlSerialization_Prologue(struct ConfidentialComputeApi *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return rmresControlSerialization_Prologue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_ConfidentialComputeApi_RmResource.offset), pCallContext, pParams); +} + +static NV_STATUS __nvoc_thunk_RmResource_confComputeApiControl_Prologue(struct ConfidentialComputeApi *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return rmresControl_Prologue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_ConfidentialComputeApi_RmResource.offset), pCallContext, pParams); +} + +static NvBool __nvoc_thunk_RsResource_confComputeApiCanCopy(struct ConfidentialComputeApi *pResource) { + return resCanCopy((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_ConfidentialComputeApi_RsResource.offset)); +} + +static NV_STATUS __nvoc_thunk_RsResource_confComputeApiUnmap(struct ConfidentialComputeApi *pResource, struct CALL_CONTEXT *pCallContext, RsCpuMapping *pCpuMapping) { + return resUnmap((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_ConfidentialComputeApi_RsResource.offset), pCallContext, pCpuMapping); +} + +static void __nvoc_thunk_RsResource_confComputeApiPreDestruct(struct ConfidentialComputeApi *pResource) { + resPreDestruct((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_ConfidentialComputeApi_RsResource.offset)); +} + +static NV_STATUS __nvoc_thunk_RsResource_confComputeApiMapTo(struct ConfidentialComputeApi *pResource, RS_RES_MAP_TO_PARAMS *pParams) { + return resMapTo((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_ConfidentialComputeApi_RsResource.offset), pParams); +} + +static NV_STATUS __nvoc_thunk_RsResource_confComputeApiIsDuplicate(struct ConfidentialComputeApi *pResource, NvHandle hMemory, NvBool *pDuplicate) { + return resIsDuplicate((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_ConfidentialComputeApi_RsResource.offset), hMemory, pDuplicate); +} + +static void __nvoc_thunk_RmResource_confComputeApiControlSerialization_Epilogue(struct ConfidentialComputeApi *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + rmresControlSerialization_Epilogue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_ConfidentialComputeApi_RmResource.offset), pCallContext, pParams); +} + +static void __nvoc_thunk_RmResource_confComputeApiControl_Epilogue(struct ConfidentialComputeApi *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + rmresControl_Epilogue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_ConfidentialComputeApi_RmResource.offset), pCallContext, pParams); +} + +static NV_STATUS __nvoc_thunk_RsResource_confComputeApiControlLookup(struct ConfidentialComputeApi *pResource, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams, const struct NVOC_EXPORTED_METHOD_DEF **ppEntry) { + return resControlLookup((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_ConfidentialComputeApi_RsResource.offset), pParams, ppEntry); +} + +static NV_STATUS __nvoc_thunk_RsResource_confComputeApiMap(struct ConfidentialComputeApi *pResource, struct CALL_CONTEXT *pCallContext, RS_CPU_MAP_PARAMS *pParams, RsCpuMapping *pCpuMapping) { + return resMap((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_ConfidentialComputeApi_RsResource.offset), pCallContext, pParams, pCpuMapping); +} + +static NvBool __nvoc_thunk_RmResource_confComputeApiAccessCallback(struct ConfidentialComputeApi *pResource, struct RsClient *pInvokingClient, void *pAllocParams, RsAccessRight accessRight) { + return rmresAccessCallback((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_ConfidentialComputeApi_RmResource.offset), pInvokingClient, pAllocParams, accessRight); +} + +#if !defined(NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG) +#define NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(x) (0) +#endif + +static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_ConfidentialComputeApi[] = +{ + { /* [0] */ +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) + /*pFunc=*/ (void (*)(void)) NULL, +#else + /*pFunc=*/ (void (*)(void)) confComputeApiCtrlCmdSystemGetCapabilities_IMPL, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) + /*flags=*/ 0x10u, + /*accessRight=*/0x0u, + /*methodId=*/ 0xcb330101u, + /*paramSize=*/ sizeof(NV_CONF_COMPUTE_CTRL_CMD_SYSTEM_GET_CAPABILITIES_PARAMS), + /*pClassInfo=*/ &(__nvoc_class_def_ConfidentialComputeApi.classInfo), +#if NV_PRINTF_STRINGS_ALLOWED + /*func=*/ "confComputeApiCtrlCmdSystemGetCapabilities" +#endif + }, + { /* [1] */ +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) + /*pFunc=*/ (void (*)(void)) NULL, +#else + /*pFunc=*/ (void (*)(void)) confComputeApiCtrlCmdSystemGetGpusState_IMPL, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) + /*flags=*/ 0x10u, + /*accessRight=*/0x0u, + /*methodId=*/ 0xcb330104u, + /*paramSize=*/ sizeof(NV_CONF_COMPUTE_CTRL_CMD_SYSTEM_GET_GPUS_STATE_PARAMS), + /*pClassInfo=*/ &(__nvoc_class_def_ConfidentialComputeApi.classInfo), +#if NV_PRINTF_STRINGS_ALLOWED + /*func=*/ "confComputeApiCtrlCmdSystemGetGpusState" +#endif + }, + { /* [2] */ +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x4u) + /*pFunc=*/ (void (*)(void)) NULL, +#else + /*pFunc=*/ (void (*)(void)) confComputeApiCtrlCmdSystemSetGpusState_IMPL, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x4u) + /*flags=*/ 0x4u, + /*accessRight=*/0x0u, + /*methodId=*/ 0xcb330105u, + /*paramSize=*/ sizeof(NV_CONF_COMPUTE_CTRL_CMD_SYSTEM_SET_GPUS_STATE_PARAMS), + /*pClassInfo=*/ &(__nvoc_class_def_ConfidentialComputeApi.classInfo), +#if NV_PRINTF_STRINGS_ALLOWED + /*func=*/ "confComputeApiCtrlCmdSystemSetGpusState" +#endif + }, + { /* [3] */ +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) + /*pFunc=*/ (void (*)(void)) NULL, +#else + /*pFunc=*/ (void (*)(void)) confComputeApiCtrlCmdGpuGetVidmemSize_IMPL, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) + /*flags=*/ 0x10u, + /*accessRight=*/0x0u, + /*methodId=*/ 0xcb330106u, + /*paramSize=*/ sizeof(NV_CONF_COMPUTE_CTRL_CMD_GPU_GET_VIDMEM_SIZE_PARAMS), + /*pClassInfo=*/ &(__nvoc_class_def_ConfidentialComputeApi.classInfo), +#if NV_PRINTF_STRINGS_ALLOWED + /*func=*/ "confComputeApiCtrlCmdGpuGetVidmemSize" +#endif + }, + { /* [4] */ +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x4u) + /*pFunc=*/ (void (*)(void)) NULL, +#else + /*pFunc=*/ (void (*)(void)) confComputeApiCtrlCmdGpuSetVidmemSize_IMPL, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x4u) + /*flags=*/ 0x4u, + /*accessRight=*/0x0u, + /*methodId=*/ 0xcb330107u, + /*paramSize=*/ sizeof(NV_CONF_COMPUTE_CTRL_CMD_GPU_SET_VIDMEM_SIZE_PARAMS), + /*pClassInfo=*/ &(__nvoc_class_def_ConfidentialComputeApi.classInfo), +#if NV_PRINTF_STRINGS_ALLOWED + /*func=*/ "confComputeApiCtrlCmdGpuSetVidmemSize" +#endif + }, + { /* [5] */ +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) + /*pFunc=*/ (void (*)(void)) NULL, +#else + /*pFunc=*/ (void (*)(void)) confComputeApiCtrlCmdGetGpuCertificate_IMPL, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) + /*flags=*/ 0x10u, + /*accessRight=*/0x0u, + /*methodId=*/ 0xcb330109u, + /*paramSize=*/ sizeof(NV_CONF_COMPUTE_CTRL_CMD_GET_GPU_CERTIFICATE_PARAMS), + /*pClassInfo=*/ &(__nvoc_class_def_ConfidentialComputeApi.classInfo), +#if NV_PRINTF_STRINGS_ALLOWED + /*func=*/ "confComputeApiCtrlCmdGetGpuCertificate" +#endif + }, + { /* [6] */ +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) + /*pFunc=*/ (void (*)(void)) NULL, +#else + /*pFunc=*/ (void (*)(void)) confComputeApiCtrlCmdGetGpuAttestationReport_IMPL, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) + /*flags=*/ 0x10u, + /*accessRight=*/0x0u, + /*methodId=*/ 0xcb33010au, + /*paramSize=*/ sizeof(NV_CONF_COMPUTE_CTRL_CMD_GET_GPU_ATTESTATION_REPORT_PARAMS), + /*pClassInfo=*/ &(__nvoc_class_def_ConfidentialComputeApi.classInfo), +#if NV_PRINTF_STRINGS_ALLOWED + /*func=*/ "confComputeApiCtrlCmdGetGpuAttestationReport" +#endif + }, + { /* [7] */ +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) + /*pFunc=*/ (void (*)(void)) NULL, +#else + /*pFunc=*/ (void (*)(void)) confComputeApiCtrlCmdGpuGetNumSecureChannels_IMPL, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) + /*flags=*/ 0x10u, + /*accessRight=*/0x0u, + /*methodId=*/ 0xcb33010bu, + /*paramSize=*/ sizeof(NV_CONF_COMPUTE_CTRL_CMD_GPU_GET_NUM_SECURE_CHANNELS_PARAMS), + /*pClassInfo=*/ &(__nvoc_class_def_ConfidentialComputeApi.classInfo), +#if NV_PRINTF_STRINGS_ALLOWED + /*func=*/ "confComputeApiCtrlCmdGpuGetNumSecureChannels" +#endif + }, + +}; + +const struct NVOC_EXPORT_INFO __nvoc_export_info_ConfidentialComputeApi = +{ + /*numEntries=*/ 8, + /*pExportEntries=*/ __nvoc_exported_method_def_ConfidentialComputeApi +}; + +void __nvoc_dtor_RmResource(RmResource*); +void __nvoc_dtor_ConfidentialComputeApi(ConfidentialComputeApi *pThis) { + __nvoc_confComputeApiDestruct(pThis); + __nvoc_dtor_RmResource(&pThis->__nvoc_base_RmResource); + PORT_UNREFERENCED_VARIABLE(pThis); +} + +void __nvoc_init_dataField_ConfidentialComputeApi(ConfidentialComputeApi *pThis) { + PORT_UNREFERENCED_VARIABLE(pThis); +} + +NV_STATUS __nvoc_ctor_RmResource(RmResource* , CALL_CONTEXT *, struct RS_RES_ALLOC_PARAMS_INTERNAL *); +NV_STATUS __nvoc_ctor_ConfidentialComputeApi(ConfidentialComputeApi *pThis, CALL_CONTEXT * arg_pCallContext, struct RS_RES_ALLOC_PARAMS_INTERNAL * arg_pParams) { + NV_STATUS status = NV_OK; + status = __nvoc_ctor_RmResource(&pThis->__nvoc_base_RmResource, arg_pCallContext, arg_pParams); + if (status != NV_OK) goto __nvoc_ctor_ConfidentialComputeApi_fail_RmResource; + __nvoc_init_dataField_ConfidentialComputeApi(pThis); + + status = __nvoc_confComputeApiConstruct(pThis, arg_pCallContext, arg_pParams); + if (status != NV_OK) goto __nvoc_ctor_ConfidentialComputeApi_fail__init; + goto __nvoc_ctor_ConfidentialComputeApi_exit; // Success + +__nvoc_ctor_ConfidentialComputeApi_fail__init: + __nvoc_dtor_RmResource(&pThis->__nvoc_base_RmResource); +__nvoc_ctor_ConfidentialComputeApi_fail_RmResource: +__nvoc_ctor_ConfidentialComputeApi_exit: + + return status; +} + +static void __nvoc_init_funcTable_ConfidentialComputeApi_1(ConfidentialComputeApi *pThis) { + PORT_UNREFERENCED_VARIABLE(pThis); + +#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) + pThis->__confComputeApiCtrlCmdSystemGetCapabilities__ = &confComputeApiCtrlCmdSystemGetCapabilities_IMPL; +#endif + +#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) + pThis->__confComputeApiCtrlCmdSystemGetGpusState__ = &confComputeApiCtrlCmdSystemGetGpusState_IMPL; +#endif + +#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x4u) + pThis->__confComputeApiCtrlCmdSystemSetGpusState__ = &confComputeApiCtrlCmdSystemSetGpusState_IMPL; +#endif + +#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) + pThis->__confComputeApiCtrlCmdGpuGetVidmemSize__ = &confComputeApiCtrlCmdGpuGetVidmemSize_IMPL; +#endif + +#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x4u) + pThis->__confComputeApiCtrlCmdGpuSetVidmemSize__ = &confComputeApiCtrlCmdGpuSetVidmemSize_IMPL; +#endif + +#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) + pThis->__confComputeApiCtrlCmdGetGpuCertificate__ = &confComputeApiCtrlCmdGetGpuCertificate_IMPL; +#endif + +#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) + pThis->__confComputeApiCtrlCmdGetGpuAttestationReport__ = &confComputeApiCtrlCmdGetGpuAttestationReport_IMPL; +#endif + +#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) + pThis->__confComputeApiCtrlCmdGpuGetNumSecureChannels__ = &confComputeApiCtrlCmdGpuGetNumSecureChannels_IMPL; +#endif + + pThis->__confComputeApiShareCallback__ = &__nvoc_thunk_RmResource_confComputeApiShareCallback; + + pThis->__confComputeApiCheckMemInterUnmap__ = &__nvoc_thunk_RmResource_confComputeApiCheckMemInterUnmap; + + pThis->__confComputeApiControl__ = &__nvoc_thunk_RsResource_confComputeApiControl; + + pThis->__confComputeApiGetMemInterMapParams__ = &__nvoc_thunk_RmResource_confComputeApiGetMemInterMapParams; + + pThis->__confComputeApiGetMemoryMappingDescriptor__ = &__nvoc_thunk_RmResource_confComputeApiGetMemoryMappingDescriptor; + + pThis->__confComputeApiGetRefCount__ = &__nvoc_thunk_RsResource_confComputeApiGetRefCount; + + pThis->__confComputeApiControlFilter__ = &__nvoc_thunk_RsResource_confComputeApiControlFilter; + + pThis->__confComputeApiAddAdditionalDependants__ = &__nvoc_thunk_RsResource_confComputeApiAddAdditionalDependants; + + pThis->__confComputeApiUnmapFrom__ = &__nvoc_thunk_RsResource_confComputeApiUnmapFrom; + + pThis->__confComputeApiControlSerialization_Prologue__ = &__nvoc_thunk_RmResource_confComputeApiControlSerialization_Prologue; + + pThis->__confComputeApiControl_Prologue__ = &__nvoc_thunk_RmResource_confComputeApiControl_Prologue; + + pThis->__confComputeApiCanCopy__ = &__nvoc_thunk_RsResource_confComputeApiCanCopy; + + pThis->__confComputeApiUnmap__ = &__nvoc_thunk_RsResource_confComputeApiUnmap; + + pThis->__confComputeApiPreDestruct__ = &__nvoc_thunk_RsResource_confComputeApiPreDestruct; + + pThis->__confComputeApiMapTo__ = &__nvoc_thunk_RsResource_confComputeApiMapTo; + + pThis->__confComputeApiIsDuplicate__ = &__nvoc_thunk_RsResource_confComputeApiIsDuplicate; + + pThis->__confComputeApiControlSerialization_Epilogue__ = &__nvoc_thunk_RmResource_confComputeApiControlSerialization_Epilogue; + + pThis->__confComputeApiControl_Epilogue__ = &__nvoc_thunk_RmResource_confComputeApiControl_Epilogue; + + pThis->__confComputeApiControlLookup__ = &__nvoc_thunk_RsResource_confComputeApiControlLookup; + + pThis->__confComputeApiMap__ = &__nvoc_thunk_RsResource_confComputeApiMap; + + pThis->__confComputeApiAccessCallback__ = &__nvoc_thunk_RmResource_confComputeApiAccessCallback; +} + +void __nvoc_init_funcTable_ConfidentialComputeApi(ConfidentialComputeApi *pThis) { + __nvoc_init_funcTable_ConfidentialComputeApi_1(pThis); +} + +void __nvoc_init_RmResource(RmResource*); +void __nvoc_init_ConfidentialComputeApi(ConfidentialComputeApi *pThis) { + pThis->__nvoc_pbase_ConfidentialComputeApi = pThis; + pThis->__nvoc_pbase_Object = &pThis->__nvoc_base_RmResource.__nvoc_base_RsResource.__nvoc_base_Object; + pThis->__nvoc_pbase_RsResource = &pThis->__nvoc_base_RmResource.__nvoc_base_RsResource; + pThis->__nvoc_pbase_RmResourceCommon = &pThis->__nvoc_base_RmResource.__nvoc_base_RmResourceCommon; + pThis->__nvoc_pbase_RmResource = &pThis->__nvoc_base_RmResource; + __nvoc_init_RmResource(&pThis->__nvoc_base_RmResource); + __nvoc_init_funcTable_ConfidentialComputeApi(pThis); +} + +NV_STATUS __nvoc_objCreate_ConfidentialComputeApi(ConfidentialComputeApi **ppThis, Dynamic *pParent, NvU32 createFlags, CALL_CONTEXT * arg_pCallContext, struct RS_RES_ALLOC_PARAMS_INTERNAL * arg_pParams) { + NV_STATUS status; + Object *pParentObj; + ConfidentialComputeApi *pThis; + + status = __nvoc_handleObjCreateMemAlloc(createFlags, sizeof(ConfidentialComputeApi), (void**)&pThis, (void**)ppThis); + if (status != NV_OK) + return status; + + portMemSet(pThis, 0, sizeof(ConfidentialComputeApi)); + + __nvoc_initRtti(staticCast(pThis, Dynamic), &__nvoc_class_def_ConfidentialComputeApi); + + pThis->__nvoc_base_RmResource.__nvoc_base_RsResource.__nvoc_base_Object.createFlags = createFlags; + + if (pParent != NULL && !(createFlags & NVOC_OBJ_CREATE_FLAGS_PARENT_HALSPEC_ONLY)) + { + pParentObj = dynamicCast(pParent, Object); + objAddChild(pParentObj, &pThis->__nvoc_base_RmResource.__nvoc_base_RsResource.__nvoc_base_Object); + } + else + { + pThis->__nvoc_base_RmResource.__nvoc_base_RsResource.__nvoc_base_Object.pParent = NULL; + } + + __nvoc_init_ConfidentialComputeApi(pThis); + status = __nvoc_ctor_ConfidentialComputeApi(pThis, arg_pCallContext, arg_pParams); + if (status != NV_OK) goto __nvoc_objCreate_ConfidentialComputeApi_cleanup; + + *ppThis = pThis; + + return NV_OK; + +__nvoc_objCreate_ConfidentialComputeApi_cleanup: + // do not call destructors here since the constructor already called them + if (createFlags & NVOC_OBJ_CREATE_FLAGS_IN_PLACE_CONSTRUCT) + portMemSet(pThis, 0, sizeof(ConfidentialComputeApi)); + else + portMemFree(pThis); + + // coverity[leaked_storage:FALSE] + return status; +} + +NV_STATUS __nvoc_objCreateDynamic_ConfidentialComputeApi(ConfidentialComputeApi **ppThis, Dynamic *pParent, NvU32 createFlags, va_list args) { + NV_STATUS status; + CALL_CONTEXT * arg_pCallContext = va_arg(args, CALL_CONTEXT *); + struct RS_RES_ALLOC_PARAMS_INTERNAL * arg_pParams = va_arg(args, struct RS_RES_ALLOC_PARAMS_INTERNAL *); + + status = __nvoc_objCreate_ConfidentialComputeApi(ppThis, pParent, createFlags, arg_pCallContext, arg_pParams); + + return status; +} + diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/generated/g_conf_compute_api_nvoc.h nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_conf_compute_api_nvoc.h --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/generated/g_conf_compute_api_nvoc.h 1970-01-01 00:00:00.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_conf_compute_api_nvoc.h 2024-03-05 22:18:08.000000000 +0000 @@ -0,0 +1,297 @@ +#ifndef _G_CONF_COMPUTE_API_NVOC_H_ +#define _G_CONF_COMPUTE_API_NVOC_H_ +#include "nvoc/runtime.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/* + * SPDX-FileCopyrightText: Copyright (c) 2021-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#include "g_conf_compute_api_nvoc.h" + +#ifndef CONF_COMPUTE_API_H +#define CONF_COMPUTE_API_H + +#include "gpu/gpu.h" +#include "rmapi/resource.h" +#include "ctrl/ctrlcb33.h" +#include "gpu_mgr/gpu_mgr.h" +#include "gpu/conf_compute/conf_compute.h" + + +/****************************************************************************\ + * * + * Confidential Compute module header. * + * * + ****************************************************************************/ + +#ifdef NVOC_CONF_COMPUTE_API_H_PRIVATE_ACCESS_ALLOWED +#define PRIVATE_FIELD(x) x +#else +#define PRIVATE_FIELD(x) NVOC_PRIVATE_FIELD(x) +#endif +struct ConfidentialComputeApi { + const struct NVOC_RTTI *__nvoc_rtti; + struct RmResource __nvoc_base_RmResource; + struct Object *__nvoc_pbase_Object; + struct RsResource *__nvoc_pbase_RsResource; + struct RmResourceCommon *__nvoc_pbase_RmResourceCommon; + struct RmResource *__nvoc_pbase_RmResource; + struct ConfidentialComputeApi *__nvoc_pbase_ConfidentialComputeApi; + NV_STATUS (*__confComputeApiCtrlCmdSystemGetCapabilities__)(struct ConfidentialComputeApi *, NV_CONF_COMPUTE_CTRL_CMD_SYSTEM_GET_CAPABILITIES_PARAMS *); + NV_STATUS (*__confComputeApiCtrlCmdSystemGetGpusState__)(struct ConfidentialComputeApi *, NV_CONF_COMPUTE_CTRL_CMD_SYSTEM_GET_GPUS_STATE_PARAMS *); + NV_STATUS (*__confComputeApiCtrlCmdSystemSetGpusState__)(struct ConfidentialComputeApi *, NV_CONF_COMPUTE_CTRL_CMD_SYSTEM_SET_GPUS_STATE_PARAMS *); + NV_STATUS (*__confComputeApiCtrlCmdGpuGetVidmemSize__)(struct ConfidentialComputeApi *, NV_CONF_COMPUTE_CTRL_CMD_GPU_GET_VIDMEM_SIZE_PARAMS *); + NV_STATUS (*__confComputeApiCtrlCmdGpuSetVidmemSize__)(struct ConfidentialComputeApi *, NV_CONF_COMPUTE_CTRL_CMD_GPU_SET_VIDMEM_SIZE_PARAMS *); + NV_STATUS (*__confComputeApiCtrlCmdGetGpuCertificate__)(struct ConfidentialComputeApi *, NV_CONF_COMPUTE_CTRL_CMD_GET_GPU_CERTIFICATE_PARAMS *); + NV_STATUS (*__confComputeApiCtrlCmdGetGpuAttestationReport__)(struct ConfidentialComputeApi *, NV_CONF_COMPUTE_CTRL_CMD_GET_GPU_ATTESTATION_REPORT_PARAMS *); + NV_STATUS (*__confComputeApiCtrlCmdGpuGetNumSecureChannels__)(struct ConfidentialComputeApi *, NV_CONF_COMPUTE_CTRL_CMD_GPU_GET_NUM_SECURE_CHANNELS_PARAMS *); + NvBool (*__confComputeApiShareCallback__)(struct ConfidentialComputeApi *, struct RsClient *, struct RsResourceRef *, RS_SHARE_POLICY *); + NV_STATUS (*__confComputeApiCheckMemInterUnmap__)(struct ConfidentialComputeApi *, NvBool); + NV_STATUS (*__confComputeApiControl__)(struct ConfidentialComputeApi *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); + NV_STATUS (*__confComputeApiGetMemInterMapParams__)(struct ConfidentialComputeApi *, RMRES_MEM_INTER_MAP_PARAMS *); + NV_STATUS (*__confComputeApiGetMemoryMappingDescriptor__)(struct ConfidentialComputeApi *, struct MEMORY_DESCRIPTOR **); + NvU32 (*__confComputeApiGetRefCount__)(struct ConfidentialComputeApi *); + NV_STATUS (*__confComputeApiControlFilter__)(struct ConfidentialComputeApi *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); + void (*__confComputeApiAddAdditionalDependants__)(struct RsClient *, struct ConfidentialComputeApi *, RsResourceRef *); + NV_STATUS (*__confComputeApiUnmapFrom__)(struct ConfidentialComputeApi *, RS_RES_UNMAP_FROM_PARAMS *); + NV_STATUS (*__confComputeApiControlSerialization_Prologue__)(struct ConfidentialComputeApi *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); + NV_STATUS (*__confComputeApiControl_Prologue__)(struct ConfidentialComputeApi *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); + NvBool (*__confComputeApiCanCopy__)(struct ConfidentialComputeApi *); + NV_STATUS (*__confComputeApiUnmap__)(struct ConfidentialComputeApi *, struct CALL_CONTEXT *, RsCpuMapping *); + void (*__confComputeApiPreDestruct__)(struct ConfidentialComputeApi *); + NV_STATUS (*__confComputeApiMapTo__)(struct ConfidentialComputeApi *, RS_RES_MAP_TO_PARAMS *); + NV_STATUS (*__confComputeApiIsDuplicate__)(struct ConfidentialComputeApi *, NvHandle, NvBool *); + void (*__confComputeApiControlSerialization_Epilogue__)(struct ConfidentialComputeApi *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); + void (*__confComputeApiControl_Epilogue__)(struct ConfidentialComputeApi *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); + NV_STATUS (*__confComputeApiControlLookup__)(struct ConfidentialComputeApi *, struct RS_RES_CONTROL_PARAMS_INTERNAL *, const struct NVOC_EXPORTED_METHOD_DEF **); + NV_STATUS (*__confComputeApiMap__)(struct ConfidentialComputeApi *, struct CALL_CONTEXT *, RS_CPU_MAP_PARAMS *, RsCpuMapping *); + NvBool (*__confComputeApiAccessCallback__)(struct ConfidentialComputeApi *, struct RsClient *, void *, RsAccessRight); + struct CONF_COMPUTE_CAPS *pCcCaps; +}; + +#ifndef __NVOC_CLASS_ConfidentialComputeApi_TYPEDEF__ +#define __NVOC_CLASS_ConfidentialComputeApi_TYPEDEF__ +typedef struct ConfidentialComputeApi ConfidentialComputeApi; +#endif /* __NVOC_CLASS_ConfidentialComputeApi_TYPEDEF__ */ + +#ifndef __nvoc_class_id_ConfidentialComputeApi +#define __nvoc_class_id_ConfidentialComputeApi 0xea5cb0 +#endif /* __nvoc_class_id_ConfidentialComputeApi */ + +extern const struct NVOC_CLASS_DEF __nvoc_class_def_ConfidentialComputeApi; + +#define __staticCast_ConfidentialComputeApi(pThis) \ + ((pThis)->__nvoc_pbase_ConfidentialComputeApi) + +#ifdef __nvoc_conf_compute_api_h_disabled +#define __dynamicCast_ConfidentialComputeApi(pThis) ((ConfidentialComputeApi*)NULL) +#else //__nvoc_conf_compute_api_h_disabled +#define __dynamicCast_ConfidentialComputeApi(pThis) \ + ((ConfidentialComputeApi*)__nvoc_dynamicCast(staticCast((pThis), Dynamic), classInfo(ConfidentialComputeApi))) +#endif //__nvoc_conf_compute_api_h_disabled + + +NV_STATUS __nvoc_objCreateDynamic_ConfidentialComputeApi(ConfidentialComputeApi**, Dynamic*, NvU32, va_list); + +NV_STATUS __nvoc_objCreate_ConfidentialComputeApi(ConfidentialComputeApi**, Dynamic*, NvU32, CALL_CONTEXT * arg_pCallContext, struct RS_RES_ALLOC_PARAMS_INTERNAL * arg_pParams); +#define __objCreate_ConfidentialComputeApi(ppNewObj, pParent, createFlags, arg_pCallContext, arg_pParams) \ + __nvoc_objCreate_ConfidentialComputeApi((ppNewObj), staticCast((pParent), Dynamic), (createFlags), arg_pCallContext, arg_pParams) + +#define confComputeApiCtrlCmdSystemGetCapabilities(pConfComputeApi, pParams) confComputeApiCtrlCmdSystemGetCapabilities_DISPATCH(pConfComputeApi, pParams) +#define confComputeApiCtrlCmdSystemGetGpusState(pConfComputeApi, pParams) confComputeApiCtrlCmdSystemGetGpusState_DISPATCH(pConfComputeApi, pParams) +#define confComputeApiCtrlCmdSystemSetGpusState(pConfComputeApi, pParams) confComputeApiCtrlCmdSystemSetGpusState_DISPATCH(pConfComputeApi, pParams) +#define confComputeApiCtrlCmdGpuGetVidmemSize(pConfComputeApi, pParams) confComputeApiCtrlCmdGpuGetVidmemSize_DISPATCH(pConfComputeApi, pParams) +#define confComputeApiCtrlCmdGpuSetVidmemSize(pConfComputeApi, pParams) confComputeApiCtrlCmdGpuSetVidmemSize_DISPATCH(pConfComputeApi, pParams) +#define confComputeApiCtrlCmdGetGpuCertificate(pConfComputeApi, pParams) confComputeApiCtrlCmdGetGpuCertificate_DISPATCH(pConfComputeApi, pParams) +#define confComputeApiCtrlCmdGetGpuAttestationReport(pConfComputeApi, pParams) confComputeApiCtrlCmdGetGpuAttestationReport_DISPATCH(pConfComputeApi, pParams) +#define confComputeApiCtrlCmdGpuGetNumSecureChannels(pConfComputeApi, pParams) confComputeApiCtrlCmdGpuGetNumSecureChannels_DISPATCH(pConfComputeApi, pParams) +#define confComputeApiShareCallback(pResource, pInvokingClient, pParentRef, pSharePolicy) confComputeApiShareCallback_DISPATCH(pResource, pInvokingClient, pParentRef, pSharePolicy) +#define confComputeApiCheckMemInterUnmap(pRmResource, bSubdeviceHandleProvided) confComputeApiCheckMemInterUnmap_DISPATCH(pRmResource, bSubdeviceHandleProvided) +#define confComputeApiControl(pResource, pCallContext, pParams) confComputeApiControl_DISPATCH(pResource, pCallContext, pParams) +#define confComputeApiGetMemInterMapParams(pRmResource, pParams) confComputeApiGetMemInterMapParams_DISPATCH(pRmResource, pParams) +#define confComputeApiGetMemoryMappingDescriptor(pRmResource, ppMemDesc) confComputeApiGetMemoryMappingDescriptor_DISPATCH(pRmResource, ppMemDesc) +#define confComputeApiGetRefCount(pResource) confComputeApiGetRefCount_DISPATCH(pResource) +#define confComputeApiControlFilter(pResource, pCallContext, pParams) confComputeApiControlFilter_DISPATCH(pResource, pCallContext, pParams) +#define confComputeApiAddAdditionalDependants(pClient, pResource, pReference) confComputeApiAddAdditionalDependants_DISPATCH(pClient, pResource, pReference) +#define confComputeApiUnmapFrom(pResource, pParams) confComputeApiUnmapFrom_DISPATCH(pResource, pParams) +#define confComputeApiControlSerialization_Prologue(pResource, pCallContext, pParams) confComputeApiControlSerialization_Prologue_DISPATCH(pResource, pCallContext, pParams) +#define confComputeApiControl_Prologue(pResource, pCallContext, pParams) confComputeApiControl_Prologue_DISPATCH(pResource, pCallContext, pParams) +#define confComputeApiCanCopy(pResource) confComputeApiCanCopy_DISPATCH(pResource) +#define confComputeApiUnmap(pResource, pCallContext, pCpuMapping) confComputeApiUnmap_DISPATCH(pResource, pCallContext, pCpuMapping) +#define confComputeApiPreDestruct(pResource) confComputeApiPreDestruct_DISPATCH(pResource) +#define confComputeApiMapTo(pResource, pParams) confComputeApiMapTo_DISPATCH(pResource, pParams) +#define confComputeApiIsDuplicate(pResource, hMemory, pDuplicate) confComputeApiIsDuplicate_DISPATCH(pResource, hMemory, pDuplicate) +#define confComputeApiControlSerialization_Epilogue(pResource, pCallContext, pParams) confComputeApiControlSerialization_Epilogue_DISPATCH(pResource, pCallContext, pParams) +#define confComputeApiControl_Epilogue(pResource, pCallContext, pParams) confComputeApiControl_Epilogue_DISPATCH(pResource, pCallContext, pParams) +#define confComputeApiControlLookup(pResource, pParams, ppEntry) confComputeApiControlLookup_DISPATCH(pResource, pParams, ppEntry) +#define confComputeApiMap(pResource, pCallContext, pParams, pCpuMapping) confComputeApiMap_DISPATCH(pResource, pCallContext, pParams, pCpuMapping) +#define confComputeApiAccessCallback(pResource, pInvokingClient, pAllocParams, accessRight) confComputeApiAccessCallback_DISPATCH(pResource, pInvokingClient, pAllocParams, accessRight) +NV_STATUS confComputeApiCtrlCmdSystemGetCapabilities_IMPL(struct ConfidentialComputeApi *pConfComputeApi, NV_CONF_COMPUTE_CTRL_CMD_SYSTEM_GET_CAPABILITIES_PARAMS *pParams); + +static inline NV_STATUS confComputeApiCtrlCmdSystemGetCapabilities_DISPATCH(struct ConfidentialComputeApi *pConfComputeApi, NV_CONF_COMPUTE_CTRL_CMD_SYSTEM_GET_CAPABILITIES_PARAMS *pParams) { + return pConfComputeApi->__confComputeApiCtrlCmdSystemGetCapabilities__(pConfComputeApi, pParams); +} + +NV_STATUS confComputeApiCtrlCmdSystemGetGpusState_IMPL(struct ConfidentialComputeApi *pConfComputeApi, NV_CONF_COMPUTE_CTRL_CMD_SYSTEM_GET_GPUS_STATE_PARAMS *pParams); + +static inline NV_STATUS confComputeApiCtrlCmdSystemGetGpusState_DISPATCH(struct ConfidentialComputeApi *pConfComputeApi, NV_CONF_COMPUTE_CTRL_CMD_SYSTEM_GET_GPUS_STATE_PARAMS *pParams) { + return pConfComputeApi->__confComputeApiCtrlCmdSystemGetGpusState__(pConfComputeApi, pParams); +} + +NV_STATUS confComputeApiCtrlCmdSystemSetGpusState_IMPL(struct ConfidentialComputeApi *pConfComputeApi, NV_CONF_COMPUTE_CTRL_CMD_SYSTEM_SET_GPUS_STATE_PARAMS *pParams); + +static inline NV_STATUS confComputeApiCtrlCmdSystemSetGpusState_DISPATCH(struct ConfidentialComputeApi *pConfComputeApi, NV_CONF_COMPUTE_CTRL_CMD_SYSTEM_SET_GPUS_STATE_PARAMS *pParams) { + return pConfComputeApi->__confComputeApiCtrlCmdSystemSetGpusState__(pConfComputeApi, pParams); +} + +NV_STATUS confComputeApiCtrlCmdGpuGetVidmemSize_IMPL(struct ConfidentialComputeApi *pConfComputeApi, NV_CONF_COMPUTE_CTRL_CMD_GPU_GET_VIDMEM_SIZE_PARAMS *pParams); + +static inline NV_STATUS confComputeApiCtrlCmdGpuGetVidmemSize_DISPATCH(struct ConfidentialComputeApi *pConfComputeApi, NV_CONF_COMPUTE_CTRL_CMD_GPU_GET_VIDMEM_SIZE_PARAMS *pParams) { + return pConfComputeApi->__confComputeApiCtrlCmdGpuGetVidmemSize__(pConfComputeApi, pParams); +} + +NV_STATUS confComputeApiCtrlCmdGpuSetVidmemSize_IMPL(struct ConfidentialComputeApi *pConfComputeApi, NV_CONF_COMPUTE_CTRL_CMD_GPU_SET_VIDMEM_SIZE_PARAMS *pParams); + +static inline NV_STATUS confComputeApiCtrlCmdGpuSetVidmemSize_DISPATCH(struct ConfidentialComputeApi *pConfComputeApi, NV_CONF_COMPUTE_CTRL_CMD_GPU_SET_VIDMEM_SIZE_PARAMS *pParams) { + return pConfComputeApi->__confComputeApiCtrlCmdGpuSetVidmemSize__(pConfComputeApi, pParams); +} + +NV_STATUS confComputeApiCtrlCmdGetGpuCertificate_IMPL(struct ConfidentialComputeApi *pConfComputeApi, NV_CONF_COMPUTE_CTRL_CMD_GET_GPU_CERTIFICATE_PARAMS *pParams); + +static inline NV_STATUS confComputeApiCtrlCmdGetGpuCertificate_DISPATCH(struct ConfidentialComputeApi *pConfComputeApi, NV_CONF_COMPUTE_CTRL_CMD_GET_GPU_CERTIFICATE_PARAMS *pParams) { + return pConfComputeApi->__confComputeApiCtrlCmdGetGpuCertificate__(pConfComputeApi, pParams); +} + +NV_STATUS confComputeApiCtrlCmdGetGpuAttestationReport_IMPL(struct ConfidentialComputeApi *pConfComputeApi, NV_CONF_COMPUTE_CTRL_CMD_GET_GPU_ATTESTATION_REPORT_PARAMS *pParams); + +static inline NV_STATUS confComputeApiCtrlCmdGetGpuAttestationReport_DISPATCH(struct ConfidentialComputeApi *pConfComputeApi, NV_CONF_COMPUTE_CTRL_CMD_GET_GPU_ATTESTATION_REPORT_PARAMS *pParams) { + return pConfComputeApi->__confComputeApiCtrlCmdGetGpuAttestationReport__(pConfComputeApi, pParams); +} + +NV_STATUS confComputeApiCtrlCmdGpuGetNumSecureChannels_IMPL(struct ConfidentialComputeApi *pConfComputeApi, NV_CONF_COMPUTE_CTRL_CMD_GPU_GET_NUM_SECURE_CHANNELS_PARAMS *pParams); + +static inline NV_STATUS confComputeApiCtrlCmdGpuGetNumSecureChannels_DISPATCH(struct ConfidentialComputeApi *pConfComputeApi, NV_CONF_COMPUTE_CTRL_CMD_GPU_GET_NUM_SECURE_CHANNELS_PARAMS *pParams) { + return pConfComputeApi->__confComputeApiCtrlCmdGpuGetNumSecureChannels__(pConfComputeApi, pParams); +} + +static inline NvBool confComputeApiShareCallback_DISPATCH(struct ConfidentialComputeApi *pResource, struct RsClient *pInvokingClient, struct RsResourceRef *pParentRef, RS_SHARE_POLICY *pSharePolicy) { + return pResource->__confComputeApiShareCallback__(pResource, pInvokingClient, pParentRef, pSharePolicy); +} + +static inline NV_STATUS confComputeApiCheckMemInterUnmap_DISPATCH(struct ConfidentialComputeApi *pRmResource, NvBool bSubdeviceHandleProvided) { + return pRmResource->__confComputeApiCheckMemInterUnmap__(pRmResource, bSubdeviceHandleProvided); +} + +static inline NV_STATUS confComputeApiControl_DISPATCH(struct ConfidentialComputeApi *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return pResource->__confComputeApiControl__(pResource, pCallContext, pParams); +} + +static inline NV_STATUS confComputeApiGetMemInterMapParams_DISPATCH(struct ConfidentialComputeApi *pRmResource, RMRES_MEM_INTER_MAP_PARAMS *pParams) { + return pRmResource->__confComputeApiGetMemInterMapParams__(pRmResource, pParams); +} + +static inline NV_STATUS confComputeApiGetMemoryMappingDescriptor_DISPATCH(struct ConfidentialComputeApi *pRmResource, struct MEMORY_DESCRIPTOR **ppMemDesc) { + return pRmResource->__confComputeApiGetMemoryMappingDescriptor__(pRmResource, ppMemDesc); +} + +static inline NvU32 confComputeApiGetRefCount_DISPATCH(struct ConfidentialComputeApi *pResource) { + return pResource->__confComputeApiGetRefCount__(pResource); +} + +static inline NV_STATUS confComputeApiControlFilter_DISPATCH(struct ConfidentialComputeApi *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return pResource->__confComputeApiControlFilter__(pResource, pCallContext, pParams); +} + +static inline void confComputeApiAddAdditionalDependants_DISPATCH(struct RsClient *pClient, struct ConfidentialComputeApi *pResource, RsResourceRef *pReference) { + pResource->__confComputeApiAddAdditionalDependants__(pClient, pResource, pReference); +} + +static inline NV_STATUS confComputeApiUnmapFrom_DISPATCH(struct ConfidentialComputeApi *pResource, RS_RES_UNMAP_FROM_PARAMS *pParams) { + return pResource->__confComputeApiUnmapFrom__(pResource, pParams); +} + +static inline NV_STATUS confComputeApiControlSerialization_Prologue_DISPATCH(struct ConfidentialComputeApi *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return pResource->__confComputeApiControlSerialization_Prologue__(pResource, pCallContext, pParams); +} + +static inline NV_STATUS confComputeApiControl_Prologue_DISPATCH(struct ConfidentialComputeApi *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return pResource->__confComputeApiControl_Prologue__(pResource, pCallContext, pParams); +} + +static inline NvBool confComputeApiCanCopy_DISPATCH(struct ConfidentialComputeApi *pResource) { + return pResource->__confComputeApiCanCopy__(pResource); +} + +static inline NV_STATUS confComputeApiUnmap_DISPATCH(struct ConfidentialComputeApi *pResource, struct CALL_CONTEXT *pCallContext, RsCpuMapping *pCpuMapping) { + return pResource->__confComputeApiUnmap__(pResource, pCallContext, pCpuMapping); +} + +static inline void confComputeApiPreDestruct_DISPATCH(struct ConfidentialComputeApi *pResource) { + pResource->__confComputeApiPreDestruct__(pResource); +} + +static inline NV_STATUS confComputeApiMapTo_DISPATCH(struct ConfidentialComputeApi *pResource, RS_RES_MAP_TO_PARAMS *pParams) { + return pResource->__confComputeApiMapTo__(pResource, pParams); +} + +static inline NV_STATUS confComputeApiIsDuplicate_DISPATCH(struct ConfidentialComputeApi *pResource, NvHandle hMemory, NvBool *pDuplicate) { + return pResource->__confComputeApiIsDuplicate__(pResource, hMemory, pDuplicate); +} + +static inline void confComputeApiControlSerialization_Epilogue_DISPATCH(struct ConfidentialComputeApi *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + pResource->__confComputeApiControlSerialization_Epilogue__(pResource, pCallContext, pParams); +} + +static inline void confComputeApiControl_Epilogue_DISPATCH(struct ConfidentialComputeApi *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + pResource->__confComputeApiControl_Epilogue__(pResource, pCallContext, pParams); +} + +static inline NV_STATUS confComputeApiControlLookup_DISPATCH(struct ConfidentialComputeApi *pResource, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams, const struct NVOC_EXPORTED_METHOD_DEF **ppEntry) { + return pResource->__confComputeApiControlLookup__(pResource, pParams, ppEntry); +} + +static inline NV_STATUS confComputeApiMap_DISPATCH(struct ConfidentialComputeApi *pResource, struct CALL_CONTEXT *pCallContext, RS_CPU_MAP_PARAMS *pParams, RsCpuMapping *pCpuMapping) { + return pResource->__confComputeApiMap__(pResource, pCallContext, pParams, pCpuMapping); +} + +static inline NvBool confComputeApiAccessCallback_DISPATCH(struct ConfidentialComputeApi *pResource, struct RsClient *pInvokingClient, void *pAllocParams, RsAccessRight accessRight) { + return pResource->__confComputeApiAccessCallback__(pResource, pInvokingClient, pAllocParams, accessRight); +} + +NV_STATUS confComputeApiConstruct_IMPL(struct ConfidentialComputeApi *arg_pConfComputeApi, CALL_CONTEXT *arg_pCallContext, struct RS_RES_ALLOC_PARAMS_INTERNAL *arg_pParams); + +#define __nvoc_confComputeApiConstruct(arg_pConfComputeApi, arg_pCallContext, arg_pParams) confComputeApiConstruct_IMPL(arg_pConfComputeApi, arg_pCallContext, arg_pParams) +void confComputeApiDestruct_IMPL(struct ConfidentialComputeApi *pConfComputeApi); + +#define __nvoc_confComputeApiDestruct(pConfComputeApi) confComputeApiDestruct_IMPL(pConfComputeApi) +#undef PRIVATE_FIELD + +#endif // CONF_COMPUTE_H + +#ifdef __cplusplus +} // extern "C" +#endif +#endif // _G_CONF_COMPUTE_API_NVOC_H_ diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/generated/g_conf_compute_nvoc.c nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_conf_compute_nvoc.c --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/generated/g_conf_compute_nvoc.c 1970-01-01 00:00:00.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_conf_compute_nvoc.c 2024-03-05 22:18:08.000000000 +0000 @@ -0,0 +1,442 @@ +#define NVOC_CONF_COMPUTE_H_PRIVATE_ACCESS_ALLOWED +#include "nvoc/runtime.h" +#include "nvoc/rtti.h" +#include "nvtypes.h" +#include "nvport/nvport.h" +#include "nvport/inline/util_valist.h" +#include "utils/nvassert.h" +#include "g_conf_compute_nvoc.h" + +#ifdef DEBUG +char __nvoc_class_id_uniqueness_check_0x9798cc = 1; +#endif + +extern const struct NVOC_CLASS_DEF __nvoc_class_def_ConfidentialCompute; + +extern const struct NVOC_CLASS_DEF __nvoc_class_def_Object; + +extern const struct NVOC_CLASS_DEF __nvoc_class_def_OBJENGSTATE; + +void __nvoc_init_ConfidentialCompute(ConfidentialCompute*, RmHalspecOwner* ); +void __nvoc_init_funcTable_ConfidentialCompute(ConfidentialCompute*, RmHalspecOwner* ); +NV_STATUS __nvoc_ctor_ConfidentialCompute(ConfidentialCompute*, RmHalspecOwner* ); +void __nvoc_init_dataField_ConfidentialCompute(ConfidentialCompute*, RmHalspecOwner* ); +void __nvoc_dtor_ConfidentialCompute(ConfidentialCompute*); +extern const struct NVOC_EXPORT_INFO __nvoc_export_info_ConfidentialCompute; + +static const struct NVOC_RTTI __nvoc_rtti_ConfidentialCompute_ConfidentialCompute = { + /*pClassDef=*/ &__nvoc_class_def_ConfidentialCompute, + /*dtor=*/ (NVOC_DYNAMIC_DTOR) &__nvoc_dtor_ConfidentialCompute, + /*offset=*/ 0, +}; + +static const struct NVOC_RTTI __nvoc_rtti_ConfidentialCompute_Object = { + /*pClassDef=*/ &__nvoc_class_def_Object, + /*dtor=*/ &__nvoc_destructFromBase, + /*offset=*/ NV_OFFSETOF(ConfidentialCompute, __nvoc_base_OBJENGSTATE.__nvoc_base_Object), +}; + +static const struct NVOC_RTTI __nvoc_rtti_ConfidentialCompute_OBJENGSTATE = { + /*pClassDef=*/ &__nvoc_class_def_OBJENGSTATE, + /*dtor=*/ &__nvoc_destructFromBase, + /*offset=*/ NV_OFFSETOF(ConfidentialCompute, __nvoc_base_OBJENGSTATE), +}; + +static const struct NVOC_CASTINFO __nvoc_castinfo_ConfidentialCompute = { + /*numRelatives=*/ 3, + /*relatives=*/ { + &__nvoc_rtti_ConfidentialCompute_ConfidentialCompute, + &__nvoc_rtti_ConfidentialCompute_OBJENGSTATE, + &__nvoc_rtti_ConfidentialCompute_Object, + }, +}; + +const struct NVOC_CLASS_DEF __nvoc_class_def_ConfidentialCompute = +{ + /*classInfo=*/ { + /*size=*/ sizeof(ConfidentialCompute), + /*classId=*/ classId(ConfidentialCompute), + /*providerId=*/ &__nvoc_rtti_provider, +#if NV_PRINTF_STRINGS_ALLOWED + /*name=*/ "ConfidentialCompute", +#endif + }, + /*objCreatefn=*/ (NVOC_DYNAMIC_OBJ_CREATE) &__nvoc_objCreateDynamic_ConfidentialCompute, + /*pCastInfo=*/ &__nvoc_castinfo_ConfidentialCompute, + /*pExportInfo=*/ &__nvoc_export_info_ConfidentialCompute +}; + +static NV_STATUS __nvoc_thunk_ConfidentialCompute_engstateConstructEngine(struct OBJGPU *pGpu, struct OBJENGSTATE *pConfCompute, ENGDESCRIPTOR engDesc) { + return confComputeConstructEngine(pGpu, (struct ConfidentialCompute *)(((unsigned char *)pConfCompute) - __nvoc_rtti_ConfidentialCompute_OBJENGSTATE.offset), engDesc); +} + +static NV_STATUS __nvoc_thunk_ConfidentialCompute_engstateStatePreInitLocked(struct OBJGPU *pGpu, struct OBJENGSTATE *pConfCompute) { + return confComputeStatePreInitLocked(pGpu, (struct ConfidentialCompute *)(((unsigned char *)pConfCompute) - __nvoc_rtti_ConfidentialCompute_OBJENGSTATE.offset)); +} + +static NV_STATUS __nvoc_thunk_ConfidentialCompute_engstateStateInitLocked(struct OBJGPU *pGpu, struct OBJENGSTATE *pConfCompute) { + return confComputeStateInitLocked(pGpu, (struct ConfidentialCompute *)(((unsigned char *)pConfCompute) - __nvoc_rtti_ConfidentialCompute_OBJENGSTATE.offset)); +} + +static NV_STATUS __nvoc_thunk_ConfidentialCompute_engstateStatePostLoad(struct OBJGPU *pGpu, struct OBJENGSTATE *pConfCompute, NvU32 flags) { + return confComputeStatePostLoad(pGpu, (struct ConfidentialCompute *)(((unsigned char *)pConfCompute) - __nvoc_rtti_ConfidentialCompute_OBJENGSTATE.offset), flags); +} + +static NV_STATUS __nvoc_thunk_ConfidentialCompute_engstateStatePreUnload(struct OBJGPU *pGpu, struct OBJENGSTATE *pConfCompute, NvU32 flags) { + return confComputeStatePreUnload(pGpu, (struct ConfidentialCompute *)(((unsigned char *)pConfCompute) - __nvoc_rtti_ConfidentialCompute_OBJENGSTATE.offset), flags); +} + +static void __nvoc_thunk_ConfidentialCompute_engstateStateDestroy(struct OBJGPU *pGpu, struct OBJENGSTATE *pConfCompute) { + confComputeStateDestroy(pGpu, (struct ConfidentialCompute *)(((unsigned char *)pConfCompute) - __nvoc_rtti_ConfidentialCompute_OBJENGSTATE.offset)); +} + +static NV_STATUS __nvoc_thunk_OBJENGSTATE_confComputeStateLoad(POBJGPU pGpu, struct ConfidentialCompute *pEngstate, NvU32 arg0) { + return engstateStateLoad(pGpu, (struct OBJENGSTATE *)(((unsigned char *)pEngstate) + __nvoc_rtti_ConfidentialCompute_OBJENGSTATE.offset), arg0); +} + +static NV_STATUS __nvoc_thunk_OBJENGSTATE_confComputeStateUnload(POBJGPU pGpu, struct ConfidentialCompute *pEngstate, NvU32 arg0) { + return engstateStateUnload(pGpu, (struct OBJENGSTATE *)(((unsigned char *)pEngstate) + __nvoc_rtti_ConfidentialCompute_OBJENGSTATE.offset), arg0); +} + +static NV_STATUS __nvoc_thunk_OBJENGSTATE_confComputeStatePreLoad(POBJGPU pGpu, struct ConfidentialCompute *pEngstate, NvU32 arg0) { + return engstateStatePreLoad(pGpu, (struct OBJENGSTATE *)(((unsigned char *)pEngstate) + __nvoc_rtti_ConfidentialCompute_OBJENGSTATE.offset), arg0); +} + +static NV_STATUS __nvoc_thunk_OBJENGSTATE_confComputeStatePostUnload(POBJGPU pGpu, struct ConfidentialCompute *pEngstate, NvU32 arg0) { + return engstateStatePostUnload(pGpu, (struct OBJENGSTATE *)(((unsigned char *)pEngstate) + __nvoc_rtti_ConfidentialCompute_OBJENGSTATE.offset), arg0); +} + +static NV_STATUS __nvoc_thunk_OBJENGSTATE_confComputeStateInitUnlocked(POBJGPU pGpu, struct ConfidentialCompute *pEngstate) { + return engstateStateInitUnlocked(pGpu, (struct OBJENGSTATE *)(((unsigned char *)pEngstate) + __nvoc_rtti_ConfidentialCompute_OBJENGSTATE.offset)); +} + +static void __nvoc_thunk_OBJENGSTATE_confComputeInitMissing(POBJGPU pGpu, struct ConfidentialCompute *pEngstate) { + engstateInitMissing(pGpu, (struct OBJENGSTATE *)(((unsigned char *)pEngstate) + __nvoc_rtti_ConfidentialCompute_OBJENGSTATE.offset)); +} + +static NV_STATUS __nvoc_thunk_OBJENGSTATE_confComputeStatePreInitUnlocked(POBJGPU pGpu, struct ConfidentialCompute *pEngstate) { + return engstateStatePreInitUnlocked(pGpu, (struct OBJENGSTATE *)(((unsigned char *)pEngstate) + __nvoc_rtti_ConfidentialCompute_OBJENGSTATE.offset)); +} + +static NvBool __nvoc_thunk_OBJENGSTATE_confComputeIsPresent(POBJGPU pGpu, struct ConfidentialCompute *pEngstate) { + return engstateIsPresent(pGpu, (struct OBJENGSTATE *)(((unsigned char *)pEngstate) + __nvoc_rtti_ConfidentialCompute_OBJENGSTATE.offset)); +} + +const struct NVOC_EXPORT_INFO __nvoc_export_info_ConfidentialCompute = +{ + /*numEntries=*/ 0, + /*pExportEntries=*/ 0 +}; + +void __nvoc_dtor_OBJENGSTATE(OBJENGSTATE*); +void __nvoc_dtor_ConfidentialCompute(ConfidentialCompute *pThis) { + __nvoc_dtor_OBJENGSTATE(&pThis->__nvoc_base_OBJENGSTATE); + PORT_UNREFERENCED_VARIABLE(pThis); +} + +void __nvoc_init_dataField_ConfidentialCompute(ConfidentialCompute *pThis, RmHalspecOwner *pRmhalspecowner) { + RmVariantHal *rmVariantHal = &pRmhalspecowner->rmVariantHal; + const unsigned long rmVariantHal_HalVarIdx = (unsigned long)rmVariantHal->__nvoc_HalVarIdx; + ChipHal *chipHal = &pRmhalspecowner->chipHal; + const unsigned long chipHal_HalVarIdx = (unsigned long)chipHal->__nvoc_HalVarIdx; + PORT_UNREFERENCED_VARIABLE(pThis); + PORT_UNREFERENCED_VARIABLE(pRmhalspecowner); + PORT_UNREFERENCED_VARIABLE(rmVariantHal); + PORT_UNREFERENCED_VARIABLE(rmVariantHal_HalVarIdx); + PORT_UNREFERENCED_VARIABLE(chipHal); + PORT_UNREFERENCED_VARIABLE(chipHal_HalVarIdx); + pThis->setProperty(pThis, PDB_PROP_CONFCOMPUTE_ENABLED, ((NvBool)(0 != 0))); + pThis->setProperty(pThis, PDB_PROP_CONFCOMPUTE_CC_FEATURE_ENABLED, ((NvBool)(0 != 0))); + pThis->setProperty(pThis, PDB_PROP_CONFCOMPUTE_APM_FEATURE_ENABLED, ((NvBool)(0 != 0))); + pThis->setProperty(pThis, PDB_PROP_CONFCOMPUTE_DEVTOOLS_MODE_ENABLED, ((NvBool)(0 != 0))); + pThis->setProperty(pThis, PDB_PROP_CONFCOMPUTE_ENABLE_EARLY_INIT, ((NvBool)(0 != 0))); + pThis->setProperty(pThis, PDB_PROP_CONFCOMPUTE_GPUS_READY_CHECK_ENABLED, ((NvBool)(0 == 0))); + pThis->setProperty(pThis, PDB_PROP_CONFCOMPUTE_SPDM_ENABLED, ((NvBool)(0 != 0))); + pThis->setProperty(pThis, PDB_PROP_CONFCOMPUTE_ENCRYPT_READY, ((NvBool)(0 != 0))); + pThis->setProperty(pThis, PDB_PROP_CONFCOMPUTE_ENCRYPT_ENABLED, ((NvBool)(0 != 0))); +} + +NV_STATUS __nvoc_ctor_OBJENGSTATE(OBJENGSTATE* ); +NV_STATUS __nvoc_ctor_ConfidentialCompute(ConfidentialCompute *pThis, RmHalspecOwner *pRmhalspecowner) { + NV_STATUS status = NV_OK; + status = __nvoc_ctor_OBJENGSTATE(&pThis->__nvoc_base_OBJENGSTATE); + if (status != NV_OK) goto __nvoc_ctor_ConfidentialCompute_fail_OBJENGSTATE; + __nvoc_init_dataField_ConfidentialCompute(pThis, pRmhalspecowner); + goto __nvoc_ctor_ConfidentialCompute_exit; // Success + +__nvoc_ctor_ConfidentialCompute_fail_OBJENGSTATE: +__nvoc_ctor_ConfidentialCompute_exit: + + return status; +} + +static void __nvoc_init_funcTable_ConfidentialCompute_1(ConfidentialCompute *pThis, RmHalspecOwner *pRmhalspecowner) { + RmVariantHal *rmVariantHal = &pRmhalspecowner->rmVariantHal; + const unsigned long rmVariantHal_HalVarIdx = (unsigned long)rmVariantHal->__nvoc_HalVarIdx; + ChipHal *chipHal = &pRmhalspecowner->chipHal; + const unsigned long chipHal_HalVarIdx = (unsigned long)chipHal->__nvoc_HalVarIdx; + PORT_UNREFERENCED_VARIABLE(pThis); + PORT_UNREFERENCED_VARIABLE(pRmhalspecowner); + PORT_UNREFERENCED_VARIABLE(rmVariantHal); + PORT_UNREFERENCED_VARIABLE(rmVariantHal_HalVarIdx); + PORT_UNREFERENCED_VARIABLE(chipHal); + PORT_UNREFERENCED_VARIABLE(chipHal_HalVarIdx); + + pThis->__confComputeConstructEngine__ = &confComputeConstructEngine_IMPL; + + // Hal function -- confComputeStatePreInitLocked + pThis->__confComputeStatePreInitLocked__ = &confComputeStatePreInitLocked_IMPL; + + pThis->__confComputeStateInitLocked__ = &confComputeStateInitLocked_IMPL; + + // Hal function -- confComputeStatePostLoad + pThis->__confComputeStatePostLoad__ = &confComputeStatePostLoad_IMPL; + + // Hal function -- confComputeStatePreUnload + pThis->__confComputeStatePreUnload__ = &confComputeStatePreUnload_56cd7a; + + // Hal function -- confComputeStateDestroy + pThis->__confComputeStateDestroy__ = &confComputeStateDestroy_IMPL; + + // Hal function -- confComputeKeyStoreRetrieveViaChannel + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ + { + pThis->__confComputeKeyStoreRetrieveViaChannel__ = &confComputeKeyStoreRetrieveViaChannel_GH100; + } + // default + else + { + pThis->__confComputeKeyStoreRetrieveViaChannel__ = &confComputeKeyStoreRetrieveViaChannel_46f6a7; + } + + // Hal function -- confComputeKeyStoreRetrieveViaKeyId + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ + { + pThis->__confComputeKeyStoreRetrieveViaKeyId__ = &confComputeKeyStoreRetrieveViaKeyId_GH100; + } + // default + else + { + pThis->__confComputeKeyStoreRetrieveViaKeyId__ = &confComputeKeyStoreRetrieveViaKeyId_46f6a7; + } + + // Hal function -- confComputeDeriveSecrets + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ + { + pThis->__confComputeDeriveSecrets__ = &confComputeDeriveSecrets_GH100; + } + // default + else + { + pThis->__confComputeDeriveSecrets__ = &confComputeDeriveSecrets_46f6a7; + } + + // Hal function -- confComputeIsSpdmEnabled + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ + { + pThis->__confComputeIsSpdmEnabled__ = &confComputeIsSpdmEnabled_cbe027; + } + // default + else + { + pThis->__confComputeIsSpdmEnabled__ = &confComputeIsSpdmEnabled_491d52; + } + + // Hal function -- confComputeIsDebugModeEnabled + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ + { + pThis->__confComputeIsDebugModeEnabled__ = &confComputeIsDebugModeEnabled_GH100; + } + // default + else + { + pThis->__confComputeIsDebugModeEnabled__ = &confComputeIsDebugModeEnabled_491d52; + } + + // Hal function -- confComputeIsGpuCcCapable + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ + { + pThis->__confComputeIsGpuCcCapable__ = &confComputeIsGpuCcCapable_GH100; + } + // default + else + { + pThis->__confComputeIsGpuCcCapable__ = &confComputeIsGpuCcCapable_491d52; + } + + // Hal function -- confComputeKeyStoreDepositIvMask + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ + { + pThis->__confComputeKeyStoreDepositIvMask__ = &confComputeKeyStoreDepositIvMask_GH100; + } + // default + else + { + pThis->__confComputeKeyStoreDepositIvMask__ = &confComputeKeyStoreDepositIvMask_b3696a; + } + + // Hal function -- confComputeKeyStoreInit + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ + { + pThis->__confComputeKeyStoreInit__ = &confComputeKeyStoreInit_GH100; + } + // default + else + { + pThis->__confComputeKeyStoreInit__ = &confComputeKeyStoreInit_46f6a7; + } + + // Hal function -- confComputeKeyStoreDeinit + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ + { + pThis->__confComputeKeyStoreDeinit__ = &confComputeKeyStoreDeinit_GH100; + } + // default + else + { + pThis->__confComputeKeyStoreDeinit__ = &confComputeKeyStoreDeinit_b3696a; + } + + // Hal function -- confComputeKeyStoreGetExportMasterKey + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ + { + pThis->__confComputeKeyStoreGetExportMasterKey__ = &confComputeKeyStoreGetExportMasterKey_GH100; + } + // default + else + { + pThis->__confComputeKeyStoreGetExportMasterKey__ = &confComputeKeyStoreGetExportMasterKey_fa6e19; + } + + // Hal function -- confComputeKeyStoreDeriveKey + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ + { + pThis->__confComputeKeyStoreDeriveKey__ = &confComputeKeyStoreDeriveKey_GH100; + } + // default + else + { + pThis->__confComputeKeyStoreDeriveKey__ = &confComputeKeyStoreDeriveKey_46f6a7; + } + + // Hal function -- confComputeKeyStoreClearExportMasterKey + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ + { + pThis->__confComputeKeyStoreClearExportMasterKey__ = &confComputeKeyStoreClearExportMasterKey_GH100; + } + // default + else + { + pThis->__confComputeKeyStoreClearExportMasterKey__ = &confComputeKeyStoreClearExportMasterKey_b3696a; + } + + // Hal function -- confComputeKeyStoreUpdateKey + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ + { + pThis->__confComputeKeyStoreUpdateKey__ = &confComputeKeyStoreUpdateKey_GH100; + } + // default + else + { + pThis->__confComputeKeyStoreUpdateKey__ = &confComputeKeyStoreUpdateKey_46f6a7; + } + + pThis->__nvoc_base_OBJENGSTATE.__engstateConstructEngine__ = &__nvoc_thunk_ConfidentialCompute_engstateConstructEngine; + + pThis->__nvoc_base_OBJENGSTATE.__engstateStatePreInitLocked__ = &__nvoc_thunk_ConfidentialCompute_engstateStatePreInitLocked; + + pThis->__nvoc_base_OBJENGSTATE.__engstateStateInitLocked__ = &__nvoc_thunk_ConfidentialCompute_engstateStateInitLocked; + + pThis->__nvoc_base_OBJENGSTATE.__engstateStatePostLoad__ = &__nvoc_thunk_ConfidentialCompute_engstateStatePostLoad; + + pThis->__nvoc_base_OBJENGSTATE.__engstateStatePreUnload__ = &__nvoc_thunk_ConfidentialCompute_engstateStatePreUnload; + + pThis->__nvoc_base_OBJENGSTATE.__engstateStateDestroy__ = &__nvoc_thunk_ConfidentialCompute_engstateStateDestroy; + + pThis->__confComputeStateLoad__ = &__nvoc_thunk_OBJENGSTATE_confComputeStateLoad; + + pThis->__confComputeStateUnload__ = &__nvoc_thunk_OBJENGSTATE_confComputeStateUnload; + + pThis->__confComputeStatePreLoad__ = &__nvoc_thunk_OBJENGSTATE_confComputeStatePreLoad; + + pThis->__confComputeStatePostUnload__ = &__nvoc_thunk_OBJENGSTATE_confComputeStatePostUnload; + + pThis->__confComputeStateInitUnlocked__ = &__nvoc_thunk_OBJENGSTATE_confComputeStateInitUnlocked; + + pThis->__confComputeInitMissing__ = &__nvoc_thunk_OBJENGSTATE_confComputeInitMissing; + + pThis->__confComputeStatePreInitUnlocked__ = &__nvoc_thunk_OBJENGSTATE_confComputeStatePreInitUnlocked; + + pThis->__confComputeIsPresent__ = &__nvoc_thunk_OBJENGSTATE_confComputeIsPresent; +} + +void __nvoc_init_funcTable_ConfidentialCompute(ConfidentialCompute *pThis, RmHalspecOwner *pRmhalspecowner) { + __nvoc_init_funcTable_ConfidentialCompute_1(pThis, pRmhalspecowner); +} + +void __nvoc_init_OBJENGSTATE(OBJENGSTATE*); +void __nvoc_init_ConfidentialCompute(ConfidentialCompute *pThis, RmHalspecOwner *pRmhalspecowner) { + pThis->__nvoc_pbase_ConfidentialCompute = pThis; + pThis->__nvoc_pbase_Object = &pThis->__nvoc_base_OBJENGSTATE.__nvoc_base_Object; + pThis->__nvoc_pbase_OBJENGSTATE = &pThis->__nvoc_base_OBJENGSTATE; + __nvoc_init_OBJENGSTATE(&pThis->__nvoc_base_OBJENGSTATE); + __nvoc_init_funcTable_ConfidentialCompute(pThis, pRmhalspecowner); +} + +NV_STATUS __nvoc_objCreate_ConfidentialCompute(ConfidentialCompute **ppThis, Dynamic *pParent, NvU32 createFlags) { + NV_STATUS status; + Object *pParentObj; + ConfidentialCompute *pThis; + RmHalspecOwner *pRmhalspecowner; + + status = __nvoc_handleObjCreateMemAlloc(createFlags, sizeof(ConfidentialCompute), (void**)&pThis, (void**)ppThis); + if (status != NV_OK) + return status; + + portMemSet(pThis, 0, sizeof(ConfidentialCompute)); + + __nvoc_initRtti(staticCast(pThis, Dynamic), &__nvoc_class_def_ConfidentialCompute); + + pThis->__nvoc_base_OBJENGSTATE.__nvoc_base_Object.createFlags = createFlags; + + if (pParent != NULL && !(createFlags & NVOC_OBJ_CREATE_FLAGS_PARENT_HALSPEC_ONLY)) + { + pParentObj = dynamicCast(pParent, Object); + objAddChild(pParentObj, &pThis->__nvoc_base_OBJENGSTATE.__nvoc_base_Object); + } + else + { + pThis->__nvoc_base_OBJENGSTATE.__nvoc_base_Object.pParent = NULL; + } + + if ((pRmhalspecowner = dynamicCast(pParent, RmHalspecOwner)) == NULL) + pRmhalspecowner = objFindAncestorOfType(RmHalspecOwner, pParent); + NV_ASSERT_OR_RETURN(pRmhalspecowner != NULL, NV_ERR_INVALID_ARGUMENT); + + __nvoc_init_ConfidentialCompute(pThis, pRmhalspecowner); + status = __nvoc_ctor_ConfidentialCompute(pThis, pRmhalspecowner); + if (status != NV_OK) goto __nvoc_objCreate_ConfidentialCompute_cleanup; + + *ppThis = pThis; + + return NV_OK; + +__nvoc_objCreate_ConfidentialCompute_cleanup: + // do not call destructors here since the constructor already called them + if (createFlags & NVOC_OBJ_CREATE_FLAGS_IN_PLACE_CONSTRUCT) + portMemSet(pThis, 0, sizeof(ConfidentialCompute)); + else + portMemFree(pThis); + + // coverity[leaked_storage:FALSE] + return status; +} + +NV_STATUS __nvoc_objCreateDynamic_ConfidentialCompute(ConfidentialCompute **ppThis, Dynamic *pParent, NvU32 createFlags, va_list args) { + NV_STATUS status; + + status = __nvoc_objCreate_ConfidentialCompute(ppThis, pParent, createFlags); + + return status; +} + diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/generated/g_conf_compute_nvoc.h nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_conf_compute_nvoc.h --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/generated/g_conf_compute_nvoc.h 1970-01-01 00:00:00.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_conf_compute_nvoc.h 2024-03-05 22:18:08.000000000 +0000 @@ -0,0 +1,537 @@ +#ifndef _G_CONF_COMPUTE_NVOC_H_ +#define _G_CONF_COMPUTE_NVOC_H_ +#include "nvoc/runtime.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/* + * SPDX-FileCopyrightText: Copyright (c) 2021-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#include "g_conf_compute_nvoc.h" + +#ifndef CONF_COMPUTE_H +#define CONF_COMPUTE_H + +#include "gpu/gpu.h" +#include "gpu/eng_state.h" +#include "gpu/spdm/spdm.h" +#include "ctrl/ctrl2080/ctrl2080spdm.h" +#include "ctrl/ctrl2080/ctrl2080internal.h" +#include "cc_drv.h" +#include "conf_compute/cc_keystore.h" +#include "kernel/gpu/fifo/kernel_channel.h" +#include "kernel/gpu/intr/engine_idx.h" +#include "kernel/gpu/conf_compute/ccsl_context.h" + +/****************************************************************************\ + * * + * Confidential Compute module header. * + * * + ****************************************************************************/ + +#ifdef NVOC_CONF_COMPUTE_H_PRIVATE_ACCESS_ALLOWED +#define PRIVATE_FIELD(x) x +#else +#define PRIVATE_FIELD(x) NVOC_PRIVATE_FIELD(x) +#endif +struct ConfidentialCompute { + const struct NVOC_RTTI *__nvoc_rtti; + struct OBJENGSTATE __nvoc_base_OBJENGSTATE; + struct Object *__nvoc_pbase_Object; + struct OBJENGSTATE *__nvoc_pbase_OBJENGSTATE; + struct ConfidentialCompute *__nvoc_pbase_ConfidentialCompute; + NV_STATUS (*__confComputeConstructEngine__)(struct OBJGPU *, struct ConfidentialCompute *, ENGDESCRIPTOR); + NV_STATUS (*__confComputeStatePreInitLocked__)(struct OBJGPU *, struct ConfidentialCompute *); + NV_STATUS (*__confComputeStateInitLocked__)(struct OBJGPU *, struct ConfidentialCompute *); + NV_STATUS (*__confComputeStatePostLoad__)(struct OBJGPU *, struct ConfidentialCompute *, NvU32); + NV_STATUS (*__confComputeStatePreUnload__)(struct OBJGPU *, struct ConfidentialCompute *, NvU32); + void (*__confComputeStateDestroy__)(struct OBJGPU *, struct ConfidentialCompute *); + NV_STATUS (*__confComputeKeyStoreRetrieveViaChannel__)(struct ConfidentialCompute *, struct KernelChannel *, ROTATE_IV_TYPE, NvBool, CC_KMB *); + NV_STATUS (*__confComputeKeyStoreRetrieveViaKeyId__)(struct ConfidentialCompute *, NvU32, ROTATE_IV_TYPE, NvBool, CC_KMB *); + NV_STATUS (*__confComputeDeriveSecrets__)(struct ConfidentialCompute *, NvU32); + NvBool (*__confComputeIsSpdmEnabled__)(struct OBJGPU *, struct ConfidentialCompute *); + NvBool (*__confComputeIsDebugModeEnabled__)(struct OBJGPU *, struct ConfidentialCompute *); + NvBool (*__confComputeIsGpuCcCapable__)(struct OBJGPU *, struct ConfidentialCompute *); + void (*__confComputeKeyStoreDepositIvMask__)(struct ConfidentialCompute *, NvU32, void *); + NV_STATUS (*__confComputeKeyStoreInit__)(struct ConfidentialCompute *); + void (*__confComputeKeyStoreDeinit__)(struct ConfidentialCompute *); + void *(*__confComputeKeyStoreGetExportMasterKey__)(struct ConfidentialCompute *); + NV_STATUS (*__confComputeKeyStoreDeriveKey__)(struct ConfidentialCompute *, NvU32); + void (*__confComputeKeyStoreClearExportMasterKey__)(struct ConfidentialCompute *); + NV_STATUS (*__confComputeKeyStoreUpdateKey__)(struct ConfidentialCompute *, NvU32); + NV_STATUS (*__confComputeStateLoad__)(POBJGPU, struct ConfidentialCompute *, NvU32); + NV_STATUS (*__confComputeStateUnload__)(POBJGPU, struct ConfidentialCompute *, NvU32); + NV_STATUS (*__confComputeStatePreLoad__)(POBJGPU, struct ConfidentialCompute *, NvU32); + NV_STATUS (*__confComputeStatePostUnload__)(POBJGPU, struct ConfidentialCompute *, NvU32); + NV_STATUS (*__confComputeStateInitUnlocked__)(POBJGPU, struct ConfidentialCompute *); + void (*__confComputeInitMissing__)(POBJGPU, struct ConfidentialCompute *); + NV_STATUS (*__confComputeStatePreInitUnlocked__)(POBJGPU, struct ConfidentialCompute *); + NvBool (*__confComputeIsPresent__)(POBJGPU, struct ConfidentialCompute *); + NvBool PDB_PROP_CONFCOMPUTE_ENABLED; + NvBool PDB_PROP_CONFCOMPUTE_CC_FEATURE_ENABLED; + NvBool PDB_PROP_CONFCOMPUTE_APM_FEATURE_ENABLED; + NvBool PDB_PROP_CONFCOMPUTE_DEVTOOLS_MODE_ENABLED; + NvBool PDB_PROP_CONFCOMPUTE_ENABLE_EARLY_INIT; + NvBool PDB_PROP_CONFCOMPUTE_GPUS_READY_CHECK_ENABLED; + NvBool PDB_PROP_CONFCOMPUTE_SPDM_ENABLED; + NvBool PDB_PROP_CONFCOMPUTE_ENCRYPT_READY; + NvBool PDB_PROP_CONFCOMPUTE_ENCRYPT_ENABLED; + NvU32 gspProxyRegkeys; + struct Spdm *pSpdm; + NV2080_CTRL_INTERNAL_CONF_COMPUTE_GET_STATIC_INFO_PARAMS ccStaticInfo; + struct ccslContext_t *pRpcCcslCtx; + struct ccslContext_t *pDmaCcslCtx; + struct ccslContext_t *pNonReplayableFaultCcslCtx; + struct ccslContext_t *pReplayableFaultCcslCtx; + PORT_SPINLOCK *pAesEngineLock; + NvU8 PRIVATE_FIELD(m_exportMasterKey)[32]; + void *PRIVATE_FIELD(m_keySlot); +}; + +#ifndef __NVOC_CLASS_ConfidentialCompute_TYPEDEF__ +#define __NVOC_CLASS_ConfidentialCompute_TYPEDEF__ +typedef struct ConfidentialCompute ConfidentialCompute; +#endif /* __NVOC_CLASS_ConfidentialCompute_TYPEDEF__ */ + +#ifndef __nvoc_class_id_ConfidentialCompute +#define __nvoc_class_id_ConfidentialCompute 0x9798cc +#endif /* __nvoc_class_id_ConfidentialCompute */ + +extern const struct NVOC_CLASS_DEF __nvoc_class_def_ConfidentialCompute; + +#define __staticCast_ConfidentialCompute(pThis) \ + ((pThis)->__nvoc_pbase_ConfidentialCompute) + +#ifdef __nvoc_conf_compute_h_disabled +#define __dynamicCast_ConfidentialCompute(pThis) ((ConfidentialCompute*)NULL) +#else //__nvoc_conf_compute_h_disabled +#define __dynamicCast_ConfidentialCompute(pThis) \ + ((ConfidentialCompute*)__nvoc_dynamicCast(staticCast((pThis), Dynamic), classInfo(ConfidentialCompute))) +#endif //__nvoc_conf_compute_h_disabled + +#define PDB_PROP_CONFCOMPUTE_ENCRYPT_ENABLED_BASE_CAST +#define PDB_PROP_CONFCOMPUTE_ENCRYPT_ENABLED_BASE_NAME PDB_PROP_CONFCOMPUTE_ENCRYPT_ENABLED +#define PDB_PROP_CONFCOMPUTE_APM_FEATURE_ENABLED_BASE_CAST +#define PDB_PROP_CONFCOMPUTE_APM_FEATURE_ENABLED_BASE_NAME PDB_PROP_CONFCOMPUTE_APM_FEATURE_ENABLED +#define PDB_PROP_CONFCOMPUTE_IS_MISSING_BASE_CAST __nvoc_base_OBJENGSTATE. +#define PDB_PROP_CONFCOMPUTE_IS_MISSING_BASE_NAME PDB_PROP_ENGSTATE_IS_MISSING +#define PDB_PROP_CONFCOMPUTE_ENABLE_EARLY_INIT_BASE_CAST +#define PDB_PROP_CONFCOMPUTE_ENABLE_EARLY_INIT_BASE_NAME PDB_PROP_CONFCOMPUTE_ENABLE_EARLY_INIT +#define PDB_PROP_CONFCOMPUTE_ENCRYPT_READY_BASE_CAST +#define PDB_PROP_CONFCOMPUTE_ENCRYPT_READY_BASE_NAME PDB_PROP_CONFCOMPUTE_ENCRYPT_READY +#define PDB_PROP_CONFCOMPUTE_GPUS_READY_CHECK_ENABLED_BASE_CAST +#define PDB_PROP_CONFCOMPUTE_GPUS_READY_CHECK_ENABLED_BASE_NAME PDB_PROP_CONFCOMPUTE_GPUS_READY_CHECK_ENABLED +#define PDB_PROP_CONFCOMPUTE_ENABLED_BASE_CAST +#define PDB_PROP_CONFCOMPUTE_ENABLED_BASE_NAME PDB_PROP_CONFCOMPUTE_ENABLED +#define PDB_PROP_CONFCOMPUTE_CC_FEATURE_ENABLED_BASE_CAST +#define PDB_PROP_CONFCOMPUTE_CC_FEATURE_ENABLED_BASE_NAME PDB_PROP_CONFCOMPUTE_CC_FEATURE_ENABLED +#define PDB_PROP_CONFCOMPUTE_DEVTOOLS_MODE_ENABLED_BASE_CAST +#define PDB_PROP_CONFCOMPUTE_DEVTOOLS_MODE_ENABLED_BASE_NAME PDB_PROP_CONFCOMPUTE_DEVTOOLS_MODE_ENABLED +#define PDB_PROP_CONFCOMPUTE_SPDM_ENABLED_BASE_CAST +#define PDB_PROP_CONFCOMPUTE_SPDM_ENABLED_BASE_NAME PDB_PROP_CONFCOMPUTE_SPDM_ENABLED + +NV_STATUS __nvoc_objCreateDynamic_ConfidentialCompute(ConfidentialCompute**, Dynamic*, NvU32, va_list); + +NV_STATUS __nvoc_objCreate_ConfidentialCompute(ConfidentialCompute**, Dynamic*, NvU32); +#define __objCreate_ConfidentialCompute(ppNewObj, pParent, createFlags) \ + __nvoc_objCreate_ConfidentialCompute((ppNewObj), staticCast((pParent), Dynamic), (createFlags)) + +#define confComputeConstructEngine(pGpu, pConfCompute, engDesc) confComputeConstructEngine_DISPATCH(pGpu, pConfCompute, engDesc) +#define confComputeStatePreInitLocked(pGpu, pConfCompute) confComputeStatePreInitLocked_DISPATCH(pGpu, pConfCompute) +#define confComputeStatePreInitLocked_HAL(pGpu, pConfCompute) confComputeStatePreInitLocked_DISPATCH(pGpu, pConfCompute) +#define confComputeStateInitLocked(pGpu, pConfCompute) confComputeStateInitLocked_DISPATCH(pGpu, pConfCompute) +#define confComputeStatePostLoad(pGpu, pConfCompute, flags) confComputeStatePostLoad_DISPATCH(pGpu, pConfCompute, flags) +#define confComputeStatePostLoad_HAL(pGpu, pConfCompute, flags) confComputeStatePostLoad_DISPATCH(pGpu, pConfCompute, flags) +#define confComputeStatePreUnload(pGpu, pConfCompute, flags) confComputeStatePreUnload_DISPATCH(pGpu, pConfCompute, flags) +#define confComputeStatePreUnload_HAL(pGpu, pConfCompute, flags) confComputeStatePreUnload_DISPATCH(pGpu, pConfCompute, flags) +#define confComputeStateDestroy(pGpu, pConfCompute) confComputeStateDestroy_DISPATCH(pGpu, pConfCompute) +#define confComputeStateDestroy_HAL(pGpu, pConfCompute) confComputeStateDestroy_DISPATCH(pGpu, pConfCompute) +#define confComputeKeyStoreRetrieveViaChannel(pConfCompute, pKernelChannel, rotateOperation, includeSecrets, keyMaterialBundle) confComputeKeyStoreRetrieveViaChannel_DISPATCH(pConfCompute, pKernelChannel, rotateOperation, includeSecrets, keyMaterialBundle) +#define confComputeKeyStoreRetrieveViaChannel_HAL(pConfCompute, pKernelChannel, rotateOperation, includeSecrets, keyMaterialBundle) confComputeKeyStoreRetrieveViaChannel_DISPATCH(pConfCompute, pKernelChannel, rotateOperation, includeSecrets, keyMaterialBundle) +#define confComputeKeyStoreRetrieveViaKeyId(pConfCompute, globalKeyId, rotateOperation, includeSecrets, keyMaterialBundle) confComputeKeyStoreRetrieveViaKeyId_DISPATCH(pConfCompute, globalKeyId, rotateOperation, includeSecrets, keyMaterialBundle) +#define confComputeKeyStoreRetrieveViaKeyId_HAL(pConfCompute, globalKeyId, rotateOperation, includeSecrets, keyMaterialBundle) confComputeKeyStoreRetrieveViaKeyId_DISPATCH(pConfCompute, globalKeyId, rotateOperation, includeSecrets, keyMaterialBundle) +#define confComputeDeriveSecrets(pConfCompute, engine) confComputeDeriveSecrets_DISPATCH(pConfCompute, engine) +#define confComputeDeriveSecrets_HAL(pConfCompute, engine) confComputeDeriveSecrets_DISPATCH(pConfCompute, engine) +#define confComputeIsSpdmEnabled(pGpu, pConfCompute) confComputeIsSpdmEnabled_DISPATCH(pGpu, pConfCompute) +#define confComputeIsSpdmEnabled_HAL(pGpu, pConfCompute) confComputeIsSpdmEnabled_DISPATCH(pGpu, pConfCompute) +#define confComputeIsDebugModeEnabled(pGpu, pConfCompute) confComputeIsDebugModeEnabled_DISPATCH(pGpu, pConfCompute) +#define confComputeIsDebugModeEnabled_HAL(pGpu, pConfCompute) confComputeIsDebugModeEnabled_DISPATCH(pGpu, pConfCompute) +#define confComputeIsGpuCcCapable(pGpu, pConfCompute) confComputeIsGpuCcCapable_DISPATCH(pGpu, pConfCompute) +#define confComputeIsGpuCcCapable_HAL(pGpu, pConfCompute) confComputeIsGpuCcCapable_DISPATCH(pGpu, pConfCompute) +#define confComputeKeyStoreDepositIvMask(pConfCompute, globalKeyId, ivMask) confComputeKeyStoreDepositIvMask_DISPATCH(pConfCompute, globalKeyId, ivMask) +#define confComputeKeyStoreDepositIvMask_HAL(pConfCompute, globalKeyId, ivMask) confComputeKeyStoreDepositIvMask_DISPATCH(pConfCompute, globalKeyId, ivMask) +#define confComputeKeyStoreInit(pConfCompute) confComputeKeyStoreInit_DISPATCH(pConfCompute) +#define confComputeKeyStoreInit_HAL(pConfCompute) confComputeKeyStoreInit_DISPATCH(pConfCompute) +#define confComputeKeyStoreDeinit(pConfCompute) confComputeKeyStoreDeinit_DISPATCH(pConfCompute) +#define confComputeKeyStoreDeinit_HAL(pConfCompute) confComputeKeyStoreDeinit_DISPATCH(pConfCompute) +#define confComputeKeyStoreGetExportMasterKey(pConfCompute) confComputeKeyStoreGetExportMasterKey_DISPATCH(pConfCompute) +#define confComputeKeyStoreGetExportMasterKey_HAL(pConfCompute) confComputeKeyStoreGetExportMasterKey_DISPATCH(pConfCompute) +#define confComputeKeyStoreDeriveKey(pConfCompute, globalKeyId) confComputeKeyStoreDeriveKey_DISPATCH(pConfCompute, globalKeyId) +#define confComputeKeyStoreDeriveKey_HAL(pConfCompute, globalKeyId) confComputeKeyStoreDeriveKey_DISPATCH(pConfCompute, globalKeyId) +#define confComputeKeyStoreClearExportMasterKey(pConfCompute) confComputeKeyStoreClearExportMasterKey_DISPATCH(pConfCompute) +#define confComputeKeyStoreClearExportMasterKey_HAL(pConfCompute) confComputeKeyStoreClearExportMasterKey_DISPATCH(pConfCompute) +#define confComputeKeyStoreUpdateKey(pConfCompute, globalKeyId) confComputeKeyStoreUpdateKey_DISPATCH(pConfCompute, globalKeyId) +#define confComputeKeyStoreUpdateKey_HAL(pConfCompute, globalKeyId) confComputeKeyStoreUpdateKey_DISPATCH(pConfCompute, globalKeyId) +#define confComputeStateLoad(pGpu, pEngstate, arg0) confComputeStateLoad_DISPATCH(pGpu, pEngstate, arg0) +#define confComputeStateUnload(pGpu, pEngstate, arg0) confComputeStateUnload_DISPATCH(pGpu, pEngstate, arg0) +#define confComputeStatePreLoad(pGpu, pEngstate, arg0) confComputeStatePreLoad_DISPATCH(pGpu, pEngstate, arg0) +#define confComputeStatePostUnload(pGpu, pEngstate, arg0) confComputeStatePostUnload_DISPATCH(pGpu, pEngstate, arg0) +#define confComputeStateInitUnlocked(pGpu, pEngstate) confComputeStateInitUnlocked_DISPATCH(pGpu, pEngstate) +#define confComputeInitMissing(pGpu, pEngstate) confComputeInitMissing_DISPATCH(pGpu, pEngstate) +#define confComputeStatePreInitUnlocked(pGpu, pEngstate) confComputeStatePreInitUnlocked_DISPATCH(pGpu, pEngstate) +#define confComputeIsPresent(pGpu, pEngstate) confComputeIsPresent_DISPATCH(pGpu, pEngstate) +static inline NV_STATUS confComputeEarlyInit_56cd7a(struct OBJGPU *pGpu, struct ConfidentialCompute *pConfCompute) { + return NV_OK; +} + + +#ifdef __nvoc_conf_compute_h_disabled +static inline NV_STATUS confComputeEarlyInit(struct OBJGPU *pGpu, struct ConfidentialCompute *pConfCompute) { + NV_ASSERT_FAILED_PRECOMP("ConfidentialCompute was disabled!"); + return NV_ERR_NOT_SUPPORTED; +} +#else //__nvoc_conf_compute_h_disabled +#define confComputeEarlyInit(pGpu, pConfCompute) confComputeEarlyInit_56cd7a(pGpu, pConfCompute) +#endif //__nvoc_conf_compute_h_disabled + +#define confComputeEarlyInit_HAL(pGpu, pConfCompute) confComputeEarlyInit(pGpu, pConfCompute) + +NV_STATUS confComputeStartEncryption_KERNEL(struct OBJGPU *pGpu, struct ConfidentialCompute *pConfCompute); + + +#ifdef __nvoc_conf_compute_h_disabled +static inline NV_STATUS confComputeStartEncryption(struct OBJGPU *pGpu, struct ConfidentialCompute *pConfCompute) { + NV_ASSERT_FAILED_PRECOMP("ConfidentialCompute was disabled!"); + return NV_ERR_NOT_SUPPORTED; +} +#else //__nvoc_conf_compute_h_disabled +#define confComputeStartEncryption(pGpu, pConfCompute) confComputeStartEncryption_KERNEL(pGpu, pConfCompute) +#endif //__nvoc_conf_compute_h_disabled + +#define confComputeStartEncryption_HAL(pGpu, pConfCompute) confComputeStartEncryption(pGpu, pConfCompute) + +NV_STATUS confComputeStopEncryption_KERNEL(struct OBJGPU *pGpu, struct ConfidentialCompute *pConfCompute); + + +#ifdef __nvoc_conf_compute_h_disabled +static inline NV_STATUS confComputeStopEncryption(struct OBJGPU *pGpu, struct ConfidentialCompute *pConfCompute) { + NV_ASSERT_FAILED_PRECOMP("ConfidentialCompute was disabled!"); + return NV_ERR_NOT_SUPPORTED; +} +#else //__nvoc_conf_compute_h_disabled +#define confComputeStopEncryption(pGpu, pConfCompute) confComputeStopEncryption_KERNEL(pGpu, pConfCompute) +#endif //__nvoc_conf_compute_h_disabled + +#define confComputeStopEncryption_HAL(pGpu, pConfCompute) confComputeStopEncryption(pGpu, pConfCompute) + +NV_STATUS confComputeEstablishSpdmSessionAndKeys_KERNEL(struct OBJGPU *pGpu, struct ConfidentialCompute *pConfCompute); + + +#ifdef __nvoc_conf_compute_h_disabled +static inline NV_STATUS confComputeEstablishSpdmSessionAndKeys(struct OBJGPU *pGpu, struct ConfidentialCompute *pConfCompute) { + NV_ASSERT_FAILED_PRECOMP("ConfidentialCompute was disabled!"); + return NV_ERR_NOT_SUPPORTED; +} +#else //__nvoc_conf_compute_h_disabled +#define confComputeEstablishSpdmSessionAndKeys(pGpu, pConfCompute) confComputeEstablishSpdmSessionAndKeys_KERNEL(pGpu, pConfCompute) +#endif //__nvoc_conf_compute_h_disabled + +#define confComputeEstablishSpdmSessionAndKeys_HAL(pGpu, pConfCompute) confComputeEstablishSpdmSessionAndKeys(pGpu, pConfCompute) + +NV_STATUS confComputeConstructEngine_IMPL(struct OBJGPU *pGpu, struct ConfidentialCompute *pConfCompute, ENGDESCRIPTOR engDesc); + +static inline NV_STATUS confComputeConstructEngine_DISPATCH(struct OBJGPU *pGpu, struct ConfidentialCompute *pConfCompute, ENGDESCRIPTOR engDesc) { + return pConfCompute->__confComputeConstructEngine__(pGpu, pConfCompute, engDesc); +} + +NV_STATUS confComputeStatePreInitLocked_IMPL(struct OBJGPU *pGpu, struct ConfidentialCompute *pConfCompute); + +static inline NV_STATUS confComputeStatePreInitLocked_DISPATCH(struct OBJGPU *pGpu, struct ConfidentialCompute *pConfCompute) { + return pConfCompute->__confComputeStatePreInitLocked__(pGpu, pConfCompute); +} + +NV_STATUS confComputeStateInitLocked_IMPL(struct OBJGPU *pGpu, struct ConfidentialCompute *pConfCompute); + +static inline NV_STATUS confComputeStateInitLocked_DISPATCH(struct OBJGPU *pGpu, struct ConfidentialCompute *pConfCompute) { + return pConfCompute->__confComputeStateInitLocked__(pGpu, pConfCompute); +} + +NV_STATUS confComputeStatePostLoad_IMPL(struct OBJGPU *pGpu, struct ConfidentialCompute *pConfCompute, NvU32 flags); + +static inline NV_STATUS confComputeStatePostLoad_DISPATCH(struct OBJGPU *pGpu, struct ConfidentialCompute *pConfCompute, NvU32 flags) { + return pConfCompute->__confComputeStatePostLoad__(pGpu, pConfCompute, flags); +} + +static inline NV_STATUS confComputeStatePreUnload_56cd7a(struct OBJGPU *pGpu, struct ConfidentialCompute *pConfCompute, NvU32 flags) { + return NV_OK; +} + +static inline NV_STATUS confComputeStatePreUnload_DISPATCH(struct OBJGPU *pGpu, struct ConfidentialCompute *pConfCompute, NvU32 flags) { + return pConfCompute->__confComputeStatePreUnload__(pGpu, pConfCompute, flags); +} + +void confComputeStateDestroy_IMPL(struct OBJGPU *pGpu, struct ConfidentialCompute *pConfCompute); + +static inline void confComputeStateDestroy_DISPATCH(struct OBJGPU *pGpu, struct ConfidentialCompute *pConfCompute) { + pConfCompute->__confComputeStateDestroy__(pGpu, pConfCompute); +} + +NV_STATUS confComputeKeyStoreRetrieveViaChannel_GH100(struct ConfidentialCompute *pConfCompute, struct KernelChannel *pKernelChannel, ROTATE_IV_TYPE rotateOperation, NvBool includeSecrets, CC_KMB *keyMaterialBundle); + +static inline NV_STATUS confComputeKeyStoreRetrieveViaChannel_46f6a7(struct ConfidentialCompute *pConfCompute, struct KernelChannel *pKernelChannel, ROTATE_IV_TYPE rotateOperation, NvBool includeSecrets, CC_KMB *keyMaterialBundle) { + return NV_ERR_NOT_SUPPORTED; +} + +static inline NV_STATUS confComputeKeyStoreRetrieveViaChannel_DISPATCH(struct ConfidentialCompute *pConfCompute, struct KernelChannel *pKernelChannel, ROTATE_IV_TYPE rotateOperation, NvBool includeSecrets, CC_KMB *keyMaterialBundle) { + return pConfCompute->__confComputeKeyStoreRetrieveViaChannel__(pConfCompute, pKernelChannel, rotateOperation, includeSecrets, keyMaterialBundle); +} + +NV_STATUS confComputeKeyStoreRetrieveViaKeyId_GH100(struct ConfidentialCompute *pConfCompute, NvU32 globalKeyId, ROTATE_IV_TYPE rotateOperation, NvBool includeSecrets, CC_KMB *keyMaterialBundle); + +static inline NV_STATUS confComputeKeyStoreRetrieveViaKeyId_46f6a7(struct ConfidentialCompute *pConfCompute, NvU32 globalKeyId, ROTATE_IV_TYPE rotateOperation, NvBool includeSecrets, CC_KMB *keyMaterialBundle) { + return NV_ERR_NOT_SUPPORTED; +} + +static inline NV_STATUS confComputeKeyStoreRetrieveViaKeyId_DISPATCH(struct ConfidentialCompute *pConfCompute, NvU32 globalKeyId, ROTATE_IV_TYPE rotateOperation, NvBool includeSecrets, CC_KMB *keyMaterialBundle) { + return pConfCompute->__confComputeKeyStoreRetrieveViaKeyId__(pConfCompute, globalKeyId, rotateOperation, includeSecrets, keyMaterialBundle); +} + +NV_STATUS confComputeDeriveSecrets_GH100(struct ConfidentialCompute *pConfCompute, NvU32 engine); + +static inline NV_STATUS confComputeDeriveSecrets_46f6a7(struct ConfidentialCompute *pConfCompute, NvU32 engine) { + return NV_ERR_NOT_SUPPORTED; +} + +static inline NV_STATUS confComputeDeriveSecrets_DISPATCH(struct ConfidentialCompute *pConfCompute, NvU32 engine) { + return pConfCompute->__confComputeDeriveSecrets__(pConfCompute, engine); +} + +static inline NvBool confComputeIsSpdmEnabled_cbe027(struct OBJGPU *pGpu, struct ConfidentialCompute *pConfCompute) { + return ((NvBool)(0 == 0)); +} + +static inline NvBool confComputeIsSpdmEnabled_491d52(struct OBJGPU *pGpu, struct ConfidentialCompute *pConfCompute) { + return ((NvBool)(0 != 0)); +} + +static inline NvBool confComputeIsSpdmEnabled_DISPATCH(struct OBJGPU *pGpu, struct ConfidentialCompute *pConfCompute) { + return pConfCompute->__confComputeIsSpdmEnabled__(pGpu, pConfCompute); +} + +NvBool confComputeIsDebugModeEnabled_GH100(struct OBJGPU *pGpu, struct ConfidentialCompute *pConfCompute); + +static inline NvBool confComputeIsDebugModeEnabled_491d52(struct OBJGPU *pGpu, struct ConfidentialCompute *pConfCompute) { + return ((NvBool)(0 != 0)); +} + +static inline NvBool confComputeIsDebugModeEnabled_DISPATCH(struct OBJGPU *pGpu, struct ConfidentialCompute *pConfCompute) { + return pConfCompute->__confComputeIsDebugModeEnabled__(pGpu, pConfCompute); +} + +NvBool confComputeIsGpuCcCapable_GH100(struct OBJGPU *pGpu, struct ConfidentialCompute *pConfCompute); + +static inline NvBool confComputeIsGpuCcCapable_491d52(struct OBJGPU *pGpu, struct ConfidentialCompute *pConfCompute) { + return ((NvBool)(0 != 0)); +} + +static inline NvBool confComputeIsGpuCcCapable_DISPATCH(struct OBJGPU *pGpu, struct ConfidentialCompute *pConfCompute) { + return pConfCompute->__confComputeIsGpuCcCapable__(pGpu, pConfCompute); +} + +void confComputeKeyStoreDepositIvMask_GH100(struct ConfidentialCompute *pConfCompute, NvU32 globalKeyId, void *ivMask); + +static inline void confComputeKeyStoreDepositIvMask_b3696a(struct ConfidentialCompute *pConfCompute, NvU32 globalKeyId, void *ivMask) { + return; +} + +static inline void confComputeKeyStoreDepositIvMask_DISPATCH(struct ConfidentialCompute *pConfCompute, NvU32 globalKeyId, void *ivMask) { + pConfCompute->__confComputeKeyStoreDepositIvMask__(pConfCompute, globalKeyId, ivMask); +} + +NV_STATUS confComputeKeyStoreInit_GH100(struct ConfidentialCompute *pConfCompute); + +static inline NV_STATUS confComputeKeyStoreInit_46f6a7(struct ConfidentialCompute *pConfCompute) { + return NV_ERR_NOT_SUPPORTED; +} + +static inline NV_STATUS confComputeKeyStoreInit_DISPATCH(struct ConfidentialCompute *pConfCompute) { + return pConfCompute->__confComputeKeyStoreInit__(pConfCompute); +} + +void confComputeKeyStoreDeinit_GH100(struct ConfidentialCompute *pConfCompute); + +static inline void confComputeKeyStoreDeinit_b3696a(struct ConfidentialCompute *pConfCompute) { + return; +} + +static inline void confComputeKeyStoreDeinit_DISPATCH(struct ConfidentialCompute *pConfCompute) { + pConfCompute->__confComputeKeyStoreDeinit__(pConfCompute); +} + +void *confComputeKeyStoreGetExportMasterKey_GH100(struct ConfidentialCompute *pConfCompute); + +static inline void *confComputeKeyStoreGetExportMasterKey_fa6e19(struct ConfidentialCompute *pConfCompute) { + return ((void *)0); +} + +static inline void *confComputeKeyStoreGetExportMasterKey_DISPATCH(struct ConfidentialCompute *pConfCompute) { + return pConfCompute->__confComputeKeyStoreGetExportMasterKey__(pConfCompute); +} + +NV_STATUS confComputeKeyStoreDeriveKey_GH100(struct ConfidentialCompute *pConfCompute, NvU32 globalKeyId); + +static inline NV_STATUS confComputeKeyStoreDeriveKey_46f6a7(struct ConfidentialCompute *pConfCompute, NvU32 globalKeyId) { + return NV_ERR_NOT_SUPPORTED; +} + +static inline NV_STATUS confComputeKeyStoreDeriveKey_DISPATCH(struct ConfidentialCompute *pConfCompute, NvU32 globalKeyId) { + return pConfCompute->__confComputeKeyStoreDeriveKey__(pConfCompute, globalKeyId); +} + +void confComputeKeyStoreClearExportMasterKey_GH100(struct ConfidentialCompute *pConfCompute); + +static inline void confComputeKeyStoreClearExportMasterKey_b3696a(struct ConfidentialCompute *pConfCompute) { + return; +} + +static inline void confComputeKeyStoreClearExportMasterKey_DISPATCH(struct ConfidentialCompute *pConfCompute) { + pConfCompute->__confComputeKeyStoreClearExportMasterKey__(pConfCompute); +} + +NV_STATUS confComputeKeyStoreUpdateKey_GH100(struct ConfidentialCompute *pConfCompute, NvU32 globalKeyId); + +static inline NV_STATUS confComputeKeyStoreUpdateKey_46f6a7(struct ConfidentialCompute *pConfCompute, NvU32 globalKeyId) { + return NV_ERR_NOT_SUPPORTED; +} + +static inline NV_STATUS confComputeKeyStoreUpdateKey_DISPATCH(struct ConfidentialCompute *pConfCompute, NvU32 globalKeyId) { + return pConfCompute->__confComputeKeyStoreUpdateKey__(pConfCompute, globalKeyId); +} + +static inline NV_STATUS confComputeStateLoad_DISPATCH(POBJGPU pGpu, struct ConfidentialCompute *pEngstate, NvU32 arg0) { + return pEngstate->__confComputeStateLoad__(pGpu, pEngstate, arg0); +} + +static inline NV_STATUS confComputeStateUnload_DISPATCH(POBJGPU pGpu, struct ConfidentialCompute *pEngstate, NvU32 arg0) { + return pEngstate->__confComputeStateUnload__(pGpu, pEngstate, arg0); +} + +static inline NV_STATUS confComputeStatePreLoad_DISPATCH(POBJGPU pGpu, struct ConfidentialCompute *pEngstate, NvU32 arg0) { + return pEngstate->__confComputeStatePreLoad__(pGpu, pEngstate, arg0); +} + +static inline NV_STATUS confComputeStatePostUnload_DISPATCH(POBJGPU pGpu, struct ConfidentialCompute *pEngstate, NvU32 arg0) { + return pEngstate->__confComputeStatePostUnload__(pGpu, pEngstate, arg0); +} + +static inline NV_STATUS confComputeStateInitUnlocked_DISPATCH(POBJGPU pGpu, struct ConfidentialCompute *pEngstate) { + return pEngstate->__confComputeStateInitUnlocked__(pGpu, pEngstate); +} + +static inline void confComputeInitMissing_DISPATCH(POBJGPU pGpu, struct ConfidentialCompute *pEngstate) { + pEngstate->__confComputeInitMissing__(pGpu, pEngstate); +} + +static inline NV_STATUS confComputeStatePreInitUnlocked_DISPATCH(POBJGPU pGpu, struct ConfidentialCompute *pEngstate) { + return pEngstate->__confComputeStatePreInitUnlocked__(pGpu, pEngstate); +} + +static inline NvBool confComputeIsPresent_DISPATCH(POBJGPU pGpu, struct ConfidentialCompute *pEngstate) { + return pEngstate->__confComputeIsPresent__(pGpu, pEngstate); +} + +NvBool confComputeAcceptClientRequest_IMPL(struct OBJGPU *pGpu, struct ConfidentialCompute *pConfCompute); + +#ifdef __nvoc_conf_compute_h_disabled +static inline NvBool confComputeAcceptClientRequest(struct OBJGPU *pGpu, struct ConfidentialCompute *pConfCompute) { + NV_ASSERT_FAILED_PRECOMP("ConfidentialCompute was disabled!"); + return NV_FALSE; +} +#else //__nvoc_conf_compute_h_disabled +#define confComputeAcceptClientRequest(pGpu, pConfCompute) confComputeAcceptClientRequest_IMPL(pGpu, pConfCompute) +#endif //__nvoc_conf_compute_h_disabled + +#undef PRIVATE_FIELD + +#ifndef NVOC_CONF_COMPUTE_H_PRIVATE_ACCESS_ALLOWED +#undef confComputeKeyStoreInit +NV_STATUS NVOC_PRIVATE_FUNCTION(confComputeKeyStoreInit)(struct ConfidentialCompute *pConfCompute); + +#undef confComputeKeyStoreInit_HAL +NV_STATUS NVOC_PRIVATE_FUNCTION(confComputeKeyStoreInit_HAL)(struct ConfidentialCompute *pConfCompute); + +#undef confComputeKeyStoreDeinit +void NVOC_PRIVATE_FUNCTION(confComputeKeyStoreDeinit)(struct ConfidentialCompute *pConfCompute); + +#undef confComputeKeyStoreDeinit_HAL +void NVOC_PRIVATE_FUNCTION(confComputeKeyStoreDeinit_HAL)(struct ConfidentialCompute *pConfCompute); + +#undef confComputeKeyStoreGetExportMasterKey +void *NVOC_PRIVATE_FUNCTION(confComputeKeyStoreGetExportMasterKey)(struct ConfidentialCompute *pConfCompute); + +#undef confComputeKeyStoreGetExportMasterKey_HAL +void *NVOC_PRIVATE_FUNCTION(confComputeKeyStoreGetExportMasterKey_HAL)(struct ConfidentialCompute *pConfCompute); + +#undef confComputeKeyStoreDeriveKey +NV_STATUS NVOC_PRIVATE_FUNCTION(confComputeKeyStoreDeriveKey)(struct ConfidentialCompute *pConfCompute, NvU32 globalKeyId); + +#undef confComputeKeyStoreDeriveKey_HAL +NV_STATUS NVOC_PRIVATE_FUNCTION(confComputeKeyStoreDeriveKey_HAL)(struct ConfidentialCompute *pConfCompute, NvU32 globalKeyId); + +#undef confComputeKeyStoreClearExportMasterKey +void NVOC_PRIVATE_FUNCTION(confComputeKeyStoreClearExportMasterKey)(struct ConfidentialCompute *pConfCompute); + +#undef confComputeKeyStoreClearExportMasterKey_HAL +void NVOC_PRIVATE_FUNCTION(confComputeKeyStoreClearExportMasterKey_HAL)(struct ConfidentialCompute *pConfCompute); + +#undef confComputeKeyStoreUpdateKey +NV_STATUS NVOC_PRIVATE_FUNCTION(confComputeKeyStoreUpdateKey)(struct ConfidentialCompute *pConfCompute, NvU32 globalKeyId); + +#undef confComputeKeyStoreUpdateKey_HAL +NV_STATUS NVOC_PRIVATE_FUNCTION(confComputeKeyStoreUpdateKey_HAL)(struct ConfidentialCompute *pConfCompute, NvU32 globalKeyId); + +#endif // NVOC_CONF_COMPUTE_H_PRIVATE_ACCESS_ALLOWED + + +// Refactor spdmCtrlSpdmPartition into SPDM module. + +/*! + * @brief spdmCtrlSpdmPartition + * Common function used to call gspCommandPostBlocking based on the platform on which it runs (i.e. vGPU, GSP-RM, Monolithic). + * + * @param[in] pGpu : OBJGPU Pointer + * @param[in] pSpdmPartitionParams : SPDM RPC structure pointer + */ +NV_STATUS spdmCtrlSpdmPartition(struct OBJGPU *pGpu, NV2080_CTRL_INTERNAL_SPDM_PARTITION_PARAMS *pSpdmPartitionParams); + +// spdmCtrlWriteSharedMemory is a common function called from both Physical-RM and Kernel-RM. +// However, SPDM module is disabled on Phyiscal-RM and hence declared in conf_compute.h. + +#endif // CONF_COMPUTE_H + +#ifdef __cplusplus +} // extern "C" +#endif +#endif // _G_CONF_COMPUTE_NVOC_H_ diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/generated/g_console_mem_nvoc.c nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_console_mem_nvoc.c --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/generated/g_console_mem_nvoc.c 2023-10-25 20:26:53.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_console_mem_nvoc.c 2024-03-05 22:18:08.000000000 +0000 @@ -101,60 +101,76 @@ return memCheckMemInterUnmap((struct Memory *)(((unsigned char *)pMemory) + __nvoc_rtti_ConsoleMemory_Memory.offset), bSubdeviceHandleProvided); } -static NV_STATUS __nvoc_thunk_Memory_conmemControl(struct ConsoleMemory *pMemory, CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { - return memControl((struct Memory *)(((unsigned char *)pMemory) + __nvoc_rtti_ConsoleMemory_Memory.offset), pCallContext, pParams); +static NvBool __nvoc_thunk_RmResource_conmemShareCallback(struct ConsoleMemory *pResource, struct RsClient *pInvokingClient, struct RsResourceRef *pParentRef, RS_SHARE_POLICY *pSharePolicy) { + return rmresShareCallback((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_ConsoleMemory_RmResource.offset), pInvokingClient, pParentRef, pSharePolicy); } -static NV_STATUS __nvoc_thunk_Memory_conmemUnmap(struct ConsoleMemory *pMemory, CALL_CONTEXT *pCallContext, RsCpuMapping *pCpuMapping) { - return memUnmap((struct Memory *)(((unsigned char *)pMemory) + __nvoc_rtti_ConsoleMemory_Memory.offset), pCallContext, pCpuMapping); +static NV_STATUS __nvoc_thunk_RsResource_conmemMapTo(struct ConsoleMemory *pResource, RS_RES_MAP_TO_PARAMS *pParams) { + return resMapTo((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_ConsoleMemory_RsResource.offset), pParams); } -static NV_STATUS __nvoc_thunk_Memory_conmemGetMemInterMapParams(struct ConsoleMemory *pMemory, RMRES_MEM_INTER_MAP_PARAMS *pParams) { - return memGetMemInterMapParams((struct Memory *)(((unsigned char *)pMemory) + __nvoc_rtti_ConsoleMemory_Memory.offset), pParams); +static NV_STATUS __nvoc_thunk_Memory_conmemGetMapAddrSpace(struct ConsoleMemory *pMemory, CALL_CONTEXT *pCallContext, NvU32 mapFlags, NV_ADDRESS_SPACE *pAddrSpace) { + return memGetMapAddrSpace((struct Memory *)(((unsigned char *)pMemory) + __nvoc_rtti_ConsoleMemory_Memory.offset), pCallContext, mapFlags, pAddrSpace); } -static NV_STATUS __nvoc_thunk_Memory_conmemGetMemoryMappingDescriptor(struct ConsoleMemory *pMemory, MEMORY_DESCRIPTOR **ppMemDesc) { - return memGetMemoryMappingDescriptor((struct Memory *)(((unsigned char *)pMemory) + __nvoc_rtti_ConsoleMemory_Memory.offset), ppMemDesc); +static NvU32 __nvoc_thunk_RsResource_conmemGetRefCount(struct ConsoleMemory *pResource) { + return resGetRefCount((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_ConsoleMemory_RsResource.offset)); } -static NV_STATUS __nvoc_thunk_Memory_conmemGetMapAddrSpace(struct ConsoleMemory *pMemory, CALL_CONTEXT *pCallContext, NvU32 mapFlags, NV_ADDRESS_SPACE *pAddrSpace) { - return memGetMapAddrSpace((struct Memory *)(((unsigned char *)pMemory) + __nvoc_rtti_ConsoleMemory_Memory.offset), pCallContext, mapFlags, pAddrSpace); +static void __nvoc_thunk_RsResource_conmemAddAdditionalDependants(struct RsClient *pClient, struct ConsoleMemory *pResource, RsResourceRef *pReference) { + resAddAdditionalDependants(pClient, (struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_ConsoleMemory_RsResource.offset), pReference); } -static NvBool __nvoc_thunk_RmResource_conmemShareCallback(struct ConsoleMemory *pResource, struct RsClient *pInvokingClient, struct RsResourceRef *pParentRef, RS_SHARE_POLICY *pSharePolicy) { - return rmresShareCallback((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_ConsoleMemory_RmResource.offset), pInvokingClient, pParentRef, pSharePolicy); +static NV_STATUS __nvoc_thunk_RmResource_conmemControl_Prologue(struct ConsoleMemory *pResource, CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return rmresControl_Prologue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_ConsoleMemory_RmResource.offset), pCallContext, pParams); } -static NV_STATUS __nvoc_thunk_RsResource_conmemControlFilter(struct ConsoleMemory *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { - return resControlFilter((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_ConsoleMemory_RsResource.offset), pCallContext, pParams); +static NvBool __nvoc_thunk_Memory_conmemIsGpuMapAllowed(struct ConsoleMemory *pMemory, struct OBJGPU *pGpu) { + return memIsGpuMapAllowed((struct Memory *)(((unsigned char *)pMemory) + __nvoc_rtti_ConsoleMemory_Memory.offset), pGpu); } -static void __nvoc_thunk_RsResource_conmemAddAdditionalDependants(struct RsClient *pClient, struct ConsoleMemory *pResource, RsResourceRef *pReference) { - resAddAdditionalDependants(pClient, (struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_ConsoleMemory_RsResource.offset), pReference); +static NV_STATUS __nvoc_thunk_RsResource_conmemUnmapFrom(struct ConsoleMemory *pResource, RS_RES_UNMAP_FROM_PARAMS *pParams) { + return resUnmapFrom((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_ConsoleMemory_RsResource.offset), pParams); } -static NvU32 __nvoc_thunk_RsResource_conmemGetRefCount(struct ConsoleMemory *pResource) { - return resGetRefCount((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_ConsoleMemory_RsResource.offset)); +static void __nvoc_thunk_RmResource_conmemControl_Epilogue(struct ConsoleMemory *pResource, CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + rmresControl_Epilogue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_ConsoleMemory_RmResource.offset), pCallContext, pParams); } -static NV_STATUS __nvoc_thunk_RsResource_conmemMapTo(struct ConsoleMemory *pResource, RS_RES_MAP_TO_PARAMS *pParams) { - return resMapTo((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_ConsoleMemory_RsResource.offset), pParams); +static NV_STATUS __nvoc_thunk_RsResource_conmemControlLookup(struct ConsoleMemory *pResource, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams, const struct NVOC_EXPORTED_METHOD_DEF **ppEntry) { + return resControlLookup((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_ConsoleMemory_RsResource.offset), pParams, ppEntry); } -static NV_STATUS __nvoc_thunk_RmResource_conmemControl_Prologue(struct ConsoleMemory *pResource, CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { - return rmresControl_Prologue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_ConsoleMemory_RmResource.offset), pCallContext, pParams); +static NV_STATUS __nvoc_thunk_Memory_conmemControl(struct ConsoleMemory *pMemory, CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return memControl((struct Memory *)(((unsigned char *)pMemory) + __nvoc_rtti_ConsoleMemory_Memory.offset), pCallContext, pParams); } -static NvBool __nvoc_thunk_Memory_conmemIsGpuMapAllowed(struct ConsoleMemory *pMemory, struct OBJGPU *pGpu) { - return memIsGpuMapAllowed((struct Memory *)(((unsigned char *)pMemory) + __nvoc_rtti_ConsoleMemory_Memory.offset), pGpu); +static NV_STATUS __nvoc_thunk_Memory_conmemUnmap(struct ConsoleMemory *pMemory, CALL_CONTEXT *pCallContext, RsCpuMapping *pCpuMapping) { + return memUnmap((struct Memory *)(((unsigned char *)pMemory) + __nvoc_rtti_ConsoleMemory_Memory.offset), pCallContext, pCpuMapping); +} + +static NV_STATUS __nvoc_thunk_Memory_conmemGetMemInterMapParams(struct ConsoleMemory *pMemory, RMRES_MEM_INTER_MAP_PARAMS *pParams) { + return memGetMemInterMapParams((struct Memory *)(((unsigned char *)pMemory) + __nvoc_rtti_ConsoleMemory_Memory.offset), pParams); +} + +static NV_STATUS __nvoc_thunk_Memory_conmemGetMemoryMappingDescriptor(struct ConsoleMemory *pMemory, MEMORY_DESCRIPTOR **ppMemDesc) { + return memGetMemoryMappingDescriptor((struct Memory *)(((unsigned char *)pMemory) + __nvoc_rtti_ConsoleMemory_Memory.offset), ppMemDesc); +} + +static NV_STATUS __nvoc_thunk_RsResource_conmemControlFilter(struct ConsoleMemory *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return resControlFilter((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_ConsoleMemory_RsResource.offset), pCallContext, pParams); +} + +static NV_STATUS __nvoc_thunk_RmResource_conmemControlSerialization_Prologue(struct ConsoleMemory *pResource, CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return rmresControlSerialization_Prologue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_ConsoleMemory_RmResource.offset), pCallContext, pParams); } static NV_STATUS __nvoc_thunk_Memory_conmemIsReady(struct ConsoleMemory *pMemory, NvBool bCopyConstructorContext) { return memIsReady((struct Memory *)(((unsigned char *)pMemory) + __nvoc_rtti_ConsoleMemory_Memory.offset), bCopyConstructorContext); } -static NV_STATUS __nvoc_thunk_Memory_conmemCheckCopyPermissions(struct ConsoleMemory *pMemory, struct OBJGPU *pDstGpu, NvHandle hDstClientNvBool) { - return memCheckCopyPermissions((struct Memory *)(((unsigned char *)pMemory) + __nvoc_rtti_ConsoleMemory_Memory.offset), pDstGpu, hDstClientNvBool); +static NV_STATUS __nvoc_thunk_Memory_conmemCheckCopyPermissions(struct ConsoleMemory *pMemory, struct OBJGPU *pDstGpu, struct Device *pDstDevice) { + return memCheckCopyPermissions((struct Memory *)(((unsigned char *)pMemory) + __nvoc_rtti_ConsoleMemory_Memory.offset), pDstGpu, pDstDevice); } static void __nvoc_thunk_RsResource_conmemPreDestruct(struct ConsoleMemory *pResource) { @@ -165,16 +181,8 @@ return memIsDuplicate((struct Memory *)(((unsigned char *)pMemory) + __nvoc_rtti_ConsoleMemory_Memory.offset), hMemory, pDuplicate); } -static NV_STATUS __nvoc_thunk_RsResource_conmemUnmapFrom(struct ConsoleMemory *pResource, RS_RES_UNMAP_FROM_PARAMS *pParams) { - return resUnmapFrom((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_ConsoleMemory_RsResource.offset), pParams); -} - -static void __nvoc_thunk_RmResource_conmemControl_Epilogue(struct ConsoleMemory *pResource, CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { - rmresControl_Epilogue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_ConsoleMemory_RmResource.offset), pCallContext, pParams); -} - -static NV_STATUS __nvoc_thunk_RsResource_conmemControlLookup(struct ConsoleMemory *pResource, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams, const struct NVOC_EXPORTED_METHOD_DEF **ppEntry) { - return resControlLookup((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_ConsoleMemory_RsResource.offset), pParams, ppEntry); +static void __nvoc_thunk_RmResource_conmemControlSerialization_Epilogue(struct ConsoleMemory *pResource, CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + rmresControlSerialization_Epilogue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_ConsoleMemory_RmResource.offset), pCallContext, pParams); } static NV_STATUS __nvoc_thunk_Memory_conmemMap(struct ConsoleMemory *pMemory, CALL_CONTEXT *pCallContext, struct RS_CPU_MAP_PARAMS *pParams, RsCpuMapping *pCpuMapping) { @@ -229,29 +237,37 @@ pThis->__conmemCheckMemInterUnmap__ = &__nvoc_thunk_Memory_conmemCheckMemInterUnmap; - pThis->__conmemControl__ = &__nvoc_thunk_Memory_conmemControl; + pThis->__conmemShareCallback__ = &__nvoc_thunk_RmResource_conmemShareCallback; - pThis->__conmemUnmap__ = &__nvoc_thunk_Memory_conmemUnmap; + pThis->__conmemMapTo__ = &__nvoc_thunk_RsResource_conmemMapTo; - pThis->__conmemGetMemInterMapParams__ = &__nvoc_thunk_Memory_conmemGetMemInterMapParams; + pThis->__conmemGetMapAddrSpace__ = &__nvoc_thunk_Memory_conmemGetMapAddrSpace; - pThis->__conmemGetMemoryMappingDescriptor__ = &__nvoc_thunk_Memory_conmemGetMemoryMappingDescriptor; + pThis->__conmemGetRefCount__ = &__nvoc_thunk_RsResource_conmemGetRefCount; - pThis->__conmemGetMapAddrSpace__ = &__nvoc_thunk_Memory_conmemGetMapAddrSpace; + pThis->__conmemAddAdditionalDependants__ = &__nvoc_thunk_RsResource_conmemAddAdditionalDependants; - pThis->__conmemShareCallback__ = &__nvoc_thunk_RmResource_conmemShareCallback; + pThis->__conmemControl_Prologue__ = &__nvoc_thunk_RmResource_conmemControl_Prologue; - pThis->__conmemControlFilter__ = &__nvoc_thunk_RsResource_conmemControlFilter; + pThis->__conmemIsGpuMapAllowed__ = &__nvoc_thunk_Memory_conmemIsGpuMapAllowed; - pThis->__conmemAddAdditionalDependants__ = &__nvoc_thunk_RsResource_conmemAddAdditionalDependants; + pThis->__conmemUnmapFrom__ = &__nvoc_thunk_RsResource_conmemUnmapFrom; - pThis->__conmemGetRefCount__ = &__nvoc_thunk_RsResource_conmemGetRefCount; + pThis->__conmemControl_Epilogue__ = &__nvoc_thunk_RmResource_conmemControl_Epilogue; - pThis->__conmemMapTo__ = &__nvoc_thunk_RsResource_conmemMapTo; + pThis->__conmemControlLookup__ = &__nvoc_thunk_RsResource_conmemControlLookup; - pThis->__conmemControl_Prologue__ = &__nvoc_thunk_RmResource_conmemControl_Prologue; + pThis->__conmemControl__ = &__nvoc_thunk_Memory_conmemControl; - pThis->__conmemIsGpuMapAllowed__ = &__nvoc_thunk_Memory_conmemIsGpuMapAllowed; + pThis->__conmemUnmap__ = &__nvoc_thunk_Memory_conmemUnmap; + + pThis->__conmemGetMemInterMapParams__ = &__nvoc_thunk_Memory_conmemGetMemInterMapParams; + + pThis->__conmemGetMemoryMappingDescriptor__ = &__nvoc_thunk_Memory_conmemGetMemoryMappingDescriptor; + + pThis->__conmemControlFilter__ = &__nvoc_thunk_RsResource_conmemControlFilter; + + pThis->__conmemControlSerialization_Prologue__ = &__nvoc_thunk_RmResource_conmemControlSerialization_Prologue; pThis->__conmemIsReady__ = &__nvoc_thunk_Memory_conmemIsReady; @@ -261,11 +277,7 @@ pThis->__conmemIsDuplicate__ = &__nvoc_thunk_Memory_conmemIsDuplicate; - pThis->__conmemUnmapFrom__ = &__nvoc_thunk_RsResource_conmemUnmapFrom; - - pThis->__conmemControl_Epilogue__ = &__nvoc_thunk_RmResource_conmemControl_Epilogue; - - pThis->__conmemControlLookup__ = &__nvoc_thunk_RsResource_conmemControlLookup; + pThis->__conmemControlSerialization_Epilogue__ = &__nvoc_thunk_RmResource_conmemControlSerialization_Epilogue; pThis->__conmemMap__ = &__nvoc_thunk_Memory_conmemMap; @@ -293,13 +305,16 @@ Object *pParentObj; ConsoleMemory *pThis; - pThis = portMemAllocNonPaged(sizeof(ConsoleMemory)); - if (pThis == NULL) return NV_ERR_NO_MEMORY; + status = __nvoc_handleObjCreateMemAlloc(createFlags, sizeof(ConsoleMemory), (void**)&pThis, (void**)ppThis); + if (status != NV_OK) + return status; portMemSet(pThis, 0, sizeof(ConsoleMemory)); __nvoc_initRtti(staticCast(pThis, Dynamic), &__nvoc_class_def_ConsoleMemory); + pThis->__nvoc_base_Memory.__nvoc_base_RmResource.__nvoc_base_RsResource.__nvoc_base_Object.createFlags = createFlags; + if (pParent != NULL && !(createFlags & NVOC_OBJ_CREATE_FLAGS_PARENT_HALSPEC_ONLY)) { pParentObj = dynamicCast(pParent, Object); @@ -315,11 +330,17 @@ if (status != NV_OK) goto __nvoc_objCreate_ConsoleMemory_cleanup; *ppThis = pThis; + return NV_OK; __nvoc_objCreate_ConsoleMemory_cleanup: // do not call destructors here since the constructor already called them - portMemFree(pThis); + if (createFlags & NVOC_OBJ_CREATE_FLAGS_IN_PLACE_CONSTRUCT) + portMemSet(pThis, 0, sizeof(ConsoleMemory)); + else + portMemFree(pThis); + + // coverity[leaked_storage:FALSE] return status; } diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/generated/g_console_mem_nvoc.h nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_console_mem_nvoc.h --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/generated/g_console_mem_nvoc.h 2023-10-25 20:26:53.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_console_mem_nvoc.h 2024-03-05 22:18:08.000000000 +0000 @@ -55,25 +55,27 @@ struct ConsoleMemory *__nvoc_pbase_ConsoleMemory; NvBool (*__conmemCanCopy__)(struct ConsoleMemory *); NV_STATUS (*__conmemCheckMemInterUnmap__)(struct ConsoleMemory *, NvBool); + NvBool (*__conmemShareCallback__)(struct ConsoleMemory *, struct RsClient *, struct RsResourceRef *, RS_SHARE_POLICY *); + NV_STATUS (*__conmemMapTo__)(struct ConsoleMemory *, RS_RES_MAP_TO_PARAMS *); + NV_STATUS (*__conmemGetMapAddrSpace__)(struct ConsoleMemory *, CALL_CONTEXT *, NvU32, NV_ADDRESS_SPACE *); + NvU32 (*__conmemGetRefCount__)(struct ConsoleMemory *); + void (*__conmemAddAdditionalDependants__)(struct RsClient *, struct ConsoleMemory *, RsResourceRef *); + NV_STATUS (*__conmemControl_Prologue__)(struct ConsoleMemory *, CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); + NvBool (*__conmemIsGpuMapAllowed__)(struct ConsoleMemory *, struct OBJGPU *); + NV_STATUS (*__conmemUnmapFrom__)(struct ConsoleMemory *, RS_RES_UNMAP_FROM_PARAMS *); + void (*__conmemControl_Epilogue__)(struct ConsoleMemory *, CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); + NV_STATUS (*__conmemControlLookup__)(struct ConsoleMemory *, struct RS_RES_CONTROL_PARAMS_INTERNAL *, const struct NVOC_EXPORTED_METHOD_DEF **); NV_STATUS (*__conmemControl__)(struct ConsoleMemory *, CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); NV_STATUS (*__conmemUnmap__)(struct ConsoleMemory *, CALL_CONTEXT *, RsCpuMapping *); NV_STATUS (*__conmemGetMemInterMapParams__)(struct ConsoleMemory *, RMRES_MEM_INTER_MAP_PARAMS *); NV_STATUS (*__conmemGetMemoryMappingDescriptor__)(struct ConsoleMemory *, MEMORY_DESCRIPTOR **); - NV_STATUS (*__conmemGetMapAddrSpace__)(struct ConsoleMemory *, CALL_CONTEXT *, NvU32, NV_ADDRESS_SPACE *); - NvBool (*__conmemShareCallback__)(struct ConsoleMemory *, struct RsClient *, struct RsResourceRef *, RS_SHARE_POLICY *); NV_STATUS (*__conmemControlFilter__)(struct ConsoleMemory *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); - void (*__conmemAddAdditionalDependants__)(struct RsClient *, struct ConsoleMemory *, RsResourceRef *); - NvU32 (*__conmemGetRefCount__)(struct ConsoleMemory *); - NV_STATUS (*__conmemMapTo__)(struct ConsoleMemory *, RS_RES_MAP_TO_PARAMS *); - NV_STATUS (*__conmemControl_Prologue__)(struct ConsoleMemory *, CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); - NvBool (*__conmemIsGpuMapAllowed__)(struct ConsoleMemory *, struct OBJGPU *); + NV_STATUS (*__conmemControlSerialization_Prologue__)(struct ConsoleMemory *, CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); NV_STATUS (*__conmemIsReady__)(struct ConsoleMemory *, NvBool); - NV_STATUS (*__conmemCheckCopyPermissions__)(struct ConsoleMemory *, struct OBJGPU *, NvHandle); + NV_STATUS (*__conmemCheckCopyPermissions__)(struct ConsoleMemory *, struct OBJGPU *, struct Device *); void (*__conmemPreDestruct__)(struct ConsoleMemory *); NV_STATUS (*__conmemIsDuplicate__)(struct ConsoleMemory *, NvHandle, NvBool *); - NV_STATUS (*__conmemUnmapFrom__)(struct ConsoleMemory *, RS_RES_UNMAP_FROM_PARAMS *); - void (*__conmemControl_Epilogue__)(struct ConsoleMemory *, CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); - NV_STATUS (*__conmemControlLookup__)(struct ConsoleMemory *, struct RS_RES_CONTROL_PARAMS_INTERNAL *, const struct NVOC_EXPORTED_METHOD_DEF **); + void (*__conmemControlSerialization_Epilogue__)(struct ConsoleMemory *, CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); NV_STATUS (*__conmemMap__)(struct ConsoleMemory *, CALL_CONTEXT *, struct RS_CPU_MAP_PARAMS *, RsCpuMapping *); NvBool (*__conmemAccessCallback__)(struct ConsoleMemory *, struct RsClient *, void *, RsAccessRight); }; @@ -108,25 +110,27 @@ #define conmemCanCopy(pConsoleMemory) conmemCanCopy_DISPATCH(pConsoleMemory) #define conmemCheckMemInterUnmap(pMemory, bSubdeviceHandleProvided) conmemCheckMemInterUnmap_DISPATCH(pMemory, bSubdeviceHandleProvided) +#define conmemShareCallback(pResource, pInvokingClient, pParentRef, pSharePolicy) conmemShareCallback_DISPATCH(pResource, pInvokingClient, pParentRef, pSharePolicy) +#define conmemMapTo(pResource, pParams) conmemMapTo_DISPATCH(pResource, pParams) +#define conmemGetMapAddrSpace(pMemory, pCallContext, mapFlags, pAddrSpace) conmemGetMapAddrSpace_DISPATCH(pMemory, pCallContext, mapFlags, pAddrSpace) +#define conmemGetRefCount(pResource) conmemGetRefCount_DISPATCH(pResource) +#define conmemAddAdditionalDependants(pClient, pResource, pReference) conmemAddAdditionalDependants_DISPATCH(pClient, pResource, pReference) +#define conmemControl_Prologue(pResource, pCallContext, pParams) conmemControl_Prologue_DISPATCH(pResource, pCallContext, pParams) +#define conmemIsGpuMapAllowed(pMemory, pGpu) conmemIsGpuMapAllowed_DISPATCH(pMemory, pGpu) +#define conmemUnmapFrom(pResource, pParams) conmemUnmapFrom_DISPATCH(pResource, pParams) +#define conmemControl_Epilogue(pResource, pCallContext, pParams) conmemControl_Epilogue_DISPATCH(pResource, pCallContext, pParams) +#define conmemControlLookup(pResource, pParams, ppEntry) conmemControlLookup_DISPATCH(pResource, pParams, ppEntry) #define conmemControl(pMemory, pCallContext, pParams) conmemControl_DISPATCH(pMemory, pCallContext, pParams) #define conmemUnmap(pMemory, pCallContext, pCpuMapping) conmemUnmap_DISPATCH(pMemory, pCallContext, pCpuMapping) #define conmemGetMemInterMapParams(pMemory, pParams) conmemGetMemInterMapParams_DISPATCH(pMemory, pParams) #define conmemGetMemoryMappingDescriptor(pMemory, ppMemDesc) conmemGetMemoryMappingDescriptor_DISPATCH(pMemory, ppMemDesc) -#define conmemGetMapAddrSpace(pMemory, pCallContext, mapFlags, pAddrSpace) conmemGetMapAddrSpace_DISPATCH(pMemory, pCallContext, mapFlags, pAddrSpace) -#define conmemShareCallback(pResource, pInvokingClient, pParentRef, pSharePolicy) conmemShareCallback_DISPATCH(pResource, pInvokingClient, pParentRef, pSharePolicy) #define conmemControlFilter(pResource, pCallContext, pParams) conmemControlFilter_DISPATCH(pResource, pCallContext, pParams) -#define conmemAddAdditionalDependants(pClient, pResource, pReference) conmemAddAdditionalDependants_DISPATCH(pClient, pResource, pReference) -#define conmemGetRefCount(pResource) conmemGetRefCount_DISPATCH(pResource) -#define conmemMapTo(pResource, pParams) conmemMapTo_DISPATCH(pResource, pParams) -#define conmemControl_Prologue(pResource, pCallContext, pParams) conmemControl_Prologue_DISPATCH(pResource, pCallContext, pParams) -#define conmemIsGpuMapAllowed(pMemory, pGpu) conmemIsGpuMapAllowed_DISPATCH(pMemory, pGpu) +#define conmemControlSerialization_Prologue(pResource, pCallContext, pParams) conmemControlSerialization_Prologue_DISPATCH(pResource, pCallContext, pParams) #define conmemIsReady(pMemory, bCopyConstructorContext) conmemIsReady_DISPATCH(pMemory, bCopyConstructorContext) -#define conmemCheckCopyPermissions(pMemory, pDstGpu, hDstClientNvBool) conmemCheckCopyPermissions_DISPATCH(pMemory, pDstGpu, hDstClientNvBool) +#define conmemCheckCopyPermissions(pMemory, pDstGpu, pDstDevice) conmemCheckCopyPermissions_DISPATCH(pMemory, pDstGpu, pDstDevice) #define conmemPreDestruct(pResource) conmemPreDestruct_DISPATCH(pResource) #define conmemIsDuplicate(pMemory, hMemory, pDuplicate) conmemIsDuplicate_DISPATCH(pMemory, hMemory, pDuplicate) -#define conmemUnmapFrom(pResource, pParams) conmemUnmapFrom_DISPATCH(pResource, pParams) -#define conmemControl_Epilogue(pResource, pCallContext, pParams) conmemControl_Epilogue_DISPATCH(pResource, pCallContext, pParams) -#define conmemControlLookup(pResource, pParams, ppEntry) conmemControlLookup_DISPATCH(pResource, pParams, ppEntry) +#define conmemControlSerialization_Epilogue(pResource, pCallContext, pParams) conmemControlSerialization_Epilogue_DISPATCH(pResource, pCallContext, pParams) #define conmemMap(pMemory, pCallContext, pParams, pCpuMapping) conmemMap_DISPATCH(pMemory, pCallContext, pParams, pCpuMapping) #define conmemAccessCallback(pResource, pInvokingClient, pAllocParams, accessRight) conmemAccessCallback_DISPATCH(pResource, pInvokingClient, pAllocParams, accessRight) NvBool conmemCanCopy_IMPL(struct ConsoleMemory *pConsoleMemory); @@ -139,60 +143,76 @@ return pMemory->__conmemCheckMemInterUnmap__(pMemory, bSubdeviceHandleProvided); } -static inline NV_STATUS conmemControl_DISPATCH(struct ConsoleMemory *pMemory, CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { - return pMemory->__conmemControl__(pMemory, pCallContext, pParams); +static inline NvBool conmemShareCallback_DISPATCH(struct ConsoleMemory *pResource, struct RsClient *pInvokingClient, struct RsResourceRef *pParentRef, RS_SHARE_POLICY *pSharePolicy) { + return pResource->__conmemShareCallback__(pResource, pInvokingClient, pParentRef, pSharePolicy); } -static inline NV_STATUS conmemUnmap_DISPATCH(struct ConsoleMemory *pMemory, CALL_CONTEXT *pCallContext, RsCpuMapping *pCpuMapping) { - return pMemory->__conmemUnmap__(pMemory, pCallContext, pCpuMapping); +static inline NV_STATUS conmemMapTo_DISPATCH(struct ConsoleMemory *pResource, RS_RES_MAP_TO_PARAMS *pParams) { + return pResource->__conmemMapTo__(pResource, pParams); } -static inline NV_STATUS conmemGetMemInterMapParams_DISPATCH(struct ConsoleMemory *pMemory, RMRES_MEM_INTER_MAP_PARAMS *pParams) { - return pMemory->__conmemGetMemInterMapParams__(pMemory, pParams); +static inline NV_STATUS conmemGetMapAddrSpace_DISPATCH(struct ConsoleMemory *pMemory, CALL_CONTEXT *pCallContext, NvU32 mapFlags, NV_ADDRESS_SPACE *pAddrSpace) { + return pMemory->__conmemGetMapAddrSpace__(pMemory, pCallContext, mapFlags, pAddrSpace); } -static inline NV_STATUS conmemGetMemoryMappingDescriptor_DISPATCH(struct ConsoleMemory *pMemory, MEMORY_DESCRIPTOR **ppMemDesc) { - return pMemory->__conmemGetMemoryMappingDescriptor__(pMemory, ppMemDesc); +static inline NvU32 conmemGetRefCount_DISPATCH(struct ConsoleMemory *pResource) { + return pResource->__conmemGetRefCount__(pResource); } -static inline NV_STATUS conmemGetMapAddrSpace_DISPATCH(struct ConsoleMemory *pMemory, CALL_CONTEXT *pCallContext, NvU32 mapFlags, NV_ADDRESS_SPACE *pAddrSpace) { - return pMemory->__conmemGetMapAddrSpace__(pMemory, pCallContext, mapFlags, pAddrSpace); +static inline void conmemAddAdditionalDependants_DISPATCH(struct RsClient *pClient, struct ConsoleMemory *pResource, RsResourceRef *pReference) { + pResource->__conmemAddAdditionalDependants__(pClient, pResource, pReference); } -static inline NvBool conmemShareCallback_DISPATCH(struct ConsoleMemory *pResource, struct RsClient *pInvokingClient, struct RsResourceRef *pParentRef, RS_SHARE_POLICY *pSharePolicy) { - return pResource->__conmemShareCallback__(pResource, pInvokingClient, pParentRef, pSharePolicy); +static inline NV_STATUS conmemControl_Prologue_DISPATCH(struct ConsoleMemory *pResource, CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return pResource->__conmemControl_Prologue__(pResource, pCallContext, pParams); } -static inline NV_STATUS conmemControlFilter_DISPATCH(struct ConsoleMemory *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { - return pResource->__conmemControlFilter__(pResource, pCallContext, pParams); +static inline NvBool conmemIsGpuMapAllowed_DISPATCH(struct ConsoleMemory *pMemory, struct OBJGPU *pGpu) { + return pMemory->__conmemIsGpuMapAllowed__(pMemory, pGpu); } -static inline void conmemAddAdditionalDependants_DISPATCH(struct RsClient *pClient, struct ConsoleMemory *pResource, RsResourceRef *pReference) { - pResource->__conmemAddAdditionalDependants__(pClient, pResource, pReference); +static inline NV_STATUS conmemUnmapFrom_DISPATCH(struct ConsoleMemory *pResource, RS_RES_UNMAP_FROM_PARAMS *pParams) { + return pResource->__conmemUnmapFrom__(pResource, pParams); } -static inline NvU32 conmemGetRefCount_DISPATCH(struct ConsoleMemory *pResource) { - return pResource->__conmemGetRefCount__(pResource); +static inline void conmemControl_Epilogue_DISPATCH(struct ConsoleMemory *pResource, CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + pResource->__conmemControl_Epilogue__(pResource, pCallContext, pParams); } -static inline NV_STATUS conmemMapTo_DISPATCH(struct ConsoleMemory *pResource, RS_RES_MAP_TO_PARAMS *pParams) { - return pResource->__conmemMapTo__(pResource, pParams); +static inline NV_STATUS conmemControlLookup_DISPATCH(struct ConsoleMemory *pResource, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams, const struct NVOC_EXPORTED_METHOD_DEF **ppEntry) { + return pResource->__conmemControlLookup__(pResource, pParams, ppEntry); } -static inline NV_STATUS conmemControl_Prologue_DISPATCH(struct ConsoleMemory *pResource, CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { - return pResource->__conmemControl_Prologue__(pResource, pCallContext, pParams); +static inline NV_STATUS conmemControl_DISPATCH(struct ConsoleMemory *pMemory, CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return pMemory->__conmemControl__(pMemory, pCallContext, pParams); } -static inline NvBool conmemIsGpuMapAllowed_DISPATCH(struct ConsoleMemory *pMemory, struct OBJGPU *pGpu) { - return pMemory->__conmemIsGpuMapAllowed__(pMemory, pGpu); +static inline NV_STATUS conmemUnmap_DISPATCH(struct ConsoleMemory *pMemory, CALL_CONTEXT *pCallContext, RsCpuMapping *pCpuMapping) { + return pMemory->__conmemUnmap__(pMemory, pCallContext, pCpuMapping); +} + +static inline NV_STATUS conmemGetMemInterMapParams_DISPATCH(struct ConsoleMemory *pMemory, RMRES_MEM_INTER_MAP_PARAMS *pParams) { + return pMemory->__conmemGetMemInterMapParams__(pMemory, pParams); +} + +static inline NV_STATUS conmemGetMemoryMappingDescriptor_DISPATCH(struct ConsoleMemory *pMemory, MEMORY_DESCRIPTOR **ppMemDesc) { + return pMemory->__conmemGetMemoryMappingDescriptor__(pMemory, ppMemDesc); +} + +static inline NV_STATUS conmemControlFilter_DISPATCH(struct ConsoleMemory *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return pResource->__conmemControlFilter__(pResource, pCallContext, pParams); +} + +static inline NV_STATUS conmemControlSerialization_Prologue_DISPATCH(struct ConsoleMemory *pResource, CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return pResource->__conmemControlSerialization_Prologue__(pResource, pCallContext, pParams); } static inline NV_STATUS conmemIsReady_DISPATCH(struct ConsoleMemory *pMemory, NvBool bCopyConstructorContext) { return pMemory->__conmemIsReady__(pMemory, bCopyConstructorContext); } -static inline NV_STATUS conmemCheckCopyPermissions_DISPATCH(struct ConsoleMemory *pMemory, struct OBJGPU *pDstGpu, NvHandle hDstClientNvBool) { - return pMemory->__conmemCheckCopyPermissions__(pMemory, pDstGpu, hDstClientNvBool); +static inline NV_STATUS conmemCheckCopyPermissions_DISPATCH(struct ConsoleMemory *pMemory, struct OBJGPU *pDstGpu, struct Device *pDstDevice) { + return pMemory->__conmemCheckCopyPermissions__(pMemory, pDstGpu, pDstDevice); } static inline void conmemPreDestruct_DISPATCH(struct ConsoleMemory *pResource) { @@ -203,16 +223,8 @@ return pMemory->__conmemIsDuplicate__(pMemory, hMemory, pDuplicate); } -static inline NV_STATUS conmemUnmapFrom_DISPATCH(struct ConsoleMemory *pResource, RS_RES_UNMAP_FROM_PARAMS *pParams) { - return pResource->__conmemUnmapFrom__(pResource, pParams); -} - -static inline void conmemControl_Epilogue_DISPATCH(struct ConsoleMemory *pResource, CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { - pResource->__conmemControl_Epilogue__(pResource, pCallContext, pParams); -} - -static inline NV_STATUS conmemControlLookup_DISPATCH(struct ConsoleMemory *pResource, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams, const struct NVOC_EXPORTED_METHOD_DEF **ppEntry) { - return pResource->__conmemControlLookup__(pResource, pParams, ppEntry); +static inline void conmemControlSerialization_Epilogue_DISPATCH(struct ConsoleMemory *pResource, CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + pResource->__conmemControlSerialization_Epilogue__(pResource, pCallContext, pParams); } static inline NV_STATUS conmemMap_DISPATCH(struct ConsoleMemory *pMemory, CALL_CONTEXT *pCallContext, struct RS_CPU_MAP_PARAMS *pParams, RsCpuMapping *pCpuMapping) { diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/generated/g_context_dma_nvoc.c nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_context_dma_nvoc.c --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/generated/g_context_dma_nvoc.c 2023-10-25 20:26:53.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_context_dma_nvoc.c 2024-03-05 22:18:09.000000000 +0000 @@ -122,48 +122,60 @@ return rmresAccessCallback((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_ContextDma_RmResource.offset), pInvokingClient, pAllocParams, accessRight); } -static NV_STATUS __nvoc_thunk_RmResource_ctxdmaGetMemInterMapParams(struct ContextDma *pRmResource, RMRES_MEM_INTER_MAP_PARAMS *pParams) { - return rmresGetMemInterMapParams((struct RmResource *)(((unsigned char *)pRmResource) + __nvoc_rtti_ContextDma_RmResource.offset), pParams); +static void __nvoc_thunk_Notifier_ctxdmaSetNotificationShare(struct ContextDma *pNotifier, struct NotifShare *pNotifShare) { + notifySetNotificationShare((struct Notifier *)(((unsigned char *)pNotifier) + __nvoc_rtti_ContextDma_Notifier.offset), pNotifShare); } -static NV_STATUS __nvoc_thunk_RmResource_ctxdmaGetMemoryMappingDescriptor(struct ContextDma *pRmResource, struct MEMORY_DESCRIPTOR **ppMemDesc) { - return rmresGetMemoryMappingDescriptor((struct RmResource *)(((unsigned char *)pRmResource) + __nvoc_rtti_ContextDma_RmResource.offset), ppMemDesc); +static NvU32 __nvoc_thunk_RsResource_ctxdmaGetRefCount(struct ContextDma *pResource) { + return resGetRefCount((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_ContextDma_RsResource.offset)); } -static void __nvoc_thunk_Notifier_ctxdmaSetNotificationShare(struct ContextDma *pNotifier, struct NotifShare *pNotifShare) { - notifySetNotificationShare((struct Notifier *)(((unsigned char *)pNotifier) + __nvoc_rtti_ContextDma_Notifier.offset), pNotifShare); +static void __nvoc_thunk_RsResource_ctxdmaAddAdditionalDependants(struct RsClient *pClient, struct ContextDma *pResource, RsResourceRef *pReference) { + resAddAdditionalDependants(pClient, (struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_ContextDma_RsResource.offset), pReference); } -static NV_STATUS __nvoc_thunk_RsResource_ctxdmaControl(struct ContextDma *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { - return resControl((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_ContextDma_RsResource.offset), pCallContext, pParams); +static NV_STATUS __nvoc_thunk_RmResource_ctxdmaControl_Prologue(struct ContextDma *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return rmresControl_Prologue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_ContextDma_RmResource.offset), pCallContext, pParams); } -static NV_STATUS __nvoc_thunk_RsResource_ctxdmaControlFilter(struct ContextDma *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { - return resControlFilter((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_ContextDma_RsResource.offset), pCallContext, pParams); +static void __nvoc_thunk_RmResource_ctxdmaControl_Epilogue(struct ContextDma *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + rmresControl_Epilogue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_ContextDma_RmResource.offset), pCallContext, pParams); } -static NvU32 __nvoc_thunk_RsResource_ctxdmaGetRefCount(struct ContextDma *pResource) { - return resGetRefCount((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_ContextDma_RsResource.offset)); +static NV_STATUS __nvoc_thunk_RsResource_ctxdmaControlLookup(struct ContextDma *pResource, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams, const struct NVOC_EXPORTED_METHOD_DEF **ppEntry) { + return resControlLookup((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_ContextDma_RsResource.offset), pParams, ppEntry); } -static NV_STATUS __nvoc_thunk_Notifier_ctxdmaUnregisterEvent(struct ContextDma *pNotifier, NvHandle hNotifierClient, NvHandle hNotifierResource, NvHandle hEventClient, NvHandle hEvent) { - return notifyUnregisterEvent((struct Notifier *)(((unsigned char *)pNotifier) + __nvoc_rtti_ContextDma_Notifier.offset), hNotifierClient, hNotifierResource, hEventClient, hEvent); +static NV_STATUS __nvoc_thunk_RsResource_ctxdmaControl(struct ContextDma *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return resControl((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_ContextDma_RsResource.offset), pCallContext, pParams); } static NV_STATUS __nvoc_thunk_RsResource_ctxdmaUnmap(struct ContextDma *pResource, struct CALL_CONTEXT *pCallContext, RsCpuMapping *pCpuMapping) { return resUnmap((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_ContextDma_RsResource.offset), pCallContext, pCpuMapping); } -static NvBool __nvoc_thunk_RsResource_ctxdmaCanCopy(struct ContextDma *pResource) { - return resCanCopy((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_ContextDma_RsResource.offset)); +static NV_STATUS __nvoc_thunk_RmResource_ctxdmaGetMemInterMapParams(struct ContextDma *pRmResource, RMRES_MEM_INTER_MAP_PARAMS *pParams) { + return rmresGetMemInterMapParams((struct RmResource *)(((unsigned char *)pRmResource) + __nvoc_rtti_ContextDma_RmResource.offset), pParams); } -static NV_STATUS __nvoc_thunk_RmResource_ctxdmaControl_Prologue(struct ContextDma *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { - return rmresControl_Prologue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_ContextDma_RmResource.offset), pCallContext, pParams); +static NV_STATUS __nvoc_thunk_RmResource_ctxdmaGetMemoryMappingDescriptor(struct ContextDma *pRmResource, struct MEMORY_DESCRIPTOR **ppMemDesc) { + return rmresGetMemoryMappingDescriptor((struct RmResource *)(((unsigned char *)pRmResource) + __nvoc_rtti_ContextDma_RmResource.offset), ppMemDesc); } -static void __nvoc_thunk_RsResource_ctxdmaAddAdditionalDependants(struct RsClient *pClient, struct ContextDma *pResource, RsResourceRef *pReference) { - resAddAdditionalDependants(pClient, (struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_ContextDma_RsResource.offset), pReference); +static NV_STATUS __nvoc_thunk_RsResource_ctxdmaControlFilter(struct ContextDma *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return resControlFilter((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_ContextDma_RsResource.offset), pCallContext, pParams); +} + +static NV_STATUS __nvoc_thunk_Notifier_ctxdmaUnregisterEvent(struct ContextDma *pNotifier, NvHandle hNotifierClient, NvHandle hNotifierResource, NvHandle hEventClient, NvHandle hEvent) { + return notifyUnregisterEvent((struct Notifier *)(((unsigned char *)pNotifier) + __nvoc_rtti_ContextDma_Notifier.offset), hNotifierClient, hNotifierResource, hEventClient, hEvent); +} + +static NV_STATUS __nvoc_thunk_RmResource_ctxdmaControlSerialization_Prologue(struct ContextDma *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return rmresControlSerialization_Prologue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_ContextDma_RmResource.offset), pCallContext, pParams); +} + +static NvBool __nvoc_thunk_RsResource_ctxdmaCanCopy(struct ContextDma *pResource) { + return resCanCopy((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_ContextDma_RsResource.offset)); } static void __nvoc_thunk_RsResource_ctxdmaPreDestruct(struct ContextDma *pResource) { @@ -174,22 +186,18 @@ return resIsDuplicate((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_ContextDma_RsResource.offset), hMemory, pDuplicate); } -static PEVENTNOTIFICATION *__nvoc_thunk_Notifier_ctxdmaGetNotificationListPtr(struct ContextDma *pNotifier) { - return notifyGetNotificationListPtr((struct Notifier *)(((unsigned char *)pNotifier) + __nvoc_rtti_ContextDma_Notifier.offset)); +static void __nvoc_thunk_RmResource_ctxdmaControlSerialization_Epilogue(struct ContextDma *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + rmresControlSerialization_Epilogue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_ContextDma_RmResource.offset), pCallContext, pParams); } -static void __nvoc_thunk_RmResource_ctxdmaControl_Epilogue(struct ContextDma *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { - rmresControl_Epilogue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_ContextDma_RmResource.offset), pCallContext, pParams); +static PEVENTNOTIFICATION *__nvoc_thunk_Notifier_ctxdmaGetNotificationListPtr(struct ContextDma *pNotifier) { + return notifyGetNotificationListPtr((struct Notifier *)(((unsigned char *)pNotifier) + __nvoc_rtti_ContextDma_Notifier.offset)); } static struct NotifShare *__nvoc_thunk_Notifier_ctxdmaGetNotificationShare(struct ContextDma *pNotifier) { return notifyGetNotificationShare((struct Notifier *)(((unsigned char *)pNotifier) + __nvoc_rtti_ContextDma_Notifier.offset)); } -static NV_STATUS __nvoc_thunk_RsResource_ctxdmaControlLookup(struct ContextDma *pResource, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams, const struct NVOC_EXPORTED_METHOD_DEF **ppEntry) { - return resControlLookup((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_ContextDma_RsResource.offset), pParams, ppEntry); -} - static NV_STATUS __nvoc_thunk_RsResource_ctxdmaMap(struct ContextDma *pResource, struct CALL_CONTEXT *pCallContext, RS_CPU_MAP_PARAMS *pParams, RsCpuMapping *pCpuMapping) { return resMap((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_ContextDma_RsResource.offset), pCallContext, pParams, pCpuMapping); } @@ -328,40 +336,44 @@ pThis->__ctxdmaAccessCallback__ = &__nvoc_thunk_RmResource_ctxdmaAccessCallback; - pThis->__ctxdmaGetMemInterMapParams__ = &__nvoc_thunk_RmResource_ctxdmaGetMemInterMapParams; + pThis->__ctxdmaSetNotificationShare__ = &__nvoc_thunk_Notifier_ctxdmaSetNotificationShare; - pThis->__ctxdmaGetMemoryMappingDescriptor__ = &__nvoc_thunk_RmResource_ctxdmaGetMemoryMappingDescriptor; + pThis->__ctxdmaGetRefCount__ = &__nvoc_thunk_RsResource_ctxdmaGetRefCount; - pThis->__ctxdmaSetNotificationShare__ = &__nvoc_thunk_Notifier_ctxdmaSetNotificationShare; + pThis->__ctxdmaAddAdditionalDependants__ = &__nvoc_thunk_RsResource_ctxdmaAddAdditionalDependants; - pThis->__ctxdmaControl__ = &__nvoc_thunk_RsResource_ctxdmaControl; + pThis->__ctxdmaControl_Prologue__ = &__nvoc_thunk_RmResource_ctxdmaControl_Prologue; - pThis->__ctxdmaControlFilter__ = &__nvoc_thunk_RsResource_ctxdmaControlFilter; + pThis->__ctxdmaControl_Epilogue__ = &__nvoc_thunk_RmResource_ctxdmaControl_Epilogue; - pThis->__ctxdmaGetRefCount__ = &__nvoc_thunk_RsResource_ctxdmaGetRefCount; + pThis->__ctxdmaControlLookup__ = &__nvoc_thunk_RsResource_ctxdmaControlLookup; - pThis->__ctxdmaUnregisterEvent__ = &__nvoc_thunk_Notifier_ctxdmaUnregisterEvent; + pThis->__ctxdmaControl__ = &__nvoc_thunk_RsResource_ctxdmaControl; pThis->__ctxdmaUnmap__ = &__nvoc_thunk_RsResource_ctxdmaUnmap; - pThis->__ctxdmaCanCopy__ = &__nvoc_thunk_RsResource_ctxdmaCanCopy; + pThis->__ctxdmaGetMemInterMapParams__ = &__nvoc_thunk_RmResource_ctxdmaGetMemInterMapParams; - pThis->__ctxdmaControl_Prologue__ = &__nvoc_thunk_RmResource_ctxdmaControl_Prologue; + pThis->__ctxdmaGetMemoryMappingDescriptor__ = &__nvoc_thunk_RmResource_ctxdmaGetMemoryMappingDescriptor; - pThis->__ctxdmaAddAdditionalDependants__ = &__nvoc_thunk_RsResource_ctxdmaAddAdditionalDependants; + pThis->__ctxdmaControlFilter__ = &__nvoc_thunk_RsResource_ctxdmaControlFilter; + + pThis->__ctxdmaUnregisterEvent__ = &__nvoc_thunk_Notifier_ctxdmaUnregisterEvent; + + pThis->__ctxdmaControlSerialization_Prologue__ = &__nvoc_thunk_RmResource_ctxdmaControlSerialization_Prologue; + + pThis->__ctxdmaCanCopy__ = &__nvoc_thunk_RsResource_ctxdmaCanCopy; pThis->__ctxdmaPreDestruct__ = &__nvoc_thunk_RsResource_ctxdmaPreDestruct; pThis->__ctxdmaIsDuplicate__ = &__nvoc_thunk_RsResource_ctxdmaIsDuplicate; - pThis->__ctxdmaGetNotificationListPtr__ = &__nvoc_thunk_Notifier_ctxdmaGetNotificationListPtr; + pThis->__ctxdmaControlSerialization_Epilogue__ = &__nvoc_thunk_RmResource_ctxdmaControlSerialization_Epilogue; - pThis->__ctxdmaControl_Epilogue__ = &__nvoc_thunk_RmResource_ctxdmaControl_Epilogue; + pThis->__ctxdmaGetNotificationListPtr__ = &__nvoc_thunk_Notifier_ctxdmaGetNotificationListPtr; pThis->__ctxdmaGetNotificationShare__ = &__nvoc_thunk_Notifier_ctxdmaGetNotificationShare; - pThis->__ctxdmaControlLookup__ = &__nvoc_thunk_RsResource_ctxdmaControlLookup; - pThis->__ctxdmaMap__ = &__nvoc_thunk_RsResource_ctxdmaMap; pThis->__ctxdmaGetOrAllocNotifShare__ = &__nvoc_thunk_Notifier_ctxdmaGetOrAllocNotifShare; @@ -391,13 +403,16 @@ Object *pParentObj; ContextDma *pThis; - pThis = portMemAllocNonPaged(sizeof(ContextDma)); - if (pThis == NULL) return NV_ERR_NO_MEMORY; + status = __nvoc_handleObjCreateMemAlloc(createFlags, sizeof(ContextDma), (void**)&pThis, (void**)ppThis); + if (status != NV_OK) + return status; portMemSet(pThis, 0, sizeof(ContextDma)); __nvoc_initRtti(staticCast(pThis, Dynamic), &__nvoc_class_def_ContextDma); + pThis->__nvoc_base_RmResource.__nvoc_base_RsResource.__nvoc_base_Object.createFlags = createFlags; + if (pParent != NULL && !(createFlags & NVOC_OBJ_CREATE_FLAGS_PARENT_HALSPEC_ONLY)) { pParentObj = dynamicCast(pParent, Object); @@ -413,11 +428,17 @@ if (status != NV_OK) goto __nvoc_objCreate_ContextDma_cleanup; *ppThis = pThis; + return NV_OK; __nvoc_objCreate_ContextDma_cleanup: // do not call destructors here since the constructor already called them - portMemFree(pThis); + if (createFlags & NVOC_OBJ_CREATE_FLAGS_IN_PLACE_CONSTRUCT) + portMemSet(pThis, 0, sizeof(ContextDma)); + else + portMemFree(pThis); + + // coverity[leaked_storage:FALSE] return status; } diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/generated/g_context_dma_nvoc.h nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_context_dma_nvoc.h --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/generated/g_context_dma_nvoc.h 2023-10-25 20:26:53.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_context_dma_nvoc.h 2024-03-05 22:18:09.000000000 +0000 @@ -96,23 +96,25 @@ NvBool (*__ctxdmaShareCallback__)(struct ContextDma *, struct RsClient *, struct RsResourceRef *, RS_SHARE_POLICY *); NV_STATUS (*__ctxdmaCheckMemInterUnmap__)(struct ContextDma *, NvBool); NvBool (*__ctxdmaAccessCallback__)(struct ContextDma *, struct RsClient *, void *, RsAccessRight); - NV_STATUS (*__ctxdmaGetMemInterMapParams__)(struct ContextDma *, RMRES_MEM_INTER_MAP_PARAMS *); - NV_STATUS (*__ctxdmaGetMemoryMappingDescriptor__)(struct ContextDma *, struct MEMORY_DESCRIPTOR **); void (*__ctxdmaSetNotificationShare__)(struct ContextDma *, struct NotifShare *); + NvU32 (*__ctxdmaGetRefCount__)(struct ContextDma *); + void (*__ctxdmaAddAdditionalDependants__)(struct RsClient *, struct ContextDma *, RsResourceRef *); + NV_STATUS (*__ctxdmaControl_Prologue__)(struct ContextDma *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); + void (*__ctxdmaControl_Epilogue__)(struct ContextDma *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); + NV_STATUS (*__ctxdmaControlLookup__)(struct ContextDma *, struct RS_RES_CONTROL_PARAMS_INTERNAL *, const struct NVOC_EXPORTED_METHOD_DEF **); NV_STATUS (*__ctxdmaControl__)(struct ContextDma *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); + NV_STATUS (*__ctxdmaUnmap__)(struct ContextDma *, struct CALL_CONTEXT *, RsCpuMapping *); + NV_STATUS (*__ctxdmaGetMemInterMapParams__)(struct ContextDma *, RMRES_MEM_INTER_MAP_PARAMS *); + NV_STATUS (*__ctxdmaGetMemoryMappingDescriptor__)(struct ContextDma *, struct MEMORY_DESCRIPTOR **); NV_STATUS (*__ctxdmaControlFilter__)(struct ContextDma *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); - NvU32 (*__ctxdmaGetRefCount__)(struct ContextDma *); NV_STATUS (*__ctxdmaUnregisterEvent__)(struct ContextDma *, NvHandle, NvHandle, NvHandle, NvHandle); - NV_STATUS (*__ctxdmaUnmap__)(struct ContextDma *, struct CALL_CONTEXT *, RsCpuMapping *); + NV_STATUS (*__ctxdmaControlSerialization_Prologue__)(struct ContextDma *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); NvBool (*__ctxdmaCanCopy__)(struct ContextDma *); - NV_STATUS (*__ctxdmaControl_Prologue__)(struct ContextDma *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); - void (*__ctxdmaAddAdditionalDependants__)(struct RsClient *, struct ContextDma *, RsResourceRef *); void (*__ctxdmaPreDestruct__)(struct ContextDma *); NV_STATUS (*__ctxdmaIsDuplicate__)(struct ContextDma *, NvHandle, NvBool *); + void (*__ctxdmaControlSerialization_Epilogue__)(struct ContextDma *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); PEVENTNOTIFICATION *(*__ctxdmaGetNotificationListPtr__)(struct ContextDma *); - void (*__ctxdmaControl_Epilogue__)(struct ContextDma *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); struct NotifShare *(*__ctxdmaGetNotificationShare__)(struct ContextDma *); - NV_STATUS (*__ctxdmaControlLookup__)(struct ContextDma *, struct RS_RES_CONTROL_PARAMS_INTERNAL *, const struct NVOC_EXPORTED_METHOD_DEF **); NV_STATUS (*__ctxdmaMap__)(struct ContextDma *, struct CALL_CONTEXT *, RS_CPU_MAP_PARAMS *, RsCpuMapping *); NV_STATUS (*__ctxdmaGetOrAllocNotifShare__)(struct ContextDma *, NvHandle, NvHandle, struct NotifShare **); NvU32 Class; @@ -173,23 +175,25 @@ #define ctxdmaShareCallback(pResource, pInvokingClient, pParentRef, pSharePolicy) ctxdmaShareCallback_DISPATCH(pResource, pInvokingClient, pParentRef, pSharePolicy) #define ctxdmaCheckMemInterUnmap(pRmResource, bSubdeviceHandleProvided) ctxdmaCheckMemInterUnmap_DISPATCH(pRmResource, bSubdeviceHandleProvided) #define ctxdmaAccessCallback(pResource, pInvokingClient, pAllocParams, accessRight) ctxdmaAccessCallback_DISPATCH(pResource, pInvokingClient, pAllocParams, accessRight) -#define ctxdmaGetMemInterMapParams(pRmResource, pParams) ctxdmaGetMemInterMapParams_DISPATCH(pRmResource, pParams) -#define ctxdmaGetMemoryMappingDescriptor(pRmResource, ppMemDesc) ctxdmaGetMemoryMappingDescriptor_DISPATCH(pRmResource, ppMemDesc) #define ctxdmaSetNotificationShare(pNotifier, pNotifShare) ctxdmaSetNotificationShare_DISPATCH(pNotifier, pNotifShare) +#define ctxdmaGetRefCount(pResource) ctxdmaGetRefCount_DISPATCH(pResource) +#define ctxdmaAddAdditionalDependants(pClient, pResource, pReference) ctxdmaAddAdditionalDependants_DISPATCH(pClient, pResource, pReference) +#define ctxdmaControl_Prologue(pResource, pCallContext, pParams) ctxdmaControl_Prologue_DISPATCH(pResource, pCallContext, pParams) +#define ctxdmaControl_Epilogue(pResource, pCallContext, pParams) ctxdmaControl_Epilogue_DISPATCH(pResource, pCallContext, pParams) +#define ctxdmaControlLookup(pResource, pParams, ppEntry) ctxdmaControlLookup_DISPATCH(pResource, pParams, ppEntry) #define ctxdmaControl(pResource, pCallContext, pParams) ctxdmaControl_DISPATCH(pResource, pCallContext, pParams) +#define ctxdmaUnmap(pResource, pCallContext, pCpuMapping) ctxdmaUnmap_DISPATCH(pResource, pCallContext, pCpuMapping) +#define ctxdmaGetMemInterMapParams(pRmResource, pParams) ctxdmaGetMemInterMapParams_DISPATCH(pRmResource, pParams) +#define ctxdmaGetMemoryMappingDescriptor(pRmResource, ppMemDesc) ctxdmaGetMemoryMappingDescriptor_DISPATCH(pRmResource, ppMemDesc) #define ctxdmaControlFilter(pResource, pCallContext, pParams) ctxdmaControlFilter_DISPATCH(pResource, pCallContext, pParams) -#define ctxdmaGetRefCount(pResource) ctxdmaGetRefCount_DISPATCH(pResource) #define ctxdmaUnregisterEvent(pNotifier, hNotifierClient, hNotifierResource, hEventClient, hEvent) ctxdmaUnregisterEvent_DISPATCH(pNotifier, hNotifierClient, hNotifierResource, hEventClient, hEvent) -#define ctxdmaUnmap(pResource, pCallContext, pCpuMapping) ctxdmaUnmap_DISPATCH(pResource, pCallContext, pCpuMapping) +#define ctxdmaControlSerialization_Prologue(pResource, pCallContext, pParams) ctxdmaControlSerialization_Prologue_DISPATCH(pResource, pCallContext, pParams) #define ctxdmaCanCopy(pResource) ctxdmaCanCopy_DISPATCH(pResource) -#define ctxdmaControl_Prologue(pResource, pCallContext, pParams) ctxdmaControl_Prologue_DISPATCH(pResource, pCallContext, pParams) -#define ctxdmaAddAdditionalDependants(pClient, pResource, pReference) ctxdmaAddAdditionalDependants_DISPATCH(pClient, pResource, pReference) #define ctxdmaPreDestruct(pResource) ctxdmaPreDestruct_DISPATCH(pResource) #define ctxdmaIsDuplicate(pResource, hMemory, pDuplicate) ctxdmaIsDuplicate_DISPATCH(pResource, hMemory, pDuplicate) +#define ctxdmaControlSerialization_Epilogue(pResource, pCallContext, pParams) ctxdmaControlSerialization_Epilogue_DISPATCH(pResource, pCallContext, pParams) #define ctxdmaGetNotificationListPtr(pNotifier) ctxdmaGetNotificationListPtr_DISPATCH(pNotifier) -#define ctxdmaControl_Epilogue(pResource, pCallContext, pParams) ctxdmaControl_Epilogue_DISPATCH(pResource, pCallContext, pParams) #define ctxdmaGetNotificationShare(pNotifier) ctxdmaGetNotificationShare_DISPATCH(pNotifier) -#define ctxdmaControlLookup(pResource, pParams, ppEntry) ctxdmaControlLookup_DISPATCH(pResource, pParams, ppEntry) #define ctxdmaMap(pResource, pCallContext, pParams, pCpuMapping) ctxdmaMap_DISPATCH(pResource, pCallContext, pParams, pCpuMapping) #define ctxdmaGetOrAllocNotifShare(pNotifier, hNotifierClient, hNotifierResource, ppNotifShare) ctxdmaGetOrAllocNotifShare_DISPATCH(pNotifier, hNotifierClient, hNotifierResource, ppNotifShare) NV_STATUS ctxdmaValidate_IMPL(struct ContextDma *pContextDma, NvU64 start, NvU64 len); @@ -246,48 +250,60 @@ return pResource->__ctxdmaAccessCallback__(pResource, pInvokingClient, pAllocParams, accessRight); } -static inline NV_STATUS ctxdmaGetMemInterMapParams_DISPATCH(struct ContextDma *pRmResource, RMRES_MEM_INTER_MAP_PARAMS *pParams) { - return pRmResource->__ctxdmaGetMemInterMapParams__(pRmResource, pParams); +static inline void ctxdmaSetNotificationShare_DISPATCH(struct ContextDma *pNotifier, struct NotifShare *pNotifShare) { + pNotifier->__ctxdmaSetNotificationShare__(pNotifier, pNotifShare); } -static inline NV_STATUS ctxdmaGetMemoryMappingDescriptor_DISPATCH(struct ContextDma *pRmResource, struct MEMORY_DESCRIPTOR **ppMemDesc) { - return pRmResource->__ctxdmaGetMemoryMappingDescriptor__(pRmResource, ppMemDesc); +static inline NvU32 ctxdmaGetRefCount_DISPATCH(struct ContextDma *pResource) { + return pResource->__ctxdmaGetRefCount__(pResource); } -static inline void ctxdmaSetNotificationShare_DISPATCH(struct ContextDma *pNotifier, struct NotifShare *pNotifShare) { - pNotifier->__ctxdmaSetNotificationShare__(pNotifier, pNotifShare); +static inline void ctxdmaAddAdditionalDependants_DISPATCH(struct RsClient *pClient, struct ContextDma *pResource, RsResourceRef *pReference) { + pResource->__ctxdmaAddAdditionalDependants__(pClient, pResource, pReference); } -static inline NV_STATUS ctxdmaControl_DISPATCH(struct ContextDma *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { - return pResource->__ctxdmaControl__(pResource, pCallContext, pParams); +static inline NV_STATUS ctxdmaControl_Prologue_DISPATCH(struct ContextDma *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return pResource->__ctxdmaControl_Prologue__(pResource, pCallContext, pParams); } -static inline NV_STATUS ctxdmaControlFilter_DISPATCH(struct ContextDma *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { - return pResource->__ctxdmaControlFilter__(pResource, pCallContext, pParams); +static inline void ctxdmaControl_Epilogue_DISPATCH(struct ContextDma *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + pResource->__ctxdmaControl_Epilogue__(pResource, pCallContext, pParams); } -static inline NvU32 ctxdmaGetRefCount_DISPATCH(struct ContextDma *pResource) { - return pResource->__ctxdmaGetRefCount__(pResource); +static inline NV_STATUS ctxdmaControlLookup_DISPATCH(struct ContextDma *pResource, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams, const struct NVOC_EXPORTED_METHOD_DEF **ppEntry) { + return pResource->__ctxdmaControlLookup__(pResource, pParams, ppEntry); } -static inline NV_STATUS ctxdmaUnregisterEvent_DISPATCH(struct ContextDma *pNotifier, NvHandle hNotifierClient, NvHandle hNotifierResource, NvHandle hEventClient, NvHandle hEvent) { - return pNotifier->__ctxdmaUnregisterEvent__(pNotifier, hNotifierClient, hNotifierResource, hEventClient, hEvent); +static inline NV_STATUS ctxdmaControl_DISPATCH(struct ContextDma *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return pResource->__ctxdmaControl__(pResource, pCallContext, pParams); } static inline NV_STATUS ctxdmaUnmap_DISPATCH(struct ContextDma *pResource, struct CALL_CONTEXT *pCallContext, RsCpuMapping *pCpuMapping) { return pResource->__ctxdmaUnmap__(pResource, pCallContext, pCpuMapping); } -static inline NvBool ctxdmaCanCopy_DISPATCH(struct ContextDma *pResource) { - return pResource->__ctxdmaCanCopy__(pResource); +static inline NV_STATUS ctxdmaGetMemInterMapParams_DISPATCH(struct ContextDma *pRmResource, RMRES_MEM_INTER_MAP_PARAMS *pParams) { + return pRmResource->__ctxdmaGetMemInterMapParams__(pRmResource, pParams); } -static inline NV_STATUS ctxdmaControl_Prologue_DISPATCH(struct ContextDma *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { - return pResource->__ctxdmaControl_Prologue__(pResource, pCallContext, pParams); +static inline NV_STATUS ctxdmaGetMemoryMappingDescriptor_DISPATCH(struct ContextDma *pRmResource, struct MEMORY_DESCRIPTOR **ppMemDesc) { + return pRmResource->__ctxdmaGetMemoryMappingDescriptor__(pRmResource, ppMemDesc); } -static inline void ctxdmaAddAdditionalDependants_DISPATCH(struct RsClient *pClient, struct ContextDma *pResource, RsResourceRef *pReference) { - pResource->__ctxdmaAddAdditionalDependants__(pClient, pResource, pReference); +static inline NV_STATUS ctxdmaControlFilter_DISPATCH(struct ContextDma *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return pResource->__ctxdmaControlFilter__(pResource, pCallContext, pParams); +} + +static inline NV_STATUS ctxdmaUnregisterEvent_DISPATCH(struct ContextDma *pNotifier, NvHandle hNotifierClient, NvHandle hNotifierResource, NvHandle hEventClient, NvHandle hEvent) { + return pNotifier->__ctxdmaUnregisterEvent__(pNotifier, hNotifierClient, hNotifierResource, hEventClient, hEvent); +} + +static inline NV_STATUS ctxdmaControlSerialization_Prologue_DISPATCH(struct ContextDma *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return pResource->__ctxdmaControlSerialization_Prologue__(pResource, pCallContext, pParams); +} + +static inline NvBool ctxdmaCanCopy_DISPATCH(struct ContextDma *pResource) { + return pResource->__ctxdmaCanCopy__(pResource); } static inline void ctxdmaPreDestruct_DISPATCH(struct ContextDma *pResource) { @@ -298,22 +314,18 @@ return pResource->__ctxdmaIsDuplicate__(pResource, hMemory, pDuplicate); } -static inline PEVENTNOTIFICATION *ctxdmaGetNotificationListPtr_DISPATCH(struct ContextDma *pNotifier) { - return pNotifier->__ctxdmaGetNotificationListPtr__(pNotifier); +static inline void ctxdmaControlSerialization_Epilogue_DISPATCH(struct ContextDma *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + pResource->__ctxdmaControlSerialization_Epilogue__(pResource, pCallContext, pParams); } -static inline void ctxdmaControl_Epilogue_DISPATCH(struct ContextDma *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { - pResource->__ctxdmaControl_Epilogue__(pResource, pCallContext, pParams); +static inline PEVENTNOTIFICATION *ctxdmaGetNotificationListPtr_DISPATCH(struct ContextDma *pNotifier) { + return pNotifier->__ctxdmaGetNotificationListPtr__(pNotifier); } static inline struct NotifShare *ctxdmaGetNotificationShare_DISPATCH(struct ContextDma *pNotifier) { return pNotifier->__ctxdmaGetNotificationShare__(pNotifier); } -static inline NV_STATUS ctxdmaControlLookup_DISPATCH(struct ContextDma *pResource, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams, const struct NVOC_EXPORTED_METHOD_DEF **ppEntry) { - return pResource->__ctxdmaControlLookup__(pResource, pParams, ppEntry); -} - static inline NV_STATUS ctxdmaMap_DISPATCH(struct ContextDma *pResource, struct CALL_CONTEXT *pCallContext, RS_CPU_MAP_PARAMS *pParams, RsCpuMapping *pCpuMapping) { return pResource->__ctxdmaMap__(pResource, pCallContext, pParams, pCpuMapping); } diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/generated/g_crashcat_engine_nvoc.c nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_crashcat_engine_nvoc.c --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/generated/g_crashcat_engine_nvoc.c 1970-01-01 00:00:00.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_crashcat_engine_nvoc.c 2024-03-05 22:18:09.000000000 +0000 @@ -0,0 +1,123 @@ +#define NVOC_CRASHCAT_ENGINE_H_PRIVATE_ACCESS_ALLOWED +#include "nvoc/runtime.h" +#include "nvoc/rtti.h" +#include "nvtypes.h" +#include "nvport/nvport.h" +#include "nvport/inline/util_valist.h" +#include "utils/nvassert.h" +#include "g_crashcat_engine_nvoc.h" + +#ifdef DEBUG +char __nvoc_class_id_uniqueness_check_0x654166 = 1; +#endif + +extern const struct NVOC_CLASS_DEF __nvoc_class_def_CrashCatEngine; + +void __nvoc_init_CrashCatEngine(CrashCatEngine*); +void __nvoc_init_funcTable_CrashCatEngine(CrashCatEngine*); +NV_STATUS __nvoc_ctor_CrashCatEngine(CrashCatEngine*); +void __nvoc_init_dataField_CrashCatEngine(CrashCatEngine*); +void __nvoc_dtor_CrashCatEngine(CrashCatEngine*); +extern const struct NVOC_EXPORT_INFO __nvoc_export_info_CrashCatEngine; + +static const struct NVOC_RTTI __nvoc_rtti_CrashCatEngine_CrashCatEngine = { + /*pClassDef=*/ &__nvoc_class_def_CrashCatEngine, + /*dtor=*/ (NVOC_DYNAMIC_DTOR) &__nvoc_dtor_CrashCatEngine, + /*offset=*/ 0, +}; + +static const struct NVOC_CASTINFO __nvoc_castinfo_CrashCatEngine = { + /*numRelatives=*/ 1, + /*relatives=*/ { + &__nvoc_rtti_CrashCatEngine_CrashCatEngine, + }, +}; + +// Not instantiable because it's not derived from class "Object" +// Not instantiable because it's an abstract class with following pure virtual functions: +// crashcatEngineConfigured +// crashcatEngineVprintf +// crashcatEnginePriRead +// crashcatEnginePriWrite +// crashcatEngineMapBufferDescriptor +// crashcatEngineUnmapBufferDescriptor +// crashcatEngineSyncBufferDescriptor +// crashcatEngineGetScratchOffsets +// crashcatEngineGetWFL0Offset +const struct NVOC_CLASS_DEF __nvoc_class_def_CrashCatEngine = +{ + /*classInfo=*/ { + /*size=*/ sizeof(CrashCatEngine), + /*classId=*/ classId(CrashCatEngine), + /*providerId=*/ &__nvoc_rtti_provider, +#if NV_PRINTF_STRINGS_ALLOWED + /*name=*/ "CrashCatEngine", +#endif + }, + /*objCreatefn=*/ (NVOC_DYNAMIC_OBJ_CREATE) NULL, + /*pCastInfo=*/ &__nvoc_castinfo_CrashCatEngine, + /*pExportInfo=*/ &__nvoc_export_info_CrashCatEngine +}; + +const struct NVOC_EXPORT_INFO __nvoc_export_info_CrashCatEngine = +{ + /*numEntries=*/ 0, + /*pExportEntries=*/ 0 +}; + +void __nvoc_dtor_CrashCatEngine(CrashCatEngine *pThis) { + __nvoc_crashcatEngineDestruct(pThis); + PORT_UNREFERENCED_VARIABLE(pThis); +} + +void __nvoc_init_dataField_CrashCatEngine(CrashCatEngine *pThis) { + PORT_UNREFERENCED_VARIABLE(pThis); +} + +NV_STATUS __nvoc_ctor_CrashCatEngine(CrashCatEngine *pThis) { + NV_STATUS status = NV_OK; + __nvoc_init_dataField_CrashCatEngine(pThis); + + status = __nvoc_crashcatEngineConstruct(pThis); + if (status != NV_OK) goto __nvoc_ctor_CrashCatEngine_fail__init; + goto __nvoc_ctor_CrashCatEngine_exit; // Success + +__nvoc_ctor_CrashCatEngine_fail__init: +__nvoc_ctor_CrashCatEngine_exit: + + return status; +} + +static void __nvoc_init_funcTable_CrashCatEngine_1(CrashCatEngine *pThis) { + PORT_UNREFERENCED_VARIABLE(pThis); + + pThis->__crashcatEngineUnload__ = &crashcatEngineUnload_IMPL; + + pThis->__crashcatEngineConfigured__ = NULL; + + pThis->__crashcatEngineVprintf__ = NULL; + + pThis->__crashcatEnginePriRead__ = NULL; + + pThis->__crashcatEnginePriWrite__ = NULL; + + pThis->__crashcatEngineMapBufferDescriptor__ = NULL; + + pThis->__crashcatEngineUnmapBufferDescriptor__ = NULL; + + pThis->__crashcatEngineSyncBufferDescriptor__ = NULL; + + pThis->__crashcatEngineGetScratchOffsets__ = NULL; + + pThis->__crashcatEngineGetWFL0Offset__ = NULL; +} + +void __nvoc_init_funcTable_CrashCatEngine(CrashCatEngine *pThis) { + __nvoc_init_funcTable_CrashCatEngine_1(pThis); +} + +void __nvoc_init_CrashCatEngine(CrashCatEngine *pThis) { + pThis->__nvoc_pbase_CrashCatEngine = pThis; + __nvoc_init_funcTable_CrashCatEngine(pThis); +} + diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/generated/g_crashcat_engine_nvoc.h nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_crashcat_engine_nvoc.h --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/generated/g_crashcat_engine_nvoc.h 1970-01-01 00:00:00.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_crashcat_engine_nvoc.h 2024-03-05 22:18:09.000000000 +0000 @@ -0,0 +1,287 @@ +#ifndef _G_CRASHCAT_ENGINE_NVOC_H_ +#define _G_CRASHCAT_ENGINE_NVOC_H_ +#include "nvoc/runtime.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/* + * SPDX-FileCopyrightText: Copyright (c) 2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#include "g_crashcat_engine_nvoc.h" + +#ifndef CRASHCAT_ENGINE_H +#define CRASHCAT_ENGINE_H + +#include "containers/map.h" +#include "nvoc/object.h" +#include "nvport/inline/util_valist.h" +#include "nv-crashcat.h" + +struct CrashCatReport; + +#ifndef __NVOC_CLASS_CrashCatReport_TYPEDEF__ +#define __NVOC_CLASS_CrashCatReport_TYPEDEF__ +typedef struct CrashCatReport CrashCatReport; +#endif /* __NVOC_CLASS_CrashCatReport_TYPEDEF__ */ + +#ifndef __nvoc_class_id_CrashCatReport +#define __nvoc_class_id_CrashCatReport 0xde4777 +#endif /* __nvoc_class_id_CrashCatReport */ + + +struct CrashCatWayfinder; + +#ifndef __NVOC_CLASS_CrashCatWayfinder_TYPEDEF__ +#define __NVOC_CLASS_CrashCatWayfinder_TYPEDEF__ +typedef struct CrashCatWayfinder CrashCatWayfinder; +#endif /* __NVOC_CLASS_CrashCatWayfinder_TYPEDEF__ */ + +#ifndef __nvoc_class_id_CrashCatWayfinder +#define __nvoc_class_id_CrashCatWayfinder 0x085e32 +#endif /* __nvoc_class_id_CrashCatWayfinder */ + + + +typedef struct { + void *pEngPriv; + void *pMapping; + NvBool bRegistered; + NV_CRASHCAT_MEM_APERTURE aperture; + NvU64 physOffset; + NvLength size; + MapNode registeredBufferMapNode; + MapNode mappedBufferMapNode; +} CrashCatBufferDescriptor; + +MAKE_INTRUSIVE_MAP(CrashCatRegisteredBufferMap, CrashCatBufferDescriptor, registeredBufferMapNode); +MAKE_INTRUSIVE_MAP(CrashCatMappedBufferMap, CrashCatBufferDescriptor, mappedBufferMapNode); + +// Base class for engine-specific accessors - must be implemented by the host codebase. +#ifdef NVOC_CRASHCAT_ENGINE_H_PRIVATE_ACCESS_ALLOWED +#define PRIVATE_FIELD(x) x +#else +#define PRIVATE_FIELD(x) NVOC_PRIVATE_FIELD(x) +#endif +struct CrashCatEngine { + const struct NVOC_RTTI *__nvoc_rtti; + struct CrashCatEngine *__nvoc_pbase_CrashCatEngine; + void (*__crashcatEngineUnload__)(struct CrashCatEngine *); + NvBool (*__crashcatEngineConfigured__)(struct CrashCatEngine *); + void (*__crashcatEngineVprintf__)(struct CrashCatEngine *, NvBool, const char *, va_list); + NvU32 (*__crashcatEnginePriRead__)(struct CrashCatEngine *, NvU32); + void (*__crashcatEnginePriWrite__)(struct CrashCatEngine *, NvU32, NvU32); + void *(*__crashcatEngineMapBufferDescriptor__)(struct CrashCatEngine *, CrashCatBufferDescriptor *); + void (*__crashcatEngineUnmapBufferDescriptor__)(struct CrashCatEngine *, CrashCatBufferDescriptor *); + void (*__crashcatEngineSyncBufferDescriptor__)(struct CrashCatEngine *, CrashCatBufferDescriptor *, NvU32, NvU32); + const NvU32 *(*__crashcatEngineGetScratchOffsets__)(struct CrashCatEngine *, NV_CRASHCAT_SCRATCH_GROUP_ID); + NvU32 (*__crashcatEngineGetWFL0Offset__)(struct CrashCatEngine *); + NvBool PRIVATE_FIELD(bEnabled); + struct CrashCatWayfinder *PRIVATE_FIELD(pWayfinder); + CrashCatRegisteredBufferMap PRIVATE_FIELD(registeredCrashBuffers); + CrashCatMappedBufferMap PRIVATE_FIELD(mappedCrashBuffers); +}; + +#ifndef __NVOC_CLASS_CrashCatEngine_TYPEDEF__ +#define __NVOC_CLASS_CrashCatEngine_TYPEDEF__ +typedef struct CrashCatEngine CrashCatEngine; +#endif /* __NVOC_CLASS_CrashCatEngine_TYPEDEF__ */ + +#ifndef __nvoc_class_id_CrashCatEngine +#define __nvoc_class_id_CrashCatEngine 0x654166 +#endif /* __nvoc_class_id_CrashCatEngine */ + +extern const struct NVOC_CLASS_DEF __nvoc_class_def_CrashCatEngine; + +#define __staticCast_CrashCatEngine(pThis) \ + ((pThis)->__nvoc_pbase_CrashCatEngine) + +#ifdef __nvoc_crashcat_engine_h_disabled +#define __dynamicCast_CrashCatEngine(pThis) ((CrashCatEngine*)NULL) +#else //__nvoc_crashcat_engine_h_disabled +#define __dynamicCast_CrashCatEngine(pThis) \ + ((CrashCatEngine*)__nvoc_dynamicCast(staticCast((pThis), Dynamic), classInfo(CrashCatEngine))) +#endif //__nvoc_crashcat_engine_h_disabled + + +NV_STATUS __nvoc_objCreateDynamic_CrashCatEngine(CrashCatEngine**, Dynamic*, NvU32, va_list); + +NV_STATUS __nvoc_objCreate_CrashCatEngine(CrashCatEngine**, Dynamic*, NvU32); +#define __objCreate_CrashCatEngine(ppNewObj, pParent, createFlags) \ + __nvoc_objCreate_CrashCatEngine((ppNewObj), staticCast((pParent), Dynamic), (createFlags)) + +#define crashcatEngineUnload(arg0) crashcatEngineUnload_DISPATCH(arg0) +#define crashcatEngineConfigured(arg0) crashcatEngineConfigured_DISPATCH(arg0) +#define crashcatEngineVprintf(arg0, bReportStart, fmt, args) crashcatEngineVprintf_DISPATCH(arg0, bReportStart, fmt, args) +#define crashcatEnginePriRead(arg0, offset) crashcatEnginePriRead_DISPATCH(arg0, offset) +#define crashcatEnginePriWrite(arg0, offset, data) crashcatEnginePriWrite_DISPATCH(arg0, offset, data) +#define crashcatEngineMapBufferDescriptor(arg0, pBufDesc) crashcatEngineMapBufferDescriptor_DISPATCH(arg0, pBufDesc) +#define crashcatEngineUnmapBufferDescriptor(arg0, pBufDesc) crashcatEngineUnmapBufferDescriptor_DISPATCH(arg0, pBufDesc) +#define crashcatEngineSyncBufferDescriptor(arg0, pBufDesc, offset, size) crashcatEngineSyncBufferDescriptor_DISPATCH(arg0, pBufDesc, offset, size) +#define crashcatEngineGetScratchOffsets(arg0, scratchId) crashcatEngineGetScratchOffsets_DISPATCH(arg0, scratchId) +#define crashcatEngineGetWFL0Offset(arg0) crashcatEngineGetWFL0Offset_DISPATCH(arg0) +void crashcatEngineUnload_IMPL(struct CrashCatEngine *arg0); + +static inline void crashcatEngineUnload_DISPATCH(struct CrashCatEngine *arg0) { + arg0->__crashcatEngineUnload__(arg0); +} + +static inline NvBool crashcatEngineConfigured_DISPATCH(struct CrashCatEngine *arg0) { + return arg0->__crashcatEngineConfigured__(arg0); +} + +static inline void crashcatEngineVprintf_DISPATCH(struct CrashCatEngine *arg0, NvBool bReportStart, const char *fmt, va_list args) { + arg0->__crashcatEngineVprintf__(arg0, bReportStart, fmt, args); +} + +static inline NvU32 crashcatEnginePriRead_DISPATCH(struct CrashCatEngine *arg0, NvU32 offset) { + return arg0->__crashcatEnginePriRead__(arg0, offset); +} + +static inline void crashcatEnginePriWrite_DISPATCH(struct CrashCatEngine *arg0, NvU32 offset, NvU32 data) { + arg0->__crashcatEnginePriWrite__(arg0, offset, data); +} + +static inline void *crashcatEngineMapBufferDescriptor_DISPATCH(struct CrashCatEngine *arg0, CrashCatBufferDescriptor *pBufDesc) { + return arg0->__crashcatEngineMapBufferDescriptor__(arg0, pBufDesc); +} + +static inline void crashcatEngineUnmapBufferDescriptor_DISPATCH(struct CrashCatEngine *arg0, CrashCatBufferDescriptor *pBufDesc) { + arg0->__crashcatEngineUnmapBufferDescriptor__(arg0, pBufDesc); +} + +static inline void crashcatEngineSyncBufferDescriptor_DISPATCH(struct CrashCatEngine *arg0, CrashCatBufferDescriptor *pBufDesc, NvU32 offset, NvU32 size) { + arg0->__crashcatEngineSyncBufferDescriptor__(arg0, pBufDesc, offset, size); +} + +static inline const NvU32 *crashcatEngineGetScratchOffsets_DISPATCH(struct CrashCatEngine *arg0, NV_CRASHCAT_SCRATCH_GROUP_ID scratchId) { + return arg0->__crashcatEngineGetScratchOffsets__(arg0, scratchId); +} + +static inline NvU32 crashcatEngineGetWFL0Offset_DISPATCH(struct CrashCatEngine *arg0) { + return arg0->__crashcatEngineGetWFL0Offset__(arg0); +} + +NV_STATUS crashcatEngineConstruct_IMPL(struct CrashCatEngine *arg_); + +#define __nvoc_crashcatEngineConstruct(arg_) crashcatEngineConstruct_IMPL(arg_) +void crashcatEngineDestruct_IMPL(struct CrashCatEngine *arg0); + +#define __nvoc_crashcatEngineDestruct(arg0) crashcatEngineDestruct_IMPL(arg0) +struct CrashCatReport *crashcatEngineGetNextCrashReport_IMPL(struct CrashCatEngine *arg0); + +#ifdef __nvoc_crashcat_engine_h_disabled +static inline struct CrashCatReport *crashcatEngineGetNextCrashReport(struct CrashCatEngine *arg0) { + NV_ASSERT_FAILED_PRECOMP("CrashCatEngine was disabled!"); + return NULL; +} +#else //__nvoc_crashcat_engine_h_disabled +#define crashcatEngineGetNextCrashReport(arg0) crashcatEngineGetNextCrashReport_IMPL(arg0) +#endif //__nvoc_crashcat_engine_h_disabled + +NV_STATUS crashcatEngineRegisterCrashBuffer_IMPL(struct CrashCatEngine *arg0, NV_CRASHCAT_MEM_APERTURE aperture, NvU64 offset, NvU64 size, void *pEngPriv); + +#ifdef __nvoc_crashcat_engine_h_disabled +static inline NV_STATUS crashcatEngineRegisterCrashBuffer(struct CrashCatEngine *arg0, NV_CRASHCAT_MEM_APERTURE aperture, NvU64 offset, NvU64 size, void *pEngPriv) { + NV_ASSERT_FAILED_PRECOMP("CrashCatEngine was disabled!"); + return NV_ERR_NOT_SUPPORTED; +} +#else //__nvoc_crashcat_engine_h_disabled +#define crashcatEngineRegisterCrashBuffer(arg0, aperture, offset, size, pEngPriv) crashcatEngineRegisterCrashBuffer_IMPL(arg0, aperture, offset, size, pEngPriv) +#endif //__nvoc_crashcat_engine_h_disabled + +void crashcatEngineUnregisterCrashBuffer_IMPL(struct CrashCatEngine *arg0, NV_CRASHCAT_MEM_APERTURE aperture, NvU64 offset, NvU64 size); + +#ifdef __nvoc_crashcat_engine_h_disabled +static inline void crashcatEngineUnregisterCrashBuffer(struct CrashCatEngine *arg0, NV_CRASHCAT_MEM_APERTURE aperture, NvU64 offset, NvU64 size) { + NV_ASSERT_FAILED_PRECOMP("CrashCatEngine was disabled!"); +} +#else //__nvoc_crashcat_engine_h_disabled +#define crashcatEngineUnregisterCrashBuffer(arg0, aperture, offset, size) crashcatEngineUnregisterCrashBuffer_IMPL(arg0, aperture, offset, size) +#endif //__nvoc_crashcat_engine_h_disabled + +void *crashcatEngineMapCrashBuffer_IMPL(struct CrashCatEngine *arg0, NV_CRASHCAT_MEM_APERTURE aperture, NvU64 offset, NvU64 size); + +#ifdef __nvoc_crashcat_engine_h_disabled +static inline void *crashcatEngineMapCrashBuffer(struct CrashCatEngine *arg0, NV_CRASHCAT_MEM_APERTURE aperture, NvU64 offset, NvU64 size) { + NV_ASSERT_FAILED_PRECOMP("CrashCatEngine was disabled!"); + return NULL; +} +#else //__nvoc_crashcat_engine_h_disabled +#define crashcatEngineMapCrashBuffer(arg0, aperture, offset, size) crashcatEngineMapCrashBuffer_IMPL(arg0, aperture, offset, size) +#endif //__nvoc_crashcat_engine_h_disabled + +void crashcatEngineUnmapCrashBuffer_IMPL(struct CrashCatEngine *arg0, void *ptr); + +#ifdef __nvoc_crashcat_engine_h_disabled +static inline void crashcatEngineUnmapCrashBuffer(struct CrashCatEngine *arg0, void *ptr) { + NV_ASSERT_FAILED_PRECOMP("CrashCatEngine was disabled!"); +} +#else //__nvoc_crashcat_engine_h_disabled +#define crashcatEngineUnmapCrashBuffer(arg0, ptr) crashcatEngineUnmapCrashBuffer_IMPL(arg0, ptr) +#endif //__nvoc_crashcat_engine_h_disabled + +void crashcatEngineSyncCrashBuffer_IMPL(struct CrashCatEngine *arg0, void *ptr, NvU32 offset, NvU32 size); + +#ifdef __nvoc_crashcat_engine_h_disabled +static inline void crashcatEngineSyncCrashBuffer(struct CrashCatEngine *arg0, void *ptr, NvU32 offset, NvU32 size) { + NV_ASSERT_FAILED_PRECOMP("CrashCatEngine was disabled!"); +} +#else //__nvoc_crashcat_engine_h_disabled +#define crashcatEngineSyncCrashBuffer(arg0, ptr, offset, size) crashcatEngineSyncCrashBuffer_IMPL(arg0, ptr, offset, size) +#endif //__nvoc_crashcat_engine_h_disabled + +NV_STATUS crashcatEngineLoadWayfinder_IMPL(struct CrashCatEngine *arg0); + +#ifdef __nvoc_crashcat_engine_h_disabled +static inline NV_STATUS crashcatEngineLoadWayfinder(struct CrashCatEngine *arg0) { + NV_ASSERT_FAILED_PRECOMP("CrashCatEngine was disabled!"); + return NV_ERR_NOT_SUPPORTED; +} +#else //__nvoc_crashcat_engine_h_disabled +#define crashcatEngineLoadWayfinder(arg0) crashcatEngineLoadWayfinder_IMPL(arg0) +#endif //__nvoc_crashcat_engine_h_disabled + +#undef PRIVATE_FIELD + +#ifndef NVOC_CRASHCAT_ENGINE_H_PRIVATE_ACCESS_ALLOWED +#ifndef __nvoc_crashcat_engine_h_disabled +#undef crashcatEngineLoadWayfinder +NV_STATUS NVOC_PRIVATE_FUNCTION(crashcatEngineLoadWayfinder)(struct CrashCatEngine *arg0); +#endif //__nvoc_crashcat_engine_h_disabled + +#endif // NVOC_CRASHCAT_ENGINE_H_PRIVATE_ACCESS_ALLOWED + + +#define CRASHCAT_GET_ENGINE(pCrashCatObj) objFindAncestorOfType(CrashCatEngine, pCrashCatObj) + +// Non-NVOC wrapper for handling variadic arguments +void crashcatEnginePrintf(struct CrashCatEngine *, NvBool, const char *, ...); + +#endif // CRASHCAT_ENGINE_H + +#ifdef __cplusplus +} // extern "C" +#endif +#endif // _G_CRASHCAT_ENGINE_NVOC_H_ diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/generated/g_crashcat_queue_nvoc.c nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_crashcat_queue_nvoc.c --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/generated/g_crashcat_queue_nvoc.c 1970-01-01 00:00:00.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_crashcat_queue_nvoc.c 2024-03-05 22:18:09.000000000 +0000 @@ -0,0 +1,179 @@ +#define NVOC_CRASHCAT_QUEUE_H_PRIVATE_ACCESS_ALLOWED +#include "nvoc/runtime.h" +#include "nvoc/rtti.h" +#include "nvtypes.h" +#include "nvport/nvport.h" +#include "nvport/inline/util_valist.h" +#include "utils/nvassert.h" +#include "g_crashcat_queue_nvoc.h" + +#ifdef DEBUG +char __nvoc_class_id_uniqueness_check_0xbaa900 = 1; +#endif + +extern const struct NVOC_CLASS_DEF __nvoc_class_def_CrashCatQueue; + +extern const struct NVOC_CLASS_DEF __nvoc_class_def_Object; + +void __nvoc_init_CrashCatQueue(CrashCatQueue*, CrashCatWayfinder* ); +void __nvoc_init_funcTable_CrashCatQueue(CrashCatQueue*, CrashCatWayfinder* ); +NV_STATUS __nvoc_ctor_CrashCatQueue(CrashCatQueue*, CrashCatWayfinder* , CrashCatQueueConfig * arg_pQueueConfig); +void __nvoc_init_dataField_CrashCatQueue(CrashCatQueue*, CrashCatWayfinder* ); +void __nvoc_dtor_CrashCatQueue(CrashCatQueue*); +extern const struct NVOC_EXPORT_INFO __nvoc_export_info_CrashCatQueue; + +static const struct NVOC_RTTI __nvoc_rtti_CrashCatQueue_CrashCatQueue = { + /*pClassDef=*/ &__nvoc_class_def_CrashCatQueue, + /*dtor=*/ (NVOC_DYNAMIC_DTOR) &__nvoc_dtor_CrashCatQueue, + /*offset=*/ 0, +}; + +static const struct NVOC_RTTI __nvoc_rtti_CrashCatQueue_Object = { + /*pClassDef=*/ &__nvoc_class_def_Object, + /*dtor=*/ &__nvoc_destructFromBase, + /*offset=*/ NV_OFFSETOF(CrashCatQueue, __nvoc_base_Object), +}; + +static const struct NVOC_CASTINFO __nvoc_castinfo_CrashCatQueue = { + /*numRelatives=*/ 2, + /*relatives=*/ { + &__nvoc_rtti_CrashCatQueue_CrashCatQueue, + &__nvoc_rtti_CrashCatQueue_Object, + }, +}; + +const struct NVOC_CLASS_DEF __nvoc_class_def_CrashCatQueue = +{ + /*classInfo=*/ { + /*size=*/ sizeof(CrashCatQueue), + /*classId=*/ classId(CrashCatQueue), + /*providerId=*/ &__nvoc_rtti_provider, +#if NV_PRINTF_STRINGS_ALLOWED + /*name=*/ "CrashCatQueue", +#endif + }, + /*objCreatefn=*/ (NVOC_DYNAMIC_OBJ_CREATE) &__nvoc_objCreateDynamic_CrashCatQueue, + /*pCastInfo=*/ &__nvoc_castinfo_CrashCatQueue, + /*pExportInfo=*/ &__nvoc_export_info_CrashCatQueue +}; + +const struct NVOC_EXPORT_INFO __nvoc_export_info_CrashCatQueue = +{ + /*numEntries=*/ 0, + /*pExportEntries=*/ 0 +}; + +void __nvoc_dtor_Object(Object*); +void __nvoc_dtor_CrashCatQueue(CrashCatQueue *pThis) { + __nvoc_crashcatQueueDestruct(pThis); + __nvoc_dtor_Object(&pThis->__nvoc_base_Object); + PORT_UNREFERENCED_VARIABLE(pThis); +} + +void __nvoc_init_dataField_CrashCatQueue(CrashCatQueue *pThis, CrashCatWayfinder *pCrashcatWayfinder) { + CrashCatWayfinderHal *wayfinderHal = &pCrashcatWayfinder->wayfinderHal; + const unsigned long wayfinderHal_HalVarIdx = (unsigned long)wayfinderHal->__nvoc_HalVarIdx; + PORT_UNREFERENCED_VARIABLE(pThis); + PORT_UNREFERENCED_VARIABLE(pCrashcatWayfinder); + PORT_UNREFERENCED_VARIABLE(wayfinderHal); + PORT_UNREFERENCED_VARIABLE(wayfinderHal_HalVarIdx); +} + +NV_STATUS __nvoc_ctor_Object(Object* ); +NV_STATUS __nvoc_ctor_CrashCatQueue(CrashCatQueue *pThis, CrashCatWayfinder *pCrashcatWayfinder, CrashCatQueueConfig * arg_pQueueConfig) { + NV_STATUS status = NV_OK; + status = __nvoc_ctor_Object(&pThis->__nvoc_base_Object); + if (status != NV_OK) goto __nvoc_ctor_CrashCatQueue_fail_Object; + __nvoc_init_dataField_CrashCatQueue(pThis, pCrashcatWayfinder); + + status = __nvoc_crashcatQueueConstruct(pThis, arg_pQueueConfig); + if (status != NV_OK) goto __nvoc_ctor_CrashCatQueue_fail__init; + goto __nvoc_ctor_CrashCatQueue_exit; // Success + +__nvoc_ctor_CrashCatQueue_fail__init: + __nvoc_dtor_Object(&pThis->__nvoc_base_Object); +__nvoc_ctor_CrashCatQueue_fail_Object: +__nvoc_ctor_CrashCatQueue_exit: + + return status; +} + +static void __nvoc_init_funcTable_CrashCatQueue_1(CrashCatQueue *pThis, CrashCatWayfinder *pCrashcatWayfinder) { + CrashCatWayfinderHal *wayfinderHal = &pCrashcatWayfinder->wayfinderHal; + const unsigned long wayfinderHal_HalVarIdx = (unsigned long)wayfinderHal->__nvoc_HalVarIdx; + PORT_UNREFERENCED_VARIABLE(pThis); + PORT_UNREFERENCED_VARIABLE(pCrashcatWayfinder); + PORT_UNREFERENCED_VARIABLE(wayfinderHal); + PORT_UNREFERENCED_VARIABLE(wayfinderHal_HalVarIdx); +} + +void __nvoc_init_funcTable_CrashCatQueue(CrashCatQueue *pThis, CrashCatWayfinder *pCrashcatWayfinder) { + __nvoc_init_funcTable_CrashCatQueue_1(pThis, pCrashcatWayfinder); +} + +void __nvoc_init_Object(Object*); +void __nvoc_init_CrashCatQueue(CrashCatQueue *pThis, CrashCatWayfinder *pCrashcatWayfinder) { + pThis->__nvoc_pbase_CrashCatQueue = pThis; + pThis->__nvoc_pbase_Object = &pThis->__nvoc_base_Object; + __nvoc_init_Object(&pThis->__nvoc_base_Object); + __nvoc_init_funcTable_CrashCatQueue(pThis, pCrashcatWayfinder); +} + +NV_STATUS __nvoc_objCreate_CrashCatQueue(CrashCatQueue **ppThis, Dynamic *pParent, NvU32 createFlags, CrashCatQueueConfig * arg_pQueueConfig) { + NV_STATUS status; + Object *pParentObj; + CrashCatQueue *pThis; + CrashCatWayfinder *pCrashcatWayfinder; + + status = __nvoc_handleObjCreateMemAlloc(createFlags, sizeof(CrashCatQueue), (void**)&pThis, (void**)ppThis); + if (status != NV_OK) + return status; + + portMemSet(pThis, 0, sizeof(CrashCatQueue)); + + __nvoc_initRtti(staticCast(pThis, Dynamic), &__nvoc_class_def_CrashCatQueue); + + pThis->__nvoc_base_Object.createFlags = createFlags; + + if (pParent != NULL && !(createFlags & NVOC_OBJ_CREATE_FLAGS_PARENT_HALSPEC_ONLY)) + { + pParentObj = dynamicCast(pParent, Object); + objAddChild(pParentObj, &pThis->__nvoc_base_Object); + } + else + { + pThis->__nvoc_base_Object.pParent = NULL; + } + + if ((pCrashcatWayfinder = dynamicCast(pParent, CrashCatWayfinder)) == NULL) + pCrashcatWayfinder = objFindAncestorOfType(CrashCatWayfinder, pParent); + NV_ASSERT_OR_RETURN(pCrashcatWayfinder != NULL, NV_ERR_INVALID_ARGUMENT); + + __nvoc_init_CrashCatQueue(pThis, pCrashcatWayfinder); + status = __nvoc_ctor_CrashCatQueue(pThis, pCrashcatWayfinder, arg_pQueueConfig); + if (status != NV_OK) goto __nvoc_objCreate_CrashCatQueue_cleanup; + + *ppThis = pThis; + + return NV_OK; + +__nvoc_objCreate_CrashCatQueue_cleanup: + // do not call destructors here since the constructor already called them + if (createFlags & NVOC_OBJ_CREATE_FLAGS_IN_PLACE_CONSTRUCT) + portMemSet(pThis, 0, sizeof(CrashCatQueue)); + else + portMemFree(pThis); + + // coverity[leaked_storage:FALSE] + return status; +} + +NV_STATUS __nvoc_objCreateDynamic_CrashCatQueue(CrashCatQueue **ppThis, Dynamic *pParent, NvU32 createFlags, va_list args) { + NV_STATUS status; + CrashCatQueueConfig * arg_pQueueConfig = va_arg(args, CrashCatQueueConfig *); + + status = __nvoc_objCreate_CrashCatQueue(ppThis, pParent, createFlags, arg_pQueueConfig); + + return status; +} + diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/generated/g_crashcat_queue_nvoc.h nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_crashcat_queue_nvoc.h --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/generated/g_crashcat_queue_nvoc.h 1970-01-01 00:00:00.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_crashcat_queue_nvoc.h 2024-03-05 22:18:09.000000000 +0000 @@ -0,0 +1,147 @@ +#ifndef _G_CRASHCAT_QUEUE_NVOC_H_ +#define _G_CRASHCAT_QUEUE_NVOC_H_ +#include "nvoc/runtime.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/* + * SPDX-FileCopyrightText: Copyright (c) 2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#include "g_crashcat_queue_nvoc.h" + +#ifndef CRASHCAT_QUEUE_H +#define CRASHCAT_QUEUE_H + +#include "nvoc/object.h" +#include "nv-crashcat.h" +#include "crashcat/crashcat_wayfinder.h" // for CrashCatWayfinderHal spec + +struct CrashCatEngine; + +#ifndef __NVOC_CLASS_CrashCatEngine_TYPEDEF__ +#define __NVOC_CLASS_CrashCatEngine_TYPEDEF__ +typedef struct CrashCatEngine CrashCatEngine; +#endif /* __NVOC_CLASS_CrashCatEngine_TYPEDEF__ */ + +#ifndef __nvoc_class_id_CrashCatEngine +#define __nvoc_class_id_CrashCatEngine 0x654166 +#endif /* __nvoc_class_id_CrashCatEngine */ + + +struct CrashCatReport; + +#ifndef __NVOC_CLASS_CrashCatReport_TYPEDEF__ +#define __NVOC_CLASS_CrashCatReport_TYPEDEF__ +typedef struct CrashCatReport CrashCatReport; +#endif /* __NVOC_CLASS_CrashCatReport_TYPEDEF__ */ + +#ifndef __nvoc_class_id_CrashCatReport +#define __nvoc_class_id_CrashCatReport 0xde4777 +#endif /* __nvoc_class_id_CrashCatReport */ + + + +typedef struct +{ + NV_CRASHCAT_MEM_APERTURE aperture; + NvU32 size; + NvU64 offset; + + NvU32 putRegOffset; + NvU32 getRegOffset; +} CrashCatQueueConfig; + +#ifdef NVOC_CRASHCAT_QUEUE_H_PRIVATE_ACCESS_ALLOWED +#define PRIVATE_FIELD(x) x +#else +#define PRIVATE_FIELD(x) NVOC_PRIVATE_FIELD(x) +#endif +struct CrashCatQueue { + const struct NVOC_RTTI *__nvoc_rtti; + struct Object __nvoc_base_Object; + struct Object *__nvoc_pbase_Object; + struct CrashCatQueue *__nvoc_pbase_CrashCatQueue; + CrashCatQueueConfig PRIVATE_FIELD(config); + struct CrashCatEngine *PRIVATE_FIELD(pEngine); + void *PRIVATE_FIELD(pMapping); +}; + +#ifndef __NVOC_CLASS_CrashCatQueue_TYPEDEF__ +#define __NVOC_CLASS_CrashCatQueue_TYPEDEF__ +typedef struct CrashCatQueue CrashCatQueue; +#endif /* __NVOC_CLASS_CrashCatQueue_TYPEDEF__ */ + +#ifndef __nvoc_class_id_CrashCatQueue +#define __nvoc_class_id_CrashCatQueue 0xbaa900 +#endif /* __nvoc_class_id_CrashCatQueue */ + +extern const struct NVOC_CLASS_DEF __nvoc_class_def_CrashCatQueue; + +#define __staticCast_CrashCatQueue(pThis) \ + ((pThis)->__nvoc_pbase_CrashCatQueue) + +#ifdef __nvoc_crashcat_queue_h_disabled +#define __dynamicCast_CrashCatQueue(pThis) ((CrashCatQueue*)NULL) +#else //__nvoc_crashcat_queue_h_disabled +#define __dynamicCast_CrashCatQueue(pThis) \ + ((CrashCatQueue*)__nvoc_dynamicCast(staticCast((pThis), Dynamic), classInfo(CrashCatQueue))) +#endif //__nvoc_crashcat_queue_h_disabled + + +NV_STATUS __nvoc_objCreateDynamic_CrashCatQueue(CrashCatQueue**, Dynamic*, NvU32, va_list); + +NV_STATUS __nvoc_objCreate_CrashCatQueue(CrashCatQueue**, Dynamic*, NvU32, CrashCatQueueConfig * arg_pQueueConfig); +#define __objCreate_CrashCatQueue(ppNewObj, pParent, createFlags, arg_pQueueConfig) \ + __nvoc_objCreate_CrashCatQueue((ppNewObj), staticCast((pParent), Dynamic), (createFlags), arg_pQueueConfig) + +struct CrashCatReport *crashcatQueueConsumeNextReport_V1(struct CrashCatQueue *arg0); + + +#ifdef __nvoc_crashcat_queue_h_disabled +static inline struct CrashCatReport *crashcatQueueConsumeNextReport(struct CrashCatQueue *arg0) { + NV_ASSERT_FAILED_PRECOMP("CrashCatQueue was disabled!"); + return NULL; +} +#else //__nvoc_crashcat_queue_h_disabled +#define crashcatQueueConsumeNextReport(arg0) crashcatQueueConsumeNextReport_V1(arg0) +#endif //__nvoc_crashcat_queue_h_disabled + +#define crashcatQueueConsumeNextReport_HAL(arg0) crashcatQueueConsumeNextReport(arg0) + +NV_STATUS crashcatQueueConstruct_IMPL(struct CrashCatQueue *arg_, CrashCatQueueConfig *arg_pQueueConfig); + +#define __nvoc_crashcatQueueConstruct(arg_, arg_pQueueConfig) crashcatQueueConstruct_IMPL(arg_, arg_pQueueConfig) +void crashcatQueueDestruct_IMPL(struct CrashCatQueue *arg0); + +#define __nvoc_crashcatQueueDestruct(arg0) crashcatQueueDestruct_IMPL(arg0) +#undef PRIVATE_FIELD + + +#endif // CRASHCAT_QUEUE_H + +#ifdef __cplusplus +} // extern "C" +#endif +#endif // _G_CRASHCAT_QUEUE_NVOC_H_ diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/generated/g_crashcat_report_nvoc.c nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_crashcat_report_nvoc.c --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/generated/g_crashcat_report_nvoc.c 1970-01-01 00:00:00.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_crashcat_report_nvoc.c 2024-03-05 22:18:09.000000000 +0000 @@ -0,0 +1,226 @@ +#define NVOC_CRASHCAT_REPORT_H_PRIVATE_ACCESS_ALLOWED +#include "nvoc/runtime.h" +#include "nvoc/rtti.h" +#include "nvtypes.h" +#include "nvport/nvport.h" +#include "nvport/inline/util_valist.h" +#include "utils/nvassert.h" +#include "g_crashcat_report_nvoc.h" + +void __nvoc_init_halspec_CrashCatReportHal(CrashCatReportHal *pCrashCatReportHal, NV_CRASHCAT_PACKET_FORMAT_VERSION version, CrashCatImplementer implementer) +{ + // V1_GENERIC + if(version == 0x1 && implementer == 0x0) + { + pCrashCatReportHal->__nvoc_HalVarIdx = 0; + } + // V1_LIBOS2 + else if(version == 0x1 && implementer == 0x4C49424F53322E30) + { + pCrashCatReportHal->__nvoc_HalVarIdx = 1; + } + // V1_LIBOS3 + else if(version == 0x1 && implementer == 0x4C49424F53332E31) + { + pCrashCatReportHal->__nvoc_HalVarIdx = 2; + } +} + +#ifdef DEBUG +char __nvoc_class_id_uniqueness_check_0xde4777 = 1; +#endif + +extern const struct NVOC_CLASS_DEF __nvoc_class_def_CrashCatReport; + +extern const struct NVOC_CLASS_DEF __nvoc_class_def_Object; + +void __nvoc_init_CrashCatReport(CrashCatReport*, + NV_CRASHCAT_PACKET_FORMAT_VERSION CrashCatReportHal_version, CrashCatImplementer CrashCatReportHal_implementer); +void __nvoc_init_funcTable_CrashCatReport(CrashCatReport*); +NV_STATUS __nvoc_ctor_CrashCatReport(CrashCatReport*, void ** arg_ppReportBytes, NvLength arg_bytesRemaining); +void __nvoc_init_dataField_CrashCatReport(CrashCatReport*); +void __nvoc_dtor_CrashCatReport(CrashCatReport*); +extern const struct NVOC_EXPORT_INFO __nvoc_export_info_CrashCatReport; + +static const struct NVOC_RTTI __nvoc_rtti_CrashCatReport_CrashCatReport = { + /*pClassDef=*/ &__nvoc_class_def_CrashCatReport, + /*dtor=*/ (NVOC_DYNAMIC_DTOR) &__nvoc_dtor_CrashCatReport, + /*offset=*/ 0, +}; + +static const struct NVOC_RTTI __nvoc_rtti_CrashCatReport_Object = { + /*pClassDef=*/ &__nvoc_class_def_Object, + /*dtor=*/ &__nvoc_destructFromBase, + /*offset=*/ NV_OFFSETOF(CrashCatReport, __nvoc_base_Object), +}; + +static const struct NVOC_CASTINFO __nvoc_castinfo_CrashCatReport = { + /*numRelatives=*/ 2, + /*relatives=*/ { + &__nvoc_rtti_CrashCatReport_CrashCatReport, + &__nvoc_rtti_CrashCatReport_Object, + }, +}; + +const struct NVOC_CLASS_DEF __nvoc_class_def_CrashCatReport = +{ + /*classInfo=*/ { + /*size=*/ sizeof(CrashCatReport), + /*classId=*/ classId(CrashCatReport), + /*providerId=*/ &__nvoc_rtti_provider, +#if NV_PRINTF_STRINGS_ALLOWED + /*name=*/ "CrashCatReport", +#endif + }, + /*objCreatefn=*/ (NVOC_DYNAMIC_OBJ_CREATE) &__nvoc_objCreateDynamic_CrashCatReport, + /*pCastInfo=*/ &__nvoc_castinfo_CrashCatReport, + /*pExportInfo=*/ &__nvoc_export_info_CrashCatReport +}; + +const struct NVOC_EXPORT_INFO __nvoc_export_info_CrashCatReport = +{ + /*numEntries=*/ 0, + /*pExportEntries=*/ 0 +}; + +void __nvoc_dtor_Object(Object*); +void __nvoc_dtor_CrashCatReport(CrashCatReport *pThis) { + __nvoc_crashcatReportDestruct(pThis); + __nvoc_dtor_Object(&pThis->__nvoc_base_Object); + PORT_UNREFERENCED_VARIABLE(pThis); +} + +void __nvoc_init_dataField_CrashCatReport(CrashCatReport *pThis) { + CrashCatReportHal *reportHal = &pThis->reportHal; + const unsigned long reportHal_HalVarIdx = (unsigned long)reportHal->__nvoc_HalVarIdx; + PORT_UNREFERENCED_VARIABLE(pThis); + PORT_UNREFERENCED_VARIABLE(reportHal); + PORT_UNREFERENCED_VARIABLE(reportHal_HalVarIdx); +} + +NV_STATUS __nvoc_ctor_Object(Object* ); +NV_STATUS __nvoc_ctor_CrashCatReport(CrashCatReport *pThis, void ** arg_ppReportBytes, NvLength arg_bytesRemaining) { + NV_STATUS status = NV_OK; + status = __nvoc_ctor_Object(&pThis->__nvoc_base_Object); + if (status != NV_OK) goto __nvoc_ctor_CrashCatReport_fail_Object; + __nvoc_init_dataField_CrashCatReport(pThis); + + status = __nvoc_crashcatReportConstruct(pThis, arg_ppReportBytes, arg_bytesRemaining); + if (status != NV_OK) goto __nvoc_ctor_CrashCatReport_fail__init; + goto __nvoc_ctor_CrashCatReport_exit; // Success + +__nvoc_ctor_CrashCatReport_fail__init: + __nvoc_dtor_Object(&pThis->__nvoc_base_Object); +__nvoc_ctor_CrashCatReport_fail_Object: +__nvoc_ctor_CrashCatReport_exit: + + return status; +} + +static void __nvoc_init_funcTable_CrashCatReport_1(CrashCatReport *pThis) { + CrashCatReportHal *reportHal = &pThis->reportHal; + const unsigned long reportHal_HalVarIdx = (unsigned long)reportHal->__nvoc_HalVarIdx; + PORT_UNREFERENCED_VARIABLE(pThis); + PORT_UNREFERENCED_VARIABLE(reportHal); + PORT_UNREFERENCED_VARIABLE(reportHal_HalVarIdx); + + // Hal function -- crashcatReportLogReporter + if (( ((reportHal_HalVarIdx >> 5) == 0UL) && ((1UL << (reportHal_HalVarIdx & 0x1f)) & 0x00000002UL) )) /* CrashCatReportHal: V1_LIBOS2 */ + { + pThis->__crashcatReportLogReporter__ = &crashcatReportLogReporter_V1_LIBOS2; + } + else if (( ((reportHal_HalVarIdx >> 5) == 0UL) && ((1UL << (reportHal_HalVarIdx & 0x1f)) & 0x00000004UL) )) /* CrashCatReportHal: V1_LIBOS3 */ + { + pThis->__crashcatReportLogReporter__ = &crashcatReportLogReporter_V1_LIBOS3; + } + else + { + pThis->__crashcatReportLogReporter__ = &crashcatReportLogReporter_V1_GENERIC; + } + + // Hal function -- crashcatReportLogSource + if (( ((reportHal_HalVarIdx >> 5) == 0UL) && ((1UL << (reportHal_HalVarIdx & 0x1f)) & 0x00000002UL) )) /* CrashCatReportHal: V1_LIBOS2 */ + { + pThis->__crashcatReportLogSource__ = &crashcatReportLogSource_V1_LIBOS2; + } + else if (( ((reportHal_HalVarIdx >> 5) == 0UL) && ((1UL << (reportHal_HalVarIdx & 0x1f)) & 0x00000004UL) )) /* CrashCatReportHal: V1_LIBOS3 */ + { + pThis->__crashcatReportLogSource__ = &crashcatReportLogSource_V1_LIBOS3; + } + else + { + pThis->__crashcatReportLogSource__ = &crashcatReportLogSource_V1_GENERIC; + } +} + +void __nvoc_init_funcTable_CrashCatReport(CrashCatReport *pThis) { + __nvoc_init_funcTable_CrashCatReport_1(pThis); +} + +void __nvoc_init_Object(Object*); +void __nvoc_init_CrashCatReport(CrashCatReport *pThis, + NV_CRASHCAT_PACKET_FORMAT_VERSION CrashCatReportHal_version, CrashCatImplementer CrashCatReportHal_implementer) { + pThis->__nvoc_pbase_CrashCatReport = pThis; + pThis->__nvoc_pbase_Object = &pThis->__nvoc_base_Object; + __nvoc_init_Object(&pThis->__nvoc_base_Object); + __nvoc_init_halspec_CrashCatReportHal(&pThis->reportHal, CrashCatReportHal_version, CrashCatReportHal_implementer); + __nvoc_init_funcTable_CrashCatReport(pThis); +} + +NV_STATUS __nvoc_objCreate_CrashCatReport(CrashCatReport **ppThis, Dynamic *pParent, NvU32 createFlags, + NV_CRASHCAT_PACKET_FORMAT_VERSION CrashCatReportHal_version, CrashCatImplementer CrashCatReportHal_implementer, void ** arg_ppReportBytes, NvLength arg_bytesRemaining) { + NV_STATUS status; + Object *pParentObj; + CrashCatReport *pThis; + + status = __nvoc_handleObjCreateMemAlloc(createFlags, sizeof(CrashCatReport), (void**)&pThis, (void**)ppThis); + if (status != NV_OK) + return status; + + portMemSet(pThis, 0, sizeof(CrashCatReport)); + + __nvoc_initRtti(staticCast(pThis, Dynamic), &__nvoc_class_def_CrashCatReport); + + pThis->__nvoc_base_Object.createFlags = createFlags; + + if (pParent != NULL && !(createFlags & NVOC_OBJ_CREATE_FLAGS_PARENT_HALSPEC_ONLY)) + { + pParentObj = dynamicCast(pParent, Object); + objAddChild(pParentObj, &pThis->__nvoc_base_Object); + } + else + { + pThis->__nvoc_base_Object.pParent = NULL; + } + + __nvoc_init_CrashCatReport(pThis, CrashCatReportHal_version, CrashCatReportHal_implementer); + status = __nvoc_ctor_CrashCatReport(pThis, arg_ppReportBytes, arg_bytesRemaining); + if (status != NV_OK) goto __nvoc_objCreate_CrashCatReport_cleanup; + + *ppThis = pThis; + + return NV_OK; + +__nvoc_objCreate_CrashCatReport_cleanup: + // do not call destructors here since the constructor already called them + if (createFlags & NVOC_OBJ_CREATE_FLAGS_IN_PLACE_CONSTRUCT) + portMemSet(pThis, 0, sizeof(CrashCatReport)); + else + portMemFree(pThis); + + // coverity[leaked_storage:FALSE] + return status; +} + +NV_STATUS __nvoc_objCreateDynamic_CrashCatReport(CrashCatReport **ppThis, Dynamic *pParent, NvU32 createFlags, va_list args) { + NV_STATUS status; + NV_CRASHCAT_PACKET_FORMAT_VERSION CrashCatReportHal_version = va_arg(args, NV_CRASHCAT_PACKET_FORMAT_VERSION); + CrashCatImplementer CrashCatReportHal_implementer = va_arg(args, CrashCatImplementer); + void ** arg_ppReportBytes = va_arg(args, void **); + NvLength arg_bytesRemaining = va_arg(args, NvLength); + + status = __nvoc_objCreate_CrashCatReport(ppThis, pParent, createFlags, CrashCatReportHal_version, CrashCatReportHal_implementer, arg_ppReportBytes, arg_bytesRemaining); + + return status; +} + diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/generated/g_crashcat_report_nvoc.h nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_crashcat_report_nvoc.h --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/generated/g_crashcat_report_nvoc.h 1970-01-01 00:00:00.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_crashcat_report_nvoc.h 2024-03-05 22:18:09.000000000 +0000 @@ -0,0 +1,393 @@ +#ifndef _G_CRASHCAT_REPORT_NVOC_H_ +#define _G_CRASHCAT_REPORT_NVOC_H_ +#include "nvoc/runtime.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/* + * SPDX-FileCopyrightText: Copyright (c) 2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#include "g_crashcat_report_nvoc.h" + +#ifndef CRASHCAT_REPORT_H +#define CRASHCAT_REPORT_H + +#include "nv-crashcat.h" +#include "nvoc/object.h" + +struct CrashCatEngine; + +#ifndef __NVOC_CLASS_CrashCatEngine_TYPEDEF__ +#define __NVOC_CLASS_CrashCatEngine_TYPEDEF__ +typedef struct CrashCatEngine CrashCatEngine; +#endif /* __NVOC_CLASS_CrashCatEngine_TYPEDEF__ */ + +#ifndef __nvoc_class_id_CrashCatEngine +#define __nvoc_class_id_CrashCatEngine 0x654166 +#endif /* __nvoc_class_id_CrashCatEngine */ + + + +typedef NvU64 CrashCatImplementer; + +#define CRASHCAT_IMPLEMENTER_UNSPECIFIED 0ull +#define CRASHCAT_IMPLEMENTER_LIBOS2 0x4C49424F53322E30ull // "LIBOS2.0" +#define CRASHCAT_IMPLEMENTER_LIBOS3 0x4C49424F53332E31ull // "LIBOS3.1" + +struct CrashCatReportHal { + unsigned short __nvoc_HalVarIdx; +}; +typedef struct CrashCatReportHal CrashCatReportHal; +void __nvoc_init_halspec_CrashCatReportHal(CrashCatReportHal*, NV_CRASHCAT_PACKET_FORMAT_VERSION, CrashCatImplementer); + +#ifdef NVOC_CRASHCAT_REPORT_H_PRIVATE_ACCESS_ALLOWED +#define PRIVATE_FIELD(x) x +#else +#define PRIVATE_FIELD(x) NVOC_PRIVATE_FIELD(x) +#endif +struct __nvoc_inner_struc_CrashCatReport_1__ { + NvCrashCatReport_V1 report; + NvCrashCatRiscv64CsrState_V1 riscv64CsrState; + NvCrashCatRiscv64GprState_V1 riscv64GprState; + NvCrashCatRiscv64Trace_V1 *pRiscv64StackTrace; + NvCrashCatRiscv64Trace_V1 *pRiscv64PcTrace; + NvCrashCatIo32State_V1 *pIo32State; +}; + + +struct CrashCatReport { + const struct NVOC_RTTI *__nvoc_rtti; + struct Object __nvoc_base_Object; + struct Object *__nvoc_pbase_Object; + struct CrashCatReport *__nvoc_pbase_CrashCatReport; + void (*__crashcatReportLogReporter__)(struct CrashCatReport *); + void (*__crashcatReportLogSource__)(struct CrashCatReport *); + struct CrashCatReportHal reportHal; + struct CrashCatEngine *PRIVATE_FIELD(pEngine); + NvU32 PRIVATE_FIELD(validTags); + struct __nvoc_inner_struc_CrashCatReport_1__ PRIVATE_FIELD(v1); +}; + +#ifndef __NVOC_CLASS_CrashCatReport_TYPEDEF__ +#define __NVOC_CLASS_CrashCatReport_TYPEDEF__ +typedef struct CrashCatReport CrashCatReport; +#endif /* __NVOC_CLASS_CrashCatReport_TYPEDEF__ */ + +#ifndef __nvoc_class_id_CrashCatReport +#define __nvoc_class_id_CrashCatReport 0xde4777 +#endif /* __nvoc_class_id_CrashCatReport */ + +extern const struct NVOC_CLASS_DEF __nvoc_class_def_CrashCatReport; + +#define __staticCast_CrashCatReport(pThis) \ + ((pThis)->__nvoc_pbase_CrashCatReport) + +#ifdef __nvoc_crashcat_report_h_disabled +#define __dynamicCast_CrashCatReport(pThis) ((CrashCatReport*)NULL) +#else //__nvoc_crashcat_report_h_disabled +#define __dynamicCast_CrashCatReport(pThis) \ + ((CrashCatReport*)__nvoc_dynamicCast(staticCast((pThis), Dynamic), classInfo(CrashCatReport))) +#endif //__nvoc_crashcat_report_h_disabled + + +NV_STATUS __nvoc_objCreateDynamic_CrashCatReport(CrashCatReport**, Dynamic*, NvU32, va_list); + +NV_STATUS __nvoc_objCreate_CrashCatReport(CrashCatReport**, Dynamic*, NvU32, + NV_CRASHCAT_PACKET_FORMAT_VERSION CrashCatReportHal_version, CrashCatImplementer CrashCatReportHal_implementer, void ** arg_ppReportBytes, NvLength arg_bytesRemaining); +#define __objCreate_CrashCatReport(ppNewObj, pParent, createFlags, CrashCatReportHal_version, CrashCatReportHal_implementer, arg_ppReportBytes, arg_bytesRemaining) \ + __nvoc_objCreate_CrashCatReport((ppNewObj), staticCast((pParent), Dynamic), (createFlags), CrashCatReportHal_version, CrashCatReportHal_implementer, arg_ppReportBytes, arg_bytesRemaining) + +#define crashcatReportLogReporter(arg0) crashcatReportLogReporter_DISPATCH(arg0) +#define crashcatReportLogReporter_HAL(arg0) crashcatReportLogReporter_DISPATCH(arg0) +#define crashcatReportLogSource(arg0) crashcatReportLogSource_DISPATCH(arg0) +#define crashcatReportLogSource_HAL(arg0) crashcatReportLogSource_DISPATCH(arg0) +void crashcatReportDestruct_V1(struct CrashCatReport *arg0); + + +#define __nvoc_crashcatReportDestruct(arg0) crashcatReportDestruct_V1(arg0) +void *crashcatReportExtract_V1(struct CrashCatReport *arg0, void *pReportBytes, NvLength bytesRemaining); + + +#ifdef __nvoc_crashcat_report_h_disabled +static inline void *crashcatReportExtract(struct CrashCatReport *arg0, void *pReportBytes, NvLength bytesRemaining) { + NV_ASSERT_FAILED_PRECOMP("CrashCatReport was disabled!"); + return NULL; +} +#else //__nvoc_crashcat_report_h_disabled +#define crashcatReportExtract(arg0, pReportBytes, bytesRemaining) crashcatReportExtract_V1(arg0, pReportBytes, bytesRemaining) +#endif //__nvoc_crashcat_report_h_disabled + +#define crashcatReportExtract_HAL(arg0, pReportBytes, bytesRemaining) crashcatReportExtract(arg0, pReportBytes, bytesRemaining) + +void *crashcatReportExtractReport_V1(struct CrashCatReport *arg0, void *pReportBytes, NvLength bytesRemaining); + + +#ifdef __nvoc_crashcat_report_h_disabled +static inline void *crashcatReportExtractReport(struct CrashCatReport *arg0, void *pReportBytes, NvLength bytesRemaining) { + NV_ASSERT_FAILED_PRECOMP("CrashCatReport was disabled!"); + return NULL; +} +#else //__nvoc_crashcat_report_h_disabled +#define crashcatReportExtractReport(arg0, pReportBytes, bytesRemaining) crashcatReportExtractReport_V1(arg0, pReportBytes, bytesRemaining) +#endif //__nvoc_crashcat_report_h_disabled + +#define crashcatReportExtractReport_HAL(arg0, pReportBytes, bytesRemaining) crashcatReportExtractReport(arg0, pReportBytes, bytesRemaining) + +void *crashcatReportExtractRiscv64CsrState_V1(struct CrashCatReport *arg0, void *pReportBytes, NvLength bytesRemaining); + + +#ifdef __nvoc_crashcat_report_h_disabled +static inline void *crashcatReportExtractRiscv64CsrState(struct CrashCatReport *arg0, void *pReportBytes, NvLength bytesRemaining) { + NV_ASSERT_FAILED_PRECOMP("CrashCatReport was disabled!"); + return NULL; +} +#else //__nvoc_crashcat_report_h_disabled +#define crashcatReportExtractRiscv64CsrState(arg0, pReportBytes, bytesRemaining) crashcatReportExtractRiscv64CsrState_V1(arg0, pReportBytes, bytesRemaining) +#endif //__nvoc_crashcat_report_h_disabled + +#define crashcatReportExtractRiscv64CsrState_HAL(arg0, pReportBytes, bytesRemaining) crashcatReportExtractRiscv64CsrState(arg0, pReportBytes, bytesRemaining) + +void *crashcatReportExtractRiscv64GprState_V1(struct CrashCatReport *arg0, void *pReportBytes, NvLength bytesRemaining); + + +#ifdef __nvoc_crashcat_report_h_disabled +static inline void *crashcatReportExtractRiscv64GprState(struct CrashCatReport *arg0, void *pReportBytes, NvLength bytesRemaining) { + NV_ASSERT_FAILED_PRECOMP("CrashCatReport was disabled!"); + return NULL; +} +#else //__nvoc_crashcat_report_h_disabled +#define crashcatReportExtractRiscv64GprState(arg0, pReportBytes, bytesRemaining) crashcatReportExtractRiscv64GprState_V1(arg0, pReportBytes, bytesRemaining) +#endif //__nvoc_crashcat_report_h_disabled + +#define crashcatReportExtractRiscv64GprState_HAL(arg0, pReportBytes, bytesRemaining) crashcatReportExtractRiscv64GprState(arg0, pReportBytes, bytesRemaining) + +void *crashcatReportExtractRiscv64Trace_V1(struct CrashCatReport *arg0, void *pReportBytes, NvLength bytesRemaining); + + +#ifdef __nvoc_crashcat_report_h_disabled +static inline void *crashcatReportExtractRiscv64Trace(struct CrashCatReport *arg0, void *pReportBytes, NvLength bytesRemaining) { + NV_ASSERT_FAILED_PRECOMP("CrashCatReport was disabled!"); + return NULL; +} +#else //__nvoc_crashcat_report_h_disabled +#define crashcatReportExtractRiscv64Trace(arg0, pReportBytes, bytesRemaining) crashcatReportExtractRiscv64Trace_V1(arg0, pReportBytes, bytesRemaining) +#endif //__nvoc_crashcat_report_h_disabled + +#define crashcatReportExtractRiscv64Trace_HAL(arg0, pReportBytes, bytesRemaining) crashcatReportExtractRiscv64Trace(arg0, pReportBytes, bytesRemaining) + +void *crashcatReportExtractIo32State_V1(struct CrashCatReport *arg0, void *pReportBytes, NvLength bytesRemaining); + + +#ifdef __nvoc_crashcat_report_h_disabled +static inline void *crashcatReportExtractIo32State(struct CrashCatReport *arg0, void *pReportBytes, NvLength bytesRemaining) { + NV_ASSERT_FAILED_PRECOMP("CrashCatReport was disabled!"); + return NULL; +} +#else //__nvoc_crashcat_report_h_disabled +#define crashcatReportExtractIo32State(arg0, pReportBytes, bytesRemaining) crashcatReportExtractIo32State_V1(arg0, pReportBytes, bytesRemaining) +#endif //__nvoc_crashcat_report_h_disabled + +#define crashcatReportExtractIo32State_HAL(arg0, pReportBytes, bytesRemaining) crashcatReportExtractIo32State(arg0, pReportBytes, bytesRemaining) + +void crashcatReportLogRiscv64CsrState_V1(struct CrashCatReport *arg0); + + +#ifdef __nvoc_crashcat_report_h_disabled +static inline void crashcatReportLogRiscv64CsrState(struct CrashCatReport *arg0) { + NV_ASSERT_FAILED_PRECOMP("CrashCatReport was disabled!"); +} +#else //__nvoc_crashcat_report_h_disabled +#define crashcatReportLogRiscv64CsrState(arg0) crashcatReportLogRiscv64CsrState_V1(arg0) +#endif //__nvoc_crashcat_report_h_disabled + +#define crashcatReportLogRiscv64CsrState_HAL(arg0) crashcatReportLogRiscv64CsrState(arg0) + +void crashcatReportLogRiscv64GprState_V1(struct CrashCatReport *arg0); + + +#ifdef __nvoc_crashcat_report_h_disabled +static inline void crashcatReportLogRiscv64GprState(struct CrashCatReport *arg0) { + NV_ASSERT_FAILED_PRECOMP("CrashCatReport was disabled!"); +} +#else //__nvoc_crashcat_report_h_disabled +#define crashcatReportLogRiscv64GprState(arg0) crashcatReportLogRiscv64GprState_V1(arg0) +#endif //__nvoc_crashcat_report_h_disabled + +#define crashcatReportLogRiscv64GprState_HAL(arg0) crashcatReportLogRiscv64GprState(arg0) + +void crashcatReportLogRiscv64Traces_V1(struct CrashCatReport *arg0); + + +#ifdef __nvoc_crashcat_report_h_disabled +static inline void crashcatReportLogRiscv64Traces(struct CrashCatReport *arg0) { + NV_ASSERT_FAILED_PRECOMP("CrashCatReport was disabled!"); +} +#else //__nvoc_crashcat_report_h_disabled +#define crashcatReportLogRiscv64Traces(arg0) crashcatReportLogRiscv64Traces_V1(arg0) +#endif //__nvoc_crashcat_report_h_disabled + +#define crashcatReportLogRiscv64Traces_HAL(arg0) crashcatReportLogRiscv64Traces(arg0) + +void crashcatReportLogIo32State_V1(struct CrashCatReport *arg0); + + +#ifdef __nvoc_crashcat_report_h_disabled +static inline void crashcatReportLogIo32State(struct CrashCatReport *arg0) { + NV_ASSERT_FAILED_PRECOMP("CrashCatReport was disabled!"); +} +#else //__nvoc_crashcat_report_h_disabled +#define crashcatReportLogIo32State(arg0) crashcatReportLogIo32State_V1(arg0) +#endif //__nvoc_crashcat_report_h_disabled + +#define crashcatReportLogIo32State_HAL(arg0) crashcatReportLogIo32State(arg0) + +void crashcatReportLogReporter_V1_GENERIC(struct CrashCatReport *arg0); + +void crashcatReportLogReporter_V1_LIBOS2(struct CrashCatReport *arg0); + +void crashcatReportLogReporter_V1_LIBOS3(struct CrashCatReport *arg0); + +static inline void crashcatReportLogReporter_DISPATCH(struct CrashCatReport *arg0) { + arg0->__crashcatReportLogReporter__(arg0); +} + +void crashcatReportLogSource_V1_GENERIC(struct CrashCatReport *arg0); + +void crashcatReportLogSource_V1_LIBOS2(struct CrashCatReport *arg0); + +void crashcatReportLogSource_V1_LIBOS3(struct CrashCatReport *arg0); + +static inline void crashcatReportLogSource_DISPATCH(struct CrashCatReport *arg0) { + arg0->__crashcatReportLogSource__(arg0); +} + +NV_STATUS crashcatReportConstruct_IMPL(struct CrashCatReport *arg_, void **arg_ppReportBytes, NvLength arg_bytesRemaining); + +#define __nvoc_crashcatReportConstruct(arg_, arg_ppReportBytes, arg_bytesRemaining) crashcatReportConstruct_IMPL(arg_, arg_ppReportBytes, arg_bytesRemaining) +void crashcatReportLog_IMPL(struct CrashCatReport *arg0); + +#ifdef __nvoc_crashcat_report_h_disabled +static inline void crashcatReportLog(struct CrashCatReport *arg0) { + NV_ASSERT_FAILED_PRECOMP("CrashCatReport was disabled!"); +} +#else //__nvoc_crashcat_report_h_disabled +#define crashcatReportLog(arg0) crashcatReportLog_IMPL(arg0) +#endif //__nvoc_crashcat_report_h_disabled + +#undef PRIVATE_FIELD + +#ifndef NVOC_CRASHCAT_REPORT_H_PRIVATE_ACCESS_ALLOWED +#undef crashcatReportLogReporter +void NVOC_PRIVATE_FUNCTION(crashcatReportLogReporter)(struct CrashCatReport *arg0); + +#undef crashcatReportLogReporter_HAL +void NVOC_PRIVATE_FUNCTION(crashcatReportLogReporter_HAL)(struct CrashCatReport *arg0); + +#undef crashcatReportLogSource +void NVOC_PRIVATE_FUNCTION(crashcatReportLogSource)(struct CrashCatReport *arg0); + +#undef crashcatReportLogSource_HAL +void NVOC_PRIVATE_FUNCTION(crashcatReportLogSource_HAL)(struct CrashCatReport *arg0); + +#ifndef __nvoc_crashcat_report_h_disabled +#undef crashcatReportExtract +void *NVOC_PRIVATE_FUNCTION(crashcatReportExtract)(struct CrashCatReport *arg0, void *pReportBytes, NvLength bytesRemaining); +#endif //__nvoc_crashcat_report_h_disabled + +#ifndef __nvoc_crashcat_report_h_disabled +#undef crashcatReportExtractReport +void *NVOC_PRIVATE_FUNCTION(crashcatReportExtractReport)(struct CrashCatReport *arg0, void *pReportBytes, NvLength bytesRemaining); +#endif //__nvoc_crashcat_report_h_disabled + +#ifndef __nvoc_crashcat_report_h_disabled +#undef crashcatReportExtractRiscv64CsrState +void *NVOC_PRIVATE_FUNCTION(crashcatReportExtractRiscv64CsrState)(struct CrashCatReport *arg0, void *pReportBytes, NvLength bytesRemaining); +#endif //__nvoc_crashcat_report_h_disabled + +#ifndef __nvoc_crashcat_report_h_disabled +#undef crashcatReportExtractRiscv64GprState +void *NVOC_PRIVATE_FUNCTION(crashcatReportExtractRiscv64GprState)(struct CrashCatReport *arg0, void *pReportBytes, NvLength bytesRemaining); +#endif //__nvoc_crashcat_report_h_disabled + +#ifndef __nvoc_crashcat_report_h_disabled +#undef crashcatReportExtractRiscv64Trace +void *NVOC_PRIVATE_FUNCTION(crashcatReportExtractRiscv64Trace)(struct CrashCatReport *arg0, void *pReportBytes, NvLength bytesRemaining); +#endif //__nvoc_crashcat_report_h_disabled + +#ifndef __nvoc_crashcat_report_h_disabled +#undef crashcatReportExtractIo32State +void *NVOC_PRIVATE_FUNCTION(crashcatReportExtractIo32State)(struct CrashCatReport *arg0, void *pReportBytes, NvLength bytesRemaining); +#endif //__nvoc_crashcat_report_h_disabled + +#ifndef __nvoc_crashcat_report_h_disabled +#undef crashcatReportLogRiscv64CsrState +void NVOC_PRIVATE_FUNCTION(crashcatReportLogRiscv64CsrState)(struct CrashCatReport *arg0); +#endif //__nvoc_crashcat_report_h_disabled + +#ifndef __nvoc_crashcat_report_h_disabled +#undef crashcatReportLogRiscv64GprState +void NVOC_PRIVATE_FUNCTION(crashcatReportLogRiscv64GprState)(struct CrashCatReport *arg0); +#endif //__nvoc_crashcat_report_h_disabled + +#ifndef __nvoc_crashcat_report_h_disabled +#undef crashcatReportLogRiscv64Traces +void NVOC_PRIVATE_FUNCTION(crashcatReportLogRiscv64Traces)(struct CrashCatReport *arg0); +#endif //__nvoc_crashcat_report_h_disabled + +#ifndef __nvoc_crashcat_report_h_disabled +#undef crashcatReportLogIo32State +void NVOC_PRIVATE_FUNCTION(crashcatReportLogIo32State)(struct CrashCatReport *arg0); +#endif //__nvoc_crashcat_report_h_disabled + +#endif // NVOC_CRASHCAT_REPORT_H_PRIVATE_ACCESS_ALLOWED + + +// Utility to convert a cause code to a user-friendly string +const char *crashcatReportRiscvCauseToString(NvU64 xcause); + +// Log indentation used for multi-line reports +#define CRASHCAT_LOG_INDENT " " + +// Prefix used for multi-line reports +#if defined(NVRM) +#define CRASHCAT_LOG_PREFIX "NVRM: " +#else +#define CRASHCAT_LOG_PREFIX +#endif + +#define CRASHCAT_REPORT_LOG_PACKET_TYPE(pReport, fmt, ...) \ + crashcatEnginePrintf(pReport->pEngine, NV_FALSE, \ + CRASHCAT_LOG_PREFIX CRASHCAT_LOG_INDENT fmt, ##__VA_ARGS__) +#define CRASHCAT_REPORT_LOG_DATA(pReport, fmt, ...) \ + crashcatEnginePrintf(pReport->pEngine, NV_FALSE, \ + CRASHCAT_LOG_PREFIX CRASHCAT_LOG_INDENT CRASHCAT_LOG_INDENT fmt, \ + ##__VA_ARGS__) + +#endif // CRASHCAT_REPORT_H + +#ifdef __cplusplus +} // extern "C" +#endif +#endif // _G_CRASHCAT_REPORT_NVOC_H_ diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/generated/g_crashcat_wayfinder_nvoc.c nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_crashcat_wayfinder_nvoc.c --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/generated/g_crashcat_wayfinder_nvoc.c 1970-01-01 00:00:00.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_crashcat_wayfinder_nvoc.c 2024-03-05 22:18:09.000000000 +0000 @@ -0,0 +1,186 @@ +#define NVOC_CRASHCAT_WAYFINDER_H_PRIVATE_ACCESS_ALLOWED +#include "nvoc/runtime.h" +#include "nvoc/rtti.h" +#include "nvtypes.h" +#include "nvport/nvport.h" +#include "nvport/inline/util_valist.h" +#include "utils/nvassert.h" +#include "g_crashcat_wayfinder_nvoc.h" + +void __nvoc_init_halspec_CrashCatWayfinderHal(CrashCatWayfinderHal *pCrashCatWayfinderHal, NV_CRASHCAT_WAYFINDER_VERSION version) +{ + // V1 + if(version == 0x1) + { + pCrashCatWayfinderHal->__nvoc_HalVarIdx = 0; + } +} + +#ifdef DEBUG +char __nvoc_class_id_uniqueness_check_0x085e32 = 1; +#endif + +extern const struct NVOC_CLASS_DEF __nvoc_class_def_CrashCatWayfinder; + +extern const struct NVOC_CLASS_DEF __nvoc_class_def_Object; + +void __nvoc_init_CrashCatWayfinder(CrashCatWayfinder*, + NV_CRASHCAT_WAYFINDER_VERSION CrashCatWayfinderHal_version); +void __nvoc_init_funcTable_CrashCatWayfinder(CrashCatWayfinder*); +NV_STATUS __nvoc_ctor_CrashCatWayfinder(CrashCatWayfinder*, NvU32 arg_wfl0); +void __nvoc_init_dataField_CrashCatWayfinder(CrashCatWayfinder*); +void __nvoc_dtor_CrashCatWayfinder(CrashCatWayfinder*); +extern const struct NVOC_EXPORT_INFO __nvoc_export_info_CrashCatWayfinder; + +static const struct NVOC_RTTI __nvoc_rtti_CrashCatWayfinder_CrashCatWayfinder = { + /*pClassDef=*/ &__nvoc_class_def_CrashCatWayfinder, + /*dtor=*/ (NVOC_DYNAMIC_DTOR) &__nvoc_dtor_CrashCatWayfinder, + /*offset=*/ 0, +}; + +static const struct NVOC_RTTI __nvoc_rtti_CrashCatWayfinder_Object = { + /*pClassDef=*/ &__nvoc_class_def_Object, + /*dtor=*/ &__nvoc_destructFromBase, + /*offset=*/ NV_OFFSETOF(CrashCatWayfinder, __nvoc_base_Object), +}; + +static const struct NVOC_CASTINFO __nvoc_castinfo_CrashCatWayfinder = { + /*numRelatives=*/ 2, + /*relatives=*/ { + &__nvoc_rtti_CrashCatWayfinder_CrashCatWayfinder, + &__nvoc_rtti_CrashCatWayfinder_Object, + }, +}; + +const struct NVOC_CLASS_DEF __nvoc_class_def_CrashCatWayfinder = +{ + /*classInfo=*/ { + /*size=*/ sizeof(CrashCatWayfinder), + /*classId=*/ classId(CrashCatWayfinder), + /*providerId=*/ &__nvoc_rtti_provider, +#if NV_PRINTF_STRINGS_ALLOWED + /*name=*/ "CrashCatWayfinder", +#endif + }, + /*objCreatefn=*/ (NVOC_DYNAMIC_OBJ_CREATE) &__nvoc_objCreateDynamic_CrashCatWayfinder, + /*pCastInfo=*/ &__nvoc_castinfo_CrashCatWayfinder, + /*pExportInfo=*/ &__nvoc_export_info_CrashCatWayfinder +}; + +const struct NVOC_EXPORT_INFO __nvoc_export_info_CrashCatWayfinder = +{ + /*numEntries=*/ 0, + /*pExportEntries=*/ 0 +}; + +void __nvoc_dtor_Object(Object*); +void __nvoc_dtor_CrashCatWayfinder(CrashCatWayfinder *pThis) { + __nvoc_crashcatWayfinderDestruct(pThis); + __nvoc_dtor_Object(&pThis->__nvoc_base_Object); + PORT_UNREFERENCED_VARIABLE(pThis); +} + +void __nvoc_init_dataField_CrashCatWayfinder(CrashCatWayfinder *pThis) { + CrashCatWayfinderHal *wayfinderHal = &pThis->wayfinderHal; + const unsigned long wayfinderHal_HalVarIdx = (unsigned long)wayfinderHal->__nvoc_HalVarIdx; + PORT_UNREFERENCED_VARIABLE(pThis); + PORT_UNREFERENCED_VARIABLE(wayfinderHal); + PORT_UNREFERENCED_VARIABLE(wayfinderHal_HalVarIdx); +} + +NV_STATUS __nvoc_ctor_Object(Object* ); +NV_STATUS __nvoc_ctor_CrashCatWayfinder(CrashCatWayfinder *pThis, NvU32 arg_wfl0) { + NV_STATUS status = NV_OK; + status = __nvoc_ctor_Object(&pThis->__nvoc_base_Object); + if (status != NV_OK) goto __nvoc_ctor_CrashCatWayfinder_fail_Object; + __nvoc_init_dataField_CrashCatWayfinder(pThis); + + status = __nvoc_crashcatWayfinderConstruct(pThis, arg_wfl0); + if (status != NV_OK) goto __nvoc_ctor_CrashCatWayfinder_fail__init; + goto __nvoc_ctor_CrashCatWayfinder_exit; // Success + +__nvoc_ctor_CrashCatWayfinder_fail__init: + __nvoc_dtor_Object(&pThis->__nvoc_base_Object); +__nvoc_ctor_CrashCatWayfinder_fail_Object: +__nvoc_ctor_CrashCatWayfinder_exit: + + return status; +} + +static void __nvoc_init_funcTable_CrashCatWayfinder_1(CrashCatWayfinder *pThis) { + CrashCatWayfinderHal *wayfinderHal = &pThis->wayfinderHal; + const unsigned long wayfinderHal_HalVarIdx = (unsigned long)wayfinderHal->__nvoc_HalVarIdx; + PORT_UNREFERENCED_VARIABLE(pThis); + PORT_UNREFERENCED_VARIABLE(wayfinderHal); + PORT_UNREFERENCED_VARIABLE(wayfinderHal_HalVarIdx); +} + +void __nvoc_init_funcTable_CrashCatWayfinder(CrashCatWayfinder *pThis) { + __nvoc_init_funcTable_CrashCatWayfinder_1(pThis); +} + +void __nvoc_init_Object(Object*); +void __nvoc_init_CrashCatWayfinder(CrashCatWayfinder *pThis, + NV_CRASHCAT_WAYFINDER_VERSION CrashCatWayfinderHal_version) { + pThis->__nvoc_pbase_CrashCatWayfinder = pThis; + pThis->__nvoc_pbase_Object = &pThis->__nvoc_base_Object; + __nvoc_init_Object(&pThis->__nvoc_base_Object); + __nvoc_init_halspec_CrashCatWayfinderHal(&pThis->wayfinderHal, CrashCatWayfinderHal_version); + __nvoc_init_funcTable_CrashCatWayfinder(pThis); +} + +NV_STATUS __nvoc_objCreate_CrashCatWayfinder(CrashCatWayfinder **ppThis, Dynamic *pParent, NvU32 createFlags, + NV_CRASHCAT_WAYFINDER_VERSION CrashCatWayfinderHal_version, NvU32 arg_wfl0) { + NV_STATUS status; + Object *pParentObj; + CrashCatWayfinder *pThis; + + status = __nvoc_handleObjCreateMemAlloc(createFlags, sizeof(CrashCatWayfinder), (void**)&pThis, (void**)ppThis); + if (status != NV_OK) + return status; + + portMemSet(pThis, 0, sizeof(CrashCatWayfinder)); + + __nvoc_initRtti(staticCast(pThis, Dynamic), &__nvoc_class_def_CrashCatWayfinder); + + pThis->__nvoc_base_Object.createFlags = createFlags; + + if (pParent != NULL && !(createFlags & NVOC_OBJ_CREATE_FLAGS_PARENT_HALSPEC_ONLY)) + { + pParentObj = dynamicCast(pParent, Object); + objAddChild(pParentObj, &pThis->__nvoc_base_Object); + } + else + { + pThis->__nvoc_base_Object.pParent = NULL; + } + + __nvoc_init_CrashCatWayfinder(pThis, CrashCatWayfinderHal_version); + status = __nvoc_ctor_CrashCatWayfinder(pThis, arg_wfl0); + if (status != NV_OK) goto __nvoc_objCreate_CrashCatWayfinder_cleanup; + + *ppThis = pThis; + + return NV_OK; + +__nvoc_objCreate_CrashCatWayfinder_cleanup: + // do not call destructors here since the constructor already called them + if (createFlags & NVOC_OBJ_CREATE_FLAGS_IN_PLACE_CONSTRUCT) + portMemSet(pThis, 0, sizeof(CrashCatWayfinder)); + else + portMemFree(pThis); + + // coverity[leaked_storage:FALSE] + return status; +} + +NV_STATUS __nvoc_objCreateDynamic_CrashCatWayfinder(CrashCatWayfinder **ppThis, Dynamic *pParent, NvU32 createFlags, va_list args) { + NV_STATUS status; + NV_CRASHCAT_WAYFINDER_VERSION CrashCatWayfinderHal_version = va_arg(args, NV_CRASHCAT_WAYFINDER_VERSION); + NvU32 arg_wfl0 = va_arg(args, NvU32); + + status = __nvoc_objCreate_CrashCatWayfinder(ppThis, pParent, createFlags, CrashCatWayfinderHal_version, arg_wfl0); + + return status; +} + diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/generated/g_crashcat_wayfinder_nvoc.h nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_crashcat_wayfinder_nvoc.h --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/generated/g_crashcat_wayfinder_nvoc.h 1970-01-01 00:00:00.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_crashcat_wayfinder_nvoc.h 2024-03-05 22:18:10.000000000 +0000 @@ -0,0 +1,170 @@ +#ifndef _G_CRASHCAT_WAYFINDER_NVOC_H_ +#define _G_CRASHCAT_WAYFINDER_NVOC_H_ +#include "nvoc/runtime.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/* + * SPDX-FileCopyrightText: Copyright (c) 2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#include "g_crashcat_wayfinder_nvoc.h" + +#ifndef CRASHCAT_WAYFINDER_H +#define CRASHCAT_WAYFINDER_H + +#include "nvoc/object.h" +#include "nv-crashcat.h" + +struct CrashCatQueue; + +#ifndef __NVOC_CLASS_CrashCatQueue_TYPEDEF__ +#define __NVOC_CLASS_CrashCatQueue_TYPEDEF__ +typedef struct CrashCatQueue CrashCatQueue; +#endif /* __NVOC_CLASS_CrashCatQueue_TYPEDEF__ */ + +#ifndef __nvoc_class_id_CrashCatQueue +#define __nvoc_class_id_CrashCatQueue 0xbaa900 +#endif /* __nvoc_class_id_CrashCatQueue */ + + +struct CrashCatReport; + +#ifndef __NVOC_CLASS_CrashCatReport_TYPEDEF__ +#define __NVOC_CLASS_CrashCatReport_TYPEDEF__ +typedef struct CrashCatReport CrashCatReport; +#endif /* __NVOC_CLASS_CrashCatReport_TYPEDEF__ */ + +#ifndef __nvoc_class_id_CrashCatReport +#define __nvoc_class_id_CrashCatReport 0xde4777 +#endif /* __nvoc_class_id_CrashCatReport */ + + + +struct CrashCatWayfinderHal { + unsigned short __nvoc_HalVarIdx; +}; +typedef struct CrashCatWayfinderHal CrashCatWayfinderHal; +void __nvoc_init_halspec_CrashCatWayfinderHal(CrashCatWayfinderHal*, NV_CRASHCAT_WAYFINDER_VERSION); + +#ifdef NVOC_CRASHCAT_WAYFINDER_H_PRIVATE_ACCESS_ALLOWED +#define PRIVATE_FIELD(x) x +#else +#define PRIVATE_FIELD(x) NVOC_PRIVATE_FIELD(x) +#endif +struct __nvoc_inner_struc_CrashCatWayfinder_1__ { + NvCrashCatWayfinderL0_V1 wfl0; + NvCrashCatWayfinderL1_V1 wfl1; +}; + + +struct CrashCatWayfinder { + const struct NVOC_RTTI *__nvoc_rtti; + struct Object __nvoc_base_Object; + struct Object *__nvoc_pbase_Object; + struct CrashCatWayfinder *__nvoc_pbase_CrashCatWayfinder; + struct CrashCatWayfinderHal wayfinderHal; + struct CrashCatQueue *PRIVATE_FIELD(pQueue); + struct __nvoc_inner_struc_CrashCatWayfinder_1__ PRIVATE_FIELD(v1); +}; + +#ifndef __NVOC_CLASS_CrashCatWayfinder_TYPEDEF__ +#define __NVOC_CLASS_CrashCatWayfinder_TYPEDEF__ +typedef struct CrashCatWayfinder CrashCatWayfinder; +#endif /* __NVOC_CLASS_CrashCatWayfinder_TYPEDEF__ */ + +#ifndef __nvoc_class_id_CrashCatWayfinder +#define __nvoc_class_id_CrashCatWayfinder 0x085e32 +#endif /* __nvoc_class_id_CrashCatWayfinder */ + +extern const struct NVOC_CLASS_DEF __nvoc_class_def_CrashCatWayfinder; + +#define __staticCast_CrashCatWayfinder(pThis) \ + ((pThis)->__nvoc_pbase_CrashCatWayfinder) + +#ifdef __nvoc_crashcat_wayfinder_h_disabled +#define __dynamicCast_CrashCatWayfinder(pThis) ((CrashCatWayfinder*)NULL) +#else //__nvoc_crashcat_wayfinder_h_disabled +#define __dynamicCast_CrashCatWayfinder(pThis) \ + ((CrashCatWayfinder*)__nvoc_dynamicCast(staticCast((pThis), Dynamic), classInfo(CrashCatWayfinder))) +#endif //__nvoc_crashcat_wayfinder_h_disabled + + +NV_STATUS __nvoc_objCreateDynamic_CrashCatWayfinder(CrashCatWayfinder**, Dynamic*, NvU32, va_list); + +NV_STATUS __nvoc_objCreate_CrashCatWayfinder(CrashCatWayfinder**, Dynamic*, NvU32, + NV_CRASHCAT_WAYFINDER_VERSION CrashCatWayfinderHal_version, NvU32 arg_wfl0); +#define __objCreate_CrashCatWayfinder(ppNewObj, pParent, createFlags, CrashCatWayfinderHal_version, arg_wfl0) \ + __nvoc_objCreate_CrashCatWayfinder((ppNewObj), staticCast((pParent), Dynamic), (createFlags), CrashCatWayfinderHal_version, arg_wfl0) + +struct CrashCatQueue *crashcatWayfinderGetReportQueue_V1(struct CrashCatWayfinder *arg0); + + +#ifdef __nvoc_crashcat_wayfinder_h_disabled +static inline struct CrashCatQueue *crashcatWayfinderGetReportQueue(struct CrashCatWayfinder *arg0) { + NV_ASSERT_FAILED_PRECOMP("CrashCatWayfinder was disabled!"); + return NULL; +} +#else //__nvoc_crashcat_wayfinder_h_disabled +#define crashcatWayfinderGetReportQueue(arg0) crashcatWayfinderGetReportQueue_V1(arg0) +#endif //__nvoc_crashcat_wayfinder_h_disabled + +#define crashcatWayfinderGetReportQueue_HAL(arg0) crashcatWayfinderGetReportQueue(arg0) + +void crashcatWayfinderSetWFL0_V1(struct CrashCatWayfinder *arg0, NvU32 wfl0); + + +#ifdef __nvoc_crashcat_wayfinder_h_disabled +static inline void crashcatWayfinderSetWFL0(struct CrashCatWayfinder *arg0, NvU32 wfl0) { + NV_ASSERT_FAILED_PRECOMP("CrashCatWayfinder was disabled!"); +} +#else //__nvoc_crashcat_wayfinder_h_disabled +#define crashcatWayfinderSetWFL0(arg0, wfl0) crashcatWayfinderSetWFL0_V1(arg0, wfl0) +#endif //__nvoc_crashcat_wayfinder_h_disabled + +#define crashcatWayfinderSetWFL0_HAL(arg0, wfl0) crashcatWayfinderSetWFL0(arg0, wfl0) + +NV_STATUS crashcatWayfinderConstruct_IMPL(struct CrashCatWayfinder *arg_, NvU32 arg_wfl0); + +#define __nvoc_crashcatWayfinderConstruct(arg_, arg_wfl0) crashcatWayfinderConstruct_IMPL(arg_, arg_wfl0) +void crashcatWayfinderDestruct_IMPL(struct CrashCatWayfinder *arg0); + +#define __nvoc_crashcatWayfinderDestruct(arg0) crashcatWayfinderDestruct_IMPL(arg0) +#undef PRIVATE_FIELD + +#ifndef NVOC_CRASHCAT_WAYFINDER_H_PRIVATE_ACCESS_ALLOWED +#ifndef __nvoc_crashcat_wayfinder_h_disabled +#undef crashcatWayfinderSetWFL0 +void NVOC_PRIVATE_FUNCTION(crashcatWayfinderSetWFL0)(struct CrashCatWayfinder *arg0, NvU32 wfl0); +#endif //__nvoc_crashcat_wayfinder_h_disabled + +#endif // NVOC_CRASHCAT_WAYFINDER_H_PRIVATE_ACCESS_ALLOWED + + +#endif // CRASHCAT_VECTOR_H + +#ifdef __cplusplus +} // extern "C" +#endif +#endif // _G_CRASHCAT_WAYFINDER_NVOC_H_ diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/generated/g_dbgbuffer_nvoc.c nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_dbgbuffer_nvoc.c --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/generated/g_dbgbuffer_nvoc.c 2023-10-25 20:26:53.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_dbgbuffer_nvoc.c 2024-03-05 22:18:10.000000000 +0000 @@ -113,36 +113,20 @@ return gpuresShareCallback((struct GpuResource *)(((unsigned char *)pGpuResource) + __nvoc_rtti_DebugBufferApi_GpuResource.offset), pInvokingClient, pParentRef, pSharePolicy); } -static NV_STATUS __nvoc_thunk_GpuResource_dbgbufControl(struct DebugBufferApi *pGpuResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { - return gpuresControl((struct GpuResource *)(((unsigned char *)pGpuResource) + __nvoc_rtti_DebugBufferApi_GpuResource.offset), pCallContext, pParams); -} - -static NV_STATUS __nvoc_thunk_RmResource_dbgbufGetMemInterMapParams(struct DebugBufferApi *pRmResource, RMRES_MEM_INTER_MAP_PARAMS *pParams) { - return rmresGetMemInterMapParams((struct RmResource *)(((unsigned char *)pRmResource) + __nvoc_rtti_DebugBufferApi_RmResource.offset), pParams); -} - -static NvHandle __nvoc_thunk_GpuResource_dbgbufGetInternalObjectHandle(struct DebugBufferApi *pGpuResource) { - return gpuresGetInternalObjectHandle((struct GpuResource *)(((unsigned char *)pGpuResource) + __nvoc_rtti_DebugBufferApi_GpuResource.offset)); -} - -static NV_STATUS __nvoc_thunk_RsResource_dbgbufControlFilter(struct DebugBufferApi *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { - return resControlFilter((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_DebugBufferApi_RsResource.offset), pCallContext, pParams); +static NV_STATUS __nvoc_thunk_RmResource_dbgbufCheckMemInterUnmap(struct DebugBufferApi *pRmResource, NvBool bSubdeviceHandleProvided) { + return rmresCheckMemInterUnmap((struct RmResource *)(((unsigned char *)pRmResource) + __nvoc_rtti_DebugBufferApi_RmResource.offset), bSubdeviceHandleProvided); } -static void __nvoc_thunk_RsResource_dbgbufAddAdditionalDependants(struct RsClient *pClient, struct DebugBufferApi *pResource, RsResourceRef *pReference) { - resAddAdditionalDependants(pClient, (struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_DebugBufferApi_RsResource.offset), pReference); +static NV_STATUS __nvoc_thunk_RsResource_dbgbufMapTo(struct DebugBufferApi *pResource, RS_RES_MAP_TO_PARAMS *pParams) { + return resMapTo((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_DebugBufferApi_RsResource.offset), pParams); } static NvU32 __nvoc_thunk_RsResource_dbgbufGetRefCount(struct DebugBufferApi *pResource) { return resGetRefCount((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_DebugBufferApi_RsResource.offset)); } -static NV_STATUS __nvoc_thunk_RmResource_dbgbufCheckMemInterUnmap(struct DebugBufferApi *pRmResource, NvBool bSubdeviceHandleProvided) { - return rmresCheckMemInterUnmap((struct RmResource *)(((unsigned char *)pRmResource) + __nvoc_rtti_DebugBufferApi_RmResource.offset), bSubdeviceHandleProvided); -} - -static NV_STATUS __nvoc_thunk_RsResource_dbgbufMapTo(struct DebugBufferApi *pResource, RS_RES_MAP_TO_PARAMS *pParams) { - return resMapTo((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_DebugBufferApi_RsResource.offset), pParams); +static void __nvoc_thunk_RsResource_dbgbufAddAdditionalDependants(struct RsClient *pClient, struct DebugBufferApi *pResource, RsResourceRef *pReference) { + resAddAdditionalDependants(pClient, (struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_DebugBufferApi_RsResource.offset), pReference); } static NV_STATUS __nvoc_thunk_RmResource_dbgbufControl_Prologue(struct DebugBufferApi *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { @@ -153,26 +137,14 @@ return gpuresGetRegBaseOffsetAndSize((struct GpuResource *)(((unsigned char *)pGpuResource) + __nvoc_rtti_DebugBufferApi_GpuResource.offset), pGpu, pOffset, pSize); } -static NvBool __nvoc_thunk_RsResource_dbgbufCanCopy(struct DebugBufferApi *pResource) { - return resCanCopy((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_DebugBufferApi_RsResource.offset)); -} - static NV_STATUS __nvoc_thunk_GpuResource_dbgbufInternalControlForward(struct DebugBufferApi *pGpuResource, NvU32 command, void *pParams, NvU32 size) { return gpuresInternalControlForward((struct GpuResource *)(((unsigned char *)pGpuResource) + __nvoc_rtti_DebugBufferApi_GpuResource.offset), command, pParams, size); } -static void __nvoc_thunk_RsResource_dbgbufPreDestruct(struct DebugBufferApi *pResource) { - resPreDestruct((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_DebugBufferApi_RsResource.offset)); -} - static NV_STATUS __nvoc_thunk_RsResource_dbgbufUnmapFrom(struct DebugBufferApi *pResource, RS_RES_UNMAP_FROM_PARAMS *pParams) { return resUnmapFrom((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_DebugBufferApi_RsResource.offset), pParams); } -static NV_STATUS __nvoc_thunk_RsResource_dbgbufIsDuplicate(struct DebugBufferApi *pResource, NvHandle hMemory, NvBool *pDuplicate) { - return resIsDuplicate((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_DebugBufferApi_RsResource.offset), hMemory, pDuplicate); -} - static void __nvoc_thunk_RmResource_dbgbufControl_Epilogue(struct DebugBufferApi *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { rmresControl_Epilogue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_DebugBufferApi_RmResource.offset), pCallContext, pParams); } @@ -181,6 +153,42 @@ return resControlLookup((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_DebugBufferApi_RsResource.offset), pParams, ppEntry); } +static NvHandle __nvoc_thunk_GpuResource_dbgbufGetInternalObjectHandle(struct DebugBufferApi *pGpuResource) { + return gpuresGetInternalObjectHandle((struct GpuResource *)(((unsigned char *)pGpuResource) + __nvoc_rtti_DebugBufferApi_GpuResource.offset)); +} + +static NV_STATUS __nvoc_thunk_GpuResource_dbgbufControl(struct DebugBufferApi *pGpuResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return gpuresControl((struct GpuResource *)(((unsigned char *)pGpuResource) + __nvoc_rtti_DebugBufferApi_GpuResource.offset), pCallContext, pParams); +} + +static NV_STATUS __nvoc_thunk_RmResource_dbgbufGetMemInterMapParams(struct DebugBufferApi *pRmResource, RMRES_MEM_INTER_MAP_PARAMS *pParams) { + return rmresGetMemInterMapParams((struct RmResource *)(((unsigned char *)pRmResource) + __nvoc_rtti_DebugBufferApi_RmResource.offset), pParams); +} + +static NV_STATUS __nvoc_thunk_RsResource_dbgbufControlFilter(struct DebugBufferApi *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return resControlFilter((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_DebugBufferApi_RsResource.offset), pCallContext, pParams); +} + +static NV_STATUS __nvoc_thunk_RmResource_dbgbufControlSerialization_Prologue(struct DebugBufferApi *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return rmresControlSerialization_Prologue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_DebugBufferApi_RmResource.offset), pCallContext, pParams); +} + +static NvBool __nvoc_thunk_RsResource_dbgbufCanCopy(struct DebugBufferApi *pResource) { + return resCanCopy((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_DebugBufferApi_RsResource.offset)); +} + +static void __nvoc_thunk_RsResource_dbgbufPreDestruct(struct DebugBufferApi *pResource) { + resPreDestruct((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_DebugBufferApi_RsResource.offset)); +} + +static NV_STATUS __nvoc_thunk_RsResource_dbgbufIsDuplicate(struct DebugBufferApi *pResource, NvHandle hMemory, NvBool *pDuplicate) { + return resIsDuplicate((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_DebugBufferApi_RsResource.offset), hMemory, pDuplicate); +} + +static void __nvoc_thunk_RmResource_dbgbufControlSerialization_Epilogue(struct DebugBufferApi *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + rmresControlSerialization_Epilogue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_DebugBufferApi_RmResource.offset), pCallContext, pParams); +} + static NvBool __nvoc_thunk_RmResource_dbgbufAccessCallback(struct DebugBufferApi *pResource, struct RsClient *pInvokingClient, void *pAllocParams, RsAccessRight accessRight) { return rmresAccessCallback((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_DebugBufferApi_RmResource.offset), pInvokingClient, pAllocParams, accessRight); } @@ -242,40 +250,44 @@ pThis->__dbgbufShareCallback__ = &__nvoc_thunk_GpuResource_dbgbufShareCallback; - pThis->__dbgbufControl__ = &__nvoc_thunk_GpuResource_dbgbufControl; - - pThis->__dbgbufGetMemInterMapParams__ = &__nvoc_thunk_RmResource_dbgbufGetMemInterMapParams; - - pThis->__dbgbufGetInternalObjectHandle__ = &__nvoc_thunk_GpuResource_dbgbufGetInternalObjectHandle; - - pThis->__dbgbufControlFilter__ = &__nvoc_thunk_RsResource_dbgbufControlFilter; + pThis->__dbgbufCheckMemInterUnmap__ = &__nvoc_thunk_RmResource_dbgbufCheckMemInterUnmap; - pThis->__dbgbufAddAdditionalDependants__ = &__nvoc_thunk_RsResource_dbgbufAddAdditionalDependants; + pThis->__dbgbufMapTo__ = &__nvoc_thunk_RsResource_dbgbufMapTo; pThis->__dbgbufGetRefCount__ = &__nvoc_thunk_RsResource_dbgbufGetRefCount; - pThis->__dbgbufCheckMemInterUnmap__ = &__nvoc_thunk_RmResource_dbgbufCheckMemInterUnmap; - - pThis->__dbgbufMapTo__ = &__nvoc_thunk_RsResource_dbgbufMapTo; + pThis->__dbgbufAddAdditionalDependants__ = &__nvoc_thunk_RsResource_dbgbufAddAdditionalDependants; pThis->__dbgbufControl_Prologue__ = &__nvoc_thunk_RmResource_dbgbufControl_Prologue; pThis->__dbgbufGetRegBaseOffsetAndSize__ = &__nvoc_thunk_GpuResource_dbgbufGetRegBaseOffsetAndSize; - pThis->__dbgbufCanCopy__ = &__nvoc_thunk_RsResource_dbgbufCanCopy; - pThis->__dbgbufInternalControlForward__ = &__nvoc_thunk_GpuResource_dbgbufInternalControlForward; - pThis->__dbgbufPreDestruct__ = &__nvoc_thunk_RsResource_dbgbufPreDestruct; - pThis->__dbgbufUnmapFrom__ = &__nvoc_thunk_RsResource_dbgbufUnmapFrom; - pThis->__dbgbufIsDuplicate__ = &__nvoc_thunk_RsResource_dbgbufIsDuplicate; - pThis->__dbgbufControl_Epilogue__ = &__nvoc_thunk_RmResource_dbgbufControl_Epilogue; pThis->__dbgbufControlLookup__ = &__nvoc_thunk_RsResource_dbgbufControlLookup; + pThis->__dbgbufGetInternalObjectHandle__ = &__nvoc_thunk_GpuResource_dbgbufGetInternalObjectHandle; + + pThis->__dbgbufControl__ = &__nvoc_thunk_GpuResource_dbgbufControl; + + pThis->__dbgbufGetMemInterMapParams__ = &__nvoc_thunk_RmResource_dbgbufGetMemInterMapParams; + + pThis->__dbgbufControlFilter__ = &__nvoc_thunk_RsResource_dbgbufControlFilter; + + pThis->__dbgbufControlSerialization_Prologue__ = &__nvoc_thunk_RmResource_dbgbufControlSerialization_Prologue; + + pThis->__dbgbufCanCopy__ = &__nvoc_thunk_RsResource_dbgbufCanCopy; + + pThis->__dbgbufPreDestruct__ = &__nvoc_thunk_RsResource_dbgbufPreDestruct; + + pThis->__dbgbufIsDuplicate__ = &__nvoc_thunk_RsResource_dbgbufIsDuplicate; + + pThis->__dbgbufControlSerialization_Epilogue__ = &__nvoc_thunk_RmResource_dbgbufControlSerialization_Epilogue; + pThis->__dbgbufAccessCallback__ = &__nvoc_thunk_RmResource_dbgbufAccessCallback; } @@ -300,13 +312,16 @@ Object *pParentObj; DebugBufferApi *pThis; - pThis = portMemAllocNonPaged(sizeof(DebugBufferApi)); - if (pThis == NULL) return NV_ERR_NO_MEMORY; + status = __nvoc_handleObjCreateMemAlloc(createFlags, sizeof(DebugBufferApi), (void**)&pThis, (void**)ppThis); + if (status != NV_OK) + return status; portMemSet(pThis, 0, sizeof(DebugBufferApi)); __nvoc_initRtti(staticCast(pThis, Dynamic), &__nvoc_class_def_DebugBufferApi); + pThis->__nvoc_base_GpuResource.__nvoc_base_RmResource.__nvoc_base_RsResource.__nvoc_base_Object.createFlags = createFlags; + if (pParent != NULL && !(createFlags & NVOC_OBJ_CREATE_FLAGS_PARENT_HALSPEC_ONLY)) { pParentObj = dynamicCast(pParent, Object); @@ -322,11 +337,17 @@ if (status != NV_OK) goto __nvoc_objCreate_DebugBufferApi_cleanup; *ppThis = pThis; + return NV_OK; __nvoc_objCreate_DebugBufferApi_cleanup: // do not call destructors here since the constructor already called them - portMemFree(pThis); + if (createFlags & NVOC_OBJ_CREATE_FLAGS_IN_PLACE_CONSTRUCT) + portMemSet(pThis, 0, sizeof(DebugBufferApi)); + else + portMemFree(pThis); + + // coverity[leaked_storage:FALSE] return status; } diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/generated/g_dbgbuffer_nvoc.h nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_dbgbuffer_nvoc.h --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/generated/g_dbgbuffer_nvoc.h 2023-10-25 20:26:53.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_dbgbuffer_nvoc.h 2024-03-05 22:18:10.000000000 +0000 @@ -66,23 +66,25 @@ NV_STATUS (*__dbgbufGetMapAddrSpace__)(struct DebugBufferApi *, CALL_CONTEXT *, NvU32, NV_ADDRESS_SPACE *); NV_STATUS (*__dbgbufGetMemoryMappingDescriptor__)(struct DebugBufferApi *, MEMORY_DESCRIPTOR **); NvBool (*__dbgbufShareCallback__)(struct DebugBufferApi *, struct RsClient *, struct RsResourceRef *, RS_SHARE_POLICY *); - NV_STATUS (*__dbgbufControl__)(struct DebugBufferApi *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); - NV_STATUS (*__dbgbufGetMemInterMapParams__)(struct DebugBufferApi *, RMRES_MEM_INTER_MAP_PARAMS *); - NvHandle (*__dbgbufGetInternalObjectHandle__)(struct DebugBufferApi *); - NV_STATUS (*__dbgbufControlFilter__)(struct DebugBufferApi *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); - void (*__dbgbufAddAdditionalDependants__)(struct RsClient *, struct DebugBufferApi *, RsResourceRef *); - NvU32 (*__dbgbufGetRefCount__)(struct DebugBufferApi *); NV_STATUS (*__dbgbufCheckMemInterUnmap__)(struct DebugBufferApi *, NvBool); NV_STATUS (*__dbgbufMapTo__)(struct DebugBufferApi *, RS_RES_MAP_TO_PARAMS *); + NvU32 (*__dbgbufGetRefCount__)(struct DebugBufferApi *); + void (*__dbgbufAddAdditionalDependants__)(struct RsClient *, struct DebugBufferApi *, RsResourceRef *); NV_STATUS (*__dbgbufControl_Prologue__)(struct DebugBufferApi *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); NV_STATUS (*__dbgbufGetRegBaseOffsetAndSize__)(struct DebugBufferApi *, struct OBJGPU *, NvU32 *, NvU32 *); - NvBool (*__dbgbufCanCopy__)(struct DebugBufferApi *); NV_STATUS (*__dbgbufInternalControlForward__)(struct DebugBufferApi *, NvU32, void *, NvU32); - void (*__dbgbufPreDestruct__)(struct DebugBufferApi *); NV_STATUS (*__dbgbufUnmapFrom__)(struct DebugBufferApi *, RS_RES_UNMAP_FROM_PARAMS *); - NV_STATUS (*__dbgbufIsDuplicate__)(struct DebugBufferApi *, NvHandle, NvBool *); void (*__dbgbufControl_Epilogue__)(struct DebugBufferApi *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); NV_STATUS (*__dbgbufControlLookup__)(struct DebugBufferApi *, struct RS_RES_CONTROL_PARAMS_INTERNAL *, const struct NVOC_EXPORTED_METHOD_DEF **); + NvHandle (*__dbgbufGetInternalObjectHandle__)(struct DebugBufferApi *); + NV_STATUS (*__dbgbufControl__)(struct DebugBufferApi *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); + NV_STATUS (*__dbgbufGetMemInterMapParams__)(struct DebugBufferApi *, RMRES_MEM_INTER_MAP_PARAMS *); + NV_STATUS (*__dbgbufControlFilter__)(struct DebugBufferApi *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); + NV_STATUS (*__dbgbufControlSerialization_Prologue__)(struct DebugBufferApi *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); + NvBool (*__dbgbufCanCopy__)(struct DebugBufferApi *); + void (*__dbgbufPreDestruct__)(struct DebugBufferApi *); + NV_STATUS (*__dbgbufIsDuplicate__)(struct DebugBufferApi *, NvHandle, NvBool *); + void (*__dbgbufControlSerialization_Epilogue__)(struct DebugBufferApi *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); NvBool (*__dbgbufAccessCallback__)(struct DebugBufferApi *, struct RsClient *, void *, RsAccessRight); MEMORY_DESCRIPTOR *pMemDesc; }; @@ -120,23 +122,25 @@ #define dbgbufGetMapAddrSpace(pDebugBufferApi, pCallContext, mapFlags, pAddrSpace) dbgbufGetMapAddrSpace_DISPATCH(pDebugBufferApi, pCallContext, mapFlags, pAddrSpace) #define dbgbufGetMemoryMappingDescriptor(pDebugBufferApi, ppMemDesc) dbgbufGetMemoryMappingDescriptor_DISPATCH(pDebugBufferApi, ppMemDesc) #define dbgbufShareCallback(pGpuResource, pInvokingClient, pParentRef, pSharePolicy) dbgbufShareCallback_DISPATCH(pGpuResource, pInvokingClient, pParentRef, pSharePolicy) -#define dbgbufControl(pGpuResource, pCallContext, pParams) dbgbufControl_DISPATCH(pGpuResource, pCallContext, pParams) -#define dbgbufGetMemInterMapParams(pRmResource, pParams) dbgbufGetMemInterMapParams_DISPATCH(pRmResource, pParams) -#define dbgbufGetInternalObjectHandle(pGpuResource) dbgbufGetInternalObjectHandle_DISPATCH(pGpuResource) -#define dbgbufControlFilter(pResource, pCallContext, pParams) dbgbufControlFilter_DISPATCH(pResource, pCallContext, pParams) -#define dbgbufAddAdditionalDependants(pClient, pResource, pReference) dbgbufAddAdditionalDependants_DISPATCH(pClient, pResource, pReference) -#define dbgbufGetRefCount(pResource) dbgbufGetRefCount_DISPATCH(pResource) #define dbgbufCheckMemInterUnmap(pRmResource, bSubdeviceHandleProvided) dbgbufCheckMemInterUnmap_DISPATCH(pRmResource, bSubdeviceHandleProvided) #define dbgbufMapTo(pResource, pParams) dbgbufMapTo_DISPATCH(pResource, pParams) +#define dbgbufGetRefCount(pResource) dbgbufGetRefCount_DISPATCH(pResource) +#define dbgbufAddAdditionalDependants(pClient, pResource, pReference) dbgbufAddAdditionalDependants_DISPATCH(pClient, pResource, pReference) #define dbgbufControl_Prologue(pResource, pCallContext, pParams) dbgbufControl_Prologue_DISPATCH(pResource, pCallContext, pParams) #define dbgbufGetRegBaseOffsetAndSize(pGpuResource, pGpu, pOffset, pSize) dbgbufGetRegBaseOffsetAndSize_DISPATCH(pGpuResource, pGpu, pOffset, pSize) -#define dbgbufCanCopy(pResource) dbgbufCanCopy_DISPATCH(pResource) #define dbgbufInternalControlForward(pGpuResource, command, pParams, size) dbgbufInternalControlForward_DISPATCH(pGpuResource, command, pParams, size) -#define dbgbufPreDestruct(pResource) dbgbufPreDestruct_DISPATCH(pResource) #define dbgbufUnmapFrom(pResource, pParams) dbgbufUnmapFrom_DISPATCH(pResource, pParams) -#define dbgbufIsDuplicate(pResource, hMemory, pDuplicate) dbgbufIsDuplicate_DISPATCH(pResource, hMemory, pDuplicate) #define dbgbufControl_Epilogue(pResource, pCallContext, pParams) dbgbufControl_Epilogue_DISPATCH(pResource, pCallContext, pParams) #define dbgbufControlLookup(pResource, pParams, ppEntry) dbgbufControlLookup_DISPATCH(pResource, pParams, ppEntry) +#define dbgbufGetInternalObjectHandle(pGpuResource) dbgbufGetInternalObjectHandle_DISPATCH(pGpuResource) +#define dbgbufControl(pGpuResource, pCallContext, pParams) dbgbufControl_DISPATCH(pGpuResource, pCallContext, pParams) +#define dbgbufGetMemInterMapParams(pRmResource, pParams) dbgbufGetMemInterMapParams_DISPATCH(pRmResource, pParams) +#define dbgbufControlFilter(pResource, pCallContext, pParams) dbgbufControlFilter_DISPATCH(pResource, pCallContext, pParams) +#define dbgbufControlSerialization_Prologue(pResource, pCallContext, pParams) dbgbufControlSerialization_Prologue_DISPATCH(pResource, pCallContext, pParams) +#define dbgbufCanCopy(pResource) dbgbufCanCopy_DISPATCH(pResource) +#define dbgbufPreDestruct(pResource) dbgbufPreDestruct_DISPATCH(pResource) +#define dbgbufIsDuplicate(pResource, hMemory, pDuplicate) dbgbufIsDuplicate_DISPATCH(pResource, hMemory, pDuplicate) +#define dbgbufControlSerialization_Epilogue(pResource, pCallContext, pParams) dbgbufControlSerialization_Epilogue_DISPATCH(pResource, pCallContext, pParams) #define dbgbufAccessCallback(pResource, pInvokingClient, pAllocParams, accessRight) dbgbufAccessCallback_DISPATCH(pResource, pInvokingClient, pAllocParams, accessRight) NV_STATUS dbgbufMap_IMPL(struct DebugBufferApi *pDebugBufferApi, CALL_CONTEXT *pCallContext, struct RS_CPU_MAP_PARAMS *pParams, RsCpuMapping *pCpuMapping); @@ -166,36 +170,20 @@ return pGpuResource->__dbgbufShareCallback__(pGpuResource, pInvokingClient, pParentRef, pSharePolicy); } -static inline NV_STATUS dbgbufControl_DISPATCH(struct DebugBufferApi *pGpuResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { - return pGpuResource->__dbgbufControl__(pGpuResource, pCallContext, pParams); -} - -static inline NV_STATUS dbgbufGetMemInterMapParams_DISPATCH(struct DebugBufferApi *pRmResource, RMRES_MEM_INTER_MAP_PARAMS *pParams) { - return pRmResource->__dbgbufGetMemInterMapParams__(pRmResource, pParams); -} - -static inline NvHandle dbgbufGetInternalObjectHandle_DISPATCH(struct DebugBufferApi *pGpuResource) { - return pGpuResource->__dbgbufGetInternalObjectHandle__(pGpuResource); -} - -static inline NV_STATUS dbgbufControlFilter_DISPATCH(struct DebugBufferApi *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { - return pResource->__dbgbufControlFilter__(pResource, pCallContext, pParams); +static inline NV_STATUS dbgbufCheckMemInterUnmap_DISPATCH(struct DebugBufferApi *pRmResource, NvBool bSubdeviceHandleProvided) { + return pRmResource->__dbgbufCheckMemInterUnmap__(pRmResource, bSubdeviceHandleProvided); } -static inline void dbgbufAddAdditionalDependants_DISPATCH(struct RsClient *pClient, struct DebugBufferApi *pResource, RsResourceRef *pReference) { - pResource->__dbgbufAddAdditionalDependants__(pClient, pResource, pReference); +static inline NV_STATUS dbgbufMapTo_DISPATCH(struct DebugBufferApi *pResource, RS_RES_MAP_TO_PARAMS *pParams) { + return pResource->__dbgbufMapTo__(pResource, pParams); } static inline NvU32 dbgbufGetRefCount_DISPATCH(struct DebugBufferApi *pResource) { return pResource->__dbgbufGetRefCount__(pResource); } -static inline NV_STATUS dbgbufCheckMemInterUnmap_DISPATCH(struct DebugBufferApi *pRmResource, NvBool bSubdeviceHandleProvided) { - return pRmResource->__dbgbufCheckMemInterUnmap__(pRmResource, bSubdeviceHandleProvided); -} - -static inline NV_STATUS dbgbufMapTo_DISPATCH(struct DebugBufferApi *pResource, RS_RES_MAP_TO_PARAMS *pParams) { - return pResource->__dbgbufMapTo__(pResource, pParams); +static inline void dbgbufAddAdditionalDependants_DISPATCH(struct RsClient *pClient, struct DebugBufferApi *pResource, RsResourceRef *pReference) { + pResource->__dbgbufAddAdditionalDependants__(pClient, pResource, pReference); } static inline NV_STATUS dbgbufControl_Prologue_DISPATCH(struct DebugBufferApi *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { @@ -206,26 +194,14 @@ return pGpuResource->__dbgbufGetRegBaseOffsetAndSize__(pGpuResource, pGpu, pOffset, pSize); } -static inline NvBool dbgbufCanCopy_DISPATCH(struct DebugBufferApi *pResource) { - return pResource->__dbgbufCanCopy__(pResource); -} - static inline NV_STATUS dbgbufInternalControlForward_DISPATCH(struct DebugBufferApi *pGpuResource, NvU32 command, void *pParams, NvU32 size) { return pGpuResource->__dbgbufInternalControlForward__(pGpuResource, command, pParams, size); } -static inline void dbgbufPreDestruct_DISPATCH(struct DebugBufferApi *pResource) { - pResource->__dbgbufPreDestruct__(pResource); -} - static inline NV_STATUS dbgbufUnmapFrom_DISPATCH(struct DebugBufferApi *pResource, RS_RES_UNMAP_FROM_PARAMS *pParams) { return pResource->__dbgbufUnmapFrom__(pResource, pParams); } -static inline NV_STATUS dbgbufIsDuplicate_DISPATCH(struct DebugBufferApi *pResource, NvHandle hMemory, NvBool *pDuplicate) { - return pResource->__dbgbufIsDuplicate__(pResource, hMemory, pDuplicate); -} - static inline void dbgbufControl_Epilogue_DISPATCH(struct DebugBufferApi *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { pResource->__dbgbufControl_Epilogue__(pResource, pCallContext, pParams); } @@ -234,6 +210,42 @@ return pResource->__dbgbufControlLookup__(pResource, pParams, ppEntry); } +static inline NvHandle dbgbufGetInternalObjectHandle_DISPATCH(struct DebugBufferApi *pGpuResource) { + return pGpuResource->__dbgbufGetInternalObjectHandle__(pGpuResource); +} + +static inline NV_STATUS dbgbufControl_DISPATCH(struct DebugBufferApi *pGpuResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return pGpuResource->__dbgbufControl__(pGpuResource, pCallContext, pParams); +} + +static inline NV_STATUS dbgbufGetMemInterMapParams_DISPATCH(struct DebugBufferApi *pRmResource, RMRES_MEM_INTER_MAP_PARAMS *pParams) { + return pRmResource->__dbgbufGetMemInterMapParams__(pRmResource, pParams); +} + +static inline NV_STATUS dbgbufControlFilter_DISPATCH(struct DebugBufferApi *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return pResource->__dbgbufControlFilter__(pResource, pCallContext, pParams); +} + +static inline NV_STATUS dbgbufControlSerialization_Prologue_DISPATCH(struct DebugBufferApi *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return pResource->__dbgbufControlSerialization_Prologue__(pResource, pCallContext, pParams); +} + +static inline NvBool dbgbufCanCopy_DISPATCH(struct DebugBufferApi *pResource) { + return pResource->__dbgbufCanCopy__(pResource); +} + +static inline void dbgbufPreDestruct_DISPATCH(struct DebugBufferApi *pResource) { + pResource->__dbgbufPreDestruct__(pResource); +} + +static inline NV_STATUS dbgbufIsDuplicate_DISPATCH(struct DebugBufferApi *pResource, NvHandle hMemory, NvBool *pDuplicate) { + return pResource->__dbgbufIsDuplicate__(pResource, hMemory, pDuplicate); +} + +static inline void dbgbufControlSerialization_Epilogue_DISPATCH(struct DebugBufferApi *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + pResource->__dbgbufControlSerialization_Epilogue__(pResource, pCallContext, pParams); +} + static inline NvBool dbgbufAccessCallback_DISPATCH(struct DebugBufferApi *pResource, struct RsClient *pInvokingClient, void *pAllocParams, RsAccessRight accessRight) { return pResource->__dbgbufAccessCallback__(pResource, pInvokingClient, pAllocParams, accessRight); } diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/generated/g_dce_client_nvoc.h nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_dce_client_nvoc.h --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/generated/g_dce_client_nvoc.h 2023-10-25 20:26:54.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_dce_client_nvoc.h 2024-03-05 22:18:10.000000000 +0000 @@ -66,7 +66,6 @@ struct OBJDCECLIENTRM *__nvoc_pbase_OBJDCECLIENTRM; NV_STATUS (*__dceclientConstructEngine__)(struct OBJGPU *, struct OBJDCECLIENTRM *, ENGDESCRIPTOR); void (*__dceclientStateDestroy__)(struct OBJGPU *, struct OBJDCECLIENTRM *); - NV_STATUS (*__dceclientReconcileTunableState__)(POBJGPU, struct OBJDCECLIENTRM *, void *); NV_STATUS (*__dceclientStateLoad__)(POBJGPU, struct OBJDCECLIENTRM *, NvU32); NV_STATUS (*__dceclientStateUnload__)(POBJGPU, struct OBJDCECLIENTRM *, NvU32); NV_STATUS (*__dceclientStateInitLocked__)(POBJGPU, struct OBJDCECLIENTRM *); @@ -77,12 +76,7 @@ void (*__dceclientInitMissing__)(POBJGPU, struct OBJDCECLIENTRM *); NV_STATUS (*__dceclientStatePreInitLocked__)(POBJGPU, struct OBJDCECLIENTRM *); NV_STATUS (*__dceclientStatePreInitUnlocked__)(POBJGPU, struct OBJDCECLIENTRM *); - NV_STATUS (*__dceclientGetTunableState__)(POBJGPU, struct OBJDCECLIENTRM *, void *); - NV_STATUS (*__dceclientCompareTunableState__)(POBJGPU, struct OBJDCECLIENTRM *, void *, void *); - void (*__dceclientFreeTunableState__)(POBJGPU, struct OBJDCECLIENTRM *, void *); NV_STATUS (*__dceclientStatePostLoad__)(POBJGPU, struct OBJDCECLIENTRM *, NvU32); - NV_STATUS (*__dceclientAllocTunableState__)(POBJGPU, struct OBJDCECLIENTRM *, void **); - NV_STATUS (*__dceclientSetTunableState__)(POBJGPU, struct OBJDCECLIENTRM *, void *); NvBool (*__dceclientIsPresent__)(POBJGPU, struct OBJDCECLIENTRM *); struct OBJRPC *pRpc; NvU32 clientId[2]; @@ -120,7 +114,6 @@ #define dceclientConstructEngine(arg0, arg1, arg2) dceclientConstructEngine_DISPATCH(arg0, arg1, arg2) #define dceclientStateDestroy(arg0, arg1) dceclientStateDestroy_DISPATCH(arg0, arg1) -#define dceclientReconcileTunableState(pGpu, pEngstate, pTunableState) dceclientReconcileTunableState_DISPATCH(pGpu, pEngstate, pTunableState) #define dceclientStateLoad(pGpu, pEngstate, arg0) dceclientStateLoad_DISPATCH(pGpu, pEngstate, arg0) #define dceclientStateUnload(pGpu, pEngstate, arg0) dceclientStateUnload_DISPATCH(pGpu, pEngstate, arg0) #define dceclientStateInitLocked(pGpu, pEngstate) dceclientStateInitLocked_DISPATCH(pGpu, pEngstate) @@ -131,12 +124,7 @@ #define dceclientInitMissing(pGpu, pEngstate) dceclientInitMissing_DISPATCH(pGpu, pEngstate) #define dceclientStatePreInitLocked(pGpu, pEngstate) dceclientStatePreInitLocked_DISPATCH(pGpu, pEngstate) #define dceclientStatePreInitUnlocked(pGpu, pEngstate) dceclientStatePreInitUnlocked_DISPATCH(pGpu, pEngstate) -#define dceclientGetTunableState(pGpu, pEngstate, pTunableState) dceclientGetTunableState_DISPATCH(pGpu, pEngstate, pTunableState) -#define dceclientCompareTunableState(pGpu, pEngstate, pTunables1, pTunables2) dceclientCompareTunableState_DISPATCH(pGpu, pEngstate, pTunables1, pTunables2) -#define dceclientFreeTunableState(pGpu, pEngstate, pTunableState) dceclientFreeTunableState_DISPATCH(pGpu, pEngstate, pTunableState) #define dceclientStatePostLoad(pGpu, pEngstate, arg0) dceclientStatePostLoad_DISPATCH(pGpu, pEngstate, arg0) -#define dceclientAllocTunableState(pGpu, pEngstate, ppTunableState) dceclientAllocTunableState_DISPATCH(pGpu, pEngstate, ppTunableState) -#define dceclientSetTunableState(pGpu, pEngstate, pTunableState) dceclientSetTunableState_DISPATCH(pGpu, pEngstate, pTunableState) #define dceclientIsPresent(pGpu, pEngstate) dceclientIsPresent_DISPATCH(pGpu, pEngstate) NV_STATUS dceclientConstructEngine_IMPL(struct OBJGPU *arg0, struct OBJDCECLIENTRM *arg1, ENGDESCRIPTOR arg2); @@ -150,10 +138,6 @@ arg1->__dceclientStateDestroy__(arg0, arg1); } -static inline NV_STATUS dceclientReconcileTunableState_DISPATCH(POBJGPU pGpu, struct OBJDCECLIENTRM *pEngstate, void *pTunableState) { - return pEngstate->__dceclientReconcileTunableState__(pGpu, pEngstate, pTunableState); -} - static inline NV_STATUS dceclientStateLoad_DISPATCH(POBJGPU pGpu, struct OBJDCECLIENTRM *pEngstate, NvU32 arg0) { return pEngstate->__dceclientStateLoad__(pGpu, pEngstate, arg0); } @@ -194,30 +178,10 @@ return pEngstate->__dceclientStatePreInitUnlocked__(pGpu, pEngstate); } -static inline NV_STATUS dceclientGetTunableState_DISPATCH(POBJGPU pGpu, struct OBJDCECLIENTRM *pEngstate, void *pTunableState) { - return pEngstate->__dceclientGetTunableState__(pGpu, pEngstate, pTunableState); -} - -static inline NV_STATUS dceclientCompareTunableState_DISPATCH(POBJGPU pGpu, struct OBJDCECLIENTRM *pEngstate, void *pTunables1, void *pTunables2) { - return pEngstate->__dceclientCompareTunableState__(pGpu, pEngstate, pTunables1, pTunables2); -} - -static inline void dceclientFreeTunableState_DISPATCH(POBJGPU pGpu, struct OBJDCECLIENTRM *pEngstate, void *pTunableState) { - pEngstate->__dceclientFreeTunableState__(pGpu, pEngstate, pTunableState); -} - static inline NV_STATUS dceclientStatePostLoad_DISPATCH(POBJGPU pGpu, struct OBJDCECLIENTRM *pEngstate, NvU32 arg0) { return pEngstate->__dceclientStatePostLoad__(pGpu, pEngstate, arg0); } -static inline NV_STATUS dceclientAllocTunableState_DISPATCH(POBJGPU pGpu, struct OBJDCECLIENTRM *pEngstate, void **ppTunableState) { - return pEngstate->__dceclientAllocTunableState__(pGpu, pEngstate, ppTunableState); -} - -static inline NV_STATUS dceclientSetTunableState_DISPATCH(POBJGPU pGpu, struct OBJDCECLIENTRM *pEngstate, void *pTunableState) { - return pEngstate->__dceclientSetTunableState__(pGpu, pEngstate, pTunableState); -} - static inline NvBool dceclientIsPresent_DISPATCH(POBJGPU pGpu, struct OBJDCECLIENTRM *pEngstate) { return pEngstate->__dceclientIsPresent__(pGpu, pEngstate); } @@ -275,7 +239,7 @@ NV_STATUS rpcRmApiAlloc_dce(RM_API *pRmApi, NvHandle hClient, NvHandle hParent, NvHandle hObject, NvU32 hClass, - void *pAllocParams); + void *pAllocParams, NvU32 allocParamsSize); NV_STATUS rpcRmApiDupObject_dce(RM_API *pRmApi, NvHandle hClient, NvHandle hParent, NvHandle *phObject, NvHandle hClientSrc, NvHandle hObjectSrc, NvU32 flags); diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/generated/g_deferred_api_nvoc.c nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_deferred_api_nvoc.c --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/generated/g_deferred_api_nvoc.c 2023-10-25 20:26:54.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_deferred_api_nvoc.c 2024-03-05 22:18:10.000000000 +0000 @@ -120,7 +120,7 @@ /*pExportInfo=*/ &__nvoc_export_info_DeferredApiObject }; -static NV_STATUS __nvoc_thunk_DeferredApiObject_chandesGetSwMethods(struct ChannelDescendant *pDeferredApi, METHOD **ppMethods, NvU32 *pNumMethods) { +static NV_STATUS __nvoc_thunk_DeferredApiObject_chandesGetSwMethods(struct ChannelDescendant *pDeferredApi, const METHOD **ppMethods, NvU32 *pNumMethods) { return defapiGetSwMethods((struct DeferredApiObject *)(((unsigned char *)pDeferredApi) - __nvoc_rtti_DeferredApiObject_ChannelDescendant.offset), ppMethods, pNumMethods); } @@ -212,6 +212,10 @@ return notifyUnregisterEvent((struct Notifier *)(((unsigned char *)pNotifier) + __nvoc_rtti_DeferredApiObject_Notifier.offset), hNotifierClient, hNotifierResource, hEventClient, hEvent); } +static NV_STATUS __nvoc_thunk_RmResource_defapiControlSerialization_Prologue(struct DeferredApiObject *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return rmresControlSerialization_Prologue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_DeferredApiObject_RmResource.offset), pCallContext, pParams); +} + static NvBool __nvoc_thunk_RsResource_defapiCanCopy(struct DeferredApiObject *pResource) { return resCanCopy((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_DeferredApiObject_RsResource.offset)); } @@ -224,6 +228,10 @@ return resIsDuplicate((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_DeferredApiObject_RsResource.offset), hMemory, pDuplicate); } +static void __nvoc_thunk_RmResource_defapiControlSerialization_Epilogue(struct DeferredApiObject *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + rmresControlSerialization_Epilogue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_DeferredApiObject_RmResource.offset), pCallContext, pParams); +} + static PEVENTNOTIFICATION *__nvoc_thunk_Notifier_defapiGetNotificationListPtr(struct DeferredApiObject *pNotifier) { return notifyGetNotificationListPtr((struct Notifier *)(((unsigned char *)pNotifier) + __nvoc_rtti_DeferredApiObject_Notifier.offset)); } @@ -247,12 +255,12 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_DeferredApiObject[] = { { /* [0] */ -#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) /*pFunc=*/ (void (*)(void)) NULL, #else /*pFunc=*/ (void (*)(void)) defapiCtrlCmdDeferredApi_IMPL, -#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) - /*flags=*/ 0x10u, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) + /*flags=*/ 0x210u, /*accessRight=*/0x0u, /*methodId=*/ 0x50800101u, /*paramSize=*/ sizeof(NV5080_CTRL_DEFERRED_API_PARAMS), @@ -262,12 +270,12 @@ #endif }, { /* [1] */ -#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) /*pFunc=*/ (void (*)(void)) NULL, #else /*pFunc=*/ (void (*)(void)) defapiCtrlCmdRemoveApi_IMPL, -#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) - /*flags=*/ 0x10u, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) + /*flags=*/ 0x210u, /*accessRight=*/0x0u, /*methodId=*/ 0x50800102u, /*paramSize=*/ sizeof(NV5080_CTRL_REMOVE_API_PARAMS), @@ -277,12 +285,12 @@ #endif }, { /* [2] */ -#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) /*pFunc=*/ (void (*)(void)) NULL, #else /*pFunc=*/ (void (*)(void)) defapiCtrlCmdDeferredApiV2_IMPL, -#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) - /*flags=*/ 0x10u, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) + /*flags=*/ 0x210u, /*accessRight=*/0x0u, /*methodId=*/ 0x50800103u, /*paramSize=*/ sizeof(NV5080_CTRL_DEFERRED_API_V2_PARAMS), @@ -337,15 +345,15 @@ pThis->__defapiIsSwMethodStalling__ = &defapiIsSwMethodStalling_IMPL; -#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) +#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) pThis->__defapiCtrlCmdDeferredApi__ = &defapiCtrlCmdDeferredApi_IMPL; #endif -#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) +#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) pThis->__defapiCtrlCmdDeferredApiV2__ = &defapiCtrlCmdDeferredApiV2_IMPL; #endif -#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) +#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) pThis->__defapiCtrlCmdRemoveApi__ = &defapiCtrlCmdRemoveApi_IMPL; #endif @@ -395,12 +403,16 @@ pThis->__defapiUnregisterEvent__ = &__nvoc_thunk_Notifier_defapiUnregisterEvent; + pThis->__defapiControlSerialization_Prologue__ = &__nvoc_thunk_RmResource_defapiControlSerialization_Prologue; + pThis->__defapiCanCopy__ = &__nvoc_thunk_RsResource_defapiCanCopy; pThis->__defapiPreDestruct__ = &__nvoc_thunk_RsResource_defapiPreDestruct; pThis->__defapiIsDuplicate__ = &__nvoc_thunk_RsResource_defapiIsDuplicate; + pThis->__defapiControlSerialization_Epilogue__ = &__nvoc_thunk_RmResource_defapiControlSerialization_Epilogue; + pThis->__defapiGetNotificationListPtr__ = &__nvoc_thunk_Notifier_defapiGetNotificationListPtr; pThis->__defapiGetNotificationShare__ = &__nvoc_thunk_Notifier_defapiGetNotificationShare; @@ -435,13 +447,16 @@ DeferredApiObject *pThis; RmHalspecOwner *pRmhalspecowner; - pThis = portMemAllocNonPaged(sizeof(DeferredApiObject)); - if (pThis == NULL) return NV_ERR_NO_MEMORY; + status = __nvoc_handleObjCreateMemAlloc(createFlags, sizeof(DeferredApiObject), (void**)&pThis, (void**)ppThis); + if (status != NV_OK) + return status; portMemSet(pThis, 0, sizeof(DeferredApiObject)); __nvoc_initRtti(staticCast(pThis, Dynamic), &__nvoc_class_def_DeferredApiObject); + pThis->__nvoc_base_ChannelDescendant.__nvoc_base_GpuResource.__nvoc_base_RmResource.__nvoc_base_RsResource.__nvoc_base_Object.createFlags = createFlags; + if (pParent != NULL && !(createFlags & NVOC_OBJ_CREATE_FLAGS_PARENT_HALSPEC_ONLY)) { pParentObj = dynamicCast(pParent, Object); @@ -461,11 +476,17 @@ if (status != NV_OK) goto __nvoc_objCreate_DeferredApiObject_cleanup; *ppThis = pThis; + return NV_OK; __nvoc_objCreate_DeferredApiObject_cleanup: // do not call destructors here since the constructor already called them - portMemFree(pThis); + if (createFlags & NVOC_OBJ_CREATE_FLAGS_IN_PLACE_CONSTRUCT) + portMemSet(pThis, 0, sizeof(DeferredApiObject)); + else + portMemFree(pThis); + + // coverity[leaked_storage:FALSE] return status; } diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/generated/g_deferred_api_nvoc.h nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_deferred_api_nvoc.h --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/generated/g_deferred_api_nvoc.h 2023-10-25 20:26:54.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_deferred_api_nvoc.h 2024-03-05 22:18:10.000000000 +0000 @@ -75,7 +75,7 @@ struct Notifier *__nvoc_pbase_Notifier; struct ChannelDescendant *__nvoc_pbase_ChannelDescendant; struct DeferredApiObject *__nvoc_pbase_DeferredApiObject; - NV_STATUS (*__defapiGetSwMethods__)(struct DeferredApiObject *, METHOD **, NvU32 *); + NV_STATUS (*__defapiGetSwMethods__)(struct DeferredApiObject *, const METHOD **, NvU32 *); NvBool (*__defapiIsSwMethodStalling__)(struct DeferredApiObject *, NvU32); NV_STATUS (*__defapiCtrlCmdDeferredApi__)(struct DeferredApiObject *, NV5080_CTRL_DEFERRED_API_PARAMS *); NV_STATUS (*__defapiCtrlCmdDeferredApiV2__)(struct DeferredApiObject *, NV5080_CTRL_DEFERRED_API_V2_PARAMS *); @@ -101,9 +101,11 @@ NV_STATUS (*__defapiGetMemoryMappingDescriptor__)(struct DeferredApiObject *, struct MEMORY_DESCRIPTOR **); NV_STATUS (*__defapiControlFilter__)(struct DeferredApiObject *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); NV_STATUS (*__defapiUnregisterEvent__)(struct DeferredApiObject *, NvHandle, NvHandle, NvHandle, NvHandle); + NV_STATUS (*__defapiControlSerialization_Prologue__)(struct DeferredApiObject *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); NvBool (*__defapiCanCopy__)(struct DeferredApiObject *); void (*__defapiPreDestruct__)(struct DeferredApiObject *); NV_STATUS (*__defapiIsDuplicate__)(struct DeferredApiObject *, NvHandle, NvBool *); + void (*__defapiControlSerialization_Epilogue__)(struct DeferredApiObject *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); PEVENTNOTIFICATION *(*__defapiGetNotificationListPtr__)(struct DeferredApiObject *); struct NotifShare *(*__defapiGetNotificationShare__)(struct DeferredApiObject *); NV_STATUS (*__defapiMap__)(struct DeferredApiObject *, struct CALL_CONTEXT *, struct RS_CPU_MAP_PARAMS *, struct RsCpuMapping *); @@ -166,16 +168,18 @@ #define defapiGetMemoryMappingDescriptor(pRmResource, ppMemDesc) defapiGetMemoryMappingDescriptor_DISPATCH(pRmResource, ppMemDesc) #define defapiControlFilter(pResource, pCallContext, pParams) defapiControlFilter_DISPATCH(pResource, pCallContext, pParams) #define defapiUnregisterEvent(pNotifier, hNotifierClient, hNotifierResource, hEventClient, hEvent) defapiUnregisterEvent_DISPATCH(pNotifier, hNotifierClient, hNotifierResource, hEventClient, hEvent) +#define defapiControlSerialization_Prologue(pResource, pCallContext, pParams) defapiControlSerialization_Prologue_DISPATCH(pResource, pCallContext, pParams) #define defapiCanCopy(pResource) defapiCanCopy_DISPATCH(pResource) #define defapiPreDestruct(pResource) defapiPreDestruct_DISPATCH(pResource) #define defapiIsDuplicate(pResource, hMemory, pDuplicate) defapiIsDuplicate_DISPATCH(pResource, hMemory, pDuplicate) +#define defapiControlSerialization_Epilogue(pResource, pCallContext, pParams) defapiControlSerialization_Epilogue_DISPATCH(pResource, pCallContext, pParams) #define defapiGetNotificationListPtr(pNotifier) defapiGetNotificationListPtr_DISPATCH(pNotifier) #define defapiGetNotificationShare(pNotifier) defapiGetNotificationShare_DISPATCH(pNotifier) #define defapiMap(pGpuResource, pCallContext, pParams, pCpuMapping) defapiMap_DISPATCH(pGpuResource, pCallContext, pParams, pCpuMapping) #define defapiGetOrAllocNotifShare(pNotifier, hNotifierClient, hNotifierResource, ppNotifShare) defapiGetOrAllocNotifShare_DISPATCH(pNotifier, hNotifierClient, hNotifierResource, ppNotifShare) -NV_STATUS defapiGetSwMethods_IMPL(struct DeferredApiObject *pDeferredApi, METHOD **ppMethods, NvU32 *pNumMethods); +NV_STATUS defapiGetSwMethods_IMPL(struct DeferredApiObject *pDeferredApi, const METHOD **ppMethods, NvU32 *pNumMethods); -static inline NV_STATUS defapiGetSwMethods_DISPATCH(struct DeferredApiObject *pDeferredApi, METHOD **ppMethods, NvU32 *pNumMethods) { +static inline NV_STATUS defapiGetSwMethods_DISPATCH(struct DeferredApiObject *pDeferredApi, const METHOD **ppMethods, NvU32 *pNumMethods) { return pDeferredApi->__defapiGetSwMethods__(pDeferredApi, ppMethods, pNumMethods); } @@ -287,6 +291,10 @@ return pNotifier->__defapiUnregisterEvent__(pNotifier, hNotifierClient, hNotifierResource, hEventClient, hEvent); } +static inline NV_STATUS defapiControlSerialization_Prologue_DISPATCH(struct DeferredApiObject *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return pResource->__defapiControlSerialization_Prologue__(pResource, pCallContext, pParams); +} + static inline NvBool defapiCanCopy_DISPATCH(struct DeferredApiObject *pResource) { return pResource->__defapiCanCopy__(pResource); } @@ -299,6 +307,10 @@ return pResource->__defapiIsDuplicate__(pResource, hMemory, pDuplicate); } +static inline void defapiControlSerialization_Epilogue_DISPATCH(struct DeferredApiObject *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + pResource->__defapiControlSerialization_Epilogue__(pResource, pCallContext, pParams); +} + static inline PEVENTNOTIFICATION *defapiGetNotificationListPtr_DISPATCH(struct DeferredApiObject *pNotifier) { return pNotifier->__defapiGetNotificationListPtr__(pNotifier); } diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/generated/g_device_nvoc.c nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_device_nvoc.c --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/generated/g_device_nvoc.c 2023-10-25 20:26:54.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_device_nvoc.c 2024-03-05 22:18:10.000000000 +0000 @@ -105,52 +105,68 @@ return gpuresShareCallback((struct GpuResource *)(((unsigned char *)pGpuResource) + __nvoc_rtti_Device_GpuResource.offset), pInvokingClient, pParentRef, pSharePolicy); } -static NV_STATUS __nvoc_thunk_GpuResource_deviceUnmap(struct Device *pGpuResource, struct CALL_CONTEXT *pCallContext, struct RsCpuMapping *pCpuMapping) { - return gpuresUnmap((struct GpuResource *)(((unsigned char *)pGpuResource) + __nvoc_rtti_Device_GpuResource.offset), pCallContext, pCpuMapping); -} - -static NV_STATUS __nvoc_thunk_RmResource_deviceGetMemInterMapParams(struct Device *pRmResource, RMRES_MEM_INTER_MAP_PARAMS *pParams) { - return rmresGetMemInterMapParams((struct RmResource *)(((unsigned char *)pRmResource) + __nvoc_rtti_Device_RmResource.offset), pParams); +static NV_STATUS __nvoc_thunk_RmResource_deviceCheckMemInterUnmap(struct Device *pRmResource, NvBool bSubdeviceHandleProvided) { + return rmresCheckMemInterUnmap((struct RmResource *)(((unsigned char *)pRmResource) + __nvoc_rtti_Device_RmResource.offset), bSubdeviceHandleProvided); } -static NV_STATUS __nvoc_thunk_RmResource_deviceGetMemoryMappingDescriptor(struct Device *pRmResource, struct MEMORY_DESCRIPTOR **ppMemDesc) { - return rmresGetMemoryMappingDescriptor((struct RmResource *)(((unsigned char *)pRmResource) + __nvoc_rtti_Device_RmResource.offset), ppMemDesc); +static NV_STATUS __nvoc_thunk_RsResource_deviceMapTo(struct Device *pResource, RS_RES_MAP_TO_PARAMS *pParams) { + return resMapTo((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_Device_RsResource.offset), pParams); } static NV_STATUS __nvoc_thunk_GpuResource_deviceGetMapAddrSpace(struct Device *pGpuResource, struct CALL_CONTEXT *pCallContext, NvU32 mapFlags, NV_ADDRESS_SPACE *pAddrSpace) { return gpuresGetMapAddrSpace((struct GpuResource *)(((unsigned char *)pGpuResource) + __nvoc_rtti_Device_GpuResource.offset), pCallContext, mapFlags, pAddrSpace); } -static NvHandle __nvoc_thunk_GpuResource_deviceGetInternalObjectHandle(struct Device *pGpuResource) { - return gpuresGetInternalObjectHandle((struct GpuResource *)(((unsigned char *)pGpuResource) + __nvoc_rtti_Device_GpuResource.offset)); -} - -static NV_STATUS __nvoc_thunk_RsResource_deviceControlFilter(struct Device *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { - return resControlFilter((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_Device_RsResource.offset), pCallContext, pParams); +static NvU32 __nvoc_thunk_RsResource_deviceGetRefCount(struct Device *pResource) { + return resGetRefCount((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_Device_RsResource.offset)); } static void __nvoc_thunk_RsResource_deviceAddAdditionalDependants(struct RsClient *pClient, struct Device *pResource, RsResourceRef *pReference) { resAddAdditionalDependants(pClient, (struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_Device_RsResource.offset), pReference); } -static NvU32 __nvoc_thunk_RsResource_deviceGetRefCount(struct Device *pResource) { - return resGetRefCount((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_Device_RsResource.offset)); +static NV_STATUS __nvoc_thunk_RmResource_deviceControl_Prologue(struct Device *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return rmresControl_Prologue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_Device_RmResource.offset), pCallContext, pParams); } -static NV_STATUS __nvoc_thunk_RmResource_deviceCheckMemInterUnmap(struct Device *pRmResource, NvBool bSubdeviceHandleProvided) { - return rmresCheckMemInterUnmap((struct RmResource *)(((unsigned char *)pRmResource) + __nvoc_rtti_Device_RmResource.offset), bSubdeviceHandleProvided); +static NV_STATUS __nvoc_thunk_GpuResource_deviceGetRegBaseOffsetAndSize(struct Device *pGpuResource, struct OBJGPU *pGpu, NvU32 *pOffset, NvU32 *pSize) { + return gpuresGetRegBaseOffsetAndSize((struct GpuResource *)(((unsigned char *)pGpuResource) + __nvoc_rtti_Device_GpuResource.offset), pGpu, pOffset, pSize); } -static NV_STATUS __nvoc_thunk_RsResource_deviceMapTo(struct Device *pResource, RS_RES_MAP_TO_PARAMS *pParams) { - return resMapTo((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_Device_RsResource.offset), pParams); +static NV_STATUS __nvoc_thunk_RsResource_deviceUnmapFrom(struct Device *pResource, RS_RES_UNMAP_FROM_PARAMS *pParams) { + return resUnmapFrom((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_Device_RsResource.offset), pParams); } -static NV_STATUS __nvoc_thunk_RmResource_deviceControl_Prologue(struct Device *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { - return rmresControl_Prologue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_Device_RmResource.offset), pCallContext, pParams); +static void __nvoc_thunk_RmResource_deviceControl_Epilogue(struct Device *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + rmresControl_Epilogue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_Device_RmResource.offset), pCallContext, pParams); } -static NV_STATUS __nvoc_thunk_GpuResource_deviceGetRegBaseOffsetAndSize(struct Device *pGpuResource, struct OBJGPU *pGpu, NvU32 *pOffset, NvU32 *pSize) { - return gpuresGetRegBaseOffsetAndSize((struct GpuResource *)(((unsigned char *)pGpuResource) + __nvoc_rtti_Device_GpuResource.offset), pGpu, pOffset, pSize); +static NV_STATUS __nvoc_thunk_RsResource_deviceControlLookup(struct Device *pResource, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams, const struct NVOC_EXPORTED_METHOD_DEF **ppEntry) { + return resControlLookup((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_Device_RsResource.offset), pParams, ppEntry); +} + +static NvHandle __nvoc_thunk_GpuResource_deviceGetInternalObjectHandle(struct Device *pGpuResource) { + return gpuresGetInternalObjectHandle((struct GpuResource *)(((unsigned char *)pGpuResource) + __nvoc_rtti_Device_GpuResource.offset)); +} + +static NV_STATUS __nvoc_thunk_GpuResource_deviceUnmap(struct Device *pGpuResource, struct CALL_CONTEXT *pCallContext, struct RsCpuMapping *pCpuMapping) { + return gpuresUnmap((struct GpuResource *)(((unsigned char *)pGpuResource) + __nvoc_rtti_Device_GpuResource.offset), pCallContext, pCpuMapping); +} + +static NV_STATUS __nvoc_thunk_RmResource_deviceGetMemInterMapParams(struct Device *pRmResource, RMRES_MEM_INTER_MAP_PARAMS *pParams) { + return rmresGetMemInterMapParams((struct RmResource *)(((unsigned char *)pRmResource) + __nvoc_rtti_Device_RmResource.offset), pParams); +} + +static NV_STATUS __nvoc_thunk_RmResource_deviceGetMemoryMappingDescriptor(struct Device *pRmResource, struct MEMORY_DESCRIPTOR **ppMemDesc) { + return rmresGetMemoryMappingDescriptor((struct RmResource *)(((unsigned char *)pRmResource) + __nvoc_rtti_Device_RmResource.offset), ppMemDesc); +} + +static NV_STATUS __nvoc_thunk_RsResource_deviceControlFilter(struct Device *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return resControlFilter((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_Device_RsResource.offset), pCallContext, pParams); +} + +static NV_STATUS __nvoc_thunk_RmResource_deviceControlSerialization_Prologue(struct Device *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return rmresControlSerialization_Prologue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_Device_RmResource.offset), pCallContext, pParams); } static NvBool __nvoc_thunk_RsResource_deviceCanCopy(struct Device *pResource) { @@ -161,20 +177,12 @@ resPreDestruct((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_Device_RsResource.offset)); } -static NV_STATUS __nvoc_thunk_RsResource_deviceUnmapFrom(struct Device *pResource, RS_RES_UNMAP_FROM_PARAMS *pParams) { - return resUnmapFrom((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_Device_RsResource.offset), pParams); -} - static NV_STATUS __nvoc_thunk_RsResource_deviceIsDuplicate(struct Device *pResource, NvHandle hMemory, NvBool *pDuplicate) { return resIsDuplicate((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_Device_RsResource.offset), hMemory, pDuplicate); } -static void __nvoc_thunk_RmResource_deviceControl_Epilogue(struct Device *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { - rmresControl_Epilogue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_Device_RmResource.offset), pCallContext, pParams); -} - -static NV_STATUS __nvoc_thunk_RsResource_deviceControlLookup(struct Device *pResource, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams, const struct NVOC_EXPORTED_METHOD_DEF **ppEntry) { - return resControlLookup((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_Device_RsResource.offset), pParams, ppEntry); +static void __nvoc_thunk_RmResource_deviceControlSerialization_Epilogue(struct Device *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + rmresControlSerialization_Epilogue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_Device_RmResource.offset), pCallContext, pParams); } static NV_STATUS __nvoc_thunk_GpuResource_deviceMap(struct Device *pGpuResource, struct CALL_CONTEXT *pCallContext, struct RS_CPU_MAP_PARAMS *pParams, struct RsCpuMapping *pCpuMapping) { @@ -237,6 +245,21 @@ #endif }, { /* [3] */ +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x200u) + /*pFunc=*/ (void (*)(void)) NULL, +#else + /*pFunc=*/ (void (*)(void)) deviceCtrlCmdBifGetPciePowerControlMask_IMPL, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x200u) + /*flags=*/ 0x200u, + /*accessRight=*/0x0u, + /*methodId=*/ 0x800106u, + /*paramSize=*/ sizeof(NV0080_CTRL_CMD_BIF_GET_PCIE_POWER_CONTROL_MASK_PARAMS), + /*pClassInfo=*/ &(__nvoc_class_def_Device.classInfo), +#if NV_PRINTF_STRINGS_ALLOWED + /*func=*/ "deviceCtrlCmdBifGetPciePowerControlMask" +#endif + }, + { /* [4] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x813u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -251,13 +274,13 @@ /*func=*/ "deviceCtrlCmdGpuGetClasslist" #endif }, - { /* [4] */ -#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x811u) + { /* [5] */ +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x4811u) /*pFunc=*/ (void (*)(void)) NULL, #else /*pFunc=*/ (void (*)(void)) deviceCtrlCmdGpuGetNumSubdevices_IMPL, -#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x811u) - /*flags=*/ 0x811u, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x4811u) + /*flags=*/ 0x4811u, /*accessRight=*/0x0u, /*methodId=*/ 0x800280u, /*paramSize=*/ sizeof(NV0080_CTRL_GPU_GET_NUM_SUBDEVICES_PARAMS), @@ -266,7 +289,7 @@ /*func=*/ "deviceCtrlCmdGpuGetNumSubdevices" #endif }, - { /* [5] */ + { /* [6] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x5u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -281,7 +304,7 @@ /*func=*/ "deviceCtrlCmdGpuModifyGpuSwStatePersistence" #endif }, - { /* [6] */ + { /* [7] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x11u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -296,13 +319,13 @@ /*func=*/ "deviceCtrlCmdGpuQueryGpuSwStatePersistence" #endif }, - { /* [7] */ -#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x810u) + { /* [8] */ +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x811u) /*pFunc=*/ (void (*)(void)) NULL, #else /*pFunc=*/ (void (*)(void)) deviceCtrlCmdGpuGetVirtualizationMode_IMPL, -#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x810u) - /*flags=*/ 0x810u, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x811u) + /*flags=*/ 0x811u, /*accessRight=*/0x0u, /*methodId=*/ 0x800289u, /*paramSize=*/ sizeof(NV0080_CTRL_GPU_GET_VIRTUALIZATION_MODE_PARAMS), @@ -311,7 +334,7 @@ /*func=*/ "deviceCtrlCmdGpuGetVirtualizationMode" #endif }, - { /* [8] */ + { /* [9] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x11u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -326,7 +349,7 @@ /*func=*/ "deviceCtrlCmdGpuGetSparseTextureComputeMode" #endif }, - { /* [9] */ + { /* [10] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x11u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -341,7 +364,7 @@ /*func=*/ "deviceCtrlCmdGpuSetSparseTextureComputeMode" #endif }, - { /* [10] */ + { /* [11] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x11u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -356,7 +379,7 @@ /*func=*/ "deviceCtrlCmdGpuGetVgxCaps" #endif }, - { /* [11] */ + { /* [12] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -371,7 +394,7 @@ /*func=*/ "deviceCtrlCmdGpuGetSriovCaps" #endif }, - { /* [12] */ + { /* [13] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x813u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -386,7 +409,7 @@ /*func=*/ "deviceCtrlCmdGpuGetClasslistV2" #endif }, - { /* [13] */ + { /* [14] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x13u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -401,7 +424,7 @@ /*func=*/ "deviceCtrlCmdGpuGetFindSubDeviceHandle" #endif }, - { /* [14] */ + { /* [15] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x211u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -416,7 +439,7 @@ /*func=*/ "deviceCtrlCmdGpuGetBrandCaps" #endif }, - { /* [15] */ + { /* [16] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x204u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -431,7 +454,7 @@ /*func=*/ "deviceCtrlCmdGpuSetVgpuVfBar1Size" #endif }, - { /* [16] */ + { /* [17] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x812u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -446,7 +469,7 @@ /*func=*/ "deviceCtrlCmdKGrGetCaps" #endif }, - { /* [17] */ + { /* [18] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x810u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -461,7 +484,7 @@ /*func=*/ "deviceCtrlCmdKGrGetInfo" #endif }, - { /* [18] */ + { /* [19] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x2210u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -476,7 +499,7 @@ /*func=*/ "deviceCtrlCmdKGrGetTpcPartitionMode" #endif }, - { /* [19] */ + { /* [20] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x2210u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -491,7 +514,7 @@ /*func=*/ "deviceCtrlCmdKGrSetTpcPartitionMode" #endif }, - { /* [20] */ + { /* [21] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x812u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -506,7 +529,7 @@ /*func=*/ "deviceCtrlCmdKGrGetCapsV2" #endif }, - { /* [21] */ + { /* [22] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -521,13 +544,13 @@ /*func=*/ "deviceCtrlCmdKGrGetInfoV2" #endif }, - { /* [22] */ -#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x11u) + { /* [23] */ +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x811u) /*pFunc=*/ (void (*)(void)) NULL, #else /*pFunc=*/ (void (*)(void)) deviceCtrlCmdFbGetCaps_IMPL, -#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x11u) - /*flags=*/ 0x11u, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x811u) + /*flags=*/ 0x811u, /*accessRight=*/0x0u, /*methodId=*/ 0x801301u, /*paramSize=*/ sizeof(NV0080_CTRL_FB_GET_CAPS_PARAMS), @@ -536,7 +559,7 @@ /*func=*/ "deviceCtrlCmdFbGetCaps" #endif }, - { /* [23] */ + { /* [24] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -551,13 +574,13 @@ /*func=*/ "deviceCtrlCmdFbGetCompbitStoreInfo" #endif }, - { /* [24] */ -#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x11u) + { /* [25] */ +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x4811u) /*pFunc=*/ (void (*)(void)) NULL, #else /*pFunc=*/ (void (*)(void)) deviceCtrlCmdFbGetCapsV2_IMPL, -#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x11u) - /*flags=*/ 0x11u, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x4811u) + /*flags=*/ 0x4811u, /*accessRight=*/0x0u, /*methodId=*/ 0x801307u, /*paramSize=*/ sizeof(NV0080_CTRL_FB_GET_CAPS_V2_PARAMS), @@ -566,13 +589,28 @@ /*func=*/ "deviceCtrlCmdFbGetCapsV2" #endif }, - { /* [25] */ -#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x810u) + { /* [26] */ +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x11u) + /*pFunc=*/ (void (*)(void)) NULL, +#else + /*pFunc=*/ (void (*)(void)) deviceCtrlCmdSetDefaultVidmemPhysicality_IMPL, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x11u) + /*flags=*/ 0x11u, + /*accessRight=*/0x0u, + /*methodId=*/ 0x801308u, + /*paramSize=*/ sizeof(NV0080_CTRL_FB_SET_DEFAULT_VIDMEM_PHYSICALITY_PARAMS), + /*pClassInfo=*/ &(__nvoc_class_def_Device.classInfo), +#if NV_PRINTF_STRINGS_ALLOWED + /*func=*/ "deviceCtrlCmdSetDefaultVidmemPhysicality" +#endif + }, + { /* [27] */ +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x850u) /*pFunc=*/ (void (*)(void)) NULL, #else /*pFunc=*/ (void (*)(void)) deviceCtrlCmdHostGetCaps_IMPL, -#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x810u) - /*flags=*/ 0x810u, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x850u) + /*flags=*/ 0x850u, /*accessRight=*/0x0u, /*methodId=*/ 0x801401u, /*paramSize=*/ sizeof(NV0080_CTRL_HOST_GET_CAPS_PARAMS), @@ -581,13 +619,13 @@ /*func=*/ "deviceCtrlCmdHostGetCaps" #endif }, - { /* [26] */ -#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x810u) + { /* [28] */ +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x4850u) /*pFunc=*/ (void (*)(void)) NULL, #else /*pFunc=*/ (void (*)(void)) deviceCtrlCmdHostGetCapsV2_IMPL, -#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x810u) - /*flags=*/ 0x810u, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x4850u) + /*flags=*/ 0x4850u, /*accessRight=*/0x0u, /*methodId=*/ 0x801402u, /*paramSize=*/ sizeof(NV0080_CTRL_HOST_GET_CAPS_V2_PARAMS), @@ -596,7 +634,7 @@ /*func=*/ "deviceCtrlCmdHostGetCapsV2" #endif }, - { /* [27] */ + { /* [29] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x810u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -611,7 +649,7 @@ /*func=*/ "deviceCtrlCmdFifoGetCaps" #endif }, - { /* [28] */ + { /* [30] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x2210u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -626,7 +664,7 @@ /*func=*/ "deviceCtrlCmdFifoStartSelectedChannels" #endif }, - { /* [29] */ + { /* [31] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x2210u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -641,13 +679,13 @@ /*func=*/ "deviceCtrlCmdFifoGetEngineContextProperties" #endif }, - { /* [30] */ -#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x810u) + { /* [32] */ +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x811u) /*pFunc=*/ (void (*)(void)) NULL, #else /*pFunc=*/ (void (*)(void)) deviceCtrlCmdFifoGetChannelList_IMPL, -#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x810u) - /*flags=*/ 0x810u, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x811u) + /*flags=*/ 0x811u, /*accessRight=*/0x0u, /*methodId=*/ 0x80170du, /*paramSize=*/ sizeof(NV0080_CTRL_FIFO_GET_CHANNELLIST_PARAMS), @@ -656,7 +694,7 @@ /*func=*/ "deviceCtrlCmdFifoGetChannelList" #endif }, - { /* [31] */ + { /* [33] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x2211u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -671,7 +709,7 @@ /*func=*/ "deviceCtrlCmdFifoGetLatencyBufferSize" #endif }, - { /* [32] */ + { /* [34] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x2210u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -686,7 +724,7 @@ /*func=*/ "deviceCtrlCmdFifoSetChannelProperties" #endif }, - { /* [33] */ + { /* [35] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x2204u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -701,7 +739,7 @@ /*func=*/ "deviceCtrlCmdFifoStopRunlist" #endif }, - { /* [34] */ + { /* [36] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x2204u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -716,7 +754,7 @@ /*func=*/ "deviceCtrlCmdFifoStartRunlist" #endif }, - { /* [35] */ + { /* [37] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x810u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -731,7 +769,7 @@ /*func=*/ "deviceCtrlCmdFifoGetCapsV2" #endif }, - { /* [36] */ + { /* [38] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x811u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -746,7 +784,7 @@ /*func=*/ "deviceCtrlCmdFifoIdleChannels" #endif }, - { /* [37] */ + { /* [39] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -761,7 +799,7 @@ /*func=*/ "deviceCtrlCmdDmaGetPteInfo" #endif }, - { /* [38] */ + { /* [40] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -776,7 +814,7 @@ /*func=*/ "deviceCtrlCmdDmaFlush" #endif }, - { /* [39] */ + { /* [41] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x11u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -791,7 +829,7 @@ /*func=*/ "deviceCtrlCmdDmaAdvSchedGetVaCaps" #endif }, - { /* [40] */ + { /* [42] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -806,7 +844,7 @@ /*func=*/ "deviceCtrlCmdDmaGetPdeInfo" #endif }, - { /* [41] */ + { /* [43] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -821,7 +859,7 @@ /*func=*/ "deviceCtrlCmdDmaSetPteInfo" #endif }, - { /* [42] */ + { /* [44] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -836,7 +874,7 @@ /*func=*/ "deviceCtrlCmdDmaInvalidateTLB" #endif }, - { /* [43] */ + { /* [45] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x11u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -851,7 +889,7 @@ /*func=*/ "deviceCtrlCmdDmaGetCaps" #endif }, - { /* [44] */ + { /* [46] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -866,7 +904,7 @@ /*func=*/ "deviceCtrlCmdDmaSetVASpaceSize" #endif }, - { /* [45] */ + { /* [47] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -881,7 +919,7 @@ /*func=*/ "deviceCtrlCmdDmaUpdatePde2" #endif }, - { /* [46] */ + { /* [48] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -896,7 +934,7 @@ /*func=*/ "deviceCtrlCmdDmaEnablePrivilegedRange" #endif }, - { /* [47] */ + { /* [49] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x1c0000u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -911,7 +949,7 @@ /*func=*/ "deviceCtrlCmdDmaSetDefaultVASpace" #endif }, - { /* [48] */ + { /* [50] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x140004u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -926,7 +964,7 @@ /*func=*/ "deviceCtrlCmdDmaSetPageDirectory" #endif }, - { /* [49] */ + { /* [51] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x140004u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -941,7 +979,7 @@ /*func=*/ "deviceCtrlCmdDmaUnsetPageDirectory" #endif }, - { /* [50] */ + { /* [52] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -956,7 +994,7 @@ /*func=*/ "deviceCtrlCmdMsencGetCaps" #endif }, - { /* [51] */ + { /* [53] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -971,7 +1009,7 @@ /*func=*/ "deviceCtrlCmdBspGetCapsV2" #endif }, - { /* [52] */ + { /* [54] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x1u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -986,7 +1024,7 @@ /*func=*/ "deviceCtrlCmdOsUnixVTSwitch" #endif }, - { /* [53] */ + { /* [55] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x1u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -1001,7 +1039,7 @@ /*func=*/ "deviceCtrlCmdOsUnixVTGetFBInfo" #endif }, - { /* [54] */ + { /* [56] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -1016,7 +1054,7 @@ /*func=*/ "deviceCtrlCmdNvjpgGetCapsV2" #endif }, - { /* [55] */ + { /* [57] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -1031,7 +1069,7 @@ /*func=*/ "deviceCtrlCmdInternalPerfCudaLimitDisable" #endif }, - { /* [56] */ + { /* [58] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -1046,13 +1084,13 @@ /*func=*/ "deviceCtrlCmdInternalPerfGetUnderpoweredGpuCount" #endif }, - { /* [57] */ -#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0xe10u) + { /* [59] */ +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0xe50u) /*pFunc=*/ (void (*)(void)) NULL, #else /*pFunc=*/ (void (*)(void)) deviceCtrlCmdInternalPerfCudaLimitSetControl_IMPL, -#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0xe10u) - /*flags=*/ 0xe10u, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0xe50u) + /*flags=*/ 0xe50u, /*accessRight=*/0x0u, /*methodId=*/ 0x802009u, /*paramSize=*/ sizeof(NV0080_CTRL_PERF_CUDA_LIMIT_CONTROL_PARAMS), @@ -1066,7 +1104,7 @@ const struct NVOC_EXPORT_INFO __nvoc_export_info_Device = { - /*numEntries=*/ 58, + /*numEntries=*/ 60, /*pExportEntries=*/ __nvoc_exported_method_def_Device }; @@ -1119,6 +1157,10 @@ pThis->__deviceCtrlCmdBifAspmCyaUpdate__ = &deviceCtrlCmdBifAspmCyaUpdate_IMPL; #endif +#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x200u) + pThis->__deviceCtrlCmdBifGetPciePowerControlMask__ = &deviceCtrlCmdBifGetPciePowerControlMask_IMPL; +#endif + #if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) pThis->__deviceCtrlCmdDmaGetPteInfo__ = &deviceCtrlCmdDmaGetPteInfo_IMPL; #endif @@ -1199,14 +1241,18 @@ pThis->__deviceCtrlCmdFbGetCompbitStoreInfo__ = &deviceCtrlCmdFbGetCompbitStoreInfo_IMPL; #endif -#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x11u) +#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x811u) pThis->__deviceCtrlCmdFbGetCaps__ = &deviceCtrlCmdFbGetCaps_IMPL; #endif -#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x11u) +#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x4811u) pThis->__deviceCtrlCmdFbGetCapsV2__ = &deviceCtrlCmdFbGetCapsV2_IMPL; #endif +#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x11u) + pThis->__deviceCtrlCmdSetDefaultVidmemPhysicality__ = &deviceCtrlCmdSetDefaultVidmemPhysicality_IMPL; +#endif + #if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x810u) pThis->__deviceCtrlCmdFifoGetCaps__ = &deviceCtrlCmdFifoGetCaps_IMPL; #endif @@ -1231,7 +1277,7 @@ pThis->__deviceCtrlCmdFifoStartRunlist__ = &deviceCtrlCmdFifoStartRunlist_IMPL; #endif -#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x810u) +#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x811u) pThis->__deviceCtrlCmdFifoGetChannelList__ = &deviceCtrlCmdFifoGetChannelList_IMPL; #endif @@ -1247,15 +1293,15 @@ pThis->__deviceCtrlCmdFifoIdleChannels__ = &deviceCtrlCmdFifoIdleChannels_IMPL; #endif -#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x810u) +#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x850u) pThis->__deviceCtrlCmdHostGetCaps__ = &deviceCtrlCmdHostGetCaps_IMPL; #endif -#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x810u) +#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x4850u) pThis->__deviceCtrlCmdHostGetCapsV2__ = &deviceCtrlCmdHostGetCapsV2_IMPL; #endif -#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0xe10u) +#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0xe50u) pThis->__deviceCtrlCmdInternalPerfCudaLimitSetControl__ = &deviceCtrlCmdInternalPerfCudaLimitSetControl_IMPL; #endif @@ -1275,7 +1321,7 @@ pThis->__deviceCtrlCmdGpuGetClasslistV2__ = &deviceCtrlCmdGpuGetClasslistV2_IMPL; #endif -#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x811u) +#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x4811u) pThis->__deviceCtrlCmdGpuGetNumSubdevices__ = &deviceCtrlCmdGpuGetNumSubdevices_IMPL; #endif @@ -1287,7 +1333,7 @@ pThis->__deviceCtrlCmdGpuQueryGpuSwStatePersistence__ = &deviceCtrlCmdGpuQueryGpuSwStatePersistence_IMPL; #endif -#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x810u) +#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x811u) pThis->__deviceCtrlCmdGpuGetVirtualizationMode__ = &deviceCtrlCmdGpuGetVirtualizationMode_IMPL; #endif @@ -1345,41 +1391,45 @@ pThis->__deviceShareCallback__ = &__nvoc_thunk_GpuResource_deviceShareCallback; - pThis->__deviceUnmap__ = &__nvoc_thunk_GpuResource_deviceUnmap; - - pThis->__deviceGetMemInterMapParams__ = &__nvoc_thunk_RmResource_deviceGetMemInterMapParams; + pThis->__deviceCheckMemInterUnmap__ = &__nvoc_thunk_RmResource_deviceCheckMemInterUnmap; - pThis->__deviceGetMemoryMappingDescriptor__ = &__nvoc_thunk_RmResource_deviceGetMemoryMappingDescriptor; + pThis->__deviceMapTo__ = &__nvoc_thunk_RsResource_deviceMapTo; pThis->__deviceGetMapAddrSpace__ = &__nvoc_thunk_GpuResource_deviceGetMapAddrSpace; - pThis->__deviceGetInternalObjectHandle__ = &__nvoc_thunk_GpuResource_deviceGetInternalObjectHandle; - - pThis->__deviceControlFilter__ = &__nvoc_thunk_RsResource_deviceControlFilter; + pThis->__deviceGetRefCount__ = &__nvoc_thunk_RsResource_deviceGetRefCount; pThis->__deviceAddAdditionalDependants__ = &__nvoc_thunk_RsResource_deviceAddAdditionalDependants; - pThis->__deviceGetRefCount__ = &__nvoc_thunk_RsResource_deviceGetRefCount; + pThis->__deviceControl_Prologue__ = &__nvoc_thunk_RmResource_deviceControl_Prologue; - pThis->__deviceCheckMemInterUnmap__ = &__nvoc_thunk_RmResource_deviceCheckMemInterUnmap; + pThis->__deviceGetRegBaseOffsetAndSize__ = &__nvoc_thunk_GpuResource_deviceGetRegBaseOffsetAndSize; - pThis->__deviceMapTo__ = &__nvoc_thunk_RsResource_deviceMapTo; + pThis->__deviceUnmapFrom__ = &__nvoc_thunk_RsResource_deviceUnmapFrom; - pThis->__deviceControl_Prologue__ = &__nvoc_thunk_RmResource_deviceControl_Prologue; + pThis->__deviceControl_Epilogue__ = &__nvoc_thunk_RmResource_deviceControl_Epilogue; - pThis->__deviceGetRegBaseOffsetAndSize__ = &__nvoc_thunk_GpuResource_deviceGetRegBaseOffsetAndSize; + pThis->__deviceControlLookup__ = &__nvoc_thunk_RsResource_deviceControlLookup; + + pThis->__deviceGetInternalObjectHandle__ = &__nvoc_thunk_GpuResource_deviceGetInternalObjectHandle; + + pThis->__deviceUnmap__ = &__nvoc_thunk_GpuResource_deviceUnmap; + + pThis->__deviceGetMemInterMapParams__ = &__nvoc_thunk_RmResource_deviceGetMemInterMapParams; + + pThis->__deviceGetMemoryMappingDescriptor__ = &__nvoc_thunk_RmResource_deviceGetMemoryMappingDescriptor; + + pThis->__deviceControlFilter__ = &__nvoc_thunk_RsResource_deviceControlFilter; + + pThis->__deviceControlSerialization_Prologue__ = &__nvoc_thunk_RmResource_deviceControlSerialization_Prologue; pThis->__deviceCanCopy__ = &__nvoc_thunk_RsResource_deviceCanCopy; pThis->__devicePreDestruct__ = &__nvoc_thunk_RsResource_devicePreDestruct; - pThis->__deviceUnmapFrom__ = &__nvoc_thunk_RsResource_deviceUnmapFrom; - pThis->__deviceIsDuplicate__ = &__nvoc_thunk_RsResource_deviceIsDuplicate; - pThis->__deviceControl_Epilogue__ = &__nvoc_thunk_RmResource_deviceControl_Epilogue; - - pThis->__deviceControlLookup__ = &__nvoc_thunk_RsResource_deviceControlLookup; + pThis->__deviceControlSerialization_Epilogue__ = &__nvoc_thunk_RmResource_deviceControlSerialization_Epilogue; pThis->__deviceMap__ = &__nvoc_thunk_GpuResource_deviceMap; @@ -1407,13 +1457,16 @@ Object *pParentObj; Device *pThis; - pThis = portMemAllocNonPaged(sizeof(Device)); - if (pThis == NULL) return NV_ERR_NO_MEMORY; + status = __nvoc_handleObjCreateMemAlloc(createFlags, sizeof(Device), (void**)&pThis, (void**)ppThis); + if (status != NV_OK) + return status; portMemSet(pThis, 0, sizeof(Device)); __nvoc_initRtti(staticCast(pThis, Dynamic), &__nvoc_class_def_Device); + pThis->__nvoc_base_GpuResource.__nvoc_base_RmResource.__nvoc_base_RsResource.__nvoc_base_Object.createFlags = createFlags; + if (pParent != NULL && !(createFlags & NVOC_OBJ_CREATE_FLAGS_PARENT_HALSPEC_ONLY)) { pParentObj = dynamicCast(pParent, Object); @@ -1429,11 +1482,17 @@ if (status != NV_OK) goto __nvoc_objCreate_Device_cleanup; *ppThis = pThis; + return NV_OK; __nvoc_objCreate_Device_cleanup: // do not call destructors here since the constructor already called them - portMemFree(pThis); + if (createFlags & NVOC_OBJ_CREATE_FLAGS_IN_PLACE_CONSTRUCT) + portMemSet(pThis, 0, sizeof(Device)); + else + portMemFree(pThis); + + // coverity[leaked_storage:FALSE] return status; } diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/generated/g_device_nvoc.h nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_device_nvoc.h --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/generated/g_device_nvoc.h 2023-10-25 20:26:54.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_device_nvoc.h 2024-03-05 22:18:10.000000000 +0000 @@ -86,6 +86,7 @@ NV_STATUS (*__deviceCtrlCmdBifGetDmaBaseSysmemAddr__)(struct Device *, NV0080_CTRL_BIF_GET_DMA_BASE_SYSMEM_ADDR_PARAMS *); NV_STATUS (*__deviceCtrlCmdBifAspmFeatureSupported__)(struct Device *, NV0080_CTRL_BIF_SET_ASPM_FEATURE_PARAMS *); NV_STATUS (*__deviceCtrlCmdBifAspmCyaUpdate__)(struct Device *, NV0080_CTRL_BIF_ASPM_CYA_UPDATE_PARAMS *); + NV_STATUS (*__deviceCtrlCmdBifGetPciePowerControlMask__)(struct Device *, NV0080_CTRL_CMD_BIF_GET_PCIE_POWER_CONTROL_MASK_PARAMS *); NV_STATUS (*__deviceCtrlCmdDmaGetPteInfo__)(struct Device *, NV0080_CTRL_DMA_GET_PTE_INFO_PARAMS *); NV_STATUS (*__deviceCtrlCmdDmaUpdatePde2__)(struct Device *, NV0080_CTRL_DMA_UPDATE_PDE_2_PARAMS *); NV_STATUS (*__deviceCtrlCmdDmaSetPageDirectory__)(struct Device *, NV0080_CTRL_DMA_SET_PAGE_DIRECTORY_PARAMS *); @@ -108,6 +109,7 @@ NV_STATUS (*__deviceCtrlCmdFbGetCompbitStoreInfo__)(struct Device *, NV0080_CTRL_FB_GET_COMPBIT_STORE_INFO_PARAMS *); NV_STATUS (*__deviceCtrlCmdFbGetCaps__)(struct Device *, NV0080_CTRL_FB_GET_CAPS_PARAMS *); NV_STATUS (*__deviceCtrlCmdFbGetCapsV2__)(struct Device *, NV0080_CTRL_FB_GET_CAPS_V2_PARAMS *); + NV_STATUS (*__deviceCtrlCmdSetDefaultVidmemPhysicality__)(struct Device *, NV0080_CTRL_FB_SET_DEFAULT_VIDMEM_PHYSICALITY_PARAMS *); NV_STATUS (*__deviceCtrlCmdFifoGetCaps__)(struct Device *, NV0080_CTRL_FIFO_GET_CAPS_PARAMS *); NV_STATUS (*__deviceCtrlCmdFifoGetCapsV2__)(struct Device *, NV0080_CTRL_FIFO_GET_CAPS_V2_PARAMS *); NV_STATUS (*__deviceCtrlCmdFifoStartSelectedChannels__)(struct Device *, NV0080_CTRL_FIFO_START_SELECTED_CHANNELS_PARAMS *); @@ -142,24 +144,26 @@ NV_STATUS (*__deviceCtrlCmdOsUnixVTSwitch__)(struct Device *, NV0080_CTRL_OS_UNIX_VT_SWITCH_PARAMS *); NV_STATUS (*__deviceCtrlCmdOsUnixVTGetFBInfo__)(struct Device *, NV0080_CTRL_OS_UNIX_VT_GET_FB_INFO_PARAMS *); NvBool (*__deviceShareCallback__)(struct Device *, struct RsClient *, struct RsResourceRef *, RS_SHARE_POLICY *); - NV_STATUS (*__deviceUnmap__)(struct Device *, struct CALL_CONTEXT *, struct RsCpuMapping *); - NV_STATUS (*__deviceGetMemInterMapParams__)(struct Device *, RMRES_MEM_INTER_MAP_PARAMS *); - NV_STATUS (*__deviceGetMemoryMappingDescriptor__)(struct Device *, struct MEMORY_DESCRIPTOR **); - NV_STATUS (*__deviceGetMapAddrSpace__)(struct Device *, struct CALL_CONTEXT *, NvU32, NV_ADDRESS_SPACE *); - NvHandle (*__deviceGetInternalObjectHandle__)(struct Device *); - NV_STATUS (*__deviceControlFilter__)(struct Device *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); - void (*__deviceAddAdditionalDependants__)(struct RsClient *, struct Device *, RsResourceRef *); - NvU32 (*__deviceGetRefCount__)(struct Device *); NV_STATUS (*__deviceCheckMemInterUnmap__)(struct Device *, NvBool); NV_STATUS (*__deviceMapTo__)(struct Device *, RS_RES_MAP_TO_PARAMS *); + NV_STATUS (*__deviceGetMapAddrSpace__)(struct Device *, struct CALL_CONTEXT *, NvU32, NV_ADDRESS_SPACE *); + NvU32 (*__deviceGetRefCount__)(struct Device *); + void (*__deviceAddAdditionalDependants__)(struct RsClient *, struct Device *, RsResourceRef *); NV_STATUS (*__deviceControl_Prologue__)(struct Device *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); NV_STATUS (*__deviceGetRegBaseOffsetAndSize__)(struct Device *, struct OBJGPU *, NvU32 *, NvU32 *); - NvBool (*__deviceCanCopy__)(struct Device *); - void (*__devicePreDestruct__)(struct Device *); NV_STATUS (*__deviceUnmapFrom__)(struct Device *, RS_RES_UNMAP_FROM_PARAMS *); - NV_STATUS (*__deviceIsDuplicate__)(struct Device *, NvHandle, NvBool *); void (*__deviceControl_Epilogue__)(struct Device *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); NV_STATUS (*__deviceControlLookup__)(struct Device *, struct RS_RES_CONTROL_PARAMS_INTERNAL *, const struct NVOC_EXPORTED_METHOD_DEF **); + NvHandle (*__deviceGetInternalObjectHandle__)(struct Device *); + NV_STATUS (*__deviceUnmap__)(struct Device *, struct CALL_CONTEXT *, struct RsCpuMapping *); + NV_STATUS (*__deviceGetMemInterMapParams__)(struct Device *, RMRES_MEM_INTER_MAP_PARAMS *); + NV_STATUS (*__deviceGetMemoryMappingDescriptor__)(struct Device *, struct MEMORY_DESCRIPTOR **); + NV_STATUS (*__deviceControlFilter__)(struct Device *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); + NV_STATUS (*__deviceControlSerialization_Prologue__)(struct Device *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); + NvBool (*__deviceCanCopy__)(struct Device *); + void (*__devicePreDestruct__)(struct Device *); + NV_STATUS (*__deviceIsDuplicate__)(struct Device *, NvHandle, NvBool *); + void (*__deviceControlSerialization_Epilogue__)(struct Device *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); NV_STATUS (*__deviceMap__)(struct Device *, struct CALL_CONTEXT *, struct RS_CPU_MAP_PARAMS *, struct RsCpuMapping *); NvBool (*__deviceAccessCallback__)(struct Device *, struct RsClient *, void *, RsAccessRight); NvU32 deviceInst; @@ -179,6 +183,7 @@ NvU64 vaLimitInternal; NvU64 vaSize; NvU32 vaMode; + NvU32 defaultVidmemPhysicalityOverride; struct KERNEL_HOST_VGPU_DEVICE *pKernelHostVgpuDevice; }; @@ -215,6 +220,7 @@ #define deviceCtrlCmdBifGetDmaBaseSysmemAddr(pDevice, pBifDmaBaseSysmemParams) deviceCtrlCmdBifGetDmaBaseSysmemAddr_DISPATCH(pDevice, pBifDmaBaseSysmemParams) #define deviceCtrlCmdBifAspmFeatureSupported(pDevice, pBifAspmParams) deviceCtrlCmdBifAspmFeatureSupported_DISPATCH(pDevice, pBifAspmParams) #define deviceCtrlCmdBifAspmCyaUpdate(pDevice, pBifAspmCyaParams) deviceCtrlCmdBifAspmCyaUpdate_DISPATCH(pDevice, pBifAspmCyaParams) +#define deviceCtrlCmdBifGetPciePowerControlMask(pDevice, pBifPciePowerControlParams) deviceCtrlCmdBifGetPciePowerControlMask_DISPATCH(pDevice, pBifPciePowerControlParams) #define deviceCtrlCmdDmaGetPteInfo(pDevice, pParams) deviceCtrlCmdDmaGetPteInfo_DISPATCH(pDevice, pParams) #define deviceCtrlCmdDmaUpdatePde2(pDevice, pParams) deviceCtrlCmdDmaUpdatePde2_DISPATCH(pDevice, pParams) #define deviceCtrlCmdDmaSetPageDirectory(pDevice, pParams) deviceCtrlCmdDmaSetPageDirectory_DISPATCH(pDevice, pParams) @@ -237,6 +243,7 @@ #define deviceCtrlCmdFbGetCompbitStoreInfo(pDevice, pCompbitStoreParams) deviceCtrlCmdFbGetCompbitStoreInfo_DISPATCH(pDevice, pCompbitStoreParams) #define deviceCtrlCmdFbGetCaps(pDevice, pFbCapsParams) deviceCtrlCmdFbGetCaps_DISPATCH(pDevice, pFbCapsParams) #define deviceCtrlCmdFbGetCapsV2(pDevice, pFbCapsParams) deviceCtrlCmdFbGetCapsV2_DISPATCH(pDevice, pFbCapsParams) +#define deviceCtrlCmdSetDefaultVidmemPhysicality(pDevice, pParams) deviceCtrlCmdSetDefaultVidmemPhysicality_DISPATCH(pDevice, pParams) #define deviceCtrlCmdFifoGetCaps(pDevice, pFifoCapsParams) deviceCtrlCmdFifoGetCaps_DISPATCH(pDevice, pFifoCapsParams) #define deviceCtrlCmdFifoGetCapsV2(pDevice, pFifoCapsParams) deviceCtrlCmdFifoGetCapsV2_DISPATCH(pDevice, pFifoCapsParams) #define deviceCtrlCmdFifoStartSelectedChannels(pDevice, pStartSel) deviceCtrlCmdFifoStartSelectedChannels_DISPATCH(pDevice, pStartSel) @@ -271,24 +278,26 @@ #define deviceCtrlCmdOsUnixVTSwitch(pDevice, pParams) deviceCtrlCmdOsUnixVTSwitch_DISPATCH(pDevice, pParams) #define deviceCtrlCmdOsUnixVTGetFBInfo(pDevice, pParams) deviceCtrlCmdOsUnixVTGetFBInfo_DISPATCH(pDevice, pParams) #define deviceShareCallback(pGpuResource, pInvokingClient, pParentRef, pSharePolicy) deviceShareCallback_DISPATCH(pGpuResource, pInvokingClient, pParentRef, pSharePolicy) -#define deviceUnmap(pGpuResource, pCallContext, pCpuMapping) deviceUnmap_DISPATCH(pGpuResource, pCallContext, pCpuMapping) -#define deviceGetMemInterMapParams(pRmResource, pParams) deviceGetMemInterMapParams_DISPATCH(pRmResource, pParams) -#define deviceGetMemoryMappingDescriptor(pRmResource, ppMemDesc) deviceGetMemoryMappingDescriptor_DISPATCH(pRmResource, ppMemDesc) -#define deviceGetMapAddrSpace(pGpuResource, pCallContext, mapFlags, pAddrSpace) deviceGetMapAddrSpace_DISPATCH(pGpuResource, pCallContext, mapFlags, pAddrSpace) -#define deviceGetInternalObjectHandle(pGpuResource) deviceGetInternalObjectHandle_DISPATCH(pGpuResource) -#define deviceControlFilter(pResource, pCallContext, pParams) deviceControlFilter_DISPATCH(pResource, pCallContext, pParams) -#define deviceAddAdditionalDependants(pClient, pResource, pReference) deviceAddAdditionalDependants_DISPATCH(pClient, pResource, pReference) -#define deviceGetRefCount(pResource) deviceGetRefCount_DISPATCH(pResource) #define deviceCheckMemInterUnmap(pRmResource, bSubdeviceHandleProvided) deviceCheckMemInterUnmap_DISPATCH(pRmResource, bSubdeviceHandleProvided) #define deviceMapTo(pResource, pParams) deviceMapTo_DISPATCH(pResource, pParams) +#define deviceGetMapAddrSpace(pGpuResource, pCallContext, mapFlags, pAddrSpace) deviceGetMapAddrSpace_DISPATCH(pGpuResource, pCallContext, mapFlags, pAddrSpace) +#define deviceGetRefCount(pResource) deviceGetRefCount_DISPATCH(pResource) +#define deviceAddAdditionalDependants(pClient, pResource, pReference) deviceAddAdditionalDependants_DISPATCH(pClient, pResource, pReference) #define deviceControl_Prologue(pResource, pCallContext, pParams) deviceControl_Prologue_DISPATCH(pResource, pCallContext, pParams) #define deviceGetRegBaseOffsetAndSize(pGpuResource, pGpu, pOffset, pSize) deviceGetRegBaseOffsetAndSize_DISPATCH(pGpuResource, pGpu, pOffset, pSize) -#define deviceCanCopy(pResource) deviceCanCopy_DISPATCH(pResource) -#define devicePreDestruct(pResource) devicePreDestruct_DISPATCH(pResource) #define deviceUnmapFrom(pResource, pParams) deviceUnmapFrom_DISPATCH(pResource, pParams) -#define deviceIsDuplicate(pResource, hMemory, pDuplicate) deviceIsDuplicate_DISPATCH(pResource, hMemory, pDuplicate) #define deviceControl_Epilogue(pResource, pCallContext, pParams) deviceControl_Epilogue_DISPATCH(pResource, pCallContext, pParams) #define deviceControlLookup(pResource, pParams, ppEntry) deviceControlLookup_DISPATCH(pResource, pParams, ppEntry) +#define deviceGetInternalObjectHandle(pGpuResource) deviceGetInternalObjectHandle_DISPATCH(pGpuResource) +#define deviceUnmap(pGpuResource, pCallContext, pCpuMapping) deviceUnmap_DISPATCH(pGpuResource, pCallContext, pCpuMapping) +#define deviceGetMemInterMapParams(pRmResource, pParams) deviceGetMemInterMapParams_DISPATCH(pRmResource, pParams) +#define deviceGetMemoryMappingDescriptor(pRmResource, ppMemDesc) deviceGetMemoryMappingDescriptor_DISPATCH(pRmResource, ppMemDesc) +#define deviceControlFilter(pResource, pCallContext, pParams) deviceControlFilter_DISPATCH(pResource, pCallContext, pParams) +#define deviceControlSerialization_Prologue(pResource, pCallContext, pParams) deviceControlSerialization_Prologue_DISPATCH(pResource, pCallContext, pParams) +#define deviceCanCopy(pResource) deviceCanCopy_DISPATCH(pResource) +#define devicePreDestruct(pResource) devicePreDestruct_DISPATCH(pResource) +#define deviceIsDuplicate(pResource, hMemory, pDuplicate) deviceIsDuplicate_DISPATCH(pResource, hMemory, pDuplicate) +#define deviceControlSerialization_Epilogue(pResource, pCallContext, pParams) deviceControlSerialization_Epilogue_DISPATCH(pResource, pCallContext, pParams) #define deviceMap(pGpuResource, pCallContext, pParams, pCpuMapping) deviceMap_DISPATCH(pGpuResource, pCallContext, pParams, pCpuMapping) #define deviceAccessCallback(pResource, pInvokingClient, pAllocParams, accessRight) deviceAccessCallback_DISPATCH(pResource, pInvokingClient, pAllocParams, accessRight) NV_STATUS deviceControl_IMPL(struct Device *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams); @@ -321,6 +330,12 @@ return pDevice->__deviceCtrlCmdBifAspmCyaUpdate__(pDevice, pBifAspmCyaParams); } +NV_STATUS deviceCtrlCmdBifGetPciePowerControlMask_IMPL(struct Device *pDevice, NV0080_CTRL_CMD_BIF_GET_PCIE_POWER_CONTROL_MASK_PARAMS *pBifPciePowerControlParams); + +static inline NV_STATUS deviceCtrlCmdBifGetPciePowerControlMask_DISPATCH(struct Device *pDevice, NV0080_CTRL_CMD_BIF_GET_PCIE_POWER_CONTROL_MASK_PARAMS *pBifPciePowerControlParams) { + return pDevice->__deviceCtrlCmdBifGetPciePowerControlMask__(pDevice, pBifPciePowerControlParams); +} + NV_STATUS deviceCtrlCmdDmaGetPteInfo_IMPL(struct Device *pDevice, NV0080_CTRL_DMA_GET_PTE_INFO_PARAMS *pParams); static inline NV_STATUS deviceCtrlCmdDmaGetPteInfo_DISPATCH(struct Device *pDevice, NV0080_CTRL_DMA_GET_PTE_INFO_PARAMS *pParams) { @@ -453,6 +468,12 @@ return pDevice->__deviceCtrlCmdFbGetCapsV2__(pDevice, pFbCapsParams); } +NV_STATUS deviceCtrlCmdSetDefaultVidmemPhysicality_IMPL(struct Device *pDevice, NV0080_CTRL_FB_SET_DEFAULT_VIDMEM_PHYSICALITY_PARAMS *pParams); + +static inline NV_STATUS deviceCtrlCmdSetDefaultVidmemPhysicality_DISPATCH(struct Device *pDevice, NV0080_CTRL_FB_SET_DEFAULT_VIDMEM_PHYSICALITY_PARAMS *pParams) { + return pDevice->__deviceCtrlCmdSetDefaultVidmemPhysicality__(pDevice, pParams); +} + NV_STATUS deviceCtrlCmdFifoGetCaps_IMPL(struct Device *pDevice, NV0080_CTRL_FIFO_GET_CAPS_PARAMS *pFifoCapsParams); static inline NV_STATUS deviceCtrlCmdFifoGetCaps_DISPATCH(struct Device *pDevice, NV0080_CTRL_FIFO_GET_CAPS_PARAMS *pFifoCapsParams) { @@ -655,52 +676,68 @@ return pGpuResource->__deviceShareCallback__(pGpuResource, pInvokingClient, pParentRef, pSharePolicy); } -static inline NV_STATUS deviceUnmap_DISPATCH(struct Device *pGpuResource, struct CALL_CONTEXT *pCallContext, struct RsCpuMapping *pCpuMapping) { - return pGpuResource->__deviceUnmap__(pGpuResource, pCallContext, pCpuMapping); -} - -static inline NV_STATUS deviceGetMemInterMapParams_DISPATCH(struct Device *pRmResource, RMRES_MEM_INTER_MAP_PARAMS *pParams) { - return pRmResource->__deviceGetMemInterMapParams__(pRmResource, pParams); +static inline NV_STATUS deviceCheckMemInterUnmap_DISPATCH(struct Device *pRmResource, NvBool bSubdeviceHandleProvided) { + return pRmResource->__deviceCheckMemInterUnmap__(pRmResource, bSubdeviceHandleProvided); } -static inline NV_STATUS deviceGetMemoryMappingDescriptor_DISPATCH(struct Device *pRmResource, struct MEMORY_DESCRIPTOR **ppMemDesc) { - return pRmResource->__deviceGetMemoryMappingDescriptor__(pRmResource, ppMemDesc); +static inline NV_STATUS deviceMapTo_DISPATCH(struct Device *pResource, RS_RES_MAP_TO_PARAMS *pParams) { + return pResource->__deviceMapTo__(pResource, pParams); } static inline NV_STATUS deviceGetMapAddrSpace_DISPATCH(struct Device *pGpuResource, struct CALL_CONTEXT *pCallContext, NvU32 mapFlags, NV_ADDRESS_SPACE *pAddrSpace) { return pGpuResource->__deviceGetMapAddrSpace__(pGpuResource, pCallContext, mapFlags, pAddrSpace); } -static inline NvHandle deviceGetInternalObjectHandle_DISPATCH(struct Device *pGpuResource) { - return pGpuResource->__deviceGetInternalObjectHandle__(pGpuResource); -} - -static inline NV_STATUS deviceControlFilter_DISPATCH(struct Device *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { - return pResource->__deviceControlFilter__(pResource, pCallContext, pParams); +static inline NvU32 deviceGetRefCount_DISPATCH(struct Device *pResource) { + return pResource->__deviceGetRefCount__(pResource); } static inline void deviceAddAdditionalDependants_DISPATCH(struct RsClient *pClient, struct Device *pResource, RsResourceRef *pReference) { pResource->__deviceAddAdditionalDependants__(pClient, pResource, pReference); } -static inline NvU32 deviceGetRefCount_DISPATCH(struct Device *pResource) { - return pResource->__deviceGetRefCount__(pResource); +static inline NV_STATUS deviceControl_Prologue_DISPATCH(struct Device *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return pResource->__deviceControl_Prologue__(pResource, pCallContext, pParams); } -static inline NV_STATUS deviceCheckMemInterUnmap_DISPATCH(struct Device *pRmResource, NvBool bSubdeviceHandleProvided) { - return pRmResource->__deviceCheckMemInterUnmap__(pRmResource, bSubdeviceHandleProvided); +static inline NV_STATUS deviceGetRegBaseOffsetAndSize_DISPATCH(struct Device *pGpuResource, struct OBJGPU *pGpu, NvU32 *pOffset, NvU32 *pSize) { + return pGpuResource->__deviceGetRegBaseOffsetAndSize__(pGpuResource, pGpu, pOffset, pSize); } -static inline NV_STATUS deviceMapTo_DISPATCH(struct Device *pResource, RS_RES_MAP_TO_PARAMS *pParams) { - return pResource->__deviceMapTo__(pResource, pParams); +static inline NV_STATUS deviceUnmapFrom_DISPATCH(struct Device *pResource, RS_RES_UNMAP_FROM_PARAMS *pParams) { + return pResource->__deviceUnmapFrom__(pResource, pParams); } -static inline NV_STATUS deviceControl_Prologue_DISPATCH(struct Device *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { - return pResource->__deviceControl_Prologue__(pResource, pCallContext, pParams); +static inline void deviceControl_Epilogue_DISPATCH(struct Device *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + pResource->__deviceControl_Epilogue__(pResource, pCallContext, pParams); } -static inline NV_STATUS deviceGetRegBaseOffsetAndSize_DISPATCH(struct Device *pGpuResource, struct OBJGPU *pGpu, NvU32 *pOffset, NvU32 *pSize) { - return pGpuResource->__deviceGetRegBaseOffsetAndSize__(pGpuResource, pGpu, pOffset, pSize); +static inline NV_STATUS deviceControlLookup_DISPATCH(struct Device *pResource, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams, const struct NVOC_EXPORTED_METHOD_DEF **ppEntry) { + return pResource->__deviceControlLookup__(pResource, pParams, ppEntry); +} + +static inline NvHandle deviceGetInternalObjectHandle_DISPATCH(struct Device *pGpuResource) { + return pGpuResource->__deviceGetInternalObjectHandle__(pGpuResource); +} + +static inline NV_STATUS deviceUnmap_DISPATCH(struct Device *pGpuResource, struct CALL_CONTEXT *pCallContext, struct RsCpuMapping *pCpuMapping) { + return pGpuResource->__deviceUnmap__(pGpuResource, pCallContext, pCpuMapping); +} + +static inline NV_STATUS deviceGetMemInterMapParams_DISPATCH(struct Device *pRmResource, RMRES_MEM_INTER_MAP_PARAMS *pParams) { + return pRmResource->__deviceGetMemInterMapParams__(pRmResource, pParams); +} + +static inline NV_STATUS deviceGetMemoryMappingDescriptor_DISPATCH(struct Device *pRmResource, struct MEMORY_DESCRIPTOR **ppMemDesc) { + return pRmResource->__deviceGetMemoryMappingDescriptor__(pRmResource, ppMemDesc); +} + +static inline NV_STATUS deviceControlFilter_DISPATCH(struct Device *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return pResource->__deviceControlFilter__(pResource, pCallContext, pParams); +} + +static inline NV_STATUS deviceControlSerialization_Prologue_DISPATCH(struct Device *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return pResource->__deviceControlSerialization_Prologue__(pResource, pCallContext, pParams); } static inline NvBool deviceCanCopy_DISPATCH(struct Device *pResource) { @@ -711,20 +748,12 @@ pResource->__devicePreDestruct__(pResource); } -static inline NV_STATUS deviceUnmapFrom_DISPATCH(struct Device *pResource, RS_RES_UNMAP_FROM_PARAMS *pParams) { - return pResource->__deviceUnmapFrom__(pResource, pParams); -} - static inline NV_STATUS deviceIsDuplicate_DISPATCH(struct Device *pResource, NvHandle hMemory, NvBool *pDuplicate) { return pResource->__deviceIsDuplicate__(pResource, hMemory, pDuplicate); } -static inline void deviceControl_Epilogue_DISPATCH(struct Device *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { - pResource->__deviceControl_Epilogue__(pResource, pCallContext, pParams); -} - -static inline NV_STATUS deviceControlLookup_DISPATCH(struct Device *pResource, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams, const struct NVOC_EXPORTED_METHOD_DEF **ppEntry) { - return pResource->__deviceControlLookup__(pResource, pParams, ppEntry); +static inline void deviceControlSerialization_Epilogue_DISPATCH(struct Device *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + pResource->__deviceControlSerialization_Epilogue__(pResource, pCallContext, pParams); } static inline NV_STATUS deviceMap_DISPATCH(struct Device *pGpuResource, struct CALL_CONTEXT *pCallContext, struct RS_CPU_MAP_PARAMS *pParams, struct RsCpuMapping *pCpuMapping) { @@ -812,11 +841,6 @@ // **************************************************************************** /** - * WARNING: This function is deprecated! Please use deviceGetByHandle. - */ -struct Device *CliGetDeviceInfo(NvHandle, NvHandle); - -/** * WARNING: This function is deprecated and use is *strongly* discouraged * (especially for new code!) * diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/generated/g_disp_capabilities_nvoc.c nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_disp_capabilities_nvoc.c --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/generated/g_disp_capabilities_nvoc.c 2023-10-25 20:26:54.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_disp_capabilities_nvoc.c 2024-03-05 22:18:11.000000000 +0000 @@ -101,80 +101,88 @@ return gpuresShareCallback((struct GpuResource *)(((unsigned char *)pGpuResource) + __nvoc_rtti_DispCapabilities_GpuResource.offset), pInvokingClient, pParentRef, pSharePolicy); } -static NV_STATUS __nvoc_thunk_GpuResource_dispcapControl(struct DispCapabilities *pGpuResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { - return gpuresControl((struct GpuResource *)(((unsigned char *)pGpuResource) + __nvoc_rtti_DispCapabilities_GpuResource.offset), pCallContext, pParams); +static NV_STATUS __nvoc_thunk_RmResource_dispcapCheckMemInterUnmap(struct DispCapabilities *pRmResource, NvBool bSubdeviceHandleProvided) { + return rmresCheckMemInterUnmap((struct RmResource *)(((unsigned char *)pRmResource) + __nvoc_rtti_DispCapabilities_RmResource.offset), bSubdeviceHandleProvided); } -static NV_STATUS __nvoc_thunk_GpuResource_dispcapUnmap(struct DispCapabilities *pGpuResource, struct CALL_CONTEXT *pCallContext, struct RsCpuMapping *pCpuMapping) { - return gpuresUnmap((struct GpuResource *)(((unsigned char *)pGpuResource) + __nvoc_rtti_DispCapabilities_GpuResource.offset), pCallContext, pCpuMapping); +static NV_STATUS __nvoc_thunk_RsResource_dispcapMapTo(struct DispCapabilities *pResource, RS_RES_MAP_TO_PARAMS *pParams) { + return resMapTo((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_DispCapabilities_RsResource.offset), pParams); } -static NV_STATUS __nvoc_thunk_RmResource_dispcapGetMemInterMapParams(struct DispCapabilities *pRmResource, RMRES_MEM_INTER_MAP_PARAMS *pParams) { - return rmresGetMemInterMapParams((struct RmResource *)(((unsigned char *)pRmResource) + __nvoc_rtti_DispCapabilities_RmResource.offset), pParams); +static NV_STATUS __nvoc_thunk_GpuResource_dispcapGetMapAddrSpace(struct DispCapabilities *pGpuResource, struct CALL_CONTEXT *pCallContext, NvU32 mapFlags, NV_ADDRESS_SPACE *pAddrSpace) { + return gpuresGetMapAddrSpace((struct GpuResource *)(((unsigned char *)pGpuResource) + __nvoc_rtti_DispCapabilities_GpuResource.offset), pCallContext, mapFlags, pAddrSpace); } -static NV_STATUS __nvoc_thunk_RmResource_dispcapGetMemoryMappingDescriptor(struct DispCapabilities *pRmResource, struct MEMORY_DESCRIPTOR **ppMemDesc) { - return rmresGetMemoryMappingDescriptor((struct RmResource *)(((unsigned char *)pRmResource) + __nvoc_rtti_DispCapabilities_RmResource.offset), ppMemDesc); +static NvU32 __nvoc_thunk_RsResource_dispcapGetRefCount(struct DispCapabilities *pResource) { + return resGetRefCount((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_DispCapabilities_RsResource.offset)); } -static NV_STATUS __nvoc_thunk_GpuResource_dispcapGetMapAddrSpace(struct DispCapabilities *pGpuResource, struct CALL_CONTEXT *pCallContext, NvU32 mapFlags, NV_ADDRESS_SPACE *pAddrSpace) { - return gpuresGetMapAddrSpace((struct GpuResource *)(((unsigned char *)pGpuResource) + __nvoc_rtti_DispCapabilities_GpuResource.offset), pCallContext, mapFlags, pAddrSpace); +static void __nvoc_thunk_RsResource_dispcapAddAdditionalDependants(struct RsClient *pClient, struct DispCapabilities *pResource, RsResourceRef *pReference) { + resAddAdditionalDependants(pClient, (struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_DispCapabilities_RsResource.offset), pReference); +} + +static NV_STATUS __nvoc_thunk_RmResource_dispcapControl_Prologue(struct DispCapabilities *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return rmresControl_Prologue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_DispCapabilities_RmResource.offset), pCallContext, pParams); +} + +static NV_STATUS __nvoc_thunk_GpuResource_dispcapInternalControlForward(struct DispCapabilities *pGpuResource, NvU32 command, void *pParams, NvU32 size) { + return gpuresInternalControlForward((struct GpuResource *)(((unsigned char *)pGpuResource) + __nvoc_rtti_DispCapabilities_GpuResource.offset), command, pParams, size); +} + +static NV_STATUS __nvoc_thunk_RsResource_dispcapUnmapFrom(struct DispCapabilities *pResource, RS_RES_UNMAP_FROM_PARAMS *pParams) { + return resUnmapFrom((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_DispCapabilities_RsResource.offset), pParams); +} + +static void __nvoc_thunk_RmResource_dispcapControl_Epilogue(struct DispCapabilities *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + rmresControl_Epilogue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_DispCapabilities_RmResource.offset), pCallContext, pParams); +} + +static NV_STATUS __nvoc_thunk_RsResource_dispcapControlLookup(struct DispCapabilities *pResource, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams, const struct NVOC_EXPORTED_METHOD_DEF **ppEntry) { + return resControlLookup((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_DispCapabilities_RsResource.offset), pParams, ppEntry); } static NvHandle __nvoc_thunk_GpuResource_dispcapGetInternalObjectHandle(struct DispCapabilities *pGpuResource) { return gpuresGetInternalObjectHandle((struct GpuResource *)(((unsigned char *)pGpuResource) + __nvoc_rtti_DispCapabilities_GpuResource.offset)); } -static NV_STATUS __nvoc_thunk_RsResource_dispcapControlFilter(struct DispCapabilities *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { - return resControlFilter((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_DispCapabilities_RsResource.offset), pCallContext, pParams); +static NV_STATUS __nvoc_thunk_GpuResource_dispcapControl(struct DispCapabilities *pGpuResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return gpuresControl((struct GpuResource *)(((unsigned char *)pGpuResource) + __nvoc_rtti_DispCapabilities_GpuResource.offset), pCallContext, pParams); } -static void __nvoc_thunk_RsResource_dispcapAddAdditionalDependants(struct RsClient *pClient, struct DispCapabilities *pResource, RsResourceRef *pReference) { - resAddAdditionalDependants(pClient, (struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_DispCapabilities_RsResource.offset), pReference); +static NV_STATUS __nvoc_thunk_GpuResource_dispcapUnmap(struct DispCapabilities *pGpuResource, struct CALL_CONTEXT *pCallContext, struct RsCpuMapping *pCpuMapping) { + return gpuresUnmap((struct GpuResource *)(((unsigned char *)pGpuResource) + __nvoc_rtti_DispCapabilities_GpuResource.offset), pCallContext, pCpuMapping); } -static NvU32 __nvoc_thunk_RsResource_dispcapGetRefCount(struct DispCapabilities *pResource) { - return resGetRefCount((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_DispCapabilities_RsResource.offset)); +static NV_STATUS __nvoc_thunk_RmResource_dispcapGetMemInterMapParams(struct DispCapabilities *pRmResource, RMRES_MEM_INTER_MAP_PARAMS *pParams) { + return rmresGetMemInterMapParams((struct RmResource *)(((unsigned char *)pRmResource) + __nvoc_rtti_DispCapabilities_RmResource.offset), pParams); } -static NV_STATUS __nvoc_thunk_RmResource_dispcapCheckMemInterUnmap(struct DispCapabilities *pRmResource, NvBool bSubdeviceHandleProvided) { - return rmresCheckMemInterUnmap((struct RmResource *)(((unsigned char *)pRmResource) + __nvoc_rtti_DispCapabilities_RmResource.offset), bSubdeviceHandleProvided); +static NV_STATUS __nvoc_thunk_RmResource_dispcapGetMemoryMappingDescriptor(struct DispCapabilities *pRmResource, struct MEMORY_DESCRIPTOR **ppMemDesc) { + return rmresGetMemoryMappingDescriptor((struct RmResource *)(((unsigned char *)pRmResource) + __nvoc_rtti_DispCapabilities_RmResource.offset), ppMemDesc); } -static NV_STATUS __nvoc_thunk_RsResource_dispcapMapTo(struct DispCapabilities *pResource, RS_RES_MAP_TO_PARAMS *pParams) { - return resMapTo((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_DispCapabilities_RsResource.offset), pParams); +static NV_STATUS __nvoc_thunk_RsResource_dispcapControlFilter(struct DispCapabilities *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return resControlFilter((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_DispCapabilities_RsResource.offset), pCallContext, pParams); } -static NV_STATUS __nvoc_thunk_RmResource_dispcapControl_Prologue(struct DispCapabilities *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { - return rmresControl_Prologue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_DispCapabilities_RmResource.offset), pCallContext, pParams); +static NV_STATUS __nvoc_thunk_RmResource_dispcapControlSerialization_Prologue(struct DispCapabilities *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return rmresControlSerialization_Prologue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_DispCapabilities_RmResource.offset), pCallContext, pParams); } static NvBool __nvoc_thunk_RsResource_dispcapCanCopy(struct DispCapabilities *pResource) { return resCanCopy((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_DispCapabilities_RsResource.offset)); } -static NV_STATUS __nvoc_thunk_GpuResource_dispcapInternalControlForward(struct DispCapabilities *pGpuResource, NvU32 command, void *pParams, NvU32 size) { - return gpuresInternalControlForward((struct GpuResource *)(((unsigned char *)pGpuResource) + __nvoc_rtti_DispCapabilities_GpuResource.offset), command, pParams, size); -} - static void __nvoc_thunk_RsResource_dispcapPreDestruct(struct DispCapabilities *pResource) { resPreDestruct((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_DispCapabilities_RsResource.offset)); } -static NV_STATUS __nvoc_thunk_RsResource_dispcapUnmapFrom(struct DispCapabilities *pResource, RS_RES_UNMAP_FROM_PARAMS *pParams) { - return resUnmapFrom((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_DispCapabilities_RsResource.offset), pParams); -} - static NV_STATUS __nvoc_thunk_RsResource_dispcapIsDuplicate(struct DispCapabilities *pResource, NvHandle hMemory, NvBool *pDuplicate) { return resIsDuplicate((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_DispCapabilities_RsResource.offset), hMemory, pDuplicate); } -static void __nvoc_thunk_RmResource_dispcapControl_Epilogue(struct DispCapabilities *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { - rmresControl_Epilogue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_DispCapabilities_RmResource.offset), pCallContext, pParams); -} - -static NV_STATUS __nvoc_thunk_RsResource_dispcapControlLookup(struct DispCapabilities *pResource, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams, const struct NVOC_EXPORTED_METHOD_DEF **ppEntry) { - return resControlLookup((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_DispCapabilities_RsResource.offset), pParams, ppEntry); +static void __nvoc_thunk_RmResource_dispcapControlSerialization_Epilogue(struct DispCapabilities *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + rmresControlSerialization_Epilogue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_DispCapabilities_RmResource.offset), pCallContext, pParams); } static NV_STATUS __nvoc_thunk_GpuResource_dispcapMap(struct DispCapabilities *pGpuResource, struct CALL_CONTEXT *pCallContext, struct RS_CPU_MAP_PARAMS *pParams, struct RsCpuMapping *pCpuMapping) { @@ -229,43 +237,47 @@ pThis->__dispcapShareCallback__ = &__nvoc_thunk_GpuResource_dispcapShareCallback; - pThis->__dispcapControl__ = &__nvoc_thunk_GpuResource_dispcapControl; + pThis->__dispcapCheckMemInterUnmap__ = &__nvoc_thunk_RmResource_dispcapCheckMemInterUnmap; - pThis->__dispcapUnmap__ = &__nvoc_thunk_GpuResource_dispcapUnmap; + pThis->__dispcapMapTo__ = &__nvoc_thunk_RsResource_dispcapMapTo; - pThis->__dispcapGetMemInterMapParams__ = &__nvoc_thunk_RmResource_dispcapGetMemInterMapParams; + pThis->__dispcapGetMapAddrSpace__ = &__nvoc_thunk_GpuResource_dispcapGetMapAddrSpace; - pThis->__dispcapGetMemoryMappingDescriptor__ = &__nvoc_thunk_RmResource_dispcapGetMemoryMappingDescriptor; + pThis->__dispcapGetRefCount__ = &__nvoc_thunk_RsResource_dispcapGetRefCount; - pThis->__dispcapGetMapAddrSpace__ = &__nvoc_thunk_GpuResource_dispcapGetMapAddrSpace; + pThis->__dispcapAddAdditionalDependants__ = &__nvoc_thunk_RsResource_dispcapAddAdditionalDependants; + + pThis->__dispcapControl_Prologue__ = &__nvoc_thunk_RmResource_dispcapControl_Prologue; + + pThis->__dispcapInternalControlForward__ = &__nvoc_thunk_GpuResource_dispcapInternalControlForward; + + pThis->__dispcapUnmapFrom__ = &__nvoc_thunk_RsResource_dispcapUnmapFrom; + + pThis->__dispcapControl_Epilogue__ = &__nvoc_thunk_RmResource_dispcapControl_Epilogue; + + pThis->__dispcapControlLookup__ = &__nvoc_thunk_RsResource_dispcapControlLookup; pThis->__dispcapGetInternalObjectHandle__ = &__nvoc_thunk_GpuResource_dispcapGetInternalObjectHandle; - pThis->__dispcapControlFilter__ = &__nvoc_thunk_RsResource_dispcapControlFilter; + pThis->__dispcapControl__ = &__nvoc_thunk_GpuResource_dispcapControl; - pThis->__dispcapAddAdditionalDependants__ = &__nvoc_thunk_RsResource_dispcapAddAdditionalDependants; + pThis->__dispcapUnmap__ = &__nvoc_thunk_GpuResource_dispcapUnmap; - pThis->__dispcapGetRefCount__ = &__nvoc_thunk_RsResource_dispcapGetRefCount; + pThis->__dispcapGetMemInterMapParams__ = &__nvoc_thunk_RmResource_dispcapGetMemInterMapParams; - pThis->__dispcapCheckMemInterUnmap__ = &__nvoc_thunk_RmResource_dispcapCheckMemInterUnmap; + pThis->__dispcapGetMemoryMappingDescriptor__ = &__nvoc_thunk_RmResource_dispcapGetMemoryMappingDescriptor; - pThis->__dispcapMapTo__ = &__nvoc_thunk_RsResource_dispcapMapTo; + pThis->__dispcapControlFilter__ = &__nvoc_thunk_RsResource_dispcapControlFilter; - pThis->__dispcapControl_Prologue__ = &__nvoc_thunk_RmResource_dispcapControl_Prologue; + pThis->__dispcapControlSerialization_Prologue__ = &__nvoc_thunk_RmResource_dispcapControlSerialization_Prologue; pThis->__dispcapCanCopy__ = &__nvoc_thunk_RsResource_dispcapCanCopy; - pThis->__dispcapInternalControlForward__ = &__nvoc_thunk_GpuResource_dispcapInternalControlForward; - pThis->__dispcapPreDestruct__ = &__nvoc_thunk_RsResource_dispcapPreDestruct; - pThis->__dispcapUnmapFrom__ = &__nvoc_thunk_RsResource_dispcapUnmapFrom; - pThis->__dispcapIsDuplicate__ = &__nvoc_thunk_RsResource_dispcapIsDuplicate; - pThis->__dispcapControl_Epilogue__ = &__nvoc_thunk_RmResource_dispcapControl_Epilogue; - - pThis->__dispcapControlLookup__ = &__nvoc_thunk_RsResource_dispcapControlLookup; + pThis->__dispcapControlSerialization_Epilogue__ = &__nvoc_thunk_RmResource_dispcapControlSerialization_Epilogue; pThis->__dispcapMap__ = &__nvoc_thunk_GpuResource_dispcapMap; @@ -293,13 +305,16 @@ Object *pParentObj; DispCapabilities *pThis; - pThis = portMemAllocNonPaged(sizeof(DispCapabilities)); - if (pThis == NULL) return NV_ERR_NO_MEMORY; + status = __nvoc_handleObjCreateMemAlloc(createFlags, sizeof(DispCapabilities), (void**)&pThis, (void**)ppThis); + if (status != NV_OK) + return status; portMemSet(pThis, 0, sizeof(DispCapabilities)); __nvoc_initRtti(staticCast(pThis, Dynamic), &__nvoc_class_def_DispCapabilities); + pThis->__nvoc_base_GpuResource.__nvoc_base_RmResource.__nvoc_base_RsResource.__nvoc_base_Object.createFlags = createFlags; + if (pParent != NULL && !(createFlags & NVOC_OBJ_CREATE_FLAGS_PARENT_HALSPEC_ONLY)) { pParentObj = dynamicCast(pParent, Object); @@ -315,11 +330,17 @@ if (status != NV_OK) goto __nvoc_objCreate_DispCapabilities_cleanup; *ppThis = pThis; + return NV_OK; __nvoc_objCreate_DispCapabilities_cleanup: // do not call destructors here since the constructor already called them - portMemFree(pThis); + if (createFlags & NVOC_OBJ_CREATE_FLAGS_IN_PLACE_CONSTRUCT) + portMemSet(pThis, 0, sizeof(DispCapabilities)); + else + portMemFree(pThis); + + // coverity[leaked_storage:FALSE] return status; } diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/generated/g_disp_capabilities_nvoc.h nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_disp_capabilities_nvoc.h --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/generated/g_disp_capabilities_nvoc.h 2023-10-25 20:26:54.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_disp_capabilities_nvoc.h 2024-03-05 22:18:11.000000000 +0000 @@ -62,25 +62,27 @@ struct DispCapabilities *__nvoc_pbase_DispCapabilities; NV_STATUS (*__dispcapGetRegBaseOffsetAndSize__)(struct DispCapabilities *, struct OBJGPU *, NvU32 *, NvU32 *); NvBool (*__dispcapShareCallback__)(struct DispCapabilities *, struct RsClient *, struct RsResourceRef *, RS_SHARE_POLICY *); + NV_STATUS (*__dispcapCheckMemInterUnmap__)(struct DispCapabilities *, NvBool); + NV_STATUS (*__dispcapMapTo__)(struct DispCapabilities *, RS_RES_MAP_TO_PARAMS *); + NV_STATUS (*__dispcapGetMapAddrSpace__)(struct DispCapabilities *, struct CALL_CONTEXT *, NvU32, NV_ADDRESS_SPACE *); + NvU32 (*__dispcapGetRefCount__)(struct DispCapabilities *); + void (*__dispcapAddAdditionalDependants__)(struct RsClient *, struct DispCapabilities *, RsResourceRef *); + NV_STATUS (*__dispcapControl_Prologue__)(struct DispCapabilities *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); + NV_STATUS (*__dispcapInternalControlForward__)(struct DispCapabilities *, NvU32, void *, NvU32); + NV_STATUS (*__dispcapUnmapFrom__)(struct DispCapabilities *, RS_RES_UNMAP_FROM_PARAMS *); + void (*__dispcapControl_Epilogue__)(struct DispCapabilities *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); + NV_STATUS (*__dispcapControlLookup__)(struct DispCapabilities *, struct RS_RES_CONTROL_PARAMS_INTERNAL *, const struct NVOC_EXPORTED_METHOD_DEF **); + NvHandle (*__dispcapGetInternalObjectHandle__)(struct DispCapabilities *); NV_STATUS (*__dispcapControl__)(struct DispCapabilities *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); NV_STATUS (*__dispcapUnmap__)(struct DispCapabilities *, struct CALL_CONTEXT *, struct RsCpuMapping *); NV_STATUS (*__dispcapGetMemInterMapParams__)(struct DispCapabilities *, RMRES_MEM_INTER_MAP_PARAMS *); NV_STATUS (*__dispcapGetMemoryMappingDescriptor__)(struct DispCapabilities *, struct MEMORY_DESCRIPTOR **); - NV_STATUS (*__dispcapGetMapAddrSpace__)(struct DispCapabilities *, struct CALL_CONTEXT *, NvU32, NV_ADDRESS_SPACE *); - NvHandle (*__dispcapGetInternalObjectHandle__)(struct DispCapabilities *); NV_STATUS (*__dispcapControlFilter__)(struct DispCapabilities *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); - void (*__dispcapAddAdditionalDependants__)(struct RsClient *, struct DispCapabilities *, RsResourceRef *); - NvU32 (*__dispcapGetRefCount__)(struct DispCapabilities *); - NV_STATUS (*__dispcapCheckMemInterUnmap__)(struct DispCapabilities *, NvBool); - NV_STATUS (*__dispcapMapTo__)(struct DispCapabilities *, RS_RES_MAP_TO_PARAMS *); - NV_STATUS (*__dispcapControl_Prologue__)(struct DispCapabilities *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); + NV_STATUS (*__dispcapControlSerialization_Prologue__)(struct DispCapabilities *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); NvBool (*__dispcapCanCopy__)(struct DispCapabilities *); - NV_STATUS (*__dispcapInternalControlForward__)(struct DispCapabilities *, NvU32, void *, NvU32); void (*__dispcapPreDestruct__)(struct DispCapabilities *); - NV_STATUS (*__dispcapUnmapFrom__)(struct DispCapabilities *, RS_RES_UNMAP_FROM_PARAMS *); NV_STATUS (*__dispcapIsDuplicate__)(struct DispCapabilities *, NvHandle, NvBool *); - void (*__dispcapControl_Epilogue__)(struct DispCapabilities *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); - NV_STATUS (*__dispcapControlLookup__)(struct DispCapabilities *, struct RS_RES_CONTROL_PARAMS_INTERNAL *, const struct NVOC_EXPORTED_METHOD_DEF **); + void (*__dispcapControlSerialization_Epilogue__)(struct DispCapabilities *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); NV_STATUS (*__dispcapMap__)(struct DispCapabilities *, struct CALL_CONTEXT *, struct RS_CPU_MAP_PARAMS *, struct RsCpuMapping *); NvBool (*__dispcapAccessCallback__)(struct DispCapabilities *, struct RsClient *, void *, RsAccessRight); NvU32 ControlOffset; @@ -117,25 +119,27 @@ #define dispcapGetRegBaseOffsetAndSize(pDispCapabilities, pGpu, pOffset, pSize) dispcapGetRegBaseOffsetAndSize_DISPATCH(pDispCapabilities, pGpu, pOffset, pSize) #define dispcapShareCallback(pGpuResource, pInvokingClient, pParentRef, pSharePolicy) dispcapShareCallback_DISPATCH(pGpuResource, pInvokingClient, pParentRef, pSharePolicy) +#define dispcapCheckMemInterUnmap(pRmResource, bSubdeviceHandleProvided) dispcapCheckMemInterUnmap_DISPATCH(pRmResource, bSubdeviceHandleProvided) +#define dispcapMapTo(pResource, pParams) dispcapMapTo_DISPATCH(pResource, pParams) +#define dispcapGetMapAddrSpace(pGpuResource, pCallContext, mapFlags, pAddrSpace) dispcapGetMapAddrSpace_DISPATCH(pGpuResource, pCallContext, mapFlags, pAddrSpace) +#define dispcapGetRefCount(pResource) dispcapGetRefCount_DISPATCH(pResource) +#define dispcapAddAdditionalDependants(pClient, pResource, pReference) dispcapAddAdditionalDependants_DISPATCH(pClient, pResource, pReference) +#define dispcapControl_Prologue(pResource, pCallContext, pParams) dispcapControl_Prologue_DISPATCH(pResource, pCallContext, pParams) +#define dispcapInternalControlForward(pGpuResource, command, pParams, size) dispcapInternalControlForward_DISPATCH(pGpuResource, command, pParams, size) +#define dispcapUnmapFrom(pResource, pParams) dispcapUnmapFrom_DISPATCH(pResource, pParams) +#define dispcapControl_Epilogue(pResource, pCallContext, pParams) dispcapControl_Epilogue_DISPATCH(pResource, pCallContext, pParams) +#define dispcapControlLookup(pResource, pParams, ppEntry) dispcapControlLookup_DISPATCH(pResource, pParams, ppEntry) +#define dispcapGetInternalObjectHandle(pGpuResource) dispcapGetInternalObjectHandle_DISPATCH(pGpuResource) #define dispcapControl(pGpuResource, pCallContext, pParams) dispcapControl_DISPATCH(pGpuResource, pCallContext, pParams) #define dispcapUnmap(pGpuResource, pCallContext, pCpuMapping) dispcapUnmap_DISPATCH(pGpuResource, pCallContext, pCpuMapping) #define dispcapGetMemInterMapParams(pRmResource, pParams) dispcapGetMemInterMapParams_DISPATCH(pRmResource, pParams) #define dispcapGetMemoryMappingDescriptor(pRmResource, ppMemDesc) dispcapGetMemoryMappingDescriptor_DISPATCH(pRmResource, ppMemDesc) -#define dispcapGetMapAddrSpace(pGpuResource, pCallContext, mapFlags, pAddrSpace) dispcapGetMapAddrSpace_DISPATCH(pGpuResource, pCallContext, mapFlags, pAddrSpace) -#define dispcapGetInternalObjectHandle(pGpuResource) dispcapGetInternalObjectHandle_DISPATCH(pGpuResource) #define dispcapControlFilter(pResource, pCallContext, pParams) dispcapControlFilter_DISPATCH(pResource, pCallContext, pParams) -#define dispcapAddAdditionalDependants(pClient, pResource, pReference) dispcapAddAdditionalDependants_DISPATCH(pClient, pResource, pReference) -#define dispcapGetRefCount(pResource) dispcapGetRefCount_DISPATCH(pResource) -#define dispcapCheckMemInterUnmap(pRmResource, bSubdeviceHandleProvided) dispcapCheckMemInterUnmap_DISPATCH(pRmResource, bSubdeviceHandleProvided) -#define dispcapMapTo(pResource, pParams) dispcapMapTo_DISPATCH(pResource, pParams) -#define dispcapControl_Prologue(pResource, pCallContext, pParams) dispcapControl_Prologue_DISPATCH(pResource, pCallContext, pParams) +#define dispcapControlSerialization_Prologue(pResource, pCallContext, pParams) dispcapControlSerialization_Prologue_DISPATCH(pResource, pCallContext, pParams) #define dispcapCanCopy(pResource) dispcapCanCopy_DISPATCH(pResource) -#define dispcapInternalControlForward(pGpuResource, command, pParams, size) dispcapInternalControlForward_DISPATCH(pGpuResource, command, pParams, size) #define dispcapPreDestruct(pResource) dispcapPreDestruct_DISPATCH(pResource) -#define dispcapUnmapFrom(pResource, pParams) dispcapUnmapFrom_DISPATCH(pResource, pParams) #define dispcapIsDuplicate(pResource, hMemory, pDuplicate) dispcapIsDuplicate_DISPATCH(pResource, hMemory, pDuplicate) -#define dispcapControl_Epilogue(pResource, pCallContext, pParams) dispcapControl_Epilogue_DISPATCH(pResource, pCallContext, pParams) -#define dispcapControlLookup(pResource, pParams, ppEntry) dispcapControlLookup_DISPATCH(pResource, pParams, ppEntry) +#define dispcapControlSerialization_Epilogue(pResource, pCallContext, pParams) dispcapControlSerialization_Epilogue_DISPATCH(pResource, pCallContext, pParams) #define dispcapMap(pGpuResource, pCallContext, pParams, pCpuMapping) dispcapMap_DISPATCH(pGpuResource, pCallContext, pParams, pCpuMapping) #define dispcapAccessCallback(pResource, pInvokingClient, pAllocParams, accessRight) dispcapAccessCallback_DISPATCH(pResource, pInvokingClient, pAllocParams, accessRight) NV_STATUS dispcapGetRegBaseOffsetAndSize_IMPL(struct DispCapabilities *pDispCapabilities, struct OBJGPU *pGpu, NvU32 *pOffset, NvU32 *pSize); @@ -148,80 +152,88 @@ return pGpuResource->__dispcapShareCallback__(pGpuResource, pInvokingClient, pParentRef, pSharePolicy); } -static inline NV_STATUS dispcapControl_DISPATCH(struct DispCapabilities *pGpuResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { - return pGpuResource->__dispcapControl__(pGpuResource, pCallContext, pParams); +static inline NV_STATUS dispcapCheckMemInterUnmap_DISPATCH(struct DispCapabilities *pRmResource, NvBool bSubdeviceHandleProvided) { + return pRmResource->__dispcapCheckMemInterUnmap__(pRmResource, bSubdeviceHandleProvided); } -static inline NV_STATUS dispcapUnmap_DISPATCH(struct DispCapabilities *pGpuResource, struct CALL_CONTEXT *pCallContext, struct RsCpuMapping *pCpuMapping) { - return pGpuResource->__dispcapUnmap__(pGpuResource, pCallContext, pCpuMapping); +static inline NV_STATUS dispcapMapTo_DISPATCH(struct DispCapabilities *pResource, RS_RES_MAP_TO_PARAMS *pParams) { + return pResource->__dispcapMapTo__(pResource, pParams); } -static inline NV_STATUS dispcapGetMemInterMapParams_DISPATCH(struct DispCapabilities *pRmResource, RMRES_MEM_INTER_MAP_PARAMS *pParams) { - return pRmResource->__dispcapGetMemInterMapParams__(pRmResource, pParams); +static inline NV_STATUS dispcapGetMapAddrSpace_DISPATCH(struct DispCapabilities *pGpuResource, struct CALL_CONTEXT *pCallContext, NvU32 mapFlags, NV_ADDRESS_SPACE *pAddrSpace) { + return pGpuResource->__dispcapGetMapAddrSpace__(pGpuResource, pCallContext, mapFlags, pAddrSpace); } -static inline NV_STATUS dispcapGetMemoryMappingDescriptor_DISPATCH(struct DispCapabilities *pRmResource, struct MEMORY_DESCRIPTOR **ppMemDesc) { - return pRmResource->__dispcapGetMemoryMappingDescriptor__(pRmResource, ppMemDesc); +static inline NvU32 dispcapGetRefCount_DISPATCH(struct DispCapabilities *pResource) { + return pResource->__dispcapGetRefCount__(pResource); } -static inline NV_STATUS dispcapGetMapAddrSpace_DISPATCH(struct DispCapabilities *pGpuResource, struct CALL_CONTEXT *pCallContext, NvU32 mapFlags, NV_ADDRESS_SPACE *pAddrSpace) { - return pGpuResource->__dispcapGetMapAddrSpace__(pGpuResource, pCallContext, mapFlags, pAddrSpace); +static inline void dispcapAddAdditionalDependants_DISPATCH(struct RsClient *pClient, struct DispCapabilities *pResource, RsResourceRef *pReference) { + pResource->__dispcapAddAdditionalDependants__(pClient, pResource, pReference); +} + +static inline NV_STATUS dispcapControl_Prologue_DISPATCH(struct DispCapabilities *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return pResource->__dispcapControl_Prologue__(pResource, pCallContext, pParams); +} + +static inline NV_STATUS dispcapInternalControlForward_DISPATCH(struct DispCapabilities *pGpuResource, NvU32 command, void *pParams, NvU32 size) { + return pGpuResource->__dispcapInternalControlForward__(pGpuResource, command, pParams, size); +} + +static inline NV_STATUS dispcapUnmapFrom_DISPATCH(struct DispCapabilities *pResource, RS_RES_UNMAP_FROM_PARAMS *pParams) { + return pResource->__dispcapUnmapFrom__(pResource, pParams); +} + +static inline void dispcapControl_Epilogue_DISPATCH(struct DispCapabilities *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + pResource->__dispcapControl_Epilogue__(pResource, pCallContext, pParams); +} + +static inline NV_STATUS dispcapControlLookup_DISPATCH(struct DispCapabilities *pResource, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams, const struct NVOC_EXPORTED_METHOD_DEF **ppEntry) { + return pResource->__dispcapControlLookup__(pResource, pParams, ppEntry); } static inline NvHandle dispcapGetInternalObjectHandle_DISPATCH(struct DispCapabilities *pGpuResource) { return pGpuResource->__dispcapGetInternalObjectHandle__(pGpuResource); } -static inline NV_STATUS dispcapControlFilter_DISPATCH(struct DispCapabilities *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { - return pResource->__dispcapControlFilter__(pResource, pCallContext, pParams); +static inline NV_STATUS dispcapControl_DISPATCH(struct DispCapabilities *pGpuResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return pGpuResource->__dispcapControl__(pGpuResource, pCallContext, pParams); } -static inline void dispcapAddAdditionalDependants_DISPATCH(struct RsClient *pClient, struct DispCapabilities *pResource, RsResourceRef *pReference) { - pResource->__dispcapAddAdditionalDependants__(pClient, pResource, pReference); +static inline NV_STATUS dispcapUnmap_DISPATCH(struct DispCapabilities *pGpuResource, struct CALL_CONTEXT *pCallContext, struct RsCpuMapping *pCpuMapping) { + return pGpuResource->__dispcapUnmap__(pGpuResource, pCallContext, pCpuMapping); } -static inline NvU32 dispcapGetRefCount_DISPATCH(struct DispCapabilities *pResource) { - return pResource->__dispcapGetRefCount__(pResource); +static inline NV_STATUS dispcapGetMemInterMapParams_DISPATCH(struct DispCapabilities *pRmResource, RMRES_MEM_INTER_MAP_PARAMS *pParams) { + return pRmResource->__dispcapGetMemInterMapParams__(pRmResource, pParams); } -static inline NV_STATUS dispcapCheckMemInterUnmap_DISPATCH(struct DispCapabilities *pRmResource, NvBool bSubdeviceHandleProvided) { - return pRmResource->__dispcapCheckMemInterUnmap__(pRmResource, bSubdeviceHandleProvided); +static inline NV_STATUS dispcapGetMemoryMappingDescriptor_DISPATCH(struct DispCapabilities *pRmResource, struct MEMORY_DESCRIPTOR **ppMemDesc) { + return pRmResource->__dispcapGetMemoryMappingDescriptor__(pRmResource, ppMemDesc); } -static inline NV_STATUS dispcapMapTo_DISPATCH(struct DispCapabilities *pResource, RS_RES_MAP_TO_PARAMS *pParams) { - return pResource->__dispcapMapTo__(pResource, pParams); +static inline NV_STATUS dispcapControlFilter_DISPATCH(struct DispCapabilities *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return pResource->__dispcapControlFilter__(pResource, pCallContext, pParams); } -static inline NV_STATUS dispcapControl_Prologue_DISPATCH(struct DispCapabilities *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { - return pResource->__dispcapControl_Prologue__(pResource, pCallContext, pParams); +static inline NV_STATUS dispcapControlSerialization_Prologue_DISPATCH(struct DispCapabilities *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return pResource->__dispcapControlSerialization_Prologue__(pResource, pCallContext, pParams); } static inline NvBool dispcapCanCopy_DISPATCH(struct DispCapabilities *pResource) { return pResource->__dispcapCanCopy__(pResource); } -static inline NV_STATUS dispcapInternalControlForward_DISPATCH(struct DispCapabilities *pGpuResource, NvU32 command, void *pParams, NvU32 size) { - return pGpuResource->__dispcapInternalControlForward__(pGpuResource, command, pParams, size); -} - static inline void dispcapPreDestruct_DISPATCH(struct DispCapabilities *pResource) { pResource->__dispcapPreDestruct__(pResource); } -static inline NV_STATUS dispcapUnmapFrom_DISPATCH(struct DispCapabilities *pResource, RS_RES_UNMAP_FROM_PARAMS *pParams) { - return pResource->__dispcapUnmapFrom__(pResource, pParams); -} - static inline NV_STATUS dispcapIsDuplicate_DISPATCH(struct DispCapabilities *pResource, NvHandle hMemory, NvBool *pDuplicate) { return pResource->__dispcapIsDuplicate__(pResource, hMemory, pDuplicate); } -static inline void dispcapControl_Epilogue_DISPATCH(struct DispCapabilities *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { - pResource->__dispcapControl_Epilogue__(pResource, pCallContext, pParams); -} - -static inline NV_STATUS dispcapControlLookup_DISPATCH(struct DispCapabilities *pResource, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams, const struct NVOC_EXPORTED_METHOD_DEF **ppEntry) { - return pResource->__dispcapControlLookup__(pResource, pParams, ppEntry); +static inline void dispcapControlSerialization_Epilogue_DISPATCH(struct DispCapabilities *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + pResource->__dispcapControlSerialization_Epilogue__(pResource, pCallContext, pParams); } static inline NV_STATUS dispcapMap_DISPATCH(struct DispCapabilities *pGpuResource, struct CALL_CONTEXT *pCallContext, struct RS_CPU_MAP_PARAMS *pParams, struct RsCpuMapping *pCpuMapping) { diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/generated/g_disp_channel_nvoc.c nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_disp_channel_nvoc.c --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/generated/g_disp_channel_nvoc.c 2023-10-25 20:26:54.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_disp_channel_nvoc.c 2024-03-05 22:18:11.000000000 +0000 @@ -119,16 +119,16 @@ return gpuresShareCallback((struct GpuResource *)(((unsigned char *)pGpuResource) + __nvoc_rtti_DispChannel_GpuResource.offset), pInvokingClient, pParentRef, pSharePolicy); } -static NV_STATUS __nvoc_thunk_RsResource_dispchnMapTo(struct DispChannel *pResource, RS_RES_MAP_TO_PARAMS *pParams) { - return resMapTo((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_DispChannel_RsResource.offset), pParams); +static NV_STATUS __nvoc_thunk_RmResource_dispchnCheckMemInterUnmap(struct DispChannel *pRmResource, NvBool bSubdeviceHandleProvided) { + return rmresCheckMemInterUnmap((struct RmResource *)(((unsigned char *)pRmResource) + __nvoc_rtti_DispChannel_RmResource.offset), bSubdeviceHandleProvided); } static NV_STATUS __nvoc_thunk_Notifier_dispchnGetOrAllocNotifShare(struct DispChannel *pNotifier, NvHandle hNotifierClient, NvHandle hNotifierResource, struct NotifShare **ppNotifShare) { return notifyGetOrAllocNotifShare((struct Notifier *)(((unsigned char *)pNotifier) + __nvoc_rtti_DispChannel_Notifier.offset), hNotifierClient, hNotifierResource, ppNotifShare); } -static NV_STATUS __nvoc_thunk_RmResource_dispchnCheckMemInterUnmap(struct DispChannel *pRmResource, NvBool bSubdeviceHandleProvided) { - return rmresCheckMemInterUnmap((struct RmResource *)(((unsigned char *)pRmResource) + __nvoc_rtti_DispChannel_RmResource.offset), bSubdeviceHandleProvided); +static NV_STATUS __nvoc_thunk_RsResource_dispchnMapTo(struct DispChannel *pResource, RS_RES_MAP_TO_PARAMS *pParams) { + return resMapTo((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_DispChannel_RsResource.offset), pParams); } static NV_STATUS __nvoc_thunk_GpuResource_dispchnGetMapAddrSpace(struct DispChannel *pGpuResource, struct CALL_CONTEXT *pCallContext, NvU32 mapFlags, NV_ADDRESS_SPACE *pAddrSpace) { @@ -195,6 +195,10 @@ return notifyUnregisterEvent((struct Notifier *)(((unsigned char *)pNotifier) + __nvoc_rtti_DispChannel_Notifier.offset), hNotifierClient, hNotifierResource, hEventClient, hEvent); } +static NV_STATUS __nvoc_thunk_RmResource_dispchnControlSerialization_Prologue(struct DispChannel *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return rmresControlSerialization_Prologue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_DispChannel_RmResource.offset), pCallContext, pParams); +} + static NvBool __nvoc_thunk_RsResource_dispchnCanCopy(struct DispChannel *pResource) { return resCanCopy((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_DispChannel_RsResource.offset)); } @@ -207,6 +211,10 @@ return resIsDuplicate((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_DispChannel_RsResource.offset), hMemory, pDuplicate); } +static void __nvoc_thunk_RmResource_dispchnControlSerialization_Epilogue(struct DispChannel *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + rmresControlSerialization_Epilogue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_DispChannel_RmResource.offset), pCallContext, pParams); +} + static PEVENTNOTIFICATION *__nvoc_thunk_Notifier_dispchnGetNotificationListPtr(struct DispChannel *pNotifier) { return notifyGetNotificationListPtr((struct Notifier *)(((unsigned char *)pNotifier) + __nvoc_rtti_DispChannel_Notifier.offset)); } @@ -275,11 +283,11 @@ pThis->__dispchnShareCallback__ = &__nvoc_thunk_GpuResource_dispchnShareCallback; - pThis->__dispchnMapTo__ = &__nvoc_thunk_RsResource_dispchnMapTo; + pThis->__dispchnCheckMemInterUnmap__ = &__nvoc_thunk_RmResource_dispchnCheckMemInterUnmap; pThis->__dispchnGetOrAllocNotifShare__ = &__nvoc_thunk_Notifier_dispchnGetOrAllocNotifShare; - pThis->__dispchnCheckMemInterUnmap__ = &__nvoc_thunk_RmResource_dispchnCheckMemInterUnmap; + pThis->__dispchnMapTo__ = &__nvoc_thunk_RsResource_dispchnMapTo; pThis->__dispchnGetMapAddrSpace__ = &__nvoc_thunk_GpuResource_dispchnGetMapAddrSpace; @@ -313,12 +321,16 @@ pThis->__dispchnUnregisterEvent__ = &__nvoc_thunk_Notifier_dispchnUnregisterEvent; + pThis->__dispchnControlSerialization_Prologue__ = &__nvoc_thunk_RmResource_dispchnControlSerialization_Prologue; + pThis->__dispchnCanCopy__ = &__nvoc_thunk_RsResource_dispchnCanCopy; pThis->__dispchnPreDestruct__ = &__nvoc_thunk_RsResource_dispchnPreDestruct; pThis->__dispchnIsDuplicate__ = &__nvoc_thunk_RsResource_dispchnIsDuplicate; + pThis->__dispchnControlSerialization_Epilogue__ = &__nvoc_thunk_RmResource_dispchnControlSerialization_Epilogue; + pThis->__dispchnGetNotificationListPtr__ = &__nvoc_thunk_Notifier_dispchnGetNotificationListPtr; pThis->__dispchnGetNotificationShare__ = &__nvoc_thunk_Notifier_dispchnGetNotificationShare; @@ -353,13 +365,16 @@ Object *pParentObj; DispChannel *pThis; - pThis = portMemAllocNonPaged(sizeof(DispChannel)); - if (pThis == NULL) return NV_ERR_NO_MEMORY; + status = __nvoc_handleObjCreateMemAlloc(createFlags, sizeof(DispChannel), (void**)&pThis, (void**)ppThis); + if (status != NV_OK) + return status; portMemSet(pThis, 0, sizeof(DispChannel)); __nvoc_initRtti(staticCast(pThis, Dynamic), &__nvoc_class_def_DispChannel); + pThis->__nvoc_base_GpuResource.__nvoc_base_RmResource.__nvoc_base_RsResource.__nvoc_base_Object.createFlags = createFlags; + if (pParent != NULL && !(createFlags & NVOC_OBJ_CREATE_FLAGS_PARENT_HALSPEC_ONLY)) { pParentObj = dynamicCast(pParent, Object); @@ -375,11 +390,17 @@ if (status != NV_OK) goto __nvoc_objCreate_DispChannel_cleanup; *ppThis = pThis; + return NV_OK; __nvoc_objCreate_DispChannel_cleanup: // do not call destructors here since the constructor already called them - portMemFree(pThis); + if (createFlags & NVOC_OBJ_CREATE_FLAGS_IN_PLACE_CONSTRUCT) + portMemSet(pThis, 0, sizeof(DispChannel)); + else + portMemFree(pThis); + + // coverity[leaked_storage:FALSE] return status; } @@ -511,16 +532,16 @@ return gpuresShareCallback((struct GpuResource *)(((unsigned char *)pGpuResource) + __nvoc_rtti_DispChannelPio_GpuResource.offset), pInvokingClient, pParentRef, pSharePolicy); } -static NV_STATUS __nvoc_thunk_RsResource_dispchnpioMapTo(struct DispChannelPio *pResource, RS_RES_MAP_TO_PARAMS *pParams) { - return resMapTo((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_DispChannelPio_RsResource.offset), pParams); +static NV_STATUS __nvoc_thunk_RmResource_dispchnpioCheckMemInterUnmap(struct DispChannelPio *pRmResource, NvBool bSubdeviceHandleProvided) { + return rmresCheckMemInterUnmap((struct RmResource *)(((unsigned char *)pRmResource) + __nvoc_rtti_DispChannelPio_RmResource.offset), bSubdeviceHandleProvided); } static NV_STATUS __nvoc_thunk_Notifier_dispchnpioGetOrAllocNotifShare(struct DispChannelPio *pNotifier, NvHandle hNotifierClient, NvHandle hNotifierResource, struct NotifShare **ppNotifShare) { return notifyGetOrAllocNotifShare((struct Notifier *)(((unsigned char *)pNotifier) + __nvoc_rtti_DispChannelPio_Notifier.offset), hNotifierClient, hNotifierResource, ppNotifShare); } -static NV_STATUS __nvoc_thunk_RmResource_dispchnpioCheckMemInterUnmap(struct DispChannelPio *pRmResource, NvBool bSubdeviceHandleProvided) { - return rmresCheckMemInterUnmap((struct RmResource *)(((unsigned char *)pRmResource) + __nvoc_rtti_DispChannelPio_RmResource.offset), bSubdeviceHandleProvided); +static NV_STATUS __nvoc_thunk_RsResource_dispchnpioMapTo(struct DispChannelPio *pResource, RS_RES_MAP_TO_PARAMS *pParams) { + return resMapTo((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_DispChannelPio_RsResource.offset), pParams); } static NV_STATUS __nvoc_thunk_GpuResource_dispchnpioGetMapAddrSpace(struct DispChannelPio *pGpuResource, struct CALL_CONTEXT *pCallContext, NvU32 mapFlags, NV_ADDRESS_SPACE *pAddrSpace) { @@ -591,6 +612,10 @@ return notifyUnregisterEvent((struct Notifier *)(((unsigned char *)pNotifier) + __nvoc_rtti_DispChannelPio_Notifier.offset), hNotifierClient, hNotifierResource, hEventClient, hEvent); } +static NV_STATUS __nvoc_thunk_RmResource_dispchnpioControlSerialization_Prologue(struct DispChannelPio *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return rmresControlSerialization_Prologue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_DispChannelPio_RmResource.offset), pCallContext, pParams); +} + static NvBool __nvoc_thunk_RsResource_dispchnpioCanCopy(struct DispChannelPio *pResource) { return resCanCopy((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_DispChannelPio_RsResource.offset)); } @@ -603,6 +628,10 @@ return resIsDuplicate((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_DispChannelPio_RsResource.offset), hMemory, pDuplicate); } +static void __nvoc_thunk_RmResource_dispchnpioControlSerialization_Epilogue(struct DispChannelPio *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + rmresControlSerialization_Epilogue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_DispChannelPio_RmResource.offset), pCallContext, pParams); +} + static PEVENTNOTIFICATION *__nvoc_thunk_Notifier_dispchnpioGetNotificationListPtr(struct DispChannelPio *pNotifier) { return notifyGetNotificationListPtr((struct Notifier *)(((unsigned char *)pNotifier) + __nvoc_rtti_DispChannelPio_Notifier.offset)); } @@ -659,11 +688,11 @@ pThis->__dispchnpioShareCallback__ = &__nvoc_thunk_GpuResource_dispchnpioShareCallback; - pThis->__dispchnpioMapTo__ = &__nvoc_thunk_RsResource_dispchnpioMapTo; + pThis->__dispchnpioCheckMemInterUnmap__ = &__nvoc_thunk_RmResource_dispchnpioCheckMemInterUnmap; pThis->__dispchnpioGetOrAllocNotifShare__ = &__nvoc_thunk_Notifier_dispchnpioGetOrAllocNotifShare; - pThis->__dispchnpioCheckMemInterUnmap__ = &__nvoc_thunk_RmResource_dispchnpioCheckMemInterUnmap; + pThis->__dispchnpioMapTo__ = &__nvoc_thunk_RsResource_dispchnpioMapTo; pThis->__dispchnpioGetMapAddrSpace__ = &__nvoc_thunk_GpuResource_dispchnpioGetMapAddrSpace; @@ -699,12 +728,16 @@ pThis->__dispchnpioUnregisterEvent__ = &__nvoc_thunk_Notifier_dispchnpioUnregisterEvent; + pThis->__dispchnpioControlSerialization_Prologue__ = &__nvoc_thunk_RmResource_dispchnpioControlSerialization_Prologue; + pThis->__dispchnpioCanCopy__ = &__nvoc_thunk_RsResource_dispchnpioCanCopy; pThis->__dispchnpioPreDestruct__ = &__nvoc_thunk_RsResource_dispchnpioPreDestruct; pThis->__dispchnpioIsDuplicate__ = &__nvoc_thunk_RsResource_dispchnpioIsDuplicate; + pThis->__dispchnpioControlSerialization_Epilogue__ = &__nvoc_thunk_RmResource_dispchnpioControlSerialization_Epilogue; + pThis->__dispchnpioGetNotificationListPtr__ = &__nvoc_thunk_Notifier_dispchnpioGetNotificationListPtr; pThis->__dispchnpioGetNotificationShare__ = &__nvoc_thunk_Notifier_dispchnpioGetNotificationShare; @@ -738,13 +771,16 @@ Object *pParentObj; DispChannelPio *pThis; - pThis = portMemAllocNonPaged(sizeof(DispChannelPio)); - if (pThis == NULL) return NV_ERR_NO_MEMORY; + status = __nvoc_handleObjCreateMemAlloc(createFlags, sizeof(DispChannelPio), (void**)&pThis, (void**)ppThis); + if (status != NV_OK) + return status; portMemSet(pThis, 0, sizeof(DispChannelPio)); __nvoc_initRtti(staticCast(pThis, Dynamic), &__nvoc_class_def_DispChannelPio); + pThis->__nvoc_base_DispChannel.__nvoc_base_GpuResource.__nvoc_base_RmResource.__nvoc_base_RsResource.__nvoc_base_Object.createFlags = createFlags; + if (pParent != NULL && !(createFlags & NVOC_OBJ_CREATE_FLAGS_PARENT_HALSPEC_ONLY)) { pParentObj = dynamicCast(pParent, Object); @@ -760,11 +796,17 @@ if (status != NV_OK) goto __nvoc_objCreate_DispChannelPio_cleanup; *ppThis = pThis; + return NV_OK; __nvoc_objCreate_DispChannelPio_cleanup: // do not call destructors here since the constructor already called them - portMemFree(pThis); + if (createFlags & NVOC_OBJ_CREATE_FLAGS_IN_PLACE_CONSTRUCT) + portMemSet(pThis, 0, sizeof(DispChannelPio)); + else + portMemFree(pThis); + + // coverity[leaked_storage:FALSE] return status; } @@ -895,16 +937,16 @@ return gpuresShareCallback((struct GpuResource *)(((unsigned char *)pGpuResource) + __nvoc_rtti_DispChannelDma_GpuResource.offset), pInvokingClient, pParentRef, pSharePolicy); } -static NV_STATUS __nvoc_thunk_RsResource_dispchndmaMapTo(struct DispChannelDma *pResource, RS_RES_MAP_TO_PARAMS *pParams) { - return resMapTo((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_DispChannelDma_RsResource.offset), pParams); +static NV_STATUS __nvoc_thunk_RmResource_dispchndmaCheckMemInterUnmap(struct DispChannelDma *pRmResource, NvBool bSubdeviceHandleProvided) { + return rmresCheckMemInterUnmap((struct RmResource *)(((unsigned char *)pRmResource) + __nvoc_rtti_DispChannelDma_RmResource.offset), bSubdeviceHandleProvided); } static NV_STATUS __nvoc_thunk_Notifier_dispchndmaGetOrAllocNotifShare(struct DispChannelDma *pNotifier, NvHandle hNotifierClient, NvHandle hNotifierResource, struct NotifShare **ppNotifShare) { return notifyGetOrAllocNotifShare((struct Notifier *)(((unsigned char *)pNotifier) + __nvoc_rtti_DispChannelDma_Notifier.offset), hNotifierClient, hNotifierResource, ppNotifShare); } -static NV_STATUS __nvoc_thunk_RmResource_dispchndmaCheckMemInterUnmap(struct DispChannelDma *pRmResource, NvBool bSubdeviceHandleProvided) { - return rmresCheckMemInterUnmap((struct RmResource *)(((unsigned char *)pRmResource) + __nvoc_rtti_DispChannelDma_RmResource.offset), bSubdeviceHandleProvided); +static NV_STATUS __nvoc_thunk_RsResource_dispchndmaMapTo(struct DispChannelDma *pResource, RS_RES_MAP_TO_PARAMS *pParams) { + return resMapTo((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_DispChannelDma_RsResource.offset), pParams); } static NV_STATUS __nvoc_thunk_GpuResource_dispchndmaGetMapAddrSpace(struct DispChannelDma *pGpuResource, struct CALL_CONTEXT *pCallContext, NvU32 mapFlags, NV_ADDRESS_SPACE *pAddrSpace) { @@ -975,6 +1017,10 @@ return notifyUnregisterEvent((struct Notifier *)(((unsigned char *)pNotifier) + __nvoc_rtti_DispChannelDma_Notifier.offset), hNotifierClient, hNotifierResource, hEventClient, hEvent); } +static NV_STATUS __nvoc_thunk_RmResource_dispchndmaControlSerialization_Prologue(struct DispChannelDma *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return rmresControlSerialization_Prologue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_DispChannelDma_RmResource.offset), pCallContext, pParams); +} + static NvBool __nvoc_thunk_RsResource_dispchndmaCanCopy(struct DispChannelDma *pResource) { return resCanCopy((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_DispChannelDma_RsResource.offset)); } @@ -987,6 +1033,10 @@ return resIsDuplicate((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_DispChannelDma_RsResource.offset), hMemory, pDuplicate); } +static void __nvoc_thunk_RmResource_dispchndmaControlSerialization_Epilogue(struct DispChannelDma *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + rmresControlSerialization_Epilogue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_DispChannelDma_RmResource.offset), pCallContext, pParams); +} + static PEVENTNOTIFICATION *__nvoc_thunk_Notifier_dispchndmaGetNotificationListPtr(struct DispChannelDma *pNotifier) { return notifyGetNotificationListPtr((struct Notifier *)(((unsigned char *)pNotifier) + __nvoc_rtti_DispChannelDma_Notifier.offset)); } @@ -1043,11 +1093,11 @@ pThis->__dispchndmaShareCallback__ = &__nvoc_thunk_GpuResource_dispchndmaShareCallback; - pThis->__dispchndmaMapTo__ = &__nvoc_thunk_RsResource_dispchndmaMapTo; + pThis->__dispchndmaCheckMemInterUnmap__ = &__nvoc_thunk_RmResource_dispchndmaCheckMemInterUnmap; pThis->__dispchndmaGetOrAllocNotifShare__ = &__nvoc_thunk_Notifier_dispchndmaGetOrAllocNotifShare; - pThis->__dispchndmaCheckMemInterUnmap__ = &__nvoc_thunk_RmResource_dispchndmaCheckMemInterUnmap; + pThis->__dispchndmaMapTo__ = &__nvoc_thunk_RsResource_dispchndmaMapTo; pThis->__dispchndmaGetMapAddrSpace__ = &__nvoc_thunk_GpuResource_dispchndmaGetMapAddrSpace; @@ -1083,12 +1133,16 @@ pThis->__dispchndmaUnregisterEvent__ = &__nvoc_thunk_Notifier_dispchndmaUnregisterEvent; + pThis->__dispchndmaControlSerialization_Prologue__ = &__nvoc_thunk_RmResource_dispchndmaControlSerialization_Prologue; + pThis->__dispchndmaCanCopy__ = &__nvoc_thunk_RsResource_dispchndmaCanCopy; pThis->__dispchndmaPreDestruct__ = &__nvoc_thunk_RsResource_dispchndmaPreDestruct; pThis->__dispchndmaIsDuplicate__ = &__nvoc_thunk_RsResource_dispchndmaIsDuplicate; + pThis->__dispchndmaControlSerialization_Epilogue__ = &__nvoc_thunk_RmResource_dispchndmaControlSerialization_Epilogue; + pThis->__dispchndmaGetNotificationListPtr__ = &__nvoc_thunk_Notifier_dispchndmaGetNotificationListPtr; pThis->__dispchndmaGetNotificationShare__ = &__nvoc_thunk_Notifier_dispchndmaGetNotificationShare; @@ -1122,13 +1176,16 @@ Object *pParentObj; DispChannelDma *pThis; - pThis = portMemAllocNonPaged(sizeof(DispChannelDma)); - if (pThis == NULL) return NV_ERR_NO_MEMORY; + status = __nvoc_handleObjCreateMemAlloc(createFlags, sizeof(DispChannelDma), (void**)&pThis, (void**)ppThis); + if (status != NV_OK) + return status; portMemSet(pThis, 0, sizeof(DispChannelDma)); __nvoc_initRtti(staticCast(pThis, Dynamic), &__nvoc_class_def_DispChannelDma); + pThis->__nvoc_base_DispChannel.__nvoc_base_GpuResource.__nvoc_base_RmResource.__nvoc_base_RsResource.__nvoc_base_Object.createFlags = createFlags; + if (pParent != NULL && !(createFlags & NVOC_OBJ_CREATE_FLAGS_PARENT_HALSPEC_ONLY)) { pParentObj = dynamicCast(pParent, Object); @@ -1144,11 +1201,17 @@ if (status != NV_OK) goto __nvoc_objCreate_DispChannelDma_cleanup; *ppThis = pThis; + return NV_OK; __nvoc_objCreate_DispChannelDma_cleanup: // do not call destructors here since the constructor already called them - portMemFree(pThis); + if (createFlags & NVOC_OBJ_CREATE_FLAGS_IN_PLACE_CONSTRUCT) + portMemSet(pThis, 0, sizeof(DispChannelDma)); + else + portMemFree(pThis); + + // coverity[leaked_storage:FALSE] return status; } diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/generated/g_disp_channel_nvoc.h nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_disp_channel_nvoc.h --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/generated/g_disp_channel_nvoc.h 2023-10-25 20:26:54.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_disp_channel_nvoc.h 2024-03-05 22:18:11.000000000 +0000 @@ -91,9 +91,9 @@ struct DispChannel *__nvoc_pbase_DispChannel; NV_STATUS (*__dispchnGetRegBaseOffsetAndSize__)(struct DispChannel *, struct OBJGPU *, NvU32 *, NvU32 *); NvBool (*__dispchnShareCallback__)(struct DispChannel *, struct RsClient *, struct RsResourceRef *, RS_SHARE_POLICY *); - NV_STATUS (*__dispchnMapTo__)(struct DispChannel *, RS_RES_MAP_TO_PARAMS *); - NV_STATUS (*__dispchnGetOrAllocNotifShare__)(struct DispChannel *, NvHandle, NvHandle, struct NotifShare **); NV_STATUS (*__dispchnCheckMemInterUnmap__)(struct DispChannel *, NvBool); + NV_STATUS (*__dispchnGetOrAllocNotifShare__)(struct DispChannel *, NvHandle, NvHandle, struct NotifShare **); + NV_STATUS (*__dispchnMapTo__)(struct DispChannel *, RS_RES_MAP_TO_PARAMS *); NV_STATUS (*__dispchnGetMapAddrSpace__)(struct DispChannel *, struct CALL_CONTEXT *, NvU32, NV_ADDRESS_SPACE *); void (*__dispchnSetNotificationShare__)(struct DispChannel *, struct NotifShare *); NvU32 (*__dispchnGetRefCount__)(struct DispChannel *); @@ -110,9 +110,11 @@ NV_STATUS (*__dispchnGetMemoryMappingDescriptor__)(struct DispChannel *, struct MEMORY_DESCRIPTOR **); NV_STATUS (*__dispchnControlFilter__)(struct DispChannel *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); NV_STATUS (*__dispchnUnregisterEvent__)(struct DispChannel *, NvHandle, NvHandle, NvHandle, NvHandle); + NV_STATUS (*__dispchnControlSerialization_Prologue__)(struct DispChannel *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); NvBool (*__dispchnCanCopy__)(struct DispChannel *); void (*__dispchnPreDestruct__)(struct DispChannel *); NV_STATUS (*__dispchnIsDuplicate__)(struct DispChannel *, NvHandle, NvBool *); + void (*__dispchnControlSerialization_Epilogue__)(struct DispChannel *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); PEVENTNOTIFICATION *(*__dispchnGetNotificationListPtr__)(struct DispChannel *); struct NotifShare *(*__dispchnGetNotificationShare__)(struct DispChannel *); NV_STATUS (*__dispchnMap__)(struct DispChannel *, struct CALL_CONTEXT *, struct RS_CPU_MAP_PARAMS *, struct RsCpuMapping *); @@ -157,9 +159,9 @@ #define dispchnGetRegBaseOffsetAndSize(pDispChannel, pGpu, pOffset, pSize) dispchnGetRegBaseOffsetAndSize_DISPATCH(pDispChannel, pGpu, pOffset, pSize) #define dispchnShareCallback(pGpuResource, pInvokingClient, pParentRef, pSharePolicy) dispchnShareCallback_DISPATCH(pGpuResource, pInvokingClient, pParentRef, pSharePolicy) -#define dispchnMapTo(pResource, pParams) dispchnMapTo_DISPATCH(pResource, pParams) -#define dispchnGetOrAllocNotifShare(pNotifier, hNotifierClient, hNotifierResource, ppNotifShare) dispchnGetOrAllocNotifShare_DISPATCH(pNotifier, hNotifierClient, hNotifierResource, ppNotifShare) #define dispchnCheckMemInterUnmap(pRmResource, bSubdeviceHandleProvided) dispchnCheckMemInterUnmap_DISPATCH(pRmResource, bSubdeviceHandleProvided) +#define dispchnGetOrAllocNotifShare(pNotifier, hNotifierClient, hNotifierResource, ppNotifShare) dispchnGetOrAllocNotifShare_DISPATCH(pNotifier, hNotifierClient, hNotifierResource, ppNotifShare) +#define dispchnMapTo(pResource, pParams) dispchnMapTo_DISPATCH(pResource, pParams) #define dispchnGetMapAddrSpace(pGpuResource, pCallContext, mapFlags, pAddrSpace) dispchnGetMapAddrSpace_DISPATCH(pGpuResource, pCallContext, mapFlags, pAddrSpace) #define dispchnSetNotificationShare(pNotifier, pNotifShare) dispchnSetNotificationShare_DISPATCH(pNotifier, pNotifShare) #define dispchnGetRefCount(pResource) dispchnGetRefCount_DISPATCH(pResource) @@ -176,9 +178,11 @@ #define dispchnGetMemoryMappingDescriptor(pRmResource, ppMemDesc) dispchnGetMemoryMappingDescriptor_DISPATCH(pRmResource, ppMemDesc) #define dispchnControlFilter(pResource, pCallContext, pParams) dispchnControlFilter_DISPATCH(pResource, pCallContext, pParams) #define dispchnUnregisterEvent(pNotifier, hNotifierClient, hNotifierResource, hEventClient, hEvent) dispchnUnregisterEvent_DISPATCH(pNotifier, hNotifierClient, hNotifierResource, hEventClient, hEvent) +#define dispchnControlSerialization_Prologue(pResource, pCallContext, pParams) dispchnControlSerialization_Prologue_DISPATCH(pResource, pCallContext, pParams) #define dispchnCanCopy(pResource) dispchnCanCopy_DISPATCH(pResource) #define dispchnPreDestruct(pResource) dispchnPreDestruct_DISPATCH(pResource) #define dispchnIsDuplicate(pResource, hMemory, pDuplicate) dispchnIsDuplicate_DISPATCH(pResource, hMemory, pDuplicate) +#define dispchnControlSerialization_Epilogue(pResource, pCallContext, pParams) dispchnControlSerialization_Epilogue_DISPATCH(pResource, pCallContext, pParams) #define dispchnGetNotificationListPtr(pNotifier) dispchnGetNotificationListPtr_DISPATCH(pNotifier) #define dispchnGetNotificationShare(pNotifier) dispchnGetNotificationShare_DISPATCH(pNotifier) #define dispchnMap(pGpuResource, pCallContext, pParams, pCpuMapping) dispchnMap_DISPATCH(pGpuResource, pCallContext, pParams, pCpuMapping) @@ -193,16 +197,16 @@ return pGpuResource->__dispchnShareCallback__(pGpuResource, pInvokingClient, pParentRef, pSharePolicy); } -static inline NV_STATUS dispchnMapTo_DISPATCH(struct DispChannel *pResource, RS_RES_MAP_TO_PARAMS *pParams) { - return pResource->__dispchnMapTo__(pResource, pParams); +static inline NV_STATUS dispchnCheckMemInterUnmap_DISPATCH(struct DispChannel *pRmResource, NvBool bSubdeviceHandleProvided) { + return pRmResource->__dispchnCheckMemInterUnmap__(pRmResource, bSubdeviceHandleProvided); } static inline NV_STATUS dispchnGetOrAllocNotifShare_DISPATCH(struct DispChannel *pNotifier, NvHandle hNotifierClient, NvHandle hNotifierResource, struct NotifShare **ppNotifShare) { return pNotifier->__dispchnGetOrAllocNotifShare__(pNotifier, hNotifierClient, hNotifierResource, ppNotifShare); } -static inline NV_STATUS dispchnCheckMemInterUnmap_DISPATCH(struct DispChannel *pRmResource, NvBool bSubdeviceHandleProvided) { - return pRmResource->__dispchnCheckMemInterUnmap__(pRmResource, bSubdeviceHandleProvided); +static inline NV_STATUS dispchnMapTo_DISPATCH(struct DispChannel *pResource, RS_RES_MAP_TO_PARAMS *pParams) { + return pResource->__dispchnMapTo__(pResource, pParams); } static inline NV_STATUS dispchnGetMapAddrSpace_DISPATCH(struct DispChannel *pGpuResource, struct CALL_CONTEXT *pCallContext, NvU32 mapFlags, NV_ADDRESS_SPACE *pAddrSpace) { @@ -269,6 +273,10 @@ return pNotifier->__dispchnUnregisterEvent__(pNotifier, hNotifierClient, hNotifierResource, hEventClient, hEvent); } +static inline NV_STATUS dispchnControlSerialization_Prologue_DISPATCH(struct DispChannel *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return pResource->__dispchnControlSerialization_Prologue__(pResource, pCallContext, pParams); +} + static inline NvBool dispchnCanCopy_DISPATCH(struct DispChannel *pResource) { return pResource->__dispchnCanCopy__(pResource); } @@ -281,6 +289,10 @@ return pResource->__dispchnIsDuplicate__(pResource, hMemory, pDuplicate); } +static inline void dispchnControlSerialization_Epilogue_DISPATCH(struct DispChannel *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + pResource->__dispchnControlSerialization_Epilogue__(pResource, pCallContext, pParams); +} + static inline PEVENTNOTIFICATION *dispchnGetNotificationListPtr_DISPATCH(struct DispChannel *pNotifier) { return pNotifier->__dispchnGetNotificationListPtr__(pNotifier); } @@ -370,9 +382,9 @@ struct DispChannel *__nvoc_pbase_DispChannel; struct DispChannelPio *__nvoc_pbase_DispChannelPio; NvBool (*__dispchnpioShareCallback__)(struct DispChannelPio *, struct RsClient *, struct RsResourceRef *, RS_SHARE_POLICY *); - NV_STATUS (*__dispchnpioMapTo__)(struct DispChannelPio *, RS_RES_MAP_TO_PARAMS *); - NV_STATUS (*__dispchnpioGetOrAllocNotifShare__)(struct DispChannelPio *, NvHandle, NvHandle, struct NotifShare **); NV_STATUS (*__dispchnpioCheckMemInterUnmap__)(struct DispChannelPio *, NvBool); + NV_STATUS (*__dispchnpioGetOrAllocNotifShare__)(struct DispChannelPio *, NvHandle, NvHandle, struct NotifShare **); + NV_STATUS (*__dispchnpioMapTo__)(struct DispChannelPio *, RS_RES_MAP_TO_PARAMS *); NV_STATUS (*__dispchnpioGetMapAddrSpace__)(struct DispChannelPio *, struct CALL_CONTEXT *, NvU32, NV_ADDRESS_SPACE *); void (*__dispchnpioSetNotificationShare__)(struct DispChannelPio *, struct NotifShare *); NvU32 (*__dispchnpioGetRefCount__)(struct DispChannelPio *); @@ -390,9 +402,11 @@ NV_STATUS (*__dispchnpioGetMemoryMappingDescriptor__)(struct DispChannelPio *, struct MEMORY_DESCRIPTOR **); NV_STATUS (*__dispchnpioControlFilter__)(struct DispChannelPio *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); NV_STATUS (*__dispchnpioUnregisterEvent__)(struct DispChannelPio *, NvHandle, NvHandle, NvHandle, NvHandle); + NV_STATUS (*__dispchnpioControlSerialization_Prologue__)(struct DispChannelPio *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); NvBool (*__dispchnpioCanCopy__)(struct DispChannelPio *); void (*__dispchnpioPreDestruct__)(struct DispChannelPio *); NV_STATUS (*__dispchnpioIsDuplicate__)(struct DispChannelPio *, NvHandle, NvBool *); + void (*__dispchnpioControlSerialization_Epilogue__)(struct DispChannelPio *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); PEVENTNOTIFICATION *(*__dispchnpioGetNotificationListPtr__)(struct DispChannelPio *); struct NotifShare *(*__dispchnpioGetNotificationShare__)(struct DispChannelPio *); NV_STATUS (*__dispchnpioMap__)(struct DispChannelPio *, struct CALL_CONTEXT *, struct RS_CPU_MAP_PARAMS *, struct RsCpuMapping *); @@ -428,9 +442,9 @@ __nvoc_objCreate_DispChannelPio((ppNewObj), staticCast((pParent), Dynamic), (createFlags), arg_pCallContext, arg_pParams) #define dispchnpioShareCallback(pGpuResource, pInvokingClient, pParentRef, pSharePolicy) dispchnpioShareCallback_DISPATCH(pGpuResource, pInvokingClient, pParentRef, pSharePolicy) -#define dispchnpioMapTo(pResource, pParams) dispchnpioMapTo_DISPATCH(pResource, pParams) -#define dispchnpioGetOrAllocNotifShare(pNotifier, hNotifierClient, hNotifierResource, ppNotifShare) dispchnpioGetOrAllocNotifShare_DISPATCH(pNotifier, hNotifierClient, hNotifierResource, ppNotifShare) #define dispchnpioCheckMemInterUnmap(pRmResource, bSubdeviceHandleProvided) dispchnpioCheckMemInterUnmap_DISPATCH(pRmResource, bSubdeviceHandleProvided) +#define dispchnpioGetOrAllocNotifShare(pNotifier, hNotifierClient, hNotifierResource, ppNotifShare) dispchnpioGetOrAllocNotifShare_DISPATCH(pNotifier, hNotifierClient, hNotifierResource, ppNotifShare) +#define dispchnpioMapTo(pResource, pParams) dispchnpioMapTo_DISPATCH(pResource, pParams) #define dispchnpioGetMapAddrSpace(pGpuResource, pCallContext, mapFlags, pAddrSpace) dispchnpioGetMapAddrSpace_DISPATCH(pGpuResource, pCallContext, mapFlags, pAddrSpace) #define dispchnpioSetNotificationShare(pNotifier, pNotifShare) dispchnpioSetNotificationShare_DISPATCH(pNotifier, pNotifShare) #define dispchnpioGetRefCount(pResource) dispchnpioGetRefCount_DISPATCH(pResource) @@ -448,9 +462,11 @@ #define dispchnpioGetMemoryMappingDescriptor(pRmResource, ppMemDesc) dispchnpioGetMemoryMappingDescriptor_DISPATCH(pRmResource, ppMemDesc) #define dispchnpioControlFilter(pResource, pCallContext, pParams) dispchnpioControlFilter_DISPATCH(pResource, pCallContext, pParams) #define dispchnpioUnregisterEvent(pNotifier, hNotifierClient, hNotifierResource, hEventClient, hEvent) dispchnpioUnregisterEvent_DISPATCH(pNotifier, hNotifierClient, hNotifierResource, hEventClient, hEvent) +#define dispchnpioControlSerialization_Prologue(pResource, pCallContext, pParams) dispchnpioControlSerialization_Prologue_DISPATCH(pResource, pCallContext, pParams) #define dispchnpioCanCopy(pResource) dispchnpioCanCopy_DISPATCH(pResource) #define dispchnpioPreDestruct(pResource) dispchnpioPreDestruct_DISPATCH(pResource) #define dispchnpioIsDuplicate(pResource, hMemory, pDuplicate) dispchnpioIsDuplicate_DISPATCH(pResource, hMemory, pDuplicate) +#define dispchnpioControlSerialization_Epilogue(pResource, pCallContext, pParams) dispchnpioControlSerialization_Epilogue_DISPATCH(pResource, pCallContext, pParams) #define dispchnpioGetNotificationListPtr(pNotifier) dispchnpioGetNotificationListPtr_DISPATCH(pNotifier) #define dispchnpioGetNotificationShare(pNotifier) dispchnpioGetNotificationShare_DISPATCH(pNotifier) #define dispchnpioMap(pGpuResource, pCallContext, pParams, pCpuMapping) dispchnpioMap_DISPATCH(pGpuResource, pCallContext, pParams, pCpuMapping) @@ -459,16 +475,16 @@ return pGpuResource->__dispchnpioShareCallback__(pGpuResource, pInvokingClient, pParentRef, pSharePolicy); } -static inline NV_STATUS dispchnpioMapTo_DISPATCH(struct DispChannelPio *pResource, RS_RES_MAP_TO_PARAMS *pParams) { - return pResource->__dispchnpioMapTo__(pResource, pParams); +static inline NV_STATUS dispchnpioCheckMemInterUnmap_DISPATCH(struct DispChannelPio *pRmResource, NvBool bSubdeviceHandleProvided) { + return pRmResource->__dispchnpioCheckMemInterUnmap__(pRmResource, bSubdeviceHandleProvided); } static inline NV_STATUS dispchnpioGetOrAllocNotifShare_DISPATCH(struct DispChannelPio *pNotifier, NvHandle hNotifierClient, NvHandle hNotifierResource, struct NotifShare **ppNotifShare) { return pNotifier->__dispchnpioGetOrAllocNotifShare__(pNotifier, hNotifierClient, hNotifierResource, ppNotifShare); } -static inline NV_STATUS dispchnpioCheckMemInterUnmap_DISPATCH(struct DispChannelPio *pRmResource, NvBool bSubdeviceHandleProvided) { - return pRmResource->__dispchnpioCheckMemInterUnmap__(pRmResource, bSubdeviceHandleProvided); +static inline NV_STATUS dispchnpioMapTo_DISPATCH(struct DispChannelPio *pResource, RS_RES_MAP_TO_PARAMS *pParams) { + return pResource->__dispchnpioMapTo__(pResource, pParams); } static inline NV_STATUS dispchnpioGetMapAddrSpace_DISPATCH(struct DispChannelPio *pGpuResource, struct CALL_CONTEXT *pCallContext, NvU32 mapFlags, NV_ADDRESS_SPACE *pAddrSpace) { @@ -539,6 +555,10 @@ return pNotifier->__dispchnpioUnregisterEvent__(pNotifier, hNotifierClient, hNotifierResource, hEventClient, hEvent); } +static inline NV_STATUS dispchnpioControlSerialization_Prologue_DISPATCH(struct DispChannelPio *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return pResource->__dispchnpioControlSerialization_Prologue__(pResource, pCallContext, pParams); +} + static inline NvBool dispchnpioCanCopy_DISPATCH(struct DispChannelPio *pResource) { return pResource->__dispchnpioCanCopy__(pResource); } @@ -551,6 +571,10 @@ return pResource->__dispchnpioIsDuplicate__(pResource, hMemory, pDuplicate); } +static inline void dispchnpioControlSerialization_Epilogue_DISPATCH(struct DispChannelPio *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + pResource->__dispchnpioControlSerialization_Epilogue__(pResource, pCallContext, pParams); +} + static inline PEVENTNOTIFICATION *dispchnpioGetNotificationListPtr_DISPATCH(struct DispChannelPio *pNotifier) { return pNotifier->__dispchnpioGetNotificationListPtr__(pNotifier); } @@ -594,9 +618,9 @@ struct DispChannel *__nvoc_pbase_DispChannel; struct DispChannelDma *__nvoc_pbase_DispChannelDma; NvBool (*__dispchndmaShareCallback__)(struct DispChannelDma *, struct RsClient *, struct RsResourceRef *, RS_SHARE_POLICY *); - NV_STATUS (*__dispchndmaMapTo__)(struct DispChannelDma *, RS_RES_MAP_TO_PARAMS *); - NV_STATUS (*__dispchndmaGetOrAllocNotifShare__)(struct DispChannelDma *, NvHandle, NvHandle, struct NotifShare **); NV_STATUS (*__dispchndmaCheckMemInterUnmap__)(struct DispChannelDma *, NvBool); + NV_STATUS (*__dispchndmaGetOrAllocNotifShare__)(struct DispChannelDma *, NvHandle, NvHandle, struct NotifShare **); + NV_STATUS (*__dispchndmaMapTo__)(struct DispChannelDma *, RS_RES_MAP_TO_PARAMS *); NV_STATUS (*__dispchndmaGetMapAddrSpace__)(struct DispChannelDma *, struct CALL_CONTEXT *, NvU32, NV_ADDRESS_SPACE *); void (*__dispchndmaSetNotificationShare__)(struct DispChannelDma *, struct NotifShare *); NvU32 (*__dispchndmaGetRefCount__)(struct DispChannelDma *); @@ -614,9 +638,11 @@ NV_STATUS (*__dispchndmaGetMemoryMappingDescriptor__)(struct DispChannelDma *, struct MEMORY_DESCRIPTOR **); NV_STATUS (*__dispchndmaControlFilter__)(struct DispChannelDma *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); NV_STATUS (*__dispchndmaUnregisterEvent__)(struct DispChannelDma *, NvHandle, NvHandle, NvHandle, NvHandle); + NV_STATUS (*__dispchndmaControlSerialization_Prologue__)(struct DispChannelDma *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); NvBool (*__dispchndmaCanCopy__)(struct DispChannelDma *); void (*__dispchndmaPreDestruct__)(struct DispChannelDma *); NV_STATUS (*__dispchndmaIsDuplicate__)(struct DispChannelDma *, NvHandle, NvBool *); + void (*__dispchndmaControlSerialization_Epilogue__)(struct DispChannelDma *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); PEVENTNOTIFICATION *(*__dispchndmaGetNotificationListPtr__)(struct DispChannelDma *); struct NotifShare *(*__dispchndmaGetNotificationShare__)(struct DispChannelDma *); NV_STATUS (*__dispchndmaMap__)(struct DispChannelDma *, struct CALL_CONTEXT *, struct RS_CPU_MAP_PARAMS *, struct RsCpuMapping *); @@ -652,9 +678,9 @@ __nvoc_objCreate_DispChannelDma((ppNewObj), staticCast((pParent), Dynamic), (createFlags), arg_pCallContext, arg_pParams) #define dispchndmaShareCallback(pGpuResource, pInvokingClient, pParentRef, pSharePolicy) dispchndmaShareCallback_DISPATCH(pGpuResource, pInvokingClient, pParentRef, pSharePolicy) -#define dispchndmaMapTo(pResource, pParams) dispchndmaMapTo_DISPATCH(pResource, pParams) -#define dispchndmaGetOrAllocNotifShare(pNotifier, hNotifierClient, hNotifierResource, ppNotifShare) dispchndmaGetOrAllocNotifShare_DISPATCH(pNotifier, hNotifierClient, hNotifierResource, ppNotifShare) #define dispchndmaCheckMemInterUnmap(pRmResource, bSubdeviceHandleProvided) dispchndmaCheckMemInterUnmap_DISPATCH(pRmResource, bSubdeviceHandleProvided) +#define dispchndmaGetOrAllocNotifShare(pNotifier, hNotifierClient, hNotifierResource, ppNotifShare) dispchndmaGetOrAllocNotifShare_DISPATCH(pNotifier, hNotifierClient, hNotifierResource, ppNotifShare) +#define dispchndmaMapTo(pResource, pParams) dispchndmaMapTo_DISPATCH(pResource, pParams) #define dispchndmaGetMapAddrSpace(pGpuResource, pCallContext, mapFlags, pAddrSpace) dispchndmaGetMapAddrSpace_DISPATCH(pGpuResource, pCallContext, mapFlags, pAddrSpace) #define dispchndmaSetNotificationShare(pNotifier, pNotifShare) dispchndmaSetNotificationShare_DISPATCH(pNotifier, pNotifShare) #define dispchndmaGetRefCount(pResource) dispchndmaGetRefCount_DISPATCH(pResource) @@ -672,9 +698,11 @@ #define dispchndmaGetMemoryMappingDescriptor(pRmResource, ppMemDesc) dispchndmaGetMemoryMappingDescriptor_DISPATCH(pRmResource, ppMemDesc) #define dispchndmaControlFilter(pResource, pCallContext, pParams) dispchndmaControlFilter_DISPATCH(pResource, pCallContext, pParams) #define dispchndmaUnregisterEvent(pNotifier, hNotifierClient, hNotifierResource, hEventClient, hEvent) dispchndmaUnregisterEvent_DISPATCH(pNotifier, hNotifierClient, hNotifierResource, hEventClient, hEvent) +#define dispchndmaControlSerialization_Prologue(pResource, pCallContext, pParams) dispchndmaControlSerialization_Prologue_DISPATCH(pResource, pCallContext, pParams) #define dispchndmaCanCopy(pResource) dispchndmaCanCopy_DISPATCH(pResource) #define dispchndmaPreDestruct(pResource) dispchndmaPreDestruct_DISPATCH(pResource) #define dispchndmaIsDuplicate(pResource, hMemory, pDuplicate) dispchndmaIsDuplicate_DISPATCH(pResource, hMemory, pDuplicate) +#define dispchndmaControlSerialization_Epilogue(pResource, pCallContext, pParams) dispchndmaControlSerialization_Epilogue_DISPATCH(pResource, pCallContext, pParams) #define dispchndmaGetNotificationListPtr(pNotifier) dispchndmaGetNotificationListPtr_DISPATCH(pNotifier) #define dispchndmaGetNotificationShare(pNotifier) dispchndmaGetNotificationShare_DISPATCH(pNotifier) #define dispchndmaMap(pGpuResource, pCallContext, pParams, pCpuMapping) dispchndmaMap_DISPATCH(pGpuResource, pCallContext, pParams, pCpuMapping) @@ -683,16 +711,16 @@ return pGpuResource->__dispchndmaShareCallback__(pGpuResource, pInvokingClient, pParentRef, pSharePolicy); } -static inline NV_STATUS dispchndmaMapTo_DISPATCH(struct DispChannelDma *pResource, RS_RES_MAP_TO_PARAMS *pParams) { - return pResource->__dispchndmaMapTo__(pResource, pParams); +static inline NV_STATUS dispchndmaCheckMemInterUnmap_DISPATCH(struct DispChannelDma *pRmResource, NvBool bSubdeviceHandleProvided) { + return pRmResource->__dispchndmaCheckMemInterUnmap__(pRmResource, bSubdeviceHandleProvided); } static inline NV_STATUS dispchndmaGetOrAllocNotifShare_DISPATCH(struct DispChannelDma *pNotifier, NvHandle hNotifierClient, NvHandle hNotifierResource, struct NotifShare **ppNotifShare) { return pNotifier->__dispchndmaGetOrAllocNotifShare__(pNotifier, hNotifierClient, hNotifierResource, ppNotifShare); } -static inline NV_STATUS dispchndmaCheckMemInterUnmap_DISPATCH(struct DispChannelDma *pRmResource, NvBool bSubdeviceHandleProvided) { - return pRmResource->__dispchndmaCheckMemInterUnmap__(pRmResource, bSubdeviceHandleProvided); +static inline NV_STATUS dispchndmaMapTo_DISPATCH(struct DispChannelDma *pResource, RS_RES_MAP_TO_PARAMS *pParams) { + return pResource->__dispchndmaMapTo__(pResource, pParams); } static inline NV_STATUS dispchndmaGetMapAddrSpace_DISPATCH(struct DispChannelDma *pGpuResource, struct CALL_CONTEXT *pCallContext, NvU32 mapFlags, NV_ADDRESS_SPACE *pAddrSpace) { @@ -763,6 +791,10 @@ return pNotifier->__dispchndmaUnregisterEvent__(pNotifier, hNotifierClient, hNotifierResource, hEventClient, hEvent); } +static inline NV_STATUS dispchndmaControlSerialization_Prologue_DISPATCH(struct DispChannelDma *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return pResource->__dispchndmaControlSerialization_Prologue__(pResource, pCallContext, pParams); +} + static inline NvBool dispchndmaCanCopy_DISPATCH(struct DispChannelDma *pResource) { return pResource->__dispchndmaCanCopy__(pResource); } @@ -775,6 +807,10 @@ return pResource->__dispchndmaIsDuplicate__(pResource, hMemory, pDuplicate); } +static inline void dispchndmaControlSerialization_Epilogue_DISPATCH(struct DispChannelDma *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + pResource->__dispchndmaControlSerialization_Epilogue__(pResource, pCallContext, pParams); +} + static inline PEVENTNOTIFICATION *dispchndmaGetNotificationListPtr_DISPATCH(struct DispChannelDma *pNotifier) { return pNotifier->__dispchndmaGetNotificationListPtr__(pNotifier); } diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/generated/g_disp_inst_mem_nvoc.c nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_disp_inst_mem_nvoc.c --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/generated/g_disp_inst_mem_nvoc.c 2023-10-25 20:26:54.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_disp_inst_mem_nvoc.c 2024-03-05 22:18:11.000000000 +0000 @@ -107,73 +107,73 @@ PORT_UNREFERENCED_VARIABLE(dispIpHal_HalVarIdx); // Hal function -- instmemGetSize - if (( ((dispIpHal_HalVarIdx >> 5) == 0UL) && ((1UL << (dispIpHal_HalVarIdx & 0x1f)) & 0x00004c00UL) )) /* DispIpHal: DISPv0400 | DISPv0401 | DISPv0404 */ + if (( ((dispIpHal_HalVarIdx >> 5) == 0UL) && ((1UL << (dispIpHal_HalVarIdx & 0x1f)) & 0x00020000UL) )) /* DispIpHal: DISPv0000 */ { - pThis->__instmemGetSize__ = &instmemGetSize_v03_00; + pThis->__instmemGetSize__ = &instmemGetSize_f2d351; } - else if (( ((dispIpHal_HalVarIdx >> 5) == 0UL) && ((1UL << (dispIpHal_HalVarIdx & 0x1f)) & 0x00008000UL) )) /* DispIpHal: DISPv0000 */ + else { - pThis->__instmemGetSize__ = &instmemGetSize_f2d351; + pThis->__instmemGetSize__ = &instmemGetSize_v03_00; } // Hal function -- instmemGetHashTableBaseAddr - if (( ((dispIpHal_HalVarIdx >> 5) == 0UL) && ((1UL << (dispIpHal_HalVarIdx & 0x1f)) & 0x00004c00UL) )) /* DispIpHal: DISPv0400 | DISPv0401 | DISPv0404 */ + if (( ((dispIpHal_HalVarIdx >> 5) == 0UL) && ((1UL << (dispIpHal_HalVarIdx & 0x1f)) & 0x00020000UL) )) /* DispIpHal: DISPv0000 */ { - pThis->__instmemGetHashTableBaseAddr__ = &instmemGetHashTableBaseAddr_v03_00; + pThis->__instmemGetHashTableBaseAddr__ = &instmemGetHashTableBaseAddr_4a4dee; } - else if (( ((dispIpHal_HalVarIdx >> 5) == 0UL) && ((1UL << (dispIpHal_HalVarIdx & 0x1f)) & 0x00008000UL) )) /* DispIpHal: DISPv0000 */ + else { - pThis->__instmemGetHashTableBaseAddr__ = &instmemGetHashTableBaseAddr_4a4dee; + pThis->__instmemGetHashTableBaseAddr__ = &instmemGetHashTableBaseAddr_v03_00; } // Hal function -- instmemIsValid - if (( ((dispIpHal_HalVarIdx >> 5) == 0UL) && ((1UL << (dispIpHal_HalVarIdx & 0x1f)) & 0x00004c00UL) )) /* DispIpHal: DISPv0400 | DISPv0401 | DISPv0404 */ + if (( ((dispIpHal_HalVarIdx >> 5) == 0UL) && ((1UL << (dispIpHal_HalVarIdx & 0x1f)) & 0x00020000UL) )) /* DispIpHal: DISPv0000 */ { - pThis->__instmemIsValid__ = &instmemIsValid_v03_00; + pThis->__instmemIsValid__ = &instmemIsValid_491d52; } - else if (( ((dispIpHal_HalVarIdx >> 5) == 0UL) && ((1UL << (dispIpHal_HalVarIdx & 0x1f)) & 0x00008000UL) )) /* DispIpHal: DISPv0000 */ + else { - pThis->__instmemIsValid__ = &instmemIsValid_491d52; + pThis->__instmemIsValid__ = &instmemIsValid_v03_00; } // Hal function -- instmemGenerateHashTableData - if (( ((dispIpHal_HalVarIdx >> 5) == 0UL) && ((1UL << (dispIpHal_HalVarIdx & 0x1f)) & 0x00004c00UL) )) /* DispIpHal: DISPv0400 | DISPv0401 | DISPv0404 */ + if (( ((dispIpHal_HalVarIdx >> 5) == 0UL) && ((1UL << (dispIpHal_HalVarIdx & 0x1f)) & 0x00020000UL) )) /* DispIpHal: DISPv0000 */ { - pThis->__instmemGenerateHashTableData__ = &instmemGenerateHashTableData_v03_00; + pThis->__instmemGenerateHashTableData__ = &instmemGenerateHashTableData_4a4dee; } - else if (( ((dispIpHal_HalVarIdx >> 5) == 0UL) && ((1UL << (dispIpHal_HalVarIdx & 0x1f)) & 0x00008000UL) )) /* DispIpHal: DISPv0000 */ + else { - pThis->__instmemGenerateHashTableData__ = &instmemGenerateHashTableData_4a4dee; + pThis->__instmemGenerateHashTableData__ = &instmemGenerateHashTableData_v03_00; } // Hal function -- instmemHashFunc - if (( ((dispIpHal_HalVarIdx >> 5) == 0UL) && ((1UL << (dispIpHal_HalVarIdx & 0x1f)) & 0x00004c00UL) )) /* DispIpHal: DISPv0400 | DISPv0401 | DISPv0404 */ + if (( ((dispIpHal_HalVarIdx >> 5) == 0UL) && ((1UL << (dispIpHal_HalVarIdx & 0x1f)) & 0x00020000UL) )) /* DispIpHal: DISPv0000 */ { - pThis->__instmemHashFunc__ = &instmemHashFunc_v03_00; + pThis->__instmemHashFunc__ = &instmemHashFunc_46f6a7; } - else if (( ((dispIpHal_HalVarIdx >> 5) == 0UL) && ((1UL << (dispIpHal_HalVarIdx & 0x1f)) & 0x00008000UL) )) /* DispIpHal: DISPv0000 */ + else { - pThis->__instmemHashFunc__ = &instmemHashFunc_46f6a7; + pThis->__instmemHashFunc__ = &instmemHashFunc_v03_00; } // Hal function -- instmemCommitContextDma - if (( ((dispIpHal_HalVarIdx >> 5) == 0UL) && ((1UL << (dispIpHal_HalVarIdx & 0x1f)) & 0x00004c00UL) )) /* DispIpHal: DISPv0400 | DISPv0401 | DISPv0404 */ + if (( ((dispIpHal_HalVarIdx >> 5) == 0UL) && ((1UL << (dispIpHal_HalVarIdx & 0x1f)) & 0x00020000UL) )) /* DispIpHal: DISPv0000 */ { - pThis->__instmemCommitContextDma__ = &instmemCommitContextDma_v03_00; + pThis->__instmemCommitContextDma__ = &instmemCommitContextDma_46f6a7; } - else if (( ((dispIpHal_HalVarIdx >> 5) == 0UL) && ((1UL << (dispIpHal_HalVarIdx & 0x1f)) & 0x00008000UL) )) /* DispIpHal: DISPv0000 */ + else { - pThis->__instmemCommitContextDma__ = &instmemCommitContextDma_46f6a7; + pThis->__instmemCommitContextDma__ = &instmemCommitContextDma_v03_00; } // Hal function -- instmemUpdateContextDma - if (( ((dispIpHal_HalVarIdx >> 5) == 0UL) && ((1UL << (dispIpHal_HalVarIdx & 0x1f)) & 0x00004c00UL) )) /* DispIpHal: DISPv0400 | DISPv0401 | DISPv0404 */ + if (( ((dispIpHal_HalVarIdx >> 5) == 0UL) && ((1UL << (dispIpHal_HalVarIdx & 0x1f)) & 0x00020000UL) )) /* DispIpHal: DISPv0000 */ { - pThis->__instmemUpdateContextDma__ = &instmemUpdateContextDma_v03_00; + pThis->__instmemUpdateContextDma__ = &instmemUpdateContextDma_46f6a7; } - else if (( ((dispIpHal_HalVarIdx >> 5) == 0UL) && ((1UL << (dispIpHal_HalVarIdx & 0x1f)) & 0x00008000UL) )) /* DispIpHal: DISPv0000 */ + else { - pThis->__instmemUpdateContextDma__ = &instmemUpdateContextDma_46f6a7; + pThis->__instmemUpdateContextDma__ = &instmemUpdateContextDma_v03_00; } } @@ -195,13 +195,16 @@ DisplayInstanceMemory *pThis; RmHalspecOwner *pRmhalspecowner; - pThis = portMemAllocNonPaged(sizeof(DisplayInstanceMemory)); - if (pThis == NULL) return NV_ERR_NO_MEMORY; + status = __nvoc_handleObjCreateMemAlloc(createFlags, sizeof(DisplayInstanceMemory), (void**)&pThis, (void**)ppThis); + if (status != NV_OK) + return status; portMemSet(pThis, 0, sizeof(DisplayInstanceMemory)); __nvoc_initRtti(staticCast(pThis, Dynamic), &__nvoc_class_def_DisplayInstanceMemory); + pThis->__nvoc_base_Object.createFlags = createFlags; + if (pParent != NULL && !(createFlags & NVOC_OBJ_CREATE_FLAGS_PARENT_HALSPEC_ONLY)) { pParentObj = dynamicCast(pParent, Object); @@ -221,11 +224,17 @@ if (status != NV_OK) goto __nvoc_objCreate_DisplayInstanceMemory_cleanup; *ppThis = pThis; + return NV_OK; __nvoc_objCreate_DisplayInstanceMemory_cleanup: // do not call destructors here since the constructor already called them - portMemFree(pThis); + if (createFlags & NVOC_OBJ_CREATE_FLAGS_IN_PLACE_CONSTRUCT) + portMemSet(pThis, 0, sizeof(DisplayInstanceMemory)); + else + portMemFree(pThis); + + // coverity[leaked_storage:FALSE] return status; } diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/generated/g_disp_objs_nvoc.c nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_disp_objs_nvoc.c --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/generated/g_disp_objs_nvoc.c 2023-10-25 20:26:55.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_disp_objs_nvoc.c 2024-03-05 22:18:11.000000000 +0000 @@ -122,10 +122,38 @@ return rmresCheckMemInterUnmap((struct RmResource *)(((unsigned char *)pRmResource) + __nvoc_rtti_DisplayApi_RmResource.offset), bSubdeviceHandleProvided); } +static NV_STATUS __nvoc_thunk_RsResource_dispapiMapTo(struct DisplayApi *pResource, RS_RES_MAP_TO_PARAMS *pParams) { + return resMapTo((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_DisplayApi_RsResource.offset), pParams); +} + static NvBool __nvoc_thunk_RmResource_dispapiAccessCallback(struct DisplayApi *pResource, struct RsClient *pInvokingClient, void *pAllocParams, RsAccessRight accessRight) { return rmresAccessCallback((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_DisplayApi_RmResource.offset), pInvokingClient, pAllocParams, accessRight); } +static void __nvoc_thunk_Notifier_dispapiSetNotificationShare(struct DisplayApi *pNotifier, struct NotifShare *pNotifShare) { + notifySetNotificationShare((struct Notifier *)(((unsigned char *)pNotifier) + __nvoc_rtti_DisplayApi_Notifier.offset), pNotifShare); +} + +static NvU32 __nvoc_thunk_RsResource_dispapiGetRefCount(struct DisplayApi *pResource) { + return resGetRefCount((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_DisplayApi_RsResource.offset)); +} + +static void __nvoc_thunk_RsResource_dispapiAddAdditionalDependants(struct RsClient *pClient, struct DisplayApi *pResource, RsResourceRef *pReference) { + resAddAdditionalDependants(pClient, (struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_DisplayApi_RsResource.offset), pReference); +} + +static NV_STATUS __nvoc_thunk_RsResource_dispapiUnmapFrom(struct DisplayApi *pResource, RS_RES_UNMAP_FROM_PARAMS *pParams) { + return resUnmapFrom((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_DisplayApi_RsResource.offset), pParams); +} + +static NV_STATUS __nvoc_thunk_RsResource_dispapiControlLookup(struct DisplayApi *pResource, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams, const struct NVOC_EXPORTED_METHOD_DEF **ppEntry) { + return resControlLookup((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_DisplayApi_RsResource.offset), pParams, ppEntry); +} + +static NV_STATUS __nvoc_thunk_RsResource_dispapiUnmap(struct DisplayApi *pResource, struct CALL_CONTEXT *pCallContext, RsCpuMapping *pCpuMapping) { + return resUnmap((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_DisplayApi_RsResource.offset), pCallContext, pCpuMapping); +} + static NV_STATUS __nvoc_thunk_RmResource_dispapiGetMemInterMapParams(struct DisplayApi *pRmResource, RMRES_MEM_INTER_MAP_PARAMS *pParams) { return rmresGetMemInterMapParams((struct RmResource *)(((unsigned char *)pRmResource) + __nvoc_rtti_DisplayApi_RmResource.offset), pParams); } @@ -134,50 +162,34 @@ return rmresGetMemoryMappingDescriptor((struct RmResource *)(((unsigned char *)pRmResource) + __nvoc_rtti_DisplayApi_RmResource.offset), ppMemDesc); } -static void __nvoc_thunk_Notifier_dispapiSetNotificationShare(struct DisplayApi *pNotifier, struct NotifShare *pNotifShare) { - notifySetNotificationShare((struct Notifier *)(((unsigned char *)pNotifier) + __nvoc_rtti_DisplayApi_Notifier.offset), pNotifShare); -} - static NV_STATUS __nvoc_thunk_RsResource_dispapiControlFilter(struct DisplayApi *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { return resControlFilter((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_DisplayApi_RsResource.offset), pCallContext, pParams); } -static NvU32 __nvoc_thunk_RsResource_dispapiGetRefCount(struct DisplayApi *pResource) { - return resGetRefCount((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_DisplayApi_RsResource.offset)); -} - static NV_STATUS __nvoc_thunk_Notifier_dispapiUnregisterEvent(struct DisplayApi *pNotifier, NvHandle hNotifierClient, NvHandle hNotifierResource, NvHandle hEventClient, NvHandle hEvent) { return notifyUnregisterEvent((struct Notifier *)(((unsigned char *)pNotifier) + __nvoc_rtti_DisplayApi_Notifier.offset), hNotifierClient, hNotifierResource, hEventClient, hEvent); } -static NV_STATUS __nvoc_thunk_RsResource_dispapiUnmap(struct DisplayApi *pResource, struct CALL_CONTEXT *pCallContext, RsCpuMapping *pCpuMapping) { - return resUnmap((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_DisplayApi_RsResource.offset), pCallContext, pCpuMapping); +static NV_STATUS __nvoc_thunk_RmResource_dispapiControlSerialization_Prologue(struct DisplayApi *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return rmresControlSerialization_Prologue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_DisplayApi_RmResource.offset), pCallContext, pParams); } static NvBool __nvoc_thunk_RsResource_dispapiCanCopy(struct DisplayApi *pResource) { return resCanCopy((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_DisplayApi_RsResource.offset)); } -static NV_STATUS __nvoc_thunk_RsResource_dispapiMapTo(struct DisplayApi *pResource, RS_RES_MAP_TO_PARAMS *pParams) { - return resMapTo((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_DisplayApi_RsResource.offset), pParams); -} - -static void __nvoc_thunk_RsResource_dispapiAddAdditionalDependants(struct RsClient *pClient, struct DisplayApi *pResource, RsResourceRef *pReference) { - resAddAdditionalDependants(pClient, (struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_DisplayApi_RsResource.offset), pReference); -} - static void __nvoc_thunk_RsResource_dispapiPreDestruct(struct DisplayApi *pResource) { resPreDestruct((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_DisplayApi_RsResource.offset)); } -static NV_STATUS __nvoc_thunk_RsResource_dispapiUnmapFrom(struct DisplayApi *pResource, RS_RES_UNMAP_FROM_PARAMS *pParams) { - return resUnmapFrom((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_DisplayApi_RsResource.offset), pParams); -} - static NV_STATUS __nvoc_thunk_RsResource_dispapiIsDuplicate(struct DisplayApi *pResource, NvHandle hMemory, NvBool *pDuplicate) { return resIsDuplicate((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_DisplayApi_RsResource.offset), hMemory, pDuplicate); } +static void __nvoc_thunk_RmResource_dispapiControlSerialization_Epilogue(struct DisplayApi *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + rmresControlSerialization_Epilogue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_DisplayApi_RmResource.offset), pCallContext, pParams); +} + static PEVENTNOTIFICATION *__nvoc_thunk_Notifier_dispapiGetNotificationListPtr(struct DisplayApi *pNotifier) { return notifyGetNotificationListPtr((struct Notifier *)(((unsigned char *)pNotifier) + __nvoc_rtti_DisplayApi_Notifier.offset)); } @@ -186,10 +198,6 @@ return notifyGetNotificationShare((struct Notifier *)(((unsigned char *)pNotifier) + __nvoc_rtti_DisplayApi_Notifier.offset)); } -static NV_STATUS __nvoc_thunk_RsResource_dispapiControlLookup(struct DisplayApi *pResource, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams, const struct NVOC_EXPORTED_METHOD_DEF **ppEntry) { - return resControlLookup((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_DisplayApi_RsResource.offset), pParams, ppEntry); -} - static NV_STATUS __nvoc_thunk_RsResource_dispapiMap(struct DisplayApi *pResource, struct CALL_CONTEXT *pCallContext, RS_CPU_MAP_PARAMS *pParams, RsCpuMapping *pCpuMapping) { return resMap((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_DisplayApi_RsResource.offset), pCallContext, pParams, pCpuMapping); } @@ -270,40 +278,44 @@ pThis->__dispapiCheckMemInterUnmap__ = &__nvoc_thunk_RmResource_dispapiCheckMemInterUnmap; + pThis->__dispapiMapTo__ = &__nvoc_thunk_RsResource_dispapiMapTo; + pThis->__dispapiAccessCallback__ = &__nvoc_thunk_RmResource_dispapiAccessCallback; + pThis->__dispapiSetNotificationShare__ = &__nvoc_thunk_Notifier_dispapiSetNotificationShare; + + pThis->__dispapiGetRefCount__ = &__nvoc_thunk_RsResource_dispapiGetRefCount; + + pThis->__dispapiAddAdditionalDependants__ = &__nvoc_thunk_RsResource_dispapiAddAdditionalDependants; + + pThis->__dispapiUnmapFrom__ = &__nvoc_thunk_RsResource_dispapiUnmapFrom; + + pThis->__dispapiControlLookup__ = &__nvoc_thunk_RsResource_dispapiControlLookup; + + pThis->__dispapiUnmap__ = &__nvoc_thunk_RsResource_dispapiUnmap; + pThis->__dispapiGetMemInterMapParams__ = &__nvoc_thunk_RmResource_dispapiGetMemInterMapParams; pThis->__dispapiGetMemoryMappingDescriptor__ = &__nvoc_thunk_RmResource_dispapiGetMemoryMappingDescriptor; - pThis->__dispapiSetNotificationShare__ = &__nvoc_thunk_Notifier_dispapiSetNotificationShare; - pThis->__dispapiControlFilter__ = &__nvoc_thunk_RsResource_dispapiControlFilter; - pThis->__dispapiGetRefCount__ = &__nvoc_thunk_RsResource_dispapiGetRefCount; - pThis->__dispapiUnregisterEvent__ = &__nvoc_thunk_Notifier_dispapiUnregisterEvent; - pThis->__dispapiUnmap__ = &__nvoc_thunk_RsResource_dispapiUnmap; + pThis->__dispapiControlSerialization_Prologue__ = &__nvoc_thunk_RmResource_dispapiControlSerialization_Prologue; pThis->__dispapiCanCopy__ = &__nvoc_thunk_RsResource_dispapiCanCopy; - pThis->__dispapiMapTo__ = &__nvoc_thunk_RsResource_dispapiMapTo; - - pThis->__dispapiAddAdditionalDependants__ = &__nvoc_thunk_RsResource_dispapiAddAdditionalDependants; - pThis->__dispapiPreDestruct__ = &__nvoc_thunk_RsResource_dispapiPreDestruct; - pThis->__dispapiUnmapFrom__ = &__nvoc_thunk_RsResource_dispapiUnmapFrom; - pThis->__dispapiIsDuplicate__ = &__nvoc_thunk_RsResource_dispapiIsDuplicate; + pThis->__dispapiControlSerialization_Epilogue__ = &__nvoc_thunk_RmResource_dispapiControlSerialization_Epilogue; + pThis->__dispapiGetNotificationListPtr__ = &__nvoc_thunk_Notifier_dispapiGetNotificationListPtr; pThis->__dispapiGetNotificationShare__ = &__nvoc_thunk_Notifier_dispapiGetNotificationShare; - pThis->__dispapiControlLookup__ = &__nvoc_thunk_RsResource_dispapiControlLookup; - pThis->__dispapiMap__ = &__nvoc_thunk_RsResource_dispapiMap; pThis->__dispapiGetOrAllocNotifShare__ = &__nvoc_thunk_Notifier_dispapiGetOrAllocNotifShare; @@ -334,13 +346,16 @@ DisplayApi *pThis; RmHalspecOwner *pRmhalspecowner; - pThis = portMemAllocNonPaged(sizeof(DisplayApi)); - if (pThis == NULL) return NV_ERR_NO_MEMORY; + status = __nvoc_handleObjCreateMemAlloc(createFlags, sizeof(DisplayApi), (void**)&pThis, (void**)ppThis); + if (status != NV_OK) + return status; portMemSet(pThis, 0, sizeof(DisplayApi)); __nvoc_initRtti(staticCast(pThis, Dynamic), &__nvoc_class_def_DisplayApi); + pThis->__nvoc_base_RmResource.__nvoc_base_RsResource.__nvoc_base_Object.createFlags = createFlags; + if (pParent != NULL && !(createFlags & NVOC_OBJ_CREATE_FLAGS_PARENT_HALSPEC_ONLY)) { pParentObj = dynamicCast(pParent, Object); @@ -360,11 +375,17 @@ if (status != NV_OK) goto __nvoc_objCreate_DisplayApi_cleanup; *ppThis = pThis; + return NV_OK; __nvoc_objCreate_DisplayApi_cleanup: // do not call destructors here since the constructor already called them - portMemFree(pThis); + if (createFlags & NVOC_OBJ_CREATE_FLAGS_IN_PLACE_CONSTRUCT) + portMemSet(pThis, 0, sizeof(DisplayApi)); + else + portMemFree(pThis); + + // coverity[leaked_storage:FALSE] return status; } @@ -486,90 +507,98 @@ return rmresShareCallback((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_DispObject_RmResource.offset), pInvokingClient, pParentRef, pSharePolicy); } -static NV_STATUS __nvoc_thunk_DisplayApi_dispobjControl(struct DispObject *pDisplayApi, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { - return dispapiControl((struct DisplayApi *)(((unsigned char *)pDisplayApi) + __nvoc_rtti_DispObject_DisplayApi.offset), pCallContext, pParams); +static NV_STATUS __nvoc_thunk_RmResource_dispobjCheckMemInterUnmap(struct DispObject *pRmResource, NvBool bSubdeviceHandleProvided) { + return rmresCheckMemInterUnmap((struct RmResource *)(((unsigned char *)pRmResource) + __nvoc_rtti_DispObject_RmResource.offset), bSubdeviceHandleProvided); +} + +static NV_STATUS __nvoc_thunk_RsResource_dispobjMapTo(struct DispObject *pResource, RS_RES_MAP_TO_PARAMS *pParams) { + return resMapTo((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_DispObject_RsResource.offset), pParams); } static NvBool __nvoc_thunk_RmResource_dispobjAccessCallback(struct DispObject *pResource, struct RsClient *pInvokingClient, void *pAllocParams, RsAccessRight accessRight) { return rmresAccessCallback((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_DispObject_RmResource.offset), pInvokingClient, pAllocParams, accessRight); } -static NV_STATUS __nvoc_thunk_RmResource_dispobjGetMemInterMapParams(struct DispObject *pRmResource, RMRES_MEM_INTER_MAP_PARAMS *pParams) { - return rmresGetMemInterMapParams((struct RmResource *)(((unsigned char *)pRmResource) + __nvoc_rtti_DispObject_RmResource.offset), pParams); +static void __nvoc_thunk_Notifier_dispobjSetNotificationShare(struct DispObject *pNotifier, struct NotifShare *pNotifShare) { + notifySetNotificationShare((struct Notifier *)(((unsigned char *)pNotifier) + __nvoc_rtti_DispObject_Notifier.offset), pNotifShare); } -static NV_STATUS __nvoc_thunk_RmResource_dispobjGetMemoryMappingDescriptor(struct DispObject *pRmResource, struct MEMORY_DESCRIPTOR **ppMemDesc) { - return rmresGetMemoryMappingDescriptor((struct RmResource *)(((unsigned char *)pRmResource) + __nvoc_rtti_DispObject_RmResource.offset), ppMemDesc); +static NvU32 __nvoc_thunk_RsResource_dispobjGetRefCount(struct DispObject *pResource) { + return resGetRefCount((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_DispObject_RsResource.offset)); } -static NV_STATUS __nvoc_thunk_RmResource_dispobjCheckMemInterUnmap(struct DispObject *pRmResource, NvBool bSubdeviceHandleProvided) { - return rmresCheckMemInterUnmap((struct RmResource *)(((unsigned char *)pRmResource) + __nvoc_rtti_DispObject_RmResource.offset), bSubdeviceHandleProvided); +static void __nvoc_thunk_RsResource_dispobjAddAdditionalDependants(struct RsClient *pClient, struct DispObject *pResource, RsResourceRef *pReference) { + resAddAdditionalDependants(pClient, (struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_DispObject_RsResource.offset), pReference); } -static void __nvoc_thunk_Notifier_dispobjSetNotificationShare(struct DispObject *pNotifier, struct NotifShare *pNotifShare) { - notifySetNotificationShare((struct Notifier *)(((unsigned char *)pNotifier) + __nvoc_rtti_DispObject_Notifier.offset), pNotifShare); +static NV_STATUS __nvoc_thunk_DisplayApi_dispobjControl_Prologue(struct DispObject *pDisplayApi, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pRsParams) { + return dispapiControl_Prologue((struct DisplayApi *)(((unsigned char *)pDisplayApi) + __nvoc_rtti_DispObject_DisplayApi.offset), pCallContext, pRsParams); } -static NV_STATUS __nvoc_thunk_RsResource_dispobjControlFilter(struct DispObject *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { - return resControlFilter((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_DispObject_RsResource.offset), pCallContext, pParams); +static NV_STATUS __nvoc_thunk_RsResource_dispobjUnmapFrom(struct DispObject *pResource, RS_RES_UNMAP_FROM_PARAMS *pParams) { + return resUnmapFrom((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_DispObject_RsResource.offset), pParams); } -static NvU32 __nvoc_thunk_RsResource_dispobjGetRefCount(struct DispObject *pResource) { - return resGetRefCount((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_DispObject_RsResource.offset)); +static void __nvoc_thunk_DisplayApi_dispobjControl_Epilogue(struct DispObject *pDisplayApi, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pRsParams) { + dispapiControl_Epilogue((struct DisplayApi *)(((unsigned char *)pDisplayApi) + __nvoc_rtti_DispObject_DisplayApi.offset), pCallContext, pRsParams); } -static NV_STATUS __nvoc_thunk_Notifier_dispobjUnregisterEvent(struct DispObject *pNotifier, NvHandle hNotifierClient, NvHandle hNotifierResource, NvHandle hEventClient, NvHandle hEvent) { - return notifyUnregisterEvent((struct Notifier *)(((unsigned char *)pNotifier) + __nvoc_rtti_DispObject_Notifier.offset), hNotifierClient, hNotifierResource, hEventClient, hEvent); +static NV_STATUS __nvoc_thunk_RsResource_dispobjControlLookup(struct DispObject *pResource, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams, const struct NVOC_EXPORTED_METHOD_DEF **ppEntry) { + return resControlLookup((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_DispObject_RsResource.offset), pParams, ppEntry); +} + +static NV_STATUS __nvoc_thunk_DisplayApi_dispobjControl(struct DispObject *pDisplayApi, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return dispapiControl((struct DisplayApi *)(((unsigned char *)pDisplayApi) + __nvoc_rtti_DispObject_DisplayApi.offset), pCallContext, pParams); } static NV_STATUS __nvoc_thunk_RsResource_dispobjUnmap(struct DispObject *pResource, struct CALL_CONTEXT *pCallContext, RsCpuMapping *pCpuMapping) { return resUnmap((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_DispObject_RsResource.offset), pCallContext, pCpuMapping); } -static NV_STATUS __nvoc_thunk_DisplayApi_dispobjControl_Prologue(struct DispObject *pDisplayApi, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pRsParams) { - return dispapiControl_Prologue((struct DisplayApi *)(((unsigned char *)pDisplayApi) + __nvoc_rtti_DispObject_DisplayApi.offset), pCallContext, pRsParams); +static NV_STATUS __nvoc_thunk_RmResource_dispobjGetMemInterMapParams(struct DispObject *pRmResource, RMRES_MEM_INTER_MAP_PARAMS *pParams) { + return rmresGetMemInterMapParams((struct RmResource *)(((unsigned char *)pRmResource) + __nvoc_rtti_DispObject_RmResource.offset), pParams); } -static NvBool __nvoc_thunk_RsResource_dispobjCanCopy(struct DispObject *pResource) { - return resCanCopy((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_DispObject_RsResource.offset)); +static NV_STATUS __nvoc_thunk_RmResource_dispobjGetMemoryMappingDescriptor(struct DispObject *pRmResource, struct MEMORY_DESCRIPTOR **ppMemDesc) { + return rmresGetMemoryMappingDescriptor((struct RmResource *)(((unsigned char *)pRmResource) + __nvoc_rtti_DispObject_RmResource.offset), ppMemDesc); } -static NV_STATUS __nvoc_thunk_RsResource_dispobjMapTo(struct DispObject *pResource, RS_RES_MAP_TO_PARAMS *pParams) { - return resMapTo((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_DispObject_RsResource.offset), pParams); +static NV_STATUS __nvoc_thunk_RsResource_dispobjControlFilter(struct DispObject *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return resControlFilter((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_DispObject_RsResource.offset), pCallContext, pParams); } -static void __nvoc_thunk_RsResource_dispobjAddAdditionalDependants(struct RsClient *pClient, struct DispObject *pResource, RsResourceRef *pReference) { - resAddAdditionalDependants(pClient, (struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_DispObject_RsResource.offset), pReference); +static NV_STATUS __nvoc_thunk_Notifier_dispobjUnregisterEvent(struct DispObject *pNotifier, NvHandle hNotifierClient, NvHandle hNotifierResource, NvHandle hEventClient, NvHandle hEvent) { + return notifyUnregisterEvent((struct Notifier *)(((unsigned char *)pNotifier) + __nvoc_rtti_DispObject_Notifier.offset), hNotifierClient, hNotifierResource, hEventClient, hEvent); } -static void __nvoc_thunk_RsResource_dispobjPreDestruct(struct DispObject *pResource) { - resPreDestruct((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_DispObject_RsResource.offset)); +static NV_STATUS __nvoc_thunk_RmResource_dispobjControlSerialization_Prologue(struct DispObject *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return rmresControlSerialization_Prologue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_DispObject_RmResource.offset), pCallContext, pParams); } -static NV_STATUS __nvoc_thunk_RsResource_dispobjUnmapFrom(struct DispObject *pResource, RS_RES_UNMAP_FROM_PARAMS *pParams) { - return resUnmapFrom((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_DispObject_RsResource.offset), pParams); +static NvBool __nvoc_thunk_RsResource_dispobjCanCopy(struct DispObject *pResource) { + return resCanCopy((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_DispObject_RsResource.offset)); +} + +static void __nvoc_thunk_RsResource_dispobjPreDestruct(struct DispObject *pResource) { + resPreDestruct((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_DispObject_RsResource.offset)); } static NV_STATUS __nvoc_thunk_RsResource_dispobjIsDuplicate(struct DispObject *pResource, NvHandle hMemory, NvBool *pDuplicate) { return resIsDuplicate((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_DispObject_RsResource.offset), hMemory, pDuplicate); } -static PEVENTNOTIFICATION *__nvoc_thunk_Notifier_dispobjGetNotificationListPtr(struct DispObject *pNotifier) { - return notifyGetNotificationListPtr((struct Notifier *)(((unsigned char *)pNotifier) + __nvoc_rtti_DispObject_Notifier.offset)); +static void __nvoc_thunk_RmResource_dispobjControlSerialization_Epilogue(struct DispObject *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + rmresControlSerialization_Epilogue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_DispObject_RmResource.offset), pCallContext, pParams); } -static void __nvoc_thunk_DisplayApi_dispobjControl_Epilogue(struct DispObject *pDisplayApi, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pRsParams) { - dispapiControl_Epilogue((struct DisplayApi *)(((unsigned char *)pDisplayApi) + __nvoc_rtti_DispObject_DisplayApi.offset), pCallContext, pRsParams); +static PEVENTNOTIFICATION *__nvoc_thunk_Notifier_dispobjGetNotificationListPtr(struct DispObject *pNotifier) { + return notifyGetNotificationListPtr((struct Notifier *)(((unsigned char *)pNotifier) + __nvoc_rtti_DispObject_Notifier.offset)); } static struct NotifShare *__nvoc_thunk_Notifier_dispobjGetNotificationShare(struct DispObject *pNotifier) { return notifyGetNotificationShare((struct Notifier *)(((unsigned char *)pNotifier) + __nvoc_rtti_DispObject_Notifier.offset)); } -static NV_STATUS __nvoc_thunk_RsResource_dispobjControlLookup(struct DispObject *pResource, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams, const struct NVOC_EXPORTED_METHOD_DEF **ppEntry) { - return resControlLookup((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_DispObject_RsResource.offset), pParams, ppEntry); -} - static NV_STATUS __nvoc_thunk_RsResource_dispobjMap(struct DispObject *pResource, struct CALL_CONTEXT *pCallContext, RS_CPU_MAP_PARAMS *pParams, RsCpuMapping *pCpuMapping) { return resMap((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_DispObject_RsResource.offset), pCallContext, pParams, pCpuMapping); } @@ -735,27 +764,12 @@ #endif }, { /* [10] */ -#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) - /*pFunc=*/ (void (*)(void)) NULL, -#else - /*pFunc=*/ (void (*)(void)) dispobjCtrlCmdGetRgConnectedLockpin_IMPL, -#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) - /*flags=*/ 0x210u, - /*accessRight=*/0x0u, - /*methodId=*/ 0x50700207u, - /*paramSize=*/ sizeof(NV5070_CTRL_CMD_GET_RG_CONNECTED_LOCKPIN_PARAMS), - /*pClassInfo=*/ &(__nvoc_class_def_DispObject.classInfo), -#if NV_PRINTF_STRINGS_ALLOWED - /*func=*/ "dispobjCtrlCmdGetRgConnectedLockpin" -#endif - }, - { /* [11] */ -#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x200u) +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x0u) /*pFunc=*/ (void (*)(void)) NULL, #else /*pFunc=*/ (void (*)(void)) dispobjCtrlCmdGetRgConnectedLockpinStateless_IMPL, -#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x200u) - /*flags=*/ 0x200u, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x0u) + /*flags=*/ 0x0u, /*accessRight=*/0x0u, /*methodId=*/ 0x5070020au, /*paramSize=*/ sizeof(NV5070_CTRL_GET_RG_CONNECTED_LOCKPIN_STATELESS_PARAMS), @@ -764,7 +778,7 @@ /*func=*/ "dispobjCtrlCmdGetRgConnectedLockpinStateless" #endif }, - { /* [12] */ + { /* [11] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -779,7 +793,7 @@ /*func=*/ "dispobjCtrlCmdGetPinsetLockpins" #endif }, - { /* [13] */ + { /* [12] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -794,7 +808,7 @@ /*func=*/ "dispobjCtrlCmdGetRgScanLine" #endif }, - { /* [14] */ + { /* [13] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x200u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -809,7 +823,7 @@ /*func=*/ "dispobjCtrlCmdGetFrameLockHeaderLockPins" #endif }, - { /* [15] */ + { /* [14] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -824,7 +838,7 @@ /*func=*/ "dispobjCtrlCmdGetSorSeqCtl" #endif }, - { /* [16] */ + { /* [15] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -839,7 +853,7 @@ /*func=*/ "dispobjCtrlCmdSetSorSeqCtl" #endif }, - { /* [17] */ + { /* [16] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -854,7 +868,7 @@ /*func=*/ "dispobjCtrlCmdGetPiorSeqCtl" #endif }, - { /* [18] */ + { /* [17] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -869,7 +883,7 @@ /*func=*/ "dispobjCtrlCmdSetPiorSeqCtl" #endif }, - { /* [19] */ + { /* [18] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -884,7 +898,7 @@ /*func=*/ "dispobjCtrlCmdSeqProgSpeed" #endif }, - { /* [20] */ + { /* [19] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x200u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -899,7 +913,7 @@ /*func=*/ "dispobjCtrlCmdGetSorPwm" #endif }, - { /* [21] */ + { /* [20] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x200u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -914,7 +928,7 @@ /*func=*/ "dispobjCtrlCmdSetSorPwm" #endif }, - { /* [22] */ + { /* [21] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x200u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -929,7 +943,7 @@ /*func=*/ "dispobjCtrlCmdGetSorOpMode" #endif }, - { /* [23] */ + { /* [22] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x200u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -944,7 +958,7 @@ /*func=*/ "dispobjCtrlCmdSetSorOpMode" #endif }, - { /* [24] */ + { /* [23] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -959,7 +973,7 @@ /*func=*/ "dispobjCtrlCmdGetPiorOpMode" #endif }, - { /* [25] */ + { /* [24] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -974,7 +988,7 @@ /*func=*/ "dispobjCtrlCmdSetPiorOpMode" #endif }, - { /* [26] */ + { /* [25] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x200u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -989,7 +1003,7 @@ /*func=*/ "dispobjCtrlCmdSetSorFlushMode" #endif }, - { /* [27] */ + { /* [26] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -1004,7 +1018,7 @@ /*func=*/ "dispobjCtrlCmdSystemGetCapsV2" #endif }, - { /* [28] */ + { /* [27] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -1019,7 +1033,7 @@ /*func=*/ "dispobjCtrlCmdEventSetTrigger" #endif }, - { /* [29] */ + { /* [28] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -1039,7 +1053,7 @@ const struct NVOC_EXPORT_INFO __nvoc_export_info_DispObject = { - /*numEntries=*/ 30, + /*numEntries=*/ 29, /*pExportEntries=*/ __nvoc_exported_method_def_DispObject }; @@ -1153,11 +1167,7 @@ pThis->__dispobjCtrlCmdSetRgFliplockProp__ = &dispobjCtrlCmdSetRgFliplockProp_IMPL; #endif -#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) - pThis->__dispobjCtrlCmdGetRgConnectedLockpin__ = &dispobjCtrlCmdGetRgConnectedLockpin_IMPL; -#endif - -#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x200u) +#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x0u) pThis->__dispobjCtrlCmdGetRgConnectedLockpinStateless__ = &dispobjCtrlCmdGetRgConnectedLockpinStateless_IMPL; #endif @@ -1207,48 +1217,52 @@ pThis->__dispobjShareCallback__ = &__nvoc_thunk_RmResource_dispobjShareCallback; - pThis->__dispobjControl__ = &__nvoc_thunk_DisplayApi_dispobjControl; + pThis->__dispobjCheckMemInterUnmap__ = &__nvoc_thunk_RmResource_dispobjCheckMemInterUnmap; + + pThis->__dispobjMapTo__ = &__nvoc_thunk_RsResource_dispobjMapTo; pThis->__dispobjAccessCallback__ = &__nvoc_thunk_RmResource_dispobjAccessCallback; - pThis->__dispobjGetMemInterMapParams__ = &__nvoc_thunk_RmResource_dispobjGetMemInterMapParams; + pThis->__dispobjSetNotificationShare__ = &__nvoc_thunk_Notifier_dispobjSetNotificationShare; - pThis->__dispobjGetMemoryMappingDescriptor__ = &__nvoc_thunk_RmResource_dispobjGetMemoryMappingDescriptor; + pThis->__dispobjGetRefCount__ = &__nvoc_thunk_RsResource_dispobjGetRefCount; - pThis->__dispobjCheckMemInterUnmap__ = &__nvoc_thunk_RmResource_dispobjCheckMemInterUnmap; + pThis->__dispobjAddAdditionalDependants__ = &__nvoc_thunk_RsResource_dispobjAddAdditionalDependants; - pThis->__dispobjSetNotificationShare__ = &__nvoc_thunk_Notifier_dispobjSetNotificationShare; + pThis->__dispobjControl_Prologue__ = &__nvoc_thunk_DisplayApi_dispobjControl_Prologue; - pThis->__dispobjControlFilter__ = &__nvoc_thunk_RsResource_dispobjControlFilter; + pThis->__dispobjUnmapFrom__ = &__nvoc_thunk_RsResource_dispobjUnmapFrom; - pThis->__dispobjGetRefCount__ = &__nvoc_thunk_RsResource_dispobjGetRefCount; + pThis->__dispobjControl_Epilogue__ = &__nvoc_thunk_DisplayApi_dispobjControl_Epilogue; - pThis->__dispobjUnregisterEvent__ = &__nvoc_thunk_Notifier_dispobjUnregisterEvent; + pThis->__dispobjControlLookup__ = &__nvoc_thunk_RsResource_dispobjControlLookup; + + pThis->__dispobjControl__ = &__nvoc_thunk_DisplayApi_dispobjControl; pThis->__dispobjUnmap__ = &__nvoc_thunk_RsResource_dispobjUnmap; - pThis->__dispobjControl_Prologue__ = &__nvoc_thunk_DisplayApi_dispobjControl_Prologue; + pThis->__dispobjGetMemInterMapParams__ = &__nvoc_thunk_RmResource_dispobjGetMemInterMapParams; - pThis->__dispobjCanCopy__ = &__nvoc_thunk_RsResource_dispobjCanCopy; + pThis->__dispobjGetMemoryMappingDescriptor__ = &__nvoc_thunk_RmResource_dispobjGetMemoryMappingDescriptor; - pThis->__dispobjMapTo__ = &__nvoc_thunk_RsResource_dispobjMapTo; + pThis->__dispobjControlFilter__ = &__nvoc_thunk_RsResource_dispobjControlFilter; - pThis->__dispobjAddAdditionalDependants__ = &__nvoc_thunk_RsResource_dispobjAddAdditionalDependants; + pThis->__dispobjUnregisterEvent__ = &__nvoc_thunk_Notifier_dispobjUnregisterEvent; - pThis->__dispobjPreDestruct__ = &__nvoc_thunk_RsResource_dispobjPreDestruct; + pThis->__dispobjControlSerialization_Prologue__ = &__nvoc_thunk_RmResource_dispobjControlSerialization_Prologue; - pThis->__dispobjUnmapFrom__ = &__nvoc_thunk_RsResource_dispobjUnmapFrom; + pThis->__dispobjCanCopy__ = &__nvoc_thunk_RsResource_dispobjCanCopy; + + pThis->__dispobjPreDestruct__ = &__nvoc_thunk_RsResource_dispobjPreDestruct; pThis->__dispobjIsDuplicate__ = &__nvoc_thunk_RsResource_dispobjIsDuplicate; - pThis->__dispobjGetNotificationListPtr__ = &__nvoc_thunk_Notifier_dispobjGetNotificationListPtr; + pThis->__dispobjControlSerialization_Epilogue__ = &__nvoc_thunk_RmResource_dispobjControlSerialization_Epilogue; - pThis->__dispobjControl_Epilogue__ = &__nvoc_thunk_DisplayApi_dispobjControl_Epilogue; + pThis->__dispobjGetNotificationListPtr__ = &__nvoc_thunk_Notifier_dispobjGetNotificationListPtr; pThis->__dispobjGetNotificationShare__ = &__nvoc_thunk_Notifier_dispobjGetNotificationShare; - pThis->__dispobjControlLookup__ = &__nvoc_thunk_RsResource_dispobjControlLookup; - pThis->__dispobjMap__ = &__nvoc_thunk_RsResource_dispobjMap; pThis->__dispobjGetOrAllocNotifShare__ = &__nvoc_thunk_Notifier_dispobjGetOrAllocNotifShare; @@ -1278,13 +1292,16 @@ DispObject *pThis; RmHalspecOwner *pRmhalspecowner; - pThis = portMemAllocNonPaged(sizeof(DispObject)); - if (pThis == NULL) return NV_ERR_NO_MEMORY; + status = __nvoc_handleObjCreateMemAlloc(createFlags, sizeof(DispObject), (void**)&pThis, (void**)ppThis); + if (status != NV_OK) + return status; portMemSet(pThis, 0, sizeof(DispObject)); __nvoc_initRtti(staticCast(pThis, Dynamic), &__nvoc_class_def_DispObject); + pThis->__nvoc_base_DisplayApi.__nvoc_base_RmResource.__nvoc_base_RsResource.__nvoc_base_Object.createFlags = createFlags; + if (pParent != NULL && !(createFlags & NVOC_OBJ_CREATE_FLAGS_PARENT_HALSPEC_ONLY)) { pParentObj = dynamicCast(pParent, Object); @@ -1304,11 +1321,17 @@ if (status != NV_OK) goto __nvoc_objCreate_DispObject_cleanup; *ppThis = pThis; + return NV_OK; __nvoc_objCreate_DispObject_cleanup: // do not call destructors here since the constructor already called them - portMemFree(pThis); + if (createFlags & NVOC_OBJ_CREATE_FLAGS_IN_PLACE_CONSTRUCT) + portMemSet(pThis, 0, sizeof(DispObject)); + else + portMemFree(pThis); + + // coverity[leaked_storage:FALSE] return status; } @@ -1439,90 +1462,98 @@ return rmresShareCallback((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_NvDispApi_RmResource.offset), pInvokingClient, pParentRef, pSharePolicy); } -static NV_STATUS __nvoc_thunk_DisplayApi_nvdispapiControl(struct NvDispApi *pDisplayApi, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { - return dispapiControl((struct DisplayApi *)(((unsigned char *)pDisplayApi) + __nvoc_rtti_NvDispApi_DisplayApi.offset), pCallContext, pParams); +static NV_STATUS __nvoc_thunk_RmResource_nvdispapiCheckMemInterUnmap(struct NvDispApi *pRmResource, NvBool bSubdeviceHandleProvided) { + return rmresCheckMemInterUnmap((struct RmResource *)(((unsigned char *)pRmResource) + __nvoc_rtti_NvDispApi_RmResource.offset), bSubdeviceHandleProvided); +} + +static NV_STATUS __nvoc_thunk_RsResource_nvdispapiMapTo(struct NvDispApi *pResource, RS_RES_MAP_TO_PARAMS *pParams) { + return resMapTo((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_NvDispApi_RsResource.offset), pParams); } static NvBool __nvoc_thunk_RmResource_nvdispapiAccessCallback(struct NvDispApi *pResource, struct RsClient *pInvokingClient, void *pAllocParams, RsAccessRight accessRight) { return rmresAccessCallback((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_NvDispApi_RmResource.offset), pInvokingClient, pAllocParams, accessRight); } -static NV_STATUS __nvoc_thunk_RmResource_nvdispapiGetMemInterMapParams(struct NvDispApi *pRmResource, RMRES_MEM_INTER_MAP_PARAMS *pParams) { - return rmresGetMemInterMapParams((struct RmResource *)(((unsigned char *)pRmResource) + __nvoc_rtti_NvDispApi_RmResource.offset), pParams); +static void __nvoc_thunk_Notifier_nvdispapiSetNotificationShare(struct NvDispApi *pNotifier, struct NotifShare *pNotifShare) { + notifySetNotificationShare((struct Notifier *)(((unsigned char *)pNotifier) + __nvoc_rtti_NvDispApi_Notifier.offset), pNotifShare); } -static NV_STATUS __nvoc_thunk_RmResource_nvdispapiGetMemoryMappingDescriptor(struct NvDispApi *pRmResource, struct MEMORY_DESCRIPTOR **ppMemDesc) { - return rmresGetMemoryMappingDescriptor((struct RmResource *)(((unsigned char *)pRmResource) + __nvoc_rtti_NvDispApi_RmResource.offset), ppMemDesc); +static NvU32 __nvoc_thunk_RsResource_nvdispapiGetRefCount(struct NvDispApi *pResource) { + return resGetRefCount((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_NvDispApi_RsResource.offset)); } -static NV_STATUS __nvoc_thunk_RmResource_nvdispapiCheckMemInterUnmap(struct NvDispApi *pRmResource, NvBool bSubdeviceHandleProvided) { - return rmresCheckMemInterUnmap((struct RmResource *)(((unsigned char *)pRmResource) + __nvoc_rtti_NvDispApi_RmResource.offset), bSubdeviceHandleProvided); +static void __nvoc_thunk_RsResource_nvdispapiAddAdditionalDependants(struct RsClient *pClient, struct NvDispApi *pResource, RsResourceRef *pReference) { + resAddAdditionalDependants(pClient, (struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_NvDispApi_RsResource.offset), pReference); } -static void __nvoc_thunk_Notifier_nvdispapiSetNotificationShare(struct NvDispApi *pNotifier, struct NotifShare *pNotifShare) { - notifySetNotificationShare((struct Notifier *)(((unsigned char *)pNotifier) + __nvoc_rtti_NvDispApi_Notifier.offset), pNotifShare); +static NV_STATUS __nvoc_thunk_DisplayApi_nvdispapiControl_Prologue(struct NvDispApi *pDisplayApi, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pRsParams) { + return dispapiControl_Prologue((struct DisplayApi *)(((unsigned char *)pDisplayApi) + __nvoc_rtti_NvDispApi_DisplayApi.offset), pCallContext, pRsParams); } -static NV_STATUS __nvoc_thunk_RsResource_nvdispapiControlFilter(struct NvDispApi *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { - return resControlFilter((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_NvDispApi_RsResource.offset), pCallContext, pParams); +static NV_STATUS __nvoc_thunk_RsResource_nvdispapiUnmapFrom(struct NvDispApi *pResource, RS_RES_UNMAP_FROM_PARAMS *pParams) { + return resUnmapFrom((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_NvDispApi_RsResource.offset), pParams); } -static NvU32 __nvoc_thunk_RsResource_nvdispapiGetRefCount(struct NvDispApi *pResource) { - return resGetRefCount((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_NvDispApi_RsResource.offset)); +static void __nvoc_thunk_DisplayApi_nvdispapiControl_Epilogue(struct NvDispApi *pDisplayApi, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pRsParams) { + dispapiControl_Epilogue((struct DisplayApi *)(((unsigned char *)pDisplayApi) + __nvoc_rtti_NvDispApi_DisplayApi.offset), pCallContext, pRsParams); } -static NV_STATUS __nvoc_thunk_Notifier_nvdispapiUnregisterEvent(struct NvDispApi *pNotifier, NvHandle hNotifierClient, NvHandle hNotifierResource, NvHandle hEventClient, NvHandle hEvent) { - return notifyUnregisterEvent((struct Notifier *)(((unsigned char *)pNotifier) + __nvoc_rtti_NvDispApi_Notifier.offset), hNotifierClient, hNotifierResource, hEventClient, hEvent); +static NV_STATUS __nvoc_thunk_RsResource_nvdispapiControlLookup(struct NvDispApi *pResource, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams, const struct NVOC_EXPORTED_METHOD_DEF **ppEntry) { + return resControlLookup((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_NvDispApi_RsResource.offset), pParams, ppEntry); +} + +static NV_STATUS __nvoc_thunk_DisplayApi_nvdispapiControl(struct NvDispApi *pDisplayApi, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return dispapiControl((struct DisplayApi *)(((unsigned char *)pDisplayApi) + __nvoc_rtti_NvDispApi_DisplayApi.offset), pCallContext, pParams); } static NV_STATUS __nvoc_thunk_RsResource_nvdispapiUnmap(struct NvDispApi *pResource, struct CALL_CONTEXT *pCallContext, RsCpuMapping *pCpuMapping) { return resUnmap((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_NvDispApi_RsResource.offset), pCallContext, pCpuMapping); } -static NV_STATUS __nvoc_thunk_DisplayApi_nvdispapiControl_Prologue(struct NvDispApi *pDisplayApi, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pRsParams) { - return dispapiControl_Prologue((struct DisplayApi *)(((unsigned char *)pDisplayApi) + __nvoc_rtti_NvDispApi_DisplayApi.offset), pCallContext, pRsParams); +static NV_STATUS __nvoc_thunk_RmResource_nvdispapiGetMemInterMapParams(struct NvDispApi *pRmResource, RMRES_MEM_INTER_MAP_PARAMS *pParams) { + return rmresGetMemInterMapParams((struct RmResource *)(((unsigned char *)pRmResource) + __nvoc_rtti_NvDispApi_RmResource.offset), pParams); } -static NvBool __nvoc_thunk_RsResource_nvdispapiCanCopy(struct NvDispApi *pResource) { - return resCanCopy((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_NvDispApi_RsResource.offset)); +static NV_STATUS __nvoc_thunk_RmResource_nvdispapiGetMemoryMappingDescriptor(struct NvDispApi *pRmResource, struct MEMORY_DESCRIPTOR **ppMemDesc) { + return rmresGetMemoryMappingDescriptor((struct RmResource *)(((unsigned char *)pRmResource) + __nvoc_rtti_NvDispApi_RmResource.offset), ppMemDesc); } -static NV_STATUS __nvoc_thunk_RsResource_nvdispapiMapTo(struct NvDispApi *pResource, RS_RES_MAP_TO_PARAMS *pParams) { - return resMapTo((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_NvDispApi_RsResource.offset), pParams); +static NV_STATUS __nvoc_thunk_RsResource_nvdispapiControlFilter(struct NvDispApi *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return resControlFilter((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_NvDispApi_RsResource.offset), pCallContext, pParams); } -static void __nvoc_thunk_RsResource_nvdispapiAddAdditionalDependants(struct RsClient *pClient, struct NvDispApi *pResource, RsResourceRef *pReference) { - resAddAdditionalDependants(pClient, (struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_NvDispApi_RsResource.offset), pReference); +static NV_STATUS __nvoc_thunk_Notifier_nvdispapiUnregisterEvent(struct NvDispApi *pNotifier, NvHandle hNotifierClient, NvHandle hNotifierResource, NvHandle hEventClient, NvHandle hEvent) { + return notifyUnregisterEvent((struct Notifier *)(((unsigned char *)pNotifier) + __nvoc_rtti_NvDispApi_Notifier.offset), hNotifierClient, hNotifierResource, hEventClient, hEvent); } -static void __nvoc_thunk_RsResource_nvdispapiPreDestruct(struct NvDispApi *pResource) { - resPreDestruct((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_NvDispApi_RsResource.offset)); +static NV_STATUS __nvoc_thunk_RmResource_nvdispapiControlSerialization_Prologue(struct NvDispApi *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return rmresControlSerialization_Prologue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_NvDispApi_RmResource.offset), pCallContext, pParams); } -static NV_STATUS __nvoc_thunk_RsResource_nvdispapiUnmapFrom(struct NvDispApi *pResource, RS_RES_UNMAP_FROM_PARAMS *pParams) { - return resUnmapFrom((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_NvDispApi_RsResource.offset), pParams); +static NvBool __nvoc_thunk_RsResource_nvdispapiCanCopy(struct NvDispApi *pResource) { + return resCanCopy((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_NvDispApi_RsResource.offset)); +} + +static void __nvoc_thunk_RsResource_nvdispapiPreDestruct(struct NvDispApi *pResource) { + resPreDestruct((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_NvDispApi_RsResource.offset)); } static NV_STATUS __nvoc_thunk_RsResource_nvdispapiIsDuplicate(struct NvDispApi *pResource, NvHandle hMemory, NvBool *pDuplicate) { return resIsDuplicate((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_NvDispApi_RsResource.offset), hMemory, pDuplicate); } -static PEVENTNOTIFICATION *__nvoc_thunk_Notifier_nvdispapiGetNotificationListPtr(struct NvDispApi *pNotifier) { - return notifyGetNotificationListPtr((struct Notifier *)(((unsigned char *)pNotifier) + __nvoc_rtti_NvDispApi_Notifier.offset)); +static void __nvoc_thunk_RmResource_nvdispapiControlSerialization_Epilogue(struct NvDispApi *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + rmresControlSerialization_Epilogue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_NvDispApi_RmResource.offset), pCallContext, pParams); } -static void __nvoc_thunk_DisplayApi_nvdispapiControl_Epilogue(struct NvDispApi *pDisplayApi, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pRsParams) { - dispapiControl_Epilogue((struct DisplayApi *)(((unsigned char *)pDisplayApi) + __nvoc_rtti_NvDispApi_DisplayApi.offset), pCallContext, pRsParams); +static PEVENTNOTIFICATION *__nvoc_thunk_Notifier_nvdispapiGetNotificationListPtr(struct NvDispApi *pNotifier) { + return notifyGetNotificationListPtr((struct Notifier *)(((unsigned char *)pNotifier) + __nvoc_rtti_NvDispApi_Notifier.offset)); } static struct NotifShare *__nvoc_thunk_Notifier_nvdispapiGetNotificationShare(struct NvDispApi *pNotifier) { return notifyGetNotificationShare((struct Notifier *)(((unsigned char *)pNotifier) + __nvoc_rtti_NvDispApi_Notifier.offset)); } -static NV_STATUS __nvoc_thunk_RsResource_nvdispapiControlLookup(struct NvDispApi *pResource, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams, const struct NVOC_EXPORTED_METHOD_DEF **ppEntry) { - return resControlLookup((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_NvDispApi_RsResource.offset), pParams, ppEntry); -} - static NV_STATUS __nvoc_thunk_RsResource_nvdispapiMap(struct NvDispApi *pResource, struct CALL_CONTEXT *pCallContext, RS_CPU_MAP_PARAMS *pParams, RsCpuMapping *pCpuMapping) { return resMap((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_NvDispApi_RsResource.offset), pCallContext, pParams, pCpuMapping); } @@ -1713,48 +1744,52 @@ pThis->__nvdispapiShareCallback__ = &__nvoc_thunk_RmResource_nvdispapiShareCallback; - pThis->__nvdispapiControl__ = &__nvoc_thunk_DisplayApi_nvdispapiControl; + pThis->__nvdispapiCheckMemInterUnmap__ = &__nvoc_thunk_RmResource_nvdispapiCheckMemInterUnmap; + + pThis->__nvdispapiMapTo__ = &__nvoc_thunk_RsResource_nvdispapiMapTo; pThis->__nvdispapiAccessCallback__ = &__nvoc_thunk_RmResource_nvdispapiAccessCallback; - pThis->__nvdispapiGetMemInterMapParams__ = &__nvoc_thunk_RmResource_nvdispapiGetMemInterMapParams; + pThis->__nvdispapiSetNotificationShare__ = &__nvoc_thunk_Notifier_nvdispapiSetNotificationShare; - pThis->__nvdispapiGetMemoryMappingDescriptor__ = &__nvoc_thunk_RmResource_nvdispapiGetMemoryMappingDescriptor; + pThis->__nvdispapiGetRefCount__ = &__nvoc_thunk_RsResource_nvdispapiGetRefCount; - pThis->__nvdispapiCheckMemInterUnmap__ = &__nvoc_thunk_RmResource_nvdispapiCheckMemInterUnmap; + pThis->__nvdispapiAddAdditionalDependants__ = &__nvoc_thunk_RsResource_nvdispapiAddAdditionalDependants; - pThis->__nvdispapiSetNotificationShare__ = &__nvoc_thunk_Notifier_nvdispapiSetNotificationShare; + pThis->__nvdispapiControl_Prologue__ = &__nvoc_thunk_DisplayApi_nvdispapiControl_Prologue; - pThis->__nvdispapiControlFilter__ = &__nvoc_thunk_RsResource_nvdispapiControlFilter; + pThis->__nvdispapiUnmapFrom__ = &__nvoc_thunk_RsResource_nvdispapiUnmapFrom; - pThis->__nvdispapiGetRefCount__ = &__nvoc_thunk_RsResource_nvdispapiGetRefCount; + pThis->__nvdispapiControl_Epilogue__ = &__nvoc_thunk_DisplayApi_nvdispapiControl_Epilogue; - pThis->__nvdispapiUnregisterEvent__ = &__nvoc_thunk_Notifier_nvdispapiUnregisterEvent; + pThis->__nvdispapiControlLookup__ = &__nvoc_thunk_RsResource_nvdispapiControlLookup; + + pThis->__nvdispapiControl__ = &__nvoc_thunk_DisplayApi_nvdispapiControl; pThis->__nvdispapiUnmap__ = &__nvoc_thunk_RsResource_nvdispapiUnmap; - pThis->__nvdispapiControl_Prologue__ = &__nvoc_thunk_DisplayApi_nvdispapiControl_Prologue; + pThis->__nvdispapiGetMemInterMapParams__ = &__nvoc_thunk_RmResource_nvdispapiGetMemInterMapParams; - pThis->__nvdispapiCanCopy__ = &__nvoc_thunk_RsResource_nvdispapiCanCopy; + pThis->__nvdispapiGetMemoryMappingDescriptor__ = &__nvoc_thunk_RmResource_nvdispapiGetMemoryMappingDescriptor; - pThis->__nvdispapiMapTo__ = &__nvoc_thunk_RsResource_nvdispapiMapTo; + pThis->__nvdispapiControlFilter__ = &__nvoc_thunk_RsResource_nvdispapiControlFilter; - pThis->__nvdispapiAddAdditionalDependants__ = &__nvoc_thunk_RsResource_nvdispapiAddAdditionalDependants; + pThis->__nvdispapiUnregisterEvent__ = &__nvoc_thunk_Notifier_nvdispapiUnregisterEvent; - pThis->__nvdispapiPreDestruct__ = &__nvoc_thunk_RsResource_nvdispapiPreDestruct; + pThis->__nvdispapiControlSerialization_Prologue__ = &__nvoc_thunk_RmResource_nvdispapiControlSerialization_Prologue; - pThis->__nvdispapiUnmapFrom__ = &__nvoc_thunk_RsResource_nvdispapiUnmapFrom; + pThis->__nvdispapiCanCopy__ = &__nvoc_thunk_RsResource_nvdispapiCanCopy; + + pThis->__nvdispapiPreDestruct__ = &__nvoc_thunk_RsResource_nvdispapiPreDestruct; pThis->__nvdispapiIsDuplicate__ = &__nvoc_thunk_RsResource_nvdispapiIsDuplicate; - pThis->__nvdispapiGetNotificationListPtr__ = &__nvoc_thunk_Notifier_nvdispapiGetNotificationListPtr; + pThis->__nvdispapiControlSerialization_Epilogue__ = &__nvoc_thunk_RmResource_nvdispapiControlSerialization_Epilogue; - pThis->__nvdispapiControl_Epilogue__ = &__nvoc_thunk_DisplayApi_nvdispapiControl_Epilogue; + pThis->__nvdispapiGetNotificationListPtr__ = &__nvoc_thunk_Notifier_nvdispapiGetNotificationListPtr; pThis->__nvdispapiGetNotificationShare__ = &__nvoc_thunk_Notifier_nvdispapiGetNotificationShare; - pThis->__nvdispapiControlLookup__ = &__nvoc_thunk_RsResource_nvdispapiControlLookup; - pThis->__nvdispapiMap__ = &__nvoc_thunk_RsResource_nvdispapiMap; pThis->__nvdispapiGetOrAllocNotifShare__ = &__nvoc_thunk_Notifier_nvdispapiGetOrAllocNotifShare; @@ -1785,13 +1820,16 @@ NvDispApi *pThis; RmHalspecOwner *pRmhalspecowner; - pThis = portMemAllocNonPaged(sizeof(NvDispApi)); - if (pThis == NULL) return NV_ERR_NO_MEMORY; + status = __nvoc_handleObjCreateMemAlloc(createFlags, sizeof(NvDispApi), (void**)&pThis, (void**)ppThis); + if (status != NV_OK) + return status; portMemSet(pThis, 0, sizeof(NvDispApi)); __nvoc_initRtti(staticCast(pThis, Dynamic), &__nvoc_class_def_NvDispApi); + pThis->__nvoc_base_DispObject.__nvoc_base_DisplayApi.__nvoc_base_RmResource.__nvoc_base_RsResource.__nvoc_base_Object.createFlags = createFlags; + if (pParent != NULL && !(createFlags & NVOC_OBJ_CREATE_FLAGS_PARENT_HALSPEC_ONLY)) { pParentObj = dynamicCast(pParent, Object); @@ -1811,11 +1849,17 @@ if (status != NV_OK) goto __nvoc_objCreate_NvDispApi_cleanup; *ppThis = pThis; + return NV_OK; __nvoc_objCreate_NvDispApi_cleanup: // do not call destructors here since the constructor already called them - portMemFree(pThis); + if (createFlags & NVOC_OBJ_CREATE_FLAGS_IN_PLACE_CONSTRUCT) + portMemSet(pThis, 0, sizeof(NvDispApi)); + else + portMemFree(pThis); + + // coverity[leaked_storage:FALSE] return status; } @@ -1937,90 +1981,98 @@ return rmresShareCallback((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_DispSwObj_RmResource.offset), pInvokingClient, pParentRef, pSharePolicy); } -static NV_STATUS __nvoc_thunk_DisplayApi_dispswobjControl(struct DispSwObj *pDisplayApi, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { - return dispapiControl((struct DisplayApi *)(((unsigned char *)pDisplayApi) + __nvoc_rtti_DispSwObj_DisplayApi.offset), pCallContext, pParams); +static NV_STATUS __nvoc_thunk_RmResource_dispswobjCheckMemInterUnmap(struct DispSwObj *pRmResource, NvBool bSubdeviceHandleProvided) { + return rmresCheckMemInterUnmap((struct RmResource *)(((unsigned char *)pRmResource) + __nvoc_rtti_DispSwObj_RmResource.offset), bSubdeviceHandleProvided); +} + +static NV_STATUS __nvoc_thunk_RsResource_dispswobjMapTo(struct DispSwObj *pResource, RS_RES_MAP_TO_PARAMS *pParams) { + return resMapTo((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_DispSwObj_RsResource.offset), pParams); } static NvBool __nvoc_thunk_RmResource_dispswobjAccessCallback(struct DispSwObj *pResource, struct RsClient *pInvokingClient, void *pAllocParams, RsAccessRight accessRight) { return rmresAccessCallback((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_DispSwObj_RmResource.offset), pInvokingClient, pAllocParams, accessRight); } -static NV_STATUS __nvoc_thunk_RmResource_dispswobjGetMemInterMapParams(struct DispSwObj *pRmResource, RMRES_MEM_INTER_MAP_PARAMS *pParams) { - return rmresGetMemInterMapParams((struct RmResource *)(((unsigned char *)pRmResource) + __nvoc_rtti_DispSwObj_RmResource.offset), pParams); +static void __nvoc_thunk_Notifier_dispswobjSetNotificationShare(struct DispSwObj *pNotifier, struct NotifShare *pNotifShare) { + notifySetNotificationShare((struct Notifier *)(((unsigned char *)pNotifier) + __nvoc_rtti_DispSwObj_Notifier.offset), pNotifShare); } -static NV_STATUS __nvoc_thunk_RmResource_dispswobjGetMemoryMappingDescriptor(struct DispSwObj *pRmResource, struct MEMORY_DESCRIPTOR **ppMemDesc) { - return rmresGetMemoryMappingDescriptor((struct RmResource *)(((unsigned char *)pRmResource) + __nvoc_rtti_DispSwObj_RmResource.offset), ppMemDesc); +static NvU32 __nvoc_thunk_RsResource_dispswobjGetRefCount(struct DispSwObj *pResource) { + return resGetRefCount((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_DispSwObj_RsResource.offset)); } -static NV_STATUS __nvoc_thunk_RmResource_dispswobjCheckMemInterUnmap(struct DispSwObj *pRmResource, NvBool bSubdeviceHandleProvided) { - return rmresCheckMemInterUnmap((struct RmResource *)(((unsigned char *)pRmResource) + __nvoc_rtti_DispSwObj_RmResource.offset), bSubdeviceHandleProvided); +static void __nvoc_thunk_RsResource_dispswobjAddAdditionalDependants(struct RsClient *pClient, struct DispSwObj *pResource, RsResourceRef *pReference) { + resAddAdditionalDependants(pClient, (struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_DispSwObj_RsResource.offset), pReference); } -static void __nvoc_thunk_Notifier_dispswobjSetNotificationShare(struct DispSwObj *pNotifier, struct NotifShare *pNotifShare) { - notifySetNotificationShare((struct Notifier *)(((unsigned char *)pNotifier) + __nvoc_rtti_DispSwObj_Notifier.offset), pNotifShare); +static NV_STATUS __nvoc_thunk_DisplayApi_dispswobjControl_Prologue(struct DispSwObj *pDisplayApi, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pRsParams) { + return dispapiControl_Prologue((struct DisplayApi *)(((unsigned char *)pDisplayApi) + __nvoc_rtti_DispSwObj_DisplayApi.offset), pCallContext, pRsParams); } -static NV_STATUS __nvoc_thunk_RsResource_dispswobjControlFilter(struct DispSwObj *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { - return resControlFilter((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_DispSwObj_RsResource.offset), pCallContext, pParams); +static NV_STATUS __nvoc_thunk_RsResource_dispswobjUnmapFrom(struct DispSwObj *pResource, RS_RES_UNMAP_FROM_PARAMS *pParams) { + return resUnmapFrom((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_DispSwObj_RsResource.offset), pParams); } -static NvU32 __nvoc_thunk_RsResource_dispswobjGetRefCount(struct DispSwObj *pResource) { - return resGetRefCount((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_DispSwObj_RsResource.offset)); +static void __nvoc_thunk_DisplayApi_dispswobjControl_Epilogue(struct DispSwObj *pDisplayApi, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pRsParams) { + dispapiControl_Epilogue((struct DisplayApi *)(((unsigned char *)pDisplayApi) + __nvoc_rtti_DispSwObj_DisplayApi.offset), pCallContext, pRsParams); } -static NV_STATUS __nvoc_thunk_Notifier_dispswobjUnregisterEvent(struct DispSwObj *pNotifier, NvHandle hNotifierClient, NvHandle hNotifierResource, NvHandle hEventClient, NvHandle hEvent) { - return notifyUnregisterEvent((struct Notifier *)(((unsigned char *)pNotifier) + __nvoc_rtti_DispSwObj_Notifier.offset), hNotifierClient, hNotifierResource, hEventClient, hEvent); +static NV_STATUS __nvoc_thunk_RsResource_dispswobjControlLookup(struct DispSwObj *pResource, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams, const struct NVOC_EXPORTED_METHOD_DEF **ppEntry) { + return resControlLookup((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_DispSwObj_RsResource.offset), pParams, ppEntry); +} + +static NV_STATUS __nvoc_thunk_DisplayApi_dispswobjControl(struct DispSwObj *pDisplayApi, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return dispapiControl((struct DisplayApi *)(((unsigned char *)pDisplayApi) + __nvoc_rtti_DispSwObj_DisplayApi.offset), pCallContext, pParams); } static NV_STATUS __nvoc_thunk_RsResource_dispswobjUnmap(struct DispSwObj *pResource, struct CALL_CONTEXT *pCallContext, RsCpuMapping *pCpuMapping) { return resUnmap((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_DispSwObj_RsResource.offset), pCallContext, pCpuMapping); } -static NV_STATUS __nvoc_thunk_DisplayApi_dispswobjControl_Prologue(struct DispSwObj *pDisplayApi, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pRsParams) { - return dispapiControl_Prologue((struct DisplayApi *)(((unsigned char *)pDisplayApi) + __nvoc_rtti_DispSwObj_DisplayApi.offset), pCallContext, pRsParams); +static NV_STATUS __nvoc_thunk_RmResource_dispswobjGetMemInterMapParams(struct DispSwObj *pRmResource, RMRES_MEM_INTER_MAP_PARAMS *pParams) { + return rmresGetMemInterMapParams((struct RmResource *)(((unsigned char *)pRmResource) + __nvoc_rtti_DispSwObj_RmResource.offset), pParams); } -static NvBool __nvoc_thunk_RsResource_dispswobjCanCopy(struct DispSwObj *pResource) { - return resCanCopy((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_DispSwObj_RsResource.offset)); +static NV_STATUS __nvoc_thunk_RmResource_dispswobjGetMemoryMappingDescriptor(struct DispSwObj *pRmResource, struct MEMORY_DESCRIPTOR **ppMemDesc) { + return rmresGetMemoryMappingDescriptor((struct RmResource *)(((unsigned char *)pRmResource) + __nvoc_rtti_DispSwObj_RmResource.offset), ppMemDesc); } -static NV_STATUS __nvoc_thunk_RsResource_dispswobjMapTo(struct DispSwObj *pResource, RS_RES_MAP_TO_PARAMS *pParams) { - return resMapTo((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_DispSwObj_RsResource.offset), pParams); +static NV_STATUS __nvoc_thunk_RsResource_dispswobjControlFilter(struct DispSwObj *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return resControlFilter((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_DispSwObj_RsResource.offset), pCallContext, pParams); } -static void __nvoc_thunk_RsResource_dispswobjAddAdditionalDependants(struct RsClient *pClient, struct DispSwObj *pResource, RsResourceRef *pReference) { - resAddAdditionalDependants(pClient, (struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_DispSwObj_RsResource.offset), pReference); +static NV_STATUS __nvoc_thunk_Notifier_dispswobjUnregisterEvent(struct DispSwObj *pNotifier, NvHandle hNotifierClient, NvHandle hNotifierResource, NvHandle hEventClient, NvHandle hEvent) { + return notifyUnregisterEvent((struct Notifier *)(((unsigned char *)pNotifier) + __nvoc_rtti_DispSwObj_Notifier.offset), hNotifierClient, hNotifierResource, hEventClient, hEvent); } -static void __nvoc_thunk_RsResource_dispswobjPreDestruct(struct DispSwObj *pResource) { - resPreDestruct((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_DispSwObj_RsResource.offset)); +static NV_STATUS __nvoc_thunk_RmResource_dispswobjControlSerialization_Prologue(struct DispSwObj *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return rmresControlSerialization_Prologue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_DispSwObj_RmResource.offset), pCallContext, pParams); } -static NV_STATUS __nvoc_thunk_RsResource_dispswobjUnmapFrom(struct DispSwObj *pResource, RS_RES_UNMAP_FROM_PARAMS *pParams) { - return resUnmapFrom((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_DispSwObj_RsResource.offset), pParams); +static NvBool __nvoc_thunk_RsResource_dispswobjCanCopy(struct DispSwObj *pResource) { + return resCanCopy((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_DispSwObj_RsResource.offset)); +} + +static void __nvoc_thunk_RsResource_dispswobjPreDestruct(struct DispSwObj *pResource) { + resPreDestruct((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_DispSwObj_RsResource.offset)); } static NV_STATUS __nvoc_thunk_RsResource_dispswobjIsDuplicate(struct DispSwObj *pResource, NvHandle hMemory, NvBool *pDuplicate) { return resIsDuplicate((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_DispSwObj_RsResource.offset), hMemory, pDuplicate); } -static PEVENTNOTIFICATION *__nvoc_thunk_Notifier_dispswobjGetNotificationListPtr(struct DispSwObj *pNotifier) { - return notifyGetNotificationListPtr((struct Notifier *)(((unsigned char *)pNotifier) + __nvoc_rtti_DispSwObj_Notifier.offset)); +static void __nvoc_thunk_RmResource_dispswobjControlSerialization_Epilogue(struct DispSwObj *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + rmresControlSerialization_Epilogue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_DispSwObj_RmResource.offset), pCallContext, pParams); } -static void __nvoc_thunk_DisplayApi_dispswobjControl_Epilogue(struct DispSwObj *pDisplayApi, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pRsParams) { - dispapiControl_Epilogue((struct DisplayApi *)(((unsigned char *)pDisplayApi) + __nvoc_rtti_DispSwObj_DisplayApi.offset), pCallContext, pRsParams); +static PEVENTNOTIFICATION *__nvoc_thunk_Notifier_dispswobjGetNotificationListPtr(struct DispSwObj *pNotifier) { + return notifyGetNotificationListPtr((struct Notifier *)(((unsigned char *)pNotifier) + __nvoc_rtti_DispSwObj_Notifier.offset)); } static struct NotifShare *__nvoc_thunk_Notifier_dispswobjGetNotificationShare(struct DispSwObj *pNotifier) { return notifyGetNotificationShare((struct Notifier *)(((unsigned char *)pNotifier) + __nvoc_rtti_DispSwObj_Notifier.offset)); } -static NV_STATUS __nvoc_thunk_RsResource_dispswobjControlLookup(struct DispSwObj *pResource, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams, const struct NVOC_EXPORTED_METHOD_DEF **ppEntry) { - return resControlLookup((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_DispSwObj_RsResource.offset), pParams, ppEntry); -} - static NV_STATUS __nvoc_thunk_RsResource_dispswobjMap(struct DispSwObj *pResource, struct CALL_CONTEXT *pCallContext, RS_CPU_MAP_PARAMS *pParams, RsCpuMapping *pCpuMapping) { return resMap((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_DispSwObj_RsResource.offset), pCallContext, pParams, pCpuMapping); } @@ -2154,48 +2206,52 @@ pThis->__dispswobjShareCallback__ = &__nvoc_thunk_RmResource_dispswobjShareCallback; - pThis->__dispswobjControl__ = &__nvoc_thunk_DisplayApi_dispswobjControl; + pThis->__dispswobjCheckMemInterUnmap__ = &__nvoc_thunk_RmResource_dispswobjCheckMemInterUnmap; + + pThis->__dispswobjMapTo__ = &__nvoc_thunk_RsResource_dispswobjMapTo; pThis->__dispswobjAccessCallback__ = &__nvoc_thunk_RmResource_dispswobjAccessCallback; - pThis->__dispswobjGetMemInterMapParams__ = &__nvoc_thunk_RmResource_dispswobjGetMemInterMapParams; + pThis->__dispswobjSetNotificationShare__ = &__nvoc_thunk_Notifier_dispswobjSetNotificationShare; - pThis->__dispswobjGetMemoryMappingDescriptor__ = &__nvoc_thunk_RmResource_dispswobjGetMemoryMappingDescriptor; + pThis->__dispswobjGetRefCount__ = &__nvoc_thunk_RsResource_dispswobjGetRefCount; - pThis->__dispswobjCheckMemInterUnmap__ = &__nvoc_thunk_RmResource_dispswobjCheckMemInterUnmap; + pThis->__dispswobjAddAdditionalDependants__ = &__nvoc_thunk_RsResource_dispswobjAddAdditionalDependants; - pThis->__dispswobjSetNotificationShare__ = &__nvoc_thunk_Notifier_dispswobjSetNotificationShare; + pThis->__dispswobjControl_Prologue__ = &__nvoc_thunk_DisplayApi_dispswobjControl_Prologue; - pThis->__dispswobjControlFilter__ = &__nvoc_thunk_RsResource_dispswobjControlFilter; + pThis->__dispswobjUnmapFrom__ = &__nvoc_thunk_RsResource_dispswobjUnmapFrom; - pThis->__dispswobjGetRefCount__ = &__nvoc_thunk_RsResource_dispswobjGetRefCount; + pThis->__dispswobjControl_Epilogue__ = &__nvoc_thunk_DisplayApi_dispswobjControl_Epilogue; - pThis->__dispswobjUnregisterEvent__ = &__nvoc_thunk_Notifier_dispswobjUnregisterEvent; + pThis->__dispswobjControlLookup__ = &__nvoc_thunk_RsResource_dispswobjControlLookup; + + pThis->__dispswobjControl__ = &__nvoc_thunk_DisplayApi_dispswobjControl; pThis->__dispswobjUnmap__ = &__nvoc_thunk_RsResource_dispswobjUnmap; - pThis->__dispswobjControl_Prologue__ = &__nvoc_thunk_DisplayApi_dispswobjControl_Prologue; + pThis->__dispswobjGetMemInterMapParams__ = &__nvoc_thunk_RmResource_dispswobjGetMemInterMapParams; - pThis->__dispswobjCanCopy__ = &__nvoc_thunk_RsResource_dispswobjCanCopy; + pThis->__dispswobjGetMemoryMappingDescriptor__ = &__nvoc_thunk_RmResource_dispswobjGetMemoryMappingDescriptor; - pThis->__dispswobjMapTo__ = &__nvoc_thunk_RsResource_dispswobjMapTo; + pThis->__dispswobjControlFilter__ = &__nvoc_thunk_RsResource_dispswobjControlFilter; - pThis->__dispswobjAddAdditionalDependants__ = &__nvoc_thunk_RsResource_dispswobjAddAdditionalDependants; + pThis->__dispswobjUnregisterEvent__ = &__nvoc_thunk_Notifier_dispswobjUnregisterEvent; - pThis->__dispswobjPreDestruct__ = &__nvoc_thunk_RsResource_dispswobjPreDestruct; + pThis->__dispswobjControlSerialization_Prologue__ = &__nvoc_thunk_RmResource_dispswobjControlSerialization_Prologue; - pThis->__dispswobjUnmapFrom__ = &__nvoc_thunk_RsResource_dispswobjUnmapFrom; + pThis->__dispswobjCanCopy__ = &__nvoc_thunk_RsResource_dispswobjCanCopy; + + pThis->__dispswobjPreDestruct__ = &__nvoc_thunk_RsResource_dispswobjPreDestruct; pThis->__dispswobjIsDuplicate__ = &__nvoc_thunk_RsResource_dispswobjIsDuplicate; - pThis->__dispswobjGetNotificationListPtr__ = &__nvoc_thunk_Notifier_dispswobjGetNotificationListPtr; + pThis->__dispswobjControlSerialization_Epilogue__ = &__nvoc_thunk_RmResource_dispswobjControlSerialization_Epilogue; - pThis->__dispswobjControl_Epilogue__ = &__nvoc_thunk_DisplayApi_dispswobjControl_Epilogue; + pThis->__dispswobjGetNotificationListPtr__ = &__nvoc_thunk_Notifier_dispswobjGetNotificationListPtr; pThis->__dispswobjGetNotificationShare__ = &__nvoc_thunk_Notifier_dispswobjGetNotificationShare; - pThis->__dispswobjControlLookup__ = &__nvoc_thunk_RsResource_dispswobjControlLookup; - pThis->__dispswobjMap__ = &__nvoc_thunk_RsResource_dispswobjMap; pThis->__dispswobjGetOrAllocNotifShare__ = &__nvoc_thunk_Notifier_dispswobjGetOrAllocNotifShare; @@ -2225,13 +2281,16 @@ DispSwObj *pThis; RmHalspecOwner *pRmhalspecowner; - pThis = portMemAllocNonPaged(sizeof(DispSwObj)); - if (pThis == NULL) return NV_ERR_NO_MEMORY; + status = __nvoc_handleObjCreateMemAlloc(createFlags, sizeof(DispSwObj), (void**)&pThis, (void**)ppThis); + if (status != NV_OK) + return status; portMemSet(pThis, 0, sizeof(DispSwObj)); __nvoc_initRtti(staticCast(pThis, Dynamic), &__nvoc_class_def_DispSwObj); + pThis->__nvoc_base_DisplayApi.__nvoc_base_RmResource.__nvoc_base_RsResource.__nvoc_base_Object.createFlags = createFlags; + if (pParent != NULL && !(createFlags & NVOC_OBJ_CREATE_FLAGS_PARENT_HALSPEC_ONLY)) { pParentObj = dynamicCast(pParent, Object); @@ -2251,11 +2310,17 @@ if (status != NV_OK) goto __nvoc_objCreate_DispSwObj_cleanup; *ppThis = pThis; + return NV_OK; __nvoc_objCreate_DispSwObj_cleanup: // do not call destructors here since the constructor already called them - portMemFree(pThis); + if (createFlags & NVOC_OBJ_CREATE_FLAGS_IN_PLACE_CONSTRUCT) + portMemSet(pThis, 0, sizeof(DispSwObj)); + else + portMemFree(pThis); + + // coverity[leaked_storage:FALSE] return status; } @@ -2377,90 +2442,98 @@ return rmresShareCallback((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_DispCommon_RmResource.offset), pInvokingClient, pParentRef, pSharePolicy); } -static NV_STATUS __nvoc_thunk_DisplayApi_dispcmnControl(struct DispCommon *pDisplayApi, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { - return dispapiControl((struct DisplayApi *)(((unsigned char *)pDisplayApi) + __nvoc_rtti_DispCommon_DisplayApi.offset), pCallContext, pParams); +static NV_STATUS __nvoc_thunk_RmResource_dispcmnCheckMemInterUnmap(struct DispCommon *pRmResource, NvBool bSubdeviceHandleProvided) { + return rmresCheckMemInterUnmap((struct RmResource *)(((unsigned char *)pRmResource) + __nvoc_rtti_DispCommon_RmResource.offset), bSubdeviceHandleProvided); +} + +static NV_STATUS __nvoc_thunk_RsResource_dispcmnMapTo(struct DispCommon *pResource, RS_RES_MAP_TO_PARAMS *pParams) { + return resMapTo((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_DispCommon_RsResource.offset), pParams); } static NvBool __nvoc_thunk_RmResource_dispcmnAccessCallback(struct DispCommon *pResource, struct RsClient *pInvokingClient, void *pAllocParams, RsAccessRight accessRight) { return rmresAccessCallback((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_DispCommon_RmResource.offset), pInvokingClient, pAllocParams, accessRight); } -static NV_STATUS __nvoc_thunk_RmResource_dispcmnGetMemInterMapParams(struct DispCommon *pRmResource, RMRES_MEM_INTER_MAP_PARAMS *pParams) { - return rmresGetMemInterMapParams((struct RmResource *)(((unsigned char *)pRmResource) + __nvoc_rtti_DispCommon_RmResource.offset), pParams); +static void __nvoc_thunk_Notifier_dispcmnSetNotificationShare(struct DispCommon *pNotifier, struct NotifShare *pNotifShare) { + notifySetNotificationShare((struct Notifier *)(((unsigned char *)pNotifier) + __nvoc_rtti_DispCommon_Notifier.offset), pNotifShare); } -static NV_STATUS __nvoc_thunk_RmResource_dispcmnGetMemoryMappingDescriptor(struct DispCommon *pRmResource, struct MEMORY_DESCRIPTOR **ppMemDesc) { - return rmresGetMemoryMappingDescriptor((struct RmResource *)(((unsigned char *)pRmResource) + __nvoc_rtti_DispCommon_RmResource.offset), ppMemDesc); +static NvU32 __nvoc_thunk_RsResource_dispcmnGetRefCount(struct DispCommon *pResource) { + return resGetRefCount((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_DispCommon_RsResource.offset)); } -static NV_STATUS __nvoc_thunk_RmResource_dispcmnCheckMemInterUnmap(struct DispCommon *pRmResource, NvBool bSubdeviceHandleProvided) { - return rmresCheckMemInterUnmap((struct RmResource *)(((unsigned char *)pRmResource) + __nvoc_rtti_DispCommon_RmResource.offset), bSubdeviceHandleProvided); +static void __nvoc_thunk_RsResource_dispcmnAddAdditionalDependants(struct RsClient *pClient, struct DispCommon *pResource, RsResourceRef *pReference) { + resAddAdditionalDependants(pClient, (struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_DispCommon_RsResource.offset), pReference); } -static void __nvoc_thunk_Notifier_dispcmnSetNotificationShare(struct DispCommon *pNotifier, struct NotifShare *pNotifShare) { - notifySetNotificationShare((struct Notifier *)(((unsigned char *)pNotifier) + __nvoc_rtti_DispCommon_Notifier.offset), pNotifShare); +static NV_STATUS __nvoc_thunk_DisplayApi_dispcmnControl_Prologue(struct DispCommon *pDisplayApi, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pRsParams) { + return dispapiControl_Prologue((struct DisplayApi *)(((unsigned char *)pDisplayApi) + __nvoc_rtti_DispCommon_DisplayApi.offset), pCallContext, pRsParams); } -static NV_STATUS __nvoc_thunk_RsResource_dispcmnControlFilter(struct DispCommon *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { - return resControlFilter((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_DispCommon_RsResource.offset), pCallContext, pParams); +static NV_STATUS __nvoc_thunk_RsResource_dispcmnUnmapFrom(struct DispCommon *pResource, RS_RES_UNMAP_FROM_PARAMS *pParams) { + return resUnmapFrom((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_DispCommon_RsResource.offset), pParams); } -static NvU32 __nvoc_thunk_RsResource_dispcmnGetRefCount(struct DispCommon *pResource) { - return resGetRefCount((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_DispCommon_RsResource.offset)); +static void __nvoc_thunk_DisplayApi_dispcmnControl_Epilogue(struct DispCommon *pDisplayApi, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pRsParams) { + dispapiControl_Epilogue((struct DisplayApi *)(((unsigned char *)pDisplayApi) + __nvoc_rtti_DispCommon_DisplayApi.offset), pCallContext, pRsParams); } -static NV_STATUS __nvoc_thunk_Notifier_dispcmnUnregisterEvent(struct DispCommon *pNotifier, NvHandle hNotifierClient, NvHandle hNotifierResource, NvHandle hEventClient, NvHandle hEvent) { - return notifyUnregisterEvent((struct Notifier *)(((unsigned char *)pNotifier) + __nvoc_rtti_DispCommon_Notifier.offset), hNotifierClient, hNotifierResource, hEventClient, hEvent); +static NV_STATUS __nvoc_thunk_RsResource_dispcmnControlLookup(struct DispCommon *pResource, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams, const struct NVOC_EXPORTED_METHOD_DEF **ppEntry) { + return resControlLookup((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_DispCommon_RsResource.offset), pParams, ppEntry); +} + +static NV_STATUS __nvoc_thunk_DisplayApi_dispcmnControl(struct DispCommon *pDisplayApi, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return dispapiControl((struct DisplayApi *)(((unsigned char *)pDisplayApi) + __nvoc_rtti_DispCommon_DisplayApi.offset), pCallContext, pParams); } static NV_STATUS __nvoc_thunk_RsResource_dispcmnUnmap(struct DispCommon *pResource, struct CALL_CONTEXT *pCallContext, RsCpuMapping *pCpuMapping) { return resUnmap((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_DispCommon_RsResource.offset), pCallContext, pCpuMapping); } -static NV_STATUS __nvoc_thunk_DisplayApi_dispcmnControl_Prologue(struct DispCommon *pDisplayApi, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pRsParams) { - return dispapiControl_Prologue((struct DisplayApi *)(((unsigned char *)pDisplayApi) + __nvoc_rtti_DispCommon_DisplayApi.offset), pCallContext, pRsParams); +static NV_STATUS __nvoc_thunk_RmResource_dispcmnGetMemInterMapParams(struct DispCommon *pRmResource, RMRES_MEM_INTER_MAP_PARAMS *pParams) { + return rmresGetMemInterMapParams((struct RmResource *)(((unsigned char *)pRmResource) + __nvoc_rtti_DispCommon_RmResource.offset), pParams); } -static NvBool __nvoc_thunk_RsResource_dispcmnCanCopy(struct DispCommon *pResource) { - return resCanCopy((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_DispCommon_RsResource.offset)); +static NV_STATUS __nvoc_thunk_RmResource_dispcmnGetMemoryMappingDescriptor(struct DispCommon *pRmResource, struct MEMORY_DESCRIPTOR **ppMemDesc) { + return rmresGetMemoryMappingDescriptor((struct RmResource *)(((unsigned char *)pRmResource) + __nvoc_rtti_DispCommon_RmResource.offset), ppMemDesc); } -static NV_STATUS __nvoc_thunk_RsResource_dispcmnMapTo(struct DispCommon *pResource, RS_RES_MAP_TO_PARAMS *pParams) { - return resMapTo((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_DispCommon_RsResource.offset), pParams); +static NV_STATUS __nvoc_thunk_RsResource_dispcmnControlFilter(struct DispCommon *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return resControlFilter((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_DispCommon_RsResource.offset), pCallContext, pParams); } -static void __nvoc_thunk_RsResource_dispcmnAddAdditionalDependants(struct RsClient *pClient, struct DispCommon *pResource, RsResourceRef *pReference) { - resAddAdditionalDependants(pClient, (struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_DispCommon_RsResource.offset), pReference); +static NV_STATUS __nvoc_thunk_Notifier_dispcmnUnregisterEvent(struct DispCommon *pNotifier, NvHandle hNotifierClient, NvHandle hNotifierResource, NvHandle hEventClient, NvHandle hEvent) { + return notifyUnregisterEvent((struct Notifier *)(((unsigned char *)pNotifier) + __nvoc_rtti_DispCommon_Notifier.offset), hNotifierClient, hNotifierResource, hEventClient, hEvent); } -static void __nvoc_thunk_RsResource_dispcmnPreDestruct(struct DispCommon *pResource) { - resPreDestruct((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_DispCommon_RsResource.offset)); +static NV_STATUS __nvoc_thunk_RmResource_dispcmnControlSerialization_Prologue(struct DispCommon *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return rmresControlSerialization_Prologue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_DispCommon_RmResource.offset), pCallContext, pParams); } -static NV_STATUS __nvoc_thunk_RsResource_dispcmnUnmapFrom(struct DispCommon *pResource, RS_RES_UNMAP_FROM_PARAMS *pParams) { - return resUnmapFrom((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_DispCommon_RsResource.offset), pParams); +static NvBool __nvoc_thunk_RsResource_dispcmnCanCopy(struct DispCommon *pResource) { + return resCanCopy((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_DispCommon_RsResource.offset)); +} + +static void __nvoc_thunk_RsResource_dispcmnPreDestruct(struct DispCommon *pResource) { + resPreDestruct((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_DispCommon_RsResource.offset)); } static NV_STATUS __nvoc_thunk_RsResource_dispcmnIsDuplicate(struct DispCommon *pResource, NvHandle hMemory, NvBool *pDuplicate) { return resIsDuplicate((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_DispCommon_RsResource.offset), hMemory, pDuplicate); } -static PEVENTNOTIFICATION *__nvoc_thunk_Notifier_dispcmnGetNotificationListPtr(struct DispCommon *pNotifier) { - return notifyGetNotificationListPtr((struct Notifier *)(((unsigned char *)pNotifier) + __nvoc_rtti_DispCommon_Notifier.offset)); +static void __nvoc_thunk_RmResource_dispcmnControlSerialization_Epilogue(struct DispCommon *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + rmresControlSerialization_Epilogue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_DispCommon_RmResource.offset), pCallContext, pParams); } -static void __nvoc_thunk_DisplayApi_dispcmnControl_Epilogue(struct DispCommon *pDisplayApi, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pRsParams) { - dispapiControl_Epilogue((struct DisplayApi *)(((unsigned char *)pDisplayApi) + __nvoc_rtti_DispCommon_DisplayApi.offset), pCallContext, pRsParams); +static PEVENTNOTIFICATION *__nvoc_thunk_Notifier_dispcmnGetNotificationListPtr(struct DispCommon *pNotifier) { + return notifyGetNotificationListPtr((struct Notifier *)(((unsigned char *)pNotifier) + __nvoc_rtti_DispCommon_Notifier.offset)); } static struct NotifShare *__nvoc_thunk_Notifier_dispcmnGetNotificationShare(struct DispCommon *pNotifier) { return notifyGetNotificationShare((struct Notifier *)(((unsigned char *)pNotifier) + __nvoc_rtti_DispCommon_Notifier.offset)); } -static NV_STATUS __nvoc_thunk_RsResource_dispcmnControlLookup(struct DispCommon *pResource, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams, const struct NVOC_EXPORTED_METHOD_DEF **ppEntry) { - return resControlLookup((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_DispCommon_RsResource.offset), pParams, ppEntry); -} - static NV_STATUS __nvoc_thunk_RsResource_dispcmnMap(struct DispCommon *pResource, struct CALL_CONTEXT *pCallContext, RS_CPU_MAP_PARAMS *pParams, RsCpuMapping *pCpuMapping) { return resMap((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_DispCommon_RsResource.offset), pCallContext, pParams, pCpuMapping); } @@ -2584,6 +2657,21 @@ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) /*pFunc=*/ (void (*)(void)) NULL, #else + /*pFunc=*/ (void (*)(void)) dispcmnCtrlCmdSystemGetHotplugState_IMPL, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) + /*flags=*/ 0x210u, + /*accessRight=*/0x0u, + /*methodId=*/ 0x730124u, + /*paramSize=*/ sizeof(NV0073_CTRL_SYSTEM_GET_HOTPLUG_STATE_PARAMS), + /*pClassInfo=*/ &(__nvoc_class_def_DispCommon.classInfo), +#if NV_PRINTF_STRINGS_ALLOWED + /*func=*/ "dispcmnCtrlCmdSystemGetHotplugState" +#endif + }, + { /* [8] */ +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) + /*pFunc=*/ (void (*)(void)) NULL, +#else /*pFunc=*/ (void (*)(void)) dispcmnCtrlCmdSystemGetHeadRoutingMap_IMPL, #endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) /*flags=*/ 0x210u, @@ -2595,7 +2683,7 @@ /*func=*/ "dispcmnCtrlCmdSystemGetHeadRoutingMap" #endif }, - { /* [8] */ + { /* [9] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -2610,7 +2698,7 @@ /*func=*/ "dispcmnCtrlCmdSystemGetActive" #endif }, - { /* [9] */ + { /* [10] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -2625,13 +2713,13 @@ /*func=*/ "dispcmnCtrlCmdSystemGetCapsV2" #endif }, - { /* [10] */ -#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) + { /* [11] */ +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x204u) /*pFunc=*/ (void (*)(void)) NULL, #else /*pFunc=*/ (void (*)(void)) dispcmnCtrlCmdSystemGetAcpiIdMap_IMPL, -#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) - /*flags=*/ 0x210u, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x204u) + /*flags=*/ 0x204u, /*accessRight=*/0x0u, /*methodId=*/ 0x73015au, /*paramSize=*/ sizeof(NV0073_CTRL_SYSTEM_GET_ACPI_ID_MAP_PARAMS), @@ -2640,7 +2728,7 @@ /*func=*/ "dispcmnCtrlCmdSystemGetAcpiIdMap" #endif }, - { /* [11] */ + { /* [12] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x212u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -2655,7 +2743,37 @@ /*func=*/ "dispcmnCtrlCmdSystemGetInternalDisplays" #endif }, - { /* [12] */ + { /* [13] */ +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x4u) + /*pFunc=*/ (void (*)(void)) NULL, +#else + /*pFunc=*/ (void (*)(void)) dispcmnCtrlCmdSystemAcpiSubsystemActivated_IMPL, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x4u) + /*flags=*/ 0x4u, + /*accessRight=*/0x0u, + /*methodId=*/ 0x73015cu, + /*paramSize=*/ sizeof(NV0073_CTRL_SYSTEM_ACPI_SUBSYSTEM_ACTIVATED_PARAMS), + /*pClassInfo=*/ &(__nvoc_class_def_DispCommon.classInfo), +#if NV_PRINTF_STRINGS_ALLOWED + /*func=*/ "dispcmnCtrlCmdSystemAcpiSubsystemActivated" +#endif + }, + { /* [14] */ +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x204u) + /*pFunc=*/ (void (*)(void)) NULL, +#else + /*pFunc=*/ (void (*)(void)) dispcmnCtrlCmdSystemGetConnectorTable_IMPL, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x204u) + /*flags=*/ 0x204u, + /*accessRight=*/0x0u, + /*methodId=*/ 0x730165u, + /*paramSize=*/ sizeof(NV0073_CTRL_SYSTEM_GET_CONNECTOR_TABLE_PARAMS), + /*pClassInfo=*/ &(__nvoc_class_def_DispCommon.classInfo), +#if NV_PRINTF_STRINGS_ALLOWED + /*func=*/ "dispcmnCtrlCmdSystemGetConnectorTable" +#endif + }, + { /* [15] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x204u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -2670,7 +2788,7 @@ /*func=*/ "dispcmnCtrlCmdSystemGetBootDisplays" #endif }, - { /* [13] */ + { /* [16] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x12u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -2685,7 +2803,7 @@ /*func=*/ "dispcmnCtrlCmdSystemExecuteAcpiMethod" #endif }, - { /* [14] */ + { /* [17] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x0u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -2700,7 +2818,7 @@ /*func=*/ "dispcmnCtrlCmdSystemGetHotplugUnplugState" #endif }, - { /* [15] */ + { /* [18] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x200u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -2715,7 +2833,7 @@ /*func=*/ "dispcmnCtrlCmdClearELVBlock" #endif }, - { /* [16] */ + { /* [19] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x200u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -2730,7 +2848,7 @@ /*func=*/ "dispcmnCtrlCmdSystemArmLightweightSupervisor" #endif }, - { /* [17] */ + { /* [20] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x200u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -2745,7 +2863,22 @@ /*func=*/ "dispcmnCtrlCmdSystemConfigVrrPstateSwitch" #endif }, - { /* [18] */ + { /* [21] */ +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x204u) + /*pFunc=*/ (void (*)(void)) NULL, +#else + /*pFunc=*/ (void (*)(void)) dispcmnCtrlCmdSystemVrrDisplayInfo_IMPL, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x204u) + /*flags=*/ 0x204u, + /*accessRight=*/0x0u, + /*methodId=*/ 0x730185u, + /*paramSize=*/ sizeof(NV0073_CTRL_SYSTEM_VRR_DISPLAY_INFO_PARAMS), + /*pClassInfo=*/ &(__nvoc_class_def_DispCommon.classInfo), +#if NV_PRINTF_STRINGS_ALLOWED + /*func=*/ "dispcmnCtrlCmdSystemVrrDisplayInfo" +#endif + }, + { /* [22] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x200u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -2760,7 +2893,7 @@ /*func=*/ "dispcmnCtrlCmdSystemQueryDisplayIdsWithMux" #endif }, - { /* [19] */ + { /* [23] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x0u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -2775,7 +2908,7 @@ /*func=*/ "dispcmnCtrlCmdSystemAllocateDisplayBandwidth" #endif }, - { /* [20] */ + { /* [24] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x204u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -2790,7 +2923,7 @@ /*func=*/ "dispcmnCtrlCmdSystemGetHotplugEventConfig" #endif }, - { /* [21] */ + { /* [25] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x204u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -2805,7 +2938,7 @@ /*func=*/ "dispcmnCtrlCmdSystemSetHotplugEventConfig" #endif }, - { /* [22] */ + { /* [26] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x200u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -2820,7 +2953,7 @@ /*func=*/ "dispcmnCtrlCmdDfpRecordChannelRegisters" #endif }, - { /* [23] */ + { /* [27] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x200u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -2835,7 +2968,7 @@ /*func=*/ "dispcmnCtrlCmdSystemCheckSidebandI2cSupport" #endif }, - { /* [24] */ + { /* [28] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x200u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -2850,7 +2983,22 @@ /*func=*/ "dispcmnCtrlCmdSystemCheckSidebandSrSupport" #endif }, - { /* [25] */ + { /* [29] */ +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x0u) + /*pFunc=*/ (void (*)(void)) NULL, +#else + /*pFunc=*/ (void (*)(void)) dispcmnCtrlCmdVRRSetRgLineActive_IMPL, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x0u) + /*flags=*/ 0x0u, + /*accessRight=*/0x0u, + /*methodId=*/ 0x73019eu, + /*paramSize=*/ sizeof(NV0073_CTRL_CMD_SYSTEM_VRR_SET_RGLINE_ACTIVE_PARAMS), + /*pClassInfo=*/ &(__nvoc_class_def_DispCommon.classInfo), +#if NV_PRINTF_STRINGS_ALLOWED + /*func=*/ "dispcmnCtrlCmdVRRSetRgLineActive" +#endif + }, + { /* [30] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -2865,7 +3013,7 @@ /*func=*/ "dispcmnCtrlCmdSpecificGetI2cPortid" #endif }, - { /* [26] */ + { /* [31] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x206u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -2880,7 +3028,7 @@ /*func=*/ "dispcmnCtrlCmdSpecificGetType" #endif }, - { /* [27] */ + { /* [32] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x204u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -2895,7 +3043,7 @@ /*func=*/ "dispcmnCtrlCmdSpecificFakeDevice" #endif }, - { /* [28] */ + { /* [33] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x204u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -2910,7 +3058,7 @@ /*func=*/ "dispcmnCtrlCmdSpecificGetEdidV2" #endif }, - { /* [29] */ + { /* [34] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x204u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -2925,7 +3073,7 @@ /*func=*/ "dispcmnCtrlCmdSpecificSetEdidV2" #endif }, - { /* [30] */ + { /* [35] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -2940,7 +3088,7 @@ /*func=*/ "dispcmnCtrlCmdSpecificGetConnectorData" #endif }, - { /* [31] */ + { /* [36] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x200u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -2955,7 +3103,7 @@ /*func=*/ "dispcmnCtrlCmdSpecificSetHdmiEnable" #endif }, - { /* [32] */ + { /* [37] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x204u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -2970,7 +3118,22 @@ /*func=*/ "dispcmnCtrlCmdSpecificCtrlHdmi" #endif }, - { /* [33] */ + { /* [38] */ +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x204u) + /*pFunc=*/ (void (*)(void)) NULL, +#else + /*pFunc=*/ (void (*)(void)) dispcmnCtrlCmdSpecificSetHdmiAudioMutestream_IMPL, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x204u) + /*flags=*/ 0x204u, + /*accessRight=*/0x0u, + /*methodId=*/ 0x730275u, + /*paramSize=*/ sizeof(NV0073_CTRL_CMD_SPECIFIC_SET_HDMI_AUDIO_MUTESTREAM_PARAMS), + /*pClassInfo=*/ &(__nvoc_class_def_DispCommon.classInfo), +#if NV_PRINTF_STRINGS_ALLOWED + /*func=*/ "dispcmnCtrlCmdSpecificSetHdmiAudioMutestream" +#endif + }, + { /* [39] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x4u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -2985,7 +3148,7 @@ /*func=*/ "dispcmnCtrlCmdSpecificSetAcpiIdMapping" #endif }, - { /* [34] */ + { /* [40] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x204u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -3000,7 +3163,7 @@ /*func=*/ "dispcmnCtrlCmdSpecificGetAcpiDodDisplayPortAttachment" #endif }, - { /* [35] */ + { /* [41] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x204u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -3015,7 +3178,7 @@ /*func=*/ "dispcmnCtrlCmdSpecificGetAllHeadMask" #endif }, - { /* [36] */ + { /* [42] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x200u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -3030,7 +3193,7 @@ /*func=*/ "dispcmnCtrlCmdSpecificSetOdPacket" #endif }, - { /* [37] */ + { /* [43] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x200u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -3045,7 +3208,7 @@ /*func=*/ "dispcmnCtrlCmdSpecificSetOdPacketCtrl" #endif }, - { /* [38] */ + { /* [44] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x200u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -3060,7 +3223,7 @@ /*func=*/ "dispcmnCtrlCmdSpecificGetPclkLimit" #endif }, - { /* [39] */ + { /* [45] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x206u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -3075,7 +3238,7 @@ /*func=*/ "dispcmnCtrlCmdSpecificOrGetInfo" #endif }, - { /* [40] */ + { /* [46] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x200u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -3090,7 +3253,7 @@ /*func=*/ "dispcmnCtrlCmdSpecificGetBacklightBrightness" #endif }, - { /* [41] */ + { /* [47] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x200u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -3105,7 +3268,7 @@ /*func=*/ "dispcmnCtrlCmdSpecificSetBacklightBrightness" #endif }, - { /* [42] */ + { /* [48] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x200u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -3120,7 +3283,7 @@ /*func=*/ "dispcmnCtrlCmdSpecificSetHdmiSinkCaps" #endif }, - { /* [43] */ + { /* [49] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x200u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -3135,7 +3298,7 @@ /*func=*/ "dispcmnCtrlCmdSpecificSetMonitorPower" #endif }, - { /* [44] */ + { /* [50] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x200u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -3150,7 +3313,7 @@ /*func=*/ "dispcmnCtrlCmdSpecificSetHdmiFrlLinkConfig" #endif }, - { /* [45] */ + { /* [51] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x200u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -3165,7 +3328,7 @@ /*func=*/ "dispcmnCtrlCmdSpecificApplyEdidOverrideV2" #endif }, - { /* [46] */ + { /* [52] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x200u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -3180,7 +3343,7 @@ /*func=*/ "dispcmnCtrlCmdSpecificGetHdmiGpuCaps" #endif }, - { /* [47] */ + { /* [53] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x200u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -3195,7 +3358,7 @@ /*func=*/ "dispcmnCtrlCmdSpecificDisplayChange" #endif }, - { /* [48] */ + { /* [54] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x200u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -3210,7 +3373,7 @@ /*func=*/ "dispcmnCtrlCmdSpecificGetHdmiScdcData" #endif }, - { /* [49] */ + { /* [55] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x200u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -3225,7 +3388,7 @@ /*func=*/ "dispcmnCtrlCmdSpecificIsDirectmodeDisplay" #endif }, - { /* [50] */ + { /* [56] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x200u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -3240,7 +3403,7 @@ /*func=*/ "dispcmnCtrlCmdSpecificSetHdmiFrlCapacityComputation" #endif }, - { /* [51] */ + { /* [57] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x200u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -3255,7 +3418,7 @@ /*func=*/ "dispcmnCtrlCmdSpecificSetSharedGenericPacket" #endif }, - { /* [52] */ + { /* [58] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x200u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -3270,7 +3433,7 @@ /*func=*/ "dispcmnCtrlCmdSpecificAcquireSharedGenericPacket" #endif }, - { /* [53] */ + { /* [59] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x200u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -3285,7 +3448,7 @@ /*func=*/ "dispcmnCtrlCmdSpecificReleaseSharedGenericPacket" #endif }, - { /* [54] */ + { /* [60] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x200u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -3300,7 +3463,7 @@ /*func=*/ "dispcmnCtrlCmdSpecificDispI2cReadWrite" #endif }, - { /* [55] */ + { /* [61] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -3315,7 +3478,22 @@ /*func=*/ "dispcmnCtrlCmdSpecificGetValidHeadWindowAssignment" #endif }, - { /* [56] */ + { /* [62] */ +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x200u) + /*pFunc=*/ (void (*)(void)) NULL, +#else + /*pFunc=*/ (void (*)(void)) dispcmnCtrlCmdSpecificDefaultAdaptivesyncDisplay_IMPL, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x200u) + /*flags=*/ 0x200u, + /*accessRight=*/0x0u, + /*methodId=*/ 0x7302aeu, + /*paramSize=*/ sizeof(NV0073_CTRL_SPECIFIC_DEFAULT_ADAPTIVESYNC_DISPLAY_PARAMS), + /*pClassInfo=*/ &(__nvoc_class_def_DispCommon.classInfo), +#if NV_PRINTF_STRINGS_ALLOWED + /*func=*/ "dispcmnCtrlCmdSpecificDefaultAdaptivesyncDisplay" +#endif + }, + { /* [63] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -3330,13 +3508,28 @@ /*func=*/ "dispcmnCtrlCmdInternalGetHotplugUnplugState" #endif }, - { /* [57] */ -#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x206u) + { /* [64] */ +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) + /*pFunc=*/ (void (*)(void)) NULL, +#else + /*pFunc=*/ (void (*)(void)) dispcmnCtrlCmdInternalVRRSetRgLineActive_IMPL, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) + /*flags=*/ 0x600u, + /*accessRight=*/0x0u, + /*methodId=*/ 0x730402u, + /*paramSize=*/ sizeof(NV0073_CTRL_CMD_SYSTEM_VRR_SET_RGLINE_ACTIVE_PARAMS), + /*pClassInfo=*/ &(__nvoc_class_def_DispCommon.classInfo), +#if NV_PRINTF_STRINGS_ALLOWED + /*func=*/ "dispcmnCtrlCmdInternalVRRSetRgLineActive" +#endif + }, + { /* [65] */ +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x212u) /*pFunc=*/ (void (*)(void)) NULL, #else /*pFunc=*/ (void (*)(void)) dispcmnCtrlCmdDfpGetInfo_IMPL, -#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x206u) - /*flags=*/ 0x206u, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x212u) + /*flags=*/ 0x212u, /*accessRight=*/0x0u, /*methodId=*/ 0x731140u, /*paramSize=*/ sizeof(NV0073_CTRL_DFP_GET_INFO_PARAMS), @@ -3345,7 +3538,7 @@ /*func=*/ "dispcmnCtrlCmdDfpGetInfo" #endif }, - { /* [58] */ + { /* [66] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -3360,7 +3553,7 @@ /*func=*/ "dispcmnCtrlCmdDfpGetDisplayportDongleInfo" #endif }, - { /* [59] */ + { /* [67] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x200u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -3375,7 +3568,7 @@ /*func=*/ "dispcmnCtrlCmdDfpSetEldAudioCaps" #endif }, - { /* [60] */ + { /* [68] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x204u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -3390,7 +3583,7 @@ /*func=*/ "dispcmnCtrlCmdDfpGetSpreadSpectrum" #endif }, - { /* [61] */ + { /* [69] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x204u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -3405,7 +3598,7 @@ /*func=*/ "dispcmnCtrlCmdDfpUpdateDynamicDfpCache" #endif }, - { /* [62] */ + { /* [70] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x200u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -3420,13 +3613,13 @@ /*func=*/ "dispcmnCtrlCmdDfpSetAudioEnable" #endif }, - { /* [63] */ -#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x204u) + { /* [71] */ +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x200u) /*pFunc=*/ (void (*)(void)) NULL, #else /*pFunc=*/ (void (*)(void)) dispcmnCtrlCmdDfpAssignSor_IMPL, -#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x204u) - /*flags=*/ 0x204u, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x200u) + /*flags=*/ 0x200u, /*accessRight=*/0x0u, /*methodId=*/ 0x731152u, /*paramSize=*/ sizeof(NV0073_CTRL_DFP_ASSIGN_SOR_PARAMS), @@ -3435,7 +3628,7 @@ /*func=*/ "dispcmnCtrlCmdDfpAssignSor" #endif }, - { /* [64] */ + { /* [72] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x204u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -3450,7 +3643,7 @@ /*func=*/ "dispcmnCtrlCmdDfpGetPadlinkMask" #endif }, - { /* [65] */ + { /* [73] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x204u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -3465,7 +3658,7 @@ /*func=*/ "dispcmnCtrlCmdDfpGetLcdGpioPinNum" #endif }, - { /* [66] */ + { /* [74] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x204u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -3480,7 +3673,7 @@ /*func=*/ "dispcmnCtrlCmdDfpConfigTwoHeadOneOr" #endif }, - { /* [67] */ + { /* [75] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x204u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -3495,7 +3688,7 @@ /*func=*/ "dispcmnCtrlCmdDfpDscCrcControl" #endif }, - { /* [68] */ + { /* [76] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x200u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -3510,7 +3703,7 @@ /*func=*/ "dispcmnCtrlCmdDfpInitMuxData" #endif }, - { /* [69] */ + { /* [77] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x204u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -3525,7 +3718,7 @@ /*func=*/ "dispcmnCtrlCmdDfpSwitchDispMux" #endif }, - { /* [70] */ + { /* [78] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x200u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -3540,7 +3733,7 @@ /*func=*/ "dispcmnCtrlCmdDfpRunPreDispMuxOperations" #endif }, - { /* [71] */ + { /* [79] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x200u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -3555,7 +3748,7 @@ /*func=*/ "dispcmnCtrlCmdDfpRunPostDispMuxOperations" #endif }, - { /* [72] */ + { /* [80] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x200u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -3570,7 +3763,7 @@ /*func=*/ "dispcmnCtrlCmdDfpGetDispMuxStatus" #endif }, - { /* [73] */ + { /* [81] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x204u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -3585,7 +3778,7 @@ /*func=*/ "dispcmnCtrlCmdDfpGetDsiModeTiming" #endif }, - { /* [74] */ + { /* [82] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x202u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -3600,7 +3793,7 @@ /*func=*/ "dispcmnCtrlCmdDfpGetFixedModeTiming" #endif }, - { /* [75] */ + { /* [83] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x8204u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -3615,7 +3808,7 @@ /*func=*/ "dispcmnCtrlCmdDpAuxchCtrl" #endif }, - { /* [76] */ + { /* [84] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x204u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -3630,7 +3823,7 @@ /*func=*/ "dispcmnCtrlCmdDpAuxchSetSema" #endif }, - { /* [77] */ + { /* [85] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x8204u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -3645,7 +3838,7 @@ /*func=*/ "dispcmnCtrlCmdDpCtrl" #endif }, - { /* [78] */ + { /* [86] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x204u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -3660,7 +3853,7 @@ /*func=*/ "dispcmnCtrlCmdDpGetLaneData" #endif }, - { /* [79] */ + { /* [87] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x204u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -3675,7 +3868,7 @@ /*func=*/ "dispcmnCtrlCmdDpSetLaneData" #endif }, - { /* [80] */ + { /* [88] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x204u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -3690,7 +3883,7 @@ /*func=*/ "dispcmnCtrlCmdDpSetTestpattern" #endif }, - { /* [81] */ + { /* [89] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x204u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -3705,7 +3898,7 @@ /*func=*/ "dispcmnCtrlCmdDpSetPreemphasisDrivecurrentPostcursor2Data" #endif }, - { /* [82] */ + { /* [90] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x204u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -3720,7 +3913,7 @@ /*func=*/ "dispcmnCtrlCmdDpGetPreemphasisDrivecurrentPostcursor2Data" #endif }, - { /* [83] */ + { /* [91] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x204u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -3735,7 +3928,7 @@ /*func=*/ "dispcmnCtrlCmdDpMainLinkCtrl" #endif }, - { /* [84] */ + { /* [92] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x204u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -3750,7 +3943,7 @@ /*func=*/ "dispcmnCtrlCmdDpGetAudioMuteStream" #endif }, - { /* [85] */ + { /* [93] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x200u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -3765,7 +3958,7 @@ /*func=*/ "dispcmnCtrlCmdDpSetAudioMuteStream" #endif }, - { /* [86] */ + { /* [94] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x204u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -3780,7 +3973,7 @@ /*func=*/ "dispcmnCtrlCmdDpASSRCtrl" #endif }, - { /* [87] */ + { /* [95] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x204u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -3795,7 +3988,7 @@ /*func=*/ "dispcmnCtrlCmdDpTopologyAllocateDisplayId" #endif }, - { /* [88] */ + { /* [96] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x204u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -3810,7 +4003,7 @@ /*func=*/ "dispcmnCtrlCmdDpTopologyFreeDisplayId" #endif }, - { /* [89] */ + { /* [97] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x204u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -3825,7 +4018,7 @@ /*func=*/ "dispcmnCtrlCmdDpGetLinkConfig" #endif }, - { /* [90] */ + { /* [98] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x204u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -3840,7 +4033,7 @@ /*func=*/ "dispcmnCtrlCmdDpGetEDPData" #endif }, - { /* [91] */ + { /* [99] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x204u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -3855,7 +4048,7 @@ /*func=*/ "dispcmnCtrlCmdDpConfigStream" #endif }, - { /* [92] */ + { /* [100] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x204u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -3870,7 +4063,7 @@ /*func=*/ "dispcmnCtrlCmdDpSetRateGov" #endif }, - { /* [93] */ + { /* [101] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x204u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -3885,7 +4078,7 @@ /*func=*/ "dispcmnCtrlCmdDpSetManualDisplayPort" #endif }, - { /* [94] */ + { /* [102] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x204u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -3900,7 +4093,7 @@ /*func=*/ "dispcmnCtrlCmdDpSetEcf" #endif }, - { /* [95] */ + { /* [103] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x204u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -3915,7 +4108,7 @@ /*func=*/ "dispcmnCtrlCmdDpSendACT" #endif }, - { /* [96] */ + { /* [104] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x206u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -3930,7 +4123,7 @@ /*func=*/ "dispcmnCtrlCmdDpGetCaps" #endif }, - { /* [97] */ + { /* [105] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x4u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -3945,7 +4138,7 @@ /*func=*/ "dispcmnCtrlCmdDpGenerateFakeInterrupt" #endif }, - { /* [98] */ + { /* [106] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x204u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -3960,7 +4153,7 @@ /*func=*/ "dispcmnCtrlCmdDpConfigRadScratchReg" #endif }, - { /* [99] */ + { /* [107] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x204u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -3975,7 +4168,7 @@ /*func=*/ "dispcmnCtrlCmdDpConfigSingleHeadMultiStream" #endif }, - { /* [100] */ + { /* [108] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x204u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -3990,7 +4183,7 @@ /*func=*/ "dispcmnCtrlCmdDpSetTriggerSelect" #endif }, - { /* [101] */ + { /* [109] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x204u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -4005,13 +4198,13 @@ /*func=*/ "dispcmnCtrlCmdDpSetTriggerAll" #endif }, - { /* [102] */ -#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) + { /* [110] */ +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x204u) /*pFunc=*/ (void (*)(void)) NULL, #else /*pFunc=*/ (void (*)(void)) dispcmnCtrlCmdDpGetAuxLogData_IMPL, -#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) - /*flags=*/ 0x210u, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x204u) + /*flags=*/ 0x204u, /*accessRight=*/0x0u, /*methodId=*/ 0x731373u, /*paramSize=*/ sizeof(NV0073_CTRL_CMD_DP_GET_AUXLOGGER_BUFFER_DATA_PARAMS), @@ -4020,7 +4213,7 @@ /*func=*/ "dispcmnCtrlCmdDpGetAuxLogData" #endif }, - { /* [103] */ + { /* [111] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x204u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -4035,7 +4228,7 @@ /*func=*/ "dispcmnCtrlCmdDpConfigIndexedLinkRates" #endif }, - { /* [104] */ + { /* [112] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x204u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -4050,7 +4243,7 @@ /*func=*/ "dispcmnCtrlCmdDpSetStereoMSAProperties" #endif }, - { /* [105] */ + { /* [113] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x204u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -4065,7 +4258,7 @@ /*func=*/ "dispcmnCtrlCmdDpConfigureFec" #endif }, - { /* [106] */ + { /* [114] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x204u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -4080,7 +4273,7 @@ /*func=*/ "dispcmnCtrlCmdDpConfigMacroPad" #endif }, - { /* [107] */ + { /* [115] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x200u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -4095,13 +4288,13 @@ /*func=*/ "dispcmnCtrlCmdDpAuxchI2cTransferCtrl" #endif }, - { /* [108] */ -#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x204u) + { /* [116] */ +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x8204u) /*pFunc=*/ (void (*)(void)) NULL, #else /*pFunc=*/ (void (*)(void)) dispcmnCtrlCmdDpEnableVrr_IMPL, -#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x204u) - /*flags=*/ 0x204u, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x8204u) + /*flags=*/ 0x8204u, /*accessRight=*/0x0u, /*methodId=*/ 0x73137du, /*paramSize=*/ sizeof(NV0073_CTRL_CMD_DP_ENABLE_VRR_PARAMS), @@ -4110,7 +4303,7 @@ /*func=*/ "dispcmnCtrlCmdDpEnableVrr" #endif }, - { /* [109] */ + { /* [117] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x204u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -4125,7 +4318,7 @@ /*func=*/ "dispcmnCtrlCmdDpGetGenericInfoframe" #endif }, - { /* [110] */ + { /* [118] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x204u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -4140,7 +4333,7 @@ /*func=*/ "dispcmnCtrlCmdDpGetMsaAttributes" #endif }, - { /* [111] */ + { /* [119] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x204u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -4155,7 +4348,7 @@ /*func=*/ "dispcmnCtrlCmdDfpInternalLcdOverdrive" #endif }, - { /* [112] */ + { /* [120] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x204u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -4170,12 +4363,57 @@ /*func=*/ "dispcmnCtrlCmdDpSetMSAPropertiesv2" #endif }, + { /* [121] */ +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x200u) + /*pFunc=*/ (void (*)(void)) NULL, +#else + /*pFunc=*/ (void (*)(void)) dispcmnCtrlCmdDfpExecuteInternalLcdOverDrivePolicy_IMPL, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x200u) + /*flags=*/ 0x200u, + /*accessRight=*/0x0u, + /*methodId=*/ 0x731382u, + /*paramSize=*/ sizeof(NV0073_CTRL_DP_EXECUTE_OVERDRIVE_POLICY_PARAMS), + /*pClassInfo=*/ &(__nvoc_class_def_DispCommon.classInfo), +#if NV_PRINTF_STRINGS_ALLOWED + /*func=*/ "dispcmnCtrlCmdDfpExecuteInternalLcdOverDrivePolicy" +#endif + }, + { /* [122] */ +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x204u) + /*pFunc=*/ (void (*)(void)) NULL, +#else + /*pFunc=*/ (void (*)(void)) dispcmnCtrlCmdPsrGetSrPanelInfo_IMPL, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x204u) + /*flags=*/ 0x204u, + /*accessRight=*/0x0u, + /*methodId=*/ 0x731602u, + /*paramSize=*/ sizeof(NV0073_CTRL_PSR_GET_SR_PANEL_INFO_PARAMS), + /*pClassInfo=*/ &(__nvoc_class_def_DispCommon.classInfo), +#if NV_PRINTF_STRINGS_ALLOWED + /*func=*/ "dispcmnCtrlCmdPsrGetSrPanelInfo" +#endif + }, + { /* [123] */ +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x204u) + /*pFunc=*/ (void (*)(void)) NULL, +#else + /*pFunc=*/ (void (*)(void)) dispcmnCtrlCmdStereoDongleSupported_IMPL, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x204u) + /*flags=*/ 0x204u, + /*accessRight=*/0x0u, + /*methodId=*/ 0x731702u, + /*paramSize=*/ sizeof(NV0073_CTRL_STEREO_DONGLE_SUPPORTED_PARAMS), + /*pClassInfo=*/ &(__nvoc_class_def_DispCommon.classInfo), +#if NV_PRINTF_STRINGS_ALLOWED + /*func=*/ "dispcmnCtrlCmdStereoDongleSupported" +#endif + }, }; const struct NVOC_EXPORT_INFO __nvoc_export_info_DispCommon = { - /*numEntries=*/ 113, + /*numEntries=*/ 124, /*pExportEntries=*/ __nvoc_exported_method_def_DispCommon }; @@ -4223,11 +4461,31 @@ pThis->__dispcmnCtrlCmdSystemCheckSidebandSrSupport__ = &dispcmnCtrlCmdSystemCheckSidebandSrSupport_IMPL; #endif +#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) + pThis->__dispcmnCtrlCmdSystemGetHotplugState__ = &dispcmnCtrlCmdSystemGetHotplugState_IMPL; +#endif + #if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x212u) pThis->__dispcmnCtrlCmdSystemGetInternalDisplays__ = &dispcmnCtrlCmdSystemGetInternalDisplays_IMPL; #endif #if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x204u) + pThis->__dispcmnCtrlCmdSystemGetConnectorTable__ = &dispcmnCtrlCmdSystemGetConnectorTable_IMPL; +#endif + +#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x204u) + pThis->__dispcmnCtrlCmdSystemVrrDisplayInfo__ = &dispcmnCtrlCmdSystemVrrDisplayInfo_IMPL; +#endif + +#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x0u) + pThis->__dispcmnCtrlCmdVRRSetRgLineActive__ = &dispcmnCtrlCmdVRRSetRgLineActive_IMPL; +#endif + +#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) + pThis->__dispcmnCtrlCmdInternalVRRSetRgLineActive__ = &dispcmnCtrlCmdInternalVRRSetRgLineActive_IMPL; +#endif + +#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x8204u) pThis->__dispcmnCtrlCmdDpEnableVrr__ = &dispcmnCtrlCmdDpEnableVrr_IMPL; #endif @@ -4263,6 +4521,14 @@ pThis->__dispcmnCtrlCmdDpSetEcf__ = &dispcmnCtrlCmdDpSetEcf_IMPL; #endif +#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x204u) + pThis->__dispcmnCtrlCmdStereoDongleSupported__ = &dispcmnCtrlCmdStereoDongleSupported_IMPL; +#endif + +#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x200u) + pThis->__dispcmnCtrlCmdDfpRecordChannelRegisters__ = &dispcmnCtrlCmdDfpRecordChannelRegisters_IMPL; +#endif + #if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x200u) pThis->__dispcmnCtrlCmdSpecificGetBacklightBrightness__ = &dispcmnCtrlCmdSpecificGetBacklightBrightness_IMPL; #endif @@ -4272,6 +4538,10 @@ #endif #if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x204u) + pThis->__dispcmnCtrlCmdPsrGetSrPanelInfo__ = &dispcmnCtrlCmdPsrGetSrPanelInfo_IMPL; +#endif + +#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x204u) pThis->__dispcmnCtrlCmdDfpSwitchDispMux__ = &dispcmnCtrlCmdDfpSwitchDispMux_IMPL; #endif @@ -4287,23 +4557,27 @@ pThis->__dispcmnCtrlCmdDfpGetDispMuxStatus__ = &dispcmnCtrlCmdDfpGetDispMuxStatus_IMPL; #endif -#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x200u) - pThis->__dispcmnCtrlCmdDfpRecordChannelRegisters__ = &dispcmnCtrlCmdDfpRecordChannelRegisters_IMPL; -#endif - #if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x204u) pThis->__dispcmnCtrlCmdDfpInternalLcdOverdrive__ = &dispcmnCtrlCmdDfpInternalLcdOverdrive_IMPL; #endif +#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x200u) + pThis->__dispcmnCtrlCmdDfpExecuteInternalLcdOverDrivePolicy__ = &dispcmnCtrlCmdDfpExecuteInternalLcdOverDrivePolicy_IMPL; +#endif + #if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x12u) pThis->__dispcmnCtrlCmdSystemExecuteAcpiMethod__ = &dispcmnCtrlCmdSystemExecuteAcpiMethod_IMPL; #endif -#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) +#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x204u) pThis->__dispcmnCtrlCmdSystemGetAcpiIdMap__ = &dispcmnCtrlCmdSystemGetAcpiIdMap_IMPL; #endif #if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x4u) + pThis->__dispcmnCtrlCmdSystemAcpiSubsystemActivated__ = &dispcmnCtrlCmdSystemAcpiSubsystemActivated_IMPL; +#endif + +#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x4u) pThis->__dispcmnCtrlCmdSpecificSetAcpiIdMapping__ = &dispcmnCtrlCmdSpecificSetAcpiIdMapping_IMPL; #endif @@ -4476,6 +4750,10 @@ #endif #if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x200u) + pThis->__dispcmnCtrlCmdSpecificDefaultAdaptivesyncDisplay__ = &dispcmnCtrlCmdSpecificDefaultAdaptivesyncDisplay_IMPL; +#endif + +#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x200u) pThis->__dispcmnCtrlCmdSpecificSetHdmiFrlCapacityComputation__ = &dispcmnCtrlCmdSpecificSetHdmiFrlCapacityComputation_IMPL; #endif @@ -4487,7 +4765,11 @@ pThis->__dispcmnCtrlCmdSpecificGetValidHeadWindowAssignment__ = &dispcmnCtrlCmdSpecificGetValidHeadWindowAssignment_IMPL; #endif -#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x206u) +#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x204u) + pThis->__dispcmnCtrlCmdSpecificSetHdmiAudioMutestream__ = &dispcmnCtrlCmdSpecificSetHdmiAudioMutestream_IMPL; +#endif + +#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x212u) pThis->__dispcmnCtrlCmdDfpGetInfo__ = &dispcmnCtrlCmdDfpGetInfo_IMPL; #endif @@ -4507,7 +4789,7 @@ pThis->__dispcmnCtrlCmdDfpUpdateDynamicDfpCache__ = &dispcmnCtrlCmdDfpUpdateDynamicDfpCache_IMPL; #endif -#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x204u) +#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x200u) pThis->__dispcmnCtrlCmdDfpAssignSor__ = &dispcmnCtrlCmdDfpAssignSor_IMPL; #endif @@ -4631,7 +4913,7 @@ pThis->__dispcmnCtrlCmdDpSetTriggerAll__ = &dispcmnCtrlCmdDpSetTriggerAll_IMPL; #endif -#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) +#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x204u) pThis->__dispcmnCtrlCmdDpGetAuxLogData__ = &dispcmnCtrlCmdDpGetAuxLogData_IMPL; #endif @@ -4665,48 +4947,52 @@ pThis->__dispcmnShareCallback__ = &__nvoc_thunk_RmResource_dispcmnShareCallback; - pThis->__dispcmnControl__ = &__nvoc_thunk_DisplayApi_dispcmnControl; + pThis->__dispcmnCheckMemInterUnmap__ = &__nvoc_thunk_RmResource_dispcmnCheckMemInterUnmap; + + pThis->__dispcmnMapTo__ = &__nvoc_thunk_RsResource_dispcmnMapTo; pThis->__dispcmnAccessCallback__ = &__nvoc_thunk_RmResource_dispcmnAccessCallback; - pThis->__dispcmnGetMemInterMapParams__ = &__nvoc_thunk_RmResource_dispcmnGetMemInterMapParams; + pThis->__dispcmnSetNotificationShare__ = &__nvoc_thunk_Notifier_dispcmnSetNotificationShare; - pThis->__dispcmnGetMemoryMappingDescriptor__ = &__nvoc_thunk_RmResource_dispcmnGetMemoryMappingDescriptor; + pThis->__dispcmnGetRefCount__ = &__nvoc_thunk_RsResource_dispcmnGetRefCount; - pThis->__dispcmnCheckMemInterUnmap__ = &__nvoc_thunk_RmResource_dispcmnCheckMemInterUnmap; + pThis->__dispcmnAddAdditionalDependants__ = &__nvoc_thunk_RsResource_dispcmnAddAdditionalDependants; - pThis->__dispcmnSetNotificationShare__ = &__nvoc_thunk_Notifier_dispcmnSetNotificationShare; + pThis->__dispcmnControl_Prologue__ = &__nvoc_thunk_DisplayApi_dispcmnControl_Prologue; - pThis->__dispcmnControlFilter__ = &__nvoc_thunk_RsResource_dispcmnControlFilter; + pThis->__dispcmnUnmapFrom__ = &__nvoc_thunk_RsResource_dispcmnUnmapFrom; - pThis->__dispcmnGetRefCount__ = &__nvoc_thunk_RsResource_dispcmnGetRefCount; + pThis->__dispcmnControl_Epilogue__ = &__nvoc_thunk_DisplayApi_dispcmnControl_Epilogue; - pThis->__dispcmnUnregisterEvent__ = &__nvoc_thunk_Notifier_dispcmnUnregisterEvent; + pThis->__dispcmnControlLookup__ = &__nvoc_thunk_RsResource_dispcmnControlLookup; + + pThis->__dispcmnControl__ = &__nvoc_thunk_DisplayApi_dispcmnControl; pThis->__dispcmnUnmap__ = &__nvoc_thunk_RsResource_dispcmnUnmap; - pThis->__dispcmnControl_Prologue__ = &__nvoc_thunk_DisplayApi_dispcmnControl_Prologue; + pThis->__dispcmnGetMemInterMapParams__ = &__nvoc_thunk_RmResource_dispcmnGetMemInterMapParams; - pThis->__dispcmnCanCopy__ = &__nvoc_thunk_RsResource_dispcmnCanCopy; + pThis->__dispcmnGetMemoryMappingDescriptor__ = &__nvoc_thunk_RmResource_dispcmnGetMemoryMappingDescriptor; - pThis->__dispcmnMapTo__ = &__nvoc_thunk_RsResource_dispcmnMapTo; + pThis->__dispcmnControlFilter__ = &__nvoc_thunk_RsResource_dispcmnControlFilter; - pThis->__dispcmnAddAdditionalDependants__ = &__nvoc_thunk_RsResource_dispcmnAddAdditionalDependants; + pThis->__dispcmnUnregisterEvent__ = &__nvoc_thunk_Notifier_dispcmnUnregisterEvent; - pThis->__dispcmnPreDestruct__ = &__nvoc_thunk_RsResource_dispcmnPreDestruct; + pThis->__dispcmnControlSerialization_Prologue__ = &__nvoc_thunk_RmResource_dispcmnControlSerialization_Prologue; - pThis->__dispcmnUnmapFrom__ = &__nvoc_thunk_RsResource_dispcmnUnmapFrom; + pThis->__dispcmnCanCopy__ = &__nvoc_thunk_RsResource_dispcmnCanCopy; + + pThis->__dispcmnPreDestruct__ = &__nvoc_thunk_RsResource_dispcmnPreDestruct; pThis->__dispcmnIsDuplicate__ = &__nvoc_thunk_RsResource_dispcmnIsDuplicate; - pThis->__dispcmnGetNotificationListPtr__ = &__nvoc_thunk_Notifier_dispcmnGetNotificationListPtr; + pThis->__dispcmnControlSerialization_Epilogue__ = &__nvoc_thunk_RmResource_dispcmnControlSerialization_Epilogue; - pThis->__dispcmnControl_Epilogue__ = &__nvoc_thunk_DisplayApi_dispcmnControl_Epilogue; + pThis->__dispcmnGetNotificationListPtr__ = &__nvoc_thunk_Notifier_dispcmnGetNotificationListPtr; pThis->__dispcmnGetNotificationShare__ = &__nvoc_thunk_Notifier_dispcmnGetNotificationShare; - pThis->__dispcmnControlLookup__ = &__nvoc_thunk_RsResource_dispcmnControlLookup; - pThis->__dispcmnMap__ = &__nvoc_thunk_RsResource_dispcmnMap; pThis->__dispcmnGetOrAllocNotifShare__ = &__nvoc_thunk_Notifier_dispcmnGetOrAllocNotifShare; @@ -4736,13 +5022,16 @@ DispCommon *pThis; RmHalspecOwner *pRmhalspecowner; - pThis = portMemAllocNonPaged(sizeof(DispCommon)); - if (pThis == NULL) return NV_ERR_NO_MEMORY; + status = __nvoc_handleObjCreateMemAlloc(createFlags, sizeof(DispCommon), (void**)&pThis, (void**)ppThis); + if (status != NV_OK) + return status; portMemSet(pThis, 0, sizeof(DispCommon)); __nvoc_initRtti(staticCast(pThis, Dynamic), &__nvoc_class_def_DispCommon); + pThis->__nvoc_base_DisplayApi.__nvoc_base_RmResource.__nvoc_base_RsResource.__nvoc_base_Object.createFlags = createFlags; + if (pParent != NULL && !(createFlags & NVOC_OBJ_CREATE_FLAGS_PARENT_HALSPEC_ONLY)) { pParentObj = dynamicCast(pParent, Object); @@ -4762,11 +5051,17 @@ if (status != NV_OK) goto __nvoc_objCreate_DispCommon_cleanup; *ppThis = pThis; + return NV_OK; __nvoc_objCreate_DispCommon_cleanup: // do not call destructors here since the constructor already called them - portMemFree(pThis); + if (createFlags & NVOC_OBJ_CREATE_FLAGS_IN_PLACE_CONSTRUCT) + portMemSet(pThis, 0, sizeof(DispCommon)); + else + portMemFree(pThis); + + // coverity[leaked_storage:FALSE] return status; } diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/generated/g_disp_objs_nvoc.h nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_disp_objs_nvoc.h --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/generated/g_disp_objs_nvoc.h 2023-10-25 20:26:55.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_disp_objs_nvoc.h 2024-03-05 22:18:11.000000000 +0000 @@ -7,7 +7,7 @@ #endif /* - * SPDX-FileCopyrightText: Copyright (c) 1993-2021 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 1993-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -120,23 +120,25 @@ void (*__dispapiControl_Epilogue__)(struct DisplayApi *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); NvBool (*__dispapiShareCallback__)(struct DisplayApi *, struct RsClient *, struct RsResourceRef *, RS_SHARE_POLICY *); NV_STATUS (*__dispapiCheckMemInterUnmap__)(struct DisplayApi *, NvBool); + NV_STATUS (*__dispapiMapTo__)(struct DisplayApi *, RS_RES_MAP_TO_PARAMS *); NvBool (*__dispapiAccessCallback__)(struct DisplayApi *, struct RsClient *, void *, RsAccessRight); + void (*__dispapiSetNotificationShare__)(struct DisplayApi *, struct NotifShare *); + NvU32 (*__dispapiGetRefCount__)(struct DisplayApi *); + void (*__dispapiAddAdditionalDependants__)(struct RsClient *, struct DisplayApi *, RsResourceRef *); + NV_STATUS (*__dispapiUnmapFrom__)(struct DisplayApi *, RS_RES_UNMAP_FROM_PARAMS *); + NV_STATUS (*__dispapiControlLookup__)(struct DisplayApi *, struct RS_RES_CONTROL_PARAMS_INTERNAL *, const struct NVOC_EXPORTED_METHOD_DEF **); + NV_STATUS (*__dispapiUnmap__)(struct DisplayApi *, struct CALL_CONTEXT *, RsCpuMapping *); NV_STATUS (*__dispapiGetMemInterMapParams__)(struct DisplayApi *, RMRES_MEM_INTER_MAP_PARAMS *); NV_STATUS (*__dispapiGetMemoryMappingDescriptor__)(struct DisplayApi *, struct MEMORY_DESCRIPTOR **); - void (*__dispapiSetNotificationShare__)(struct DisplayApi *, struct NotifShare *); NV_STATUS (*__dispapiControlFilter__)(struct DisplayApi *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); - NvU32 (*__dispapiGetRefCount__)(struct DisplayApi *); NV_STATUS (*__dispapiUnregisterEvent__)(struct DisplayApi *, NvHandle, NvHandle, NvHandle, NvHandle); - NV_STATUS (*__dispapiUnmap__)(struct DisplayApi *, struct CALL_CONTEXT *, RsCpuMapping *); + NV_STATUS (*__dispapiControlSerialization_Prologue__)(struct DisplayApi *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); NvBool (*__dispapiCanCopy__)(struct DisplayApi *); - NV_STATUS (*__dispapiMapTo__)(struct DisplayApi *, RS_RES_MAP_TO_PARAMS *); - void (*__dispapiAddAdditionalDependants__)(struct RsClient *, struct DisplayApi *, RsResourceRef *); void (*__dispapiPreDestruct__)(struct DisplayApi *); - NV_STATUS (*__dispapiUnmapFrom__)(struct DisplayApi *, RS_RES_UNMAP_FROM_PARAMS *); NV_STATUS (*__dispapiIsDuplicate__)(struct DisplayApi *, NvHandle, NvBool *); + void (*__dispapiControlSerialization_Epilogue__)(struct DisplayApi *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); PEVENTNOTIFICATION *(*__dispapiGetNotificationListPtr__)(struct DisplayApi *); struct NotifShare *(*__dispapiGetNotificationShare__)(struct DisplayApi *); - NV_STATUS (*__dispapiControlLookup__)(struct DisplayApi *, struct RS_RES_CONTROL_PARAMS_INTERNAL *, const struct NVOC_EXPORTED_METHOD_DEF **); NV_STATUS (*__dispapiMap__)(struct DisplayApi *, struct CALL_CONTEXT *, RS_CPU_MAP_PARAMS *, RsCpuMapping *); NV_STATUS (*__dispapiGetOrAllocNotifShare__)(struct DisplayApi *, NvHandle, NvHandle, struct NotifShare **); struct OBJGPU *pGpuInRmctrl; @@ -181,38 +183,40 @@ #define dispapiControl_Epilogue(pDisplayApi, pCallContext, pRsParams) dispapiControl_Epilogue_DISPATCH(pDisplayApi, pCallContext, pRsParams) #define dispapiShareCallback(pResource, pInvokingClient, pParentRef, pSharePolicy) dispapiShareCallback_DISPATCH(pResource, pInvokingClient, pParentRef, pSharePolicy) #define dispapiCheckMemInterUnmap(pRmResource, bSubdeviceHandleProvided) dispapiCheckMemInterUnmap_DISPATCH(pRmResource, bSubdeviceHandleProvided) +#define dispapiMapTo(pResource, pParams) dispapiMapTo_DISPATCH(pResource, pParams) #define dispapiAccessCallback(pResource, pInvokingClient, pAllocParams, accessRight) dispapiAccessCallback_DISPATCH(pResource, pInvokingClient, pAllocParams, accessRight) +#define dispapiSetNotificationShare(pNotifier, pNotifShare) dispapiSetNotificationShare_DISPATCH(pNotifier, pNotifShare) +#define dispapiGetRefCount(pResource) dispapiGetRefCount_DISPATCH(pResource) +#define dispapiAddAdditionalDependants(pClient, pResource, pReference) dispapiAddAdditionalDependants_DISPATCH(pClient, pResource, pReference) +#define dispapiUnmapFrom(pResource, pParams) dispapiUnmapFrom_DISPATCH(pResource, pParams) +#define dispapiControlLookup(pResource, pParams, ppEntry) dispapiControlLookup_DISPATCH(pResource, pParams, ppEntry) +#define dispapiUnmap(pResource, pCallContext, pCpuMapping) dispapiUnmap_DISPATCH(pResource, pCallContext, pCpuMapping) #define dispapiGetMemInterMapParams(pRmResource, pParams) dispapiGetMemInterMapParams_DISPATCH(pRmResource, pParams) #define dispapiGetMemoryMappingDescriptor(pRmResource, ppMemDesc) dispapiGetMemoryMappingDescriptor_DISPATCH(pRmResource, ppMemDesc) -#define dispapiSetNotificationShare(pNotifier, pNotifShare) dispapiSetNotificationShare_DISPATCH(pNotifier, pNotifShare) #define dispapiControlFilter(pResource, pCallContext, pParams) dispapiControlFilter_DISPATCH(pResource, pCallContext, pParams) -#define dispapiGetRefCount(pResource) dispapiGetRefCount_DISPATCH(pResource) #define dispapiUnregisterEvent(pNotifier, hNotifierClient, hNotifierResource, hEventClient, hEvent) dispapiUnregisterEvent_DISPATCH(pNotifier, hNotifierClient, hNotifierResource, hEventClient, hEvent) -#define dispapiUnmap(pResource, pCallContext, pCpuMapping) dispapiUnmap_DISPATCH(pResource, pCallContext, pCpuMapping) +#define dispapiControlSerialization_Prologue(pResource, pCallContext, pParams) dispapiControlSerialization_Prologue_DISPATCH(pResource, pCallContext, pParams) #define dispapiCanCopy(pResource) dispapiCanCopy_DISPATCH(pResource) -#define dispapiMapTo(pResource, pParams) dispapiMapTo_DISPATCH(pResource, pParams) -#define dispapiAddAdditionalDependants(pClient, pResource, pReference) dispapiAddAdditionalDependants_DISPATCH(pClient, pResource, pReference) #define dispapiPreDestruct(pResource) dispapiPreDestruct_DISPATCH(pResource) -#define dispapiUnmapFrom(pResource, pParams) dispapiUnmapFrom_DISPATCH(pResource, pParams) #define dispapiIsDuplicate(pResource, hMemory, pDuplicate) dispapiIsDuplicate_DISPATCH(pResource, hMemory, pDuplicate) +#define dispapiControlSerialization_Epilogue(pResource, pCallContext, pParams) dispapiControlSerialization_Epilogue_DISPATCH(pResource, pCallContext, pParams) #define dispapiGetNotificationListPtr(pNotifier) dispapiGetNotificationListPtr_DISPATCH(pNotifier) #define dispapiGetNotificationShare(pNotifier) dispapiGetNotificationShare_DISPATCH(pNotifier) -#define dispapiControlLookup(pResource, pParams, ppEntry) dispapiControlLookup_DISPATCH(pResource, pParams, ppEntry) #define dispapiMap(pResource, pCallContext, pParams, pCpuMapping) dispapiMap_DISPATCH(pResource, pCallContext, pParams, pCpuMapping) #define dispapiGetOrAllocNotifShare(pNotifier, hNotifierClient, hNotifierResource, ppNotifShare) dispapiGetOrAllocNotifShare_DISPATCH(pNotifier, hNotifierClient, hNotifierResource, ppNotifShare) -NV_STATUS dispapiSetUnicastAndSynchronize_KERNEL(struct DisplayApi *pDisplayApi, struct OBJGPUGRP *pGpuGroup, struct OBJGPU **ppGpu, NvU32 subDeviceInstance); +NV_STATUS dispapiSetUnicastAndSynchronize_KERNEL(struct DisplayApi *pDisplayApi, struct OBJGPUGRP *pGpuGroup, struct OBJGPU **ppGpu, OBJDISP **ppDisp, NvU32 subDeviceInstance); #ifdef __nvoc_disp_objs_h_disabled -static inline NV_STATUS dispapiSetUnicastAndSynchronize(struct DisplayApi *pDisplayApi, struct OBJGPUGRP *pGpuGroup, struct OBJGPU **ppGpu, NvU32 subDeviceInstance) { +static inline NV_STATUS dispapiSetUnicastAndSynchronize(struct DisplayApi *pDisplayApi, struct OBJGPUGRP *pGpuGroup, struct OBJGPU **ppGpu, OBJDISP **ppDisp, NvU32 subDeviceInstance) { NV_ASSERT_FAILED_PRECOMP("DisplayApi was disabled!"); return NV_ERR_NOT_SUPPORTED; } #else //__nvoc_disp_objs_h_disabled -#define dispapiSetUnicastAndSynchronize(pDisplayApi, pGpuGroup, ppGpu, subDeviceInstance) dispapiSetUnicastAndSynchronize_KERNEL(pDisplayApi, pGpuGroup, ppGpu, subDeviceInstance) +#define dispapiSetUnicastAndSynchronize(pDisplayApi, pGpuGroup, ppGpu, ppDisp, subDeviceInstance) dispapiSetUnicastAndSynchronize_KERNEL(pDisplayApi, pGpuGroup, ppGpu, ppDisp, subDeviceInstance) #endif //__nvoc_disp_objs_h_disabled -#define dispapiSetUnicastAndSynchronize_HAL(pDisplayApi, pGpuGroup, ppGpu, subDeviceInstance) dispapiSetUnicastAndSynchronize(pDisplayApi, pGpuGroup, ppGpu, subDeviceInstance) +#define dispapiSetUnicastAndSynchronize_HAL(pDisplayApi, pGpuGroup, ppGpu, ppDisp, subDeviceInstance) dispapiSetUnicastAndSynchronize(pDisplayApi, pGpuGroup, ppGpu, ppDisp, subDeviceInstance) NV_STATUS dispapiControl_IMPL(struct DisplayApi *pDisplayApi, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams); @@ -240,10 +244,38 @@ return pRmResource->__dispapiCheckMemInterUnmap__(pRmResource, bSubdeviceHandleProvided); } +static inline NV_STATUS dispapiMapTo_DISPATCH(struct DisplayApi *pResource, RS_RES_MAP_TO_PARAMS *pParams) { + return pResource->__dispapiMapTo__(pResource, pParams); +} + static inline NvBool dispapiAccessCallback_DISPATCH(struct DisplayApi *pResource, struct RsClient *pInvokingClient, void *pAllocParams, RsAccessRight accessRight) { return pResource->__dispapiAccessCallback__(pResource, pInvokingClient, pAllocParams, accessRight); } +static inline void dispapiSetNotificationShare_DISPATCH(struct DisplayApi *pNotifier, struct NotifShare *pNotifShare) { + pNotifier->__dispapiSetNotificationShare__(pNotifier, pNotifShare); +} + +static inline NvU32 dispapiGetRefCount_DISPATCH(struct DisplayApi *pResource) { + return pResource->__dispapiGetRefCount__(pResource); +} + +static inline void dispapiAddAdditionalDependants_DISPATCH(struct RsClient *pClient, struct DisplayApi *pResource, RsResourceRef *pReference) { + pResource->__dispapiAddAdditionalDependants__(pClient, pResource, pReference); +} + +static inline NV_STATUS dispapiUnmapFrom_DISPATCH(struct DisplayApi *pResource, RS_RES_UNMAP_FROM_PARAMS *pParams) { + return pResource->__dispapiUnmapFrom__(pResource, pParams); +} + +static inline NV_STATUS dispapiControlLookup_DISPATCH(struct DisplayApi *pResource, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams, const struct NVOC_EXPORTED_METHOD_DEF **ppEntry) { + return pResource->__dispapiControlLookup__(pResource, pParams, ppEntry); +} + +static inline NV_STATUS dispapiUnmap_DISPATCH(struct DisplayApi *pResource, struct CALL_CONTEXT *pCallContext, RsCpuMapping *pCpuMapping) { + return pResource->__dispapiUnmap__(pResource, pCallContext, pCpuMapping); +} + static inline NV_STATUS dispapiGetMemInterMapParams_DISPATCH(struct DisplayApi *pRmResource, RMRES_MEM_INTER_MAP_PARAMS *pParams) { return pRmResource->__dispapiGetMemInterMapParams__(pRmResource, pParams); } @@ -252,50 +284,34 @@ return pRmResource->__dispapiGetMemoryMappingDescriptor__(pRmResource, ppMemDesc); } -static inline void dispapiSetNotificationShare_DISPATCH(struct DisplayApi *pNotifier, struct NotifShare *pNotifShare) { - pNotifier->__dispapiSetNotificationShare__(pNotifier, pNotifShare); -} - static inline NV_STATUS dispapiControlFilter_DISPATCH(struct DisplayApi *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { return pResource->__dispapiControlFilter__(pResource, pCallContext, pParams); } -static inline NvU32 dispapiGetRefCount_DISPATCH(struct DisplayApi *pResource) { - return pResource->__dispapiGetRefCount__(pResource); -} - static inline NV_STATUS dispapiUnregisterEvent_DISPATCH(struct DisplayApi *pNotifier, NvHandle hNotifierClient, NvHandle hNotifierResource, NvHandle hEventClient, NvHandle hEvent) { return pNotifier->__dispapiUnregisterEvent__(pNotifier, hNotifierClient, hNotifierResource, hEventClient, hEvent); } -static inline NV_STATUS dispapiUnmap_DISPATCH(struct DisplayApi *pResource, struct CALL_CONTEXT *pCallContext, RsCpuMapping *pCpuMapping) { - return pResource->__dispapiUnmap__(pResource, pCallContext, pCpuMapping); +static inline NV_STATUS dispapiControlSerialization_Prologue_DISPATCH(struct DisplayApi *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return pResource->__dispapiControlSerialization_Prologue__(pResource, pCallContext, pParams); } static inline NvBool dispapiCanCopy_DISPATCH(struct DisplayApi *pResource) { return pResource->__dispapiCanCopy__(pResource); } -static inline NV_STATUS dispapiMapTo_DISPATCH(struct DisplayApi *pResource, RS_RES_MAP_TO_PARAMS *pParams) { - return pResource->__dispapiMapTo__(pResource, pParams); -} - -static inline void dispapiAddAdditionalDependants_DISPATCH(struct RsClient *pClient, struct DisplayApi *pResource, RsResourceRef *pReference) { - pResource->__dispapiAddAdditionalDependants__(pClient, pResource, pReference); -} - static inline void dispapiPreDestruct_DISPATCH(struct DisplayApi *pResource) { pResource->__dispapiPreDestruct__(pResource); } -static inline NV_STATUS dispapiUnmapFrom_DISPATCH(struct DisplayApi *pResource, RS_RES_UNMAP_FROM_PARAMS *pParams) { - return pResource->__dispapiUnmapFrom__(pResource, pParams); -} - static inline NV_STATUS dispapiIsDuplicate_DISPATCH(struct DisplayApi *pResource, NvHandle hMemory, NvBool *pDuplicate) { return pResource->__dispapiIsDuplicate__(pResource, hMemory, pDuplicate); } +static inline void dispapiControlSerialization_Epilogue_DISPATCH(struct DisplayApi *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + pResource->__dispapiControlSerialization_Epilogue__(pResource, pCallContext, pParams); +} + static inline PEVENTNOTIFICATION *dispapiGetNotificationListPtr_DISPATCH(struct DisplayApi *pNotifier) { return pNotifier->__dispapiGetNotificationListPtr__(pNotifier); } @@ -304,10 +320,6 @@ return pNotifier->__dispapiGetNotificationShare__(pNotifier); } -static inline NV_STATUS dispapiControlLookup_DISPATCH(struct DisplayApi *pResource, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams, const struct NVOC_EXPORTED_METHOD_DEF **ppEntry) { - return pResource->__dispapiControlLookup__(pResource, pParams, ppEntry); -} - static inline NV_STATUS dispapiMap_DISPATCH(struct DisplayApi *pResource, struct CALL_CONTEXT *pCallContext, RS_CPU_MAP_PARAMS *pParams, RsCpuMapping *pCpuMapping) { return pResource->__dispapiMap__(pResource, pCallContext, pParams, pCpuMapping); } @@ -376,7 +388,6 @@ NV_STATUS (*__dispobjCtrlCmdSetRgUnderflowProp__)(struct DispObject *, NV5070_CTRL_CMD_SET_RG_UNDERFLOW_PROP_PARAMS *); NV_STATUS (*__dispobjCtrlCmdGetRgFliplockProp__)(struct DispObject *, NV5070_CTRL_CMD_GET_RG_FLIPLOCK_PROP_PARAMS *); NV_STATUS (*__dispobjCtrlCmdSetRgFliplockProp__)(struct DispObject *, NV5070_CTRL_CMD_SET_RG_FLIPLOCK_PROP_PARAMS *); - NV_STATUS (*__dispobjCtrlCmdGetRgConnectedLockpin__)(struct DispObject *, NV5070_CTRL_CMD_GET_RG_CONNECTED_LOCKPIN_PARAMS *); NV_STATUS (*__dispobjCtrlCmdGetRgConnectedLockpinStateless__)(struct DispObject *, NV5070_CTRL_GET_RG_CONNECTED_LOCKPIN_STATELESS_PARAMS *); NV_STATUS (*__dispobjCtrlCmdGetRgScanLine__)(struct DispObject *, NV5070_CTRL_CMD_GET_RG_SCAN_LINE_PARAMS *); NV_STATUS (*__dispobjCtrlCmdGetSorSeqCtl__)(struct DispObject *, NV5070_CTRL_CMD_GET_SOR_SEQ_CTL_PARAMS *); @@ -390,27 +401,29 @@ NV_STATUS (*__dispobjCtrlCmdSystemGetCapsV2__)(struct DispObject *, NV5070_CTRL_SYSTEM_GET_CAPS_V2_PARAMS *); NV_STATUS (*__dispobjCtrlCmdEventSetTrigger__)(struct DispObject *); NvBool (*__dispobjShareCallback__)(struct DispObject *, struct RsClient *, struct RsResourceRef *, RS_SHARE_POLICY *); - NV_STATUS (*__dispobjControl__)(struct DispObject *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); + NV_STATUS (*__dispobjCheckMemInterUnmap__)(struct DispObject *, NvBool); + NV_STATUS (*__dispobjMapTo__)(struct DispObject *, RS_RES_MAP_TO_PARAMS *); NvBool (*__dispobjAccessCallback__)(struct DispObject *, struct RsClient *, void *, RsAccessRight); + void (*__dispobjSetNotificationShare__)(struct DispObject *, struct NotifShare *); + NvU32 (*__dispobjGetRefCount__)(struct DispObject *); + void (*__dispobjAddAdditionalDependants__)(struct RsClient *, struct DispObject *, RsResourceRef *); + NV_STATUS (*__dispobjControl_Prologue__)(struct DispObject *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); + NV_STATUS (*__dispobjUnmapFrom__)(struct DispObject *, RS_RES_UNMAP_FROM_PARAMS *); + void (*__dispobjControl_Epilogue__)(struct DispObject *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); + NV_STATUS (*__dispobjControlLookup__)(struct DispObject *, struct RS_RES_CONTROL_PARAMS_INTERNAL *, const struct NVOC_EXPORTED_METHOD_DEF **); + NV_STATUS (*__dispobjControl__)(struct DispObject *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); + NV_STATUS (*__dispobjUnmap__)(struct DispObject *, struct CALL_CONTEXT *, RsCpuMapping *); NV_STATUS (*__dispobjGetMemInterMapParams__)(struct DispObject *, RMRES_MEM_INTER_MAP_PARAMS *); NV_STATUS (*__dispobjGetMemoryMappingDescriptor__)(struct DispObject *, struct MEMORY_DESCRIPTOR **); - NV_STATUS (*__dispobjCheckMemInterUnmap__)(struct DispObject *, NvBool); - void (*__dispobjSetNotificationShare__)(struct DispObject *, struct NotifShare *); NV_STATUS (*__dispobjControlFilter__)(struct DispObject *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); - NvU32 (*__dispobjGetRefCount__)(struct DispObject *); NV_STATUS (*__dispobjUnregisterEvent__)(struct DispObject *, NvHandle, NvHandle, NvHandle, NvHandle); - NV_STATUS (*__dispobjUnmap__)(struct DispObject *, struct CALL_CONTEXT *, RsCpuMapping *); - NV_STATUS (*__dispobjControl_Prologue__)(struct DispObject *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); + NV_STATUS (*__dispobjControlSerialization_Prologue__)(struct DispObject *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); NvBool (*__dispobjCanCopy__)(struct DispObject *); - NV_STATUS (*__dispobjMapTo__)(struct DispObject *, RS_RES_MAP_TO_PARAMS *); - void (*__dispobjAddAdditionalDependants__)(struct RsClient *, struct DispObject *, RsResourceRef *); void (*__dispobjPreDestruct__)(struct DispObject *); - NV_STATUS (*__dispobjUnmapFrom__)(struct DispObject *, RS_RES_UNMAP_FROM_PARAMS *); NV_STATUS (*__dispobjIsDuplicate__)(struct DispObject *, NvHandle, NvBool *); + void (*__dispobjControlSerialization_Epilogue__)(struct DispObject *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); PEVENTNOTIFICATION *(*__dispobjGetNotificationListPtr__)(struct DispObject *); - void (*__dispobjControl_Epilogue__)(struct DispObject *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); struct NotifShare *(*__dispobjGetNotificationShare__)(struct DispObject *); - NV_STATUS (*__dispobjControlLookup__)(struct DispObject *, struct RS_RES_CONTROL_PARAMS_INTERNAL *, const struct NVOC_EXPORTED_METHOD_DEF **); NV_STATUS (*__dispobjMap__)(struct DispObject *, struct CALL_CONTEXT *, RS_CPU_MAP_PARAMS *, RsCpuMapping *); NV_STATUS (*__dispobjGetOrAllocNotifShare__)(struct DispObject *, NvHandle, NvHandle, struct NotifShare **); NvU32 rmFreeFlags; @@ -461,7 +474,6 @@ #define dispobjCtrlCmdSetRgUnderflowProp(pDispObject, pParams) dispobjCtrlCmdSetRgUnderflowProp_DISPATCH(pDispObject, pParams) #define dispobjCtrlCmdGetRgFliplockProp(pDispObject, pParams) dispobjCtrlCmdGetRgFliplockProp_DISPATCH(pDispObject, pParams) #define dispobjCtrlCmdSetRgFliplockProp(pDispObject, pParams) dispobjCtrlCmdSetRgFliplockProp_DISPATCH(pDispObject, pParams) -#define dispobjCtrlCmdGetRgConnectedLockpin(pDispObject, pParams) dispobjCtrlCmdGetRgConnectedLockpin_DISPATCH(pDispObject, pParams) #define dispobjCtrlCmdGetRgConnectedLockpinStateless(pDispObject, pParams) dispobjCtrlCmdGetRgConnectedLockpinStateless_DISPATCH(pDispObject, pParams) #define dispobjCtrlCmdGetRgScanLine(pDispObject, pParams) dispobjCtrlCmdGetRgScanLine_DISPATCH(pDispObject, pParams) #define dispobjCtrlCmdGetSorSeqCtl(pDispObject, pParams) dispobjCtrlCmdGetSorSeqCtl_DISPATCH(pDispObject, pParams) @@ -475,27 +487,29 @@ #define dispobjCtrlCmdSystemGetCapsV2(pDispObject, pCapsParams) dispobjCtrlCmdSystemGetCapsV2_DISPATCH(pDispObject, pCapsParams) #define dispobjCtrlCmdEventSetTrigger(pDispObject) dispobjCtrlCmdEventSetTrigger_DISPATCH(pDispObject) #define dispobjShareCallback(pResource, pInvokingClient, pParentRef, pSharePolicy) dispobjShareCallback_DISPATCH(pResource, pInvokingClient, pParentRef, pSharePolicy) -#define dispobjControl(pDisplayApi, pCallContext, pParams) dispobjControl_DISPATCH(pDisplayApi, pCallContext, pParams) +#define dispobjCheckMemInterUnmap(pRmResource, bSubdeviceHandleProvided) dispobjCheckMemInterUnmap_DISPATCH(pRmResource, bSubdeviceHandleProvided) +#define dispobjMapTo(pResource, pParams) dispobjMapTo_DISPATCH(pResource, pParams) #define dispobjAccessCallback(pResource, pInvokingClient, pAllocParams, accessRight) dispobjAccessCallback_DISPATCH(pResource, pInvokingClient, pAllocParams, accessRight) +#define dispobjSetNotificationShare(pNotifier, pNotifShare) dispobjSetNotificationShare_DISPATCH(pNotifier, pNotifShare) +#define dispobjGetRefCount(pResource) dispobjGetRefCount_DISPATCH(pResource) +#define dispobjAddAdditionalDependants(pClient, pResource, pReference) dispobjAddAdditionalDependants_DISPATCH(pClient, pResource, pReference) +#define dispobjControl_Prologue(pDisplayApi, pCallContext, pRsParams) dispobjControl_Prologue_DISPATCH(pDisplayApi, pCallContext, pRsParams) +#define dispobjUnmapFrom(pResource, pParams) dispobjUnmapFrom_DISPATCH(pResource, pParams) +#define dispobjControl_Epilogue(pDisplayApi, pCallContext, pRsParams) dispobjControl_Epilogue_DISPATCH(pDisplayApi, pCallContext, pRsParams) +#define dispobjControlLookup(pResource, pParams, ppEntry) dispobjControlLookup_DISPATCH(pResource, pParams, ppEntry) +#define dispobjControl(pDisplayApi, pCallContext, pParams) dispobjControl_DISPATCH(pDisplayApi, pCallContext, pParams) +#define dispobjUnmap(pResource, pCallContext, pCpuMapping) dispobjUnmap_DISPATCH(pResource, pCallContext, pCpuMapping) #define dispobjGetMemInterMapParams(pRmResource, pParams) dispobjGetMemInterMapParams_DISPATCH(pRmResource, pParams) #define dispobjGetMemoryMappingDescriptor(pRmResource, ppMemDesc) dispobjGetMemoryMappingDescriptor_DISPATCH(pRmResource, ppMemDesc) -#define dispobjCheckMemInterUnmap(pRmResource, bSubdeviceHandleProvided) dispobjCheckMemInterUnmap_DISPATCH(pRmResource, bSubdeviceHandleProvided) -#define dispobjSetNotificationShare(pNotifier, pNotifShare) dispobjSetNotificationShare_DISPATCH(pNotifier, pNotifShare) #define dispobjControlFilter(pResource, pCallContext, pParams) dispobjControlFilter_DISPATCH(pResource, pCallContext, pParams) -#define dispobjGetRefCount(pResource) dispobjGetRefCount_DISPATCH(pResource) #define dispobjUnregisterEvent(pNotifier, hNotifierClient, hNotifierResource, hEventClient, hEvent) dispobjUnregisterEvent_DISPATCH(pNotifier, hNotifierClient, hNotifierResource, hEventClient, hEvent) -#define dispobjUnmap(pResource, pCallContext, pCpuMapping) dispobjUnmap_DISPATCH(pResource, pCallContext, pCpuMapping) -#define dispobjControl_Prologue(pDisplayApi, pCallContext, pRsParams) dispobjControl_Prologue_DISPATCH(pDisplayApi, pCallContext, pRsParams) +#define dispobjControlSerialization_Prologue(pResource, pCallContext, pParams) dispobjControlSerialization_Prologue_DISPATCH(pResource, pCallContext, pParams) #define dispobjCanCopy(pResource) dispobjCanCopy_DISPATCH(pResource) -#define dispobjMapTo(pResource, pParams) dispobjMapTo_DISPATCH(pResource, pParams) -#define dispobjAddAdditionalDependants(pClient, pResource, pReference) dispobjAddAdditionalDependants_DISPATCH(pClient, pResource, pReference) #define dispobjPreDestruct(pResource) dispobjPreDestruct_DISPATCH(pResource) -#define dispobjUnmapFrom(pResource, pParams) dispobjUnmapFrom_DISPATCH(pResource, pParams) #define dispobjIsDuplicate(pResource, hMemory, pDuplicate) dispobjIsDuplicate_DISPATCH(pResource, hMemory, pDuplicate) +#define dispobjControlSerialization_Epilogue(pResource, pCallContext, pParams) dispobjControlSerialization_Epilogue_DISPATCH(pResource, pCallContext, pParams) #define dispobjGetNotificationListPtr(pNotifier) dispobjGetNotificationListPtr_DISPATCH(pNotifier) -#define dispobjControl_Epilogue(pDisplayApi, pCallContext, pRsParams) dispobjControl_Epilogue_DISPATCH(pDisplayApi, pCallContext, pRsParams) #define dispobjGetNotificationShare(pNotifier) dispobjGetNotificationShare_DISPATCH(pNotifier) -#define dispobjControlLookup(pResource, pParams, ppEntry) dispobjControlLookup_DISPATCH(pResource, pParams, ppEntry) #define dispobjMap(pResource, pCallContext, pParams, pCpuMapping) dispobjMap_DISPATCH(pResource, pCallContext, pParams, pCpuMapping) #define dispobjGetOrAllocNotifShare(pNotifier, hNotifierClient, hNotifierResource, ppNotifShare) dispobjGetOrAllocNotifShare_DISPATCH(pNotifier, hNotifierClient, hNotifierResource, ppNotifShare) NV_STATUS dispobjConstructHal_IMPL(struct DispObject *pDispObject, struct CALL_CONTEXT *pCallContext, struct RS_RES_ALLOC_PARAMS_INTERNAL *pParams); @@ -614,12 +628,6 @@ return pDispObject->__dispobjCtrlCmdSetRgFliplockProp__(pDispObject, pParams); } -NV_STATUS dispobjCtrlCmdGetRgConnectedLockpin_IMPL(struct DispObject *pDispObject, NV5070_CTRL_CMD_GET_RG_CONNECTED_LOCKPIN_PARAMS *pParams); - -static inline NV_STATUS dispobjCtrlCmdGetRgConnectedLockpin_DISPATCH(struct DispObject *pDispObject, NV5070_CTRL_CMD_GET_RG_CONNECTED_LOCKPIN_PARAMS *pParams) { - return pDispObject->__dispobjCtrlCmdGetRgConnectedLockpin__(pDispObject, pParams); -} - NV_STATUS dispobjCtrlCmdGetRgConnectedLockpinStateless_IMPL(struct DispObject *pDispObject, NV5070_CTRL_GET_RG_CONNECTED_LOCKPIN_STATELESS_PARAMS *pParams); static inline NV_STATUS dispobjCtrlCmdGetRgConnectedLockpinStateless_DISPATCH(struct DispObject *pDispObject, NV5070_CTRL_GET_RG_CONNECTED_LOCKPIN_STATELESS_PARAMS *pParams) { @@ -696,90 +704,98 @@ return pResource->__dispobjShareCallback__(pResource, pInvokingClient, pParentRef, pSharePolicy); } -static inline NV_STATUS dispobjControl_DISPATCH(struct DispObject *pDisplayApi, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { - return pDisplayApi->__dispobjControl__(pDisplayApi, pCallContext, pParams); +static inline NV_STATUS dispobjCheckMemInterUnmap_DISPATCH(struct DispObject *pRmResource, NvBool bSubdeviceHandleProvided) { + return pRmResource->__dispobjCheckMemInterUnmap__(pRmResource, bSubdeviceHandleProvided); +} + +static inline NV_STATUS dispobjMapTo_DISPATCH(struct DispObject *pResource, RS_RES_MAP_TO_PARAMS *pParams) { + return pResource->__dispobjMapTo__(pResource, pParams); } static inline NvBool dispobjAccessCallback_DISPATCH(struct DispObject *pResource, struct RsClient *pInvokingClient, void *pAllocParams, RsAccessRight accessRight) { return pResource->__dispobjAccessCallback__(pResource, pInvokingClient, pAllocParams, accessRight); } -static inline NV_STATUS dispobjGetMemInterMapParams_DISPATCH(struct DispObject *pRmResource, RMRES_MEM_INTER_MAP_PARAMS *pParams) { - return pRmResource->__dispobjGetMemInterMapParams__(pRmResource, pParams); +static inline void dispobjSetNotificationShare_DISPATCH(struct DispObject *pNotifier, struct NotifShare *pNotifShare) { + pNotifier->__dispobjSetNotificationShare__(pNotifier, pNotifShare); } -static inline NV_STATUS dispobjGetMemoryMappingDescriptor_DISPATCH(struct DispObject *pRmResource, struct MEMORY_DESCRIPTOR **ppMemDesc) { - return pRmResource->__dispobjGetMemoryMappingDescriptor__(pRmResource, ppMemDesc); +static inline NvU32 dispobjGetRefCount_DISPATCH(struct DispObject *pResource) { + return pResource->__dispobjGetRefCount__(pResource); } -static inline NV_STATUS dispobjCheckMemInterUnmap_DISPATCH(struct DispObject *pRmResource, NvBool bSubdeviceHandleProvided) { - return pRmResource->__dispobjCheckMemInterUnmap__(pRmResource, bSubdeviceHandleProvided); +static inline void dispobjAddAdditionalDependants_DISPATCH(struct RsClient *pClient, struct DispObject *pResource, RsResourceRef *pReference) { + pResource->__dispobjAddAdditionalDependants__(pClient, pResource, pReference); } -static inline void dispobjSetNotificationShare_DISPATCH(struct DispObject *pNotifier, struct NotifShare *pNotifShare) { - pNotifier->__dispobjSetNotificationShare__(pNotifier, pNotifShare); +static inline NV_STATUS dispobjControl_Prologue_DISPATCH(struct DispObject *pDisplayApi, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pRsParams) { + return pDisplayApi->__dispobjControl_Prologue__(pDisplayApi, pCallContext, pRsParams); } -static inline NV_STATUS dispobjControlFilter_DISPATCH(struct DispObject *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { - return pResource->__dispobjControlFilter__(pResource, pCallContext, pParams); +static inline NV_STATUS dispobjUnmapFrom_DISPATCH(struct DispObject *pResource, RS_RES_UNMAP_FROM_PARAMS *pParams) { + return pResource->__dispobjUnmapFrom__(pResource, pParams); } -static inline NvU32 dispobjGetRefCount_DISPATCH(struct DispObject *pResource) { - return pResource->__dispobjGetRefCount__(pResource); +static inline void dispobjControl_Epilogue_DISPATCH(struct DispObject *pDisplayApi, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pRsParams) { + pDisplayApi->__dispobjControl_Epilogue__(pDisplayApi, pCallContext, pRsParams); } -static inline NV_STATUS dispobjUnregisterEvent_DISPATCH(struct DispObject *pNotifier, NvHandle hNotifierClient, NvHandle hNotifierResource, NvHandle hEventClient, NvHandle hEvent) { - return pNotifier->__dispobjUnregisterEvent__(pNotifier, hNotifierClient, hNotifierResource, hEventClient, hEvent); +static inline NV_STATUS dispobjControlLookup_DISPATCH(struct DispObject *pResource, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams, const struct NVOC_EXPORTED_METHOD_DEF **ppEntry) { + return pResource->__dispobjControlLookup__(pResource, pParams, ppEntry); +} + +static inline NV_STATUS dispobjControl_DISPATCH(struct DispObject *pDisplayApi, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return pDisplayApi->__dispobjControl__(pDisplayApi, pCallContext, pParams); } static inline NV_STATUS dispobjUnmap_DISPATCH(struct DispObject *pResource, struct CALL_CONTEXT *pCallContext, RsCpuMapping *pCpuMapping) { return pResource->__dispobjUnmap__(pResource, pCallContext, pCpuMapping); } -static inline NV_STATUS dispobjControl_Prologue_DISPATCH(struct DispObject *pDisplayApi, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pRsParams) { - return pDisplayApi->__dispobjControl_Prologue__(pDisplayApi, pCallContext, pRsParams); +static inline NV_STATUS dispobjGetMemInterMapParams_DISPATCH(struct DispObject *pRmResource, RMRES_MEM_INTER_MAP_PARAMS *pParams) { + return pRmResource->__dispobjGetMemInterMapParams__(pRmResource, pParams); } -static inline NvBool dispobjCanCopy_DISPATCH(struct DispObject *pResource) { - return pResource->__dispobjCanCopy__(pResource); +static inline NV_STATUS dispobjGetMemoryMappingDescriptor_DISPATCH(struct DispObject *pRmResource, struct MEMORY_DESCRIPTOR **ppMemDesc) { + return pRmResource->__dispobjGetMemoryMappingDescriptor__(pRmResource, ppMemDesc); } -static inline NV_STATUS dispobjMapTo_DISPATCH(struct DispObject *pResource, RS_RES_MAP_TO_PARAMS *pParams) { - return pResource->__dispobjMapTo__(pResource, pParams); +static inline NV_STATUS dispobjControlFilter_DISPATCH(struct DispObject *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return pResource->__dispobjControlFilter__(pResource, pCallContext, pParams); } -static inline void dispobjAddAdditionalDependants_DISPATCH(struct RsClient *pClient, struct DispObject *pResource, RsResourceRef *pReference) { - pResource->__dispobjAddAdditionalDependants__(pClient, pResource, pReference); +static inline NV_STATUS dispobjUnregisterEvent_DISPATCH(struct DispObject *pNotifier, NvHandle hNotifierClient, NvHandle hNotifierResource, NvHandle hEventClient, NvHandle hEvent) { + return pNotifier->__dispobjUnregisterEvent__(pNotifier, hNotifierClient, hNotifierResource, hEventClient, hEvent); } -static inline void dispobjPreDestruct_DISPATCH(struct DispObject *pResource) { - pResource->__dispobjPreDestruct__(pResource); +static inline NV_STATUS dispobjControlSerialization_Prologue_DISPATCH(struct DispObject *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return pResource->__dispobjControlSerialization_Prologue__(pResource, pCallContext, pParams); } -static inline NV_STATUS dispobjUnmapFrom_DISPATCH(struct DispObject *pResource, RS_RES_UNMAP_FROM_PARAMS *pParams) { - return pResource->__dispobjUnmapFrom__(pResource, pParams); +static inline NvBool dispobjCanCopy_DISPATCH(struct DispObject *pResource) { + return pResource->__dispobjCanCopy__(pResource); +} + +static inline void dispobjPreDestruct_DISPATCH(struct DispObject *pResource) { + pResource->__dispobjPreDestruct__(pResource); } static inline NV_STATUS dispobjIsDuplicate_DISPATCH(struct DispObject *pResource, NvHandle hMemory, NvBool *pDuplicate) { return pResource->__dispobjIsDuplicate__(pResource, hMemory, pDuplicate); } -static inline PEVENTNOTIFICATION *dispobjGetNotificationListPtr_DISPATCH(struct DispObject *pNotifier) { - return pNotifier->__dispobjGetNotificationListPtr__(pNotifier); +static inline void dispobjControlSerialization_Epilogue_DISPATCH(struct DispObject *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + pResource->__dispobjControlSerialization_Epilogue__(pResource, pCallContext, pParams); } -static inline void dispobjControl_Epilogue_DISPATCH(struct DispObject *pDisplayApi, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pRsParams) { - pDisplayApi->__dispobjControl_Epilogue__(pDisplayApi, pCallContext, pRsParams); +static inline PEVENTNOTIFICATION *dispobjGetNotificationListPtr_DISPATCH(struct DispObject *pNotifier) { + return pNotifier->__dispobjGetNotificationListPtr__(pNotifier); } static inline struct NotifShare *dispobjGetNotificationShare_DISPATCH(struct DispObject *pNotifier) { return pNotifier->__dispobjGetNotificationShare__(pNotifier); } -static inline NV_STATUS dispobjControlLookup_DISPATCH(struct DispObject *pResource, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams, const struct NVOC_EXPORTED_METHOD_DEF **ppEntry) { - return pResource->__dispobjControlLookup__(pResource, pParams, ppEntry); -} - static inline NV_STATUS dispobjMap_DISPATCH(struct DispObject *pResource, struct CALL_CONTEXT *pCallContext, RS_CPU_MAP_PARAMS *pParams, RsCpuMapping *pCpuMapping) { return pResource->__dispobjMap__(pResource, pCallContext, pParams, pCpuMapping); } @@ -853,27 +869,29 @@ NV_STATUS (*__nvdispapiCtrlCmdGetLockpinsCaps__)(struct NvDispApi *, NVC370_CTRL_GET_LOCKPINS_CAPS_PARAMS *); NV_STATUS (*__nvdispapiCtrlCmdSetForceModeswitchFlagsOverrides__)(struct NvDispApi *, NVC370_CTRL_CMD_SET_FORCE_MODESWITCH_FLAGS_OVERRIDES_PARAMS *); NvBool (*__nvdispapiShareCallback__)(struct NvDispApi *, struct RsClient *, struct RsResourceRef *, RS_SHARE_POLICY *); - NV_STATUS (*__nvdispapiControl__)(struct NvDispApi *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); + NV_STATUS (*__nvdispapiCheckMemInterUnmap__)(struct NvDispApi *, NvBool); + NV_STATUS (*__nvdispapiMapTo__)(struct NvDispApi *, RS_RES_MAP_TO_PARAMS *); NvBool (*__nvdispapiAccessCallback__)(struct NvDispApi *, struct RsClient *, void *, RsAccessRight); + void (*__nvdispapiSetNotificationShare__)(struct NvDispApi *, struct NotifShare *); + NvU32 (*__nvdispapiGetRefCount__)(struct NvDispApi *); + void (*__nvdispapiAddAdditionalDependants__)(struct RsClient *, struct NvDispApi *, RsResourceRef *); + NV_STATUS (*__nvdispapiControl_Prologue__)(struct NvDispApi *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); + NV_STATUS (*__nvdispapiUnmapFrom__)(struct NvDispApi *, RS_RES_UNMAP_FROM_PARAMS *); + void (*__nvdispapiControl_Epilogue__)(struct NvDispApi *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); + NV_STATUS (*__nvdispapiControlLookup__)(struct NvDispApi *, struct RS_RES_CONTROL_PARAMS_INTERNAL *, const struct NVOC_EXPORTED_METHOD_DEF **); + NV_STATUS (*__nvdispapiControl__)(struct NvDispApi *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); + NV_STATUS (*__nvdispapiUnmap__)(struct NvDispApi *, struct CALL_CONTEXT *, RsCpuMapping *); NV_STATUS (*__nvdispapiGetMemInterMapParams__)(struct NvDispApi *, RMRES_MEM_INTER_MAP_PARAMS *); NV_STATUS (*__nvdispapiGetMemoryMappingDescriptor__)(struct NvDispApi *, struct MEMORY_DESCRIPTOR **); - NV_STATUS (*__nvdispapiCheckMemInterUnmap__)(struct NvDispApi *, NvBool); - void (*__nvdispapiSetNotificationShare__)(struct NvDispApi *, struct NotifShare *); NV_STATUS (*__nvdispapiControlFilter__)(struct NvDispApi *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); - NvU32 (*__nvdispapiGetRefCount__)(struct NvDispApi *); NV_STATUS (*__nvdispapiUnregisterEvent__)(struct NvDispApi *, NvHandle, NvHandle, NvHandle, NvHandle); - NV_STATUS (*__nvdispapiUnmap__)(struct NvDispApi *, struct CALL_CONTEXT *, RsCpuMapping *); - NV_STATUS (*__nvdispapiControl_Prologue__)(struct NvDispApi *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); + NV_STATUS (*__nvdispapiControlSerialization_Prologue__)(struct NvDispApi *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); NvBool (*__nvdispapiCanCopy__)(struct NvDispApi *); - NV_STATUS (*__nvdispapiMapTo__)(struct NvDispApi *, RS_RES_MAP_TO_PARAMS *); - void (*__nvdispapiAddAdditionalDependants__)(struct RsClient *, struct NvDispApi *, RsResourceRef *); void (*__nvdispapiPreDestruct__)(struct NvDispApi *); - NV_STATUS (*__nvdispapiUnmapFrom__)(struct NvDispApi *, RS_RES_UNMAP_FROM_PARAMS *); NV_STATUS (*__nvdispapiIsDuplicate__)(struct NvDispApi *, NvHandle, NvBool *); + void (*__nvdispapiControlSerialization_Epilogue__)(struct NvDispApi *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); PEVENTNOTIFICATION *(*__nvdispapiGetNotificationListPtr__)(struct NvDispApi *); - void (*__nvdispapiControl_Epilogue__)(struct NvDispApi *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); struct NotifShare *(*__nvdispapiGetNotificationShare__)(struct NvDispApi *); - NV_STATUS (*__nvdispapiControlLookup__)(struct NvDispApi *, struct RS_RES_CONTROL_PARAMS_INTERNAL *, const struct NVOC_EXPORTED_METHOD_DEF **); NV_STATUS (*__nvdispapiMap__)(struct NvDispApi *, struct CALL_CONTEXT *, RS_CPU_MAP_PARAMS *, RsCpuMapping *); NV_STATUS (*__nvdispapiGetOrAllocNotifShare__)(struct NvDispApi *, NvHandle, NvHandle, struct NotifShare **); }; @@ -914,27 +932,29 @@ #define nvdispapiCtrlCmdGetLockpinsCaps(pNvDispApi, pParams) nvdispapiCtrlCmdGetLockpinsCaps_DISPATCH(pNvDispApi, pParams) #define nvdispapiCtrlCmdSetForceModeswitchFlagsOverrides(pNvDispApi, pParams) nvdispapiCtrlCmdSetForceModeswitchFlagsOverrides_DISPATCH(pNvDispApi, pParams) #define nvdispapiShareCallback(pResource, pInvokingClient, pParentRef, pSharePolicy) nvdispapiShareCallback_DISPATCH(pResource, pInvokingClient, pParentRef, pSharePolicy) -#define nvdispapiControl(pDisplayApi, pCallContext, pParams) nvdispapiControl_DISPATCH(pDisplayApi, pCallContext, pParams) +#define nvdispapiCheckMemInterUnmap(pRmResource, bSubdeviceHandleProvided) nvdispapiCheckMemInterUnmap_DISPATCH(pRmResource, bSubdeviceHandleProvided) +#define nvdispapiMapTo(pResource, pParams) nvdispapiMapTo_DISPATCH(pResource, pParams) #define nvdispapiAccessCallback(pResource, pInvokingClient, pAllocParams, accessRight) nvdispapiAccessCallback_DISPATCH(pResource, pInvokingClient, pAllocParams, accessRight) +#define nvdispapiSetNotificationShare(pNotifier, pNotifShare) nvdispapiSetNotificationShare_DISPATCH(pNotifier, pNotifShare) +#define nvdispapiGetRefCount(pResource) nvdispapiGetRefCount_DISPATCH(pResource) +#define nvdispapiAddAdditionalDependants(pClient, pResource, pReference) nvdispapiAddAdditionalDependants_DISPATCH(pClient, pResource, pReference) +#define nvdispapiControl_Prologue(pDisplayApi, pCallContext, pRsParams) nvdispapiControl_Prologue_DISPATCH(pDisplayApi, pCallContext, pRsParams) +#define nvdispapiUnmapFrom(pResource, pParams) nvdispapiUnmapFrom_DISPATCH(pResource, pParams) +#define nvdispapiControl_Epilogue(pDisplayApi, pCallContext, pRsParams) nvdispapiControl_Epilogue_DISPATCH(pDisplayApi, pCallContext, pRsParams) +#define nvdispapiControlLookup(pResource, pParams, ppEntry) nvdispapiControlLookup_DISPATCH(pResource, pParams, ppEntry) +#define nvdispapiControl(pDisplayApi, pCallContext, pParams) nvdispapiControl_DISPATCH(pDisplayApi, pCallContext, pParams) +#define nvdispapiUnmap(pResource, pCallContext, pCpuMapping) nvdispapiUnmap_DISPATCH(pResource, pCallContext, pCpuMapping) #define nvdispapiGetMemInterMapParams(pRmResource, pParams) nvdispapiGetMemInterMapParams_DISPATCH(pRmResource, pParams) #define nvdispapiGetMemoryMappingDescriptor(pRmResource, ppMemDesc) nvdispapiGetMemoryMappingDescriptor_DISPATCH(pRmResource, ppMemDesc) -#define nvdispapiCheckMemInterUnmap(pRmResource, bSubdeviceHandleProvided) nvdispapiCheckMemInterUnmap_DISPATCH(pRmResource, bSubdeviceHandleProvided) -#define nvdispapiSetNotificationShare(pNotifier, pNotifShare) nvdispapiSetNotificationShare_DISPATCH(pNotifier, pNotifShare) #define nvdispapiControlFilter(pResource, pCallContext, pParams) nvdispapiControlFilter_DISPATCH(pResource, pCallContext, pParams) -#define nvdispapiGetRefCount(pResource) nvdispapiGetRefCount_DISPATCH(pResource) #define nvdispapiUnregisterEvent(pNotifier, hNotifierClient, hNotifierResource, hEventClient, hEvent) nvdispapiUnregisterEvent_DISPATCH(pNotifier, hNotifierClient, hNotifierResource, hEventClient, hEvent) -#define nvdispapiUnmap(pResource, pCallContext, pCpuMapping) nvdispapiUnmap_DISPATCH(pResource, pCallContext, pCpuMapping) -#define nvdispapiControl_Prologue(pDisplayApi, pCallContext, pRsParams) nvdispapiControl_Prologue_DISPATCH(pDisplayApi, pCallContext, pRsParams) +#define nvdispapiControlSerialization_Prologue(pResource, pCallContext, pParams) nvdispapiControlSerialization_Prologue_DISPATCH(pResource, pCallContext, pParams) #define nvdispapiCanCopy(pResource) nvdispapiCanCopy_DISPATCH(pResource) -#define nvdispapiMapTo(pResource, pParams) nvdispapiMapTo_DISPATCH(pResource, pParams) -#define nvdispapiAddAdditionalDependants(pClient, pResource, pReference) nvdispapiAddAdditionalDependants_DISPATCH(pClient, pResource, pReference) #define nvdispapiPreDestruct(pResource) nvdispapiPreDestruct_DISPATCH(pResource) -#define nvdispapiUnmapFrom(pResource, pParams) nvdispapiUnmapFrom_DISPATCH(pResource, pParams) #define nvdispapiIsDuplicate(pResource, hMemory, pDuplicate) nvdispapiIsDuplicate_DISPATCH(pResource, hMemory, pDuplicate) +#define nvdispapiControlSerialization_Epilogue(pResource, pCallContext, pParams) nvdispapiControlSerialization_Epilogue_DISPATCH(pResource, pCallContext, pParams) #define nvdispapiGetNotificationListPtr(pNotifier) nvdispapiGetNotificationListPtr_DISPATCH(pNotifier) -#define nvdispapiControl_Epilogue(pDisplayApi, pCallContext, pRsParams) nvdispapiControl_Epilogue_DISPATCH(pDisplayApi, pCallContext, pRsParams) #define nvdispapiGetNotificationShare(pNotifier) nvdispapiGetNotificationShare_DISPATCH(pNotifier) -#define nvdispapiControlLookup(pResource, pParams, ppEntry) nvdispapiControlLookup_DISPATCH(pResource, pParams, ppEntry) #define nvdispapiMap(pResource, pCallContext, pParams, pCpuMapping) nvdispapiMap_DISPATCH(pResource, pCallContext, pParams, pCpuMapping) #define nvdispapiGetOrAllocNotifShare(pNotifier, hNotifierClient, hNotifierResource, ppNotifShare) nvdispapiGetOrAllocNotifShare_DISPATCH(pNotifier, hNotifierClient, hNotifierResource, ppNotifShare) NV_STATUS nvdispapiCtrlCmdIdleChannel_IMPL(struct NvDispApi *pNvDispApi, NVC370_CTRL_IDLE_CHANNEL_PARAMS *pParams); @@ -983,90 +1003,98 @@ return pResource->__nvdispapiShareCallback__(pResource, pInvokingClient, pParentRef, pSharePolicy); } -static inline NV_STATUS nvdispapiControl_DISPATCH(struct NvDispApi *pDisplayApi, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { - return pDisplayApi->__nvdispapiControl__(pDisplayApi, pCallContext, pParams); +static inline NV_STATUS nvdispapiCheckMemInterUnmap_DISPATCH(struct NvDispApi *pRmResource, NvBool bSubdeviceHandleProvided) { + return pRmResource->__nvdispapiCheckMemInterUnmap__(pRmResource, bSubdeviceHandleProvided); +} + +static inline NV_STATUS nvdispapiMapTo_DISPATCH(struct NvDispApi *pResource, RS_RES_MAP_TO_PARAMS *pParams) { + return pResource->__nvdispapiMapTo__(pResource, pParams); } static inline NvBool nvdispapiAccessCallback_DISPATCH(struct NvDispApi *pResource, struct RsClient *pInvokingClient, void *pAllocParams, RsAccessRight accessRight) { return pResource->__nvdispapiAccessCallback__(pResource, pInvokingClient, pAllocParams, accessRight); } -static inline NV_STATUS nvdispapiGetMemInterMapParams_DISPATCH(struct NvDispApi *pRmResource, RMRES_MEM_INTER_MAP_PARAMS *pParams) { - return pRmResource->__nvdispapiGetMemInterMapParams__(pRmResource, pParams); +static inline void nvdispapiSetNotificationShare_DISPATCH(struct NvDispApi *pNotifier, struct NotifShare *pNotifShare) { + pNotifier->__nvdispapiSetNotificationShare__(pNotifier, pNotifShare); } -static inline NV_STATUS nvdispapiGetMemoryMappingDescriptor_DISPATCH(struct NvDispApi *pRmResource, struct MEMORY_DESCRIPTOR **ppMemDesc) { - return pRmResource->__nvdispapiGetMemoryMappingDescriptor__(pRmResource, ppMemDesc); +static inline NvU32 nvdispapiGetRefCount_DISPATCH(struct NvDispApi *pResource) { + return pResource->__nvdispapiGetRefCount__(pResource); } -static inline NV_STATUS nvdispapiCheckMemInterUnmap_DISPATCH(struct NvDispApi *pRmResource, NvBool bSubdeviceHandleProvided) { - return pRmResource->__nvdispapiCheckMemInterUnmap__(pRmResource, bSubdeviceHandleProvided); +static inline void nvdispapiAddAdditionalDependants_DISPATCH(struct RsClient *pClient, struct NvDispApi *pResource, RsResourceRef *pReference) { + pResource->__nvdispapiAddAdditionalDependants__(pClient, pResource, pReference); } -static inline void nvdispapiSetNotificationShare_DISPATCH(struct NvDispApi *pNotifier, struct NotifShare *pNotifShare) { - pNotifier->__nvdispapiSetNotificationShare__(pNotifier, pNotifShare); +static inline NV_STATUS nvdispapiControl_Prologue_DISPATCH(struct NvDispApi *pDisplayApi, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pRsParams) { + return pDisplayApi->__nvdispapiControl_Prologue__(pDisplayApi, pCallContext, pRsParams); } -static inline NV_STATUS nvdispapiControlFilter_DISPATCH(struct NvDispApi *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { - return pResource->__nvdispapiControlFilter__(pResource, pCallContext, pParams); +static inline NV_STATUS nvdispapiUnmapFrom_DISPATCH(struct NvDispApi *pResource, RS_RES_UNMAP_FROM_PARAMS *pParams) { + return pResource->__nvdispapiUnmapFrom__(pResource, pParams); } -static inline NvU32 nvdispapiGetRefCount_DISPATCH(struct NvDispApi *pResource) { - return pResource->__nvdispapiGetRefCount__(pResource); +static inline void nvdispapiControl_Epilogue_DISPATCH(struct NvDispApi *pDisplayApi, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pRsParams) { + pDisplayApi->__nvdispapiControl_Epilogue__(pDisplayApi, pCallContext, pRsParams); } -static inline NV_STATUS nvdispapiUnregisterEvent_DISPATCH(struct NvDispApi *pNotifier, NvHandle hNotifierClient, NvHandle hNotifierResource, NvHandle hEventClient, NvHandle hEvent) { - return pNotifier->__nvdispapiUnregisterEvent__(pNotifier, hNotifierClient, hNotifierResource, hEventClient, hEvent); +static inline NV_STATUS nvdispapiControlLookup_DISPATCH(struct NvDispApi *pResource, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams, const struct NVOC_EXPORTED_METHOD_DEF **ppEntry) { + return pResource->__nvdispapiControlLookup__(pResource, pParams, ppEntry); +} + +static inline NV_STATUS nvdispapiControl_DISPATCH(struct NvDispApi *pDisplayApi, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return pDisplayApi->__nvdispapiControl__(pDisplayApi, pCallContext, pParams); } static inline NV_STATUS nvdispapiUnmap_DISPATCH(struct NvDispApi *pResource, struct CALL_CONTEXT *pCallContext, RsCpuMapping *pCpuMapping) { return pResource->__nvdispapiUnmap__(pResource, pCallContext, pCpuMapping); } -static inline NV_STATUS nvdispapiControl_Prologue_DISPATCH(struct NvDispApi *pDisplayApi, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pRsParams) { - return pDisplayApi->__nvdispapiControl_Prologue__(pDisplayApi, pCallContext, pRsParams); +static inline NV_STATUS nvdispapiGetMemInterMapParams_DISPATCH(struct NvDispApi *pRmResource, RMRES_MEM_INTER_MAP_PARAMS *pParams) { + return pRmResource->__nvdispapiGetMemInterMapParams__(pRmResource, pParams); } -static inline NvBool nvdispapiCanCopy_DISPATCH(struct NvDispApi *pResource) { - return pResource->__nvdispapiCanCopy__(pResource); +static inline NV_STATUS nvdispapiGetMemoryMappingDescriptor_DISPATCH(struct NvDispApi *pRmResource, struct MEMORY_DESCRIPTOR **ppMemDesc) { + return pRmResource->__nvdispapiGetMemoryMappingDescriptor__(pRmResource, ppMemDesc); } -static inline NV_STATUS nvdispapiMapTo_DISPATCH(struct NvDispApi *pResource, RS_RES_MAP_TO_PARAMS *pParams) { - return pResource->__nvdispapiMapTo__(pResource, pParams); +static inline NV_STATUS nvdispapiControlFilter_DISPATCH(struct NvDispApi *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return pResource->__nvdispapiControlFilter__(pResource, pCallContext, pParams); } -static inline void nvdispapiAddAdditionalDependants_DISPATCH(struct RsClient *pClient, struct NvDispApi *pResource, RsResourceRef *pReference) { - pResource->__nvdispapiAddAdditionalDependants__(pClient, pResource, pReference); +static inline NV_STATUS nvdispapiUnregisterEvent_DISPATCH(struct NvDispApi *pNotifier, NvHandle hNotifierClient, NvHandle hNotifierResource, NvHandle hEventClient, NvHandle hEvent) { + return pNotifier->__nvdispapiUnregisterEvent__(pNotifier, hNotifierClient, hNotifierResource, hEventClient, hEvent); } -static inline void nvdispapiPreDestruct_DISPATCH(struct NvDispApi *pResource) { - pResource->__nvdispapiPreDestruct__(pResource); +static inline NV_STATUS nvdispapiControlSerialization_Prologue_DISPATCH(struct NvDispApi *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return pResource->__nvdispapiControlSerialization_Prologue__(pResource, pCallContext, pParams); } -static inline NV_STATUS nvdispapiUnmapFrom_DISPATCH(struct NvDispApi *pResource, RS_RES_UNMAP_FROM_PARAMS *pParams) { - return pResource->__nvdispapiUnmapFrom__(pResource, pParams); +static inline NvBool nvdispapiCanCopy_DISPATCH(struct NvDispApi *pResource) { + return pResource->__nvdispapiCanCopy__(pResource); +} + +static inline void nvdispapiPreDestruct_DISPATCH(struct NvDispApi *pResource) { + pResource->__nvdispapiPreDestruct__(pResource); } static inline NV_STATUS nvdispapiIsDuplicate_DISPATCH(struct NvDispApi *pResource, NvHandle hMemory, NvBool *pDuplicate) { return pResource->__nvdispapiIsDuplicate__(pResource, hMemory, pDuplicate); } -static inline PEVENTNOTIFICATION *nvdispapiGetNotificationListPtr_DISPATCH(struct NvDispApi *pNotifier) { - return pNotifier->__nvdispapiGetNotificationListPtr__(pNotifier); +static inline void nvdispapiControlSerialization_Epilogue_DISPATCH(struct NvDispApi *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + pResource->__nvdispapiControlSerialization_Epilogue__(pResource, pCallContext, pParams); } -static inline void nvdispapiControl_Epilogue_DISPATCH(struct NvDispApi *pDisplayApi, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pRsParams) { - pDisplayApi->__nvdispapiControl_Epilogue__(pDisplayApi, pCallContext, pRsParams); +static inline PEVENTNOTIFICATION *nvdispapiGetNotificationListPtr_DISPATCH(struct NvDispApi *pNotifier) { + return pNotifier->__nvdispapiGetNotificationListPtr__(pNotifier); } static inline struct NotifShare *nvdispapiGetNotificationShare_DISPATCH(struct NvDispApi *pNotifier) { return pNotifier->__nvdispapiGetNotificationShare__(pNotifier); } -static inline NV_STATUS nvdispapiControlLookup_DISPATCH(struct NvDispApi *pResource, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams, const struct NVOC_EXPORTED_METHOD_DEF **ppEntry) { - return pResource->__nvdispapiControlLookup__(pResource, pParams, ppEntry); -} - static inline NV_STATUS nvdispapiMap_DISPATCH(struct NvDispApi *pResource, struct CALL_CONTEXT *pCallContext, RS_CPU_MAP_PARAMS *pParams, RsCpuMapping *pCpuMapping) { return pResource->__nvdispapiMap__(pResource, pCallContext, pParams, pCpuMapping); } @@ -1112,27 +1140,29 @@ NV_STATUS (*__dispswobjCtrlCmdVideoAdaptiveRefreshRate__)(struct DispSwObj *, NVC372_CTRL_CMD_VIDEO_ADAPTIVE_REFRESH_RATE_PARAMS *); NV_STATUS (*__dispswobjCtrlCmdGetActiveViewportPointIn__)(struct DispSwObj *, NVC372_CTRL_CMD_GET_ACTIVE_VIEWPORT_POINT_IN_PARAMS *); NvBool (*__dispswobjShareCallback__)(struct DispSwObj *, struct RsClient *, struct RsResourceRef *, RS_SHARE_POLICY *); - NV_STATUS (*__dispswobjControl__)(struct DispSwObj *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); + NV_STATUS (*__dispswobjCheckMemInterUnmap__)(struct DispSwObj *, NvBool); + NV_STATUS (*__dispswobjMapTo__)(struct DispSwObj *, RS_RES_MAP_TO_PARAMS *); NvBool (*__dispswobjAccessCallback__)(struct DispSwObj *, struct RsClient *, void *, RsAccessRight); + void (*__dispswobjSetNotificationShare__)(struct DispSwObj *, struct NotifShare *); + NvU32 (*__dispswobjGetRefCount__)(struct DispSwObj *); + void (*__dispswobjAddAdditionalDependants__)(struct RsClient *, struct DispSwObj *, RsResourceRef *); + NV_STATUS (*__dispswobjControl_Prologue__)(struct DispSwObj *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); + NV_STATUS (*__dispswobjUnmapFrom__)(struct DispSwObj *, RS_RES_UNMAP_FROM_PARAMS *); + void (*__dispswobjControl_Epilogue__)(struct DispSwObj *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); + NV_STATUS (*__dispswobjControlLookup__)(struct DispSwObj *, struct RS_RES_CONTROL_PARAMS_INTERNAL *, const struct NVOC_EXPORTED_METHOD_DEF **); + NV_STATUS (*__dispswobjControl__)(struct DispSwObj *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); + NV_STATUS (*__dispswobjUnmap__)(struct DispSwObj *, struct CALL_CONTEXT *, RsCpuMapping *); NV_STATUS (*__dispswobjGetMemInterMapParams__)(struct DispSwObj *, RMRES_MEM_INTER_MAP_PARAMS *); NV_STATUS (*__dispswobjGetMemoryMappingDescriptor__)(struct DispSwObj *, struct MEMORY_DESCRIPTOR **); - NV_STATUS (*__dispswobjCheckMemInterUnmap__)(struct DispSwObj *, NvBool); - void (*__dispswobjSetNotificationShare__)(struct DispSwObj *, struct NotifShare *); NV_STATUS (*__dispswobjControlFilter__)(struct DispSwObj *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); - NvU32 (*__dispswobjGetRefCount__)(struct DispSwObj *); NV_STATUS (*__dispswobjUnregisterEvent__)(struct DispSwObj *, NvHandle, NvHandle, NvHandle, NvHandle); - NV_STATUS (*__dispswobjUnmap__)(struct DispSwObj *, struct CALL_CONTEXT *, RsCpuMapping *); - NV_STATUS (*__dispswobjControl_Prologue__)(struct DispSwObj *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); + NV_STATUS (*__dispswobjControlSerialization_Prologue__)(struct DispSwObj *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); NvBool (*__dispswobjCanCopy__)(struct DispSwObj *); - NV_STATUS (*__dispswobjMapTo__)(struct DispSwObj *, RS_RES_MAP_TO_PARAMS *); - void (*__dispswobjAddAdditionalDependants__)(struct RsClient *, struct DispSwObj *, RsResourceRef *); void (*__dispswobjPreDestruct__)(struct DispSwObj *); - NV_STATUS (*__dispswobjUnmapFrom__)(struct DispSwObj *, RS_RES_UNMAP_FROM_PARAMS *); NV_STATUS (*__dispswobjIsDuplicate__)(struct DispSwObj *, NvHandle, NvBool *); + void (*__dispswobjControlSerialization_Epilogue__)(struct DispSwObj *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); PEVENTNOTIFICATION *(*__dispswobjGetNotificationListPtr__)(struct DispSwObj *); - void (*__dispswobjControl_Epilogue__)(struct DispSwObj *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); struct NotifShare *(*__dispswobjGetNotificationShare__)(struct DispSwObj *); - NV_STATUS (*__dispswobjControlLookup__)(struct DispSwObj *, struct RS_RES_CONTROL_PARAMS_INTERNAL *, const struct NVOC_EXPORTED_METHOD_DEF **); NV_STATUS (*__dispswobjMap__)(struct DispSwObj *, struct CALL_CONTEXT *, RS_CPU_MAP_PARAMS *, RsCpuMapping *); NV_STATUS (*__dispswobjGetOrAllocNotifShare__)(struct DispSwObj *, NvHandle, NvHandle, struct NotifShare **); }; @@ -1170,27 +1200,29 @@ #define dispswobjCtrlCmdVideoAdaptiveRefreshRate(pDispSwObj, pParams) dispswobjCtrlCmdVideoAdaptiveRefreshRate_DISPATCH(pDispSwObj, pParams) #define dispswobjCtrlCmdGetActiveViewportPointIn(pDispSwObj, pParams) dispswobjCtrlCmdGetActiveViewportPointIn_DISPATCH(pDispSwObj, pParams) #define dispswobjShareCallback(pResource, pInvokingClient, pParentRef, pSharePolicy) dispswobjShareCallback_DISPATCH(pResource, pInvokingClient, pParentRef, pSharePolicy) -#define dispswobjControl(pDisplayApi, pCallContext, pParams) dispswobjControl_DISPATCH(pDisplayApi, pCallContext, pParams) +#define dispswobjCheckMemInterUnmap(pRmResource, bSubdeviceHandleProvided) dispswobjCheckMemInterUnmap_DISPATCH(pRmResource, bSubdeviceHandleProvided) +#define dispswobjMapTo(pResource, pParams) dispswobjMapTo_DISPATCH(pResource, pParams) #define dispswobjAccessCallback(pResource, pInvokingClient, pAllocParams, accessRight) dispswobjAccessCallback_DISPATCH(pResource, pInvokingClient, pAllocParams, accessRight) +#define dispswobjSetNotificationShare(pNotifier, pNotifShare) dispswobjSetNotificationShare_DISPATCH(pNotifier, pNotifShare) +#define dispswobjGetRefCount(pResource) dispswobjGetRefCount_DISPATCH(pResource) +#define dispswobjAddAdditionalDependants(pClient, pResource, pReference) dispswobjAddAdditionalDependants_DISPATCH(pClient, pResource, pReference) +#define dispswobjControl_Prologue(pDisplayApi, pCallContext, pRsParams) dispswobjControl_Prologue_DISPATCH(pDisplayApi, pCallContext, pRsParams) +#define dispswobjUnmapFrom(pResource, pParams) dispswobjUnmapFrom_DISPATCH(pResource, pParams) +#define dispswobjControl_Epilogue(pDisplayApi, pCallContext, pRsParams) dispswobjControl_Epilogue_DISPATCH(pDisplayApi, pCallContext, pRsParams) +#define dispswobjControlLookup(pResource, pParams, ppEntry) dispswobjControlLookup_DISPATCH(pResource, pParams, ppEntry) +#define dispswobjControl(pDisplayApi, pCallContext, pParams) dispswobjControl_DISPATCH(pDisplayApi, pCallContext, pParams) +#define dispswobjUnmap(pResource, pCallContext, pCpuMapping) dispswobjUnmap_DISPATCH(pResource, pCallContext, pCpuMapping) #define dispswobjGetMemInterMapParams(pRmResource, pParams) dispswobjGetMemInterMapParams_DISPATCH(pRmResource, pParams) #define dispswobjGetMemoryMappingDescriptor(pRmResource, ppMemDesc) dispswobjGetMemoryMappingDescriptor_DISPATCH(pRmResource, ppMemDesc) -#define dispswobjCheckMemInterUnmap(pRmResource, bSubdeviceHandleProvided) dispswobjCheckMemInterUnmap_DISPATCH(pRmResource, bSubdeviceHandleProvided) -#define dispswobjSetNotificationShare(pNotifier, pNotifShare) dispswobjSetNotificationShare_DISPATCH(pNotifier, pNotifShare) #define dispswobjControlFilter(pResource, pCallContext, pParams) dispswobjControlFilter_DISPATCH(pResource, pCallContext, pParams) -#define dispswobjGetRefCount(pResource) dispswobjGetRefCount_DISPATCH(pResource) #define dispswobjUnregisterEvent(pNotifier, hNotifierClient, hNotifierResource, hEventClient, hEvent) dispswobjUnregisterEvent_DISPATCH(pNotifier, hNotifierClient, hNotifierResource, hEventClient, hEvent) -#define dispswobjUnmap(pResource, pCallContext, pCpuMapping) dispswobjUnmap_DISPATCH(pResource, pCallContext, pCpuMapping) -#define dispswobjControl_Prologue(pDisplayApi, pCallContext, pRsParams) dispswobjControl_Prologue_DISPATCH(pDisplayApi, pCallContext, pRsParams) +#define dispswobjControlSerialization_Prologue(pResource, pCallContext, pParams) dispswobjControlSerialization_Prologue_DISPATCH(pResource, pCallContext, pParams) #define dispswobjCanCopy(pResource) dispswobjCanCopy_DISPATCH(pResource) -#define dispswobjMapTo(pResource, pParams) dispswobjMapTo_DISPATCH(pResource, pParams) -#define dispswobjAddAdditionalDependants(pClient, pResource, pReference) dispswobjAddAdditionalDependants_DISPATCH(pClient, pResource, pReference) #define dispswobjPreDestruct(pResource) dispswobjPreDestruct_DISPATCH(pResource) -#define dispswobjUnmapFrom(pResource, pParams) dispswobjUnmapFrom_DISPATCH(pResource, pParams) #define dispswobjIsDuplicate(pResource, hMemory, pDuplicate) dispswobjIsDuplicate_DISPATCH(pResource, hMemory, pDuplicate) +#define dispswobjControlSerialization_Epilogue(pResource, pCallContext, pParams) dispswobjControlSerialization_Epilogue_DISPATCH(pResource, pCallContext, pParams) #define dispswobjGetNotificationListPtr(pNotifier) dispswobjGetNotificationListPtr_DISPATCH(pNotifier) -#define dispswobjControl_Epilogue(pDisplayApi, pCallContext, pRsParams) dispswobjControl_Epilogue_DISPATCH(pDisplayApi, pCallContext, pRsParams) #define dispswobjGetNotificationShare(pNotifier) dispswobjGetNotificationShare_DISPATCH(pNotifier) -#define dispswobjControlLookup(pResource, pParams, ppEntry) dispswobjControlLookup_DISPATCH(pResource, pParams, ppEntry) #define dispswobjMap(pResource, pCallContext, pParams, pCpuMapping) dispswobjMap_DISPATCH(pResource, pCallContext, pParams, pCpuMapping) #define dispswobjGetOrAllocNotifShare(pNotifier, hNotifierClient, hNotifierResource, ppNotifShare) dispswobjGetOrAllocNotifShare_DISPATCH(pNotifier, hNotifierClient, hNotifierResource, ppNotifShare) NV_STATUS dispswobjCtrlCmdIsModePossible_IMPL(struct DispSwObj *pDispSwObj, NVC372_CTRL_IS_MODE_POSSIBLE_PARAMS *pParams); @@ -1221,90 +1253,98 @@ return pResource->__dispswobjShareCallback__(pResource, pInvokingClient, pParentRef, pSharePolicy); } -static inline NV_STATUS dispswobjControl_DISPATCH(struct DispSwObj *pDisplayApi, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { - return pDisplayApi->__dispswobjControl__(pDisplayApi, pCallContext, pParams); +static inline NV_STATUS dispswobjCheckMemInterUnmap_DISPATCH(struct DispSwObj *pRmResource, NvBool bSubdeviceHandleProvided) { + return pRmResource->__dispswobjCheckMemInterUnmap__(pRmResource, bSubdeviceHandleProvided); +} + +static inline NV_STATUS dispswobjMapTo_DISPATCH(struct DispSwObj *pResource, RS_RES_MAP_TO_PARAMS *pParams) { + return pResource->__dispswobjMapTo__(pResource, pParams); } static inline NvBool dispswobjAccessCallback_DISPATCH(struct DispSwObj *pResource, struct RsClient *pInvokingClient, void *pAllocParams, RsAccessRight accessRight) { return pResource->__dispswobjAccessCallback__(pResource, pInvokingClient, pAllocParams, accessRight); } -static inline NV_STATUS dispswobjGetMemInterMapParams_DISPATCH(struct DispSwObj *pRmResource, RMRES_MEM_INTER_MAP_PARAMS *pParams) { - return pRmResource->__dispswobjGetMemInterMapParams__(pRmResource, pParams); +static inline void dispswobjSetNotificationShare_DISPATCH(struct DispSwObj *pNotifier, struct NotifShare *pNotifShare) { + pNotifier->__dispswobjSetNotificationShare__(pNotifier, pNotifShare); } -static inline NV_STATUS dispswobjGetMemoryMappingDescriptor_DISPATCH(struct DispSwObj *pRmResource, struct MEMORY_DESCRIPTOR **ppMemDesc) { - return pRmResource->__dispswobjGetMemoryMappingDescriptor__(pRmResource, ppMemDesc); +static inline NvU32 dispswobjGetRefCount_DISPATCH(struct DispSwObj *pResource) { + return pResource->__dispswobjGetRefCount__(pResource); } -static inline NV_STATUS dispswobjCheckMemInterUnmap_DISPATCH(struct DispSwObj *pRmResource, NvBool bSubdeviceHandleProvided) { - return pRmResource->__dispswobjCheckMemInterUnmap__(pRmResource, bSubdeviceHandleProvided); +static inline void dispswobjAddAdditionalDependants_DISPATCH(struct RsClient *pClient, struct DispSwObj *pResource, RsResourceRef *pReference) { + pResource->__dispswobjAddAdditionalDependants__(pClient, pResource, pReference); } -static inline void dispswobjSetNotificationShare_DISPATCH(struct DispSwObj *pNotifier, struct NotifShare *pNotifShare) { - pNotifier->__dispswobjSetNotificationShare__(pNotifier, pNotifShare); +static inline NV_STATUS dispswobjControl_Prologue_DISPATCH(struct DispSwObj *pDisplayApi, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pRsParams) { + return pDisplayApi->__dispswobjControl_Prologue__(pDisplayApi, pCallContext, pRsParams); } -static inline NV_STATUS dispswobjControlFilter_DISPATCH(struct DispSwObj *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { - return pResource->__dispswobjControlFilter__(pResource, pCallContext, pParams); +static inline NV_STATUS dispswobjUnmapFrom_DISPATCH(struct DispSwObj *pResource, RS_RES_UNMAP_FROM_PARAMS *pParams) { + return pResource->__dispswobjUnmapFrom__(pResource, pParams); } -static inline NvU32 dispswobjGetRefCount_DISPATCH(struct DispSwObj *pResource) { - return pResource->__dispswobjGetRefCount__(pResource); +static inline void dispswobjControl_Epilogue_DISPATCH(struct DispSwObj *pDisplayApi, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pRsParams) { + pDisplayApi->__dispswobjControl_Epilogue__(pDisplayApi, pCallContext, pRsParams); } -static inline NV_STATUS dispswobjUnregisterEvent_DISPATCH(struct DispSwObj *pNotifier, NvHandle hNotifierClient, NvHandle hNotifierResource, NvHandle hEventClient, NvHandle hEvent) { - return pNotifier->__dispswobjUnregisterEvent__(pNotifier, hNotifierClient, hNotifierResource, hEventClient, hEvent); +static inline NV_STATUS dispswobjControlLookup_DISPATCH(struct DispSwObj *pResource, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams, const struct NVOC_EXPORTED_METHOD_DEF **ppEntry) { + return pResource->__dispswobjControlLookup__(pResource, pParams, ppEntry); +} + +static inline NV_STATUS dispswobjControl_DISPATCH(struct DispSwObj *pDisplayApi, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return pDisplayApi->__dispswobjControl__(pDisplayApi, pCallContext, pParams); } static inline NV_STATUS dispswobjUnmap_DISPATCH(struct DispSwObj *pResource, struct CALL_CONTEXT *pCallContext, RsCpuMapping *pCpuMapping) { return pResource->__dispswobjUnmap__(pResource, pCallContext, pCpuMapping); } -static inline NV_STATUS dispswobjControl_Prologue_DISPATCH(struct DispSwObj *pDisplayApi, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pRsParams) { - return pDisplayApi->__dispswobjControl_Prologue__(pDisplayApi, pCallContext, pRsParams); +static inline NV_STATUS dispswobjGetMemInterMapParams_DISPATCH(struct DispSwObj *pRmResource, RMRES_MEM_INTER_MAP_PARAMS *pParams) { + return pRmResource->__dispswobjGetMemInterMapParams__(pRmResource, pParams); } -static inline NvBool dispswobjCanCopy_DISPATCH(struct DispSwObj *pResource) { - return pResource->__dispswobjCanCopy__(pResource); +static inline NV_STATUS dispswobjGetMemoryMappingDescriptor_DISPATCH(struct DispSwObj *pRmResource, struct MEMORY_DESCRIPTOR **ppMemDesc) { + return pRmResource->__dispswobjGetMemoryMappingDescriptor__(pRmResource, ppMemDesc); } -static inline NV_STATUS dispswobjMapTo_DISPATCH(struct DispSwObj *pResource, RS_RES_MAP_TO_PARAMS *pParams) { - return pResource->__dispswobjMapTo__(pResource, pParams); +static inline NV_STATUS dispswobjControlFilter_DISPATCH(struct DispSwObj *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return pResource->__dispswobjControlFilter__(pResource, pCallContext, pParams); } -static inline void dispswobjAddAdditionalDependants_DISPATCH(struct RsClient *pClient, struct DispSwObj *pResource, RsResourceRef *pReference) { - pResource->__dispswobjAddAdditionalDependants__(pClient, pResource, pReference); +static inline NV_STATUS dispswobjUnregisterEvent_DISPATCH(struct DispSwObj *pNotifier, NvHandle hNotifierClient, NvHandle hNotifierResource, NvHandle hEventClient, NvHandle hEvent) { + return pNotifier->__dispswobjUnregisterEvent__(pNotifier, hNotifierClient, hNotifierResource, hEventClient, hEvent); } -static inline void dispswobjPreDestruct_DISPATCH(struct DispSwObj *pResource) { - pResource->__dispswobjPreDestruct__(pResource); +static inline NV_STATUS dispswobjControlSerialization_Prologue_DISPATCH(struct DispSwObj *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return pResource->__dispswobjControlSerialization_Prologue__(pResource, pCallContext, pParams); } -static inline NV_STATUS dispswobjUnmapFrom_DISPATCH(struct DispSwObj *pResource, RS_RES_UNMAP_FROM_PARAMS *pParams) { - return pResource->__dispswobjUnmapFrom__(pResource, pParams); +static inline NvBool dispswobjCanCopy_DISPATCH(struct DispSwObj *pResource) { + return pResource->__dispswobjCanCopy__(pResource); +} + +static inline void dispswobjPreDestruct_DISPATCH(struct DispSwObj *pResource) { + pResource->__dispswobjPreDestruct__(pResource); } static inline NV_STATUS dispswobjIsDuplicate_DISPATCH(struct DispSwObj *pResource, NvHandle hMemory, NvBool *pDuplicate) { return pResource->__dispswobjIsDuplicate__(pResource, hMemory, pDuplicate); } -static inline PEVENTNOTIFICATION *dispswobjGetNotificationListPtr_DISPATCH(struct DispSwObj *pNotifier) { - return pNotifier->__dispswobjGetNotificationListPtr__(pNotifier); +static inline void dispswobjControlSerialization_Epilogue_DISPATCH(struct DispSwObj *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + pResource->__dispswobjControlSerialization_Epilogue__(pResource, pCallContext, pParams); } -static inline void dispswobjControl_Epilogue_DISPATCH(struct DispSwObj *pDisplayApi, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pRsParams) { - pDisplayApi->__dispswobjControl_Epilogue__(pDisplayApi, pCallContext, pRsParams); +static inline PEVENTNOTIFICATION *dispswobjGetNotificationListPtr_DISPATCH(struct DispSwObj *pNotifier) { + return pNotifier->__dispswobjGetNotificationListPtr__(pNotifier); } static inline struct NotifShare *dispswobjGetNotificationShare_DISPATCH(struct DispSwObj *pNotifier) { return pNotifier->__dispswobjGetNotificationShare__(pNotifier); } -static inline NV_STATUS dispswobjControlLookup_DISPATCH(struct DispSwObj *pResource, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams, const struct NVOC_EXPORTED_METHOD_DEF **ppEntry) { - return pResource->__dispswobjControlLookup__(pResource, pParams, ppEntry); -} - static inline NV_STATUS dispswobjMap_DISPATCH(struct DispSwObj *pResource, struct CALL_CONTEXT *pCallContext, RS_CPU_MAP_PARAMS *pParams, RsCpuMapping *pCpuMapping) { return pResource->__dispswobjMap__(pResource, pCallContext, pParams, pCpuMapping); } @@ -1344,7 +1384,12 @@ NV_STATUS (*__dispcmnCtrlCmdSystemGetVblankCounter__)(struct DispCommon *, NV0073_CTRL_SYSTEM_GET_VBLANK_COUNTER_PARAMS *); NV_STATUS (*__dispcmnCtrlCmdSystemGetVblankEnable__)(struct DispCommon *, NV0073_CTRL_SYSTEM_GET_VBLANK_ENABLE_PARAMS *); NV_STATUS (*__dispcmnCtrlCmdSystemCheckSidebandSrSupport__)(struct DispCommon *, NV0073_CTRL_CMD_SYSTEM_CHECK_SIDEBAND_SR_SUPPORT_PARAMS *); + NV_STATUS (*__dispcmnCtrlCmdSystemGetHotplugState__)(struct DispCommon *, NV0073_CTRL_SYSTEM_GET_HOTPLUG_STATE_PARAMS *); NV_STATUS (*__dispcmnCtrlCmdSystemGetInternalDisplays__)(struct DispCommon *, NV0073_CTRL_SYSTEM_GET_INTERNAL_DISPLAYS_PARAMS *); + NV_STATUS (*__dispcmnCtrlCmdSystemGetConnectorTable__)(struct DispCommon *, NV0073_CTRL_SYSTEM_GET_CONNECTOR_TABLE_PARAMS *); + NV_STATUS (*__dispcmnCtrlCmdSystemVrrDisplayInfo__)(struct DispCommon *, NV0073_CTRL_SYSTEM_VRR_DISPLAY_INFO_PARAMS *); + NV_STATUS (*__dispcmnCtrlCmdVRRSetRgLineActive__)(struct DispCommon *, NV0073_CTRL_CMD_SYSTEM_VRR_SET_RGLINE_ACTIVE_PARAMS *); + NV_STATUS (*__dispcmnCtrlCmdInternalVRRSetRgLineActive__)(struct DispCommon *, NV0073_CTRL_CMD_SYSTEM_VRR_SET_RGLINE_ACTIVE_PARAMS *); NV_STATUS (*__dispcmnCtrlCmdDpEnableVrr__)(struct DispCommon *, NV0073_CTRL_CMD_DP_ENABLE_VRR_PARAMS *); NV_STATUS (*__dispcmnCtrlCmdClearELVBlock__)(struct DispCommon *, NV0073_CTRL_SYSTEM_CLEAR_ELV_BLOCK_PARAMS *); NV_STATUS (*__dispcmnCtrlCmdSpecificDisplayChange__)(struct DispCommon *, NV0073_CTRL_SPECIFIC_DISPLAY_CHANGE_PARAMS *); @@ -1354,16 +1399,20 @@ NV_STATUS (*__dispcmnCtrlCmdDpAuxchI2cTransferCtrl__)(struct DispCommon *, NV0073_CTRL_DP_AUXCH_I2C_TRANSFER_CTRL_PARAMS *); NV_STATUS (*__dispcmnCtrlCmdDpASSRCtrl__)(struct DispCommon *, NV0073_CTRL_DP_ASSR_CTRL_PARAMS *); NV_STATUS (*__dispcmnCtrlCmdDpSetEcf__)(struct DispCommon *, NV0073_CTRL_CMD_DP_SET_ECF_PARAMS *); + NV_STATUS (*__dispcmnCtrlCmdStereoDongleSupported__)(struct DispCommon *, NV0073_CTRL_STEREO_DONGLE_SUPPORTED_PARAMS *); + NV_STATUS (*__dispcmnCtrlCmdDfpRecordChannelRegisters__)(struct DispCommon *, NV0073_CTRL_CMD_SYSTEM_RECORD_CHANNEL_REGS_PARAMS *); NV_STATUS (*__dispcmnCtrlCmdSpecificGetBacklightBrightness__)(struct DispCommon *, NV0073_CTRL_SPECIFIC_BACKLIGHT_BRIGHTNESS_PARAMS *); NV_STATUS (*__dispcmnCtrlCmdSpecificSetBacklightBrightness__)(struct DispCommon *, NV0073_CTRL_SPECIFIC_BACKLIGHT_BRIGHTNESS_PARAMS *); + NV_STATUS (*__dispcmnCtrlCmdPsrGetSrPanelInfo__)(struct DispCommon *, NV0073_CTRL_PSR_GET_SR_PANEL_INFO_PARAMS *); NV_STATUS (*__dispcmnCtrlCmdDfpSwitchDispMux__)(struct DispCommon *, NV0073_CTRL_CMD_DFP_SWITCH_DISP_MUX_PARAMS *); NV_STATUS (*__dispcmnCtrlCmdDfpRunPreDispMuxOperations__)(struct DispCommon *, NV0073_CTRL_CMD_DFP_RUN_PRE_DISP_MUX_OPERATIONS_PARAMS *); NV_STATUS (*__dispcmnCtrlCmdDfpRunPostDispMuxOperations__)(struct DispCommon *, NV0073_CTRL_CMD_DFP_RUN_POST_DISP_MUX_OPERATIONS_PARAMS *); NV_STATUS (*__dispcmnCtrlCmdDfpGetDispMuxStatus__)(struct DispCommon *, NV0073_CTRL_CMD_DFP_GET_DISP_MUX_STATUS_PARAMS *); - NV_STATUS (*__dispcmnCtrlCmdDfpRecordChannelRegisters__)(struct DispCommon *, NV0073_CTRL_CMD_SYSTEM_RECORD_CHANNEL_REGS_PARAMS *); NV_STATUS (*__dispcmnCtrlCmdDfpInternalLcdOverdrive__)(struct DispCommon *, NV0073_CTRL_CMD_DP_AUXCH_OD_CTRL_PARAMS *); + NV_STATUS (*__dispcmnCtrlCmdDfpExecuteInternalLcdOverDrivePolicy__)(struct DispCommon *, NV0073_CTRL_DP_EXECUTE_OVERDRIVE_POLICY_PARAMS *); NV_STATUS (*__dispcmnCtrlCmdSystemExecuteAcpiMethod__)(struct DispCommon *, NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_PARAMS *); NV_STATUS (*__dispcmnCtrlCmdSystemGetAcpiIdMap__)(struct DispCommon *, NV0073_CTRL_SYSTEM_GET_ACPI_ID_MAP_PARAMS *); + NV_STATUS (*__dispcmnCtrlCmdSystemAcpiSubsystemActivated__)(struct DispCommon *, NV0073_CTRL_SYSTEM_ACPI_SUBSYSTEM_ACTIVATED_PARAMS *); NV_STATUS (*__dispcmnCtrlCmdSpecificSetAcpiIdMapping__)(struct DispCommon *, NV0073_CTRL_SPECIFIC_SET_ACPI_ID_MAPPING_PARAMS *); NV_STATUS (*__dispcmnCtrlCmdSpecificGetAcpiDodDisplayPortAttachment__)(struct DispCommon *, NV0073_CTRL_GET_ACPI_DOD_DISPLAY_PORT_ATTACHMENT_PARAMS *); NV_STATUS (*__dispcmnCtrlCmdSystemGetCapsV2__)(struct DispCommon *, NV0073_CTRL_SYSTEM_GET_CAPS_V2_PARAMS *); @@ -1407,9 +1456,11 @@ NV_STATUS (*__dispcmnCtrlCmdSpecificGetHdmiGpuCaps__)(struct DispCommon *, NV0073_CTRL_SPECIFIC_GET_HDMI_GPU_CAPS_PARAMS *); NV_STATUS (*__dispcmnCtrlCmdSpecificGetHdmiScdcData__)(struct DispCommon *, NV0073_CTRL_SPECIFIC_GET_HDMI_SCDC_DATA_PARAMS *); NV_STATUS (*__dispcmnCtrlCmdSpecificIsDirectmodeDisplay__)(struct DispCommon *, NV0073_CTRL_SPECIFIC_IS_DIRECTMODE_DISPLAY_PARAMS *); + NV_STATUS (*__dispcmnCtrlCmdSpecificDefaultAdaptivesyncDisplay__)(struct DispCommon *, NV0073_CTRL_SPECIFIC_DEFAULT_ADAPTIVESYNC_DISPLAY_PARAMS *); NV_STATUS (*__dispcmnCtrlCmdSpecificSetHdmiFrlCapacityComputation__)(struct DispCommon *, NV0073_CTRL_SPECIFIC_GET_HDMI_FRL_CAPACITY_COMPUTATION_PARAMS *); NV_STATUS (*__dispcmnCtrlCmdSpecificDispI2cReadWrite__)(struct DispCommon *, NV0073_CTRL_SPECIFIC_DISP_I2C_READ_WRITE_PARAMS *); NV_STATUS (*__dispcmnCtrlCmdSpecificGetValidHeadWindowAssignment__)(struct DispCommon *, NV0073_CTRL_SPECIFIC_GET_VALID_HEAD_WINDOW_ASSIGNMENT_PARAMS *); + NV_STATUS (*__dispcmnCtrlCmdSpecificSetHdmiAudioMutestream__)(struct DispCommon *, NV0073_CTRL_CMD_SPECIFIC_SET_HDMI_AUDIO_MUTESTREAM_PARAMS *); NV_STATUS (*__dispcmnCtrlCmdDfpGetInfo__)(struct DispCommon *, NV0073_CTRL_DFP_GET_INFO_PARAMS *); NV_STATUS (*__dispcmnCtrlCmdDfpGetDisplayportDongleInfo__)(struct DispCommon *, NV0073_CTRL_DFP_GET_DISPLAYPORT_DONGLE_INFO_PARAMS *); NV_STATUS (*__dispcmnCtrlCmdDfpSetEldAudioCaps__)(struct DispCommon *, NV0073_CTRL_DFP_SET_ELD_AUDIO_CAP_PARAMS *); @@ -1455,27 +1506,29 @@ NV_STATUS (*__dispcmnCtrlCmdDpSetPreemphasisDrivecurrentPostcursor2Data__)(struct DispCommon *, NV0073_CTRL_DP_SET_PREEMPHASIS_DRIVECURRENT_POSTCURSOR2_DATA_PARAMS *); NV_STATUS (*__dispcmnCtrlCmdDpGetPreemphasisDrivecurrentPostcursor2Data__)(struct DispCommon *, NV0073_CTRL_DP_GET_PREEMPHASIS_DRIVECURRENT_POSTCURSOR2_DATA_PARAMS *); NvBool (*__dispcmnShareCallback__)(struct DispCommon *, struct RsClient *, struct RsResourceRef *, RS_SHARE_POLICY *); - NV_STATUS (*__dispcmnControl__)(struct DispCommon *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); + NV_STATUS (*__dispcmnCheckMemInterUnmap__)(struct DispCommon *, NvBool); + NV_STATUS (*__dispcmnMapTo__)(struct DispCommon *, RS_RES_MAP_TO_PARAMS *); NvBool (*__dispcmnAccessCallback__)(struct DispCommon *, struct RsClient *, void *, RsAccessRight); + void (*__dispcmnSetNotificationShare__)(struct DispCommon *, struct NotifShare *); + NvU32 (*__dispcmnGetRefCount__)(struct DispCommon *); + void (*__dispcmnAddAdditionalDependants__)(struct RsClient *, struct DispCommon *, RsResourceRef *); + NV_STATUS (*__dispcmnControl_Prologue__)(struct DispCommon *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); + NV_STATUS (*__dispcmnUnmapFrom__)(struct DispCommon *, RS_RES_UNMAP_FROM_PARAMS *); + void (*__dispcmnControl_Epilogue__)(struct DispCommon *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); + NV_STATUS (*__dispcmnControlLookup__)(struct DispCommon *, struct RS_RES_CONTROL_PARAMS_INTERNAL *, const struct NVOC_EXPORTED_METHOD_DEF **); + NV_STATUS (*__dispcmnControl__)(struct DispCommon *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); + NV_STATUS (*__dispcmnUnmap__)(struct DispCommon *, struct CALL_CONTEXT *, RsCpuMapping *); NV_STATUS (*__dispcmnGetMemInterMapParams__)(struct DispCommon *, RMRES_MEM_INTER_MAP_PARAMS *); NV_STATUS (*__dispcmnGetMemoryMappingDescriptor__)(struct DispCommon *, struct MEMORY_DESCRIPTOR **); - NV_STATUS (*__dispcmnCheckMemInterUnmap__)(struct DispCommon *, NvBool); - void (*__dispcmnSetNotificationShare__)(struct DispCommon *, struct NotifShare *); NV_STATUS (*__dispcmnControlFilter__)(struct DispCommon *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); - NvU32 (*__dispcmnGetRefCount__)(struct DispCommon *); NV_STATUS (*__dispcmnUnregisterEvent__)(struct DispCommon *, NvHandle, NvHandle, NvHandle, NvHandle); - NV_STATUS (*__dispcmnUnmap__)(struct DispCommon *, struct CALL_CONTEXT *, RsCpuMapping *); - NV_STATUS (*__dispcmnControl_Prologue__)(struct DispCommon *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); + NV_STATUS (*__dispcmnControlSerialization_Prologue__)(struct DispCommon *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); NvBool (*__dispcmnCanCopy__)(struct DispCommon *); - NV_STATUS (*__dispcmnMapTo__)(struct DispCommon *, RS_RES_MAP_TO_PARAMS *); - void (*__dispcmnAddAdditionalDependants__)(struct RsClient *, struct DispCommon *, RsResourceRef *); void (*__dispcmnPreDestruct__)(struct DispCommon *); - NV_STATUS (*__dispcmnUnmapFrom__)(struct DispCommon *, RS_RES_UNMAP_FROM_PARAMS *); NV_STATUS (*__dispcmnIsDuplicate__)(struct DispCommon *, NvHandle, NvBool *); + void (*__dispcmnControlSerialization_Epilogue__)(struct DispCommon *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); PEVENTNOTIFICATION *(*__dispcmnGetNotificationListPtr__)(struct DispCommon *); - void (*__dispcmnControl_Epilogue__)(struct DispCommon *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); struct NotifShare *(*__dispcmnGetNotificationShare__)(struct DispCommon *); - NV_STATUS (*__dispcmnControlLookup__)(struct DispCommon *, struct RS_RES_CONTROL_PARAMS_INTERNAL *, const struct NVOC_EXPORTED_METHOD_DEF **); NV_STATUS (*__dispcmnMap__)(struct DispCommon *, struct CALL_CONTEXT *, RS_CPU_MAP_PARAMS *, RsCpuMapping *); NV_STATUS (*__dispcmnGetOrAllocNotifShare__)(struct DispCommon *, NvHandle, NvHandle, struct NotifShare **); NvU32 hotPlugMaskToBeReported; @@ -1513,7 +1566,12 @@ #define dispcmnCtrlCmdSystemGetVblankCounter(pDispCommon, pVBCounterParams) dispcmnCtrlCmdSystemGetVblankCounter_DISPATCH(pDispCommon, pVBCounterParams) #define dispcmnCtrlCmdSystemGetVblankEnable(pDispCommon, pVBEnableParams) dispcmnCtrlCmdSystemGetVblankEnable_DISPATCH(pDispCommon, pVBEnableParams) #define dispcmnCtrlCmdSystemCheckSidebandSrSupport(pDispCommon, pParams) dispcmnCtrlCmdSystemCheckSidebandSrSupport_DISPATCH(pDispCommon, pParams) +#define dispcmnCtrlCmdSystemGetHotplugState(pDispCommon, pHotplugParams) dispcmnCtrlCmdSystemGetHotplugState_DISPATCH(pDispCommon, pHotplugParams) #define dispcmnCtrlCmdSystemGetInternalDisplays(pDispCommon, pInternalDisplaysParams) dispcmnCtrlCmdSystemGetInternalDisplays_DISPATCH(pDispCommon, pInternalDisplaysParams) +#define dispcmnCtrlCmdSystemGetConnectorTable(pDispCommon, pParams) dispcmnCtrlCmdSystemGetConnectorTable_DISPATCH(pDispCommon, pParams) +#define dispcmnCtrlCmdSystemVrrDisplayInfo(pDispCommon, pParams) dispcmnCtrlCmdSystemVrrDisplayInfo_DISPATCH(pDispCommon, pParams) +#define dispcmnCtrlCmdVRRSetRgLineActive(pDispCommon, pParams) dispcmnCtrlCmdVRRSetRgLineActive_DISPATCH(pDispCommon, pParams) +#define dispcmnCtrlCmdInternalVRRSetRgLineActive(pDispCommon, pParams) dispcmnCtrlCmdInternalVRRSetRgLineActive_DISPATCH(pDispCommon, pParams) #define dispcmnCtrlCmdDpEnableVrr(pDispCommon, pParams) dispcmnCtrlCmdDpEnableVrr_DISPATCH(pDispCommon, pParams) #define dispcmnCtrlCmdClearELVBlock(pDispCommon, pParams) dispcmnCtrlCmdClearELVBlock_DISPATCH(pDispCommon, pParams) #define dispcmnCtrlCmdSpecificDisplayChange(pDispCommon, pParams) dispcmnCtrlCmdSpecificDisplayChange_DISPATCH(pDispCommon, pParams) @@ -1523,16 +1581,20 @@ #define dispcmnCtrlCmdDpAuxchI2cTransferCtrl(pDispCommon, pParams) dispcmnCtrlCmdDpAuxchI2cTransferCtrl_DISPATCH(pDispCommon, pParams) #define dispcmnCtrlCmdDpASSRCtrl(pDispCommon, pParams) dispcmnCtrlCmdDpASSRCtrl_DISPATCH(pDispCommon, pParams) #define dispcmnCtrlCmdDpSetEcf(pDispCommon, pCtrlEcfParams) dispcmnCtrlCmdDpSetEcf_DISPATCH(pDispCommon, pCtrlEcfParams) +#define dispcmnCtrlCmdStereoDongleSupported(pDispCommon, pCtrlStereoParams) dispcmnCtrlCmdStereoDongleSupported_DISPATCH(pDispCommon, pCtrlStereoParams) +#define dispcmnCtrlCmdDfpRecordChannelRegisters(pDispCommon, pParams) dispcmnCtrlCmdDfpRecordChannelRegisters_DISPATCH(pDispCommon, pParams) #define dispcmnCtrlCmdSpecificGetBacklightBrightness(pDispCommon, pAllHeadMaskParams) dispcmnCtrlCmdSpecificGetBacklightBrightness_DISPATCH(pDispCommon, pAllHeadMaskParams) #define dispcmnCtrlCmdSpecificSetBacklightBrightness(pDispCommon, pParams) dispcmnCtrlCmdSpecificSetBacklightBrightness_DISPATCH(pDispCommon, pParams) +#define dispcmnCtrlCmdPsrGetSrPanelInfo(pDispCommon, pParams) dispcmnCtrlCmdPsrGetSrPanelInfo_DISPATCH(pDispCommon, pParams) #define dispcmnCtrlCmdDfpSwitchDispMux(pDispCommon, pParams) dispcmnCtrlCmdDfpSwitchDispMux_DISPATCH(pDispCommon, pParams) #define dispcmnCtrlCmdDfpRunPreDispMuxOperations(pDispCommon, pParams) dispcmnCtrlCmdDfpRunPreDispMuxOperations_DISPATCH(pDispCommon, pParams) #define dispcmnCtrlCmdDfpRunPostDispMuxOperations(pDispCommon, pParams) dispcmnCtrlCmdDfpRunPostDispMuxOperations_DISPATCH(pDispCommon, pParams) #define dispcmnCtrlCmdDfpGetDispMuxStatus(pDispCommon, pParams) dispcmnCtrlCmdDfpGetDispMuxStatus_DISPATCH(pDispCommon, pParams) -#define dispcmnCtrlCmdDfpRecordChannelRegisters(pDispCommon, pParams) dispcmnCtrlCmdDfpRecordChannelRegisters_DISPATCH(pDispCommon, pParams) #define dispcmnCtrlCmdDfpInternalLcdOverdrive(pDispCommon, pParams) dispcmnCtrlCmdDfpInternalLcdOverdrive_DISPATCH(pDispCommon, pParams) +#define dispcmnCtrlCmdDfpExecuteInternalLcdOverDrivePolicy(pDispCommon, pParams) dispcmnCtrlCmdDfpExecuteInternalLcdOverDrivePolicy_DISPATCH(pDispCommon, pParams) #define dispcmnCtrlCmdSystemExecuteAcpiMethod(pDispCommon, pAcpiMethodParams) dispcmnCtrlCmdSystemExecuteAcpiMethod_DISPATCH(pDispCommon, pAcpiMethodParams) #define dispcmnCtrlCmdSystemGetAcpiIdMap(pDispCommon, pAcpiIdMapParams) dispcmnCtrlCmdSystemGetAcpiIdMap_DISPATCH(pDispCommon, pAcpiIdMapParams) +#define dispcmnCtrlCmdSystemAcpiSubsystemActivated(pDispCommon, pParams) dispcmnCtrlCmdSystemAcpiSubsystemActivated_DISPATCH(pDispCommon, pParams) #define dispcmnCtrlCmdSpecificSetAcpiIdMapping(pDispCommon, pParams) dispcmnCtrlCmdSpecificSetAcpiIdMapping_DISPATCH(pDispCommon, pParams) #define dispcmnCtrlCmdSpecificGetAcpiDodDisplayPortAttachment(pDispCommon, pParams) dispcmnCtrlCmdSpecificGetAcpiDodDisplayPortAttachment_DISPATCH(pDispCommon, pParams) #define dispcmnCtrlCmdSystemGetCapsV2(pDispCommon, pCapsParams) dispcmnCtrlCmdSystemGetCapsV2_DISPATCH(pDispCommon, pCapsParams) @@ -1576,9 +1638,11 @@ #define dispcmnCtrlCmdSpecificGetHdmiGpuCaps(pDispCommon, pParams) dispcmnCtrlCmdSpecificGetHdmiGpuCaps_DISPATCH(pDispCommon, pParams) #define dispcmnCtrlCmdSpecificGetHdmiScdcData(pDispCommon, pParams) dispcmnCtrlCmdSpecificGetHdmiScdcData_DISPATCH(pDispCommon, pParams) #define dispcmnCtrlCmdSpecificIsDirectmodeDisplay(pDispCommon, pParams) dispcmnCtrlCmdSpecificIsDirectmodeDisplay_DISPATCH(pDispCommon, pParams) +#define dispcmnCtrlCmdSpecificDefaultAdaptivesyncDisplay(pDispCommon, pParams) dispcmnCtrlCmdSpecificDefaultAdaptivesyncDisplay_DISPATCH(pDispCommon, pParams) #define dispcmnCtrlCmdSpecificSetHdmiFrlCapacityComputation(pDispCommon, pParams) dispcmnCtrlCmdSpecificSetHdmiFrlCapacityComputation_DISPATCH(pDispCommon, pParams) #define dispcmnCtrlCmdSpecificDispI2cReadWrite(pDispCommon, pParams) dispcmnCtrlCmdSpecificDispI2cReadWrite_DISPATCH(pDispCommon, pParams) #define dispcmnCtrlCmdSpecificGetValidHeadWindowAssignment(pDispCommon, pParams) dispcmnCtrlCmdSpecificGetValidHeadWindowAssignment_DISPATCH(pDispCommon, pParams) +#define dispcmnCtrlCmdSpecificSetHdmiAudioMutestream(pDispCommon, pParams) dispcmnCtrlCmdSpecificSetHdmiAudioMutestream_DISPATCH(pDispCommon, pParams) #define dispcmnCtrlCmdDfpGetInfo(pDispCommon, pParams) dispcmnCtrlCmdDfpGetInfo_DISPATCH(pDispCommon, pParams) #define dispcmnCtrlCmdDfpGetDisplayportDongleInfo(pDispCommon, pParams) dispcmnCtrlCmdDfpGetDisplayportDongleInfo_DISPATCH(pDispCommon, pParams) #define dispcmnCtrlCmdDfpSetEldAudioCaps(pDispCommon, pEldAudioCapsParams) dispcmnCtrlCmdDfpSetEldAudioCaps_DISPATCH(pDispCommon, pEldAudioCapsParams) @@ -1624,27 +1688,29 @@ #define dispcmnCtrlCmdDpSetPreemphasisDrivecurrentPostcursor2Data(pDispCommon, pParams) dispcmnCtrlCmdDpSetPreemphasisDrivecurrentPostcursor2Data_DISPATCH(pDispCommon, pParams) #define dispcmnCtrlCmdDpGetPreemphasisDrivecurrentPostcursor2Data(pDispCommon, pParams) dispcmnCtrlCmdDpGetPreemphasisDrivecurrentPostcursor2Data_DISPATCH(pDispCommon, pParams) #define dispcmnShareCallback(pResource, pInvokingClient, pParentRef, pSharePolicy) dispcmnShareCallback_DISPATCH(pResource, pInvokingClient, pParentRef, pSharePolicy) -#define dispcmnControl(pDisplayApi, pCallContext, pParams) dispcmnControl_DISPATCH(pDisplayApi, pCallContext, pParams) +#define dispcmnCheckMemInterUnmap(pRmResource, bSubdeviceHandleProvided) dispcmnCheckMemInterUnmap_DISPATCH(pRmResource, bSubdeviceHandleProvided) +#define dispcmnMapTo(pResource, pParams) dispcmnMapTo_DISPATCH(pResource, pParams) #define dispcmnAccessCallback(pResource, pInvokingClient, pAllocParams, accessRight) dispcmnAccessCallback_DISPATCH(pResource, pInvokingClient, pAllocParams, accessRight) +#define dispcmnSetNotificationShare(pNotifier, pNotifShare) dispcmnSetNotificationShare_DISPATCH(pNotifier, pNotifShare) +#define dispcmnGetRefCount(pResource) dispcmnGetRefCount_DISPATCH(pResource) +#define dispcmnAddAdditionalDependants(pClient, pResource, pReference) dispcmnAddAdditionalDependants_DISPATCH(pClient, pResource, pReference) +#define dispcmnControl_Prologue(pDisplayApi, pCallContext, pRsParams) dispcmnControl_Prologue_DISPATCH(pDisplayApi, pCallContext, pRsParams) +#define dispcmnUnmapFrom(pResource, pParams) dispcmnUnmapFrom_DISPATCH(pResource, pParams) +#define dispcmnControl_Epilogue(pDisplayApi, pCallContext, pRsParams) dispcmnControl_Epilogue_DISPATCH(pDisplayApi, pCallContext, pRsParams) +#define dispcmnControlLookup(pResource, pParams, ppEntry) dispcmnControlLookup_DISPATCH(pResource, pParams, ppEntry) +#define dispcmnControl(pDisplayApi, pCallContext, pParams) dispcmnControl_DISPATCH(pDisplayApi, pCallContext, pParams) +#define dispcmnUnmap(pResource, pCallContext, pCpuMapping) dispcmnUnmap_DISPATCH(pResource, pCallContext, pCpuMapping) #define dispcmnGetMemInterMapParams(pRmResource, pParams) dispcmnGetMemInterMapParams_DISPATCH(pRmResource, pParams) #define dispcmnGetMemoryMappingDescriptor(pRmResource, ppMemDesc) dispcmnGetMemoryMappingDescriptor_DISPATCH(pRmResource, ppMemDesc) -#define dispcmnCheckMemInterUnmap(pRmResource, bSubdeviceHandleProvided) dispcmnCheckMemInterUnmap_DISPATCH(pRmResource, bSubdeviceHandleProvided) -#define dispcmnSetNotificationShare(pNotifier, pNotifShare) dispcmnSetNotificationShare_DISPATCH(pNotifier, pNotifShare) #define dispcmnControlFilter(pResource, pCallContext, pParams) dispcmnControlFilter_DISPATCH(pResource, pCallContext, pParams) -#define dispcmnGetRefCount(pResource) dispcmnGetRefCount_DISPATCH(pResource) #define dispcmnUnregisterEvent(pNotifier, hNotifierClient, hNotifierResource, hEventClient, hEvent) dispcmnUnregisterEvent_DISPATCH(pNotifier, hNotifierClient, hNotifierResource, hEventClient, hEvent) -#define dispcmnUnmap(pResource, pCallContext, pCpuMapping) dispcmnUnmap_DISPATCH(pResource, pCallContext, pCpuMapping) -#define dispcmnControl_Prologue(pDisplayApi, pCallContext, pRsParams) dispcmnControl_Prologue_DISPATCH(pDisplayApi, pCallContext, pRsParams) +#define dispcmnControlSerialization_Prologue(pResource, pCallContext, pParams) dispcmnControlSerialization_Prologue_DISPATCH(pResource, pCallContext, pParams) #define dispcmnCanCopy(pResource) dispcmnCanCopy_DISPATCH(pResource) -#define dispcmnMapTo(pResource, pParams) dispcmnMapTo_DISPATCH(pResource, pParams) -#define dispcmnAddAdditionalDependants(pClient, pResource, pReference) dispcmnAddAdditionalDependants_DISPATCH(pClient, pResource, pReference) #define dispcmnPreDestruct(pResource) dispcmnPreDestruct_DISPATCH(pResource) -#define dispcmnUnmapFrom(pResource, pParams) dispcmnUnmapFrom_DISPATCH(pResource, pParams) #define dispcmnIsDuplicate(pResource, hMemory, pDuplicate) dispcmnIsDuplicate_DISPATCH(pResource, hMemory, pDuplicate) +#define dispcmnControlSerialization_Epilogue(pResource, pCallContext, pParams) dispcmnControlSerialization_Epilogue_DISPATCH(pResource, pCallContext, pParams) #define dispcmnGetNotificationListPtr(pNotifier) dispcmnGetNotificationListPtr_DISPATCH(pNotifier) -#define dispcmnControl_Epilogue(pDisplayApi, pCallContext, pRsParams) dispcmnControl_Epilogue_DISPATCH(pDisplayApi, pCallContext, pRsParams) #define dispcmnGetNotificationShare(pNotifier) dispcmnGetNotificationShare_DISPATCH(pNotifier) -#define dispcmnControlLookup(pResource, pParams, ppEntry) dispcmnControlLookup_DISPATCH(pResource, pParams, ppEntry) #define dispcmnMap(pResource, pCallContext, pParams, pCpuMapping) dispcmnMap_DISPATCH(pResource, pCallContext, pParams, pCpuMapping) #define dispcmnGetOrAllocNotifShare(pNotifier, hNotifierClient, hNotifierResource, ppNotifShare) dispcmnGetOrAllocNotifShare_DISPATCH(pNotifier, hNotifierClient, hNotifierResource, ppNotifShare) NV_STATUS dispcmnCtrlCmdSystemGetVblankCounter_IMPL(struct DispCommon *pDispCommon, NV0073_CTRL_SYSTEM_GET_VBLANK_COUNTER_PARAMS *pVBCounterParams); @@ -1665,12 +1731,42 @@ return pDispCommon->__dispcmnCtrlCmdSystemCheckSidebandSrSupport__(pDispCommon, pParams); } +NV_STATUS dispcmnCtrlCmdSystemGetHotplugState_IMPL(struct DispCommon *pDispCommon, NV0073_CTRL_SYSTEM_GET_HOTPLUG_STATE_PARAMS *pHotplugParams); + +static inline NV_STATUS dispcmnCtrlCmdSystemGetHotplugState_DISPATCH(struct DispCommon *pDispCommon, NV0073_CTRL_SYSTEM_GET_HOTPLUG_STATE_PARAMS *pHotplugParams) { + return pDispCommon->__dispcmnCtrlCmdSystemGetHotplugState__(pDispCommon, pHotplugParams); +} + NV_STATUS dispcmnCtrlCmdSystemGetInternalDisplays_IMPL(struct DispCommon *pDispCommon, NV0073_CTRL_SYSTEM_GET_INTERNAL_DISPLAYS_PARAMS *pInternalDisplaysParams); static inline NV_STATUS dispcmnCtrlCmdSystemGetInternalDisplays_DISPATCH(struct DispCommon *pDispCommon, NV0073_CTRL_SYSTEM_GET_INTERNAL_DISPLAYS_PARAMS *pInternalDisplaysParams) { return pDispCommon->__dispcmnCtrlCmdSystemGetInternalDisplays__(pDispCommon, pInternalDisplaysParams); } +NV_STATUS dispcmnCtrlCmdSystemGetConnectorTable_IMPL(struct DispCommon *pDispCommon, NV0073_CTRL_SYSTEM_GET_CONNECTOR_TABLE_PARAMS *pParams); + +static inline NV_STATUS dispcmnCtrlCmdSystemGetConnectorTable_DISPATCH(struct DispCommon *pDispCommon, NV0073_CTRL_SYSTEM_GET_CONNECTOR_TABLE_PARAMS *pParams) { + return pDispCommon->__dispcmnCtrlCmdSystemGetConnectorTable__(pDispCommon, pParams); +} + +NV_STATUS dispcmnCtrlCmdSystemVrrDisplayInfo_IMPL(struct DispCommon *pDispCommon, NV0073_CTRL_SYSTEM_VRR_DISPLAY_INFO_PARAMS *pParams); + +static inline NV_STATUS dispcmnCtrlCmdSystemVrrDisplayInfo_DISPATCH(struct DispCommon *pDispCommon, NV0073_CTRL_SYSTEM_VRR_DISPLAY_INFO_PARAMS *pParams) { + return pDispCommon->__dispcmnCtrlCmdSystemVrrDisplayInfo__(pDispCommon, pParams); +} + +NV_STATUS dispcmnCtrlCmdVRRSetRgLineActive_IMPL(struct DispCommon *pDispCommon, NV0073_CTRL_CMD_SYSTEM_VRR_SET_RGLINE_ACTIVE_PARAMS *pParams); + +static inline NV_STATUS dispcmnCtrlCmdVRRSetRgLineActive_DISPATCH(struct DispCommon *pDispCommon, NV0073_CTRL_CMD_SYSTEM_VRR_SET_RGLINE_ACTIVE_PARAMS *pParams) { + return pDispCommon->__dispcmnCtrlCmdVRRSetRgLineActive__(pDispCommon, pParams); +} + +NV_STATUS dispcmnCtrlCmdInternalVRRSetRgLineActive_IMPL(struct DispCommon *pDispCommon, NV0073_CTRL_CMD_SYSTEM_VRR_SET_RGLINE_ACTIVE_PARAMS *pParams); + +static inline NV_STATUS dispcmnCtrlCmdInternalVRRSetRgLineActive_DISPATCH(struct DispCommon *pDispCommon, NV0073_CTRL_CMD_SYSTEM_VRR_SET_RGLINE_ACTIVE_PARAMS *pParams) { + return pDispCommon->__dispcmnCtrlCmdInternalVRRSetRgLineActive__(pDispCommon, pParams); +} + NV_STATUS dispcmnCtrlCmdDpEnableVrr_IMPL(struct DispCommon *pDispCommon, NV0073_CTRL_CMD_DP_ENABLE_VRR_PARAMS *pParams); static inline NV_STATUS dispcmnCtrlCmdDpEnableVrr_DISPATCH(struct DispCommon *pDispCommon, NV0073_CTRL_CMD_DP_ENABLE_VRR_PARAMS *pParams) { @@ -1725,6 +1821,18 @@ return pDispCommon->__dispcmnCtrlCmdDpSetEcf__(pDispCommon, pCtrlEcfParams); } +NV_STATUS dispcmnCtrlCmdStereoDongleSupported_IMPL(struct DispCommon *pDispCommon, NV0073_CTRL_STEREO_DONGLE_SUPPORTED_PARAMS *pCtrlStereoParams); + +static inline NV_STATUS dispcmnCtrlCmdStereoDongleSupported_DISPATCH(struct DispCommon *pDispCommon, NV0073_CTRL_STEREO_DONGLE_SUPPORTED_PARAMS *pCtrlStereoParams) { + return pDispCommon->__dispcmnCtrlCmdStereoDongleSupported__(pDispCommon, pCtrlStereoParams); +} + +NV_STATUS dispcmnCtrlCmdDfpRecordChannelRegisters_IMPL(struct DispCommon *pDispCommon, NV0073_CTRL_CMD_SYSTEM_RECORD_CHANNEL_REGS_PARAMS *pParams); + +static inline NV_STATUS dispcmnCtrlCmdDfpRecordChannelRegisters_DISPATCH(struct DispCommon *pDispCommon, NV0073_CTRL_CMD_SYSTEM_RECORD_CHANNEL_REGS_PARAMS *pParams) { + return pDispCommon->__dispcmnCtrlCmdDfpRecordChannelRegisters__(pDispCommon, pParams); +} + NV_STATUS dispcmnCtrlCmdSpecificGetBacklightBrightness_IMPL(struct DispCommon *pDispCommon, NV0073_CTRL_SPECIFIC_BACKLIGHT_BRIGHTNESS_PARAMS *pAllHeadMaskParams); static inline NV_STATUS dispcmnCtrlCmdSpecificGetBacklightBrightness_DISPATCH(struct DispCommon *pDispCommon, NV0073_CTRL_SPECIFIC_BACKLIGHT_BRIGHTNESS_PARAMS *pAllHeadMaskParams) { @@ -1737,6 +1845,12 @@ return pDispCommon->__dispcmnCtrlCmdSpecificSetBacklightBrightness__(pDispCommon, pParams); } +NV_STATUS dispcmnCtrlCmdPsrGetSrPanelInfo_IMPL(struct DispCommon *pDispCommon, NV0073_CTRL_PSR_GET_SR_PANEL_INFO_PARAMS *pParams); + +static inline NV_STATUS dispcmnCtrlCmdPsrGetSrPanelInfo_DISPATCH(struct DispCommon *pDispCommon, NV0073_CTRL_PSR_GET_SR_PANEL_INFO_PARAMS *pParams) { + return pDispCommon->__dispcmnCtrlCmdPsrGetSrPanelInfo__(pDispCommon, pParams); +} + NV_STATUS dispcmnCtrlCmdDfpSwitchDispMux_IMPL(struct DispCommon *pDispCommon, NV0073_CTRL_CMD_DFP_SWITCH_DISP_MUX_PARAMS *pParams); static inline NV_STATUS dispcmnCtrlCmdDfpSwitchDispMux_DISPATCH(struct DispCommon *pDispCommon, NV0073_CTRL_CMD_DFP_SWITCH_DISP_MUX_PARAMS *pParams) { @@ -1761,18 +1875,18 @@ return pDispCommon->__dispcmnCtrlCmdDfpGetDispMuxStatus__(pDispCommon, pParams); } -NV_STATUS dispcmnCtrlCmdDfpRecordChannelRegisters_IMPL(struct DispCommon *pDispCommon, NV0073_CTRL_CMD_SYSTEM_RECORD_CHANNEL_REGS_PARAMS *pParams); - -static inline NV_STATUS dispcmnCtrlCmdDfpRecordChannelRegisters_DISPATCH(struct DispCommon *pDispCommon, NV0073_CTRL_CMD_SYSTEM_RECORD_CHANNEL_REGS_PARAMS *pParams) { - return pDispCommon->__dispcmnCtrlCmdDfpRecordChannelRegisters__(pDispCommon, pParams); -} - NV_STATUS dispcmnCtrlCmdDfpInternalLcdOverdrive_IMPL(struct DispCommon *pDispCommon, NV0073_CTRL_CMD_DP_AUXCH_OD_CTRL_PARAMS *pParams); static inline NV_STATUS dispcmnCtrlCmdDfpInternalLcdOverdrive_DISPATCH(struct DispCommon *pDispCommon, NV0073_CTRL_CMD_DP_AUXCH_OD_CTRL_PARAMS *pParams) { return pDispCommon->__dispcmnCtrlCmdDfpInternalLcdOverdrive__(pDispCommon, pParams); } +NV_STATUS dispcmnCtrlCmdDfpExecuteInternalLcdOverDrivePolicy_IMPL(struct DispCommon *pDispCommon, NV0073_CTRL_DP_EXECUTE_OVERDRIVE_POLICY_PARAMS *pParams); + +static inline NV_STATUS dispcmnCtrlCmdDfpExecuteInternalLcdOverDrivePolicy_DISPATCH(struct DispCommon *pDispCommon, NV0073_CTRL_DP_EXECUTE_OVERDRIVE_POLICY_PARAMS *pParams) { + return pDispCommon->__dispcmnCtrlCmdDfpExecuteInternalLcdOverDrivePolicy__(pDispCommon, pParams); +} + NV_STATUS dispcmnCtrlCmdSystemExecuteAcpiMethod_IMPL(struct DispCommon *pDispCommon, NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_PARAMS *pAcpiMethodParams); static inline NV_STATUS dispcmnCtrlCmdSystemExecuteAcpiMethod_DISPATCH(struct DispCommon *pDispCommon, NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_PARAMS *pAcpiMethodParams) { @@ -1785,6 +1899,12 @@ return pDispCommon->__dispcmnCtrlCmdSystemGetAcpiIdMap__(pDispCommon, pAcpiIdMapParams); } +NV_STATUS dispcmnCtrlCmdSystemAcpiSubsystemActivated_IMPL(struct DispCommon *pDispCommon, NV0073_CTRL_SYSTEM_ACPI_SUBSYSTEM_ACTIVATED_PARAMS *pParams); + +static inline NV_STATUS dispcmnCtrlCmdSystemAcpiSubsystemActivated_DISPATCH(struct DispCommon *pDispCommon, NV0073_CTRL_SYSTEM_ACPI_SUBSYSTEM_ACTIVATED_PARAMS *pParams) { + return pDispCommon->__dispcmnCtrlCmdSystemAcpiSubsystemActivated__(pDispCommon, pParams); +} + NV_STATUS dispcmnCtrlCmdSpecificSetAcpiIdMapping_IMPL(struct DispCommon *pDispCommon, NV0073_CTRL_SPECIFIC_SET_ACPI_ID_MAPPING_PARAMS *pParams); static inline NV_STATUS dispcmnCtrlCmdSpecificSetAcpiIdMapping_DISPATCH(struct DispCommon *pDispCommon, NV0073_CTRL_SPECIFIC_SET_ACPI_ID_MAPPING_PARAMS *pParams) { @@ -2043,6 +2163,12 @@ return pDispCommon->__dispcmnCtrlCmdSpecificIsDirectmodeDisplay__(pDispCommon, pParams); } +NV_STATUS dispcmnCtrlCmdSpecificDefaultAdaptivesyncDisplay_IMPL(struct DispCommon *pDispCommon, NV0073_CTRL_SPECIFIC_DEFAULT_ADAPTIVESYNC_DISPLAY_PARAMS *pParams); + +static inline NV_STATUS dispcmnCtrlCmdSpecificDefaultAdaptivesyncDisplay_DISPATCH(struct DispCommon *pDispCommon, NV0073_CTRL_SPECIFIC_DEFAULT_ADAPTIVESYNC_DISPLAY_PARAMS *pParams) { + return pDispCommon->__dispcmnCtrlCmdSpecificDefaultAdaptivesyncDisplay__(pDispCommon, pParams); +} + NV_STATUS dispcmnCtrlCmdSpecificSetHdmiFrlCapacityComputation_IMPL(struct DispCommon *pDispCommon, NV0073_CTRL_SPECIFIC_GET_HDMI_FRL_CAPACITY_COMPUTATION_PARAMS *pParams); static inline NV_STATUS dispcmnCtrlCmdSpecificSetHdmiFrlCapacityComputation_DISPATCH(struct DispCommon *pDispCommon, NV0073_CTRL_SPECIFIC_GET_HDMI_FRL_CAPACITY_COMPUTATION_PARAMS *pParams) { @@ -2061,6 +2187,12 @@ return pDispCommon->__dispcmnCtrlCmdSpecificGetValidHeadWindowAssignment__(pDispCommon, pParams); } +NV_STATUS dispcmnCtrlCmdSpecificSetHdmiAudioMutestream_IMPL(struct DispCommon *pDispCommon, NV0073_CTRL_CMD_SPECIFIC_SET_HDMI_AUDIO_MUTESTREAM_PARAMS *pParams); + +static inline NV_STATUS dispcmnCtrlCmdSpecificSetHdmiAudioMutestream_DISPATCH(struct DispCommon *pDispCommon, NV0073_CTRL_CMD_SPECIFIC_SET_HDMI_AUDIO_MUTESTREAM_PARAMS *pParams) { + return pDispCommon->__dispcmnCtrlCmdSpecificSetHdmiAudioMutestream__(pDispCommon, pParams); +} + NV_STATUS dispcmnCtrlCmdDfpGetInfo_IMPL(struct DispCommon *pDispCommon, NV0073_CTRL_DFP_GET_INFO_PARAMS *pParams); static inline NV_STATUS dispcmnCtrlCmdDfpGetInfo_DISPATCH(struct DispCommon *pDispCommon, NV0073_CTRL_DFP_GET_INFO_PARAMS *pParams) { @@ -2329,90 +2461,98 @@ return pResource->__dispcmnShareCallback__(pResource, pInvokingClient, pParentRef, pSharePolicy); } -static inline NV_STATUS dispcmnControl_DISPATCH(struct DispCommon *pDisplayApi, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { - return pDisplayApi->__dispcmnControl__(pDisplayApi, pCallContext, pParams); +static inline NV_STATUS dispcmnCheckMemInterUnmap_DISPATCH(struct DispCommon *pRmResource, NvBool bSubdeviceHandleProvided) { + return pRmResource->__dispcmnCheckMemInterUnmap__(pRmResource, bSubdeviceHandleProvided); +} + +static inline NV_STATUS dispcmnMapTo_DISPATCH(struct DispCommon *pResource, RS_RES_MAP_TO_PARAMS *pParams) { + return pResource->__dispcmnMapTo__(pResource, pParams); } static inline NvBool dispcmnAccessCallback_DISPATCH(struct DispCommon *pResource, struct RsClient *pInvokingClient, void *pAllocParams, RsAccessRight accessRight) { return pResource->__dispcmnAccessCallback__(pResource, pInvokingClient, pAllocParams, accessRight); } -static inline NV_STATUS dispcmnGetMemInterMapParams_DISPATCH(struct DispCommon *pRmResource, RMRES_MEM_INTER_MAP_PARAMS *pParams) { - return pRmResource->__dispcmnGetMemInterMapParams__(pRmResource, pParams); +static inline void dispcmnSetNotificationShare_DISPATCH(struct DispCommon *pNotifier, struct NotifShare *pNotifShare) { + pNotifier->__dispcmnSetNotificationShare__(pNotifier, pNotifShare); } -static inline NV_STATUS dispcmnGetMemoryMappingDescriptor_DISPATCH(struct DispCommon *pRmResource, struct MEMORY_DESCRIPTOR **ppMemDesc) { - return pRmResource->__dispcmnGetMemoryMappingDescriptor__(pRmResource, ppMemDesc); +static inline NvU32 dispcmnGetRefCount_DISPATCH(struct DispCommon *pResource) { + return pResource->__dispcmnGetRefCount__(pResource); } -static inline NV_STATUS dispcmnCheckMemInterUnmap_DISPATCH(struct DispCommon *pRmResource, NvBool bSubdeviceHandleProvided) { - return pRmResource->__dispcmnCheckMemInterUnmap__(pRmResource, bSubdeviceHandleProvided); +static inline void dispcmnAddAdditionalDependants_DISPATCH(struct RsClient *pClient, struct DispCommon *pResource, RsResourceRef *pReference) { + pResource->__dispcmnAddAdditionalDependants__(pClient, pResource, pReference); } -static inline void dispcmnSetNotificationShare_DISPATCH(struct DispCommon *pNotifier, struct NotifShare *pNotifShare) { - pNotifier->__dispcmnSetNotificationShare__(pNotifier, pNotifShare); +static inline NV_STATUS dispcmnControl_Prologue_DISPATCH(struct DispCommon *pDisplayApi, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pRsParams) { + return pDisplayApi->__dispcmnControl_Prologue__(pDisplayApi, pCallContext, pRsParams); } -static inline NV_STATUS dispcmnControlFilter_DISPATCH(struct DispCommon *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { - return pResource->__dispcmnControlFilter__(pResource, pCallContext, pParams); +static inline NV_STATUS dispcmnUnmapFrom_DISPATCH(struct DispCommon *pResource, RS_RES_UNMAP_FROM_PARAMS *pParams) { + return pResource->__dispcmnUnmapFrom__(pResource, pParams); } -static inline NvU32 dispcmnGetRefCount_DISPATCH(struct DispCommon *pResource) { - return pResource->__dispcmnGetRefCount__(pResource); +static inline void dispcmnControl_Epilogue_DISPATCH(struct DispCommon *pDisplayApi, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pRsParams) { + pDisplayApi->__dispcmnControl_Epilogue__(pDisplayApi, pCallContext, pRsParams); } -static inline NV_STATUS dispcmnUnregisterEvent_DISPATCH(struct DispCommon *pNotifier, NvHandle hNotifierClient, NvHandle hNotifierResource, NvHandle hEventClient, NvHandle hEvent) { - return pNotifier->__dispcmnUnregisterEvent__(pNotifier, hNotifierClient, hNotifierResource, hEventClient, hEvent); +static inline NV_STATUS dispcmnControlLookup_DISPATCH(struct DispCommon *pResource, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams, const struct NVOC_EXPORTED_METHOD_DEF **ppEntry) { + return pResource->__dispcmnControlLookup__(pResource, pParams, ppEntry); +} + +static inline NV_STATUS dispcmnControl_DISPATCH(struct DispCommon *pDisplayApi, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return pDisplayApi->__dispcmnControl__(pDisplayApi, pCallContext, pParams); } static inline NV_STATUS dispcmnUnmap_DISPATCH(struct DispCommon *pResource, struct CALL_CONTEXT *pCallContext, RsCpuMapping *pCpuMapping) { return pResource->__dispcmnUnmap__(pResource, pCallContext, pCpuMapping); } -static inline NV_STATUS dispcmnControl_Prologue_DISPATCH(struct DispCommon *pDisplayApi, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pRsParams) { - return pDisplayApi->__dispcmnControl_Prologue__(pDisplayApi, pCallContext, pRsParams); +static inline NV_STATUS dispcmnGetMemInterMapParams_DISPATCH(struct DispCommon *pRmResource, RMRES_MEM_INTER_MAP_PARAMS *pParams) { + return pRmResource->__dispcmnGetMemInterMapParams__(pRmResource, pParams); } -static inline NvBool dispcmnCanCopy_DISPATCH(struct DispCommon *pResource) { - return pResource->__dispcmnCanCopy__(pResource); +static inline NV_STATUS dispcmnGetMemoryMappingDescriptor_DISPATCH(struct DispCommon *pRmResource, struct MEMORY_DESCRIPTOR **ppMemDesc) { + return pRmResource->__dispcmnGetMemoryMappingDescriptor__(pRmResource, ppMemDesc); } -static inline NV_STATUS dispcmnMapTo_DISPATCH(struct DispCommon *pResource, RS_RES_MAP_TO_PARAMS *pParams) { - return pResource->__dispcmnMapTo__(pResource, pParams); +static inline NV_STATUS dispcmnControlFilter_DISPATCH(struct DispCommon *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return pResource->__dispcmnControlFilter__(pResource, pCallContext, pParams); } -static inline void dispcmnAddAdditionalDependants_DISPATCH(struct RsClient *pClient, struct DispCommon *pResource, RsResourceRef *pReference) { - pResource->__dispcmnAddAdditionalDependants__(pClient, pResource, pReference); +static inline NV_STATUS dispcmnUnregisterEvent_DISPATCH(struct DispCommon *pNotifier, NvHandle hNotifierClient, NvHandle hNotifierResource, NvHandle hEventClient, NvHandle hEvent) { + return pNotifier->__dispcmnUnregisterEvent__(pNotifier, hNotifierClient, hNotifierResource, hEventClient, hEvent); } -static inline void dispcmnPreDestruct_DISPATCH(struct DispCommon *pResource) { - pResource->__dispcmnPreDestruct__(pResource); +static inline NV_STATUS dispcmnControlSerialization_Prologue_DISPATCH(struct DispCommon *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return pResource->__dispcmnControlSerialization_Prologue__(pResource, pCallContext, pParams); } -static inline NV_STATUS dispcmnUnmapFrom_DISPATCH(struct DispCommon *pResource, RS_RES_UNMAP_FROM_PARAMS *pParams) { - return pResource->__dispcmnUnmapFrom__(pResource, pParams); +static inline NvBool dispcmnCanCopy_DISPATCH(struct DispCommon *pResource) { + return pResource->__dispcmnCanCopy__(pResource); +} + +static inline void dispcmnPreDestruct_DISPATCH(struct DispCommon *pResource) { + pResource->__dispcmnPreDestruct__(pResource); } static inline NV_STATUS dispcmnIsDuplicate_DISPATCH(struct DispCommon *pResource, NvHandle hMemory, NvBool *pDuplicate) { return pResource->__dispcmnIsDuplicate__(pResource, hMemory, pDuplicate); } -static inline PEVENTNOTIFICATION *dispcmnGetNotificationListPtr_DISPATCH(struct DispCommon *pNotifier) { - return pNotifier->__dispcmnGetNotificationListPtr__(pNotifier); +static inline void dispcmnControlSerialization_Epilogue_DISPATCH(struct DispCommon *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + pResource->__dispcmnControlSerialization_Epilogue__(pResource, pCallContext, pParams); } -static inline void dispcmnControl_Epilogue_DISPATCH(struct DispCommon *pDisplayApi, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pRsParams) { - pDisplayApi->__dispcmnControl_Epilogue__(pDisplayApi, pCallContext, pRsParams); +static inline PEVENTNOTIFICATION *dispcmnGetNotificationListPtr_DISPATCH(struct DispCommon *pNotifier) { + return pNotifier->__dispcmnGetNotificationListPtr__(pNotifier); } static inline struct NotifShare *dispcmnGetNotificationShare_DISPATCH(struct DispCommon *pNotifier) { return pNotifier->__dispcmnGetNotificationShare__(pNotifier); } -static inline NV_STATUS dispcmnControlLookup_DISPATCH(struct DispCommon *pResource, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams, const struct NVOC_EXPORTED_METHOD_DEF **ppEntry) { - return pResource->__dispcmnControlLookup__(pResource, pParams, ppEntry); -} - static inline NV_STATUS dispcmnMap_DISPATCH(struct DispCommon *pResource, struct CALL_CONTEXT *pCallContext, RS_CPU_MAP_PARAMS *pParams, RsCpuMapping *pCpuMapping) { return pResource->__dispcmnMap__(pResource, pCallContext, pParams, pCpuMapping); } diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/generated/g_disp_sf_user_nvoc.c nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_disp_sf_user_nvoc.c --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/generated/g_disp_sf_user_nvoc.c 2023-10-25 20:26:55.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_disp_sf_user_nvoc.c 2024-03-05 22:18:11.000000000 +0000 @@ -101,80 +101,88 @@ return gpuresShareCallback((struct GpuResource *)(((unsigned char *)pGpuResource) + __nvoc_rtti_DispSfUser_GpuResource.offset), pInvokingClient, pParentRef, pSharePolicy); } -static NV_STATUS __nvoc_thunk_GpuResource_dispsfControl(struct DispSfUser *pGpuResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { - return gpuresControl((struct GpuResource *)(((unsigned char *)pGpuResource) + __nvoc_rtti_DispSfUser_GpuResource.offset), pCallContext, pParams); +static NV_STATUS __nvoc_thunk_RmResource_dispsfCheckMemInterUnmap(struct DispSfUser *pRmResource, NvBool bSubdeviceHandleProvided) { + return rmresCheckMemInterUnmap((struct RmResource *)(((unsigned char *)pRmResource) + __nvoc_rtti_DispSfUser_RmResource.offset), bSubdeviceHandleProvided); } -static NV_STATUS __nvoc_thunk_GpuResource_dispsfUnmap(struct DispSfUser *pGpuResource, struct CALL_CONTEXT *pCallContext, struct RsCpuMapping *pCpuMapping) { - return gpuresUnmap((struct GpuResource *)(((unsigned char *)pGpuResource) + __nvoc_rtti_DispSfUser_GpuResource.offset), pCallContext, pCpuMapping); +static NV_STATUS __nvoc_thunk_RsResource_dispsfMapTo(struct DispSfUser *pResource, RS_RES_MAP_TO_PARAMS *pParams) { + return resMapTo((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_DispSfUser_RsResource.offset), pParams); } -static NV_STATUS __nvoc_thunk_RmResource_dispsfGetMemInterMapParams(struct DispSfUser *pRmResource, RMRES_MEM_INTER_MAP_PARAMS *pParams) { - return rmresGetMemInterMapParams((struct RmResource *)(((unsigned char *)pRmResource) + __nvoc_rtti_DispSfUser_RmResource.offset), pParams); +static NV_STATUS __nvoc_thunk_GpuResource_dispsfGetMapAddrSpace(struct DispSfUser *pGpuResource, struct CALL_CONTEXT *pCallContext, NvU32 mapFlags, NV_ADDRESS_SPACE *pAddrSpace) { + return gpuresGetMapAddrSpace((struct GpuResource *)(((unsigned char *)pGpuResource) + __nvoc_rtti_DispSfUser_GpuResource.offset), pCallContext, mapFlags, pAddrSpace); } -static NV_STATUS __nvoc_thunk_RmResource_dispsfGetMemoryMappingDescriptor(struct DispSfUser *pRmResource, struct MEMORY_DESCRIPTOR **ppMemDesc) { - return rmresGetMemoryMappingDescriptor((struct RmResource *)(((unsigned char *)pRmResource) + __nvoc_rtti_DispSfUser_RmResource.offset), ppMemDesc); +static NvU32 __nvoc_thunk_RsResource_dispsfGetRefCount(struct DispSfUser *pResource) { + return resGetRefCount((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_DispSfUser_RsResource.offset)); } -static NV_STATUS __nvoc_thunk_GpuResource_dispsfGetMapAddrSpace(struct DispSfUser *pGpuResource, struct CALL_CONTEXT *pCallContext, NvU32 mapFlags, NV_ADDRESS_SPACE *pAddrSpace) { - return gpuresGetMapAddrSpace((struct GpuResource *)(((unsigned char *)pGpuResource) + __nvoc_rtti_DispSfUser_GpuResource.offset), pCallContext, mapFlags, pAddrSpace); +static void __nvoc_thunk_RsResource_dispsfAddAdditionalDependants(struct RsClient *pClient, struct DispSfUser *pResource, RsResourceRef *pReference) { + resAddAdditionalDependants(pClient, (struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_DispSfUser_RsResource.offset), pReference); +} + +static NV_STATUS __nvoc_thunk_RmResource_dispsfControl_Prologue(struct DispSfUser *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return rmresControl_Prologue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_DispSfUser_RmResource.offset), pCallContext, pParams); +} + +static NV_STATUS __nvoc_thunk_GpuResource_dispsfInternalControlForward(struct DispSfUser *pGpuResource, NvU32 command, void *pParams, NvU32 size) { + return gpuresInternalControlForward((struct GpuResource *)(((unsigned char *)pGpuResource) + __nvoc_rtti_DispSfUser_GpuResource.offset), command, pParams, size); +} + +static NV_STATUS __nvoc_thunk_RsResource_dispsfUnmapFrom(struct DispSfUser *pResource, RS_RES_UNMAP_FROM_PARAMS *pParams) { + return resUnmapFrom((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_DispSfUser_RsResource.offset), pParams); +} + +static void __nvoc_thunk_RmResource_dispsfControl_Epilogue(struct DispSfUser *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + rmresControl_Epilogue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_DispSfUser_RmResource.offset), pCallContext, pParams); +} + +static NV_STATUS __nvoc_thunk_RsResource_dispsfControlLookup(struct DispSfUser *pResource, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams, const struct NVOC_EXPORTED_METHOD_DEF **ppEntry) { + return resControlLookup((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_DispSfUser_RsResource.offset), pParams, ppEntry); } static NvHandle __nvoc_thunk_GpuResource_dispsfGetInternalObjectHandle(struct DispSfUser *pGpuResource) { return gpuresGetInternalObjectHandle((struct GpuResource *)(((unsigned char *)pGpuResource) + __nvoc_rtti_DispSfUser_GpuResource.offset)); } -static NV_STATUS __nvoc_thunk_RsResource_dispsfControlFilter(struct DispSfUser *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { - return resControlFilter((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_DispSfUser_RsResource.offset), pCallContext, pParams); +static NV_STATUS __nvoc_thunk_GpuResource_dispsfControl(struct DispSfUser *pGpuResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return gpuresControl((struct GpuResource *)(((unsigned char *)pGpuResource) + __nvoc_rtti_DispSfUser_GpuResource.offset), pCallContext, pParams); } -static void __nvoc_thunk_RsResource_dispsfAddAdditionalDependants(struct RsClient *pClient, struct DispSfUser *pResource, RsResourceRef *pReference) { - resAddAdditionalDependants(pClient, (struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_DispSfUser_RsResource.offset), pReference); +static NV_STATUS __nvoc_thunk_GpuResource_dispsfUnmap(struct DispSfUser *pGpuResource, struct CALL_CONTEXT *pCallContext, struct RsCpuMapping *pCpuMapping) { + return gpuresUnmap((struct GpuResource *)(((unsigned char *)pGpuResource) + __nvoc_rtti_DispSfUser_GpuResource.offset), pCallContext, pCpuMapping); } -static NvU32 __nvoc_thunk_RsResource_dispsfGetRefCount(struct DispSfUser *pResource) { - return resGetRefCount((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_DispSfUser_RsResource.offset)); +static NV_STATUS __nvoc_thunk_RmResource_dispsfGetMemInterMapParams(struct DispSfUser *pRmResource, RMRES_MEM_INTER_MAP_PARAMS *pParams) { + return rmresGetMemInterMapParams((struct RmResource *)(((unsigned char *)pRmResource) + __nvoc_rtti_DispSfUser_RmResource.offset), pParams); } -static NV_STATUS __nvoc_thunk_RmResource_dispsfCheckMemInterUnmap(struct DispSfUser *pRmResource, NvBool bSubdeviceHandleProvided) { - return rmresCheckMemInterUnmap((struct RmResource *)(((unsigned char *)pRmResource) + __nvoc_rtti_DispSfUser_RmResource.offset), bSubdeviceHandleProvided); +static NV_STATUS __nvoc_thunk_RmResource_dispsfGetMemoryMappingDescriptor(struct DispSfUser *pRmResource, struct MEMORY_DESCRIPTOR **ppMemDesc) { + return rmresGetMemoryMappingDescriptor((struct RmResource *)(((unsigned char *)pRmResource) + __nvoc_rtti_DispSfUser_RmResource.offset), ppMemDesc); } -static NV_STATUS __nvoc_thunk_RsResource_dispsfMapTo(struct DispSfUser *pResource, RS_RES_MAP_TO_PARAMS *pParams) { - return resMapTo((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_DispSfUser_RsResource.offset), pParams); +static NV_STATUS __nvoc_thunk_RsResource_dispsfControlFilter(struct DispSfUser *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return resControlFilter((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_DispSfUser_RsResource.offset), pCallContext, pParams); } -static NV_STATUS __nvoc_thunk_RmResource_dispsfControl_Prologue(struct DispSfUser *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { - return rmresControl_Prologue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_DispSfUser_RmResource.offset), pCallContext, pParams); +static NV_STATUS __nvoc_thunk_RmResource_dispsfControlSerialization_Prologue(struct DispSfUser *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return rmresControlSerialization_Prologue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_DispSfUser_RmResource.offset), pCallContext, pParams); } static NvBool __nvoc_thunk_RsResource_dispsfCanCopy(struct DispSfUser *pResource) { return resCanCopy((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_DispSfUser_RsResource.offset)); } -static NV_STATUS __nvoc_thunk_GpuResource_dispsfInternalControlForward(struct DispSfUser *pGpuResource, NvU32 command, void *pParams, NvU32 size) { - return gpuresInternalControlForward((struct GpuResource *)(((unsigned char *)pGpuResource) + __nvoc_rtti_DispSfUser_GpuResource.offset), command, pParams, size); -} - static void __nvoc_thunk_RsResource_dispsfPreDestruct(struct DispSfUser *pResource) { resPreDestruct((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_DispSfUser_RsResource.offset)); } -static NV_STATUS __nvoc_thunk_RsResource_dispsfUnmapFrom(struct DispSfUser *pResource, RS_RES_UNMAP_FROM_PARAMS *pParams) { - return resUnmapFrom((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_DispSfUser_RsResource.offset), pParams); -} - static NV_STATUS __nvoc_thunk_RsResource_dispsfIsDuplicate(struct DispSfUser *pResource, NvHandle hMemory, NvBool *pDuplicate) { return resIsDuplicate((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_DispSfUser_RsResource.offset), hMemory, pDuplicate); } -static void __nvoc_thunk_RmResource_dispsfControl_Epilogue(struct DispSfUser *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { - rmresControl_Epilogue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_DispSfUser_RmResource.offset), pCallContext, pParams); -} - -static NV_STATUS __nvoc_thunk_RsResource_dispsfControlLookup(struct DispSfUser *pResource, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams, const struct NVOC_EXPORTED_METHOD_DEF **ppEntry) { - return resControlLookup((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_DispSfUser_RsResource.offset), pParams, ppEntry); +static void __nvoc_thunk_RmResource_dispsfControlSerialization_Epilogue(struct DispSfUser *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + rmresControlSerialization_Epilogue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_DispSfUser_RmResource.offset), pCallContext, pParams); } static NV_STATUS __nvoc_thunk_GpuResource_dispsfMap(struct DispSfUser *pGpuResource, struct CALL_CONTEXT *pCallContext, struct RS_CPU_MAP_PARAMS *pParams, struct RsCpuMapping *pCpuMapping) { @@ -229,43 +237,47 @@ pThis->__dispsfShareCallback__ = &__nvoc_thunk_GpuResource_dispsfShareCallback; - pThis->__dispsfControl__ = &__nvoc_thunk_GpuResource_dispsfControl; + pThis->__dispsfCheckMemInterUnmap__ = &__nvoc_thunk_RmResource_dispsfCheckMemInterUnmap; - pThis->__dispsfUnmap__ = &__nvoc_thunk_GpuResource_dispsfUnmap; + pThis->__dispsfMapTo__ = &__nvoc_thunk_RsResource_dispsfMapTo; - pThis->__dispsfGetMemInterMapParams__ = &__nvoc_thunk_RmResource_dispsfGetMemInterMapParams; + pThis->__dispsfGetMapAddrSpace__ = &__nvoc_thunk_GpuResource_dispsfGetMapAddrSpace; - pThis->__dispsfGetMemoryMappingDescriptor__ = &__nvoc_thunk_RmResource_dispsfGetMemoryMappingDescriptor; + pThis->__dispsfGetRefCount__ = &__nvoc_thunk_RsResource_dispsfGetRefCount; - pThis->__dispsfGetMapAddrSpace__ = &__nvoc_thunk_GpuResource_dispsfGetMapAddrSpace; + pThis->__dispsfAddAdditionalDependants__ = &__nvoc_thunk_RsResource_dispsfAddAdditionalDependants; + + pThis->__dispsfControl_Prologue__ = &__nvoc_thunk_RmResource_dispsfControl_Prologue; + + pThis->__dispsfInternalControlForward__ = &__nvoc_thunk_GpuResource_dispsfInternalControlForward; + + pThis->__dispsfUnmapFrom__ = &__nvoc_thunk_RsResource_dispsfUnmapFrom; + + pThis->__dispsfControl_Epilogue__ = &__nvoc_thunk_RmResource_dispsfControl_Epilogue; + + pThis->__dispsfControlLookup__ = &__nvoc_thunk_RsResource_dispsfControlLookup; pThis->__dispsfGetInternalObjectHandle__ = &__nvoc_thunk_GpuResource_dispsfGetInternalObjectHandle; - pThis->__dispsfControlFilter__ = &__nvoc_thunk_RsResource_dispsfControlFilter; + pThis->__dispsfControl__ = &__nvoc_thunk_GpuResource_dispsfControl; - pThis->__dispsfAddAdditionalDependants__ = &__nvoc_thunk_RsResource_dispsfAddAdditionalDependants; + pThis->__dispsfUnmap__ = &__nvoc_thunk_GpuResource_dispsfUnmap; - pThis->__dispsfGetRefCount__ = &__nvoc_thunk_RsResource_dispsfGetRefCount; + pThis->__dispsfGetMemInterMapParams__ = &__nvoc_thunk_RmResource_dispsfGetMemInterMapParams; - pThis->__dispsfCheckMemInterUnmap__ = &__nvoc_thunk_RmResource_dispsfCheckMemInterUnmap; + pThis->__dispsfGetMemoryMappingDescriptor__ = &__nvoc_thunk_RmResource_dispsfGetMemoryMappingDescriptor; - pThis->__dispsfMapTo__ = &__nvoc_thunk_RsResource_dispsfMapTo; + pThis->__dispsfControlFilter__ = &__nvoc_thunk_RsResource_dispsfControlFilter; - pThis->__dispsfControl_Prologue__ = &__nvoc_thunk_RmResource_dispsfControl_Prologue; + pThis->__dispsfControlSerialization_Prologue__ = &__nvoc_thunk_RmResource_dispsfControlSerialization_Prologue; pThis->__dispsfCanCopy__ = &__nvoc_thunk_RsResource_dispsfCanCopy; - pThis->__dispsfInternalControlForward__ = &__nvoc_thunk_GpuResource_dispsfInternalControlForward; - pThis->__dispsfPreDestruct__ = &__nvoc_thunk_RsResource_dispsfPreDestruct; - pThis->__dispsfUnmapFrom__ = &__nvoc_thunk_RsResource_dispsfUnmapFrom; - pThis->__dispsfIsDuplicate__ = &__nvoc_thunk_RsResource_dispsfIsDuplicate; - pThis->__dispsfControl_Epilogue__ = &__nvoc_thunk_RmResource_dispsfControl_Epilogue; - - pThis->__dispsfControlLookup__ = &__nvoc_thunk_RsResource_dispsfControlLookup; + pThis->__dispsfControlSerialization_Epilogue__ = &__nvoc_thunk_RmResource_dispsfControlSerialization_Epilogue; pThis->__dispsfMap__ = &__nvoc_thunk_GpuResource_dispsfMap; @@ -293,13 +305,16 @@ Object *pParentObj; DispSfUser *pThis; - pThis = portMemAllocNonPaged(sizeof(DispSfUser)); - if (pThis == NULL) return NV_ERR_NO_MEMORY; + status = __nvoc_handleObjCreateMemAlloc(createFlags, sizeof(DispSfUser), (void**)&pThis, (void**)ppThis); + if (status != NV_OK) + return status; portMemSet(pThis, 0, sizeof(DispSfUser)); __nvoc_initRtti(staticCast(pThis, Dynamic), &__nvoc_class_def_DispSfUser); + pThis->__nvoc_base_GpuResource.__nvoc_base_RmResource.__nvoc_base_RsResource.__nvoc_base_Object.createFlags = createFlags; + if (pParent != NULL && !(createFlags & NVOC_OBJ_CREATE_FLAGS_PARENT_HALSPEC_ONLY)) { pParentObj = dynamicCast(pParent, Object); @@ -315,11 +330,17 @@ if (status != NV_OK) goto __nvoc_objCreate_DispSfUser_cleanup; *ppThis = pThis; + return NV_OK; __nvoc_objCreate_DispSfUser_cleanup: // do not call destructors here since the constructor already called them - portMemFree(pThis); + if (createFlags & NVOC_OBJ_CREATE_FLAGS_IN_PLACE_CONSTRUCT) + portMemSet(pThis, 0, sizeof(DispSfUser)); + else + portMemFree(pThis); + + // coverity[leaked_storage:FALSE] return status; } diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/generated/g_disp_sf_user_nvoc.h nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_disp_sf_user_nvoc.h --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/generated/g_disp_sf_user_nvoc.h 2023-10-25 20:26:55.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_disp_sf_user_nvoc.h 2024-03-05 22:18:12.000000000 +0000 @@ -62,25 +62,27 @@ struct DispSfUser *__nvoc_pbase_DispSfUser; NV_STATUS (*__dispsfGetRegBaseOffsetAndSize__)(struct DispSfUser *, struct OBJGPU *, NvU32 *, NvU32 *); NvBool (*__dispsfShareCallback__)(struct DispSfUser *, struct RsClient *, struct RsResourceRef *, RS_SHARE_POLICY *); + NV_STATUS (*__dispsfCheckMemInterUnmap__)(struct DispSfUser *, NvBool); + NV_STATUS (*__dispsfMapTo__)(struct DispSfUser *, RS_RES_MAP_TO_PARAMS *); + NV_STATUS (*__dispsfGetMapAddrSpace__)(struct DispSfUser *, struct CALL_CONTEXT *, NvU32, NV_ADDRESS_SPACE *); + NvU32 (*__dispsfGetRefCount__)(struct DispSfUser *); + void (*__dispsfAddAdditionalDependants__)(struct RsClient *, struct DispSfUser *, RsResourceRef *); + NV_STATUS (*__dispsfControl_Prologue__)(struct DispSfUser *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); + NV_STATUS (*__dispsfInternalControlForward__)(struct DispSfUser *, NvU32, void *, NvU32); + NV_STATUS (*__dispsfUnmapFrom__)(struct DispSfUser *, RS_RES_UNMAP_FROM_PARAMS *); + void (*__dispsfControl_Epilogue__)(struct DispSfUser *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); + NV_STATUS (*__dispsfControlLookup__)(struct DispSfUser *, struct RS_RES_CONTROL_PARAMS_INTERNAL *, const struct NVOC_EXPORTED_METHOD_DEF **); + NvHandle (*__dispsfGetInternalObjectHandle__)(struct DispSfUser *); NV_STATUS (*__dispsfControl__)(struct DispSfUser *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); NV_STATUS (*__dispsfUnmap__)(struct DispSfUser *, struct CALL_CONTEXT *, struct RsCpuMapping *); NV_STATUS (*__dispsfGetMemInterMapParams__)(struct DispSfUser *, RMRES_MEM_INTER_MAP_PARAMS *); NV_STATUS (*__dispsfGetMemoryMappingDescriptor__)(struct DispSfUser *, struct MEMORY_DESCRIPTOR **); - NV_STATUS (*__dispsfGetMapAddrSpace__)(struct DispSfUser *, struct CALL_CONTEXT *, NvU32, NV_ADDRESS_SPACE *); - NvHandle (*__dispsfGetInternalObjectHandle__)(struct DispSfUser *); NV_STATUS (*__dispsfControlFilter__)(struct DispSfUser *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); - void (*__dispsfAddAdditionalDependants__)(struct RsClient *, struct DispSfUser *, RsResourceRef *); - NvU32 (*__dispsfGetRefCount__)(struct DispSfUser *); - NV_STATUS (*__dispsfCheckMemInterUnmap__)(struct DispSfUser *, NvBool); - NV_STATUS (*__dispsfMapTo__)(struct DispSfUser *, RS_RES_MAP_TO_PARAMS *); - NV_STATUS (*__dispsfControl_Prologue__)(struct DispSfUser *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); + NV_STATUS (*__dispsfControlSerialization_Prologue__)(struct DispSfUser *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); NvBool (*__dispsfCanCopy__)(struct DispSfUser *); - NV_STATUS (*__dispsfInternalControlForward__)(struct DispSfUser *, NvU32, void *, NvU32); void (*__dispsfPreDestruct__)(struct DispSfUser *); - NV_STATUS (*__dispsfUnmapFrom__)(struct DispSfUser *, RS_RES_UNMAP_FROM_PARAMS *); NV_STATUS (*__dispsfIsDuplicate__)(struct DispSfUser *, NvHandle, NvBool *); - void (*__dispsfControl_Epilogue__)(struct DispSfUser *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); - NV_STATUS (*__dispsfControlLookup__)(struct DispSfUser *, struct RS_RES_CONTROL_PARAMS_INTERNAL *, const struct NVOC_EXPORTED_METHOD_DEF **); + void (*__dispsfControlSerialization_Epilogue__)(struct DispSfUser *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); NV_STATUS (*__dispsfMap__)(struct DispSfUser *, struct CALL_CONTEXT *, struct RS_CPU_MAP_PARAMS *, struct RsCpuMapping *); NvBool (*__dispsfAccessCallback__)(struct DispSfUser *, struct RsClient *, void *, RsAccessRight); NvU32 ControlOffset; @@ -117,25 +119,27 @@ #define dispsfGetRegBaseOffsetAndSize(pDispSfUser, pGpu, pOffset, pSize) dispsfGetRegBaseOffsetAndSize_DISPATCH(pDispSfUser, pGpu, pOffset, pSize) #define dispsfShareCallback(pGpuResource, pInvokingClient, pParentRef, pSharePolicy) dispsfShareCallback_DISPATCH(pGpuResource, pInvokingClient, pParentRef, pSharePolicy) +#define dispsfCheckMemInterUnmap(pRmResource, bSubdeviceHandleProvided) dispsfCheckMemInterUnmap_DISPATCH(pRmResource, bSubdeviceHandleProvided) +#define dispsfMapTo(pResource, pParams) dispsfMapTo_DISPATCH(pResource, pParams) +#define dispsfGetMapAddrSpace(pGpuResource, pCallContext, mapFlags, pAddrSpace) dispsfGetMapAddrSpace_DISPATCH(pGpuResource, pCallContext, mapFlags, pAddrSpace) +#define dispsfGetRefCount(pResource) dispsfGetRefCount_DISPATCH(pResource) +#define dispsfAddAdditionalDependants(pClient, pResource, pReference) dispsfAddAdditionalDependants_DISPATCH(pClient, pResource, pReference) +#define dispsfControl_Prologue(pResource, pCallContext, pParams) dispsfControl_Prologue_DISPATCH(pResource, pCallContext, pParams) +#define dispsfInternalControlForward(pGpuResource, command, pParams, size) dispsfInternalControlForward_DISPATCH(pGpuResource, command, pParams, size) +#define dispsfUnmapFrom(pResource, pParams) dispsfUnmapFrom_DISPATCH(pResource, pParams) +#define dispsfControl_Epilogue(pResource, pCallContext, pParams) dispsfControl_Epilogue_DISPATCH(pResource, pCallContext, pParams) +#define dispsfControlLookup(pResource, pParams, ppEntry) dispsfControlLookup_DISPATCH(pResource, pParams, ppEntry) +#define dispsfGetInternalObjectHandle(pGpuResource) dispsfGetInternalObjectHandle_DISPATCH(pGpuResource) #define dispsfControl(pGpuResource, pCallContext, pParams) dispsfControl_DISPATCH(pGpuResource, pCallContext, pParams) #define dispsfUnmap(pGpuResource, pCallContext, pCpuMapping) dispsfUnmap_DISPATCH(pGpuResource, pCallContext, pCpuMapping) #define dispsfGetMemInterMapParams(pRmResource, pParams) dispsfGetMemInterMapParams_DISPATCH(pRmResource, pParams) #define dispsfGetMemoryMappingDescriptor(pRmResource, ppMemDesc) dispsfGetMemoryMappingDescriptor_DISPATCH(pRmResource, ppMemDesc) -#define dispsfGetMapAddrSpace(pGpuResource, pCallContext, mapFlags, pAddrSpace) dispsfGetMapAddrSpace_DISPATCH(pGpuResource, pCallContext, mapFlags, pAddrSpace) -#define dispsfGetInternalObjectHandle(pGpuResource) dispsfGetInternalObjectHandle_DISPATCH(pGpuResource) #define dispsfControlFilter(pResource, pCallContext, pParams) dispsfControlFilter_DISPATCH(pResource, pCallContext, pParams) -#define dispsfAddAdditionalDependants(pClient, pResource, pReference) dispsfAddAdditionalDependants_DISPATCH(pClient, pResource, pReference) -#define dispsfGetRefCount(pResource) dispsfGetRefCount_DISPATCH(pResource) -#define dispsfCheckMemInterUnmap(pRmResource, bSubdeviceHandleProvided) dispsfCheckMemInterUnmap_DISPATCH(pRmResource, bSubdeviceHandleProvided) -#define dispsfMapTo(pResource, pParams) dispsfMapTo_DISPATCH(pResource, pParams) -#define dispsfControl_Prologue(pResource, pCallContext, pParams) dispsfControl_Prologue_DISPATCH(pResource, pCallContext, pParams) +#define dispsfControlSerialization_Prologue(pResource, pCallContext, pParams) dispsfControlSerialization_Prologue_DISPATCH(pResource, pCallContext, pParams) #define dispsfCanCopy(pResource) dispsfCanCopy_DISPATCH(pResource) -#define dispsfInternalControlForward(pGpuResource, command, pParams, size) dispsfInternalControlForward_DISPATCH(pGpuResource, command, pParams, size) #define dispsfPreDestruct(pResource) dispsfPreDestruct_DISPATCH(pResource) -#define dispsfUnmapFrom(pResource, pParams) dispsfUnmapFrom_DISPATCH(pResource, pParams) #define dispsfIsDuplicate(pResource, hMemory, pDuplicate) dispsfIsDuplicate_DISPATCH(pResource, hMemory, pDuplicate) -#define dispsfControl_Epilogue(pResource, pCallContext, pParams) dispsfControl_Epilogue_DISPATCH(pResource, pCallContext, pParams) -#define dispsfControlLookup(pResource, pParams, ppEntry) dispsfControlLookup_DISPATCH(pResource, pParams, ppEntry) +#define dispsfControlSerialization_Epilogue(pResource, pCallContext, pParams) dispsfControlSerialization_Epilogue_DISPATCH(pResource, pCallContext, pParams) #define dispsfMap(pGpuResource, pCallContext, pParams, pCpuMapping) dispsfMap_DISPATCH(pGpuResource, pCallContext, pParams, pCpuMapping) #define dispsfAccessCallback(pResource, pInvokingClient, pAllocParams, accessRight) dispsfAccessCallback_DISPATCH(pResource, pInvokingClient, pAllocParams, accessRight) NV_STATUS dispsfGetRegBaseOffsetAndSize_IMPL(struct DispSfUser *pDispSfUser, struct OBJGPU *pGpu, NvU32 *pOffset, NvU32 *pSize); @@ -148,80 +152,88 @@ return pGpuResource->__dispsfShareCallback__(pGpuResource, pInvokingClient, pParentRef, pSharePolicy); } -static inline NV_STATUS dispsfControl_DISPATCH(struct DispSfUser *pGpuResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { - return pGpuResource->__dispsfControl__(pGpuResource, pCallContext, pParams); +static inline NV_STATUS dispsfCheckMemInterUnmap_DISPATCH(struct DispSfUser *pRmResource, NvBool bSubdeviceHandleProvided) { + return pRmResource->__dispsfCheckMemInterUnmap__(pRmResource, bSubdeviceHandleProvided); } -static inline NV_STATUS dispsfUnmap_DISPATCH(struct DispSfUser *pGpuResource, struct CALL_CONTEXT *pCallContext, struct RsCpuMapping *pCpuMapping) { - return pGpuResource->__dispsfUnmap__(pGpuResource, pCallContext, pCpuMapping); +static inline NV_STATUS dispsfMapTo_DISPATCH(struct DispSfUser *pResource, RS_RES_MAP_TO_PARAMS *pParams) { + return pResource->__dispsfMapTo__(pResource, pParams); } -static inline NV_STATUS dispsfGetMemInterMapParams_DISPATCH(struct DispSfUser *pRmResource, RMRES_MEM_INTER_MAP_PARAMS *pParams) { - return pRmResource->__dispsfGetMemInterMapParams__(pRmResource, pParams); +static inline NV_STATUS dispsfGetMapAddrSpace_DISPATCH(struct DispSfUser *pGpuResource, struct CALL_CONTEXT *pCallContext, NvU32 mapFlags, NV_ADDRESS_SPACE *pAddrSpace) { + return pGpuResource->__dispsfGetMapAddrSpace__(pGpuResource, pCallContext, mapFlags, pAddrSpace); } -static inline NV_STATUS dispsfGetMemoryMappingDescriptor_DISPATCH(struct DispSfUser *pRmResource, struct MEMORY_DESCRIPTOR **ppMemDesc) { - return pRmResource->__dispsfGetMemoryMappingDescriptor__(pRmResource, ppMemDesc); +static inline NvU32 dispsfGetRefCount_DISPATCH(struct DispSfUser *pResource) { + return pResource->__dispsfGetRefCount__(pResource); } -static inline NV_STATUS dispsfGetMapAddrSpace_DISPATCH(struct DispSfUser *pGpuResource, struct CALL_CONTEXT *pCallContext, NvU32 mapFlags, NV_ADDRESS_SPACE *pAddrSpace) { - return pGpuResource->__dispsfGetMapAddrSpace__(pGpuResource, pCallContext, mapFlags, pAddrSpace); +static inline void dispsfAddAdditionalDependants_DISPATCH(struct RsClient *pClient, struct DispSfUser *pResource, RsResourceRef *pReference) { + pResource->__dispsfAddAdditionalDependants__(pClient, pResource, pReference); +} + +static inline NV_STATUS dispsfControl_Prologue_DISPATCH(struct DispSfUser *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return pResource->__dispsfControl_Prologue__(pResource, pCallContext, pParams); +} + +static inline NV_STATUS dispsfInternalControlForward_DISPATCH(struct DispSfUser *pGpuResource, NvU32 command, void *pParams, NvU32 size) { + return pGpuResource->__dispsfInternalControlForward__(pGpuResource, command, pParams, size); +} + +static inline NV_STATUS dispsfUnmapFrom_DISPATCH(struct DispSfUser *pResource, RS_RES_UNMAP_FROM_PARAMS *pParams) { + return pResource->__dispsfUnmapFrom__(pResource, pParams); +} + +static inline void dispsfControl_Epilogue_DISPATCH(struct DispSfUser *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + pResource->__dispsfControl_Epilogue__(pResource, pCallContext, pParams); +} + +static inline NV_STATUS dispsfControlLookup_DISPATCH(struct DispSfUser *pResource, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams, const struct NVOC_EXPORTED_METHOD_DEF **ppEntry) { + return pResource->__dispsfControlLookup__(pResource, pParams, ppEntry); } static inline NvHandle dispsfGetInternalObjectHandle_DISPATCH(struct DispSfUser *pGpuResource) { return pGpuResource->__dispsfGetInternalObjectHandle__(pGpuResource); } -static inline NV_STATUS dispsfControlFilter_DISPATCH(struct DispSfUser *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { - return pResource->__dispsfControlFilter__(pResource, pCallContext, pParams); +static inline NV_STATUS dispsfControl_DISPATCH(struct DispSfUser *pGpuResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return pGpuResource->__dispsfControl__(pGpuResource, pCallContext, pParams); } -static inline void dispsfAddAdditionalDependants_DISPATCH(struct RsClient *pClient, struct DispSfUser *pResource, RsResourceRef *pReference) { - pResource->__dispsfAddAdditionalDependants__(pClient, pResource, pReference); +static inline NV_STATUS dispsfUnmap_DISPATCH(struct DispSfUser *pGpuResource, struct CALL_CONTEXT *pCallContext, struct RsCpuMapping *pCpuMapping) { + return pGpuResource->__dispsfUnmap__(pGpuResource, pCallContext, pCpuMapping); } -static inline NvU32 dispsfGetRefCount_DISPATCH(struct DispSfUser *pResource) { - return pResource->__dispsfGetRefCount__(pResource); +static inline NV_STATUS dispsfGetMemInterMapParams_DISPATCH(struct DispSfUser *pRmResource, RMRES_MEM_INTER_MAP_PARAMS *pParams) { + return pRmResource->__dispsfGetMemInterMapParams__(pRmResource, pParams); } -static inline NV_STATUS dispsfCheckMemInterUnmap_DISPATCH(struct DispSfUser *pRmResource, NvBool bSubdeviceHandleProvided) { - return pRmResource->__dispsfCheckMemInterUnmap__(pRmResource, bSubdeviceHandleProvided); +static inline NV_STATUS dispsfGetMemoryMappingDescriptor_DISPATCH(struct DispSfUser *pRmResource, struct MEMORY_DESCRIPTOR **ppMemDesc) { + return pRmResource->__dispsfGetMemoryMappingDescriptor__(pRmResource, ppMemDesc); } -static inline NV_STATUS dispsfMapTo_DISPATCH(struct DispSfUser *pResource, RS_RES_MAP_TO_PARAMS *pParams) { - return pResource->__dispsfMapTo__(pResource, pParams); +static inline NV_STATUS dispsfControlFilter_DISPATCH(struct DispSfUser *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return pResource->__dispsfControlFilter__(pResource, pCallContext, pParams); } -static inline NV_STATUS dispsfControl_Prologue_DISPATCH(struct DispSfUser *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { - return pResource->__dispsfControl_Prologue__(pResource, pCallContext, pParams); +static inline NV_STATUS dispsfControlSerialization_Prologue_DISPATCH(struct DispSfUser *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return pResource->__dispsfControlSerialization_Prologue__(pResource, pCallContext, pParams); } static inline NvBool dispsfCanCopy_DISPATCH(struct DispSfUser *pResource) { return pResource->__dispsfCanCopy__(pResource); } -static inline NV_STATUS dispsfInternalControlForward_DISPATCH(struct DispSfUser *pGpuResource, NvU32 command, void *pParams, NvU32 size) { - return pGpuResource->__dispsfInternalControlForward__(pGpuResource, command, pParams, size); -} - static inline void dispsfPreDestruct_DISPATCH(struct DispSfUser *pResource) { pResource->__dispsfPreDestruct__(pResource); } -static inline NV_STATUS dispsfUnmapFrom_DISPATCH(struct DispSfUser *pResource, RS_RES_UNMAP_FROM_PARAMS *pParams) { - return pResource->__dispsfUnmapFrom__(pResource, pParams); -} - static inline NV_STATUS dispsfIsDuplicate_DISPATCH(struct DispSfUser *pResource, NvHandle hMemory, NvBool *pDuplicate) { return pResource->__dispsfIsDuplicate__(pResource, hMemory, pDuplicate); } -static inline void dispsfControl_Epilogue_DISPATCH(struct DispSfUser *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { - pResource->__dispsfControl_Epilogue__(pResource, pCallContext, pParams); -} - -static inline NV_STATUS dispsfControlLookup_DISPATCH(struct DispSfUser *pResource, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams, const struct NVOC_EXPORTED_METHOD_DEF **ppEntry) { - return pResource->__dispsfControlLookup__(pResource, pParams, ppEntry); +static inline void dispsfControlSerialization_Epilogue_DISPATCH(struct DispSfUser *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + pResource->__dispsfControlSerialization_Epilogue__(pResource, pCallContext, pParams); } static inline NV_STATUS dispsfMap_DISPATCH(struct DispSfUser *pGpuResource, struct CALL_CONTEXT *pCallContext, struct RS_CPU_MAP_PARAMS *pParams, struct RsCpuMapping *pCpuMapping) { diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/generated/g_dispsw_nvoc.c nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_dispsw_nvoc.c --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/generated/g_dispsw_nvoc.c 2023-10-25 20:26:55.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_dispsw_nvoc.c 2024-03-05 22:18:12.000000000 +0000 @@ -120,7 +120,7 @@ /*pExportInfo=*/ &__nvoc_export_info_DispSwObject }; -static NV_STATUS __nvoc_thunk_DispSwObject_chandesGetSwMethods(struct ChannelDescendant *pDispSw, METHOD **ppMethods, NvU32 *pNumMethods) { +static NV_STATUS __nvoc_thunk_DispSwObject_chandesGetSwMethods(struct ChannelDescendant *pDispSw, const METHOD **ppMethods, NvU32 *pNumMethods) { return dispswGetSwMethods((struct DispSwObject *)(((unsigned char *)pDispSw) - __nvoc_rtti_DispSwObject_ChannelDescendant.offset), ppMethods, pNumMethods); } @@ -212,6 +212,10 @@ return notifyUnregisterEvent((struct Notifier *)(((unsigned char *)pNotifier) + __nvoc_rtti_DispSwObject_Notifier.offset), hNotifierClient, hNotifierResource, hEventClient, hEvent); } +static NV_STATUS __nvoc_thunk_RmResource_dispswControlSerialization_Prologue(struct DispSwObject *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return rmresControlSerialization_Prologue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_DispSwObject_RmResource.offset), pCallContext, pParams); +} + static NvBool __nvoc_thunk_RsResource_dispswCanCopy(struct DispSwObject *pResource) { return resCanCopy((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_DispSwObject_RsResource.offset)); } @@ -224,6 +228,10 @@ return resIsDuplicate((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_DispSwObject_RsResource.offset), hMemory, pDuplicate); } +static void __nvoc_thunk_RmResource_dispswControlSerialization_Epilogue(struct DispSwObject *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + rmresControlSerialization_Epilogue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_DispSwObject_RmResource.offset), pCallContext, pParams); +} + static PEVENTNOTIFICATION *__nvoc_thunk_Notifier_dispswGetNotificationListPtr(struct DispSwObject *pNotifier) { return notifyGetNotificationListPtr((struct Notifier *)(((unsigned char *)pNotifier) + __nvoc_rtti_DispSwObject_Notifier.offset)); } @@ -314,10 +322,7 @@ PORT_UNREFERENCED_VARIABLE(rmVariantHal_HalVarIdx); // Hal function -- dispswGetSwMethods - if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000002UL) )) /* RmVariantHal: PF_KERNEL_ONLY */ - { - pThis->__dispswGetSwMethods__ = &dispswGetSwMethods_46f6a7; - } + pThis->__dispswGetSwMethods__ = &dispswGetSwMethods_46f6a7; #if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) pThis->__dispswCtrlCmdNotifyOnVblank__ = &dispswCtrlCmdNotifyOnVblank_IMPL; @@ -369,12 +374,16 @@ pThis->__dispswUnregisterEvent__ = &__nvoc_thunk_Notifier_dispswUnregisterEvent; + pThis->__dispswControlSerialization_Prologue__ = &__nvoc_thunk_RmResource_dispswControlSerialization_Prologue; + pThis->__dispswCanCopy__ = &__nvoc_thunk_RsResource_dispswCanCopy; pThis->__dispswPreDestruct__ = &__nvoc_thunk_RsResource_dispswPreDestruct; pThis->__dispswIsDuplicate__ = &__nvoc_thunk_RsResource_dispswIsDuplicate; + pThis->__dispswControlSerialization_Epilogue__ = &__nvoc_thunk_RmResource_dispswControlSerialization_Epilogue; + pThis->__dispswGetNotificationListPtr__ = &__nvoc_thunk_Notifier_dispswGetNotificationListPtr; pThis->__dispswGetNotificationShare__ = &__nvoc_thunk_Notifier_dispswGetNotificationShare; @@ -409,13 +418,16 @@ DispSwObject *pThis; RmHalspecOwner *pRmhalspecowner; - pThis = portMemAllocNonPaged(sizeof(DispSwObject)); - if (pThis == NULL) return NV_ERR_NO_MEMORY; + status = __nvoc_handleObjCreateMemAlloc(createFlags, sizeof(DispSwObject), (void**)&pThis, (void**)ppThis); + if (status != NV_OK) + return status; portMemSet(pThis, 0, sizeof(DispSwObject)); __nvoc_initRtti(staticCast(pThis, Dynamic), &__nvoc_class_def_DispSwObject); + pThis->__nvoc_base_ChannelDescendant.__nvoc_base_GpuResource.__nvoc_base_RmResource.__nvoc_base_RsResource.__nvoc_base_Object.createFlags = createFlags; + if (pParent != NULL && !(createFlags & NVOC_OBJ_CREATE_FLAGS_PARENT_HALSPEC_ONLY)) { pParentObj = dynamicCast(pParent, Object); @@ -435,11 +447,17 @@ if (status != NV_OK) goto __nvoc_objCreate_DispSwObject_cleanup; *ppThis = pThis; + return NV_OK; __nvoc_objCreate_DispSwObject_cleanup: // do not call destructors here since the constructor already called them - portMemFree(pThis); + if (createFlags & NVOC_OBJ_CREATE_FLAGS_IN_PLACE_CONSTRUCT) + portMemSet(pThis, 0, sizeof(DispSwObject)); + else + portMemFree(pThis); + + // coverity[leaked_storage:FALSE] return status; } diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/generated/g_dispsw_nvoc.h nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_dispsw_nvoc.h --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/generated/g_dispsw_nvoc.h 2023-10-25 20:26:55.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_dispsw_nvoc.h 2024-03-05 22:18:12.000000000 +0000 @@ -99,7 +99,7 @@ NvU32 releasevalue, NvU32 flags, NvU32 completionStatus, - NvHandle hClient, + struct RsClient *pClient, NvHandle hEvent); /*! @@ -122,7 +122,7 @@ struct Notifier *__nvoc_pbase_Notifier; struct ChannelDescendant *__nvoc_pbase_ChannelDescendant; struct DispSwObject *__nvoc_pbase_DispSwObject; - NV_STATUS (*__dispswGetSwMethods__)(struct DispSwObject *, METHOD **, NvU32 *); + NV_STATUS (*__dispswGetSwMethods__)(struct DispSwObject *, const METHOD **, NvU32 *); NV_STATUS (*__dispswCtrlCmdNotifyOnVblank__)(struct DispSwObject *, NV9072_CTRL_CMD_NOTIFY_ON_VBLANK_PARAMS *); NV_STATUS (*__dispswCheckMemInterUnmap__)(struct DispSwObject *, NvBool); NvBool (*__dispswShareCallback__)(struct DispSwObject *, struct RsClient *, struct RsResourceRef *, RS_SHARE_POLICY *); @@ -146,9 +146,11 @@ NvBool (*__dispswIsSwMethodStalling__)(struct DispSwObject *, NvU32); NV_STATUS (*__dispswControlFilter__)(struct DispSwObject *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); NV_STATUS (*__dispswUnregisterEvent__)(struct DispSwObject *, NvHandle, NvHandle, NvHandle, NvHandle); + NV_STATUS (*__dispswControlSerialization_Prologue__)(struct DispSwObject *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); NvBool (*__dispswCanCopy__)(struct DispSwObject *); void (*__dispswPreDestruct__)(struct DispSwObject *); NV_STATUS (*__dispswIsDuplicate__)(struct DispSwObject *, NvHandle, NvBool *); + void (*__dispswControlSerialization_Epilogue__)(struct DispSwObject *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); PEVENTNOTIFICATION *(*__dispswGetNotificationListPtr__)(struct DispSwObject *); struct NotifShare *(*__dispswGetNotificationShare__)(struct DispSwObject *); NV_STATUS (*__dispswMap__)(struct DispSwObject *, struct CALL_CONTEXT *, struct RS_CPU_MAP_PARAMS *, struct RsCpuMapping *); @@ -212,18 +214,20 @@ #define dispswIsSwMethodStalling(pChannelDescendant, hHandle) dispswIsSwMethodStalling_DISPATCH(pChannelDescendant, hHandle) #define dispswControlFilter(pResource, pCallContext, pParams) dispswControlFilter_DISPATCH(pResource, pCallContext, pParams) #define dispswUnregisterEvent(pNotifier, hNotifierClient, hNotifierResource, hEventClient, hEvent) dispswUnregisterEvent_DISPATCH(pNotifier, hNotifierClient, hNotifierResource, hEventClient, hEvent) +#define dispswControlSerialization_Prologue(pResource, pCallContext, pParams) dispswControlSerialization_Prologue_DISPATCH(pResource, pCallContext, pParams) #define dispswCanCopy(pResource) dispswCanCopy_DISPATCH(pResource) #define dispswPreDestruct(pResource) dispswPreDestruct_DISPATCH(pResource) #define dispswIsDuplicate(pResource, hMemory, pDuplicate) dispswIsDuplicate_DISPATCH(pResource, hMemory, pDuplicate) +#define dispswControlSerialization_Epilogue(pResource, pCallContext, pParams) dispswControlSerialization_Epilogue_DISPATCH(pResource, pCallContext, pParams) #define dispswGetNotificationListPtr(pNotifier) dispswGetNotificationListPtr_DISPATCH(pNotifier) #define dispswGetNotificationShare(pNotifier) dispswGetNotificationShare_DISPATCH(pNotifier) #define dispswMap(pGpuResource, pCallContext, pParams, pCpuMapping) dispswMap_DISPATCH(pGpuResource, pCallContext, pParams, pCpuMapping) #define dispswGetOrAllocNotifShare(pNotifier, hNotifierClient, hNotifierResource, ppNotifShare) dispswGetOrAllocNotifShare_DISPATCH(pNotifier, hNotifierClient, hNotifierResource, ppNotifShare) -static inline NV_STATUS dispswGetSwMethods_46f6a7(struct DispSwObject *pDispSw, METHOD **ppMethods, NvU32 *pNumMethods) { +static inline NV_STATUS dispswGetSwMethods_46f6a7(struct DispSwObject *pDispSw, const METHOD **ppMethods, NvU32 *pNumMethods) { return NV_ERR_NOT_SUPPORTED; } -static inline NV_STATUS dispswGetSwMethods_DISPATCH(struct DispSwObject *pDispSw, METHOD **ppMethods, NvU32 *pNumMethods) { +static inline NV_STATUS dispswGetSwMethods_DISPATCH(struct DispSwObject *pDispSw, const METHOD **ppMethods, NvU32 *pNumMethods) { return pDispSw->__dispswGetSwMethods__(pDispSw, ppMethods, pNumMethods); } @@ -321,6 +325,10 @@ return pNotifier->__dispswUnregisterEvent__(pNotifier, hNotifierClient, hNotifierResource, hEventClient, hEvent); } +static inline NV_STATUS dispswControlSerialization_Prologue_DISPATCH(struct DispSwObject *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return pResource->__dispswControlSerialization_Prologue__(pResource, pCallContext, pParams); +} + static inline NvBool dispswCanCopy_DISPATCH(struct DispSwObject *pResource) { return pResource->__dispswCanCopy__(pResource); } @@ -333,6 +341,10 @@ return pResource->__dispswIsDuplicate__(pResource, hMemory, pDuplicate); } +static inline void dispswControlSerialization_Epilogue_DISPATCH(struct DispSwObject *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + pResource->__dispswControlSerialization_Epilogue__(pResource, pCallContext, pParams); +} + static inline PEVENTNOTIFICATION *dispswGetNotificationListPtr_DISPATCH(struct DispSwObject *pNotifier) { return pNotifier->__dispswGetNotificationListPtr__(pNotifier); } diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/generated/g_egm_mem_nvoc.c nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_egm_mem_nvoc.c --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/generated/g_egm_mem_nvoc.c 1970-01-01 00:00:00.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_egm_mem_nvoc.c 2024-03-05 22:18:12.000000000 +0000 @@ -0,0 +1,364 @@ +#define NVOC_EGM_MEM_H_PRIVATE_ACCESS_ALLOWED +#include "nvoc/runtime.h" +#include "nvoc/rtti.h" +#include "nvtypes.h" +#include "nvport/nvport.h" +#include "nvport/inline/util_valist.h" +#include "utils/nvassert.h" +#include "g_egm_mem_nvoc.h" + +#ifdef DEBUG +char __nvoc_class_id_uniqueness_check_0xeffa5c = 1; +#endif + +extern const struct NVOC_CLASS_DEF __nvoc_class_def_ExtendedGpuMemory; + +extern const struct NVOC_CLASS_DEF __nvoc_class_def_Object; + +extern const struct NVOC_CLASS_DEF __nvoc_class_def_RsResource; + +extern const struct NVOC_CLASS_DEF __nvoc_class_def_RmResourceCommon; + +extern const struct NVOC_CLASS_DEF __nvoc_class_def_RmResource; + +extern const struct NVOC_CLASS_DEF __nvoc_class_def_Memory; + +extern const struct NVOC_CLASS_DEF __nvoc_class_def_StandardMemory; + +void __nvoc_init_ExtendedGpuMemory(ExtendedGpuMemory*); +void __nvoc_init_funcTable_ExtendedGpuMemory(ExtendedGpuMemory*); +NV_STATUS __nvoc_ctor_ExtendedGpuMemory(ExtendedGpuMemory*, CALL_CONTEXT * arg_pCallContext, struct RS_RES_ALLOC_PARAMS_INTERNAL * arg_pParams); +void __nvoc_init_dataField_ExtendedGpuMemory(ExtendedGpuMemory*); +void __nvoc_dtor_ExtendedGpuMemory(ExtendedGpuMemory*); +extern const struct NVOC_EXPORT_INFO __nvoc_export_info_ExtendedGpuMemory; + +static const struct NVOC_RTTI __nvoc_rtti_ExtendedGpuMemory_ExtendedGpuMemory = { + /*pClassDef=*/ &__nvoc_class_def_ExtendedGpuMemory, + /*dtor=*/ (NVOC_DYNAMIC_DTOR) &__nvoc_dtor_ExtendedGpuMemory, + /*offset=*/ 0, +}; + +static const struct NVOC_RTTI __nvoc_rtti_ExtendedGpuMemory_Object = { + /*pClassDef=*/ &__nvoc_class_def_Object, + /*dtor=*/ &__nvoc_destructFromBase, + /*offset=*/ NV_OFFSETOF(ExtendedGpuMemory, __nvoc_base_StandardMemory.__nvoc_base_Memory.__nvoc_base_RmResource.__nvoc_base_RsResource.__nvoc_base_Object), +}; + +static const struct NVOC_RTTI __nvoc_rtti_ExtendedGpuMemory_RsResource = { + /*pClassDef=*/ &__nvoc_class_def_RsResource, + /*dtor=*/ &__nvoc_destructFromBase, + /*offset=*/ NV_OFFSETOF(ExtendedGpuMemory, __nvoc_base_StandardMemory.__nvoc_base_Memory.__nvoc_base_RmResource.__nvoc_base_RsResource), +}; + +static const struct NVOC_RTTI __nvoc_rtti_ExtendedGpuMemory_RmResourceCommon = { + /*pClassDef=*/ &__nvoc_class_def_RmResourceCommon, + /*dtor=*/ &__nvoc_destructFromBase, + /*offset=*/ NV_OFFSETOF(ExtendedGpuMemory, __nvoc_base_StandardMemory.__nvoc_base_Memory.__nvoc_base_RmResource.__nvoc_base_RmResourceCommon), +}; + +static const struct NVOC_RTTI __nvoc_rtti_ExtendedGpuMemory_RmResource = { + /*pClassDef=*/ &__nvoc_class_def_RmResource, + /*dtor=*/ &__nvoc_destructFromBase, + /*offset=*/ NV_OFFSETOF(ExtendedGpuMemory, __nvoc_base_StandardMemory.__nvoc_base_Memory.__nvoc_base_RmResource), +}; + +static const struct NVOC_RTTI __nvoc_rtti_ExtendedGpuMemory_Memory = { + /*pClassDef=*/ &__nvoc_class_def_Memory, + /*dtor=*/ &__nvoc_destructFromBase, + /*offset=*/ NV_OFFSETOF(ExtendedGpuMemory, __nvoc_base_StandardMemory.__nvoc_base_Memory), +}; + +static const struct NVOC_RTTI __nvoc_rtti_ExtendedGpuMemory_StandardMemory = { + /*pClassDef=*/ &__nvoc_class_def_StandardMemory, + /*dtor=*/ &__nvoc_destructFromBase, + /*offset=*/ NV_OFFSETOF(ExtendedGpuMemory, __nvoc_base_StandardMemory), +}; + +static const struct NVOC_CASTINFO __nvoc_castinfo_ExtendedGpuMemory = { + /*numRelatives=*/ 7, + /*relatives=*/ { + &__nvoc_rtti_ExtendedGpuMemory_ExtendedGpuMemory, + &__nvoc_rtti_ExtendedGpuMemory_StandardMemory, + &__nvoc_rtti_ExtendedGpuMemory_Memory, + &__nvoc_rtti_ExtendedGpuMemory_RmResource, + &__nvoc_rtti_ExtendedGpuMemory_RmResourceCommon, + &__nvoc_rtti_ExtendedGpuMemory_RsResource, + &__nvoc_rtti_ExtendedGpuMemory_Object, + }, +}; + +const struct NVOC_CLASS_DEF __nvoc_class_def_ExtendedGpuMemory = +{ + /*classInfo=*/ { + /*size=*/ sizeof(ExtendedGpuMemory), + /*classId=*/ classId(ExtendedGpuMemory), + /*providerId=*/ &__nvoc_rtti_provider, +#if NV_PRINTF_STRINGS_ALLOWED + /*name=*/ "ExtendedGpuMemory", +#endif + }, + /*objCreatefn=*/ (NVOC_DYNAMIC_OBJ_CREATE) &__nvoc_objCreateDynamic_ExtendedGpuMemory, + /*pCastInfo=*/ &__nvoc_castinfo_ExtendedGpuMemory, + /*pExportInfo=*/ &__nvoc_export_info_ExtendedGpuMemory +}; + +static NV_STATUS __nvoc_thunk_Memory_egmmemCheckMemInterUnmap(struct ExtendedGpuMemory *pMemory, NvBool bSubdeviceHandleProvided) { + return memCheckMemInterUnmap((struct Memory *)(((unsigned char *)pMemory) + __nvoc_rtti_ExtendedGpuMemory_Memory.offset), bSubdeviceHandleProvided); +} + +static NvBool __nvoc_thunk_RmResource_egmmemShareCallback(struct ExtendedGpuMemory *pResource, struct RsClient *pInvokingClient, struct RsResourceRef *pParentRef, RS_SHARE_POLICY *pSharePolicy) { + return rmresShareCallback((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_ExtendedGpuMemory_RmResource.offset), pInvokingClient, pParentRef, pSharePolicy); +} + +static NV_STATUS __nvoc_thunk_RsResource_egmmemMapTo(struct ExtendedGpuMemory *pResource, RS_RES_MAP_TO_PARAMS *pParams) { + return resMapTo((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_ExtendedGpuMemory_RsResource.offset), pParams); +} + +static NV_STATUS __nvoc_thunk_Memory_egmmemGetMapAddrSpace(struct ExtendedGpuMemory *pMemory, CALL_CONTEXT *pCallContext, NvU32 mapFlags, NV_ADDRESS_SPACE *pAddrSpace) { + return memGetMapAddrSpace((struct Memory *)(((unsigned char *)pMemory) + __nvoc_rtti_ExtendedGpuMemory_Memory.offset), pCallContext, mapFlags, pAddrSpace); +} + +static NvU32 __nvoc_thunk_RsResource_egmmemGetRefCount(struct ExtendedGpuMemory *pResource) { + return resGetRefCount((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_ExtendedGpuMemory_RsResource.offset)); +} + +static void __nvoc_thunk_RsResource_egmmemAddAdditionalDependants(struct RsClient *pClient, struct ExtendedGpuMemory *pResource, RsResourceRef *pReference) { + resAddAdditionalDependants(pClient, (struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_ExtendedGpuMemory_RsResource.offset), pReference); +} + +static NV_STATUS __nvoc_thunk_RmResource_egmmemControl_Prologue(struct ExtendedGpuMemory *pResource, CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return rmresControl_Prologue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_ExtendedGpuMemory_RmResource.offset), pCallContext, pParams); +} + +static NvBool __nvoc_thunk_Memory_egmmemIsGpuMapAllowed(struct ExtendedGpuMemory *pMemory, struct OBJGPU *pGpu) { + return memIsGpuMapAllowed((struct Memory *)(((unsigned char *)pMemory) + __nvoc_rtti_ExtendedGpuMemory_Memory.offset), pGpu); +} + +static NV_STATUS __nvoc_thunk_RsResource_egmmemUnmapFrom(struct ExtendedGpuMemory *pResource, RS_RES_UNMAP_FROM_PARAMS *pParams) { + return resUnmapFrom((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_ExtendedGpuMemory_RsResource.offset), pParams); +} + +static void __nvoc_thunk_RmResource_egmmemControl_Epilogue(struct ExtendedGpuMemory *pResource, CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + rmresControl_Epilogue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_ExtendedGpuMemory_RmResource.offset), pCallContext, pParams); +} + +static NV_STATUS __nvoc_thunk_RsResource_egmmemControlLookup(struct ExtendedGpuMemory *pResource, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams, const struct NVOC_EXPORTED_METHOD_DEF **ppEntry) { + return resControlLookup((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_ExtendedGpuMemory_RsResource.offset), pParams, ppEntry); +} + +static NV_STATUS __nvoc_thunk_Memory_egmmemControl(struct ExtendedGpuMemory *pMemory, CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return memControl((struct Memory *)(((unsigned char *)pMemory) + __nvoc_rtti_ExtendedGpuMemory_Memory.offset), pCallContext, pParams); +} + +static NV_STATUS __nvoc_thunk_Memory_egmmemUnmap(struct ExtendedGpuMemory *pMemory, CALL_CONTEXT *pCallContext, RsCpuMapping *pCpuMapping) { + return memUnmap((struct Memory *)(((unsigned char *)pMemory) + __nvoc_rtti_ExtendedGpuMemory_Memory.offset), pCallContext, pCpuMapping); +} + +static NV_STATUS __nvoc_thunk_Memory_egmmemGetMemInterMapParams(struct ExtendedGpuMemory *pMemory, RMRES_MEM_INTER_MAP_PARAMS *pParams) { + return memGetMemInterMapParams((struct Memory *)(((unsigned char *)pMemory) + __nvoc_rtti_ExtendedGpuMemory_Memory.offset), pParams); +} + +static NV_STATUS __nvoc_thunk_Memory_egmmemGetMemoryMappingDescriptor(struct ExtendedGpuMemory *pMemory, MEMORY_DESCRIPTOR **ppMemDesc) { + return memGetMemoryMappingDescriptor((struct Memory *)(((unsigned char *)pMemory) + __nvoc_rtti_ExtendedGpuMemory_Memory.offset), ppMemDesc); +} + +static NV_STATUS __nvoc_thunk_RsResource_egmmemControlFilter(struct ExtendedGpuMemory *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return resControlFilter((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_ExtendedGpuMemory_RsResource.offset), pCallContext, pParams); +} + +static NV_STATUS __nvoc_thunk_RmResource_egmmemControlSerialization_Prologue(struct ExtendedGpuMemory *pResource, CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return rmresControlSerialization_Prologue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_ExtendedGpuMemory_RmResource.offset), pCallContext, pParams); +} + +static NvBool __nvoc_thunk_StandardMemory_egmmemCanCopy(struct ExtendedGpuMemory *pStandardMemory) { + return stdmemCanCopy((struct StandardMemory *)(((unsigned char *)pStandardMemory) + __nvoc_rtti_ExtendedGpuMemory_StandardMemory.offset)); +} + +static NV_STATUS __nvoc_thunk_Memory_egmmemIsReady(struct ExtendedGpuMemory *pMemory, NvBool bCopyConstructorContext) { + return memIsReady((struct Memory *)(((unsigned char *)pMemory) + __nvoc_rtti_ExtendedGpuMemory_Memory.offset), bCopyConstructorContext); +} + +static NV_STATUS __nvoc_thunk_Memory_egmmemCheckCopyPermissions(struct ExtendedGpuMemory *pMemory, struct OBJGPU *pDstGpu, struct Device *pDstDevice) { + return memCheckCopyPermissions((struct Memory *)(((unsigned char *)pMemory) + __nvoc_rtti_ExtendedGpuMemory_Memory.offset), pDstGpu, pDstDevice); +} + +static void __nvoc_thunk_RsResource_egmmemPreDestruct(struct ExtendedGpuMemory *pResource) { + resPreDestruct((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_ExtendedGpuMemory_RsResource.offset)); +} + +static NV_STATUS __nvoc_thunk_Memory_egmmemIsDuplicate(struct ExtendedGpuMemory *pMemory, NvHandle hMemory, NvBool *pDuplicate) { + return memIsDuplicate((struct Memory *)(((unsigned char *)pMemory) + __nvoc_rtti_ExtendedGpuMemory_Memory.offset), hMemory, pDuplicate); +} + +static void __nvoc_thunk_RmResource_egmmemControlSerialization_Epilogue(struct ExtendedGpuMemory *pResource, CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + rmresControlSerialization_Epilogue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_ExtendedGpuMemory_RmResource.offset), pCallContext, pParams); +} + +static NV_STATUS __nvoc_thunk_Memory_egmmemMap(struct ExtendedGpuMemory *pMemory, CALL_CONTEXT *pCallContext, struct RS_CPU_MAP_PARAMS *pParams, RsCpuMapping *pCpuMapping) { + return memMap((struct Memory *)(((unsigned char *)pMemory) + __nvoc_rtti_ExtendedGpuMemory_Memory.offset), pCallContext, pParams, pCpuMapping); +} + +static NvBool __nvoc_thunk_RmResource_egmmemAccessCallback(struct ExtendedGpuMemory *pResource, struct RsClient *pInvokingClient, void *pAllocParams, RsAccessRight accessRight) { + return rmresAccessCallback((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_ExtendedGpuMemory_RmResource.offset), pInvokingClient, pAllocParams, accessRight); +} + +const struct NVOC_EXPORT_INFO __nvoc_export_info_ExtendedGpuMemory = +{ + /*numEntries=*/ 0, + /*pExportEntries=*/ 0 +}; + +void __nvoc_dtor_StandardMemory(StandardMemory*); +void __nvoc_dtor_ExtendedGpuMemory(ExtendedGpuMemory *pThis) { + __nvoc_dtor_StandardMemory(&pThis->__nvoc_base_StandardMemory); + PORT_UNREFERENCED_VARIABLE(pThis); +} + +void __nvoc_init_dataField_ExtendedGpuMemory(ExtendedGpuMemory *pThis) { + PORT_UNREFERENCED_VARIABLE(pThis); +} + +NV_STATUS __nvoc_ctor_StandardMemory(StandardMemory* , CALL_CONTEXT *, struct RS_RES_ALLOC_PARAMS_INTERNAL *); +NV_STATUS __nvoc_ctor_ExtendedGpuMemory(ExtendedGpuMemory *pThis, CALL_CONTEXT * arg_pCallContext, struct RS_RES_ALLOC_PARAMS_INTERNAL * arg_pParams) { + NV_STATUS status = NV_OK; + status = __nvoc_ctor_StandardMemory(&pThis->__nvoc_base_StandardMemory, arg_pCallContext, arg_pParams); + if (status != NV_OK) goto __nvoc_ctor_ExtendedGpuMemory_fail_StandardMemory; + __nvoc_init_dataField_ExtendedGpuMemory(pThis); + + status = __nvoc_egmmemConstruct(pThis, arg_pCallContext, arg_pParams); + if (status != NV_OK) goto __nvoc_ctor_ExtendedGpuMemory_fail__init; + goto __nvoc_ctor_ExtendedGpuMemory_exit; // Success + +__nvoc_ctor_ExtendedGpuMemory_fail__init: + __nvoc_dtor_StandardMemory(&pThis->__nvoc_base_StandardMemory); +__nvoc_ctor_ExtendedGpuMemory_fail_StandardMemory: +__nvoc_ctor_ExtendedGpuMemory_exit: + + return status; +} + +static void __nvoc_init_funcTable_ExtendedGpuMemory_1(ExtendedGpuMemory *pThis) { + PORT_UNREFERENCED_VARIABLE(pThis); + + pThis->__egmmemCheckMemInterUnmap__ = &__nvoc_thunk_Memory_egmmemCheckMemInterUnmap; + + pThis->__egmmemShareCallback__ = &__nvoc_thunk_RmResource_egmmemShareCallback; + + pThis->__egmmemMapTo__ = &__nvoc_thunk_RsResource_egmmemMapTo; + + pThis->__egmmemGetMapAddrSpace__ = &__nvoc_thunk_Memory_egmmemGetMapAddrSpace; + + pThis->__egmmemGetRefCount__ = &__nvoc_thunk_RsResource_egmmemGetRefCount; + + pThis->__egmmemAddAdditionalDependants__ = &__nvoc_thunk_RsResource_egmmemAddAdditionalDependants; + + pThis->__egmmemControl_Prologue__ = &__nvoc_thunk_RmResource_egmmemControl_Prologue; + + pThis->__egmmemIsGpuMapAllowed__ = &__nvoc_thunk_Memory_egmmemIsGpuMapAllowed; + + pThis->__egmmemUnmapFrom__ = &__nvoc_thunk_RsResource_egmmemUnmapFrom; + + pThis->__egmmemControl_Epilogue__ = &__nvoc_thunk_RmResource_egmmemControl_Epilogue; + + pThis->__egmmemControlLookup__ = &__nvoc_thunk_RsResource_egmmemControlLookup; + + pThis->__egmmemControl__ = &__nvoc_thunk_Memory_egmmemControl; + + pThis->__egmmemUnmap__ = &__nvoc_thunk_Memory_egmmemUnmap; + + pThis->__egmmemGetMemInterMapParams__ = &__nvoc_thunk_Memory_egmmemGetMemInterMapParams; + + pThis->__egmmemGetMemoryMappingDescriptor__ = &__nvoc_thunk_Memory_egmmemGetMemoryMappingDescriptor; + + pThis->__egmmemControlFilter__ = &__nvoc_thunk_RsResource_egmmemControlFilter; + + pThis->__egmmemControlSerialization_Prologue__ = &__nvoc_thunk_RmResource_egmmemControlSerialization_Prologue; + + pThis->__egmmemCanCopy__ = &__nvoc_thunk_StandardMemory_egmmemCanCopy; + + pThis->__egmmemIsReady__ = &__nvoc_thunk_Memory_egmmemIsReady; + + pThis->__egmmemCheckCopyPermissions__ = &__nvoc_thunk_Memory_egmmemCheckCopyPermissions; + + pThis->__egmmemPreDestruct__ = &__nvoc_thunk_RsResource_egmmemPreDestruct; + + pThis->__egmmemIsDuplicate__ = &__nvoc_thunk_Memory_egmmemIsDuplicate; + + pThis->__egmmemControlSerialization_Epilogue__ = &__nvoc_thunk_RmResource_egmmemControlSerialization_Epilogue; + + pThis->__egmmemMap__ = &__nvoc_thunk_Memory_egmmemMap; + + pThis->__egmmemAccessCallback__ = &__nvoc_thunk_RmResource_egmmemAccessCallback; +} + +void __nvoc_init_funcTable_ExtendedGpuMemory(ExtendedGpuMemory *pThis) { + __nvoc_init_funcTable_ExtendedGpuMemory_1(pThis); +} + +void __nvoc_init_StandardMemory(StandardMemory*); +void __nvoc_init_ExtendedGpuMemory(ExtendedGpuMemory *pThis) { + pThis->__nvoc_pbase_ExtendedGpuMemory = pThis; + pThis->__nvoc_pbase_Object = &pThis->__nvoc_base_StandardMemory.__nvoc_base_Memory.__nvoc_base_RmResource.__nvoc_base_RsResource.__nvoc_base_Object; + pThis->__nvoc_pbase_RsResource = &pThis->__nvoc_base_StandardMemory.__nvoc_base_Memory.__nvoc_base_RmResource.__nvoc_base_RsResource; + pThis->__nvoc_pbase_RmResourceCommon = &pThis->__nvoc_base_StandardMemory.__nvoc_base_Memory.__nvoc_base_RmResource.__nvoc_base_RmResourceCommon; + pThis->__nvoc_pbase_RmResource = &pThis->__nvoc_base_StandardMemory.__nvoc_base_Memory.__nvoc_base_RmResource; + pThis->__nvoc_pbase_Memory = &pThis->__nvoc_base_StandardMemory.__nvoc_base_Memory; + pThis->__nvoc_pbase_StandardMemory = &pThis->__nvoc_base_StandardMemory; + __nvoc_init_StandardMemory(&pThis->__nvoc_base_StandardMemory); + __nvoc_init_funcTable_ExtendedGpuMemory(pThis); +} + +NV_STATUS __nvoc_objCreate_ExtendedGpuMemory(ExtendedGpuMemory **ppThis, Dynamic *pParent, NvU32 createFlags, CALL_CONTEXT * arg_pCallContext, struct RS_RES_ALLOC_PARAMS_INTERNAL * arg_pParams) { + NV_STATUS status; + Object *pParentObj; + ExtendedGpuMemory *pThis; + + status = __nvoc_handleObjCreateMemAlloc(createFlags, sizeof(ExtendedGpuMemory), (void**)&pThis, (void**)ppThis); + if (status != NV_OK) + return status; + + portMemSet(pThis, 0, sizeof(ExtendedGpuMemory)); + + __nvoc_initRtti(staticCast(pThis, Dynamic), &__nvoc_class_def_ExtendedGpuMemory); + + pThis->__nvoc_base_StandardMemory.__nvoc_base_Memory.__nvoc_base_RmResource.__nvoc_base_RsResource.__nvoc_base_Object.createFlags = createFlags; + + if (pParent != NULL && !(createFlags & NVOC_OBJ_CREATE_FLAGS_PARENT_HALSPEC_ONLY)) + { + pParentObj = dynamicCast(pParent, Object); + objAddChild(pParentObj, &pThis->__nvoc_base_StandardMemory.__nvoc_base_Memory.__nvoc_base_RmResource.__nvoc_base_RsResource.__nvoc_base_Object); + } + else + { + pThis->__nvoc_base_StandardMemory.__nvoc_base_Memory.__nvoc_base_RmResource.__nvoc_base_RsResource.__nvoc_base_Object.pParent = NULL; + } + + __nvoc_init_ExtendedGpuMemory(pThis); + status = __nvoc_ctor_ExtendedGpuMemory(pThis, arg_pCallContext, arg_pParams); + if (status != NV_OK) goto __nvoc_objCreate_ExtendedGpuMemory_cleanup; + + *ppThis = pThis; + + return NV_OK; + +__nvoc_objCreate_ExtendedGpuMemory_cleanup: + // do not call destructors here since the constructor already called them + if (createFlags & NVOC_OBJ_CREATE_FLAGS_IN_PLACE_CONSTRUCT) + portMemSet(pThis, 0, sizeof(ExtendedGpuMemory)); + else + portMemFree(pThis); + + // coverity[leaked_storage:FALSE] + return status; +} + +NV_STATUS __nvoc_objCreateDynamic_ExtendedGpuMemory(ExtendedGpuMemory **ppThis, Dynamic *pParent, NvU32 createFlags, va_list args) { + NV_STATUS status; + CALL_CONTEXT * arg_pCallContext = va_arg(args, CALL_CONTEXT *); + struct RS_RES_ALLOC_PARAMS_INTERNAL * arg_pParams = va_arg(args, struct RS_RES_ALLOC_PARAMS_INTERNAL *); + + status = __nvoc_objCreate_ExtendedGpuMemory(ppThis, pParent, createFlags, arg_pCallContext, arg_pParams); + + return status; +} + diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/generated/g_egm_mem_nvoc.h nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_egm_mem_nvoc.h --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/generated/g_egm_mem_nvoc.h 1970-01-01 00:00:00.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_egm_mem_nvoc.h 2024-03-05 22:18:12.000000000 +0000 @@ -0,0 +1,257 @@ +#ifndef _G_EGM_MEM_NVOC_H_ +#define _G_EGM_MEM_NVOC_H_ +#include "nvoc/runtime.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/* + * SPDX-FileCopyrightText: Copyright (c) 2021-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#include "g_egm_mem_nvoc.h" + +#ifndef _EGM_MEMORY_H_ +#define _EGM_MEMORY_H_ + +#include "mem_mgr/video_mem.h" +#include "mem_mgr/system_mem.h" + + +/*! + * Allocator for Extended GPU Memory (EGM) + * EGM is CPU_MEM accessed like peer GPU_MEM + */ +#ifdef NVOC_EGM_MEM_H_PRIVATE_ACCESS_ALLOWED +#define PRIVATE_FIELD(x) x +#else +#define PRIVATE_FIELD(x) NVOC_PRIVATE_FIELD(x) +#endif +struct ExtendedGpuMemory { + const struct NVOC_RTTI *__nvoc_rtti; + struct StandardMemory __nvoc_base_StandardMemory; + struct Object *__nvoc_pbase_Object; + struct RsResource *__nvoc_pbase_RsResource; + struct RmResourceCommon *__nvoc_pbase_RmResourceCommon; + struct RmResource *__nvoc_pbase_RmResource; + struct Memory *__nvoc_pbase_Memory; + struct StandardMemory *__nvoc_pbase_StandardMemory; + struct ExtendedGpuMemory *__nvoc_pbase_ExtendedGpuMemory; + NV_STATUS (*__egmmemCheckMemInterUnmap__)(struct ExtendedGpuMemory *, NvBool); + NvBool (*__egmmemShareCallback__)(struct ExtendedGpuMemory *, struct RsClient *, struct RsResourceRef *, RS_SHARE_POLICY *); + NV_STATUS (*__egmmemMapTo__)(struct ExtendedGpuMemory *, RS_RES_MAP_TO_PARAMS *); + NV_STATUS (*__egmmemGetMapAddrSpace__)(struct ExtendedGpuMemory *, CALL_CONTEXT *, NvU32, NV_ADDRESS_SPACE *); + NvU32 (*__egmmemGetRefCount__)(struct ExtendedGpuMemory *); + void (*__egmmemAddAdditionalDependants__)(struct RsClient *, struct ExtendedGpuMemory *, RsResourceRef *); + NV_STATUS (*__egmmemControl_Prologue__)(struct ExtendedGpuMemory *, CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); + NvBool (*__egmmemIsGpuMapAllowed__)(struct ExtendedGpuMemory *, struct OBJGPU *); + NV_STATUS (*__egmmemUnmapFrom__)(struct ExtendedGpuMemory *, RS_RES_UNMAP_FROM_PARAMS *); + void (*__egmmemControl_Epilogue__)(struct ExtendedGpuMemory *, CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); + NV_STATUS (*__egmmemControlLookup__)(struct ExtendedGpuMemory *, struct RS_RES_CONTROL_PARAMS_INTERNAL *, const struct NVOC_EXPORTED_METHOD_DEF **); + NV_STATUS (*__egmmemControl__)(struct ExtendedGpuMemory *, CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); + NV_STATUS (*__egmmemUnmap__)(struct ExtendedGpuMemory *, CALL_CONTEXT *, RsCpuMapping *); + NV_STATUS (*__egmmemGetMemInterMapParams__)(struct ExtendedGpuMemory *, RMRES_MEM_INTER_MAP_PARAMS *); + NV_STATUS (*__egmmemGetMemoryMappingDescriptor__)(struct ExtendedGpuMemory *, MEMORY_DESCRIPTOR **); + NV_STATUS (*__egmmemControlFilter__)(struct ExtendedGpuMemory *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); + NV_STATUS (*__egmmemControlSerialization_Prologue__)(struct ExtendedGpuMemory *, CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); + NvBool (*__egmmemCanCopy__)(struct ExtendedGpuMemory *); + NV_STATUS (*__egmmemIsReady__)(struct ExtendedGpuMemory *, NvBool); + NV_STATUS (*__egmmemCheckCopyPermissions__)(struct ExtendedGpuMemory *, struct OBJGPU *, struct Device *); + void (*__egmmemPreDestruct__)(struct ExtendedGpuMemory *); + NV_STATUS (*__egmmemIsDuplicate__)(struct ExtendedGpuMemory *, NvHandle, NvBool *); + void (*__egmmemControlSerialization_Epilogue__)(struct ExtendedGpuMemory *, CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); + NV_STATUS (*__egmmemMap__)(struct ExtendedGpuMemory *, CALL_CONTEXT *, struct RS_CPU_MAP_PARAMS *, RsCpuMapping *); + NvBool (*__egmmemAccessCallback__)(struct ExtendedGpuMemory *, struct RsClient *, void *, RsAccessRight); +}; + +#ifndef __NVOC_CLASS_ExtendedGpuMemory_TYPEDEF__ +#define __NVOC_CLASS_ExtendedGpuMemory_TYPEDEF__ +typedef struct ExtendedGpuMemory ExtendedGpuMemory; +#endif /* __NVOC_CLASS_ExtendedGpuMemory_TYPEDEF__ */ + +#ifndef __nvoc_class_id_ExtendedGpuMemory +#define __nvoc_class_id_ExtendedGpuMemory 0xeffa5c +#endif /* __nvoc_class_id_ExtendedGpuMemory */ + +extern const struct NVOC_CLASS_DEF __nvoc_class_def_ExtendedGpuMemory; + +#define __staticCast_ExtendedGpuMemory(pThis) \ + ((pThis)->__nvoc_pbase_ExtendedGpuMemory) + +#ifdef __nvoc_egm_mem_h_disabled +#define __dynamicCast_ExtendedGpuMemory(pThis) ((ExtendedGpuMemory*)NULL) +#else //__nvoc_egm_mem_h_disabled +#define __dynamicCast_ExtendedGpuMemory(pThis) \ + ((ExtendedGpuMemory*)__nvoc_dynamicCast(staticCast((pThis), Dynamic), classInfo(ExtendedGpuMemory))) +#endif //__nvoc_egm_mem_h_disabled + + +NV_STATUS __nvoc_objCreateDynamic_ExtendedGpuMemory(ExtendedGpuMemory**, Dynamic*, NvU32, va_list); + +NV_STATUS __nvoc_objCreate_ExtendedGpuMemory(ExtendedGpuMemory**, Dynamic*, NvU32, CALL_CONTEXT * arg_pCallContext, struct RS_RES_ALLOC_PARAMS_INTERNAL * arg_pParams); +#define __objCreate_ExtendedGpuMemory(ppNewObj, pParent, createFlags, arg_pCallContext, arg_pParams) \ + __nvoc_objCreate_ExtendedGpuMemory((ppNewObj), staticCast((pParent), Dynamic), (createFlags), arg_pCallContext, arg_pParams) + +#define egmmemCheckMemInterUnmap(pMemory, bSubdeviceHandleProvided) egmmemCheckMemInterUnmap_DISPATCH(pMemory, bSubdeviceHandleProvided) +#define egmmemShareCallback(pResource, pInvokingClient, pParentRef, pSharePolicy) egmmemShareCallback_DISPATCH(pResource, pInvokingClient, pParentRef, pSharePolicy) +#define egmmemMapTo(pResource, pParams) egmmemMapTo_DISPATCH(pResource, pParams) +#define egmmemGetMapAddrSpace(pMemory, pCallContext, mapFlags, pAddrSpace) egmmemGetMapAddrSpace_DISPATCH(pMemory, pCallContext, mapFlags, pAddrSpace) +#define egmmemGetRefCount(pResource) egmmemGetRefCount_DISPATCH(pResource) +#define egmmemAddAdditionalDependants(pClient, pResource, pReference) egmmemAddAdditionalDependants_DISPATCH(pClient, pResource, pReference) +#define egmmemControl_Prologue(pResource, pCallContext, pParams) egmmemControl_Prologue_DISPATCH(pResource, pCallContext, pParams) +#define egmmemIsGpuMapAllowed(pMemory, pGpu) egmmemIsGpuMapAllowed_DISPATCH(pMemory, pGpu) +#define egmmemUnmapFrom(pResource, pParams) egmmemUnmapFrom_DISPATCH(pResource, pParams) +#define egmmemControl_Epilogue(pResource, pCallContext, pParams) egmmemControl_Epilogue_DISPATCH(pResource, pCallContext, pParams) +#define egmmemControlLookup(pResource, pParams, ppEntry) egmmemControlLookup_DISPATCH(pResource, pParams, ppEntry) +#define egmmemControl(pMemory, pCallContext, pParams) egmmemControl_DISPATCH(pMemory, pCallContext, pParams) +#define egmmemUnmap(pMemory, pCallContext, pCpuMapping) egmmemUnmap_DISPATCH(pMemory, pCallContext, pCpuMapping) +#define egmmemGetMemInterMapParams(pMemory, pParams) egmmemGetMemInterMapParams_DISPATCH(pMemory, pParams) +#define egmmemGetMemoryMappingDescriptor(pMemory, ppMemDesc) egmmemGetMemoryMappingDescriptor_DISPATCH(pMemory, ppMemDesc) +#define egmmemControlFilter(pResource, pCallContext, pParams) egmmemControlFilter_DISPATCH(pResource, pCallContext, pParams) +#define egmmemControlSerialization_Prologue(pResource, pCallContext, pParams) egmmemControlSerialization_Prologue_DISPATCH(pResource, pCallContext, pParams) +#define egmmemCanCopy(pStandardMemory) egmmemCanCopy_DISPATCH(pStandardMemory) +#define egmmemIsReady(pMemory, bCopyConstructorContext) egmmemIsReady_DISPATCH(pMemory, bCopyConstructorContext) +#define egmmemCheckCopyPermissions(pMemory, pDstGpu, pDstDevice) egmmemCheckCopyPermissions_DISPATCH(pMemory, pDstGpu, pDstDevice) +#define egmmemPreDestruct(pResource) egmmemPreDestruct_DISPATCH(pResource) +#define egmmemIsDuplicate(pMemory, hMemory, pDuplicate) egmmemIsDuplicate_DISPATCH(pMemory, hMemory, pDuplicate) +#define egmmemControlSerialization_Epilogue(pResource, pCallContext, pParams) egmmemControlSerialization_Epilogue_DISPATCH(pResource, pCallContext, pParams) +#define egmmemMap(pMemory, pCallContext, pParams, pCpuMapping) egmmemMap_DISPATCH(pMemory, pCallContext, pParams, pCpuMapping) +#define egmmemAccessCallback(pResource, pInvokingClient, pAllocParams, accessRight) egmmemAccessCallback_DISPATCH(pResource, pInvokingClient, pAllocParams, accessRight) +static inline NV_STATUS egmmemCheckMemInterUnmap_DISPATCH(struct ExtendedGpuMemory *pMemory, NvBool bSubdeviceHandleProvided) { + return pMemory->__egmmemCheckMemInterUnmap__(pMemory, bSubdeviceHandleProvided); +} + +static inline NvBool egmmemShareCallback_DISPATCH(struct ExtendedGpuMemory *pResource, struct RsClient *pInvokingClient, struct RsResourceRef *pParentRef, RS_SHARE_POLICY *pSharePolicy) { + return pResource->__egmmemShareCallback__(pResource, pInvokingClient, pParentRef, pSharePolicy); +} + +static inline NV_STATUS egmmemMapTo_DISPATCH(struct ExtendedGpuMemory *pResource, RS_RES_MAP_TO_PARAMS *pParams) { + return pResource->__egmmemMapTo__(pResource, pParams); +} + +static inline NV_STATUS egmmemGetMapAddrSpace_DISPATCH(struct ExtendedGpuMemory *pMemory, CALL_CONTEXT *pCallContext, NvU32 mapFlags, NV_ADDRESS_SPACE *pAddrSpace) { + return pMemory->__egmmemGetMapAddrSpace__(pMemory, pCallContext, mapFlags, pAddrSpace); +} + +static inline NvU32 egmmemGetRefCount_DISPATCH(struct ExtendedGpuMemory *pResource) { + return pResource->__egmmemGetRefCount__(pResource); +} + +static inline void egmmemAddAdditionalDependants_DISPATCH(struct RsClient *pClient, struct ExtendedGpuMemory *pResource, RsResourceRef *pReference) { + pResource->__egmmemAddAdditionalDependants__(pClient, pResource, pReference); +} + +static inline NV_STATUS egmmemControl_Prologue_DISPATCH(struct ExtendedGpuMemory *pResource, CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return pResource->__egmmemControl_Prologue__(pResource, pCallContext, pParams); +} + +static inline NvBool egmmemIsGpuMapAllowed_DISPATCH(struct ExtendedGpuMemory *pMemory, struct OBJGPU *pGpu) { + return pMemory->__egmmemIsGpuMapAllowed__(pMemory, pGpu); +} + +static inline NV_STATUS egmmemUnmapFrom_DISPATCH(struct ExtendedGpuMemory *pResource, RS_RES_UNMAP_FROM_PARAMS *pParams) { + return pResource->__egmmemUnmapFrom__(pResource, pParams); +} + +static inline void egmmemControl_Epilogue_DISPATCH(struct ExtendedGpuMemory *pResource, CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + pResource->__egmmemControl_Epilogue__(pResource, pCallContext, pParams); +} + +static inline NV_STATUS egmmemControlLookup_DISPATCH(struct ExtendedGpuMemory *pResource, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams, const struct NVOC_EXPORTED_METHOD_DEF **ppEntry) { + return pResource->__egmmemControlLookup__(pResource, pParams, ppEntry); +} + +static inline NV_STATUS egmmemControl_DISPATCH(struct ExtendedGpuMemory *pMemory, CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return pMemory->__egmmemControl__(pMemory, pCallContext, pParams); +} + +static inline NV_STATUS egmmemUnmap_DISPATCH(struct ExtendedGpuMemory *pMemory, CALL_CONTEXT *pCallContext, RsCpuMapping *pCpuMapping) { + return pMemory->__egmmemUnmap__(pMemory, pCallContext, pCpuMapping); +} + +static inline NV_STATUS egmmemGetMemInterMapParams_DISPATCH(struct ExtendedGpuMemory *pMemory, RMRES_MEM_INTER_MAP_PARAMS *pParams) { + return pMemory->__egmmemGetMemInterMapParams__(pMemory, pParams); +} + +static inline NV_STATUS egmmemGetMemoryMappingDescriptor_DISPATCH(struct ExtendedGpuMemory *pMemory, MEMORY_DESCRIPTOR **ppMemDesc) { + return pMemory->__egmmemGetMemoryMappingDescriptor__(pMemory, ppMemDesc); +} + +static inline NV_STATUS egmmemControlFilter_DISPATCH(struct ExtendedGpuMemory *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return pResource->__egmmemControlFilter__(pResource, pCallContext, pParams); +} + +static inline NV_STATUS egmmemControlSerialization_Prologue_DISPATCH(struct ExtendedGpuMemory *pResource, CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return pResource->__egmmemControlSerialization_Prologue__(pResource, pCallContext, pParams); +} + +static inline NvBool egmmemCanCopy_DISPATCH(struct ExtendedGpuMemory *pStandardMemory) { + return pStandardMemory->__egmmemCanCopy__(pStandardMemory); +} + +static inline NV_STATUS egmmemIsReady_DISPATCH(struct ExtendedGpuMemory *pMemory, NvBool bCopyConstructorContext) { + return pMemory->__egmmemIsReady__(pMemory, bCopyConstructorContext); +} + +static inline NV_STATUS egmmemCheckCopyPermissions_DISPATCH(struct ExtendedGpuMemory *pMemory, struct OBJGPU *pDstGpu, struct Device *pDstDevice) { + return pMemory->__egmmemCheckCopyPermissions__(pMemory, pDstGpu, pDstDevice); +} + +static inline void egmmemPreDestruct_DISPATCH(struct ExtendedGpuMemory *pResource) { + pResource->__egmmemPreDestruct__(pResource); +} + +static inline NV_STATUS egmmemIsDuplicate_DISPATCH(struct ExtendedGpuMemory *pMemory, NvHandle hMemory, NvBool *pDuplicate) { + return pMemory->__egmmemIsDuplicate__(pMemory, hMemory, pDuplicate); +} + +static inline void egmmemControlSerialization_Epilogue_DISPATCH(struct ExtendedGpuMemory *pResource, CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + pResource->__egmmemControlSerialization_Epilogue__(pResource, pCallContext, pParams); +} + +static inline NV_STATUS egmmemMap_DISPATCH(struct ExtendedGpuMemory *pMemory, CALL_CONTEXT *pCallContext, struct RS_CPU_MAP_PARAMS *pParams, RsCpuMapping *pCpuMapping) { + return pMemory->__egmmemMap__(pMemory, pCallContext, pParams, pCpuMapping); +} + +static inline NvBool egmmemAccessCallback_DISPATCH(struct ExtendedGpuMemory *pResource, struct RsClient *pInvokingClient, void *pAllocParams, RsAccessRight accessRight) { + return pResource->__egmmemAccessCallback__(pResource, pInvokingClient, pAllocParams, accessRight); +} + +NV_STATUS egmmemConstruct_IMPL(struct ExtendedGpuMemory *arg_pStandardMemory, CALL_CONTEXT *arg_pCallContext, struct RS_RES_ALLOC_PARAMS_INTERNAL *arg_pParams); + +#define __nvoc_egmmemConstruct(arg_pStandardMemory, arg_pCallContext, arg_pParams) egmmemConstruct_IMPL(arg_pStandardMemory, arg_pCallContext, arg_pParams) +NV_STATUS egmmemValidateParams_IMPL(struct OBJGPU *pGpu, NvHandle hClient, NV_MEMORY_ALLOCATION_PARAMS *pAllocData); + +#define egmmemValidateParams(pGpu, hClient, pAllocData) egmmemValidateParams_IMPL(pGpu, hClient, pAllocData) +#undef PRIVATE_FIELD + + +NV_STATUS egmmemAllocResources(OBJGPU *pGpu, struct MemoryManager *pMemoryManager, + MEMORY_ALLOCATION_REQUEST *pAllocRequest, FB_ALLOC_INFO *pFbAllocInfo); + +#endif // _EGM_MEMORY_H_ + +#ifdef __cplusplus +} // extern "C" +#endif +#endif // _G_EGM_MEM_NVOC_H_ diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/generated/g_eng_desc_nvoc.h nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_eng_desc_nvoc.h --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/generated/g_eng_desc_nvoc.h 2023-10-25 20:26:55.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_eng_desc_nvoc.h 2024-03-05 22:18:12.000000000 +0000 @@ -440,6 +440,18 @@ #endif /* __nvoc_class_id_KernelPerf */ +struct Pxuc; + +#ifndef __NVOC_CLASS_Pxuc_TYPEDEF__ +#define __NVOC_CLASS_Pxuc_TYPEDEF__ +typedef struct Pxuc Pxuc; +#endif /* __NVOC_CLASS_Pxuc_TYPEDEF__ */ + +#ifndef __nvoc_class_id_Pxuc +#define __nvoc_class_id_Pxuc 0xba06f5 +#endif /* __nvoc_class_id_Pxuc */ + + struct OBJBIF; #ifndef __NVOC_CLASS_OBJBIF_TYPEDEF__ @@ -1124,18 +1136,6 @@ #endif /* __nvoc_class_id_OBJNVJPG */ -struct OBJFAS; - -#ifndef __NVOC_CLASS_OBJFAS_TYPEDEF__ -#define __NVOC_CLASS_OBJFAS_TYPEDEF__ -typedef struct OBJFAS OBJFAS; -#endif /* __NVOC_CLASS_OBJFAS_TYPEDEF__ */ - -#ifndef __nvoc_class_id_OBJFAS -#define __nvoc_class_id_OBJFAS 0x4ddf48 -#endif /* __nvoc_class_id_OBJFAS */ - - struct OBJVMMU; #ifndef __NVOC_CLASS_OBJVMMU_TYPEDEF__ @@ -1268,16 +1268,16 @@ #endif /* __nvoc_class_id_OBJDISPMACRO */ -struct OBJNNE; +struct Nne; -#ifndef __NVOC_CLASS_OBJNNE_TYPEDEF__ -#define __NVOC_CLASS_OBJNNE_TYPEDEF__ -typedef struct OBJNNE OBJNNE; -#endif /* __NVOC_CLASS_OBJNNE_TYPEDEF__ */ - -#ifndef __nvoc_class_id_OBJNNE -#define __nvoc_class_id_OBJNNE 0xc7f0f8 -#endif /* __nvoc_class_id_OBJNNE */ +#ifndef __NVOC_CLASS_Nne_TYPEDEF__ +#define __NVOC_CLASS_Nne_TYPEDEF__ +typedef struct Nne Nne; +#endif /* __NVOC_CLASS_Nne_TYPEDEF__ */ + +#ifndef __nvoc_class_id_Nne +#define __nvoc_class_id_Nne 0x2487e2 +#endif /* __nvoc_class_id_Nne */ struct Smbpbi; @@ -1340,6 +1340,18 @@ #endif /* __nvoc_class_id_OBJGMMU */ +struct ConfidentialCompute; + +#ifndef __NVOC_CLASS_ConfidentialCompute_TYPEDEF__ +#define __NVOC_CLASS_ConfidentialCompute_TYPEDEF__ +typedef struct ConfidentialCompute ConfidentialCompute; +#endif /* __NVOC_CLASS_ConfidentialCompute_TYPEDEF__ */ + +#ifndef __nvoc_class_id_ConfidentialCompute +#define __nvoc_class_id_ConfidentialCompute 0x9798cc +#endif /* __nvoc_class_id_ConfidentialCompute */ + + struct KernelCcu; #ifndef __NVOC_CLASS_KernelCcu_TYPEDEF__ @@ -1380,9 +1392,10 @@ #define ENG_INFOROM MKENGDESC(classId(OBJINFOROM), 0) #define ENG_PERF MKENGDESC(classId(Perf), 0) #define ENG_KERNEL_PERF MKENGDESC(classId(KernelPerf), 0) +#define ENG_PXUC MKENGDESC(classId(Pxuc), 0) #define ENG_BIF MKENGDESC(classId(OBJBIF), 0) #define ENG_KERNEL_BIF MKENGDESC(classId(KernelBif), 0) -#define ENG_HSHUBMANAGER MKENGDESC(classId(OBJHSHUBMANAGER)), 0) +#define ENG_HSHUBMANAGER MKENGDESC(classId(OBJHSHUBMANAGER), 0) #define ENG_SF MKENGDESC(classId(OBJSF), 0) #define ENG_GPIO MKENGDESC(classId(OBJGPIO), 0) #define ENG_CLK MKENGDESC(classId(ClockManager), 0) @@ -1448,6 +1461,7 @@ #define ENG_KERNEL_NVLINK MKENGDESC(classId(KernelNvlink), 0) #define ENG_GMMU MKENGDESC(classId(OBJGMMU), 0) #define ENG_KERNEL_GMMU MKENGDESC(classId(KernelGmmu), 0) +#define ENG_CONF_COMPUTE MKENGDESC(classId(ConfidentialCompute), 0) #define ENG_KERNEL_CCU MKENGDESC(classId(KernelCcu), 0) // Indexed CE engine tag reference diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/generated/g_eng_state_nvoc.c nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_eng_state_nvoc.c --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/generated/g_eng_state_nvoc.c 2023-10-25 20:26:55.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_eng_state_nvoc.c 2024-03-05 22:18:12.000000000 +0000 @@ -117,18 +117,6 @@ pThis->__engstateStateDestroy__ = &engstateStateDestroy_IMPL; - pThis->__engstateAllocTunableState__ = &engstateAllocTunableState_IMPL; - - pThis->__engstateFreeTunableState__ = &engstateFreeTunableState_IMPL; - - pThis->__engstateGetTunableState__ = &engstateGetTunableState_IMPL; - - pThis->__engstateSetTunableState__ = &engstateSetTunableState_IMPL; - - pThis->__engstateReconcileTunableState__ = &engstateReconcileTunableState_IMPL; - - pThis->__engstateCompareTunableState__ = &engstateCompareTunableState_IMPL; - pThis->__engstateIsPresent__ = &engstateIsPresent_IMPL; } @@ -149,13 +137,16 @@ Object *pParentObj; OBJENGSTATE *pThis; - pThis = portMemAllocNonPaged(sizeof(OBJENGSTATE)); - if (pThis == NULL) return NV_ERR_NO_MEMORY; + status = __nvoc_handleObjCreateMemAlloc(createFlags, sizeof(OBJENGSTATE), (void**)&pThis, (void**)ppThis); + if (status != NV_OK) + return status; portMemSet(pThis, 0, sizeof(OBJENGSTATE)); __nvoc_initRtti(staticCast(pThis, Dynamic), &__nvoc_class_def_OBJENGSTATE); + pThis->__nvoc_base_Object.createFlags = createFlags; + if (pParent != NULL && !(createFlags & NVOC_OBJ_CREATE_FLAGS_PARENT_HALSPEC_ONLY)) { pParentObj = dynamicCast(pParent, Object); @@ -171,11 +162,17 @@ if (status != NV_OK) goto __nvoc_objCreate_OBJENGSTATE_cleanup; *ppThis = pThis; + return NV_OK; __nvoc_objCreate_OBJENGSTATE_cleanup: // do not call destructors here since the constructor already called them - portMemFree(pThis); + if (createFlags & NVOC_OBJ_CREATE_FLAGS_IN_PLACE_CONSTRUCT) + portMemSet(pThis, 0, sizeof(OBJENGSTATE)); + else + portMemFree(pThis); + + // coverity[leaked_storage:FALSE] return status; } diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/generated/g_eng_state_nvoc.h nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_eng_state_nvoc.h --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/generated/g_eng_state_nvoc.h 2023-10-25 20:26:55.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_eng_state_nvoc.h 2024-03-05 22:18:12.000000000 +0000 @@ -106,16 +106,9 @@ NV_STATUS (*__engstateStateUnload__)(POBJGPU, POBJENGSTATE, NvU32); NV_STATUS (*__engstateStatePostUnload__)(POBJGPU, POBJENGSTATE, NvU32); void (*__engstateStateDestroy__)(POBJGPU, POBJENGSTATE); - NV_STATUS (*__engstateAllocTunableState__)(POBJGPU, POBJENGSTATE, void **); - void (*__engstateFreeTunableState__)(POBJGPU, POBJENGSTATE, void *); - NV_STATUS (*__engstateGetTunableState__)(POBJGPU, POBJENGSTATE, void *); - NV_STATUS (*__engstateSetTunableState__)(POBJGPU, POBJENGSTATE, void *); - NV_STATUS (*__engstateReconcileTunableState__)(POBJGPU, POBJENGSTATE, void *); - NV_STATUS (*__engstateCompareTunableState__)(POBJGPU, POBJENGSTATE, void *, void *); NvBool (*__engstateIsPresent__)(POBJGPU, POBJENGSTATE); NvBool PDB_PROP_ENGSTATE_IS_MISSING; ENGDESCRIPTOR engDesc; - void *pOriginalTunableState; struct OBJGPU *pGpu; ENGSTATE_STATE currentState; ENGSTATE_STATS stats[11]; @@ -165,12 +158,6 @@ #define engstateStateUnload(pGpu, pEngstate, arg0) engstateStateUnload_DISPATCH(pGpu, pEngstate, arg0) #define engstateStatePostUnload(pGpu, pEngstate, arg0) engstateStatePostUnload_DISPATCH(pGpu, pEngstate, arg0) #define engstateStateDestroy(pGpu, pEngstate) engstateStateDestroy_DISPATCH(pGpu, pEngstate) -#define engstateAllocTunableState(pGpu, pEngstate, ppTunableState) engstateAllocTunableState_DISPATCH(pGpu, pEngstate, ppTunableState) -#define engstateFreeTunableState(pGpu, pEngstate, pTunableState) engstateFreeTunableState_DISPATCH(pGpu, pEngstate, pTunableState) -#define engstateGetTunableState(pGpu, pEngstate, pTunableState) engstateGetTunableState_DISPATCH(pGpu, pEngstate, pTunableState) -#define engstateSetTunableState(pGpu, pEngstate, pTunableState) engstateSetTunableState_DISPATCH(pGpu, pEngstate, pTunableState) -#define engstateReconcileTunableState(pGpu, pEngstate, pTunableState) engstateReconcileTunableState_DISPATCH(pGpu, pEngstate, pTunableState) -#define engstateCompareTunableState(pGpu, pEngstate, pTunables1, pTunables2) engstateCompareTunableState_DISPATCH(pGpu, pEngstate, pTunables1, pTunables2) #define engstateIsPresent(pGpu, pEngstate) engstateIsPresent_DISPATCH(pGpu, pEngstate) NV_STATUS engstateConstructEngine_IMPL(POBJGPU pGpu, POBJENGSTATE pEngstate, ENGDESCRIPTOR arg0); @@ -250,42 +237,6 @@ pEngstate->__engstateStateDestroy__(pGpu, pEngstate); } -NV_STATUS engstateAllocTunableState_IMPL(POBJGPU pGpu, POBJENGSTATE pEngstate, void **ppTunableState); - -static inline NV_STATUS engstateAllocTunableState_DISPATCH(POBJGPU pGpu, POBJENGSTATE pEngstate, void **ppTunableState) { - return pEngstate->__engstateAllocTunableState__(pGpu, pEngstate, ppTunableState); -} - -void engstateFreeTunableState_IMPL(POBJGPU pGpu, POBJENGSTATE pEngstate, void *pTunableState); - -static inline void engstateFreeTunableState_DISPATCH(POBJGPU pGpu, POBJENGSTATE pEngstate, void *pTunableState) { - pEngstate->__engstateFreeTunableState__(pGpu, pEngstate, pTunableState); -} - -NV_STATUS engstateGetTunableState_IMPL(POBJGPU pGpu, POBJENGSTATE pEngstate, void *pTunableState); - -static inline NV_STATUS engstateGetTunableState_DISPATCH(POBJGPU pGpu, POBJENGSTATE pEngstate, void *pTunableState) { - return pEngstate->__engstateGetTunableState__(pGpu, pEngstate, pTunableState); -} - -NV_STATUS engstateSetTunableState_IMPL(POBJGPU pGpu, POBJENGSTATE pEngstate, void *pTunableState); - -static inline NV_STATUS engstateSetTunableState_DISPATCH(POBJGPU pGpu, POBJENGSTATE pEngstate, void *pTunableState) { - return pEngstate->__engstateSetTunableState__(pGpu, pEngstate, pTunableState); -} - -NV_STATUS engstateReconcileTunableState_IMPL(POBJGPU pGpu, POBJENGSTATE pEngstate, void *pTunableState); - -static inline NV_STATUS engstateReconcileTunableState_DISPATCH(POBJGPU pGpu, POBJENGSTATE pEngstate, void *pTunableState) { - return pEngstate->__engstateReconcileTunableState__(pGpu, pEngstate, pTunableState); -} - -NV_STATUS engstateCompareTunableState_IMPL(POBJGPU pGpu, POBJENGSTATE pEngstate, void *pTunables1, void *pTunables2); - -static inline NV_STATUS engstateCompareTunableState_DISPATCH(POBJGPU pGpu, POBJENGSTATE pEngstate, void *pTunables1, void *pTunables2) { - return pEngstate->__engstateCompareTunableState__(pGpu, pEngstate, pTunables1, pTunables2); -} - NvBool engstateIsPresent_IMPL(POBJGPU pGpu, POBJENGSTATE pEngstate); static inline NvBool engstateIsPresent_DISPATCH(POBJGPU pGpu, POBJENGSTATE pEngstate) { diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/generated/g_event_buffer_nvoc.c nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_event_buffer_nvoc.c --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/generated/g_event_buffer_nvoc.c 2023-10-25 20:26:56.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_event_buffer_nvoc.c 2024-03-05 22:18:12.000000000 +0000 @@ -116,8 +116,12 @@ resAddAdditionalDependants(pClient, (struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_EventBuffer_RsResource.offset), pReference); } -static NV_STATUS __nvoc_thunk_RsResource_eventbufferUnmap(struct EventBuffer *pResource, struct CALL_CONTEXT *pCallContext, RsCpuMapping *pCpuMapping) { - return resUnmap((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_EventBuffer_RsResource.offset), pCallContext, pCpuMapping); +static NV_STATUS __nvoc_thunk_RsResource_eventbufferUnmapFrom(struct EventBuffer *pResource, RS_RES_UNMAP_FROM_PARAMS *pParams) { + return resUnmapFrom((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_EventBuffer_RsResource.offset), pParams); +} + +static NV_STATUS __nvoc_thunk_RmResource_eventbufferControlSerialization_Prologue(struct EventBuffer *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return rmresControlSerialization_Prologue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_EventBuffer_RmResource.offset), pCallContext, pParams); } static NV_STATUS __nvoc_thunk_RmResource_eventbufferControl_Prologue(struct EventBuffer *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { @@ -128,22 +132,26 @@ return resCanCopy((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_EventBuffer_RsResource.offset)); } -static NV_STATUS __nvoc_thunk_RsResource_eventbufferMapTo(struct EventBuffer *pResource, RS_RES_MAP_TO_PARAMS *pParams) { - return resMapTo((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_EventBuffer_RsResource.offset), pParams); +static NV_STATUS __nvoc_thunk_RsResource_eventbufferUnmap(struct EventBuffer *pResource, struct CALL_CONTEXT *pCallContext, RsCpuMapping *pCpuMapping) { + return resUnmap((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_EventBuffer_RsResource.offset), pCallContext, pCpuMapping); } static void __nvoc_thunk_RsResource_eventbufferPreDestruct(struct EventBuffer *pResource) { resPreDestruct((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_EventBuffer_RsResource.offset)); } -static NV_STATUS __nvoc_thunk_RsResource_eventbufferUnmapFrom(struct EventBuffer *pResource, RS_RES_UNMAP_FROM_PARAMS *pParams) { - return resUnmapFrom((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_EventBuffer_RsResource.offset), pParams); +static NV_STATUS __nvoc_thunk_RsResource_eventbufferMapTo(struct EventBuffer *pResource, RS_RES_MAP_TO_PARAMS *pParams) { + return resMapTo((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_EventBuffer_RsResource.offset), pParams); } static NV_STATUS __nvoc_thunk_RsResource_eventbufferIsDuplicate(struct EventBuffer *pResource, NvHandle hMemory, NvBool *pDuplicate) { return resIsDuplicate((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_EventBuffer_RsResource.offset), hMemory, pDuplicate); } +static void __nvoc_thunk_RmResource_eventbufferControlSerialization_Epilogue(struct EventBuffer *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + rmresControlSerialization_Epilogue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_EventBuffer_RmResource.offset), pCallContext, pParams); +} + static void __nvoc_thunk_RmResource_eventbufferControl_Epilogue(struct EventBuffer *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { rmresControl_Epilogue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_EventBuffer_RmResource.offset), pCallContext, pParams); } @@ -300,20 +308,24 @@ pThis->__eventbufferAddAdditionalDependants__ = &__nvoc_thunk_RsResource_eventbufferAddAdditionalDependants; - pThis->__eventbufferUnmap__ = &__nvoc_thunk_RsResource_eventbufferUnmap; + pThis->__eventbufferUnmapFrom__ = &__nvoc_thunk_RsResource_eventbufferUnmapFrom; + + pThis->__eventbufferControlSerialization_Prologue__ = &__nvoc_thunk_RmResource_eventbufferControlSerialization_Prologue; pThis->__eventbufferControl_Prologue__ = &__nvoc_thunk_RmResource_eventbufferControl_Prologue; pThis->__eventbufferCanCopy__ = &__nvoc_thunk_RsResource_eventbufferCanCopy; - pThis->__eventbufferMapTo__ = &__nvoc_thunk_RsResource_eventbufferMapTo; + pThis->__eventbufferUnmap__ = &__nvoc_thunk_RsResource_eventbufferUnmap; pThis->__eventbufferPreDestruct__ = &__nvoc_thunk_RsResource_eventbufferPreDestruct; - pThis->__eventbufferUnmapFrom__ = &__nvoc_thunk_RsResource_eventbufferUnmapFrom; + pThis->__eventbufferMapTo__ = &__nvoc_thunk_RsResource_eventbufferMapTo; pThis->__eventbufferIsDuplicate__ = &__nvoc_thunk_RsResource_eventbufferIsDuplicate; + pThis->__eventbufferControlSerialization_Epilogue__ = &__nvoc_thunk_RmResource_eventbufferControlSerialization_Epilogue; + pThis->__eventbufferControl_Epilogue__ = &__nvoc_thunk_RmResource_eventbufferControl_Epilogue; pThis->__eventbufferControlLookup__ = &__nvoc_thunk_RsResource_eventbufferControlLookup; @@ -343,13 +355,16 @@ Object *pParentObj; EventBuffer *pThis; - pThis = portMemAllocNonPaged(sizeof(EventBuffer)); - if (pThis == NULL) return NV_ERR_NO_MEMORY; + status = __nvoc_handleObjCreateMemAlloc(createFlags, sizeof(EventBuffer), (void**)&pThis, (void**)ppThis); + if (status != NV_OK) + return status; portMemSet(pThis, 0, sizeof(EventBuffer)); __nvoc_initRtti(staticCast(pThis, Dynamic), &__nvoc_class_def_EventBuffer); + pThis->__nvoc_base_RmResource.__nvoc_base_RsResource.__nvoc_base_Object.createFlags = createFlags; + if (pParent != NULL && !(createFlags & NVOC_OBJ_CREATE_FLAGS_PARENT_HALSPEC_ONLY)) { pParentObj = dynamicCast(pParent, Object); @@ -365,11 +380,17 @@ if (status != NV_OK) goto __nvoc_objCreate_EventBuffer_cleanup; *ppThis = pThis; + return NV_OK; __nvoc_objCreate_EventBuffer_cleanup: // do not call destructors here since the constructor already called them - portMemFree(pThis); + if (createFlags & NVOC_OBJ_CREATE_FLAGS_IN_PLACE_CONSTRUCT) + portMemSet(pThis, 0, sizeof(EventBuffer)); + else + portMemFree(pThis); + + // coverity[leaked_storage:FALSE] return status; } diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/generated/g_event_buffer_nvoc.h nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_event_buffer_nvoc.h --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/generated/g_event_buffer_nvoc.h 2023-10-25 20:26:56.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_event_buffer_nvoc.h 2024-03-05 22:18:13.000000000 +0000 @@ -93,13 +93,15 @@ NvU32 (*__eventbufferGetRefCount__)(struct EventBuffer *); NV_STATUS (*__eventbufferControlFilter__)(struct EventBuffer *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); void (*__eventbufferAddAdditionalDependants__)(struct RsClient *, struct EventBuffer *, RsResourceRef *); - NV_STATUS (*__eventbufferUnmap__)(struct EventBuffer *, struct CALL_CONTEXT *, RsCpuMapping *); + NV_STATUS (*__eventbufferUnmapFrom__)(struct EventBuffer *, RS_RES_UNMAP_FROM_PARAMS *); + NV_STATUS (*__eventbufferControlSerialization_Prologue__)(struct EventBuffer *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); NV_STATUS (*__eventbufferControl_Prologue__)(struct EventBuffer *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); NvBool (*__eventbufferCanCopy__)(struct EventBuffer *); - NV_STATUS (*__eventbufferMapTo__)(struct EventBuffer *, RS_RES_MAP_TO_PARAMS *); + NV_STATUS (*__eventbufferUnmap__)(struct EventBuffer *, struct CALL_CONTEXT *, RsCpuMapping *); void (*__eventbufferPreDestruct__)(struct EventBuffer *); - NV_STATUS (*__eventbufferUnmapFrom__)(struct EventBuffer *, RS_RES_UNMAP_FROM_PARAMS *); + NV_STATUS (*__eventbufferMapTo__)(struct EventBuffer *, RS_RES_MAP_TO_PARAMS *); NV_STATUS (*__eventbufferIsDuplicate__)(struct EventBuffer *, NvHandle, NvBool *); + void (*__eventbufferControlSerialization_Epilogue__)(struct EventBuffer *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); void (*__eventbufferControl_Epilogue__)(struct EventBuffer *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); NV_STATUS (*__eventbufferControlLookup__)(struct EventBuffer *, struct RS_RES_CONTROL_PARAMS_INTERNAL *, const struct NVOC_EXPORTED_METHOD_DEF **); NV_STATUS (*__eventbufferMap__)(struct EventBuffer *, struct CALL_CONTEXT *, RS_CPU_MAP_PARAMS *, RsCpuMapping *); @@ -166,13 +168,15 @@ #define eventbufferGetRefCount(pResource) eventbufferGetRefCount_DISPATCH(pResource) #define eventbufferControlFilter(pResource, pCallContext, pParams) eventbufferControlFilter_DISPATCH(pResource, pCallContext, pParams) #define eventbufferAddAdditionalDependants(pClient, pResource, pReference) eventbufferAddAdditionalDependants_DISPATCH(pClient, pResource, pReference) -#define eventbufferUnmap(pResource, pCallContext, pCpuMapping) eventbufferUnmap_DISPATCH(pResource, pCallContext, pCpuMapping) +#define eventbufferUnmapFrom(pResource, pParams) eventbufferUnmapFrom_DISPATCH(pResource, pParams) +#define eventbufferControlSerialization_Prologue(pResource, pCallContext, pParams) eventbufferControlSerialization_Prologue_DISPATCH(pResource, pCallContext, pParams) #define eventbufferControl_Prologue(pResource, pCallContext, pParams) eventbufferControl_Prologue_DISPATCH(pResource, pCallContext, pParams) #define eventbufferCanCopy(pResource) eventbufferCanCopy_DISPATCH(pResource) -#define eventbufferMapTo(pResource, pParams) eventbufferMapTo_DISPATCH(pResource, pParams) +#define eventbufferUnmap(pResource, pCallContext, pCpuMapping) eventbufferUnmap_DISPATCH(pResource, pCallContext, pCpuMapping) #define eventbufferPreDestruct(pResource) eventbufferPreDestruct_DISPATCH(pResource) -#define eventbufferUnmapFrom(pResource, pParams) eventbufferUnmapFrom_DISPATCH(pResource, pParams) +#define eventbufferMapTo(pResource, pParams) eventbufferMapTo_DISPATCH(pResource, pParams) #define eventbufferIsDuplicate(pResource, hMemory, pDuplicate) eventbufferIsDuplicate_DISPATCH(pResource, hMemory, pDuplicate) +#define eventbufferControlSerialization_Epilogue(pResource, pCallContext, pParams) eventbufferControlSerialization_Epilogue_DISPATCH(pResource, pCallContext, pParams) #define eventbufferControl_Epilogue(pResource, pCallContext, pParams) eventbufferControl_Epilogue_DISPATCH(pResource, pCallContext, pParams) #define eventbufferControlLookup(pResource, pParams, ppEntry) eventbufferControlLookup_DISPATCH(pResource, pParams, ppEntry) #define eventbufferMap(pResource, pCallContext, pParams, pCpuMapping) eventbufferMap_DISPATCH(pResource, pCallContext, pParams, pCpuMapping) @@ -233,8 +237,12 @@ pResource->__eventbufferAddAdditionalDependants__(pClient, pResource, pReference); } -static inline NV_STATUS eventbufferUnmap_DISPATCH(struct EventBuffer *pResource, struct CALL_CONTEXT *pCallContext, RsCpuMapping *pCpuMapping) { - return pResource->__eventbufferUnmap__(pResource, pCallContext, pCpuMapping); +static inline NV_STATUS eventbufferUnmapFrom_DISPATCH(struct EventBuffer *pResource, RS_RES_UNMAP_FROM_PARAMS *pParams) { + return pResource->__eventbufferUnmapFrom__(pResource, pParams); +} + +static inline NV_STATUS eventbufferControlSerialization_Prologue_DISPATCH(struct EventBuffer *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return pResource->__eventbufferControlSerialization_Prologue__(pResource, pCallContext, pParams); } static inline NV_STATUS eventbufferControl_Prologue_DISPATCH(struct EventBuffer *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { @@ -245,22 +253,26 @@ return pResource->__eventbufferCanCopy__(pResource); } -static inline NV_STATUS eventbufferMapTo_DISPATCH(struct EventBuffer *pResource, RS_RES_MAP_TO_PARAMS *pParams) { - return pResource->__eventbufferMapTo__(pResource, pParams); +static inline NV_STATUS eventbufferUnmap_DISPATCH(struct EventBuffer *pResource, struct CALL_CONTEXT *pCallContext, RsCpuMapping *pCpuMapping) { + return pResource->__eventbufferUnmap__(pResource, pCallContext, pCpuMapping); } static inline void eventbufferPreDestruct_DISPATCH(struct EventBuffer *pResource) { pResource->__eventbufferPreDestruct__(pResource); } -static inline NV_STATUS eventbufferUnmapFrom_DISPATCH(struct EventBuffer *pResource, RS_RES_UNMAP_FROM_PARAMS *pParams) { - return pResource->__eventbufferUnmapFrom__(pResource, pParams); +static inline NV_STATUS eventbufferMapTo_DISPATCH(struct EventBuffer *pResource, RS_RES_MAP_TO_PARAMS *pParams) { + return pResource->__eventbufferMapTo__(pResource, pParams); } static inline NV_STATUS eventbufferIsDuplicate_DISPATCH(struct EventBuffer *pResource, NvHandle hMemory, NvBool *pDuplicate) { return pResource->__eventbufferIsDuplicate__(pResource, hMemory, pDuplicate); } +static inline void eventbufferControlSerialization_Epilogue_DISPATCH(struct EventBuffer *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + pResource->__eventbufferControlSerialization_Epilogue__(pResource, pCallContext, pParams); +} + static inline void eventbufferControl_Epilogue_DISPATCH(struct EventBuffer *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { pResource->__eventbufferControl_Epilogue__(pResource, pCallContext, pParams); } diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/generated/g_event_nvoc.c nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_event_nvoc.c --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/generated/g_event_nvoc.c 2023-10-25 20:26:56.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_event_nvoc.c 2024-03-05 22:18:13.000000000 +0000 @@ -124,13 +124,16 @@ Object *pParentObj; NotifShare *pThis; - pThis = portMemAllocNonPaged(sizeof(NotifShare)); - if (pThis == NULL) return NV_ERR_NO_MEMORY; + status = __nvoc_handleObjCreateMemAlloc(createFlags, sizeof(NotifShare), (void**)&pThis, (void**)ppThis); + if (status != NV_OK) + return status; portMemSet(pThis, 0, sizeof(NotifShare)); __nvoc_initRtti(staticCast(pThis, Dynamic), &__nvoc_class_def_NotifShare); + pThis->__nvoc_base_RsShared.__nvoc_base_Object.createFlags = createFlags; + if (pParent != NULL && !(createFlags & NVOC_OBJ_CREATE_FLAGS_PARENT_HALSPEC_ONLY)) { pParentObj = dynamicCast(pParent, Object); @@ -146,11 +149,17 @@ if (status != NV_OK) goto __nvoc_objCreate_NotifShare_cleanup; *ppThis = pThis; + return NV_OK; __nvoc_objCreate_NotifShare_cleanup: // do not call destructors here since the constructor already called them - portMemFree(pThis); + if (createFlags & NVOC_OBJ_CREATE_FLAGS_IN_PLACE_CONSTRUCT) + portMemSet(pThis, 0, sizeof(NotifShare)); + else + portMemFree(pThis); + + // coverity[leaked_storage:FALSE] return status; } @@ -271,8 +280,12 @@ resAddAdditionalDependants(pClient, (struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_Event_RsResource.offset), pReference); } -static NV_STATUS __nvoc_thunk_RsResource_eventUnmap(struct Event *pResource, struct CALL_CONTEXT *pCallContext, RsCpuMapping *pCpuMapping) { - return resUnmap((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_Event_RsResource.offset), pCallContext, pCpuMapping); +static NV_STATUS __nvoc_thunk_RsResource_eventUnmapFrom(struct Event *pResource, RS_RES_UNMAP_FROM_PARAMS *pParams) { + return resUnmapFrom((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_Event_RsResource.offset), pParams); +} + +static NV_STATUS __nvoc_thunk_RmResource_eventControlSerialization_Prologue(struct Event *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return rmresControlSerialization_Prologue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_Event_RmResource.offset), pCallContext, pParams); } static NV_STATUS __nvoc_thunk_RmResource_eventControl_Prologue(struct Event *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { @@ -283,22 +296,26 @@ return resCanCopy((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_Event_RsResource.offset)); } -static NV_STATUS __nvoc_thunk_RsResource_eventMapTo(struct Event *pResource, RS_RES_MAP_TO_PARAMS *pParams) { - return resMapTo((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_Event_RsResource.offset), pParams); +static NV_STATUS __nvoc_thunk_RsResource_eventUnmap(struct Event *pResource, struct CALL_CONTEXT *pCallContext, RsCpuMapping *pCpuMapping) { + return resUnmap((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_Event_RsResource.offset), pCallContext, pCpuMapping); } static void __nvoc_thunk_RsResource_eventPreDestruct(struct Event *pResource) { resPreDestruct((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_Event_RsResource.offset)); } -static NV_STATUS __nvoc_thunk_RsResource_eventUnmapFrom(struct Event *pResource, RS_RES_UNMAP_FROM_PARAMS *pParams) { - return resUnmapFrom((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_Event_RsResource.offset), pParams); +static NV_STATUS __nvoc_thunk_RsResource_eventMapTo(struct Event *pResource, RS_RES_MAP_TO_PARAMS *pParams) { + return resMapTo((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_Event_RsResource.offset), pParams); } static NV_STATUS __nvoc_thunk_RsResource_eventIsDuplicate(struct Event *pResource, NvHandle hMemory, NvBool *pDuplicate) { return resIsDuplicate((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_Event_RsResource.offset), hMemory, pDuplicate); } +static void __nvoc_thunk_RmResource_eventControlSerialization_Epilogue(struct Event *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + rmresControlSerialization_Epilogue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_Event_RmResource.offset), pCallContext, pParams); +} + static void __nvoc_thunk_RmResource_eventControl_Epilogue(struct Event *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { rmresControl_Epilogue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_Event_RmResource.offset), pCallContext, pParams); } @@ -370,20 +387,24 @@ pThis->__eventAddAdditionalDependants__ = &__nvoc_thunk_RsResource_eventAddAdditionalDependants; - pThis->__eventUnmap__ = &__nvoc_thunk_RsResource_eventUnmap; + pThis->__eventUnmapFrom__ = &__nvoc_thunk_RsResource_eventUnmapFrom; + + pThis->__eventControlSerialization_Prologue__ = &__nvoc_thunk_RmResource_eventControlSerialization_Prologue; pThis->__eventControl_Prologue__ = &__nvoc_thunk_RmResource_eventControl_Prologue; pThis->__eventCanCopy__ = &__nvoc_thunk_RsResource_eventCanCopy; - pThis->__eventMapTo__ = &__nvoc_thunk_RsResource_eventMapTo; + pThis->__eventUnmap__ = &__nvoc_thunk_RsResource_eventUnmap; pThis->__eventPreDestruct__ = &__nvoc_thunk_RsResource_eventPreDestruct; - pThis->__eventUnmapFrom__ = &__nvoc_thunk_RsResource_eventUnmapFrom; + pThis->__eventMapTo__ = &__nvoc_thunk_RsResource_eventMapTo; pThis->__eventIsDuplicate__ = &__nvoc_thunk_RsResource_eventIsDuplicate; + pThis->__eventControlSerialization_Epilogue__ = &__nvoc_thunk_RmResource_eventControlSerialization_Epilogue; + pThis->__eventControl_Epilogue__ = &__nvoc_thunk_RmResource_eventControl_Epilogue; pThis->__eventControlLookup__ = &__nvoc_thunk_RsResource_eventControlLookup; @@ -413,13 +434,16 @@ Object *pParentObj; Event *pThis; - pThis = portMemAllocNonPaged(sizeof(Event)); - if (pThis == NULL) return NV_ERR_NO_MEMORY; + status = __nvoc_handleObjCreateMemAlloc(createFlags, sizeof(Event), (void**)&pThis, (void**)ppThis); + if (status != NV_OK) + return status; portMemSet(pThis, 0, sizeof(Event)); __nvoc_initRtti(staticCast(pThis, Dynamic), &__nvoc_class_def_Event); + pThis->__nvoc_base_RmResource.__nvoc_base_RsResource.__nvoc_base_Object.createFlags = createFlags; + if (pParent != NULL && !(createFlags & NVOC_OBJ_CREATE_FLAGS_PARENT_HALSPEC_ONLY)) { pParentObj = dynamicCast(pParent, Object); @@ -435,11 +459,17 @@ if (status != NV_OK) goto __nvoc_objCreate_Event_cleanup; *ppThis = pThis; + return NV_OK; __nvoc_objCreate_Event_cleanup: // do not call destructors here since the constructor already called them - portMemFree(pThis); + if (createFlags & NVOC_OBJ_CREATE_FLAGS_IN_PLACE_CONSTRUCT) + portMemSet(pThis, 0, sizeof(Event)); + else + portMemFree(pThis); + + // coverity[leaked_storage:FALSE] return status; } diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/generated/g_event_nvoc.h nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_event_nvoc.h --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/generated/g_event_nvoc.h 2023-10-25 20:26:56.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_event_nvoc.h 2024-03-05 22:18:13.000000000 +0000 @@ -179,13 +179,15 @@ NvU32 (*__eventGetRefCount__)(struct Event *); NV_STATUS (*__eventControlFilter__)(struct Event *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); void (*__eventAddAdditionalDependants__)(struct RsClient *, struct Event *, RsResourceRef *); - NV_STATUS (*__eventUnmap__)(struct Event *, struct CALL_CONTEXT *, RsCpuMapping *); + NV_STATUS (*__eventUnmapFrom__)(struct Event *, RS_RES_UNMAP_FROM_PARAMS *); + NV_STATUS (*__eventControlSerialization_Prologue__)(struct Event *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); NV_STATUS (*__eventControl_Prologue__)(struct Event *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); NvBool (*__eventCanCopy__)(struct Event *); - NV_STATUS (*__eventMapTo__)(struct Event *, RS_RES_MAP_TO_PARAMS *); + NV_STATUS (*__eventUnmap__)(struct Event *, struct CALL_CONTEXT *, RsCpuMapping *); void (*__eventPreDestruct__)(struct Event *); - NV_STATUS (*__eventUnmapFrom__)(struct Event *, RS_RES_UNMAP_FROM_PARAMS *); + NV_STATUS (*__eventMapTo__)(struct Event *, RS_RES_MAP_TO_PARAMS *); NV_STATUS (*__eventIsDuplicate__)(struct Event *, NvHandle, NvBool *); + void (*__eventControlSerialization_Epilogue__)(struct Event *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); void (*__eventControl_Epilogue__)(struct Event *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); NV_STATUS (*__eventControlLookup__)(struct Event *, struct RS_RES_CONTROL_PARAMS_INTERNAL *, const struct NVOC_EXPORTED_METHOD_DEF **); NV_STATUS (*__eventMap__)(struct Event *, struct CALL_CONTEXT *, RS_CPU_MAP_PARAMS *, RsCpuMapping *); @@ -232,13 +234,15 @@ #define eventGetRefCount(pResource) eventGetRefCount_DISPATCH(pResource) #define eventControlFilter(pResource, pCallContext, pParams) eventControlFilter_DISPATCH(pResource, pCallContext, pParams) #define eventAddAdditionalDependants(pClient, pResource, pReference) eventAddAdditionalDependants_DISPATCH(pClient, pResource, pReference) -#define eventUnmap(pResource, pCallContext, pCpuMapping) eventUnmap_DISPATCH(pResource, pCallContext, pCpuMapping) +#define eventUnmapFrom(pResource, pParams) eventUnmapFrom_DISPATCH(pResource, pParams) +#define eventControlSerialization_Prologue(pResource, pCallContext, pParams) eventControlSerialization_Prologue_DISPATCH(pResource, pCallContext, pParams) #define eventControl_Prologue(pResource, pCallContext, pParams) eventControl_Prologue_DISPATCH(pResource, pCallContext, pParams) #define eventCanCopy(pResource) eventCanCopy_DISPATCH(pResource) -#define eventMapTo(pResource, pParams) eventMapTo_DISPATCH(pResource, pParams) +#define eventUnmap(pResource, pCallContext, pCpuMapping) eventUnmap_DISPATCH(pResource, pCallContext, pCpuMapping) #define eventPreDestruct(pResource) eventPreDestruct_DISPATCH(pResource) -#define eventUnmapFrom(pResource, pParams) eventUnmapFrom_DISPATCH(pResource, pParams) +#define eventMapTo(pResource, pParams) eventMapTo_DISPATCH(pResource, pParams) #define eventIsDuplicate(pResource, hMemory, pDuplicate) eventIsDuplicate_DISPATCH(pResource, hMemory, pDuplicate) +#define eventControlSerialization_Epilogue(pResource, pCallContext, pParams) eventControlSerialization_Epilogue_DISPATCH(pResource, pCallContext, pParams) #define eventControl_Epilogue(pResource, pCallContext, pParams) eventControl_Epilogue_DISPATCH(pResource, pCallContext, pParams) #define eventControlLookup(pResource, pParams, ppEntry) eventControlLookup_DISPATCH(pResource, pParams, ppEntry) #define eventMap(pResource, pCallContext, pParams, pCpuMapping) eventMap_DISPATCH(pResource, pCallContext, pParams, pCpuMapping) @@ -275,8 +279,12 @@ pResource->__eventAddAdditionalDependants__(pClient, pResource, pReference); } -static inline NV_STATUS eventUnmap_DISPATCH(struct Event *pResource, struct CALL_CONTEXT *pCallContext, RsCpuMapping *pCpuMapping) { - return pResource->__eventUnmap__(pResource, pCallContext, pCpuMapping); +static inline NV_STATUS eventUnmapFrom_DISPATCH(struct Event *pResource, RS_RES_UNMAP_FROM_PARAMS *pParams) { + return pResource->__eventUnmapFrom__(pResource, pParams); +} + +static inline NV_STATUS eventControlSerialization_Prologue_DISPATCH(struct Event *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return pResource->__eventControlSerialization_Prologue__(pResource, pCallContext, pParams); } static inline NV_STATUS eventControl_Prologue_DISPATCH(struct Event *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { @@ -287,22 +295,26 @@ return pResource->__eventCanCopy__(pResource); } -static inline NV_STATUS eventMapTo_DISPATCH(struct Event *pResource, RS_RES_MAP_TO_PARAMS *pParams) { - return pResource->__eventMapTo__(pResource, pParams); +static inline NV_STATUS eventUnmap_DISPATCH(struct Event *pResource, struct CALL_CONTEXT *pCallContext, RsCpuMapping *pCpuMapping) { + return pResource->__eventUnmap__(pResource, pCallContext, pCpuMapping); } static inline void eventPreDestruct_DISPATCH(struct Event *pResource) { pResource->__eventPreDestruct__(pResource); } -static inline NV_STATUS eventUnmapFrom_DISPATCH(struct Event *pResource, RS_RES_UNMAP_FROM_PARAMS *pParams) { - return pResource->__eventUnmapFrom__(pResource, pParams); +static inline NV_STATUS eventMapTo_DISPATCH(struct Event *pResource, RS_RES_MAP_TO_PARAMS *pParams) { + return pResource->__eventMapTo__(pResource, pParams); } static inline NV_STATUS eventIsDuplicate_DISPATCH(struct Event *pResource, NvHandle hMemory, NvBool *pDuplicate) { return pResource->__eventIsDuplicate__(pResource, hMemory, pDuplicate); } +static inline void eventControlSerialization_Epilogue_DISPATCH(struct Event *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + pResource->__eventControlSerialization_Epilogue__(pResource, pCallContext, pParams); +} + static inline void eventControl_Epilogue_DISPATCH(struct Event *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { pResource->__eventControl_Epilogue__(pResource, pCallContext, pParams); } @@ -530,7 +542,7 @@ struct INotifier **ppNotifier, PEVENTNOTIFICATION **pppEventNotification); -NV_STATUS registerEventNotification(PEVENTNOTIFICATION*, NvHandle, NvHandle, NvHandle, NvU32, NvU32, NvP64, NvBool); +NV_STATUS registerEventNotification(PEVENTNOTIFICATION*, struct RsClient *, NvHandle, NvHandle, NvU32, NvU32, NvP64, NvBool); NV_STATUS unregisterEventNotification(PEVENTNOTIFICATION*, NvHandle, NvHandle, NvHandle); NV_STATUS unregisterEventNotificationWithData(PEVENTNOTIFICATION *, NvHandle, NvHandle, NvHandle, NvBool, NvP64); NV_STATUS bindEventNotificationToSubdevice(PEVENTNOTIFICATION, NvHandle, NvU32); diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/generated/g_fabric_nvoc.c nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_fabric_nvoc.c --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/generated/g_fabric_nvoc.c 2023-10-25 20:26:56.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_fabric_nvoc.c 2024-03-05 22:18:13.000000000 +0000 @@ -114,13 +114,16 @@ Object *pParentObj; Fabric *pThis; - pThis = portMemAllocNonPaged(sizeof(Fabric)); - if (pThis == NULL) return NV_ERR_NO_MEMORY; + status = __nvoc_handleObjCreateMemAlloc(createFlags, sizeof(Fabric), (void**)&pThis, (void**)ppThis); + if (status != NV_OK) + return status; portMemSet(pThis, 0, sizeof(Fabric)); __nvoc_initRtti(staticCast(pThis, Dynamic), &__nvoc_class_def_Fabric); + pThis->__nvoc_base_Object.createFlags = createFlags; + if (pParent != NULL && !(createFlags & NVOC_OBJ_CREATE_FLAGS_PARENT_HALSPEC_ONLY)) { pParentObj = dynamicCast(pParent, Object); @@ -136,11 +139,17 @@ if (status != NV_OK) goto __nvoc_objCreate_Fabric_cleanup; *ppThis = pThis; + return NV_OK; __nvoc_objCreate_Fabric_cleanup: // do not call destructors here since the constructor already called them - portMemFree(pThis); + if (createFlags & NVOC_OBJ_CREATE_FLAGS_IN_PLACE_CONSTRUCT) + portMemSet(pThis, 0, sizeof(Fabric)); + else + portMemFree(pThis); + + // coverity[leaked_storage:FALSE] return status; } diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/generated/g_fabric_nvoc.h nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_fabric_nvoc.h --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/generated/g_fabric_nvoc.h 2023-10-25 20:26:56.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_fabric_nvoc.h 2024-03-05 22:18:13.000000000 +0000 @@ -7,7 +7,7 @@ #endif /* - * SPDX-FileCopyrightText: Copyright (c) 2019-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2019-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/generated/g_fabric_vaspace_nvoc.c nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_fabric_vaspace_nvoc.c --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/generated/g_fabric_vaspace_nvoc.c 2023-10-25 20:26:56.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_fabric_vaspace_nvoc.c 2024-03-05 22:18:13.000000000 +0000 @@ -126,7 +126,7 @@ return vaspaceIsAtsEnabled((struct OBJVASPACE *)(((unsigned char *)pVAS) + __nvoc_rtti_FABRIC_VASPACE_OBJVASPACE.offset)); } -static NvU32 __nvoc_thunk_OBJVASPACE_fabricvaspaceGetBigPageSize(struct FABRIC_VASPACE *pVAS) { +static NvU64 __nvoc_thunk_OBJVASPACE_fabricvaspaceGetBigPageSize(struct FABRIC_VASPACE *pVAS) { return vaspaceGetBigPageSize((struct OBJVASPACE *)(((unsigned char *)pVAS) + __nvoc_rtti_FABRIC_VASPACE_OBJVASPACE.offset)); } @@ -146,7 +146,7 @@ return vaspaceGetKernelPageDirBase((struct OBJVASPACE *)(((unsigned char *)pVAS) + __nvoc_rtti_FABRIC_VASPACE_OBJVASPACE.offset), pGpu); } -static NvU32 __nvoc_thunk_OBJVASPACE_fabricvaspaceGetMapPageSize(struct FABRIC_VASPACE *pVAS, struct OBJGPU *pGpu, EMEMBLOCK *pMemBlock) { +static NvU64 __nvoc_thunk_OBJVASPACE_fabricvaspaceGetMapPageSize(struct FABRIC_VASPACE *pVAS, struct OBJGPU *pGpu, EMEMBLOCK *pMemBlock) { return vaspaceGetMapPageSize((struct OBJVASPACE *)(((unsigned char *)pVAS) + __nvoc_rtti_FABRIC_VASPACE_OBJVASPACE.offset), pGpu, pMemBlock); } @@ -319,13 +319,16 @@ Object *pParentObj; FABRIC_VASPACE *pThis; - pThis = portMemAllocNonPaged(sizeof(FABRIC_VASPACE)); - if (pThis == NULL) return NV_ERR_NO_MEMORY; + status = __nvoc_handleObjCreateMemAlloc(createFlags, sizeof(FABRIC_VASPACE), (void**)&pThis, (void**)ppThis); + if (status != NV_OK) + return status; portMemSet(pThis, 0, sizeof(FABRIC_VASPACE)); __nvoc_initRtti(staticCast(pThis, Dynamic), &__nvoc_class_def_FABRIC_VASPACE); + pThis->__nvoc_base_OBJVASPACE.__nvoc_base_Object.createFlags = createFlags; + if (pParent != NULL && !(createFlags & NVOC_OBJ_CREATE_FLAGS_PARENT_HALSPEC_ONLY)) { pParentObj = dynamicCast(pParent, Object); @@ -341,11 +344,17 @@ if (status != NV_OK) goto __nvoc_objCreate_FABRIC_VASPACE_cleanup; *ppThis = pThis; + return NV_OK; __nvoc_objCreate_FABRIC_VASPACE_cleanup: // do not call destructors here since the constructor already called them - portMemFree(pThis); + if (createFlags & NVOC_OBJ_CREATE_FLAGS_IN_PLACE_CONSTRUCT) + portMemSet(pThis, 0, sizeof(FABRIC_VASPACE)); + else + portMemFree(pThis); + + // coverity[leaked_storage:FALSE] return status; } diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/generated/g_fabric_vaspace_nvoc.h nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_fabric_vaspace_nvoc.h --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/generated/g_fabric_vaspace_nvoc.h 2023-10-25 20:26:56.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_fabric_vaspace_nvoc.h 2024-03-05 22:18:13.000000000 +0000 @@ -7,7 +7,7 @@ #endif /* - * SPDX-FileCopyrightText: Copyright (c) 2021-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2021-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -48,6 +48,7 @@ #include "gpu/mem_mgr/heap.h" #include "gpu/mem_mgr/virt_mem_allocator.h" #include "ctrl/ctrl0080/ctrl0080dma.h" +#include "ctrl/ctrl90f1.h" #include "gpu/mem_mgr/mem_desc.h" #include "containers/list.h" @@ -92,12 +93,12 @@ NvBool (*__fabricvaspaceIsInternalVaRestricted__)(struct FABRIC_VASPACE *); NvU32 (*__fabricvaspaceGetFlags__)(struct FABRIC_VASPACE *); NvBool (*__fabricvaspaceIsAtsEnabled__)(struct FABRIC_VASPACE *); - NvU32 (*__fabricvaspaceGetBigPageSize__)(struct FABRIC_VASPACE *); + NvU64 (*__fabricvaspaceGetBigPageSize__)(struct FABRIC_VASPACE *); NV_STATUS (*__fabricvaspaceGetPteInfo__)(struct FABRIC_VASPACE *, struct OBJGPU *, NV0080_CTRL_DMA_GET_PTE_INFO_PARAMS *, RmPhysAddr *); NvU64 (*__fabricvaspaceGetVaLimit__)(struct FABRIC_VASPACE *); PMEMORY_DESCRIPTOR (*__fabricvaspaceGetPageDirBase__)(struct FABRIC_VASPACE *, struct OBJGPU *); PMEMORY_DESCRIPTOR (*__fabricvaspaceGetKernelPageDirBase__)(struct FABRIC_VASPACE *, struct OBJGPU *); - NvU32 (*__fabricvaspaceGetMapPageSize__)(struct FABRIC_VASPACE *, struct OBJGPU *, EMEMBLOCK *); + NvU64 (*__fabricvaspaceGetMapPageSize__)(struct FABRIC_VASPACE *, struct OBJGPU *, EMEMBLOCK *); struct OBJEHEAP *(*__fabricvaspaceGetHeap__)(struct FABRIC_VASPACE *); NvBool (*__fabricvaspaceIsFaultCapable__)(struct FABRIC_VASPACE *); NvU64 (*__fabricvaspaceGetVaStart__)(struct FABRIC_VASPACE *); @@ -258,7 +259,7 @@ return pVAS->__fabricvaspaceIsAtsEnabled__(pVAS); } -static inline NvU32 fabricvaspaceGetBigPageSize_DISPATCH(struct FABRIC_VASPACE *pVAS) { +static inline NvU64 fabricvaspaceGetBigPageSize_DISPATCH(struct FABRIC_VASPACE *pVAS) { return pVAS->__fabricvaspaceGetBigPageSize__(pVAS); } @@ -278,7 +279,7 @@ return pVAS->__fabricvaspaceGetKernelPageDirBase__(pVAS, pGpu); } -static inline NvU32 fabricvaspaceGetMapPageSize_DISPATCH(struct FABRIC_VASPACE *pVAS, struct OBJGPU *pGpu, EMEMBLOCK *pMemBlock) { +static inline NvU64 fabricvaspaceGetMapPageSize_DISPATCH(struct FABRIC_VASPACE *pVAS, struct OBJGPU *pGpu, EMEMBLOCK *pMemBlock) { return pVAS->__fabricvaspaceGetMapPageSize__(pVAS, pGpu, pMemBlock); } @@ -446,6 +447,38 @@ #define fabricvaspaceInitUCRange(pFabricVAS, pGpu, ucFabricBase, ucFabricSize) fabricvaspaceInitUCRange_IMPL(pFabricVAS, pGpu, ucFabricBase, ucFabricSize) #endif //__nvoc_fabric_vaspace_h_disabled +void fabricvaspaceClearUCRange_IMPL(struct FABRIC_VASPACE *pFabricVAS); + +#ifdef __nvoc_fabric_vaspace_h_disabled +static inline void fabricvaspaceClearUCRange(struct FABRIC_VASPACE *pFabricVAS) { + NV_ASSERT_FAILED_PRECOMP("FABRIC_VASPACE was disabled!"); +} +#else //__nvoc_fabric_vaspace_h_disabled +#define fabricvaspaceClearUCRange(pFabricVAS) fabricvaspaceClearUCRange_IMPL(pFabricVAS) +#endif //__nvoc_fabric_vaspace_h_disabled + +NV_STATUS fabricvaspaceGetPageLevelInfo_IMPL(struct FABRIC_VASPACE *pFabricVAS, struct OBJGPU *pGpu, NV90F1_CTRL_VASPACE_GET_PAGE_LEVEL_INFO_PARAMS *pParams); + +#ifdef __nvoc_fabric_vaspace_h_disabled +static inline NV_STATUS fabricvaspaceGetPageLevelInfo(struct FABRIC_VASPACE *pFabricVAS, struct OBJGPU *pGpu, NV90F1_CTRL_VASPACE_GET_PAGE_LEVEL_INFO_PARAMS *pParams) { + NV_ASSERT_FAILED_PRECOMP("FABRIC_VASPACE was disabled!"); + return NV_ERR_NOT_SUPPORTED; +} +#else //__nvoc_fabric_vaspace_h_disabled +#define fabricvaspaceGetPageLevelInfo(pFabricVAS, pGpu, pParams) fabricvaspaceGetPageLevelInfo_IMPL(pFabricVAS, pGpu, pParams) +#endif //__nvoc_fabric_vaspace_h_disabled + +NvBool fabricvaspaceIsInUse_IMPL(struct FABRIC_VASPACE *pFabricVAS); + +#ifdef __nvoc_fabric_vaspace_h_disabled +static inline NvBool fabricvaspaceIsInUse(struct FABRIC_VASPACE *pFabricVAS) { + NV_ASSERT_FAILED_PRECOMP("FABRIC_VASPACE was disabled!"); + return NV_FALSE; +} +#else //__nvoc_fabric_vaspace_h_disabled +#define fabricvaspaceIsInUse(pFabricVAS) fabricvaspaceIsInUse_IMPL(pFabricVAS) +#endif //__nvoc_fabric_vaspace_h_disabled + #undef PRIVATE_FIELD diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/generated/g_fbsr_nvoc.c nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_fbsr_nvoc.c --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/generated/g_fbsr_nvoc.c 2023-10-25 20:26:57.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_fbsr_nvoc.c 2024-03-05 22:18:13.000000000 +0000 @@ -109,29 +109,34 @@ PORT_UNREFERENCED_VARIABLE(chipHal_HalVarIdx); // Hal function -- fbsrBegin - if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000002UL) )) /* RmVariantHal: PF_KERNEL_ONLY */ + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x100003e0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GH100 */ { - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x01f0fc00UL) )) /* ChipHal: GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 */ - { - pThis->__fbsrBegin__ = &fbsrBegin_GA100; - } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x100003e0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GH100 */ - { - pThis->__fbsrBegin__ = &fbsrBegin_GM107; - } + pThis->__fbsrBegin__ = &fbsrBegin_GM107; + } + else + { + pThis->__fbsrBegin__ = &fbsrBegin_GA100; } // Hal function -- fbsrEnd - if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000002UL) )) /* RmVariantHal: PF_KERNEL_ONLY */ + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x100003e0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GH100 */ + { + pThis->__fbsrEnd__ = &fbsrEnd_GM107; + } + else + { + pThis->__fbsrEnd__ = &fbsrEnd_GA100; + } + + // Hal function -- fbsrSendMemsysProgramRawCompressionMode + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x11f0fc00UL) )) /* ChipHal: GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 | GH100 */ + { + pThis->__fbsrSendMemsysProgramRawCompressionMode__ = &fbsrSendMemsysProgramRawCompressionMode_GA100; + } + // default + else { - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x01f0fc00UL) )) /* ChipHal: GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 */ - { - pThis->__fbsrEnd__ = &fbsrEnd_GA100; - } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x100003e0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GH100 */ - { - pThis->__fbsrEnd__ = &fbsrEnd_GM107; - } + pThis->__fbsrSendMemsysProgramRawCompressionMode__ = &fbsrSendMemsysProgramRawCompressionMode_56cd7a; } } @@ -153,13 +158,16 @@ OBJFBSR *pThis; RmHalspecOwner *pRmhalspecowner; - pThis = portMemAllocNonPaged(sizeof(OBJFBSR)); - if (pThis == NULL) return NV_ERR_NO_MEMORY; + status = __nvoc_handleObjCreateMemAlloc(createFlags, sizeof(OBJFBSR), (void**)&pThis, (void**)ppThis); + if (status != NV_OK) + return status; portMemSet(pThis, 0, sizeof(OBJFBSR)); __nvoc_initRtti(staticCast(pThis, Dynamic), &__nvoc_class_def_OBJFBSR); + pThis->__nvoc_base_Object.createFlags = createFlags; + if (pParent != NULL && !(createFlags & NVOC_OBJ_CREATE_FLAGS_PARENT_HALSPEC_ONLY)) { pParentObj = dynamicCast(pParent, Object); @@ -179,11 +187,17 @@ if (status != NV_OK) goto __nvoc_objCreate_OBJFBSR_cleanup; *ppThis = pThis; + return NV_OK; __nvoc_objCreate_OBJFBSR_cleanup: // do not call destructors here since the constructor already called them - portMemFree(pThis); + if (createFlags & NVOC_OBJ_CREATE_FLAGS_IN_PLACE_CONSTRUCT) + portMemSet(pThis, 0, sizeof(OBJFBSR)); + else + portMemFree(pThis); + + // coverity[leaked_storage:FALSE] return status; } diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/generated/g_fbsr_nvoc.h nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_fbsr_nvoc.h --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/generated/g_fbsr_nvoc.h 2023-10-25 20:26:57.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_fbsr_nvoc.h 2024-03-05 22:18:13.000000000 +0000 @@ -103,6 +103,7 @@ struct OBJFBSR *__nvoc_pbase_OBJFBSR; NV_STATUS (*__fbsrBegin__)(struct OBJGPU *, struct OBJFBSR *, FBSR_OP_TYPE); NV_STATUS (*__fbsrEnd__)(struct OBJGPU *, struct OBJFBSR *); + NV_STATUS (*__fbsrSendMemsysProgramRawCompressionMode__)(struct OBJGPU *, struct OBJFBSR *, NvBool); NvU32 type; struct OBJCE *pCe; FBSR_OP_TYPE op; @@ -158,6 +159,8 @@ #define fbsrBegin_HAL(pGpu, pFbsr, op) fbsrBegin_DISPATCH(pGpu, pFbsr, op) #define fbsrEnd(pGpu, pFbsr) fbsrEnd_DISPATCH(pGpu, pFbsr) #define fbsrEnd_HAL(pGpu, pFbsr) fbsrEnd_DISPATCH(pGpu, pFbsr) +#define fbsrSendMemsysProgramRawCompressionMode(pGpu, pFbsr, bRawMode) fbsrSendMemsysProgramRawCompressionMode_DISPATCH(pGpu, pFbsr, bRawMode) +#define fbsrSendMemsysProgramRawCompressionMode_HAL(pGpu, pFbsr, bRawMode) fbsrSendMemsysProgramRawCompressionMode_DISPATCH(pGpu, pFbsr, bRawMode) static inline NV_STATUS fbsrCreateChannelForCopy_46f6a7(struct OBJGPU *pGpu, struct OBJFBSR *pFbsr) { return NV_ERR_NOT_SUPPORTED; } @@ -262,6 +265,16 @@ return pFbsr->__fbsrEnd__(pGpu, pFbsr); } +NV_STATUS fbsrSendMemsysProgramRawCompressionMode_GA100(struct OBJGPU *pGpu, struct OBJFBSR *pFbsr, NvBool bRawMode); + +static inline NV_STATUS fbsrSendMemsysProgramRawCompressionMode_56cd7a(struct OBJGPU *pGpu, struct OBJFBSR *pFbsr, NvBool bRawMode) { + return NV_OK; +} + +static inline NV_STATUS fbsrSendMemsysProgramRawCompressionMode_DISPATCH(struct OBJGPU *pGpu, struct OBJFBSR *pFbsr, NvBool bRawMode) { + return pFbsr->__fbsrSendMemsysProgramRawCompressionMode__(pGpu, pFbsr, bRawMode); +} + NV_STATUS fbsrObjectInit_IMPL(struct OBJFBSR *pFbsr, NvU32 arg0); #ifdef __nvoc_fbsr_h_disabled diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/generated/g_fecs_event_list_nvoc.h nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_fecs_event_list_nvoc.h --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/generated/g_fecs_event_list_nvoc.h 2023-10-25 20:26:57.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_fecs_event_list_nvoc.h 2024-03-05 22:18:13.000000000 +0000 @@ -44,6 +44,7 @@ #include "class/cl90cdfecs.h" #include "containers/multimap.h" #include "resserv/resserv.h" +#include "rmapi/client.h" #include "ctrl/ctrl2080/ctrl2080gr.h" // NV2080_CTRL_GR_FECS_BIND_EVTBUF_LOD @@ -127,7 +128,7 @@ NV_STATUS fecsAddBindpoint ( OBJGPU *pGpu, - struct RsClient *pClient, + struct RmClient *pClient, RsResourceRef *pEventBufferRef, NvHandle hNotifier, NvBool bAllUsers, diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/generated/g_fla_mem_nvoc.c nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_fla_mem_nvoc.c --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/generated/g_fla_mem_nvoc.c 2023-10-25 20:26:57.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_fla_mem_nvoc.c 2024-03-05 22:18:13.000000000 +0000 @@ -101,60 +101,76 @@ return memCheckMemInterUnmap((struct Memory *)(((unsigned char *)pMemory) + __nvoc_rtti_FlaMemory_Memory.offset), bSubdeviceHandleProvided); } -static NV_STATUS __nvoc_thunk_Memory_flamemControl(struct FlaMemory *pMemory, CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { - return memControl((struct Memory *)(((unsigned char *)pMemory) + __nvoc_rtti_FlaMemory_Memory.offset), pCallContext, pParams); +static NvBool __nvoc_thunk_RmResource_flamemShareCallback(struct FlaMemory *pResource, struct RsClient *pInvokingClient, struct RsResourceRef *pParentRef, RS_SHARE_POLICY *pSharePolicy) { + return rmresShareCallback((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_FlaMemory_RmResource.offset), pInvokingClient, pParentRef, pSharePolicy); } -static NV_STATUS __nvoc_thunk_Memory_flamemUnmap(struct FlaMemory *pMemory, CALL_CONTEXT *pCallContext, RsCpuMapping *pCpuMapping) { - return memUnmap((struct Memory *)(((unsigned char *)pMemory) + __nvoc_rtti_FlaMemory_Memory.offset), pCallContext, pCpuMapping); +static NV_STATUS __nvoc_thunk_RsResource_flamemMapTo(struct FlaMemory *pResource, RS_RES_MAP_TO_PARAMS *pParams) { + return resMapTo((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_FlaMemory_RsResource.offset), pParams); } -static NV_STATUS __nvoc_thunk_Memory_flamemGetMemInterMapParams(struct FlaMemory *pMemory, RMRES_MEM_INTER_MAP_PARAMS *pParams) { - return memGetMemInterMapParams((struct Memory *)(((unsigned char *)pMemory) + __nvoc_rtti_FlaMemory_Memory.offset), pParams); +static NV_STATUS __nvoc_thunk_Memory_flamemGetMapAddrSpace(struct FlaMemory *pMemory, CALL_CONTEXT *pCallContext, NvU32 mapFlags, NV_ADDRESS_SPACE *pAddrSpace) { + return memGetMapAddrSpace((struct Memory *)(((unsigned char *)pMemory) + __nvoc_rtti_FlaMemory_Memory.offset), pCallContext, mapFlags, pAddrSpace); } -static NV_STATUS __nvoc_thunk_Memory_flamemGetMemoryMappingDescriptor(struct FlaMemory *pMemory, MEMORY_DESCRIPTOR **ppMemDesc) { - return memGetMemoryMappingDescriptor((struct Memory *)(((unsigned char *)pMemory) + __nvoc_rtti_FlaMemory_Memory.offset), ppMemDesc); +static NvU32 __nvoc_thunk_RsResource_flamemGetRefCount(struct FlaMemory *pResource) { + return resGetRefCount((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_FlaMemory_RsResource.offset)); } -static NV_STATUS __nvoc_thunk_Memory_flamemGetMapAddrSpace(struct FlaMemory *pMemory, CALL_CONTEXT *pCallContext, NvU32 mapFlags, NV_ADDRESS_SPACE *pAddrSpace) { - return memGetMapAddrSpace((struct Memory *)(((unsigned char *)pMemory) + __nvoc_rtti_FlaMemory_Memory.offset), pCallContext, mapFlags, pAddrSpace); +static void __nvoc_thunk_RsResource_flamemAddAdditionalDependants(struct RsClient *pClient, struct FlaMemory *pResource, RsResourceRef *pReference) { + resAddAdditionalDependants(pClient, (struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_FlaMemory_RsResource.offset), pReference); } -static NvBool __nvoc_thunk_RmResource_flamemShareCallback(struct FlaMemory *pResource, struct RsClient *pInvokingClient, struct RsResourceRef *pParentRef, RS_SHARE_POLICY *pSharePolicy) { - return rmresShareCallback((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_FlaMemory_RmResource.offset), pInvokingClient, pParentRef, pSharePolicy); +static NV_STATUS __nvoc_thunk_RmResource_flamemControl_Prologue(struct FlaMemory *pResource, CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return rmresControl_Prologue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_FlaMemory_RmResource.offset), pCallContext, pParams); } -static NV_STATUS __nvoc_thunk_RsResource_flamemControlFilter(struct FlaMemory *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { - return resControlFilter((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_FlaMemory_RsResource.offset), pCallContext, pParams); +static NvBool __nvoc_thunk_Memory_flamemIsGpuMapAllowed(struct FlaMemory *pMemory, struct OBJGPU *pGpu) { + return memIsGpuMapAllowed((struct Memory *)(((unsigned char *)pMemory) + __nvoc_rtti_FlaMemory_Memory.offset), pGpu); } -static void __nvoc_thunk_RsResource_flamemAddAdditionalDependants(struct RsClient *pClient, struct FlaMemory *pResource, RsResourceRef *pReference) { - resAddAdditionalDependants(pClient, (struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_FlaMemory_RsResource.offset), pReference); +static NV_STATUS __nvoc_thunk_RsResource_flamemUnmapFrom(struct FlaMemory *pResource, RS_RES_UNMAP_FROM_PARAMS *pParams) { + return resUnmapFrom((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_FlaMemory_RsResource.offset), pParams); } -static NvU32 __nvoc_thunk_RsResource_flamemGetRefCount(struct FlaMemory *pResource) { - return resGetRefCount((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_FlaMemory_RsResource.offset)); +static void __nvoc_thunk_RmResource_flamemControl_Epilogue(struct FlaMemory *pResource, CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + rmresControl_Epilogue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_FlaMemory_RmResource.offset), pCallContext, pParams); } -static NV_STATUS __nvoc_thunk_RsResource_flamemMapTo(struct FlaMemory *pResource, RS_RES_MAP_TO_PARAMS *pParams) { - return resMapTo((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_FlaMemory_RsResource.offset), pParams); +static NV_STATUS __nvoc_thunk_RsResource_flamemControlLookup(struct FlaMemory *pResource, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams, const struct NVOC_EXPORTED_METHOD_DEF **ppEntry) { + return resControlLookup((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_FlaMemory_RsResource.offset), pParams, ppEntry); } -static NV_STATUS __nvoc_thunk_RmResource_flamemControl_Prologue(struct FlaMemory *pResource, CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { - return rmresControl_Prologue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_FlaMemory_RmResource.offset), pCallContext, pParams); +static NV_STATUS __nvoc_thunk_Memory_flamemControl(struct FlaMemory *pMemory, CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return memControl((struct Memory *)(((unsigned char *)pMemory) + __nvoc_rtti_FlaMemory_Memory.offset), pCallContext, pParams); } -static NvBool __nvoc_thunk_Memory_flamemIsGpuMapAllowed(struct FlaMemory *pMemory, struct OBJGPU *pGpu) { - return memIsGpuMapAllowed((struct Memory *)(((unsigned char *)pMemory) + __nvoc_rtti_FlaMemory_Memory.offset), pGpu); +static NV_STATUS __nvoc_thunk_Memory_flamemUnmap(struct FlaMemory *pMemory, CALL_CONTEXT *pCallContext, RsCpuMapping *pCpuMapping) { + return memUnmap((struct Memory *)(((unsigned char *)pMemory) + __nvoc_rtti_FlaMemory_Memory.offset), pCallContext, pCpuMapping); +} + +static NV_STATUS __nvoc_thunk_Memory_flamemGetMemInterMapParams(struct FlaMemory *pMemory, RMRES_MEM_INTER_MAP_PARAMS *pParams) { + return memGetMemInterMapParams((struct Memory *)(((unsigned char *)pMemory) + __nvoc_rtti_FlaMemory_Memory.offset), pParams); +} + +static NV_STATUS __nvoc_thunk_Memory_flamemGetMemoryMappingDescriptor(struct FlaMemory *pMemory, MEMORY_DESCRIPTOR **ppMemDesc) { + return memGetMemoryMappingDescriptor((struct Memory *)(((unsigned char *)pMemory) + __nvoc_rtti_FlaMemory_Memory.offset), ppMemDesc); +} + +static NV_STATUS __nvoc_thunk_RsResource_flamemControlFilter(struct FlaMemory *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return resControlFilter((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_FlaMemory_RsResource.offset), pCallContext, pParams); +} + +static NV_STATUS __nvoc_thunk_RmResource_flamemControlSerialization_Prologue(struct FlaMemory *pResource, CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return rmresControlSerialization_Prologue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_FlaMemory_RmResource.offset), pCallContext, pParams); } static NV_STATUS __nvoc_thunk_Memory_flamemIsReady(struct FlaMemory *pMemory, NvBool bCopyConstructorContext) { return memIsReady((struct Memory *)(((unsigned char *)pMemory) + __nvoc_rtti_FlaMemory_Memory.offset), bCopyConstructorContext); } -static NV_STATUS __nvoc_thunk_Memory_flamemCheckCopyPermissions(struct FlaMemory *pMemory, struct OBJGPU *pDstGpu, NvHandle hDstClientNvBool) { - return memCheckCopyPermissions((struct Memory *)(((unsigned char *)pMemory) + __nvoc_rtti_FlaMemory_Memory.offset), pDstGpu, hDstClientNvBool); +static NV_STATUS __nvoc_thunk_Memory_flamemCheckCopyPermissions(struct FlaMemory *pMemory, struct OBJGPU *pDstGpu, struct Device *pDstDevice) { + return memCheckCopyPermissions((struct Memory *)(((unsigned char *)pMemory) + __nvoc_rtti_FlaMemory_Memory.offset), pDstGpu, pDstDevice); } static void __nvoc_thunk_RsResource_flamemPreDestruct(struct FlaMemory *pResource) { @@ -165,16 +181,8 @@ return memIsDuplicate((struct Memory *)(((unsigned char *)pMemory) + __nvoc_rtti_FlaMemory_Memory.offset), hMemory, pDuplicate); } -static NV_STATUS __nvoc_thunk_RsResource_flamemUnmapFrom(struct FlaMemory *pResource, RS_RES_UNMAP_FROM_PARAMS *pParams) { - return resUnmapFrom((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_FlaMemory_RsResource.offset), pParams); -} - -static void __nvoc_thunk_RmResource_flamemControl_Epilogue(struct FlaMemory *pResource, CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { - rmresControl_Epilogue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_FlaMemory_RmResource.offset), pCallContext, pParams); -} - -static NV_STATUS __nvoc_thunk_RsResource_flamemControlLookup(struct FlaMemory *pResource, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams, const struct NVOC_EXPORTED_METHOD_DEF **ppEntry) { - return resControlLookup((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_FlaMemory_RsResource.offset), pParams, ppEntry); +static void __nvoc_thunk_RmResource_flamemControlSerialization_Epilogue(struct FlaMemory *pResource, CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + rmresControlSerialization_Epilogue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_FlaMemory_RmResource.offset), pCallContext, pParams); } static NV_STATUS __nvoc_thunk_Memory_flamemMap(struct FlaMemory *pMemory, CALL_CONTEXT *pCallContext, struct RS_CPU_MAP_PARAMS *pParams, RsCpuMapping *pCpuMapping) { @@ -232,29 +240,37 @@ pThis->__flamemCheckMemInterUnmap__ = &__nvoc_thunk_Memory_flamemCheckMemInterUnmap; - pThis->__flamemControl__ = &__nvoc_thunk_Memory_flamemControl; + pThis->__flamemShareCallback__ = &__nvoc_thunk_RmResource_flamemShareCallback; - pThis->__flamemUnmap__ = &__nvoc_thunk_Memory_flamemUnmap; + pThis->__flamemMapTo__ = &__nvoc_thunk_RsResource_flamemMapTo; - pThis->__flamemGetMemInterMapParams__ = &__nvoc_thunk_Memory_flamemGetMemInterMapParams; + pThis->__flamemGetMapAddrSpace__ = &__nvoc_thunk_Memory_flamemGetMapAddrSpace; - pThis->__flamemGetMemoryMappingDescriptor__ = &__nvoc_thunk_Memory_flamemGetMemoryMappingDescriptor; + pThis->__flamemGetRefCount__ = &__nvoc_thunk_RsResource_flamemGetRefCount; - pThis->__flamemGetMapAddrSpace__ = &__nvoc_thunk_Memory_flamemGetMapAddrSpace; + pThis->__flamemAddAdditionalDependants__ = &__nvoc_thunk_RsResource_flamemAddAdditionalDependants; - pThis->__flamemShareCallback__ = &__nvoc_thunk_RmResource_flamemShareCallback; + pThis->__flamemControl_Prologue__ = &__nvoc_thunk_RmResource_flamemControl_Prologue; - pThis->__flamemControlFilter__ = &__nvoc_thunk_RsResource_flamemControlFilter; + pThis->__flamemIsGpuMapAllowed__ = &__nvoc_thunk_Memory_flamemIsGpuMapAllowed; - pThis->__flamemAddAdditionalDependants__ = &__nvoc_thunk_RsResource_flamemAddAdditionalDependants; + pThis->__flamemUnmapFrom__ = &__nvoc_thunk_RsResource_flamemUnmapFrom; - pThis->__flamemGetRefCount__ = &__nvoc_thunk_RsResource_flamemGetRefCount; + pThis->__flamemControl_Epilogue__ = &__nvoc_thunk_RmResource_flamemControl_Epilogue; - pThis->__flamemMapTo__ = &__nvoc_thunk_RsResource_flamemMapTo; + pThis->__flamemControlLookup__ = &__nvoc_thunk_RsResource_flamemControlLookup; - pThis->__flamemControl_Prologue__ = &__nvoc_thunk_RmResource_flamemControl_Prologue; + pThis->__flamemControl__ = &__nvoc_thunk_Memory_flamemControl; - pThis->__flamemIsGpuMapAllowed__ = &__nvoc_thunk_Memory_flamemIsGpuMapAllowed; + pThis->__flamemUnmap__ = &__nvoc_thunk_Memory_flamemUnmap; + + pThis->__flamemGetMemInterMapParams__ = &__nvoc_thunk_Memory_flamemGetMemInterMapParams; + + pThis->__flamemGetMemoryMappingDescriptor__ = &__nvoc_thunk_Memory_flamemGetMemoryMappingDescriptor; + + pThis->__flamemControlFilter__ = &__nvoc_thunk_RsResource_flamemControlFilter; + + pThis->__flamemControlSerialization_Prologue__ = &__nvoc_thunk_RmResource_flamemControlSerialization_Prologue; pThis->__flamemIsReady__ = &__nvoc_thunk_Memory_flamemIsReady; @@ -264,11 +280,7 @@ pThis->__flamemIsDuplicate__ = &__nvoc_thunk_Memory_flamemIsDuplicate; - pThis->__flamemUnmapFrom__ = &__nvoc_thunk_RsResource_flamemUnmapFrom; - - pThis->__flamemControl_Epilogue__ = &__nvoc_thunk_RmResource_flamemControl_Epilogue; - - pThis->__flamemControlLookup__ = &__nvoc_thunk_RsResource_flamemControlLookup; + pThis->__flamemControlSerialization_Epilogue__ = &__nvoc_thunk_RmResource_flamemControlSerialization_Epilogue; pThis->__flamemMap__ = &__nvoc_thunk_Memory_flamemMap; @@ -296,13 +308,16 @@ Object *pParentObj; FlaMemory *pThis; - pThis = portMemAllocNonPaged(sizeof(FlaMemory)); - if (pThis == NULL) return NV_ERR_NO_MEMORY; + status = __nvoc_handleObjCreateMemAlloc(createFlags, sizeof(FlaMemory), (void**)&pThis, (void**)ppThis); + if (status != NV_OK) + return status; portMemSet(pThis, 0, sizeof(FlaMemory)); __nvoc_initRtti(staticCast(pThis, Dynamic), &__nvoc_class_def_FlaMemory); + pThis->__nvoc_base_Memory.__nvoc_base_RmResource.__nvoc_base_RsResource.__nvoc_base_Object.createFlags = createFlags; + if (pParent != NULL && !(createFlags & NVOC_OBJ_CREATE_FLAGS_PARENT_HALSPEC_ONLY)) { pParentObj = dynamicCast(pParent, Object); @@ -318,11 +333,17 @@ if (status != NV_OK) goto __nvoc_objCreate_FlaMemory_cleanup; *ppThis = pThis; + return NV_OK; __nvoc_objCreate_FlaMemory_cleanup: // do not call destructors here since the constructor already called them - portMemFree(pThis); + if (createFlags & NVOC_OBJ_CREATE_FLAGS_IN_PLACE_CONSTRUCT) + portMemSet(pThis, 0, sizeof(FlaMemory)); + else + portMemFree(pThis); + + // coverity[leaked_storage:FALSE] return status; } diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/generated/g_fla_mem_nvoc.h nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_fla_mem_nvoc.h --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/generated/g_fla_mem_nvoc.h 2023-10-25 20:26:57.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_fla_mem_nvoc.h 2024-03-05 22:18:14.000000000 +0000 @@ -56,25 +56,27 @@ NvBool (*__flamemCanCopy__)(struct FlaMemory *); NV_STATUS (*__flamemCopyConstruct__)(struct FlaMemory *, CALL_CONTEXT *, struct RS_RES_ALLOC_PARAMS_INTERNAL *); NV_STATUS (*__flamemCheckMemInterUnmap__)(struct FlaMemory *, NvBool); + NvBool (*__flamemShareCallback__)(struct FlaMemory *, struct RsClient *, struct RsResourceRef *, RS_SHARE_POLICY *); + NV_STATUS (*__flamemMapTo__)(struct FlaMemory *, RS_RES_MAP_TO_PARAMS *); + NV_STATUS (*__flamemGetMapAddrSpace__)(struct FlaMemory *, CALL_CONTEXT *, NvU32, NV_ADDRESS_SPACE *); + NvU32 (*__flamemGetRefCount__)(struct FlaMemory *); + void (*__flamemAddAdditionalDependants__)(struct RsClient *, struct FlaMemory *, RsResourceRef *); + NV_STATUS (*__flamemControl_Prologue__)(struct FlaMemory *, CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); + NvBool (*__flamemIsGpuMapAllowed__)(struct FlaMemory *, struct OBJGPU *); + NV_STATUS (*__flamemUnmapFrom__)(struct FlaMemory *, RS_RES_UNMAP_FROM_PARAMS *); + void (*__flamemControl_Epilogue__)(struct FlaMemory *, CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); + NV_STATUS (*__flamemControlLookup__)(struct FlaMemory *, struct RS_RES_CONTROL_PARAMS_INTERNAL *, const struct NVOC_EXPORTED_METHOD_DEF **); NV_STATUS (*__flamemControl__)(struct FlaMemory *, CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); NV_STATUS (*__flamemUnmap__)(struct FlaMemory *, CALL_CONTEXT *, RsCpuMapping *); NV_STATUS (*__flamemGetMemInterMapParams__)(struct FlaMemory *, RMRES_MEM_INTER_MAP_PARAMS *); NV_STATUS (*__flamemGetMemoryMappingDescriptor__)(struct FlaMemory *, MEMORY_DESCRIPTOR **); - NV_STATUS (*__flamemGetMapAddrSpace__)(struct FlaMemory *, CALL_CONTEXT *, NvU32, NV_ADDRESS_SPACE *); - NvBool (*__flamemShareCallback__)(struct FlaMemory *, struct RsClient *, struct RsResourceRef *, RS_SHARE_POLICY *); NV_STATUS (*__flamemControlFilter__)(struct FlaMemory *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); - void (*__flamemAddAdditionalDependants__)(struct RsClient *, struct FlaMemory *, RsResourceRef *); - NvU32 (*__flamemGetRefCount__)(struct FlaMemory *); - NV_STATUS (*__flamemMapTo__)(struct FlaMemory *, RS_RES_MAP_TO_PARAMS *); - NV_STATUS (*__flamemControl_Prologue__)(struct FlaMemory *, CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); - NvBool (*__flamemIsGpuMapAllowed__)(struct FlaMemory *, struct OBJGPU *); + NV_STATUS (*__flamemControlSerialization_Prologue__)(struct FlaMemory *, CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); NV_STATUS (*__flamemIsReady__)(struct FlaMemory *, NvBool); - NV_STATUS (*__flamemCheckCopyPermissions__)(struct FlaMemory *, struct OBJGPU *, NvHandle); + NV_STATUS (*__flamemCheckCopyPermissions__)(struct FlaMemory *, struct OBJGPU *, struct Device *); void (*__flamemPreDestruct__)(struct FlaMemory *); NV_STATUS (*__flamemIsDuplicate__)(struct FlaMemory *, NvHandle, NvBool *); - NV_STATUS (*__flamemUnmapFrom__)(struct FlaMemory *, RS_RES_UNMAP_FROM_PARAMS *); - void (*__flamemControl_Epilogue__)(struct FlaMemory *, CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); - NV_STATUS (*__flamemControlLookup__)(struct FlaMemory *, struct RS_RES_CONTROL_PARAMS_INTERNAL *, const struct NVOC_EXPORTED_METHOD_DEF **); + void (*__flamemControlSerialization_Epilogue__)(struct FlaMemory *, CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); NV_STATUS (*__flamemMap__)(struct FlaMemory *, CALL_CONTEXT *, struct RS_CPU_MAP_PARAMS *, RsCpuMapping *); NvBool (*__flamemAccessCallback__)(struct FlaMemory *, struct RsClient *, void *, RsAccessRight); NvU32 peerDeviceInst; @@ -113,25 +115,27 @@ #define flamemCanCopy(pFlaMemory) flamemCanCopy_DISPATCH(pFlaMemory) #define flamemCopyConstruct(pFlaMemory, pCallContext, pParams) flamemCopyConstruct_DISPATCH(pFlaMemory, pCallContext, pParams) #define flamemCheckMemInterUnmap(pMemory, bSubdeviceHandleProvided) flamemCheckMemInterUnmap_DISPATCH(pMemory, bSubdeviceHandleProvided) +#define flamemShareCallback(pResource, pInvokingClient, pParentRef, pSharePolicy) flamemShareCallback_DISPATCH(pResource, pInvokingClient, pParentRef, pSharePolicy) +#define flamemMapTo(pResource, pParams) flamemMapTo_DISPATCH(pResource, pParams) +#define flamemGetMapAddrSpace(pMemory, pCallContext, mapFlags, pAddrSpace) flamemGetMapAddrSpace_DISPATCH(pMemory, pCallContext, mapFlags, pAddrSpace) +#define flamemGetRefCount(pResource) flamemGetRefCount_DISPATCH(pResource) +#define flamemAddAdditionalDependants(pClient, pResource, pReference) flamemAddAdditionalDependants_DISPATCH(pClient, pResource, pReference) +#define flamemControl_Prologue(pResource, pCallContext, pParams) flamemControl_Prologue_DISPATCH(pResource, pCallContext, pParams) +#define flamemIsGpuMapAllowed(pMemory, pGpu) flamemIsGpuMapAllowed_DISPATCH(pMemory, pGpu) +#define flamemUnmapFrom(pResource, pParams) flamemUnmapFrom_DISPATCH(pResource, pParams) +#define flamemControl_Epilogue(pResource, pCallContext, pParams) flamemControl_Epilogue_DISPATCH(pResource, pCallContext, pParams) +#define flamemControlLookup(pResource, pParams, ppEntry) flamemControlLookup_DISPATCH(pResource, pParams, ppEntry) #define flamemControl(pMemory, pCallContext, pParams) flamemControl_DISPATCH(pMemory, pCallContext, pParams) #define flamemUnmap(pMemory, pCallContext, pCpuMapping) flamemUnmap_DISPATCH(pMemory, pCallContext, pCpuMapping) #define flamemGetMemInterMapParams(pMemory, pParams) flamemGetMemInterMapParams_DISPATCH(pMemory, pParams) #define flamemGetMemoryMappingDescriptor(pMemory, ppMemDesc) flamemGetMemoryMappingDescriptor_DISPATCH(pMemory, ppMemDesc) -#define flamemGetMapAddrSpace(pMemory, pCallContext, mapFlags, pAddrSpace) flamemGetMapAddrSpace_DISPATCH(pMemory, pCallContext, mapFlags, pAddrSpace) -#define flamemShareCallback(pResource, pInvokingClient, pParentRef, pSharePolicy) flamemShareCallback_DISPATCH(pResource, pInvokingClient, pParentRef, pSharePolicy) #define flamemControlFilter(pResource, pCallContext, pParams) flamemControlFilter_DISPATCH(pResource, pCallContext, pParams) -#define flamemAddAdditionalDependants(pClient, pResource, pReference) flamemAddAdditionalDependants_DISPATCH(pClient, pResource, pReference) -#define flamemGetRefCount(pResource) flamemGetRefCount_DISPATCH(pResource) -#define flamemMapTo(pResource, pParams) flamemMapTo_DISPATCH(pResource, pParams) -#define flamemControl_Prologue(pResource, pCallContext, pParams) flamemControl_Prologue_DISPATCH(pResource, pCallContext, pParams) -#define flamemIsGpuMapAllowed(pMemory, pGpu) flamemIsGpuMapAllowed_DISPATCH(pMemory, pGpu) +#define flamemControlSerialization_Prologue(pResource, pCallContext, pParams) flamemControlSerialization_Prologue_DISPATCH(pResource, pCallContext, pParams) #define flamemIsReady(pMemory, bCopyConstructorContext) flamemIsReady_DISPATCH(pMemory, bCopyConstructorContext) -#define flamemCheckCopyPermissions(pMemory, pDstGpu, hDstClientNvBool) flamemCheckCopyPermissions_DISPATCH(pMemory, pDstGpu, hDstClientNvBool) +#define flamemCheckCopyPermissions(pMemory, pDstGpu, pDstDevice) flamemCheckCopyPermissions_DISPATCH(pMemory, pDstGpu, pDstDevice) #define flamemPreDestruct(pResource) flamemPreDestruct_DISPATCH(pResource) #define flamemIsDuplicate(pMemory, hMemory, pDuplicate) flamemIsDuplicate_DISPATCH(pMemory, hMemory, pDuplicate) -#define flamemUnmapFrom(pResource, pParams) flamemUnmapFrom_DISPATCH(pResource, pParams) -#define flamemControl_Epilogue(pResource, pCallContext, pParams) flamemControl_Epilogue_DISPATCH(pResource, pCallContext, pParams) -#define flamemControlLookup(pResource, pParams, ppEntry) flamemControlLookup_DISPATCH(pResource, pParams, ppEntry) +#define flamemControlSerialization_Epilogue(pResource, pCallContext, pParams) flamemControlSerialization_Epilogue_DISPATCH(pResource, pCallContext, pParams) #define flamemMap(pMemory, pCallContext, pParams, pCpuMapping) flamemMap_DISPATCH(pMemory, pCallContext, pParams, pCpuMapping) #define flamemAccessCallback(pResource, pInvokingClient, pAllocParams, accessRight) flamemAccessCallback_DISPATCH(pResource, pInvokingClient, pAllocParams, accessRight) NvBool flamemCanCopy_IMPL(struct FlaMemory *pFlaMemory); @@ -150,60 +154,76 @@ return pMemory->__flamemCheckMemInterUnmap__(pMemory, bSubdeviceHandleProvided); } -static inline NV_STATUS flamemControl_DISPATCH(struct FlaMemory *pMemory, CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { - return pMemory->__flamemControl__(pMemory, pCallContext, pParams); +static inline NvBool flamemShareCallback_DISPATCH(struct FlaMemory *pResource, struct RsClient *pInvokingClient, struct RsResourceRef *pParentRef, RS_SHARE_POLICY *pSharePolicy) { + return pResource->__flamemShareCallback__(pResource, pInvokingClient, pParentRef, pSharePolicy); } -static inline NV_STATUS flamemUnmap_DISPATCH(struct FlaMemory *pMemory, CALL_CONTEXT *pCallContext, RsCpuMapping *pCpuMapping) { - return pMemory->__flamemUnmap__(pMemory, pCallContext, pCpuMapping); +static inline NV_STATUS flamemMapTo_DISPATCH(struct FlaMemory *pResource, RS_RES_MAP_TO_PARAMS *pParams) { + return pResource->__flamemMapTo__(pResource, pParams); } -static inline NV_STATUS flamemGetMemInterMapParams_DISPATCH(struct FlaMemory *pMemory, RMRES_MEM_INTER_MAP_PARAMS *pParams) { - return pMemory->__flamemGetMemInterMapParams__(pMemory, pParams); +static inline NV_STATUS flamemGetMapAddrSpace_DISPATCH(struct FlaMemory *pMemory, CALL_CONTEXT *pCallContext, NvU32 mapFlags, NV_ADDRESS_SPACE *pAddrSpace) { + return pMemory->__flamemGetMapAddrSpace__(pMemory, pCallContext, mapFlags, pAddrSpace); } -static inline NV_STATUS flamemGetMemoryMappingDescriptor_DISPATCH(struct FlaMemory *pMemory, MEMORY_DESCRIPTOR **ppMemDesc) { - return pMemory->__flamemGetMemoryMappingDescriptor__(pMemory, ppMemDesc); +static inline NvU32 flamemGetRefCount_DISPATCH(struct FlaMemory *pResource) { + return pResource->__flamemGetRefCount__(pResource); } -static inline NV_STATUS flamemGetMapAddrSpace_DISPATCH(struct FlaMemory *pMemory, CALL_CONTEXT *pCallContext, NvU32 mapFlags, NV_ADDRESS_SPACE *pAddrSpace) { - return pMemory->__flamemGetMapAddrSpace__(pMemory, pCallContext, mapFlags, pAddrSpace); +static inline void flamemAddAdditionalDependants_DISPATCH(struct RsClient *pClient, struct FlaMemory *pResource, RsResourceRef *pReference) { + pResource->__flamemAddAdditionalDependants__(pClient, pResource, pReference); } -static inline NvBool flamemShareCallback_DISPATCH(struct FlaMemory *pResource, struct RsClient *pInvokingClient, struct RsResourceRef *pParentRef, RS_SHARE_POLICY *pSharePolicy) { - return pResource->__flamemShareCallback__(pResource, pInvokingClient, pParentRef, pSharePolicy); +static inline NV_STATUS flamemControl_Prologue_DISPATCH(struct FlaMemory *pResource, CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return pResource->__flamemControl_Prologue__(pResource, pCallContext, pParams); } -static inline NV_STATUS flamemControlFilter_DISPATCH(struct FlaMemory *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { - return pResource->__flamemControlFilter__(pResource, pCallContext, pParams); +static inline NvBool flamemIsGpuMapAllowed_DISPATCH(struct FlaMemory *pMemory, struct OBJGPU *pGpu) { + return pMemory->__flamemIsGpuMapAllowed__(pMemory, pGpu); } -static inline void flamemAddAdditionalDependants_DISPATCH(struct RsClient *pClient, struct FlaMemory *pResource, RsResourceRef *pReference) { - pResource->__flamemAddAdditionalDependants__(pClient, pResource, pReference); +static inline NV_STATUS flamemUnmapFrom_DISPATCH(struct FlaMemory *pResource, RS_RES_UNMAP_FROM_PARAMS *pParams) { + return pResource->__flamemUnmapFrom__(pResource, pParams); } -static inline NvU32 flamemGetRefCount_DISPATCH(struct FlaMemory *pResource) { - return pResource->__flamemGetRefCount__(pResource); +static inline void flamemControl_Epilogue_DISPATCH(struct FlaMemory *pResource, CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + pResource->__flamemControl_Epilogue__(pResource, pCallContext, pParams); } -static inline NV_STATUS flamemMapTo_DISPATCH(struct FlaMemory *pResource, RS_RES_MAP_TO_PARAMS *pParams) { - return pResource->__flamemMapTo__(pResource, pParams); +static inline NV_STATUS flamemControlLookup_DISPATCH(struct FlaMemory *pResource, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams, const struct NVOC_EXPORTED_METHOD_DEF **ppEntry) { + return pResource->__flamemControlLookup__(pResource, pParams, ppEntry); } -static inline NV_STATUS flamemControl_Prologue_DISPATCH(struct FlaMemory *pResource, CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { - return pResource->__flamemControl_Prologue__(pResource, pCallContext, pParams); +static inline NV_STATUS flamemControl_DISPATCH(struct FlaMemory *pMemory, CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return pMemory->__flamemControl__(pMemory, pCallContext, pParams); } -static inline NvBool flamemIsGpuMapAllowed_DISPATCH(struct FlaMemory *pMemory, struct OBJGPU *pGpu) { - return pMemory->__flamemIsGpuMapAllowed__(pMemory, pGpu); +static inline NV_STATUS flamemUnmap_DISPATCH(struct FlaMemory *pMemory, CALL_CONTEXT *pCallContext, RsCpuMapping *pCpuMapping) { + return pMemory->__flamemUnmap__(pMemory, pCallContext, pCpuMapping); +} + +static inline NV_STATUS flamemGetMemInterMapParams_DISPATCH(struct FlaMemory *pMemory, RMRES_MEM_INTER_MAP_PARAMS *pParams) { + return pMemory->__flamemGetMemInterMapParams__(pMemory, pParams); +} + +static inline NV_STATUS flamemGetMemoryMappingDescriptor_DISPATCH(struct FlaMemory *pMemory, MEMORY_DESCRIPTOR **ppMemDesc) { + return pMemory->__flamemGetMemoryMappingDescriptor__(pMemory, ppMemDesc); +} + +static inline NV_STATUS flamemControlFilter_DISPATCH(struct FlaMemory *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return pResource->__flamemControlFilter__(pResource, pCallContext, pParams); +} + +static inline NV_STATUS flamemControlSerialization_Prologue_DISPATCH(struct FlaMemory *pResource, CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return pResource->__flamemControlSerialization_Prologue__(pResource, pCallContext, pParams); } static inline NV_STATUS flamemIsReady_DISPATCH(struct FlaMemory *pMemory, NvBool bCopyConstructorContext) { return pMemory->__flamemIsReady__(pMemory, bCopyConstructorContext); } -static inline NV_STATUS flamemCheckCopyPermissions_DISPATCH(struct FlaMemory *pMemory, struct OBJGPU *pDstGpu, NvHandle hDstClientNvBool) { - return pMemory->__flamemCheckCopyPermissions__(pMemory, pDstGpu, hDstClientNvBool); +static inline NV_STATUS flamemCheckCopyPermissions_DISPATCH(struct FlaMemory *pMemory, struct OBJGPU *pDstGpu, struct Device *pDstDevice) { + return pMemory->__flamemCheckCopyPermissions__(pMemory, pDstGpu, pDstDevice); } static inline void flamemPreDestruct_DISPATCH(struct FlaMemory *pResource) { @@ -214,16 +234,8 @@ return pMemory->__flamemIsDuplicate__(pMemory, hMemory, pDuplicate); } -static inline NV_STATUS flamemUnmapFrom_DISPATCH(struct FlaMemory *pResource, RS_RES_UNMAP_FROM_PARAMS *pParams) { - return pResource->__flamemUnmapFrom__(pResource, pParams); -} - -static inline void flamemControl_Epilogue_DISPATCH(struct FlaMemory *pResource, CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { - pResource->__flamemControl_Epilogue__(pResource, pCallContext, pParams); -} - -static inline NV_STATUS flamemControlLookup_DISPATCH(struct FlaMemory *pResource, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams, const struct NVOC_EXPORTED_METHOD_DEF **ppEntry) { - return pResource->__flamemControlLookup__(pResource, pParams, ppEntry); +static inline void flamemControlSerialization_Epilogue_DISPATCH(struct FlaMemory *pResource, CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + pResource->__flamemControlSerialization_Epilogue__(pResource, pCallContext, pParams); } static inline NV_STATUS flamemMap_DISPATCH(struct FlaMemory *pMemory, CALL_CONTEXT *pCallContext, struct RS_CPU_MAP_PARAMS *pParams, RsCpuMapping *pCpuMapping) { diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/generated/g_fm_session_api_nvoc.c nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_fm_session_api_nvoc.c --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/generated/g_fm_session_api_nvoc.c 2023-10-25 20:26:57.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_fm_session_api_nvoc.c 2024-03-05 22:18:14.000000000 +0000 @@ -110,86 +110,94 @@ return rmresCheckMemInterUnmap((struct RmResource *)(((unsigned char *)pRmResource) + __nvoc_rtti_FmSessionApi_RmResource.offset), bSubdeviceHandleProvided); } +static NV_STATUS __nvoc_thunk_RsResource_fmsessionapiMapTo(struct FmSessionApi *pResource, RS_RES_MAP_TO_PARAMS *pParams) { + return resMapTo((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_FmSessionApi_RsResource.offset), pParams); +} + static NvBool __nvoc_thunk_RmResource_fmsessionapiAccessCallback(struct FmSessionApi *pResource, struct RsClient *pInvokingClient, void *pAllocParams, RsAccessRight accessRight) { return rmresAccessCallback((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_FmSessionApi_RmResource.offset), pInvokingClient, pAllocParams, accessRight); } -static NV_STATUS __nvoc_thunk_RmResource_fmsessionapiGetMemInterMapParams(struct FmSessionApi *pRmResource, RMRES_MEM_INTER_MAP_PARAMS *pParams) { - return rmresGetMemInterMapParams((struct RmResource *)(((unsigned char *)pRmResource) + __nvoc_rtti_FmSessionApi_RmResource.offset), pParams); +static void __nvoc_thunk_Notifier_fmsessionapiSetNotificationShare(struct FmSessionApi *pNotifier, struct NotifShare *pNotifShare) { + notifySetNotificationShare((struct Notifier *)(((unsigned char *)pNotifier) + __nvoc_rtti_FmSessionApi_Notifier.offset), pNotifShare); } -static NV_STATUS __nvoc_thunk_RmResource_fmsessionapiGetMemoryMappingDescriptor(struct FmSessionApi *pRmResource, struct MEMORY_DESCRIPTOR **ppMemDesc) { - return rmresGetMemoryMappingDescriptor((struct RmResource *)(((unsigned char *)pRmResource) + __nvoc_rtti_FmSessionApi_RmResource.offset), ppMemDesc); +static NvU32 __nvoc_thunk_RsResource_fmsessionapiGetRefCount(struct FmSessionApi *pResource) { + return resGetRefCount((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_FmSessionApi_RsResource.offset)); } -static void __nvoc_thunk_Notifier_fmsessionapiSetNotificationShare(struct FmSessionApi *pNotifier, struct NotifShare *pNotifShare) { - notifySetNotificationShare((struct Notifier *)(((unsigned char *)pNotifier) + __nvoc_rtti_FmSessionApi_Notifier.offset), pNotifShare); +static void __nvoc_thunk_RsResource_fmsessionapiAddAdditionalDependants(struct RsClient *pClient, struct FmSessionApi *pResource, RsResourceRef *pReference) { + resAddAdditionalDependants(pClient, (struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_FmSessionApi_RsResource.offset), pReference); } -static NV_STATUS __nvoc_thunk_RsResource_fmsessionapiControl(struct FmSessionApi *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { - return resControl((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_FmSessionApi_RsResource.offset), pCallContext, pParams); +static NV_STATUS __nvoc_thunk_RmResource_fmsessionapiControl_Prologue(struct FmSessionApi *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return rmresControl_Prologue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_FmSessionApi_RmResource.offset), pCallContext, pParams); } -static NV_STATUS __nvoc_thunk_RsResource_fmsessionapiControlFilter(struct FmSessionApi *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { - return resControlFilter((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_FmSessionApi_RsResource.offset), pCallContext, pParams); +static NV_STATUS __nvoc_thunk_RsResource_fmsessionapiUnmapFrom(struct FmSessionApi *pResource, RS_RES_UNMAP_FROM_PARAMS *pParams) { + return resUnmapFrom((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_FmSessionApi_RsResource.offset), pParams); } -static NvU32 __nvoc_thunk_RsResource_fmsessionapiGetRefCount(struct FmSessionApi *pResource) { - return resGetRefCount((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_FmSessionApi_RsResource.offset)); +static void __nvoc_thunk_RmResource_fmsessionapiControl_Epilogue(struct FmSessionApi *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + rmresControl_Epilogue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_FmSessionApi_RmResource.offset), pCallContext, pParams); } -static NV_STATUS __nvoc_thunk_Notifier_fmsessionapiUnregisterEvent(struct FmSessionApi *pNotifier, NvHandle hNotifierClient, NvHandle hNotifierResource, NvHandle hEventClient, NvHandle hEvent) { - return notifyUnregisterEvent((struct Notifier *)(((unsigned char *)pNotifier) + __nvoc_rtti_FmSessionApi_Notifier.offset), hNotifierClient, hNotifierResource, hEventClient, hEvent); +static NV_STATUS __nvoc_thunk_RsResource_fmsessionapiControlLookup(struct FmSessionApi *pResource, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams, const struct NVOC_EXPORTED_METHOD_DEF **ppEntry) { + return resControlLookup((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_FmSessionApi_RsResource.offset), pParams, ppEntry); +} + +static NV_STATUS __nvoc_thunk_RsResource_fmsessionapiControl(struct FmSessionApi *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return resControl((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_FmSessionApi_RsResource.offset), pCallContext, pParams); } static NV_STATUS __nvoc_thunk_RsResource_fmsessionapiUnmap(struct FmSessionApi *pResource, struct CALL_CONTEXT *pCallContext, RsCpuMapping *pCpuMapping) { return resUnmap((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_FmSessionApi_RsResource.offset), pCallContext, pCpuMapping); } -static NvBool __nvoc_thunk_RsResource_fmsessionapiCanCopy(struct FmSessionApi *pResource) { - return resCanCopy((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_FmSessionApi_RsResource.offset)); +static NV_STATUS __nvoc_thunk_RmResource_fmsessionapiGetMemInterMapParams(struct FmSessionApi *pRmResource, RMRES_MEM_INTER_MAP_PARAMS *pParams) { + return rmresGetMemInterMapParams((struct RmResource *)(((unsigned char *)pRmResource) + __nvoc_rtti_FmSessionApi_RmResource.offset), pParams); } -static NV_STATUS __nvoc_thunk_RmResource_fmsessionapiControl_Prologue(struct FmSessionApi *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { - return rmresControl_Prologue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_FmSessionApi_RmResource.offset), pCallContext, pParams); +static NV_STATUS __nvoc_thunk_RmResource_fmsessionapiGetMemoryMappingDescriptor(struct FmSessionApi *pRmResource, struct MEMORY_DESCRIPTOR **ppMemDesc) { + return rmresGetMemoryMappingDescriptor((struct RmResource *)(((unsigned char *)pRmResource) + __nvoc_rtti_FmSessionApi_RmResource.offset), ppMemDesc); } -static NV_STATUS __nvoc_thunk_RsResource_fmsessionapiMapTo(struct FmSessionApi *pResource, RS_RES_MAP_TO_PARAMS *pParams) { - return resMapTo((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_FmSessionApi_RsResource.offset), pParams); +static NV_STATUS __nvoc_thunk_RsResource_fmsessionapiControlFilter(struct FmSessionApi *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return resControlFilter((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_FmSessionApi_RsResource.offset), pCallContext, pParams); } -static void __nvoc_thunk_RsResource_fmsessionapiAddAdditionalDependants(struct RsClient *pClient, struct FmSessionApi *pResource, RsResourceRef *pReference) { - resAddAdditionalDependants(pClient, (struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_FmSessionApi_RsResource.offset), pReference); +static NV_STATUS __nvoc_thunk_Notifier_fmsessionapiUnregisterEvent(struct FmSessionApi *pNotifier, NvHandle hNotifierClient, NvHandle hNotifierResource, NvHandle hEventClient, NvHandle hEvent) { + return notifyUnregisterEvent((struct Notifier *)(((unsigned char *)pNotifier) + __nvoc_rtti_FmSessionApi_Notifier.offset), hNotifierClient, hNotifierResource, hEventClient, hEvent); } -static void __nvoc_thunk_RsResource_fmsessionapiPreDestruct(struct FmSessionApi *pResource) { - resPreDestruct((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_FmSessionApi_RsResource.offset)); +static NV_STATUS __nvoc_thunk_RmResource_fmsessionapiControlSerialization_Prologue(struct FmSessionApi *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return rmresControlSerialization_Prologue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_FmSessionApi_RmResource.offset), pCallContext, pParams); } -static NV_STATUS __nvoc_thunk_RsResource_fmsessionapiUnmapFrom(struct FmSessionApi *pResource, RS_RES_UNMAP_FROM_PARAMS *pParams) { - return resUnmapFrom((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_FmSessionApi_RsResource.offset), pParams); +static NvBool __nvoc_thunk_RsResource_fmsessionapiCanCopy(struct FmSessionApi *pResource) { + return resCanCopy((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_FmSessionApi_RsResource.offset)); +} + +static void __nvoc_thunk_RsResource_fmsessionapiPreDestruct(struct FmSessionApi *pResource) { + resPreDestruct((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_FmSessionApi_RsResource.offset)); } static NV_STATUS __nvoc_thunk_RsResource_fmsessionapiIsDuplicate(struct FmSessionApi *pResource, NvHandle hMemory, NvBool *pDuplicate) { return resIsDuplicate((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_FmSessionApi_RsResource.offset), hMemory, pDuplicate); } -static PEVENTNOTIFICATION *__nvoc_thunk_Notifier_fmsessionapiGetNotificationListPtr(struct FmSessionApi *pNotifier) { - return notifyGetNotificationListPtr((struct Notifier *)(((unsigned char *)pNotifier) + __nvoc_rtti_FmSessionApi_Notifier.offset)); +static void __nvoc_thunk_RmResource_fmsessionapiControlSerialization_Epilogue(struct FmSessionApi *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + rmresControlSerialization_Epilogue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_FmSessionApi_RmResource.offset), pCallContext, pParams); } -static void __nvoc_thunk_RmResource_fmsessionapiControl_Epilogue(struct FmSessionApi *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { - rmresControl_Epilogue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_FmSessionApi_RmResource.offset), pCallContext, pParams); +static PEVENTNOTIFICATION *__nvoc_thunk_Notifier_fmsessionapiGetNotificationListPtr(struct FmSessionApi *pNotifier) { + return notifyGetNotificationListPtr((struct Notifier *)(((unsigned char *)pNotifier) + __nvoc_rtti_FmSessionApi_Notifier.offset)); } static struct NotifShare *__nvoc_thunk_Notifier_fmsessionapiGetNotificationShare(struct FmSessionApi *pNotifier) { return notifyGetNotificationShare((struct Notifier *)(((unsigned char *)pNotifier) + __nvoc_rtti_FmSessionApi_Notifier.offset)); } -static NV_STATUS __nvoc_thunk_RsResource_fmsessionapiControlLookup(struct FmSessionApi *pResource, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams, const struct NVOC_EXPORTED_METHOD_DEF **ppEntry) { - return resControlLookup((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_FmSessionApi_RsResource.offset), pParams, ppEntry); -} - static NV_STATUS __nvoc_thunk_RsResource_fmsessionapiMap(struct FmSessionApi *pResource, struct CALL_CONTEXT *pCallContext, RS_CPU_MAP_PARAMS *pParams, RsCpuMapping *pCpuMapping) { return resMap((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_FmSessionApi_RsResource.offset), pCallContext, pParams, pCpuMapping); } @@ -295,46 +303,50 @@ pThis->__fmsessionapiCheckMemInterUnmap__ = &__nvoc_thunk_RmResource_fmsessionapiCheckMemInterUnmap; + pThis->__fmsessionapiMapTo__ = &__nvoc_thunk_RsResource_fmsessionapiMapTo; + pThis->__fmsessionapiAccessCallback__ = &__nvoc_thunk_RmResource_fmsessionapiAccessCallback; - pThis->__fmsessionapiGetMemInterMapParams__ = &__nvoc_thunk_RmResource_fmsessionapiGetMemInterMapParams; + pThis->__fmsessionapiSetNotificationShare__ = &__nvoc_thunk_Notifier_fmsessionapiSetNotificationShare; - pThis->__fmsessionapiGetMemoryMappingDescriptor__ = &__nvoc_thunk_RmResource_fmsessionapiGetMemoryMappingDescriptor; + pThis->__fmsessionapiGetRefCount__ = &__nvoc_thunk_RsResource_fmsessionapiGetRefCount; - pThis->__fmsessionapiSetNotificationShare__ = &__nvoc_thunk_Notifier_fmsessionapiSetNotificationShare; + pThis->__fmsessionapiAddAdditionalDependants__ = &__nvoc_thunk_RsResource_fmsessionapiAddAdditionalDependants; - pThis->__fmsessionapiControl__ = &__nvoc_thunk_RsResource_fmsessionapiControl; + pThis->__fmsessionapiControl_Prologue__ = &__nvoc_thunk_RmResource_fmsessionapiControl_Prologue; - pThis->__fmsessionapiControlFilter__ = &__nvoc_thunk_RsResource_fmsessionapiControlFilter; + pThis->__fmsessionapiUnmapFrom__ = &__nvoc_thunk_RsResource_fmsessionapiUnmapFrom; - pThis->__fmsessionapiGetRefCount__ = &__nvoc_thunk_RsResource_fmsessionapiGetRefCount; + pThis->__fmsessionapiControl_Epilogue__ = &__nvoc_thunk_RmResource_fmsessionapiControl_Epilogue; - pThis->__fmsessionapiUnregisterEvent__ = &__nvoc_thunk_Notifier_fmsessionapiUnregisterEvent; + pThis->__fmsessionapiControlLookup__ = &__nvoc_thunk_RsResource_fmsessionapiControlLookup; + + pThis->__fmsessionapiControl__ = &__nvoc_thunk_RsResource_fmsessionapiControl; pThis->__fmsessionapiUnmap__ = &__nvoc_thunk_RsResource_fmsessionapiUnmap; - pThis->__fmsessionapiCanCopy__ = &__nvoc_thunk_RsResource_fmsessionapiCanCopy; + pThis->__fmsessionapiGetMemInterMapParams__ = &__nvoc_thunk_RmResource_fmsessionapiGetMemInterMapParams; - pThis->__fmsessionapiControl_Prologue__ = &__nvoc_thunk_RmResource_fmsessionapiControl_Prologue; + pThis->__fmsessionapiGetMemoryMappingDescriptor__ = &__nvoc_thunk_RmResource_fmsessionapiGetMemoryMappingDescriptor; - pThis->__fmsessionapiMapTo__ = &__nvoc_thunk_RsResource_fmsessionapiMapTo; + pThis->__fmsessionapiControlFilter__ = &__nvoc_thunk_RsResource_fmsessionapiControlFilter; - pThis->__fmsessionapiAddAdditionalDependants__ = &__nvoc_thunk_RsResource_fmsessionapiAddAdditionalDependants; + pThis->__fmsessionapiUnregisterEvent__ = &__nvoc_thunk_Notifier_fmsessionapiUnregisterEvent; - pThis->__fmsessionapiPreDestruct__ = &__nvoc_thunk_RsResource_fmsessionapiPreDestruct; + pThis->__fmsessionapiControlSerialization_Prologue__ = &__nvoc_thunk_RmResource_fmsessionapiControlSerialization_Prologue; - pThis->__fmsessionapiUnmapFrom__ = &__nvoc_thunk_RsResource_fmsessionapiUnmapFrom; + pThis->__fmsessionapiCanCopy__ = &__nvoc_thunk_RsResource_fmsessionapiCanCopy; + + pThis->__fmsessionapiPreDestruct__ = &__nvoc_thunk_RsResource_fmsessionapiPreDestruct; pThis->__fmsessionapiIsDuplicate__ = &__nvoc_thunk_RsResource_fmsessionapiIsDuplicate; - pThis->__fmsessionapiGetNotificationListPtr__ = &__nvoc_thunk_Notifier_fmsessionapiGetNotificationListPtr; + pThis->__fmsessionapiControlSerialization_Epilogue__ = &__nvoc_thunk_RmResource_fmsessionapiControlSerialization_Epilogue; - pThis->__fmsessionapiControl_Epilogue__ = &__nvoc_thunk_RmResource_fmsessionapiControl_Epilogue; + pThis->__fmsessionapiGetNotificationListPtr__ = &__nvoc_thunk_Notifier_fmsessionapiGetNotificationListPtr; pThis->__fmsessionapiGetNotificationShare__ = &__nvoc_thunk_Notifier_fmsessionapiGetNotificationShare; - pThis->__fmsessionapiControlLookup__ = &__nvoc_thunk_RsResource_fmsessionapiControlLookup; - pThis->__fmsessionapiMap__ = &__nvoc_thunk_RsResource_fmsessionapiMap; pThis->__fmsessionapiGetOrAllocNotifShare__ = &__nvoc_thunk_Notifier_fmsessionapiGetOrAllocNotifShare; @@ -364,13 +376,16 @@ Object *pParentObj; FmSessionApi *pThis; - pThis = portMemAllocNonPaged(sizeof(FmSessionApi)); - if (pThis == NULL) return NV_ERR_NO_MEMORY; + status = __nvoc_handleObjCreateMemAlloc(createFlags, sizeof(FmSessionApi), (void**)&pThis, (void**)ppThis); + if (status != NV_OK) + return status; portMemSet(pThis, 0, sizeof(FmSessionApi)); __nvoc_initRtti(staticCast(pThis, Dynamic), &__nvoc_class_def_FmSessionApi); + pThis->__nvoc_base_RmResource.__nvoc_base_RsResource.__nvoc_base_Object.createFlags = createFlags; + if (pParent != NULL && !(createFlags & NVOC_OBJ_CREATE_FLAGS_PARENT_HALSPEC_ONLY)) { pParentObj = dynamicCast(pParent, Object); @@ -386,11 +401,17 @@ if (status != NV_OK) goto __nvoc_objCreate_FmSessionApi_cleanup; *ppThis = pThis; + return NV_OK; __nvoc_objCreate_FmSessionApi_cleanup: // do not call destructors here since the constructor already called them - portMemFree(pThis); + if (createFlags & NVOC_OBJ_CREATE_FLAGS_IN_PLACE_CONSTRUCT) + portMemSet(pThis, 0, sizeof(FmSessionApi)); + else + portMemFree(pThis); + + // coverity[leaked_storage:FALSE] return status; } diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/generated/g_fm_session_api_nvoc.h nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_fm_session_api_nvoc.h --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/generated/g_fm_session_api_nvoc.h 2023-10-25 20:26:57.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_fm_session_api_nvoc.h 2024-03-05 22:18:14.000000000 +0000 @@ -84,26 +84,28 @@ NV_STATUS (*__fmsessionapiCtrlCmdClearFmState__)(struct FmSessionApi *); NvBool (*__fmsessionapiShareCallback__)(struct FmSessionApi *, struct RsClient *, struct RsResourceRef *, RS_SHARE_POLICY *); NV_STATUS (*__fmsessionapiCheckMemInterUnmap__)(struct FmSessionApi *, NvBool); + NV_STATUS (*__fmsessionapiMapTo__)(struct FmSessionApi *, RS_RES_MAP_TO_PARAMS *); NvBool (*__fmsessionapiAccessCallback__)(struct FmSessionApi *, struct RsClient *, void *, RsAccessRight); - NV_STATUS (*__fmsessionapiGetMemInterMapParams__)(struct FmSessionApi *, RMRES_MEM_INTER_MAP_PARAMS *); - NV_STATUS (*__fmsessionapiGetMemoryMappingDescriptor__)(struct FmSessionApi *, struct MEMORY_DESCRIPTOR **); void (*__fmsessionapiSetNotificationShare__)(struct FmSessionApi *, struct NotifShare *); + NvU32 (*__fmsessionapiGetRefCount__)(struct FmSessionApi *); + void (*__fmsessionapiAddAdditionalDependants__)(struct RsClient *, struct FmSessionApi *, RsResourceRef *); + NV_STATUS (*__fmsessionapiControl_Prologue__)(struct FmSessionApi *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); + NV_STATUS (*__fmsessionapiUnmapFrom__)(struct FmSessionApi *, RS_RES_UNMAP_FROM_PARAMS *); + void (*__fmsessionapiControl_Epilogue__)(struct FmSessionApi *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); + NV_STATUS (*__fmsessionapiControlLookup__)(struct FmSessionApi *, struct RS_RES_CONTROL_PARAMS_INTERNAL *, const struct NVOC_EXPORTED_METHOD_DEF **); NV_STATUS (*__fmsessionapiControl__)(struct FmSessionApi *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); + NV_STATUS (*__fmsessionapiUnmap__)(struct FmSessionApi *, struct CALL_CONTEXT *, RsCpuMapping *); + NV_STATUS (*__fmsessionapiGetMemInterMapParams__)(struct FmSessionApi *, RMRES_MEM_INTER_MAP_PARAMS *); + NV_STATUS (*__fmsessionapiGetMemoryMappingDescriptor__)(struct FmSessionApi *, struct MEMORY_DESCRIPTOR **); NV_STATUS (*__fmsessionapiControlFilter__)(struct FmSessionApi *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); - NvU32 (*__fmsessionapiGetRefCount__)(struct FmSessionApi *); NV_STATUS (*__fmsessionapiUnregisterEvent__)(struct FmSessionApi *, NvHandle, NvHandle, NvHandle, NvHandle); - NV_STATUS (*__fmsessionapiUnmap__)(struct FmSessionApi *, struct CALL_CONTEXT *, RsCpuMapping *); + NV_STATUS (*__fmsessionapiControlSerialization_Prologue__)(struct FmSessionApi *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); NvBool (*__fmsessionapiCanCopy__)(struct FmSessionApi *); - NV_STATUS (*__fmsessionapiControl_Prologue__)(struct FmSessionApi *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); - NV_STATUS (*__fmsessionapiMapTo__)(struct FmSessionApi *, RS_RES_MAP_TO_PARAMS *); - void (*__fmsessionapiAddAdditionalDependants__)(struct RsClient *, struct FmSessionApi *, RsResourceRef *); void (*__fmsessionapiPreDestruct__)(struct FmSessionApi *); - NV_STATUS (*__fmsessionapiUnmapFrom__)(struct FmSessionApi *, RS_RES_UNMAP_FROM_PARAMS *); NV_STATUS (*__fmsessionapiIsDuplicate__)(struct FmSessionApi *, NvHandle, NvBool *); + void (*__fmsessionapiControlSerialization_Epilogue__)(struct FmSessionApi *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); PEVENTNOTIFICATION *(*__fmsessionapiGetNotificationListPtr__)(struct FmSessionApi *); - void (*__fmsessionapiControl_Epilogue__)(struct FmSessionApi *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); struct NotifShare *(*__fmsessionapiGetNotificationShare__)(struct FmSessionApi *); - NV_STATUS (*__fmsessionapiControlLookup__)(struct FmSessionApi *, struct RS_RES_CONTROL_PARAMS_INTERNAL *, const struct NVOC_EXPORTED_METHOD_DEF **); NV_STATUS (*__fmsessionapiMap__)(struct FmSessionApi *, struct CALL_CONTEXT *, RS_CPU_MAP_PARAMS *, RsCpuMapping *); NV_STATUS (*__fmsessionapiGetOrAllocNotifShare__)(struct FmSessionApi *, NvHandle, NvHandle, struct NotifShare **); NvU64 dupedCapDescriptor; @@ -141,26 +143,28 @@ #define fmsessionapiCtrlCmdClearFmState(pFmSessionApi) fmsessionapiCtrlCmdClearFmState_DISPATCH(pFmSessionApi) #define fmsessionapiShareCallback(pResource, pInvokingClient, pParentRef, pSharePolicy) fmsessionapiShareCallback_DISPATCH(pResource, pInvokingClient, pParentRef, pSharePolicy) #define fmsessionapiCheckMemInterUnmap(pRmResource, bSubdeviceHandleProvided) fmsessionapiCheckMemInterUnmap_DISPATCH(pRmResource, bSubdeviceHandleProvided) +#define fmsessionapiMapTo(pResource, pParams) fmsessionapiMapTo_DISPATCH(pResource, pParams) #define fmsessionapiAccessCallback(pResource, pInvokingClient, pAllocParams, accessRight) fmsessionapiAccessCallback_DISPATCH(pResource, pInvokingClient, pAllocParams, accessRight) -#define fmsessionapiGetMemInterMapParams(pRmResource, pParams) fmsessionapiGetMemInterMapParams_DISPATCH(pRmResource, pParams) -#define fmsessionapiGetMemoryMappingDescriptor(pRmResource, ppMemDesc) fmsessionapiGetMemoryMappingDescriptor_DISPATCH(pRmResource, ppMemDesc) #define fmsessionapiSetNotificationShare(pNotifier, pNotifShare) fmsessionapiSetNotificationShare_DISPATCH(pNotifier, pNotifShare) +#define fmsessionapiGetRefCount(pResource) fmsessionapiGetRefCount_DISPATCH(pResource) +#define fmsessionapiAddAdditionalDependants(pClient, pResource, pReference) fmsessionapiAddAdditionalDependants_DISPATCH(pClient, pResource, pReference) +#define fmsessionapiControl_Prologue(pResource, pCallContext, pParams) fmsessionapiControl_Prologue_DISPATCH(pResource, pCallContext, pParams) +#define fmsessionapiUnmapFrom(pResource, pParams) fmsessionapiUnmapFrom_DISPATCH(pResource, pParams) +#define fmsessionapiControl_Epilogue(pResource, pCallContext, pParams) fmsessionapiControl_Epilogue_DISPATCH(pResource, pCallContext, pParams) +#define fmsessionapiControlLookup(pResource, pParams, ppEntry) fmsessionapiControlLookup_DISPATCH(pResource, pParams, ppEntry) #define fmsessionapiControl(pResource, pCallContext, pParams) fmsessionapiControl_DISPATCH(pResource, pCallContext, pParams) +#define fmsessionapiUnmap(pResource, pCallContext, pCpuMapping) fmsessionapiUnmap_DISPATCH(pResource, pCallContext, pCpuMapping) +#define fmsessionapiGetMemInterMapParams(pRmResource, pParams) fmsessionapiGetMemInterMapParams_DISPATCH(pRmResource, pParams) +#define fmsessionapiGetMemoryMappingDescriptor(pRmResource, ppMemDesc) fmsessionapiGetMemoryMappingDescriptor_DISPATCH(pRmResource, ppMemDesc) #define fmsessionapiControlFilter(pResource, pCallContext, pParams) fmsessionapiControlFilter_DISPATCH(pResource, pCallContext, pParams) -#define fmsessionapiGetRefCount(pResource) fmsessionapiGetRefCount_DISPATCH(pResource) #define fmsessionapiUnregisterEvent(pNotifier, hNotifierClient, hNotifierResource, hEventClient, hEvent) fmsessionapiUnregisterEvent_DISPATCH(pNotifier, hNotifierClient, hNotifierResource, hEventClient, hEvent) -#define fmsessionapiUnmap(pResource, pCallContext, pCpuMapping) fmsessionapiUnmap_DISPATCH(pResource, pCallContext, pCpuMapping) +#define fmsessionapiControlSerialization_Prologue(pResource, pCallContext, pParams) fmsessionapiControlSerialization_Prologue_DISPATCH(pResource, pCallContext, pParams) #define fmsessionapiCanCopy(pResource) fmsessionapiCanCopy_DISPATCH(pResource) -#define fmsessionapiControl_Prologue(pResource, pCallContext, pParams) fmsessionapiControl_Prologue_DISPATCH(pResource, pCallContext, pParams) -#define fmsessionapiMapTo(pResource, pParams) fmsessionapiMapTo_DISPATCH(pResource, pParams) -#define fmsessionapiAddAdditionalDependants(pClient, pResource, pReference) fmsessionapiAddAdditionalDependants_DISPATCH(pClient, pResource, pReference) #define fmsessionapiPreDestruct(pResource) fmsessionapiPreDestruct_DISPATCH(pResource) -#define fmsessionapiUnmapFrom(pResource, pParams) fmsessionapiUnmapFrom_DISPATCH(pResource, pParams) #define fmsessionapiIsDuplicate(pResource, hMemory, pDuplicate) fmsessionapiIsDuplicate_DISPATCH(pResource, hMemory, pDuplicate) +#define fmsessionapiControlSerialization_Epilogue(pResource, pCallContext, pParams) fmsessionapiControlSerialization_Epilogue_DISPATCH(pResource, pCallContext, pParams) #define fmsessionapiGetNotificationListPtr(pNotifier) fmsessionapiGetNotificationListPtr_DISPATCH(pNotifier) -#define fmsessionapiControl_Epilogue(pResource, pCallContext, pParams) fmsessionapiControl_Epilogue_DISPATCH(pResource, pCallContext, pParams) #define fmsessionapiGetNotificationShare(pNotifier) fmsessionapiGetNotificationShare_DISPATCH(pNotifier) -#define fmsessionapiControlLookup(pResource, pParams, ppEntry) fmsessionapiControlLookup_DISPATCH(pResource, pParams, ppEntry) #define fmsessionapiMap(pResource, pCallContext, pParams, pCpuMapping) fmsessionapiMap_DISPATCH(pResource, pCallContext, pParams, pCpuMapping) #define fmsessionapiGetOrAllocNotifShare(pNotifier, hNotifierClient, hNotifierResource, ppNotifShare) fmsessionapiGetOrAllocNotifShare_DISPATCH(pNotifier, hNotifierClient, hNotifierResource, ppNotifShare) NV_STATUS fmsessionapiCtrlCmdSetFmState_IMPL(struct FmSessionApi *pFmSessionApi); @@ -183,86 +187,94 @@ return pRmResource->__fmsessionapiCheckMemInterUnmap__(pRmResource, bSubdeviceHandleProvided); } +static inline NV_STATUS fmsessionapiMapTo_DISPATCH(struct FmSessionApi *pResource, RS_RES_MAP_TO_PARAMS *pParams) { + return pResource->__fmsessionapiMapTo__(pResource, pParams); +} + static inline NvBool fmsessionapiAccessCallback_DISPATCH(struct FmSessionApi *pResource, struct RsClient *pInvokingClient, void *pAllocParams, RsAccessRight accessRight) { return pResource->__fmsessionapiAccessCallback__(pResource, pInvokingClient, pAllocParams, accessRight); } -static inline NV_STATUS fmsessionapiGetMemInterMapParams_DISPATCH(struct FmSessionApi *pRmResource, RMRES_MEM_INTER_MAP_PARAMS *pParams) { - return pRmResource->__fmsessionapiGetMemInterMapParams__(pRmResource, pParams); +static inline void fmsessionapiSetNotificationShare_DISPATCH(struct FmSessionApi *pNotifier, struct NotifShare *pNotifShare) { + pNotifier->__fmsessionapiSetNotificationShare__(pNotifier, pNotifShare); } -static inline NV_STATUS fmsessionapiGetMemoryMappingDescriptor_DISPATCH(struct FmSessionApi *pRmResource, struct MEMORY_DESCRIPTOR **ppMemDesc) { - return pRmResource->__fmsessionapiGetMemoryMappingDescriptor__(pRmResource, ppMemDesc); +static inline NvU32 fmsessionapiGetRefCount_DISPATCH(struct FmSessionApi *pResource) { + return pResource->__fmsessionapiGetRefCount__(pResource); } -static inline void fmsessionapiSetNotificationShare_DISPATCH(struct FmSessionApi *pNotifier, struct NotifShare *pNotifShare) { - pNotifier->__fmsessionapiSetNotificationShare__(pNotifier, pNotifShare); +static inline void fmsessionapiAddAdditionalDependants_DISPATCH(struct RsClient *pClient, struct FmSessionApi *pResource, RsResourceRef *pReference) { + pResource->__fmsessionapiAddAdditionalDependants__(pClient, pResource, pReference); } -static inline NV_STATUS fmsessionapiControl_DISPATCH(struct FmSessionApi *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { - return pResource->__fmsessionapiControl__(pResource, pCallContext, pParams); +static inline NV_STATUS fmsessionapiControl_Prologue_DISPATCH(struct FmSessionApi *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return pResource->__fmsessionapiControl_Prologue__(pResource, pCallContext, pParams); } -static inline NV_STATUS fmsessionapiControlFilter_DISPATCH(struct FmSessionApi *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { - return pResource->__fmsessionapiControlFilter__(pResource, pCallContext, pParams); +static inline NV_STATUS fmsessionapiUnmapFrom_DISPATCH(struct FmSessionApi *pResource, RS_RES_UNMAP_FROM_PARAMS *pParams) { + return pResource->__fmsessionapiUnmapFrom__(pResource, pParams); } -static inline NvU32 fmsessionapiGetRefCount_DISPATCH(struct FmSessionApi *pResource) { - return pResource->__fmsessionapiGetRefCount__(pResource); +static inline void fmsessionapiControl_Epilogue_DISPATCH(struct FmSessionApi *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + pResource->__fmsessionapiControl_Epilogue__(pResource, pCallContext, pParams); } -static inline NV_STATUS fmsessionapiUnregisterEvent_DISPATCH(struct FmSessionApi *pNotifier, NvHandle hNotifierClient, NvHandle hNotifierResource, NvHandle hEventClient, NvHandle hEvent) { - return pNotifier->__fmsessionapiUnregisterEvent__(pNotifier, hNotifierClient, hNotifierResource, hEventClient, hEvent); +static inline NV_STATUS fmsessionapiControlLookup_DISPATCH(struct FmSessionApi *pResource, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams, const struct NVOC_EXPORTED_METHOD_DEF **ppEntry) { + return pResource->__fmsessionapiControlLookup__(pResource, pParams, ppEntry); +} + +static inline NV_STATUS fmsessionapiControl_DISPATCH(struct FmSessionApi *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return pResource->__fmsessionapiControl__(pResource, pCallContext, pParams); } static inline NV_STATUS fmsessionapiUnmap_DISPATCH(struct FmSessionApi *pResource, struct CALL_CONTEXT *pCallContext, RsCpuMapping *pCpuMapping) { return pResource->__fmsessionapiUnmap__(pResource, pCallContext, pCpuMapping); } -static inline NvBool fmsessionapiCanCopy_DISPATCH(struct FmSessionApi *pResource) { - return pResource->__fmsessionapiCanCopy__(pResource); +static inline NV_STATUS fmsessionapiGetMemInterMapParams_DISPATCH(struct FmSessionApi *pRmResource, RMRES_MEM_INTER_MAP_PARAMS *pParams) { + return pRmResource->__fmsessionapiGetMemInterMapParams__(pRmResource, pParams); } -static inline NV_STATUS fmsessionapiControl_Prologue_DISPATCH(struct FmSessionApi *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { - return pResource->__fmsessionapiControl_Prologue__(pResource, pCallContext, pParams); +static inline NV_STATUS fmsessionapiGetMemoryMappingDescriptor_DISPATCH(struct FmSessionApi *pRmResource, struct MEMORY_DESCRIPTOR **ppMemDesc) { + return pRmResource->__fmsessionapiGetMemoryMappingDescriptor__(pRmResource, ppMemDesc); } -static inline NV_STATUS fmsessionapiMapTo_DISPATCH(struct FmSessionApi *pResource, RS_RES_MAP_TO_PARAMS *pParams) { - return pResource->__fmsessionapiMapTo__(pResource, pParams); +static inline NV_STATUS fmsessionapiControlFilter_DISPATCH(struct FmSessionApi *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return pResource->__fmsessionapiControlFilter__(pResource, pCallContext, pParams); } -static inline void fmsessionapiAddAdditionalDependants_DISPATCH(struct RsClient *pClient, struct FmSessionApi *pResource, RsResourceRef *pReference) { - pResource->__fmsessionapiAddAdditionalDependants__(pClient, pResource, pReference); +static inline NV_STATUS fmsessionapiUnregisterEvent_DISPATCH(struct FmSessionApi *pNotifier, NvHandle hNotifierClient, NvHandle hNotifierResource, NvHandle hEventClient, NvHandle hEvent) { + return pNotifier->__fmsessionapiUnregisterEvent__(pNotifier, hNotifierClient, hNotifierResource, hEventClient, hEvent); } -static inline void fmsessionapiPreDestruct_DISPATCH(struct FmSessionApi *pResource) { - pResource->__fmsessionapiPreDestruct__(pResource); +static inline NV_STATUS fmsessionapiControlSerialization_Prologue_DISPATCH(struct FmSessionApi *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return pResource->__fmsessionapiControlSerialization_Prologue__(pResource, pCallContext, pParams); } -static inline NV_STATUS fmsessionapiUnmapFrom_DISPATCH(struct FmSessionApi *pResource, RS_RES_UNMAP_FROM_PARAMS *pParams) { - return pResource->__fmsessionapiUnmapFrom__(pResource, pParams); +static inline NvBool fmsessionapiCanCopy_DISPATCH(struct FmSessionApi *pResource) { + return pResource->__fmsessionapiCanCopy__(pResource); +} + +static inline void fmsessionapiPreDestruct_DISPATCH(struct FmSessionApi *pResource) { + pResource->__fmsessionapiPreDestruct__(pResource); } static inline NV_STATUS fmsessionapiIsDuplicate_DISPATCH(struct FmSessionApi *pResource, NvHandle hMemory, NvBool *pDuplicate) { return pResource->__fmsessionapiIsDuplicate__(pResource, hMemory, pDuplicate); } -static inline PEVENTNOTIFICATION *fmsessionapiGetNotificationListPtr_DISPATCH(struct FmSessionApi *pNotifier) { - return pNotifier->__fmsessionapiGetNotificationListPtr__(pNotifier); +static inline void fmsessionapiControlSerialization_Epilogue_DISPATCH(struct FmSessionApi *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + pResource->__fmsessionapiControlSerialization_Epilogue__(pResource, pCallContext, pParams); } -static inline void fmsessionapiControl_Epilogue_DISPATCH(struct FmSessionApi *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { - pResource->__fmsessionapiControl_Epilogue__(pResource, pCallContext, pParams); +static inline PEVENTNOTIFICATION *fmsessionapiGetNotificationListPtr_DISPATCH(struct FmSessionApi *pNotifier) { + return pNotifier->__fmsessionapiGetNotificationListPtr__(pNotifier); } static inline struct NotifShare *fmsessionapiGetNotificationShare_DISPATCH(struct FmSessionApi *pNotifier) { return pNotifier->__fmsessionapiGetNotificationShare__(pNotifier); } -static inline NV_STATUS fmsessionapiControlLookup_DISPATCH(struct FmSessionApi *pResource, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams, const struct NVOC_EXPORTED_METHOD_DEF **ppEntry) { - return pResource->__fmsessionapiControlLookup__(pResource, pParams, ppEntry); -} - static inline NV_STATUS fmsessionapiMap_DISPATCH(struct FmSessionApi *pResource, struct CALL_CONTEXT *pCallContext, RS_CPU_MAP_PARAMS *pParams, RsCpuMapping *pCpuMapping) { return pResource->__fmsessionapiMap__(pResource, pCallContext, pParams, pCpuMapping); } diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/generated/g_generic_engine_nvoc.c nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_generic_engine_nvoc.c --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/generated/g_generic_engine_nvoc.c 2023-10-25 20:26:57.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_generic_engine_nvoc.c 2024-03-05 22:18:14.000000000 +0000 @@ -109,76 +109,84 @@ return gpuresShareCallback((struct GpuResource *)(((unsigned char *)pGpuResource) + __nvoc_rtti_GenericEngineApi_GpuResource.offset), pInvokingClient, pParentRef, pSharePolicy); } -static NV_STATUS __nvoc_thunk_GpuResource_genapiUnmap(struct GenericEngineApi *pGpuResource, struct CALL_CONTEXT *pCallContext, struct RsCpuMapping *pCpuMapping) { - return gpuresUnmap((struct GpuResource *)(((unsigned char *)pGpuResource) + __nvoc_rtti_GenericEngineApi_GpuResource.offset), pCallContext, pCpuMapping); +static NV_STATUS __nvoc_thunk_RmResource_genapiCheckMemInterUnmap(struct GenericEngineApi *pRmResource, NvBool bSubdeviceHandleProvided) { + return rmresCheckMemInterUnmap((struct RmResource *)(((unsigned char *)pRmResource) + __nvoc_rtti_GenericEngineApi_RmResource.offset), bSubdeviceHandleProvided); } -static NV_STATUS __nvoc_thunk_RmResource_genapiGetMemInterMapParams(struct GenericEngineApi *pRmResource, RMRES_MEM_INTER_MAP_PARAMS *pParams) { - return rmresGetMemInterMapParams((struct RmResource *)(((unsigned char *)pRmResource) + __nvoc_rtti_GenericEngineApi_RmResource.offset), pParams); +static NV_STATUS __nvoc_thunk_RsResource_genapiMapTo(struct GenericEngineApi *pResource, RS_RES_MAP_TO_PARAMS *pParams) { + return resMapTo((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_GenericEngineApi_RsResource.offset), pParams); } -static NV_STATUS __nvoc_thunk_RmResource_genapiGetMemoryMappingDescriptor(struct GenericEngineApi *pRmResource, struct MEMORY_DESCRIPTOR **ppMemDesc) { - return rmresGetMemoryMappingDescriptor((struct RmResource *)(((unsigned char *)pRmResource) + __nvoc_rtti_GenericEngineApi_RmResource.offset), ppMemDesc); +static NvU32 __nvoc_thunk_RsResource_genapiGetRefCount(struct GenericEngineApi *pResource) { + return resGetRefCount((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_GenericEngineApi_RsResource.offset)); } -static NvHandle __nvoc_thunk_GpuResource_genapiGetInternalObjectHandle(struct GenericEngineApi *pGpuResource) { - return gpuresGetInternalObjectHandle((struct GpuResource *)(((unsigned char *)pGpuResource) + __nvoc_rtti_GenericEngineApi_GpuResource.offset)); +static void __nvoc_thunk_RsResource_genapiAddAdditionalDependants(struct RsClient *pClient, struct GenericEngineApi *pResource, RsResourceRef *pReference) { + resAddAdditionalDependants(pClient, (struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_GenericEngineApi_RsResource.offset), pReference); } -static NV_STATUS __nvoc_thunk_RsResource_genapiControlFilter(struct GenericEngineApi *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { - return resControlFilter((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_GenericEngineApi_RsResource.offset), pCallContext, pParams); +static NV_STATUS __nvoc_thunk_RmResource_genapiControl_Prologue(struct GenericEngineApi *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return rmresControl_Prologue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_GenericEngineApi_RmResource.offset), pCallContext, pParams); } -static void __nvoc_thunk_RsResource_genapiAddAdditionalDependants(struct RsClient *pClient, struct GenericEngineApi *pResource, RsResourceRef *pReference) { - resAddAdditionalDependants(pClient, (struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_GenericEngineApi_RsResource.offset), pReference); +static NV_STATUS __nvoc_thunk_GpuResource_genapiGetRegBaseOffsetAndSize(struct GenericEngineApi *pGpuResource, struct OBJGPU *pGpu, NvU32 *pOffset, NvU32 *pSize) { + return gpuresGetRegBaseOffsetAndSize((struct GpuResource *)(((unsigned char *)pGpuResource) + __nvoc_rtti_GenericEngineApi_GpuResource.offset), pGpu, pOffset, pSize); } -static NvU32 __nvoc_thunk_RsResource_genapiGetRefCount(struct GenericEngineApi *pResource) { - return resGetRefCount((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_GenericEngineApi_RsResource.offset)); +static NV_STATUS __nvoc_thunk_GpuResource_genapiInternalControlForward(struct GenericEngineApi *pGpuResource, NvU32 command, void *pParams, NvU32 size) { + return gpuresInternalControlForward((struct GpuResource *)(((unsigned char *)pGpuResource) + __nvoc_rtti_GenericEngineApi_GpuResource.offset), command, pParams, size); } -static NV_STATUS __nvoc_thunk_RmResource_genapiCheckMemInterUnmap(struct GenericEngineApi *pRmResource, NvBool bSubdeviceHandleProvided) { - return rmresCheckMemInterUnmap((struct RmResource *)(((unsigned char *)pRmResource) + __nvoc_rtti_GenericEngineApi_RmResource.offset), bSubdeviceHandleProvided); +static NV_STATUS __nvoc_thunk_RsResource_genapiUnmapFrom(struct GenericEngineApi *pResource, RS_RES_UNMAP_FROM_PARAMS *pParams) { + return resUnmapFrom((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_GenericEngineApi_RsResource.offset), pParams); } -static NV_STATUS __nvoc_thunk_RsResource_genapiMapTo(struct GenericEngineApi *pResource, RS_RES_MAP_TO_PARAMS *pParams) { - return resMapTo((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_GenericEngineApi_RsResource.offset), pParams); +static void __nvoc_thunk_RmResource_genapiControl_Epilogue(struct GenericEngineApi *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + rmresControl_Epilogue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_GenericEngineApi_RmResource.offset), pCallContext, pParams); } -static NV_STATUS __nvoc_thunk_RmResource_genapiControl_Prologue(struct GenericEngineApi *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { - return rmresControl_Prologue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_GenericEngineApi_RmResource.offset), pCallContext, pParams); +static NV_STATUS __nvoc_thunk_RsResource_genapiControlLookup(struct GenericEngineApi *pResource, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams, const struct NVOC_EXPORTED_METHOD_DEF **ppEntry) { + return resControlLookup((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_GenericEngineApi_RsResource.offset), pParams, ppEntry); } -static NV_STATUS __nvoc_thunk_GpuResource_genapiGetRegBaseOffsetAndSize(struct GenericEngineApi *pGpuResource, struct OBJGPU *pGpu, NvU32 *pOffset, NvU32 *pSize) { - return gpuresGetRegBaseOffsetAndSize((struct GpuResource *)(((unsigned char *)pGpuResource) + __nvoc_rtti_GenericEngineApi_GpuResource.offset), pGpu, pOffset, pSize); +static NvHandle __nvoc_thunk_GpuResource_genapiGetInternalObjectHandle(struct GenericEngineApi *pGpuResource) { + return gpuresGetInternalObjectHandle((struct GpuResource *)(((unsigned char *)pGpuResource) + __nvoc_rtti_GenericEngineApi_GpuResource.offset)); } -static NvBool __nvoc_thunk_RsResource_genapiCanCopy(struct GenericEngineApi *pResource) { - return resCanCopy((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_GenericEngineApi_RsResource.offset)); +static NV_STATUS __nvoc_thunk_GpuResource_genapiUnmap(struct GenericEngineApi *pGpuResource, struct CALL_CONTEXT *pCallContext, struct RsCpuMapping *pCpuMapping) { + return gpuresUnmap((struct GpuResource *)(((unsigned char *)pGpuResource) + __nvoc_rtti_GenericEngineApi_GpuResource.offset), pCallContext, pCpuMapping); } -static NV_STATUS __nvoc_thunk_GpuResource_genapiInternalControlForward(struct GenericEngineApi *pGpuResource, NvU32 command, void *pParams, NvU32 size) { - return gpuresInternalControlForward((struct GpuResource *)(((unsigned char *)pGpuResource) + __nvoc_rtti_GenericEngineApi_GpuResource.offset), command, pParams, size); +static NV_STATUS __nvoc_thunk_RmResource_genapiGetMemInterMapParams(struct GenericEngineApi *pRmResource, RMRES_MEM_INTER_MAP_PARAMS *pParams) { + return rmresGetMemInterMapParams((struct RmResource *)(((unsigned char *)pRmResource) + __nvoc_rtti_GenericEngineApi_RmResource.offset), pParams); } -static void __nvoc_thunk_RsResource_genapiPreDestruct(struct GenericEngineApi *pResource) { - resPreDestruct((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_GenericEngineApi_RsResource.offset)); +static NV_STATUS __nvoc_thunk_RmResource_genapiGetMemoryMappingDescriptor(struct GenericEngineApi *pRmResource, struct MEMORY_DESCRIPTOR **ppMemDesc) { + return rmresGetMemoryMappingDescriptor((struct RmResource *)(((unsigned char *)pRmResource) + __nvoc_rtti_GenericEngineApi_RmResource.offset), ppMemDesc); } -static NV_STATUS __nvoc_thunk_RsResource_genapiUnmapFrom(struct GenericEngineApi *pResource, RS_RES_UNMAP_FROM_PARAMS *pParams) { - return resUnmapFrom((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_GenericEngineApi_RsResource.offset), pParams); +static NV_STATUS __nvoc_thunk_RsResource_genapiControlFilter(struct GenericEngineApi *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return resControlFilter((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_GenericEngineApi_RsResource.offset), pCallContext, pParams); } -static NV_STATUS __nvoc_thunk_RsResource_genapiIsDuplicate(struct GenericEngineApi *pResource, NvHandle hMemory, NvBool *pDuplicate) { - return resIsDuplicate((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_GenericEngineApi_RsResource.offset), hMemory, pDuplicate); +static NV_STATUS __nvoc_thunk_RmResource_genapiControlSerialization_Prologue(struct GenericEngineApi *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return rmresControlSerialization_Prologue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_GenericEngineApi_RmResource.offset), pCallContext, pParams); } -static void __nvoc_thunk_RmResource_genapiControl_Epilogue(struct GenericEngineApi *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { - rmresControl_Epilogue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_GenericEngineApi_RmResource.offset), pCallContext, pParams); +static NvBool __nvoc_thunk_RsResource_genapiCanCopy(struct GenericEngineApi *pResource) { + return resCanCopy((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_GenericEngineApi_RsResource.offset)); } -static NV_STATUS __nvoc_thunk_RsResource_genapiControlLookup(struct GenericEngineApi *pResource, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams, const struct NVOC_EXPORTED_METHOD_DEF **ppEntry) { - return resControlLookup((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_GenericEngineApi_RsResource.offset), pParams, ppEntry); +static void __nvoc_thunk_RsResource_genapiPreDestruct(struct GenericEngineApi *pResource) { + resPreDestruct((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_GenericEngineApi_RsResource.offset)); +} + +static NV_STATUS __nvoc_thunk_RsResource_genapiIsDuplicate(struct GenericEngineApi *pResource, NvHandle hMemory, NvBool *pDuplicate) { + return resIsDuplicate((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_GenericEngineApi_RsResource.offset), hMemory, pDuplicate); +} + +static void __nvoc_thunk_RmResource_genapiControlSerialization_Epilogue(struct GenericEngineApi *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + rmresControlSerialization_Epilogue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_GenericEngineApi_RmResource.offset), pCallContext, pParams); } static NvBool __nvoc_thunk_RmResource_genapiAccessCallback(struct GenericEngineApi *pResource, struct RsClient *pInvokingClient, void *pAllocParams, RsAccessRight accessRight) { @@ -221,12 +229,27 @@ /*func=*/ "genapiCtrlCmdMasterGetVirtualFunctionErrorContIntrMask" #endif }, + { /* [2] */ +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x250u) + /*pFunc=*/ (void (*)(void)) NULL, +#else + /*pFunc=*/ (void (*)(void)) genapiCtrlCmdBBXGetLastFlushTime_IMPL, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x250u) + /*flags=*/ 0x250u, + /*accessRight=*/0x0u, + /*methodId=*/ 0x90e70113u, + /*paramSize=*/ sizeof(NV90E7_CTRL_BBX_GET_LAST_FLUSH_TIME_PARAMS), + /*pClassInfo=*/ &(__nvoc_class_def_GenericEngineApi.classInfo), +#if NV_PRINTF_STRINGS_ALLOWED + /*func=*/ "genapiCtrlCmdBBXGetLastFlushTime" +#endif + }, }; const struct NVOC_EXPORT_INFO __nvoc_export_info_GenericEngineApi = { - /*numEntries=*/ 2, + /*numEntries=*/ 3, /*pExportEntries=*/ __nvoc_exported_method_def_GenericEngineApi }; @@ -277,6 +300,10 @@ pThis->__genapiCtrlCmdMasterGetVirtualFunctionErrorContIntrMask__ = &genapiCtrlCmdMasterGetVirtualFunctionErrorContIntrMask_IMPL; #endif +#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x250u) + pThis->__genapiCtrlCmdBBXGetLastFlushTime__ = &genapiCtrlCmdBBXGetLastFlushTime_IMPL; +#endif + pThis->__nvoc_base_GpuResource.__gpuresMap__ = &__nvoc_thunk_GenericEngineApi_gpuresMap; pThis->__nvoc_base_GpuResource.__gpuresGetMapAddrSpace__ = &__nvoc_thunk_GenericEngineApi_gpuresGetMapAddrSpace; @@ -285,41 +312,45 @@ pThis->__genapiShareCallback__ = &__nvoc_thunk_GpuResource_genapiShareCallback; - pThis->__genapiUnmap__ = &__nvoc_thunk_GpuResource_genapiUnmap; + pThis->__genapiCheckMemInterUnmap__ = &__nvoc_thunk_RmResource_genapiCheckMemInterUnmap; - pThis->__genapiGetMemInterMapParams__ = &__nvoc_thunk_RmResource_genapiGetMemInterMapParams; + pThis->__genapiMapTo__ = &__nvoc_thunk_RsResource_genapiMapTo; - pThis->__genapiGetMemoryMappingDescriptor__ = &__nvoc_thunk_RmResource_genapiGetMemoryMappingDescriptor; + pThis->__genapiGetRefCount__ = &__nvoc_thunk_RsResource_genapiGetRefCount; - pThis->__genapiGetInternalObjectHandle__ = &__nvoc_thunk_GpuResource_genapiGetInternalObjectHandle; + pThis->__genapiAddAdditionalDependants__ = &__nvoc_thunk_RsResource_genapiAddAdditionalDependants; - pThis->__genapiControlFilter__ = &__nvoc_thunk_RsResource_genapiControlFilter; + pThis->__genapiControl_Prologue__ = &__nvoc_thunk_RmResource_genapiControl_Prologue; - pThis->__genapiAddAdditionalDependants__ = &__nvoc_thunk_RsResource_genapiAddAdditionalDependants; + pThis->__genapiGetRegBaseOffsetAndSize__ = &__nvoc_thunk_GpuResource_genapiGetRegBaseOffsetAndSize; - pThis->__genapiGetRefCount__ = &__nvoc_thunk_RsResource_genapiGetRefCount; + pThis->__genapiInternalControlForward__ = &__nvoc_thunk_GpuResource_genapiInternalControlForward; - pThis->__genapiCheckMemInterUnmap__ = &__nvoc_thunk_RmResource_genapiCheckMemInterUnmap; + pThis->__genapiUnmapFrom__ = &__nvoc_thunk_RsResource_genapiUnmapFrom; - pThis->__genapiMapTo__ = &__nvoc_thunk_RsResource_genapiMapTo; + pThis->__genapiControl_Epilogue__ = &__nvoc_thunk_RmResource_genapiControl_Epilogue; - pThis->__genapiControl_Prologue__ = &__nvoc_thunk_RmResource_genapiControl_Prologue; + pThis->__genapiControlLookup__ = &__nvoc_thunk_RsResource_genapiControlLookup; - pThis->__genapiGetRegBaseOffsetAndSize__ = &__nvoc_thunk_GpuResource_genapiGetRegBaseOffsetAndSize; + pThis->__genapiGetInternalObjectHandle__ = &__nvoc_thunk_GpuResource_genapiGetInternalObjectHandle; - pThis->__genapiCanCopy__ = &__nvoc_thunk_RsResource_genapiCanCopy; + pThis->__genapiUnmap__ = &__nvoc_thunk_GpuResource_genapiUnmap; - pThis->__genapiInternalControlForward__ = &__nvoc_thunk_GpuResource_genapiInternalControlForward; + pThis->__genapiGetMemInterMapParams__ = &__nvoc_thunk_RmResource_genapiGetMemInterMapParams; - pThis->__genapiPreDestruct__ = &__nvoc_thunk_RsResource_genapiPreDestruct; + pThis->__genapiGetMemoryMappingDescriptor__ = &__nvoc_thunk_RmResource_genapiGetMemoryMappingDescriptor; - pThis->__genapiUnmapFrom__ = &__nvoc_thunk_RsResource_genapiUnmapFrom; + pThis->__genapiControlFilter__ = &__nvoc_thunk_RsResource_genapiControlFilter; - pThis->__genapiIsDuplicate__ = &__nvoc_thunk_RsResource_genapiIsDuplicate; + pThis->__genapiControlSerialization_Prologue__ = &__nvoc_thunk_RmResource_genapiControlSerialization_Prologue; - pThis->__genapiControl_Epilogue__ = &__nvoc_thunk_RmResource_genapiControl_Epilogue; + pThis->__genapiCanCopy__ = &__nvoc_thunk_RsResource_genapiCanCopy; - pThis->__genapiControlLookup__ = &__nvoc_thunk_RsResource_genapiControlLookup; + pThis->__genapiPreDestruct__ = &__nvoc_thunk_RsResource_genapiPreDestruct; + + pThis->__genapiIsDuplicate__ = &__nvoc_thunk_RsResource_genapiIsDuplicate; + + pThis->__genapiControlSerialization_Epilogue__ = &__nvoc_thunk_RmResource_genapiControlSerialization_Epilogue; pThis->__genapiAccessCallback__ = &__nvoc_thunk_RmResource_genapiAccessCallback; } @@ -345,13 +376,16 @@ Object *pParentObj; GenericEngineApi *pThis; - pThis = portMemAllocNonPaged(sizeof(GenericEngineApi)); - if (pThis == NULL) return NV_ERR_NO_MEMORY; + status = __nvoc_handleObjCreateMemAlloc(createFlags, sizeof(GenericEngineApi), (void**)&pThis, (void**)ppThis); + if (status != NV_OK) + return status; portMemSet(pThis, 0, sizeof(GenericEngineApi)); __nvoc_initRtti(staticCast(pThis, Dynamic), &__nvoc_class_def_GenericEngineApi); + pThis->__nvoc_base_GpuResource.__nvoc_base_RmResource.__nvoc_base_RsResource.__nvoc_base_Object.createFlags = createFlags; + if (pParent != NULL && !(createFlags & NVOC_OBJ_CREATE_FLAGS_PARENT_HALSPEC_ONLY)) { pParentObj = dynamicCast(pParent, Object); @@ -367,11 +401,17 @@ if (status != NV_OK) goto __nvoc_objCreate_GenericEngineApi_cleanup; *ppThis = pThis; + return NV_OK; __nvoc_objCreate_GenericEngineApi_cleanup: // do not call destructors here since the constructor already called them - portMemFree(pThis); + if (createFlags & NVOC_OBJ_CREATE_FLAGS_IN_PLACE_CONSTRUCT) + portMemSet(pThis, 0, sizeof(GenericEngineApi)); + else + portMemFree(pThis); + + // coverity[leaked_storage:FALSE] return status; } diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/generated/g_generic_engine_nvoc.h nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_generic_engine_nvoc.h --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/generated/g_generic_engine_nvoc.h 2023-10-25 20:26:57.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_generic_engine_nvoc.h 2024-03-05 22:18:14.000000000 +0000 @@ -7,7 +7,7 @@ #endif /* - * SPDX-FileCopyrightText: Copyright (c) 2016-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2016-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -35,6 +35,7 @@ #include "gpu/gpu_resource.h" #include "ctrl/ctrl90e6.h" +#include "ctrl/ctrl90e7.h" #include "rmapi/resource.h" // for macro RMCTRL_EXPORT etc. /*! @@ -61,25 +62,28 @@ NV_STATUS (*__genapiControl__)(struct GenericEngineApi *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); NV_STATUS (*__genapiCtrlCmdMasterGetErrorIntrOffsetMask__)(struct GenericEngineApi *, NV90E6_CTRL_MASTER_GET_ERROR_INTR_OFFSET_MASK_PARAMS *); NV_STATUS (*__genapiCtrlCmdMasterGetVirtualFunctionErrorContIntrMask__)(struct GenericEngineApi *, NV90E6_CTRL_MASTER_GET_VIRTUAL_FUNCTION_ERROR_CONT_INTR_MASK_PARAMS *); + NV_STATUS (*__genapiCtrlCmdBBXGetLastFlushTime__)(struct GenericEngineApi *, NV90E7_CTRL_BBX_GET_LAST_FLUSH_TIME_PARAMS *); NvBool (*__genapiShareCallback__)(struct GenericEngineApi *, struct RsClient *, struct RsResourceRef *, RS_SHARE_POLICY *); - NV_STATUS (*__genapiUnmap__)(struct GenericEngineApi *, struct CALL_CONTEXT *, struct RsCpuMapping *); - NV_STATUS (*__genapiGetMemInterMapParams__)(struct GenericEngineApi *, RMRES_MEM_INTER_MAP_PARAMS *); - NV_STATUS (*__genapiGetMemoryMappingDescriptor__)(struct GenericEngineApi *, struct MEMORY_DESCRIPTOR **); - NvHandle (*__genapiGetInternalObjectHandle__)(struct GenericEngineApi *); - NV_STATUS (*__genapiControlFilter__)(struct GenericEngineApi *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); - void (*__genapiAddAdditionalDependants__)(struct RsClient *, struct GenericEngineApi *, RsResourceRef *); - NvU32 (*__genapiGetRefCount__)(struct GenericEngineApi *); NV_STATUS (*__genapiCheckMemInterUnmap__)(struct GenericEngineApi *, NvBool); NV_STATUS (*__genapiMapTo__)(struct GenericEngineApi *, RS_RES_MAP_TO_PARAMS *); + NvU32 (*__genapiGetRefCount__)(struct GenericEngineApi *); + void (*__genapiAddAdditionalDependants__)(struct RsClient *, struct GenericEngineApi *, RsResourceRef *); NV_STATUS (*__genapiControl_Prologue__)(struct GenericEngineApi *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); NV_STATUS (*__genapiGetRegBaseOffsetAndSize__)(struct GenericEngineApi *, struct OBJGPU *, NvU32 *, NvU32 *); - NvBool (*__genapiCanCopy__)(struct GenericEngineApi *); NV_STATUS (*__genapiInternalControlForward__)(struct GenericEngineApi *, NvU32, void *, NvU32); - void (*__genapiPreDestruct__)(struct GenericEngineApi *); NV_STATUS (*__genapiUnmapFrom__)(struct GenericEngineApi *, RS_RES_UNMAP_FROM_PARAMS *); - NV_STATUS (*__genapiIsDuplicate__)(struct GenericEngineApi *, NvHandle, NvBool *); void (*__genapiControl_Epilogue__)(struct GenericEngineApi *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); NV_STATUS (*__genapiControlLookup__)(struct GenericEngineApi *, struct RS_RES_CONTROL_PARAMS_INTERNAL *, const struct NVOC_EXPORTED_METHOD_DEF **); + NvHandle (*__genapiGetInternalObjectHandle__)(struct GenericEngineApi *); + NV_STATUS (*__genapiUnmap__)(struct GenericEngineApi *, struct CALL_CONTEXT *, struct RsCpuMapping *); + NV_STATUS (*__genapiGetMemInterMapParams__)(struct GenericEngineApi *, RMRES_MEM_INTER_MAP_PARAMS *); + NV_STATUS (*__genapiGetMemoryMappingDescriptor__)(struct GenericEngineApi *, struct MEMORY_DESCRIPTOR **); + NV_STATUS (*__genapiControlFilter__)(struct GenericEngineApi *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); + NV_STATUS (*__genapiControlSerialization_Prologue__)(struct GenericEngineApi *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); + NvBool (*__genapiCanCopy__)(struct GenericEngineApi *); + void (*__genapiPreDestruct__)(struct GenericEngineApi *); + NV_STATUS (*__genapiIsDuplicate__)(struct GenericEngineApi *, NvHandle, NvBool *); + void (*__genapiControlSerialization_Epilogue__)(struct GenericEngineApi *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); NvBool (*__genapiAccessCallback__)(struct GenericEngineApi *, struct RsClient *, void *, RsAccessRight); }; @@ -116,25 +120,28 @@ #define genapiControl(pGenericEngineApi, pCallContext, pParams) genapiControl_DISPATCH(pGenericEngineApi, pCallContext, pParams) #define genapiCtrlCmdMasterGetErrorIntrOffsetMask(pGenericEngineApi, pParams) genapiCtrlCmdMasterGetErrorIntrOffsetMask_DISPATCH(pGenericEngineApi, pParams) #define genapiCtrlCmdMasterGetVirtualFunctionErrorContIntrMask(pGenericEngineApi, pParams) genapiCtrlCmdMasterGetVirtualFunctionErrorContIntrMask_DISPATCH(pGenericEngineApi, pParams) +#define genapiCtrlCmdBBXGetLastFlushTime(pGenericEngineApi, pParams) genapiCtrlCmdBBXGetLastFlushTime_DISPATCH(pGenericEngineApi, pParams) #define genapiShareCallback(pGpuResource, pInvokingClient, pParentRef, pSharePolicy) genapiShareCallback_DISPATCH(pGpuResource, pInvokingClient, pParentRef, pSharePolicy) -#define genapiUnmap(pGpuResource, pCallContext, pCpuMapping) genapiUnmap_DISPATCH(pGpuResource, pCallContext, pCpuMapping) -#define genapiGetMemInterMapParams(pRmResource, pParams) genapiGetMemInterMapParams_DISPATCH(pRmResource, pParams) -#define genapiGetMemoryMappingDescriptor(pRmResource, ppMemDesc) genapiGetMemoryMappingDescriptor_DISPATCH(pRmResource, ppMemDesc) -#define genapiGetInternalObjectHandle(pGpuResource) genapiGetInternalObjectHandle_DISPATCH(pGpuResource) -#define genapiControlFilter(pResource, pCallContext, pParams) genapiControlFilter_DISPATCH(pResource, pCallContext, pParams) -#define genapiAddAdditionalDependants(pClient, pResource, pReference) genapiAddAdditionalDependants_DISPATCH(pClient, pResource, pReference) -#define genapiGetRefCount(pResource) genapiGetRefCount_DISPATCH(pResource) #define genapiCheckMemInterUnmap(pRmResource, bSubdeviceHandleProvided) genapiCheckMemInterUnmap_DISPATCH(pRmResource, bSubdeviceHandleProvided) #define genapiMapTo(pResource, pParams) genapiMapTo_DISPATCH(pResource, pParams) +#define genapiGetRefCount(pResource) genapiGetRefCount_DISPATCH(pResource) +#define genapiAddAdditionalDependants(pClient, pResource, pReference) genapiAddAdditionalDependants_DISPATCH(pClient, pResource, pReference) #define genapiControl_Prologue(pResource, pCallContext, pParams) genapiControl_Prologue_DISPATCH(pResource, pCallContext, pParams) #define genapiGetRegBaseOffsetAndSize(pGpuResource, pGpu, pOffset, pSize) genapiGetRegBaseOffsetAndSize_DISPATCH(pGpuResource, pGpu, pOffset, pSize) -#define genapiCanCopy(pResource) genapiCanCopy_DISPATCH(pResource) #define genapiInternalControlForward(pGpuResource, command, pParams, size) genapiInternalControlForward_DISPATCH(pGpuResource, command, pParams, size) -#define genapiPreDestruct(pResource) genapiPreDestruct_DISPATCH(pResource) #define genapiUnmapFrom(pResource, pParams) genapiUnmapFrom_DISPATCH(pResource, pParams) -#define genapiIsDuplicate(pResource, hMemory, pDuplicate) genapiIsDuplicate_DISPATCH(pResource, hMemory, pDuplicate) #define genapiControl_Epilogue(pResource, pCallContext, pParams) genapiControl_Epilogue_DISPATCH(pResource, pCallContext, pParams) #define genapiControlLookup(pResource, pParams, ppEntry) genapiControlLookup_DISPATCH(pResource, pParams, ppEntry) +#define genapiGetInternalObjectHandle(pGpuResource) genapiGetInternalObjectHandle_DISPATCH(pGpuResource) +#define genapiUnmap(pGpuResource, pCallContext, pCpuMapping) genapiUnmap_DISPATCH(pGpuResource, pCallContext, pCpuMapping) +#define genapiGetMemInterMapParams(pRmResource, pParams) genapiGetMemInterMapParams_DISPATCH(pRmResource, pParams) +#define genapiGetMemoryMappingDescriptor(pRmResource, ppMemDesc) genapiGetMemoryMappingDescriptor_DISPATCH(pRmResource, ppMemDesc) +#define genapiControlFilter(pResource, pCallContext, pParams) genapiControlFilter_DISPATCH(pResource, pCallContext, pParams) +#define genapiControlSerialization_Prologue(pResource, pCallContext, pParams) genapiControlSerialization_Prologue_DISPATCH(pResource, pCallContext, pParams) +#define genapiCanCopy(pResource) genapiCanCopy_DISPATCH(pResource) +#define genapiPreDestruct(pResource) genapiPreDestruct_DISPATCH(pResource) +#define genapiIsDuplicate(pResource, hMemory, pDuplicate) genapiIsDuplicate_DISPATCH(pResource, hMemory, pDuplicate) +#define genapiControlSerialization_Epilogue(pResource, pCallContext, pParams) genapiControlSerialization_Epilogue_DISPATCH(pResource, pCallContext, pParams) #define genapiAccessCallback(pResource, pInvokingClient, pAllocParams, accessRight) genapiAccessCallback_DISPATCH(pResource, pInvokingClient, pAllocParams, accessRight) NV_STATUS genapiMap_IMPL(struct GenericEngineApi *pGenericEngineApi, struct CALL_CONTEXT *pCallContext, struct RS_CPU_MAP_PARAMS *pParams, struct RsCpuMapping *pCpuMapping); @@ -166,80 +173,94 @@ return pGenericEngineApi->__genapiCtrlCmdMasterGetVirtualFunctionErrorContIntrMask__(pGenericEngineApi, pParams); } +NV_STATUS genapiCtrlCmdBBXGetLastFlushTime_IMPL(struct GenericEngineApi *pGenericEngineApi, NV90E7_CTRL_BBX_GET_LAST_FLUSH_TIME_PARAMS *pParams); + +static inline NV_STATUS genapiCtrlCmdBBXGetLastFlushTime_DISPATCH(struct GenericEngineApi *pGenericEngineApi, NV90E7_CTRL_BBX_GET_LAST_FLUSH_TIME_PARAMS *pParams) { + return pGenericEngineApi->__genapiCtrlCmdBBXGetLastFlushTime__(pGenericEngineApi, pParams); +} + static inline NvBool genapiShareCallback_DISPATCH(struct GenericEngineApi *pGpuResource, struct RsClient *pInvokingClient, struct RsResourceRef *pParentRef, RS_SHARE_POLICY *pSharePolicy) { return pGpuResource->__genapiShareCallback__(pGpuResource, pInvokingClient, pParentRef, pSharePolicy); } -static inline NV_STATUS genapiUnmap_DISPATCH(struct GenericEngineApi *pGpuResource, struct CALL_CONTEXT *pCallContext, struct RsCpuMapping *pCpuMapping) { - return pGpuResource->__genapiUnmap__(pGpuResource, pCallContext, pCpuMapping); +static inline NV_STATUS genapiCheckMemInterUnmap_DISPATCH(struct GenericEngineApi *pRmResource, NvBool bSubdeviceHandleProvided) { + return pRmResource->__genapiCheckMemInterUnmap__(pRmResource, bSubdeviceHandleProvided); } -static inline NV_STATUS genapiGetMemInterMapParams_DISPATCH(struct GenericEngineApi *pRmResource, RMRES_MEM_INTER_MAP_PARAMS *pParams) { - return pRmResource->__genapiGetMemInterMapParams__(pRmResource, pParams); +static inline NV_STATUS genapiMapTo_DISPATCH(struct GenericEngineApi *pResource, RS_RES_MAP_TO_PARAMS *pParams) { + return pResource->__genapiMapTo__(pResource, pParams); } -static inline NV_STATUS genapiGetMemoryMappingDescriptor_DISPATCH(struct GenericEngineApi *pRmResource, struct MEMORY_DESCRIPTOR **ppMemDesc) { - return pRmResource->__genapiGetMemoryMappingDescriptor__(pRmResource, ppMemDesc); +static inline NvU32 genapiGetRefCount_DISPATCH(struct GenericEngineApi *pResource) { + return pResource->__genapiGetRefCount__(pResource); } -static inline NvHandle genapiGetInternalObjectHandle_DISPATCH(struct GenericEngineApi *pGpuResource) { - return pGpuResource->__genapiGetInternalObjectHandle__(pGpuResource); +static inline void genapiAddAdditionalDependants_DISPATCH(struct RsClient *pClient, struct GenericEngineApi *pResource, RsResourceRef *pReference) { + pResource->__genapiAddAdditionalDependants__(pClient, pResource, pReference); } -static inline NV_STATUS genapiControlFilter_DISPATCH(struct GenericEngineApi *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { - return pResource->__genapiControlFilter__(pResource, pCallContext, pParams); +static inline NV_STATUS genapiControl_Prologue_DISPATCH(struct GenericEngineApi *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return pResource->__genapiControl_Prologue__(pResource, pCallContext, pParams); } -static inline void genapiAddAdditionalDependants_DISPATCH(struct RsClient *pClient, struct GenericEngineApi *pResource, RsResourceRef *pReference) { - pResource->__genapiAddAdditionalDependants__(pClient, pResource, pReference); +static inline NV_STATUS genapiGetRegBaseOffsetAndSize_DISPATCH(struct GenericEngineApi *pGpuResource, struct OBJGPU *pGpu, NvU32 *pOffset, NvU32 *pSize) { + return pGpuResource->__genapiGetRegBaseOffsetAndSize__(pGpuResource, pGpu, pOffset, pSize); } -static inline NvU32 genapiGetRefCount_DISPATCH(struct GenericEngineApi *pResource) { - return pResource->__genapiGetRefCount__(pResource); +static inline NV_STATUS genapiInternalControlForward_DISPATCH(struct GenericEngineApi *pGpuResource, NvU32 command, void *pParams, NvU32 size) { + return pGpuResource->__genapiInternalControlForward__(pGpuResource, command, pParams, size); } -static inline NV_STATUS genapiCheckMemInterUnmap_DISPATCH(struct GenericEngineApi *pRmResource, NvBool bSubdeviceHandleProvided) { - return pRmResource->__genapiCheckMemInterUnmap__(pRmResource, bSubdeviceHandleProvided); +static inline NV_STATUS genapiUnmapFrom_DISPATCH(struct GenericEngineApi *pResource, RS_RES_UNMAP_FROM_PARAMS *pParams) { + return pResource->__genapiUnmapFrom__(pResource, pParams); } -static inline NV_STATUS genapiMapTo_DISPATCH(struct GenericEngineApi *pResource, RS_RES_MAP_TO_PARAMS *pParams) { - return pResource->__genapiMapTo__(pResource, pParams); +static inline void genapiControl_Epilogue_DISPATCH(struct GenericEngineApi *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + pResource->__genapiControl_Epilogue__(pResource, pCallContext, pParams); } -static inline NV_STATUS genapiControl_Prologue_DISPATCH(struct GenericEngineApi *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { - return pResource->__genapiControl_Prologue__(pResource, pCallContext, pParams); +static inline NV_STATUS genapiControlLookup_DISPATCH(struct GenericEngineApi *pResource, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams, const struct NVOC_EXPORTED_METHOD_DEF **ppEntry) { + return pResource->__genapiControlLookup__(pResource, pParams, ppEntry); } -static inline NV_STATUS genapiGetRegBaseOffsetAndSize_DISPATCH(struct GenericEngineApi *pGpuResource, struct OBJGPU *pGpu, NvU32 *pOffset, NvU32 *pSize) { - return pGpuResource->__genapiGetRegBaseOffsetAndSize__(pGpuResource, pGpu, pOffset, pSize); +static inline NvHandle genapiGetInternalObjectHandle_DISPATCH(struct GenericEngineApi *pGpuResource) { + return pGpuResource->__genapiGetInternalObjectHandle__(pGpuResource); } -static inline NvBool genapiCanCopy_DISPATCH(struct GenericEngineApi *pResource) { - return pResource->__genapiCanCopy__(pResource); +static inline NV_STATUS genapiUnmap_DISPATCH(struct GenericEngineApi *pGpuResource, struct CALL_CONTEXT *pCallContext, struct RsCpuMapping *pCpuMapping) { + return pGpuResource->__genapiUnmap__(pGpuResource, pCallContext, pCpuMapping); } -static inline NV_STATUS genapiInternalControlForward_DISPATCH(struct GenericEngineApi *pGpuResource, NvU32 command, void *pParams, NvU32 size) { - return pGpuResource->__genapiInternalControlForward__(pGpuResource, command, pParams, size); +static inline NV_STATUS genapiGetMemInterMapParams_DISPATCH(struct GenericEngineApi *pRmResource, RMRES_MEM_INTER_MAP_PARAMS *pParams) { + return pRmResource->__genapiGetMemInterMapParams__(pRmResource, pParams); } -static inline void genapiPreDestruct_DISPATCH(struct GenericEngineApi *pResource) { - pResource->__genapiPreDestruct__(pResource); +static inline NV_STATUS genapiGetMemoryMappingDescriptor_DISPATCH(struct GenericEngineApi *pRmResource, struct MEMORY_DESCRIPTOR **ppMemDesc) { + return pRmResource->__genapiGetMemoryMappingDescriptor__(pRmResource, ppMemDesc); } -static inline NV_STATUS genapiUnmapFrom_DISPATCH(struct GenericEngineApi *pResource, RS_RES_UNMAP_FROM_PARAMS *pParams) { - return pResource->__genapiUnmapFrom__(pResource, pParams); +static inline NV_STATUS genapiControlFilter_DISPATCH(struct GenericEngineApi *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return pResource->__genapiControlFilter__(pResource, pCallContext, pParams); } -static inline NV_STATUS genapiIsDuplicate_DISPATCH(struct GenericEngineApi *pResource, NvHandle hMemory, NvBool *pDuplicate) { - return pResource->__genapiIsDuplicate__(pResource, hMemory, pDuplicate); +static inline NV_STATUS genapiControlSerialization_Prologue_DISPATCH(struct GenericEngineApi *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return pResource->__genapiControlSerialization_Prologue__(pResource, pCallContext, pParams); } -static inline void genapiControl_Epilogue_DISPATCH(struct GenericEngineApi *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { - pResource->__genapiControl_Epilogue__(pResource, pCallContext, pParams); +static inline NvBool genapiCanCopy_DISPATCH(struct GenericEngineApi *pResource) { + return pResource->__genapiCanCopy__(pResource); } -static inline NV_STATUS genapiControlLookup_DISPATCH(struct GenericEngineApi *pResource, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams, const struct NVOC_EXPORTED_METHOD_DEF **ppEntry) { - return pResource->__genapiControlLookup__(pResource, pParams, ppEntry); +static inline void genapiPreDestruct_DISPATCH(struct GenericEngineApi *pResource) { + pResource->__genapiPreDestruct__(pResource); +} + +static inline NV_STATUS genapiIsDuplicate_DISPATCH(struct GenericEngineApi *pResource, NvHandle hMemory, NvBool *pDuplicate) { + return pResource->__genapiIsDuplicate__(pResource, hMemory, pDuplicate); +} + +static inline void genapiControlSerialization_Epilogue_DISPATCH(struct GenericEngineApi *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + pResource->__genapiControlSerialization_Epilogue__(pResource, pCallContext, pParams); } static inline NvBool genapiAccessCallback_DISPATCH(struct GenericEngineApi *pResource, struct RsClient *pInvokingClient, void *pAllocParams, RsAccessRight accessRight) { diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/generated/g_gpu_access_nvoc.c nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_gpu_access_nvoc.c --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/generated/g_gpu_access_nvoc.c 1970-01-01 00:00:00.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_gpu_access_nvoc.c 2024-03-05 22:18:14.000000000 +0000 @@ -0,0 +1,491 @@ +#define NVOC_GPU_ACCESS_H_PRIVATE_ACCESS_ALLOWED +#include "nvoc/runtime.h" +#include "nvoc/rtti.h" +#include "nvtypes.h" +#include "nvport/nvport.h" +#include "nvport/inline/util_valist.h" +#include "utils/nvassert.h" +#include "g_gpu_access_nvoc.h" + +#ifdef DEBUG +char __nvoc_class_id_uniqueness_check_0x40549c = 1; +#endif + +extern const struct NVOC_CLASS_DEF __nvoc_class_def_IoAperture; + +extern const struct NVOC_CLASS_DEF __nvoc_class_def_Object; + +extern const struct NVOC_CLASS_DEF __nvoc_class_def_RegisterAperture; + +void __nvoc_init_IoAperture(IoAperture*); +void __nvoc_init_funcTable_IoAperture(IoAperture*); +NV_STATUS __nvoc_ctor_IoAperture(IoAperture*, struct IoAperture * arg_pParentAperture, OBJGPU * arg_pGpu, NvU32 arg_deviceIndex, NvU32 arg_deviceInstance, DEVICE_MAPPING * arg_pMapping, NvU32 arg_mappingStartAddr, NvU32 arg_offset, NvU32 arg_length); +void __nvoc_init_dataField_IoAperture(IoAperture*); +void __nvoc_dtor_IoAperture(IoAperture*); +extern const struct NVOC_EXPORT_INFO __nvoc_export_info_IoAperture; + +static const struct NVOC_RTTI __nvoc_rtti_IoAperture_IoAperture = { + /*pClassDef=*/ &__nvoc_class_def_IoAperture, + /*dtor=*/ (NVOC_DYNAMIC_DTOR) &__nvoc_dtor_IoAperture, + /*offset=*/ 0, +}; + +static const struct NVOC_RTTI __nvoc_rtti_IoAperture_Object = { + /*pClassDef=*/ &__nvoc_class_def_Object, + /*dtor=*/ &__nvoc_destructFromBase, + /*offset=*/ NV_OFFSETOF(IoAperture, __nvoc_base_Object), +}; + +static const struct NVOC_RTTI __nvoc_rtti_IoAperture_RegisterAperture = { + /*pClassDef=*/ &__nvoc_class_def_RegisterAperture, + /*dtor=*/ &__nvoc_destructFromBase, + /*offset=*/ NV_OFFSETOF(IoAperture, __nvoc_base_RegisterAperture), +}; + +static const struct NVOC_CASTINFO __nvoc_castinfo_IoAperture = { + /*numRelatives=*/ 3, + /*relatives=*/ { + &__nvoc_rtti_IoAperture_IoAperture, + &__nvoc_rtti_IoAperture_RegisterAperture, + &__nvoc_rtti_IoAperture_Object, + }, +}; + +const struct NVOC_CLASS_DEF __nvoc_class_def_IoAperture = +{ + /*classInfo=*/ { + /*size=*/ sizeof(IoAperture), + /*classId=*/ classId(IoAperture), + /*providerId=*/ &__nvoc_rtti_provider, +#if NV_PRINTF_STRINGS_ALLOWED + /*name=*/ "IoAperture", +#endif + }, + /*objCreatefn=*/ (NVOC_DYNAMIC_OBJ_CREATE) &__nvoc_objCreateDynamic_IoAperture, + /*pCastInfo=*/ &__nvoc_castinfo_IoAperture, + /*pExportInfo=*/ &__nvoc_export_info_IoAperture +}; + +static NvU8 __nvoc_thunk_IoAperture_regaprtReadReg08(struct RegisterAperture *pAperture, NvU32 addr) { + return ioaprtReadReg08((struct IoAperture *)(((unsigned char *)pAperture) - __nvoc_rtti_IoAperture_RegisterAperture.offset), addr); +} + +static NvU16 __nvoc_thunk_IoAperture_regaprtReadReg16(struct RegisterAperture *pAperture, NvU32 addr) { + return ioaprtReadReg16((struct IoAperture *)(((unsigned char *)pAperture) - __nvoc_rtti_IoAperture_RegisterAperture.offset), addr); +} + +static NvU32 __nvoc_thunk_IoAperture_regaprtReadReg32(struct RegisterAperture *pAperture, NvU32 addr) { + return ioaprtReadReg32((struct IoAperture *)(((unsigned char *)pAperture) - __nvoc_rtti_IoAperture_RegisterAperture.offset), addr); +} + +static void __nvoc_thunk_IoAperture_regaprtWriteReg08(struct RegisterAperture *pAperture, NvU32 addr, NvV8 value) { + ioaprtWriteReg08((struct IoAperture *)(((unsigned char *)pAperture) - __nvoc_rtti_IoAperture_RegisterAperture.offset), addr, value); +} + +static void __nvoc_thunk_IoAperture_regaprtWriteReg16(struct RegisterAperture *pAperture, NvU32 addr, NvV16 value) { + ioaprtWriteReg16((struct IoAperture *)(((unsigned char *)pAperture) - __nvoc_rtti_IoAperture_RegisterAperture.offset), addr, value); +} + +static void __nvoc_thunk_IoAperture_regaprtWriteReg32(struct RegisterAperture *pAperture, NvU32 addr, NvV32 value) { + ioaprtWriteReg32((struct IoAperture *)(((unsigned char *)pAperture) - __nvoc_rtti_IoAperture_RegisterAperture.offset), addr, value); +} + +static void __nvoc_thunk_IoAperture_regaprtWriteReg32Uc(struct RegisterAperture *pAperture, NvU32 addr, NvV32 value) { + ioaprtWriteReg32Uc((struct IoAperture *)(((unsigned char *)pAperture) - __nvoc_rtti_IoAperture_RegisterAperture.offset), addr, value); +} + +static NvBool __nvoc_thunk_IoAperture_regaprtIsRegValid(struct RegisterAperture *pAperture, NvU32 addr) { + return ioaprtIsRegValid((struct IoAperture *)(((unsigned char *)pAperture) - __nvoc_rtti_IoAperture_RegisterAperture.offset), addr); +} + +const struct NVOC_EXPORT_INFO __nvoc_export_info_IoAperture = +{ + /*numEntries=*/ 0, + /*pExportEntries=*/ 0 +}; + +void __nvoc_dtor_Object(Object*); +void __nvoc_dtor_RegisterAperture(RegisterAperture*); +void __nvoc_dtor_IoAperture(IoAperture *pThis) { + __nvoc_dtor_Object(&pThis->__nvoc_base_Object); + __nvoc_dtor_RegisterAperture(&pThis->__nvoc_base_RegisterAperture); + PORT_UNREFERENCED_VARIABLE(pThis); +} + +void __nvoc_init_dataField_IoAperture(IoAperture *pThis) { + PORT_UNREFERENCED_VARIABLE(pThis); +} + +NV_STATUS __nvoc_ctor_Object(Object* ); +NV_STATUS __nvoc_ctor_RegisterAperture(RegisterAperture* ); +NV_STATUS __nvoc_ctor_IoAperture(IoAperture *pThis, struct IoAperture * arg_pParentAperture, OBJGPU * arg_pGpu, NvU32 arg_deviceIndex, NvU32 arg_deviceInstance, DEVICE_MAPPING * arg_pMapping, NvU32 arg_mappingStartAddr, NvU32 arg_offset, NvU32 arg_length) { + NV_STATUS status = NV_OK; + status = __nvoc_ctor_Object(&pThis->__nvoc_base_Object); + if (status != NV_OK) goto __nvoc_ctor_IoAperture_fail_Object; + status = __nvoc_ctor_RegisterAperture(&pThis->__nvoc_base_RegisterAperture); + if (status != NV_OK) goto __nvoc_ctor_IoAperture_fail_RegisterAperture; + __nvoc_init_dataField_IoAperture(pThis); + + status = __nvoc_ioaprtConstruct(pThis, arg_pParentAperture, arg_pGpu, arg_deviceIndex, arg_deviceInstance, arg_pMapping, arg_mappingStartAddr, arg_offset, arg_length); + if (status != NV_OK) goto __nvoc_ctor_IoAperture_fail__init; + goto __nvoc_ctor_IoAperture_exit; // Success + +__nvoc_ctor_IoAperture_fail__init: + __nvoc_dtor_RegisterAperture(&pThis->__nvoc_base_RegisterAperture); +__nvoc_ctor_IoAperture_fail_RegisterAperture: + __nvoc_dtor_Object(&pThis->__nvoc_base_Object); +__nvoc_ctor_IoAperture_fail_Object: +__nvoc_ctor_IoAperture_exit: + + return status; +} + +static void __nvoc_init_funcTable_IoAperture_1(IoAperture *pThis) { + PORT_UNREFERENCED_VARIABLE(pThis); + + pThis->__ioaprtReadReg08__ = &ioaprtReadReg08_IMPL; + + pThis->__ioaprtReadReg16__ = &ioaprtReadReg16_IMPL; + + pThis->__ioaprtReadReg32__ = &ioaprtReadReg32_IMPL; + + pThis->__ioaprtWriteReg08__ = &ioaprtWriteReg08_IMPL; + + pThis->__ioaprtWriteReg16__ = &ioaprtWriteReg16_IMPL; + + pThis->__ioaprtWriteReg32__ = &ioaprtWriteReg32_IMPL; + + pThis->__ioaprtWriteReg32Uc__ = &ioaprtWriteReg32Uc_IMPL; + + pThis->__ioaprtIsRegValid__ = &ioaprtIsRegValid_IMPL; + + pThis->__nvoc_base_RegisterAperture.__regaprtReadReg08__ = &__nvoc_thunk_IoAperture_regaprtReadReg08; + + pThis->__nvoc_base_RegisterAperture.__regaprtReadReg16__ = &__nvoc_thunk_IoAperture_regaprtReadReg16; + + pThis->__nvoc_base_RegisterAperture.__regaprtReadReg32__ = &__nvoc_thunk_IoAperture_regaprtReadReg32; + + pThis->__nvoc_base_RegisterAperture.__regaprtWriteReg08__ = &__nvoc_thunk_IoAperture_regaprtWriteReg08; + + pThis->__nvoc_base_RegisterAperture.__regaprtWriteReg16__ = &__nvoc_thunk_IoAperture_regaprtWriteReg16; + + pThis->__nvoc_base_RegisterAperture.__regaprtWriteReg32__ = &__nvoc_thunk_IoAperture_regaprtWriteReg32; + + pThis->__nvoc_base_RegisterAperture.__regaprtWriteReg32Uc__ = &__nvoc_thunk_IoAperture_regaprtWriteReg32Uc; + + pThis->__nvoc_base_RegisterAperture.__regaprtIsRegValid__ = &__nvoc_thunk_IoAperture_regaprtIsRegValid; +} + +void __nvoc_init_funcTable_IoAperture(IoAperture *pThis) { + __nvoc_init_funcTable_IoAperture_1(pThis); +} + +void __nvoc_init_Object(Object*); +void __nvoc_init_RegisterAperture(RegisterAperture*); +void __nvoc_init_IoAperture(IoAperture *pThis) { + pThis->__nvoc_pbase_IoAperture = pThis; + pThis->__nvoc_pbase_Object = &pThis->__nvoc_base_Object; + pThis->__nvoc_pbase_RegisterAperture = &pThis->__nvoc_base_RegisterAperture; + __nvoc_init_Object(&pThis->__nvoc_base_Object); + __nvoc_init_RegisterAperture(&pThis->__nvoc_base_RegisterAperture); + __nvoc_init_funcTable_IoAperture(pThis); +} + +NV_STATUS __nvoc_objCreate_IoAperture(IoAperture **ppThis, Dynamic *pParent, NvU32 createFlags, struct IoAperture * arg_pParentAperture, OBJGPU * arg_pGpu, NvU32 arg_deviceIndex, NvU32 arg_deviceInstance, DEVICE_MAPPING * arg_pMapping, NvU32 arg_mappingStartAddr, NvU32 arg_offset, NvU32 arg_length) { + NV_STATUS status; + Object *pParentObj; + IoAperture *pThis; + + status = __nvoc_handleObjCreateMemAlloc(createFlags, sizeof(IoAperture), (void**)&pThis, (void**)ppThis); + if (status != NV_OK) + return status; + + portMemSet(pThis, 0, sizeof(IoAperture)); + + __nvoc_initRtti(staticCast(pThis, Dynamic), &__nvoc_class_def_IoAperture); + + pThis->__nvoc_base_Object.createFlags = createFlags; + + if (pParent != NULL && !(createFlags & NVOC_OBJ_CREATE_FLAGS_PARENT_HALSPEC_ONLY)) + { + pParentObj = dynamicCast(pParent, Object); + objAddChild(pParentObj, &pThis->__nvoc_base_Object); + } + else + { + pThis->__nvoc_base_Object.pParent = NULL; + } + + __nvoc_init_IoAperture(pThis); + status = __nvoc_ctor_IoAperture(pThis, arg_pParentAperture, arg_pGpu, arg_deviceIndex, arg_deviceInstance, arg_pMapping, arg_mappingStartAddr, arg_offset, arg_length); + if (status != NV_OK) goto __nvoc_objCreate_IoAperture_cleanup; + + *ppThis = pThis; + + return NV_OK; + +__nvoc_objCreate_IoAperture_cleanup: + // do not call destructors here since the constructor already called them + if (createFlags & NVOC_OBJ_CREATE_FLAGS_IN_PLACE_CONSTRUCT) + portMemSet(pThis, 0, sizeof(IoAperture)); + else + portMemFree(pThis); + + // coverity[leaked_storage:FALSE] + return status; +} + +NV_STATUS __nvoc_objCreateDynamic_IoAperture(IoAperture **ppThis, Dynamic *pParent, NvU32 createFlags, va_list args) { + NV_STATUS status; + struct IoAperture * arg_pParentAperture = va_arg(args, struct IoAperture *); + OBJGPU * arg_pGpu = va_arg(args, OBJGPU *); + NvU32 arg_deviceIndex = va_arg(args, NvU32); + NvU32 arg_deviceInstance = va_arg(args, NvU32); + DEVICE_MAPPING * arg_pMapping = va_arg(args, DEVICE_MAPPING *); + NvU32 arg_mappingStartAddr = va_arg(args, NvU32); + NvU32 arg_offset = va_arg(args, NvU32); + NvU32 arg_length = va_arg(args, NvU32); + + status = __nvoc_objCreate_IoAperture(ppThis, pParent, createFlags, arg_pParentAperture, arg_pGpu, arg_deviceIndex, arg_deviceInstance, arg_pMapping, arg_mappingStartAddr, arg_offset, arg_length); + + return status; +} + +#ifdef DEBUG +char __nvoc_class_id_uniqueness_check_0x6d0f88 = 1; +#endif + +extern const struct NVOC_CLASS_DEF __nvoc_class_def_SwBcAperture; + +extern const struct NVOC_CLASS_DEF __nvoc_class_def_Object; + +extern const struct NVOC_CLASS_DEF __nvoc_class_def_RegisterAperture; + +void __nvoc_init_SwBcAperture(SwBcAperture*); +void __nvoc_init_funcTable_SwBcAperture(SwBcAperture*); +NV_STATUS __nvoc_ctor_SwBcAperture(SwBcAperture*, struct IoAperture * arg_pApertures, NvU32 arg_numApertures); +void __nvoc_init_dataField_SwBcAperture(SwBcAperture*); +void __nvoc_dtor_SwBcAperture(SwBcAperture*); +extern const struct NVOC_EXPORT_INFO __nvoc_export_info_SwBcAperture; + +static const struct NVOC_RTTI __nvoc_rtti_SwBcAperture_SwBcAperture = { + /*pClassDef=*/ &__nvoc_class_def_SwBcAperture, + /*dtor=*/ (NVOC_DYNAMIC_DTOR) &__nvoc_dtor_SwBcAperture, + /*offset=*/ 0, +}; + +static const struct NVOC_RTTI __nvoc_rtti_SwBcAperture_Object = { + /*pClassDef=*/ &__nvoc_class_def_Object, + /*dtor=*/ &__nvoc_destructFromBase, + /*offset=*/ NV_OFFSETOF(SwBcAperture, __nvoc_base_Object), +}; + +static const struct NVOC_RTTI __nvoc_rtti_SwBcAperture_RegisterAperture = { + /*pClassDef=*/ &__nvoc_class_def_RegisterAperture, + /*dtor=*/ &__nvoc_destructFromBase, + /*offset=*/ NV_OFFSETOF(SwBcAperture, __nvoc_base_RegisterAperture), +}; + +static const struct NVOC_CASTINFO __nvoc_castinfo_SwBcAperture = { + /*numRelatives=*/ 3, + /*relatives=*/ { + &__nvoc_rtti_SwBcAperture_SwBcAperture, + &__nvoc_rtti_SwBcAperture_RegisterAperture, + &__nvoc_rtti_SwBcAperture_Object, + }, +}; + +const struct NVOC_CLASS_DEF __nvoc_class_def_SwBcAperture = +{ + /*classInfo=*/ { + /*size=*/ sizeof(SwBcAperture), + /*classId=*/ classId(SwBcAperture), + /*providerId=*/ &__nvoc_rtti_provider, +#if NV_PRINTF_STRINGS_ALLOWED + /*name=*/ "SwBcAperture", +#endif + }, + /*objCreatefn=*/ (NVOC_DYNAMIC_OBJ_CREATE) &__nvoc_objCreateDynamic_SwBcAperture, + /*pCastInfo=*/ &__nvoc_castinfo_SwBcAperture, + /*pExportInfo=*/ &__nvoc_export_info_SwBcAperture +}; + +static NvU8 __nvoc_thunk_SwBcAperture_regaprtReadReg08(struct RegisterAperture *pAperture, NvU32 addr) { + return swbcaprtReadReg08((struct SwBcAperture *)(((unsigned char *)pAperture) - __nvoc_rtti_SwBcAperture_RegisterAperture.offset), addr); +} + +static NvU16 __nvoc_thunk_SwBcAperture_regaprtReadReg16(struct RegisterAperture *pAperture, NvU32 addr) { + return swbcaprtReadReg16((struct SwBcAperture *)(((unsigned char *)pAperture) - __nvoc_rtti_SwBcAperture_RegisterAperture.offset), addr); +} + +static NvU32 __nvoc_thunk_SwBcAperture_regaprtReadReg32(struct RegisterAperture *pAperture, NvU32 addr) { + return swbcaprtReadReg32((struct SwBcAperture *)(((unsigned char *)pAperture) - __nvoc_rtti_SwBcAperture_RegisterAperture.offset), addr); +} + +static void __nvoc_thunk_SwBcAperture_regaprtWriteReg08(struct RegisterAperture *pAperture, NvU32 addr, NvV8 value) { + swbcaprtWriteReg08((struct SwBcAperture *)(((unsigned char *)pAperture) - __nvoc_rtti_SwBcAperture_RegisterAperture.offset), addr, value); +} + +static void __nvoc_thunk_SwBcAperture_regaprtWriteReg16(struct RegisterAperture *pAperture, NvU32 addr, NvV16 value) { + swbcaprtWriteReg16((struct SwBcAperture *)(((unsigned char *)pAperture) - __nvoc_rtti_SwBcAperture_RegisterAperture.offset), addr, value); +} + +static void __nvoc_thunk_SwBcAperture_regaprtWriteReg32(struct RegisterAperture *pAperture, NvU32 addr, NvV32 value) { + swbcaprtWriteReg32((struct SwBcAperture *)(((unsigned char *)pAperture) - __nvoc_rtti_SwBcAperture_RegisterAperture.offset), addr, value); +} + +static void __nvoc_thunk_SwBcAperture_regaprtWriteReg32Uc(struct RegisterAperture *pAperture, NvU32 addr, NvV32 value) { + swbcaprtWriteReg32Uc((struct SwBcAperture *)(((unsigned char *)pAperture) - __nvoc_rtti_SwBcAperture_RegisterAperture.offset), addr, value); +} + +static NvBool __nvoc_thunk_SwBcAperture_regaprtIsRegValid(struct RegisterAperture *pAperture, NvU32 addr) { + return swbcaprtIsRegValid((struct SwBcAperture *)(((unsigned char *)pAperture) - __nvoc_rtti_SwBcAperture_RegisterAperture.offset), addr); +} + +const struct NVOC_EXPORT_INFO __nvoc_export_info_SwBcAperture = +{ + /*numEntries=*/ 0, + /*pExportEntries=*/ 0 +}; + +void __nvoc_dtor_Object(Object*); +void __nvoc_dtor_RegisterAperture(RegisterAperture*); +void __nvoc_dtor_SwBcAperture(SwBcAperture *pThis) { + __nvoc_dtor_Object(&pThis->__nvoc_base_Object); + __nvoc_dtor_RegisterAperture(&pThis->__nvoc_base_RegisterAperture); + PORT_UNREFERENCED_VARIABLE(pThis); +} + +void __nvoc_init_dataField_SwBcAperture(SwBcAperture *pThis) { + PORT_UNREFERENCED_VARIABLE(pThis); +} + +NV_STATUS __nvoc_ctor_Object(Object* ); +NV_STATUS __nvoc_ctor_RegisterAperture(RegisterAperture* ); +NV_STATUS __nvoc_ctor_SwBcAperture(SwBcAperture *pThis, struct IoAperture * arg_pApertures, NvU32 arg_numApertures) { + NV_STATUS status = NV_OK; + status = __nvoc_ctor_Object(&pThis->__nvoc_base_Object); + if (status != NV_OK) goto __nvoc_ctor_SwBcAperture_fail_Object; + status = __nvoc_ctor_RegisterAperture(&pThis->__nvoc_base_RegisterAperture); + if (status != NV_OK) goto __nvoc_ctor_SwBcAperture_fail_RegisterAperture; + __nvoc_init_dataField_SwBcAperture(pThis); + + status = __nvoc_swbcaprtConstruct(pThis, arg_pApertures, arg_numApertures); + if (status != NV_OK) goto __nvoc_ctor_SwBcAperture_fail__init; + goto __nvoc_ctor_SwBcAperture_exit; // Success + +__nvoc_ctor_SwBcAperture_fail__init: + __nvoc_dtor_RegisterAperture(&pThis->__nvoc_base_RegisterAperture); +__nvoc_ctor_SwBcAperture_fail_RegisterAperture: + __nvoc_dtor_Object(&pThis->__nvoc_base_Object); +__nvoc_ctor_SwBcAperture_fail_Object: +__nvoc_ctor_SwBcAperture_exit: + + return status; +} + +static void __nvoc_init_funcTable_SwBcAperture_1(SwBcAperture *pThis) { + PORT_UNREFERENCED_VARIABLE(pThis); + + pThis->__swbcaprtReadReg08__ = &swbcaprtReadReg08_IMPL; + + pThis->__swbcaprtReadReg16__ = &swbcaprtReadReg16_IMPL; + + pThis->__swbcaprtReadReg32__ = &swbcaprtReadReg32_IMPL; + + pThis->__swbcaprtWriteReg08__ = &swbcaprtWriteReg08_IMPL; + + pThis->__swbcaprtWriteReg16__ = &swbcaprtWriteReg16_IMPL; + + pThis->__swbcaprtWriteReg32__ = &swbcaprtWriteReg32_IMPL; + + pThis->__swbcaprtWriteReg32Uc__ = &swbcaprtWriteReg32Uc_IMPL; + + pThis->__swbcaprtIsRegValid__ = &swbcaprtIsRegValid_IMPL; + + pThis->__nvoc_base_RegisterAperture.__regaprtReadReg08__ = &__nvoc_thunk_SwBcAperture_regaprtReadReg08; + + pThis->__nvoc_base_RegisterAperture.__regaprtReadReg16__ = &__nvoc_thunk_SwBcAperture_regaprtReadReg16; + + pThis->__nvoc_base_RegisterAperture.__regaprtReadReg32__ = &__nvoc_thunk_SwBcAperture_regaprtReadReg32; + + pThis->__nvoc_base_RegisterAperture.__regaprtWriteReg08__ = &__nvoc_thunk_SwBcAperture_regaprtWriteReg08; + + pThis->__nvoc_base_RegisterAperture.__regaprtWriteReg16__ = &__nvoc_thunk_SwBcAperture_regaprtWriteReg16; + + pThis->__nvoc_base_RegisterAperture.__regaprtWriteReg32__ = &__nvoc_thunk_SwBcAperture_regaprtWriteReg32; + + pThis->__nvoc_base_RegisterAperture.__regaprtWriteReg32Uc__ = &__nvoc_thunk_SwBcAperture_regaprtWriteReg32Uc; + + pThis->__nvoc_base_RegisterAperture.__regaprtIsRegValid__ = &__nvoc_thunk_SwBcAperture_regaprtIsRegValid; +} + +void __nvoc_init_funcTable_SwBcAperture(SwBcAperture *pThis) { + __nvoc_init_funcTable_SwBcAperture_1(pThis); +} + +void __nvoc_init_Object(Object*); +void __nvoc_init_RegisterAperture(RegisterAperture*); +void __nvoc_init_SwBcAperture(SwBcAperture *pThis) { + pThis->__nvoc_pbase_SwBcAperture = pThis; + pThis->__nvoc_pbase_Object = &pThis->__nvoc_base_Object; + pThis->__nvoc_pbase_RegisterAperture = &pThis->__nvoc_base_RegisterAperture; + __nvoc_init_Object(&pThis->__nvoc_base_Object); + __nvoc_init_RegisterAperture(&pThis->__nvoc_base_RegisterAperture); + __nvoc_init_funcTable_SwBcAperture(pThis); +} + +NV_STATUS __nvoc_objCreate_SwBcAperture(SwBcAperture **ppThis, Dynamic *pParent, NvU32 createFlags, struct IoAperture * arg_pApertures, NvU32 arg_numApertures) { + NV_STATUS status; + Object *pParentObj; + SwBcAperture *pThis; + + status = __nvoc_handleObjCreateMemAlloc(createFlags, sizeof(SwBcAperture), (void**)&pThis, (void**)ppThis); + if (status != NV_OK) + return status; + + portMemSet(pThis, 0, sizeof(SwBcAperture)); + + __nvoc_initRtti(staticCast(pThis, Dynamic), &__nvoc_class_def_SwBcAperture); + + pThis->__nvoc_base_Object.createFlags = createFlags; + + if (pParent != NULL && !(createFlags & NVOC_OBJ_CREATE_FLAGS_PARENT_HALSPEC_ONLY)) + { + pParentObj = dynamicCast(pParent, Object); + objAddChild(pParentObj, &pThis->__nvoc_base_Object); + } + else + { + pThis->__nvoc_base_Object.pParent = NULL; + } + + __nvoc_init_SwBcAperture(pThis); + status = __nvoc_ctor_SwBcAperture(pThis, arg_pApertures, arg_numApertures); + if (status != NV_OK) goto __nvoc_objCreate_SwBcAperture_cleanup; + + *ppThis = pThis; + + return NV_OK; + +__nvoc_objCreate_SwBcAperture_cleanup: + // do not call destructors here since the constructor already called them + if (createFlags & NVOC_OBJ_CREATE_FLAGS_IN_PLACE_CONSTRUCT) + portMemSet(pThis, 0, sizeof(SwBcAperture)); + else + portMemFree(pThis); + + // coverity[leaked_storage:FALSE] + return status; +} + +NV_STATUS __nvoc_objCreateDynamic_SwBcAperture(SwBcAperture **ppThis, Dynamic *pParent, NvU32 createFlags, va_list args) { + NV_STATUS status; + struct IoAperture * arg_pApertures = va_arg(args, struct IoAperture *); + NvU32 arg_numApertures = va_arg(args, NvU32); + + status = __nvoc_objCreate_SwBcAperture(ppThis, pParent, createFlags, arg_pApertures, arg_numApertures); + + return status; +} + diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/generated/g_gpu_access_nvoc.h nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_gpu_access_nvoc.h --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/generated/g_gpu_access_nvoc.h 1970-01-01 00:00:00.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_gpu_access_nvoc.h 2024-03-05 22:18:14.000000000 +0000 @@ -0,0 +1,633 @@ +#ifndef _G_GPU_ACCESS_NVOC_H_ +#define _G_GPU_ACCESS_NVOC_H_ +#include "nvoc/runtime.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/* + * SPDX-FileCopyrightText: Copyright (c) 2004-2021 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ +#include "g_gpu_access_nvoc.h" + +#ifndef _GPU_ACCESS_H_ +#define _GPU_ACCESS_H_ + +#include "core/core.h" +#include "ioaccess/ioaccess.h" +#include "gpu/gpu_device_mapping.h" + +// Go straight at the memory or hardware. +#define MEM_RD08(a) (*(const volatile NvU8 *)(a)) +#define MEM_RD16(a) (*(const volatile NvU16 *)(a)) +#define MEM_RD32(a) (*(const volatile NvU32 *)(a)) +#define MEM_WR08(a, d) do { *(volatile NvU8 *)(a) = (d); } while (0) +#define MEM_WR16(a, d) do { *(volatile NvU16 *)(a) = (d); } while (0) +#define MEM_WR32(a, d) do { *(volatile NvU32 *)(a) = (d); } while (0) +#define MEM_WR64(a, d) do { *(volatile NvU64 *)(a) = (d); } while (0) + +// +// Define the signature of the register filter callback function +// +// flags can be optionally used for filters to decide whether to actually +// touch HW or not. flags should be OR'ed every time a new filter is found. (see objgpu.c) +// +typedef void (*GpuWriteRegCallback)(OBJGPU *, void *, NvU32 addr, NvU32 val, NvU32 accessSize, NvU32 flags); +typedef NvU32 (*GpuReadRegCallback)(OBJGPU *, void *, NvU32 addr, NvU32 accessSize, NvU32 flags); + +union GPUHWREG +{ + volatile NvV8 Reg008[1]; + volatile NvV16 Reg016[1]; + volatile NvV32 Reg032[1]; +}; + +typedef union GPUHWREG GPUHWREG; + +// +// Register filter record +// +// If REGISTER_FILTER_FLAGS_READ is set, then that means that the base RegRead +// function will not read the register, so the provided read callback function +// is expected to read the register and return the value. +// +// If REGISTER_FILTER_FLAGS_WRITE is set, then that means that the base RegWrite +// function will not write the register, so the provided callback write function +// is expected to write the given value to the register. +// +// It is an error to specify REGISTER_FILTER_FLAGS_READ and not provide a +// read callback function. +// +// It is an error to specify REGISTER_FILTER_FLAGS_WRITE and not provide a +// write callback function. +// +#define REGISTER_FILTER_FLAGS_READ (NVBIT(0)) +#define REGISTER_FILTER_FLAGS_WRITE (NVBIT(1)) +// filter is in the list but it is invalid and should be removed +#define REGISTER_FILTER_FLAGS_INVALID (NVBIT(2)) + +#define REGISTER_FILTER_FLAGS_VIRTUAL (0) +#define REGISTER_FILTER_FLAGS_READ_WRITE (REGISTER_FILTER_FLAGS_READ | REGISTER_FILTER_FLAGS_WRITE) + +typedef struct REGISTER_FILTER REGISTER_FILTER; + +struct REGISTER_FILTER +{ + REGISTER_FILTER *pNext; //!< pointer to next filter + NvU32 flags; //!< attributes of this filter + DEVICE_INDEX devIndex; //!< filter device + NvU32 devInstance; //!< filter device instance + NvU32 rangeStart; //!< filter range start (can overlap) + NvU32 rangeEnd; //!< filter range end (can overlap) + GpuWriteRegCallback pWriteCallback; //!< callback for write + GpuReadRegCallback pReadCallback; //!< callback for read + void *pParam; //!< pointer to param which gets passed to callbacks +}; + +typedef struct { + REGISTER_FILTER *pRegFilterList; // Active filters + REGISTER_FILTER *pRegFilterRecycleList; // Inactive filters + PORT_SPINLOCK * pRegFilterLock; // Thread-safe list management + NvU32 regFilterRefCnt; // Thread-safe list management + NvBool bRegFilterNeedRemove; // Thread-safe list garbage collection +} DEVICE_REGFILTER_INFO; + +typedef struct DEVICE_MAPPING +{ + GPUHWREG *gpuNvAddr; // CPU Virtual Address + RmPhysAddr gpuNvPAddr; // Physical Base Address + NvU32 gpuNvLength; // Length of the Aperture + NvU32 gpuNvSaveLength; + NvU32 gpuDeviceEnum; // Device ID NV_DEVID_* + NvU32 refCount; // refCount for the device map. + DEVICE_REGFILTER_INFO devRegFilterInfo; // register filter range list +} DEVICE_MAPPING; + +typedef struct +{ + // Pointer to GPU linked to this RegisterAccess object + OBJGPU *pGpu; + + // HW register access tools + GPUHWREG *gpuFbAddr; + GPUHWREG *gpuInstAddr; + + // Register access profiling + NvU32 regReadCount; + NvU32 regWriteCount; +} RegisterAccess; + +/*! Init register IO access path */ +NV_STATUS regAccessConstruct(RegisterAccess *, OBJGPU *pGpu); + +/*! Shutdown register IO access path */ +void regAccessDestruct(RegisterAccess *); + +/*! Writes to 8 bit register */ +void regWrite008(RegisterAccess *, DEVICE_INDEX, NvU32, NvU32, NvV8); + +/*! Writes to 16 bit register */ +void regWrite016(RegisterAccess *, DEVICE_INDEX, NvU32, NvU32, NvV16); + +/*! Writes to 32 bit register, with thread state on the stack */ +void regWrite032(RegisterAccess *, DEVICE_INDEX, NvU32, NvU32, NvV32, THREAD_STATE_NODE *); + +/*! Unicast register access, with thread state on the stack */ +void regWrite032Unicast(RegisterAccess *, DEVICE_INDEX, NvU32, NvU32, NvV32, THREAD_STATE_NODE *); + +/*! Reads from 8 bit register */ +NvU8 regRead008(RegisterAccess *, DEVICE_INDEX, NvU32, NvU32); + +/*! Reads from 16 bit register */ +NvU16 regRead016(RegisterAccess *, DEVICE_INDEX, NvU32, NvU32); + +/*! Reads from 32 bit register, with thread state on the stack */ +NvU32 regRead032(RegisterAccess *, DEVICE_INDEX, NvU32, NvU32, THREAD_STATE_NODE *); + +/*! Reads from 32 bit register and checks bit mask, with thread state on the stack */ +NvU32 regCheckRead032(RegisterAccess *, NvU32, NvU32, THREAD_STATE_NODE *); + +/*! Reads 32 bit register and polls bit field for specific value */ +NV_STATUS regRead032_AndPoll(RegisterAccess *, DEVICE_INDEX, NvU32, NvU32, NvU32); + +/*! Adds a register filter */ +NV_STATUS regAddRegisterFilter(RegisterAccess *, NvU32, DEVICE_INDEX, NvU32, NvU32, NvU32, GpuWriteRegCallback, GpuReadRegCallback, void *, REGISTER_FILTER **); + +/*! Removes register filter */ +void regRemoveRegisterFilter(RegisterAccess *, REGISTER_FILTER *); + +/*! Check status of read return value for GPU/bus errors */ +void regCheckAndLogReadFailure(RegisterAccess *, NvU32 addr, NvU32 mask, NvU32 value); + +// +// GPU register I/O macros. +// + +// +// GPU neutral macros typically used for register I/O. +// +#define GPU_DRF_SHIFT(drf) ((0?drf) % 32) +#define GPU_DRF_MASK(drf) (0xFFFFFFFF>>(31-((1?drf) % 32)+((0?drf) % 32))) +#define GPU_DRF_DEF(d,r,f,c) ((NV ## d ## r ## f ## c)<>GPU_DRF_SHIFT(NV ## d ## r ## f))&GPU_DRF_MASK(NV ## d ## r ## f)) +#define GPU_DRF_SHIFTMASK(drf) (GPU_DRF_MASK(drf)<<(GPU_DRF_SHIFT(drf))) +#define GPU_DRF_WIDTH(drf) ((1?drf) - (0?drf) + 1) + + +// Device independent macros +// Multiple device instance macros + +#define REG_INST_RD08(g,dev,inst,a) regRead008(GPU_GET_REGISTER_ACCESS(g), DEVICE_INDEX_##dev, inst, a) +#define REG_INST_RD16(g,dev,inst,a) regRead016(GPU_GET_REGISTER_ACCESS(g), DEVICE_INDEX_##dev, inst, a) +#define REG_INST_RD32(g,dev,inst,a) regRead032(GPU_GET_REGISTER_ACCESS(g), DEVICE_INDEX_##dev, inst, a, NULL) + +#define REG_INST_WR08(g,dev,inst,a,v) regWrite008(GPU_GET_REGISTER_ACCESS(g), DEVICE_INDEX_##dev, inst, a, v) +#define REG_INST_WR16(g,dev,inst,a,v) regWrite016(GPU_GET_REGISTER_ACCESS(g), DEVICE_INDEX_##dev, inst, a, v) +#define REG_INST_WR32(g,dev,inst,a,v) regWrite032(GPU_GET_REGISTER_ACCESS(g), DEVICE_INDEX_##dev, inst, a, v, NULL) +#define REG_INST_WR32_UC(g,dev,inst,a,v) regWrite032Unicast(GPU_GET_REGISTER_ACCESS(g), DEVICE_INDEX_##dev, inst, a, v, NULL) + +#define REG_INST_RD32_EX(g,dev,inst,a,t) regRead032(GPU_GET_REGISTER_ACCESS(g), DEVICE_INDEX_##dev, inst, a, t) +#define REG_INST_WR32_EX(g,dev,inst,a,v,t) regWrite032(GPU_GET_REGISTER_ACCESS(g), DEVICE_INDEX_##dev, inst, a, v, t) + +#define REG_INST_DEVIDX_RD32_EX(g,devidx,inst,a,t) regRead032(GPU_GET_REGISTER_ACCESS(g), devidx, inst, a, t) +#define REG_INST_DEVIDX_WR32_EX(g,devidx,inst,a,v,t) regWrite032(GPU_GET_REGISTER_ACCESS(g), devidx, inst, a, v, t) + +// Get the address of a register given the Aperture and offset. +#define REG_GET_ADDR(ap, offset) ioaprtGetRegAddr(ap, offset) + +// GPU macros defined in terms of DEV_ macros +#define GPU_REG_RD08(g,a) REG_INST_RD08(g,GPU,0,a) +#define GPU_REG_RD16(g,a) REG_INST_RD16(g,GPU,0,a) +#define GPU_REG_RD32(g,a) REG_INST_RD32(g,GPU,0,a) +#define GPU_CHECK_REG_RD32(g,a,m) regCheckRead032(GPU_GET_REGISTER_ACCESS(g),a,m,NULL) +#define GPU_REG_RD32_AND_POLL(g,r,m,v) regRead032_AndPoll(GPU_GET_REGISTER_ACCESS(g), DEVICE_INDEX_GPU, r, m, v) + +#define GPU_REG_WR08(g,a,v) REG_INST_WR08(g,GPU,0,a,v) +#define GPU_REG_WR16(g,a,v) REG_INST_WR16(g,GPU,0,a,v) +#define GPU_REG_WR32(g,a,v) REG_INST_WR32(g,GPU,0,a,v) +#define GPU_REG_WR32_UC(g,a,v) REG_INST_WR32_UC(g,GPU,0,a,v) + +// GPU macros for SR-IOV +#define GPU_VREG_RD32(g, a) GPU_REG_RD32(g, g->sriovState.virtualRegPhysOffset + a) +#define GPU_VREG_WR32(g, a, v) GPU_REG_WR32(g, g->sriovState.virtualRegPhysOffset + a, v) +#define GPU_VREG_RD32_EX(g,a,t) REG_INST_RD32_EX(g, GPU, 0, g->sriovState.virtualRegPhysOffset + a, t) +#define GPU_VREG_WR32_EX(g,a,v,t) REG_INST_WR32_EX(g, GPU, 0, g->sriovState.virtualRegPhysOffset + a, v, t) +#define GPU_VREG_FLD_WR_DRF_DEF(g,d,r,f,c) GPU_VREG_WR32(g, NV##d##r,(GPU_VREG_RD32(g,NV##d##r)&~(GPU_DRF_MASK(NV##d##r##f)<>GPU_DRF_SHIFT(NV ## d ## r ## f))&GPU_DRF_MASK(NV ## d ## r ## f)) + +#define VREG_INST_RD32(g,dev,inst,a) regRead032(GPU_GET_REGISTER_ACCESS(g), DEVICE_INDEX_##dev, inst, g->sriovState.virtualRegPhysOffset + a, NULL) +#define VREG_INST_WR32(g,dev,inst,a,v) regWrite032(GPU_GET_REGISTER_ACCESS(g), DEVICE_INDEX_##dev, inst, g->sriovState.virtualRegPhysOffset + a, v, NULL) +#define GPU_VREG_FLD_WR_DRF_NUM(g,d,r,f,n) VREG_INST_WR32(g,GPU,0,NV##d##r,(VREG_INST_RD32(g,GPU,0,NV##d##r)&~(GPU_DRF_MASK(NV##d##r##f)<sriovState.virtualRegPhysOffset + a) + +#define GPU_VREG_IDX_RD_DRF(g,d,r,i,f) (((GPU_VREG_RD32(g, NV ## d ## r(i)))>>GPU_DRF_SHIFT(NV ## d ## r ## f))&GPU_DRF_MASK(NV ## d ## r ## f)) +#define GPU_VREG_FLD_IDX_WR_DRF_DEF(g,d,r,i,f,c) GPU_VREG_WR32(g, NV##d##r(i),(GPU_VREG_RD32(g,NV##d##r(i))&~(GPU_DRF_MASK(NV##d##r##f)<sriovState.virtualRegPhysOffset + a) +#define GPU_VREG_WR32(g, a, v) gpuRegWr32_dumpinfo(__FUNCTION__,#a,"(VREG)",g, g->sriovState.virtualRegPhysOffset + a, v) + +#endif // GPU_REGISTER_ACCESS_DUMP + +// +// Macros for register I/O +// +#define GPU_FLD_WR_DRF_NUM(g,d,r,f,n) REG_INST_WR32(g,GPU,0,NV##d##r,(REG_INST_RD32(g,GPU,0,NV##d##r)&~(GPU_DRF_MASK(NV##d##r##f)<>GPU_DRF_SHIFT(NV ## d ## r ## f))&GPU_DRF_MASK(NV ## d ## r ## f)) +#define GPU_FLD_TEST_DRF_DEF(g,d,r,f,c) (GPU_REG_RD_DRF(g, d, r, f) == NV##d##r##f##c) +#define GPU_FLD_TEST_DRF_NUM(g,d,r,f,n) (GPU_REG_RD_DRF(g, d, r, f) == n) +#define GPU_FLD_IDX_TEST_DRF_DEF(g,d,r,f,c,i) (GPU_REG_IDX_RD_DRF(g, d, r, i, f) == NV##d##r##f##c) +#define GPU_FLD_2IDX_TEST_DRF_DEF(g,d,r,f,c,i,j) (GPU_REG_2IDX_RD_DRF(g, d, r, i, j, f) == NV##d##r##f##c) + +#define GPU_REG_RD_DRF_EX(g,d,r,f,t) (((GPU_REG_RD32_EX(g, NV ## d ## r, t))>>GPU_DRF_SHIFT(NV ## d ## r ## f))&GPU_DRF_MASK(NV ## d ## r ## f)) + +#define GPU_FLD_WR_DRF_NUM_EX(g,d,r,f,n,t) REG_INST_WR32_EX(g,GPU,0,NV##d##r,(REG_INST_RD32_EX(g,GPU,0,NV##d##r,t)&~(GPU_DRF_MASK(NV##d##r##f)<>GPU_DRF_SHIFT(NV ## d ## r ## f))&GPU_DRF_MASK(NV ## d ## r ## f)) +#define GPU_REG_2IDX_RD_DRF(g,d,r,i,j,f) (((GPU_REG_RD32(g, NV ## d ## r(i, j)))>>GPU_DRF_SHIFT(NV ## d ## r ## f))&GPU_DRF_MASK(NV ## d ## r ## f)) +#define GPU_REG_RD_DRF_IDX(g,d,r,f,i) (((GPU_REG_RD32(g, NV ## d ## r))>>GPU_DRF_SHIFT(NV ## d ## r ## f(i)))&GPU_DRF_MASK(NV ## d ## r ## f(i))) +#define GPU_REG_IDX_OFFSET_RD_DRF(g,d,r,i,o,f) (((GPU_REG_RD32(g, NV ## d ## r(i,o)))>>GPU_DRF_SHIFT(NV ## d ## r ## f))&GPU_DRF_MASK(NV ## d ## r ## f)) + +// +// Macros that abstract the use of bif object to access GPU bus config registers +// This is the preferred set >= NV50 +// +#define GPU_BUS_CFG_RD32(g,r,d) gpuReadBusConfigReg_HAL(g, r, d) +#define GPU_BUS_CFG_WR32(g,r,d) gpuWriteBusConfigReg_HAL(g, r, d) +#define GPU_BUS_CFG_FLD_WR_DRF_DEF(g,x,d,r,f,c) GPU_BUS_CFG_WR32(g, NV##d##r,(x &~(GPU_DRF_MASK(NV##d##r##f)<>(31-(1?sf)+(0?sf))) +#define SF_SHIFTMASK(sf) (SF_MASK(sf) << SF_SHIFT(sf)) +#define SF_DEF(s,f,c) ((NV ## s ## f ## c)<>SF_SHIFT(NV ## s ## f))&SF_MASK(NV ## s ## f)) +#define SF_WIDTH(sf) ((1?sf) - (0?sf) + 1) +// This macro parses multi-word/array defines +#define SF_ARR32_VAL(s,f,arr) \ + (((arr)[SF_INDEX(NV ## s ## f)] >> SF_SHIFT(NV ## s ## f)) & SF_MASK(NV ## s ## f)) +#define FLD_SF_DEF(s,f,d,l) ((l)&~(SF_MASK(NV##s##f) << SF_SHIFT(NV##s##f)))| SF_DEF(s,f,d) +#define FLD_SF_NUM(s,f,n,l) ((l)&~(SF_MASK(NV##s##f) << SF_SHIFT(NV##s##f)))| SF_NUM(s,f,n) +#define FLD_SF_IDX_DEF(s,f,c,i,l) (((l) & ~SF_SHIFTMASK(NV ## s ## f(i))) | SF_IDX_DEF(s,f,c,i)) +#define FLD_SF_IDX_NUM(s,f,n,i,l) (((l) & ~SF_SHIFTMASK(NV ## s ## f(i))) | SF_IDX_NUM(s,f,n,i)) + +#ifdef NVOC_GPU_ACCESS_H_PRIVATE_ACCESS_ALLOWED +#define PRIVATE_FIELD(x) x +#else +#define PRIVATE_FIELD(x) NVOC_PRIVATE_FIELD(x) +#endif +struct IoAperture { + const struct NVOC_RTTI *__nvoc_rtti; + struct Object __nvoc_base_Object; + struct RegisterAperture __nvoc_base_RegisterAperture; + struct Object *__nvoc_pbase_Object; + struct RegisterAperture *__nvoc_pbase_RegisterAperture; + struct IoAperture *__nvoc_pbase_IoAperture; + NvU8 (*__ioaprtReadReg08__)(struct IoAperture *, NvU32); + NvU16 (*__ioaprtReadReg16__)(struct IoAperture *, NvU32); + NvU32 (*__ioaprtReadReg32__)(struct IoAperture *, NvU32); + void (*__ioaprtWriteReg08__)(struct IoAperture *, NvU32, NvV8); + void (*__ioaprtWriteReg16__)(struct IoAperture *, NvU32, NvV16); + void (*__ioaprtWriteReg32__)(struct IoAperture *, NvU32, NvV32); + void (*__ioaprtWriteReg32Uc__)(struct IoAperture *, NvU32, NvV32); + NvBool (*__ioaprtIsRegValid__)(struct IoAperture *, NvU32); + OBJGPU *pGpu; + NvU32 deviceIndex; + NvU32 deviceInstance; + DEVICE_MAPPING *pMapping; + NvU32 mappingStartAddr; + NvU32 baseAddress; + NvU32 length; +}; + +#ifndef __NVOC_CLASS_IoAperture_TYPEDEF__ +#define __NVOC_CLASS_IoAperture_TYPEDEF__ +typedef struct IoAperture IoAperture; +#endif /* __NVOC_CLASS_IoAperture_TYPEDEF__ */ + +#ifndef __nvoc_class_id_IoAperture +#define __nvoc_class_id_IoAperture 0x40549c +#endif /* __nvoc_class_id_IoAperture */ + +extern const struct NVOC_CLASS_DEF __nvoc_class_def_IoAperture; + +#define __staticCast_IoAperture(pThis) \ + ((pThis)->__nvoc_pbase_IoAperture) + +#ifdef __nvoc_gpu_access_h_disabled +#define __dynamicCast_IoAperture(pThis) ((IoAperture*)NULL) +#else //__nvoc_gpu_access_h_disabled +#define __dynamicCast_IoAperture(pThis) \ + ((IoAperture*)__nvoc_dynamicCast(staticCast((pThis), Dynamic), classInfo(IoAperture))) +#endif //__nvoc_gpu_access_h_disabled + + +NV_STATUS __nvoc_objCreateDynamic_IoAperture(IoAperture**, Dynamic*, NvU32, va_list); + +NV_STATUS __nvoc_objCreate_IoAperture(IoAperture**, Dynamic*, NvU32, struct IoAperture * arg_pParentAperture, OBJGPU * arg_pGpu, NvU32 arg_deviceIndex, NvU32 arg_deviceInstance, DEVICE_MAPPING * arg_pMapping, NvU32 arg_mappingStartAddr, NvU32 arg_offset, NvU32 arg_length); +#define __objCreate_IoAperture(ppNewObj, pParent, createFlags, arg_pParentAperture, arg_pGpu, arg_deviceIndex, arg_deviceInstance, arg_pMapping, arg_mappingStartAddr, arg_offset, arg_length) \ + __nvoc_objCreate_IoAperture((ppNewObj), staticCast((pParent), Dynamic), (createFlags), arg_pParentAperture, arg_pGpu, arg_deviceIndex, arg_deviceInstance, arg_pMapping, arg_mappingStartAddr, arg_offset, arg_length) + +#define ioaprtReadReg08(pAperture, addr) ioaprtReadReg08_DISPATCH(pAperture, addr) +#define ioaprtReadReg16(pAperture, addr) ioaprtReadReg16_DISPATCH(pAperture, addr) +#define ioaprtReadReg32(pAperture, addr) ioaprtReadReg32_DISPATCH(pAperture, addr) +#define ioaprtWriteReg08(pAperture, addr, value) ioaprtWriteReg08_DISPATCH(pAperture, addr, value) +#define ioaprtWriteReg16(pAperture, addr, value) ioaprtWriteReg16_DISPATCH(pAperture, addr, value) +#define ioaprtWriteReg32(pAperture, addr, value) ioaprtWriteReg32_DISPATCH(pAperture, addr, value) +#define ioaprtWriteReg32Uc(pAperture, addr, value) ioaprtWriteReg32Uc_DISPATCH(pAperture, addr, value) +#define ioaprtIsRegValid(pAperture, addr) ioaprtIsRegValid_DISPATCH(pAperture, addr) +NvU8 ioaprtReadReg08_IMPL(struct IoAperture *pAperture, NvU32 addr); + +static inline NvU8 ioaprtReadReg08_DISPATCH(struct IoAperture *pAperture, NvU32 addr) { + return pAperture->__ioaprtReadReg08__(pAperture, addr); +} + +NvU16 ioaprtReadReg16_IMPL(struct IoAperture *pAperture, NvU32 addr); + +static inline NvU16 ioaprtReadReg16_DISPATCH(struct IoAperture *pAperture, NvU32 addr) { + return pAperture->__ioaprtReadReg16__(pAperture, addr); +} + +NvU32 ioaprtReadReg32_IMPL(struct IoAperture *pAperture, NvU32 addr); + +static inline NvU32 ioaprtReadReg32_DISPATCH(struct IoAperture *pAperture, NvU32 addr) { + return pAperture->__ioaprtReadReg32__(pAperture, addr); +} + +void ioaprtWriteReg08_IMPL(struct IoAperture *pAperture, NvU32 addr, NvV8 value); + +static inline void ioaprtWriteReg08_DISPATCH(struct IoAperture *pAperture, NvU32 addr, NvV8 value) { + pAperture->__ioaprtWriteReg08__(pAperture, addr, value); +} + +void ioaprtWriteReg16_IMPL(struct IoAperture *pAperture, NvU32 addr, NvV16 value); + +static inline void ioaprtWriteReg16_DISPATCH(struct IoAperture *pAperture, NvU32 addr, NvV16 value) { + pAperture->__ioaprtWriteReg16__(pAperture, addr, value); +} + +void ioaprtWriteReg32_IMPL(struct IoAperture *pAperture, NvU32 addr, NvV32 value); + +static inline void ioaprtWriteReg32_DISPATCH(struct IoAperture *pAperture, NvU32 addr, NvV32 value) { + pAperture->__ioaprtWriteReg32__(pAperture, addr, value); +} + +void ioaprtWriteReg32Uc_IMPL(struct IoAperture *pAperture, NvU32 addr, NvV32 value); + +static inline void ioaprtWriteReg32Uc_DISPATCH(struct IoAperture *pAperture, NvU32 addr, NvV32 value) { + pAperture->__ioaprtWriteReg32Uc__(pAperture, addr, value); +} + +NvBool ioaprtIsRegValid_IMPL(struct IoAperture *pAperture, NvU32 addr); + +static inline NvBool ioaprtIsRegValid_DISPATCH(struct IoAperture *pAperture, NvU32 addr) { + return pAperture->__ioaprtIsRegValid__(pAperture, addr); +} + +static inline NvU32 ioaprtGetRegAddr(struct IoAperture *pAperture, NvU32 addr) { + return pAperture->baseAddress + addr; +} + +static inline NvU32 ioaprtGetBaseAddr(struct IoAperture *pAperture) { + return pAperture->baseAddress; +} + +static inline NvU32 ioaprtGetLength(struct IoAperture *pAperture) { + return pAperture->length; +} + +NV_STATUS ioaprtConstruct_IMPL(struct IoAperture *arg_pAperture, struct IoAperture *arg_pParentAperture, OBJGPU *arg_pGpu, NvU32 arg_deviceIndex, NvU32 arg_deviceInstance, DEVICE_MAPPING *arg_pMapping, NvU32 arg_mappingStartAddr, NvU32 arg_offset, NvU32 arg_length); + +#define __nvoc_ioaprtConstruct(arg_pAperture, arg_pParentAperture, arg_pGpu, arg_deviceIndex, arg_deviceInstance, arg_pMapping, arg_mappingStartAddr, arg_offset, arg_length) ioaprtConstruct_IMPL(arg_pAperture, arg_pParentAperture, arg_pGpu, arg_deviceIndex, arg_deviceInstance, arg_pMapping, arg_mappingStartAddr, arg_offset, arg_length) +#undef PRIVATE_FIELD + + +// In-place construct wrapper +NV_STATUS ioaprtInit(struct IoAperture *pAperture, struct IoAperture *pParentAperture, NvU32 offset, NvU32 length); + +#ifdef NVOC_GPU_ACCESS_H_PRIVATE_ACCESS_ALLOWED +#define PRIVATE_FIELD(x) x +#else +#define PRIVATE_FIELD(x) NVOC_PRIVATE_FIELD(x) +#endif +struct SwBcAperture { + const struct NVOC_RTTI *__nvoc_rtti; + struct Object __nvoc_base_Object; + struct RegisterAperture __nvoc_base_RegisterAperture; + struct Object *__nvoc_pbase_Object; + struct RegisterAperture *__nvoc_pbase_RegisterAperture; + struct SwBcAperture *__nvoc_pbase_SwBcAperture; + NvU8 (*__swbcaprtReadReg08__)(struct SwBcAperture *, NvU32); + NvU16 (*__swbcaprtReadReg16__)(struct SwBcAperture *, NvU32); + NvU32 (*__swbcaprtReadReg32__)(struct SwBcAperture *, NvU32); + void (*__swbcaprtWriteReg08__)(struct SwBcAperture *, NvU32, NvV8); + void (*__swbcaprtWriteReg16__)(struct SwBcAperture *, NvU32, NvV16); + void (*__swbcaprtWriteReg32__)(struct SwBcAperture *, NvU32, NvV32); + void (*__swbcaprtWriteReg32Uc__)(struct SwBcAperture *, NvU32, NvV32); + NvBool (*__swbcaprtIsRegValid__)(struct SwBcAperture *, NvU32); + struct IoAperture *pApertures; + NvU32 numApertures; +}; + +#ifndef __NVOC_CLASS_SwBcAperture_TYPEDEF__ +#define __NVOC_CLASS_SwBcAperture_TYPEDEF__ +typedef struct SwBcAperture SwBcAperture; +#endif /* __NVOC_CLASS_SwBcAperture_TYPEDEF__ */ + +#ifndef __nvoc_class_id_SwBcAperture +#define __nvoc_class_id_SwBcAperture 0x6d0f88 +#endif /* __nvoc_class_id_SwBcAperture */ + +extern const struct NVOC_CLASS_DEF __nvoc_class_def_SwBcAperture; + +#define __staticCast_SwBcAperture(pThis) \ + ((pThis)->__nvoc_pbase_SwBcAperture) + +#ifdef __nvoc_gpu_access_h_disabled +#define __dynamicCast_SwBcAperture(pThis) ((SwBcAperture*)NULL) +#else //__nvoc_gpu_access_h_disabled +#define __dynamicCast_SwBcAperture(pThis) \ + ((SwBcAperture*)__nvoc_dynamicCast(staticCast((pThis), Dynamic), classInfo(SwBcAperture))) +#endif //__nvoc_gpu_access_h_disabled + + +NV_STATUS __nvoc_objCreateDynamic_SwBcAperture(SwBcAperture**, Dynamic*, NvU32, va_list); + +NV_STATUS __nvoc_objCreate_SwBcAperture(SwBcAperture**, Dynamic*, NvU32, struct IoAperture * arg_pApertures, NvU32 arg_numApertures); +#define __objCreate_SwBcAperture(ppNewObj, pParent, createFlags, arg_pApertures, arg_numApertures) \ + __nvoc_objCreate_SwBcAperture((ppNewObj), staticCast((pParent), Dynamic), (createFlags), arg_pApertures, arg_numApertures) + +#define swbcaprtReadReg08(pAperture, addr) swbcaprtReadReg08_DISPATCH(pAperture, addr) +#define swbcaprtReadReg16(pAperture, addr) swbcaprtReadReg16_DISPATCH(pAperture, addr) +#define swbcaprtReadReg32(pAperture, addr) swbcaprtReadReg32_DISPATCH(pAperture, addr) +#define swbcaprtWriteReg08(pAperture, addr, value) swbcaprtWriteReg08_DISPATCH(pAperture, addr, value) +#define swbcaprtWriteReg16(pAperture, addr, value) swbcaprtWriteReg16_DISPATCH(pAperture, addr, value) +#define swbcaprtWriteReg32(pAperture, addr, value) swbcaprtWriteReg32_DISPATCH(pAperture, addr, value) +#define swbcaprtWriteReg32Uc(pAperture, addr, value) swbcaprtWriteReg32Uc_DISPATCH(pAperture, addr, value) +#define swbcaprtIsRegValid(pAperture, addr) swbcaprtIsRegValid_DISPATCH(pAperture, addr) +NvU8 swbcaprtReadReg08_IMPL(struct SwBcAperture *pAperture, NvU32 addr); + +static inline NvU8 swbcaprtReadReg08_DISPATCH(struct SwBcAperture *pAperture, NvU32 addr) { + return pAperture->__swbcaprtReadReg08__(pAperture, addr); +} + +NvU16 swbcaprtReadReg16_IMPL(struct SwBcAperture *pAperture, NvU32 addr); + +static inline NvU16 swbcaprtReadReg16_DISPATCH(struct SwBcAperture *pAperture, NvU32 addr) { + return pAperture->__swbcaprtReadReg16__(pAperture, addr); +} + +NvU32 swbcaprtReadReg32_IMPL(struct SwBcAperture *pAperture, NvU32 addr); + +static inline NvU32 swbcaprtReadReg32_DISPATCH(struct SwBcAperture *pAperture, NvU32 addr) { + return pAperture->__swbcaprtReadReg32__(pAperture, addr); +} + +void swbcaprtWriteReg08_IMPL(struct SwBcAperture *pAperture, NvU32 addr, NvV8 value); + +static inline void swbcaprtWriteReg08_DISPATCH(struct SwBcAperture *pAperture, NvU32 addr, NvV8 value) { + pAperture->__swbcaprtWriteReg08__(pAperture, addr, value); +} + +void swbcaprtWriteReg16_IMPL(struct SwBcAperture *pAperture, NvU32 addr, NvV16 value); + +static inline void swbcaprtWriteReg16_DISPATCH(struct SwBcAperture *pAperture, NvU32 addr, NvV16 value) { + pAperture->__swbcaprtWriteReg16__(pAperture, addr, value); +} + +void swbcaprtWriteReg32_IMPL(struct SwBcAperture *pAperture, NvU32 addr, NvV32 value); + +static inline void swbcaprtWriteReg32_DISPATCH(struct SwBcAperture *pAperture, NvU32 addr, NvV32 value) { + pAperture->__swbcaprtWriteReg32__(pAperture, addr, value); +} + +void swbcaprtWriteReg32Uc_IMPL(struct SwBcAperture *pAperture, NvU32 addr, NvV32 value); + +static inline void swbcaprtWriteReg32Uc_DISPATCH(struct SwBcAperture *pAperture, NvU32 addr, NvV32 value) { + pAperture->__swbcaprtWriteReg32Uc__(pAperture, addr, value); +} + +NvBool swbcaprtIsRegValid_IMPL(struct SwBcAperture *pAperture, NvU32 addr); + +static inline NvBool swbcaprtIsRegValid_DISPATCH(struct SwBcAperture *pAperture, NvU32 addr) { + return pAperture->__swbcaprtIsRegValid__(pAperture, addr); +} + +NV_STATUS swbcaprtConstruct_IMPL(struct SwBcAperture *arg_pAperture, struct IoAperture *arg_pApertures, NvU32 arg_numApertures); + +#define __nvoc_swbcaprtConstruct(arg_pAperture, arg_pApertures, arg_numApertures) swbcaprtConstruct_IMPL(arg_pAperture, arg_pApertures, arg_numApertures) +#undef PRIVATE_FIELD + + +#endif // _GPU_ACCESS_H_ + +#ifdef __cplusplus +} // extern "C" +#endif +#endif // _G_GPU_ACCESS_NVOC_H_ diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/generated/g_gpu_acct_nvoc.c nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_gpu_acct_nvoc.c --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/generated/g_gpu_acct_nvoc.c 2023-10-25 20:26:57.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_gpu_acct_nvoc.c 2024-03-05 22:18:14.000000000 +0000 @@ -114,13 +114,16 @@ Object *pParentObj; GpuAccounting *pThis; - pThis = portMemAllocNonPaged(sizeof(GpuAccounting)); - if (pThis == NULL) return NV_ERR_NO_MEMORY; + status = __nvoc_handleObjCreateMemAlloc(createFlags, sizeof(GpuAccounting), (void**)&pThis, (void**)ppThis); + if (status != NV_OK) + return status; portMemSet(pThis, 0, sizeof(GpuAccounting)); __nvoc_initRtti(staticCast(pThis, Dynamic), &__nvoc_class_def_GpuAccounting); + pThis->__nvoc_base_Object.createFlags = createFlags; + if (pParent != NULL && !(createFlags & NVOC_OBJ_CREATE_FLAGS_PARENT_HALSPEC_ONLY)) { pParentObj = dynamicCast(pParent, Object); @@ -136,11 +139,17 @@ if (status != NV_OK) goto __nvoc_objCreate_GpuAccounting_cleanup; *ppThis = pThis; + return NV_OK; __nvoc_objCreate_GpuAccounting_cleanup: // do not call destructors here since the constructor already called them - portMemFree(pThis); + if (createFlags & NVOC_OBJ_CREATE_FLAGS_IN_PLACE_CONSTRUCT) + portMemSet(pThis, 0, sizeof(GpuAccounting)); + else + portMemFree(pThis); + + // coverity[leaked_storage:FALSE] return status; } diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/generated/g_gpu_boost_mgr_nvoc.c nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_gpu_boost_mgr_nvoc.c --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/generated/g_gpu_boost_mgr_nvoc.c 2023-10-25 20:26:58.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_gpu_boost_mgr_nvoc.c 2024-03-05 22:18:14.000000000 +0000 @@ -114,13 +114,16 @@ Object *pParentObj; OBJGPUBOOSTMGR *pThis; - pThis = portMemAllocNonPaged(sizeof(OBJGPUBOOSTMGR)); - if (pThis == NULL) return NV_ERR_NO_MEMORY; + status = __nvoc_handleObjCreateMemAlloc(createFlags, sizeof(OBJGPUBOOSTMGR), (void**)&pThis, (void**)ppThis); + if (status != NV_OK) + return status; portMemSet(pThis, 0, sizeof(OBJGPUBOOSTMGR)); __nvoc_initRtti(staticCast(pThis, Dynamic), &__nvoc_class_def_OBJGPUBOOSTMGR); + pThis->__nvoc_base_Object.createFlags = createFlags; + if (pParent != NULL && !(createFlags & NVOC_OBJ_CREATE_FLAGS_PARENT_HALSPEC_ONLY)) { pParentObj = dynamicCast(pParent, Object); @@ -136,11 +139,17 @@ if (status != NV_OK) goto __nvoc_objCreate_OBJGPUBOOSTMGR_cleanup; *ppThis = pThis; + return NV_OK; __nvoc_objCreate_OBJGPUBOOSTMGR_cleanup: // do not call destructors here since the constructor already called them - portMemFree(pThis); + if (createFlags & NVOC_OBJ_CREATE_FLAGS_IN_PLACE_CONSTRUCT) + portMemSet(pThis, 0, sizeof(OBJGPUBOOSTMGR)); + else + portMemFree(pThis); + + // coverity[leaked_storage:FALSE] return status; } diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/generated/g_gpu_boost_mgr_nvoc.h nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_gpu_boost_mgr_nvoc.h --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/generated/g_gpu_boost_mgr_nvoc.h 2023-10-25 20:26:58.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_gpu_boost_mgr_nvoc.h 2024-03-05 22:18:15.000000000 +0000 @@ -57,11 +57,11 @@ * For every successful iteration, pGpuItr will point to the GPU being looped over. * After all the iterations are complete, pGpuItr will be NULL. */ -#define GPUBOOSTMGR_ITR_START(pBoostMgr, grpId, pGpuItr) \ -{ \ - NvU32 itrIdx = 0; \ - NV_ASSERT(NULL != (pBoostMgr)); \ - while (NULL != ((pGpuItr) = gpuboostmgrGpuItr((pBoostMgr), (grpId), &(itrIdx)))) \ +#define GPUBOOSTMGR_ITR_START(pBoostMgr, grpId, pGpuItr) \ +{ \ + NvU32 itrIdx = 0; \ + NV_ASSERT(NULL != (pBoostMgr)); \ + while (NULL != ((pGpuItr) = gpuboostmgrGpuItr((pBoostMgr), (grpId), &(itrIdx)))) \ { #define GPUBOOSTMGR_ITR_END \ diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/generated/g_gpu_class_list.c nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_gpu_class_list.c --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/generated/g_gpu_class_list.c 2023-10-25 20:19:28.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_gpu_class_list.c 2024-03-05 22:11:19.000000000 +0000 @@ -39,6 +39,7 @@ { G84_PERFBUFFER, ENG_BUS }, { GF100_DISP_SW, ENG_SW }, { GF100_HDACODEC, ENG_HDACODEC }, + { GF100_SUBDEVICE_INFOROM, ENG_GPU }, { GF100_SUBDEVICE_MASTER, ENG_GPU }, { GF100_TIMED_SEMAPHORE_SW, ENG_SW }, { GF100_ZBC_CLEAR, ENG_KERNEL_MEMORY_SYSTEM }, @@ -103,6 +104,7 @@ { G84_PERFBUFFER, ENG_BUS }, { GF100_DISP_SW, ENG_SW }, { GF100_HDACODEC, ENG_HDACODEC }, + { GF100_SUBDEVICE_INFOROM, ENG_GPU }, { GF100_SUBDEVICE_MASTER, ENG_GPU }, { GF100_TIMED_SEMAPHORE_SW, ENG_SW }, { GF100_ZBC_CLEAR, ENG_KERNEL_MEMORY_SYSTEM }, @@ -168,6 +170,7 @@ { G84_PERFBUFFER, ENG_BUS }, { GF100_DISP_SW, ENG_SW }, { GF100_HDACODEC, ENG_HDACODEC }, + { GF100_SUBDEVICE_INFOROM, ENG_GPU }, { GF100_SUBDEVICE_MASTER, ENG_GPU }, { GF100_TIMED_SEMAPHORE_SW, ENG_SW }, { GF100_ZBC_CLEAR, ENG_KERNEL_MEMORY_SYSTEM }, @@ -234,6 +237,7 @@ { G84_PERFBUFFER, ENG_BUS }, { GF100_DISP_SW, ENG_SW }, { GF100_HDACODEC, ENG_HDACODEC }, + { GF100_SUBDEVICE_INFOROM, ENG_GPU }, { GF100_SUBDEVICE_MASTER, ENG_GPU }, { GF100_TIMED_SEMAPHORE_SW, ENG_SW }, { GF100_ZBC_CLEAR, ENG_KERNEL_MEMORY_SYSTEM }, @@ -298,6 +302,7 @@ { G84_PERFBUFFER, ENG_BUS }, { GF100_DISP_SW, ENG_SW }, { GF100_HDACODEC, ENG_HDACODEC }, + { GF100_SUBDEVICE_INFOROM, ENG_GPU }, { GF100_SUBDEVICE_MASTER, ENG_GPU }, { GF100_TIMED_SEMAPHORE_SW, ENG_SW }, { GF100_ZBC_CLEAR, ENG_KERNEL_MEMORY_SYSTEM }, @@ -381,6 +386,7 @@ { FERMI_TWOD_A, ENG_GR(0) }, { FERMI_VASPACE_A, ENG_DMA }, { G84_PERFBUFFER, ENG_BUS }, + { GF100_SUBDEVICE_INFOROM, ENG_GPU }, { GF100_SUBDEVICE_MASTER, ENG_GPU }, { GF100_TIMED_SEMAPHORE_SW, ENG_SW }, { GF100_ZBC_CLEAR, ENG_KERNEL_MEMORY_SYSTEM }, @@ -404,6 +410,7 @@ { NVC6B0_VIDEO_DECODER, ENG_NVDEC(3) }, { NVC6B0_VIDEO_DECODER, ENG_NVDEC(4) }, { NVC6FA_VIDEO_OFA, ENG_OFA }, + { NV_CONFIDENTIAL_COMPUTE, ENG_CONF_COMPUTE }, { RM_USER_SHARED_DATA, ENG_GPU }, { TURING_CHANNEL_GPFIFO_A, ENG_KERNEL_FIFO }, { TURING_USERMODE_A, ENG_GPU }, @@ -443,6 +450,7 @@ { G84_PERFBUFFER, ENG_BUS }, { GF100_DISP_SW, ENG_SW }, { GF100_HDACODEC, ENG_HDACODEC }, + { GF100_SUBDEVICE_INFOROM, ENG_GPU }, { GF100_SUBDEVICE_MASTER, ENG_GPU }, { GF100_TIMED_SEMAPHORE_SW, ENG_SW }, { GF100_ZBC_CLEAR, ENG_KERNEL_MEMORY_SYSTEM }, @@ -473,6 +481,7 @@ { NVC7B0_VIDEO_DECODER, ENG_NVDEC(1) }, { NVC7B7_VIDEO_ENCODER, ENG_MSENC(0) }, { NVC7FA_VIDEO_OFA, ENG_OFA }, + { NV_CONFIDENTIAL_COMPUTE, ENG_CONF_COMPUTE }, { RM_USER_SHARED_DATA, ENG_GPU }, { TURING_CHANNEL_GPFIFO_A, ENG_KERNEL_FIFO }, { TURING_USERMODE_A, ENG_GPU }, @@ -512,6 +521,7 @@ { G84_PERFBUFFER, ENG_BUS }, { GF100_DISP_SW, ENG_SW }, { GF100_HDACODEC, ENG_HDACODEC }, + { GF100_SUBDEVICE_INFOROM, ENG_GPU }, { GF100_SUBDEVICE_MASTER, ENG_GPU }, { GF100_TIMED_SEMAPHORE_SW, ENG_SW }, { GF100_ZBC_CLEAR, ENG_KERNEL_MEMORY_SYSTEM }, @@ -542,6 +552,7 @@ { NVC7B0_VIDEO_DECODER, ENG_NVDEC(1) }, { NVC7B7_VIDEO_ENCODER, ENG_MSENC(0) }, { NVC7FA_VIDEO_OFA, ENG_OFA }, + { NV_CONFIDENTIAL_COMPUTE, ENG_CONF_COMPUTE }, { RM_USER_SHARED_DATA, ENG_GPU }, { TURING_CHANNEL_GPFIFO_A, ENG_KERNEL_FIFO }, { TURING_USERMODE_A, ENG_GPU }, @@ -581,6 +592,7 @@ { G84_PERFBUFFER, ENG_BUS }, { GF100_DISP_SW, ENG_SW }, { GF100_HDACODEC, ENG_HDACODEC }, + { GF100_SUBDEVICE_INFOROM, ENG_GPU }, { GF100_SUBDEVICE_MASTER, ENG_GPU }, { GF100_TIMED_SEMAPHORE_SW, ENG_SW }, { GF100_ZBC_CLEAR, ENG_KERNEL_MEMORY_SYSTEM }, @@ -611,6 +623,7 @@ { NVC7B0_VIDEO_DECODER, ENG_NVDEC(1) }, { NVC7B7_VIDEO_ENCODER, ENG_MSENC(0) }, { NVC7FA_VIDEO_OFA, ENG_OFA }, + { NV_CONFIDENTIAL_COMPUTE, ENG_CONF_COMPUTE }, { RM_USER_SHARED_DATA, ENG_GPU }, { TURING_CHANNEL_GPFIFO_A, ENG_KERNEL_FIFO }, { TURING_USERMODE_A, ENG_GPU }, @@ -650,6 +663,7 @@ { G84_PERFBUFFER, ENG_BUS }, { GF100_DISP_SW, ENG_SW }, { GF100_HDACODEC, ENG_HDACODEC }, + { GF100_SUBDEVICE_INFOROM, ENG_GPU }, { GF100_SUBDEVICE_MASTER, ENG_GPU }, { GF100_TIMED_SEMAPHORE_SW, ENG_SW }, { GF100_ZBC_CLEAR, ENG_KERNEL_MEMORY_SYSTEM }, @@ -680,6 +694,7 @@ { NVC7B0_VIDEO_DECODER, ENG_NVDEC(1) }, { NVC7B7_VIDEO_ENCODER, ENG_MSENC(0) }, { NVC7FA_VIDEO_OFA, ENG_OFA }, + { NV_CONFIDENTIAL_COMPUTE, ENG_CONF_COMPUTE }, { RM_USER_SHARED_DATA, ENG_GPU }, { TURING_CHANNEL_GPFIFO_A, ENG_KERNEL_FIFO }, { TURING_USERMODE_A, ENG_GPU }, @@ -719,6 +734,7 @@ { G84_PERFBUFFER, ENG_BUS }, { GF100_DISP_SW, ENG_SW }, { GF100_HDACODEC, ENG_HDACODEC }, + { GF100_SUBDEVICE_INFOROM, ENG_GPU }, { GF100_SUBDEVICE_MASTER, ENG_GPU }, { GF100_TIMED_SEMAPHORE_SW, ENG_SW }, { GF100_ZBC_CLEAR, ENG_KERNEL_MEMORY_SYSTEM }, @@ -749,6 +765,7 @@ { NVC7B0_VIDEO_DECODER, ENG_NVDEC(1) }, { NVC7B7_VIDEO_ENCODER, ENG_MSENC(0) }, { NVC7FA_VIDEO_OFA, ENG_OFA }, + { NV_CONFIDENTIAL_COMPUTE, ENG_CONF_COMPUTE }, { RM_USER_SHARED_DATA, ENG_GPU }, { TURING_CHANNEL_GPFIFO_A, ENG_KERNEL_FIFO }, { TURING_USERMODE_A, ENG_GPU }, @@ -788,6 +805,7 @@ { G84_PERFBUFFER, ENG_BUS }, { GF100_DISP_SW, ENG_SW }, { GF100_HDACODEC, ENG_HDACODEC }, + { GF100_SUBDEVICE_INFOROM, ENG_GPU }, { GF100_SUBDEVICE_MASTER, ENG_GPU }, { GF100_TIMED_SEMAPHORE_SW, ENG_SW }, { GF100_ZBC_CLEAR, ENG_KERNEL_MEMORY_SYSTEM }, @@ -826,6 +844,7 @@ { NVC9D1_VIDEO_NVJPG, ENG_NVJPEG(2) }, { NVC9D1_VIDEO_NVJPG, ENG_NVJPEG(3) }, { NVC9FA_VIDEO_OFA, ENG_OFA }, + { NV_CONFIDENTIAL_COMPUTE, ENG_CONF_COMPUTE }, { RM_USER_SHARED_DATA, ENG_GPU }, { TURING_CHANNEL_GPFIFO_A, ENG_KERNEL_FIFO }, { TURING_USERMODE_A, ENG_GPU }, @@ -865,6 +884,7 @@ { G84_PERFBUFFER, ENG_BUS }, { GF100_DISP_SW, ENG_SW }, { GF100_HDACODEC, ENG_HDACODEC }, + { GF100_SUBDEVICE_INFOROM, ENG_GPU }, { GF100_SUBDEVICE_MASTER, ENG_GPU }, { GF100_TIMED_SEMAPHORE_SW, ENG_SW }, { GF100_ZBC_CLEAR, ENG_KERNEL_MEMORY_SYSTEM }, @@ -903,6 +923,7 @@ { NVC9D1_VIDEO_NVJPG, ENG_NVJPEG(2) }, { NVC9D1_VIDEO_NVJPG, ENG_NVJPEG(3) }, { NVC9FA_VIDEO_OFA, ENG_OFA }, + { NV_CONFIDENTIAL_COMPUTE, ENG_CONF_COMPUTE }, { RM_USER_SHARED_DATA, ENG_GPU }, { TURING_CHANNEL_GPFIFO_A, ENG_KERNEL_FIFO }, { TURING_USERMODE_A, ENG_GPU }, @@ -942,6 +963,7 @@ { G84_PERFBUFFER, ENG_BUS }, { GF100_DISP_SW, ENG_SW }, { GF100_HDACODEC, ENG_HDACODEC }, + { GF100_SUBDEVICE_INFOROM, ENG_GPU }, { GF100_SUBDEVICE_MASTER, ENG_GPU }, { GF100_TIMED_SEMAPHORE_SW, ENG_SW }, { GF100_ZBC_CLEAR, ENG_KERNEL_MEMORY_SYSTEM }, @@ -980,6 +1002,7 @@ { NVC9D1_VIDEO_NVJPG, ENG_NVJPEG(2) }, { NVC9D1_VIDEO_NVJPG, ENG_NVJPEG(3) }, { NVC9FA_VIDEO_OFA, ENG_OFA }, + { NV_CONFIDENTIAL_COMPUTE, ENG_CONF_COMPUTE }, { RM_USER_SHARED_DATA, ENG_GPU }, { TURING_CHANNEL_GPFIFO_A, ENG_KERNEL_FIFO }, { TURING_USERMODE_A, ENG_GPU }, @@ -1019,6 +1042,7 @@ { G84_PERFBUFFER, ENG_BUS }, { GF100_DISP_SW, ENG_SW }, { GF100_HDACODEC, ENG_HDACODEC }, + { GF100_SUBDEVICE_INFOROM, ENG_GPU }, { GF100_SUBDEVICE_MASTER, ENG_GPU }, { GF100_TIMED_SEMAPHORE_SW, ENG_SW }, { GF100_ZBC_CLEAR, ENG_KERNEL_MEMORY_SYSTEM }, @@ -1057,6 +1081,7 @@ { NVC9D1_VIDEO_NVJPG, ENG_NVJPEG(2) }, { NVC9D1_VIDEO_NVJPG, ENG_NVJPEG(3) }, { NVC9FA_VIDEO_OFA, ENG_OFA }, + { NV_CONFIDENTIAL_COMPUTE, ENG_CONF_COMPUTE }, { RM_USER_SHARED_DATA, ENG_GPU }, { TURING_CHANNEL_GPFIFO_A, ENG_KERNEL_FIFO }, { TURING_USERMODE_A, ENG_GPU }, @@ -1096,6 +1121,7 @@ { G84_PERFBUFFER, ENG_BUS }, { GF100_DISP_SW, ENG_SW }, { GF100_HDACODEC, ENG_HDACODEC }, + { GF100_SUBDEVICE_INFOROM, ENG_GPU }, { GF100_SUBDEVICE_MASTER, ENG_GPU }, { GF100_TIMED_SEMAPHORE_SW, ENG_SW }, { GF100_ZBC_CLEAR, ENG_KERNEL_MEMORY_SYSTEM }, @@ -1134,6 +1160,7 @@ { NVC9D1_VIDEO_NVJPG, ENG_NVJPEG(2) }, { NVC9D1_VIDEO_NVJPG, ENG_NVJPEG(3) }, { NVC9FA_VIDEO_OFA, ENG_OFA }, + { NV_CONFIDENTIAL_COMPUTE, ENG_CONF_COMPUTE }, { RM_USER_SHARED_DATA, ENG_GPU }, { TURING_CHANNEL_GPFIFO_A, ENG_KERNEL_FIFO }, { TURING_USERMODE_A, ENG_GPU }, @@ -1164,6 +1191,7 @@ { FERMI_TWOD_A, ENG_GR(0) }, { FERMI_VASPACE_A, ENG_DMA }, { G84_PERFBUFFER, ENG_BUS }, + { GF100_SUBDEVICE_INFOROM, ENG_GPU }, { GF100_SUBDEVICE_MASTER, ENG_GPU }, { GF100_TIMED_SEMAPHORE_SW, ENG_SW }, { GF100_ZBC_CLEAR, ENG_KERNEL_MEMORY_SYSTEM }, @@ -1188,6 +1216,7 @@ { HOPPER_DMA_COPY_A, ENG_CE(7) }, { HOPPER_DMA_COPY_A, ENG_CE(8) }, { HOPPER_DMA_COPY_A, ENG_CE(9) }, + { HOPPER_SEC2_WORK_LAUNCH_A, ENG_SEC2 }, { HOPPER_USERMODE_A, ENG_GPU }, { KEPLER_CHANNEL_GROUP_A, ENG_KERNEL_FIFO }, { KEPLER_INLINE_TO_MEMORY_B, ENG_GR(0) }, @@ -1218,6 +1247,7 @@ { NVB8D1_VIDEO_NVJPG, ENG_NVJPEG(6) }, { NVB8D1_VIDEO_NVJPG, ENG_NVJPEG(7) }, { NVB8FA_VIDEO_OFA, ENG_OFA }, + { NV_CONFIDENTIAL_COMPUTE, ENG_CONF_COMPUTE }, { RM_USER_SHARED_DATA, ENG_GPU }, { TURING_CHANNEL_GPFIFO_A, ENG_KERNEL_FIFO }, { TURING_USERMODE_A, ENG_GPU }, diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/generated/g_gpu_db_nvoc.c nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_gpu_db_nvoc.c --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/generated/g_gpu_db_nvoc.c 2023-10-25 20:26:58.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_gpu_db_nvoc.c 2024-03-05 22:18:15.000000000 +0000 @@ -114,13 +114,16 @@ Object *pParentObj; GpuDb *pThis; - pThis = portMemAllocNonPaged(sizeof(GpuDb)); - if (pThis == NULL) return NV_ERR_NO_MEMORY; + status = __nvoc_handleObjCreateMemAlloc(createFlags, sizeof(GpuDb), (void**)&pThis, (void**)ppThis); + if (status != NV_OK) + return status; portMemSet(pThis, 0, sizeof(GpuDb)); __nvoc_initRtti(staticCast(pThis, Dynamic), &__nvoc_class_def_GpuDb); + pThis->__nvoc_base_Object.createFlags = createFlags; + if (pParent != NULL && !(createFlags & NVOC_OBJ_CREATE_FLAGS_PARENT_HALSPEC_ONLY)) { pParentObj = dynamicCast(pParent, Object); @@ -136,11 +139,17 @@ if (status != NV_OK) goto __nvoc_objCreate_GpuDb_cleanup; *ppThis = pThis; + return NV_OK; __nvoc_objCreate_GpuDb_cleanup: // do not call destructors here since the constructor already called them - portMemFree(pThis); + if (createFlags & NVOC_OBJ_CREATE_FLAGS_IN_PLACE_CONSTRUCT) + portMemSet(pThis, 0, sizeof(GpuDb)); + else + portMemFree(pThis); + + // coverity[leaked_storage:FALSE] return status; } diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/generated/g_gpu_group_nvoc.c nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_gpu_group_nvoc.c --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/generated/g_gpu_group_nvoc.c 2023-10-25 20:26:58.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_gpu_group_nvoc.c 2024-03-05 22:18:15.000000000 +0000 @@ -108,13 +108,16 @@ Object *pParentObj; OBJGPUGRP *pThis; - pThis = portMemAllocNonPaged(sizeof(OBJGPUGRP)); - if (pThis == NULL) return NV_ERR_NO_MEMORY; + status = __nvoc_handleObjCreateMemAlloc(createFlags, sizeof(OBJGPUGRP), (void**)&pThis, (void**)ppThis); + if (status != NV_OK) + return status; portMemSet(pThis, 0, sizeof(OBJGPUGRP)); __nvoc_initRtti(staticCast(pThis, Dynamic), &__nvoc_class_def_OBJGPUGRP); + pThis->__nvoc_base_Object.createFlags = createFlags; + if (pParent != NULL && !(createFlags & NVOC_OBJ_CREATE_FLAGS_PARENT_HALSPEC_ONLY)) { pParentObj = dynamicCast(pParent, Object); @@ -130,11 +133,17 @@ if (status != NV_OK) goto __nvoc_objCreate_OBJGPUGRP_cleanup; *ppThis = pThis; + return NV_OK; __nvoc_objCreate_OBJGPUGRP_cleanup: // do not call destructors here since the constructor already called them - portMemFree(pThis); + if (createFlags & NVOC_OBJ_CREATE_FLAGS_IN_PLACE_CONSTRUCT) + portMemSet(pThis, 0, sizeof(OBJGPUGRP)); + else + portMemFree(pThis); + + // coverity[leaked_storage:FALSE] return status; } diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/generated/g_gpu_group_nvoc.h nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_gpu_group_nvoc.h --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/generated/g_gpu_group_nvoc.h 2023-10-25 20:26:58.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_gpu_group_nvoc.h 2024-03-05 22:18:15.000000000 +0000 @@ -85,19 +85,19 @@ bOrigBcState = gpumgrGetBcEnabledStatus(pGpu); \ gpumgrSetBcEnabledStatus(pGpu, NV_FALSE); \ -#define FOR_EACH_GPU_IN_MASK_UC_END \ - } \ - FOR_EACH_INDEX_IN_MASK_END \ - if (NULL != pGpu) /* break */ \ - { \ - gpumgrSetBcEnabledStatus(pGpu, bOrigBcState); \ - pGpu = NULL; \ - } \ - if (pEntryGpu != NULL) \ - { \ - NV_ASSERT(bEntryBcState == gpumgrGetBcEnabledStatus(pEntryGpu));\ - pGpu = pEntryGpu; \ - } \ +#define FOR_EACH_GPU_IN_MASK_UC_END \ + } \ + FOR_EACH_INDEX_IN_MASK_END \ + if (NULL != pGpu) /* break */ \ + { \ + gpumgrSetBcEnabledStatus(pGpu, bOrigBcState); \ + pGpu = NULL; \ + } \ + if (pEntryGpu != NULL) \ + { \ + NV_ASSERT(bEntryBcState == gpumgrGetBcEnabledStatus(pEntryGpu)); \ + pGpu = pEntryGpu; \ + } \ } typedef struct _def_vid_link_node diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/generated/g_gpu_instance_subscription_nvoc.c nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_gpu_instance_subscription_nvoc.c --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/generated/g_gpu_instance_subscription_nvoc.c 2023-10-25 20:26:58.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_gpu_instance_subscription_nvoc.c 2024-03-05 22:18:15.000000000 +0000 @@ -101,48 +101,24 @@ return gpuresShareCallback((struct GpuResource *)(((unsigned char *)pGpuResource) + __nvoc_rtti_GPUInstanceSubscription_GpuResource.offset), pInvokingClient, pParentRef, pSharePolicy); } -static NV_STATUS __nvoc_thunk_GpuResource_gisubscriptionControl(struct GPUInstanceSubscription *pGpuResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { - return gpuresControl((struct GpuResource *)(((unsigned char *)pGpuResource) + __nvoc_rtti_GPUInstanceSubscription_GpuResource.offset), pCallContext, pParams); -} - -static NV_STATUS __nvoc_thunk_GpuResource_gisubscriptionUnmap(struct GPUInstanceSubscription *pGpuResource, struct CALL_CONTEXT *pCallContext, struct RsCpuMapping *pCpuMapping) { - return gpuresUnmap((struct GpuResource *)(((unsigned char *)pGpuResource) + __nvoc_rtti_GPUInstanceSubscription_GpuResource.offset), pCallContext, pCpuMapping); -} - -static NV_STATUS __nvoc_thunk_RmResource_gisubscriptionGetMemInterMapParams(struct GPUInstanceSubscription *pRmResource, RMRES_MEM_INTER_MAP_PARAMS *pParams) { - return rmresGetMemInterMapParams((struct RmResource *)(((unsigned char *)pRmResource) + __nvoc_rtti_GPUInstanceSubscription_RmResource.offset), pParams); +static NV_STATUS __nvoc_thunk_RmResource_gisubscriptionCheckMemInterUnmap(struct GPUInstanceSubscription *pRmResource, NvBool bSubdeviceHandleProvided) { + return rmresCheckMemInterUnmap((struct RmResource *)(((unsigned char *)pRmResource) + __nvoc_rtti_GPUInstanceSubscription_RmResource.offset), bSubdeviceHandleProvided); } -static NV_STATUS __nvoc_thunk_RmResource_gisubscriptionGetMemoryMappingDescriptor(struct GPUInstanceSubscription *pRmResource, struct MEMORY_DESCRIPTOR **ppMemDesc) { - return rmresGetMemoryMappingDescriptor((struct RmResource *)(((unsigned char *)pRmResource) + __nvoc_rtti_GPUInstanceSubscription_RmResource.offset), ppMemDesc); +static NV_STATUS __nvoc_thunk_RsResource_gisubscriptionMapTo(struct GPUInstanceSubscription *pResource, RS_RES_MAP_TO_PARAMS *pParams) { + return resMapTo((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_GPUInstanceSubscription_RsResource.offset), pParams); } static NV_STATUS __nvoc_thunk_GpuResource_gisubscriptionGetMapAddrSpace(struct GPUInstanceSubscription *pGpuResource, struct CALL_CONTEXT *pCallContext, NvU32 mapFlags, NV_ADDRESS_SPACE *pAddrSpace) { return gpuresGetMapAddrSpace((struct GpuResource *)(((unsigned char *)pGpuResource) + __nvoc_rtti_GPUInstanceSubscription_GpuResource.offset), pCallContext, mapFlags, pAddrSpace); } -static NvHandle __nvoc_thunk_GpuResource_gisubscriptionGetInternalObjectHandle(struct GPUInstanceSubscription *pGpuResource) { - return gpuresGetInternalObjectHandle((struct GpuResource *)(((unsigned char *)pGpuResource) + __nvoc_rtti_GPUInstanceSubscription_GpuResource.offset)); -} - -static NV_STATUS __nvoc_thunk_RsResource_gisubscriptionControlFilter(struct GPUInstanceSubscription *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { - return resControlFilter((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_GPUInstanceSubscription_RsResource.offset), pCallContext, pParams); -} - -static void __nvoc_thunk_RsResource_gisubscriptionAddAdditionalDependants(struct RsClient *pClient, struct GPUInstanceSubscription *pResource, RsResourceRef *pReference) { - resAddAdditionalDependants(pClient, (struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_GPUInstanceSubscription_RsResource.offset), pReference); -} - static NvU32 __nvoc_thunk_RsResource_gisubscriptionGetRefCount(struct GPUInstanceSubscription *pResource) { return resGetRefCount((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_GPUInstanceSubscription_RsResource.offset)); } -static NV_STATUS __nvoc_thunk_RmResource_gisubscriptionCheckMemInterUnmap(struct GPUInstanceSubscription *pRmResource, NvBool bSubdeviceHandleProvided) { - return rmresCheckMemInterUnmap((struct RmResource *)(((unsigned char *)pRmResource) + __nvoc_rtti_GPUInstanceSubscription_RmResource.offset), bSubdeviceHandleProvided); -} - -static NV_STATUS __nvoc_thunk_RsResource_gisubscriptionMapTo(struct GPUInstanceSubscription *pResource, RS_RES_MAP_TO_PARAMS *pParams) { - return resMapTo((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_GPUInstanceSubscription_RsResource.offset), pParams); +static void __nvoc_thunk_RsResource_gisubscriptionAddAdditionalDependants(struct RsClient *pClient, struct GPUInstanceSubscription *pResource, RsResourceRef *pReference) { + resAddAdditionalDependants(pClient, (struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_GPUInstanceSubscription_RsResource.offset), pReference); } static NV_STATUS __nvoc_thunk_RmResource_gisubscriptionControl_Prologue(struct GPUInstanceSubscription *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { @@ -157,18 +133,10 @@ return gpuresInternalControlForward((struct GpuResource *)(((unsigned char *)pGpuResource) + __nvoc_rtti_GPUInstanceSubscription_GpuResource.offset), command, pParams, size); } -static void __nvoc_thunk_RsResource_gisubscriptionPreDestruct(struct GPUInstanceSubscription *pResource) { - resPreDestruct((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_GPUInstanceSubscription_RsResource.offset)); -} - static NV_STATUS __nvoc_thunk_RsResource_gisubscriptionUnmapFrom(struct GPUInstanceSubscription *pResource, RS_RES_UNMAP_FROM_PARAMS *pParams) { return resUnmapFrom((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_GPUInstanceSubscription_RsResource.offset), pParams); } -static NV_STATUS __nvoc_thunk_RsResource_gisubscriptionIsDuplicate(struct GPUInstanceSubscription *pResource, NvHandle hMemory, NvBool *pDuplicate) { - return resIsDuplicate((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_GPUInstanceSubscription_RsResource.offset), hMemory, pDuplicate); -} - static void __nvoc_thunk_RmResource_gisubscriptionControl_Epilogue(struct GPUInstanceSubscription *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { rmresControl_Epilogue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_GPUInstanceSubscription_RmResource.offset), pCallContext, pParams); } @@ -177,6 +145,46 @@ return resControlLookup((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_GPUInstanceSubscription_RsResource.offset), pParams, ppEntry); } +static NvHandle __nvoc_thunk_GpuResource_gisubscriptionGetInternalObjectHandle(struct GPUInstanceSubscription *pGpuResource) { + return gpuresGetInternalObjectHandle((struct GpuResource *)(((unsigned char *)pGpuResource) + __nvoc_rtti_GPUInstanceSubscription_GpuResource.offset)); +} + +static NV_STATUS __nvoc_thunk_GpuResource_gisubscriptionControl(struct GPUInstanceSubscription *pGpuResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return gpuresControl((struct GpuResource *)(((unsigned char *)pGpuResource) + __nvoc_rtti_GPUInstanceSubscription_GpuResource.offset), pCallContext, pParams); +} + +static NV_STATUS __nvoc_thunk_GpuResource_gisubscriptionUnmap(struct GPUInstanceSubscription *pGpuResource, struct CALL_CONTEXT *pCallContext, struct RsCpuMapping *pCpuMapping) { + return gpuresUnmap((struct GpuResource *)(((unsigned char *)pGpuResource) + __nvoc_rtti_GPUInstanceSubscription_GpuResource.offset), pCallContext, pCpuMapping); +} + +static NV_STATUS __nvoc_thunk_RmResource_gisubscriptionGetMemInterMapParams(struct GPUInstanceSubscription *pRmResource, RMRES_MEM_INTER_MAP_PARAMS *pParams) { + return rmresGetMemInterMapParams((struct RmResource *)(((unsigned char *)pRmResource) + __nvoc_rtti_GPUInstanceSubscription_RmResource.offset), pParams); +} + +static NV_STATUS __nvoc_thunk_RmResource_gisubscriptionGetMemoryMappingDescriptor(struct GPUInstanceSubscription *pRmResource, struct MEMORY_DESCRIPTOR **ppMemDesc) { + return rmresGetMemoryMappingDescriptor((struct RmResource *)(((unsigned char *)pRmResource) + __nvoc_rtti_GPUInstanceSubscription_RmResource.offset), ppMemDesc); +} + +static NV_STATUS __nvoc_thunk_RsResource_gisubscriptionControlFilter(struct GPUInstanceSubscription *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return resControlFilter((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_GPUInstanceSubscription_RsResource.offset), pCallContext, pParams); +} + +static NV_STATUS __nvoc_thunk_RmResource_gisubscriptionControlSerialization_Prologue(struct GPUInstanceSubscription *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return rmresControlSerialization_Prologue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_GPUInstanceSubscription_RmResource.offset), pCallContext, pParams); +} + +static void __nvoc_thunk_RsResource_gisubscriptionPreDestruct(struct GPUInstanceSubscription *pResource) { + resPreDestruct((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_GPUInstanceSubscription_RsResource.offset)); +} + +static NV_STATUS __nvoc_thunk_RsResource_gisubscriptionIsDuplicate(struct GPUInstanceSubscription *pResource, NvHandle hMemory, NvBool *pDuplicate) { + return resIsDuplicate((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_GPUInstanceSubscription_RsResource.offset), hMemory, pDuplicate); +} + +static void __nvoc_thunk_RmResource_gisubscriptionControlSerialization_Epilogue(struct GPUInstanceSubscription *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + rmresControlSerialization_Epilogue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_GPUInstanceSubscription_RmResource.offset), pCallContext, pParams); +} + static NV_STATUS __nvoc_thunk_GpuResource_gisubscriptionMap(struct GPUInstanceSubscription *pGpuResource, struct CALL_CONTEXT *pCallContext, struct RS_CPU_MAP_PARAMS *pParams, struct RsCpuMapping *pCpuMapping) { return gpuresMap((struct GpuResource *)(((unsigned char *)pGpuResource) + __nvoc_rtti_GPUInstanceSubscription_GpuResource.offset), pCallContext, pParams, pCpuMapping); } @@ -372,27 +380,15 @@ pThis->__gisubscriptionShareCallback__ = &__nvoc_thunk_GpuResource_gisubscriptionShareCallback; - pThis->__gisubscriptionControl__ = &__nvoc_thunk_GpuResource_gisubscriptionControl; - - pThis->__gisubscriptionUnmap__ = &__nvoc_thunk_GpuResource_gisubscriptionUnmap; - - pThis->__gisubscriptionGetMemInterMapParams__ = &__nvoc_thunk_RmResource_gisubscriptionGetMemInterMapParams; + pThis->__gisubscriptionCheckMemInterUnmap__ = &__nvoc_thunk_RmResource_gisubscriptionCheckMemInterUnmap; - pThis->__gisubscriptionGetMemoryMappingDescriptor__ = &__nvoc_thunk_RmResource_gisubscriptionGetMemoryMappingDescriptor; + pThis->__gisubscriptionMapTo__ = &__nvoc_thunk_RsResource_gisubscriptionMapTo; pThis->__gisubscriptionGetMapAddrSpace__ = &__nvoc_thunk_GpuResource_gisubscriptionGetMapAddrSpace; - pThis->__gisubscriptionGetInternalObjectHandle__ = &__nvoc_thunk_GpuResource_gisubscriptionGetInternalObjectHandle; - - pThis->__gisubscriptionControlFilter__ = &__nvoc_thunk_RsResource_gisubscriptionControlFilter; - - pThis->__gisubscriptionAddAdditionalDependants__ = &__nvoc_thunk_RsResource_gisubscriptionAddAdditionalDependants; - pThis->__gisubscriptionGetRefCount__ = &__nvoc_thunk_RsResource_gisubscriptionGetRefCount; - pThis->__gisubscriptionCheckMemInterUnmap__ = &__nvoc_thunk_RmResource_gisubscriptionCheckMemInterUnmap; - - pThis->__gisubscriptionMapTo__ = &__nvoc_thunk_RsResource_gisubscriptionMapTo; + pThis->__gisubscriptionAddAdditionalDependants__ = &__nvoc_thunk_RsResource_gisubscriptionAddAdditionalDependants; pThis->__gisubscriptionControl_Prologue__ = &__nvoc_thunk_RmResource_gisubscriptionControl_Prologue; @@ -400,16 +396,32 @@ pThis->__gisubscriptionInternalControlForward__ = &__nvoc_thunk_GpuResource_gisubscriptionInternalControlForward; - pThis->__gisubscriptionPreDestruct__ = &__nvoc_thunk_RsResource_gisubscriptionPreDestruct; - pThis->__gisubscriptionUnmapFrom__ = &__nvoc_thunk_RsResource_gisubscriptionUnmapFrom; - pThis->__gisubscriptionIsDuplicate__ = &__nvoc_thunk_RsResource_gisubscriptionIsDuplicate; - pThis->__gisubscriptionControl_Epilogue__ = &__nvoc_thunk_RmResource_gisubscriptionControl_Epilogue; pThis->__gisubscriptionControlLookup__ = &__nvoc_thunk_RsResource_gisubscriptionControlLookup; + pThis->__gisubscriptionGetInternalObjectHandle__ = &__nvoc_thunk_GpuResource_gisubscriptionGetInternalObjectHandle; + + pThis->__gisubscriptionControl__ = &__nvoc_thunk_GpuResource_gisubscriptionControl; + + pThis->__gisubscriptionUnmap__ = &__nvoc_thunk_GpuResource_gisubscriptionUnmap; + + pThis->__gisubscriptionGetMemInterMapParams__ = &__nvoc_thunk_RmResource_gisubscriptionGetMemInterMapParams; + + pThis->__gisubscriptionGetMemoryMappingDescriptor__ = &__nvoc_thunk_RmResource_gisubscriptionGetMemoryMappingDescriptor; + + pThis->__gisubscriptionControlFilter__ = &__nvoc_thunk_RsResource_gisubscriptionControlFilter; + + pThis->__gisubscriptionControlSerialization_Prologue__ = &__nvoc_thunk_RmResource_gisubscriptionControlSerialization_Prologue; + + pThis->__gisubscriptionPreDestruct__ = &__nvoc_thunk_RsResource_gisubscriptionPreDestruct; + + pThis->__gisubscriptionIsDuplicate__ = &__nvoc_thunk_RsResource_gisubscriptionIsDuplicate; + + pThis->__gisubscriptionControlSerialization_Epilogue__ = &__nvoc_thunk_RmResource_gisubscriptionControlSerialization_Epilogue; + pThis->__gisubscriptionMap__ = &__nvoc_thunk_GpuResource_gisubscriptionMap; pThis->__gisubscriptionAccessCallback__ = &__nvoc_thunk_RmResource_gisubscriptionAccessCallback; @@ -436,13 +448,16 @@ Object *pParentObj; GPUInstanceSubscription *pThis; - pThis = portMemAllocNonPaged(sizeof(GPUInstanceSubscription)); - if (pThis == NULL) return NV_ERR_NO_MEMORY; + status = __nvoc_handleObjCreateMemAlloc(createFlags, sizeof(GPUInstanceSubscription), (void**)&pThis, (void**)ppThis); + if (status != NV_OK) + return status; portMemSet(pThis, 0, sizeof(GPUInstanceSubscription)); __nvoc_initRtti(staticCast(pThis, Dynamic), &__nvoc_class_def_GPUInstanceSubscription); + pThis->__nvoc_base_GpuResource.__nvoc_base_RmResource.__nvoc_base_RsResource.__nvoc_base_Object.createFlags = createFlags; + if (pParent != NULL && !(createFlags & NVOC_OBJ_CREATE_FLAGS_PARENT_HALSPEC_ONLY)) { pParentObj = dynamicCast(pParent, Object); @@ -458,11 +473,17 @@ if (status != NV_OK) goto __nvoc_objCreate_GPUInstanceSubscription_cleanup; *ppThis = pThis; + return NV_OK; __nvoc_objCreate_GPUInstanceSubscription_cleanup: // do not call destructors here since the constructor already called them - portMemFree(pThis); + if (createFlags & NVOC_OBJ_CREATE_FLAGS_IN_PLACE_CONSTRUCT) + portMemSet(pThis, 0, sizeof(GPUInstanceSubscription)); + else + portMemFree(pThis); + + // coverity[leaked_storage:FALSE] return status; } diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/generated/g_gpu_instance_subscription_nvoc.h nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_gpu_instance_subscription_nvoc.h --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/generated/g_gpu_instance_subscription_nvoc.h 2023-10-25 20:26:58.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_gpu_instance_subscription_nvoc.h 2024-03-05 22:18:15.000000000 +0000 @@ -7,7 +7,7 @@ #endif /* - * SPDX-FileCopyrightText: Copyright (c) 2018-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2018-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -72,25 +72,73 @@ NV_STATUS (*__gisubscriptionCtrlCmdExecPartitionsExport__)(struct GPUInstanceSubscription *, NVC637_CTRL_EXEC_PARTITIONS_IMPORT_EXPORT_PARAMS *); NV_STATUS (*__gisubscriptionCtrlCmdExecPartitionsImport__)(struct GPUInstanceSubscription *, NVC637_CTRL_EXEC_PARTITIONS_IMPORT_EXPORT_PARAMS *); NvBool (*__gisubscriptionShareCallback__)(struct GPUInstanceSubscription *, struct RsClient *, struct RsResourceRef *, RS_SHARE_POLICY *); + NV_STATUS (*__gisubscriptionCheckMemInterUnmap__)(struct GPUInstanceSubscription *, NvBool); + NV_STATUS (*__gisubscriptionMapTo__)(struct GPUInstanceSubscription *, RS_RES_MAP_TO_PARAMS *); + NV_STATUS (*__gisubscriptionGetMapAddrSpace__)(struct GPUInstanceSubscription *, struct CALL_CONTEXT *, NvU32, NV_ADDRESS_SPACE *); + NvU32 (*__gisubscriptionGetRefCount__)(struct GPUInstanceSubscription *); + void (*__gisubscriptionAddAdditionalDependants__)(struct RsClient *, struct GPUInstanceSubscription *, RsResourceRef *); + NV_STATUS (*__gisubscriptionControl_Prologue__)(struct GPUInstanceSubscription *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); + NV_STATUS (*__gisubscriptionGetRegBaseOffsetAndSize__)(struct GPUInstanceSubscription *, struct OBJGPU *, NvU32 *, NvU32 *); + NV_STATUS (*__gisubscriptionInternalControlForward__)(struct GPUInstanceSubscription *, NvU32, void *, NvU32); + NV_STATUS (*__gisubscriptionUnmapFrom__)(struct GPUInstanceSubscription *, RS_RES_UNMAP_FROM_PARAMS *); + void (*__gisubscriptionControl_Epilogue__)(struct GPUInstanceSubscription *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); + NV_STATUS (*__gisubscriptionControlLookup__)(struct GPUInstanceSubscription *, struct RS_RES_CONTROL_PARAMS_INTERNAL *, const struct NVOC_EXPORTED_METHOD_DEF **); + NvHandle (*__gisubscriptionGetInternalObjectHandle__)(struct GPUInstanceSubscription *); NV_STATUS (*__gisubscriptionControl__)(struct GPUInstanceSubscription *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); NV_STATUS (*__gisubscriptionUnmap__)(struct GPUInstanceSubscription *, struct CALL_CONTEXT *, struct RsCpuMapping *); NV_STATUS (*__gisubscriptionGetMemInterMapParams__)(struct GPUInstanceSubscription *, RMRES_MEM_INTER_MAP_PARAMS *); NV_STATUS (*__gisubscriptionGetMemoryMappingDescriptor__)(struct GPUInstanceSubscription *, struct MEMORY_DESCRIPTOR **); - NV_STATUS (*__gisubscriptionGetMapAddrSpace__)(struct GPUInstanceSubscription *, struct CALL_CONTEXT *, NvU32, NV_ADDRESS_SPACE *); - NvHandle (*__gisubscriptionGetInternalObjectHandle__)(struct GPUInstanceSubscription *); NV_STATUS (*__gisubscriptionControlFilter__)(struct GPUInstanceSubscription *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); - void (*__gisubscriptionAddAdditionalDependants__)(struct RsClient *, struct GPUInstanceSubscription *, RsResourceRef *); - NvU32 (*__gisubscriptionGetRefCount__)(struct GPUInstanceSubscription *); + NV_STATUS (*__gisubscriptionControlSerialization_Prologue__)(struct GPUInstanceSubscription *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); + void (*__gisubscriptionPreDestruct__)(struct GPUInstanceSubscription *); + NV_STATUS (*__gisubscriptionIsDuplicate__)(struct GPUInstanceSubscription *, NvHandle, NvBool *); + void (*__gisubscriptionControlSerialization_Epilogue__)(struct GPUInstanceSubscription *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); + NV_STATUS (*__gisubscriptionMap__)(struct GPUInstanceSubscription *, struct CALL_CONTEXT *, struct RS_CPU_MAP_PARAMS *, struct RsCpuMapping *); + NvBool (*__gisubscriptionAccessCallback__)(struct GPUInstanceSubscription *, struct RsClient *, void *, RsAccessRight); + KERNEL_MIG_GPU_INSTANCE *PRIVATE_FIELD(pKernelMIGGpuInstance); + NvBool PRIVATE_FIELD(bDeviceProfiling); + NvBool PRIVATE_FIELD(bIsDuped); + NvU64 PRIVATE_FIELD(dupedCapDescriptor); +}; +struct GPUInstanceSubscription_PRIVATE { + const struct NVOC_RTTI *__nvoc_rtti; + struct GpuResource __nvoc_base_GpuResource; + struct Object *__nvoc_pbase_Object; + struct RsResource *__nvoc_pbase_RsResource; + struct RmResourceCommon *__nvoc_pbase_RmResourceCommon; + struct RmResource *__nvoc_pbase_RmResource; + struct GpuResource *__nvoc_pbase_GpuResource; + struct GPUInstanceSubscription *__nvoc_pbase_GPUInstanceSubscription; + NvBool (*__gisubscriptionCanCopy__)(struct GPUInstanceSubscription *); + NV_STATUS (*__gisubscriptionCtrlCmdExecPartitionsCreate__)(struct GPUInstanceSubscription *, NVC637_CTRL_EXEC_PARTITIONS_CREATE_PARAMS *); + NV_STATUS (*__gisubscriptionCtrlCmdExecPartitionsDelete__)(struct GPUInstanceSubscription *, NVC637_CTRL_EXEC_PARTITIONS_DELETE_PARAMS *); + NV_STATUS (*__gisubscriptionCtrlCmdExecPartitionsGet__)(struct GPUInstanceSubscription *, NVC637_CTRL_EXEC_PARTITIONS_GET_PARAMS *); + NV_STATUS (*__gisubscriptionCtrlCmdExecPartitionsGetProfileCapacity__)(struct GPUInstanceSubscription *, NVC637_CTRL_EXEC_PARTITIONS_GET_PROFILE_CAPACITY_PARAMS *); + NV_STATUS (*__gisubscriptionCtrlCmdExecPartitionsGetActiveIds__)(struct GPUInstanceSubscription *, NVC637_CTRL_EXEC_PARTITIONS_GET_ACTIVE_IDS_PARAMS *); + NV_STATUS (*__gisubscriptionCtrlCmdExecPartitionsExport__)(struct GPUInstanceSubscription *, NVC637_CTRL_EXEC_PARTITIONS_IMPORT_EXPORT_PARAMS *); + NV_STATUS (*__gisubscriptionCtrlCmdExecPartitionsImport__)(struct GPUInstanceSubscription *, NVC637_CTRL_EXEC_PARTITIONS_IMPORT_EXPORT_PARAMS *); + NvBool (*__gisubscriptionShareCallback__)(struct GPUInstanceSubscription *, struct RsClient *, struct RsResourceRef *, RS_SHARE_POLICY *); NV_STATUS (*__gisubscriptionCheckMemInterUnmap__)(struct GPUInstanceSubscription *, NvBool); NV_STATUS (*__gisubscriptionMapTo__)(struct GPUInstanceSubscription *, RS_RES_MAP_TO_PARAMS *); + NV_STATUS (*__gisubscriptionGetMapAddrSpace__)(struct GPUInstanceSubscription *, struct CALL_CONTEXT *, NvU32, NV_ADDRESS_SPACE *); + NvU32 (*__gisubscriptionGetRefCount__)(struct GPUInstanceSubscription *); + void (*__gisubscriptionAddAdditionalDependants__)(struct RsClient *, struct GPUInstanceSubscription *, RsResourceRef *); NV_STATUS (*__gisubscriptionControl_Prologue__)(struct GPUInstanceSubscription *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); NV_STATUS (*__gisubscriptionGetRegBaseOffsetAndSize__)(struct GPUInstanceSubscription *, struct OBJGPU *, NvU32 *, NvU32 *); NV_STATUS (*__gisubscriptionInternalControlForward__)(struct GPUInstanceSubscription *, NvU32, void *, NvU32); - void (*__gisubscriptionPreDestruct__)(struct GPUInstanceSubscription *); NV_STATUS (*__gisubscriptionUnmapFrom__)(struct GPUInstanceSubscription *, RS_RES_UNMAP_FROM_PARAMS *); - NV_STATUS (*__gisubscriptionIsDuplicate__)(struct GPUInstanceSubscription *, NvHandle, NvBool *); void (*__gisubscriptionControl_Epilogue__)(struct GPUInstanceSubscription *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); NV_STATUS (*__gisubscriptionControlLookup__)(struct GPUInstanceSubscription *, struct RS_RES_CONTROL_PARAMS_INTERNAL *, const struct NVOC_EXPORTED_METHOD_DEF **); + NvHandle (*__gisubscriptionGetInternalObjectHandle__)(struct GPUInstanceSubscription *); + NV_STATUS (*__gisubscriptionControl__)(struct GPUInstanceSubscription *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); + NV_STATUS (*__gisubscriptionUnmap__)(struct GPUInstanceSubscription *, struct CALL_CONTEXT *, struct RsCpuMapping *); + NV_STATUS (*__gisubscriptionGetMemInterMapParams__)(struct GPUInstanceSubscription *, RMRES_MEM_INTER_MAP_PARAMS *); + NV_STATUS (*__gisubscriptionGetMemoryMappingDescriptor__)(struct GPUInstanceSubscription *, struct MEMORY_DESCRIPTOR **); + NV_STATUS (*__gisubscriptionControlFilter__)(struct GPUInstanceSubscription *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); + NV_STATUS (*__gisubscriptionControlSerialization_Prologue__)(struct GPUInstanceSubscription *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); + void (*__gisubscriptionPreDestruct__)(struct GPUInstanceSubscription *); + NV_STATUS (*__gisubscriptionIsDuplicate__)(struct GPUInstanceSubscription *, NvHandle, NvBool *); + void (*__gisubscriptionControlSerialization_Epilogue__)(struct GPUInstanceSubscription *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); NV_STATUS (*__gisubscriptionMap__)(struct GPUInstanceSubscription *, struct CALL_CONTEXT *, struct RS_CPU_MAP_PARAMS *, struct RsCpuMapping *); NvBool (*__gisubscriptionAccessCallback__)(struct GPUInstanceSubscription *, struct RsClient *, void *, RsAccessRight); KERNEL_MIG_GPU_INSTANCE *pKernelMIGGpuInstance; @@ -136,25 +184,27 @@ #define gisubscriptionCtrlCmdExecPartitionsExport(arg0, arg1) gisubscriptionCtrlCmdExecPartitionsExport_DISPATCH(arg0, arg1) #define gisubscriptionCtrlCmdExecPartitionsImport(arg0, arg1) gisubscriptionCtrlCmdExecPartitionsImport_DISPATCH(arg0, arg1) #define gisubscriptionShareCallback(pGpuResource, pInvokingClient, pParentRef, pSharePolicy) gisubscriptionShareCallback_DISPATCH(pGpuResource, pInvokingClient, pParentRef, pSharePolicy) -#define gisubscriptionControl(pGpuResource, pCallContext, pParams) gisubscriptionControl_DISPATCH(pGpuResource, pCallContext, pParams) -#define gisubscriptionUnmap(pGpuResource, pCallContext, pCpuMapping) gisubscriptionUnmap_DISPATCH(pGpuResource, pCallContext, pCpuMapping) -#define gisubscriptionGetMemInterMapParams(pRmResource, pParams) gisubscriptionGetMemInterMapParams_DISPATCH(pRmResource, pParams) -#define gisubscriptionGetMemoryMappingDescriptor(pRmResource, ppMemDesc) gisubscriptionGetMemoryMappingDescriptor_DISPATCH(pRmResource, ppMemDesc) -#define gisubscriptionGetMapAddrSpace(pGpuResource, pCallContext, mapFlags, pAddrSpace) gisubscriptionGetMapAddrSpace_DISPATCH(pGpuResource, pCallContext, mapFlags, pAddrSpace) -#define gisubscriptionGetInternalObjectHandle(pGpuResource) gisubscriptionGetInternalObjectHandle_DISPATCH(pGpuResource) -#define gisubscriptionControlFilter(pResource, pCallContext, pParams) gisubscriptionControlFilter_DISPATCH(pResource, pCallContext, pParams) -#define gisubscriptionAddAdditionalDependants(pClient, pResource, pReference) gisubscriptionAddAdditionalDependants_DISPATCH(pClient, pResource, pReference) -#define gisubscriptionGetRefCount(pResource) gisubscriptionGetRefCount_DISPATCH(pResource) #define gisubscriptionCheckMemInterUnmap(pRmResource, bSubdeviceHandleProvided) gisubscriptionCheckMemInterUnmap_DISPATCH(pRmResource, bSubdeviceHandleProvided) #define gisubscriptionMapTo(pResource, pParams) gisubscriptionMapTo_DISPATCH(pResource, pParams) +#define gisubscriptionGetMapAddrSpace(pGpuResource, pCallContext, mapFlags, pAddrSpace) gisubscriptionGetMapAddrSpace_DISPATCH(pGpuResource, pCallContext, mapFlags, pAddrSpace) +#define gisubscriptionGetRefCount(pResource) gisubscriptionGetRefCount_DISPATCH(pResource) +#define gisubscriptionAddAdditionalDependants(pClient, pResource, pReference) gisubscriptionAddAdditionalDependants_DISPATCH(pClient, pResource, pReference) #define gisubscriptionControl_Prologue(pResource, pCallContext, pParams) gisubscriptionControl_Prologue_DISPATCH(pResource, pCallContext, pParams) #define gisubscriptionGetRegBaseOffsetAndSize(pGpuResource, pGpu, pOffset, pSize) gisubscriptionGetRegBaseOffsetAndSize_DISPATCH(pGpuResource, pGpu, pOffset, pSize) #define gisubscriptionInternalControlForward(pGpuResource, command, pParams, size) gisubscriptionInternalControlForward_DISPATCH(pGpuResource, command, pParams, size) -#define gisubscriptionPreDestruct(pResource) gisubscriptionPreDestruct_DISPATCH(pResource) #define gisubscriptionUnmapFrom(pResource, pParams) gisubscriptionUnmapFrom_DISPATCH(pResource, pParams) -#define gisubscriptionIsDuplicate(pResource, hMemory, pDuplicate) gisubscriptionIsDuplicate_DISPATCH(pResource, hMemory, pDuplicate) #define gisubscriptionControl_Epilogue(pResource, pCallContext, pParams) gisubscriptionControl_Epilogue_DISPATCH(pResource, pCallContext, pParams) #define gisubscriptionControlLookup(pResource, pParams, ppEntry) gisubscriptionControlLookup_DISPATCH(pResource, pParams, ppEntry) +#define gisubscriptionGetInternalObjectHandle(pGpuResource) gisubscriptionGetInternalObjectHandle_DISPATCH(pGpuResource) +#define gisubscriptionControl(pGpuResource, pCallContext, pParams) gisubscriptionControl_DISPATCH(pGpuResource, pCallContext, pParams) +#define gisubscriptionUnmap(pGpuResource, pCallContext, pCpuMapping) gisubscriptionUnmap_DISPATCH(pGpuResource, pCallContext, pCpuMapping) +#define gisubscriptionGetMemInterMapParams(pRmResource, pParams) gisubscriptionGetMemInterMapParams_DISPATCH(pRmResource, pParams) +#define gisubscriptionGetMemoryMappingDescriptor(pRmResource, ppMemDesc) gisubscriptionGetMemoryMappingDescriptor_DISPATCH(pRmResource, ppMemDesc) +#define gisubscriptionControlFilter(pResource, pCallContext, pParams) gisubscriptionControlFilter_DISPATCH(pResource, pCallContext, pParams) +#define gisubscriptionControlSerialization_Prologue(pResource, pCallContext, pParams) gisubscriptionControlSerialization_Prologue_DISPATCH(pResource, pCallContext, pParams) +#define gisubscriptionPreDestruct(pResource) gisubscriptionPreDestruct_DISPATCH(pResource) +#define gisubscriptionIsDuplicate(pResource, hMemory, pDuplicate) gisubscriptionIsDuplicate_DISPATCH(pResource, hMemory, pDuplicate) +#define gisubscriptionControlSerialization_Epilogue(pResource, pCallContext, pParams) gisubscriptionControlSerialization_Epilogue_DISPATCH(pResource, pCallContext, pParams) #define gisubscriptionMap(pGpuResource, pCallContext, pParams, pCpuMapping) gisubscriptionMap_DISPATCH(pGpuResource, pCallContext, pParams, pCpuMapping) #define gisubscriptionAccessCallback(pResource, pInvokingClient, pAllocParams, accessRight) gisubscriptionAccessCallback_DISPATCH(pResource, pInvokingClient, pAllocParams, accessRight) NvBool gisubscriptionCanCopy_IMPL(struct GPUInstanceSubscription *arg0); @@ -209,48 +259,24 @@ return pGpuResource->__gisubscriptionShareCallback__(pGpuResource, pInvokingClient, pParentRef, pSharePolicy); } -static inline NV_STATUS gisubscriptionControl_DISPATCH(struct GPUInstanceSubscription *pGpuResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { - return pGpuResource->__gisubscriptionControl__(pGpuResource, pCallContext, pParams); -} - -static inline NV_STATUS gisubscriptionUnmap_DISPATCH(struct GPUInstanceSubscription *pGpuResource, struct CALL_CONTEXT *pCallContext, struct RsCpuMapping *pCpuMapping) { - return pGpuResource->__gisubscriptionUnmap__(pGpuResource, pCallContext, pCpuMapping); -} - -static inline NV_STATUS gisubscriptionGetMemInterMapParams_DISPATCH(struct GPUInstanceSubscription *pRmResource, RMRES_MEM_INTER_MAP_PARAMS *pParams) { - return pRmResource->__gisubscriptionGetMemInterMapParams__(pRmResource, pParams); +static inline NV_STATUS gisubscriptionCheckMemInterUnmap_DISPATCH(struct GPUInstanceSubscription *pRmResource, NvBool bSubdeviceHandleProvided) { + return pRmResource->__gisubscriptionCheckMemInterUnmap__(pRmResource, bSubdeviceHandleProvided); } -static inline NV_STATUS gisubscriptionGetMemoryMappingDescriptor_DISPATCH(struct GPUInstanceSubscription *pRmResource, struct MEMORY_DESCRIPTOR **ppMemDesc) { - return pRmResource->__gisubscriptionGetMemoryMappingDescriptor__(pRmResource, ppMemDesc); +static inline NV_STATUS gisubscriptionMapTo_DISPATCH(struct GPUInstanceSubscription *pResource, RS_RES_MAP_TO_PARAMS *pParams) { + return pResource->__gisubscriptionMapTo__(pResource, pParams); } static inline NV_STATUS gisubscriptionGetMapAddrSpace_DISPATCH(struct GPUInstanceSubscription *pGpuResource, struct CALL_CONTEXT *pCallContext, NvU32 mapFlags, NV_ADDRESS_SPACE *pAddrSpace) { return pGpuResource->__gisubscriptionGetMapAddrSpace__(pGpuResource, pCallContext, mapFlags, pAddrSpace); } -static inline NvHandle gisubscriptionGetInternalObjectHandle_DISPATCH(struct GPUInstanceSubscription *pGpuResource) { - return pGpuResource->__gisubscriptionGetInternalObjectHandle__(pGpuResource); -} - -static inline NV_STATUS gisubscriptionControlFilter_DISPATCH(struct GPUInstanceSubscription *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { - return pResource->__gisubscriptionControlFilter__(pResource, pCallContext, pParams); -} - -static inline void gisubscriptionAddAdditionalDependants_DISPATCH(struct RsClient *pClient, struct GPUInstanceSubscription *pResource, RsResourceRef *pReference) { - pResource->__gisubscriptionAddAdditionalDependants__(pClient, pResource, pReference); -} - static inline NvU32 gisubscriptionGetRefCount_DISPATCH(struct GPUInstanceSubscription *pResource) { return pResource->__gisubscriptionGetRefCount__(pResource); } -static inline NV_STATUS gisubscriptionCheckMemInterUnmap_DISPATCH(struct GPUInstanceSubscription *pRmResource, NvBool bSubdeviceHandleProvided) { - return pRmResource->__gisubscriptionCheckMemInterUnmap__(pRmResource, bSubdeviceHandleProvided); -} - -static inline NV_STATUS gisubscriptionMapTo_DISPATCH(struct GPUInstanceSubscription *pResource, RS_RES_MAP_TO_PARAMS *pParams) { - return pResource->__gisubscriptionMapTo__(pResource, pParams); +static inline void gisubscriptionAddAdditionalDependants_DISPATCH(struct RsClient *pClient, struct GPUInstanceSubscription *pResource, RsResourceRef *pReference) { + pResource->__gisubscriptionAddAdditionalDependants__(pClient, pResource, pReference); } static inline NV_STATUS gisubscriptionControl_Prologue_DISPATCH(struct GPUInstanceSubscription *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { @@ -265,18 +291,10 @@ return pGpuResource->__gisubscriptionInternalControlForward__(pGpuResource, command, pParams, size); } -static inline void gisubscriptionPreDestruct_DISPATCH(struct GPUInstanceSubscription *pResource) { - pResource->__gisubscriptionPreDestruct__(pResource); -} - static inline NV_STATUS gisubscriptionUnmapFrom_DISPATCH(struct GPUInstanceSubscription *pResource, RS_RES_UNMAP_FROM_PARAMS *pParams) { return pResource->__gisubscriptionUnmapFrom__(pResource, pParams); } -static inline NV_STATUS gisubscriptionIsDuplicate_DISPATCH(struct GPUInstanceSubscription *pResource, NvHandle hMemory, NvBool *pDuplicate) { - return pResource->__gisubscriptionIsDuplicate__(pResource, hMemory, pDuplicate); -} - static inline void gisubscriptionControl_Epilogue_DISPATCH(struct GPUInstanceSubscription *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { pResource->__gisubscriptionControl_Epilogue__(pResource, pCallContext, pParams); } @@ -285,6 +303,46 @@ return pResource->__gisubscriptionControlLookup__(pResource, pParams, ppEntry); } +static inline NvHandle gisubscriptionGetInternalObjectHandle_DISPATCH(struct GPUInstanceSubscription *pGpuResource) { + return pGpuResource->__gisubscriptionGetInternalObjectHandle__(pGpuResource); +} + +static inline NV_STATUS gisubscriptionControl_DISPATCH(struct GPUInstanceSubscription *pGpuResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return pGpuResource->__gisubscriptionControl__(pGpuResource, pCallContext, pParams); +} + +static inline NV_STATUS gisubscriptionUnmap_DISPATCH(struct GPUInstanceSubscription *pGpuResource, struct CALL_CONTEXT *pCallContext, struct RsCpuMapping *pCpuMapping) { + return pGpuResource->__gisubscriptionUnmap__(pGpuResource, pCallContext, pCpuMapping); +} + +static inline NV_STATUS gisubscriptionGetMemInterMapParams_DISPATCH(struct GPUInstanceSubscription *pRmResource, RMRES_MEM_INTER_MAP_PARAMS *pParams) { + return pRmResource->__gisubscriptionGetMemInterMapParams__(pRmResource, pParams); +} + +static inline NV_STATUS gisubscriptionGetMemoryMappingDescriptor_DISPATCH(struct GPUInstanceSubscription *pRmResource, struct MEMORY_DESCRIPTOR **ppMemDesc) { + return pRmResource->__gisubscriptionGetMemoryMappingDescriptor__(pRmResource, ppMemDesc); +} + +static inline NV_STATUS gisubscriptionControlFilter_DISPATCH(struct GPUInstanceSubscription *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return pResource->__gisubscriptionControlFilter__(pResource, pCallContext, pParams); +} + +static inline NV_STATUS gisubscriptionControlSerialization_Prologue_DISPATCH(struct GPUInstanceSubscription *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return pResource->__gisubscriptionControlSerialization_Prologue__(pResource, pCallContext, pParams); +} + +static inline void gisubscriptionPreDestruct_DISPATCH(struct GPUInstanceSubscription *pResource) { + pResource->__gisubscriptionPreDestruct__(pResource); +} + +static inline NV_STATUS gisubscriptionIsDuplicate_DISPATCH(struct GPUInstanceSubscription *pResource, NvHandle hMemory, NvBool *pDuplicate) { + return pResource->__gisubscriptionIsDuplicate__(pResource, hMemory, pDuplicate); +} + +static inline void gisubscriptionControlSerialization_Epilogue_DISPATCH(struct GPUInstanceSubscription *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + pResource->__gisubscriptionControlSerialization_Epilogue__(pResource, pCallContext, pParams); +} + static inline NV_STATUS gisubscriptionMap_DISPATCH(struct GPUInstanceSubscription *pGpuResource, struct CALL_CONTEXT *pCallContext, struct RS_CPU_MAP_PARAMS *pParams, struct RsCpuMapping *pCpuMapping) { return pGpuResource->__gisubscriptionMap__(pGpuResource, pCallContext, pParams, pCpuMapping); } @@ -294,7 +352,8 @@ } static inline NvBool gisubscriptionIsDeviceProfiling(struct GPUInstanceSubscription *pGPUInstanceSubscription) { - return pGPUInstanceSubscription->bDeviceProfiling; + struct GPUInstanceSubscription_PRIVATE *pGPUInstanceSubscription_PRIVATE = (struct GPUInstanceSubscription_PRIVATE *)pGPUInstanceSubscription; + return pGPUInstanceSubscription_PRIVATE->bDeviceProfiling; } NV_STATUS gisubscriptionGetGPUInstanceSubscription_IMPL(struct RsClient *arg0, NvHandle arg1, struct GPUInstanceSubscription **arg2); diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/generated/g_gpu_mgmt_api_nvoc.c nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_gpu_mgmt_api_nvoc.c --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/generated/g_gpu_mgmt_api_nvoc.c 2023-10-25 20:26:59.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_gpu_mgmt_api_nvoc.c 2024-03-05 22:18:16.000000000 +0000 @@ -116,8 +116,12 @@ resAddAdditionalDependants(pClient, (struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_GpuManagementApi_RsResource.offset), pReference); } -static NV_STATUS __nvoc_thunk_RsResource_gpumgmtapiUnmap(struct GpuManagementApi *pResource, struct CALL_CONTEXT *pCallContext, RsCpuMapping *pCpuMapping) { - return resUnmap((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_GpuManagementApi_RsResource.offset), pCallContext, pCpuMapping); +static NV_STATUS __nvoc_thunk_RsResource_gpumgmtapiUnmapFrom(struct GpuManagementApi *pResource, RS_RES_UNMAP_FROM_PARAMS *pParams) { + return resUnmapFrom((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_GpuManagementApi_RsResource.offset), pParams); +} + +static NV_STATUS __nvoc_thunk_RmResource_gpumgmtapiControlSerialization_Prologue(struct GpuManagementApi *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return rmresControlSerialization_Prologue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_GpuManagementApi_RmResource.offset), pCallContext, pParams); } static NV_STATUS __nvoc_thunk_RmResource_gpumgmtapiControl_Prologue(struct GpuManagementApi *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { @@ -128,22 +132,26 @@ return resCanCopy((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_GpuManagementApi_RsResource.offset)); } -static NV_STATUS __nvoc_thunk_RsResource_gpumgmtapiMapTo(struct GpuManagementApi *pResource, RS_RES_MAP_TO_PARAMS *pParams) { - return resMapTo((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_GpuManagementApi_RsResource.offset), pParams); +static NV_STATUS __nvoc_thunk_RsResource_gpumgmtapiUnmap(struct GpuManagementApi *pResource, struct CALL_CONTEXT *pCallContext, RsCpuMapping *pCpuMapping) { + return resUnmap((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_GpuManagementApi_RsResource.offset), pCallContext, pCpuMapping); } static void __nvoc_thunk_RsResource_gpumgmtapiPreDestruct(struct GpuManagementApi *pResource) { resPreDestruct((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_GpuManagementApi_RsResource.offset)); } -static NV_STATUS __nvoc_thunk_RsResource_gpumgmtapiUnmapFrom(struct GpuManagementApi *pResource, RS_RES_UNMAP_FROM_PARAMS *pParams) { - return resUnmapFrom((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_GpuManagementApi_RsResource.offset), pParams); +static NV_STATUS __nvoc_thunk_RsResource_gpumgmtapiMapTo(struct GpuManagementApi *pResource, RS_RES_MAP_TO_PARAMS *pParams) { + return resMapTo((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_GpuManagementApi_RsResource.offset), pParams); } static NV_STATUS __nvoc_thunk_RsResource_gpumgmtapiIsDuplicate(struct GpuManagementApi *pResource, NvHandle hMemory, NvBool *pDuplicate) { return resIsDuplicate((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_GpuManagementApi_RsResource.offset), hMemory, pDuplicate); } +static void __nvoc_thunk_RmResource_gpumgmtapiControlSerialization_Epilogue(struct GpuManagementApi *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + rmresControlSerialization_Epilogue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_GpuManagementApi_RmResource.offset), pCallContext, pParams); +} + static void __nvoc_thunk_RmResource_gpumgmtapiControl_Epilogue(struct GpuManagementApi *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { rmresControl_Epilogue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_GpuManagementApi_RmResource.offset), pCallContext, pParams); } @@ -243,20 +251,24 @@ pThis->__gpumgmtapiAddAdditionalDependants__ = &__nvoc_thunk_RsResource_gpumgmtapiAddAdditionalDependants; - pThis->__gpumgmtapiUnmap__ = &__nvoc_thunk_RsResource_gpumgmtapiUnmap; + pThis->__gpumgmtapiUnmapFrom__ = &__nvoc_thunk_RsResource_gpumgmtapiUnmapFrom; + + pThis->__gpumgmtapiControlSerialization_Prologue__ = &__nvoc_thunk_RmResource_gpumgmtapiControlSerialization_Prologue; pThis->__gpumgmtapiControl_Prologue__ = &__nvoc_thunk_RmResource_gpumgmtapiControl_Prologue; pThis->__gpumgmtapiCanCopy__ = &__nvoc_thunk_RsResource_gpumgmtapiCanCopy; - pThis->__gpumgmtapiMapTo__ = &__nvoc_thunk_RsResource_gpumgmtapiMapTo; + pThis->__gpumgmtapiUnmap__ = &__nvoc_thunk_RsResource_gpumgmtapiUnmap; pThis->__gpumgmtapiPreDestruct__ = &__nvoc_thunk_RsResource_gpumgmtapiPreDestruct; - pThis->__gpumgmtapiUnmapFrom__ = &__nvoc_thunk_RsResource_gpumgmtapiUnmapFrom; + pThis->__gpumgmtapiMapTo__ = &__nvoc_thunk_RsResource_gpumgmtapiMapTo; pThis->__gpumgmtapiIsDuplicate__ = &__nvoc_thunk_RsResource_gpumgmtapiIsDuplicate; + pThis->__gpumgmtapiControlSerialization_Epilogue__ = &__nvoc_thunk_RmResource_gpumgmtapiControlSerialization_Epilogue; + pThis->__gpumgmtapiControl_Epilogue__ = &__nvoc_thunk_RmResource_gpumgmtapiControl_Epilogue; pThis->__gpumgmtapiControlLookup__ = &__nvoc_thunk_RsResource_gpumgmtapiControlLookup; @@ -286,13 +298,16 @@ Object *pParentObj; GpuManagementApi *pThis; - pThis = portMemAllocNonPaged(sizeof(GpuManagementApi)); - if (pThis == NULL) return NV_ERR_NO_MEMORY; + status = __nvoc_handleObjCreateMemAlloc(createFlags, sizeof(GpuManagementApi), (void**)&pThis, (void**)ppThis); + if (status != NV_OK) + return status; portMemSet(pThis, 0, sizeof(GpuManagementApi)); __nvoc_initRtti(staticCast(pThis, Dynamic), &__nvoc_class_def_GpuManagementApi); + pThis->__nvoc_base_RmResource.__nvoc_base_RsResource.__nvoc_base_Object.createFlags = createFlags; + if (pParent != NULL && !(createFlags & NVOC_OBJ_CREATE_FLAGS_PARENT_HALSPEC_ONLY)) { pParentObj = dynamicCast(pParent, Object); @@ -308,11 +323,17 @@ if (status != NV_OK) goto __nvoc_objCreate_GpuManagementApi_cleanup; *ppThis = pThis; + return NV_OK; __nvoc_objCreate_GpuManagementApi_cleanup: // do not call destructors here since the constructor already called them - portMemFree(pThis); + if (createFlags & NVOC_OBJ_CREATE_FLAGS_IN_PLACE_CONSTRUCT) + portMemSet(pThis, 0, sizeof(GpuManagementApi)); + else + portMemFree(pThis); + + // coverity[leaked_storage:FALSE] return status; } diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/generated/g_gpu_mgmt_api_nvoc.h nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_gpu_mgmt_api_nvoc.h --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/generated/g_gpu_mgmt_api_nvoc.h 2023-10-25 20:26:59.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_gpu_mgmt_api_nvoc.h 2024-03-05 22:18:16.000000000 +0000 @@ -69,13 +69,15 @@ NvU32 (*__gpumgmtapiGetRefCount__)(struct GpuManagementApi *); NV_STATUS (*__gpumgmtapiControlFilter__)(struct GpuManagementApi *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); void (*__gpumgmtapiAddAdditionalDependants__)(struct RsClient *, struct GpuManagementApi *, RsResourceRef *); - NV_STATUS (*__gpumgmtapiUnmap__)(struct GpuManagementApi *, struct CALL_CONTEXT *, RsCpuMapping *); + NV_STATUS (*__gpumgmtapiUnmapFrom__)(struct GpuManagementApi *, RS_RES_UNMAP_FROM_PARAMS *); + NV_STATUS (*__gpumgmtapiControlSerialization_Prologue__)(struct GpuManagementApi *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); NV_STATUS (*__gpumgmtapiControl_Prologue__)(struct GpuManagementApi *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); NvBool (*__gpumgmtapiCanCopy__)(struct GpuManagementApi *); - NV_STATUS (*__gpumgmtapiMapTo__)(struct GpuManagementApi *, RS_RES_MAP_TO_PARAMS *); + NV_STATUS (*__gpumgmtapiUnmap__)(struct GpuManagementApi *, struct CALL_CONTEXT *, RsCpuMapping *); void (*__gpumgmtapiPreDestruct__)(struct GpuManagementApi *); - NV_STATUS (*__gpumgmtapiUnmapFrom__)(struct GpuManagementApi *, RS_RES_UNMAP_FROM_PARAMS *); + NV_STATUS (*__gpumgmtapiMapTo__)(struct GpuManagementApi *, RS_RES_MAP_TO_PARAMS *); NV_STATUS (*__gpumgmtapiIsDuplicate__)(struct GpuManagementApi *, NvHandle, NvBool *); + void (*__gpumgmtapiControlSerialization_Epilogue__)(struct GpuManagementApi *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); void (*__gpumgmtapiControl_Epilogue__)(struct GpuManagementApi *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); NV_STATUS (*__gpumgmtapiControlLookup__)(struct GpuManagementApi *, struct RS_RES_CONTROL_PARAMS_INTERNAL *, const struct NVOC_EXPORTED_METHOD_DEF **); NV_STATUS (*__gpumgmtapiMap__)(struct GpuManagementApi *, struct CALL_CONTEXT *, RS_CPU_MAP_PARAMS *, RsCpuMapping *); @@ -119,13 +121,15 @@ #define gpumgmtapiGetRefCount(pResource) gpumgmtapiGetRefCount_DISPATCH(pResource) #define gpumgmtapiControlFilter(pResource, pCallContext, pParams) gpumgmtapiControlFilter_DISPATCH(pResource, pCallContext, pParams) #define gpumgmtapiAddAdditionalDependants(pClient, pResource, pReference) gpumgmtapiAddAdditionalDependants_DISPATCH(pClient, pResource, pReference) -#define gpumgmtapiUnmap(pResource, pCallContext, pCpuMapping) gpumgmtapiUnmap_DISPATCH(pResource, pCallContext, pCpuMapping) +#define gpumgmtapiUnmapFrom(pResource, pParams) gpumgmtapiUnmapFrom_DISPATCH(pResource, pParams) +#define gpumgmtapiControlSerialization_Prologue(pResource, pCallContext, pParams) gpumgmtapiControlSerialization_Prologue_DISPATCH(pResource, pCallContext, pParams) #define gpumgmtapiControl_Prologue(pResource, pCallContext, pParams) gpumgmtapiControl_Prologue_DISPATCH(pResource, pCallContext, pParams) #define gpumgmtapiCanCopy(pResource) gpumgmtapiCanCopy_DISPATCH(pResource) -#define gpumgmtapiMapTo(pResource, pParams) gpumgmtapiMapTo_DISPATCH(pResource, pParams) +#define gpumgmtapiUnmap(pResource, pCallContext, pCpuMapping) gpumgmtapiUnmap_DISPATCH(pResource, pCallContext, pCpuMapping) #define gpumgmtapiPreDestruct(pResource) gpumgmtapiPreDestruct_DISPATCH(pResource) -#define gpumgmtapiUnmapFrom(pResource, pParams) gpumgmtapiUnmapFrom_DISPATCH(pResource, pParams) +#define gpumgmtapiMapTo(pResource, pParams) gpumgmtapiMapTo_DISPATCH(pResource, pParams) #define gpumgmtapiIsDuplicate(pResource, hMemory, pDuplicate) gpumgmtapiIsDuplicate_DISPATCH(pResource, hMemory, pDuplicate) +#define gpumgmtapiControlSerialization_Epilogue(pResource, pCallContext, pParams) gpumgmtapiControlSerialization_Epilogue_DISPATCH(pResource, pCallContext, pParams) #define gpumgmtapiControl_Epilogue(pResource, pCallContext, pParams) gpumgmtapiControl_Epilogue_DISPATCH(pResource, pCallContext, pParams) #define gpumgmtapiControlLookup(pResource, pParams, ppEntry) gpumgmtapiControlLookup_DISPATCH(pResource, pParams, ppEntry) #define gpumgmtapiMap(pResource, pCallContext, pParams, pCpuMapping) gpumgmtapiMap_DISPATCH(pResource, pCallContext, pParams, pCpuMapping) @@ -168,8 +172,12 @@ pResource->__gpumgmtapiAddAdditionalDependants__(pClient, pResource, pReference); } -static inline NV_STATUS gpumgmtapiUnmap_DISPATCH(struct GpuManagementApi *pResource, struct CALL_CONTEXT *pCallContext, RsCpuMapping *pCpuMapping) { - return pResource->__gpumgmtapiUnmap__(pResource, pCallContext, pCpuMapping); +static inline NV_STATUS gpumgmtapiUnmapFrom_DISPATCH(struct GpuManagementApi *pResource, RS_RES_UNMAP_FROM_PARAMS *pParams) { + return pResource->__gpumgmtapiUnmapFrom__(pResource, pParams); +} + +static inline NV_STATUS gpumgmtapiControlSerialization_Prologue_DISPATCH(struct GpuManagementApi *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return pResource->__gpumgmtapiControlSerialization_Prologue__(pResource, pCallContext, pParams); } static inline NV_STATUS gpumgmtapiControl_Prologue_DISPATCH(struct GpuManagementApi *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { @@ -180,22 +188,26 @@ return pResource->__gpumgmtapiCanCopy__(pResource); } -static inline NV_STATUS gpumgmtapiMapTo_DISPATCH(struct GpuManagementApi *pResource, RS_RES_MAP_TO_PARAMS *pParams) { - return pResource->__gpumgmtapiMapTo__(pResource, pParams); +static inline NV_STATUS gpumgmtapiUnmap_DISPATCH(struct GpuManagementApi *pResource, struct CALL_CONTEXT *pCallContext, RsCpuMapping *pCpuMapping) { + return pResource->__gpumgmtapiUnmap__(pResource, pCallContext, pCpuMapping); } static inline void gpumgmtapiPreDestruct_DISPATCH(struct GpuManagementApi *pResource) { pResource->__gpumgmtapiPreDestruct__(pResource); } -static inline NV_STATUS gpumgmtapiUnmapFrom_DISPATCH(struct GpuManagementApi *pResource, RS_RES_UNMAP_FROM_PARAMS *pParams) { - return pResource->__gpumgmtapiUnmapFrom__(pResource, pParams); +static inline NV_STATUS gpumgmtapiMapTo_DISPATCH(struct GpuManagementApi *pResource, RS_RES_MAP_TO_PARAMS *pParams) { + return pResource->__gpumgmtapiMapTo__(pResource, pParams); } static inline NV_STATUS gpumgmtapiIsDuplicate_DISPATCH(struct GpuManagementApi *pResource, NvHandle hMemory, NvBool *pDuplicate) { return pResource->__gpumgmtapiIsDuplicate__(pResource, hMemory, pDuplicate); } +static inline void gpumgmtapiControlSerialization_Epilogue_DISPATCH(struct GpuManagementApi *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + pResource->__gpumgmtapiControlSerialization_Epilogue__(pResource, pCallContext, pParams); +} + static inline void gpumgmtapiControl_Epilogue_DISPATCH(struct GpuManagementApi *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { pResource->__gpumgmtapiControl_Epilogue__(pResource, pCallContext, pParams); } diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/generated/g_gpu_mgr_nvoc.c nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_gpu_mgr_nvoc.c --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/generated/g_gpu_mgr_nvoc.c 2023-10-25 20:26:59.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_gpu_mgr_nvoc.c 2024-03-05 22:18:16.000000000 +0000 @@ -114,13 +114,16 @@ Object *pParentObj; OBJGPUMGR *pThis; - pThis = portMemAllocNonPaged(sizeof(OBJGPUMGR)); - if (pThis == NULL) return NV_ERR_NO_MEMORY; + status = __nvoc_handleObjCreateMemAlloc(createFlags, sizeof(OBJGPUMGR), (void**)&pThis, (void**)ppThis); + if (status != NV_OK) + return status; portMemSet(pThis, 0, sizeof(OBJGPUMGR)); __nvoc_initRtti(staticCast(pThis, Dynamic), &__nvoc_class_def_OBJGPUMGR); + pThis->__nvoc_base_Object.createFlags = createFlags; + if (pParent != NULL && !(createFlags & NVOC_OBJ_CREATE_FLAGS_PARENT_HALSPEC_ONLY)) { pParentObj = dynamicCast(pParent, Object); @@ -136,11 +139,17 @@ if (status != NV_OK) goto __nvoc_objCreate_OBJGPUMGR_cleanup; *ppThis = pThis; + return NV_OK; __nvoc_objCreate_OBJGPUMGR_cleanup: // do not call destructors here since the constructor already called them - portMemFree(pThis); + if (createFlags & NVOC_OBJ_CREATE_FLAGS_IN_PLACE_CONSTRUCT) + portMemSet(pThis, 0, sizeof(OBJGPUMGR)); + else + portMemFree(pThis); + + // coverity[leaked_storage:FALSE] return status; } diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/generated/g_gpu_mgr_nvoc.h nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_gpu_mgr_nvoc.h --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/generated/g_gpu_mgr_nvoc.h 2023-10-25 20:26:59.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_gpu_mgr_nvoc.h 2024-03-05 22:18:16.000000000 +0000 @@ -7,7 +7,7 @@ #endif /* - * SPDX-FileCopyrightText: Copyright (c) 2005-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2005-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -30,6 +30,7 @@ */ #include "g_gpu_mgr_nvoc.h" + #ifndef _GPUMGR_H_ #define _GPUMGR_H_ @@ -50,7 +51,8 @@ #include "ctrl/ctrl2080/ctrl2080internal.h" #include "ctrl/ctrlc637.h" #include "nvoc/utility.h" -#include "nv_firmware_types.h" + +#include "gpu_mgr/gpu_mgr_sli.h" #include "gpu/perf/kern_perf_gpuboostsync.h" @@ -78,7 +80,6 @@ #define gpumgrGetSliLinkConnectionCount(pGpu) ((NvU32) 0) #define gpumgrGetSLIConfig(gpuInstance, onlyWithSliLink) ((NvU32) 0) #define gpumgrDisableVidLink(pGpu, head, max_dr_port) -#define gpumgrPinsetToPinsetTableIndex(pinset, pPinsetIndex) (NV_ERR_NOT_SUPPORTED) #define gpumgrGetBcEnabledStatus(g) (NV_FALSE) #define gpumgrGetBcEnabledStatusEx(g, t) (NV_FALSE) #define gpumgrSetBcEnabledStatus(g, b) do { NvBool b2 = b; (void)b2; } while (0) @@ -86,7 +87,6 @@ #define gpumgrSLILoopReentrancyPop(pGpu) ((NvU32)0) #define gpumgrSLILoopReentrancyPush(pGpu, sliLoopReentrancy) do { NvU32 x = sliLoopReentrancy; (void)x; } while(0) - typedef struct { NvU32 gpuId; @@ -120,6 +120,15 @@ void *pSaveRegsOpaque; //> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x01f00000UL) )) /* ChipHal: AD102 | AD103 | AD104 | AD106 | AD107 */ + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x11f00000UL) )) /* ChipHal: AD102 | AD103 | AD104 | AD106 | AD107 | GH100 */ { pThis->setProperty(pThis, PDB_PROP_GPU_VGPU_OFFLOAD_CAPABLE, ((NvBool)(0 == 0))); } @@ -209,6 +209,12 @@ pThis->setProperty(pThis, PDB_PROP_GPU_VGPU_OFFLOAD_CAPABLE, ((NvBool)(0 != 0))); } + // NVOC Property Hal field -- PDB_PROP_GPU_UNIX_DYNAMIC_POWER_SUPPORTED + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x11f0ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 | GH100 */ + { + pThis->setProperty(pThis, PDB_PROP_GPU_UNIX_DYNAMIC_POWER_SUPPORTED, ((NvBool)(0 == 0))); + } + // NVOC Property Hal field -- PDB_PROP_GPU_SKIP_CE_MAPPINGS_NO_NVLINK if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ { @@ -222,6 +228,46 @@ pThis->setProperty(pThis, PDB_PROP_GPU_OPTIMUS_GOLD_CFG_SPACE_RESTORE, ((NvBool)(0 == 0))); pThis->setProperty(pThis, PDB_PROP_GPU_SRIOV_HEAVY_FORCE_INVALIDATE_ALL_PDBS_WAR_BUG3896322, ((NvBool)(0 != 0))); + // NVOC Property Hal field -- PDB_PROP_GPU_CC_FEATURE_CAPABLE + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ + { + pThis->setProperty(pThis, PDB_PROP_GPU_CC_FEATURE_CAPABLE, ((NvBool)(0 == 0))); + } + // default + else + { + pThis->setProperty(pThis, PDB_PROP_GPU_CC_FEATURE_CAPABLE, ((NvBool)(0 != 0))); + } + + // NVOC Property Hal field -- PDB_PROP_GPU_APM_FEATURE_CAPABLE + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x01f0fc00UL) )) /* ChipHal: GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 */ + { + pThis->setProperty(pThis, PDB_PROP_GPU_APM_FEATURE_CAPABLE, ((NvBool)(0 == 0))); + } + // default + else + { + pThis->setProperty(pThis, PDB_PROP_GPU_APM_FEATURE_CAPABLE, ((NvBool)(0 != 0))); + } + + // NVOC Property Hal field -- PDB_PROP_GPU_EXTENDED_GSP_RM_INITIALIZATION_TIMEOUT_FOR_VGX + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ + { + pThis->setProperty(pThis, PDB_PROP_GPU_EXTENDED_GSP_RM_INITIALIZATION_TIMEOUT_FOR_VGX, ((NvBool)(0 == 0))); + } + // default + else + { + pThis->setProperty(pThis, PDB_PROP_GPU_EXTENDED_GSP_RM_INITIALIZATION_TIMEOUT_FOR_VGX, ((NvBool)(0 != 0))); + } + + // NVOC Property Hal field -- PDB_PROP_GPU_CHIP_SUPPORTS_RTD3_DEF + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x11f0ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 | GH100 */ + { + pThis->setProperty(pThis, PDB_PROP_GPU_CHIP_SUPPORTS_RTD3_DEF, ((NvBool)(0 == 0))); + } + pThis->setProperty(pThis, PDB_PROP_GPU_FASTPATH_SEQ_ENABLED, ((NvBool)(0 != 0))); + pThis->boardId = ~0; pThis->deviceInstance = 32; @@ -315,6 +361,14 @@ pThis->bSriovCapable = ((NvBool)(0 == 0)); } + // Hal field -- bRecheckSliSupportAtResume + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x11f0ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 | GH100 */ + { + pThis->bRecheckSliSupportAtResume = ((NvBool)(0 == 0)); + } + + pThis->bIsGspOwnedFaultBuffersEnabled = ((NvBool)(0 != 0)); + // Hal field -- bEnableBar1SparseForFillPteMemUnmap if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x11f0fc00UL) )) /* ChipHal: GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 | GH100 */ { @@ -367,64 +421,75 @@ PORT_UNREFERENCED_VARIABLE(rmVariantHal); PORT_UNREFERENCED_VARIABLE(rmVariantHal_HalVarIdx); - // Hal function -- gpuWriteBusConfigReg - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x01f0ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 */ + // Hal function -- gpuConstructDeviceInfoTable + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x11f0fc00UL) )) /* ChipHal: GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 | GH100 */ { - pThis->__gpuWriteBusConfigReg__ = &gpuWriteBusConfigReg_GM107; + pThis->__gpuConstructDeviceInfoTable__ = &gpuConstructDeviceInfoTable_FWCLIENT; } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ + // default + else + { + pThis->__gpuConstructDeviceInfoTable__ = &gpuConstructDeviceInfoTable_56cd7a; + } + + // Hal function -- gpuWriteBusConfigReg + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ { pThis->__gpuWriteBusConfigReg__ = &gpuWriteBusConfigReg_GH100; } + else + { + pThis->__gpuWriteBusConfigReg__ = &gpuWriteBusConfigReg_GM107; + } // Hal function -- gpuReadBusConfigReg - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x01f0ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 */ + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ { - pThis->__gpuReadBusConfigReg__ = &gpuReadBusConfigReg_GM107; + pThis->__gpuReadBusConfigReg__ = &gpuReadBusConfigReg_GH100; } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ + else { - pThis->__gpuReadBusConfigReg__ = &gpuReadBusConfigReg_GH100; + pThis->__gpuReadBusConfigReg__ = &gpuReadBusConfigReg_GM107; } // Hal function -- gpuReadBusConfigRegEx - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x01f0ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 */ + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ { - pThis->__gpuReadBusConfigRegEx__ = &gpuReadBusConfigRegEx_GM107; + pThis->__gpuReadBusConfigRegEx__ = &gpuReadBusConfigRegEx_5baef9; } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ + else { - pThis->__gpuReadBusConfigRegEx__ = &gpuReadBusConfigRegEx_46f6a7; + pThis->__gpuReadBusConfigRegEx__ = &gpuReadBusConfigRegEx_GM107; } // Hal function -- gpuReadFunctionConfigReg - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x01f0ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 */ + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ { - pThis->__gpuReadFunctionConfigReg__ = &gpuReadFunctionConfigReg_GM107; + pThis->__gpuReadFunctionConfigReg__ = &gpuReadFunctionConfigReg_5baef9; } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ + else { - pThis->__gpuReadFunctionConfigReg__ = &gpuReadFunctionConfigReg_5baef9; + pThis->__gpuReadFunctionConfigReg__ = &gpuReadFunctionConfigReg_GM107; } // Hal function -- gpuWriteFunctionConfigReg - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x01f0ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 */ + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ { - pThis->__gpuWriteFunctionConfigReg__ = &gpuWriteFunctionConfigReg_GM107; + pThis->__gpuWriteFunctionConfigReg__ = &gpuWriteFunctionConfigReg_5baef9; } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ + else { - pThis->__gpuWriteFunctionConfigReg__ = &gpuWriteFunctionConfigReg_5baef9; + pThis->__gpuWriteFunctionConfigReg__ = &gpuWriteFunctionConfigReg_GM107; } // Hal function -- gpuWriteFunctionConfigRegEx - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x01f0ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 */ + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ { - pThis->__gpuWriteFunctionConfigRegEx__ = &gpuWriteFunctionConfigRegEx_GM107; + pThis->__gpuWriteFunctionConfigRegEx__ = &gpuWriteFunctionConfigRegEx_5baef9; } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ + else { - pThis->__gpuWriteFunctionConfigRegEx__ = &gpuWriteFunctionConfigRegEx_5baef9; + pThis->__gpuWriteFunctionConfigRegEx__ = &gpuWriteFunctionConfigRegEx_GM107; } // Hal function -- gpuReadVgpuConfigReg @@ -439,23 +504,23 @@ } // Hal function -- gpuGetIdInfo - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x01f0ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 */ + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ { - pThis->__gpuGetIdInfo__ = &gpuGetIdInfo_GM107; + pThis->__gpuGetIdInfo__ = &gpuGetIdInfo_GH100; } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ + else { - pThis->__gpuGetIdInfo__ = &gpuGetIdInfo_GH100; + pThis->__gpuGetIdInfo__ = &gpuGetIdInfo_GM107; } // Hal function -- gpuHandleSanityCheckRegReadError - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x01f0ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 */ + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ { - pThis->__gpuHandleSanityCheckRegReadError__ = &gpuHandleSanityCheckRegReadError_GM107; + pThis->__gpuHandleSanityCheckRegReadError__ = &gpuHandleSanityCheckRegReadError_GH100; } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ + else { - pThis->__gpuHandleSanityCheckRegReadError__ = &gpuHandleSanityCheckRegReadError_GH100; + pThis->__gpuHandleSanityCheckRegReadError__ = &gpuHandleSanityCheckRegReadError_GM107; } // Hal function -- gpuHandleSecFault @@ -470,11 +535,7 @@ } // Hal function -- gpuGetChildrenPresent - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x00000320UL) )) /* ChipHal: TU102 | TU116 | TU117 */ - { - pThis->__gpuGetChildrenPresent__ = &gpuGetChildrenPresent_TU102; - } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x00000040UL) )) /* ChipHal: TU104 */ + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x00000040UL) )) /* ChipHal: TU104 */ { pThis->__gpuGetChildrenPresent__ = &gpuGetChildrenPresent_TU104; } @@ -486,25 +547,25 @@ { pThis->__gpuGetChildrenPresent__ = &gpuGetChildrenPresent_GA100; } + else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ + { + pThis->__gpuGetChildrenPresent__ = &gpuGetChildrenPresent_GH100; + } + else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x00000320UL) )) /* ChipHal: TU102 | TU116 | TU117 */ + { + pThis->__gpuGetChildrenPresent__ = &gpuGetChildrenPresent_TU102; + } else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0000f800UL) )) /* ChipHal: GA102 | GA103 | GA104 | GA106 | GA107 */ { pThis->__gpuGetChildrenPresent__ = &gpuGetChildrenPresent_GA102; } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x01f00000UL) )) /* ChipHal: AD102 | AD103 | AD104 | AD106 | AD107 */ + else { pThis->__gpuGetChildrenPresent__ = &gpuGetChildrenPresent_AD102; } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ - { - pThis->__gpuGetChildrenPresent__ = &gpuGetChildrenPresent_GH100; - } // Hal function -- gpuGetClassDescriptorList - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x00000120UL) )) /* ChipHal: TU102 | TU116 */ - { - pThis->__gpuGetClassDescriptorList__ = &gpuGetClassDescriptorList_TU102; - } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x00000040UL) )) /* ChipHal: TU104 */ + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x00000040UL) )) /* ChipHal: TU104 */ { pThis->__gpuGetClassDescriptorList__ = &gpuGetClassDescriptorList_TU104; } @@ -520,82 +581,80 @@ { pThis->__gpuGetClassDescriptorList__ = &gpuGetClassDescriptorList_GA100; } + else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ + { + pThis->__gpuGetClassDescriptorList__ = &gpuGetClassDescriptorList_GH100; + } + else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x00000120UL) )) /* ChipHal: TU102 | TU116 */ + { + pThis->__gpuGetClassDescriptorList__ = &gpuGetClassDescriptorList_TU102; + } else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0000f800UL) )) /* ChipHal: GA102 | GA103 | GA104 | GA106 | GA107 */ { pThis->__gpuGetClassDescriptorList__ = &gpuGetClassDescriptorList_GA102; } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x01f00000UL) )) /* ChipHal: AD102 | AD103 | AD104 | AD106 | AD107 */ + else { pThis->__gpuGetClassDescriptorList__ = &gpuGetClassDescriptorList_AD102; } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ - { - pThis->__gpuGetClassDescriptorList__ = &gpuGetClassDescriptorList_GH100; - } // Hal function -- gpuGetPhysAddrWidth - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x01f0ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 */ + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ { - pThis->__gpuGetPhysAddrWidth__ = &gpuGetPhysAddrWidth_TU102; + pThis->__gpuGetPhysAddrWidth__ = &gpuGetPhysAddrWidth_GH100; } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ + else { - pThis->__gpuGetPhysAddrWidth__ = &gpuGetPhysAddrWidth_GH100; + pThis->__gpuGetPhysAddrWidth__ = &gpuGetPhysAddrWidth_TU102; } // Hal function -- gpuFuseSupportsDisplay - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x000003e0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 */ + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000400UL) )) /* ChipHal: GA100 | GH100 */ + { + pThis->__gpuFuseSupportsDisplay__ = &gpuFuseSupportsDisplay_491d52; + } + else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x000003e0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 */ { pThis->__gpuFuseSupportsDisplay__ = &gpuFuseSupportsDisplay_GM107; } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x11f0fc00UL) )) /* ChipHal: GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 | GH100 */ + else { pThis->__gpuFuseSupportsDisplay__ = &gpuFuseSupportsDisplay_GA100; } // Hal function -- gpuClearFbhubPoisonIntrForBug2924523 - if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000002UL) )) /* RmVariantHal: PF_KERNEL_ONLY */ + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000400UL) )) /* ChipHal: GA100 | GH100 */ { - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000400UL) )) /* ChipHal: GA100 | GH100 */ - { - pThis->__gpuClearFbhubPoisonIntrForBug2924523__ = &gpuClearFbhubPoisonIntrForBug2924523_GA100_KERNEL; - } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x01f0fbe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 */ - { - pThis->__gpuClearFbhubPoisonIntrForBug2924523__ = &gpuClearFbhubPoisonIntrForBug2924523_56cd7a; - } + pThis->__gpuClearFbhubPoisonIntrForBug2924523__ = &gpuClearFbhubPoisonIntrForBug2924523_GA100_KERNEL; + } + else + { + pThis->__gpuClearFbhubPoisonIntrForBug2924523__ = &gpuClearFbhubPoisonIntrForBug2924523_56cd7a; } - // Hal function -- gpuReadDeviceId - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x01f0ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 */ + // Hal function -- gpuCheckIfFbhubPoisonIntrPending + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000400UL) )) /* ChipHal: GA100 | GH100 */ { - pThis->__gpuReadDeviceId__ = &gpuReadDeviceId_GM107; + pThis->__gpuCheckIfFbhubPoisonIntrPending__ = &gpuCheckIfFbhubPoisonIntrPending_GA100; } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ + // default + else { - pThis->__gpuReadDeviceId__ = &gpuReadDeviceId_GH100; + pThis->__gpuCheckIfFbhubPoisonIntrPending__ = &gpuCheckIfFbhubPoisonIntrPending_491d52; } - // Hal function -- gpuConstructDeviceInfoTable - if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000002UL) )) /* RmVariantHal: PF_KERNEL_ONLY */ + // Hal function -- gpuReadDeviceId + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ { - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x11f0fc00UL) )) /* ChipHal: GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 | GH100 */ - { - pThis->__gpuConstructDeviceInfoTable__ = &gpuConstructDeviceInfoTable_FWCLIENT; - } - // default - else - { - pThis->__gpuConstructDeviceInfoTable__ = &gpuConstructDeviceInfoTable_56cd7a; - } + pThis->__gpuReadDeviceId__ = &gpuReadDeviceId_GH100; } - - // Hal function -- gpuGetFlaVasSize - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x01f0fc00UL) )) /* ChipHal: GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 */ + else { - pThis->__gpuGetFlaVasSize__ = &gpuGetFlaVasSize_GA100; + pThis->__gpuReadDeviceId__ = &gpuReadDeviceId_GM107; } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ + + // Hal function -- gpuGetFlaVasSize + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ { pThis->__gpuGetFlaVasSize__ = &gpuGetFlaVasSize_GH100; } @@ -603,6 +662,32 @@ { pThis->__gpuGetFlaVasSize__ = &gpuGetFlaVasSize_474d46; } + else + { + pThis->__gpuGetFlaVasSize__ = &gpuGetFlaVasSize_GA100; + } + + // Hal function -- gpuDetermineSelfHostedMode + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ + { + pThis->__gpuDetermineSelfHostedMode__ = &gpuDetermineSelfHostedMode_KERNEL_GH100; + } + // default + else + { + pThis->__gpuDetermineSelfHostedMode__ = &gpuDetermineSelfHostedMode_b3696a; + } + + // Hal function -- gpuDetermineMIGSupport + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ + { + pThis->__gpuDetermineMIGSupport__ = &gpuDetermineMIGSupport_GH100; + } + // default + else + { + pThis->__gpuDetermineMIGSupport__ = &gpuDetermineMIGSupport_b3696a; + } // Hal function -- gpuIsAtsSupportedWithSmcMemPartitioning if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ @@ -625,6 +710,50 @@ { pThis->__gpuIsSliCapableWithoutDisplay__ = &gpuIsSliCapableWithoutDisplay_491d52; } + + // Hal function -- gpuIsCCEnabledInHw + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ + { + pThis->__gpuIsCCEnabledInHw__ = &gpuIsCCEnabledInHw_GH100; + } + // default + else + { + pThis->__gpuIsCCEnabledInHw__ = &gpuIsCCEnabledInHw_491d52; + } + + // Hal function -- gpuIsDevModeEnabledInHw + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ + { + pThis->__gpuIsDevModeEnabledInHw__ = &gpuIsDevModeEnabledInHw_GH100; + } + // default + else + { + pThis->__gpuIsDevModeEnabledInHw__ = &gpuIsDevModeEnabledInHw_491d52; + } + + // Hal function -- gpuIsCtxBufAllocInPmaSupported + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x11f0fc00UL) )) /* ChipHal: GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 | GH100 */ + { + pThis->__gpuIsCtxBufAllocInPmaSupported__ = &gpuIsCtxBufAllocInPmaSupported_GA100; + } + // default + else + { + pThis->__gpuIsCtxBufAllocInPmaSupported__ = &gpuIsCtxBufAllocInPmaSupported_491d52; + } + + // Hal function -- gpuWaitForGfwBootComplete + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x01f0ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 */ + { + pThis->__gpuWaitForGfwBootComplete__ = &gpuWaitForGfwBootComplete_TU102; + } + // default + else + { + pThis->__gpuWaitForGfwBootComplete__ = &gpuWaitForGfwBootComplete_5baef9; + } } void __nvoc_init_funcTable_OBJGPU(OBJGPU *pThis) { @@ -656,13 +785,16 @@ Object *pParentObj; OBJGPU *pThis; - pThis = portMemAllocNonPaged(sizeof(OBJGPU)); - if (pThis == NULL) return NV_ERR_NO_MEMORY; + status = __nvoc_handleObjCreateMemAlloc(createFlags, sizeof(OBJGPU), (void**)&pThis, (void**)ppThis); + if (status != NV_OK) + return status; portMemSet(pThis, 0, sizeof(OBJGPU)); __nvoc_initRtti(staticCast(pThis, Dynamic), &__nvoc_class_def_OBJGPU); + pThis->__nvoc_base_Object.createFlags = createFlags; + if (pParent != NULL && !(createFlags & NVOC_OBJ_CREATE_FLAGS_PARENT_HALSPEC_ONLY)) { pParentObj = dynamicCast(pParent, Object); @@ -678,11 +810,17 @@ if (status != NV_OK) goto __nvoc_objCreate_OBJGPU_cleanup; *ppThis = pThis; + return NV_OK; __nvoc_objCreate_OBJGPU_cleanup: // do not call destructors here since the constructor already called them - portMemFree(pThis); + if (createFlags & NVOC_OBJ_CREATE_FLAGS_IN_PLACE_CONSTRUCT) + portMemSet(pThis, 0, sizeof(OBJGPU)); + else + portMemFree(pThis); + + // coverity[leaked_storage:FALSE] return status; } diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/generated/g_gpu_nvoc.h nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_gpu_nvoc.h --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/generated/g_gpu_nvoc.h 2023-10-25 20:26:59.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_gpu_nvoc.h 2024-03-05 22:18:16.000000000 +0000 @@ -7,7 +7,7 @@ #endif /* - * SPDX-FileCopyrightText: Copyright (c) 2004-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2004-2024 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -73,6 +73,7 @@ #include "gpu/gpu_timeout.h" #include "gpu/gpu_access.h" #include "gpu/gpu_shared_data_map.h" +#include "gpu/kern_gpu_power.h" #include "platform/acpi_common.h" #include "gpu/gpu_acpi_data.h" @@ -143,16 +144,16 @@ #endif /* __nvoc_class_id_OBJHOSTENG */ -struct OBJPMUCLIENT; +struct OBJPMU_CLIENT_IMPLEMENTER; -#ifndef __NVOC_CLASS_OBJPMUCLIENT_TYPEDEF__ -#define __NVOC_CLASS_OBJPMUCLIENT_TYPEDEF__ -typedef struct OBJPMUCLIENT OBJPMUCLIENT; -#endif /* __NVOC_CLASS_OBJPMUCLIENT_TYPEDEF__ */ - -#ifndef __nvoc_class_id_OBJPMUCLIENT -#define __nvoc_class_id_OBJPMUCLIENT 0xea631d -#endif /* __nvoc_class_id_OBJPMUCLIENT */ +#ifndef __NVOC_CLASS_OBJPMU_CLIENT_IMPLEMENTER_TYPEDEF__ +#define __NVOC_CLASS_OBJPMU_CLIENT_IMPLEMENTER_TYPEDEF__ +typedef struct OBJPMU_CLIENT_IMPLEMENTER OBJPMU_CLIENT_IMPLEMENTER; +#endif /* __NVOC_CLASS_OBJPMU_CLIENT_IMPLEMENTER_TYPEDEF__ */ + +#ifndef __nvoc_class_id_OBJPMU_CLIENT_IMPLEMENTER +#define __nvoc_class_id_OBJPMU_CLIENT_IMPLEMENTER 0x88cace +#endif /* __nvoc_class_id_OBJPMU_CLIENT_IMPLEMENTER */ struct OBJINTRABLE; @@ -299,7 +300,7 @@ COMPUTE_BRANDING_TYPE_TESLA, } COMPUTE_BRANDING_TYPE; -#define OOR_ARCH_DEF(x) \ +#define OOR_ARCH_DEF(x) \ NV_ENUM_ENTRY(x, OOR_ARCH_X86_64, 0x00000000) \ NV_ENUM_ENTRY(x, OOR_ARCH_PPC64LE, 0x00000001) \ NV_ENUM_ENTRY(x, OOR_ARCH_ARM, 0x00000002) \ @@ -318,8 +319,61 @@ { NvU32 classId; NvU32 instances; + + /*! + * Pointer to the @ref NVOC_CLASS_INFO for the concrete class to instantiate + * for this child. + */ + const NVOC_CLASS_INFO *pClassInfo; } GPUCHILDPRESENT; +/*! + * @brief Generates an entry for a list of @ref GPUCHILDPRESENT objects for a + * class of the given name + * + * @param[in] _childClassName + * Name of the class for the entry + * @param[in] _instances + * Number of instances of the child that may be present; see + * @ref GPUCHILDPRESENT::instances + * + * @return An entry suitable for a list of @ref GPUCHILDPRESENT for the given + * child of @ref OBJGPU + */ +#define GPU_CHILD_PRESENT(_childClassName, _instances) \ + GPU_CHILD_PRESENT_POLYMORPHIC(_childClassName, (_instances), _childClassName) + +/*! + * @brief Generates an entry for a list of @ref GPUCHILDPRESENT objects that + * allows the @ref OBJGPU child to instantiate a sub-class of the base + * @ref OBJGPU child class. + * + * @details The intention of this macro is to allow a list of + * @ref GPUCHILDPRESENT to essentially state "this child should be + * present with this concrete class type". This allows for different + * @ref GPUCHILDPRESENT lists to request different classes with + * different behavior via sub-classes, for the same basic @ref OBJGPU + * child. + * + * @param[in] _childClassName + * Name of the base class at which @ref OBJGPU points + * @param[in] _instances + * Number of instances of the child that may be present; see + * @ref GPUCHILDPRESENT::instances + * @param[in] _concreteClassName + * Name of the sub-class of _childClassName that should actually be + * instantiated + * + * @return An entry suitable for a list of @ref GPUCHILDPRESENT for the given + * child of @ref OBJGPU with the given concrete class type. + */ +#define GPU_CHILD_PRESENT_POLYMORPHIC(_childClassName, _instances, _concreteClassName) \ + { \ + .classId = classId(_childClassName), \ + .instances = (_instances), \ + .pClassInfo = classInfo(_concreteClassName) \ + } + // GPU Child Order Flags #define GCO_LIST_INIT NVBIT(0) // entry is used for init ordering (DO NOT USE) #define GCO_LIST_LOAD NVBIT(1) // entry is used for load and postload ordering (DO NOT USE) @@ -338,7 +392,7 @@ } GPU_CHILD_ITER; typedef GPU_CHILD_ITER ENGSTATE_ITER; -typedef GPU_CHILD_ITER PMUCLIENT_ITER; +typedef GPU_CHILD_ITER PMU_CLIENT_IMPLEMENTER_ITER; // // Object 'get' macros for GPU relative object retrievals. @@ -490,16 +544,6 @@ NvU32 PCIRevisionID; NvU32 Subrevision; - // - // ImplentationExternal and ArchitectureExternal are only valid if they are - // not both zero. They are used when we want to report a different - // arch/imp to an external client. For example, MCP73 is almost the same - // as MCP67, so we report the MCP67 arch/imp to external clients of MCP73. - // (If an MCP73 client really needs to know that it is running on MCP73 - // instead of MCP67, it should check capability bits.) - // - NvU32 ImplementationExternal; - NvU32 ArchitectureExternal; } GPUIDINFO; @@ -509,7 +553,6 @@ NvU32 arch; NvU32 majorRev; NvU32 minorRev; - NvU32 devIDStrap; NvU32 minorExtRev; } PMCBOOT0; @@ -519,7 +562,6 @@ NvU32 arch; NvU32 majorRev; NvU32 minorRev; - NvU32 devIDStrap; NvU32 minorExtRev; } PMCBOOT42; @@ -595,6 +637,13 @@ PORTDATA boardDownstreamPort; // If there is no BR03 these data are not set. } GPUCLDATA; +// For SLI Support Using Peer Model +typedef struct +{ + OBJGPU *pGpu; // Mapping from the local pinset number (i.e. array index) to peer GPU + NvU32 pinset; // Mapping from the local pinset number (i.e. array index) to peer pinset number +} _GPU_SLI_PEER; + // // Flags for gpuStateLoad() and gpuStateUnload() routines. Flags *must* be used @@ -778,7 +827,11 @@ // parsing the DEVICE_INFO2 table during init. // -typedef struct NV2080_CTRL_INTERNAL_DEVICE_INFO DEVICE_INFO2_TABLE; +typedef struct NV2080_CTRL_INTERNAL_DEVICE_INFO DEVICE_INFO2_ENTRY; + + +//! Value of DEV_GROUP_ID used in gpuGetDeviceEntryByType for any group ID. +#define DEVICE_INFO2_ENTRY_GROUP_ID_ANY (-1) #define NV_GPU_INTERNAL_DEVICE_HANDLE 0xABCD0080 #define NV_GPU_INTERNAL_SUBDEVICE_HANDLE 0xABCD2080 @@ -817,6 +870,7 @@ struct RmHalspecOwner *__nvoc_pbase_RmHalspecOwner; struct OBJTRACEABLE *__nvoc_pbase_OBJTRACEABLE; struct OBJGPU *__nvoc_pbase_OBJGPU; + NV_STATUS (*__gpuConstructDeviceInfoTable__)(struct OBJGPU *); NV_STATUS (*__gpuWriteBusConfigReg__)(struct OBJGPU *, NvU32, NvU32); NV_STATUS (*__gpuReadBusConfigReg__)(struct OBJGPU *, NvU32, NvU32 *); NV_STATUS (*__gpuReadBusConfigRegEx__)(struct OBJGPU *, NvU32, NvU32 *, THREAD_STATE_NODE *); @@ -832,19 +886,26 @@ NvU32 (*__gpuGetPhysAddrWidth__)(struct OBJGPU *, NV_ADDRESS_SPACE); NvBool (*__gpuFuseSupportsDisplay__)(struct OBJGPU *); NV_STATUS (*__gpuClearFbhubPoisonIntrForBug2924523__)(struct OBJGPU *); + NvBool (*__gpuCheckIfFbhubPoisonIntrPending__)(struct OBJGPU *); void (*__gpuReadDeviceId__)(struct OBJGPU *, NvU32 *, NvU32 *); - NV_STATUS (*__gpuConstructDeviceInfoTable__)(struct OBJGPU *); NvU64 (*__gpuGetFlaVasSize__)(struct OBJGPU *, NvBool); + void (*__gpuDetermineSelfHostedMode__)(struct OBJGPU *); + void (*__gpuDetermineMIGSupport__)(struct OBJGPU *); NvBool (*__gpuIsAtsSupportedWithSmcMemPartitioning__)(struct OBJGPU *); NvBool (*__gpuIsSliCapableWithoutDisplay__)(struct OBJGPU *); - GPU_FABRIC_PROBE_INFO *pGpuFabricProbeInfo; + NvBool (*__gpuIsCCEnabledInHw__)(struct OBJGPU *); + NvBool (*__gpuIsDevModeEnabledInHw__)(struct OBJGPU *); + NvBool (*__gpuIsCtxBufAllocInPmaSupported__)(struct OBJGPU *); + NV_STATUS (*__gpuWaitForGfwBootComplete__)(struct OBJGPU *); + NvBool PDB_PROP_GPU_HIGH_SPEED_BRIDGE_CONNECTED; + NvBool bVideoLinkDisabled; + GPU_FABRIC_PROBE_INFO_KERNEL *pGpuFabricProbeInfoKernel; NvU32 moduleId; NvU8 nvswitchSupport; NvBool PDB_PROP_GPU_IN_STANDBY; NvBool PDB_PROP_GPU_IN_HIBERNATE; NvBool PDB_PROP_GPU_IN_PM_CODEPATH; NvBool PDB_PROP_GPU_IN_PM_RESUME_CODEPATH; - NvBool PDB_PROP_GPU_PM_RESUME_WAR_BUG_3936017_ENABLED; NvBool PDB_PROP_GPU_STATE_INITIALIZED; NvBool PDB_PROP_GPU_EMULATION; NvBool PDB_PROP_GPU_PRIMARY_DEVICE; @@ -896,8 +957,16 @@ NvBool PDB_PROP_GPU_DO_NOT_CHECK_REG_ACCESS_IN_PM_CODEPATH; NvBool PDB_PROP_GPU_EXTERNAL_HEAP_CONTROL; NvBool PDB_PROP_GPU_IS_MOBILE; + NvBool PDB_PROP_GPU_READ_MULTIPLE_EDID_BLOCKS_VIA_ACPI_DDC; + NvBool PDB_PROP_GPU_RTD3_GC6_SUPPORTED; NvBool PDB_PROP_GPU_RTD3_GC6_ACTIVE; NvBool PDB_PROP_GPU_FAST_GC6_ACTIVE; + NvBool PDB_PROP_GPU_UNIX_DYNAMIC_POWER_SUPPORTED; + NvBool PDB_PROP_GPU_MOVE_CTX_BUFFERS_TO_PMA; + NvBool PDB_PROP_GPU_LEGACY_GCOFF_SUPPORTED; + NvBool PDB_PROP_GPU_RTD3_GCOFF_SUPPORTED; + NvBool PDB_PROP_GPU_GCOFF_STATE_ENTERING; + NvBool PDB_PROP_GPU_GCOFF_STATE_ENTERED; NvBool PDB_PROP_GPU_ACCOUNTING_ON; NvBool PDB_PROP_GPU_INACCESSIBLE; NvBool PDB_PROP_GPU_NVLINK_SYSMEM; @@ -911,7 +980,6 @@ NvBool PDB_PROP_GPU_IGNORE_REPLAYABLE_FAULTS; NvBool PDB_PROP_GPU_IS_VIRTUALIZATION_MODE_HOST_VGPU; NvBool PDB_PROP_GPU_IS_VIRTUALIZATION_MODE_HOST_VSGA; - NvBool PDB_PROP_GPU_MOVE_CTX_BUFFERS_TO_PMA; NvBool PDB_PROP_GPU_NVLINK_P2P_LOOPBACK_DISABLED; NvBool PDB_PROP_GPU_NV_USERMODE_ENABLED; NvBool PDB_PROP_GPU_IN_FATAL_ERROR; @@ -921,6 +989,13 @@ NvBool PDB_PROP_GPU_GSYNC_III_ATTACHED; NvBool PDB_PROP_GPU_QSYNC_II_ATTACHED; NvBool PDB_PROP_GPU_SRIOV_HEAVY_FORCE_INVALIDATE_ALL_PDBS_WAR_BUG3896322; + NvBool PDB_PROP_GPU_CC_FEATURE_CAPABLE; + NvBool PDB_PROP_GPU_APM_FEATURE_CAPABLE; + NvBool PDB_PROP_GPU_EXTENDED_GSP_RM_INITIALIZATION_TIMEOUT_FOR_VGX; + NvBool PDB_PROP_GPU_SKIP_TABLE_CE_MAP; + NvBool PDB_PROP_GPU_CHIP_SUPPORTS_RTD3_DEF; + NvBool PDB_PROP_GPU_FORCE_PERF_BIOS_LEVEL; + NvBool PDB_PROP_GPU_FASTPATH_SEQ_ENABLED; OS_GPU_INFO *pOsGpuInfo; OS_RM_CAPS *pOsRmCaps; NvU32 halImpl; @@ -938,6 +1013,7 @@ NvU32 gpuPhysicalId; NvU32 gpuTerminatedLinkMask; NvBool gpuLinkTerminationEnabled; + NvBool gspRmInitialized; _GPU_PCIE_PEER_CLIQUE pciePeerClique; NvU32 i2cPortForExtdev; GPUIDINFO idInfo; @@ -964,7 +1040,7 @@ RmPhysAddr dmaStartAddress; NvU32 gpuDeviceMapCount; DEVICE_MAPPING deviceMappings[60]; - PIO_APERTURE pIOApertures[12]; + struct IoAperture *pIOApertures[12]; DEVICE_MAPPING *pDeviceMappingsByDeviceInstance[12]; void *gpuCfgAddr; TIMEOUT_DATA timeoutData; @@ -1004,6 +1080,7 @@ struct OBJGPUMON *pGpuMon; struct OBJSWENG *pSwEng; struct KernelFsp *pKernelFsp; + struct ConfidentialCompute *pConfCompute; struct KernelCcu *pKernelCcu; HWBC_LIST *pHWBCList; GPUCLDATA gpuClData; @@ -1036,7 +1113,7 @@ NvHandle hDefaultClientShareDevice; NvHandle hDefaultClientShareSubDevice; NvU32 externalKernelClientCount; - DEVICE_INFO2_TABLE *pDeviceInfoTable; + DEVICE_INFO2_ENTRY *pDeviceInfoTable; NvU32 numDeviceInfoEntries; NvHandle hInternalClient; NvHandle hInternalDevice; @@ -1064,11 +1141,13 @@ NvBool bIsVirtualWithSriov; NvU32 P2PPeerGpuCount; GPU_P2P_PEER_GPU_CAPS P2PPeerGpuCaps[32]; - NvBool bCpuFirmwareHandlesFbEccInterruptEnabled; + NvBool bIsSelfHosted; NvBool bStateLoading; NvBool bStateUnloading; NvBool bStateLoaded; NvBool bFullyConstructed; + NvBool bRecoveryMarginPresent; + NvBool bBf3WarBug4040336Enabled; NvBool bUnifiedMemorySpaceEnabled; NvBool bSriovEnabled; NvBool bWarBug200577889SriovHeavyEnabled; @@ -1103,6 +1182,7 @@ NvBool bIsNvidiaNvs; NvBool bIsTitan; NvBool bIsTesla; + NvBool bIsAC; BRANDING_TYPE brandingCache; NvBool bComputePolicyTimesliceSupported; NvBool bGlobalPoisonFuseEnabled; @@ -1112,7 +1192,11 @@ NvU8 fabricProbeSlowdownThreshold; NvBool bVgpuGspPluginOffloadEnabled; NvBool bSriovCapable; + NvBool bRecheckSliSupportAtResume; + _GPU_SLI_PEER peer[2]; + NvBool bIsGspOwnedFaultBuffersEnabled; NvBool bEnableBar1SparseForFillPteMemUnmap; + _GPU_GC6_STATE gc6State; }; #ifndef __NVOC_CLASS_OBJGPU_TYPEDEF__ @@ -1138,8 +1222,12 @@ #define PDB_PROP_GPU_EXTERNAL_HEAP_CONTROL_BASE_CAST #define PDB_PROP_GPU_EXTERNAL_HEAP_CONTROL_BASE_NAME PDB_PROP_GPU_EXTERNAL_HEAP_CONTROL +#define PDB_PROP_GPU_RTD3_GC6_SUPPORTED_BASE_CAST +#define PDB_PROP_GPU_RTD3_GC6_SUPPORTED_BASE_NAME PDB_PROP_GPU_RTD3_GC6_SUPPORTED #define PDB_PROP_GPU_IS_VIRTUALIZATION_MODE_HOST_VGPU_BASE_CAST #define PDB_PROP_GPU_IS_VIRTUALIZATION_MODE_HOST_VGPU_BASE_NAME PDB_PROP_GPU_IS_VIRTUALIZATION_MODE_HOST_VGPU +#define PDB_PROP_GPU_VGPU_BIG_PAGE_SIZE_64K_BASE_CAST +#define PDB_PROP_GPU_VGPU_BIG_PAGE_SIZE_64K_BASE_NAME PDB_PROP_GPU_VGPU_BIG_PAGE_SIZE_64K #define PDB_PROP_GPU_INACCESSIBLE_BASE_CAST #define PDB_PROP_GPU_INACCESSIBLE_BASE_NAME PDB_PROP_GPU_INACCESSIBLE #define PDB_PROP_GPU_DO_NOT_CHECK_REG_ACCESS_IN_PM_CODEPATH_BASE_CAST @@ -1156,10 +1244,12 @@ #define PDB_PROP_GPU_IS_COT_ENABLED_BASE_NAME PDB_PROP_GPU_IS_COT_ENABLED #define PDB_PROP_GPU_COHERENT_CPU_MAPPING_BASE_CAST #define PDB_PROP_GPU_COHERENT_CPU_MAPPING_BASE_NAME PDB_PROP_GPU_COHERENT_CPU_MAPPING -#define PDB_PROP_GPU_UPSTREAM_PORT_L0S_UNSUPPORTED_BASE_CAST -#define PDB_PROP_GPU_UPSTREAM_PORT_L0S_UNSUPPORTED_BASE_NAME PDB_PROP_GPU_UPSTREAM_PORT_L0S_UNSUPPORTED +#define PDB_PROP_GPU_HIGH_SPEED_BRIDGE_CONNECTED_BASE_CAST +#define PDB_PROP_GPU_HIGH_SPEED_BRIDGE_CONNECTED_BASE_NAME PDB_PROP_GPU_HIGH_SPEED_BRIDGE_CONNECTED #define PDB_PROP_GPU_TEGRA_SOC_NVDISPLAY_BASE_CAST #define PDB_PROP_GPU_TEGRA_SOC_NVDISPLAY_BASE_NAME PDB_PROP_GPU_TEGRA_SOC_NVDISPLAY +#define PDB_PROP_GPU_UPSTREAM_PORT_L0S_UNSUPPORTED_BASE_CAST +#define PDB_PROP_GPU_UPSTREAM_PORT_L0S_UNSUPPORTED_BASE_NAME PDB_PROP_GPU_UPSTREAM_PORT_L0S_UNSUPPORTED #define PDB_PROP_GPU_SLI_LINK_ACTIVE_BASE_CAST #define PDB_PROP_GPU_SLI_LINK_ACTIVE_BASE_NAME PDB_PROP_GPU_SLI_LINK_ACTIVE #define PDB_PROP_GPU_IN_TCC_MODE_BASE_CAST @@ -1178,12 +1268,20 @@ #define PDB_PROP_GPU_RESETLESS_MIG_SUPPORTED_BASE_NAME PDB_PROP_GPU_RESETLESS_MIG_SUPPORTED #define PDB_PROP_GPU_MSHYBRID_GC6_ACTIVE_BASE_CAST #define PDB_PROP_GPU_MSHYBRID_GC6_ACTIVE_BASE_NAME PDB_PROP_GPU_MSHYBRID_GC6_ACTIVE +#define PDB_PROP_GPU_READ_MULTIPLE_EDID_BLOCKS_VIA_ACPI_DDC_BASE_CAST +#define PDB_PROP_GPU_READ_MULTIPLE_EDID_BLOCKS_VIA_ACPI_DDC_BASE_NAME PDB_PROP_GPU_READ_MULTIPLE_EDID_BLOCKS_VIA_ACPI_DDC #define PDB_PROP_GPU_VC_CAPABILITY_SUPPORTED_BASE_CAST #define PDB_PROP_GPU_VC_CAPABILITY_SUPPORTED_BASE_NAME PDB_PROP_GPU_VC_CAPABILITY_SUPPORTED #define PDB_PROP_GPU_RM_UNLINKED_SLI_BASE_CAST #define PDB_PROP_GPU_RM_UNLINKED_SLI_BASE_NAME PDB_PROP_GPU_RM_UNLINKED_SLI +#define PDB_PROP_GPU_FORCE_PERF_BIOS_LEVEL_BASE_CAST +#define PDB_PROP_GPU_FORCE_PERF_BIOS_LEVEL_BASE_NAME PDB_PROP_GPU_FORCE_PERF_BIOS_LEVEL +#define PDB_PROP_GPU_FASTPATH_SEQ_ENABLED_BASE_CAST +#define PDB_PROP_GPU_FASTPATH_SEQ_ENABLED_BASE_NAME PDB_PROP_GPU_FASTPATH_SEQ_ENABLED #define PDB_PROP_GPU_IS_UEFI_BASE_CAST #define PDB_PROP_GPU_IS_UEFI_BASE_NAME PDB_PROP_GPU_IS_UEFI +#define PDB_PROP_GPU_SKIP_TABLE_CE_MAP_BASE_CAST +#define PDB_PROP_GPU_SKIP_TABLE_CE_MAP_BASE_NAME PDB_PROP_GPU_SKIP_TABLE_CE_MAP #define PDB_PROP_GPU_IN_SECONDARY_BUS_RESET_BASE_CAST #define PDB_PROP_GPU_IN_SECONDARY_BUS_RESET_BASE_NAME PDB_PROP_GPU_IN_SECONDARY_BUS_RESET #define PDB_PROP_GPU_OPTIMIZE_SPARSE_TEXTURE_BY_DEFAULT_BASE_CAST @@ -1198,6 +1296,8 @@ #define PDB_PROP_GPU_IS_MOBILE_BASE_NAME PDB_PROP_GPU_IS_MOBILE #define PDB_PROP_GPU_RTD3_GC6_ACTIVE_BASE_CAST #define PDB_PROP_GPU_RTD3_GC6_ACTIVE_BASE_NAME PDB_PROP_GPU_RTD3_GC6_ACTIVE +#define PDB_PROP_GPU_CC_FEATURE_CAPABLE_BASE_CAST +#define PDB_PROP_GPU_CC_FEATURE_CAPABLE_BASE_NAME PDB_PROP_GPU_CC_FEATURE_CAPABLE #define PDB_PROP_GPU_ALTERNATE_TREE_ENABLED_BASE_CAST #define PDB_PROP_GPU_ALTERNATE_TREE_ENABLED_BASE_NAME PDB_PROP_GPU_ALTERNATE_TREE_ENABLED #define PDB_PROP_GPU_PERSISTENT_SW_STATE_BASE_CAST @@ -1220,6 +1320,8 @@ #define PDB_PROP_GPU_VGPU_OFFLOAD_CAPABLE_BASE_NAME PDB_PROP_GPU_VGPU_OFFLOAD_CAPABLE #define PDB_PROP_GPU_CAN_OPTIMIZE_COMPUTE_USE_CASE_BASE_CAST #define PDB_PROP_GPU_CAN_OPTIMIZE_COMPUTE_USE_CASE_BASE_NAME PDB_PROP_GPU_CAN_OPTIMIZE_COMPUTE_USE_CASE +#define PDB_PROP_GPU_GCOFF_STATE_ENTERING_BASE_CAST +#define PDB_PROP_GPU_GCOFF_STATE_ENTERING_BASE_NAME PDB_PROP_GPU_GCOFF_STATE_ENTERING #define PDB_PROP_GPU_ACCOUNTING_ON_BASE_CAST #define PDB_PROP_GPU_ACCOUNTING_ON_BASE_NAME PDB_PROP_GPU_ACCOUNTING_ON #define PDB_PROP_GPU_IN_HIBERNATE_BASE_CAST @@ -1230,6 +1332,8 @@ #define PDB_PROP_GPU_ENABLE_IOMMU_SUPPORT_BASE_NAME PDB_PROP_GPU_ENABLE_IOMMU_SUPPORT #define PDB_PROP_GPU_IN_TIMEOUT_RECOVERY_BASE_CAST #define PDB_PROP_GPU_IN_TIMEOUT_RECOVERY_BASE_NAME PDB_PROP_GPU_IN_TIMEOUT_RECOVERY +#define PDB_PROP_GPU_GCOFF_STATE_ENTERED_BASE_CAST +#define PDB_PROP_GPU_GCOFF_STATE_ENTERED_BASE_NAME PDB_PROP_GPU_GCOFF_STATE_ENTERED #define PDB_PROP_GPU_FAST_GC6_ACTIVE_BASE_CAST #define PDB_PROP_GPU_FAST_GC6_ACTIVE_BASE_NAME PDB_PROP_GPU_FAST_GC6_ACTIVE #define PDB_PROP_GPU_IN_FULLCHIP_RESET_BASE_CAST @@ -1244,8 +1348,8 @@ #define PDB_PROP_GPU_IS_BR03_PRESENT_BASE_NAME PDB_PROP_GPU_IS_BR03_PRESENT #define PDB_PROP_GPU_IS_GEMINI_BASE_CAST #define PDB_PROP_GPU_IS_GEMINI_BASE_NAME PDB_PROP_GPU_IS_GEMINI -#define PDB_PROP_GPU_SRIOV_HEAVY_FORCE_INVALIDATE_ALL_PDBS_WAR_BUG3896322_BASE_CAST -#define PDB_PROP_GPU_SRIOV_HEAVY_FORCE_INVALIDATE_ALL_PDBS_WAR_BUG3896322_BASE_NAME PDB_PROP_GPU_SRIOV_HEAVY_FORCE_INVALIDATE_ALL_PDBS_WAR_BUG3896322 +#define PDB_PROP_GPU_UNIX_DYNAMIC_POWER_SUPPORTED_BASE_CAST +#define PDB_PROP_GPU_UNIX_DYNAMIC_POWER_SUPPORTED_BASE_NAME PDB_PROP_GPU_UNIX_DYNAMIC_POWER_SUPPORTED #define PDB_PROP_GPU_STATE_INITIALIZED_BASE_CAST #define PDB_PROP_GPU_STATE_INITIALIZED_BASE_NAME PDB_PROP_GPU_STATE_INITIALIZED #define PDB_PROP_GPU_NV_USERMODE_ENABLED_BASE_CAST @@ -1254,12 +1358,16 @@ #define PDB_PROP_GPU_IS_MXM_3X_BASE_NAME PDB_PROP_GPU_IS_MXM_3X #define PDB_PROP_GPU_ALTERNATE_TREE_HANDLE_LOCKLESS_BASE_CAST #define PDB_PROP_GPU_ALTERNATE_TREE_HANDLE_LOCKLESS_BASE_NAME PDB_PROP_GPU_ALTERNATE_TREE_HANDLE_LOCKLESS +#define PDB_PROP_GPU_SRIOV_HEAVY_FORCE_INVALIDATE_ALL_PDBS_WAR_BUG3896322_BASE_CAST +#define PDB_PROP_GPU_SRIOV_HEAVY_FORCE_INVALIDATE_ALL_PDBS_WAR_BUG3896322_BASE_NAME PDB_PROP_GPU_SRIOV_HEAVY_FORCE_INVALIDATE_ALL_PDBS_WAR_BUG3896322 #define PDB_PROP_GPU_GSYNC_III_ATTACHED_BASE_CAST #define PDB_PROP_GPU_GSYNC_III_ATTACHED_BASE_NAME PDB_PROP_GPU_GSYNC_III_ATTACHED #define PDB_PROP_GPU_QSYNC_II_ATTACHED_BASE_CAST #define PDB_PROP_GPU_QSYNC_II_ATTACHED_BASE_NAME PDB_PROP_GPU_QSYNC_II_ATTACHED #define PDB_PROP_GPU_IS_BR04_PRESENT_BASE_CAST #define PDB_PROP_GPU_IS_BR04_PRESENT_BASE_NAME PDB_PROP_GPU_IS_BR04_PRESENT +#define PDB_PROP_GPU_CHIP_SUPPORTS_RTD3_DEF_BASE_CAST +#define PDB_PROP_GPU_CHIP_SUPPORTS_RTD3_DEF_BASE_NAME PDB_PROP_GPU_CHIP_SUPPORTS_RTD3_DEF #define PDB_PROP_GPU_OPTIMUS_GOLD_CFG_SPACE_RESTORE_BASE_CAST #define PDB_PROP_GPU_OPTIMUS_GOLD_CFG_SPACE_RESTORE_BASE_NAME PDB_PROP_GPU_OPTIMUS_GOLD_CFG_SPACE_RESTORE #define PDB_PROP_GPU_IS_ALL_INST_IN_SYSMEM_BASE_CAST @@ -1270,18 +1378,20 @@ #define PDB_PROP_GPU_UPSTREAM_PORT_L1_POR_SUPPORTED_BASE_NAME PDB_PROP_GPU_UPSTREAM_PORT_L1_POR_SUPPORTED #define PDB_PROP_GPU_ZERO_FB_BASE_CAST #define PDB_PROP_GPU_ZERO_FB_BASE_NAME PDB_PROP_GPU_ZERO_FB -#define PDB_PROP_GPU_PM_RESUME_WAR_BUG_3936017_ENABLED_BASE_CAST -#define PDB_PROP_GPU_PM_RESUME_WAR_BUG_3936017_ENABLED_BASE_NAME PDB_PROP_GPU_PM_RESUME_WAR_BUG_3936017_ENABLED #define PDB_PROP_GPU_SWRL_GRANULAR_LOCKING_BASE_CAST #define PDB_PROP_GPU_SWRL_GRANULAR_LOCKING_BASE_NAME PDB_PROP_GPU_SWRL_GRANULAR_LOCKING -#define PDB_PROP_GPU_TEGRA_SOC_IGPU_BASE_CAST -#define PDB_PROP_GPU_TEGRA_SOC_IGPU_BASE_NAME PDB_PROP_GPU_TEGRA_SOC_IGPU #define PDB_PROP_GPU_SKIP_CE_MAPPINGS_NO_NVLINK_BASE_CAST #define PDB_PROP_GPU_SKIP_CE_MAPPINGS_NO_NVLINK_BASE_NAME PDB_PROP_GPU_SKIP_CE_MAPPINGS_NO_NVLINK +#define PDB_PROP_GPU_TEGRA_SOC_IGPU_BASE_CAST +#define PDB_PROP_GPU_TEGRA_SOC_IGPU_BASE_NAME PDB_PROP_GPU_TEGRA_SOC_IGPU +#define PDB_PROP_GPU_RTD3_GCOFF_SUPPORTED_BASE_CAST +#define PDB_PROP_GPU_RTD3_GCOFF_SUPPORTED_BASE_NAME PDB_PROP_GPU_RTD3_GCOFF_SUPPORTED #define PDB_PROP_GPU_ATS_SUPPORTED_BASE_CAST #define PDB_PROP_GPU_ATS_SUPPORTED_BASE_NAME PDB_PROP_GPU_ATS_SUPPORTED #define PDB_PROP_GPU_EMULATION_BASE_CAST #define PDB_PROP_GPU_EMULATION_BASE_NAME PDB_PROP_GPU_EMULATION +#define PDB_PROP_GPU_APM_FEATURE_CAPABLE_BASE_CAST +#define PDB_PROP_GPU_APM_FEATURE_CAPABLE_BASE_NAME PDB_PROP_GPU_APM_FEATURE_CAPABLE #define PDB_PROP_GPU_IGNORE_REPLAYABLE_FAULTS_BASE_CAST #define PDB_PROP_GPU_IGNORE_REPLAYABLE_FAULTS_BASE_NAME PDB_PROP_GPU_IGNORE_REPLAYABLE_FAULTS #define PDB_PROP_GPU_PRIMARY_DEVICE_BASE_CAST @@ -1296,8 +1406,10 @@ #define PDB_PROP_GPU_ENABLE_REG_ACCESS_IN_LOW_POWER_FOR_SIM_SRTEST_BASE_NAME PDB_PROP_GPU_ENABLE_REG_ACCESS_IN_LOW_POWER_FOR_SIM_SRTEST #define PDB_PROP_GPU_IS_LOST_BASE_CAST #define PDB_PROP_GPU_IS_LOST_BASE_NAME PDB_PROP_GPU_IS_LOST -#define PDB_PROP_GPU_VGPU_BIG_PAGE_SIZE_64K_BASE_CAST -#define PDB_PROP_GPU_VGPU_BIG_PAGE_SIZE_64K_BASE_NAME PDB_PROP_GPU_VGPU_BIG_PAGE_SIZE_64K +#define PDB_PROP_GPU_LEGACY_GCOFF_SUPPORTED_BASE_CAST +#define PDB_PROP_GPU_LEGACY_GCOFF_SUPPORTED_BASE_NAME PDB_PROP_GPU_LEGACY_GCOFF_SUPPORTED +#define PDB_PROP_GPU_EXTENDED_GSP_RM_INITIALIZATION_TIMEOUT_FOR_VGX_BASE_CAST +#define PDB_PROP_GPU_EXTENDED_GSP_RM_INITIALIZATION_TIMEOUT_FOR_VGX_BASE_NAME PDB_PROP_GPU_EXTENDED_GSP_RM_INITIALIZATION_TIMEOUT_FOR_VGX NV_STATUS __nvoc_objCreateDynamic_OBJGPU(OBJGPU**, Dynamic*, NvU32, va_list); @@ -1308,6 +1420,8 @@ #define __objCreate_OBJGPU(ppNewObj, pParent, createFlags, ChipHal_arch, ChipHal_impl, ChipHal_hidrev, RmVariantHal_rmVariant, DispIpHal_ipver, arg_gpuInstance) \ __nvoc_objCreate_OBJGPU((ppNewObj), staticCast((pParent), Dynamic), (createFlags), ChipHal_arch, ChipHal_impl, ChipHal_hidrev, RmVariantHal_rmVariant, DispIpHal_ipver, arg_gpuInstance) +#define gpuConstructDeviceInfoTable(pGpu) gpuConstructDeviceInfoTable_DISPATCH(pGpu) +#define gpuConstructDeviceInfoTable_HAL(pGpu) gpuConstructDeviceInfoTable_DISPATCH(pGpu) #define gpuWriteBusConfigReg(pGpu, index, value) gpuWriteBusConfigReg_DISPATCH(pGpu, index, value) #define gpuWriteBusConfigReg_HAL(pGpu, index, value) gpuWriteBusConfigReg_DISPATCH(pGpu, index, value) #define gpuReadBusConfigReg(pGpu, index, data) gpuReadBusConfigReg_DISPATCH(pGpu, index, data) @@ -1338,16 +1452,28 @@ #define gpuFuseSupportsDisplay_HAL(pGpu) gpuFuseSupportsDisplay_DISPATCH(pGpu) #define gpuClearFbhubPoisonIntrForBug2924523(pGpu) gpuClearFbhubPoisonIntrForBug2924523_DISPATCH(pGpu) #define gpuClearFbhubPoisonIntrForBug2924523_HAL(pGpu) gpuClearFbhubPoisonIntrForBug2924523_DISPATCH(pGpu) +#define gpuCheckIfFbhubPoisonIntrPending(pGpu) gpuCheckIfFbhubPoisonIntrPending_DISPATCH(pGpu) +#define gpuCheckIfFbhubPoisonIntrPending_HAL(pGpu) gpuCheckIfFbhubPoisonIntrPending_DISPATCH(pGpu) #define gpuReadDeviceId(pGpu, arg0, arg1) gpuReadDeviceId_DISPATCH(pGpu, arg0, arg1) #define gpuReadDeviceId_HAL(pGpu, arg0, arg1) gpuReadDeviceId_DISPATCH(pGpu, arg0, arg1) -#define gpuConstructDeviceInfoTable(pGpu) gpuConstructDeviceInfoTable_DISPATCH(pGpu) -#define gpuConstructDeviceInfoTable_HAL(pGpu) gpuConstructDeviceInfoTable_DISPATCH(pGpu) #define gpuGetFlaVasSize(pGpu, bNvswitchVirtualization) gpuGetFlaVasSize_DISPATCH(pGpu, bNvswitchVirtualization) #define gpuGetFlaVasSize_HAL(pGpu, bNvswitchVirtualization) gpuGetFlaVasSize_DISPATCH(pGpu, bNvswitchVirtualization) +#define gpuDetermineSelfHostedMode(pGpu) gpuDetermineSelfHostedMode_DISPATCH(pGpu) +#define gpuDetermineSelfHostedMode_HAL(pGpu) gpuDetermineSelfHostedMode_DISPATCH(pGpu) +#define gpuDetermineMIGSupport(pGpu) gpuDetermineMIGSupport_DISPATCH(pGpu) +#define gpuDetermineMIGSupport_HAL(pGpu) gpuDetermineMIGSupport_DISPATCH(pGpu) #define gpuIsAtsSupportedWithSmcMemPartitioning(pGpu) gpuIsAtsSupportedWithSmcMemPartitioning_DISPATCH(pGpu) #define gpuIsAtsSupportedWithSmcMemPartitioning_HAL(pGpu) gpuIsAtsSupportedWithSmcMemPartitioning_DISPATCH(pGpu) #define gpuIsSliCapableWithoutDisplay(pGpu) gpuIsSliCapableWithoutDisplay_DISPATCH(pGpu) #define gpuIsSliCapableWithoutDisplay_HAL(pGpu) gpuIsSliCapableWithoutDisplay_DISPATCH(pGpu) +#define gpuIsCCEnabledInHw(pGpu) gpuIsCCEnabledInHw_DISPATCH(pGpu) +#define gpuIsCCEnabledInHw_HAL(pGpu) gpuIsCCEnabledInHw_DISPATCH(pGpu) +#define gpuIsDevModeEnabledInHw(pGpu) gpuIsDevModeEnabledInHw_DISPATCH(pGpu) +#define gpuIsDevModeEnabledInHw_HAL(pGpu) gpuIsDevModeEnabledInHw_DISPATCH(pGpu) +#define gpuIsCtxBufAllocInPmaSupported(pGpu) gpuIsCtxBufAllocInPmaSupported_DISPATCH(pGpu) +#define gpuIsCtxBufAllocInPmaSupported_HAL(pGpu) gpuIsCtxBufAllocInPmaSupported_DISPATCH(pGpu) +#define gpuWaitForGfwBootComplete(pGpu) gpuWaitForGfwBootComplete_DISPATCH(pGpu) +#define gpuWaitForGfwBootComplete_HAL(pGpu) gpuWaitForGfwBootComplete_DISPATCH(pGpu) static inline NV_STATUS gpuConstructPhysical_56cd7a(struct OBJGPU *pGpu) { return NV_OK; } @@ -1573,6 +1699,22 @@ #define gpuPowerManagementResumePostLoadPhysical_HAL(pGpu) gpuPowerManagementResumePostLoadPhysical(pGpu) +static inline NV_STATUS gpuInitializeMemDescFromPromotedCtx_46f6a7(struct OBJGPU *pGpu, MEMORY_DESCRIPTOR **ppMemDesc, NvU64 gpuPhysAddr, NvU64 size, NvU32 physAttr, NvBool bIsCallingContextVgpuPlugin) { + return NV_ERR_NOT_SUPPORTED; +} + + +#ifdef __nvoc_gpu_h_disabled +static inline NV_STATUS gpuInitializeMemDescFromPromotedCtx(struct OBJGPU *pGpu, MEMORY_DESCRIPTOR **ppMemDesc, NvU64 gpuPhysAddr, NvU64 size, NvU32 physAttr, NvBool bIsCallingContextVgpuPlugin) { + NV_ASSERT_FAILED_PRECOMP("OBJGPU was disabled!"); + return NV_ERR_NOT_SUPPORTED; +} +#else //__nvoc_gpu_h_disabled +#define gpuInitializeMemDescFromPromotedCtx(pGpu, ppMemDesc, gpuPhysAddr, size, physAttr, bIsCallingContextVgpuPlugin) gpuInitializeMemDescFromPromotedCtx_46f6a7(pGpu, ppMemDesc, gpuPhysAddr, size, physAttr, bIsCallingContextVgpuPlugin) +#endif //__nvoc_gpu_h_disabled + +#define gpuInitializeMemDescFromPromotedCtx_HAL(pGpu, ppMemDesc, gpuPhysAddr, size, physAttr, bIsCallingContextVgpuPlugin) gpuInitializeMemDescFromPromotedCtx(pGpu, ppMemDesc, gpuPhysAddr, size, physAttr, bIsCallingContextVgpuPlugin) + NV_STATUS gpuGetNameString_KERNEL(struct OBJGPU *pGpu, NvU32 arg0, void *arg1); NV_STATUS gpuGetNameString_IMPL(struct OBJGPU *pGpu, NvU32 arg0, void *arg1); @@ -1679,6 +1821,21 @@ #define gpuInitProperties_HAL(pGpu) gpuInitProperties(pGpu) +static inline void gpuSetThreadBcState_b3696a(struct OBJGPU *pGpu, NvBool arg0) { + return; +} + + +#ifdef __nvoc_gpu_h_disabled +static inline void gpuSetThreadBcState(struct OBJGPU *pGpu, NvBool arg0) { + NV_ASSERT_FAILED_PRECOMP("OBJGPU was disabled!"); +} +#else //__nvoc_gpu_h_disabled +#define gpuSetThreadBcState(pGpu, arg0) gpuSetThreadBcState_b3696a(pGpu, arg0) +#endif //__nvoc_gpu_h_disabled + +#define gpuSetThreadBcState_HAL(pGpu, arg0) gpuSetThreadBcState(pGpu, arg0) + static inline void gpuDeterminePersistantIllumSettings_b3696a(struct OBJGPU *pGpu) { return; } @@ -1795,7 +1952,23 @@ #define gpuGetDmaEndAddress_HAL(pGpu) gpuGetDmaEndAddress(pGpu) -static inline NV_STATUS gpuMarkDeviceForReset_46f6a7(struct OBJGPU *pGpu) { +static inline NV_STATUS gpuSetStateResetRequired_395e98(struct OBJGPU *pGpu, NvU32 exceptType) { + return NV_ERR_NOT_SUPPORTED; +} + + +#ifdef __nvoc_gpu_h_disabled +static inline NV_STATUS gpuSetStateResetRequired(struct OBJGPU *pGpu, NvU32 exceptType) { + NV_ASSERT_FAILED_PRECOMP("OBJGPU was disabled!"); + return NV_ERR_NOT_SUPPORTED; +} +#else //__nvoc_gpu_h_disabled +#define gpuSetStateResetRequired(pGpu, exceptType) gpuSetStateResetRequired_395e98(pGpu, exceptType) +#endif //__nvoc_gpu_h_disabled + +#define gpuSetStateResetRequired_HAL(pGpu, exceptType) gpuSetStateResetRequired(pGpu, exceptType) + +static inline NV_STATUS gpuMarkDeviceForReset_395e98(struct OBJGPU *pGpu) { return NV_ERR_NOT_SUPPORTED; } @@ -1806,12 +1979,48 @@ return NV_ERR_NOT_SUPPORTED; } #else //__nvoc_gpu_h_disabled -#define gpuMarkDeviceForReset(pGpu) gpuMarkDeviceForReset_46f6a7(pGpu) +#define gpuMarkDeviceForReset(pGpu) gpuMarkDeviceForReset_395e98(pGpu) #endif //__nvoc_gpu_h_disabled #define gpuMarkDeviceForReset_HAL(pGpu) gpuMarkDeviceForReset(pGpu) -static inline NV_STATUS gpuMarkDeviceForDrainAndReset_46f6a7(struct OBJGPU *pGpu) { +static inline NV_STATUS gpuUnmarkDeviceForReset_395e98(struct OBJGPU *pGpu) { + return NV_ERR_NOT_SUPPORTED; +} + + +#ifdef __nvoc_gpu_h_disabled +static inline NV_STATUS gpuUnmarkDeviceForReset(struct OBJGPU *pGpu) { + NV_ASSERT_FAILED_PRECOMP("OBJGPU was disabled!"); + return NV_ERR_NOT_SUPPORTED; +} +#else //__nvoc_gpu_h_disabled +#define gpuUnmarkDeviceForReset(pGpu) gpuUnmarkDeviceForReset_395e98(pGpu) +#endif //__nvoc_gpu_h_disabled + +#define gpuUnmarkDeviceForReset_HAL(pGpu) gpuUnmarkDeviceForReset(pGpu) + +static inline NV_STATUS gpuIsDeviceMarkedForReset_82f166(struct OBJGPU *pGpu, NvBool *pbResetRequired) { + *pbResetRequired = ((NvBool)(0 != 0)); + { + return NV_ERR_NOT_SUPPORTED; + } + ; +} + + +#ifdef __nvoc_gpu_h_disabled +static inline NV_STATUS gpuIsDeviceMarkedForReset(struct OBJGPU *pGpu, NvBool *pbResetRequired) { + NV_ASSERT_FAILED_PRECOMP("OBJGPU was disabled!"); + return NV_ERR_NOT_SUPPORTED; +} +#else //__nvoc_gpu_h_disabled +#define gpuIsDeviceMarkedForReset(pGpu, pbResetRequired) gpuIsDeviceMarkedForReset_82f166(pGpu, pbResetRequired) +#endif //__nvoc_gpu_h_disabled + +#define gpuIsDeviceMarkedForReset_HAL(pGpu, pbResetRequired) gpuIsDeviceMarkedForReset(pGpu, pbResetRequired) + +static inline NV_STATUS gpuMarkDeviceForDrainAndReset_395e98(struct OBJGPU *pGpu) { return NV_ERR_NOT_SUPPORTED; } @@ -1822,11 +2031,47 @@ return NV_ERR_NOT_SUPPORTED; } #else //__nvoc_gpu_h_disabled -#define gpuMarkDeviceForDrainAndReset(pGpu) gpuMarkDeviceForDrainAndReset_46f6a7(pGpu) +#define gpuMarkDeviceForDrainAndReset(pGpu) gpuMarkDeviceForDrainAndReset_395e98(pGpu) #endif //__nvoc_gpu_h_disabled #define gpuMarkDeviceForDrainAndReset_HAL(pGpu) gpuMarkDeviceForDrainAndReset(pGpu) +static inline NV_STATUS gpuUnmarkDeviceForDrainAndReset_395e98(struct OBJGPU *pGpu) { + return NV_ERR_NOT_SUPPORTED; +} + + +#ifdef __nvoc_gpu_h_disabled +static inline NV_STATUS gpuUnmarkDeviceForDrainAndReset(struct OBJGPU *pGpu) { + NV_ASSERT_FAILED_PRECOMP("OBJGPU was disabled!"); + return NV_ERR_NOT_SUPPORTED; +} +#else //__nvoc_gpu_h_disabled +#define gpuUnmarkDeviceForDrainAndReset(pGpu) gpuUnmarkDeviceForDrainAndReset_395e98(pGpu) +#endif //__nvoc_gpu_h_disabled + +#define gpuUnmarkDeviceForDrainAndReset_HAL(pGpu) gpuUnmarkDeviceForDrainAndReset(pGpu) + +static inline NV_STATUS gpuIsDeviceMarkedForDrainAndReset_244f65(struct OBJGPU *pGpu, NvBool *pbDrainRecommended) { + *pbDrainRecommended = ((NvBool)(0 != 0)); + { + return NV_ERR_NOT_SUPPORTED; + } + ; +} + + +#ifdef __nvoc_gpu_h_disabled +static inline NV_STATUS gpuIsDeviceMarkedForDrainAndReset(struct OBJGPU *pGpu, NvBool *pbDrainRecommended) { + NV_ASSERT_FAILED_PRECOMP("OBJGPU was disabled!"); + return NV_ERR_NOT_SUPPORTED; +} +#else //__nvoc_gpu_h_disabled +#define gpuIsDeviceMarkedForDrainAndReset(pGpu, pbDrainRecommended) gpuIsDeviceMarkedForDrainAndReset_244f65(pGpu, pbDrainRecommended) +#endif //__nvoc_gpu_h_disabled + +#define gpuIsDeviceMarkedForDrainAndReset_HAL(pGpu, pbDrainRecommended) gpuIsDeviceMarkedForDrainAndReset(pGpu, pbDrainRecommended) + static inline NvU32 gpuGetSliFingerPinsetMask_4a4dee(struct OBJGPU *pGpu) { return 0; } @@ -1874,6 +2119,20 @@ #define gpuDestroyOverrides_HAL(pGpu) gpuDestroyOverrides(pGpu) +NV_STATUS gpuPowerOff_KERNEL(struct OBJGPU *pGpu); + + +#ifdef __nvoc_gpu_h_disabled +static inline NV_STATUS gpuPowerOff(struct OBJGPU *pGpu) { + NV_ASSERT_FAILED_PRECOMP("OBJGPU was disabled!"); + return NV_ERR_NOT_SUPPORTED; +} +#else //__nvoc_gpu_h_disabled +#define gpuPowerOff(pGpu) gpuPowerOff_KERNEL(pGpu) +#endif //__nvoc_gpu_h_disabled + +#define gpuPowerOff_HAL(pGpu) gpuPowerOff(pGpu) + NV_STATUS gpuSetPower_GM107(struct OBJGPU *pGpu, NvU32 arg1, NvU32 arg2, NvU32 arg3); @@ -2163,6 +2422,19 @@ #define gpuDestroyDefaultClientShare_HAL(pGpu) gpuDestroyDefaultClientShare(pGpu) +void gpuUpdateUserSharedData_KERNEL(struct OBJGPU *pGpu); + + +#ifdef __nvoc_gpu_h_disabled +static inline void gpuUpdateUserSharedData(struct OBJGPU *pGpu) { + NV_ASSERT_FAILED_PRECOMP("OBJGPU was disabled!"); +} +#else //__nvoc_gpu_h_disabled +#define gpuUpdateUserSharedData(pGpu) gpuUpdateUserSharedData_KERNEL(pGpu) +#endif //__nvoc_gpu_h_disabled + +#define gpuUpdateUserSharedData_HAL(pGpu) gpuUpdateUserSharedData(pGpu) + void gpuGetTerminatedLinkMask_GA100(struct OBJGPU *pGpu, NvU32 arg0); @@ -2176,6 +2448,54 @@ #define gpuGetTerminatedLinkMask_HAL(pGpu, arg0) gpuGetTerminatedLinkMask(pGpu, arg0) +NV_STATUS gpuJtVersionSanityCheck_TU102(struct OBJGPU *pGpu); + + +#ifdef __nvoc_gpu_h_disabled +static inline NV_STATUS gpuJtVersionSanityCheck(struct OBJGPU *pGpu) { + NV_ASSERT_FAILED_PRECOMP("OBJGPU was disabled!"); + return NV_ERR_NOT_SUPPORTED; +} +#else //__nvoc_gpu_h_disabled +#define gpuJtVersionSanityCheck(pGpu) gpuJtVersionSanityCheck_TU102(pGpu) +#endif //__nvoc_gpu_h_disabled + +#define gpuJtVersionSanityCheck_HAL(pGpu) gpuJtVersionSanityCheck(pGpu) + +static inline NvBool gpuCompletedGC6PowerOff_cbe027(struct OBJGPU *pGpu) { + return ((NvBool)(0 == 0)); +} + +NvBool gpuCompletedGC6PowerOff_GV100(struct OBJGPU *pGpu); + + +#ifdef __nvoc_gpu_h_disabled +static inline NvBool gpuCompletedGC6PowerOff(struct OBJGPU *pGpu) { + NV_ASSERT_FAILED_PRECOMP("OBJGPU was disabled!"); + return NV_FALSE; +} +#else //__nvoc_gpu_h_disabled +#define gpuCompletedGC6PowerOff(pGpu) gpuCompletedGC6PowerOff_cbe027(pGpu) +#endif //__nvoc_gpu_h_disabled + +#define gpuCompletedGC6PowerOff_HAL(pGpu) gpuCompletedGC6PowerOff(pGpu) + +static inline NvBool gpuIsACPIPatchRequiredForBug2473619_491d52(struct OBJGPU *pGpu) { + return ((NvBool)(0 != 0)); +} + + +#ifdef __nvoc_gpu_h_disabled +static inline NvBool gpuIsACPIPatchRequiredForBug2473619(struct OBJGPU *pGpu) { + NV_ASSERT_FAILED_PRECOMP("OBJGPU was disabled!"); + return NV_FALSE; +} +#else //__nvoc_gpu_h_disabled +#define gpuIsACPIPatchRequiredForBug2473619(pGpu) gpuIsACPIPatchRequiredForBug2473619_491d52(pGpu) +#endif //__nvoc_gpu_h_disabled + +#define gpuIsACPIPatchRequiredForBug2473619_HAL(pGpu) gpuIsACPIPatchRequiredForBug2473619(pGpu) + NvU32 gpuGetActiveFBIOs_FWCLIENT(struct OBJGPU *pGpu); NvU32 gpuGetActiveFBIOs_GM107(struct OBJGPU *pGpu); @@ -2322,13 +2642,13 @@ #define gpuCheckIsP2PAllocated_HAL(pGpu) gpuCheckIsP2PAllocated(pGpu) -static inline void gpuDecodeDeviceInfoTableGroupId_b3696a(struct OBJGPU *pGpu, DEVICE_INFO2_TABLE *pEntry, NvU32 *pDeviceAccum) { +static inline void gpuDecodeDeviceInfoTableGroupId_b3696a(struct OBJGPU *pGpu, DEVICE_INFO2_ENTRY *pEntry, NvU32 *pDeviceAccum) { return; } #ifdef __nvoc_gpu_h_disabled -static inline void gpuDecodeDeviceInfoTableGroupId(struct OBJGPU *pGpu, DEVICE_INFO2_TABLE *pEntry, NvU32 *pDeviceAccum) { +static inline void gpuDecodeDeviceInfoTableGroupId(struct OBJGPU *pGpu, DEVICE_INFO2_ENTRY *pEntry, NvU32 *pDeviceAccum) { NV_ASSERT_FAILED_PRECOMP("OBJGPU was disabled!"); } #else //__nvoc_gpu_h_disabled @@ -2337,6 +2657,58 @@ #define gpuDecodeDeviceInfoTableGroupId_HAL(pGpu, pEntry, pDeviceAccum) gpuDecodeDeviceInfoTableGroupId(pGpu, pEntry, pDeviceAccum) +static inline NV_STATUS gpuGc6EntryPstateCheck_56cd7a(struct OBJGPU *pGpu) { + return NV_OK; +} + + +#ifdef __nvoc_gpu_h_disabled +static inline NV_STATUS gpuGc6EntryPstateCheck(struct OBJGPU *pGpu) { + NV_ASSERT_FAILED_PRECOMP("OBJGPU was disabled!"); + return NV_ERR_NOT_SUPPORTED; +} +#else //__nvoc_gpu_h_disabled +#define gpuGc6EntryPstateCheck(pGpu) gpuGc6EntryPstateCheck_56cd7a(pGpu) +#endif //__nvoc_gpu_h_disabled + +#define gpuGc6EntryPstateCheck_HAL(pGpu) gpuGc6EntryPstateCheck(pGpu) + +static inline NV_STATUS gpuWaitGC6Ready_56cd7a(struct OBJGPU *pGpu) { + return NV_OK; +} + +NV_STATUS gpuWaitGC6Ready_GM107(struct OBJGPU *pGpu); + + +#ifdef __nvoc_gpu_h_disabled +static inline NV_STATUS gpuWaitGC6Ready(struct OBJGPU *pGpu) { + NV_ASSERT_FAILED_PRECOMP("OBJGPU was disabled!"); + return NV_ERR_NOT_SUPPORTED; +} +#else //__nvoc_gpu_h_disabled +#define gpuWaitGC6Ready(pGpu) gpuWaitGC6Ready_56cd7a(pGpu) +#endif //__nvoc_gpu_h_disabled + +#define gpuWaitGC6Ready_HAL(pGpu) gpuWaitGC6Ready(pGpu) + +static inline NV_STATUS gpuPrePowerOff_56cd7a(struct OBJGPU *pGpu) { + return NV_OK; +} + +NV_STATUS gpuPrePowerOff_GM107(struct OBJGPU *pGpu); + + +#ifdef __nvoc_gpu_h_disabled +static inline NV_STATUS gpuPrePowerOff(struct OBJGPU *pGpu) { + NV_ASSERT_FAILED_PRECOMP("OBJGPU was disabled!"); + return NV_ERR_NOT_SUPPORTED; +} +#else //__nvoc_gpu_h_disabled +#define gpuPrePowerOff(pGpu) gpuPrePowerOff_56cd7a(pGpu) +#endif //__nvoc_gpu_h_disabled + +#define gpuPrePowerOff_HAL(pGpu) gpuPrePowerOff(pGpu) + NV_STATUS gpuVerifyExistence_IMPL(struct OBJGPU *pGpu); @@ -2368,6 +2740,64 @@ #define gpuResetVFRegisters_HAL(pGpu, gfid) gpuResetVFRegisters(pGpu, gfid) +static inline NvU32 gpuGetSliLinkDetectionHalFlag_539ab4(struct OBJGPU *pGpu) { + return 1; +} + + +#ifdef __nvoc_gpu_h_disabled +static inline NvU32 gpuGetSliLinkDetectionHalFlag(struct OBJGPU *pGpu) { + NV_ASSERT_FAILED_PRECOMP("OBJGPU was disabled!"); + return 0; +} +#else //__nvoc_gpu_h_disabled +#define gpuGetSliLinkDetectionHalFlag(pGpu) gpuGetSliLinkDetectionHalFlag_539ab4(pGpu) +#endif //__nvoc_gpu_h_disabled + +#define gpuGetSliLinkDetectionHalFlag_HAL(pGpu) gpuGetSliLinkDetectionHalFlag(pGpu) + +void gpuDetectSliLinkFromGpus_GK104(struct OBJGPU *pGpu, NvU32 gpuCount, NvU32 gpuMaskArg, NvU32 *pSliLinkOutputMask, NvBool *pSliLinkCircular, NvU32 *pSliLinkEndsMask, NvU32 *pVidLinkCount); + + +#ifdef __nvoc_gpu_h_disabled +static inline void gpuDetectSliLinkFromGpus(struct OBJGPU *pGpu, NvU32 gpuCount, NvU32 gpuMaskArg, NvU32 *pSliLinkOutputMask, NvBool *pSliLinkCircular, NvU32 *pSliLinkEndsMask, NvU32 *pVidLinkCount) { + NV_ASSERT_FAILED_PRECOMP("OBJGPU was disabled!"); +} +#else //__nvoc_gpu_h_disabled +#define gpuDetectSliLinkFromGpus(pGpu, gpuCount, gpuMaskArg, pSliLinkOutputMask, pSliLinkCircular, pSliLinkEndsMask, pVidLinkCount) gpuDetectSliLinkFromGpus_GK104(pGpu, gpuCount, gpuMaskArg, pSliLinkOutputMask, pSliLinkCircular, pSliLinkEndsMask, pVidLinkCount) +#endif //__nvoc_gpu_h_disabled + +#define gpuDetectSliLinkFromGpus_HAL(pGpu, gpuCount, gpuMaskArg, pSliLinkOutputMask, pSliLinkCircular, pSliLinkEndsMask, pVidLinkCount) gpuDetectSliLinkFromGpus(pGpu, gpuCount, gpuMaskArg, pSliLinkOutputMask, pSliLinkCircular, pSliLinkEndsMask, pVidLinkCount) + +static inline NvU32 gpuGetNvlinkLinkDetectionHalFlag_adde13(struct OBJGPU *pGpu) { + return 2; +} + + +#ifdef __nvoc_gpu_h_disabled +static inline NvU32 gpuGetNvlinkLinkDetectionHalFlag(struct OBJGPU *pGpu) { + NV_ASSERT_FAILED_PRECOMP("OBJGPU was disabled!"); + return 0; +} +#else //__nvoc_gpu_h_disabled +#define gpuGetNvlinkLinkDetectionHalFlag(pGpu) gpuGetNvlinkLinkDetectionHalFlag_adde13(pGpu) +#endif //__nvoc_gpu_h_disabled + +#define gpuGetNvlinkLinkDetectionHalFlag_HAL(pGpu) gpuGetNvlinkLinkDetectionHalFlag(pGpu) + +void gpuDetectNvlinkLinkFromGpus_GP100(struct OBJGPU *pGpu, NvU32 gpuCount, NvU32 gpuMaskArg, NvU32 *pSliLinkOutputMask, NvBool *pSliLinkCircular, NvU32 *pSliLinkEndsMask, NvU32 *pVidLinkCount); + + +#ifdef __nvoc_gpu_h_disabled +static inline void gpuDetectNvlinkLinkFromGpus(struct OBJGPU *pGpu, NvU32 gpuCount, NvU32 gpuMaskArg, NvU32 *pSliLinkOutputMask, NvBool *pSliLinkCircular, NvU32 *pSliLinkEndsMask, NvU32 *pVidLinkCount) { + NV_ASSERT_FAILED_PRECOMP("OBJGPU was disabled!"); +} +#else //__nvoc_gpu_h_disabled +#define gpuDetectNvlinkLinkFromGpus(pGpu, gpuCount, gpuMaskArg, pSliLinkOutputMask, pSliLinkCircular, pSliLinkEndsMask, pVidLinkCount) gpuDetectNvlinkLinkFromGpus_GP100(pGpu, gpuCount, gpuMaskArg, pSliLinkOutputMask, pSliLinkCircular, pSliLinkEndsMask, pVidLinkCount) +#endif //__nvoc_gpu_h_disabled + +#define gpuDetectNvlinkLinkFromGpus_HAL(pGpu, gpuCount, gpuMaskArg, pSliLinkOutputMask, pSliLinkCircular, pSliLinkEndsMask, pVidLinkCount) gpuDetectNvlinkLinkFromGpus(pGpu, gpuCount, gpuMaskArg, pSliLinkOutputMask, pSliLinkCircular, pSliLinkEndsMask, pVidLinkCount) + NvU32 gpuGetLitterValues_FWCLIENT(struct OBJGPU *pGpu, NvU32 index); NvU32 gpuGetLitterValues_TU102(struct OBJGPU *pGpu, NvU32 index); @@ -2498,6 +2928,32 @@ #define gpuFindP2PPeerGpuCapsByGpuId_HAL(pGpu, peerGpuId) gpuFindP2PPeerGpuCapsByGpuId(pGpu, peerGpuId) +NvBool gpuCheckEccCounts_TU102(struct OBJGPU *pGpu); + + +#ifdef __nvoc_gpu_h_disabled +static inline NvBool gpuCheckEccCounts(struct OBJGPU *pGpu) { + NV_ASSERT_FAILED_PRECOMP("OBJGPU was disabled!"); + return NV_FALSE; +} +#else //__nvoc_gpu_h_disabled +#define gpuCheckEccCounts(pGpu) gpuCheckEccCounts_TU102(pGpu) +#endif //__nvoc_gpu_h_disabled + +#define gpuCheckEccCounts_HAL(pGpu) gpuCheckEccCounts(pGpu) + +NV_STATUS gpuConstructDeviceInfoTable_FWCLIENT(struct OBJGPU *pGpu); + +static inline NV_STATUS gpuConstructDeviceInfoTable_56cd7a(struct OBJGPU *pGpu) { + return NV_OK; +} + +NV_STATUS gpuConstructDeviceInfoTable_GA100(struct OBJGPU *pGpu); + +static inline NV_STATUS gpuConstructDeviceInfoTable_DISPATCH(struct OBJGPU *pGpu) { + return pGpu->__gpuConstructDeviceInfoTable__(pGpu); +} + NV_STATUS gpuWriteBusConfigReg_GM107(struct OBJGPU *pGpu, NvU32 index, NvU32 value); NV_STATUS gpuWriteBusConfigReg_GH100(struct OBJGPU *pGpu, NvU32 index, NvU32 value); @@ -2516,8 +2972,8 @@ NV_STATUS gpuReadBusConfigRegEx_GM107(struct OBJGPU *pGpu, NvU32 index, NvU32 *data, THREAD_STATE_NODE *pThreadState); -static inline NV_STATUS gpuReadBusConfigRegEx_46f6a7(struct OBJGPU *pGpu, NvU32 index, NvU32 *data, THREAD_STATE_NODE *pThreadState) { - return NV_ERR_NOT_SUPPORTED; +static inline NV_STATUS gpuReadBusConfigRegEx_5baef9(struct OBJGPU *pGpu, NvU32 index, NvU32 *data, THREAD_STATE_NODE *pThreadState) { + NV_ASSERT_OR_RETURN_PRECOMP(0, NV_ERR_NOT_SUPPORTED); } static inline NV_STATUS gpuReadBusConfigRegEx_DISPATCH(struct OBJGPU *pGpu, NvU32 index, NvU32 *data, THREAD_STATE_NODE *pThreadState) { @@ -2640,6 +3096,10 @@ NvBool gpuFuseSupportsDisplay_GA100(struct OBJGPU *pGpu); +static inline NvBool gpuFuseSupportsDisplay_491d52(struct OBJGPU *pGpu) { + return ((NvBool)(0 != 0)); +} + static inline NvBool gpuFuseSupportsDisplay_DISPATCH(struct OBJGPU *pGpu) { return pGpu->__gpuFuseSupportsDisplay__(pGpu); } @@ -2656,24 +3116,22 @@ return pGpu->__gpuClearFbhubPoisonIntrForBug2924523__(pGpu); } -void gpuReadDeviceId_GM107(struct OBJGPU *pGpu, NvU32 *arg0, NvU32 *arg1); - -void gpuReadDeviceId_GH100(struct OBJGPU *pGpu, NvU32 *arg0, NvU32 *arg1); +NvBool gpuCheckIfFbhubPoisonIntrPending_GA100(struct OBJGPU *pGpu); -static inline void gpuReadDeviceId_DISPATCH(struct OBJGPU *pGpu, NvU32 *arg0, NvU32 *arg1) { - pGpu->__gpuReadDeviceId__(pGpu, arg0, arg1); +static inline NvBool gpuCheckIfFbhubPoisonIntrPending_491d52(struct OBJGPU *pGpu) { + return ((NvBool)(0 != 0)); } -NV_STATUS gpuConstructDeviceInfoTable_FWCLIENT(struct OBJGPU *pGpu); - -static inline NV_STATUS gpuConstructDeviceInfoTable_56cd7a(struct OBJGPU *pGpu) { - return NV_OK; +static inline NvBool gpuCheckIfFbhubPoisonIntrPending_DISPATCH(struct OBJGPU *pGpu) { + return pGpu->__gpuCheckIfFbhubPoisonIntrPending__(pGpu); } -NV_STATUS gpuConstructDeviceInfoTable_GA100(struct OBJGPU *pGpu); +void gpuReadDeviceId_GM107(struct OBJGPU *pGpu, NvU32 *arg0, NvU32 *arg1); -static inline NV_STATUS gpuConstructDeviceInfoTable_DISPATCH(struct OBJGPU *pGpu) { - return pGpu->__gpuConstructDeviceInfoTable__(pGpu); +void gpuReadDeviceId_GH100(struct OBJGPU *pGpu, NvU32 *arg0, NvU32 *arg1); + +static inline void gpuReadDeviceId_DISPATCH(struct OBJGPU *pGpu, NvU32 *arg0, NvU32 *arg1) { + pGpu->__gpuReadDeviceId__(pGpu, arg0, arg1); } NvU64 gpuGetFlaVasSize_GA100(struct OBJGPU *pGpu, NvBool bNvswitchVirtualization); @@ -2688,6 +3146,28 @@ return pGpu->__gpuGetFlaVasSize__(pGpu, bNvswitchVirtualization); } +void gpuDetermineSelfHostedMode_PHYSICAL_GH100(struct OBJGPU *pGpu); + +static inline void gpuDetermineSelfHostedMode_b3696a(struct OBJGPU *pGpu) { + return; +} + +void gpuDetermineSelfHostedMode_KERNEL_GH100(struct OBJGPU *pGpu); + +static inline void gpuDetermineSelfHostedMode_DISPATCH(struct OBJGPU *pGpu) { + pGpu->__gpuDetermineSelfHostedMode__(pGpu); +} + +void gpuDetermineMIGSupport_GH100(struct OBJGPU *pGpu); + +static inline void gpuDetermineMIGSupport_b3696a(struct OBJGPU *pGpu) { + return; +} + +static inline void gpuDetermineMIGSupport_DISPATCH(struct OBJGPU *pGpu) { + pGpu->__gpuDetermineMIGSupport__(pGpu); +} + NvBool gpuIsAtsSupportedWithSmcMemPartitioning_GH100(struct OBJGPU *pGpu); static inline NvBool gpuIsAtsSupportedWithSmcMemPartitioning_491d52(struct OBJGPU *pGpu) { @@ -2710,6 +3190,46 @@ return pGpu->__gpuIsSliCapableWithoutDisplay__(pGpu); } +NvBool gpuIsCCEnabledInHw_GH100(struct OBJGPU *pGpu); + +static inline NvBool gpuIsCCEnabledInHw_491d52(struct OBJGPU *pGpu) { + return ((NvBool)(0 != 0)); +} + +static inline NvBool gpuIsCCEnabledInHw_DISPATCH(struct OBJGPU *pGpu) { + return pGpu->__gpuIsCCEnabledInHw__(pGpu); +} + +NvBool gpuIsDevModeEnabledInHw_GH100(struct OBJGPU *pGpu); + +static inline NvBool gpuIsDevModeEnabledInHw_491d52(struct OBJGPU *pGpu) { + return ((NvBool)(0 != 0)); +} + +static inline NvBool gpuIsDevModeEnabledInHw_DISPATCH(struct OBJGPU *pGpu) { + return pGpu->__gpuIsDevModeEnabledInHw__(pGpu); +} + +NvBool gpuIsCtxBufAllocInPmaSupported_GA100(struct OBJGPU *pGpu); + +static inline NvBool gpuIsCtxBufAllocInPmaSupported_491d52(struct OBJGPU *pGpu) { + return ((NvBool)(0 != 0)); +} + +static inline NvBool gpuIsCtxBufAllocInPmaSupported_DISPATCH(struct OBJGPU *pGpu) { + return pGpu->__gpuIsCtxBufAllocInPmaSupported__(pGpu); +} + +NV_STATUS gpuWaitForGfwBootComplete_TU102(struct OBJGPU *pGpu); + +static inline NV_STATUS gpuWaitForGfwBootComplete_5baef9(struct OBJGPU *pGpu) { + NV_ASSERT_OR_RETURN_PRECOMP(0, NV_ERR_NOT_SUPPORTED); +} + +static inline NV_STATUS gpuWaitForGfwBootComplete_DISPATCH(struct OBJGPU *pGpu) { + return pGpu->__gpuWaitForGfwBootComplete__(pGpu); +} + static inline PENGDESCRIPTOR gpuGetInitEngineDescriptors(struct OBJGPU *pGpu) { return pGpu->engineOrder.pEngineInitDescriptors; } @@ -2767,22 +3287,6 @@ return pGpu->dmaStartAddress; } -static inline NvBool gpuIsCCFeatureEnabled(struct OBJGPU *pGpu) { - return ((NvBool)(0 != 0)); -} - -static inline NvBool gpuIsApmFeatureEnabled(struct OBJGPU *pGpu) { - return ((NvBool)(0 != 0)); -} - -static inline NvBool gpuIsCCorApmFeatureEnabled(struct OBJGPU *pGpu) { - return ((NvBool)(0 != 0)); -} - -static inline NvBool gpuIsInCCorApmDevMode(struct OBJGPU *pGpu) { - return ((NvBool)(0 != 0)); -} - static inline NV_STATUS gpuFreeEventHandle(struct OBJGPU *pGpu) { return NV_OK; } @@ -2811,6 +3315,10 @@ return pGpu->vmmuSegmentSize; } +static inline NvBool gpuIsVideoLinkDisabled(struct OBJGPU *pGpu) { + return pGpu->bVideoLinkDisabled; +} + static inline const NV2080_CTRL_INTERNAL_GPU_GET_CHIP_INFO_PARAMS *gpuGetChipInfo(struct OBJGPU *pGpu) { return pGpu->pChipInfo; } @@ -2851,6 +3359,10 @@ return pGpu->bUnifiedMemorySpaceEnabled; } +static inline NvBool gpuIsWarBug4040336Enabled(struct OBJGPU *pGpu) { + return pGpu->bBf3WarBug4040336Enabled; +} + static inline NvBool gpuIsSriovEnabled(struct OBJGPU *pGpu) { return pGpu->bSriovEnabled; } @@ -2927,6 +3439,10 @@ return pGpu->bIsVgx; } +static inline NvBool gpuIsACBranded(struct OBJGPU *pGpu) { + return pGpu->bIsAC; +} + static inline NvBool gpuIsNvidiaNvsBranded(struct OBJGPU *pGpu) { return pGpu->bIsNvidiaNvs; } @@ -2947,22 +3463,26 @@ return pGpu->bSriovCapable; } -static inline NvBool gpuIsCpuFirmwareHandlesFbEccInterruptEnabled(struct OBJGPU *pGpu) { - return pGpu->bCpuFirmwareHandlesFbEccInterruptEnabled; +static inline NvBool gpuIsSelfHosted(struct OBJGPU *pGpu) { + return pGpu->bIsSelfHosted; +} + +static inline NvBool gpuIsGspOwnedFaultBuffersEnabled(struct OBJGPU *pGpu) { + return pGpu->bIsGspOwnedFaultBuffersEnabled; } NV_STATUS gpuConstruct_IMPL(struct OBJGPU *arg_pGpu, NvU32 arg_gpuInstance); #define __nvoc_gpuConstruct(arg_pGpu, arg_gpuInstance) gpuConstruct_IMPL(arg_pGpu, arg_gpuInstance) -NV_STATUS gpuBindHalLegacy_IMPL(struct OBJGPU *pGpu, NvU32 chipId0, NvU32 chipId1); +NV_STATUS gpuBindHalLegacy_IMPL(struct OBJGPU *pGpu, NvU32 chipId0, NvU32 chipId1, NvU32 socChipId0); #ifdef __nvoc_gpu_h_disabled -static inline NV_STATUS gpuBindHalLegacy(struct OBJGPU *pGpu, NvU32 chipId0, NvU32 chipId1) { +static inline NV_STATUS gpuBindHalLegacy(struct OBJGPU *pGpu, NvU32 chipId0, NvU32 chipId1, NvU32 socChipId0) { NV_ASSERT_FAILED_PRECOMP("OBJGPU was disabled!"); return NV_ERR_NOT_SUPPORTED; } #else //__nvoc_gpu_h_disabled -#define gpuBindHalLegacy(pGpu, chipId0, chipId1) gpuBindHalLegacy_IMPL(pGpu, chipId0, chipId1) +#define gpuBindHalLegacy(pGpu, chipId0, chipId1, socChipId0) gpuBindHalLegacy_IMPL(pGpu, chipId0, chipId1, socChipId0) #endif //__nvoc_gpu_h_disabled NV_STATUS gpuPostConstruct_IMPL(struct OBJGPU *pGpu, GPUATTACHARG *arg0); @@ -3077,6 +3597,17 @@ #define gpuIsGpuFullPowerForPmResume(pGpu) gpuIsGpuFullPowerForPmResume_IMPL(pGpu) #endif //__nvoc_gpu_h_disabled +NV_STATUS gpuGetDeviceEntryByType_IMPL(struct OBJGPU *pGpu, NvU32 deviceTypeEnum, NvS32 groupId, NvU32 instanceId, const DEVICE_INFO2_ENTRY **ppDeviceEntry); + +#ifdef __nvoc_gpu_h_disabled +static inline NV_STATUS gpuGetDeviceEntryByType(struct OBJGPU *pGpu, NvU32 deviceTypeEnum, NvS32 groupId, NvU32 instanceId, const DEVICE_INFO2_ENTRY **ppDeviceEntry) { + NV_ASSERT_FAILED_PRECOMP("OBJGPU was disabled!"); + return NV_ERR_NOT_SUPPORTED; +} +#else //__nvoc_gpu_h_disabled +#define gpuGetDeviceEntryByType(pGpu, deviceTypeEnum, groupId, instanceId, ppDeviceEntry) gpuGetDeviceEntryByType_IMPL(pGpu, deviceTypeEnum, groupId, instanceId, ppDeviceEntry) +#endif //__nvoc_gpu_h_disabled + NV_STATUS gpuBuildClassDB_IMPL(struct OBJGPU *pGpu); #ifdef __nvoc_gpu_h_disabled @@ -3431,16 +3962,6 @@ #define gpuGetGidInfo(pGpu, ppGidString, pGidStrlen, gidFlags) gpuGetGidInfo_IMPL(pGpu, ppGidString, pGidStrlen, gidFlags) #endif //__nvoc_gpu_h_disabled -void gpuSetThreadBcState_IMPL(struct OBJGPU *pGpu, NvBool arg0); - -#ifdef __nvoc_gpu_h_disabled -static inline void gpuSetThreadBcState(struct OBJGPU *pGpu, NvBool arg0) { - NV_ASSERT_FAILED_PRECOMP("OBJGPU was disabled!"); -} -#else //__nvoc_gpu_h_disabled -#define gpuSetThreadBcState(pGpu, arg0) gpuSetThreadBcState_IMPL(pGpu, arg0) -#endif //__nvoc_gpu_h_disabled - void gpuSetDisconnectedProperties_IMPL(struct OBJGPU *pGpu); #ifdef __nvoc_gpu_h_disabled @@ -3764,6 +4285,105 @@ #define gpuFindClientInfoWithPidIterator(pGpu, pid, subPid, internalClassId, pData, pSmcInfo, pRef, bGlobalInfo) gpuFindClientInfoWithPidIterator_IMPL(pGpu, pid, subPid, internalClassId, pData, pSmcInfo, pRef, bGlobalInfo) #endif //__nvoc_gpu_h_disabled +NvBool gpuIsCCFeatureEnabled_IMPL(struct OBJGPU *pGpu); + +#ifdef __nvoc_gpu_h_disabled +static inline NvBool gpuIsCCFeatureEnabled(struct OBJGPU *pGpu) { + NV_ASSERT_FAILED_PRECOMP("OBJGPU was disabled!"); + return NV_FALSE; +} +#else //__nvoc_gpu_h_disabled +#define gpuIsCCFeatureEnabled(pGpu) gpuIsCCFeatureEnabled_IMPL(pGpu) +#endif //__nvoc_gpu_h_disabled + +NvBool gpuIsApmFeatureEnabled_IMPL(struct OBJGPU *pGpu); + +#ifdef __nvoc_gpu_h_disabled +static inline NvBool gpuIsApmFeatureEnabled(struct OBJGPU *pGpu) { + NV_ASSERT_FAILED_PRECOMP("OBJGPU was disabled!"); + return NV_FALSE; +} +#else //__nvoc_gpu_h_disabled +#define gpuIsApmFeatureEnabled(pGpu) gpuIsApmFeatureEnabled_IMPL(pGpu) +#endif //__nvoc_gpu_h_disabled + +NvBool gpuIsCCorApmFeatureEnabled_IMPL(struct OBJGPU *pGpu); + +#ifdef __nvoc_gpu_h_disabled +static inline NvBool gpuIsCCorApmFeatureEnabled(struct OBJGPU *pGpu) { + NV_ASSERT_FAILED_PRECOMP("OBJGPU was disabled!"); + return NV_FALSE; +} +#else //__nvoc_gpu_h_disabled +#define gpuIsCCorApmFeatureEnabled(pGpu) gpuIsCCorApmFeatureEnabled_IMPL(pGpu) +#endif //__nvoc_gpu_h_disabled + +NvBool gpuIsCCDevToolsModeEnabled_IMPL(struct OBJGPU *pGpu); + +#ifdef __nvoc_gpu_h_disabled +static inline NvBool gpuIsCCDevToolsModeEnabled(struct OBJGPU *pGpu) { + NV_ASSERT_FAILED_PRECOMP("OBJGPU was disabled!"); + return NV_FALSE; +} +#else //__nvoc_gpu_h_disabled +#define gpuIsCCDevToolsModeEnabled(pGpu) gpuIsCCDevToolsModeEnabled_IMPL(pGpu) +#endif //__nvoc_gpu_h_disabled + +NvBool gpuIsOnTheBus_IMPL(struct OBJGPU *pGpu); + +#ifdef __nvoc_gpu_h_disabled +static inline NvBool gpuIsOnTheBus(struct OBJGPU *pGpu) { + NV_ASSERT_FAILED_PRECOMP("OBJGPU was disabled!"); + return NV_FALSE; +} +#else //__nvoc_gpu_h_disabled +#define gpuIsOnTheBus(pGpu) gpuIsOnTheBus_IMPL(pGpu) +#endif //__nvoc_gpu_h_disabled + +NV_STATUS gpuEnterStandby_IMPL(struct OBJGPU *pGpu); + +#ifdef __nvoc_gpu_h_disabled +static inline NV_STATUS gpuEnterStandby(struct OBJGPU *pGpu) { + NV_ASSERT_FAILED_PRECOMP("OBJGPU was disabled!"); + return NV_ERR_NOT_SUPPORTED; +} +#else //__nvoc_gpu_h_disabled +#define gpuEnterStandby(pGpu) gpuEnterStandby_IMPL(pGpu) +#endif //__nvoc_gpu_h_disabled + +NV_STATUS gpuEnterHibernate_IMPL(struct OBJGPU *pGpu); + +#ifdef __nvoc_gpu_h_disabled +static inline NV_STATUS gpuEnterHibernate(struct OBJGPU *pGpu) { + NV_ASSERT_FAILED_PRECOMP("OBJGPU was disabled!"); + return NV_ERR_NOT_SUPPORTED; +} +#else //__nvoc_gpu_h_disabled +#define gpuEnterHibernate(pGpu) gpuEnterHibernate_IMPL(pGpu) +#endif //__nvoc_gpu_h_disabled + +NV_STATUS gpuResumeFromStandby_IMPL(struct OBJGPU *pGpu); + +#ifdef __nvoc_gpu_h_disabled +static inline NV_STATUS gpuResumeFromStandby(struct OBJGPU *pGpu) { + NV_ASSERT_FAILED_PRECOMP("OBJGPU was disabled!"); + return NV_ERR_NOT_SUPPORTED; +} +#else //__nvoc_gpu_h_disabled +#define gpuResumeFromStandby(pGpu) gpuResumeFromStandby_IMPL(pGpu) +#endif //__nvoc_gpu_h_disabled + +NV_STATUS gpuResumeFromHibernate_IMPL(struct OBJGPU *pGpu); + +#ifdef __nvoc_gpu_h_disabled +static inline NV_STATUS gpuResumeFromHibernate(struct OBJGPU *pGpu) { + NV_ASSERT_FAILED_PRECOMP("OBJGPU was disabled!"); + return NV_ERR_NOT_SUPPORTED; +} +#else //__nvoc_gpu_h_disabled +#define gpuResumeFromHibernate(pGpu) gpuResumeFromHibernate_IMPL(pGpu) +#endif //__nvoc_gpu_h_disabled + NvBool gpuCheckSysmemAccess_IMPL(struct OBJGPU *pGpu); #ifdef __nvoc_gpu_h_disabled @@ -3818,6 +4438,50 @@ #define gpuValidateRegOffset(pGpu, arg0) gpuValidateRegOffset_IMPL(pGpu, arg0) #endif //__nvoc_gpu_h_disabled +NV_STATUS gpuSetGC6SBIOSCapabilities_IMPL(struct OBJGPU *pGpu); + +#ifdef __nvoc_gpu_h_disabled +static inline NV_STATUS gpuSetGC6SBIOSCapabilities(struct OBJGPU *pGpu) { + NV_ASSERT_FAILED_PRECOMP("OBJGPU was disabled!"); + return NV_ERR_NOT_SUPPORTED; +} +#else //__nvoc_gpu_h_disabled +#define gpuSetGC6SBIOSCapabilities(pGpu) gpuSetGC6SBIOSCapabilities_IMPL(pGpu) +#endif //__nvoc_gpu_h_disabled + +NV_STATUS gpuGc6Entry_IMPL(struct OBJGPU *pGpu, NV2080_CTRL_GC6_ENTRY_PARAMS *arg0); + +#ifdef __nvoc_gpu_h_disabled +static inline NV_STATUS gpuGc6Entry(struct OBJGPU *pGpu, NV2080_CTRL_GC6_ENTRY_PARAMS *arg0) { + NV_ASSERT_FAILED_PRECOMP("OBJGPU was disabled!"); + return NV_ERR_NOT_SUPPORTED; +} +#else //__nvoc_gpu_h_disabled +#define gpuGc6Entry(pGpu, arg0) gpuGc6Entry_IMPL(pGpu, arg0) +#endif //__nvoc_gpu_h_disabled + +NV_STATUS gpuGc6EntryGpuPowerOff_IMPL(struct OBJGPU *pGpu); + +#ifdef __nvoc_gpu_h_disabled +static inline NV_STATUS gpuGc6EntryGpuPowerOff(struct OBJGPU *pGpu) { + NV_ASSERT_FAILED_PRECOMP("OBJGPU was disabled!"); + return NV_ERR_NOT_SUPPORTED; +} +#else //__nvoc_gpu_h_disabled +#define gpuGc6EntryGpuPowerOff(pGpu) gpuGc6EntryGpuPowerOff_IMPL(pGpu) +#endif //__nvoc_gpu_h_disabled + +NV_STATUS gpuGc6Exit_IMPL(struct OBJGPU *pGpu, NV2080_CTRL_GC6_EXIT_PARAMS *arg0); + +#ifdef __nvoc_gpu_h_disabled +static inline NV_STATUS gpuGc6Exit(struct OBJGPU *pGpu, NV2080_CTRL_GC6_EXIT_PARAMS *arg0) { + NV_ASSERT_FAILED_PRECOMP("OBJGPU was disabled!"); + return NV_ERR_NOT_SUPPORTED; +} +#else //__nvoc_gpu_h_disabled +#define gpuGc6Exit(pGpu, arg0) gpuGc6Exit_IMPL(pGpu, arg0) +#endif //__nvoc_gpu_h_disabled + #undef PRIVATE_FIELD @@ -3837,11 +4501,11 @@ // // Generates GPU child accessor macros (i.e.: GPU_GET_{ENG}) // -#define GPU_CHILD_SINGLE_INST(className, accessorName, numInstances, bConstructEarly, bAlwaysCreate, gpuField) \ - static NV_FORCEINLINE className *accessorName(OBJGPU *pGpu) { return pGpu->gpuField; } \ +#define GPU_CHILD_SINGLE_INST(className, accessorName, numInstances, bConstructEarly, gpuField) \ + static NV_FORCEINLINE className *accessorName(OBJGPU *pGpu) { return pGpu->gpuField; } \ ct_assert(numInstances == 1); -#define GPU_CHILD_MULTI_INST(className, accessorName, numInstances, bConstructEarly, bAlwaysCreate, gpuField) \ +#define GPU_CHILD_MULTI_INST(className, accessorName, numInstances, bConstructEarly, gpuField) \ static NV_FORCEINLINE className *accessorName(OBJGPU *pGpu, NvU32 index) { return index < numInstances ? pGpu->gpuField[index] : NULL; } #include "gpu/gpu_child_list.h" @@ -3851,10 +4515,10 @@ // Temporary stubs #if RM_STRICT_CONFIG_EMIT_DISABLED_GPU_ENGINE_ACCESSORS #define GPU_CHILD_LIST_DISABLED_ONLY -#define GPU_CHILD_SINGLE_INST(className, accessorName, numInstances, bConstructEarly, bAlwaysCreate, gpuField) \ +#define GPU_CHILD_SINGLE_INST(className, accessorName, numInstances, bConstructEarly, gpuField) \ static NV_FORCEINLINE className *accessorName(OBJGPU *pGpu) { return NULL; } -#define GPU_CHILD_MULTI_INST(className, accessorName, numInstances, bConstructEarly, bAlwaysCreate, gpuField) \ +#define GPU_CHILD_MULTI_INST(className, accessorName, numInstances, bConstructEarly, gpuField) \ static NV_FORCEINLINE className *accessorName(OBJGPU *pGpu, NvU32 index) { return NULL; } #include "gpu/gpu_child_list.h" @@ -3919,7 +4583,6 @@ // IS_SILICON Real hardware // IS_VIRTUAL RM is running within a guest VM // IS_GSP_CLIENT RM is a GSP/DCE client with GPU support offloaded to GSP/DCE -// IS_FW_CLIENT RM is a firmware client with GPU support offloaded microprocessor // #define IS_EMULATION(pGpu) ((pGpu)->getProperty((pGpu), PDB_PROP_GPU_EMULATION)) @@ -3930,7 +4593,6 @@ #define IS_SILICON(pGpu) (!(IS_EMULATION(pGpu) || IS_SIMULATION(pGpu))) #define IS_PASSTHRU(pGpu) ((pGpu)->bIsPassthru) #define IS_GSP_CLIENT(pGpu) ((RMCFG_FEATURE_GSP_CLIENT_RM || RMCFG_FEATURE_DCE_CLIENT_RM) && (pGpu)->isGspClient) -#define IS_FW_CLIENT(pGpu) IS_GSP_CLIENT(pGpu) // TODO to be removed #define IS_VIRTUAL(pGpu) NV_FALSE #define IS_VIRTUAL_WITH_SRIOV(pGpu) NV_FALSE #define IS_VIRTUAL_WITH_HEAVY_SRIOV(pGpu) NV_FALSE @@ -4047,12 +4709,12 @@ GspStaticConfigInfo *gpuGetGspStaticInfo(struct OBJGPU *pGpu); #define GPU_GET_GSP_STATIC_INFO(pGpu) gpuGetGspStaticInfo(pGpu) - -#define IS_GPU_GC6_STATE_POWERED_ON(obj) NV_TRUE -#define IS_GPU_GC6_STATE_EXITED(obj) NV_FALSE -#define IS_GPU_GC6_STATE_ENTERING(obj) NV_FALSE -#define IS_GPU_GC6_STATE_ENTERED(obj) NV_FALSE -#define IS_GPU_GC6_STATE_EXITING(obj) NV_FALSE +// +// This function needs to be called when OBJGPU is not created. HAL +// infrastructure can’t be used for this case, so it has been added manually. +// It will be invoked directly by gpumgrIsDeviceMsixAllowed(). +// +NvBool gpuIsMsixAllowed_TU102(RmPhysAddr bar0BaseAddr); #endif // _OBJGPU_H_ diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/generated/g_gpu_resource_nvoc.c nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_gpu_resource_nvoc.c --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/generated/g_gpu_resource_nvoc.c 2023-10-25 20:26:59.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_gpu_resource_nvoc.c 2024-03-05 22:18:16.000000000 +0000 @@ -124,6 +124,14 @@ resAddAdditionalDependants(pClient, (struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_GpuResource_RsResource.offset), pReference); } +static NV_STATUS __nvoc_thunk_RsResource_gpuresUnmapFrom(struct GpuResource *pResource, RS_RES_UNMAP_FROM_PARAMS *pParams) { + return resUnmapFrom((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_GpuResource_RsResource.offset), pParams); +} + +static NV_STATUS __nvoc_thunk_RmResource_gpuresControlSerialization_Prologue(struct GpuResource *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return rmresControlSerialization_Prologue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_GpuResource_RmResource.offset), pCallContext, pParams); +} + static NV_STATUS __nvoc_thunk_RmResource_gpuresControl_Prologue(struct GpuResource *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { return rmresControl_Prologue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_GpuResource_RmResource.offset), pCallContext, pParams); } @@ -132,22 +140,22 @@ return resCanCopy((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_GpuResource_RsResource.offset)); } -static NV_STATUS __nvoc_thunk_RsResource_gpuresMapTo(struct GpuResource *pResource, RS_RES_MAP_TO_PARAMS *pParams) { - return resMapTo((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_GpuResource_RsResource.offset), pParams); -} - static void __nvoc_thunk_RsResource_gpuresPreDestruct(struct GpuResource *pResource) { resPreDestruct((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_GpuResource_RsResource.offset)); } -static NV_STATUS __nvoc_thunk_RsResource_gpuresUnmapFrom(struct GpuResource *pResource, RS_RES_UNMAP_FROM_PARAMS *pParams) { - return resUnmapFrom((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_GpuResource_RsResource.offset), pParams); +static NV_STATUS __nvoc_thunk_RsResource_gpuresMapTo(struct GpuResource *pResource, RS_RES_MAP_TO_PARAMS *pParams) { + return resMapTo((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_GpuResource_RsResource.offset), pParams); } static NV_STATUS __nvoc_thunk_RsResource_gpuresIsDuplicate(struct GpuResource *pResource, NvHandle hMemory, NvBool *pDuplicate) { return resIsDuplicate((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_GpuResource_RsResource.offset), hMemory, pDuplicate); } +static void __nvoc_thunk_RmResource_gpuresControlSerialization_Epilogue(struct GpuResource *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + rmresControlSerialization_Epilogue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_GpuResource_RmResource.offset), pCallContext, pParams); +} + static void __nvoc_thunk_RmResource_gpuresControl_Epilogue(struct GpuResource *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { rmresControl_Epilogue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_GpuResource_RmResource.offset), pCallContext, pParams); } @@ -234,18 +242,22 @@ pThis->__gpuresAddAdditionalDependants__ = &__nvoc_thunk_RsResource_gpuresAddAdditionalDependants; + pThis->__gpuresUnmapFrom__ = &__nvoc_thunk_RsResource_gpuresUnmapFrom; + + pThis->__gpuresControlSerialization_Prologue__ = &__nvoc_thunk_RmResource_gpuresControlSerialization_Prologue; + pThis->__gpuresControl_Prologue__ = &__nvoc_thunk_RmResource_gpuresControl_Prologue; pThis->__gpuresCanCopy__ = &__nvoc_thunk_RsResource_gpuresCanCopy; - pThis->__gpuresMapTo__ = &__nvoc_thunk_RsResource_gpuresMapTo; - pThis->__gpuresPreDestruct__ = &__nvoc_thunk_RsResource_gpuresPreDestruct; - pThis->__gpuresUnmapFrom__ = &__nvoc_thunk_RsResource_gpuresUnmapFrom; + pThis->__gpuresMapTo__ = &__nvoc_thunk_RsResource_gpuresMapTo; pThis->__gpuresIsDuplicate__ = &__nvoc_thunk_RsResource_gpuresIsDuplicate; + pThis->__gpuresControlSerialization_Epilogue__ = &__nvoc_thunk_RmResource_gpuresControlSerialization_Epilogue; + pThis->__gpuresControl_Epilogue__ = &__nvoc_thunk_RmResource_gpuresControl_Epilogue; pThis->__gpuresControlLookup__ = &__nvoc_thunk_RsResource_gpuresControlLookup; @@ -273,13 +285,16 @@ Object *pParentObj; GpuResource *pThis; - pThis = portMemAllocNonPaged(sizeof(GpuResource)); - if (pThis == NULL) return NV_ERR_NO_MEMORY; + status = __nvoc_handleObjCreateMemAlloc(createFlags, sizeof(GpuResource), (void**)&pThis, (void**)ppThis); + if (status != NV_OK) + return status; portMemSet(pThis, 0, sizeof(GpuResource)); __nvoc_initRtti(staticCast(pThis, Dynamic), &__nvoc_class_def_GpuResource); + pThis->__nvoc_base_RmResource.__nvoc_base_RsResource.__nvoc_base_Object.createFlags = createFlags; + if (pParent != NULL && !(createFlags & NVOC_OBJ_CREATE_FLAGS_PARENT_HALSPEC_ONLY)) { pParentObj = dynamicCast(pParent, Object); @@ -295,11 +310,17 @@ if (status != NV_OK) goto __nvoc_objCreate_GpuResource_cleanup; *ppThis = pThis; + return NV_OK; __nvoc_objCreate_GpuResource_cleanup: // do not call destructors here since the constructor already called them - portMemFree(pThis); + if (createFlags & NVOC_OBJ_CREATE_FLAGS_IN_PLACE_CONSTRUCT) + portMemSet(pThis, 0, sizeof(GpuResource)); + else + portMemFree(pThis); + + // coverity[leaked_storage:FALSE] return status; } diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/generated/g_gpu_resource_nvoc.h nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_gpu_resource_nvoc.h --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/generated/g_gpu_resource_nvoc.h 2023-10-25 20:26:59.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_gpu_resource_nvoc.h 2024-03-05 22:18:17.000000000 +0000 @@ -80,10 +80,7 @@ #define GPU_RES_GET_DEVICE(pRes) staticCastNoPtrCheck((pRes), GpuResource)->pDevice #define GPU_RES_GET_SUBDEVICE(pRes) staticCastNoPtrCheck((pRes), GpuResource)->pSubdevice -#define GPU_RES_SET_THREAD_BC_STATE(pRes) do { \ - gpuSetThreadBcState(staticCastNoPtrCheck((pRes), GpuResource)->pGpu, \ - staticCastNoPtrCheck((pRes), GpuResource)->bBcResource); \ - } while(0) +#define GPU_RES_SET_THREAD_BC_STATE(pRes) PORT_UNREFERENCED_VARIABLE(pRes) /*! * Abstract base class for common CPU mapping operations @@ -115,12 +112,14 @@ NvU32 (*__gpuresGetRefCount__)(struct GpuResource *); NV_STATUS (*__gpuresControlFilter__)(struct GpuResource *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); void (*__gpuresAddAdditionalDependants__)(struct RsClient *, struct GpuResource *, RsResourceRef *); + NV_STATUS (*__gpuresUnmapFrom__)(struct GpuResource *, RS_RES_UNMAP_FROM_PARAMS *); + NV_STATUS (*__gpuresControlSerialization_Prologue__)(struct GpuResource *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); NV_STATUS (*__gpuresControl_Prologue__)(struct GpuResource *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); NvBool (*__gpuresCanCopy__)(struct GpuResource *); - NV_STATUS (*__gpuresMapTo__)(struct GpuResource *, RS_RES_MAP_TO_PARAMS *); void (*__gpuresPreDestruct__)(struct GpuResource *); - NV_STATUS (*__gpuresUnmapFrom__)(struct GpuResource *, RS_RES_UNMAP_FROM_PARAMS *); + NV_STATUS (*__gpuresMapTo__)(struct GpuResource *, RS_RES_MAP_TO_PARAMS *); NV_STATUS (*__gpuresIsDuplicate__)(struct GpuResource *, NvHandle, NvBool *); + void (*__gpuresControlSerialization_Epilogue__)(struct GpuResource *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); void (*__gpuresControl_Epilogue__)(struct GpuResource *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); NV_STATUS (*__gpuresControlLookup__)(struct GpuResource *, struct RS_RES_CONTROL_PARAMS_INTERNAL *, const struct NVOC_EXPORTED_METHOD_DEF **); NvBool (*__gpuresAccessCallback__)(struct GpuResource *, struct RsClient *, void *, RsAccessRight); @@ -173,12 +172,14 @@ #define gpuresGetRefCount(pResource) gpuresGetRefCount_DISPATCH(pResource) #define gpuresControlFilter(pResource, pCallContext, pParams) gpuresControlFilter_DISPATCH(pResource, pCallContext, pParams) #define gpuresAddAdditionalDependants(pClient, pResource, pReference) gpuresAddAdditionalDependants_DISPATCH(pClient, pResource, pReference) +#define gpuresUnmapFrom(pResource, pParams) gpuresUnmapFrom_DISPATCH(pResource, pParams) +#define gpuresControlSerialization_Prologue(pResource, pCallContext, pParams) gpuresControlSerialization_Prologue_DISPATCH(pResource, pCallContext, pParams) #define gpuresControl_Prologue(pResource, pCallContext, pParams) gpuresControl_Prologue_DISPATCH(pResource, pCallContext, pParams) #define gpuresCanCopy(pResource) gpuresCanCopy_DISPATCH(pResource) -#define gpuresMapTo(pResource, pParams) gpuresMapTo_DISPATCH(pResource, pParams) #define gpuresPreDestruct(pResource) gpuresPreDestruct_DISPATCH(pResource) -#define gpuresUnmapFrom(pResource, pParams) gpuresUnmapFrom_DISPATCH(pResource, pParams) +#define gpuresMapTo(pResource, pParams) gpuresMapTo_DISPATCH(pResource, pParams) #define gpuresIsDuplicate(pResource, hMemory, pDuplicate) gpuresIsDuplicate_DISPATCH(pResource, hMemory, pDuplicate) +#define gpuresControlSerialization_Epilogue(pResource, pCallContext, pParams) gpuresControlSerialization_Epilogue_DISPATCH(pResource, pCallContext, pParams) #define gpuresControl_Epilogue(pResource, pCallContext, pParams) gpuresControl_Epilogue_DISPATCH(pResource, pCallContext, pParams) #define gpuresControlLookup(pResource, pParams, ppEntry) gpuresControlLookup_DISPATCH(pResource, pParams, ppEntry) #define gpuresAccessCallback(pResource, pInvokingClient, pAllocParams, accessRight) gpuresAccessCallback_DISPATCH(pResource, pInvokingClient, pAllocParams, accessRight) @@ -254,6 +255,14 @@ pResource->__gpuresAddAdditionalDependants__(pClient, pResource, pReference); } +static inline NV_STATUS gpuresUnmapFrom_DISPATCH(struct GpuResource *pResource, RS_RES_UNMAP_FROM_PARAMS *pParams) { + return pResource->__gpuresUnmapFrom__(pResource, pParams); +} + +static inline NV_STATUS gpuresControlSerialization_Prologue_DISPATCH(struct GpuResource *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return pResource->__gpuresControlSerialization_Prologue__(pResource, pCallContext, pParams); +} + static inline NV_STATUS gpuresControl_Prologue_DISPATCH(struct GpuResource *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { return pResource->__gpuresControl_Prologue__(pResource, pCallContext, pParams); } @@ -262,22 +271,22 @@ return pResource->__gpuresCanCopy__(pResource); } -static inline NV_STATUS gpuresMapTo_DISPATCH(struct GpuResource *pResource, RS_RES_MAP_TO_PARAMS *pParams) { - return pResource->__gpuresMapTo__(pResource, pParams); -} - static inline void gpuresPreDestruct_DISPATCH(struct GpuResource *pResource) { pResource->__gpuresPreDestruct__(pResource); } -static inline NV_STATUS gpuresUnmapFrom_DISPATCH(struct GpuResource *pResource, RS_RES_UNMAP_FROM_PARAMS *pParams) { - return pResource->__gpuresUnmapFrom__(pResource, pParams); +static inline NV_STATUS gpuresMapTo_DISPATCH(struct GpuResource *pResource, RS_RES_MAP_TO_PARAMS *pParams) { + return pResource->__gpuresMapTo__(pResource, pParams); } static inline NV_STATUS gpuresIsDuplicate_DISPATCH(struct GpuResource *pResource, NvHandle hMemory, NvBool *pDuplicate) { return pResource->__gpuresIsDuplicate__(pResource, hMemory, pDuplicate); } +static inline void gpuresControlSerialization_Epilogue_DISPATCH(struct GpuResource *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + pResource->__gpuresControlSerialization_Epilogue__(pResource, pCallContext, pParams); +} + static inline void gpuresControl_Epilogue_DISPATCH(struct GpuResource *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { pResource->__gpuresControl_Epilogue__(pResource, pCallContext, pParams); } diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/generated/g_gpu_user_shared_data_nvoc.c nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_gpu_user_shared_data_nvoc.c --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/generated/g_gpu_user_shared_data_nvoc.c 2023-10-25 20:27:00.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_gpu_user_shared_data_nvoc.c 2024-03-05 22:18:17.000000000 +0000 @@ -21,11 +21,11 @@ extern const struct NVOC_CLASS_DEF __nvoc_class_def_RmResource; -extern const struct NVOC_CLASS_DEF __nvoc_class_def_GpuResource; +extern const struct NVOC_CLASS_DEF __nvoc_class_def_Memory; void __nvoc_init_GpuUserSharedData(GpuUserSharedData*); void __nvoc_init_funcTable_GpuUserSharedData(GpuUserSharedData*); -NV_STATUS __nvoc_ctor_GpuUserSharedData(GpuUserSharedData*, struct CALL_CONTEXT * arg_pCallContext, struct RS_RES_ALLOC_PARAMS_INTERNAL * arg_pParams); +NV_STATUS __nvoc_ctor_GpuUserSharedData(GpuUserSharedData*, CALL_CONTEXT * arg_pCallContext, struct RS_RES_ALLOC_PARAMS_INTERNAL * arg_pParams); void __nvoc_init_dataField_GpuUserSharedData(GpuUserSharedData*); void __nvoc_dtor_GpuUserSharedData(GpuUserSharedData*); extern const struct NVOC_EXPORT_INFO __nvoc_export_info_GpuUserSharedData; @@ -39,38 +39,38 @@ static const struct NVOC_RTTI __nvoc_rtti_GpuUserSharedData_Object = { /*pClassDef=*/ &__nvoc_class_def_Object, /*dtor=*/ &__nvoc_destructFromBase, - /*offset=*/ NV_OFFSETOF(GpuUserSharedData, __nvoc_base_GpuResource.__nvoc_base_RmResource.__nvoc_base_RsResource.__nvoc_base_Object), + /*offset=*/ NV_OFFSETOF(GpuUserSharedData, __nvoc_base_Memory.__nvoc_base_RmResource.__nvoc_base_RsResource.__nvoc_base_Object), }; static const struct NVOC_RTTI __nvoc_rtti_GpuUserSharedData_RsResource = { /*pClassDef=*/ &__nvoc_class_def_RsResource, /*dtor=*/ &__nvoc_destructFromBase, - /*offset=*/ NV_OFFSETOF(GpuUserSharedData, __nvoc_base_GpuResource.__nvoc_base_RmResource.__nvoc_base_RsResource), + /*offset=*/ NV_OFFSETOF(GpuUserSharedData, __nvoc_base_Memory.__nvoc_base_RmResource.__nvoc_base_RsResource), }; static const struct NVOC_RTTI __nvoc_rtti_GpuUserSharedData_RmResourceCommon = { /*pClassDef=*/ &__nvoc_class_def_RmResourceCommon, /*dtor=*/ &__nvoc_destructFromBase, - /*offset=*/ NV_OFFSETOF(GpuUserSharedData, __nvoc_base_GpuResource.__nvoc_base_RmResource.__nvoc_base_RmResourceCommon), + /*offset=*/ NV_OFFSETOF(GpuUserSharedData, __nvoc_base_Memory.__nvoc_base_RmResource.__nvoc_base_RmResourceCommon), }; static const struct NVOC_RTTI __nvoc_rtti_GpuUserSharedData_RmResource = { /*pClassDef=*/ &__nvoc_class_def_RmResource, /*dtor=*/ &__nvoc_destructFromBase, - /*offset=*/ NV_OFFSETOF(GpuUserSharedData, __nvoc_base_GpuResource.__nvoc_base_RmResource), + /*offset=*/ NV_OFFSETOF(GpuUserSharedData, __nvoc_base_Memory.__nvoc_base_RmResource), }; -static const struct NVOC_RTTI __nvoc_rtti_GpuUserSharedData_GpuResource = { - /*pClassDef=*/ &__nvoc_class_def_GpuResource, +static const struct NVOC_RTTI __nvoc_rtti_GpuUserSharedData_Memory = { + /*pClassDef=*/ &__nvoc_class_def_Memory, /*dtor=*/ &__nvoc_destructFromBase, - /*offset=*/ NV_OFFSETOF(GpuUserSharedData, __nvoc_base_GpuResource), + /*offset=*/ NV_OFFSETOF(GpuUserSharedData, __nvoc_base_Memory), }; static const struct NVOC_CASTINFO __nvoc_castinfo_GpuUserSharedData = { /*numRelatives=*/ 6, /*relatives=*/ { &__nvoc_rtti_GpuUserSharedData_GpuUserSharedData, - &__nvoc_rtti_GpuUserSharedData_GpuResource, + &__nvoc_rtti_GpuUserSharedData_Memory, &__nvoc_rtti_GpuUserSharedData_RmResource, &__nvoc_rtti_GpuUserSharedData_RmResourceCommon, &__nvoc_rtti_GpuUserSharedData_RsResource, @@ -93,92 +93,100 @@ /*pExportInfo=*/ &__nvoc_export_info_GpuUserSharedData }; -static NV_STATUS __nvoc_thunk_GpuUserSharedData_gpuresMap(struct GpuResource *pData, struct CALL_CONTEXT *pCallContext, struct RS_CPU_MAP_PARAMS *pParams, struct RsCpuMapping *pCpuMapping) { - return gpushareddataMap((struct GpuUserSharedData *)(((unsigned char *)pData) - __nvoc_rtti_GpuUserSharedData_GpuResource.offset), pCallContext, pParams, pCpuMapping); +static NvBool __nvoc_thunk_GpuUserSharedData_resCanCopy(struct RsResource *pData) { + return gpushareddataCanCopy((struct GpuUserSharedData *)(((unsigned char *)pData) - __nvoc_rtti_GpuUserSharedData_RsResource.offset)); } -static NV_STATUS __nvoc_thunk_GpuUserSharedData_gpuresUnmap(struct GpuResource *pData, struct CALL_CONTEXT *pCallContext, struct RsCpuMapping *pCpuMapping) { - return gpushareddataUnmap((struct GpuUserSharedData *)(((unsigned char *)pData) - __nvoc_rtti_GpuUserSharedData_GpuResource.offset), pCallContext, pCpuMapping); +static NV_STATUS __nvoc_thunk_Memory_gpushareddataCheckMemInterUnmap(struct GpuUserSharedData *pMemory, NvBool bSubdeviceHandleProvided) { + return memCheckMemInterUnmap((struct Memory *)(((unsigned char *)pMemory) + __nvoc_rtti_GpuUserSharedData_Memory.offset), bSubdeviceHandleProvided); } -static NV_STATUS __nvoc_thunk_GpuUserSharedData_gpuresGetMapAddrSpace(struct GpuResource *pData, struct CALL_CONTEXT *pCallContext, NvU32 mapFlags, NV_ADDRESS_SPACE *pAddrSpace) { - return gpushareddataGetMapAddrSpace((struct GpuUserSharedData *)(((unsigned char *)pData) - __nvoc_rtti_GpuUserSharedData_GpuResource.offset), pCallContext, mapFlags, pAddrSpace); +static NvBool __nvoc_thunk_RmResource_gpushareddataShareCallback(struct GpuUserSharedData *pResource, struct RsClient *pInvokingClient, struct RsResourceRef *pParentRef, RS_SHARE_POLICY *pSharePolicy) { + return rmresShareCallback((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_GpuUserSharedData_RmResource.offset), pInvokingClient, pParentRef, pSharePolicy); } -static NV_STATUS __nvoc_thunk_GpuUserSharedData_rmresGetMemoryMappingDescriptor(struct RmResource *pData, struct MEMORY_DESCRIPTOR **ppMemDesc) { - return gpushareddataGetMemoryMappingDescriptor((struct GpuUserSharedData *)(((unsigned char *)pData) - __nvoc_rtti_GpuUserSharedData_RmResource.offset), ppMemDesc); +static NV_STATUS __nvoc_thunk_RsResource_gpushareddataMapTo(struct GpuUserSharedData *pResource, RS_RES_MAP_TO_PARAMS *pParams) { + return resMapTo((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_GpuUserSharedData_RsResource.offset), pParams); } -static NvBool __nvoc_thunk_GpuResource_gpushareddataShareCallback(struct GpuUserSharedData *pGpuResource, struct RsClient *pInvokingClient, struct RsResourceRef *pParentRef, RS_SHARE_POLICY *pSharePolicy) { - return gpuresShareCallback((struct GpuResource *)(((unsigned char *)pGpuResource) + __nvoc_rtti_GpuUserSharedData_GpuResource.offset), pInvokingClient, pParentRef, pSharePolicy); +static NV_STATUS __nvoc_thunk_Memory_gpushareddataGetMapAddrSpace(struct GpuUserSharedData *pMemory, CALL_CONTEXT *pCallContext, NvU32 mapFlags, NV_ADDRESS_SPACE *pAddrSpace) { + return memGetMapAddrSpace((struct Memory *)(((unsigned char *)pMemory) + __nvoc_rtti_GpuUserSharedData_Memory.offset), pCallContext, mapFlags, pAddrSpace); } -static NV_STATUS __nvoc_thunk_GpuResource_gpushareddataControl(struct GpuUserSharedData *pGpuResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { - return gpuresControl((struct GpuResource *)(((unsigned char *)pGpuResource) + __nvoc_rtti_GpuUserSharedData_GpuResource.offset), pCallContext, pParams); +static NvU32 __nvoc_thunk_RsResource_gpushareddataGetRefCount(struct GpuUserSharedData *pResource) { + return resGetRefCount((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_GpuUserSharedData_RsResource.offset)); } -static NV_STATUS __nvoc_thunk_RmResource_gpushareddataGetMemInterMapParams(struct GpuUserSharedData *pRmResource, RMRES_MEM_INTER_MAP_PARAMS *pParams) { - return rmresGetMemInterMapParams((struct RmResource *)(((unsigned char *)pRmResource) + __nvoc_rtti_GpuUserSharedData_RmResource.offset), pParams); +static void __nvoc_thunk_RsResource_gpushareddataAddAdditionalDependants(struct RsClient *pClient, struct GpuUserSharedData *pResource, RsResourceRef *pReference) { + resAddAdditionalDependants(pClient, (struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_GpuUserSharedData_RsResource.offset), pReference); } -static NvHandle __nvoc_thunk_GpuResource_gpushareddataGetInternalObjectHandle(struct GpuUserSharedData *pGpuResource) { - return gpuresGetInternalObjectHandle((struct GpuResource *)(((unsigned char *)pGpuResource) + __nvoc_rtti_GpuUserSharedData_GpuResource.offset)); +static NV_STATUS __nvoc_thunk_RmResource_gpushareddataControl_Prologue(struct GpuUserSharedData *pResource, CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return rmresControl_Prologue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_GpuUserSharedData_RmResource.offset), pCallContext, pParams); } -static NV_STATUS __nvoc_thunk_RsResource_gpushareddataControlFilter(struct GpuUserSharedData *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { - return resControlFilter((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_GpuUserSharedData_RsResource.offset), pCallContext, pParams); +static NvBool __nvoc_thunk_Memory_gpushareddataIsGpuMapAllowed(struct GpuUserSharedData *pMemory, struct OBJGPU *pGpu) { + return memIsGpuMapAllowed((struct Memory *)(((unsigned char *)pMemory) + __nvoc_rtti_GpuUserSharedData_Memory.offset), pGpu); } -static void __nvoc_thunk_RsResource_gpushareddataAddAdditionalDependants(struct RsClient *pClient, struct GpuUserSharedData *pResource, RsResourceRef *pReference) { - resAddAdditionalDependants(pClient, (struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_GpuUserSharedData_RsResource.offset), pReference); +static NV_STATUS __nvoc_thunk_RsResource_gpushareddataUnmapFrom(struct GpuUserSharedData *pResource, RS_RES_UNMAP_FROM_PARAMS *pParams) { + return resUnmapFrom((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_GpuUserSharedData_RsResource.offset), pParams); } -static NvU32 __nvoc_thunk_RsResource_gpushareddataGetRefCount(struct GpuUserSharedData *pResource) { - return resGetRefCount((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_GpuUserSharedData_RsResource.offset)); +static void __nvoc_thunk_RmResource_gpushareddataControl_Epilogue(struct GpuUserSharedData *pResource, CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + rmresControl_Epilogue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_GpuUserSharedData_RmResource.offset), pCallContext, pParams); } -static NV_STATUS __nvoc_thunk_RmResource_gpushareddataCheckMemInterUnmap(struct GpuUserSharedData *pRmResource, NvBool bSubdeviceHandleProvided) { - return rmresCheckMemInterUnmap((struct RmResource *)(((unsigned char *)pRmResource) + __nvoc_rtti_GpuUserSharedData_RmResource.offset), bSubdeviceHandleProvided); +static NV_STATUS __nvoc_thunk_RsResource_gpushareddataControlLookup(struct GpuUserSharedData *pResource, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams, const struct NVOC_EXPORTED_METHOD_DEF **ppEntry) { + return resControlLookup((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_GpuUserSharedData_RsResource.offset), pParams, ppEntry); } -static NV_STATUS __nvoc_thunk_RsResource_gpushareddataMapTo(struct GpuUserSharedData *pResource, RS_RES_MAP_TO_PARAMS *pParams) { - return resMapTo((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_GpuUserSharedData_RsResource.offset), pParams); +static NV_STATUS __nvoc_thunk_Memory_gpushareddataControl(struct GpuUserSharedData *pMemory, CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return memControl((struct Memory *)(((unsigned char *)pMemory) + __nvoc_rtti_GpuUserSharedData_Memory.offset), pCallContext, pParams); } -static NV_STATUS __nvoc_thunk_RmResource_gpushareddataControl_Prologue(struct GpuUserSharedData *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { - return rmresControl_Prologue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_GpuUserSharedData_RmResource.offset), pCallContext, pParams); +static NV_STATUS __nvoc_thunk_Memory_gpushareddataUnmap(struct GpuUserSharedData *pMemory, CALL_CONTEXT *pCallContext, RsCpuMapping *pCpuMapping) { + return memUnmap((struct Memory *)(((unsigned char *)pMemory) + __nvoc_rtti_GpuUserSharedData_Memory.offset), pCallContext, pCpuMapping); } -static NV_STATUS __nvoc_thunk_GpuResource_gpushareddataGetRegBaseOffsetAndSize(struct GpuUserSharedData *pGpuResource, struct OBJGPU *pGpu, NvU32 *pOffset, NvU32 *pSize) { - return gpuresGetRegBaseOffsetAndSize((struct GpuResource *)(((unsigned char *)pGpuResource) + __nvoc_rtti_GpuUserSharedData_GpuResource.offset), pGpu, pOffset, pSize); +static NV_STATUS __nvoc_thunk_Memory_gpushareddataGetMemInterMapParams(struct GpuUserSharedData *pMemory, RMRES_MEM_INTER_MAP_PARAMS *pParams) { + return memGetMemInterMapParams((struct Memory *)(((unsigned char *)pMemory) + __nvoc_rtti_GpuUserSharedData_Memory.offset), pParams); } -static NvBool __nvoc_thunk_RsResource_gpushareddataCanCopy(struct GpuUserSharedData *pResource) { - return resCanCopy((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_GpuUserSharedData_RsResource.offset)); +static NV_STATUS __nvoc_thunk_Memory_gpushareddataGetMemoryMappingDescriptor(struct GpuUserSharedData *pMemory, MEMORY_DESCRIPTOR **ppMemDesc) { + return memGetMemoryMappingDescriptor((struct Memory *)(((unsigned char *)pMemory) + __nvoc_rtti_GpuUserSharedData_Memory.offset), ppMemDesc); } -static NV_STATUS __nvoc_thunk_GpuResource_gpushareddataInternalControlForward(struct GpuUserSharedData *pGpuResource, NvU32 command, void *pParams, NvU32 size) { - return gpuresInternalControlForward((struct GpuResource *)(((unsigned char *)pGpuResource) + __nvoc_rtti_GpuUserSharedData_GpuResource.offset), command, pParams, size); +static NV_STATUS __nvoc_thunk_RsResource_gpushareddataControlFilter(struct GpuUserSharedData *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return resControlFilter((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_GpuUserSharedData_RsResource.offset), pCallContext, pParams); } -static void __nvoc_thunk_RsResource_gpushareddataPreDestruct(struct GpuUserSharedData *pResource) { - resPreDestruct((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_GpuUserSharedData_RsResource.offset)); +static NV_STATUS __nvoc_thunk_RmResource_gpushareddataControlSerialization_Prologue(struct GpuUserSharedData *pResource, CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return rmresControlSerialization_Prologue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_GpuUserSharedData_RmResource.offset), pCallContext, pParams); } -static NV_STATUS __nvoc_thunk_RsResource_gpushareddataUnmapFrom(struct GpuUserSharedData *pResource, RS_RES_UNMAP_FROM_PARAMS *pParams) { - return resUnmapFrom((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_GpuUserSharedData_RsResource.offset), pParams); +static NV_STATUS __nvoc_thunk_Memory_gpushareddataIsReady(struct GpuUserSharedData *pMemory, NvBool bCopyConstructorContext) { + return memIsReady((struct Memory *)(((unsigned char *)pMemory) + __nvoc_rtti_GpuUserSharedData_Memory.offset), bCopyConstructorContext); } -static NV_STATUS __nvoc_thunk_RsResource_gpushareddataIsDuplicate(struct GpuUserSharedData *pResource, NvHandle hMemory, NvBool *pDuplicate) { - return resIsDuplicate((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_GpuUserSharedData_RsResource.offset), hMemory, pDuplicate); +static NV_STATUS __nvoc_thunk_Memory_gpushareddataCheckCopyPermissions(struct GpuUserSharedData *pMemory, struct OBJGPU *pDstGpu, struct Device *pDstDevice) { + return memCheckCopyPermissions((struct Memory *)(((unsigned char *)pMemory) + __nvoc_rtti_GpuUserSharedData_Memory.offset), pDstGpu, pDstDevice); } -static void __nvoc_thunk_RmResource_gpushareddataControl_Epilogue(struct GpuUserSharedData *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { - rmresControl_Epilogue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_GpuUserSharedData_RmResource.offset), pCallContext, pParams); +static void __nvoc_thunk_RsResource_gpushareddataPreDestruct(struct GpuUserSharedData *pResource) { + resPreDestruct((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_GpuUserSharedData_RsResource.offset)); } -static NV_STATUS __nvoc_thunk_RsResource_gpushareddataControlLookup(struct GpuUserSharedData *pResource, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams, const struct NVOC_EXPORTED_METHOD_DEF **ppEntry) { - return resControlLookup((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_GpuUserSharedData_RsResource.offset), pParams, ppEntry); +static NV_STATUS __nvoc_thunk_Memory_gpushareddataIsDuplicate(struct GpuUserSharedData *pMemory, NvHandle hMemory, NvBool *pDuplicate) { + return memIsDuplicate((struct Memory *)(((unsigned char *)pMemory) + __nvoc_rtti_GpuUserSharedData_Memory.offset), hMemory, pDuplicate); +} + +static void __nvoc_thunk_RmResource_gpushareddataControlSerialization_Epilogue(struct GpuUserSharedData *pResource, CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + rmresControlSerialization_Epilogue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_GpuUserSharedData_RmResource.offset), pCallContext, pParams); +} + +static NV_STATUS __nvoc_thunk_Memory_gpushareddataMap(struct GpuUserSharedData *pMemory, CALL_CONTEXT *pCallContext, struct RS_CPU_MAP_PARAMS *pParams, RsCpuMapping *pCpuMapping) { + return memMap((struct Memory *)(((unsigned char *)pMemory) + __nvoc_rtti_GpuUserSharedData_Memory.offset), pCallContext, pParams, pCpuMapping); } static NvBool __nvoc_thunk_RmResource_gpushareddataAccessCallback(struct GpuUserSharedData *pResource, struct RsClient *pInvokingClient, void *pAllocParams, RsAccessRight accessRight) { @@ -191,10 +199,9 @@ /*pExportEntries=*/ 0 }; -void __nvoc_dtor_GpuResource(GpuResource*); +void __nvoc_dtor_Memory(Memory*); void __nvoc_dtor_GpuUserSharedData(GpuUserSharedData *pThis) { - __nvoc_gpushareddataDestruct(pThis); - __nvoc_dtor_GpuResource(&pThis->__nvoc_base_GpuResource); + __nvoc_dtor_Memory(&pThis->__nvoc_base_Memory); PORT_UNREFERENCED_VARIABLE(pThis); } @@ -202,11 +209,11 @@ PORT_UNREFERENCED_VARIABLE(pThis); } -NV_STATUS __nvoc_ctor_GpuResource(GpuResource* , struct CALL_CONTEXT *, struct RS_RES_ALLOC_PARAMS_INTERNAL *); -NV_STATUS __nvoc_ctor_GpuUserSharedData(GpuUserSharedData *pThis, struct CALL_CONTEXT * arg_pCallContext, struct RS_RES_ALLOC_PARAMS_INTERNAL * arg_pParams) { +NV_STATUS __nvoc_ctor_Memory(Memory* , CALL_CONTEXT *, struct RS_RES_ALLOC_PARAMS_INTERNAL *); +NV_STATUS __nvoc_ctor_GpuUserSharedData(GpuUserSharedData *pThis, CALL_CONTEXT * arg_pCallContext, struct RS_RES_ALLOC_PARAMS_INTERNAL * arg_pParams) { NV_STATUS status = NV_OK; - status = __nvoc_ctor_GpuResource(&pThis->__nvoc_base_GpuResource, arg_pCallContext, arg_pParams); - if (status != NV_OK) goto __nvoc_ctor_GpuUserSharedData_fail_GpuResource; + status = __nvoc_ctor_Memory(&pThis->__nvoc_base_Memory, arg_pCallContext, arg_pParams); + if (status != NV_OK) goto __nvoc_ctor_GpuUserSharedData_fail_Memory; __nvoc_init_dataField_GpuUserSharedData(pThis); status = __nvoc_gpushareddataConstruct(pThis, arg_pCallContext, arg_pParams); @@ -214,8 +221,8 @@ goto __nvoc_ctor_GpuUserSharedData_exit; // Success __nvoc_ctor_GpuUserSharedData_fail__init: - __nvoc_dtor_GpuResource(&pThis->__nvoc_base_GpuResource); -__nvoc_ctor_GpuUserSharedData_fail_GpuResource: + __nvoc_dtor_Memory(&pThis->__nvoc_base_Memory); +__nvoc_ctor_GpuUserSharedData_fail_Memory: __nvoc_ctor_GpuUserSharedData_exit: return status; @@ -224,57 +231,55 @@ static void __nvoc_init_funcTable_GpuUserSharedData_1(GpuUserSharedData *pThis) { PORT_UNREFERENCED_VARIABLE(pThis); - pThis->__gpushareddataMap__ = &gpushareddataMap_IMPL; + pThis->__gpushareddataCanCopy__ = &gpushareddataCanCopy_IMPL; - pThis->__gpushareddataUnmap__ = &gpushareddataUnmap_IMPL; + pThis->__nvoc_base_Memory.__nvoc_base_RmResource.__nvoc_base_RsResource.__resCanCopy__ = &__nvoc_thunk_GpuUserSharedData_resCanCopy; - pThis->__gpushareddataGetMapAddrSpace__ = &gpushareddataGetMapAddrSpace_IMPL; + pThis->__gpushareddataCheckMemInterUnmap__ = &__nvoc_thunk_Memory_gpushareddataCheckMemInterUnmap; - pThis->__gpushareddataGetMemoryMappingDescriptor__ = &gpushareddataGetMemoryMappingDescriptor_IMPL; + pThis->__gpushareddataShareCallback__ = &__nvoc_thunk_RmResource_gpushareddataShareCallback; - pThis->__nvoc_base_GpuResource.__gpuresMap__ = &__nvoc_thunk_GpuUserSharedData_gpuresMap; + pThis->__gpushareddataMapTo__ = &__nvoc_thunk_RsResource_gpushareddataMapTo; - pThis->__nvoc_base_GpuResource.__gpuresUnmap__ = &__nvoc_thunk_GpuUserSharedData_gpuresUnmap; + pThis->__gpushareddataGetMapAddrSpace__ = &__nvoc_thunk_Memory_gpushareddataGetMapAddrSpace; - pThis->__nvoc_base_GpuResource.__gpuresGetMapAddrSpace__ = &__nvoc_thunk_GpuUserSharedData_gpuresGetMapAddrSpace; + pThis->__gpushareddataGetRefCount__ = &__nvoc_thunk_RsResource_gpushareddataGetRefCount; - pThis->__nvoc_base_GpuResource.__nvoc_base_RmResource.__rmresGetMemoryMappingDescriptor__ = &__nvoc_thunk_GpuUserSharedData_rmresGetMemoryMappingDescriptor; + pThis->__gpushareddataAddAdditionalDependants__ = &__nvoc_thunk_RsResource_gpushareddataAddAdditionalDependants; - pThis->__gpushareddataShareCallback__ = &__nvoc_thunk_GpuResource_gpushareddataShareCallback; + pThis->__gpushareddataControl_Prologue__ = &__nvoc_thunk_RmResource_gpushareddataControl_Prologue; - pThis->__gpushareddataControl__ = &__nvoc_thunk_GpuResource_gpushareddataControl; + pThis->__gpushareddataIsGpuMapAllowed__ = &__nvoc_thunk_Memory_gpushareddataIsGpuMapAllowed; - pThis->__gpushareddataGetMemInterMapParams__ = &__nvoc_thunk_RmResource_gpushareddataGetMemInterMapParams; + pThis->__gpushareddataUnmapFrom__ = &__nvoc_thunk_RsResource_gpushareddataUnmapFrom; - pThis->__gpushareddataGetInternalObjectHandle__ = &__nvoc_thunk_GpuResource_gpushareddataGetInternalObjectHandle; + pThis->__gpushareddataControl_Epilogue__ = &__nvoc_thunk_RmResource_gpushareddataControl_Epilogue; - pThis->__gpushareddataControlFilter__ = &__nvoc_thunk_RsResource_gpushareddataControlFilter; + pThis->__gpushareddataControlLookup__ = &__nvoc_thunk_RsResource_gpushareddataControlLookup; - pThis->__gpushareddataAddAdditionalDependants__ = &__nvoc_thunk_RsResource_gpushareddataAddAdditionalDependants; + pThis->__gpushareddataControl__ = &__nvoc_thunk_Memory_gpushareddataControl; - pThis->__gpushareddataGetRefCount__ = &__nvoc_thunk_RsResource_gpushareddataGetRefCount; + pThis->__gpushareddataUnmap__ = &__nvoc_thunk_Memory_gpushareddataUnmap; - pThis->__gpushareddataCheckMemInterUnmap__ = &__nvoc_thunk_RmResource_gpushareddataCheckMemInterUnmap; + pThis->__gpushareddataGetMemInterMapParams__ = &__nvoc_thunk_Memory_gpushareddataGetMemInterMapParams; - pThis->__gpushareddataMapTo__ = &__nvoc_thunk_RsResource_gpushareddataMapTo; + pThis->__gpushareddataGetMemoryMappingDescriptor__ = &__nvoc_thunk_Memory_gpushareddataGetMemoryMappingDescriptor; - pThis->__gpushareddataControl_Prologue__ = &__nvoc_thunk_RmResource_gpushareddataControl_Prologue; + pThis->__gpushareddataControlFilter__ = &__nvoc_thunk_RsResource_gpushareddataControlFilter; - pThis->__gpushareddataGetRegBaseOffsetAndSize__ = &__nvoc_thunk_GpuResource_gpushareddataGetRegBaseOffsetAndSize; + pThis->__gpushareddataControlSerialization_Prologue__ = &__nvoc_thunk_RmResource_gpushareddataControlSerialization_Prologue; - pThis->__gpushareddataCanCopy__ = &__nvoc_thunk_RsResource_gpushareddataCanCopy; + pThis->__gpushareddataIsReady__ = &__nvoc_thunk_Memory_gpushareddataIsReady; - pThis->__gpushareddataInternalControlForward__ = &__nvoc_thunk_GpuResource_gpushareddataInternalControlForward; + pThis->__gpushareddataCheckCopyPermissions__ = &__nvoc_thunk_Memory_gpushareddataCheckCopyPermissions; pThis->__gpushareddataPreDestruct__ = &__nvoc_thunk_RsResource_gpushareddataPreDestruct; - pThis->__gpushareddataUnmapFrom__ = &__nvoc_thunk_RsResource_gpushareddataUnmapFrom; - - pThis->__gpushareddataIsDuplicate__ = &__nvoc_thunk_RsResource_gpushareddataIsDuplicate; + pThis->__gpushareddataIsDuplicate__ = &__nvoc_thunk_Memory_gpushareddataIsDuplicate; - pThis->__gpushareddataControl_Epilogue__ = &__nvoc_thunk_RmResource_gpushareddataControl_Epilogue; + pThis->__gpushareddataControlSerialization_Epilogue__ = &__nvoc_thunk_RmResource_gpushareddataControlSerialization_Epilogue; - pThis->__gpushareddataControlLookup__ = &__nvoc_thunk_RsResource_gpushareddataControlLookup; + pThis->__gpushareddataMap__ = &__nvoc_thunk_Memory_gpushareddataMap; pThis->__gpushareddataAccessCallback__ = &__nvoc_thunk_RmResource_gpushareddataAccessCallback; } @@ -283,38 +288,41 @@ __nvoc_init_funcTable_GpuUserSharedData_1(pThis); } -void __nvoc_init_GpuResource(GpuResource*); +void __nvoc_init_Memory(Memory*); void __nvoc_init_GpuUserSharedData(GpuUserSharedData *pThis) { pThis->__nvoc_pbase_GpuUserSharedData = pThis; - pThis->__nvoc_pbase_Object = &pThis->__nvoc_base_GpuResource.__nvoc_base_RmResource.__nvoc_base_RsResource.__nvoc_base_Object; - pThis->__nvoc_pbase_RsResource = &pThis->__nvoc_base_GpuResource.__nvoc_base_RmResource.__nvoc_base_RsResource; - pThis->__nvoc_pbase_RmResourceCommon = &pThis->__nvoc_base_GpuResource.__nvoc_base_RmResource.__nvoc_base_RmResourceCommon; - pThis->__nvoc_pbase_RmResource = &pThis->__nvoc_base_GpuResource.__nvoc_base_RmResource; - pThis->__nvoc_pbase_GpuResource = &pThis->__nvoc_base_GpuResource; - __nvoc_init_GpuResource(&pThis->__nvoc_base_GpuResource); + pThis->__nvoc_pbase_Object = &pThis->__nvoc_base_Memory.__nvoc_base_RmResource.__nvoc_base_RsResource.__nvoc_base_Object; + pThis->__nvoc_pbase_RsResource = &pThis->__nvoc_base_Memory.__nvoc_base_RmResource.__nvoc_base_RsResource; + pThis->__nvoc_pbase_RmResourceCommon = &pThis->__nvoc_base_Memory.__nvoc_base_RmResource.__nvoc_base_RmResourceCommon; + pThis->__nvoc_pbase_RmResource = &pThis->__nvoc_base_Memory.__nvoc_base_RmResource; + pThis->__nvoc_pbase_Memory = &pThis->__nvoc_base_Memory; + __nvoc_init_Memory(&pThis->__nvoc_base_Memory); __nvoc_init_funcTable_GpuUserSharedData(pThis); } -NV_STATUS __nvoc_objCreate_GpuUserSharedData(GpuUserSharedData **ppThis, Dynamic *pParent, NvU32 createFlags, struct CALL_CONTEXT * arg_pCallContext, struct RS_RES_ALLOC_PARAMS_INTERNAL * arg_pParams) { +NV_STATUS __nvoc_objCreate_GpuUserSharedData(GpuUserSharedData **ppThis, Dynamic *pParent, NvU32 createFlags, CALL_CONTEXT * arg_pCallContext, struct RS_RES_ALLOC_PARAMS_INTERNAL * arg_pParams) { NV_STATUS status; Object *pParentObj; GpuUserSharedData *pThis; - pThis = portMemAllocNonPaged(sizeof(GpuUserSharedData)); - if (pThis == NULL) return NV_ERR_NO_MEMORY; + status = __nvoc_handleObjCreateMemAlloc(createFlags, sizeof(GpuUserSharedData), (void**)&pThis, (void**)ppThis); + if (status != NV_OK) + return status; portMemSet(pThis, 0, sizeof(GpuUserSharedData)); __nvoc_initRtti(staticCast(pThis, Dynamic), &__nvoc_class_def_GpuUserSharedData); + pThis->__nvoc_base_Memory.__nvoc_base_RmResource.__nvoc_base_RsResource.__nvoc_base_Object.createFlags = createFlags; + if (pParent != NULL && !(createFlags & NVOC_OBJ_CREATE_FLAGS_PARENT_HALSPEC_ONLY)) { pParentObj = dynamicCast(pParent, Object); - objAddChild(pParentObj, &pThis->__nvoc_base_GpuResource.__nvoc_base_RmResource.__nvoc_base_RsResource.__nvoc_base_Object); + objAddChild(pParentObj, &pThis->__nvoc_base_Memory.__nvoc_base_RmResource.__nvoc_base_RsResource.__nvoc_base_Object); } else { - pThis->__nvoc_base_GpuResource.__nvoc_base_RmResource.__nvoc_base_RsResource.__nvoc_base_Object.pParent = NULL; + pThis->__nvoc_base_Memory.__nvoc_base_RmResource.__nvoc_base_RsResource.__nvoc_base_Object.pParent = NULL; } __nvoc_init_GpuUserSharedData(pThis); @@ -322,17 +330,23 @@ if (status != NV_OK) goto __nvoc_objCreate_GpuUserSharedData_cleanup; *ppThis = pThis; + return NV_OK; __nvoc_objCreate_GpuUserSharedData_cleanup: // do not call destructors here since the constructor already called them - portMemFree(pThis); + if (createFlags & NVOC_OBJ_CREATE_FLAGS_IN_PLACE_CONSTRUCT) + portMemSet(pThis, 0, sizeof(GpuUserSharedData)); + else + portMemFree(pThis); + + // coverity[leaked_storage:FALSE] return status; } NV_STATUS __nvoc_objCreateDynamic_GpuUserSharedData(GpuUserSharedData **ppThis, Dynamic *pParent, NvU32 createFlags, va_list args) { NV_STATUS status; - struct CALL_CONTEXT * arg_pCallContext = va_arg(args, struct CALL_CONTEXT *); + CALL_CONTEXT * arg_pCallContext = va_arg(args, CALL_CONTEXT *); struct RS_RES_ALLOC_PARAMS_INTERNAL * arg_pParams = va_arg(args, struct RS_RES_ALLOC_PARAMS_INTERNAL *); status = __nvoc_objCreate_GpuUserSharedData(ppThis, pParent, createFlags, arg_pCallContext, arg_pParams); diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/generated/g_gpu_user_shared_data_nvoc.h nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_gpu_user_shared_data_nvoc.h --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/generated/g_gpu_user_shared_data_nvoc.h 2023-10-25 20:27:00.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_gpu_user_shared_data_nvoc.h 2024-03-05 22:18:17.000000000 +0000 @@ -35,8 +35,9 @@ #define GPU_USER_SHARED_DATA_H #include "core/core.h" -#include "gpu/gpu_resource.h" -#include "gpu/mem_mgr/mem_desc.h" +#include "mem_mgr/mem.h" +#include "gpu/gpu.h" +#include "nvoc/utility.h" // **************************************************************************** // Type definitions @@ -52,35 +53,37 @@ #endif struct GpuUserSharedData { const struct NVOC_RTTI *__nvoc_rtti; - struct GpuResource __nvoc_base_GpuResource; + struct Memory __nvoc_base_Memory; struct Object *__nvoc_pbase_Object; struct RsResource *__nvoc_pbase_RsResource; struct RmResourceCommon *__nvoc_pbase_RmResourceCommon; struct RmResource *__nvoc_pbase_RmResource; - struct GpuResource *__nvoc_pbase_GpuResource; + struct Memory *__nvoc_pbase_Memory; struct GpuUserSharedData *__nvoc_pbase_GpuUserSharedData; - NV_STATUS (*__gpushareddataMap__)(struct GpuUserSharedData *, struct CALL_CONTEXT *, struct RS_CPU_MAP_PARAMS *, struct RsCpuMapping *); - NV_STATUS (*__gpushareddataUnmap__)(struct GpuUserSharedData *, struct CALL_CONTEXT *, struct RsCpuMapping *); - NV_STATUS (*__gpushareddataGetMapAddrSpace__)(struct GpuUserSharedData *, struct CALL_CONTEXT *, NvU32, NV_ADDRESS_SPACE *); - NV_STATUS (*__gpushareddataGetMemoryMappingDescriptor__)(struct GpuUserSharedData *, struct MEMORY_DESCRIPTOR **); + NvBool (*__gpushareddataCanCopy__)(struct GpuUserSharedData *); + NV_STATUS (*__gpushareddataCheckMemInterUnmap__)(struct GpuUserSharedData *, NvBool); NvBool (*__gpushareddataShareCallback__)(struct GpuUserSharedData *, struct RsClient *, struct RsResourceRef *, RS_SHARE_POLICY *); - NV_STATUS (*__gpushareddataControl__)(struct GpuUserSharedData *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); + NV_STATUS (*__gpushareddataMapTo__)(struct GpuUserSharedData *, RS_RES_MAP_TO_PARAMS *); + NV_STATUS (*__gpushareddataGetMapAddrSpace__)(struct GpuUserSharedData *, CALL_CONTEXT *, NvU32, NV_ADDRESS_SPACE *); + NvU32 (*__gpushareddataGetRefCount__)(struct GpuUserSharedData *); + void (*__gpushareddataAddAdditionalDependants__)(struct RsClient *, struct GpuUserSharedData *, RsResourceRef *); + NV_STATUS (*__gpushareddataControl_Prologue__)(struct GpuUserSharedData *, CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); + NvBool (*__gpushareddataIsGpuMapAllowed__)(struct GpuUserSharedData *, struct OBJGPU *); + NV_STATUS (*__gpushareddataUnmapFrom__)(struct GpuUserSharedData *, RS_RES_UNMAP_FROM_PARAMS *); + void (*__gpushareddataControl_Epilogue__)(struct GpuUserSharedData *, CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); + NV_STATUS (*__gpushareddataControlLookup__)(struct GpuUserSharedData *, struct RS_RES_CONTROL_PARAMS_INTERNAL *, const struct NVOC_EXPORTED_METHOD_DEF **); + NV_STATUS (*__gpushareddataControl__)(struct GpuUserSharedData *, CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); + NV_STATUS (*__gpushareddataUnmap__)(struct GpuUserSharedData *, CALL_CONTEXT *, RsCpuMapping *); NV_STATUS (*__gpushareddataGetMemInterMapParams__)(struct GpuUserSharedData *, RMRES_MEM_INTER_MAP_PARAMS *); - NvHandle (*__gpushareddataGetInternalObjectHandle__)(struct GpuUserSharedData *); + NV_STATUS (*__gpushareddataGetMemoryMappingDescriptor__)(struct GpuUserSharedData *, MEMORY_DESCRIPTOR **); NV_STATUS (*__gpushareddataControlFilter__)(struct GpuUserSharedData *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); - void (*__gpushareddataAddAdditionalDependants__)(struct RsClient *, struct GpuUserSharedData *, RsResourceRef *); - NvU32 (*__gpushareddataGetRefCount__)(struct GpuUserSharedData *); - NV_STATUS (*__gpushareddataCheckMemInterUnmap__)(struct GpuUserSharedData *, NvBool); - NV_STATUS (*__gpushareddataMapTo__)(struct GpuUserSharedData *, RS_RES_MAP_TO_PARAMS *); - NV_STATUS (*__gpushareddataControl_Prologue__)(struct GpuUserSharedData *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); - NV_STATUS (*__gpushareddataGetRegBaseOffsetAndSize__)(struct GpuUserSharedData *, struct OBJGPU *, NvU32 *, NvU32 *); - NvBool (*__gpushareddataCanCopy__)(struct GpuUserSharedData *); - NV_STATUS (*__gpushareddataInternalControlForward__)(struct GpuUserSharedData *, NvU32, void *, NvU32); + NV_STATUS (*__gpushareddataControlSerialization_Prologue__)(struct GpuUserSharedData *, CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); + NV_STATUS (*__gpushareddataIsReady__)(struct GpuUserSharedData *, NvBool); + NV_STATUS (*__gpushareddataCheckCopyPermissions__)(struct GpuUserSharedData *, struct OBJGPU *, struct Device *); void (*__gpushareddataPreDestruct__)(struct GpuUserSharedData *); - NV_STATUS (*__gpushareddataUnmapFrom__)(struct GpuUserSharedData *, RS_RES_UNMAP_FROM_PARAMS *); NV_STATUS (*__gpushareddataIsDuplicate__)(struct GpuUserSharedData *, NvHandle, NvBool *); - void (*__gpushareddataControl_Epilogue__)(struct GpuUserSharedData *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); - NV_STATUS (*__gpushareddataControlLookup__)(struct GpuUserSharedData *, struct RS_RES_CONTROL_PARAMS_INTERNAL *, const struct NVOC_EXPORTED_METHOD_DEF **); + void (*__gpushareddataControlSerialization_Epilogue__)(struct GpuUserSharedData *, CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); + NV_STATUS (*__gpushareddataMap__)(struct GpuUserSharedData *, CALL_CONTEXT *, struct RS_CPU_MAP_PARAMS *, RsCpuMapping *); NvBool (*__gpushareddataAccessCallback__)(struct GpuUserSharedData *, struct RsClient *, void *, RsAccessRight); }; @@ -108,139 +111,140 @@ NV_STATUS __nvoc_objCreateDynamic_GpuUserSharedData(GpuUserSharedData**, Dynamic*, NvU32, va_list); -NV_STATUS __nvoc_objCreate_GpuUserSharedData(GpuUserSharedData**, Dynamic*, NvU32, struct CALL_CONTEXT * arg_pCallContext, struct RS_RES_ALLOC_PARAMS_INTERNAL * arg_pParams); +NV_STATUS __nvoc_objCreate_GpuUserSharedData(GpuUserSharedData**, Dynamic*, NvU32, CALL_CONTEXT * arg_pCallContext, struct RS_RES_ALLOC_PARAMS_INTERNAL * arg_pParams); #define __objCreate_GpuUserSharedData(ppNewObj, pParent, createFlags, arg_pCallContext, arg_pParams) \ __nvoc_objCreate_GpuUserSharedData((ppNewObj), staticCast((pParent), Dynamic), (createFlags), arg_pCallContext, arg_pParams) -#define gpushareddataMap(pData, pCallContext, pParams, pCpuMapping) gpushareddataMap_DISPATCH(pData, pCallContext, pParams, pCpuMapping) -#define gpushareddataUnmap(pData, pCallContext, pCpuMapping) gpushareddataUnmap_DISPATCH(pData, pCallContext, pCpuMapping) -#define gpushareddataGetMapAddrSpace(pData, pCallContext, mapFlags, pAddrSpace) gpushareddataGetMapAddrSpace_DISPATCH(pData, pCallContext, mapFlags, pAddrSpace) -#define gpushareddataGetMemoryMappingDescriptor(pData, ppMemDesc) gpushareddataGetMemoryMappingDescriptor_DISPATCH(pData, ppMemDesc) -#define gpushareddataShareCallback(pGpuResource, pInvokingClient, pParentRef, pSharePolicy) gpushareddataShareCallback_DISPATCH(pGpuResource, pInvokingClient, pParentRef, pSharePolicy) -#define gpushareddataControl(pGpuResource, pCallContext, pParams) gpushareddataControl_DISPATCH(pGpuResource, pCallContext, pParams) -#define gpushareddataGetMemInterMapParams(pRmResource, pParams) gpushareddataGetMemInterMapParams_DISPATCH(pRmResource, pParams) -#define gpushareddataGetInternalObjectHandle(pGpuResource) gpushareddataGetInternalObjectHandle_DISPATCH(pGpuResource) -#define gpushareddataControlFilter(pResource, pCallContext, pParams) gpushareddataControlFilter_DISPATCH(pResource, pCallContext, pParams) -#define gpushareddataAddAdditionalDependants(pClient, pResource, pReference) gpushareddataAddAdditionalDependants_DISPATCH(pClient, pResource, pReference) -#define gpushareddataGetRefCount(pResource) gpushareddataGetRefCount_DISPATCH(pResource) -#define gpushareddataCheckMemInterUnmap(pRmResource, bSubdeviceHandleProvided) gpushareddataCheckMemInterUnmap_DISPATCH(pRmResource, bSubdeviceHandleProvided) +#define gpushareddataCanCopy(pData) gpushareddataCanCopy_DISPATCH(pData) +#define gpushareddataCheckMemInterUnmap(pMemory, bSubdeviceHandleProvided) gpushareddataCheckMemInterUnmap_DISPATCH(pMemory, bSubdeviceHandleProvided) +#define gpushareddataShareCallback(pResource, pInvokingClient, pParentRef, pSharePolicy) gpushareddataShareCallback_DISPATCH(pResource, pInvokingClient, pParentRef, pSharePolicy) #define gpushareddataMapTo(pResource, pParams) gpushareddataMapTo_DISPATCH(pResource, pParams) +#define gpushareddataGetMapAddrSpace(pMemory, pCallContext, mapFlags, pAddrSpace) gpushareddataGetMapAddrSpace_DISPATCH(pMemory, pCallContext, mapFlags, pAddrSpace) +#define gpushareddataGetRefCount(pResource) gpushareddataGetRefCount_DISPATCH(pResource) +#define gpushareddataAddAdditionalDependants(pClient, pResource, pReference) gpushareddataAddAdditionalDependants_DISPATCH(pClient, pResource, pReference) #define gpushareddataControl_Prologue(pResource, pCallContext, pParams) gpushareddataControl_Prologue_DISPATCH(pResource, pCallContext, pParams) -#define gpushareddataGetRegBaseOffsetAndSize(pGpuResource, pGpu, pOffset, pSize) gpushareddataGetRegBaseOffsetAndSize_DISPATCH(pGpuResource, pGpu, pOffset, pSize) -#define gpushareddataCanCopy(pResource) gpushareddataCanCopy_DISPATCH(pResource) -#define gpushareddataInternalControlForward(pGpuResource, command, pParams, size) gpushareddataInternalControlForward_DISPATCH(pGpuResource, command, pParams, size) -#define gpushareddataPreDestruct(pResource) gpushareddataPreDestruct_DISPATCH(pResource) +#define gpushareddataIsGpuMapAllowed(pMemory, pGpu) gpushareddataIsGpuMapAllowed_DISPATCH(pMemory, pGpu) #define gpushareddataUnmapFrom(pResource, pParams) gpushareddataUnmapFrom_DISPATCH(pResource, pParams) -#define gpushareddataIsDuplicate(pResource, hMemory, pDuplicate) gpushareddataIsDuplicate_DISPATCH(pResource, hMemory, pDuplicate) #define gpushareddataControl_Epilogue(pResource, pCallContext, pParams) gpushareddataControl_Epilogue_DISPATCH(pResource, pCallContext, pParams) #define gpushareddataControlLookup(pResource, pParams, ppEntry) gpushareddataControlLookup_DISPATCH(pResource, pParams, ppEntry) +#define gpushareddataControl(pMemory, pCallContext, pParams) gpushareddataControl_DISPATCH(pMemory, pCallContext, pParams) +#define gpushareddataUnmap(pMemory, pCallContext, pCpuMapping) gpushareddataUnmap_DISPATCH(pMemory, pCallContext, pCpuMapping) +#define gpushareddataGetMemInterMapParams(pMemory, pParams) gpushareddataGetMemInterMapParams_DISPATCH(pMemory, pParams) +#define gpushareddataGetMemoryMappingDescriptor(pMemory, ppMemDesc) gpushareddataGetMemoryMappingDescriptor_DISPATCH(pMemory, ppMemDesc) +#define gpushareddataControlFilter(pResource, pCallContext, pParams) gpushareddataControlFilter_DISPATCH(pResource, pCallContext, pParams) +#define gpushareddataControlSerialization_Prologue(pResource, pCallContext, pParams) gpushareddataControlSerialization_Prologue_DISPATCH(pResource, pCallContext, pParams) +#define gpushareddataIsReady(pMemory, bCopyConstructorContext) gpushareddataIsReady_DISPATCH(pMemory, bCopyConstructorContext) +#define gpushareddataCheckCopyPermissions(pMemory, pDstGpu, pDstDevice) gpushareddataCheckCopyPermissions_DISPATCH(pMemory, pDstGpu, pDstDevice) +#define gpushareddataPreDestruct(pResource) gpushareddataPreDestruct_DISPATCH(pResource) +#define gpushareddataIsDuplicate(pMemory, hMemory, pDuplicate) gpushareddataIsDuplicate_DISPATCH(pMemory, hMemory, pDuplicate) +#define gpushareddataControlSerialization_Epilogue(pResource, pCallContext, pParams) gpushareddataControlSerialization_Epilogue_DISPATCH(pResource, pCallContext, pParams) +#define gpushareddataMap(pMemory, pCallContext, pParams, pCpuMapping) gpushareddataMap_DISPATCH(pMemory, pCallContext, pParams, pCpuMapping) #define gpushareddataAccessCallback(pResource, pInvokingClient, pAllocParams, accessRight) gpushareddataAccessCallback_DISPATCH(pResource, pInvokingClient, pAllocParams, accessRight) -NV_STATUS gpushareddataMap_IMPL(struct GpuUserSharedData *pData, struct CALL_CONTEXT *pCallContext, struct RS_CPU_MAP_PARAMS *pParams, struct RsCpuMapping *pCpuMapping); +NvBool gpushareddataCanCopy_IMPL(struct GpuUserSharedData *pData); -static inline NV_STATUS gpushareddataMap_DISPATCH(struct GpuUserSharedData *pData, struct CALL_CONTEXT *pCallContext, struct RS_CPU_MAP_PARAMS *pParams, struct RsCpuMapping *pCpuMapping) { - return pData->__gpushareddataMap__(pData, pCallContext, pParams, pCpuMapping); +static inline NvBool gpushareddataCanCopy_DISPATCH(struct GpuUserSharedData *pData) { + return pData->__gpushareddataCanCopy__(pData); } -NV_STATUS gpushareddataUnmap_IMPL(struct GpuUserSharedData *pData, struct CALL_CONTEXT *pCallContext, struct RsCpuMapping *pCpuMapping); +static inline NV_STATUS gpushareddataCheckMemInterUnmap_DISPATCH(struct GpuUserSharedData *pMemory, NvBool bSubdeviceHandleProvided) { + return pMemory->__gpushareddataCheckMemInterUnmap__(pMemory, bSubdeviceHandleProvided); +} -static inline NV_STATUS gpushareddataUnmap_DISPATCH(struct GpuUserSharedData *pData, struct CALL_CONTEXT *pCallContext, struct RsCpuMapping *pCpuMapping) { - return pData->__gpushareddataUnmap__(pData, pCallContext, pCpuMapping); +static inline NvBool gpushareddataShareCallback_DISPATCH(struct GpuUserSharedData *pResource, struct RsClient *pInvokingClient, struct RsResourceRef *pParentRef, RS_SHARE_POLICY *pSharePolicy) { + return pResource->__gpushareddataShareCallback__(pResource, pInvokingClient, pParentRef, pSharePolicy); } -NV_STATUS gpushareddataGetMapAddrSpace_IMPL(struct GpuUserSharedData *pData, struct CALL_CONTEXT *pCallContext, NvU32 mapFlags, NV_ADDRESS_SPACE *pAddrSpace); +static inline NV_STATUS gpushareddataMapTo_DISPATCH(struct GpuUserSharedData *pResource, RS_RES_MAP_TO_PARAMS *pParams) { + return pResource->__gpushareddataMapTo__(pResource, pParams); +} -static inline NV_STATUS gpushareddataGetMapAddrSpace_DISPATCH(struct GpuUserSharedData *pData, struct CALL_CONTEXT *pCallContext, NvU32 mapFlags, NV_ADDRESS_SPACE *pAddrSpace) { - return pData->__gpushareddataGetMapAddrSpace__(pData, pCallContext, mapFlags, pAddrSpace); +static inline NV_STATUS gpushareddataGetMapAddrSpace_DISPATCH(struct GpuUserSharedData *pMemory, CALL_CONTEXT *pCallContext, NvU32 mapFlags, NV_ADDRESS_SPACE *pAddrSpace) { + return pMemory->__gpushareddataGetMapAddrSpace__(pMemory, pCallContext, mapFlags, pAddrSpace); } -NV_STATUS gpushareddataGetMemoryMappingDescriptor_IMPL(struct GpuUserSharedData *pData, struct MEMORY_DESCRIPTOR **ppMemDesc); +static inline NvU32 gpushareddataGetRefCount_DISPATCH(struct GpuUserSharedData *pResource) { + return pResource->__gpushareddataGetRefCount__(pResource); +} -static inline NV_STATUS gpushareddataGetMemoryMappingDescriptor_DISPATCH(struct GpuUserSharedData *pData, struct MEMORY_DESCRIPTOR **ppMemDesc) { - return pData->__gpushareddataGetMemoryMappingDescriptor__(pData, ppMemDesc); +static inline void gpushareddataAddAdditionalDependants_DISPATCH(struct RsClient *pClient, struct GpuUserSharedData *pResource, RsResourceRef *pReference) { + pResource->__gpushareddataAddAdditionalDependants__(pClient, pResource, pReference); } -static inline NvBool gpushareddataShareCallback_DISPATCH(struct GpuUserSharedData *pGpuResource, struct RsClient *pInvokingClient, struct RsResourceRef *pParentRef, RS_SHARE_POLICY *pSharePolicy) { - return pGpuResource->__gpushareddataShareCallback__(pGpuResource, pInvokingClient, pParentRef, pSharePolicy); +static inline NV_STATUS gpushareddataControl_Prologue_DISPATCH(struct GpuUserSharedData *pResource, CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return pResource->__gpushareddataControl_Prologue__(pResource, pCallContext, pParams); } -static inline NV_STATUS gpushareddataControl_DISPATCH(struct GpuUserSharedData *pGpuResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { - return pGpuResource->__gpushareddataControl__(pGpuResource, pCallContext, pParams); +static inline NvBool gpushareddataIsGpuMapAllowed_DISPATCH(struct GpuUserSharedData *pMemory, struct OBJGPU *pGpu) { + return pMemory->__gpushareddataIsGpuMapAllowed__(pMemory, pGpu); } -static inline NV_STATUS gpushareddataGetMemInterMapParams_DISPATCH(struct GpuUserSharedData *pRmResource, RMRES_MEM_INTER_MAP_PARAMS *pParams) { - return pRmResource->__gpushareddataGetMemInterMapParams__(pRmResource, pParams); +static inline NV_STATUS gpushareddataUnmapFrom_DISPATCH(struct GpuUserSharedData *pResource, RS_RES_UNMAP_FROM_PARAMS *pParams) { + return pResource->__gpushareddataUnmapFrom__(pResource, pParams); } -static inline NvHandle gpushareddataGetInternalObjectHandle_DISPATCH(struct GpuUserSharedData *pGpuResource) { - return pGpuResource->__gpushareddataGetInternalObjectHandle__(pGpuResource); +static inline void gpushareddataControl_Epilogue_DISPATCH(struct GpuUserSharedData *pResource, CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + pResource->__gpushareddataControl_Epilogue__(pResource, pCallContext, pParams); } -static inline NV_STATUS gpushareddataControlFilter_DISPATCH(struct GpuUserSharedData *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { - return pResource->__gpushareddataControlFilter__(pResource, pCallContext, pParams); +static inline NV_STATUS gpushareddataControlLookup_DISPATCH(struct GpuUserSharedData *pResource, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams, const struct NVOC_EXPORTED_METHOD_DEF **ppEntry) { + return pResource->__gpushareddataControlLookup__(pResource, pParams, ppEntry); } -static inline void gpushareddataAddAdditionalDependants_DISPATCH(struct RsClient *pClient, struct GpuUserSharedData *pResource, RsResourceRef *pReference) { - pResource->__gpushareddataAddAdditionalDependants__(pClient, pResource, pReference); +static inline NV_STATUS gpushareddataControl_DISPATCH(struct GpuUserSharedData *pMemory, CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return pMemory->__gpushareddataControl__(pMemory, pCallContext, pParams); } -static inline NvU32 gpushareddataGetRefCount_DISPATCH(struct GpuUserSharedData *pResource) { - return pResource->__gpushareddataGetRefCount__(pResource); +static inline NV_STATUS gpushareddataUnmap_DISPATCH(struct GpuUserSharedData *pMemory, CALL_CONTEXT *pCallContext, RsCpuMapping *pCpuMapping) { + return pMemory->__gpushareddataUnmap__(pMemory, pCallContext, pCpuMapping); } -static inline NV_STATUS gpushareddataCheckMemInterUnmap_DISPATCH(struct GpuUserSharedData *pRmResource, NvBool bSubdeviceHandleProvided) { - return pRmResource->__gpushareddataCheckMemInterUnmap__(pRmResource, bSubdeviceHandleProvided); +static inline NV_STATUS gpushareddataGetMemInterMapParams_DISPATCH(struct GpuUserSharedData *pMemory, RMRES_MEM_INTER_MAP_PARAMS *pParams) { + return pMemory->__gpushareddataGetMemInterMapParams__(pMemory, pParams); } -static inline NV_STATUS gpushareddataMapTo_DISPATCH(struct GpuUserSharedData *pResource, RS_RES_MAP_TO_PARAMS *pParams) { - return pResource->__gpushareddataMapTo__(pResource, pParams); +static inline NV_STATUS gpushareddataGetMemoryMappingDescriptor_DISPATCH(struct GpuUserSharedData *pMemory, MEMORY_DESCRIPTOR **ppMemDesc) { + return pMemory->__gpushareddataGetMemoryMappingDescriptor__(pMemory, ppMemDesc); } -static inline NV_STATUS gpushareddataControl_Prologue_DISPATCH(struct GpuUserSharedData *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { - return pResource->__gpushareddataControl_Prologue__(pResource, pCallContext, pParams); +static inline NV_STATUS gpushareddataControlFilter_DISPATCH(struct GpuUserSharedData *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return pResource->__gpushareddataControlFilter__(pResource, pCallContext, pParams); } -static inline NV_STATUS gpushareddataGetRegBaseOffsetAndSize_DISPATCH(struct GpuUserSharedData *pGpuResource, struct OBJGPU *pGpu, NvU32 *pOffset, NvU32 *pSize) { - return pGpuResource->__gpushareddataGetRegBaseOffsetAndSize__(pGpuResource, pGpu, pOffset, pSize); +static inline NV_STATUS gpushareddataControlSerialization_Prologue_DISPATCH(struct GpuUserSharedData *pResource, CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return pResource->__gpushareddataControlSerialization_Prologue__(pResource, pCallContext, pParams); } -static inline NvBool gpushareddataCanCopy_DISPATCH(struct GpuUserSharedData *pResource) { - return pResource->__gpushareddataCanCopy__(pResource); +static inline NV_STATUS gpushareddataIsReady_DISPATCH(struct GpuUserSharedData *pMemory, NvBool bCopyConstructorContext) { + return pMemory->__gpushareddataIsReady__(pMemory, bCopyConstructorContext); } -static inline NV_STATUS gpushareddataInternalControlForward_DISPATCH(struct GpuUserSharedData *pGpuResource, NvU32 command, void *pParams, NvU32 size) { - return pGpuResource->__gpushareddataInternalControlForward__(pGpuResource, command, pParams, size); +static inline NV_STATUS gpushareddataCheckCopyPermissions_DISPATCH(struct GpuUserSharedData *pMemory, struct OBJGPU *pDstGpu, struct Device *pDstDevice) { + return pMemory->__gpushareddataCheckCopyPermissions__(pMemory, pDstGpu, pDstDevice); } static inline void gpushareddataPreDestruct_DISPATCH(struct GpuUserSharedData *pResource) { pResource->__gpushareddataPreDestruct__(pResource); } -static inline NV_STATUS gpushareddataUnmapFrom_DISPATCH(struct GpuUserSharedData *pResource, RS_RES_UNMAP_FROM_PARAMS *pParams) { - return pResource->__gpushareddataUnmapFrom__(pResource, pParams); -} - -static inline NV_STATUS gpushareddataIsDuplicate_DISPATCH(struct GpuUserSharedData *pResource, NvHandle hMemory, NvBool *pDuplicate) { - return pResource->__gpushareddataIsDuplicate__(pResource, hMemory, pDuplicate); +static inline NV_STATUS gpushareddataIsDuplicate_DISPATCH(struct GpuUserSharedData *pMemory, NvHandle hMemory, NvBool *pDuplicate) { + return pMemory->__gpushareddataIsDuplicate__(pMemory, hMemory, pDuplicate); } -static inline void gpushareddataControl_Epilogue_DISPATCH(struct GpuUserSharedData *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { - pResource->__gpushareddataControl_Epilogue__(pResource, pCallContext, pParams); +static inline void gpushareddataControlSerialization_Epilogue_DISPATCH(struct GpuUserSharedData *pResource, CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + pResource->__gpushareddataControlSerialization_Epilogue__(pResource, pCallContext, pParams); } -static inline NV_STATUS gpushareddataControlLookup_DISPATCH(struct GpuUserSharedData *pResource, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams, const struct NVOC_EXPORTED_METHOD_DEF **ppEntry) { - return pResource->__gpushareddataControlLookup__(pResource, pParams, ppEntry); +static inline NV_STATUS gpushareddataMap_DISPATCH(struct GpuUserSharedData *pMemory, CALL_CONTEXT *pCallContext, struct RS_CPU_MAP_PARAMS *pParams, RsCpuMapping *pCpuMapping) { + return pMemory->__gpushareddataMap__(pMemory, pCallContext, pParams, pCpuMapping); } static inline NvBool gpushareddataAccessCallback_DISPATCH(struct GpuUserSharedData *pResource, struct RsClient *pInvokingClient, void *pAllocParams, RsAccessRight accessRight) { return pResource->__gpushareddataAccessCallback__(pResource, pInvokingClient, pAllocParams, accessRight); } -NV_STATUS gpushareddataConstruct_IMPL(struct GpuUserSharedData *arg_pData, struct CALL_CONTEXT *arg_pCallContext, struct RS_RES_ALLOC_PARAMS_INTERNAL *arg_pParams); +NV_STATUS gpushareddataConstruct_IMPL(struct GpuUserSharedData *arg_pData, CALL_CONTEXT *arg_pCallContext, struct RS_RES_ALLOC_PARAMS_INTERNAL *arg_pParams); #define __nvoc_gpushareddataConstruct(arg_pData, arg_pCallContext, arg_pParams) gpushareddataConstruct_IMPL(arg_pData, arg_pCallContext, arg_pParams) -void gpushareddataDestruct_IMPL(struct GpuUserSharedData *pData); - -#define __nvoc_gpushareddataDestruct(pData) gpushareddataDestruct_IMPL(pData) #undef PRIVATE_FIELD diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/generated/g_gpu_vaspace_nvoc.c nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_gpu_vaspace_nvoc.c --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/generated/g_gpu_vaspace_nvoc.c 2023-10-25 20:27:00.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_gpu_vaspace_nvoc.c 2024-03-05 22:18:17.000000000 +0000 @@ -102,11 +102,11 @@ return gvaspaceGetHeap((struct OBJGVASPACE *)(((unsigned char *)pVAS) - __nvoc_rtti_OBJGVASPACE_OBJVASPACE.offset)); } -static NvU32 __nvoc_thunk_OBJGVASPACE_vaspaceGetMapPageSize(struct OBJVASPACE *pVAS, struct OBJGPU *pGpu, EMEMBLOCK *pMemBlock) { +static NvU64 __nvoc_thunk_OBJGVASPACE_vaspaceGetMapPageSize(struct OBJVASPACE *pVAS, struct OBJGPU *pGpu, EMEMBLOCK *pMemBlock) { return gvaspaceGetMapPageSize((struct OBJGVASPACE *)(((unsigned char *)pVAS) - __nvoc_rtti_OBJGVASPACE_OBJVASPACE.offset), pGpu, pMemBlock); } -static NvU32 __nvoc_thunk_OBJGVASPACE_vaspaceGetBigPageSize(struct OBJVASPACE *pVAS) { +static NvU64 __nvoc_thunk_OBJGVASPACE_vaspaceGetBigPageSize(struct OBJVASPACE *pVAS) { return gvaspaceGetBigPageSize((struct OBJGVASPACE *)(((unsigned char *)pVAS) - __nvoc_rtti_OBJGVASPACE_OBJVASPACE.offset)); } @@ -355,13 +355,16 @@ Object *pParentObj; OBJGVASPACE *pThis; - pThis = portMemAllocNonPaged(sizeof(OBJGVASPACE)); - if (pThis == NULL) return NV_ERR_NO_MEMORY; + status = __nvoc_handleObjCreateMemAlloc(createFlags, sizeof(OBJGVASPACE), (void**)&pThis, (void**)ppThis); + if (status != NV_OK) + return status; portMemSet(pThis, 0, sizeof(OBJGVASPACE)); __nvoc_initRtti(staticCast(pThis, Dynamic), &__nvoc_class_def_OBJGVASPACE); + pThis->__nvoc_base_OBJVASPACE.__nvoc_base_Object.createFlags = createFlags; + if (pParent != NULL && !(createFlags & NVOC_OBJ_CREATE_FLAGS_PARENT_HALSPEC_ONLY)) { pParentObj = dynamicCast(pParent, Object); @@ -377,11 +380,17 @@ if (status != NV_OK) goto __nvoc_objCreate_OBJGVASPACE_cleanup; *ppThis = pThis; + return NV_OK; __nvoc_objCreate_OBJGVASPACE_cleanup: // do not call destructors here since the constructor already called them - portMemFree(pThis); + if (createFlags & NVOC_OBJ_CREATE_FLAGS_IN_PLACE_CONSTRUCT) + portMemSet(pThis, 0, sizeof(OBJGVASPACE)); + else + portMemFree(pThis); + + // coverity[leaked_storage:FALSE] return status; } diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/generated/g_gpu_vaspace_nvoc.h nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_gpu_vaspace_nvoc.h --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/generated/g_gpu_vaspace_nvoc.h 2023-10-25 20:27:00.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_gpu_vaspace_nvoc.h 2024-03-05 22:18:17.000000000 +0000 @@ -227,8 +227,8 @@ NV_STATUS (*__gvaspaceMap__)(struct OBJGVASPACE *, struct OBJGPU *, const NvU64, const NvU64, const MMU_MAP_TARGET *, const VAS_MAP_FLAGS); void (*__gvaspaceUnmap__)(struct OBJGVASPACE *, struct OBJGPU *, const NvU64, const NvU64); struct OBJEHEAP *(*__gvaspaceGetHeap__)(struct OBJGVASPACE *); - NvU32 (*__gvaspaceGetMapPageSize__)(struct OBJGVASPACE *, struct OBJGPU *, EMEMBLOCK *); - NvU32 (*__gvaspaceGetBigPageSize__)(struct OBJGVASPACE *); + NvU64 (*__gvaspaceGetMapPageSize__)(struct OBJGVASPACE *, struct OBJGPU *, EMEMBLOCK *); + NvU64 (*__gvaspaceGetBigPageSize__)(struct OBJGVASPACE *); NvU32 (*__gvaspaceGetFlags__)(struct OBJGVASPACE *); NvBool (*__gvaspaceIsMirrored__)(struct OBJGVASPACE *); NvBool (*__gvaspaceIsFaultCapable__)(struct OBJGVASPACE *); @@ -249,8 +249,7 @@ NvU64 (*__gvaspaceGetVaLimit__)(struct OBJGVASPACE *); NvU64 (*__gvaspaceGetVaStart__)(struct OBJGVASPACE *); struct OBJEHEAP *pHeap; - NvU32 bigPageSize; - NvU64 maxPageSizeSupported; + NvU64 bigPageSize; NvU64 compPageSize; NvU64 extManagedAlign; NvU32 flags; @@ -386,15 +385,15 @@ return pVAS->__gvaspaceGetHeap__(pVAS); } -NvU32 gvaspaceGetMapPageSize_IMPL(struct OBJGVASPACE *pVAS, struct OBJGPU *pGpu, EMEMBLOCK *pMemBlock); +NvU64 gvaspaceGetMapPageSize_IMPL(struct OBJGVASPACE *pVAS, struct OBJGPU *pGpu, EMEMBLOCK *pMemBlock); -static inline NvU32 gvaspaceGetMapPageSize_DISPATCH(struct OBJGVASPACE *pVAS, struct OBJGPU *pGpu, EMEMBLOCK *pMemBlock) { +static inline NvU64 gvaspaceGetMapPageSize_DISPATCH(struct OBJGVASPACE *pVAS, struct OBJGPU *pGpu, EMEMBLOCK *pMemBlock) { return pVAS->__gvaspaceGetMapPageSize__(pVAS, pGpu, pMemBlock); } -NvU32 gvaspaceGetBigPageSize_IMPL(struct OBJGVASPACE *pVAS); +NvU64 gvaspaceGetBigPageSize_IMPL(struct OBJGVASPACE *pVAS); -static inline NvU32 gvaspaceGetBigPageSize_DISPATCH(struct OBJGVASPACE *pVAS) { +static inline NvU64 gvaspaceGetBigPageSize_DISPATCH(struct OBJGVASPACE *pVAS) { return pVAS->__gvaspaceGetBigPageSize__(pVAS); } diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/generated/g_gsync_api_nvoc.c nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_gsync_api_nvoc.c --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/generated/g_gsync_api_nvoc.c 2023-10-25 20:27:00.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_gsync_api_nvoc.c 2024-03-05 22:18:17.000000000 +0000 @@ -114,82 +114,90 @@ return rmresCheckMemInterUnmap((struct RmResource *)(((unsigned char *)pRmResource) + __nvoc_rtti_GSyncApi_RmResource.offset), bSubdeviceHandleProvided); } +static NV_STATUS __nvoc_thunk_RsResource_gsyncapiMapTo(struct GSyncApi *pResource, RS_RES_MAP_TO_PARAMS *pParams) { + return resMapTo((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_GSyncApi_RsResource.offset), pParams); +} + static NvBool __nvoc_thunk_RmResource_gsyncapiAccessCallback(struct GSyncApi *pResource, struct RsClient *pInvokingClient, void *pAllocParams, RsAccessRight accessRight) { return rmresAccessCallback((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_GSyncApi_RmResource.offset), pInvokingClient, pAllocParams, accessRight); } -static NV_STATUS __nvoc_thunk_RmResource_gsyncapiGetMemInterMapParams(struct GSyncApi *pRmResource, RMRES_MEM_INTER_MAP_PARAMS *pParams) { - return rmresGetMemInterMapParams((struct RmResource *)(((unsigned char *)pRmResource) + __nvoc_rtti_GSyncApi_RmResource.offset), pParams); +static void __nvoc_thunk_Notifier_gsyncapiSetNotificationShare(struct GSyncApi *pNotifier, struct NotifShare *pNotifShare) { + notifySetNotificationShare((struct Notifier *)(((unsigned char *)pNotifier) + __nvoc_rtti_GSyncApi_Notifier.offset), pNotifShare); } -static NV_STATUS __nvoc_thunk_RmResource_gsyncapiGetMemoryMappingDescriptor(struct GSyncApi *pRmResource, struct MEMORY_DESCRIPTOR **ppMemDesc) { - return rmresGetMemoryMappingDescriptor((struct RmResource *)(((unsigned char *)pRmResource) + __nvoc_rtti_GSyncApi_RmResource.offset), ppMemDesc); +static NvU32 __nvoc_thunk_RsResource_gsyncapiGetRefCount(struct GSyncApi *pResource) { + return resGetRefCount((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_GSyncApi_RsResource.offset)); } -static void __nvoc_thunk_Notifier_gsyncapiSetNotificationShare(struct GSyncApi *pNotifier, struct NotifShare *pNotifShare) { - notifySetNotificationShare((struct Notifier *)(((unsigned char *)pNotifier) + __nvoc_rtti_GSyncApi_Notifier.offset), pNotifShare); +static void __nvoc_thunk_RsResource_gsyncapiAddAdditionalDependants(struct RsClient *pClient, struct GSyncApi *pResource, RsResourceRef *pReference) { + resAddAdditionalDependants(pClient, (struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_GSyncApi_RsResource.offset), pReference); } -static NV_STATUS __nvoc_thunk_RsResource_gsyncapiControlFilter(struct GSyncApi *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { - return resControlFilter((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_GSyncApi_RsResource.offset), pCallContext, pParams); +static NV_STATUS __nvoc_thunk_RmResource_gsyncapiControl_Prologue(struct GSyncApi *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return rmresControl_Prologue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_GSyncApi_RmResource.offset), pCallContext, pParams); } -static NvU32 __nvoc_thunk_RsResource_gsyncapiGetRefCount(struct GSyncApi *pResource) { - return resGetRefCount((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_GSyncApi_RsResource.offset)); +static NV_STATUS __nvoc_thunk_RsResource_gsyncapiUnmapFrom(struct GSyncApi *pResource, RS_RES_UNMAP_FROM_PARAMS *pParams) { + return resUnmapFrom((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_GSyncApi_RsResource.offset), pParams); } -static NV_STATUS __nvoc_thunk_Notifier_gsyncapiUnregisterEvent(struct GSyncApi *pNotifier, NvHandle hNotifierClient, NvHandle hNotifierResource, NvHandle hEventClient, NvHandle hEvent) { - return notifyUnregisterEvent((struct Notifier *)(((unsigned char *)pNotifier) + __nvoc_rtti_GSyncApi_Notifier.offset), hNotifierClient, hNotifierResource, hEventClient, hEvent); +static void __nvoc_thunk_RmResource_gsyncapiControl_Epilogue(struct GSyncApi *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + rmresControl_Epilogue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_GSyncApi_RmResource.offset), pCallContext, pParams); +} + +static NV_STATUS __nvoc_thunk_RsResource_gsyncapiControlLookup(struct GSyncApi *pResource, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams, const struct NVOC_EXPORTED_METHOD_DEF **ppEntry) { + return resControlLookup((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_GSyncApi_RsResource.offset), pParams, ppEntry); } static NV_STATUS __nvoc_thunk_RsResource_gsyncapiUnmap(struct GSyncApi *pResource, struct CALL_CONTEXT *pCallContext, RsCpuMapping *pCpuMapping) { return resUnmap((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_GSyncApi_RsResource.offset), pCallContext, pCpuMapping); } -static NvBool __nvoc_thunk_RsResource_gsyncapiCanCopy(struct GSyncApi *pResource) { - return resCanCopy((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_GSyncApi_RsResource.offset)); +static NV_STATUS __nvoc_thunk_RmResource_gsyncapiGetMemInterMapParams(struct GSyncApi *pRmResource, RMRES_MEM_INTER_MAP_PARAMS *pParams) { + return rmresGetMemInterMapParams((struct RmResource *)(((unsigned char *)pRmResource) + __nvoc_rtti_GSyncApi_RmResource.offset), pParams); } -static NV_STATUS __nvoc_thunk_RmResource_gsyncapiControl_Prologue(struct GSyncApi *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { - return rmresControl_Prologue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_GSyncApi_RmResource.offset), pCallContext, pParams); +static NV_STATUS __nvoc_thunk_RmResource_gsyncapiGetMemoryMappingDescriptor(struct GSyncApi *pRmResource, struct MEMORY_DESCRIPTOR **ppMemDesc) { + return rmresGetMemoryMappingDescriptor((struct RmResource *)(((unsigned char *)pRmResource) + __nvoc_rtti_GSyncApi_RmResource.offset), ppMemDesc); } -static NV_STATUS __nvoc_thunk_RsResource_gsyncapiMapTo(struct GSyncApi *pResource, RS_RES_MAP_TO_PARAMS *pParams) { - return resMapTo((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_GSyncApi_RsResource.offset), pParams); +static NV_STATUS __nvoc_thunk_RsResource_gsyncapiControlFilter(struct GSyncApi *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return resControlFilter((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_GSyncApi_RsResource.offset), pCallContext, pParams); } -static void __nvoc_thunk_RsResource_gsyncapiAddAdditionalDependants(struct RsClient *pClient, struct GSyncApi *pResource, RsResourceRef *pReference) { - resAddAdditionalDependants(pClient, (struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_GSyncApi_RsResource.offset), pReference); +static NV_STATUS __nvoc_thunk_Notifier_gsyncapiUnregisterEvent(struct GSyncApi *pNotifier, NvHandle hNotifierClient, NvHandle hNotifierResource, NvHandle hEventClient, NvHandle hEvent) { + return notifyUnregisterEvent((struct Notifier *)(((unsigned char *)pNotifier) + __nvoc_rtti_GSyncApi_Notifier.offset), hNotifierClient, hNotifierResource, hEventClient, hEvent); } -static void __nvoc_thunk_RsResource_gsyncapiPreDestruct(struct GSyncApi *pResource) { - resPreDestruct((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_GSyncApi_RsResource.offset)); +static NV_STATUS __nvoc_thunk_RmResource_gsyncapiControlSerialization_Prologue(struct GSyncApi *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return rmresControlSerialization_Prologue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_GSyncApi_RmResource.offset), pCallContext, pParams); } -static NV_STATUS __nvoc_thunk_RsResource_gsyncapiUnmapFrom(struct GSyncApi *pResource, RS_RES_UNMAP_FROM_PARAMS *pParams) { - return resUnmapFrom((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_GSyncApi_RsResource.offset), pParams); +static NvBool __nvoc_thunk_RsResource_gsyncapiCanCopy(struct GSyncApi *pResource) { + return resCanCopy((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_GSyncApi_RsResource.offset)); +} + +static void __nvoc_thunk_RsResource_gsyncapiPreDestruct(struct GSyncApi *pResource) { + resPreDestruct((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_GSyncApi_RsResource.offset)); } static NV_STATUS __nvoc_thunk_RsResource_gsyncapiIsDuplicate(struct GSyncApi *pResource, NvHandle hMemory, NvBool *pDuplicate) { return resIsDuplicate((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_GSyncApi_RsResource.offset), hMemory, pDuplicate); } -static PEVENTNOTIFICATION *__nvoc_thunk_Notifier_gsyncapiGetNotificationListPtr(struct GSyncApi *pNotifier) { - return notifyGetNotificationListPtr((struct Notifier *)(((unsigned char *)pNotifier) + __nvoc_rtti_GSyncApi_Notifier.offset)); +static void __nvoc_thunk_RmResource_gsyncapiControlSerialization_Epilogue(struct GSyncApi *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + rmresControlSerialization_Epilogue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_GSyncApi_RmResource.offset), pCallContext, pParams); } -static void __nvoc_thunk_RmResource_gsyncapiControl_Epilogue(struct GSyncApi *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { - rmresControl_Epilogue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_GSyncApi_RmResource.offset), pCallContext, pParams); +static PEVENTNOTIFICATION *__nvoc_thunk_Notifier_gsyncapiGetNotificationListPtr(struct GSyncApi *pNotifier) { + return notifyGetNotificationListPtr((struct Notifier *)(((unsigned char *)pNotifier) + __nvoc_rtti_GSyncApi_Notifier.offset)); } static struct NotifShare *__nvoc_thunk_Notifier_gsyncapiGetNotificationShare(struct GSyncApi *pNotifier) { return notifyGetNotificationShare((struct Notifier *)(((unsigned char *)pNotifier) + __nvoc_rtti_GSyncApi_Notifier.offset)); } -static NV_STATUS __nvoc_thunk_RsResource_gsyncapiControlLookup(struct GSyncApi *pResource, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams, const struct NVOC_EXPORTED_METHOD_DEF **ppEntry) { - return resControlLookup((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_GSyncApi_RsResource.offset), pParams, ppEntry); -} - static NV_STATUS __nvoc_thunk_RsResource_gsyncapiMap(struct GSyncApi *pResource, struct CALL_CONTEXT *pCallContext, RS_CPU_MAP_PARAMS *pParams, RsCpuMapping *pCpuMapping) { return resMap((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_GSyncApi_RsResource.offset), pCallContext, pParams, pCpuMapping); } @@ -811,44 +819,48 @@ pThis->__gsyncapiCheckMemInterUnmap__ = &__nvoc_thunk_RmResource_gsyncapiCheckMemInterUnmap; + pThis->__gsyncapiMapTo__ = &__nvoc_thunk_RsResource_gsyncapiMapTo; + pThis->__gsyncapiAccessCallback__ = &__nvoc_thunk_RmResource_gsyncapiAccessCallback; - pThis->__gsyncapiGetMemInterMapParams__ = &__nvoc_thunk_RmResource_gsyncapiGetMemInterMapParams; + pThis->__gsyncapiSetNotificationShare__ = &__nvoc_thunk_Notifier_gsyncapiSetNotificationShare; - pThis->__gsyncapiGetMemoryMappingDescriptor__ = &__nvoc_thunk_RmResource_gsyncapiGetMemoryMappingDescriptor; + pThis->__gsyncapiGetRefCount__ = &__nvoc_thunk_RsResource_gsyncapiGetRefCount; - pThis->__gsyncapiSetNotificationShare__ = &__nvoc_thunk_Notifier_gsyncapiSetNotificationShare; + pThis->__gsyncapiAddAdditionalDependants__ = &__nvoc_thunk_RsResource_gsyncapiAddAdditionalDependants; - pThis->__gsyncapiControlFilter__ = &__nvoc_thunk_RsResource_gsyncapiControlFilter; + pThis->__gsyncapiControl_Prologue__ = &__nvoc_thunk_RmResource_gsyncapiControl_Prologue; - pThis->__gsyncapiGetRefCount__ = &__nvoc_thunk_RsResource_gsyncapiGetRefCount; + pThis->__gsyncapiUnmapFrom__ = &__nvoc_thunk_RsResource_gsyncapiUnmapFrom; - pThis->__gsyncapiUnregisterEvent__ = &__nvoc_thunk_Notifier_gsyncapiUnregisterEvent; + pThis->__gsyncapiControl_Epilogue__ = &__nvoc_thunk_RmResource_gsyncapiControl_Epilogue; + + pThis->__gsyncapiControlLookup__ = &__nvoc_thunk_RsResource_gsyncapiControlLookup; pThis->__gsyncapiUnmap__ = &__nvoc_thunk_RsResource_gsyncapiUnmap; - pThis->__gsyncapiCanCopy__ = &__nvoc_thunk_RsResource_gsyncapiCanCopy; + pThis->__gsyncapiGetMemInterMapParams__ = &__nvoc_thunk_RmResource_gsyncapiGetMemInterMapParams; - pThis->__gsyncapiControl_Prologue__ = &__nvoc_thunk_RmResource_gsyncapiControl_Prologue; + pThis->__gsyncapiGetMemoryMappingDescriptor__ = &__nvoc_thunk_RmResource_gsyncapiGetMemoryMappingDescriptor; - pThis->__gsyncapiMapTo__ = &__nvoc_thunk_RsResource_gsyncapiMapTo; + pThis->__gsyncapiControlFilter__ = &__nvoc_thunk_RsResource_gsyncapiControlFilter; - pThis->__gsyncapiAddAdditionalDependants__ = &__nvoc_thunk_RsResource_gsyncapiAddAdditionalDependants; + pThis->__gsyncapiUnregisterEvent__ = &__nvoc_thunk_Notifier_gsyncapiUnregisterEvent; - pThis->__gsyncapiPreDestruct__ = &__nvoc_thunk_RsResource_gsyncapiPreDestruct; + pThis->__gsyncapiControlSerialization_Prologue__ = &__nvoc_thunk_RmResource_gsyncapiControlSerialization_Prologue; - pThis->__gsyncapiUnmapFrom__ = &__nvoc_thunk_RsResource_gsyncapiUnmapFrom; + pThis->__gsyncapiCanCopy__ = &__nvoc_thunk_RsResource_gsyncapiCanCopy; + + pThis->__gsyncapiPreDestruct__ = &__nvoc_thunk_RsResource_gsyncapiPreDestruct; pThis->__gsyncapiIsDuplicate__ = &__nvoc_thunk_RsResource_gsyncapiIsDuplicate; - pThis->__gsyncapiGetNotificationListPtr__ = &__nvoc_thunk_Notifier_gsyncapiGetNotificationListPtr; + pThis->__gsyncapiControlSerialization_Epilogue__ = &__nvoc_thunk_RmResource_gsyncapiControlSerialization_Epilogue; - pThis->__gsyncapiControl_Epilogue__ = &__nvoc_thunk_RmResource_gsyncapiControl_Epilogue; + pThis->__gsyncapiGetNotificationListPtr__ = &__nvoc_thunk_Notifier_gsyncapiGetNotificationListPtr; pThis->__gsyncapiGetNotificationShare__ = &__nvoc_thunk_Notifier_gsyncapiGetNotificationShare; - pThis->__gsyncapiControlLookup__ = &__nvoc_thunk_RsResource_gsyncapiControlLookup; - pThis->__gsyncapiMap__ = &__nvoc_thunk_RsResource_gsyncapiMap; pThis->__gsyncapiGetOrAllocNotifShare__ = &__nvoc_thunk_Notifier_gsyncapiGetOrAllocNotifShare; @@ -878,13 +890,16 @@ Object *pParentObj; GSyncApi *pThis; - pThis = portMemAllocNonPaged(sizeof(GSyncApi)); - if (pThis == NULL) return NV_ERR_NO_MEMORY; + status = __nvoc_handleObjCreateMemAlloc(createFlags, sizeof(GSyncApi), (void**)&pThis, (void**)ppThis); + if (status != NV_OK) + return status; portMemSet(pThis, 0, sizeof(GSyncApi)); __nvoc_initRtti(staticCast(pThis, Dynamic), &__nvoc_class_def_GSyncApi); + pThis->__nvoc_base_RmResource.__nvoc_base_RsResource.__nvoc_base_Object.createFlags = createFlags; + if (pParent != NULL && !(createFlags & NVOC_OBJ_CREATE_FLAGS_PARENT_HALSPEC_ONLY)) { pParentObj = dynamicCast(pParent, Object); @@ -900,11 +915,17 @@ if (status != NV_OK) goto __nvoc_objCreate_GSyncApi_cleanup; *ppThis = pThis; + return NV_OK; __nvoc_objCreate_GSyncApi_cleanup: // do not call destructors here since the constructor already called them - portMemFree(pThis); + if (createFlags & NVOC_OBJ_CREATE_FLAGS_IN_PLACE_CONSTRUCT) + portMemSet(pThis, 0, sizeof(GSyncApi)); + else + portMemFree(pThis); + + // coverity[leaked_storage:FALSE] return status; } diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/generated/g_gsync_api_nvoc.h nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_gsync_api_nvoc.h --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/generated/g_gsync_api_nvoc.h 2023-10-25 20:27:00.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_gsync_api_nvoc.h 2024-03-05 22:18:17.000000000 +0000 @@ -91,25 +91,27 @@ NV_STATUS (*__gsyncapiCtrlCmdGsyncSetHouseSyncMode__)(struct GSyncApi *, NV30F1_CTRL_GSYNC_HOUSE_SYNC_MODE_PARAMS *); NvBool (*__gsyncapiShareCallback__)(struct GSyncApi *, struct RsClient *, struct RsResourceRef *, RS_SHARE_POLICY *); NV_STATUS (*__gsyncapiCheckMemInterUnmap__)(struct GSyncApi *, NvBool); + NV_STATUS (*__gsyncapiMapTo__)(struct GSyncApi *, RS_RES_MAP_TO_PARAMS *); NvBool (*__gsyncapiAccessCallback__)(struct GSyncApi *, struct RsClient *, void *, RsAccessRight); + void (*__gsyncapiSetNotificationShare__)(struct GSyncApi *, struct NotifShare *); + NvU32 (*__gsyncapiGetRefCount__)(struct GSyncApi *); + void (*__gsyncapiAddAdditionalDependants__)(struct RsClient *, struct GSyncApi *, RsResourceRef *); + NV_STATUS (*__gsyncapiControl_Prologue__)(struct GSyncApi *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); + NV_STATUS (*__gsyncapiUnmapFrom__)(struct GSyncApi *, RS_RES_UNMAP_FROM_PARAMS *); + void (*__gsyncapiControl_Epilogue__)(struct GSyncApi *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); + NV_STATUS (*__gsyncapiControlLookup__)(struct GSyncApi *, struct RS_RES_CONTROL_PARAMS_INTERNAL *, const struct NVOC_EXPORTED_METHOD_DEF **); + NV_STATUS (*__gsyncapiUnmap__)(struct GSyncApi *, struct CALL_CONTEXT *, RsCpuMapping *); NV_STATUS (*__gsyncapiGetMemInterMapParams__)(struct GSyncApi *, RMRES_MEM_INTER_MAP_PARAMS *); NV_STATUS (*__gsyncapiGetMemoryMappingDescriptor__)(struct GSyncApi *, struct MEMORY_DESCRIPTOR **); - void (*__gsyncapiSetNotificationShare__)(struct GSyncApi *, struct NotifShare *); NV_STATUS (*__gsyncapiControlFilter__)(struct GSyncApi *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); - NvU32 (*__gsyncapiGetRefCount__)(struct GSyncApi *); NV_STATUS (*__gsyncapiUnregisterEvent__)(struct GSyncApi *, NvHandle, NvHandle, NvHandle, NvHandle); - NV_STATUS (*__gsyncapiUnmap__)(struct GSyncApi *, struct CALL_CONTEXT *, RsCpuMapping *); + NV_STATUS (*__gsyncapiControlSerialization_Prologue__)(struct GSyncApi *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); NvBool (*__gsyncapiCanCopy__)(struct GSyncApi *); - NV_STATUS (*__gsyncapiControl_Prologue__)(struct GSyncApi *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); - NV_STATUS (*__gsyncapiMapTo__)(struct GSyncApi *, RS_RES_MAP_TO_PARAMS *); - void (*__gsyncapiAddAdditionalDependants__)(struct RsClient *, struct GSyncApi *, RsResourceRef *); void (*__gsyncapiPreDestruct__)(struct GSyncApi *); - NV_STATUS (*__gsyncapiUnmapFrom__)(struct GSyncApi *, RS_RES_UNMAP_FROM_PARAMS *); NV_STATUS (*__gsyncapiIsDuplicate__)(struct GSyncApi *, NvHandle, NvBool *); + void (*__gsyncapiControlSerialization_Epilogue__)(struct GSyncApi *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); PEVENTNOTIFICATION *(*__gsyncapiGetNotificationListPtr__)(struct GSyncApi *); - void (*__gsyncapiControl_Epilogue__)(struct GSyncApi *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); struct NotifShare *(*__gsyncapiGetNotificationShare__)(struct GSyncApi *); - NV_STATUS (*__gsyncapiControlLookup__)(struct GSyncApi *, struct RS_RES_CONTROL_PARAMS_INTERNAL *, const struct NVOC_EXPORTED_METHOD_DEF **); NV_STATUS (*__gsyncapiMap__)(struct GSyncApi *, struct CALL_CONTEXT *, RS_CPU_MAP_PARAMS *, RsCpuMapping *); NV_STATUS (*__gsyncapiGetOrAllocNotifShare__)(struct GSyncApi *, NvHandle, NvHandle, struct NotifShare **); NvU32 instance; @@ -180,25 +182,27 @@ #define gsyncapiCtrlCmdGsyncSetHouseSyncMode(pGsyncApi, pParams) gsyncapiCtrlCmdGsyncSetHouseSyncMode_DISPATCH(pGsyncApi, pParams) #define gsyncapiShareCallback(pResource, pInvokingClient, pParentRef, pSharePolicy) gsyncapiShareCallback_DISPATCH(pResource, pInvokingClient, pParentRef, pSharePolicy) #define gsyncapiCheckMemInterUnmap(pRmResource, bSubdeviceHandleProvided) gsyncapiCheckMemInterUnmap_DISPATCH(pRmResource, bSubdeviceHandleProvided) +#define gsyncapiMapTo(pResource, pParams) gsyncapiMapTo_DISPATCH(pResource, pParams) #define gsyncapiAccessCallback(pResource, pInvokingClient, pAllocParams, accessRight) gsyncapiAccessCallback_DISPATCH(pResource, pInvokingClient, pAllocParams, accessRight) +#define gsyncapiSetNotificationShare(pNotifier, pNotifShare) gsyncapiSetNotificationShare_DISPATCH(pNotifier, pNotifShare) +#define gsyncapiGetRefCount(pResource) gsyncapiGetRefCount_DISPATCH(pResource) +#define gsyncapiAddAdditionalDependants(pClient, pResource, pReference) gsyncapiAddAdditionalDependants_DISPATCH(pClient, pResource, pReference) +#define gsyncapiControl_Prologue(pResource, pCallContext, pParams) gsyncapiControl_Prologue_DISPATCH(pResource, pCallContext, pParams) +#define gsyncapiUnmapFrom(pResource, pParams) gsyncapiUnmapFrom_DISPATCH(pResource, pParams) +#define gsyncapiControl_Epilogue(pResource, pCallContext, pParams) gsyncapiControl_Epilogue_DISPATCH(pResource, pCallContext, pParams) +#define gsyncapiControlLookup(pResource, pParams, ppEntry) gsyncapiControlLookup_DISPATCH(pResource, pParams, ppEntry) +#define gsyncapiUnmap(pResource, pCallContext, pCpuMapping) gsyncapiUnmap_DISPATCH(pResource, pCallContext, pCpuMapping) #define gsyncapiGetMemInterMapParams(pRmResource, pParams) gsyncapiGetMemInterMapParams_DISPATCH(pRmResource, pParams) #define gsyncapiGetMemoryMappingDescriptor(pRmResource, ppMemDesc) gsyncapiGetMemoryMappingDescriptor_DISPATCH(pRmResource, ppMemDesc) -#define gsyncapiSetNotificationShare(pNotifier, pNotifShare) gsyncapiSetNotificationShare_DISPATCH(pNotifier, pNotifShare) #define gsyncapiControlFilter(pResource, pCallContext, pParams) gsyncapiControlFilter_DISPATCH(pResource, pCallContext, pParams) -#define gsyncapiGetRefCount(pResource) gsyncapiGetRefCount_DISPATCH(pResource) #define gsyncapiUnregisterEvent(pNotifier, hNotifierClient, hNotifierResource, hEventClient, hEvent) gsyncapiUnregisterEvent_DISPATCH(pNotifier, hNotifierClient, hNotifierResource, hEventClient, hEvent) -#define gsyncapiUnmap(pResource, pCallContext, pCpuMapping) gsyncapiUnmap_DISPATCH(pResource, pCallContext, pCpuMapping) +#define gsyncapiControlSerialization_Prologue(pResource, pCallContext, pParams) gsyncapiControlSerialization_Prologue_DISPATCH(pResource, pCallContext, pParams) #define gsyncapiCanCopy(pResource) gsyncapiCanCopy_DISPATCH(pResource) -#define gsyncapiControl_Prologue(pResource, pCallContext, pParams) gsyncapiControl_Prologue_DISPATCH(pResource, pCallContext, pParams) -#define gsyncapiMapTo(pResource, pParams) gsyncapiMapTo_DISPATCH(pResource, pParams) -#define gsyncapiAddAdditionalDependants(pClient, pResource, pReference) gsyncapiAddAdditionalDependants_DISPATCH(pClient, pResource, pReference) #define gsyncapiPreDestruct(pResource) gsyncapiPreDestruct_DISPATCH(pResource) -#define gsyncapiUnmapFrom(pResource, pParams) gsyncapiUnmapFrom_DISPATCH(pResource, pParams) #define gsyncapiIsDuplicate(pResource, hMemory, pDuplicate) gsyncapiIsDuplicate_DISPATCH(pResource, hMemory, pDuplicate) +#define gsyncapiControlSerialization_Epilogue(pResource, pCallContext, pParams) gsyncapiControlSerialization_Epilogue_DISPATCH(pResource, pCallContext, pParams) #define gsyncapiGetNotificationListPtr(pNotifier) gsyncapiGetNotificationListPtr_DISPATCH(pNotifier) -#define gsyncapiControl_Epilogue(pResource, pCallContext, pParams) gsyncapiControl_Epilogue_DISPATCH(pResource, pCallContext, pParams) #define gsyncapiGetNotificationShare(pNotifier) gsyncapiGetNotificationShare_DISPATCH(pNotifier) -#define gsyncapiControlLookup(pResource, pParams, ppEntry) gsyncapiControlLookup_DISPATCH(pResource, pParams, ppEntry) #define gsyncapiMap(pResource, pCallContext, pParams, pCpuMapping) gsyncapiMap_DISPATCH(pResource, pCallContext, pParams, pCpuMapping) #define gsyncapiGetOrAllocNotifShare(pNotifier, hNotifierClient, hNotifierResource, ppNotifShare) gsyncapiGetOrAllocNotifShare_DISPATCH(pNotifier, hNotifierClient, hNotifierResource, ppNotifShare) NV_STATUS gsyncapiControl_IMPL(struct GSyncApi *pGsyncApi, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams); @@ -389,82 +393,90 @@ return pRmResource->__gsyncapiCheckMemInterUnmap__(pRmResource, bSubdeviceHandleProvided); } +static inline NV_STATUS gsyncapiMapTo_DISPATCH(struct GSyncApi *pResource, RS_RES_MAP_TO_PARAMS *pParams) { + return pResource->__gsyncapiMapTo__(pResource, pParams); +} + static inline NvBool gsyncapiAccessCallback_DISPATCH(struct GSyncApi *pResource, struct RsClient *pInvokingClient, void *pAllocParams, RsAccessRight accessRight) { return pResource->__gsyncapiAccessCallback__(pResource, pInvokingClient, pAllocParams, accessRight); } -static inline NV_STATUS gsyncapiGetMemInterMapParams_DISPATCH(struct GSyncApi *pRmResource, RMRES_MEM_INTER_MAP_PARAMS *pParams) { - return pRmResource->__gsyncapiGetMemInterMapParams__(pRmResource, pParams); +static inline void gsyncapiSetNotificationShare_DISPATCH(struct GSyncApi *pNotifier, struct NotifShare *pNotifShare) { + pNotifier->__gsyncapiSetNotificationShare__(pNotifier, pNotifShare); } -static inline NV_STATUS gsyncapiGetMemoryMappingDescriptor_DISPATCH(struct GSyncApi *pRmResource, struct MEMORY_DESCRIPTOR **ppMemDesc) { - return pRmResource->__gsyncapiGetMemoryMappingDescriptor__(pRmResource, ppMemDesc); +static inline NvU32 gsyncapiGetRefCount_DISPATCH(struct GSyncApi *pResource) { + return pResource->__gsyncapiGetRefCount__(pResource); } -static inline void gsyncapiSetNotificationShare_DISPATCH(struct GSyncApi *pNotifier, struct NotifShare *pNotifShare) { - pNotifier->__gsyncapiSetNotificationShare__(pNotifier, pNotifShare); +static inline void gsyncapiAddAdditionalDependants_DISPATCH(struct RsClient *pClient, struct GSyncApi *pResource, RsResourceRef *pReference) { + pResource->__gsyncapiAddAdditionalDependants__(pClient, pResource, pReference); } -static inline NV_STATUS gsyncapiControlFilter_DISPATCH(struct GSyncApi *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { - return pResource->__gsyncapiControlFilter__(pResource, pCallContext, pParams); +static inline NV_STATUS gsyncapiControl_Prologue_DISPATCH(struct GSyncApi *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return pResource->__gsyncapiControl_Prologue__(pResource, pCallContext, pParams); } -static inline NvU32 gsyncapiGetRefCount_DISPATCH(struct GSyncApi *pResource) { - return pResource->__gsyncapiGetRefCount__(pResource); +static inline NV_STATUS gsyncapiUnmapFrom_DISPATCH(struct GSyncApi *pResource, RS_RES_UNMAP_FROM_PARAMS *pParams) { + return pResource->__gsyncapiUnmapFrom__(pResource, pParams); } -static inline NV_STATUS gsyncapiUnregisterEvent_DISPATCH(struct GSyncApi *pNotifier, NvHandle hNotifierClient, NvHandle hNotifierResource, NvHandle hEventClient, NvHandle hEvent) { - return pNotifier->__gsyncapiUnregisterEvent__(pNotifier, hNotifierClient, hNotifierResource, hEventClient, hEvent); +static inline void gsyncapiControl_Epilogue_DISPATCH(struct GSyncApi *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + pResource->__gsyncapiControl_Epilogue__(pResource, pCallContext, pParams); +} + +static inline NV_STATUS gsyncapiControlLookup_DISPATCH(struct GSyncApi *pResource, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams, const struct NVOC_EXPORTED_METHOD_DEF **ppEntry) { + return pResource->__gsyncapiControlLookup__(pResource, pParams, ppEntry); } static inline NV_STATUS gsyncapiUnmap_DISPATCH(struct GSyncApi *pResource, struct CALL_CONTEXT *pCallContext, RsCpuMapping *pCpuMapping) { return pResource->__gsyncapiUnmap__(pResource, pCallContext, pCpuMapping); } -static inline NvBool gsyncapiCanCopy_DISPATCH(struct GSyncApi *pResource) { - return pResource->__gsyncapiCanCopy__(pResource); +static inline NV_STATUS gsyncapiGetMemInterMapParams_DISPATCH(struct GSyncApi *pRmResource, RMRES_MEM_INTER_MAP_PARAMS *pParams) { + return pRmResource->__gsyncapiGetMemInterMapParams__(pRmResource, pParams); } -static inline NV_STATUS gsyncapiControl_Prologue_DISPATCH(struct GSyncApi *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { - return pResource->__gsyncapiControl_Prologue__(pResource, pCallContext, pParams); +static inline NV_STATUS gsyncapiGetMemoryMappingDescriptor_DISPATCH(struct GSyncApi *pRmResource, struct MEMORY_DESCRIPTOR **ppMemDesc) { + return pRmResource->__gsyncapiGetMemoryMappingDescriptor__(pRmResource, ppMemDesc); } -static inline NV_STATUS gsyncapiMapTo_DISPATCH(struct GSyncApi *pResource, RS_RES_MAP_TO_PARAMS *pParams) { - return pResource->__gsyncapiMapTo__(pResource, pParams); +static inline NV_STATUS gsyncapiControlFilter_DISPATCH(struct GSyncApi *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return pResource->__gsyncapiControlFilter__(pResource, pCallContext, pParams); } -static inline void gsyncapiAddAdditionalDependants_DISPATCH(struct RsClient *pClient, struct GSyncApi *pResource, RsResourceRef *pReference) { - pResource->__gsyncapiAddAdditionalDependants__(pClient, pResource, pReference); +static inline NV_STATUS gsyncapiUnregisterEvent_DISPATCH(struct GSyncApi *pNotifier, NvHandle hNotifierClient, NvHandle hNotifierResource, NvHandle hEventClient, NvHandle hEvent) { + return pNotifier->__gsyncapiUnregisterEvent__(pNotifier, hNotifierClient, hNotifierResource, hEventClient, hEvent); } -static inline void gsyncapiPreDestruct_DISPATCH(struct GSyncApi *pResource) { - pResource->__gsyncapiPreDestruct__(pResource); +static inline NV_STATUS gsyncapiControlSerialization_Prologue_DISPATCH(struct GSyncApi *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return pResource->__gsyncapiControlSerialization_Prologue__(pResource, pCallContext, pParams); } -static inline NV_STATUS gsyncapiUnmapFrom_DISPATCH(struct GSyncApi *pResource, RS_RES_UNMAP_FROM_PARAMS *pParams) { - return pResource->__gsyncapiUnmapFrom__(pResource, pParams); +static inline NvBool gsyncapiCanCopy_DISPATCH(struct GSyncApi *pResource) { + return pResource->__gsyncapiCanCopy__(pResource); +} + +static inline void gsyncapiPreDestruct_DISPATCH(struct GSyncApi *pResource) { + pResource->__gsyncapiPreDestruct__(pResource); } static inline NV_STATUS gsyncapiIsDuplicate_DISPATCH(struct GSyncApi *pResource, NvHandle hMemory, NvBool *pDuplicate) { return pResource->__gsyncapiIsDuplicate__(pResource, hMemory, pDuplicate); } -static inline PEVENTNOTIFICATION *gsyncapiGetNotificationListPtr_DISPATCH(struct GSyncApi *pNotifier) { - return pNotifier->__gsyncapiGetNotificationListPtr__(pNotifier); +static inline void gsyncapiControlSerialization_Epilogue_DISPATCH(struct GSyncApi *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + pResource->__gsyncapiControlSerialization_Epilogue__(pResource, pCallContext, pParams); } -static inline void gsyncapiControl_Epilogue_DISPATCH(struct GSyncApi *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { - pResource->__gsyncapiControl_Epilogue__(pResource, pCallContext, pParams); +static inline PEVENTNOTIFICATION *gsyncapiGetNotificationListPtr_DISPATCH(struct GSyncApi *pNotifier) { + return pNotifier->__gsyncapiGetNotificationListPtr__(pNotifier); } static inline struct NotifShare *gsyncapiGetNotificationShare_DISPATCH(struct GSyncApi *pNotifier) { return pNotifier->__gsyncapiGetNotificationShare__(pNotifier); } -static inline NV_STATUS gsyncapiControlLookup_DISPATCH(struct GSyncApi *pResource, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams, const struct NVOC_EXPORTED_METHOD_DEF **ppEntry) { - return pResource->__gsyncapiControlLookup__(pResource, pParams, ppEntry); -} - static inline NV_STATUS gsyncapiMap_DISPATCH(struct GSyncApi *pResource, struct CALL_CONTEXT *pCallContext, RS_CPU_MAP_PARAMS *pParams, RsCpuMapping *pCpuMapping) { return pResource->__gsyncapiMap__(pResource, pCallContext, pParams, pCpuMapping); } diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/generated/g_gsync_nvoc.c nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_gsync_nvoc.c --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/generated/g_gsync_nvoc.c 2023-10-25 20:27:00.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_gsync_nvoc.c 2024-03-05 22:18:17.000000000 +0000 @@ -114,13 +114,16 @@ Object *pParentObj; OBJGSYNCMGR *pThis; - pThis = portMemAllocNonPaged(sizeof(OBJGSYNCMGR)); - if (pThis == NULL) return NV_ERR_NO_MEMORY; + status = __nvoc_handleObjCreateMemAlloc(createFlags, sizeof(OBJGSYNCMGR), (void**)&pThis, (void**)ppThis); + if (status != NV_OK) + return status; portMemSet(pThis, 0, sizeof(OBJGSYNCMGR)); __nvoc_initRtti(staticCast(pThis, Dynamic), &__nvoc_class_def_OBJGSYNCMGR); + pThis->__nvoc_base_Object.createFlags = createFlags; + if (pParent != NULL && !(createFlags & NVOC_OBJ_CREATE_FLAGS_PARENT_HALSPEC_ONLY)) { pParentObj = dynamicCast(pParent, Object); @@ -136,11 +139,17 @@ if (status != NV_OK) goto __nvoc_objCreate_OBJGSYNCMGR_cleanup; *ppThis = pThis; + return NV_OK; __nvoc_objCreate_OBJGSYNCMGR_cleanup: // do not call destructors here since the constructor already called them - portMemFree(pThis); + if (createFlags & NVOC_OBJ_CREATE_FLAGS_IN_PLACE_CONSTRUCT) + portMemSet(pThis, 0, sizeof(OBJGSYNCMGR)); + else + portMemFree(pThis); + + // coverity[leaked_storage:FALSE] return status; } diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/generated/g_gsync_nvoc.h nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_gsync_nvoc.h --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/generated/g_gsync_nvoc.h 2023-10-25 20:27:00.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_gsync_nvoc.h 2024-03-05 22:18:17.000000000 +0000 @@ -141,6 +141,8 @@ typedef NV_STATUS GsyncConfigFlashGsync (struct OBJGPU *, PDACEXTERNALDEVICE, NvU32); typedef NV_STATUS GsyncGetHouseSyncMode (struct OBJGPU *, PDACEXTERNALDEVICE, NvU8*); typedef NV_STATUS GsyncSetHouseSyncMode (struct OBJGPU *, PDACEXTERNALDEVICE, NvU8); +typedef NV_STATUS GsyncGetMulDiv (struct OBJGPU *, DACEXTERNALDEVICE *, NV30F1_CTRL_GSYNC_MULTIPLY_DIVIDE_SETTINGS *); +typedef NV_STATUS GsyncSetMulDiv (struct OBJGPU *, DACEXTERNALDEVICE *, NV30F1_CTRL_GSYNC_MULTIPLY_DIVIDE_SETTINGS *); typedef struct GSYNC_HAL_IFACES { @@ -176,6 +178,8 @@ GsyncConfigFlashGsync *gsyncConfigFlashGsync; GsyncGetHouseSyncMode *gsyncGetHouseSyncMode; GsyncSetHouseSyncMode *gsyncSetHouseSyncMode; + GsyncGetMulDiv *gsyncGetMulDiv; + GsyncSetMulDiv *gsyncSetMulDiv; } GSYNC_HAL_IFACES; diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/generated/g_hal.h nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_hal.h --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/generated/g_hal.h 2023-10-25 20:19:28.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_hal.h 2024-03-05 22:11:19.000000000 +0000 @@ -38,7 +38,6 @@ // generic form of Head_iGrp_ipVersions_getInfo typedef -typedef NV_STATUS IGrp_ipVersions_getInfo(IGRP_IP_VERSIONS_TABLE_INFO *); typedef void IGrp_ipVersions_install(IGRP_IP_VERSIONS_TABLE_INFO *); typedef NV_STATUS IGrp_ipVersions_wrapup(IGRP_IP_VERSIONS_TABLE_INFO *); diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/generated/g_hal_mgr_nvoc.c nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_hal_mgr_nvoc.c --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/generated/g_hal_mgr_nvoc.c 2023-10-25 20:27:00.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_hal_mgr_nvoc.c 2024-03-05 22:18:17.000000000 +0000 @@ -114,13 +114,16 @@ Object *pParentObj; OBJHALMGR *pThis; - pThis = portMemAllocNonPaged(sizeof(OBJHALMGR)); - if (pThis == NULL) return NV_ERR_NO_MEMORY; + status = __nvoc_handleObjCreateMemAlloc(createFlags, sizeof(OBJHALMGR), (void**)&pThis, (void**)ppThis); + if (status != NV_OK) + return status; portMemSet(pThis, 0, sizeof(OBJHALMGR)); __nvoc_initRtti(staticCast(pThis, Dynamic), &__nvoc_class_def_OBJHALMGR); + pThis->__nvoc_base_Object.createFlags = createFlags; + if (pParent != NULL && !(createFlags & NVOC_OBJ_CREATE_FLAGS_PARENT_HALSPEC_ONLY)) { pParentObj = dynamicCast(pParent, Object); @@ -136,11 +139,17 @@ if (status != NV_OK) goto __nvoc_objCreate_OBJHALMGR_cleanup; *ppThis = pThis; + return NV_OK; __nvoc_objCreate_OBJHALMGR_cleanup: // do not call destructors here since the constructor already called them - portMemFree(pThis); + if (createFlags & NVOC_OBJ_CREATE_FLAGS_IN_PLACE_CONSTRUCT) + portMemSet(pThis, 0, sizeof(OBJHALMGR)); + else + portMemFree(pThis); + + // coverity[leaked_storage:FALSE] return status; } diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/generated/g_hal_nvoc.c nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_hal_nvoc.c --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/generated/g_hal_nvoc.c 2023-10-25 20:27:01.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_hal_nvoc.c 2024-03-05 22:18:18.000000000 +0000 @@ -108,13 +108,16 @@ Object *pParentObj; OBJHAL *pThis; - pThis = portMemAllocNonPaged(sizeof(OBJHAL)); - if (pThis == NULL) return NV_ERR_NO_MEMORY; + status = __nvoc_handleObjCreateMemAlloc(createFlags, sizeof(OBJHAL), (void**)&pThis, (void**)ppThis); + if (status != NV_OK) + return status; portMemSet(pThis, 0, sizeof(OBJHAL)); __nvoc_initRtti(staticCast(pThis, Dynamic), &__nvoc_class_def_OBJHAL); + pThis->__nvoc_base_Object.createFlags = createFlags; + if (pParent != NULL && !(createFlags & NVOC_OBJ_CREATE_FLAGS_PARENT_HALSPEC_ONLY)) { pParentObj = dynamicCast(pParent, Object); @@ -130,11 +133,17 @@ if (status != NV_OK) goto __nvoc_objCreate_OBJHAL_cleanup; *ppThis = pThis; + return NV_OK; __nvoc_objCreate_OBJHAL_cleanup: // do not call destructors here since the constructor already called them - portMemFree(pThis); + if (createFlags & NVOC_OBJ_CREATE_FLAGS_IN_PLACE_CONSTRUCT) + portMemSet(pThis, 0, sizeof(OBJHAL)); + else + portMemFree(pThis); + + // coverity[leaked_storage:FALSE] return status; } diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/generated/g_hal_nvoc.h nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_hal_nvoc.h --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/generated/g_hal_nvoc.h 2023-10-25 20:27:01.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_hal_nvoc.h 2024-03-05 22:18:18.000000000 +0000 @@ -133,12 +133,6 @@ #undef PRIVATE_FIELD -//-------------------------------------------------------------------- -// RM routines. -//-------------------------------------------------------------------- - -NV_STATUS ipVersionsSetupHal(struct OBJGPU *, void *pDynamic, IGrp_ipVersions_getInfo getInfoFn); - #endif // _OBJHAL_H_ #ifdef __cplusplus diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/generated/g_hal_stubs.h nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_hal_stubs.h --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/generated/g_hal_stubs.h 2023-10-25 20:19:28.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_hal_stubs.h 2024-03-05 22:11:20.000000000 +0000 @@ -700,6 +700,15 @@ return NV_VGPU_MSG_RESULT_RPC_UNKNOWN_FUNCTION; } +// RPC:hal:ECC_NOTIFIER_WRITE_ACK - TU10X, GA100, GA102, GA103, GA104, GA106, GA107, AD102, AD103, AD104, AD106, AD107, GH10X +NV_STATUS rpcEccNotifierWriteAck_STUB( + POBJGPU pGpu, + POBJRPC pRpc +) +{ + return NV_VGPU_MSG_RESULT_RPC_UNKNOWN_FUNCTION; +} + // RPC:hal:ALLOC_MEMORY - TU10X, GA100, GA102, GA103, GA104, GA106, GA107, AD102, AD103, AD104, AD106, AD107, GH10X NV_STATUS rpcAllocMemory_STUB( POBJGPU pGpu, @@ -900,6 +909,17 @@ return NV_VGPU_MSG_RESULT_RPC_UNKNOWN_FUNCTION; } +// RPCSTRUCTURECOPY:hal:NV2080_CTRL_CMD_BUS_GET_C2C_INFO_PARAMS - RPCSTRUCTURECOPY disabled +NV_STATUS deserialize_NV2080_CTRL_CMD_BUS_GET_C2C_INFO_PARAMS_STUB( + NV2080_CTRL_CMD_BUS_GET_C2C_INFO_PARAMS *data, + NvU8 *stream, + NvU32 streamSize, + NvU32 *offset +) +{ + return NV_OK; +} + // RPCSTRUCTURECOPY:hal:NV2080_CTRL_CE_GET_ALL_CAPS_PARAMS - RPCSTRUCTURECOPY disabled NV_STATUS deserialize_NV2080_CTRL_CE_GET_ALL_CAPS_PARAMS_STUB( NV2080_CTRL_CE_GET_ALL_CAPS_PARAMS *data, diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/generated/g_hda_codec_api_nvoc.c nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_hda_codec_api_nvoc.c --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/generated/g_hda_codec_api_nvoc.c 2023-10-25 20:27:01.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_hda_codec_api_nvoc.c 2024-03-05 22:18:18.000000000 +0000 @@ -97,84 +97,92 @@ return gpuresShareCallback((struct GpuResource *)(((unsigned char *)pGpuResource) + __nvoc_rtti_Hdacodec_GpuResource.offset), pInvokingClient, pParentRef, pSharePolicy); } -static NV_STATUS __nvoc_thunk_GpuResource_hdacodecControl(struct Hdacodec *pGpuResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { - return gpuresControl((struct GpuResource *)(((unsigned char *)pGpuResource) + __nvoc_rtti_Hdacodec_GpuResource.offset), pCallContext, pParams); +static NV_STATUS __nvoc_thunk_RmResource_hdacodecCheckMemInterUnmap(struct Hdacodec *pRmResource, NvBool bSubdeviceHandleProvided) { + return rmresCheckMemInterUnmap((struct RmResource *)(((unsigned char *)pRmResource) + __nvoc_rtti_Hdacodec_RmResource.offset), bSubdeviceHandleProvided); } -static NV_STATUS __nvoc_thunk_GpuResource_hdacodecUnmap(struct Hdacodec *pGpuResource, struct CALL_CONTEXT *pCallContext, struct RsCpuMapping *pCpuMapping) { - return gpuresUnmap((struct GpuResource *)(((unsigned char *)pGpuResource) + __nvoc_rtti_Hdacodec_GpuResource.offset), pCallContext, pCpuMapping); +static NV_STATUS __nvoc_thunk_RsResource_hdacodecMapTo(struct Hdacodec *pResource, RS_RES_MAP_TO_PARAMS *pParams) { + return resMapTo((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_Hdacodec_RsResource.offset), pParams); } -static NV_STATUS __nvoc_thunk_RmResource_hdacodecGetMemInterMapParams(struct Hdacodec *pRmResource, RMRES_MEM_INTER_MAP_PARAMS *pParams) { - return rmresGetMemInterMapParams((struct RmResource *)(((unsigned char *)pRmResource) + __nvoc_rtti_Hdacodec_RmResource.offset), pParams); +static NV_STATUS __nvoc_thunk_GpuResource_hdacodecGetMapAddrSpace(struct Hdacodec *pGpuResource, struct CALL_CONTEXT *pCallContext, NvU32 mapFlags, NV_ADDRESS_SPACE *pAddrSpace) { + return gpuresGetMapAddrSpace((struct GpuResource *)(((unsigned char *)pGpuResource) + __nvoc_rtti_Hdacodec_GpuResource.offset), pCallContext, mapFlags, pAddrSpace); } -static NV_STATUS __nvoc_thunk_RmResource_hdacodecGetMemoryMappingDescriptor(struct Hdacodec *pRmResource, struct MEMORY_DESCRIPTOR **ppMemDesc) { - return rmresGetMemoryMappingDescriptor((struct RmResource *)(((unsigned char *)pRmResource) + __nvoc_rtti_Hdacodec_RmResource.offset), ppMemDesc); +static NvU32 __nvoc_thunk_RsResource_hdacodecGetRefCount(struct Hdacodec *pResource) { + return resGetRefCount((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_Hdacodec_RsResource.offset)); } -static NV_STATUS __nvoc_thunk_GpuResource_hdacodecGetMapAddrSpace(struct Hdacodec *pGpuResource, struct CALL_CONTEXT *pCallContext, NvU32 mapFlags, NV_ADDRESS_SPACE *pAddrSpace) { - return gpuresGetMapAddrSpace((struct GpuResource *)(((unsigned char *)pGpuResource) + __nvoc_rtti_Hdacodec_GpuResource.offset), pCallContext, mapFlags, pAddrSpace); +static void __nvoc_thunk_RsResource_hdacodecAddAdditionalDependants(struct RsClient *pClient, struct Hdacodec *pResource, RsResourceRef *pReference) { + resAddAdditionalDependants(pClient, (struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_Hdacodec_RsResource.offset), pReference); } -static NvHandle __nvoc_thunk_GpuResource_hdacodecGetInternalObjectHandle(struct Hdacodec *pGpuResource) { - return gpuresGetInternalObjectHandle((struct GpuResource *)(((unsigned char *)pGpuResource) + __nvoc_rtti_Hdacodec_GpuResource.offset)); +static NV_STATUS __nvoc_thunk_RmResource_hdacodecControl_Prologue(struct Hdacodec *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return rmresControl_Prologue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_Hdacodec_RmResource.offset), pCallContext, pParams); } -static NV_STATUS __nvoc_thunk_RsResource_hdacodecControlFilter(struct Hdacodec *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { - return resControlFilter((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_Hdacodec_RsResource.offset), pCallContext, pParams); +static NV_STATUS __nvoc_thunk_GpuResource_hdacodecGetRegBaseOffsetAndSize(struct Hdacodec *pGpuResource, struct OBJGPU *pGpu, NvU32 *pOffset, NvU32 *pSize) { + return gpuresGetRegBaseOffsetAndSize((struct GpuResource *)(((unsigned char *)pGpuResource) + __nvoc_rtti_Hdacodec_GpuResource.offset), pGpu, pOffset, pSize); } -static void __nvoc_thunk_RsResource_hdacodecAddAdditionalDependants(struct RsClient *pClient, struct Hdacodec *pResource, RsResourceRef *pReference) { - resAddAdditionalDependants(pClient, (struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_Hdacodec_RsResource.offset), pReference); +static NV_STATUS __nvoc_thunk_GpuResource_hdacodecInternalControlForward(struct Hdacodec *pGpuResource, NvU32 command, void *pParams, NvU32 size) { + return gpuresInternalControlForward((struct GpuResource *)(((unsigned char *)pGpuResource) + __nvoc_rtti_Hdacodec_GpuResource.offset), command, pParams, size); } -static NvU32 __nvoc_thunk_RsResource_hdacodecGetRefCount(struct Hdacodec *pResource) { - return resGetRefCount((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_Hdacodec_RsResource.offset)); +static NV_STATUS __nvoc_thunk_RsResource_hdacodecUnmapFrom(struct Hdacodec *pResource, RS_RES_UNMAP_FROM_PARAMS *pParams) { + return resUnmapFrom((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_Hdacodec_RsResource.offset), pParams); } -static NV_STATUS __nvoc_thunk_RmResource_hdacodecCheckMemInterUnmap(struct Hdacodec *pRmResource, NvBool bSubdeviceHandleProvided) { - return rmresCheckMemInterUnmap((struct RmResource *)(((unsigned char *)pRmResource) + __nvoc_rtti_Hdacodec_RmResource.offset), bSubdeviceHandleProvided); +static void __nvoc_thunk_RmResource_hdacodecControl_Epilogue(struct Hdacodec *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + rmresControl_Epilogue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_Hdacodec_RmResource.offset), pCallContext, pParams); } -static NV_STATUS __nvoc_thunk_RsResource_hdacodecMapTo(struct Hdacodec *pResource, RS_RES_MAP_TO_PARAMS *pParams) { - return resMapTo((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_Hdacodec_RsResource.offset), pParams); +static NV_STATUS __nvoc_thunk_RsResource_hdacodecControlLookup(struct Hdacodec *pResource, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams, const struct NVOC_EXPORTED_METHOD_DEF **ppEntry) { + return resControlLookup((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_Hdacodec_RsResource.offset), pParams, ppEntry); } -static NV_STATUS __nvoc_thunk_RmResource_hdacodecControl_Prologue(struct Hdacodec *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { - return rmresControl_Prologue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_Hdacodec_RmResource.offset), pCallContext, pParams); +static NvHandle __nvoc_thunk_GpuResource_hdacodecGetInternalObjectHandle(struct Hdacodec *pGpuResource) { + return gpuresGetInternalObjectHandle((struct GpuResource *)(((unsigned char *)pGpuResource) + __nvoc_rtti_Hdacodec_GpuResource.offset)); } -static NV_STATUS __nvoc_thunk_GpuResource_hdacodecGetRegBaseOffsetAndSize(struct Hdacodec *pGpuResource, struct OBJGPU *pGpu, NvU32 *pOffset, NvU32 *pSize) { - return gpuresGetRegBaseOffsetAndSize((struct GpuResource *)(((unsigned char *)pGpuResource) + __nvoc_rtti_Hdacodec_GpuResource.offset), pGpu, pOffset, pSize); +static NV_STATUS __nvoc_thunk_GpuResource_hdacodecControl(struct Hdacodec *pGpuResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return gpuresControl((struct GpuResource *)(((unsigned char *)pGpuResource) + __nvoc_rtti_Hdacodec_GpuResource.offset), pCallContext, pParams); } -static NvBool __nvoc_thunk_RsResource_hdacodecCanCopy(struct Hdacodec *pResource) { - return resCanCopy((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_Hdacodec_RsResource.offset)); +static NV_STATUS __nvoc_thunk_GpuResource_hdacodecUnmap(struct Hdacodec *pGpuResource, struct CALL_CONTEXT *pCallContext, struct RsCpuMapping *pCpuMapping) { + return gpuresUnmap((struct GpuResource *)(((unsigned char *)pGpuResource) + __nvoc_rtti_Hdacodec_GpuResource.offset), pCallContext, pCpuMapping); } -static NV_STATUS __nvoc_thunk_GpuResource_hdacodecInternalControlForward(struct Hdacodec *pGpuResource, NvU32 command, void *pParams, NvU32 size) { - return gpuresInternalControlForward((struct GpuResource *)(((unsigned char *)pGpuResource) + __nvoc_rtti_Hdacodec_GpuResource.offset), command, pParams, size); +static NV_STATUS __nvoc_thunk_RmResource_hdacodecGetMemInterMapParams(struct Hdacodec *pRmResource, RMRES_MEM_INTER_MAP_PARAMS *pParams) { + return rmresGetMemInterMapParams((struct RmResource *)(((unsigned char *)pRmResource) + __nvoc_rtti_Hdacodec_RmResource.offset), pParams); } -static void __nvoc_thunk_RsResource_hdacodecPreDestruct(struct Hdacodec *pResource) { - resPreDestruct((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_Hdacodec_RsResource.offset)); +static NV_STATUS __nvoc_thunk_RmResource_hdacodecGetMemoryMappingDescriptor(struct Hdacodec *pRmResource, struct MEMORY_DESCRIPTOR **ppMemDesc) { + return rmresGetMemoryMappingDescriptor((struct RmResource *)(((unsigned char *)pRmResource) + __nvoc_rtti_Hdacodec_RmResource.offset), ppMemDesc); } -static NV_STATUS __nvoc_thunk_RsResource_hdacodecUnmapFrom(struct Hdacodec *pResource, RS_RES_UNMAP_FROM_PARAMS *pParams) { - return resUnmapFrom((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_Hdacodec_RsResource.offset), pParams); +static NV_STATUS __nvoc_thunk_RsResource_hdacodecControlFilter(struct Hdacodec *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return resControlFilter((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_Hdacodec_RsResource.offset), pCallContext, pParams); } -static NV_STATUS __nvoc_thunk_RsResource_hdacodecIsDuplicate(struct Hdacodec *pResource, NvHandle hMemory, NvBool *pDuplicate) { - return resIsDuplicate((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_Hdacodec_RsResource.offset), hMemory, pDuplicate); +static NV_STATUS __nvoc_thunk_RmResource_hdacodecControlSerialization_Prologue(struct Hdacodec *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return rmresControlSerialization_Prologue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_Hdacodec_RmResource.offset), pCallContext, pParams); } -static void __nvoc_thunk_RmResource_hdacodecControl_Epilogue(struct Hdacodec *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { - rmresControl_Epilogue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_Hdacodec_RmResource.offset), pCallContext, pParams); +static NvBool __nvoc_thunk_RsResource_hdacodecCanCopy(struct Hdacodec *pResource) { + return resCanCopy((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_Hdacodec_RsResource.offset)); } -static NV_STATUS __nvoc_thunk_RsResource_hdacodecControlLookup(struct Hdacodec *pResource, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams, const struct NVOC_EXPORTED_METHOD_DEF **ppEntry) { - return resControlLookup((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_Hdacodec_RsResource.offset), pParams, ppEntry); +static void __nvoc_thunk_RsResource_hdacodecPreDestruct(struct Hdacodec *pResource) { + resPreDestruct((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_Hdacodec_RsResource.offset)); +} + +static NV_STATUS __nvoc_thunk_RsResource_hdacodecIsDuplicate(struct Hdacodec *pResource, NvHandle hMemory, NvBool *pDuplicate) { + return resIsDuplicate((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_Hdacodec_RsResource.offset), hMemory, pDuplicate); +} + +static void __nvoc_thunk_RmResource_hdacodecControlSerialization_Epilogue(struct Hdacodec *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + rmresControlSerialization_Epilogue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_Hdacodec_RmResource.offset), pCallContext, pParams); } static NV_STATUS __nvoc_thunk_GpuResource_hdacodecMap(struct Hdacodec *pGpuResource, struct CALL_CONTEXT *pCallContext, struct RS_CPU_MAP_PARAMS *pParams, struct RsCpuMapping *pCpuMapping) { @@ -225,45 +233,49 @@ pThis->__hdacodecShareCallback__ = &__nvoc_thunk_GpuResource_hdacodecShareCallback; - pThis->__hdacodecControl__ = &__nvoc_thunk_GpuResource_hdacodecControl; + pThis->__hdacodecCheckMemInterUnmap__ = &__nvoc_thunk_RmResource_hdacodecCheckMemInterUnmap; - pThis->__hdacodecUnmap__ = &__nvoc_thunk_GpuResource_hdacodecUnmap; + pThis->__hdacodecMapTo__ = &__nvoc_thunk_RsResource_hdacodecMapTo; - pThis->__hdacodecGetMemInterMapParams__ = &__nvoc_thunk_RmResource_hdacodecGetMemInterMapParams; + pThis->__hdacodecGetMapAddrSpace__ = &__nvoc_thunk_GpuResource_hdacodecGetMapAddrSpace; - pThis->__hdacodecGetMemoryMappingDescriptor__ = &__nvoc_thunk_RmResource_hdacodecGetMemoryMappingDescriptor; + pThis->__hdacodecGetRefCount__ = &__nvoc_thunk_RsResource_hdacodecGetRefCount; - pThis->__hdacodecGetMapAddrSpace__ = &__nvoc_thunk_GpuResource_hdacodecGetMapAddrSpace; + pThis->__hdacodecAddAdditionalDependants__ = &__nvoc_thunk_RsResource_hdacodecAddAdditionalDependants; - pThis->__hdacodecGetInternalObjectHandle__ = &__nvoc_thunk_GpuResource_hdacodecGetInternalObjectHandle; + pThis->__hdacodecControl_Prologue__ = &__nvoc_thunk_RmResource_hdacodecControl_Prologue; - pThis->__hdacodecControlFilter__ = &__nvoc_thunk_RsResource_hdacodecControlFilter; + pThis->__hdacodecGetRegBaseOffsetAndSize__ = &__nvoc_thunk_GpuResource_hdacodecGetRegBaseOffsetAndSize; - pThis->__hdacodecAddAdditionalDependants__ = &__nvoc_thunk_RsResource_hdacodecAddAdditionalDependants; + pThis->__hdacodecInternalControlForward__ = &__nvoc_thunk_GpuResource_hdacodecInternalControlForward; - pThis->__hdacodecGetRefCount__ = &__nvoc_thunk_RsResource_hdacodecGetRefCount; + pThis->__hdacodecUnmapFrom__ = &__nvoc_thunk_RsResource_hdacodecUnmapFrom; - pThis->__hdacodecCheckMemInterUnmap__ = &__nvoc_thunk_RmResource_hdacodecCheckMemInterUnmap; + pThis->__hdacodecControl_Epilogue__ = &__nvoc_thunk_RmResource_hdacodecControl_Epilogue; - pThis->__hdacodecMapTo__ = &__nvoc_thunk_RsResource_hdacodecMapTo; + pThis->__hdacodecControlLookup__ = &__nvoc_thunk_RsResource_hdacodecControlLookup; - pThis->__hdacodecControl_Prologue__ = &__nvoc_thunk_RmResource_hdacodecControl_Prologue; + pThis->__hdacodecGetInternalObjectHandle__ = &__nvoc_thunk_GpuResource_hdacodecGetInternalObjectHandle; - pThis->__hdacodecGetRegBaseOffsetAndSize__ = &__nvoc_thunk_GpuResource_hdacodecGetRegBaseOffsetAndSize; + pThis->__hdacodecControl__ = &__nvoc_thunk_GpuResource_hdacodecControl; - pThis->__hdacodecCanCopy__ = &__nvoc_thunk_RsResource_hdacodecCanCopy; + pThis->__hdacodecUnmap__ = &__nvoc_thunk_GpuResource_hdacodecUnmap; - pThis->__hdacodecInternalControlForward__ = &__nvoc_thunk_GpuResource_hdacodecInternalControlForward; + pThis->__hdacodecGetMemInterMapParams__ = &__nvoc_thunk_RmResource_hdacodecGetMemInterMapParams; - pThis->__hdacodecPreDestruct__ = &__nvoc_thunk_RsResource_hdacodecPreDestruct; + pThis->__hdacodecGetMemoryMappingDescriptor__ = &__nvoc_thunk_RmResource_hdacodecGetMemoryMappingDescriptor; - pThis->__hdacodecUnmapFrom__ = &__nvoc_thunk_RsResource_hdacodecUnmapFrom; + pThis->__hdacodecControlFilter__ = &__nvoc_thunk_RsResource_hdacodecControlFilter; - pThis->__hdacodecIsDuplicate__ = &__nvoc_thunk_RsResource_hdacodecIsDuplicate; + pThis->__hdacodecControlSerialization_Prologue__ = &__nvoc_thunk_RmResource_hdacodecControlSerialization_Prologue; - pThis->__hdacodecControl_Epilogue__ = &__nvoc_thunk_RmResource_hdacodecControl_Epilogue; + pThis->__hdacodecCanCopy__ = &__nvoc_thunk_RsResource_hdacodecCanCopy; - pThis->__hdacodecControlLookup__ = &__nvoc_thunk_RsResource_hdacodecControlLookup; + pThis->__hdacodecPreDestruct__ = &__nvoc_thunk_RsResource_hdacodecPreDestruct; + + pThis->__hdacodecIsDuplicate__ = &__nvoc_thunk_RsResource_hdacodecIsDuplicate; + + pThis->__hdacodecControlSerialization_Epilogue__ = &__nvoc_thunk_RmResource_hdacodecControlSerialization_Epilogue; pThis->__hdacodecMap__ = &__nvoc_thunk_GpuResource_hdacodecMap; @@ -291,13 +303,16 @@ Object *pParentObj; Hdacodec *pThis; - pThis = portMemAllocNonPaged(sizeof(Hdacodec)); - if (pThis == NULL) return NV_ERR_NO_MEMORY; + status = __nvoc_handleObjCreateMemAlloc(createFlags, sizeof(Hdacodec), (void**)&pThis, (void**)ppThis); + if (status != NV_OK) + return status; portMemSet(pThis, 0, sizeof(Hdacodec)); __nvoc_initRtti(staticCast(pThis, Dynamic), &__nvoc_class_def_Hdacodec); + pThis->__nvoc_base_GpuResource.__nvoc_base_RmResource.__nvoc_base_RsResource.__nvoc_base_Object.createFlags = createFlags; + if (pParent != NULL && !(createFlags & NVOC_OBJ_CREATE_FLAGS_PARENT_HALSPEC_ONLY)) { pParentObj = dynamicCast(pParent, Object); @@ -313,11 +328,17 @@ if (status != NV_OK) goto __nvoc_objCreate_Hdacodec_cleanup; *ppThis = pThis; + return NV_OK; __nvoc_objCreate_Hdacodec_cleanup: // do not call destructors here since the constructor already called them - portMemFree(pThis); + if (createFlags & NVOC_OBJ_CREATE_FLAGS_IN_PLACE_CONSTRUCT) + portMemSet(pThis, 0, sizeof(Hdacodec)); + else + portMemFree(pThis); + + // coverity[leaked_storage:FALSE] return status; } diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/generated/g_hda_codec_api_nvoc.h nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_hda_codec_api_nvoc.h --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/generated/g_hda_codec_api_nvoc.h 2023-10-25 20:27:01.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_hda_codec_api_nvoc.h 2024-03-05 22:18:18.000000000 +0000 @@ -55,26 +55,28 @@ struct GpuResource *__nvoc_pbase_GpuResource; struct Hdacodec *__nvoc_pbase_Hdacodec; NvBool (*__hdacodecShareCallback__)(struct Hdacodec *, struct RsClient *, struct RsResourceRef *, RS_SHARE_POLICY *); - NV_STATUS (*__hdacodecControl__)(struct Hdacodec *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); - NV_STATUS (*__hdacodecUnmap__)(struct Hdacodec *, struct CALL_CONTEXT *, struct RsCpuMapping *); - NV_STATUS (*__hdacodecGetMemInterMapParams__)(struct Hdacodec *, RMRES_MEM_INTER_MAP_PARAMS *); - NV_STATUS (*__hdacodecGetMemoryMappingDescriptor__)(struct Hdacodec *, struct MEMORY_DESCRIPTOR **); - NV_STATUS (*__hdacodecGetMapAddrSpace__)(struct Hdacodec *, struct CALL_CONTEXT *, NvU32, NV_ADDRESS_SPACE *); - NvHandle (*__hdacodecGetInternalObjectHandle__)(struct Hdacodec *); - NV_STATUS (*__hdacodecControlFilter__)(struct Hdacodec *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); - void (*__hdacodecAddAdditionalDependants__)(struct RsClient *, struct Hdacodec *, RsResourceRef *); - NvU32 (*__hdacodecGetRefCount__)(struct Hdacodec *); NV_STATUS (*__hdacodecCheckMemInterUnmap__)(struct Hdacodec *, NvBool); NV_STATUS (*__hdacodecMapTo__)(struct Hdacodec *, RS_RES_MAP_TO_PARAMS *); + NV_STATUS (*__hdacodecGetMapAddrSpace__)(struct Hdacodec *, struct CALL_CONTEXT *, NvU32, NV_ADDRESS_SPACE *); + NvU32 (*__hdacodecGetRefCount__)(struct Hdacodec *); + void (*__hdacodecAddAdditionalDependants__)(struct RsClient *, struct Hdacodec *, RsResourceRef *); NV_STATUS (*__hdacodecControl_Prologue__)(struct Hdacodec *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); NV_STATUS (*__hdacodecGetRegBaseOffsetAndSize__)(struct Hdacodec *, struct OBJGPU *, NvU32 *, NvU32 *); - NvBool (*__hdacodecCanCopy__)(struct Hdacodec *); NV_STATUS (*__hdacodecInternalControlForward__)(struct Hdacodec *, NvU32, void *, NvU32); - void (*__hdacodecPreDestruct__)(struct Hdacodec *); NV_STATUS (*__hdacodecUnmapFrom__)(struct Hdacodec *, RS_RES_UNMAP_FROM_PARAMS *); - NV_STATUS (*__hdacodecIsDuplicate__)(struct Hdacodec *, NvHandle, NvBool *); void (*__hdacodecControl_Epilogue__)(struct Hdacodec *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); NV_STATUS (*__hdacodecControlLookup__)(struct Hdacodec *, struct RS_RES_CONTROL_PARAMS_INTERNAL *, const struct NVOC_EXPORTED_METHOD_DEF **); + NvHandle (*__hdacodecGetInternalObjectHandle__)(struct Hdacodec *); + NV_STATUS (*__hdacodecControl__)(struct Hdacodec *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); + NV_STATUS (*__hdacodecUnmap__)(struct Hdacodec *, struct CALL_CONTEXT *, struct RsCpuMapping *); + NV_STATUS (*__hdacodecGetMemInterMapParams__)(struct Hdacodec *, RMRES_MEM_INTER_MAP_PARAMS *); + NV_STATUS (*__hdacodecGetMemoryMappingDescriptor__)(struct Hdacodec *, struct MEMORY_DESCRIPTOR **); + NV_STATUS (*__hdacodecControlFilter__)(struct Hdacodec *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); + NV_STATUS (*__hdacodecControlSerialization_Prologue__)(struct Hdacodec *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); + NvBool (*__hdacodecCanCopy__)(struct Hdacodec *); + void (*__hdacodecPreDestruct__)(struct Hdacodec *); + NV_STATUS (*__hdacodecIsDuplicate__)(struct Hdacodec *, NvHandle, NvBool *); + void (*__hdacodecControlSerialization_Epilogue__)(struct Hdacodec *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); NV_STATUS (*__hdacodecMap__)(struct Hdacodec *, struct CALL_CONTEXT *, struct RS_CPU_MAP_PARAMS *, struct RsCpuMapping *); NvBool (*__hdacodecAccessCallback__)(struct Hdacodec *, struct RsClient *, void *, RsAccessRight); }; @@ -108,110 +110,120 @@ __nvoc_objCreate_Hdacodec((ppNewObj), staticCast((pParent), Dynamic), (createFlags), arg_pCallContext, arg_pParams) #define hdacodecShareCallback(pGpuResource, pInvokingClient, pParentRef, pSharePolicy) hdacodecShareCallback_DISPATCH(pGpuResource, pInvokingClient, pParentRef, pSharePolicy) -#define hdacodecControl(pGpuResource, pCallContext, pParams) hdacodecControl_DISPATCH(pGpuResource, pCallContext, pParams) -#define hdacodecUnmap(pGpuResource, pCallContext, pCpuMapping) hdacodecUnmap_DISPATCH(pGpuResource, pCallContext, pCpuMapping) -#define hdacodecGetMemInterMapParams(pRmResource, pParams) hdacodecGetMemInterMapParams_DISPATCH(pRmResource, pParams) -#define hdacodecGetMemoryMappingDescriptor(pRmResource, ppMemDesc) hdacodecGetMemoryMappingDescriptor_DISPATCH(pRmResource, ppMemDesc) -#define hdacodecGetMapAddrSpace(pGpuResource, pCallContext, mapFlags, pAddrSpace) hdacodecGetMapAddrSpace_DISPATCH(pGpuResource, pCallContext, mapFlags, pAddrSpace) -#define hdacodecGetInternalObjectHandle(pGpuResource) hdacodecGetInternalObjectHandle_DISPATCH(pGpuResource) -#define hdacodecControlFilter(pResource, pCallContext, pParams) hdacodecControlFilter_DISPATCH(pResource, pCallContext, pParams) -#define hdacodecAddAdditionalDependants(pClient, pResource, pReference) hdacodecAddAdditionalDependants_DISPATCH(pClient, pResource, pReference) -#define hdacodecGetRefCount(pResource) hdacodecGetRefCount_DISPATCH(pResource) #define hdacodecCheckMemInterUnmap(pRmResource, bSubdeviceHandleProvided) hdacodecCheckMemInterUnmap_DISPATCH(pRmResource, bSubdeviceHandleProvided) #define hdacodecMapTo(pResource, pParams) hdacodecMapTo_DISPATCH(pResource, pParams) +#define hdacodecGetMapAddrSpace(pGpuResource, pCallContext, mapFlags, pAddrSpace) hdacodecGetMapAddrSpace_DISPATCH(pGpuResource, pCallContext, mapFlags, pAddrSpace) +#define hdacodecGetRefCount(pResource) hdacodecGetRefCount_DISPATCH(pResource) +#define hdacodecAddAdditionalDependants(pClient, pResource, pReference) hdacodecAddAdditionalDependants_DISPATCH(pClient, pResource, pReference) #define hdacodecControl_Prologue(pResource, pCallContext, pParams) hdacodecControl_Prologue_DISPATCH(pResource, pCallContext, pParams) #define hdacodecGetRegBaseOffsetAndSize(pGpuResource, pGpu, pOffset, pSize) hdacodecGetRegBaseOffsetAndSize_DISPATCH(pGpuResource, pGpu, pOffset, pSize) -#define hdacodecCanCopy(pResource) hdacodecCanCopy_DISPATCH(pResource) #define hdacodecInternalControlForward(pGpuResource, command, pParams, size) hdacodecInternalControlForward_DISPATCH(pGpuResource, command, pParams, size) -#define hdacodecPreDestruct(pResource) hdacodecPreDestruct_DISPATCH(pResource) #define hdacodecUnmapFrom(pResource, pParams) hdacodecUnmapFrom_DISPATCH(pResource, pParams) -#define hdacodecIsDuplicate(pResource, hMemory, pDuplicate) hdacodecIsDuplicate_DISPATCH(pResource, hMemory, pDuplicate) #define hdacodecControl_Epilogue(pResource, pCallContext, pParams) hdacodecControl_Epilogue_DISPATCH(pResource, pCallContext, pParams) #define hdacodecControlLookup(pResource, pParams, ppEntry) hdacodecControlLookup_DISPATCH(pResource, pParams, ppEntry) +#define hdacodecGetInternalObjectHandle(pGpuResource) hdacodecGetInternalObjectHandle_DISPATCH(pGpuResource) +#define hdacodecControl(pGpuResource, pCallContext, pParams) hdacodecControl_DISPATCH(pGpuResource, pCallContext, pParams) +#define hdacodecUnmap(pGpuResource, pCallContext, pCpuMapping) hdacodecUnmap_DISPATCH(pGpuResource, pCallContext, pCpuMapping) +#define hdacodecGetMemInterMapParams(pRmResource, pParams) hdacodecGetMemInterMapParams_DISPATCH(pRmResource, pParams) +#define hdacodecGetMemoryMappingDescriptor(pRmResource, ppMemDesc) hdacodecGetMemoryMappingDescriptor_DISPATCH(pRmResource, ppMemDesc) +#define hdacodecControlFilter(pResource, pCallContext, pParams) hdacodecControlFilter_DISPATCH(pResource, pCallContext, pParams) +#define hdacodecControlSerialization_Prologue(pResource, pCallContext, pParams) hdacodecControlSerialization_Prologue_DISPATCH(pResource, pCallContext, pParams) +#define hdacodecCanCopy(pResource) hdacodecCanCopy_DISPATCH(pResource) +#define hdacodecPreDestruct(pResource) hdacodecPreDestruct_DISPATCH(pResource) +#define hdacodecIsDuplicate(pResource, hMemory, pDuplicate) hdacodecIsDuplicate_DISPATCH(pResource, hMemory, pDuplicate) +#define hdacodecControlSerialization_Epilogue(pResource, pCallContext, pParams) hdacodecControlSerialization_Epilogue_DISPATCH(pResource, pCallContext, pParams) #define hdacodecMap(pGpuResource, pCallContext, pParams, pCpuMapping) hdacodecMap_DISPATCH(pGpuResource, pCallContext, pParams, pCpuMapping) #define hdacodecAccessCallback(pResource, pInvokingClient, pAllocParams, accessRight) hdacodecAccessCallback_DISPATCH(pResource, pInvokingClient, pAllocParams, accessRight) static inline NvBool hdacodecShareCallback_DISPATCH(struct Hdacodec *pGpuResource, struct RsClient *pInvokingClient, struct RsResourceRef *pParentRef, RS_SHARE_POLICY *pSharePolicy) { return pGpuResource->__hdacodecShareCallback__(pGpuResource, pInvokingClient, pParentRef, pSharePolicy); } -static inline NV_STATUS hdacodecControl_DISPATCH(struct Hdacodec *pGpuResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { - return pGpuResource->__hdacodecControl__(pGpuResource, pCallContext, pParams); +static inline NV_STATUS hdacodecCheckMemInterUnmap_DISPATCH(struct Hdacodec *pRmResource, NvBool bSubdeviceHandleProvided) { + return pRmResource->__hdacodecCheckMemInterUnmap__(pRmResource, bSubdeviceHandleProvided); } -static inline NV_STATUS hdacodecUnmap_DISPATCH(struct Hdacodec *pGpuResource, struct CALL_CONTEXT *pCallContext, struct RsCpuMapping *pCpuMapping) { - return pGpuResource->__hdacodecUnmap__(pGpuResource, pCallContext, pCpuMapping); +static inline NV_STATUS hdacodecMapTo_DISPATCH(struct Hdacodec *pResource, RS_RES_MAP_TO_PARAMS *pParams) { + return pResource->__hdacodecMapTo__(pResource, pParams); } -static inline NV_STATUS hdacodecGetMemInterMapParams_DISPATCH(struct Hdacodec *pRmResource, RMRES_MEM_INTER_MAP_PARAMS *pParams) { - return pRmResource->__hdacodecGetMemInterMapParams__(pRmResource, pParams); +static inline NV_STATUS hdacodecGetMapAddrSpace_DISPATCH(struct Hdacodec *pGpuResource, struct CALL_CONTEXT *pCallContext, NvU32 mapFlags, NV_ADDRESS_SPACE *pAddrSpace) { + return pGpuResource->__hdacodecGetMapAddrSpace__(pGpuResource, pCallContext, mapFlags, pAddrSpace); } -static inline NV_STATUS hdacodecGetMemoryMappingDescriptor_DISPATCH(struct Hdacodec *pRmResource, struct MEMORY_DESCRIPTOR **ppMemDesc) { - return pRmResource->__hdacodecGetMemoryMappingDescriptor__(pRmResource, ppMemDesc); +static inline NvU32 hdacodecGetRefCount_DISPATCH(struct Hdacodec *pResource) { + return pResource->__hdacodecGetRefCount__(pResource); } -static inline NV_STATUS hdacodecGetMapAddrSpace_DISPATCH(struct Hdacodec *pGpuResource, struct CALL_CONTEXT *pCallContext, NvU32 mapFlags, NV_ADDRESS_SPACE *pAddrSpace) { - return pGpuResource->__hdacodecGetMapAddrSpace__(pGpuResource, pCallContext, mapFlags, pAddrSpace); +static inline void hdacodecAddAdditionalDependants_DISPATCH(struct RsClient *pClient, struct Hdacodec *pResource, RsResourceRef *pReference) { + pResource->__hdacodecAddAdditionalDependants__(pClient, pResource, pReference); } -static inline NvHandle hdacodecGetInternalObjectHandle_DISPATCH(struct Hdacodec *pGpuResource) { - return pGpuResource->__hdacodecGetInternalObjectHandle__(pGpuResource); +static inline NV_STATUS hdacodecControl_Prologue_DISPATCH(struct Hdacodec *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return pResource->__hdacodecControl_Prologue__(pResource, pCallContext, pParams); } -static inline NV_STATUS hdacodecControlFilter_DISPATCH(struct Hdacodec *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { - return pResource->__hdacodecControlFilter__(pResource, pCallContext, pParams); +static inline NV_STATUS hdacodecGetRegBaseOffsetAndSize_DISPATCH(struct Hdacodec *pGpuResource, struct OBJGPU *pGpu, NvU32 *pOffset, NvU32 *pSize) { + return pGpuResource->__hdacodecGetRegBaseOffsetAndSize__(pGpuResource, pGpu, pOffset, pSize); } -static inline void hdacodecAddAdditionalDependants_DISPATCH(struct RsClient *pClient, struct Hdacodec *pResource, RsResourceRef *pReference) { - pResource->__hdacodecAddAdditionalDependants__(pClient, pResource, pReference); +static inline NV_STATUS hdacodecInternalControlForward_DISPATCH(struct Hdacodec *pGpuResource, NvU32 command, void *pParams, NvU32 size) { + return pGpuResource->__hdacodecInternalControlForward__(pGpuResource, command, pParams, size); } -static inline NvU32 hdacodecGetRefCount_DISPATCH(struct Hdacodec *pResource) { - return pResource->__hdacodecGetRefCount__(pResource); +static inline NV_STATUS hdacodecUnmapFrom_DISPATCH(struct Hdacodec *pResource, RS_RES_UNMAP_FROM_PARAMS *pParams) { + return pResource->__hdacodecUnmapFrom__(pResource, pParams); } -static inline NV_STATUS hdacodecCheckMemInterUnmap_DISPATCH(struct Hdacodec *pRmResource, NvBool bSubdeviceHandleProvided) { - return pRmResource->__hdacodecCheckMemInterUnmap__(pRmResource, bSubdeviceHandleProvided); +static inline void hdacodecControl_Epilogue_DISPATCH(struct Hdacodec *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + pResource->__hdacodecControl_Epilogue__(pResource, pCallContext, pParams); } -static inline NV_STATUS hdacodecMapTo_DISPATCH(struct Hdacodec *pResource, RS_RES_MAP_TO_PARAMS *pParams) { - return pResource->__hdacodecMapTo__(pResource, pParams); +static inline NV_STATUS hdacodecControlLookup_DISPATCH(struct Hdacodec *pResource, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams, const struct NVOC_EXPORTED_METHOD_DEF **ppEntry) { + return pResource->__hdacodecControlLookup__(pResource, pParams, ppEntry); } -static inline NV_STATUS hdacodecControl_Prologue_DISPATCH(struct Hdacodec *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { - return pResource->__hdacodecControl_Prologue__(pResource, pCallContext, pParams); +static inline NvHandle hdacodecGetInternalObjectHandle_DISPATCH(struct Hdacodec *pGpuResource) { + return pGpuResource->__hdacodecGetInternalObjectHandle__(pGpuResource); } -static inline NV_STATUS hdacodecGetRegBaseOffsetAndSize_DISPATCH(struct Hdacodec *pGpuResource, struct OBJGPU *pGpu, NvU32 *pOffset, NvU32 *pSize) { - return pGpuResource->__hdacodecGetRegBaseOffsetAndSize__(pGpuResource, pGpu, pOffset, pSize); +static inline NV_STATUS hdacodecControl_DISPATCH(struct Hdacodec *pGpuResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return pGpuResource->__hdacodecControl__(pGpuResource, pCallContext, pParams); } -static inline NvBool hdacodecCanCopy_DISPATCH(struct Hdacodec *pResource) { - return pResource->__hdacodecCanCopy__(pResource); +static inline NV_STATUS hdacodecUnmap_DISPATCH(struct Hdacodec *pGpuResource, struct CALL_CONTEXT *pCallContext, struct RsCpuMapping *pCpuMapping) { + return pGpuResource->__hdacodecUnmap__(pGpuResource, pCallContext, pCpuMapping); } -static inline NV_STATUS hdacodecInternalControlForward_DISPATCH(struct Hdacodec *pGpuResource, NvU32 command, void *pParams, NvU32 size) { - return pGpuResource->__hdacodecInternalControlForward__(pGpuResource, command, pParams, size); +static inline NV_STATUS hdacodecGetMemInterMapParams_DISPATCH(struct Hdacodec *pRmResource, RMRES_MEM_INTER_MAP_PARAMS *pParams) { + return pRmResource->__hdacodecGetMemInterMapParams__(pRmResource, pParams); } -static inline void hdacodecPreDestruct_DISPATCH(struct Hdacodec *pResource) { - pResource->__hdacodecPreDestruct__(pResource); +static inline NV_STATUS hdacodecGetMemoryMappingDescriptor_DISPATCH(struct Hdacodec *pRmResource, struct MEMORY_DESCRIPTOR **ppMemDesc) { + return pRmResource->__hdacodecGetMemoryMappingDescriptor__(pRmResource, ppMemDesc); } -static inline NV_STATUS hdacodecUnmapFrom_DISPATCH(struct Hdacodec *pResource, RS_RES_UNMAP_FROM_PARAMS *pParams) { - return pResource->__hdacodecUnmapFrom__(pResource, pParams); +static inline NV_STATUS hdacodecControlFilter_DISPATCH(struct Hdacodec *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return pResource->__hdacodecControlFilter__(pResource, pCallContext, pParams); } -static inline NV_STATUS hdacodecIsDuplicate_DISPATCH(struct Hdacodec *pResource, NvHandle hMemory, NvBool *pDuplicate) { - return pResource->__hdacodecIsDuplicate__(pResource, hMemory, pDuplicate); +static inline NV_STATUS hdacodecControlSerialization_Prologue_DISPATCH(struct Hdacodec *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return pResource->__hdacodecControlSerialization_Prologue__(pResource, pCallContext, pParams); } -static inline void hdacodecControl_Epilogue_DISPATCH(struct Hdacodec *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { - pResource->__hdacodecControl_Epilogue__(pResource, pCallContext, pParams); +static inline NvBool hdacodecCanCopy_DISPATCH(struct Hdacodec *pResource) { + return pResource->__hdacodecCanCopy__(pResource); } -static inline NV_STATUS hdacodecControlLookup_DISPATCH(struct Hdacodec *pResource, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams, const struct NVOC_EXPORTED_METHOD_DEF **ppEntry) { - return pResource->__hdacodecControlLookup__(pResource, pParams, ppEntry); +static inline void hdacodecPreDestruct_DISPATCH(struct Hdacodec *pResource) { + pResource->__hdacodecPreDestruct__(pResource); +} + +static inline NV_STATUS hdacodecIsDuplicate_DISPATCH(struct Hdacodec *pResource, NvHandle hMemory, NvBool *pDuplicate) { + return pResource->__hdacodecIsDuplicate__(pResource, hMemory, pDuplicate); +} + +static inline void hdacodecControlSerialization_Epilogue_DISPATCH(struct Hdacodec *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + pResource->__hdacodecControlSerialization_Epilogue__(pResource, pCallContext, pParams); } static inline NV_STATUS hdacodecMap_DISPATCH(struct Hdacodec *pGpuResource, struct CALL_CONTEXT *pCallContext, struct RS_CPU_MAP_PARAMS *pParams, struct RsCpuMapping *pCpuMapping) { diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/generated/g_heap_nvoc.c nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_heap_nvoc.c --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/generated/g_heap_nvoc.c 2023-10-25 20:27:01.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_heap_nvoc.c 2024-03-05 22:18:18.000000000 +0000 @@ -109,13 +109,16 @@ Object *pParentObj; Heap *pThis; - pThis = portMemAllocNonPaged(sizeof(Heap)); - if (pThis == NULL) return NV_ERR_NO_MEMORY; + status = __nvoc_handleObjCreateMemAlloc(createFlags, sizeof(Heap), (void**)&pThis, (void**)ppThis); + if (status != NV_OK) + return status; portMemSet(pThis, 0, sizeof(Heap)); __nvoc_initRtti(staticCast(pThis, Dynamic), &__nvoc_class_def_Heap); + pThis->__nvoc_base_Object.createFlags = createFlags; + if (pParent != NULL && !(createFlags & NVOC_OBJ_CREATE_FLAGS_PARENT_HALSPEC_ONLY)) { pParentObj = dynamicCast(pParent, Object); @@ -131,11 +134,17 @@ if (status != NV_OK) goto __nvoc_objCreate_Heap_cleanup; *ppThis = pThis; + return NV_OK; __nvoc_objCreate_Heap_cleanup: // do not call destructors here since the constructor already called them - portMemFree(pThis); + if (createFlags & NVOC_OBJ_CREATE_FLAGS_IN_PLACE_CONSTRUCT) + portMemSet(pThis, 0, sizeof(Heap)); + else + portMemFree(pThis); + + // coverity[leaked_storage:FALSE] return status; } diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/generated/g_host_eng_nvoc.c nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_host_eng_nvoc.c --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/generated/g_host_eng_nvoc.c 2023-10-25 20:27:01.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_host_eng_nvoc.c 2024-03-05 22:18:18.000000000 +0000 @@ -76,11 +76,7 @@ static void __nvoc_init_funcTable_OBJHOSTENG_1(OBJHOSTENG *pThis) { PORT_UNREFERENCED_VARIABLE(pThis); - pThis->__hostengHaltEngine__ = &hostengHaltEngine_IMPL; - pThis->__hostengHaltAndReset__ = &hostengHaltAndReset_IMPL; - - pThis->__hostengReset__ = &hostengReset_IMPL; } void __nvoc_init_funcTable_OBJHOSTENG(OBJHOSTENG *pThis) { diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/generated/g_host_eng_nvoc.h nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_host_eng_nvoc.h --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/generated/g_host_eng_nvoc.h 2023-10-25 20:27:01.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_host_eng_nvoc.h 2024-03-05 22:18:18.000000000 +0000 @@ -57,9 +57,7 @@ struct OBJHOSTENG { const struct NVOC_RTTI *__nvoc_rtti; struct OBJHOSTENG *__nvoc_pbase_OBJHOSTENG; - NV_STATUS (*__hostengHaltEngine__)(struct OBJGPU *, struct OBJHOSTENG *); NV_STATUS (*__hostengHaltAndReset__)(struct OBJGPU *, struct OBJHOSTENG *, RMTIMEOUT *); - NV_STATUS (*__hostengReset__)(struct OBJGPU *, struct OBJHOSTENG *, NvBool, struct KernelChannel *, struct KernelChannel **); }; #ifndef __NVOC_CLASS_OBJHOSTENG_TYPEDEF__ @@ -90,27 +88,13 @@ #define __objCreate_OBJHOSTENG(ppNewObj, pParent, createFlags) \ __nvoc_objCreate_OBJHOSTENG((ppNewObj), staticCast((pParent), Dynamic), (createFlags)) -#define hostengHaltEngine(pGpu, pHosteng) hostengHaltEngine_DISPATCH(pGpu, pHosteng) #define hostengHaltAndReset(pGpu, pHosteng, pRmTimeout) hostengHaltAndReset_DISPATCH(pGpu, pHosteng, pRmTimeout) -#define hostengReset(pGpu, pHosteng, bReload, pKernelChannel, ppCurrentKernelChannel) hostengReset_DISPATCH(pGpu, pHosteng, bReload, pKernelChannel, ppCurrentKernelChannel) -NV_STATUS hostengHaltEngine_IMPL(struct OBJGPU *pGpu, struct OBJHOSTENG *pHosteng); - -static inline NV_STATUS hostengHaltEngine_DISPATCH(struct OBJGPU *pGpu, struct OBJHOSTENG *pHosteng) { - return pHosteng->__hostengHaltEngine__(pGpu, pHosteng); -} - NV_STATUS hostengHaltAndReset_IMPL(struct OBJGPU *pGpu, struct OBJHOSTENG *pHosteng, RMTIMEOUT *pRmTimeout); static inline NV_STATUS hostengHaltAndReset_DISPATCH(struct OBJGPU *pGpu, struct OBJHOSTENG *pHosteng, RMTIMEOUT *pRmTimeout) { return pHosteng->__hostengHaltAndReset__(pGpu, pHosteng, pRmTimeout); } -NV_STATUS hostengReset_IMPL(struct OBJGPU *pGpu, struct OBJHOSTENG *pHosteng, NvBool bReload, struct KernelChannel *pKernelChannel, struct KernelChannel **ppCurrentKernelChannel); - -static inline NV_STATUS hostengReset_DISPATCH(struct OBJGPU *pGpu, struct OBJHOSTENG *pHosteng, NvBool bReload, struct KernelChannel *pKernelChannel, struct KernelChannel **ppCurrentKernelChannel) { - return pHosteng->__hostengReset__(pGpu, pHosteng, bReload, pKernelChannel, ppCurrentKernelChannel); -} - #undef PRIVATE_FIELD diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/generated/g_hw_resources_nvoc.c nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_hw_resources_nvoc.c --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/generated/g_hw_resources_nvoc.c 2023-10-25 20:27:02.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_hw_resources_nvoc.c 2024-03-05 22:18:18.000000000 +0000 @@ -101,60 +101,76 @@ return memCheckMemInterUnmap((struct Memory *)(((unsigned char *)pMemory) + __nvoc_rtti_MemoryHwResources_Memory.offset), bSubdeviceHandleProvided); } -static NV_STATUS __nvoc_thunk_Memory_hwresControl(struct MemoryHwResources *pMemory, CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { - return memControl((struct Memory *)(((unsigned char *)pMemory) + __nvoc_rtti_MemoryHwResources_Memory.offset), pCallContext, pParams); +static NvBool __nvoc_thunk_RmResource_hwresShareCallback(struct MemoryHwResources *pResource, struct RsClient *pInvokingClient, struct RsResourceRef *pParentRef, RS_SHARE_POLICY *pSharePolicy) { + return rmresShareCallback((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_MemoryHwResources_RmResource.offset), pInvokingClient, pParentRef, pSharePolicy); } -static NV_STATUS __nvoc_thunk_Memory_hwresUnmap(struct MemoryHwResources *pMemory, CALL_CONTEXT *pCallContext, RsCpuMapping *pCpuMapping) { - return memUnmap((struct Memory *)(((unsigned char *)pMemory) + __nvoc_rtti_MemoryHwResources_Memory.offset), pCallContext, pCpuMapping); +static NV_STATUS __nvoc_thunk_RsResource_hwresMapTo(struct MemoryHwResources *pResource, RS_RES_MAP_TO_PARAMS *pParams) { + return resMapTo((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_MemoryHwResources_RsResource.offset), pParams); } -static NV_STATUS __nvoc_thunk_Memory_hwresGetMemInterMapParams(struct MemoryHwResources *pMemory, RMRES_MEM_INTER_MAP_PARAMS *pParams) { - return memGetMemInterMapParams((struct Memory *)(((unsigned char *)pMemory) + __nvoc_rtti_MemoryHwResources_Memory.offset), pParams); +static NV_STATUS __nvoc_thunk_Memory_hwresGetMapAddrSpace(struct MemoryHwResources *pMemory, CALL_CONTEXT *pCallContext, NvU32 mapFlags, NV_ADDRESS_SPACE *pAddrSpace) { + return memGetMapAddrSpace((struct Memory *)(((unsigned char *)pMemory) + __nvoc_rtti_MemoryHwResources_Memory.offset), pCallContext, mapFlags, pAddrSpace); } -static NV_STATUS __nvoc_thunk_Memory_hwresGetMemoryMappingDescriptor(struct MemoryHwResources *pMemory, MEMORY_DESCRIPTOR **ppMemDesc) { - return memGetMemoryMappingDescriptor((struct Memory *)(((unsigned char *)pMemory) + __nvoc_rtti_MemoryHwResources_Memory.offset), ppMemDesc); +static NvU32 __nvoc_thunk_RsResource_hwresGetRefCount(struct MemoryHwResources *pResource) { + return resGetRefCount((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_MemoryHwResources_RsResource.offset)); } -static NV_STATUS __nvoc_thunk_Memory_hwresGetMapAddrSpace(struct MemoryHwResources *pMemory, CALL_CONTEXT *pCallContext, NvU32 mapFlags, NV_ADDRESS_SPACE *pAddrSpace) { - return memGetMapAddrSpace((struct Memory *)(((unsigned char *)pMemory) + __nvoc_rtti_MemoryHwResources_Memory.offset), pCallContext, mapFlags, pAddrSpace); +static void __nvoc_thunk_RsResource_hwresAddAdditionalDependants(struct RsClient *pClient, struct MemoryHwResources *pResource, RsResourceRef *pReference) { + resAddAdditionalDependants(pClient, (struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_MemoryHwResources_RsResource.offset), pReference); } -static NvBool __nvoc_thunk_RmResource_hwresShareCallback(struct MemoryHwResources *pResource, struct RsClient *pInvokingClient, struct RsResourceRef *pParentRef, RS_SHARE_POLICY *pSharePolicy) { - return rmresShareCallback((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_MemoryHwResources_RmResource.offset), pInvokingClient, pParentRef, pSharePolicy); +static NV_STATUS __nvoc_thunk_RmResource_hwresControl_Prologue(struct MemoryHwResources *pResource, CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return rmresControl_Prologue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_MemoryHwResources_RmResource.offset), pCallContext, pParams); } -static NV_STATUS __nvoc_thunk_RsResource_hwresControlFilter(struct MemoryHwResources *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { - return resControlFilter((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_MemoryHwResources_RsResource.offset), pCallContext, pParams); +static NvBool __nvoc_thunk_Memory_hwresIsGpuMapAllowed(struct MemoryHwResources *pMemory, struct OBJGPU *pGpu) { + return memIsGpuMapAllowed((struct Memory *)(((unsigned char *)pMemory) + __nvoc_rtti_MemoryHwResources_Memory.offset), pGpu); } -static void __nvoc_thunk_RsResource_hwresAddAdditionalDependants(struct RsClient *pClient, struct MemoryHwResources *pResource, RsResourceRef *pReference) { - resAddAdditionalDependants(pClient, (struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_MemoryHwResources_RsResource.offset), pReference); +static NV_STATUS __nvoc_thunk_RsResource_hwresUnmapFrom(struct MemoryHwResources *pResource, RS_RES_UNMAP_FROM_PARAMS *pParams) { + return resUnmapFrom((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_MemoryHwResources_RsResource.offset), pParams); } -static NvU32 __nvoc_thunk_RsResource_hwresGetRefCount(struct MemoryHwResources *pResource) { - return resGetRefCount((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_MemoryHwResources_RsResource.offset)); +static void __nvoc_thunk_RmResource_hwresControl_Epilogue(struct MemoryHwResources *pResource, CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + rmresControl_Epilogue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_MemoryHwResources_RmResource.offset), pCallContext, pParams); } -static NV_STATUS __nvoc_thunk_RsResource_hwresMapTo(struct MemoryHwResources *pResource, RS_RES_MAP_TO_PARAMS *pParams) { - return resMapTo((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_MemoryHwResources_RsResource.offset), pParams); +static NV_STATUS __nvoc_thunk_RsResource_hwresControlLookup(struct MemoryHwResources *pResource, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams, const struct NVOC_EXPORTED_METHOD_DEF **ppEntry) { + return resControlLookup((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_MemoryHwResources_RsResource.offset), pParams, ppEntry); } -static NV_STATUS __nvoc_thunk_RmResource_hwresControl_Prologue(struct MemoryHwResources *pResource, CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { - return rmresControl_Prologue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_MemoryHwResources_RmResource.offset), pCallContext, pParams); +static NV_STATUS __nvoc_thunk_Memory_hwresControl(struct MemoryHwResources *pMemory, CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return memControl((struct Memory *)(((unsigned char *)pMemory) + __nvoc_rtti_MemoryHwResources_Memory.offset), pCallContext, pParams); } -static NvBool __nvoc_thunk_Memory_hwresIsGpuMapAllowed(struct MemoryHwResources *pMemory, struct OBJGPU *pGpu) { - return memIsGpuMapAllowed((struct Memory *)(((unsigned char *)pMemory) + __nvoc_rtti_MemoryHwResources_Memory.offset), pGpu); +static NV_STATUS __nvoc_thunk_Memory_hwresUnmap(struct MemoryHwResources *pMemory, CALL_CONTEXT *pCallContext, RsCpuMapping *pCpuMapping) { + return memUnmap((struct Memory *)(((unsigned char *)pMemory) + __nvoc_rtti_MemoryHwResources_Memory.offset), pCallContext, pCpuMapping); +} + +static NV_STATUS __nvoc_thunk_Memory_hwresGetMemInterMapParams(struct MemoryHwResources *pMemory, RMRES_MEM_INTER_MAP_PARAMS *pParams) { + return memGetMemInterMapParams((struct Memory *)(((unsigned char *)pMemory) + __nvoc_rtti_MemoryHwResources_Memory.offset), pParams); +} + +static NV_STATUS __nvoc_thunk_Memory_hwresGetMemoryMappingDescriptor(struct MemoryHwResources *pMemory, MEMORY_DESCRIPTOR **ppMemDesc) { + return memGetMemoryMappingDescriptor((struct Memory *)(((unsigned char *)pMemory) + __nvoc_rtti_MemoryHwResources_Memory.offset), ppMemDesc); +} + +static NV_STATUS __nvoc_thunk_RsResource_hwresControlFilter(struct MemoryHwResources *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return resControlFilter((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_MemoryHwResources_RsResource.offset), pCallContext, pParams); +} + +static NV_STATUS __nvoc_thunk_RmResource_hwresControlSerialization_Prologue(struct MemoryHwResources *pResource, CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return rmresControlSerialization_Prologue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_MemoryHwResources_RmResource.offset), pCallContext, pParams); } static NV_STATUS __nvoc_thunk_Memory_hwresIsReady(struct MemoryHwResources *pMemory, NvBool bCopyConstructorContext) { return memIsReady((struct Memory *)(((unsigned char *)pMemory) + __nvoc_rtti_MemoryHwResources_Memory.offset), bCopyConstructorContext); } -static NV_STATUS __nvoc_thunk_Memory_hwresCheckCopyPermissions(struct MemoryHwResources *pMemory, struct OBJGPU *pDstGpu, NvHandle hDstClientNvBool) { - return memCheckCopyPermissions((struct Memory *)(((unsigned char *)pMemory) + __nvoc_rtti_MemoryHwResources_Memory.offset), pDstGpu, hDstClientNvBool); +static NV_STATUS __nvoc_thunk_Memory_hwresCheckCopyPermissions(struct MemoryHwResources *pMemory, struct OBJGPU *pDstGpu, struct Device *pDstDevice) { + return memCheckCopyPermissions((struct Memory *)(((unsigned char *)pMemory) + __nvoc_rtti_MemoryHwResources_Memory.offset), pDstGpu, pDstDevice); } static void __nvoc_thunk_RsResource_hwresPreDestruct(struct MemoryHwResources *pResource) { @@ -165,16 +181,8 @@ return memIsDuplicate((struct Memory *)(((unsigned char *)pMemory) + __nvoc_rtti_MemoryHwResources_Memory.offset), hMemory, pDuplicate); } -static NV_STATUS __nvoc_thunk_RsResource_hwresUnmapFrom(struct MemoryHwResources *pResource, RS_RES_UNMAP_FROM_PARAMS *pParams) { - return resUnmapFrom((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_MemoryHwResources_RsResource.offset), pParams); -} - -static void __nvoc_thunk_RmResource_hwresControl_Epilogue(struct MemoryHwResources *pResource, CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { - rmresControl_Epilogue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_MemoryHwResources_RmResource.offset), pCallContext, pParams); -} - -static NV_STATUS __nvoc_thunk_RsResource_hwresControlLookup(struct MemoryHwResources *pResource, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams, const struct NVOC_EXPORTED_METHOD_DEF **ppEntry) { - return resControlLookup((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_MemoryHwResources_RsResource.offset), pParams, ppEntry); +static void __nvoc_thunk_RmResource_hwresControlSerialization_Epilogue(struct MemoryHwResources *pResource, CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + rmresControlSerialization_Epilogue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_MemoryHwResources_RmResource.offset), pCallContext, pParams); } static NV_STATUS __nvoc_thunk_Memory_hwresMap(struct MemoryHwResources *pMemory, CALL_CONTEXT *pCallContext, struct RS_CPU_MAP_PARAMS *pParams, RsCpuMapping *pCpuMapping) { @@ -230,29 +238,37 @@ pThis->__hwresCheckMemInterUnmap__ = &__nvoc_thunk_Memory_hwresCheckMemInterUnmap; - pThis->__hwresControl__ = &__nvoc_thunk_Memory_hwresControl; + pThis->__hwresShareCallback__ = &__nvoc_thunk_RmResource_hwresShareCallback; - pThis->__hwresUnmap__ = &__nvoc_thunk_Memory_hwresUnmap; + pThis->__hwresMapTo__ = &__nvoc_thunk_RsResource_hwresMapTo; - pThis->__hwresGetMemInterMapParams__ = &__nvoc_thunk_Memory_hwresGetMemInterMapParams; + pThis->__hwresGetMapAddrSpace__ = &__nvoc_thunk_Memory_hwresGetMapAddrSpace; - pThis->__hwresGetMemoryMappingDescriptor__ = &__nvoc_thunk_Memory_hwresGetMemoryMappingDescriptor; + pThis->__hwresGetRefCount__ = &__nvoc_thunk_RsResource_hwresGetRefCount; - pThis->__hwresGetMapAddrSpace__ = &__nvoc_thunk_Memory_hwresGetMapAddrSpace; + pThis->__hwresAddAdditionalDependants__ = &__nvoc_thunk_RsResource_hwresAddAdditionalDependants; - pThis->__hwresShareCallback__ = &__nvoc_thunk_RmResource_hwresShareCallback; + pThis->__hwresControl_Prologue__ = &__nvoc_thunk_RmResource_hwresControl_Prologue; - pThis->__hwresControlFilter__ = &__nvoc_thunk_RsResource_hwresControlFilter; + pThis->__hwresIsGpuMapAllowed__ = &__nvoc_thunk_Memory_hwresIsGpuMapAllowed; - pThis->__hwresAddAdditionalDependants__ = &__nvoc_thunk_RsResource_hwresAddAdditionalDependants; + pThis->__hwresUnmapFrom__ = &__nvoc_thunk_RsResource_hwresUnmapFrom; - pThis->__hwresGetRefCount__ = &__nvoc_thunk_RsResource_hwresGetRefCount; + pThis->__hwresControl_Epilogue__ = &__nvoc_thunk_RmResource_hwresControl_Epilogue; - pThis->__hwresMapTo__ = &__nvoc_thunk_RsResource_hwresMapTo; + pThis->__hwresControlLookup__ = &__nvoc_thunk_RsResource_hwresControlLookup; - pThis->__hwresControl_Prologue__ = &__nvoc_thunk_RmResource_hwresControl_Prologue; + pThis->__hwresControl__ = &__nvoc_thunk_Memory_hwresControl; - pThis->__hwresIsGpuMapAllowed__ = &__nvoc_thunk_Memory_hwresIsGpuMapAllowed; + pThis->__hwresUnmap__ = &__nvoc_thunk_Memory_hwresUnmap; + + pThis->__hwresGetMemInterMapParams__ = &__nvoc_thunk_Memory_hwresGetMemInterMapParams; + + pThis->__hwresGetMemoryMappingDescriptor__ = &__nvoc_thunk_Memory_hwresGetMemoryMappingDescriptor; + + pThis->__hwresControlFilter__ = &__nvoc_thunk_RsResource_hwresControlFilter; + + pThis->__hwresControlSerialization_Prologue__ = &__nvoc_thunk_RmResource_hwresControlSerialization_Prologue; pThis->__hwresIsReady__ = &__nvoc_thunk_Memory_hwresIsReady; @@ -262,11 +278,7 @@ pThis->__hwresIsDuplicate__ = &__nvoc_thunk_Memory_hwresIsDuplicate; - pThis->__hwresUnmapFrom__ = &__nvoc_thunk_RsResource_hwresUnmapFrom; - - pThis->__hwresControl_Epilogue__ = &__nvoc_thunk_RmResource_hwresControl_Epilogue; - - pThis->__hwresControlLookup__ = &__nvoc_thunk_RsResource_hwresControlLookup; + pThis->__hwresControlSerialization_Epilogue__ = &__nvoc_thunk_RmResource_hwresControlSerialization_Epilogue; pThis->__hwresMap__ = &__nvoc_thunk_Memory_hwresMap; @@ -294,13 +306,16 @@ Object *pParentObj; MemoryHwResources *pThis; - pThis = portMemAllocNonPaged(sizeof(MemoryHwResources)); - if (pThis == NULL) return NV_ERR_NO_MEMORY; + status = __nvoc_handleObjCreateMemAlloc(createFlags, sizeof(MemoryHwResources), (void**)&pThis, (void**)ppThis); + if (status != NV_OK) + return status; portMemSet(pThis, 0, sizeof(MemoryHwResources)); __nvoc_initRtti(staticCast(pThis, Dynamic), &__nvoc_class_def_MemoryHwResources); + pThis->__nvoc_base_Memory.__nvoc_base_RmResource.__nvoc_base_RsResource.__nvoc_base_Object.createFlags = createFlags; + if (pParent != NULL && !(createFlags & NVOC_OBJ_CREATE_FLAGS_PARENT_HALSPEC_ONLY)) { pParentObj = dynamicCast(pParent, Object); @@ -316,11 +331,17 @@ if (status != NV_OK) goto __nvoc_objCreate_MemoryHwResources_cleanup; *ppThis = pThis; + return NV_OK; __nvoc_objCreate_MemoryHwResources_cleanup: // do not call destructors here since the constructor already called them - portMemFree(pThis); + if (createFlags & NVOC_OBJ_CREATE_FLAGS_IN_PLACE_CONSTRUCT) + portMemSet(pThis, 0, sizeof(MemoryHwResources)); + else + portMemFree(pThis); + + // coverity[leaked_storage:FALSE] return status; } diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/generated/g_hw_resources_nvoc.h nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_hw_resources_nvoc.h --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/generated/g_hw_resources_nvoc.h 2023-10-25 20:27:02.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_hw_resources_nvoc.h 2024-03-05 22:18:19.000000000 +0000 @@ -55,25 +55,27 @@ struct MemoryHwResources *__nvoc_pbase_MemoryHwResources; NvBool (*__hwresCanCopy__)(struct MemoryHwResources *); NV_STATUS (*__hwresCheckMemInterUnmap__)(struct MemoryHwResources *, NvBool); + NvBool (*__hwresShareCallback__)(struct MemoryHwResources *, struct RsClient *, struct RsResourceRef *, RS_SHARE_POLICY *); + NV_STATUS (*__hwresMapTo__)(struct MemoryHwResources *, RS_RES_MAP_TO_PARAMS *); + NV_STATUS (*__hwresGetMapAddrSpace__)(struct MemoryHwResources *, CALL_CONTEXT *, NvU32, NV_ADDRESS_SPACE *); + NvU32 (*__hwresGetRefCount__)(struct MemoryHwResources *); + void (*__hwresAddAdditionalDependants__)(struct RsClient *, struct MemoryHwResources *, RsResourceRef *); + NV_STATUS (*__hwresControl_Prologue__)(struct MemoryHwResources *, CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); + NvBool (*__hwresIsGpuMapAllowed__)(struct MemoryHwResources *, struct OBJGPU *); + NV_STATUS (*__hwresUnmapFrom__)(struct MemoryHwResources *, RS_RES_UNMAP_FROM_PARAMS *); + void (*__hwresControl_Epilogue__)(struct MemoryHwResources *, CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); + NV_STATUS (*__hwresControlLookup__)(struct MemoryHwResources *, struct RS_RES_CONTROL_PARAMS_INTERNAL *, const struct NVOC_EXPORTED_METHOD_DEF **); NV_STATUS (*__hwresControl__)(struct MemoryHwResources *, CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); NV_STATUS (*__hwresUnmap__)(struct MemoryHwResources *, CALL_CONTEXT *, RsCpuMapping *); NV_STATUS (*__hwresGetMemInterMapParams__)(struct MemoryHwResources *, RMRES_MEM_INTER_MAP_PARAMS *); NV_STATUS (*__hwresGetMemoryMappingDescriptor__)(struct MemoryHwResources *, MEMORY_DESCRIPTOR **); - NV_STATUS (*__hwresGetMapAddrSpace__)(struct MemoryHwResources *, CALL_CONTEXT *, NvU32, NV_ADDRESS_SPACE *); - NvBool (*__hwresShareCallback__)(struct MemoryHwResources *, struct RsClient *, struct RsResourceRef *, RS_SHARE_POLICY *); NV_STATUS (*__hwresControlFilter__)(struct MemoryHwResources *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); - void (*__hwresAddAdditionalDependants__)(struct RsClient *, struct MemoryHwResources *, RsResourceRef *); - NvU32 (*__hwresGetRefCount__)(struct MemoryHwResources *); - NV_STATUS (*__hwresMapTo__)(struct MemoryHwResources *, RS_RES_MAP_TO_PARAMS *); - NV_STATUS (*__hwresControl_Prologue__)(struct MemoryHwResources *, CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); - NvBool (*__hwresIsGpuMapAllowed__)(struct MemoryHwResources *, struct OBJGPU *); + NV_STATUS (*__hwresControlSerialization_Prologue__)(struct MemoryHwResources *, CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); NV_STATUS (*__hwresIsReady__)(struct MemoryHwResources *, NvBool); - NV_STATUS (*__hwresCheckCopyPermissions__)(struct MemoryHwResources *, struct OBJGPU *, NvHandle); + NV_STATUS (*__hwresCheckCopyPermissions__)(struct MemoryHwResources *, struct OBJGPU *, struct Device *); void (*__hwresPreDestruct__)(struct MemoryHwResources *); NV_STATUS (*__hwresIsDuplicate__)(struct MemoryHwResources *, NvHandle, NvBool *); - NV_STATUS (*__hwresUnmapFrom__)(struct MemoryHwResources *, RS_RES_UNMAP_FROM_PARAMS *); - void (*__hwresControl_Epilogue__)(struct MemoryHwResources *, CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); - NV_STATUS (*__hwresControlLookup__)(struct MemoryHwResources *, struct RS_RES_CONTROL_PARAMS_INTERNAL *, const struct NVOC_EXPORTED_METHOD_DEF **); + void (*__hwresControlSerialization_Epilogue__)(struct MemoryHwResources *, CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); NV_STATUS (*__hwresMap__)(struct MemoryHwResources *, CALL_CONTEXT *, struct RS_CPU_MAP_PARAMS *, RsCpuMapping *); NvBool (*__hwresAccessCallback__)(struct MemoryHwResources *, struct RsClient *, void *, RsAccessRight); }; @@ -108,25 +110,27 @@ #define hwresCanCopy(pMemoryHwResources) hwresCanCopy_DISPATCH(pMemoryHwResources) #define hwresCheckMemInterUnmap(pMemory, bSubdeviceHandleProvided) hwresCheckMemInterUnmap_DISPATCH(pMemory, bSubdeviceHandleProvided) +#define hwresShareCallback(pResource, pInvokingClient, pParentRef, pSharePolicy) hwresShareCallback_DISPATCH(pResource, pInvokingClient, pParentRef, pSharePolicy) +#define hwresMapTo(pResource, pParams) hwresMapTo_DISPATCH(pResource, pParams) +#define hwresGetMapAddrSpace(pMemory, pCallContext, mapFlags, pAddrSpace) hwresGetMapAddrSpace_DISPATCH(pMemory, pCallContext, mapFlags, pAddrSpace) +#define hwresGetRefCount(pResource) hwresGetRefCount_DISPATCH(pResource) +#define hwresAddAdditionalDependants(pClient, pResource, pReference) hwresAddAdditionalDependants_DISPATCH(pClient, pResource, pReference) +#define hwresControl_Prologue(pResource, pCallContext, pParams) hwresControl_Prologue_DISPATCH(pResource, pCallContext, pParams) +#define hwresIsGpuMapAllowed(pMemory, pGpu) hwresIsGpuMapAllowed_DISPATCH(pMemory, pGpu) +#define hwresUnmapFrom(pResource, pParams) hwresUnmapFrom_DISPATCH(pResource, pParams) +#define hwresControl_Epilogue(pResource, pCallContext, pParams) hwresControl_Epilogue_DISPATCH(pResource, pCallContext, pParams) +#define hwresControlLookup(pResource, pParams, ppEntry) hwresControlLookup_DISPATCH(pResource, pParams, ppEntry) #define hwresControl(pMemory, pCallContext, pParams) hwresControl_DISPATCH(pMemory, pCallContext, pParams) #define hwresUnmap(pMemory, pCallContext, pCpuMapping) hwresUnmap_DISPATCH(pMemory, pCallContext, pCpuMapping) #define hwresGetMemInterMapParams(pMemory, pParams) hwresGetMemInterMapParams_DISPATCH(pMemory, pParams) #define hwresGetMemoryMappingDescriptor(pMemory, ppMemDesc) hwresGetMemoryMappingDescriptor_DISPATCH(pMemory, ppMemDesc) -#define hwresGetMapAddrSpace(pMemory, pCallContext, mapFlags, pAddrSpace) hwresGetMapAddrSpace_DISPATCH(pMemory, pCallContext, mapFlags, pAddrSpace) -#define hwresShareCallback(pResource, pInvokingClient, pParentRef, pSharePolicy) hwresShareCallback_DISPATCH(pResource, pInvokingClient, pParentRef, pSharePolicy) #define hwresControlFilter(pResource, pCallContext, pParams) hwresControlFilter_DISPATCH(pResource, pCallContext, pParams) -#define hwresAddAdditionalDependants(pClient, pResource, pReference) hwresAddAdditionalDependants_DISPATCH(pClient, pResource, pReference) -#define hwresGetRefCount(pResource) hwresGetRefCount_DISPATCH(pResource) -#define hwresMapTo(pResource, pParams) hwresMapTo_DISPATCH(pResource, pParams) -#define hwresControl_Prologue(pResource, pCallContext, pParams) hwresControl_Prologue_DISPATCH(pResource, pCallContext, pParams) -#define hwresIsGpuMapAllowed(pMemory, pGpu) hwresIsGpuMapAllowed_DISPATCH(pMemory, pGpu) +#define hwresControlSerialization_Prologue(pResource, pCallContext, pParams) hwresControlSerialization_Prologue_DISPATCH(pResource, pCallContext, pParams) #define hwresIsReady(pMemory, bCopyConstructorContext) hwresIsReady_DISPATCH(pMemory, bCopyConstructorContext) -#define hwresCheckCopyPermissions(pMemory, pDstGpu, hDstClientNvBool) hwresCheckCopyPermissions_DISPATCH(pMemory, pDstGpu, hDstClientNvBool) +#define hwresCheckCopyPermissions(pMemory, pDstGpu, pDstDevice) hwresCheckCopyPermissions_DISPATCH(pMemory, pDstGpu, pDstDevice) #define hwresPreDestruct(pResource) hwresPreDestruct_DISPATCH(pResource) #define hwresIsDuplicate(pMemory, hMemory, pDuplicate) hwresIsDuplicate_DISPATCH(pMemory, hMemory, pDuplicate) -#define hwresUnmapFrom(pResource, pParams) hwresUnmapFrom_DISPATCH(pResource, pParams) -#define hwresControl_Epilogue(pResource, pCallContext, pParams) hwresControl_Epilogue_DISPATCH(pResource, pCallContext, pParams) -#define hwresControlLookup(pResource, pParams, ppEntry) hwresControlLookup_DISPATCH(pResource, pParams, ppEntry) +#define hwresControlSerialization_Epilogue(pResource, pCallContext, pParams) hwresControlSerialization_Epilogue_DISPATCH(pResource, pCallContext, pParams) #define hwresMap(pMemory, pCallContext, pParams, pCpuMapping) hwresMap_DISPATCH(pMemory, pCallContext, pParams, pCpuMapping) #define hwresAccessCallback(pResource, pInvokingClient, pAllocParams, accessRight) hwresAccessCallback_DISPATCH(pResource, pInvokingClient, pAllocParams, accessRight) NvBool hwresCanCopy_IMPL(struct MemoryHwResources *pMemoryHwResources); @@ -139,60 +143,76 @@ return pMemory->__hwresCheckMemInterUnmap__(pMemory, bSubdeviceHandleProvided); } -static inline NV_STATUS hwresControl_DISPATCH(struct MemoryHwResources *pMemory, CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { - return pMemory->__hwresControl__(pMemory, pCallContext, pParams); +static inline NvBool hwresShareCallback_DISPATCH(struct MemoryHwResources *pResource, struct RsClient *pInvokingClient, struct RsResourceRef *pParentRef, RS_SHARE_POLICY *pSharePolicy) { + return pResource->__hwresShareCallback__(pResource, pInvokingClient, pParentRef, pSharePolicy); } -static inline NV_STATUS hwresUnmap_DISPATCH(struct MemoryHwResources *pMemory, CALL_CONTEXT *pCallContext, RsCpuMapping *pCpuMapping) { - return pMemory->__hwresUnmap__(pMemory, pCallContext, pCpuMapping); +static inline NV_STATUS hwresMapTo_DISPATCH(struct MemoryHwResources *pResource, RS_RES_MAP_TO_PARAMS *pParams) { + return pResource->__hwresMapTo__(pResource, pParams); } -static inline NV_STATUS hwresGetMemInterMapParams_DISPATCH(struct MemoryHwResources *pMemory, RMRES_MEM_INTER_MAP_PARAMS *pParams) { - return pMemory->__hwresGetMemInterMapParams__(pMemory, pParams); +static inline NV_STATUS hwresGetMapAddrSpace_DISPATCH(struct MemoryHwResources *pMemory, CALL_CONTEXT *pCallContext, NvU32 mapFlags, NV_ADDRESS_SPACE *pAddrSpace) { + return pMemory->__hwresGetMapAddrSpace__(pMemory, pCallContext, mapFlags, pAddrSpace); } -static inline NV_STATUS hwresGetMemoryMappingDescriptor_DISPATCH(struct MemoryHwResources *pMemory, MEMORY_DESCRIPTOR **ppMemDesc) { - return pMemory->__hwresGetMemoryMappingDescriptor__(pMemory, ppMemDesc); +static inline NvU32 hwresGetRefCount_DISPATCH(struct MemoryHwResources *pResource) { + return pResource->__hwresGetRefCount__(pResource); } -static inline NV_STATUS hwresGetMapAddrSpace_DISPATCH(struct MemoryHwResources *pMemory, CALL_CONTEXT *pCallContext, NvU32 mapFlags, NV_ADDRESS_SPACE *pAddrSpace) { - return pMemory->__hwresGetMapAddrSpace__(pMemory, pCallContext, mapFlags, pAddrSpace); +static inline void hwresAddAdditionalDependants_DISPATCH(struct RsClient *pClient, struct MemoryHwResources *pResource, RsResourceRef *pReference) { + pResource->__hwresAddAdditionalDependants__(pClient, pResource, pReference); } -static inline NvBool hwresShareCallback_DISPATCH(struct MemoryHwResources *pResource, struct RsClient *pInvokingClient, struct RsResourceRef *pParentRef, RS_SHARE_POLICY *pSharePolicy) { - return pResource->__hwresShareCallback__(pResource, pInvokingClient, pParentRef, pSharePolicy); +static inline NV_STATUS hwresControl_Prologue_DISPATCH(struct MemoryHwResources *pResource, CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return pResource->__hwresControl_Prologue__(pResource, pCallContext, pParams); } -static inline NV_STATUS hwresControlFilter_DISPATCH(struct MemoryHwResources *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { - return pResource->__hwresControlFilter__(pResource, pCallContext, pParams); +static inline NvBool hwresIsGpuMapAllowed_DISPATCH(struct MemoryHwResources *pMemory, struct OBJGPU *pGpu) { + return pMemory->__hwresIsGpuMapAllowed__(pMemory, pGpu); } -static inline void hwresAddAdditionalDependants_DISPATCH(struct RsClient *pClient, struct MemoryHwResources *pResource, RsResourceRef *pReference) { - pResource->__hwresAddAdditionalDependants__(pClient, pResource, pReference); +static inline NV_STATUS hwresUnmapFrom_DISPATCH(struct MemoryHwResources *pResource, RS_RES_UNMAP_FROM_PARAMS *pParams) { + return pResource->__hwresUnmapFrom__(pResource, pParams); } -static inline NvU32 hwresGetRefCount_DISPATCH(struct MemoryHwResources *pResource) { - return pResource->__hwresGetRefCount__(pResource); +static inline void hwresControl_Epilogue_DISPATCH(struct MemoryHwResources *pResource, CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + pResource->__hwresControl_Epilogue__(pResource, pCallContext, pParams); } -static inline NV_STATUS hwresMapTo_DISPATCH(struct MemoryHwResources *pResource, RS_RES_MAP_TO_PARAMS *pParams) { - return pResource->__hwresMapTo__(pResource, pParams); +static inline NV_STATUS hwresControlLookup_DISPATCH(struct MemoryHwResources *pResource, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams, const struct NVOC_EXPORTED_METHOD_DEF **ppEntry) { + return pResource->__hwresControlLookup__(pResource, pParams, ppEntry); } -static inline NV_STATUS hwresControl_Prologue_DISPATCH(struct MemoryHwResources *pResource, CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { - return pResource->__hwresControl_Prologue__(pResource, pCallContext, pParams); +static inline NV_STATUS hwresControl_DISPATCH(struct MemoryHwResources *pMemory, CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return pMemory->__hwresControl__(pMemory, pCallContext, pParams); } -static inline NvBool hwresIsGpuMapAllowed_DISPATCH(struct MemoryHwResources *pMemory, struct OBJGPU *pGpu) { - return pMemory->__hwresIsGpuMapAllowed__(pMemory, pGpu); +static inline NV_STATUS hwresUnmap_DISPATCH(struct MemoryHwResources *pMemory, CALL_CONTEXT *pCallContext, RsCpuMapping *pCpuMapping) { + return pMemory->__hwresUnmap__(pMemory, pCallContext, pCpuMapping); +} + +static inline NV_STATUS hwresGetMemInterMapParams_DISPATCH(struct MemoryHwResources *pMemory, RMRES_MEM_INTER_MAP_PARAMS *pParams) { + return pMemory->__hwresGetMemInterMapParams__(pMemory, pParams); +} + +static inline NV_STATUS hwresGetMemoryMappingDescriptor_DISPATCH(struct MemoryHwResources *pMemory, MEMORY_DESCRIPTOR **ppMemDesc) { + return pMemory->__hwresGetMemoryMappingDescriptor__(pMemory, ppMemDesc); +} + +static inline NV_STATUS hwresControlFilter_DISPATCH(struct MemoryHwResources *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return pResource->__hwresControlFilter__(pResource, pCallContext, pParams); +} + +static inline NV_STATUS hwresControlSerialization_Prologue_DISPATCH(struct MemoryHwResources *pResource, CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return pResource->__hwresControlSerialization_Prologue__(pResource, pCallContext, pParams); } static inline NV_STATUS hwresIsReady_DISPATCH(struct MemoryHwResources *pMemory, NvBool bCopyConstructorContext) { return pMemory->__hwresIsReady__(pMemory, bCopyConstructorContext); } -static inline NV_STATUS hwresCheckCopyPermissions_DISPATCH(struct MemoryHwResources *pMemory, struct OBJGPU *pDstGpu, NvHandle hDstClientNvBool) { - return pMemory->__hwresCheckCopyPermissions__(pMemory, pDstGpu, hDstClientNvBool); +static inline NV_STATUS hwresCheckCopyPermissions_DISPATCH(struct MemoryHwResources *pMemory, struct OBJGPU *pDstGpu, struct Device *pDstDevice) { + return pMemory->__hwresCheckCopyPermissions__(pMemory, pDstGpu, pDstDevice); } static inline void hwresPreDestruct_DISPATCH(struct MemoryHwResources *pResource) { @@ -203,16 +223,8 @@ return pMemory->__hwresIsDuplicate__(pMemory, hMemory, pDuplicate); } -static inline NV_STATUS hwresUnmapFrom_DISPATCH(struct MemoryHwResources *pResource, RS_RES_UNMAP_FROM_PARAMS *pParams) { - return pResource->__hwresUnmapFrom__(pResource, pParams); -} - -static inline void hwresControl_Epilogue_DISPATCH(struct MemoryHwResources *pResource, CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { - pResource->__hwresControl_Epilogue__(pResource, pCallContext, pParams); -} - -static inline NV_STATUS hwresControlLookup_DISPATCH(struct MemoryHwResources *pResource, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams, const struct NVOC_EXPORTED_METHOD_DEF **ppEntry) { - return pResource->__hwresControlLookup__(pResource, pParams, ppEntry); +static inline void hwresControlSerialization_Epilogue_DISPATCH(struct MemoryHwResources *pResource, CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + pResource->__hwresControlSerialization_Epilogue__(pResource, pCallContext, pParams); } static inline NV_STATUS hwresMap_DISPATCH(struct MemoryHwResources *pMemory, CALL_CONTEXT *pCallContext, struct RS_CPU_MAP_PARAMS *pParams, RsCpuMapping *pCpuMapping) { diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/generated/g_hypervisor_nvoc.c nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_hypervisor_nvoc.c --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/generated/g_hypervisor_nvoc.c 2023-10-25 20:27:02.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_hypervisor_nvoc.c 2024-03-05 22:18:19.000000000 +0000 @@ -114,13 +114,16 @@ Object *pParentObj; OBJHYPERVISOR *pThis; - pThis = portMemAllocNonPaged(sizeof(OBJHYPERVISOR)); - if (pThis == NULL) return NV_ERR_NO_MEMORY; + status = __nvoc_handleObjCreateMemAlloc(createFlags, sizeof(OBJHYPERVISOR), (void**)&pThis, (void**)ppThis); + if (status != NV_OK) + return status; portMemSet(pThis, 0, sizeof(OBJHYPERVISOR)); __nvoc_initRtti(staticCast(pThis, Dynamic), &__nvoc_class_def_OBJHYPERVISOR); + pThis->__nvoc_base_Object.createFlags = createFlags; + if (pParent != NULL && !(createFlags & NVOC_OBJ_CREATE_FLAGS_PARENT_HALSPEC_ONLY)) { pParentObj = dynamicCast(pParent, Object); @@ -136,11 +139,17 @@ if (status != NV_OK) goto __nvoc_objCreate_OBJHYPERVISOR_cleanup; *ppThis = pThis; + return NV_OK; __nvoc_objCreate_OBJHYPERVISOR_cleanup: // do not call destructors here since the constructor already called them - portMemFree(pThis); + if (createFlags & NVOC_OBJ_CREATE_FLAGS_IN_PLACE_CONSTRUCT) + portMemSet(pThis, 0, sizeof(OBJHYPERVISOR)); + else + portMemFree(pThis); + + // coverity[leaked_storage:FALSE] return status; } diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/generated/g_hypervisor_nvoc.h nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_hypervisor_nvoc.h --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/generated/g_hypervisor_nvoc.h 2023-10-25 20:27:02.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_hypervisor_nvoc.h 2024-03-05 22:18:19.000000000 +0000 @@ -88,6 +88,7 @@ HYPERVISOR_TYPE type; NvBool bIsHypervHost; NvBool bIsHypervVgpuSupported; + NvBool bIsACSupported; }; #ifndef __NVOC_CLASS_OBJHYPERVISOR_TYPEDEF__ @@ -153,162 +154,24 @@ #define hypervisorSetHypervVgpuSupported_HAL(arg0) hypervisorSetHypervVgpuSupported(arg0) -static inline NV_STATUS hypervisorSetupGuestVmBusChannel_56cd7a(struct OBJHYPERVISOR *arg0, struct OBJGPU *arg1) { - return NV_OK; -} - - -#ifdef __nvoc_hypervisor_h_disabled -static inline NV_STATUS hypervisorSetupGuestVmBusChannel(struct OBJHYPERVISOR *arg0, struct OBJGPU *arg1) { - NV_ASSERT_FAILED_PRECOMP("OBJHYPERVISOR was disabled!"); - return NV_ERR_NOT_SUPPORTED; -} -#else //__nvoc_hypervisor_h_disabled -#define hypervisorSetupGuestVmBusChannel(arg0, arg1) hypervisorSetupGuestVmBusChannel_56cd7a(arg0, arg1) -#endif //__nvoc_hypervisor_h_disabled - -#define hypervisorSetupGuestVmBusChannel_HAL(arg0, arg1) hypervisorSetupGuestVmBusChannel(arg0, arg1) - -static inline void hypervisorDestroyGuestVmBusChannel_b3696a(struct OBJHYPERVISOR *arg0) { - return; -} - - -#ifdef __nvoc_hypervisor_h_disabled -static inline void hypervisorDestroyGuestVmBusChannel(struct OBJHYPERVISOR *arg0) { - NV_ASSERT_FAILED_PRECOMP("OBJHYPERVISOR was disabled!"); -} -#else //__nvoc_hypervisor_h_disabled -#define hypervisorDestroyGuestVmBusChannel(arg0) hypervisorDestroyGuestVmBusChannel_b3696a(arg0) -#endif //__nvoc_hypervisor_h_disabled - -#define hypervisorDestroyGuestVmBusChannel_HAL(arg0) hypervisorDestroyGuestVmBusChannel(arg0) - -static inline NV_STATUS hypervisorSetupHostVmBusChannel_56cd7a(struct OBJHYPERVISOR *arg0, NvU64 arg1, struct OBJGPU *arg2, HOST_VGPU_DEVICE *arg3) { - return NV_OK; -} - - -#ifdef __nvoc_hypervisor_h_disabled -static inline NV_STATUS hypervisorSetupHostVmBusChannel(struct OBJHYPERVISOR *arg0, NvU64 arg1, struct OBJGPU *arg2, HOST_VGPU_DEVICE *arg3) { - NV_ASSERT_FAILED_PRECOMP("OBJHYPERVISOR was disabled!"); - return NV_ERR_NOT_SUPPORTED; -} -#else //__nvoc_hypervisor_h_disabled -#define hypervisorSetupHostVmBusChannel(arg0, arg1, arg2, arg3) hypervisorSetupHostVmBusChannel_56cd7a(arg0, arg1, arg2, arg3) -#endif //__nvoc_hypervisor_h_disabled - -#define hypervisorSetupHostVmBusChannel_HAL(arg0, arg1, arg2, arg3) hypervisorSetupHostVmBusChannel(arg0, arg1, arg2, arg3) - -static inline void hypervisorResetHostVmBusChannel_b3696a(struct OBJHYPERVISOR *arg0, HOST_VGPU_DEVICE *arg1) { - return; -} - - -#ifdef __nvoc_hypervisor_h_disabled -static inline void hypervisorResetHostVmBusChannel(struct OBJHYPERVISOR *arg0, HOST_VGPU_DEVICE *arg1) { - NV_ASSERT_FAILED_PRECOMP("OBJHYPERVISOR was disabled!"); -} -#else //__nvoc_hypervisor_h_disabled -#define hypervisorResetHostVmBusChannel(arg0, arg1) hypervisorResetHostVmBusChannel_b3696a(arg0, arg1) -#endif //__nvoc_hypervisor_h_disabled - -#define hypervisorResetHostVmBusChannel_HAL(arg0, arg1) hypervisorResetHostVmBusChannel(arg0, arg1) - -static inline NV_STATUS hypervisorGuestPinPages_56cd7a(struct OBJHYPERVISOR *arg0, MEMORY_DESCRIPTOR *arg1) { - return NV_OK; -} - - -#ifdef __nvoc_hypervisor_h_disabled -static inline NV_STATUS hypervisorGuestPinPages(struct OBJHYPERVISOR *arg0, MEMORY_DESCRIPTOR *arg1) { - NV_ASSERT_FAILED_PRECOMP("OBJHYPERVISOR was disabled!"); - return NV_ERR_NOT_SUPPORTED; -} -#else //__nvoc_hypervisor_h_disabled -#define hypervisorGuestPinPages(arg0, arg1) hypervisorGuestPinPages_56cd7a(arg0, arg1) -#endif //__nvoc_hypervisor_h_disabled +NvBool hypervisorIsAC_IMPL(void); -#define hypervisorGuestPinPages_HAL(arg0, arg1) hypervisorGuestPinPages(arg0, arg1) - -static inline NV_STATUS hypervisorGuestPinPagesUsingPfns_56cd7a(struct OBJHYPERVISOR *arg0, NvU32 arg1, NvU64 *arg2) { - return NV_OK; -} - - -#ifdef __nvoc_hypervisor_h_disabled -static inline NV_STATUS hypervisorGuestPinPagesUsingPfns(struct OBJHYPERVISOR *arg0, NvU32 arg1, NvU64 *arg2) { - NV_ASSERT_FAILED_PRECOMP("OBJHYPERVISOR was disabled!"); - return NV_ERR_NOT_SUPPORTED; -} -#else //__nvoc_hypervisor_h_disabled -#define hypervisorGuestPinPagesUsingPfns(arg0, arg1, arg2) hypervisorGuestPinPagesUsingPfns_56cd7a(arg0, arg1, arg2) -#endif //__nvoc_hypervisor_h_disabled - -#define hypervisorGuestPinPagesUsingPfns_HAL(arg0, arg1, arg2) hypervisorGuestPinPagesUsingPfns(arg0, arg1, arg2) - -static inline NV_STATUS hypervisorSendEventToGuest_56cd7a(struct OBJHYPERVISOR *arg0, void *arg1) { - return NV_OK; -} +#define hypervisorIsAC() hypervisorIsAC_IMPL() +#define hypervisorIsAC_HAL() hypervisorIsAC() -#ifdef __nvoc_hypervisor_h_disabled -static inline NV_STATUS hypervisorSendEventToGuest(struct OBJHYPERVISOR *arg0, void *arg1) { - NV_ASSERT_FAILED_PRECOMP("OBJHYPERVISOR was disabled!"); - return NV_ERR_NOT_SUPPORTED; -} -#else //__nvoc_hypervisor_h_disabled -#define hypervisorSendEventToGuest(arg0, arg1) hypervisorSendEventToGuest_56cd7a(arg0, arg1) -#endif //__nvoc_hypervisor_h_disabled - -#define hypervisorSendEventToGuest_HAL(arg0, arg1) hypervisorSendEventToGuest(arg0, arg1) - -static inline NV_STATUS hypervisorAllocHostVmbusChannel_56cd7a(struct OBJHYPERVISOR *arg0, HOST_VGPU_DEVICE *arg1) { - return NV_OK; -} +void hypervisorSetACSupported_IMPL(struct OBJHYPERVISOR *arg0); #ifdef __nvoc_hypervisor_h_disabled -static inline NV_STATUS hypervisorAllocHostVmbusChannel(struct OBJHYPERVISOR *arg0, HOST_VGPU_DEVICE *arg1) { +static inline void hypervisorSetACSupported(struct OBJHYPERVISOR *arg0) { NV_ASSERT_FAILED_PRECOMP("OBJHYPERVISOR was disabled!"); - return NV_ERR_NOT_SUPPORTED; } #else //__nvoc_hypervisor_h_disabled -#define hypervisorAllocHostVmbusChannel(arg0, arg1) hypervisorAllocHostVmbusChannel_56cd7a(arg0, arg1) +#define hypervisorSetACSupported(arg0) hypervisorSetACSupported_IMPL(arg0) #endif //__nvoc_hypervisor_h_disabled -#define hypervisorAllocHostVmbusChannel_HAL(arg0, arg1) hypervisorAllocHostVmbusChannel(arg0, arg1) - -static inline void hypervisorFreeHostVmbusChannel_b3696a(struct OBJHYPERVISOR *arg0, HOST_VGPU_DEVICE *arg1) { - return; -} - - -#ifdef __nvoc_hypervisor_h_disabled -static inline void hypervisorFreeHostVmbusChannel(struct OBJHYPERVISOR *arg0, HOST_VGPU_DEVICE *arg1) { - NV_ASSERT_FAILED_PRECOMP("OBJHYPERVISOR was disabled!"); -} -#else //__nvoc_hypervisor_h_disabled -#define hypervisorFreeHostVmbusChannel(arg0, arg1) hypervisorFreeHostVmbusChannel_b3696a(arg0, arg1) -#endif //__nvoc_hypervisor_h_disabled - -#define hypervisorFreeHostVmbusChannel_HAL(arg0, arg1) hypervisorFreeHostVmbusChannel(arg0, arg1) - -static inline NV_STATUS hypervisorVmbusHostCompletePacket_56cd7a(struct OBJHYPERVISOR *arg0, NvU64 arg1, HOST_VGPU_DEVICE *arg2) { - return NV_OK; -} - - -#ifdef __nvoc_hypervisor_h_disabled -static inline NV_STATUS hypervisorVmbusHostCompletePacket(struct OBJHYPERVISOR *arg0, NvU64 arg1, HOST_VGPU_DEVICE *arg2) { - NV_ASSERT_FAILED_PRECOMP("OBJHYPERVISOR was disabled!"); - return NV_ERR_NOT_SUPPORTED; -} -#else //__nvoc_hypervisor_h_disabled -#define hypervisorVmbusHostCompletePacket(arg0, arg1, arg2) hypervisorVmbusHostCompletePacket_56cd7a(arg0, arg1, arg2) -#endif //__nvoc_hypervisor_h_disabled - -#define hypervisorVmbusHostCompletePacket_HAL(arg0, arg1, arg2) hypervisorVmbusHostCompletePacket(arg0, arg1, arg2) +#define hypervisorSetACSupported_HAL(arg0) hypervisorSetACSupported(arg0) NvBool hypervisorCheckForObjectAccess_IMPL(NvHandle hClient); @@ -357,6 +220,16 @@ #define hypervisorGetHypervisorType(arg0) hypervisorGetHypervisorType_IMPL(arg0) #endif //__nvoc_hypervisor_h_disabled +void hypervisorSetHypervisorType_IMPL(struct OBJHYPERVISOR *pHypervisor, HYPERVISOR_TYPE type); + +#ifdef __nvoc_hypervisor_h_disabled +static inline void hypervisorSetHypervisorType(struct OBJHYPERVISOR *pHypervisor, HYPERVISOR_TYPE type) { + NV_ASSERT_FAILED_PRECOMP("OBJHYPERVISOR was disabled!"); +} +#else //__nvoc_hypervisor_h_disabled +#define hypervisorSetHypervisorType(pHypervisor, type) hypervisorSetHypervisorType_IMPL(pHypervisor, type) +#endif //__nvoc_hypervisor_h_disabled + #undef PRIVATE_FIELD diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/generated/g_i2c_api_nvoc.c nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_i2c_api_nvoc.c --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/generated/g_i2c_api_nvoc.c 2023-10-25 20:27:02.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_i2c_api_nvoc.c 2024-03-05 22:18:19.000000000 +0000 @@ -97,84 +97,92 @@ return gpuresShareCallback((struct GpuResource *)(((unsigned char *)pGpuResource) + __nvoc_rtti_I2cApi_GpuResource.offset), pInvokingClient, pParentRef, pSharePolicy); } -static NV_STATUS __nvoc_thunk_GpuResource_i2capiControl(struct I2cApi *pGpuResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { - return gpuresControl((struct GpuResource *)(((unsigned char *)pGpuResource) + __nvoc_rtti_I2cApi_GpuResource.offset), pCallContext, pParams); +static NV_STATUS __nvoc_thunk_RmResource_i2capiCheckMemInterUnmap(struct I2cApi *pRmResource, NvBool bSubdeviceHandleProvided) { + return rmresCheckMemInterUnmap((struct RmResource *)(((unsigned char *)pRmResource) + __nvoc_rtti_I2cApi_RmResource.offset), bSubdeviceHandleProvided); } -static NV_STATUS __nvoc_thunk_GpuResource_i2capiUnmap(struct I2cApi *pGpuResource, struct CALL_CONTEXT *pCallContext, struct RsCpuMapping *pCpuMapping) { - return gpuresUnmap((struct GpuResource *)(((unsigned char *)pGpuResource) + __nvoc_rtti_I2cApi_GpuResource.offset), pCallContext, pCpuMapping); +static NV_STATUS __nvoc_thunk_RsResource_i2capiMapTo(struct I2cApi *pResource, RS_RES_MAP_TO_PARAMS *pParams) { + return resMapTo((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_I2cApi_RsResource.offset), pParams); } -static NV_STATUS __nvoc_thunk_RmResource_i2capiGetMemInterMapParams(struct I2cApi *pRmResource, RMRES_MEM_INTER_MAP_PARAMS *pParams) { - return rmresGetMemInterMapParams((struct RmResource *)(((unsigned char *)pRmResource) + __nvoc_rtti_I2cApi_RmResource.offset), pParams); +static NV_STATUS __nvoc_thunk_GpuResource_i2capiGetMapAddrSpace(struct I2cApi *pGpuResource, struct CALL_CONTEXT *pCallContext, NvU32 mapFlags, NV_ADDRESS_SPACE *pAddrSpace) { + return gpuresGetMapAddrSpace((struct GpuResource *)(((unsigned char *)pGpuResource) + __nvoc_rtti_I2cApi_GpuResource.offset), pCallContext, mapFlags, pAddrSpace); } -static NV_STATUS __nvoc_thunk_RmResource_i2capiGetMemoryMappingDescriptor(struct I2cApi *pRmResource, struct MEMORY_DESCRIPTOR **ppMemDesc) { - return rmresGetMemoryMappingDescriptor((struct RmResource *)(((unsigned char *)pRmResource) + __nvoc_rtti_I2cApi_RmResource.offset), ppMemDesc); +static NvU32 __nvoc_thunk_RsResource_i2capiGetRefCount(struct I2cApi *pResource) { + return resGetRefCount((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_I2cApi_RsResource.offset)); } -static NV_STATUS __nvoc_thunk_GpuResource_i2capiGetMapAddrSpace(struct I2cApi *pGpuResource, struct CALL_CONTEXT *pCallContext, NvU32 mapFlags, NV_ADDRESS_SPACE *pAddrSpace) { - return gpuresGetMapAddrSpace((struct GpuResource *)(((unsigned char *)pGpuResource) + __nvoc_rtti_I2cApi_GpuResource.offset), pCallContext, mapFlags, pAddrSpace); +static void __nvoc_thunk_RsResource_i2capiAddAdditionalDependants(struct RsClient *pClient, struct I2cApi *pResource, RsResourceRef *pReference) { + resAddAdditionalDependants(pClient, (struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_I2cApi_RsResource.offset), pReference); } -static NvHandle __nvoc_thunk_GpuResource_i2capiGetInternalObjectHandle(struct I2cApi *pGpuResource) { - return gpuresGetInternalObjectHandle((struct GpuResource *)(((unsigned char *)pGpuResource) + __nvoc_rtti_I2cApi_GpuResource.offset)); +static NV_STATUS __nvoc_thunk_RmResource_i2capiControl_Prologue(struct I2cApi *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return rmresControl_Prologue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_I2cApi_RmResource.offset), pCallContext, pParams); } -static NV_STATUS __nvoc_thunk_RsResource_i2capiControlFilter(struct I2cApi *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { - return resControlFilter((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_I2cApi_RsResource.offset), pCallContext, pParams); +static NV_STATUS __nvoc_thunk_GpuResource_i2capiGetRegBaseOffsetAndSize(struct I2cApi *pGpuResource, struct OBJGPU *pGpu, NvU32 *pOffset, NvU32 *pSize) { + return gpuresGetRegBaseOffsetAndSize((struct GpuResource *)(((unsigned char *)pGpuResource) + __nvoc_rtti_I2cApi_GpuResource.offset), pGpu, pOffset, pSize); } -static void __nvoc_thunk_RsResource_i2capiAddAdditionalDependants(struct RsClient *pClient, struct I2cApi *pResource, RsResourceRef *pReference) { - resAddAdditionalDependants(pClient, (struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_I2cApi_RsResource.offset), pReference); +static NV_STATUS __nvoc_thunk_GpuResource_i2capiInternalControlForward(struct I2cApi *pGpuResource, NvU32 command, void *pParams, NvU32 size) { + return gpuresInternalControlForward((struct GpuResource *)(((unsigned char *)pGpuResource) + __nvoc_rtti_I2cApi_GpuResource.offset), command, pParams, size); } -static NvU32 __nvoc_thunk_RsResource_i2capiGetRefCount(struct I2cApi *pResource) { - return resGetRefCount((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_I2cApi_RsResource.offset)); +static NV_STATUS __nvoc_thunk_RsResource_i2capiUnmapFrom(struct I2cApi *pResource, RS_RES_UNMAP_FROM_PARAMS *pParams) { + return resUnmapFrom((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_I2cApi_RsResource.offset), pParams); } -static NV_STATUS __nvoc_thunk_RmResource_i2capiCheckMemInterUnmap(struct I2cApi *pRmResource, NvBool bSubdeviceHandleProvided) { - return rmresCheckMemInterUnmap((struct RmResource *)(((unsigned char *)pRmResource) + __nvoc_rtti_I2cApi_RmResource.offset), bSubdeviceHandleProvided); +static void __nvoc_thunk_RmResource_i2capiControl_Epilogue(struct I2cApi *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + rmresControl_Epilogue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_I2cApi_RmResource.offset), pCallContext, pParams); } -static NV_STATUS __nvoc_thunk_RsResource_i2capiMapTo(struct I2cApi *pResource, RS_RES_MAP_TO_PARAMS *pParams) { - return resMapTo((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_I2cApi_RsResource.offset), pParams); +static NV_STATUS __nvoc_thunk_RsResource_i2capiControlLookup(struct I2cApi *pResource, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams, const struct NVOC_EXPORTED_METHOD_DEF **ppEntry) { + return resControlLookup((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_I2cApi_RsResource.offset), pParams, ppEntry); } -static NV_STATUS __nvoc_thunk_RmResource_i2capiControl_Prologue(struct I2cApi *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { - return rmresControl_Prologue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_I2cApi_RmResource.offset), pCallContext, pParams); +static NvHandle __nvoc_thunk_GpuResource_i2capiGetInternalObjectHandle(struct I2cApi *pGpuResource) { + return gpuresGetInternalObjectHandle((struct GpuResource *)(((unsigned char *)pGpuResource) + __nvoc_rtti_I2cApi_GpuResource.offset)); } -static NV_STATUS __nvoc_thunk_GpuResource_i2capiGetRegBaseOffsetAndSize(struct I2cApi *pGpuResource, struct OBJGPU *pGpu, NvU32 *pOffset, NvU32 *pSize) { - return gpuresGetRegBaseOffsetAndSize((struct GpuResource *)(((unsigned char *)pGpuResource) + __nvoc_rtti_I2cApi_GpuResource.offset), pGpu, pOffset, pSize); +static NV_STATUS __nvoc_thunk_GpuResource_i2capiControl(struct I2cApi *pGpuResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return gpuresControl((struct GpuResource *)(((unsigned char *)pGpuResource) + __nvoc_rtti_I2cApi_GpuResource.offset), pCallContext, pParams); } -static NvBool __nvoc_thunk_RsResource_i2capiCanCopy(struct I2cApi *pResource) { - return resCanCopy((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_I2cApi_RsResource.offset)); +static NV_STATUS __nvoc_thunk_GpuResource_i2capiUnmap(struct I2cApi *pGpuResource, struct CALL_CONTEXT *pCallContext, struct RsCpuMapping *pCpuMapping) { + return gpuresUnmap((struct GpuResource *)(((unsigned char *)pGpuResource) + __nvoc_rtti_I2cApi_GpuResource.offset), pCallContext, pCpuMapping); } -static NV_STATUS __nvoc_thunk_GpuResource_i2capiInternalControlForward(struct I2cApi *pGpuResource, NvU32 command, void *pParams, NvU32 size) { - return gpuresInternalControlForward((struct GpuResource *)(((unsigned char *)pGpuResource) + __nvoc_rtti_I2cApi_GpuResource.offset), command, pParams, size); +static NV_STATUS __nvoc_thunk_RmResource_i2capiGetMemInterMapParams(struct I2cApi *pRmResource, RMRES_MEM_INTER_MAP_PARAMS *pParams) { + return rmresGetMemInterMapParams((struct RmResource *)(((unsigned char *)pRmResource) + __nvoc_rtti_I2cApi_RmResource.offset), pParams); } -static void __nvoc_thunk_RsResource_i2capiPreDestruct(struct I2cApi *pResource) { - resPreDestruct((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_I2cApi_RsResource.offset)); +static NV_STATUS __nvoc_thunk_RmResource_i2capiGetMemoryMappingDescriptor(struct I2cApi *pRmResource, struct MEMORY_DESCRIPTOR **ppMemDesc) { + return rmresGetMemoryMappingDescriptor((struct RmResource *)(((unsigned char *)pRmResource) + __nvoc_rtti_I2cApi_RmResource.offset), ppMemDesc); } -static NV_STATUS __nvoc_thunk_RsResource_i2capiUnmapFrom(struct I2cApi *pResource, RS_RES_UNMAP_FROM_PARAMS *pParams) { - return resUnmapFrom((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_I2cApi_RsResource.offset), pParams); +static NV_STATUS __nvoc_thunk_RsResource_i2capiControlFilter(struct I2cApi *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return resControlFilter((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_I2cApi_RsResource.offset), pCallContext, pParams); } -static NV_STATUS __nvoc_thunk_RsResource_i2capiIsDuplicate(struct I2cApi *pResource, NvHandle hMemory, NvBool *pDuplicate) { - return resIsDuplicate((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_I2cApi_RsResource.offset), hMemory, pDuplicate); +static NV_STATUS __nvoc_thunk_RmResource_i2capiControlSerialization_Prologue(struct I2cApi *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return rmresControlSerialization_Prologue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_I2cApi_RmResource.offset), pCallContext, pParams); } -static void __nvoc_thunk_RmResource_i2capiControl_Epilogue(struct I2cApi *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { - rmresControl_Epilogue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_I2cApi_RmResource.offset), pCallContext, pParams); +static NvBool __nvoc_thunk_RsResource_i2capiCanCopy(struct I2cApi *pResource) { + return resCanCopy((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_I2cApi_RsResource.offset)); } -static NV_STATUS __nvoc_thunk_RsResource_i2capiControlLookup(struct I2cApi *pResource, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams, const struct NVOC_EXPORTED_METHOD_DEF **ppEntry) { - return resControlLookup((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_I2cApi_RsResource.offset), pParams, ppEntry); +static void __nvoc_thunk_RsResource_i2capiPreDestruct(struct I2cApi *pResource) { + resPreDestruct((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_I2cApi_RsResource.offset)); +} + +static NV_STATUS __nvoc_thunk_RsResource_i2capiIsDuplicate(struct I2cApi *pResource, NvHandle hMemory, NvBool *pDuplicate) { + return resIsDuplicate((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_I2cApi_RsResource.offset), hMemory, pDuplicate); +} + +static void __nvoc_thunk_RmResource_i2capiControlSerialization_Epilogue(struct I2cApi *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + rmresControlSerialization_Epilogue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_I2cApi_RmResource.offset), pCallContext, pParams); } static NV_STATUS __nvoc_thunk_GpuResource_i2capiMap(struct I2cApi *pGpuResource, struct CALL_CONTEXT *pCallContext, struct RS_CPU_MAP_PARAMS *pParams, struct RsCpuMapping *pCpuMapping) { @@ -330,45 +338,49 @@ pThis->__i2capiShareCallback__ = &__nvoc_thunk_GpuResource_i2capiShareCallback; - pThis->__i2capiControl__ = &__nvoc_thunk_GpuResource_i2capiControl; + pThis->__i2capiCheckMemInterUnmap__ = &__nvoc_thunk_RmResource_i2capiCheckMemInterUnmap; - pThis->__i2capiUnmap__ = &__nvoc_thunk_GpuResource_i2capiUnmap; + pThis->__i2capiMapTo__ = &__nvoc_thunk_RsResource_i2capiMapTo; - pThis->__i2capiGetMemInterMapParams__ = &__nvoc_thunk_RmResource_i2capiGetMemInterMapParams; + pThis->__i2capiGetMapAddrSpace__ = &__nvoc_thunk_GpuResource_i2capiGetMapAddrSpace; - pThis->__i2capiGetMemoryMappingDescriptor__ = &__nvoc_thunk_RmResource_i2capiGetMemoryMappingDescriptor; + pThis->__i2capiGetRefCount__ = &__nvoc_thunk_RsResource_i2capiGetRefCount; - pThis->__i2capiGetMapAddrSpace__ = &__nvoc_thunk_GpuResource_i2capiGetMapAddrSpace; + pThis->__i2capiAddAdditionalDependants__ = &__nvoc_thunk_RsResource_i2capiAddAdditionalDependants; - pThis->__i2capiGetInternalObjectHandle__ = &__nvoc_thunk_GpuResource_i2capiGetInternalObjectHandle; + pThis->__i2capiControl_Prologue__ = &__nvoc_thunk_RmResource_i2capiControl_Prologue; - pThis->__i2capiControlFilter__ = &__nvoc_thunk_RsResource_i2capiControlFilter; + pThis->__i2capiGetRegBaseOffsetAndSize__ = &__nvoc_thunk_GpuResource_i2capiGetRegBaseOffsetAndSize; - pThis->__i2capiAddAdditionalDependants__ = &__nvoc_thunk_RsResource_i2capiAddAdditionalDependants; + pThis->__i2capiInternalControlForward__ = &__nvoc_thunk_GpuResource_i2capiInternalControlForward; - pThis->__i2capiGetRefCount__ = &__nvoc_thunk_RsResource_i2capiGetRefCount; + pThis->__i2capiUnmapFrom__ = &__nvoc_thunk_RsResource_i2capiUnmapFrom; - pThis->__i2capiCheckMemInterUnmap__ = &__nvoc_thunk_RmResource_i2capiCheckMemInterUnmap; + pThis->__i2capiControl_Epilogue__ = &__nvoc_thunk_RmResource_i2capiControl_Epilogue; - pThis->__i2capiMapTo__ = &__nvoc_thunk_RsResource_i2capiMapTo; + pThis->__i2capiControlLookup__ = &__nvoc_thunk_RsResource_i2capiControlLookup; - pThis->__i2capiControl_Prologue__ = &__nvoc_thunk_RmResource_i2capiControl_Prologue; + pThis->__i2capiGetInternalObjectHandle__ = &__nvoc_thunk_GpuResource_i2capiGetInternalObjectHandle; - pThis->__i2capiGetRegBaseOffsetAndSize__ = &__nvoc_thunk_GpuResource_i2capiGetRegBaseOffsetAndSize; + pThis->__i2capiControl__ = &__nvoc_thunk_GpuResource_i2capiControl; - pThis->__i2capiCanCopy__ = &__nvoc_thunk_RsResource_i2capiCanCopy; + pThis->__i2capiUnmap__ = &__nvoc_thunk_GpuResource_i2capiUnmap; - pThis->__i2capiInternalControlForward__ = &__nvoc_thunk_GpuResource_i2capiInternalControlForward; + pThis->__i2capiGetMemInterMapParams__ = &__nvoc_thunk_RmResource_i2capiGetMemInterMapParams; - pThis->__i2capiPreDestruct__ = &__nvoc_thunk_RsResource_i2capiPreDestruct; + pThis->__i2capiGetMemoryMappingDescriptor__ = &__nvoc_thunk_RmResource_i2capiGetMemoryMappingDescriptor; - pThis->__i2capiUnmapFrom__ = &__nvoc_thunk_RsResource_i2capiUnmapFrom; + pThis->__i2capiControlFilter__ = &__nvoc_thunk_RsResource_i2capiControlFilter; - pThis->__i2capiIsDuplicate__ = &__nvoc_thunk_RsResource_i2capiIsDuplicate; + pThis->__i2capiControlSerialization_Prologue__ = &__nvoc_thunk_RmResource_i2capiControlSerialization_Prologue; - pThis->__i2capiControl_Epilogue__ = &__nvoc_thunk_RmResource_i2capiControl_Epilogue; + pThis->__i2capiCanCopy__ = &__nvoc_thunk_RsResource_i2capiCanCopy; - pThis->__i2capiControlLookup__ = &__nvoc_thunk_RsResource_i2capiControlLookup; + pThis->__i2capiPreDestruct__ = &__nvoc_thunk_RsResource_i2capiPreDestruct; + + pThis->__i2capiIsDuplicate__ = &__nvoc_thunk_RsResource_i2capiIsDuplicate; + + pThis->__i2capiControlSerialization_Epilogue__ = &__nvoc_thunk_RmResource_i2capiControlSerialization_Epilogue; pThis->__i2capiMap__ = &__nvoc_thunk_GpuResource_i2capiMap; @@ -396,13 +408,16 @@ Object *pParentObj; I2cApi *pThis; - pThis = portMemAllocNonPaged(sizeof(I2cApi)); - if (pThis == NULL) return NV_ERR_NO_MEMORY; + status = __nvoc_handleObjCreateMemAlloc(createFlags, sizeof(I2cApi), (void**)&pThis, (void**)ppThis); + if (status != NV_OK) + return status; portMemSet(pThis, 0, sizeof(I2cApi)); __nvoc_initRtti(staticCast(pThis, Dynamic), &__nvoc_class_def_I2cApi); + pThis->__nvoc_base_GpuResource.__nvoc_base_RmResource.__nvoc_base_RsResource.__nvoc_base_Object.createFlags = createFlags; + if (pParent != NULL && !(createFlags & NVOC_OBJ_CREATE_FLAGS_PARENT_HALSPEC_ONLY)) { pParentObj = dynamicCast(pParent, Object); @@ -418,11 +433,17 @@ if (status != NV_OK) goto __nvoc_objCreate_I2cApi_cleanup; *ppThis = pThis; + return NV_OK; __nvoc_objCreate_I2cApi_cleanup: // do not call destructors here since the constructor already called them - portMemFree(pThis); + if (createFlags & NVOC_OBJ_CREATE_FLAGS_IN_PLACE_CONSTRUCT) + portMemSet(pThis, 0, sizeof(I2cApi)); + else + portMemFree(pThis); + + // coverity[leaked_storage:FALSE] return status; } diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/generated/g_i2c_api_nvoc.h nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_i2c_api_nvoc.h --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/generated/g_i2c_api_nvoc.h 2023-10-25 20:27:02.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_i2c_api_nvoc.h 2024-03-05 22:18:19.000000000 +0000 @@ -61,26 +61,28 @@ NV_STATUS (*__i2capiCtrlCmdI2cTableGetDevInfo__)(struct I2cApi *, NV402C_CTRL_I2C_TABLE_GET_DEV_INFO_PARAMS *); NV_STATUS (*__i2capiCtrlCmdI2cTransaction__)(struct I2cApi *, NV402C_CTRL_I2C_TRANSACTION_PARAMS *); NvBool (*__i2capiShareCallback__)(struct I2cApi *, struct RsClient *, struct RsResourceRef *, RS_SHARE_POLICY *); - NV_STATUS (*__i2capiControl__)(struct I2cApi *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); - NV_STATUS (*__i2capiUnmap__)(struct I2cApi *, struct CALL_CONTEXT *, struct RsCpuMapping *); - NV_STATUS (*__i2capiGetMemInterMapParams__)(struct I2cApi *, RMRES_MEM_INTER_MAP_PARAMS *); - NV_STATUS (*__i2capiGetMemoryMappingDescriptor__)(struct I2cApi *, struct MEMORY_DESCRIPTOR **); - NV_STATUS (*__i2capiGetMapAddrSpace__)(struct I2cApi *, struct CALL_CONTEXT *, NvU32, NV_ADDRESS_SPACE *); - NvHandle (*__i2capiGetInternalObjectHandle__)(struct I2cApi *); - NV_STATUS (*__i2capiControlFilter__)(struct I2cApi *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); - void (*__i2capiAddAdditionalDependants__)(struct RsClient *, struct I2cApi *, RsResourceRef *); - NvU32 (*__i2capiGetRefCount__)(struct I2cApi *); NV_STATUS (*__i2capiCheckMemInterUnmap__)(struct I2cApi *, NvBool); NV_STATUS (*__i2capiMapTo__)(struct I2cApi *, RS_RES_MAP_TO_PARAMS *); + NV_STATUS (*__i2capiGetMapAddrSpace__)(struct I2cApi *, struct CALL_CONTEXT *, NvU32, NV_ADDRESS_SPACE *); + NvU32 (*__i2capiGetRefCount__)(struct I2cApi *); + void (*__i2capiAddAdditionalDependants__)(struct RsClient *, struct I2cApi *, RsResourceRef *); NV_STATUS (*__i2capiControl_Prologue__)(struct I2cApi *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); NV_STATUS (*__i2capiGetRegBaseOffsetAndSize__)(struct I2cApi *, struct OBJGPU *, NvU32 *, NvU32 *); - NvBool (*__i2capiCanCopy__)(struct I2cApi *); NV_STATUS (*__i2capiInternalControlForward__)(struct I2cApi *, NvU32, void *, NvU32); - void (*__i2capiPreDestruct__)(struct I2cApi *); NV_STATUS (*__i2capiUnmapFrom__)(struct I2cApi *, RS_RES_UNMAP_FROM_PARAMS *); - NV_STATUS (*__i2capiIsDuplicate__)(struct I2cApi *, NvHandle, NvBool *); void (*__i2capiControl_Epilogue__)(struct I2cApi *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); NV_STATUS (*__i2capiControlLookup__)(struct I2cApi *, struct RS_RES_CONTROL_PARAMS_INTERNAL *, const struct NVOC_EXPORTED_METHOD_DEF **); + NvHandle (*__i2capiGetInternalObjectHandle__)(struct I2cApi *); + NV_STATUS (*__i2capiControl__)(struct I2cApi *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); + NV_STATUS (*__i2capiUnmap__)(struct I2cApi *, struct CALL_CONTEXT *, struct RsCpuMapping *); + NV_STATUS (*__i2capiGetMemInterMapParams__)(struct I2cApi *, RMRES_MEM_INTER_MAP_PARAMS *); + NV_STATUS (*__i2capiGetMemoryMappingDescriptor__)(struct I2cApi *, struct MEMORY_DESCRIPTOR **); + NV_STATUS (*__i2capiControlFilter__)(struct I2cApi *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); + NV_STATUS (*__i2capiControlSerialization_Prologue__)(struct I2cApi *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); + NvBool (*__i2capiCanCopy__)(struct I2cApi *); + void (*__i2capiPreDestruct__)(struct I2cApi *); + NV_STATUS (*__i2capiIsDuplicate__)(struct I2cApi *, NvHandle, NvBool *); + void (*__i2capiControlSerialization_Epilogue__)(struct I2cApi *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); NV_STATUS (*__i2capiMap__)(struct I2cApi *, struct CALL_CONTEXT *, struct RS_CPU_MAP_PARAMS *, struct RsCpuMapping *); NvBool (*__i2capiAccessCallback__)(struct I2cApi *, struct RsClient *, void *, RsAccessRight); }; @@ -119,26 +121,28 @@ #define i2capiCtrlCmdI2cTableGetDevInfo(pI2cApi, pParams) i2capiCtrlCmdI2cTableGetDevInfo_DISPATCH(pI2cApi, pParams) #define i2capiCtrlCmdI2cTransaction(pI2cApi, pParams) i2capiCtrlCmdI2cTransaction_DISPATCH(pI2cApi, pParams) #define i2capiShareCallback(pGpuResource, pInvokingClient, pParentRef, pSharePolicy) i2capiShareCallback_DISPATCH(pGpuResource, pInvokingClient, pParentRef, pSharePolicy) -#define i2capiControl(pGpuResource, pCallContext, pParams) i2capiControl_DISPATCH(pGpuResource, pCallContext, pParams) -#define i2capiUnmap(pGpuResource, pCallContext, pCpuMapping) i2capiUnmap_DISPATCH(pGpuResource, pCallContext, pCpuMapping) -#define i2capiGetMemInterMapParams(pRmResource, pParams) i2capiGetMemInterMapParams_DISPATCH(pRmResource, pParams) -#define i2capiGetMemoryMappingDescriptor(pRmResource, ppMemDesc) i2capiGetMemoryMappingDescriptor_DISPATCH(pRmResource, ppMemDesc) -#define i2capiGetMapAddrSpace(pGpuResource, pCallContext, mapFlags, pAddrSpace) i2capiGetMapAddrSpace_DISPATCH(pGpuResource, pCallContext, mapFlags, pAddrSpace) -#define i2capiGetInternalObjectHandle(pGpuResource) i2capiGetInternalObjectHandle_DISPATCH(pGpuResource) -#define i2capiControlFilter(pResource, pCallContext, pParams) i2capiControlFilter_DISPATCH(pResource, pCallContext, pParams) -#define i2capiAddAdditionalDependants(pClient, pResource, pReference) i2capiAddAdditionalDependants_DISPATCH(pClient, pResource, pReference) -#define i2capiGetRefCount(pResource) i2capiGetRefCount_DISPATCH(pResource) #define i2capiCheckMemInterUnmap(pRmResource, bSubdeviceHandleProvided) i2capiCheckMemInterUnmap_DISPATCH(pRmResource, bSubdeviceHandleProvided) #define i2capiMapTo(pResource, pParams) i2capiMapTo_DISPATCH(pResource, pParams) +#define i2capiGetMapAddrSpace(pGpuResource, pCallContext, mapFlags, pAddrSpace) i2capiGetMapAddrSpace_DISPATCH(pGpuResource, pCallContext, mapFlags, pAddrSpace) +#define i2capiGetRefCount(pResource) i2capiGetRefCount_DISPATCH(pResource) +#define i2capiAddAdditionalDependants(pClient, pResource, pReference) i2capiAddAdditionalDependants_DISPATCH(pClient, pResource, pReference) #define i2capiControl_Prologue(pResource, pCallContext, pParams) i2capiControl_Prologue_DISPATCH(pResource, pCallContext, pParams) #define i2capiGetRegBaseOffsetAndSize(pGpuResource, pGpu, pOffset, pSize) i2capiGetRegBaseOffsetAndSize_DISPATCH(pGpuResource, pGpu, pOffset, pSize) -#define i2capiCanCopy(pResource) i2capiCanCopy_DISPATCH(pResource) #define i2capiInternalControlForward(pGpuResource, command, pParams, size) i2capiInternalControlForward_DISPATCH(pGpuResource, command, pParams, size) -#define i2capiPreDestruct(pResource) i2capiPreDestruct_DISPATCH(pResource) #define i2capiUnmapFrom(pResource, pParams) i2capiUnmapFrom_DISPATCH(pResource, pParams) -#define i2capiIsDuplicate(pResource, hMemory, pDuplicate) i2capiIsDuplicate_DISPATCH(pResource, hMemory, pDuplicate) #define i2capiControl_Epilogue(pResource, pCallContext, pParams) i2capiControl_Epilogue_DISPATCH(pResource, pCallContext, pParams) #define i2capiControlLookup(pResource, pParams, ppEntry) i2capiControlLookup_DISPATCH(pResource, pParams, ppEntry) +#define i2capiGetInternalObjectHandle(pGpuResource) i2capiGetInternalObjectHandle_DISPATCH(pGpuResource) +#define i2capiControl(pGpuResource, pCallContext, pParams) i2capiControl_DISPATCH(pGpuResource, pCallContext, pParams) +#define i2capiUnmap(pGpuResource, pCallContext, pCpuMapping) i2capiUnmap_DISPATCH(pGpuResource, pCallContext, pCpuMapping) +#define i2capiGetMemInterMapParams(pRmResource, pParams) i2capiGetMemInterMapParams_DISPATCH(pRmResource, pParams) +#define i2capiGetMemoryMappingDescriptor(pRmResource, ppMemDesc) i2capiGetMemoryMappingDescriptor_DISPATCH(pRmResource, ppMemDesc) +#define i2capiControlFilter(pResource, pCallContext, pParams) i2capiControlFilter_DISPATCH(pResource, pCallContext, pParams) +#define i2capiControlSerialization_Prologue(pResource, pCallContext, pParams) i2capiControlSerialization_Prologue_DISPATCH(pResource, pCallContext, pParams) +#define i2capiCanCopy(pResource) i2capiCanCopy_DISPATCH(pResource) +#define i2capiPreDestruct(pResource) i2capiPreDestruct_DISPATCH(pResource) +#define i2capiIsDuplicate(pResource, hMemory, pDuplicate) i2capiIsDuplicate_DISPATCH(pResource, hMemory, pDuplicate) +#define i2capiControlSerialization_Epilogue(pResource, pCallContext, pParams) i2capiControlSerialization_Epilogue_DISPATCH(pResource, pCallContext, pParams) #define i2capiMap(pGpuResource, pCallContext, pParams, pCpuMapping) i2capiMap_DISPATCH(pGpuResource, pCallContext, pParams, pCpuMapping) #define i2capiAccessCallback(pResource, pInvokingClient, pAllocParams, accessRight) i2capiAccessCallback_DISPATCH(pResource, pInvokingClient, pAllocParams, accessRight) NV_STATUS i2capiCtrlCmdI2cGetPortInfo_IMPL(struct I2cApi *pI2cApi, NV402C_CTRL_I2C_GET_PORT_INFO_PARAMS *pParams); @@ -175,84 +179,92 @@ return pGpuResource->__i2capiShareCallback__(pGpuResource, pInvokingClient, pParentRef, pSharePolicy); } -static inline NV_STATUS i2capiControl_DISPATCH(struct I2cApi *pGpuResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { - return pGpuResource->__i2capiControl__(pGpuResource, pCallContext, pParams); +static inline NV_STATUS i2capiCheckMemInterUnmap_DISPATCH(struct I2cApi *pRmResource, NvBool bSubdeviceHandleProvided) { + return pRmResource->__i2capiCheckMemInterUnmap__(pRmResource, bSubdeviceHandleProvided); } -static inline NV_STATUS i2capiUnmap_DISPATCH(struct I2cApi *pGpuResource, struct CALL_CONTEXT *pCallContext, struct RsCpuMapping *pCpuMapping) { - return pGpuResource->__i2capiUnmap__(pGpuResource, pCallContext, pCpuMapping); +static inline NV_STATUS i2capiMapTo_DISPATCH(struct I2cApi *pResource, RS_RES_MAP_TO_PARAMS *pParams) { + return pResource->__i2capiMapTo__(pResource, pParams); } -static inline NV_STATUS i2capiGetMemInterMapParams_DISPATCH(struct I2cApi *pRmResource, RMRES_MEM_INTER_MAP_PARAMS *pParams) { - return pRmResource->__i2capiGetMemInterMapParams__(pRmResource, pParams); +static inline NV_STATUS i2capiGetMapAddrSpace_DISPATCH(struct I2cApi *pGpuResource, struct CALL_CONTEXT *pCallContext, NvU32 mapFlags, NV_ADDRESS_SPACE *pAddrSpace) { + return pGpuResource->__i2capiGetMapAddrSpace__(pGpuResource, pCallContext, mapFlags, pAddrSpace); } -static inline NV_STATUS i2capiGetMemoryMappingDescriptor_DISPATCH(struct I2cApi *pRmResource, struct MEMORY_DESCRIPTOR **ppMemDesc) { - return pRmResource->__i2capiGetMemoryMappingDescriptor__(pRmResource, ppMemDesc); +static inline NvU32 i2capiGetRefCount_DISPATCH(struct I2cApi *pResource) { + return pResource->__i2capiGetRefCount__(pResource); } -static inline NV_STATUS i2capiGetMapAddrSpace_DISPATCH(struct I2cApi *pGpuResource, struct CALL_CONTEXT *pCallContext, NvU32 mapFlags, NV_ADDRESS_SPACE *pAddrSpace) { - return pGpuResource->__i2capiGetMapAddrSpace__(pGpuResource, pCallContext, mapFlags, pAddrSpace); +static inline void i2capiAddAdditionalDependants_DISPATCH(struct RsClient *pClient, struct I2cApi *pResource, RsResourceRef *pReference) { + pResource->__i2capiAddAdditionalDependants__(pClient, pResource, pReference); } -static inline NvHandle i2capiGetInternalObjectHandle_DISPATCH(struct I2cApi *pGpuResource) { - return pGpuResource->__i2capiGetInternalObjectHandle__(pGpuResource); +static inline NV_STATUS i2capiControl_Prologue_DISPATCH(struct I2cApi *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return pResource->__i2capiControl_Prologue__(pResource, pCallContext, pParams); } -static inline NV_STATUS i2capiControlFilter_DISPATCH(struct I2cApi *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { - return pResource->__i2capiControlFilter__(pResource, pCallContext, pParams); +static inline NV_STATUS i2capiGetRegBaseOffsetAndSize_DISPATCH(struct I2cApi *pGpuResource, struct OBJGPU *pGpu, NvU32 *pOffset, NvU32 *pSize) { + return pGpuResource->__i2capiGetRegBaseOffsetAndSize__(pGpuResource, pGpu, pOffset, pSize); } -static inline void i2capiAddAdditionalDependants_DISPATCH(struct RsClient *pClient, struct I2cApi *pResource, RsResourceRef *pReference) { - pResource->__i2capiAddAdditionalDependants__(pClient, pResource, pReference); +static inline NV_STATUS i2capiInternalControlForward_DISPATCH(struct I2cApi *pGpuResource, NvU32 command, void *pParams, NvU32 size) { + return pGpuResource->__i2capiInternalControlForward__(pGpuResource, command, pParams, size); } -static inline NvU32 i2capiGetRefCount_DISPATCH(struct I2cApi *pResource) { - return pResource->__i2capiGetRefCount__(pResource); +static inline NV_STATUS i2capiUnmapFrom_DISPATCH(struct I2cApi *pResource, RS_RES_UNMAP_FROM_PARAMS *pParams) { + return pResource->__i2capiUnmapFrom__(pResource, pParams); } -static inline NV_STATUS i2capiCheckMemInterUnmap_DISPATCH(struct I2cApi *pRmResource, NvBool bSubdeviceHandleProvided) { - return pRmResource->__i2capiCheckMemInterUnmap__(pRmResource, bSubdeviceHandleProvided); +static inline void i2capiControl_Epilogue_DISPATCH(struct I2cApi *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + pResource->__i2capiControl_Epilogue__(pResource, pCallContext, pParams); } -static inline NV_STATUS i2capiMapTo_DISPATCH(struct I2cApi *pResource, RS_RES_MAP_TO_PARAMS *pParams) { - return pResource->__i2capiMapTo__(pResource, pParams); +static inline NV_STATUS i2capiControlLookup_DISPATCH(struct I2cApi *pResource, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams, const struct NVOC_EXPORTED_METHOD_DEF **ppEntry) { + return pResource->__i2capiControlLookup__(pResource, pParams, ppEntry); } -static inline NV_STATUS i2capiControl_Prologue_DISPATCH(struct I2cApi *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { - return pResource->__i2capiControl_Prologue__(pResource, pCallContext, pParams); +static inline NvHandle i2capiGetInternalObjectHandle_DISPATCH(struct I2cApi *pGpuResource) { + return pGpuResource->__i2capiGetInternalObjectHandle__(pGpuResource); } -static inline NV_STATUS i2capiGetRegBaseOffsetAndSize_DISPATCH(struct I2cApi *pGpuResource, struct OBJGPU *pGpu, NvU32 *pOffset, NvU32 *pSize) { - return pGpuResource->__i2capiGetRegBaseOffsetAndSize__(pGpuResource, pGpu, pOffset, pSize); +static inline NV_STATUS i2capiControl_DISPATCH(struct I2cApi *pGpuResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return pGpuResource->__i2capiControl__(pGpuResource, pCallContext, pParams); } -static inline NvBool i2capiCanCopy_DISPATCH(struct I2cApi *pResource) { - return pResource->__i2capiCanCopy__(pResource); +static inline NV_STATUS i2capiUnmap_DISPATCH(struct I2cApi *pGpuResource, struct CALL_CONTEXT *pCallContext, struct RsCpuMapping *pCpuMapping) { + return pGpuResource->__i2capiUnmap__(pGpuResource, pCallContext, pCpuMapping); } -static inline NV_STATUS i2capiInternalControlForward_DISPATCH(struct I2cApi *pGpuResource, NvU32 command, void *pParams, NvU32 size) { - return pGpuResource->__i2capiInternalControlForward__(pGpuResource, command, pParams, size); +static inline NV_STATUS i2capiGetMemInterMapParams_DISPATCH(struct I2cApi *pRmResource, RMRES_MEM_INTER_MAP_PARAMS *pParams) { + return pRmResource->__i2capiGetMemInterMapParams__(pRmResource, pParams); } -static inline void i2capiPreDestruct_DISPATCH(struct I2cApi *pResource) { - pResource->__i2capiPreDestruct__(pResource); +static inline NV_STATUS i2capiGetMemoryMappingDescriptor_DISPATCH(struct I2cApi *pRmResource, struct MEMORY_DESCRIPTOR **ppMemDesc) { + return pRmResource->__i2capiGetMemoryMappingDescriptor__(pRmResource, ppMemDesc); } -static inline NV_STATUS i2capiUnmapFrom_DISPATCH(struct I2cApi *pResource, RS_RES_UNMAP_FROM_PARAMS *pParams) { - return pResource->__i2capiUnmapFrom__(pResource, pParams); +static inline NV_STATUS i2capiControlFilter_DISPATCH(struct I2cApi *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return pResource->__i2capiControlFilter__(pResource, pCallContext, pParams); } -static inline NV_STATUS i2capiIsDuplicate_DISPATCH(struct I2cApi *pResource, NvHandle hMemory, NvBool *pDuplicate) { - return pResource->__i2capiIsDuplicate__(pResource, hMemory, pDuplicate); +static inline NV_STATUS i2capiControlSerialization_Prologue_DISPATCH(struct I2cApi *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return pResource->__i2capiControlSerialization_Prologue__(pResource, pCallContext, pParams); } -static inline void i2capiControl_Epilogue_DISPATCH(struct I2cApi *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { - pResource->__i2capiControl_Epilogue__(pResource, pCallContext, pParams); +static inline NvBool i2capiCanCopy_DISPATCH(struct I2cApi *pResource) { + return pResource->__i2capiCanCopy__(pResource); } -static inline NV_STATUS i2capiControlLookup_DISPATCH(struct I2cApi *pResource, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams, const struct NVOC_EXPORTED_METHOD_DEF **ppEntry) { - return pResource->__i2capiControlLookup__(pResource, pParams, ppEntry); +static inline void i2capiPreDestruct_DISPATCH(struct I2cApi *pResource) { + pResource->__i2capiPreDestruct__(pResource); +} + +static inline NV_STATUS i2capiIsDuplicate_DISPATCH(struct I2cApi *pResource, NvHandle hMemory, NvBool *pDuplicate) { + return pResource->__i2capiIsDuplicate__(pResource, hMemory, pDuplicate); +} + +static inline void i2capiControlSerialization_Epilogue_DISPATCH(struct I2cApi *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + pResource->__i2capiControlSerialization_Epilogue__(pResource, pCallContext, pParams); } static inline NV_STATUS i2capiMap_DISPATCH(struct I2cApi *pGpuResource, struct CALL_CONTEXT *pCallContext, struct RS_CPU_MAP_PARAMS *pParams, struct RsCpuMapping *pCpuMapping) { diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/generated/g_intr_nvoc.c nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_intr_nvoc.c --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/generated/g_intr_nvoc.c 2023-10-25 20:27:02.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_intr_nvoc.c 2024-03-05 22:18:19.000000000 +0000 @@ -90,10 +90,6 @@ return intrStateUnload(pGpu, (struct Intr *)(((unsigned char *)pIntr) - __nvoc_rtti_Intr_OBJENGSTATE.offset), arg0); } -static NV_STATUS __nvoc_thunk_OBJENGSTATE_intrReconcileTunableState(POBJGPU pGpu, struct Intr *pEngstate, void *pTunableState) { - return engstateReconcileTunableState(pGpu, (struct OBJENGSTATE *)(((unsigned char *)pEngstate) + __nvoc_rtti_Intr_OBJENGSTATE.offset), pTunableState); -} - static NV_STATUS __nvoc_thunk_OBJENGSTATE_intrStatePreLoad(POBJGPU pGpu, struct Intr *pEngstate, NvU32 arg0) { return engstateStatePreLoad(pGpu, (struct OBJENGSTATE *)(((unsigned char *)pEngstate) + __nvoc_rtti_Intr_OBJENGSTATE.offset), arg0); } @@ -118,30 +114,10 @@ return engstateStatePreInitUnlocked(pGpu, (struct OBJENGSTATE *)(((unsigned char *)pEngstate) + __nvoc_rtti_Intr_OBJENGSTATE.offset)); } -static NV_STATUS __nvoc_thunk_OBJENGSTATE_intrGetTunableState(POBJGPU pGpu, struct Intr *pEngstate, void *pTunableState) { - return engstateGetTunableState(pGpu, (struct OBJENGSTATE *)(((unsigned char *)pEngstate) + __nvoc_rtti_Intr_OBJENGSTATE.offset), pTunableState); -} - -static NV_STATUS __nvoc_thunk_OBJENGSTATE_intrCompareTunableState(POBJGPU pGpu, struct Intr *pEngstate, void *pTunables1, void *pTunables2) { - return engstateCompareTunableState(pGpu, (struct OBJENGSTATE *)(((unsigned char *)pEngstate) + __nvoc_rtti_Intr_OBJENGSTATE.offset), pTunables1, pTunables2); -} - -static void __nvoc_thunk_OBJENGSTATE_intrFreeTunableState(POBJGPU pGpu, struct Intr *pEngstate, void *pTunableState) { - engstateFreeTunableState(pGpu, (struct OBJENGSTATE *)(((unsigned char *)pEngstate) + __nvoc_rtti_Intr_OBJENGSTATE.offset), pTunableState); -} - static NV_STATUS __nvoc_thunk_OBJENGSTATE_intrStatePostLoad(POBJGPU pGpu, struct Intr *pEngstate, NvU32 arg0) { return engstateStatePostLoad(pGpu, (struct OBJENGSTATE *)(((unsigned char *)pEngstate) + __nvoc_rtti_Intr_OBJENGSTATE.offset), arg0); } -static NV_STATUS __nvoc_thunk_OBJENGSTATE_intrAllocTunableState(POBJGPU pGpu, struct Intr *pEngstate, void **ppTunableState) { - return engstateAllocTunableState(pGpu, (struct OBJENGSTATE *)(((unsigned char *)pEngstate) + __nvoc_rtti_Intr_OBJENGSTATE.offset), ppTunableState); -} - -static NV_STATUS __nvoc_thunk_OBJENGSTATE_intrSetTunableState(POBJGPU pGpu, struct Intr *pEngstate, void *pTunableState) { - return engstateSetTunableState(pGpu, (struct OBJENGSTATE *)(((unsigned char *)pEngstate) + __nvoc_rtti_Intr_OBJENGSTATE.offset), pTunableState); -} - static NvBool __nvoc_thunk_OBJENGSTATE_intrIsPresent(POBJGPU pGpu, struct Intr *pEngstate) { return engstateIsPresent(pGpu, (struct OBJENGSTATE *)(((unsigned char *)pEngstate) + __nvoc_rtti_Intr_OBJENGSTATE.offset)); } @@ -217,11 +193,16 @@ pThis->bDefaultNonstallNotify = ((NvBool)(0 == 0)); } - pThis->bTablesPopulated = ((NvBool)(0 != 0)); - - pThis->numPhysicalEntries = 0; - - pThis->numKernelEntries = 0; + // Hal field -- bUseLegacyVectorAssignment + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ + { + pThis->bUseLegacyVectorAssignment = ((NvBool)(0 == 0)); + } + // default + else + { + pThis->bUseLegacyVectorAssignment = ((NvBool)(0 == 0)); + } } NV_STATUS __nvoc_ctor_OBJENGSTATE(OBJENGSTATE* ); @@ -263,7 +244,7 @@ { pThis->__intrDecodeStallIntrEn__ = &intrDecodeStallIntrEn_TU102; } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x11f0fc00UL) )) /* ChipHal: GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 | GH100 */ + else { pThis->__intrDecodeStallIntrEn__ = &intrDecodeStallIntrEn_4a4dee; } @@ -273,7 +254,7 @@ { pThis->__intrGetNonStallBaseVector__ = &intrGetNonStallBaseVector_TU102; } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x11f0fc00UL) )) /* ChipHal: GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 | GH100 */ + else { pThis->__intrGetNonStallBaseVector__ = &intrGetNonStallBaseVector_c067f9; } @@ -283,7 +264,7 @@ { pThis->__intrGetUvmSharedLeafEnDisableMask__ = &intrGetUvmSharedLeafEnDisableMask_TU102; } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x11f0fc00UL) )) /* ChipHal: GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 | GH100 */ + else { pThis->__intrGetUvmSharedLeafEnDisableMask__ = &intrGetUvmSharedLeafEnDisableMask_GA100; } @@ -304,7 +285,7 @@ { pThis->__intrReadRegTopEnSet__ = &intrReadRegTopEnSet_TU102; } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x11f0f800UL) )) /* ChipHal: GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 | GH100 */ + else { pThis->__intrReadRegTopEnSet__ = &intrReadRegTopEnSet_GA102; } @@ -314,7 +295,7 @@ { pThis->__intrWriteRegTopEnSet__ = &intrWriteRegTopEnSet_TU102; } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x11f0f800UL) )) /* ChipHal: GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 | GH100 */ + else { pThis->__intrWriteRegTopEnSet__ = &intrWriteRegTopEnSet_GA102; } @@ -324,59 +305,49 @@ { pThis->__intrWriteRegTopEnClear__ = &intrWriteRegTopEnClear_TU102; } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x11f0f800UL) )) /* ChipHal: GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 | GH100 */ + else { pThis->__intrWriteRegTopEnClear__ = &intrWriteRegTopEnClear_GA102; } - // Hal function -- intrGetStallSubtreeLast - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x01f0ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 */ - { - pThis->__intrGetStallSubtreeLast__ = &intrGetStallSubtreeLast_TU102; - } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ - { - pThis->__intrGetStallSubtreeLast__ = &intrGetStallSubtreeLast_GH100; - } - // Hal function -- intrGetNumLeaves - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x01f0ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 */ + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ { - pThis->__intrGetNumLeaves__ = &intrGetNumLeaves_TU102; + pThis->__intrGetNumLeaves__ = &intrGetNumLeaves_GH100; } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ + else { - pThis->__intrGetNumLeaves__ = &intrGetNumLeaves_GH100; + pThis->__intrGetNumLeaves__ = &intrGetNumLeaves_TU102; } // Hal function -- intrGetLeafSize - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x01f0ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 */ + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ { - pThis->__intrGetLeafSize__ = &intrGetLeafSize_TU102; + pThis->__intrGetLeafSize__ = &intrGetLeafSize_GH100; } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ + else { - pThis->__intrGetLeafSize__ = &intrGetLeafSize_GH100; + pThis->__intrGetLeafSize__ = &intrGetLeafSize_TU102; } // Hal function -- intrGetIntrTopNonStallMask - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x01f0ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 */ + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ { - pThis->__intrGetIntrTopNonStallMask__ = &intrGetIntrTopNonStallMask_TU102; + pThis->__intrGetIntrTopNonStallMask__ = &intrGetIntrTopNonStallMask_GH100; } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ + else { - pThis->__intrGetIntrTopNonStallMask__ = &intrGetIntrTopNonStallMask_GH100; + pThis->__intrGetIntrTopNonStallMask__ = &intrGetIntrTopNonStallMask_TU102; } // Hal function -- intrSanityCheckEngineIntrStallVector - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x01f0fc00UL) )) /* ChipHal: GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 */ + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ { - pThis->__intrSanityCheckEngineIntrStallVector__ = &intrSanityCheckEngineIntrStallVector_GA100; + pThis->__intrSanityCheckEngineIntrStallVector__ = &intrSanityCheckEngineIntrStallVector_GH100; } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ + else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x01f0fc00UL) )) /* ChipHal: GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 */ { - pThis->__intrSanityCheckEngineIntrStallVector__ = &intrSanityCheckEngineIntrStallVector_GH100; + pThis->__intrSanityCheckEngineIntrStallVector__ = &intrSanityCheckEngineIntrStallVector_GA100; } // default else @@ -385,13 +356,13 @@ } // Hal function -- intrSanityCheckEngineIntrNotificationVector - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x01f0fc00UL) )) /* ChipHal: GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 */ + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ { - pThis->__intrSanityCheckEngineIntrNotificationVector__ = &intrSanityCheckEngineIntrNotificationVector_GA100; + pThis->__intrSanityCheckEngineIntrNotificationVector__ = &intrSanityCheckEngineIntrNotificationVector_GH100; } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ + else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x01f0fc00UL) )) /* ChipHal: GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 */ { - pThis->__intrSanityCheckEngineIntrNotificationVector__ = &intrSanityCheckEngineIntrNotificationVector_GH100; + pThis->__intrSanityCheckEngineIntrNotificationVector__ = &intrSanityCheckEngineIntrNotificationVector_GA100; } // default else @@ -400,23 +371,17 @@ } // Hal function -- intrStateLoad - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x11f0ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 | GH100 */ - { - pThis->__intrStateLoad__ = &intrStateLoad_TU102; - } + pThis->__intrStateLoad__ = &intrStateLoad_TU102; // Hal function -- intrStateUnload - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x11f0ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 | GH100 */ - { - pThis->__intrStateUnload__ = &intrStateUnload_TU102; - } + pThis->__intrStateUnload__ = &intrStateUnload_TU102; // Hal function -- intrSetIntrMask if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x000003e0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 */ { pThis->__intrSetIntrMask__ = &intrSetIntrMask_GP100; } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x11f0fc00UL) )) /* ChipHal: GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 | GH100 */ + else { pThis->__intrSetIntrMask__ = &intrSetIntrMask_46f6a7; } @@ -426,7 +391,7 @@ { pThis->__intrSetIntrEnInHw__ = &intrSetIntrEnInHw_GP100; } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x11f0fc00UL) )) /* ChipHal: GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 | GH100 */ + else { pThis->__intrSetIntrEnInHw__ = &intrSetIntrEnInHw_d44104; } @@ -436,7 +401,7 @@ { pThis->__intrGetIntrEnFromHw__ = &intrGetIntrEnFromHw_GP100; } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x11f0fc00UL) )) /* ChipHal: GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 | GH100 */ + else { pThis->__intrGetIntrEnFromHw__ = &intrGetIntrEnFromHw_b2b553; } @@ -453,8 +418,6 @@ pThis->__nvoc_base_OBJENGSTATE.__engstateStateUnload__ = &__nvoc_thunk_Intr_engstateStateUnload; - pThis->__intrReconcileTunableState__ = &__nvoc_thunk_OBJENGSTATE_intrReconcileTunableState; - pThis->__intrStatePreLoad__ = &__nvoc_thunk_OBJENGSTATE_intrStatePreLoad; pThis->__intrStatePostUnload__ = &__nvoc_thunk_OBJENGSTATE_intrStatePostUnload; @@ -467,18 +430,8 @@ pThis->__intrStatePreInitUnlocked__ = &__nvoc_thunk_OBJENGSTATE_intrStatePreInitUnlocked; - pThis->__intrGetTunableState__ = &__nvoc_thunk_OBJENGSTATE_intrGetTunableState; - - pThis->__intrCompareTunableState__ = &__nvoc_thunk_OBJENGSTATE_intrCompareTunableState; - - pThis->__intrFreeTunableState__ = &__nvoc_thunk_OBJENGSTATE_intrFreeTunableState; - pThis->__intrStatePostLoad__ = &__nvoc_thunk_OBJENGSTATE_intrStatePostLoad; - pThis->__intrAllocTunableState__ = &__nvoc_thunk_OBJENGSTATE_intrAllocTunableState; - - pThis->__intrSetTunableState__ = &__nvoc_thunk_OBJENGSTATE_intrSetTunableState; - pThis->__intrIsPresent__ = &__nvoc_thunk_OBJENGSTATE_intrIsPresent; } @@ -501,13 +454,16 @@ Intr *pThis; RmHalspecOwner *pRmhalspecowner; - pThis = portMemAllocNonPaged(sizeof(Intr)); - if (pThis == NULL) return NV_ERR_NO_MEMORY; + status = __nvoc_handleObjCreateMemAlloc(createFlags, sizeof(Intr), (void**)&pThis, (void**)ppThis); + if (status != NV_OK) + return status; portMemSet(pThis, 0, sizeof(Intr)); __nvoc_initRtti(staticCast(pThis, Dynamic), &__nvoc_class_def_Intr); + pThis->__nvoc_base_OBJENGSTATE.__nvoc_base_Object.createFlags = createFlags; + if (pParent != NULL && !(createFlags & NVOC_OBJ_CREATE_FLAGS_PARENT_HALSPEC_ONLY)) { pParentObj = dynamicCast(pParent, Object); @@ -527,11 +483,17 @@ if (status != NV_OK) goto __nvoc_objCreate_Intr_cleanup; *ppThis = pThis; + return NV_OK; __nvoc_objCreate_Intr_cleanup: // do not call destructors here since the constructor already called them - portMemFree(pThis); + if (createFlags & NVOC_OBJ_CREATE_FLAGS_IN_PLACE_CONSTRUCT) + portMemSet(pThis, 0, sizeof(Intr)); + else + portMemFree(pThis); + + // coverity[leaked_storage:FALSE] return status; } diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/generated/g_intr_nvoc.h nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_intr_nvoc.h --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/generated/g_intr_nvoc.h 2023-10-25 20:27:02.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_intr_nvoc.h 2024-03-05 22:18:19.000000000 +0000 @@ -7,7 +7,7 @@ #endif /* - * SPDX-FileCopyrightText: Copyright (c) 2006-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2006-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -34,14 +34,21 @@ #ifndef INTR_H #define INTR_H -#include "gpu/gpu.h" -#include "gpu/eng_state.h" -#include "nvoc/utility.h" -#include "utils/nvbitvector.h" -#include "dev_ctrl_defines.h" +#include "kernel/gpu/eng_state.h" +#include "kernel/gpu/gpu.h" #include "kernel/gpu/intr/engine_idx.h" +#include "kernel/gpu/intr/intr_common.h" #include "kernel/gpu/intr/intr_service.h" +#include "ctrl/ctrl2080/ctrl2080internal.h" + +#include "dev_ctrl_defines.h" +#include "libraries/containers/list.h" +#include "libraries/containers/vector.h" +#include "libraries/nvoc/utility.h" +#include "libraries/utils/nvbitvector.h" + + // // Interrupt Type // @@ -79,34 +86,13 @@ * unavailable */ NvU32 intrVectorNonStall; - /** Boolean set to NV_TRUE if Nonstalling interrupt is disabled in CTRL - * interrupt tree (Turing+). This may change to Enum in future. We are - * moving towards the direction where GSP-RM is fully aware of MC interrupt - * table and it provisions a subset of entries to CPU RM. - */ - NvBool bDisableNonStall; } INTR_TABLE_ENTRY; #define INTR_TABLE_MAX_INTRS_PER_ENTRY 6 -// -// The max number of interrupts we can fit in the dynamically populated, -// but statically sized, interrupt table. -// -#define INTR_TABLE_MAX_STATIC_PHYSICAL_INTRS 19 -#define INTR_TABLE_MAX_STATIC_KERNEL_INTRS 17 - -#define POPULATE_INTR_TABLE(pTable, numEntries, localMcEngineIdxs, localIntrVectors, localCount, localMax) \ -NV_ASSERT(numEntries + localCount <= localMax); \ -for (i = 0; i < localCount; i++) \ -{ \ - (pTable)[(numEntries)].mcEngine = (localMcEngineIdxs)[i]; \ - (pTable)[(numEntries)].pmcIntrMask = NV_PMC_INTR_INVALID_MASK; \ - (pTable)[(numEntries)].intrVector = (intrVectors)[i]; \ - (pTable)[(numEntries)].intrVectorNonStall = NV_INTR_VECTOR_INVALID; \ - numEntries++; \ -} +MAKE_VECTOR(InterruptTable, INTR_TABLE_ENTRY); +// // Default value for intrStuckThreshold #define INTR_STUCK_THRESHOLD 1000 @@ -183,11 +169,26 @@ MC_ENGINE_BITVECTOR intrMask; } INTR_MASK_CTX; + // // IntrMask Locking Flag Defines // #define INTR_MASK_FLAGS_ISR_SKIP_MASK_UPDATE NVBIT(0) + +struct Device; + +#ifndef __NVOC_CLASS_Device_TYPEDEF__ +#define __NVOC_CLASS_Device_TYPEDEF__ +typedef struct Device Device; +#endif /* __NVOC_CLASS_Device_TYPEDEF__ */ + +#ifndef __nvoc_class_id_Device +#define __nvoc_class_id_Device 0xe0ac20 +#endif /* __nvoc_class_id_Device */ + + + #ifdef NVOC_INTR_H_PRIVATE_ACCESS_ALLOWED #define PRIVATE_FIELD(x) x #else @@ -210,10 +211,9 @@ NvU32 (*__intrReadRegTopEnSet__)(OBJGPU *, struct Intr *, NvU32, struct THREAD_STATE_NODE *); void (*__intrWriteRegTopEnSet__)(OBJGPU *, struct Intr *, NvU32, NvU32, struct THREAD_STATE_NODE *); void (*__intrWriteRegTopEnClear__)(OBJGPU *, struct Intr *, NvU32, NvU32, struct THREAD_STATE_NODE *); - NvU32 (*__intrGetStallSubtreeLast__)(OBJGPU *, struct Intr *); NvU32 (*__intrGetNumLeaves__)(OBJGPU *, struct Intr *); NvU32 (*__intrGetLeafSize__)(OBJGPU *, struct Intr *); - NvU32 (*__intrGetIntrTopNonStallMask__)(OBJGPU *, struct Intr *); + NvU64 (*__intrGetIntrTopNonStallMask__)(OBJGPU *, struct Intr *); void (*__intrSanityCheckEngineIntrStallVector__)(OBJGPU *, struct Intr *, NvU32, NvU16); void (*__intrSanityCheckEngineIntrNotificationVector__)(OBJGPU *, struct Intr *, NvU32, NvU16); NV_STATUS (*__intrStateLoad__)(OBJGPU *, struct Intr *, NvU32); @@ -221,19 +221,13 @@ NV_STATUS (*__intrSetIntrMask__)(OBJGPU *, struct Intr *, union MC_ENGINE_BITVECTOR *, struct THREAD_STATE_NODE *); void (*__intrSetIntrEnInHw__)(OBJGPU *, struct Intr *, NvU32, struct THREAD_STATE_NODE *); NvU32 (*__intrGetIntrEnFromHw__)(OBJGPU *, struct Intr *, struct THREAD_STATE_NODE *); - NV_STATUS (*__intrReconcileTunableState__)(POBJGPU, struct Intr *, void *); NV_STATUS (*__intrStatePreLoad__)(POBJGPU, struct Intr *, NvU32); NV_STATUS (*__intrStatePostUnload__)(POBJGPU, struct Intr *, NvU32); NV_STATUS (*__intrStatePreUnload__)(POBJGPU, struct Intr *, NvU32); void (*__intrInitMissing__)(POBJGPU, struct Intr *); NV_STATUS (*__intrStatePreInitLocked__)(POBJGPU, struct Intr *); NV_STATUS (*__intrStatePreInitUnlocked__)(POBJGPU, struct Intr *); - NV_STATUS (*__intrGetTunableState__)(POBJGPU, struct Intr *, void *); - NV_STATUS (*__intrCompareTunableState__)(POBJGPU, struct Intr *, void *, void *); - void (*__intrFreeTunableState__)(POBJGPU, struct Intr *, void *); NV_STATUS (*__intrStatePostLoad__)(POBJGPU, struct Intr *, NvU32); - NV_STATUS (*__intrAllocTunableState__)(POBJGPU, struct Intr *, void **); - NV_STATUS (*__intrSetTunableState__)(POBJGPU, struct Intr *, void *); NvBool (*__intrIsPresent__)(POBJGPU, struct Intr *); NvBool PDB_PROP_INTR_ENABLE_DETAILED_LOGS; NvBool PDB_PROP_INTR_HOST_DRIVEN_ENGINES_REMOVED_FROM_PMC; @@ -249,13 +243,12 @@ NvU32 replayableFaultIntrVector; NvU32 accessCntrIntrVector; NvU32 displayIntrVector; - NvU32 intrTopEnMask; - IntrServiceRecord intrServiceTable[163]; + NvU64 intrTopEnMask; + IntrServiceRecord intrServiceTable[167]; NvBool bDefaultNonstallNotify; - NvU32 intrTableSz; - INTR_TABLE_ENTRY *pIntrTable; - INTR_TABLE_ENTRY pStaticPhysicalTable[19]; - INTR_TABLE_ENTRY pStaticKernelTable[17]; + NvBool bUseLegacyVectorAssignment; + InterruptTable intrTable; + NV2080_INTR_CATEGORY_SUBTREE_MAP subtreeMap[7]; NvBool bDpcStarted; union MC_ENGINE_BITVECTOR pmcIntrPending; DPCQUEUE dpcQueue; @@ -269,9 +262,6 @@ NvU32 intrEn0Orig; NvBool halIntrEnabled; NvU32 saveIntrEn0; - NvBool bTablesPopulated; - NvU32 numPhysicalEntries; - NvU32 numKernelEntries; }; #ifndef __NVOC_CLASS_Intr_TYPEDEF__ @@ -338,8 +328,6 @@ #define intrWriteRegTopEnSet_HAL(pGpu, pIntr, arg0, arg1, arg2) intrWriteRegTopEnSet_DISPATCH(pGpu, pIntr, arg0, arg1, arg2) #define intrWriteRegTopEnClear(pGpu, pIntr, arg0, arg1, arg2) intrWriteRegTopEnClear_DISPATCH(pGpu, pIntr, arg0, arg1, arg2) #define intrWriteRegTopEnClear_HAL(pGpu, pIntr, arg0, arg1, arg2) intrWriteRegTopEnClear_DISPATCH(pGpu, pIntr, arg0, arg1, arg2) -#define intrGetStallSubtreeLast(pGpu, pIntr) intrGetStallSubtreeLast_DISPATCH(pGpu, pIntr) -#define intrGetStallSubtreeLast_HAL(pGpu, pIntr) intrGetStallSubtreeLast_DISPATCH(pGpu, pIntr) #define intrGetNumLeaves(pGpu, pIntr) intrGetNumLeaves_DISPATCH(pGpu, pIntr) #define intrGetNumLeaves_HAL(pGpu, pIntr) intrGetNumLeaves_DISPATCH(pGpu, pIntr) #define intrGetLeafSize(pGpu, pIntr) intrGetLeafSize_DISPATCH(pGpu, pIntr) @@ -360,19 +348,13 @@ #define intrSetIntrEnInHw_HAL(pGpu, pIntr, arg0, arg1) intrSetIntrEnInHw_DISPATCH(pGpu, pIntr, arg0, arg1) #define intrGetIntrEnFromHw(pGpu, pIntr, arg0) intrGetIntrEnFromHw_DISPATCH(pGpu, pIntr, arg0) #define intrGetIntrEnFromHw_HAL(pGpu, pIntr, arg0) intrGetIntrEnFromHw_DISPATCH(pGpu, pIntr, arg0) -#define intrReconcileTunableState(pGpu, pEngstate, pTunableState) intrReconcileTunableState_DISPATCH(pGpu, pEngstate, pTunableState) #define intrStatePreLoad(pGpu, pEngstate, arg0) intrStatePreLoad_DISPATCH(pGpu, pEngstate, arg0) #define intrStatePostUnload(pGpu, pEngstate, arg0) intrStatePostUnload_DISPATCH(pGpu, pEngstate, arg0) #define intrStatePreUnload(pGpu, pEngstate, arg0) intrStatePreUnload_DISPATCH(pGpu, pEngstate, arg0) #define intrInitMissing(pGpu, pEngstate) intrInitMissing_DISPATCH(pGpu, pEngstate) #define intrStatePreInitLocked(pGpu, pEngstate) intrStatePreInitLocked_DISPATCH(pGpu, pEngstate) #define intrStatePreInitUnlocked(pGpu, pEngstate) intrStatePreInitUnlocked_DISPATCH(pGpu, pEngstate) -#define intrGetTunableState(pGpu, pEngstate, pTunableState) intrGetTunableState_DISPATCH(pGpu, pEngstate, pTunableState) -#define intrCompareTunableState(pGpu, pEngstate, pTunables1, pTunables2) intrCompareTunableState_DISPATCH(pGpu, pEngstate, pTunables1, pTunables2) -#define intrFreeTunableState(pGpu, pEngstate, pTunableState) intrFreeTunableState_DISPATCH(pGpu, pEngstate, pTunableState) #define intrStatePostLoad(pGpu, pEngstate, arg0) intrStatePostLoad_DISPATCH(pGpu, pEngstate, arg0) -#define intrAllocTunableState(pGpu, pEngstate, ppTunableState) intrAllocTunableState_DISPATCH(pGpu, pEngstate, ppTunableState) -#define intrSetTunableState(pGpu, pEngstate, pTunableState) intrSetTunableState_DISPATCH(pGpu, pEngstate, pTunableState) #define intrIsPresent(pGpu, pEngstate) intrIsPresent_DISPATCH(pGpu, pEngstate) NV_STATUS intrCheckFecsEventbufferPending_IMPL(OBJGPU *pGpu, struct Intr *pIntr, union MC_ENGINE_BITVECTOR *arg0, NvBool *arg1); @@ -643,40 +625,6 @@ #define intrClearLeafVector_HAL(pGpu, pIntr, vector, pThreadState) intrClearLeafVector(pGpu, pIntr, vector, pThreadState) -static inline void intrClearCpuLeafVector_b3696a(OBJGPU *pGpu, struct Intr *pIntr, NvU32 vector, struct THREAD_STATE_NODE *pThreadState) { - return; -} - -void intrClearCpuLeafVector_GH100(OBJGPU *pGpu, struct Intr *pIntr, NvU32 vector, struct THREAD_STATE_NODE *pThreadState); - - -#ifdef __nvoc_intr_h_disabled -static inline void intrClearCpuLeafVector(OBJGPU *pGpu, struct Intr *pIntr, NvU32 vector, struct THREAD_STATE_NODE *pThreadState) { - NV_ASSERT_FAILED_PRECOMP("Intr was disabled!"); -} -#else //__nvoc_intr_h_disabled -#define intrClearCpuLeafVector(pGpu, pIntr, vector, pThreadState) intrClearCpuLeafVector_b3696a(pGpu, pIntr, vector, pThreadState) -#endif //__nvoc_intr_h_disabled - -#define intrClearCpuLeafVector_HAL(pGpu, pIntr, vector, pThreadState) intrClearCpuLeafVector(pGpu, pIntr, vector, pThreadState) - -static inline void intrWriteCpuRegLeaf_b3696a(OBJGPU *pGpu, struct Intr *pIntr, NvU32 arg0, NvU32 arg1, struct THREAD_STATE_NODE *arg2) { - return; -} - -void intrWriteCpuRegLeaf_GH100(OBJGPU *pGpu, struct Intr *pIntr, NvU32 arg0, NvU32 arg1, struct THREAD_STATE_NODE *arg2); - - -#ifdef __nvoc_intr_h_disabled -static inline void intrWriteCpuRegLeaf(OBJGPU *pGpu, struct Intr *pIntr, NvU32 arg0, NvU32 arg1, struct THREAD_STATE_NODE *arg2) { - NV_ASSERT_FAILED_PRECOMP("Intr was disabled!"); -} -#else //__nvoc_intr_h_disabled -#define intrWriteCpuRegLeaf(pGpu, pIntr, arg0, arg1, arg2) intrWriteCpuRegLeaf_b3696a(pGpu, pIntr, arg0, arg1, arg2) -#endif //__nvoc_intr_h_disabled - -#define intrWriteCpuRegLeaf_HAL(pGpu, pIntr, arg0, arg1, arg2) intrWriteCpuRegLeaf(pGpu, pIntr, arg0, arg1, arg2) - NvBool intrIsVectorPending_TU102(OBJGPU *pGpu, struct Intr *pIntr, NvU32 vector, struct THREAD_STATE_NODE *pThreadState); @@ -745,20 +693,6 @@ #define intrDisableStallSWIntr_HAL(pGpu, pIntr) intrDisableStallSWIntr(pGpu, pIntr) -NV_STATUS intrEnableVirtualIntrLeaf_TU102(OBJGPU *pGpu, struct Intr *pIntr, NvU32 gfid); - - -#ifdef __nvoc_intr_h_disabled -static inline NV_STATUS intrEnableVirtualIntrLeaf(OBJGPU *pGpu, struct Intr *pIntr, NvU32 gfid) { - NV_ASSERT_FAILED_PRECOMP("Intr was disabled!"); - return NV_ERR_NOT_SUPPORTED; -} -#else //__nvoc_intr_h_disabled -#define intrEnableVirtualIntrLeaf(pGpu, pIntr, gfid) intrEnableVirtualIntrLeaf_TU102(pGpu, pIntr, gfid) -#endif //__nvoc_intr_h_disabled - -#define intrEnableVirtualIntrLeaf_HAL(pGpu, pIntr, gfid) intrEnableVirtualIntrLeaf(pGpu, pIntr, gfid) - void intrServiceVirtual_TU102(OBJGPU *pGpu, struct Intr *pIntr); @@ -1006,89 +940,74 @@ #define intrWriteRegLeaf_HAL(pGpu, pIntr, arg0, arg1, arg2) intrWriteRegLeaf(pGpu, pIntr, arg0, arg1, arg2) -static inline NvU32 intrUpdateIntrCtrlValue_4a4dee(OBJGPU *pGpu, struct Intr *pIntr, NvU32 intrCtrl, NvU32 routing) { - return 0; -} - -NvU32 intrUpdateIntrCtrlValue_GH100(OBJGPU *pGpu, struct Intr *pIntr, NvU32 intrCtrl, NvU32 routing); - - -#ifdef __nvoc_intr_h_disabled -static inline NvU32 intrUpdateIntrCtrlValue(OBJGPU *pGpu, struct Intr *pIntr, NvU32 intrCtrl, NvU32 routing) { - NV_ASSERT_FAILED_PRECOMP("Intr was disabled!"); - return 0; -} -#else //__nvoc_intr_h_disabled -#define intrUpdateIntrCtrlValue(pGpu, pIntr, intrCtrl, routing) intrUpdateIntrCtrlValue_4a4dee(pGpu, pIntr, intrCtrl, routing) -#endif //__nvoc_intr_h_disabled - -#define intrUpdateIntrCtrlValue_HAL(pGpu, pIntr, intrCtrl, routing) intrUpdateIntrCtrlValue(pGpu, pIntr, intrCtrl, routing) - -static inline void intrSetRouting_b3696a(OBJGPU *pGpu, struct Intr *pIntr, NvU32 intrCtrl, NvU32 intrCtrlReg, NvU32 routing) { +static inline void intrRouteInterruptsToSystemFirmware_b3696a(OBJGPU *pGpu, struct Intr *pIntr, NvBool bEnable) { return; } -void intrSetRouting_GH100(OBJGPU *pGpu, struct Intr *pIntr, NvU32 intrCtrl, NvU32 intrCtrlReg, NvU32 routing); +void intrRouteInterruptsToSystemFirmware_GH100(OBJGPU *pGpu, struct Intr *pIntr, NvBool bEnable); #ifdef __nvoc_intr_h_disabled -static inline void intrSetRouting(OBJGPU *pGpu, struct Intr *pIntr, NvU32 intrCtrl, NvU32 intrCtrlReg, NvU32 routing) { +static inline void intrRouteInterruptsToSystemFirmware(OBJGPU *pGpu, struct Intr *pIntr, NvBool bEnable) { NV_ASSERT_FAILED_PRECOMP("Intr was disabled!"); } #else //__nvoc_intr_h_disabled -#define intrSetRouting(pGpu, pIntr, intrCtrl, intrCtrlReg, routing) intrSetRouting_b3696a(pGpu, pIntr, intrCtrl, intrCtrlReg, routing) +#define intrRouteInterruptsToSystemFirmware(pGpu, pIntr, bEnable) intrRouteInterruptsToSystemFirmware_b3696a(pGpu, pIntr, bEnable) #endif //__nvoc_intr_h_disabled -#define intrSetRouting_HAL(pGpu, pIntr, intrCtrl, intrCtrlReg, routing) intrSetRouting(pGpu, pIntr, intrCtrl, intrCtrlReg, routing) +#define intrRouteInterruptsToSystemFirmware_HAL(pGpu, pIntr, bEnable) intrRouteInterruptsToSystemFirmware(pGpu, pIntr, bEnable) -static inline void intrRouteFBInterruptsToSystemFirmware_b3696a(OBJGPU *pGpu, struct Intr *pIntr, NvBool bEnable) { - return; +static inline NV_STATUS intrInitDynamicInterruptTable_5baef9(OBJGPU *pGpu, struct Intr *pIntr, struct OBJFIFO *arg0, InterruptTable *arg1, NvU32 initFlags) { + NV_ASSERT_OR_RETURN_PRECOMP(0, NV_ERR_NOT_SUPPORTED); } -void intrRouteFBInterruptsToSystemFirmware_GH100(OBJGPU *pGpu, struct Intr *pIntr, NvBool bEnable); - #ifdef __nvoc_intr_h_disabled -static inline void intrRouteFBInterruptsToSystemFirmware(OBJGPU *pGpu, struct Intr *pIntr, NvBool bEnable) { +static inline NV_STATUS intrInitDynamicInterruptTable(OBJGPU *pGpu, struct Intr *pIntr, struct OBJFIFO *arg0, InterruptTable *arg1, NvU32 initFlags) { NV_ASSERT_FAILED_PRECOMP("Intr was disabled!"); + return NV_ERR_NOT_SUPPORTED; } #else //__nvoc_intr_h_disabled -#define intrRouteFBInterruptsToSystemFirmware(pGpu, pIntr, bEnable) intrRouteFBInterruptsToSystemFirmware_b3696a(pGpu, pIntr, bEnable) +#define intrInitDynamicInterruptTable(pGpu, pIntr, arg0, arg1, initFlags) intrInitDynamicInterruptTable_5baef9(pGpu, pIntr, arg0, arg1, initFlags) #endif //__nvoc_intr_h_disabled -#define intrRouteFBInterruptsToSystemFirmware_HAL(pGpu, pIntr, bEnable) intrRouteFBInterruptsToSystemFirmware(pGpu, pIntr, bEnable) +#define intrInitDynamicInterruptTable_HAL(pGpu, pIntr, arg0, arg1, initFlags) intrInitDynamicInterruptTable(pGpu, pIntr, arg0, arg1, initFlags) -static inline NV_STATUS intrInitDynamicInterruptTable_5baef9(OBJGPU *pGpu, struct Intr *pIntr, struct OBJFIFO *arg0, INTR_TABLE_ENTRY *arg1, NvU32 arg2, NvU32 initFlags) { +static inline NV_STATUS intrInitAnyInterruptTable_5baef9(OBJGPU *pGpu, struct Intr *pIntr, InterruptTable *pIntrTable, NvU32 initFlags) { NV_ASSERT_OR_RETURN_PRECOMP(0, NV_ERR_NOT_SUPPORTED); } #ifdef __nvoc_intr_h_disabled -static inline NV_STATUS intrInitDynamicInterruptTable(OBJGPU *pGpu, struct Intr *pIntr, struct OBJFIFO *arg0, INTR_TABLE_ENTRY *arg1, NvU32 arg2, NvU32 initFlags) { +static inline NV_STATUS intrInitAnyInterruptTable(OBJGPU *pGpu, struct Intr *pIntr, InterruptTable *pIntrTable, NvU32 initFlags) { NV_ASSERT_FAILED_PRECOMP("Intr was disabled!"); return NV_ERR_NOT_SUPPORTED; } #else //__nvoc_intr_h_disabled -#define intrInitDynamicInterruptTable(pGpu, pIntr, arg0, arg1, arg2, initFlags) intrInitDynamicInterruptTable_5baef9(pGpu, pIntr, arg0, arg1, arg2, initFlags) +#define intrInitAnyInterruptTable(pGpu, pIntr, pIntrTable, initFlags) intrInitAnyInterruptTable_5baef9(pGpu, pIntr, pIntrTable, initFlags) #endif //__nvoc_intr_h_disabled -#define intrInitDynamicInterruptTable_HAL(pGpu, pIntr, arg0, arg1, arg2, initFlags) intrInitDynamicInterruptTable(pGpu, pIntr, arg0, arg1, arg2, initFlags) +#define intrInitAnyInterruptTable_HAL(pGpu, pIntr, pIntrTable, initFlags) intrInitAnyInterruptTable(pGpu, pIntr, pIntrTable, initFlags) -static inline NV_STATUS intrInitAnyInterruptTable_5baef9(OBJGPU *pGpu, struct Intr *pIntr, INTR_TABLE_ENTRY **ppIntrTable, NvU32 *pIntrTableSz, NvU32 initFlags) { - NV_ASSERT_OR_RETURN_PRECOMP(0, NV_ERR_NOT_SUPPORTED); +static inline NV_STATUS intrInitSubtreeMap_395e98(OBJGPU *pGpu, struct Intr *pIntr) { + return NV_ERR_NOT_SUPPORTED; } +NV_STATUS intrInitSubtreeMap_TU102(OBJGPU *pGpu, struct Intr *pIntr); + +NV_STATUS intrInitSubtreeMap_GH100(OBJGPU *pGpu, struct Intr *pIntr); + #ifdef __nvoc_intr_h_disabled -static inline NV_STATUS intrInitAnyInterruptTable(OBJGPU *pGpu, struct Intr *pIntr, INTR_TABLE_ENTRY **ppIntrTable, NvU32 *pIntrTableSz, NvU32 initFlags) { +static inline NV_STATUS intrInitSubtreeMap(OBJGPU *pGpu, struct Intr *pIntr) { NV_ASSERT_FAILED_PRECOMP("Intr was disabled!"); return NV_ERR_NOT_SUPPORTED; } #else //__nvoc_intr_h_disabled -#define intrInitAnyInterruptTable(pGpu, pIntr, ppIntrTable, pIntrTableSz, initFlags) intrInitAnyInterruptTable_5baef9(pGpu, pIntr, ppIntrTable, pIntrTableSz, initFlags) +#define intrInitSubtreeMap(pGpu, pIntr) intrInitSubtreeMap_395e98(pGpu, pIntr) #endif //__nvoc_intr_h_disabled -#define intrInitAnyInterruptTable_HAL(pGpu, pIntr, ppIntrTable, pIntrTableSz, initFlags) intrInitAnyInterruptTable(pGpu, pIntr, ppIntrTable, pIntrTableSz, initFlags) +#define intrInitSubtreeMap_HAL(pGpu, pIntr) intrInitSubtreeMap(pGpu, pIntr) NV_STATUS intrInitInterruptTable_KERNEL(OBJGPU *pGpu, struct Intr *pIntr); @@ -1104,19 +1023,19 @@ #define intrInitInterruptTable_HAL(pGpu, pIntr) intrInitInterruptTable(pGpu, pIntr) -NV_STATUS intrGetInterruptTable_IMPL(OBJGPU *pGpu, struct Intr *pIntr, INTR_TABLE_ENTRY **arg0, NvU32 *arg1); +NV_STATUS intrGetInterruptTable_IMPL(OBJGPU *pGpu, struct Intr *pIntr, InterruptTable **ppIntrTable); #ifdef __nvoc_intr_h_disabled -static inline NV_STATUS intrGetInterruptTable(OBJGPU *pGpu, struct Intr *pIntr, INTR_TABLE_ENTRY **arg0, NvU32 *arg1) { +static inline NV_STATUS intrGetInterruptTable(OBJGPU *pGpu, struct Intr *pIntr, InterruptTable **ppIntrTable) { NV_ASSERT_FAILED_PRECOMP("Intr was disabled!"); return NV_ERR_NOT_SUPPORTED; } #else //__nvoc_intr_h_disabled -#define intrGetInterruptTable(pGpu, pIntr, arg0, arg1) intrGetInterruptTable_IMPL(pGpu, pIntr, arg0, arg1) +#define intrGetInterruptTable(pGpu, pIntr, ppIntrTable) intrGetInterruptTable_IMPL(pGpu, pIntr, ppIntrTable) #endif //__nvoc_intr_h_disabled -#define intrGetInterruptTable_HAL(pGpu, pIntr, arg0, arg1) intrGetInterruptTable(pGpu, pIntr, arg0, arg1) +#define intrGetInterruptTable_HAL(pGpu, pIntr, ppIntrTable) intrGetInterruptTable(pGpu, pIntr, ppIntrTable) NV_STATUS intrDestroyInterruptTable_IMPL(OBJGPU *pGpu, struct Intr *pIntr); @@ -1152,85 +1071,65 @@ #define intrGetStaticVFmcEngines_HAL(pGpu, pIntr, ppMcEngines, pCount) intrGetStaticVFmcEngines(pGpu, pIntr, ppMcEngines, pCount) -static inline NV_STATUS intrGetStaticInterruptTable_5baef9(OBJGPU *pGpu, struct Intr *pIntr, INTR_TABLE_ENTRY *pTable, NvU32 *pCount, NvU32 maxCount, NvU32 initFlags) { +static inline NV_STATUS intrGetStaticInterruptTable_5baef9(OBJGPU *pGpu, struct Intr *pIntr, InterruptTable *pTable, NvU32 initFlags) { NV_ASSERT_OR_RETURN_PRECOMP(0, NV_ERR_NOT_SUPPORTED); } -NV_STATUS intrGetStaticInterruptTable_TU102(OBJGPU *pGpu, struct Intr *pIntr, INTR_TABLE_ENTRY *pTable, NvU32 *pCount, NvU32 maxCount, NvU32 initFlags); +NV_STATUS intrGetStaticInterruptTable_TU102(OBJGPU *pGpu, struct Intr *pIntr, InterruptTable *pTable, NvU32 initFlags); -NV_STATUS intrGetStaticInterruptTable_GA100(OBJGPU *pGpu, struct Intr *pIntr, INTR_TABLE_ENTRY *pTable, NvU32 *pCount, NvU32 maxCount, NvU32 initFlags); +NV_STATUS intrGetStaticInterruptTable_GA100(OBJGPU *pGpu, struct Intr *pIntr, InterruptTable *pTable, NvU32 initFlags); -NV_STATUS intrGetStaticInterruptTable_GA102(OBJGPU *pGpu, struct Intr *pIntr, INTR_TABLE_ENTRY *pTable, NvU32 *pCount, NvU32 maxCount, NvU32 initFlags); +NV_STATUS intrGetStaticInterruptTable_GA102(OBJGPU *pGpu, struct Intr *pIntr, InterruptTable *pTable, NvU32 initFlags); -NV_STATUS intrGetStaticInterruptTable_GH100(OBJGPU *pGpu, struct Intr *pIntr, INTR_TABLE_ENTRY *pTable, NvU32 *pCount, NvU32 maxCount, NvU32 initFlags); +NV_STATUS intrGetStaticInterruptTable_GH100(OBJGPU *pGpu, struct Intr *pIntr, InterruptTable *pTable, NvU32 initFlags); #ifdef __nvoc_intr_h_disabled -static inline NV_STATUS intrGetStaticInterruptTable(OBJGPU *pGpu, struct Intr *pIntr, INTR_TABLE_ENTRY *pTable, NvU32 *pCount, NvU32 maxCount, NvU32 initFlags) { +static inline NV_STATUS intrGetStaticInterruptTable(OBJGPU *pGpu, struct Intr *pIntr, InterruptTable *pTable, NvU32 initFlags) { NV_ASSERT_FAILED_PRECOMP("Intr was disabled!"); return NV_ERR_NOT_SUPPORTED; } #else //__nvoc_intr_h_disabled -#define intrGetStaticInterruptTable(pGpu, pIntr, pTable, pCount, maxCount, initFlags) intrGetStaticInterruptTable_5baef9(pGpu, pIntr, pTable, pCount, maxCount, initFlags) -#endif //__nvoc_intr_h_disabled - -#define intrGetStaticInterruptTable_HAL(pGpu, pIntr, pTable, pCount, maxCount, initFlags) intrGetStaticInterruptTable(pGpu, pIntr, pTable, pCount, maxCount, initFlags) - -static inline NvU32 intrGetGPUHostInterruptTableSize_5baef9(OBJGPU *pGpu, struct Intr *pIntr, NvU32 initFlags) { - NV_ASSERT_OR_RETURN_PRECOMP(0, NV_ERR_NOT_SUPPORTED); -} - -NvU32 intrGetGPUHostInterruptTableSize_GM107(OBJGPU *pGpu, struct Intr *pIntr, NvU32 initFlags); - -NvU32 intrGetGPUHostInterruptTableSize_GA100(OBJGPU *pGpu, struct Intr *pIntr, NvU32 initFlags); - - -#ifdef __nvoc_intr_h_disabled -static inline NvU32 intrGetGPUHostInterruptTableSize(OBJGPU *pGpu, struct Intr *pIntr, NvU32 initFlags) { - NV_ASSERT_FAILED_PRECOMP("Intr was disabled!"); - return 0; -} -#else //__nvoc_intr_h_disabled -#define intrGetGPUHostInterruptTableSize(pGpu, pIntr, initFlags) intrGetGPUHostInterruptTableSize_5baef9(pGpu, pIntr, initFlags) +#define intrGetStaticInterruptTable(pGpu, pIntr, pTable, initFlags) intrGetStaticInterruptTable_5baef9(pGpu, pIntr, pTable, initFlags) #endif //__nvoc_intr_h_disabled -#define intrGetGPUHostInterruptTableSize_HAL(pGpu, pIntr, initFlags) intrGetGPUHostInterruptTableSize(pGpu, pIntr, initFlags) +#define intrGetStaticInterruptTable_HAL(pGpu, pIntr, pTable, initFlags) intrGetStaticInterruptTable(pGpu, pIntr, pTable, initFlags) -static inline NV_STATUS intrInitGPUHostInterruptTable_5baef9(OBJGPU *pGpu, struct Intr *pIntr, INTR_TABLE_ENTRY *arg0, NvU32 arg1, NvU32 initFlags) { +static inline NV_STATUS intrInitGPUHostInterruptTable_5baef9(OBJGPU *pGpu, struct Intr *pIntr, InterruptTable *pIntrTable, NvU32 initFlags) { NV_ASSERT_OR_RETURN_PRECOMP(0, NV_ERR_NOT_SUPPORTED); } -NV_STATUS intrInitGPUHostInterruptTable_GM107(OBJGPU *pGpu, struct Intr *pIntr, INTR_TABLE_ENTRY *arg0, NvU32 arg1, NvU32 initFlags); +NV_STATUS intrInitGPUHostInterruptTable_GM107(OBJGPU *pGpu, struct Intr *pIntr, InterruptTable *pIntrTable, NvU32 initFlags); -NV_STATUS intrInitGPUHostInterruptTable_GA100(OBJGPU *pGpu, struct Intr *pIntr, INTR_TABLE_ENTRY *arg0, NvU32 arg1, NvU32 initFlags); +NV_STATUS intrInitGPUHostInterruptTable_GA100(OBJGPU *pGpu, struct Intr *pIntr, InterruptTable *pIntrTable, NvU32 initFlags); #ifdef __nvoc_intr_h_disabled -static inline NV_STATUS intrInitGPUHostInterruptTable(OBJGPU *pGpu, struct Intr *pIntr, INTR_TABLE_ENTRY *arg0, NvU32 arg1, NvU32 initFlags) { +static inline NV_STATUS intrInitGPUHostInterruptTable(OBJGPU *pGpu, struct Intr *pIntr, InterruptTable *pIntrTable, NvU32 initFlags) { NV_ASSERT_FAILED_PRECOMP("Intr was disabled!"); return NV_ERR_NOT_SUPPORTED; } #else //__nvoc_intr_h_disabled -#define intrInitGPUHostInterruptTable(pGpu, pIntr, arg0, arg1, initFlags) intrInitGPUHostInterruptTable_5baef9(pGpu, pIntr, arg0, arg1, initFlags) +#define intrInitGPUHostInterruptTable(pGpu, pIntr, pIntrTable, initFlags) intrInitGPUHostInterruptTable_5baef9(pGpu, pIntr, pIntrTable, initFlags) #endif //__nvoc_intr_h_disabled -#define intrInitGPUHostInterruptTable_HAL(pGpu, pIntr, arg0, arg1, initFlags) intrInitGPUHostInterruptTable(pGpu, pIntr, arg0, arg1, initFlags) +#define intrInitGPUHostInterruptTable_HAL(pGpu, pIntr, pIntrTable, initFlags) intrInitGPUHostInterruptTable(pGpu, pIntr, pIntrTable, initFlags) -static inline NV_STATUS intrInitEngineSchedInterruptTable_5baef9(OBJGPU *pGpu, struct Intr *pIntr, INTR_TABLE_ENTRY *arg0, NvU32 arg1) { +static inline NV_STATUS intrInitEngineSchedInterruptTable_5baef9(OBJGPU *pGpu, struct Intr *pIntr, InterruptTable *pIntrTable) { NV_ASSERT_OR_RETURN_PRECOMP(0, NV_ERR_NOT_SUPPORTED); } #ifdef __nvoc_intr_h_disabled -static inline NV_STATUS intrInitEngineSchedInterruptTable(OBJGPU *pGpu, struct Intr *pIntr, INTR_TABLE_ENTRY *arg0, NvU32 arg1) { +static inline NV_STATUS intrInitEngineSchedInterruptTable(OBJGPU *pGpu, struct Intr *pIntr, InterruptTable *pIntrTable) { NV_ASSERT_FAILED_PRECOMP("Intr was disabled!"); return NV_ERR_NOT_SUPPORTED; } #else //__nvoc_intr_h_disabled -#define intrInitEngineSchedInterruptTable(pGpu, pIntr, arg0, arg1) intrInitEngineSchedInterruptTable_5baef9(pGpu, pIntr, arg0, arg1) +#define intrInitEngineSchedInterruptTable(pGpu, pIntr, pIntrTable) intrInitEngineSchedInterruptTable_5baef9(pGpu, pIntr, pIntrTable) #endif //__nvoc_intr_h_disabled -#define intrInitEngineSchedInterruptTable_HAL(pGpu, pIntr, arg0, arg1) intrInitEngineSchedInterruptTable(pGpu, pIntr, arg0, arg1) +#define intrInitEngineSchedInterruptTable_HAL(pGpu, pIntr, pIntrTable) intrInitEngineSchedInterruptTable(pGpu, pIntr, pIntrTable) void intrServiceStall_IMPL(OBJGPU *pGpu, struct Intr *pIntr); @@ -1342,27 +1241,27 @@ #define intrGetNvlinkIntrMaskOffset_HAL(pGpu, pIntr, arg0, arg1) intrGetNvlinkIntrMaskOffset(pGpu, pIntr, arg0, arg1) -static inline NV_STATUS intrGetEccVirtualFunctionIntrMask_5baef9(OBJGPU *pGpu, struct Intr *pIntr, NvHandle arg0, NvU32 *arg1) { +static inline NV_STATUS intrGetEccVirtualFunctionIntrMask_5baef9(OBJGPU *pGpu, struct Intr *pIntr, struct Device *pDevice, NvU32 *arg0) { NV_ASSERT_OR_RETURN_PRECOMP(0, NV_ERR_NOT_SUPPORTED); } -NV_STATUS intrGetEccVirtualFunctionIntrMask_TU102(OBJGPU *pGpu, struct Intr *pIntr, NvHandle arg0, NvU32 *arg1); +NV_STATUS intrGetEccVirtualFunctionIntrMask_TU102(OBJGPU *pGpu, struct Intr *pIntr, struct Device *pDevice, NvU32 *arg0); -NV_STATUS intrGetEccVirtualFunctionIntrMask_GA100(OBJGPU *pGpu, struct Intr *pIntr, NvHandle arg0, NvU32 *arg1); +NV_STATUS intrGetEccVirtualFunctionIntrMask_GA100(OBJGPU *pGpu, struct Intr *pIntr, struct Device *pDevice, NvU32 *arg0); -NV_STATUS intrGetEccVirtualFunctionIntrMask_GH100(OBJGPU *pGpu, struct Intr *pIntr, NvHandle arg0, NvU32 *arg1); +NV_STATUS intrGetEccVirtualFunctionIntrMask_GH100(OBJGPU *pGpu, struct Intr *pIntr, struct Device *pDevice, NvU32 *arg0); #ifdef __nvoc_intr_h_disabled -static inline NV_STATUS intrGetEccVirtualFunctionIntrMask(OBJGPU *pGpu, struct Intr *pIntr, NvHandle arg0, NvU32 *arg1) { +static inline NV_STATUS intrGetEccVirtualFunctionIntrMask(OBJGPU *pGpu, struct Intr *pIntr, struct Device *pDevice, NvU32 *arg0) { NV_ASSERT_FAILED_PRECOMP("Intr was disabled!"); return NV_ERR_NOT_SUPPORTED; } #else //__nvoc_intr_h_disabled -#define intrGetEccVirtualFunctionIntrMask(pGpu, pIntr, arg0, arg1) intrGetEccVirtualFunctionIntrMask_5baef9(pGpu, pIntr, arg0, arg1) +#define intrGetEccVirtualFunctionIntrMask(pGpu, pIntr, pDevice, arg0) intrGetEccVirtualFunctionIntrMask_5baef9(pGpu, pIntr, pDevice, arg0) #endif //__nvoc_intr_h_disabled -#define intrGetEccVirtualFunctionIntrMask_HAL(pGpu, pIntr, arg0, arg1) intrGetEccVirtualFunctionIntrMask(pGpu, pIntr, arg0, arg1) +#define intrGetEccVirtualFunctionIntrMask_HAL(pGpu, pIntr, pDevice, arg0) intrGetEccVirtualFunctionIntrMask(pGpu, pIntr, pDevice, arg0) static inline NV_STATUS intrGetNvlinkVirtualFunctionIntrMask_5baef9(OBJGPU *pGpu, struct Intr *pIntr, NvU32 arg0, NvU32 *arg1) { NV_ASSERT_OR_RETURN_PRECOMP(0, NV_ERR_NOT_SUPPORTED); @@ -1606,14 +1505,6 @@ pIntr->__intrWriteRegTopEnClear__(pGpu, pIntr, arg0, arg1, arg2); } -NvU32 intrGetStallSubtreeLast_TU102(OBJGPU *pGpu, struct Intr *pIntr); - -NvU32 intrGetStallSubtreeLast_GH100(OBJGPU *pGpu, struct Intr *pIntr); - -static inline NvU32 intrGetStallSubtreeLast_DISPATCH(OBJGPU *pGpu, struct Intr *pIntr) { - return pIntr->__intrGetStallSubtreeLast__(pGpu, pIntr); -} - NvU32 intrGetNumLeaves_TU102(OBJGPU *pGpu, struct Intr *pIntr); NvU32 intrGetNumLeaves_GH100(OBJGPU *pGpu, struct Intr *pIntr); @@ -1630,11 +1521,11 @@ return pIntr->__intrGetLeafSize__(pGpu, pIntr); } -NvU32 intrGetIntrTopNonStallMask_TU102(OBJGPU *pGpu, struct Intr *pIntr); +NvU64 intrGetIntrTopNonStallMask_TU102(OBJGPU *pGpu, struct Intr *pIntr); -NvU32 intrGetIntrTopNonStallMask_GH100(OBJGPU *pGpu, struct Intr *pIntr); +NvU64 intrGetIntrTopNonStallMask_GH100(OBJGPU *pGpu, struct Intr *pIntr); -static inline NvU32 intrGetIntrTopNonStallMask_DISPATCH(OBJGPU *pGpu, struct Intr *pIntr) { +static inline NvU64 intrGetIntrTopNonStallMask_DISPATCH(OBJGPU *pGpu, struct Intr *pIntr) { return pIntr->__intrGetIntrTopNonStallMask__(pGpu, pIntr); } @@ -1704,10 +1595,6 @@ return pIntr->__intrGetIntrEnFromHw__(pGpu, pIntr, arg0); } -static inline NV_STATUS intrReconcileTunableState_DISPATCH(POBJGPU pGpu, struct Intr *pEngstate, void *pTunableState) { - return pEngstate->__intrReconcileTunableState__(pGpu, pEngstate, pTunableState); -} - static inline NV_STATUS intrStatePreLoad_DISPATCH(POBJGPU pGpu, struct Intr *pEngstate, NvU32 arg0) { return pEngstate->__intrStatePreLoad__(pGpu, pEngstate, arg0); } @@ -1732,30 +1619,10 @@ return pEngstate->__intrStatePreInitUnlocked__(pGpu, pEngstate); } -static inline NV_STATUS intrGetTunableState_DISPATCH(POBJGPU pGpu, struct Intr *pEngstate, void *pTunableState) { - return pEngstate->__intrGetTunableState__(pGpu, pEngstate, pTunableState); -} - -static inline NV_STATUS intrCompareTunableState_DISPATCH(POBJGPU pGpu, struct Intr *pEngstate, void *pTunables1, void *pTunables2) { - return pEngstate->__intrCompareTunableState__(pGpu, pEngstate, pTunables1, pTunables2); -} - -static inline void intrFreeTunableState_DISPATCH(POBJGPU pGpu, struct Intr *pEngstate, void *pTunableState) { - pEngstate->__intrFreeTunableState__(pGpu, pEngstate, pTunableState); -} - static inline NV_STATUS intrStatePostLoad_DISPATCH(POBJGPU pGpu, struct Intr *pEngstate, NvU32 arg0) { return pEngstate->__intrStatePostLoad__(pGpu, pEngstate, arg0); } -static inline NV_STATUS intrAllocTunableState_DISPATCH(POBJGPU pGpu, struct Intr *pEngstate, void **ppTunableState) { - return pEngstate->__intrAllocTunableState__(pGpu, pEngstate, ppTunableState); -} - -static inline NV_STATUS intrSetTunableState_DISPATCH(POBJGPU pGpu, struct Intr *pEngstate, void *pTunableState) { - return pEngstate->__intrSetTunableState__(pGpu, pEngstate, pTunableState); -} - static inline NvBool intrIsPresent_DISPATCH(POBJGPU pGpu, struct Intr *pEngstate) { return pEngstate->__intrIsPresent__(pGpu, pEngstate); } @@ -1785,6 +1652,50 @@ #define intrServiceNotificationRecords(pGpu, pIntr, mcEngineIdx, arg0) intrServiceNotificationRecords_IMPL(pGpu, pIntr, mcEngineIdx, arg0) #endif //__nvoc_intr_h_disabled +NvU64 intrGetIntrTopLegacyStallMask_IMPL(struct Intr *pIntr); + +#ifdef __nvoc_intr_h_disabled +static inline NvU64 intrGetIntrTopLegacyStallMask(struct Intr *pIntr) { + NV_ASSERT_FAILED_PRECOMP("Intr was disabled!"); + return 0; +} +#else //__nvoc_intr_h_disabled +#define intrGetIntrTopLegacyStallMask(pIntr) intrGetIntrTopLegacyStallMask_IMPL(pIntr) +#endif //__nvoc_intr_h_disabled + +NvU64 intrGetIntrTopLockedMask_IMPL(OBJGPU *pGpu, struct Intr *pIntr); + +#ifdef __nvoc_intr_h_disabled +static inline NvU64 intrGetIntrTopLockedMask(OBJGPU *pGpu, struct Intr *pIntr) { + NV_ASSERT_FAILED_PRECOMP("Intr was disabled!"); + return 0; +} +#else //__nvoc_intr_h_disabled +#define intrGetIntrTopLockedMask(pGpu, pIntr) intrGetIntrTopLockedMask_IMPL(pGpu, pIntr) +#endif //__nvoc_intr_h_disabled + +NV_STATUS intrGetSubtreeRange_IMPL(struct Intr *pIntr, NV2080_INTR_CATEGORY category, NV2080_INTR_CATEGORY_SUBTREE_MAP *pRange); + +#ifdef __nvoc_intr_h_disabled +static inline NV_STATUS intrGetSubtreeRange(struct Intr *pIntr, NV2080_INTR_CATEGORY category, NV2080_INTR_CATEGORY_SUBTREE_MAP *pRange) { + NV_ASSERT_FAILED_PRECOMP("Intr was disabled!"); + return NV_ERR_NOT_SUPPORTED; +} +#else //__nvoc_intr_h_disabled +#define intrGetSubtreeRange(pIntr, category, pRange) intrGetSubtreeRange_IMPL(pIntr, category, pRange) +#endif //__nvoc_intr_h_disabled + +NvU64 intrGetIntrTopCategoryMask_IMPL(struct Intr *pIntr, NV2080_INTR_CATEGORY category); + +#ifdef __nvoc_intr_h_disabled +static inline NvU64 intrGetIntrTopCategoryMask(struct Intr *pIntr, NV2080_INTR_CATEGORY category) { + NV_ASSERT_FAILED_PRECOMP("Intr was disabled!"); + return 0; +} +#else //__nvoc_intr_h_disabled +#define intrGetIntrTopCategoryMask(pIntr, category) intrGetIntrTopCategoryMask_IMPL(pIntr, category) +#endif //__nvoc_intr_h_disabled + void intrServiceStallListAllGpusCond_IMPL(OBJGPU *pGpu, struct Intr *pIntr, union MC_ENGINE_BITVECTOR *arg0, NvBool arg1); #ifdef __nvoc_intr_h_disabled @@ -2010,19 +1921,6 @@ // This mask is used for interrupts that should be masked off in the PMC tree #define NV_PMC_INTR_INVALID_MASK (0) -#define INTR_WRITE_TABLE(status, pTable, maxCount, count, entry) \ - do { \ - if ((count) < (maxCount)) \ - { \ - (pTable)[count] = entry; \ - } \ - else \ - { \ - status = NV_ERR_BUFFER_TOO_SMALL; \ - } \ - count += 1; \ - } while(0) - #endif // INTR_H #ifdef __cplusplus diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/generated/g_intr_service_nvoc.h nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_intr_service_nvoc.h --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/generated/g_intr_service_nvoc.h 2023-10-25 20:27:03.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_intr_service_nvoc.h 2024-03-05 22:18:20.000000000 +0000 @@ -122,9 +122,9 @@ #define intrservClearInterrupt(pGpu, pIntrService, pParams) intrservClearInterrupt_DISPATCH(pGpu, pIntrService, pParams) #define intrservServiceInterrupt(pGpu, pIntrService, pParams) intrservServiceInterrupt_DISPATCH(pGpu, pIntrService, pParams) #define intrservServiceNotificationInterrupt(pGpu, pIntrService, pParams) intrservServiceNotificationInterrupt_DISPATCH(pGpu, pIntrService, pParams) -void intrservRegisterIntrService_IMPL(struct OBJGPU *pGpu, struct IntrService *pIntrService, IntrServiceRecord pRecords[163]); +void intrservRegisterIntrService_IMPL(struct OBJGPU *pGpu, struct IntrService *pIntrService, IntrServiceRecord pRecords[167]); -static inline void intrservRegisterIntrService_DISPATCH(struct OBJGPU *pGpu, struct IntrService *pIntrService, IntrServiceRecord pRecords[163]) { +static inline void intrservRegisterIntrService_DISPATCH(struct OBJGPU *pGpu, struct IntrService *pIntrService, IntrServiceRecord pRecords[167]) { pIntrService->__intrservRegisterIntrService__(pGpu, pIntrService, pRecords); } diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/generated/g_io_vaspace_nvoc.c nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_io_vaspace_nvoc.c --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/generated/g_io_vaspace_nvoc.c 2023-10-25 20:27:03.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_io_vaspace_nvoc.c 2024-03-05 22:18:20.000000000 +0000 @@ -118,7 +118,7 @@ return vaspaceIsAtsEnabled((struct OBJVASPACE *)(((unsigned char *)pVAS) + __nvoc_rtti_OBJIOVASPACE_OBJVASPACE.offset)); } -static NvU32 __nvoc_thunk_OBJVASPACE_iovaspaceGetBigPageSize(struct OBJIOVASPACE *pVAS) { +static NvU64 __nvoc_thunk_OBJVASPACE_iovaspaceGetBigPageSize(struct OBJIOVASPACE *pVAS) { return vaspaceGetBigPageSize((struct OBJVASPACE *)(((unsigned char *)pVAS) + __nvoc_rtti_OBJIOVASPACE_OBJVASPACE.offset)); } @@ -134,7 +134,7 @@ return vaspaceGetKernelPageDirBase((struct OBJVASPACE *)(((unsigned char *)pVAS) + __nvoc_rtti_OBJIOVASPACE_OBJVASPACE.offset), pGpu); } -static NvU32 __nvoc_thunk_OBJVASPACE_iovaspaceGetMapPageSize(struct OBJIOVASPACE *pVAS, struct OBJGPU *pGpu, EMEMBLOCK *pMemBlock) { +static NvU64 __nvoc_thunk_OBJVASPACE_iovaspaceGetMapPageSize(struct OBJIOVASPACE *pVAS, struct OBJGPU *pGpu, EMEMBLOCK *pMemBlock) { return vaspaceGetMapPageSize((struct OBJVASPACE *)(((unsigned char *)pVAS) + __nvoc_rtti_OBJIOVASPACE_OBJVASPACE.offset), pGpu, pMemBlock); } @@ -315,13 +315,16 @@ Object *pParentObj; OBJIOVASPACE *pThis; - pThis = portMemAllocNonPaged(sizeof(OBJIOVASPACE)); - if (pThis == NULL) return NV_ERR_NO_MEMORY; + status = __nvoc_handleObjCreateMemAlloc(createFlags, sizeof(OBJIOVASPACE), (void**)&pThis, (void**)ppThis); + if (status != NV_OK) + return status; portMemSet(pThis, 0, sizeof(OBJIOVASPACE)); __nvoc_initRtti(staticCast(pThis, Dynamic), &__nvoc_class_def_OBJIOVASPACE); + pThis->__nvoc_base_OBJVASPACE.__nvoc_base_Object.createFlags = createFlags; + if (pParent != NULL && !(createFlags & NVOC_OBJ_CREATE_FLAGS_PARENT_HALSPEC_ONLY)) { pParentObj = dynamicCast(pParent, Object); @@ -337,11 +340,17 @@ if (status != NV_OK) goto __nvoc_objCreate_OBJIOVASPACE_cleanup; *ppThis = pThis; + return NV_OK; __nvoc_objCreate_OBJIOVASPACE_cleanup: // do not call destructors here since the constructor already called them - portMemFree(pThis); + if (createFlags & NVOC_OBJ_CREATE_FLAGS_IN_PLACE_CONSTRUCT) + portMemSet(pThis, 0, sizeof(OBJIOVASPACE)); + else + portMemFree(pThis); + + // coverity[leaked_storage:FALSE] return status; } diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/generated/g_io_vaspace_nvoc.h nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_io_vaspace_nvoc.h --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/generated/g_io_vaspace_nvoc.h 2023-10-25 20:27:03.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_io_vaspace_nvoc.h 2024-03-05 22:18:20.000000000 +0000 @@ -159,11 +159,11 @@ NvBool (*__iovaspaceIsInternalVaRestricted__)(struct OBJIOVASPACE *); NvU32 (*__iovaspaceGetFlags__)(struct OBJIOVASPACE *); NvBool (*__iovaspaceIsAtsEnabled__)(struct OBJIOVASPACE *); - NvU32 (*__iovaspaceGetBigPageSize__)(struct OBJIOVASPACE *); + NvU64 (*__iovaspaceGetBigPageSize__)(struct OBJIOVASPACE *); NV_STATUS (*__iovaspaceGetPteInfo__)(struct OBJIOVASPACE *, struct OBJGPU *, NV0080_CTRL_DMA_GET_PTE_INFO_PARAMS *, RmPhysAddr *); PMEMORY_DESCRIPTOR (*__iovaspaceGetPageDirBase__)(struct OBJIOVASPACE *, struct OBJGPU *); PMEMORY_DESCRIPTOR (*__iovaspaceGetKernelPageDirBase__)(struct OBJIOVASPACE *, struct OBJGPU *); - NvU32 (*__iovaspaceGetMapPageSize__)(struct OBJIOVASPACE *, struct OBJGPU *, EMEMBLOCK *); + NvU64 (*__iovaspaceGetMapPageSize__)(struct OBJIOVASPACE *, struct OBJGPU *, EMEMBLOCK *); struct OBJEHEAP *(*__iovaspaceGetHeap__)(struct OBJIOVASPACE *); NvBool (*__iovaspaceIsFaultCapable__)(struct OBJIOVASPACE *); void (*__iovaspaceUnmap__)(struct OBJIOVASPACE *, struct OBJGPU *, const NvU64, const NvU64); @@ -305,7 +305,7 @@ return pVAS->__iovaspaceIsAtsEnabled__(pVAS); } -static inline NvU32 iovaspaceGetBigPageSize_DISPATCH(struct OBJIOVASPACE *pVAS) { +static inline NvU64 iovaspaceGetBigPageSize_DISPATCH(struct OBJIOVASPACE *pVAS) { return pVAS->__iovaspaceGetBigPageSize__(pVAS); } @@ -321,7 +321,7 @@ return pVAS->__iovaspaceGetKernelPageDirBase__(pVAS, pGpu); } -static inline NvU32 iovaspaceGetMapPageSize_DISPATCH(struct OBJIOVASPACE *pVAS, struct OBJGPU *pGpu, EMEMBLOCK *pMemBlock) { +static inline NvU64 iovaspaceGetMapPageSize_DISPATCH(struct OBJIOVASPACE *pVAS, struct OBJGPU *pGpu, EMEMBLOCK *pMemBlock) { return pVAS->__iovaspaceGetMapPageSize__(pVAS, pGpu, pMemBlock); } diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/generated/g_ioaccess_nvoc.c nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_ioaccess_nvoc.c --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/generated/g_ioaccess_nvoc.c 1970-01-01 00:00:00.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_ioaccess_nvoc.c 2024-03-05 22:18:20.000000000 +0000 @@ -0,0 +1,113 @@ +#define NVOC_IOACCESS_H_PRIVATE_ACCESS_ALLOWED +#include "nvoc/runtime.h" +#include "nvoc/rtti.h" +#include "nvtypes.h" +#include "nvport/nvport.h" +#include "nvport/inline/util_valist.h" +#include "utils/nvassert.h" +#include "g_ioaccess_nvoc.h" + +#ifdef DEBUG +char __nvoc_class_id_uniqueness_check_0xfcaf2e = 1; +#endif + +extern const struct NVOC_CLASS_DEF __nvoc_class_def_RegisterAperture; + +void __nvoc_init_RegisterAperture(RegisterAperture*); +void __nvoc_init_funcTable_RegisterAperture(RegisterAperture*); +NV_STATUS __nvoc_ctor_RegisterAperture(RegisterAperture*); +void __nvoc_init_dataField_RegisterAperture(RegisterAperture*); +void __nvoc_dtor_RegisterAperture(RegisterAperture*); +extern const struct NVOC_EXPORT_INFO __nvoc_export_info_RegisterAperture; + +static const struct NVOC_RTTI __nvoc_rtti_RegisterAperture_RegisterAperture = { + /*pClassDef=*/ &__nvoc_class_def_RegisterAperture, + /*dtor=*/ (NVOC_DYNAMIC_DTOR) &__nvoc_dtor_RegisterAperture, + /*offset=*/ 0, +}; + +static const struct NVOC_CASTINFO __nvoc_castinfo_RegisterAperture = { + /*numRelatives=*/ 1, + /*relatives=*/ { + &__nvoc_rtti_RegisterAperture_RegisterAperture, + }, +}; + +// Not instantiable because it's not derived from class "Object" +// Not instantiable because it's an abstract class with following pure virtual functions: +// regaprtReadReg08 +// regaprtReadReg16 +// regaprtReadReg32 +// regaprtWriteReg08 +// regaprtWriteReg16 +// regaprtWriteReg32 +// regaprtWriteReg32Uc +// regaprtIsRegValid +const struct NVOC_CLASS_DEF __nvoc_class_def_RegisterAperture = +{ + /*classInfo=*/ { + /*size=*/ sizeof(RegisterAperture), + /*classId=*/ classId(RegisterAperture), + /*providerId=*/ &__nvoc_rtti_provider, +#if NV_PRINTF_STRINGS_ALLOWED + /*name=*/ "RegisterAperture", +#endif + }, + /*objCreatefn=*/ (NVOC_DYNAMIC_OBJ_CREATE) NULL, + /*pCastInfo=*/ &__nvoc_castinfo_RegisterAperture, + /*pExportInfo=*/ &__nvoc_export_info_RegisterAperture +}; + +const struct NVOC_EXPORT_INFO __nvoc_export_info_RegisterAperture = +{ + /*numEntries=*/ 0, + /*pExportEntries=*/ 0 +}; + +void __nvoc_dtor_RegisterAperture(RegisterAperture *pThis) { + PORT_UNREFERENCED_VARIABLE(pThis); +} + +void __nvoc_init_dataField_RegisterAperture(RegisterAperture *pThis) { + PORT_UNREFERENCED_VARIABLE(pThis); +} + +NV_STATUS __nvoc_ctor_RegisterAperture(RegisterAperture *pThis) { + NV_STATUS status = NV_OK; + __nvoc_init_dataField_RegisterAperture(pThis); + goto __nvoc_ctor_RegisterAperture_exit; // Success + +__nvoc_ctor_RegisterAperture_exit: + + return status; +} + +static void __nvoc_init_funcTable_RegisterAperture_1(RegisterAperture *pThis) { + PORT_UNREFERENCED_VARIABLE(pThis); + + pThis->__regaprtReadReg08__ = NULL; + + pThis->__regaprtReadReg16__ = NULL; + + pThis->__regaprtReadReg32__ = NULL; + + pThis->__regaprtWriteReg08__ = NULL; + + pThis->__regaprtWriteReg16__ = NULL; + + pThis->__regaprtWriteReg32__ = NULL; + + pThis->__regaprtWriteReg32Uc__ = NULL; + + pThis->__regaprtIsRegValid__ = NULL; +} + +void __nvoc_init_funcTable_RegisterAperture(RegisterAperture *pThis) { + __nvoc_init_funcTable_RegisterAperture_1(pThis); +} + +void __nvoc_init_RegisterAperture(RegisterAperture *pThis) { + pThis->__nvoc_pbase_RegisterAperture = pThis; + __nvoc_init_funcTable_RegisterAperture(pThis); +} + diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/generated/g_ioaccess_nvoc.h nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_ioaccess_nvoc.h --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/generated/g_ioaccess_nvoc.h 1970-01-01 00:00:00.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_ioaccess_nvoc.h 2024-03-05 22:18:20.000000000 +0000 @@ -0,0 +1,236 @@ +#ifndef _G_IOACCESS_NVOC_H_ +#define _G_IOACCESS_NVOC_H_ +#include "nvoc/runtime.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/* + * SPDX-FileCopyrightText: Copyright (c) 2018-2020 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ +#if (defined(NVRM) || defined(RMCFG_FEATURE_PLATFORM_GSP)) && !defined(NVWATCH) +#include "g_ioaccess_nvoc.h" +#endif + +#ifndef _IO_ACCESS_H_ +#define _IO_ACCESS_H_ + +#include "nvtypes.h" +#include "nvstatus.h" +#if (defined(NVRM) || defined(RMCFG_FEATURE_PLATFORM_GSP)) && !defined(NVWATCH) +#include "nvoc/prelude.h" +#endif + +#define REG_DRF_SHIFT(drf) ((0?drf) % 32) +#define REG_DRF_MASK(drf) (0xFFFFFFFF>>(31-((1?drf) % 32)+((0?drf) % 32))) +#define REG_DRF_DEF(d,r,f,c) ((NV ## d ## r ## f ## c)<>REG_DRF_SHIFT(NV ## d ## r ## f))®_DRF_MASK(NV ## d ## r ## f)) +#define REG_DRF_SHIFTMASK(drf) (REG_DRF_MASK(drf)<<(REG_DRF_SHIFT(drf))) +#define REG_DRF_WIDTH(drf) ((1?drf) - (0?drf) + 1) + +#if (defined(NVRM) || defined(RMCFG_FEATURE_PLATFORM_GSP)) && !defined(NVWATCH) +#define REG_RD08(ap, addr) regaprtReadReg08 (staticCast(ap, RegisterAperture), addr) +#define REG_RD16(ap, addr) regaprtReadReg16 (staticCast(ap, RegisterAperture), addr) +#define REG_RD32(ap, addr) regaprtReadReg32 (staticCast(ap, RegisterAperture), addr) +#define REG_WR08(ap, addr, val) regaprtWriteReg08 (staticCast(ap, RegisterAperture), addr, val) +#define REG_WR16(ap, addr, val) regaprtWriteReg16 (staticCast(ap, RegisterAperture), addr, val) +#define REG_WR32(ap, addr, val) regaprtWriteReg32 (staticCast(ap, RegisterAperture), addr, val) +#define REG_WR32_UC(ap, addr, val) regaprtWriteReg32Uc(staticCast(ap, RegisterAperture), addr, val) +#define REG_VALID(ap, addr) regaprtIsRegValid (staticCast(ap, RegisterAperture), addr) + +#ifdef NVOC_IOACCESS_H_PRIVATE_ACCESS_ALLOWED +#define PRIVATE_FIELD(x) x +#else +#define PRIVATE_FIELD(x) NVOC_PRIVATE_FIELD(x) +#endif +struct RegisterAperture { + const struct NVOC_RTTI *__nvoc_rtti; + struct RegisterAperture *__nvoc_pbase_RegisterAperture; + NvU8 (*__regaprtReadReg08__)(struct RegisterAperture *, NvU32); + NvU16 (*__regaprtReadReg16__)(struct RegisterAperture *, NvU32); + NvU32 (*__regaprtReadReg32__)(struct RegisterAperture *, NvU32); + void (*__regaprtWriteReg08__)(struct RegisterAperture *, NvU32, NvV8); + void (*__regaprtWriteReg16__)(struct RegisterAperture *, NvU32, NvV16); + void (*__regaprtWriteReg32__)(struct RegisterAperture *, NvU32, NvV32); + void (*__regaprtWriteReg32Uc__)(struct RegisterAperture *, NvU32, NvV32); + NvBool (*__regaprtIsRegValid__)(struct RegisterAperture *, NvU32); +}; + +#ifndef __NVOC_CLASS_RegisterAperture_TYPEDEF__ +#define __NVOC_CLASS_RegisterAperture_TYPEDEF__ +typedef struct RegisterAperture RegisterAperture; +#endif /* __NVOC_CLASS_RegisterAperture_TYPEDEF__ */ + +#ifndef __nvoc_class_id_RegisterAperture +#define __nvoc_class_id_RegisterAperture 0xfcaf2e +#endif /* __nvoc_class_id_RegisterAperture */ + +extern const struct NVOC_CLASS_DEF __nvoc_class_def_RegisterAperture; + +#define __staticCast_RegisterAperture(pThis) \ + ((pThis)->__nvoc_pbase_RegisterAperture) + +#ifdef __nvoc_ioaccess_h_disabled +#define __dynamicCast_RegisterAperture(pThis) ((RegisterAperture*)NULL) +#else //__nvoc_ioaccess_h_disabled +#define __dynamicCast_RegisterAperture(pThis) \ + ((RegisterAperture*)__nvoc_dynamicCast(staticCast((pThis), Dynamic), classInfo(RegisterAperture))) +#endif //__nvoc_ioaccess_h_disabled + + +NV_STATUS __nvoc_objCreateDynamic_RegisterAperture(RegisterAperture**, Dynamic*, NvU32, va_list); + +NV_STATUS __nvoc_objCreate_RegisterAperture(RegisterAperture**, Dynamic*, NvU32); +#define __objCreate_RegisterAperture(ppNewObj, pParent, createFlags) \ + __nvoc_objCreate_RegisterAperture((ppNewObj), staticCast((pParent), Dynamic), (createFlags)) + +#define regaprtReadReg08(pAperture, addr) regaprtReadReg08_DISPATCH(pAperture, addr) +#define regaprtReadReg16(pAperture, addr) regaprtReadReg16_DISPATCH(pAperture, addr) +#define regaprtReadReg32(pAperture, addr) regaprtReadReg32_DISPATCH(pAperture, addr) +#define regaprtWriteReg08(pAperture, addr, value) regaprtWriteReg08_DISPATCH(pAperture, addr, value) +#define regaprtWriteReg16(pAperture, addr, value) regaprtWriteReg16_DISPATCH(pAperture, addr, value) +#define regaprtWriteReg32(pAperture, addr, value) regaprtWriteReg32_DISPATCH(pAperture, addr, value) +#define regaprtWriteReg32Uc(pAperture, addr, value) regaprtWriteReg32Uc_DISPATCH(pAperture, addr, value) +#define regaprtIsRegValid(pAperture, addr) regaprtIsRegValid_DISPATCH(pAperture, addr) +static inline NvU8 regaprtReadReg08_DISPATCH(struct RegisterAperture *pAperture, NvU32 addr) { + return pAperture->__regaprtReadReg08__(pAperture, addr); +} + +static inline NvU16 regaprtReadReg16_DISPATCH(struct RegisterAperture *pAperture, NvU32 addr) { + return pAperture->__regaprtReadReg16__(pAperture, addr); +} + +static inline NvU32 regaprtReadReg32_DISPATCH(struct RegisterAperture *pAperture, NvU32 addr) { + return pAperture->__regaprtReadReg32__(pAperture, addr); +} + +static inline void regaprtWriteReg08_DISPATCH(struct RegisterAperture *pAperture, NvU32 addr, NvV8 value) { + pAperture->__regaprtWriteReg08__(pAperture, addr, value); +} + +static inline void regaprtWriteReg16_DISPATCH(struct RegisterAperture *pAperture, NvU32 addr, NvV16 value) { + pAperture->__regaprtWriteReg16__(pAperture, addr, value); +} + +static inline void regaprtWriteReg32_DISPATCH(struct RegisterAperture *pAperture, NvU32 addr, NvV32 value) { + pAperture->__regaprtWriteReg32__(pAperture, addr, value); +} + +static inline void regaprtWriteReg32Uc_DISPATCH(struct RegisterAperture *pAperture, NvU32 addr, NvV32 value) { + pAperture->__regaprtWriteReg32Uc__(pAperture, addr, value); +} + +static inline NvBool regaprtIsRegValid_DISPATCH(struct RegisterAperture *pAperture, NvU32 addr) { + return pAperture->__regaprtIsRegValid__(pAperture, addr); +} + +#undef PRIVATE_FIELD + + +// +// TODO: Remove the wrapper structure WAR once NVOC supports in-place object construction +// The proxy structure was introduced to avoid major refactoring until the feature is implemented +// Also fix IoAperture getters +// Use the interface class in NVWATCH once NVOC is enabled there +// +#else // (defined(NVRM) || defined(RMCFG_FEATURE_PLATFORM_GSP)) && !defined(NVWATCH) +typedef struct IO_DEVICE IO_DEVICE; +typedef struct IO_APERTURE IO_APERTURE; + +typedef NvU8 ReadReg008Fn(IO_APERTURE *a, NvU32 addr); +typedef NvU16 ReadReg016Fn(IO_APERTURE *a, NvU32 addr); +typedef NvU32 ReadReg032Fn(IO_APERTURE *a, NvU32 addr); +typedef void WriteReg008Fn(IO_APERTURE *a, NvU32 addr, NvV8 value); +typedef void WriteReg016Fn(IO_APERTURE *a, NvU32 addr, NvV16 value); +typedef void WriteReg032Fn(IO_APERTURE *a, NvU32 addr, NvV32 value); +typedef NvBool ValidRegFn(IO_APERTURE *a, NvU32 addr); + +#define REG_RD08(ap, addr) (ap)->pDevice->pReadReg008Fn((ap), (addr)) +#define REG_RD16(ap, addr) (ap)->pDevice->pReadReg016Fn((ap), (addr)) +#define REG_RD32(ap, addr) (ap)->pDevice->pReadReg032Fn((ap), (addr)) +#define REG_WR08(ap, addr, val) (ap)->pDevice->pWriteReg008Fn((ap), (addr), (val)) +#define REG_WR16(ap, addr, val) (ap)->pDevice->pWriteReg016Fn((ap), (addr), (val)) +#define REG_WR32(ap, addr, val) (ap)->pDevice->pWriteReg032Fn((ap), (addr), (val)) +#define REG_WR32_UC(ap, addr, val) (ap)->pDevice->pWriteReg032UcFn((ap), (addr), (val)) +#define REG_VALID(ap, addr) (ap)->pDevice->pValidRegFn((ap), (addr)) + +// Get the address of a register given the Aperture and offset. +#define REG_GET_ADDR(ap, offset) ((ap)->baseAddress + (offset)) + +struct IO_DEVICE +{ + ReadReg008Fn *pReadReg008Fn; + ReadReg016Fn *pReadReg016Fn; + ReadReg032Fn *pReadReg032Fn; + WriteReg008Fn *pWriteReg008Fn; + WriteReg016Fn *pWriteReg016Fn; + WriteReg032Fn *pWriteReg032Fn; + WriteReg032Fn *pWriteReg032UcFn; + ValidRegFn *pValidRegFn; +}; + +struct IO_APERTURE +{ + IO_DEVICE *pDevice; // Pointer to module specific IO_DEVICE + NvU32 baseAddress; // register base address + NvU32 length; // length of aperture +}; + +NV_STATUS ioaccessInitIOAperture +( + IO_APERTURE *pAperture, + IO_APERTURE *pParentAperture, + IO_DEVICE *pDevice, + NvU32 offset, + NvU32 length +); +#endif // (defined(NVRM) || defined(RMCFG_FEATURE_PLATFORM_GSP)) && !defined(NVWATCH) + + +// +// Macros for register I/O +// + +#define REG_FLD_WR_DRF_NUM(ap,d,r,f,n) REG_WR32(ap,NV##d##r,(REG_RD32(ap,NV##d##r)&~(REG_DRF_MASK(NV##d##r##f)<>REG_DRF_SHIFT(NV ## d ## r ## f))®_DRF_MASK(NV ## d ## r ## f)) +#define REG_FLD_TEST_DRF_DEF(ap,d,r,f,c) (REG_RD_DRF(ap,d, r, f) == NV##d##r##f##c) +#define REG_FLD_TEST_DRF_NUM(ap,d,r,f,n) (REG_RD_DRF(ap,d, r, f) == n) +#define REG_FLD_IDX_TEST_DRF_DEF(ap,d,r,f,c,i) (REG_IDX_RD_DRF(ap, d, r, i, f) == NV##d##r##f##c) + +// Read/write a field or entire register of which there are several copies each accessed via an index +#define REG_IDX_WR_DRF_NUM(ap,d,r,i,f,n) REG_WR32(ap,NV ## d ## r(i), REG_DRF_NUM(d,r,f,n)) +#define REG_IDX_WR_DRF_DEF(ap,d,r,i,f,c) REG_WR32(ap,NV ## d ## r(i), REG_DRF_DEF(d,r,f,c)) +#define REG_FLD_IDX_WR_DRF_NUM(ap,d,r,i,f,n) REG_WR32(ap,NV##d##r(i),(REG_RD32(ap,NV##d##r(i))&~(REG_DRF_MASK(NV##d##r##f)<>REG_DRF_SHIFT(NV ## d ## r ## f))®_DRF_MASK(NV ## d ## r ## f)) +#define REG_RD_DRF_IDX(ap,d,r,f,i) (((REG_RD32(ap,NV ## d ## r))>>REG_DRF_SHIFT(NV ## d ## r ## f(i)))®_DRF_MASK(NV ## d ## r ## f(i))) +#define REG_IDX_OFFSET_RD_DRF(ap,d,r,i,o,f) (((REG_RD32(ap,NV ## d ## r(i,o)))>>REG_DRF_SHIFT(NV ## d ## r ## f))®_DRF_MASK(NV ## d ## r ## f)) + +#endif // _IO_ACCESS_H_ + +#ifdef __cplusplus +} // extern "C" +#endif +#endif // _G_IOACCESS_NVOC_H_ diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/generated/g_journal_nvoc.c nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_journal_nvoc.c --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/generated/g_journal_nvoc.c 2023-10-25 20:27:03.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_journal_nvoc.c 2024-03-05 22:18:20.000000000 +0000 @@ -134,13 +134,16 @@ Object *pParentObj; OBJRCDB *pThis; - pThis = portMemAllocNonPaged(sizeof(OBJRCDB)); - if (pThis == NULL) return NV_ERR_NO_MEMORY; + status = __nvoc_handleObjCreateMemAlloc(createFlags, sizeof(OBJRCDB), (void**)&pThis, (void**)ppThis); + if (status != NV_OK) + return status; portMemSet(pThis, 0, sizeof(OBJRCDB)); __nvoc_initRtti(staticCast(pThis, Dynamic), &__nvoc_class_def_OBJRCDB); + pThis->__nvoc_base_Object.createFlags = createFlags; + if (pParent != NULL && !(createFlags & NVOC_OBJ_CREATE_FLAGS_PARENT_HALSPEC_ONLY)) { pParentObj = dynamicCast(pParent, Object); @@ -156,11 +159,17 @@ if (status != NV_OK) goto __nvoc_objCreate_OBJRCDB_cleanup; *ppThis = pThis; + return NV_OK; __nvoc_objCreate_OBJRCDB_cleanup: // do not call destructors here since the constructor already called them - portMemFree(pThis); + if (createFlags & NVOC_OBJ_CREATE_FLAGS_IN_PLACE_CONSTRUCT) + portMemSet(pThis, 0, sizeof(OBJRCDB)); + else + portMemFree(pThis); + + // coverity[leaked_storage:FALSE] return status; } diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/generated/g_journal_nvoc.h nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_journal_nvoc.h --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/generated/g_journal_nvoc.h 2023-10-25 20:27:03.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_journal_nvoc.h 2024-03-05 22:18:21.000000000 +0000 @@ -346,25 +346,26 @@ #define rcdbDestroyRingBuffer(pRcdb, type) rcdbDestroyRingBuffer_IMPL(pRcdb, type) #endif //__nvoc_journal_h_disabled -void rcdbAddRecToRingBuffer_IMPL(struct OBJGPU *pGpu, struct OBJRCDB *pRcdb, RMCD_RECORD_TYPE type, NvU32 recordSize, NvU8 *pRecord); +RmRCCommonJournal_RECORD *rcdbAddRecToRingBuffer_IMPL(struct OBJGPU *pGpu, struct OBJRCDB *pRcdb, RMCD_RECORD_TYPE type, NvU32 recordSize, NvU8 *pRecord); #ifdef __nvoc_journal_h_disabled -static inline void rcdbAddRecToRingBuffer(struct OBJGPU *pGpu, struct OBJRCDB *pRcdb, RMCD_RECORD_TYPE type, NvU32 recordSize, NvU8 *pRecord) { +static inline RmRCCommonJournal_RECORD *rcdbAddRecToRingBuffer(struct OBJGPU *pGpu, struct OBJRCDB *pRcdb, RMCD_RECORD_TYPE type, NvU32 recordSize, NvU8 *pRecord) { NV_ASSERT_FAILED_PRECOMP("OBJRCDB was disabled!"); + return NULL; } #else //__nvoc_journal_h_disabled #define rcdbAddRecToRingBuffer(pGpu, pRcdb, type, recordSize, pRecord) rcdbAddRecToRingBuffer_IMPL(pGpu, pRcdb, type, recordSize, pRecord) #endif //__nvoc_journal_h_disabled -NvU32 rcdbGetOcaRecordSize_IMPL(struct OBJRCDB *pRcdb, RMCD_RECORD_TYPE type); +NvU32 rcdbGetOcaRecordSizeWithHeader_IMPL(struct OBJRCDB *pRcdb, RMCD_RECORD_TYPE type); #ifdef __nvoc_journal_h_disabled -static inline NvU32 rcdbGetOcaRecordSize(struct OBJRCDB *pRcdb, RMCD_RECORD_TYPE type) { +static inline NvU32 rcdbGetOcaRecordSizeWithHeader(struct OBJRCDB *pRcdb, RMCD_RECORD_TYPE type) { NV_ASSERT_FAILED_PRECOMP("OBJRCDB was disabled!"); return 0; } #else //__nvoc_journal_h_disabled -#define rcdbGetOcaRecordSize(pRcdb, type) rcdbGetOcaRecordSize_IMPL(pRcdb, type) +#define rcdbGetOcaRecordSizeWithHeader(pRcdb, type) rcdbGetOcaRecordSizeWithHeader_IMPL(pRcdb, type) #endif //__nvoc_journal_h_disabled NvU32 rcdbDumpJournal_IMPL(struct OBJRCDB *pRcdb, struct OBJGPU *pGpu, PRB_ENCODER *pPrbEnc, NVD_STATE *pNvDumpState, const PRB_FIELD_DESC *pFieldDesc); @@ -433,17 +434,28 @@ #define rcdbGetRcDiagRecBoundaries(pRcdb, arg0, arg1, arg2, arg3) rcdbGetRcDiagRecBoundaries_IMPL(pRcdb, arg0, arg1, arg2, arg3) #endif //__nvoc_journal_h_disabled -NV_STATUS rcdbAddRcDiagRec_IMPL(struct OBJGPU *pGpu, struct OBJRCDB *pRcdb, RmRcDiag_RECORD *arg0); +RmRCCommonJournal_RECORD *rcdbAddRcDiagRec_IMPL(struct OBJGPU *pGpu, struct OBJRCDB *pRcdb, RmRcDiag_RECORD *arg0); #ifdef __nvoc_journal_h_disabled -static inline NV_STATUS rcdbAddRcDiagRec(struct OBJGPU *pGpu, struct OBJRCDB *pRcdb, RmRcDiag_RECORD *arg0) { +static inline RmRCCommonJournal_RECORD *rcdbAddRcDiagRec(struct OBJGPU *pGpu, struct OBJRCDB *pRcdb, RmRcDiag_RECORD *arg0) { NV_ASSERT_FAILED_PRECOMP("OBJRCDB was disabled!"); - return NV_ERR_NOT_SUPPORTED; + return NULL; } #else //__nvoc_journal_h_disabled #define rcdbAddRcDiagRec(pGpu, pRcdb, arg0) rcdbAddRcDiagRec_IMPL(pGpu, pRcdb, arg0) #endif //__nvoc_journal_h_disabled +RmRCCommonJournal_RECORD *rcdbAddRcDiagRecFromGsp_IMPL(struct OBJGPU *pGpu, struct OBJRCDB *pRcdb, RmRCCommonJournal_RECORD *arg0, RmRcDiag_RECORD *arg1); + +#ifdef __nvoc_journal_h_disabled +static inline RmRCCommonJournal_RECORD *rcdbAddRcDiagRecFromGsp(struct OBJGPU *pGpu, struct OBJRCDB *pRcdb, RmRCCommonJournal_RECORD *arg0, RmRcDiag_RECORD *arg1) { + NV_ASSERT_FAILED_PRECOMP("OBJRCDB was disabled!"); + return NULL; +} +#else //__nvoc_journal_h_disabled +#define rcdbAddRcDiagRecFromGsp(pGpu, pRcdb, arg0, arg1) rcdbAddRcDiagRecFromGsp_IMPL(pGpu, pRcdb, arg0, arg1) +#endif //__nvoc_journal_h_disabled + NV_STATUS rcdbGetRcDiagRec_IMPL(struct OBJRCDB *pRcdb, NvU16 arg0, RmRCCommonJournal_RECORD **arg1, NvU32 arg2, NvU32 arg3); #ifdef __nvoc_journal_h_disabled diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/generated/g_kern_bus_nvoc.c nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_kern_bus_nvoc.c --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/generated/g_kern_bus_nvoc.c 2023-10-25 20:27:03.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_kern_bus_nvoc.c 2024-03-05 22:18:21.000000000 +0000 @@ -98,16 +98,12 @@ return kbusStateUnload(pGpu, (struct KernelBus *)(((unsigned char *)pKernelBus) - __nvoc_rtti_KernelBus_OBJENGSTATE.offset), flags); } -static NV_STATUS __nvoc_thunk_KernelBus_engstateStatePostUnload(OBJGPU *pGpu, struct OBJENGSTATE *pKernelBus, NvU32 arg0) { - return kbusStatePostUnload(pGpu, (struct KernelBus *)(((unsigned char *)pKernelBus) - __nvoc_rtti_KernelBus_OBJENGSTATE.offset), arg0); -} - static void __nvoc_thunk_KernelBus_engstateStateDestroy(OBJGPU *pGpu, struct OBJENGSTATE *pKernelBus) { kbusStateDestroy(pGpu, (struct KernelBus *)(((unsigned char *)pKernelBus) - __nvoc_rtti_KernelBus_OBJENGSTATE.offset)); } -static NV_STATUS __nvoc_thunk_OBJENGSTATE_kbusReconcileTunableState(POBJGPU pGpu, struct KernelBus *pEngstate, void *pTunableState) { - return engstateReconcileTunableState(pGpu, (struct OBJENGSTATE *)(((unsigned char *)pEngstate) + __nvoc_rtti_KernelBus_OBJENGSTATE.offset), pTunableState); +static NV_STATUS __nvoc_thunk_OBJENGSTATE_kbusStatePostUnload(POBJGPU pGpu, struct KernelBus *pEngstate, NvU32 arg0) { + return engstateStatePostUnload(pGpu, (struct OBJENGSTATE *)(((unsigned char *)pEngstate) + __nvoc_rtti_KernelBus_OBJENGSTATE.offset), arg0); } static NV_STATUS __nvoc_thunk_OBJENGSTATE_kbusStateInitUnlocked(POBJGPU pGpu, struct KernelBus *pEngstate) { @@ -122,26 +118,6 @@ return engstateStatePreInitUnlocked(pGpu, (struct OBJENGSTATE *)(((unsigned char *)pEngstate) + __nvoc_rtti_KernelBus_OBJENGSTATE.offset)); } -static NV_STATUS __nvoc_thunk_OBJENGSTATE_kbusGetTunableState(POBJGPU pGpu, struct KernelBus *pEngstate, void *pTunableState) { - return engstateGetTunableState(pGpu, (struct OBJENGSTATE *)(((unsigned char *)pEngstate) + __nvoc_rtti_KernelBus_OBJENGSTATE.offset), pTunableState); -} - -static NV_STATUS __nvoc_thunk_OBJENGSTATE_kbusCompareTunableState(POBJGPU pGpu, struct KernelBus *pEngstate, void *pTunables1, void *pTunables2) { - return engstateCompareTunableState(pGpu, (struct OBJENGSTATE *)(((unsigned char *)pEngstate) + __nvoc_rtti_KernelBus_OBJENGSTATE.offset), pTunables1, pTunables2); -} - -static void __nvoc_thunk_OBJENGSTATE_kbusFreeTunableState(POBJGPU pGpu, struct KernelBus *pEngstate, void *pTunableState) { - engstateFreeTunableState(pGpu, (struct OBJENGSTATE *)(((unsigned char *)pEngstate) + __nvoc_rtti_KernelBus_OBJENGSTATE.offset), pTunableState); -} - -static NV_STATUS __nvoc_thunk_OBJENGSTATE_kbusAllocTunableState(POBJGPU pGpu, struct KernelBus *pEngstate, void **ppTunableState) { - return engstateAllocTunableState(pGpu, (struct OBJENGSTATE *)(((unsigned char *)pEngstate) + __nvoc_rtti_KernelBus_OBJENGSTATE.offset), ppTunableState); -} - -static NV_STATUS __nvoc_thunk_OBJENGSTATE_kbusSetTunableState(POBJGPU pGpu, struct KernelBus *pEngstate, void *pTunableState) { - return engstateSetTunableState(pGpu, (struct OBJENGSTATE *)(((unsigned char *)pEngstate) + __nvoc_rtti_KernelBus_OBJENGSTATE.offset), pTunableState); -} - static NvBool __nvoc_thunk_OBJENGSTATE_kbusIsPresent(POBJGPU pGpu, struct KernelBus *pEngstate) { return engstateIsPresent(pGpu, (struct OBJENGSTATE *)(((unsigned char *)pEngstate) + __nvoc_rtti_KernelBus_OBJENGSTATE.offset)); } @@ -212,6 +188,17 @@ pThis->bBar2InternalOnly = ((NvBool)(0 != 0)); } + // Hal field -- bIsEntireBar2RegionVirtuallyAddressible + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ + { + pThis->bIsEntireBar2RegionVirtuallyAddressible = ((NvBool)(0 == 0)); + } + // default + else + { + pThis->bIsEntireBar2RegionVirtuallyAddressible = ((NvBool)(0 != 0)); + } + // Hal field -- bSkipBar2TestOnGc6Exit // default { @@ -271,109 +258,87 @@ pThis->__kbusConstructEngine__ = &kbusConstructEngine_IMPL; // Hal function -- kbusStatePreInitLocked - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x11f0ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 | GH100 */ - { - pThis->__kbusStatePreInitLocked__ = &kbusStatePreInitLocked_GM107; - } + pThis->__kbusStatePreInitLocked__ = &kbusStatePreInitLocked_GM107; pThis->__kbusStateInitLocked__ = &kbusStateInitLocked_IMPL; // Hal function -- kbusStatePreLoad - if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000002UL) )) /* RmVariantHal: PF_KERNEL_ONLY */ - { - pThis->__kbusStatePreLoad__ = &kbusStatePreLoad_56cd7a; - } + pThis->__kbusStatePreLoad__ = &kbusStatePreLoad_56cd7a; // Hal function -- kbusStateLoad - if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000002UL) )) /* RmVariantHal: PF_KERNEL_ONLY */ - { - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x11f0ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 | GH100 */ - { - pThis->__kbusStateLoad__ = &kbusStateLoad_GM107; - } - } + pThis->__kbusStateLoad__ = &kbusStateLoad_GM107; // Hal function -- kbusStatePostLoad - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x11f0ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 | GH100 */ - { - pThis->__kbusStatePostLoad__ = &kbusStatePostLoad_GM107; - } + pThis->__kbusStatePostLoad__ = &kbusStatePostLoad_GM107; // Hal function -- kbusStatePreUnload - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x11f0ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 | GH100 */ - { - pThis->__kbusStatePreUnload__ = &kbusStatePreUnload_GM107; - } + pThis->__kbusStatePreUnload__ = &kbusStatePreUnload_GM107; // Hal function -- kbusStateUnload - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x11f0ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 | GH100 */ - { - pThis->__kbusStateUnload__ = &kbusStateUnload_GM107; - } - - // Hal function -- kbusStatePostUnload - if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000002UL) )) /* RmVariantHal: PF_KERNEL_ONLY */ - { - pThis->__kbusStatePostUnload__ = &kbusStatePostUnload_56cd7a; - } + pThis->__kbusStateUnload__ = &kbusStateUnload_GM107; // Hal function -- kbusStateDestroy - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x11f0ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 | GH100 */ - { - pThis->__kbusStateDestroy__ = &kbusStateDestroy_GM107; - } + pThis->__kbusStateDestroy__ = &kbusStateDestroy_GM107; // Hal function -- kbusTeardownBar2CpuAperture - if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000002UL) )) /* RmVariantHal: PF_KERNEL_ONLY */ + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ { - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x01f0ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 */ - { - pThis->__kbusTeardownBar2CpuAperture__ = &kbusTeardownBar2CpuAperture_GM107; - } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ - { - pThis->__kbusTeardownBar2CpuAperture__ = &kbusTeardownBar2CpuAperture_GH100; - } + pThis->__kbusTeardownBar2CpuAperture__ = &kbusTeardownBar2CpuAperture_GH100; + } + else + { + pThis->__kbusTeardownBar2CpuAperture__ = &kbusTeardownBar2CpuAperture_GM107; } // Hal function -- kbusGetP2PMailboxAttributes - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x01f0ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 */ + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ { - pThis->__kbusGetP2PMailboxAttributes__ = &kbusGetP2PMailboxAttributes_GM200; + pThis->__kbusGetP2PMailboxAttributes__ = &kbusGetP2PMailboxAttributes_GH100; } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ + else { - pThis->__kbusGetP2PMailboxAttributes__ = &kbusGetP2PMailboxAttributes_GH100; + pThis->__kbusGetP2PMailboxAttributes__ = &kbusGetP2PMailboxAttributes_GM200; } // Hal function -- kbusCreateP2PMapping - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x01f0ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 */ + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ { - pThis->__kbusCreateP2PMapping__ = &kbusCreateP2PMapping_GP100; + pThis->__kbusCreateP2PMapping__ = &kbusCreateP2PMapping_GH100; } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ + else { - pThis->__kbusCreateP2PMapping__ = &kbusCreateP2PMapping_GH100; + pThis->__kbusCreateP2PMapping__ = &kbusCreateP2PMapping_GP100; } // Hal function -- kbusRemoveP2PMapping - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x01f0ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 */ + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ + { + pThis->__kbusRemoveP2PMapping__ = &kbusRemoveP2PMapping_GH100; + } + else { pThis->__kbusRemoveP2PMapping__ = &kbusRemoveP2PMapping_GP100; } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ + + // Hal function -- kbusGetEgmPeerId + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ { - pThis->__kbusRemoveP2PMapping__ = &kbusRemoveP2PMapping_GH100; + pThis->__kbusGetEgmPeerId__ = &kbusGetEgmPeerId_GH100; + } + // default + else + { + pThis->__kbusGetEgmPeerId__ = &kbusGetEgmPeerId_56cd7a; } // Hal function -- kbusGetPeerId - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x01f0ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 */ + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ { - pThis->__kbusGetPeerId__ = &kbusGetPeerId_GP100; + pThis->__kbusGetPeerId__ = &kbusGetPeerId_GH100; } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ + else { - pThis->__kbusGetPeerId__ = &kbusGetPeerId_GH100; + pThis->__kbusGetPeerId__ = &kbusGetPeerId_GP100; } // Hal function -- kbusGetNvSwitchPeerId @@ -388,70 +353,67 @@ } // Hal function -- kbusGetUnusedPciePeerId - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x11f0fc00UL) )) /* ChipHal: GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 | GH100 */ + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x000003e0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 */ { - pThis->__kbusGetUnusedPciePeerId__ = &kbusGetUnusedPciePeerId_GM107; + pThis->__kbusGetUnusedPciePeerId__ = &kbusGetUnusedPciePeerId_TU102; } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x000003e0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 */ + else { - pThis->__kbusGetUnusedPciePeerId__ = &kbusGetUnusedPciePeerId_TU102; + pThis->__kbusGetUnusedPciePeerId__ = &kbusGetUnusedPciePeerId_GM107; } // Hal function -- kbusIsPeerIdValid - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x01f0ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 */ + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ { - pThis->__kbusIsPeerIdValid__ = &kbusIsPeerIdValid_GP100; + pThis->__kbusIsPeerIdValid__ = &kbusIsPeerIdValid_GH100; } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ + else { - pThis->__kbusIsPeerIdValid__ = &kbusIsPeerIdValid_GH100; + pThis->__kbusIsPeerIdValid__ = &kbusIsPeerIdValid_GP100; } // Hal function -- kbusGetNvlinkP2PPeerId - if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000002UL) )) /* RmVariantHal: PF_KERNEL_ONLY */ + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x00000060UL) )) /* ChipHal: TU102 | TU104 */ + { + pThis->__kbusGetNvlinkP2PPeerId__ = &kbusGetNvlinkP2PPeerId_GP100; + } + else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x00000380UL) )) /* ChipHal: TU106 | TU116 | TU117 */ + { + pThis->__kbusGetNvlinkP2PPeerId__ = &kbusGetNvlinkP2PPeerId_56cd7a; + } + else { - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x00000060UL) )) /* ChipHal: TU102 | TU104 */ - { - pThis->__kbusGetNvlinkP2PPeerId__ = &kbusGetNvlinkP2PPeerId_GP100; - } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x11f0fc00UL) )) /* ChipHal: GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 | GH100 */ - { - pThis->__kbusGetNvlinkP2PPeerId__ = &kbusGetNvlinkP2PPeerId_GA100; - } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x00000380UL) )) /* ChipHal: TU106 | TU116 | TU117 */ - { - pThis->__kbusGetNvlinkP2PPeerId__ = &kbusGetNvlinkP2PPeerId_56cd7a; - } + pThis->__kbusGetNvlinkP2PPeerId__ = &kbusGetNvlinkP2PPeerId_GA100; } // Hal function -- kbusWriteP2PWmbTag - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x01f0ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 */ + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ { - pThis->__kbusWriteP2PWmbTag__ = &kbusWriteP2PWmbTag_GM200; + pThis->__kbusWriteP2PWmbTag__ = &kbusWriteP2PWmbTag_GH100; } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ + else { - pThis->__kbusWriteP2PWmbTag__ = &kbusWriteP2PWmbTag_GH100; + pThis->__kbusWriteP2PWmbTag__ = &kbusWriteP2PWmbTag_GM200; } // Hal function -- kbusSetupP2PDomainAccess - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x01f0ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 */ + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ { - pThis->__kbusSetupP2PDomainAccess__ = &kbusSetupP2PDomainAccess_GM200; + pThis->__kbusSetupP2PDomainAccess__ = &kbusSetupP2PDomainAccess_GH100; } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ + else { - pThis->__kbusSetupP2PDomainAccess__ = &kbusSetupP2PDomainAccess_GH100; + pThis->__kbusSetupP2PDomainAccess__ = &kbusSetupP2PDomainAccess_GM200; } // Hal function -- kbusNeedWarForBug999673 - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x01f0ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 */ + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ { - pThis->__kbusNeedWarForBug999673__ = &kbusNeedWarForBug999673_GM200; + pThis->__kbusNeedWarForBug999673__ = &kbusNeedWarForBug999673_491d52; } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ + else { - pThis->__kbusNeedWarForBug999673__ = &kbusNeedWarForBug999673_491d52; + pThis->__kbusNeedWarForBug999673__ = &kbusNeedWarForBug999673_GM200; } // Hal function -- kbusCreateP2PMappingForC2C @@ -477,13 +439,79 @@ } // Hal function -- kbusUnreserveP2PPeerIds - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x11f0fc00UL) )) /* ChipHal: GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 | GH100 */ + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x000003e0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 */ + { + pThis->__kbusUnreserveP2PPeerIds__ = &kbusUnreserveP2PPeerIds_46f6a7; + } + else { pThis->__kbusUnreserveP2PPeerIds__ = &kbusUnreserveP2PPeerIds_GP100; } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x000003e0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 */ + + // Hal function -- kbusNeedStaticBar1Mapping + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ { - pThis->__kbusUnreserveP2PPeerIds__ = &kbusUnreserveP2PPeerIds_46f6a7; + pThis->__kbusNeedStaticBar1Mapping__ = &kbusNeedStaticBar1Mapping_GH100; + } + // default + else + { + pThis->__kbusNeedStaticBar1Mapping__ = &kbusNeedStaticBar1Mapping_bf6dfa; + } + + // Hal function -- kbusEnableStaticBar1Mapping + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ + { + pThis->__kbusEnableStaticBar1Mapping__ = &kbusEnableStaticBar1Mapping_GH100; + } + // default + else + { + pThis->__kbusEnableStaticBar1Mapping__ = &kbusEnableStaticBar1Mapping_46f6a7; + } + + // Hal function -- kbusDisableStaticBar1Mapping + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ + { + pThis->__kbusDisableStaticBar1Mapping__ = &kbusDisableStaticBar1Mapping_GH100; + } + // default + else + { + pThis->__kbusDisableStaticBar1Mapping__ = &kbusDisableStaticBar1Mapping_56cd7a; + } + + // Hal function -- kbusGetBar1P2PDmaInfo + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ + { + pThis->__kbusGetBar1P2PDmaInfo__ = &kbusGetBar1P2PDmaInfo_GH100; + } + // default + else + { + pThis->__kbusGetBar1P2PDmaInfo__ = &kbusGetBar1P2PDmaInfo_395e98; + } + + // Hal function -- kbusStaticMapFbAperture + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ + { + pThis->__kbusStaticMapFbAperture__ = &kbusStaticMapFbAperture_GH100; + } + // default + else + { + pThis->__kbusStaticMapFbAperture__ = &kbusStaticMapFbAperture_395e98; + } + + // Hal function -- kbusStaticUnmapFbAperture + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ + { + pThis->__kbusStaticUnmapFbAperture__ = &kbusStaticUnmapFbAperture_GH100; + } + // default + else + { + pThis->__kbusStaticUnmapFbAperture__ = &kbusStaticUnmapFbAperture_395e98; } // Hal function -- kbusCreateP2PMappingForBar1P2P @@ -519,12 +547,34 @@ pThis->__kbusHasPcieBar1P2PMapping__ = &kbusHasPcieBar1P2PMapping_491d52; } + // Hal function -- kbusIsPcieBar1P2PMappingSupported + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ + { + pThis->__kbusIsPcieBar1P2PMappingSupported__ = &kbusIsPcieBar1P2PMappingSupported_GH100; + } + // default + else + { + pThis->__kbusIsPcieBar1P2PMappingSupported__ = &kbusIsPcieBar1P2PMappingSupported_491d52; + } + + // Hal function -- kbusSetupBar1P2PCapability + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ + { + pThis->__kbusSetupBar1P2PCapability__ = &kbusSetupBar1P2PCapability_GH100; + } + // default + else + { + pThis->__kbusSetupBar1P2PCapability__ = &kbusSetupBar1P2PCapability_b3696a; + } + // Hal function -- kbusCheckFlaSupportedAndInit if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000400UL) )) /* ChipHal: GA100 | GH100 */ { pThis->__kbusCheckFlaSupportedAndInit__ = &kbusCheckFlaSupportedAndInit_GA100; } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x01f0fbe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 */ + else { pThis->__kbusCheckFlaSupportedAndInit__ = &kbusCheckFlaSupportedAndInit_ac1694; } @@ -579,7 +629,7 @@ { pThis->__kbusAllocateLegacyFlaVaspace__ = &kbusAllocateLegacyFlaVaspace_GA100; } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x01f0fbe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 */ + else { pThis->__kbusAllocateLegacyFlaVaspace__ = &kbusAllocateLegacyFlaVaspace_395e98; } @@ -589,7 +639,7 @@ { pThis->__kbusAllocateHostManagedFlaVaspace__ = &kbusAllocateHostManagedFlaVaspace_GA100; } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x01f0fbe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 */ + else { pThis->__kbusAllocateHostManagedFlaVaspace__ = &kbusAllocateHostManagedFlaVaspace_395e98; } @@ -614,7 +664,7 @@ { pThis->__kbusGetFlaVaspace__ = &kbusGetFlaVaspace_GA100; } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x01f0fbe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 */ + else { pThis->__kbusGetFlaVaspace__ = &kbusGetFlaVaspace_395e98; } @@ -624,7 +674,7 @@ { pThis->__kbusDestroyHostManagedFlaVaspace__ = &kbusDestroyHostManagedFlaVaspace_GA100; } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x01f0fbe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 */ + else { pThis->__kbusDestroyHostManagedFlaVaspace__ = &kbusDestroyHostManagedFlaVaspace_d44104; } @@ -634,7 +684,7 @@ { pThis->__kbusVerifyFlaRange__ = &kbusVerifyFlaRange_GA100; } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x01f0fbe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 */ + else { pThis->__kbusVerifyFlaRange__ = &kbusVerifyFlaRange_bf6dfa; } @@ -644,7 +694,7 @@ { pThis->__kbusConstructFlaInstBlk__ = &kbusConstructFlaInstBlk_GA100; } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x01f0fbe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 */ + else { pThis->__kbusConstructFlaInstBlk__ = &kbusConstructFlaInstBlk_395e98; } @@ -654,7 +704,7 @@ { pThis->__kbusDestructFlaInstBlk__ = &kbusDestructFlaInstBlk_GA100; } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x01f0fbe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 */ + else { pThis->__kbusDestructFlaInstBlk__ = &kbusDestructFlaInstBlk_d44104; } @@ -664,45 +714,37 @@ { pThis->__kbusValidateFlaBaseAddress__ = &kbusValidateFlaBaseAddress_GA100; } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x01f0fbe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 */ + else { pThis->__kbusValidateFlaBaseAddress__ = &kbusValidateFlaBaseAddress_395e98; } // Hal function -- kbusSetupUnbindFla - if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000002UL) )) /* RmVariantHal: PF_KERNEL_ONLY */ + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x00000400UL) )) /* ChipHal: GA100 */ + { + pThis->__kbusSetupUnbindFla__ = &kbusSetupUnbindFla_GA100; + } + else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ { - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x00000400UL) )) /* ChipHal: GA100 */ - { - pThis->__kbusSetupUnbindFla__ = &kbusSetupUnbindFla_GA100; - } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ - { - pThis->__kbusSetupUnbindFla__ = &kbusSetupUnbindFla_GH100; - } - // default - else - { - pThis->__kbusSetupUnbindFla__ = &kbusSetupUnbindFla_46f6a7; - } + pThis->__kbusSetupUnbindFla__ = &kbusSetupUnbindFla_GH100; + } + else + { + pThis->__kbusSetupUnbindFla__ = &kbusSetupUnbindFla_46f6a7; } // Hal function -- kbusSetupBindFla - if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000002UL) )) /* RmVariantHal: PF_KERNEL_ONLY */ + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x00000400UL) )) /* ChipHal: GA100 */ { - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x00000400UL) )) /* ChipHal: GA100 */ - { - pThis->__kbusSetupBindFla__ = &kbusSetupBindFla_GA100; - } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ - { - pThis->__kbusSetupBindFla__ = &kbusSetupBindFla_GH100; - } - // default - else - { - pThis->__kbusSetupBindFla__ = &kbusSetupBindFla_46f6a7; - } + pThis->__kbusSetupBindFla__ = &kbusSetupBindFla_GA100; + } + else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ + { + pThis->__kbusSetupBindFla__ = &kbusSetupBindFla_GH100; + } + else + { + pThis->__kbusSetupBindFla__ = &kbusSetupBindFla_46f6a7; } // Hal function -- kbusIsDirectMappingAllowed @@ -710,7 +752,7 @@ { pThis->__kbusIsDirectMappingAllowed__ = &kbusIsDirectMappingAllowed_GM107; } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x11f0fc00UL) )) /* ChipHal: GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 | GH100 */ + else { pThis->__kbusIsDirectMappingAllowed__ = &kbusIsDirectMappingAllowed_GA100; } @@ -720,7 +762,7 @@ { pThis->__kbusUseDirectSysmemMap__ = &kbusUseDirectSysmemMap_GM107; } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x11f0fc00UL) )) /* ChipHal: GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 | GH100 */ + else { pThis->__kbusUseDirectSysmemMap__ = &kbusUseDirectSysmemMap_GA100; } @@ -730,7 +772,7 @@ { pThis->__kbusWriteBAR0WindowBase__ = &kbusWriteBAR0WindowBase_GH100; } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x01f0ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 */ + else { pThis->__kbusWriteBAR0WindowBase__ = &kbusWriteBAR0WindowBase_395e98; } @@ -740,7 +782,7 @@ { pThis->__kbusReadBAR0WindowBase__ = &kbusReadBAR0WindowBase_GH100; } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x01f0ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 */ + else { pThis->__kbusReadBAR0WindowBase__ = &kbusReadBAR0WindowBase_13cd8d; } @@ -750,45 +792,50 @@ { pThis->__kbusValidateBAR0WindowBase__ = &kbusValidateBAR0WindowBase_GH100; } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x01f0ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 */ + else { pThis->__kbusValidateBAR0WindowBase__ = &kbusValidateBAR0WindowBase_ceaee8; } // Hal function -- kbusSetBAR0WindowVidOffset - if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000002UL) )) /* RmVariantHal: PF_KERNEL_ONLY */ + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ { - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x01f0ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 */ - { - pThis->__kbusSetBAR0WindowVidOffset__ = &kbusSetBAR0WindowVidOffset_GM107; - } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ - { - pThis->__kbusSetBAR0WindowVidOffset__ = &kbusSetBAR0WindowVidOffset_GH100; - } + pThis->__kbusSetBAR0WindowVidOffset__ = &kbusSetBAR0WindowVidOffset_GH100; + } + else + { + pThis->__kbusSetBAR0WindowVidOffset__ = &kbusSetBAR0WindowVidOffset_GM107; } // Hal function -- kbusGetBAR0WindowVidOffset - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x01f0ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 */ + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ { - pThis->__kbusGetBAR0WindowVidOffset__ = &kbusGetBAR0WindowVidOffset_GM107; + pThis->__kbusGetBAR0WindowVidOffset__ = &kbusGetBAR0WindowVidOffset_GH100; } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ + else { - pThis->__kbusGetBAR0WindowVidOffset__ = &kbusGetBAR0WindowVidOffset_GH100; + pThis->__kbusGetBAR0WindowVidOffset__ = &kbusGetBAR0WindowVidOffset_GM107; } // Hal function -- kbusVerifyBar2 - if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000002UL) )) /* RmVariantHal: PF_KERNEL_ONLY */ + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ + { + pThis->__kbusVerifyBar2__ = &kbusVerifyBar2_GH100; + } + else { - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x01f0ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 */ - { - pThis->__kbusVerifyBar2__ = &kbusVerifyBar2_GM107; - } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ - { - pThis->__kbusVerifyBar2__ = &kbusVerifyBar2_GH100; - } + pThis->__kbusVerifyBar2__ = &kbusVerifyBar2_GM107; + } + + // Hal function -- kbusVerifyCoherentLink + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ + { + pThis->__kbusVerifyCoherentLink__ = &kbusVerifyCoherentLink_GH100; + } + // default + else + { + pThis->__kbusVerifyCoherentLink__ = &kbusVerifyCoherentLink_56cd7a; } // Hal function -- kbusFlushPcieForBar0Doorbell @@ -796,11 +843,22 @@ { pThis->__kbusFlushPcieForBar0Doorbell__ = &kbusFlushPcieForBar0Doorbell_GH100; } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x01f0ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 */ + else { pThis->__kbusFlushPcieForBar0Doorbell__ = &kbusFlushPcieForBar0Doorbell_56cd7a; } + // Hal function -- kbusCreateCoherentCpuMapping + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ + { + pThis->__kbusCreateCoherentCpuMapping__ = &kbusCreateCoherentCpuMapping_GH100; + } + // default + else + { + pThis->__kbusCreateCoherentCpuMapping__ = &kbusCreateCoherentCpuMapping_46f6a7; + } + // Hal function -- kbusMapCoherentCpuMapping if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ { @@ -834,6 +892,17 @@ pThis->__kbusTeardownCoherentCpuMapping__ = &kbusTeardownCoherentCpuMapping_d44104; } + // Hal function -- kbusGetEccCounts + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ + { + pThis->__kbusGetEccCounts__ = &kbusGetEccCounts_GH100; + } + // default + else + { + pThis->__kbusGetEccCounts__ = &kbusGetEccCounts_4a4dee; + } + pThis->__nvoc_base_OBJENGSTATE.__engstateConstructEngine__ = &__nvoc_thunk_KernelBus_engstateConstructEngine; pThis->__nvoc_base_OBJENGSTATE.__engstateStatePreInitLocked__ = &__nvoc_thunk_KernelBus_engstateStatePreInitLocked; @@ -850,11 +919,9 @@ pThis->__nvoc_base_OBJENGSTATE.__engstateStateUnload__ = &__nvoc_thunk_KernelBus_engstateStateUnload; - pThis->__nvoc_base_OBJENGSTATE.__engstateStatePostUnload__ = &__nvoc_thunk_KernelBus_engstateStatePostUnload; - pThis->__nvoc_base_OBJENGSTATE.__engstateStateDestroy__ = &__nvoc_thunk_KernelBus_engstateStateDestroy; - pThis->__kbusReconcileTunableState__ = &__nvoc_thunk_OBJENGSTATE_kbusReconcileTunableState; + pThis->__kbusStatePostUnload__ = &__nvoc_thunk_OBJENGSTATE_kbusStatePostUnload; pThis->__kbusStateInitUnlocked__ = &__nvoc_thunk_OBJENGSTATE_kbusStateInitUnlocked; @@ -862,16 +929,6 @@ pThis->__kbusStatePreInitUnlocked__ = &__nvoc_thunk_OBJENGSTATE_kbusStatePreInitUnlocked; - pThis->__kbusGetTunableState__ = &__nvoc_thunk_OBJENGSTATE_kbusGetTunableState; - - pThis->__kbusCompareTunableState__ = &__nvoc_thunk_OBJENGSTATE_kbusCompareTunableState; - - pThis->__kbusFreeTunableState__ = &__nvoc_thunk_OBJENGSTATE_kbusFreeTunableState; - - pThis->__kbusAllocTunableState__ = &__nvoc_thunk_OBJENGSTATE_kbusAllocTunableState; - - pThis->__kbusSetTunableState__ = &__nvoc_thunk_OBJENGSTATE_kbusSetTunableState; - pThis->__kbusIsPresent__ = &__nvoc_thunk_OBJENGSTATE_kbusIsPresent; } @@ -887,7 +944,7 @@ { return kbusGetP2PWriteMailboxAddressSize_GH100(pGpu); } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x01f0ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 */ + else { return kbusGetP2PWriteMailboxAddressSize_474d46(pGpu); } @@ -912,13 +969,16 @@ KernelBus *pThis; RmHalspecOwner *pRmhalspecowner; - pThis = portMemAllocNonPaged(sizeof(KernelBus)); - if (pThis == NULL) return NV_ERR_NO_MEMORY; + status = __nvoc_handleObjCreateMemAlloc(createFlags, sizeof(KernelBus), (void**)&pThis, (void**)ppThis); + if (status != NV_OK) + return status; portMemSet(pThis, 0, sizeof(KernelBus)); __nvoc_initRtti(staticCast(pThis, Dynamic), &__nvoc_class_def_KernelBus); + pThis->__nvoc_base_OBJENGSTATE.__nvoc_base_Object.createFlags = createFlags; + if (pParent != NULL && !(createFlags & NVOC_OBJ_CREATE_FLAGS_PARENT_HALSPEC_ONLY)) { pParentObj = dynamicCast(pParent, Object); @@ -938,11 +998,17 @@ if (status != NV_OK) goto __nvoc_objCreate_KernelBus_cleanup; *ppThis = pThis; + return NV_OK; __nvoc_objCreate_KernelBus_cleanup: // do not call destructors here since the constructor already called them - portMemFree(pThis); + if (createFlags & NVOC_OBJ_CREATE_FLAGS_IN_PLACE_CONSTRUCT) + portMemSet(pThis, 0, sizeof(KernelBus)); + else + portMemFree(pThis); + + // coverity[leaked_storage:FALSE] return status; } diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/generated/g_kern_bus_nvoc.h nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_kern_bus_nvoc.h --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/generated/g_kern_bus_nvoc.h 2023-10-25 20:27:03.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_kern_bus_nvoc.h 2024-03-05 22:18:22.000000000 +0000 @@ -52,7 +52,7 @@ // // Virtual BAR2 mapping info is shared by tesla and fermi code // -#if defined(NV_UNIX) && defined(NVCPU_X86_64) +#if defined(NV_UNIX) && (defined(NVCPU_X86_64) || defined(NVCPU_AARCH64)) // 64-bit Unix can support many more mappings than some other operating systems: #define BUS_BAR2_MAX_MAPPINGS 200 #else @@ -174,6 +174,19 @@ MAKE_INTRUSIVE_LIST(VirtualBar2MapList, VirtualBar2MapEntry, node); +struct Device; + +#ifndef __NVOC_CLASS_Device_TYPEDEF__ +#define __NVOC_CLASS_Device_TYPEDEF__ +typedef struct Device Device; +#endif /* __NVOC_CLASS_Device_TYPEDEF__ */ + +#ifndef __nvoc_class_id_Device +#define __nvoc_class_id_Device 0xe0ac20 +#endif /* __nvoc_class_id_Device */ + + + #ifdef NVOC_KERN_BUS_H_PRIVATE_ACCESS_ALLOWED #define PRIVATE_FIELD(x) x #else @@ -185,6 +198,13 @@ struct OBJVASPACE *pVAS; NvU64 instBlockBase; MEMORY_DESCRIPTOR *pInstBlkMemDesc; + NvBool bStaticBar1Enabled; + struct { + MEMORY_DESCRIPTOR *pVidMemDesc; + MEMORY_DESCRIPTOR *pDmaMemDesc; + NvU64 base; + NvU64 size; + } staticBar1; }; struct __nvoc_inner_struc_KernelBus_2__ { @@ -214,9 +234,9 @@ NvU32 pageDirSize; NvU32 numPageTbls; NvU32 pageTblSize; + NvBool bIsBar2SizeReduced; NvU32 pageDirInit; NvU32 pageTblInit; - NvU32 cpuVisiblePgTblSize; }; struct __nvoc_inner_struc_KernelBus_3__ { @@ -270,6 +290,7 @@ NvU32 busNvlinkMappingRefcountPerGpu[32]; NvU32 busNvlinkMappingRefcountPerPeerId[8]; NvU32 busNvlinkMappingRefcountPerPeerIdSpa[8]; + NvBool bEgmPeer[8]; }; struct __nvoc_inner_struc_KernelBus_7__ { @@ -303,26 +324,34 @@ NV_STATUS (*__kbusStatePostLoad__)(OBJGPU *, struct KernelBus *, NvU32); NV_STATUS (*__kbusStatePreUnload__)(OBJGPU *, struct KernelBus *, NvU32); NV_STATUS (*__kbusStateUnload__)(OBJGPU *, struct KernelBus *, NvU32); - NV_STATUS (*__kbusStatePostUnload__)(OBJGPU *, struct KernelBus *, NvU32); void (*__kbusStateDestroy__)(OBJGPU *, struct KernelBus *); NV_STATUS (*__kbusTeardownBar2CpuAperture__)(OBJGPU *, struct KernelBus *, NvU32); void (*__kbusGetP2PMailboxAttributes__)(OBJGPU *, struct KernelBus *, NvU32 *, NvU32 *, NvU32 *); NV_STATUS (*__kbusCreateP2PMapping__)(OBJGPU *, struct KernelBus *, OBJGPU *, struct KernelBus *, NvU32 *, NvU32 *, NvU32); NV_STATUS (*__kbusRemoveP2PMapping__)(OBJGPU *, struct KernelBus *, OBJGPU *, struct KernelBus *, NvU32, NvU32, NvU32); + NvU32 (*__kbusGetEgmPeerId__)(OBJGPU *, struct KernelBus *, OBJGPU *); NvU32 (*__kbusGetPeerId__)(OBJGPU *, struct KernelBus *, OBJGPU *); NvU32 (*__kbusGetNvSwitchPeerId__)(OBJGPU *, struct KernelBus *); NvU32 (*__kbusGetUnusedPciePeerId__)(OBJGPU *, struct KernelBus *); NV_STATUS (*__kbusIsPeerIdValid__)(OBJGPU *, struct KernelBus *, NvU32); - NV_STATUS (*__kbusGetNvlinkP2PPeerId__)(OBJGPU *, struct KernelBus *, OBJGPU *, struct KernelBus *, NvU32 *); + NV_STATUS (*__kbusGetNvlinkP2PPeerId__)(OBJGPU *, struct KernelBus *, OBJGPU *, struct KernelBus *, NvU32 *, NvU32); void (*__kbusWriteP2PWmbTag__)(OBJGPU *, struct KernelBus *, NvU32, NvU64); RmPhysAddr (*__kbusSetupP2PDomainAccess__)(OBJGPU *, struct KernelBus *, OBJGPU *, PMEMORY_DESCRIPTOR *); NvBool (*__kbusNeedWarForBug999673__)(OBJGPU *, struct KernelBus *, OBJGPU *); NV_STATUS (*__kbusCreateP2PMappingForC2C__)(OBJGPU *, struct KernelBus *, OBJGPU *, struct KernelBus *, NvU32 *, NvU32 *, NvU32); NV_STATUS (*__kbusRemoveP2PMappingForC2C__)(OBJGPU *, struct KernelBus *, OBJGPU *, struct KernelBus *, NvU32, NvU32, NvU32); NV_STATUS (*__kbusUnreserveP2PPeerIds__)(OBJGPU *, struct KernelBus *, NvU32); + NvBool (*__kbusNeedStaticBar1Mapping__)(OBJGPU *, struct KernelBus *); + NV_STATUS (*__kbusEnableStaticBar1Mapping__)(OBJGPU *, struct KernelBus *, NvU64, NvU32); + NV_STATUS (*__kbusDisableStaticBar1Mapping__)(OBJGPU *, struct KernelBus *, NvU32); + NV_STATUS (*__kbusGetBar1P2PDmaInfo__)(OBJGPU *, OBJGPU *, struct KernelBus *, NvU64 *, NvU64 *); + NV_STATUS (*__kbusStaticMapFbAperture__)(OBJGPU *, struct KernelBus *, MEMORY_DESCRIPTOR *, NvU64, NvU64 *, NvU64 *, NvU32); + NV_STATUS (*__kbusStaticUnmapFbAperture__)(OBJGPU *, struct KernelBus *, MEMORY_DESCRIPTOR *, NvU32); NV_STATUS (*__kbusCreateP2PMappingForBar1P2P__)(OBJGPU *, struct KernelBus *, OBJGPU *, struct KernelBus *, NvU32); NV_STATUS (*__kbusRemoveP2PMappingForBar1P2P__)(OBJGPU *, struct KernelBus *, OBJGPU *, struct KernelBus *, NvU32); NvBool (*__kbusHasPcieBar1P2PMapping__)(OBJGPU *, struct KernelBus *, OBJGPU *, struct KernelBus *); + NvBool (*__kbusIsPcieBar1P2PMappingSupported__)(OBJGPU *, struct KernelBus *, OBJGPU *, struct KernelBus *); + void (*__kbusSetupBar1P2PCapability__)(OBJGPU *, struct KernelBus *); NV_STATUS (*__kbusCheckFlaSupportedAndInit__)(OBJGPU *, struct KernelBus *, NvU64, NvU64); NV_STATUS (*__kbusDetermineFlaRangeAndAllocate__)(OBJGPU *, struct KernelBus *, NvU64, NvU64); NV_STATUS (*__kbusAllocateFlaVaspace__)(OBJGPU *, struct KernelBus *, NvU64, NvU64); @@ -346,19 +375,17 @@ NV_STATUS (*__kbusSetBAR0WindowVidOffset__)(OBJGPU *, struct KernelBus *, NvU64); NvU64 (*__kbusGetBAR0WindowVidOffset__)(OBJGPU *, struct KernelBus *); NV_STATUS (*__kbusVerifyBar2__)(OBJGPU *, struct KernelBus *, PMEMORY_DESCRIPTOR, NvU8 *, NvU64, NvU64); + NV_STATUS (*__kbusVerifyCoherentLink__)(OBJGPU *, struct KernelBus *); NV_STATUS (*__kbusFlushPcieForBar0Doorbell__)(OBJGPU *, struct KernelBus *); + NV_STATUS (*__kbusCreateCoherentCpuMapping__)(OBJGPU *, struct KernelBus *, NvU64, NvBool); NvU8 *(*__kbusMapCoherentCpuMapping__)(OBJGPU *, struct KernelBus *, PMEMORY_DESCRIPTOR); void (*__kbusUnmapCoherentCpuMapping__)(OBJGPU *, struct KernelBus *, PMEMORY_DESCRIPTOR); void (*__kbusTeardownCoherentCpuMapping__)(OBJGPU *, struct KernelBus *, NvBool); - NV_STATUS (*__kbusReconcileTunableState__)(POBJGPU, struct KernelBus *, void *); + NvU32 (*__kbusGetEccCounts__)(OBJGPU *, struct KernelBus *); + NV_STATUS (*__kbusStatePostUnload__)(POBJGPU, struct KernelBus *, NvU32); NV_STATUS (*__kbusStateInitUnlocked__)(POBJGPU, struct KernelBus *); void (*__kbusInitMissing__)(POBJGPU, struct KernelBus *); NV_STATUS (*__kbusStatePreInitUnlocked__)(POBJGPU, struct KernelBus *); - NV_STATUS (*__kbusGetTunableState__)(POBJGPU, struct KernelBus *, void *); - NV_STATUS (*__kbusCompareTunableState__)(POBJGPU, struct KernelBus *, void *, void *); - void (*__kbusFreeTunableState__)(POBJGPU, struct KernelBus *, void *); - NV_STATUS (*__kbusAllocTunableState__)(POBJGPU, struct KernelBus *, void **); - NV_STATUS (*__kbusSetTunableState__)(POBJGPU, struct KernelBus *, void *); NvBool (*__kbusIsPresent__)(POBJGPU, struct KernelBus *); NvU32 totalPciBars; RmPhysAddr pciBars[8]; @@ -399,10 +426,12 @@ NvBool bIsBar2SetupInPhysicalMode; NvBool bPreserveBar1ConsoleEnabled; NvBool bBar1ConsolePreserved; + NvBool bBarAccessBlocked; NvBool bBug2751296LimitBar2PtSize; NvBool bAllowReflectedMappingAccess; NvBool bBar2Tunnelled; NvBool bBar2InternalOnly; + NvBool bIsEntireBar2RegionVirtuallyAddressible; NvBool bSkipBar2TestOnGc6Exit; NvBool bFbFlushDisabled; PMEMORY_DESCRIPTOR pFlushMemDesc; @@ -463,8 +492,6 @@ #define kbusStatePreUnload_HAL(pGpu, pKernelBus, arg0) kbusStatePreUnload_DISPATCH(pGpu, pKernelBus, arg0) #define kbusStateUnload(pGpu, pKernelBus, flags) kbusStateUnload_DISPATCH(pGpu, pKernelBus, flags) #define kbusStateUnload_HAL(pGpu, pKernelBus, flags) kbusStateUnload_DISPATCH(pGpu, pKernelBus, flags) -#define kbusStatePostUnload(pGpu, pKernelBus, arg0) kbusStatePostUnload_DISPATCH(pGpu, pKernelBus, arg0) -#define kbusStatePostUnload_HAL(pGpu, pKernelBus, arg0) kbusStatePostUnload_DISPATCH(pGpu, pKernelBus, arg0) #define kbusStateDestroy(pGpu, pKernelBus) kbusStateDestroy_DISPATCH(pGpu, pKernelBus) #define kbusStateDestroy_HAL(pGpu, pKernelBus) kbusStateDestroy_DISPATCH(pGpu, pKernelBus) #define kbusTeardownBar2CpuAperture(pGpu, pKernelBus, gfid) kbusTeardownBar2CpuAperture_DISPATCH(pGpu, pKernelBus, gfid) @@ -477,6 +504,8 @@ #define kbusCreateP2PMapping_HAL(pGpu0, pKernelBus0, pGpu1, pKernelBus1, peer0, peer1, attributes) kbusCreateP2PMapping_DISPATCH(pGpu0, pKernelBus0, pGpu1, pKernelBus1, peer0, peer1, attributes) #define kbusRemoveP2PMapping(pGpu0, pKernelBus0, pGpu1, pKernelBus1, peer0, peer1, attributes) kbusRemoveP2PMapping_DISPATCH(pGpu0, pKernelBus0, pGpu1, pKernelBus1, peer0, peer1, attributes) #define kbusRemoveP2PMapping_HAL(pGpu0, pKernelBus0, pGpu1, pKernelBus1, peer0, peer1, attributes) kbusRemoveP2PMapping_DISPATCH(pGpu0, pKernelBus0, pGpu1, pKernelBus1, peer0, peer1, attributes) +#define kbusGetEgmPeerId(pLocalGpu, pLocalKernelBus, pRemoteGpu) kbusGetEgmPeerId_DISPATCH(pLocalGpu, pLocalKernelBus, pRemoteGpu) +#define kbusGetEgmPeerId_HAL(pLocalGpu, pLocalKernelBus, pRemoteGpu) kbusGetEgmPeerId_DISPATCH(pLocalGpu, pLocalKernelBus, pRemoteGpu) #define kbusGetPeerId(pGpu, pKernelBus, pPeerGpu) kbusGetPeerId_DISPATCH(pGpu, pKernelBus, pPeerGpu) #define kbusGetPeerId_HAL(pGpu, pKernelBus, pPeerGpu) kbusGetPeerId_DISPATCH(pGpu, pKernelBus, pPeerGpu) #define kbusGetNvSwitchPeerId(pGpu, pKernelBus) kbusGetNvSwitchPeerId_DISPATCH(pGpu, pKernelBus) @@ -485,8 +514,8 @@ #define kbusGetUnusedPciePeerId_HAL(pGpu, pKernelBus) kbusGetUnusedPciePeerId_DISPATCH(pGpu, pKernelBus) #define kbusIsPeerIdValid(pGpu, pKernelBus, peerId) kbusIsPeerIdValid_DISPATCH(pGpu, pKernelBus, peerId) #define kbusIsPeerIdValid_HAL(pGpu, pKernelBus, peerId) kbusIsPeerIdValid_DISPATCH(pGpu, pKernelBus, peerId) -#define kbusGetNvlinkP2PPeerId(pGpu0, pKernelBus0, pGpu1, pKernelBus1, nvlinkPeer) kbusGetNvlinkP2PPeerId_DISPATCH(pGpu0, pKernelBus0, pGpu1, pKernelBus1, nvlinkPeer) -#define kbusGetNvlinkP2PPeerId_HAL(pGpu0, pKernelBus0, pGpu1, pKernelBus1, nvlinkPeer) kbusGetNvlinkP2PPeerId_DISPATCH(pGpu0, pKernelBus0, pGpu1, pKernelBus1, nvlinkPeer) +#define kbusGetNvlinkP2PPeerId(pGpu0, pKernelBus0, pGpu1, pKernelBus1, nvlinkPeer, attributes) kbusGetNvlinkP2PPeerId_DISPATCH(pGpu0, pKernelBus0, pGpu1, pKernelBus1, nvlinkPeer, attributes) +#define kbusGetNvlinkP2PPeerId_HAL(pGpu0, pKernelBus0, pGpu1, pKernelBus1, nvlinkPeer, attributes) kbusGetNvlinkP2PPeerId_DISPATCH(pGpu0, pKernelBus0, pGpu1, pKernelBus1, nvlinkPeer, attributes) #define kbusWriteP2PWmbTag(pGpu, pKernelBus, remote2Local, p2pWmbTag) kbusWriteP2PWmbTag_DISPATCH(pGpu, pKernelBus, remote2Local, p2pWmbTag) #define kbusWriteP2PWmbTag_HAL(pGpu, pKernelBus, remote2Local, p2pWmbTag) kbusWriteP2PWmbTag_DISPATCH(pGpu, pKernelBus, remote2Local, p2pWmbTag) #define kbusSetupP2PDomainAccess(pGpu0, pKernelBus0, pGpu1, ppP2PDomMemDesc) kbusSetupP2PDomainAccess_DISPATCH(pGpu0, pKernelBus0, pGpu1, ppP2PDomMemDesc) @@ -499,12 +528,28 @@ #define kbusRemoveP2PMappingForC2C_HAL(pGpu0, pKernelBus0, pGpu1, pKernelBus1, peer0, peer1, attributes) kbusRemoveP2PMappingForC2C_DISPATCH(pGpu0, pKernelBus0, pGpu1, pKernelBus1, peer0, peer1, attributes) #define kbusUnreserveP2PPeerIds(pGpu, pKernelBus, peerMask) kbusUnreserveP2PPeerIds_DISPATCH(pGpu, pKernelBus, peerMask) #define kbusUnreserveP2PPeerIds_HAL(pGpu, pKernelBus, peerMask) kbusUnreserveP2PPeerIds_DISPATCH(pGpu, pKernelBus, peerMask) +#define kbusNeedStaticBar1Mapping(pGpu, pKernelBus) kbusNeedStaticBar1Mapping_DISPATCH(pGpu, pKernelBus) +#define kbusNeedStaticBar1Mapping_HAL(pGpu, pKernelBus) kbusNeedStaticBar1Mapping_DISPATCH(pGpu, pKernelBus) +#define kbusEnableStaticBar1Mapping(pGpu, pKernelBus, reservedFbSize, gfid) kbusEnableStaticBar1Mapping_DISPATCH(pGpu, pKernelBus, reservedFbSize, gfid) +#define kbusEnableStaticBar1Mapping_HAL(pGpu, pKernelBus, reservedFbSize, gfid) kbusEnableStaticBar1Mapping_DISPATCH(pGpu, pKernelBus, reservedFbSize, gfid) +#define kbusDisableStaticBar1Mapping(pGpu, pKernelBus, gfid) kbusDisableStaticBar1Mapping_DISPATCH(pGpu, pKernelBus, gfid) +#define kbusDisableStaticBar1Mapping_HAL(pGpu, pKernelBus, gfid) kbusDisableStaticBar1Mapping_DISPATCH(pGpu, pKernelBus, gfid) +#define kbusGetBar1P2PDmaInfo(pSrcGpu, pPeerGpu, pPeerKernelBus, dma_addr, dma_size) kbusGetBar1P2PDmaInfo_DISPATCH(pSrcGpu, pPeerGpu, pPeerKernelBus, dma_addr, dma_size) +#define kbusGetBar1P2PDmaInfo_HAL(pSrcGpu, pPeerGpu, pPeerKernelBus, dma_addr, dma_size) kbusGetBar1P2PDmaInfo_DISPATCH(pSrcGpu, pPeerGpu, pPeerKernelBus, dma_addr, dma_size) +#define kbusStaticMapFbAperture(pGpu, pKernelBus, pMemDesc, offset, pAperOffset, pLength, gfid) kbusStaticMapFbAperture_DISPATCH(pGpu, pKernelBus, pMemDesc, offset, pAperOffset, pLength, gfid) +#define kbusStaticMapFbAperture_HAL(pGpu, pKernelBus, pMemDesc, offset, pAperOffset, pLength, gfid) kbusStaticMapFbAperture_DISPATCH(pGpu, pKernelBus, pMemDesc, offset, pAperOffset, pLength, gfid) +#define kbusStaticUnmapFbAperture(pGpu, pKernelBus, pMemDesc, gfid) kbusStaticUnmapFbAperture_DISPATCH(pGpu, pKernelBus, pMemDesc, gfid) +#define kbusStaticUnmapFbAperture_HAL(pGpu, pKernelBus, pMemDesc, gfid) kbusStaticUnmapFbAperture_DISPATCH(pGpu, pKernelBus, pMemDesc, gfid) #define kbusCreateP2PMappingForBar1P2P(pGpu0, pKernelBus0, pGpu1, pKernelBus1, attributes) kbusCreateP2PMappingForBar1P2P_DISPATCH(pGpu0, pKernelBus0, pGpu1, pKernelBus1, attributes) #define kbusCreateP2PMappingForBar1P2P_HAL(pGpu0, pKernelBus0, pGpu1, pKernelBus1, attributes) kbusCreateP2PMappingForBar1P2P_DISPATCH(pGpu0, pKernelBus0, pGpu1, pKernelBus1, attributes) #define kbusRemoveP2PMappingForBar1P2P(pGpu0, pKernelBus0, pGpu1, pKernelBus1, attributes) kbusRemoveP2PMappingForBar1P2P_DISPATCH(pGpu0, pKernelBus0, pGpu1, pKernelBus1, attributes) #define kbusRemoveP2PMappingForBar1P2P_HAL(pGpu0, pKernelBus0, pGpu1, pKernelBus1, attributes) kbusRemoveP2PMappingForBar1P2P_DISPATCH(pGpu0, pKernelBus0, pGpu1, pKernelBus1, attributes) #define kbusHasPcieBar1P2PMapping(pGpu0, pKernelBus0, pGpu1, pKernelBus1) kbusHasPcieBar1P2PMapping_DISPATCH(pGpu0, pKernelBus0, pGpu1, pKernelBus1) #define kbusHasPcieBar1P2PMapping_HAL(pGpu0, pKernelBus0, pGpu1, pKernelBus1) kbusHasPcieBar1P2PMapping_DISPATCH(pGpu0, pKernelBus0, pGpu1, pKernelBus1) +#define kbusIsPcieBar1P2PMappingSupported(pGpu0, pKernelBus0, pGpu1, pKernelBus1) kbusIsPcieBar1P2PMappingSupported_DISPATCH(pGpu0, pKernelBus0, pGpu1, pKernelBus1) +#define kbusIsPcieBar1P2PMappingSupported_HAL(pGpu0, pKernelBus0, pGpu1, pKernelBus1) kbusIsPcieBar1P2PMappingSupported_DISPATCH(pGpu0, pKernelBus0, pGpu1, pKernelBus1) +#define kbusSetupBar1P2PCapability(pGpu, pKernelBus) kbusSetupBar1P2PCapability_DISPATCH(pGpu, pKernelBus) +#define kbusSetupBar1P2PCapability_HAL(pGpu, pKernelBus) kbusSetupBar1P2PCapability_DISPATCH(pGpu, pKernelBus) #define kbusCheckFlaSupportedAndInit(pGpu, pKernelBus, base, size) kbusCheckFlaSupportedAndInit_DISPATCH(pGpu, pKernelBus, base, size) #define kbusCheckFlaSupportedAndInit_HAL(pGpu, pKernelBus, base, size) kbusCheckFlaSupportedAndInit_DISPATCH(pGpu, pKernelBus, base, size) #define kbusDetermineFlaRangeAndAllocate(pGpu, pKernelBus, base, size) kbusDetermineFlaRangeAndAllocate_DISPATCH(pGpu, pKernelBus, base, size) @@ -551,23 +596,24 @@ #define kbusGetBAR0WindowVidOffset_HAL(pGpu, pKernelBus) kbusGetBAR0WindowVidOffset_DISPATCH(pGpu, pKernelBus) #define kbusVerifyBar2(pGpu, pKernelBus, memDescIn, pCpuPtrIn, offset, size) kbusVerifyBar2_DISPATCH(pGpu, pKernelBus, memDescIn, pCpuPtrIn, offset, size) #define kbusVerifyBar2_HAL(pGpu, pKernelBus, memDescIn, pCpuPtrIn, offset, size) kbusVerifyBar2_DISPATCH(pGpu, pKernelBus, memDescIn, pCpuPtrIn, offset, size) +#define kbusVerifyCoherentLink(pGpu, pKernelBus) kbusVerifyCoherentLink_DISPATCH(pGpu, pKernelBus) +#define kbusVerifyCoherentLink_HAL(pGpu, pKernelBus) kbusVerifyCoherentLink_DISPATCH(pGpu, pKernelBus) #define kbusFlushPcieForBar0Doorbell(pGpu, pKernelBus) kbusFlushPcieForBar0Doorbell_DISPATCH(pGpu, pKernelBus) #define kbusFlushPcieForBar0Doorbell_HAL(pGpu, pKernelBus) kbusFlushPcieForBar0Doorbell_DISPATCH(pGpu, pKernelBus) +#define kbusCreateCoherentCpuMapping(pGpu, pKernelBus, numaOnlineMemorySize, bFlush) kbusCreateCoherentCpuMapping_DISPATCH(pGpu, pKernelBus, numaOnlineMemorySize, bFlush) +#define kbusCreateCoherentCpuMapping_HAL(pGpu, pKernelBus, numaOnlineMemorySize, bFlush) kbusCreateCoherentCpuMapping_DISPATCH(pGpu, pKernelBus, numaOnlineMemorySize, bFlush) #define kbusMapCoherentCpuMapping(pGpu, pKernelBus, arg0) kbusMapCoherentCpuMapping_DISPATCH(pGpu, pKernelBus, arg0) #define kbusMapCoherentCpuMapping_HAL(pGpu, pKernelBus, arg0) kbusMapCoherentCpuMapping_DISPATCH(pGpu, pKernelBus, arg0) #define kbusUnmapCoherentCpuMapping(pGpu, pKernelBus, arg0) kbusUnmapCoherentCpuMapping_DISPATCH(pGpu, pKernelBus, arg0) #define kbusUnmapCoherentCpuMapping_HAL(pGpu, pKernelBus, arg0) kbusUnmapCoherentCpuMapping_DISPATCH(pGpu, pKernelBus, arg0) #define kbusTeardownCoherentCpuMapping(pGpu, pKernelBus, arg0) kbusTeardownCoherentCpuMapping_DISPATCH(pGpu, pKernelBus, arg0) #define kbusTeardownCoherentCpuMapping_HAL(pGpu, pKernelBus, arg0) kbusTeardownCoherentCpuMapping_DISPATCH(pGpu, pKernelBus, arg0) -#define kbusReconcileTunableState(pGpu, pEngstate, pTunableState) kbusReconcileTunableState_DISPATCH(pGpu, pEngstate, pTunableState) +#define kbusGetEccCounts(pGpu, pKernelBus) kbusGetEccCounts_DISPATCH(pGpu, pKernelBus) +#define kbusGetEccCounts_HAL(pGpu, pKernelBus) kbusGetEccCounts_DISPATCH(pGpu, pKernelBus) +#define kbusStatePostUnload(pGpu, pEngstate, arg0) kbusStatePostUnload_DISPATCH(pGpu, pEngstate, arg0) #define kbusStateInitUnlocked(pGpu, pEngstate) kbusStateInitUnlocked_DISPATCH(pGpu, pEngstate) #define kbusInitMissing(pGpu, pEngstate) kbusInitMissing_DISPATCH(pGpu, pEngstate) #define kbusStatePreInitUnlocked(pGpu, pEngstate) kbusStatePreInitUnlocked_DISPATCH(pGpu, pEngstate) -#define kbusGetTunableState(pGpu, pEngstate, pTunableState) kbusGetTunableState_DISPATCH(pGpu, pEngstate, pTunableState) -#define kbusCompareTunableState(pGpu, pEngstate, pTunables1, pTunables2) kbusCompareTunableState_DISPATCH(pGpu, pEngstate, pTunables1, pTunables2) -#define kbusFreeTunableState(pGpu, pEngstate, pTunableState) kbusFreeTunableState_DISPATCH(pGpu, pEngstate, pTunableState) -#define kbusAllocTunableState(pGpu, pEngstate, ppTunableState) kbusAllocTunableState_DISPATCH(pGpu, pEngstate, ppTunableState) -#define kbusSetTunableState(pGpu, pEngstate, pTunableState) kbusSetTunableState_DISPATCH(pGpu, pEngstate, pTunableState) #define kbusIsPresent(pGpu, pEngstate) kbusIsPresent_DISPATCH(pGpu, pEngstate) NV_STATUS kbusInitBarsSize_KERNEL(OBJGPU *pGpu, struct KernelBus *pKernelBus); @@ -1248,37 +1294,6 @@ #define kbusUnlinkP2P_HAL(pGpu, pKernelBu) kbusUnlinkP2P(pGpu, pKernelBu) -static inline NvBool kbusIsPcieBar1P2PMappingSupported_491d52(OBJGPU *pGpu0, struct KernelBus *pKernelBus0, OBJGPU *pGpu1, struct KernelBus *pKernelBus1) { - return ((NvBool)(0 != 0)); -} - - -#ifdef __nvoc_kern_bus_h_disabled -static inline NvBool kbusIsPcieBar1P2PMappingSupported(OBJGPU *pGpu0, struct KernelBus *pKernelBus0, OBJGPU *pGpu1, struct KernelBus *pKernelBus1) { - NV_ASSERT_FAILED_PRECOMP("KernelBus was disabled!"); - return NV_FALSE; -} -#else //__nvoc_kern_bus_h_disabled -#define kbusIsPcieBar1P2PMappingSupported(pGpu0, pKernelBus0, pGpu1, pKernelBus1) kbusIsPcieBar1P2PMappingSupported_491d52(pGpu0, pKernelBus0, pGpu1, pKernelBus1) -#endif //__nvoc_kern_bus_h_disabled - -#define kbusIsPcieBar1P2PMappingSupported_HAL(pGpu0, pKernelBus0, pGpu1, pKernelBus1) kbusIsPcieBar1P2PMappingSupported(pGpu0, pKernelBus0, pGpu1, pKernelBus1) - -static inline void kbusSetupBar1P2PCapability_b3696a(OBJGPU *pGpu, struct KernelBus *pKernelBus) { - return; -} - - -#ifdef __nvoc_kern_bus_h_disabled -static inline void kbusSetupBar1P2PCapability(OBJGPU *pGpu, struct KernelBus *pKernelBus) { - NV_ASSERT_FAILED_PRECOMP("KernelBus was disabled!"); -} -#else //__nvoc_kern_bus_h_disabled -#define kbusSetupBar1P2PCapability(pGpu, pKernelBus) kbusSetupBar1P2PCapability_b3696a(pGpu, pKernelBus) -#endif //__nvoc_kern_bus_h_disabled - -#define kbusSetupBar1P2PCapability_HAL(pGpu, pKernelBus) kbusSetupBar1P2PCapability(pGpu, pKernelBus) - NV_STATUS kbusFlushSingle_GM107(OBJGPU *pGpu, struct KernelBus *pKernelBus, NvU32 flags); @@ -1459,19 +1474,19 @@ #define kbusDestroyBar1_HAL(pGpu, pKernelBus, gfid) kbusDestroyBar1(pGpu, pKernelBus, gfid) -NV_STATUS kbusMapFbAperture_GM107(OBJGPU *pGpu, struct KernelBus *pKernelBus, PMEMORY_DESCRIPTOR arg0, NvU64 offset, NvU64 *pAperOffset, NvU64 *pLength, NvU32 flags, NvHandle hClient); +NV_STATUS kbusMapFbAperture_GM107(OBJGPU *pGpu, struct KernelBus *pKernelBus, PMEMORY_DESCRIPTOR arg0, NvU64 offset, NvU64 *pAperOffset, NvU64 *pLength, NvU32 flags, struct Device *pDevice); #ifdef __nvoc_kern_bus_h_disabled -static inline NV_STATUS kbusMapFbAperture(OBJGPU *pGpu, struct KernelBus *pKernelBus, PMEMORY_DESCRIPTOR arg0, NvU64 offset, NvU64 *pAperOffset, NvU64 *pLength, NvU32 flags, NvHandle hClient) { +static inline NV_STATUS kbusMapFbAperture(OBJGPU *pGpu, struct KernelBus *pKernelBus, PMEMORY_DESCRIPTOR arg0, NvU64 offset, NvU64 *pAperOffset, NvU64 *pLength, NvU32 flags, struct Device *pDevice) { NV_ASSERT_FAILED_PRECOMP("KernelBus was disabled!"); return NV_ERR_NOT_SUPPORTED; } #else //__nvoc_kern_bus_h_disabled -#define kbusMapFbAperture(pGpu, pKernelBus, arg0, offset, pAperOffset, pLength, flags, hClient) kbusMapFbAperture_GM107(pGpu, pKernelBus, arg0, offset, pAperOffset, pLength, flags, hClient) +#define kbusMapFbAperture(pGpu, pKernelBus, arg0, offset, pAperOffset, pLength, flags, pDevice) kbusMapFbAperture_GM107(pGpu, pKernelBus, arg0, offset, pAperOffset, pLength, flags, pDevice) #endif //__nvoc_kern_bus_h_disabled -#define kbusMapFbAperture_HAL(pGpu, pKernelBus, arg0, offset, pAperOffset, pLength, flags, hClient) kbusMapFbAperture(pGpu, pKernelBus, arg0, offset, pAperOffset, pLength, flags, hClient) +#define kbusMapFbAperture_HAL(pGpu, pKernelBus, arg0, offset, pAperOffset, pLength, flags, pDevice) kbusMapFbAperture(pGpu, pKernelBus, arg0, offset, pAperOffset, pLength, flags, pDevice) NV_STATUS kbusUnmapFbAperture_GM107(OBJGPU *pGpu, struct KernelBus *pKernelBus, PMEMORY_DESCRIPTOR arg0, NvU64 aperOffset, NvU64 length, NvU32 flags); @@ -1514,13 +1529,13 @@ #define kbusGetBar1VASpace_HAL(pGpu, pKernelBus) kbusGetBar1VASpace(pGpu, pKernelBus) -static inline NV_STATUS kbusInitInstBlk_56cd7a(OBJGPU *pGpu, struct KernelBus *pKernelBus, PMEMORY_DESCRIPTOR pInstBlkMemDesc, PMEMORY_DESCRIPTOR pPDB, NvU64 vaLimit, NvU32 bigPageSize, struct OBJVASPACE *pVAS) { +static inline NV_STATUS kbusInitInstBlk_56cd7a(OBJGPU *pGpu, struct KernelBus *pKernelBus, PMEMORY_DESCRIPTOR pInstBlkMemDesc, PMEMORY_DESCRIPTOR pPDB, NvU64 vaLimit, NvU64 bigPageSize, struct OBJVASPACE *pVAS) { return NV_OK; } #ifdef __nvoc_kern_bus_h_disabled -static inline NV_STATUS kbusInitInstBlk(OBJGPU *pGpu, struct KernelBus *pKernelBus, PMEMORY_DESCRIPTOR pInstBlkMemDesc, PMEMORY_DESCRIPTOR pPDB, NvU64 vaLimit, NvU32 bigPageSize, struct OBJVASPACE *pVAS) { +static inline NV_STATUS kbusInitInstBlk(OBJGPU *pGpu, struct KernelBus *pKernelBus, PMEMORY_DESCRIPTOR pInstBlkMemDesc, PMEMORY_DESCRIPTOR pPDB, NvU64 vaLimit, NvU64 bigPageSize, struct OBJVASPACE *pVAS) { NV_ASSERT_FAILED_PRECOMP("KernelBus was disabled!"); return NV_ERR_NOT_SUPPORTED; } @@ -1576,22 +1591,6 @@ #define kbusFlush_HAL(pGpu, pKernelBus, flags) kbusFlush(pGpu, pKernelBus, flags) -static inline NV_STATUS kbusCreateCoherentCpuMapping_46f6a7(OBJGPU *pGpu, struct KernelBus *pKernelBus, NvBool bFlush) { - return NV_ERR_NOT_SUPPORTED; -} - - -#ifdef __nvoc_kern_bus_h_disabled -static inline NV_STATUS kbusCreateCoherentCpuMapping(OBJGPU *pGpu, struct KernelBus *pKernelBus, NvBool bFlush) { - NV_ASSERT_FAILED_PRECOMP("KernelBus was disabled!"); - return NV_ERR_NOT_SUPPORTED; -} -#else //__nvoc_kern_bus_h_disabled -#define kbusCreateCoherentCpuMapping(pGpu, pKernelBus, bFlush) kbusCreateCoherentCpuMapping_46f6a7(pGpu, pKernelBus, bFlush) -#endif //__nvoc_kern_bus_h_disabled - -#define kbusCreateCoherentCpuMapping_HAL(pGpu, pKernelBus, bFlush) kbusCreateCoherentCpuMapping(pGpu, pKernelBus, bFlush) - static inline void kbusTeardownCoherentCpuMappingAcr_b3696a(OBJGPU *pGpu, struct KernelBus *pKernelBus) { return; } @@ -1657,14 +1656,6 @@ return pKernelBus->__kbusStateUnload__(pGpu, pKernelBus, flags); } -static inline NV_STATUS kbusStatePostUnload_56cd7a(OBJGPU *pGpu, struct KernelBus *pKernelBus, NvU32 arg0) { - return NV_OK; -} - -static inline NV_STATUS kbusStatePostUnload_DISPATCH(OBJGPU *pGpu, struct KernelBus *pKernelBus, NvU32 arg0) { - return pKernelBus->__kbusStatePostUnload__(pGpu, pKernelBus, arg0); -} - void kbusStateDestroy_GM107(OBJGPU *pGpu, struct KernelBus *pKernelBus); static inline void kbusStateDestroy_DISPATCH(OBJGPU *pGpu, struct KernelBus *pKernelBus) { @@ -1711,6 +1702,16 @@ return pKernelBus0->__kbusRemoveP2PMapping__(pGpu0, pKernelBus0, pGpu1, pKernelBus1, peer0, peer1, attributes); } +NvU32 kbusGetEgmPeerId_GH100(OBJGPU *pLocalGpu, struct KernelBus *pLocalKernelBus, OBJGPU *pRemoteGpu); + +static inline NvU32 kbusGetEgmPeerId_56cd7a(OBJGPU *pLocalGpu, struct KernelBus *pLocalKernelBus, OBJGPU *pRemoteGpu) { + return NV_OK; +} + +static inline NvU32 kbusGetEgmPeerId_DISPATCH(OBJGPU *pLocalGpu, struct KernelBus *pLocalKernelBus, OBJGPU *pRemoteGpu) { + return pLocalKernelBus->__kbusGetEgmPeerId__(pLocalGpu, pLocalKernelBus, pRemoteGpu); +} + NvU32 kbusGetPeerId_GP100(OBJGPU *pGpu, struct KernelBus *pKernelBus, OBJGPU *pPeerGpu); NvU32 kbusGetPeerId_GH100(OBJGPU *pGpu, struct KernelBus *pKernelBus, OBJGPU *pPeerGpu); @@ -1745,16 +1746,16 @@ return pKernelBus->__kbusIsPeerIdValid__(pGpu, pKernelBus, peerId); } -NV_STATUS kbusGetNvlinkP2PPeerId_GP100(OBJGPU *pGpu0, struct KernelBus *pKernelBus0, OBJGPU *pGpu1, struct KernelBus *pKernelBus1, NvU32 *nvlinkPeer); +NV_STATUS kbusGetNvlinkP2PPeerId_GP100(OBJGPU *pGpu0, struct KernelBus *pKernelBus0, OBJGPU *pGpu1, struct KernelBus *pKernelBus1, NvU32 *nvlinkPeer, NvU32 attributes); -NV_STATUS kbusGetNvlinkP2PPeerId_GA100(OBJGPU *pGpu0, struct KernelBus *pKernelBus0, OBJGPU *pGpu1, struct KernelBus *pKernelBus1, NvU32 *nvlinkPeer); +NV_STATUS kbusGetNvlinkP2PPeerId_GA100(OBJGPU *pGpu0, struct KernelBus *pKernelBus0, OBJGPU *pGpu1, struct KernelBus *pKernelBus1, NvU32 *nvlinkPeer, NvU32 attributes); -static inline NV_STATUS kbusGetNvlinkP2PPeerId_56cd7a(OBJGPU *pGpu0, struct KernelBus *pKernelBus0, OBJGPU *pGpu1, struct KernelBus *pKernelBus1, NvU32 *nvlinkPeer) { +static inline NV_STATUS kbusGetNvlinkP2PPeerId_56cd7a(OBJGPU *pGpu0, struct KernelBus *pKernelBus0, OBJGPU *pGpu1, struct KernelBus *pKernelBus1, NvU32 *nvlinkPeer, NvU32 attributes) { return NV_OK; } -static inline NV_STATUS kbusGetNvlinkP2PPeerId_DISPATCH(OBJGPU *pGpu0, struct KernelBus *pKernelBus0, OBJGPU *pGpu1, struct KernelBus *pKernelBus1, NvU32 *nvlinkPeer) { - return pKernelBus0->__kbusGetNvlinkP2PPeerId__(pGpu0, pKernelBus0, pGpu1, pKernelBus1, nvlinkPeer); +static inline NV_STATUS kbusGetNvlinkP2PPeerId_DISPATCH(OBJGPU *pGpu0, struct KernelBus *pKernelBus0, OBJGPU *pGpu1, struct KernelBus *pKernelBus1, NvU32 *nvlinkPeer, NvU32 attributes) { + return pKernelBus0->__kbusGetNvlinkP2PPeerId__(pGpu0, pKernelBus0, pGpu1, pKernelBus1, nvlinkPeer, attributes); } void kbusWriteP2PWmbTag_GM200(OBJGPU *pGpu, struct KernelBus *pKernelBus, NvU32 remote2Local, NvU64 p2pWmbTag); @@ -1813,6 +1814,66 @@ return pKernelBus->__kbusUnreserveP2PPeerIds__(pGpu, pKernelBus, peerMask); } +NvBool kbusNeedStaticBar1Mapping_GH100(OBJGPU *pGpu, struct KernelBus *pKernelBus); + +static inline NvBool kbusNeedStaticBar1Mapping_bf6dfa(OBJGPU *pGpu, struct KernelBus *pKernelBus) { + return ((NvBool)(0 != 0)); +} + +static inline NvBool kbusNeedStaticBar1Mapping_DISPATCH(OBJGPU *pGpu, struct KernelBus *pKernelBus) { + return pKernelBus->__kbusNeedStaticBar1Mapping__(pGpu, pKernelBus); +} + +NV_STATUS kbusEnableStaticBar1Mapping_GH100(OBJGPU *pGpu, struct KernelBus *pKernelBus, NvU64 reservedFbSize, NvU32 gfid); + +static inline NV_STATUS kbusEnableStaticBar1Mapping_46f6a7(OBJGPU *pGpu, struct KernelBus *pKernelBus, NvU64 reservedFbSize, NvU32 gfid) { + return NV_ERR_NOT_SUPPORTED; +} + +static inline NV_STATUS kbusEnableStaticBar1Mapping_DISPATCH(OBJGPU *pGpu, struct KernelBus *pKernelBus, NvU64 reservedFbSize, NvU32 gfid) { + return pKernelBus->__kbusEnableStaticBar1Mapping__(pGpu, pKernelBus, reservedFbSize, gfid); +} + +NV_STATUS kbusDisableStaticBar1Mapping_GH100(OBJGPU *pGpu, struct KernelBus *pKernelBus, NvU32 gfid); + +static inline NV_STATUS kbusDisableStaticBar1Mapping_56cd7a(OBJGPU *pGpu, struct KernelBus *pKernelBus, NvU32 gfid) { + return NV_OK; +} + +static inline NV_STATUS kbusDisableStaticBar1Mapping_DISPATCH(OBJGPU *pGpu, struct KernelBus *pKernelBus, NvU32 gfid) { + return pKernelBus->__kbusDisableStaticBar1Mapping__(pGpu, pKernelBus, gfid); +} + +NV_STATUS kbusGetBar1P2PDmaInfo_GH100(OBJGPU *pSrcGpu, OBJGPU *pPeerGpu, struct KernelBus *pPeerKernelBus, NvU64 *dma_addr, NvU64 *dma_size); + +static inline NV_STATUS kbusGetBar1P2PDmaInfo_395e98(OBJGPU *pSrcGpu, OBJGPU *pPeerGpu, struct KernelBus *pPeerKernelBus, NvU64 *dma_addr, NvU64 *dma_size) { + return NV_ERR_NOT_SUPPORTED; +} + +static inline NV_STATUS kbusGetBar1P2PDmaInfo_DISPATCH(OBJGPU *pSrcGpu, OBJGPU *pPeerGpu, struct KernelBus *pPeerKernelBus, NvU64 *dma_addr, NvU64 *dma_size) { + return pPeerKernelBus->__kbusGetBar1P2PDmaInfo__(pSrcGpu, pPeerGpu, pPeerKernelBus, dma_addr, dma_size); +} + +NV_STATUS kbusStaticMapFbAperture_GH100(OBJGPU *pGpu, struct KernelBus *pKernelBus, MEMORY_DESCRIPTOR *pMemDesc, NvU64 offset, NvU64 *pAperOffset, NvU64 *pLength, NvU32 gfid); + +static inline NV_STATUS kbusStaticMapFbAperture_395e98(OBJGPU *pGpu, struct KernelBus *pKernelBus, MEMORY_DESCRIPTOR *pMemDesc, NvU64 offset, NvU64 *pAperOffset, NvU64 *pLength, NvU32 gfid) { + return NV_ERR_NOT_SUPPORTED; +} + +static inline NV_STATUS kbusStaticMapFbAperture_DISPATCH(OBJGPU *pGpu, struct KernelBus *pKernelBus, MEMORY_DESCRIPTOR *pMemDesc, NvU64 offset, NvU64 *pAperOffset, NvU64 *pLength, NvU32 gfid) { + return pKernelBus->__kbusStaticMapFbAperture__(pGpu, pKernelBus, pMemDesc, offset, pAperOffset, pLength, gfid); +} + +NV_STATUS kbusStaticUnmapFbAperture_GH100(OBJGPU *pGpu, struct KernelBus *pKernelBus, MEMORY_DESCRIPTOR *pMemDesc, NvU32 gfid); + +static inline NV_STATUS kbusStaticUnmapFbAperture_395e98(OBJGPU *pGpu, struct KernelBus *pKernelBus, MEMORY_DESCRIPTOR *pMemDesc, NvU32 gfid) { + return NV_ERR_NOT_SUPPORTED; +} + +static inline NV_STATUS kbusStaticUnmapFbAperture_DISPATCH(OBJGPU *pGpu, struct KernelBus *pKernelBus, MEMORY_DESCRIPTOR *pMemDesc, NvU32 gfid) { + return pKernelBus->__kbusStaticUnmapFbAperture__(pGpu, pKernelBus, pMemDesc, gfid); +} + NV_STATUS kbusCreateP2PMappingForBar1P2P_GH100(OBJGPU *pGpu0, struct KernelBus *pKernelBus0, OBJGPU *pGpu1, struct KernelBus *pKernelBus1, NvU32 attributes); static inline NV_STATUS kbusCreateP2PMappingForBar1P2P_46f6a7(OBJGPU *pGpu0, struct KernelBus *pKernelBus0, OBJGPU *pGpu1, struct KernelBus *pKernelBus1, NvU32 attributes) { @@ -1843,6 +1904,26 @@ return pKernelBus0->__kbusHasPcieBar1P2PMapping__(pGpu0, pKernelBus0, pGpu1, pKernelBus1); } +NvBool kbusIsPcieBar1P2PMappingSupported_GH100(OBJGPU *pGpu0, struct KernelBus *pKernelBus0, OBJGPU *pGpu1, struct KernelBus *pKernelBus1); + +static inline NvBool kbusIsPcieBar1P2PMappingSupported_491d52(OBJGPU *pGpu0, struct KernelBus *pKernelBus0, OBJGPU *pGpu1, struct KernelBus *pKernelBus1) { + return ((NvBool)(0 != 0)); +} + +static inline NvBool kbusIsPcieBar1P2PMappingSupported_DISPATCH(OBJGPU *pGpu0, struct KernelBus *pKernelBus0, OBJGPU *pGpu1, struct KernelBus *pKernelBus1) { + return pKernelBus0->__kbusIsPcieBar1P2PMappingSupported__(pGpu0, pKernelBus0, pGpu1, pKernelBus1); +} + +void kbusSetupBar1P2PCapability_GH100(OBJGPU *pGpu, struct KernelBus *pKernelBus); + +static inline void kbusSetupBar1P2PCapability_b3696a(OBJGPU *pGpu, struct KernelBus *pKernelBus) { + return; +} + +static inline void kbusSetupBar1P2PCapability_DISPATCH(OBJGPU *pGpu, struct KernelBus *pKernelBus) { + pKernelBus->__kbusSetupBar1P2PCapability__(pGpu, pKernelBus); +} + NV_STATUS kbusCheckFlaSupportedAndInit_GA100(OBJGPU *pGpu, struct KernelBus *pKernelBus, NvU64 base, NvU64 size); static inline NV_STATUS kbusCheckFlaSupportedAndInit_ac1694(OBJGPU *pGpu, struct KernelBus *pKernelBus, NvU64 base, NvU64 size) { @@ -2077,6 +2158,16 @@ return pKernelBus->__kbusVerifyBar2__(pGpu, pKernelBus, memDescIn, pCpuPtrIn, offset, size); } +static inline NV_STATUS kbusVerifyCoherentLink_56cd7a(OBJGPU *pGpu, struct KernelBus *pKernelBus) { + return NV_OK; +} + +NV_STATUS kbusVerifyCoherentLink_GH100(OBJGPU *pGpu, struct KernelBus *pKernelBus); + +static inline NV_STATUS kbusVerifyCoherentLink_DISPATCH(OBJGPU *pGpu, struct KernelBus *pKernelBus) { + return pKernelBus->__kbusVerifyCoherentLink__(pGpu, pKernelBus); +} + NV_STATUS kbusFlushPcieForBar0Doorbell_GH100(OBJGPU *pGpu, struct KernelBus *pKernelBus); static inline NV_STATUS kbusFlushPcieForBar0Doorbell_56cd7a(OBJGPU *pGpu, struct KernelBus *pKernelBus) { @@ -2087,6 +2178,16 @@ return pKernelBus->__kbusFlushPcieForBar0Doorbell__(pGpu, pKernelBus); } +NV_STATUS kbusCreateCoherentCpuMapping_GH100(OBJGPU *pGpu, struct KernelBus *pKernelBus, NvU64 numaOnlineMemorySize, NvBool bFlush); + +static inline NV_STATUS kbusCreateCoherentCpuMapping_46f6a7(OBJGPU *pGpu, struct KernelBus *pKernelBus, NvU64 numaOnlineMemorySize, NvBool bFlush) { + return NV_ERR_NOT_SUPPORTED; +} + +static inline NV_STATUS kbusCreateCoherentCpuMapping_DISPATCH(OBJGPU *pGpu, struct KernelBus *pKernelBus, NvU64 numaOnlineMemorySize, NvBool bFlush) { + return pKernelBus->__kbusCreateCoherentCpuMapping__(pGpu, pKernelBus, numaOnlineMemorySize, bFlush); +} + NvU8 *kbusMapCoherentCpuMapping_GV100(OBJGPU *pGpu, struct KernelBus *pKernelBus, PMEMORY_DESCRIPTOR arg0); static inline NvU8 *kbusMapCoherentCpuMapping_9e2234(OBJGPU *pGpu, struct KernelBus *pKernelBus, PMEMORY_DESCRIPTOR arg0) { @@ -2117,8 +2218,18 @@ pKernelBus->__kbusTeardownCoherentCpuMapping__(pGpu, pKernelBus, arg0); } -static inline NV_STATUS kbusReconcileTunableState_DISPATCH(POBJGPU pGpu, struct KernelBus *pEngstate, void *pTunableState) { - return pEngstate->__kbusReconcileTunableState__(pGpu, pEngstate, pTunableState); +NvU32 kbusGetEccCounts_GH100(OBJGPU *pGpu, struct KernelBus *pKernelBus); + +static inline NvU32 kbusGetEccCounts_4a4dee(OBJGPU *pGpu, struct KernelBus *pKernelBus) { + return 0; +} + +static inline NvU32 kbusGetEccCounts_DISPATCH(OBJGPU *pGpu, struct KernelBus *pKernelBus) { + return pKernelBus->__kbusGetEccCounts__(pGpu, pKernelBus); +} + +static inline NV_STATUS kbusStatePostUnload_DISPATCH(POBJGPU pGpu, struct KernelBus *pEngstate, NvU32 arg0) { + return pEngstate->__kbusStatePostUnload__(pGpu, pEngstate, arg0); } static inline NV_STATUS kbusStateInitUnlocked_DISPATCH(POBJGPU pGpu, struct KernelBus *pEngstate) { @@ -2133,26 +2244,6 @@ return pEngstate->__kbusStatePreInitUnlocked__(pGpu, pEngstate); } -static inline NV_STATUS kbusGetTunableState_DISPATCH(POBJGPU pGpu, struct KernelBus *pEngstate, void *pTunableState) { - return pEngstate->__kbusGetTunableState__(pGpu, pEngstate, pTunableState); -} - -static inline NV_STATUS kbusCompareTunableState_DISPATCH(POBJGPU pGpu, struct KernelBus *pEngstate, void *pTunables1, void *pTunables2) { - return pEngstate->__kbusCompareTunableState__(pGpu, pEngstate, pTunables1, pTunables2); -} - -static inline void kbusFreeTunableState_DISPATCH(POBJGPU pGpu, struct KernelBus *pEngstate, void *pTunableState) { - pEngstate->__kbusFreeTunableState__(pGpu, pEngstate, pTunableState); -} - -static inline NV_STATUS kbusAllocTunableState_DISPATCH(POBJGPU pGpu, struct KernelBus *pEngstate, void **ppTunableState) { - return pEngstate->__kbusAllocTunableState__(pGpu, pEngstate, ppTunableState); -} - -static inline NV_STATUS kbusSetTunableState_DISPATCH(POBJGPU pGpu, struct KernelBus *pEngstate, void *pTunableState) { - return pEngstate->__kbusSetTunableState__(pGpu, pEngstate, pTunableState); -} - static inline NvBool kbusIsPresent_DISPATCH(POBJGPU pGpu, struct KernelBus *pEngstate) { return pEngstate->__kbusIsPresent__(pGpu, pEngstate); } @@ -2229,6 +2320,10 @@ return pKernelBus->bBar1P2pCapable; } +static inline NvBool kbusIsBarAccessBlocked(struct KernelBus *pKernelBus) { + return pKernelBus->bBarAccessBlocked; +} + void kbusDestruct_IMPL(struct KernelBus *pKernelBus); #define __nvoc_kbusDestruct(pKernelBus) kbusDestruct_IMPL(pKernelBus) @@ -2332,15 +2427,15 @@ #define kbusDetermineBar1ApertureLength(pKernelBus, gfid) kbusDetermineBar1ApertureLength_IMPL(pKernelBus, gfid) #endif //__nvoc_kern_bus_h_disabled -NV_STATUS kbusMapFbApertureByHandle_IMPL(OBJGPU *pGpu, struct KernelBus *pKernelBus, NvHandle hClient, NvHandle hMemory, NvU64 offset, NvU64 size, NvU64 *pBar1Va); +NV_STATUS kbusMapFbApertureByHandle_IMPL(OBJGPU *pGpu, struct KernelBus *pKernelBus, NvHandle hClient, NvHandle hMemory, NvU64 offset, NvU64 size, NvU64 *pBar1Va, struct Device *pDevice); #ifdef __nvoc_kern_bus_h_disabled -static inline NV_STATUS kbusMapFbApertureByHandle(OBJGPU *pGpu, struct KernelBus *pKernelBus, NvHandle hClient, NvHandle hMemory, NvU64 offset, NvU64 size, NvU64 *pBar1Va) { +static inline NV_STATUS kbusMapFbApertureByHandle(OBJGPU *pGpu, struct KernelBus *pKernelBus, NvHandle hClient, NvHandle hMemory, NvU64 offset, NvU64 size, NvU64 *pBar1Va, struct Device *pDevice) { NV_ASSERT_FAILED_PRECOMP("KernelBus was disabled!"); return NV_ERR_NOT_SUPPORTED; } #else //__nvoc_kern_bus_h_disabled -#define kbusMapFbApertureByHandle(pGpu, pKernelBus, hClient, hMemory, offset, size, pBar1Va) kbusMapFbApertureByHandle_IMPL(pGpu, pKernelBus, hClient, hMemory, offset, size, pBar1Va) +#define kbusMapFbApertureByHandle(pGpu, pKernelBus, hClient, hMemory, offset, size, pBar1Va, pDevice) kbusMapFbApertureByHandle_IMPL(pGpu, pKernelBus, hClient, hMemory, offset, size, pBar1Va, pDevice) #endif //__nvoc_kern_bus_h_disabled NV_STATUS kbusUnmapFbApertureByHandle_IMPL(OBJGPU *pGpu, struct KernelBus *pKernelBus, NvHandle hClient, NvHandle hMemory, NvU64 bar1Va); @@ -2400,6 +2495,17 @@ kbusUnmapRmApertureWithFlags_HAL(pGpu, pMemDesc, pCpuPtr, \ (bFlush) ? TRANSFER_FLAGS_NONE : TRANSFER_FLAGS_DEFER_FLUSH) +// +// For SHH/GH180, BAR0 PRAMIN and CPU-visible BAR1/2 should be disabled when C2C is being used. +// For P9+GV100, BAR0 PRAMIN and CPU-visible BAR1/2 should never be disabled. +// +#define KBUS_BAR0_PRAMIN_DISABLED(pGpu) \ + ( pGpu->getProperty(pGpu, PDB_PROP_GPU_COHERENT_CPU_MAPPING) && \ + gpuIsSelfHosted(pGpu) ) +#define KBUS_CPU_VISIBLE_BAR12_DISABLED(pGpu) \ + ( pGpu->getProperty(pGpu, PDB_PROP_GPU_COHERENT_CPU_MAPPING) && \ + gpuIsSelfHosted(pGpu) ) + #endif // KERN_BUS_H #ifdef __cplusplus diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/generated/g_kern_disp_nvoc.c nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_kern_disp_nvoc.c --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/generated/g_kern_disp_nvoc.c 2023-10-25 20:27:03.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_kern_disp_nvoc.c 2024-03-05 22:18:22.000000000 +0000 @@ -99,7 +99,7 @@ return kdispStateUnload(pGpu, (struct KernelDisplay *)(((unsigned char *)pKernelDisplay) - __nvoc_rtti_KernelDisplay_OBJENGSTATE.offset), flags); } -static void __nvoc_thunk_KernelDisplay_intrservRegisterIntrService(OBJGPU *pGpu, struct IntrService *pKernelDisplay, IntrServiceRecord pRecords[163]) { +static void __nvoc_thunk_KernelDisplay_intrservRegisterIntrService(OBJGPU *pGpu, struct IntrService *pKernelDisplay, IntrServiceRecord pRecords[167]) { kdispRegisterIntrService(pGpu, (struct KernelDisplay *)(((unsigned char *)pKernelDisplay) - __nvoc_rtti_KernelDisplay_IntrService.offset), pRecords); } @@ -107,10 +107,6 @@ return kdispServiceInterrupt(pGpu, (struct KernelDisplay *)(((unsigned char *)pKernelDisplay) - __nvoc_rtti_KernelDisplay_IntrService.offset), pParams); } -static NV_STATUS __nvoc_thunk_OBJENGSTATE_kdispReconcileTunableState(POBJGPU pGpu, struct KernelDisplay *pEngstate, void *pTunableState) { - return engstateReconcileTunableState(pGpu, (struct OBJENGSTATE *)(((unsigned char *)pEngstate) + __nvoc_rtti_KernelDisplay_OBJENGSTATE.offset), pTunableState); -} - static NV_STATUS __nvoc_thunk_IntrService_kdispServiceNotificationInterrupt(OBJGPU *pGpu, struct KernelDisplay *pIntrService, IntrServiceServiceNotificationInterruptArguments *pParams) { return intrservServiceNotificationInterrupt(pGpu, (struct IntrService *)(((unsigned char *)pIntrService) + __nvoc_rtti_KernelDisplay_IntrService.offset), pParams); } @@ -139,18 +135,6 @@ return engstateStatePreInitUnlocked(pGpu, (struct OBJENGSTATE *)(((unsigned char *)pEngstate) + __nvoc_rtti_KernelDisplay_OBJENGSTATE.offset)); } -static NV_STATUS __nvoc_thunk_OBJENGSTATE_kdispGetTunableState(POBJGPU pGpu, struct KernelDisplay *pEngstate, void *pTunableState) { - return engstateGetTunableState(pGpu, (struct OBJENGSTATE *)(((unsigned char *)pEngstate) + __nvoc_rtti_KernelDisplay_OBJENGSTATE.offset), pTunableState); -} - -static NV_STATUS __nvoc_thunk_OBJENGSTATE_kdispCompareTunableState(POBJGPU pGpu, struct KernelDisplay *pEngstate, void *pTunables1, void *pTunables2) { - return engstateCompareTunableState(pGpu, (struct OBJENGSTATE *)(((unsigned char *)pEngstate) + __nvoc_rtti_KernelDisplay_OBJENGSTATE.offset), pTunables1, pTunables2); -} - -static void __nvoc_thunk_OBJENGSTATE_kdispFreeTunableState(POBJGPU pGpu, struct KernelDisplay *pEngstate, void *pTunableState) { - engstateFreeTunableState(pGpu, (struct OBJENGSTATE *)(((unsigned char *)pEngstate) + __nvoc_rtti_KernelDisplay_OBJENGSTATE.offset), pTunableState); -} - static NvBool __nvoc_thunk_IntrService_kdispClearInterrupt(OBJGPU *pGpu, struct KernelDisplay *pIntrService, IntrServiceClearInterruptArguments *pParams) { return intrservClearInterrupt(pGpu, (struct IntrService *)(((unsigned char *)pIntrService) + __nvoc_rtti_KernelDisplay_IntrService.offset), pParams); } @@ -159,14 +143,6 @@ return engstateStatePostLoad(pGpu, (struct OBJENGSTATE *)(((unsigned char *)pEngstate) + __nvoc_rtti_KernelDisplay_OBJENGSTATE.offset), arg0); } -static NV_STATUS __nvoc_thunk_OBJENGSTATE_kdispAllocTunableState(POBJGPU pGpu, struct KernelDisplay *pEngstate, void **ppTunableState) { - return engstateAllocTunableState(pGpu, (struct OBJENGSTATE *)(((unsigned char *)pEngstate) + __nvoc_rtti_KernelDisplay_OBJENGSTATE.offset), ppTunableState); -} - -static NV_STATUS __nvoc_thunk_OBJENGSTATE_kdispSetTunableState(POBJGPU pGpu, struct KernelDisplay *pEngstate, void *pTunableState) { - return engstateSetTunableState(pGpu, (struct OBJENGSTATE *)(((unsigned char *)pEngstate) + __nvoc_rtti_KernelDisplay_OBJENGSTATE.offset), pTunableState); -} - static NvBool __nvoc_thunk_OBJENGSTATE_kdispIsPresent(POBJGPU pGpu, struct KernelDisplay *pEngstate) { return engstateIsPresent(pGpu, (struct OBJENGSTATE *)(((unsigned char *)pEngstate) + __nvoc_rtti_KernelDisplay_OBJENGSTATE.offset)); } @@ -209,11 +185,17 @@ } // NVOC Property Hal field -- PDB_PROP_KDISP_IMP_ENABLE - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x11f0ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 | GH100 */ + if (((( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x11f0ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 | GH100 */ && (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000002UL) )) /* RmVariantHal: PF_KERNEL_ONLY */ )) { pThis->setProperty(pThis, PDB_PROP_KDISP_IMP_ENABLE, ((NvBool)(0 == 0))); } + // NVOC Property Hal field -- PDB_PROP_KDISP_BUG_2089053_SERIALIZE_AGGRESSIVE_VBLANK_ALWAYS + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x11f0ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 | GH100 */ + { + pThis->setProperty(pThis, PDB_PROP_KDISP_BUG_2089053_SERIALIZE_AGGRESSIVE_VBLANK_ALWAYS, ((NvBool)(0 == 0))); + } + pThis->pStaticInfo = ((void *)0); pThis->bWarPurgeSatellitesOnCoreFree = ((NvBool)(0 != 0)); @@ -271,122 +253,140 @@ pThis->__kdispRegisterIntrService__ = &kdispRegisterIntrService_IMPL; // Hal function -- kdispServiceInterrupt - if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000002UL) )) /* RmVariantHal: PF_KERNEL_ONLY */ - { - pThis->__kdispServiceInterrupt__ = &kdispServiceInterrupt_d3ef2b; - } + pThis->__kdispServiceInterrupt__ = &kdispServiceInterrupt_acff5e; // Hal function -- kdispSelectClass - if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000002UL) )) /* RmVariantHal: PF_KERNEL_ONLY */ + if (( ((dispIpHal_HalVarIdx >> 5) == 0UL) && ((1UL << (dispIpHal_HalVarIdx & 0x1f)) & 0x00020000UL) )) /* DispIpHal: DISPv0000 */ { - if (( ((dispIpHal_HalVarIdx >> 5) == 0UL) && ((1UL << (dispIpHal_HalVarIdx & 0x1f)) & 0x00008000UL) )) /* DispIpHal: DISPv0000 */ - { - pThis->__kdispSelectClass__ = &kdispSelectClass_46f6a7; - } - else if (( ((dispIpHal_HalVarIdx >> 5) == 0UL) && ((1UL << (dispIpHal_HalVarIdx & 0x1f)) & 0x00004c00UL) )) /* DispIpHal: DISPv0400 | DISPv0401 | DISPv0404 */ - { - pThis->__kdispSelectClass__ = &kdispSelectClass_v03_00_KERNEL; - } + pThis->__kdispSelectClass__ = &kdispSelectClass_46f6a7; + } + else + { + pThis->__kdispSelectClass__ = &kdispSelectClass_v03_00_KERNEL; } // Hal function -- kdispGetChannelNum - if (( ((dispIpHal_HalVarIdx >> 5) == 0UL) && ((1UL << (dispIpHal_HalVarIdx & 0x1f)) & 0x00008000UL) )) /* DispIpHal: DISPv0000 */ + if (( ((dispIpHal_HalVarIdx >> 5) == 0UL) && ((1UL << (dispIpHal_HalVarIdx & 0x1f)) & 0x00020000UL) )) /* DispIpHal: DISPv0000 */ { pThis->__kdispGetChannelNum__ = &kdispGetChannelNum_46f6a7; } - else if (( ((dispIpHal_HalVarIdx >> 5) == 0UL) && ((1UL << (dispIpHal_HalVarIdx & 0x1f)) & 0x00004c00UL) )) /* DispIpHal: DISPv0400 | DISPv0401 | DISPv0404 */ + else { pThis->__kdispGetChannelNum__ = &kdispGetChannelNum_v03_00; } // Hal function -- kdispGetDisplayCapsBaseAndSize - if (((( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000400UL) )) /* ChipHal: GA100 | GH100 */ && (( ((dispIpHal_HalVarIdx >> 5) == 0UL) && ((1UL << (dispIpHal_HalVarIdx & 0x1f)) & 0x00008000UL) )) /* DispIpHal: DISPv0000 */ )) + if (((( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000400UL) )) /* ChipHal: GA100 | GH100 */ && (( ((dispIpHal_HalVarIdx >> 5) == 0UL) && ((1UL << (dispIpHal_HalVarIdx & 0x1f)) & 0x00020000UL) )) /* DispIpHal: DISPv0000 */ )) { pThis->__kdispGetDisplayCapsBaseAndSize__ = &kdispGetDisplayCapsBaseAndSize_b3696a; } - else if (((( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x000003e0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 */ && (( ((dispIpHal_HalVarIdx >> 5) == 0UL) && ((1UL << (dispIpHal_HalVarIdx & 0x1f)) & 0x00000400UL) )) /* DispIpHal: DISPv0400 */ ) || - ((( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0000f800UL) )) /* ChipHal: GA102 | GA103 | GA104 | GA106 | GA107 */ && (( ((dispIpHal_HalVarIdx >> 5) == 0UL) && ((1UL << (dispIpHal_HalVarIdx & 0x1f)) & 0x00000800UL) )) /* DispIpHal: DISPv0401 */ ) || - ((( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x01f00000UL) )) /* ChipHal: AD102 | AD103 | AD104 | AD106 | AD107 */ && (( ((dispIpHal_HalVarIdx >> 5) == 0UL) && ((1UL << (dispIpHal_HalVarIdx & 0x1f)) & 0x00004000UL) )) /* DispIpHal: DISPv0404 */ )) + else { pThis->__kdispGetDisplayCapsBaseAndSize__ = &kdispGetDisplayCapsBaseAndSize_v03_00; } // Hal function -- kdispGetDisplaySfUserBaseAndSize - if (( ((dispIpHal_HalVarIdx >> 5) == 0UL) && ((1UL << (dispIpHal_HalVarIdx & 0x1f)) & 0x00008000UL) )) /* DispIpHal: DISPv0000 */ + if (( ((dispIpHal_HalVarIdx >> 5) == 0UL) && ((1UL << (dispIpHal_HalVarIdx & 0x1f)) & 0x00020000UL) )) /* DispIpHal: DISPv0000 */ { pThis->__kdispGetDisplaySfUserBaseAndSize__ = &kdispGetDisplaySfUserBaseAndSize_b3696a; } - else if (( ((dispIpHal_HalVarIdx >> 5) == 0UL) && ((1UL << (dispIpHal_HalVarIdx & 0x1f)) & 0x00004c00UL) )) /* DispIpHal: DISPv0400 | DISPv0401 | DISPv0404 */ + else { pThis->__kdispGetDisplaySfUserBaseAndSize__ = &kdispGetDisplaySfUserBaseAndSize_v03_00; } // Hal function -- kdispGetDisplayChannelUserBaseAndSize - if (( ((dispIpHal_HalVarIdx >> 5) == 0UL) && ((1UL << (dispIpHal_HalVarIdx & 0x1f)) & 0x00008000UL) )) /* DispIpHal: DISPv0000 */ + if (( ((dispIpHal_HalVarIdx >> 5) == 0UL) && ((1UL << (dispIpHal_HalVarIdx & 0x1f)) & 0x00020000UL) )) /* DispIpHal: DISPv0000 */ { pThis->__kdispGetDisplayChannelUserBaseAndSize__ = &kdispGetDisplayChannelUserBaseAndSize_46f6a7; } - else if (( ((dispIpHal_HalVarIdx >> 5) == 0UL) && ((1UL << (dispIpHal_HalVarIdx & 0x1f)) & 0x00004c00UL) )) /* DispIpHal: DISPv0400 | DISPv0401 | DISPv0404 */ + else { pThis->__kdispGetDisplayChannelUserBaseAndSize__ = &kdispGetDisplayChannelUserBaseAndSize_v03_00; } // Hal function -- kdispGetVgaWorkspaceBase - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x01f0fbe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 */ + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000400UL) )) /* ChipHal: GA100 | GH100 */ { - pThis->__kdispGetVgaWorkspaceBase__ = &kdispGetVgaWorkspaceBase_v04_00; + pThis->__kdispGetVgaWorkspaceBase__ = &kdispGetVgaWorkspaceBase_491d52; } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000400UL) )) /* ChipHal: GA100 | GH100 */ + else { - pThis->__kdispGetVgaWorkspaceBase__ = &kdispGetVgaWorkspaceBase_491d52; + pThis->__kdispGetVgaWorkspaceBase__ = &kdispGetVgaWorkspaceBase_v04_00; } // Hal function -- kdispReadRgLineCountAndFrameCount - if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000002UL) )) /* RmVariantHal: PF_KERNEL_ONLY */ + if (( ((dispIpHal_HalVarIdx >> 5) == 0UL) && ((1UL << (dispIpHal_HalVarIdx & 0x1f)) & 0x00004c00UL) )) /* DispIpHal: DISPv0400 | DISPv0401 | DISPv0404 */ + { + pThis->__kdispReadRgLineCountAndFrameCount__ = &kdispReadRgLineCountAndFrameCount_v03_00_KERNEL; + } + // default + else { - if (( ((dispIpHal_HalVarIdx >> 5) == 0UL) && ((1UL << (dispIpHal_HalVarIdx & 0x1f)) & 0x00004c00UL) )) /* DispIpHal: DISPv0400 | DISPv0401 | DISPv0404 */ - { - pThis->__kdispReadRgLineCountAndFrameCount__ = &kdispReadRgLineCountAndFrameCount_v03_00_KERNEL; - } - // default - else - { - pThis->__kdispReadRgLineCountAndFrameCount__ = &kdispReadRgLineCountAndFrameCount_46f6a7; - } + pThis->__kdispReadRgLineCountAndFrameCount__ = &kdispReadRgLineCountAndFrameCount_46f6a7; } // Hal function -- kdispRestoreOriginalLsrMinTime - if (((( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x000003e0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 */ && (( ((dispIpHal_HalVarIdx >> 5) == 0UL) && ((1UL << (dispIpHal_HalVarIdx & 0x1f)) & 0x00000400UL) )) /* DispIpHal: DISPv0400 */ ) || - ((( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0000f800UL) )) /* ChipHal: GA102 | GA103 | GA104 | GA106 | GA107 */ && (( ((dispIpHal_HalVarIdx >> 5) == 0UL) && ((1UL << (dispIpHal_HalVarIdx & 0x1f)) & 0x00000800UL) )) /* DispIpHal: DISPv0401 */ ) || - ((( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x01f00000UL) )) /* ChipHal: AD102 | AD103 | AD104 | AD106 | AD107 */ && (( ((dispIpHal_HalVarIdx >> 5) == 0UL) && ((1UL << (dispIpHal_HalVarIdx & 0x1f)) & 0x00004000UL) )) /* DispIpHal: DISPv0404 */ )) + if (((( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000400UL) )) /* ChipHal: GA100 | GH100 */ && (( ((dispIpHal_HalVarIdx >> 5) == 0UL) && ((1UL << (dispIpHal_HalVarIdx & 0x1f)) & 0x00020000UL) )) /* DispIpHal: DISPv0000 */ )) { - pThis->__kdispRestoreOriginalLsrMinTime__ = &kdispRestoreOriginalLsrMinTime_v03_00; + pThis->__kdispRestoreOriginalLsrMinTime__ = &kdispRestoreOriginalLsrMinTime_b3696a; } - else if (((( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000400UL) )) /* ChipHal: GA100 | GH100 */ && (( ((dispIpHal_HalVarIdx >> 5) == 0UL) && ((1UL << (dispIpHal_HalVarIdx & 0x1f)) & 0x00008000UL) )) /* DispIpHal: DISPv0000 */ )) + else { - pThis->__kdispRestoreOriginalLsrMinTime__ = &kdispRestoreOriginalLsrMinTime_b3696a; + pThis->__kdispRestoreOriginalLsrMinTime__ = &kdispRestoreOriginalLsrMinTime_v03_00; } // Hal function -- kdispComputeLsrMinTimeValue - if (( ((dispIpHal_HalVarIdx >> 5) == 0UL) && ((1UL << (dispIpHal_HalVarIdx & 0x1f)) & 0x00004c00UL) )) /* DispIpHal: DISPv0400 | DISPv0401 | DISPv0404 */ + if (( ((dispIpHal_HalVarIdx >> 5) == 0UL) && ((1UL << (dispIpHal_HalVarIdx & 0x1f)) & 0x00020000UL) )) /* DispIpHal: DISPv0000 */ { - pThis->__kdispComputeLsrMinTimeValue__ = &kdispComputeLsrMinTimeValue_v02_07; + pThis->__kdispComputeLsrMinTimeValue__ = &kdispComputeLsrMinTimeValue_56cd7a; } - else if (( ((dispIpHal_HalVarIdx >> 5) == 0UL) && ((1UL << (dispIpHal_HalVarIdx & 0x1f)) & 0x00008000UL) )) /* DispIpHal: DISPv0000 */ + else { - pThis->__kdispComputeLsrMinTimeValue__ = &kdispComputeLsrMinTimeValue_56cd7a; + pThis->__kdispComputeLsrMinTimeValue__ = &kdispComputeLsrMinTimeValue_v02_07; } // Hal function -- kdispSetSwapBarrierLsrMinTime - if (((( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x000003e0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 */ && (( ((dispIpHal_HalVarIdx >> 5) == 0UL) && ((1UL << (dispIpHal_HalVarIdx & 0x1f)) & 0x00000400UL) )) /* DispIpHal: DISPv0400 */ ) || - ((( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0000f800UL) )) /* ChipHal: GA102 | GA103 | GA104 | GA106 | GA107 */ && (( ((dispIpHal_HalVarIdx >> 5) == 0UL) && ((1UL << (dispIpHal_HalVarIdx & 0x1f)) & 0x00000800UL) )) /* DispIpHal: DISPv0401 */ ) || - ((( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x01f00000UL) )) /* ChipHal: AD102 | AD103 | AD104 | AD106 | AD107 */ && (( ((dispIpHal_HalVarIdx >> 5) == 0UL) && ((1UL << (dispIpHal_HalVarIdx & 0x1f)) & 0x00004000UL) )) /* DispIpHal: DISPv0404 */ )) + if (((( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000400UL) )) /* ChipHal: GA100 | GH100 */ && (( ((dispIpHal_HalVarIdx >> 5) == 0UL) && ((1UL << (dispIpHal_HalVarIdx & 0x1f)) & 0x00020000UL) )) /* DispIpHal: DISPv0000 */ )) + { + pThis->__kdispSetSwapBarrierLsrMinTime__ = &kdispSetSwapBarrierLsrMinTime_b3696a; + } + else { pThis->__kdispSetSwapBarrierLsrMinTime__ = &kdispSetSwapBarrierLsrMinTime_v03_00; } - else if (((( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000400UL) )) /* ChipHal: GA100 | GH100 */ && (( ((dispIpHal_HalVarIdx >> 5) == 0UL) && ((1UL << (dispIpHal_HalVarIdx & 0x1f)) & 0x00008000UL) )) /* DispIpHal: DISPv0000 */ )) + + // Hal function -- kdispGetRgScanLock + if (( ((dispIpHal_HalVarIdx >> 5) == 0UL) && ((1UL << (dispIpHal_HalVarIdx & 0x1f)) & 0x00004c00UL) )) /* DispIpHal: DISPv0400 | DISPv0401 | DISPv0404 */ { - pThis->__kdispSetSwapBarrierLsrMinTime__ = &kdispSetSwapBarrierLsrMinTime_b3696a; + pThis->__kdispGetRgScanLock__ = &kdispGetRgScanLock_v02_01; + } + // default + else + { + pThis->__kdispGetRgScanLock__ = &kdispGetRgScanLock_92bfc3; + } + + // Hal function -- kdispDetectSliLink + if (( ((dispIpHal_HalVarIdx >> 5) == 0UL) && ((1UL << (dispIpHal_HalVarIdx & 0x1f)) & 0x00004c00UL) )) /* DispIpHal: DISPv0400 | DISPv0401 | DISPv0404 */ + { + pThis->__kdispDetectSliLink__ = &kdispDetectSliLink_v04_00; + } + // default + else + { + pThis->__kdispDetectSliLink__ = &kdispDetectSliLink_92bfc3; + } + + // Hal function -- kdispInitRegistryOverrides + if (((( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000400UL) )) /* ChipHal: GA100 | GH100 */ && (( ((dispIpHal_HalVarIdx >> 5) == 0UL) && ((1UL << (dispIpHal_HalVarIdx & 0x1f)) & 0x00020000UL) )) /* DispIpHal: DISPv0000 */ )) + { + pThis->__kdispInitRegistryOverrides__ = &kdispInitRegistryOverrides_b3696a; + } + // default + else + { + pThis->__kdispInitRegistryOverrides__ = &kdispInitRegistryOverrides_IMPL; } pThis->__nvoc_base_OBJENGSTATE.__engstateConstructEngine__ = &__nvoc_thunk_KernelDisplay_engstateConstructEngine; @@ -405,8 +405,6 @@ pThis->__nvoc_base_IntrService.__intrservServiceInterrupt__ = &__nvoc_thunk_KernelDisplay_intrservServiceInterrupt; - pThis->__kdispReconcileTunableState__ = &__nvoc_thunk_OBJENGSTATE_kdispReconcileTunableState; - pThis->__kdispServiceNotificationInterrupt__ = &__nvoc_thunk_IntrService_kdispServiceNotificationInterrupt; pThis->__kdispStatePreLoad__ = &__nvoc_thunk_OBJENGSTATE_kdispStatePreLoad; @@ -421,20 +419,10 @@ pThis->__kdispStatePreInitUnlocked__ = &__nvoc_thunk_OBJENGSTATE_kdispStatePreInitUnlocked; - pThis->__kdispGetTunableState__ = &__nvoc_thunk_OBJENGSTATE_kdispGetTunableState; - - pThis->__kdispCompareTunableState__ = &__nvoc_thunk_OBJENGSTATE_kdispCompareTunableState; - - pThis->__kdispFreeTunableState__ = &__nvoc_thunk_OBJENGSTATE_kdispFreeTunableState; - pThis->__kdispClearInterrupt__ = &__nvoc_thunk_IntrService_kdispClearInterrupt; pThis->__kdispStatePostLoad__ = &__nvoc_thunk_OBJENGSTATE_kdispStatePostLoad; - pThis->__kdispAllocTunableState__ = &__nvoc_thunk_OBJENGSTATE_kdispAllocTunableState; - - pThis->__kdispSetTunableState__ = &__nvoc_thunk_OBJENGSTATE_kdispSetTunableState; - pThis->__kdispIsPresent__ = &__nvoc_thunk_OBJENGSTATE_kdispIsPresent; } @@ -460,13 +448,16 @@ KernelDisplay *pThis; RmHalspecOwner *pRmhalspecowner; - pThis = portMemAllocNonPaged(sizeof(KernelDisplay)); - if (pThis == NULL) return NV_ERR_NO_MEMORY; + status = __nvoc_handleObjCreateMemAlloc(createFlags, sizeof(KernelDisplay), (void**)&pThis, (void**)ppThis); + if (status != NV_OK) + return status; portMemSet(pThis, 0, sizeof(KernelDisplay)); __nvoc_initRtti(staticCast(pThis, Dynamic), &__nvoc_class_def_KernelDisplay); + pThis->__nvoc_base_OBJENGSTATE.__nvoc_base_Object.createFlags = createFlags; + if (pParent != NULL && !(createFlags & NVOC_OBJ_CREATE_FLAGS_PARENT_HALSPEC_ONLY)) { pParentObj = dynamicCast(pParent, Object); @@ -486,11 +477,17 @@ if (status != NV_OK) goto __nvoc_objCreate_KernelDisplay_cleanup; *ppThis = pThis; + return NV_OK; __nvoc_objCreate_KernelDisplay_cleanup: // do not call destructors here since the constructor already called them - portMemFree(pThis); + if (createFlags & NVOC_OBJ_CREATE_FLAGS_IN_PLACE_CONSTRUCT) + portMemSet(pThis, 0, sizeof(KernelDisplay)); + else + portMemFree(pThis); + + // coverity[leaked_storage:FALSE] return status; } diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/generated/g_kern_disp_nvoc.h nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_kern_disp_nvoc.h --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/generated/g_kern_disp_nvoc.h 2023-10-25 20:27:04.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_kern_disp_nvoc.h 2024-03-05 22:18:22.000000000 +0000 @@ -118,7 +118,9 @@ void (*__kdispRestoreOriginalLsrMinTime__)(OBJGPU *, struct KernelDisplay *, NvU32, NvU32); NV_STATUS (*__kdispComputeLsrMinTimeValue__)(OBJGPU *, struct KernelDisplay *, NvU32, NvU32, NvU32 *); void (*__kdispSetSwapBarrierLsrMinTime__)(OBJGPU *, struct KernelDisplay *, NvU32, NvU32 *, NvU32); - NV_STATUS (*__kdispReconcileTunableState__)(POBJGPU, struct KernelDisplay *, void *); + NV_STATUS (*__kdispGetRgScanLock__)(OBJGPU *, struct KernelDisplay *, NvU32, OBJGPU *, NvU32, NvBool *, NvU32 *, NvBool *, NvU32 *); + NV_STATUS (*__kdispDetectSliLink__)(struct KernelDisplay *, OBJGPU *, OBJGPU *, NvU32, NvU32); + void (*__kdispInitRegistryOverrides__)(OBJGPU *, struct KernelDisplay *); NV_STATUS (*__kdispServiceNotificationInterrupt__)(OBJGPU *, struct KernelDisplay *, IntrServiceServiceNotificationInterruptArguments *); NV_STATUS (*__kdispStatePreLoad__)(POBJGPU, struct KernelDisplay *, NvU32); NV_STATUS (*__kdispStatePostUnload__)(POBJGPU, struct KernelDisplay *, NvU32); @@ -126,15 +128,13 @@ NV_STATUS (*__kdispStateInitUnlocked__)(POBJGPU, struct KernelDisplay *); void (*__kdispInitMissing__)(POBJGPU, struct KernelDisplay *); NV_STATUS (*__kdispStatePreInitUnlocked__)(POBJGPU, struct KernelDisplay *); - NV_STATUS (*__kdispGetTunableState__)(POBJGPU, struct KernelDisplay *, void *); - NV_STATUS (*__kdispCompareTunableState__)(POBJGPU, struct KernelDisplay *, void *, void *); - void (*__kdispFreeTunableState__)(POBJGPU, struct KernelDisplay *, void *); NvBool (*__kdispClearInterrupt__)(OBJGPU *, struct KernelDisplay *, IntrServiceClearInterruptArguments *); NV_STATUS (*__kdispStatePostLoad__)(POBJGPU, struct KernelDisplay *, NvU32); - NV_STATUS (*__kdispAllocTunableState__)(POBJGPU, struct KernelDisplay *, void **); - NV_STATUS (*__kdispSetTunableState__)(POBJGPU, struct KernelDisplay *, void *); NvBool (*__kdispIsPresent__)(POBJGPU, struct KernelDisplay *); NvBool PDB_PROP_KDISP_IMP_ENABLE; + NvBool PDB_PROP_KDISP_BUG_2089053_SERIALIZE_AGGRESSIVE_VBLANK_ALWAYS; + NvBool PDB_PROP_KDISP_BUG_2089053_SERIALIZE_AGGRESSIVE_VBLANKS_ONLY_ON_HMD_ACTIVE; + NvBool PDB_PROP_KDISP_IN_AWAKEN_INTR; struct DisplayInstanceMemory *pInst; struct KernelHead *pKernelHead[4]; const KernelDisplayStaticInfo *pStaticInfo; @@ -143,6 +143,11 @@ NvU32 isrVblankHeads; NvBool bExtdevIntrSupported; NvU32 numHeads; + NvU32 deferredVblankHeadMask; + NvHandle hInternalClient; + NvHandle hInternalDevice; + NvHandle hInternalSubdevice; + NvHandle hDispCommonHandle; }; #ifndef __NVOC_CLASS_KernelDisplay_TYPEDEF__ @@ -168,8 +173,14 @@ #define PDB_PROP_KDISP_IS_MISSING_BASE_CAST __nvoc_base_OBJENGSTATE. #define PDB_PROP_KDISP_IS_MISSING_BASE_NAME PDB_PROP_ENGSTATE_IS_MISSING +#define PDB_PROP_KDISP_IN_AWAKEN_INTR_BASE_CAST +#define PDB_PROP_KDISP_IN_AWAKEN_INTR_BASE_NAME PDB_PROP_KDISP_IN_AWAKEN_INTR +#define PDB_PROP_KDISP_BUG_2089053_SERIALIZE_AGGRESSIVE_VBLANK_ALWAYS_BASE_CAST +#define PDB_PROP_KDISP_BUG_2089053_SERIALIZE_AGGRESSIVE_VBLANK_ALWAYS_BASE_NAME PDB_PROP_KDISP_BUG_2089053_SERIALIZE_AGGRESSIVE_VBLANK_ALWAYS #define PDB_PROP_KDISP_IMP_ENABLE_BASE_CAST #define PDB_PROP_KDISP_IMP_ENABLE_BASE_NAME PDB_PROP_KDISP_IMP_ENABLE +#define PDB_PROP_KDISP_BUG_2089053_SERIALIZE_AGGRESSIVE_VBLANKS_ONLY_ON_HMD_ACTIVE_BASE_CAST +#define PDB_PROP_KDISP_BUG_2089053_SERIALIZE_AGGRESSIVE_VBLANKS_ONLY_ON_HMD_ACTIVE_BASE_NAME PDB_PROP_KDISP_BUG_2089053_SERIALIZE_AGGRESSIVE_VBLANKS_ONLY_ON_HMD_ACTIVE NV_STATUS __nvoc_objCreateDynamic_KernelDisplay(KernelDisplay**, Dynamic*, NvU32, va_list); @@ -206,7 +217,12 @@ #define kdispComputeLsrMinTimeValue_HAL(pGpu, pKernelDisplay, head, swapRdyHiLsrMinTime, pComputedLsrMinTime) kdispComputeLsrMinTimeValue_DISPATCH(pGpu, pKernelDisplay, head, swapRdyHiLsrMinTime, pComputedLsrMinTime) #define kdispSetSwapBarrierLsrMinTime(pGpu, pKernelDisplay, head, pOrigLsrMinTime, newLsrMinTime) kdispSetSwapBarrierLsrMinTime_DISPATCH(pGpu, pKernelDisplay, head, pOrigLsrMinTime, newLsrMinTime) #define kdispSetSwapBarrierLsrMinTime_HAL(pGpu, pKernelDisplay, head, pOrigLsrMinTime, newLsrMinTime) kdispSetSwapBarrierLsrMinTime_DISPATCH(pGpu, pKernelDisplay, head, pOrigLsrMinTime, newLsrMinTime) -#define kdispReconcileTunableState(pGpu, pEngstate, pTunableState) kdispReconcileTunableState_DISPATCH(pGpu, pEngstate, pTunableState) +#define kdispGetRgScanLock(pGpu, pKernelDisplay, head0, pPeerGpu, head1, pMasterScanLock, pMasterScanLockPin, pSlaveScanLock, pSlaveScanLockPin) kdispGetRgScanLock_DISPATCH(pGpu, pKernelDisplay, head0, pPeerGpu, head1, pMasterScanLock, pMasterScanLockPin, pSlaveScanLock, pSlaveScanLockPin) +#define kdispGetRgScanLock_HAL(pGpu, pKernelDisplay, head0, pPeerGpu, head1, pMasterScanLock, pMasterScanLockPin, pSlaveScanLock, pSlaveScanLockPin) kdispGetRgScanLock_DISPATCH(pGpu, pKernelDisplay, head0, pPeerGpu, head1, pMasterScanLock, pMasterScanLockPin, pSlaveScanLock, pSlaveScanLockPin) +#define kdispDetectSliLink(pKernelDisplay, pParentGpu, pChildGpu, ParentDrPort, ChildDrPort) kdispDetectSliLink_DISPATCH(pKernelDisplay, pParentGpu, pChildGpu, ParentDrPort, ChildDrPort) +#define kdispDetectSliLink_HAL(pKernelDisplay, pParentGpu, pChildGpu, ParentDrPort, ChildDrPort) kdispDetectSliLink_DISPATCH(pKernelDisplay, pParentGpu, pChildGpu, ParentDrPort, ChildDrPort) +#define kdispInitRegistryOverrides(pGpu, pKernelDisplay) kdispInitRegistryOverrides_DISPATCH(pGpu, pKernelDisplay) +#define kdispInitRegistryOverrides_HAL(pGpu, pKernelDisplay) kdispInitRegistryOverrides_DISPATCH(pGpu, pKernelDisplay) #define kdispServiceNotificationInterrupt(pGpu, pIntrService, pParams) kdispServiceNotificationInterrupt_DISPATCH(pGpu, pIntrService, pParams) #define kdispStatePreLoad(pGpu, pEngstate, arg0) kdispStatePreLoad_DISPATCH(pGpu, pEngstate, arg0) #define kdispStatePostUnload(pGpu, pEngstate, arg0) kdispStatePostUnload_DISPATCH(pGpu, pEngstate, arg0) @@ -214,13 +230,8 @@ #define kdispStateInitUnlocked(pGpu, pEngstate) kdispStateInitUnlocked_DISPATCH(pGpu, pEngstate) #define kdispInitMissing(pGpu, pEngstate) kdispInitMissing_DISPATCH(pGpu, pEngstate) #define kdispStatePreInitUnlocked(pGpu, pEngstate) kdispStatePreInitUnlocked_DISPATCH(pGpu, pEngstate) -#define kdispGetTunableState(pGpu, pEngstate, pTunableState) kdispGetTunableState_DISPATCH(pGpu, pEngstate, pTunableState) -#define kdispCompareTunableState(pGpu, pEngstate, pTunables1, pTunables2) kdispCompareTunableState_DISPATCH(pGpu, pEngstate, pTunables1, pTunables2) -#define kdispFreeTunableState(pGpu, pEngstate, pTunableState) kdispFreeTunableState_DISPATCH(pGpu, pEngstate, pTunableState) #define kdispClearInterrupt(pGpu, pIntrService, pParams) kdispClearInterrupt_DISPATCH(pGpu, pIntrService, pParams) #define kdispStatePostLoad(pGpu, pEngstate, arg0) kdispStatePostLoad_DISPATCH(pGpu, pEngstate, arg0) -#define kdispAllocTunableState(pGpu, pEngstate, ppTunableState) kdispAllocTunableState_DISPATCH(pGpu, pEngstate, ppTunableState) -#define kdispSetTunableState(pGpu, pEngstate, pTunableState) kdispSetTunableState_DISPATCH(pGpu, pEngstate, pTunableState) #define kdispIsPresent(pGpu, pEngstate) kdispIsPresent_DISPATCH(pGpu, pEngstate) NV_STATUS kdispConstructInstMem_IMPL(struct KernelDisplay *pKernelDisplay); @@ -410,7 +421,7 @@ #define kdispServiceVblank_HAL(pGpu, pKernelDisplay, arg0, arg1, arg2) kdispServiceVblank(pGpu, pKernelDisplay, arg0, arg1, arg2) -NvU32 kdispReadPendingVblank_KERNEL(OBJGPU *pGpu, struct KernelDisplay *pKernelDisplay, struct THREAD_STATE_NODE *arg0); +NvU32 kdispReadPendingVblank_IMPL(OBJGPU *pGpu, struct KernelDisplay *pKernelDisplay, struct THREAD_STATE_NODE *arg0); #ifdef __nvoc_kern_disp_h_disabled @@ -419,7 +430,7 @@ return 0; } #else //__nvoc_kern_disp_h_disabled -#define kdispReadPendingVblank(pGpu, pKernelDisplay, arg0) kdispReadPendingVblank_KERNEL(pGpu, pKernelDisplay, arg0) +#define kdispReadPendingVblank(pGpu, pKernelDisplay, arg0) kdispReadPendingVblank_IMPL(pGpu, pKernelDisplay, arg0) #endif //__nvoc_kern_disp_h_disabled #define kdispReadPendingVblank_HAL(pGpu, pKernelDisplay, arg0) kdispReadPendingVblank(pGpu, pKernelDisplay, arg0) @@ -470,6 +481,93 @@ #define kdispInitBrightcStateLoad_HAL(pGpu, pKernelDisplay) kdispInitBrightcStateLoad(pGpu, pKernelDisplay) +NV_STATUS kdispSetupAcpiEdid_IMPL(OBJGPU *pGpu, struct KernelDisplay *pKernelDisplay); + + +#ifdef __nvoc_kern_disp_h_disabled +static inline NV_STATUS kdispSetupAcpiEdid(OBJGPU *pGpu, struct KernelDisplay *pKernelDisplay) { + NV_ASSERT_FAILED_PRECOMP("KernelDisplay was disabled!"); + return NV_ERR_NOT_SUPPORTED; +} +#else //__nvoc_kern_disp_h_disabled +#define kdispSetupAcpiEdid(pGpu, pKernelDisplay) kdispSetupAcpiEdid_IMPL(pGpu, pKernelDisplay) +#endif //__nvoc_kern_disp_h_disabled + +#define kdispSetupAcpiEdid_HAL(pGpu, pKernelDisplay) kdispSetupAcpiEdid(pGpu, pKernelDisplay) + +static inline NvBool kdispReadPendingAwakenIntr_ceaee8(OBJGPU *pGpu, struct KernelDisplay *pKernelDisplay, NvU32 *pCachedIntr, struct THREAD_STATE_NODE *arg0) { + NV_ASSERT_PRECOMP(0); + return ((NvBool)(0 != 0)); +} + +NvBool kdispReadPendingAwakenIntr_v03_00_IMPL(OBJGPU *pGpu, struct KernelDisplay *pKernelDisplay, NvU32 *pCachedIntr, struct THREAD_STATE_NODE *arg0); + +static inline NvBool kdispReadPendingAwakenIntr_491d52(OBJGPU *pGpu, struct KernelDisplay *pKernelDisplay, NvU32 *pCachedIntr, struct THREAD_STATE_NODE *arg0) { + return ((NvBool)(0 != 0)); +} + + +#ifdef __nvoc_kern_disp_h_disabled +static inline NvBool kdispReadPendingAwakenIntr(OBJGPU *pGpu, struct KernelDisplay *pKernelDisplay, NvU32 *pCachedIntr, struct THREAD_STATE_NODE *arg0) { + NV_ASSERT_FAILED_PRECOMP("KernelDisplay was disabled!"); + return NV_FALSE; +} +#else //__nvoc_kern_disp_h_disabled +#define kdispReadPendingAwakenIntr(pGpu, pKernelDisplay, pCachedIntr, arg0) kdispReadPendingAwakenIntr_ceaee8(pGpu, pKernelDisplay, pCachedIntr, arg0) +#endif //__nvoc_kern_disp_h_disabled + +#define kdispReadPendingAwakenIntr_HAL(pGpu, pKernelDisplay, pCachedIntr, arg0) kdispReadPendingAwakenIntr(pGpu, pKernelDisplay, pCachedIntr, arg0) + +static inline NV_STATUS kdispReadAwakenChannelNumMask_92bfc3(OBJGPU *pGpu, struct KernelDisplay *pKernelDisplay, NvU32 *arg0, DISPCHNCLASS arg1, struct THREAD_STATE_NODE *arg2) { + NV_ASSERT_PRECOMP(0); + return NV_ERR_NOT_SUPPORTED; +} + +NV_STATUS kdispReadAwakenChannelNumMask_v03_00_IMPL(OBJGPU *pGpu, struct KernelDisplay *pKernelDisplay, NvU32 *arg0, DISPCHNCLASS arg1, struct THREAD_STATE_NODE *arg2); + +static inline NV_STATUS kdispReadAwakenChannelNumMask_46f6a7(OBJGPU *pGpu, struct KernelDisplay *pKernelDisplay, NvU32 *arg0, DISPCHNCLASS arg1, struct THREAD_STATE_NODE *arg2) { + return NV_ERR_NOT_SUPPORTED; +} + + +#ifdef __nvoc_kern_disp_h_disabled +static inline NV_STATUS kdispReadAwakenChannelNumMask(OBJGPU *pGpu, struct KernelDisplay *pKernelDisplay, NvU32 *arg0, DISPCHNCLASS arg1, struct THREAD_STATE_NODE *arg2) { + NV_ASSERT_FAILED_PRECOMP("KernelDisplay was disabled!"); + return NV_ERR_NOT_SUPPORTED; +} +#else //__nvoc_kern_disp_h_disabled +#define kdispReadAwakenChannelNumMask(pGpu, pKernelDisplay, arg0, arg1, arg2) kdispReadAwakenChannelNumMask_92bfc3(pGpu, pKernelDisplay, arg0, arg1, arg2) +#endif //__nvoc_kern_disp_h_disabled + +#define kdispReadAwakenChannelNumMask_HAL(pGpu, pKernelDisplay, arg0, arg1, arg2) kdispReadAwakenChannelNumMask(pGpu, pKernelDisplay, arg0, arg1, arg2) + +NV_STATUS kdispAllocateCommonHandle_IMPL(OBJGPU *pGpu, struct KernelDisplay *pKernelDisplay); + + +#ifdef __nvoc_kern_disp_h_disabled +static inline NV_STATUS kdispAllocateCommonHandle(OBJGPU *pGpu, struct KernelDisplay *pKernelDisplay) { + NV_ASSERT_FAILED_PRECOMP("KernelDisplay was disabled!"); + return NV_ERR_NOT_SUPPORTED; +} +#else //__nvoc_kern_disp_h_disabled +#define kdispAllocateCommonHandle(pGpu, pKernelDisplay) kdispAllocateCommonHandle_IMPL(pGpu, pKernelDisplay) +#endif //__nvoc_kern_disp_h_disabled + +#define kdispAllocateCommonHandle_HAL(pGpu, pKernelDisplay) kdispAllocateCommonHandle(pGpu, pKernelDisplay) + +void kdispDestroyCommonHandle_IMPL(struct KernelDisplay *pKernelDisplay); + + +#ifdef __nvoc_kern_disp_h_disabled +static inline void kdispDestroyCommonHandle(struct KernelDisplay *pKernelDisplay) { + NV_ASSERT_FAILED_PRECOMP("KernelDisplay was disabled!"); +} +#else //__nvoc_kern_disp_h_disabled +#define kdispDestroyCommonHandle(pKernelDisplay) kdispDestroyCommonHandle_IMPL(pKernelDisplay) +#endif //__nvoc_kern_disp_h_disabled + +#define kdispDestroyCommonHandle_HAL(pKernelDisplay) kdispDestroyCommonHandle(pKernelDisplay) + NV_STATUS kdispConstructEngine_IMPL(OBJGPU *pGpu, struct KernelDisplay *pKernelDisplay, ENGDESCRIPTOR engDesc); static inline NV_STATUS kdispConstructEngine_DISPATCH(OBJGPU *pGpu, struct KernelDisplay *pKernelDisplay, ENGDESCRIPTOR engDesc) { @@ -506,14 +604,14 @@ return pKernelDisplay->__kdispStateUnload__(pGpu, pKernelDisplay, flags); } -void kdispRegisterIntrService_IMPL(OBJGPU *pGpu, struct KernelDisplay *pKernelDisplay, IntrServiceRecord pRecords[163]); +void kdispRegisterIntrService_IMPL(OBJGPU *pGpu, struct KernelDisplay *pKernelDisplay, IntrServiceRecord pRecords[167]); -static inline void kdispRegisterIntrService_DISPATCH(OBJGPU *pGpu, struct KernelDisplay *pKernelDisplay, IntrServiceRecord pRecords[163]) { +static inline void kdispRegisterIntrService_DISPATCH(OBJGPU *pGpu, struct KernelDisplay *pKernelDisplay, IntrServiceRecord pRecords[167]) { pKernelDisplay->__kdispRegisterIntrService__(pGpu, pKernelDisplay, pRecords); } -static inline NvU32 kdispServiceInterrupt_d3ef2b(OBJGPU *pGpu, struct KernelDisplay *pKernelDisplay, IntrServiceServiceInterruptArguments *pParams) { - kdispServiceVblank(pGpu, pKernelDisplay, 0, ((2) | (16)), ((void *)0)); +static inline NvU32 kdispServiceInterrupt_acff5e(OBJGPU *pGpu, struct KernelDisplay *pKernelDisplay, IntrServiceServiceInterruptArguments *pParams) { + kdispServiceVblank(pGpu, pKernelDisplay, 0, (4), ((void *)0)); return NV_OK; } @@ -623,8 +721,36 @@ pKernelDisplay->__kdispSetSwapBarrierLsrMinTime__(pGpu, pKernelDisplay, head, pOrigLsrMinTime, newLsrMinTime); } -static inline NV_STATUS kdispReconcileTunableState_DISPATCH(POBJGPU pGpu, struct KernelDisplay *pEngstate, void *pTunableState) { - return pEngstate->__kdispReconcileTunableState__(pGpu, pEngstate, pTunableState); +NV_STATUS kdispGetRgScanLock_v02_01(OBJGPU *pGpu, struct KernelDisplay *pKernelDisplay, NvU32 head0, OBJGPU *pPeerGpu, NvU32 head1, NvBool *pMasterScanLock, NvU32 *pMasterScanLockPin, NvBool *pSlaveScanLock, NvU32 *pSlaveScanLockPin); + +static inline NV_STATUS kdispGetRgScanLock_92bfc3(OBJGPU *pGpu, struct KernelDisplay *pKernelDisplay, NvU32 head0, OBJGPU *pPeerGpu, NvU32 head1, NvBool *pMasterScanLock, NvU32 *pMasterScanLockPin, NvBool *pSlaveScanLock, NvU32 *pSlaveScanLockPin) { + NV_ASSERT_PRECOMP(0); + return NV_ERR_NOT_SUPPORTED; +} + +static inline NV_STATUS kdispGetRgScanLock_DISPATCH(OBJGPU *pGpu, struct KernelDisplay *pKernelDisplay, NvU32 head0, OBJGPU *pPeerGpu, NvU32 head1, NvBool *pMasterScanLock, NvU32 *pMasterScanLockPin, NvBool *pSlaveScanLock, NvU32 *pSlaveScanLockPin) { + return pKernelDisplay->__kdispGetRgScanLock__(pGpu, pKernelDisplay, head0, pPeerGpu, head1, pMasterScanLock, pMasterScanLockPin, pSlaveScanLock, pSlaveScanLockPin); +} + +NV_STATUS kdispDetectSliLink_v04_00(struct KernelDisplay *pKernelDisplay, OBJGPU *pParentGpu, OBJGPU *pChildGpu, NvU32 ParentDrPort, NvU32 ChildDrPort); + +static inline NV_STATUS kdispDetectSliLink_92bfc3(struct KernelDisplay *pKernelDisplay, OBJGPU *pParentGpu, OBJGPU *pChildGpu, NvU32 ParentDrPort, NvU32 ChildDrPort) { + NV_ASSERT_PRECOMP(0); + return NV_ERR_NOT_SUPPORTED; +} + +static inline NV_STATUS kdispDetectSliLink_DISPATCH(struct KernelDisplay *pKernelDisplay, OBJGPU *pParentGpu, OBJGPU *pChildGpu, NvU32 ParentDrPort, NvU32 ChildDrPort) { + return pKernelDisplay->__kdispDetectSliLink__(pKernelDisplay, pParentGpu, pChildGpu, ParentDrPort, ChildDrPort); +} + +static inline void kdispInitRegistryOverrides_b3696a(OBJGPU *pGpu, struct KernelDisplay *pKernelDisplay) { + return; +} + +void kdispInitRegistryOverrides_IMPL(OBJGPU *pGpu, struct KernelDisplay *pKernelDisplay); + +static inline void kdispInitRegistryOverrides_DISPATCH(OBJGPU *pGpu, struct KernelDisplay *pKernelDisplay) { + pKernelDisplay->__kdispInitRegistryOverrides__(pGpu, pKernelDisplay); } static inline NV_STATUS kdispServiceNotificationInterrupt_DISPATCH(OBJGPU *pGpu, struct KernelDisplay *pIntrService, IntrServiceServiceNotificationInterruptArguments *pParams) { @@ -655,18 +781,6 @@ return pEngstate->__kdispStatePreInitUnlocked__(pGpu, pEngstate); } -static inline NV_STATUS kdispGetTunableState_DISPATCH(POBJGPU pGpu, struct KernelDisplay *pEngstate, void *pTunableState) { - return pEngstate->__kdispGetTunableState__(pGpu, pEngstate, pTunableState); -} - -static inline NV_STATUS kdispCompareTunableState_DISPATCH(POBJGPU pGpu, struct KernelDisplay *pEngstate, void *pTunables1, void *pTunables2) { - return pEngstate->__kdispCompareTunableState__(pGpu, pEngstate, pTunables1, pTunables2); -} - -static inline void kdispFreeTunableState_DISPATCH(POBJGPU pGpu, struct KernelDisplay *pEngstate, void *pTunableState) { - pEngstate->__kdispFreeTunableState__(pGpu, pEngstate, pTunableState); -} - static inline NvBool kdispClearInterrupt_DISPATCH(OBJGPU *pGpu, struct KernelDisplay *pIntrService, IntrServiceClearInterruptArguments *pParams) { return pIntrService->__kdispClearInterrupt__(pGpu, pIntrService, pParams); } @@ -675,14 +789,6 @@ return pEngstate->__kdispStatePostLoad__(pGpu, pEngstate, arg0); } -static inline NV_STATUS kdispAllocTunableState_DISPATCH(POBJGPU pGpu, struct KernelDisplay *pEngstate, void **ppTunableState) { - return pEngstate->__kdispAllocTunableState__(pGpu, pEngstate, ppTunableState); -} - -static inline NV_STATUS kdispSetTunableState_DISPATCH(POBJGPU pGpu, struct KernelDisplay *pEngstate, void *pTunableState) { - return pEngstate->__kdispSetTunableState__(pGpu, pEngstate, pTunableState); -} - static inline NvBool kdispIsPresent_DISPATCH(POBJGPU pGpu, struct KernelDisplay *pEngstate) { return pEngstate->__kdispIsPresent__(pGpu, pEngstate); } @@ -745,7 +851,7 @@ #undef PRIVATE_FIELD -void +void dispdeviceFillVgaSavedDisplayState( OBJGPU *pGpu, NvU64 vgaAddr, NvU8 vgaMemType, @@ -772,19 +878,44 @@ return pKernelDisplay->pKernelHead[head]; } -static NV_INLINE NvU32 +static NV_INLINE NvU32 kdispGetNumHeads(struct KernelDisplay *pKernelDisplay) { NV_ASSERT(pKernelDisplay != NULL); return pKernelDisplay->numHeads; } -static NV_INLINE NvU32 +static NV_INLINE NvU32 kdispGetIsPrimaryVga(struct KernelDisplay *pKernelDisplay) { NV_ASSERT(pKernelDisplay->pStaticInfo != NULL); return pKernelDisplay->pStaticInfo->bPrimaryVga; } + +static NV_INLINE NvU32 +kdispGetDeferredVblankHeadMask(struct KernelDisplay *pKernelDisplay) +{ + return pKernelDisplay->deferredVblankHeadMask; +} + +static NV_INLINE void +kdispSetDeferredVblankHeadMask(struct KernelDisplay *pKernelDisplay, NvU32 vblankHeadMask) +{ + pKernelDisplay->deferredVblankHeadMask = vblankHeadMask; +} + +static NV_INLINE NvHandle +kdispGetInternalClientHandle(struct KernelDisplay *pKernelDisplay) +{ + return pKernelDisplay->hInternalClient; +} + +static NV_INLINE NvHandle +kdispGetDispCommonHandle(struct KernelDisplay *pKernelDisplay) +{ + return pKernelDisplay->hDispCommonHandle; +} + #endif // KERN_DISP_H #ifdef __cplusplus diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/generated/g_kern_fsp_nvoc.c nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_kern_fsp_nvoc.c --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/generated/g_kern_fsp_nvoc.c 2023-10-25 20:27:04.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_kern_fsp_nvoc.c 2024-03-05 22:18:22.000000000 +0000 @@ -74,10 +74,6 @@ kfspStateDestroy(pGpu, (struct KernelFsp *)(((unsigned char *)pKernelFsp) - __nvoc_rtti_KernelFsp_OBJENGSTATE.offset)); } -static NV_STATUS __nvoc_thunk_OBJENGSTATE_kfspReconcileTunableState(POBJGPU pGpu, struct KernelFsp *pEngstate, void *pTunableState) { - return engstateReconcileTunableState(pGpu, (struct OBJENGSTATE *)(((unsigned char *)pEngstate) + __nvoc_rtti_KernelFsp_OBJENGSTATE.offset), pTunableState); -} - static NV_STATUS __nvoc_thunk_OBJENGSTATE_kfspStateLoad(POBJGPU pGpu, struct KernelFsp *pEngstate, NvU32 arg0) { return engstateStateLoad(pGpu, (struct OBJENGSTATE *)(((unsigned char *)pEngstate) + __nvoc_rtti_KernelFsp_OBJENGSTATE.offset), arg0); } @@ -118,30 +114,10 @@ return engstateStatePreInitUnlocked(pGpu, (struct OBJENGSTATE *)(((unsigned char *)pEngstate) + __nvoc_rtti_KernelFsp_OBJENGSTATE.offset)); } -static NV_STATUS __nvoc_thunk_OBJENGSTATE_kfspGetTunableState(POBJGPU pGpu, struct KernelFsp *pEngstate, void *pTunableState) { - return engstateGetTunableState(pGpu, (struct OBJENGSTATE *)(((unsigned char *)pEngstate) + __nvoc_rtti_KernelFsp_OBJENGSTATE.offset), pTunableState); -} - -static NV_STATUS __nvoc_thunk_OBJENGSTATE_kfspCompareTunableState(POBJGPU pGpu, struct KernelFsp *pEngstate, void *pTunables1, void *pTunables2) { - return engstateCompareTunableState(pGpu, (struct OBJENGSTATE *)(((unsigned char *)pEngstate) + __nvoc_rtti_KernelFsp_OBJENGSTATE.offset), pTunables1, pTunables2); -} - -static void __nvoc_thunk_OBJENGSTATE_kfspFreeTunableState(POBJGPU pGpu, struct KernelFsp *pEngstate, void *pTunableState) { - engstateFreeTunableState(pGpu, (struct OBJENGSTATE *)(((unsigned char *)pEngstate) + __nvoc_rtti_KernelFsp_OBJENGSTATE.offset), pTunableState); -} - static NV_STATUS __nvoc_thunk_OBJENGSTATE_kfspStatePostLoad(POBJGPU pGpu, struct KernelFsp *pEngstate, NvU32 arg0) { return engstateStatePostLoad(pGpu, (struct OBJENGSTATE *)(((unsigned char *)pEngstate) + __nvoc_rtti_KernelFsp_OBJENGSTATE.offset), arg0); } -static NV_STATUS __nvoc_thunk_OBJENGSTATE_kfspAllocTunableState(POBJGPU pGpu, struct KernelFsp *pEngstate, void **ppTunableState) { - return engstateAllocTunableState(pGpu, (struct OBJENGSTATE *)(((unsigned char *)pEngstate) + __nvoc_rtti_KernelFsp_OBJENGSTATE.offset), ppTunableState); -} - -static NV_STATUS __nvoc_thunk_OBJENGSTATE_kfspSetTunableState(POBJGPU pGpu, struct KernelFsp *pEngstate, void *pTunableState) { - return engstateSetTunableState(pGpu, (struct OBJENGSTATE *)(((unsigned char *)pEngstate) + __nvoc_rtti_KernelFsp_OBJENGSTATE.offset), pTunableState); -} - static NvBool __nvoc_thunk_OBJENGSTATE_kfspIsPresent(POBJGPU pGpu, struct KernelFsp *pEngstate) { return engstateIsPresent(pGpu, (struct OBJENGSTATE *)(((unsigned char *)pEngstate) + __nvoc_rtti_KernelFsp_OBJENGSTATE.offset)); } @@ -248,7 +224,7 @@ { pThis->__kfspSendBootCommands__ = &kfspSendBootCommands_GH100; } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x01f0ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 */ + else { pThis->__kfspSendBootCommands__ = &kfspSendBootCommands_ac1694; } @@ -258,7 +234,7 @@ { pThis->__kfspWaitForSecureBoot__ = &kfspWaitForSecureBoot_GH100; } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x01f0ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 */ + else { pThis->__kfspWaitForSecureBoot__ = &kfspWaitForSecureBoot_395e98; } @@ -268,7 +244,7 @@ { pThis->__kfspGetRmChannelSize__ = &kfspGetRmChannelSize_GH100; } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x01f0ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 */ + else { pThis->__kfspGetRmChannelSize__ = &kfspGetRmChannelSize_b2b553; } @@ -278,7 +254,7 @@ { pThis->__kfspConfigEmemc__ = &kfspConfigEmemc_GH100; } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x01f0ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 */ + else { pThis->__kfspConfigEmemc__ = &kfspConfigEmemc_395e98; } @@ -288,7 +264,7 @@ { pThis->__kfspUpdateQueueHeadTail__ = &kfspUpdateQueueHeadTail_GH100; } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x01f0ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 */ + else { pThis->__kfspUpdateQueueHeadTail__ = &kfspUpdateQueueHeadTail_d44104; } @@ -298,7 +274,7 @@ { pThis->__kfspGetQueueHeadTail__ = &kfspGetQueueHeadTail_GH100; } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x01f0ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 */ + else { pThis->__kfspGetQueueHeadTail__ = &kfspGetQueueHeadTail_d44104; } @@ -308,7 +284,7 @@ { pThis->__kfspUpdateMsgQueueHeadTail__ = &kfspUpdateMsgQueueHeadTail_GH100; } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x01f0ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 */ + else { pThis->__kfspUpdateMsgQueueHeadTail__ = &kfspUpdateMsgQueueHeadTail_d44104; } @@ -318,7 +294,7 @@ { pThis->__kfspGetMsgQueueHeadTail__ = &kfspGetMsgQueueHeadTail_GH100; } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x01f0ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 */ + else { pThis->__kfspGetMsgQueueHeadTail__ = &kfspGetMsgQueueHeadTail_d44104; } @@ -328,7 +304,7 @@ { pThis->__kfspNvdmToSeid__ = &kfspNvdmToSeid_GH100; } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x01f0ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 */ + else { pThis->__kfspNvdmToSeid__ = &kfspNvdmToSeid_b2b553; } @@ -338,7 +314,7 @@ { pThis->__kfspCreateMctpHeader__ = &kfspCreateMctpHeader_GH100; } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x01f0ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 */ + else { pThis->__kfspCreateMctpHeader__ = &kfspCreateMctpHeader_b2b553; } @@ -348,7 +324,7 @@ { pThis->__kfspCreateNvdmHeader__ = &kfspCreateNvdmHeader_GH100; } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x01f0ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 */ + else { pThis->__kfspCreateNvdmHeader__ = &kfspCreateNvdmHeader_b2b553; } @@ -358,7 +334,7 @@ { pThis->__kfspWriteToEmem__ = &kfspWriteToEmem_GH100; } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x01f0ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 */ + else { pThis->__kfspWriteToEmem__ = &kfspWriteToEmem_395e98; } @@ -368,7 +344,7 @@ { pThis->__kfspReadFromEmem__ = &kfspReadFromEmem_GH100; } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x01f0ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 */ + else { pThis->__kfspReadFromEmem__ = &kfspReadFromEmem_395e98; } @@ -378,7 +354,7 @@ { pThis->__kfspGetPacketInfo__ = &kfspGetPacketInfo_GH100; } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x01f0ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 */ + else { pThis->__kfspGetPacketInfo__ = &kfspGetPacketInfo_395e98; } @@ -388,7 +364,7 @@ { pThis->__kfspValidateMctpPayloadHeader__ = &kfspValidateMctpPayloadHeader_GH100; } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x01f0ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 */ + else { pThis->__kfspValidateMctpPayloadHeader__ = &kfspValidateMctpPayloadHeader_395e98; } @@ -398,7 +374,7 @@ { pThis->__kfspProcessNvdmMessage__ = &kfspProcessNvdmMessage_GH100; } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x01f0ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 */ + else { pThis->__kfspProcessNvdmMessage__ = &kfspProcessNvdmMessage_395e98; } @@ -408,7 +384,7 @@ { pThis->__kfspProcessCommandResponse__ = &kfspProcessCommandResponse_GH100; } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x01f0ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 */ + else { pThis->__kfspProcessCommandResponse__ = &kfspProcessCommandResponse_395e98; } @@ -418,7 +394,7 @@ { pThis->__kfspDumpDebugState__ = &kfspDumpDebugState_GH100; } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x01f0ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 */ + else { pThis->__kfspDumpDebugState__ = &kfspDumpDebugState_d44104; } @@ -428,7 +404,7 @@ { pThis->__kfspErrorCode2NvStatusMap__ = &kfspErrorCode2NvStatusMap_GH100; } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x01f0ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 */ + else { pThis->__kfspErrorCode2NvStatusMap__ = &kfspErrorCode2NvStatusMap_395e98; } @@ -455,6 +431,16 @@ pThis->__kfspCheckGspSecureScratch__ = &kfspCheckGspSecureScratch_491d52; } + // Hal function -- kfspWaitForGspTargetMaskReleased + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ + { + pThis->__kfspWaitForGspTargetMaskReleased__ = &kfspWaitForGspTargetMaskReleased_GH100; + } + else + { + pThis->__kfspWaitForGspTargetMaskReleased__ = &kfspWaitForGspTargetMaskReleased_395e98; + } + // Hal function -- kfspRequiresBug3957833WAR if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ { @@ -470,8 +456,6 @@ pThis->__nvoc_base_OBJENGSTATE.__engstateStateDestroy__ = &__nvoc_thunk_KernelFsp_engstateStateDestroy; - pThis->__kfspReconcileTunableState__ = &__nvoc_thunk_OBJENGSTATE_kfspReconcileTunableState; - pThis->__kfspStateLoad__ = &__nvoc_thunk_OBJENGSTATE_kfspStateLoad; pThis->__kfspStateUnload__ = &__nvoc_thunk_OBJENGSTATE_kfspStateUnload; @@ -492,18 +476,8 @@ pThis->__kfspStatePreInitUnlocked__ = &__nvoc_thunk_OBJENGSTATE_kfspStatePreInitUnlocked; - pThis->__kfspGetTunableState__ = &__nvoc_thunk_OBJENGSTATE_kfspGetTunableState; - - pThis->__kfspCompareTunableState__ = &__nvoc_thunk_OBJENGSTATE_kfspCompareTunableState; - - pThis->__kfspFreeTunableState__ = &__nvoc_thunk_OBJENGSTATE_kfspFreeTunableState; - pThis->__kfspStatePostLoad__ = &__nvoc_thunk_OBJENGSTATE_kfspStatePostLoad; - pThis->__kfspAllocTunableState__ = &__nvoc_thunk_OBJENGSTATE_kfspAllocTunableState; - - pThis->__kfspSetTunableState__ = &__nvoc_thunk_OBJENGSTATE_kfspSetTunableState; - pThis->__kfspIsPresent__ = &__nvoc_thunk_OBJENGSTATE_kfspIsPresent; } @@ -526,13 +500,16 @@ KernelFsp *pThis; RmHalspecOwner *pRmhalspecowner; - pThis = portMemAllocNonPaged(sizeof(KernelFsp)); - if (pThis == NULL) return NV_ERR_NO_MEMORY; + status = __nvoc_handleObjCreateMemAlloc(createFlags, sizeof(KernelFsp), (void**)&pThis, (void**)ppThis); + if (status != NV_OK) + return status; portMemSet(pThis, 0, sizeof(KernelFsp)); __nvoc_initRtti(staticCast(pThis, Dynamic), &__nvoc_class_def_KernelFsp); + pThis->__nvoc_base_OBJENGSTATE.__nvoc_base_Object.createFlags = createFlags; + if (pParent != NULL && !(createFlags & NVOC_OBJ_CREATE_FLAGS_PARENT_HALSPEC_ONLY)) { pParentObj = dynamicCast(pParent, Object); @@ -552,11 +529,17 @@ if (status != NV_OK) goto __nvoc_objCreate_KernelFsp_cleanup; *ppThis = pThis; + return NV_OK; __nvoc_objCreate_KernelFsp_cleanup: // do not call destructors here since the constructor already called them - portMemFree(pThis); + if (createFlags & NVOC_OBJ_CREATE_FLAGS_IN_PLACE_CONSTRUCT) + portMemSet(pThis, 0, sizeof(KernelFsp)); + else + portMemFree(pThis); + + // coverity[leaked_storage:FALSE] return status; } diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/generated/g_kern_fsp_nvoc.h nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_kern_fsp_nvoc.h --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/generated/g_kern_fsp_nvoc.h 2023-10-25 20:27:04.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_kern_fsp_nvoc.h 2024-03-05 22:18:22.000000000 +0000 @@ -40,12 +40,6 @@ #include "kernel/gpu/intr/intr_service.h" #include "fsp/nvdm_payload_cmd_response.h" -#if RMCFG_MODULE_ENABLED (FSP) -#include "gpu/falcon/falcon.h" -#include "gpu/falcon/falcon_queue.h" -#include "objflcnable.h" -#endif - // // VBIOS ucode descriptor v4 format. Used for the CPU command to FSP to boot // GSP FMC. @@ -153,7 +147,7 @@ void (*__kfspGetQueueHeadTail__)(struct OBJGPU *, struct KernelFsp *, NvU32 *, NvU32 *); void (*__kfspUpdateMsgQueueHeadTail__)(struct OBJGPU *, struct KernelFsp *, NvU32, NvU32); void (*__kfspGetMsgQueueHeadTail__)(struct OBJGPU *, struct KernelFsp *, NvU32 *, NvU32 *); - NvU8 (*__kfspNvdmToSeid__)(POBJGPU, struct KernelFsp *, NvU8); + NvU8 (*__kfspNvdmToSeid__)(struct OBJGPU *, struct KernelFsp *, NvU8); NvU32 (*__kfspCreateMctpHeader__)(struct OBJGPU *, struct KernelFsp *, NvU8, NvU8, NvU8, NvU8); NvU32 (*__kfspCreateNvdmHeader__)(struct OBJGPU *, struct KernelFsp *, NvU32); NV_STATUS (*__kfspWriteToEmem__)(struct OBJGPU *, struct KernelFsp *, NvU8 *, NvU32); @@ -166,8 +160,8 @@ NV_STATUS (*__kfspErrorCode2NvStatusMap__)(struct OBJGPU *, struct KernelFsp *, NvU32); NvU64 (*__kfspGetExtraReservedMemorySize__)(struct OBJGPU *, struct KernelFsp *); NvBool (*__kfspCheckGspSecureScratch__)(struct OBJGPU *, struct KernelFsp *); + NV_STATUS (*__kfspWaitForGspTargetMaskReleased__)(struct OBJGPU *, struct KernelFsp *); NvBool (*__kfspRequiresBug3957833WAR__)(struct OBJGPU *, struct KernelFsp *); - NV_STATUS (*__kfspReconcileTunableState__)(POBJGPU, struct KernelFsp *, void *); NV_STATUS (*__kfspStateLoad__)(POBJGPU, struct KernelFsp *, NvU32); NV_STATUS (*__kfspStateUnload__)(POBJGPU, struct KernelFsp *, NvU32); NV_STATUS (*__kfspStateInitLocked__)(POBJGPU, struct KernelFsp *); @@ -178,19 +172,13 @@ void (*__kfspInitMissing__)(POBJGPU, struct KernelFsp *); NV_STATUS (*__kfspStatePreInitLocked__)(POBJGPU, struct KernelFsp *); NV_STATUS (*__kfspStatePreInitUnlocked__)(POBJGPU, struct KernelFsp *); - NV_STATUS (*__kfspGetTunableState__)(POBJGPU, struct KernelFsp *, void *); - NV_STATUS (*__kfspCompareTunableState__)(POBJGPU, struct KernelFsp *, void *, void *); - void (*__kfspFreeTunableState__)(POBJGPU, struct KernelFsp *, void *); NV_STATUS (*__kfspStatePostLoad__)(POBJGPU, struct KernelFsp *, NvU32); - NV_STATUS (*__kfspAllocTunableState__)(POBJGPU, struct KernelFsp *, void **); - NV_STATUS (*__kfspSetTunableState__)(POBJGPU, struct KernelFsp *, void *); NvBool (*__kfspIsPresent__)(POBJGPU, struct KernelFsp *); NvBool PDB_PROP_KFSP_BOOT_COMMAND_OK; NvBool PDB_PROP_KFSP_GSP_MODE_GSPRM; NvBool PDB_PROP_KFSP_DISABLE_FRTS_SYSMEM; NvBool PDB_PROP_KFSP_DISABLE_FRTS_VIDMEM; NvBool PDB_PROP_KFSP_DISABLE_GSPFMC; - NvBool PDB_PROP_KFSP_HULK_EXECUTED; MEMORY_DESCRIPTOR *pSysmemFrtsMemdesc; MEMORY_DESCRIPTOR *pVidmemFrtsMemdesc; MEMORY_DESCRIPTOR *pGspFmcMemdesc; @@ -228,8 +216,6 @@ #define PDB_PROP_KFSP_IS_MISSING_BASE_NAME PDB_PROP_ENGSTATE_IS_MISSING #define PDB_PROP_KFSP_GSP_MODE_GSPRM_BASE_CAST #define PDB_PROP_KFSP_GSP_MODE_GSPRM_BASE_NAME PDB_PROP_KFSP_GSP_MODE_GSPRM -#define PDB_PROP_KFSP_HULK_EXECUTED_BASE_CAST -#define PDB_PROP_KFSP_HULK_EXECUTED_BASE_NAME PDB_PROP_KFSP_HULK_EXECUTED #define PDB_PROP_KFSP_BOOT_COMMAND_OK_BASE_CAST #define PDB_PROP_KFSP_BOOT_COMMAND_OK_BASE_NAME PDB_PROP_KFSP_BOOT_COMMAND_OK #define PDB_PROP_KFSP_DISABLE_FRTS_SYSMEM_BASE_CAST @@ -294,9 +280,10 @@ #define kfspGetExtraReservedMemorySize_HAL(pGpu, pKernelFsp) kfspGetExtraReservedMemorySize_DISPATCH(pGpu, pKernelFsp) #define kfspCheckGspSecureScratch(pGpu, pKernelFsp) kfspCheckGspSecureScratch_DISPATCH(pGpu, pKernelFsp) #define kfspCheckGspSecureScratch_HAL(pGpu, pKernelFsp) kfspCheckGspSecureScratch_DISPATCH(pGpu, pKernelFsp) +#define kfspWaitForGspTargetMaskReleased(pGpu, pKernelFsp) kfspWaitForGspTargetMaskReleased_DISPATCH(pGpu, pKernelFsp) +#define kfspWaitForGspTargetMaskReleased_HAL(pGpu, pKernelFsp) kfspWaitForGspTargetMaskReleased_DISPATCH(pGpu, pKernelFsp) #define kfspRequiresBug3957833WAR(pGpu, pKernelFsp) kfspRequiresBug3957833WAR_DISPATCH(pGpu, pKernelFsp) #define kfspRequiresBug3957833WAR_HAL(pGpu, pKernelFsp) kfspRequiresBug3957833WAR_DISPATCH(pGpu, pKernelFsp) -#define kfspReconcileTunableState(pGpu, pEngstate, pTunableState) kfspReconcileTunableState_DISPATCH(pGpu, pEngstate, pTunableState) #define kfspStateLoad(pGpu, pEngstate, arg0) kfspStateLoad_DISPATCH(pGpu, pEngstate, arg0) #define kfspStateUnload(pGpu, pEngstate, arg0) kfspStateUnload_DISPATCH(pGpu, pEngstate, arg0) #define kfspStateInitLocked(pGpu, pEngstate) kfspStateInitLocked_DISPATCH(pGpu, pEngstate) @@ -307,12 +294,7 @@ #define kfspInitMissing(pGpu, pEngstate) kfspInitMissing_DISPATCH(pGpu, pEngstate) #define kfspStatePreInitLocked(pGpu, pEngstate) kfspStatePreInitLocked_DISPATCH(pGpu, pEngstate) #define kfspStatePreInitUnlocked(pGpu, pEngstate) kfspStatePreInitUnlocked_DISPATCH(pGpu, pEngstate) -#define kfspGetTunableState(pGpu, pEngstate, pTunableState) kfspGetTunableState_DISPATCH(pGpu, pEngstate, pTunableState) -#define kfspCompareTunableState(pGpu, pEngstate, pTunables1, pTunables2) kfspCompareTunableState_DISPATCH(pGpu, pEngstate, pTunables1, pTunables2) -#define kfspFreeTunableState(pGpu, pEngstate, pTunableState) kfspFreeTunableState_DISPATCH(pGpu, pEngstate, pTunableState) #define kfspStatePostLoad(pGpu, pEngstate, arg0) kfspStatePostLoad_DISPATCH(pGpu, pEngstate, arg0) -#define kfspAllocTunableState(pGpu, pEngstate, ppTunableState) kfspAllocTunableState_DISPATCH(pGpu, pEngstate, ppTunableState) -#define kfspSetTunableState(pGpu, pEngstate, pTunableState) kfspSetTunableState_DISPATCH(pGpu, pEngstate, pTunableState) #define kfspIsPresent(pGpu, pEngstate) kfspIsPresent_DISPATCH(pGpu, pEngstate) NV_STATUS kfspConstructEngine_IMPL(struct OBJGPU *pGpu, struct KernelFsp *pKernelFsp, ENGDESCRIPTOR arg0); @@ -458,13 +440,13 @@ pKernelFsp->__kfspGetMsgQueueHeadTail__(pGpu, pKernelFsp, pMsgqHead, pMsgqTail); } -NvU8 kfspNvdmToSeid_GH100(POBJGPU pGpu, struct KernelFsp *pKernelFsp, NvU8 nvdmType); +NvU8 kfspNvdmToSeid_GH100(struct OBJGPU *pGpu, struct KernelFsp *pKernelFsp, NvU8 nvdmType); -static inline NvU8 kfspNvdmToSeid_b2b553(POBJGPU pGpu, struct KernelFsp *pKernelFsp, NvU8 nvdmType) { +static inline NvU8 kfspNvdmToSeid_b2b553(struct OBJGPU *pGpu, struct KernelFsp *pKernelFsp, NvU8 nvdmType) { return 0; } -static inline NvU8 kfspNvdmToSeid_DISPATCH(POBJGPU pGpu, struct KernelFsp *pKernelFsp, NvU8 nvdmType) { +static inline NvU8 kfspNvdmToSeid_DISPATCH(struct OBJGPU *pGpu, struct KernelFsp *pKernelFsp, NvU8 nvdmType) { return pKernelFsp->__kfspNvdmToSeid__(pGpu, pKernelFsp, nvdmType); } @@ -588,6 +570,16 @@ return pKernelFsp->__kfspCheckGspSecureScratch__(pGpu, pKernelFsp); } +NV_STATUS kfspWaitForGspTargetMaskReleased_GH100(struct OBJGPU *pGpu, struct KernelFsp *pKernelFsp); + +static inline NV_STATUS kfspWaitForGspTargetMaskReleased_395e98(struct OBJGPU *pGpu, struct KernelFsp *pKernelFsp) { + return NV_ERR_NOT_SUPPORTED; +} + +static inline NV_STATUS kfspWaitForGspTargetMaskReleased_DISPATCH(struct OBJGPU *pGpu, struct KernelFsp *pKernelFsp) { + return pKernelFsp->__kfspWaitForGspTargetMaskReleased__(pGpu, pKernelFsp); +} + NvBool kfspRequiresBug3957833WAR_GH100(struct OBJGPU *pGpu, struct KernelFsp *pKernelFsp); static inline NvBool kfspRequiresBug3957833WAR_491d52(struct OBJGPU *pGpu, struct KernelFsp *pKernelFsp) { @@ -598,10 +590,6 @@ return pKernelFsp->__kfspRequiresBug3957833WAR__(pGpu, pKernelFsp); } -static inline NV_STATUS kfspReconcileTunableState_DISPATCH(POBJGPU pGpu, struct KernelFsp *pEngstate, void *pTunableState) { - return pEngstate->__kfspReconcileTunableState__(pGpu, pEngstate, pTunableState); -} - static inline NV_STATUS kfspStateLoad_DISPATCH(POBJGPU pGpu, struct KernelFsp *pEngstate, NvU32 arg0) { return pEngstate->__kfspStateLoad__(pGpu, pEngstate, arg0); } @@ -642,30 +630,10 @@ return pEngstate->__kfspStatePreInitUnlocked__(pGpu, pEngstate); } -static inline NV_STATUS kfspGetTunableState_DISPATCH(POBJGPU pGpu, struct KernelFsp *pEngstate, void *pTunableState) { - return pEngstate->__kfspGetTunableState__(pGpu, pEngstate, pTunableState); -} - -static inline NV_STATUS kfspCompareTunableState_DISPATCH(POBJGPU pGpu, struct KernelFsp *pEngstate, void *pTunables1, void *pTunables2) { - return pEngstate->__kfspCompareTunableState__(pGpu, pEngstate, pTunables1, pTunables2); -} - -static inline void kfspFreeTunableState_DISPATCH(POBJGPU pGpu, struct KernelFsp *pEngstate, void *pTunableState) { - pEngstate->__kfspFreeTunableState__(pGpu, pEngstate, pTunableState); -} - static inline NV_STATUS kfspStatePostLoad_DISPATCH(POBJGPU pGpu, struct KernelFsp *pEngstate, NvU32 arg0) { return pEngstate->__kfspStatePostLoad__(pGpu, pEngstate, arg0); } -static inline NV_STATUS kfspAllocTunableState_DISPATCH(POBJGPU pGpu, struct KernelFsp *pEngstate, void **ppTunableState) { - return pEngstate->__kfspAllocTunableState__(pGpu, pEngstate, ppTunableState); -} - -static inline NV_STATUS kfspSetTunableState_DISPATCH(POBJGPU pGpu, struct KernelFsp *pEngstate, void *pTunableState) { - return pEngstate->__kfspSetTunableState__(pGpu, pEngstate, pTunableState); -} - static inline NvBool kfspIsPresent_DISPATCH(POBJGPU pGpu, struct KernelFsp *pEngstate) { return pEngstate->__kfspIsPresent__(pGpu, pEngstate); } diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/generated/g_kern_gmmu_nvoc.c nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_kern_gmmu_nvoc.c --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/generated/g_kern_gmmu_nvoc.c 2023-10-25 20:27:04.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_kern_gmmu_nvoc.c 2024-03-05 22:18:22.000000000 +0000 @@ -95,7 +95,7 @@ kgmmuStateDestroy(pGpu, (struct KernelGmmu *)(((unsigned char *)pKernelGmmu) - __nvoc_rtti_KernelGmmu_OBJENGSTATE.offset)); } -static void __nvoc_thunk_KernelGmmu_intrservRegisterIntrService(OBJGPU *pGpu, struct IntrService *pKernelGmmu, IntrServiceRecord arg0[163]) { +static void __nvoc_thunk_KernelGmmu_intrservRegisterIntrService(OBJGPU *pGpu, struct IntrService *pKernelGmmu, IntrServiceRecord arg0[167]) { kgmmuRegisterIntrService(pGpu, (struct KernelGmmu *)(((unsigned char *)pKernelGmmu) - __nvoc_rtti_KernelGmmu_IntrService.offset), arg0); } @@ -103,10 +103,6 @@ return kgmmuServiceInterrupt(pGpu, (struct KernelGmmu *)(((unsigned char *)pKernelGmmu) - __nvoc_rtti_KernelGmmu_IntrService.offset), pParams); } -static NV_STATUS __nvoc_thunk_OBJENGSTATE_kgmmuReconcileTunableState(POBJGPU pGpu, struct KernelGmmu *pEngstate, void *pTunableState) { - return engstateReconcileTunableState(pGpu, (struct OBJENGSTATE *)(((unsigned char *)pEngstate) + __nvoc_rtti_KernelGmmu_OBJENGSTATE.offset), pTunableState); -} - static NV_STATUS __nvoc_thunk_OBJENGSTATE_kgmmuStateLoad(POBJGPU pGpu, struct KernelGmmu *pEngstate, NvU32 arg0) { return engstateStateLoad(pGpu, (struct OBJENGSTATE *)(((unsigned char *)pEngstate) + __nvoc_rtti_KernelGmmu_OBJENGSTATE.offset), arg0); } @@ -143,30 +139,10 @@ return engstateStatePreInitUnlocked(pGpu, (struct OBJENGSTATE *)(((unsigned char *)pEngstate) + __nvoc_rtti_KernelGmmu_OBJENGSTATE.offset)); } -static NV_STATUS __nvoc_thunk_OBJENGSTATE_kgmmuGetTunableState(POBJGPU pGpu, struct KernelGmmu *pEngstate, void *pTunableState) { - return engstateGetTunableState(pGpu, (struct OBJENGSTATE *)(((unsigned char *)pEngstate) + __nvoc_rtti_KernelGmmu_OBJENGSTATE.offset), pTunableState); -} - -static NV_STATUS __nvoc_thunk_OBJENGSTATE_kgmmuCompareTunableState(POBJGPU pGpu, struct KernelGmmu *pEngstate, void *pTunables1, void *pTunables2) { - return engstateCompareTunableState(pGpu, (struct OBJENGSTATE *)(((unsigned char *)pEngstate) + __nvoc_rtti_KernelGmmu_OBJENGSTATE.offset), pTunables1, pTunables2); -} - -static void __nvoc_thunk_OBJENGSTATE_kgmmuFreeTunableState(POBJGPU pGpu, struct KernelGmmu *pEngstate, void *pTunableState) { - engstateFreeTunableState(pGpu, (struct OBJENGSTATE *)(((unsigned char *)pEngstate) + __nvoc_rtti_KernelGmmu_OBJENGSTATE.offset), pTunableState); -} - static NvBool __nvoc_thunk_IntrService_kgmmuClearInterrupt(struct OBJGPU *pGpu, struct KernelGmmu *pIntrService, IntrServiceClearInterruptArguments *pParams) { return intrservClearInterrupt(pGpu, (struct IntrService *)(((unsigned char *)pIntrService) + __nvoc_rtti_KernelGmmu_IntrService.offset), pParams); } -static NV_STATUS __nvoc_thunk_OBJENGSTATE_kgmmuAllocTunableState(POBJGPU pGpu, struct KernelGmmu *pEngstate, void **ppTunableState) { - return engstateAllocTunableState(pGpu, (struct OBJENGSTATE *)(((unsigned char *)pEngstate) + __nvoc_rtti_KernelGmmu_OBJENGSTATE.offset), ppTunableState); -} - -static NV_STATUS __nvoc_thunk_OBJENGSTATE_kgmmuSetTunableState(POBJGPU pGpu, struct KernelGmmu *pEngstate, void *pTunableState) { - return engstateSetTunableState(pGpu, (struct OBJENGSTATE *)(((unsigned char *)pEngstate) + __nvoc_rtti_KernelGmmu_OBJENGSTATE.offset), pTunableState); -} - static NvBool __nvoc_thunk_OBJENGSTATE_kgmmuIsPresent(POBJGPU pGpu, struct KernelGmmu *pEngstate) { return engstateIsPresent(pGpu, (struct OBJENGSTATE *)(((unsigned char *)pEngstate) + __nvoc_rtti_KernelGmmu_OBJENGSTATE.offset)); } @@ -281,16 +257,10 @@ pThis->__kgmmuStateInitLocked__ = &kgmmuStateInitLocked_IMPL; // Hal function -- kgmmuStatePostLoad - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x11f0ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 | GH100 */ - { - pThis->__kgmmuStatePostLoad__ = &kgmmuStatePostLoad_IMPL; - } + pThis->__kgmmuStatePostLoad__ = &kgmmuStatePostLoad_IMPL; // Hal function -- kgmmuStatePreUnload - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x11f0ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 | GH100 */ - { - pThis->__kgmmuStatePreUnload__ = &kgmmuStatePreUnload_IMPL; - } + pThis->__kgmmuStatePreUnload__ = &kgmmuStatePreUnload_IMPL; pThis->__kgmmuStateDestroy__ = &kgmmuStateDestroy_IMPL; @@ -303,7 +273,7 @@ { pThis->__kgmmuInstBlkVaLimitGet__ = &kgmmuInstBlkVaLimitGet_GV100; } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x11f0fc00UL) )) /* ChipHal: GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 | GH100 */ + else { pThis->__kgmmuInstBlkVaLimitGet__ = &kgmmuInstBlkVaLimitGet_f03539; } @@ -313,103 +283,103 @@ { pThis->__kgmmuSetTlbInvalidateMembarWarParameters__ = &kgmmuSetTlbInvalidateMembarWarParameters_TU102; } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x11f0fc00UL) )) /* ChipHal: GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 | GH100 */ + else { pThis->__kgmmuSetTlbInvalidateMembarWarParameters__ = &kgmmuSetTlbInvalidateMembarWarParameters_4a4dee; } // Hal function -- kgmmuSetTlbInvalidationScope - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x11f0fc00UL) )) /* ChipHal: GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 | GH100 */ + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x000003e0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 */ { - pThis->__kgmmuSetTlbInvalidationScope__ = &kgmmuSetTlbInvalidationScope_GA100; + pThis->__kgmmuSetTlbInvalidationScope__ = &kgmmuSetTlbInvalidationScope_46f6a7; } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x000003e0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 */ + else { - pThis->__kgmmuSetTlbInvalidationScope__ = &kgmmuSetTlbInvalidationScope_46f6a7; + pThis->__kgmmuSetTlbInvalidationScope__ = &kgmmuSetTlbInvalidationScope_GA100; } // Hal function -- kgmmuFmtInitPteComptagLine - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x01f0ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 */ + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ { - pThis->__kgmmuFmtInitPteComptagLine__ = &kgmmuFmtInitPteComptagLine_TU10X; + pThis->__kgmmuFmtInitPteComptagLine__ = &kgmmuFmtInitPteComptagLine_b3696a; } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ + else { - pThis->__kgmmuFmtInitPteComptagLine__ = &kgmmuFmtInitPteComptagLine_b3696a; + pThis->__kgmmuFmtInitPteComptagLine__ = &kgmmuFmtInitPteComptagLine_TU10X; } // Hal function -- kgmmuFmtInitPeerPteFld - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x01f0ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 */ + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ { - pThis->__kgmmuFmtInitPeerPteFld__ = &kgmmuFmtInitPeerPteFld_TU10X; + pThis->__kgmmuFmtInitPeerPteFld__ = &kgmmuFmtInitPeerPteFld_b3696a; } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ + else { - pThis->__kgmmuFmtInitPeerPteFld__ = &kgmmuFmtInitPeerPteFld_b3696a; + pThis->__kgmmuFmtInitPeerPteFld__ = &kgmmuFmtInitPeerPteFld_TU10X; } // Hal function -- kgmmuFmtInitPte - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x01f0ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 */ + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ { - pThis->__kgmmuFmtInitPte__ = &kgmmuFmtInitPte_GP10X; + pThis->__kgmmuFmtInitPte__ = &kgmmuFmtInitPte_GH10X; } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ + else { - pThis->__kgmmuFmtInitPte__ = &kgmmuFmtInitPte_GH10X; + pThis->__kgmmuFmtInitPte__ = &kgmmuFmtInitPte_GP10X; } // Hal function -- kgmmuFmtInitPde - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x01f0ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 */ + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ { - pThis->__kgmmuFmtInitPde__ = &kgmmuFmtInitPde_GP10X; + pThis->__kgmmuFmtInitPde__ = &kgmmuFmtInitPde_GH10X; } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ + else { - pThis->__kgmmuFmtInitPde__ = &kgmmuFmtInitPde_GH10X; + pThis->__kgmmuFmtInitPde__ = &kgmmuFmtInitPde_GP10X; } // Hal function -- kgmmuFmtIsVersionSupported - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x01f0ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 */ + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ { - pThis->__kgmmuFmtIsVersionSupported__ = &kgmmuFmtIsVersionSupported_GP10X; + pThis->__kgmmuFmtIsVersionSupported__ = &kgmmuFmtIsVersionSupported_GH10X; } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ + else { - pThis->__kgmmuFmtIsVersionSupported__ = &kgmmuFmtIsVersionSupported_GH10X; + pThis->__kgmmuFmtIsVersionSupported__ = &kgmmuFmtIsVersionSupported_GP10X; } // Hal function -- kgmmuFmtInitLevels - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x000003e0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 */ + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ { - pThis->__kgmmuFmtInitLevels__ = &kgmmuFmtInitLevels_GP10X; + pThis->__kgmmuFmtInitLevels__ = &kgmmuFmtInitLevels_GH10X; } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x01f0fc00UL) )) /* ChipHal: GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 */ + else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x000003e0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 */ { - pThis->__kgmmuFmtInitLevels__ = &kgmmuFmtInitLevels_GA10X; + pThis->__kgmmuFmtInitLevels__ = &kgmmuFmtInitLevels_GP10X; } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ + else { - pThis->__kgmmuFmtInitLevels__ = &kgmmuFmtInitLevels_GH10X; + pThis->__kgmmuFmtInitLevels__ = &kgmmuFmtInitLevels_GA10X; } // Hal function -- kgmmuFmtInitPdeMulti - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x01f0ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 */ + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ { - pThis->__kgmmuFmtInitPdeMulti__ = &kgmmuFmtInitPdeMulti_GP10X; + pThis->__kgmmuFmtInitPdeMulti__ = &kgmmuFmtInitPdeMulti_GH10X; } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ + else { - pThis->__kgmmuFmtInitPdeMulti__ = &kgmmuFmtInitPdeMulti_GH10X; + pThis->__kgmmuFmtInitPdeMulti__ = &kgmmuFmtInitPdeMulti_GP10X; } // Hal function -- kgmmuFmtFamiliesInit - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x01f0ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 */ + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ { - pThis->__kgmmuFmtFamiliesInit__ = &kgmmuFmtFamiliesInit_TU102; + pThis->__kgmmuFmtFamiliesInit__ = &kgmmuFmtFamiliesInit_GH100; } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ + else { - pThis->__kgmmuFmtFamiliesInit__ = &kgmmuFmtFamiliesInit_GH100; + pThis->__kgmmuFmtFamiliesInit__ = &kgmmuFmtFamiliesInit_TU102; } // Hal function -- kgmmuTranslatePtePcfFromSw @@ -417,7 +387,7 @@ { pThis->__kgmmuTranslatePtePcfFromSw__ = &kgmmuTranslatePtePcfFromSw_GH100; } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x01f0ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 */ + else { pThis->__kgmmuTranslatePtePcfFromSw__ = &kgmmuTranslatePtePcfFromSw_56cd7a; } @@ -427,7 +397,7 @@ { pThis->__kgmmuTranslatePtePcfFromHw__ = &kgmmuTranslatePtePcfFromHw_GH100; } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x01f0ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 */ + else { pThis->__kgmmuTranslatePtePcfFromHw__ = &kgmmuTranslatePtePcfFromHw_56cd7a; } @@ -437,7 +407,7 @@ { pThis->__kgmmuTranslatePdePcfFromSw__ = &kgmmuTranslatePdePcfFromSw_GH100; } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x01f0ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 */ + else { pThis->__kgmmuTranslatePdePcfFromSw__ = &kgmmuTranslatePdePcfFromSw_56cd7a; } @@ -447,29 +417,91 @@ { pThis->__kgmmuTranslatePdePcfFromHw__ = &kgmmuTranslatePdePcfFromHw_GH100; } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x01f0ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 */ + else { pThis->__kgmmuTranslatePdePcfFromHw__ = &kgmmuTranslatePdePcfFromHw_56cd7a; } + // Hal function -- kgmmuGetFaultRegisterMappings + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ + { + pThis->__kgmmuGetFaultRegisterMappings__ = &kgmmuGetFaultRegisterMappings_GH100; + } + else + { + pThis->__kgmmuGetFaultRegisterMappings__ = &kgmmuGetFaultRegisterMappings_TU102; + } + + // Hal function -- kgmmuIssueReplayableFaultBufferFlush + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ + { + pThis->__kgmmuIssueReplayableFaultBufferFlush__ = &kgmmuIssueReplayableFaultBufferFlush_GH100; + } + else + { + pThis->__kgmmuIssueReplayableFaultBufferFlush__ = &kgmmuIssueReplayableFaultBufferFlush_46f6a7; + } + + // Hal function -- kgmmuFaultBufferAllocSharedMemory + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ + { + pThis->__kgmmuFaultBufferAllocSharedMemory__ = &kgmmuFaultBufferAllocSharedMemory_GH100; + } + else + { + pThis->__kgmmuFaultBufferAllocSharedMemory__ = &kgmmuFaultBufferAllocSharedMemory_56cd7a; + } + + // Hal function -- kgmmuFaultBufferFreeSharedMemory + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ + { + pThis->__kgmmuFaultBufferFreeSharedMemory__ = &kgmmuFaultBufferFreeSharedMemory_GH100; + } + else + { + pThis->__kgmmuFaultBufferFreeSharedMemory__ = &kgmmuFaultBufferFreeSharedMemory_b3696a; + } + // Hal function -- kgmmuSetupWarForBug2720120 if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x00000400UL) )) /* ChipHal: GA100 */ { pThis->__kgmmuSetupWarForBug2720120__ = &kgmmuSetupWarForBug2720120_GA100; } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x11f0fbe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 | GH100 */ + else { pThis->__kgmmuSetupWarForBug2720120__ = &kgmmuSetupWarForBug2720120_56cd7a; } // Hal function -- kgmmuGetGraphicsEngineId - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x01f0ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 */ + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ + { + pThis->__kgmmuGetGraphicsEngineId__ = &kgmmuGetGraphicsEngineId_GH100; + } + else { pThis->__kgmmuGetGraphicsEngineId__ = &kgmmuGetGraphicsEngineId_GV100; } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ + + // Hal function -- kgmmuReadShadowBufPutIndex + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ { - pThis->__kgmmuGetGraphicsEngineId__ = &kgmmuGetGraphicsEngineId_GH100; + pThis->__kgmmuReadShadowBufPutIndex__ = &kgmmuReadShadowBufPutIndex_GH100; + } + // default + else + { + pThis->__kgmmuReadShadowBufPutIndex__ = &kgmmuReadShadowBufPutIndex_4a4dee; + } + + // Hal function -- kgmmuGetEccCounts + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000420UL) )) /* ChipHal: TU102 | GA100 | GH100 */ + { + pThis->__kgmmuGetEccCounts__ = &kgmmuGetEccCounts_TU102; + } + // default + else + { + pThis->__kgmmuGetEccCounts__ = &kgmmuGetEccCounts_4a4dee; } pThis->__nvoc_base_OBJENGSTATE.__engstateConstructEngine__ = &__nvoc_thunk_KernelGmmu_engstateConstructEngine; @@ -486,8 +518,6 @@ pThis->__nvoc_base_IntrService.__intrservServiceInterrupt__ = &__nvoc_thunk_KernelGmmu_intrservServiceInterrupt; - pThis->__kgmmuReconcileTunableState__ = &__nvoc_thunk_OBJENGSTATE_kgmmuReconcileTunableState; - pThis->__kgmmuStateLoad__ = &__nvoc_thunk_OBJENGSTATE_kgmmuStateLoad; pThis->__kgmmuStateUnload__ = &__nvoc_thunk_OBJENGSTATE_kgmmuStateUnload; @@ -506,18 +536,8 @@ pThis->__kgmmuStatePreInitUnlocked__ = &__nvoc_thunk_OBJENGSTATE_kgmmuStatePreInitUnlocked; - pThis->__kgmmuGetTunableState__ = &__nvoc_thunk_OBJENGSTATE_kgmmuGetTunableState; - - pThis->__kgmmuCompareTunableState__ = &__nvoc_thunk_OBJENGSTATE_kgmmuCompareTunableState; - - pThis->__kgmmuFreeTunableState__ = &__nvoc_thunk_OBJENGSTATE_kgmmuFreeTunableState; - pThis->__kgmmuClearInterrupt__ = &__nvoc_thunk_IntrService_kgmmuClearInterrupt; - pThis->__kgmmuAllocTunableState__ = &__nvoc_thunk_OBJENGSTATE_kgmmuAllocTunableState; - - pThis->__kgmmuSetTunableState__ = &__nvoc_thunk_OBJENGSTATE_kgmmuSetTunableState; - pThis->__kgmmuIsPresent__ = &__nvoc_thunk_OBJENGSTATE_kgmmuIsPresent; } @@ -543,13 +563,16 @@ KernelGmmu *pThis; RmHalspecOwner *pRmhalspecowner; - pThis = portMemAllocNonPaged(sizeof(KernelGmmu)); - if (pThis == NULL) return NV_ERR_NO_MEMORY; + status = __nvoc_handleObjCreateMemAlloc(createFlags, sizeof(KernelGmmu), (void**)&pThis, (void**)ppThis); + if (status != NV_OK) + return status; portMemSet(pThis, 0, sizeof(KernelGmmu)); __nvoc_initRtti(staticCast(pThis, Dynamic), &__nvoc_class_def_KernelGmmu); + pThis->__nvoc_base_OBJENGSTATE.__nvoc_base_Object.createFlags = createFlags; + if (pParent != NULL && !(createFlags & NVOC_OBJ_CREATE_FLAGS_PARENT_HALSPEC_ONLY)) { pParentObj = dynamicCast(pParent, Object); @@ -569,11 +592,17 @@ if (status != NV_OK) goto __nvoc_objCreate_KernelGmmu_cleanup; *ppThis = pThis; + return NV_OK; __nvoc_objCreate_KernelGmmu_cleanup: // do not call destructors here since the constructor already called them - portMemFree(pThis); + if (createFlags & NVOC_OBJ_CREATE_FLAGS_IN_PLACE_CONSTRUCT) + portMemSet(pThis, 0, sizeof(KernelGmmu)); + else + portMemFree(pThis); + + // coverity[leaked_storage:FALSE] return status; } diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/generated/g_kern_gmmu_nvoc.h nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_kern_gmmu_nvoc.h --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/generated/g_kern_gmmu_nvoc.h 2023-10-25 20:27:04.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_kern_gmmu_nvoc.h 2024-03-05 22:18:23.000000000 +0000 @@ -7,7 +7,7 @@ #endif /* - * SPDX-FileCopyrightText: Copyright (c) 2021-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. +3* SPDX-FileCopyrightText: Copyright (c) 2021-2024 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -146,6 +146,25 @@ }; /*! + * This structure holds information shared between CPU-RM + * and GSP-RM + */ +typedef struct +{ + /*! + * The value updated by GSP-RM to notify CPU-RM that + * a successful flush has happened + */ + NvU32 flushBufferSeqNum; + + /*! + * The GET index of replayable shadow buffer. This + * is updated by UVM driver and read by GSP-RM + */ + NvU32 swGetIndex; +} FAULT_BUFFER_SHARED_MEMORY; + +/*! * This structure holds information about the client shadow fault buffer. */ typedef struct @@ -185,6 +204,25 @@ GMMU_FAULT_BUFFER_PAGE *pBufferPages; NvU32 numBufferPages; + + /*! + * Start index of the page containing the fault buffer metadata. + * 0 if no metadata is present. + */ + NvU32 metadataStartIndex; + + /*! + * Used only by the replayable fault buffer. Memory descriptor used to + * describe shared memory b/w CPU-RM and GSP-RM. + */ + MEMORY_DESCRIPTOR *pFaultBufferSharedMemDesc; + + NvP64 pFaultBufferSharedMemoryAddress; + + NvP64 pFaultBufferSharedMemoryPriv; + + NvP64 pFaultBufferMetadataAddress; + } GMMU_CLIENT_SHADOW_FAULT_BUFFER; /*! @@ -209,9 +247,11 @@ /*! * Client shadow fault buffer data and pointer protected by gpu locks. + * Client may allocate upto 2 shadow buffers one each for replayable and + * non-replayable faults */ - GMMU_CLIENT_SHADOW_FAULT_BUFFER *pClientShadowFaultBuffer; - GMMU_CLIENT_SHADOW_FAULT_BUFFER clientShadowFaultBuffer; + GMMU_CLIENT_SHADOW_FAULT_BUFFER *pClientShadowFaultBuffer[NUM_FAULT_BUFFERS]; + GMMU_CLIENT_SHADOW_FAULT_BUFFER clientShadowFaultBuffer[NUM_FAULT_BUFFERS]; /*! * SpinLock to protect shadow buffer pointers @@ -222,6 +262,9 @@ * Flag stating fatalfault interrupt pending */ NvS32 fatalFaultIntrPending; + + /*! Generational counter for fault buffer. Incremented when the fault buffer wraps around. */ + volatile NvU64 faultBufferGenerationCounter; }; typedef struct GMMU_FAULT_PACKET @@ -233,6 +276,18 @@ // Initialize Circular Queue for MMU Shadow fault buffer MAKE_QUEUE_CIRCULAR(GMMU_SHADOW_FAULT_BUF, GMMU_FAULT_PACKET); +#define GMMU_FAULT_PACKET_METADATA_SIZE 32 +#define GMMU_FAULT_PACKET_METADATA_AUTHTAG_IDX 0 +#define GMMU_FAULT_PACKET_METADATA_AUTHTAG_SIZE 16 +#define GMMU_FAULT_PACKET_METADATA_VALID_IDX 16 +#define GMMU_FAULT_PACKET_METADATA_VALID_SIZE 1 +#define GMMU_FAULT_PACKET_METADATA_VALID_YES NV_TRUE +#define GMMU_FAULT_PACKET_METADATA_VALID_NO NV_FALSE + +typedef struct GMMU_FAULT_PACKET_METADATA +{ + NvU8 metadata[GMMU_FAULT_PACKET_METADATA_SIZE]; +} GMMU_FAULT_PACKET_METADATA; /*! * Structure that holds different parameters passed by an engine to kgmmuInstBlkInit @@ -294,9 +349,14 @@ NV_STATUS (*__kgmmuTranslatePtePcfFromHw__)(struct KernelGmmu *, NvU32, NvBool, NvU32 *); NV_STATUS (*__kgmmuTranslatePdePcfFromSw__)(struct KernelGmmu *, NvU32, NvU32 *); NV_STATUS (*__kgmmuTranslatePdePcfFromHw__)(struct KernelGmmu *, NvU32, GMMU_APERTURE, NvU32 *); + NV_STATUS (*__kgmmuGetFaultRegisterMappings__)(OBJGPU *, struct KernelGmmu *, NvU32, NvP64 *, NvP64 *, NvP64 *, NvP64 *, NvP64 *, NvP64 *, NvU32 *, NvP64 *); + NV_STATUS (*__kgmmuIssueReplayableFaultBufferFlush__)(OBJGPU *, struct KernelGmmu *); + NV_STATUS (*__kgmmuFaultBufferAllocSharedMemory__)(OBJGPU *, struct KernelGmmu *, FAULT_BUFFER_TYPE); + void (*__kgmmuFaultBufferFreeSharedMemory__)(OBJGPU *, struct KernelGmmu *, FAULT_BUFFER_TYPE); NV_STATUS (*__kgmmuSetupWarForBug2720120__)(struct KernelGmmu *, GMMU_FMT_FAMILY *); NvU32 (*__kgmmuGetGraphicsEngineId__)(struct KernelGmmu *); - NV_STATUS (*__kgmmuReconcileTunableState__)(POBJGPU, struct KernelGmmu *, void *); + NvU32 (*__kgmmuReadShadowBufPutIndex__)(OBJGPU *, struct KernelGmmu *, FAULT_BUFFER_TYPE); + NvU32 (*__kgmmuGetEccCounts__)(OBJGPU *, struct KernelGmmu *); NV_STATUS (*__kgmmuStateLoad__)(POBJGPU, struct KernelGmmu *, NvU32); NV_STATUS (*__kgmmuStateUnload__)(POBJGPU, struct KernelGmmu *, NvU32); NV_STATUS (*__kgmmuServiceNotificationInterrupt__)(struct OBJGPU *, struct KernelGmmu *, IntrServiceServiceNotificationInterruptArguments *); @@ -306,17 +366,12 @@ void (*__kgmmuInitMissing__)(POBJGPU, struct KernelGmmu *); NV_STATUS (*__kgmmuStatePreInitLocked__)(POBJGPU, struct KernelGmmu *); NV_STATUS (*__kgmmuStatePreInitUnlocked__)(POBJGPU, struct KernelGmmu *); - NV_STATUS (*__kgmmuGetTunableState__)(POBJGPU, struct KernelGmmu *, void *); - NV_STATUS (*__kgmmuCompareTunableState__)(POBJGPU, struct KernelGmmu *, void *, void *); - void (*__kgmmuFreeTunableState__)(POBJGPU, struct KernelGmmu *, void *); NvBool (*__kgmmuClearInterrupt__)(struct OBJGPU *, struct KernelGmmu *, IntrServiceClearInterruptArguments *); - NV_STATUS (*__kgmmuAllocTunableState__)(POBJGPU, struct KernelGmmu *, void **); - NV_STATUS (*__kgmmuSetTunableState__)(POBJGPU, struct KernelGmmu *, void *); NvBool (*__kgmmuIsPresent__)(POBJGPU, struct KernelGmmu *); NvBool PDB_PROP_KGMMU_SYSMEM_FAULT_BUFFER_GPU_UNCACHED; NvBool PDB_PROP_KGMMU_FAULT_BUFFER_DISABLED; const NV2080_CTRL_INTERNAL_GMMU_GET_STATIC_INFO_PARAMS *pStaticInfo; - NvU32 defaultBigPageSize; + NvU64 defaultBigPageSize; NvU32 uvmSharedIntrRmOwnsMask; GMMU_FMT_FAMILY *PRIVATE_FIELD(pFmtFamilies)[3]; NvU32 PRIVATE_FIELD(PDEAperture); @@ -327,7 +382,7 @@ NvU32 PRIVATE_FIELD(PTEAttr); NvU32 PRIVATE_FIELD(PTEBAR1Aperture); NvU32 PRIVATE_FIELD(PTEBAR1Attr); - NvU32 PRIVATE_FIELD(overrideBigPageSize); + NvU64 PRIVATE_FIELD(overrideBigPageSize); NvBool PRIVATE_FIELD(bEnablePerVaspaceBigPage); NvBool PRIVATE_FIELD(bIgnoreHubTlbInvalidate); NvU64 PRIVATE_FIELD(maxVASize); @@ -372,9 +427,14 @@ NV_STATUS (*__kgmmuTranslatePtePcfFromHw__)(struct KernelGmmu *, NvU32, NvBool, NvU32 *); NV_STATUS (*__kgmmuTranslatePdePcfFromSw__)(struct KernelGmmu *, NvU32, NvU32 *); NV_STATUS (*__kgmmuTranslatePdePcfFromHw__)(struct KernelGmmu *, NvU32, GMMU_APERTURE, NvU32 *); + NV_STATUS (*__kgmmuGetFaultRegisterMappings__)(OBJGPU *, struct KernelGmmu *, NvU32, NvP64 *, NvP64 *, NvP64 *, NvP64 *, NvP64 *, NvP64 *, NvU32 *, NvP64 *); + NV_STATUS (*__kgmmuIssueReplayableFaultBufferFlush__)(OBJGPU *, struct KernelGmmu *); + NV_STATUS (*__kgmmuFaultBufferAllocSharedMemory__)(OBJGPU *, struct KernelGmmu *, FAULT_BUFFER_TYPE); + void (*__kgmmuFaultBufferFreeSharedMemory__)(OBJGPU *, struct KernelGmmu *, FAULT_BUFFER_TYPE); NV_STATUS (*__kgmmuSetupWarForBug2720120__)(struct KernelGmmu *, GMMU_FMT_FAMILY *); NvU32 (*__kgmmuGetGraphicsEngineId__)(struct KernelGmmu *); - NV_STATUS (*__kgmmuReconcileTunableState__)(POBJGPU, struct KernelGmmu *, void *); + NvU32 (*__kgmmuReadShadowBufPutIndex__)(OBJGPU *, struct KernelGmmu *, FAULT_BUFFER_TYPE); + NvU32 (*__kgmmuGetEccCounts__)(OBJGPU *, struct KernelGmmu *); NV_STATUS (*__kgmmuStateLoad__)(POBJGPU, struct KernelGmmu *, NvU32); NV_STATUS (*__kgmmuStateUnload__)(POBJGPU, struct KernelGmmu *, NvU32); NV_STATUS (*__kgmmuServiceNotificationInterrupt__)(struct OBJGPU *, struct KernelGmmu *, IntrServiceServiceNotificationInterruptArguments *); @@ -384,17 +444,12 @@ void (*__kgmmuInitMissing__)(POBJGPU, struct KernelGmmu *); NV_STATUS (*__kgmmuStatePreInitLocked__)(POBJGPU, struct KernelGmmu *); NV_STATUS (*__kgmmuStatePreInitUnlocked__)(POBJGPU, struct KernelGmmu *); - NV_STATUS (*__kgmmuGetTunableState__)(POBJGPU, struct KernelGmmu *, void *); - NV_STATUS (*__kgmmuCompareTunableState__)(POBJGPU, struct KernelGmmu *, void *, void *); - void (*__kgmmuFreeTunableState__)(POBJGPU, struct KernelGmmu *, void *); NvBool (*__kgmmuClearInterrupt__)(struct OBJGPU *, struct KernelGmmu *, IntrServiceClearInterruptArguments *); - NV_STATUS (*__kgmmuAllocTunableState__)(POBJGPU, struct KernelGmmu *, void **); - NV_STATUS (*__kgmmuSetTunableState__)(POBJGPU, struct KernelGmmu *, void *); NvBool (*__kgmmuIsPresent__)(POBJGPU, struct KernelGmmu *); NvBool PDB_PROP_KGMMU_SYSMEM_FAULT_BUFFER_GPU_UNCACHED; NvBool PDB_PROP_KGMMU_FAULT_BUFFER_DISABLED; const NV2080_CTRL_INTERNAL_GMMU_GET_STATIC_INFO_PARAMS *pStaticInfo; - NvU32 defaultBigPageSize; + NvU64 defaultBigPageSize; NvU32 uvmSharedIntrRmOwnsMask; GMMU_FMT_FAMILY *pFmtFamilies[3]; NvU32 PDEAperture; @@ -405,7 +460,7 @@ NvU32 PTEAttr; NvU32 PTEBAR1Aperture; NvU32 PTEBAR1Attr; - NvU32 overrideBigPageSize; + NvU64 overrideBigPageSize; NvBool bEnablePerVaspaceBigPage; NvBool bIgnoreHubTlbInvalidate; NvU64 maxVASize; @@ -494,11 +549,22 @@ #define kgmmuTranslatePdePcfFromSw_HAL(pKernelGmmu, arg0, arg1) kgmmuTranslatePdePcfFromSw_DISPATCH(pKernelGmmu, arg0, arg1) #define kgmmuTranslatePdePcfFromHw(pKernelGmmu, arg0, arg1, arg2) kgmmuTranslatePdePcfFromHw_DISPATCH(pKernelGmmu, arg0, arg1, arg2) #define kgmmuTranslatePdePcfFromHw_HAL(pKernelGmmu, arg0, arg1, arg2) kgmmuTranslatePdePcfFromHw_DISPATCH(pKernelGmmu, arg0, arg1, arg2) +#define kgmmuGetFaultRegisterMappings(pGpu, pKernelGmmu, index, pFaultBufferGet, pFaultBufferPut, pFaultBufferInfo, faultIntr, faultIntrSet, faultIntrClear, faultMask, pPrefetchCtrl) kgmmuGetFaultRegisterMappings_DISPATCH(pGpu, pKernelGmmu, index, pFaultBufferGet, pFaultBufferPut, pFaultBufferInfo, faultIntr, faultIntrSet, faultIntrClear, faultMask, pPrefetchCtrl) +#define kgmmuGetFaultRegisterMappings_HAL(pGpu, pKernelGmmu, index, pFaultBufferGet, pFaultBufferPut, pFaultBufferInfo, faultIntr, faultIntrSet, faultIntrClear, faultMask, pPrefetchCtrl) kgmmuGetFaultRegisterMappings_DISPATCH(pGpu, pKernelGmmu, index, pFaultBufferGet, pFaultBufferPut, pFaultBufferInfo, faultIntr, faultIntrSet, faultIntrClear, faultMask, pPrefetchCtrl) +#define kgmmuIssueReplayableFaultBufferFlush(pGpu, pKernelGmmu) kgmmuIssueReplayableFaultBufferFlush_DISPATCH(pGpu, pKernelGmmu) +#define kgmmuIssueReplayableFaultBufferFlush_HAL(pGpu, pKernelGmmu) kgmmuIssueReplayableFaultBufferFlush_DISPATCH(pGpu, pKernelGmmu) +#define kgmmuFaultBufferAllocSharedMemory(pGpu, pKernelGmmu, arg0) kgmmuFaultBufferAllocSharedMemory_DISPATCH(pGpu, pKernelGmmu, arg0) +#define kgmmuFaultBufferAllocSharedMemory_HAL(pGpu, pKernelGmmu, arg0) kgmmuFaultBufferAllocSharedMemory_DISPATCH(pGpu, pKernelGmmu, arg0) +#define kgmmuFaultBufferFreeSharedMemory(pGpu, pKernelGmmu, arg0) kgmmuFaultBufferFreeSharedMemory_DISPATCH(pGpu, pKernelGmmu, arg0) +#define kgmmuFaultBufferFreeSharedMemory_HAL(pGpu, pKernelGmmu, arg0) kgmmuFaultBufferFreeSharedMemory_DISPATCH(pGpu, pKernelGmmu, arg0) #define kgmmuSetupWarForBug2720120(pKernelGmmu, pFam) kgmmuSetupWarForBug2720120_DISPATCH(pKernelGmmu, pFam) #define kgmmuSetupWarForBug2720120_HAL(pKernelGmmu, pFam) kgmmuSetupWarForBug2720120_DISPATCH(pKernelGmmu, pFam) #define kgmmuGetGraphicsEngineId(pKernelGmmu) kgmmuGetGraphicsEngineId_DISPATCH(pKernelGmmu) #define kgmmuGetGraphicsEngineId_HAL(pKernelGmmu) kgmmuGetGraphicsEngineId_DISPATCH(pKernelGmmu) -#define kgmmuReconcileTunableState(pGpu, pEngstate, pTunableState) kgmmuReconcileTunableState_DISPATCH(pGpu, pEngstate, pTunableState) +#define kgmmuReadShadowBufPutIndex(pGpu, pKernelGmmu, type) kgmmuReadShadowBufPutIndex_DISPATCH(pGpu, pKernelGmmu, type) +#define kgmmuReadShadowBufPutIndex_HAL(pGpu, pKernelGmmu, type) kgmmuReadShadowBufPutIndex_DISPATCH(pGpu, pKernelGmmu, type) +#define kgmmuGetEccCounts(pGpu, pKernelGmmu) kgmmuGetEccCounts_DISPATCH(pGpu, pKernelGmmu) +#define kgmmuGetEccCounts_HAL(pGpu, pKernelGmmu) kgmmuGetEccCounts_DISPATCH(pGpu, pKernelGmmu) #define kgmmuStateLoad(pGpu, pEngstate, arg0) kgmmuStateLoad_DISPATCH(pGpu, pEngstate, arg0) #define kgmmuStateUnload(pGpu, pEngstate, arg0) kgmmuStateUnload_DISPATCH(pGpu, pEngstate, arg0) #define kgmmuServiceNotificationInterrupt(pGpu, pIntrService, pParams) kgmmuServiceNotificationInterrupt_DISPATCH(pGpu, pIntrService, pParams) @@ -508,18 +574,13 @@ #define kgmmuInitMissing(pGpu, pEngstate) kgmmuInitMissing_DISPATCH(pGpu, pEngstate) #define kgmmuStatePreInitLocked(pGpu, pEngstate) kgmmuStatePreInitLocked_DISPATCH(pGpu, pEngstate) #define kgmmuStatePreInitUnlocked(pGpu, pEngstate) kgmmuStatePreInitUnlocked_DISPATCH(pGpu, pEngstate) -#define kgmmuGetTunableState(pGpu, pEngstate, pTunableState) kgmmuGetTunableState_DISPATCH(pGpu, pEngstate, pTunableState) -#define kgmmuCompareTunableState(pGpu, pEngstate, pTunables1, pTunables2) kgmmuCompareTunableState_DISPATCH(pGpu, pEngstate, pTunables1, pTunables2) -#define kgmmuFreeTunableState(pGpu, pEngstate, pTunableState) kgmmuFreeTunableState_DISPATCH(pGpu, pEngstate, pTunableState) #define kgmmuClearInterrupt(pGpu, pIntrService, pParams) kgmmuClearInterrupt_DISPATCH(pGpu, pIntrService, pParams) -#define kgmmuAllocTunableState(pGpu, pEngstate, ppTunableState) kgmmuAllocTunableState_DISPATCH(pGpu, pEngstate, ppTunableState) -#define kgmmuSetTunableState(pGpu, pEngstate, pTunableState) kgmmuSetTunableState_DISPATCH(pGpu, pEngstate, pTunableState) #define kgmmuIsPresent(pGpu, pEngstate) kgmmuIsPresent_DISPATCH(pGpu, pEngstate) -NvU32 kgmmuGetMaxBigPageSize_GM107(struct KernelGmmu *pKernelGmmu); +NvU64 kgmmuGetMaxBigPageSize_GM107(struct KernelGmmu *pKernelGmmu); #ifdef __nvoc_kern_gmmu_h_disabled -static inline NvU32 kgmmuGetMaxBigPageSize(struct KernelGmmu *pKernelGmmu) { +static inline NvU64 kgmmuGetMaxBigPageSize(struct KernelGmmu *pKernelGmmu) { NV_ASSERT_FAILED_PRECOMP("KernelGmmu was disabled!"); return 0; } @@ -559,6 +620,22 @@ #define kgmmuInstBlkAtsGet_HAL(pKernelGmmu, pVAS, subctxid, pOffset, pData) kgmmuInstBlkAtsGet(pKernelGmmu, pVAS, subctxid, pOffset, pData) +static inline NV_STATUS kgmmuInstBlkMagicValueGet_46f6a7(struct KernelGmmu *pKernelGmmu, NvU32 *pOffset, NvU32 *pData) { + return NV_ERR_NOT_SUPPORTED; +} + + +#ifdef __nvoc_kern_gmmu_h_disabled +static inline NV_STATUS kgmmuInstBlkMagicValueGet(struct KernelGmmu *pKernelGmmu, NvU32 *pOffset, NvU32 *pData) { + NV_ASSERT_FAILED_PRECOMP("KernelGmmu was disabled!"); + return NV_ERR_NOT_SUPPORTED; +} +#else //__nvoc_kern_gmmu_h_disabled +#define kgmmuInstBlkMagicValueGet(pKernelGmmu, pOffset, pData) kgmmuInstBlkMagicValueGet_46f6a7(pKernelGmmu, pOffset, pData) +#endif //__nvoc_kern_gmmu_h_disabled + +#define kgmmuInstBlkMagicValueGet_HAL(pKernelGmmu, pOffset, pData) kgmmuInstBlkMagicValueGet(pKernelGmmu, pOffset, pData) + NV_STATUS kgmmuInstBlkPageDirBaseGet_GV100(OBJGPU *pGpu, struct KernelGmmu *pKernelGmmu, struct OBJVASPACE *pVAS, INST_BLK_INIT_PARAMS *pParams, NvU32 subctxid, NvU32 *pOffsetLo, NvU32 *pDataLo, NvU32 *pOffsetHi, NvU32 *pDataHi); @@ -587,11 +664,11 @@ #define kgmmuGetPDBAllocSize_HAL(pKernelGmmu, arg0, arg1) kgmmuGetPDBAllocSize(pKernelGmmu, arg0, arg1) -NvU32 kgmmuGetBigPageSize_GM107(struct KernelGmmu *pKernelGmmu); +NvU64 kgmmuGetBigPageSize_GM107(struct KernelGmmu *pKernelGmmu); #ifdef __nvoc_kern_gmmu_h_disabled -static inline NvU32 kgmmuGetBigPageSize(struct KernelGmmu *pKernelGmmu) { +static inline NvU64 kgmmuGetBigPageSize(struct KernelGmmu *pKernelGmmu) { NV_ASSERT_FAILED_PRECOMP("KernelGmmu was disabled!"); return 0; } @@ -735,20 +812,6 @@ #define kgmmuDetermineMaxVASize_HAL(pGpu, pKernelGmmu) kgmmuDetermineMaxVASize(pGpu, pKernelGmmu) -NV_STATUS kgmmuGetFaultRegisterMappings_TU102(OBJGPU *pGpu, struct KernelGmmu *pKernelGmmu, NvU32 index, NvP64 *pFaultBufferGet, NvP64 *pFaultBufferPut, NvP64 *pFaultBufferInfo, NvP64 *faultIntr, NvP64 *faultIntrSet, NvP64 *faultIntrClear, NvU32 *faultMask, NvP64 *pPrefetchCtrl); - - -#ifdef __nvoc_kern_gmmu_h_disabled -static inline NV_STATUS kgmmuGetFaultRegisterMappings(OBJGPU *pGpu, struct KernelGmmu *pKernelGmmu, NvU32 index, NvP64 *pFaultBufferGet, NvP64 *pFaultBufferPut, NvP64 *pFaultBufferInfo, NvP64 *faultIntr, NvP64 *faultIntrSet, NvP64 *faultIntrClear, NvU32 *faultMask, NvP64 *pPrefetchCtrl) { - NV_ASSERT_FAILED_PRECOMP("KernelGmmu was disabled!"); - return NV_ERR_NOT_SUPPORTED; -} -#else //__nvoc_kern_gmmu_h_disabled -#define kgmmuGetFaultRegisterMappings(pGpu, pKernelGmmu, index, pFaultBufferGet, pFaultBufferPut, pFaultBufferInfo, faultIntr, faultIntrSet, faultIntrClear, faultMask, pPrefetchCtrl) kgmmuGetFaultRegisterMappings_TU102(pGpu, pKernelGmmu, index, pFaultBufferGet, pFaultBufferPut, pFaultBufferInfo, faultIntr, faultIntrSet, faultIntrClear, faultMask, pPrefetchCtrl) -#endif //__nvoc_kern_gmmu_h_disabled - -#define kgmmuGetFaultRegisterMappings_HAL(pGpu, pKernelGmmu, index, pFaultBufferGet, pFaultBufferPut, pFaultBufferInfo, faultIntr, faultIntrSet, faultIntrClear, faultMask, pPrefetchCtrl) kgmmuGetFaultRegisterMappings(pGpu, pKernelGmmu, index, pFaultBufferGet, pFaultBufferPut, pFaultBufferInfo, faultIntr, faultIntrSet, faultIntrClear, faultMask, pPrefetchCtrl) - const char *kgmmuGetFaultTypeString_GP100(struct KernelGmmu *pKernelGmmu, NvU32 faultType); @@ -888,33 +951,33 @@ #define kgmmuIsNonReplayableFaultPending_HAL(pGpu, pKernelGmmu, arg0) kgmmuIsNonReplayableFaultPending(pGpu, pKernelGmmu, arg0) -NV_STATUS kgmmuClientShadowFaultBufferAlloc_GV100(OBJGPU *pGpu, struct KernelGmmu *pKernelGmmu); +NV_STATUS kgmmuClientShadowFaultBufferAlloc_GV100(OBJGPU *pGpu, struct KernelGmmu *pKernelGmmu, FAULT_BUFFER_TYPE arg0); #ifdef __nvoc_kern_gmmu_h_disabled -static inline NV_STATUS kgmmuClientShadowFaultBufferAlloc(OBJGPU *pGpu, struct KernelGmmu *pKernelGmmu) { +static inline NV_STATUS kgmmuClientShadowFaultBufferAlloc(OBJGPU *pGpu, struct KernelGmmu *pKernelGmmu, FAULT_BUFFER_TYPE arg0) { NV_ASSERT_FAILED_PRECOMP("KernelGmmu was disabled!"); return NV_ERR_NOT_SUPPORTED; } #else //__nvoc_kern_gmmu_h_disabled -#define kgmmuClientShadowFaultBufferAlloc(pGpu, pKernelGmmu) kgmmuClientShadowFaultBufferAlloc_GV100(pGpu, pKernelGmmu) +#define kgmmuClientShadowFaultBufferAlloc(pGpu, pKernelGmmu, arg0) kgmmuClientShadowFaultBufferAlloc_GV100(pGpu, pKernelGmmu, arg0) #endif //__nvoc_kern_gmmu_h_disabled -#define kgmmuClientShadowFaultBufferAlloc_HAL(pGpu, pKernelGmmu) kgmmuClientShadowFaultBufferAlloc(pGpu, pKernelGmmu) +#define kgmmuClientShadowFaultBufferAlloc_HAL(pGpu, pKernelGmmu, arg0) kgmmuClientShadowFaultBufferAlloc(pGpu, pKernelGmmu, arg0) -NV_STATUS kgmmuClientShadowFaultBufferFree_GV100(OBJGPU *pGpu, struct KernelGmmu *pKernelGmmu); +NV_STATUS kgmmuClientShadowFaultBufferFree_GV100(OBJGPU *pGpu, struct KernelGmmu *pKernelGmmu, FAULT_BUFFER_TYPE arg0); #ifdef __nvoc_kern_gmmu_h_disabled -static inline NV_STATUS kgmmuClientShadowFaultBufferFree(OBJGPU *pGpu, struct KernelGmmu *pKernelGmmu) { +static inline NV_STATUS kgmmuClientShadowFaultBufferFree(OBJGPU *pGpu, struct KernelGmmu *pKernelGmmu, FAULT_BUFFER_TYPE arg0) { NV_ASSERT_FAILED_PRECOMP("KernelGmmu was disabled!"); return NV_ERR_NOT_SUPPORTED; } #else //__nvoc_kern_gmmu_h_disabled -#define kgmmuClientShadowFaultBufferFree(pGpu, pKernelGmmu) kgmmuClientShadowFaultBufferFree_GV100(pGpu, pKernelGmmu) +#define kgmmuClientShadowFaultBufferFree(pGpu, pKernelGmmu, arg0) kgmmuClientShadowFaultBufferFree_GV100(pGpu, pKernelGmmu, arg0) #endif //__nvoc_kern_gmmu_h_disabled -#define kgmmuClientShadowFaultBufferFree_HAL(pGpu, pKernelGmmu) kgmmuClientShadowFaultBufferFree(pGpu, pKernelGmmu) +#define kgmmuClientShadowFaultBufferFree_HAL(pGpu, pKernelGmmu, arg0) kgmmuClientShadowFaultBufferFree(pGpu, pKernelGmmu, arg0) void kgmmuEncodeSysmemAddrs_GM107(struct KernelGmmu *pKernelGmmu, NvU64 *pAddresses, NvU64 count); @@ -984,6 +1047,19 @@ #define kgmmuClearNonReplayableFaultIntr_HAL(pGpu, pKernelGmmu, arg0) kgmmuClearNonReplayableFaultIntr(pGpu, pKernelGmmu, arg0) +void kgmmuClearReplayableFaultIntr_TU102(OBJGPU *pGpu, struct KernelGmmu *pKernelGmmu, struct THREAD_STATE_NODE *arg0); + + +#ifdef __nvoc_kern_gmmu_h_disabled +static inline void kgmmuClearReplayableFaultIntr(OBJGPU *pGpu, struct KernelGmmu *pKernelGmmu, struct THREAD_STATE_NODE *arg0) { + NV_ASSERT_FAILED_PRECOMP("KernelGmmu was disabled!"); +} +#else //__nvoc_kern_gmmu_h_disabled +#define kgmmuClearReplayableFaultIntr(pGpu, pKernelGmmu, arg0) kgmmuClearReplayableFaultIntr_TU102(pGpu, pKernelGmmu, arg0) +#endif //__nvoc_kern_gmmu_h_disabled + +#define kgmmuClearReplayableFaultIntr_HAL(pGpu, pKernelGmmu, arg0) kgmmuClearReplayableFaultIntr(pGpu, pKernelGmmu, arg0) + NV_STATUS kgmmuConstructEngine_IMPL(OBJGPU *pGpu, struct KernelGmmu *pKernelGmmu, ENGDESCRIPTOR arg0); static inline NV_STATUS kgmmuConstructEngine_DISPATCH(OBJGPU *pGpu, struct KernelGmmu *pKernelGmmu, ENGDESCRIPTOR arg0) { @@ -1014,9 +1090,9 @@ pKernelGmmu->__kgmmuStateDestroy__(pGpu, pKernelGmmu); } -void kgmmuRegisterIntrService_IMPL(OBJGPU *pGpu, struct KernelGmmu *pKernelGmmu, IntrServiceRecord arg0[163]); +void kgmmuRegisterIntrService_IMPL(OBJGPU *pGpu, struct KernelGmmu *pKernelGmmu, IntrServiceRecord arg0[167]); -static inline void kgmmuRegisterIntrService_DISPATCH(OBJGPU *pGpu, struct KernelGmmu *pKernelGmmu, IntrServiceRecord arg0[163]) { +static inline void kgmmuRegisterIntrService_DISPATCH(OBJGPU *pGpu, struct KernelGmmu *pKernelGmmu, IntrServiceRecord arg0[167]) { pKernelGmmu->__kgmmuRegisterIntrService__(pGpu, pKernelGmmu, arg0); } @@ -1167,6 +1243,44 @@ return pKernelGmmu->__kgmmuTranslatePdePcfFromHw__(pKernelGmmu, arg0, arg1, arg2); } +NV_STATUS kgmmuGetFaultRegisterMappings_TU102(OBJGPU *pGpu, struct KernelGmmu *pKernelGmmu, NvU32 index, NvP64 *pFaultBufferGet, NvP64 *pFaultBufferPut, NvP64 *pFaultBufferInfo, NvP64 *faultIntr, NvP64 *faultIntrSet, NvP64 *faultIntrClear, NvU32 *faultMask, NvP64 *pPrefetchCtrl); + +NV_STATUS kgmmuGetFaultRegisterMappings_GH100(OBJGPU *pGpu, struct KernelGmmu *pKernelGmmu, NvU32 index, NvP64 *pFaultBufferGet, NvP64 *pFaultBufferPut, NvP64 *pFaultBufferInfo, NvP64 *faultIntr, NvP64 *faultIntrSet, NvP64 *faultIntrClear, NvU32 *faultMask, NvP64 *pPrefetchCtrl); + +static inline NV_STATUS kgmmuGetFaultRegisterMappings_DISPATCH(OBJGPU *pGpu, struct KernelGmmu *pKernelGmmu, NvU32 index, NvP64 *pFaultBufferGet, NvP64 *pFaultBufferPut, NvP64 *pFaultBufferInfo, NvP64 *faultIntr, NvP64 *faultIntrSet, NvP64 *faultIntrClear, NvU32 *faultMask, NvP64 *pPrefetchCtrl) { + return pKernelGmmu->__kgmmuGetFaultRegisterMappings__(pGpu, pKernelGmmu, index, pFaultBufferGet, pFaultBufferPut, pFaultBufferInfo, faultIntr, faultIntrSet, faultIntrClear, faultMask, pPrefetchCtrl); +} + +NV_STATUS kgmmuIssueReplayableFaultBufferFlush_GH100(OBJGPU *pGpu, struct KernelGmmu *pKernelGmmu); + +static inline NV_STATUS kgmmuIssueReplayableFaultBufferFlush_46f6a7(OBJGPU *pGpu, struct KernelGmmu *pKernelGmmu) { + return NV_ERR_NOT_SUPPORTED; +} + +static inline NV_STATUS kgmmuIssueReplayableFaultBufferFlush_DISPATCH(OBJGPU *pGpu, struct KernelGmmu *pKernelGmmu) { + return pKernelGmmu->__kgmmuIssueReplayableFaultBufferFlush__(pGpu, pKernelGmmu); +} + +NV_STATUS kgmmuFaultBufferAllocSharedMemory_GH100(OBJGPU *pGpu, struct KernelGmmu *pKernelGmmu, FAULT_BUFFER_TYPE arg0); + +static inline NV_STATUS kgmmuFaultBufferAllocSharedMemory_56cd7a(OBJGPU *pGpu, struct KernelGmmu *pKernelGmmu, FAULT_BUFFER_TYPE arg0) { + return NV_OK; +} + +static inline NV_STATUS kgmmuFaultBufferAllocSharedMemory_DISPATCH(OBJGPU *pGpu, struct KernelGmmu *pKernelGmmu, FAULT_BUFFER_TYPE arg0) { + return pKernelGmmu->__kgmmuFaultBufferAllocSharedMemory__(pGpu, pKernelGmmu, arg0); +} + +void kgmmuFaultBufferFreeSharedMemory_GH100(OBJGPU *pGpu, struct KernelGmmu *pKernelGmmu, FAULT_BUFFER_TYPE arg0); + +static inline void kgmmuFaultBufferFreeSharedMemory_b3696a(OBJGPU *pGpu, struct KernelGmmu *pKernelGmmu, FAULT_BUFFER_TYPE arg0) { + return; +} + +static inline void kgmmuFaultBufferFreeSharedMemory_DISPATCH(OBJGPU *pGpu, struct KernelGmmu *pKernelGmmu, FAULT_BUFFER_TYPE arg0) { + pKernelGmmu->__kgmmuFaultBufferFreeSharedMemory__(pGpu, pKernelGmmu, arg0); +} + NV_STATUS kgmmuSetupWarForBug2720120_GA100(struct KernelGmmu *pKernelGmmu, GMMU_FMT_FAMILY *pFam); static inline NV_STATUS kgmmuSetupWarForBug2720120_56cd7a(struct KernelGmmu *pKernelGmmu, GMMU_FMT_FAMILY *pFam) { @@ -1185,8 +1299,24 @@ return pKernelGmmu->__kgmmuGetGraphicsEngineId__(pKernelGmmu); } -static inline NV_STATUS kgmmuReconcileTunableState_DISPATCH(POBJGPU pGpu, struct KernelGmmu *pEngstate, void *pTunableState) { - return pEngstate->__kgmmuReconcileTunableState__(pGpu, pEngstate, pTunableState); +NvU32 kgmmuReadShadowBufPutIndex_GH100(OBJGPU *pGpu, struct KernelGmmu *pKernelGmmu, FAULT_BUFFER_TYPE type); + +static inline NvU32 kgmmuReadShadowBufPutIndex_4a4dee(OBJGPU *pGpu, struct KernelGmmu *pKernelGmmu, FAULT_BUFFER_TYPE type) { + return 0; +} + +static inline NvU32 kgmmuReadShadowBufPutIndex_DISPATCH(OBJGPU *pGpu, struct KernelGmmu *pKernelGmmu, FAULT_BUFFER_TYPE type) { + return pKernelGmmu->__kgmmuReadShadowBufPutIndex__(pGpu, pKernelGmmu, type); +} + +NvU32 kgmmuGetEccCounts_TU102(OBJGPU *pGpu, struct KernelGmmu *pKernelGmmu); + +static inline NvU32 kgmmuGetEccCounts_4a4dee(OBJGPU *pGpu, struct KernelGmmu *pKernelGmmu) { + return 0; +} + +static inline NvU32 kgmmuGetEccCounts_DISPATCH(OBJGPU *pGpu, struct KernelGmmu *pKernelGmmu) { + return pKernelGmmu->__kgmmuGetEccCounts__(pGpu, pKernelGmmu); } static inline NV_STATUS kgmmuStateLoad_DISPATCH(POBJGPU pGpu, struct KernelGmmu *pEngstate, NvU32 arg0) { @@ -1225,30 +1355,10 @@ return pEngstate->__kgmmuStatePreInitUnlocked__(pGpu, pEngstate); } -static inline NV_STATUS kgmmuGetTunableState_DISPATCH(POBJGPU pGpu, struct KernelGmmu *pEngstate, void *pTunableState) { - return pEngstate->__kgmmuGetTunableState__(pGpu, pEngstate, pTunableState); -} - -static inline NV_STATUS kgmmuCompareTunableState_DISPATCH(POBJGPU pGpu, struct KernelGmmu *pEngstate, void *pTunables1, void *pTunables2) { - return pEngstate->__kgmmuCompareTunableState__(pGpu, pEngstate, pTunables1, pTunables2); -} - -static inline void kgmmuFreeTunableState_DISPATCH(POBJGPU pGpu, struct KernelGmmu *pEngstate, void *pTunableState) { - pEngstate->__kgmmuFreeTunableState__(pGpu, pEngstate, pTunableState); -} - static inline NvBool kgmmuClearInterrupt_DISPATCH(struct OBJGPU *pGpu, struct KernelGmmu *pIntrService, IntrServiceClearInterruptArguments *pParams) { return pIntrService->__kgmmuClearInterrupt__(pGpu, pIntrService, pParams); } -static inline NV_STATUS kgmmuAllocTunableState_DISPATCH(POBJGPU pGpu, struct KernelGmmu *pEngstate, void **ppTunableState) { - return pEngstate->__kgmmuAllocTunableState__(pGpu, pEngstate, ppTunableState); -} - -static inline NV_STATUS kgmmuSetTunableState_DISPATCH(POBJGPU pGpu, struct KernelGmmu *pEngstate, void *pTunableState) { - return pEngstate->__kgmmuSetTunableState__(pGpu, pEngstate, pTunableState); -} - static inline NvBool kgmmuIsPresent_DISPATCH(POBJGPU pGpu, struct KernelGmmu *pEngstate) { return pEngstate->__kgmmuIsPresent__(pGpu, pEngstate); } @@ -1293,12 +1403,12 @@ return pKernelGmmu_PRIVATE->PTEAttr; } -static inline NvU32 kgmmuGetBigPageSizeOverride(struct KernelGmmu *pKernelGmmu) { +static inline NvU64 kgmmuGetBigPageSizeOverride(struct KernelGmmu *pKernelGmmu) { struct KernelGmmu_PRIVATE *pKernelGmmu_PRIVATE = (struct KernelGmmu_PRIVATE *)pKernelGmmu; return pKernelGmmu_PRIVATE->overrideBigPageSize; } -static inline void kgmmuSetBigPageSizeOverride(struct KernelGmmu *pKernelGmmu, NvU32 bigPageSize) { +static inline void kgmmuSetBigPageSizeOverride(struct KernelGmmu *pKernelGmmu, NvU64 bigPageSize) { struct KernelGmmu_PRIVATE *pKernelGmmu_PRIVATE = (struct KernelGmmu_PRIVATE *)pKernelGmmu; pKernelGmmu_PRIVATE->overrideBigPageSize = bigPageSize; } @@ -1445,10 +1555,10 @@ #define kgmmuFmtGetLatestSupportedFormat(pGpu, pKernelGmmu) kgmmuFmtGetLatestSupportedFormat_IMPL(pGpu, pKernelGmmu) #endif //__nvoc_kern_gmmu_h_disabled -NvU32 kgmmuGetMinBigPageSize_IMPL(struct KernelGmmu *pKernelGmmu); +NvU64 kgmmuGetMinBigPageSize_IMPL(struct KernelGmmu *pKernelGmmu); #ifdef __nvoc_kern_gmmu_h_disabled -static inline NvU32 kgmmuGetMinBigPageSize(struct KernelGmmu *pKernelGmmu) { +static inline NvU64 kgmmuGetMinBigPageSize(struct KernelGmmu *pKernelGmmu) { NV_ASSERT_FAILED_PRECOMP("KernelGmmu was disabled!"); return 0; } @@ -1544,67 +1654,67 @@ #define kgmmuFaultBufferUnregister(pGpu, pKernelGmmu, arg0) kgmmuFaultBufferUnregister_IMPL(pGpu, pKernelGmmu, arg0) #endif //__nvoc_kern_gmmu_h_disabled -NV_STATUS kgmmuClientShadowFaultBufferNonreplayableAllocate_IMPL(OBJGPU *pGpu, struct KernelGmmu *pKernelGmmu); +NV_STATUS kgmmuClientShadowFaultBufferAllocate_IMPL(OBJGPU *pGpu, struct KernelGmmu *pKernelGmmu, FAULT_BUFFER_TYPE arg0); #ifdef __nvoc_kern_gmmu_h_disabled -static inline NV_STATUS kgmmuClientShadowFaultBufferNonreplayableAllocate(OBJGPU *pGpu, struct KernelGmmu *pKernelGmmu) { +static inline NV_STATUS kgmmuClientShadowFaultBufferAllocate(OBJGPU *pGpu, struct KernelGmmu *pKernelGmmu, FAULT_BUFFER_TYPE arg0) { NV_ASSERT_FAILED_PRECOMP("KernelGmmu was disabled!"); return NV_ERR_NOT_SUPPORTED; } #else //__nvoc_kern_gmmu_h_disabled -#define kgmmuClientShadowFaultBufferNonreplayableAllocate(pGpu, pKernelGmmu) kgmmuClientShadowFaultBufferNonreplayableAllocate_IMPL(pGpu, pKernelGmmu) +#define kgmmuClientShadowFaultBufferAllocate(pGpu, pKernelGmmu, arg0) kgmmuClientShadowFaultBufferAllocate_IMPL(pGpu, pKernelGmmu, arg0) #endif //__nvoc_kern_gmmu_h_disabled -NV_STATUS kgmmuClientShadowFaultBufferNonreplayableDestroy_IMPL(OBJGPU *pGpu, struct KernelGmmu *pKernelGmmu); +NV_STATUS kgmmuClientShadowFaultBufferDestroy_IMPL(OBJGPU *pGpu, struct KernelGmmu *pKernelGmmu, FAULT_BUFFER_TYPE arg0); #ifdef __nvoc_kern_gmmu_h_disabled -static inline NV_STATUS kgmmuClientShadowFaultBufferNonreplayableDestroy(OBJGPU *pGpu, struct KernelGmmu *pKernelGmmu) { +static inline NV_STATUS kgmmuClientShadowFaultBufferDestroy(OBJGPU *pGpu, struct KernelGmmu *pKernelGmmu, FAULT_BUFFER_TYPE arg0) { NV_ASSERT_FAILED_PRECOMP("KernelGmmu was disabled!"); return NV_ERR_NOT_SUPPORTED; } #else //__nvoc_kern_gmmu_h_disabled -#define kgmmuClientShadowFaultBufferNonreplayableDestroy(pGpu, pKernelGmmu) kgmmuClientShadowFaultBufferNonreplayableDestroy_IMPL(pGpu, pKernelGmmu) +#define kgmmuClientShadowFaultBufferDestroy(pGpu, pKernelGmmu, arg0) kgmmuClientShadowFaultBufferDestroy_IMPL(pGpu, pKernelGmmu, arg0) #endif //__nvoc_kern_gmmu_h_disabled -NV_STATUS kgmmuClientShadowFaultBufferRegister_IMPL(OBJGPU *pGpu, struct KernelGmmu *pKernelGmmu); +NV_STATUS kgmmuClientShadowFaultBufferRegister_IMPL(OBJGPU *pGpu, struct KernelGmmu *pKernelGmmu, FAULT_BUFFER_TYPE arg0); #ifdef __nvoc_kern_gmmu_h_disabled -static inline NV_STATUS kgmmuClientShadowFaultBufferRegister(OBJGPU *pGpu, struct KernelGmmu *pKernelGmmu) { +static inline NV_STATUS kgmmuClientShadowFaultBufferRegister(OBJGPU *pGpu, struct KernelGmmu *pKernelGmmu, FAULT_BUFFER_TYPE arg0) { NV_ASSERT_FAILED_PRECOMP("KernelGmmu was disabled!"); return NV_ERR_NOT_SUPPORTED; } #else //__nvoc_kern_gmmu_h_disabled -#define kgmmuClientShadowFaultBufferRegister(pGpu, pKernelGmmu) kgmmuClientShadowFaultBufferRegister_IMPL(pGpu, pKernelGmmu) +#define kgmmuClientShadowFaultBufferRegister(pGpu, pKernelGmmu, arg0) kgmmuClientShadowFaultBufferRegister_IMPL(pGpu, pKernelGmmu, arg0) #endif //__nvoc_kern_gmmu_h_disabled -void kgmmuClientShadowFaultBufferUnregister_IMPL(OBJGPU *pGpu, struct KernelGmmu *pKernelGmmu); +void kgmmuClientShadowFaultBufferUnregister_IMPL(OBJGPU *pGpu, struct KernelGmmu *pKernelGmmu, FAULT_BUFFER_TYPE arg0); #ifdef __nvoc_kern_gmmu_h_disabled -static inline void kgmmuClientShadowFaultBufferUnregister(OBJGPU *pGpu, struct KernelGmmu *pKernelGmmu) { +static inline void kgmmuClientShadowFaultBufferUnregister(OBJGPU *pGpu, struct KernelGmmu *pKernelGmmu, FAULT_BUFFER_TYPE arg0) { NV_ASSERT_FAILED_PRECOMP("KernelGmmu was disabled!"); } #else //__nvoc_kern_gmmu_h_disabled -#define kgmmuClientShadowFaultBufferUnregister(pGpu, pKernelGmmu) kgmmuClientShadowFaultBufferUnregister_IMPL(pGpu, pKernelGmmu) +#define kgmmuClientShadowFaultBufferUnregister(pGpu, pKernelGmmu, arg0) kgmmuClientShadowFaultBufferUnregister_IMPL(pGpu, pKernelGmmu, arg0) #endif //__nvoc_kern_gmmu_h_disabled -void kgmmuClientShadowFaultBufferPagesDestroy_IMPL(OBJGPU *pGpu, struct KernelGmmu *pKernelGmmu, NvBool arg0); +void kgmmuClientShadowFaultBufferPagesDestroy_IMPL(OBJGPU *pGpu, struct KernelGmmu *pKernelGmmu, NvBool arg0, FAULT_BUFFER_TYPE arg1); #ifdef __nvoc_kern_gmmu_h_disabled -static inline void kgmmuClientShadowFaultBufferPagesDestroy(OBJGPU *pGpu, struct KernelGmmu *pKernelGmmu, NvBool arg0) { +static inline void kgmmuClientShadowFaultBufferPagesDestroy(OBJGPU *pGpu, struct KernelGmmu *pKernelGmmu, NvBool arg0, FAULT_BUFFER_TYPE arg1) { NV_ASSERT_FAILED_PRECOMP("KernelGmmu was disabled!"); } #else //__nvoc_kern_gmmu_h_disabled -#define kgmmuClientShadowFaultBufferPagesDestroy(pGpu, pKernelGmmu, arg0) kgmmuClientShadowFaultBufferPagesDestroy_IMPL(pGpu, pKernelGmmu, arg0) +#define kgmmuClientShadowFaultBufferPagesDestroy(pGpu, pKernelGmmu, arg0, arg1) kgmmuClientShadowFaultBufferPagesDestroy_IMPL(pGpu, pKernelGmmu, arg0, arg1) #endif //__nvoc_kern_gmmu_h_disabled -void kgmmuClientShadowFaultBufferQueueDestroy_IMPL(OBJGPU *pGpu, struct KernelGmmu *pKernelGmmu, NvBool arg0); +void kgmmuClientShadowFaultBufferQueueDestroy_IMPL(OBJGPU *pGpu, struct KernelGmmu *pKernelGmmu, NvBool arg0, FAULT_BUFFER_TYPE arg1); #ifdef __nvoc_kern_gmmu_h_disabled -static inline void kgmmuClientShadowFaultBufferQueueDestroy(OBJGPU *pGpu, struct KernelGmmu *pKernelGmmu, NvBool arg0) { +static inline void kgmmuClientShadowFaultBufferQueueDestroy(OBJGPU *pGpu, struct KernelGmmu *pKernelGmmu, NvBool arg0, FAULT_BUFFER_TYPE arg1) { NV_ASSERT_FAILED_PRECOMP("KernelGmmu was disabled!"); } #else //__nvoc_kern_gmmu_h_disabled -#define kgmmuClientShadowFaultBufferQueueDestroy(pGpu, pKernelGmmu, arg0) kgmmuClientShadowFaultBufferQueueDestroy_IMPL(pGpu, pKernelGmmu, arg0) +#define kgmmuClientShadowFaultBufferQueueDestroy(pGpu, pKernelGmmu, arg0, arg1) kgmmuClientShadowFaultBufferQueueDestroy_IMPL(pGpu, pKernelGmmu, arg0, arg1) #endif //__nvoc_kern_gmmu_h_disabled NvU64 kgmmuGetSizeOfPageTables_IMPL(OBJGPU *pGpu, struct KernelGmmu *pKernelGmmu, const struct GMMU_FMT *arg0, NvU64 arg1, NvU64 arg2, NvU64 arg3); @@ -1663,6 +1773,17 @@ #define kgmmuAccessCntrChangeIntrOwnership(pGpu, pKernelGmmu, arg0) kgmmuAccessCntrChangeIntrOwnership_IMPL(pGpu, pKernelGmmu, arg0) #endif //__nvoc_kern_gmmu_h_disabled +void *kgmmuGetShadowFaultBufferCslContext_IMPL(OBJGPU *pGpu, struct KernelGmmu *pKernelGmmu, FAULT_BUFFER_TYPE type); + +#ifdef __nvoc_kern_gmmu_h_disabled +static inline void *kgmmuGetShadowFaultBufferCslContext(OBJGPU *pGpu, struct KernelGmmu *pKernelGmmu, FAULT_BUFFER_TYPE type) { + NV_ASSERT_FAILED_PRECOMP("KernelGmmu was disabled!"); + return NULL; +} +#else //__nvoc_kern_gmmu_h_disabled +#define kgmmuGetShadowFaultBufferCslContext(pGpu, pKernelGmmu, type) kgmmuGetShadowFaultBufferCslContext_IMPL(pGpu, pKernelGmmu, type) +#endif //__nvoc_kern_gmmu_h_disabled + NvS32 *kgmmuGetFatalFaultIntrPendingState_IMPL(struct KernelGmmu *pKernelGmmu, NvU8 gfid); #ifdef __nvoc_kern_gmmu_h_disabled @@ -1685,6 +1806,17 @@ #define kgmmuGetHwFaultBufferPtr(pKernelGmmu, gfid, faultBufferIndex) kgmmuGetHwFaultBufferPtr_IMPL(pKernelGmmu, gfid, faultBufferIndex) #endif //__nvoc_kern_gmmu_h_disabled +NvU64 kgmmuGetFaultBufferGenCnt_IMPL(OBJGPU *pGpu, struct KernelGmmu *pKernelGmmu, NvU8 gfid); + +#ifdef __nvoc_kern_gmmu_h_disabled +static inline NvU64 kgmmuGetFaultBufferGenCnt(OBJGPU *pGpu, struct KernelGmmu *pKernelGmmu, NvU8 gfid) { + NV_ASSERT_FAILED_PRECOMP("KernelGmmu was disabled!"); + return 0; +} +#else //__nvoc_kern_gmmu_h_disabled +#define kgmmuGetFaultBufferGenCnt(pGpu, pKernelGmmu, gfid) kgmmuGetFaultBufferGenCnt_IMPL(pGpu, pKernelGmmu, gfid) +#endif //__nvoc_kern_gmmu_h_disabled + #undef PRIVATE_FIELD diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/generated/g_kern_mem_sys_nvoc.c nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_kern_mem_sys_nvoc.c --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/generated/g_kern_mem_sys_nvoc.c 2023-10-25 20:27:04.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_kern_mem_sys_nvoc.c 2024-03-05 22:18:23.000000000 +0000 @@ -78,12 +78,16 @@ return kmemsysStatePreLoad(pGpu, (struct KernelMemorySystem *)(((unsigned char *)pKernelMemorySystem) - __nvoc_rtti_KernelMemorySystem_OBJENGSTATE.offset), flags); } -static void __nvoc_thunk_KernelMemorySystem_engstateStateDestroy(OBJGPU *pGpu, struct OBJENGSTATE *pKernelMemorySystem) { - kmemsysStateDestroy(pGpu, (struct KernelMemorySystem *)(((unsigned char *)pKernelMemorySystem) - __nvoc_rtti_KernelMemorySystem_OBJENGSTATE.offset)); +static NV_STATUS __nvoc_thunk_KernelMemorySystem_engstateStatePostLoad(OBJGPU *pGpu, struct OBJENGSTATE *pKernelMemorySystem, NvU32 flags) { + return kmemsysStatePostLoad(pGpu, (struct KernelMemorySystem *)(((unsigned char *)pKernelMemorySystem) - __nvoc_rtti_KernelMemorySystem_OBJENGSTATE.offset), flags); +} + +static NV_STATUS __nvoc_thunk_KernelMemorySystem_engstateStatePreUnload(OBJGPU *pGpu, struct OBJENGSTATE *pKernelMemorySystem, NvU32 flags) { + return kmemsysStatePreUnload(pGpu, (struct KernelMemorySystem *)(((unsigned char *)pKernelMemorySystem) - __nvoc_rtti_KernelMemorySystem_OBJENGSTATE.offset), flags); } -static NV_STATUS __nvoc_thunk_OBJENGSTATE_kmemsysReconcileTunableState(POBJGPU pGpu, struct KernelMemorySystem *pEngstate, void *pTunableState) { - return engstateReconcileTunableState(pGpu, (struct OBJENGSTATE *)(((unsigned char *)pEngstate) + __nvoc_rtti_KernelMemorySystem_OBJENGSTATE.offset), pTunableState); +static void __nvoc_thunk_KernelMemorySystem_engstateStateDestroy(OBJGPU *pGpu, struct OBJENGSTATE *pKernelMemorySystem) { + kmemsysStateDestroy(pGpu, (struct KernelMemorySystem *)(((unsigned char *)pKernelMemorySystem) - __nvoc_rtti_KernelMemorySystem_OBJENGSTATE.offset)); } static NV_STATUS __nvoc_thunk_OBJENGSTATE_kmemsysStateLoad(POBJGPU pGpu, struct KernelMemorySystem *pEngstate, NvU32 arg0) { @@ -98,10 +102,6 @@ return engstateStatePostUnload(pGpu, (struct OBJENGSTATE *)(((unsigned char *)pEngstate) + __nvoc_rtti_KernelMemorySystem_OBJENGSTATE.offset), arg0); } -static NV_STATUS __nvoc_thunk_OBJENGSTATE_kmemsysStatePreUnload(POBJGPU pGpu, struct KernelMemorySystem *pEngstate, NvU32 arg0) { - return engstateStatePreUnload(pGpu, (struct OBJENGSTATE *)(((unsigned char *)pEngstate) + __nvoc_rtti_KernelMemorySystem_OBJENGSTATE.offset), arg0); -} - static NV_STATUS __nvoc_thunk_OBJENGSTATE_kmemsysStateInitUnlocked(POBJGPU pGpu, struct KernelMemorySystem *pEngstate) { return engstateStateInitUnlocked(pGpu, (struct OBJENGSTATE *)(((unsigned char *)pEngstate) + __nvoc_rtti_KernelMemorySystem_OBJENGSTATE.offset)); } @@ -118,30 +118,6 @@ return engstateStatePreInitUnlocked(pGpu, (struct OBJENGSTATE *)(((unsigned char *)pEngstate) + __nvoc_rtti_KernelMemorySystem_OBJENGSTATE.offset)); } -static NV_STATUS __nvoc_thunk_OBJENGSTATE_kmemsysGetTunableState(POBJGPU pGpu, struct KernelMemorySystem *pEngstate, void *pTunableState) { - return engstateGetTunableState(pGpu, (struct OBJENGSTATE *)(((unsigned char *)pEngstate) + __nvoc_rtti_KernelMemorySystem_OBJENGSTATE.offset), pTunableState); -} - -static NV_STATUS __nvoc_thunk_OBJENGSTATE_kmemsysCompareTunableState(POBJGPU pGpu, struct KernelMemorySystem *pEngstate, void *pTunables1, void *pTunables2) { - return engstateCompareTunableState(pGpu, (struct OBJENGSTATE *)(((unsigned char *)pEngstate) + __nvoc_rtti_KernelMemorySystem_OBJENGSTATE.offset), pTunables1, pTunables2); -} - -static void __nvoc_thunk_OBJENGSTATE_kmemsysFreeTunableState(POBJGPU pGpu, struct KernelMemorySystem *pEngstate, void *pTunableState) { - engstateFreeTunableState(pGpu, (struct OBJENGSTATE *)(((unsigned char *)pEngstate) + __nvoc_rtti_KernelMemorySystem_OBJENGSTATE.offset), pTunableState); -} - -static NV_STATUS __nvoc_thunk_OBJENGSTATE_kmemsysStatePostLoad(POBJGPU pGpu, struct KernelMemorySystem *pEngstate, NvU32 arg0) { - return engstateStatePostLoad(pGpu, (struct OBJENGSTATE *)(((unsigned char *)pEngstate) + __nvoc_rtti_KernelMemorySystem_OBJENGSTATE.offset), arg0); -} - -static NV_STATUS __nvoc_thunk_OBJENGSTATE_kmemsysAllocTunableState(POBJGPU pGpu, struct KernelMemorySystem *pEngstate, void **ppTunableState) { - return engstateAllocTunableState(pGpu, (struct OBJENGSTATE *)(((unsigned char *)pEngstate) + __nvoc_rtti_KernelMemorySystem_OBJENGSTATE.offset), ppTunableState); -} - -static NV_STATUS __nvoc_thunk_OBJENGSTATE_kmemsysSetTunableState(POBJGPU pGpu, struct KernelMemorySystem *pEngstate, void *pTunableState) { - return engstateSetTunableState(pGpu, (struct OBJENGSTATE *)(((unsigned char *)pEngstate) + __nvoc_rtti_KernelMemorySystem_OBJENGSTATE.offset), pTunableState); -} - static NvBool __nvoc_thunk_OBJENGSTATE_kmemsysIsPresent(POBJGPU pGpu, struct KernelMemorySystem *pEngstate) { return engstateIsPresent(pGpu, (struct OBJENGSTATE *)(((unsigned char *)pEngstate) + __nvoc_rtti_KernelMemorySystem_OBJENGSTATE.offset)); } @@ -194,6 +170,17 @@ // Hal field -- bPreserveComptagBackingStoreOnSuspend pThis->bPreserveComptagBackingStoreOnSuspend = ((NvBool)(0 != 0)); + + // Hal field -- bBug3656943WAR + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ + { + pThis->bBug3656943WAR = ((NvBool)(0 == 0)); + } + // default + else + { + pThis->bBug3656943WAR = ((NvBool)(0 != 0)); + } } NV_STATUS __nvoc_ctor_OBJENGSTATE(OBJENGSTATE* ); @@ -228,16 +215,20 @@ pThis->__kmemsysStatePreLoad__ = &kmemsysStatePreLoad_IMPL; + pThis->__kmemsysStatePostLoad__ = &kmemsysStatePostLoad_IMPL; + + pThis->__kmemsysStatePreUnload__ = &kmemsysStatePreUnload_IMPL; + pThis->__kmemsysStateDestroy__ = &kmemsysStateDestroy_IMPL; // Hal function -- kmemsysGetFbNumaInfo - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x11f0fc00UL) )) /* ChipHal: GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 | GH100 */ + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x000003e0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 */ { - pThis->__kmemsysGetFbNumaInfo__ = &kmemsysGetFbNumaInfo_GV100; + pThis->__kmemsysGetFbNumaInfo__ = &kmemsysGetFbNumaInfo_56cd7a; } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x000003e0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 */ + else { - pThis->__kmemsysGetFbNumaInfo__ = &kmemsysGetFbNumaInfo_56cd7a; + pThis->__kmemsysGetFbNumaInfo__ = &kmemsysGetFbNumaInfo_GV100; } // Hal function -- kmemsysReadUsableFbSize @@ -245,177 +236,228 @@ { pThis->__kmemsysReadUsableFbSize__ = &kmemsysReadUsableFbSize_GP102; } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x11f0f800UL) )) /* ChipHal: GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 | GH100 */ + else { pThis->__kmemsysReadUsableFbSize__ = &kmemsysReadUsableFbSize_GA102; } // Hal function -- kmemsysCacheOp - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x01f0ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 */ + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ { - pThis->__kmemsysCacheOp__ = &kmemsysCacheOp_GM200; + pThis->__kmemsysCacheOp__ = &kmemsysCacheOp_GH100; } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ + else { - pThis->__kmemsysCacheOp__ = &kmemsysCacheOp_GH100; + pThis->__kmemsysCacheOp__ = &kmemsysCacheOp_GM200; } // Hal function -- kmemsysDoCacheOp - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x01f0ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 */ + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ { - pThis->__kmemsysDoCacheOp__ = &kmemsysDoCacheOp_GM107; + pThis->__kmemsysDoCacheOp__ = &kmemsysDoCacheOp_GH100; } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ + else { - pThis->__kmemsysDoCacheOp__ = &kmemsysDoCacheOp_GH100; + pThis->__kmemsysDoCacheOp__ = &kmemsysDoCacheOp_GM107; } // Hal function -- kmemsysReadL2SysmemInvalidateReg - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x01f0ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 */ + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ { - pThis->__kmemsysReadL2SysmemInvalidateReg__ = &kmemsysReadL2SysmemInvalidateReg_TU102; + pThis->__kmemsysReadL2SysmemInvalidateReg__ = &kmemsysReadL2SysmemInvalidateReg_68b109; } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ + else { - pThis->__kmemsysReadL2SysmemInvalidateReg__ = &kmemsysReadL2SysmemInvalidateReg_68b109; + pThis->__kmemsysReadL2SysmemInvalidateReg__ = &kmemsysReadL2SysmemInvalidateReg_TU102; } // Hal function -- kmemsysWriteL2SysmemInvalidateReg - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x01f0ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 */ + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ { - pThis->__kmemsysWriteL2SysmemInvalidateReg__ = &kmemsysWriteL2SysmemInvalidateReg_TU102; + pThis->__kmemsysWriteL2SysmemInvalidateReg__ = &kmemsysWriteL2SysmemInvalidateReg_f2d351; } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ + else { - pThis->__kmemsysWriteL2SysmemInvalidateReg__ = &kmemsysWriteL2SysmemInvalidateReg_f2d351; + pThis->__kmemsysWriteL2SysmemInvalidateReg__ = &kmemsysWriteL2SysmemInvalidateReg_TU102; } // Hal function -- kmemsysReadL2PeermemInvalidateReg - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x01f0ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 */ + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ { - pThis->__kmemsysReadL2PeermemInvalidateReg__ = &kmemsysReadL2PeermemInvalidateReg_TU102; + pThis->__kmemsysReadL2PeermemInvalidateReg__ = &kmemsysReadL2PeermemInvalidateReg_68b109; } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ + else { - pThis->__kmemsysReadL2PeermemInvalidateReg__ = &kmemsysReadL2PeermemInvalidateReg_68b109; + pThis->__kmemsysReadL2PeermemInvalidateReg__ = &kmemsysReadL2PeermemInvalidateReg_TU102; } // Hal function -- kmemsysWriteL2PeermemInvalidateReg - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x01f0ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 */ + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ { - pThis->__kmemsysWriteL2PeermemInvalidateReg__ = &kmemsysWriteL2PeermemInvalidateReg_TU102; + pThis->__kmemsysWriteL2PeermemInvalidateReg__ = &kmemsysWriteL2PeermemInvalidateReg_f2d351; } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ + else { - pThis->__kmemsysWriteL2PeermemInvalidateReg__ = &kmemsysWriteL2PeermemInvalidateReg_f2d351; + pThis->__kmemsysWriteL2PeermemInvalidateReg__ = &kmemsysWriteL2PeermemInvalidateReg_TU102; } // Hal function -- kmemsysInitFlushSysmemBuffer - if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000002UL) )) /* RmVariantHal: PF_KERNEL_ONLY */ + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x000003e0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 */ + { + pThis->__kmemsysInitFlushSysmemBuffer__ = &kmemsysInitFlushSysmemBuffer_GM107; + } + else { - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x000003e0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 */ - { - pThis->__kmemsysInitFlushSysmemBuffer__ = &kmemsysInitFlushSysmemBuffer_GM107; - } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x11f0fc00UL) )) /* ChipHal: GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 | GH100 */ - { - pThis->__kmemsysInitFlushSysmemBuffer__ = &kmemsysInitFlushSysmemBuffer_GA100; - } + pThis->__kmemsysInitFlushSysmemBuffer__ = &kmemsysInitFlushSysmemBuffer_GA100; } // Hal function -- kmemsysProgramSysmemFlushBuffer - if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000002UL) )) /* RmVariantHal: PF_KERNEL_ONLY */ + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ + { + pThis->__kmemsysProgramSysmemFlushBuffer__ = &kmemsysProgramSysmemFlushBuffer_GH100; + } + else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x000003e0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 */ { - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x000003e0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 */ - { - pThis->__kmemsysProgramSysmemFlushBuffer__ = &kmemsysProgramSysmemFlushBuffer_GM107; - } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x01f0fc00UL) )) /* ChipHal: GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 */ - { - pThis->__kmemsysProgramSysmemFlushBuffer__ = &kmemsysProgramSysmemFlushBuffer_GA100; - } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ - { - pThis->__kmemsysProgramSysmemFlushBuffer__ = &kmemsysProgramSysmemFlushBuffer_GH100; - } + pThis->__kmemsysProgramSysmemFlushBuffer__ = &kmemsysProgramSysmemFlushBuffer_GM107; + } + else + { + pThis->__kmemsysProgramSysmemFlushBuffer__ = &kmemsysProgramSysmemFlushBuffer_GA100; } // Hal function -- kmemsysIsPagePLCable - if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000002UL) )) /* RmVariantHal: PF_KERNEL_ONLY */ + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x00000400UL) )) /* ChipHal: GA100 */ + { + pThis->__kmemsysIsPagePLCable__ = &kmemsysIsPagePLCable_GA100; + } + else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0000f800UL) )) /* ChipHal: GA102 | GA103 | GA104 | GA106 | GA107 */ { - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x00000400UL) )) /* ChipHal: GA100 */ - { - pThis->__kmemsysIsPagePLCable__ = &kmemsysIsPagePLCable_GA100; - } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0000f800UL) )) /* ChipHal: GA102 | GA103 | GA104 | GA106 | GA107 */ - { - pThis->__kmemsysIsPagePLCable__ = &kmemsysIsPagePLCable_GA102; - } - // default - else - { - pThis->__kmemsysIsPagePLCable__ = &kmemsysIsPagePLCable_510167; - } + pThis->__kmemsysIsPagePLCable__ = &kmemsysIsPagePLCable_GA102; + } + // default + else + { + pThis->__kmemsysIsPagePLCable__ = &kmemsysIsPagePLCable_510167; } // Hal function -- kmemsysReadMIGMemoryCfg - if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000002UL) )) /* RmVariantHal: PF_KERNEL_ONLY */ + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x11f0fc00UL) )) /* ChipHal: GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 | GH100 */ { - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x11f0fc00UL) )) /* ChipHal: GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 | GH100 */ - { - pThis->__kmemsysReadMIGMemoryCfg__ = &kmemsysReadMIGMemoryCfg_GA100; - } - // default - else - { - pThis->__kmemsysReadMIGMemoryCfg__ = &kmemsysReadMIGMemoryCfg_46f6a7; - } + pThis->__kmemsysReadMIGMemoryCfg__ = &kmemsysReadMIGMemoryCfg_GA100; + } + // default + else + { + pThis->__kmemsysReadMIGMemoryCfg__ = &kmemsysReadMIGMemoryCfg_46f6a7; } // Hal function -- kmemsysInitMIGMemoryPartitionTable - if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000002UL) )) /* RmVariantHal: PF_KERNEL_ONLY */ + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x00000400UL) )) /* ChipHal: GA100 */ + { + pThis->__kmemsysInitMIGMemoryPartitionTable__ = &kmemsysInitMIGMemoryPartitionTable_GA100; + } + // default + else { - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x00000400UL) )) /* ChipHal: GA100 */ - { - pThis->__kmemsysInitMIGMemoryPartitionTable__ = &kmemsysInitMIGMemoryPartitionTable_GA100; - } - // default - else - { - pThis->__kmemsysInitMIGMemoryPartitionTable__ = &kmemsysInitMIGMemoryPartitionTable_56cd7a; - } + pThis->__kmemsysInitMIGMemoryPartitionTable__ = &kmemsysInitMIGMemoryPartitionTable_56cd7a; } // Hal function -- kmemsysSwizzIdToVmmuSegmentsRange - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x01f0ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 */ + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ + { + pThis->__kmemsysSwizzIdToVmmuSegmentsRange__ = &kmemsysSwizzIdToVmmuSegmentsRange_GH100; + } + else { pThis->__kmemsysSwizzIdToVmmuSegmentsRange__ = &kmemsysSwizzIdToVmmuSegmentsRange_GA100; } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ + + // Hal function -- kmemsysNumaAddMemory + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ + { + pThis->__kmemsysNumaAddMemory__ = &kmemsysNumaAddMemory_GH100; + } + // default + else { - pThis->__kmemsysSwizzIdToVmmuSegmentsRange__ = &kmemsysSwizzIdToVmmuSegmentsRange_GH100; + pThis->__kmemsysNumaAddMemory__ = &kmemsysNumaAddMemory_56cd7a; } - // Hal function -- kmemsysCheckEccCounts + // Hal function -- kmemsysNumaRemoveMemory if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ { - pThis->__kmemsysCheckEccCounts__ = &kmemsysCheckEccCounts_GH100; + pThis->__kmemsysNumaRemoveMemory__ = &kmemsysNumaRemoveMemory_GH100; } // default else { - pThis->__kmemsysCheckEccCounts__ = &kmemsysCheckEccCounts_b3696a; + pThis->__kmemsysNumaRemoveMemory__ = &kmemsysNumaRemoveMemory_b3696a; } - // Hal function -- kmemsysClearEccCounts + // Hal function -- kmemsysNumaRemoveAllMemory if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ { - pThis->__kmemsysClearEccCounts__ = &kmemsysClearEccCounts_GH100; + pThis->__kmemsysNumaRemoveAllMemory__ = &kmemsysNumaRemoveAllMemory_GH100; + } + // default + else + { + pThis->__kmemsysNumaRemoveAllMemory__ = &kmemsysNumaRemoveAllMemory_b3696a; + } + + // Hal function -- kmemsysSetupAllAtsPeers + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x000003e0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 */ + { + pThis->__kmemsysSetupAllAtsPeers__ = &kmemsysSetupAllAtsPeers_46f6a7; + } + else + { + pThis->__kmemsysSetupAllAtsPeers__ = &kmemsysSetupAllAtsPeers_GV100; + } + + // Hal function -- kmemsysRemoveAllAtsPeers + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x000003e0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 */ + { + pThis->__kmemsysRemoveAllAtsPeers__ = &kmemsysRemoveAllAtsPeers_b3696a; + } + else + { + pThis->__kmemsysRemoveAllAtsPeers__ = &kmemsysRemoveAllAtsPeers_GV100; + } + + // Hal function -- kmemsysGetMaxFbpas + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000400UL) )) /* ChipHal: GA100 | GH100 */ + { + pThis->__kmemsysGetMaxFbpas__ = &kmemsysGetMaxFbpas_GA100; + } + else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x000003e0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 */ + { + pThis->__kmemsysGetMaxFbpas__ = &kmemsysGetMaxFbpas_TU102; } // default else { - pThis->__kmemsysClearEccCounts__ = &kmemsysClearEccCounts_56cd7a; + pThis->__kmemsysGetMaxFbpas__ = &kmemsysGetMaxFbpas_4a4dee; + } + + // Hal function -- kmemsysGetEccDedCountSize + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ + { + pThis->__kmemsysGetEccDedCountSize__ = &kmemsysGetEccDedCountSize_GH100; + } + else + { + pThis->__kmemsysGetEccDedCountSize__ = &kmemsysGetEccDedCountSize_TU102; + } + + // Hal function -- kmemsysGetEccDedCountRegAddr + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ + { + pThis->__kmemsysGetEccDedCountRegAddr__ = &kmemsysGetEccDedCountRegAddr_GH100; + } + else + { + pThis->__kmemsysGetEccDedCountRegAddr__ = &kmemsysGetEccDedCountRegAddr_TU102; } pThis->__nvoc_base_OBJENGSTATE.__engstateConstructEngine__ = &__nvoc_thunk_KernelMemorySystem_engstateConstructEngine; @@ -424,9 +466,11 @@ pThis->__nvoc_base_OBJENGSTATE.__engstateStatePreLoad__ = &__nvoc_thunk_KernelMemorySystem_engstateStatePreLoad; - pThis->__nvoc_base_OBJENGSTATE.__engstateStateDestroy__ = &__nvoc_thunk_KernelMemorySystem_engstateStateDestroy; + pThis->__nvoc_base_OBJENGSTATE.__engstateStatePostLoad__ = &__nvoc_thunk_KernelMemorySystem_engstateStatePostLoad; - pThis->__kmemsysReconcileTunableState__ = &__nvoc_thunk_OBJENGSTATE_kmemsysReconcileTunableState; + pThis->__nvoc_base_OBJENGSTATE.__engstateStatePreUnload__ = &__nvoc_thunk_KernelMemorySystem_engstateStatePreUnload; + + pThis->__nvoc_base_OBJENGSTATE.__engstateStateDestroy__ = &__nvoc_thunk_KernelMemorySystem_engstateStateDestroy; pThis->__kmemsysStateLoad__ = &__nvoc_thunk_OBJENGSTATE_kmemsysStateLoad; @@ -434,8 +478,6 @@ pThis->__kmemsysStatePostUnload__ = &__nvoc_thunk_OBJENGSTATE_kmemsysStatePostUnload; - pThis->__kmemsysStatePreUnload__ = &__nvoc_thunk_OBJENGSTATE_kmemsysStatePreUnload; - pThis->__kmemsysStateInitUnlocked__ = &__nvoc_thunk_OBJENGSTATE_kmemsysStateInitUnlocked; pThis->__kmemsysInitMissing__ = &__nvoc_thunk_OBJENGSTATE_kmemsysInitMissing; @@ -444,18 +486,6 @@ pThis->__kmemsysStatePreInitUnlocked__ = &__nvoc_thunk_OBJENGSTATE_kmemsysStatePreInitUnlocked; - pThis->__kmemsysGetTunableState__ = &__nvoc_thunk_OBJENGSTATE_kmemsysGetTunableState; - - pThis->__kmemsysCompareTunableState__ = &__nvoc_thunk_OBJENGSTATE_kmemsysCompareTunableState; - - pThis->__kmemsysFreeTunableState__ = &__nvoc_thunk_OBJENGSTATE_kmemsysFreeTunableState; - - pThis->__kmemsysStatePostLoad__ = &__nvoc_thunk_OBJENGSTATE_kmemsysStatePostLoad; - - pThis->__kmemsysAllocTunableState__ = &__nvoc_thunk_OBJENGSTATE_kmemsysAllocTunableState; - - pThis->__kmemsysSetTunableState__ = &__nvoc_thunk_OBJENGSTATE_kmemsysSetTunableState; - pThis->__kmemsysIsPresent__ = &__nvoc_thunk_OBJENGSTATE_kmemsysIsPresent; } @@ -478,13 +508,16 @@ KernelMemorySystem *pThis; RmHalspecOwner *pRmhalspecowner; - pThis = portMemAllocNonPaged(sizeof(KernelMemorySystem)); - if (pThis == NULL) return NV_ERR_NO_MEMORY; + status = __nvoc_handleObjCreateMemAlloc(createFlags, sizeof(KernelMemorySystem), (void**)&pThis, (void**)ppThis); + if (status != NV_OK) + return status; portMemSet(pThis, 0, sizeof(KernelMemorySystem)); __nvoc_initRtti(staticCast(pThis, Dynamic), &__nvoc_class_def_KernelMemorySystem); + pThis->__nvoc_base_OBJENGSTATE.__nvoc_base_Object.createFlags = createFlags; + if (pParent != NULL && !(createFlags & NVOC_OBJ_CREATE_FLAGS_PARENT_HALSPEC_ONLY)) { pParentObj = dynamicCast(pParent, Object); @@ -504,11 +537,17 @@ if (status != NV_OK) goto __nvoc_objCreate_KernelMemorySystem_cleanup; *ppThis = pThis; + return NV_OK; __nvoc_objCreate_KernelMemorySystem_cleanup: // do not call destructors here since the constructor already called them - portMemFree(pThis); + if (createFlags & NVOC_OBJ_CREATE_FLAGS_IN_PLACE_CONSTRUCT) + portMemSet(pThis, 0, sizeof(KernelMemorySystem)); + else + portMemFree(pThis); + + // coverity[leaked_storage:FALSE] return status; } diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/generated/g_kern_mem_sys_nvoc.h nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_kern_mem_sys_nvoc.h --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/generated/g_kern_mem_sys_nvoc.h 2023-10-25 20:27:04.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_kern_mem_sys_nvoc.h 2024-03-05 22:18:23.000000000 +0000 @@ -7,7 +7,7 @@ #endif /* - * SPDX-FileCopyrightText: Copyright (c) 1993-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 1993-2024 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -28,7 +28,7 @@ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * DEALINGS IN THE SOFTWARE. */ - + #include "g_kern_mem_sys_nvoc.h" #ifndef KERN_MEM_SYS_H @@ -157,7 +157,7 @@ #define FB_HWRESID_CTAGID_NUM_FERMI(i) \ (((i) & DRF_MASK(FB_HWRESID_CTAGID_FERMI)) << DRF_SHIFT(FB_HWRESID_CTAGID_FERMI)) -#define FB_SET_HWRESID_CTAGID_FERMI(h, i) \ +#define FB_SET_HWRESID_CTAGID_FERMI(h, i) \ h = ( ((h) & ~(DRF_MASK(FB_HWRESID_CTAGID_FERMI) << DRF_SHIFT(FB_HWRESID_CTAGID_FERMI))) | \ FB_HWRESID_CTAGID_NUM_FERMI(i) ) @@ -200,6 +200,8 @@ NV_STATUS (*__kmemsysConstructEngine__)(OBJGPU *, struct KernelMemorySystem *, ENGDESCRIPTOR); NV_STATUS (*__kmemsysStateInitLocked__)(OBJGPU *, struct KernelMemorySystem *); NV_STATUS (*__kmemsysStatePreLoad__)(OBJGPU *, struct KernelMemorySystem *, NvU32); + NV_STATUS (*__kmemsysStatePostLoad__)(OBJGPU *, struct KernelMemorySystem *, NvU32); + NV_STATUS (*__kmemsysStatePreUnload__)(OBJGPU *, struct KernelMemorySystem *, NvU32); void (*__kmemsysStateDestroy__)(OBJGPU *, struct KernelMemorySystem *); NV_STATUS (*__kmemsysGetFbNumaInfo__)(OBJGPU *, struct KernelMemorySystem *, NvU64 *, NvS32 *); NV_STATUS (*__kmemsysReadUsableFbSize__)(OBJGPU *, struct KernelMemorySystem *, NvU64 *); @@ -215,29 +217,28 @@ NV_STATUS (*__kmemsysReadMIGMemoryCfg__)(OBJGPU *, struct KernelMemorySystem *); NV_STATUS (*__kmemsysInitMIGMemoryPartitionTable__)(OBJGPU *, struct KernelMemorySystem *); NV_STATUS (*__kmemsysSwizzIdToVmmuSegmentsRange__)(OBJGPU *, struct KernelMemorySystem *, NvU32, NvU32, NvU32); - void (*__kmemsysCheckEccCounts__)(OBJGPU *, struct KernelMemorySystem *); - NV_STATUS (*__kmemsysClearEccCounts__)(OBJGPU *, struct KernelMemorySystem *); - NV_STATUS (*__kmemsysReconcileTunableState__)(POBJGPU, struct KernelMemorySystem *, void *); + NV_STATUS (*__kmemsysNumaAddMemory__)(OBJGPU *, struct KernelMemorySystem *, NvU32, NvU64, NvU64, NvS32 *); + void (*__kmemsysNumaRemoveMemory__)(OBJGPU *, struct KernelMemorySystem *, NvU32); + void (*__kmemsysNumaRemoveAllMemory__)(OBJGPU *, struct KernelMemorySystem *); + NV_STATUS (*__kmemsysSetupAllAtsPeers__)(OBJGPU *, struct KernelMemorySystem *); + void (*__kmemsysRemoveAllAtsPeers__)(OBJGPU *, struct KernelMemorySystem *); + NvU32 (*__kmemsysGetMaxFbpas__)(OBJGPU *, struct KernelMemorySystem *); + NvU32 (*__kmemsysGetEccDedCountSize__)(OBJGPU *, struct KernelMemorySystem *); + NvU32 (*__kmemsysGetEccDedCountRegAddr__)(OBJGPU *, struct KernelMemorySystem *, NvU32, NvU32); NV_STATUS (*__kmemsysStateLoad__)(POBJGPU, struct KernelMemorySystem *, NvU32); NV_STATUS (*__kmemsysStateUnload__)(POBJGPU, struct KernelMemorySystem *, NvU32); NV_STATUS (*__kmemsysStatePostUnload__)(POBJGPU, struct KernelMemorySystem *, NvU32); - NV_STATUS (*__kmemsysStatePreUnload__)(POBJGPU, struct KernelMemorySystem *, NvU32); NV_STATUS (*__kmemsysStateInitUnlocked__)(POBJGPU, struct KernelMemorySystem *); void (*__kmemsysInitMissing__)(POBJGPU, struct KernelMemorySystem *); NV_STATUS (*__kmemsysStatePreInitLocked__)(POBJGPU, struct KernelMemorySystem *); NV_STATUS (*__kmemsysStatePreInitUnlocked__)(POBJGPU, struct KernelMemorySystem *); - NV_STATUS (*__kmemsysGetTunableState__)(POBJGPU, struct KernelMemorySystem *, void *); - NV_STATUS (*__kmemsysCompareTunableState__)(POBJGPU, struct KernelMemorySystem *, void *, void *); - void (*__kmemsysFreeTunableState__)(POBJGPU, struct KernelMemorySystem *, void *); - NV_STATUS (*__kmemsysStatePostLoad__)(POBJGPU, struct KernelMemorySystem *, NvU32); - NV_STATUS (*__kmemsysAllocTunableState__)(POBJGPU, struct KernelMemorySystem *, void **); - NV_STATUS (*__kmemsysSetTunableState__)(POBJGPU, struct KernelMemorySystem *, void *); NvBool (*__kmemsysIsPresent__)(POBJGPU, struct KernelMemorySystem *); NvBool bDisableTiledCachingInvalidatesWithEccBug1521641; NvBool bGpuCacheEnable; NvBool bNumaNodesAdded; NvBool bL2CleanFbPull; NvBool bPreserveComptagBackingStoreOnSuspend; + NvBool bBug3656943WAR; const MEMORY_SYSTEM_STATIC_CONFIG *pStaticConfig; MEM_PARTITION_NUMA_INFO *memPartitionNumaInfo; MIG_MEM_BOUNDARY_CONFIG_TABLE memBoundaryCfgTable; @@ -249,6 +250,8 @@ NvU64 coherentCpuFbEnd; NvU64 numaOnlineBase; NvU64 numaOnlineSize; + NvU64 numaMigPartitionSize[15]; + NvBool bNumaMigPartitionSizeEnumerated; }; #ifndef __NVOC_CLASS_KernelMemorySystem_TYPEDEF__ @@ -284,6 +287,8 @@ #define kmemsysConstructEngine(pGpu, pKernelMemorySystem, arg0) kmemsysConstructEngine_DISPATCH(pGpu, pKernelMemorySystem, arg0) #define kmemsysStateInitLocked(pGpu, pKernelMemorySystem) kmemsysStateInitLocked_DISPATCH(pGpu, pKernelMemorySystem) #define kmemsysStatePreLoad(pGpu, pKernelMemorySystem, flags) kmemsysStatePreLoad_DISPATCH(pGpu, pKernelMemorySystem, flags) +#define kmemsysStatePostLoad(pGpu, pKernelMemorySystem, flags) kmemsysStatePostLoad_DISPATCH(pGpu, pKernelMemorySystem, flags) +#define kmemsysStatePreUnload(pGpu, pKernelMemorySystem, flags) kmemsysStatePreUnload_DISPATCH(pGpu, pKernelMemorySystem, flags) #define kmemsysStateDestroy(pGpu, pKernelMemorySystem) kmemsysStateDestroy_DISPATCH(pGpu, pKernelMemorySystem) #define kmemsysGetFbNumaInfo(pGpu, pKernelMemorySystem, physAddr, numaNodeId) kmemsysGetFbNumaInfo_DISPATCH(pGpu, pKernelMemorySystem, physAddr, numaNodeId) #define kmemsysGetFbNumaInfo_HAL(pGpu, pKernelMemorySystem, physAddr, numaNodeId) kmemsysGetFbNumaInfo_DISPATCH(pGpu, pKernelMemorySystem, physAddr, numaNodeId) @@ -313,25 +318,29 @@ #define kmemsysInitMIGMemoryPartitionTable_HAL(pGpu, pKernelMemorySystem) kmemsysInitMIGMemoryPartitionTable_DISPATCH(pGpu, pKernelMemorySystem) #define kmemsysSwizzIdToVmmuSegmentsRange(pGpu, pKernelMemorySystem, swizzId, vmmuSegmentSize, totalVmmuSegments) kmemsysSwizzIdToVmmuSegmentsRange_DISPATCH(pGpu, pKernelMemorySystem, swizzId, vmmuSegmentSize, totalVmmuSegments) #define kmemsysSwizzIdToVmmuSegmentsRange_HAL(pGpu, pKernelMemorySystem, swizzId, vmmuSegmentSize, totalVmmuSegments) kmemsysSwizzIdToVmmuSegmentsRange_DISPATCH(pGpu, pKernelMemorySystem, swizzId, vmmuSegmentSize, totalVmmuSegments) -#define kmemsysCheckEccCounts(pGpu, pKernelMemorySystem) kmemsysCheckEccCounts_DISPATCH(pGpu, pKernelMemorySystem) -#define kmemsysCheckEccCounts_HAL(pGpu, pKernelMemorySystem) kmemsysCheckEccCounts_DISPATCH(pGpu, pKernelMemorySystem) -#define kmemsysClearEccCounts(pGpu, pKernelMemorySystem) kmemsysClearEccCounts_DISPATCH(pGpu, pKernelMemorySystem) -#define kmemsysClearEccCounts_HAL(pGpu, pKernelMemorySystem) kmemsysClearEccCounts_DISPATCH(pGpu, pKernelMemorySystem) -#define kmemsysReconcileTunableState(pGpu, pEngstate, pTunableState) kmemsysReconcileTunableState_DISPATCH(pGpu, pEngstate, pTunableState) +#define kmemsysNumaAddMemory(pGpu, pKernelMemorySystem, swizzId, offset, size, numaNodeId) kmemsysNumaAddMemory_DISPATCH(pGpu, pKernelMemorySystem, swizzId, offset, size, numaNodeId) +#define kmemsysNumaAddMemory_HAL(pGpu, pKernelMemorySystem, swizzId, offset, size, numaNodeId) kmemsysNumaAddMemory_DISPATCH(pGpu, pKernelMemorySystem, swizzId, offset, size, numaNodeId) +#define kmemsysNumaRemoveMemory(pGpu, pKernelMemorySystem, swizzId) kmemsysNumaRemoveMemory_DISPATCH(pGpu, pKernelMemorySystem, swizzId) +#define kmemsysNumaRemoveMemory_HAL(pGpu, pKernelMemorySystem, swizzId) kmemsysNumaRemoveMemory_DISPATCH(pGpu, pKernelMemorySystem, swizzId) +#define kmemsysNumaRemoveAllMemory(pGpu, pKernelMemorySystem) kmemsysNumaRemoveAllMemory_DISPATCH(pGpu, pKernelMemorySystem) +#define kmemsysNumaRemoveAllMemory_HAL(pGpu, pKernelMemorySystem) kmemsysNumaRemoveAllMemory_DISPATCH(pGpu, pKernelMemorySystem) +#define kmemsysSetupAllAtsPeers(pGpu, pKernelMemorySystem) kmemsysSetupAllAtsPeers_DISPATCH(pGpu, pKernelMemorySystem) +#define kmemsysSetupAllAtsPeers_HAL(pGpu, pKernelMemorySystem) kmemsysSetupAllAtsPeers_DISPATCH(pGpu, pKernelMemorySystem) +#define kmemsysRemoveAllAtsPeers(pGpu, pKernelMemorySystem) kmemsysRemoveAllAtsPeers_DISPATCH(pGpu, pKernelMemorySystem) +#define kmemsysRemoveAllAtsPeers_HAL(pGpu, pKernelMemorySystem) kmemsysRemoveAllAtsPeers_DISPATCH(pGpu, pKernelMemorySystem) +#define kmemsysGetMaxFbpas(pGpu, pKernelMemorySystem) kmemsysGetMaxFbpas_DISPATCH(pGpu, pKernelMemorySystem) +#define kmemsysGetMaxFbpas_HAL(pGpu, pKernelMemorySystem) kmemsysGetMaxFbpas_DISPATCH(pGpu, pKernelMemorySystem) +#define kmemsysGetEccDedCountSize(pGpu, pKernelMemorySystem) kmemsysGetEccDedCountSize_DISPATCH(pGpu, pKernelMemorySystem) +#define kmemsysGetEccDedCountSize_HAL(pGpu, pKernelMemorySystem) kmemsysGetEccDedCountSize_DISPATCH(pGpu, pKernelMemorySystem) +#define kmemsysGetEccDedCountRegAddr(pGpu, pKernelMemorySystem, fbpa, subp) kmemsysGetEccDedCountRegAddr_DISPATCH(pGpu, pKernelMemorySystem, fbpa, subp) +#define kmemsysGetEccDedCountRegAddr_HAL(pGpu, pKernelMemorySystem, fbpa, subp) kmemsysGetEccDedCountRegAddr_DISPATCH(pGpu, pKernelMemorySystem, fbpa, subp) #define kmemsysStateLoad(pGpu, pEngstate, arg0) kmemsysStateLoad_DISPATCH(pGpu, pEngstate, arg0) #define kmemsysStateUnload(pGpu, pEngstate, arg0) kmemsysStateUnload_DISPATCH(pGpu, pEngstate, arg0) #define kmemsysStatePostUnload(pGpu, pEngstate, arg0) kmemsysStatePostUnload_DISPATCH(pGpu, pEngstate, arg0) -#define kmemsysStatePreUnload(pGpu, pEngstate, arg0) kmemsysStatePreUnload_DISPATCH(pGpu, pEngstate, arg0) #define kmemsysStateInitUnlocked(pGpu, pEngstate) kmemsysStateInitUnlocked_DISPATCH(pGpu, pEngstate) #define kmemsysInitMissing(pGpu, pEngstate) kmemsysInitMissing_DISPATCH(pGpu, pEngstate) #define kmemsysStatePreInitLocked(pGpu, pEngstate) kmemsysStatePreInitLocked_DISPATCH(pGpu, pEngstate) #define kmemsysStatePreInitUnlocked(pGpu, pEngstate) kmemsysStatePreInitUnlocked_DISPATCH(pGpu, pEngstate) -#define kmemsysGetTunableState(pGpu, pEngstate, pTunableState) kmemsysGetTunableState_DISPATCH(pGpu, pEngstate, pTunableState) -#define kmemsysCompareTunableState(pGpu, pEngstate, pTunables1, pTunables2) kmemsysCompareTunableState_DISPATCH(pGpu, pEngstate, pTunables1, pTunables2) -#define kmemsysFreeTunableState(pGpu, pEngstate, pTunableState) kmemsysFreeTunableState_DISPATCH(pGpu, pEngstate, pTunableState) -#define kmemsysStatePostLoad(pGpu, pEngstate, arg0) kmemsysStatePostLoad_DISPATCH(pGpu, pEngstate, arg0) -#define kmemsysAllocTunableState(pGpu, pEngstate, ppTunableState) kmemsysAllocTunableState_DISPATCH(pGpu, pEngstate, ppTunableState) -#define kmemsysSetTunableState(pGpu, pEngstate, pTunableState) kmemsysSetTunableState_DISPATCH(pGpu, pEngstate, pTunableState) #define kmemsysIsPresent(pGpu, pEngstate) kmemsysIsPresent_DISPATCH(pGpu, pEngstate) NV_STATUS kmemsysGetUsableFbSize_KERNEL(OBJGPU *pGpu, struct KernelMemorySystem *pKernelMemorySystem, NvU64 *pFbSize); @@ -503,6 +512,33 @@ #define kmemsysPopulateMIGGPUInstanceMemConfig_HAL(pGpu, pKernelMemorySystem) kmemsysPopulateMIGGPUInstanceMemConfig(pGpu, pKernelMemorySystem) +NvBool kmemsysNeedInvalidateGpuCacheOnMap_GV100(OBJGPU *pGpu, struct KernelMemorySystem *pKernelMemorySystem, NvBool bIsVolatile, NvU32 aperture); + + +#ifdef __nvoc_kern_mem_sys_h_disabled +static inline NvBool kmemsysNeedInvalidateGpuCacheOnMap(OBJGPU *pGpu, struct KernelMemorySystem *pKernelMemorySystem, NvBool bIsVolatile, NvU32 aperture) { + NV_ASSERT_FAILED_PRECOMP("KernelMemorySystem was disabled!"); + return NV_FALSE; +} +#else //__nvoc_kern_mem_sys_h_disabled +#define kmemsysNeedInvalidateGpuCacheOnMap(pGpu, pKernelMemorySystem, bIsVolatile, aperture) kmemsysNeedInvalidateGpuCacheOnMap_GV100(pGpu, pKernelMemorySystem, bIsVolatile, aperture) +#endif //__nvoc_kern_mem_sys_h_disabled + +#define kmemsysNeedInvalidateGpuCacheOnMap_HAL(pGpu, pKernelMemorySystem, bIsVolatile, aperture) kmemsysNeedInvalidateGpuCacheOnMap(pGpu, pKernelMemorySystem, bIsVolatile, aperture) + +void kmemsysGetEccCounts_TU102(OBJGPU *pGpu, struct KernelMemorySystem *pKernelMemorySystem, NvU32 *arg0, NvU32 *arg1); + + +#ifdef __nvoc_kern_mem_sys_h_disabled +static inline void kmemsysGetEccCounts(OBJGPU *pGpu, struct KernelMemorySystem *pKernelMemorySystem, NvU32 *arg0, NvU32 *arg1) { + NV_ASSERT_FAILED_PRECOMP("KernelMemorySystem was disabled!"); +} +#else //__nvoc_kern_mem_sys_h_disabled +#define kmemsysGetEccCounts(pGpu, pKernelMemorySystem, arg0, arg1) kmemsysGetEccCounts_TU102(pGpu, pKernelMemorySystem, arg0, arg1) +#endif //__nvoc_kern_mem_sys_h_disabled + +#define kmemsysGetEccCounts_HAL(pGpu, pKernelMemorySystem, arg0, arg1) kmemsysGetEccCounts(pGpu, pKernelMemorySystem, arg0, arg1) + NV_STATUS kmemsysConstructEngine_IMPL(OBJGPU *pGpu, struct KernelMemorySystem *pKernelMemorySystem, ENGDESCRIPTOR arg0); static inline NV_STATUS kmemsysConstructEngine_DISPATCH(OBJGPU *pGpu, struct KernelMemorySystem *pKernelMemorySystem, ENGDESCRIPTOR arg0) { @@ -521,6 +557,18 @@ return pKernelMemorySystem->__kmemsysStatePreLoad__(pGpu, pKernelMemorySystem, flags); } +NV_STATUS kmemsysStatePostLoad_IMPL(OBJGPU *pGpu, struct KernelMemorySystem *pKernelMemorySystem, NvU32 flags); + +static inline NV_STATUS kmemsysStatePostLoad_DISPATCH(OBJGPU *pGpu, struct KernelMemorySystem *pKernelMemorySystem, NvU32 flags) { + return pKernelMemorySystem->__kmemsysStatePostLoad__(pGpu, pKernelMemorySystem, flags); +} + +NV_STATUS kmemsysStatePreUnload_IMPL(OBJGPU *pGpu, struct KernelMemorySystem *pKernelMemorySystem, NvU32 flags); + +static inline NV_STATUS kmemsysStatePreUnload_DISPATCH(OBJGPU *pGpu, struct KernelMemorySystem *pKernelMemorySystem, NvU32 flags) { + return pKernelMemorySystem->__kmemsysStatePreUnload__(pGpu, pKernelMemorySystem, flags); +} + void kmemsysStateDestroy_IMPL(OBJGPU *pGpu, struct KernelMemorySystem *pKernelMemorySystem); static inline void kmemsysStateDestroy_DISPATCH(OBJGPU *pGpu, struct KernelMemorySystem *pKernelMemorySystem) { @@ -659,84 +707,110 @@ return pKernelMemorySystem->__kmemsysSwizzIdToVmmuSegmentsRange__(pGpu, pKernelMemorySystem, swizzId, vmmuSegmentSize, totalVmmuSegments); } -void kmemsysCheckEccCounts_GH100(OBJGPU *pGpu, struct KernelMemorySystem *pKernelMemorySystem); +NV_STATUS kmemsysNumaAddMemory_GH100(OBJGPU *pGpu, struct KernelMemorySystem *pKernelMemorySystem, NvU32 swizzId, NvU64 offset, NvU64 size, NvS32 *numaNodeId); + +static inline NV_STATUS kmemsysNumaAddMemory_56cd7a(OBJGPU *pGpu, struct KernelMemorySystem *pKernelMemorySystem, NvU32 swizzId, NvU64 offset, NvU64 size, NvS32 *numaNodeId) { + return NV_OK; +} + +static inline NV_STATUS kmemsysNumaAddMemory_DISPATCH(OBJGPU *pGpu, struct KernelMemorySystem *pKernelMemorySystem, NvU32 swizzId, NvU64 offset, NvU64 size, NvS32 *numaNodeId) { + return pKernelMemorySystem->__kmemsysNumaAddMemory__(pGpu, pKernelMemorySystem, swizzId, offset, size, numaNodeId); +} -static inline void kmemsysCheckEccCounts_b3696a(OBJGPU *pGpu, struct KernelMemorySystem *pKernelMemorySystem) { +void kmemsysNumaRemoveMemory_GH100(OBJGPU *pGpu, struct KernelMemorySystem *pKernelMemorySystem, NvU32 swizzId); + +static inline void kmemsysNumaRemoveMemory_b3696a(OBJGPU *pGpu, struct KernelMemorySystem *pKernelMemorySystem, NvU32 swizzId) { return; } -static inline void kmemsysCheckEccCounts_DISPATCH(OBJGPU *pGpu, struct KernelMemorySystem *pKernelMemorySystem) { - pKernelMemorySystem->__kmemsysCheckEccCounts__(pGpu, pKernelMemorySystem); +static inline void kmemsysNumaRemoveMemory_DISPATCH(OBJGPU *pGpu, struct KernelMemorySystem *pKernelMemorySystem, NvU32 swizzId) { + pKernelMemorySystem->__kmemsysNumaRemoveMemory__(pGpu, pKernelMemorySystem, swizzId); } -NV_STATUS kmemsysClearEccCounts_GH100(OBJGPU *pGpu, struct KernelMemorySystem *pKernelMemorySystem); +void kmemsysNumaRemoveAllMemory_GH100(OBJGPU *pGpu, struct KernelMemorySystem *pKernelMemorySystem); -static inline NV_STATUS kmemsysClearEccCounts_56cd7a(OBJGPU *pGpu, struct KernelMemorySystem *pKernelMemorySystem) { - return NV_OK; +static inline void kmemsysNumaRemoveAllMemory_b3696a(OBJGPU *pGpu, struct KernelMemorySystem *pKernelMemorySystem) { + return; } -static inline NV_STATUS kmemsysClearEccCounts_DISPATCH(OBJGPU *pGpu, struct KernelMemorySystem *pKernelMemorySystem) { - return pKernelMemorySystem->__kmemsysClearEccCounts__(pGpu, pKernelMemorySystem); +static inline void kmemsysNumaRemoveAllMemory_DISPATCH(OBJGPU *pGpu, struct KernelMemorySystem *pKernelMemorySystem) { + pKernelMemorySystem->__kmemsysNumaRemoveAllMemory__(pGpu, pKernelMemorySystem); } -static inline NV_STATUS kmemsysReconcileTunableState_DISPATCH(POBJGPU pGpu, struct KernelMemorySystem *pEngstate, void *pTunableState) { - return pEngstate->__kmemsysReconcileTunableState__(pGpu, pEngstate, pTunableState); +static inline NV_STATUS kmemsysSetupAllAtsPeers_46f6a7(OBJGPU *pGpu, struct KernelMemorySystem *pKernelMemorySystem) { + return NV_ERR_NOT_SUPPORTED; } -static inline NV_STATUS kmemsysStateLoad_DISPATCH(POBJGPU pGpu, struct KernelMemorySystem *pEngstate, NvU32 arg0) { - return pEngstate->__kmemsysStateLoad__(pGpu, pEngstate, arg0); +NV_STATUS kmemsysSetupAllAtsPeers_GV100(OBJGPU *pGpu, struct KernelMemorySystem *pKernelMemorySystem); + +static inline NV_STATUS kmemsysSetupAllAtsPeers_DISPATCH(OBJGPU *pGpu, struct KernelMemorySystem *pKernelMemorySystem) { + return pKernelMemorySystem->__kmemsysSetupAllAtsPeers__(pGpu, pKernelMemorySystem); } -static inline NV_STATUS kmemsysStateUnload_DISPATCH(POBJGPU pGpu, struct KernelMemorySystem *pEngstate, NvU32 arg0) { - return pEngstate->__kmemsysStateUnload__(pGpu, pEngstate, arg0); +static inline void kmemsysRemoveAllAtsPeers_b3696a(OBJGPU *pGpu, struct KernelMemorySystem *pKernelMemorySystem) { + return; } -static inline NV_STATUS kmemsysStatePostUnload_DISPATCH(POBJGPU pGpu, struct KernelMemorySystem *pEngstate, NvU32 arg0) { - return pEngstate->__kmemsysStatePostUnload__(pGpu, pEngstate, arg0); +void kmemsysRemoveAllAtsPeers_GV100(OBJGPU *pGpu, struct KernelMemorySystem *pKernelMemorySystem); + +static inline void kmemsysRemoveAllAtsPeers_DISPATCH(OBJGPU *pGpu, struct KernelMemorySystem *pKernelMemorySystem) { + pKernelMemorySystem->__kmemsysRemoveAllAtsPeers__(pGpu, pKernelMemorySystem); } -static inline NV_STATUS kmemsysStatePreUnload_DISPATCH(POBJGPU pGpu, struct KernelMemorySystem *pEngstate, NvU32 arg0) { - return pEngstate->__kmemsysStatePreUnload__(pGpu, pEngstate, arg0); +NvU32 kmemsysGetMaxFbpas_TU102(OBJGPU *pGpu, struct KernelMemorySystem *pKernelMemorySystem); + +NvU32 kmemsysGetMaxFbpas_GA100(OBJGPU *pGpu, struct KernelMemorySystem *pKernelMemorySystem); + +static inline NvU32 kmemsysGetMaxFbpas_4a4dee(OBJGPU *pGpu, struct KernelMemorySystem *pKernelMemorySystem) { + return 0; } -static inline NV_STATUS kmemsysStateInitUnlocked_DISPATCH(POBJGPU pGpu, struct KernelMemorySystem *pEngstate) { - return pEngstate->__kmemsysStateInitUnlocked__(pGpu, pEngstate); +static inline NvU32 kmemsysGetMaxFbpas_DISPATCH(OBJGPU *pGpu, struct KernelMemorySystem *pKernelMemorySystem) { + return pKernelMemorySystem->__kmemsysGetMaxFbpas__(pGpu, pKernelMemorySystem); } -static inline void kmemsysInitMissing_DISPATCH(POBJGPU pGpu, struct KernelMemorySystem *pEngstate) { - pEngstate->__kmemsysInitMissing__(pGpu, pEngstate); +NvU32 kmemsysGetEccDedCountSize_TU102(OBJGPU *pGpu, struct KernelMemorySystem *pKernelMemorySystem); + +NvU32 kmemsysGetEccDedCountSize_GH100(OBJGPU *pGpu, struct KernelMemorySystem *pKernelMemorySystem); + +static inline NvU32 kmemsysGetEccDedCountSize_DISPATCH(OBJGPU *pGpu, struct KernelMemorySystem *pKernelMemorySystem) { + return pKernelMemorySystem->__kmemsysGetEccDedCountSize__(pGpu, pKernelMemorySystem); } -static inline NV_STATUS kmemsysStatePreInitLocked_DISPATCH(POBJGPU pGpu, struct KernelMemorySystem *pEngstate) { - return pEngstate->__kmemsysStatePreInitLocked__(pGpu, pEngstate); +NvU32 kmemsysGetEccDedCountRegAddr_TU102(OBJGPU *pGpu, struct KernelMemorySystem *pKernelMemorySystem, NvU32 fbpa, NvU32 subp); + +NvU32 kmemsysGetEccDedCountRegAddr_GH100(OBJGPU *pGpu, struct KernelMemorySystem *pKernelMemorySystem, NvU32 fbpa, NvU32 subp); + +static inline NvU32 kmemsysGetEccDedCountRegAddr_DISPATCH(OBJGPU *pGpu, struct KernelMemorySystem *pKernelMemorySystem, NvU32 fbpa, NvU32 subp) { + return pKernelMemorySystem->__kmemsysGetEccDedCountRegAddr__(pGpu, pKernelMemorySystem, fbpa, subp); } -static inline NV_STATUS kmemsysStatePreInitUnlocked_DISPATCH(POBJGPU pGpu, struct KernelMemorySystem *pEngstate) { - return pEngstate->__kmemsysStatePreInitUnlocked__(pGpu, pEngstate); +static inline NV_STATUS kmemsysStateLoad_DISPATCH(POBJGPU pGpu, struct KernelMemorySystem *pEngstate, NvU32 arg0) { + return pEngstate->__kmemsysStateLoad__(pGpu, pEngstate, arg0); } -static inline NV_STATUS kmemsysGetTunableState_DISPATCH(POBJGPU pGpu, struct KernelMemorySystem *pEngstate, void *pTunableState) { - return pEngstate->__kmemsysGetTunableState__(pGpu, pEngstate, pTunableState); +static inline NV_STATUS kmemsysStateUnload_DISPATCH(POBJGPU pGpu, struct KernelMemorySystem *pEngstate, NvU32 arg0) { + return pEngstate->__kmemsysStateUnload__(pGpu, pEngstate, arg0); } -static inline NV_STATUS kmemsysCompareTunableState_DISPATCH(POBJGPU pGpu, struct KernelMemorySystem *pEngstate, void *pTunables1, void *pTunables2) { - return pEngstate->__kmemsysCompareTunableState__(pGpu, pEngstate, pTunables1, pTunables2); +static inline NV_STATUS kmemsysStatePostUnload_DISPATCH(POBJGPU pGpu, struct KernelMemorySystem *pEngstate, NvU32 arg0) { + return pEngstate->__kmemsysStatePostUnload__(pGpu, pEngstate, arg0); } -static inline void kmemsysFreeTunableState_DISPATCH(POBJGPU pGpu, struct KernelMemorySystem *pEngstate, void *pTunableState) { - pEngstate->__kmemsysFreeTunableState__(pGpu, pEngstate, pTunableState); +static inline NV_STATUS kmemsysStateInitUnlocked_DISPATCH(POBJGPU pGpu, struct KernelMemorySystem *pEngstate) { + return pEngstate->__kmemsysStateInitUnlocked__(pGpu, pEngstate); } -static inline NV_STATUS kmemsysStatePostLoad_DISPATCH(POBJGPU pGpu, struct KernelMemorySystem *pEngstate, NvU32 arg0) { - return pEngstate->__kmemsysStatePostLoad__(pGpu, pEngstate, arg0); +static inline void kmemsysInitMissing_DISPATCH(POBJGPU pGpu, struct KernelMemorySystem *pEngstate) { + pEngstate->__kmemsysInitMissing__(pGpu, pEngstate); } -static inline NV_STATUS kmemsysAllocTunableState_DISPATCH(POBJGPU pGpu, struct KernelMemorySystem *pEngstate, void **ppTunableState) { - return pEngstate->__kmemsysAllocTunableState__(pGpu, pEngstate, ppTunableState); +static inline NV_STATUS kmemsysStatePreInitLocked_DISPATCH(POBJGPU pGpu, struct KernelMemorySystem *pEngstate) { + return pEngstate->__kmemsysStatePreInitLocked__(pGpu, pEngstate); } -static inline NV_STATUS kmemsysSetTunableState_DISPATCH(POBJGPU pGpu, struct KernelMemorySystem *pEngstate, void *pTunableState) { - return pEngstate->__kmemsysSetTunableState__(pGpu, pEngstate, pTunableState); +static inline NV_STATUS kmemsysStatePreInitUnlocked_DISPATCH(POBJGPU pGpu, struct KernelMemorySystem *pEngstate) { + return pEngstate->__kmemsysStatePreInitUnlocked__(pGpu, pEngstate); } static inline NvBool kmemsysIsPresent_DISPATCH(POBJGPU pGpu, struct KernelMemorySystem *pEngstate) { @@ -873,9 +947,9 @@ #undef PRIVATE_FIELD -#define IS_COHERENT_CPU_ATS_OFFSET(kmemsys, offset, length) \ - (kmemsys && ((offset) >= kmemsys->coherentCpuFbBase) && \ - (((NvU64)offset + size) <= kmemsys->coherentCpuFbEnd)) +#define IS_COHERENT_CPU_ATS_OFFSET(kmemsys, offset, length) \ + (kmemsys && ((offset) >= (kmemsys->coherentCpuFbBase + kmemsys->numaOnlineBase)) && \ + (((NvU64)offset + size) <= (kmemsys->coherentCpuFbBase + kmemsys->numaOnlineBase + kmemsys->numaOnlineSize))) #endif // KERN_MEM_SYS_H diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/generated/g_kern_perf_nvoc.c nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_kern_perf_nvoc.c --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/generated/g_kern_perf_nvoc.c 2023-10-25 20:27:04.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_kern_perf_nvoc.c 2024-03-05 22:18:23.000000000 +0000 @@ -86,10 +86,6 @@ kperfStateDestroy(pGpu, (struct KernelPerf *)(((unsigned char *)pKernelPerf) - __nvoc_rtti_KernelPerf_OBJENGSTATE.offset)); } -static NV_STATUS __nvoc_thunk_OBJENGSTATE_kperfReconcileTunableState(POBJGPU pGpu, struct KernelPerf *pEngstate, void *pTunableState) { - return engstateReconcileTunableState(pGpu, (struct OBJENGSTATE *)(((unsigned char *)pEngstate) + __nvoc_rtti_KernelPerf_OBJENGSTATE.offset), pTunableState); -} - static NV_STATUS __nvoc_thunk_OBJENGSTATE_kperfStatePreLoad(POBJGPU pGpu, struct KernelPerf *pEngstate, NvU32 arg0) { return engstateStatePreLoad(pGpu, (struct OBJENGSTATE *)(((unsigned char *)pEngstate) + __nvoc_rtti_KernelPerf_OBJENGSTATE.offset), arg0); } @@ -118,30 +114,10 @@ return engstateStatePreInitUnlocked(pGpu, (struct OBJENGSTATE *)(((unsigned char *)pEngstate) + __nvoc_rtti_KernelPerf_OBJENGSTATE.offset)); } -static NV_STATUS __nvoc_thunk_OBJENGSTATE_kperfGetTunableState(POBJGPU pGpu, struct KernelPerf *pEngstate, void *pTunableState) { - return engstateGetTunableState(pGpu, (struct OBJENGSTATE *)(((unsigned char *)pEngstate) + __nvoc_rtti_KernelPerf_OBJENGSTATE.offset), pTunableState); -} - -static NV_STATUS __nvoc_thunk_OBJENGSTATE_kperfCompareTunableState(POBJGPU pGpu, struct KernelPerf *pEngstate, void *pTunables1, void *pTunables2) { - return engstateCompareTunableState(pGpu, (struct OBJENGSTATE *)(((unsigned char *)pEngstate) + __nvoc_rtti_KernelPerf_OBJENGSTATE.offset), pTunables1, pTunables2); -} - -static void __nvoc_thunk_OBJENGSTATE_kperfFreeTunableState(POBJGPU pGpu, struct KernelPerf *pEngstate, void *pTunableState) { - engstateFreeTunableState(pGpu, (struct OBJENGSTATE *)(((unsigned char *)pEngstate) + __nvoc_rtti_KernelPerf_OBJENGSTATE.offset), pTunableState); -} - static NV_STATUS __nvoc_thunk_OBJENGSTATE_kperfStatePostLoad(POBJGPU pGpu, struct KernelPerf *pEngstate, NvU32 arg0) { return engstateStatePostLoad(pGpu, (struct OBJENGSTATE *)(((unsigned char *)pEngstate) + __nvoc_rtti_KernelPerf_OBJENGSTATE.offset), arg0); } -static NV_STATUS __nvoc_thunk_OBJENGSTATE_kperfAllocTunableState(POBJGPU pGpu, struct KernelPerf *pEngstate, void **ppTunableState) { - return engstateAllocTunableState(pGpu, (struct OBJENGSTATE *)(((unsigned char *)pEngstate) + __nvoc_rtti_KernelPerf_OBJENGSTATE.offset), ppTunableState); -} - -static NV_STATUS __nvoc_thunk_OBJENGSTATE_kperfSetTunableState(POBJGPU pGpu, struct KernelPerf *pEngstate, void *pTunableState) { - return engstateSetTunableState(pGpu, (struct OBJENGSTATE *)(((unsigned char *)pEngstate) + __nvoc_rtti_KernelPerf_OBJENGSTATE.offset), pTunableState); -} - static NvBool __nvoc_thunk_OBJENGSTATE_kperfIsPresent(POBJGPU pGpu, struct KernelPerf *pEngstate) { return engstateIsPresent(pGpu, (struct OBJENGSTATE *)(((unsigned char *)pEngstate) + __nvoc_rtti_KernelPerf_OBJENGSTATE.offset)); } @@ -209,8 +185,6 @@ pThis->__nvoc_base_OBJENGSTATE.__engstateStateDestroy__ = &__nvoc_thunk_KernelPerf_engstateStateDestroy; - pThis->__kperfReconcileTunableState__ = &__nvoc_thunk_OBJENGSTATE_kperfReconcileTunableState; - pThis->__kperfStatePreLoad__ = &__nvoc_thunk_OBJENGSTATE_kperfStatePreLoad; pThis->__kperfStatePostUnload__ = &__nvoc_thunk_OBJENGSTATE_kperfStatePostUnload; @@ -225,18 +199,8 @@ pThis->__kperfStatePreInitUnlocked__ = &__nvoc_thunk_OBJENGSTATE_kperfStatePreInitUnlocked; - pThis->__kperfGetTunableState__ = &__nvoc_thunk_OBJENGSTATE_kperfGetTunableState; - - pThis->__kperfCompareTunableState__ = &__nvoc_thunk_OBJENGSTATE_kperfCompareTunableState; - - pThis->__kperfFreeTunableState__ = &__nvoc_thunk_OBJENGSTATE_kperfFreeTunableState; - pThis->__kperfStatePostLoad__ = &__nvoc_thunk_OBJENGSTATE_kperfStatePostLoad; - pThis->__kperfAllocTunableState__ = &__nvoc_thunk_OBJENGSTATE_kperfAllocTunableState; - - pThis->__kperfSetTunableState__ = &__nvoc_thunk_OBJENGSTATE_kperfSetTunableState; - pThis->__kperfIsPresent__ = &__nvoc_thunk_OBJENGSTATE_kperfIsPresent; } @@ -259,13 +223,16 @@ KernelPerf *pThis; RmHalspecOwner *pRmhalspecowner; - pThis = portMemAllocNonPaged(sizeof(KernelPerf)); - if (pThis == NULL) return NV_ERR_NO_MEMORY; + status = __nvoc_handleObjCreateMemAlloc(createFlags, sizeof(KernelPerf), (void**)&pThis, (void**)ppThis); + if (status != NV_OK) + return status; portMemSet(pThis, 0, sizeof(KernelPerf)); __nvoc_initRtti(staticCast(pThis, Dynamic), &__nvoc_class_def_KernelPerf); + pThis->__nvoc_base_OBJENGSTATE.__nvoc_base_Object.createFlags = createFlags; + if (pParent != NULL && !(createFlags & NVOC_OBJ_CREATE_FLAGS_PARENT_HALSPEC_ONLY)) { pParentObj = dynamicCast(pParent, Object); @@ -285,11 +252,17 @@ if (status != NV_OK) goto __nvoc_objCreate_KernelPerf_cleanup; *ppThis = pThis; + return NV_OK; __nvoc_objCreate_KernelPerf_cleanup: // do not call destructors here since the constructor already called them - portMemFree(pThis); + if (createFlags & NVOC_OBJ_CREATE_FLAGS_IN_PLACE_CONSTRUCT) + portMemSet(pThis, 0, sizeof(KernelPerf)); + else + portMemFree(pThis); + + // coverity[leaked_storage:FALSE] return status; } diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/generated/g_kern_perf_nvoc.h nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_kern_perf_nvoc.h --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/generated/g_kern_perf_nvoc.h 2023-10-25 20:27:05.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_kern_perf_nvoc.h 2024-03-05 22:18:23.000000000 +0000 @@ -77,7 +77,6 @@ NV_STATUS (*__kperfStateLoad__)(struct OBJGPU *, struct KernelPerf *, NvU32); NV_STATUS (*__kperfStateUnload__)(struct OBJGPU *, struct KernelPerf *, NvU32); void (*__kperfStateDestroy__)(struct OBJGPU *, struct KernelPerf *); - NV_STATUS (*__kperfReconcileTunableState__)(POBJGPU, struct KernelPerf *, void *); NV_STATUS (*__kperfStatePreLoad__)(POBJGPU, struct KernelPerf *, NvU32); NV_STATUS (*__kperfStatePostUnload__)(POBJGPU, struct KernelPerf *, NvU32); NV_STATUS (*__kperfStatePreUnload__)(POBJGPU, struct KernelPerf *, NvU32); @@ -85,12 +84,7 @@ void (*__kperfInitMissing__)(POBJGPU, struct KernelPerf *); NV_STATUS (*__kperfStatePreInitLocked__)(POBJGPU, struct KernelPerf *); NV_STATUS (*__kperfStatePreInitUnlocked__)(POBJGPU, struct KernelPerf *); - NV_STATUS (*__kperfGetTunableState__)(POBJGPU, struct KernelPerf *, void *); - NV_STATUS (*__kperfCompareTunableState__)(POBJGPU, struct KernelPerf *, void *, void *); - void (*__kperfFreeTunableState__)(POBJGPU, struct KernelPerf *, void *); NV_STATUS (*__kperfStatePostLoad__)(POBJGPU, struct KernelPerf *, NvU32); - NV_STATUS (*__kperfAllocTunableState__)(POBJGPU, struct KernelPerf *, void **); - NV_STATUS (*__kperfSetTunableState__)(POBJGPU, struct KernelPerf *, void *); NvBool (*__kperfIsPresent__)(POBJGPU, struct KernelPerf *); struct KERNEL_PERF_GPU_BOOST_SYNC sliGpuBoostSync; NvU32 reentrancyMask; @@ -131,7 +125,6 @@ #define kperfStateLoad(pGpu, pKernelPerf, flags) kperfStateLoad_DISPATCH(pGpu, pKernelPerf, flags) #define kperfStateUnload(pGpu, pKernelPerf, flags) kperfStateUnload_DISPATCH(pGpu, pKernelPerf, flags) #define kperfStateDestroy(pGpu, pKernelPerf) kperfStateDestroy_DISPATCH(pGpu, pKernelPerf) -#define kperfReconcileTunableState(pGpu, pEngstate, pTunableState) kperfReconcileTunableState_DISPATCH(pGpu, pEngstate, pTunableState) #define kperfStatePreLoad(pGpu, pEngstate, arg0) kperfStatePreLoad_DISPATCH(pGpu, pEngstate, arg0) #define kperfStatePostUnload(pGpu, pEngstate, arg0) kperfStatePostUnload_DISPATCH(pGpu, pEngstate, arg0) #define kperfStatePreUnload(pGpu, pEngstate, arg0) kperfStatePreUnload_DISPATCH(pGpu, pEngstate, arg0) @@ -139,12 +132,7 @@ #define kperfInitMissing(pGpu, pEngstate) kperfInitMissing_DISPATCH(pGpu, pEngstate) #define kperfStatePreInitLocked(pGpu, pEngstate) kperfStatePreInitLocked_DISPATCH(pGpu, pEngstate) #define kperfStatePreInitUnlocked(pGpu, pEngstate) kperfStatePreInitUnlocked_DISPATCH(pGpu, pEngstate) -#define kperfGetTunableState(pGpu, pEngstate, pTunableState) kperfGetTunableState_DISPATCH(pGpu, pEngstate, pTunableState) -#define kperfCompareTunableState(pGpu, pEngstate, pTunables1, pTunables2) kperfCompareTunableState_DISPATCH(pGpu, pEngstate, pTunables1, pTunables2) -#define kperfFreeTunableState(pGpu, pEngstate, pTunableState) kperfFreeTunableState_DISPATCH(pGpu, pEngstate, pTunableState) #define kperfStatePostLoad(pGpu, pEngstate, arg0) kperfStatePostLoad_DISPATCH(pGpu, pEngstate, arg0) -#define kperfAllocTunableState(pGpu, pEngstate, ppTunableState) kperfAllocTunableState_DISPATCH(pGpu, pEngstate, ppTunableState) -#define kperfSetTunableState(pGpu, pEngstate, pTunableState) kperfSetTunableState_DISPATCH(pGpu, pEngstate, pTunableState) #define kperfIsPresent(pGpu, pEngstate) kperfIsPresent_DISPATCH(pGpu, pEngstate) NV_STATUS kperfGpuBoostSyncStateInit_IMPL(struct OBJGPU *pGpu, struct KernelPerf *pKernelPerf); @@ -204,10 +192,6 @@ pKernelPerf->__kperfStateDestroy__(pGpu, pKernelPerf); } -static inline NV_STATUS kperfReconcileTunableState_DISPATCH(POBJGPU pGpu, struct KernelPerf *pEngstate, void *pTunableState) { - return pEngstate->__kperfReconcileTunableState__(pGpu, pEngstate, pTunableState); -} - static inline NV_STATUS kperfStatePreLoad_DISPATCH(POBJGPU pGpu, struct KernelPerf *pEngstate, NvU32 arg0) { return pEngstate->__kperfStatePreLoad__(pGpu, pEngstate, arg0); } @@ -236,30 +220,10 @@ return pEngstate->__kperfStatePreInitUnlocked__(pGpu, pEngstate); } -static inline NV_STATUS kperfGetTunableState_DISPATCH(POBJGPU pGpu, struct KernelPerf *pEngstate, void *pTunableState) { - return pEngstate->__kperfGetTunableState__(pGpu, pEngstate, pTunableState); -} - -static inline NV_STATUS kperfCompareTunableState_DISPATCH(POBJGPU pGpu, struct KernelPerf *pEngstate, void *pTunables1, void *pTunables2) { - return pEngstate->__kperfCompareTunableState__(pGpu, pEngstate, pTunables1, pTunables2); -} - -static inline void kperfFreeTunableState_DISPATCH(POBJGPU pGpu, struct KernelPerf *pEngstate, void *pTunableState) { - pEngstate->__kperfFreeTunableState__(pGpu, pEngstate, pTunableState); -} - static inline NV_STATUS kperfStatePostLoad_DISPATCH(POBJGPU pGpu, struct KernelPerf *pEngstate, NvU32 arg0) { return pEngstate->__kperfStatePostLoad__(pGpu, pEngstate, arg0); } -static inline NV_STATUS kperfAllocTunableState_DISPATCH(POBJGPU pGpu, struct KernelPerf *pEngstate, void **ppTunableState) { - return pEngstate->__kperfAllocTunableState__(pGpu, pEngstate, ppTunableState); -} - -static inline NV_STATUS kperfSetTunableState_DISPATCH(POBJGPU pGpu, struct KernelPerf *pEngstate, void *pTunableState) { - return pEngstate->__kperfSetTunableState__(pGpu, pEngstate, pTunableState); -} - static inline NvBool kperfIsPresent_DISPATCH(POBJGPU pGpu, struct KernelPerf *pEngstate) { return pEngstate->__kperfIsPresent__(pGpu, pEngstate); } diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/generated/g_kern_perfbuffer_nvoc.c nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_kern_perfbuffer_nvoc.c --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/generated/g_kern_perfbuffer_nvoc.c 2023-10-25 20:27:05.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_kern_perfbuffer_nvoc.c 2024-03-05 22:18:23.000000000 +0000 @@ -97,84 +97,92 @@ return gpuresShareCallback((struct GpuResource *)(((unsigned char *)pGpuResource) + __nvoc_rtti_PerfBuffer_GpuResource.offset), pInvokingClient, pParentRef, pSharePolicy); } -static NV_STATUS __nvoc_thunk_GpuResource_perfbufferControl(struct PerfBuffer *pGpuResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { - return gpuresControl((struct GpuResource *)(((unsigned char *)pGpuResource) + __nvoc_rtti_PerfBuffer_GpuResource.offset), pCallContext, pParams); +static NV_STATUS __nvoc_thunk_RmResource_perfbufferCheckMemInterUnmap(struct PerfBuffer *pRmResource, NvBool bSubdeviceHandleProvided) { + return rmresCheckMemInterUnmap((struct RmResource *)(((unsigned char *)pRmResource) + __nvoc_rtti_PerfBuffer_RmResource.offset), bSubdeviceHandleProvided); } -static NV_STATUS __nvoc_thunk_GpuResource_perfbufferUnmap(struct PerfBuffer *pGpuResource, struct CALL_CONTEXT *pCallContext, struct RsCpuMapping *pCpuMapping) { - return gpuresUnmap((struct GpuResource *)(((unsigned char *)pGpuResource) + __nvoc_rtti_PerfBuffer_GpuResource.offset), pCallContext, pCpuMapping); +static NV_STATUS __nvoc_thunk_RsResource_perfbufferMapTo(struct PerfBuffer *pResource, RS_RES_MAP_TO_PARAMS *pParams) { + return resMapTo((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_PerfBuffer_RsResource.offset), pParams); } -static NV_STATUS __nvoc_thunk_RmResource_perfbufferGetMemInterMapParams(struct PerfBuffer *pRmResource, RMRES_MEM_INTER_MAP_PARAMS *pParams) { - return rmresGetMemInterMapParams((struct RmResource *)(((unsigned char *)pRmResource) + __nvoc_rtti_PerfBuffer_RmResource.offset), pParams); +static NV_STATUS __nvoc_thunk_GpuResource_perfbufferGetMapAddrSpace(struct PerfBuffer *pGpuResource, struct CALL_CONTEXT *pCallContext, NvU32 mapFlags, NV_ADDRESS_SPACE *pAddrSpace) { + return gpuresGetMapAddrSpace((struct GpuResource *)(((unsigned char *)pGpuResource) + __nvoc_rtti_PerfBuffer_GpuResource.offset), pCallContext, mapFlags, pAddrSpace); } -static NV_STATUS __nvoc_thunk_RmResource_perfbufferGetMemoryMappingDescriptor(struct PerfBuffer *pRmResource, struct MEMORY_DESCRIPTOR **ppMemDesc) { - return rmresGetMemoryMappingDescriptor((struct RmResource *)(((unsigned char *)pRmResource) + __nvoc_rtti_PerfBuffer_RmResource.offset), ppMemDesc); +static NvU32 __nvoc_thunk_RsResource_perfbufferGetRefCount(struct PerfBuffer *pResource) { + return resGetRefCount((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_PerfBuffer_RsResource.offset)); } -static NV_STATUS __nvoc_thunk_GpuResource_perfbufferGetMapAddrSpace(struct PerfBuffer *pGpuResource, struct CALL_CONTEXT *pCallContext, NvU32 mapFlags, NV_ADDRESS_SPACE *pAddrSpace) { - return gpuresGetMapAddrSpace((struct GpuResource *)(((unsigned char *)pGpuResource) + __nvoc_rtti_PerfBuffer_GpuResource.offset), pCallContext, mapFlags, pAddrSpace); +static void __nvoc_thunk_RsResource_perfbufferAddAdditionalDependants(struct RsClient *pClient, struct PerfBuffer *pResource, RsResourceRef *pReference) { + resAddAdditionalDependants(pClient, (struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_PerfBuffer_RsResource.offset), pReference); } -static NvHandle __nvoc_thunk_GpuResource_perfbufferGetInternalObjectHandle(struct PerfBuffer *pGpuResource) { - return gpuresGetInternalObjectHandle((struct GpuResource *)(((unsigned char *)pGpuResource) + __nvoc_rtti_PerfBuffer_GpuResource.offset)); +static NV_STATUS __nvoc_thunk_RmResource_perfbufferControl_Prologue(struct PerfBuffer *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return rmresControl_Prologue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_PerfBuffer_RmResource.offset), pCallContext, pParams); } -static NV_STATUS __nvoc_thunk_RsResource_perfbufferControlFilter(struct PerfBuffer *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { - return resControlFilter((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_PerfBuffer_RsResource.offset), pCallContext, pParams); +static NV_STATUS __nvoc_thunk_GpuResource_perfbufferGetRegBaseOffsetAndSize(struct PerfBuffer *pGpuResource, struct OBJGPU *pGpu, NvU32 *pOffset, NvU32 *pSize) { + return gpuresGetRegBaseOffsetAndSize((struct GpuResource *)(((unsigned char *)pGpuResource) + __nvoc_rtti_PerfBuffer_GpuResource.offset), pGpu, pOffset, pSize); } -static void __nvoc_thunk_RsResource_perfbufferAddAdditionalDependants(struct RsClient *pClient, struct PerfBuffer *pResource, RsResourceRef *pReference) { - resAddAdditionalDependants(pClient, (struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_PerfBuffer_RsResource.offset), pReference); +static NV_STATUS __nvoc_thunk_GpuResource_perfbufferInternalControlForward(struct PerfBuffer *pGpuResource, NvU32 command, void *pParams, NvU32 size) { + return gpuresInternalControlForward((struct GpuResource *)(((unsigned char *)pGpuResource) + __nvoc_rtti_PerfBuffer_GpuResource.offset), command, pParams, size); } -static NvU32 __nvoc_thunk_RsResource_perfbufferGetRefCount(struct PerfBuffer *pResource) { - return resGetRefCount((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_PerfBuffer_RsResource.offset)); +static NV_STATUS __nvoc_thunk_RsResource_perfbufferUnmapFrom(struct PerfBuffer *pResource, RS_RES_UNMAP_FROM_PARAMS *pParams) { + return resUnmapFrom((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_PerfBuffer_RsResource.offset), pParams); } -static NV_STATUS __nvoc_thunk_RmResource_perfbufferCheckMemInterUnmap(struct PerfBuffer *pRmResource, NvBool bSubdeviceHandleProvided) { - return rmresCheckMemInterUnmap((struct RmResource *)(((unsigned char *)pRmResource) + __nvoc_rtti_PerfBuffer_RmResource.offset), bSubdeviceHandleProvided); +static void __nvoc_thunk_RmResource_perfbufferControl_Epilogue(struct PerfBuffer *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + rmresControl_Epilogue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_PerfBuffer_RmResource.offset), pCallContext, pParams); } -static NV_STATUS __nvoc_thunk_RsResource_perfbufferMapTo(struct PerfBuffer *pResource, RS_RES_MAP_TO_PARAMS *pParams) { - return resMapTo((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_PerfBuffer_RsResource.offset), pParams); +static NV_STATUS __nvoc_thunk_RsResource_perfbufferControlLookup(struct PerfBuffer *pResource, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams, const struct NVOC_EXPORTED_METHOD_DEF **ppEntry) { + return resControlLookup((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_PerfBuffer_RsResource.offset), pParams, ppEntry); } -static NV_STATUS __nvoc_thunk_RmResource_perfbufferControl_Prologue(struct PerfBuffer *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { - return rmresControl_Prologue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_PerfBuffer_RmResource.offset), pCallContext, pParams); +static NvHandle __nvoc_thunk_GpuResource_perfbufferGetInternalObjectHandle(struct PerfBuffer *pGpuResource) { + return gpuresGetInternalObjectHandle((struct GpuResource *)(((unsigned char *)pGpuResource) + __nvoc_rtti_PerfBuffer_GpuResource.offset)); } -static NV_STATUS __nvoc_thunk_GpuResource_perfbufferGetRegBaseOffsetAndSize(struct PerfBuffer *pGpuResource, struct OBJGPU *pGpu, NvU32 *pOffset, NvU32 *pSize) { - return gpuresGetRegBaseOffsetAndSize((struct GpuResource *)(((unsigned char *)pGpuResource) + __nvoc_rtti_PerfBuffer_GpuResource.offset), pGpu, pOffset, pSize); +static NV_STATUS __nvoc_thunk_GpuResource_perfbufferControl(struct PerfBuffer *pGpuResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return gpuresControl((struct GpuResource *)(((unsigned char *)pGpuResource) + __nvoc_rtti_PerfBuffer_GpuResource.offset), pCallContext, pParams); } -static NvBool __nvoc_thunk_RsResource_perfbufferCanCopy(struct PerfBuffer *pResource) { - return resCanCopy((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_PerfBuffer_RsResource.offset)); +static NV_STATUS __nvoc_thunk_GpuResource_perfbufferUnmap(struct PerfBuffer *pGpuResource, struct CALL_CONTEXT *pCallContext, struct RsCpuMapping *pCpuMapping) { + return gpuresUnmap((struct GpuResource *)(((unsigned char *)pGpuResource) + __nvoc_rtti_PerfBuffer_GpuResource.offset), pCallContext, pCpuMapping); } -static NV_STATUS __nvoc_thunk_GpuResource_perfbufferInternalControlForward(struct PerfBuffer *pGpuResource, NvU32 command, void *pParams, NvU32 size) { - return gpuresInternalControlForward((struct GpuResource *)(((unsigned char *)pGpuResource) + __nvoc_rtti_PerfBuffer_GpuResource.offset), command, pParams, size); +static NV_STATUS __nvoc_thunk_RmResource_perfbufferGetMemInterMapParams(struct PerfBuffer *pRmResource, RMRES_MEM_INTER_MAP_PARAMS *pParams) { + return rmresGetMemInterMapParams((struct RmResource *)(((unsigned char *)pRmResource) + __nvoc_rtti_PerfBuffer_RmResource.offset), pParams); } -static void __nvoc_thunk_RsResource_perfbufferPreDestruct(struct PerfBuffer *pResource) { - resPreDestruct((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_PerfBuffer_RsResource.offset)); +static NV_STATUS __nvoc_thunk_RmResource_perfbufferGetMemoryMappingDescriptor(struct PerfBuffer *pRmResource, struct MEMORY_DESCRIPTOR **ppMemDesc) { + return rmresGetMemoryMappingDescriptor((struct RmResource *)(((unsigned char *)pRmResource) + __nvoc_rtti_PerfBuffer_RmResource.offset), ppMemDesc); } -static NV_STATUS __nvoc_thunk_RsResource_perfbufferUnmapFrom(struct PerfBuffer *pResource, RS_RES_UNMAP_FROM_PARAMS *pParams) { - return resUnmapFrom((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_PerfBuffer_RsResource.offset), pParams); +static NV_STATUS __nvoc_thunk_RsResource_perfbufferControlFilter(struct PerfBuffer *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return resControlFilter((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_PerfBuffer_RsResource.offset), pCallContext, pParams); } -static NV_STATUS __nvoc_thunk_RsResource_perfbufferIsDuplicate(struct PerfBuffer *pResource, NvHandle hMemory, NvBool *pDuplicate) { - return resIsDuplicate((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_PerfBuffer_RsResource.offset), hMemory, pDuplicate); +static NV_STATUS __nvoc_thunk_RmResource_perfbufferControlSerialization_Prologue(struct PerfBuffer *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return rmresControlSerialization_Prologue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_PerfBuffer_RmResource.offset), pCallContext, pParams); } -static void __nvoc_thunk_RmResource_perfbufferControl_Epilogue(struct PerfBuffer *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { - rmresControl_Epilogue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_PerfBuffer_RmResource.offset), pCallContext, pParams); +static NvBool __nvoc_thunk_RsResource_perfbufferCanCopy(struct PerfBuffer *pResource) { + return resCanCopy((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_PerfBuffer_RsResource.offset)); } -static NV_STATUS __nvoc_thunk_RsResource_perfbufferControlLookup(struct PerfBuffer *pResource, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams, const struct NVOC_EXPORTED_METHOD_DEF **ppEntry) { - return resControlLookup((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_PerfBuffer_RsResource.offset), pParams, ppEntry); +static void __nvoc_thunk_RsResource_perfbufferPreDestruct(struct PerfBuffer *pResource) { + resPreDestruct((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_PerfBuffer_RsResource.offset)); +} + +static NV_STATUS __nvoc_thunk_RsResource_perfbufferIsDuplicate(struct PerfBuffer *pResource, NvHandle hMemory, NvBool *pDuplicate) { + return resIsDuplicate((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_PerfBuffer_RsResource.offset), hMemory, pDuplicate); +} + +static void __nvoc_thunk_RmResource_perfbufferControlSerialization_Epilogue(struct PerfBuffer *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + rmresControlSerialization_Epilogue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_PerfBuffer_RmResource.offset), pCallContext, pParams); } static NV_STATUS __nvoc_thunk_GpuResource_perfbufferMap(struct PerfBuffer *pGpuResource, struct CALL_CONTEXT *pCallContext, struct RS_CPU_MAP_PARAMS *pParams, struct RsCpuMapping *pCpuMapping) { @@ -236,45 +244,49 @@ pThis->__perfbufferShareCallback__ = &__nvoc_thunk_GpuResource_perfbufferShareCallback; - pThis->__perfbufferControl__ = &__nvoc_thunk_GpuResource_perfbufferControl; + pThis->__perfbufferCheckMemInterUnmap__ = &__nvoc_thunk_RmResource_perfbufferCheckMemInterUnmap; - pThis->__perfbufferUnmap__ = &__nvoc_thunk_GpuResource_perfbufferUnmap; + pThis->__perfbufferMapTo__ = &__nvoc_thunk_RsResource_perfbufferMapTo; - pThis->__perfbufferGetMemInterMapParams__ = &__nvoc_thunk_RmResource_perfbufferGetMemInterMapParams; + pThis->__perfbufferGetMapAddrSpace__ = &__nvoc_thunk_GpuResource_perfbufferGetMapAddrSpace; - pThis->__perfbufferGetMemoryMappingDescriptor__ = &__nvoc_thunk_RmResource_perfbufferGetMemoryMappingDescriptor; + pThis->__perfbufferGetRefCount__ = &__nvoc_thunk_RsResource_perfbufferGetRefCount; - pThis->__perfbufferGetMapAddrSpace__ = &__nvoc_thunk_GpuResource_perfbufferGetMapAddrSpace; + pThis->__perfbufferAddAdditionalDependants__ = &__nvoc_thunk_RsResource_perfbufferAddAdditionalDependants; - pThis->__perfbufferGetInternalObjectHandle__ = &__nvoc_thunk_GpuResource_perfbufferGetInternalObjectHandle; + pThis->__perfbufferControl_Prologue__ = &__nvoc_thunk_RmResource_perfbufferControl_Prologue; - pThis->__perfbufferControlFilter__ = &__nvoc_thunk_RsResource_perfbufferControlFilter; + pThis->__perfbufferGetRegBaseOffsetAndSize__ = &__nvoc_thunk_GpuResource_perfbufferGetRegBaseOffsetAndSize; - pThis->__perfbufferAddAdditionalDependants__ = &__nvoc_thunk_RsResource_perfbufferAddAdditionalDependants; + pThis->__perfbufferInternalControlForward__ = &__nvoc_thunk_GpuResource_perfbufferInternalControlForward; - pThis->__perfbufferGetRefCount__ = &__nvoc_thunk_RsResource_perfbufferGetRefCount; + pThis->__perfbufferUnmapFrom__ = &__nvoc_thunk_RsResource_perfbufferUnmapFrom; - pThis->__perfbufferCheckMemInterUnmap__ = &__nvoc_thunk_RmResource_perfbufferCheckMemInterUnmap; + pThis->__perfbufferControl_Epilogue__ = &__nvoc_thunk_RmResource_perfbufferControl_Epilogue; - pThis->__perfbufferMapTo__ = &__nvoc_thunk_RsResource_perfbufferMapTo; + pThis->__perfbufferControlLookup__ = &__nvoc_thunk_RsResource_perfbufferControlLookup; - pThis->__perfbufferControl_Prologue__ = &__nvoc_thunk_RmResource_perfbufferControl_Prologue; + pThis->__perfbufferGetInternalObjectHandle__ = &__nvoc_thunk_GpuResource_perfbufferGetInternalObjectHandle; - pThis->__perfbufferGetRegBaseOffsetAndSize__ = &__nvoc_thunk_GpuResource_perfbufferGetRegBaseOffsetAndSize; + pThis->__perfbufferControl__ = &__nvoc_thunk_GpuResource_perfbufferControl; - pThis->__perfbufferCanCopy__ = &__nvoc_thunk_RsResource_perfbufferCanCopy; + pThis->__perfbufferUnmap__ = &__nvoc_thunk_GpuResource_perfbufferUnmap; - pThis->__perfbufferInternalControlForward__ = &__nvoc_thunk_GpuResource_perfbufferInternalControlForward; + pThis->__perfbufferGetMemInterMapParams__ = &__nvoc_thunk_RmResource_perfbufferGetMemInterMapParams; - pThis->__perfbufferPreDestruct__ = &__nvoc_thunk_RsResource_perfbufferPreDestruct; + pThis->__perfbufferGetMemoryMappingDescriptor__ = &__nvoc_thunk_RmResource_perfbufferGetMemoryMappingDescriptor; - pThis->__perfbufferUnmapFrom__ = &__nvoc_thunk_RsResource_perfbufferUnmapFrom; + pThis->__perfbufferControlFilter__ = &__nvoc_thunk_RsResource_perfbufferControlFilter; - pThis->__perfbufferIsDuplicate__ = &__nvoc_thunk_RsResource_perfbufferIsDuplicate; + pThis->__perfbufferControlSerialization_Prologue__ = &__nvoc_thunk_RmResource_perfbufferControlSerialization_Prologue; - pThis->__perfbufferControl_Epilogue__ = &__nvoc_thunk_RmResource_perfbufferControl_Epilogue; + pThis->__perfbufferCanCopy__ = &__nvoc_thunk_RsResource_perfbufferCanCopy; - pThis->__perfbufferControlLookup__ = &__nvoc_thunk_RsResource_perfbufferControlLookup; + pThis->__perfbufferPreDestruct__ = &__nvoc_thunk_RsResource_perfbufferPreDestruct; + + pThis->__perfbufferIsDuplicate__ = &__nvoc_thunk_RsResource_perfbufferIsDuplicate; + + pThis->__perfbufferControlSerialization_Epilogue__ = &__nvoc_thunk_RmResource_perfbufferControlSerialization_Epilogue; pThis->__perfbufferMap__ = &__nvoc_thunk_GpuResource_perfbufferMap; @@ -303,13 +315,16 @@ PerfBuffer *pThis; RmHalspecOwner *pRmhalspecowner; - pThis = portMemAllocNonPaged(sizeof(PerfBuffer)); - if (pThis == NULL) return NV_ERR_NO_MEMORY; + status = __nvoc_handleObjCreateMemAlloc(createFlags, sizeof(PerfBuffer), (void**)&pThis, (void**)ppThis); + if (status != NV_OK) + return status; portMemSet(pThis, 0, sizeof(PerfBuffer)); __nvoc_initRtti(staticCast(pThis, Dynamic), &__nvoc_class_def_PerfBuffer); + pThis->__nvoc_base_GpuResource.__nvoc_base_RmResource.__nvoc_base_RsResource.__nvoc_base_Object.createFlags = createFlags; + if (pParent != NULL && !(createFlags & NVOC_OBJ_CREATE_FLAGS_PARENT_HALSPEC_ONLY)) { pParentObj = dynamicCast(pParent, Object); @@ -329,11 +344,17 @@ if (status != NV_OK) goto __nvoc_objCreate_PerfBuffer_cleanup; *ppThis = pThis; + return NV_OK; __nvoc_objCreate_PerfBuffer_cleanup: // do not call destructors here since the constructor already called them - portMemFree(pThis); + if (createFlags & NVOC_OBJ_CREATE_FLAGS_IN_PLACE_CONSTRUCT) + portMemSet(pThis, 0, sizeof(PerfBuffer)); + else + portMemFree(pThis); + + // coverity[leaked_storage:FALSE] return status; } diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/generated/g_kern_perfbuffer_nvoc.h nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_kern_perfbuffer_nvoc.h --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/generated/g_kern_perfbuffer_nvoc.h 2023-10-25 20:27:05.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_kern_perfbuffer_nvoc.h 2024-03-05 22:18:23.000000000 +0000 @@ -56,26 +56,28 @@ struct GpuResource *__nvoc_pbase_GpuResource; struct PerfBuffer *__nvoc_pbase_PerfBuffer; NvBool (*__perfbufferShareCallback__)(struct PerfBuffer *, struct RsClient *, struct RsResourceRef *, RS_SHARE_POLICY *); - NV_STATUS (*__perfbufferControl__)(struct PerfBuffer *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); - NV_STATUS (*__perfbufferUnmap__)(struct PerfBuffer *, struct CALL_CONTEXT *, struct RsCpuMapping *); - NV_STATUS (*__perfbufferGetMemInterMapParams__)(struct PerfBuffer *, RMRES_MEM_INTER_MAP_PARAMS *); - NV_STATUS (*__perfbufferGetMemoryMappingDescriptor__)(struct PerfBuffer *, struct MEMORY_DESCRIPTOR **); - NV_STATUS (*__perfbufferGetMapAddrSpace__)(struct PerfBuffer *, struct CALL_CONTEXT *, NvU32, NV_ADDRESS_SPACE *); - NvHandle (*__perfbufferGetInternalObjectHandle__)(struct PerfBuffer *); - NV_STATUS (*__perfbufferControlFilter__)(struct PerfBuffer *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); - void (*__perfbufferAddAdditionalDependants__)(struct RsClient *, struct PerfBuffer *, RsResourceRef *); - NvU32 (*__perfbufferGetRefCount__)(struct PerfBuffer *); NV_STATUS (*__perfbufferCheckMemInterUnmap__)(struct PerfBuffer *, NvBool); NV_STATUS (*__perfbufferMapTo__)(struct PerfBuffer *, RS_RES_MAP_TO_PARAMS *); + NV_STATUS (*__perfbufferGetMapAddrSpace__)(struct PerfBuffer *, struct CALL_CONTEXT *, NvU32, NV_ADDRESS_SPACE *); + NvU32 (*__perfbufferGetRefCount__)(struct PerfBuffer *); + void (*__perfbufferAddAdditionalDependants__)(struct RsClient *, struct PerfBuffer *, RsResourceRef *); NV_STATUS (*__perfbufferControl_Prologue__)(struct PerfBuffer *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); NV_STATUS (*__perfbufferGetRegBaseOffsetAndSize__)(struct PerfBuffer *, struct OBJGPU *, NvU32 *, NvU32 *); - NvBool (*__perfbufferCanCopy__)(struct PerfBuffer *); NV_STATUS (*__perfbufferInternalControlForward__)(struct PerfBuffer *, NvU32, void *, NvU32); - void (*__perfbufferPreDestruct__)(struct PerfBuffer *); NV_STATUS (*__perfbufferUnmapFrom__)(struct PerfBuffer *, RS_RES_UNMAP_FROM_PARAMS *); - NV_STATUS (*__perfbufferIsDuplicate__)(struct PerfBuffer *, NvHandle, NvBool *); void (*__perfbufferControl_Epilogue__)(struct PerfBuffer *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); NV_STATUS (*__perfbufferControlLookup__)(struct PerfBuffer *, struct RS_RES_CONTROL_PARAMS_INTERNAL *, const struct NVOC_EXPORTED_METHOD_DEF **); + NvHandle (*__perfbufferGetInternalObjectHandle__)(struct PerfBuffer *); + NV_STATUS (*__perfbufferControl__)(struct PerfBuffer *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); + NV_STATUS (*__perfbufferUnmap__)(struct PerfBuffer *, struct CALL_CONTEXT *, struct RsCpuMapping *); + NV_STATUS (*__perfbufferGetMemInterMapParams__)(struct PerfBuffer *, RMRES_MEM_INTER_MAP_PARAMS *); + NV_STATUS (*__perfbufferGetMemoryMappingDescriptor__)(struct PerfBuffer *, struct MEMORY_DESCRIPTOR **); + NV_STATUS (*__perfbufferControlFilter__)(struct PerfBuffer *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); + NV_STATUS (*__perfbufferControlSerialization_Prologue__)(struct PerfBuffer *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); + NvBool (*__perfbufferCanCopy__)(struct PerfBuffer *); + void (*__perfbufferPreDestruct__)(struct PerfBuffer *); + NV_STATUS (*__perfbufferIsDuplicate__)(struct PerfBuffer *, NvHandle, NvBool *); + void (*__perfbufferControlSerialization_Epilogue__)(struct PerfBuffer *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); NV_STATUS (*__perfbufferMap__)(struct PerfBuffer *, struct CALL_CONTEXT *, struct RS_CPU_MAP_PARAMS *, struct RsCpuMapping *); NvBool (*__perfbufferAccessCallback__)(struct PerfBuffer *, struct RsClient *, void *, RsAccessRight); void *pObject; @@ -110,26 +112,28 @@ __nvoc_objCreate_PerfBuffer((ppNewObj), staticCast((pParent), Dynamic), (createFlags), arg_pCallContext, arg_pParams) #define perfbufferShareCallback(pGpuResource, pInvokingClient, pParentRef, pSharePolicy) perfbufferShareCallback_DISPATCH(pGpuResource, pInvokingClient, pParentRef, pSharePolicy) -#define perfbufferControl(pGpuResource, pCallContext, pParams) perfbufferControl_DISPATCH(pGpuResource, pCallContext, pParams) -#define perfbufferUnmap(pGpuResource, pCallContext, pCpuMapping) perfbufferUnmap_DISPATCH(pGpuResource, pCallContext, pCpuMapping) -#define perfbufferGetMemInterMapParams(pRmResource, pParams) perfbufferGetMemInterMapParams_DISPATCH(pRmResource, pParams) -#define perfbufferGetMemoryMappingDescriptor(pRmResource, ppMemDesc) perfbufferGetMemoryMappingDescriptor_DISPATCH(pRmResource, ppMemDesc) -#define perfbufferGetMapAddrSpace(pGpuResource, pCallContext, mapFlags, pAddrSpace) perfbufferGetMapAddrSpace_DISPATCH(pGpuResource, pCallContext, mapFlags, pAddrSpace) -#define perfbufferGetInternalObjectHandle(pGpuResource) perfbufferGetInternalObjectHandle_DISPATCH(pGpuResource) -#define perfbufferControlFilter(pResource, pCallContext, pParams) perfbufferControlFilter_DISPATCH(pResource, pCallContext, pParams) -#define perfbufferAddAdditionalDependants(pClient, pResource, pReference) perfbufferAddAdditionalDependants_DISPATCH(pClient, pResource, pReference) -#define perfbufferGetRefCount(pResource) perfbufferGetRefCount_DISPATCH(pResource) #define perfbufferCheckMemInterUnmap(pRmResource, bSubdeviceHandleProvided) perfbufferCheckMemInterUnmap_DISPATCH(pRmResource, bSubdeviceHandleProvided) #define perfbufferMapTo(pResource, pParams) perfbufferMapTo_DISPATCH(pResource, pParams) +#define perfbufferGetMapAddrSpace(pGpuResource, pCallContext, mapFlags, pAddrSpace) perfbufferGetMapAddrSpace_DISPATCH(pGpuResource, pCallContext, mapFlags, pAddrSpace) +#define perfbufferGetRefCount(pResource) perfbufferGetRefCount_DISPATCH(pResource) +#define perfbufferAddAdditionalDependants(pClient, pResource, pReference) perfbufferAddAdditionalDependants_DISPATCH(pClient, pResource, pReference) #define perfbufferControl_Prologue(pResource, pCallContext, pParams) perfbufferControl_Prologue_DISPATCH(pResource, pCallContext, pParams) #define perfbufferGetRegBaseOffsetAndSize(pGpuResource, pGpu, pOffset, pSize) perfbufferGetRegBaseOffsetAndSize_DISPATCH(pGpuResource, pGpu, pOffset, pSize) -#define perfbufferCanCopy(pResource) perfbufferCanCopy_DISPATCH(pResource) #define perfbufferInternalControlForward(pGpuResource, command, pParams, size) perfbufferInternalControlForward_DISPATCH(pGpuResource, command, pParams, size) -#define perfbufferPreDestruct(pResource) perfbufferPreDestruct_DISPATCH(pResource) #define perfbufferUnmapFrom(pResource, pParams) perfbufferUnmapFrom_DISPATCH(pResource, pParams) -#define perfbufferIsDuplicate(pResource, hMemory, pDuplicate) perfbufferIsDuplicate_DISPATCH(pResource, hMemory, pDuplicate) #define perfbufferControl_Epilogue(pResource, pCallContext, pParams) perfbufferControl_Epilogue_DISPATCH(pResource, pCallContext, pParams) #define perfbufferControlLookup(pResource, pParams, ppEntry) perfbufferControlLookup_DISPATCH(pResource, pParams, ppEntry) +#define perfbufferGetInternalObjectHandle(pGpuResource) perfbufferGetInternalObjectHandle_DISPATCH(pGpuResource) +#define perfbufferControl(pGpuResource, pCallContext, pParams) perfbufferControl_DISPATCH(pGpuResource, pCallContext, pParams) +#define perfbufferUnmap(pGpuResource, pCallContext, pCpuMapping) perfbufferUnmap_DISPATCH(pGpuResource, pCallContext, pCpuMapping) +#define perfbufferGetMemInterMapParams(pRmResource, pParams) perfbufferGetMemInterMapParams_DISPATCH(pRmResource, pParams) +#define perfbufferGetMemoryMappingDescriptor(pRmResource, ppMemDesc) perfbufferGetMemoryMappingDescriptor_DISPATCH(pRmResource, ppMemDesc) +#define perfbufferControlFilter(pResource, pCallContext, pParams) perfbufferControlFilter_DISPATCH(pResource, pCallContext, pParams) +#define perfbufferControlSerialization_Prologue(pResource, pCallContext, pParams) perfbufferControlSerialization_Prologue_DISPATCH(pResource, pCallContext, pParams) +#define perfbufferCanCopy(pResource) perfbufferCanCopy_DISPATCH(pResource) +#define perfbufferPreDestruct(pResource) perfbufferPreDestruct_DISPATCH(pResource) +#define perfbufferIsDuplicate(pResource, hMemory, pDuplicate) perfbufferIsDuplicate_DISPATCH(pResource, hMemory, pDuplicate) +#define perfbufferControlSerialization_Epilogue(pResource, pCallContext, pParams) perfbufferControlSerialization_Epilogue_DISPATCH(pResource, pCallContext, pParams) #define perfbufferMap(pGpuResource, pCallContext, pParams, pCpuMapping) perfbufferMap_DISPATCH(pGpuResource, pCallContext, pParams, pCpuMapping) #define perfbufferAccessCallback(pResource, pInvokingClient, pAllocParams, accessRight) perfbufferAccessCallback_DISPATCH(pResource, pInvokingClient, pAllocParams, accessRight) NV_STATUS perfbufferConstructHal_KERNEL(struct PerfBuffer *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_ALLOC_PARAMS_INTERNAL *pParams); @@ -156,84 +160,92 @@ return pGpuResource->__perfbufferShareCallback__(pGpuResource, pInvokingClient, pParentRef, pSharePolicy); } -static inline NV_STATUS perfbufferControl_DISPATCH(struct PerfBuffer *pGpuResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { - return pGpuResource->__perfbufferControl__(pGpuResource, pCallContext, pParams); +static inline NV_STATUS perfbufferCheckMemInterUnmap_DISPATCH(struct PerfBuffer *pRmResource, NvBool bSubdeviceHandleProvided) { + return pRmResource->__perfbufferCheckMemInterUnmap__(pRmResource, bSubdeviceHandleProvided); } -static inline NV_STATUS perfbufferUnmap_DISPATCH(struct PerfBuffer *pGpuResource, struct CALL_CONTEXT *pCallContext, struct RsCpuMapping *pCpuMapping) { - return pGpuResource->__perfbufferUnmap__(pGpuResource, pCallContext, pCpuMapping); +static inline NV_STATUS perfbufferMapTo_DISPATCH(struct PerfBuffer *pResource, RS_RES_MAP_TO_PARAMS *pParams) { + return pResource->__perfbufferMapTo__(pResource, pParams); } -static inline NV_STATUS perfbufferGetMemInterMapParams_DISPATCH(struct PerfBuffer *pRmResource, RMRES_MEM_INTER_MAP_PARAMS *pParams) { - return pRmResource->__perfbufferGetMemInterMapParams__(pRmResource, pParams); +static inline NV_STATUS perfbufferGetMapAddrSpace_DISPATCH(struct PerfBuffer *pGpuResource, struct CALL_CONTEXT *pCallContext, NvU32 mapFlags, NV_ADDRESS_SPACE *pAddrSpace) { + return pGpuResource->__perfbufferGetMapAddrSpace__(pGpuResource, pCallContext, mapFlags, pAddrSpace); } -static inline NV_STATUS perfbufferGetMemoryMappingDescriptor_DISPATCH(struct PerfBuffer *pRmResource, struct MEMORY_DESCRIPTOR **ppMemDesc) { - return pRmResource->__perfbufferGetMemoryMappingDescriptor__(pRmResource, ppMemDesc); +static inline NvU32 perfbufferGetRefCount_DISPATCH(struct PerfBuffer *pResource) { + return pResource->__perfbufferGetRefCount__(pResource); } -static inline NV_STATUS perfbufferGetMapAddrSpace_DISPATCH(struct PerfBuffer *pGpuResource, struct CALL_CONTEXT *pCallContext, NvU32 mapFlags, NV_ADDRESS_SPACE *pAddrSpace) { - return pGpuResource->__perfbufferGetMapAddrSpace__(pGpuResource, pCallContext, mapFlags, pAddrSpace); +static inline void perfbufferAddAdditionalDependants_DISPATCH(struct RsClient *pClient, struct PerfBuffer *pResource, RsResourceRef *pReference) { + pResource->__perfbufferAddAdditionalDependants__(pClient, pResource, pReference); } -static inline NvHandle perfbufferGetInternalObjectHandle_DISPATCH(struct PerfBuffer *pGpuResource) { - return pGpuResource->__perfbufferGetInternalObjectHandle__(pGpuResource); +static inline NV_STATUS perfbufferControl_Prologue_DISPATCH(struct PerfBuffer *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return pResource->__perfbufferControl_Prologue__(pResource, pCallContext, pParams); } -static inline NV_STATUS perfbufferControlFilter_DISPATCH(struct PerfBuffer *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { - return pResource->__perfbufferControlFilter__(pResource, pCallContext, pParams); +static inline NV_STATUS perfbufferGetRegBaseOffsetAndSize_DISPATCH(struct PerfBuffer *pGpuResource, struct OBJGPU *pGpu, NvU32 *pOffset, NvU32 *pSize) { + return pGpuResource->__perfbufferGetRegBaseOffsetAndSize__(pGpuResource, pGpu, pOffset, pSize); } -static inline void perfbufferAddAdditionalDependants_DISPATCH(struct RsClient *pClient, struct PerfBuffer *pResource, RsResourceRef *pReference) { - pResource->__perfbufferAddAdditionalDependants__(pClient, pResource, pReference); +static inline NV_STATUS perfbufferInternalControlForward_DISPATCH(struct PerfBuffer *pGpuResource, NvU32 command, void *pParams, NvU32 size) { + return pGpuResource->__perfbufferInternalControlForward__(pGpuResource, command, pParams, size); } -static inline NvU32 perfbufferGetRefCount_DISPATCH(struct PerfBuffer *pResource) { - return pResource->__perfbufferGetRefCount__(pResource); +static inline NV_STATUS perfbufferUnmapFrom_DISPATCH(struct PerfBuffer *pResource, RS_RES_UNMAP_FROM_PARAMS *pParams) { + return pResource->__perfbufferUnmapFrom__(pResource, pParams); } -static inline NV_STATUS perfbufferCheckMemInterUnmap_DISPATCH(struct PerfBuffer *pRmResource, NvBool bSubdeviceHandleProvided) { - return pRmResource->__perfbufferCheckMemInterUnmap__(pRmResource, bSubdeviceHandleProvided); +static inline void perfbufferControl_Epilogue_DISPATCH(struct PerfBuffer *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + pResource->__perfbufferControl_Epilogue__(pResource, pCallContext, pParams); } -static inline NV_STATUS perfbufferMapTo_DISPATCH(struct PerfBuffer *pResource, RS_RES_MAP_TO_PARAMS *pParams) { - return pResource->__perfbufferMapTo__(pResource, pParams); +static inline NV_STATUS perfbufferControlLookup_DISPATCH(struct PerfBuffer *pResource, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams, const struct NVOC_EXPORTED_METHOD_DEF **ppEntry) { + return pResource->__perfbufferControlLookup__(pResource, pParams, ppEntry); } -static inline NV_STATUS perfbufferControl_Prologue_DISPATCH(struct PerfBuffer *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { - return pResource->__perfbufferControl_Prologue__(pResource, pCallContext, pParams); +static inline NvHandle perfbufferGetInternalObjectHandle_DISPATCH(struct PerfBuffer *pGpuResource) { + return pGpuResource->__perfbufferGetInternalObjectHandle__(pGpuResource); } -static inline NV_STATUS perfbufferGetRegBaseOffsetAndSize_DISPATCH(struct PerfBuffer *pGpuResource, struct OBJGPU *pGpu, NvU32 *pOffset, NvU32 *pSize) { - return pGpuResource->__perfbufferGetRegBaseOffsetAndSize__(pGpuResource, pGpu, pOffset, pSize); +static inline NV_STATUS perfbufferControl_DISPATCH(struct PerfBuffer *pGpuResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return pGpuResource->__perfbufferControl__(pGpuResource, pCallContext, pParams); } -static inline NvBool perfbufferCanCopy_DISPATCH(struct PerfBuffer *pResource) { - return pResource->__perfbufferCanCopy__(pResource); +static inline NV_STATUS perfbufferUnmap_DISPATCH(struct PerfBuffer *pGpuResource, struct CALL_CONTEXT *pCallContext, struct RsCpuMapping *pCpuMapping) { + return pGpuResource->__perfbufferUnmap__(pGpuResource, pCallContext, pCpuMapping); } -static inline NV_STATUS perfbufferInternalControlForward_DISPATCH(struct PerfBuffer *pGpuResource, NvU32 command, void *pParams, NvU32 size) { - return pGpuResource->__perfbufferInternalControlForward__(pGpuResource, command, pParams, size); +static inline NV_STATUS perfbufferGetMemInterMapParams_DISPATCH(struct PerfBuffer *pRmResource, RMRES_MEM_INTER_MAP_PARAMS *pParams) { + return pRmResource->__perfbufferGetMemInterMapParams__(pRmResource, pParams); } -static inline void perfbufferPreDestruct_DISPATCH(struct PerfBuffer *pResource) { - pResource->__perfbufferPreDestruct__(pResource); +static inline NV_STATUS perfbufferGetMemoryMappingDescriptor_DISPATCH(struct PerfBuffer *pRmResource, struct MEMORY_DESCRIPTOR **ppMemDesc) { + return pRmResource->__perfbufferGetMemoryMappingDescriptor__(pRmResource, ppMemDesc); } -static inline NV_STATUS perfbufferUnmapFrom_DISPATCH(struct PerfBuffer *pResource, RS_RES_UNMAP_FROM_PARAMS *pParams) { - return pResource->__perfbufferUnmapFrom__(pResource, pParams); +static inline NV_STATUS perfbufferControlFilter_DISPATCH(struct PerfBuffer *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return pResource->__perfbufferControlFilter__(pResource, pCallContext, pParams); } -static inline NV_STATUS perfbufferIsDuplicate_DISPATCH(struct PerfBuffer *pResource, NvHandle hMemory, NvBool *pDuplicate) { - return pResource->__perfbufferIsDuplicate__(pResource, hMemory, pDuplicate); +static inline NV_STATUS perfbufferControlSerialization_Prologue_DISPATCH(struct PerfBuffer *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return pResource->__perfbufferControlSerialization_Prologue__(pResource, pCallContext, pParams); } -static inline void perfbufferControl_Epilogue_DISPATCH(struct PerfBuffer *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { - pResource->__perfbufferControl_Epilogue__(pResource, pCallContext, pParams); +static inline NvBool perfbufferCanCopy_DISPATCH(struct PerfBuffer *pResource) { + return pResource->__perfbufferCanCopy__(pResource); } -static inline NV_STATUS perfbufferControlLookup_DISPATCH(struct PerfBuffer *pResource, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams, const struct NVOC_EXPORTED_METHOD_DEF **ppEntry) { - return pResource->__perfbufferControlLookup__(pResource, pParams, ppEntry); +static inline void perfbufferPreDestruct_DISPATCH(struct PerfBuffer *pResource) { + pResource->__perfbufferPreDestruct__(pResource); +} + +static inline NV_STATUS perfbufferIsDuplicate_DISPATCH(struct PerfBuffer *pResource, NvHandle hMemory, NvBool *pDuplicate) { + return pResource->__perfbufferIsDuplicate__(pResource, hMemory, pDuplicate); +} + +static inline void perfbufferControlSerialization_Epilogue_DISPATCH(struct PerfBuffer *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + pResource->__perfbufferControlSerialization_Epilogue__(pResource, pCallContext, pParams); } static inline NV_STATUS perfbufferMap_DISPATCH(struct PerfBuffer *pGpuResource, struct CALL_CONTEXT *pCallContext, struct RS_CPU_MAP_PARAMS *pParams, struct RsCpuMapping *pCpuMapping) { diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/generated/g_kern_pmu_nvoc.c nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_kern_pmu_nvoc.c --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/generated/g_kern_pmu_nvoc.c 2023-10-25 20:27:05.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_kern_pmu_nvoc.c 2024-03-05 22:18:23.000000000 +0000 @@ -17,10 +17,10 @@ extern const struct NVOC_CLASS_DEF __nvoc_class_def_OBJENGSTATE; -void __nvoc_init_KernelPmu(KernelPmu*, RmHalspecOwner* ); -void __nvoc_init_funcTable_KernelPmu(KernelPmu*, RmHalspecOwner* ); -NV_STATUS __nvoc_ctor_KernelPmu(KernelPmu*, RmHalspecOwner* ); -void __nvoc_init_dataField_KernelPmu(KernelPmu*, RmHalspecOwner* ); +void __nvoc_init_KernelPmu(KernelPmu*); +void __nvoc_init_funcTable_KernelPmu(KernelPmu*); +NV_STATUS __nvoc_ctor_KernelPmu(KernelPmu*); +void __nvoc_init_dataField_KernelPmu(KernelPmu*); void __nvoc_dtor_KernelPmu(KernelPmu*); extern const struct NVOC_EXPORT_INFO __nvoc_export_info_KernelPmu; @@ -74,10 +74,6 @@ return kpmuStateInitLocked(pGpu, (struct KernelPmu *)(((unsigned char *)pKernelPmu) - __nvoc_rtti_KernelPmu_OBJENGSTATE.offset)); } -static NV_STATUS __nvoc_thunk_OBJENGSTATE_kpmuReconcileTunableState(POBJGPU pGpu, struct KernelPmu *pEngstate, void *pTunableState) { - return engstateReconcileTunableState(pGpu, (struct OBJENGSTATE *)(((unsigned char *)pEngstate) + __nvoc_rtti_KernelPmu_OBJENGSTATE.offset), pTunableState); -} - static NV_STATUS __nvoc_thunk_OBJENGSTATE_kpmuStateLoad(POBJGPU pGpu, struct KernelPmu *pEngstate, NvU32 arg0) { return engstateStateLoad(pGpu, (struct OBJENGSTATE *)(((unsigned char *)pEngstate) + __nvoc_rtti_KernelPmu_OBJENGSTATE.offset), arg0); } @@ -118,30 +114,10 @@ return engstateStatePreInitUnlocked(pGpu, (struct OBJENGSTATE *)(((unsigned char *)pEngstate) + __nvoc_rtti_KernelPmu_OBJENGSTATE.offset)); } -static NV_STATUS __nvoc_thunk_OBJENGSTATE_kpmuGetTunableState(POBJGPU pGpu, struct KernelPmu *pEngstate, void *pTunableState) { - return engstateGetTunableState(pGpu, (struct OBJENGSTATE *)(((unsigned char *)pEngstate) + __nvoc_rtti_KernelPmu_OBJENGSTATE.offset), pTunableState); -} - -static NV_STATUS __nvoc_thunk_OBJENGSTATE_kpmuCompareTunableState(POBJGPU pGpu, struct KernelPmu *pEngstate, void *pTunables1, void *pTunables2) { - return engstateCompareTunableState(pGpu, (struct OBJENGSTATE *)(((unsigned char *)pEngstate) + __nvoc_rtti_KernelPmu_OBJENGSTATE.offset), pTunables1, pTunables2); -} - -static void __nvoc_thunk_OBJENGSTATE_kpmuFreeTunableState(POBJGPU pGpu, struct KernelPmu *pEngstate, void *pTunableState) { - engstateFreeTunableState(pGpu, (struct OBJENGSTATE *)(((unsigned char *)pEngstate) + __nvoc_rtti_KernelPmu_OBJENGSTATE.offset), pTunableState); -} - static NV_STATUS __nvoc_thunk_OBJENGSTATE_kpmuStatePostLoad(POBJGPU pGpu, struct KernelPmu *pEngstate, NvU32 arg0) { return engstateStatePostLoad(pGpu, (struct OBJENGSTATE *)(((unsigned char *)pEngstate) + __nvoc_rtti_KernelPmu_OBJENGSTATE.offset), arg0); } -static NV_STATUS __nvoc_thunk_OBJENGSTATE_kpmuAllocTunableState(POBJGPU pGpu, struct KernelPmu *pEngstate, void **ppTunableState) { - return engstateAllocTunableState(pGpu, (struct OBJENGSTATE *)(((unsigned char *)pEngstate) + __nvoc_rtti_KernelPmu_OBJENGSTATE.offset), ppTunableState); -} - -static NV_STATUS __nvoc_thunk_OBJENGSTATE_kpmuSetTunableState(POBJGPU pGpu, struct KernelPmu *pEngstate, void *pTunableState) { - return engstateSetTunableState(pGpu, (struct OBJENGSTATE *)(((unsigned char *)pEngstate) + __nvoc_rtti_KernelPmu_OBJENGSTATE.offset), pTunableState); -} - static NvBool __nvoc_thunk_OBJENGSTATE_kpmuIsPresent(POBJGPU pGpu, struct KernelPmu *pEngstate) { return engstateIsPresent(pGpu, (struct OBJENGSTATE *)(((unsigned char *)pEngstate) + __nvoc_rtti_KernelPmu_OBJENGSTATE.offset)); } @@ -159,21 +135,16 @@ PORT_UNREFERENCED_VARIABLE(pThis); } -void __nvoc_init_dataField_KernelPmu(KernelPmu *pThis, RmHalspecOwner *pRmhalspecowner) { - ChipHal *chipHal = &pRmhalspecowner->chipHal; - const unsigned long chipHal_HalVarIdx = (unsigned long)chipHal->__nvoc_HalVarIdx; +void __nvoc_init_dataField_KernelPmu(KernelPmu *pThis) { PORT_UNREFERENCED_VARIABLE(pThis); - PORT_UNREFERENCED_VARIABLE(pRmhalspecowner); - PORT_UNREFERENCED_VARIABLE(chipHal); - PORT_UNREFERENCED_VARIABLE(chipHal_HalVarIdx); } NV_STATUS __nvoc_ctor_OBJENGSTATE(OBJENGSTATE* ); -NV_STATUS __nvoc_ctor_KernelPmu(KernelPmu *pThis, RmHalspecOwner *pRmhalspecowner) { +NV_STATUS __nvoc_ctor_KernelPmu(KernelPmu *pThis) { NV_STATUS status = NV_OK; status = __nvoc_ctor_OBJENGSTATE(&pThis->__nvoc_base_OBJENGSTATE); if (status != NV_OK) goto __nvoc_ctor_KernelPmu_fail_OBJENGSTATE; - __nvoc_init_dataField_KernelPmu(pThis, pRmhalspecowner); + __nvoc_init_dataField_KernelPmu(pThis); goto __nvoc_ctor_KernelPmu_exit; // Success __nvoc_ctor_KernelPmu_fail_OBJENGSTATE: @@ -182,35 +153,17 @@ return status; } -static void __nvoc_init_funcTable_KernelPmu_1(KernelPmu *pThis, RmHalspecOwner *pRmhalspecowner) { - ChipHal *chipHal = &pRmhalspecowner->chipHal; - const unsigned long chipHal_HalVarIdx = (unsigned long)chipHal->__nvoc_HalVarIdx; +static void __nvoc_init_funcTable_KernelPmu_1(KernelPmu *pThis) { PORT_UNREFERENCED_VARIABLE(pThis); - PORT_UNREFERENCED_VARIABLE(pRmhalspecowner); - PORT_UNREFERENCED_VARIABLE(chipHal); - PORT_UNREFERENCED_VARIABLE(chipHal_HalVarIdx); pThis->__kpmuConstructEngine__ = &kpmuConstructEngine_IMPL; pThis->__kpmuStateInitLocked__ = &kpmuStateInitLocked_IMPL; - // Hal function -- kpmuPreOsGlobalErotGrantRequest - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x01f00000UL) )) /* ChipHal: AD102 | AD103 | AD104 | AD106 | AD107 */ - { - pThis->__kpmuPreOsGlobalErotGrantRequest__ = &kpmuPreOsGlobalErotGrantRequest_AD102; - } - // default - else - { - pThis->__kpmuPreOsGlobalErotGrantRequest__ = &kpmuPreOsGlobalErotGrantRequest_56cd7a; - } - pThis->__nvoc_base_OBJENGSTATE.__engstateConstructEngine__ = &__nvoc_thunk_KernelPmu_engstateConstructEngine; pThis->__nvoc_base_OBJENGSTATE.__engstateStateInitLocked__ = &__nvoc_thunk_KernelPmu_engstateStateInitLocked; - pThis->__kpmuReconcileTunableState__ = &__nvoc_thunk_OBJENGSTATE_kpmuReconcileTunableState; - pThis->__kpmuStateLoad__ = &__nvoc_thunk_OBJENGSTATE_kpmuStateLoad; pThis->__kpmuStateUnload__ = &__nvoc_thunk_OBJENGSTATE_kpmuStateUnload; @@ -231,47 +184,39 @@ pThis->__kpmuStatePreInitUnlocked__ = &__nvoc_thunk_OBJENGSTATE_kpmuStatePreInitUnlocked; - pThis->__kpmuGetTunableState__ = &__nvoc_thunk_OBJENGSTATE_kpmuGetTunableState; - - pThis->__kpmuCompareTunableState__ = &__nvoc_thunk_OBJENGSTATE_kpmuCompareTunableState; - - pThis->__kpmuFreeTunableState__ = &__nvoc_thunk_OBJENGSTATE_kpmuFreeTunableState; - pThis->__kpmuStatePostLoad__ = &__nvoc_thunk_OBJENGSTATE_kpmuStatePostLoad; - pThis->__kpmuAllocTunableState__ = &__nvoc_thunk_OBJENGSTATE_kpmuAllocTunableState; - - pThis->__kpmuSetTunableState__ = &__nvoc_thunk_OBJENGSTATE_kpmuSetTunableState; - pThis->__kpmuIsPresent__ = &__nvoc_thunk_OBJENGSTATE_kpmuIsPresent; } -void __nvoc_init_funcTable_KernelPmu(KernelPmu *pThis, RmHalspecOwner *pRmhalspecowner) { - __nvoc_init_funcTable_KernelPmu_1(pThis, pRmhalspecowner); +void __nvoc_init_funcTable_KernelPmu(KernelPmu *pThis) { + __nvoc_init_funcTable_KernelPmu_1(pThis); } void __nvoc_init_OBJENGSTATE(OBJENGSTATE*); -void __nvoc_init_KernelPmu(KernelPmu *pThis, RmHalspecOwner *pRmhalspecowner) { +void __nvoc_init_KernelPmu(KernelPmu *pThis) { pThis->__nvoc_pbase_KernelPmu = pThis; pThis->__nvoc_pbase_Object = &pThis->__nvoc_base_OBJENGSTATE.__nvoc_base_Object; pThis->__nvoc_pbase_OBJENGSTATE = &pThis->__nvoc_base_OBJENGSTATE; __nvoc_init_OBJENGSTATE(&pThis->__nvoc_base_OBJENGSTATE); - __nvoc_init_funcTable_KernelPmu(pThis, pRmhalspecowner); + __nvoc_init_funcTable_KernelPmu(pThis); } NV_STATUS __nvoc_objCreate_KernelPmu(KernelPmu **ppThis, Dynamic *pParent, NvU32 createFlags) { NV_STATUS status; Object *pParentObj; KernelPmu *pThis; - RmHalspecOwner *pRmhalspecowner; - pThis = portMemAllocNonPaged(sizeof(KernelPmu)); - if (pThis == NULL) return NV_ERR_NO_MEMORY; + status = __nvoc_handleObjCreateMemAlloc(createFlags, sizeof(KernelPmu), (void**)&pThis, (void**)ppThis); + if (status != NV_OK) + return status; portMemSet(pThis, 0, sizeof(KernelPmu)); __nvoc_initRtti(staticCast(pThis, Dynamic), &__nvoc_class_def_KernelPmu); + pThis->__nvoc_base_OBJENGSTATE.__nvoc_base_Object.createFlags = createFlags; + if (pParent != NULL && !(createFlags & NVOC_OBJ_CREATE_FLAGS_PARENT_HALSPEC_ONLY)) { pParentObj = dynamicCast(pParent, Object); @@ -282,20 +227,22 @@ pThis->__nvoc_base_OBJENGSTATE.__nvoc_base_Object.pParent = NULL; } - if ((pRmhalspecowner = dynamicCast(pParent, RmHalspecOwner)) == NULL) - pRmhalspecowner = objFindAncestorOfType(RmHalspecOwner, pParent); - NV_ASSERT_OR_RETURN(pRmhalspecowner != NULL, NV_ERR_INVALID_ARGUMENT); - - __nvoc_init_KernelPmu(pThis, pRmhalspecowner); - status = __nvoc_ctor_KernelPmu(pThis, pRmhalspecowner); + __nvoc_init_KernelPmu(pThis); + status = __nvoc_ctor_KernelPmu(pThis); if (status != NV_OK) goto __nvoc_objCreate_KernelPmu_cleanup; *ppThis = pThis; + return NV_OK; __nvoc_objCreate_KernelPmu_cleanup: // do not call destructors here since the constructor already called them - portMemFree(pThis); + if (createFlags & NVOC_OBJ_CREATE_FLAGS_IN_PLACE_CONSTRUCT) + portMemSet(pThis, 0, sizeof(KernelPmu)); + else + portMemFree(pThis); + + // coverity[leaked_storage:FALSE] return status; } diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/generated/g_kern_pmu_nvoc.h nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_kern_pmu_nvoc.h --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/generated/g_kern_pmu_nvoc.h 2023-10-25 20:27:05.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_kern_pmu_nvoc.h 2024-03-05 22:18:23.000000000 +0000 @@ -7,7 +7,7 @@ #endif /* - * SPDX-FileCopyrightText: Copyright (c) 2021-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2021-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -66,8 +66,6 @@ struct KernelPmu *__nvoc_pbase_KernelPmu; NV_STATUS (*__kpmuConstructEngine__)(struct OBJGPU *, struct KernelPmu *, ENGDESCRIPTOR); NV_STATUS (*__kpmuStateInitLocked__)(struct OBJGPU *, struct KernelPmu *); - NV_STATUS (*__kpmuPreOsGlobalErotGrantRequest__)(struct OBJGPU *, struct KernelPmu *); - NV_STATUS (*__kpmuReconcileTunableState__)(POBJGPU, struct KernelPmu *, void *); NV_STATUS (*__kpmuStateLoad__)(POBJGPU, struct KernelPmu *, NvU32); NV_STATUS (*__kpmuStateUnload__)(POBJGPU, struct KernelPmu *, NvU32); NV_STATUS (*__kpmuStatePreLoad__)(POBJGPU, struct KernelPmu *, NvU32); @@ -78,12 +76,7 @@ void (*__kpmuInitMissing__)(POBJGPU, struct KernelPmu *); NV_STATUS (*__kpmuStatePreInitLocked__)(POBJGPU, struct KernelPmu *); NV_STATUS (*__kpmuStatePreInitUnlocked__)(POBJGPU, struct KernelPmu *); - NV_STATUS (*__kpmuGetTunableState__)(POBJGPU, struct KernelPmu *, void *); - NV_STATUS (*__kpmuCompareTunableState__)(POBJGPU, struct KernelPmu *, void *, void *); - void (*__kpmuFreeTunableState__)(POBJGPU, struct KernelPmu *, void *); NV_STATUS (*__kpmuStatePostLoad__)(POBJGPU, struct KernelPmu *, NvU32); - NV_STATUS (*__kpmuAllocTunableState__)(POBJGPU, struct KernelPmu *, void **); - NV_STATUS (*__kpmuSetTunableState__)(POBJGPU, struct KernelPmu *, void *); NvBool (*__kpmuIsPresent__)(POBJGPU, struct KernelPmu *); LIBOS_LOG_DECODE logDecode; NvU32 printBufSize; @@ -124,9 +117,6 @@ #define kpmuConstructEngine(pGpu, pKernelPmu, engDesc) kpmuConstructEngine_DISPATCH(pGpu, pKernelPmu, engDesc) #define kpmuStateInitLocked(pGpu, pKernelPmu) kpmuStateInitLocked_DISPATCH(pGpu, pKernelPmu) -#define kpmuPreOsGlobalErotGrantRequest(pGpu, pKernelPmu) kpmuPreOsGlobalErotGrantRequest_DISPATCH(pGpu, pKernelPmu) -#define kpmuPreOsGlobalErotGrantRequest_HAL(pGpu, pKernelPmu) kpmuPreOsGlobalErotGrantRequest_DISPATCH(pGpu, pKernelPmu) -#define kpmuReconcileTunableState(pGpu, pEngstate, pTunableState) kpmuReconcileTunableState_DISPATCH(pGpu, pEngstate, pTunableState) #define kpmuStateLoad(pGpu, pEngstate, arg0) kpmuStateLoad_DISPATCH(pGpu, pEngstate, arg0) #define kpmuStateUnload(pGpu, pEngstate, arg0) kpmuStateUnload_DISPATCH(pGpu, pEngstate, arg0) #define kpmuStatePreLoad(pGpu, pEngstate, arg0) kpmuStatePreLoad_DISPATCH(pGpu, pEngstate, arg0) @@ -137,12 +127,7 @@ #define kpmuInitMissing(pGpu, pEngstate) kpmuInitMissing_DISPATCH(pGpu, pEngstate) #define kpmuStatePreInitLocked(pGpu, pEngstate) kpmuStatePreInitLocked_DISPATCH(pGpu, pEngstate) #define kpmuStatePreInitUnlocked(pGpu, pEngstate) kpmuStatePreInitUnlocked_DISPATCH(pGpu, pEngstate) -#define kpmuGetTunableState(pGpu, pEngstate, pTunableState) kpmuGetTunableState_DISPATCH(pGpu, pEngstate, pTunableState) -#define kpmuCompareTunableState(pGpu, pEngstate, pTunables1, pTunables2) kpmuCompareTunableState_DISPATCH(pGpu, pEngstate, pTunables1, pTunables2) -#define kpmuFreeTunableState(pGpu, pEngstate, pTunableState) kpmuFreeTunableState_DISPATCH(pGpu, pEngstate, pTunableState) #define kpmuStatePostLoad(pGpu, pEngstate, arg0) kpmuStatePostLoad_DISPATCH(pGpu, pEngstate, arg0) -#define kpmuAllocTunableState(pGpu, pEngstate, ppTunableState) kpmuAllocTunableState_DISPATCH(pGpu, pEngstate, ppTunableState) -#define kpmuSetTunableState(pGpu, pEngstate, pTunableState) kpmuSetTunableState_DISPATCH(pGpu, pEngstate, pTunableState) #define kpmuIsPresent(pGpu, pEngstate) kpmuIsPresent_DISPATCH(pGpu, pEngstate) NV_STATUS kpmuConstructEngine_IMPL(struct OBJGPU *pGpu, struct KernelPmu *pKernelPmu, ENGDESCRIPTOR engDesc); @@ -156,20 +141,6 @@ return pKernelPmu->__kpmuStateInitLocked__(pGpu, pKernelPmu); } -NV_STATUS kpmuPreOsGlobalErotGrantRequest_AD102(struct OBJGPU *pGpu, struct KernelPmu *pKernelPmu); - -static inline NV_STATUS kpmuPreOsGlobalErotGrantRequest_56cd7a(struct OBJGPU *pGpu, struct KernelPmu *pKernelPmu) { - return NV_OK; -} - -static inline NV_STATUS kpmuPreOsGlobalErotGrantRequest_DISPATCH(struct OBJGPU *pGpu, struct KernelPmu *pKernelPmu) { - return pKernelPmu->__kpmuPreOsGlobalErotGrantRequest__(pGpu, pKernelPmu); -} - -static inline NV_STATUS kpmuReconcileTunableState_DISPATCH(POBJGPU pGpu, struct KernelPmu *pEngstate, void *pTunableState) { - return pEngstate->__kpmuReconcileTunableState__(pGpu, pEngstate, pTunableState); -} - static inline NV_STATUS kpmuStateLoad_DISPATCH(POBJGPU pGpu, struct KernelPmu *pEngstate, NvU32 arg0) { return pEngstate->__kpmuStateLoad__(pGpu, pEngstate, arg0); } @@ -210,30 +181,10 @@ return pEngstate->__kpmuStatePreInitUnlocked__(pGpu, pEngstate); } -static inline NV_STATUS kpmuGetTunableState_DISPATCH(POBJGPU pGpu, struct KernelPmu *pEngstate, void *pTunableState) { - return pEngstate->__kpmuGetTunableState__(pGpu, pEngstate, pTunableState); -} - -static inline NV_STATUS kpmuCompareTunableState_DISPATCH(POBJGPU pGpu, struct KernelPmu *pEngstate, void *pTunables1, void *pTunables2) { - return pEngstate->__kpmuCompareTunableState__(pGpu, pEngstate, pTunables1, pTunables2); -} - -static inline void kpmuFreeTunableState_DISPATCH(POBJGPU pGpu, struct KernelPmu *pEngstate, void *pTunableState) { - pEngstate->__kpmuFreeTunableState__(pGpu, pEngstate, pTunableState); -} - static inline NV_STATUS kpmuStatePostLoad_DISPATCH(POBJGPU pGpu, struct KernelPmu *pEngstate, NvU32 arg0) { return pEngstate->__kpmuStatePostLoad__(pGpu, pEngstate, arg0); } -static inline NV_STATUS kpmuAllocTunableState_DISPATCH(POBJGPU pGpu, struct KernelPmu *pEngstate, void **ppTunableState) { - return pEngstate->__kpmuAllocTunableState__(pGpu, pEngstate, ppTunableState); -} - -static inline NV_STATUS kpmuSetTunableState_DISPATCH(POBJGPU pGpu, struct KernelPmu *pEngstate, void *pTunableState) { - return pEngstate->__kpmuSetTunableState__(pGpu, pEngstate, pTunableState); -} - static inline NvBool kpmuIsPresent_DISPATCH(POBJGPU pGpu, struct KernelPmu *pEngstate) { return pEngstate->__kpmuIsPresent__(pGpu, pEngstate); } diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/generated/g_kernel_bif_nvoc.c nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_kernel_bif_nvoc.c --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/generated/g_kernel_bif_nvoc.c 2023-10-25 20:27:05.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_kernel_bif_nvoc.c 2024-03-05 22:18:24.000000000 +0000 @@ -86,10 +86,6 @@ return kbifStateUnload(pGpu, (struct KernelBif *)(((unsigned char *)pKernelBif) - __nvoc_rtti_KernelBif_OBJENGSTATE.offset), arg0); } -static NV_STATUS __nvoc_thunk_OBJENGSTATE_kbifReconcileTunableState(POBJGPU pGpu, struct KernelBif *pEngstate, void *pTunableState) { - return engstateReconcileTunableState(pGpu, (struct OBJENGSTATE *)(((unsigned char *)pEngstate) + __nvoc_rtti_KernelBif_OBJENGSTATE.offset), pTunableState); -} - static NV_STATUS __nvoc_thunk_OBJENGSTATE_kbifStatePreLoad(POBJGPU pGpu, struct KernelBif *pEngstate, NvU32 arg0) { return engstateStatePreLoad(pGpu, (struct OBJENGSTATE *)(((unsigned char *)pEngstate) + __nvoc_rtti_KernelBif_OBJENGSTATE.offset), arg0); } @@ -122,26 +118,6 @@ return engstateStatePreInitUnlocked(pGpu, (struct OBJENGSTATE *)(((unsigned char *)pEngstate) + __nvoc_rtti_KernelBif_OBJENGSTATE.offset)); } -static NV_STATUS __nvoc_thunk_OBJENGSTATE_kbifGetTunableState(POBJGPU pGpu, struct KernelBif *pEngstate, void *pTunableState) { - return engstateGetTunableState(pGpu, (struct OBJENGSTATE *)(((unsigned char *)pEngstate) + __nvoc_rtti_KernelBif_OBJENGSTATE.offset), pTunableState); -} - -static NV_STATUS __nvoc_thunk_OBJENGSTATE_kbifCompareTunableState(POBJGPU pGpu, struct KernelBif *pEngstate, void *pTunables1, void *pTunables2) { - return engstateCompareTunableState(pGpu, (struct OBJENGSTATE *)(((unsigned char *)pEngstate) + __nvoc_rtti_KernelBif_OBJENGSTATE.offset), pTunables1, pTunables2); -} - -static void __nvoc_thunk_OBJENGSTATE_kbifFreeTunableState(POBJGPU pGpu, struct KernelBif *pEngstate, void *pTunableState) { - engstateFreeTunableState(pGpu, (struct OBJENGSTATE *)(((unsigned char *)pEngstate) + __nvoc_rtti_KernelBif_OBJENGSTATE.offset), pTunableState); -} - -static NV_STATUS __nvoc_thunk_OBJENGSTATE_kbifAllocTunableState(POBJGPU pGpu, struct KernelBif *pEngstate, void **ppTunableState) { - return engstateAllocTunableState(pGpu, (struct OBJENGSTATE *)(((unsigned char *)pEngstate) + __nvoc_rtti_KernelBif_OBJENGSTATE.offset), ppTunableState); -} - -static NV_STATUS __nvoc_thunk_OBJENGSTATE_kbifSetTunableState(POBJGPU pGpu, struct KernelBif *pEngstate, void *pTunableState) { - return engstateSetTunableState(pGpu, (struct OBJENGSTATE *)(((unsigned char *)pEngstate) + __nvoc_rtti_KernelBif_OBJENGSTATE.offset), pTunableState); -} - static NvBool __nvoc_thunk_OBJENGSTATE_kbifIsPresent(POBJGPU pGpu, struct KernelBif *pEngstate) { return engstateIsPresent(pGpu, (struct OBJENGSTATE *)(((unsigned char *)pEngstate) + __nvoc_rtti_KernelBif_OBJENGSTATE.offset)); } @@ -254,271 +230,268 @@ pThis->__kbifStateInitLocked__ = &kbifStateInitLocked_IMPL; // Hal function -- kbifStateLoad - if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000002UL) )) /* RmVariantHal: PF_KERNEL_ONLY */ - { - pThis->__kbifStateLoad__ = &kbifStateLoad_IMPL; - } + pThis->__kbifStateLoad__ = &kbifStateLoad_IMPL; // Hal function -- kbifStatePostLoad - if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000002UL) )) /* RmVariantHal: PF_KERNEL_ONLY */ - { - pThis->__kbifStatePostLoad__ = &kbifStatePostLoad_IMPL; - } + pThis->__kbifStatePostLoad__ = &kbifStatePostLoad_IMPL; // Hal function -- kbifStateUnload - if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000002UL) )) /* RmVariantHal: PF_KERNEL_ONLY */ - { - pThis->__kbifStateUnload__ = &kbifStateUnload_IMPL; - } + pThis->__kbifStateUnload__ = &kbifStateUnload_IMPL; // Hal function -- kbifGetXveStatusBits - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x01f0ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 */ + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ { - pThis->__kbifGetXveStatusBits__ = &kbifGetXveStatusBits_GM107; + pThis->__kbifGetXveStatusBits__ = &kbifGetXveStatusBits_GH100; } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ + else { - pThis->__kbifGetXveStatusBits__ = &kbifGetXveStatusBits_GH100; + pThis->__kbifGetXveStatusBits__ = &kbifGetXveStatusBits_GM107; } // Hal function -- kbifClearXveStatus - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x01f0ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 */ + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ { - pThis->__kbifClearXveStatus__ = &kbifClearXveStatus_GM107; + pThis->__kbifClearXveStatus__ = &kbifClearXveStatus_GH100; } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ + else { - pThis->__kbifClearXveStatus__ = &kbifClearXveStatus_GH100; + pThis->__kbifClearXveStatus__ = &kbifClearXveStatus_GM107; } // Hal function -- kbifGetXveAerBits - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x01f0ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 */ + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ { - pThis->__kbifGetXveAerBits__ = &kbifGetXveAerBits_GM107; + pThis->__kbifGetXveAerBits__ = &kbifGetXveAerBits_GH100; } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ + else { - pThis->__kbifGetXveAerBits__ = &kbifGetXveAerBits_GH100; + pThis->__kbifGetXveAerBits__ = &kbifGetXveAerBits_GM107; } // Hal function -- kbifClearXveAer - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x01f0ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 */ + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ { - pThis->__kbifClearXveAer__ = &kbifClearXveAer_GM107; + pThis->__kbifClearXveAer__ = &kbifClearXveAer_GH100; } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ + else { - pThis->__kbifClearXveAer__ = &kbifClearXveAer_GH100; + pThis->__kbifClearXveAer__ = &kbifClearXveAer_GM107; } // Hal function -- kbifGetPcieConfigAccessTestRegisters - if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000002UL) )) /* RmVariantHal: PF_KERNEL_ONLY */ + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ + { + pThis->__kbifGetPcieConfigAccessTestRegisters__ = &kbifGetPcieConfigAccessTestRegisters_b3696a; + } + else { - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x01f0ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 */ - { - pThis->__kbifGetPcieConfigAccessTestRegisters__ = &kbifGetPcieConfigAccessTestRegisters_GM107; - } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ - { - pThis->__kbifGetPcieConfigAccessTestRegisters__ = &kbifGetPcieConfigAccessTestRegisters_b3696a; - } + pThis->__kbifGetPcieConfigAccessTestRegisters__ = &kbifGetPcieConfigAccessTestRegisters_GM107; } // Hal function -- kbifVerifyPcieConfigAccessTestRegisters - if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000002UL) )) /* RmVariantHal: PF_KERNEL_ONLY */ + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ { - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x01f0ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 */ - { - pThis->__kbifVerifyPcieConfigAccessTestRegisters__ = &kbifVerifyPcieConfigAccessTestRegisters_GM107; - } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ - { - pThis->__kbifVerifyPcieConfigAccessTestRegisters__ = &kbifVerifyPcieConfigAccessTestRegisters_46f6a7; - } + pThis->__kbifVerifyPcieConfigAccessTestRegisters__ = &kbifVerifyPcieConfigAccessTestRegisters_56cd7a; + } + else + { + pThis->__kbifVerifyPcieConfigAccessTestRegisters__ = &kbifVerifyPcieConfigAccessTestRegisters_GM107; } // Hal function -- kbifRearmMSI - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x01f0ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 */ + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ { - pThis->__kbifRearmMSI__ = &kbifRearmMSI_GM107; + pThis->__kbifRearmMSI__ = &kbifRearmMSI_f2d351; } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ + else { - pThis->__kbifRearmMSI__ = &kbifRearmMSI_f2d351; + pThis->__kbifRearmMSI__ = &kbifRearmMSI_GM107; } // Hal function -- kbifIsMSIEnabledInHW - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x01f0ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 */ + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ { - pThis->__kbifIsMSIEnabledInHW__ = &kbifIsMSIEnabledInHW_GM107; + pThis->__kbifIsMSIEnabledInHW__ = &kbifIsMSIEnabledInHW_GH100; } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ + else { - pThis->__kbifIsMSIEnabledInHW__ = &kbifIsMSIEnabledInHW_GH100; + pThis->__kbifIsMSIEnabledInHW__ = &kbifIsMSIEnabledInHW_GM107; } // Hal function -- kbifIsMSIXEnabledInHW - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x01f0ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 */ + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ { - pThis->__kbifIsMSIXEnabledInHW__ = &kbifIsMSIXEnabledInHW_TU102; + pThis->__kbifIsMSIXEnabledInHW__ = &kbifIsMSIXEnabledInHW_GH100; } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ + else { - pThis->__kbifIsMSIXEnabledInHW__ = &kbifIsMSIXEnabledInHW_GH100; + pThis->__kbifIsMSIXEnabledInHW__ = &kbifIsMSIXEnabledInHW_TU102; } // Hal function -- kbifIsPciIoAccessEnabled - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x01f0fbe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 */ + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000400UL) )) /* ChipHal: GA100 | GH100 */ { - pThis->__kbifIsPciIoAccessEnabled__ = &kbifIsPciIoAccessEnabled_GM107; + pThis->__kbifIsPciIoAccessEnabled__ = &kbifIsPciIoAccessEnabled_491d52; } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000400UL) )) /* ChipHal: GA100 | GH100 */ + else { - pThis->__kbifIsPciIoAccessEnabled__ = &kbifIsPciIoAccessEnabled_491d52; + pThis->__kbifIsPciIoAccessEnabled__ = &kbifIsPciIoAccessEnabled_GM107; } // Hal function -- kbifIs3dController - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x01f0ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 */ + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ { - pThis->__kbifIs3dController__ = &kbifIs3dController_GM107; + pThis->__kbifIs3dController__ = &kbifIs3dController_GH100; } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ + else { - pThis->__kbifIs3dController__ = &kbifIs3dController_GH100; + pThis->__kbifIs3dController__ = &kbifIs3dController_GM107; } // Hal function -- kbifExecC73War - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x01f0ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 */ + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ { - pThis->__kbifExecC73War__ = &kbifExecC73War_GM107; + pThis->__kbifExecC73War__ = &kbifExecC73War_b3696a; } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ + else { - pThis->__kbifExecC73War__ = &kbifExecC73War_b3696a; + pThis->__kbifExecC73War__ = &kbifExecC73War_GM107; } // Hal function -- kbifEnableExtendedTagSupport - if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000002UL) )) /* RmVariantHal: PF_KERNEL_ONLY */ + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ + { + pThis->__kbifEnableExtendedTagSupport__ = &kbifEnableExtendedTagSupport_GH100; + } + // default + else { - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ - { - pThis->__kbifEnableExtendedTagSupport__ = &kbifEnableExtendedTagSupport_GH100; - } - // default - else - { - pThis->__kbifEnableExtendedTagSupport__ = &kbifEnableExtendedTagSupport_b3696a; - } + pThis->__kbifEnableExtendedTagSupport__ = &kbifEnableExtendedTagSupport_b3696a; } // Hal function -- kbifPcieConfigEnableRelaxedOrdering - if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000002UL) )) /* RmVariantHal: PF_KERNEL_ONLY */ + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ + { + pThis->__kbifPcieConfigEnableRelaxedOrdering__ = &kbifPcieConfigEnableRelaxedOrdering_GH100; + } + else { - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x01f0ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 */ - { - pThis->__kbifPcieConfigEnableRelaxedOrdering__ = &kbifPcieConfigEnableRelaxedOrdering_GM107; - } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ - { - pThis->__kbifPcieConfigEnableRelaxedOrdering__ = &kbifPcieConfigEnableRelaxedOrdering_GH100; - } + pThis->__kbifPcieConfigEnableRelaxedOrdering__ = &kbifPcieConfigEnableRelaxedOrdering_GM107; } // Hal function -- kbifPcieConfigDisableRelaxedOrdering - if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000002UL) )) /* RmVariantHal: PF_KERNEL_ONLY */ + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ { - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x01f0ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 */ - { - pThis->__kbifPcieConfigDisableRelaxedOrdering__ = &kbifPcieConfigDisableRelaxedOrdering_GM107; - } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ - { - pThis->__kbifPcieConfigDisableRelaxedOrdering__ = &kbifPcieConfigDisableRelaxedOrdering_GH100; - } + pThis->__kbifPcieConfigDisableRelaxedOrdering__ = &kbifPcieConfigDisableRelaxedOrdering_GH100; + } + else + { + pThis->__kbifPcieConfigDisableRelaxedOrdering__ = &kbifPcieConfigDisableRelaxedOrdering_GM107; } // Hal function -- kbifInitRelaxedOrderingFromEmulatedConfigSpace - if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000002UL) )) /* RmVariantHal: PF_KERNEL_ONLY */ + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0000fc00UL) )) /* ChipHal: GA100 | GA102 | GA103 | GA104 | GA106 | GA107 */ + { + pThis->__kbifInitRelaxedOrderingFromEmulatedConfigSpace__ = &kbifInitRelaxedOrderingFromEmulatedConfigSpace_GA100; + } + // default + else { - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0000fc00UL) )) /* ChipHal: GA100 | GA102 | GA103 | GA104 | GA106 | GA107 */ - { - pThis->__kbifInitRelaxedOrderingFromEmulatedConfigSpace__ = &kbifInitRelaxedOrderingFromEmulatedConfigSpace_GA100; - } - // default - else - { - pThis->__kbifInitRelaxedOrderingFromEmulatedConfigSpace__ = &kbifInitRelaxedOrderingFromEmulatedConfigSpace_b3696a; - } + pThis->__kbifInitRelaxedOrderingFromEmulatedConfigSpace__ = &kbifInitRelaxedOrderingFromEmulatedConfigSpace_b3696a; } // Hal function -- kbifEnableNoSnoop - if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000002UL) )) /* RmVariantHal: PF_KERNEL_ONLY */ + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ + { + pThis->__kbifEnableNoSnoop__ = &kbifEnableNoSnoop_GH100; + } + else { - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x01f0ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 */ - { - pThis->__kbifEnableNoSnoop__ = &kbifEnableNoSnoop_GM107; - } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ - { - pThis->__kbifEnableNoSnoop__ = &kbifEnableNoSnoop_GH100; - } + pThis->__kbifEnableNoSnoop__ = &kbifEnableNoSnoop_GM107; } // Hal function -- kbifApplyWARBug3208922 - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x01f0fc00UL) )) /* ChipHal: GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 */ + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x100003e0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GH100 */ { - pThis->__kbifApplyWARBug3208922__ = &kbifApplyWARBug3208922_GA100; + pThis->__kbifApplyWARBug3208922__ = &kbifApplyWARBug3208922_b3696a; } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x100003e0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GH100 */ + else { - pThis->__kbifApplyWARBug3208922__ = &kbifApplyWARBug3208922_b3696a; + pThis->__kbifApplyWARBug3208922__ = &kbifApplyWARBug3208922_GA100; } // Hal function -- kbifProbePcieReqAtomicCaps - if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000002UL) )) /* RmVariantHal: PF_KERNEL_ONLY */ + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ + { + pThis->__kbifProbePcieReqAtomicCaps__ = &kbifProbePcieReqAtomicCaps_GH100; + } + // default + else { - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ - { - pThis->__kbifProbePcieReqAtomicCaps__ = &kbifProbePcieReqAtomicCaps_GH100; - } - // default - else - { - pThis->__kbifProbePcieReqAtomicCaps__ = &kbifProbePcieReqAtomicCaps_b3696a; - } + pThis->__kbifProbePcieReqAtomicCaps__ = &kbifProbePcieReqAtomicCaps_b3696a; } - // Hal function -- kbifGetPciConfigSpacePriMirror - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x01f0ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 */ + // Hal function -- kbifEnablePcieAtomics + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ { - pThis->__kbifGetPciConfigSpacePriMirror__ = &kbifGetPciConfigSpacePriMirror_GM107; + pThis->__kbifEnablePcieAtomics__ = &kbifEnablePcieAtomics_GH100; } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ + // default + else + { + pThis->__kbifEnablePcieAtomics__ = &kbifEnablePcieAtomics_b3696a; + } + + // Hal function -- kbifGetPciConfigSpacePriMirror + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ { pThis->__kbifGetPciConfigSpacePriMirror__ = &kbifGetPciConfigSpacePriMirror_GH100; } + else + { + pThis->__kbifGetPciConfigSpacePriMirror__ = &kbifGetPciConfigSpacePriMirror_GM107; + } // Hal function -- kbifGetBusOptionsAddr - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x01f0ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 */ + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ + { + pThis->__kbifGetBusOptionsAddr__ = &kbifGetBusOptionsAddr_GH100; + } + else { pThis->__kbifGetBusOptionsAddr__ = &kbifGetBusOptionsAddr_GM107; } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ + + // Hal function -- kbifPreOsGlobalErotGrantRequest + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x01f00000UL) )) /* ChipHal: AD102 | AD103 | AD104 | AD106 | AD107 */ { - pThis->__kbifGetBusOptionsAddr__ = &kbifGetBusOptionsAddr_GH100; + pThis->__kbifPreOsGlobalErotGrantRequest__ = &kbifPreOsGlobalErotGrantRequest_AD102; + } + // default + else + { + pThis->__kbifPreOsGlobalErotGrantRequest__ = &kbifPreOsGlobalErotGrantRequest_56cd7a; } // Hal function -- kbifCacheVFInfo - if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000002UL) )) /* RmVariantHal: PF_KERNEL_ONLY */ + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ { - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x01f0ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 */ - { - pThis->__kbifCacheVFInfo__ = &kbifCacheVFInfo_TU102; - } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ - { - pThis->__kbifCacheVFInfo__ = &kbifCacheVFInfo_GH100; - } + pThis->__kbifCacheVFInfo__ = &kbifCacheVFInfo_GH100; + } + else + { + pThis->__kbifCacheVFInfo__ = &kbifCacheVFInfo_TU102; + } + + // Hal function -- kbifGetEccCounts + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ + { + pThis->__kbifGetEccCounts__ = &kbifGetEccCounts_GH100; + } + // default + else + { + pThis->__kbifGetEccCounts__ = &kbifGetEccCounts_4a4dee; } pThis->__nvoc_base_OBJENGSTATE.__engstateConstructEngine__ = &__nvoc_thunk_KernelBif_engstateConstructEngine; @@ -531,8 +504,6 @@ pThis->__nvoc_base_OBJENGSTATE.__engstateStateUnload__ = &__nvoc_thunk_KernelBif_engstateStateUnload; - pThis->__kbifReconcileTunableState__ = &__nvoc_thunk_OBJENGSTATE_kbifReconcileTunableState; - pThis->__kbifStatePreLoad__ = &__nvoc_thunk_OBJENGSTATE_kbifStatePreLoad; pThis->__kbifStatePostUnload__ = &__nvoc_thunk_OBJENGSTATE_kbifStatePostUnload; @@ -549,16 +520,6 @@ pThis->__kbifStatePreInitUnlocked__ = &__nvoc_thunk_OBJENGSTATE_kbifStatePreInitUnlocked; - pThis->__kbifGetTunableState__ = &__nvoc_thunk_OBJENGSTATE_kbifGetTunableState; - - pThis->__kbifCompareTunableState__ = &__nvoc_thunk_OBJENGSTATE_kbifCompareTunableState; - - pThis->__kbifFreeTunableState__ = &__nvoc_thunk_OBJENGSTATE_kbifFreeTunableState; - - pThis->__kbifAllocTunableState__ = &__nvoc_thunk_OBJENGSTATE_kbifAllocTunableState; - - pThis->__kbifSetTunableState__ = &__nvoc_thunk_OBJENGSTATE_kbifSetTunableState; - pThis->__kbifIsPresent__ = &__nvoc_thunk_OBJENGSTATE_kbifIsPresent; } @@ -581,13 +542,16 @@ KernelBif *pThis; RmHalspecOwner *pRmhalspecowner; - pThis = portMemAllocNonPaged(sizeof(KernelBif)); - if (pThis == NULL) return NV_ERR_NO_MEMORY; + status = __nvoc_handleObjCreateMemAlloc(createFlags, sizeof(KernelBif), (void**)&pThis, (void**)ppThis); + if (status != NV_OK) + return status; portMemSet(pThis, 0, sizeof(KernelBif)); __nvoc_initRtti(staticCast(pThis, Dynamic), &__nvoc_class_def_KernelBif); + pThis->__nvoc_base_OBJENGSTATE.__nvoc_base_Object.createFlags = createFlags; + if (pParent != NULL && !(createFlags & NVOC_OBJ_CREATE_FLAGS_PARENT_HALSPEC_ONLY)) { pParentObj = dynamicCast(pParent, Object); @@ -607,11 +571,17 @@ if (status != NV_OK) goto __nvoc_objCreate_KernelBif_cleanup; *ppThis = pThis; + return NV_OK; __nvoc_objCreate_KernelBif_cleanup: // do not call destructors here since the constructor already called them - portMemFree(pThis); + if (createFlags & NVOC_OBJ_CREATE_FLAGS_IN_PLACE_CONSTRUCT) + portMemSet(pThis, 0, sizeof(KernelBif)); + else + portMemFree(pThis); + + // coverity[leaked_storage:FALSE] return status; } diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/generated/g_kernel_bif_nvoc.h nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_kernel_bif_nvoc.h --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/generated/g_kernel_bif_nvoc.h 2023-10-25 20:27:05.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_kernel_bif_nvoc.h 2024-03-05 22:18:24.000000000 +0000 @@ -7,7 +7,7 @@ #endif /* - * SPDX-FileCopyrightText: Copyright (c) 2013-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2013-2024 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -111,10 +111,12 @@ NV_STATUS (*__kbifEnableNoSnoop__)(struct OBJGPU *, struct KernelBif *, NvBool); void (*__kbifApplyWARBug3208922__)(struct OBJGPU *, struct KernelBif *); void (*__kbifProbePcieReqAtomicCaps__)(struct OBJGPU *, struct KernelBif *); + void (*__kbifEnablePcieAtomics__)(struct OBJGPU *, struct KernelBif *); NV_STATUS (*__kbifGetPciConfigSpacePriMirror__)(struct OBJGPU *, struct KernelBif *, NvU32 *, NvU32 *); NV_STATUS (*__kbifGetBusOptionsAddr__)(struct OBJGPU *, struct KernelBif *, BUS_OPTIONS, NvU32 *); + NV_STATUS (*__kbifPreOsGlobalErotGrantRequest__)(struct OBJGPU *, struct KernelBif *); void (*__kbifCacheVFInfo__)(struct OBJGPU *, struct KernelBif *); - NV_STATUS (*__kbifReconcileTunableState__)(POBJGPU, struct KernelBif *, void *); + NvU32 (*__kbifGetEccCounts__)(struct OBJGPU *, struct KernelBif *); NV_STATUS (*__kbifStatePreLoad__)(POBJGPU, struct KernelBif *, NvU32); NV_STATUS (*__kbifStatePostUnload__)(POBJGPU, struct KernelBif *, NvU32); void (*__kbifStateDestroy__)(POBJGPU, struct KernelBif *); @@ -123,11 +125,6 @@ void (*__kbifInitMissing__)(POBJGPU, struct KernelBif *); NV_STATUS (*__kbifStatePreInitLocked__)(POBJGPU, struct KernelBif *); NV_STATUS (*__kbifStatePreInitUnlocked__)(POBJGPU, struct KernelBif *); - NV_STATUS (*__kbifGetTunableState__)(POBJGPU, struct KernelBif *, void *); - NV_STATUS (*__kbifCompareTunableState__)(POBJGPU, struct KernelBif *, void *, void *); - void (*__kbifFreeTunableState__)(POBJGPU, struct KernelBif *, void *); - NV_STATUS (*__kbifAllocTunableState__)(POBJGPU, struct KernelBif *, void **); - NV_STATUS (*__kbifSetTunableState__)(POBJGPU, struct KernelBif *, void *); NvBool (*__kbifIsPresent__)(POBJGPU, struct KernelBif *); NvBool PDB_PROP_KBIF_CHECK_IF_GPU_EXISTS_DEF; NvBool PDB_PROP_KBIF_IS_MSI_ENABLED; @@ -143,6 +140,7 @@ NvBool PDB_PROP_KBIF_SUPPORT_NONCOHERENT; NvBool PDB_PROP_KBIF_PCIE_GEN4_CAPABLE; NvBool PDB_PROP_KBIF_PCIE_RELAXED_ORDERING_SET_IN_EMULATED_CONFIG_SPACE; + NvBool PDB_PROP_KBIF_SYSTEM_ACCESS_DISABLED; NvU32 dmaCaps; RmPhysAddr dmaWindowStartAddress; NvU32 p2pOverride; @@ -150,6 +148,7 @@ NvBool peerMappingOverride; NvBool EnteredRecoverySinceErrorsLastChecked; NvU32 osPcieAtomicsOpMask; + NvBool bMnocAvailable; }; #ifndef __NVOC_CLASS_KernelBif_TYPEDEF__ @@ -187,6 +186,8 @@ #define PDB_PROP_KBIF_IS_MSI_ENABLED_BASE_NAME PDB_PROP_KBIF_IS_MSI_ENABLED #define PDB_PROP_KBIF_PCIE_RELAXED_ORDERING_SET_IN_EMULATED_CONFIG_SPACE_BASE_CAST #define PDB_PROP_KBIF_PCIE_RELAXED_ORDERING_SET_IN_EMULATED_CONFIG_SPACE_BASE_NAME PDB_PROP_KBIF_PCIE_RELAXED_ORDERING_SET_IN_EMULATED_CONFIG_SPACE +#define PDB_PROP_KBIF_SYSTEM_ACCESS_DISABLED_BASE_CAST +#define PDB_PROP_KBIF_SYSTEM_ACCESS_DISABLED_BASE_NAME PDB_PROP_KBIF_SYSTEM_ACCESS_DISABLED #define PDB_PROP_KBIF_UPSTREAM_LTR_SUPPORT_WAR_BUG_200634944_BASE_CAST #define PDB_PROP_KBIF_UPSTREAM_LTR_SUPPORT_WAR_BUG_200634944_BASE_NAME PDB_PROP_KBIF_UPSTREAM_LTR_SUPPORT_WAR_BUG_200634944 #define PDB_PROP_KBIF_IS_MSIX_CACHED_BASE_CAST @@ -256,13 +257,18 @@ #define kbifApplyWARBug3208922_HAL(pGpu, pKernelBif) kbifApplyWARBug3208922_DISPATCH(pGpu, pKernelBif) #define kbifProbePcieReqAtomicCaps(pGpu, pKernelBif) kbifProbePcieReqAtomicCaps_DISPATCH(pGpu, pKernelBif) #define kbifProbePcieReqAtomicCaps_HAL(pGpu, pKernelBif) kbifProbePcieReqAtomicCaps_DISPATCH(pGpu, pKernelBif) +#define kbifEnablePcieAtomics(pGpu, pKernelBif) kbifEnablePcieAtomics_DISPATCH(pGpu, pKernelBif) +#define kbifEnablePcieAtomics_HAL(pGpu, pKernelBif) kbifEnablePcieAtomics_DISPATCH(pGpu, pKernelBif) #define kbifGetPciConfigSpacePriMirror(pGpu, pKernelBif, pMirrorBase, pMirrorSize) kbifGetPciConfigSpacePriMirror_DISPATCH(pGpu, pKernelBif, pMirrorBase, pMirrorSize) #define kbifGetPciConfigSpacePriMirror_HAL(pGpu, pKernelBif, pMirrorBase, pMirrorSize) kbifGetPciConfigSpacePriMirror_DISPATCH(pGpu, pKernelBif, pMirrorBase, pMirrorSize) #define kbifGetBusOptionsAddr(pGpu, pKernelBif, options, addrReg) kbifGetBusOptionsAddr_DISPATCH(pGpu, pKernelBif, options, addrReg) #define kbifGetBusOptionsAddr_HAL(pGpu, pKernelBif, options, addrReg) kbifGetBusOptionsAddr_DISPATCH(pGpu, pKernelBif, options, addrReg) +#define kbifPreOsGlobalErotGrantRequest(pGpu, pKernelBif) kbifPreOsGlobalErotGrantRequest_DISPATCH(pGpu, pKernelBif) +#define kbifPreOsGlobalErotGrantRequest_HAL(pGpu, pKernelBif) kbifPreOsGlobalErotGrantRequest_DISPATCH(pGpu, pKernelBif) #define kbifCacheVFInfo(pGpu, pKernelBif) kbifCacheVFInfo_DISPATCH(pGpu, pKernelBif) #define kbifCacheVFInfo_HAL(pGpu, pKernelBif) kbifCacheVFInfo_DISPATCH(pGpu, pKernelBif) -#define kbifReconcileTunableState(pGpu, pEngstate, pTunableState) kbifReconcileTunableState_DISPATCH(pGpu, pEngstate, pTunableState) +#define kbifGetEccCounts(pGpu, pKernelBif) kbifGetEccCounts_DISPATCH(pGpu, pKernelBif) +#define kbifGetEccCounts_HAL(pGpu, pKernelBif) kbifGetEccCounts_DISPATCH(pGpu, pKernelBif) #define kbifStatePreLoad(pGpu, pEngstate, arg0) kbifStatePreLoad_DISPATCH(pGpu, pEngstate, arg0) #define kbifStatePostUnload(pGpu, pEngstate, arg0) kbifStatePostUnload_DISPATCH(pGpu, pEngstate, arg0) #define kbifStateDestroy(pGpu, pEngstate) kbifStateDestroy_DISPATCH(pGpu, pEngstate) @@ -271,11 +277,6 @@ #define kbifInitMissing(pGpu, pEngstate) kbifInitMissing_DISPATCH(pGpu, pEngstate) #define kbifStatePreInitLocked(pGpu, pEngstate) kbifStatePreInitLocked_DISPATCH(pGpu, pEngstate) #define kbifStatePreInitUnlocked(pGpu, pEngstate) kbifStatePreInitUnlocked_DISPATCH(pGpu, pEngstate) -#define kbifGetTunableState(pGpu, pEngstate, pTunableState) kbifGetTunableState_DISPATCH(pGpu, pEngstate, pTunableState) -#define kbifCompareTunableState(pGpu, pEngstate, pTunables1, pTunables2) kbifCompareTunableState_DISPATCH(pGpu, pEngstate, pTunables1, pTunables2) -#define kbifFreeTunableState(pGpu, pEngstate, pTunableState) kbifFreeTunableState_DISPATCH(pGpu, pEngstate, pTunableState) -#define kbifAllocTunableState(pGpu, pEngstate, ppTunableState) kbifAllocTunableState_DISPATCH(pGpu, pEngstate, ppTunableState) -#define kbifSetTunableState(pGpu, pEngstate, pTunableState) kbifSetTunableState_DISPATCH(pGpu, pEngstate, pTunableState) #define kbifIsPresent(pGpu, pEngstate) kbifIsPresent_DISPATCH(pGpu, pEngstate) static inline NvU32 kbifGetBusIntfType_2f2c74(struct KernelBif *pKernelBif) { return (3); @@ -332,33 +333,48 @@ #define kbifDisableP2PTransactions_HAL(pGpu, pKernelBif) kbifDisableP2PTransactions(pGpu, pKernelBif) -NV_STATUS kbifGetNumVFSparseMmapRegions_TU102(struct OBJGPU *pGpu, struct KernelBif *pKernelBif, KERNEL_HOST_VGPU_DEVICE *pKernelHostVgpuDevice, NvU32 *numAreas); +NV_STATUS kbifGetVFSparseMmapRegions_TU102(struct OBJGPU *pGpu, struct KernelBif *pKernelBif, KERNEL_HOST_VGPU_DEVICE *pKernelHostVgpuDevice, NvU64 osPageSize, NvU32 *pNumAreas, NvU64 *pOffsets, NvU64 *pSizes); #ifdef __nvoc_kernel_bif_h_disabled -static inline NV_STATUS kbifGetNumVFSparseMmapRegions(struct OBJGPU *pGpu, struct KernelBif *pKernelBif, KERNEL_HOST_VGPU_DEVICE *pKernelHostVgpuDevice, NvU32 *numAreas) { +static inline NV_STATUS kbifGetVFSparseMmapRegions(struct OBJGPU *pGpu, struct KernelBif *pKernelBif, KERNEL_HOST_VGPU_DEVICE *pKernelHostVgpuDevice, NvU64 osPageSize, NvU32 *pNumAreas, NvU64 *pOffsets, NvU64 *pSizes) { NV_ASSERT_FAILED_PRECOMP("KernelBif was disabled!"); return NV_ERR_NOT_SUPPORTED; } #else //__nvoc_kernel_bif_h_disabled -#define kbifGetNumVFSparseMmapRegions(pGpu, pKernelBif, pKernelHostVgpuDevice, numAreas) kbifGetNumVFSparseMmapRegions_TU102(pGpu, pKernelBif, pKernelHostVgpuDevice, numAreas) +#define kbifGetVFSparseMmapRegions(pGpu, pKernelBif, pKernelHostVgpuDevice, osPageSize, pNumAreas, pOffsets, pSizes) kbifGetVFSparseMmapRegions_TU102(pGpu, pKernelBif, pKernelHostVgpuDevice, osPageSize, pNumAreas, pOffsets, pSizes) #endif //__nvoc_kernel_bif_h_disabled -#define kbifGetNumVFSparseMmapRegions_HAL(pGpu, pKernelBif, pKernelHostVgpuDevice, numAreas) kbifGetNumVFSparseMmapRegions(pGpu, pKernelBif, pKernelHostVgpuDevice, numAreas) +#define kbifGetVFSparseMmapRegions_HAL(pGpu, pKernelBif, pKernelHostVgpuDevice, osPageSize, pNumAreas, pOffsets, pSizes) kbifGetVFSparseMmapRegions(pGpu, pKernelBif, pKernelHostVgpuDevice, osPageSize, pNumAreas, pOffsets, pSizes) -NV_STATUS kbifGetVFSparseMmapRegions_TU102(struct OBJGPU *pGpu, struct KernelBif *pKernelBif, KERNEL_HOST_VGPU_DEVICE *pKernelHostVgpuDevice, NvU64 os_page_size, NvU64 *offsets, NvU64 *sizes); +NV_STATUS kbifDisableSysmemAccess_GM107(struct OBJGPU *pGpu, struct KernelBif *pKernelBif, NvBool bDisable); #ifdef __nvoc_kernel_bif_h_disabled -static inline NV_STATUS kbifGetVFSparseMmapRegions(struct OBJGPU *pGpu, struct KernelBif *pKernelBif, KERNEL_HOST_VGPU_DEVICE *pKernelHostVgpuDevice, NvU64 os_page_size, NvU64 *offsets, NvU64 *sizes) { +static inline NV_STATUS kbifDisableSysmemAccess(struct OBJGPU *pGpu, struct KernelBif *pKernelBif, NvBool bDisable) { NV_ASSERT_FAILED_PRECOMP("KernelBif was disabled!"); return NV_ERR_NOT_SUPPORTED; } #else //__nvoc_kernel_bif_h_disabled -#define kbifGetVFSparseMmapRegions(pGpu, pKernelBif, pKernelHostVgpuDevice, os_page_size, offsets, sizes) kbifGetVFSparseMmapRegions_TU102(pGpu, pKernelBif, pKernelHostVgpuDevice, os_page_size, offsets, sizes) +#define kbifDisableSysmemAccess(pGpu, pKernelBif, bDisable) kbifDisableSysmemAccess_GM107(pGpu, pKernelBif, bDisable) #endif //__nvoc_kernel_bif_h_disabled -#define kbifGetVFSparseMmapRegions_HAL(pGpu, pKernelBif, pKernelHostVgpuDevice, os_page_size, offsets, sizes) kbifGetVFSparseMmapRegions(pGpu, pKernelBif, pKernelHostVgpuDevice, os_page_size, offsets, sizes) +#define kbifDisableSysmemAccess_HAL(pGpu, pKernelBif, bDisable) kbifDisableSysmemAccess(pGpu, pKernelBif, bDisable) + +static inline void kbifIsMnocSupported_b3696a(struct OBJGPU *pGpu, struct KernelBif *pKernelBif) { + return; +} + + +#ifdef __nvoc_kernel_bif_h_disabled +static inline void kbifIsMnocSupported(struct OBJGPU *pGpu, struct KernelBif *pKernelBif) { + NV_ASSERT_FAILED_PRECOMP("KernelBif was disabled!"); +} +#else //__nvoc_kernel_bif_h_disabled +#define kbifIsMnocSupported(pGpu, pKernelBif) kbifIsMnocSupported_b3696a(pGpu, pKernelBif) +#endif //__nvoc_kernel_bif_h_disabled + +#define kbifIsMnocSupported_HAL(pGpu, pKernelBif) kbifIsMnocSupported(pGpu, pKernelBif) NV_STATUS kbifConstructEngine_IMPL(struct OBJGPU *pGpu, struct KernelBif *pKernelBif, ENGDESCRIPTOR arg0); @@ -434,8 +450,8 @@ NV_STATUS kbifVerifyPcieConfigAccessTestRegisters_GM107(struct OBJGPU *pGpu, struct KernelBif *pKernelBif, NvU32 nvXveId, NvU32 nvXveVccapHdr); -static inline NV_STATUS kbifVerifyPcieConfigAccessTestRegisters_46f6a7(struct OBJGPU *pGpu, struct KernelBif *pKernelBif, NvU32 nvXveId, NvU32 nvXveVccapHdr) { - return NV_ERR_NOT_SUPPORTED; +static inline NV_STATUS kbifVerifyPcieConfigAccessTestRegisters_56cd7a(struct OBJGPU *pGpu, struct KernelBif *pKernelBif, NvU32 nvXveId, NvU32 nvXveVccapHdr) { + return NV_OK; } static inline NV_STATUS kbifVerifyPcieConfigAccessTestRegisters_DISPATCH(struct OBJGPU *pGpu, struct KernelBif *pKernelBif, NvU32 nvXveId, NvU32 nvXveVccapHdr) { @@ -560,6 +576,16 @@ pKernelBif->__kbifProbePcieReqAtomicCaps__(pGpu, pKernelBif); } +void kbifEnablePcieAtomics_GH100(struct OBJGPU *pGpu, struct KernelBif *pKernelBif); + +static inline void kbifEnablePcieAtomics_b3696a(struct OBJGPU *pGpu, struct KernelBif *pKernelBif) { + return; +} + +static inline void kbifEnablePcieAtomics_DISPATCH(struct OBJGPU *pGpu, struct KernelBif *pKernelBif) { + pKernelBif->__kbifEnablePcieAtomics__(pGpu, pKernelBif); +} + NV_STATUS kbifGetPciConfigSpacePriMirror_GM107(struct OBJGPU *pGpu, struct KernelBif *pKernelBif, NvU32 *pMirrorBase, NvU32 *pMirrorSize); NV_STATUS kbifGetPciConfigSpacePriMirror_GH100(struct OBJGPU *pGpu, struct KernelBif *pKernelBif, NvU32 *pMirrorBase, NvU32 *pMirrorSize); @@ -576,6 +602,16 @@ return pKernelBif->__kbifGetBusOptionsAddr__(pGpu, pKernelBif, options, addrReg); } +NV_STATUS kbifPreOsGlobalErotGrantRequest_AD102(struct OBJGPU *pGpu, struct KernelBif *pKernelBif); + +static inline NV_STATUS kbifPreOsGlobalErotGrantRequest_56cd7a(struct OBJGPU *pGpu, struct KernelBif *pKernelBif) { + return NV_OK; +} + +static inline NV_STATUS kbifPreOsGlobalErotGrantRequest_DISPATCH(struct OBJGPU *pGpu, struct KernelBif *pKernelBif) { + return pKernelBif->__kbifPreOsGlobalErotGrantRequest__(pGpu, pKernelBif); +} + void kbifCacheVFInfo_TU102(struct OBJGPU *pGpu, struct KernelBif *pKernelBif); void kbifCacheVFInfo_GH100(struct OBJGPU *pGpu, struct KernelBif *pKernelBif); @@ -584,8 +620,14 @@ pKernelBif->__kbifCacheVFInfo__(pGpu, pKernelBif); } -static inline NV_STATUS kbifReconcileTunableState_DISPATCH(POBJGPU pGpu, struct KernelBif *pEngstate, void *pTunableState) { - return pEngstate->__kbifReconcileTunableState__(pGpu, pEngstate, pTunableState); +NvU32 kbifGetEccCounts_GH100(struct OBJGPU *pGpu, struct KernelBif *pKernelBif); + +static inline NvU32 kbifGetEccCounts_4a4dee(struct OBJGPU *pGpu, struct KernelBif *pKernelBif) { + return 0; +} + +static inline NvU32 kbifGetEccCounts_DISPATCH(struct OBJGPU *pGpu, struct KernelBif *pKernelBif) { + return pKernelBif->__kbifGetEccCounts__(pGpu, pKernelBif); } static inline NV_STATUS kbifStatePreLoad_DISPATCH(POBJGPU pGpu, struct KernelBif *pEngstate, NvU32 arg0) { @@ -620,26 +662,6 @@ return pEngstate->__kbifStatePreInitUnlocked__(pGpu, pEngstate); } -static inline NV_STATUS kbifGetTunableState_DISPATCH(POBJGPU pGpu, struct KernelBif *pEngstate, void *pTunableState) { - return pEngstate->__kbifGetTunableState__(pGpu, pEngstate, pTunableState); -} - -static inline NV_STATUS kbifCompareTunableState_DISPATCH(POBJGPU pGpu, struct KernelBif *pEngstate, void *pTunables1, void *pTunables2) { - return pEngstate->__kbifCompareTunableState__(pGpu, pEngstate, pTunables1, pTunables2); -} - -static inline void kbifFreeTunableState_DISPATCH(POBJGPU pGpu, struct KernelBif *pEngstate, void *pTunableState) { - pEngstate->__kbifFreeTunableState__(pGpu, pEngstate, pTunableState); -} - -static inline NV_STATUS kbifAllocTunableState_DISPATCH(POBJGPU pGpu, struct KernelBif *pEngstate, void **ppTunableState) { - return pEngstate->__kbifAllocTunableState__(pGpu, pEngstate, ppTunableState); -} - -static inline NV_STATUS kbifSetTunableState_DISPATCH(POBJGPU pGpu, struct KernelBif *pEngstate, void *pTunableState) { - return pEngstate->__kbifSetTunableState__(pGpu, pEngstate, pTunableState); -} - static inline NvBool kbifIsPresent_DISPATCH(POBJGPU pGpu, struct KernelBif *pEngstate) { return pEngstate->__kbifIsPresent__(pGpu, pEngstate); } @@ -697,6 +719,39 @@ #define kbifIsMSIXEnabled(pGpu, pKernelBif) kbifIsMSIXEnabled_IMPL(pGpu, pKernelBif) #endif //__nvoc_kernel_bif_h_disabled +NV_STATUS kbifPollDeviceOnBus_IMPL(struct OBJGPU *pGpu, struct KernelBif *pKernelBif); + +#ifdef __nvoc_kernel_bif_h_disabled +static inline NV_STATUS kbifPollDeviceOnBus(struct OBJGPU *pGpu, struct KernelBif *pKernelBif) { + NV_ASSERT_FAILED_PRECOMP("KernelBif was disabled!"); + return NV_ERR_NOT_SUPPORTED; +} +#else //__nvoc_kernel_bif_h_disabled +#define kbifPollDeviceOnBus(pGpu, pKernelBif) kbifPollDeviceOnBus_IMPL(pGpu, pKernelBif) +#endif //__nvoc_kernel_bif_h_disabled + +NvU32 kbifGetGpuLinkCapabilities_IMPL(struct OBJGPU *pGpu, struct KernelBif *pKernelBif); + +#ifdef __nvoc_kernel_bif_h_disabled +static inline NvU32 kbifGetGpuLinkCapabilities(struct OBJGPU *pGpu, struct KernelBif *pKernelBif) { + NV_ASSERT_FAILED_PRECOMP("KernelBif was disabled!"); + return 0; +} +#else //__nvoc_kernel_bif_h_disabled +#define kbifGetGpuLinkCapabilities(pGpu, pKernelBif) kbifGetGpuLinkCapabilities_IMPL(pGpu, pKernelBif) +#endif //__nvoc_kernel_bif_h_disabled + +NvU32 kbifGetGpuLinkControlStatus_IMPL(struct OBJGPU *pGpu, struct KernelBif *pKernelBif); + +#ifdef __nvoc_kernel_bif_h_disabled +static inline NvU32 kbifGetGpuLinkControlStatus(struct OBJGPU *pGpu, struct KernelBif *pKernelBif) { + NV_ASSERT_FAILED_PRECOMP("KernelBif was disabled!"); + return 0; +} +#else //__nvoc_kernel_bif_h_disabled +#define kbifGetGpuLinkControlStatus(pGpu, pKernelBif) kbifGetGpuLinkControlStatus_IMPL(pGpu, pKernelBif) +#endif //__nvoc_kernel_bif_h_disabled + NvBool kbifIsPciBusFamily_IMPL(struct KernelBif *pKernelBif); #ifdef __nvoc_kernel_bif_h_disabled diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/generated/g_kernel_ccu_api_nvoc.c nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_kernel_ccu_api_nvoc.c --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/generated/g_kernel_ccu_api_nvoc.c 2023-10-25 20:27:05.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_kernel_ccu_api_nvoc.c 2024-03-05 22:18:24.000000000 +0000 @@ -113,36 +113,20 @@ return gpuresShareCallback((struct GpuResource *)(((unsigned char *)pGpuResource) + __nvoc_rtti_KernelCcuApi_GpuResource.offset), pInvokingClient, pParentRef, pSharePolicy); } -static NV_STATUS __nvoc_thunk_GpuResource_kccuapiControl(struct KernelCcuApi *pGpuResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { - return gpuresControl((struct GpuResource *)(((unsigned char *)pGpuResource) + __nvoc_rtti_KernelCcuApi_GpuResource.offset), pCallContext, pParams); -} - -static NV_STATUS __nvoc_thunk_RmResource_kccuapiGetMemInterMapParams(struct KernelCcuApi *pRmResource, RMRES_MEM_INTER_MAP_PARAMS *pParams) { - return rmresGetMemInterMapParams((struct RmResource *)(((unsigned char *)pRmResource) + __nvoc_rtti_KernelCcuApi_RmResource.offset), pParams); -} - -static NvHandle __nvoc_thunk_GpuResource_kccuapiGetInternalObjectHandle(struct KernelCcuApi *pGpuResource) { - return gpuresGetInternalObjectHandle((struct GpuResource *)(((unsigned char *)pGpuResource) + __nvoc_rtti_KernelCcuApi_GpuResource.offset)); -} - -static NV_STATUS __nvoc_thunk_RsResource_kccuapiControlFilter(struct KernelCcuApi *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { - return resControlFilter((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_KernelCcuApi_RsResource.offset), pCallContext, pParams); +static NV_STATUS __nvoc_thunk_RmResource_kccuapiCheckMemInterUnmap(struct KernelCcuApi *pRmResource, NvBool bSubdeviceHandleProvided) { + return rmresCheckMemInterUnmap((struct RmResource *)(((unsigned char *)pRmResource) + __nvoc_rtti_KernelCcuApi_RmResource.offset), bSubdeviceHandleProvided); } -static void __nvoc_thunk_RsResource_kccuapiAddAdditionalDependants(struct RsClient *pClient, struct KernelCcuApi *pResource, RsResourceRef *pReference) { - resAddAdditionalDependants(pClient, (struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_KernelCcuApi_RsResource.offset), pReference); +static NV_STATUS __nvoc_thunk_RsResource_kccuapiMapTo(struct KernelCcuApi *pResource, RS_RES_MAP_TO_PARAMS *pParams) { + return resMapTo((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_KernelCcuApi_RsResource.offset), pParams); } static NvU32 __nvoc_thunk_RsResource_kccuapiGetRefCount(struct KernelCcuApi *pResource) { return resGetRefCount((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_KernelCcuApi_RsResource.offset)); } -static NV_STATUS __nvoc_thunk_RmResource_kccuapiCheckMemInterUnmap(struct KernelCcuApi *pRmResource, NvBool bSubdeviceHandleProvided) { - return rmresCheckMemInterUnmap((struct RmResource *)(((unsigned char *)pRmResource) + __nvoc_rtti_KernelCcuApi_RmResource.offset), bSubdeviceHandleProvided); -} - -static NV_STATUS __nvoc_thunk_RsResource_kccuapiMapTo(struct KernelCcuApi *pResource, RS_RES_MAP_TO_PARAMS *pParams) { - return resMapTo((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_KernelCcuApi_RsResource.offset), pParams); +static void __nvoc_thunk_RsResource_kccuapiAddAdditionalDependants(struct RsClient *pClient, struct KernelCcuApi *pResource, RsResourceRef *pReference) { + resAddAdditionalDependants(pClient, (struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_KernelCcuApi_RsResource.offset), pReference); } static NV_STATUS __nvoc_thunk_RmResource_kccuapiControl_Prologue(struct KernelCcuApi *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { @@ -153,26 +137,14 @@ return gpuresGetRegBaseOffsetAndSize((struct GpuResource *)(((unsigned char *)pGpuResource) + __nvoc_rtti_KernelCcuApi_GpuResource.offset), pGpu, pOffset, pSize); } -static NvBool __nvoc_thunk_RsResource_kccuapiCanCopy(struct KernelCcuApi *pResource) { - return resCanCopy((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_KernelCcuApi_RsResource.offset)); -} - static NV_STATUS __nvoc_thunk_GpuResource_kccuapiInternalControlForward(struct KernelCcuApi *pGpuResource, NvU32 command, void *pParams, NvU32 size) { return gpuresInternalControlForward((struct GpuResource *)(((unsigned char *)pGpuResource) + __nvoc_rtti_KernelCcuApi_GpuResource.offset), command, pParams, size); } -static void __nvoc_thunk_RsResource_kccuapiPreDestruct(struct KernelCcuApi *pResource) { - resPreDestruct((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_KernelCcuApi_RsResource.offset)); -} - static NV_STATUS __nvoc_thunk_RsResource_kccuapiUnmapFrom(struct KernelCcuApi *pResource, RS_RES_UNMAP_FROM_PARAMS *pParams) { return resUnmapFrom((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_KernelCcuApi_RsResource.offset), pParams); } -static NV_STATUS __nvoc_thunk_RsResource_kccuapiIsDuplicate(struct KernelCcuApi *pResource, NvHandle hMemory, NvBool *pDuplicate) { - return resIsDuplicate((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_KernelCcuApi_RsResource.offset), hMemory, pDuplicate); -} - static void __nvoc_thunk_RmResource_kccuapiControl_Epilogue(struct KernelCcuApi *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { rmresControl_Epilogue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_KernelCcuApi_RmResource.offset), pCallContext, pParams); } @@ -181,6 +153,42 @@ return resControlLookup((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_KernelCcuApi_RsResource.offset), pParams, ppEntry); } +static NvHandle __nvoc_thunk_GpuResource_kccuapiGetInternalObjectHandle(struct KernelCcuApi *pGpuResource) { + return gpuresGetInternalObjectHandle((struct GpuResource *)(((unsigned char *)pGpuResource) + __nvoc_rtti_KernelCcuApi_GpuResource.offset)); +} + +static NV_STATUS __nvoc_thunk_GpuResource_kccuapiControl(struct KernelCcuApi *pGpuResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return gpuresControl((struct GpuResource *)(((unsigned char *)pGpuResource) + __nvoc_rtti_KernelCcuApi_GpuResource.offset), pCallContext, pParams); +} + +static NV_STATUS __nvoc_thunk_RmResource_kccuapiGetMemInterMapParams(struct KernelCcuApi *pRmResource, RMRES_MEM_INTER_MAP_PARAMS *pParams) { + return rmresGetMemInterMapParams((struct RmResource *)(((unsigned char *)pRmResource) + __nvoc_rtti_KernelCcuApi_RmResource.offset), pParams); +} + +static NV_STATUS __nvoc_thunk_RsResource_kccuapiControlFilter(struct KernelCcuApi *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return resControlFilter((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_KernelCcuApi_RsResource.offset), pCallContext, pParams); +} + +static NV_STATUS __nvoc_thunk_RmResource_kccuapiControlSerialization_Prologue(struct KernelCcuApi *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return rmresControlSerialization_Prologue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_KernelCcuApi_RmResource.offset), pCallContext, pParams); +} + +static NvBool __nvoc_thunk_RsResource_kccuapiCanCopy(struct KernelCcuApi *pResource) { + return resCanCopy((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_KernelCcuApi_RsResource.offset)); +} + +static void __nvoc_thunk_RsResource_kccuapiPreDestruct(struct KernelCcuApi *pResource) { + resPreDestruct((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_KernelCcuApi_RsResource.offset)); +} + +static NV_STATUS __nvoc_thunk_RsResource_kccuapiIsDuplicate(struct KernelCcuApi *pResource, NvHandle hMemory, NvBool *pDuplicate) { + return resIsDuplicate((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_KernelCcuApi_RsResource.offset), hMemory, pDuplicate); +} + +static void __nvoc_thunk_RmResource_kccuapiControlSerialization_Epilogue(struct KernelCcuApi *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + rmresControlSerialization_Epilogue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_KernelCcuApi_RmResource.offset), pCallContext, pParams); +} + static NvBool __nvoc_thunk_RmResource_kccuapiAccessCallback(struct KernelCcuApi *pResource, struct RsClient *pInvokingClient, void *pAllocParams, RsAccessRight accessRight) { return rmresAccessCallback((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_KernelCcuApi_RmResource.offset), pInvokingClient, pAllocParams, accessRight); } @@ -327,40 +335,44 @@ pThis->__kccuapiShareCallback__ = &__nvoc_thunk_GpuResource_kccuapiShareCallback; - pThis->__kccuapiControl__ = &__nvoc_thunk_GpuResource_kccuapiControl; - - pThis->__kccuapiGetMemInterMapParams__ = &__nvoc_thunk_RmResource_kccuapiGetMemInterMapParams; - - pThis->__kccuapiGetInternalObjectHandle__ = &__nvoc_thunk_GpuResource_kccuapiGetInternalObjectHandle; - - pThis->__kccuapiControlFilter__ = &__nvoc_thunk_RsResource_kccuapiControlFilter; + pThis->__kccuapiCheckMemInterUnmap__ = &__nvoc_thunk_RmResource_kccuapiCheckMemInterUnmap; - pThis->__kccuapiAddAdditionalDependants__ = &__nvoc_thunk_RsResource_kccuapiAddAdditionalDependants; + pThis->__kccuapiMapTo__ = &__nvoc_thunk_RsResource_kccuapiMapTo; pThis->__kccuapiGetRefCount__ = &__nvoc_thunk_RsResource_kccuapiGetRefCount; - pThis->__kccuapiCheckMemInterUnmap__ = &__nvoc_thunk_RmResource_kccuapiCheckMemInterUnmap; - - pThis->__kccuapiMapTo__ = &__nvoc_thunk_RsResource_kccuapiMapTo; + pThis->__kccuapiAddAdditionalDependants__ = &__nvoc_thunk_RsResource_kccuapiAddAdditionalDependants; pThis->__kccuapiControl_Prologue__ = &__nvoc_thunk_RmResource_kccuapiControl_Prologue; pThis->__kccuapiGetRegBaseOffsetAndSize__ = &__nvoc_thunk_GpuResource_kccuapiGetRegBaseOffsetAndSize; - pThis->__kccuapiCanCopy__ = &__nvoc_thunk_RsResource_kccuapiCanCopy; - pThis->__kccuapiInternalControlForward__ = &__nvoc_thunk_GpuResource_kccuapiInternalControlForward; - pThis->__kccuapiPreDestruct__ = &__nvoc_thunk_RsResource_kccuapiPreDestruct; - pThis->__kccuapiUnmapFrom__ = &__nvoc_thunk_RsResource_kccuapiUnmapFrom; - pThis->__kccuapiIsDuplicate__ = &__nvoc_thunk_RsResource_kccuapiIsDuplicate; - pThis->__kccuapiControl_Epilogue__ = &__nvoc_thunk_RmResource_kccuapiControl_Epilogue; pThis->__kccuapiControlLookup__ = &__nvoc_thunk_RsResource_kccuapiControlLookup; + pThis->__kccuapiGetInternalObjectHandle__ = &__nvoc_thunk_GpuResource_kccuapiGetInternalObjectHandle; + + pThis->__kccuapiControl__ = &__nvoc_thunk_GpuResource_kccuapiControl; + + pThis->__kccuapiGetMemInterMapParams__ = &__nvoc_thunk_RmResource_kccuapiGetMemInterMapParams; + + pThis->__kccuapiControlFilter__ = &__nvoc_thunk_RsResource_kccuapiControlFilter; + + pThis->__kccuapiControlSerialization_Prologue__ = &__nvoc_thunk_RmResource_kccuapiControlSerialization_Prologue; + + pThis->__kccuapiCanCopy__ = &__nvoc_thunk_RsResource_kccuapiCanCopy; + + pThis->__kccuapiPreDestruct__ = &__nvoc_thunk_RsResource_kccuapiPreDestruct; + + pThis->__kccuapiIsDuplicate__ = &__nvoc_thunk_RsResource_kccuapiIsDuplicate; + + pThis->__kccuapiControlSerialization_Epilogue__ = &__nvoc_thunk_RmResource_kccuapiControlSerialization_Epilogue; + pThis->__kccuapiAccessCallback__ = &__nvoc_thunk_RmResource_kccuapiAccessCallback; } @@ -385,13 +397,16 @@ Object *pParentObj; KernelCcuApi *pThis; - pThis = portMemAllocNonPaged(sizeof(KernelCcuApi)); - if (pThis == NULL) return NV_ERR_NO_MEMORY; + status = __nvoc_handleObjCreateMemAlloc(createFlags, sizeof(KernelCcuApi), (void**)&pThis, (void**)ppThis); + if (status != NV_OK) + return status; portMemSet(pThis, 0, sizeof(KernelCcuApi)); __nvoc_initRtti(staticCast(pThis, Dynamic), &__nvoc_class_def_KernelCcuApi); + pThis->__nvoc_base_GpuResource.__nvoc_base_RmResource.__nvoc_base_RsResource.__nvoc_base_Object.createFlags = createFlags; + if (pParent != NULL && !(createFlags & NVOC_OBJ_CREATE_FLAGS_PARENT_HALSPEC_ONLY)) { pParentObj = dynamicCast(pParent, Object); @@ -407,11 +422,17 @@ if (status != NV_OK) goto __nvoc_objCreate_KernelCcuApi_cleanup; *ppThis = pThis; + return NV_OK; __nvoc_objCreate_KernelCcuApi_cleanup: // do not call destructors here since the constructor already called them - portMemFree(pThis); + if (createFlags & NVOC_OBJ_CREATE_FLAGS_IN_PLACE_CONSTRUCT) + portMemSet(pThis, 0, sizeof(KernelCcuApi)); + else + portMemFree(pThis); + + // coverity[leaked_storage:FALSE] return status; } diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/generated/g_kernel_ccu_api_nvoc.h nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_kernel_ccu_api_nvoc.h --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/generated/g_kernel_ccu_api_nvoc.h 2023-10-25 20:27:05.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_kernel_ccu_api_nvoc.h 2024-03-05 22:18:24.000000000 +0000 @@ -66,23 +66,25 @@ NV_STATUS (*__kccuapiCtrlCmdSetStreamState__)(struct KernelCcuApi *, NV_COUNTER_COLLECTION_UNIT_STREAM_STATE_PARAMS *); NV_STATUS (*__kccuapiCtrlCmdGetStreamState__)(struct KernelCcuApi *, NV_COUNTER_COLLECTION_UNIT_STREAM_STATE_PARAMS *); NvBool (*__kccuapiShareCallback__)(struct KernelCcuApi *, struct RsClient *, struct RsResourceRef *, RS_SHARE_POLICY *); - NV_STATUS (*__kccuapiControl__)(struct KernelCcuApi *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); - NV_STATUS (*__kccuapiGetMemInterMapParams__)(struct KernelCcuApi *, RMRES_MEM_INTER_MAP_PARAMS *); - NvHandle (*__kccuapiGetInternalObjectHandle__)(struct KernelCcuApi *); - NV_STATUS (*__kccuapiControlFilter__)(struct KernelCcuApi *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); - void (*__kccuapiAddAdditionalDependants__)(struct RsClient *, struct KernelCcuApi *, RsResourceRef *); - NvU32 (*__kccuapiGetRefCount__)(struct KernelCcuApi *); NV_STATUS (*__kccuapiCheckMemInterUnmap__)(struct KernelCcuApi *, NvBool); NV_STATUS (*__kccuapiMapTo__)(struct KernelCcuApi *, RS_RES_MAP_TO_PARAMS *); + NvU32 (*__kccuapiGetRefCount__)(struct KernelCcuApi *); + void (*__kccuapiAddAdditionalDependants__)(struct RsClient *, struct KernelCcuApi *, RsResourceRef *); NV_STATUS (*__kccuapiControl_Prologue__)(struct KernelCcuApi *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); NV_STATUS (*__kccuapiGetRegBaseOffsetAndSize__)(struct KernelCcuApi *, struct OBJGPU *, NvU32 *, NvU32 *); - NvBool (*__kccuapiCanCopy__)(struct KernelCcuApi *); NV_STATUS (*__kccuapiInternalControlForward__)(struct KernelCcuApi *, NvU32, void *, NvU32); - void (*__kccuapiPreDestruct__)(struct KernelCcuApi *); NV_STATUS (*__kccuapiUnmapFrom__)(struct KernelCcuApi *, RS_RES_UNMAP_FROM_PARAMS *); - NV_STATUS (*__kccuapiIsDuplicate__)(struct KernelCcuApi *, NvHandle, NvBool *); void (*__kccuapiControl_Epilogue__)(struct KernelCcuApi *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); NV_STATUS (*__kccuapiControlLookup__)(struct KernelCcuApi *, struct RS_RES_CONTROL_PARAMS_INTERNAL *, const struct NVOC_EXPORTED_METHOD_DEF **); + NvHandle (*__kccuapiGetInternalObjectHandle__)(struct KernelCcuApi *); + NV_STATUS (*__kccuapiControl__)(struct KernelCcuApi *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); + NV_STATUS (*__kccuapiGetMemInterMapParams__)(struct KernelCcuApi *, RMRES_MEM_INTER_MAP_PARAMS *); + NV_STATUS (*__kccuapiControlFilter__)(struct KernelCcuApi *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); + NV_STATUS (*__kccuapiControlSerialization_Prologue__)(struct KernelCcuApi *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); + NvBool (*__kccuapiCanCopy__)(struct KernelCcuApi *); + void (*__kccuapiPreDestruct__)(struct KernelCcuApi *); + NV_STATUS (*__kccuapiIsDuplicate__)(struct KernelCcuApi *, NvHandle, NvBool *); + void (*__kccuapiControlSerialization_Epilogue__)(struct KernelCcuApi *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); NvBool (*__kccuapiAccessCallback__)(struct KernelCcuApi *, struct RsClient *, void *, RsAccessRight); }; @@ -123,23 +125,25 @@ #define kccuapiCtrlCmdSetStreamState(pKernelCcuApi, pParams) kccuapiCtrlCmdSetStreamState_DISPATCH(pKernelCcuApi, pParams) #define kccuapiCtrlCmdGetStreamState(pKernelCcuApi, pParams) kccuapiCtrlCmdGetStreamState_DISPATCH(pKernelCcuApi, pParams) #define kccuapiShareCallback(pGpuResource, pInvokingClient, pParentRef, pSharePolicy) kccuapiShareCallback_DISPATCH(pGpuResource, pInvokingClient, pParentRef, pSharePolicy) -#define kccuapiControl(pGpuResource, pCallContext, pParams) kccuapiControl_DISPATCH(pGpuResource, pCallContext, pParams) -#define kccuapiGetMemInterMapParams(pRmResource, pParams) kccuapiGetMemInterMapParams_DISPATCH(pRmResource, pParams) -#define kccuapiGetInternalObjectHandle(pGpuResource) kccuapiGetInternalObjectHandle_DISPATCH(pGpuResource) -#define kccuapiControlFilter(pResource, pCallContext, pParams) kccuapiControlFilter_DISPATCH(pResource, pCallContext, pParams) -#define kccuapiAddAdditionalDependants(pClient, pResource, pReference) kccuapiAddAdditionalDependants_DISPATCH(pClient, pResource, pReference) -#define kccuapiGetRefCount(pResource) kccuapiGetRefCount_DISPATCH(pResource) #define kccuapiCheckMemInterUnmap(pRmResource, bSubdeviceHandleProvided) kccuapiCheckMemInterUnmap_DISPATCH(pRmResource, bSubdeviceHandleProvided) #define kccuapiMapTo(pResource, pParams) kccuapiMapTo_DISPATCH(pResource, pParams) +#define kccuapiGetRefCount(pResource) kccuapiGetRefCount_DISPATCH(pResource) +#define kccuapiAddAdditionalDependants(pClient, pResource, pReference) kccuapiAddAdditionalDependants_DISPATCH(pClient, pResource, pReference) #define kccuapiControl_Prologue(pResource, pCallContext, pParams) kccuapiControl_Prologue_DISPATCH(pResource, pCallContext, pParams) #define kccuapiGetRegBaseOffsetAndSize(pGpuResource, pGpu, pOffset, pSize) kccuapiGetRegBaseOffsetAndSize_DISPATCH(pGpuResource, pGpu, pOffset, pSize) -#define kccuapiCanCopy(pResource) kccuapiCanCopy_DISPATCH(pResource) #define kccuapiInternalControlForward(pGpuResource, command, pParams, size) kccuapiInternalControlForward_DISPATCH(pGpuResource, command, pParams, size) -#define kccuapiPreDestruct(pResource) kccuapiPreDestruct_DISPATCH(pResource) #define kccuapiUnmapFrom(pResource, pParams) kccuapiUnmapFrom_DISPATCH(pResource, pParams) -#define kccuapiIsDuplicate(pResource, hMemory, pDuplicate) kccuapiIsDuplicate_DISPATCH(pResource, hMemory, pDuplicate) #define kccuapiControl_Epilogue(pResource, pCallContext, pParams) kccuapiControl_Epilogue_DISPATCH(pResource, pCallContext, pParams) #define kccuapiControlLookup(pResource, pParams, ppEntry) kccuapiControlLookup_DISPATCH(pResource, pParams, ppEntry) +#define kccuapiGetInternalObjectHandle(pGpuResource) kccuapiGetInternalObjectHandle_DISPATCH(pGpuResource) +#define kccuapiControl(pGpuResource, pCallContext, pParams) kccuapiControl_DISPATCH(pGpuResource, pCallContext, pParams) +#define kccuapiGetMemInterMapParams(pRmResource, pParams) kccuapiGetMemInterMapParams_DISPATCH(pRmResource, pParams) +#define kccuapiControlFilter(pResource, pCallContext, pParams) kccuapiControlFilter_DISPATCH(pResource, pCallContext, pParams) +#define kccuapiControlSerialization_Prologue(pResource, pCallContext, pParams) kccuapiControlSerialization_Prologue_DISPATCH(pResource, pCallContext, pParams) +#define kccuapiCanCopy(pResource) kccuapiCanCopy_DISPATCH(pResource) +#define kccuapiPreDestruct(pResource) kccuapiPreDestruct_DISPATCH(pResource) +#define kccuapiIsDuplicate(pResource, hMemory, pDuplicate) kccuapiIsDuplicate_DISPATCH(pResource, hMemory, pDuplicate) +#define kccuapiControlSerialization_Epilogue(pResource, pCallContext, pParams) kccuapiControlSerialization_Epilogue_DISPATCH(pResource, pCallContext, pParams) #define kccuapiAccessCallback(pResource, pInvokingClient, pAllocParams, accessRight) kccuapiAccessCallback_DISPATCH(pResource, pInvokingClient, pAllocParams, accessRight) NV_STATUS kccuapiMap_IMPL(struct KernelCcuApi *pKernelCcuApi, struct CALL_CONTEXT *pCallContext, struct RS_CPU_MAP_PARAMS *pParams, struct RsCpuMapping *pCpuMapping); @@ -193,36 +197,20 @@ return pGpuResource->__kccuapiShareCallback__(pGpuResource, pInvokingClient, pParentRef, pSharePolicy); } -static inline NV_STATUS kccuapiControl_DISPATCH(struct KernelCcuApi *pGpuResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { - return pGpuResource->__kccuapiControl__(pGpuResource, pCallContext, pParams); -} - -static inline NV_STATUS kccuapiGetMemInterMapParams_DISPATCH(struct KernelCcuApi *pRmResource, RMRES_MEM_INTER_MAP_PARAMS *pParams) { - return pRmResource->__kccuapiGetMemInterMapParams__(pRmResource, pParams); -} - -static inline NvHandle kccuapiGetInternalObjectHandle_DISPATCH(struct KernelCcuApi *pGpuResource) { - return pGpuResource->__kccuapiGetInternalObjectHandle__(pGpuResource); -} - -static inline NV_STATUS kccuapiControlFilter_DISPATCH(struct KernelCcuApi *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { - return pResource->__kccuapiControlFilter__(pResource, pCallContext, pParams); +static inline NV_STATUS kccuapiCheckMemInterUnmap_DISPATCH(struct KernelCcuApi *pRmResource, NvBool bSubdeviceHandleProvided) { + return pRmResource->__kccuapiCheckMemInterUnmap__(pRmResource, bSubdeviceHandleProvided); } -static inline void kccuapiAddAdditionalDependants_DISPATCH(struct RsClient *pClient, struct KernelCcuApi *pResource, RsResourceRef *pReference) { - pResource->__kccuapiAddAdditionalDependants__(pClient, pResource, pReference); +static inline NV_STATUS kccuapiMapTo_DISPATCH(struct KernelCcuApi *pResource, RS_RES_MAP_TO_PARAMS *pParams) { + return pResource->__kccuapiMapTo__(pResource, pParams); } static inline NvU32 kccuapiGetRefCount_DISPATCH(struct KernelCcuApi *pResource) { return pResource->__kccuapiGetRefCount__(pResource); } -static inline NV_STATUS kccuapiCheckMemInterUnmap_DISPATCH(struct KernelCcuApi *pRmResource, NvBool bSubdeviceHandleProvided) { - return pRmResource->__kccuapiCheckMemInterUnmap__(pRmResource, bSubdeviceHandleProvided); -} - -static inline NV_STATUS kccuapiMapTo_DISPATCH(struct KernelCcuApi *pResource, RS_RES_MAP_TO_PARAMS *pParams) { - return pResource->__kccuapiMapTo__(pResource, pParams); +static inline void kccuapiAddAdditionalDependants_DISPATCH(struct RsClient *pClient, struct KernelCcuApi *pResource, RsResourceRef *pReference) { + pResource->__kccuapiAddAdditionalDependants__(pClient, pResource, pReference); } static inline NV_STATUS kccuapiControl_Prologue_DISPATCH(struct KernelCcuApi *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { @@ -233,26 +221,14 @@ return pGpuResource->__kccuapiGetRegBaseOffsetAndSize__(pGpuResource, pGpu, pOffset, pSize); } -static inline NvBool kccuapiCanCopy_DISPATCH(struct KernelCcuApi *pResource) { - return pResource->__kccuapiCanCopy__(pResource); -} - static inline NV_STATUS kccuapiInternalControlForward_DISPATCH(struct KernelCcuApi *pGpuResource, NvU32 command, void *pParams, NvU32 size) { return pGpuResource->__kccuapiInternalControlForward__(pGpuResource, command, pParams, size); } -static inline void kccuapiPreDestruct_DISPATCH(struct KernelCcuApi *pResource) { - pResource->__kccuapiPreDestruct__(pResource); -} - static inline NV_STATUS kccuapiUnmapFrom_DISPATCH(struct KernelCcuApi *pResource, RS_RES_UNMAP_FROM_PARAMS *pParams) { return pResource->__kccuapiUnmapFrom__(pResource, pParams); } -static inline NV_STATUS kccuapiIsDuplicate_DISPATCH(struct KernelCcuApi *pResource, NvHandle hMemory, NvBool *pDuplicate) { - return pResource->__kccuapiIsDuplicate__(pResource, hMemory, pDuplicate); -} - static inline void kccuapiControl_Epilogue_DISPATCH(struct KernelCcuApi *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { pResource->__kccuapiControl_Epilogue__(pResource, pCallContext, pParams); } @@ -261,6 +237,42 @@ return pResource->__kccuapiControlLookup__(pResource, pParams, ppEntry); } +static inline NvHandle kccuapiGetInternalObjectHandle_DISPATCH(struct KernelCcuApi *pGpuResource) { + return pGpuResource->__kccuapiGetInternalObjectHandle__(pGpuResource); +} + +static inline NV_STATUS kccuapiControl_DISPATCH(struct KernelCcuApi *pGpuResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return pGpuResource->__kccuapiControl__(pGpuResource, pCallContext, pParams); +} + +static inline NV_STATUS kccuapiGetMemInterMapParams_DISPATCH(struct KernelCcuApi *pRmResource, RMRES_MEM_INTER_MAP_PARAMS *pParams) { + return pRmResource->__kccuapiGetMemInterMapParams__(pRmResource, pParams); +} + +static inline NV_STATUS kccuapiControlFilter_DISPATCH(struct KernelCcuApi *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return pResource->__kccuapiControlFilter__(pResource, pCallContext, pParams); +} + +static inline NV_STATUS kccuapiControlSerialization_Prologue_DISPATCH(struct KernelCcuApi *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return pResource->__kccuapiControlSerialization_Prologue__(pResource, pCallContext, pParams); +} + +static inline NvBool kccuapiCanCopy_DISPATCH(struct KernelCcuApi *pResource) { + return pResource->__kccuapiCanCopy__(pResource); +} + +static inline void kccuapiPreDestruct_DISPATCH(struct KernelCcuApi *pResource) { + pResource->__kccuapiPreDestruct__(pResource); +} + +static inline NV_STATUS kccuapiIsDuplicate_DISPATCH(struct KernelCcuApi *pResource, NvHandle hMemory, NvBool *pDuplicate) { + return pResource->__kccuapiIsDuplicate__(pResource, hMemory, pDuplicate); +} + +static inline void kccuapiControlSerialization_Epilogue_DISPATCH(struct KernelCcuApi *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + pResource->__kccuapiControlSerialization_Epilogue__(pResource, pCallContext, pParams); +} + static inline NvBool kccuapiAccessCallback_DISPATCH(struct KernelCcuApi *pResource, struct RsClient *pInvokingClient, void *pAllocParams, RsAccessRight accessRight) { return pResource->__kccuapiAccessCallback__(pResource, pInvokingClient, pAllocParams, accessRight); } diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/generated/g_kernel_ccu_nvoc.c nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_kernel_ccu_nvoc.c --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/generated/g_kernel_ccu_nvoc.c 2023-10-25 20:27:05.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_kernel_ccu_nvoc.c 2024-03-05 22:18:24.000000000 +0000 @@ -78,10 +78,6 @@ return kccuStateUnload(arg0, (struct KernelCcu *)(((unsigned char *)arg1) - __nvoc_rtti_KernelCcu_OBJENGSTATE.offset), flags); } -static NV_STATUS __nvoc_thunk_OBJENGSTATE_kccuReconcileTunableState(POBJGPU pGpu, struct KernelCcu *pEngstate, void *pTunableState) { - return engstateReconcileTunableState(pGpu, (struct OBJENGSTATE *)(((unsigned char *)pEngstate) + __nvoc_rtti_KernelCcu_OBJENGSTATE.offset), pTunableState); -} - static NV_STATUS __nvoc_thunk_OBJENGSTATE_kccuStateInitLocked(POBJGPU pGpu, struct KernelCcu *pEngstate) { return engstateStateInitLocked(pGpu, (struct OBJENGSTATE *)(((unsigned char *)pEngstate) + __nvoc_rtti_KernelCcu_OBJENGSTATE.offset)); } @@ -118,30 +114,10 @@ return engstateStatePreInitUnlocked(pGpu, (struct OBJENGSTATE *)(((unsigned char *)pEngstate) + __nvoc_rtti_KernelCcu_OBJENGSTATE.offset)); } -static NV_STATUS __nvoc_thunk_OBJENGSTATE_kccuGetTunableState(POBJGPU pGpu, struct KernelCcu *pEngstate, void *pTunableState) { - return engstateGetTunableState(pGpu, (struct OBJENGSTATE *)(((unsigned char *)pEngstate) + __nvoc_rtti_KernelCcu_OBJENGSTATE.offset), pTunableState); -} - -static NV_STATUS __nvoc_thunk_OBJENGSTATE_kccuCompareTunableState(POBJGPU pGpu, struct KernelCcu *pEngstate, void *pTunables1, void *pTunables2) { - return engstateCompareTunableState(pGpu, (struct OBJENGSTATE *)(((unsigned char *)pEngstate) + __nvoc_rtti_KernelCcu_OBJENGSTATE.offset), pTunables1, pTunables2); -} - -static void __nvoc_thunk_OBJENGSTATE_kccuFreeTunableState(POBJGPU pGpu, struct KernelCcu *pEngstate, void *pTunableState) { - engstateFreeTunableState(pGpu, (struct OBJENGSTATE *)(((unsigned char *)pEngstate) + __nvoc_rtti_KernelCcu_OBJENGSTATE.offset), pTunableState); -} - static NV_STATUS __nvoc_thunk_OBJENGSTATE_kccuStatePostLoad(POBJGPU pGpu, struct KernelCcu *pEngstate, NvU32 arg0) { return engstateStatePostLoad(pGpu, (struct OBJENGSTATE *)(((unsigned char *)pEngstate) + __nvoc_rtti_KernelCcu_OBJENGSTATE.offset), arg0); } -static NV_STATUS __nvoc_thunk_OBJENGSTATE_kccuAllocTunableState(POBJGPU pGpu, struct KernelCcu *pEngstate, void **ppTunableState) { - return engstateAllocTunableState(pGpu, (struct OBJENGSTATE *)(((unsigned char *)pEngstate) + __nvoc_rtti_KernelCcu_OBJENGSTATE.offset), ppTunableState); -} - -static NV_STATUS __nvoc_thunk_OBJENGSTATE_kccuSetTunableState(POBJGPU pGpu, struct KernelCcu *pEngstate, void *pTunableState) { - return engstateSetTunableState(pGpu, (struct OBJENGSTATE *)(((unsigned char *)pEngstate) + __nvoc_rtti_KernelCcu_OBJENGSTATE.offset), pTunableState); -} - static NvBool __nvoc_thunk_OBJENGSTATE_kccuIsPresent(POBJGPU pGpu, struct KernelCcu *pEngstate) { return engstateIsPresent(pGpu, (struct OBJENGSTATE *)(((unsigned char *)pEngstate) + __nvoc_rtti_KernelCcu_OBJENGSTATE.offset)); } @@ -199,10 +175,7 @@ PORT_UNREFERENCED_VARIABLE(chipHal_HalVarIdx); // Hal function -- kccuConstructEngine - if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000002UL) )) /* RmVariantHal: PF_KERNEL_ONLY */ - { - pThis->__kccuConstructEngine__ = &kccuConstructEngine_IMPL; - } + pThis->__kccuConstructEngine__ = &kccuConstructEngine_IMPL; pThis->__kccuStateLoad__ = &kccuStateLoad_IMPL; @@ -225,8 +198,6 @@ pThis->__nvoc_base_OBJENGSTATE.__engstateStateUnload__ = &__nvoc_thunk_KernelCcu_engstateStateUnload; - pThis->__kccuReconcileTunableState__ = &__nvoc_thunk_OBJENGSTATE_kccuReconcileTunableState; - pThis->__kccuStateInitLocked__ = &__nvoc_thunk_OBJENGSTATE_kccuStateInitLocked; pThis->__kccuStatePreLoad__ = &__nvoc_thunk_OBJENGSTATE_kccuStatePreLoad; @@ -245,18 +216,8 @@ pThis->__kccuStatePreInitUnlocked__ = &__nvoc_thunk_OBJENGSTATE_kccuStatePreInitUnlocked; - pThis->__kccuGetTunableState__ = &__nvoc_thunk_OBJENGSTATE_kccuGetTunableState; - - pThis->__kccuCompareTunableState__ = &__nvoc_thunk_OBJENGSTATE_kccuCompareTunableState; - - pThis->__kccuFreeTunableState__ = &__nvoc_thunk_OBJENGSTATE_kccuFreeTunableState; - pThis->__kccuStatePostLoad__ = &__nvoc_thunk_OBJENGSTATE_kccuStatePostLoad; - pThis->__kccuAllocTunableState__ = &__nvoc_thunk_OBJENGSTATE_kccuAllocTunableState; - - pThis->__kccuSetTunableState__ = &__nvoc_thunk_OBJENGSTATE_kccuSetTunableState; - pThis->__kccuIsPresent__ = &__nvoc_thunk_OBJENGSTATE_kccuIsPresent; } @@ -279,13 +240,16 @@ KernelCcu *pThis; RmHalspecOwner *pRmhalspecowner; - pThis = portMemAllocNonPaged(sizeof(KernelCcu)); - if (pThis == NULL) return NV_ERR_NO_MEMORY; + status = __nvoc_handleObjCreateMemAlloc(createFlags, sizeof(KernelCcu), (void**)&pThis, (void**)ppThis); + if (status != NV_OK) + return status; portMemSet(pThis, 0, sizeof(KernelCcu)); __nvoc_initRtti(staticCast(pThis, Dynamic), &__nvoc_class_def_KernelCcu); + pThis->__nvoc_base_OBJENGSTATE.__nvoc_base_Object.createFlags = createFlags; + if (pParent != NULL && !(createFlags & NVOC_OBJ_CREATE_FLAGS_PARENT_HALSPEC_ONLY)) { pParentObj = dynamicCast(pParent, Object); @@ -305,11 +269,17 @@ if (status != NV_OK) goto __nvoc_objCreate_KernelCcu_cleanup; *ppThis = pThis; + return NV_OK; __nvoc_objCreate_KernelCcu_cleanup: // do not call destructors here since the constructor already called them - portMemFree(pThis); + if (createFlags & NVOC_OBJ_CREATE_FLAGS_IN_PLACE_CONSTRUCT) + portMemSet(pThis, 0, sizeof(KernelCcu)); + else + portMemFree(pThis); + + // coverity[leaked_storage:FALSE] return status; } diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/generated/g_kernel_ccu_nvoc.h nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_kernel_ccu_nvoc.h --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/generated/g_kernel_ccu_nvoc.h 2023-10-25 20:27:06.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_kernel_ccu_nvoc.h 2024-03-05 22:18:24.000000000 +0000 @@ -117,7 +117,6 @@ NV_STATUS (*__kccuStateLoad__)(OBJGPU *, struct KernelCcu *, NvU32); NV_STATUS (*__kccuStateUnload__)(OBJGPU *, struct KernelCcu *, NvU32); NV_STATUS (*__kccuMigShrBufHandler__)(OBJGPU *, struct KernelCcu *, NvBool); - NV_STATUS (*__kccuReconcileTunableState__)(POBJGPU, struct KernelCcu *, void *); NV_STATUS (*__kccuStateInitLocked__)(POBJGPU, struct KernelCcu *); NV_STATUS (*__kccuStatePreLoad__)(POBJGPU, struct KernelCcu *, NvU32); NV_STATUS (*__kccuStatePostUnload__)(POBJGPU, struct KernelCcu *, NvU32); @@ -127,12 +126,7 @@ void (*__kccuInitMissing__)(POBJGPU, struct KernelCcu *); NV_STATUS (*__kccuStatePreInitLocked__)(POBJGPU, struct KernelCcu *); NV_STATUS (*__kccuStatePreInitUnlocked__)(POBJGPU, struct KernelCcu *); - NV_STATUS (*__kccuGetTunableState__)(POBJGPU, struct KernelCcu *, void *); - NV_STATUS (*__kccuCompareTunableState__)(POBJGPU, struct KernelCcu *, void *, void *); - void (*__kccuFreeTunableState__)(POBJGPU, struct KernelCcu *, void *); NV_STATUS (*__kccuStatePostLoad__)(POBJGPU, struct KernelCcu *, NvU32); - NV_STATUS (*__kccuAllocTunableState__)(POBJGPU, struct KernelCcu *, void **); - NV_STATUS (*__kccuSetTunableState__)(POBJGPU, struct KernelCcu *, void *); NvBool (*__kccuIsPresent__)(POBJGPU, struct KernelCcu *); MEMORY_DESCRIPTOR *pMemDesc[9]; NvBool bStreamState; @@ -176,7 +170,6 @@ #define kccuStateUnload(arg0, arg1, flags) kccuStateUnload_DISPATCH(arg0, arg1, flags) #define kccuMigShrBufHandler(arg0, arg1, bMigEnabled) kccuMigShrBufHandler_DISPATCH(arg0, arg1, bMigEnabled) #define kccuMigShrBufHandler_HAL(arg0, arg1, bMigEnabled) kccuMigShrBufHandler_DISPATCH(arg0, arg1, bMigEnabled) -#define kccuReconcileTunableState(pGpu, pEngstate, pTunableState) kccuReconcileTunableState_DISPATCH(pGpu, pEngstate, pTunableState) #define kccuStateInitLocked(pGpu, pEngstate) kccuStateInitLocked_DISPATCH(pGpu, pEngstate) #define kccuStatePreLoad(pGpu, pEngstate, arg0) kccuStatePreLoad_DISPATCH(pGpu, pEngstate, arg0) #define kccuStatePostUnload(pGpu, pEngstate, arg0) kccuStatePostUnload_DISPATCH(pGpu, pEngstate, arg0) @@ -186,12 +179,7 @@ #define kccuInitMissing(pGpu, pEngstate) kccuInitMissing_DISPATCH(pGpu, pEngstate) #define kccuStatePreInitLocked(pGpu, pEngstate) kccuStatePreInitLocked_DISPATCH(pGpu, pEngstate) #define kccuStatePreInitUnlocked(pGpu, pEngstate) kccuStatePreInitUnlocked_DISPATCH(pGpu, pEngstate) -#define kccuGetTunableState(pGpu, pEngstate, pTunableState) kccuGetTunableState_DISPATCH(pGpu, pEngstate, pTunableState) -#define kccuCompareTunableState(pGpu, pEngstate, pTunables1, pTunables2) kccuCompareTunableState_DISPATCH(pGpu, pEngstate, pTunables1, pTunables2) -#define kccuFreeTunableState(pGpu, pEngstate, pTunableState) kccuFreeTunableState_DISPATCH(pGpu, pEngstate, pTunableState) #define kccuStatePostLoad(pGpu, pEngstate, arg0) kccuStatePostLoad_DISPATCH(pGpu, pEngstate, arg0) -#define kccuAllocTunableState(pGpu, pEngstate, ppTunableState) kccuAllocTunableState_DISPATCH(pGpu, pEngstate, ppTunableState) -#define kccuSetTunableState(pGpu, pEngstate, pTunableState) kccuSetTunableState_DISPATCH(pGpu, pEngstate, pTunableState) #define kccuIsPresent(pGpu, pEngstate) kccuIsPresent_DISPATCH(pGpu, pEngstate) void kccuDestruct_IMPL(struct KernelCcu *arg0); @@ -225,10 +213,6 @@ return arg1->__kccuMigShrBufHandler__(arg0, arg1, bMigEnabled); } -static inline NV_STATUS kccuReconcileTunableState_DISPATCH(POBJGPU pGpu, struct KernelCcu *pEngstate, void *pTunableState) { - return pEngstate->__kccuReconcileTunableState__(pGpu, pEngstate, pTunableState); -} - static inline NV_STATUS kccuStateInitLocked_DISPATCH(POBJGPU pGpu, struct KernelCcu *pEngstate) { return pEngstate->__kccuStateInitLocked__(pGpu, pEngstate); } @@ -265,30 +249,10 @@ return pEngstate->__kccuStatePreInitUnlocked__(pGpu, pEngstate); } -static inline NV_STATUS kccuGetTunableState_DISPATCH(POBJGPU pGpu, struct KernelCcu *pEngstate, void *pTunableState) { - return pEngstate->__kccuGetTunableState__(pGpu, pEngstate, pTunableState); -} - -static inline NV_STATUS kccuCompareTunableState_DISPATCH(POBJGPU pGpu, struct KernelCcu *pEngstate, void *pTunables1, void *pTunables2) { - return pEngstate->__kccuCompareTunableState__(pGpu, pEngstate, pTunables1, pTunables2); -} - -static inline void kccuFreeTunableState_DISPATCH(POBJGPU pGpu, struct KernelCcu *pEngstate, void *pTunableState) { - pEngstate->__kccuFreeTunableState__(pGpu, pEngstate, pTunableState); -} - static inline NV_STATUS kccuStatePostLoad_DISPATCH(POBJGPU pGpu, struct KernelCcu *pEngstate, NvU32 arg0) { return pEngstate->__kccuStatePostLoad__(pGpu, pEngstate, arg0); } -static inline NV_STATUS kccuAllocTunableState_DISPATCH(POBJGPU pGpu, struct KernelCcu *pEngstate, void **ppTunableState) { - return pEngstate->__kccuAllocTunableState__(pGpu, pEngstate, ppTunableState); -} - -static inline NV_STATUS kccuSetTunableState_DISPATCH(POBJGPU pGpu, struct KernelCcu *pEngstate, void *pTunableState) { - return pEngstate->__kccuSetTunableState__(pGpu, pEngstate, pTunableState); -} - static inline NvBool kccuIsPresent_DISPATCH(POBJGPU pGpu, struct KernelCcu *pEngstate) { return pEngstate->__kccuIsPresent__(pGpu, pEngstate); } diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/generated/g_kernel_ce_context_nvoc.c nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_kernel_ce_context_nvoc.c --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/generated/g_kernel_ce_context_nvoc.c 2023-10-25 20:27:06.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_kernel_ce_context_nvoc.c 2024-03-05 22:18:24.000000000 +0000 @@ -176,7 +176,7 @@ return resControlLookup((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_KernelCeContext_RsResource.offset), pParams, ppEntry); } -static NV_STATUS __nvoc_thunk_ChannelDescendant_kcectxGetSwMethods(struct KernelCeContext *pChannelDescendant, METHOD **ppMethods, NvU32 *pNumMethods) { +static NV_STATUS __nvoc_thunk_ChannelDescendant_kcectxGetSwMethods(struct KernelCeContext *pChannelDescendant, const METHOD **ppMethods, NvU32 *pNumMethods) { return chandesGetSwMethods((struct ChannelDescendant *)(((unsigned char *)pChannelDescendant) + __nvoc_rtti_KernelCeContext_ChannelDescendant.offset), ppMethods, pNumMethods); } @@ -212,6 +212,10 @@ return notifyUnregisterEvent((struct Notifier *)(((unsigned char *)pNotifier) + __nvoc_rtti_KernelCeContext_Notifier.offset), hNotifierClient, hNotifierResource, hEventClient, hEvent); } +static NV_STATUS __nvoc_thunk_RmResource_kcectxControlSerialization_Prologue(struct KernelCeContext *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return rmresControlSerialization_Prologue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_KernelCeContext_RmResource.offset), pCallContext, pParams); +} + static NvBool __nvoc_thunk_RsResource_kcectxCanCopy(struct KernelCeContext *pResource) { return resCanCopy((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_KernelCeContext_RsResource.offset)); } @@ -224,6 +228,10 @@ return resIsDuplicate((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_KernelCeContext_RsResource.offset), hMemory, pDuplicate); } +static void __nvoc_thunk_RmResource_kcectxControlSerialization_Epilogue(struct KernelCeContext *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + rmresControlSerialization_Epilogue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_KernelCeContext_RmResource.offset), pCallContext, pParams); +} + static PEVENTNOTIFICATION *__nvoc_thunk_Notifier_kcectxGetNotificationListPtr(struct KernelCeContext *pNotifier) { return notifyGetNotificationListPtr((struct Notifier *)(((unsigned char *)pNotifier) + __nvoc_rtti_KernelCeContext_Notifier.offset)); } @@ -325,12 +333,16 @@ pThis->__kcectxUnregisterEvent__ = &__nvoc_thunk_Notifier_kcectxUnregisterEvent; + pThis->__kcectxControlSerialization_Prologue__ = &__nvoc_thunk_RmResource_kcectxControlSerialization_Prologue; + pThis->__kcectxCanCopy__ = &__nvoc_thunk_RsResource_kcectxCanCopy; pThis->__kcectxPreDestruct__ = &__nvoc_thunk_RsResource_kcectxPreDestruct; pThis->__kcectxIsDuplicate__ = &__nvoc_thunk_RsResource_kcectxIsDuplicate; + pThis->__kcectxControlSerialization_Epilogue__ = &__nvoc_thunk_RmResource_kcectxControlSerialization_Epilogue; + pThis->__kcectxGetNotificationListPtr__ = &__nvoc_thunk_Notifier_kcectxGetNotificationListPtr; pThis->__kcectxGetNotificationShare__ = &__nvoc_thunk_Notifier_kcectxGetNotificationShare; @@ -365,13 +377,16 @@ KernelCeContext *pThis; RmHalspecOwner *pRmhalspecowner; - pThis = portMemAllocNonPaged(sizeof(KernelCeContext)); - if (pThis == NULL) return NV_ERR_NO_MEMORY; + status = __nvoc_handleObjCreateMemAlloc(createFlags, sizeof(KernelCeContext), (void**)&pThis, (void**)ppThis); + if (status != NV_OK) + return status; portMemSet(pThis, 0, sizeof(KernelCeContext)); __nvoc_initRtti(staticCast(pThis, Dynamic), &__nvoc_class_def_KernelCeContext); + pThis->__nvoc_base_ChannelDescendant.__nvoc_base_GpuResource.__nvoc_base_RmResource.__nvoc_base_RsResource.__nvoc_base_Object.createFlags = createFlags; + if (pParent != NULL && !(createFlags & NVOC_OBJ_CREATE_FLAGS_PARENT_HALSPEC_ONLY)) { pParentObj = dynamicCast(pParent, Object); @@ -391,11 +406,17 @@ if (status != NV_OK) goto __nvoc_objCreate_KernelCeContext_cleanup; *ppThis = pThis; + return NV_OK; __nvoc_objCreate_KernelCeContext_cleanup: // do not call destructors here since the constructor already called them - portMemFree(pThis); + if (createFlags & NVOC_OBJ_CREATE_FLAGS_IN_PLACE_CONSTRUCT) + portMemSet(pThis, 0, sizeof(KernelCeContext)); + else + portMemFree(pThis); + + // coverity[leaked_storage:FALSE] return status; } diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/generated/g_kernel_ce_context_nvoc.h nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_kernel_ce_context_nvoc.h --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/generated/g_kernel_ce_context_nvoc.h 2023-10-25 20:27:06.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_kernel_ce_context_nvoc.h 2024-03-05 22:18:24.000000000 +0000 @@ -76,7 +76,7 @@ NV_STATUS (*__kcectxUnmapFrom__)(struct KernelCeContext *, RS_RES_UNMAP_FROM_PARAMS *); void (*__kcectxControl_Epilogue__)(struct KernelCeContext *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); NV_STATUS (*__kcectxControlLookup__)(struct KernelCeContext *, struct RS_RES_CONTROL_PARAMS_INTERNAL *, const struct NVOC_EXPORTED_METHOD_DEF **); - NV_STATUS (*__kcectxGetSwMethods__)(struct KernelCeContext *, METHOD **, NvU32 *); + NV_STATUS (*__kcectxGetSwMethods__)(struct KernelCeContext *, const METHOD **, NvU32 *); NvHandle (*__kcectxGetInternalObjectHandle__)(struct KernelCeContext *); NV_STATUS (*__kcectxControl__)(struct KernelCeContext *, CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); NV_STATUS (*__kcectxUnmap__)(struct KernelCeContext *, CALL_CONTEXT *, RsCpuMapping *); @@ -85,9 +85,11 @@ NvBool (*__kcectxIsSwMethodStalling__)(struct KernelCeContext *, NvU32); NV_STATUS (*__kcectxControlFilter__)(struct KernelCeContext *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); NV_STATUS (*__kcectxUnregisterEvent__)(struct KernelCeContext *, NvHandle, NvHandle, NvHandle, NvHandle); + NV_STATUS (*__kcectxControlSerialization_Prologue__)(struct KernelCeContext *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); NvBool (*__kcectxCanCopy__)(struct KernelCeContext *); void (*__kcectxPreDestruct__)(struct KernelCeContext *); NV_STATUS (*__kcectxIsDuplicate__)(struct KernelCeContext *, NvHandle, NvBool *); + void (*__kcectxControlSerialization_Epilogue__)(struct KernelCeContext *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); PEVENTNOTIFICATION *(*__kcectxGetNotificationListPtr__)(struct KernelCeContext *); struct NotifShare *(*__kcectxGetNotificationShare__)(struct KernelCeContext *); NV_STATUS (*__kcectxMap__)(struct KernelCeContext *, CALL_CONTEXT *, struct RS_CPU_MAP_PARAMS *, RsCpuMapping *); @@ -145,9 +147,11 @@ #define kcectxIsSwMethodStalling(pChannelDescendant, hHandle) kcectxIsSwMethodStalling_DISPATCH(pChannelDescendant, hHandle) #define kcectxControlFilter(pResource, pCallContext, pParams) kcectxControlFilter_DISPATCH(pResource, pCallContext, pParams) #define kcectxUnregisterEvent(pNotifier, hNotifierClient, hNotifierResource, hEventClient, hEvent) kcectxUnregisterEvent_DISPATCH(pNotifier, hNotifierClient, hNotifierResource, hEventClient, hEvent) +#define kcectxControlSerialization_Prologue(pResource, pCallContext, pParams) kcectxControlSerialization_Prologue_DISPATCH(pResource, pCallContext, pParams) #define kcectxCanCopy(pResource) kcectxCanCopy_DISPATCH(pResource) #define kcectxPreDestruct(pResource) kcectxPreDestruct_DISPATCH(pResource) #define kcectxIsDuplicate(pResource, hMemory, pDuplicate) kcectxIsDuplicate_DISPATCH(pResource, hMemory, pDuplicate) +#define kcectxControlSerialization_Epilogue(pResource, pCallContext, pParams) kcectxControlSerialization_Epilogue_DISPATCH(pResource, pCallContext, pParams) #define kcectxGetNotificationListPtr(pNotifier) kcectxGetNotificationListPtr_DISPATCH(pNotifier) #define kcectxGetNotificationShare(pNotifier) kcectxGetNotificationShare_DISPATCH(pNotifier) #define kcectxMap(pGpuResource, pCallContext, pParams, pCpuMapping) kcectxMap_DISPATCH(pGpuResource, pCallContext, pParams, pCpuMapping) @@ -208,7 +212,7 @@ return pResource->__kcectxControlLookup__(pResource, pParams, ppEntry); } -static inline NV_STATUS kcectxGetSwMethods_DISPATCH(struct KernelCeContext *pChannelDescendant, METHOD **ppMethods, NvU32 *pNumMethods) { +static inline NV_STATUS kcectxGetSwMethods_DISPATCH(struct KernelCeContext *pChannelDescendant, const METHOD **ppMethods, NvU32 *pNumMethods) { return pChannelDescendant->__kcectxGetSwMethods__(pChannelDescendant, ppMethods, pNumMethods); } @@ -244,6 +248,10 @@ return pNotifier->__kcectxUnregisterEvent__(pNotifier, hNotifierClient, hNotifierResource, hEventClient, hEvent); } +static inline NV_STATUS kcectxControlSerialization_Prologue_DISPATCH(struct KernelCeContext *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return pResource->__kcectxControlSerialization_Prologue__(pResource, pCallContext, pParams); +} + static inline NvBool kcectxCanCopy_DISPATCH(struct KernelCeContext *pResource) { return pResource->__kcectxCanCopy__(pResource); } @@ -256,6 +264,10 @@ return pResource->__kcectxIsDuplicate__(pResource, hMemory, pDuplicate); } +static inline void kcectxControlSerialization_Epilogue_DISPATCH(struct KernelCeContext *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + pResource->__kcectxControlSerialization_Epilogue__(pResource, pCallContext, pParams); +} + static inline PEVENTNOTIFICATION *kcectxGetNotificationListPtr_DISPATCH(struct KernelCeContext *pNotifier) { return pNotifier->__kcectxGetNotificationListPtr__(pNotifier); } diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/generated/g_kernel_ce_nvoc.c nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_kernel_ce_nvoc.c --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/generated/g_kernel_ce_nvoc.c 2023-10-25 20:27:06.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_kernel_ce_nvoc.c 2024-03-05 22:18:25.000000000 +0000 @@ -87,7 +87,11 @@ return kceStateLoad(arg0, (struct KernelCE *)(((unsigned char *)arg1) - __nvoc_rtti_KernelCE_OBJENGSTATE.offset), arg2); } -static void __nvoc_thunk_KernelCE_intrservRegisterIntrService(OBJGPU *arg0, struct IntrService *arg1, IntrServiceRecord arg2[163]) { +static NV_STATUS __nvoc_thunk_KernelCE_engstateStateUnload(OBJGPU *pGpu, struct OBJENGSTATE *pKCe, NvU32 flags) { + return kceStateUnload(pGpu, (struct KernelCE *)(((unsigned char *)pKCe) - __nvoc_rtti_KernelCE_OBJENGSTATE.offset), flags); +} + +static void __nvoc_thunk_KernelCE_intrservRegisterIntrService(OBJGPU *arg0, struct IntrService *arg1, IntrServiceRecord arg2[167]) { kceRegisterIntrService(arg0, (struct KernelCE *)(((unsigned char *)arg1) - __nvoc_rtti_KernelCE_IntrService.offset), arg2); } @@ -95,14 +99,6 @@ return kceServiceNotificationInterrupt(arg0, (struct KernelCE *)(((unsigned char *)arg1) - __nvoc_rtti_KernelCE_IntrService.offset), arg2); } -static NV_STATUS __nvoc_thunk_OBJENGSTATE_kceReconcileTunableState(POBJGPU pGpu, struct KernelCE *pEngstate, void *pTunableState) { - return engstateReconcileTunableState(pGpu, (struct OBJENGSTATE *)(((unsigned char *)pEngstate) + __nvoc_rtti_KernelCE_OBJENGSTATE.offset), pTunableState); -} - -static NV_STATUS __nvoc_thunk_OBJENGSTATE_kceStateUnload(POBJGPU pGpu, struct KernelCE *pEngstate, NvU32 arg0) { - return engstateStateUnload(pGpu, (struct OBJENGSTATE *)(((unsigned char *)pEngstate) + __nvoc_rtti_KernelCE_OBJENGSTATE.offset), arg0); -} - static NV_STATUS __nvoc_thunk_OBJENGSTATE_kceStateInitLocked(POBJGPU pGpu, struct KernelCE *pEngstate) { return engstateStateInitLocked(pGpu, (struct OBJENGSTATE *)(((unsigned char *)pEngstate) + __nvoc_rtti_KernelCE_OBJENGSTATE.offset)); } @@ -139,18 +135,6 @@ return engstateStatePreInitUnlocked(pGpu, (struct OBJENGSTATE *)(((unsigned char *)pEngstate) + __nvoc_rtti_KernelCE_OBJENGSTATE.offset)); } -static NV_STATUS __nvoc_thunk_OBJENGSTATE_kceGetTunableState(POBJGPU pGpu, struct KernelCE *pEngstate, void *pTunableState) { - return engstateGetTunableState(pGpu, (struct OBJENGSTATE *)(((unsigned char *)pEngstate) + __nvoc_rtti_KernelCE_OBJENGSTATE.offset), pTunableState); -} - -static NV_STATUS __nvoc_thunk_OBJENGSTATE_kceCompareTunableState(POBJGPU pGpu, struct KernelCE *pEngstate, void *pTunables1, void *pTunables2) { - return engstateCompareTunableState(pGpu, (struct OBJENGSTATE *)(((unsigned char *)pEngstate) + __nvoc_rtti_KernelCE_OBJENGSTATE.offset), pTunables1, pTunables2); -} - -static void __nvoc_thunk_OBJENGSTATE_kceFreeTunableState(POBJGPU pGpu, struct KernelCE *pEngstate, void *pTunableState) { - engstateFreeTunableState(pGpu, (struct OBJENGSTATE *)(((unsigned char *)pEngstate) + __nvoc_rtti_KernelCE_OBJENGSTATE.offset), pTunableState); -} - static NvBool __nvoc_thunk_IntrService_kceClearInterrupt(OBJGPU *pGpu, struct KernelCE *pIntrService, IntrServiceClearInterruptArguments *pParams) { return intrservClearInterrupt(pGpu, (struct IntrService *)(((unsigned char *)pIntrService) + __nvoc_rtti_KernelCE_IntrService.offset), pParams); } @@ -159,14 +143,6 @@ return engstateStatePostLoad(pGpu, (struct OBJENGSTATE *)(((unsigned char *)pEngstate) + __nvoc_rtti_KernelCE_OBJENGSTATE.offset), arg0); } -static NV_STATUS __nvoc_thunk_OBJENGSTATE_kceAllocTunableState(POBJGPU pGpu, struct KernelCE *pEngstate, void **ppTunableState) { - return engstateAllocTunableState(pGpu, (struct OBJENGSTATE *)(((unsigned char *)pEngstate) + __nvoc_rtti_KernelCE_OBJENGSTATE.offset), ppTunableState); -} - -static NV_STATUS __nvoc_thunk_OBJENGSTATE_kceSetTunableState(POBJGPU pGpu, struct KernelCE *pEngstate, void *pTunableState) { - return engstateSetTunableState(pGpu, (struct OBJENGSTATE *)(((unsigned char *)pEngstate) + __nvoc_rtti_KernelCE_OBJENGSTATE.offset), pTunableState); -} - static NvU32 __nvoc_thunk_IntrService_kceServiceInterrupt(OBJGPU *pGpu, struct KernelCE *pIntrService, IntrServiceServiceInterruptArguments *pParams) { return intrservServiceInterrupt(pGpu, (struct IntrService *)(((unsigned char *)pIntrService) + __nvoc_rtti_KernelCE_IntrService.offset), pParams); } @@ -232,27 +208,35 @@ pThis->__kceConstructEngine__ = &kceConstructEngine_IMPL; // Hal function -- kceIsPresent - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x11f0ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 | GH100 */ - { - pThis->__kceIsPresent__ = &kceIsPresent_IMPL; - } + pThis->__kceIsPresent__ = &kceIsPresent_IMPL; // Hal function -- kceStateLoad - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x11f0ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 | GH100 */ - { - pThis->__kceStateLoad__ = &kceStateLoad_GP100; - } + pThis->__kceStateLoad__ = &kceStateLoad_GP100; + + // Hal function -- kceStateUnload + // default + pThis->__kceStateUnload__ = &kceStateUnload_56cd7a; pThis->__kceRegisterIntrService__ = &kceRegisterIntrService_IMPL; pThis->__kceServiceNotificationInterrupt__ = &kceServiceNotificationInterrupt_IMPL; + // Hal function -- kceGetP2PCes + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ + { + pThis->__kceGetP2PCes__ = &kceGetP2PCes_GH100; + } + else + { + pThis->__kceGetP2PCes__ = &kceGetP2PCes_GV100; + } + // Hal function -- kceGetNvlinkAutoConfigCeValues if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x000003e0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 */ { pThis->__kceGetNvlinkAutoConfigCeValues__ = &kceGetNvlinkAutoConfigCeValues_TU102; } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x11f0fc00UL) )) /* ChipHal: GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 | GH100 */ + else { pThis->__kceGetNvlinkAutoConfigCeValues__ = &kceGetNvlinkAutoConfigCeValues_GA100; } @@ -262,45 +246,51 @@ { pThis->__kceGetNvlinkMaxTopoForTable__ = &kceGetNvlinkMaxTopoForTable_GP100; } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x11f0fc00UL) )) /* ChipHal: GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 | GH100 */ + else { pThis->__kceGetNvlinkMaxTopoForTable__ = &kceGetNvlinkMaxTopoForTable_491d52; } // Hal function -- kceIsCurrentMaxTopology - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x11f0fc00UL) )) /* ChipHal: GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 | GH100 */ + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x000003e0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 */ { - pThis->__kceIsCurrentMaxTopology__ = &kceIsCurrentMaxTopology_GA100; + pThis->__kceIsCurrentMaxTopology__ = &kceIsCurrentMaxTopology_491d52; } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x000003e0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 */ + else { - pThis->__kceIsCurrentMaxTopology__ = &kceIsCurrentMaxTopology_491d52; + pThis->__kceIsCurrentMaxTopology__ = &kceIsCurrentMaxTopology_GA100; } - // Hal function -- kceGetPce2lceConfigSize1 - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x000003e0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 */ + // Hal function -- kceGetAutoConfigTableEntry + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ { - pThis->__kceGetPce2lceConfigSize1__ = &kceGetPce2lceConfigSize1_TU102; + pThis->__kceGetAutoConfigTableEntry__ = &kceGetAutoConfigTableEntry_GH100; } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x00000400UL) )) /* ChipHal: GA100 */ + else { - pThis->__kceGetPce2lceConfigSize1__ = &kceGetPce2lceConfigSize1_GA100; + pThis->__kceGetAutoConfigTableEntry__ = &kceGetAutoConfigTableEntry_GV100; } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x01f0f800UL) )) /* ChipHal: GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 */ + + // Hal function -- kceGetPce2lceConfigSize1 + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x00000400UL) )) /* ChipHal: GA100 */ { - pThis->__kceGetPce2lceConfigSize1__ = &kceGetPce2lceConfigSize1_GA102; + pThis->__kceGetPce2lceConfigSize1__ = &kceGetPce2lceConfigSize1_GA100; } else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ { pThis->__kceGetPce2lceConfigSize1__ = &kceGetPce2lceConfigSize1_GH100; } - - // Hal function -- kceGetMappings - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x01f0fc00UL) )) /* ChipHal: GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 */ + else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x000003e0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 */ { - pThis->__kceGetMappings__ = &kceGetMappings_GA100; + pThis->__kceGetPce2lceConfigSize1__ = &kceGetPce2lceConfigSize1_TU102; } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ + else + { + pThis->__kceGetPce2lceConfigSize1__ = &kceGetPce2lceConfigSize1_GA102; + } + + // Hal function -- kceGetMappings + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ { pThis->__kceGetMappings__ = &kceGetMappings_GH100; } @@ -308,13 +298,17 @@ { pThis->__kceGetMappings__ = &kceGetMappings_46f6a7; } + else + { + pThis->__kceGetMappings__ = &kceGetMappings_GA100; + } // Hal function -- kceMapPceLceForC2C if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ { pThis->__kceMapPceLceForC2C__ = &kceMapPceLceForC2C_GH100; } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x01f0ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 */ + else { pThis->__kceMapPceLceForC2C__ = &kceMapPceLceForC2C_46f6a7; } @@ -324,7 +318,8 @@ { pThis->__kceMapPceLceForGRCE__ = &kceMapPceLceForGRCE_GH100; } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x01f0ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 */ + // default + else { pThis->__kceMapPceLceForGRCE__ = &kceMapPceLceForGRCE_b3696a; } @@ -334,21 +329,17 @@ { pThis->__kceMapPceLceForSysmemLinks__ = &kceMapPceLceForSysmemLinks_GA100; } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x01f0f800UL) )) /* ChipHal: GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 */ - { - pThis->__kceMapPceLceForSysmemLinks__ = &kceMapPceLceForSysmemLinks_GA102; - } else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x100003e0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GH100 */ { pThis->__kceMapPceLceForSysmemLinks__ = &kceMapPceLceForSysmemLinks_46f6a7; } - - // Hal function -- kceMapPceLceForNvlinkPeers - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x01f0fc00UL) )) /* ChipHal: GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 */ + else { - pThis->__kceMapPceLceForNvlinkPeers__ = &kceMapPceLceForNvlinkPeers_GA100; + pThis->__kceMapPceLceForSysmemLinks__ = &kceMapPceLceForSysmemLinks_GA102; } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ + + // Hal function -- kceMapPceLceForNvlinkPeers + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ { pThis->__kceMapPceLceForNvlinkPeers__ = &kceMapPceLceForNvlinkPeers_GH100; } @@ -356,27 +347,27 @@ { pThis->__kceMapPceLceForNvlinkPeers__ = &kceMapPceLceForNvlinkPeers_46f6a7; } + else + { + pThis->__kceMapPceLceForNvlinkPeers__ = &kceMapPceLceForNvlinkPeers_GA100; + } // Hal function -- kceGetSysmemSupportedLceMask if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x00000400UL) )) /* ChipHal: GA100 */ { pThis->__kceGetSysmemSupportedLceMask__ = &kceGetSysmemSupportedLceMask_GA100; } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x01f0f800UL) )) /* ChipHal: GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 */ - { - pThis->__kceGetSysmemSupportedLceMask__ = &kceGetSysmemSupportedLceMask_GA102; - } else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x100003e0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GH100 */ { pThis->__kceGetSysmemSupportedLceMask__ = &kceGetSysmemSupportedLceMask_4a4dee; } - - // Hal function -- kceMapAsyncLceDefault - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x01f0fc00UL) )) /* ChipHal: GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 */ + else { - pThis->__kceMapAsyncLceDefault__ = &kceMapAsyncLceDefault_GA100; + pThis->__kceGetSysmemSupportedLceMask__ = &kceGetSysmemSupportedLceMask_GA102; } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ + + // Hal function -- kceMapAsyncLceDefault + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ { pThis->__kceMapAsyncLceDefault__ = &kceMapAsyncLceDefault_GH100; } @@ -384,34 +375,38 @@ { pThis->__kceMapAsyncLceDefault__ = &kceMapAsyncLceDefault_46f6a7; } + else + { + pThis->__kceMapAsyncLceDefault__ = &kceMapAsyncLceDefault_GA100; + } // Hal function -- kceGetNvlinkPeerSupportedLceMask if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000400UL) )) /* ChipHal: GA100 | GH100 */ { pThis->__kceGetNvlinkPeerSupportedLceMask__ = &kceGetNvlinkPeerSupportedLceMask_GA100; } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x01f0f800UL) )) /* ChipHal: GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 */ - { - pThis->__kceGetNvlinkPeerSupportedLceMask__ = &kceGetNvlinkPeerSupportedLceMask_GA102; - } else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x000003e0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 */ { pThis->__kceGetNvlinkPeerSupportedLceMask__ = &kceGetNvlinkPeerSupportedLceMask_4a4dee; } + else + { + pThis->__kceGetNvlinkPeerSupportedLceMask__ = &kceGetNvlinkPeerSupportedLceMask_GA102; + } // Hal function -- kceGetGrceSupportedLceMask if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x00000400UL) )) /* ChipHal: GA100 */ { pThis->__kceGetGrceSupportedLceMask__ = &kceGetGrceSupportedLceMask_GA100; } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x11f0f800UL) )) /* ChipHal: GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 | GH100 */ - { - pThis->__kceGetGrceSupportedLceMask__ = &kceGetGrceSupportedLceMask_GA102; - } else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x000003e0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 */ { pThis->__kceGetGrceSupportedLceMask__ = &kceGetGrceSupportedLceMask_4a4dee; } + else + { + pThis->__kceGetGrceSupportedLceMask__ = &kceGetGrceSupportedLceMask_GA102; + } // Hal function -- kceIsGenXorHigherSupported if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x00000400UL) )) /* ChipHal: GA100 */ @@ -422,7 +417,7 @@ { pThis->__kceIsGenXorHigherSupported__ = &kceIsGenXorHigherSupported_GH100; } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x01f0fbe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 */ + else { pThis->__kceIsGenXorHigherSupported__ = &kceIsGenXorHigherSupported_cbe027; } @@ -432,7 +427,7 @@ { pThis->__kceApplyGen4orHigherMapping__ = &kceApplyGen4orHigherMapping_GA100; } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x11f0fbe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 | GH100 */ + else { pThis->__kceApplyGen4orHigherMapping__ = &kceApplyGen4orHigherMapping_b3696a; } @@ -443,14 +438,12 @@ pThis->__nvoc_base_OBJENGSTATE.__engstateStateLoad__ = &__nvoc_thunk_KernelCE_engstateStateLoad; + pThis->__nvoc_base_OBJENGSTATE.__engstateStateUnload__ = &__nvoc_thunk_KernelCE_engstateStateUnload; + pThis->__nvoc_base_IntrService.__intrservRegisterIntrService__ = &__nvoc_thunk_KernelCE_intrservRegisterIntrService; pThis->__nvoc_base_IntrService.__intrservServiceNotificationInterrupt__ = &__nvoc_thunk_KernelCE_intrservServiceNotificationInterrupt; - pThis->__kceReconcileTunableState__ = &__nvoc_thunk_OBJENGSTATE_kceReconcileTunableState; - - pThis->__kceStateUnload__ = &__nvoc_thunk_OBJENGSTATE_kceStateUnload; - pThis->__kceStateInitLocked__ = &__nvoc_thunk_OBJENGSTATE_kceStateInitLocked; pThis->__kceStatePreLoad__ = &__nvoc_thunk_OBJENGSTATE_kceStatePreLoad; @@ -469,20 +462,10 @@ pThis->__kceStatePreInitUnlocked__ = &__nvoc_thunk_OBJENGSTATE_kceStatePreInitUnlocked; - pThis->__kceGetTunableState__ = &__nvoc_thunk_OBJENGSTATE_kceGetTunableState; - - pThis->__kceCompareTunableState__ = &__nvoc_thunk_OBJENGSTATE_kceCompareTunableState; - - pThis->__kceFreeTunableState__ = &__nvoc_thunk_OBJENGSTATE_kceFreeTunableState; - pThis->__kceClearInterrupt__ = &__nvoc_thunk_IntrService_kceClearInterrupt; pThis->__kceStatePostLoad__ = &__nvoc_thunk_OBJENGSTATE_kceStatePostLoad; - pThis->__kceAllocTunableState__ = &__nvoc_thunk_OBJENGSTATE_kceAllocTunableState; - - pThis->__kceSetTunableState__ = &__nvoc_thunk_OBJENGSTATE_kceSetTunableState; - pThis->__kceServiceInterrupt__ = &__nvoc_thunk_IntrService_kceServiceInterrupt; } @@ -508,13 +491,16 @@ KernelCE *pThis; RmHalspecOwner *pRmhalspecowner; - pThis = portMemAllocNonPaged(sizeof(KernelCE)); - if (pThis == NULL) return NV_ERR_NO_MEMORY; + status = __nvoc_handleObjCreateMemAlloc(createFlags, sizeof(KernelCE), (void**)&pThis, (void**)ppThis); + if (status != NV_OK) + return status; portMemSet(pThis, 0, sizeof(KernelCE)); __nvoc_initRtti(staticCast(pThis, Dynamic), &__nvoc_class_def_KernelCE); + pThis->__nvoc_base_OBJENGSTATE.__nvoc_base_Object.createFlags = createFlags; + if (pParent != NULL && !(createFlags & NVOC_OBJ_CREATE_FLAGS_PARENT_HALSPEC_ONLY)) { pParentObj = dynamicCast(pParent, Object); @@ -534,11 +520,17 @@ if (status != NV_OK) goto __nvoc_objCreate_KernelCE_cleanup; *ppThis = pThis; + return NV_OK; __nvoc_objCreate_KernelCE_cleanup: // do not call destructors here since the constructor already called them - portMemFree(pThis); + if (createFlags & NVOC_OBJ_CREATE_FLAGS_IN_PLACE_CONSTRUCT) + portMemSet(pThis, 0, sizeof(KernelCE)); + else + portMemFree(pThis); + + // coverity[leaked_storage:FALSE] return status; } diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/generated/g_kernel_ce_nvoc.h nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_kernel_ce_nvoc.h --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/generated/g_kernel_ce_nvoc.h 2023-10-25 20:27:06.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_kernel_ce_nvoc.h 2024-03-05 22:18:25.000000000 +0000 @@ -7,7 +7,7 @@ #endif /* - * SPDX-FileCopyrightText: Copyright (c) 1993-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 1993-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -110,11 +110,14 @@ NV_STATUS (*__kceConstructEngine__)(OBJGPU *, struct KernelCE *, ENGDESCRIPTOR); NvBool (*__kceIsPresent__)(OBJGPU *, struct KernelCE *); NV_STATUS (*__kceStateLoad__)(OBJGPU *, struct KernelCE *, NvU32); + NV_STATUS (*__kceStateUnload__)(OBJGPU *, struct KernelCE *, NvU32); void (*__kceRegisterIntrService__)(OBJGPU *, struct KernelCE *, IntrServiceRecord *); NV_STATUS (*__kceServiceNotificationInterrupt__)(OBJGPU *, struct KernelCE *, IntrServiceServiceNotificationInterruptArguments *); + NV_STATUS (*__kceGetP2PCes__)(struct KernelCE *, OBJGPU *, NvU32, NvU32 *); NV_STATUS (*__kceGetNvlinkAutoConfigCeValues__)(OBJGPU *, struct KernelCE *, NvU32 *, NvU32 *, NvU32 *); NvBool (*__kceGetNvlinkMaxTopoForTable__)(OBJGPU *, struct KernelCE *, struct NVLINK_TOPOLOGY_PARAMS *, void *, NvU32, NvU32 *); NvBool (*__kceIsCurrentMaxTopology__)(OBJGPU *, struct KernelCE *, struct NVLINK_TOPOLOGY_PARAMS *, NvU32 *, NvU32 *); + NvBool (*__kceGetAutoConfigTableEntry__)(OBJGPU *, struct KernelCE *, struct NVLINK_TOPOLOGY_PARAMS *, struct NVLINK_CE_AUTO_CONFIG_TABLE *, NvU32, NvU32 *, NvU32 *); NvU32 (*__kceGetPce2lceConfigSize1__)(struct KernelCE *); NV_STATUS (*__kceGetMappings__)(OBJGPU *, struct KernelCE *, NVLINK_TOPOLOGY_PARAMS *, NvU32 *, NvU32 *, NvU32 *); NV_STATUS (*__kceMapPceLceForC2C__)(OBJGPU *, struct KernelCE *, NvU32 *, NvU32 *, NvU32 *); @@ -127,8 +130,6 @@ NvU32 (*__kceGetGrceSupportedLceMask__)(OBJGPU *, struct KernelCE *); NvBool (*__kceIsGenXorHigherSupported__)(OBJGPU *, struct KernelCE *, NvU32); void (*__kceApplyGen4orHigherMapping__)(OBJGPU *, struct KernelCE *, NvU32 *, NvU32 *, NvU32, NvU32); - NV_STATUS (*__kceReconcileTunableState__)(POBJGPU, struct KernelCE *, void *); - NV_STATUS (*__kceStateUnload__)(POBJGPU, struct KernelCE *, NvU32); NV_STATUS (*__kceStateInitLocked__)(POBJGPU, struct KernelCE *); NV_STATUS (*__kceStatePreLoad__)(POBJGPU, struct KernelCE *, NvU32); NV_STATUS (*__kceStatePostUnload__)(POBJGPU, struct KernelCE *, NvU32); @@ -138,13 +139,8 @@ void (*__kceInitMissing__)(POBJGPU, struct KernelCE *); NV_STATUS (*__kceStatePreInitLocked__)(POBJGPU, struct KernelCE *); NV_STATUS (*__kceStatePreInitUnlocked__)(POBJGPU, struct KernelCE *); - NV_STATUS (*__kceGetTunableState__)(POBJGPU, struct KernelCE *, void *); - NV_STATUS (*__kceCompareTunableState__)(POBJGPU, struct KernelCE *, void *, void *); - void (*__kceFreeTunableState__)(POBJGPU, struct KernelCE *, void *); NvBool (*__kceClearInterrupt__)(OBJGPU *, struct KernelCE *, IntrServiceClearInterruptArguments *); NV_STATUS (*__kceStatePostLoad__)(POBJGPU, struct KernelCE *, NvU32); - NV_STATUS (*__kceAllocTunableState__)(POBJGPU, struct KernelCE *, void **); - NV_STATUS (*__kceSetTunableState__)(POBJGPU, struct KernelCE *, void *); NvU32 (*__kceServiceInterrupt__)(OBJGPU *, struct KernelCE *, IntrServiceServiceInterruptArguments *); NvU32 publicID; NvBool bShimOwner; @@ -153,7 +149,7 @@ NvU32 nvlinkNumPeers; NvBool bIsAutoConfigEnabled; NvBool bUseGen4Mapping; - struct IO_APERTURE aperture; + struct IoAperture aperture; }; #ifndef __NVOC_CLASS_KernelCE_TYPEDEF__ @@ -191,14 +187,20 @@ #define kceIsPresent_HAL(pGpu, pKCe) kceIsPresent_DISPATCH(pGpu, pKCe) #define kceStateLoad(arg0, arg1, arg2) kceStateLoad_DISPATCH(arg0, arg1, arg2) #define kceStateLoad_HAL(arg0, arg1, arg2) kceStateLoad_DISPATCH(arg0, arg1, arg2) +#define kceStateUnload(pGpu, pKCe, flags) kceStateUnload_DISPATCH(pGpu, pKCe, flags) +#define kceStateUnload_HAL(pGpu, pKCe, flags) kceStateUnload_DISPATCH(pGpu, pKCe, flags) #define kceRegisterIntrService(arg0, arg1, arg2) kceRegisterIntrService_DISPATCH(arg0, arg1, arg2) #define kceServiceNotificationInterrupt(arg0, arg1, arg2) kceServiceNotificationInterrupt_DISPATCH(arg0, arg1, arg2) +#define kceGetP2PCes(arg0, pGpu, gpuMask, nvlinkP2PCeMask) kceGetP2PCes_DISPATCH(arg0, pGpu, gpuMask, nvlinkP2PCeMask) +#define kceGetP2PCes_HAL(arg0, pGpu, gpuMask, nvlinkP2PCeMask) kceGetP2PCes_DISPATCH(arg0, pGpu, gpuMask, nvlinkP2PCeMask) #define kceGetNvlinkAutoConfigCeValues(pGpu, pKCe, arg0, arg1, arg2) kceGetNvlinkAutoConfigCeValues_DISPATCH(pGpu, pKCe, arg0, arg1, arg2) #define kceGetNvlinkAutoConfigCeValues_HAL(pGpu, pKCe, arg0, arg1, arg2) kceGetNvlinkAutoConfigCeValues_DISPATCH(pGpu, pKCe, arg0, arg1, arg2) #define kceGetNvlinkMaxTopoForTable(pGpu, pKCe, arg0, arg1, arg2, arg3) kceGetNvlinkMaxTopoForTable_DISPATCH(pGpu, pKCe, arg0, arg1, arg2, arg3) #define kceGetNvlinkMaxTopoForTable_HAL(pGpu, pKCe, arg0, arg1, arg2, arg3) kceGetNvlinkMaxTopoForTable_DISPATCH(pGpu, pKCe, arg0, arg1, arg2, arg3) #define kceIsCurrentMaxTopology(pGpu, arg0, arg1, arg2, arg3) kceIsCurrentMaxTopology_DISPATCH(pGpu, arg0, arg1, arg2, arg3) #define kceIsCurrentMaxTopology_HAL(pGpu, arg0, arg1, arg2, arg3) kceIsCurrentMaxTopology_DISPATCH(pGpu, arg0, arg1, arg2, arg3) +#define kceGetAutoConfigTableEntry(pGpu, pKCe, arg0, arg1, arg2, arg3, arg4) kceGetAutoConfigTableEntry_DISPATCH(pGpu, pKCe, arg0, arg1, arg2, arg3, arg4) +#define kceGetAutoConfigTableEntry_HAL(pGpu, pKCe, arg0, arg1, arg2, arg3, arg4) kceGetAutoConfigTableEntry_DISPATCH(pGpu, pKCe, arg0, arg1, arg2, arg3, arg4) #define kceGetPce2lceConfigSize1(arg0) kceGetPce2lceConfigSize1_DISPATCH(arg0) #define kceGetPce2lceConfigSize1_HAL(arg0) kceGetPce2lceConfigSize1_DISPATCH(arg0) #define kceGetMappings(pGpu, pCe, arg0, arg1, arg2, arg3) kceGetMappings_DISPATCH(pGpu, pCe, arg0, arg1, arg2, arg3) @@ -223,8 +225,6 @@ #define kceIsGenXorHigherSupported_HAL(pGpu, pCe, checkGen) kceIsGenXorHigherSupported_DISPATCH(pGpu, pCe, checkGen) #define kceApplyGen4orHigherMapping(pGpu, pCe, arg0, arg1, arg2, arg3) kceApplyGen4orHigherMapping_DISPATCH(pGpu, pCe, arg0, arg1, arg2, arg3) #define kceApplyGen4orHigherMapping_HAL(pGpu, pCe, arg0, arg1, arg2, arg3) kceApplyGen4orHigherMapping_DISPATCH(pGpu, pCe, arg0, arg1, arg2, arg3) -#define kceReconcileTunableState(pGpu, pEngstate, pTunableState) kceReconcileTunableState_DISPATCH(pGpu, pEngstate, pTunableState) -#define kceStateUnload(pGpu, pEngstate, arg0) kceStateUnload_DISPATCH(pGpu, pEngstate, arg0) #define kceStateInitLocked(pGpu, pEngstate) kceStateInitLocked_DISPATCH(pGpu, pEngstate) #define kceStatePreLoad(pGpu, pEngstate, arg0) kceStatePreLoad_DISPATCH(pGpu, pEngstate, arg0) #define kceStatePostUnload(pGpu, pEngstate, arg0) kceStatePostUnload_DISPATCH(pGpu, pEngstate, arg0) @@ -234,13 +234,8 @@ #define kceInitMissing(pGpu, pEngstate) kceInitMissing_DISPATCH(pGpu, pEngstate) #define kceStatePreInitLocked(pGpu, pEngstate) kceStatePreInitLocked_DISPATCH(pGpu, pEngstate) #define kceStatePreInitUnlocked(pGpu, pEngstate) kceStatePreInitUnlocked_DISPATCH(pGpu, pEngstate) -#define kceGetTunableState(pGpu, pEngstate, pTunableState) kceGetTunableState_DISPATCH(pGpu, pEngstate, pTunableState) -#define kceCompareTunableState(pGpu, pEngstate, pTunables1, pTunables2) kceCompareTunableState_DISPATCH(pGpu, pEngstate, pTunables1, pTunables2) -#define kceFreeTunableState(pGpu, pEngstate, pTunableState) kceFreeTunableState_DISPATCH(pGpu, pEngstate, pTunableState) #define kceClearInterrupt(pGpu, pIntrService, pParams) kceClearInterrupt_DISPATCH(pGpu, pIntrService, pParams) #define kceStatePostLoad(pGpu, pEngstate, arg0) kceStatePostLoad_DISPATCH(pGpu, pEngstate, arg0) -#define kceAllocTunableState(pGpu, pEngstate, ppTunableState) kceAllocTunableState_DISPATCH(pGpu, pEngstate, ppTunableState) -#define kceSetTunableState(pGpu, pEngstate, pTunableState) kceSetTunableState_DISPATCH(pGpu, pEngstate, pTunableState) #define kceServiceInterrupt(pGpu, pIntrService, pParams) kceServiceInterrupt_DISPATCH(pGpu, pIntrService, pParams) static inline void kceNonstallIntrCheckAndClear_b3696a(OBJGPU *arg0, struct KernelCE *arg1, struct THREAD_STATE_NODE *arg2) { return; @@ -313,20 +308,6 @@ #define kceIsCeNvlinkP2P_HAL(pGpu, pKCe) kceIsCeNvlinkP2P(pGpu, pKCe) -NV_STATUS kceGetP2PCes_GV100(struct KernelCE *arg0, OBJGPU *pGpu, NvU32 gpuMask, NvU32 *nvlinkP2PCeMask); - - -#ifdef __nvoc_kernel_ce_h_disabled -static inline NV_STATUS kceGetP2PCes(struct KernelCE *arg0, OBJGPU *pGpu, NvU32 gpuMask, NvU32 *nvlinkP2PCeMask) { - NV_ASSERT_FAILED_PRECOMP("KernelCE was disabled!"); - return NV_ERR_NOT_SUPPORTED; -} -#else //__nvoc_kernel_ce_h_disabled -#define kceGetP2PCes(arg0, pGpu, gpuMask, nvlinkP2PCeMask) kceGetP2PCes_GV100(arg0, pGpu, gpuMask, nvlinkP2PCeMask) -#endif //__nvoc_kernel_ce_h_disabled - -#define kceGetP2PCes_HAL(arg0, pGpu, gpuMask, nvlinkP2PCeMask) kceGetP2PCes(arg0, pGpu, gpuMask, nvlinkP2PCeMask) - void kceGetSysmemRWLCEs_GV100(struct KernelCE *arg0, NvU32 *rd, NvU32 *wr); @@ -353,20 +334,6 @@ #define kceClearAssignedNvlinkPeerMasks_HAL(pGpu, pKCe) kceClearAssignedNvlinkPeerMasks(pGpu, pKCe) -NvBool kceGetAutoConfigTableEntry_GV100(OBJGPU *pGpu, struct KernelCE *pKCe, struct NVLINK_TOPOLOGY_PARAMS *arg0, struct NVLINK_CE_AUTO_CONFIG_TABLE *arg1, NvU32 arg2, NvU32 *arg3, NvU32 *arg4); - - -#ifdef __nvoc_kernel_ce_h_disabled -static inline NvBool kceGetAutoConfigTableEntry(OBJGPU *pGpu, struct KernelCE *pKCe, struct NVLINK_TOPOLOGY_PARAMS *arg0, struct NVLINK_CE_AUTO_CONFIG_TABLE *arg1, NvU32 arg2, NvU32 *arg3, NvU32 *arg4) { - NV_ASSERT_FAILED_PRECOMP("KernelCE was disabled!"); - return NV_FALSE; -} -#else //__nvoc_kernel_ce_h_disabled -#define kceGetAutoConfigTableEntry(pGpu, pKCe, arg0, arg1, arg2, arg3, arg4) kceGetAutoConfigTableEntry_GV100(pGpu, pKCe, arg0, arg1, arg2, arg3, arg4) -#endif //__nvoc_kernel_ce_h_disabled - -#define kceGetAutoConfigTableEntry_HAL(pGpu, pKCe, arg0, arg1, arg2, arg3, arg4) kceGetAutoConfigTableEntry(pGpu, pKCe, arg0, arg1, arg2, arg3, arg4) - NvU32 kceGetGrceConfigSize1_TU102(struct KernelCE *arg0); @@ -399,9 +366,17 @@ return arg1->__kceStateLoad__(arg0, arg1, arg2); } -void kceRegisterIntrService_IMPL(OBJGPU *arg0, struct KernelCE *arg1, IntrServiceRecord arg2[163]); +static inline NV_STATUS kceStateUnload_56cd7a(OBJGPU *pGpu, struct KernelCE *pKCe, NvU32 flags) { + return NV_OK; +} + +static inline NV_STATUS kceStateUnload_DISPATCH(OBJGPU *pGpu, struct KernelCE *pKCe, NvU32 flags) { + return pKCe->__kceStateUnload__(pGpu, pKCe, flags); +} + +void kceRegisterIntrService_IMPL(OBJGPU *arg0, struct KernelCE *arg1, IntrServiceRecord arg2[167]); -static inline void kceRegisterIntrService_DISPATCH(OBJGPU *arg0, struct KernelCE *arg1, IntrServiceRecord arg2[163]) { +static inline void kceRegisterIntrService_DISPATCH(OBJGPU *arg0, struct KernelCE *arg1, IntrServiceRecord arg2[167]) { arg1->__kceRegisterIntrService__(arg0, arg1, arg2); } @@ -411,6 +386,14 @@ return arg1->__kceServiceNotificationInterrupt__(arg0, arg1, arg2); } +NV_STATUS kceGetP2PCes_GV100(struct KernelCE *arg0, OBJGPU *pGpu, NvU32 gpuMask, NvU32 *nvlinkP2PCeMask); + +NV_STATUS kceGetP2PCes_GH100(struct KernelCE *arg0, OBJGPU *pGpu, NvU32 gpuMask, NvU32 *nvlinkP2PCeMask); + +static inline NV_STATUS kceGetP2PCes_DISPATCH(struct KernelCE *arg0, OBJGPU *pGpu, NvU32 gpuMask, NvU32 *nvlinkP2PCeMask) { + return arg0->__kceGetP2PCes__(arg0, pGpu, gpuMask, nvlinkP2PCeMask); +} + NV_STATUS kceGetNvlinkAutoConfigCeValues_TU102(OBJGPU *pGpu, struct KernelCE *pKCe, NvU32 *arg0, NvU32 *arg1, NvU32 *arg2); NV_STATUS kceGetNvlinkAutoConfigCeValues_GA100(OBJGPU *pGpu, struct KernelCE *pKCe, NvU32 *arg0, NvU32 *arg1, NvU32 *arg2); @@ -439,6 +422,14 @@ return arg0->__kceIsCurrentMaxTopology__(pGpu, arg0, arg1, arg2, arg3); } +NvBool kceGetAutoConfigTableEntry_GV100(OBJGPU *pGpu, struct KernelCE *pKCe, struct NVLINK_TOPOLOGY_PARAMS *arg0, struct NVLINK_CE_AUTO_CONFIG_TABLE *arg1, NvU32 arg2, NvU32 *arg3, NvU32 *arg4); + +NvBool kceGetAutoConfigTableEntry_GH100(OBJGPU *pGpu, struct KernelCE *pKCe, struct NVLINK_TOPOLOGY_PARAMS *arg0, struct NVLINK_CE_AUTO_CONFIG_TABLE *arg1, NvU32 arg2, NvU32 *arg3, NvU32 *arg4); + +static inline NvBool kceGetAutoConfigTableEntry_DISPATCH(OBJGPU *pGpu, struct KernelCE *pKCe, struct NVLINK_TOPOLOGY_PARAMS *arg0, struct NVLINK_CE_AUTO_CONFIG_TABLE *arg1, NvU32 arg2, NvU32 *arg3, NvU32 *arg4) { + return pKCe->__kceGetAutoConfigTableEntry__(pGpu, pKCe, arg0, arg1, arg2, arg3, arg4); +} + NvU32 kceGetPce2lceConfigSize1_TU102(struct KernelCE *arg0); NvU32 kceGetPce2lceConfigSize1_GA100(struct KernelCE *arg0); @@ -577,14 +568,6 @@ pCe->__kceApplyGen4orHigherMapping__(pGpu, pCe, arg0, arg1, arg2, arg3); } -static inline NV_STATUS kceReconcileTunableState_DISPATCH(POBJGPU pGpu, struct KernelCE *pEngstate, void *pTunableState) { - return pEngstate->__kceReconcileTunableState__(pGpu, pEngstate, pTunableState); -} - -static inline NV_STATUS kceStateUnload_DISPATCH(POBJGPU pGpu, struct KernelCE *pEngstate, NvU32 arg0) { - return pEngstate->__kceStateUnload__(pGpu, pEngstate, arg0); -} - static inline NV_STATUS kceStateInitLocked_DISPATCH(POBJGPU pGpu, struct KernelCE *pEngstate) { return pEngstate->__kceStateInitLocked__(pGpu, pEngstate); } @@ -621,18 +604,6 @@ return pEngstate->__kceStatePreInitUnlocked__(pGpu, pEngstate); } -static inline NV_STATUS kceGetTunableState_DISPATCH(POBJGPU pGpu, struct KernelCE *pEngstate, void *pTunableState) { - return pEngstate->__kceGetTunableState__(pGpu, pEngstate, pTunableState); -} - -static inline NV_STATUS kceCompareTunableState_DISPATCH(POBJGPU pGpu, struct KernelCE *pEngstate, void *pTunables1, void *pTunables2) { - return pEngstate->__kceCompareTunableState__(pGpu, pEngstate, pTunables1, pTunables2); -} - -static inline void kceFreeTunableState_DISPATCH(POBJGPU pGpu, struct KernelCE *pEngstate, void *pTunableState) { - pEngstate->__kceFreeTunableState__(pGpu, pEngstate, pTunableState); -} - static inline NvBool kceClearInterrupt_DISPATCH(OBJGPU *pGpu, struct KernelCE *pIntrService, IntrServiceClearInterruptArguments *pParams) { return pIntrService->__kceClearInterrupt__(pGpu, pIntrService, pParams); } @@ -641,14 +612,6 @@ return pEngstate->__kceStatePostLoad__(pGpu, pEngstate, arg0); } -static inline NV_STATUS kceAllocTunableState_DISPATCH(POBJGPU pGpu, struct KernelCE *pEngstate, void **ppTunableState) { - return pEngstate->__kceAllocTunableState__(pGpu, pEngstate, ppTunableState); -} - -static inline NV_STATUS kceSetTunableState_DISPATCH(POBJGPU pGpu, struct KernelCE *pEngstate, void *pTunableState) { - return pEngstate->__kceSetTunableState__(pGpu, pEngstate, pTunableState); -} - static inline NvU32 kceServiceInterrupt_DISPATCH(OBJGPU *pGpu, struct KernelCE *pIntrService, IntrServiceServiceInterruptArguments *pParams) { return pIntrService->__kceServiceInterrupt__(pGpu, pIntrService, pParams); } @@ -732,24 +695,24 @@ continue; \ } -// Iterate over all CE visible to hClient -#define KCE_ITER_CLIENT_BEGIN(pGpu, pKCeIter, hClient) \ - { \ - NvU32 maxCe = ENG_CE__SIZE_1; \ - NV_STATUS kceStatus; \ - NvU32 kceInst; \ - NvU32 kceIdx; \ - for (kceInst = 0; kceInst < maxCe; kceInst++) \ - { \ - kceStatus = ceIndexFromType(pGpu, hClient, RM_ENGINE_TYPE_COPY(kceInst), &kceIdx); \ - if (kceStatus != NV_OK) \ - { \ - continue; \ - } \ - pKCeIter = GPU_GET_KCE(pGpu, kceIdx); \ - if (pKCeIter == NULL) \ - { \ - continue; \ +// Iterate over all CE visible to Device +#define KCE_ITER_DEVICE_BEGIN(pGpu, pKCeIter, pDevice) \ + { \ + NvU32 maxCe = ENG_CE__SIZE_1; \ + NV_STATUS kceStatus; \ + NvU32 kceInst; \ + NvU32 kceIdx; \ + for (kceInst = 0; kceInst < maxCe; kceInst++) \ + { \ + kceStatus = ceIndexFromType(pGpu, pDevice, RM_ENGINE_TYPE_COPY(kceInst), &kceIdx); \ + if (kceStatus != NV_OK) \ + { \ + continue; \ + } \ + pKCeIter = GPU_GET_KCE(pGpu, kceIdx); \ + if (pKCeIter == NULL) \ + { \ + continue; \ } #define KCE_ITER_END \ diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/generated/g_kernel_channel_group_api_nvoc.c nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_kernel_channel_group_api_nvoc.c --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/generated/g_kernel_channel_group_api_nvoc.c 2023-10-25 20:27:06.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_kernel_channel_group_api_nvoc.c 2024-03-05 22:18:25.000000000 +0000 @@ -105,44 +105,24 @@ return gpuresShareCallback((struct GpuResource *)(((unsigned char *)pGpuResource) + __nvoc_rtti_KernelChannelGroupApi_GpuResource.offset), pInvokingClient, pParentRef, pSharePolicy); } -static NV_STATUS __nvoc_thunk_GpuResource_kchangrpapiUnmap(struct KernelChannelGroupApi *pGpuResource, struct CALL_CONTEXT *pCallContext, struct RsCpuMapping *pCpuMapping) { - return gpuresUnmap((struct GpuResource *)(((unsigned char *)pGpuResource) + __nvoc_rtti_KernelChannelGroupApi_GpuResource.offset), pCallContext, pCpuMapping); -} - -static NV_STATUS __nvoc_thunk_RmResource_kchangrpapiGetMemInterMapParams(struct KernelChannelGroupApi *pRmResource, RMRES_MEM_INTER_MAP_PARAMS *pParams) { - return rmresGetMemInterMapParams((struct RmResource *)(((unsigned char *)pRmResource) + __nvoc_rtti_KernelChannelGroupApi_RmResource.offset), pParams); +static NV_STATUS __nvoc_thunk_RmResource_kchangrpapiCheckMemInterUnmap(struct KernelChannelGroupApi *pRmResource, NvBool bSubdeviceHandleProvided) { + return rmresCheckMemInterUnmap((struct RmResource *)(((unsigned char *)pRmResource) + __nvoc_rtti_KernelChannelGroupApi_RmResource.offset), bSubdeviceHandleProvided); } -static NV_STATUS __nvoc_thunk_RmResource_kchangrpapiGetMemoryMappingDescriptor(struct KernelChannelGroupApi *pRmResource, struct MEMORY_DESCRIPTOR **ppMemDesc) { - return rmresGetMemoryMappingDescriptor((struct RmResource *)(((unsigned char *)pRmResource) + __nvoc_rtti_KernelChannelGroupApi_RmResource.offset), ppMemDesc); +static NV_STATUS __nvoc_thunk_RsResource_kchangrpapiMapTo(struct KernelChannelGroupApi *pResource, RS_RES_MAP_TO_PARAMS *pParams) { + return resMapTo((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_KernelChannelGroupApi_RsResource.offset), pParams); } static NV_STATUS __nvoc_thunk_GpuResource_kchangrpapiGetMapAddrSpace(struct KernelChannelGroupApi *pGpuResource, struct CALL_CONTEXT *pCallContext, NvU32 mapFlags, NV_ADDRESS_SPACE *pAddrSpace) { return gpuresGetMapAddrSpace((struct GpuResource *)(((unsigned char *)pGpuResource) + __nvoc_rtti_KernelChannelGroupApi_GpuResource.offset), pCallContext, mapFlags, pAddrSpace); } -static NvHandle __nvoc_thunk_GpuResource_kchangrpapiGetInternalObjectHandle(struct KernelChannelGroupApi *pGpuResource) { - return gpuresGetInternalObjectHandle((struct GpuResource *)(((unsigned char *)pGpuResource) + __nvoc_rtti_KernelChannelGroupApi_GpuResource.offset)); -} - -static NV_STATUS __nvoc_thunk_RsResource_kchangrpapiControlFilter(struct KernelChannelGroupApi *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { - return resControlFilter((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_KernelChannelGroupApi_RsResource.offset), pCallContext, pParams); -} - -static void __nvoc_thunk_RsResource_kchangrpapiAddAdditionalDependants(struct RsClient *pClient, struct KernelChannelGroupApi *pResource, RsResourceRef *pReference) { - resAddAdditionalDependants(pClient, (struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_KernelChannelGroupApi_RsResource.offset), pReference); -} - static NvU32 __nvoc_thunk_RsResource_kchangrpapiGetRefCount(struct KernelChannelGroupApi *pResource) { return resGetRefCount((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_KernelChannelGroupApi_RsResource.offset)); } -static NV_STATUS __nvoc_thunk_RmResource_kchangrpapiCheckMemInterUnmap(struct KernelChannelGroupApi *pRmResource, NvBool bSubdeviceHandleProvided) { - return rmresCheckMemInterUnmap((struct RmResource *)(((unsigned char *)pRmResource) + __nvoc_rtti_KernelChannelGroupApi_RmResource.offset), bSubdeviceHandleProvided); -} - -static NV_STATUS __nvoc_thunk_RsResource_kchangrpapiMapTo(struct KernelChannelGroupApi *pResource, RS_RES_MAP_TO_PARAMS *pParams) { - return resMapTo((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_KernelChannelGroupApi_RsResource.offset), pParams); +static void __nvoc_thunk_RsResource_kchangrpapiAddAdditionalDependants(struct RsClient *pClient, struct KernelChannelGroupApi *pResource, RsResourceRef *pReference) { + resAddAdditionalDependants(pClient, (struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_KernelChannelGroupApi_RsResource.offset), pReference); } static NV_STATUS __nvoc_thunk_RmResource_kchangrpapiControl_Prologue(struct KernelChannelGroupApi *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { @@ -157,18 +137,10 @@ return gpuresInternalControlForward((struct GpuResource *)(((unsigned char *)pGpuResource) + __nvoc_rtti_KernelChannelGroupApi_GpuResource.offset), command, pParams, size); } -static void __nvoc_thunk_RsResource_kchangrpapiPreDestruct(struct KernelChannelGroupApi *pResource) { - resPreDestruct((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_KernelChannelGroupApi_RsResource.offset)); -} - static NV_STATUS __nvoc_thunk_RsResource_kchangrpapiUnmapFrom(struct KernelChannelGroupApi *pResource, RS_RES_UNMAP_FROM_PARAMS *pParams) { return resUnmapFrom((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_KernelChannelGroupApi_RsResource.offset), pParams); } -static NV_STATUS __nvoc_thunk_RsResource_kchangrpapiIsDuplicate(struct KernelChannelGroupApi *pResource, NvHandle hMemory, NvBool *pDuplicate) { - return resIsDuplicate((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_KernelChannelGroupApi_RsResource.offset), hMemory, pDuplicate); -} - static void __nvoc_thunk_RmResource_kchangrpapiControl_Epilogue(struct KernelChannelGroupApi *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { rmresControl_Epilogue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_KernelChannelGroupApi_RmResource.offset), pCallContext, pParams); } @@ -177,6 +149,42 @@ return resControlLookup((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_KernelChannelGroupApi_RsResource.offset), pParams, ppEntry); } +static NvHandle __nvoc_thunk_GpuResource_kchangrpapiGetInternalObjectHandle(struct KernelChannelGroupApi *pGpuResource) { + return gpuresGetInternalObjectHandle((struct GpuResource *)(((unsigned char *)pGpuResource) + __nvoc_rtti_KernelChannelGroupApi_GpuResource.offset)); +} + +static NV_STATUS __nvoc_thunk_GpuResource_kchangrpapiUnmap(struct KernelChannelGroupApi *pGpuResource, struct CALL_CONTEXT *pCallContext, struct RsCpuMapping *pCpuMapping) { + return gpuresUnmap((struct GpuResource *)(((unsigned char *)pGpuResource) + __nvoc_rtti_KernelChannelGroupApi_GpuResource.offset), pCallContext, pCpuMapping); +} + +static NV_STATUS __nvoc_thunk_RmResource_kchangrpapiGetMemInterMapParams(struct KernelChannelGroupApi *pRmResource, RMRES_MEM_INTER_MAP_PARAMS *pParams) { + return rmresGetMemInterMapParams((struct RmResource *)(((unsigned char *)pRmResource) + __nvoc_rtti_KernelChannelGroupApi_RmResource.offset), pParams); +} + +static NV_STATUS __nvoc_thunk_RmResource_kchangrpapiGetMemoryMappingDescriptor(struct KernelChannelGroupApi *pRmResource, struct MEMORY_DESCRIPTOR **ppMemDesc) { + return rmresGetMemoryMappingDescriptor((struct RmResource *)(((unsigned char *)pRmResource) + __nvoc_rtti_KernelChannelGroupApi_RmResource.offset), ppMemDesc); +} + +static NV_STATUS __nvoc_thunk_RsResource_kchangrpapiControlFilter(struct KernelChannelGroupApi *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return resControlFilter((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_KernelChannelGroupApi_RsResource.offset), pCallContext, pParams); +} + +static NV_STATUS __nvoc_thunk_RmResource_kchangrpapiControlSerialization_Prologue(struct KernelChannelGroupApi *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return rmresControlSerialization_Prologue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_KernelChannelGroupApi_RmResource.offset), pCallContext, pParams); +} + +static void __nvoc_thunk_RsResource_kchangrpapiPreDestruct(struct KernelChannelGroupApi *pResource) { + resPreDestruct((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_KernelChannelGroupApi_RsResource.offset)); +} + +static NV_STATUS __nvoc_thunk_RsResource_kchangrpapiIsDuplicate(struct KernelChannelGroupApi *pResource, NvHandle hMemory, NvBool *pDuplicate) { + return resIsDuplicate((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_KernelChannelGroupApi_RsResource.offset), hMemory, pDuplicate); +} + +static void __nvoc_thunk_RmResource_kchangrpapiControlSerialization_Epilogue(struct KernelChannelGroupApi *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + rmresControlSerialization_Epilogue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_KernelChannelGroupApi_RmResource.offset), pCallContext, pParams); +} + static NV_STATUS __nvoc_thunk_GpuResource_kchangrpapiMap(struct KernelChannelGroupApi *pGpuResource, struct CALL_CONTEXT *pCallContext, struct RS_CPU_MAP_PARAMS *pParams, struct RsCpuMapping *pCpuMapping) { return gpuresMap((struct GpuResource *)(((unsigned char *)pGpuResource) + __nvoc_rtti_KernelChannelGroupApi_GpuResource.offset), pCallContext, pParams, pCpuMapping); } @@ -549,25 +557,15 @@ pThis->__kchangrpapiShareCallback__ = &__nvoc_thunk_GpuResource_kchangrpapiShareCallback; - pThis->__kchangrpapiUnmap__ = &__nvoc_thunk_GpuResource_kchangrpapiUnmap; - - pThis->__kchangrpapiGetMemInterMapParams__ = &__nvoc_thunk_RmResource_kchangrpapiGetMemInterMapParams; + pThis->__kchangrpapiCheckMemInterUnmap__ = &__nvoc_thunk_RmResource_kchangrpapiCheckMemInterUnmap; - pThis->__kchangrpapiGetMemoryMappingDescriptor__ = &__nvoc_thunk_RmResource_kchangrpapiGetMemoryMappingDescriptor; + pThis->__kchangrpapiMapTo__ = &__nvoc_thunk_RsResource_kchangrpapiMapTo; pThis->__kchangrpapiGetMapAddrSpace__ = &__nvoc_thunk_GpuResource_kchangrpapiGetMapAddrSpace; - pThis->__kchangrpapiGetInternalObjectHandle__ = &__nvoc_thunk_GpuResource_kchangrpapiGetInternalObjectHandle; - - pThis->__kchangrpapiControlFilter__ = &__nvoc_thunk_RsResource_kchangrpapiControlFilter; - - pThis->__kchangrpapiAddAdditionalDependants__ = &__nvoc_thunk_RsResource_kchangrpapiAddAdditionalDependants; - pThis->__kchangrpapiGetRefCount__ = &__nvoc_thunk_RsResource_kchangrpapiGetRefCount; - pThis->__kchangrpapiCheckMemInterUnmap__ = &__nvoc_thunk_RmResource_kchangrpapiCheckMemInterUnmap; - - pThis->__kchangrpapiMapTo__ = &__nvoc_thunk_RsResource_kchangrpapiMapTo; + pThis->__kchangrpapiAddAdditionalDependants__ = &__nvoc_thunk_RsResource_kchangrpapiAddAdditionalDependants; pThis->__kchangrpapiControl_Prologue__ = &__nvoc_thunk_RmResource_kchangrpapiControl_Prologue; @@ -575,16 +573,30 @@ pThis->__kchangrpapiInternalControlForward__ = &__nvoc_thunk_GpuResource_kchangrpapiInternalControlForward; - pThis->__kchangrpapiPreDestruct__ = &__nvoc_thunk_RsResource_kchangrpapiPreDestruct; - pThis->__kchangrpapiUnmapFrom__ = &__nvoc_thunk_RsResource_kchangrpapiUnmapFrom; - pThis->__kchangrpapiIsDuplicate__ = &__nvoc_thunk_RsResource_kchangrpapiIsDuplicate; - pThis->__kchangrpapiControl_Epilogue__ = &__nvoc_thunk_RmResource_kchangrpapiControl_Epilogue; pThis->__kchangrpapiControlLookup__ = &__nvoc_thunk_RsResource_kchangrpapiControlLookup; + pThis->__kchangrpapiGetInternalObjectHandle__ = &__nvoc_thunk_GpuResource_kchangrpapiGetInternalObjectHandle; + + pThis->__kchangrpapiUnmap__ = &__nvoc_thunk_GpuResource_kchangrpapiUnmap; + + pThis->__kchangrpapiGetMemInterMapParams__ = &__nvoc_thunk_RmResource_kchangrpapiGetMemInterMapParams; + + pThis->__kchangrpapiGetMemoryMappingDescriptor__ = &__nvoc_thunk_RmResource_kchangrpapiGetMemoryMappingDescriptor; + + pThis->__kchangrpapiControlFilter__ = &__nvoc_thunk_RsResource_kchangrpapiControlFilter; + + pThis->__kchangrpapiControlSerialization_Prologue__ = &__nvoc_thunk_RmResource_kchangrpapiControlSerialization_Prologue; + + pThis->__kchangrpapiPreDestruct__ = &__nvoc_thunk_RsResource_kchangrpapiPreDestruct; + + pThis->__kchangrpapiIsDuplicate__ = &__nvoc_thunk_RsResource_kchangrpapiIsDuplicate; + + pThis->__kchangrpapiControlSerialization_Epilogue__ = &__nvoc_thunk_RmResource_kchangrpapiControlSerialization_Epilogue; + pThis->__kchangrpapiMap__ = &__nvoc_thunk_GpuResource_kchangrpapiMap; pThis->__kchangrpapiAccessCallback__ = &__nvoc_thunk_RmResource_kchangrpapiAccessCallback; @@ -611,13 +623,16 @@ Object *pParentObj; KernelChannelGroupApi *pThis; - pThis = portMemAllocNonPaged(sizeof(KernelChannelGroupApi)); - if (pThis == NULL) return NV_ERR_NO_MEMORY; + status = __nvoc_handleObjCreateMemAlloc(createFlags, sizeof(KernelChannelGroupApi), (void**)&pThis, (void**)ppThis); + if (status != NV_OK) + return status; portMemSet(pThis, 0, sizeof(KernelChannelGroupApi)); __nvoc_initRtti(staticCast(pThis, Dynamic), &__nvoc_class_def_KernelChannelGroupApi); + pThis->__nvoc_base_GpuResource.__nvoc_base_RmResource.__nvoc_base_RsResource.__nvoc_base_Object.createFlags = createFlags; + if (pParent != NULL && !(createFlags & NVOC_OBJ_CREATE_FLAGS_PARENT_HALSPEC_ONLY)) { pParentObj = dynamicCast(pParent, Object); @@ -633,11 +648,17 @@ if (status != NV_OK) goto __nvoc_objCreate_KernelChannelGroupApi_cleanup; *ppThis = pThis; + return NV_OK; __nvoc_objCreate_KernelChannelGroupApi_cleanup: // do not call destructors here since the constructor already called them - portMemFree(pThis); + if (createFlags & NVOC_OBJ_CREATE_FLAGS_IN_PLACE_CONSTRUCT) + portMemSet(pThis, 0, sizeof(KernelChannelGroupApi)); + else + portMemFree(pThis); + + // coverity[leaked_storage:FALSE] return status; } diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/generated/g_kernel_channel_group_api_nvoc.h nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_kernel_channel_group_api_nvoc.h --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/generated/g_kernel_channel_group_api_nvoc.h 2023-10-25 20:27:06.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_kernel_channel_group_api_nvoc.h 2024-03-05 22:18:25.000000000 +0000 @@ -103,24 +103,26 @@ NV_STATUS (*__kchangrpapiCtrlGetMMUDebugMode__)(struct KernelChannelGroupApi *, NV0090_CTRL_GET_MMU_DEBUG_MODE_PARAMS *); NV_STATUS (*__kchangrpapiCtrlProgramVidmemPromote__)(struct KernelChannelGroupApi *, NV0090_CTRL_PROGRAM_VIDMEM_PROMOTE_PARAMS *); NvBool (*__kchangrpapiShareCallback__)(struct KernelChannelGroupApi *, struct RsClient *, struct RsResourceRef *, RS_SHARE_POLICY *); - NV_STATUS (*__kchangrpapiUnmap__)(struct KernelChannelGroupApi *, struct CALL_CONTEXT *, struct RsCpuMapping *); - NV_STATUS (*__kchangrpapiGetMemInterMapParams__)(struct KernelChannelGroupApi *, RMRES_MEM_INTER_MAP_PARAMS *); - NV_STATUS (*__kchangrpapiGetMemoryMappingDescriptor__)(struct KernelChannelGroupApi *, struct MEMORY_DESCRIPTOR **); - NV_STATUS (*__kchangrpapiGetMapAddrSpace__)(struct KernelChannelGroupApi *, struct CALL_CONTEXT *, NvU32, NV_ADDRESS_SPACE *); - NvHandle (*__kchangrpapiGetInternalObjectHandle__)(struct KernelChannelGroupApi *); - NV_STATUS (*__kchangrpapiControlFilter__)(struct KernelChannelGroupApi *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); - void (*__kchangrpapiAddAdditionalDependants__)(struct RsClient *, struct KernelChannelGroupApi *, RsResourceRef *); - NvU32 (*__kchangrpapiGetRefCount__)(struct KernelChannelGroupApi *); NV_STATUS (*__kchangrpapiCheckMemInterUnmap__)(struct KernelChannelGroupApi *, NvBool); NV_STATUS (*__kchangrpapiMapTo__)(struct KernelChannelGroupApi *, RS_RES_MAP_TO_PARAMS *); + NV_STATUS (*__kchangrpapiGetMapAddrSpace__)(struct KernelChannelGroupApi *, struct CALL_CONTEXT *, NvU32, NV_ADDRESS_SPACE *); + NvU32 (*__kchangrpapiGetRefCount__)(struct KernelChannelGroupApi *); + void (*__kchangrpapiAddAdditionalDependants__)(struct RsClient *, struct KernelChannelGroupApi *, RsResourceRef *); NV_STATUS (*__kchangrpapiControl_Prologue__)(struct KernelChannelGroupApi *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); NV_STATUS (*__kchangrpapiGetRegBaseOffsetAndSize__)(struct KernelChannelGroupApi *, struct OBJGPU *, NvU32 *, NvU32 *); NV_STATUS (*__kchangrpapiInternalControlForward__)(struct KernelChannelGroupApi *, NvU32, void *, NvU32); - void (*__kchangrpapiPreDestruct__)(struct KernelChannelGroupApi *); NV_STATUS (*__kchangrpapiUnmapFrom__)(struct KernelChannelGroupApi *, RS_RES_UNMAP_FROM_PARAMS *); - NV_STATUS (*__kchangrpapiIsDuplicate__)(struct KernelChannelGroupApi *, NvHandle, NvBool *); void (*__kchangrpapiControl_Epilogue__)(struct KernelChannelGroupApi *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); NV_STATUS (*__kchangrpapiControlLookup__)(struct KernelChannelGroupApi *, struct RS_RES_CONTROL_PARAMS_INTERNAL *, const struct NVOC_EXPORTED_METHOD_DEF **); + NvHandle (*__kchangrpapiGetInternalObjectHandle__)(struct KernelChannelGroupApi *); + NV_STATUS (*__kchangrpapiUnmap__)(struct KernelChannelGroupApi *, struct CALL_CONTEXT *, struct RsCpuMapping *); + NV_STATUS (*__kchangrpapiGetMemInterMapParams__)(struct KernelChannelGroupApi *, RMRES_MEM_INTER_MAP_PARAMS *); + NV_STATUS (*__kchangrpapiGetMemoryMappingDescriptor__)(struct KernelChannelGroupApi *, struct MEMORY_DESCRIPTOR **); + NV_STATUS (*__kchangrpapiControlFilter__)(struct KernelChannelGroupApi *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); + NV_STATUS (*__kchangrpapiControlSerialization_Prologue__)(struct KernelChannelGroupApi *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); + void (*__kchangrpapiPreDestruct__)(struct KernelChannelGroupApi *); + NV_STATUS (*__kchangrpapiIsDuplicate__)(struct KernelChannelGroupApi *, NvHandle, NvBool *); + void (*__kchangrpapiControlSerialization_Epilogue__)(struct KernelChannelGroupApi *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); NV_STATUS (*__kchangrpapiMap__)(struct KernelChannelGroupApi *, struct CALL_CONTEXT *, struct RS_CPU_MAP_PARAMS *, struct RsCpuMapping *); NvBool (*__kchangrpapiAccessCallback__)(struct KernelChannelGroupApi *, struct RsClient *, void *, RsAccessRight); struct KernelChannelGroup *pKernelChannelGroup; @@ -180,24 +182,26 @@ #define kchangrpapiCtrlGetMMUDebugMode(pKernelChannelGroupApi, pParams) kchangrpapiCtrlGetMMUDebugMode_DISPATCH(pKernelChannelGroupApi, pParams) #define kchangrpapiCtrlProgramVidmemPromote(pKernelChannelGroupApi, pParams) kchangrpapiCtrlProgramVidmemPromote_DISPATCH(pKernelChannelGroupApi, pParams) #define kchangrpapiShareCallback(pGpuResource, pInvokingClient, pParentRef, pSharePolicy) kchangrpapiShareCallback_DISPATCH(pGpuResource, pInvokingClient, pParentRef, pSharePolicy) -#define kchangrpapiUnmap(pGpuResource, pCallContext, pCpuMapping) kchangrpapiUnmap_DISPATCH(pGpuResource, pCallContext, pCpuMapping) -#define kchangrpapiGetMemInterMapParams(pRmResource, pParams) kchangrpapiGetMemInterMapParams_DISPATCH(pRmResource, pParams) -#define kchangrpapiGetMemoryMappingDescriptor(pRmResource, ppMemDesc) kchangrpapiGetMemoryMappingDescriptor_DISPATCH(pRmResource, ppMemDesc) -#define kchangrpapiGetMapAddrSpace(pGpuResource, pCallContext, mapFlags, pAddrSpace) kchangrpapiGetMapAddrSpace_DISPATCH(pGpuResource, pCallContext, mapFlags, pAddrSpace) -#define kchangrpapiGetInternalObjectHandle(pGpuResource) kchangrpapiGetInternalObjectHandle_DISPATCH(pGpuResource) -#define kchangrpapiControlFilter(pResource, pCallContext, pParams) kchangrpapiControlFilter_DISPATCH(pResource, pCallContext, pParams) -#define kchangrpapiAddAdditionalDependants(pClient, pResource, pReference) kchangrpapiAddAdditionalDependants_DISPATCH(pClient, pResource, pReference) -#define kchangrpapiGetRefCount(pResource) kchangrpapiGetRefCount_DISPATCH(pResource) #define kchangrpapiCheckMemInterUnmap(pRmResource, bSubdeviceHandleProvided) kchangrpapiCheckMemInterUnmap_DISPATCH(pRmResource, bSubdeviceHandleProvided) #define kchangrpapiMapTo(pResource, pParams) kchangrpapiMapTo_DISPATCH(pResource, pParams) +#define kchangrpapiGetMapAddrSpace(pGpuResource, pCallContext, mapFlags, pAddrSpace) kchangrpapiGetMapAddrSpace_DISPATCH(pGpuResource, pCallContext, mapFlags, pAddrSpace) +#define kchangrpapiGetRefCount(pResource) kchangrpapiGetRefCount_DISPATCH(pResource) +#define kchangrpapiAddAdditionalDependants(pClient, pResource, pReference) kchangrpapiAddAdditionalDependants_DISPATCH(pClient, pResource, pReference) #define kchangrpapiControl_Prologue(pResource, pCallContext, pParams) kchangrpapiControl_Prologue_DISPATCH(pResource, pCallContext, pParams) #define kchangrpapiGetRegBaseOffsetAndSize(pGpuResource, pGpu, pOffset, pSize) kchangrpapiGetRegBaseOffsetAndSize_DISPATCH(pGpuResource, pGpu, pOffset, pSize) #define kchangrpapiInternalControlForward(pGpuResource, command, pParams, size) kchangrpapiInternalControlForward_DISPATCH(pGpuResource, command, pParams, size) -#define kchangrpapiPreDestruct(pResource) kchangrpapiPreDestruct_DISPATCH(pResource) #define kchangrpapiUnmapFrom(pResource, pParams) kchangrpapiUnmapFrom_DISPATCH(pResource, pParams) -#define kchangrpapiIsDuplicate(pResource, hMemory, pDuplicate) kchangrpapiIsDuplicate_DISPATCH(pResource, hMemory, pDuplicate) #define kchangrpapiControl_Epilogue(pResource, pCallContext, pParams) kchangrpapiControl_Epilogue_DISPATCH(pResource, pCallContext, pParams) #define kchangrpapiControlLookup(pResource, pParams, ppEntry) kchangrpapiControlLookup_DISPATCH(pResource, pParams, ppEntry) +#define kchangrpapiGetInternalObjectHandle(pGpuResource) kchangrpapiGetInternalObjectHandle_DISPATCH(pGpuResource) +#define kchangrpapiUnmap(pGpuResource, pCallContext, pCpuMapping) kchangrpapiUnmap_DISPATCH(pGpuResource, pCallContext, pCpuMapping) +#define kchangrpapiGetMemInterMapParams(pRmResource, pParams) kchangrpapiGetMemInterMapParams_DISPATCH(pRmResource, pParams) +#define kchangrpapiGetMemoryMappingDescriptor(pRmResource, ppMemDesc) kchangrpapiGetMemoryMappingDescriptor_DISPATCH(pRmResource, ppMemDesc) +#define kchangrpapiControlFilter(pResource, pCallContext, pParams) kchangrpapiControlFilter_DISPATCH(pResource, pCallContext, pParams) +#define kchangrpapiControlSerialization_Prologue(pResource, pCallContext, pParams) kchangrpapiControlSerialization_Prologue_DISPATCH(pResource, pCallContext, pParams) +#define kchangrpapiPreDestruct(pResource) kchangrpapiPreDestruct_DISPATCH(pResource) +#define kchangrpapiIsDuplicate(pResource, hMemory, pDuplicate) kchangrpapiIsDuplicate_DISPATCH(pResource, hMemory, pDuplicate) +#define kchangrpapiControlSerialization_Epilogue(pResource, pCallContext, pParams) kchangrpapiControlSerialization_Epilogue_DISPATCH(pResource, pCallContext, pParams) #define kchangrpapiMap(pGpuResource, pCallContext, pParams, pCpuMapping) kchangrpapiMap_DISPATCH(pGpuResource, pCallContext, pParams, pCpuMapping) #define kchangrpapiAccessCallback(pResource, pInvokingClient, pAllocParams, accessRight) kchangrpapiAccessCallback_DISPATCH(pResource, pInvokingClient, pAllocParams, accessRight) NvBool kchangrpapiCanCopy_IMPL(struct KernelChannelGroupApi *pKernelChannelGroupApi); @@ -326,44 +330,24 @@ return pGpuResource->__kchangrpapiShareCallback__(pGpuResource, pInvokingClient, pParentRef, pSharePolicy); } -static inline NV_STATUS kchangrpapiUnmap_DISPATCH(struct KernelChannelGroupApi *pGpuResource, struct CALL_CONTEXT *pCallContext, struct RsCpuMapping *pCpuMapping) { - return pGpuResource->__kchangrpapiUnmap__(pGpuResource, pCallContext, pCpuMapping); -} - -static inline NV_STATUS kchangrpapiGetMemInterMapParams_DISPATCH(struct KernelChannelGroupApi *pRmResource, RMRES_MEM_INTER_MAP_PARAMS *pParams) { - return pRmResource->__kchangrpapiGetMemInterMapParams__(pRmResource, pParams); +static inline NV_STATUS kchangrpapiCheckMemInterUnmap_DISPATCH(struct KernelChannelGroupApi *pRmResource, NvBool bSubdeviceHandleProvided) { + return pRmResource->__kchangrpapiCheckMemInterUnmap__(pRmResource, bSubdeviceHandleProvided); } -static inline NV_STATUS kchangrpapiGetMemoryMappingDescriptor_DISPATCH(struct KernelChannelGroupApi *pRmResource, struct MEMORY_DESCRIPTOR **ppMemDesc) { - return pRmResource->__kchangrpapiGetMemoryMappingDescriptor__(pRmResource, ppMemDesc); +static inline NV_STATUS kchangrpapiMapTo_DISPATCH(struct KernelChannelGroupApi *pResource, RS_RES_MAP_TO_PARAMS *pParams) { + return pResource->__kchangrpapiMapTo__(pResource, pParams); } static inline NV_STATUS kchangrpapiGetMapAddrSpace_DISPATCH(struct KernelChannelGroupApi *pGpuResource, struct CALL_CONTEXT *pCallContext, NvU32 mapFlags, NV_ADDRESS_SPACE *pAddrSpace) { return pGpuResource->__kchangrpapiGetMapAddrSpace__(pGpuResource, pCallContext, mapFlags, pAddrSpace); } -static inline NvHandle kchangrpapiGetInternalObjectHandle_DISPATCH(struct KernelChannelGroupApi *pGpuResource) { - return pGpuResource->__kchangrpapiGetInternalObjectHandle__(pGpuResource); -} - -static inline NV_STATUS kchangrpapiControlFilter_DISPATCH(struct KernelChannelGroupApi *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { - return pResource->__kchangrpapiControlFilter__(pResource, pCallContext, pParams); -} - -static inline void kchangrpapiAddAdditionalDependants_DISPATCH(struct RsClient *pClient, struct KernelChannelGroupApi *pResource, RsResourceRef *pReference) { - pResource->__kchangrpapiAddAdditionalDependants__(pClient, pResource, pReference); -} - static inline NvU32 kchangrpapiGetRefCount_DISPATCH(struct KernelChannelGroupApi *pResource) { return pResource->__kchangrpapiGetRefCount__(pResource); } -static inline NV_STATUS kchangrpapiCheckMemInterUnmap_DISPATCH(struct KernelChannelGroupApi *pRmResource, NvBool bSubdeviceHandleProvided) { - return pRmResource->__kchangrpapiCheckMemInterUnmap__(pRmResource, bSubdeviceHandleProvided); -} - -static inline NV_STATUS kchangrpapiMapTo_DISPATCH(struct KernelChannelGroupApi *pResource, RS_RES_MAP_TO_PARAMS *pParams) { - return pResource->__kchangrpapiMapTo__(pResource, pParams); +static inline void kchangrpapiAddAdditionalDependants_DISPATCH(struct RsClient *pClient, struct KernelChannelGroupApi *pResource, RsResourceRef *pReference) { + pResource->__kchangrpapiAddAdditionalDependants__(pClient, pResource, pReference); } static inline NV_STATUS kchangrpapiControl_Prologue_DISPATCH(struct KernelChannelGroupApi *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { @@ -378,18 +362,10 @@ return pGpuResource->__kchangrpapiInternalControlForward__(pGpuResource, command, pParams, size); } -static inline void kchangrpapiPreDestruct_DISPATCH(struct KernelChannelGroupApi *pResource) { - pResource->__kchangrpapiPreDestruct__(pResource); -} - static inline NV_STATUS kchangrpapiUnmapFrom_DISPATCH(struct KernelChannelGroupApi *pResource, RS_RES_UNMAP_FROM_PARAMS *pParams) { return pResource->__kchangrpapiUnmapFrom__(pResource, pParams); } -static inline NV_STATUS kchangrpapiIsDuplicate_DISPATCH(struct KernelChannelGroupApi *pResource, NvHandle hMemory, NvBool *pDuplicate) { - return pResource->__kchangrpapiIsDuplicate__(pResource, hMemory, pDuplicate); -} - static inline void kchangrpapiControl_Epilogue_DISPATCH(struct KernelChannelGroupApi *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { pResource->__kchangrpapiControl_Epilogue__(pResource, pCallContext, pParams); } @@ -398,6 +374,42 @@ return pResource->__kchangrpapiControlLookup__(pResource, pParams, ppEntry); } +static inline NvHandle kchangrpapiGetInternalObjectHandle_DISPATCH(struct KernelChannelGroupApi *pGpuResource) { + return pGpuResource->__kchangrpapiGetInternalObjectHandle__(pGpuResource); +} + +static inline NV_STATUS kchangrpapiUnmap_DISPATCH(struct KernelChannelGroupApi *pGpuResource, struct CALL_CONTEXT *pCallContext, struct RsCpuMapping *pCpuMapping) { + return pGpuResource->__kchangrpapiUnmap__(pGpuResource, pCallContext, pCpuMapping); +} + +static inline NV_STATUS kchangrpapiGetMemInterMapParams_DISPATCH(struct KernelChannelGroupApi *pRmResource, RMRES_MEM_INTER_MAP_PARAMS *pParams) { + return pRmResource->__kchangrpapiGetMemInterMapParams__(pRmResource, pParams); +} + +static inline NV_STATUS kchangrpapiGetMemoryMappingDescriptor_DISPATCH(struct KernelChannelGroupApi *pRmResource, struct MEMORY_DESCRIPTOR **ppMemDesc) { + return pRmResource->__kchangrpapiGetMemoryMappingDescriptor__(pRmResource, ppMemDesc); +} + +static inline NV_STATUS kchangrpapiControlFilter_DISPATCH(struct KernelChannelGroupApi *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return pResource->__kchangrpapiControlFilter__(pResource, pCallContext, pParams); +} + +static inline NV_STATUS kchangrpapiControlSerialization_Prologue_DISPATCH(struct KernelChannelGroupApi *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return pResource->__kchangrpapiControlSerialization_Prologue__(pResource, pCallContext, pParams); +} + +static inline void kchangrpapiPreDestruct_DISPATCH(struct KernelChannelGroupApi *pResource) { + pResource->__kchangrpapiPreDestruct__(pResource); +} + +static inline NV_STATUS kchangrpapiIsDuplicate_DISPATCH(struct KernelChannelGroupApi *pResource, NvHandle hMemory, NvBool *pDuplicate) { + return pResource->__kchangrpapiIsDuplicate__(pResource, hMemory, pDuplicate); +} + +static inline void kchangrpapiControlSerialization_Epilogue_DISPATCH(struct KernelChannelGroupApi *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + pResource->__kchangrpapiControlSerialization_Epilogue__(pResource, pCallContext, pParams); +} + static inline NV_STATUS kchangrpapiMap_DISPATCH(struct KernelChannelGroupApi *pGpuResource, struct CALL_CONTEXT *pCallContext, struct RS_CPU_MAP_PARAMS *pParams, struct RsCpuMapping *pCpuMapping) { return pGpuResource->__kchangrpapiMap__(pGpuResource, pCallContext, pParams, pCpuMapping); } diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/generated/g_kernel_channel_group_nvoc.c nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_kernel_channel_group_nvoc.c --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/generated/g_kernel_channel_group_nvoc.c 2023-10-25 20:27:06.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_kernel_channel_group_nvoc.c 2024-03-05 22:18:25.000000000 +0000 @@ -143,13 +143,16 @@ KernelChannelGroup *pThis; RmHalspecOwner *pRmhalspecowner; - pThis = portMemAllocNonPaged(sizeof(KernelChannelGroup)); - if (pThis == NULL) return NV_ERR_NO_MEMORY; + status = __nvoc_handleObjCreateMemAlloc(createFlags, sizeof(KernelChannelGroup), (void**)&pThis, (void**)ppThis); + if (status != NV_OK) + return status; portMemSet(pThis, 0, sizeof(KernelChannelGroup)); __nvoc_initRtti(staticCast(pThis, Dynamic), &__nvoc_class_def_KernelChannelGroup); + pThis->__nvoc_base_RsShared.__nvoc_base_Object.createFlags = createFlags; + if (pParent != NULL && !(createFlags & NVOC_OBJ_CREATE_FLAGS_PARENT_HALSPEC_ONLY)) { pParentObj = dynamicCast(pParent, Object); @@ -169,11 +172,17 @@ if (status != NV_OK) goto __nvoc_objCreate_KernelChannelGroup_cleanup; *ppThis = pThis; + return NV_OK; __nvoc_objCreate_KernelChannelGroup_cleanup: // do not call destructors here since the constructor already called them - portMemFree(pThis); + if (createFlags & NVOC_OBJ_CREATE_FLAGS_IN_PLACE_CONSTRUCT) + portMemSet(pThis, 0, sizeof(KernelChannelGroup)); + else + portMemFree(pThis); + + // coverity[leaked_storage:FALSE] return status; } diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/generated/g_kernel_channel_group_nvoc.h nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_kernel_channel_group_nvoc.h --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/generated/g_kernel_channel_group_nvoc.h 2023-10-25 20:27:06.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_kernel_channel_group_nvoc.h 2024-03-05 22:18:25.000000000 +0000 @@ -192,20 +192,6 @@ #define kchangrpSetInterleaveLevelSched_HAL(pGpu, pKernelChannelGroup, value) kchangrpSetInterleaveLevelSched(pGpu, pKernelChannelGroup, value) -NvU32 kchangrpGetDefaultRunlist_GM107(struct OBJGPU *pGpu, struct KernelChannelGroup *pKernelChannelGroup); - - -#ifdef __nvoc_kernel_channel_group_h_disabled -static inline NvU32 kchangrpGetDefaultRunlist(struct OBJGPU *pGpu, struct KernelChannelGroup *pKernelChannelGroup) { - NV_ASSERT_FAILED_PRECOMP("KernelChannelGroup was disabled!"); - return 0; -} -#else //__nvoc_kernel_channel_group_h_disabled -#define kchangrpGetDefaultRunlist(pGpu, pKernelChannelGroup) kchangrpGetDefaultRunlist_GM107(pGpu, pKernelChannelGroup) -#endif //__nvoc_kernel_channel_group_h_disabled - -#define kchangrpGetDefaultRunlist_HAL(pGpu, pKernelChannelGroup) kchangrpGetDefaultRunlist(pGpu, pKernelChannelGroup) - static inline void kchangrpUpdateSubcontextMask_b3696a(struct OBJGPU *pGpu, struct KernelChannelGroup *arg0, NvU32 arg1, NvBool arg2) { return; } @@ -255,22 +241,6 @@ #define kchangrpGetSubcontextZombieState_HAL(pGpu, arg0, arg1) kchangrpGetSubcontextZombieState(pGpu, arg0, arg1) -static inline NV_STATUS kchangrpFreeGrSubcontextHdrs_56cd7a(struct OBJGPU *pGpu, struct KernelChannelGroup *arg0) { - return NV_OK; -} - - -#ifdef __nvoc_kernel_channel_group_h_disabled -static inline NV_STATUS kchangrpFreeGrSubcontextHdrs(struct OBJGPU *pGpu, struct KernelChannelGroup *arg0) { - NV_ASSERT_FAILED_PRECOMP("KernelChannelGroup was disabled!"); - return NV_ERR_NOT_SUPPORTED; -} -#else //__nvoc_kernel_channel_group_h_disabled -#define kchangrpFreeGrSubcontextHdrs(pGpu, arg0) kchangrpFreeGrSubcontextHdrs_56cd7a(pGpu, arg0) -#endif //__nvoc_kernel_channel_group_h_disabled - -#define kchangrpFreeGrSubcontextHdrs_HAL(pGpu, arg0) kchangrpFreeGrSubcontextHdrs(pGpu, arg0) - NV_STATUS kchangrpAllocFaultMethodBuffers_GV100(struct OBJGPU *pGpu, struct KernelChannelGroup *pKernelChannelGroup); diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/generated/g_kernel_channel_nvoc.c nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_kernel_channel_nvoc.c --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/generated/g_kernel_channel_nvoc.c 2023-10-25 20:27:07.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_kernel_channel_nvoc.c 2024-03-05 22:18:25.000000000 +0000 @@ -135,14 +135,14 @@ return gpuresShareCallback((struct GpuResource *)(((unsigned char *)pGpuResource) + __nvoc_rtti_KernelChannel_GpuResource.offset), pInvokingClient, pParentRef, pSharePolicy); } -static NV_STATUS __nvoc_thunk_RsResource_kchannelMapTo(struct KernelChannel *pResource, RS_RES_MAP_TO_PARAMS *pParams) { - return resMapTo((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_KernelChannel_RsResource.offset), pParams); -} - static NV_STATUS __nvoc_thunk_Notifier_kchannelGetOrAllocNotifShare(struct KernelChannel *pNotifier, NvHandle hNotifierClient, NvHandle hNotifierResource, struct NotifShare **ppNotifShare) { return notifyGetOrAllocNotifShare((struct Notifier *)(((unsigned char *)pNotifier) + __nvoc_rtti_KernelChannel_Notifier.offset), hNotifierClient, hNotifierResource, ppNotifShare); } +static NV_STATUS __nvoc_thunk_RsResource_kchannelMapTo(struct KernelChannel *pResource, RS_RES_MAP_TO_PARAMS *pParams) { + return resMapTo((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_KernelChannel_RsResource.offset), pParams); +} + static void __nvoc_thunk_Notifier_kchannelSetNotificationShare(struct KernelChannel *pNotifier, struct NotifShare *pNotifShare) { notifySetNotificationShare((struct Notifier *)(((unsigned char *)pNotifier) + __nvoc_rtti_KernelChannel_Notifier.offset), pNotifShare); } @@ -199,6 +199,10 @@ return notifyUnregisterEvent((struct Notifier *)(((unsigned char *)pNotifier) + __nvoc_rtti_KernelChannel_Notifier.offset), hNotifierClient, hNotifierResource, hEventClient, hEvent); } +static NV_STATUS __nvoc_thunk_RmResource_kchannelControlSerialization_Prologue(struct KernelChannel *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return rmresControlSerialization_Prologue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_KernelChannel_RmResource.offset), pCallContext, pParams); +} + static NvBool __nvoc_thunk_RsResource_kchannelCanCopy(struct KernelChannel *pResource) { return resCanCopy((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_KernelChannel_RsResource.offset)); } @@ -211,6 +215,10 @@ return resIsDuplicate((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_KernelChannel_RsResource.offset), hMemory, pDuplicate); } +static void __nvoc_thunk_RmResource_kchannelControlSerialization_Epilogue(struct KernelChannel *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + rmresControlSerialization_Epilogue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_KernelChannel_RmResource.offset), pCallContext, pParams); +} + static PEVENTNOTIFICATION *__nvoc_thunk_Notifier_kchannelGetNotificationListPtr(struct KernelChannel *pNotifier) { return notifyGetNotificationListPtr((struct Notifier *)(((unsigned char *)pNotifier) + __nvoc_rtti_KernelChannel_Notifier.offset)); } @@ -949,12 +957,42 @@ /*func=*/ "kchannelCtrlCmdGpfifoSetWorkSubmitTokenNotifIndex" #endif }, + { /* [48] */ +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x2010u) + /*pFunc=*/ (void (*)(void)) NULL, +#else + /*pFunc=*/ (void (*)(void)) kchannelCtrlCmdGetKmb_DISPATCH, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x2010u) + /*flags=*/ 0x2010u, + /*accessRight=*/0x0u, + /*methodId=*/ 0xc56f010bu, + /*paramSize=*/ sizeof(NVC56F_CTRL_CMD_GET_KMB_PARAMS), + /*pClassInfo=*/ &(__nvoc_class_def_KernelChannel.classInfo), +#if NV_PRINTF_STRINGS_ALLOWED + /*func=*/ "kchannelCtrlCmdGetKmb" +#endif + }, + { /* [49] */ +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x2010u) + /*pFunc=*/ (void (*)(void)) NULL, +#else + /*pFunc=*/ (void (*)(void)) kchannelCtrlRotateSecureChannelIv_DISPATCH, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x2010u) + /*flags=*/ 0x2010u, + /*accessRight=*/0x0u, + /*methodId=*/ 0xc56f010cu, + /*paramSize=*/ sizeof(NVC56F_CTRL_ROTATE_SECURE_CHANNEL_IV_PARAMS), + /*pClassInfo=*/ &(__nvoc_class_def_KernelChannel.classInfo), +#if NV_PRINTF_STRINGS_ALLOWED + /*func=*/ "kchannelCtrlRotateSecureChannelIv" +#endif + }, }; const struct NVOC_EXPORT_INFO __nvoc_export_info_KernelChannel = { - /*numEntries=*/ 48, + /*numEntries=*/ 50, /*pExportEntries=*/ __nvoc_exported_method_def_KernelChannel }; @@ -1027,27 +1065,27 @@ pThis->__kchannelCheckMemInterUnmap__ = &kchannelCheckMemInterUnmap_IMPL; // Hal function -- kchannelCreateUserMemDesc - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x01f0ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 */ + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ { - pThis->__kchannelCreateUserMemDesc__ = &kchannelCreateUserMemDesc_GM107; + pThis->__kchannelCreateUserMemDesc__ = &kchannelCreateUserMemDesc_GA10B; } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ + else { - pThis->__kchannelCreateUserMemDesc__ = &kchannelCreateUserMemDesc_GA10B; + pThis->__kchannelCreateUserMemDesc__ = &kchannelCreateUserMemDesc_GM107; } // Hal function -- kchannelIsUserdAddrSizeValid - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x000003e0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 */ + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ { - pThis->__kchannelIsUserdAddrSizeValid__ = &kchannelIsUserdAddrSizeValid_GV100; + pThis->__kchannelIsUserdAddrSizeValid__ = &kchannelIsUserdAddrSizeValid_GH100; } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x01f0fc00UL) )) /* ChipHal: GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 */ + else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x000003e0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 */ { - pThis->__kchannelIsUserdAddrSizeValid__ = &kchannelIsUserdAddrSizeValid_GA100; + pThis->__kchannelIsUserdAddrSizeValid__ = &kchannelIsUserdAddrSizeValid_GV100; } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ + else { - pThis->__kchannelIsUserdAddrSizeValid__ = &kchannelIsUserdAddrSizeValid_GH100; + pThis->__kchannelIsUserdAddrSizeValid__ = &kchannelIsUserdAddrSizeValid_GA100; } #if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x2210u) @@ -1226,6 +1264,12 @@ pThis->__kchannelCtrlCmdStopChannel__ = &kchannelCtrlCmdStopChannel_IMPL; #endif + // Hal function -- kchannelCtrlCmdGetKmb + pThis->__kchannelCtrlCmdGetKmb__ = &kchannelCtrlCmdGetKmb_KERNEL; + + // Hal function -- kchannelCtrlRotateSecureChannelIv + pThis->__kchannelCtrlRotateSecureChannelIv__ = &kchannelCtrlRotateSecureChannelIv_KERNEL; + #if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) pThis->__kchannelCtrlGetTpcPartitionMode__ = &kchannelCtrlGetTpcPartitionMode_a094e1; #endif @@ -1254,10 +1298,10 @@ pThis->__kchannelShareCallback__ = &__nvoc_thunk_GpuResource_kchannelShareCallback; - pThis->__kchannelMapTo__ = &__nvoc_thunk_RsResource_kchannelMapTo; - pThis->__kchannelGetOrAllocNotifShare__ = &__nvoc_thunk_Notifier_kchannelGetOrAllocNotifShare; + pThis->__kchannelMapTo__ = &__nvoc_thunk_RsResource_kchannelMapTo; + pThis->__kchannelSetNotificationShare__ = &__nvoc_thunk_Notifier_kchannelSetNotificationShare; pThis->__kchannelGetRefCount__ = &__nvoc_thunk_RsResource_kchannelGetRefCount; @@ -1286,12 +1330,16 @@ pThis->__kchannelUnregisterEvent__ = &__nvoc_thunk_Notifier_kchannelUnregisterEvent; + pThis->__kchannelControlSerialization_Prologue__ = &__nvoc_thunk_RmResource_kchannelControlSerialization_Prologue; + pThis->__kchannelCanCopy__ = &__nvoc_thunk_RsResource_kchannelCanCopy; pThis->__kchannelPreDestruct__ = &__nvoc_thunk_RsResource_kchannelPreDestruct; pThis->__kchannelIsDuplicate__ = &__nvoc_thunk_RsResource_kchannelIsDuplicate; + pThis->__kchannelControlSerialization_Epilogue__ = &__nvoc_thunk_RmResource_kchannelControlSerialization_Epilogue; + pThis->__kchannelGetNotificationListPtr__ = &__nvoc_thunk_Notifier_kchannelGetNotificationListPtr; pThis->__kchannelGetNotificationShare__ = &__nvoc_thunk_Notifier_kchannelGetNotificationShare; @@ -1325,13 +1373,16 @@ KernelChannel *pThis; RmHalspecOwner *pRmhalspecowner; - pThis = portMemAllocNonPaged(sizeof(KernelChannel)); - if (pThis == NULL) return NV_ERR_NO_MEMORY; + status = __nvoc_handleObjCreateMemAlloc(createFlags, sizeof(KernelChannel), (void**)&pThis, (void**)ppThis); + if (status != NV_OK) + return status; portMemSet(pThis, 0, sizeof(KernelChannel)); __nvoc_initRtti(staticCast(pThis, Dynamic), &__nvoc_class_def_KernelChannel); + pThis->__nvoc_base_GpuResource.__nvoc_base_RmResource.__nvoc_base_RsResource.__nvoc_base_Object.createFlags = createFlags; + if (pParent != NULL && !(createFlags & NVOC_OBJ_CREATE_FLAGS_PARENT_HALSPEC_ONLY)) { pParentObj = dynamicCast(pParent, Object); @@ -1351,11 +1402,17 @@ if (status != NV_OK) goto __nvoc_objCreate_KernelChannel_cleanup; *ppThis = pThis; + return NV_OK; __nvoc_objCreate_KernelChannel_cleanup: // do not call destructors here since the constructor already called them - portMemFree(pThis); + if (createFlags & NVOC_OBJ_CREATE_FLAGS_IN_PLACE_CONSTRUCT) + portMemSet(pThis, 0, sizeof(KernelChannel)); + else + portMemFree(pThis); + + // coverity[leaked_storage:FALSE] return status; } diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/generated/g_kernel_channel_nvoc.h nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_kernel_channel_nvoc.h --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/generated/g_kernel_channel_nvoc.h 2023-10-25 20:27:07.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_kernel_channel_nvoc.h 2024-03-05 22:18:26.000000000 +0000 @@ -7,7 +7,7 @@ #endif /* - * SPDX-FileCopyrightText: Copyright (c) 2020-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2020-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -58,6 +58,8 @@ #include "ctrl/ctrlc36f.h" #include "ctrl/ctrlc56f.h" +#include "cc_drv.h" + struct OBJGPU; #ifndef __NVOC_CLASS_OBJGPU_TYPEDEF__ @@ -257,13 +259,15 @@ NV_STATUS (*__kchannelCtrlCmdGpfifoUpdateFaultMethodBuffer__)(struct KernelChannel *, NVC36F_CTRL_GPFIFO_UPDATE_FAULT_METHOD_BUFFER_PARAMS *); NV_STATUS (*__kchannelCtrlCmdGpfifoSetWorkSubmitTokenNotifIndex__)(struct KernelChannel *, NVC36F_CTRL_GPFIFO_SET_WORK_SUBMIT_TOKEN_NOTIF_INDEX_PARAMS *); NV_STATUS (*__kchannelCtrlCmdStopChannel__)(struct KernelChannel *, NVA06F_CTRL_STOP_CHANNEL_PARAMS *); + NV_STATUS (*__kchannelCtrlCmdGetKmb__)(struct KernelChannel *, NVC56F_CTRL_CMD_GET_KMB_PARAMS *); + NV_STATUS (*__kchannelCtrlRotateSecureChannelIv__)(struct KernelChannel *, NVC56F_CTRL_ROTATE_SECURE_CHANNEL_IV_PARAMS *); NV_STATUS (*__kchannelCtrlGetTpcPartitionMode__)(struct KernelChannel *, NV0090_CTRL_TPC_PARTITION_MODE_PARAMS *); NV_STATUS (*__kchannelCtrlSetTpcPartitionMode__)(struct KernelChannel *, NV0090_CTRL_TPC_PARTITION_MODE_PARAMS *); NV_STATUS (*__kchannelCtrlGetMMUDebugMode__)(struct KernelChannel *, NV0090_CTRL_GET_MMU_DEBUG_MODE_PARAMS *); NV_STATUS (*__kchannelCtrlProgramVidmemPromote__)(struct KernelChannel *, NV0090_CTRL_PROGRAM_VIDMEM_PROMOTE_PARAMS *); NvBool (*__kchannelShareCallback__)(struct KernelChannel *, struct RsClient *, struct RsResourceRef *, RS_SHARE_POLICY *); - NV_STATUS (*__kchannelMapTo__)(struct KernelChannel *, RS_RES_MAP_TO_PARAMS *); NV_STATUS (*__kchannelGetOrAllocNotifShare__)(struct KernelChannel *, NvHandle, NvHandle, struct NotifShare **); + NV_STATUS (*__kchannelMapTo__)(struct KernelChannel *, RS_RES_MAP_TO_PARAMS *); void (*__kchannelSetNotificationShare__)(struct KernelChannel *, struct NotifShare *); NvU32 (*__kchannelGetRefCount__)(struct KernelChannel *); void (*__kchannelAddAdditionalDependants__)(struct RsClient *, struct KernelChannel *, RsResourceRef *); @@ -278,9 +282,11 @@ NV_STATUS (*__kchannelGetMemoryMappingDescriptor__)(struct KernelChannel *, struct MEMORY_DESCRIPTOR **); NV_STATUS (*__kchannelControlFilter__)(struct KernelChannel *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); NV_STATUS (*__kchannelUnregisterEvent__)(struct KernelChannel *, NvHandle, NvHandle, NvHandle, NvHandle); + NV_STATUS (*__kchannelControlSerialization_Prologue__)(struct KernelChannel *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); NvBool (*__kchannelCanCopy__)(struct KernelChannel *); void (*__kchannelPreDestruct__)(struct KernelChannel *); NV_STATUS (*__kchannelIsDuplicate__)(struct KernelChannel *, NvHandle, NvBool *); + void (*__kchannelControlSerialization_Epilogue__)(struct KernelChannel *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); PEVENTNOTIFICATION *(*__kchannelGetNotificationListPtr__)(struct KernelChannel *); struct NotifShare *(*__kchannelGetNotificationShare__)(struct KernelChannel *); NvBool (*__kchannelAccessCallback__)(struct KernelChannel *, struct RsClient *, void *, RsAccessRight); @@ -322,6 +328,8 @@ struct MIG_INSTANCE_REF partitionRef; NvU32 runqueue; RM_ENGINE_TYPE engineType; + CC_KMB clientKmb; + NvBool bCCSecureChannel; }; #ifndef __NVOC_CLASS_KernelChannel_TYPEDEF__ @@ -405,13 +413,17 @@ #define kchannelCtrlCmdGpfifoUpdateFaultMethodBuffer(pKernelChannel, pFaultMthdBufferParams) kchannelCtrlCmdGpfifoUpdateFaultMethodBuffer_DISPATCH(pKernelChannel, pFaultMthdBufferParams) #define kchannelCtrlCmdGpfifoSetWorkSubmitTokenNotifIndex(pKernelChannel, pParams) kchannelCtrlCmdGpfifoSetWorkSubmitTokenNotifIndex_DISPATCH(pKernelChannel, pParams) #define kchannelCtrlCmdStopChannel(pKernelChannel, pStopChannelParams) kchannelCtrlCmdStopChannel_DISPATCH(pKernelChannel, pStopChannelParams) +#define kchannelCtrlCmdGetKmb(pKernelChannel, pGetKmbParams) kchannelCtrlCmdGetKmb_DISPATCH(pKernelChannel, pGetKmbParams) +#define kchannelCtrlCmdGetKmb_HAL(pKernelChannel, pGetKmbParams) kchannelCtrlCmdGetKmb_DISPATCH(pKernelChannel, pGetKmbParams) +#define kchannelCtrlRotateSecureChannelIv(pKernelChannel, pRotateIvParams) kchannelCtrlRotateSecureChannelIv_DISPATCH(pKernelChannel, pRotateIvParams) +#define kchannelCtrlRotateSecureChannelIv_HAL(pKernelChannel, pRotateIvParams) kchannelCtrlRotateSecureChannelIv_DISPATCH(pKernelChannel, pRotateIvParams) #define kchannelCtrlGetTpcPartitionMode(pKernelChannel, pParams) kchannelCtrlGetTpcPartitionMode_DISPATCH(pKernelChannel, pParams) #define kchannelCtrlSetTpcPartitionMode(pKernelChannel, pParams) kchannelCtrlSetTpcPartitionMode_DISPATCH(pKernelChannel, pParams) #define kchannelCtrlGetMMUDebugMode(pKernelChannel, pParams) kchannelCtrlGetMMUDebugMode_DISPATCH(pKernelChannel, pParams) #define kchannelCtrlProgramVidmemPromote(pKernelChannel, pParams) kchannelCtrlProgramVidmemPromote_DISPATCH(pKernelChannel, pParams) #define kchannelShareCallback(pGpuResource, pInvokingClient, pParentRef, pSharePolicy) kchannelShareCallback_DISPATCH(pGpuResource, pInvokingClient, pParentRef, pSharePolicy) -#define kchannelMapTo(pResource, pParams) kchannelMapTo_DISPATCH(pResource, pParams) #define kchannelGetOrAllocNotifShare(pNotifier, hNotifierClient, hNotifierResource, ppNotifShare) kchannelGetOrAllocNotifShare_DISPATCH(pNotifier, hNotifierClient, hNotifierResource, ppNotifShare) +#define kchannelMapTo(pResource, pParams) kchannelMapTo_DISPATCH(pResource, pParams) #define kchannelSetNotificationShare(pNotifier, pNotifShare) kchannelSetNotificationShare_DISPATCH(pNotifier, pNotifShare) #define kchannelGetRefCount(pResource) kchannelGetRefCount_DISPATCH(pResource) #define kchannelAddAdditionalDependants(pClient, pResource, pReference) kchannelAddAdditionalDependants_DISPATCH(pClient, pResource, pReference) @@ -426,9 +438,11 @@ #define kchannelGetMemoryMappingDescriptor(pRmResource, ppMemDesc) kchannelGetMemoryMappingDescriptor_DISPATCH(pRmResource, ppMemDesc) #define kchannelControlFilter(pResource, pCallContext, pParams) kchannelControlFilter_DISPATCH(pResource, pCallContext, pParams) #define kchannelUnregisterEvent(pNotifier, hNotifierClient, hNotifierResource, hEventClient, hEvent) kchannelUnregisterEvent_DISPATCH(pNotifier, hNotifierClient, hNotifierResource, hEventClient, hEvent) +#define kchannelControlSerialization_Prologue(pResource, pCallContext, pParams) kchannelControlSerialization_Prologue_DISPATCH(pResource, pCallContext, pParams) #define kchannelCanCopy(pResource) kchannelCanCopy_DISPATCH(pResource) #define kchannelPreDestruct(pResource) kchannelPreDestruct_DISPATCH(pResource) #define kchannelIsDuplicate(pResource, hMemory, pDuplicate) kchannelIsDuplicate_DISPATCH(pResource, hMemory, pDuplicate) +#define kchannelControlSerialization_Epilogue(pResource, pCallContext, pParams) kchannelControlSerialization_Epilogue_DISPATCH(pResource, pCallContext, pParams) #define kchannelGetNotificationListPtr(pNotifier) kchannelGetNotificationListPtr_DISPATCH(pNotifier) #define kchannelGetNotificationShare(pNotifier) kchannelGetNotificationShare_DISPATCH(pNotifier) #define kchannelAccessCallback(pResource, pInvokingClient, pAllocParams, accessRight) kchannelAccessCallback_DISPATCH(pResource, pInvokingClient, pAllocParams, accessRight) @@ -705,6 +719,36 @@ #define kchannelEnableVirtualContext_HAL(arg0) kchannelEnableVirtualContext(arg0) +static inline NV_STATUS kchannelRotateSecureChannelIv_46f6a7(struct KernelChannel *pKernelChannel, ROTATE_IV_TYPE rotateOperation, NvU32 *encryptIv, NvU32 *decryptIv) { + return NV_ERR_NOT_SUPPORTED; +} + + +#ifdef __nvoc_kernel_channel_h_disabled +static inline NV_STATUS kchannelRotateSecureChannelIv(struct KernelChannel *pKernelChannel, ROTATE_IV_TYPE rotateOperation, NvU32 *encryptIv, NvU32 *decryptIv) { + NV_ASSERT_FAILED_PRECOMP("KernelChannel was disabled!"); + return NV_ERR_NOT_SUPPORTED; +} +#else //__nvoc_kernel_channel_h_disabled +#define kchannelRotateSecureChannelIv(pKernelChannel, rotateOperation, encryptIv, decryptIv) kchannelRotateSecureChannelIv_46f6a7(pKernelChannel, rotateOperation, encryptIv, decryptIv) +#endif //__nvoc_kernel_channel_h_disabled + +#define kchannelRotateSecureChannelIv_HAL(pKernelChannel, rotateOperation, encryptIv, decryptIv) kchannelRotateSecureChannelIv(pKernelChannel, rotateOperation, encryptIv, decryptIv) + +NV_STATUS kchannelRetrieveKmb_KERNEL(struct OBJGPU *pGpu, struct KernelChannel *pKernelChannel, ROTATE_IV_TYPE rotateOperation, NvBool includeSecrets, CC_KMB *keyMaterialBundle); + + +#ifdef __nvoc_kernel_channel_h_disabled +static inline NV_STATUS kchannelRetrieveKmb(struct OBJGPU *pGpu, struct KernelChannel *pKernelChannel, ROTATE_IV_TYPE rotateOperation, NvBool includeSecrets, CC_KMB *keyMaterialBundle) { + NV_ASSERT_FAILED_PRECOMP("KernelChannel was disabled!"); + return NV_ERR_NOT_SUPPORTED; +} +#else //__nvoc_kernel_channel_h_disabled +#define kchannelRetrieveKmb(pGpu, pKernelChannel, rotateOperation, includeSecrets, keyMaterialBundle) kchannelRetrieveKmb_KERNEL(pGpu, pKernelChannel, rotateOperation, includeSecrets, keyMaterialBundle) +#endif //__nvoc_kernel_channel_h_disabled + +#define kchannelRetrieveKmb_HAL(pGpu, pKernelChannel, rotateOperation, includeSecrets, keyMaterialBundle) kchannelRetrieveKmb(pGpu, pKernelChannel, rotateOperation, includeSecrets, keyMaterialBundle) + NV_STATUS kchannelMap_IMPL(struct KernelChannel *pKernelChannel, CALL_CONTEXT *pCallContext, struct RS_CPU_MAP_PARAMS *pParams, RsCpuMapping *pCpuMapping); static inline NV_STATUS kchannelMap_DISPATCH(struct KernelChannel *pKernelChannel, CALL_CONTEXT *pCallContext, struct RS_CPU_MAP_PARAMS *pParams, RsCpuMapping *pCpuMapping) { @@ -1059,6 +1103,18 @@ return pKernelChannel->__kchannelCtrlCmdStopChannel__(pKernelChannel, pStopChannelParams); } +NV_STATUS kchannelCtrlCmdGetKmb_KERNEL(struct KernelChannel *pKernelChannel, NVC56F_CTRL_CMD_GET_KMB_PARAMS *pGetKmbParams); + +static inline NV_STATUS kchannelCtrlCmdGetKmb_DISPATCH(struct KernelChannel *pKernelChannel, NVC56F_CTRL_CMD_GET_KMB_PARAMS *pGetKmbParams) { + return pKernelChannel->__kchannelCtrlCmdGetKmb__(pKernelChannel, pGetKmbParams); +} + +NV_STATUS kchannelCtrlRotateSecureChannelIv_KERNEL(struct KernelChannel *pKernelChannel, NVC56F_CTRL_ROTATE_SECURE_CHANNEL_IV_PARAMS *pRotateIvParams); + +static inline NV_STATUS kchannelCtrlRotateSecureChannelIv_DISPATCH(struct KernelChannel *pKernelChannel, NVC56F_CTRL_ROTATE_SECURE_CHANNEL_IV_PARAMS *pRotateIvParams) { + return pKernelChannel->__kchannelCtrlRotateSecureChannelIv__(pKernelChannel, pRotateIvParams); +} + static inline NV_STATUS kchannelCtrlGetTpcPartitionMode_a094e1(struct KernelChannel *pKernelChannel, NV0090_CTRL_TPC_PARTITION_MODE_PARAMS *pParams) { return kgrctxCtrlHandle(resservGetTlsCallContext(), pKernelChannel->hKernelGraphicsContext); } @@ -1095,14 +1151,14 @@ return pGpuResource->__kchannelShareCallback__(pGpuResource, pInvokingClient, pParentRef, pSharePolicy); } -static inline NV_STATUS kchannelMapTo_DISPATCH(struct KernelChannel *pResource, RS_RES_MAP_TO_PARAMS *pParams) { - return pResource->__kchannelMapTo__(pResource, pParams); -} - static inline NV_STATUS kchannelGetOrAllocNotifShare_DISPATCH(struct KernelChannel *pNotifier, NvHandle hNotifierClient, NvHandle hNotifierResource, struct NotifShare **ppNotifShare) { return pNotifier->__kchannelGetOrAllocNotifShare__(pNotifier, hNotifierClient, hNotifierResource, ppNotifShare); } +static inline NV_STATUS kchannelMapTo_DISPATCH(struct KernelChannel *pResource, RS_RES_MAP_TO_PARAMS *pParams) { + return pResource->__kchannelMapTo__(pResource, pParams); +} + static inline void kchannelSetNotificationShare_DISPATCH(struct KernelChannel *pNotifier, struct NotifShare *pNotifShare) { pNotifier->__kchannelSetNotificationShare__(pNotifier, pNotifShare); } @@ -1159,6 +1215,10 @@ return pNotifier->__kchannelUnregisterEvent__(pNotifier, hNotifierClient, hNotifierResource, hEventClient, hEvent); } +static inline NV_STATUS kchannelControlSerialization_Prologue_DISPATCH(struct KernelChannel *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return pResource->__kchannelControlSerialization_Prologue__(pResource, pCallContext, pParams); +} + static inline NvBool kchannelCanCopy_DISPATCH(struct KernelChannel *pResource) { return pResource->__kchannelCanCopy__(pResource); } @@ -1171,6 +1231,10 @@ return pResource->__kchannelIsDuplicate__(pResource, hMemory, pDuplicate); } +static inline void kchannelControlSerialization_Epilogue_DISPATCH(struct KernelChannel *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + pResource->__kchannelControlSerialization_Epilogue__(pResource, pCallContext, pParams); +} + static inline PEVENTNOTIFICATION *kchannelGetNotificationListPtr_DISPATCH(struct KernelChannel *pNotifier) { return pNotifier->__kchannelGetNotificationListPtr__(pNotifier); } @@ -1259,6 +1323,17 @@ #define kchannelNotifyGeneric(pKernelChannel, notifyIndex, pNotifyParams, notifyParamsSize) kchannelNotifyGeneric_IMPL(pKernelChannel, notifyIndex, pNotifyParams, notifyParamsSize) #endif //__nvoc_kernel_channel_h_disabled +NvBool kchannelCheckIsUserMode_IMPL(struct KernelChannel *pKernelChannel); + +#ifdef __nvoc_kernel_channel_h_disabled +static inline NvBool kchannelCheckIsUserMode(struct KernelChannel *pKernelChannel) { + NV_ASSERT_FAILED_PRECOMP("KernelChannel was disabled!"); + return NV_FALSE; +} +#else //__nvoc_kernel_channel_h_disabled +#define kchannelCheckIsUserMode(pKernelChannel) kchannelCheckIsUserMode_IMPL(pKernelChannel) +#endif //__nvoc_kernel_channel_h_disabled + NvBool kchannelCheckIsKernel_IMPL(struct KernelChannel *pKernelChannel); #ifdef __nvoc_kernel_channel_h_disabled @@ -1379,10 +1454,10 @@ #define kchannelUnmapUserD(pGpu, arg0, arg1, arg2, arg3) kchannelUnmapUserD_IMPL(pGpu, arg0, arg1, arg2, arg3) #endif //__nvoc_kernel_channel_h_disabled -NV_STATUS kchannelGetFromDualHandle_IMPL(NvHandle arg0, NvHandle arg1, struct KernelChannel **arg2); +NV_STATUS kchannelGetFromDualHandle_IMPL(struct RsClient *arg0, NvHandle arg1, struct KernelChannel **arg2); #define kchannelGetFromDualHandle(arg0, arg1, arg2) kchannelGetFromDualHandle_IMPL(arg0, arg1, arg2) -NV_STATUS kchannelGetFromDualHandleRestricted_IMPL(NvHandle arg0, NvHandle arg1, struct KernelChannel **arg2); +NV_STATUS kchannelGetFromDualHandleRestricted_IMPL(struct RsClient *arg0, NvHandle arg1, struct KernelChannel **arg2); #define kchannelGetFromDualHandleRestricted(arg0, arg1, arg2) kchannelGetFromDualHandleRestricted_IMPL(arg0, arg1, arg2) NvU32 kchannelGetGfid_IMPL(struct KernelChannel *pKernelChannel); @@ -1398,6 +1473,19 @@ #undef PRIVATE_FIELD +#ifndef NVOC_KERNEL_CHANNEL_H_PRIVATE_ACCESS_ALLOWED +#ifndef __nvoc_kernel_channel_h_disabled +#undef kchannelRotateSecureChannelIv +NV_STATUS NVOC_PRIVATE_FUNCTION(kchannelRotateSecureChannelIv)(struct KernelChannel *pKernelChannel, ROTATE_IV_TYPE rotateOperation, NvU32 *encryptIv, NvU32 *decryptIv); +#endif //__nvoc_kernel_channel_h_disabled + +#ifndef __nvoc_kernel_channel_h_disabled +#undef kchannelRetrieveKmb +NV_STATUS NVOC_PRIVATE_FUNCTION(kchannelRetrieveKmb)(struct OBJGPU *pGpu, struct KernelChannel *pKernelChannel, ROTATE_IV_TYPE rotateOperation, NvBool includeSecrets, CC_KMB *keyMaterialBundle); +#endif //__nvoc_kernel_channel_h_disabled + +#endif // NVOC_KERNEL_CHANNEL_H_PRIVATE_ACCESS_ALLOWED + RS_ORDERED_ITERATOR kchannelGetIter( struct RsClient *pClient, @@ -1408,13 +1496,13 @@ CHANNEL_ITERATOR *pIt, struct KernelChannel **ppKernelChannel); -NV_STATUS CliGetKernelChannelWithDevice(NvHandle hClient, - NvHandle hParent, - NvHandle hKernelChannel, +NV_STATUS CliGetKernelChannelWithDevice(struct RsClient *pClient, + NvHandle hParent, + NvHandle hKernelChannel, struct KernelChannel **ppKernelChannel); -NV_STATUS CliGetKernelChannel(NvHandle hClient, - NvHandle hKernelChannel, +NV_STATUS CliGetKernelChannel(struct RsClient *pClient, + NvHandle hKernelChannel, struct KernelChannel **ppKernelChannel); /*! diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/generated/g_kernel_crashcat_engine_nvoc.c nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_kernel_crashcat_engine_nvoc.c --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/generated/g_kernel_crashcat_engine_nvoc.c 1970-01-01 00:00:00.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_kernel_crashcat_engine_nvoc.c 2024-03-05 22:18:26.000000000 +0000 @@ -0,0 +1,213 @@ +#define NVOC_KERNEL_CRASHCAT_ENGINE_H_PRIVATE_ACCESS_ALLOWED +#include "nvoc/runtime.h" +#include "nvoc/rtti.h" +#include "nvtypes.h" +#include "nvport/nvport.h" +#include "nvport/inline/util_valist.h" +#include "utils/nvassert.h" +#include "g_kernel_crashcat_engine_nvoc.h" + +#ifdef DEBUG +char __nvoc_class_id_uniqueness_check_0xc37aef = 1; +#endif + +extern const struct NVOC_CLASS_DEF __nvoc_class_def_KernelCrashCatEngine; + +extern const struct NVOC_CLASS_DEF __nvoc_class_def_CrashCatEngine; + +void __nvoc_init_KernelCrashCatEngine(KernelCrashCatEngine*, RmHalspecOwner* ); +void __nvoc_init_funcTable_KernelCrashCatEngine(KernelCrashCatEngine*, RmHalspecOwner* ); +NV_STATUS __nvoc_ctor_KernelCrashCatEngine(KernelCrashCatEngine*, RmHalspecOwner* ); +void __nvoc_init_dataField_KernelCrashCatEngine(KernelCrashCatEngine*, RmHalspecOwner* ); +void __nvoc_dtor_KernelCrashCatEngine(KernelCrashCatEngine*); +extern const struct NVOC_EXPORT_INFO __nvoc_export_info_KernelCrashCatEngine; + +static const struct NVOC_RTTI __nvoc_rtti_KernelCrashCatEngine_KernelCrashCatEngine = { + /*pClassDef=*/ &__nvoc_class_def_KernelCrashCatEngine, + /*dtor=*/ (NVOC_DYNAMIC_DTOR) &__nvoc_dtor_KernelCrashCatEngine, + /*offset=*/ 0, +}; + +static const struct NVOC_RTTI __nvoc_rtti_KernelCrashCatEngine_CrashCatEngine = { + /*pClassDef=*/ &__nvoc_class_def_CrashCatEngine, + /*dtor=*/ &__nvoc_destructFromBase, + /*offset=*/ NV_OFFSETOF(KernelCrashCatEngine, __nvoc_base_CrashCatEngine), +}; + +static const struct NVOC_CASTINFO __nvoc_castinfo_KernelCrashCatEngine = { + /*numRelatives=*/ 2, + /*relatives=*/ { + &__nvoc_rtti_KernelCrashCatEngine_KernelCrashCatEngine, + &__nvoc_rtti_KernelCrashCatEngine_CrashCatEngine, + }, +}; + +// Not instantiable because it's not derived from class "Object" +// Not instantiable because it's an abstract class with following pure virtual functions: +// kcrashcatEngineRegRead +// kcrashcatEngineRegWrite +// kcrashcatEngineMaskDmemAddr +const struct NVOC_CLASS_DEF __nvoc_class_def_KernelCrashCatEngine = +{ + /*classInfo=*/ { + /*size=*/ sizeof(KernelCrashCatEngine), + /*classId=*/ classId(KernelCrashCatEngine), + /*providerId=*/ &__nvoc_rtti_provider, +#if NV_PRINTF_STRINGS_ALLOWED + /*name=*/ "KernelCrashCatEngine", +#endif + }, + /*objCreatefn=*/ (NVOC_DYNAMIC_OBJ_CREATE) NULL, + /*pCastInfo=*/ &__nvoc_castinfo_KernelCrashCatEngine, + /*pExportInfo=*/ &__nvoc_export_info_KernelCrashCatEngine +}; + +static NvBool __nvoc_thunk_KernelCrashCatEngine_crashcatEngineConfigured(struct CrashCatEngine *arg0) { + return kcrashcatEngineConfigured((struct KernelCrashCatEngine *)(((unsigned char *)arg0) - __nvoc_rtti_KernelCrashCatEngine_CrashCatEngine.offset)); +} + +static void __nvoc_thunk_KernelCrashCatEngine_crashcatEngineUnload(struct CrashCatEngine *arg0) { + kcrashcatEngineUnload((struct KernelCrashCatEngine *)(((unsigned char *)arg0) - __nvoc_rtti_KernelCrashCatEngine_CrashCatEngine.offset)); +} + +static void __nvoc_thunk_KernelCrashCatEngine_crashcatEngineVprintf(struct CrashCatEngine *arg0, NvBool bReportStart, const char *fmt, va_list args) { + kcrashcatEngineVprintf((struct KernelCrashCatEngine *)(((unsigned char *)arg0) - __nvoc_rtti_KernelCrashCatEngine_CrashCatEngine.offset), bReportStart, fmt, args); +} + +static NvU32 __nvoc_thunk_KernelCrashCatEngine_crashcatEnginePriRead(struct CrashCatEngine *arg0, NvU32 offset) { + return kcrashcatEnginePriRead((struct KernelCrashCatEngine *)(((unsigned char *)arg0) - __nvoc_rtti_KernelCrashCatEngine_CrashCatEngine.offset), offset); +} + +static void __nvoc_thunk_KernelCrashCatEngine_crashcatEnginePriWrite(struct CrashCatEngine *arg0, NvU32 offset, NvU32 data) { + kcrashcatEnginePriWrite((struct KernelCrashCatEngine *)(((unsigned char *)arg0) - __nvoc_rtti_KernelCrashCatEngine_CrashCatEngine.offset), offset, data); +} + +static void *__nvoc_thunk_KernelCrashCatEngine_crashcatEngineMapBufferDescriptor(struct CrashCatEngine *arg0, CrashCatBufferDescriptor *pBufDesc) { + return kcrashcatEngineMapBufferDescriptor((struct KernelCrashCatEngine *)(((unsigned char *)arg0) - __nvoc_rtti_KernelCrashCatEngine_CrashCatEngine.offset), pBufDesc); +} + +static void __nvoc_thunk_KernelCrashCatEngine_crashcatEngineUnmapBufferDescriptor(struct CrashCatEngine *arg0, CrashCatBufferDescriptor *pBufDesc) { + kcrashcatEngineUnmapBufferDescriptor((struct KernelCrashCatEngine *)(((unsigned char *)arg0) - __nvoc_rtti_KernelCrashCatEngine_CrashCatEngine.offset), pBufDesc); +} + +static void __nvoc_thunk_KernelCrashCatEngine_crashcatEngineSyncBufferDescriptor(struct CrashCatEngine *arg0, CrashCatBufferDescriptor *pBufDesc, NvU32 offset, NvU32 size) { + kcrashcatEngineSyncBufferDescriptor((struct KernelCrashCatEngine *)(((unsigned char *)arg0) - __nvoc_rtti_KernelCrashCatEngine_CrashCatEngine.offset), pBufDesc, offset, size); +} + +static const NvU32 *__nvoc_thunk_KernelCrashCatEngine_crashcatEngineGetScratchOffsets(struct CrashCatEngine *arg0, NV_CRASHCAT_SCRATCH_GROUP_ID scratchGroupId) { + return kcrashcatEngineGetScratchOffsets((struct KernelCrashCatEngine *)(((unsigned char *)arg0) - __nvoc_rtti_KernelCrashCatEngine_CrashCatEngine.offset), scratchGroupId); +} + +static NvU32 __nvoc_thunk_KernelCrashCatEngine_crashcatEngineGetWFL0Offset(struct CrashCatEngine *arg0) { + return kcrashcatEngineGetWFL0Offset((struct KernelCrashCatEngine *)(((unsigned char *)arg0) - __nvoc_rtti_KernelCrashCatEngine_CrashCatEngine.offset)); +} + +const struct NVOC_EXPORT_INFO __nvoc_export_info_KernelCrashCatEngine = +{ + /*numEntries=*/ 0, + /*pExportEntries=*/ 0 +}; + +void __nvoc_dtor_CrashCatEngine(CrashCatEngine*); +void __nvoc_dtor_KernelCrashCatEngine(KernelCrashCatEngine *pThis) { + __nvoc_dtor_CrashCatEngine(&pThis->__nvoc_base_CrashCatEngine); + PORT_UNREFERENCED_VARIABLE(pThis); +} + +void __nvoc_init_dataField_KernelCrashCatEngine(KernelCrashCatEngine *pThis, RmHalspecOwner *pRmhalspecowner) { + ChipHal *chipHal = &pRmhalspecowner->chipHal; + const unsigned long chipHal_HalVarIdx = (unsigned long)chipHal->__nvoc_HalVarIdx; + PORT_UNREFERENCED_VARIABLE(pThis); + PORT_UNREFERENCED_VARIABLE(pRmhalspecowner); + PORT_UNREFERENCED_VARIABLE(chipHal); + PORT_UNREFERENCED_VARIABLE(chipHal_HalVarIdx); +} + +NV_STATUS __nvoc_ctor_CrashCatEngine(CrashCatEngine* ); +NV_STATUS __nvoc_ctor_KernelCrashCatEngine(KernelCrashCatEngine *pThis, RmHalspecOwner *pRmhalspecowner) { + NV_STATUS status = NV_OK; + status = __nvoc_ctor_CrashCatEngine(&pThis->__nvoc_base_CrashCatEngine); + if (status != NV_OK) goto __nvoc_ctor_KernelCrashCatEngine_fail_CrashCatEngine; + __nvoc_init_dataField_KernelCrashCatEngine(pThis, pRmhalspecowner); + goto __nvoc_ctor_KernelCrashCatEngine_exit; // Success + +__nvoc_ctor_KernelCrashCatEngine_fail_CrashCatEngine: +__nvoc_ctor_KernelCrashCatEngine_exit: + + return status; +} + +static void __nvoc_init_funcTable_KernelCrashCatEngine_1(KernelCrashCatEngine *pThis, RmHalspecOwner *pRmhalspecowner) { + ChipHal *chipHal = &pRmhalspecowner->chipHal; + const unsigned long chipHal_HalVarIdx = (unsigned long)chipHal->__nvoc_HalVarIdx; + PORT_UNREFERENCED_VARIABLE(pThis); + PORT_UNREFERENCED_VARIABLE(pRmhalspecowner); + PORT_UNREFERENCED_VARIABLE(chipHal); + PORT_UNREFERENCED_VARIABLE(chipHal_HalVarIdx); + + pThis->__kcrashcatEngineConfigured__ = &kcrashcatEngineConfigured_IMPL; + + pThis->__kcrashcatEngineUnload__ = &kcrashcatEngineUnload_IMPL; + + pThis->__kcrashcatEngineVprintf__ = &kcrashcatEngineVprintf_IMPL; + + pThis->__kcrashcatEngineRegRead__ = NULL; + + pThis->__kcrashcatEngineRegWrite__ = NULL; + + pThis->__kcrashcatEngineMaskDmemAddr__ = NULL; + + pThis->__kcrashcatEnginePriRead__ = &kcrashcatEnginePriRead_IMPL; + + pThis->__kcrashcatEnginePriWrite__ = &kcrashcatEnginePriWrite_IMPL; + + pThis->__kcrashcatEngineMapBufferDescriptor__ = &kcrashcatEngineMapBufferDescriptor_IMPL; + + pThis->__kcrashcatEngineUnmapBufferDescriptor__ = &kcrashcatEngineUnmapBufferDescriptor_IMPL; + + pThis->__kcrashcatEngineSyncBufferDescriptor__ = &kcrashcatEngineSyncBufferDescriptor_IMPL; + + // Hal function -- kcrashcatEngineReadDmem + pThis->__kcrashcatEngineReadDmem__ = &kcrashcatEngineReadDmem_TU102; + + pThis->__kcrashcatEngineReadEmem__ = &kcrashcatEngineReadEmem_2fced3; + + // Hal function -- kcrashcatEngineGetScratchOffsets + pThis->__kcrashcatEngineGetScratchOffsets__ = &kcrashcatEngineGetScratchOffsets_TU102; + + // Hal function -- kcrashcatEngineGetWFL0Offset + pThis->__kcrashcatEngineGetWFL0Offset__ = &kcrashcatEngineGetWFL0Offset_TU102; + + pThis->__nvoc_base_CrashCatEngine.__crashcatEngineConfigured__ = &__nvoc_thunk_KernelCrashCatEngine_crashcatEngineConfigured; + + pThis->__nvoc_base_CrashCatEngine.__crashcatEngineUnload__ = &__nvoc_thunk_KernelCrashCatEngine_crashcatEngineUnload; + + pThis->__nvoc_base_CrashCatEngine.__crashcatEngineVprintf__ = &__nvoc_thunk_KernelCrashCatEngine_crashcatEngineVprintf; + + pThis->__nvoc_base_CrashCatEngine.__crashcatEnginePriRead__ = &__nvoc_thunk_KernelCrashCatEngine_crashcatEnginePriRead; + + pThis->__nvoc_base_CrashCatEngine.__crashcatEnginePriWrite__ = &__nvoc_thunk_KernelCrashCatEngine_crashcatEnginePriWrite; + + pThis->__nvoc_base_CrashCatEngine.__crashcatEngineMapBufferDescriptor__ = &__nvoc_thunk_KernelCrashCatEngine_crashcatEngineMapBufferDescriptor; + + pThis->__nvoc_base_CrashCatEngine.__crashcatEngineUnmapBufferDescriptor__ = &__nvoc_thunk_KernelCrashCatEngine_crashcatEngineUnmapBufferDescriptor; + + pThis->__nvoc_base_CrashCatEngine.__crashcatEngineSyncBufferDescriptor__ = &__nvoc_thunk_KernelCrashCatEngine_crashcatEngineSyncBufferDescriptor; + + pThis->__nvoc_base_CrashCatEngine.__crashcatEngineGetScratchOffsets__ = &__nvoc_thunk_KernelCrashCatEngine_crashcatEngineGetScratchOffsets; + + pThis->__nvoc_base_CrashCatEngine.__crashcatEngineGetWFL0Offset__ = &__nvoc_thunk_KernelCrashCatEngine_crashcatEngineGetWFL0Offset; +} + +void __nvoc_init_funcTable_KernelCrashCatEngine(KernelCrashCatEngine *pThis, RmHalspecOwner *pRmhalspecowner) { + __nvoc_init_funcTable_KernelCrashCatEngine_1(pThis, pRmhalspecowner); +} + +void __nvoc_init_CrashCatEngine(CrashCatEngine*); +void __nvoc_init_KernelCrashCatEngine(KernelCrashCatEngine *pThis, RmHalspecOwner *pRmhalspecowner) { + pThis->__nvoc_pbase_KernelCrashCatEngine = pThis; + pThis->__nvoc_pbase_CrashCatEngine = &pThis->__nvoc_base_CrashCatEngine; + __nvoc_init_CrashCatEngine(&pThis->__nvoc_base_CrashCatEngine); + __nvoc_init_funcTable_KernelCrashCatEngine(pThis, pRmhalspecowner); +} + diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/generated/g_kernel_crashcat_engine_nvoc.h nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_kernel_crashcat_engine_nvoc.h --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/generated/g_kernel_crashcat_engine_nvoc.h 1970-01-01 00:00:00.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_kernel_crashcat_engine_nvoc.h 2024-03-05 22:18:26.000000000 +0000 @@ -0,0 +1,274 @@ +#ifndef _G_KERNEL_CRASHCAT_ENGINE_NVOC_H_ +#define _G_KERNEL_CRASHCAT_ENGINE_NVOC_H_ +#include "nvoc/runtime.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/* + * SPDX-FileCopyrightText: Copyright (c) 2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#include "g_kernel_crashcat_engine_nvoc.h" + +#ifndef KERNEL_CRASHCAT_ENGINE_H +#define KERNEL_CRASHCAT_ENGINE_H + +#include "containers/map.h" +#include "core/core.h" +#include "crashcat/crashcat_engine.h" +#include "gpu/gpu_halspec.h" +#include "gpu/mem_mgr/mem_desc.h" + +typedef struct KernelCrashCatEngineConfig +{ + const char *pName; // Engine name passed to nvErrorLog_va() for crash reports + NvU32 allocQueueSize; // Size of the system memory buffer to allocate for the CrashCat queue + NvU32 errorId; // Error ID passed to nvErrorLog_va() for crash reports + NvU8 dmemPort; // DMEM port allocated for CrashCat usage + NvBool bEnable; // Enable CrashCat monitoring for the engine +} KernelCrashCatEngineConfig; + +/*! + * Base implementation of CrashCatEngine in RM. + */ +#ifdef NVOC_KERNEL_CRASHCAT_ENGINE_H_PRIVATE_ACCESS_ALLOWED +#define PRIVATE_FIELD(x) x +#else +#define PRIVATE_FIELD(x) NVOC_PRIVATE_FIELD(x) +#endif +struct KernelCrashCatEngine { + const struct NVOC_RTTI *__nvoc_rtti; + struct CrashCatEngine __nvoc_base_CrashCatEngine; + struct CrashCatEngine *__nvoc_pbase_CrashCatEngine; + struct KernelCrashCatEngine *__nvoc_pbase_KernelCrashCatEngine; + NvBool (*__kcrashcatEngineConfigured__)(struct KernelCrashCatEngine *); + void (*__kcrashcatEngineUnload__)(struct KernelCrashCatEngine *); + void (*__kcrashcatEngineVprintf__)(struct KernelCrashCatEngine *, NvBool, const char *, va_list); + NvU32 (*__kcrashcatEngineRegRead__)(struct OBJGPU *, struct KernelCrashCatEngine *, NvU32); + void (*__kcrashcatEngineRegWrite__)(struct OBJGPU *, struct KernelCrashCatEngine *, NvU32, NvU32); + NvU32 (*__kcrashcatEngineMaskDmemAddr__)(struct OBJGPU *, struct KernelCrashCatEngine *, NvU32); + NvU32 (*__kcrashcatEnginePriRead__)(struct KernelCrashCatEngine *, NvU32); + void (*__kcrashcatEnginePriWrite__)(struct KernelCrashCatEngine *, NvU32, NvU32); + void *(*__kcrashcatEngineMapBufferDescriptor__)(struct KernelCrashCatEngine *, CrashCatBufferDescriptor *); + void (*__kcrashcatEngineUnmapBufferDescriptor__)(struct KernelCrashCatEngine *, CrashCatBufferDescriptor *); + void (*__kcrashcatEngineSyncBufferDescriptor__)(struct KernelCrashCatEngine *, CrashCatBufferDescriptor *, NvU32, NvU32); + void (*__kcrashcatEngineReadDmem__)(struct KernelCrashCatEngine *, NvU32, NvU32, void *); + void (*__kcrashcatEngineReadEmem__)(struct KernelCrashCatEngine *, NvU64, NvU64, void *); + const NvU32 *(*__kcrashcatEngineGetScratchOffsets__)(struct KernelCrashCatEngine *, NV_CRASHCAT_SCRATCH_GROUP_ID); + NvU32 (*__kcrashcatEngineGetWFL0Offset__)(struct KernelCrashCatEngine *); + NvBool PRIVATE_FIELD(bConfigured); + MEMORY_DESCRIPTOR *PRIVATE_FIELD(pQueueMemDesc); + const char *PRIVATE_FIELD(pName); + NvU32 PRIVATE_FIELD(errorId); + struct OBJGPU *PRIVATE_FIELD(pGpu); + NvU32 PRIVATE_FIELD(dmemPort); + char PRIVATE_FIELD(printBuffer)[512]; + char PRIVATE_FIELD(fmtBuffer)[512]; +}; + +#ifndef __NVOC_CLASS_KernelCrashCatEngine_TYPEDEF__ +#define __NVOC_CLASS_KernelCrashCatEngine_TYPEDEF__ +typedef struct KernelCrashCatEngine KernelCrashCatEngine; +#endif /* __NVOC_CLASS_KernelCrashCatEngine_TYPEDEF__ */ + +#ifndef __nvoc_class_id_KernelCrashCatEngine +#define __nvoc_class_id_KernelCrashCatEngine 0xc37aef +#endif /* __nvoc_class_id_KernelCrashCatEngine */ + +extern const struct NVOC_CLASS_DEF __nvoc_class_def_KernelCrashCatEngine; + +#define __staticCast_KernelCrashCatEngine(pThis) \ + ((pThis)->__nvoc_pbase_KernelCrashCatEngine) + +#ifdef __nvoc_kernel_crashcat_engine_h_disabled +#define __dynamicCast_KernelCrashCatEngine(pThis) ((KernelCrashCatEngine*)NULL) +#else //__nvoc_kernel_crashcat_engine_h_disabled +#define __dynamicCast_KernelCrashCatEngine(pThis) \ + ((KernelCrashCatEngine*)__nvoc_dynamicCast(staticCast((pThis), Dynamic), classInfo(KernelCrashCatEngine))) +#endif //__nvoc_kernel_crashcat_engine_h_disabled + + +NV_STATUS __nvoc_objCreateDynamic_KernelCrashCatEngine(KernelCrashCatEngine**, Dynamic*, NvU32, va_list); + +NV_STATUS __nvoc_objCreate_KernelCrashCatEngine(KernelCrashCatEngine**, Dynamic*, NvU32); +#define __objCreate_KernelCrashCatEngine(ppNewObj, pParent, createFlags) \ + __nvoc_objCreate_KernelCrashCatEngine((ppNewObj), staticCast((pParent), Dynamic), (createFlags)) + +#define kcrashcatEngineConfigured(arg0) kcrashcatEngineConfigured_DISPATCH(arg0) +#define kcrashcatEngineUnload(arg0) kcrashcatEngineUnload_DISPATCH(arg0) +#define kcrashcatEngineVprintf(arg0, bReportStart, fmt, args) kcrashcatEngineVprintf_DISPATCH(arg0, bReportStart, fmt, args) +#define kcrashcatEngineRegRead(pGpu, arg0, offset) kcrashcatEngineRegRead_DISPATCH(pGpu, arg0, offset) +#define kcrashcatEngineRegWrite(pGpu, arg0, offset, data) kcrashcatEngineRegWrite_DISPATCH(pGpu, arg0, offset, data) +#define kcrashcatEngineMaskDmemAddr(pGpu, arg0, addr) kcrashcatEngineMaskDmemAddr_DISPATCH(pGpu, arg0, addr) +#define kcrashcatEnginePriRead(arg0, offset) kcrashcatEnginePriRead_DISPATCH(arg0, offset) +#define kcrashcatEnginePriWrite(arg0, offset, data) kcrashcatEnginePriWrite_DISPATCH(arg0, offset, data) +#define kcrashcatEngineMapBufferDescriptor(arg0, pBufDesc) kcrashcatEngineMapBufferDescriptor_DISPATCH(arg0, pBufDesc) +#define kcrashcatEngineUnmapBufferDescriptor(arg0, pBufDesc) kcrashcatEngineUnmapBufferDescriptor_DISPATCH(arg0, pBufDesc) +#define kcrashcatEngineSyncBufferDescriptor(arg0, pBufDesc, offset, size) kcrashcatEngineSyncBufferDescriptor_DISPATCH(arg0, pBufDesc, offset, size) +#define kcrashcatEngineReadDmem(arg0, offset, size, pBuf) kcrashcatEngineReadDmem_DISPATCH(arg0, offset, size, pBuf) +#define kcrashcatEngineReadDmem_HAL(arg0, offset, size, pBuf) kcrashcatEngineReadDmem_DISPATCH(arg0, offset, size, pBuf) +#define kcrashcatEngineReadEmem(arg0, offset, size, pBuf) kcrashcatEngineReadEmem_DISPATCH(arg0, offset, size, pBuf) +#define kcrashcatEngineReadEmem_HAL(arg0, offset, size, pBuf) kcrashcatEngineReadEmem_DISPATCH(arg0, offset, size, pBuf) +#define kcrashcatEngineGetScratchOffsets(arg0, scratchGroupId) kcrashcatEngineGetScratchOffsets_DISPATCH(arg0, scratchGroupId) +#define kcrashcatEngineGetScratchOffsets_HAL(arg0, scratchGroupId) kcrashcatEngineGetScratchOffsets_DISPATCH(arg0, scratchGroupId) +#define kcrashcatEngineGetWFL0Offset(arg0) kcrashcatEngineGetWFL0Offset_DISPATCH(arg0) +#define kcrashcatEngineGetWFL0Offset_HAL(arg0) kcrashcatEngineGetWFL0Offset_DISPATCH(arg0) +NvBool kcrashcatEngineConfigured_IMPL(struct KernelCrashCatEngine *arg0); + +static inline NvBool kcrashcatEngineConfigured_DISPATCH(struct KernelCrashCatEngine *arg0) { + return arg0->__kcrashcatEngineConfigured__(arg0); +} + +void kcrashcatEngineUnload_IMPL(struct KernelCrashCatEngine *arg0); + +static inline void kcrashcatEngineUnload_DISPATCH(struct KernelCrashCatEngine *arg0) { + arg0->__kcrashcatEngineUnload__(arg0); +} + +void kcrashcatEngineVprintf_IMPL(struct KernelCrashCatEngine *arg0, NvBool bReportStart, const char *fmt, va_list args); + +static inline void kcrashcatEngineVprintf_DISPATCH(struct KernelCrashCatEngine *arg0, NvBool bReportStart, const char *fmt, va_list args) { + arg0->__kcrashcatEngineVprintf__(arg0, bReportStart, fmt, args); +} + +static inline NvU32 kcrashcatEngineRegRead_DISPATCH(struct OBJGPU *pGpu, struct KernelCrashCatEngine *arg0, NvU32 offset) { + return arg0->__kcrashcatEngineRegRead__(pGpu, arg0, offset); +} + +static inline void kcrashcatEngineRegWrite_DISPATCH(struct OBJGPU *pGpu, struct KernelCrashCatEngine *arg0, NvU32 offset, NvU32 data) { + arg0->__kcrashcatEngineRegWrite__(pGpu, arg0, offset, data); +} + +static inline NvU32 kcrashcatEngineMaskDmemAddr_DISPATCH(struct OBJGPU *pGpu, struct KernelCrashCatEngine *arg0, NvU32 addr) { + return arg0->__kcrashcatEngineMaskDmemAddr__(pGpu, arg0, addr); +} + +NvU32 kcrashcatEnginePriRead_IMPL(struct KernelCrashCatEngine *arg0, NvU32 offset); + +static inline NvU32 kcrashcatEnginePriRead_DISPATCH(struct KernelCrashCatEngine *arg0, NvU32 offset) { + return arg0->__kcrashcatEnginePriRead__(arg0, offset); +} + +void kcrashcatEnginePriWrite_IMPL(struct KernelCrashCatEngine *arg0, NvU32 offset, NvU32 data); + +static inline void kcrashcatEnginePriWrite_DISPATCH(struct KernelCrashCatEngine *arg0, NvU32 offset, NvU32 data) { + arg0->__kcrashcatEnginePriWrite__(arg0, offset, data); +} + +void *kcrashcatEngineMapBufferDescriptor_IMPL(struct KernelCrashCatEngine *arg0, CrashCatBufferDescriptor *pBufDesc); + +static inline void *kcrashcatEngineMapBufferDescriptor_DISPATCH(struct KernelCrashCatEngine *arg0, CrashCatBufferDescriptor *pBufDesc) { + return arg0->__kcrashcatEngineMapBufferDescriptor__(arg0, pBufDesc); +} + +void kcrashcatEngineUnmapBufferDescriptor_IMPL(struct KernelCrashCatEngine *arg0, CrashCatBufferDescriptor *pBufDesc); + +static inline void kcrashcatEngineUnmapBufferDescriptor_DISPATCH(struct KernelCrashCatEngine *arg0, CrashCatBufferDescriptor *pBufDesc) { + arg0->__kcrashcatEngineUnmapBufferDescriptor__(arg0, pBufDesc); +} + +void kcrashcatEngineSyncBufferDescriptor_IMPL(struct KernelCrashCatEngine *arg0, CrashCatBufferDescriptor *pBufDesc, NvU32 offset, NvU32 size); + +static inline void kcrashcatEngineSyncBufferDescriptor_DISPATCH(struct KernelCrashCatEngine *arg0, CrashCatBufferDescriptor *pBufDesc, NvU32 offset, NvU32 size) { + arg0->__kcrashcatEngineSyncBufferDescriptor__(arg0, pBufDesc, offset, size); +} + +void kcrashcatEngineReadDmem_TU102(struct KernelCrashCatEngine *arg0, NvU32 offset, NvU32 size, void *pBuf); + +static inline void kcrashcatEngineReadDmem_DISPATCH(struct KernelCrashCatEngine *arg0, NvU32 offset, NvU32 size, void *pBuf) { + arg0->__kcrashcatEngineReadDmem__(arg0, offset, size, pBuf); +} + +static inline void kcrashcatEngineReadEmem_2fced3(struct KernelCrashCatEngine *arg0, NvU64 offset, NvU64 size, void *pBuf) { + NV_ASSERT_PRECOMP(0); +} + +static inline void kcrashcatEngineReadEmem_DISPATCH(struct KernelCrashCatEngine *arg0, NvU64 offset, NvU64 size, void *pBuf) { + arg0->__kcrashcatEngineReadEmem__(arg0, offset, size, pBuf); +} + +const NvU32 *kcrashcatEngineGetScratchOffsets_TU102(struct KernelCrashCatEngine *arg0, NV_CRASHCAT_SCRATCH_GROUP_ID scratchGroupId); + +static inline const NvU32 *kcrashcatEngineGetScratchOffsets_DISPATCH(struct KernelCrashCatEngine *arg0, NV_CRASHCAT_SCRATCH_GROUP_ID scratchGroupId) { + return arg0->__kcrashcatEngineGetScratchOffsets__(arg0, scratchGroupId); +} + +NvU32 kcrashcatEngineGetWFL0Offset_TU102(struct KernelCrashCatEngine *arg0); + +static inline NvU32 kcrashcatEngineGetWFL0Offset_DISPATCH(struct KernelCrashCatEngine *arg0) { + return arg0->__kcrashcatEngineGetWFL0Offset__(arg0); +} + +NV_STATUS kcrashcatEngineConfigure_IMPL(struct KernelCrashCatEngine *arg0, KernelCrashCatEngineConfig *pEngConfig); + +#ifdef __nvoc_kernel_crashcat_engine_h_disabled +static inline NV_STATUS kcrashcatEngineConfigure(struct KernelCrashCatEngine *arg0, KernelCrashCatEngineConfig *pEngConfig) { + NV_ASSERT_FAILED_PRECOMP("KernelCrashCatEngine was disabled!"); + return NV_ERR_NOT_SUPPORTED; +} +#else //__nvoc_kernel_crashcat_engine_h_disabled +#define kcrashcatEngineConfigure(arg0, pEngConfig) kcrashcatEngineConfigure_IMPL(arg0, pEngConfig) +#endif //__nvoc_kernel_crashcat_engine_h_disabled + +MEMORY_DESCRIPTOR *kcrashcatEngineGetQueueMemDesc_IMPL(struct KernelCrashCatEngine *arg0); + +#ifdef __nvoc_kernel_crashcat_engine_h_disabled +static inline MEMORY_DESCRIPTOR *kcrashcatEngineGetQueueMemDesc(struct KernelCrashCatEngine *arg0) { + NV_ASSERT_FAILED_PRECOMP("KernelCrashCatEngine was disabled!"); + return NULL; +} +#else //__nvoc_kernel_crashcat_engine_h_disabled +#define kcrashcatEngineGetQueueMemDesc(arg0) kcrashcatEngineGetQueueMemDesc_IMPL(arg0) +#endif //__nvoc_kernel_crashcat_engine_h_disabled + +NV_STATUS kcrashcatEngineRegisterCrashBuffer_IMPL(struct KernelCrashCatEngine *arg0, MEMORY_DESCRIPTOR *arg1); + +#ifdef __nvoc_kernel_crashcat_engine_h_disabled +static inline NV_STATUS kcrashcatEngineRegisterCrashBuffer(struct KernelCrashCatEngine *arg0, MEMORY_DESCRIPTOR *arg1) { + NV_ASSERT_FAILED_PRECOMP("KernelCrashCatEngine was disabled!"); + return NV_ERR_NOT_SUPPORTED; +} +#else //__nvoc_kernel_crashcat_engine_h_disabled +#define kcrashcatEngineRegisterCrashBuffer(arg0, arg1) kcrashcatEngineRegisterCrashBuffer_IMPL(arg0, arg1) +#endif //__nvoc_kernel_crashcat_engine_h_disabled + +void kcrashcatEngineUnregisterCrashBuffer_IMPL(struct KernelCrashCatEngine *arg0, MEMORY_DESCRIPTOR *arg1); + +#ifdef __nvoc_kernel_crashcat_engine_h_disabled +static inline void kcrashcatEngineUnregisterCrashBuffer(struct KernelCrashCatEngine *arg0, MEMORY_DESCRIPTOR *arg1) { + NV_ASSERT_FAILED_PRECOMP("KernelCrashCatEngine was disabled!"); +} +#else //__nvoc_kernel_crashcat_engine_h_disabled +#define kcrashcatEngineUnregisterCrashBuffer(arg0, arg1) kcrashcatEngineUnregisterCrashBuffer_IMPL(arg0, arg1) +#endif //__nvoc_kernel_crashcat_engine_h_disabled + +#undef PRIVATE_FIELD + + +#endif // KERNEL_CRASHCAT_ENGINE_H + +#ifdef __cplusplus +} // extern "C" +#endif +#endif // _G_KERNEL_CRASHCAT_ENGINE_NVOC_H_ diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/generated/g_kernel_ctxshare_nvoc.c nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_kernel_ctxshare_nvoc.c --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/generated/g_kernel_ctxshare_nvoc.c 2023-10-25 20:27:07.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_kernel_ctxshare_nvoc.c 2024-03-05 22:18:26.000000000 +0000 @@ -135,13 +135,16 @@ KernelCtxShare *pThis; RmHalspecOwner *pRmhalspecowner; - pThis = portMemAllocNonPaged(sizeof(KernelCtxShare)); - if (pThis == NULL) return NV_ERR_NO_MEMORY; + status = __nvoc_handleObjCreateMemAlloc(createFlags, sizeof(KernelCtxShare), (void**)&pThis, (void**)ppThis); + if (status != NV_OK) + return status; portMemSet(pThis, 0, sizeof(KernelCtxShare)); __nvoc_initRtti(staticCast(pThis, Dynamic), &__nvoc_class_def_KernelCtxShare); + pThis->__nvoc_base_RsShared.__nvoc_base_Object.createFlags = createFlags; + if (pParent != NULL && !(createFlags & NVOC_OBJ_CREATE_FLAGS_PARENT_HALSPEC_ONLY)) { pParentObj = dynamicCast(pParent, Object); @@ -161,11 +164,17 @@ if (status != NV_OK) goto __nvoc_objCreate_KernelCtxShare_cleanup; *ppThis = pThis; + return NV_OK; __nvoc_objCreate_KernelCtxShare_cleanup: // do not call destructors here since the constructor already called them - portMemFree(pThis); + if (createFlags & NVOC_OBJ_CREATE_FLAGS_IN_PLACE_CONSTRUCT) + portMemSet(pThis, 0, sizeof(KernelCtxShare)); + else + portMemFree(pThis); + + // coverity[leaked_storage:FALSE] return status; } @@ -271,48 +280,24 @@ return gpuresShareCallback((struct GpuResource *)(((unsigned char *)pGpuResource) + __nvoc_rtti_KernelCtxShareApi_GpuResource.offset), pInvokingClient, pParentRef, pSharePolicy); } -static NV_STATUS __nvoc_thunk_GpuResource_kctxshareapiControl(struct KernelCtxShareApi *pGpuResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { - return gpuresControl((struct GpuResource *)(((unsigned char *)pGpuResource) + __nvoc_rtti_KernelCtxShareApi_GpuResource.offset), pCallContext, pParams); -} - -static NV_STATUS __nvoc_thunk_GpuResource_kctxshareapiUnmap(struct KernelCtxShareApi *pGpuResource, struct CALL_CONTEXT *pCallContext, struct RsCpuMapping *pCpuMapping) { - return gpuresUnmap((struct GpuResource *)(((unsigned char *)pGpuResource) + __nvoc_rtti_KernelCtxShareApi_GpuResource.offset), pCallContext, pCpuMapping); -} - -static NV_STATUS __nvoc_thunk_RmResource_kctxshareapiGetMemInterMapParams(struct KernelCtxShareApi *pRmResource, RMRES_MEM_INTER_MAP_PARAMS *pParams) { - return rmresGetMemInterMapParams((struct RmResource *)(((unsigned char *)pRmResource) + __nvoc_rtti_KernelCtxShareApi_RmResource.offset), pParams); +static NV_STATUS __nvoc_thunk_RmResource_kctxshareapiCheckMemInterUnmap(struct KernelCtxShareApi *pRmResource, NvBool bSubdeviceHandleProvided) { + return rmresCheckMemInterUnmap((struct RmResource *)(((unsigned char *)pRmResource) + __nvoc_rtti_KernelCtxShareApi_RmResource.offset), bSubdeviceHandleProvided); } -static NV_STATUS __nvoc_thunk_RmResource_kctxshareapiGetMemoryMappingDescriptor(struct KernelCtxShareApi *pRmResource, struct MEMORY_DESCRIPTOR **ppMemDesc) { - return rmresGetMemoryMappingDescriptor((struct RmResource *)(((unsigned char *)pRmResource) + __nvoc_rtti_KernelCtxShareApi_RmResource.offset), ppMemDesc); +static NV_STATUS __nvoc_thunk_RsResource_kctxshareapiMapTo(struct KernelCtxShareApi *pResource, RS_RES_MAP_TO_PARAMS *pParams) { + return resMapTo((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_KernelCtxShareApi_RsResource.offset), pParams); } static NV_STATUS __nvoc_thunk_GpuResource_kctxshareapiGetMapAddrSpace(struct KernelCtxShareApi *pGpuResource, struct CALL_CONTEXT *pCallContext, NvU32 mapFlags, NV_ADDRESS_SPACE *pAddrSpace) { return gpuresGetMapAddrSpace((struct GpuResource *)(((unsigned char *)pGpuResource) + __nvoc_rtti_KernelCtxShareApi_GpuResource.offset), pCallContext, mapFlags, pAddrSpace); } -static NvHandle __nvoc_thunk_GpuResource_kctxshareapiGetInternalObjectHandle(struct KernelCtxShareApi *pGpuResource) { - return gpuresGetInternalObjectHandle((struct GpuResource *)(((unsigned char *)pGpuResource) + __nvoc_rtti_KernelCtxShareApi_GpuResource.offset)); -} - -static NV_STATUS __nvoc_thunk_RsResource_kctxshareapiControlFilter(struct KernelCtxShareApi *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { - return resControlFilter((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_KernelCtxShareApi_RsResource.offset), pCallContext, pParams); -} - -static void __nvoc_thunk_RsResource_kctxshareapiAddAdditionalDependants(struct RsClient *pClient, struct KernelCtxShareApi *pResource, RsResourceRef *pReference) { - resAddAdditionalDependants(pClient, (struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_KernelCtxShareApi_RsResource.offset), pReference); -} - static NvU32 __nvoc_thunk_RsResource_kctxshareapiGetRefCount(struct KernelCtxShareApi *pResource) { return resGetRefCount((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_KernelCtxShareApi_RsResource.offset)); } -static NV_STATUS __nvoc_thunk_RmResource_kctxshareapiCheckMemInterUnmap(struct KernelCtxShareApi *pRmResource, NvBool bSubdeviceHandleProvided) { - return rmresCheckMemInterUnmap((struct RmResource *)(((unsigned char *)pRmResource) + __nvoc_rtti_KernelCtxShareApi_RmResource.offset), bSubdeviceHandleProvided); -} - -static NV_STATUS __nvoc_thunk_RsResource_kctxshareapiMapTo(struct KernelCtxShareApi *pResource, RS_RES_MAP_TO_PARAMS *pParams) { - return resMapTo((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_KernelCtxShareApi_RsResource.offset), pParams); +static void __nvoc_thunk_RsResource_kctxshareapiAddAdditionalDependants(struct RsClient *pClient, struct KernelCtxShareApi *pResource, RsResourceRef *pReference) { + resAddAdditionalDependants(pClient, (struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_KernelCtxShareApi_RsResource.offset), pReference); } static NV_STATUS __nvoc_thunk_RmResource_kctxshareapiControl_Prologue(struct KernelCtxShareApi *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { @@ -327,18 +312,10 @@ return gpuresInternalControlForward((struct GpuResource *)(((unsigned char *)pGpuResource) + __nvoc_rtti_KernelCtxShareApi_GpuResource.offset), command, pParams, size); } -static void __nvoc_thunk_RsResource_kctxshareapiPreDestruct(struct KernelCtxShareApi *pResource) { - resPreDestruct((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_KernelCtxShareApi_RsResource.offset)); -} - static NV_STATUS __nvoc_thunk_RsResource_kctxshareapiUnmapFrom(struct KernelCtxShareApi *pResource, RS_RES_UNMAP_FROM_PARAMS *pParams) { return resUnmapFrom((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_KernelCtxShareApi_RsResource.offset), pParams); } -static NV_STATUS __nvoc_thunk_RsResource_kctxshareapiIsDuplicate(struct KernelCtxShareApi *pResource, NvHandle hMemory, NvBool *pDuplicate) { - return resIsDuplicate((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_KernelCtxShareApi_RsResource.offset), hMemory, pDuplicate); -} - static void __nvoc_thunk_RmResource_kctxshareapiControl_Epilogue(struct KernelCtxShareApi *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { rmresControl_Epilogue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_KernelCtxShareApi_RmResource.offset), pCallContext, pParams); } @@ -347,6 +324,46 @@ return resControlLookup((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_KernelCtxShareApi_RsResource.offset), pParams, ppEntry); } +static NvHandle __nvoc_thunk_GpuResource_kctxshareapiGetInternalObjectHandle(struct KernelCtxShareApi *pGpuResource) { + return gpuresGetInternalObjectHandle((struct GpuResource *)(((unsigned char *)pGpuResource) + __nvoc_rtti_KernelCtxShareApi_GpuResource.offset)); +} + +static NV_STATUS __nvoc_thunk_GpuResource_kctxshareapiControl(struct KernelCtxShareApi *pGpuResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return gpuresControl((struct GpuResource *)(((unsigned char *)pGpuResource) + __nvoc_rtti_KernelCtxShareApi_GpuResource.offset), pCallContext, pParams); +} + +static NV_STATUS __nvoc_thunk_GpuResource_kctxshareapiUnmap(struct KernelCtxShareApi *pGpuResource, struct CALL_CONTEXT *pCallContext, struct RsCpuMapping *pCpuMapping) { + return gpuresUnmap((struct GpuResource *)(((unsigned char *)pGpuResource) + __nvoc_rtti_KernelCtxShareApi_GpuResource.offset), pCallContext, pCpuMapping); +} + +static NV_STATUS __nvoc_thunk_RmResource_kctxshareapiGetMemInterMapParams(struct KernelCtxShareApi *pRmResource, RMRES_MEM_INTER_MAP_PARAMS *pParams) { + return rmresGetMemInterMapParams((struct RmResource *)(((unsigned char *)pRmResource) + __nvoc_rtti_KernelCtxShareApi_RmResource.offset), pParams); +} + +static NV_STATUS __nvoc_thunk_RmResource_kctxshareapiGetMemoryMappingDescriptor(struct KernelCtxShareApi *pRmResource, struct MEMORY_DESCRIPTOR **ppMemDesc) { + return rmresGetMemoryMappingDescriptor((struct RmResource *)(((unsigned char *)pRmResource) + __nvoc_rtti_KernelCtxShareApi_RmResource.offset), ppMemDesc); +} + +static NV_STATUS __nvoc_thunk_RsResource_kctxshareapiControlFilter(struct KernelCtxShareApi *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return resControlFilter((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_KernelCtxShareApi_RsResource.offset), pCallContext, pParams); +} + +static NV_STATUS __nvoc_thunk_RmResource_kctxshareapiControlSerialization_Prologue(struct KernelCtxShareApi *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return rmresControlSerialization_Prologue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_KernelCtxShareApi_RmResource.offset), pCallContext, pParams); +} + +static void __nvoc_thunk_RsResource_kctxshareapiPreDestruct(struct KernelCtxShareApi *pResource) { + resPreDestruct((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_KernelCtxShareApi_RsResource.offset)); +} + +static NV_STATUS __nvoc_thunk_RsResource_kctxshareapiIsDuplicate(struct KernelCtxShareApi *pResource, NvHandle hMemory, NvBool *pDuplicate) { + return resIsDuplicate((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_KernelCtxShareApi_RsResource.offset), hMemory, pDuplicate); +} + +static void __nvoc_thunk_RmResource_kctxshareapiControlSerialization_Epilogue(struct KernelCtxShareApi *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + rmresControlSerialization_Epilogue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_KernelCtxShareApi_RmResource.offset), pCallContext, pParams); +} + static NV_STATUS __nvoc_thunk_GpuResource_kctxshareapiMap(struct KernelCtxShareApi *pGpuResource, struct CALL_CONTEXT *pCallContext, struct RS_CPU_MAP_PARAMS *pParams, struct RsCpuMapping *pCpuMapping) { return gpuresMap((struct GpuResource *)(((unsigned char *)pGpuResource) + __nvoc_rtti_KernelCtxShareApi_GpuResource.offset), pCallContext, pParams, pCpuMapping); } @@ -466,27 +483,15 @@ pThis->__kctxshareapiShareCallback__ = &__nvoc_thunk_GpuResource_kctxshareapiShareCallback; - pThis->__kctxshareapiControl__ = &__nvoc_thunk_GpuResource_kctxshareapiControl; - - pThis->__kctxshareapiUnmap__ = &__nvoc_thunk_GpuResource_kctxshareapiUnmap; - - pThis->__kctxshareapiGetMemInterMapParams__ = &__nvoc_thunk_RmResource_kctxshareapiGetMemInterMapParams; + pThis->__kctxshareapiCheckMemInterUnmap__ = &__nvoc_thunk_RmResource_kctxshareapiCheckMemInterUnmap; - pThis->__kctxshareapiGetMemoryMappingDescriptor__ = &__nvoc_thunk_RmResource_kctxshareapiGetMemoryMappingDescriptor; + pThis->__kctxshareapiMapTo__ = &__nvoc_thunk_RsResource_kctxshareapiMapTo; pThis->__kctxshareapiGetMapAddrSpace__ = &__nvoc_thunk_GpuResource_kctxshareapiGetMapAddrSpace; - pThis->__kctxshareapiGetInternalObjectHandle__ = &__nvoc_thunk_GpuResource_kctxshareapiGetInternalObjectHandle; - - pThis->__kctxshareapiControlFilter__ = &__nvoc_thunk_RsResource_kctxshareapiControlFilter; - - pThis->__kctxshareapiAddAdditionalDependants__ = &__nvoc_thunk_RsResource_kctxshareapiAddAdditionalDependants; - pThis->__kctxshareapiGetRefCount__ = &__nvoc_thunk_RsResource_kctxshareapiGetRefCount; - pThis->__kctxshareapiCheckMemInterUnmap__ = &__nvoc_thunk_RmResource_kctxshareapiCheckMemInterUnmap; - - pThis->__kctxshareapiMapTo__ = &__nvoc_thunk_RsResource_kctxshareapiMapTo; + pThis->__kctxshareapiAddAdditionalDependants__ = &__nvoc_thunk_RsResource_kctxshareapiAddAdditionalDependants; pThis->__kctxshareapiControl_Prologue__ = &__nvoc_thunk_RmResource_kctxshareapiControl_Prologue; @@ -494,16 +499,32 @@ pThis->__kctxshareapiInternalControlForward__ = &__nvoc_thunk_GpuResource_kctxshareapiInternalControlForward; - pThis->__kctxshareapiPreDestruct__ = &__nvoc_thunk_RsResource_kctxshareapiPreDestruct; - pThis->__kctxshareapiUnmapFrom__ = &__nvoc_thunk_RsResource_kctxshareapiUnmapFrom; - pThis->__kctxshareapiIsDuplicate__ = &__nvoc_thunk_RsResource_kctxshareapiIsDuplicate; - pThis->__kctxshareapiControl_Epilogue__ = &__nvoc_thunk_RmResource_kctxshareapiControl_Epilogue; pThis->__kctxshareapiControlLookup__ = &__nvoc_thunk_RsResource_kctxshareapiControlLookup; + pThis->__kctxshareapiGetInternalObjectHandle__ = &__nvoc_thunk_GpuResource_kctxshareapiGetInternalObjectHandle; + + pThis->__kctxshareapiControl__ = &__nvoc_thunk_GpuResource_kctxshareapiControl; + + pThis->__kctxshareapiUnmap__ = &__nvoc_thunk_GpuResource_kctxshareapiUnmap; + + pThis->__kctxshareapiGetMemInterMapParams__ = &__nvoc_thunk_RmResource_kctxshareapiGetMemInterMapParams; + + pThis->__kctxshareapiGetMemoryMappingDescriptor__ = &__nvoc_thunk_RmResource_kctxshareapiGetMemoryMappingDescriptor; + + pThis->__kctxshareapiControlFilter__ = &__nvoc_thunk_RsResource_kctxshareapiControlFilter; + + pThis->__kctxshareapiControlSerialization_Prologue__ = &__nvoc_thunk_RmResource_kctxshareapiControlSerialization_Prologue; + + pThis->__kctxshareapiPreDestruct__ = &__nvoc_thunk_RsResource_kctxshareapiPreDestruct; + + pThis->__kctxshareapiIsDuplicate__ = &__nvoc_thunk_RsResource_kctxshareapiIsDuplicate; + + pThis->__kctxshareapiControlSerialization_Epilogue__ = &__nvoc_thunk_RmResource_kctxshareapiControlSerialization_Epilogue; + pThis->__kctxshareapiMap__ = &__nvoc_thunk_GpuResource_kctxshareapiMap; pThis->__kctxshareapiAccessCallback__ = &__nvoc_thunk_RmResource_kctxshareapiAccessCallback; @@ -530,13 +551,16 @@ Object *pParentObj; KernelCtxShareApi *pThis; - pThis = portMemAllocNonPaged(sizeof(KernelCtxShareApi)); - if (pThis == NULL) return NV_ERR_NO_MEMORY; + status = __nvoc_handleObjCreateMemAlloc(createFlags, sizeof(KernelCtxShareApi), (void**)&pThis, (void**)ppThis); + if (status != NV_OK) + return status; portMemSet(pThis, 0, sizeof(KernelCtxShareApi)); __nvoc_initRtti(staticCast(pThis, Dynamic), &__nvoc_class_def_KernelCtxShareApi); + pThis->__nvoc_base_GpuResource.__nvoc_base_RmResource.__nvoc_base_RsResource.__nvoc_base_Object.createFlags = createFlags; + if (pParent != NULL && !(createFlags & NVOC_OBJ_CREATE_FLAGS_PARENT_HALSPEC_ONLY)) { pParentObj = dynamicCast(pParent, Object); @@ -552,11 +576,17 @@ if (status != NV_OK) goto __nvoc_objCreate_KernelCtxShareApi_cleanup; *ppThis = pThis; + return NV_OK; __nvoc_objCreate_KernelCtxShareApi_cleanup: // do not call destructors here since the constructor already called them - portMemFree(pThis); + if (createFlags & NVOC_OBJ_CREATE_FLAGS_IN_PLACE_CONSTRUCT) + portMemSet(pThis, 0, sizeof(KernelCtxShareApi)); + else + portMemFree(pThis); + + // coverity[leaked_storage:FALSE] return status; } diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/generated/g_kernel_ctxshare_nvoc.h nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_kernel_ctxshare_nvoc.h --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/generated/g_kernel_ctxshare_nvoc.h 2023-10-25 20:27:07.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_kernel_ctxshare_nvoc.h 2024-03-05 22:18:26.000000000 +0000 @@ -206,25 +206,27 @@ NV_STATUS (*__kctxshareapiCtrlCmdGetCwdWatermark__)(struct KernelCtxShareApi *, NV9067_CTRL_CWD_WATERMARK_PARAMS *); NV_STATUS (*__kctxshareapiCtrlCmdSetCwdWatermark__)(struct KernelCtxShareApi *, NV9067_CTRL_CWD_WATERMARK_PARAMS *); NvBool (*__kctxshareapiShareCallback__)(struct KernelCtxShareApi *, struct RsClient *, struct RsResourceRef *, RS_SHARE_POLICY *); - NV_STATUS (*__kctxshareapiControl__)(struct KernelCtxShareApi *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); - NV_STATUS (*__kctxshareapiUnmap__)(struct KernelCtxShareApi *, struct CALL_CONTEXT *, struct RsCpuMapping *); - NV_STATUS (*__kctxshareapiGetMemInterMapParams__)(struct KernelCtxShareApi *, RMRES_MEM_INTER_MAP_PARAMS *); - NV_STATUS (*__kctxshareapiGetMemoryMappingDescriptor__)(struct KernelCtxShareApi *, struct MEMORY_DESCRIPTOR **); - NV_STATUS (*__kctxshareapiGetMapAddrSpace__)(struct KernelCtxShareApi *, struct CALL_CONTEXT *, NvU32, NV_ADDRESS_SPACE *); - NvHandle (*__kctxshareapiGetInternalObjectHandle__)(struct KernelCtxShareApi *); - NV_STATUS (*__kctxshareapiControlFilter__)(struct KernelCtxShareApi *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); - void (*__kctxshareapiAddAdditionalDependants__)(struct RsClient *, struct KernelCtxShareApi *, RsResourceRef *); - NvU32 (*__kctxshareapiGetRefCount__)(struct KernelCtxShareApi *); NV_STATUS (*__kctxshareapiCheckMemInterUnmap__)(struct KernelCtxShareApi *, NvBool); NV_STATUS (*__kctxshareapiMapTo__)(struct KernelCtxShareApi *, RS_RES_MAP_TO_PARAMS *); + NV_STATUS (*__kctxshareapiGetMapAddrSpace__)(struct KernelCtxShareApi *, struct CALL_CONTEXT *, NvU32, NV_ADDRESS_SPACE *); + NvU32 (*__kctxshareapiGetRefCount__)(struct KernelCtxShareApi *); + void (*__kctxshareapiAddAdditionalDependants__)(struct RsClient *, struct KernelCtxShareApi *, RsResourceRef *); NV_STATUS (*__kctxshareapiControl_Prologue__)(struct KernelCtxShareApi *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); NV_STATUS (*__kctxshareapiGetRegBaseOffsetAndSize__)(struct KernelCtxShareApi *, struct OBJGPU *, NvU32 *, NvU32 *); NV_STATUS (*__kctxshareapiInternalControlForward__)(struct KernelCtxShareApi *, NvU32, void *, NvU32); - void (*__kctxshareapiPreDestruct__)(struct KernelCtxShareApi *); NV_STATUS (*__kctxshareapiUnmapFrom__)(struct KernelCtxShareApi *, RS_RES_UNMAP_FROM_PARAMS *); - NV_STATUS (*__kctxshareapiIsDuplicate__)(struct KernelCtxShareApi *, NvHandle, NvBool *); void (*__kctxshareapiControl_Epilogue__)(struct KernelCtxShareApi *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); NV_STATUS (*__kctxshareapiControlLookup__)(struct KernelCtxShareApi *, struct RS_RES_CONTROL_PARAMS_INTERNAL *, const struct NVOC_EXPORTED_METHOD_DEF **); + NvHandle (*__kctxshareapiGetInternalObjectHandle__)(struct KernelCtxShareApi *); + NV_STATUS (*__kctxshareapiControl__)(struct KernelCtxShareApi *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); + NV_STATUS (*__kctxshareapiUnmap__)(struct KernelCtxShareApi *, struct CALL_CONTEXT *, struct RsCpuMapping *); + NV_STATUS (*__kctxshareapiGetMemInterMapParams__)(struct KernelCtxShareApi *, RMRES_MEM_INTER_MAP_PARAMS *); + NV_STATUS (*__kctxshareapiGetMemoryMappingDescriptor__)(struct KernelCtxShareApi *, struct MEMORY_DESCRIPTOR **); + NV_STATUS (*__kctxshareapiControlFilter__)(struct KernelCtxShareApi *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); + NV_STATUS (*__kctxshareapiControlSerialization_Prologue__)(struct KernelCtxShareApi *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); + void (*__kctxshareapiPreDestruct__)(struct KernelCtxShareApi *); + NV_STATUS (*__kctxshareapiIsDuplicate__)(struct KernelCtxShareApi *, NvHandle, NvBool *); + void (*__kctxshareapiControlSerialization_Epilogue__)(struct KernelCtxShareApi *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); NV_STATUS (*__kctxshareapiMap__)(struct KernelCtxShareApi *, struct CALL_CONTEXT *, struct RS_CPU_MAP_PARAMS *, struct RsCpuMapping *); NvBool (*__kctxshareapiAccessCallback__)(struct KernelCtxShareApi *, struct RsClient *, void *, RsAccessRight); struct KernelCtxShare *pShareData; @@ -264,25 +266,27 @@ #define kctxshareapiCtrlCmdGetCwdWatermark(pKernelCtxShareApi, pParams) kctxshareapiCtrlCmdGetCwdWatermark_DISPATCH(pKernelCtxShareApi, pParams) #define kctxshareapiCtrlCmdSetCwdWatermark(pKernelCtxShareApi, pParams) kctxshareapiCtrlCmdSetCwdWatermark_DISPATCH(pKernelCtxShareApi, pParams) #define kctxshareapiShareCallback(pGpuResource, pInvokingClient, pParentRef, pSharePolicy) kctxshareapiShareCallback_DISPATCH(pGpuResource, pInvokingClient, pParentRef, pSharePolicy) -#define kctxshareapiControl(pGpuResource, pCallContext, pParams) kctxshareapiControl_DISPATCH(pGpuResource, pCallContext, pParams) -#define kctxshareapiUnmap(pGpuResource, pCallContext, pCpuMapping) kctxshareapiUnmap_DISPATCH(pGpuResource, pCallContext, pCpuMapping) -#define kctxshareapiGetMemInterMapParams(pRmResource, pParams) kctxshareapiGetMemInterMapParams_DISPATCH(pRmResource, pParams) -#define kctxshareapiGetMemoryMappingDescriptor(pRmResource, ppMemDesc) kctxshareapiGetMemoryMappingDescriptor_DISPATCH(pRmResource, ppMemDesc) -#define kctxshareapiGetMapAddrSpace(pGpuResource, pCallContext, mapFlags, pAddrSpace) kctxshareapiGetMapAddrSpace_DISPATCH(pGpuResource, pCallContext, mapFlags, pAddrSpace) -#define kctxshareapiGetInternalObjectHandle(pGpuResource) kctxshareapiGetInternalObjectHandle_DISPATCH(pGpuResource) -#define kctxshareapiControlFilter(pResource, pCallContext, pParams) kctxshareapiControlFilter_DISPATCH(pResource, pCallContext, pParams) -#define kctxshareapiAddAdditionalDependants(pClient, pResource, pReference) kctxshareapiAddAdditionalDependants_DISPATCH(pClient, pResource, pReference) -#define kctxshareapiGetRefCount(pResource) kctxshareapiGetRefCount_DISPATCH(pResource) #define kctxshareapiCheckMemInterUnmap(pRmResource, bSubdeviceHandleProvided) kctxshareapiCheckMemInterUnmap_DISPATCH(pRmResource, bSubdeviceHandleProvided) #define kctxshareapiMapTo(pResource, pParams) kctxshareapiMapTo_DISPATCH(pResource, pParams) +#define kctxshareapiGetMapAddrSpace(pGpuResource, pCallContext, mapFlags, pAddrSpace) kctxshareapiGetMapAddrSpace_DISPATCH(pGpuResource, pCallContext, mapFlags, pAddrSpace) +#define kctxshareapiGetRefCount(pResource) kctxshareapiGetRefCount_DISPATCH(pResource) +#define kctxshareapiAddAdditionalDependants(pClient, pResource, pReference) kctxshareapiAddAdditionalDependants_DISPATCH(pClient, pResource, pReference) #define kctxshareapiControl_Prologue(pResource, pCallContext, pParams) kctxshareapiControl_Prologue_DISPATCH(pResource, pCallContext, pParams) #define kctxshareapiGetRegBaseOffsetAndSize(pGpuResource, pGpu, pOffset, pSize) kctxshareapiGetRegBaseOffsetAndSize_DISPATCH(pGpuResource, pGpu, pOffset, pSize) #define kctxshareapiInternalControlForward(pGpuResource, command, pParams, size) kctxshareapiInternalControlForward_DISPATCH(pGpuResource, command, pParams, size) -#define kctxshareapiPreDestruct(pResource) kctxshareapiPreDestruct_DISPATCH(pResource) #define kctxshareapiUnmapFrom(pResource, pParams) kctxshareapiUnmapFrom_DISPATCH(pResource, pParams) -#define kctxshareapiIsDuplicate(pResource, hMemory, pDuplicate) kctxshareapiIsDuplicate_DISPATCH(pResource, hMemory, pDuplicate) #define kctxshareapiControl_Epilogue(pResource, pCallContext, pParams) kctxshareapiControl_Epilogue_DISPATCH(pResource, pCallContext, pParams) #define kctxshareapiControlLookup(pResource, pParams, ppEntry) kctxshareapiControlLookup_DISPATCH(pResource, pParams, ppEntry) +#define kctxshareapiGetInternalObjectHandle(pGpuResource) kctxshareapiGetInternalObjectHandle_DISPATCH(pGpuResource) +#define kctxshareapiControl(pGpuResource, pCallContext, pParams) kctxshareapiControl_DISPATCH(pGpuResource, pCallContext, pParams) +#define kctxshareapiUnmap(pGpuResource, pCallContext, pCpuMapping) kctxshareapiUnmap_DISPATCH(pGpuResource, pCallContext, pCpuMapping) +#define kctxshareapiGetMemInterMapParams(pRmResource, pParams) kctxshareapiGetMemInterMapParams_DISPATCH(pRmResource, pParams) +#define kctxshareapiGetMemoryMappingDescriptor(pRmResource, ppMemDesc) kctxshareapiGetMemoryMappingDescriptor_DISPATCH(pRmResource, ppMemDesc) +#define kctxshareapiControlFilter(pResource, pCallContext, pParams) kctxshareapiControlFilter_DISPATCH(pResource, pCallContext, pParams) +#define kctxshareapiControlSerialization_Prologue(pResource, pCallContext, pParams) kctxshareapiControlSerialization_Prologue_DISPATCH(pResource, pCallContext, pParams) +#define kctxshareapiPreDestruct(pResource) kctxshareapiPreDestruct_DISPATCH(pResource) +#define kctxshareapiIsDuplicate(pResource, hMemory, pDuplicate) kctxshareapiIsDuplicate_DISPATCH(pResource, hMemory, pDuplicate) +#define kctxshareapiControlSerialization_Epilogue(pResource, pCallContext, pParams) kctxshareapiControlSerialization_Epilogue_DISPATCH(pResource, pCallContext, pParams) #define kctxshareapiMap(pGpuResource, pCallContext, pParams, pCpuMapping) kctxshareapiMap_DISPATCH(pGpuResource, pCallContext, pParams, pCpuMapping) #define kctxshareapiAccessCallback(pResource, pInvokingClient, pAllocParams, accessRight) kctxshareapiAccessCallback_DISPATCH(pResource, pInvokingClient, pAllocParams, accessRight) NvBool kctxshareapiCanCopy_IMPL(struct KernelCtxShareApi *pKernelCtxShareApi); @@ -313,48 +317,24 @@ return pGpuResource->__kctxshareapiShareCallback__(pGpuResource, pInvokingClient, pParentRef, pSharePolicy); } -static inline NV_STATUS kctxshareapiControl_DISPATCH(struct KernelCtxShareApi *pGpuResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { - return pGpuResource->__kctxshareapiControl__(pGpuResource, pCallContext, pParams); -} - -static inline NV_STATUS kctxshareapiUnmap_DISPATCH(struct KernelCtxShareApi *pGpuResource, struct CALL_CONTEXT *pCallContext, struct RsCpuMapping *pCpuMapping) { - return pGpuResource->__kctxshareapiUnmap__(pGpuResource, pCallContext, pCpuMapping); -} - -static inline NV_STATUS kctxshareapiGetMemInterMapParams_DISPATCH(struct KernelCtxShareApi *pRmResource, RMRES_MEM_INTER_MAP_PARAMS *pParams) { - return pRmResource->__kctxshareapiGetMemInterMapParams__(pRmResource, pParams); +static inline NV_STATUS kctxshareapiCheckMemInterUnmap_DISPATCH(struct KernelCtxShareApi *pRmResource, NvBool bSubdeviceHandleProvided) { + return pRmResource->__kctxshareapiCheckMemInterUnmap__(pRmResource, bSubdeviceHandleProvided); } -static inline NV_STATUS kctxshareapiGetMemoryMappingDescriptor_DISPATCH(struct KernelCtxShareApi *pRmResource, struct MEMORY_DESCRIPTOR **ppMemDesc) { - return pRmResource->__kctxshareapiGetMemoryMappingDescriptor__(pRmResource, ppMemDesc); +static inline NV_STATUS kctxshareapiMapTo_DISPATCH(struct KernelCtxShareApi *pResource, RS_RES_MAP_TO_PARAMS *pParams) { + return pResource->__kctxshareapiMapTo__(pResource, pParams); } static inline NV_STATUS kctxshareapiGetMapAddrSpace_DISPATCH(struct KernelCtxShareApi *pGpuResource, struct CALL_CONTEXT *pCallContext, NvU32 mapFlags, NV_ADDRESS_SPACE *pAddrSpace) { return pGpuResource->__kctxshareapiGetMapAddrSpace__(pGpuResource, pCallContext, mapFlags, pAddrSpace); } -static inline NvHandle kctxshareapiGetInternalObjectHandle_DISPATCH(struct KernelCtxShareApi *pGpuResource) { - return pGpuResource->__kctxshareapiGetInternalObjectHandle__(pGpuResource); -} - -static inline NV_STATUS kctxshareapiControlFilter_DISPATCH(struct KernelCtxShareApi *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { - return pResource->__kctxshareapiControlFilter__(pResource, pCallContext, pParams); -} - -static inline void kctxshareapiAddAdditionalDependants_DISPATCH(struct RsClient *pClient, struct KernelCtxShareApi *pResource, RsResourceRef *pReference) { - pResource->__kctxshareapiAddAdditionalDependants__(pClient, pResource, pReference); -} - static inline NvU32 kctxshareapiGetRefCount_DISPATCH(struct KernelCtxShareApi *pResource) { return pResource->__kctxshareapiGetRefCount__(pResource); } -static inline NV_STATUS kctxshareapiCheckMemInterUnmap_DISPATCH(struct KernelCtxShareApi *pRmResource, NvBool bSubdeviceHandleProvided) { - return pRmResource->__kctxshareapiCheckMemInterUnmap__(pRmResource, bSubdeviceHandleProvided); -} - -static inline NV_STATUS kctxshareapiMapTo_DISPATCH(struct KernelCtxShareApi *pResource, RS_RES_MAP_TO_PARAMS *pParams) { - return pResource->__kctxshareapiMapTo__(pResource, pParams); +static inline void kctxshareapiAddAdditionalDependants_DISPATCH(struct RsClient *pClient, struct KernelCtxShareApi *pResource, RsResourceRef *pReference) { + pResource->__kctxshareapiAddAdditionalDependants__(pClient, pResource, pReference); } static inline NV_STATUS kctxshareapiControl_Prologue_DISPATCH(struct KernelCtxShareApi *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { @@ -369,18 +349,10 @@ return pGpuResource->__kctxshareapiInternalControlForward__(pGpuResource, command, pParams, size); } -static inline void kctxshareapiPreDestruct_DISPATCH(struct KernelCtxShareApi *pResource) { - pResource->__kctxshareapiPreDestruct__(pResource); -} - static inline NV_STATUS kctxshareapiUnmapFrom_DISPATCH(struct KernelCtxShareApi *pResource, RS_RES_UNMAP_FROM_PARAMS *pParams) { return pResource->__kctxshareapiUnmapFrom__(pResource, pParams); } -static inline NV_STATUS kctxshareapiIsDuplicate_DISPATCH(struct KernelCtxShareApi *pResource, NvHandle hMemory, NvBool *pDuplicate) { - return pResource->__kctxshareapiIsDuplicate__(pResource, hMemory, pDuplicate); -} - static inline void kctxshareapiControl_Epilogue_DISPATCH(struct KernelCtxShareApi *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { pResource->__kctxshareapiControl_Epilogue__(pResource, pCallContext, pParams); } @@ -389,6 +361,46 @@ return pResource->__kctxshareapiControlLookup__(pResource, pParams, ppEntry); } +static inline NvHandle kctxshareapiGetInternalObjectHandle_DISPATCH(struct KernelCtxShareApi *pGpuResource) { + return pGpuResource->__kctxshareapiGetInternalObjectHandle__(pGpuResource); +} + +static inline NV_STATUS kctxshareapiControl_DISPATCH(struct KernelCtxShareApi *pGpuResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return pGpuResource->__kctxshareapiControl__(pGpuResource, pCallContext, pParams); +} + +static inline NV_STATUS kctxshareapiUnmap_DISPATCH(struct KernelCtxShareApi *pGpuResource, struct CALL_CONTEXT *pCallContext, struct RsCpuMapping *pCpuMapping) { + return pGpuResource->__kctxshareapiUnmap__(pGpuResource, pCallContext, pCpuMapping); +} + +static inline NV_STATUS kctxshareapiGetMemInterMapParams_DISPATCH(struct KernelCtxShareApi *pRmResource, RMRES_MEM_INTER_MAP_PARAMS *pParams) { + return pRmResource->__kctxshareapiGetMemInterMapParams__(pRmResource, pParams); +} + +static inline NV_STATUS kctxshareapiGetMemoryMappingDescriptor_DISPATCH(struct KernelCtxShareApi *pRmResource, struct MEMORY_DESCRIPTOR **ppMemDesc) { + return pRmResource->__kctxshareapiGetMemoryMappingDescriptor__(pRmResource, ppMemDesc); +} + +static inline NV_STATUS kctxshareapiControlFilter_DISPATCH(struct KernelCtxShareApi *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return pResource->__kctxshareapiControlFilter__(pResource, pCallContext, pParams); +} + +static inline NV_STATUS kctxshareapiControlSerialization_Prologue_DISPATCH(struct KernelCtxShareApi *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return pResource->__kctxshareapiControlSerialization_Prologue__(pResource, pCallContext, pParams); +} + +static inline void kctxshareapiPreDestruct_DISPATCH(struct KernelCtxShareApi *pResource) { + pResource->__kctxshareapiPreDestruct__(pResource); +} + +static inline NV_STATUS kctxshareapiIsDuplicate_DISPATCH(struct KernelCtxShareApi *pResource, NvHandle hMemory, NvBool *pDuplicate) { + return pResource->__kctxshareapiIsDuplicate__(pResource, hMemory, pDuplicate); +} + +static inline void kctxshareapiControlSerialization_Epilogue_DISPATCH(struct KernelCtxShareApi *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + pResource->__kctxshareapiControlSerialization_Epilogue__(pResource, pCallContext, pParams); +} + static inline NV_STATUS kctxshareapiMap_DISPATCH(struct KernelCtxShareApi *pGpuResource, struct CALL_CONTEXT *pCallContext, struct RS_CPU_MAP_PARAMS *pParams, struct RsCpuMapping *pCpuMapping) { return pGpuResource->__kctxshareapiMap__(pGpuResource, pCallContext, pParams, pCpuMapping); } diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/generated/g_kernel_falcon_nvoc.c nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_kernel_falcon_nvoc.c --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/generated/g_kernel_falcon_nvoc.c 2023-10-25 20:27:07.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_kernel_falcon_nvoc.c 2024-03-05 22:18:26.000000000 +0000 @@ -13,6 +13,10 @@ extern const struct NVOC_CLASS_DEF __nvoc_class_def_KernelFalcon; +extern const struct NVOC_CLASS_DEF __nvoc_class_def_CrashCatEngine; + +extern const struct NVOC_CLASS_DEF __nvoc_class_def_KernelCrashCatEngine; + void __nvoc_init_KernelFalcon(KernelFalcon*, RmHalspecOwner* ); void __nvoc_init_funcTable_KernelFalcon(KernelFalcon*, RmHalspecOwner* ); NV_STATUS __nvoc_ctor_KernelFalcon(KernelFalcon*, RmHalspecOwner* ); @@ -26,17 +30,30 @@ /*offset=*/ 0, }; +static const struct NVOC_RTTI __nvoc_rtti_KernelFalcon_CrashCatEngine = { + /*pClassDef=*/ &__nvoc_class_def_CrashCatEngine, + /*dtor=*/ &__nvoc_destructFromBase, + /*offset=*/ NV_OFFSETOF(KernelFalcon, __nvoc_base_KernelCrashCatEngine.__nvoc_base_CrashCatEngine), +}; + +static const struct NVOC_RTTI __nvoc_rtti_KernelFalcon_KernelCrashCatEngine = { + /*pClassDef=*/ &__nvoc_class_def_KernelCrashCatEngine, + /*dtor=*/ &__nvoc_destructFromBase, + /*offset=*/ NV_OFFSETOF(KernelFalcon, __nvoc_base_KernelCrashCatEngine), +}; + static const struct NVOC_CASTINFO __nvoc_castinfo_KernelFalcon = { - /*numRelatives=*/ 1, + /*numRelatives=*/ 3, /*relatives=*/ { &__nvoc_rtti_KernelFalcon_KernelFalcon, + &__nvoc_rtti_KernelFalcon_KernelCrashCatEngine, + &__nvoc_rtti_KernelFalcon_CrashCatEngine, }, }; // Not instantiable because it's not derived from class "Object" // Not instantiable because it's an abstract class with following pure virtual functions: // kflcnResetHw -// kflcnIsEngineInReset const struct NVOC_CLASS_DEF __nvoc_class_def_KernelFalcon = { /*classInfo=*/ { @@ -52,13 +69,75 @@ /*pExportInfo=*/ &__nvoc_export_info_KernelFalcon }; +static NvU32 __nvoc_thunk_KernelFalcon_kcrashcatEngineRegRead(struct OBJGPU *pGpu, struct KernelCrashCatEngine *pKernelFlcn, NvU32 offset) { + return kflcnRegRead(pGpu, (struct KernelFalcon *)(((unsigned char *)pKernelFlcn) - __nvoc_rtti_KernelFalcon_KernelCrashCatEngine.offset), offset); +} + +static void __nvoc_thunk_KernelFalcon_kcrashcatEngineRegWrite(struct OBJGPU *pGpu, struct KernelCrashCatEngine *pKernelFlcn, NvU32 offset, NvU32 data) { + kflcnRegWrite(pGpu, (struct KernelFalcon *)(((unsigned char *)pKernelFlcn) - __nvoc_rtti_KernelFalcon_KernelCrashCatEngine.offset), offset, data); +} + +static NvU32 __nvoc_thunk_KernelFalcon_kcrashcatEngineMaskDmemAddr(struct OBJGPU *pGpu, struct KernelCrashCatEngine *pKernelFlcn, NvU32 addr) { + return kflcnMaskDmemAddr(pGpu, (struct KernelFalcon *)(((unsigned char *)pKernelFlcn) - __nvoc_rtti_KernelFalcon_KernelCrashCatEngine.offset), addr); +} + +static void __nvoc_thunk_KernelCrashCatEngine_kflcnReadEmem(struct KernelFalcon *arg0, NvU64 offset, NvU64 size, void *pBuf) { + kcrashcatEngineReadEmem((struct KernelCrashCatEngine *)(((unsigned char *)arg0) + __nvoc_rtti_KernelFalcon_KernelCrashCatEngine.offset), offset, size, pBuf); +} + +static NvU32 __nvoc_thunk_KernelCrashCatEngine_kflcnGetWFL0Offset(struct KernelFalcon *arg0) { + return kcrashcatEngineGetWFL0Offset((struct KernelCrashCatEngine *)(((unsigned char *)arg0) + __nvoc_rtti_KernelFalcon_KernelCrashCatEngine.offset)); +} + +static const NvU32 *__nvoc_thunk_KernelCrashCatEngine_kflcnGetScratchOffsets(struct KernelFalcon *arg0, NV_CRASHCAT_SCRATCH_GROUP_ID scratchGroupId) { + return kcrashcatEngineGetScratchOffsets((struct KernelCrashCatEngine *)(((unsigned char *)arg0) + __nvoc_rtti_KernelFalcon_KernelCrashCatEngine.offset), scratchGroupId); +} + +static void __nvoc_thunk_KernelCrashCatEngine_kflcnUnload(struct KernelFalcon *arg0) { + kcrashcatEngineUnload((struct KernelCrashCatEngine *)(((unsigned char *)arg0) + __nvoc_rtti_KernelFalcon_KernelCrashCatEngine.offset)); +} + +static NvBool __nvoc_thunk_KernelCrashCatEngine_kflcnConfigured(struct KernelFalcon *arg0) { + return kcrashcatEngineConfigured((struct KernelCrashCatEngine *)(((unsigned char *)arg0) + __nvoc_rtti_KernelFalcon_KernelCrashCatEngine.offset)); +} + +static NvU32 __nvoc_thunk_KernelCrashCatEngine_kflcnPriRead(struct KernelFalcon *arg0, NvU32 offset) { + return kcrashcatEnginePriRead((struct KernelCrashCatEngine *)(((unsigned char *)arg0) + __nvoc_rtti_KernelFalcon_KernelCrashCatEngine.offset), offset); +} + +static void __nvoc_thunk_KernelCrashCatEngine_kflcnVprintf(struct KernelFalcon *arg0, NvBool bReportStart, const char *fmt, va_list args) { + kcrashcatEngineVprintf((struct KernelCrashCatEngine *)(((unsigned char *)arg0) + __nvoc_rtti_KernelFalcon_KernelCrashCatEngine.offset), bReportStart, fmt, args); +} + +static void __nvoc_thunk_KernelCrashCatEngine_kflcnPriWrite(struct KernelFalcon *arg0, NvU32 offset, NvU32 data) { + kcrashcatEnginePriWrite((struct KernelCrashCatEngine *)(((unsigned char *)arg0) + __nvoc_rtti_KernelFalcon_KernelCrashCatEngine.offset), offset, data); +} + +static void __nvoc_thunk_KernelCrashCatEngine_kflcnSyncBufferDescriptor(struct KernelFalcon *arg0, CrashCatBufferDescriptor *pBufDesc, NvU32 offset, NvU32 size) { + kcrashcatEngineSyncBufferDescriptor((struct KernelCrashCatEngine *)(((unsigned char *)arg0) + __nvoc_rtti_KernelFalcon_KernelCrashCatEngine.offset), pBufDesc, offset, size); +} + +static void *__nvoc_thunk_KernelCrashCatEngine_kflcnMapBufferDescriptor(struct KernelFalcon *arg0, CrashCatBufferDescriptor *pBufDesc) { + return kcrashcatEngineMapBufferDescriptor((struct KernelCrashCatEngine *)(((unsigned char *)arg0) + __nvoc_rtti_KernelFalcon_KernelCrashCatEngine.offset), pBufDesc); +} + +static void __nvoc_thunk_KernelCrashCatEngine_kflcnUnmapBufferDescriptor(struct KernelFalcon *arg0, CrashCatBufferDescriptor *pBufDesc) { + kcrashcatEngineUnmapBufferDescriptor((struct KernelCrashCatEngine *)(((unsigned char *)arg0) + __nvoc_rtti_KernelFalcon_KernelCrashCatEngine.offset), pBufDesc); +} + +static void __nvoc_thunk_KernelCrashCatEngine_kflcnReadDmem(struct KernelFalcon *arg0, NvU32 offset, NvU32 size, void *pBuf) { + kcrashcatEngineReadDmem((struct KernelCrashCatEngine *)(((unsigned char *)arg0) + __nvoc_rtti_KernelFalcon_KernelCrashCatEngine.offset), offset, size, pBuf); +} + const struct NVOC_EXPORT_INFO __nvoc_export_info_KernelFalcon = { /*numEntries=*/ 0, /*pExportEntries=*/ 0 }; +void __nvoc_dtor_KernelCrashCatEngine(KernelCrashCatEngine*); void __nvoc_dtor_KernelFalcon(KernelFalcon *pThis) { + __nvoc_dtor_KernelCrashCatEngine(&pThis->__nvoc_base_KernelCrashCatEngine); PORT_UNREFERENCED_VARIABLE(pThis); } @@ -75,11 +154,15 @@ PORT_UNREFERENCED_VARIABLE(rmVariantHal_HalVarIdx); } +NV_STATUS __nvoc_ctor_KernelCrashCatEngine(KernelCrashCatEngine* , RmHalspecOwner* ); NV_STATUS __nvoc_ctor_KernelFalcon(KernelFalcon *pThis, RmHalspecOwner *pRmhalspecowner) { NV_STATUS status = NV_OK; + status = __nvoc_ctor_KernelCrashCatEngine(&pThis->__nvoc_base_KernelCrashCatEngine, pRmhalspecowner); + if (status != NV_OK) goto __nvoc_ctor_KernelFalcon_fail_KernelCrashCatEngine; __nvoc_init_dataField_KernelFalcon(pThis, pRmhalspecowner); goto __nvoc_ctor_KernelFalcon_exit; // Success +__nvoc_ctor_KernelFalcon_fail_KernelCrashCatEngine: __nvoc_ctor_KernelFalcon_exit: return status; @@ -97,135 +180,146 @@ PORT_UNREFERENCED_VARIABLE(rmVariantHal); PORT_UNREFERENCED_VARIABLE(rmVariantHal_HalVarIdx); + // Hal function -- kflcnRegRead + pThis->__kflcnRegRead__ = &kflcnRegRead_TU102; + + // Hal function -- kflcnRegWrite + pThis->__kflcnRegWrite__ = &kflcnRegWrite_TU102; + // Hal function -- kflcnIsRiscvActive - if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000002UL) )) /* RmVariantHal: PF_KERNEL_ONLY */ + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x000007e0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 */ { - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x000007e0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 */ - { - pThis->__kflcnIsRiscvActive__ = &kflcnIsRiscvActive_TU102; - } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x11f0f800UL) )) /* ChipHal: GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 | GH100 */ - { - pThis->__kflcnIsRiscvActive__ = &kflcnIsRiscvActive_GA10X; - } + pThis->__kflcnIsRiscvActive__ = &kflcnIsRiscvActive_TU102; + } + else + { + pThis->__kflcnIsRiscvActive__ = &kflcnIsRiscvActive_GA10X; } // Hal function -- kflcnRiscvProgramBcr - if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000002UL) )) /* RmVariantHal: PF_KERNEL_ONLY */ + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x000007e0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 */ + { + pThis->__kflcnRiscvProgramBcr__ = &kflcnRiscvProgramBcr_f2d351; + } + else { - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x11f0f800UL) )) /* ChipHal: GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 | GH100 */ - { - pThis->__kflcnRiscvProgramBcr__ = &kflcnRiscvProgramBcr_GA102; - } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x000007e0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 */ - { - pThis->__kflcnRiscvProgramBcr__ = &kflcnRiscvProgramBcr_f2d351; - } + pThis->__kflcnRiscvProgramBcr__ = &kflcnRiscvProgramBcr_GA102; } // Hal function -- kflcnSwitchToFalcon - if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000002UL) )) /* RmVariantHal: PF_KERNEL_ONLY */ + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x000007e0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 */ { - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x11f0f800UL) )) /* ChipHal: GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 | GH100 */ - { - pThis->__kflcnSwitchToFalcon__ = &kflcnSwitchToFalcon_GA10X; - } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x000007e0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 */ - { - pThis->__kflcnSwitchToFalcon__ = &kflcnSwitchToFalcon_b3696a; - } + pThis->__kflcnSwitchToFalcon__ = &kflcnSwitchToFalcon_b3696a; + } + else + { + pThis->__kflcnSwitchToFalcon__ = &kflcnSwitchToFalcon_GA10X; } pThis->__kflcnResetHw__ = NULL; // Hal function -- kflcnPreResetWait - if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000002UL) )) /* RmVariantHal: PF_KERNEL_ONLY */ + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x01f0f800UL) )) /* ChipHal: GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 */ { - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x01f0f800UL) )) /* ChipHal: GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 */ - { - pThis->__kflcnPreResetWait__ = &kflcnPreResetWait_GA10X; - } - // default - else - { - pThis->__kflcnPreResetWait__ = &kflcnPreResetWait_56cd7a; - } + pThis->__kflcnPreResetWait__ = &kflcnPreResetWait_GA10X; + } + // default + else + { + pThis->__kflcnPreResetWait__ = &kflcnPreResetWait_56cd7a; } // Hal function -- kflcnWaitForResetToFinish - if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000002UL) )) /* RmVariantHal: PF_KERNEL_ONLY */ + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x000007e0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 */ { - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x11f0f800UL) )) /* ChipHal: GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 | GH100 */ - { - pThis->__kflcnWaitForResetToFinish__ = &kflcnWaitForResetToFinish_GA102; - } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x000007e0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 */ - { - pThis->__kflcnWaitForResetToFinish__ = &kflcnWaitForResetToFinish_TU102; - } + pThis->__kflcnWaitForResetToFinish__ = &kflcnWaitForResetToFinish_TU102; + } + else + { + pThis->__kflcnWaitForResetToFinish__ = &kflcnWaitForResetToFinish_GA102; } - - pThis->__kflcnIsEngineInReset__ = NULL; // Hal function -- kflcnReadIntrStatus - if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000002UL) )) /* RmVariantHal: PF_KERNEL_ONLY */ + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x000007e0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 */ + { + pThis->__kflcnReadIntrStatus__ = &kflcnReadIntrStatus_TU102; + } + else { - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x000007e0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 */ - { - pThis->__kflcnReadIntrStatus__ = &kflcnReadIntrStatus_TU102; - } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x11f0f800UL) )) /* ChipHal: GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 | GH100 */ - { - pThis->__kflcnReadIntrStatus__ = &kflcnReadIntrStatus_GA102; - } + pThis->__kflcnReadIntrStatus__ = &kflcnReadIntrStatus_GA102; } // Hal function -- kflcnIntrRetrigger - if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000002UL) )) /* RmVariantHal: PF_KERNEL_ONLY */ + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x000003e0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 */ { - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x11f0fc00UL) )) /* ChipHal: GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 | GH100 */ - { - pThis->__kflcnIntrRetrigger__ = &kflcnIntrRetrigger_GA100; - } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x000003e0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 */ - { - pThis->__kflcnIntrRetrigger__ = &kflcnIntrRetrigger_b3696a; - } + pThis->__kflcnIntrRetrigger__ = &kflcnIntrRetrigger_b3696a; + } + else + { + pThis->__kflcnIntrRetrigger__ = &kflcnIntrRetrigger_GA100; } // Hal function -- kflcnMaskImemAddr - if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000002UL) )) /* RmVariantHal: PF_KERNEL_ONLY */ + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x000003e0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 */ + { + pThis->__kflcnMaskImemAddr__ = &kflcnMaskImemAddr_TU102; + } + else { - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x000003e0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 */ - { - pThis->__kflcnMaskImemAddr__ = &kflcnMaskImemAddr_TU102; - } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x11f0fc00UL) )) /* ChipHal: GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 | GH100 */ - { - pThis->__kflcnMaskImemAddr__ = &kflcnMaskImemAddr_GA100; - } + pThis->__kflcnMaskImemAddr__ = &kflcnMaskImemAddr_GA100; } // Hal function -- kflcnMaskDmemAddr - if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000002UL) )) /* RmVariantHal: PF_KERNEL_ONLY */ + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x000003e0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 */ + { + pThis->__kflcnMaskDmemAddr__ = &kflcnMaskDmemAddr_TU102; + } + else { - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x000003e0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 */ - { - pThis->__kflcnMaskDmemAddr__ = &kflcnMaskDmemAddr_TU102; - } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x11f0fc00UL) )) /* ChipHal: GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 | GH100 */ - { - pThis->__kflcnMaskDmemAddr__ = &kflcnMaskDmemAddr_GA100; - } + pThis->__kflcnMaskDmemAddr__ = &kflcnMaskDmemAddr_GA100; } + + pThis->__nvoc_base_KernelCrashCatEngine.__kcrashcatEngineRegRead__ = &__nvoc_thunk_KernelFalcon_kcrashcatEngineRegRead; + + pThis->__nvoc_base_KernelCrashCatEngine.__kcrashcatEngineRegWrite__ = &__nvoc_thunk_KernelFalcon_kcrashcatEngineRegWrite; + + pThis->__nvoc_base_KernelCrashCatEngine.__kcrashcatEngineMaskDmemAddr__ = &__nvoc_thunk_KernelFalcon_kcrashcatEngineMaskDmemAddr; + + pThis->__kflcnReadEmem__ = &__nvoc_thunk_KernelCrashCatEngine_kflcnReadEmem; + + pThis->__kflcnGetWFL0Offset__ = &__nvoc_thunk_KernelCrashCatEngine_kflcnGetWFL0Offset; + + pThis->__kflcnGetScratchOffsets__ = &__nvoc_thunk_KernelCrashCatEngine_kflcnGetScratchOffsets; + + pThis->__kflcnUnload__ = &__nvoc_thunk_KernelCrashCatEngine_kflcnUnload; + + pThis->__kflcnConfigured__ = &__nvoc_thunk_KernelCrashCatEngine_kflcnConfigured; + + pThis->__kflcnPriRead__ = &__nvoc_thunk_KernelCrashCatEngine_kflcnPriRead; + + pThis->__kflcnVprintf__ = &__nvoc_thunk_KernelCrashCatEngine_kflcnVprintf; + + pThis->__kflcnPriWrite__ = &__nvoc_thunk_KernelCrashCatEngine_kflcnPriWrite; + + pThis->__kflcnSyncBufferDescriptor__ = &__nvoc_thunk_KernelCrashCatEngine_kflcnSyncBufferDescriptor; + + pThis->__kflcnMapBufferDescriptor__ = &__nvoc_thunk_KernelCrashCatEngine_kflcnMapBufferDescriptor; + + pThis->__kflcnUnmapBufferDescriptor__ = &__nvoc_thunk_KernelCrashCatEngine_kflcnUnmapBufferDescriptor; + + pThis->__kflcnReadDmem__ = &__nvoc_thunk_KernelCrashCatEngine_kflcnReadDmem; } void __nvoc_init_funcTable_KernelFalcon(KernelFalcon *pThis, RmHalspecOwner *pRmhalspecowner) { __nvoc_init_funcTable_KernelFalcon_1(pThis, pRmhalspecowner); } +void __nvoc_init_KernelCrashCatEngine(KernelCrashCatEngine*, RmHalspecOwner* ); void __nvoc_init_KernelFalcon(KernelFalcon *pThis, RmHalspecOwner *pRmhalspecowner) { pThis->__nvoc_pbase_KernelFalcon = pThis; + pThis->__nvoc_pbase_CrashCatEngine = &pThis->__nvoc_base_KernelCrashCatEngine.__nvoc_base_CrashCatEngine; + pThis->__nvoc_pbase_KernelCrashCatEngine = &pThis->__nvoc_base_KernelCrashCatEngine; + __nvoc_init_KernelCrashCatEngine(&pThis->__nvoc_base_KernelCrashCatEngine, pRmhalspecowner); __nvoc_init_funcTable_KernelFalcon(pThis, pRmhalspecowner); } @@ -235,6 +329,10 @@ extern const struct NVOC_CLASS_DEF __nvoc_class_def_GenericKernelFalcon; +extern const struct NVOC_CLASS_DEF __nvoc_class_def_CrashCatEngine; + +extern const struct NVOC_CLASS_DEF __nvoc_class_def_KernelCrashCatEngine; + extern const struct NVOC_CLASS_DEF __nvoc_class_def_KernelFalcon; extern const struct NVOC_CLASS_DEF __nvoc_class_def_IntrService; @@ -254,6 +352,18 @@ /*offset=*/ 0, }; +static const struct NVOC_RTTI __nvoc_rtti_GenericKernelFalcon_CrashCatEngine = { + /*pClassDef=*/ &__nvoc_class_def_CrashCatEngine, + /*dtor=*/ &__nvoc_destructFromBase, + /*offset=*/ NV_OFFSETOF(GenericKernelFalcon, __nvoc_base_KernelFalcon.__nvoc_base_KernelCrashCatEngine.__nvoc_base_CrashCatEngine), +}; + +static const struct NVOC_RTTI __nvoc_rtti_GenericKernelFalcon_KernelCrashCatEngine = { + /*pClassDef=*/ &__nvoc_class_def_KernelCrashCatEngine, + /*dtor=*/ &__nvoc_destructFromBase, + /*offset=*/ NV_OFFSETOF(GenericKernelFalcon, __nvoc_base_KernelFalcon.__nvoc_base_KernelCrashCatEngine), +}; + static const struct NVOC_RTTI __nvoc_rtti_GenericKernelFalcon_KernelFalcon = { /*pClassDef=*/ &__nvoc_class_def_KernelFalcon, /*dtor=*/ &__nvoc_destructFromBase, @@ -273,12 +383,14 @@ }; static const struct NVOC_CASTINFO __nvoc_castinfo_GenericKernelFalcon = { - /*numRelatives=*/ 4, + /*numRelatives=*/ 6, /*relatives=*/ { &__nvoc_rtti_GenericKernelFalcon_GenericKernelFalcon, &__nvoc_rtti_GenericKernelFalcon_Object, &__nvoc_rtti_GenericKernelFalcon_IntrService, &__nvoc_rtti_GenericKernelFalcon_KernelFalcon, + &__nvoc_rtti_GenericKernelFalcon_KernelCrashCatEngine, + &__nvoc_rtti_GenericKernelFalcon_CrashCatEngine, }, }; @@ -301,11 +413,7 @@ return gkflcnResetHw(pGpu, (struct GenericKernelFalcon *)(((unsigned char *)pGenKernFlcn) - __nvoc_rtti_GenericKernelFalcon_KernelFalcon.offset)); } -static NvBool __nvoc_thunk_GenericKernelFalcon_kflcnIsEngineInReset(struct OBJGPU *pGpu, struct KernelFalcon *pGenKernFlcn) { - return gkflcnIsEngineInReset(pGpu, (struct GenericKernelFalcon *)(((unsigned char *)pGenKernFlcn) - __nvoc_rtti_GenericKernelFalcon_KernelFalcon.offset)); -} - -static void __nvoc_thunk_GenericKernelFalcon_intrservRegisterIntrService(struct OBJGPU *arg0, struct IntrService *arg1, IntrServiceRecord arg2[163]) { +static void __nvoc_thunk_GenericKernelFalcon_intrservRegisterIntrService(struct OBJGPU *arg0, struct IntrService *arg1, IntrServiceRecord arg2[167]) { gkflcnRegisterIntrService(arg0, (struct GenericKernelFalcon *)(((unsigned char *)arg1) - __nvoc_rtti_GenericKernelFalcon_IntrService.offset), arg2); } @@ -313,14 +421,74 @@ return gkflcnServiceNotificationInterrupt(arg0, (struct GenericKernelFalcon *)(((unsigned char *)arg1) - __nvoc_rtti_GenericKernelFalcon_IntrService.offset), arg2); } +static void __nvoc_thunk_KernelCrashCatEngine_gkflcnReadEmem(struct GenericKernelFalcon *arg0, NvU64 offset, NvU64 size, void *pBuf) { + kcrashcatEngineReadEmem((struct KernelCrashCatEngine *)(((unsigned char *)arg0) + __nvoc_rtti_GenericKernelFalcon_KernelCrashCatEngine.offset), offset, size, pBuf); +} + +static NvU32 __nvoc_thunk_KernelCrashCatEngine_gkflcnGetWFL0Offset(struct GenericKernelFalcon *arg0) { + return kcrashcatEngineGetWFL0Offset((struct KernelCrashCatEngine *)(((unsigned char *)arg0) + __nvoc_rtti_GenericKernelFalcon_KernelCrashCatEngine.offset)); +} + +static void __nvoc_thunk_KernelCrashCatEngine_gkflcnUnload(struct GenericKernelFalcon *arg0) { + kcrashcatEngineUnload((struct KernelCrashCatEngine *)(((unsigned char *)arg0) + __nvoc_rtti_GenericKernelFalcon_KernelCrashCatEngine.offset)); +} + +static NvBool __nvoc_thunk_KernelCrashCatEngine_gkflcnConfigured(struct GenericKernelFalcon *arg0) { + return kcrashcatEngineConfigured((struct KernelCrashCatEngine *)(((unsigned char *)arg0) + __nvoc_rtti_GenericKernelFalcon_KernelCrashCatEngine.offset)); +} + +static NvU32 __nvoc_thunk_KernelCrashCatEngine_gkflcnPriRead(struct GenericKernelFalcon *arg0, NvU32 offset) { + return kcrashcatEnginePriRead((struct KernelCrashCatEngine *)(((unsigned char *)arg0) + __nvoc_rtti_GenericKernelFalcon_KernelCrashCatEngine.offset), offset); +} + +static const NvU32 *__nvoc_thunk_KernelCrashCatEngine_gkflcnGetScratchOffsets(struct GenericKernelFalcon *arg0, NV_CRASHCAT_SCRATCH_GROUP_ID scratchGroupId) { + return kcrashcatEngineGetScratchOffsets((struct KernelCrashCatEngine *)(((unsigned char *)arg0) + __nvoc_rtti_GenericKernelFalcon_KernelCrashCatEngine.offset), scratchGroupId); +} + +static void __nvoc_thunk_KernelFalcon_gkflcnRegWrite(struct OBJGPU *pGpu, struct GenericKernelFalcon *pKernelFlcn, NvU32 offset, NvU32 data) { + kflcnRegWrite(pGpu, (struct KernelFalcon *)(((unsigned char *)pKernelFlcn) + __nvoc_rtti_GenericKernelFalcon_KernelFalcon.offset), offset, data); +} + +static NvU32 __nvoc_thunk_KernelFalcon_gkflcnMaskDmemAddr(struct OBJGPU *pGpu, struct GenericKernelFalcon *pKernelFlcn, NvU32 addr) { + return kflcnMaskDmemAddr(pGpu, (struct KernelFalcon *)(((unsigned char *)pKernelFlcn) + __nvoc_rtti_GenericKernelFalcon_KernelFalcon.offset), addr); +} + +static void __nvoc_thunk_KernelCrashCatEngine_gkflcnVprintf(struct GenericKernelFalcon *arg0, NvBool bReportStart, const char *fmt, va_list args) { + kcrashcatEngineVprintf((struct KernelCrashCatEngine *)(((unsigned char *)arg0) + __nvoc_rtti_GenericKernelFalcon_KernelCrashCatEngine.offset), bReportStart, fmt, args); +} + static NvBool __nvoc_thunk_IntrService_gkflcnClearInterrupt(struct OBJGPU *pGpu, struct GenericKernelFalcon *pIntrService, IntrServiceClearInterruptArguments *pParams) { return intrservClearInterrupt(pGpu, (struct IntrService *)(((unsigned char *)pIntrService) + __nvoc_rtti_GenericKernelFalcon_IntrService.offset), pParams); } +static void __nvoc_thunk_KernelCrashCatEngine_gkflcnPriWrite(struct GenericKernelFalcon *arg0, NvU32 offset, NvU32 data) { + kcrashcatEnginePriWrite((struct KernelCrashCatEngine *)(((unsigned char *)arg0) + __nvoc_rtti_GenericKernelFalcon_KernelCrashCatEngine.offset), offset, data); +} + +static void *__nvoc_thunk_KernelCrashCatEngine_gkflcnMapBufferDescriptor(struct GenericKernelFalcon *arg0, CrashCatBufferDescriptor *pBufDesc) { + return kcrashcatEngineMapBufferDescriptor((struct KernelCrashCatEngine *)(((unsigned char *)arg0) + __nvoc_rtti_GenericKernelFalcon_KernelCrashCatEngine.offset), pBufDesc); +} + +static void __nvoc_thunk_KernelCrashCatEngine_gkflcnSyncBufferDescriptor(struct GenericKernelFalcon *arg0, CrashCatBufferDescriptor *pBufDesc, NvU32 offset, NvU32 size) { + kcrashcatEngineSyncBufferDescriptor((struct KernelCrashCatEngine *)(((unsigned char *)arg0) + __nvoc_rtti_GenericKernelFalcon_KernelCrashCatEngine.offset), pBufDesc, offset, size); +} + +static NvU32 __nvoc_thunk_KernelFalcon_gkflcnRegRead(struct OBJGPU *pGpu, struct GenericKernelFalcon *pKernelFlcn, NvU32 offset) { + return kflcnRegRead(pGpu, (struct KernelFalcon *)(((unsigned char *)pKernelFlcn) + __nvoc_rtti_GenericKernelFalcon_KernelFalcon.offset), offset); +} + +static void __nvoc_thunk_KernelCrashCatEngine_gkflcnUnmapBufferDescriptor(struct GenericKernelFalcon *arg0, CrashCatBufferDescriptor *pBufDesc) { + kcrashcatEngineUnmapBufferDescriptor((struct KernelCrashCatEngine *)(((unsigned char *)arg0) + __nvoc_rtti_GenericKernelFalcon_KernelCrashCatEngine.offset), pBufDesc); +} + static NvU32 __nvoc_thunk_IntrService_gkflcnServiceInterrupt(struct OBJGPU *pGpu, struct GenericKernelFalcon *pIntrService, IntrServiceServiceInterruptArguments *pParams) { return intrservServiceInterrupt(pGpu, (struct IntrService *)(((unsigned char *)pIntrService) + __nvoc_rtti_GenericKernelFalcon_IntrService.offset), pParams); } +static void __nvoc_thunk_KernelCrashCatEngine_gkflcnReadDmem(struct GenericKernelFalcon *arg0, NvU32 offset, NvU32 size, void *pBuf) { + kcrashcatEngineReadDmem((struct KernelCrashCatEngine *)(((unsigned char *)arg0) + __nvoc_rtti_GenericKernelFalcon_KernelCrashCatEngine.offset), offset, size, pBuf); +} + const struct NVOC_EXPORT_INFO __nvoc_export_info_GenericKernelFalcon = { /*numEntries=*/ 0, @@ -375,23 +543,49 @@ pThis->__gkflcnResetHw__ = &gkflcnResetHw_IMPL; - pThis->__gkflcnIsEngineInReset__ = &gkflcnIsEngineInReset_IMPL; - pThis->__gkflcnRegisterIntrService__ = &gkflcnRegisterIntrService_IMPL; pThis->__gkflcnServiceNotificationInterrupt__ = &gkflcnServiceNotificationInterrupt_IMPL; pThis->__nvoc_base_KernelFalcon.__kflcnResetHw__ = &__nvoc_thunk_GenericKernelFalcon_kflcnResetHw; - pThis->__nvoc_base_KernelFalcon.__kflcnIsEngineInReset__ = &__nvoc_thunk_GenericKernelFalcon_kflcnIsEngineInReset; - pThis->__nvoc_base_IntrService.__intrservRegisterIntrService__ = &__nvoc_thunk_GenericKernelFalcon_intrservRegisterIntrService; pThis->__nvoc_base_IntrService.__intrservServiceNotificationInterrupt__ = &__nvoc_thunk_GenericKernelFalcon_intrservServiceNotificationInterrupt; + pThis->__gkflcnReadEmem__ = &__nvoc_thunk_KernelCrashCatEngine_gkflcnReadEmem; + + pThis->__gkflcnGetWFL0Offset__ = &__nvoc_thunk_KernelCrashCatEngine_gkflcnGetWFL0Offset; + + pThis->__gkflcnUnload__ = &__nvoc_thunk_KernelCrashCatEngine_gkflcnUnload; + + pThis->__gkflcnConfigured__ = &__nvoc_thunk_KernelCrashCatEngine_gkflcnConfigured; + + pThis->__gkflcnPriRead__ = &__nvoc_thunk_KernelCrashCatEngine_gkflcnPriRead; + + pThis->__gkflcnGetScratchOffsets__ = &__nvoc_thunk_KernelCrashCatEngine_gkflcnGetScratchOffsets; + + pThis->__gkflcnRegWrite__ = &__nvoc_thunk_KernelFalcon_gkflcnRegWrite; + + pThis->__gkflcnMaskDmemAddr__ = &__nvoc_thunk_KernelFalcon_gkflcnMaskDmemAddr; + + pThis->__gkflcnVprintf__ = &__nvoc_thunk_KernelCrashCatEngine_gkflcnVprintf; + pThis->__gkflcnClearInterrupt__ = &__nvoc_thunk_IntrService_gkflcnClearInterrupt; + pThis->__gkflcnPriWrite__ = &__nvoc_thunk_KernelCrashCatEngine_gkflcnPriWrite; + + pThis->__gkflcnMapBufferDescriptor__ = &__nvoc_thunk_KernelCrashCatEngine_gkflcnMapBufferDescriptor; + + pThis->__gkflcnSyncBufferDescriptor__ = &__nvoc_thunk_KernelCrashCatEngine_gkflcnSyncBufferDescriptor; + + pThis->__gkflcnRegRead__ = &__nvoc_thunk_KernelFalcon_gkflcnRegRead; + + pThis->__gkflcnUnmapBufferDescriptor__ = &__nvoc_thunk_KernelCrashCatEngine_gkflcnUnmapBufferDescriptor; + pThis->__gkflcnServiceInterrupt__ = &__nvoc_thunk_IntrService_gkflcnServiceInterrupt; + + pThis->__gkflcnReadDmem__ = &__nvoc_thunk_KernelCrashCatEngine_gkflcnReadDmem; } void __nvoc_init_funcTable_GenericKernelFalcon(GenericKernelFalcon *pThis) { @@ -403,6 +597,8 @@ void __nvoc_init_Object(Object*); void __nvoc_init_GenericKernelFalcon(GenericKernelFalcon *pThis, RmHalspecOwner *pRmhalspecowner) { pThis->__nvoc_pbase_GenericKernelFalcon = pThis; + pThis->__nvoc_pbase_CrashCatEngine = &pThis->__nvoc_base_KernelFalcon.__nvoc_base_KernelCrashCatEngine.__nvoc_base_CrashCatEngine; + pThis->__nvoc_pbase_KernelCrashCatEngine = &pThis->__nvoc_base_KernelFalcon.__nvoc_base_KernelCrashCatEngine; pThis->__nvoc_pbase_KernelFalcon = &pThis->__nvoc_base_KernelFalcon; pThis->__nvoc_pbase_IntrService = &pThis->__nvoc_base_IntrService; pThis->__nvoc_pbase_Object = &pThis->__nvoc_base_Object; @@ -418,13 +614,16 @@ GenericKernelFalcon *pThis; RmHalspecOwner *pRmhalspecowner; - pThis = portMemAllocNonPaged(sizeof(GenericKernelFalcon)); - if (pThis == NULL) return NV_ERR_NO_MEMORY; + status = __nvoc_handleObjCreateMemAlloc(createFlags, sizeof(GenericKernelFalcon), (void**)&pThis, (void**)ppThis); + if (status != NV_OK) + return status; portMemSet(pThis, 0, sizeof(GenericKernelFalcon)); __nvoc_initRtti(staticCast(pThis, Dynamic), &__nvoc_class_def_GenericKernelFalcon); + pThis->__nvoc_base_Object.createFlags = createFlags; + if (pParent != NULL && !(createFlags & NVOC_OBJ_CREATE_FLAGS_PARENT_HALSPEC_ONLY)) { pParentObj = dynamicCast(pParent, Object); @@ -444,11 +643,17 @@ if (status != NV_OK) goto __nvoc_objCreate_GenericKernelFalcon_cleanup; *ppThis = pThis; + return NV_OK; __nvoc_objCreate_GenericKernelFalcon_cleanup: // do not call destructors here since the constructor already called them - portMemFree(pThis); + if (createFlags & NVOC_OBJ_CREATE_FLAGS_IN_PLACE_CONSTRUCT) + portMemSet(pThis, 0, sizeof(GenericKernelFalcon)); + else + portMemFree(pThis); + + // coverity[leaked_storage:FALSE] return status; } diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/generated/g_kernel_falcon_nvoc.h nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_kernel_falcon_nvoc.h --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/generated/g_kernel_falcon_nvoc.h 2023-10-25 20:27:07.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_kernel_falcon_nvoc.h 2024-03-05 22:18:26.000000000 +0000 @@ -41,6 +41,7 @@ #include "core/core.h" #include "gpu/falcon/falcon_common.h" +#include "gpu/falcon/kernel_crashcat_engine.h" #include "gpu/intr/intr_service.h" struct KernelChannel; @@ -67,6 +68,8 @@ NvU32 ctxAttr; // Memory attributes used for context buffers NvU32 ctxBufferSize; // Context buffer size in bytes NvU32 addrSpaceList; // index into ADDRLIST array in mem_desc.h + + KernelCrashCatEngineConfig crashcatEngConfig; } KernelFalconEngineConfig; /*! @@ -79,18 +82,34 @@ #endif struct KernelFalcon { const struct NVOC_RTTI *__nvoc_rtti; + struct KernelCrashCatEngine __nvoc_base_KernelCrashCatEngine; + struct CrashCatEngine *__nvoc_pbase_CrashCatEngine; + struct KernelCrashCatEngine *__nvoc_pbase_KernelCrashCatEngine; struct KernelFalcon *__nvoc_pbase_KernelFalcon; + NvU32 (*__kflcnRegRead__)(struct OBJGPU *, struct KernelFalcon *, NvU32); + void (*__kflcnRegWrite__)(struct OBJGPU *, struct KernelFalcon *, NvU32, NvU32); NvBool (*__kflcnIsRiscvActive__)(struct OBJGPU *, struct KernelFalcon *); void (*__kflcnRiscvProgramBcr__)(struct OBJGPU *, struct KernelFalcon *, NvBool); void (*__kflcnSwitchToFalcon__)(struct OBJGPU *, struct KernelFalcon *); NV_STATUS (*__kflcnResetHw__)(struct OBJGPU *, struct KernelFalcon *); NV_STATUS (*__kflcnPreResetWait__)(struct OBJGPU *, struct KernelFalcon *); NV_STATUS (*__kflcnWaitForResetToFinish__)(struct OBJGPU *, struct KernelFalcon *); - NvBool (*__kflcnIsEngineInReset__)(struct OBJGPU *, struct KernelFalcon *); NvU32 (*__kflcnReadIntrStatus__)(struct OBJGPU *, struct KernelFalcon *); void (*__kflcnIntrRetrigger__)(struct OBJGPU *, struct KernelFalcon *); NvU32 (*__kflcnMaskImemAddr__)(struct OBJGPU *, struct KernelFalcon *, NvU32); NvU32 (*__kflcnMaskDmemAddr__)(struct OBJGPU *, struct KernelFalcon *, NvU32); + void (*__kflcnReadEmem__)(struct KernelFalcon *, NvU64, NvU64, void *); + NvU32 (*__kflcnGetWFL0Offset__)(struct KernelFalcon *); + const NvU32 *(*__kflcnGetScratchOffsets__)(struct KernelFalcon *, NV_CRASHCAT_SCRATCH_GROUP_ID); + void (*__kflcnUnload__)(struct KernelFalcon *); + NvBool (*__kflcnConfigured__)(struct KernelFalcon *); + NvU32 (*__kflcnPriRead__)(struct KernelFalcon *, NvU32); + void (*__kflcnVprintf__)(struct KernelFalcon *, NvBool, const char *, va_list); + void (*__kflcnPriWrite__)(struct KernelFalcon *, NvU32, NvU32); + void (*__kflcnSyncBufferDescriptor__)(struct KernelFalcon *, CrashCatBufferDescriptor *, NvU32, NvU32); + void *(*__kflcnMapBufferDescriptor__)(struct KernelFalcon *, CrashCatBufferDescriptor *); + void (*__kflcnUnmapBufferDescriptor__)(struct KernelFalcon *, CrashCatBufferDescriptor *); + void (*__kflcnReadDmem__)(struct KernelFalcon *, NvU32, NvU32, void *); NvU32 registerBase; NvU32 riscvRegisterBase; NvU32 fbifBase; @@ -131,6 +150,10 @@ #define __objCreate_KernelFalcon(ppNewObj, pParent, createFlags) \ __nvoc_objCreate_KernelFalcon((ppNewObj), staticCast((pParent), Dynamic), (createFlags)) +#define kflcnRegRead(pGpu, pKernelFlcn, offset) kflcnRegRead_DISPATCH(pGpu, pKernelFlcn, offset) +#define kflcnRegRead_HAL(pGpu, pKernelFlcn, offset) kflcnRegRead_DISPATCH(pGpu, pKernelFlcn, offset) +#define kflcnRegWrite(pGpu, pKernelFlcn, offset, data) kflcnRegWrite_DISPATCH(pGpu, pKernelFlcn, offset, data) +#define kflcnRegWrite_HAL(pGpu, pKernelFlcn, offset, data) kflcnRegWrite_DISPATCH(pGpu, pKernelFlcn, offset, data) #define kflcnIsRiscvActive(pGpu, pKernelFlcn) kflcnIsRiscvActive_DISPATCH(pGpu, pKernelFlcn) #define kflcnIsRiscvActive_HAL(pGpu, pKernelFlcn) kflcnIsRiscvActive_DISPATCH(pGpu, pKernelFlcn) #define kflcnRiscvProgramBcr(pGpu, pKernelFlcn, bBRFetch) kflcnRiscvProgramBcr_DISPATCH(pGpu, pKernelFlcn, bBRFetch) @@ -142,7 +165,6 @@ #define kflcnPreResetWait_HAL(pGpu, pKernelFlcn) kflcnPreResetWait_DISPATCH(pGpu, pKernelFlcn) #define kflcnWaitForResetToFinish(pGpu, pKernelFlcn) kflcnWaitForResetToFinish_DISPATCH(pGpu, pKernelFlcn) #define kflcnWaitForResetToFinish_HAL(pGpu, pKernelFlcn) kflcnWaitForResetToFinish_DISPATCH(pGpu, pKernelFlcn) -#define kflcnIsEngineInReset(pGpu, pKernelFlcn) kflcnIsEngineInReset_DISPATCH(pGpu, pKernelFlcn) #define kflcnReadIntrStatus(pGpu, pKerneFlcn) kflcnReadIntrStatus_DISPATCH(pGpu, pKerneFlcn) #define kflcnReadIntrStatus_HAL(pGpu, pKerneFlcn) kflcnReadIntrStatus_DISPATCH(pGpu, pKerneFlcn) #define kflcnIntrRetrigger(pGpu, pKernelFlcn) kflcnIntrRetrigger_DISPATCH(pGpu, pKernelFlcn) @@ -151,33 +173,18 @@ #define kflcnMaskImemAddr_HAL(pGpu, pKernelFlcn, addr) kflcnMaskImemAddr_DISPATCH(pGpu, pKernelFlcn, addr) #define kflcnMaskDmemAddr(pGpu, pKernelFlcn, addr) kflcnMaskDmemAddr_DISPATCH(pGpu, pKernelFlcn, addr) #define kflcnMaskDmemAddr_HAL(pGpu, pKernelFlcn, addr) kflcnMaskDmemAddr_DISPATCH(pGpu, pKernelFlcn, addr) -NvU32 kflcnRegRead_TU102(struct OBJGPU *pGpu, struct KernelFalcon *pKernelFlcn, NvU32 offset); - - -#ifdef __nvoc_kernel_falcon_h_disabled -static inline NvU32 kflcnRegRead(struct OBJGPU *pGpu, struct KernelFalcon *pKernelFlcn, NvU32 offset) { - NV_ASSERT_FAILED_PRECOMP("KernelFalcon was disabled!"); - return 0; -} -#else //__nvoc_kernel_falcon_h_disabled -#define kflcnRegRead(pGpu, pKernelFlcn, offset) kflcnRegRead_TU102(pGpu, pKernelFlcn, offset) -#endif //__nvoc_kernel_falcon_h_disabled - -#define kflcnRegRead_HAL(pGpu, pKernelFlcn, offset) kflcnRegRead(pGpu, pKernelFlcn, offset) - -void kflcnRegWrite_TU102(struct OBJGPU *pGpu, struct KernelFalcon *pKernelFlcn, NvU32 offset, NvU32 data); - - -#ifdef __nvoc_kernel_falcon_h_disabled -static inline void kflcnRegWrite(struct OBJGPU *pGpu, struct KernelFalcon *pKernelFlcn, NvU32 offset, NvU32 data) { - NV_ASSERT_FAILED_PRECOMP("KernelFalcon was disabled!"); -} -#else //__nvoc_kernel_falcon_h_disabled -#define kflcnRegWrite(pGpu, pKernelFlcn, offset, data) kflcnRegWrite_TU102(pGpu, pKernelFlcn, offset, data) -#endif //__nvoc_kernel_falcon_h_disabled - -#define kflcnRegWrite_HAL(pGpu, pKernelFlcn, offset, data) kflcnRegWrite(pGpu, pKernelFlcn, offset, data) - +#define kflcnReadEmem(arg0, offset, size, pBuf) kflcnReadEmem_DISPATCH(arg0, offset, size, pBuf) +#define kflcnGetWFL0Offset(arg0) kflcnGetWFL0Offset_DISPATCH(arg0) +#define kflcnGetScratchOffsets(arg0, scratchGroupId) kflcnGetScratchOffsets_DISPATCH(arg0, scratchGroupId) +#define kflcnUnload(arg0) kflcnUnload_DISPATCH(arg0) +#define kflcnConfigured(arg0) kflcnConfigured_DISPATCH(arg0) +#define kflcnPriRead(arg0, offset) kflcnPriRead_DISPATCH(arg0, offset) +#define kflcnVprintf(arg0, bReportStart, fmt, args) kflcnVprintf_DISPATCH(arg0, bReportStart, fmt, args) +#define kflcnPriWrite(arg0, offset, data) kflcnPriWrite_DISPATCH(arg0, offset, data) +#define kflcnSyncBufferDescriptor(arg0, pBufDesc, offset, size) kflcnSyncBufferDescriptor_DISPATCH(arg0, pBufDesc, offset, size) +#define kflcnMapBufferDescriptor(arg0, pBufDesc) kflcnMapBufferDescriptor_DISPATCH(arg0, pBufDesc) +#define kflcnUnmapBufferDescriptor(arg0, pBufDesc) kflcnUnmapBufferDescriptor_DISPATCH(arg0, pBufDesc) +#define kflcnReadDmem(arg0, offset, size, pBuf) kflcnReadDmem_DISPATCH(arg0, offset, size, pBuf) NvU32 kflcnRiscvRegRead_TU102(struct OBJGPU *pGpu, struct KernelFalcon *pKernelFlcn, NvU32 offset); @@ -298,6 +305,18 @@ #define kflcnWaitForHalt_HAL(pGpu, pKernelFlcn, timeoutUs, flags) kflcnWaitForHalt(pGpu, pKernelFlcn, timeoutUs, flags) +NvU32 kflcnRegRead_TU102(struct OBJGPU *pGpu, struct KernelFalcon *pKernelFlcn, NvU32 offset); + +static inline NvU32 kflcnRegRead_DISPATCH(struct OBJGPU *pGpu, struct KernelFalcon *pKernelFlcn, NvU32 offset) { + return pKernelFlcn->__kflcnRegRead__(pGpu, pKernelFlcn, offset); +} + +void kflcnRegWrite_TU102(struct OBJGPU *pGpu, struct KernelFalcon *pKernelFlcn, NvU32 offset, NvU32 data); + +static inline void kflcnRegWrite_DISPATCH(struct OBJGPU *pGpu, struct KernelFalcon *pKernelFlcn, NvU32 offset, NvU32 data) { + pKernelFlcn->__kflcnRegWrite__(pGpu, pKernelFlcn, offset, data); +} + NvBool kflcnIsRiscvActive_TU102(struct OBJGPU *pGpu, struct KernelFalcon *pKernelFlcn); NvBool kflcnIsRiscvActive_GA10X(struct OBJGPU *pGpu, struct KernelFalcon *pKernelFlcn); @@ -348,10 +367,6 @@ return pKernelFlcn->__kflcnWaitForResetToFinish__(pGpu, pKernelFlcn); } -static inline NvBool kflcnIsEngineInReset_DISPATCH(struct OBJGPU *pGpu, struct KernelFalcon *pKernelFlcn) { - return pKernelFlcn->__kflcnIsEngineInReset__(pGpu, pKernelFlcn); -} - NvU32 kflcnReadIntrStatus_TU102(struct OBJGPU *pGpu, struct KernelFalcon *pKerneFlcn); NvU32 kflcnReadIntrStatus_GA102(struct OBJGPU *pGpu, struct KernelFalcon *pKerneFlcn); @@ -386,6 +401,54 @@ return pKernelFlcn->__kflcnMaskDmemAddr__(pGpu, pKernelFlcn, addr); } +static inline void kflcnReadEmem_DISPATCH(struct KernelFalcon *arg0, NvU64 offset, NvU64 size, void *pBuf) { + arg0->__kflcnReadEmem__(arg0, offset, size, pBuf); +} + +static inline NvU32 kflcnGetWFL0Offset_DISPATCH(struct KernelFalcon *arg0) { + return arg0->__kflcnGetWFL0Offset__(arg0); +} + +static inline const NvU32 *kflcnGetScratchOffsets_DISPATCH(struct KernelFalcon *arg0, NV_CRASHCAT_SCRATCH_GROUP_ID scratchGroupId) { + return arg0->__kflcnGetScratchOffsets__(arg0, scratchGroupId); +} + +static inline void kflcnUnload_DISPATCH(struct KernelFalcon *arg0) { + arg0->__kflcnUnload__(arg0); +} + +static inline NvBool kflcnConfigured_DISPATCH(struct KernelFalcon *arg0) { + return arg0->__kflcnConfigured__(arg0); +} + +static inline NvU32 kflcnPriRead_DISPATCH(struct KernelFalcon *arg0, NvU32 offset) { + return arg0->__kflcnPriRead__(arg0, offset); +} + +static inline void kflcnVprintf_DISPATCH(struct KernelFalcon *arg0, NvBool bReportStart, const char *fmt, va_list args) { + arg0->__kflcnVprintf__(arg0, bReportStart, fmt, args); +} + +static inline void kflcnPriWrite_DISPATCH(struct KernelFalcon *arg0, NvU32 offset, NvU32 data) { + arg0->__kflcnPriWrite__(arg0, offset, data); +} + +static inline void kflcnSyncBufferDescriptor_DISPATCH(struct KernelFalcon *arg0, CrashCatBufferDescriptor *pBufDesc, NvU32 offset, NvU32 size) { + arg0->__kflcnSyncBufferDescriptor__(arg0, pBufDesc, offset, size); +} + +static inline void *kflcnMapBufferDescriptor_DISPATCH(struct KernelFalcon *arg0, CrashCatBufferDescriptor *pBufDesc) { + return arg0->__kflcnMapBufferDescriptor__(arg0, pBufDesc); +} + +static inline void kflcnUnmapBufferDescriptor_DISPATCH(struct KernelFalcon *arg0, CrashCatBufferDescriptor *pBufDesc) { + arg0->__kflcnUnmapBufferDescriptor__(arg0, pBufDesc); +} + +static inline void kflcnReadDmem_DISPATCH(struct KernelFalcon *arg0, NvU32 offset, NvU32 size, void *pBuf) { + arg0->__kflcnReadDmem__(arg0, offset, size, pBuf); +} + void kflcnConfigureEngine_IMPL(struct OBJGPU *pGpu, struct KernelFalcon *pKernelFalcon, KernelFalconEngineConfig *pFalconConfig); #ifdef __nvoc_kernel_falcon_h_disabled @@ -435,16 +498,32 @@ struct KernelFalcon __nvoc_base_KernelFalcon; struct IntrService __nvoc_base_IntrService; struct Object __nvoc_base_Object; + struct CrashCatEngine *__nvoc_pbase_CrashCatEngine; + struct KernelCrashCatEngine *__nvoc_pbase_KernelCrashCatEngine; struct KernelFalcon *__nvoc_pbase_KernelFalcon; struct IntrService *__nvoc_pbase_IntrService; struct Object *__nvoc_pbase_Object; struct GenericKernelFalcon *__nvoc_pbase_GenericKernelFalcon; NV_STATUS (*__gkflcnResetHw__)(struct OBJGPU *, struct GenericKernelFalcon *); - NvBool (*__gkflcnIsEngineInReset__)(struct OBJGPU *, struct GenericKernelFalcon *); void (*__gkflcnRegisterIntrService__)(struct OBJGPU *, struct GenericKernelFalcon *, IntrServiceRecord *); NV_STATUS (*__gkflcnServiceNotificationInterrupt__)(struct OBJGPU *, struct GenericKernelFalcon *, IntrServiceServiceNotificationInterruptArguments *); + void (*__gkflcnReadEmem__)(struct GenericKernelFalcon *, NvU64, NvU64, void *); + NvU32 (*__gkflcnGetWFL0Offset__)(struct GenericKernelFalcon *); + void (*__gkflcnUnload__)(struct GenericKernelFalcon *); + NvBool (*__gkflcnConfigured__)(struct GenericKernelFalcon *); + NvU32 (*__gkflcnPriRead__)(struct GenericKernelFalcon *, NvU32); + const NvU32 *(*__gkflcnGetScratchOffsets__)(struct GenericKernelFalcon *, NV_CRASHCAT_SCRATCH_GROUP_ID); + void (*__gkflcnRegWrite__)(struct OBJGPU *, struct GenericKernelFalcon *, NvU32, NvU32); + NvU32 (*__gkflcnMaskDmemAddr__)(struct OBJGPU *, struct GenericKernelFalcon *, NvU32); + void (*__gkflcnVprintf__)(struct GenericKernelFalcon *, NvBool, const char *, va_list); NvBool (*__gkflcnClearInterrupt__)(struct OBJGPU *, struct GenericKernelFalcon *, IntrServiceClearInterruptArguments *); + void (*__gkflcnPriWrite__)(struct GenericKernelFalcon *, NvU32, NvU32); + void *(*__gkflcnMapBufferDescriptor__)(struct GenericKernelFalcon *, CrashCatBufferDescriptor *); + void (*__gkflcnSyncBufferDescriptor__)(struct GenericKernelFalcon *, CrashCatBufferDescriptor *, NvU32, NvU32); + NvU32 (*__gkflcnRegRead__)(struct OBJGPU *, struct GenericKernelFalcon *, NvU32); + void (*__gkflcnUnmapBufferDescriptor__)(struct GenericKernelFalcon *, CrashCatBufferDescriptor *); NvU32 (*__gkflcnServiceInterrupt__)(struct OBJGPU *, struct GenericKernelFalcon *, IntrServiceServiceInterruptArguments *); + void (*__gkflcnReadDmem__)(struct GenericKernelFalcon *, NvU32, NvU32, void *); }; #ifndef __NVOC_CLASS_GenericKernelFalcon_TYPEDEF__ @@ -476,26 +555,34 @@ __nvoc_objCreate_GenericKernelFalcon((ppNewObj), staticCast((pParent), Dynamic), (createFlags), arg_pGpu, arg_pFalconConfig) #define gkflcnResetHw(pGpu, pGenKernFlcn) gkflcnResetHw_DISPATCH(pGpu, pGenKernFlcn) -#define gkflcnIsEngineInReset(pGpu, pGenKernFlcn) gkflcnIsEngineInReset_DISPATCH(pGpu, pGenKernFlcn) #define gkflcnRegisterIntrService(arg0, arg1, arg2) gkflcnRegisterIntrService_DISPATCH(arg0, arg1, arg2) #define gkflcnServiceNotificationInterrupt(arg0, arg1, arg2) gkflcnServiceNotificationInterrupt_DISPATCH(arg0, arg1, arg2) +#define gkflcnReadEmem(arg0, offset, size, pBuf) gkflcnReadEmem_DISPATCH(arg0, offset, size, pBuf) +#define gkflcnGetWFL0Offset(arg0) gkflcnGetWFL0Offset_DISPATCH(arg0) +#define gkflcnUnload(arg0) gkflcnUnload_DISPATCH(arg0) +#define gkflcnConfigured(arg0) gkflcnConfigured_DISPATCH(arg0) +#define gkflcnPriRead(arg0, offset) gkflcnPriRead_DISPATCH(arg0, offset) +#define gkflcnGetScratchOffsets(arg0, scratchGroupId) gkflcnGetScratchOffsets_DISPATCH(arg0, scratchGroupId) +#define gkflcnRegWrite(pGpu, pKernelFlcn, offset, data) gkflcnRegWrite_DISPATCH(pGpu, pKernelFlcn, offset, data) +#define gkflcnMaskDmemAddr(pGpu, pKernelFlcn, addr) gkflcnMaskDmemAddr_DISPATCH(pGpu, pKernelFlcn, addr) +#define gkflcnVprintf(arg0, bReportStart, fmt, args) gkflcnVprintf_DISPATCH(arg0, bReportStart, fmt, args) #define gkflcnClearInterrupt(pGpu, pIntrService, pParams) gkflcnClearInterrupt_DISPATCH(pGpu, pIntrService, pParams) +#define gkflcnPriWrite(arg0, offset, data) gkflcnPriWrite_DISPATCH(arg0, offset, data) +#define gkflcnMapBufferDescriptor(arg0, pBufDesc) gkflcnMapBufferDescriptor_DISPATCH(arg0, pBufDesc) +#define gkflcnSyncBufferDescriptor(arg0, pBufDesc, offset, size) gkflcnSyncBufferDescriptor_DISPATCH(arg0, pBufDesc, offset, size) +#define gkflcnRegRead(pGpu, pKernelFlcn, offset) gkflcnRegRead_DISPATCH(pGpu, pKernelFlcn, offset) +#define gkflcnUnmapBufferDescriptor(arg0, pBufDesc) gkflcnUnmapBufferDescriptor_DISPATCH(arg0, pBufDesc) #define gkflcnServiceInterrupt(pGpu, pIntrService, pParams) gkflcnServiceInterrupt_DISPATCH(pGpu, pIntrService, pParams) +#define gkflcnReadDmem(arg0, offset, size, pBuf) gkflcnReadDmem_DISPATCH(arg0, offset, size, pBuf) NV_STATUS gkflcnResetHw_IMPL(struct OBJGPU *pGpu, struct GenericKernelFalcon *pGenKernFlcn); static inline NV_STATUS gkflcnResetHw_DISPATCH(struct OBJGPU *pGpu, struct GenericKernelFalcon *pGenKernFlcn) { return pGenKernFlcn->__gkflcnResetHw__(pGpu, pGenKernFlcn); } -NvBool gkflcnIsEngineInReset_IMPL(struct OBJGPU *pGpu, struct GenericKernelFalcon *pGenKernFlcn); +void gkflcnRegisterIntrService_IMPL(struct OBJGPU *arg0, struct GenericKernelFalcon *arg1, IntrServiceRecord arg2[167]); -static inline NvBool gkflcnIsEngineInReset_DISPATCH(struct OBJGPU *pGpu, struct GenericKernelFalcon *pGenKernFlcn) { - return pGenKernFlcn->__gkflcnIsEngineInReset__(pGpu, pGenKernFlcn); -} - -void gkflcnRegisterIntrService_IMPL(struct OBJGPU *arg0, struct GenericKernelFalcon *arg1, IntrServiceRecord arg2[163]); - -static inline void gkflcnRegisterIntrService_DISPATCH(struct OBJGPU *arg0, struct GenericKernelFalcon *arg1, IntrServiceRecord arg2[163]) { +static inline void gkflcnRegisterIntrService_DISPATCH(struct OBJGPU *arg0, struct GenericKernelFalcon *arg1, IntrServiceRecord arg2[167]) { arg1->__gkflcnRegisterIntrService__(arg0, arg1, arg2); } @@ -505,14 +592,74 @@ return arg1->__gkflcnServiceNotificationInterrupt__(arg0, arg1, arg2); } +static inline void gkflcnReadEmem_DISPATCH(struct GenericKernelFalcon *arg0, NvU64 offset, NvU64 size, void *pBuf) { + arg0->__gkflcnReadEmem__(arg0, offset, size, pBuf); +} + +static inline NvU32 gkflcnGetWFL0Offset_DISPATCH(struct GenericKernelFalcon *arg0) { + return arg0->__gkflcnGetWFL0Offset__(arg0); +} + +static inline void gkflcnUnload_DISPATCH(struct GenericKernelFalcon *arg0) { + arg0->__gkflcnUnload__(arg0); +} + +static inline NvBool gkflcnConfigured_DISPATCH(struct GenericKernelFalcon *arg0) { + return arg0->__gkflcnConfigured__(arg0); +} + +static inline NvU32 gkflcnPriRead_DISPATCH(struct GenericKernelFalcon *arg0, NvU32 offset) { + return arg0->__gkflcnPriRead__(arg0, offset); +} + +static inline const NvU32 *gkflcnGetScratchOffsets_DISPATCH(struct GenericKernelFalcon *arg0, NV_CRASHCAT_SCRATCH_GROUP_ID scratchGroupId) { + return arg0->__gkflcnGetScratchOffsets__(arg0, scratchGroupId); +} + +static inline void gkflcnRegWrite_DISPATCH(struct OBJGPU *pGpu, struct GenericKernelFalcon *pKernelFlcn, NvU32 offset, NvU32 data) { + pKernelFlcn->__gkflcnRegWrite__(pGpu, pKernelFlcn, offset, data); +} + +static inline NvU32 gkflcnMaskDmemAddr_DISPATCH(struct OBJGPU *pGpu, struct GenericKernelFalcon *pKernelFlcn, NvU32 addr) { + return pKernelFlcn->__gkflcnMaskDmemAddr__(pGpu, pKernelFlcn, addr); +} + +static inline void gkflcnVprintf_DISPATCH(struct GenericKernelFalcon *arg0, NvBool bReportStart, const char *fmt, va_list args) { + arg0->__gkflcnVprintf__(arg0, bReportStart, fmt, args); +} + static inline NvBool gkflcnClearInterrupt_DISPATCH(struct OBJGPU *pGpu, struct GenericKernelFalcon *pIntrService, IntrServiceClearInterruptArguments *pParams) { return pIntrService->__gkflcnClearInterrupt__(pGpu, pIntrService, pParams); } +static inline void gkflcnPriWrite_DISPATCH(struct GenericKernelFalcon *arg0, NvU32 offset, NvU32 data) { + arg0->__gkflcnPriWrite__(arg0, offset, data); +} + +static inline void *gkflcnMapBufferDescriptor_DISPATCH(struct GenericKernelFalcon *arg0, CrashCatBufferDescriptor *pBufDesc) { + return arg0->__gkflcnMapBufferDescriptor__(arg0, pBufDesc); +} + +static inline void gkflcnSyncBufferDescriptor_DISPATCH(struct GenericKernelFalcon *arg0, CrashCatBufferDescriptor *pBufDesc, NvU32 offset, NvU32 size) { + arg0->__gkflcnSyncBufferDescriptor__(arg0, pBufDesc, offset, size); +} + +static inline NvU32 gkflcnRegRead_DISPATCH(struct OBJGPU *pGpu, struct GenericKernelFalcon *pKernelFlcn, NvU32 offset) { + return pKernelFlcn->__gkflcnRegRead__(pGpu, pKernelFlcn, offset); +} + +static inline void gkflcnUnmapBufferDescriptor_DISPATCH(struct GenericKernelFalcon *arg0, CrashCatBufferDescriptor *pBufDesc) { + arg0->__gkflcnUnmapBufferDescriptor__(arg0, pBufDesc); +} + static inline NvU32 gkflcnServiceInterrupt_DISPATCH(struct OBJGPU *pGpu, struct GenericKernelFalcon *pIntrService, IntrServiceServiceInterruptArguments *pParams) { return pIntrService->__gkflcnServiceInterrupt__(pGpu, pIntrService, pParams); } +static inline void gkflcnReadDmem_DISPATCH(struct GenericKernelFalcon *arg0, NvU32 offset, NvU32 size, void *pBuf) { + arg0->__gkflcnReadDmem__(arg0, offset, size, pBuf); +} + NV_STATUS gkflcnConstruct_IMPL(struct GenericKernelFalcon *arg_pGenKernFlcn, struct OBJGPU *arg_pGpu, KernelFalconEngineConfig *arg_pFalconConfig); #define __nvoc_gkflcnConstruct(arg_pGenKernFlcn, arg_pGpu, arg_pFalconConfig) gkflcnConstruct_IMPL(arg_pGenKernFlcn, arg_pGpu, arg_pFalconConfig) diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/generated/g_kernel_fifo_nvoc.c nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_kernel_fifo_nvoc.c --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/generated/g_kernel_fifo_nvoc.c 2023-10-25 20:27:07.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_kernel_fifo_nvoc.c 2024-03-05 22:18:26.000000000 +0000 @@ -86,10 +86,6 @@ return kfifoStatePreUnload(pGpu, (struct KernelFifo *)(((unsigned char *)pKernelFifo) - __nvoc_rtti_KernelFifo_OBJENGSTATE.offset), flags); } -static NV_STATUS __nvoc_thunk_OBJENGSTATE_kfifoReconcileTunableState(POBJGPU pGpu, struct KernelFifo *pEngstate, void *pTunableState) { - return engstateReconcileTunableState(pGpu, (struct OBJENGSTATE *)(((unsigned char *)pEngstate) + __nvoc_rtti_KernelFifo_OBJENGSTATE.offset), pTunableState); -} - static NV_STATUS __nvoc_thunk_OBJENGSTATE_kfifoStateLoad(POBJGPU pGpu, struct KernelFifo *pEngstate, NvU32 arg0) { return engstateStateLoad(pGpu, (struct OBJENGSTATE *)(((unsigned char *)pEngstate) + __nvoc_rtti_KernelFifo_OBJENGSTATE.offset), arg0); } @@ -122,26 +118,6 @@ return engstateStatePreInitUnlocked(pGpu, (struct OBJENGSTATE *)(((unsigned char *)pEngstate) + __nvoc_rtti_KernelFifo_OBJENGSTATE.offset)); } -static NV_STATUS __nvoc_thunk_OBJENGSTATE_kfifoGetTunableState(POBJGPU pGpu, struct KernelFifo *pEngstate, void *pTunableState) { - return engstateGetTunableState(pGpu, (struct OBJENGSTATE *)(((unsigned char *)pEngstate) + __nvoc_rtti_KernelFifo_OBJENGSTATE.offset), pTunableState); -} - -static NV_STATUS __nvoc_thunk_OBJENGSTATE_kfifoCompareTunableState(POBJGPU pGpu, struct KernelFifo *pEngstate, void *pTunables1, void *pTunables2) { - return engstateCompareTunableState(pGpu, (struct OBJENGSTATE *)(((unsigned char *)pEngstate) + __nvoc_rtti_KernelFifo_OBJENGSTATE.offset), pTunables1, pTunables2); -} - -static void __nvoc_thunk_OBJENGSTATE_kfifoFreeTunableState(POBJGPU pGpu, struct KernelFifo *pEngstate, void *pTunableState) { - engstateFreeTunableState(pGpu, (struct OBJENGSTATE *)(((unsigned char *)pEngstate) + __nvoc_rtti_KernelFifo_OBJENGSTATE.offset), pTunableState); -} - -static NV_STATUS __nvoc_thunk_OBJENGSTATE_kfifoAllocTunableState(POBJGPU pGpu, struct KernelFifo *pEngstate, void **ppTunableState) { - return engstateAllocTunableState(pGpu, (struct OBJENGSTATE *)(((unsigned char *)pEngstate) + __nvoc_rtti_KernelFifo_OBJENGSTATE.offset), ppTunableState); -} - -static NV_STATUS __nvoc_thunk_OBJENGSTATE_kfifoSetTunableState(POBJGPU pGpu, struct KernelFifo *pEngstate, void *pTunableState) { - return engstateSetTunableState(pGpu, (struct OBJENGSTATE *)(((unsigned char *)pEngstate) + __nvoc_rtti_KernelFifo_OBJENGSTATE.offset), pTunableState); -} - static NvBool __nvoc_thunk_OBJENGSTATE_kfifoIsPresent(POBJGPU pGpu, struct KernelFifo *pEngstate) { return engstateIsPresent(pGpu, (struct OBJENGSTATE *)(((unsigned char *)pEngstate) + __nvoc_rtti_KernelFifo_OBJENGSTATE.offset)); } @@ -231,6 +207,12 @@ { pThis->bIsSchedSupported = ((NvBool)(0 == 0)); } + + pThis->pBar1VF = ((void *)0); + + pThis->pBar1PrivVF = ((void *)0); + + pThis->pRegVF = ((void *)0); } NV_STATUS __nvoc_ctor_OBJENGSTATE(OBJENGSTATE* ); @@ -266,16 +248,10 @@ pThis->__kfifoStateDestroy__ = &kfifoStateDestroy_IMPL; // Hal function -- kfifoStatePostLoad - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x11f0ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 | GH100 */ - { - pThis->__kfifoStatePostLoad__ = &kfifoStatePostLoad_GM107; - } + pThis->__kfifoStatePostLoad__ = &kfifoStatePostLoad_GM107; // Hal function -- kfifoStatePreUnload - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x11f0ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 | GH100 */ - { - pThis->__kfifoStatePreUnload__ = &kfifoStatePreUnload_GM107; - } + pThis->__kfifoStatePreUnload__ = &kfifoStatePreUnload_GM107; // Hal function -- kfifoCheckChannelAllocAddrSpaces if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ @@ -288,24 +264,14 @@ pThis->__kfifoCheckChannelAllocAddrSpaces__ = &kfifoCheckChannelAllocAddrSpaces_56cd7a; } - // Hal function -- kfifoGetMmioUsermodeOffset + // Hal function -- kfifoConstructUsermodeMemdescs if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ { - pThis->__kfifoGetMmioUsermodeOffset__ = &kfifoGetMmioUsermodeOffset_GH100; + pThis->__kfifoConstructUsermodeMemdescs__ = &kfifoConstructUsermodeMemdescs_GH100; } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x01f0ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 */ - { - pThis->__kfifoGetMmioUsermodeOffset__ = &kfifoGetMmioUsermodeOffset_474d46; - } - - // Hal function -- kfifoGetMmioUsermodeSize - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ - { - pThis->__kfifoGetMmioUsermodeSize__ = &kfifoGetMmioUsermodeSize_GH100; - } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x01f0ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 */ + else { - pThis->__kfifoGetMmioUsermodeSize__ = &kfifoGetMmioUsermodeSize_474d46; + pThis->__kfifoConstructUsermodeMemdescs__ = &kfifoConstructUsermodeMemdescs_GV100; } // Hal function -- kfifoChannelGroupGetLocalMaxSubcontext @@ -313,7 +279,7 @@ { pThis->__kfifoChannelGroupGetLocalMaxSubcontext__ = &kfifoChannelGroupGetLocalMaxSubcontext_GM107; } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x11f0fc00UL) )) /* ChipHal: GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 | GH100 */ + else { pThis->__kfifoChannelGroupGetLocalMaxSubcontext__ = &kfifoChannelGroupGetLocalMaxSubcontext_GA100; } @@ -334,7 +300,7 @@ { pThis->__kfifoEngineInfoXlate__ = &kfifoEngineInfoXlate_GV100; } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x11f0fc00UL) )) /* ChipHal: GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 | GH100 */ + else { pThis->__kfifoEngineInfoXlate__ = &kfifoEngineInfoXlate_GA100; } @@ -344,7 +310,7 @@ { pThis->__kfifoGenerateWorkSubmitToken__ = &kfifoGenerateWorkSubmitToken_TU102; } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x11f0fc00UL) )) /* ChipHal: GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 | GH100 */ + else { pThis->__kfifoGenerateWorkSubmitToken__ = &kfifoGenerateWorkSubmitToken_GA100; } @@ -354,21 +320,21 @@ { pThis->__kfifoUpdateUsermodeDoorbell__ = &kfifoUpdateUsermodeDoorbell_TU102; } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x11f0fc00UL) )) /* ChipHal: GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 | GH100 */ + else { pThis->__kfifoUpdateUsermodeDoorbell__ = &kfifoUpdateUsermodeDoorbell_GA100; } // Hal function -- kfifoRunlistGetBaseShift - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x000003e0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 */ + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x00000400UL) )) /* ChipHal: GA100 */ { - pThis->__kfifoRunlistGetBaseShift__ = &kfifoRunlistGetBaseShift_GM107; + pThis->__kfifoRunlistGetBaseShift__ = &kfifoRunlistGetBaseShift_GA100; } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x00000400UL) )) /* ChipHal: GA100 */ + else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x000003e0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 */ { - pThis->__kfifoRunlistGetBaseShift__ = &kfifoRunlistGetBaseShift_GA100; + pThis->__kfifoRunlistGetBaseShift__ = &kfifoRunlistGetBaseShift_GM107; } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x11f0f800UL) )) /* ChipHal: GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 | GH100 */ + else { pThis->__kfifoRunlistGetBaseShift__ = &kfifoRunlistGetBaseShift_GA102; } @@ -378,21 +344,11 @@ { pThis->__kfifoGetMaxCeChannelGroups__ = &kfifoGetMaxCeChannelGroups_GV100; } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x11f0fc00UL) )) /* ChipHal: GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 | GH100 */ + else { pThis->__kfifoGetMaxCeChannelGroups__ = &kfifoGetMaxCeChannelGroups_GA100; } - // Hal function -- kfifoSetupUserD - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x000003e0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 */ - { - pThis->__kfifoSetupUserD__ = &kfifoSetupUserD_GM107; - } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x11f0fc00UL) )) /* ChipHal: GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 | GH100 */ - { - pThis->__kfifoSetupUserD__ = &kfifoSetupUserD_GA100; - } - pThis->__nvoc_base_OBJENGSTATE.__engstateConstructEngine__ = &__nvoc_thunk_KernelFifo_engstateConstructEngine; pThis->__nvoc_base_OBJENGSTATE.__engstateStateInitLocked__ = &__nvoc_thunk_KernelFifo_engstateStateInitLocked; @@ -403,8 +359,6 @@ pThis->__nvoc_base_OBJENGSTATE.__engstateStatePreUnload__ = &__nvoc_thunk_KernelFifo_engstateStatePreUnload; - pThis->__kfifoReconcileTunableState__ = &__nvoc_thunk_OBJENGSTATE_kfifoReconcileTunableState; - pThis->__kfifoStateLoad__ = &__nvoc_thunk_OBJENGSTATE_kfifoStateLoad; pThis->__kfifoStateUnload__ = &__nvoc_thunk_OBJENGSTATE_kfifoStateUnload; @@ -421,16 +375,6 @@ pThis->__kfifoStatePreInitUnlocked__ = &__nvoc_thunk_OBJENGSTATE_kfifoStatePreInitUnlocked; - pThis->__kfifoGetTunableState__ = &__nvoc_thunk_OBJENGSTATE_kfifoGetTunableState; - - pThis->__kfifoCompareTunableState__ = &__nvoc_thunk_OBJENGSTATE_kfifoCompareTunableState; - - pThis->__kfifoFreeTunableState__ = &__nvoc_thunk_OBJENGSTATE_kfifoFreeTunableState; - - pThis->__kfifoAllocTunableState__ = &__nvoc_thunk_OBJENGSTATE_kfifoAllocTunableState; - - pThis->__kfifoSetTunableState__ = &__nvoc_thunk_OBJENGSTATE_kfifoSetTunableState; - pThis->__kfifoIsPresent__ = &__nvoc_thunk_OBJENGSTATE_kfifoIsPresent; } @@ -453,13 +397,16 @@ KernelFifo *pThis; RmHalspecOwner *pRmhalspecowner; - pThis = portMemAllocNonPaged(sizeof(KernelFifo)); - if (pThis == NULL) return NV_ERR_NO_MEMORY; + status = __nvoc_handleObjCreateMemAlloc(createFlags, sizeof(KernelFifo), (void**)&pThis, (void**)ppThis); + if (status != NV_OK) + return status; portMemSet(pThis, 0, sizeof(KernelFifo)); __nvoc_initRtti(staticCast(pThis, Dynamic), &__nvoc_class_def_KernelFifo); + pThis->__nvoc_base_OBJENGSTATE.__nvoc_base_Object.createFlags = createFlags; + if (pParent != NULL && !(createFlags & NVOC_OBJ_CREATE_FLAGS_PARENT_HALSPEC_ONLY)) { pParentObj = dynamicCast(pParent, Object); @@ -479,11 +426,17 @@ if (status != NV_OK) goto __nvoc_objCreate_KernelFifo_cleanup; *ppThis = pThis; + return NV_OK; __nvoc_objCreate_KernelFifo_cleanup: // do not call destructors here since the constructor already called them - portMemFree(pThis); + if (createFlags & NVOC_OBJ_CREATE_FLAGS_IN_PLACE_CONSTRUCT) + portMemSet(pThis, 0, sizeof(KernelFifo)); + else + portMemFree(pThis); + + // coverity[leaked_storage:FALSE] return status; } diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/generated/g_kernel_fifo_nvoc.h nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_kernel_fifo_nvoc.h --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/generated/g_kernel_fifo_nvoc.h 2023-10-25 20:27:07.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_kernel_fifo_nvoc.h 2024-03-05 22:18:26.000000000 +0000 @@ -7,7 +7,7 @@ #endif /* - * SPDX-FileCopyrightText: Copyright (c) 2021-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2021-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -56,6 +56,8 @@ #include "ctrl/ctrl2080/ctrl2080internal.h" // NV2080_CTRL_INTERNAL_FIFO_MAX_RUNLIST_* #include "ctrl/ctrl906f.h" +#include "class/clc369.h" // MMU_FAULT_BUFFER + struct KernelChannel; #ifndef __NVOC_CLASS_KernelChannel_TYPEDEF__ @@ -116,6 +118,9 @@ #define VID_PB_ALLOWED 0x1 #define PCI_PB_ALLOWED 0x2 +#define PBDMA_FAULT_MAX_ID (0x1 << DRF_SIZE_MW(NVC369_BUF_ENTRY_ENGINE_ID)) +MAKE_BITVECTOR(PBDMA_ID_BITVECTOR, PBDMA_FAULT_MAX_ID); + /*! * USERD isolation domain * @@ -274,42 +279,92 @@ typedef enum { + /* ************************************************************************* + * Bug 3820969 + * THINK BEFORE CHANGING ENUM ORDER HERE. + * VGPU-guest uses this same ordering. Because this enum is not versioned, + * changing the order here WILL BREAK old-guest-on-newer-host compatibility. + * ************************************************************************/ + // *ENG_XYZ, e.g.: ENG_GR, ENG_CE etc., ENGINE_INFO_TYPE_ENG_DESC = 0, + // HW engine ID ENGINE_INFO_TYPE_FIFO_TAG, + // RM_ENGINE_TYPE_* ENGINE_INFO_TYPE_RM_ENGINE_TYPE, + + // // runlist id (meaning varies by GPU) + // Valid only for Esched-driven engines + // ENGINE_INFO_TYPE_RUNLIST, + // NV_PFIFO_INTR_MMU_FAULT_ENG_ID_* ENGINE_INFO_TYPE_MMU_FAULT_ID, + // ROBUST_CHANNEL_* ENGINE_INFO_TYPE_RC_MASK, + // Reset Bit Position. On Ampere, only valid if not _INVALID ENGINE_INFO_TYPE_RESET, + // Interrupt Bit Position ENGINE_INFO_TYPE_INTR, + // log2(MC_ENGINE_*) ENGINE_INFO_TYPE_MC, + // The DEV_TYPE_ENUM for this engine ENGINE_INFO_TYPE_DEV_TYPE_ENUM, + // The particular instance of this engine type ENGINE_INFO_TYPE_INSTANCE_ID, + + // // The base address for this engine's NV_RUNLIST. Valid only on Ampere+ + // Valid only for Esched-driven engines + // ENGINE_INFO_TYPE_RUNLIST_PRI_BASE, - // If this entry is a host-driven engine. Valid only on Ampere+ - ENGINE_INFO_TYPE_IS_ENGINE, + + // + // If this entry is a host-driven engine. + // Update _isEngineInfoTypeValidForOnlyHostDriven when adding any new entry. + // + ENGINE_INFO_TYPE_IS_HOST_DRIVEN_ENGINE, + + // // The index into the per-engine NV_RUNLIST registers. Valid only on Ampere+ + // Valid only for Esched-driven engines + // ENGINE_INFO_TYPE_RUNLIST_ENGINE_ID, - // The base address for this engine's NV_CHRAM registers. Valid only on Ampere+ + + // + // The base address for this engine's NV_CHRAM registers. Valid only on + // Ampere+ + // + // Valid only for Esched-driven engines + // ENGINE_INFO_TYPE_CHRAM_PRI_BASE, + // This entry added to copy data at RMCTRL_EXPORT() call for Kernel RM + ENGINE_INFO_TYPE_KERNEL_RM_MAX, // Used for iterating the engine info table by the index passed. - ENGINE_INFO_TYPE_INVALID, + ENGINE_INFO_TYPE_INVALID = ENGINE_INFO_TYPE_KERNEL_RM_MAX, + + // Size of FIFO_ENGINE_LIST.engineData + ENGINE_INFO_TYPE_ENGINE_DATA_ARRAY_SIZE = ENGINE_INFO_TYPE_INVALID, - // Input-only parameter for fifoEngineInfoXlate. + // Input-only parameter for kfifoEngineInfoXlate. ENGINE_INFO_TYPE_PBDMA_ID + + /* ************************************************************************* + * Bug 3820969 + * THINK BEFORE CHANGING ENUM ORDER HERE. + * VGPU-guest uses this same ordering. Because this enum is not versioned, + * changing the order here WILL BREAK old-guest-on-newer-host compatibility. + * ************************************************************************/ } ENGINE_INFO_TYPE; // Maximum number of pbdma IDs for a given engine @@ -320,12 +375,12 @@ typedef struct _def_fifo_engine_list { - NvU32 engineData[ENGINE_INFO_TYPE_INVALID]; + NvU32 engineData[ENGINE_INFO_TYPE_ENGINE_DATA_ARRAY_SIZE]; NvU32 pbdmaIds[FIFO_ENGINE_MAX_NUM_PBDMA]; NvU32 pbdmaFaultIds[FIFO_ENGINE_MAX_NUM_PBDMA]; NvU32 numPbdmas; char engineName[FIFO_ENGINE_NAME_MAX_SIZE]; -} FIFO_ENGINE_LIST, *PFIFO_ENGINE_LIST; +} FIFO_ENGINE_LIST; typedef struct { @@ -335,10 +390,20 @@ typedef struct _def_engine_info { - NvU32 maxNumPbdmas; // max number of PBDMAs - NvU32 basePbdmaFaultId; // base PBDMA Fault ID - NvU32 maxNumRunlists; // max number of runlists - NvU32 numRunlists; // Gets the number of runlists, not the maximum + NvU32 maxNumPbdmas; + PBDMA_ID_BITVECTOR validEngineIdsForPbdmas; + // + // The highest runlist ID. Valid runlist IDs are < maxNumRunlists + // However, the entire [0, maxNumRunlists) range is not valid. There are + // missing runlist IDs in this range. + // + NvU32 maxNumRunlists; + // + // Multiple engines may have the same runlist ID. This is the total number + // of engines with a runlist which is equal to the number of Esched driven + // engines and does not include the SW engine. + // + NvU32 numRunlists; NvU32 engineInfoListSize; FIFO_ENGINE_LIST *engineInfoList; } ENGINE_INFO; @@ -395,8 +460,8 @@ #define INST_BLOCK_APERTURE_SYSTEM_NON_COHERENT_MEMORY 0x00000003 // Macro to verify HW and class defines are compatible -#define VERIFY_INST_BLOCK_APERTURE(vid, coh, ncoh) \ - ct_assert((vid) == INST_BLOCK_APERTURE_VIDEO_MEMORY); \ +#define VERIFY_INST_BLOCK_APERTURE(vid, coh, ncoh) \ + ct_assert((vid) == INST_BLOCK_APERTURE_VIDEO_MEMORY); \ ct_assert((coh) == INST_BLOCK_APERTURE_SYSTEM_COHERENT_MEMORY); \ ct_assert((ncoh) == INST_BLOCK_APERTURE_SYSTEM_NON_COHERENT_MEMORY) @@ -420,8 +485,7 @@ NV_STATUS (*__kfifoStatePostLoad__)(struct OBJGPU *, struct KernelFifo *, NvU32); NV_STATUS (*__kfifoStatePreUnload__)(struct OBJGPU *, struct KernelFifo *, NvU32); NV_STATUS (*__kfifoCheckChannelAllocAddrSpaces__)(struct KernelFifo *, NV_ADDRESS_SPACE, NV_ADDRESS_SPACE, NV_ADDRESS_SPACE); - NvU64 (*__kfifoGetMmioUsermodeOffset__)(struct OBJGPU *, struct KernelFifo *, NvBool); - NvU64 (*__kfifoGetMmioUsermodeSize__)(struct OBJGPU *, struct KernelFifo *, NvBool); + NV_STATUS (*__kfifoConstructUsermodeMemdescs__)(struct OBJGPU *, struct KernelFifo *); NvU32 (*__kfifoChannelGroupGetLocalMaxSubcontext__)(struct OBJGPU *, struct KernelFifo *, struct KernelChannelGroup *, NvBool); void (*__kfifoGetCtxBufferMapFlags__)(struct OBJGPU *, struct KernelFifo *, NvU32, NvU32 *); NV_STATUS (*__kfifoEngineInfoXlate__)(struct OBJGPU *, struct KernelFifo *, ENGINE_INFO_TYPE, NvU32, ENGINE_INFO_TYPE, NvU32 *); @@ -429,8 +493,6 @@ NV_STATUS (*__kfifoUpdateUsermodeDoorbell__)(struct OBJGPU *, struct KernelFifo *, NvU32, NvU32); NvU32 (*__kfifoRunlistGetBaseShift__)(struct KernelFifo *); NvU32 (*__kfifoGetMaxCeChannelGroups__)(struct OBJGPU *, struct KernelFifo *); - void (*__kfifoSetupUserD__)(struct KernelFifo *, NvU8 *); - NV_STATUS (*__kfifoReconcileTunableState__)(POBJGPU, struct KernelFifo *, void *); NV_STATUS (*__kfifoStateLoad__)(POBJGPU, struct KernelFifo *, NvU32); NV_STATUS (*__kfifoStateUnload__)(POBJGPU, struct KernelFifo *, NvU32); NV_STATUS (*__kfifoStatePreLoad__)(POBJGPU, struct KernelFifo *, NvU32); @@ -439,11 +501,6 @@ void (*__kfifoInitMissing__)(POBJGPU, struct KernelFifo *); NV_STATUS (*__kfifoStatePreInitLocked__)(POBJGPU, struct KernelFifo *); NV_STATUS (*__kfifoStatePreInitUnlocked__)(POBJGPU, struct KernelFifo *); - NV_STATUS (*__kfifoGetTunableState__)(POBJGPU, struct KernelFifo *, void *); - NV_STATUS (*__kfifoCompareTunableState__)(POBJGPU, struct KernelFifo *, void *, void *); - void (*__kfifoFreeTunableState__)(POBJGPU, struct KernelFifo *, void *); - NV_STATUS (*__kfifoAllocTunableState__)(POBJGPU, struct KernelFifo *, void **); - NV_STATUS (*__kfifoSetTunableState__)(POBJGPU, struct KernelFifo *, void *); NvBool (*__kfifoIsPresent__)(POBJGPU, struct KernelFifo *); struct KernelSchedMgr *pKernelSchedMgr; CHID_MGR **ppChidMgr; @@ -454,6 +511,8 @@ NvU32 maxSubcontextCount; FifoSchedulingHandlerEntryList postSchedulingEnableHandlerList; FifoSchedulingHandlerEntryList preSchedulingDisableHandlerList; + NvU32 maxSec2SecureChannels; + NvU32 maxCeSecureChannels; NvBool bUseChidHeap; NvBool bUsePerRunlistChram; NvBool bDisableChidIsolation; @@ -474,6 +533,9 @@ NvU32 InstAttr; const NV_ADDRESS_SPACE *pInstAllocList; MEMORY_DESCRIPTOR *pDummyPageMemDesc; + MEMORY_DESCRIPTOR *pBar1VF; + MEMORY_DESCRIPTOR *pBar1PrivVF; + MEMORY_DESCRIPTOR *pRegVF; CTX_BUF_POOL_INFO *pRunlistBufPool[62]; MEMORY_DESCRIPTOR ***pppRunlistBufMemDesc; }; @@ -517,10 +579,8 @@ #define kfifoStatePreUnload_HAL(pGpu, pKernelFifo, flags) kfifoStatePreUnload_DISPATCH(pGpu, pKernelFifo, flags) #define kfifoCheckChannelAllocAddrSpaces(pKernelFifo, userdAddrSpace, pushBuffAddrSpace, gpFifoAddrSpace) kfifoCheckChannelAllocAddrSpaces_DISPATCH(pKernelFifo, userdAddrSpace, pushBuffAddrSpace, gpFifoAddrSpace) #define kfifoCheckChannelAllocAddrSpaces_HAL(pKernelFifo, userdAddrSpace, pushBuffAddrSpace, gpFifoAddrSpace) kfifoCheckChannelAllocAddrSpaces_DISPATCH(pKernelFifo, userdAddrSpace, pushBuffAddrSpace, gpFifoAddrSpace) -#define kfifoGetMmioUsermodeOffset(pGpu, pKernelFifo, arg0) kfifoGetMmioUsermodeOffset_DISPATCH(pGpu, pKernelFifo, arg0) -#define kfifoGetMmioUsermodeOffset_HAL(pGpu, pKernelFifo, arg0) kfifoGetMmioUsermodeOffset_DISPATCH(pGpu, pKernelFifo, arg0) -#define kfifoGetMmioUsermodeSize(pGpu, pKernelFifo, arg0) kfifoGetMmioUsermodeSize_DISPATCH(pGpu, pKernelFifo, arg0) -#define kfifoGetMmioUsermodeSize_HAL(pGpu, pKernelFifo, arg0) kfifoGetMmioUsermodeSize_DISPATCH(pGpu, pKernelFifo, arg0) +#define kfifoConstructUsermodeMemdescs(pGpu, pKernelFifo) kfifoConstructUsermodeMemdescs_DISPATCH(pGpu, pKernelFifo) +#define kfifoConstructUsermodeMemdescs_HAL(pGpu, pKernelFifo) kfifoConstructUsermodeMemdescs_DISPATCH(pGpu, pKernelFifo) #define kfifoChannelGroupGetLocalMaxSubcontext(pGpu, pKernelFifo, arg0, arg1) kfifoChannelGroupGetLocalMaxSubcontext_DISPATCH(pGpu, pKernelFifo, arg0, arg1) #define kfifoChannelGroupGetLocalMaxSubcontext_HAL(pGpu, pKernelFifo, arg0, arg1) kfifoChannelGroupGetLocalMaxSubcontext_DISPATCH(pGpu, pKernelFifo, arg0, arg1) #define kfifoGetCtxBufferMapFlags(pGpu, pKernelFifo, engine, pFlags) kfifoGetCtxBufferMapFlags_DISPATCH(pGpu, pKernelFifo, engine, pFlags) @@ -535,9 +595,6 @@ #define kfifoRunlistGetBaseShift_HAL(pKernelFifo) kfifoRunlistGetBaseShift_DISPATCH(pKernelFifo) #define kfifoGetMaxCeChannelGroups(pGpu, pKernelFifo) kfifoGetMaxCeChannelGroups_DISPATCH(pGpu, pKernelFifo) #define kfifoGetMaxCeChannelGroups_HAL(pGpu, pKernelFifo) kfifoGetMaxCeChannelGroups_DISPATCH(pGpu, pKernelFifo) -#define kfifoSetupUserD(pKernelFifo, pUserD) kfifoSetupUserD_DISPATCH(pKernelFifo, pUserD) -#define kfifoSetupUserD_HAL(pKernelFifo, pUserD) kfifoSetupUserD_DISPATCH(pKernelFifo, pUserD) -#define kfifoReconcileTunableState(pGpu, pEngstate, pTunableState) kfifoReconcileTunableState_DISPATCH(pGpu, pEngstate, pTunableState) #define kfifoStateLoad(pGpu, pEngstate, arg0) kfifoStateLoad_DISPATCH(pGpu, pEngstate, arg0) #define kfifoStateUnload(pGpu, pEngstate, arg0) kfifoStateUnload_DISPATCH(pGpu, pEngstate, arg0) #define kfifoStatePreLoad(pGpu, pEngstate, arg0) kfifoStatePreLoad_DISPATCH(pGpu, pEngstate, arg0) @@ -546,11 +603,6 @@ #define kfifoInitMissing(pGpu, pEngstate) kfifoInitMissing_DISPATCH(pGpu, pEngstate) #define kfifoStatePreInitLocked(pGpu, pEngstate) kfifoStatePreInitLocked_DISPATCH(pGpu, pEngstate) #define kfifoStatePreInitUnlocked(pGpu, pEngstate) kfifoStatePreInitUnlocked_DISPATCH(pGpu, pEngstate) -#define kfifoGetTunableState(pGpu, pEngstate, pTunableState) kfifoGetTunableState_DISPATCH(pGpu, pEngstate, pTunableState) -#define kfifoCompareTunableState(pGpu, pEngstate, pTunables1, pTunables2) kfifoCompareTunableState_DISPATCH(pGpu, pEngstate, pTunables1, pTunables2) -#define kfifoFreeTunableState(pGpu, pEngstate, pTunableState) kfifoFreeTunableState_DISPATCH(pGpu, pEngstate, pTunableState) -#define kfifoAllocTunableState(pGpu, pEngstate, ppTunableState) kfifoAllocTunableState_DISPATCH(pGpu, pEngstate, ppTunableState) -#define kfifoSetTunableState(pGpu, pEngstate, pTunableState) kfifoSetTunableState_DISPATCH(pGpu, pEngstate, pTunableState) #define kfifoIsPresent(pGpu, pEngstate) kfifoIsPresent_DISPATCH(pGpu, pEngstate) NV_STATUS kfifoConstructHal_GM107(struct OBJGPU *pGpu, struct KernelFifo *pKernelFifo); @@ -1026,6 +1078,22 @@ #define kfifoGetEnginePbdmaIds_HAL(pGpu, pKernelFifo, type, val, ppPbdmaIds, pNumPbdmas) kfifoGetEnginePbdmaIds(pGpu, pKernelFifo, type, val, ppPbdmaIds, pNumPbdmas) +static inline NV_STATUS kfifoReservePbdmaFaultIds_56cd7a(struct OBJGPU *pGpu, struct KernelFifo *pKernelFifo, FIFO_ENGINE_LIST *arg0, NvU32 arg1) { + return NV_OK; +} + + +#ifdef __nvoc_kernel_fifo_h_disabled +static inline NV_STATUS kfifoReservePbdmaFaultIds(struct OBJGPU *pGpu, struct KernelFifo *pKernelFifo, FIFO_ENGINE_LIST *arg0, NvU32 arg1) { + NV_ASSERT_FAILED_PRECOMP("KernelFifo was disabled!"); + return NV_ERR_NOT_SUPPORTED; +} +#else //__nvoc_kernel_fifo_h_disabled +#define kfifoReservePbdmaFaultIds(pGpu, pKernelFifo, arg0, arg1) kfifoReservePbdmaFaultIds_56cd7a(pGpu, pKernelFifo, arg0, arg1) +#endif //__nvoc_kernel_fifo_h_disabled + +#define kfifoReservePbdmaFaultIds_HAL(pGpu, pKernelFifo, arg0, arg1) kfifoReservePbdmaFaultIds(pGpu, pKernelFifo, arg0, arg1) + NV_STATUS kfifoGetEnginePartnerList_GM107(struct OBJGPU *pGpu, struct KernelFifo *pKernelFifo, NV2080_CTRL_GPU_GET_ENGINE_PARTNERLIST_PARAMS *pParams); @@ -1243,6 +1311,20 @@ #define kfifoRestoreSchedPolicy_HAL(pGpu, pKernelFifo) kfifoRestoreSchedPolicy(pGpu, pKernelFifo) +NV_STATUS kfifoGetMaxSecureChannels_KERNEL(struct OBJGPU *pGpu, struct KernelFifo *pKernelFifo); + + +#ifdef __nvoc_kernel_fifo_h_disabled +static inline NV_STATUS kfifoGetMaxSecureChannels(struct OBJGPU *pGpu, struct KernelFifo *pKernelFifo) { + NV_ASSERT_FAILED_PRECOMP("KernelFifo was disabled!"); + return NV_ERR_NOT_SUPPORTED; +} +#else //__nvoc_kernel_fifo_h_disabled +#define kfifoGetMaxSecureChannels(pGpu, pKernelFifo) kfifoGetMaxSecureChannels_KERNEL(pGpu, pKernelFifo) +#endif //__nvoc_kernel_fifo_h_disabled + +#define kfifoGetMaxSecureChannels_HAL(pGpu, pKernelFifo) kfifoGetMaxSecureChannels(pGpu, pKernelFifo) + NV_STATUS kfifoRunlistSetId_GM107(struct OBJGPU *pGpu, struct KernelFifo *pKernelFifo, struct KernelChannel *arg0, NvU32 runlistId); @@ -1271,6 +1353,19 @@ #define kfifoRunlistSetIdByEngine_HAL(pGpu, pKernelFifo, arg0, engDesc) kfifoRunlistSetIdByEngine(pGpu, pKernelFifo, arg0, engDesc) +void kfifoSetupUserD_GM107(struct OBJGPU *pGpu, struct KernelFifo *pKernelFifo, MEMORY_DESCRIPTOR *pMemDesc); + + +#ifdef __nvoc_kernel_fifo_h_disabled +static inline void kfifoSetupUserD(struct OBJGPU *pGpu, struct KernelFifo *pKernelFifo, MEMORY_DESCRIPTOR *pMemDesc) { + NV_ASSERT_FAILED_PRECOMP("KernelFifo was disabled!"); +} +#else //__nvoc_kernel_fifo_h_disabled +#define kfifoSetupUserD(pGpu, pKernelFifo, pMemDesc) kfifoSetupUserD_GM107(pGpu, pKernelFifo, pMemDesc) +#endif //__nvoc_kernel_fifo_h_disabled + +#define kfifoSetupUserD_HAL(pGpu, pKernelFifo, pMemDesc) kfifoSetupUserD(pGpu, pKernelFifo, pMemDesc) + NV_STATUS kfifoConstructEngine_IMPL(struct OBJGPU *pGpu, struct KernelFifo *pKernelFifo, ENGDESCRIPTOR engDesc); static inline NV_STATUS kfifoConstructEngine_DISPATCH(struct OBJGPU *pGpu, struct KernelFifo *pKernelFifo, ENGDESCRIPTOR engDesc) { @@ -1311,24 +1406,12 @@ return pKernelFifo->__kfifoCheckChannelAllocAddrSpaces__(pKernelFifo, userdAddrSpace, pushBuffAddrSpace, gpFifoAddrSpace); } -NvU64 kfifoGetMmioUsermodeOffset_GH100(struct OBJGPU *pGpu, struct KernelFifo *pKernelFifo, NvBool arg0); +NV_STATUS kfifoConstructUsermodeMemdescs_GH100(struct OBJGPU *pGpu, struct KernelFifo *pKernelFifo); -static inline NvU64 kfifoGetMmioUsermodeOffset_474d46(struct OBJGPU *pGpu, struct KernelFifo *pKernelFifo, NvBool arg0) { - NV_ASSERT_OR_RETURN_PRECOMP(0, 0); -} - -static inline NvU64 kfifoGetMmioUsermodeOffset_DISPATCH(struct OBJGPU *pGpu, struct KernelFifo *pKernelFifo, NvBool arg0) { - return pKernelFifo->__kfifoGetMmioUsermodeOffset__(pGpu, pKernelFifo, arg0); -} - -NvU64 kfifoGetMmioUsermodeSize_GH100(struct OBJGPU *pGpu, struct KernelFifo *pKernelFifo, NvBool arg0); - -static inline NvU64 kfifoGetMmioUsermodeSize_474d46(struct OBJGPU *pGpu, struct KernelFifo *pKernelFifo, NvBool arg0) { - NV_ASSERT_OR_RETURN_PRECOMP(0, 0); -} +NV_STATUS kfifoConstructUsermodeMemdescs_GV100(struct OBJGPU *pGpu, struct KernelFifo *pKernelFifo); -static inline NvU64 kfifoGetMmioUsermodeSize_DISPATCH(struct OBJGPU *pGpu, struct KernelFifo *pKernelFifo, NvBool arg0) { - return pKernelFifo->__kfifoGetMmioUsermodeSize__(pGpu, pKernelFifo, arg0); +static inline NV_STATUS kfifoConstructUsermodeMemdescs_DISPATCH(struct OBJGPU *pGpu, struct KernelFifo *pKernelFifo) { + return pKernelFifo->__kfifoConstructUsermodeMemdescs__(pGpu, pKernelFifo); } NvU32 kfifoChannelGroupGetLocalMaxSubcontext_GM107(struct OBJGPU *pGpu, struct KernelFifo *pKernelFifo, struct KernelChannelGroup *arg0, NvBool arg1); @@ -1391,18 +1474,6 @@ return pKernelFifo->__kfifoGetMaxCeChannelGroups__(pGpu, pKernelFifo); } -void kfifoSetupUserD_GM107(struct KernelFifo *pKernelFifo, NvU8 *pUserD); - -void kfifoSetupUserD_GA100(struct KernelFifo *pKernelFifo, NvU8 *pUserD); - -static inline void kfifoSetupUserD_DISPATCH(struct KernelFifo *pKernelFifo, NvU8 *pUserD) { - pKernelFifo->__kfifoSetupUserD__(pKernelFifo, pUserD); -} - -static inline NV_STATUS kfifoReconcileTunableState_DISPATCH(POBJGPU pGpu, struct KernelFifo *pEngstate, void *pTunableState) { - return pEngstate->__kfifoReconcileTunableState__(pGpu, pEngstate, pTunableState); -} - static inline NV_STATUS kfifoStateLoad_DISPATCH(POBJGPU pGpu, struct KernelFifo *pEngstate, NvU32 arg0) { return pEngstate->__kfifoStateLoad__(pGpu, pEngstate, arg0); } @@ -1435,26 +1506,6 @@ return pEngstate->__kfifoStatePreInitUnlocked__(pGpu, pEngstate); } -static inline NV_STATUS kfifoGetTunableState_DISPATCH(POBJGPU pGpu, struct KernelFifo *pEngstate, void *pTunableState) { - return pEngstate->__kfifoGetTunableState__(pGpu, pEngstate, pTunableState); -} - -static inline NV_STATUS kfifoCompareTunableState_DISPATCH(POBJGPU pGpu, struct KernelFifo *pEngstate, void *pTunables1, void *pTunables2) { - return pEngstate->__kfifoCompareTunableState__(pGpu, pEngstate, pTunables1, pTunables2); -} - -static inline void kfifoFreeTunableState_DISPATCH(POBJGPU pGpu, struct KernelFifo *pEngstate, void *pTunableState) { - pEngstate->__kfifoFreeTunableState__(pGpu, pEngstate, pTunableState); -} - -static inline NV_STATUS kfifoAllocTunableState_DISPATCH(POBJGPU pGpu, struct KernelFifo *pEngstate, void **ppTunableState) { - return pEngstate->__kfifoAllocTunableState__(pGpu, pEngstate, ppTunableState); -} - -static inline NV_STATUS kfifoSetTunableState_DISPATCH(POBJGPU pGpu, struct KernelFifo *pEngstate, void *pTunableState) { - return pEngstate->__kfifoSetTunableState__(pGpu, pEngstate, pTunableState); -} - static inline NvBool kfifoIsPresent_DISPATCH(POBJGPU pGpu, struct KernelFifo *pEngstate) { return pEngstate->__kfifoIsPresent__(pGpu, pEngstate); } @@ -1593,37 +1644,37 @@ #define kfifoChidMgrFreeChid(pGpu, pKernelFifo, pChidMgr, ChID) kfifoChidMgrFreeChid_IMPL(pGpu, pKernelFifo, pChidMgr, ChID) #endif //__nvoc_kernel_fifo_h_disabled -NV_STATUS kfifoChidMgrReserveSystemChids_IMPL(struct OBJGPU *pGpu, struct KernelFifo *pKernelFifo, CHID_MGR *pChidMgr, NvU32 numChannels, NvU32 flags, NvU32 gfid, NvU32 *pChidOffset, NvHandle hMigClient, NvU32 engineFifoListNumEntries, FIFO_ENGINE_LIST *pEngineFifoList); +NV_STATUS kfifoChidMgrReserveSystemChids_IMPL(struct OBJGPU *pGpu, struct KernelFifo *pKernelFifo, CHID_MGR *pChidMgr, NvU32 numChannels, NvU32 flags, NvU32 gfid, NvU32 *pChidOffset, NvU32 *pChannelCount, NvHandle hMigClient, NvU32 engineFifoListNumEntries, FIFO_ENGINE_LIST *pEngineFifoList); #ifdef __nvoc_kernel_fifo_h_disabled -static inline NV_STATUS kfifoChidMgrReserveSystemChids(struct OBJGPU *pGpu, struct KernelFifo *pKernelFifo, CHID_MGR *pChidMgr, NvU32 numChannels, NvU32 flags, NvU32 gfid, NvU32 *pChidOffset, NvHandle hMigClient, NvU32 engineFifoListNumEntries, FIFO_ENGINE_LIST *pEngineFifoList) { +static inline NV_STATUS kfifoChidMgrReserveSystemChids(struct OBJGPU *pGpu, struct KernelFifo *pKernelFifo, CHID_MGR *pChidMgr, NvU32 numChannels, NvU32 flags, NvU32 gfid, NvU32 *pChidOffset, NvU32 *pChannelCount, NvHandle hMigClient, NvU32 engineFifoListNumEntries, FIFO_ENGINE_LIST *pEngineFifoList) { NV_ASSERT_FAILED_PRECOMP("KernelFifo was disabled!"); return NV_ERR_NOT_SUPPORTED; } #else //__nvoc_kernel_fifo_h_disabled -#define kfifoChidMgrReserveSystemChids(pGpu, pKernelFifo, pChidMgr, numChannels, flags, gfid, pChidOffset, hMigClient, engineFifoListNumEntries, pEngineFifoList) kfifoChidMgrReserveSystemChids_IMPL(pGpu, pKernelFifo, pChidMgr, numChannels, flags, gfid, pChidOffset, hMigClient, engineFifoListNumEntries, pEngineFifoList) +#define kfifoChidMgrReserveSystemChids(pGpu, pKernelFifo, pChidMgr, numChannels, flags, gfid, pChidOffset, pChannelCount, hMigClient, engineFifoListNumEntries, pEngineFifoList) kfifoChidMgrReserveSystemChids_IMPL(pGpu, pKernelFifo, pChidMgr, numChannels, flags, gfid, pChidOffset, pChannelCount, hMigClient, engineFifoListNumEntries, pEngineFifoList) #endif //__nvoc_kernel_fifo_h_disabled -NV_STATUS kfifoChidMgrFreeSystemChids_IMPL(struct OBJGPU *pGpu, struct KernelFifo *pKernelFifo, CHID_MGR *pChidMgr, NvU32 gfid, NvU32 *pChidOffset, NvHandle hMigClient, NvU32 engineFifoListNumEntries, FIFO_ENGINE_LIST *pEngineFifoList); +NV_STATUS kfifoChidMgrFreeSystemChids_IMPL(struct OBJGPU *pGpu, struct KernelFifo *pKernelFifo, CHID_MGR *pChidMgr, NvU32 gfid, NvU32 *pChidOffset, NvU32 *pChannelCount, NvHandle hMigClient, NvU32 engineFifoListNumEntries, FIFO_ENGINE_LIST *pEngineFifoList); #ifdef __nvoc_kernel_fifo_h_disabled -static inline NV_STATUS kfifoChidMgrFreeSystemChids(struct OBJGPU *pGpu, struct KernelFifo *pKernelFifo, CHID_MGR *pChidMgr, NvU32 gfid, NvU32 *pChidOffset, NvHandle hMigClient, NvU32 engineFifoListNumEntries, FIFO_ENGINE_LIST *pEngineFifoList) { +static inline NV_STATUS kfifoChidMgrFreeSystemChids(struct OBJGPU *pGpu, struct KernelFifo *pKernelFifo, CHID_MGR *pChidMgr, NvU32 gfid, NvU32 *pChidOffset, NvU32 *pChannelCount, NvHandle hMigClient, NvU32 engineFifoListNumEntries, FIFO_ENGINE_LIST *pEngineFifoList) { NV_ASSERT_FAILED_PRECOMP("KernelFifo was disabled!"); return NV_ERR_NOT_SUPPORTED; } #else //__nvoc_kernel_fifo_h_disabled -#define kfifoChidMgrFreeSystemChids(pGpu, pKernelFifo, pChidMgr, gfid, pChidOffset, hMigClient, engineFifoListNumEntries, pEngineFifoList) kfifoChidMgrFreeSystemChids_IMPL(pGpu, pKernelFifo, pChidMgr, gfid, pChidOffset, hMigClient, engineFifoListNumEntries, pEngineFifoList) +#define kfifoChidMgrFreeSystemChids(pGpu, pKernelFifo, pChidMgr, gfid, pChidOffset, pChannelCount, hMigClient, engineFifoListNumEntries, pEngineFifoList) kfifoChidMgrFreeSystemChids_IMPL(pGpu, pKernelFifo, pChidMgr, gfid, pChidOffset, pChannelCount, hMigClient, engineFifoListNumEntries, pEngineFifoList) #endif //__nvoc_kernel_fifo_h_disabled -NV_STATUS kfifoSetChidOffset_IMPL(struct OBJGPU *pGpu, struct KernelFifo *pKernelFifo, CHID_MGR *pChidMgr, NvU32 offset, NvU32 numChannels, NvU32 gfid, NvU32 *pChidOffset, NvHandle hMigClient, NvU32 engineFifoListNumEntries, FIFO_ENGINE_LIST *pEngineFifoList); +NV_STATUS kfifoSetChidOffset_IMPL(struct OBJGPU *pGpu, struct KernelFifo *pKernelFifo, CHID_MGR *pChidMgr, NvU32 offset, NvU32 numChannels, NvU32 gfid, NvU32 *pChidOffset, NvU32 *pChannelCount, NvHandle hMigClient, NvU32 engineFifoListNumEntries, FIFO_ENGINE_LIST *pEngineFifoList); #ifdef __nvoc_kernel_fifo_h_disabled -static inline NV_STATUS kfifoSetChidOffset(struct OBJGPU *pGpu, struct KernelFifo *pKernelFifo, CHID_MGR *pChidMgr, NvU32 offset, NvU32 numChannels, NvU32 gfid, NvU32 *pChidOffset, NvHandle hMigClient, NvU32 engineFifoListNumEntries, FIFO_ENGINE_LIST *pEngineFifoList) { +static inline NV_STATUS kfifoSetChidOffset(struct OBJGPU *pGpu, struct KernelFifo *pKernelFifo, CHID_MGR *pChidMgr, NvU32 offset, NvU32 numChannels, NvU32 gfid, NvU32 *pChidOffset, NvU32 *pChannelCount, NvHandle hMigClient, NvU32 engineFifoListNumEntries, FIFO_ENGINE_LIST *pEngineFifoList) { NV_ASSERT_FAILED_PRECOMP("KernelFifo was disabled!"); return NV_ERR_NOT_SUPPORTED; } #else //__nvoc_kernel_fifo_h_disabled -#define kfifoSetChidOffset(pGpu, pKernelFifo, pChidMgr, offset, numChannels, gfid, pChidOffset, hMigClient, engineFifoListNumEntries, pEngineFifoList) kfifoSetChidOffset_IMPL(pGpu, pKernelFifo, pChidMgr, offset, numChannels, gfid, pChidOffset, hMigClient, engineFifoListNumEntries, pEngineFifoList) +#define kfifoSetChidOffset(pGpu, pKernelFifo, pChidMgr, offset, numChannels, gfid, pChidOffset, pChannelCount, hMigClient, engineFifoListNumEntries, pEngineFifoList) kfifoSetChidOffset_IMPL(pGpu, pKernelFifo, pChidMgr, offset, numChannels, gfid, pChidOffset, pChannelCount, hMigClient, engineFifoListNumEntries, pEngineFifoList) #endif //__nvoc_kernel_fifo_h_disabled NvU32 kfifoChidMgrGetNumChannels_IMPL(struct OBJGPU *pGpu, struct KernelFifo *pKernelFifo, CHID_MGR *pChidMgr); @@ -1991,6 +2042,17 @@ const FIFO_GUEST_ENGINE_TABLE *kfifoGetGuestEngineLookupTable_IMPL(NvU32 *pTableSize); #define kfifoGetGuestEngineLookupTable(pTableSize) kfifoGetGuestEngineLookupTable_IMPL(pTableSize) +NvU32 kfifoGetNumEschedDrivenEngines_IMPL(struct KernelFifo *pKernelFifo); + +#ifdef __nvoc_kernel_fifo_h_disabled +static inline NvU32 kfifoGetNumEschedDrivenEngines(struct KernelFifo *pKernelFifo) { + NV_ASSERT_FAILED_PRECOMP("KernelFifo was disabled!"); + return 0; +} +#else //__nvoc_kernel_fifo_h_disabled +#define kfifoGetNumEschedDrivenEngines(pKernelFifo) kfifoGetNumEschedDrivenEngines_IMPL(pKernelFifo) +#endif //__nvoc_kernel_fifo_h_disabled + #undef PRIVATE_FIELD diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/generated/g_kernel_graphics_context_nvoc.c nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_kernel_graphics_context_nvoc.c --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/generated/g_kernel_graphics_context_nvoc.c 2023-10-25 20:27:07.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_kernel_graphics_context_nvoc.c 2024-03-05 22:18:27.000000000 +0000 @@ -105,44 +105,24 @@ return gpuresShareCallback((struct GpuResource *)(((unsigned char *)pGpuResource) + __nvoc_rtti_KernelGraphicsContext_GpuResource.offset), pInvokingClient, pParentRef, pSharePolicy); } -static NV_STATUS __nvoc_thunk_GpuResource_kgrctxControl(struct KernelGraphicsContext *pGpuResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { - return gpuresControl((struct GpuResource *)(((unsigned char *)pGpuResource) + __nvoc_rtti_KernelGraphicsContext_GpuResource.offset), pCallContext, pParams); -} - -static NV_STATUS __nvoc_thunk_GpuResource_kgrctxUnmap(struct KernelGraphicsContext *pGpuResource, struct CALL_CONTEXT *pCallContext, struct RsCpuMapping *pCpuMapping) { - return gpuresUnmap((struct GpuResource *)(((unsigned char *)pGpuResource) + __nvoc_rtti_KernelGraphicsContext_GpuResource.offset), pCallContext, pCpuMapping); -} - -static NV_STATUS __nvoc_thunk_RmResource_kgrctxGetMemInterMapParams(struct KernelGraphicsContext *pRmResource, RMRES_MEM_INTER_MAP_PARAMS *pParams) { - return rmresGetMemInterMapParams((struct RmResource *)(((unsigned char *)pRmResource) + __nvoc_rtti_KernelGraphicsContext_RmResource.offset), pParams); +static NV_STATUS __nvoc_thunk_RmResource_kgrctxCheckMemInterUnmap(struct KernelGraphicsContext *pRmResource, NvBool bSubdeviceHandleProvided) { + return rmresCheckMemInterUnmap((struct RmResource *)(((unsigned char *)pRmResource) + __nvoc_rtti_KernelGraphicsContext_RmResource.offset), bSubdeviceHandleProvided); } -static NV_STATUS __nvoc_thunk_RmResource_kgrctxGetMemoryMappingDescriptor(struct KernelGraphicsContext *pRmResource, struct MEMORY_DESCRIPTOR **ppMemDesc) { - return rmresGetMemoryMappingDescriptor((struct RmResource *)(((unsigned char *)pRmResource) + __nvoc_rtti_KernelGraphicsContext_RmResource.offset), ppMemDesc); +static NV_STATUS __nvoc_thunk_RsResource_kgrctxMapTo(struct KernelGraphicsContext *pResource, RS_RES_MAP_TO_PARAMS *pParams) { + return resMapTo((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_KernelGraphicsContext_RsResource.offset), pParams); } static NV_STATUS __nvoc_thunk_GpuResource_kgrctxGetMapAddrSpace(struct KernelGraphicsContext *pGpuResource, struct CALL_CONTEXT *pCallContext, NvU32 mapFlags, NV_ADDRESS_SPACE *pAddrSpace) { return gpuresGetMapAddrSpace((struct GpuResource *)(((unsigned char *)pGpuResource) + __nvoc_rtti_KernelGraphicsContext_GpuResource.offset), pCallContext, mapFlags, pAddrSpace); } -static NV_STATUS __nvoc_thunk_RsResource_kgrctxControlFilter(struct KernelGraphicsContext *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { - return resControlFilter((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_KernelGraphicsContext_RsResource.offset), pCallContext, pParams); -} - -static void __nvoc_thunk_RsResource_kgrctxAddAdditionalDependants(struct RsClient *pClient, struct KernelGraphicsContext *pResource, RsResourceRef *pReference) { - resAddAdditionalDependants(pClient, (struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_KernelGraphicsContext_RsResource.offset), pReference); -} - static NvU32 __nvoc_thunk_RsResource_kgrctxGetRefCount(struct KernelGraphicsContext *pResource) { return resGetRefCount((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_KernelGraphicsContext_RsResource.offset)); } -static NV_STATUS __nvoc_thunk_RmResource_kgrctxCheckMemInterUnmap(struct KernelGraphicsContext *pRmResource, NvBool bSubdeviceHandleProvided) { - return rmresCheckMemInterUnmap((struct RmResource *)(((unsigned char *)pRmResource) + __nvoc_rtti_KernelGraphicsContext_RmResource.offset), bSubdeviceHandleProvided); -} - -static NV_STATUS __nvoc_thunk_RsResource_kgrctxMapTo(struct KernelGraphicsContext *pResource, RS_RES_MAP_TO_PARAMS *pParams) { - return resMapTo((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_KernelGraphicsContext_RsResource.offset), pParams); +static void __nvoc_thunk_RsResource_kgrctxAddAdditionalDependants(struct RsClient *pClient, struct KernelGraphicsContext *pResource, RsResourceRef *pReference) { + resAddAdditionalDependants(pClient, (struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_KernelGraphicsContext_RsResource.offset), pReference); } static NV_STATUS __nvoc_thunk_RmResource_kgrctxControl_Prologue(struct KernelGraphicsContext *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { @@ -157,18 +137,10 @@ return gpuresInternalControlForward((struct GpuResource *)(((unsigned char *)pGpuResource) + __nvoc_rtti_KernelGraphicsContext_GpuResource.offset), command, pParams, size); } -static void __nvoc_thunk_RsResource_kgrctxPreDestruct(struct KernelGraphicsContext *pResource) { - resPreDestruct((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_KernelGraphicsContext_RsResource.offset)); -} - static NV_STATUS __nvoc_thunk_RsResource_kgrctxUnmapFrom(struct KernelGraphicsContext *pResource, RS_RES_UNMAP_FROM_PARAMS *pParams) { return resUnmapFrom((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_KernelGraphicsContext_RsResource.offset), pParams); } -static NV_STATUS __nvoc_thunk_RsResource_kgrctxIsDuplicate(struct KernelGraphicsContext *pResource, NvHandle hMemory, NvBool *pDuplicate) { - return resIsDuplicate((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_KernelGraphicsContext_RsResource.offset), hMemory, pDuplicate); -} - static void __nvoc_thunk_RmResource_kgrctxControl_Epilogue(struct KernelGraphicsContext *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { rmresControl_Epilogue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_KernelGraphicsContext_RmResource.offset), pCallContext, pParams); } @@ -177,6 +149,42 @@ return resControlLookup((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_KernelGraphicsContext_RsResource.offset), pParams, ppEntry); } +static NV_STATUS __nvoc_thunk_GpuResource_kgrctxControl(struct KernelGraphicsContext *pGpuResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return gpuresControl((struct GpuResource *)(((unsigned char *)pGpuResource) + __nvoc_rtti_KernelGraphicsContext_GpuResource.offset), pCallContext, pParams); +} + +static NV_STATUS __nvoc_thunk_GpuResource_kgrctxUnmap(struct KernelGraphicsContext *pGpuResource, struct CALL_CONTEXT *pCallContext, struct RsCpuMapping *pCpuMapping) { + return gpuresUnmap((struct GpuResource *)(((unsigned char *)pGpuResource) + __nvoc_rtti_KernelGraphicsContext_GpuResource.offset), pCallContext, pCpuMapping); +} + +static NV_STATUS __nvoc_thunk_RmResource_kgrctxGetMemInterMapParams(struct KernelGraphicsContext *pRmResource, RMRES_MEM_INTER_MAP_PARAMS *pParams) { + return rmresGetMemInterMapParams((struct RmResource *)(((unsigned char *)pRmResource) + __nvoc_rtti_KernelGraphicsContext_RmResource.offset), pParams); +} + +static NV_STATUS __nvoc_thunk_RmResource_kgrctxGetMemoryMappingDescriptor(struct KernelGraphicsContext *pRmResource, struct MEMORY_DESCRIPTOR **ppMemDesc) { + return rmresGetMemoryMappingDescriptor((struct RmResource *)(((unsigned char *)pRmResource) + __nvoc_rtti_KernelGraphicsContext_RmResource.offset), ppMemDesc); +} + +static NV_STATUS __nvoc_thunk_RsResource_kgrctxControlFilter(struct KernelGraphicsContext *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return resControlFilter((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_KernelGraphicsContext_RsResource.offset), pCallContext, pParams); +} + +static NV_STATUS __nvoc_thunk_RmResource_kgrctxControlSerialization_Prologue(struct KernelGraphicsContext *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return rmresControlSerialization_Prologue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_KernelGraphicsContext_RmResource.offset), pCallContext, pParams); +} + +static void __nvoc_thunk_RsResource_kgrctxPreDestruct(struct KernelGraphicsContext *pResource) { + resPreDestruct((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_KernelGraphicsContext_RsResource.offset)); +} + +static NV_STATUS __nvoc_thunk_RsResource_kgrctxIsDuplicate(struct KernelGraphicsContext *pResource, NvHandle hMemory, NvBool *pDuplicate) { + return resIsDuplicate((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_KernelGraphicsContext_RsResource.offset), hMemory, pDuplicate); +} + +static void __nvoc_thunk_RmResource_kgrctxControlSerialization_Epilogue(struct KernelGraphicsContext *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + rmresControlSerialization_Epilogue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_KernelGraphicsContext_RmResource.offset), pCallContext, pParams); +} + static NV_STATUS __nvoc_thunk_GpuResource_kgrctxMap(struct KernelGraphicsContext *pGpuResource, struct CALL_CONTEXT *pCallContext, struct RS_CPU_MAP_PARAMS *pParams, struct RsCpuMapping *pCpuMapping) { return gpuresMap((struct GpuResource *)(((unsigned char *)pGpuResource) + __nvoc_rtti_KernelGraphicsContext_GpuResource.offset), pCallContext, pParams, pCpuMapping); } @@ -337,25 +345,15 @@ pThis->__kgrctxShareCallback__ = &__nvoc_thunk_GpuResource_kgrctxShareCallback; - pThis->__kgrctxControl__ = &__nvoc_thunk_GpuResource_kgrctxControl; - - pThis->__kgrctxUnmap__ = &__nvoc_thunk_GpuResource_kgrctxUnmap; - - pThis->__kgrctxGetMemInterMapParams__ = &__nvoc_thunk_RmResource_kgrctxGetMemInterMapParams; + pThis->__kgrctxCheckMemInterUnmap__ = &__nvoc_thunk_RmResource_kgrctxCheckMemInterUnmap; - pThis->__kgrctxGetMemoryMappingDescriptor__ = &__nvoc_thunk_RmResource_kgrctxGetMemoryMappingDescriptor; + pThis->__kgrctxMapTo__ = &__nvoc_thunk_RsResource_kgrctxMapTo; pThis->__kgrctxGetMapAddrSpace__ = &__nvoc_thunk_GpuResource_kgrctxGetMapAddrSpace; - pThis->__kgrctxControlFilter__ = &__nvoc_thunk_RsResource_kgrctxControlFilter; - - pThis->__kgrctxAddAdditionalDependants__ = &__nvoc_thunk_RsResource_kgrctxAddAdditionalDependants; - pThis->__kgrctxGetRefCount__ = &__nvoc_thunk_RsResource_kgrctxGetRefCount; - pThis->__kgrctxCheckMemInterUnmap__ = &__nvoc_thunk_RmResource_kgrctxCheckMemInterUnmap; - - pThis->__kgrctxMapTo__ = &__nvoc_thunk_RsResource_kgrctxMapTo; + pThis->__kgrctxAddAdditionalDependants__ = &__nvoc_thunk_RsResource_kgrctxAddAdditionalDependants; pThis->__kgrctxControl_Prologue__ = &__nvoc_thunk_RmResource_kgrctxControl_Prologue; @@ -363,16 +361,30 @@ pThis->__kgrctxInternalControlForward__ = &__nvoc_thunk_GpuResource_kgrctxInternalControlForward; - pThis->__kgrctxPreDestruct__ = &__nvoc_thunk_RsResource_kgrctxPreDestruct; - pThis->__kgrctxUnmapFrom__ = &__nvoc_thunk_RsResource_kgrctxUnmapFrom; - pThis->__kgrctxIsDuplicate__ = &__nvoc_thunk_RsResource_kgrctxIsDuplicate; - pThis->__kgrctxControl_Epilogue__ = &__nvoc_thunk_RmResource_kgrctxControl_Epilogue; pThis->__kgrctxControlLookup__ = &__nvoc_thunk_RsResource_kgrctxControlLookup; + pThis->__kgrctxControl__ = &__nvoc_thunk_GpuResource_kgrctxControl; + + pThis->__kgrctxUnmap__ = &__nvoc_thunk_GpuResource_kgrctxUnmap; + + pThis->__kgrctxGetMemInterMapParams__ = &__nvoc_thunk_RmResource_kgrctxGetMemInterMapParams; + + pThis->__kgrctxGetMemoryMappingDescriptor__ = &__nvoc_thunk_RmResource_kgrctxGetMemoryMappingDescriptor; + + pThis->__kgrctxControlFilter__ = &__nvoc_thunk_RsResource_kgrctxControlFilter; + + pThis->__kgrctxControlSerialization_Prologue__ = &__nvoc_thunk_RmResource_kgrctxControlSerialization_Prologue; + + pThis->__kgrctxPreDestruct__ = &__nvoc_thunk_RsResource_kgrctxPreDestruct; + + pThis->__kgrctxIsDuplicate__ = &__nvoc_thunk_RsResource_kgrctxIsDuplicate; + + pThis->__kgrctxControlSerialization_Epilogue__ = &__nvoc_thunk_RmResource_kgrctxControlSerialization_Epilogue; + pThis->__kgrctxMap__ = &__nvoc_thunk_GpuResource_kgrctxMap; pThis->__kgrctxAccessCallback__ = &__nvoc_thunk_RmResource_kgrctxAccessCallback; @@ -400,13 +412,16 @@ KernelGraphicsContext *pThis; RmHalspecOwner *pRmhalspecowner; - pThis = portMemAllocNonPaged(sizeof(KernelGraphicsContext)); - if (pThis == NULL) return NV_ERR_NO_MEMORY; + status = __nvoc_handleObjCreateMemAlloc(createFlags, sizeof(KernelGraphicsContext), (void**)&pThis, (void**)ppThis); + if (status != NV_OK) + return status; portMemSet(pThis, 0, sizeof(KernelGraphicsContext)); __nvoc_initRtti(staticCast(pThis, Dynamic), &__nvoc_class_def_KernelGraphicsContext); + pThis->__nvoc_base_GpuResource.__nvoc_base_RmResource.__nvoc_base_RsResource.__nvoc_base_Object.createFlags = createFlags; + if (pParent != NULL && !(createFlags & NVOC_OBJ_CREATE_FLAGS_PARENT_HALSPEC_ONLY)) { pParentObj = dynamicCast(pParent, Object); @@ -426,11 +441,17 @@ if (status != NV_OK) goto __nvoc_objCreate_KernelGraphicsContext_cleanup; *ppThis = pThis; + return NV_OK; __nvoc_objCreate_KernelGraphicsContext_cleanup: // do not call destructors here since the constructor already called them - portMemFree(pThis); + if (createFlags & NVOC_OBJ_CREATE_FLAGS_IN_PLACE_CONSTRUCT) + portMemSet(pThis, 0, sizeof(KernelGraphicsContext)); + else + portMemFree(pThis); + + // coverity[leaked_storage:FALSE] return status; } @@ -561,13 +582,16 @@ Object *pParentObj; KernelGraphicsContextShared *pThis; - pThis = portMemAllocNonPaged(sizeof(KernelGraphicsContextShared)); - if (pThis == NULL) return NV_ERR_NO_MEMORY; + status = __nvoc_handleObjCreateMemAlloc(createFlags, sizeof(KernelGraphicsContextShared), (void**)&pThis, (void**)ppThis); + if (status != NV_OK) + return status; portMemSet(pThis, 0, sizeof(KernelGraphicsContextShared)); __nvoc_initRtti(staticCast(pThis, Dynamic), &__nvoc_class_def_KernelGraphicsContextShared); + pThis->__nvoc_base_RsShared.__nvoc_base_Object.createFlags = createFlags; + if (pParent != NULL && !(createFlags & NVOC_OBJ_CREATE_FLAGS_PARENT_HALSPEC_ONLY)) { pParentObj = dynamicCast(pParent, Object); @@ -583,11 +607,17 @@ if (status != NV_OK) goto __nvoc_objCreate_KernelGraphicsContextShared_cleanup; *ppThis = pThis; + return NV_OK; __nvoc_objCreate_KernelGraphicsContextShared_cleanup: // do not call destructors here since the constructor already called them - portMemFree(pThis); + if (createFlags & NVOC_OBJ_CREATE_FLAGS_IN_PLACE_CONSTRUCT) + portMemSet(pThis, 0, sizeof(KernelGraphicsContextShared)); + else + portMemFree(pThis); + + // coverity[leaked_storage:FALSE] return status; } diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/generated/g_kernel_graphics_context_nvoc.h nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_kernel_graphics_context_nvoc.h --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/generated/g_kernel_graphics_context_nvoc.h 2023-10-25 20:27:07.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_kernel_graphics_context_nvoc.h 2024-03-05 22:18:27.000000000 +0000 @@ -7,7 +7,7 @@ #endif /* - * SPDX-FileCopyrightText: Copyright (c) 2020-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2020-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -97,9 +97,6 @@ // Tracks whether Physical has initialized the memory descriptor for the promoted Kernel buffer NvBool bInitialized[GR_GLOBALCTX_BUFFER_COUNT]; - - // Check if vGPU Guest is running with FECS Trace feature supported driver - NvBool bFecsTraceUnsupportedInGuest; } GR_GLOBALCTX_BUFFERS; struct KernelGraphicsContextUnicast; @@ -169,27 +166,29 @@ NV_STATUS (*__kgrctxCtrlGetMMUDebugMode__)(struct KernelGraphicsContext *, NV0090_CTRL_GET_MMU_DEBUG_MODE_PARAMS *); NV_STATUS (*__kgrctxCtrlProgramVidmemPromote__)(struct KernelGraphicsContext *, NV0090_CTRL_PROGRAM_VIDMEM_PROMOTE_PARAMS *); NvBool (*__kgrctxShareCallback__)(struct KernelGraphicsContext *, struct RsClient *, struct RsResourceRef *, RS_SHARE_POLICY *); - NV_STATUS (*__kgrctxControl__)(struct KernelGraphicsContext *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); - NV_STATUS (*__kgrctxUnmap__)(struct KernelGraphicsContext *, struct CALL_CONTEXT *, struct RsCpuMapping *); - NV_STATUS (*__kgrctxGetMemInterMapParams__)(struct KernelGraphicsContext *, RMRES_MEM_INTER_MAP_PARAMS *); - NV_STATUS (*__kgrctxGetMemoryMappingDescriptor__)(struct KernelGraphicsContext *, struct MEMORY_DESCRIPTOR **); - NV_STATUS (*__kgrctxGetMapAddrSpace__)(struct KernelGraphicsContext *, struct CALL_CONTEXT *, NvU32, NV_ADDRESS_SPACE *); - NV_STATUS (*__kgrctxControlFilter__)(struct KernelGraphicsContext *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); - void (*__kgrctxAddAdditionalDependants__)(struct RsClient *, struct KernelGraphicsContext *, RsResourceRef *); - NvU32 (*__kgrctxGetRefCount__)(struct KernelGraphicsContext *); NV_STATUS (*__kgrctxCheckMemInterUnmap__)(struct KernelGraphicsContext *, NvBool); NV_STATUS (*__kgrctxMapTo__)(struct KernelGraphicsContext *, RS_RES_MAP_TO_PARAMS *); + NV_STATUS (*__kgrctxGetMapAddrSpace__)(struct KernelGraphicsContext *, struct CALL_CONTEXT *, NvU32, NV_ADDRESS_SPACE *); + NvU32 (*__kgrctxGetRefCount__)(struct KernelGraphicsContext *); + void (*__kgrctxAddAdditionalDependants__)(struct RsClient *, struct KernelGraphicsContext *, RsResourceRef *); NV_STATUS (*__kgrctxControl_Prologue__)(struct KernelGraphicsContext *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); NV_STATUS (*__kgrctxGetRegBaseOffsetAndSize__)(struct KernelGraphicsContext *, struct OBJGPU *, NvU32 *, NvU32 *); NV_STATUS (*__kgrctxInternalControlForward__)(struct KernelGraphicsContext *, NvU32, void *, NvU32); - void (*__kgrctxPreDestruct__)(struct KernelGraphicsContext *); NV_STATUS (*__kgrctxUnmapFrom__)(struct KernelGraphicsContext *, RS_RES_UNMAP_FROM_PARAMS *); - NV_STATUS (*__kgrctxIsDuplicate__)(struct KernelGraphicsContext *, NvHandle, NvBool *); void (*__kgrctxControl_Epilogue__)(struct KernelGraphicsContext *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); NV_STATUS (*__kgrctxControlLookup__)(struct KernelGraphicsContext *, struct RS_RES_CONTROL_PARAMS_INTERNAL *, const struct NVOC_EXPORTED_METHOD_DEF **); + NV_STATUS (*__kgrctxControl__)(struct KernelGraphicsContext *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); + NV_STATUS (*__kgrctxUnmap__)(struct KernelGraphicsContext *, struct CALL_CONTEXT *, struct RsCpuMapping *); + NV_STATUS (*__kgrctxGetMemInterMapParams__)(struct KernelGraphicsContext *, RMRES_MEM_INTER_MAP_PARAMS *); + NV_STATUS (*__kgrctxGetMemoryMappingDescriptor__)(struct KernelGraphicsContext *, struct MEMORY_DESCRIPTOR **); + NV_STATUS (*__kgrctxControlFilter__)(struct KernelGraphicsContext *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); + NV_STATUS (*__kgrctxControlSerialization_Prologue__)(struct KernelGraphicsContext *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); + void (*__kgrctxPreDestruct__)(struct KernelGraphicsContext *); + NV_STATUS (*__kgrctxIsDuplicate__)(struct KernelGraphicsContext *, NvHandle, NvBool *); + void (*__kgrctxControlSerialization_Epilogue__)(struct KernelGraphicsContext *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); NV_STATUS (*__kgrctxMap__)(struct KernelGraphicsContext *, struct CALL_CONTEXT *, struct RS_CPU_MAP_PARAMS *, struct RsCpuMapping *); NvBool (*__kgrctxAccessCallback__)(struct KernelGraphicsContext *, struct RsClient *, void *, RsAccessRight); - struct KernelGraphicsContextShared *pShared; + struct KernelGraphicsContextShared *PRIVATE_FIELD(pShared); }; #ifndef __NVOC_CLASS_KernelGraphicsContext_TYPEDEF__ @@ -227,24 +226,26 @@ #define kgrctxCtrlGetMMUDebugMode(pKernelGraphicsContext, pParams) kgrctxCtrlGetMMUDebugMode_DISPATCH(pKernelGraphicsContext, pParams) #define kgrctxCtrlProgramVidmemPromote(pKernelGraphicsContext, pParams) kgrctxCtrlProgramVidmemPromote_DISPATCH(pKernelGraphicsContext, pParams) #define kgrctxShareCallback(pGpuResource, pInvokingClient, pParentRef, pSharePolicy) kgrctxShareCallback_DISPATCH(pGpuResource, pInvokingClient, pParentRef, pSharePolicy) -#define kgrctxControl(pGpuResource, pCallContext, pParams) kgrctxControl_DISPATCH(pGpuResource, pCallContext, pParams) -#define kgrctxUnmap(pGpuResource, pCallContext, pCpuMapping) kgrctxUnmap_DISPATCH(pGpuResource, pCallContext, pCpuMapping) -#define kgrctxGetMemInterMapParams(pRmResource, pParams) kgrctxGetMemInterMapParams_DISPATCH(pRmResource, pParams) -#define kgrctxGetMemoryMappingDescriptor(pRmResource, ppMemDesc) kgrctxGetMemoryMappingDescriptor_DISPATCH(pRmResource, ppMemDesc) -#define kgrctxGetMapAddrSpace(pGpuResource, pCallContext, mapFlags, pAddrSpace) kgrctxGetMapAddrSpace_DISPATCH(pGpuResource, pCallContext, mapFlags, pAddrSpace) -#define kgrctxControlFilter(pResource, pCallContext, pParams) kgrctxControlFilter_DISPATCH(pResource, pCallContext, pParams) -#define kgrctxAddAdditionalDependants(pClient, pResource, pReference) kgrctxAddAdditionalDependants_DISPATCH(pClient, pResource, pReference) -#define kgrctxGetRefCount(pResource) kgrctxGetRefCount_DISPATCH(pResource) #define kgrctxCheckMemInterUnmap(pRmResource, bSubdeviceHandleProvided) kgrctxCheckMemInterUnmap_DISPATCH(pRmResource, bSubdeviceHandleProvided) #define kgrctxMapTo(pResource, pParams) kgrctxMapTo_DISPATCH(pResource, pParams) +#define kgrctxGetMapAddrSpace(pGpuResource, pCallContext, mapFlags, pAddrSpace) kgrctxGetMapAddrSpace_DISPATCH(pGpuResource, pCallContext, mapFlags, pAddrSpace) +#define kgrctxGetRefCount(pResource) kgrctxGetRefCount_DISPATCH(pResource) +#define kgrctxAddAdditionalDependants(pClient, pResource, pReference) kgrctxAddAdditionalDependants_DISPATCH(pClient, pResource, pReference) #define kgrctxControl_Prologue(pResource, pCallContext, pParams) kgrctxControl_Prologue_DISPATCH(pResource, pCallContext, pParams) #define kgrctxGetRegBaseOffsetAndSize(pGpuResource, pGpu, pOffset, pSize) kgrctxGetRegBaseOffsetAndSize_DISPATCH(pGpuResource, pGpu, pOffset, pSize) #define kgrctxInternalControlForward(pGpuResource, command, pParams, size) kgrctxInternalControlForward_DISPATCH(pGpuResource, command, pParams, size) -#define kgrctxPreDestruct(pResource) kgrctxPreDestruct_DISPATCH(pResource) #define kgrctxUnmapFrom(pResource, pParams) kgrctxUnmapFrom_DISPATCH(pResource, pParams) -#define kgrctxIsDuplicate(pResource, hMemory, pDuplicate) kgrctxIsDuplicate_DISPATCH(pResource, hMemory, pDuplicate) #define kgrctxControl_Epilogue(pResource, pCallContext, pParams) kgrctxControl_Epilogue_DISPATCH(pResource, pCallContext, pParams) #define kgrctxControlLookup(pResource, pParams, ppEntry) kgrctxControlLookup_DISPATCH(pResource, pParams, ppEntry) +#define kgrctxControl(pGpuResource, pCallContext, pParams) kgrctxControl_DISPATCH(pGpuResource, pCallContext, pParams) +#define kgrctxUnmap(pGpuResource, pCallContext, pCpuMapping) kgrctxUnmap_DISPATCH(pGpuResource, pCallContext, pCpuMapping) +#define kgrctxGetMemInterMapParams(pRmResource, pParams) kgrctxGetMemInterMapParams_DISPATCH(pRmResource, pParams) +#define kgrctxGetMemoryMappingDescriptor(pRmResource, ppMemDesc) kgrctxGetMemoryMappingDescriptor_DISPATCH(pRmResource, ppMemDesc) +#define kgrctxControlFilter(pResource, pCallContext, pParams) kgrctxControlFilter_DISPATCH(pResource, pCallContext, pParams) +#define kgrctxControlSerialization_Prologue(pResource, pCallContext, pParams) kgrctxControlSerialization_Prologue_DISPATCH(pResource, pCallContext, pParams) +#define kgrctxPreDestruct(pResource) kgrctxPreDestruct_DISPATCH(pResource) +#define kgrctxIsDuplicate(pResource, hMemory, pDuplicate) kgrctxIsDuplicate_DISPATCH(pResource, hMemory, pDuplicate) +#define kgrctxControlSerialization_Epilogue(pResource, pCallContext, pParams) kgrctxControlSerialization_Epilogue_DISPATCH(pResource, pCallContext, pParams) #define kgrctxMap(pGpuResource, pCallContext, pParams, pCpuMapping) kgrctxMap_DISPATCH(pGpuResource, pCallContext, pParams, pCpuMapping) #define kgrctxAccessCallback(pResource, pInvokingClient, pAllocParams, accessRight) kgrctxAccessCallback_DISPATCH(pResource, pInvokingClient, pAllocParams, accessRight) NvBool kgrctxShouldManageCtxBuffers_KERNEL(struct OBJGPU *arg0, struct KernelGraphicsContext *arg1, NvU32 gfid); @@ -400,44 +401,24 @@ return pGpuResource->__kgrctxShareCallback__(pGpuResource, pInvokingClient, pParentRef, pSharePolicy); } -static inline NV_STATUS kgrctxControl_DISPATCH(struct KernelGraphicsContext *pGpuResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { - return pGpuResource->__kgrctxControl__(pGpuResource, pCallContext, pParams); -} - -static inline NV_STATUS kgrctxUnmap_DISPATCH(struct KernelGraphicsContext *pGpuResource, struct CALL_CONTEXT *pCallContext, struct RsCpuMapping *pCpuMapping) { - return pGpuResource->__kgrctxUnmap__(pGpuResource, pCallContext, pCpuMapping); -} - -static inline NV_STATUS kgrctxGetMemInterMapParams_DISPATCH(struct KernelGraphicsContext *pRmResource, RMRES_MEM_INTER_MAP_PARAMS *pParams) { - return pRmResource->__kgrctxGetMemInterMapParams__(pRmResource, pParams); +static inline NV_STATUS kgrctxCheckMemInterUnmap_DISPATCH(struct KernelGraphicsContext *pRmResource, NvBool bSubdeviceHandleProvided) { + return pRmResource->__kgrctxCheckMemInterUnmap__(pRmResource, bSubdeviceHandleProvided); } -static inline NV_STATUS kgrctxGetMemoryMappingDescriptor_DISPATCH(struct KernelGraphicsContext *pRmResource, struct MEMORY_DESCRIPTOR **ppMemDesc) { - return pRmResource->__kgrctxGetMemoryMappingDescriptor__(pRmResource, ppMemDesc); +static inline NV_STATUS kgrctxMapTo_DISPATCH(struct KernelGraphicsContext *pResource, RS_RES_MAP_TO_PARAMS *pParams) { + return pResource->__kgrctxMapTo__(pResource, pParams); } static inline NV_STATUS kgrctxGetMapAddrSpace_DISPATCH(struct KernelGraphicsContext *pGpuResource, struct CALL_CONTEXT *pCallContext, NvU32 mapFlags, NV_ADDRESS_SPACE *pAddrSpace) { return pGpuResource->__kgrctxGetMapAddrSpace__(pGpuResource, pCallContext, mapFlags, pAddrSpace); } -static inline NV_STATUS kgrctxControlFilter_DISPATCH(struct KernelGraphicsContext *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { - return pResource->__kgrctxControlFilter__(pResource, pCallContext, pParams); -} - -static inline void kgrctxAddAdditionalDependants_DISPATCH(struct RsClient *pClient, struct KernelGraphicsContext *pResource, RsResourceRef *pReference) { - pResource->__kgrctxAddAdditionalDependants__(pClient, pResource, pReference); -} - static inline NvU32 kgrctxGetRefCount_DISPATCH(struct KernelGraphicsContext *pResource) { return pResource->__kgrctxGetRefCount__(pResource); } -static inline NV_STATUS kgrctxCheckMemInterUnmap_DISPATCH(struct KernelGraphicsContext *pRmResource, NvBool bSubdeviceHandleProvided) { - return pRmResource->__kgrctxCheckMemInterUnmap__(pRmResource, bSubdeviceHandleProvided); -} - -static inline NV_STATUS kgrctxMapTo_DISPATCH(struct KernelGraphicsContext *pResource, RS_RES_MAP_TO_PARAMS *pParams) { - return pResource->__kgrctxMapTo__(pResource, pParams); +static inline void kgrctxAddAdditionalDependants_DISPATCH(struct RsClient *pClient, struct KernelGraphicsContext *pResource, RsResourceRef *pReference) { + pResource->__kgrctxAddAdditionalDependants__(pClient, pResource, pReference); } static inline NV_STATUS kgrctxControl_Prologue_DISPATCH(struct KernelGraphicsContext *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { @@ -452,18 +433,10 @@ return pGpuResource->__kgrctxInternalControlForward__(pGpuResource, command, pParams, size); } -static inline void kgrctxPreDestruct_DISPATCH(struct KernelGraphicsContext *pResource) { - pResource->__kgrctxPreDestruct__(pResource); -} - static inline NV_STATUS kgrctxUnmapFrom_DISPATCH(struct KernelGraphicsContext *pResource, RS_RES_UNMAP_FROM_PARAMS *pParams) { return pResource->__kgrctxUnmapFrom__(pResource, pParams); } -static inline NV_STATUS kgrctxIsDuplicate_DISPATCH(struct KernelGraphicsContext *pResource, NvHandle hMemory, NvBool *pDuplicate) { - return pResource->__kgrctxIsDuplicate__(pResource, hMemory, pDuplicate); -} - static inline void kgrctxControl_Epilogue_DISPATCH(struct KernelGraphicsContext *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { pResource->__kgrctxControl_Epilogue__(pResource, pCallContext, pParams); } @@ -472,6 +445,42 @@ return pResource->__kgrctxControlLookup__(pResource, pParams, ppEntry); } +static inline NV_STATUS kgrctxControl_DISPATCH(struct KernelGraphicsContext *pGpuResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return pGpuResource->__kgrctxControl__(pGpuResource, pCallContext, pParams); +} + +static inline NV_STATUS kgrctxUnmap_DISPATCH(struct KernelGraphicsContext *pGpuResource, struct CALL_CONTEXT *pCallContext, struct RsCpuMapping *pCpuMapping) { + return pGpuResource->__kgrctxUnmap__(pGpuResource, pCallContext, pCpuMapping); +} + +static inline NV_STATUS kgrctxGetMemInterMapParams_DISPATCH(struct KernelGraphicsContext *pRmResource, RMRES_MEM_INTER_MAP_PARAMS *pParams) { + return pRmResource->__kgrctxGetMemInterMapParams__(pRmResource, pParams); +} + +static inline NV_STATUS kgrctxGetMemoryMappingDescriptor_DISPATCH(struct KernelGraphicsContext *pRmResource, struct MEMORY_DESCRIPTOR **ppMemDesc) { + return pRmResource->__kgrctxGetMemoryMappingDescriptor__(pRmResource, ppMemDesc); +} + +static inline NV_STATUS kgrctxControlFilter_DISPATCH(struct KernelGraphicsContext *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return pResource->__kgrctxControlFilter__(pResource, pCallContext, pParams); +} + +static inline NV_STATUS kgrctxControlSerialization_Prologue_DISPATCH(struct KernelGraphicsContext *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return pResource->__kgrctxControlSerialization_Prologue__(pResource, pCallContext, pParams); +} + +static inline void kgrctxPreDestruct_DISPATCH(struct KernelGraphicsContext *pResource) { + pResource->__kgrctxPreDestruct__(pResource); +} + +static inline NV_STATUS kgrctxIsDuplicate_DISPATCH(struct KernelGraphicsContext *pResource, NvHandle hMemory, NvBool *pDuplicate) { + return pResource->__kgrctxIsDuplicate__(pResource, hMemory, pDuplicate); +} + +static inline void kgrctxControlSerialization_Epilogue_DISPATCH(struct KernelGraphicsContext *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + pResource->__kgrctxControlSerialization_Epilogue__(pResource, pCallContext, pParams); +} + static inline NV_STATUS kgrctxMap_DISPATCH(struct KernelGraphicsContext *pGpuResource, struct CALL_CONTEXT *pCallContext, struct RS_CPU_MAP_PARAMS *pParams, struct RsCpuMapping *pCpuMapping) { return pGpuResource->__kgrctxMap__(pGpuResource, pCallContext, pParams, pCpuMapping); } @@ -578,6 +587,17 @@ #define kgrctxRecordMmuFault(arg0, arg1, mmuFaultInfo, mmuFaultAddress, mmuFaultType, mmuFaultAccessType) kgrctxRecordMmuFault_IMPL(arg0, arg1, mmuFaultInfo, mmuFaultAddress, mmuFaultType, mmuFaultAccessType) #endif //__nvoc_kernel_graphics_context_h_disabled +NvBool kgrctxIsValid_IMPL(struct OBJGPU *arg0, struct KernelGraphicsContext *arg1, struct KernelChannel *arg2); + +#ifdef __nvoc_kernel_graphics_context_h_disabled +static inline NvBool kgrctxIsValid(struct OBJGPU *arg0, struct KernelGraphicsContext *arg1, struct KernelChannel *arg2) { + NV_ASSERT_FAILED_PRECOMP("KernelGraphicsContext was disabled!"); + return NV_FALSE; +} +#else //__nvoc_kernel_graphics_context_h_disabled +#define kgrctxIsValid(arg0, arg1, arg2) kgrctxIsValid_IMPL(arg0, arg1, arg2) +#endif //__nvoc_kernel_graphics_context_h_disabled + NvBool kgrctxIsMainContextAllocated_IMPL(struct OBJGPU *arg0, struct KernelGraphicsContext *arg1); #ifdef __nvoc_kernel_graphics_context_h_disabled @@ -904,17 +924,6 @@ #define kgrctxFreeAssociatedCtxBuffers(arg0, arg1) kgrctxFreeAssociatedCtxBuffers_IMPL(arg0, arg1) #endif //__nvoc_kernel_graphics_context_h_disabled -NvBool kgrctxIsFinalGlobalBufMapRefDuped_IMPL(struct OBJGPU *arg0, struct KernelGraphicsContext *arg1, struct KernelChannel *arg2, GR_GLOBALCTX_BUFFER bufId); - -#ifdef __nvoc_kernel_graphics_context_h_disabled -static inline NvBool kgrctxIsFinalGlobalBufMapRefDuped(struct OBJGPU *arg0, struct KernelGraphicsContext *arg1, struct KernelChannel *arg2, GR_GLOBALCTX_BUFFER bufId) { - NV_ASSERT_FAILED_PRECOMP("KernelGraphicsContext was disabled!"); - return NV_FALSE; -} -#else //__nvoc_kernel_graphics_context_h_disabled -#define kgrctxIsFinalGlobalBufMapRefDuped(arg0, arg1, arg2, bufId) kgrctxIsFinalGlobalBufMapRefDuped_IMPL(arg0, arg1, arg2, bufId) -#endif //__nvoc_kernel_graphics_context_h_disabled - #undef PRIVATE_FIELD @@ -961,7 +970,7 @@ struct Object *__nvoc_pbase_Object; struct RsShared *__nvoc_pbase_RsShared; struct KernelGraphicsContextShared *__nvoc_pbase_KernelGraphicsContextShared; - struct KernelGraphicsContextUnicast *pKernelGraphicsContextUnicast; + struct KernelGraphicsContextUnicast PRIVATE_FIELD(kernelGraphicsContextUnicast); }; #ifndef __NVOC_CLASS_KernelGraphicsContextShared_TYPEDEF__ diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/generated/g_kernel_graphics_manager_nvoc.c nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_kernel_graphics_manager_nvoc.c --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/generated/g_kernel_graphics_manager_nvoc.c 2023-10-25 20:27:08.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_kernel_graphics_manager_nvoc.c 2024-03-05 22:18:27.000000000 +0000 @@ -70,10 +70,6 @@ return kgrmgrConstructEngine(arg0, (struct KernelGraphicsManager *)(((unsigned char *)arg1) - __nvoc_rtti_KernelGraphicsManager_OBJENGSTATE.offset), arg2); } -static NV_STATUS __nvoc_thunk_OBJENGSTATE_kgrmgrReconcileTunableState(POBJGPU pGpu, struct KernelGraphicsManager *pEngstate, void *pTunableState) { - return engstateReconcileTunableState(pGpu, (struct OBJENGSTATE *)(((unsigned char *)pEngstate) + __nvoc_rtti_KernelGraphicsManager_OBJENGSTATE.offset), pTunableState); -} - static NV_STATUS __nvoc_thunk_OBJENGSTATE_kgrmgrStateLoad(POBJGPU pGpu, struct KernelGraphicsManager *pEngstate, NvU32 arg0) { return engstateStateLoad(pGpu, (struct OBJENGSTATE *)(((unsigned char *)pEngstate) + __nvoc_rtti_KernelGraphicsManager_OBJENGSTATE.offset), arg0); } @@ -118,30 +114,10 @@ return engstateStatePreInitUnlocked(pGpu, (struct OBJENGSTATE *)(((unsigned char *)pEngstate) + __nvoc_rtti_KernelGraphicsManager_OBJENGSTATE.offset)); } -static NV_STATUS __nvoc_thunk_OBJENGSTATE_kgrmgrGetTunableState(POBJGPU pGpu, struct KernelGraphicsManager *pEngstate, void *pTunableState) { - return engstateGetTunableState(pGpu, (struct OBJENGSTATE *)(((unsigned char *)pEngstate) + __nvoc_rtti_KernelGraphicsManager_OBJENGSTATE.offset), pTunableState); -} - -static NV_STATUS __nvoc_thunk_OBJENGSTATE_kgrmgrCompareTunableState(POBJGPU pGpu, struct KernelGraphicsManager *pEngstate, void *pTunables1, void *pTunables2) { - return engstateCompareTunableState(pGpu, (struct OBJENGSTATE *)(((unsigned char *)pEngstate) + __nvoc_rtti_KernelGraphicsManager_OBJENGSTATE.offset), pTunables1, pTunables2); -} - -static void __nvoc_thunk_OBJENGSTATE_kgrmgrFreeTunableState(POBJGPU pGpu, struct KernelGraphicsManager *pEngstate, void *pTunableState) { - engstateFreeTunableState(pGpu, (struct OBJENGSTATE *)(((unsigned char *)pEngstate) + __nvoc_rtti_KernelGraphicsManager_OBJENGSTATE.offset), pTunableState); -} - static NV_STATUS __nvoc_thunk_OBJENGSTATE_kgrmgrStatePostLoad(POBJGPU pGpu, struct KernelGraphicsManager *pEngstate, NvU32 arg0) { return engstateStatePostLoad(pGpu, (struct OBJENGSTATE *)(((unsigned char *)pEngstate) + __nvoc_rtti_KernelGraphicsManager_OBJENGSTATE.offset), arg0); } -static NV_STATUS __nvoc_thunk_OBJENGSTATE_kgrmgrAllocTunableState(POBJGPU pGpu, struct KernelGraphicsManager *pEngstate, void **ppTunableState) { - return engstateAllocTunableState(pGpu, (struct OBJENGSTATE *)(((unsigned char *)pEngstate) + __nvoc_rtti_KernelGraphicsManager_OBJENGSTATE.offset), ppTunableState); -} - -static NV_STATUS __nvoc_thunk_OBJENGSTATE_kgrmgrSetTunableState(POBJGPU pGpu, struct KernelGraphicsManager *pEngstate, void *pTunableState) { - return engstateSetTunableState(pGpu, (struct OBJENGSTATE *)(((unsigned char *)pEngstate) + __nvoc_rtti_KernelGraphicsManager_OBJENGSTATE.offset), pTunableState); -} - static NvBool __nvoc_thunk_OBJENGSTATE_kgrmgrIsPresent(POBJGPU pGpu, struct KernelGraphicsManager *pEngstate) { return engstateIsPresent(pGpu, (struct OBJENGSTATE *)(((unsigned char *)pEngstate) + __nvoc_rtti_KernelGraphicsManager_OBJENGSTATE.offset)); } @@ -184,8 +160,6 @@ pThis->__nvoc_base_OBJENGSTATE.__engstateConstructEngine__ = &__nvoc_thunk_KernelGraphicsManager_engstateConstructEngine; - pThis->__kgrmgrReconcileTunableState__ = &__nvoc_thunk_OBJENGSTATE_kgrmgrReconcileTunableState; - pThis->__kgrmgrStateLoad__ = &__nvoc_thunk_OBJENGSTATE_kgrmgrStateLoad; pThis->__kgrmgrStateUnload__ = &__nvoc_thunk_OBJENGSTATE_kgrmgrStateUnload; @@ -208,18 +182,8 @@ pThis->__kgrmgrStatePreInitUnlocked__ = &__nvoc_thunk_OBJENGSTATE_kgrmgrStatePreInitUnlocked; - pThis->__kgrmgrGetTunableState__ = &__nvoc_thunk_OBJENGSTATE_kgrmgrGetTunableState; - - pThis->__kgrmgrCompareTunableState__ = &__nvoc_thunk_OBJENGSTATE_kgrmgrCompareTunableState; - - pThis->__kgrmgrFreeTunableState__ = &__nvoc_thunk_OBJENGSTATE_kgrmgrFreeTunableState; - pThis->__kgrmgrStatePostLoad__ = &__nvoc_thunk_OBJENGSTATE_kgrmgrStatePostLoad; - pThis->__kgrmgrAllocTunableState__ = &__nvoc_thunk_OBJENGSTATE_kgrmgrAllocTunableState; - - pThis->__kgrmgrSetTunableState__ = &__nvoc_thunk_OBJENGSTATE_kgrmgrSetTunableState; - pThis->__kgrmgrIsPresent__ = &__nvoc_thunk_OBJENGSTATE_kgrmgrIsPresent; } @@ -241,13 +205,16 @@ Object *pParentObj; KernelGraphicsManager *pThis; - pThis = portMemAllocNonPaged(sizeof(KernelGraphicsManager)); - if (pThis == NULL) return NV_ERR_NO_MEMORY; + status = __nvoc_handleObjCreateMemAlloc(createFlags, sizeof(KernelGraphicsManager), (void**)&pThis, (void**)ppThis); + if (status != NV_OK) + return status; portMemSet(pThis, 0, sizeof(KernelGraphicsManager)); __nvoc_initRtti(staticCast(pThis, Dynamic), &__nvoc_class_def_KernelGraphicsManager); + pThis->__nvoc_base_OBJENGSTATE.__nvoc_base_Object.createFlags = createFlags; + if (pParent != NULL && !(createFlags & NVOC_OBJ_CREATE_FLAGS_PARENT_HALSPEC_ONLY)) { pParentObj = dynamicCast(pParent, Object); @@ -263,11 +230,17 @@ if (status != NV_OK) goto __nvoc_objCreate_KernelGraphicsManager_cleanup; *ppThis = pThis; + return NV_OK; __nvoc_objCreate_KernelGraphicsManager_cleanup: // do not call destructors here since the constructor already called them - portMemFree(pThis); + if (createFlags & NVOC_OBJ_CREATE_FLAGS_IN_PLACE_CONSTRUCT) + portMemSet(pThis, 0, sizeof(KernelGraphicsManager)); + else + portMemFree(pThis); + + // coverity[leaked_storage:FALSE] return status; } diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/generated/g_kernel_graphics_manager_nvoc.h nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_kernel_graphics_manager_nvoc.h --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/generated/g_kernel_graphics_manager_nvoc.h 2023-10-25 20:27:08.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_kernel_graphics_manager_nvoc.h 2024-03-05 22:18:28.000000000 +0000 @@ -7,7 +7,7 @@ #endif /* - * SPDX-FileCopyrightText: Copyright (c) 2021-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2021-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -71,7 +71,6 @@ struct OBJENGSTATE *__nvoc_pbase_OBJENGSTATE; struct KernelGraphicsManager *__nvoc_pbase_KernelGraphicsManager; NV_STATUS (*__kgrmgrConstructEngine__)(struct OBJGPU *, struct KernelGraphicsManager *, ENGDESCRIPTOR); - NV_STATUS (*__kgrmgrReconcileTunableState__)(POBJGPU, struct KernelGraphicsManager *, void *); NV_STATUS (*__kgrmgrStateLoad__)(POBJGPU, struct KernelGraphicsManager *, NvU32); NV_STATUS (*__kgrmgrStateUnload__)(POBJGPU, struct KernelGraphicsManager *, NvU32); NV_STATUS (*__kgrmgrStateInitLocked__)(POBJGPU, struct KernelGraphicsManager *); @@ -83,12 +82,32 @@ void (*__kgrmgrInitMissing__)(POBJGPU, struct KernelGraphicsManager *); NV_STATUS (*__kgrmgrStatePreInitLocked__)(POBJGPU, struct KernelGraphicsManager *); NV_STATUS (*__kgrmgrStatePreInitUnlocked__)(POBJGPU, struct KernelGraphicsManager *); - NV_STATUS (*__kgrmgrGetTunableState__)(POBJGPU, struct KernelGraphicsManager *, void *); - NV_STATUS (*__kgrmgrCompareTunableState__)(POBJGPU, struct KernelGraphicsManager *, void *, void *); - void (*__kgrmgrFreeTunableState__)(POBJGPU, struct KernelGraphicsManager *, void *); NV_STATUS (*__kgrmgrStatePostLoad__)(POBJGPU, struct KernelGraphicsManager *, NvU32); - NV_STATUS (*__kgrmgrAllocTunableState__)(POBJGPU, struct KernelGraphicsManager *, void **); - NV_STATUS (*__kgrmgrSetTunableState__)(POBJGPU, struct KernelGraphicsManager *, void *); + NvBool (*__kgrmgrIsPresent__)(POBJGPU, struct KernelGraphicsManager *); + struct GRMGR_LEGACY_KGRAPHICS_STATIC_INFO PRIVATE_FIELD(legacyKgraphicsStaticInfo); + NvU64 PRIVATE_FIELD(veidInUseMask); + NvU64 PRIVATE_FIELD(grIdxVeidMask)[8]; + CTX_BUF_INFO PRIVATE_FIELD(globalCtxBufInfo)[10]; +}; +struct KernelGraphicsManager_PRIVATE { + const struct NVOC_RTTI *__nvoc_rtti; + struct OBJENGSTATE __nvoc_base_OBJENGSTATE; + struct Object *__nvoc_pbase_Object; + struct OBJENGSTATE *__nvoc_pbase_OBJENGSTATE; + struct KernelGraphicsManager *__nvoc_pbase_KernelGraphicsManager; + NV_STATUS (*__kgrmgrConstructEngine__)(struct OBJGPU *, struct KernelGraphicsManager *, ENGDESCRIPTOR); + NV_STATUS (*__kgrmgrStateLoad__)(POBJGPU, struct KernelGraphicsManager *, NvU32); + NV_STATUS (*__kgrmgrStateUnload__)(POBJGPU, struct KernelGraphicsManager *, NvU32); + NV_STATUS (*__kgrmgrStateInitLocked__)(POBJGPU, struct KernelGraphicsManager *); + NV_STATUS (*__kgrmgrStatePreLoad__)(POBJGPU, struct KernelGraphicsManager *, NvU32); + NV_STATUS (*__kgrmgrStatePostUnload__)(POBJGPU, struct KernelGraphicsManager *, NvU32); + void (*__kgrmgrStateDestroy__)(POBJGPU, struct KernelGraphicsManager *); + NV_STATUS (*__kgrmgrStatePreUnload__)(POBJGPU, struct KernelGraphicsManager *, NvU32); + NV_STATUS (*__kgrmgrStateInitUnlocked__)(POBJGPU, struct KernelGraphicsManager *); + void (*__kgrmgrInitMissing__)(POBJGPU, struct KernelGraphicsManager *); + NV_STATUS (*__kgrmgrStatePreInitLocked__)(POBJGPU, struct KernelGraphicsManager *); + NV_STATUS (*__kgrmgrStatePreInitUnlocked__)(POBJGPU, struct KernelGraphicsManager *); + NV_STATUS (*__kgrmgrStatePostLoad__)(POBJGPU, struct KernelGraphicsManager *, NvU32); NvBool (*__kgrmgrIsPresent__)(POBJGPU, struct KernelGraphicsManager *); struct GRMGR_LEGACY_KGRAPHICS_STATIC_INFO legacyKgraphicsStaticInfo; NvU64 veidInUseMask; @@ -127,7 +146,6 @@ __nvoc_objCreate_KernelGraphicsManager((ppNewObj), staticCast((pParent), Dynamic), (createFlags)) #define kgrmgrConstructEngine(arg0, arg1, arg2) kgrmgrConstructEngine_DISPATCH(arg0, arg1, arg2) -#define kgrmgrReconcileTunableState(pGpu, pEngstate, pTunableState) kgrmgrReconcileTunableState_DISPATCH(pGpu, pEngstate, pTunableState) #define kgrmgrStateLoad(pGpu, pEngstate, arg0) kgrmgrStateLoad_DISPATCH(pGpu, pEngstate, arg0) #define kgrmgrStateUnload(pGpu, pEngstate, arg0) kgrmgrStateUnload_DISPATCH(pGpu, pEngstate, arg0) #define kgrmgrStateInitLocked(pGpu, pEngstate) kgrmgrStateInitLocked_DISPATCH(pGpu, pEngstate) @@ -139,12 +157,7 @@ #define kgrmgrInitMissing(pGpu, pEngstate) kgrmgrInitMissing_DISPATCH(pGpu, pEngstate) #define kgrmgrStatePreInitLocked(pGpu, pEngstate) kgrmgrStatePreInitLocked_DISPATCH(pGpu, pEngstate) #define kgrmgrStatePreInitUnlocked(pGpu, pEngstate) kgrmgrStatePreInitUnlocked_DISPATCH(pGpu, pEngstate) -#define kgrmgrGetTunableState(pGpu, pEngstate, pTunableState) kgrmgrGetTunableState_DISPATCH(pGpu, pEngstate, pTunableState) -#define kgrmgrCompareTunableState(pGpu, pEngstate, pTunables1, pTunables2) kgrmgrCompareTunableState_DISPATCH(pGpu, pEngstate, pTunables1, pTunables2) -#define kgrmgrFreeTunableState(pGpu, pEngstate, pTunableState) kgrmgrFreeTunableState_DISPATCH(pGpu, pEngstate, pTunableState) #define kgrmgrStatePostLoad(pGpu, pEngstate, arg0) kgrmgrStatePostLoad_DISPATCH(pGpu, pEngstate, arg0) -#define kgrmgrAllocTunableState(pGpu, pEngstate, ppTunableState) kgrmgrAllocTunableState_DISPATCH(pGpu, pEngstate, ppTunableState) -#define kgrmgrSetTunableState(pGpu, pEngstate, pTunableState) kgrmgrSetTunableState_DISPATCH(pGpu, pEngstate, pTunableState) #define kgrmgrIsPresent(pGpu, pEngstate) kgrmgrIsPresent_DISPATCH(pGpu, pEngstate) NV_STATUS kgrmgrConstructEngine_IMPL(struct OBJGPU *arg0, struct KernelGraphicsManager *arg1, ENGDESCRIPTOR arg2); @@ -152,10 +165,6 @@ return arg1->__kgrmgrConstructEngine__(arg0, arg1, arg2); } -static inline NV_STATUS kgrmgrReconcileTunableState_DISPATCH(POBJGPU pGpu, struct KernelGraphicsManager *pEngstate, void *pTunableState) { - return pEngstate->__kgrmgrReconcileTunableState__(pGpu, pEngstate, pTunableState); -} - static inline NV_STATUS kgrmgrStateLoad_DISPATCH(POBJGPU pGpu, struct KernelGraphicsManager *pEngstate, NvU32 arg0) { return pEngstate->__kgrmgrStateLoad__(pGpu, pEngstate, arg0); } @@ -200,34 +209,19 @@ return pEngstate->__kgrmgrStatePreInitUnlocked__(pGpu, pEngstate); } -static inline NV_STATUS kgrmgrGetTunableState_DISPATCH(POBJGPU pGpu, struct KernelGraphicsManager *pEngstate, void *pTunableState) { - return pEngstate->__kgrmgrGetTunableState__(pGpu, pEngstate, pTunableState); -} - -static inline NV_STATUS kgrmgrCompareTunableState_DISPATCH(POBJGPU pGpu, struct KernelGraphicsManager *pEngstate, void *pTunables1, void *pTunables2) { - return pEngstate->__kgrmgrCompareTunableState__(pGpu, pEngstate, pTunables1, pTunables2); -} - -static inline void kgrmgrFreeTunableState_DISPATCH(POBJGPU pGpu, struct KernelGraphicsManager *pEngstate, void *pTunableState) { - pEngstate->__kgrmgrFreeTunableState__(pGpu, pEngstate, pTunableState); -} - static inline NV_STATUS kgrmgrStatePostLoad_DISPATCH(POBJGPU pGpu, struct KernelGraphicsManager *pEngstate, NvU32 arg0) { return pEngstate->__kgrmgrStatePostLoad__(pGpu, pEngstate, arg0); } -static inline NV_STATUS kgrmgrAllocTunableState_DISPATCH(POBJGPU pGpu, struct KernelGraphicsManager *pEngstate, void **ppTunableState) { - return pEngstate->__kgrmgrAllocTunableState__(pGpu, pEngstate, ppTunableState); -} - -static inline NV_STATUS kgrmgrSetTunableState_DISPATCH(POBJGPU pGpu, struct KernelGraphicsManager *pEngstate, void *pTunableState) { - return pEngstate->__kgrmgrSetTunableState__(pGpu, pEngstate, pTunableState); -} - static inline NvBool kgrmgrIsPresent_DISPATCH(POBJGPU pGpu, struct KernelGraphicsManager *pEngstate) { return pEngstate->__kgrmgrIsPresent__(pGpu, pEngstate); } +static inline NvU64 kgrmgrGetGrIdxVeidMask(struct OBJGPU *pGpu, struct KernelGraphicsManager *pKernelGraphicsManager, NvU32 grIdx) { + struct KernelGraphicsManager_PRIVATE *pKernelGraphicsManager_PRIVATE = (struct KernelGraphicsManager_PRIVATE *)pKernelGraphicsManager; + return pKernelGraphicsManager_PRIVATE->grIdxVeidMask[grIdx]; +} + void kgrmgrGetGrObjectType_IMPL(NvU32 classNum, NvU32 *pObjectType); #define kgrmgrGetGrObjectType(classNum, pObjectType) kgrmgrGetGrObjectType_IMPL(classNum, pObjectType) @@ -267,6 +261,17 @@ #define kgrmgrCtrlRouteKGR(arg0, arg1, hClient, pGrRouteInfo, ppKernelGraphics) kgrmgrCtrlRouteKGR_IMPL(arg0, arg1, hClient, pGrRouteInfo, ppKernelGraphics) #endif //__nvoc_kernel_graphics_manager_h_disabled +NV_STATUS kgrmgrCtrlRouteKGRWithDevice_IMPL(struct OBJGPU *arg0, struct KernelGraphicsManager *arg1, struct Device *pDevice, const NV2080_CTRL_GR_ROUTE_INFO *pGrRouteInfo, struct KernelGraphics **ppKernelGraphics); + +#ifdef __nvoc_kernel_graphics_manager_h_disabled +static inline NV_STATUS kgrmgrCtrlRouteKGRWithDevice(struct OBJGPU *arg0, struct KernelGraphicsManager *arg1, struct Device *pDevice, const NV2080_CTRL_GR_ROUTE_INFO *pGrRouteInfo, struct KernelGraphics **ppKernelGraphics) { + NV_ASSERT_FAILED_PRECOMP("KernelGraphicsManager was disabled!"); + return NV_ERR_NOT_SUPPORTED; +} +#else //__nvoc_kernel_graphics_manager_h_disabled +#define kgrmgrCtrlRouteKGRWithDevice(arg0, arg1, pDevice, pGrRouteInfo, ppKernelGraphics) kgrmgrCtrlRouteKGRWithDevice_IMPL(arg0, arg1, pDevice, pGrRouteInfo, ppKernelGraphics) +#endif //__nvoc_kernel_graphics_manager_h_disabled + NvU32 kgrmgrGetLegacyGpcMask_IMPL(struct OBJGPU *arg0, struct KernelGraphicsManager *arg1); #ifdef __nvoc_kernel_graphics_manager_h_disabled @@ -278,6 +283,17 @@ #define kgrmgrGetLegacyGpcMask(arg0, arg1) kgrmgrGetLegacyGpcMask_IMPL(arg0, arg1) #endif //__nvoc_kernel_graphics_manager_h_disabled +NvU32 kgrmgrGetLegacyPhysGfxGpcMask_IMPL(struct OBJGPU *arg0, struct KernelGraphicsManager *arg1); + +#ifdef __nvoc_kernel_graphics_manager_h_disabled +static inline NvU32 kgrmgrGetLegacyPhysGfxGpcMask(struct OBJGPU *arg0, struct KernelGraphicsManager *arg1) { + NV_ASSERT_FAILED_PRECOMP("KernelGraphicsManager was disabled!"); + return 0; +} +#else //__nvoc_kernel_graphics_manager_h_disabled +#define kgrmgrGetLegacyPhysGfxGpcMask(arg0, arg1) kgrmgrGetLegacyPhysGfxGpcMask_IMPL(arg0, arg1) +#endif //__nvoc_kernel_graphics_manager_h_disabled + NvU32 kgrmgrGetLegacyTpcMask_IMPL(struct OBJGPU *arg0, struct KernelGraphicsManager *arg1, NvU32 gpcId); #ifdef __nvoc_kernel_graphics_manager_h_disabled diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/generated/g_kernel_graphics_nvoc.c nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_kernel_graphics_nvoc.c --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/generated/g_kernel_graphics_nvoc.c 2023-10-25 20:27:08.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_kernel_graphics_nvoc.c 2024-03-05 22:18:28.000000000 +0000 @@ -107,7 +107,7 @@ return kgraphicsStatePostLoad(arg0, (struct KernelGraphics *)(((unsigned char *)arg1) - __nvoc_rtti_KernelGraphics_OBJENGSTATE.offset), flags); } -static void __nvoc_thunk_KernelGraphics_intrservRegisterIntrService(OBJGPU *arg0, struct IntrService *arg1, IntrServiceRecord arg2[163]) { +static void __nvoc_thunk_KernelGraphics_intrservRegisterIntrService(OBJGPU *arg0, struct IntrService *arg1, IntrServiceRecord arg2[167]) { kgraphicsRegisterIntrService(arg0, (struct KernelGraphics *)(((unsigned char *)arg1) - __nvoc_rtti_KernelGraphics_IntrService.offset), arg2); } @@ -123,10 +123,6 @@ return kgraphicsServiceInterrupt(arg0, (struct KernelGraphics *)(((unsigned char *)arg1) - __nvoc_rtti_KernelGraphics_IntrService.offset), arg2); } -static NV_STATUS __nvoc_thunk_OBJENGSTATE_kgraphicsReconcileTunableState(POBJGPU pGpu, struct KernelGraphics *pEngstate, void *pTunableState) { - return engstateReconcileTunableState(pGpu, (struct OBJENGSTATE *)(((unsigned char *)pEngstate) + __nvoc_rtti_KernelGraphics_OBJENGSTATE.offset), pTunableState); -} - static NV_STATUS __nvoc_thunk_OBJENGSTATE_kgraphicsStatePreLoad(POBJGPU pGpu, struct KernelGraphics *pEngstate, NvU32 arg0) { return engstateStatePreLoad(pGpu, (struct OBJENGSTATE *)(((unsigned char *)pEngstate) + __nvoc_rtti_KernelGraphics_OBJENGSTATE.offset), arg0); } @@ -151,26 +147,6 @@ return engstateStatePreInitUnlocked(pGpu, (struct OBJENGSTATE *)(((unsigned char *)pEngstate) + __nvoc_rtti_KernelGraphics_OBJENGSTATE.offset)); } -static NV_STATUS __nvoc_thunk_OBJENGSTATE_kgraphicsGetTunableState(POBJGPU pGpu, struct KernelGraphics *pEngstate, void *pTunableState) { - return engstateGetTunableState(pGpu, (struct OBJENGSTATE *)(((unsigned char *)pEngstate) + __nvoc_rtti_KernelGraphics_OBJENGSTATE.offset), pTunableState); -} - -static NV_STATUS __nvoc_thunk_OBJENGSTATE_kgraphicsCompareTunableState(POBJGPU pGpu, struct KernelGraphics *pEngstate, void *pTunables1, void *pTunables2) { - return engstateCompareTunableState(pGpu, (struct OBJENGSTATE *)(((unsigned char *)pEngstate) + __nvoc_rtti_KernelGraphics_OBJENGSTATE.offset), pTunables1, pTunables2); -} - -static void __nvoc_thunk_OBJENGSTATE_kgraphicsFreeTunableState(POBJGPU pGpu, struct KernelGraphics *pEngstate, void *pTunableState) { - engstateFreeTunableState(pGpu, (struct OBJENGSTATE *)(((unsigned char *)pEngstate) + __nvoc_rtti_KernelGraphics_OBJENGSTATE.offset), pTunableState); -} - -static NV_STATUS __nvoc_thunk_OBJENGSTATE_kgraphicsAllocTunableState(POBJGPU pGpu, struct KernelGraphics *pEngstate, void **ppTunableState) { - return engstateAllocTunableState(pGpu, (struct OBJENGSTATE *)(((unsigned char *)pEngstate) + __nvoc_rtti_KernelGraphics_OBJENGSTATE.offset), ppTunableState); -} - -static NV_STATUS __nvoc_thunk_OBJENGSTATE_kgraphicsSetTunableState(POBJGPU pGpu, struct KernelGraphics *pEngstate, void *pTunableState) { - return engstateSetTunableState(pGpu, (struct OBJENGSTATE *)(((unsigned char *)pEngstate) + __nvoc_rtti_KernelGraphics_OBJENGSTATE.offset), pTunableState); -} - const struct NVOC_EXPORT_INFO __nvoc_export_info_KernelGraphics = { /*numEntries=*/ 0, @@ -233,6 +209,20 @@ { pThis->bRtvCbSupported = ((NvBool)(0 == 0)); } + + // Hal field -- bFecsRecordUcodeSeqnoSupported + if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000002UL) )) /* RmVariantHal: PF_KERNEL_ONLY */ + { + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ + { + pThis->bFecsRecordUcodeSeqnoSupported = ((NvBool)(0 == 0)); + } + // default + else + { + pThis->bFecsRecordUcodeSeqnoSupported = ((NvBool)(0 != 0)); + } + } } NV_STATUS __nvoc_ctor_OBJENGSTATE(OBJENGSTATE* ); @@ -287,16 +277,10 @@ pThis->__kgraphicsServiceNotificationInterrupt__ = &kgraphicsServiceNotificationInterrupt_IMPL; // Hal function -- kgraphicsClearInterrupt - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x11f0ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 | GH100 */ - { - pThis->__kgraphicsClearInterrupt__ = &kgraphicsClearInterrupt_GP100; - } + pThis->__kgraphicsClearInterrupt__ = &kgraphicsClearInterrupt_GP100; // Hal function -- kgraphicsServiceInterrupt - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x11f0ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 | GH100 */ - { - pThis->__kgraphicsServiceInterrupt__ = &kgraphicsServiceInterrupt_GP100; - } + pThis->__kgraphicsServiceInterrupt__ = &kgraphicsServiceInterrupt_GP100; pThis->__nvoc_base_OBJENGSTATE.__engstateConstructEngine__ = &__nvoc_thunk_KernelGraphics_engstateConstructEngine; @@ -322,8 +306,6 @@ pThis->__nvoc_base_IntrService.__intrservServiceInterrupt__ = &__nvoc_thunk_KernelGraphics_intrservServiceInterrupt; - pThis->__kgraphicsReconcileTunableState__ = &__nvoc_thunk_OBJENGSTATE_kgraphicsReconcileTunableState; - pThis->__kgraphicsStatePreLoad__ = &__nvoc_thunk_OBJENGSTATE_kgraphicsStatePreLoad; pThis->__kgraphicsStatePostUnload__ = &__nvoc_thunk_OBJENGSTATE_kgraphicsStatePostUnload; @@ -335,16 +317,6 @@ pThis->__kgraphicsStatePreInitLocked__ = &__nvoc_thunk_OBJENGSTATE_kgraphicsStatePreInitLocked; pThis->__kgraphicsStatePreInitUnlocked__ = &__nvoc_thunk_OBJENGSTATE_kgraphicsStatePreInitUnlocked; - - pThis->__kgraphicsGetTunableState__ = &__nvoc_thunk_OBJENGSTATE_kgraphicsGetTunableState; - - pThis->__kgraphicsCompareTunableState__ = &__nvoc_thunk_OBJENGSTATE_kgraphicsCompareTunableState; - - pThis->__kgraphicsFreeTunableState__ = &__nvoc_thunk_OBJENGSTATE_kgraphicsFreeTunableState; - - pThis->__kgraphicsAllocTunableState__ = &__nvoc_thunk_OBJENGSTATE_kgraphicsAllocTunableState; - - pThis->__kgraphicsSetTunableState__ = &__nvoc_thunk_OBJENGSTATE_kgraphicsSetTunableState; } void __nvoc_init_funcTable_KernelGraphics(KernelGraphics *pThis, RmHalspecOwner *pRmhalspecowner) { @@ -369,13 +341,16 @@ KernelGraphics *pThis; RmHalspecOwner *pRmhalspecowner; - pThis = portMemAllocNonPaged(sizeof(KernelGraphics)); - if (pThis == NULL) return NV_ERR_NO_MEMORY; + status = __nvoc_handleObjCreateMemAlloc(createFlags, sizeof(KernelGraphics), (void**)&pThis, (void**)ppThis); + if (status != NV_OK) + return status; portMemSet(pThis, 0, sizeof(KernelGraphics)); __nvoc_initRtti(staticCast(pThis, Dynamic), &__nvoc_class_def_KernelGraphics); + pThis->__nvoc_base_OBJENGSTATE.__nvoc_base_Object.createFlags = createFlags; + if (pParent != NULL && !(createFlags & NVOC_OBJ_CREATE_FLAGS_PARENT_HALSPEC_ONLY)) { pParentObj = dynamicCast(pParent, Object); @@ -395,11 +370,17 @@ if (status != NV_OK) goto __nvoc_objCreate_KernelGraphics_cleanup; *ppThis = pThis; + return NV_OK; __nvoc_objCreate_KernelGraphics_cleanup: // do not call destructors here since the constructor already called them - portMemFree(pThis); + if (createFlags & NVOC_OBJ_CREATE_FLAGS_IN_PLACE_CONSTRUCT) + portMemSet(pThis, 0, sizeof(KernelGraphics)); + else + portMemFree(pThis); + + // coverity[leaked_storage:FALSE] return status; } diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/generated/g_kernel_graphics_nvoc.h nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_kernel_graphics_nvoc.h --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/generated/g_kernel_graphics_nvoc.h 2023-10-25 20:27:08.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_kernel_graphics_nvoc.h 2024-03-05 22:18:28.000000000 +0000 @@ -170,18 +170,56 @@ NV_STATUS (*__kgraphicsServiceNotificationInterrupt__)(OBJGPU *, struct KernelGraphics *, IntrServiceServiceNotificationInterruptArguments *); NvBool (*__kgraphicsClearInterrupt__)(OBJGPU *, struct KernelGraphics *, IntrServiceClearInterruptArguments *); NvU32 (*__kgraphicsServiceInterrupt__)(OBJGPU *, struct KernelGraphics *, IntrServiceServiceInterruptArguments *); - NV_STATUS (*__kgraphicsReconcileTunableState__)(POBJGPU, struct KernelGraphics *, void *); NV_STATUS (*__kgraphicsStatePreLoad__)(POBJGPU, struct KernelGraphics *, NvU32); NV_STATUS (*__kgraphicsStatePostUnload__)(POBJGPU, struct KernelGraphics *, NvU32); NV_STATUS (*__kgraphicsStateInitUnlocked__)(POBJGPU, struct KernelGraphics *); void (*__kgraphicsInitMissing__)(POBJGPU, struct KernelGraphics *); NV_STATUS (*__kgraphicsStatePreInitLocked__)(POBJGPU, struct KernelGraphics *); NV_STATUS (*__kgraphicsStatePreInitUnlocked__)(POBJGPU, struct KernelGraphics *); - NV_STATUS (*__kgraphicsGetTunableState__)(POBJGPU, struct KernelGraphics *, void *); - NV_STATUS (*__kgraphicsCompareTunableState__)(POBJGPU, struct KernelGraphics *, void *, void *); - void (*__kgraphicsFreeTunableState__)(POBJGPU, struct KernelGraphics *, void *); - NV_STATUS (*__kgraphicsAllocTunableState__)(POBJGPU, struct KernelGraphics *, void **); - NV_STATUS (*__kgraphicsSetTunableState__)(POBJGPU, struct KernelGraphics *, void *); + NvBool PRIVATE_FIELD(bCtxswLoggingSupported); + NvBool PRIVATE_FIELD(bIntrDrivenCtxswLoggingEnabled); + NvBool PRIVATE_FIELD(bBottomHalfCtxswLoggingEnabled); + NvBool PRIVATE_FIELD(bDeferContextInit); + NvBool PRIVATE_FIELD(bPerSubcontextContextHeaderSupported); + NvBool PRIVATE_FIELD(bSetContextBuffersGPUPrivileged); + NvBool PRIVATE_FIELD(bUcodeSupportsPrivAccessMap); + NvBool PRIVATE_FIELD(bRtvCbSupported); + NvBool PRIVATE_FIELD(bFecsRecordUcodeSeqnoSupported); + NvU32 PRIVATE_FIELD(instance); + KGRAPHICS_PRIVATE_DATA *PRIVATE_FIELD(pPrivate); + NvBool PRIVATE_FIELD(bCollectingDeferredStaticData); + KGRAPHICS_FECS_TRACE_INFO *PRIVATE_FIELD(pFecsTraceInfo); + struct KGRAPHICS_GLOBAL_CTX_BUFFERS_INFO PRIVATE_FIELD(globalCtxBuffersInfo); + struct CTX_BUF_POOL_INFO *PRIVATE_FIELD(pCtxBufPool); + CTX_BUF_INFO PRIVATE_FIELD(maxCtxBufSize)[9]; + GR_BUFFER_ATTR PRIVATE_FIELD(ctxAttr)[9]; +}; +struct KernelGraphics_PRIVATE { + const struct NVOC_RTTI *__nvoc_rtti; + struct OBJENGSTATE __nvoc_base_OBJENGSTATE; + struct IntrService __nvoc_base_IntrService; + struct Object *__nvoc_pbase_Object; + struct OBJENGSTATE *__nvoc_pbase_OBJENGSTATE; + struct IntrService *__nvoc_pbase_IntrService; + struct KernelGraphics *__nvoc_pbase_KernelGraphics; + NV_STATUS (*__kgraphicsConstructEngine__)(OBJGPU *, struct KernelGraphics *, ENGDESCRIPTOR); + NV_STATUS (*__kgraphicsStateInitLocked__)(OBJGPU *, struct KernelGraphics *); + NV_STATUS (*__kgraphicsStateLoad__)(OBJGPU *, struct KernelGraphics *, NvU32); + NV_STATUS (*__kgraphicsStatePreUnload__)(OBJGPU *, struct KernelGraphics *, NvU32); + NV_STATUS (*__kgraphicsStateUnload__)(OBJGPU *, struct KernelGraphics *, NvU32); + void (*__kgraphicsStateDestroy__)(OBJGPU *, struct KernelGraphics *); + NvBool (*__kgraphicsIsPresent__)(OBJGPU *, struct KernelGraphics *); + NV_STATUS (*__kgraphicsStatePostLoad__)(OBJGPU *, struct KernelGraphics *, NvU32); + void (*__kgraphicsRegisterIntrService__)(OBJGPU *, struct KernelGraphics *, IntrServiceRecord *); + NV_STATUS (*__kgraphicsServiceNotificationInterrupt__)(OBJGPU *, struct KernelGraphics *, IntrServiceServiceNotificationInterruptArguments *); + NvBool (*__kgraphicsClearInterrupt__)(OBJGPU *, struct KernelGraphics *, IntrServiceClearInterruptArguments *); + NvU32 (*__kgraphicsServiceInterrupt__)(OBJGPU *, struct KernelGraphics *, IntrServiceServiceInterruptArguments *); + NV_STATUS (*__kgraphicsStatePreLoad__)(POBJGPU, struct KernelGraphics *, NvU32); + NV_STATUS (*__kgraphicsStatePostUnload__)(POBJGPU, struct KernelGraphics *, NvU32); + NV_STATUS (*__kgraphicsStateInitUnlocked__)(POBJGPU, struct KernelGraphics *); + void (*__kgraphicsInitMissing__)(POBJGPU, struct KernelGraphics *); + NV_STATUS (*__kgraphicsStatePreInitLocked__)(POBJGPU, struct KernelGraphics *); + NV_STATUS (*__kgraphicsStatePreInitUnlocked__)(POBJGPU, struct KernelGraphics *); NvBool bCtxswLoggingSupported; NvBool bIntrDrivenCtxswLoggingEnabled; NvBool bBottomHalfCtxswLoggingEnabled; @@ -190,6 +228,7 @@ NvBool bSetContextBuffersGPUPrivileged; NvBool bUcodeSupportsPrivAccessMap; NvBool bRtvCbSupported; + NvBool bFecsRecordUcodeSeqnoSupported; NvU32 instance; KGRAPHICS_PRIVATE_DATA *pPrivate; NvBool bCollectingDeferredStaticData; @@ -244,18 +283,12 @@ #define kgraphicsClearInterrupt_HAL(arg0, arg1, arg2) kgraphicsClearInterrupt_DISPATCH(arg0, arg1, arg2) #define kgraphicsServiceInterrupt(arg0, arg1, arg2) kgraphicsServiceInterrupt_DISPATCH(arg0, arg1, arg2) #define kgraphicsServiceInterrupt_HAL(arg0, arg1, arg2) kgraphicsServiceInterrupt_DISPATCH(arg0, arg1, arg2) -#define kgraphicsReconcileTunableState(pGpu, pEngstate, pTunableState) kgraphicsReconcileTunableState_DISPATCH(pGpu, pEngstate, pTunableState) #define kgraphicsStatePreLoad(pGpu, pEngstate, arg0) kgraphicsStatePreLoad_DISPATCH(pGpu, pEngstate, arg0) #define kgraphicsStatePostUnload(pGpu, pEngstate, arg0) kgraphicsStatePostUnload_DISPATCH(pGpu, pEngstate, arg0) #define kgraphicsStateInitUnlocked(pGpu, pEngstate) kgraphicsStateInitUnlocked_DISPATCH(pGpu, pEngstate) #define kgraphicsInitMissing(pGpu, pEngstate) kgraphicsInitMissing_DISPATCH(pGpu, pEngstate) #define kgraphicsStatePreInitLocked(pGpu, pEngstate) kgraphicsStatePreInitLocked_DISPATCH(pGpu, pEngstate) #define kgraphicsStatePreInitUnlocked(pGpu, pEngstate) kgraphicsStatePreInitUnlocked_DISPATCH(pGpu, pEngstate) -#define kgraphicsGetTunableState(pGpu, pEngstate, pTunableState) kgraphicsGetTunableState_DISPATCH(pGpu, pEngstate, pTunableState) -#define kgraphicsCompareTunableState(pGpu, pEngstate, pTunables1, pTunables2) kgraphicsCompareTunableState_DISPATCH(pGpu, pEngstate, pTunables1, pTunables2) -#define kgraphicsFreeTunableState(pGpu, pEngstate, pTunableState) kgraphicsFreeTunableState_DISPATCH(pGpu, pEngstate, pTunableState) -#define kgraphicsAllocTunableState(pGpu, pEngstate, ppTunableState) kgraphicsAllocTunableState_DISPATCH(pGpu, pEngstate, ppTunableState) -#define kgraphicsSetTunableState(pGpu, pEngstate, pTunableState) kgraphicsSetTunableState_DISPATCH(pGpu, pEngstate, pTunableState) static inline NvBool kgraphicsShouldForceMainCtxContiguity_cbe027(OBJGPU *arg0, struct KernelGraphics *arg1) { return ((NvBool)(0 == 0)); } @@ -418,9 +451,9 @@ return arg1->__kgraphicsStatePostLoad__(arg0, arg1, flags); } -void kgraphicsRegisterIntrService_IMPL(OBJGPU *arg0, struct KernelGraphics *arg1, IntrServiceRecord arg2[163]); +void kgraphicsRegisterIntrService_IMPL(OBJGPU *arg0, struct KernelGraphics *arg1, IntrServiceRecord arg2[167]); -static inline void kgraphicsRegisterIntrService_DISPATCH(OBJGPU *arg0, struct KernelGraphics *arg1, IntrServiceRecord arg2[163]) { +static inline void kgraphicsRegisterIntrService_DISPATCH(OBJGPU *arg0, struct KernelGraphics *arg1, IntrServiceRecord arg2[167]) { arg1->__kgraphicsRegisterIntrService__(arg0, arg1, arg2); } @@ -442,10 +475,6 @@ return arg1->__kgraphicsServiceInterrupt__(arg0, arg1, arg2); } -static inline NV_STATUS kgraphicsReconcileTunableState_DISPATCH(POBJGPU pGpu, struct KernelGraphics *pEngstate, void *pTunableState) { - return pEngstate->__kgraphicsReconcileTunableState__(pGpu, pEngstate, pTunableState); -} - static inline NV_STATUS kgraphicsStatePreLoad_DISPATCH(POBJGPU pGpu, struct KernelGraphics *pEngstate, NvU32 arg0) { return pEngstate->__kgraphicsStatePreLoad__(pGpu, pEngstate, arg0); } @@ -470,80 +499,79 @@ return pEngstate->__kgraphicsStatePreInitUnlocked__(pGpu, pEngstate); } -static inline NV_STATUS kgraphicsGetTunableState_DISPATCH(POBJGPU pGpu, struct KernelGraphics *pEngstate, void *pTunableState) { - return pEngstate->__kgraphicsGetTunableState__(pGpu, pEngstate, pTunableState); -} - -static inline NV_STATUS kgraphicsCompareTunableState_DISPATCH(POBJGPU pGpu, struct KernelGraphics *pEngstate, void *pTunables1, void *pTunables2) { - return pEngstate->__kgraphicsCompareTunableState__(pGpu, pEngstate, pTunables1, pTunables2); -} - -static inline void kgraphicsFreeTunableState_DISPATCH(POBJGPU pGpu, struct KernelGraphics *pEngstate, void *pTunableState) { - pEngstate->__kgraphicsFreeTunableState__(pGpu, pEngstate, pTunableState); -} - -static inline NV_STATUS kgraphicsAllocTunableState_DISPATCH(POBJGPU pGpu, struct KernelGraphics *pEngstate, void **ppTunableState) { - return pEngstate->__kgraphicsAllocTunableState__(pGpu, pEngstate, ppTunableState); -} - -static inline NV_STATUS kgraphicsSetTunableState_DISPATCH(POBJGPU pGpu, struct KernelGraphics *pEngstate, void *pTunableState) { - return pEngstate->__kgraphicsSetTunableState__(pGpu, pEngstate, pTunableState); -} - static inline KGRAPHICS_FECS_TRACE_INFO *kgraphicsGetFecsTraceInfo(OBJGPU *pGpu, struct KernelGraphics *pKernelGraphics) { - return pKernelGraphics->pFecsTraceInfo; + struct KernelGraphics_PRIVATE *pKernelGraphics_PRIVATE = (struct KernelGraphics_PRIVATE *)pKernelGraphics; + return pKernelGraphics_PRIVATE->pFecsTraceInfo; } static inline NvU32 kgraphicsGetInstance(OBJGPU *pGpu, struct KernelGraphics *pKernelGraphics) { - return pKernelGraphics->instance; + struct KernelGraphics_PRIVATE *pKernelGraphics_PRIVATE = (struct KernelGraphics_PRIVATE *)pKernelGraphics; + return pKernelGraphics_PRIVATE->instance; } static inline NvBool kgraphicsIsCtxswLoggingSupported(OBJGPU *pGpu, struct KernelGraphics *pKernelGraphics) { - return pKernelGraphics->bCtxswLoggingSupported; + struct KernelGraphics_PRIVATE *pKernelGraphics_PRIVATE = (struct KernelGraphics_PRIVATE *)pKernelGraphics; + return pKernelGraphics_PRIVATE->bCtxswLoggingSupported; } static inline void kgraphicsSetCtxswLoggingSupported(OBJGPU *pGpu, struct KernelGraphics *pKernelGraphics, NvBool bProp) { - pKernelGraphics->bCtxswLoggingSupported = bProp; + struct KernelGraphics_PRIVATE *pKernelGraphics_PRIVATE = (struct KernelGraphics_PRIVATE *)pKernelGraphics; + pKernelGraphics_PRIVATE->bCtxswLoggingSupported = bProp; } static inline NvBool kgraphicsIsIntrDrivenCtxswLoggingEnabled(OBJGPU *pGpu, struct KernelGraphics *pKernelGraphics) { - return pKernelGraphics->bIntrDrivenCtxswLoggingEnabled; + struct KernelGraphics_PRIVATE *pKernelGraphics_PRIVATE = (struct KernelGraphics_PRIVATE *)pKernelGraphics; + return pKernelGraphics_PRIVATE->bIntrDrivenCtxswLoggingEnabled; } static inline void kgraphicsSetIntrDrivenCtxswLoggingEnabled(OBJGPU *pGpu, struct KernelGraphics *pKernelGraphics, NvBool bProp) { - pKernelGraphics->bIntrDrivenCtxswLoggingEnabled = bProp; + struct KernelGraphics_PRIVATE *pKernelGraphics_PRIVATE = (struct KernelGraphics_PRIVATE *)pKernelGraphics; + pKernelGraphics_PRIVATE->bIntrDrivenCtxswLoggingEnabled = bProp; } static inline NvBool kgraphicsIsBottomHalfCtxswLoggingEnabled(OBJGPU *pGpu, struct KernelGraphics *pKernelGraphics) { - return pKernelGraphics->bBottomHalfCtxswLoggingEnabled; + struct KernelGraphics_PRIVATE *pKernelGraphics_PRIVATE = (struct KernelGraphics_PRIVATE *)pKernelGraphics; + return pKernelGraphics_PRIVATE->bBottomHalfCtxswLoggingEnabled; } static inline void kgraphicsSetBottomHalfCtxswLoggingEnabled(OBJGPU *pGpu, struct KernelGraphics *pKernelGraphics, NvBool bProp) { - pKernelGraphics->bBottomHalfCtxswLoggingEnabled = bProp; + struct KernelGraphics_PRIVATE *pKernelGraphics_PRIVATE = (struct KernelGraphics_PRIVATE *)pKernelGraphics; + pKernelGraphics_PRIVATE->bBottomHalfCtxswLoggingEnabled = bProp; } static inline NvBool kgraphicsShouldDeferContextInit(OBJGPU *pGpu, struct KernelGraphics *pKernelGraphics) { - return pKernelGraphics->bDeferContextInit; + struct KernelGraphics_PRIVATE *pKernelGraphics_PRIVATE = (struct KernelGraphics_PRIVATE *)pKernelGraphics; + return pKernelGraphics_PRIVATE->bDeferContextInit; } static inline NvBool kgraphicsIsPerSubcontextContextHeaderSupported(OBJGPU *pGpu, struct KernelGraphics *pKernelGraphics) { - return pKernelGraphics->bPerSubcontextContextHeaderSupported; + struct KernelGraphics_PRIVATE *pKernelGraphics_PRIVATE = (struct KernelGraphics_PRIVATE *)pKernelGraphics; + return pKernelGraphics_PRIVATE->bPerSubcontextContextHeaderSupported; } static inline void kgraphicsSetPerSubcontextContextHeaderSupported(OBJGPU *pGpu, struct KernelGraphics *pKernelGraphics, NvBool bProp) { - pKernelGraphics->bPerSubcontextContextHeaderSupported = bProp; + struct KernelGraphics_PRIVATE *pKernelGraphics_PRIVATE = (struct KernelGraphics_PRIVATE *)pKernelGraphics; + pKernelGraphics_PRIVATE->bPerSubcontextContextHeaderSupported = bProp; } static inline NvBool kgraphicsShouldSetContextBuffersGPUPrivileged(OBJGPU *pGpu, struct KernelGraphics *pKernelGraphics) { - return pKernelGraphics->bSetContextBuffersGPUPrivileged; + struct KernelGraphics_PRIVATE *pKernelGraphics_PRIVATE = (struct KernelGraphics_PRIVATE *)pKernelGraphics; + return pKernelGraphics_PRIVATE->bSetContextBuffersGPUPrivileged; } static inline NvBool kgraphicsDoesUcodeSupportPrivAccessMap(OBJGPU *pGpu, struct KernelGraphics *pKernelGraphics) { - return pKernelGraphics->bUcodeSupportsPrivAccessMap; + struct KernelGraphics_PRIVATE *pKernelGraphics_PRIVATE = (struct KernelGraphics_PRIVATE *)pKernelGraphics; + return pKernelGraphics_PRIVATE->bUcodeSupportsPrivAccessMap; } static inline NvBool kgraphicsIsRtvCbSupported(OBJGPU *pGpu, struct KernelGraphics *pKernelGraphics) { - return pKernelGraphics->bRtvCbSupported; + struct KernelGraphics_PRIVATE *pKernelGraphics_PRIVATE = (struct KernelGraphics_PRIVATE *)pKernelGraphics; + return pKernelGraphics_PRIVATE->bRtvCbSupported; +} + +static inline NvBool kgraphicsIsFecsRecordUcodeSeqnoSupported(OBJGPU *pGpu, struct KernelGraphics *pKernelGraphics) { + struct KernelGraphics_PRIVATE *pKernelGraphics_PRIVATE = (struct KernelGraphics_PRIVATE *)pKernelGraphics; + return pKernelGraphics_PRIVATE->bFecsRecordUcodeSeqnoSupported; } void kgraphicsDestruct_IMPL(struct KernelGraphics *arg0); @@ -730,6 +758,28 @@ #define kgraphicsCreateGoldenImageChannel(arg0, arg1) kgraphicsCreateGoldenImageChannel_IMPL(arg0, arg1) #endif //__nvoc_kernel_graphics_h_disabled +NvBool kgraphicsIsGFXSupported_IMPL(OBJGPU *arg0, struct KernelGraphics *arg1); + +#ifdef __nvoc_kernel_graphics_h_disabled +static inline NvBool kgraphicsIsGFXSupported(OBJGPU *arg0, struct KernelGraphics *arg1) { + NV_ASSERT_FAILED_PRECOMP("KernelGraphics was disabled!"); + return NV_FALSE; +} +#else //__nvoc_kernel_graphics_h_disabled +#define kgraphicsIsGFXSupported(arg0, arg1) kgraphicsIsGFXSupported_IMPL(arg0, arg1) +#endif //__nvoc_kernel_graphics_h_disabled + +NV_STATUS kgraphicsDiscoverMaxLocalCtxBufferSize_IMPL(OBJGPU *pGpu, struct KernelGraphics *pKernelGraphics); + +#ifdef __nvoc_kernel_graphics_h_disabled +static inline NV_STATUS kgraphicsDiscoverMaxLocalCtxBufferSize(OBJGPU *pGpu, struct KernelGraphics *pKernelGraphics) { + NV_ASSERT_FAILED_PRECOMP("KernelGraphics was disabled!"); + return NV_ERR_NOT_SUPPORTED; +} +#else //__nvoc_kernel_graphics_h_disabled +#define kgraphicsDiscoverMaxLocalCtxBufferSize(pGpu, pKernelGraphics) kgraphicsDiscoverMaxLocalCtxBufferSize_IMPL(pGpu, pKernelGraphics) +#endif //__nvoc_kernel_graphics_h_disabled + NV_STATUS kgraphicsInitializeDeferredStaticData_IMPL(OBJGPU *arg0, struct KernelGraphics *arg1, NvHandle hClient, NvHandle hSubdevice); #ifdef __nvoc_kernel_graphics_h_disabled diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/generated/g_kernel_graphics_object_nvoc.c nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_kernel_graphics_object_nvoc.c --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/generated/g_kernel_graphics_object_nvoc.c 2023-10-25 20:27:08.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_kernel_graphics_object_nvoc.c 2024-03-05 22:18:29.000000000 +0000 @@ -180,7 +180,7 @@ return resControlLookup((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_KernelGraphicsObject_RsResource.offset), pParams, ppEntry); } -static NV_STATUS __nvoc_thunk_ChannelDescendant_kgrobjGetSwMethods(struct KernelGraphicsObject *pChannelDescendant, METHOD **ppMethods, NvU32 *pNumMethods) { +static NV_STATUS __nvoc_thunk_ChannelDescendant_kgrobjGetSwMethods(struct KernelGraphicsObject *pChannelDescendant, const METHOD **ppMethods, NvU32 *pNumMethods) { return chandesGetSwMethods((struct ChannelDescendant *)(((unsigned char *)pChannelDescendant) + __nvoc_rtti_KernelGraphicsObject_ChannelDescendant.offset), ppMethods, pNumMethods); } @@ -212,6 +212,10 @@ return notifyUnregisterEvent((struct Notifier *)(((unsigned char *)pNotifier) + __nvoc_rtti_KernelGraphicsObject_Notifier.offset), hNotifierClient, hNotifierResource, hEventClient, hEvent); } +static NV_STATUS __nvoc_thunk_RmResource_kgrobjControlSerialization_Prologue(struct KernelGraphicsObject *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return rmresControlSerialization_Prologue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_KernelGraphicsObject_RmResource.offset), pCallContext, pParams); +} + static NvBool __nvoc_thunk_RsResource_kgrobjCanCopy(struct KernelGraphicsObject *pResource) { return resCanCopy((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_KernelGraphicsObject_RsResource.offset)); } @@ -224,6 +228,10 @@ return resIsDuplicate((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_KernelGraphicsObject_RsResource.offset), hMemory, pDuplicate); } +static void __nvoc_thunk_RmResource_kgrobjControlSerialization_Epilogue(struct KernelGraphicsObject *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + rmresControlSerialization_Epilogue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_KernelGraphicsObject_RmResource.offset), pCallContext, pParams); +} + static PEVENTNOTIFICATION *__nvoc_thunk_Notifier_kgrobjGetNotificationListPtr(struct KernelGraphicsObject *pNotifier) { return notifyGetNotificationListPtr((struct Notifier *)(((unsigned char *)pNotifier) + __nvoc_rtti_KernelGraphicsObject_Notifier.offset)); } @@ -345,12 +353,16 @@ pThis->__kgrobjUnregisterEvent__ = &__nvoc_thunk_Notifier_kgrobjUnregisterEvent; + pThis->__kgrobjControlSerialization_Prologue__ = &__nvoc_thunk_RmResource_kgrobjControlSerialization_Prologue; + pThis->__kgrobjCanCopy__ = &__nvoc_thunk_RsResource_kgrobjCanCopy; pThis->__kgrobjPreDestruct__ = &__nvoc_thunk_RsResource_kgrobjPreDestruct; pThis->__kgrobjIsDuplicate__ = &__nvoc_thunk_RsResource_kgrobjIsDuplicate; + pThis->__kgrobjControlSerialization_Epilogue__ = &__nvoc_thunk_RmResource_kgrobjControlSerialization_Epilogue; + pThis->__kgrobjGetNotificationListPtr__ = &__nvoc_thunk_Notifier_kgrobjGetNotificationListPtr; pThis->__kgrobjGetNotificationShare__ = &__nvoc_thunk_Notifier_kgrobjGetNotificationShare; @@ -385,13 +397,16 @@ KernelGraphicsObject *pThis; RmHalspecOwner *pRmhalspecowner; - pThis = portMemAllocNonPaged(sizeof(KernelGraphicsObject)); - if (pThis == NULL) return NV_ERR_NO_MEMORY; + status = __nvoc_handleObjCreateMemAlloc(createFlags, sizeof(KernelGraphicsObject), (void**)&pThis, (void**)ppThis); + if (status != NV_OK) + return status; portMemSet(pThis, 0, sizeof(KernelGraphicsObject)); __nvoc_initRtti(staticCast(pThis, Dynamic), &__nvoc_class_def_KernelGraphicsObject); + pThis->__nvoc_base_ChannelDescendant.__nvoc_base_GpuResource.__nvoc_base_RmResource.__nvoc_base_RsResource.__nvoc_base_Object.createFlags = createFlags; + if (pParent != NULL && !(createFlags & NVOC_OBJ_CREATE_FLAGS_PARENT_HALSPEC_ONLY)) { pParentObj = dynamicCast(pParent, Object); @@ -411,11 +426,17 @@ if (status != NV_OK) goto __nvoc_objCreate_KernelGraphicsObject_cleanup; *ppThis = pThis; + return NV_OK; __nvoc_objCreate_KernelGraphicsObject_cleanup: // do not call destructors here since the constructor already called them - portMemFree(pThis); + if (createFlags & NVOC_OBJ_CREATE_FLAGS_IN_PLACE_CONSTRUCT) + portMemSet(pThis, 0, sizeof(KernelGraphicsObject)); + else + portMemFree(pThis); + + // coverity[leaked_storage:FALSE] return status; } diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/generated/g_kernel_graphics_object_nvoc.h nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_kernel_graphics_object_nvoc.h --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/generated/g_kernel_graphics_object_nvoc.h 2023-10-25 20:27:08.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_kernel_graphics_object_nvoc.h 2024-03-05 22:18:29.000000000 +0000 @@ -7,7 +7,7 @@ #endif /* - * SPDX-FileCopyrightText: Copyright (c) 1993-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 1993-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -91,7 +91,7 @@ NV_STATUS (*__kgrobjUnmapFrom__)(struct KernelGraphicsObject *, RS_RES_UNMAP_FROM_PARAMS *); void (*__kgrobjControl_Epilogue__)(struct KernelGraphicsObject *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); NV_STATUS (*__kgrobjControlLookup__)(struct KernelGraphicsObject *, struct RS_RES_CONTROL_PARAMS_INTERNAL *, const struct NVOC_EXPORTED_METHOD_DEF **); - NV_STATUS (*__kgrobjGetSwMethods__)(struct KernelGraphicsObject *, METHOD **, NvU32 *); + NV_STATUS (*__kgrobjGetSwMethods__)(struct KernelGraphicsObject *, const METHOD **, NvU32 *); NvHandle (*__kgrobjGetInternalObjectHandle__)(struct KernelGraphicsObject *); NV_STATUS (*__kgrobjControl__)(struct KernelGraphicsObject *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); NV_STATUS (*__kgrobjUnmap__)(struct KernelGraphicsObject *, struct CALL_CONTEXT *, struct RsCpuMapping *); @@ -99,14 +99,16 @@ NvBool (*__kgrobjIsSwMethodStalling__)(struct KernelGraphicsObject *, NvU32); NV_STATUS (*__kgrobjControlFilter__)(struct KernelGraphicsObject *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); NV_STATUS (*__kgrobjUnregisterEvent__)(struct KernelGraphicsObject *, NvHandle, NvHandle, NvHandle, NvHandle); + NV_STATUS (*__kgrobjControlSerialization_Prologue__)(struct KernelGraphicsObject *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); NvBool (*__kgrobjCanCopy__)(struct KernelGraphicsObject *); void (*__kgrobjPreDestruct__)(struct KernelGraphicsObject *); NV_STATUS (*__kgrobjIsDuplicate__)(struct KernelGraphicsObject *, NvHandle, NvBool *); + void (*__kgrobjControlSerialization_Epilogue__)(struct KernelGraphicsObject *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); PEVENTNOTIFICATION *(*__kgrobjGetNotificationListPtr__)(struct KernelGraphicsObject *); struct NotifShare *(*__kgrobjGetNotificationShare__)(struct KernelGraphicsObject *); NV_STATUS (*__kgrobjMap__)(struct KernelGraphicsObject *, struct CALL_CONTEXT *, struct RS_CPU_MAP_PARAMS *, struct RsCpuMapping *); NV_STATUS (*__kgrobjGetOrAllocNotifShare__)(struct KernelGraphicsObject *, NvHandle, NvHandle, struct NotifShare **); - MEMORY_DESCRIPTOR *pMmioMemDesc; + MEMORY_DESCRIPTOR *PRIVATE_FIELD(pMmioMemDesc); KernelSMDebuggerSessionList activeDebuggers; struct KernelGraphicsContext *pKernelGraphicsContext; }; @@ -162,9 +164,11 @@ #define kgrobjIsSwMethodStalling(pChannelDescendant, hHandle) kgrobjIsSwMethodStalling_DISPATCH(pChannelDescendant, hHandle) #define kgrobjControlFilter(pResource, pCallContext, pParams) kgrobjControlFilter_DISPATCH(pResource, pCallContext, pParams) #define kgrobjUnregisterEvent(pNotifier, hNotifierClient, hNotifierResource, hEventClient, hEvent) kgrobjUnregisterEvent_DISPATCH(pNotifier, hNotifierClient, hNotifierResource, hEventClient, hEvent) +#define kgrobjControlSerialization_Prologue(pResource, pCallContext, pParams) kgrobjControlSerialization_Prologue_DISPATCH(pResource, pCallContext, pParams) #define kgrobjCanCopy(pResource) kgrobjCanCopy_DISPATCH(pResource) #define kgrobjPreDestruct(pResource) kgrobjPreDestruct_DISPATCH(pResource) #define kgrobjIsDuplicate(pResource, hMemory, pDuplicate) kgrobjIsDuplicate_DISPATCH(pResource, hMemory, pDuplicate) +#define kgrobjControlSerialization_Epilogue(pResource, pCallContext, pParams) kgrobjControlSerialization_Epilogue_DISPATCH(pResource, pCallContext, pParams) #define kgrobjGetNotificationListPtr(pNotifier) kgrobjGetNotificationListPtr_DISPATCH(pNotifier) #define kgrobjGetNotificationShare(pNotifier) kgrobjGetNotificationShare_DISPATCH(pNotifier) #define kgrobjMap(pGpuResource, pCallContext, pParams, pCpuMapping) kgrobjMap_DISPATCH(pGpuResource, pCallContext, pParams, pCpuMapping) @@ -285,7 +289,7 @@ return pResource->__kgrobjControlLookup__(pResource, pParams, ppEntry); } -static inline NV_STATUS kgrobjGetSwMethods_DISPATCH(struct KernelGraphicsObject *pChannelDescendant, METHOD **ppMethods, NvU32 *pNumMethods) { +static inline NV_STATUS kgrobjGetSwMethods_DISPATCH(struct KernelGraphicsObject *pChannelDescendant, const METHOD **ppMethods, NvU32 *pNumMethods) { return pChannelDescendant->__kgrobjGetSwMethods__(pChannelDescendant, ppMethods, pNumMethods); } @@ -317,6 +321,10 @@ return pNotifier->__kgrobjUnregisterEvent__(pNotifier, hNotifierClient, hNotifierResource, hEventClient, hEvent); } +static inline NV_STATUS kgrobjControlSerialization_Prologue_DISPATCH(struct KernelGraphicsObject *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return pResource->__kgrobjControlSerialization_Prologue__(pResource, pCallContext, pParams); +} + static inline NvBool kgrobjCanCopy_DISPATCH(struct KernelGraphicsObject *pResource) { return pResource->__kgrobjCanCopy__(pResource); } @@ -329,6 +337,10 @@ return pResource->__kgrobjIsDuplicate__(pResource, hMemory, pDuplicate); } +static inline void kgrobjControlSerialization_Epilogue_DISPATCH(struct KernelGraphicsObject *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + pResource->__kgrobjControlSerialization_Epilogue__(pResource, pCallContext, pParams); +} + static inline PEVENTNOTIFICATION *kgrobjGetNotificationListPtr_DISPATCH(struct KernelGraphicsObject *pNotifier) { return pNotifier->__kgrobjGetNotificationListPtr__(pNotifier); } diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/generated/g_kernel_gsp_nvoc.c nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_kernel_gsp_nvoc.c --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/generated/g_kernel_gsp_nvoc.c 2023-10-25 20:27:08.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_kernel_gsp_nvoc.c 2024-03-05 22:18:29.000000000 +0000 @@ -19,6 +19,10 @@ extern const struct NVOC_CLASS_DEF __nvoc_class_def_IntrService; +extern const struct NVOC_CLASS_DEF __nvoc_class_def_CrashCatEngine; + +extern const struct NVOC_CLASS_DEF __nvoc_class_def_KernelCrashCatEngine; + extern const struct NVOC_CLASS_DEF __nvoc_class_def_KernelFalcon; void __nvoc_init_KernelGsp(KernelGsp*, RmHalspecOwner* ); @@ -52,6 +56,18 @@ /*offset=*/ NV_OFFSETOF(KernelGsp, __nvoc_base_IntrService), }; +static const struct NVOC_RTTI __nvoc_rtti_KernelGsp_CrashCatEngine = { + /*pClassDef=*/ &__nvoc_class_def_CrashCatEngine, + /*dtor=*/ &__nvoc_destructFromBase, + /*offset=*/ NV_OFFSETOF(KernelGsp, __nvoc_base_KernelFalcon.__nvoc_base_KernelCrashCatEngine.__nvoc_base_CrashCatEngine), +}; + +static const struct NVOC_RTTI __nvoc_rtti_KernelGsp_KernelCrashCatEngine = { + /*pClassDef=*/ &__nvoc_class_def_KernelCrashCatEngine, + /*dtor=*/ &__nvoc_destructFromBase, + /*offset=*/ NV_OFFSETOF(KernelGsp, __nvoc_base_KernelFalcon.__nvoc_base_KernelCrashCatEngine), +}; + static const struct NVOC_RTTI __nvoc_rtti_KernelGsp_KernelFalcon = { /*pClassDef=*/ &__nvoc_class_def_KernelFalcon, /*dtor=*/ &__nvoc_destructFromBase, @@ -59,10 +75,12 @@ }; static const struct NVOC_CASTINFO __nvoc_castinfo_KernelGsp = { - /*numRelatives=*/ 5, + /*numRelatives=*/ 7, /*relatives=*/ { &__nvoc_rtti_KernelGsp_KernelGsp, &__nvoc_rtti_KernelGsp_KernelFalcon, + &__nvoc_rtti_KernelGsp_KernelCrashCatEngine, + &__nvoc_rtti_KernelGsp_CrashCatEngine, &__nvoc_rtti_KernelGsp_IntrService, &__nvoc_rtti_KernelGsp_OBJENGSTATE, &__nvoc_rtti_KernelGsp_Object, @@ -88,7 +106,7 @@ return kgspConstructEngine(pGpu, (struct KernelGsp *)(((unsigned char *)pKernelGsp) - __nvoc_rtti_KernelGsp_OBJENGSTATE.offset), arg0); } -static void __nvoc_thunk_KernelGsp_intrservRegisterIntrService(struct OBJGPU *pGpu, struct IntrService *pKernelGsp, IntrServiceRecord pRecords[163]) { +static void __nvoc_thunk_KernelGsp_intrservRegisterIntrService(struct OBJGPU *pGpu, struct IntrService *pKernelGsp, IntrServiceRecord pRecords[167]) { kgspRegisterIntrService(pGpu, (struct KernelGsp *)(((unsigned char *)pKernelGsp) - __nvoc_rtti_KernelGsp_IntrService.offset), pRecords); } @@ -100,38 +118,70 @@ return kgspResetHw(pGpu, (struct KernelGsp *)(((unsigned char *)pKernelGsp) - __nvoc_rtti_KernelGsp_KernelFalcon.offset)); } -static NvBool __nvoc_thunk_KernelGsp_kflcnIsEngineInReset(struct OBJGPU *pGpu, struct KernelFalcon *pKernelGsp) { - return kgspIsEngineInReset(pGpu, (struct KernelGsp *)(((unsigned char *)pKernelGsp) - __nvoc_rtti_KernelGsp_KernelFalcon.offset)); +static void __nvoc_thunk_KernelGsp_kcrashcatEngineReadEmem(struct KernelCrashCatEngine *pKernelGsp, NvU64 offset, NvU64 size, void *pBuf) { + kgspReadEmem((struct KernelGsp *)(((unsigned char *)pKernelGsp) - __nvoc_rtti_KernelGsp_KernelCrashCatEngine.offset), offset, size, pBuf); } -static void __nvoc_thunk_OBJENGSTATE_kgspStateDestroy(POBJGPU pGpu, struct KernelGsp *pEngstate) { - engstateStateDestroy(pGpu, (struct OBJENGSTATE *)(((unsigned char *)pEngstate) + __nvoc_rtti_KernelGsp_OBJENGSTATE.offset)); +static NvBool __nvoc_thunk_KernelCrashCatEngine_kgspConfigured(struct KernelGsp *arg0) { + return kcrashcatEngineConfigured((struct KernelCrashCatEngine *)(((unsigned char *)arg0) + __nvoc_rtti_KernelGsp_KernelCrashCatEngine.offset)); +} + +static NvU32 __nvoc_thunk_KernelCrashCatEngine_kgspPriRead(struct KernelGsp *arg0, NvU32 offset) { + return kcrashcatEnginePriRead((struct KernelCrashCatEngine *)(((unsigned char *)arg0) + __nvoc_rtti_KernelGsp_KernelCrashCatEngine.offset), offset); } -static void __nvoc_thunk_OBJENGSTATE_kgspFreeTunableState(POBJGPU pGpu, struct KernelGsp *pEngstate, void *pTunableState) { - engstateFreeTunableState(pGpu, (struct OBJENGSTATE *)(((unsigned char *)pEngstate) + __nvoc_rtti_KernelGsp_OBJENGSTATE.offset), pTunableState); +static void __nvoc_thunk_KernelFalcon_kgspRegWrite(struct OBJGPU *pGpu, struct KernelGsp *pKernelFlcn, NvU32 offset, NvU32 data) { + kflcnRegWrite(pGpu, (struct KernelFalcon *)(((unsigned char *)pKernelFlcn) + __nvoc_rtti_KernelGsp_KernelFalcon.offset), offset, data); } -static NV_STATUS __nvoc_thunk_OBJENGSTATE_kgspCompareTunableState(POBJGPU pGpu, struct KernelGsp *pEngstate, void *pTunables1, void *pTunables2) { - return engstateCompareTunableState(pGpu, (struct OBJENGSTATE *)(((unsigned char *)pEngstate) + __nvoc_rtti_KernelGsp_OBJENGSTATE.offset), pTunables1, pTunables2); +static NvU32 __nvoc_thunk_KernelFalcon_kgspMaskDmemAddr(struct OBJGPU *pGpu, struct KernelGsp *pKernelFlcn, NvU32 addr) { + return kflcnMaskDmemAddr(pGpu, (struct KernelFalcon *)(((unsigned char *)pKernelFlcn) + __nvoc_rtti_KernelGsp_KernelFalcon.offset), addr); +} + +static void __nvoc_thunk_OBJENGSTATE_kgspStateDestroy(POBJGPU pGpu, struct KernelGsp *pEngstate) { + engstateStateDestroy(pGpu, (struct OBJENGSTATE *)(((unsigned char *)pEngstate) + __nvoc_rtti_KernelGsp_OBJENGSTATE.offset)); +} + +static void __nvoc_thunk_KernelCrashCatEngine_kgspVprintf(struct KernelGsp *arg0, NvBool bReportStart, const char *fmt, va_list args) { + kcrashcatEngineVprintf((struct KernelCrashCatEngine *)(((unsigned char *)arg0) + __nvoc_rtti_KernelGsp_KernelCrashCatEngine.offset), bReportStart, fmt, args); } static NvBool __nvoc_thunk_IntrService_kgspClearInterrupt(struct OBJGPU *pGpu, struct KernelGsp *pIntrService, IntrServiceClearInterruptArguments *pParams) { return intrservClearInterrupt(pGpu, (struct IntrService *)(((unsigned char *)pIntrService) + __nvoc_rtti_KernelGsp_IntrService.offset), pParams); } -static NvBool __nvoc_thunk_OBJENGSTATE_kgspIsPresent(POBJGPU pGpu, struct KernelGsp *pEngstate) { - return engstateIsPresent(pGpu, (struct OBJENGSTATE *)(((unsigned char *)pEngstate) + __nvoc_rtti_KernelGsp_OBJENGSTATE.offset)); +static void __nvoc_thunk_KernelCrashCatEngine_kgspPriWrite(struct KernelGsp *arg0, NvU32 offset, NvU32 data) { + kcrashcatEnginePriWrite((struct KernelCrashCatEngine *)(((unsigned char *)arg0) + __nvoc_rtti_KernelGsp_KernelCrashCatEngine.offset), offset, data); +} + +static void *__nvoc_thunk_KernelCrashCatEngine_kgspMapBufferDescriptor(struct KernelGsp *arg0, CrashCatBufferDescriptor *pBufDesc) { + return kcrashcatEngineMapBufferDescriptor((struct KernelCrashCatEngine *)(((unsigned char *)arg0) + __nvoc_rtti_KernelGsp_KernelCrashCatEngine.offset), pBufDesc); } -static NV_STATUS __nvoc_thunk_OBJENGSTATE_kgspReconcileTunableState(POBJGPU pGpu, struct KernelGsp *pEngstate, void *pTunableState) { - return engstateReconcileTunableState(pGpu, (struct OBJENGSTATE *)(((unsigned char *)pEngstate) + __nvoc_rtti_KernelGsp_OBJENGSTATE.offset), pTunableState); +static void __nvoc_thunk_KernelCrashCatEngine_kgspSyncBufferDescriptor(struct KernelGsp *arg0, CrashCatBufferDescriptor *pBufDesc, NvU32 offset, NvU32 size) { + kcrashcatEngineSyncBufferDescriptor((struct KernelCrashCatEngine *)(((unsigned char *)arg0) + __nvoc_rtti_KernelGsp_KernelCrashCatEngine.offset), pBufDesc, offset, size); +} + +static NvU32 __nvoc_thunk_KernelFalcon_kgspRegRead(struct OBJGPU *pGpu, struct KernelGsp *pKernelFlcn, NvU32 offset) { + return kflcnRegRead(pGpu, (struct KernelFalcon *)(((unsigned char *)pKernelFlcn) + __nvoc_rtti_KernelGsp_KernelFalcon.offset), offset); +} + +static NvBool __nvoc_thunk_OBJENGSTATE_kgspIsPresent(POBJGPU pGpu, struct KernelGsp *pEngstate) { + return engstateIsPresent(pGpu, (struct OBJENGSTATE *)(((unsigned char *)pEngstate) + __nvoc_rtti_KernelGsp_OBJENGSTATE.offset)); } static NV_STATUS __nvoc_thunk_OBJENGSTATE_kgspStateLoad(POBJGPU pGpu, struct KernelGsp *pEngstate, NvU32 arg0) { return engstateStateLoad(pGpu, (struct OBJENGSTATE *)(((unsigned char *)pEngstate) + __nvoc_rtti_KernelGsp_OBJENGSTATE.offset), arg0); } +static const NvU32 *__nvoc_thunk_KernelCrashCatEngine_kgspGetScratchOffsets(struct KernelGsp *arg0, NV_CRASHCAT_SCRATCH_GROUP_ID scratchGroupId) { + return kcrashcatEngineGetScratchOffsets((struct KernelCrashCatEngine *)(((unsigned char *)arg0) + __nvoc_rtti_KernelGsp_KernelCrashCatEngine.offset), scratchGroupId); +} + +static void __nvoc_thunk_KernelCrashCatEngine_kgspUnload(struct KernelGsp *arg0) { + kcrashcatEngineUnload((struct KernelCrashCatEngine *)(((unsigned char *)arg0) + __nvoc_rtti_KernelGsp_KernelCrashCatEngine.offset)); +} + static NV_STATUS __nvoc_thunk_OBJENGSTATE_kgspStateUnload(POBJGPU pGpu, struct KernelGsp *pEngstate, NvU32 arg0) { return engstateStateUnload(pGpu, (struct OBJENGSTATE *)(((unsigned char *)pEngstate) + __nvoc_rtti_KernelGsp_OBJENGSTATE.offset), arg0); } @@ -140,6 +190,10 @@ return intrservServiceNotificationInterrupt(pGpu, (struct IntrService *)(((unsigned char *)pIntrService) + __nvoc_rtti_KernelGsp_IntrService.offset), pParams); } +static NvU32 __nvoc_thunk_KernelCrashCatEngine_kgspGetWFL0Offset(struct KernelGsp *arg0) { + return kcrashcatEngineGetWFL0Offset((struct KernelCrashCatEngine *)(((unsigned char *)arg0) + __nvoc_rtti_KernelGsp_KernelCrashCatEngine.offset)); +} + static NV_STATUS __nvoc_thunk_OBJENGSTATE_kgspStateInitLocked(POBJGPU pGpu, struct KernelGsp *pEngstate) { return engstateStateInitLocked(pGpu, (struct OBJENGSTATE *)(((unsigned char *)pEngstate) + __nvoc_rtti_KernelGsp_OBJENGSTATE.offset)); } @@ -156,10 +210,6 @@ return engstateStatePreUnload(pGpu, (struct OBJENGSTATE *)(((unsigned char *)pEngstate) + __nvoc_rtti_KernelGsp_OBJENGSTATE.offset), arg0); } -static NV_STATUS __nvoc_thunk_OBJENGSTATE_kgspGetTunableState(POBJGPU pGpu, struct KernelGsp *pEngstate, void *pTunableState) { - return engstateGetTunableState(pGpu, (struct OBJENGSTATE *)(((unsigned char *)pEngstate) + __nvoc_rtti_KernelGsp_OBJENGSTATE.offset), pTunableState); -} - static NV_STATUS __nvoc_thunk_OBJENGSTATE_kgspStateInitUnlocked(POBJGPU pGpu, struct KernelGsp *pEngstate) { return engstateStateInitUnlocked(pGpu, (struct OBJENGSTATE *)(((unsigned char *)pEngstate) + __nvoc_rtti_KernelGsp_OBJENGSTATE.offset)); } @@ -180,12 +230,12 @@ return engstateStatePostLoad(pGpu, (struct OBJENGSTATE *)(((unsigned char *)pEngstate) + __nvoc_rtti_KernelGsp_OBJENGSTATE.offset), arg0); } -static NV_STATUS __nvoc_thunk_OBJENGSTATE_kgspAllocTunableState(POBJGPU pGpu, struct KernelGsp *pEngstate, void **ppTunableState) { - return engstateAllocTunableState(pGpu, (struct OBJENGSTATE *)(((unsigned char *)pEngstate) + __nvoc_rtti_KernelGsp_OBJENGSTATE.offset), ppTunableState); +static void __nvoc_thunk_KernelCrashCatEngine_kgspUnmapBufferDescriptor(struct KernelGsp *arg0, CrashCatBufferDescriptor *pBufDesc) { + kcrashcatEngineUnmapBufferDescriptor((struct KernelCrashCatEngine *)(((unsigned char *)arg0) + __nvoc_rtti_KernelGsp_KernelCrashCatEngine.offset), pBufDesc); } -static NV_STATUS __nvoc_thunk_OBJENGSTATE_kgspSetTunableState(POBJGPU pGpu, struct KernelGsp *pEngstate, void *pTunableState) { - return engstateSetTunableState(pGpu, (struct OBJENGSTATE *)(((unsigned char *)pEngstate) + __nvoc_rtti_KernelGsp_OBJENGSTATE.offset), pTunableState); +static void __nvoc_thunk_KernelCrashCatEngine_kgspReadDmem(struct KernelGsp *arg0, NvU32 offset, NvU32 size, void *pBuf) { + kcrashcatEngineReadDmem((struct KernelCrashCatEngine *)(((unsigned char *)arg0) + __nvoc_rtti_KernelGsp_KernelCrashCatEngine.offset), offset, size, pBuf); } const struct NVOC_EXPORT_INFO __nvoc_export_info_KernelGsp = @@ -217,6 +267,9 @@ PORT_UNREFERENCED_VARIABLE(rmVariantHal); PORT_UNREFERENCED_VARIABLE(rmVariantHal_HalVarIdx); + // Hal field -- bIsTaskIsrQueueRequired + pThis->bIsTaskIsrQueueRequired = ((NvBool)(0 != 0)); + // Hal field -- bPartitionedFmc if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ { @@ -227,6 +280,55 @@ { pThis->bPartitionedFmc = ((NvBool)(0 != 0)); } + + // Hal field -- bScrubberUcodeSupported + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x01f00000UL) )) /* ChipHal: AD102 | AD103 | AD104 | AD106 | AD107 */ + { + pThis->bScrubberUcodeSupported = ((NvBool)(0 == 0)); + } + // default + else + { + pThis->bScrubberUcodeSupported = ((NvBool)(0 != 0)); + } + + // Hal field -- fwHeapParamBaseSize + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x01f0ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 */ + { + pThis->fwHeapParamBaseSize = (8 << 20); + } + else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ + { + pThis->fwHeapParamBaseSize = (14 << 20); + } + + // Hal field -- fwHeapParamOsCarveoutSize + if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000002UL) )) /* RmVariantHal: PF_KERNEL_ONLY */ + { + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x000007e0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 */ + { + pThis->fwHeapParamOsCarveoutSize = (0 << 20); + } + else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x11f0f800UL) )) /* ChipHal: GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 | GH100 */ + { + pThis->fwHeapParamOsCarveoutSize = (20 << 20); + } + } + + // Hal field -- ememPort + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ + { + pThis->ememPort = 6; + } + else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x01f0fc00UL) )) /* ChipHal: GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 */ + { + pThis->ememPort = 2; + } + // default + else + { + pThis->ememPort = 0; + } } NV_STATUS __nvoc_ctor_OBJENGSTATE(OBJENGSTATE* ); @@ -272,494 +374,429 @@ pThis->__kgspServiceInterrupt__ = &kgspServiceInterrupt_IMPL; // Hal function -- kgspConfigureFalcon - if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000002UL) )) /* RmVariantHal: PF_KERNEL_ONLY */ + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x000007e0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 */ { - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x000007e0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 */ - { - pThis->__kgspConfigureFalcon__ = &kgspConfigureFalcon_TU102; - } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x11f0f800UL) )) /* ChipHal: GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 | GH100 */ - { - pThis->__kgspConfigureFalcon__ = &kgspConfigureFalcon_GA102; - } + pThis->__kgspConfigureFalcon__ = &kgspConfigureFalcon_TU102; + } + else + { + pThis->__kgspConfigureFalcon__ = &kgspConfigureFalcon_GA102; } // Hal function -- kgspIsDebugModeEnabled - if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000002UL) )) /* RmVariantHal: PF_KERNEL_ONLY */ + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x000003e0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 */ { - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x000003e0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 */ - { - pThis->__kgspIsDebugModeEnabled__ = &kgspIsDebugModeEnabled_TU102; - } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x11f0fc00UL) )) /* ChipHal: GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 | GH100 */ - { - pThis->__kgspIsDebugModeEnabled__ = &kgspIsDebugModeEnabled_GA100; - } + pThis->__kgspIsDebugModeEnabled__ = &kgspIsDebugModeEnabled_TU102; + } + else + { + pThis->__kgspIsDebugModeEnabled__ = &kgspIsDebugModeEnabled_GA100; } // Hal function -- kgspAllocBootArgs - if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000002UL) )) /* RmVariantHal: PF_KERNEL_ONLY */ + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ { - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x01f0ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 */ - { - pThis->__kgspAllocBootArgs__ = &kgspAllocBootArgs_TU102; - } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ - { - pThis->__kgspAllocBootArgs__ = &kgspAllocBootArgs_GH100; - } + pThis->__kgspAllocBootArgs__ = &kgspAllocBootArgs_GH100; + } + else + { + pThis->__kgspAllocBootArgs__ = &kgspAllocBootArgs_TU102; } // Hal function -- kgspFreeBootArgs - if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000002UL) )) /* RmVariantHal: PF_KERNEL_ONLY */ + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ { - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x01f0ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 */ - { - pThis->__kgspFreeBootArgs__ = &kgspFreeBootArgs_TU102; - } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ - { - pThis->__kgspFreeBootArgs__ = &kgspFreeBootArgs_GH100; - } + pThis->__kgspFreeBootArgs__ = &kgspFreeBootArgs_GH100; + } + else + { + pThis->__kgspFreeBootArgs__ = &kgspFreeBootArgs_TU102; } // Hal function -- kgspBootstrapRiscvOSEarly - if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000002UL) )) /* RmVariantHal: PF_KERNEL_ONLY */ + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ { - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x000007e0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 */ - { - pThis->__kgspBootstrapRiscvOSEarly__ = &kgspBootstrapRiscvOSEarly_TU102; - } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x01f0f800UL) )) /* ChipHal: GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 */ - { - pThis->__kgspBootstrapRiscvOSEarly__ = &kgspBootstrapRiscvOSEarly_GA102; - } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ - { - pThis->__kgspBootstrapRiscvOSEarly__ = &kgspBootstrapRiscvOSEarly_GH100; - } + pThis->__kgspBootstrapRiscvOSEarly__ = &kgspBootstrapRiscvOSEarly_GH100; + } + else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x000007e0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 */ + { + pThis->__kgspBootstrapRiscvOSEarly__ = &kgspBootstrapRiscvOSEarly_TU102; + } + else + { + pThis->__kgspBootstrapRiscvOSEarly__ = &kgspBootstrapRiscvOSEarly_GA102; } // Hal function -- kgspGetGspRmBootUcodeStorage - if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000002UL) )) /* RmVariantHal: PF_KERNEL_ONLY */ + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ { - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x000007e0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 */ - { - pThis->__kgspGetGspRmBootUcodeStorage__ = &kgspGetGspRmBootUcodeStorage_TU102; - } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x01f0f800UL) )) /* ChipHal: GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 */ - { - pThis->__kgspGetGspRmBootUcodeStorage__ = &kgspGetGspRmBootUcodeStorage_GA102; - } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ - { - pThis->__kgspGetGspRmBootUcodeStorage__ = &kgspGetGspRmBootUcodeStorage_GH100; - } + pThis->__kgspGetGspRmBootUcodeStorage__ = &kgspGetGspRmBootUcodeStorage_GH100; + } + else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x000007e0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 */ + { + pThis->__kgspGetGspRmBootUcodeStorage__ = &kgspGetGspRmBootUcodeStorage_TU102; + } + else + { + pThis->__kgspGetGspRmBootUcodeStorage__ = &kgspGetGspRmBootUcodeStorage_GA102; } // Hal function -- kgspGetBinArchiveGspRmBoot - if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000002UL) )) /* RmVariantHal: PF_KERNEL_ONLY */ + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x00000400UL) )) /* ChipHal: GA100 */ { - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x000003e0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 */ - { - pThis->__kgspGetBinArchiveGspRmBoot__ = &kgspGetBinArchiveGspRmBoot_TU102; - } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x00000400UL) )) /* ChipHal: GA100 */ - { - pThis->__kgspGetBinArchiveGspRmBoot__ = &kgspGetBinArchiveGspRmBoot_GA100; - } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0000f800UL) )) /* ChipHal: GA102 | GA103 | GA104 | GA106 | GA107 */ - { - pThis->__kgspGetBinArchiveGspRmBoot__ = &kgspGetBinArchiveGspRmBoot_GA102; - } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ - { - pThis->__kgspGetBinArchiveGspRmBoot__ = &kgspGetBinArchiveGspRmBoot_GH100; - } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x01f00000UL) )) /* ChipHal: AD102 | AD103 | AD104 | AD106 | AD107 */ - { - pThis->__kgspGetBinArchiveGspRmBoot__ = &kgspGetBinArchiveGspRmBoot_AD102; - } + pThis->__kgspGetBinArchiveGspRmBoot__ = &kgspGetBinArchiveGspRmBoot_GA100; + } + else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ + { + pThis->__kgspGetBinArchiveGspRmBoot__ = &kgspGetBinArchiveGspRmBoot_GH100; + } + else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x000003e0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 */ + { + pThis->__kgspGetBinArchiveGspRmBoot__ = &kgspGetBinArchiveGspRmBoot_TU102; + } + else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0000f800UL) )) /* ChipHal: GA102 | GA103 | GA104 | GA106 | GA107 */ + { + pThis->__kgspGetBinArchiveGspRmBoot__ = &kgspGetBinArchiveGspRmBoot_GA102; + } + else + { + pThis->__kgspGetBinArchiveGspRmBoot__ = &kgspGetBinArchiveGspRmBoot_AD102; + } + + // Hal function -- kgspGetBinArchiveConcatenatedFMCDesc + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ + { + pThis->__kgspGetBinArchiveConcatenatedFMCDesc__ = &kgspGetBinArchiveConcatenatedFMCDesc_GH100; + } + else + { + pThis->__kgspGetBinArchiveConcatenatedFMCDesc__ = &kgspGetBinArchiveConcatenatedFMCDesc_80f438; + } + + // Hal function -- kgspGetBinArchiveConcatenatedFMC + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ + { + pThis->__kgspGetBinArchiveConcatenatedFMC__ = &kgspGetBinArchiveConcatenatedFMC_GH100; + } + else + { + pThis->__kgspGetBinArchiveConcatenatedFMC__ = &kgspGetBinArchiveConcatenatedFMC_80f438; } // Hal function -- kgspGetBinArchiveGspRmFmcGfwDebugSigned - if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000002UL) )) /* RmVariantHal: PF_KERNEL_ONLY */ + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ { - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ - { - pThis->__kgspGetBinArchiveGspRmFmcGfwDebugSigned__ = &kgspGetBinArchiveGspRmFmcGfwDebugSigned_GH100; - } - // default - else - { - pThis->__kgspGetBinArchiveGspRmFmcGfwDebugSigned__ = &kgspGetBinArchiveGspRmFmcGfwDebugSigned_80f438; - } + pThis->__kgspGetBinArchiveGspRmFmcGfwDebugSigned__ = &kgspGetBinArchiveGspRmFmcGfwDebugSigned_GH100; + } + // default + else + { + pThis->__kgspGetBinArchiveGspRmFmcGfwDebugSigned__ = &kgspGetBinArchiveGspRmFmcGfwDebugSigned_80f438; } // Hal function -- kgspGetBinArchiveGspRmFmcGfwProdSigned - if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000002UL) )) /* RmVariantHal: PF_KERNEL_ONLY */ + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ { - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ - { - pThis->__kgspGetBinArchiveGspRmFmcGfwProdSigned__ = &kgspGetBinArchiveGspRmFmcGfwProdSigned_GH100; - } - // default - else - { - pThis->__kgspGetBinArchiveGspRmFmcGfwProdSigned__ = &kgspGetBinArchiveGspRmFmcGfwProdSigned_80f438; - } + pThis->__kgspGetBinArchiveGspRmFmcGfwProdSigned__ = &kgspGetBinArchiveGspRmFmcGfwProdSigned_GH100; + } + // default + else + { + pThis->__kgspGetBinArchiveGspRmFmcGfwProdSigned__ = &kgspGetBinArchiveGspRmFmcGfwProdSigned_80f438; + } + + // Hal function -- kgspGetBinArchiveGspRmCcFmcGfwProdSigned + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ + { + pThis->__kgspGetBinArchiveGspRmCcFmcGfwProdSigned__ = &kgspGetBinArchiveGspRmCcFmcGfwProdSigned_GH100; + } + // default + else + { + pThis->__kgspGetBinArchiveGspRmCcFmcGfwProdSigned__ = &kgspGetBinArchiveGspRmCcFmcGfwProdSigned_80f438; } // Hal function -- kgspCalculateFbLayout - if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000002UL) )) /* RmVariantHal: PF_KERNEL_ONLY */ + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ { - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x01f0ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 */ - { - pThis->__kgspCalculateFbLayout__ = &kgspCalculateFbLayout_TU102; - } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ - { - pThis->__kgspCalculateFbLayout__ = &kgspCalculateFbLayout_GH100; - } + pThis->__kgspCalculateFbLayout__ = &kgspCalculateFbLayout_GH100; + } + else + { + pThis->__kgspCalculateFbLayout__ = &kgspCalculateFbLayout_TU102; } // Hal function -- kgspGetNonWprHeapSize - if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000002UL) )) /* RmVariantHal: PF_KERNEL_ONLY */ + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ { - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x01f0ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 */ - { - pThis->__kgspGetNonWprHeapSize__ = &kgspGetNonWprHeapSize_ed6b8b; - } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ - { - pThis->__kgspGetNonWprHeapSize__ = &kgspGetNonWprHeapSize_d505ea; - } + pThis->__kgspGetNonWprHeapSize__ = &kgspGetNonWprHeapSize_d505ea; + } + else + { + pThis->__kgspGetNonWprHeapSize__ = &kgspGetNonWprHeapSize_ed6b8b; } // Hal function -- kgspExecuteSequencerCommand - if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000002UL) )) /* RmVariantHal: PF_KERNEL_ONLY */ + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x000007e0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 */ { - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x000007e0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 */ - { - pThis->__kgspExecuteSequencerCommand__ = &kgspExecuteSequencerCommand_TU102; - } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x11f0f800UL) )) /* ChipHal: GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 | GH100 */ - { - pThis->__kgspExecuteSequencerCommand__ = &kgspExecuteSequencerCommand_GA102; - } + pThis->__kgspExecuteSequencerCommand__ = &kgspExecuteSequencerCommand_TU102; + } + else + { + pThis->__kgspExecuteSequencerCommand__ = &kgspExecuteSequencerCommand_GA102; } // Hal function -- kgspReadUcodeFuseVersion - if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000002UL) )) /* RmVariantHal: PF_KERNEL_ONLY */ + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x000003e0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 */ { - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x000003e0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 */ - { - pThis->__kgspReadUcodeFuseVersion__ = &kgspReadUcodeFuseVersion_b2b553; - } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x11f0fc00UL) )) /* ChipHal: GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 | GH100 */ - { - pThis->__kgspReadUcodeFuseVersion__ = &kgspReadUcodeFuseVersion_GA100; - } + pThis->__kgspReadUcodeFuseVersion__ = &kgspReadUcodeFuseVersion_b2b553; + } + else + { + pThis->__kgspReadUcodeFuseVersion__ = &kgspReadUcodeFuseVersion_GA100; } // Hal function -- kgspResetHw - if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000002UL) )) /* RmVariantHal: PF_KERNEL_ONLY */ + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ { - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x01f0ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 */ - { - pThis->__kgspResetHw__ = &kgspResetHw_TU102; - } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ - { - pThis->__kgspResetHw__ = &kgspResetHw_GH100; - } + pThis->__kgspResetHw__ = &kgspResetHw_GH100; } - - // Hal function -- kgspIsEngineInReset - if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000002UL) )) /* RmVariantHal: PF_KERNEL_ONLY */ + else { - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x11f0ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 | GH100 */ - { - pThis->__kgspIsEngineInReset__ = &kgspIsEngineInReset_TU102; - } + pThis->__kgspResetHw__ = &kgspResetHw_TU102; } // Hal function -- kgspIsWpr2Up - if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000002UL) )) /* RmVariantHal: PF_KERNEL_ONLY */ + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ { - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x01f0ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 */ - { - pThis->__kgspIsWpr2Up__ = &kgspIsWpr2Up_TU102; - } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ - { - pThis->__kgspIsWpr2Up__ = &kgspIsWpr2Up_GH100; - } + pThis->__kgspIsWpr2Up__ = &kgspIsWpr2Up_GH100; + } + else + { + pThis->__kgspIsWpr2Up__ = &kgspIsWpr2Up_TU102; } // Hal function -- kgspGetFrtsSize - if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000002UL) )) /* RmVariantHal: PF_KERNEL_ONLY */ + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x00000400UL) )) /* ChipHal: GA100 */ { - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x01f0fbe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 */ - { - pThis->__kgspGetFrtsSize__ = &kgspGetFrtsSize_TU102; - } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000400UL) )) /* ChipHal: GA100 | GH100 */ - { - pThis->__kgspGetFrtsSize__ = &kgspGetFrtsSize_4a4dee; - } + pThis->__kgspGetFrtsSize__ = &kgspGetFrtsSize_4a4dee; + } + else + { + pThis->__kgspGetFrtsSize__ = &kgspGetFrtsSize_TU102; } // Hal function -- kgspGetPrescrubbedTopFbSize - if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000002UL) )) /* RmVariantHal: PF_KERNEL_ONLY */ + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000400UL) )) /* ChipHal: GA100 | GH100 */ { - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x01f0fbe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 */ - { - pThis->__kgspGetPrescrubbedTopFbSize__ = &kgspGetPrescrubbedTopFbSize_e1e623; - } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000400UL) )) /* ChipHal: GA100 | GH100 */ - { - pThis->__kgspGetPrescrubbedTopFbSize__ = &kgspGetPrescrubbedTopFbSize_dd2c0b; - } + pThis->__kgspGetPrescrubbedTopFbSize__ = &kgspGetPrescrubbedTopFbSize_604eb7; + } + else + { + pThis->__kgspGetPrescrubbedTopFbSize__ = &kgspGetPrescrubbedTopFbSize_e1e623; } // Hal function -- kgspExtractVbiosFromRom - if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000002UL) )) /* RmVariantHal: PF_KERNEL_ONLY */ + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ { - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x01f0ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 */ - { - pThis->__kgspExtractVbiosFromRom__ = &kgspExtractVbiosFromRom_TU102; - } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ - { - pThis->__kgspExtractVbiosFromRom__ = &kgspExtractVbiosFromRom_395e98; - } + pThis->__kgspExtractVbiosFromRom__ = &kgspExtractVbiosFromRom_395e98; + } + else + { + pThis->__kgspExtractVbiosFromRom__ = &kgspExtractVbiosFromRom_TU102; } // Hal function -- kgspExecuteFwsecFrts - if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000002UL) )) /* RmVariantHal: PF_KERNEL_ONLY */ + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000400UL) )) /* ChipHal: GA100 | GH100 */ { - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x01f0fbe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 */ - { - pThis->__kgspExecuteFwsecFrts__ = &kgspExecuteFwsecFrts_TU102; - } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000400UL) )) /* ChipHal: GA100 | GH100 */ - { - pThis->__kgspExecuteFwsecFrts__ = &kgspExecuteFwsecFrts_5baef9; - } + pThis->__kgspExecuteFwsecFrts__ = &kgspExecuteFwsecFrts_5baef9; + } + else + { + pThis->__kgspExecuteFwsecFrts__ = &kgspExecuteFwsecFrts_TU102; } // Hal function -- kgspExecuteFwsecSb - if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000002UL) )) /* RmVariantHal: PF_KERNEL_ONLY */ + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ { - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x01f0ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 */ - { - pThis->__kgspExecuteFwsecSb__ = &kgspExecuteFwsecSb_TU102; - } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ - { - pThis->__kgspExecuteFwsecSb__ = &kgspExecuteFwsecSb_ac1694; - } + pThis->__kgspExecuteFwsecSb__ = &kgspExecuteFwsecSb_ac1694; + } + else + { + pThis->__kgspExecuteFwsecSb__ = &kgspExecuteFwsecSb_TU102; } // Hal function -- kgspExecuteScrubberIfNeeded - if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000002UL) )) /* RmVariantHal: PF_KERNEL_ONLY */ + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x01f00000UL) )) /* ChipHal: AD102 | AD103 | AD104 | AD106 | AD107 */ { - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x01f00000UL) )) /* ChipHal: AD102 | AD103 | AD104 | AD106 | AD107 */ - { - pThis->__kgspExecuteScrubberIfNeeded__ = &kgspExecuteScrubberIfNeeded_AD102; - } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x1000ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | GH100 */ - { - pThis->__kgspExecuteScrubberIfNeeded__ = &kgspExecuteScrubberIfNeeded_5baef9; - } + pThis->__kgspExecuteScrubberIfNeeded__ = &kgspExecuteScrubberIfNeeded_AD102; + } + else + { + pThis->__kgspExecuteScrubberIfNeeded__ = &kgspExecuteScrubberIfNeeded_5baef9; } // Hal function -- kgspExecuteBooterLoad - if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000002UL) )) /* RmVariantHal: PF_KERNEL_ONLY */ + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ { - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x01f0ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 */ - { - pThis->__kgspExecuteBooterLoad__ = &kgspExecuteBooterLoad_TU102; - } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ - { - pThis->__kgspExecuteBooterLoad__ = &kgspExecuteBooterLoad_5baef9; - } + pThis->__kgspExecuteBooterLoad__ = &kgspExecuteBooterLoad_5baef9; + } + else + { + pThis->__kgspExecuteBooterLoad__ = &kgspExecuteBooterLoad_TU102; } // Hal function -- kgspExecuteBooterUnloadIfNeeded - if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000002UL) )) /* RmVariantHal: PF_KERNEL_ONLY */ + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ { - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x01f0ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 */ - { - pThis->__kgspExecuteBooterUnloadIfNeeded__ = &kgspExecuteBooterUnloadIfNeeded_TU102; - } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ - { - pThis->__kgspExecuteBooterUnloadIfNeeded__ = &kgspExecuteBooterUnloadIfNeeded_5baef9; - } + pThis->__kgspExecuteBooterUnloadIfNeeded__ = &kgspExecuteBooterUnloadIfNeeded_5baef9; + } + else + { + pThis->__kgspExecuteBooterUnloadIfNeeded__ = &kgspExecuteBooterUnloadIfNeeded_TU102; } // Hal function -- kgspExecuteHsFalcon - if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000002UL) )) /* RmVariantHal: PF_KERNEL_ONLY */ + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ { - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x000007e0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 */ - { - pThis->__kgspExecuteHsFalcon__ = &kgspExecuteHsFalcon_TU102; - } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x01f0f800UL) )) /* ChipHal: GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 */ - { - pThis->__kgspExecuteHsFalcon__ = &kgspExecuteHsFalcon_GA102; - } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ - { - pThis->__kgspExecuteHsFalcon__ = &kgspExecuteHsFalcon_5baef9; - } + pThis->__kgspExecuteHsFalcon__ = &kgspExecuteHsFalcon_5baef9; + } + else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x000007e0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 */ + { + pThis->__kgspExecuteHsFalcon__ = &kgspExecuteHsFalcon_TU102; + } + else + { + pThis->__kgspExecuteHsFalcon__ = &kgspExecuteHsFalcon_GA102; } // Hal function -- kgspWaitForGfwBootOk - if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000002UL) )) /* RmVariantHal: PF_KERNEL_ONLY */ + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ { - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x01f0ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 */ - { - pThis->__kgspWaitForGfwBootOk__ = &kgspWaitForGfwBootOk_TU102; - } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ - { - pThis->__kgspWaitForGfwBootOk__ = &kgspWaitForGfwBootOk_GH100; - } + pThis->__kgspWaitForGfwBootOk__ = &kgspWaitForGfwBootOk_GH100; + } + else + { + pThis->__kgspWaitForGfwBootOk__ = &kgspWaitForGfwBootOk_TU102; } // Hal function -- kgspGetBinArchiveBooterLoadUcode - if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000002UL) )) /* RmVariantHal: PF_KERNEL_ONLY */ + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x00000400UL) )) /* ChipHal: GA100 */ { - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x000000e0UL) )) /* ChipHal: TU102 | TU104 | TU106 */ - { - pThis->__kgspGetBinArchiveBooterLoadUcode__ = &kgspGetBinArchiveBooterLoadUcode_TU102; - } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x00000300UL) )) /* ChipHal: TU116 | TU117 */ - { - pThis->__kgspGetBinArchiveBooterLoadUcode__ = &kgspGetBinArchiveBooterLoadUcode_TU116; - } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x00000400UL) )) /* ChipHal: GA100 */ - { - pThis->__kgspGetBinArchiveBooterLoadUcode__ = &kgspGetBinArchiveBooterLoadUcode_GA100; - } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0000f800UL) )) /* ChipHal: GA102 | GA103 | GA104 | GA106 | GA107 */ - { - pThis->__kgspGetBinArchiveBooterLoadUcode__ = &kgspGetBinArchiveBooterLoadUcode_GA102; - } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x01f00000UL) )) /* ChipHal: AD102 | AD103 | AD104 | AD106 | AD107 */ - { - pThis->__kgspGetBinArchiveBooterLoadUcode__ = &kgspGetBinArchiveBooterLoadUcode_AD102; - } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ - { - pThis->__kgspGetBinArchiveBooterLoadUcode__ = &kgspGetBinArchiveBooterLoadUcode_80f438; - } + pThis->__kgspGetBinArchiveBooterLoadUcode__ = &kgspGetBinArchiveBooterLoadUcode_GA100; + } + else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ + { + pThis->__kgspGetBinArchiveBooterLoadUcode__ = &kgspGetBinArchiveBooterLoadUcode_80f438; + } + else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x00000300UL) )) /* ChipHal: TU116 | TU117 */ + { + pThis->__kgspGetBinArchiveBooterLoadUcode__ = &kgspGetBinArchiveBooterLoadUcode_TU116; + } + else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x000000e0UL) )) /* ChipHal: TU102 | TU104 | TU106 */ + { + pThis->__kgspGetBinArchiveBooterLoadUcode__ = &kgspGetBinArchiveBooterLoadUcode_TU102; + } + else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0000f800UL) )) /* ChipHal: GA102 | GA103 | GA104 | GA106 | GA107 */ + { + pThis->__kgspGetBinArchiveBooterLoadUcode__ = &kgspGetBinArchiveBooterLoadUcode_GA102; + } + else + { + pThis->__kgspGetBinArchiveBooterLoadUcode__ = &kgspGetBinArchiveBooterLoadUcode_AD102; } // Hal function -- kgspGetBinArchiveBooterUnloadUcode - if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000002UL) )) /* RmVariantHal: PF_KERNEL_ONLY */ + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x00000400UL) )) /* ChipHal: GA100 */ { - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x000000e0UL) )) /* ChipHal: TU102 | TU104 | TU106 */ - { - pThis->__kgspGetBinArchiveBooterUnloadUcode__ = &kgspGetBinArchiveBooterUnloadUcode_TU102; - } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x00000300UL) )) /* ChipHal: TU116 | TU117 */ - { - pThis->__kgspGetBinArchiveBooterUnloadUcode__ = &kgspGetBinArchiveBooterUnloadUcode_TU116; - } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x00000400UL) )) /* ChipHal: GA100 */ - { - pThis->__kgspGetBinArchiveBooterUnloadUcode__ = &kgspGetBinArchiveBooterUnloadUcode_GA100; - } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0000f800UL) )) /* ChipHal: GA102 | GA103 | GA104 | GA106 | GA107 */ - { - pThis->__kgspGetBinArchiveBooterUnloadUcode__ = &kgspGetBinArchiveBooterUnloadUcode_GA102; - } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x01f00000UL) )) /* ChipHal: AD102 | AD103 | AD104 | AD106 | AD107 */ - { - pThis->__kgspGetBinArchiveBooterUnloadUcode__ = &kgspGetBinArchiveBooterUnloadUcode_AD102; - } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ - { - pThis->__kgspGetBinArchiveBooterUnloadUcode__ = &kgspGetBinArchiveBooterUnloadUcode_80f438; - } + pThis->__kgspGetBinArchiveBooterUnloadUcode__ = &kgspGetBinArchiveBooterUnloadUcode_GA100; + } + else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ + { + pThis->__kgspGetBinArchiveBooterUnloadUcode__ = &kgspGetBinArchiveBooterUnloadUcode_80f438; + } + else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x00000300UL) )) /* ChipHal: TU116 | TU117 */ + { + pThis->__kgspGetBinArchiveBooterUnloadUcode__ = &kgspGetBinArchiveBooterUnloadUcode_TU116; + } + else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x000000e0UL) )) /* ChipHal: TU102 | TU104 | TU106 */ + { + pThis->__kgspGetBinArchiveBooterUnloadUcode__ = &kgspGetBinArchiveBooterUnloadUcode_TU102; + } + else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0000f800UL) )) /* ChipHal: GA102 | GA103 | GA104 | GA106 | GA107 */ + { + pThis->__kgspGetBinArchiveBooterUnloadUcode__ = &kgspGetBinArchiveBooterUnloadUcode_GA102; + } + else + { + pThis->__kgspGetBinArchiveBooterUnloadUcode__ = &kgspGetBinArchiveBooterUnloadUcode_AD102; } - // Hal function -- kgspGetWprHeapSize - if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000002UL) )) /* RmVariantHal: PF_KERNEL_ONLY */ + // Hal function -- kgspGetMinWprHeapSizeMB + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x000007e0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 */ { - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0000ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 */ - { - pThis->__kgspGetWprHeapSize__ = &kgspGetWprHeapSize_e3e8a1; - } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x01f00000UL) )) /* ChipHal: AD102 | AD103 | AD104 | AD106 | AD107 */ - { - pThis->__kgspGetWprHeapSize__ = &kgspGetWprHeapSize_AD102; - } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ - { - pThis->__kgspGetWprHeapSize__ = &kgspGetWprHeapSize_cffea5; - } + pThis->__kgspGetMinWprHeapSizeMB__ = &kgspGetMinWprHeapSizeMB_7185bf; + } + else + { + pThis->__kgspGetMinWprHeapSizeMB__ = &kgspGetMinWprHeapSizeMB_907c84; + } + + // Hal function -- kgspGetMaxWprHeapSizeMB + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x000007e0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 */ + { + pThis->__kgspGetMaxWprHeapSizeMB__ = &kgspGetMaxWprHeapSizeMB_ad4e6a; + } + else + { + pThis->__kgspGetMaxWprHeapSizeMB__ = &kgspGetMaxWprHeapSizeMB_5839e2; } // Hal function -- kgspInitVgpuPartitionLogging - if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000002UL) )) /* RmVariantHal: PF_KERNEL_ONLY */ + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x000007e0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 */ { - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x1000ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | GH100 */ - { - pThis->__kgspInitVgpuPartitionLogging__ = &kgspInitVgpuPartitionLogging_395e98; - } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x01f00000UL) )) /* ChipHal: AD102 | AD103 | AD104 | AD106 | AD107 */ - { - pThis->__kgspInitVgpuPartitionLogging__ = &kgspInitVgpuPartitionLogging_IMPL; - } + pThis->__kgspInitVgpuPartitionLogging__ = &kgspInitVgpuPartitionLogging_395e98; + } + else + { + pThis->__kgspInitVgpuPartitionLogging__ = &kgspInitVgpuPartitionLogging_IMPL; } // Hal function -- kgspFreeVgpuPartitionLogging - if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000002UL) )) /* RmVariantHal: PF_KERNEL_ONLY */ + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x000007e0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 */ { - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x1000ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | GH100 */ - { - pThis->__kgspFreeVgpuPartitionLogging__ = &kgspFreeVgpuPartitionLogging_395e98; - } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x01f00000UL) )) /* ChipHal: AD102 | AD103 | AD104 | AD106 | AD107 */ - { - pThis->__kgspFreeVgpuPartitionLogging__ = &kgspFreeVgpuPartitionLogging_IMPL; - } + pThis->__kgspFreeVgpuPartitionLogging__ = &kgspFreeVgpuPartitionLogging_395e98; + } + else + { + pThis->__kgspFreeVgpuPartitionLogging__ = &kgspFreeVgpuPartitionLogging_IMPL; } // Hal function -- kgspGetSignatureSectionNamePrefix - if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000002UL) )) /* RmVariantHal: PF_KERNEL_ONLY */ + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ { - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ - { - pThis->__kgspGetSignatureSectionNamePrefix__ = &kgspGetSignatureSectionNamePrefix_GH100; - } - // default - else - { - pThis->__kgspGetSignatureSectionNamePrefix__ = &kgspGetSignatureSectionNamePrefix_789efb; - } + pThis->__kgspGetSignatureSectionNamePrefix__ = &kgspGetSignatureSectionNamePrefix_GH100; + } + // default + else + { + pThis->__kgspGetSignatureSectionNamePrefix__ = &kgspGetSignatureSectionNamePrefix_789efb; } // Hal function -- kgspSetupGspFmcArgs - if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000002UL) )) /* RmVariantHal: PF_KERNEL_ONLY */ + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ { - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ - { - pThis->__kgspSetupGspFmcArgs__ = &kgspSetupGspFmcArgs_GH100; - } - // default - else - { - pThis->__kgspSetupGspFmcArgs__ = &kgspSetupGspFmcArgs_5baef9; - } + pThis->__kgspSetupGspFmcArgs__ = &kgspSetupGspFmcArgs_GH100; + } + // default + else + { + pThis->__kgspSetupGspFmcArgs__ = &kgspSetupGspFmcArgs_5baef9; } + // Hal function -- kgspReadEmem + pThis->__kgspReadEmem__ = &kgspReadEmem_TU102; + pThis->__nvoc_base_OBJENGSTATE.__engstateConstructEngine__ = &__nvoc_thunk_KernelGsp_engstateConstructEngine; pThis->__nvoc_base_IntrService.__intrservRegisterIntrService__ = &__nvoc_thunk_KernelGsp_intrservRegisterIntrService; @@ -768,26 +805,44 @@ pThis->__nvoc_base_KernelFalcon.__kflcnResetHw__ = &__nvoc_thunk_KernelGsp_kflcnResetHw; - pThis->__nvoc_base_KernelFalcon.__kflcnIsEngineInReset__ = &__nvoc_thunk_KernelGsp_kflcnIsEngineInReset; + pThis->__nvoc_base_KernelFalcon.__nvoc_base_KernelCrashCatEngine.__kcrashcatEngineReadEmem__ = &__nvoc_thunk_KernelGsp_kcrashcatEngineReadEmem; - pThis->__kgspStateDestroy__ = &__nvoc_thunk_OBJENGSTATE_kgspStateDestroy; + pThis->__kgspConfigured__ = &__nvoc_thunk_KernelCrashCatEngine_kgspConfigured; + + pThis->__kgspPriRead__ = &__nvoc_thunk_KernelCrashCatEngine_kgspPriRead; + + pThis->__kgspRegWrite__ = &__nvoc_thunk_KernelFalcon_kgspRegWrite; + + pThis->__kgspMaskDmemAddr__ = &__nvoc_thunk_KernelFalcon_kgspMaskDmemAddr; - pThis->__kgspFreeTunableState__ = &__nvoc_thunk_OBJENGSTATE_kgspFreeTunableState; + pThis->__kgspStateDestroy__ = &__nvoc_thunk_OBJENGSTATE_kgspStateDestroy; - pThis->__kgspCompareTunableState__ = &__nvoc_thunk_OBJENGSTATE_kgspCompareTunableState; + pThis->__kgspVprintf__ = &__nvoc_thunk_KernelCrashCatEngine_kgspVprintf; pThis->__kgspClearInterrupt__ = &__nvoc_thunk_IntrService_kgspClearInterrupt; - pThis->__kgspIsPresent__ = &__nvoc_thunk_OBJENGSTATE_kgspIsPresent; + pThis->__kgspPriWrite__ = &__nvoc_thunk_KernelCrashCatEngine_kgspPriWrite; + + pThis->__kgspMapBufferDescriptor__ = &__nvoc_thunk_KernelCrashCatEngine_kgspMapBufferDescriptor; + + pThis->__kgspSyncBufferDescriptor__ = &__nvoc_thunk_KernelCrashCatEngine_kgspSyncBufferDescriptor; - pThis->__kgspReconcileTunableState__ = &__nvoc_thunk_OBJENGSTATE_kgspReconcileTunableState; + pThis->__kgspRegRead__ = &__nvoc_thunk_KernelFalcon_kgspRegRead; + + pThis->__kgspIsPresent__ = &__nvoc_thunk_OBJENGSTATE_kgspIsPresent; pThis->__kgspStateLoad__ = &__nvoc_thunk_OBJENGSTATE_kgspStateLoad; + pThis->__kgspGetScratchOffsets__ = &__nvoc_thunk_KernelCrashCatEngine_kgspGetScratchOffsets; + + pThis->__kgspUnload__ = &__nvoc_thunk_KernelCrashCatEngine_kgspUnload; + pThis->__kgspStateUnload__ = &__nvoc_thunk_OBJENGSTATE_kgspStateUnload; pThis->__kgspServiceNotificationInterrupt__ = &__nvoc_thunk_IntrService_kgspServiceNotificationInterrupt; + pThis->__kgspGetWFL0Offset__ = &__nvoc_thunk_KernelCrashCatEngine_kgspGetWFL0Offset; + pThis->__kgspStateInitLocked__ = &__nvoc_thunk_OBJENGSTATE_kgspStateInitLocked; pThis->__kgspStatePreLoad__ = &__nvoc_thunk_OBJENGSTATE_kgspStatePreLoad; @@ -796,8 +851,6 @@ pThis->__kgspStatePreUnload__ = &__nvoc_thunk_OBJENGSTATE_kgspStatePreUnload; - pThis->__kgspGetTunableState__ = &__nvoc_thunk_OBJENGSTATE_kgspGetTunableState; - pThis->__kgspStateInitUnlocked__ = &__nvoc_thunk_OBJENGSTATE_kgspStateInitUnlocked; pThis->__kgspInitMissing__ = &__nvoc_thunk_OBJENGSTATE_kgspInitMissing; @@ -808,9 +861,9 @@ pThis->__kgspStatePostLoad__ = &__nvoc_thunk_OBJENGSTATE_kgspStatePostLoad; - pThis->__kgspAllocTunableState__ = &__nvoc_thunk_OBJENGSTATE_kgspAllocTunableState; + pThis->__kgspUnmapBufferDescriptor__ = &__nvoc_thunk_KernelCrashCatEngine_kgspUnmapBufferDescriptor; - pThis->__kgspSetTunableState__ = &__nvoc_thunk_OBJENGSTATE_kgspSetTunableState; + pThis->__kgspReadDmem__ = &__nvoc_thunk_KernelCrashCatEngine_kgspReadDmem; } void __nvoc_init_funcTable_KernelGsp(KernelGsp *pThis, RmHalspecOwner *pRmhalspecowner) { @@ -825,6 +878,8 @@ pThis->__nvoc_pbase_Object = &pThis->__nvoc_base_OBJENGSTATE.__nvoc_base_Object; pThis->__nvoc_pbase_OBJENGSTATE = &pThis->__nvoc_base_OBJENGSTATE; pThis->__nvoc_pbase_IntrService = &pThis->__nvoc_base_IntrService; + pThis->__nvoc_pbase_CrashCatEngine = &pThis->__nvoc_base_KernelFalcon.__nvoc_base_KernelCrashCatEngine.__nvoc_base_CrashCatEngine; + pThis->__nvoc_pbase_KernelCrashCatEngine = &pThis->__nvoc_base_KernelFalcon.__nvoc_base_KernelCrashCatEngine; pThis->__nvoc_pbase_KernelFalcon = &pThis->__nvoc_base_KernelFalcon; __nvoc_init_OBJENGSTATE(&pThis->__nvoc_base_OBJENGSTATE); __nvoc_init_IntrService(&pThis->__nvoc_base_IntrService); @@ -838,13 +893,16 @@ KernelGsp *pThis; RmHalspecOwner *pRmhalspecowner; - pThis = portMemAllocNonPaged(sizeof(KernelGsp)); - if (pThis == NULL) return NV_ERR_NO_MEMORY; + status = __nvoc_handleObjCreateMemAlloc(createFlags, sizeof(KernelGsp), (void**)&pThis, (void**)ppThis); + if (status != NV_OK) + return status; portMemSet(pThis, 0, sizeof(KernelGsp)); __nvoc_initRtti(staticCast(pThis, Dynamic), &__nvoc_class_def_KernelGsp); + pThis->__nvoc_base_OBJENGSTATE.__nvoc_base_Object.createFlags = createFlags; + if (pParent != NULL && !(createFlags & NVOC_OBJ_CREATE_FLAGS_PARENT_HALSPEC_ONLY)) { pParentObj = dynamicCast(pParent, Object); @@ -864,11 +922,17 @@ if (status != NV_OK) goto __nvoc_objCreate_KernelGsp_cleanup; *ppThis = pThis; + return NV_OK; __nvoc_objCreate_KernelGsp_cleanup: // do not call destructors here since the constructor already called them - portMemFree(pThis); + if (createFlags & NVOC_OBJ_CREATE_FLAGS_IN_PLACE_CONSTRUCT) + portMemSet(pThis, 0, sizeof(KernelGsp)); + else + portMemFree(pThis); + + // coverity[leaked_storage:FALSE] return status; } diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/generated/g_kernel_gsp_nvoc.h nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_kernel_gsp_nvoc.h --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/generated/g_kernel_gsp_nvoc.h 2023-10-25 20:27:08.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_kernel_gsp_nvoc.h 2024-03-05 22:18:29.000000000 +0000 @@ -7,7 +7,7 @@ #endif /* - * SPDX-FileCopyrightText: Copyright (c) 2017-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2017-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -48,12 +48,14 @@ #include "gpu/falcon/kernel_falcon.h" #include "gpu/gsp/gsp_static_config.h" #include "gpu/gsp/gsp_init_args.h" +#include "gpu/gsp/gsp_fw_heap.h" #include "nv-firmware.h" #include "nv_sriov_defines.h" #include "rmRiscvUcode.h" #include "libos_init_args.h" #include "gsp_fw_wpr_meta.h" +#include "gsp_fw_sr_meta.h" #include "liblogdecode.h" /*! @@ -207,6 +209,7 @@ #define GSP_IMAGE_SECTION_NAME ".fwimage" #define GSP_LOGGING_SECTION_NAME ".fwlogging" #define GSP_SIGNATURE_SECTION_NAME_PREFIX ".fwsignature_" +#define GSP_CC_SIGNATURE_SECTION_NAME_PREFIX ".fwsignature_cc_" /*! * Index into libosLogDecode array. @@ -239,6 +242,9 @@ #else #define PRIVATE_FIELD(x) NVOC_PRIVATE_FIELD(x) #endif +struct MESSAGE_QUEUE_COLLECTION; + + struct KernelGsp { const struct NVOC_RTTI *__nvoc_rtti; struct OBJENGSTATE __nvoc_base_OBJENGSTATE; @@ -247,6 +253,8 @@ struct Object *__nvoc_pbase_Object; struct OBJENGSTATE *__nvoc_pbase_OBJENGSTATE; struct IntrService *__nvoc_pbase_IntrService; + struct CrashCatEngine *__nvoc_pbase_CrashCatEngine; + struct KernelCrashCatEngine *__nvoc_pbase_KernelCrashCatEngine; struct KernelFalcon *__nvoc_pbase_KernelFalcon; struct KernelGsp *__nvoc_pbase_KernelGsp; NV_STATUS (*__kgspConstructEngine__)(struct OBJGPU *, struct KernelGsp *, ENGDESCRIPTOR); @@ -259,14 +267,16 @@ NV_STATUS (*__kgspBootstrapRiscvOSEarly__)(struct OBJGPU *, struct KernelGsp *, GSP_FIRMWARE *); void (*__kgspGetGspRmBootUcodeStorage__)(struct OBJGPU *, struct KernelGsp *, BINDATA_STORAGE **, BINDATA_STORAGE **); const BINDATA_ARCHIVE *(*__kgspGetBinArchiveGspRmBoot__)(struct KernelGsp *); + const BINDATA_ARCHIVE *(*__kgspGetBinArchiveConcatenatedFMCDesc__)(struct KernelGsp *); + const BINDATA_ARCHIVE *(*__kgspGetBinArchiveConcatenatedFMC__)(struct KernelGsp *); const BINDATA_ARCHIVE *(*__kgspGetBinArchiveGspRmFmcGfwDebugSigned__)(struct KernelGsp *); const BINDATA_ARCHIVE *(*__kgspGetBinArchiveGspRmFmcGfwProdSigned__)(struct KernelGsp *); + const BINDATA_ARCHIVE *(*__kgspGetBinArchiveGspRmCcFmcGfwProdSigned__)(struct KernelGsp *); NV_STATUS (*__kgspCalculateFbLayout__)(struct OBJGPU *, struct KernelGsp *, GSP_FIRMWARE *); NvU32 (*__kgspGetNonWprHeapSize__)(struct OBJGPU *, struct KernelGsp *); NV_STATUS (*__kgspExecuteSequencerCommand__)(struct OBJGPU *, struct KernelGsp *, NvU32, NvU32 *, NvU32); NvU32 (*__kgspReadUcodeFuseVersion__)(struct OBJGPU *, struct KernelGsp *, NvU32); NV_STATUS (*__kgspResetHw__)(struct OBJGPU *, struct KernelGsp *); - NvBool (*__kgspIsEngineInReset__)(struct OBJGPU *, struct KernelGsp *); NvBool (*__kgspIsWpr2Up__)(struct OBJGPU *, struct KernelGsp *); NvU32 (*__kgspGetFrtsSize__)(struct OBJGPU *, struct KernelGsp *); NvU64 (*__kgspGetPrescrubbedTopFbSize__)(struct OBJGPU *, struct KernelGsp *); @@ -275,38 +285,51 @@ NV_STATUS (*__kgspExecuteFwsecSb__)(struct OBJGPU *, struct KernelGsp *, KernelGspFlcnUcode *); NV_STATUS (*__kgspExecuteScrubberIfNeeded__)(struct OBJGPU *, struct KernelGsp *); NV_STATUS (*__kgspExecuteBooterLoad__)(struct OBJGPU *, struct KernelGsp *, const NvU64); - NV_STATUS (*__kgspExecuteBooterUnloadIfNeeded__)(struct OBJGPU *, struct KernelGsp *); + NV_STATUS (*__kgspExecuteBooterUnloadIfNeeded__)(struct OBJGPU *, struct KernelGsp *, const NvU64); NV_STATUS (*__kgspExecuteHsFalcon__)(struct OBJGPU *, struct KernelGsp *, KernelGspFlcnUcode *, struct KernelFalcon *, NvU32 *, NvU32 *); NV_STATUS (*__kgspWaitForGfwBootOk__)(struct OBJGPU *, struct KernelGsp *); const BINDATA_ARCHIVE *(*__kgspGetBinArchiveBooterLoadUcode__)(struct KernelGsp *); const BINDATA_ARCHIVE *(*__kgspGetBinArchiveBooterUnloadUcode__)(struct KernelGsp *); - NvU64 (*__kgspGetWprHeapSize__)(struct OBJGPU *, struct KernelGsp *); + NvU64 (*__kgspGetMinWprHeapSizeMB__)(struct OBJGPU *, struct KernelGsp *); + NvU64 (*__kgspGetMaxWprHeapSizeMB__)(struct OBJGPU *, struct KernelGsp *); NV_STATUS (*__kgspInitVgpuPartitionLogging__)(struct OBJGPU *, struct KernelGsp *, NvU32, NvU64, NvU64, NvU64, NvU64); NV_STATUS (*__kgspFreeVgpuPartitionLogging__)(struct OBJGPU *, struct KernelGsp *, NvU32); const char *(*__kgspGetSignatureSectionNamePrefix__)(struct OBJGPU *, struct KernelGsp *); NV_STATUS (*__kgspSetupGspFmcArgs__)(struct OBJGPU *, struct KernelGsp *, GSP_FIRMWARE *); + void (*__kgspReadEmem__)(struct KernelGsp *, NvU64, NvU64, void *); + NvBool (*__kgspConfigured__)(struct KernelGsp *); + NvU32 (*__kgspPriRead__)(struct KernelGsp *, NvU32); + void (*__kgspRegWrite__)(struct OBJGPU *, struct KernelGsp *, NvU32, NvU32); + NvU32 (*__kgspMaskDmemAddr__)(struct OBJGPU *, struct KernelGsp *, NvU32); void (*__kgspStateDestroy__)(POBJGPU, struct KernelGsp *); - void (*__kgspFreeTunableState__)(POBJGPU, struct KernelGsp *, void *); - NV_STATUS (*__kgspCompareTunableState__)(POBJGPU, struct KernelGsp *, void *, void *); + void (*__kgspVprintf__)(struct KernelGsp *, NvBool, const char *, va_list); NvBool (*__kgspClearInterrupt__)(struct OBJGPU *, struct KernelGsp *, IntrServiceClearInterruptArguments *); + void (*__kgspPriWrite__)(struct KernelGsp *, NvU32, NvU32); + void *(*__kgspMapBufferDescriptor__)(struct KernelGsp *, CrashCatBufferDescriptor *); + void (*__kgspSyncBufferDescriptor__)(struct KernelGsp *, CrashCatBufferDescriptor *, NvU32, NvU32); + NvU32 (*__kgspRegRead__)(struct OBJGPU *, struct KernelGsp *, NvU32); NvBool (*__kgspIsPresent__)(POBJGPU, struct KernelGsp *); - NV_STATUS (*__kgspReconcileTunableState__)(POBJGPU, struct KernelGsp *, void *); NV_STATUS (*__kgspStateLoad__)(POBJGPU, struct KernelGsp *, NvU32); + const NvU32 *(*__kgspGetScratchOffsets__)(struct KernelGsp *, NV_CRASHCAT_SCRATCH_GROUP_ID); + void (*__kgspUnload__)(struct KernelGsp *); NV_STATUS (*__kgspStateUnload__)(POBJGPU, struct KernelGsp *, NvU32); NV_STATUS (*__kgspServiceNotificationInterrupt__)(struct OBJGPU *, struct KernelGsp *, IntrServiceServiceNotificationInterruptArguments *); + NvU32 (*__kgspGetWFL0Offset__)(struct KernelGsp *); NV_STATUS (*__kgspStateInitLocked__)(POBJGPU, struct KernelGsp *); NV_STATUS (*__kgspStatePreLoad__)(POBJGPU, struct KernelGsp *, NvU32); NV_STATUS (*__kgspStatePostUnload__)(POBJGPU, struct KernelGsp *, NvU32); NV_STATUS (*__kgspStatePreUnload__)(POBJGPU, struct KernelGsp *, NvU32); - NV_STATUS (*__kgspGetTunableState__)(POBJGPU, struct KernelGsp *, void *); NV_STATUS (*__kgspStateInitUnlocked__)(POBJGPU, struct KernelGsp *); void (*__kgspInitMissing__)(POBJGPU, struct KernelGsp *); NV_STATUS (*__kgspStatePreInitLocked__)(POBJGPU, struct KernelGsp *); NV_STATUS (*__kgspStatePreInitUnlocked__)(POBJGPU, struct KernelGsp *); NV_STATUS (*__kgspStatePostLoad__)(POBJGPU, struct KernelGsp *, NvU32); - NV_STATUS (*__kgspAllocTunableState__)(POBJGPU, struct KernelGsp *, void **); - NV_STATUS (*__kgspSetTunableState__)(POBJGPU, struct KernelGsp *, void *); + void (*__kgspUnmapBufferDescriptor__)(struct KernelGsp *, CrashCatBufferDescriptor *); + void (*__kgspReadDmem__)(struct KernelGsp *, NvU32, NvU32, void *); + struct MESSAGE_QUEUE_COLLECTION *pMQCollection; struct OBJRPC *pRpc; + struct OBJRPC *pLocklessRpc; + char vbiosVersionStr[16]; KernelGspFlcnUcode *pFwsecUcode; KernelGspFlcnUcode *pScrubberUcode; KernelGspFlcnUcode *pBooterLoadUcode; @@ -314,6 +337,8 @@ MEMORY_DESCRIPTOR *pWprMetaDescriptor; GspFwWprMeta *pWprMeta; NvP64 pWprMetaMappingPriv; + MEMORY_DESCRIPTOR *pSRMetaDescriptor; + MEMORY_DESCRIPTOR *pSRRadix3Descriptor; MEMORY_DESCRIPTOR *pGspFmcArgumentsDescriptor; GSP_FMC_BOOT_PARAMS *pGspFmcArgumentsCached; NvP64 pGspFmcArgumentsMappingPriv; @@ -340,6 +365,7 @@ NvU64 logElfDataSize; PORT_MUTEX *pNvlogFlushMtx; NvBool bLibosLogsPollingEnabled; + NvU8 bootAttempts; NvBool bInInit; NvBool bInLockdown; NvBool bPollingForRpcResponse; @@ -347,8 +373,16 @@ MEMORY_DESCRIPTOR *pMemDesc_simAccessBuf; SimAccessBuffer *pSimAccessBuf; NvP64 pSimAccessBufPriv; + MEMORY_DESCRIPTOR *pProfilerSamplesMD; + void *pProfilerSamplesMDPriv; + void *pProfilerSamples; GspStaticConfigInfo gspStaticInfo; + NvBool bIsTaskIsrQueueRequired; NvBool bPartitionedFmc; + NvBool bScrubberUcodeSupported; + NvU32 fwHeapParamBaseSize; + NvU32 fwHeapParamOsCarveoutSize; + NvU8 ememPort; }; #ifndef __NVOC_CLASS_KernelGsp_TYPEDEF__ @@ -398,10 +432,16 @@ #define kgspGetGspRmBootUcodeStorage_HAL(pGpu, pKernelGsp, ppBinStorageImage, ppBinStorageDesc) kgspGetGspRmBootUcodeStorage_DISPATCH(pGpu, pKernelGsp, ppBinStorageImage, ppBinStorageDesc) #define kgspGetBinArchiveGspRmBoot(pKernelGsp) kgspGetBinArchiveGspRmBoot_DISPATCH(pKernelGsp) #define kgspGetBinArchiveGspRmBoot_HAL(pKernelGsp) kgspGetBinArchiveGspRmBoot_DISPATCH(pKernelGsp) +#define kgspGetBinArchiveConcatenatedFMCDesc(pKernelGsp) kgspGetBinArchiveConcatenatedFMCDesc_DISPATCH(pKernelGsp) +#define kgspGetBinArchiveConcatenatedFMCDesc_HAL(pKernelGsp) kgspGetBinArchiveConcatenatedFMCDesc_DISPATCH(pKernelGsp) +#define kgspGetBinArchiveConcatenatedFMC(pKernelGsp) kgspGetBinArchiveConcatenatedFMC_DISPATCH(pKernelGsp) +#define kgspGetBinArchiveConcatenatedFMC_HAL(pKernelGsp) kgspGetBinArchiveConcatenatedFMC_DISPATCH(pKernelGsp) #define kgspGetBinArchiveGspRmFmcGfwDebugSigned(pKernelGsp) kgspGetBinArchiveGspRmFmcGfwDebugSigned_DISPATCH(pKernelGsp) #define kgspGetBinArchiveGspRmFmcGfwDebugSigned_HAL(pKernelGsp) kgspGetBinArchiveGspRmFmcGfwDebugSigned_DISPATCH(pKernelGsp) #define kgspGetBinArchiveGspRmFmcGfwProdSigned(pKernelGsp) kgspGetBinArchiveGspRmFmcGfwProdSigned_DISPATCH(pKernelGsp) #define kgspGetBinArchiveGspRmFmcGfwProdSigned_HAL(pKernelGsp) kgspGetBinArchiveGspRmFmcGfwProdSigned_DISPATCH(pKernelGsp) +#define kgspGetBinArchiveGspRmCcFmcGfwProdSigned(pKernelGsp) kgspGetBinArchiveGspRmCcFmcGfwProdSigned_DISPATCH(pKernelGsp) +#define kgspGetBinArchiveGspRmCcFmcGfwProdSigned_HAL(pKernelGsp) kgspGetBinArchiveGspRmCcFmcGfwProdSigned_DISPATCH(pKernelGsp) #define kgspCalculateFbLayout(pGpu, pKernelGsp, pGspFw) kgspCalculateFbLayout_DISPATCH(pGpu, pKernelGsp, pGspFw) #define kgspCalculateFbLayout_HAL(pGpu, pKernelGsp, pGspFw) kgspCalculateFbLayout_DISPATCH(pGpu, pKernelGsp, pGspFw) #define kgspGetNonWprHeapSize(pGpu, pKernelGsp) kgspGetNonWprHeapSize_DISPATCH(pGpu, pKernelGsp) @@ -412,8 +452,6 @@ #define kgspReadUcodeFuseVersion_HAL(pGpu, pKernelGsp, ucodeId) kgspReadUcodeFuseVersion_DISPATCH(pGpu, pKernelGsp, ucodeId) #define kgspResetHw(pGpu, pKernelGsp) kgspResetHw_DISPATCH(pGpu, pKernelGsp) #define kgspResetHw_HAL(pGpu, pKernelGsp) kgspResetHw_DISPATCH(pGpu, pKernelGsp) -#define kgspIsEngineInReset(pGpu, pKernelGsp) kgspIsEngineInReset_DISPATCH(pGpu, pKernelGsp) -#define kgspIsEngineInReset_HAL(pGpu, pKernelGsp) kgspIsEngineInReset_DISPATCH(pGpu, pKernelGsp) #define kgspIsWpr2Up(pGpu, pKernelGsp) kgspIsWpr2Up_DISPATCH(pGpu, pKernelGsp) #define kgspIsWpr2Up_HAL(pGpu, pKernelGsp) kgspIsWpr2Up_DISPATCH(pGpu, pKernelGsp) #define kgspGetFrtsSize(pGpu, pKernelGsp) kgspGetFrtsSize_DISPATCH(pGpu, pKernelGsp) @@ -428,10 +466,10 @@ #define kgspExecuteFwsecSb_HAL(pGpu, pKernelGsp, pFwsecUcode) kgspExecuteFwsecSb_DISPATCH(pGpu, pKernelGsp, pFwsecUcode) #define kgspExecuteScrubberIfNeeded(pGpu, pKernelGsp) kgspExecuteScrubberIfNeeded_DISPATCH(pGpu, pKernelGsp) #define kgspExecuteScrubberIfNeeded_HAL(pGpu, pKernelGsp) kgspExecuteScrubberIfNeeded_DISPATCH(pGpu, pKernelGsp) -#define kgspExecuteBooterLoad(pGpu, pKernelGsp, gspFwWprMetaOffset) kgspExecuteBooterLoad_DISPATCH(pGpu, pKernelGsp, gspFwWprMetaOffset) -#define kgspExecuteBooterLoad_HAL(pGpu, pKernelGsp, gspFwWprMetaOffset) kgspExecuteBooterLoad_DISPATCH(pGpu, pKernelGsp, gspFwWprMetaOffset) -#define kgspExecuteBooterUnloadIfNeeded(pGpu, pKernelGsp) kgspExecuteBooterUnloadIfNeeded_DISPATCH(pGpu, pKernelGsp) -#define kgspExecuteBooterUnloadIfNeeded_HAL(pGpu, pKernelGsp) kgspExecuteBooterUnloadIfNeeded_DISPATCH(pGpu, pKernelGsp) +#define kgspExecuteBooterLoad(pGpu, pKernelGsp, sysmemAddrOfData) kgspExecuteBooterLoad_DISPATCH(pGpu, pKernelGsp, sysmemAddrOfData) +#define kgspExecuteBooterLoad_HAL(pGpu, pKernelGsp, sysmemAddrOfData) kgspExecuteBooterLoad_DISPATCH(pGpu, pKernelGsp, sysmemAddrOfData) +#define kgspExecuteBooterUnloadIfNeeded(pGpu, pKernelGsp, sysmemAddrOfSuspendResumeData) kgspExecuteBooterUnloadIfNeeded_DISPATCH(pGpu, pKernelGsp, sysmemAddrOfSuspendResumeData) +#define kgspExecuteBooterUnloadIfNeeded_HAL(pGpu, pKernelGsp, sysmemAddrOfSuspendResumeData) kgspExecuteBooterUnloadIfNeeded_DISPATCH(pGpu, pKernelGsp, sysmemAddrOfSuspendResumeData) #define kgspExecuteHsFalcon(pGpu, pKernelGsp, pFlcnUcode, pKernelFlcn, pMailbox0, pMailbox1) kgspExecuteHsFalcon_DISPATCH(pGpu, pKernelGsp, pFlcnUcode, pKernelFlcn, pMailbox0, pMailbox1) #define kgspExecuteHsFalcon_HAL(pGpu, pKernelGsp, pFlcnUcode, pKernelFlcn, pMailbox0, pMailbox1) kgspExecuteHsFalcon_DISPATCH(pGpu, pKernelGsp, pFlcnUcode, pKernelFlcn, pMailbox0, pMailbox1) #define kgspWaitForGfwBootOk(pGpu, pKernelGsp) kgspWaitForGfwBootOk_DISPATCH(pGpu, pKernelGsp) @@ -440,8 +478,10 @@ #define kgspGetBinArchiveBooterLoadUcode_HAL(pKernelGsp) kgspGetBinArchiveBooterLoadUcode_DISPATCH(pKernelGsp) #define kgspGetBinArchiveBooterUnloadUcode(pKernelGsp) kgspGetBinArchiveBooterUnloadUcode_DISPATCH(pKernelGsp) #define kgspGetBinArchiveBooterUnloadUcode_HAL(pKernelGsp) kgspGetBinArchiveBooterUnloadUcode_DISPATCH(pKernelGsp) -#define kgspGetWprHeapSize(pGpu, pKernelGsp) kgspGetWprHeapSize_DISPATCH(pGpu, pKernelGsp) -#define kgspGetWprHeapSize_HAL(pGpu, pKernelGsp) kgspGetWprHeapSize_DISPATCH(pGpu, pKernelGsp) +#define kgspGetMinWprHeapSizeMB(pGpu, pKernelGsp) kgspGetMinWprHeapSizeMB_DISPATCH(pGpu, pKernelGsp) +#define kgspGetMinWprHeapSizeMB_HAL(pGpu, pKernelGsp) kgspGetMinWprHeapSizeMB_DISPATCH(pGpu, pKernelGsp) +#define kgspGetMaxWprHeapSizeMB(pGpu, pKernelGsp) kgspGetMaxWprHeapSizeMB_DISPATCH(pGpu, pKernelGsp) +#define kgspGetMaxWprHeapSizeMB_HAL(pGpu, pKernelGsp) kgspGetMaxWprHeapSizeMB_DISPATCH(pGpu, pKernelGsp) #define kgspInitVgpuPartitionLogging(pGpu, pKernelGsp, gfid, initTaskLogBUffOffset, initTaskLogBUffSize, vgpuTaskLogBUffOffset, vgpuTaskLogBuffSize) kgspInitVgpuPartitionLogging_DISPATCH(pGpu, pKernelGsp, gfid, initTaskLogBUffOffset, initTaskLogBUffSize, vgpuTaskLogBUffOffset, vgpuTaskLogBuffSize) #define kgspInitVgpuPartitionLogging_HAL(pGpu, pKernelGsp, gfid, initTaskLogBUffOffset, initTaskLogBUffSize, vgpuTaskLogBUffOffset, vgpuTaskLogBuffSize) kgspInitVgpuPartitionLogging_DISPATCH(pGpu, pKernelGsp, gfid, initTaskLogBUffOffset, initTaskLogBUffSize, vgpuTaskLogBUffOffset, vgpuTaskLogBuffSize) #define kgspFreeVgpuPartitionLogging(pGpu, pKernelGsp, gfid) kgspFreeVgpuPartitionLogging_DISPATCH(pGpu, pKernelGsp, gfid) @@ -450,27 +490,37 @@ #define kgspGetSignatureSectionNamePrefix_HAL(pGpu, pKernelGsp) kgspGetSignatureSectionNamePrefix_DISPATCH(pGpu, pKernelGsp) #define kgspSetupGspFmcArgs(pGpu, pKernelGsp, pGspFw) kgspSetupGspFmcArgs_DISPATCH(pGpu, pKernelGsp, pGspFw) #define kgspSetupGspFmcArgs_HAL(pGpu, pKernelGsp, pGspFw) kgspSetupGspFmcArgs_DISPATCH(pGpu, pKernelGsp, pGspFw) +#define kgspReadEmem(pKernelGsp, offset, size, pBuf) kgspReadEmem_DISPATCH(pKernelGsp, offset, size, pBuf) +#define kgspReadEmem_HAL(pKernelGsp, offset, size, pBuf) kgspReadEmem_DISPATCH(pKernelGsp, offset, size, pBuf) +#define kgspConfigured(arg0) kgspConfigured_DISPATCH(arg0) +#define kgspPriRead(arg0, offset) kgspPriRead_DISPATCH(arg0, offset) +#define kgspRegWrite(pGpu, pKernelFlcn, offset, data) kgspRegWrite_DISPATCH(pGpu, pKernelFlcn, offset, data) +#define kgspMaskDmemAddr(pGpu, pKernelFlcn, addr) kgspMaskDmemAddr_DISPATCH(pGpu, pKernelFlcn, addr) #define kgspStateDestroy(pGpu, pEngstate) kgspStateDestroy_DISPATCH(pGpu, pEngstate) -#define kgspFreeTunableState(pGpu, pEngstate, pTunableState) kgspFreeTunableState_DISPATCH(pGpu, pEngstate, pTunableState) -#define kgspCompareTunableState(pGpu, pEngstate, pTunables1, pTunables2) kgspCompareTunableState_DISPATCH(pGpu, pEngstate, pTunables1, pTunables2) +#define kgspVprintf(arg0, bReportStart, fmt, args) kgspVprintf_DISPATCH(arg0, bReportStart, fmt, args) #define kgspClearInterrupt(pGpu, pIntrService, pParams) kgspClearInterrupt_DISPATCH(pGpu, pIntrService, pParams) +#define kgspPriWrite(arg0, offset, data) kgspPriWrite_DISPATCH(arg0, offset, data) +#define kgspMapBufferDescriptor(arg0, pBufDesc) kgspMapBufferDescriptor_DISPATCH(arg0, pBufDesc) +#define kgspSyncBufferDescriptor(arg0, pBufDesc, offset, size) kgspSyncBufferDescriptor_DISPATCH(arg0, pBufDesc, offset, size) +#define kgspRegRead(pGpu, pKernelFlcn, offset) kgspRegRead_DISPATCH(pGpu, pKernelFlcn, offset) #define kgspIsPresent(pGpu, pEngstate) kgspIsPresent_DISPATCH(pGpu, pEngstate) -#define kgspReconcileTunableState(pGpu, pEngstate, pTunableState) kgspReconcileTunableState_DISPATCH(pGpu, pEngstate, pTunableState) #define kgspStateLoad(pGpu, pEngstate, arg0) kgspStateLoad_DISPATCH(pGpu, pEngstate, arg0) +#define kgspGetScratchOffsets(arg0, scratchGroupId) kgspGetScratchOffsets_DISPATCH(arg0, scratchGroupId) +#define kgspUnload(arg0) kgspUnload_DISPATCH(arg0) #define kgspStateUnload(pGpu, pEngstate, arg0) kgspStateUnload_DISPATCH(pGpu, pEngstate, arg0) #define kgspServiceNotificationInterrupt(pGpu, pIntrService, pParams) kgspServiceNotificationInterrupt_DISPATCH(pGpu, pIntrService, pParams) +#define kgspGetWFL0Offset(arg0) kgspGetWFL0Offset_DISPATCH(arg0) #define kgspStateInitLocked(pGpu, pEngstate) kgspStateInitLocked_DISPATCH(pGpu, pEngstate) #define kgspStatePreLoad(pGpu, pEngstate, arg0) kgspStatePreLoad_DISPATCH(pGpu, pEngstate, arg0) #define kgspStatePostUnload(pGpu, pEngstate, arg0) kgspStatePostUnload_DISPATCH(pGpu, pEngstate, arg0) #define kgspStatePreUnload(pGpu, pEngstate, arg0) kgspStatePreUnload_DISPATCH(pGpu, pEngstate, arg0) -#define kgspGetTunableState(pGpu, pEngstate, pTunableState) kgspGetTunableState_DISPATCH(pGpu, pEngstate, pTunableState) #define kgspStateInitUnlocked(pGpu, pEngstate) kgspStateInitUnlocked_DISPATCH(pGpu, pEngstate) #define kgspInitMissing(pGpu, pEngstate) kgspInitMissing_DISPATCH(pGpu, pEngstate) #define kgspStatePreInitLocked(pGpu, pEngstate) kgspStatePreInitLocked_DISPATCH(pGpu, pEngstate) #define kgspStatePreInitUnlocked(pGpu, pEngstate) kgspStatePreInitUnlocked_DISPATCH(pGpu, pEngstate) #define kgspStatePostLoad(pGpu, pEngstate, arg0) kgspStatePostLoad_DISPATCH(pGpu, pEngstate, arg0) -#define kgspAllocTunableState(pGpu, pEngstate, ppTunableState) kgspAllocTunableState_DISPATCH(pGpu, pEngstate, ppTunableState) -#define kgspSetTunableState(pGpu, pEngstate, pTunableState) kgspSetTunableState_DISPATCH(pGpu, pEngstate, pTunableState) +#define kgspUnmapBufferDescriptor(arg0, pBufDesc) kgspUnmapBufferDescriptor_DISPATCH(arg0, pBufDesc) +#define kgspReadDmem(arg0, offset, size, pBuf) kgspReadDmem_DISPATCH(arg0, offset, size, pBuf) void kgspProgramLibosBootArgsAddr_TU102(struct OBJGPU *pGpu, struct KernelGsp *pKernelGsp); @@ -498,12 +548,13 @@ #define kgspSetCmdQueueHead_HAL(pGpu, pKernelGsp, queueIdx, value) kgspSetCmdQueueHead(pGpu, pKernelGsp, queueIdx, value) -void kgspHealthCheck_TU102(struct OBJGPU *pGpu, struct KernelGsp *pKernelGsp); +NvBool kgspHealthCheck_TU102(struct OBJGPU *pGpu, struct KernelGsp *pKernelGsp); #ifdef __nvoc_kernel_gsp_h_disabled -static inline void kgspHealthCheck(struct OBJGPU *pGpu, struct KernelGsp *pKernelGsp) { +static inline NvBool kgspHealthCheck(struct OBJGPU *pGpu, struct KernelGsp *pKernelGsp) { NV_ASSERT_FAILED_PRECOMP("KernelGsp was disabled!"); + return NV_FALSE; } #else //__nvoc_kernel_gsp_h_disabled #define kgspHealthCheck(pGpu, pKernelGsp) kgspHealthCheck_TU102(pGpu, pKernelGsp) @@ -539,15 +590,56 @@ #define kgspWaitForProcessorSuspend_HAL(pGpu, pKernelGsp) kgspWaitForProcessorSuspend(pGpu, pKernelGsp) +NV_STATUS kgspSavePowerMgmtState_TU102(struct OBJGPU *pGpu, struct KernelGsp *pKernelGsp); + + +#ifdef __nvoc_kernel_gsp_h_disabled +static inline NV_STATUS kgspSavePowerMgmtState(struct OBJGPU *pGpu, struct KernelGsp *pKernelGsp) { + NV_ASSERT_FAILED_PRECOMP("KernelGsp was disabled!"); + return NV_ERR_NOT_SUPPORTED; +} +#else //__nvoc_kernel_gsp_h_disabled +#define kgspSavePowerMgmtState(pGpu, pKernelGsp) kgspSavePowerMgmtState_TU102(pGpu, pKernelGsp) +#endif //__nvoc_kernel_gsp_h_disabled + +#define kgspSavePowerMgmtState_HAL(pGpu, pKernelGsp) kgspSavePowerMgmtState(pGpu, pKernelGsp) + +NV_STATUS kgspRestorePowerMgmtState_TU102(struct OBJGPU *pGpu, struct KernelGsp *pKernelGsp); + + +#ifdef __nvoc_kernel_gsp_h_disabled +static inline NV_STATUS kgspRestorePowerMgmtState(struct OBJGPU *pGpu, struct KernelGsp *pKernelGsp) { + NV_ASSERT_FAILED_PRECOMP("KernelGsp was disabled!"); + return NV_ERR_NOT_SUPPORTED; +} +#else //__nvoc_kernel_gsp_h_disabled +#define kgspRestorePowerMgmtState(pGpu, pKernelGsp) kgspRestorePowerMgmtState_TU102(pGpu, pKernelGsp) +#endif //__nvoc_kernel_gsp_h_disabled + +#define kgspRestorePowerMgmtState_HAL(pGpu, pKernelGsp) kgspRestorePowerMgmtState(pGpu, pKernelGsp) + +void kgspFreeSuspendResumeData_TU102(struct OBJGPU *pGpu, struct KernelGsp *pKernelGsp); + + +#ifdef __nvoc_kernel_gsp_h_disabled +static inline void kgspFreeSuspendResumeData(struct OBJGPU *pGpu, struct KernelGsp *pKernelGsp) { + NV_ASSERT_FAILED_PRECOMP("KernelGsp was disabled!"); +} +#else //__nvoc_kernel_gsp_h_disabled +#define kgspFreeSuspendResumeData(pGpu, pKernelGsp) kgspFreeSuspendResumeData_TU102(pGpu, pKernelGsp) +#endif //__nvoc_kernel_gsp_h_disabled + +#define kgspFreeSuspendResumeData_HAL(pGpu, pKernelGsp) kgspFreeSuspendResumeData(pGpu, pKernelGsp) + NV_STATUS kgspConstructEngine_IMPL(struct OBJGPU *pGpu, struct KernelGsp *pKernelGsp, ENGDESCRIPTOR arg0); static inline NV_STATUS kgspConstructEngine_DISPATCH(struct OBJGPU *pGpu, struct KernelGsp *pKernelGsp, ENGDESCRIPTOR arg0) { return pKernelGsp->__kgspConstructEngine__(pGpu, pKernelGsp, arg0); } -void kgspRegisterIntrService_IMPL(struct OBJGPU *pGpu, struct KernelGsp *pKernelGsp, IntrServiceRecord pRecords[163]); +void kgspRegisterIntrService_IMPL(struct OBJGPU *pGpu, struct KernelGsp *pKernelGsp, IntrServiceRecord pRecords[167]); -static inline void kgspRegisterIntrService_DISPATCH(struct OBJGPU *pGpu, struct KernelGsp *pKernelGsp, IntrServiceRecord pRecords[163]) { +static inline void kgspRegisterIntrService_DISPATCH(struct OBJGPU *pGpu, struct KernelGsp *pKernelGsp, IntrServiceRecord pRecords[167]) { pKernelGsp->__kgspRegisterIntrService__(pGpu, pKernelGsp, pRecords); } @@ -623,6 +715,26 @@ return pKernelGsp->__kgspGetBinArchiveGspRmBoot__(pKernelGsp); } +const BINDATA_ARCHIVE *kgspGetBinArchiveConcatenatedFMCDesc_GH100(struct KernelGsp *pKernelGsp); + +static inline const BINDATA_ARCHIVE *kgspGetBinArchiveConcatenatedFMCDesc_80f438(struct KernelGsp *pKernelGsp) { + NV_ASSERT_OR_RETURN_PRECOMP(0, ((void *)0)); +} + +static inline const BINDATA_ARCHIVE *kgspGetBinArchiveConcatenatedFMCDesc_DISPATCH(struct KernelGsp *pKernelGsp) { + return pKernelGsp->__kgspGetBinArchiveConcatenatedFMCDesc__(pKernelGsp); +} + +const BINDATA_ARCHIVE *kgspGetBinArchiveConcatenatedFMC_GH100(struct KernelGsp *pKernelGsp); + +static inline const BINDATA_ARCHIVE *kgspGetBinArchiveConcatenatedFMC_80f438(struct KernelGsp *pKernelGsp) { + NV_ASSERT_OR_RETURN_PRECOMP(0, ((void *)0)); +} + +static inline const BINDATA_ARCHIVE *kgspGetBinArchiveConcatenatedFMC_DISPATCH(struct KernelGsp *pKernelGsp) { + return pKernelGsp->__kgspGetBinArchiveConcatenatedFMC__(pKernelGsp); +} + const BINDATA_ARCHIVE *kgspGetBinArchiveGspRmFmcGfwDebugSigned_GH100(struct KernelGsp *pKernelGsp); static inline const BINDATA_ARCHIVE *kgspGetBinArchiveGspRmFmcGfwDebugSigned_80f438(struct KernelGsp *pKernelGsp) { @@ -643,6 +755,16 @@ return pKernelGsp->__kgspGetBinArchiveGspRmFmcGfwProdSigned__(pKernelGsp); } +const BINDATA_ARCHIVE *kgspGetBinArchiveGspRmCcFmcGfwProdSigned_GH100(struct KernelGsp *pKernelGsp); + +static inline const BINDATA_ARCHIVE *kgspGetBinArchiveGspRmCcFmcGfwProdSigned_80f438(struct KernelGsp *pKernelGsp) { + NV_ASSERT_OR_RETURN_PRECOMP(0, ((void *)0)); +} + +static inline const BINDATA_ARCHIVE *kgspGetBinArchiveGspRmCcFmcGfwProdSigned_DISPATCH(struct KernelGsp *pKernelGsp) { + return pKernelGsp->__kgspGetBinArchiveGspRmCcFmcGfwProdSigned__(pKernelGsp); +} + NV_STATUS kgspCalculateFbLayout_TU102(struct OBJGPU *pGpu, struct KernelGsp *pKernelGsp, GSP_FIRMWARE *pGspFw); NV_STATUS kgspCalculateFbLayout_GH100(struct OBJGPU *pGpu, struct KernelGsp *pKernelGsp, GSP_FIRMWARE *pGspFw); @@ -689,12 +811,6 @@ return pKernelGsp->__kgspResetHw__(pGpu, pKernelGsp); } -NvBool kgspIsEngineInReset_TU102(struct OBJGPU *pGpu, struct KernelGsp *pKernelGsp); - -static inline NvBool kgspIsEngineInReset_DISPATCH(struct OBJGPU *pGpu, struct KernelGsp *pKernelGsp) { - return pKernelGsp->__kgspIsEngineInReset__(pGpu, pKernelGsp); -} - NvBool kgspIsWpr2Up_TU102(struct OBJGPU *pGpu, struct KernelGsp *pKernelGsp); NvBool kgspIsWpr2Up_GH100(struct OBJGPU *pGpu, struct KernelGsp *pKernelGsp); @@ -717,8 +833,8 @@ return 256 * 1024 * 1024; } -static inline NvU64 kgspGetPrescrubbedTopFbSize_dd2c0b(struct OBJGPU *pGpu, struct KernelGsp *pKernelGsp) { - return (NvU64)(-1); +static inline NvU64 kgspGetPrescrubbedTopFbSize_604eb7(struct OBJGPU *pGpu, struct KernelGsp *pKernelGsp) { + return (+18446744073709551615ULL); } static inline NvU64 kgspGetPrescrubbedTopFbSize_DISPATCH(struct OBJGPU *pGpu, struct KernelGsp *pKernelGsp) { @@ -765,24 +881,24 @@ return pKernelGsp->__kgspExecuteScrubberIfNeeded__(pGpu, pKernelGsp); } -NV_STATUS kgspExecuteBooterLoad_TU102(struct OBJGPU *pGpu, struct KernelGsp *pKernelGsp, const NvU64 gspFwWprMetaOffset); +NV_STATUS kgspExecuteBooterLoad_TU102(struct OBJGPU *pGpu, struct KernelGsp *pKernelGsp, const NvU64 sysmemAddrOfData); -static inline NV_STATUS kgspExecuteBooterLoad_5baef9(struct OBJGPU *pGpu, struct KernelGsp *pKernelGsp, const NvU64 gspFwWprMetaOffset) { +static inline NV_STATUS kgspExecuteBooterLoad_5baef9(struct OBJGPU *pGpu, struct KernelGsp *pKernelGsp, const NvU64 sysmemAddrOfData) { NV_ASSERT_OR_RETURN_PRECOMP(0, NV_ERR_NOT_SUPPORTED); } -static inline NV_STATUS kgspExecuteBooterLoad_DISPATCH(struct OBJGPU *pGpu, struct KernelGsp *pKernelGsp, const NvU64 gspFwWprMetaOffset) { - return pKernelGsp->__kgspExecuteBooterLoad__(pGpu, pKernelGsp, gspFwWprMetaOffset); +static inline NV_STATUS kgspExecuteBooterLoad_DISPATCH(struct OBJGPU *pGpu, struct KernelGsp *pKernelGsp, const NvU64 sysmemAddrOfData) { + return pKernelGsp->__kgspExecuteBooterLoad__(pGpu, pKernelGsp, sysmemAddrOfData); } -NV_STATUS kgspExecuteBooterUnloadIfNeeded_TU102(struct OBJGPU *pGpu, struct KernelGsp *pKernelGsp); +NV_STATUS kgspExecuteBooterUnloadIfNeeded_TU102(struct OBJGPU *pGpu, struct KernelGsp *pKernelGsp, const NvU64 sysmemAddrOfSuspendResumeData); -static inline NV_STATUS kgspExecuteBooterUnloadIfNeeded_5baef9(struct OBJGPU *pGpu, struct KernelGsp *pKernelGsp) { +static inline NV_STATUS kgspExecuteBooterUnloadIfNeeded_5baef9(struct OBJGPU *pGpu, struct KernelGsp *pKernelGsp, const NvU64 sysmemAddrOfSuspendResumeData) { NV_ASSERT_OR_RETURN_PRECOMP(0, NV_ERR_NOT_SUPPORTED); } -static inline NV_STATUS kgspExecuteBooterUnloadIfNeeded_DISPATCH(struct OBJGPU *pGpu, struct KernelGsp *pKernelGsp) { - return pKernelGsp->__kgspExecuteBooterUnloadIfNeeded__(pGpu, pKernelGsp); +static inline NV_STATUS kgspExecuteBooterUnloadIfNeeded_DISPATCH(struct OBJGPU *pGpu, struct KernelGsp *pKernelGsp, const NvU64 sysmemAddrOfSuspendResumeData) { + return pKernelGsp->__kgspExecuteBooterUnloadIfNeeded__(pGpu, pKernelGsp, sysmemAddrOfSuspendResumeData); } NV_STATUS kgspExecuteHsFalcon_TU102(struct OBJGPU *pGpu, struct KernelGsp *pKernelGsp, KernelGspFlcnUcode *pFlcnUcode, struct KernelFalcon *pKernelFlcn, NvU32 *pMailbox0, NvU32 *pMailbox1); @@ -841,18 +957,28 @@ return pKernelGsp->__kgspGetBinArchiveBooterUnloadUcode__(pKernelGsp); } -static inline NvU64 kgspGetWprHeapSize_e3e8a1(struct OBJGPU *pGpu, struct KernelGsp *pKernelGsp) { - return 96 * 1024 * 1024; +static inline NvU64 kgspGetMinWprHeapSizeMB_7185bf(struct OBJGPU *pGpu, struct KernelGsp *pKernelGsp) { + return (64U); } -NvU64 kgspGetWprHeapSize_AD102(struct OBJGPU *pGpu, struct KernelGsp *pKernelGsp); +static inline NvU64 kgspGetMinWprHeapSizeMB_907c84(struct OBJGPU *pGpu, struct KernelGsp *pKernelGsp) { + return pGpu->bVgpuGspPluginOffloadEnabled ? (549U) : (84U); +} -static inline NvU64 kgspGetWprHeapSize_cffea5(struct OBJGPU *pGpu, struct KernelGsp *pKernelGsp) { - return 104 * 1024 * 1024; +static inline NvU64 kgspGetMinWprHeapSizeMB_DISPATCH(struct OBJGPU *pGpu, struct KernelGsp *pKernelGsp) { + return pKernelGsp->__kgspGetMinWprHeapSizeMB__(pGpu, pKernelGsp); } -static inline NvU64 kgspGetWprHeapSize_DISPATCH(struct OBJGPU *pGpu, struct KernelGsp *pKernelGsp) { - return pKernelGsp->__kgspGetWprHeapSize__(pGpu, pKernelGsp); +static inline NvU64 kgspGetMaxWprHeapSizeMB_ad4e6a(struct OBJGPU *pGpu, struct KernelGsp *pKernelGsp) { + return (256U); +} + +static inline NvU64 kgspGetMaxWprHeapSizeMB_5839e2(struct OBJGPU *pGpu, struct KernelGsp *pKernelGsp) { + return pGpu->bVgpuGspPluginOffloadEnabled ? (1024U) : (276U); +} + +static inline NvU64 kgspGetMaxWprHeapSizeMB_DISPATCH(struct OBJGPU *pGpu, struct KernelGsp *pKernelGsp) { + return pKernelGsp->__kgspGetMaxWprHeapSizeMB__(pGpu, pKernelGsp); } static inline NV_STATUS kgspInitVgpuPartitionLogging_395e98(struct OBJGPU *pGpu, struct KernelGsp *pKernelGsp, NvU32 gfid, NvU64 initTaskLogBUffOffset, NvU64 initTaskLogBUffSize, NvU64 vgpuTaskLogBUffOffset, NvU64 vgpuTaskLogBuffSize) { @@ -895,34 +1021,72 @@ return pKernelGsp->__kgspSetupGspFmcArgs__(pGpu, pKernelGsp, pGspFw); } -static inline void kgspStateDestroy_DISPATCH(POBJGPU pGpu, struct KernelGsp *pEngstate) { - pEngstate->__kgspStateDestroy__(pGpu, pEngstate); +void kgspReadEmem_TU102(struct KernelGsp *pKernelGsp, NvU64 offset, NvU64 size, void *pBuf); + +static inline void kgspReadEmem_DISPATCH(struct KernelGsp *pKernelGsp, NvU64 offset, NvU64 size, void *pBuf) { + pKernelGsp->__kgspReadEmem__(pKernelGsp, offset, size, pBuf); } -static inline void kgspFreeTunableState_DISPATCH(POBJGPU pGpu, struct KernelGsp *pEngstate, void *pTunableState) { - pEngstate->__kgspFreeTunableState__(pGpu, pEngstate, pTunableState); +static inline NvBool kgspConfigured_DISPATCH(struct KernelGsp *arg0) { + return arg0->__kgspConfigured__(arg0); } -static inline NV_STATUS kgspCompareTunableState_DISPATCH(POBJGPU pGpu, struct KernelGsp *pEngstate, void *pTunables1, void *pTunables2) { - return pEngstate->__kgspCompareTunableState__(pGpu, pEngstate, pTunables1, pTunables2); +static inline NvU32 kgspPriRead_DISPATCH(struct KernelGsp *arg0, NvU32 offset) { + return arg0->__kgspPriRead__(arg0, offset); +} + +static inline void kgspRegWrite_DISPATCH(struct OBJGPU *pGpu, struct KernelGsp *pKernelFlcn, NvU32 offset, NvU32 data) { + pKernelFlcn->__kgspRegWrite__(pGpu, pKernelFlcn, offset, data); +} + +static inline NvU32 kgspMaskDmemAddr_DISPATCH(struct OBJGPU *pGpu, struct KernelGsp *pKernelFlcn, NvU32 addr) { + return pKernelFlcn->__kgspMaskDmemAddr__(pGpu, pKernelFlcn, addr); +} + +static inline void kgspStateDestroy_DISPATCH(POBJGPU pGpu, struct KernelGsp *pEngstate) { + pEngstate->__kgspStateDestroy__(pGpu, pEngstate); +} + +static inline void kgspVprintf_DISPATCH(struct KernelGsp *arg0, NvBool bReportStart, const char *fmt, va_list args) { + arg0->__kgspVprintf__(arg0, bReportStart, fmt, args); } static inline NvBool kgspClearInterrupt_DISPATCH(struct OBJGPU *pGpu, struct KernelGsp *pIntrService, IntrServiceClearInterruptArguments *pParams) { return pIntrService->__kgspClearInterrupt__(pGpu, pIntrService, pParams); } -static inline NvBool kgspIsPresent_DISPATCH(POBJGPU pGpu, struct KernelGsp *pEngstate) { - return pEngstate->__kgspIsPresent__(pGpu, pEngstate); +static inline void kgspPriWrite_DISPATCH(struct KernelGsp *arg0, NvU32 offset, NvU32 data) { + arg0->__kgspPriWrite__(arg0, offset, data); +} + +static inline void *kgspMapBufferDescriptor_DISPATCH(struct KernelGsp *arg0, CrashCatBufferDescriptor *pBufDesc) { + return arg0->__kgspMapBufferDescriptor__(arg0, pBufDesc); +} + +static inline void kgspSyncBufferDescriptor_DISPATCH(struct KernelGsp *arg0, CrashCatBufferDescriptor *pBufDesc, NvU32 offset, NvU32 size) { + arg0->__kgspSyncBufferDescriptor__(arg0, pBufDesc, offset, size); } -static inline NV_STATUS kgspReconcileTunableState_DISPATCH(POBJGPU pGpu, struct KernelGsp *pEngstate, void *pTunableState) { - return pEngstate->__kgspReconcileTunableState__(pGpu, pEngstate, pTunableState); +static inline NvU32 kgspRegRead_DISPATCH(struct OBJGPU *pGpu, struct KernelGsp *pKernelFlcn, NvU32 offset) { + return pKernelFlcn->__kgspRegRead__(pGpu, pKernelFlcn, offset); +} + +static inline NvBool kgspIsPresent_DISPATCH(POBJGPU pGpu, struct KernelGsp *pEngstate) { + return pEngstate->__kgspIsPresent__(pGpu, pEngstate); } static inline NV_STATUS kgspStateLoad_DISPATCH(POBJGPU pGpu, struct KernelGsp *pEngstate, NvU32 arg0) { return pEngstate->__kgspStateLoad__(pGpu, pEngstate, arg0); } +static inline const NvU32 *kgspGetScratchOffsets_DISPATCH(struct KernelGsp *arg0, NV_CRASHCAT_SCRATCH_GROUP_ID scratchGroupId) { + return arg0->__kgspGetScratchOffsets__(arg0, scratchGroupId); +} + +static inline void kgspUnload_DISPATCH(struct KernelGsp *arg0) { + arg0->__kgspUnload__(arg0); +} + static inline NV_STATUS kgspStateUnload_DISPATCH(POBJGPU pGpu, struct KernelGsp *pEngstate, NvU32 arg0) { return pEngstate->__kgspStateUnload__(pGpu, pEngstate, arg0); } @@ -931,6 +1095,10 @@ return pIntrService->__kgspServiceNotificationInterrupt__(pGpu, pIntrService, pParams); } +static inline NvU32 kgspGetWFL0Offset_DISPATCH(struct KernelGsp *arg0) { + return arg0->__kgspGetWFL0Offset__(arg0); +} + static inline NV_STATUS kgspStateInitLocked_DISPATCH(POBJGPU pGpu, struct KernelGsp *pEngstate) { return pEngstate->__kgspStateInitLocked__(pGpu, pEngstate); } @@ -947,10 +1115,6 @@ return pEngstate->__kgspStatePreUnload__(pGpu, pEngstate, arg0); } -static inline NV_STATUS kgspGetTunableState_DISPATCH(POBJGPU pGpu, struct KernelGsp *pEngstate, void *pTunableState) { - return pEngstate->__kgspGetTunableState__(pGpu, pEngstate, pTunableState); -} - static inline NV_STATUS kgspStateInitUnlocked_DISPATCH(POBJGPU pGpu, struct KernelGsp *pEngstate) { return pEngstate->__kgspStateInitUnlocked__(pGpu, pEngstate); } @@ -971,12 +1135,12 @@ return pEngstate->__kgspStatePostLoad__(pGpu, pEngstate, arg0); } -static inline NV_STATUS kgspAllocTunableState_DISPATCH(POBJGPU pGpu, struct KernelGsp *pEngstate, void **ppTunableState) { - return pEngstate->__kgspAllocTunableState__(pGpu, pEngstate, ppTunableState); +static inline void kgspUnmapBufferDescriptor_DISPATCH(struct KernelGsp *arg0, CrashCatBufferDescriptor *pBufDesc) { + arg0->__kgspUnmapBufferDescriptor__(arg0, pBufDesc); } -static inline NV_STATUS kgspSetTunableState_DISPATCH(POBJGPU pGpu, struct KernelGsp *pEngstate, void *pTunableState) { - return pEngstate->__kgspSetTunableState__(pGpu, pEngstate, pTunableState); +static inline void kgspReadDmem_DISPATCH(struct KernelGsp *arg0, NvU32 offset, NvU32 size, void *pBuf) { + arg0->__kgspReadDmem__(arg0, offset, size, pBuf); } void kgspDestruct_IMPL(struct KernelGsp *pKernelGsp); @@ -1003,6 +1167,17 @@ #define kgspInitRm(pGpu, pKernelGsp, pGspFw) kgspInitRm_IMPL(pGpu, pKernelGsp, pGspFw) #endif //__nvoc_kernel_gsp_h_disabled +NV_STATUS kgspCreateRadix3_IMPL(struct OBJGPU *pGpu, struct KernelGsp *pKernelGsp, MEMORY_DESCRIPTOR **ppMemdescRadix3, MEMORY_DESCRIPTOR *pMemdescData, const void *pData, NvU64 sizeOfData); + +#ifdef __nvoc_kernel_gsp_h_disabled +static inline NV_STATUS kgspCreateRadix3(struct OBJGPU *pGpu, struct KernelGsp *pKernelGsp, MEMORY_DESCRIPTOR **ppMemdescRadix3, MEMORY_DESCRIPTOR *pMemdescData, const void *pData, NvU64 sizeOfData) { + NV_ASSERT_FAILED_PRECOMP("KernelGsp was disabled!"); + return NV_ERR_NOT_SUPPORTED; +} +#else //__nvoc_kernel_gsp_h_disabled +#define kgspCreateRadix3(pGpu, pKernelGsp, ppMemdescRadix3, pMemdescData, pData, sizeOfData) kgspCreateRadix3_IMPL(pGpu, pKernelGsp, ppMemdescRadix3, pMemdescData, pData, sizeOfData) +#endif //__nvoc_kernel_gsp_h_disabled + NV_STATUS kgspUnloadRm_IMPL(struct OBJGPU *pGpu, struct KernelGsp *pKernelGsp); #ifdef __nvoc_kernel_gsp_h_disabled @@ -1025,6 +1200,28 @@ #define kgspPrepareBootBinaryImage(pGpu, pKernelGsp) kgspPrepareBootBinaryImage_IMPL(pGpu, pKernelGsp) #endif //__nvoc_kernel_gsp_h_disabled +NvU64 kgspGetFwHeapSize_IMPL(struct OBJGPU *pGpu, struct KernelGsp *pKernelGsp, NvU64 posteriorFbSize); + +#ifdef __nvoc_kernel_gsp_h_disabled +static inline NvU64 kgspGetFwHeapSize(struct OBJGPU *pGpu, struct KernelGsp *pKernelGsp, NvU64 posteriorFbSize) { + NV_ASSERT_FAILED_PRECOMP("KernelGsp was disabled!"); + return 0; +} +#else //__nvoc_kernel_gsp_h_disabled +#define kgspGetFwHeapSize(pGpu, pKernelGsp, posteriorFbSize) kgspGetFwHeapSize_IMPL(pGpu, pKernelGsp, posteriorFbSize) +#endif //__nvoc_kernel_gsp_h_disabled + +NvU64 kgspGetWprEndMargin_IMPL(struct OBJGPU *pGpu, struct KernelGsp *pKernelGsp); + +#ifdef __nvoc_kernel_gsp_h_disabled +static inline NvU64 kgspGetWprEndMargin(struct OBJGPU *pGpu, struct KernelGsp *pKernelGsp) { + NV_ASSERT_FAILED_PRECOMP("KernelGsp was disabled!"); + return 0; +} +#else //__nvoc_kernel_gsp_h_disabled +#define kgspGetWprEndMargin(pGpu, pKernelGsp) kgspGetWprEndMargin_IMPL(pGpu, pKernelGsp) +#endif //__nvoc_kernel_gsp_h_disabled + void kgspSetupLibosInitArgs_IMPL(struct OBJGPU *pGpu, struct KernelGsp *pKernelGsp); #ifdef __nvoc_kernel_gsp_h_disabled @@ -1056,17 +1253,6 @@ #define kgspWaitForRmInitDone(pGpu, pKernelGsp) kgspWaitForRmInitDone_IMPL(pGpu, pKernelGsp) #endif //__nvoc_kernel_gsp_h_disabled -NV_STATUS kgspInitLogging_IMPL(struct OBJGPU *pGpu, struct KernelGsp *pKernelGsp, GSP_FIRMWARE *pGspFw); - -#ifdef __nvoc_kernel_gsp_h_disabled -static inline NV_STATUS kgspInitLogging(struct OBJGPU *pGpu, struct KernelGsp *pKernelGsp, GSP_FIRMWARE *pGspFw) { - NV_ASSERT_FAILED_PRECOMP("KernelGsp was disabled!"); - return NV_ERR_NOT_SUPPORTED; -} -#else //__nvoc_kernel_gsp_h_disabled -#define kgspInitLogging(pGpu, pKernelGsp, pGspFw) kgspInitLogging_IMPL(pGpu, pKernelGsp, pGspFw) -#endif //__nvoc_kernel_gsp_h_disabled - NV_STATUS kgspStartLogPolling_IMPL(struct OBJGPU *pGpu, struct KernelGsp *pKernelGsp); #ifdef __nvoc_kernel_gsp_h_disabled @@ -1109,15 +1295,15 @@ #define kgspExecuteSequencerBuffer(pGpu, pKernelGsp, pRunCpuSeqParams) kgspExecuteSequencerBuffer_IMPL(pGpu, pKernelGsp, pRunCpuSeqParams) #endif //__nvoc_kernel_gsp_h_disabled -NV_STATUS kgspParseFwsecUcodeFromVbiosImg_IMPL(struct OBJGPU *pGpu, struct KernelGsp *pKernelGsp, const KernelGspVbiosImg *const pVbiosImg, KernelGspFlcnUcode **ppFwsecUcode); +NV_STATUS kgspParseFwsecUcodeFromVbiosImg_IMPL(struct OBJGPU *pGpu, struct KernelGsp *pKernelGsp, const KernelGspVbiosImg *const pVbiosImg, KernelGspFlcnUcode **ppFwsecUcode, NvU64 *pVbiosVersionCombined); #ifdef __nvoc_kernel_gsp_h_disabled -static inline NV_STATUS kgspParseFwsecUcodeFromVbiosImg(struct OBJGPU *pGpu, struct KernelGsp *pKernelGsp, const KernelGspVbiosImg *const pVbiosImg, KernelGspFlcnUcode **ppFwsecUcode) { +static inline NV_STATUS kgspParseFwsecUcodeFromVbiosImg(struct OBJGPU *pGpu, struct KernelGsp *pKernelGsp, const KernelGspVbiosImg *const pVbiosImg, KernelGspFlcnUcode **ppFwsecUcode, NvU64 *pVbiosVersionCombined) { NV_ASSERT_FAILED_PRECOMP("KernelGsp was disabled!"); return NV_ERR_NOT_SUPPORTED; } #else //__nvoc_kernel_gsp_h_disabled -#define kgspParseFwsecUcodeFromVbiosImg(pGpu, pKernelGsp, pVbiosImg, ppFwsecUcode) kgspParseFwsecUcodeFromVbiosImg_IMPL(pGpu, pKernelGsp, pVbiosImg, ppFwsecUcode) +#define kgspParseFwsecUcodeFromVbiosImg(pGpu, pKernelGsp, pVbiosImg, ppFwsecUcode, pVbiosVersionCombined) kgspParseFwsecUcodeFromVbiosImg_IMPL(pGpu, pKernelGsp, pVbiosImg, ppFwsecUcode, pVbiosVersionCombined) #endif //__nvoc_kernel_gsp_h_disabled NV_STATUS kgspAllocateScrubberUcodeImage_IMPL(struct OBJGPU *pGpu, struct KernelGsp *pKernelGsp, KernelGspFlcnUcode **ppScrubberUcode); @@ -1159,7 +1345,7 @@ NV_STATUS rpcRmApiControl_GSP(RM_API *pRmApi, NvHandle hClient, NvHandle hObject, NvU32 cmd, void *pParamStructPtr, NvU32 paramsSize); NV_STATUS rpcRmApiAlloc_GSP(RM_API *pRmApi, NvHandle hClient, NvHandle hParent, - NvHandle hObject, NvU32 hClass, void *pAllocParams); + NvHandle hObject, NvU32 hClass, void *pAllocParams, NvU32 allocParamsSize); NV_STATUS rpcRmApiDupObject_GSP(RM_API *pRmApi, NvHandle hClient, NvHandle hParent, NvHandle *phObject, NvHandle hClientSrc, NvHandle hObjectSrc, NvU32 flags); NV_STATUS rpcRmApiFree_GSP(RM_API *pRmApi, NvHandle hClient, NvHandle hObject); @@ -1169,6 +1355,8 @@ /* Free a KernelGspFlcnUcode structure */ void kgspFreeFlcnUcode(KernelGspFlcnUcode *pFlcnUcode); +void kgspLogRpcDebugInfo(struct OBJGPU *pGpu, OBJRPC *pRpc, NvU32 errorNum, NvBool bPollingForRpcResponse); + #endif // KERNEL_GSP_H #ifdef __cplusplus diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/generated/g_kernel_head_nvoc.c nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_kernel_head_nvoc.c --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/generated/g_kernel_head_nvoc.c 2023-10-25 20:27:08.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_kernel_head_nvoc.c 2024-03-05 22:18:29.000000000 +0000 @@ -74,12 +74,16 @@ const unsigned long rmVariantHal_HalVarIdx = (unsigned long)rmVariantHal->__nvoc_HalVarIdx; ChipHal *chipHal = &pRmhalspecowner->chipHal; const unsigned long chipHal_HalVarIdx = (unsigned long)chipHal->__nvoc_HalVarIdx; + DispIpHal *dispIpHal = &pRmhalspecowner->dispIpHal; + const unsigned long dispIpHal_HalVarIdx = (unsigned long)dispIpHal->__nvoc_HalVarIdx; PORT_UNREFERENCED_VARIABLE(pThis); PORT_UNREFERENCED_VARIABLE(pRmhalspecowner); PORT_UNREFERENCED_VARIABLE(rmVariantHal); PORT_UNREFERENCED_VARIABLE(rmVariantHal_HalVarIdx); PORT_UNREFERENCED_VARIABLE(chipHal); PORT_UNREFERENCED_VARIABLE(chipHal_HalVarIdx); + PORT_UNREFERENCED_VARIABLE(dispIpHal); + PORT_UNREFERENCED_VARIABLE(dispIpHal_HalVarIdx); } NV_STATUS __nvoc_ctor_Object(Object* ); @@ -106,63 +110,93 @@ const unsigned long rmVariantHal_HalVarIdx = (unsigned long)rmVariantHal->__nvoc_HalVarIdx; ChipHal *chipHal = &pRmhalspecowner->chipHal; const unsigned long chipHal_HalVarIdx = (unsigned long)chipHal->__nvoc_HalVarIdx; + DispIpHal *dispIpHal = &pRmhalspecowner->dispIpHal; + const unsigned long dispIpHal_HalVarIdx = (unsigned long)dispIpHal->__nvoc_HalVarIdx; PORT_UNREFERENCED_VARIABLE(pThis); PORT_UNREFERENCED_VARIABLE(pRmhalspecowner); PORT_UNREFERENCED_VARIABLE(rmVariantHal); PORT_UNREFERENCED_VARIABLE(rmVariantHal_HalVarIdx); PORT_UNREFERENCED_VARIABLE(chipHal); PORT_UNREFERENCED_VARIABLE(chipHal_HalVarIdx); + PORT_UNREFERENCED_VARIABLE(dispIpHal); + PORT_UNREFERENCED_VARIABLE(dispIpHal_HalVarIdx); + + // Hal function -- kheadReadVblankIntrEnable + if (((( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x000003e0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 */ && (( ((dispIpHal_HalVarIdx >> 5) == 0UL) && ((1UL << (dispIpHal_HalVarIdx & 0x1f)) & 0x00000400UL) )) /* DispIpHal: DISPv0400 */ ) || + ((( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0000f800UL) )) /* ChipHal: GA102 | GA103 | GA104 | GA106 | GA107 */ && (( ((dispIpHal_HalVarIdx >> 5) == 0UL) && ((1UL << (dispIpHal_HalVarIdx & 0x1f)) & 0x00000800UL) )) /* DispIpHal: DISPv0401 */ ) || + ((( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x01f00000UL) )) /* ChipHal: AD102 | AD103 | AD104 | AD106 | AD107 */ && (( ((dispIpHal_HalVarIdx >> 5) == 0UL) && ((1UL << (dispIpHal_HalVarIdx & 0x1f)) & 0x00004000UL) )) /* DispIpHal: DISPv0404 */ )) + { + pThis->__kheadReadVblankIntrEnable__ = &kheadReadVblankIntrEnable_KERNEL; + } + // default + else + { + pThis->__kheadReadVblankIntrEnable__ = &kheadReadVblankIntrEnable_108313; + } + + // Hal function -- kheadGetDisplayInitialized + if (((( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x000003e0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 */ && (( ((dispIpHal_HalVarIdx >> 5) == 0UL) && ((1UL << (dispIpHal_HalVarIdx & 0x1f)) & 0x00000400UL) )) /* DispIpHal: DISPv0400 */ ) || + ((( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0000f800UL) )) /* ChipHal: GA102 | GA103 | GA104 | GA106 | GA107 */ && (( ((dispIpHal_HalVarIdx >> 5) == 0UL) && ((1UL << (dispIpHal_HalVarIdx & 0x1f)) & 0x00000800UL) )) /* DispIpHal: DISPv0401 */ ) || + ((( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x01f00000UL) )) /* ChipHal: AD102 | AD103 | AD104 | AD106 | AD107 */ && (( ((dispIpHal_HalVarIdx >> 5) == 0UL) && ((1UL << (dispIpHal_HalVarIdx & 0x1f)) & 0x00004000UL) )) /* DispIpHal: DISPv0404 */ )) + { + pThis->__kheadGetDisplayInitialized__ = &kheadGetDisplayInitialized_KERNEL; + } + // default + else + { + pThis->__kheadGetDisplayInitialized__ = &kheadGetDisplayInitialized_108313; + } + + // Hal function -- kheadWriteVblankIntrEnable + if (((( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x000003e0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 */ && (( ((dispIpHal_HalVarIdx >> 5) == 0UL) && ((1UL << (dispIpHal_HalVarIdx & 0x1f)) & 0x00000400UL) )) /* DispIpHal: DISPv0400 */ ) || + ((( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0000f800UL) )) /* ChipHal: GA102 | GA103 | GA104 | GA106 | GA107 */ && (( ((dispIpHal_HalVarIdx >> 5) == 0UL) && ((1UL << (dispIpHal_HalVarIdx & 0x1f)) & 0x00000800UL) )) /* DispIpHal: DISPv0401 */ ) || + ((( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x01f00000UL) )) /* ChipHal: AD102 | AD103 | AD104 | AD106 | AD107 */ && (( ((dispIpHal_HalVarIdx >> 5) == 0UL) && ((1UL << (dispIpHal_HalVarIdx & 0x1f)) & 0x00004000UL) )) /* DispIpHal: DISPv0404 */ )) + { + pThis->__kheadWriteVblankIntrEnable__ = &kheadWriteVblankIntrEnable_KERNEL; + } + // default + else + { + pThis->__kheadWriteVblankIntrEnable__ = &kheadWriteVblankIntrEnable_e426af; + } // Hal function -- kheadProcessVblankCallbacks - if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000002UL) )) /* RmVariantHal: PF_KERNEL_ONLY */ + if (((( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x000003e0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 */ && (( ((dispIpHal_HalVarIdx >> 5) == 0UL) && ((1UL << (dispIpHal_HalVarIdx & 0x1f)) & 0x00000400UL) )) /* DispIpHal: DISPv0400 */ ) || + ((( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0000f800UL) )) /* ChipHal: GA102 | GA103 | GA104 | GA106 | GA107 */ && (( ((dispIpHal_HalVarIdx >> 5) == 0UL) && ((1UL << (dispIpHal_HalVarIdx & 0x1f)) & 0x00000800UL) )) /* DispIpHal: DISPv0401 */ ) || + ((( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x01f00000UL) )) /* ChipHal: AD102 | AD103 | AD104 | AD106 | AD107 */ && (( ((dispIpHal_HalVarIdx >> 5) == 0UL) && ((1UL << (dispIpHal_HalVarIdx & 0x1f)) & 0x00004000UL) )) /* DispIpHal: DISPv0404 */ )) + { + pThis->__kheadProcessVblankCallbacks__ = &kheadProcessVblankCallbacks_IMPL; + } + // default + else { - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x01f0fbe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 */ - { - pThis->__kheadProcessVblankCallbacks__ = &kheadProcessVblankCallbacks_IMPL; - } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000400UL) )) /* ChipHal: GA100 | GH100 */ - { - pThis->__kheadProcessVblankCallbacks__ = &kheadProcessVblankCallbacks_e426af; - } + pThis->__kheadProcessVblankCallbacks__ = &kheadProcessVblankCallbacks_e426af; } // Hal function -- kheadResetPendingVblank - if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000002UL) )) /* RmVariantHal: PF_KERNEL_ONLY */ + if (((( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x000003e0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 */ && (( ((dispIpHal_HalVarIdx >> 5) == 0UL) && ((1UL << (dispIpHal_HalVarIdx & 0x1f)) & 0x00000400UL) )) /* DispIpHal: DISPv0400 */ ) || + ((( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0000f800UL) )) /* ChipHal: GA102 | GA103 | GA104 | GA106 | GA107 */ && (( ((dispIpHal_HalVarIdx >> 5) == 0UL) && ((1UL << (dispIpHal_HalVarIdx & 0x1f)) & 0x00000800UL) )) /* DispIpHal: DISPv0401 */ ) || + ((( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x01f00000UL) )) /* ChipHal: AD102 | AD103 | AD104 | AD106 | AD107 */ && (( ((dispIpHal_HalVarIdx >> 5) == 0UL) && ((1UL << (dispIpHal_HalVarIdx & 0x1f)) & 0x00004000UL) )) /* DispIpHal: DISPv0404 */ )) + { + pThis->__kheadResetPendingVblank__ = &kheadResetPendingVblank_KERNEL; + } + // default + else { - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x01f0fbe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 */ - { - pThis->__kheadResetPendingVblank__ = &kheadResetPendingVblank_v04_00_KERNEL; - } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000400UL) )) /* ChipHal: GA100 | GH100 */ - { - pThis->__kheadResetPendingVblank__ = &kheadResetPendingVblank_e426af; - } - } - - // Hal function -- kheadResetPendingVblankForKernel - if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000002UL) )) /* RmVariantHal: PF_KERNEL_ONLY */ - { - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x01f0fbe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 */ - { - pThis->__kheadResetPendingVblankForKernel__ = &kheadResetPendingVblankForKernel_8305c4; - } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000400UL) )) /* ChipHal: GA100 | GH100 */ - { - pThis->__kheadResetPendingVblankForKernel__ = &kheadResetPendingVblankForKernel_e426af; - } + pThis->__kheadResetPendingVblank__ = &kheadResetPendingVblank_e426af; } // Hal function -- kheadReadPendingVblank - if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000002UL) )) /* RmVariantHal: PF_KERNEL_ONLY */ + if (((( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x000003e0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 */ && (( ((dispIpHal_HalVarIdx >> 5) == 0UL) && ((1UL << (dispIpHal_HalVarIdx & 0x1f)) & 0x00000400UL) )) /* DispIpHal: DISPv0400 */ ) || + ((( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0000f800UL) )) /* ChipHal: GA102 | GA103 | GA104 | GA106 | GA107 */ && (( ((dispIpHal_HalVarIdx >> 5) == 0UL) && ((1UL << (dispIpHal_HalVarIdx & 0x1f)) & 0x00000800UL) )) /* DispIpHal: DISPv0401 */ ) || + ((( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x01f00000UL) )) /* ChipHal: AD102 | AD103 | AD104 | AD106 | AD107 */ && (( ((dispIpHal_HalVarIdx >> 5) == 0UL) && ((1UL << (dispIpHal_HalVarIdx & 0x1f)) & 0x00004000UL) )) /* DispIpHal: DISPv0404 */ )) { - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x01f0fbe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 */ - { - pThis->__kheadReadPendingVblank__ = &kheadReadPendingVblank_v04_00_KERNEL; - } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000400UL) )) /* ChipHal: GA100 | GH100 */ - { - pThis->__kheadReadPendingVblank__ = &kheadReadPendingVblank_92bfc3; - } + pThis->__kheadReadPendingVblank__ = &kheadReadPendingVblank_KERNEL; + } + // default + else + { + pThis->__kheadReadPendingVblank__ = &kheadReadPendingVblank_108313; } } @@ -184,13 +218,16 @@ KernelHead *pThis; RmHalspecOwner *pRmhalspecowner; - pThis = portMemAllocNonPaged(sizeof(KernelHead)); - if (pThis == NULL) return NV_ERR_NO_MEMORY; + status = __nvoc_handleObjCreateMemAlloc(createFlags, sizeof(KernelHead), (void**)&pThis, (void**)ppThis); + if (status != NV_OK) + return status; portMemSet(pThis, 0, sizeof(KernelHead)); __nvoc_initRtti(staticCast(pThis, Dynamic), &__nvoc_class_def_KernelHead); + pThis->__nvoc_base_Object.createFlags = createFlags; + if (pParent != NULL && !(createFlags & NVOC_OBJ_CREATE_FLAGS_PARENT_HALSPEC_ONLY)) { pParentObj = dynamicCast(pParent, Object); @@ -210,11 +247,17 @@ if (status != NV_OK) goto __nvoc_objCreate_KernelHead_cleanup; *ppThis = pThis; + return NV_OK; __nvoc_objCreate_KernelHead_cleanup: // do not call destructors here since the constructor already called them - portMemFree(pThis); + if (createFlags & NVOC_OBJ_CREATE_FLAGS_IN_PLACE_CONSTRUCT) + portMemSet(pThis, 0, sizeof(KernelHead)); + else + portMemFree(pThis); + + // coverity[leaked_storage:FALSE] return status; } diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/generated/g_kernel_head_nvoc.h nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_kernel_head_nvoc.h --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/generated/g_kernel_head_nvoc.h 2023-10-25 20:27:09.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_kernel_head_nvoc.h 2024-03-05 22:18:29.000000000 +0000 @@ -7,7 +7,7 @@ #endif /* - * SPDX-FileCopyrightText: Copyright (c) 2021 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2021-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -41,15 +41,10 @@ #define KERNEL_HEAD_H /* ------------------------ Includes --------------------------------------- */ +#include "gpu/eng_state.h" #include "gpu/disp/vblank_callback/vblank.h" #include "gpu/gpu_halspec.h" /* ------------------------ Types definitions ------------------------------ */ -enum -{ - headIntr_none = 0, - headIntr_vblank = NVBIT(0), -}; - /* ------------------------ Macros & Defines ------------------------------- */ #ifdef NVOC_KERNEL_HEAD_H_PRIVATE_ACCESS_ALLOWED @@ -76,10 +71,12 @@ struct Object __nvoc_base_Object; struct Object *__nvoc_pbase_Object; struct KernelHead *__nvoc_pbase_KernelHead; + NvBool (*__kheadReadVblankIntrEnable__)(struct OBJGPU *, struct KernelHead *); + NvBool (*__kheadGetDisplayInitialized__)(struct OBJGPU *, struct KernelHead *); + void (*__kheadWriteVblankIntrEnable__)(struct OBJGPU *, struct KernelHead *, NvBool); void (*__kheadProcessVblankCallbacks__)(struct OBJGPU *, struct KernelHead *, NvU32); void (*__kheadResetPendingVblank__)(struct OBJGPU *, struct KernelHead *, THREAD_STATE_NODE *); - void (*__kheadResetPendingVblankForKernel__)(struct OBJGPU *, struct KernelHead *, THREAD_STATE_NODE *); - NvU32 (*__kheadReadPendingVblank__)(struct OBJGPU *, struct KernelHead *, NvU32); + NvBool (*__kheadReadPendingVblank__)(struct OBJGPU *, struct KernelHead *, NvU32 *, THREAD_STATE_NODE *); struct __nvoc_inner_struc_KernelHead_1__ Vblank; NvU32 PublicId; }; @@ -112,14 +109,18 @@ #define __objCreate_KernelHead(ppNewObj, pParent, createFlags) \ __nvoc_objCreate_KernelHead((ppNewObj), staticCast((pParent), Dynamic), (createFlags)) +#define kheadReadVblankIntrEnable(pGpu, pKernelHead) kheadReadVblankIntrEnable_DISPATCH(pGpu, pKernelHead) +#define kheadReadVblankIntrEnable_HAL(pGpu, pKernelHead) kheadReadVblankIntrEnable_DISPATCH(pGpu, pKernelHead) +#define kheadGetDisplayInitialized(pGpu, pKernelHead) kheadGetDisplayInitialized_DISPATCH(pGpu, pKernelHead) +#define kheadGetDisplayInitialized_HAL(pGpu, pKernelHead) kheadGetDisplayInitialized_DISPATCH(pGpu, pKernelHead) +#define kheadWriteVblankIntrEnable(pGpu, pKernelHead, arg0) kheadWriteVblankIntrEnable_DISPATCH(pGpu, pKernelHead, arg0) +#define kheadWriteVblankIntrEnable_HAL(pGpu, pKernelHead, arg0) kheadWriteVblankIntrEnable_DISPATCH(pGpu, pKernelHead, arg0) #define kheadProcessVblankCallbacks(pGpu, pKernelHead, arg0) kheadProcessVblankCallbacks_DISPATCH(pGpu, pKernelHead, arg0) #define kheadProcessVblankCallbacks_HAL(pGpu, pKernelHead, arg0) kheadProcessVblankCallbacks_DISPATCH(pGpu, pKernelHead, arg0) #define kheadResetPendingVblank(pGpu, pKernelHead, arg0) kheadResetPendingVblank_DISPATCH(pGpu, pKernelHead, arg0) #define kheadResetPendingVblank_HAL(pGpu, pKernelHead, arg0) kheadResetPendingVblank_DISPATCH(pGpu, pKernelHead, arg0) -#define kheadResetPendingVblankForKernel(pGpu, pKernelHead, pThreadState) kheadResetPendingVblankForKernel_DISPATCH(pGpu, pKernelHead, pThreadState) -#define kheadResetPendingVblankForKernel_HAL(pGpu, pKernelHead, pThreadState) kheadResetPendingVblankForKernel_DISPATCH(pGpu, pKernelHead, pThreadState) -#define kheadReadPendingVblank(pGpu, pKernelHead, intr) kheadReadPendingVblank_DISPATCH(pGpu, pKernelHead, intr) -#define kheadReadPendingVblank_HAL(pGpu, pKernelHead, intr) kheadReadPendingVblank_DISPATCH(pGpu, pKernelHead, intr) +#define kheadReadPendingVblank(pGpu, pKernelHead, pCachedIntr, pThreadState) kheadReadPendingVblank_DISPATCH(pGpu, pKernelHead, pCachedIntr, pThreadState) +#define kheadReadPendingVblank_HAL(pGpu, pKernelHead, pCachedIntr, pThreadState) kheadReadPendingVblank_DISPATCH(pGpu, pKernelHead, pCachedIntr, pThreadState) NvU32 kheadGetVblankTotalCounter_IMPL(struct KernelHead *pKernelHead); @@ -205,52 +206,45 @@ #define kheadSetVblankNormLatencyCounter_HAL(pKernelHead, arg0) kheadSetVblankNormLatencyCounter(pKernelHead, arg0) -static inline NvBool kheadReadVblankIntrEnable_491d52(struct OBJGPU *pGpu, struct KernelHead *pKernelHead) { - return ((NvBool)(0 != 0)); -} - +NvBool kheadReadVblankIntrEnable_KERNEL(struct OBJGPU *pGpu, struct KernelHead *pKernelHead); -#ifdef __nvoc_kernel_head_h_disabled -static inline NvBool kheadReadVblankIntrEnable(struct OBJGPU *pGpu, struct KernelHead *pKernelHead) { - NV_ASSERT_FAILED_PRECOMP("KernelHead was disabled!"); - return NV_FALSE; +static inline NvBool kheadReadVblankIntrEnable_108313(struct OBJGPU *pGpu, struct KernelHead *pKernelHead) { + NV_ASSERT_OR_RETURN_PRECOMP(0, ((NvBool)(0 != 0))); } -#else //__nvoc_kernel_head_h_disabled -#define kheadReadVblankIntrEnable(pGpu, pKernelHead) kheadReadVblankIntrEnable_491d52(pGpu, pKernelHead) -#endif //__nvoc_kernel_head_h_disabled -#define kheadReadVblankIntrEnable_HAL(pGpu, pKernelHead) kheadReadVblankIntrEnable(pGpu, pKernelHead) +NvBool kheadReadVblankIntrEnable_v03_00(struct OBJGPU *pGpu, struct KernelHead *pKernelHead); -static inline NvBool kheadGetDisplayInitialized_491d52(struct OBJGPU *pGpu, struct KernelHead *pKernelHead) { +static inline NvBool kheadReadVblankIntrEnable_ceaee8(struct OBJGPU *pGpu, struct KernelHead *pKernelHead) { + NV_ASSERT_PRECOMP(0); return ((NvBool)(0 != 0)); } +static inline NvBool kheadReadVblankIntrEnable_DISPATCH(struct OBJGPU *pGpu, struct KernelHead *pKernelHead) { + return pKernelHead->__kheadReadVblankIntrEnable__(pGpu, pKernelHead); +} -#ifdef __nvoc_kernel_head_h_disabled -static inline NvBool kheadGetDisplayInitialized(struct OBJGPU *pGpu, struct KernelHead *pKernelHead) { - NV_ASSERT_FAILED_PRECOMP("KernelHead was disabled!"); - return NV_FALSE; +NvBool kheadGetDisplayInitialized_KERNEL(struct OBJGPU *pGpu, struct KernelHead *pKernelHead); + +static inline NvBool kheadGetDisplayInitialized_108313(struct OBJGPU *pGpu, struct KernelHead *pKernelHead) { + NV_ASSERT_OR_RETURN_PRECOMP(0, ((NvBool)(0 != 0))); +} + +static inline NvBool kheadGetDisplayInitialized_DISPATCH(struct OBJGPU *pGpu, struct KernelHead *pKernelHead) { + return pKernelHead->__kheadGetDisplayInitialized__(pGpu, pKernelHead); } -#else //__nvoc_kernel_head_h_disabled -#define kheadGetDisplayInitialized(pGpu, pKernelHead) kheadGetDisplayInitialized_491d52(pGpu, pKernelHead) -#endif //__nvoc_kernel_head_h_disabled -#define kheadGetDisplayInitialized_HAL(pGpu, pKernelHead) kheadGetDisplayInitialized(pGpu, pKernelHead) +void kheadWriteVblankIntrEnable_KERNEL(struct OBJGPU *pGpu, struct KernelHead *pKernelHead, NvBool arg0); -static inline void kheadWriteVblankIntrEnable_b3696a(struct OBJGPU *pGpu, struct KernelHead *pKernelHead, NvBool arg0) { +static inline void kheadWriteVblankIntrEnable_e426af(struct OBJGPU *pGpu, struct KernelHead *pKernelHead, NvBool arg0) { + NV_ASSERT_PRECOMP(0); return; } +void kheadWriteVblankIntrEnable_v03_00(struct OBJGPU *pGpu, struct KernelHead *pKernelHead, NvBool arg0); -#ifdef __nvoc_kernel_head_h_disabled -static inline void kheadWriteVblankIntrEnable(struct OBJGPU *pGpu, struct KernelHead *pKernelHead, NvBool arg0) { - NV_ASSERT_FAILED_PRECOMP("KernelHead was disabled!"); +static inline void kheadWriteVblankIntrEnable_DISPATCH(struct OBJGPU *pGpu, struct KernelHead *pKernelHead, NvBool arg0) { + pKernelHead->__kheadWriteVblankIntrEnable__(pGpu, pKernelHead, arg0); } -#else //__nvoc_kernel_head_h_disabled -#define kheadWriteVblankIntrEnable(pGpu, pKernelHead, arg0) kheadWriteVblankIntrEnable_b3696a(pGpu, pKernelHead, arg0) -#endif //__nvoc_kernel_head_h_disabled - -#define kheadWriteVblankIntrEnable_HAL(pGpu, pKernelHead, arg0) kheadWriteVblankIntrEnable(pGpu, pKernelHead, arg0) void kheadProcessVblankCallbacks_IMPL(struct OBJGPU *pGpu, struct KernelHead *pKernelHead, NvU32 arg0); @@ -263,39 +257,40 @@ pKernelHead->__kheadProcessVblankCallbacks__(pGpu, pKernelHead, arg0); } -void kheadResetPendingVblank_v04_00_KERNEL(struct OBJGPU *pGpu, struct KernelHead *pKernelHead, THREAD_STATE_NODE *arg0); +void kheadResetPendingVblank_KERNEL(struct OBJGPU *pGpu, struct KernelHead *pKernelHead, THREAD_STATE_NODE *arg0); static inline void kheadResetPendingVblank_e426af(struct OBJGPU *pGpu, struct KernelHead *pKernelHead, THREAD_STATE_NODE *arg0) { NV_ASSERT_PRECOMP(0); return; } -static inline void kheadResetPendingVblank_DISPATCH(struct OBJGPU *pGpu, struct KernelHead *pKernelHead, THREAD_STATE_NODE *arg0) { - pKernelHead->__kheadResetPendingVblank__(pGpu, pKernelHead, arg0); -} +void kheadResetPendingVblank_v03_00(struct OBJGPU *pGpu, struct KernelHead *pKernelHead, THREAD_STATE_NODE *arg0); -static inline void kheadResetPendingVblankForKernel_8305c4(struct OBJGPU *pGpu, struct KernelHead *pKernelHead, THREAD_STATE_NODE *pThreadState) { - kheadResetPendingVblank(pGpu, pKernelHead, pThreadState); -} +void kheadResetPendingVblank_v04_01(struct OBJGPU *pGpu, struct KernelHead *pKernelHead, THREAD_STATE_NODE *arg0); -static inline void kheadResetPendingVblankForKernel_e426af(struct OBJGPU *pGpu, struct KernelHead *pKernelHead, THREAD_STATE_NODE *pThreadState) { +static inline void kheadResetPendingVblank_f2d351(struct OBJGPU *pGpu, struct KernelHead *pKernelHead, THREAD_STATE_NODE *arg0) { NV_ASSERT_PRECOMP(0); - return; } -static inline void kheadResetPendingVblankForKernel_DISPATCH(struct OBJGPU *pGpu, struct KernelHead *pKernelHead, THREAD_STATE_NODE *pThreadState) { - pKernelHead->__kheadResetPendingVblankForKernel__(pGpu, pKernelHead, pThreadState); +static inline void kheadResetPendingVblank_DISPATCH(struct OBJGPU *pGpu, struct KernelHead *pKernelHead, THREAD_STATE_NODE *arg0) { + pKernelHead->__kheadResetPendingVblank__(pGpu, pKernelHead, arg0); } -NvU32 kheadReadPendingVblank_v04_00_KERNEL(struct OBJGPU *pGpu, struct KernelHead *pKernelHead, NvU32 intr); +NvBool kheadReadPendingVblank_KERNEL(struct OBJGPU *pGpu, struct KernelHead *pKernelHead, NvU32 *pCachedIntr, THREAD_STATE_NODE *pThreadState); -static inline NvU32 kheadReadPendingVblank_92bfc3(struct OBJGPU *pGpu, struct KernelHead *pKernelHead, NvU32 intr) { +static inline NvBool kheadReadPendingVblank_108313(struct OBJGPU *pGpu, struct KernelHead *pKernelHead, NvU32 *pCachedIntr, THREAD_STATE_NODE *pThreadState) { + NV_ASSERT_OR_RETURN_PRECOMP(0, ((NvBool)(0 != 0))); +} + +NvBool kheadReadPendingVblank_v03_00(struct OBJGPU *pGpu, struct KernelHead *pKernelHead, NvU32 *pCachedIntr, THREAD_STATE_NODE *pThreadState); + +static inline NvBool kheadReadPendingVblank_ceaee8(struct OBJGPU *pGpu, struct KernelHead *pKernelHead, NvU32 *pCachedIntr, THREAD_STATE_NODE *pThreadState) { NV_ASSERT_PRECOMP(0); - return NV_ERR_NOT_SUPPORTED; + return ((NvBool)(0 != 0)); } -static inline NvU32 kheadReadPendingVblank_DISPATCH(struct OBJGPU *pGpu, struct KernelHead *pKernelHead, NvU32 intr) { - return pKernelHead->__kheadReadPendingVblank__(pGpu, pKernelHead, intr); +static inline NvBool kheadReadPendingVblank_DISPATCH(struct OBJGPU *pGpu, struct KernelHead *pKernelHead, NvU32 *pCachedIntr, THREAD_STATE_NODE *pThreadState) { + return pKernelHead->__kheadReadPendingVblank__(pGpu, pKernelHead, pCachedIntr, pThreadState); } NV_STATUS kheadConstruct_IMPL(struct KernelHead *arg_pKernelHead); diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/generated/g_kernel_hostvgpudeviceapi_nvoc.c nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_kernel_hostvgpudeviceapi_nvoc.c --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/generated/g_kernel_hostvgpudeviceapi_nvoc.c 2023-10-25 20:27:09.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_kernel_hostvgpudeviceapi_nvoc.c 2024-03-05 22:18:29.000000000 +0000 @@ -124,13 +124,16 @@ Object *pParentObj; KernelHostVgpuDeviceShr *pThis; - pThis = portMemAllocNonPaged(sizeof(KernelHostVgpuDeviceShr)); - if (pThis == NULL) return NV_ERR_NO_MEMORY; + status = __nvoc_handleObjCreateMemAlloc(createFlags, sizeof(KernelHostVgpuDeviceShr), (void**)&pThis, (void**)ppThis); + if (status != NV_OK) + return status; portMemSet(pThis, 0, sizeof(KernelHostVgpuDeviceShr)); __nvoc_initRtti(staticCast(pThis, Dynamic), &__nvoc_class_def_KernelHostVgpuDeviceShr); + pThis->__nvoc_base_RsShared.__nvoc_base_Object.createFlags = createFlags; + if (pParent != NULL && !(createFlags & NVOC_OBJ_CREATE_FLAGS_PARENT_HALSPEC_ONLY)) { pParentObj = dynamicCast(pParent, Object); @@ -146,11 +149,17 @@ if (status != NV_OK) goto __nvoc_objCreate_KernelHostVgpuDeviceShr_cleanup; *ppThis = pThis; + return NV_OK; __nvoc_objCreate_KernelHostVgpuDeviceShr_cleanup: // do not call destructors here since the constructor already called them - portMemFree(pThis); + if (createFlags & NVOC_OBJ_CREATE_FLAGS_IN_PLACE_CONSTRUCT) + portMemSet(pThis, 0, sizeof(KernelHostVgpuDeviceShr)); + else + portMemFree(pThis); + + // coverity[leaked_storage:FALSE] return status; } @@ -274,16 +283,16 @@ return gpuresShareCallback((struct GpuResource *)(((unsigned char *)pGpuResource) + __nvoc_rtti_KernelHostVgpuDeviceApi_GpuResource.offset), pInvokingClient, pParentRef, pSharePolicy); } -static NV_STATUS __nvoc_thunk_RsResource_kernelhostvgpudeviceapiMapTo(struct KernelHostVgpuDeviceApi *pResource, RS_RES_MAP_TO_PARAMS *pParams) { - return resMapTo((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_KernelHostVgpuDeviceApi_RsResource.offset), pParams); +static NV_STATUS __nvoc_thunk_RmResource_kernelhostvgpudeviceapiCheckMemInterUnmap(struct KernelHostVgpuDeviceApi *pRmResource, NvBool bSubdeviceHandleProvided) { + return rmresCheckMemInterUnmap((struct RmResource *)(((unsigned char *)pRmResource) + __nvoc_rtti_KernelHostVgpuDeviceApi_RmResource.offset), bSubdeviceHandleProvided); } static NV_STATUS __nvoc_thunk_Notifier_kernelhostvgpudeviceapiGetOrAllocNotifShare(struct KernelHostVgpuDeviceApi *pNotifier, NvHandle hNotifierClient, NvHandle hNotifierResource, struct NotifShare **ppNotifShare) { return notifyGetOrAllocNotifShare((struct Notifier *)(((unsigned char *)pNotifier) + __nvoc_rtti_KernelHostVgpuDeviceApi_Notifier.offset), hNotifierClient, hNotifierResource, ppNotifShare); } -static NV_STATUS __nvoc_thunk_RmResource_kernelhostvgpudeviceapiCheckMemInterUnmap(struct KernelHostVgpuDeviceApi *pRmResource, NvBool bSubdeviceHandleProvided) { - return rmresCheckMemInterUnmap((struct RmResource *)(((unsigned char *)pRmResource) + __nvoc_rtti_KernelHostVgpuDeviceApi_RmResource.offset), bSubdeviceHandleProvided); +static NV_STATUS __nvoc_thunk_RsResource_kernelhostvgpudeviceapiMapTo(struct KernelHostVgpuDeviceApi *pResource, RS_RES_MAP_TO_PARAMS *pParams) { + return resMapTo((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_KernelHostVgpuDeviceApi_RsResource.offset), pParams); } static NV_STATUS __nvoc_thunk_GpuResource_kernelhostvgpudeviceapiGetMapAddrSpace(struct KernelHostVgpuDeviceApi *pGpuResource, CALL_CONTEXT *pCallContext, NvU32 mapFlags, NV_ADDRESS_SPACE *pAddrSpace) { @@ -354,6 +363,10 @@ return notifyUnregisterEvent((struct Notifier *)(((unsigned char *)pNotifier) + __nvoc_rtti_KernelHostVgpuDeviceApi_Notifier.offset), hNotifierClient, hNotifierResource, hEventClient, hEvent); } +static NV_STATUS __nvoc_thunk_RmResource_kernelhostvgpudeviceapiControlSerialization_Prologue(struct KernelHostVgpuDeviceApi *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return rmresControlSerialization_Prologue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_KernelHostVgpuDeviceApi_RmResource.offset), pCallContext, pParams); +} + static void __nvoc_thunk_RsResource_kernelhostvgpudeviceapiPreDestruct(struct KernelHostVgpuDeviceApi *pResource) { resPreDestruct((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_KernelHostVgpuDeviceApi_RsResource.offset)); } @@ -362,6 +375,10 @@ return resIsDuplicate((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_KernelHostVgpuDeviceApi_RsResource.offset), hMemory, pDuplicate); } +static void __nvoc_thunk_RmResource_kernelhostvgpudeviceapiControlSerialization_Epilogue(struct KernelHostVgpuDeviceApi *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + rmresControlSerialization_Epilogue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_KernelHostVgpuDeviceApi_RmResource.offset), pCallContext, pParams); +} + static PEVENTNOTIFICATION *__nvoc_thunk_Notifier_kernelhostvgpudeviceapiGetNotificationListPtr(struct KernelHostVgpuDeviceApi *pNotifier) { return notifyGetNotificationListPtr((struct Notifier *)(((unsigned char *)pNotifier) + __nvoc_rtti_KernelHostVgpuDeviceApi_Notifier.offset)); } @@ -493,30 +510,30 @@ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) /*pFunc=*/ (void (*)(void)) NULL, #else - /*pFunc=*/ (void (*)(void)) kernelhostvgpudeviceapiCtrlCmdSetSriovState_IMPL, + /*pFunc=*/ (void (*)(void)) kernelhostvgpudeviceapiCtrlCmdGetBarMappingRanges_IMPL, #endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) /*flags=*/ 0x10u, /*accessRight=*/0x0u, - /*methodId=*/ 0xa0840108u, - /*paramSize=*/ sizeof(NVA084_CTRL_KERNEL_HOST_VGPU_DEVICE_SET_SRIOV_STATE_PARAMS), + /*methodId=*/ 0xa084010au, + /*paramSize=*/ sizeof(NVA084_CTRL_KERNEL_HOST_VGPU_DEVICE_GET_BAR_MAPPING_RANGES_PARAMS), /*pClassInfo=*/ &(__nvoc_class_def_KernelHostVgpuDeviceApi.classInfo), #if NV_PRINTF_STRINGS_ALLOWED - /*func=*/ "kernelhostvgpudeviceapiCtrlCmdSetSriovState" + /*func=*/ "kernelhostvgpudeviceapiCtrlCmdGetBarMappingRanges" #endif }, { /* [8] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) /*pFunc=*/ (void (*)(void)) NULL, #else - /*pFunc=*/ (void (*)(void)) kernelhostvgpudeviceapiCtrlCmdSetGuestId_IMPL, + /*pFunc=*/ (void (*)(void)) kernelhostvgpudeviceapiCtrlCmdRestoreDefaultExecPartition_IMPL, #endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) /*flags=*/ 0x10u, /*accessRight=*/0x0u, - /*methodId=*/ 0xa0840109u, - /*paramSize=*/ sizeof(NVA084_CTRL_KERNEL_HOST_VGPU_DEVICE_SET_GUEST_ID_PARAMS), + /*methodId=*/ 0xa084010bu, + /*paramSize=*/ 0, /*pClassInfo=*/ &(__nvoc_class_def_KernelHostVgpuDeviceApi.classInfo), #if NV_PRINTF_STRINGS_ALLOWED - /*func=*/ "kernelhostvgpudeviceapiCtrlCmdSetGuestId" + /*func=*/ "kernelhostvgpudeviceapiCtrlCmdRestoreDefaultExecPartition" #endif }, @@ -599,22 +616,22 @@ #endif #if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) - pThis->__kernelhostvgpudeviceapiCtrlCmdSetSriovState__ = &kernelhostvgpudeviceapiCtrlCmdSetSriovState_IMPL; + pThis->__kernelhostvgpudeviceapiCtrlCmdGetBarMappingRanges__ = &kernelhostvgpudeviceapiCtrlCmdGetBarMappingRanges_IMPL; #endif #if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) - pThis->__kernelhostvgpudeviceapiCtrlCmdSetGuestId__ = &kernelhostvgpudeviceapiCtrlCmdSetGuestId_IMPL; + pThis->__kernelhostvgpudeviceapiCtrlCmdRestoreDefaultExecPartition__ = &kernelhostvgpudeviceapiCtrlCmdRestoreDefaultExecPartition_IMPL; #endif pThis->__nvoc_base_GpuResource.__nvoc_base_RmResource.__nvoc_base_RsResource.__resCanCopy__ = &__nvoc_thunk_KernelHostVgpuDeviceApi_resCanCopy; pThis->__kernelhostvgpudeviceapiShareCallback__ = &__nvoc_thunk_GpuResource_kernelhostvgpudeviceapiShareCallback; - pThis->__kernelhostvgpudeviceapiMapTo__ = &__nvoc_thunk_RsResource_kernelhostvgpudeviceapiMapTo; + pThis->__kernelhostvgpudeviceapiCheckMemInterUnmap__ = &__nvoc_thunk_RmResource_kernelhostvgpudeviceapiCheckMemInterUnmap; pThis->__kernelhostvgpudeviceapiGetOrAllocNotifShare__ = &__nvoc_thunk_Notifier_kernelhostvgpudeviceapiGetOrAllocNotifShare; - pThis->__kernelhostvgpudeviceapiCheckMemInterUnmap__ = &__nvoc_thunk_RmResource_kernelhostvgpudeviceapiCheckMemInterUnmap; + pThis->__kernelhostvgpudeviceapiMapTo__ = &__nvoc_thunk_RsResource_kernelhostvgpudeviceapiMapTo; pThis->__kernelhostvgpudeviceapiGetMapAddrSpace__ = &__nvoc_thunk_GpuResource_kernelhostvgpudeviceapiGetMapAddrSpace; @@ -650,10 +667,14 @@ pThis->__kernelhostvgpudeviceapiUnregisterEvent__ = &__nvoc_thunk_Notifier_kernelhostvgpudeviceapiUnregisterEvent; + pThis->__kernelhostvgpudeviceapiControlSerialization_Prologue__ = &__nvoc_thunk_RmResource_kernelhostvgpudeviceapiControlSerialization_Prologue; + pThis->__kernelhostvgpudeviceapiPreDestruct__ = &__nvoc_thunk_RsResource_kernelhostvgpudeviceapiPreDestruct; pThis->__kernelhostvgpudeviceapiIsDuplicate__ = &__nvoc_thunk_RsResource_kernelhostvgpudeviceapiIsDuplicate; + pThis->__kernelhostvgpudeviceapiControlSerialization_Epilogue__ = &__nvoc_thunk_RmResource_kernelhostvgpudeviceapiControlSerialization_Epilogue; + pThis->__kernelhostvgpudeviceapiGetNotificationListPtr__ = &__nvoc_thunk_Notifier_kernelhostvgpudeviceapiGetNotificationListPtr; pThis->__kernelhostvgpudeviceapiGetNotificationShare__ = &__nvoc_thunk_Notifier_kernelhostvgpudeviceapiGetNotificationShare; @@ -688,13 +709,16 @@ Object *pParentObj; KernelHostVgpuDeviceApi *pThis; - pThis = portMemAllocNonPaged(sizeof(KernelHostVgpuDeviceApi)); - if (pThis == NULL) return NV_ERR_NO_MEMORY; + status = __nvoc_handleObjCreateMemAlloc(createFlags, sizeof(KernelHostVgpuDeviceApi), (void**)&pThis, (void**)ppThis); + if (status != NV_OK) + return status; portMemSet(pThis, 0, sizeof(KernelHostVgpuDeviceApi)); __nvoc_initRtti(staticCast(pThis, Dynamic), &__nvoc_class_def_KernelHostVgpuDeviceApi); + pThis->__nvoc_base_GpuResource.__nvoc_base_RmResource.__nvoc_base_RsResource.__nvoc_base_Object.createFlags = createFlags; + if (pParent != NULL && !(createFlags & NVOC_OBJ_CREATE_FLAGS_PARENT_HALSPEC_ONLY)) { pParentObj = dynamicCast(pParent, Object); @@ -710,11 +734,17 @@ if (status != NV_OK) goto __nvoc_objCreate_KernelHostVgpuDeviceApi_cleanup; *ppThis = pThis; + return NV_OK; __nvoc_objCreate_KernelHostVgpuDeviceApi_cleanup: // do not call destructors here since the constructor already called them - portMemFree(pThis); + if (createFlags & NVOC_OBJ_CREATE_FLAGS_IN_PLACE_CONSTRUCT) + portMemSet(pThis, 0, sizeof(KernelHostVgpuDeviceApi)); + else + portMemFree(pThis); + + // coverity[leaked_storage:FALSE] return status; } diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/generated/g_kernel_hostvgpudeviceapi_nvoc.h nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_kernel_hostvgpudeviceapi_nvoc.h --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/generated/g_kernel_hostvgpudeviceapi_nvoc.h 2023-10-25 20:27:09.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_kernel_hostvgpudeviceapi_nvoc.h 2024-03-05 22:18:29.000000000 +0000 @@ -7,7 +7,7 @@ #endif /* - * SPDX-FileCopyrightText: Copyright (c) 2021-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2021-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -119,12 +119,12 @@ NV_STATUS (*__kernelhostvgpudeviceapiCtrlCmdBindFecsEvtbuf__)(struct KernelHostVgpuDeviceApi *, NVA084_CTRL_KERNEL_HOST_VGPU_DEVICE_BIND_FECS_EVTBUF_PARAMS *); NV_STATUS (*__kernelhostvgpudeviceapiCtrlCmdTriggerPrivDoorbell__)(struct KernelHostVgpuDeviceApi *, NVA084_CTRL_KERNEL_HOST_VGPU_DEVICE_TRIGGER_PRIV_DOORBELL_PARAMS *); NV_STATUS (*__kernelhostvgpudeviceapiCtrlCmdEventSetNotification__)(struct KernelHostVgpuDeviceApi *, NVA084_CTRL_KERNEL_HOST_VGPU_DEVICE_EVENT_SET_NOTIFICATION_PARAMS *); - NV_STATUS (*__kernelhostvgpudeviceapiCtrlCmdSetSriovState__)(struct KernelHostVgpuDeviceApi *, NVA084_CTRL_KERNEL_HOST_VGPU_DEVICE_SET_SRIOV_STATE_PARAMS *); - NV_STATUS (*__kernelhostvgpudeviceapiCtrlCmdSetGuestId__)(struct KernelHostVgpuDeviceApi *, NVA084_CTRL_KERNEL_HOST_VGPU_DEVICE_SET_GUEST_ID_PARAMS *); + NV_STATUS (*__kernelhostvgpudeviceapiCtrlCmdGetBarMappingRanges__)(struct KernelHostVgpuDeviceApi *, NVA084_CTRL_KERNEL_HOST_VGPU_DEVICE_GET_BAR_MAPPING_RANGES_PARAMS *); + NV_STATUS (*__kernelhostvgpudeviceapiCtrlCmdRestoreDefaultExecPartition__)(struct KernelHostVgpuDeviceApi *); NvBool (*__kernelhostvgpudeviceapiShareCallback__)(struct KernelHostVgpuDeviceApi *, struct RsClient *, struct RsResourceRef *, RS_SHARE_POLICY *); - NV_STATUS (*__kernelhostvgpudeviceapiMapTo__)(struct KernelHostVgpuDeviceApi *, RS_RES_MAP_TO_PARAMS *); - NV_STATUS (*__kernelhostvgpudeviceapiGetOrAllocNotifShare__)(struct KernelHostVgpuDeviceApi *, NvHandle, NvHandle, struct NotifShare **); NV_STATUS (*__kernelhostvgpudeviceapiCheckMemInterUnmap__)(struct KernelHostVgpuDeviceApi *, NvBool); + NV_STATUS (*__kernelhostvgpudeviceapiGetOrAllocNotifShare__)(struct KernelHostVgpuDeviceApi *, NvHandle, NvHandle, struct NotifShare **); + NV_STATUS (*__kernelhostvgpudeviceapiMapTo__)(struct KernelHostVgpuDeviceApi *, RS_RES_MAP_TO_PARAMS *); NV_STATUS (*__kernelhostvgpudeviceapiGetMapAddrSpace__)(struct KernelHostVgpuDeviceApi *, CALL_CONTEXT *, NvU32, NV_ADDRESS_SPACE *); void (*__kernelhostvgpudeviceapiSetNotificationShare__)(struct KernelHostVgpuDeviceApi *, struct NotifShare *); NvU32 (*__kernelhostvgpudeviceapiGetRefCount__)(struct KernelHostVgpuDeviceApi *); @@ -142,8 +142,10 @@ NV_STATUS (*__kernelhostvgpudeviceapiGetMemoryMappingDescriptor__)(struct KernelHostVgpuDeviceApi *, struct MEMORY_DESCRIPTOR **); NV_STATUS (*__kernelhostvgpudeviceapiControlFilter__)(struct KernelHostVgpuDeviceApi *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); NV_STATUS (*__kernelhostvgpudeviceapiUnregisterEvent__)(struct KernelHostVgpuDeviceApi *, NvHandle, NvHandle, NvHandle, NvHandle); + NV_STATUS (*__kernelhostvgpudeviceapiControlSerialization_Prologue__)(struct KernelHostVgpuDeviceApi *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); void (*__kernelhostvgpudeviceapiPreDestruct__)(struct KernelHostVgpuDeviceApi *); NV_STATUS (*__kernelhostvgpudeviceapiIsDuplicate__)(struct KernelHostVgpuDeviceApi *, NvHandle, NvBool *); + void (*__kernelhostvgpudeviceapiControlSerialization_Epilogue__)(struct KernelHostVgpuDeviceApi *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); PEVENTNOTIFICATION *(*__kernelhostvgpudeviceapiGetNotificationListPtr__)(struct KernelHostVgpuDeviceApi *); struct NotifShare *(*__kernelhostvgpudeviceapiGetNotificationShare__)(struct KernelHostVgpuDeviceApi *); NV_STATUS (*__kernelhostvgpudeviceapiMap__)(struct KernelHostVgpuDeviceApi *, CALL_CONTEXT *, struct RS_CPU_MAP_PARAMS *, RsCpuMapping *); @@ -188,12 +190,12 @@ #define kernelhostvgpudeviceapiCtrlCmdBindFecsEvtbuf(pKernelHostVgpuDeviceApi, pParams) kernelhostvgpudeviceapiCtrlCmdBindFecsEvtbuf_DISPATCH(pKernelHostVgpuDeviceApi, pParams) #define kernelhostvgpudeviceapiCtrlCmdTriggerPrivDoorbell(pKernelHostVgpuDeviceApi, pParams) kernelhostvgpudeviceapiCtrlCmdTriggerPrivDoorbell_DISPATCH(pKernelHostVgpuDeviceApi, pParams) #define kernelhostvgpudeviceapiCtrlCmdEventSetNotification(pKernelHostVgpuDeviceApi, pSetEventParams) kernelhostvgpudeviceapiCtrlCmdEventSetNotification_DISPATCH(pKernelHostVgpuDeviceApi, pSetEventParams) -#define kernelhostvgpudeviceapiCtrlCmdSetSriovState(pKernelHostVgpuDeviceApi, pParams) kernelhostvgpudeviceapiCtrlCmdSetSriovState_DISPATCH(pKernelHostVgpuDeviceApi, pParams) -#define kernelhostvgpudeviceapiCtrlCmdSetGuestId(pKernelHostVgpuDeviceApi, pParams) kernelhostvgpudeviceapiCtrlCmdSetGuestId_DISPATCH(pKernelHostVgpuDeviceApi, pParams) +#define kernelhostvgpudeviceapiCtrlCmdGetBarMappingRanges(pKernelHostVgpuDeviceApi, pParams) kernelhostvgpudeviceapiCtrlCmdGetBarMappingRanges_DISPATCH(pKernelHostVgpuDeviceApi, pParams) +#define kernelhostvgpudeviceapiCtrlCmdRestoreDefaultExecPartition(pKernelHostVgpuDeviceApi) kernelhostvgpudeviceapiCtrlCmdRestoreDefaultExecPartition_DISPATCH(pKernelHostVgpuDeviceApi) #define kernelhostvgpudeviceapiShareCallback(pGpuResource, pInvokingClient, pParentRef, pSharePolicy) kernelhostvgpudeviceapiShareCallback_DISPATCH(pGpuResource, pInvokingClient, pParentRef, pSharePolicy) -#define kernelhostvgpudeviceapiMapTo(pResource, pParams) kernelhostvgpudeviceapiMapTo_DISPATCH(pResource, pParams) -#define kernelhostvgpudeviceapiGetOrAllocNotifShare(pNotifier, hNotifierClient, hNotifierResource, ppNotifShare) kernelhostvgpudeviceapiGetOrAllocNotifShare_DISPATCH(pNotifier, hNotifierClient, hNotifierResource, ppNotifShare) #define kernelhostvgpudeviceapiCheckMemInterUnmap(pRmResource, bSubdeviceHandleProvided) kernelhostvgpudeviceapiCheckMemInterUnmap_DISPATCH(pRmResource, bSubdeviceHandleProvided) +#define kernelhostvgpudeviceapiGetOrAllocNotifShare(pNotifier, hNotifierClient, hNotifierResource, ppNotifShare) kernelhostvgpudeviceapiGetOrAllocNotifShare_DISPATCH(pNotifier, hNotifierClient, hNotifierResource, ppNotifShare) +#define kernelhostvgpudeviceapiMapTo(pResource, pParams) kernelhostvgpudeviceapiMapTo_DISPATCH(pResource, pParams) #define kernelhostvgpudeviceapiGetMapAddrSpace(pGpuResource, pCallContext, mapFlags, pAddrSpace) kernelhostvgpudeviceapiGetMapAddrSpace_DISPATCH(pGpuResource, pCallContext, mapFlags, pAddrSpace) #define kernelhostvgpudeviceapiSetNotificationShare(pNotifier, pNotifShare) kernelhostvgpudeviceapiSetNotificationShare_DISPATCH(pNotifier, pNotifShare) #define kernelhostvgpudeviceapiGetRefCount(pResource) kernelhostvgpudeviceapiGetRefCount_DISPATCH(pResource) @@ -211,8 +213,10 @@ #define kernelhostvgpudeviceapiGetMemoryMappingDescriptor(pRmResource, ppMemDesc) kernelhostvgpudeviceapiGetMemoryMappingDescriptor_DISPATCH(pRmResource, ppMemDesc) #define kernelhostvgpudeviceapiControlFilter(pResource, pCallContext, pParams) kernelhostvgpudeviceapiControlFilter_DISPATCH(pResource, pCallContext, pParams) #define kernelhostvgpudeviceapiUnregisterEvent(pNotifier, hNotifierClient, hNotifierResource, hEventClient, hEvent) kernelhostvgpudeviceapiUnregisterEvent_DISPATCH(pNotifier, hNotifierClient, hNotifierResource, hEventClient, hEvent) +#define kernelhostvgpudeviceapiControlSerialization_Prologue(pResource, pCallContext, pParams) kernelhostvgpudeviceapiControlSerialization_Prologue_DISPATCH(pResource, pCallContext, pParams) #define kernelhostvgpudeviceapiPreDestruct(pResource) kernelhostvgpudeviceapiPreDestruct_DISPATCH(pResource) #define kernelhostvgpudeviceapiIsDuplicate(pResource, hMemory, pDuplicate) kernelhostvgpudeviceapiIsDuplicate_DISPATCH(pResource, hMemory, pDuplicate) +#define kernelhostvgpudeviceapiControlSerialization_Epilogue(pResource, pCallContext, pParams) kernelhostvgpudeviceapiControlSerialization_Epilogue_DISPATCH(pResource, pCallContext, pParams) #define kernelhostvgpudeviceapiGetNotificationListPtr(pNotifier) kernelhostvgpudeviceapiGetNotificationListPtr_DISPATCH(pNotifier) #define kernelhostvgpudeviceapiGetNotificationShare(pNotifier) kernelhostvgpudeviceapiGetNotificationShare_DISPATCH(pNotifier) #define kernelhostvgpudeviceapiMap(pGpuResource, pCallContext, pParams, pCpuMapping) kernelhostvgpudeviceapiMap_DISPATCH(pGpuResource, pCallContext, pParams, pCpuMapping) @@ -265,32 +269,32 @@ return pKernelHostVgpuDeviceApi->__kernelhostvgpudeviceapiCtrlCmdEventSetNotification__(pKernelHostVgpuDeviceApi, pSetEventParams); } -NV_STATUS kernelhostvgpudeviceapiCtrlCmdSetSriovState_IMPL(struct KernelHostVgpuDeviceApi *pKernelHostVgpuDeviceApi, NVA084_CTRL_KERNEL_HOST_VGPU_DEVICE_SET_SRIOV_STATE_PARAMS *pParams); +NV_STATUS kernelhostvgpudeviceapiCtrlCmdGetBarMappingRanges_IMPL(struct KernelHostVgpuDeviceApi *pKernelHostVgpuDeviceApi, NVA084_CTRL_KERNEL_HOST_VGPU_DEVICE_GET_BAR_MAPPING_RANGES_PARAMS *pParams); -static inline NV_STATUS kernelhostvgpudeviceapiCtrlCmdSetSriovState_DISPATCH(struct KernelHostVgpuDeviceApi *pKernelHostVgpuDeviceApi, NVA084_CTRL_KERNEL_HOST_VGPU_DEVICE_SET_SRIOV_STATE_PARAMS *pParams) { - return pKernelHostVgpuDeviceApi->__kernelhostvgpudeviceapiCtrlCmdSetSriovState__(pKernelHostVgpuDeviceApi, pParams); +static inline NV_STATUS kernelhostvgpudeviceapiCtrlCmdGetBarMappingRanges_DISPATCH(struct KernelHostVgpuDeviceApi *pKernelHostVgpuDeviceApi, NVA084_CTRL_KERNEL_HOST_VGPU_DEVICE_GET_BAR_MAPPING_RANGES_PARAMS *pParams) { + return pKernelHostVgpuDeviceApi->__kernelhostvgpudeviceapiCtrlCmdGetBarMappingRanges__(pKernelHostVgpuDeviceApi, pParams); } -NV_STATUS kernelhostvgpudeviceapiCtrlCmdSetGuestId_IMPL(struct KernelHostVgpuDeviceApi *pKernelHostVgpuDeviceApi, NVA084_CTRL_KERNEL_HOST_VGPU_DEVICE_SET_GUEST_ID_PARAMS *pParams); +NV_STATUS kernelhostvgpudeviceapiCtrlCmdRestoreDefaultExecPartition_IMPL(struct KernelHostVgpuDeviceApi *pKernelHostVgpuDeviceApi); -static inline NV_STATUS kernelhostvgpudeviceapiCtrlCmdSetGuestId_DISPATCH(struct KernelHostVgpuDeviceApi *pKernelHostVgpuDeviceApi, NVA084_CTRL_KERNEL_HOST_VGPU_DEVICE_SET_GUEST_ID_PARAMS *pParams) { - return pKernelHostVgpuDeviceApi->__kernelhostvgpudeviceapiCtrlCmdSetGuestId__(pKernelHostVgpuDeviceApi, pParams); +static inline NV_STATUS kernelhostvgpudeviceapiCtrlCmdRestoreDefaultExecPartition_DISPATCH(struct KernelHostVgpuDeviceApi *pKernelHostVgpuDeviceApi) { + return pKernelHostVgpuDeviceApi->__kernelhostvgpudeviceapiCtrlCmdRestoreDefaultExecPartition__(pKernelHostVgpuDeviceApi); } static inline NvBool kernelhostvgpudeviceapiShareCallback_DISPATCH(struct KernelHostVgpuDeviceApi *pGpuResource, struct RsClient *pInvokingClient, struct RsResourceRef *pParentRef, RS_SHARE_POLICY *pSharePolicy) { return pGpuResource->__kernelhostvgpudeviceapiShareCallback__(pGpuResource, pInvokingClient, pParentRef, pSharePolicy); } -static inline NV_STATUS kernelhostvgpudeviceapiMapTo_DISPATCH(struct KernelHostVgpuDeviceApi *pResource, RS_RES_MAP_TO_PARAMS *pParams) { - return pResource->__kernelhostvgpudeviceapiMapTo__(pResource, pParams); +static inline NV_STATUS kernelhostvgpudeviceapiCheckMemInterUnmap_DISPATCH(struct KernelHostVgpuDeviceApi *pRmResource, NvBool bSubdeviceHandleProvided) { + return pRmResource->__kernelhostvgpudeviceapiCheckMemInterUnmap__(pRmResource, bSubdeviceHandleProvided); } static inline NV_STATUS kernelhostvgpudeviceapiGetOrAllocNotifShare_DISPATCH(struct KernelHostVgpuDeviceApi *pNotifier, NvHandle hNotifierClient, NvHandle hNotifierResource, struct NotifShare **ppNotifShare) { return pNotifier->__kernelhostvgpudeviceapiGetOrAllocNotifShare__(pNotifier, hNotifierClient, hNotifierResource, ppNotifShare); } -static inline NV_STATUS kernelhostvgpudeviceapiCheckMemInterUnmap_DISPATCH(struct KernelHostVgpuDeviceApi *pRmResource, NvBool bSubdeviceHandleProvided) { - return pRmResource->__kernelhostvgpudeviceapiCheckMemInterUnmap__(pRmResource, bSubdeviceHandleProvided); +static inline NV_STATUS kernelhostvgpudeviceapiMapTo_DISPATCH(struct KernelHostVgpuDeviceApi *pResource, RS_RES_MAP_TO_PARAMS *pParams) { + return pResource->__kernelhostvgpudeviceapiMapTo__(pResource, pParams); } static inline NV_STATUS kernelhostvgpudeviceapiGetMapAddrSpace_DISPATCH(struct KernelHostVgpuDeviceApi *pGpuResource, CALL_CONTEXT *pCallContext, NvU32 mapFlags, NV_ADDRESS_SPACE *pAddrSpace) { @@ -361,6 +365,10 @@ return pNotifier->__kernelhostvgpudeviceapiUnregisterEvent__(pNotifier, hNotifierClient, hNotifierResource, hEventClient, hEvent); } +static inline NV_STATUS kernelhostvgpudeviceapiControlSerialization_Prologue_DISPATCH(struct KernelHostVgpuDeviceApi *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return pResource->__kernelhostvgpudeviceapiControlSerialization_Prologue__(pResource, pCallContext, pParams); +} + static inline void kernelhostvgpudeviceapiPreDestruct_DISPATCH(struct KernelHostVgpuDeviceApi *pResource) { pResource->__kernelhostvgpudeviceapiPreDestruct__(pResource); } @@ -369,6 +377,10 @@ return pResource->__kernelhostvgpudeviceapiIsDuplicate__(pResource, hMemory, pDuplicate); } +static inline void kernelhostvgpudeviceapiControlSerialization_Epilogue_DISPATCH(struct KernelHostVgpuDeviceApi *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + pResource->__kernelhostvgpudeviceapiControlSerialization_Epilogue__(pResource, pCallContext, pParams); +} + static inline PEVENTNOTIFICATION *kernelhostvgpudeviceapiGetNotificationListPtr_DISPATCH(struct KernelHostVgpuDeviceApi *pNotifier) { return pNotifier->__kernelhostvgpudeviceapiGetNotificationListPtr__(pNotifier); } diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/generated/g_kernel_ioctrl_nvoc.c nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_kernel_ioctrl_nvoc.c --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/generated/g_kernel_ioctrl_nvoc.c 2023-10-25 20:27:09.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_kernel_ioctrl_nvoc.c 2024-03-05 22:18:30.000000000 +0000 @@ -70,10 +70,6 @@ return kioctrlConstructEngine(arg0, (struct KernelIoctrl *)(((unsigned char *)arg1) - __nvoc_rtti_KernelIoctrl_OBJENGSTATE.offset), arg2); } -static NV_STATUS __nvoc_thunk_OBJENGSTATE_kioctrlReconcileTunableState(POBJGPU pGpu, struct KernelIoctrl *pEngstate, void *pTunableState) { - return engstateReconcileTunableState(pGpu, (struct OBJENGSTATE *)(((unsigned char *)pEngstate) + __nvoc_rtti_KernelIoctrl_OBJENGSTATE.offset), pTunableState); -} - static NV_STATUS __nvoc_thunk_OBJENGSTATE_kioctrlStateLoad(POBJGPU pGpu, struct KernelIoctrl *pEngstate, NvU32 arg0) { return engstateStateLoad(pGpu, (struct OBJENGSTATE *)(((unsigned char *)pEngstate) + __nvoc_rtti_KernelIoctrl_OBJENGSTATE.offset), arg0); } @@ -118,30 +114,10 @@ return engstateStatePreInitUnlocked(pGpu, (struct OBJENGSTATE *)(((unsigned char *)pEngstate) + __nvoc_rtti_KernelIoctrl_OBJENGSTATE.offset)); } -static NV_STATUS __nvoc_thunk_OBJENGSTATE_kioctrlGetTunableState(POBJGPU pGpu, struct KernelIoctrl *pEngstate, void *pTunableState) { - return engstateGetTunableState(pGpu, (struct OBJENGSTATE *)(((unsigned char *)pEngstate) + __nvoc_rtti_KernelIoctrl_OBJENGSTATE.offset), pTunableState); -} - -static NV_STATUS __nvoc_thunk_OBJENGSTATE_kioctrlCompareTunableState(POBJGPU pGpu, struct KernelIoctrl *pEngstate, void *pTunables1, void *pTunables2) { - return engstateCompareTunableState(pGpu, (struct OBJENGSTATE *)(((unsigned char *)pEngstate) + __nvoc_rtti_KernelIoctrl_OBJENGSTATE.offset), pTunables1, pTunables2); -} - -static void __nvoc_thunk_OBJENGSTATE_kioctrlFreeTunableState(POBJGPU pGpu, struct KernelIoctrl *pEngstate, void *pTunableState) { - engstateFreeTunableState(pGpu, (struct OBJENGSTATE *)(((unsigned char *)pEngstate) + __nvoc_rtti_KernelIoctrl_OBJENGSTATE.offset), pTunableState); -} - static NV_STATUS __nvoc_thunk_OBJENGSTATE_kioctrlStatePostLoad(POBJGPU pGpu, struct KernelIoctrl *pEngstate, NvU32 arg0) { return engstateStatePostLoad(pGpu, (struct OBJENGSTATE *)(((unsigned char *)pEngstate) + __nvoc_rtti_KernelIoctrl_OBJENGSTATE.offset), arg0); } -static NV_STATUS __nvoc_thunk_OBJENGSTATE_kioctrlAllocTunableState(POBJGPU pGpu, struct KernelIoctrl *pEngstate, void **ppTunableState) { - return engstateAllocTunableState(pGpu, (struct OBJENGSTATE *)(((unsigned char *)pEngstate) + __nvoc_rtti_KernelIoctrl_OBJENGSTATE.offset), ppTunableState); -} - -static NV_STATUS __nvoc_thunk_OBJENGSTATE_kioctrlSetTunableState(POBJGPU pGpu, struct KernelIoctrl *pEngstate, void *pTunableState) { - return engstateSetTunableState(pGpu, (struct OBJENGSTATE *)(((unsigned char *)pEngstate) + __nvoc_rtti_KernelIoctrl_OBJENGSTATE.offset), pTunableState); -} - static NvBool __nvoc_thunk_OBJENGSTATE_kioctrlIsPresent(POBJGPU pGpu, struct KernelIoctrl *pEngstate) { return engstateIsPresent(pGpu, (struct OBJENGSTATE *)(((unsigned char *)pEngstate) + __nvoc_rtti_KernelIoctrl_OBJENGSTATE.offset)); } @@ -217,35 +193,27 @@ pThis->__kioctrlConstructEngine__ = &kioctrlConstructEngine_IMPL; // Hal function -- kioctrlGetMinionEnableDefault - if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000002UL) )) /* RmVariantHal: PF_KERNEL_ONLY */ + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x00000380UL) )) /* ChipHal: TU106 | TU116 | TU117 */ + { + pThis->__kioctrlGetMinionEnableDefault__ = &kioctrlGetMinionEnableDefault_bf6dfa; + } + else { - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x11f0fc60UL) )) /* ChipHal: TU102 | TU104 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 | GH100 */ - { - pThis->__kioctrlGetMinionEnableDefault__ = &kioctrlGetMinionEnableDefault_GV100; - } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x00000380UL) )) /* ChipHal: TU106 | TU116 | TU117 */ - { - pThis->__kioctrlGetMinionEnableDefault__ = &kioctrlGetMinionEnableDefault_bf6dfa; - } + pThis->__kioctrlGetMinionEnableDefault__ = &kioctrlGetMinionEnableDefault_GV100; } // Hal function -- kioctrlMinionConstruct - if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000002UL) )) /* RmVariantHal: PF_KERNEL_ONLY */ + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x00000380UL) )) /* ChipHal: TU106 | TU116 | TU117 */ + { + pThis->__kioctrlMinionConstruct__ = &kioctrlMinionConstruct_ac1694; + } + else { - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x11f0fc60UL) )) /* ChipHal: TU102 | TU104 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 | GH100 */ - { - pThis->__kioctrlMinionConstruct__ = &kioctrlMinionConstruct_GV100; - } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x00000380UL) )) /* ChipHal: TU106 | TU116 | TU117 */ - { - pThis->__kioctrlMinionConstruct__ = &kioctrlMinionConstruct_ac1694; - } + pThis->__kioctrlMinionConstruct__ = &kioctrlMinionConstruct_GV100; } pThis->__nvoc_base_OBJENGSTATE.__engstateConstructEngine__ = &__nvoc_thunk_KernelIoctrl_engstateConstructEngine; - pThis->__kioctrlReconcileTunableState__ = &__nvoc_thunk_OBJENGSTATE_kioctrlReconcileTunableState; - pThis->__kioctrlStateLoad__ = &__nvoc_thunk_OBJENGSTATE_kioctrlStateLoad; pThis->__kioctrlStateUnload__ = &__nvoc_thunk_OBJENGSTATE_kioctrlStateUnload; @@ -268,18 +236,8 @@ pThis->__kioctrlStatePreInitUnlocked__ = &__nvoc_thunk_OBJENGSTATE_kioctrlStatePreInitUnlocked; - pThis->__kioctrlGetTunableState__ = &__nvoc_thunk_OBJENGSTATE_kioctrlGetTunableState; - - pThis->__kioctrlCompareTunableState__ = &__nvoc_thunk_OBJENGSTATE_kioctrlCompareTunableState; - - pThis->__kioctrlFreeTunableState__ = &__nvoc_thunk_OBJENGSTATE_kioctrlFreeTunableState; - pThis->__kioctrlStatePostLoad__ = &__nvoc_thunk_OBJENGSTATE_kioctrlStatePostLoad; - pThis->__kioctrlAllocTunableState__ = &__nvoc_thunk_OBJENGSTATE_kioctrlAllocTunableState; - - pThis->__kioctrlSetTunableState__ = &__nvoc_thunk_OBJENGSTATE_kioctrlSetTunableState; - pThis->__kioctrlIsPresent__ = &__nvoc_thunk_OBJENGSTATE_kioctrlIsPresent; } @@ -302,13 +260,16 @@ KernelIoctrl *pThis; RmHalspecOwner *pRmhalspecowner; - pThis = portMemAllocNonPaged(sizeof(KernelIoctrl)); - if (pThis == NULL) return NV_ERR_NO_MEMORY; + status = __nvoc_handleObjCreateMemAlloc(createFlags, sizeof(KernelIoctrl), (void**)&pThis, (void**)ppThis); + if (status != NV_OK) + return status; portMemSet(pThis, 0, sizeof(KernelIoctrl)); __nvoc_initRtti(staticCast(pThis, Dynamic), &__nvoc_class_def_KernelIoctrl); + pThis->__nvoc_base_OBJENGSTATE.__nvoc_base_Object.createFlags = createFlags; + if (pParent != NULL && !(createFlags & NVOC_OBJ_CREATE_FLAGS_PARENT_HALSPEC_ONLY)) { pParentObj = dynamicCast(pParent, Object); @@ -328,11 +289,17 @@ if (status != NV_OK) goto __nvoc_objCreate_KernelIoctrl_cleanup; *ppThis = pThis; + return NV_OK; __nvoc_objCreate_KernelIoctrl_cleanup: // do not call destructors here since the constructor already called them - portMemFree(pThis); + if (createFlags & NVOC_OBJ_CREATE_FLAGS_IN_PLACE_CONSTRUCT) + portMemSet(pThis, 0, sizeof(KernelIoctrl)); + else + portMemFree(pThis); + + // coverity[leaked_storage:FALSE] return status; } diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/generated/g_kernel_ioctrl_nvoc.h nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_kernel_ioctrl_nvoc.h --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/generated/g_kernel_ioctrl_nvoc.h 2023-10-25 20:27:09.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_kernel_ioctrl_nvoc.h 2024-03-05 22:18:30.000000000 +0000 @@ -7,7 +7,7 @@ #endif /* - * SPDX-FileCopyrightText: Copyright (c) 2021-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2021-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -47,7 +47,7 @@ /*! * KernelIoctrl is a logical abstraction of the GPU Ioctrl Engine. The - * Public API of the Ioctrl Engine is exposed through this object, and + * Public API of the Ioctrl Engine is exposed through this object, and * any interfaces which do not manage the underlying Ioctrl hardware * can be managed by this object. */ @@ -65,7 +65,6 @@ NV_STATUS (*__kioctrlConstructEngine__)(struct OBJGPU *, struct KernelIoctrl *, NvU32); NvBool (*__kioctrlGetMinionEnableDefault__)(struct OBJGPU *, struct KernelIoctrl *); NV_STATUS (*__kioctrlMinionConstruct__)(struct OBJGPU *, struct KernelIoctrl *); - NV_STATUS (*__kioctrlReconcileTunableState__)(POBJGPU, struct KernelIoctrl *, void *); NV_STATUS (*__kioctrlStateLoad__)(POBJGPU, struct KernelIoctrl *, NvU32); NV_STATUS (*__kioctrlStateUnload__)(POBJGPU, struct KernelIoctrl *, NvU32); NV_STATUS (*__kioctrlStateInitLocked__)(POBJGPU, struct KernelIoctrl *); @@ -77,23 +76,18 @@ void (*__kioctrlInitMissing__)(POBJGPU, struct KernelIoctrl *); NV_STATUS (*__kioctrlStatePreInitLocked__)(POBJGPU, struct KernelIoctrl *); NV_STATUS (*__kioctrlStatePreInitUnlocked__)(POBJGPU, struct KernelIoctrl *); - NV_STATUS (*__kioctrlGetTunableState__)(POBJGPU, struct KernelIoctrl *, void *); - NV_STATUS (*__kioctrlCompareTunableState__)(POBJGPU, struct KernelIoctrl *, void *, void *); - void (*__kioctrlFreeTunableState__)(POBJGPU, struct KernelIoctrl *, void *); NV_STATUS (*__kioctrlStatePostLoad__)(POBJGPU, struct KernelIoctrl *, NvU32); - NV_STATUS (*__kioctrlAllocTunableState__)(POBJGPU, struct KernelIoctrl *, void **); - NV_STATUS (*__kioctrlSetTunableState__)(POBJGPU, struct KernelIoctrl *, void *); NvBool (*__kioctrlIsPresent__)(POBJGPU, struct KernelIoctrl *); NvBool PDB_PROP_KIOCTRL_MINION_AVAILABLE; NvBool PDB_PROP_KIOCTRL_MINION_FORCE_BOOT; NvBool PDB_PROP_KIOCTRL_MINION_CACHE_SEEDS; - NvU32 PublicId; - NvU32 localDiscoveredLinks; - NvU32 localGlobalLinkOffset; - NvU32 ipVerIoctrl; - NvU32 ipVerMinion; - NvU32 ioctrlDiscoverySize; - NvU8 numDevices; + NvU32 PRIVATE_FIELD(PublicId); + NvU32 PRIVATE_FIELD(localDiscoveredLinks); + NvU32 PRIVATE_FIELD(localGlobalLinkOffset); + NvU32 PRIVATE_FIELD(ipVerIoctrl); + NvU32 PRIVATE_FIELD(ipVerMinion); + NvU32 PRIVATE_FIELD(ioctrlDiscoverySize); + NvU8 PRIVATE_FIELD(numDevices); }; #ifndef __NVOC_CLASS_KernelIoctrl_TYPEDEF__ @@ -137,7 +131,6 @@ #define kioctrlGetMinionEnableDefault_HAL(pGpu, pKernelIoctrl) kioctrlGetMinionEnableDefault_DISPATCH(pGpu, pKernelIoctrl) #define kioctrlMinionConstruct(pGpu, pKernelIoctrl) kioctrlMinionConstruct_DISPATCH(pGpu, pKernelIoctrl) #define kioctrlMinionConstruct_HAL(pGpu, pKernelIoctrl) kioctrlMinionConstruct_DISPATCH(pGpu, pKernelIoctrl) -#define kioctrlReconcileTunableState(pGpu, pEngstate, pTunableState) kioctrlReconcileTunableState_DISPATCH(pGpu, pEngstate, pTunableState) #define kioctrlStateLoad(pGpu, pEngstate, arg0) kioctrlStateLoad_DISPATCH(pGpu, pEngstate, arg0) #define kioctrlStateUnload(pGpu, pEngstate, arg0) kioctrlStateUnload_DISPATCH(pGpu, pEngstate, arg0) #define kioctrlStateInitLocked(pGpu, pEngstate) kioctrlStateInitLocked_DISPATCH(pGpu, pEngstate) @@ -149,12 +142,7 @@ #define kioctrlInitMissing(pGpu, pEngstate) kioctrlInitMissing_DISPATCH(pGpu, pEngstate) #define kioctrlStatePreInitLocked(pGpu, pEngstate) kioctrlStatePreInitLocked_DISPATCH(pGpu, pEngstate) #define kioctrlStatePreInitUnlocked(pGpu, pEngstate) kioctrlStatePreInitUnlocked_DISPATCH(pGpu, pEngstate) -#define kioctrlGetTunableState(pGpu, pEngstate, pTunableState) kioctrlGetTunableState_DISPATCH(pGpu, pEngstate, pTunableState) -#define kioctrlCompareTunableState(pGpu, pEngstate, pTunables1, pTunables2) kioctrlCompareTunableState_DISPATCH(pGpu, pEngstate, pTunables1, pTunables2) -#define kioctrlFreeTunableState(pGpu, pEngstate, pTunableState) kioctrlFreeTunableState_DISPATCH(pGpu, pEngstate, pTunableState) #define kioctrlStatePostLoad(pGpu, pEngstate, arg0) kioctrlStatePostLoad_DISPATCH(pGpu, pEngstate, arg0) -#define kioctrlAllocTunableState(pGpu, pEngstate, ppTunableState) kioctrlAllocTunableState_DISPATCH(pGpu, pEngstate, ppTunableState) -#define kioctrlSetTunableState(pGpu, pEngstate, pTunableState) kioctrlSetTunableState_DISPATCH(pGpu, pEngstate, pTunableState) #define kioctrlIsPresent(pGpu, pEngstate) kioctrlIsPresent_DISPATCH(pGpu, pEngstate) NV_STATUS kioctrlConstructEngine_IMPL(struct OBJGPU *arg0, struct KernelIoctrl *arg1, NvU32 arg2); @@ -182,10 +170,6 @@ return pKernelIoctrl->__kioctrlMinionConstruct__(pGpu, pKernelIoctrl); } -static inline NV_STATUS kioctrlReconcileTunableState_DISPATCH(POBJGPU pGpu, struct KernelIoctrl *pEngstate, void *pTunableState) { - return pEngstate->__kioctrlReconcileTunableState__(pGpu, pEngstate, pTunableState); -} - static inline NV_STATUS kioctrlStateLoad_DISPATCH(POBJGPU pGpu, struct KernelIoctrl *pEngstate, NvU32 arg0) { return pEngstate->__kioctrlStateLoad__(pGpu, pEngstate, arg0); } @@ -230,30 +214,10 @@ return pEngstate->__kioctrlStatePreInitUnlocked__(pGpu, pEngstate); } -static inline NV_STATUS kioctrlGetTunableState_DISPATCH(POBJGPU pGpu, struct KernelIoctrl *pEngstate, void *pTunableState) { - return pEngstate->__kioctrlGetTunableState__(pGpu, pEngstate, pTunableState); -} - -static inline NV_STATUS kioctrlCompareTunableState_DISPATCH(POBJGPU pGpu, struct KernelIoctrl *pEngstate, void *pTunables1, void *pTunables2) { - return pEngstate->__kioctrlCompareTunableState__(pGpu, pEngstate, pTunables1, pTunables2); -} - -static inline void kioctrlFreeTunableState_DISPATCH(POBJGPU pGpu, struct KernelIoctrl *pEngstate, void *pTunableState) { - pEngstate->__kioctrlFreeTunableState__(pGpu, pEngstate, pTunableState); -} - static inline NV_STATUS kioctrlStatePostLoad_DISPATCH(POBJGPU pGpu, struct KernelIoctrl *pEngstate, NvU32 arg0) { return pEngstate->__kioctrlStatePostLoad__(pGpu, pEngstate, arg0); } -static inline NV_STATUS kioctrlAllocTunableState_DISPATCH(POBJGPU pGpu, struct KernelIoctrl *pEngstate, void **ppTunableState) { - return pEngstate->__kioctrlAllocTunableState__(pGpu, pEngstate, ppTunableState); -} - -static inline NV_STATUS kioctrlSetTunableState_DISPATCH(POBJGPU pGpu, struct KernelIoctrl *pEngstate, void *pTunableState) { - return pEngstate->__kioctrlSetTunableState__(pGpu, pEngstate, pTunableState); -} - static inline NvBool kioctrlIsPresent_DISPATCH(POBJGPU pGpu, struct KernelIoctrl *pEngstate) { return pEngstate->__kioctrlIsPresent__(pGpu, pEngstate); } diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/generated/g_kernel_mc_nvoc.c nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_kernel_mc_nvoc.c --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/generated/g_kernel_mc_nvoc.c 2023-10-25 20:27:09.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_kernel_mc_nvoc.c 2024-03-05 22:18:30.000000000 +0000 @@ -74,10 +74,6 @@ return kmcStateLoad(pGpu, (struct KernelMc *)(((unsigned char *)pKernelMc) - __nvoc_rtti_KernelMc_OBJENGSTATE.offset), arg0); } -static NV_STATUS __nvoc_thunk_OBJENGSTATE_kmcReconcileTunableState(POBJGPU pGpu, struct KernelMc *pEngstate, void *pTunableState) { - return engstateReconcileTunableState(pGpu, (struct OBJENGSTATE *)(((unsigned char *)pEngstate) + __nvoc_rtti_KernelMc_OBJENGSTATE.offset), pTunableState); -} - static NV_STATUS __nvoc_thunk_OBJENGSTATE_kmcStateUnload(POBJGPU pGpu, struct KernelMc *pEngstate, NvU32 arg0) { return engstateStateUnload(pGpu, (struct OBJENGSTATE *)(((unsigned char *)pEngstate) + __nvoc_rtti_KernelMc_OBJENGSTATE.offset), arg0); } @@ -114,30 +110,10 @@ return engstateStatePreInitUnlocked(pGpu, (struct OBJENGSTATE *)(((unsigned char *)pEngstate) + __nvoc_rtti_KernelMc_OBJENGSTATE.offset)); } -static NV_STATUS __nvoc_thunk_OBJENGSTATE_kmcGetTunableState(POBJGPU pGpu, struct KernelMc *pEngstate, void *pTunableState) { - return engstateGetTunableState(pGpu, (struct OBJENGSTATE *)(((unsigned char *)pEngstate) + __nvoc_rtti_KernelMc_OBJENGSTATE.offset), pTunableState); -} - -static NV_STATUS __nvoc_thunk_OBJENGSTATE_kmcCompareTunableState(POBJGPU pGpu, struct KernelMc *pEngstate, void *pTunables1, void *pTunables2) { - return engstateCompareTunableState(pGpu, (struct OBJENGSTATE *)(((unsigned char *)pEngstate) + __nvoc_rtti_KernelMc_OBJENGSTATE.offset), pTunables1, pTunables2); -} - -static void __nvoc_thunk_OBJENGSTATE_kmcFreeTunableState(POBJGPU pGpu, struct KernelMc *pEngstate, void *pTunableState) { - engstateFreeTunableState(pGpu, (struct OBJENGSTATE *)(((unsigned char *)pEngstate) + __nvoc_rtti_KernelMc_OBJENGSTATE.offset), pTunableState); -} - static NV_STATUS __nvoc_thunk_OBJENGSTATE_kmcStatePostLoad(POBJGPU pGpu, struct KernelMc *pEngstate, NvU32 arg0) { return engstateStatePostLoad(pGpu, (struct OBJENGSTATE *)(((unsigned char *)pEngstate) + __nvoc_rtti_KernelMc_OBJENGSTATE.offset), arg0); } -static NV_STATUS __nvoc_thunk_OBJENGSTATE_kmcAllocTunableState(POBJGPU pGpu, struct KernelMc *pEngstate, void **ppTunableState) { - return engstateAllocTunableState(pGpu, (struct OBJENGSTATE *)(((unsigned char *)pEngstate) + __nvoc_rtti_KernelMc_OBJENGSTATE.offset), ppTunableState); -} - -static NV_STATUS __nvoc_thunk_OBJENGSTATE_kmcSetTunableState(POBJGPU pGpu, struct KernelMc *pEngstate, void *pTunableState) { - return engstateSetTunableState(pGpu, (struct OBJENGSTATE *)(((unsigned char *)pEngstate) + __nvoc_rtti_KernelMc_OBJENGSTATE.offset), pTunableState); -} - static NV_STATUS __nvoc_thunk_OBJENGSTATE_kmcConstructEngine(POBJGPU pGpu, struct KernelMc *pEngstate, ENGDESCRIPTOR arg0) { return engstateConstructEngine(pGpu, (struct OBJENGSTATE *)(((unsigned char *)pEngstate) + __nvoc_rtti_KernelMc_OBJENGSTATE.offset), arg0); } @@ -198,7 +174,7 @@ { pThis->__kmcWritePmcEnableReg__ = &kmcWritePmcEnableReg_GK104; } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x11f0fc00UL) )) /* ChipHal: GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 | GH100 */ + else { pThis->__kmcWritePmcEnableReg__ = &kmcWritePmcEnableReg_GA100; } @@ -208,7 +184,7 @@ { pThis->__kmcReadPmcEnableReg__ = &kmcReadPmcEnableReg_GK104; } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x11f0fc00UL) )) /* ChipHal: GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 | GH100 */ + else { pThis->__kmcReadPmcEnableReg__ = &kmcReadPmcEnableReg_GA100; } @@ -217,8 +193,6 @@ pThis->__nvoc_base_OBJENGSTATE.__engstateStateLoad__ = &__nvoc_thunk_KernelMc_engstateStateLoad; - pThis->__kmcReconcileTunableState__ = &__nvoc_thunk_OBJENGSTATE_kmcReconcileTunableState; - pThis->__kmcStateUnload__ = &__nvoc_thunk_OBJENGSTATE_kmcStateUnload; pThis->__kmcStatePreLoad__ = &__nvoc_thunk_OBJENGSTATE_kmcStatePreLoad; @@ -237,18 +211,8 @@ pThis->__kmcStatePreInitUnlocked__ = &__nvoc_thunk_OBJENGSTATE_kmcStatePreInitUnlocked; - pThis->__kmcGetTunableState__ = &__nvoc_thunk_OBJENGSTATE_kmcGetTunableState; - - pThis->__kmcCompareTunableState__ = &__nvoc_thunk_OBJENGSTATE_kmcCompareTunableState; - - pThis->__kmcFreeTunableState__ = &__nvoc_thunk_OBJENGSTATE_kmcFreeTunableState; - pThis->__kmcStatePostLoad__ = &__nvoc_thunk_OBJENGSTATE_kmcStatePostLoad; - pThis->__kmcAllocTunableState__ = &__nvoc_thunk_OBJENGSTATE_kmcAllocTunableState; - - pThis->__kmcSetTunableState__ = &__nvoc_thunk_OBJENGSTATE_kmcSetTunableState; - pThis->__kmcConstructEngine__ = &__nvoc_thunk_OBJENGSTATE_kmcConstructEngine; pThis->__kmcIsPresent__ = &__nvoc_thunk_OBJENGSTATE_kmcIsPresent; @@ -273,13 +237,16 @@ KernelMc *pThis; RmHalspecOwner *pRmhalspecowner; - pThis = portMemAllocNonPaged(sizeof(KernelMc)); - if (pThis == NULL) return NV_ERR_NO_MEMORY; + status = __nvoc_handleObjCreateMemAlloc(createFlags, sizeof(KernelMc), (void**)&pThis, (void**)ppThis); + if (status != NV_OK) + return status; portMemSet(pThis, 0, sizeof(KernelMc)); __nvoc_initRtti(staticCast(pThis, Dynamic), &__nvoc_class_def_KernelMc); + pThis->__nvoc_base_OBJENGSTATE.__nvoc_base_Object.createFlags = createFlags; + if (pParent != NULL && !(createFlags & NVOC_OBJ_CREATE_FLAGS_PARENT_HALSPEC_ONLY)) { pParentObj = dynamicCast(pParent, Object); @@ -299,11 +266,17 @@ if (status != NV_OK) goto __nvoc_objCreate_KernelMc_cleanup; *ppThis = pThis; + return NV_OK; __nvoc_objCreate_KernelMc_cleanup: // do not call destructors here since the constructor already called them - portMemFree(pThis); + if (createFlags & NVOC_OBJ_CREATE_FLAGS_IN_PLACE_CONSTRUCT) + portMemSet(pThis, 0, sizeof(KernelMc)); + else + portMemFree(pThis); + + // coverity[leaked_storage:FALSE] return status; } diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/generated/g_kernel_mc_nvoc.h nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_kernel_mc_nvoc.h --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/generated/g_kernel_mc_nvoc.h 2023-10-25 20:27:09.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_kernel_mc_nvoc.h 2024-03-05 22:18:30.000000000 +0000 @@ -7,7 +7,7 @@ #endif /* - * SPDX-FileCopyrightText: Copyright (c) 2021-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2021-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -66,7 +66,6 @@ NV_STATUS (*__kmcStateLoad__)(struct OBJGPU *, struct KernelMc *, NvU32); NV_STATUS (*__kmcWritePmcEnableReg__)(struct OBJGPU *, struct KernelMc *, NvU32, NvBool, NvBool); NvU32 (*__kmcReadPmcEnableReg__)(struct OBJGPU *, struct KernelMc *, NvBool); - NV_STATUS (*__kmcReconcileTunableState__)(POBJGPU, struct KernelMc *, void *); NV_STATUS (*__kmcStateUnload__)(POBJGPU, struct KernelMc *, NvU32); NV_STATUS (*__kmcStatePreLoad__)(POBJGPU, struct KernelMc *, NvU32); NV_STATUS (*__kmcStatePostUnload__)(POBJGPU, struct KernelMc *, NvU32); @@ -76,12 +75,7 @@ void (*__kmcInitMissing__)(POBJGPU, struct KernelMc *); NV_STATUS (*__kmcStatePreInitLocked__)(POBJGPU, struct KernelMc *); NV_STATUS (*__kmcStatePreInitUnlocked__)(POBJGPU, struct KernelMc *); - NV_STATUS (*__kmcGetTunableState__)(POBJGPU, struct KernelMc *, void *); - NV_STATUS (*__kmcCompareTunableState__)(POBJGPU, struct KernelMc *, void *, void *); - void (*__kmcFreeTunableState__)(POBJGPU, struct KernelMc *, void *); NV_STATUS (*__kmcStatePostLoad__)(POBJGPU, struct KernelMc *, NvU32); - NV_STATUS (*__kmcAllocTunableState__)(POBJGPU, struct KernelMc *, void **); - NV_STATUS (*__kmcSetTunableState__)(POBJGPU, struct KernelMc *, void *); NV_STATUS (*__kmcConstructEngine__)(POBJGPU, struct KernelMc *, ENGDESCRIPTOR); NvBool (*__kmcIsPresent__)(POBJGPU, struct KernelMc *); LATENCY_TIMER_CONTROL LatencyTimerControl; @@ -123,7 +117,6 @@ #define kmcWritePmcEnableReg_HAL(pGpu, pKernelMc, arg0, arg1, arg2) kmcWritePmcEnableReg_DISPATCH(pGpu, pKernelMc, arg0, arg1, arg2) #define kmcReadPmcEnableReg(pGpu, pKernelMc, arg0) kmcReadPmcEnableReg_DISPATCH(pGpu, pKernelMc, arg0) #define kmcReadPmcEnableReg_HAL(pGpu, pKernelMc, arg0) kmcReadPmcEnableReg_DISPATCH(pGpu, pKernelMc, arg0) -#define kmcReconcileTunableState(pGpu, pEngstate, pTunableState) kmcReconcileTunableState_DISPATCH(pGpu, pEngstate, pTunableState) #define kmcStateUnload(pGpu, pEngstate, arg0) kmcStateUnload_DISPATCH(pGpu, pEngstate, arg0) #define kmcStatePreLoad(pGpu, pEngstate, arg0) kmcStatePreLoad_DISPATCH(pGpu, pEngstate, arg0) #define kmcStatePostUnload(pGpu, pEngstate, arg0) kmcStatePostUnload_DISPATCH(pGpu, pEngstate, arg0) @@ -133,12 +126,7 @@ #define kmcInitMissing(pGpu, pEngstate) kmcInitMissing_DISPATCH(pGpu, pEngstate) #define kmcStatePreInitLocked(pGpu, pEngstate) kmcStatePreInitLocked_DISPATCH(pGpu, pEngstate) #define kmcStatePreInitUnlocked(pGpu, pEngstate) kmcStatePreInitUnlocked_DISPATCH(pGpu, pEngstate) -#define kmcGetTunableState(pGpu, pEngstate, pTunableState) kmcGetTunableState_DISPATCH(pGpu, pEngstate, pTunableState) -#define kmcCompareTunableState(pGpu, pEngstate, pTunables1, pTunables2) kmcCompareTunableState_DISPATCH(pGpu, pEngstate, pTunables1, pTunables2) -#define kmcFreeTunableState(pGpu, pEngstate, pTunableState) kmcFreeTunableState_DISPATCH(pGpu, pEngstate, pTunableState) #define kmcStatePostLoad(pGpu, pEngstate, arg0) kmcStatePostLoad_DISPATCH(pGpu, pEngstate, arg0) -#define kmcAllocTunableState(pGpu, pEngstate, ppTunableState) kmcAllocTunableState_DISPATCH(pGpu, pEngstate, ppTunableState) -#define kmcSetTunableState(pGpu, pEngstate, pTunableState) kmcSetTunableState_DISPATCH(pGpu, pEngstate, pTunableState) #define kmcConstructEngine(pGpu, pEngstate, arg0) kmcConstructEngine_DISPATCH(pGpu, pEngstate, arg0) #define kmcIsPresent(pGpu, pEngstate) kmcIsPresent_DISPATCH(pGpu, pEngstate) NV_STATUS kmcPrepareForXVEReset_GK104(struct OBJGPU *pGpu, struct KernelMc *pKernelMc); @@ -197,10 +185,6 @@ return pKernelMc->__kmcReadPmcEnableReg__(pGpu, pKernelMc, arg0); } -static inline NV_STATUS kmcReconcileTunableState_DISPATCH(POBJGPU pGpu, struct KernelMc *pEngstate, void *pTunableState) { - return pEngstate->__kmcReconcileTunableState__(pGpu, pEngstate, pTunableState); -} - static inline NV_STATUS kmcStateUnload_DISPATCH(POBJGPU pGpu, struct KernelMc *pEngstate, NvU32 arg0) { return pEngstate->__kmcStateUnload__(pGpu, pEngstate, arg0); } @@ -237,30 +221,10 @@ return pEngstate->__kmcStatePreInitUnlocked__(pGpu, pEngstate); } -static inline NV_STATUS kmcGetTunableState_DISPATCH(POBJGPU pGpu, struct KernelMc *pEngstate, void *pTunableState) { - return pEngstate->__kmcGetTunableState__(pGpu, pEngstate, pTunableState); -} - -static inline NV_STATUS kmcCompareTunableState_DISPATCH(POBJGPU pGpu, struct KernelMc *pEngstate, void *pTunables1, void *pTunables2) { - return pEngstate->__kmcCompareTunableState__(pGpu, pEngstate, pTunables1, pTunables2); -} - -static inline void kmcFreeTunableState_DISPATCH(POBJGPU pGpu, struct KernelMc *pEngstate, void *pTunableState) { - pEngstate->__kmcFreeTunableState__(pGpu, pEngstate, pTunableState); -} - static inline NV_STATUS kmcStatePostLoad_DISPATCH(POBJGPU pGpu, struct KernelMc *pEngstate, NvU32 arg0) { return pEngstate->__kmcStatePostLoad__(pGpu, pEngstate, arg0); } -static inline NV_STATUS kmcAllocTunableState_DISPATCH(POBJGPU pGpu, struct KernelMc *pEngstate, void **ppTunableState) { - return pEngstate->__kmcAllocTunableState__(pGpu, pEngstate, ppTunableState); -} - -static inline NV_STATUS kmcSetTunableState_DISPATCH(POBJGPU pGpu, struct KernelMc *pEngstate, void *pTunableState) { - return pEngstate->__kmcSetTunableState__(pGpu, pEngstate, pTunableState); -} - static inline NV_STATUS kmcConstructEngine_DISPATCH(POBJGPU pGpu, struct KernelMc *pEngstate, ENGDESCRIPTOR arg0) { return pEngstate->__kmcConstructEngine__(pGpu, pEngstate, arg0); } diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/generated/g_kernel_mig_manager_nvoc.c nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_kernel_mig_manager_nvoc.c --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/generated/g_kernel_mig_manager_nvoc.c 2023-10-25 20:27:09.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_kernel_mig_manager_nvoc.c 2024-03-05 22:18:30.000000000 +0000 @@ -78,10 +78,6 @@ return kmigmgrStateUnload(arg0, (struct KernelMIGManager *)(((unsigned char *)arg1) - __nvoc_rtti_KernelMIGManager_OBJENGSTATE.offset), flags); } -static NV_STATUS __nvoc_thunk_OBJENGSTATE_kmigmgrReconcileTunableState(POBJGPU pGpu, struct KernelMIGManager *pEngstate, void *pTunableState) { - return engstateReconcileTunableState(pGpu, (struct OBJENGSTATE *)(((unsigned char *)pEngstate) + __nvoc_rtti_KernelMIGManager_OBJENGSTATE.offset), pTunableState); -} - static NV_STATUS __nvoc_thunk_OBJENGSTATE_kmigmgrStateLoad(POBJGPU pGpu, struct KernelMIGManager *pEngstate, NvU32 arg0) { return engstateStateLoad(pGpu, (struct OBJENGSTATE *)(((unsigned char *)pEngstate) + __nvoc_rtti_KernelMIGManager_OBJENGSTATE.offset), arg0); } @@ -118,30 +114,10 @@ return engstateStatePreInitUnlocked(pGpu, (struct OBJENGSTATE *)(((unsigned char *)pEngstate) + __nvoc_rtti_KernelMIGManager_OBJENGSTATE.offset)); } -static NV_STATUS __nvoc_thunk_OBJENGSTATE_kmigmgrGetTunableState(POBJGPU pGpu, struct KernelMIGManager *pEngstate, void *pTunableState) { - return engstateGetTunableState(pGpu, (struct OBJENGSTATE *)(((unsigned char *)pEngstate) + __nvoc_rtti_KernelMIGManager_OBJENGSTATE.offset), pTunableState); -} - -static NV_STATUS __nvoc_thunk_OBJENGSTATE_kmigmgrCompareTunableState(POBJGPU pGpu, struct KernelMIGManager *pEngstate, void *pTunables1, void *pTunables2) { - return engstateCompareTunableState(pGpu, (struct OBJENGSTATE *)(((unsigned char *)pEngstate) + __nvoc_rtti_KernelMIGManager_OBJENGSTATE.offset), pTunables1, pTunables2); -} - -static void __nvoc_thunk_OBJENGSTATE_kmigmgrFreeTunableState(POBJGPU pGpu, struct KernelMIGManager *pEngstate, void *pTunableState) { - engstateFreeTunableState(pGpu, (struct OBJENGSTATE *)(((unsigned char *)pEngstate) + __nvoc_rtti_KernelMIGManager_OBJENGSTATE.offset), pTunableState); -} - static NV_STATUS __nvoc_thunk_OBJENGSTATE_kmigmgrStatePostLoad(POBJGPU pGpu, struct KernelMIGManager *pEngstate, NvU32 arg0) { return engstateStatePostLoad(pGpu, (struct OBJENGSTATE *)(((unsigned char *)pEngstate) + __nvoc_rtti_KernelMIGManager_OBJENGSTATE.offset), arg0); } -static NV_STATUS __nvoc_thunk_OBJENGSTATE_kmigmgrAllocTunableState(POBJGPU pGpu, struct KernelMIGManager *pEngstate, void **ppTunableState) { - return engstateAllocTunableState(pGpu, (struct OBJENGSTATE *)(((unsigned char *)pEngstate) + __nvoc_rtti_KernelMIGManager_OBJENGSTATE.offset), ppTunableState); -} - -static NV_STATUS __nvoc_thunk_OBJENGSTATE_kmigmgrSetTunableState(POBJGPU pGpu, struct KernelMIGManager *pEngstate, void *pTunableState) { - return engstateSetTunableState(pGpu, (struct OBJENGSTATE *)(((unsigned char *)pEngstate) + __nvoc_rtti_KernelMIGManager_OBJENGSTATE.offset), pTunableState); -} - static NvBool __nvoc_thunk_OBJENGSTATE_kmigmgrIsPresent(POBJGPU pGpu, struct KernelMIGManager *pEngstate) { return engstateIsPresent(pGpu, (struct OBJENGSTATE *)(((unsigned char *)pEngstate) + __nvoc_rtti_KernelMIGManager_OBJENGSTATE.offset)); } @@ -209,23 +185,20 @@ { pThis->__kmigmgrCreateGPUInstanceCheck__ = &kmigmgrCreateGPUInstanceCheck_GA100; } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x01f0fbe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 */ + else { pThis->__kmigmgrCreateGPUInstanceCheck__ = &kmigmgrCreateGPUInstanceCheck_46f6a7; } // Hal function -- kmigmgrIsDevinitMIGBitSet - if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000002UL) )) /* RmVariantHal: PF_KERNEL_ONLY */ + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x00000400UL) )) /* ChipHal: GA100 */ + { + pThis->__kmigmgrIsDevinitMIGBitSet__ = &kmigmgrIsDevinitMIGBitSet_GA100; + } + // default + else { - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x00000400UL) )) /* ChipHal: GA100 */ - { - pThis->__kmigmgrIsDevinitMIGBitSet__ = &kmigmgrIsDevinitMIGBitSet_GA100; - } - // default - else - { - pThis->__kmigmgrIsDevinitMIGBitSet__ = &kmigmgrIsDevinitMIGBitSet_491d52; - } + pThis->__kmigmgrIsDevinitMIGBitSet__ = &kmigmgrIsDevinitMIGBitSet_491d52; } // Hal function -- kmigmgrIsGPUInstanceCombinationValid @@ -263,7 +236,7 @@ { pThis->__kmigmgrIsMemoryPartitioningRequested__ = &kmigmgrIsMemoryPartitioningRequested_GA100; } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x01f0fbe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 */ + else { pThis->__kmigmgrIsMemoryPartitioningRequested__ = &kmigmgrIsMemoryPartitioningRequested_491d52; } @@ -273,22 +246,19 @@ { pThis->__kmigmgrIsMemoryPartitioningNeeded__ = &kmigmgrIsMemoryPartitioningNeeded_GA100; } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x01f0fbe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 */ + else { pThis->__kmigmgrIsMemoryPartitioningNeeded__ = &kmigmgrIsMemoryPartitioningNeeded_491d52; } // Hal function -- kmigmgrMemSizeFlagToSwizzIdRange - if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000002UL) )) /* RmVariantHal: PF_KERNEL_ONLY */ + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000400UL) )) /* ChipHal: GA100 | GH100 */ { - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000400UL) )) /* ChipHal: GA100 | GH100 */ - { - pThis->__kmigmgrMemSizeFlagToSwizzIdRange__ = &kmigmgrMemSizeFlagToSwizzIdRange_GA100; - } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x01f0fbe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 */ - { - pThis->__kmigmgrMemSizeFlagToSwizzIdRange__ = &kmigmgrMemSizeFlagToSwizzIdRange_d64cd6; - } + pThis->__kmigmgrMemSizeFlagToSwizzIdRange__ = &kmigmgrMemSizeFlagToSwizzIdRange_GA100; + } + else + { + pThis->__kmigmgrMemSizeFlagToSwizzIdRange__ = &kmigmgrMemSizeFlagToSwizzIdRange_d64cd6; } pThis->__nvoc_base_OBJENGSTATE.__engstateConstructEngine__ = &__nvoc_thunk_KernelMIGManager_engstateConstructEngine; @@ -297,8 +267,6 @@ pThis->__nvoc_base_OBJENGSTATE.__engstateStateUnload__ = &__nvoc_thunk_KernelMIGManager_engstateStateUnload; - pThis->__kmigmgrReconcileTunableState__ = &__nvoc_thunk_OBJENGSTATE_kmigmgrReconcileTunableState; - pThis->__kmigmgrStateLoad__ = &__nvoc_thunk_OBJENGSTATE_kmigmgrStateLoad; pThis->__kmigmgrStatePreLoad__ = &__nvoc_thunk_OBJENGSTATE_kmigmgrStatePreLoad; @@ -317,18 +285,8 @@ pThis->__kmigmgrStatePreInitUnlocked__ = &__nvoc_thunk_OBJENGSTATE_kmigmgrStatePreInitUnlocked; - pThis->__kmigmgrGetTunableState__ = &__nvoc_thunk_OBJENGSTATE_kmigmgrGetTunableState; - - pThis->__kmigmgrCompareTunableState__ = &__nvoc_thunk_OBJENGSTATE_kmigmgrCompareTunableState; - - pThis->__kmigmgrFreeTunableState__ = &__nvoc_thunk_OBJENGSTATE_kmigmgrFreeTunableState; - pThis->__kmigmgrStatePostLoad__ = &__nvoc_thunk_OBJENGSTATE_kmigmgrStatePostLoad; - pThis->__kmigmgrAllocTunableState__ = &__nvoc_thunk_OBJENGSTATE_kmigmgrAllocTunableState; - - pThis->__kmigmgrSetTunableState__ = &__nvoc_thunk_OBJENGSTATE_kmigmgrSetTunableState; - pThis->__kmigmgrIsPresent__ = &__nvoc_thunk_OBJENGSTATE_kmigmgrIsPresent; } @@ -351,13 +309,16 @@ KernelMIGManager *pThis; RmHalspecOwner *pRmhalspecowner; - pThis = portMemAllocNonPaged(sizeof(KernelMIGManager)); - if (pThis == NULL) return NV_ERR_NO_MEMORY; + status = __nvoc_handleObjCreateMemAlloc(createFlags, sizeof(KernelMIGManager), (void**)&pThis, (void**)ppThis); + if (status != NV_OK) + return status; portMemSet(pThis, 0, sizeof(KernelMIGManager)); __nvoc_initRtti(staticCast(pThis, Dynamic), &__nvoc_class_def_KernelMIGManager); + pThis->__nvoc_base_OBJENGSTATE.__nvoc_base_Object.createFlags = createFlags; + if (pParent != NULL && !(createFlags & NVOC_OBJ_CREATE_FLAGS_PARENT_HALSPEC_ONLY)) { pParentObj = dynamicCast(pParent, Object); @@ -377,11 +338,17 @@ if (status != NV_OK) goto __nvoc_objCreate_KernelMIGManager_cleanup; *ppThis = pThis; + return NV_OK; __nvoc_objCreate_KernelMIGManager_cleanup: // do not call destructors here since the constructor already called them - portMemFree(pThis); + if (createFlags & NVOC_OBJ_CREATE_FLAGS_IN_PLACE_CONSTRUCT) + portMemSet(pThis, 0, sizeof(KernelMIGManager)); + else + portMemFree(pThis); + + // coverity[leaked_storage:FALSE] return status; } diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/generated/g_kernel_mig_manager_nvoc.h nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_kernel_mig_manager_nvoc.h --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/generated/g_kernel_mig_manager_nvoc.h 2023-10-25 20:27:09.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_kernel_mig_manager_nvoc.h 2024-03-05 22:18:30.000000000 +0000 @@ -7,7 +7,7 @@ #endif /* - * SPDX-FileCopyrightText: Copyright (c) 2021-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2021-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -56,13 +56,13 @@ #define IS_MIG_IN_USE(pGpu) (((pGpu) != NULL) && (GPU_GET_KERNEL_MIG_MANAGER(pGpu) != NULL) && \ kmigmgrIsMIGGpuInstancingEnabled((pGpu), GPU_GET_KERNEL_MIG_MANAGER(pGpu))) -#define FOR_EACH_VALID_GPU_INSTANCE(pGpu, pKernelMIGManager, pLocal) \ - { \ - NvU32 i; \ - for (i = 0; i < KMIGMGR_MAX_GPU_INSTANCES; ++i) \ - { \ - (pLocal) = kmigmgrGetMIGGpuInstanceSlot((pGpu), (pKernelMIGManager), i);\ - if (((pLocal) == NULL) || !(pLocal)->bValid) \ +#define FOR_EACH_VALID_GPU_INSTANCE(pGpu, pKernelMIGManager, pLocal) \ + { \ + NvU32 i; \ + for (i = 0; i < KMIGMGR_MAX_GPU_INSTANCES; ++i) \ + { \ + (pLocal) = kmigmgrGetMIGGpuInstanceSlot((pGpu), (pKernelMIGManager), i); \ + if (((pLocal) == NULL) || !(pLocal)->bValid) \ continue; #define FOR_EACH_VALID_GPU_INSTANCE_END() \ @@ -79,7 +79,7 @@ #define KMIGMGR_CTSID_INVALID 0xFFFFFFFFUL #define KMIGMGR_SPAN_OFFSET_INVALID KMIGMGR_CTSID_INVALID -#define KMIGMGR_INSTANCE_ATTRIBUTION_ID_INVALID \ +#define KMIGMGR_INSTANCE_ATTRIBUTION_ID_INVALID \ ((KMIGMGR_MAX_GPU_SWIZZID * KMIGMGR_MAX_GPU_SWIZZID) + \ KMIGMGR_MAX_COMPUTE_INSTANCES) @@ -125,6 +125,11 @@ NvU32 gpcCount; /*! + * Number of GFX GPCs associated with this instance. This should be a subset of gpcs included in gpcCount. + */ + NvU32 gfxGpcCount; + + /*! * VEID start offset for this instance */ NvU32 veidOffset; @@ -238,7 +243,7 @@ * instance ID support. (bug 2938187) * TYPE_REQUEST_AT_SPAN * Parameter refers to request data passed in via EXEC_PARTITIONS_CREATE ctrl - * call. All resources claimed by new instance are attempt to be claimed by + * call. All resources claimed by new instance are attempt to be claimed by * the RM allocater starting at the specified resource span. */ typedef struct KMIGMGR_CREATE_COMPUTE_INSTANCE_PARAMS @@ -379,10 +384,10 @@ * GR to CTS ID mapping */ NvU32 grCtsIdMap[KMIGMGR_MAX_COMPUTE_INSTANCES]; - + /*! * Mask tracking which compute spans are currently in-use - */ + */ NvU32 spanInUseMask; } KERNEL_MIG_GPU_INSTANCE; @@ -473,7 +478,6 @@ NvBool (*__kmigmgrIsMemoryPartitioningRequested__)(OBJGPU *, struct KernelMIGManager *, NvU32); NvBool (*__kmigmgrIsMemoryPartitioningNeeded__)(OBJGPU *, struct KernelMIGManager *, NvU32); struct NV_RANGE (*__kmigmgrMemSizeFlagToSwizzIdRange__)(OBJGPU *, struct KernelMIGManager *, NvU32); - NV_STATUS (*__kmigmgrReconcileTunableState__)(POBJGPU, struct KernelMIGManager *, void *); NV_STATUS (*__kmigmgrStateLoad__)(POBJGPU, struct KernelMIGManager *, NvU32); NV_STATUS (*__kmigmgrStatePreLoad__)(POBJGPU, struct KernelMIGManager *, NvU32); NV_STATUS (*__kmigmgrStatePostUnload__)(POBJGPU, struct KernelMIGManager *, NvU32); @@ -483,12 +487,45 @@ void (*__kmigmgrInitMissing__)(POBJGPU, struct KernelMIGManager *); NV_STATUS (*__kmigmgrStatePreInitLocked__)(POBJGPU, struct KernelMIGManager *); NV_STATUS (*__kmigmgrStatePreInitUnlocked__)(POBJGPU, struct KernelMIGManager *); - NV_STATUS (*__kmigmgrGetTunableState__)(POBJGPU, struct KernelMIGManager *, void *); - NV_STATUS (*__kmigmgrCompareTunableState__)(POBJGPU, struct KernelMIGManager *, void *, void *); - void (*__kmigmgrFreeTunableState__)(POBJGPU, struct KernelMIGManager *, void *); NV_STATUS (*__kmigmgrStatePostLoad__)(POBJGPU, struct KernelMIGManager *, NvU32); - NV_STATUS (*__kmigmgrAllocTunableState__)(POBJGPU, struct KernelMIGManager *, void **); - NV_STATUS (*__kmigmgrSetTunableState__)(POBJGPU, struct KernelMIGManager *, void *); + NvBool (*__kmigmgrIsPresent__)(POBJGPU, struct KernelMIGManager *); + NvBool PRIVATE_FIELD(bIsA100ReducedConfig); + KERNEL_MIG_MANAGER_PRIVATE_DATA *PRIVATE_FIELD(pPrivate); + KERNEL_MIG_GPU_INSTANCE PRIVATE_FIELD(kernelMIGGpuInstance)[8]; + NvBool PRIVATE_FIELD(bMIGEnabled); + NvU64 PRIVATE_FIELD(swizzIdInUseMask); + NvBool PRIVATE_FIELD(bRestoreWatchdog); + NvBool PRIVATE_FIELD(bReenableWatchdog); + union ENGTYPE_BIT_VECTOR PRIVATE_FIELD(partitionableEnginesInUse); + NvBool PRIVATE_FIELD(bDeviceProfilingInUse); + NvBool PRIVATE_FIELD(bMIGAutoOnlineEnabled); +}; +struct KernelMIGManager_PRIVATE { + const struct NVOC_RTTI *__nvoc_rtti; + struct OBJENGSTATE __nvoc_base_OBJENGSTATE; + struct Object *__nvoc_pbase_Object; + struct OBJENGSTATE *__nvoc_pbase_OBJENGSTATE; + struct KernelMIGManager *__nvoc_pbase_KernelMIGManager; + NV_STATUS (*__kmigmgrConstructEngine__)(OBJGPU *, struct KernelMIGManager *, ENGDESCRIPTOR); + NV_STATUS (*__kmigmgrStateInitLocked__)(OBJGPU *, struct KernelMIGManager *); + NV_STATUS (*__kmigmgrStateUnload__)(OBJGPU *, struct KernelMIGManager *, NvU32); + NV_STATUS (*__kmigmgrCreateGPUInstanceCheck__)(OBJGPU *, struct KernelMIGManager *, NvBool); + NvBool (*__kmigmgrIsDevinitMIGBitSet__)(OBJGPU *, struct KernelMIGManager *); + NvBool (*__kmigmgrIsGPUInstanceCombinationValid__)(OBJGPU *, struct KernelMIGManager *, NvU32); + NvBool (*__kmigmgrIsGPUInstanceFlagValid__)(OBJGPU *, struct KernelMIGManager *, NvU32); + NvBool (*__kmigmgrIsMemoryPartitioningRequested__)(OBJGPU *, struct KernelMIGManager *, NvU32); + NvBool (*__kmigmgrIsMemoryPartitioningNeeded__)(OBJGPU *, struct KernelMIGManager *, NvU32); + struct NV_RANGE (*__kmigmgrMemSizeFlagToSwizzIdRange__)(OBJGPU *, struct KernelMIGManager *, NvU32); + NV_STATUS (*__kmigmgrStateLoad__)(POBJGPU, struct KernelMIGManager *, NvU32); + NV_STATUS (*__kmigmgrStatePreLoad__)(POBJGPU, struct KernelMIGManager *, NvU32); + NV_STATUS (*__kmigmgrStatePostUnload__)(POBJGPU, struct KernelMIGManager *, NvU32); + void (*__kmigmgrStateDestroy__)(POBJGPU, struct KernelMIGManager *); + NV_STATUS (*__kmigmgrStatePreUnload__)(POBJGPU, struct KernelMIGManager *, NvU32); + NV_STATUS (*__kmigmgrStateInitUnlocked__)(POBJGPU, struct KernelMIGManager *); + void (*__kmigmgrInitMissing__)(POBJGPU, struct KernelMIGManager *); + NV_STATUS (*__kmigmgrStatePreInitLocked__)(POBJGPU, struct KernelMIGManager *); + NV_STATUS (*__kmigmgrStatePreInitUnlocked__)(POBJGPU, struct KernelMIGManager *); + NV_STATUS (*__kmigmgrStatePostLoad__)(POBJGPU, struct KernelMIGManager *, NvU32); NvBool (*__kmigmgrIsPresent__)(POBJGPU, struct KernelMIGManager *); NvBool bIsA100ReducedConfig; KERNEL_MIG_MANAGER_PRIVATE_DATA *pPrivate; @@ -549,7 +586,6 @@ #define kmigmgrIsMemoryPartitioningNeeded_HAL(arg0, arg1, swizzId) kmigmgrIsMemoryPartitioningNeeded_DISPATCH(arg0, arg1, swizzId) #define kmigmgrMemSizeFlagToSwizzIdRange(arg0, arg1, memSizeFlag) kmigmgrMemSizeFlagToSwizzIdRange_DISPATCH(arg0, arg1, memSizeFlag) #define kmigmgrMemSizeFlagToSwizzIdRange_HAL(arg0, arg1, memSizeFlag) kmigmgrMemSizeFlagToSwizzIdRange_DISPATCH(arg0, arg1, memSizeFlag) -#define kmigmgrReconcileTunableState(pGpu, pEngstate, pTunableState) kmigmgrReconcileTunableState_DISPATCH(pGpu, pEngstate, pTunableState) #define kmigmgrStateLoad(pGpu, pEngstate, arg0) kmigmgrStateLoad_DISPATCH(pGpu, pEngstate, arg0) #define kmigmgrStatePreLoad(pGpu, pEngstate, arg0) kmigmgrStatePreLoad_DISPATCH(pGpu, pEngstate, arg0) #define kmigmgrStatePostUnload(pGpu, pEngstate, arg0) kmigmgrStatePostUnload_DISPATCH(pGpu, pEngstate, arg0) @@ -559,12 +595,7 @@ #define kmigmgrInitMissing(pGpu, pEngstate) kmigmgrInitMissing_DISPATCH(pGpu, pEngstate) #define kmigmgrStatePreInitLocked(pGpu, pEngstate) kmigmgrStatePreInitLocked_DISPATCH(pGpu, pEngstate) #define kmigmgrStatePreInitUnlocked(pGpu, pEngstate) kmigmgrStatePreInitUnlocked_DISPATCH(pGpu, pEngstate) -#define kmigmgrGetTunableState(pGpu, pEngstate, pTunableState) kmigmgrGetTunableState_DISPATCH(pGpu, pEngstate, pTunableState) -#define kmigmgrCompareTunableState(pGpu, pEngstate, pTunables1, pTunables2) kmigmgrCompareTunableState_DISPATCH(pGpu, pEngstate, pTunables1, pTunables2) -#define kmigmgrFreeTunableState(pGpu, pEngstate, pTunableState) kmigmgrFreeTunableState_DISPATCH(pGpu, pEngstate, pTunableState) #define kmigmgrStatePostLoad(pGpu, pEngstate, arg0) kmigmgrStatePostLoad_DISPATCH(pGpu, pEngstate, arg0) -#define kmigmgrAllocTunableState(pGpu, pEngstate, ppTunableState) kmigmgrAllocTunableState_DISPATCH(pGpu, pEngstate, ppTunableState) -#define kmigmgrSetTunableState(pGpu, pEngstate, pTunableState) kmigmgrSetTunableState_DISPATCH(pGpu, pEngstate, pTunableState) #define kmigmgrIsPresent(pGpu, pEngstate) kmigmgrIsPresent_DISPATCH(pGpu, pEngstate) NV_STATUS kmigmgrLoadStaticInfo_KERNEL(OBJGPU *arg0, struct KernelMIGManager *arg1); @@ -832,10 +863,6 @@ return arg1->__kmigmgrMemSizeFlagToSwizzIdRange__(arg0, arg1, memSizeFlag); } -static inline NV_STATUS kmigmgrReconcileTunableState_DISPATCH(POBJGPU pGpu, struct KernelMIGManager *pEngstate, void *pTunableState) { - return pEngstate->__kmigmgrReconcileTunableState__(pGpu, pEngstate, pTunableState); -} - static inline NV_STATUS kmigmgrStateLoad_DISPATCH(POBJGPU pGpu, struct KernelMIGManager *pEngstate, NvU32 arg0) { return pEngstate->__kmigmgrStateLoad__(pGpu, pEngstate, arg0); } @@ -872,30 +899,10 @@ return pEngstate->__kmigmgrStatePreInitUnlocked__(pGpu, pEngstate); } -static inline NV_STATUS kmigmgrGetTunableState_DISPATCH(POBJGPU pGpu, struct KernelMIGManager *pEngstate, void *pTunableState) { - return pEngstate->__kmigmgrGetTunableState__(pGpu, pEngstate, pTunableState); -} - -static inline NV_STATUS kmigmgrCompareTunableState_DISPATCH(POBJGPU pGpu, struct KernelMIGManager *pEngstate, void *pTunables1, void *pTunables2) { - return pEngstate->__kmigmgrCompareTunableState__(pGpu, pEngstate, pTunables1, pTunables2); -} - -static inline void kmigmgrFreeTunableState_DISPATCH(POBJGPU pGpu, struct KernelMIGManager *pEngstate, void *pTunableState) { - pEngstate->__kmigmgrFreeTunableState__(pGpu, pEngstate, pTunableState); -} - static inline NV_STATUS kmigmgrStatePostLoad_DISPATCH(POBJGPU pGpu, struct KernelMIGManager *pEngstate, NvU32 arg0) { return pEngstate->__kmigmgrStatePostLoad__(pGpu, pEngstate, arg0); } -static inline NV_STATUS kmigmgrAllocTunableState_DISPATCH(POBJGPU pGpu, struct KernelMIGManager *pEngstate, void **ppTunableState) { - return pEngstate->__kmigmgrAllocTunableState__(pGpu, pEngstate, ppTunableState); -} - -static inline NV_STATUS kmigmgrSetTunableState_DISPATCH(POBJGPU pGpu, struct KernelMIGManager *pEngstate, void *pTunableState) { - return pEngstate->__kmigmgrSetTunableState__(pGpu, pEngstate, pTunableState); -} - static inline NvBool kmigmgrIsPresent_DISPATCH(POBJGPU pGpu, struct KernelMIGManager *pEngstate) { return pEngstate->__kmigmgrIsPresent__(pGpu, pEngstate); } @@ -909,11 +916,13 @@ } static inline const union ENGTYPE_BIT_VECTOR *kmigmgrGetPartitionableEnginesInUse(OBJGPU *pGpu, struct KernelMIGManager *pKernelMIGManager) { - return &pKernelMIGManager->partitionableEnginesInUse; + struct KernelMIGManager_PRIVATE *pKernelMIGManager_PRIVATE = (struct KernelMIGManager_PRIVATE *)pKernelMIGManager; + return &pKernelMIGManager_PRIVATE->partitionableEnginesInUse; } static inline NvBool kmigmgrIsA100ReducedConfig(OBJGPU *pGpu, struct KernelMIGManager *pKernelMIGManager) { - return pKernelMIGManager->bIsA100ReducedConfig; + struct KernelMIGManager_PRIVATE *pKernelMIGManager_PRIVATE = (struct KernelMIGManager_PRIVATE *)pKernelMIGManager; + return pKernelMIGManager_PRIVATE->bIsA100ReducedConfig; } NV_STATUS kmigmgrIncRefCount_IMPL(struct RsShared *arg0); @@ -949,9 +958,9 @@ NvU16 kmigmgrGetAttributionIdFromMIGReference_IMPL(struct MIG_INSTANCE_REF arg0); #define kmigmgrGetAttributionIdFromMIGReference(arg0) kmigmgrGetAttributionIdFromMIGReference_IMPL(arg0) -NV_STATUS kmigmgrAllocateInstanceEngines_IMPL(union ENGTYPE_BIT_VECTOR *pSourceEngines, NvBool bShared, struct NV_RANGE engTypeRange, NvU32 reqEngCount, union ENGTYPE_BIT_VECTOR *pOutEngines, union ENGTYPE_BIT_VECTOR *pExclusiveEngines, union ENGTYPE_BIT_VECTOR *pSharedEngines); +NV_STATUS kmigmgrAllocateInstanceEngines_IMPL(union ENGTYPE_BIT_VECTOR *pSourceEngines, NvBool bShared, struct NV_RANGE engTypeRange, NvU32 reqEngCount, union ENGTYPE_BIT_VECTOR *pOutEngines, union ENGTYPE_BIT_VECTOR *pExclusiveEngines, union ENGTYPE_BIT_VECTOR *pSharedEngines, union ENGTYPE_BIT_VECTOR *pAllocatableEngines); -#define kmigmgrAllocateInstanceEngines(pSourceEngines, bShared, engTypeRange, reqEngCount, pOutEngines, pExclusiveEngines, pSharedEngines) kmigmgrAllocateInstanceEngines_IMPL(pSourceEngines, bShared, engTypeRange, reqEngCount, pOutEngines, pExclusiveEngines, pSharedEngines) +#define kmigmgrAllocateInstanceEngines(pSourceEngines, bShared, engTypeRange, reqEngCount, pOutEngines, pExclusiveEngines, pSharedEngines, pAllocatableEngines) kmigmgrAllocateInstanceEngines_IMPL(pSourceEngines, bShared, engTypeRange, reqEngCount, pOutEngines, pExclusiveEngines, pSharedEngines, pAllocatableEngines) void kmigmgrGetLocalEngineMask_IMPL(union ENGTYPE_BIT_VECTOR *pPhysicalEngineMask, union ENGTYPE_BIT_VECTOR *pLocalEngineMask); #define kmigmgrGetLocalEngineMask(pPhysicalEngineMask, pLocalEngineMask) kmigmgrGetLocalEngineMask_IMPL(pPhysicalEngineMask, pLocalEngineMask) @@ -1197,17 +1206,6 @@ #define kmigmgrIsEngineInInstance(arg0, arg1, globalRmEngType, arg2) kmigmgrIsEngineInInstance_IMPL(arg0, arg1, globalRmEngType, arg2) #endif //__nvoc_kernel_mig_manager_h_disabled -NV_STATUS kmigmgrGetFreeEngines_IMPL(OBJGPU *arg0, struct KernelMIGManager *arg1, NvU32 engineCount, struct NV_RANGE engineRange, union ENGTYPE_BIT_VECTOR *pInstanceEngines); - -#ifdef __nvoc_kernel_mig_manager_h_disabled -static inline NV_STATUS kmigmgrGetFreeEngines(OBJGPU *arg0, struct KernelMIGManager *arg1, NvU32 engineCount, struct NV_RANGE engineRange, union ENGTYPE_BIT_VECTOR *pInstanceEngines) { - NV_ASSERT_FAILED_PRECOMP("KernelMIGManager was disabled!"); - return NV_ERR_NOT_SUPPORTED; -} -#else //__nvoc_kernel_mig_manager_h_disabled -#define kmigmgrGetFreeEngines(arg0, arg1, engineCount, engineRange, pInstanceEngines) kmigmgrGetFreeEngines_IMPL(arg0, arg1, engineCount, engineRange, pInstanceEngines) -#endif //__nvoc_kernel_mig_manager_h_disabled - NV_STATUS kmigmgrCreateGPUInstance_IMPL(OBJGPU *arg0, struct KernelMIGManager *arg1, NvU32 *pSwizzId, KMIGMGR_CREATE_GPU_INSTANCE_PARAMS arg2, NvBool bValid, NvBool bCreateCap); #ifdef __nvoc_kernel_mig_manager_h_disabled @@ -1398,6 +1396,17 @@ #define kmigmgrIsClientUsingDeviceProfiling(arg0, arg1, hClient) kmigmgrIsClientUsingDeviceProfiling_IMPL(arg0, arg1, hClient) #endif //__nvoc_kernel_mig_manager_h_disabled +NvBool kmigmgrIsDeviceUsingDeviceProfiling_IMPL(OBJGPU *arg0, struct KernelMIGManager *arg1, struct Device *pDevice); + +#ifdef __nvoc_kernel_mig_manager_h_disabled +static inline NvBool kmigmgrIsDeviceUsingDeviceProfiling(OBJGPU *arg0, struct KernelMIGManager *arg1, struct Device *pDevice) { + NV_ASSERT_FAILED_PRECOMP("KernelMIGManager was disabled!"); + return NV_FALSE; +} +#else //__nvoc_kernel_mig_manager_h_disabled +#define kmigmgrIsDeviceUsingDeviceProfiling(arg0, arg1, pDevice) kmigmgrIsDeviceUsingDeviceProfiling_IMPL(arg0, arg1, pDevice) +#endif //__nvoc_kernel_mig_manager_h_disabled + NV_STATUS kmigmgrEnableAllLCEs_IMPL(OBJGPU *arg0, struct KernelMIGManager *arg1, NvBool bEnableAllLCEs); #ifdef __nvoc_kernel_mig_manager_h_disabled @@ -1409,6 +1418,17 @@ #define kmigmgrEnableAllLCEs(arg0, arg1, bEnableAllLCEs) kmigmgrEnableAllLCEs_IMPL(arg0, arg1, bEnableAllLCEs) #endif //__nvoc_kernel_mig_manager_h_disabled +NV_STATUS kmigmgrGetInstanceRefFromDevice_IMPL(OBJGPU *arg0, struct KernelMIGManager *arg1, struct Device *arg2, struct MIG_INSTANCE_REF *arg3); + +#ifdef __nvoc_kernel_mig_manager_h_disabled +static inline NV_STATUS kmigmgrGetInstanceRefFromDevice(OBJGPU *arg0, struct KernelMIGManager *arg1, struct Device *arg2, struct MIG_INSTANCE_REF *arg3) { + NV_ASSERT_FAILED_PRECOMP("KernelMIGManager was disabled!"); + return NV_ERR_NOT_SUPPORTED; +} +#else //__nvoc_kernel_mig_manager_h_disabled +#define kmigmgrGetInstanceRefFromDevice(arg0, arg1, arg2, arg3) kmigmgrGetInstanceRefFromDevice_IMPL(arg0, arg1, arg2, arg3) +#endif //__nvoc_kernel_mig_manager_h_disabled + NV_STATUS kmigmgrGetInstanceRefFromClient_IMPL(OBJGPU *arg0, struct KernelMIGManager *arg1, NvHandle hClient, struct MIG_INSTANCE_REF *arg2); #ifdef __nvoc_kernel_mig_manager_h_disabled @@ -1420,26 +1440,26 @@ #define kmigmgrGetInstanceRefFromClient(arg0, arg1, hClient, arg2) kmigmgrGetInstanceRefFromClient_IMPL(arg0, arg1, hClient, arg2) #endif //__nvoc_kernel_mig_manager_h_disabled -NV_STATUS kmigmgrGetMemoryPartitionHeapFromClient_IMPL(OBJGPU *arg0, struct KernelMIGManager *arg1, NvHandle hClient, struct Heap **arg2); +NV_STATUS kmigmgrGetMemoryPartitionHeapFromDevice_IMPL(OBJGPU *arg0, struct KernelMIGManager *arg1, struct Device *arg2, struct Heap **arg3); #ifdef __nvoc_kernel_mig_manager_h_disabled -static inline NV_STATUS kmigmgrGetMemoryPartitionHeapFromClient(OBJGPU *arg0, struct KernelMIGManager *arg1, NvHandle hClient, struct Heap **arg2) { +static inline NV_STATUS kmigmgrGetMemoryPartitionHeapFromDevice(OBJGPU *arg0, struct KernelMIGManager *arg1, struct Device *arg2, struct Heap **arg3) { NV_ASSERT_FAILED_PRECOMP("KernelMIGManager was disabled!"); return NV_ERR_NOT_SUPPORTED; } #else //__nvoc_kernel_mig_manager_h_disabled -#define kmigmgrGetMemoryPartitionHeapFromClient(arg0, arg1, hClient, arg2) kmigmgrGetMemoryPartitionHeapFromClient_IMPL(arg0, arg1, hClient, arg2) +#define kmigmgrGetMemoryPartitionHeapFromDevice(arg0, arg1, arg2, arg3) kmigmgrGetMemoryPartitionHeapFromDevice_IMPL(arg0, arg1, arg2, arg3) #endif //__nvoc_kernel_mig_manager_h_disabled -NV_STATUS kmigmgrGetSwizzIdFromClient_IMPL(OBJGPU *arg0, struct KernelMIGManager *arg1, NvHandle hClient, NvU32 *pSwizzId); +NV_STATUS kmigmgrGetSwizzIdFromDevice_IMPL(OBJGPU *arg0, struct KernelMIGManager *arg1, struct Device *pDevice, NvU32 *pSwizzId); #ifdef __nvoc_kernel_mig_manager_h_disabled -static inline NV_STATUS kmigmgrGetSwizzIdFromClient(OBJGPU *arg0, struct KernelMIGManager *arg1, NvHandle hClient, NvU32 *pSwizzId) { +static inline NV_STATUS kmigmgrGetSwizzIdFromDevice(OBJGPU *arg0, struct KernelMIGManager *arg1, struct Device *pDevice, NvU32 *pSwizzId) { NV_ASSERT_FAILED_PRECOMP("KernelMIGManager was disabled!"); return NV_ERR_NOT_SUPPORTED; } #else //__nvoc_kernel_mig_manager_h_disabled -#define kmigmgrGetSwizzIdFromClient(arg0, arg1, hClient, pSwizzId) kmigmgrGetSwizzIdFromClient_IMPL(arg0, arg1, hClient, pSwizzId) +#define kmigmgrGetSwizzIdFromDevice(arg0, arg1, pDevice, pSwizzId) kmigmgrGetSwizzIdFromDevice_IMPL(arg0, arg1, pDevice, pSwizzId) #endif //__nvoc_kernel_mig_manager_h_disabled void kmigmgrPrintGPUInstanceInfo_IMPL(OBJGPU *arg0, struct KernelMIGManager *arg1, KERNEL_MIG_GPU_INSTANCE *arg2); @@ -1562,15 +1582,15 @@ #define kmigmgrGetMIGReferenceFromEngineType(arg0, arg1, rmEngineType, arg2) kmigmgrGetMIGReferenceFromEngineType_IMPL(arg0, arg1, rmEngineType, arg2) #endif //__nvoc_kernel_mig_manager_h_disabled -NV_STATUS kmigmgrGetGPUInstanceScrubberCe_IMPL(OBJGPU *arg0, struct KernelMIGManager *arg1, NvHandle hClient, NvU32 *ceInst); +NV_STATUS kmigmgrGetGPUInstanceScrubberCe_IMPL(OBJGPU *arg0, struct KernelMIGManager *arg1, struct Device *pDevice, NvU32 *ceInst); #ifdef __nvoc_kernel_mig_manager_h_disabled -static inline NV_STATUS kmigmgrGetGPUInstanceScrubberCe(OBJGPU *arg0, struct KernelMIGManager *arg1, NvHandle hClient, NvU32 *ceInst) { +static inline NV_STATUS kmigmgrGetGPUInstanceScrubberCe(OBJGPU *arg0, struct KernelMIGManager *arg1, struct Device *pDevice, NvU32 *ceInst) { NV_ASSERT_FAILED_PRECOMP("KernelMIGManager was disabled!"); return NV_ERR_NOT_SUPPORTED; } #else //__nvoc_kernel_mig_manager_h_disabled -#define kmigmgrGetGPUInstanceScrubberCe(arg0, arg1, hClient, ceInst) kmigmgrGetGPUInstanceScrubberCe_IMPL(arg0, arg1, hClient, ceInst) +#define kmigmgrGetGPUInstanceScrubberCe(arg0, arg1, pDevice, ceInst) kmigmgrGetGPUInstanceScrubberCe_IMPL(arg0, arg1, pDevice, ceInst) #endif //__nvoc_kernel_mig_manager_h_disabled NV_STATUS kmigmgrDescribeGPUInstances_IMPL(OBJGPU *arg0, struct KernelMIGManager *arg1, NV2080_CTRL_GPU_DESCRIBE_PARTITIONS_PARAMS *arg2); @@ -1814,6 +1834,17 @@ #define kmigmgrIsCTSIdAvailable(arg0, arg1, ctsIdValidMask, ctsIdInUseMask, ctsId) kmigmgrIsCTSIdAvailable_IMPL(arg0, arg1, ctsIdValidMask, ctsIdInUseMask, ctsId) #endif //__nvoc_kernel_mig_manager_h_disabled +NV_STATUS kmigmgrUpdateCiConfigForVgpu_IMPL(OBJGPU *pGpu, struct KernelMIGManager *pKernelMIGManager, NvU32 execPartCount, NvU32 *pExecPartId, NvU32 gfid, NvBool bDelete); + +#ifdef __nvoc_kernel_mig_manager_h_disabled +static inline NV_STATUS kmigmgrUpdateCiConfigForVgpu(OBJGPU *pGpu, struct KernelMIGManager *pKernelMIGManager, NvU32 execPartCount, NvU32 *pExecPartId, NvU32 gfid, NvBool bDelete) { + NV_ASSERT_FAILED_PRECOMP("KernelMIGManager was disabled!"); + return NV_ERR_NOT_SUPPORTED; +} +#else //__nvoc_kernel_mig_manager_h_disabled +#define kmigmgrUpdateCiConfigForVgpu(pGpu, pKernelMIGManager, execPartCount, pExecPartId, gfid, bDelete) kmigmgrUpdateCiConfigForVgpu_IMPL(pGpu, pKernelMIGManager, execPartCount, pExecPartId, gfid, bDelete) +#endif //__nvoc_kernel_mig_manager_h_disabled + #undef PRIVATE_FIELD diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/generated/g_kernel_nvdec_ctx_nvoc.c nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_kernel_nvdec_ctx_nvoc.c --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/generated/g_kernel_nvdec_ctx_nvoc.c 2023-10-25 20:27:09.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_kernel_nvdec_ctx_nvoc.c 2024-03-05 22:18:30.000000000 +0000 @@ -176,7 +176,7 @@ return resControlLookup((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_NvdecContext_RsResource.offset), pParams, ppEntry); } -static NV_STATUS __nvoc_thunk_ChannelDescendant_nvdecctxGetSwMethods(struct NvdecContext *pChannelDescendant, METHOD **ppMethods, NvU32 *pNumMethods) { +static NV_STATUS __nvoc_thunk_ChannelDescendant_nvdecctxGetSwMethods(struct NvdecContext *pChannelDescendant, const METHOD **ppMethods, NvU32 *pNumMethods) { return chandesGetSwMethods((struct ChannelDescendant *)(((unsigned char *)pChannelDescendant) + __nvoc_rtti_NvdecContext_ChannelDescendant.offset), ppMethods, pNumMethods); } @@ -212,6 +212,10 @@ return notifyUnregisterEvent((struct Notifier *)(((unsigned char *)pNotifier) + __nvoc_rtti_NvdecContext_Notifier.offset), hNotifierClient, hNotifierResource, hEventClient, hEvent); } +static NV_STATUS __nvoc_thunk_RmResource_nvdecctxControlSerialization_Prologue(struct NvdecContext *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return rmresControlSerialization_Prologue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_NvdecContext_RmResource.offset), pCallContext, pParams); +} + static NvBool __nvoc_thunk_RsResource_nvdecctxCanCopy(struct NvdecContext *pResource) { return resCanCopy((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_NvdecContext_RsResource.offset)); } @@ -224,6 +228,10 @@ return resIsDuplicate((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_NvdecContext_RsResource.offset), hMemory, pDuplicate); } +static void __nvoc_thunk_RmResource_nvdecctxControlSerialization_Epilogue(struct NvdecContext *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + rmresControlSerialization_Epilogue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_NvdecContext_RmResource.offset), pCallContext, pParams); +} + static PEVENTNOTIFICATION *__nvoc_thunk_Notifier_nvdecctxGetNotificationListPtr(struct NvdecContext *pNotifier) { return notifyGetNotificationListPtr((struct Notifier *)(((unsigned char *)pNotifier) + __nvoc_rtti_NvdecContext_Notifier.offset)); } @@ -335,12 +343,16 @@ pThis->__nvdecctxUnregisterEvent__ = &__nvoc_thunk_Notifier_nvdecctxUnregisterEvent; + pThis->__nvdecctxControlSerialization_Prologue__ = &__nvoc_thunk_RmResource_nvdecctxControlSerialization_Prologue; + pThis->__nvdecctxCanCopy__ = &__nvoc_thunk_RsResource_nvdecctxCanCopy; pThis->__nvdecctxPreDestruct__ = &__nvoc_thunk_RsResource_nvdecctxPreDestruct; pThis->__nvdecctxIsDuplicate__ = &__nvoc_thunk_RsResource_nvdecctxIsDuplicate; + pThis->__nvdecctxControlSerialization_Epilogue__ = &__nvoc_thunk_RmResource_nvdecctxControlSerialization_Epilogue; + pThis->__nvdecctxGetNotificationListPtr__ = &__nvoc_thunk_Notifier_nvdecctxGetNotificationListPtr; pThis->__nvdecctxGetNotificationShare__ = &__nvoc_thunk_Notifier_nvdecctxGetNotificationShare; @@ -375,13 +387,16 @@ NvdecContext *pThis; RmHalspecOwner *pRmhalspecowner; - pThis = portMemAllocNonPaged(sizeof(NvdecContext)); - if (pThis == NULL) return NV_ERR_NO_MEMORY; + status = __nvoc_handleObjCreateMemAlloc(createFlags, sizeof(NvdecContext), (void**)&pThis, (void**)ppThis); + if (status != NV_OK) + return status; portMemSet(pThis, 0, sizeof(NvdecContext)); __nvoc_initRtti(staticCast(pThis, Dynamic), &__nvoc_class_def_NvdecContext); + pThis->__nvoc_base_ChannelDescendant.__nvoc_base_GpuResource.__nvoc_base_RmResource.__nvoc_base_RsResource.__nvoc_base_Object.createFlags = createFlags; + if (pParent != NULL && !(createFlags & NVOC_OBJ_CREATE_FLAGS_PARENT_HALSPEC_ONLY)) { pParentObj = dynamicCast(pParent, Object); @@ -401,11 +416,17 @@ if (status != NV_OK) goto __nvoc_objCreate_NvdecContext_cleanup; *ppThis = pThis; + return NV_OK; __nvoc_objCreate_NvdecContext_cleanup: // do not call destructors here since the constructor already called them - portMemFree(pThis); + if (createFlags & NVOC_OBJ_CREATE_FLAGS_IN_PLACE_CONSTRUCT) + portMemSet(pThis, 0, sizeof(NvdecContext)); + else + portMemFree(pThis); + + // coverity[leaked_storage:FALSE] return status; } diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/generated/g_kernel_nvdec_ctx_nvoc.h nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_kernel_nvdec_ctx_nvoc.h --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/generated/g_kernel_nvdec_ctx_nvoc.h 2023-10-25 20:27:10.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_kernel_nvdec_ctx_nvoc.h 2024-03-05 22:18:30.000000000 +0000 @@ -72,7 +72,7 @@ NV_STATUS (*__nvdecctxUnmapFrom__)(struct NvdecContext *, RS_RES_UNMAP_FROM_PARAMS *); void (*__nvdecctxControl_Epilogue__)(struct NvdecContext *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); NV_STATUS (*__nvdecctxControlLookup__)(struct NvdecContext *, struct RS_RES_CONTROL_PARAMS_INTERNAL *, const struct NVOC_EXPORTED_METHOD_DEF **); - NV_STATUS (*__nvdecctxGetSwMethods__)(struct NvdecContext *, METHOD **, NvU32 *); + NV_STATUS (*__nvdecctxGetSwMethods__)(struct NvdecContext *, const METHOD **, NvU32 *); NvHandle (*__nvdecctxGetInternalObjectHandle__)(struct NvdecContext *); NV_STATUS (*__nvdecctxControl__)(struct NvdecContext *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); NV_STATUS (*__nvdecctxUnmap__)(struct NvdecContext *, struct CALL_CONTEXT *, struct RsCpuMapping *); @@ -81,9 +81,11 @@ NvBool (*__nvdecctxIsSwMethodStalling__)(struct NvdecContext *, NvU32); NV_STATUS (*__nvdecctxControlFilter__)(struct NvdecContext *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); NV_STATUS (*__nvdecctxUnregisterEvent__)(struct NvdecContext *, NvHandle, NvHandle, NvHandle, NvHandle); + NV_STATUS (*__nvdecctxControlSerialization_Prologue__)(struct NvdecContext *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); NvBool (*__nvdecctxCanCopy__)(struct NvdecContext *); void (*__nvdecctxPreDestruct__)(struct NvdecContext *); NV_STATUS (*__nvdecctxIsDuplicate__)(struct NvdecContext *, NvHandle, NvBool *); + void (*__nvdecctxControlSerialization_Epilogue__)(struct NvdecContext *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); PEVENTNOTIFICATION *(*__nvdecctxGetNotificationListPtr__)(struct NvdecContext *); struct NotifShare *(*__nvdecctxGetNotificationShare__)(struct NvdecContext *); NV_STATUS (*__nvdecctxMap__)(struct NvdecContext *, struct CALL_CONTEXT *, struct RS_CPU_MAP_PARAMS *, struct RsCpuMapping *); @@ -141,9 +143,11 @@ #define nvdecctxIsSwMethodStalling(pChannelDescendant, hHandle) nvdecctxIsSwMethodStalling_DISPATCH(pChannelDescendant, hHandle) #define nvdecctxControlFilter(pResource, pCallContext, pParams) nvdecctxControlFilter_DISPATCH(pResource, pCallContext, pParams) #define nvdecctxUnregisterEvent(pNotifier, hNotifierClient, hNotifierResource, hEventClient, hEvent) nvdecctxUnregisterEvent_DISPATCH(pNotifier, hNotifierClient, hNotifierResource, hEventClient, hEvent) +#define nvdecctxControlSerialization_Prologue(pResource, pCallContext, pParams) nvdecctxControlSerialization_Prologue_DISPATCH(pResource, pCallContext, pParams) #define nvdecctxCanCopy(pResource) nvdecctxCanCopy_DISPATCH(pResource) #define nvdecctxPreDestruct(pResource) nvdecctxPreDestruct_DISPATCH(pResource) #define nvdecctxIsDuplicate(pResource, hMemory, pDuplicate) nvdecctxIsDuplicate_DISPATCH(pResource, hMemory, pDuplicate) +#define nvdecctxControlSerialization_Epilogue(pResource, pCallContext, pParams) nvdecctxControlSerialization_Epilogue_DISPATCH(pResource, pCallContext, pParams) #define nvdecctxGetNotificationListPtr(pNotifier) nvdecctxGetNotificationListPtr_DISPATCH(pNotifier) #define nvdecctxGetNotificationShare(pNotifier) nvdecctxGetNotificationShare_DISPATCH(pNotifier) #define nvdecctxMap(pGpuResource, pCallContext, pParams, pCpuMapping) nvdecctxMap_DISPATCH(pGpuResource, pCallContext, pParams, pCpuMapping) @@ -231,7 +235,7 @@ return pResource->__nvdecctxControlLookup__(pResource, pParams, ppEntry); } -static inline NV_STATUS nvdecctxGetSwMethods_DISPATCH(struct NvdecContext *pChannelDescendant, METHOD **ppMethods, NvU32 *pNumMethods) { +static inline NV_STATUS nvdecctxGetSwMethods_DISPATCH(struct NvdecContext *pChannelDescendant, const METHOD **ppMethods, NvU32 *pNumMethods) { return pChannelDescendant->__nvdecctxGetSwMethods__(pChannelDescendant, ppMethods, pNumMethods); } @@ -267,6 +271,10 @@ return pNotifier->__nvdecctxUnregisterEvent__(pNotifier, hNotifierClient, hNotifierResource, hEventClient, hEvent); } +static inline NV_STATUS nvdecctxControlSerialization_Prologue_DISPATCH(struct NvdecContext *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return pResource->__nvdecctxControlSerialization_Prologue__(pResource, pCallContext, pParams); +} + static inline NvBool nvdecctxCanCopy_DISPATCH(struct NvdecContext *pResource) { return pResource->__nvdecctxCanCopy__(pResource); } @@ -279,6 +287,10 @@ return pResource->__nvdecctxIsDuplicate__(pResource, hMemory, pDuplicate); } +static inline void nvdecctxControlSerialization_Epilogue_DISPATCH(struct NvdecContext *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + pResource->__nvdecctxControlSerialization_Epilogue__(pResource, pCallContext, pParams); +} + static inline PEVENTNOTIFICATION *nvdecctxGetNotificationListPtr_DISPATCH(struct NvdecContext *pNotifier) { return pNotifier->__nvdecctxGetNotificationListPtr__(pNotifier); } diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/generated/g_kernel_nvenc_ctx_nvoc.c nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_kernel_nvenc_ctx_nvoc.c --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/generated/g_kernel_nvenc_ctx_nvoc.c 2023-10-25 20:27:10.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_kernel_nvenc_ctx_nvoc.c 2024-03-05 22:18:30.000000000 +0000 @@ -176,7 +176,7 @@ return resControlLookup((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_MsencContext_RsResource.offset), pParams, ppEntry); } -static NV_STATUS __nvoc_thunk_ChannelDescendant_msencctxGetSwMethods(struct MsencContext *pChannelDescendant, METHOD **ppMethods, NvU32 *pNumMethods) { +static NV_STATUS __nvoc_thunk_ChannelDescendant_msencctxGetSwMethods(struct MsencContext *pChannelDescendant, const METHOD **ppMethods, NvU32 *pNumMethods) { return chandesGetSwMethods((struct ChannelDescendant *)(((unsigned char *)pChannelDescendant) + __nvoc_rtti_MsencContext_ChannelDescendant.offset), ppMethods, pNumMethods); } @@ -212,6 +212,10 @@ return notifyUnregisterEvent((struct Notifier *)(((unsigned char *)pNotifier) + __nvoc_rtti_MsencContext_Notifier.offset), hNotifierClient, hNotifierResource, hEventClient, hEvent); } +static NV_STATUS __nvoc_thunk_RmResource_msencctxControlSerialization_Prologue(struct MsencContext *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return rmresControlSerialization_Prologue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_MsencContext_RmResource.offset), pCallContext, pParams); +} + static NvBool __nvoc_thunk_RsResource_msencctxCanCopy(struct MsencContext *pResource) { return resCanCopy((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_MsencContext_RsResource.offset)); } @@ -224,6 +228,10 @@ return resIsDuplicate((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_MsencContext_RsResource.offset), hMemory, pDuplicate); } +static void __nvoc_thunk_RmResource_msencctxControlSerialization_Epilogue(struct MsencContext *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + rmresControlSerialization_Epilogue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_MsencContext_RmResource.offset), pCallContext, pParams); +} + static PEVENTNOTIFICATION *__nvoc_thunk_Notifier_msencctxGetNotificationListPtr(struct MsencContext *pNotifier) { return notifyGetNotificationListPtr((struct Notifier *)(((unsigned char *)pNotifier) + __nvoc_rtti_MsencContext_Notifier.offset)); } @@ -335,12 +343,16 @@ pThis->__msencctxUnregisterEvent__ = &__nvoc_thunk_Notifier_msencctxUnregisterEvent; + pThis->__msencctxControlSerialization_Prologue__ = &__nvoc_thunk_RmResource_msencctxControlSerialization_Prologue; + pThis->__msencctxCanCopy__ = &__nvoc_thunk_RsResource_msencctxCanCopy; pThis->__msencctxPreDestruct__ = &__nvoc_thunk_RsResource_msencctxPreDestruct; pThis->__msencctxIsDuplicate__ = &__nvoc_thunk_RsResource_msencctxIsDuplicate; + pThis->__msencctxControlSerialization_Epilogue__ = &__nvoc_thunk_RmResource_msencctxControlSerialization_Epilogue; + pThis->__msencctxGetNotificationListPtr__ = &__nvoc_thunk_Notifier_msencctxGetNotificationListPtr; pThis->__msencctxGetNotificationShare__ = &__nvoc_thunk_Notifier_msencctxGetNotificationShare; @@ -375,13 +387,16 @@ MsencContext *pThis; RmHalspecOwner *pRmhalspecowner; - pThis = portMemAllocNonPaged(sizeof(MsencContext)); - if (pThis == NULL) return NV_ERR_NO_MEMORY; + status = __nvoc_handleObjCreateMemAlloc(createFlags, sizeof(MsencContext), (void**)&pThis, (void**)ppThis); + if (status != NV_OK) + return status; portMemSet(pThis, 0, sizeof(MsencContext)); __nvoc_initRtti(staticCast(pThis, Dynamic), &__nvoc_class_def_MsencContext); + pThis->__nvoc_base_ChannelDescendant.__nvoc_base_GpuResource.__nvoc_base_RmResource.__nvoc_base_RsResource.__nvoc_base_Object.createFlags = createFlags; + if (pParent != NULL && !(createFlags & NVOC_OBJ_CREATE_FLAGS_PARENT_HALSPEC_ONLY)) { pParentObj = dynamicCast(pParent, Object); @@ -401,11 +416,17 @@ if (status != NV_OK) goto __nvoc_objCreate_MsencContext_cleanup; *ppThis = pThis; + return NV_OK; __nvoc_objCreate_MsencContext_cleanup: // do not call destructors here since the constructor already called them - portMemFree(pThis); + if (createFlags & NVOC_OBJ_CREATE_FLAGS_IN_PLACE_CONSTRUCT) + portMemSet(pThis, 0, sizeof(MsencContext)); + else + portMemFree(pThis); + + // coverity[leaked_storage:FALSE] return status; } diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/generated/g_kernel_nvenc_ctx_nvoc.h nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_kernel_nvenc_ctx_nvoc.h --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/generated/g_kernel_nvenc_ctx_nvoc.h 2023-10-25 20:27:10.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_kernel_nvenc_ctx_nvoc.h 2024-03-05 22:18:31.000000000 +0000 @@ -72,7 +72,7 @@ NV_STATUS (*__msencctxUnmapFrom__)(struct MsencContext *, RS_RES_UNMAP_FROM_PARAMS *); void (*__msencctxControl_Epilogue__)(struct MsencContext *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); NV_STATUS (*__msencctxControlLookup__)(struct MsencContext *, struct RS_RES_CONTROL_PARAMS_INTERNAL *, const struct NVOC_EXPORTED_METHOD_DEF **); - NV_STATUS (*__msencctxGetSwMethods__)(struct MsencContext *, METHOD **, NvU32 *); + NV_STATUS (*__msencctxGetSwMethods__)(struct MsencContext *, const METHOD **, NvU32 *); NvHandle (*__msencctxGetInternalObjectHandle__)(struct MsencContext *); NV_STATUS (*__msencctxControl__)(struct MsencContext *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); NV_STATUS (*__msencctxUnmap__)(struct MsencContext *, struct CALL_CONTEXT *, struct RsCpuMapping *); @@ -81,9 +81,11 @@ NvBool (*__msencctxIsSwMethodStalling__)(struct MsencContext *, NvU32); NV_STATUS (*__msencctxControlFilter__)(struct MsencContext *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); NV_STATUS (*__msencctxUnregisterEvent__)(struct MsencContext *, NvHandle, NvHandle, NvHandle, NvHandle); + NV_STATUS (*__msencctxControlSerialization_Prologue__)(struct MsencContext *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); NvBool (*__msencctxCanCopy__)(struct MsencContext *); void (*__msencctxPreDestruct__)(struct MsencContext *); NV_STATUS (*__msencctxIsDuplicate__)(struct MsencContext *, NvHandle, NvBool *); + void (*__msencctxControlSerialization_Epilogue__)(struct MsencContext *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); PEVENTNOTIFICATION *(*__msencctxGetNotificationListPtr__)(struct MsencContext *); struct NotifShare *(*__msencctxGetNotificationShare__)(struct MsencContext *); NV_STATUS (*__msencctxMap__)(struct MsencContext *, struct CALL_CONTEXT *, struct RS_CPU_MAP_PARAMS *, struct RsCpuMapping *); @@ -141,9 +143,11 @@ #define msencctxIsSwMethodStalling(pChannelDescendant, hHandle) msencctxIsSwMethodStalling_DISPATCH(pChannelDescendant, hHandle) #define msencctxControlFilter(pResource, pCallContext, pParams) msencctxControlFilter_DISPATCH(pResource, pCallContext, pParams) #define msencctxUnregisterEvent(pNotifier, hNotifierClient, hNotifierResource, hEventClient, hEvent) msencctxUnregisterEvent_DISPATCH(pNotifier, hNotifierClient, hNotifierResource, hEventClient, hEvent) +#define msencctxControlSerialization_Prologue(pResource, pCallContext, pParams) msencctxControlSerialization_Prologue_DISPATCH(pResource, pCallContext, pParams) #define msencctxCanCopy(pResource) msencctxCanCopy_DISPATCH(pResource) #define msencctxPreDestruct(pResource) msencctxPreDestruct_DISPATCH(pResource) #define msencctxIsDuplicate(pResource, hMemory, pDuplicate) msencctxIsDuplicate_DISPATCH(pResource, hMemory, pDuplicate) +#define msencctxControlSerialization_Epilogue(pResource, pCallContext, pParams) msencctxControlSerialization_Epilogue_DISPATCH(pResource, pCallContext, pParams) #define msencctxGetNotificationListPtr(pNotifier) msencctxGetNotificationListPtr_DISPATCH(pNotifier) #define msencctxGetNotificationShare(pNotifier) msencctxGetNotificationShare_DISPATCH(pNotifier) #define msencctxMap(pGpuResource, pCallContext, pParams, pCpuMapping) msencctxMap_DISPATCH(pGpuResource, pCallContext, pParams, pCpuMapping) @@ -231,7 +235,7 @@ return pResource->__msencctxControlLookup__(pResource, pParams, ppEntry); } -static inline NV_STATUS msencctxGetSwMethods_DISPATCH(struct MsencContext *pChannelDescendant, METHOD **ppMethods, NvU32 *pNumMethods) { +static inline NV_STATUS msencctxGetSwMethods_DISPATCH(struct MsencContext *pChannelDescendant, const METHOD **ppMethods, NvU32 *pNumMethods) { return pChannelDescendant->__msencctxGetSwMethods__(pChannelDescendant, ppMethods, pNumMethods); } @@ -267,6 +271,10 @@ return pNotifier->__msencctxUnregisterEvent__(pNotifier, hNotifierClient, hNotifierResource, hEventClient, hEvent); } +static inline NV_STATUS msencctxControlSerialization_Prologue_DISPATCH(struct MsencContext *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return pResource->__msencctxControlSerialization_Prologue__(pResource, pCallContext, pParams); +} + static inline NvBool msencctxCanCopy_DISPATCH(struct MsencContext *pResource) { return pResource->__msencctxCanCopy__(pResource); } @@ -279,6 +287,10 @@ return pResource->__msencctxIsDuplicate__(pResource, hMemory, pDuplicate); } +static inline void msencctxControlSerialization_Epilogue_DISPATCH(struct MsencContext *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + pResource->__msencctxControlSerialization_Epilogue__(pResource, pCallContext, pParams); +} + static inline PEVENTNOTIFICATION *msencctxGetNotificationListPtr_DISPATCH(struct MsencContext *pNotifier) { return pNotifier->__msencctxGetNotificationListPtr__(pNotifier); } diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/generated/g_kernel_nvjpg_ctx_nvoc.c nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_kernel_nvjpg_ctx_nvoc.c --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/generated/g_kernel_nvjpg_ctx_nvoc.c 2023-10-25 20:27:10.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_kernel_nvjpg_ctx_nvoc.c 2024-03-05 22:18:31.000000000 +0000 @@ -176,7 +176,7 @@ return resControlLookup((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_NvjpgContext_RsResource.offset), pParams, ppEntry); } -static NV_STATUS __nvoc_thunk_ChannelDescendant_nvjpgctxGetSwMethods(struct NvjpgContext *pChannelDescendant, METHOD **ppMethods, NvU32 *pNumMethods) { +static NV_STATUS __nvoc_thunk_ChannelDescendant_nvjpgctxGetSwMethods(struct NvjpgContext *pChannelDescendant, const METHOD **ppMethods, NvU32 *pNumMethods) { return chandesGetSwMethods((struct ChannelDescendant *)(((unsigned char *)pChannelDescendant) + __nvoc_rtti_NvjpgContext_ChannelDescendant.offset), ppMethods, pNumMethods); } @@ -212,6 +212,10 @@ return notifyUnregisterEvent((struct Notifier *)(((unsigned char *)pNotifier) + __nvoc_rtti_NvjpgContext_Notifier.offset), hNotifierClient, hNotifierResource, hEventClient, hEvent); } +static NV_STATUS __nvoc_thunk_RmResource_nvjpgctxControlSerialization_Prologue(struct NvjpgContext *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return rmresControlSerialization_Prologue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_NvjpgContext_RmResource.offset), pCallContext, pParams); +} + static NvBool __nvoc_thunk_RsResource_nvjpgctxCanCopy(struct NvjpgContext *pResource) { return resCanCopy((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_NvjpgContext_RsResource.offset)); } @@ -224,6 +228,10 @@ return resIsDuplicate((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_NvjpgContext_RsResource.offset), hMemory, pDuplicate); } +static void __nvoc_thunk_RmResource_nvjpgctxControlSerialization_Epilogue(struct NvjpgContext *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + rmresControlSerialization_Epilogue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_NvjpgContext_RmResource.offset), pCallContext, pParams); +} + static PEVENTNOTIFICATION *__nvoc_thunk_Notifier_nvjpgctxGetNotificationListPtr(struct NvjpgContext *pNotifier) { return notifyGetNotificationListPtr((struct Notifier *)(((unsigned char *)pNotifier) + __nvoc_rtti_NvjpgContext_Notifier.offset)); } @@ -335,12 +343,16 @@ pThis->__nvjpgctxUnregisterEvent__ = &__nvoc_thunk_Notifier_nvjpgctxUnregisterEvent; + pThis->__nvjpgctxControlSerialization_Prologue__ = &__nvoc_thunk_RmResource_nvjpgctxControlSerialization_Prologue; + pThis->__nvjpgctxCanCopy__ = &__nvoc_thunk_RsResource_nvjpgctxCanCopy; pThis->__nvjpgctxPreDestruct__ = &__nvoc_thunk_RsResource_nvjpgctxPreDestruct; pThis->__nvjpgctxIsDuplicate__ = &__nvoc_thunk_RsResource_nvjpgctxIsDuplicate; + pThis->__nvjpgctxControlSerialization_Epilogue__ = &__nvoc_thunk_RmResource_nvjpgctxControlSerialization_Epilogue; + pThis->__nvjpgctxGetNotificationListPtr__ = &__nvoc_thunk_Notifier_nvjpgctxGetNotificationListPtr; pThis->__nvjpgctxGetNotificationShare__ = &__nvoc_thunk_Notifier_nvjpgctxGetNotificationShare; @@ -375,13 +387,16 @@ NvjpgContext *pThis; RmHalspecOwner *pRmhalspecowner; - pThis = portMemAllocNonPaged(sizeof(NvjpgContext)); - if (pThis == NULL) return NV_ERR_NO_MEMORY; + status = __nvoc_handleObjCreateMemAlloc(createFlags, sizeof(NvjpgContext), (void**)&pThis, (void**)ppThis); + if (status != NV_OK) + return status; portMemSet(pThis, 0, sizeof(NvjpgContext)); __nvoc_initRtti(staticCast(pThis, Dynamic), &__nvoc_class_def_NvjpgContext); + pThis->__nvoc_base_ChannelDescendant.__nvoc_base_GpuResource.__nvoc_base_RmResource.__nvoc_base_RsResource.__nvoc_base_Object.createFlags = createFlags; + if (pParent != NULL && !(createFlags & NVOC_OBJ_CREATE_FLAGS_PARENT_HALSPEC_ONLY)) { pParentObj = dynamicCast(pParent, Object); @@ -401,11 +416,17 @@ if (status != NV_OK) goto __nvoc_objCreate_NvjpgContext_cleanup; *ppThis = pThis; + return NV_OK; __nvoc_objCreate_NvjpgContext_cleanup: // do not call destructors here since the constructor already called them - portMemFree(pThis); + if (createFlags & NVOC_OBJ_CREATE_FLAGS_IN_PLACE_CONSTRUCT) + portMemSet(pThis, 0, sizeof(NvjpgContext)); + else + portMemFree(pThis); + + // coverity[leaked_storage:FALSE] return status; } diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/generated/g_kernel_nvjpg_ctx_nvoc.h nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_kernel_nvjpg_ctx_nvoc.h --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/generated/g_kernel_nvjpg_ctx_nvoc.h 2023-10-25 20:27:10.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_kernel_nvjpg_ctx_nvoc.h 2024-03-05 22:18:31.000000000 +0000 @@ -72,7 +72,7 @@ NV_STATUS (*__nvjpgctxUnmapFrom__)(struct NvjpgContext *, RS_RES_UNMAP_FROM_PARAMS *); void (*__nvjpgctxControl_Epilogue__)(struct NvjpgContext *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); NV_STATUS (*__nvjpgctxControlLookup__)(struct NvjpgContext *, struct RS_RES_CONTROL_PARAMS_INTERNAL *, const struct NVOC_EXPORTED_METHOD_DEF **); - NV_STATUS (*__nvjpgctxGetSwMethods__)(struct NvjpgContext *, METHOD **, NvU32 *); + NV_STATUS (*__nvjpgctxGetSwMethods__)(struct NvjpgContext *, const METHOD **, NvU32 *); NvHandle (*__nvjpgctxGetInternalObjectHandle__)(struct NvjpgContext *); NV_STATUS (*__nvjpgctxControl__)(struct NvjpgContext *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); NV_STATUS (*__nvjpgctxUnmap__)(struct NvjpgContext *, struct CALL_CONTEXT *, struct RsCpuMapping *); @@ -81,9 +81,11 @@ NvBool (*__nvjpgctxIsSwMethodStalling__)(struct NvjpgContext *, NvU32); NV_STATUS (*__nvjpgctxControlFilter__)(struct NvjpgContext *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); NV_STATUS (*__nvjpgctxUnregisterEvent__)(struct NvjpgContext *, NvHandle, NvHandle, NvHandle, NvHandle); + NV_STATUS (*__nvjpgctxControlSerialization_Prologue__)(struct NvjpgContext *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); NvBool (*__nvjpgctxCanCopy__)(struct NvjpgContext *); void (*__nvjpgctxPreDestruct__)(struct NvjpgContext *); NV_STATUS (*__nvjpgctxIsDuplicate__)(struct NvjpgContext *, NvHandle, NvBool *); + void (*__nvjpgctxControlSerialization_Epilogue__)(struct NvjpgContext *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); PEVENTNOTIFICATION *(*__nvjpgctxGetNotificationListPtr__)(struct NvjpgContext *); struct NotifShare *(*__nvjpgctxGetNotificationShare__)(struct NvjpgContext *); NV_STATUS (*__nvjpgctxMap__)(struct NvjpgContext *, struct CALL_CONTEXT *, struct RS_CPU_MAP_PARAMS *, struct RsCpuMapping *); @@ -141,9 +143,11 @@ #define nvjpgctxIsSwMethodStalling(pChannelDescendant, hHandle) nvjpgctxIsSwMethodStalling_DISPATCH(pChannelDescendant, hHandle) #define nvjpgctxControlFilter(pResource, pCallContext, pParams) nvjpgctxControlFilter_DISPATCH(pResource, pCallContext, pParams) #define nvjpgctxUnregisterEvent(pNotifier, hNotifierClient, hNotifierResource, hEventClient, hEvent) nvjpgctxUnregisterEvent_DISPATCH(pNotifier, hNotifierClient, hNotifierResource, hEventClient, hEvent) +#define nvjpgctxControlSerialization_Prologue(pResource, pCallContext, pParams) nvjpgctxControlSerialization_Prologue_DISPATCH(pResource, pCallContext, pParams) #define nvjpgctxCanCopy(pResource) nvjpgctxCanCopy_DISPATCH(pResource) #define nvjpgctxPreDestruct(pResource) nvjpgctxPreDestruct_DISPATCH(pResource) #define nvjpgctxIsDuplicate(pResource, hMemory, pDuplicate) nvjpgctxIsDuplicate_DISPATCH(pResource, hMemory, pDuplicate) +#define nvjpgctxControlSerialization_Epilogue(pResource, pCallContext, pParams) nvjpgctxControlSerialization_Epilogue_DISPATCH(pResource, pCallContext, pParams) #define nvjpgctxGetNotificationListPtr(pNotifier) nvjpgctxGetNotificationListPtr_DISPATCH(pNotifier) #define nvjpgctxGetNotificationShare(pNotifier) nvjpgctxGetNotificationShare_DISPATCH(pNotifier) #define nvjpgctxMap(pGpuResource, pCallContext, pParams, pCpuMapping) nvjpgctxMap_DISPATCH(pGpuResource, pCallContext, pParams, pCpuMapping) @@ -231,7 +235,7 @@ return pResource->__nvjpgctxControlLookup__(pResource, pParams, ppEntry); } -static inline NV_STATUS nvjpgctxGetSwMethods_DISPATCH(struct NvjpgContext *pChannelDescendant, METHOD **ppMethods, NvU32 *pNumMethods) { +static inline NV_STATUS nvjpgctxGetSwMethods_DISPATCH(struct NvjpgContext *pChannelDescendant, const METHOD **ppMethods, NvU32 *pNumMethods) { return pChannelDescendant->__nvjpgctxGetSwMethods__(pChannelDescendant, ppMethods, pNumMethods); } @@ -267,6 +271,10 @@ return pNotifier->__nvjpgctxUnregisterEvent__(pNotifier, hNotifierClient, hNotifierResource, hEventClient, hEvent); } +static inline NV_STATUS nvjpgctxControlSerialization_Prologue_DISPATCH(struct NvjpgContext *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return pResource->__nvjpgctxControlSerialization_Prologue__(pResource, pCallContext, pParams); +} + static inline NvBool nvjpgctxCanCopy_DISPATCH(struct NvjpgContext *pResource) { return pResource->__nvjpgctxCanCopy__(pResource); } @@ -279,6 +287,10 @@ return pResource->__nvjpgctxIsDuplicate__(pResource, hMemory, pDuplicate); } +static inline void nvjpgctxControlSerialization_Epilogue_DISPATCH(struct NvjpgContext *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + pResource->__nvjpgctxControlSerialization_Epilogue__(pResource, pCallContext, pParams); +} + static inline PEVENTNOTIFICATION *nvjpgctxGetNotificationListPtr_DISPATCH(struct NvjpgContext *pNotifier) { return pNotifier->__nvjpgctxGetNotificationListPtr__(pNotifier); } diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/generated/g_kernel_nvlink_nvoc.c nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_kernel_nvlink_nvoc.c --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/generated/g_kernel_nvlink_nvoc.c 2023-10-25 20:27:10.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_kernel_nvlink_nvoc.c 2024-03-05 22:18:31.000000000 +0000 @@ -94,10 +94,6 @@ return knvlinkIsPresent(arg0, (struct KernelNvlink *)(((unsigned char *)arg1) - __nvoc_rtti_KernelNvlink_OBJENGSTATE.offset)); } -static NV_STATUS __nvoc_thunk_OBJENGSTATE_knvlinkReconcileTunableState(POBJGPU pGpu, struct KernelNvlink *pEngstate, void *pTunableState) { - return engstateReconcileTunableState(pGpu, (struct OBJENGSTATE *)(((unsigned char *)pEngstate) + __nvoc_rtti_KernelNvlink_OBJENGSTATE.offset), pTunableState); -} - static NV_STATUS __nvoc_thunk_OBJENGSTATE_knvlinkStateInitLocked(POBJGPU pGpu, struct KernelNvlink *pEngstate) { return engstateStateInitLocked(pGpu, (struct OBJENGSTATE *)(((unsigned char *)pEngstate) + __nvoc_rtti_KernelNvlink_OBJENGSTATE.offset)); } @@ -126,26 +122,6 @@ return engstateStatePreInitUnlocked(pGpu, (struct OBJENGSTATE *)(((unsigned char *)pEngstate) + __nvoc_rtti_KernelNvlink_OBJENGSTATE.offset)); } -static NV_STATUS __nvoc_thunk_OBJENGSTATE_knvlinkGetTunableState(POBJGPU pGpu, struct KernelNvlink *pEngstate, void *pTunableState) { - return engstateGetTunableState(pGpu, (struct OBJENGSTATE *)(((unsigned char *)pEngstate) + __nvoc_rtti_KernelNvlink_OBJENGSTATE.offset), pTunableState); -} - -static NV_STATUS __nvoc_thunk_OBJENGSTATE_knvlinkCompareTunableState(POBJGPU pGpu, struct KernelNvlink *pEngstate, void *pTunables1, void *pTunables2) { - return engstateCompareTunableState(pGpu, (struct OBJENGSTATE *)(((unsigned char *)pEngstate) + __nvoc_rtti_KernelNvlink_OBJENGSTATE.offset), pTunables1, pTunables2); -} - -static void __nvoc_thunk_OBJENGSTATE_knvlinkFreeTunableState(POBJGPU pGpu, struct KernelNvlink *pEngstate, void *pTunableState) { - engstateFreeTunableState(pGpu, (struct OBJENGSTATE *)(((unsigned char *)pEngstate) + __nvoc_rtti_KernelNvlink_OBJENGSTATE.offset), pTunableState); -} - -static NV_STATUS __nvoc_thunk_OBJENGSTATE_knvlinkAllocTunableState(POBJGPU pGpu, struct KernelNvlink *pEngstate, void **ppTunableState) { - return engstateAllocTunableState(pGpu, (struct OBJENGSTATE *)(((unsigned char *)pEngstate) + __nvoc_rtti_KernelNvlink_OBJENGSTATE.offset), ppTunableState); -} - -static NV_STATUS __nvoc_thunk_OBJENGSTATE_knvlinkSetTunableState(POBJGPU pGpu, struct KernelNvlink *pEngstate, void *pTunableState) { - return engstateSetTunableState(pGpu, (struct OBJENGSTATE *)(((unsigned char *)pEngstate) + __nvoc_rtti_KernelNvlink_OBJENGSTATE.offset), pTunableState); -} - const struct NVOC_EXPORT_INFO __nvoc_export_info_KernelNvlink = { /*numEntries=*/ 0, @@ -324,308 +300,283 @@ pThis->__knvlinkIsPresent__ = &knvlinkIsPresent_IMPL; // Hal function -- knvlinkSetUniqueFabricBaseAddress - if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000002UL) )) /* RmVariantHal: PF_KERNEL_ONLY */ + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ + { + pThis->__knvlinkSetUniqueFabricBaseAddress__ = &knvlinkSetUniqueFabricBaseAddress_GH100; + } + else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x01f0fc00UL) )) /* ChipHal: GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 */ + { + pThis->__knvlinkSetUniqueFabricBaseAddress__ = &knvlinkSetUniqueFabricBaseAddress_GV100; + } + // default + else { - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x01f0fc00UL) )) /* ChipHal: GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 */ - { - pThis->__knvlinkSetUniqueFabricBaseAddress__ = &knvlinkSetUniqueFabricBaseAddress_GV100; - } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ - { - pThis->__knvlinkSetUniqueFabricBaseAddress__ = &knvlinkSetUniqueFabricBaseAddress_GH100; - } - // default - else - { - pThis->__knvlinkSetUniqueFabricBaseAddress__ = &knvlinkSetUniqueFabricBaseAddress_46f6a7; - } + pThis->__knvlinkSetUniqueFabricBaseAddress__ = &knvlinkSetUniqueFabricBaseAddress_46f6a7; + } + + // Hal function -- knvlinkClearUniqueFabricBaseAddress + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ + { + pThis->__knvlinkClearUniqueFabricBaseAddress__ = &knvlinkClearUniqueFabricBaseAddress_GH100; + } + // default + else + { + pThis->__knvlinkClearUniqueFabricBaseAddress__ = &knvlinkClearUniqueFabricBaseAddress_b3696a; } // Hal function -- knvlinkHandleFaultUpInterrupt - if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000002UL) )) /* RmVariantHal: PF_KERNEL_ONLY */ + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ { - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ - { - pThis->__knvlinkHandleFaultUpInterrupt__ = &knvlinkHandleFaultUpInterrupt_GH100; - } - // default - else - { - pThis->__knvlinkHandleFaultUpInterrupt__ = &knvlinkHandleFaultUpInterrupt_46f6a7; - } + pThis->__knvlinkHandleFaultUpInterrupt__ = &knvlinkHandleFaultUpInterrupt_GH100; + } + // default + else + { + pThis->__knvlinkHandleFaultUpInterrupt__ = &knvlinkHandleFaultUpInterrupt_46f6a7; } // Hal function -- knvlinkValidateFabricBaseAddress - if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000002UL) )) /* RmVariantHal: PF_KERNEL_ONLY */ + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ { - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x01f0fc00UL) )) /* ChipHal: GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 */ - { - pThis->__knvlinkValidateFabricBaseAddress__ = &knvlinkValidateFabricBaseAddress_GA100; - } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ - { - pThis->__knvlinkValidateFabricBaseAddress__ = &knvlinkValidateFabricBaseAddress_GH100; - } - // default - else - { - pThis->__knvlinkValidateFabricBaseAddress__ = &knvlinkValidateFabricBaseAddress_46f6a7; - } + pThis->__knvlinkValidateFabricBaseAddress__ = &knvlinkValidateFabricBaseAddress_GH100; + } + else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x01f0fc00UL) )) /* ChipHal: GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 */ + { + pThis->__knvlinkValidateFabricBaseAddress__ = &knvlinkValidateFabricBaseAddress_GA100; + } + // default + else + { + pThis->__knvlinkValidateFabricBaseAddress__ = &knvlinkValidateFabricBaseAddress_46f6a7; } // Hal function -- knvlinkGetConnectedLinksMask - if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000002UL) )) /* RmVariantHal: PF_KERNEL_ONLY */ + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000380UL) )) /* ChipHal: TU106 | TU116 | TU117 | GH100 */ + { + pThis->__knvlinkGetConnectedLinksMask__ = &knvlinkGetConnectedLinksMask_15a734; + } + else { - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x01f0fc60UL) )) /* ChipHal: TU102 | TU104 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 */ - { - pThis->__knvlinkGetConnectedLinksMask__ = &knvlinkGetConnectedLinksMask_TU102; - } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000380UL) )) /* ChipHal: TU106 | TU116 | TU117 | GH100 */ - { - pThis->__knvlinkGetConnectedLinksMask__ = &knvlinkGetConnectedLinksMask_15a734; - } + pThis->__knvlinkGetConnectedLinksMask__ = &knvlinkGetConnectedLinksMask_TU102; } // Hal function -- knvlinkEnableLinksPostTopology - if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000002UL) )) /* RmVariantHal: PF_KERNEL_ONLY */ + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x00000060UL) )) /* ChipHal: TU102 | TU104 */ + { + pThis->__knvlinkEnableLinksPostTopology__ = &knvlinkEnableLinksPostTopology_GV100; + } + else { - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x00000060UL) )) /* ChipHal: TU102 | TU104 */ - { - pThis->__knvlinkEnableLinksPostTopology__ = &knvlinkEnableLinksPostTopology_GV100; - } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x11f0ff80UL) )) /* ChipHal: TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 | GH100 */ - { - pThis->__knvlinkEnableLinksPostTopology__ = &knvlinkEnableLinksPostTopology_56cd7a; - } + pThis->__knvlinkEnableLinksPostTopology__ = &knvlinkEnableLinksPostTopology_56cd7a; } // Hal function -- knvlinkOverrideConfig - if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000002UL) )) /* RmVariantHal: PF_KERNEL_ONLY */ + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x00000060UL) )) /* ChipHal: TU102 | TU104 */ + { + pThis->__knvlinkOverrideConfig__ = &knvlinkOverrideConfig_GV100; + } + else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x00000380UL) )) /* ChipHal: TU106 | TU116 | TU117 */ { - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x00000060UL) )) /* ChipHal: TU102 | TU104 */ - { - pThis->__knvlinkOverrideConfig__ = &knvlinkOverrideConfig_GV100; - } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x11f0fc00UL) )) /* ChipHal: GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 | GH100 */ - { - pThis->__knvlinkOverrideConfig__ = &knvlinkOverrideConfig_GA100; - } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x00000380UL) )) /* ChipHal: TU106 | TU116 | TU117 */ - { - pThis->__knvlinkOverrideConfig__ = &knvlinkOverrideConfig_56cd7a; - } + pThis->__knvlinkOverrideConfig__ = &knvlinkOverrideConfig_56cd7a; + } + else + { + pThis->__knvlinkOverrideConfig__ = &knvlinkOverrideConfig_GA100; } // Hal function -- knvlinkFilterBridgeLinks - if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000002UL) )) /* RmVariantHal: PF_KERNEL_ONLY */ + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x00000380UL) )) /* ChipHal: TU106 | TU116 | TU117 */ + { + pThis->__knvlinkFilterBridgeLinks__ = &knvlinkFilterBridgeLinks_46f6a7; + } + else { - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x11f0fc60UL) )) /* ChipHal: TU102 | TU104 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 | GH100 */ - { - pThis->__knvlinkFilterBridgeLinks__ = &knvlinkFilterBridgeLinks_TU102; - } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x00000380UL) )) /* ChipHal: TU106 | TU116 | TU117 */ - { - pThis->__knvlinkFilterBridgeLinks__ = &knvlinkFilterBridgeLinks_46f6a7; - } + pThis->__knvlinkFilterBridgeLinks__ = &knvlinkFilterBridgeLinks_TU102; } // Hal function -- knvlinkGetUniquePeerIdMask - if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000002UL) )) /* RmVariantHal: PF_KERNEL_ONLY */ + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x00000060UL) )) /* ChipHal: TU102 | TU104 */ { - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x00000060UL) )) /* ChipHal: TU102 | TU104 */ - { - pThis->__knvlinkGetUniquePeerIdMask__ = &knvlinkGetUniquePeerIdMask_GP100; - } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x11f0ff80UL) )) /* ChipHal: TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 | GH100 */ - { - pThis->__knvlinkGetUniquePeerIdMask__ = &knvlinkGetUniquePeerIdMask_15a734; - } + pThis->__knvlinkGetUniquePeerIdMask__ = &knvlinkGetUniquePeerIdMask_GP100; + } + else + { + pThis->__knvlinkGetUniquePeerIdMask__ = &knvlinkGetUniquePeerIdMask_15a734; } // Hal function -- knvlinkGetUniquePeerId - if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000002UL) )) /* RmVariantHal: PF_KERNEL_ONLY */ + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x00000060UL) )) /* ChipHal: TU102 | TU104 */ { - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x00000060UL) )) /* ChipHal: TU102 | TU104 */ - { - pThis->__knvlinkGetUniquePeerId__ = &knvlinkGetUniquePeerId_GP100; - } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x11f0ff80UL) )) /* ChipHal: TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 | GH100 */ - { - pThis->__knvlinkGetUniquePeerId__ = &knvlinkGetUniquePeerId_c732fb; - } + pThis->__knvlinkGetUniquePeerId__ = &knvlinkGetUniquePeerId_GP100; + } + else + { + pThis->__knvlinkGetUniquePeerId__ = &knvlinkGetUniquePeerId_c732fb; } // Hal function -- knvlinkRemoveMapping - if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000002UL) )) /* RmVariantHal: PF_KERNEL_ONLY */ + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x00000060UL) )) /* ChipHal: TU102 | TU104 */ { - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x00000060UL) )) /* ChipHal: TU102 | TU104 */ - { - pThis->__knvlinkRemoveMapping__ = &knvlinkRemoveMapping_GP100; - } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x11f0fc00UL) )) /* ChipHal: GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 | GH100 */ - { - pThis->__knvlinkRemoveMapping__ = &knvlinkRemoveMapping_GA100; - } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x00000380UL) )) /* ChipHal: TU106 | TU116 | TU117 */ - { - pThis->__knvlinkRemoveMapping__ = &knvlinkRemoveMapping_56cd7a; - } + pThis->__knvlinkRemoveMapping__ = &knvlinkRemoveMapping_GP100; + } + else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x00000380UL) )) /* ChipHal: TU106 | TU116 | TU117 */ + { + pThis->__knvlinkRemoveMapping__ = &knvlinkRemoveMapping_56cd7a; + } + else + { + pThis->__knvlinkRemoveMapping__ = &knvlinkRemoveMapping_GA100; } // Hal function -- knvlinkGetP2POptimalCEs - if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000002UL) )) /* RmVariantHal: PF_KERNEL_ONLY */ + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x00000380UL) )) /* ChipHal: TU106 | TU116 | TU117 */ { - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x11f0fc60UL) )) /* ChipHal: TU102 | TU104 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 | GH100 */ - { - pThis->__knvlinkGetP2POptimalCEs__ = &knvlinkGetP2POptimalCEs_GP100; - } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x00000380UL) )) /* ChipHal: TU106 | TU116 | TU117 */ - { - pThis->__knvlinkGetP2POptimalCEs__ = &knvlinkGetP2POptimalCEs_56cd7a; - } + pThis->__knvlinkGetP2POptimalCEs__ = &knvlinkGetP2POptimalCEs_56cd7a; + } + else + { + pThis->__knvlinkGetP2POptimalCEs__ = &knvlinkGetP2POptimalCEs_GP100; } // Hal function -- knvlinkConstructHal - if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000002UL) )) /* RmVariantHal: PF_KERNEL_ONLY */ + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x00000380UL) )) /* ChipHal: TU106 | TU116 | TU117 */ { - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x11f0fc60UL) )) /* ChipHal: TU102 | TU104 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 | GH100 */ - { - pThis->__knvlinkConstructHal__ = &knvlinkConstructHal_GV100; - } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x00000380UL) )) /* ChipHal: TU106 | TU116 | TU117 */ - { - pThis->__knvlinkConstructHal__ = &knvlinkConstructHal_56cd7a; - } + pThis->__knvlinkConstructHal__ = &knvlinkConstructHal_56cd7a; + } + else + { + pThis->__knvlinkConstructHal__ = &knvlinkConstructHal_GV100; } // Hal function -- knvlinkSetupPeerMapping - if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000002UL) )) /* RmVariantHal: PF_KERNEL_ONLY */ + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x00000380UL) )) /* ChipHal: TU106 | TU116 | TU117 */ + { + pThis->__knvlinkSetupPeerMapping__ = &knvlinkSetupPeerMapping_b3696a; + } + else { - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x11f0fc60UL) )) /* ChipHal: TU102 | TU104 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 | GH100 */ - { - pThis->__knvlinkSetupPeerMapping__ = &knvlinkSetupPeerMapping_GP100; - } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x00000380UL) )) /* ChipHal: TU106 | TU116 | TU117 */ - { - pThis->__knvlinkSetupPeerMapping__ = &knvlinkSetupPeerMapping_b3696a; - } + pThis->__knvlinkSetupPeerMapping__ = &knvlinkSetupPeerMapping_GP100; } // Hal function -- knvlinkProgramLinkSpeed - if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000002UL) )) /* RmVariantHal: PF_KERNEL_ONLY */ + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x00000380UL) )) /* ChipHal: TU106 | TU116 | TU117 */ { - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x11f0fc60UL) )) /* ChipHal: TU102 | TU104 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 | GH100 */ - { - pThis->__knvlinkProgramLinkSpeed__ = &knvlinkProgramLinkSpeed_GV100; - } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x00000380UL) )) /* ChipHal: TU106 | TU116 | TU117 */ - { - pThis->__knvlinkProgramLinkSpeed__ = &knvlinkProgramLinkSpeed_56cd7a; - } + pThis->__knvlinkProgramLinkSpeed__ = &knvlinkProgramLinkSpeed_56cd7a; + } + else + { + pThis->__knvlinkProgramLinkSpeed__ = &knvlinkProgramLinkSpeed_GV100; } // Hal function -- knvlinkPoweredUpForD3 - if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000002UL) )) /* RmVariantHal: PF_KERNEL_ONLY */ + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x00000060UL) )) /* ChipHal: TU102 | TU104 */ { - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x00000060UL) )) /* ChipHal: TU102 | TU104 */ - { - pThis->__knvlinkPoweredUpForD3__ = &knvlinkPoweredUpForD3_TU102; - } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x11f0ff80UL) )) /* ChipHal: TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 | GH100 */ - { - pThis->__knvlinkPoweredUpForD3__ = &knvlinkPoweredUpForD3_491d52; - } + pThis->__knvlinkPoweredUpForD3__ = &knvlinkPoweredUpForD3_TU102; + } + else + { + pThis->__knvlinkPoweredUpForD3__ = &knvlinkPoweredUpForD3_491d52; } // Hal function -- knvlinkIsAliSupported - if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000002UL) )) /* RmVariantHal: PF_KERNEL_ONLY */ + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ { - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ - { - pThis->__knvlinkIsAliSupported__ = &knvlinkIsAliSupported_GH100; - } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x01f0ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 */ - { - pThis->__knvlinkIsAliSupported__ = &knvlinkIsAliSupported_56cd7a; - } + pThis->__knvlinkIsAliSupported__ = &knvlinkIsAliSupported_GH100; + } + else + { + pThis->__knvlinkIsAliSupported__ = &knvlinkIsAliSupported_56cd7a; } // Hal function -- knvlinkPostSetupNvlinkPeer - if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000002UL) )) /* RmVariantHal: PF_KERNEL_ONLY */ + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ + { + pThis->__knvlinkPostSetupNvlinkPeer__ = &knvlinkPostSetupNvlinkPeer_GH100; + } + else { - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ - { - pThis->__knvlinkPostSetupNvlinkPeer__ = &knvlinkPostSetupNvlinkPeer_GH100; - } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x01f0ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 */ - { - pThis->__knvlinkPostSetupNvlinkPeer__ = &knvlinkPostSetupNvlinkPeer_56cd7a; - } + pThis->__knvlinkPostSetupNvlinkPeer__ = &knvlinkPostSetupNvlinkPeer_56cd7a; } // Hal function -- knvlinkDiscoverPostRxDetLinks - if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000002UL) )) /* RmVariantHal: PF_KERNEL_ONLY */ + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ { - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ - { - pThis->__knvlinkDiscoverPostRxDetLinks__ = &knvlinkDiscoverPostRxDetLinks_GH100; - } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x01f0ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 */ - { - pThis->__knvlinkDiscoverPostRxDetLinks__ = &knvlinkDiscoverPostRxDetLinks_46f6a7; - } + pThis->__knvlinkDiscoverPostRxDetLinks__ = &knvlinkDiscoverPostRxDetLinks_GH100; + } + else + { + pThis->__knvlinkDiscoverPostRxDetLinks__ = &knvlinkDiscoverPostRxDetLinks_46f6a7; } // Hal function -- knvlinkLogAliDebugMessages - if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000002UL) )) /* RmVariantHal: PF_KERNEL_ONLY */ + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ + { + pThis->__knvlinkLogAliDebugMessages__ = &knvlinkLogAliDebugMessages_GH100; + } + else { - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ - { - pThis->__knvlinkLogAliDebugMessages__ = &knvlinkLogAliDebugMessages_GH100; - } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x01f0ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 */ - { - pThis->__knvlinkLogAliDebugMessages__ = &knvlinkLogAliDebugMessages_46f6a7; - } + pThis->__knvlinkLogAliDebugMessages__ = &knvlinkLogAliDebugMessages_46f6a7; } - // Hal function -- knvlinkIsFloorSweepingNeeded - if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000002UL) )) /* RmVariantHal: PF_KERNEL_ONLY */ + // Hal function -- knvlinkGetEffectivePeerLinkMask + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ + { + pThis->__knvlinkGetEffectivePeerLinkMask__ = &knvlinkGetEffectivePeerLinkMask_GH100; + } + else + { + pThis->__knvlinkGetEffectivePeerLinkMask__ = &knvlinkGetEffectivePeerLinkMask_b3696a; + } + + // Hal function -- knvlinkGetNumLinksToBeReducedPerIoctrl + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ + { + pThis->__knvlinkGetNumLinksToBeReducedPerIoctrl__ = &knvlinkGetNumLinksToBeReducedPerIoctrl_GH100; + } + else + { + pThis->__knvlinkGetNumLinksToBeReducedPerIoctrl__ = &knvlinkGetNumLinksToBeReducedPerIoctrl_4a4dee; + } + + // Hal function -- knvlinkIsBandwidthModeOff + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ + { + pThis->__knvlinkIsBandwidthModeOff__ = &knvlinkIsBandwidthModeOff_GH100; + } + else { - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ - { - pThis->__knvlinkIsFloorSweepingNeeded__ = &knvlinkIsFloorSweepingNeeded_GH100; - } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x01f0ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 */ - { - pThis->__knvlinkIsFloorSweepingNeeded__ = &knvlinkIsFloorSweepingNeeded_491d52; - } + pThis->__knvlinkIsBandwidthModeOff__ = &knvlinkIsBandwidthModeOff_491d52; } // Hal function -- knvlinkDirectConnectCheck - if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000002UL) )) /* RmVariantHal: PF_KERNEL_ONLY */ + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ { - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ - { - pThis->__knvlinkDirectConnectCheck__ = &knvlinkDirectConnectCheck_GH100; - } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x01f0ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 */ - { - pThis->__knvlinkDirectConnectCheck__ = &knvlinkDirectConnectCheck_b3696a; - } + pThis->__knvlinkDirectConnectCheck__ = &knvlinkDirectConnectCheck_GH100; + } + else + { + pThis->__knvlinkDirectConnectCheck__ = &knvlinkDirectConnectCheck_b3696a; } // Hal function -- knvlinkIsGpuReducedNvlinkConfig - if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000002UL) )) /* RmVariantHal: PF_KERNEL_ONLY */ + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0000fc00UL) )) /* ChipHal: GA100 | GA102 | GA103 | GA104 | GA106 | GA107 */ + { + pThis->__knvlinkIsGpuReducedNvlinkConfig__ = &knvlinkIsGpuReducedNvlinkConfig_GA100; + } + else { - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0000fc00UL) )) /* ChipHal: GA100 | GA102 | GA103 | GA104 | GA106 | GA107 */ - { - pThis->__knvlinkIsGpuReducedNvlinkConfig__ = &knvlinkIsGpuReducedNvlinkConfig_GA100; - } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x11f003e0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | AD102 | AD103 | AD104 | AD106 | AD107 | GH100 */ - { - pThis->__knvlinkIsGpuReducedNvlinkConfig__ = &knvlinkIsGpuReducedNvlinkConfig_491d52; - } + pThis->__knvlinkIsGpuReducedNvlinkConfig__ = &knvlinkIsGpuReducedNvlinkConfig_491d52; + } + + // Hal function -- knvlinkIsFloorSweepingNeeded + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ + { + pThis->__knvlinkIsFloorSweepingNeeded__ = &knvlinkIsFloorSweepingNeeded_GH100; + } + else + { + pThis->__knvlinkIsFloorSweepingNeeded__ = &knvlinkIsFloorSweepingNeeded_491d52; } pThis->__nvoc_base_OBJENGSTATE.__engstateConstructEngine__ = &__nvoc_thunk_KernelNvlink_engstateConstructEngine; @@ -642,8 +593,6 @@ pThis->__nvoc_base_OBJENGSTATE.__engstateIsPresent__ = &__nvoc_thunk_KernelNvlink_engstateIsPresent; - pThis->__knvlinkReconcileTunableState__ = &__nvoc_thunk_OBJENGSTATE_knvlinkReconcileTunableState; - pThis->__knvlinkStateInitLocked__ = &__nvoc_thunk_OBJENGSTATE_knvlinkStateInitLocked; pThis->__knvlinkStatePreLoad__ = &__nvoc_thunk_OBJENGSTATE_knvlinkStatePreLoad; @@ -657,16 +606,6 @@ pThis->__knvlinkInitMissing__ = &__nvoc_thunk_OBJENGSTATE_knvlinkInitMissing; pThis->__knvlinkStatePreInitUnlocked__ = &__nvoc_thunk_OBJENGSTATE_knvlinkStatePreInitUnlocked; - - pThis->__knvlinkGetTunableState__ = &__nvoc_thunk_OBJENGSTATE_knvlinkGetTunableState; - - pThis->__knvlinkCompareTunableState__ = &__nvoc_thunk_OBJENGSTATE_knvlinkCompareTunableState; - - pThis->__knvlinkFreeTunableState__ = &__nvoc_thunk_OBJENGSTATE_knvlinkFreeTunableState; - - pThis->__knvlinkAllocTunableState__ = &__nvoc_thunk_OBJENGSTATE_knvlinkAllocTunableState; - - pThis->__knvlinkSetTunableState__ = &__nvoc_thunk_OBJENGSTATE_knvlinkSetTunableState; } void __nvoc_init_funcTable_KernelNvlink(KernelNvlink *pThis, RmHalspecOwner *pRmhalspecowner) { @@ -688,13 +627,16 @@ KernelNvlink *pThis; RmHalspecOwner *pRmhalspecowner; - pThis = portMemAllocNonPaged(sizeof(KernelNvlink)); - if (pThis == NULL) return NV_ERR_NO_MEMORY; + status = __nvoc_handleObjCreateMemAlloc(createFlags, sizeof(KernelNvlink), (void**)&pThis, (void**)ppThis); + if (status != NV_OK) + return status; portMemSet(pThis, 0, sizeof(KernelNvlink)); __nvoc_initRtti(staticCast(pThis, Dynamic), &__nvoc_class_def_KernelNvlink); + pThis->__nvoc_base_OBJENGSTATE.__nvoc_base_Object.createFlags = createFlags; + if (pParent != NULL && !(createFlags & NVOC_OBJ_CREATE_FLAGS_PARENT_HALSPEC_ONLY)) { pParentObj = dynamicCast(pParent, Object); @@ -714,11 +656,17 @@ if (status != NV_OK) goto __nvoc_objCreate_KernelNvlink_cleanup; *ppThis = pThis; + return NV_OK; __nvoc_objCreate_KernelNvlink_cleanup: // do not call destructors here since the constructor already called them - portMemFree(pThis); + if (createFlags & NVOC_OBJ_CREATE_FLAGS_IN_PLACE_CONSTRUCT) + portMemSet(pThis, 0, sizeof(KernelNvlink)); + else + portMemFree(pThis); + + // coverity[leaked_storage:FALSE] return status; } diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/generated/g_kernel_nvlink_nvoc.h nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_kernel_nvlink_nvoc.h --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/generated/g_kernel_nvlink_nvoc.h 2023-10-25 20:27:10.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_kernel_nvlink_nvoc.h 2024-03-05 22:18:31.000000000 +0000 @@ -81,6 +81,7 @@ #define NVLINK_VERSION_30 0x00000005 #define NVLINK_VERSION_31 0x00000006 #define NVLINK_VERSION_40 0x00000007 +#define NVLINK_VERSION_50 0x00000008 // Maximum links the GPU NVLink SW can currently support #define NVLINK_MAX_LINKS_SW 18 @@ -190,7 +191,7 @@ typedef struct NVLINK_INBAND_CALLBACK { NvU32 messageType; - void (*pCallback)(OBJGPU *pGpu, + NV_STATUS (*pCallback)(NvU32 gpuInstance, NV2080_CTRL_NVLINK_INBAND_RECEIVED_DATA_PARAMS *pMessage); NvU32 wqItemFlags; } NVLINK_INBAND_MSG_CALLBACK; @@ -227,6 +228,7 @@ NV_STATUS (*__knvlinkStatePostUnload__)(OBJGPU *, struct KernelNvlink *, NvU32); NvBool (*__knvlinkIsPresent__)(OBJGPU *, struct KernelNvlink *); NV_STATUS (*__knvlinkSetUniqueFabricBaseAddress__)(OBJGPU *, struct KernelNvlink *, NvU64); + void (*__knvlinkClearUniqueFabricBaseAddress__)(OBJGPU *, struct KernelNvlink *); NV_STATUS (*__knvlinkHandleFaultUpInterrupt__)(OBJGPU *, struct KernelNvlink *, NvU32); NV_STATUS (*__knvlinkValidateFabricBaseAddress__)(OBJGPU *, struct KernelNvlink *, NvU64); NvU32 (*__knvlinkGetConnectedLinksMask__)(OBJGPU *, struct KernelNvlink *); @@ -245,10 +247,12 @@ NV_STATUS (*__knvlinkPostSetupNvlinkPeer__)(OBJGPU *, struct KernelNvlink *); NV_STATUS (*__knvlinkDiscoverPostRxDetLinks__)(OBJGPU *, struct KernelNvlink *, OBJGPU *); NV_STATUS (*__knvlinkLogAliDebugMessages__)(OBJGPU *, struct KernelNvlink *); - NvBool (*__knvlinkIsFloorSweepingNeeded__)(OBJGPU *, struct KernelNvlink *, NvU32, NvU32); + void (*__knvlinkGetEffectivePeerLinkMask__)(OBJGPU *, struct KernelNvlink *, OBJGPU *, NvU32 *); + NvU32 (*__knvlinkGetNumLinksToBeReducedPerIoctrl__)(struct KernelNvlink *); + NvBool (*__knvlinkIsBandwidthModeOff__)(struct KernelNvlink *); void (*__knvlinkDirectConnectCheck__)(OBJGPU *, struct KernelNvlink *); NvBool (*__knvlinkIsGpuReducedNvlinkConfig__)(OBJGPU *, struct KernelNvlink *); - NV_STATUS (*__knvlinkReconcileTunableState__)(POBJGPU, struct KernelNvlink *, void *); + NvBool (*__knvlinkIsFloorSweepingNeeded__)(OBJGPU *, struct KernelNvlink *, NvU32, NvU32); NV_STATUS (*__knvlinkStateInitLocked__)(POBJGPU, struct KernelNvlink *); NV_STATUS (*__knvlinkStatePreLoad__)(POBJGPU, struct KernelNvlink *, NvU32); void (*__knvlinkStateDestroy__)(POBJGPU, struct KernelNvlink *); @@ -256,13 +260,7 @@ NV_STATUS (*__knvlinkStateInitUnlocked__)(POBJGPU, struct KernelNvlink *); void (*__knvlinkInitMissing__)(POBJGPU, struct KernelNvlink *); NV_STATUS (*__knvlinkStatePreInitUnlocked__)(POBJGPU, struct KernelNvlink *); - NV_STATUS (*__knvlinkGetTunableState__)(POBJGPU, struct KernelNvlink *, void *); - NV_STATUS (*__knvlinkCompareTunableState__)(POBJGPU, struct KernelNvlink *, void *, void *); - void (*__knvlinkFreeTunableState__)(POBJGPU, struct KernelNvlink *, void *); - NV_STATUS (*__knvlinkAllocTunableState__)(POBJGPU, struct KernelNvlink *, void **); - NV_STATUS (*__knvlinkSetTunableState__)(POBJGPU, struct KernelNvlink *, void *); NvBool PDB_PROP_KNVLINK_ENABLED; - NvBool PDB_PROP_KNVLINK_SINGLE_LANE_POWER_STATE_ENABLED; NvBool PDB_PROP_KNVLINK_L2_POWER_STATE_ENABLED; NvBool PDB_PROP_KNVLINK_UNSET_NVLINK_PEER_SUPPORTED; NvBool PDB_PROP_KNVLINK_CONFIG_REQUIRE_INITIALIZED_LINKS_CHECK; @@ -276,54 +274,53 @@ NvBool PDB_PROP_KNVLINK_MINION_FORCE_NON_ALI_TRAINING; NvBool PDB_PROP_KNVLINK_MINION_GFW_BOOT; NvBool PDB_PROP_KNVLINK_SYSMEM_SUPPORT_ENABLED; - struct KernelIoctrl *pKernelIoctrl[3]; - NvU32 ioctrlMask; - NvU32 ipVerNvlink; - NvU8 ioctrlNumEntries; - NvU32 ioctrlSize; - NvU32 registryControl; - NvU32 minionControl; - NvU32 verboseMask; - NvU32 *pLinkConnection; - NvBool bChiplibConfig; - NvBool bRegistryLinkOverride; - NvU32 registryLinkMask; - NvBool bOverrideComputePeerMode; - NvU32 discoveredLinks; - NvU32 vbiosDisabledLinkMask; - NvU32 regkeyDisabledLinksMask; - NvU32 initDisabledLinksMask; - NvU32 connectedLinksMask; - NvU32 bridgeSensableLinks; - NvU32 bridgedLinks; - NvU32 enabledLinks; - FaultUpList faultUpLinks; - NvU32 initializedLinks; - KNVLINK_RM_LINK nvlinkLinks[18]; - NvBool bIsGpuDegraded; - NvU32 postRxDetLinkMask; - NvU32 disconnectedLinkMask; - NvU32 sysmemLinkMask; - NvU32 peerLinkMasks[32]; - NvU32 forcedSysmemDeviceType; - NVLINK_INBAND_MSG_CALLBACK inbandCallback[5]; - nvlink_device *pNvlinkDev; - NvU32 deviceLockRefcount; - NvBool bVerifTrainingEnable; - NvBool bL2Entry; - NvBool bSkipLinkTraining; - NvBool bForceAutoconfig; - NvBool bForceEnableCoreLibRtlsims; - NvBool bEnableTrainingAtLoad; - NvBool bEnableSafeModeAtLoad; - NvBool bEnableAli; - NvBool bFloorSwept; - NvBool bLinkTrainingDebugSpew; - NvBool bDisableSingleLaneMode; - NvBool bDisableL2Mode; - NvU32 nvlinkLinkSpeed; - NvU32 errorRecoveries[18]; - NvBool bNvswitchProxy; + struct KernelIoctrl *PRIVATE_FIELD(pKernelIoctrl)[3]; + NvU32 PRIVATE_FIELD(ioctrlMask); + NvU32 PRIVATE_FIELD(ipVerNvlink); + NvU8 PRIVATE_FIELD(ioctrlNumEntries); + NvU32 PRIVATE_FIELD(ioctrlSize); + NvU32 PRIVATE_FIELD(registryControl); + NvU32 PRIVATE_FIELD(minionControl); + NvU32 PRIVATE_FIELD(verboseMask); + NvU32 *PRIVATE_FIELD(pLinkConnection); + NvBool PRIVATE_FIELD(bChiplibConfig); + NvBool PRIVATE_FIELD(bRegistryLinkOverride); + NvU32 PRIVATE_FIELD(registryLinkMask); + NvBool PRIVATE_FIELD(bOverrideComputePeerMode); + NvU32 PRIVATE_FIELD(discoveredLinks); + NvU32 PRIVATE_FIELD(vbiosDisabledLinkMask); + NvU32 PRIVATE_FIELD(regkeyDisabledLinksMask); + NvU32 PRIVATE_FIELD(initDisabledLinksMask); + NvU32 PRIVATE_FIELD(connectedLinksMask); + NvU32 PRIVATE_FIELD(bridgeSensableLinks); + NvU32 PRIVATE_FIELD(bridgedLinks); + NvU32 PRIVATE_FIELD(enabledLinks); + FaultUpList PRIVATE_FIELD(faultUpLinks); + NvU32 PRIVATE_FIELD(initializedLinks); + KNVLINK_RM_LINK PRIVATE_FIELD(nvlinkLinks)[18]; + NvBool PRIVATE_FIELD(bIsGpuDegraded); + NvU32 PRIVATE_FIELD(postRxDetLinkMask); + NvU32 PRIVATE_FIELD(disconnectedLinkMask); + NvU32 PRIVATE_FIELD(sysmemLinkMask); + NvU32 PRIVATE_FIELD(peerLinkMasks)[32]; + NvU32 PRIVATE_FIELD(forcedSysmemDeviceType); + NVLINK_INBAND_MSG_CALLBACK PRIVATE_FIELD(inbandCallback)[5]; + nvlink_device *PRIVATE_FIELD(pNvlinkDev); + NvU32 PRIVATE_FIELD(deviceLockRefcount); + NvBool PRIVATE_FIELD(bVerifTrainingEnable); + NvBool PRIVATE_FIELD(bL2Entry); + NvBool PRIVATE_FIELD(bSkipLinkTraining); + NvBool PRIVATE_FIELD(bForceAutoconfig); + NvBool PRIVATE_FIELD(bForceEnableCoreLibRtlsims); + NvBool PRIVATE_FIELD(bEnableTrainingAtLoad); + NvBool PRIVATE_FIELD(bEnableSafeModeAtLoad); + NvBool PRIVATE_FIELD(bEnableAli); + NvBool PRIVATE_FIELD(bFloorSwept); + NvBool PRIVATE_FIELD(bLinkTrainingDebugSpew); + NvBool PRIVATE_FIELD(bDisableL2Mode); + NvU32 PRIVATE_FIELD(nvlinkLinkSpeed); + NvU32 PRIVATE_FIELD(errorRecoveries)[18]; + NvBool PRIVATE_FIELD(bNvswitchProxy); NvU64 fabricBaseAddr; }; @@ -370,8 +367,6 @@ #define PDB_PROP_KNVLINK_IS_MISSING_BASE_NAME PDB_PROP_ENGSTATE_IS_MISSING #define PDB_PROP_KNVLINK_WAR_BUG_3471679_PEERID_FILTERING_BASE_CAST #define PDB_PROP_KNVLINK_WAR_BUG_3471679_PEERID_FILTERING_BASE_NAME PDB_PROP_KNVLINK_WAR_BUG_3471679_PEERID_FILTERING -#define PDB_PROP_KNVLINK_SINGLE_LANE_POWER_STATE_ENABLED_BASE_CAST -#define PDB_PROP_KNVLINK_SINGLE_LANE_POWER_STATE_ENABLED_BASE_NAME PDB_PROP_KNVLINK_SINGLE_LANE_POWER_STATE_ENABLED #define PDB_PROP_KNVLINK_BUG2274645_RESET_FOR_RTD3_FGC6_BASE_CAST #define PDB_PROP_KNVLINK_BUG2274645_RESET_FOR_RTD3_FGC6_BASE_NAME PDB_PROP_KNVLINK_BUG2274645_RESET_FOR_RTD3_FGC6 #define PDB_PROP_KNVLINK_LANE_SHUTDOWN_ON_UNLOAD_BASE_CAST @@ -396,6 +391,8 @@ #define knvlinkIsPresent(arg0, arg1) knvlinkIsPresent_DISPATCH(arg0, arg1) #define knvlinkSetUniqueFabricBaseAddress(pGpu, pKernelNvlink, arg0) knvlinkSetUniqueFabricBaseAddress_DISPATCH(pGpu, pKernelNvlink, arg0) #define knvlinkSetUniqueFabricBaseAddress_HAL(pGpu, pKernelNvlink, arg0) knvlinkSetUniqueFabricBaseAddress_DISPATCH(pGpu, pKernelNvlink, arg0) +#define knvlinkClearUniqueFabricBaseAddress(pGpu, pKernelNvlink) knvlinkClearUniqueFabricBaseAddress_DISPATCH(pGpu, pKernelNvlink) +#define knvlinkClearUniqueFabricBaseAddress_HAL(pGpu, pKernelNvlink) knvlinkClearUniqueFabricBaseAddress_DISPATCH(pGpu, pKernelNvlink) #define knvlinkHandleFaultUpInterrupt(pGpu, pKernelNvlink, arg0) knvlinkHandleFaultUpInterrupt_DISPATCH(pGpu, pKernelNvlink, arg0) #define knvlinkHandleFaultUpInterrupt_HAL(pGpu, pKernelNvlink, arg0) knvlinkHandleFaultUpInterrupt_DISPATCH(pGpu, pKernelNvlink, arg0) #define knvlinkValidateFabricBaseAddress(pGpu, pKernelNvlink, arg0) knvlinkValidateFabricBaseAddress_DISPATCH(pGpu, pKernelNvlink, arg0) @@ -432,13 +429,18 @@ #define knvlinkDiscoverPostRxDetLinks_HAL(pGpu, pKernelNvlink, pPeerGpu) knvlinkDiscoverPostRxDetLinks_DISPATCH(pGpu, pKernelNvlink, pPeerGpu) #define knvlinkLogAliDebugMessages(pGpu, pKernelNvlink) knvlinkLogAliDebugMessages_DISPATCH(pGpu, pKernelNvlink) #define knvlinkLogAliDebugMessages_HAL(pGpu, pKernelNvlink) knvlinkLogAliDebugMessages_DISPATCH(pGpu, pKernelNvlink) -#define knvlinkIsFloorSweepingNeeded(pGpu, pKernelNvlink, numActiveLinksPerIoctrl, numLinksPerIoctrl) knvlinkIsFloorSweepingNeeded_DISPATCH(pGpu, pKernelNvlink, numActiveLinksPerIoctrl, numLinksPerIoctrl) -#define knvlinkIsFloorSweepingNeeded_HAL(pGpu, pKernelNvlink, numActiveLinksPerIoctrl, numLinksPerIoctrl) knvlinkIsFloorSweepingNeeded_DISPATCH(pGpu, pKernelNvlink, numActiveLinksPerIoctrl, numLinksPerIoctrl) +#define knvlinkGetEffectivePeerLinkMask(pGpu, pKernelNvlink, pRemoteGpu, pPeerLinkMask) knvlinkGetEffectivePeerLinkMask_DISPATCH(pGpu, pKernelNvlink, pRemoteGpu, pPeerLinkMask) +#define knvlinkGetEffectivePeerLinkMask_HAL(pGpu, pKernelNvlink, pRemoteGpu, pPeerLinkMask) knvlinkGetEffectivePeerLinkMask_DISPATCH(pGpu, pKernelNvlink, pRemoteGpu, pPeerLinkMask) +#define knvlinkGetNumLinksToBeReducedPerIoctrl(pKernelNvlink) knvlinkGetNumLinksToBeReducedPerIoctrl_DISPATCH(pKernelNvlink) +#define knvlinkGetNumLinksToBeReducedPerIoctrl_HAL(pKernelNvlink) knvlinkGetNumLinksToBeReducedPerIoctrl_DISPATCH(pKernelNvlink) +#define knvlinkIsBandwidthModeOff(pKernelNvlink) knvlinkIsBandwidthModeOff_DISPATCH(pKernelNvlink) +#define knvlinkIsBandwidthModeOff_HAL(pKernelNvlink) knvlinkIsBandwidthModeOff_DISPATCH(pKernelNvlink) #define knvlinkDirectConnectCheck(pGpu, pKernelNvlink) knvlinkDirectConnectCheck_DISPATCH(pGpu, pKernelNvlink) #define knvlinkDirectConnectCheck_HAL(pGpu, pKernelNvlink) knvlinkDirectConnectCheck_DISPATCH(pGpu, pKernelNvlink) #define knvlinkIsGpuReducedNvlinkConfig(pGpu, pKernelNvlink) knvlinkIsGpuReducedNvlinkConfig_DISPATCH(pGpu, pKernelNvlink) #define knvlinkIsGpuReducedNvlinkConfig_HAL(pGpu, pKernelNvlink) knvlinkIsGpuReducedNvlinkConfig_DISPATCH(pGpu, pKernelNvlink) -#define knvlinkReconcileTunableState(pGpu, pEngstate, pTunableState) knvlinkReconcileTunableState_DISPATCH(pGpu, pEngstate, pTunableState) +#define knvlinkIsFloorSweepingNeeded(pGpu, pKernelNvlink, numActiveLinksPerIoctrl, numLinksPerIoctrl) knvlinkIsFloorSweepingNeeded_DISPATCH(pGpu, pKernelNvlink, numActiveLinksPerIoctrl, numLinksPerIoctrl) +#define knvlinkIsFloorSweepingNeeded_HAL(pGpu, pKernelNvlink, numActiveLinksPerIoctrl, numLinksPerIoctrl) knvlinkIsFloorSweepingNeeded_DISPATCH(pGpu, pKernelNvlink, numActiveLinksPerIoctrl, numLinksPerIoctrl) #define knvlinkStateInitLocked(pGpu, pEngstate) knvlinkStateInitLocked_DISPATCH(pGpu, pEngstate) #define knvlinkStatePreLoad(pGpu, pEngstate, arg0) knvlinkStatePreLoad_DISPATCH(pGpu, pEngstate, arg0) #define knvlinkStateDestroy(pGpu, pEngstate) knvlinkStateDestroy_DISPATCH(pGpu, pEngstate) @@ -446,11 +448,6 @@ #define knvlinkStateInitUnlocked(pGpu, pEngstate) knvlinkStateInitUnlocked_DISPATCH(pGpu, pEngstate) #define knvlinkInitMissing(pGpu, pEngstate) knvlinkInitMissing_DISPATCH(pGpu, pEngstate) #define knvlinkStatePreInitUnlocked(pGpu, pEngstate) knvlinkStatePreInitUnlocked_DISPATCH(pGpu, pEngstate) -#define knvlinkGetTunableState(pGpu, pEngstate, pTunableState) knvlinkGetTunableState_DISPATCH(pGpu, pEngstate, pTunableState) -#define knvlinkCompareTunableState(pGpu, pEngstate, pTunables1, pTunables2) knvlinkCompareTunableState_DISPATCH(pGpu, pEngstate, pTunables1, pTunables2) -#define knvlinkFreeTunableState(pGpu, pEngstate, pTunableState) knvlinkFreeTunableState_DISPATCH(pGpu, pEngstate, pTunableState) -#define knvlinkAllocTunableState(pGpu, pEngstate, ppTunableState) knvlinkAllocTunableState_DISPATCH(pGpu, pEngstate, ppTunableState) -#define knvlinkSetTunableState(pGpu, pEngstate, pTunableState) knvlinkSetTunableState_DISPATCH(pGpu, pEngstate, pTunableState) NvBool knvlinkIsForcedConfig_IMPL(OBJGPU *arg0, struct KernelNvlink *arg1); @@ -1370,6 +1367,16 @@ return pKernelNvlink->__knvlinkSetUniqueFabricBaseAddress__(pGpu, pKernelNvlink, arg0); } +static inline void knvlinkClearUniqueFabricBaseAddress_b3696a(OBJGPU *pGpu, struct KernelNvlink *pKernelNvlink) { + return; +} + +void knvlinkClearUniqueFabricBaseAddress_GH100(OBJGPU *pGpu, struct KernelNvlink *pKernelNvlink); + +static inline void knvlinkClearUniqueFabricBaseAddress_DISPATCH(OBJGPU *pGpu, struct KernelNvlink *pKernelNvlink) { + pKernelNvlink->__knvlinkClearUniqueFabricBaseAddress__(pGpu, pKernelNvlink); +} + NV_STATUS knvlinkHandleFaultUpInterrupt_GH100(OBJGPU *pGpu, struct KernelNvlink *pKernelNvlink, NvU32 arg0); static inline NV_STATUS knvlinkHandleFaultUpInterrupt_46f6a7(OBJGPU *pGpu, struct KernelNvlink *pKernelNvlink, NvU32 arg0) { @@ -1556,14 +1563,34 @@ return pKernelNvlink->__knvlinkLogAliDebugMessages__(pGpu, pKernelNvlink); } -static inline NvBool knvlinkIsFloorSweepingNeeded_491d52(OBJGPU *pGpu, struct KernelNvlink *pKernelNvlink, NvU32 numActiveLinksPerIoctrl, NvU32 numLinksPerIoctrl) { +static inline void knvlinkGetEffectivePeerLinkMask_b3696a(OBJGPU *pGpu, struct KernelNvlink *pKernelNvlink, OBJGPU *pRemoteGpu, NvU32 *pPeerLinkMask) { + return; +} + +void knvlinkGetEffectivePeerLinkMask_GH100(OBJGPU *pGpu, struct KernelNvlink *pKernelNvlink, OBJGPU *pRemoteGpu, NvU32 *pPeerLinkMask); + +static inline void knvlinkGetEffectivePeerLinkMask_DISPATCH(OBJGPU *pGpu, struct KernelNvlink *pKernelNvlink, OBJGPU *pRemoteGpu, NvU32 *pPeerLinkMask) { + pKernelNvlink->__knvlinkGetEffectivePeerLinkMask__(pGpu, pKernelNvlink, pRemoteGpu, pPeerLinkMask); +} + +static inline NvU32 knvlinkGetNumLinksToBeReducedPerIoctrl_4a4dee(struct KernelNvlink *pKernelNvlink) { + return 0; +} + +NvU32 knvlinkGetNumLinksToBeReducedPerIoctrl_GH100(struct KernelNvlink *pKernelNvlink); + +static inline NvU32 knvlinkGetNumLinksToBeReducedPerIoctrl_DISPATCH(struct KernelNvlink *pKernelNvlink) { + return pKernelNvlink->__knvlinkGetNumLinksToBeReducedPerIoctrl__(pKernelNvlink); +} + +static inline NvBool knvlinkIsBandwidthModeOff_491d52(struct KernelNvlink *pKernelNvlink) { return ((NvBool)(0 != 0)); } -NvBool knvlinkIsFloorSweepingNeeded_GH100(OBJGPU *pGpu, struct KernelNvlink *pKernelNvlink, NvU32 numActiveLinksPerIoctrl, NvU32 numLinksPerIoctrl); +NvBool knvlinkIsBandwidthModeOff_GH100(struct KernelNvlink *pKernelNvlink); -static inline NvBool knvlinkIsFloorSweepingNeeded_DISPATCH(OBJGPU *pGpu, struct KernelNvlink *pKernelNvlink, NvU32 numActiveLinksPerIoctrl, NvU32 numLinksPerIoctrl) { - return pKernelNvlink->__knvlinkIsFloorSweepingNeeded__(pGpu, pKernelNvlink, numActiveLinksPerIoctrl, numLinksPerIoctrl); +static inline NvBool knvlinkIsBandwidthModeOff_DISPATCH(struct KernelNvlink *pKernelNvlink) { + return pKernelNvlink->__knvlinkIsBandwidthModeOff__(pKernelNvlink); } static inline void knvlinkDirectConnectCheck_b3696a(OBJGPU *pGpu, struct KernelNvlink *pKernelNvlink) { @@ -1586,8 +1613,14 @@ return pKernelNvlink->__knvlinkIsGpuReducedNvlinkConfig__(pGpu, pKernelNvlink); } -static inline NV_STATUS knvlinkReconcileTunableState_DISPATCH(POBJGPU pGpu, struct KernelNvlink *pEngstate, void *pTunableState) { - return pEngstate->__knvlinkReconcileTunableState__(pGpu, pEngstate, pTunableState); +static inline NvBool knvlinkIsFloorSweepingNeeded_491d52(OBJGPU *pGpu, struct KernelNvlink *pKernelNvlink, NvU32 numActiveLinksPerIoctrl, NvU32 numLinksPerIoctrl) { + return ((NvBool)(0 != 0)); +} + +NvBool knvlinkIsFloorSweepingNeeded_GH100(OBJGPU *pGpu, struct KernelNvlink *pKernelNvlink, NvU32 numActiveLinksPerIoctrl, NvU32 numLinksPerIoctrl); + +static inline NvBool knvlinkIsFloorSweepingNeeded_DISPATCH(OBJGPU *pGpu, struct KernelNvlink *pKernelNvlink, NvU32 numActiveLinksPerIoctrl, NvU32 numLinksPerIoctrl) { + return pKernelNvlink->__knvlinkIsFloorSweepingNeeded__(pGpu, pKernelNvlink, numActiveLinksPerIoctrl, numLinksPerIoctrl); } static inline NV_STATUS knvlinkStateInitLocked_DISPATCH(POBJGPU pGpu, struct KernelNvlink *pEngstate) { @@ -1618,26 +1651,6 @@ return pEngstate->__knvlinkStatePreInitUnlocked__(pGpu, pEngstate); } -static inline NV_STATUS knvlinkGetTunableState_DISPATCH(POBJGPU pGpu, struct KernelNvlink *pEngstate, void *pTunableState) { - return pEngstate->__knvlinkGetTunableState__(pGpu, pEngstate, pTunableState); -} - -static inline NV_STATUS knvlinkCompareTunableState_DISPATCH(POBJGPU pGpu, struct KernelNvlink *pEngstate, void *pTunables1, void *pTunables2) { - return pEngstate->__knvlinkCompareTunableState__(pGpu, pEngstate, pTunables1, pTunables2); -} - -static inline void knvlinkFreeTunableState_DISPATCH(POBJGPU pGpu, struct KernelNvlink *pEngstate, void *pTunableState) { - pEngstate->__knvlinkFreeTunableState__(pGpu, pEngstate, pTunableState); -} - -static inline NV_STATUS knvlinkAllocTunableState_DISPATCH(POBJGPU pGpu, struct KernelNvlink *pEngstate, void **ppTunableState) { - return pEngstate->__knvlinkAllocTunableState__(pGpu, pEngstate, ppTunableState); -} - -static inline NV_STATUS knvlinkSetTunableState_DISPATCH(POBJGPU pGpu, struct KernelNvlink *pEngstate, void *pTunableState) { - return pEngstate->__knvlinkSetTunableState__(pGpu, pEngstate, pTunableState); -} - void knvlinkDestruct_IMPL(struct KernelNvlink *arg0); #define __nvoc_knvlinkDestruct(arg0) knvlinkDestruct_IMPL(arg0) diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/generated/g_kernel_ofa_ctx_nvoc.c nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_kernel_ofa_ctx_nvoc.c --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/generated/g_kernel_ofa_ctx_nvoc.c 2023-10-25 20:27:10.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_kernel_ofa_ctx_nvoc.c 2024-03-05 22:18:31.000000000 +0000 @@ -176,7 +176,7 @@ return resControlLookup((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_OfaContext_RsResource.offset), pParams, ppEntry); } -static NV_STATUS __nvoc_thunk_ChannelDescendant_ofactxGetSwMethods(struct OfaContext *pChannelDescendant, METHOD **ppMethods, NvU32 *pNumMethods) { +static NV_STATUS __nvoc_thunk_ChannelDescendant_ofactxGetSwMethods(struct OfaContext *pChannelDescendant, const METHOD **ppMethods, NvU32 *pNumMethods) { return chandesGetSwMethods((struct ChannelDescendant *)(((unsigned char *)pChannelDescendant) + __nvoc_rtti_OfaContext_ChannelDescendant.offset), ppMethods, pNumMethods); } @@ -212,6 +212,10 @@ return notifyUnregisterEvent((struct Notifier *)(((unsigned char *)pNotifier) + __nvoc_rtti_OfaContext_Notifier.offset), hNotifierClient, hNotifierResource, hEventClient, hEvent); } +static NV_STATUS __nvoc_thunk_RmResource_ofactxControlSerialization_Prologue(struct OfaContext *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return rmresControlSerialization_Prologue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_OfaContext_RmResource.offset), pCallContext, pParams); +} + static NvBool __nvoc_thunk_RsResource_ofactxCanCopy(struct OfaContext *pResource) { return resCanCopy((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_OfaContext_RsResource.offset)); } @@ -224,6 +228,10 @@ return resIsDuplicate((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_OfaContext_RsResource.offset), hMemory, pDuplicate); } +static void __nvoc_thunk_RmResource_ofactxControlSerialization_Epilogue(struct OfaContext *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + rmresControlSerialization_Epilogue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_OfaContext_RmResource.offset), pCallContext, pParams); +} + static PEVENTNOTIFICATION *__nvoc_thunk_Notifier_ofactxGetNotificationListPtr(struct OfaContext *pNotifier) { return notifyGetNotificationListPtr((struct Notifier *)(((unsigned char *)pNotifier) + __nvoc_rtti_OfaContext_Notifier.offset)); } @@ -335,12 +343,16 @@ pThis->__ofactxUnregisterEvent__ = &__nvoc_thunk_Notifier_ofactxUnregisterEvent; + pThis->__ofactxControlSerialization_Prologue__ = &__nvoc_thunk_RmResource_ofactxControlSerialization_Prologue; + pThis->__ofactxCanCopy__ = &__nvoc_thunk_RsResource_ofactxCanCopy; pThis->__ofactxPreDestruct__ = &__nvoc_thunk_RsResource_ofactxPreDestruct; pThis->__ofactxIsDuplicate__ = &__nvoc_thunk_RsResource_ofactxIsDuplicate; + pThis->__ofactxControlSerialization_Epilogue__ = &__nvoc_thunk_RmResource_ofactxControlSerialization_Epilogue; + pThis->__ofactxGetNotificationListPtr__ = &__nvoc_thunk_Notifier_ofactxGetNotificationListPtr; pThis->__ofactxGetNotificationShare__ = &__nvoc_thunk_Notifier_ofactxGetNotificationShare; @@ -375,13 +387,16 @@ OfaContext *pThis; RmHalspecOwner *pRmhalspecowner; - pThis = portMemAllocNonPaged(sizeof(OfaContext)); - if (pThis == NULL) return NV_ERR_NO_MEMORY; + status = __nvoc_handleObjCreateMemAlloc(createFlags, sizeof(OfaContext), (void**)&pThis, (void**)ppThis); + if (status != NV_OK) + return status; portMemSet(pThis, 0, sizeof(OfaContext)); __nvoc_initRtti(staticCast(pThis, Dynamic), &__nvoc_class_def_OfaContext); + pThis->__nvoc_base_ChannelDescendant.__nvoc_base_GpuResource.__nvoc_base_RmResource.__nvoc_base_RsResource.__nvoc_base_Object.createFlags = createFlags; + if (pParent != NULL && !(createFlags & NVOC_OBJ_CREATE_FLAGS_PARENT_HALSPEC_ONLY)) { pParentObj = dynamicCast(pParent, Object); @@ -401,11 +416,17 @@ if (status != NV_OK) goto __nvoc_objCreate_OfaContext_cleanup; *ppThis = pThis; + return NV_OK; __nvoc_objCreate_OfaContext_cleanup: // do not call destructors here since the constructor already called them - portMemFree(pThis); + if (createFlags & NVOC_OBJ_CREATE_FLAGS_IN_PLACE_CONSTRUCT) + portMemSet(pThis, 0, sizeof(OfaContext)); + else + portMemFree(pThis); + + // coverity[leaked_storage:FALSE] return status; } diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/generated/g_kernel_ofa_ctx_nvoc.h nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_kernel_ofa_ctx_nvoc.h --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/generated/g_kernel_ofa_ctx_nvoc.h 2023-10-25 20:27:10.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_kernel_ofa_ctx_nvoc.h 2024-03-05 22:18:32.000000000 +0000 @@ -70,7 +70,7 @@ NV_STATUS (*__ofactxUnmapFrom__)(struct OfaContext *, RS_RES_UNMAP_FROM_PARAMS *); void (*__ofactxControl_Epilogue__)(struct OfaContext *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); NV_STATUS (*__ofactxControlLookup__)(struct OfaContext *, struct RS_RES_CONTROL_PARAMS_INTERNAL *, const struct NVOC_EXPORTED_METHOD_DEF **); - NV_STATUS (*__ofactxGetSwMethods__)(struct OfaContext *, METHOD **, NvU32 *); + NV_STATUS (*__ofactxGetSwMethods__)(struct OfaContext *, const METHOD **, NvU32 *); NvHandle (*__ofactxGetInternalObjectHandle__)(struct OfaContext *); NV_STATUS (*__ofactxControl__)(struct OfaContext *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); NV_STATUS (*__ofactxUnmap__)(struct OfaContext *, struct CALL_CONTEXT *, struct RsCpuMapping *); @@ -79,9 +79,11 @@ NvBool (*__ofactxIsSwMethodStalling__)(struct OfaContext *, NvU32); NV_STATUS (*__ofactxControlFilter__)(struct OfaContext *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); NV_STATUS (*__ofactxUnregisterEvent__)(struct OfaContext *, NvHandle, NvHandle, NvHandle, NvHandle); + NV_STATUS (*__ofactxControlSerialization_Prologue__)(struct OfaContext *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); NvBool (*__ofactxCanCopy__)(struct OfaContext *); void (*__ofactxPreDestruct__)(struct OfaContext *); NV_STATUS (*__ofactxIsDuplicate__)(struct OfaContext *, NvHandle, NvBool *); + void (*__ofactxControlSerialization_Epilogue__)(struct OfaContext *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); PEVENTNOTIFICATION *(*__ofactxGetNotificationListPtr__)(struct OfaContext *); struct NotifShare *(*__ofactxGetNotificationShare__)(struct OfaContext *); NV_STATUS (*__ofactxMap__)(struct OfaContext *, struct CALL_CONTEXT *, struct RS_CPU_MAP_PARAMS *, struct RsCpuMapping *); @@ -139,9 +141,11 @@ #define ofactxIsSwMethodStalling(pChannelDescendant, hHandle) ofactxIsSwMethodStalling_DISPATCH(pChannelDescendant, hHandle) #define ofactxControlFilter(pResource, pCallContext, pParams) ofactxControlFilter_DISPATCH(pResource, pCallContext, pParams) #define ofactxUnregisterEvent(pNotifier, hNotifierClient, hNotifierResource, hEventClient, hEvent) ofactxUnregisterEvent_DISPATCH(pNotifier, hNotifierClient, hNotifierResource, hEventClient, hEvent) +#define ofactxControlSerialization_Prologue(pResource, pCallContext, pParams) ofactxControlSerialization_Prologue_DISPATCH(pResource, pCallContext, pParams) #define ofactxCanCopy(pResource) ofactxCanCopy_DISPATCH(pResource) #define ofactxPreDestruct(pResource) ofactxPreDestruct_DISPATCH(pResource) #define ofactxIsDuplicate(pResource, hMemory, pDuplicate) ofactxIsDuplicate_DISPATCH(pResource, hMemory, pDuplicate) +#define ofactxControlSerialization_Epilogue(pResource, pCallContext, pParams) ofactxControlSerialization_Epilogue_DISPATCH(pResource, pCallContext, pParams) #define ofactxGetNotificationListPtr(pNotifier) ofactxGetNotificationListPtr_DISPATCH(pNotifier) #define ofactxGetNotificationShare(pNotifier) ofactxGetNotificationShare_DISPATCH(pNotifier) #define ofactxMap(pGpuResource, pCallContext, pParams, pCpuMapping) ofactxMap_DISPATCH(pGpuResource, pCallContext, pParams, pCpuMapping) @@ -229,7 +233,7 @@ return pResource->__ofactxControlLookup__(pResource, pParams, ppEntry); } -static inline NV_STATUS ofactxGetSwMethods_DISPATCH(struct OfaContext *pChannelDescendant, METHOD **ppMethods, NvU32 *pNumMethods) { +static inline NV_STATUS ofactxGetSwMethods_DISPATCH(struct OfaContext *pChannelDescendant, const METHOD **ppMethods, NvU32 *pNumMethods) { return pChannelDescendant->__ofactxGetSwMethods__(pChannelDescendant, ppMethods, pNumMethods); } @@ -265,6 +269,10 @@ return pNotifier->__ofactxUnregisterEvent__(pNotifier, hNotifierClient, hNotifierResource, hEventClient, hEvent); } +static inline NV_STATUS ofactxControlSerialization_Prologue_DISPATCH(struct OfaContext *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return pResource->__ofactxControlSerialization_Prologue__(pResource, pCallContext, pParams); +} + static inline NvBool ofactxCanCopy_DISPATCH(struct OfaContext *pResource) { return pResource->__ofactxCanCopy__(pResource); } @@ -277,6 +285,10 @@ return pResource->__ofactxIsDuplicate__(pResource, hMemory, pDuplicate); } +static inline void ofactxControlSerialization_Epilogue_DISPATCH(struct OfaContext *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + pResource->__ofactxControlSerialization_Epilogue__(pResource, pCallContext, pParams); +} + static inline PEVENTNOTIFICATION *ofactxGetNotificationListPtr_DISPATCH(struct OfaContext *pNotifier) { return pNotifier->__ofactxGetNotificationListPtr__(pNotifier); } diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/generated/g_kernel_rc_nvoc.c nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_kernel_rc_nvoc.c --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/generated/g_kernel_rc_nvoc.c 2023-10-25 20:27:10.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_kernel_rc_nvoc.c 2024-03-05 22:18:32.000000000 +0000 @@ -70,10 +70,6 @@ return krcConstructEngine(pGpu, (struct KernelRc *)(((unsigned char *)pKernelRc) - __nvoc_rtti_KernelRc_OBJENGSTATE.offset), engDescriptor); } -static NV_STATUS __nvoc_thunk_OBJENGSTATE_krcReconcileTunableState(POBJGPU pGpu, struct KernelRc *pEngstate, void *pTunableState) { - return engstateReconcileTunableState(pGpu, (struct OBJENGSTATE *)(((unsigned char *)pEngstate) + __nvoc_rtti_KernelRc_OBJENGSTATE.offset), pTunableState); -} - static NV_STATUS __nvoc_thunk_OBJENGSTATE_krcStateLoad(POBJGPU pGpu, struct KernelRc *pEngstate, NvU32 arg0) { return engstateStateLoad(pGpu, (struct OBJENGSTATE *)(((unsigned char *)pEngstate) + __nvoc_rtti_KernelRc_OBJENGSTATE.offset), arg0); } @@ -118,30 +114,10 @@ return engstateStatePreInitUnlocked(pGpu, (struct OBJENGSTATE *)(((unsigned char *)pEngstate) + __nvoc_rtti_KernelRc_OBJENGSTATE.offset)); } -static NV_STATUS __nvoc_thunk_OBJENGSTATE_krcGetTunableState(POBJGPU pGpu, struct KernelRc *pEngstate, void *pTunableState) { - return engstateGetTunableState(pGpu, (struct OBJENGSTATE *)(((unsigned char *)pEngstate) + __nvoc_rtti_KernelRc_OBJENGSTATE.offset), pTunableState); -} - -static NV_STATUS __nvoc_thunk_OBJENGSTATE_krcCompareTunableState(POBJGPU pGpu, struct KernelRc *pEngstate, void *pTunables1, void *pTunables2) { - return engstateCompareTunableState(pGpu, (struct OBJENGSTATE *)(((unsigned char *)pEngstate) + __nvoc_rtti_KernelRc_OBJENGSTATE.offset), pTunables1, pTunables2); -} - -static void __nvoc_thunk_OBJENGSTATE_krcFreeTunableState(POBJGPU pGpu, struct KernelRc *pEngstate, void *pTunableState) { - engstateFreeTunableState(pGpu, (struct OBJENGSTATE *)(((unsigned char *)pEngstate) + __nvoc_rtti_KernelRc_OBJENGSTATE.offset), pTunableState); -} - static NV_STATUS __nvoc_thunk_OBJENGSTATE_krcStatePostLoad(POBJGPU pGpu, struct KernelRc *pEngstate, NvU32 arg0) { return engstateStatePostLoad(pGpu, (struct OBJENGSTATE *)(((unsigned char *)pEngstate) + __nvoc_rtti_KernelRc_OBJENGSTATE.offset), arg0); } -static NV_STATUS __nvoc_thunk_OBJENGSTATE_krcAllocTunableState(POBJGPU pGpu, struct KernelRc *pEngstate, void **ppTunableState) { - return engstateAllocTunableState(pGpu, (struct OBJENGSTATE *)(((unsigned char *)pEngstate) + __nvoc_rtti_KernelRc_OBJENGSTATE.offset), ppTunableState); -} - -static NV_STATUS __nvoc_thunk_OBJENGSTATE_krcSetTunableState(POBJGPU pGpu, struct KernelRc *pEngstate, void *pTunableState) { - return engstateSetTunableState(pGpu, (struct OBJENGSTATE *)(((unsigned char *)pEngstate) + __nvoc_rtti_KernelRc_OBJENGSTATE.offset), pTunableState); -} - static NvBool __nvoc_thunk_OBJENGSTATE_krcIsPresent(POBJGPU pGpu, struct KernelRc *pEngstate) { return engstateIsPresent(pGpu, (struct OBJENGSTATE *)(((unsigned char *)pEngstate) + __nvoc_rtti_KernelRc_OBJENGSTATE.offset)); } @@ -201,8 +177,6 @@ pThis->__nvoc_base_OBJENGSTATE.__engstateConstructEngine__ = &__nvoc_thunk_KernelRc_engstateConstructEngine; - pThis->__krcReconcileTunableState__ = &__nvoc_thunk_OBJENGSTATE_krcReconcileTunableState; - pThis->__krcStateLoad__ = &__nvoc_thunk_OBJENGSTATE_krcStateLoad; pThis->__krcStateUnload__ = &__nvoc_thunk_OBJENGSTATE_krcStateUnload; @@ -225,18 +199,8 @@ pThis->__krcStatePreInitUnlocked__ = &__nvoc_thunk_OBJENGSTATE_krcStatePreInitUnlocked; - pThis->__krcGetTunableState__ = &__nvoc_thunk_OBJENGSTATE_krcGetTunableState; - - pThis->__krcCompareTunableState__ = &__nvoc_thunk_OBJENGSTATE_krcCompareTunableState; - - pThis->__krcFreeTunableState__ = &__nvoc_thunk_OBJENGSTATE_krcFreeTunableState; - pThis->__krcStatePostLoad__ = &__nvoc_thunk_OBJENGSTATE_krcStatePostLoad; - pThis->__krcAllocTunableState__ = &__nvoc_thunk_OBJENGSTATE_krcAllocTunableState; - - pThis->__krcSetTunableState__ = &__nvoc_thunk_OBJENGSTATE_krcSetTunableState; - pThis->__krcIsPresent__ = &__nvoc_thunk_OBJENGSTATE_krcIsPresent; } @@ -259,13 +223,16 @@ KernelRc *pThis; RmHalspecOwner *pRmhalspecowner; - pThis = portMemAllocNonPaged(sizeof(KernelRc)); - if (pThis == NULL) return NV_ERR_NO_MEMORY; + status = __nvoc_handleObjCreateMemAlloc(createFlags, sizeof(KernelRc), (void**)&pThis, (void**)ppThis); + if (status != NV_OK) + return status; portMemSet(pThis, 0, sizeof(KernelRc)); __nvoc_initRtti(staticCast(pThis, Dynamic), &__nvoc_class_def_KernelRc); + pThis->__nvoc_base_OBJENGSTATE.__nvoc_base_Object.createFlags = createFlags; + if (pParent != NULL && !(createFlags & NVOC_OBJ_CREATE_FLAGS_PARENT_HALSPEC_ONLY)) { pParentObj = dynamicCast(pParent, Object); @@ -285,11 +252,17 @@ if (status != NV_OK) goto __nvoc_objCreate_KernelRc_cleanup; *ppThis = pThis; + return NV_OK; __nvoc_objCreate_KernelRc_cleanup: // do not call destructors here since the constructor already called them - portMemFree(pThis); + if (createFlags & NVOC_OBJ_CREATE_FLAGS_IN_PLACE_CONSTRUCT) + portMemSet(pThis, 0, sizeof(KernelRc)); + else + portMemFree(pThis); + + // coverity[leaked_storage:FALSE] return status; } diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/generated/g_kernel_rc_nvoc.h nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_kernel_rc_nvoc.h --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/generated/g_kernel_rc_nvoc.h 2023-10-25 20:27:11.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_kernel_rc_nvoc.h 2024-03-05 22:18:32.000000000 +0000 @@ -65,7 +65,6 @@ struct OBJENGSTATE *__nvoc_pbase_OBJENGSTATE; struct KernelRc *__nvoc_pbase_KernelRc; NV_STATUS (*__krcConstructEngine__)(struct OBJGPU *, struct KernelRc *, ENGDESCRIPTOR); - NV_STATUS (*__krcReconcileTunableState__)(POBJGPU, struct KernelRc *, void *); NV_STATUS (*__krcStateLoad__)(POBJGPU, struct KernelRc *, NvU32); NV_STATUS (*__krcStateUnload__)(POBJGPU, struct KernelRc *, NvU32); NV_STATUS (*__krcStateInitLocked__)(POBJGPU, struct KernelRc *); @@ -77,12 +76,7 @@ void (*__krcInitMissing__)(POBJGPU, struct KernelRc *); NV_STATUS (*__krcStatePreInitLocked__)(POBJGPU, struct KernelRc *); NV_STATUS (*__krcStatePreInitUnlocked__)(POBJGPU, struct KernelRc *); - NV_STATUS (*__krcGetTunableState__)(POBJGPU, struct KernelRc *, void *); - NV_STATUS (*__krcCompareTunableState__)(POBJGPU, struct KernelRc *, void *, void *); - void (*__krcFreeTunableState__)(POBJGPU, struct KernelRc *, void *); NV_STATUS (*__krcStatePostLoad__)(POBJGPU, struct KernelRc *, NvU32); - NV_STATUS (*__krcAllocTunableState__)(POBJGPU, struct KernelRc *, void **); - NV_STATUS (*__krcSetTunableState__)(POBJGPU, struct KernelRc *, void *); NvBool (*__krcIsPresent__)(POBJGPU, struct KernelRc *); NvBool bRobustChannelsEnabled; NvBool bBreakOnRc; @@ -125,7 +119,6 @@ __nvoc_objCreate_KernelRc((ppNewObj), staticCast((pParent), Dynamic), (createFlags)) #define krcConstructEngine(pGpu, pKernelRc, engDescriptor) krcConstructEngine_DISPATCH(pGpu, pKernelRc, engDescriptor) -#define krcReconcileTunableState(pGpu, pEngstate, pTunableState) krcReconcileTunableState_DISPATCH(pGpu, pEngstate, pTunableState) #define krcStateLoad(pGpu, pEngstate, arg0) krcStateLoad_DISPATCH(pGpu, pEngstate, arg0) #define krcStateUnload(pGpu, pEngstate, arg0) krcStateUnload_DISPATCH(pGpu, pEngstate, arg0) #define krcStateInitLocked(pGpu, pEngstate) krcStateInitLocked_DISPATCH(pGpu, pEngstate) @@ -137,12 +130,7 @@ #define krcInitMissing(pGpu, pEngstate) krcInitMissing_DISPATCH(pGpu, pEngstate) #define krcStatePreInitLocked(pGpu, pEngstate) krcStatePreInitLocked_DISPATCH(pGpu, pEngstate) #define krcStatePreInitUnlocked(pGpu, pEngstate) krcStatePreInitUnlocked_DISPATCH(pGpu, pEngstate) -#define krcGetTunableState(pGpu, pEngstate, pTunableState) krcGetTunableState_DISPATCH(pGpu, pEngstate, pTunableState) -#define krcCompareTunableState(pGpu, pEngstate, pTunables1, pTunables2) krcCompareTunableState_DISPATCH(pGpu, pEngstate, pTunables1, pTunables2) -#define krcFreeTunableState(pGpu, pEngstate, pTunableState) krcFreeTunableState_DISPATCH(pGpu, pEngstate, pTunableState) #define krcStatePostLoad(pGpu, pEngstate, arg0) krcStatePostLoad_DISPATCH(pGpu, pEngstate, arg0) -#define krcAllocTunableState(pGpu, pEngstate, ppTunableState) krcAllocTunableState_DISPATCH(pGpu, pEngstate, ppTunableState) -#define krcSetTunableState(pGpu, pEngstate, pTunableState) krcSetTunableState_DISPATCH(pGpu, pEngstate, pTunableState) #define krcIsPresent(pGpu, pEngstate) krcIsPresent_DISPATCH(pGpu, pEngstate) NV_STATUS krcErrorWriteNotifier_CPU(struct OBJGPU *pGpu, struct KernelRc *pKernelRc, struct KernelChannel *pKernelChannel, NvU32 exceptType, RM_ENGINE_TYPE localRmEngineType, NV_STATUS notifierStatus, NvU32 *pFlushFlags); @@ -329,10 +317,6 @@ return pKernelRc->__krcConstructEngine__(pGpu, pKernelRc, engDescriptor); } -static inline NV_STATUS krcReconcileTunableState_DISPATCH(POBJGPU pGpu, struct KernelRc *pEngstate, void *pTunableState) { - return pEngstate->__krcReconcileTunableState__(pGpu, pEngstate, pTunableState); -} - static inline NV_STATUS krcStateLoad_DISPATCH(POBJGPU pGpu, struct KernelRc *pEngstate, NvU32 arg0) { return pEngstate->__krcStateLoad__(pGpu, pEngstate, arg0); } @@ -377,30 +361,10 @@ return pEngstate->__krcStatePreInitUnlocked__(pGpu, pEngstate); } -static inline NV_STATUS krcGetTunableState_DISPATCH(POBJGPU pGpu, struct KernelRc *pEngstate, void *pTunableState) { - return pEngstate->__krcGetTunableState__(pGpu, pEngstate, pTunableState); -} - -static inline NV_STATUS krcCompareTunableState_DISPATCH(POBJGPU pGpu, struct KernelRc *pEngstate, void *pTunables1, void *pTunables2) { - return pEngstate->__krcCompareTunableState__(pGpu, pEngstate, pTunables1, pTunables2); -} - -static inline void krcFreeTunableState_DISPATCH(POBJGPU pGpu, struct KernelRc *pEngstate, void *pTunableState) { - pEngstate->__krcFreeTunableState__(pGpu, pEngstate, pTunableState); -} - static inline NV_STATUS krcStatePostLoad_DISPATCH(POBJGPU pGpu, struct KernelRc *pEngstate, NvU32 arg0) { return pEngstate->__krcStatePostLoad__(pGpu, pEngstate, arg0); } -static inline NV_STATUS krcAllocTunableState_DISPATCH(POBJGPU pGpu, struct KernelRc *pEngstate, void **ppTunableState) { - return pEngstate->__krcAllocTunableState__(pGpu, pEngstate, ppTunableState); -} - -static inline NV_STATUS krcSetTunableState_DISPATCH(POBJGPU pGpu, struct KernelRc *pEngstate, void *pTunableState) { - return pEngstate->__krcSetTunableState__(pGpu, pEngstate, pTunableState); -} - static inline NvBool krcIsPresent_DISPATCH(POBJGPU pGpu, struct KernelRc *pEngstate) { return pEngstate->__krcIsPresent__(pGpu, pEngstate); } @@ -563,6 +527,17 @@ #define krcWatchdogCallbackVblankRecovery(pGpu, pKernelRc) krcWatchdogCallbackVblankRecovery_IMPL(pGpu, pKernelRc) #endif //__nvoc_kernel_rc_h_disabled +NV_STATUS krcWatchdogGetClientHandle_IMPL(struct KernelRc *arg0, NvHandle *arg1); + +#ifdef __nvoc_kernel_rc_h_disabled +static inline NV_STATUS krcWatchdogGetClientHandle(struct KernelRc *arg0, NvHandle *arg1) { + NV_ASSERT_FAILED_PRECOMP("KernelRc was disabled!"); + return NV_ERR_NOT_SUPPORTED; +} +#else //__nvoc_kernel_rc_h_disabled +#define krcWatchdogGetClientHandle(arg0, arg1) krcWatchdogGetClientHandle_IMPL(arg0, arg1) +#endif //__nvoc_kernel_rc_h_disabled + #undef PRIVATE_FIELD diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/generated/g_kernel_sched_mgr_nvoc.c nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_kernel_sched_mgr_nvoc.c --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/generated/g_kernel_sched_mgr_nvoc.c 2023-10-25 20:27:11.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_kernel_sched_mgr_nvoc.c 2024-03-05 22:18:32.000000000 +0000 @@ -110,13 +110,16 @@ Object *pParentObj; KernelSchedMgr *pThis; - pThis = portMemAllocNonPaged(sizeof(KernelSchedMgr)); - if (pThis == NULL) return NV_ERR_NO_MEMORY; + status = __nvoc_handleObjCreateMemAlloc(createFlags, sizeof(KernelSchedMgr), (void**)&pThis, (void**)ppThis); + if (status != NV_OK) + return status; portMemSet(pThis, 0, sizeof(KernelSchedMgr)); __nvoc_initRtti(staticCast(pThis, Dynamic), &__nvoc_class_def_KernelSchedMgr); + pThis->__nvoc_base_Object.createFlags = createFlags; + if (pParent != NULL && !(createFlags & NVOC_OBJ_CREATE_FLAGS_PARENT_HALSPEC_ONLY)) { pParentObj = dynamicCast(pParent, Object); @@ -132,11 +135,17 @@ if (status != NV_OK) goto __nvoc_objCreate_KernelSchedMgr_cleanup; *ppThis = pThis; + return NV_OK; __nvoc_objCreate_KernelSchedMgr_cleanup: // do not call destructors here since the constructor already called them - portMemFree(pThis); + if (createFlags & NVOC_OBJ_CREATE_FLAGS_IN_PLACE_CONSTRUCT) + portMemSet(pThis, 0, sizeof(KernelSchedMgr)); + else + portMemFree(pThis); + + // coverity[leaked_storage:FALSE] return status; } diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/generated/g_kernel_sched_mgr_nvoc.h nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_kernel_sched_mgr_nvoc.h --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/generated/g_kernel_sched_mgr_nvoc.h 2023-10-25 20:27:11.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_kernel_sched_mgr_nvoc.h 2024-03-05 22:18:32.000000000 +0000 @@ -7,7 +7,7 @@ #endif /* - * SPDX-FileCopyrightText: Copyright (c) 2021 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2021-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -104,6 +104,10 @@ return pKernelSchedMgr->configSchedPolicy; } +static inline NvBool kschedmgrIsPvmrlEnabled(struct KernelSchedMgr *pKernelSchedMgr) { + return ((NvBool)(0 != 0)); +} + void kschedmgrConstructPolicy_IMPL(struct KernelSchedMgr *pKernelSchedMgr, struct OBJGPU *pGpu); #ifdef __nvoc_kernel_sched_mgr_h_disabled @@ -114,6 +118,16 @@ #define kschedmgrConstructPolicy(pKernelSchedMgr, pGpu) kschedmgrConstructPolicy_IMPL(pKernelSchedMgr, pGpu) #endif //__nvoc_kernel_sched_mgr_h_disabled +void kschedmgrSetConfigPolicyFromUser_IMPL(struct KernelSchedMgr *pKernelSchedMgr, struct OBJGPU *pGpu, NvU32 schedSwPolicy); + +#ifdef __nvoc_kernel_sched_mgr_h_disabled +static inline void kschedmgrSetConfigPolicyFromUser(struct KernelSchedMgr *pKernelSchedMgr, struct OBJGPU *pGpu, NvU32 schedSwPolicy) { + NV_ASSERT_FAILED_PRECOMP("KernelSchedMgr was disabled!"); +} +#else //__nvoc_kernel_sched_mgr_h_disabled +#define kschedmgrSetConfigPolicyFromUser(pKernelSchedMgr, pGpu, schedSwPolicy) kschedmgrSetConfigPolicyFromUser_IMPL(pKernelSchedMgr, pGpu, schedSwPolicy) +#endif //__nvoc_kernel_sched_mgr_h_disabled + #undef PRIVATE_FIELD diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/generated/g_kernel_sec2_nvoc.c nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_kernel_sec2_nvoc.c --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/generated/g_kernel_sec2_nvoc.c 2023-10-25 20:27:11.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_kernel_sec2_nvoc.c 2024-03-05 22:18:32.000000000 +0000 @@ -17,6 +17,12 @@ extern const struct NVOC_CLASS_DEF __nvoc_class_def_OBJENGSTATE; +extern const struct NVOC_CLASS_DEF __nvoc_class_def_IntrService; + +extern const struct NVOC_CLASS_DEF __nvoc_class_def_CrashCatEngine; + +extern const struct NVOC_CLASS_DEF __nvoc_class_def_KernelCrashCatEngine; + extern const struct NVOC_CLASS_DEF __nvoc_class_def_KernelFalcon; void __nvoc_init_KernelSec2(KernelSec2*, RmHalspecOwner* ); @@ -44,6 +50,24 @@ /*offset=*/ NV_OFFSETOF(KernelSec2, __nvoc_base_OBJENGSTATE), }; +static const struct NVOC_RTTI __nvoc_rtti_KernelSec2_IntrService = { + /*pClassDef=*/ &__nvoc_class_def_IntrService, + /*dtor=*/ &__nvoc_destructFromBase, + /*offset=*/ NV_OFFSETOF(KernelSec2, __nvoc_base_IntrService), +}; + +static const struct NVOC_RTTI __nvoc_rtti_KernelSec2_CrashCatEngine = { + /*pClassDef=*/ &__nvoc_class_def_CrashCatEngine, + /*dtor=*/ &__nvoc_destructFromBase, + /*offset=*/ NV_OFFSETOF(KernelSec2, __nvoc_base_KernelFalcon.__nvoc_base_KernelCrashCatEngine.__nvoc_base_CrashCatEngine), +}; + +static const struct NVOC_RTTI __nvoc_rtti_KernelSec2_KernelCrashCatEngine = { + /*pClassDef=*/ &__nvoc_class_def_KernelCrashCatEngine, + /*dtor=*/ &__nvoc_destructFromBase, + /*offset=*/ NV_OFFSETOF(KernelSec2, __nvoc_base_KernelFalcon.__nvoc_base_KernelCrashCatEngine), +}; + static const struct NVOC_RTTI __nvoc_rtti_KernelSec2_KernelFalcon = { /*pClassDef=*/ &__nvoc_class_def_KernelFalcon, /*dtor=*/ &__nvoc_destructFromBase, @@ -51,10 +75,13 @@ }; static const struct NVOC_CASTINFO __nvoc_castinfo_KernelSec2 = { - /*numRelatives=*/ 4, + /*numRelatives=*/ 7, /*relatives=*/ { &__nvoc_rtti_KernelSec2_KernelSec2, &__nvoc_rtti_KernelSec2_KernelFalcon, + &__nvoc_rtti_KernelSec2_KernelCrashCatEngine, + &__nvoc_rtti_KernelSec2_CrashCatEngine, + &__nvoc_rtti_KernelSec2_IntrService, &__nvoc_rtti_KernelSec2_OBJENGSTATE, &__nvoc_rtti_KernelSec2_Object, }, @@ -79,26 +106,94 @@ return ksec2ConstructEngine(pGpu, (struct KernelSec2 *)(((unsigned char *)pKernelSec2) - __nvoc_rtti_KernelSec2_OBJENGSTATE.offset), arg0); } +static void __nvoc_thunk_KernelSec2_intrservRegisterIntrService(struct OBJGPU *pGpu, struct IntrService *pKernelSec2, IntrServiceRecord pRecords[167]) { + ksec2RegisterIntrService(pGpu, (struct KernelSec2 *)(((unsigned char *)pKernelSec2) - __nvoc_rtti_KernelSec2_IntrService.offset), pRecords); +} + +static NV_STATUS __nvoc_thunk_KernelSec2_intrservServiceNotificationInterrupt(struct OBJGPU *arg0, struct IntrService *arg1, IntrServiceServiceNotificationInterruptArguments *arg2) { + return ksec2ServiceNotificationInterrupt(arg0, (struct KernelSec2 *)(((unsigned char *)arg1) - __nvoc_rtti_KernelSec2_IntrService.offset), arg2); +} + static NV_STATUS __nvoc_thunk_KernelSec2_kflcnResetHw(struct OBJGPU *pGpu, struct KernelFalcon *pKernelSec2) { return ksec2ResetHw(pGpu, (struct KernelSec2 *)(((unsigned char *)pKernelSec2) - __nvoc_rtti_KernelSec2_KernelFalcon.offset)); } -static NvBool __nvoc_thunk_KernelSec2_kflcnIsEngineInReset(struct OBJGPU *pGpu, struct KernelFalcon *pKernelSec2) { - return ksec2IsEngineInReset(pGpu, (struct KernelSec2 *)(((unsigned char *)pKernelSec2) - __nvoc_rtti_KernelSec2_KernelFalcon.offset)); +static NV_STATUS __nvoc_thunk_KernelSec2_engstateStateLoad(struct OBJGPU *pGpu, struct OBJENGSTATE *pKernelSec2, NvU32 arg0) { + return ksec2StateLoad(pGpu, (struct KernelSec2 *)(((unsigned char *)pKernelSec2) - __nvoc_rtti_KernelSec2_OBJENGSTATE.offset), arg0); +} + +static NvBool __nvoc_thunk_KernelCrashCatEngine_ksec2Configured(struct KernelSec2 *arg0) { + return kcrashcatEngineConfigured((struct KernelCrashCatEngine *)(((unsigned char *)arg0) + __nvoc_rtti_KernelSec2_KernelCrashCatEngine.offset)); +} + +static NvU32 __nvoc_thunk_KernelCrashCatEngine_ksec2PriRead(struct KernelSec2 *arg0, NvU32 offset) { + return kcrashcatEnginePriRead((struct KernelCrashCatEngine *)(((unsigned char *)arg0) + __nvoc_rtti_KernelSec2_KernelCrashCatEngine.offset), offset); +} + +static void __nvoc_thunk_KernelFalcon_ksec2RegWrite(struct OBJGPU *pGpu, struct KernelSec2 *pKernelFlcn, NvU32 offset, NvU32 data) { + kflcnRegWrite(pGpu, (struct KernelFalcon *)(((unsigned char *)pKernelFlcn) + __nvoc_rtti_KernelSec2_KernelFalcon.offset), offset, data); +} + +static NvU32 __nvoc_thunk_KernelFalcon_ksec2MaskDmemAddr(struct OBJGPU *pGpu, struct KernelSec2 *pKernelFlcn, NvU32 addr) { + return kflcnMaskDmemAddr(pGpu, (struct KernelFalcon *)(((unsigned char *)pKernelFlcn) + __nvoc_rtti_KernelSec2_KernelFalcon.offset), addr); +} + +static void __nvoc_thunk_OBJENGSTATE_ksec2StateDestroy(POBJGPU pGpu, struct KernelSec2 *pEngstate) { + engstateStateDestroy(pGpu, (struct OBJENGSTATE *)(((unsigned char *)pEngstate) + __nvoc_rtti_KernelSec2_OBJENGSTATE.offset)); +} + +static void __nvoc_thunk_KernelCrashCatEngine_ksec2Vprintf(struct KernelSec2 *arg0, NvBool bReportStart, const char *fmt, va_list args) { + kcrashcatEngineVprintf((struct KernelCrashCatEngine *)(((unsigned char *)arg0) + __nvoc_rtti_KernelSec2_KernelCrashCatEngine.offset), bReportStart, fmt, args); } -static NV_STATUS __nvoc_thunk_OBJENGSTATE_ksec2ReconcileTunableState(POBJGPU pGpu, struct KernelSec2 *pEngstate, void *pTunableState) { - return engstateReconcileTunableState(pGpu, (struct OBJENGSTATE *)(((unsigned char *)pEngstate) + __nvoc_rtti_KernelSec2_OBJENGSTATE.offset), pTunableState); +static NvBool __nvoc_thunk_IntrService_ksec2ClearInterrupt(struct OBJGPU *pGpu, struct KernelSec2 *pIntrService, IntrServiceClearInterruptArguments *pParams) { + return intrservClearInterrupt(pGpu, (struct IntrService *)(((unsigned char *)pIntrService) + __nvoc_rtti_KernelSec2_IntrService.offset), pParams); } -static NV_STATUS __nvoc_thunk_OBJENGSTATE_ksec2StateLoad(POBJGPU pGpu, struct KernelSec2 *pEngstate, NvU32 arg0) { - return engstateStateLoad(pGpu, (struct OBJENGSTATE *)(((unsigned char *)pEngstate) + __nvoc_rtti_KernelSec2_OBJENGSTATE.offset), arg0); +static void __nvoc_thunk_KernelCrashCatEngine_ksec2PriWrite(struct KernelSec2 *arg0, NvU32 offset, NvU32 data) { + kcrashcatEnginePriWrite((struct KernelCrashCatEngine *)(((unsigned char *)arg0) + __nvoc_rtti_KernelSec2_KernelCrashCatEngine.offset), offset, data); +} + +static void *__nvoc_thunk_KernelCrashCatEngine_ksec2MapBufferDescriptor(struct KernelSec2 *arg0, CrashCatBufferDescriptor *pBufDesc) { + return kcrashcatEngineMapBufferDescriptor((struct KernelCrashCatEngine *)(((unsigned char *)arg0) + __nvoc_rtti_KernelSec2_KernelCrashCatEngine.offset), pBufDesc); +} + +static void __nvoc_thunk_KernelCrashCatEngine_ksec2SyncBufferDescriptor(struct KernelSec2 *arg0, CrashCatBufferDescriptor *pBufDesc, NvU32 offset, NvU32 size) { + kcrashcatEngineSyncBufferDescriptor((struct KernelCrashCatEngine *)(((unsigned char *)arg0) + __nvoc_rtti_KernelSec2_KernelCrashCatEngine.offset), pBufDesc, offset, size); +} + +static NvU32 __nvoc_thunk_KernelFalcon_ksec2RegRead(struct OBJGPU *pGpu, struct KernelSec2 *pKernelFlcn, NvU32 offset) { + return kflcnRegRead(pGpu, (struct KernelFalcon *)(((unsigned char *)pKernelFlcn) + __nvoc_rtti_KernelSec2_KernelFalcon.offset), offset); +} + +static NvBool __nvoc_thunk_OBJENGSTATE_ksec2IsPresent(POBJGPU pGpu, struct KernelSec2 *pEngstate) { + return engstateIsPresent(pGpu, (struct OBJENGSTATE *)(((unsigned char *)pEngstate) + __nvoc_rtti_KernelSec2_OBJENGSTATE.offset)); +} + +static NvU32 __nvoc_thunk_IntrService_ksec2ServiceInterrupt(struct OBJGPU *pGpu, struct KernelSec2 *pIntrService, IntrServiceServiceInterruptArguments *pParams) { + return intrservServiceInterrupt(pGpu, (struct IntrService *)(((unsigned char *)pIntrService) + __nvoc_rtti_KernelSec2_IntrService.offset), pParams); +} + +static void __nvoc_thunk_KernelCrashCatEngine_ksec2ReadEmem(struct KernelSec2 *arg0, NvU64 offset, NvU64 size, void *pBuf) { + kcrashcatEngineReadEmem((struct KernelCrashCatEngine *)(((unsigned char *)arg0) + __nvoc_rtti_KernelSec2_KernelCrashCatEngine.offset), offset, size, pBuf); +} + +static const NvU32 *__nvoc_thunk_KernelCrashCatEngine_ksec2GetScratchOffsets(struct KernelSec2 *arg0, NV_CRASHCAT_SCRATCH_GROUP_ID scratchGroupId) { + return kcrashcatEngineGetScratchOffsets((struct KernelCrashCatEngine *)(((unsigned char *)arg0) + __nvoc_rtti_KernelSec2_KernelCrashCatEngine.offset), scratchGroupId); +} + +static void __nvoc_thunk_KernelCrashCatEngine_ksec2Unload(struct KernelSec2 *arg0) { + kcrashcatEngineUnload((struct KernelCrashCatEngine *)(((unsigned char *)arg0) + __nvoc_rtti_KernelSec2_KernelCrashCatEngine.offset)); } static NV_STATUS __nvoc_thunk_OBJENGSTATE_ksec2StateUnload(POBJGPU pGpu, struct KernelSec2 *pEngstate, NvU32 arg0) { return engstateStateUnload(pGpu, (struct OBJENGSTATE *)(((unsigned char *)pEngstate) + __nvoc_rtti_KernelSec2_OBJENGSTATE.offset), arg0); } +static NvU32 __nvoc_thunk_KernelCrashCatEngine_ksec2GetWFL0Offset(struct KernelSec2 *arg0) { + return kcrashcatEngineGetWFL0Offset((struct KernelCrashCatEngine *)(((unsigned char *)arg0) + __nvoc_rtti_KernelSec2_KernelCrashCatEngine.offset)); +} + static NV_STATUS __nvoc_thunk_OBJENGSTATE_ksec2StateInitLocked(POBJGPU pGpu, struct KernelSec2 *pEngstate) { return engstateStateInitLocked(pGpu, (struct OBJENGSTATE *)(((unsigned char *)pEngstate) + __nvoc_rtti_KernelSec2_OBJENGSTATE.offset)); } @@ -111,10 +206,6 @@ return engstateStatePostUnload(pGpu, (struct OBJENGSTATE *)(((unsigned char *)pEngstate) + __nvoc_rtti_KernelSec2_OBJENGSTATE.offset), arg0); } -static void __nvoc_thunk_OBJENGSTATE_ksec2StateDestroy(POBJGPU pGpu, struct KernelSec2 *pEngstate) { - engstateStateDestroy(pGpu, (struct OBJENGSTATE *)(((unsigned char *)pEngstate) + __nvoc_rtti_KernelSec2_OBJENGSTATE.offset)); -} - static NV_STATUS __nvoc_thunk_OBJENGSTATE_ksec2StatePreUnload(POBJGPU pGpu, struct KernelSec2 *pEngstate, NvU32 arg0) { return engstateStatePreUnload(pGpu, (struct OBJENGSTATE *)(((unsigned char *)pEngstate) + __nvoc_rtti_KernelSec2_OBJENGSTATE.offset), arg0); } @@ -135,32 +226,16 @@ return engstateStatePreInitUnlocked(pGpu, (struct OBJENGSTATE *)(((unsigned char *)pEngstate) + __nvoc_rtti_KernelSec2_OBJENGSTATE.offset)); } -static NV_STATUS __nvoc_thunk_OBJENGSTATE_ksec2GetTunableState(POBJGPU pGpu, struct KernelSec2 *pEngstate, void *pTunableState) { - return engstateGetTunableState(pGpu, (struct OBJENGSTATE *)(((unsigned char *)pEngstate) + __nvoc_rtti_KernelSec2_OBJENGSTATE.offset), pTunableState); -} - -static NV_STATUS __nvoc_thunk_OBJENGSTATE_ksec2CompareTunableState(POBJGPU pGpu, struct KernelSec2 *pEngstate, void *pTunables1, void *pTunables2) { - return engstateCompareTunableState(pGpu, (struct OBJENGSTATE *)(((unsigned char *)pEngstate) + __nvoc_rtti_KernelSec2_OBJENGSTATE.offset), pTunables1, pTunables2); -} - -static void __nvoc_thunk_OBJENGSTATE_ksec2FreeTunableState(POBJGPU pGpu, struct KernelSec2 *pEngstate, void *pTunableState) { - engstateFreeTunableState(pGpu, (struct OBJENGSTATE *)(((unsigned char *)pEngstate) + __nvoc_rtti_KernelSec2_OBJENGSTATE.offset), pTunableState); -} - static NV_STATUS __nvoc_thunk_OBJENGSTATE_ksec2StatePostLoad(POBJGPU pGpu, struct KernelSec2 *pEngstate, NvU32 arg0) { return engstateStatePostLoad(pGpu, (struct OBJENGSTATE *)(((unsigned char *)pEngstate) + __nvoc_rtti_KernelSec2_OBJENGSTATE.offset), arg0); } -static NV_STATUS __nvoc_thunk_OBJENGSTATE_ksec2AllocTunableState(POBJGPU pGpu, struct KernelSec2 *pEngstate, void **ppTunableState) { - return engstateAllocTunableState(pGpu, (struct OBJENGSTATE *)(((unsigned char *)pEngstate) + __nvoc_rtti_KernelSec2_OBJENGSTATE.offset), ppTunableState); +static void __nvoc_thunk_KernelCrashCatEngine_ksec2UnmapBufferDescriptor(struct KernelSec2 *arg0, CrashCatBufferDescriptor *pBufDesc) { + kcrashcatEngineUnmapBufferDescriptor((struct KernelCrashCatEngine *)(((unsigned char *)arg0) + __nvoc_rtti_KernelSec2_KernelCrashCatEngine.offset), pBufDesc); } -static NV_STATUS __nvoc_thunk_OBJENGSTATE_ksec2SetTunableState(POBJGPU pGpu, struct KernelSec2 *pEngstate, void *pTunableState) { - return engstateSetTunableState(pGpu, (struct OBJENGSTATE *)(((unsigned char *)pEngstate) + __nvoc_rtti_KernelSec2_OBJENGSTATE.offset), pTunableState); -} - -static NvBool __nvoc_thunk_OBJENGSTATE_ksec2IsPresent(POBJGPU pGpu, struct KernelSec2 *pEngstate) { - return engstateIsPresent(pGpu, (struct OBJENGSTATE *)(((unsigned char *)pEngstate) + __nvoc_rtti_KernelSec2_OBJENGSTATE.offset)); +static void __nvoc_thunk_KernelCrashCatEngine_ksec2ReadDmem(struct KernelSec2 *arg0, NvU32 offset, NvU32 size, void *pBuf) { + kcrashcatEngineReadDmem((struct KernelCrashCatEngine *)(((unsigned char *)arg0) + __nvoc_rtti_KernelSec2_KernelCrashCatEngine.offset), offset, size, pBuf); } const struct NVOC_EXPORT_INFO __nvoc_export_info_KernelSec2 = @@ -170,10 +245,12 @@ }; void __nvoc_dtor_OBJENGSTATE(OBJENGSTATE*); +void __nvoc_dtor_IntrService(IntrService*); void __nvoc_dtor_KernelFalcon(KernelFalcon*); void __nvoc_dtor_KernelSec2(KernelSec2 *pThis) { __nvoc_ksec2Destruct(pThis); __nvoc_dtor_OBJENGSTATE(&pThis->__nvoc_base_OBJENGSTATE); + __nvoc_dtor_IntrService(&pThis->__nvoc_base_IntrService); __nvoc_dtor_KernelFalcon(&pThis->__nvoc_base_KernelFalcon); PORT_UNREFERENCED_VARIABLE(pThis); } @@ -192,17 +269,22 @@ } NV_STATUS __nvoc_ctor_OBJENGSTATE(OBJENGSTATE* ); +NV_STATUS __nvoc_ctor_IntrService(IntrService* ); NV_STATUS __nvoc_ctor_KernelFalcon(KernelFalcon* , RmHalspecOwner* ); NV_STATUS __nvoc_ctor_KernelSec2(KernelSec2 *pThis, RmHalspecOwner *pRmhalspecowner) { NV_STATUS status = NV_OK; status = __nvoc_ctor_OBJENGSTATE(&pThis->__nvoc_base_OBJENGSTATE); if (status != NV_OK) goto __nvoc_ctor_KernelSec2_fail_OBJENGSTATE; + status = __nvoc_ctor_IntrService(&pThis->__nvoc_base_IntrService); + if (status != NV_OK) goto __nvoc_ctor_KernelSec2_fail_IntrService; status = __nvoc_ctor_KernelFalcon(&pThis->__nvoc_base_KernelFalcon, pRmhalspecowner); if (status != NV_OK) goto __nvoc_ctor_KernelSec2_fail_KernelFalcon; __nvoc_init_dataField_KernelSec2(pThis, pRmhalspecowner); goto __nvoc_ctor_KernelSec2_exit; // Success __nvoc_ctor_KernelSec2_fail_KernelFalcon: + __nvoc_dtor_IntrService(&pThis->__nvoc_base_IntrService); +__nvoc_ctor_KernelSec2_fail_IntrService: __nvoc_dtor_OBJENGSTATE(&pThis->__nvoc_base_OBJENGSTATE); __nvoc_ctor_KernelSec2_fail_OBJENGSTATE: __nvoc_ctor_KernelSec2_exit: @@ -223,130 +305,134 @@ PORT_UNREFERENCED_VARIABLE(chipHal_HalVarIdx); // Hal function -- ksec2ConstructEngine - if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000002UL) )) /* RmVariantHal: PF_KERNEL_ONLY */ - { - pThis->__ksec2ConstructEngine__ = &ksec2ConstructEngine_IMPL; - } + pThis->__ksec2ConstructEngine__ = &ksec2ConstructEngine_IMPL; + + // Hal function -- ksec2RegisterIntrService + pThis->__ksec2RegisterIntrService__ = &ksec2RegisterIntrService_IMPL; + + // Hal function -- ksec2ServiceNotificationInterrupt + pThis->__ksec2ServiceNotificationInterrupt__ = &ksec2ServiceNotificationInterrupt_IMPL; // Hal function -- ksec2ConfigureFalcon - if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000002UL) )) /* RmVariantHal: PF_KERNEL_ONLY */ + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x00000400UL) )) /* ChipHal: GA100 */ { - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x000003e0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 */ - { - pThis->__ksec2ConfigureFalcon__ = &ksec2ConfigureFalcon_TU102; - } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x00000400UL) )) /* ChipHal: GA100 */ - { - pThis->__ksec2ConfigureFalcon__ = &ksec2ConfigureFalcon_GA100; - } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x01f0f800UL) )) /* ChipHal: GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 */ - { - pThis->__ksec2ConfigureFalcon__ = &ksec2ConfigureFalcon_GA102; - } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ - { - pThis->__ksec2ConfigureFalcon__ = &ksec2ConfigureFalcon_f2d351; - } + pThis->__ksec2ConfigureFalcon__ = &ksec2ConfigureFalcon_GA100; + } + else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x000003e0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 */ + { + pThis->__ksec2ConfigureFalcon__ = &ksec2ConfigureFalcon_TU102; + } + else + { + pThis->__ksec2ConfigureFalcon__ = &ksec2ConfigureFalcon_GA102; } // Hal function -- ksec2ResetHw - if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000002UL) )) /* RmVariantHal: PF_KERNEL_ONLY */ + pThis->__ksec2ResetHw__ = &ksec2ResetHw_TU102; + + // Hal function -- ksec2StateLoad + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ + { + pThis->__ksec2StateLoad__ = &ksec2StateLoad_GH100; + } + // default + else { - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x01f0ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 */ - { - pThis->__ksec2ResetHw__ = &ksec2ResetHw_TU102; - } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ - { - pThis->__ksec2ResetHw__ = &ksec2ResetHw_5baef9; - } - } - - // Hal function -- ksec2IsEngineInReset - if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000002UL) )) /* RmVariantHal: PF_KERNEL_ONLY */ - { - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x01f0ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 */ - { - pThis->__ksec2IsEngineInReset__ = &ksec2IsEngineInReset_TU102; - } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ - { - pThis->__ksec2IsEngineInReset__ = &ksec2IsEngineInReset_108313; - } + pThis->__ksec2StateLoad__ = &ksec2StateLoad_56cd7a; } // Hal function -- ksec2ReadUcodeFuseVersion - if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000002UL) )) /* RmVariantHal: PF_KERNEL_ONLY */ + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x000003e0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 */ + { + pThis->__ksec2ReadUcodeFuseVersion__ = &ksec2ReadUcodeFuseVersion_b2b553; + } + else { - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x000003e0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 */ - { - pThis->__ksec2ReadUcodeFuseVersion__ = &ksec2ReadUcodeFuseVersion_b2b553; - } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x11f0fc00UL) )) /* ChipHal: GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 | GH100 */ - { - pThis->__ksec2ReadUcodeFuseVersion__ = &ksec2ReadUcodeFuseVersion_GA100; - } + pThis->__ksec2ReadUcodeFuseVersion__ = &ksec2ReadUcodeFuseVersion_GA100; } // Hal function -- ksec2GetBinArchiveBlUcode - if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000002UL) )) /* RmVariantHal: PF_KERNEL_ONLY */ + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x11f00000UL) )) /* ChipHal: AD102 | AD103 | AD104 | AD106 | AD107 | GH100 */ + { + pThis->__ksec2GetBinArchiveBlUcode__ = &ksec2GetBinArchiveBlUcode_80f438; + } + else { - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0000ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 */ - { - pThis->__ksec2GetBinArchiveBlUcode__ = &ksec2GetBinArchiveBlUcode_TU102; - } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x11f00000UL) )) /* ChipHal: AD102 | AD103 | AD104 | AD106 | AD107 | GH100 */ - { - pThis->__ksec2GetBinArchiveBlUcode__ = &ksec2GetBinArchiveBlUcode_80f438; - } + pThis->__ksec2GetBinArchiveBlUcode__ = &ksec2GetBinArchiveBlUcode_TU102; } // Hal function -- ksec2GetGenericBlUcode - if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000002UL) )) /* RmVariantHal: PF_KERNEL_ONLY */ + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x11f00000UL) )) /* ChipHal: AD102 | AD103 | AD104 | AD106 | AD107 | GH100 */ { - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0000ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 */ - { - pThis->__ksec2GetGenericBlUcode__ = &ksec2GetGenericBlUcode_TU102; - } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x11f00000UL) )) /* ChipHal: AD102 | AD103 | AD104 | AD106 | AD107 | GH100 */ - { - pThis->__ksec2GetGenericBlUcode__ = &ksec2GetGenericBlUcode_5baef9; - } + pThis->__ksec2GetGenericBlUcode__ = &ksec2GetGenericBlUcode_5baef9; + } + else + { + pThis->__ksec2GetGenericBlUcode__ = &ksec2GetGenericBlUcode_TU102; } // Hal function -- ksec2GetBinArchiveSecurescrubUcode - if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000002UL) )) /* RmVariantHal: PF_KERNEL_ONLY */ + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x01f00000UL) )) /* ChipHal: AD102 | AD103 | AD104 | AD106 | AD107 */ { - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x01f00000UL) )) /* ChipHal: AD102 | AD103 | AD104 | AD106 | AD107 */ - { - pThis->__ksec2GetBinArchiveSecurescrubUcode__ = &ksec2GetBinArchiveSecurescrubUcode_AD10X; - } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x1000ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | GH100 */ - { - pThis->__ksec2GetBinArchiveSecurescrubUcode__ = &ksec2GetBinArchiveSecurescrubUcode_80f438; - } + pThis->__ksec2GetBinArchiveSecurescrubUcode__ = &ksec2GetBinArchiveSecurescrubUcode_AD10X; + } + else + { + pThis->__ksec2GetBinArchiveSecurescrubUcode__ = &ksec2GetBinArchiveSecurescrubUcode_80f438; } pThis->__nvoc_base_OBJENGSTATE.__engstateConstructEngine__ = &__nvoc_thunk_KernelSec2_engstateConstructEngine; + pThis->__nvoc_base_IntrService.__intrservRegisterIntrService__ = &__nvoc_thunk_KernelSec2_intrservRegisterIntrService; + + pThis->__nvoc_base_IntrService.__intrservServiceNotificationInterrupt__ = &__nvoc_thunk_KernelSec2_intrservServiceNotificationInterrupt; + pThis->__nvoc_base_KernelFalcon.__kflcnResetHw__ = &__nvoc_thunk_KernelSec2_kflcnResetHw; - pThis->__nvoc_base_KernelFalcon.__kflcnIsEngineInReset__ = &__nvoc_thunk_KernelSec2_kflcnIsEngineInReset; + pThis->__nvoc_base_OBJENGSTATE.__engstateStateLoad__ = &__nvoc_thunk_KernelSec2_engstateStateLoad; + + pThis->__ksec2Configured__ = &__nvoc_thunk_KernelCrashCatEngine_ksec2Configured; + + pThis->__ksec2PriRead__ = &__nvoc_thunk_KernelCrashCatEngine_ksec2PriRead; + + pThis->__ksec2RegWrite__ = &__nvoc_thunk_KernelFalcon_ksec2RegWrite; + + pThis->__ksec2MaskDmemAddr__ = &__nvoc_thunk_KernelFalcon_ksec2MaskDmemAddr; + + pThis->__ksec2StateDestroy__ = &__nvoc_thunk_OBJENGSTATE_ksec2StateDestroy; + + pThis->__ksec2Vprintf__ = &__nvoc_thunk_KernelCrashCatEngine_ksec2Vprintf; + + pThis->__ksec2ClearInterrupt__ = &__nvoc_thunk_IntrService_ksec2ClearInterrupt; + + pThis->__ksec2PriWrite__ = &__nvoc_thunk_KernelCrashCatEngine_ksec2PriWrite; + + pThis->__ksec2MapBufferDescriptor__ = &__nvoc_thunk_KernelCrashCatEngine_ksec2MapBufferDescriptor; + + pThis->__ksec2SyncBufferDescriptor__ = &__nvoc_thunk_KernelCrashCatEngine_ksec2SyncBufferDescriptor; + + pThis->__ksec2RegRead__ = &__nvoc_thunk_KernelFalcon_ksec2RegRead; + + pThis->__ksec2IsPresent__ = &__nvoc_thunk_OBJENGSTATE_ksec2IsPresent; - pThis->__ksec2ReconcileTunableState__ = &__nvoc_thunk_OBJENGSTATE_ksec2ReconcileTunableState; + pThis->__ksec2ServiceInterrupt__ = &__nvoc_thunk_IntrService_ksec2ServiceInterrupt; - pThis->__ksec2StateLoad__ = &__nvoc_thunk_OBJENGSTATE_ksec2StateLoad; + pThis->__ksec2ReadEmem__ = &__nvoc_thunk_KernelCrashCatEngine_ksec2ReadEmem; + + pThis->__ksec2GetScratchOffsets__ = &__nvoc_thunk_KernelCrashCatEngine_ksec2GetScratchOffsets; + + pThis->__ksec2Unload__ = &__nvoc_thunk_KernelCrashCatEngine_ksec2Unload; pThis->__ksec2StateUnload__ = &__nvoc_thunk_OBJENGSTATE_ksec2StateUnload; + pThis->__ksec2GetWFL0Offset__ = &__nvoc_thunk_KernelCrashCatEngine_ksec2GetWFL0Offset; + pThis->__ksec2StateInitLocked__ = &__nvoc_thunk_OBJENGSTATE_ksec2StateInitLocked; pThis->__ksec2StatePreLoad__ = &__nvoc_thunk_OBJENGSTATE_ksec2StatePreLoad; pThis->__ksec2StatePostUnload__ = &__nvoc_thunk_OBJENGSTATE_ksec2StatePostUnload; - pThis->__ksec2StateDestroy__ = &__nvoc_thunk_OBJENGSTATE_ksec2StateDestroy; - pThis->__ksec2StatePreUnload__ = &__nvoc_thunk_OBJENGSTATE_ksec2StatePreUnload; pThis->__ksec2StateInitUnlocked__ = &__nvoc_thunk_OBJENGSTATE_ksec2StateInitUnlocked; @@ -357,19 +443,11 @@ pThis->__ksec2StatePreInitUnlocked__ = &__nvoc_thunk_OBJENGSTATE_ksec2StatePreInitUnlocked; - pThis->__ksec2GetTunableState__ = &__nvoc_thunk_OBJENGSTATE_ksec2GetTunableState; - - pThis->__ksec2CompareTunableState__ = &__nvoc_thunk_OBJENGSTATE_ksec2CompareTunableState; - - pThis->__ksec2FreeTunableState__ = &__nvoc_thunk_OBJENGSTATE_ksec2FreeTunableState; - pThis->__ksec2StatePostLoad__ = &__nvoc_thunk_OBJENGSTATE_ksec2StatePostLoad; - pThis->__ksec2AllocTunableState__ = &__nvoc_thunk_OBJENGSTATE_ksec2AllocTunableState; - - pThis->__ksec2SetTunableState__ = &__nvoc_thunk_OBJENGSTATE_ksec2SetTunableState; + pThis->__ksec2UnmapBufferDescriptor__ = &__nvoc_thunk_KernelCrashCatEngine_ksec2UnmapBufferDescriptor; - pThis->__ksec2IsPresent__ = &__nvoc_thunk_OBJENGSTATE_ksec2IsPresent; + pThis->__ksec2ReadDmem__ = &__nvoc_thunk_KernelCrashCatEngine_ksec2ReadDmem; } void __nvoc_init_funcTable_KernelSec2(KernelSec2 *pThis, RmHalspecOwner *pRmhalspecowner) { @@ -377,13 +455,18 @@ } void __nvoc_init_OBJENGSTATE(OBJENGSTATE*); +void __nvoc_init_IntrService(IntrService*); void __nvoc_init_KernelFalcon(KernelFalcon*, RmHalspecOwner* ); void __nvoc_init_KernelSec2(KernelSec2 *pThis, RmHalspecOwner *pRmhalspecowner) { pThis->__nvoc_pbase_KernelSec2 = pThis; pThis->__nvoc_pbase_Object = &pThis->__nvoc_base_OBJENGSTATE.__nvoc_base_Object; pThis->__nvoc_pbase_OBJENGSTATE = &pThis->__nvoc_base_OBJENGSTATE; + pThis->__nvoc_pbase_IntrService = &pThis->__nvoc_base_IntrService; + pThis->__nvoc_pbase_CrashCatEngine = &pThis->__nvoc_base_KernelFalcon.__nvoc_base_KernelCrashCatEngine.__nvoc_base_CrashCatEngine; + pThis->__nvoc_pbase_KernelCrashCatEngine = &pThis->__nvoc_base_KernelFalcon.__nvoc_base_KernelCrashCatEngine; pThis->__nvoc_pbase_KernelFalcon = &pThis->__nvoc_base_KernelFalcon; __nvoc_init_OBJENGSTATE(&pThis->__nvoc_base_OBJENGSTATE); + __nvoc_init_IntrService(&pThis->__nvoc_base_IntrService); __nvoc_init_KernelFalcon(&pThis->__nvoc_base_KernelFalcon, pRmhalspecowner); __nvoc_init_funcTable_KernelSec2(pThis, pRmhalspecowner); } @@ -394,13 +477,16 @@ KernelSec2 *pThis; RmHalspecOwner *pRmhalspecowner; - pThis = portMemAllocNonPaged(sizeof(KernelSec2)); - if (pThis == NULL) return NV_ERR_NO_MEMORY; + status = __nvoc_handleObjCreateMemAlloc(createFlags, sizeof(KernelSec2), (void**)&pThis, (void**)ppThis); + if (status != NV_OK) + return status; portMemSet(pThis, 0, sizeof(KernelSec2)); __nvoc_initRtti(staticCast(pThis, Dynamic), &__nvoc_class_def_KernelSec2); + pThis->__nvoc_base_OBJENGSTATE.__nvoc_base_Object.createFlags = createFlags; + if (pParent != NULL && !(createFlags & NVOC_OBJ_CREATE_FLAGS_PARENT_HALSPEC_ONLY)) { pParentObj = dynamicCast(pParent, Object); @@ -420,11 +506,17 @@ if (status != NV_OK) goto __nvoc_objCreate_KernelSec2_cleanup; *ppThis = pThis; + return NV_OK; __nvoc_objCreate_KernelSec2_cleanup: // do not call destructors here since the constructor already called them - portMemFree(pThis); + if (createFlags & NVOC_OBJ_CREATE_FLAGS_IN_PLACE_CONSTRUCT) + portMemSet(pThis, 0, sizeof(KernelSec2)); + else + portMemFree(pThis); + + // coverity[leaked_storage:FALSE] return status; } diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/generated/g_kernel_sec2_nvoc.h nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_kernel_sec2_nvoc.h --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/generated/g_kernel_sec2_nvoc.h 2023-10-25 20:27:11.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_kernel_sec2_nvoc.h 2024-03-05 22:18:32.000000000 +0000 @@ -7,7 +7,7 @@ #endif /* - * SPDX-FileCopyrightText: Copyright (c) 2021-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2021-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -52,38 +52,54 @@ struct KernelSec2 { const struct NVOC_RTTI *__nvoc_rtti; struct OBJENGSTATE __nvoc_base_OBJENGSTATE; + struct IntrService __nvoc_base_IntrService; struct KernelFalcon __nvoc_base_KernelFalcon; struct Object *__nvoc_pbase_Object; struct OBJENGSTATE *__nvoc_pbase_OBJENGSTATE; + struct IntrService *__nvoc_pbase_IntrService; + struct CrashCatEngine *__nvoc_pbase_CrashCatEngine; + struct KernelCrashCatEngine *__nvoc_pbase_KernelCrashCatEngine; struct KernelFalcon *__nvoc_pbase_KernelFalcon; struct KernelSec2 *__nvoc_pbase_KernelSec2; NV_STATUS (*__ksec2ConstructEngine__)(struct OBJGPU *, struct KernelSec2 *, ENGDESCRIPTOR); + void (*__ksec2RegisterIntrService__)(struct OBJGPU *, struct KernelSec2 *, IntrServiceRecord *); + NV_STATUS (*__ksec2ServiceNotificationInterrupt__)(struct OBJGPU *, struct KernelSec2 *, IntrServiceServiceNotificationInterruptArguments *); void (*__ksec2ConfigureFalcon__)(struct OBJGPU *, struct KernelSec2 *); NV_STATUS (*__ksec2ResetHw__)(struct OBJGPU *, struct KernelSec2 *); - NvBool (*__ksec2IsEngineInReset__)(struct OBJGPU *, struct KernelSec2 *); + NV_STATUS (*__ksec2StateLoad__)(struct OBJGPU *, struct KernelSec2 *, NvU32); NvU32 (*__ksec2ReadUcodeFuseVersion__)(struct OBJGPU *, struct KernelSec2 *, NvU32); const BINDATA_ARCHIVE *(*__ksec2GetBinArchiveBlUcode__)(struct OBJGPU *, struct KernelSec2 *); NV_STATUS (*__ksec2GetGenericBlUcode__)(struct OBJGPU *, struct KernelSec2 *, const RM_FLCN_BL_DESC **, const NvU8 **); const BINDATA_ARCHIVE *(*__ksec2GetBinArchiveSecurescrubUcode__)(struct OBJGPU *, struct KernelSec2 *); - NV_STATUS (*__ksec2ReconcileTunableState__)(POBJGPU, struct KernelSec2 *, void *); - NV_STATUS (*__ksec2StateLoad__)(POBJGPU, struct KernelSec2 *, NvU32); + NvBool (*__ksec2Configured__)(struct KernelSec2 *); + NvU32 (*__ksec2PriRead__)(struct KernelSec2 *, NvU32); + void (*__ksec2RegWrite__)(struct OBJGPU *, struct KernelSec2 *, NvU32, NvU32); + NvU32 (*__ksec2MaskDmemAddr__)(struct OBJGPU *, struct KernelSec2 *, NvU32); + void (*__ksec2StateDestroy__)(POBJGPU, struct KernelSec2 *); + void (*__ksec2Vprintf__)(struct KernelSec2 *, NvBool, const char *, va_list); + NvBool (*__ksec2ClearInterrupt__)(struct OBJGPU *, struct KernelSec2 *, IntrServiceClearInterruptArguments *); + void (*__ksec2PriWrite__)(struct KernelSec2 *, NvU32, NvU32); + void *(*__ksec2MapBufferDescriptor__)(struct KernelSec2 *, CrashCatBufferDescriptor *); + void (*__ksec2SyncBufferDescriptor__)(struct KernelSec2 *, CrashCatBufferDescriptor *, NvU32, NvU32); + NvU32 (*__ksec2RegRead__)(struct OBJGPU *, struct KernelSec2 *, NvU32); + NvBool (*__ksec2IsPresent__)(POBJGPU, struct KernelSec2 *); + NvU32 (*__ksec2ServiceInterrupt__)(struct OBJGPU *, struct KernelSec2 *, IntrServiceServiceInterruptArguments *); + void (*__ksec2ReadEmem__)(struct KernelSec2 *, NvU64, NvU64, void *); + const NvU32 *(*__ksec2GetScratchOffsets__)(struct KernelSec2 *, NV_CRASHCAT_SCRATCH_GROUP_ID); + void (*__ksec2Unload__)(struct KernelSec2 *); NV_STATUS (*__ksec2StateUnload__)(POBJGPU, struct KernelSec2 *, NvU32); + NvU32 (*__ksec2GetWFL0Offset__)(struct KernelSec2 *); NV_STATUS (*__ksec2StateInitLocked__)(POBJGPU, struct KernelSec2 *); NV_STATUS (*__ksec2StatePreLoad__)(POBJGPU, struct KernelSec2 *, NvU32); NV_STATUS (*__ksec2StatePostUnload__)(POBJGPU, struct KernelSec2 *, NvU32); - void (*__ksec2StateDestroy__)(POBJGPU, struct KernelSec2 *); NV_STATUS (*__ksec2StatePreUnload__)(POBJGPU, struct KernelSec2 *, NvU32); NV_STATUS (*__ksec2StateInitUnlocked__)(POBJGPU, struct KernelSec2 *); void (*__ksec2InitMissing__)(POBJGPU, struct KernelSec2 *); NV_STATUS (*__ksec2StatePreInitLocked__)(POBJGPU, struct KernelSec2 *); NV_STATUS (*__ksec2StatePreInitUnlocked__)(POBJGPU, struct KernelSec2 *); - NV_STATUS (*__ksec2GetTunableState__)(POBJGPU, struct KernelSec2 *, void *); - NV_STATUS (*__ksec2CompareTunableState__)(POBJGPU, struct KernelSec2 *, void *, void *); - void (*__ksec2FreeTunableState__)(POBJGPU, struct KernelSec2 *, void *); NV_STATUS (*__ksec2StatePostLoad__)(POBJGPU, struct KernelSec2 *, NvU32); - NV_STATUS (*__ksec2AllocTunableState__)(POBJGPU, struct KernelSec2 *, void **); - NV_STATUS (*__ksec2SetTunableState__)(POBJGPU, struct KernelSec2 *, void *); - NvBool (*__ksec2IsPresent__)(POBJGPU, struct KernelSec2 *); + void (*__ksec2UnmapBufferDescriptor__)(struct KernelSec2 *, CrashCatBufferDescriptor *); + void (*__ksec2ReadDmem__)(struct KernelSec2 *, NvU32, NvU32, void *); const RM_FLCN_BL_DESC *pGenericBlUcodeDesc; const NvU8 *pGenericBlUcodeImg; }; @@ -120,12 +136,16 @@ #define ksec2ConstructEngine(pGpu, pKernelSec2, arg0) ksec2ConstructEngine_DISPATCH(pGpu, pKernelSec2, arg0) #define ksec2ConstructEngine_HAL(pGpu, pKernelSec2, arg0) ksec2ConstructEngine_DISPATCH(pGpu, pKernelSec2, arg0) +#define ksec2RegisterIntrService(pGpu, pKernelSec2, pRecords) ksec2RegisterIntrService_DISPATCH(pGpu, pKernelSec2, pRecords) +#define ksec2RegisterIntrService_HAL(pGpu, pKernelSec2, pRecords) ksec2RegisterIntrService_DISPATCH(pGpu, pKernelSec2, pRecords) +#define ksec2ServiceNotificationInterrupt(arg0, arg1, arg2) ksec2ServiceNotificationInterrupt_DISPATCH(arg0, arg1, arg2) +#define ksec2ServiceNotificationInterrupt_HAL(arg0, arg1, arg2) ksec2ServiceNotificationInterrupt_DISPATCH(arg0, arg1, arg2) #define ksec2ConfigureFalcon(pGpu, pKernelSec2) ksec2ConfigureFalcon_DISPATCH(pGpu, pKernelSec2) #define ksec2ConfigureFalcon_HAL(pGpu, pKernelSec2) ksec2ConfigureFalcon_DISPATCH(pGpu, pKernelSec2) #define ksec2ResetHw(pGpu, pKernelSec2) ksec2ResetHw_DISPATCH(pGpu, pKernelSec2) #define ksec2ResetHw_HAL(pGpu, pKernelSec2) ksec2ResetHw_DISPATCH(pGpu, pKernelSec2) -#define ksec2IsEngineInReset(pGpu, pKernelSec2) ksec2IsEngineInReset_DISPATCH(pGpu, pKernelSec2) -#define ksec2IsEngineInReset_HAL(pGpu, pKernelSec2) ksec2IsEngineInReset_DISPATCH(pGpu, pKernelSec2) +#define ksec2StateLoad(pGpu, pKernelSec2, arg0) ksec2StateLoad_DISPATCH(pGpu, pKernelSec2, arg0) +#define ksec2StateLoad_HAL(pGpu, pKernelSec2, arg0) ksec2StateLoad_DISPATCH(pGpu, pKernelSec2, arg0) #define ksec2ReadUcodeFuseVersion(pGpu, pKernelSec2, ucodeId) ksec2ReadUcodeFuseVersion_DISPATCH(pGpu, pKernelSec2, ucodeId) #define ksec2ReadUcodeFuseVersion_HAL(pGpu, pKernelSec2, ucodeId) ksec2ReadUcodeFuseVersion_DISPATCH(pGpu, pKernelSec2, ucodeId) #define ksec2GetBinArchiveBlUcode(pGpu, pKernelSec2) ksec2GetBinArchiveBlUcode_DISPATCH(pGpu, pKernelSec2) @@ -134,63 +154,77 @@ #define ksec2GetGenericBlUcode_HAL(pGpu, pKernelSec2, ppDesc, ppImg) ksec2GetGenericBlUcode_DISPATCH(pGpu, pKernelSec2, ppDesc, ppImg) #define ksec2GetBinArchiveSecurescrubUcode(pGpu, pKernelSec2) ksec2GetBinArchiveSecurescrubUcode_DISPATCH(pGpu, pKernelSec2) #define ksec2GetBinArchiveSecurescrubUcode_HAL(pGpu, pKernelSec2) ksec2GetBinArchiveSecurescrubUcode_DISPATCH(pGpu, pKernelSec2) -#define ksec2ReconcileTunableState(pGpu, pEngstate, pTunableState) ksec2ReconcileTunableState_DISPATCH(pGpu, pEngstate, pTunableState) -#define ksec2StateLoad(pGpu, pEngstate, arg0) ksec2StateLoad_DISPATCH(pGpu, pEngstate, arg0) +#define ksec2Configured(arg0) ksec2Configured_DISPATCH(arg0) +#define ksec2PriRead(arg0, offset) ksec2PriRead_DISPATCH(arg0, offset) +#define ksec2RegWrite(pGpu, pKernelFlcn, offset, data) ksec2RegWrite_DISPATCH(pGpu, pKernelFlcn, offset, data) +#define ksec2MaskDmemAddr(pGpu, pKernelFlcn, addr) ksec2MaskDmemAddr_DISPATCH(pGpu, pKernelFlcn, addr) +#define ksec2StateDestroy(pGpu, pEngstate) ksec2StateDestroy_DISPATCH(pGpu, pEngstate) +#define ksec2Vprintf(arg0, bReportStart, fmt, args) ksec2Vprintf_DISPATCH(arg0, bReportStart, fmt, args) +#define ksec2ClearInterrupt(pGpu, pIntrService, pParams) ksec2ClearInterrupt_DISPATCH(pGpu, pIntrService, pParams) +#define ksec2PriWrite(arg0, offset, data) ksec2PriWrite_DISPATCH(arg0, offset, data) +#define ksec2MapBufferDescriptor(arg0, pBufDesc) ksec2MapBufferDescriptor_DISPATCH(arg0, pBufDesc) +#define ksec2SyncBufferDescriptor(arg0, pBufDesc, offset, size) ksec2SyncBufferDescriptor_DISPATCH(arg0, pBufDesc, offset, size) +#define ksec2RegRead(pGpu, pKernelFlcn, offset) ksec2RegRead_DISPATCH(pGpu, pKernelFlcn, offset) +#define ksec2IsPresent(pGpu, pEngstate) ksec2IsPresent_DISPATCH(pGpu, pEngstate) +#define ksec2ServiceInterrupt(pGpu, pIntrService, pParams) ksec2ServiceInterrupt_DISPATCH(pGpu, pIntrService, pParams) +#define ksec2ReadEmem(arg0, offset, size, pBuf) ksec2ReadEmem_DISPATCH(arg0, offset, size, pBuf) +#define ksec2GetScratchOffsets(arg0, scratchGroupId) ksec2GetScratchOffsets_DISPATCH(arg0, scratchGroupId) +#define ksec2Unload(arg0) ksec2Unload_DISPATCH(arg0) #define ksec2StateUnload(pGpu, pEngstate, arg0) ksec2StateUnload_DISPATCH(pGpu, pEngstate, arg0) +#define ksec2GetWFL0Offset(arg0) ksec2GetWFL0Offset_DISPATCH(arg0) #define ksec2StateInitLocked(pGpu, pEngstate) ksec2StateInitLocked_DISPATCH(pGpu, pEngstate) #define ksec2StatePreLoad(pGpu, pEngstate, arg0) ksec2StatePreLoad_DISPATCH(pGpu, pEngstate, arg0) #define ksec2StatePostUnload(pGpu, pEngstate, arg0) ksec2StatePostUnload_DISPATCH(pGpu, pEngstate, arg0) -#define ksec2StateDestroy(pGpu, pEngstate) ksec2StateDestroy_DISPATCH(pGpu, pEngstate) #define ksec2StatePreUnload(pGpu, pEngstate, arg0) ksec2StatePreUnload_DISPATCH(pGpu, pEngstate, arg0) #define ksec2StateInitUnlocked(pGpu, pEngstate) ksec2StateInitUnlocked_DISPATCH(pGpu, pEngstate) #define ksec2InitMissing(pGpu, pEngstate) ksec2InitMissing_DISPATCH(pGpu, pEngstate) #define ksec2StatePreInitLocked(pGpu, pEngstate) ksec2StatePreInitLocked_DISPATCH(pGpu, pEngstate) #define ksec2StatePreInitUnlocked(pGpu, pEngstate) ksec2StatePreInitUnlocked_DISPATCH(pGpu, pEngstate) -#define ksec2GetTunableState(pGpu, pEngstate, pTunableState) ksec2GetTunableState_DISPATCH(pGpu, pEngstate, pTunableState) -#define ksec2CompareTunableState(pGpu, pEngstate, pTunables1, pTunables2) ksec2CompareTunableState_DISPATCH(pGpu, pEngstate, pTunables1, pTunables2) -#define ksec2FreeTunableState(pGpu, pEngstate, pTunableState) ksec2FreeTunableState_DISPATCH(pGpu, pEngstate, pTunableState) #define ksec2StatePostLoad(pGpu, pEngstate, arg0) ksec2StatePostLoad_DISPATCH(pGpu, pEngstate, arg0) -#define ksec2AllocTunableState(pGpu, pEngstate, ppTunableState) ksec2AllocTunableState_DISPATCH(pGpu, pEngstate, ppTunableState) -#define ksec2SetTunableState(pGpu, pEngstate, pTunableState) ksec2SetTunableState_DISPATCH(pGpu, pEngstate, pTunableState) -#define ksec2IsPresent(pGpu, pEngstate) ksec2IsPresent_DISPATCH(pGpu, pEngstate) +#define ksec2UnmapBufferDescriptor(arg0, pBufDesc) ksec2UnmapBufferDescriptor_DISPATCH(arg0, pBufDesc) +#define ksec2ReadDmem(arg0, offset, size, pBuf) ksec2ReadDmem_DISPATCH(arg0, offset, size, pBuf) NV_STATUS ksec2ConstructEngine_IMPL(struct OBJGPU *pGpu, struct KernelSec2 *pKernelSec2, ENGDESCRIPTOR arg0); static inline NV_STATUS ksec2ConstructEngine_DISPATCH(struct OBJGPU *pGpu, struct KernelSec2 *pKernelSec2, ENGDESCRIPTOR arg0) { return pKernelSec2->__ksec2ConstructEngine__(pGpu, pKernelSec2, arg0); } +void ksec2RegisterIntrService_IMPL(struct OBJGPU *pGpu, struct KernelSec2 *pKernelSec2, IntrServiceRecord pRecords[167]); + +static inline void ksec2RegisterIntrService_DISPATCH(struct OBJGPU *pGpu, struct KernelSec2 *pKernelSec2, IntrServiceRecord pRecords[167]) { + pKernelSec2->__ksec2RegisterIntrService__(pGpu, pKernelSec2, pRecords); +} + +NV_STATUS ksec2ServiceNotificationInterrupt_IMPL(struct OBJGPU *arg0, struct KernelSec2 *arg1, IntrServiceServiceNotificationInterruptArguments *arg2); + +static inline NV_STATUS ksec2ServiceNotificationInterrupt_DISPATCH(struct OBJGPU *arg0, struct KernelSec2 *arg1, IntrServiceServiceNotificationInterruptArguments *arg2) { + return arg1->__ksec2ServiceNotificationInterrupt__(arg0, arg1, arg2); +} + void ksec2ConfigureFalcon_TU102(struct OBJGPU *pGpu, struct KernelSec2 *pKernelSec2); void ksec2ConfigureFalcon_GA100(struct OBJGPU *pGpu, struct KernelSec2 *pKernelSec2); void ksec2ConfigureFalcon_GA102(struct OBJGPU *pGpu, struct KernelSec2 *pKernelSec2); -static inline void ksec2ConfigureFalcon_f2d351(struct OBJGPU *pGpu, struct KernelSec2 *pKernelSec2) { - NV_ASSERT_PRECOMP(0); -} - static inline void ksec2ConfigureFalcon_DISPATCH(struct OBJGPU *pGpu, struct KernelSec2 *pKernelSec2) { pKernelSec2->__ksec2ConfigureFalcon__(pGpu, pKernelSec2); } NV_STATUS ksec2ResetHw_TU102(struct OBJGPU *pGpu, struct KernelSec2 *pKernelSec2); -static inline NV_STATUS ksec2ResetHw_5baef9(struct OBJGPU *pGpu, struct KernelSec2 *pKernelSec2) { - NV_ASSERT_OR_RETURN_PRECOMP(0, NV_ERR_NOT_SUPPORTED); -} - static inline NV_STATUS ksec2ResetHw_DISPATCH(struct OBJGPU *pGpu, struct KernelSec2 *pKernelSec2) { return pKernelSec2->__ksec2ResetHw__(pGpu, pKernelSec2); } -NvBool ksec2IsEngineInReset_TU102(struct OBJGPU *pGpu, struct KernelSec2 *pKernelSec2); +NV_STATUS ksec2StateLoad_GH100(struct OBJGPU *pGpu, struct KernelSec2 *pKernelSec2, NvU32 arg0); -static inline NvBool ksec2IsEngineInReset_108313(struct OBJGPU *pGpu, struct KernelSec2 *pKernelSec2) { - NV_ASSERT_OR_RETURN_PRECOMP(0, ((NvBool)(0 != 0))); +static inline NV_STATUS ksec2StateLoad_56cd7a(struct OBJGPU *pGpu, struct KernelSec2 *pKernelSec2, NvU32 arg0) { + return NV_OK; } -static inline NvBool ksec2IsEngineInReset_DISPATCH(struct OBJGPU *pGpu, struct KernelSec2 *pKernelSec2) { - return pKernelSec2->__ksec2IsEngineInReset__(pGpu, pKernelSec2); +static inline NV_STATUS ksec2StateLoad_DISPATCH(struct OBJGPU *pGpu, struct KernelSec2 *pKernelSec2, NvU32 arg0) { + return pKernelSec2->__ksec2StateLoad__(pGpu, pKernelSec2, arg0); } static inline NvU32 ksec2ReadUcodeFuseVersion_b2b553(struct OBJGPU *pGpu, struct KernelSec2 *pKernelSec2, NvU32 ucodeId) { @@ -233,18 +267,78 @@ return pKernelSec2->__ksec2GetBinArchiveSecurescrubUcode__(pGpu, pKernelSec2); } -static inline NV_STATUS ksec2ReconcileTunableState_DISPATCH(POBJGPU pGpu, struct KernelSec2 *pEngstate, void *pTunableState) { - return pEngstate->__ksec2ReconcileTunableState__(pGpu, pEngstate, pTunableState); +static inline NvBool ksec2Configured_DISPATCH(struct KernelSec2 *arg0) { + return arg0->__ksec2Configured__(arg0); } -static inline NV_STATUS ksec2StateLoad_DISPATCH(POBJGPU pGpu, struct KernelSec2 *pEngstate, NvU32 arg0) { - return pEngstate->__ksec2StateLoad__(pGpu, pEngstate, arg0); +static inline NvU32 ksec2PriRead_DISPATCH(struct KernelSec2 *arg0, NvU32 offset) { + return arg0->__ksec2PriRead__(arg0, offset); +} + +static inline void ksec2RegWrite_DISPATCH(struct OBJGPU *pGpu, struct KernelSec2 *pKernelFlcn, NvU32 offset, NvU32 data) { + pKernelFlcn->__ksec2RegWrite__(pGpu, pKernelFlcn, offset, data); +} + +static inline NvU32 ksec2MaskDmemAddr_DISPATCH(struct OBJGPU *pGpu, struct KernelSec2 *pKernelFlcn, NvU32 addr) { + return pKernelFlcn->__ksec2MaskDmemAddr__(pGpu, pKernelFlcn, addr); +} + +static inline void ksec2StateDestroy_DISPATCH(POBJGPU pGpu, struct KernelSec2 *pEngstate) { + pEngstate->__ksec2StateDestroy__(pGpu, pEngstate); +} + +static inline void ksec2Vprintf_DISPATCH(struct KernelSec2 *arg0, NvBool bReportStart, const char *fmt, va_list args) { + arg0->__ksec2Vprintf__(arg0, bReportStart, fmt, args); +} + +static inline NvBool ksec2ClearInterrupt_DISPATCH(struct OBJGPU *pGpu, struct KernelSec2 *pIntrService, IntrServiceClearInterruptArguments *pParams) { + return pIntrService->__ksec2ClearInterrupt__(pGpu, pIntrService, pParams); +} + +static inline void ksec2PriWrite_DISPATCH(struct KernelSec2 *arg0, NvU32 offset, NvU32 data) { + arg0->__ksec2PriWrite__(arg0, offset, data); +} + +static inline void *ksec2MapBufferDescriptor_DISPATCH(struct KernelSec2 *arg0, CrashCatBufferDescriptor *pBufDesc) { + return arg0->__ksec2MapBufferDescriptor__(arg0, pBufDesc); +} + +static inline void ksec2SyncBufferDescriptor_DISPATCH(struct KernelSec2 *arg0, CrashCatBufferDescriptor *pBufDesc, NvU32 offset, NvU32 size) { + arg0->__ksec2SyncBufferDescriptor__(arg0, pBufDesc, offset, size); +} + +static inline NvU32 ksec2RegRead_DISPATCH(struct OBJGPU *pGpu, struct KernelSec2 *pKernelFlcn, NvU32 offset) { + return pKernelFlcn->__ksec2RegRead__(pGpu, pKernelFlcn, offset); +} + +static inline NvBool ksec2IsPresent_DISPATCH(POBJGPU pGpu, struct KernelSec2 *pEngstate) { + return pEngstate->__ksec2IsPresent__(pGpu, pEngstate); +} + +static inline NvU32 ksec2ServiceInterrupt_DISPATCH(struct OBJGPU *pGpu, struct KernelSec2 *pIntrService, IntrServiceServiceInterruptArguments *pParams) { + return pIntrService->__ksec2ServiceInterrupt__(pGpu, pIntrService, pParams); +} + +static inline void ksec2ReadEmem_DISPATCH(struct KernelSec2 *arg0, NvU64 offset, NvU64 size, void *pBuf) { + arg0->__ksec2ReadEmem__(arg0, offset, size, pBuf); +} + +static inline const NvU32 *ksec2GetScratchOffsets_DISPATCH(struct KernelSec2 *arg0, NV_CRASHCAT_SCRATCH_GROUP_ID scratchGroupId) { + return arg0->__ksec2GetScratchOffsets__(arg0, scratchGroupId); +} + +static inline void ksec2Unload_DISPATCH(struct KernelSec2 *arg0) { + arg0->__ksec2Unload__(arg0); } static inline NV_STATUS ksec2StateUnload_DISPATCH(POBJGPU pGpu, struct KernelSec2 *pEngstate, NvU32 arg0) { return pEngstate->__ksec2StateUnload__(pGpu, pEngstate, arg0); } +static inline NvU32 ksec2GetWFL0Offset_DISPATCH(struct KernelSec2 *arg0) { + return arg0->__ksec2GetWFL0Offset__(arg0); +} + static inline NV_STATUS ksec2StateInitLocked_DISPATCH(POBJGPU pGpu, struct KernelSec2 *pEngstate) { return pEngstate->__ksec2StateInitLocked__(pGpu, pEngstate); } @@ -257,10 +351,6 @@ return pEngstate->__ksec2StatePostUnload__(pGpu, pEngstate, arg0); } -static inline void ksec2StateDestroy_DISPATCH(POBJGPU pGpu, struct KernelSec2 *pEngstate) { - pEngstate->__ksec2StateDestroy__(pGpu, pEngstate); -} - static inline NV_STATUS ksec2StatePreUnload_DISPATCH(POBJGPU pGpu, struct KernelSec2 *pEngstate, NvU32 arg0) { return pEngstate->__ksec2StatePreUnload__(pGpu, pEngstate, arg0); } @@ -281,32 +371,16 @@ return pEngstate->__ksec2StatePreInitUnlocked__(pGpu, pEngstate); } -static inline NV_STATUS ksec2GetTunableState_DISPATCH(POBJGPU pGpu, struct KernelSec2 *pEngstate, void *pTunableState) { - return pEngstate->__ksec2GetTunableState__(pGpu, pEngstate, pTunableState); -} - -static inline NV_STATUS ksec2CompareTunableState_DISPATCH(POBJGPU pGpu, struct KernelSec2 *pEngstate, void *pTunables1, void *pTunables2) { - return pEngstate->__ksec2CompareTunableState__(pGpu, pEngstate, pTunables1, pTunables2); -} - -static inline void ksec2FreeTunableState_DISPATCH(POBJGPU pGpu, struct KernelSec2 *pEngstate, void *pTunableState) { - pEngstate->__ksec2FreeTunableState__(pGpu, pEngstate, pTunableState); -} - static inline NV_STATUS ksec2StatePostLoad_DISPATCH(POBJGPU pGpu, struct KernelSec2 *pEngstate, NvU32 arg0) { return pEngstate->__ksec2StatePostLoad__(pGpu, pEngstate, arg0); } -static inline NV_STATUS ksec2AllocTunableState_DISPATCH(POBJGPU pGpu, struct KernelSec2 *pEngstate, void **ppTunableState) { - return pEngstate->__ksec2AllocTunableState__(pGpu, pEngstate, ppTunableState); +static inline void ksec2UnmapBufferDescriptor_DISPATCH(struct KernelSec2 *arg0, CrashCatBufferDescriptor *pBufDesc) { + arg0->__ksec2UnmapBufferDescriptor__(arg0, pBufDesc); } -static inline NV_STATUS ksec2SetTunableState_DISPATCH(POBJGPU pGpu, struct KernelSec2 *pEngstate, void *pTunableState) { - return pEngstate->__ksec2SetTunableState__(pGpu, pEngstate, pTunableState); -} - -static inline NvBool ksec2IsPresent_DISPATCH(POBJGPU pGpu, struct KernelSec2 *pEngstate) { - return pEngstate->__ksec2IsPresent__(pGpu, pEngstate); +static inline void ksec2ReadDmem_DISPATCH(struct KernelSec2 *arg0, NvU32 offset, NvU32 size, void *pBuf) { + arg0->__ksec2ReadDmem__(arg0, offset, size, pBuf); } void ksec2Destruct_IMPL(struct KernelSec2 *pKernelSec2); diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/generated/g_kernel_sm_debugger_session_nvoc.c nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_kernel_sm_debugger_session_nvoc.c --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/generated/g_kernel_sm_debugger_session_nvoc.c 2023-10-25 20:27:11.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_kernel_sm_debugger_session_nvoc.c 2024-03-05 22:18:32.000000000 +0000 @@ -144,13 +144,16 @@ Object *pParentObj; RmDebuggerSession *pThis; - pThis = portMemAllocNonPaged(sizeof(RmDebuggerSession)); - if (pThis == NULL) return NV_ERR_NO_MEMORY; + status = __nvoc_handleObjCreateMemAlloc(createFlags, sizeof(RmDebuggerSession), (void**)&pThis, (void**)ppThis); + if (status != NV_OK) + return status; portMemSet(pThis, 0, sizeof(RmDebuggerSession)); __nvoc_initRtti(staticCast(pThis, Dynamic), &__nvoc_class_def_RmDebuggerSession); + pThis->__nvoc_base_RsSession.__nvoc_base_RsShared.__nvoc_base_Object.createFlags = createFlags; + if (pParent != NULL && !(createFlags & NVOC_OBJ_CREATE_FLAGS_PARENT_HALSPEC_ONLY)) { pParentObj = dynamicCast(pParent, Object); @@ -166,11 +169,17 @@ if (status != NV_OK) goto __nvoc_objCreate_RmDebuggerSession_cleanup; *ppThis = pThis; + return NV_OK; __nvoc_objCreate_RmDebuggerSession_cleanup: // do not call destructors here since the constructor already called them - portMemFree(pThis); + if (createFlags & NVOC_OBJ_CREATE_FLAGS_IN_PLACE_CONSTRUCT) + portMemSet(pThis, 0, sizeof(RmDebuggerSession)); + else + portMemFree(pThis); + + // coverity[leaked_storage:FALSE] return status; } @@ -298,16 +307,16 @@ return gpuresShareCallback((struct GpuResource *)(((unsigned char *)pGpuResource) + __nvoc_rtti_KernelSMDebuggerSession_GpuResource.offset), pInvokingClient, pParentRef, pSharePolicy); } -static NV_STATUS __nvoc_thunk_RsResource_ksmdbgssnMapTo(struct KernelSMDebuggerSession *pResource, RS_RES_MAP_TO_PARAMS *pParams) { - return resMapTo((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_KernelSMDebuggerSession_RsResource.offset), pParams); +static NV_STATUS __nvoc_thunk_RmResource_ksmdbgssnCheckMemInterUnmap(struct KernelSMDebuggerSession *pRmResource, NvBool bSubdeviceHandleProvided) { + return rmresCheckMemInterUnmap((struct RmResource *)(((unsigned char *)pRmResource) + __nvoc_rtti_KernelSMDebuggerSession_RmResource.offset), bSubdeviceHandleProvided); } static NV_STATUS __nvoc_thunk_Notifier_ksmdbgssnGetOrAllocNotifShare(struct KernelSMDebuggerSession *pNotifier, NvHandle hNotifierClient, NvHandle hNotifierResource, struct NotifShare **ppNotifShare) { return notifyGetOrAllocNotifShare((struct Notifier *)(((unsigned char *)pNotifier) + __nvoc_rtti_KernelSMDebuggerSession_Notifier.offset), hNotifierClient, hNotifierResource, ppNotifShare); } -static NV_STATUS __nvoc_thunk_RmResource_ksmdbgssnCheckMemInterUnmap(struct KernelSMDebuggerSession *pRmResource, NvBool bSubdeviceHandleProvided) { - return rmresCheckMemInterUnmap((struct RmResource *)(((unsigned char *)pRmResource) + __nvoc_rtti_KernelSMDebuggerSession_RmResource.offset), bSubdeviceHandleProvided); +static NV_STATUS __nvoc_thunk_RsResource_ksmdbgssnMapTo(struct KernelSMDebuggerSession *pResource, RS_RES_MAP_TO_PARAMS *pParams) { + return resMapTo((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_KernelSMDebuggerSession_RsResource.offset), pParams); } static NV_STATUS __nvoc_thunk_GpuResource_ksmdbgssnGetMapAddrSpace(struct KernelSMDebuggerSession *pGpuResource, struct CALL_CONTEXT *pCallContext, NvU32 mapFlags, NV_ADDRESS_SPACE *pAddrSpace) { @@ -370,6 +379,10 @@ return notifyUnregisterEvent((struct Notifier *)(((unsigned char *)pNotifier) + __nvoc_rtti_KernelSMDebuggerSession_Notifier.offset), hNotifierClient, hNotifierResource, hEventClient, hEvent); } +static NV_STATUS __nvoc_thunk_RmResource_ksmdbgssnControlSerialization_Prologue(struct KernelSMDebuggerSession *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return rmresControlSerialization_Prologue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_KernelSMDebuggerSession_RmResource.offset), pCallContext, pParams); +} + static NvBool __nvoc_thunk_RsResource_ksmdbgssnCanCopy(struct KernelSMDebuggerSession *pResource) { return resCanCopy((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_KernelSMDebuggerSession_RsResource.offset)); } @@ -382,6 +395,10 @@ return resIsDuplicate((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_KernelSMDebuggerSession_RsResource.offset), hMemory, pDuplicate); } +static void __nvoc_thunk_RmResource_ksmdbgssnControlSerialization_Epilogue(struct KernelSMDebuggerSession *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + rmresControlSerialization_Epilogue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_KernelSMDebuggerSession_RmResource.offset), pCallContext, pParams); +} + static PEVENTNOTIFICATION *__nvoc_thunk_Notifier_ksmdbgssnGetNotificationListPtr(struct KernelSMDebuggerSession *pNotifier) { return notifyGetNotificationListPtr((struct Notifier *)(((unsigned char *)pNotifier) + __nvoc_rtti_KernelSMDebuggerSession_Notifier.offset)); } @@ -405,6 +422,36 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_KernelSMDebuggerSession[] = { { /* [0] */ +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x2200u) + /*pFunc=*/ (void (*)(void)) NULL, +#else + /*pFunc=*/ (void (*)(void)) ksmdbgssnCtrlCmdSMDebugModeEnable_fcf1ac, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x2200u) + /*flags=*/ 0x2200u, + /*accessRight=*/0x0u, + /*methodId=*/ 0x83de0301u, + /*paramSize=*/ 0, + /*pClassInfo=*/ &(__nvoc_class_def_KernelSMDebuggerSession.classInfo), +#if NV_PRINTF_STRINGS_ALLOWED + /*func=*/ "ksmdbgssnCtrlCmdSMDebugModeEnable" +#endif + }, + { /* [1] */ +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x2200u) + /*pFunc=*/ (void (*)(void)) NULL, +#else + /*pFunc=*/ (void (*)(void)) ksmdbgssnCtrlCmdSMDebugModeDisable_fcf1ac, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x2200u) + /*flags=*/ 0x2200u, + /*accessRight=*/0x0u, + /*methodId=*/ 0x83de0302u, + /*paramSize=*/ 0, + /*pClassInfo=*/ &(__nvoc_class_def_KernelSMDebuggerSession.classInfo), +#if NV_PRINTF_STRINGS_ALLOWED + /*func=*/ "ksmdbgssnCtrlCmdSMDebugModeDisable" +#endif + }, + { /* [2] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x2210u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -419,7 +466,7 @@ /*func=*/ "ksmdbgssnCtrlCmdDebugSetModeMMUDebug" #endif }, - { /* [1] */ + { /* [3] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x2210u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -434,7 +481,7 @@ /*func=*/ "ksmdbgssnCtrlCmdDebugGetModeMMUDebug" #endif }, - { /* [2] */ + { /* [4] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x2210u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -449,7 +496,7 @@ /*func=*/ "ksmdbgssnCtrlCmdDebugSetExceptionMask" #endif }, - { /* [3] */ + { /* [5] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x2210u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -464,7 +511,7 @@ /*func=*/ "ksmdbgssnCtrlCmdDebugReadSingleSmErrorState" #endif }, - { /* [4] */ + { /* [6] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -479,7 +526,7 @@ /*func=*/ "ksmdbgssnCtrlCmdDebugReadAllSmErrorStates" #endif }, - { /* [5] */ + { /* [7] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x2210u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -494,7 +541,7 @@ /*func=*/ "ksmdbgssnCtrlCmdDebugClearSingleSmErrorState" #endif }, - { /* [6] */ + { /* [8] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -509,7 +556,7 @@ /*func=*/ "ksmdbgssnCtrlCmdDebugClearAllSmErrorStates" #endif }, - { /* [7] */ + { /* [9] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x2210u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -524,7 +571,7 @@ /*func=*/ "ksmdbgssnCtrlCmdDebugSetNextStopTriggerType" #endif }, - { /* [8] */ + { /* [10] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x2210u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -539,7 +586,7 @@ /*func=*/ "ksmdbgssnCtrlCmdDebugSetSingleStepInterruptHandling" #endif }, - { /* [9] */ + { /* [11] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -554,7 +601,7 @@ /*func=*/ "ksmdbgssnCtrlCmdDebugReadMemory" #endif }, - { /* [10] */ + { /* [12] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -569,7 +616,7 @@ /*func=*/ "ksmdbgssnCtrlCmdDebugWriteMemory" #endif }, - { /* [11] */ + { /* [13] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x2210u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -584,7 +631,7 @@ /*func=*/ "ksmdbgssnCtrlCmdDebugSuspendContext" #endif }, - { /* [12] */ + { /* [14] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x2210u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -599,7 +646,7 @@ /*func=*/ "ksmdbgssnCtrlCmdDebugResumeContext" #endif }, - { /* [13] */ + { /* [15] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -614,7 +661,7 @@ /*func=*/ "ksmdbgssnCtrlCmdReadSurface" #endif }, - { /* [14] */ + { /* [16] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -629,7 +676,7 @@ /*func=*/ "ksmdbgssnCtrlCmdWriteSurface" #endif }, - { /* [15] */ + { /* [17] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -644,7 +691,7 @@ /*func=*/ "ksmdbgssnCtrlCmdGetMappings" #endif }, - { /* [16] */ + { /* [18] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x2010u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -659,7 +706,7 @@ /*func=*/ "ksmdbgssnCtrlCmdDebugExecRegOps" #endif }, - { /* [17] */ + { /* [19] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x2210u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -674,7 +721,7 @@ /*func=*/ "ksmdbgssnCtrlCmdDebugSetModeErrbarDebug" #endif }, - { /* [18] */ + { /* [20] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x2210u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -689,7 +736,7 @@ /*func=*/ "ksmdbgssnCtrlCmdDebugGetModeErrbarDebug" #endif }, - { /* [19] */ + { /* [21] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x2210u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -704,7 +751,7 @@ /*func=*/ "ksmdbgssnCtrlCmdDebugSetSingleSmSingleStep" #endif }, - { /* [20] */ + { /* [22] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x2210u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -719,7 +766,7 @@ /*func=*/ "ksmdbgssnCtrlCmdDebugSetSingleSmStopTrigger" #endif }, - { /* [21] */ + { /* [23] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x2210u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -734,7 +781,7 @@ /*func=*/ "ksmdbgssnCtrlCmdDebugSetSingleSmRunTrigger" #endif }, - { /* [22] */ + { /* [24] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x2210u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -749,7 +796,7 @@ /*func=*/ "ksmdbgssnCtrlCmdDebugSetSingleSmSkipIdleWarpDetect" #endif }, - { /* [23] */ + { /* [25] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x2210u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -764,7 +811,7 @@ /*func=*/ "ksmdbgssnCtrlCmdDebugGetSingleSmDebuggerStatus" #endif }, - { /* [24] */ + { /* [26] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -779,7 +826,7 @@ /*func=*/ "ksmdbgssnCtrlCmdDebugReadBatchMemory" #endif }, - { /* [25] */ + { /* [27] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -794,7 +841,7 @@ /*func=*/ "ksmdbgssnCtrlCmdDebugWriteBatchMemory" #endif }, - { /* [26] */ + { /* [28] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -814,7 +861,7 @@ const struct NVOC_EXPORT_INFO __nvoc_export_info_KernelSMDebuggerSession = { - /*numEntries=*/ 27, + /*numEntries=*/ 29, /*pExportEntries=*/ __nvoc_exported_method_def_KernelSMDebuggerSession }; @@ -862,6 +909,14 @@ pThis->__ksmdbgssnGetInternalObjectHandle__ = &ksmdbgssnGetInternalObjectHandle_IMPL; +#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x2200u) + pThis->__ksmdbgssnCtrlCmdSMDebugModeEnable__ = &ksmdbgssnCtrlCmdSMDebugModeEnable_fcf1ac; +#endif + +#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x2200u) + pThis->__ksmdbgssnCtrlCmdSMDebugModeDisable__ = &ksmdbgssnCtrlCmdSMDebugModeDisable_fcf1ac; +#endif + #if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x2210u) pThis->__ksmdbgssnCtrlCmdDebugSetModeMMUDebug__ = &ksmdbgssnCtrlCmdDebugSetModeMMUDebug_fcf1ac; #endif @@ -976,11 +1031,11 @@ pThis->__ksmdbgssnShareCallback__ = &__nvoc_thunk_GpuResource_ksmdbgssnShareCallback; - pThis->__ksmdbgssnMapTo__ = &__nvoc_thunk_RsResource_ksmdbgssnMapTo; + pThis->__ksmdbgssnCheckMemInterUnmap__ = &__nvoc_thunk_RmResource_ksmdbgssnCheckMemInterUnmap; pThis->__ksmdbgssnGetOrAllocNotifShare__ = &__nvoc_thunk_Notifier_ksmdbgssnGetOrAllocNotifShare; - pThis->__ksmdbgssnCheckMemInterUnmap__ = &__nvoc_thunk_RmResource_ksmdbgssnCheckMemInterUnmap; + pThis->__ksmdbgssnMapTo__ = &__nvoc_thunk_RsResource_ksmdbgssnMapTo; pThis->__ksmdbgssnGetMapAddrSpace__ = &__nvoc_thunk_GpuResource_ksmdbgssnGetMapAddrSpace; @@ -1012,12 +1067,16 @@ pThis->__ksmdbgssnUnregisterEvent__ = &__nvoc_thunk_Notifier_ksmdbgssnUnregisterEvent; + pThis->__ksmdbgssnControlSerialization_Prologue__ = &__nvoc_thunk_RmResource_ksmdbgssnControlSerialization_Prologue; + pThis->__ksmdbgssnCanCopy__ = &__nvoc_thunk_RsResource_ksmdbgssnCanCopy; pThis->__ksmdbgssnPreDestruct__ = &__nvoc_thunk_RsResource_ksmdbgssnPreDestruct; pThis->__ksmdbgssnIsDuplicate__ = &__nvoc_thunk_RsResource_ksmdbgssnIsDuplicate; + pThis->__ksmdbgssnControlSerialization_Epilogue__ = &__nvoc_thunk_RmResource_ksmdbgssnControlSerialization_Epilogue; + pThis->__ksmdbgssnGetNotificationListPtr__ = &__nvoc_thunk_Notifier_ksmdbgssnGetNotificationListPtr; pThis->__ksmdbgssnGetNotificationShare__ = &__nvoc_thunk_Notifier_ksmdbgssnGetNotificationShare; @@ -1052,13 +1111,16 @@ Object *pParentObj; KernelSMDebuggerSession *pThis; - pThis = portMemAllocNonPaged(sizeof(KernelSMDebuggerSession)); - if (pThis == NULL) return NV_ERR_NO_MEMORY; + status = __nvoc_handleObjCreateMemAlloc(createFlags, sizeof(KernelSMDebuggerSession), (void**)&pThis, (void**)ppThis); + if (status != NV_OK) + return status; portMemSet(pThis, 0, sizeof(KernelSMDebuggerSession)); __nvoc_initRtti(staticCast(pThis, Dynamic), &__nvoc_class_def_KernelSMDebuggerSession); + pThis->__nvoc_base_GpuResource.__nvoc_base_RmResource.__nvoc_base_RsResource.__nvoc_base_Object.createFlags = createFlags; + if (pParent != NULL && !(createFlags & NVOC_OBJ_CREATE_FLAGS_PARENT_HALSPEC_ONLY)) { pParentObj = dynamicCast(pParent, Object); @@ -1074,11 +1136,17 @@ if (status != NV_OK) goto __nvoc_objCreate_KernelSMDebuggerSession_cleanup; *ppThis = pThis; + return NV_OK; __nvoc_objCreate_KernelSMDebuggerSession_cleanup: // do not call destructors here since the constructor already called them - portMemFree(pThis); + if (createFlags & NVOC_OBJ_CREATE_FLAGS_IN_PLACE_CONSTRUCT) + portMemSet(pThis, 0, sizeof(KernelSMDebuggerSession)); + else + portMemFree(pThis); + + // coverity[leaked_storage:FALSE] return status; } diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/generated/g_kernel_sm_debugger_session_nvoc.h nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_kernel_sm_debugger_session_nvoc.h --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/generated/g_kernel_sm_debugger_session_nvoc.h 2023-10-25 20:27:11.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_kernel_sm_debugger_session_nvoc.h 2024-03-05 22:18:33.000000000 +0000 @@ -7,7 +7,7 @@ #endif /* - * SPDX-FileCopyrightText: Copyright (c) 1993-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 1993-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -158,6 +158,8 @@ struct KernelSMDebuggerSession *__nvoc_pbase_KernelSMDebuggerSession; NV_STATUS (*__ksmdbgssnInternalControlForward__)(struct KernelSMDebuggerSession *, NvU32, void *, NvU32); NvHandle (*__ksmdbgssnGetInternalObjectHandle__)(struct KernelSMDebuggerSession *); + NV_STATUS (*__ksmdbgssnCtrlCmdSMDebugModeEnable__)(struct KernelSMDebuggerSession *); + NV_STATUS (*__ksmdbgssnCtrlCmdSMDebugModeDisable__)(struct KernelSMDebuggerSession *); NV_STATUS (*__ksmdbgssnCtrlCmdDebugSetModeMMUDebug__)(struct KernelSMDebuggerSession *, NV83DE_CTRL_DEBUG_SET_MODE_MMU_DEBUG_PARAMS *); NV_STATUS (*__ksmdbgssnCtrlCmdDebugGetModeMMUDebug__)(struct KernelSMDebuggerSession *, NV83DE_CTRL_DEBUG_GET_MODE_MMU_DEBUG_PARAMS *); NV_STATUS (*__ksmdbgssnCtrlCmdDebugSetModeErrbarDebug__)(struct KernelSMDebuggerSession *, NV83DE_CTRL_DEBUG_SET_MODE_ERRBAR_DEBUG_PARAMS *); @@ -186,9 +188,9 @@ NV_STATUS (*__ksmdbgssnCtrlCmdDebugWriteBatchMemory__)(struct KernelSMDebuggerSession *, NV83DE_CTRL_DEBUG_ACCESS_MEMORY_PARAMS *); NV_STATUS (*__ksmdbgssnCtrlCmdDebugReadMMUFaultInfo__)(struct KernelSMDebuggerSession *, NV83DE_CTRL_DEBUG_READ_MMU_FAULT_INFO_PARAMS *); NvBool (*__ksmdbgssnShareCallback__)(struct KernelSMDebuggerSession *, struct RsClient *, struct RsResourceRef *, RS_SHARE_POLICY *); - NV_STATUS (*__ksmdbgssnMapTo__)(struct KernelSMDebuggerSession *, RS_RES_MAP_TO_PARAMS *); - NV_STATUS (*__ksmdbgssnGetOrAllocNotifShare__)(struct KernelSMDebuggerSession *, NvHandle, NvHandle, struct NotifShare **); NV_STATUS (*__ksmdbgssnCheckMemInterUnmap__)(struct KernelSMDebuggerSession *, NvBool); + NV_STATUS (*__ksmdbgssnGetOrAllocNotifShare__)(struct KernelSMDebuggerSession *, NvHandle, NvHandle, struct NotifShare **); + NV_STATUS (*__ksmdbgssnMapTo__)(struct KernelSMDebuggerSession *, RS_RES_MAP_TO_PARAMS *); NV_STATUS (*__ksmdbgssnGetMapAddrSpace__)(struct KernelSMDebuggerSession *, struct CALL_CONTEXT *, NvU32, NV_ADDRESS_SPACE *); void (*__ksmdbgssnSetNotificationShare__)(struct KernelSMDebuggerSession *, struct NotifShare *); NvU32 (*__ksmdbgssnGetRefCount__)(struct KernelSMDebuggerSession *); @@ -204,25 +206,27 @@ NV_STATUS (*__ksmdbgssnGetMemoryMappingDescriptor__)(struct KernelSMDebuggerSession *, struct MEMORY_DESCRIPTOR **); NV_STATUS (*__ksmdbgssnControlFilter__)(struct KernelSMDebuggerSession *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); NV_STATUS (*__ksmdbgssnUnregisterEvent__)(struct KernelSMDebuggerSession *, NvHandle, NvHandle, NvHandle, NvHandle); + NV_STATUS (*__ksmdbgssnControlSerialization_Prologue__)(struct KernelSMDebuggerSession *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); NvBool (*__ksmdbgssnCanCopy__)(struct KernelSMDebuggerSession *); void (*__ksmdbgssnPreDestruct__)(struct KernelSMDebuggerSession *); NV_STATUS (*__ksmdbgssnIsDuplicate__)(struct KernelSMDebuggerSession *, NvHandle, NvBool *); + void (*__ksmdbgssnControlSerialization_Epilogue__)(struct KernelSMDebuggerSession *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); PEVENTNOTIFICATION *(*__ksmdbgssnGetNotificationListPtr__)(struct KernelSMDebuggerSession *); struct NotifShare *(*__ksmdbgssnGetNotificationShare__)(struct KernelSMDebuggerSession *); NV_STATUS (*__ksmdbgssnMap__)(struct KernelSMDebuggerSession *, struct CALL_CONTEXT *, struct RS_CPU_MAP_PARAMS *, struct RsCpuMapping *); NvBool (*__ksmdbgssnAccessCallback__)(struct KernelSMDebuggerSession *, struct RsClient *, void *, RsAccessRight); - struct RmDebuggerSession *pDebugSession; - struct KernelGraphicsObject *pObject; - NvHandle hDebugger; - NvHandle hDebuggerClient; - NvHandle hChannel; - NvHandle hChannelClient; - NvHandle hSubdevice; - NvHandle hInternalClient; - NvHandle hInternalDevice; - NvHandle hInternalSubdevice; - NvHandle hInternalSubscription; - NvHandle hInternalMemMapping; + struct RmDebuggerSession *PRIVATE_FIELD(pDebugSession); + struct KernelGraphicsObject *PRIVATE_FIELD(pObject); + NvHandle PRIVATE_FIELD(hDebugger); + NvHandle PRIVATE_FIELD(hDebuggerClient); + NvHandle PRIVATE_FIELD(hChannel); + NvHandle PRIVATE_FIELD(hChannelClient); + NvHandle PRIVATE_FIELD(hSubdevice); + NvHandle PRIVATE_FIELD(hInternalClient); + NvHandle PRIVATE_FIELD(hInternalDevice); + NvHandle PRIVATE_FIELD(hInternalSubdevice); + NvHandle PRIVATE_FIELD(hInternalSubscription); + NvHandle PRIVATE_FIELD(hInternalMemMapping); }; #ifndef __NVOC_CLASS_KernelSMDebuggerSession_TYPEDEF__ @@ -255,6 +259,8 @@ #define ksmdbgssnInternalControlForward(arg0, command, pParams, size) ksmdbgssnInternalControlForward_DISPATCH(arg0, command, pParams, size) #define ksmdbgssnGetInternalObjectHandle(arg0) ksmdbgssnGetInternalObjectHandle_DISPATCH(arg0) +#define ksmdbgssnCtrlCmdSMDebugModeEnable(pKernelSMDebuggerSession) ksmdbgssnCtrlCmdSMDebugModeEnable_DISPATCH(pKernelSMDebuggerSession) +#define ksmdbgssnCtrlCmdSMDebugModeDisable(pKernelSMDebuggerSession) ksmdbgssnCtrlCmdSMDebugModeDisable_DISPATCH(pKernelSMDebuggerSession) #define ksmdbgssnCtrlCmdDebugSetModeMMUDebug(pKernelSMDebuggerSession, pParams) ksmdbgssnCtrlCmdDebugSetModeMMUDebug_DISPATCH(pKernelSMDebuggerSession, pParams) #define ksmdbgssnCtrlCmdDebugGetModeMMUDebug(pKernelSMDebuggerSession, pParams) ksmdbgssnCtrlCmdDebugGetModeMMUDebug_DISPATCH(pKernelSMDebuggerSession, pParams) #define ksmdbgssnCtrlCmdDebugSetModeErrbarDebug(pKernelSMDebuggerSession, pParams) ksmdbgssnCtrlCmdDebugSetModeErrbarDebug_DISPATCH(pKernelSMDebuggerSession, pParams) @@ -283,9 +289,9 @@ #define ksmdbgssnCtrlCmdDebugWriteBatchMemory(arg0, arg1) ksmdbgssnCtrlCmdDebugWriteBatchMemory_DISPATCH(arg0, arg1) #define ksmdbgssnCtrlCmdDebugReadMMUFaultInfo(arg0, arg1) ksmdbgssnCtrlCmdDebugReadMMUFaultInfo_DISPATCH(arg0, arg1) #define ksmdbgssnShareCallback(pGpuResource, pInvokingClient, pParentRef, pSharePolicy) ksmdbgssnShareCallback_DISPATCH(pGpuResource, pInvokingClient, pParentRef, pSharePolicy) -#define ksmdbgssnMapTo(pResource, pParams) ksmdbgssnMapTo_DISPATCH(pResource, pParams) -#define ksmdbgssnGetOrAllocNotifShare(pNotifier, hNotifierClient, hNotifierResource, ppNotifShare) ksmdbgssnGetOrAllocNotifShare_DISPATCH(pNotifier, hNotifierClient, hNotifierResource, ppNotifShare) #define ksmdbgssnCheckMemInterUnmap(pRmResource, bSubdeviceHandleProvided) ksmdbgssnCheckMemInterUnmap_DISPATCH(pRmResource, bSubdeviceHandleProvided) +#define ksmdbgssnGetOrAllocNotifShare(pNotifier, hNotifierClient, hNotifierResource, ppNotifShare) ksmdbgssnGetOrAllocNotifShare_DISPATCH(pNotifier, hNotifierClient, hNotifierResource, ppNotifShare) +#define ksmdbgssnMapTo(pResource, pParams) ksmdbgssnMapTo_DISPATCH(pResource, pParams) #define ksmdbgssnGetMapAddrSpace(pGpuResource, pCallContext, mapFlags, pAddrSpace) ksmdbgssnGetMapAddrSpace_DISPATCH(pGpuResource, pCallContext, mapFlags, pAddrSpace) #define ksmdbgssnSetNotificationShare(pNotifier, pNotifShare) ksmdbgssnSetNotificationShare_DISPATCH(pNotifier, pNotifShare) #define ksmdbgssnGetRefCount(pResource) ksmdbgssnGetRefCount_DISPATCH(pResource) @@ -301,9 +307,11 @@ #define ksmdbgssnGetMemoryMappingDescriptor(pRmResource, ppMemDesc) ksmdbgssnGetMemoryMappingDescriptor_DISPATCH(pRmResource, ppMemDesc) #define ksmdbgssnControlFilter(pResource, pCallContext, pParams) ksmdbgssnControlFilter_DISPATCH(pResource, pCallContext, pParams) #define ksmdbgssnUnregisterEvent(pNotifier, hNotifierClient, hNotifierResource, hEventClient, hEvent) ksmdbgssnUnregisterEvent_DISPATCH(pNotifier, hNotifierClient, hNotifierResource, hEventClient, hEvent) +#define ksmdbgssnControlSerialization_Prologue(pResource, pCallContext, pParams) ksmdbgssnControlSerialization_Prologue_DISPATCH(pResource, pCallContext, pParams) #define ksmdbgssnCanCopy(pResource) ksmdbgssnCanCopy_DISPATCH(pResource) #define ksmdbgssnPreDestruct(pResource) ksmdbgssnPreDestruct_DISPATCH(pResource) #define ksmdbgssnIsDuplicate(pResource, hMemory, pDuplicate) ksmdbgssnIsDuplicate_DISPATCH(pResource, hMemory, pDuplicate) +#define ksmdbgssnControlSerialization_Epilogue(pResource, pCallContext, pParams) ksmdbgssnControlSerialization_Epilogue_DISPATCH(pResource, pCallContext, pParams) #define ksmdbgssnGetNotificationListPtr(pNotifier) ksmdbgssnGetNotificationListPtr_DISPATCH(pNotifier) #define ksmdbgssnGetNotificationShare(pNotifier) ksmdbgssnGetNotificationShare_DISPATCH(pNotifier) #define ksmdbgssnMap(pGpuResource, pCallContext, pParams, pCpuMapping) ksmdbgssnMap_DISPATCH(pGpuResource, pCallContext, pParams, pCpuMapping) @@ -320,6 +328,22 @@ return arg0->__ksmdbgssnGetInternalObjectHandle__(arg0); } +static inline NV_STATUS ksmdbgssnCtrlCmdSMDebugModeEnable_fcf1ac(struct KernelSMDebuggerSession *pKernelSMDebuggerSession) { + return ksmdbgssnInternalControlForward(pKernelSMDebuggerSession, (2212365313U), ((void *)0), 0); +} + +static inline NV_STATUS ksmdbgssnCtrlCmdSMDebugModeEnable_DISPATCH(struct KernelSMDebuggerSession *pKernelSMDebuggerSession) { + return pKernelSMDebuggerSession->__ksmdbgssnCtrlCmdSMDebugModeEnable__(pKernelSMDebuggerSession); +} + +static inline NV_STATUS ksmdbgssnCtrlCmdSMDebugModeDisable_fcf1ac(struct KernelSMDebuggerSession *pKernelSMDebuggerSession) { + return ksmdbgssnInternalControlForward(pKernelSMDebuggerSession, (2212365314U), ((void *)0), 0); +} + +static inline NV_STATUS ksmdbgssnCtrlCmdSMDebugModeDisable_DISPATCH(struct KernelSMDebuggerSession *pKernelSMDebuggerSession) { + return pKernelSMDebuggerSession->__ksmdbgssnCtrlCmdSMDebugModeDisable__(pKernelSMDebuggerSession); +} + static inline NV_STATUS ksmdbgssnCtrlCmdDebugSetModeMMUDebug_fcf1ac(struct KernelSMDebuggerSession *pKernelSMDebuggerSession, NV83DE_CTRL_DEBUG_SET_MODE_MMU_DEBUG_PARAMS *pParams) { return ksmdbgssnInternalControlForward(pKernelSMDebuggerSession, (2212365315U), pParams, sizeof (*pParams)); } @@ -518,16 +542,16 @@ return pGpuResource->__ksmdbgssnShareCallback__(pGpuResource, pInvokingClient, pParentRef, pSharePolicy); } -static inline NV_STATUS ksmdbgssnMapTo_DISPATCH(struct KernelSMDebuggerSession *pResource, RS_RES_MAP_TO_PARAMS *pParams) { - return pResource->__ksmdbgssnMapTo__(pResource, pParams); +static inline NV_STATUS ksmdbgssnCheckMemInterUnmap_DISPATCH(struct KernelSMDebuggerSession *pRmResource, NvBool bSubdeviceHandleProvided) { + return pRmResource->__ksmdbgssnCheckMemInterUnmap__(pRmResource, bSubdeviceHandleProvided); } static inline NV_STATUS ksmdbgssnGetOrAllocNotifShare_DISPATCH(struct KernelSMDebuggerSession *pNotifier, NvHandle hNotifierClient, NvHandle hNotifierResource, struct NotifShare **ppNotifShare) { return pNotifier->__ksmdbgssnGetOrAllocNotifShare__(pNotifier, hNotifierClient, hNotifierResource, ppNotifShare); } -static inline NV_STATUS ksmdbgssnCheckMemInterUnmap_DISPATCH(struct KernelSMDebuggerSession *pRmResource, NvBool bSubdeviceHandleProvided) { - return pRmResource->__ksmdbgssnCheckMemInterUnmap__(pRmResource, bSubdeviceHandleProvided); +static inline NV_STATUS ksmdbgssnMapTo_DISPATCH(struct KernelSMDebuggerSession *pResource, RS_RES_MAP_TO_PARAMS *pParams) { + return pResource->__ksmdbgssnMapTo__(pResource, pParams); } static inline NV_STATUS ksmdbgssnGetMapAddrSpace_DISPATCH(struct KernelSMDebuggerSession *pGpuResource, struct CALL_CONTEXT *pCallContext, NvU32 mapFlags, NV_ADDRESS_SPACE *pAddrSpace) { @@ -590,6 +614,10 @@ return pNotifier->__ksmdbgssnUnregisterEvent__(pNotifier, hNotifierClient, hNotifierResource, hEventClient, hEvent); } +static inline NV_STATUS ksmdbgssnControlSerialization_Prologue_DISPATCH(struct KernelSMDebuggerSession *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return pResource->__ksmdbgssnControlSerialization_Prologue__(pResource, pCallContext, pParams); +} + static inline NvBool ksmdbgssnCanCopy_DISPATCH(struct KernelSMDebuggerSession *pResource) { return pResource->__ksmdbgssnCanCopy__(pResource); } @@ -602,6 +630,10 @@ return pResource->__ksmdbgssnIsDuplicate__(pResource, hMemory, pDuplicate); } +static inline void ksmdbgssnControlSerialization_Epilogue_DISPATCH(struct KernelSMDebuggerSession *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + pResource->__ksmdbgssnControlSerialization_Epilogue__(pResource, pCallContext, pParams); +} + static inline PEVENTNOTIFICATION *ksmdbgssnGetNotificationListPtr_DISPATCH(struct KernelSMDebuggerSession *pNotifier) { return pNotifier->__ksmdbgssnGetNotificationListPtr__(pNotifier); } diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/generated/g_kernel_vgpu_mgr_nvoc.c nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_kernel_vgpu_mgr_nvoc.c --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/generated/g_kernel_vgpu_mgr_nvoc.c 2023-10-25 20:27:11.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_kernel_vgpu_mgr_nvoc.c 2024-03-05 22:18:33.000000000 +0000 @@ -114,13 +114,16 @@ Object *pParentObj; KernelVgpuMgr *pThis; - pThis = portMemAllocNonPaged(sizeof(KernelVgpuMgr)); - if (pThis == NULL) return NV_ERR_NO_MEMORY; + status = __nvoc_handleObjCreateMemAlloc(createFlags, sizeof(KernelVgpuMgr), (void**)&pThis, (void**)ppThis); + if (status != NV_OK) + return status; portMemSet(pThis, 0, sizeof(KernelVgpuMgr)); __nvoc_initRtti(staticCast(pThis, Dynamic), &__nvoc_class_def_KernelVgpuMgr); + pThis->__nvoc_base_Object.createFlags = createFlags; + if (pParent != NULL && !(createFlags & NVOC_OBJ_CREATE_FLAGS_PARENT_HALSPEC_ONLY)) { pParentObj = dynamicCast(pParent, Object); @@ -136,11 +139,17 @@ if (status != NV_OK) goto __nvoc_objCreate_KernelVgpuMgr_cleanup; *ppThis = pThis; + return NV_OK; __nvoc_objCreate_KernelVgpuMgr_cleanup: // do not call destructors here since the constructor already called them - portMemFree(pThis); + if (createFlags & NVOC_OBJ_CREATE_FLAGS_IN_PLACE_CONSTRUCT) + portMemSet(pThis, 0, sizeof(KernelVgpuMgr)); + else + portMemFree(pThis); + + // coverity[leaked_storage:FALSE] return status; } diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/generated/g_kernel_vgpu_mgr_nvoc.h nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_kernel_vgpu_mgr_nvoc.h --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/generated/g_kernel_vgpu_mgr_nvoc.h 2023-10-25 20:27:11.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_kernel_vgpu_mgr_nvoc.h 2024-03-05 22:18:33.000000000 +0000 @@ -7,7 +7,7 @@ #endif /* - * SPDX-FileCopyrightText: Copyright (c) 2017-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2017-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -37,6 +37,7 @@ #include "ctrl/ctrl2080/ctrl2080vgpumgrinternal.h" #include "ctrl/ctrla081.h" #include "ctrl/ctrla084.h" +#include "ctrl/ctrlc637.h" #include "gpu/gpu.h" #include "nv-hypervisor.h" @@ -71,6 +72,7 @@ #endif /* __nvoc_class_id_VgpuConfigApi */ +typedef struct KERNEL_MIG_GPU_INSTANCE KERNEL_MIG_GPU_INSTANCE; /* vGPU events info lookup node*/ typedef struct VGPU_EVENT_INFO_NODE @@ -112,20 +114,23 @@ NvU32 swizzId; NvU32 numPluginChannels; NvU32 chidOffset[RM_ENGINE_TYPE_LAST]; + NvU32 channelCount[RM_ENGINE_TYPE_LAST]; /*Number of channels available to the VF*/ NvU8 vgpuUuid[RM_SHA1_GID_SIZE]; void *pVgpuVfioRef; struct REQUEST_VGPU_INFO_NODE *pRequestVgpuInfoNode; struct PhysMemSubAlloc *pPhysMemSubAlloc; - NvU32 gpuInstance; struct HOST_VGPU_DEVICE *pHostVgpuDevice; // Legacy fields NvHandle hPluginFBAllocationClient; VGPU_DEVICE_GUEST_FB_INFO vgpuDeviceGuestFbInfo; NvU32 *pGuestFbSegment; - NvU32 guestFbSegmentPageSize; + NvU64 guestFbSegmentPageSize; NvBool bOfflinedPageInfoValid; NvU32 offlinedPageCount; /* offlined page count */ NvU64 offlinedPageGpa[NV2080_CTRL_FB_OFFLINED_PAGES_MAX_PAGES]; + MEMORY_DESCRIPTOR *pGspPluginHeapMemDesc; + NvBool bDisableDefaultSmcExecPartRestore; + struct GPUMGR_SAVE_COMPUTE_INSTANCE savedExecPartitions[NVC637_CTRL_MAX_EXEC_PARTITIONS]; } KERNEL_HOST_VGPU_DEVICE; MAKE_LIST(KERNEL_HOST_VGPU_DEVICE_LIST, KERNEL_HOST_VGPU_DEVICE); @@ -204,7 +209,6 @@ NvU32 user_max_supported_version; struct OBJEHEAP *pHeap; REQUEST_VGPU_INFO_NODE_LIST listRequestVgpuHead; - MEMORY_DESCRIPTOR *pGspPluginHeapMemDesc; }; #ifndef __NVOC_CLASS_KernelVgpuMgr_TYPEDEF__ @@ -265,10 +269,6 @@ kvgpumgrDetachGpu(NvU32 gpuPciId); NV_STATUS -kvgpumgrRegisterGuestId(NVA084_CTRL_KERNEL_HOST_VGPU_DEVICE_SET_GUEST_ID_PARAMS *pParams, - KERNEL_HOST_VGPU_DEVICE *pKernelHostVgpuDevice, struct OBJGPU *pGpu); - -NV_STATUS kvgpumgrGuestRegister(struct OBJGPU *pGpu, NvU32 gfid, NvU32 vgpuType, @@ -305,6 +305,11 @@ NvU32 *swizzId); NV_STATUS +kvgpumgrValidateSwizzId(struct OBJGPU *pGpu, + NvU32 vgpuTypeId, + NvU32 swizzId); + +NV_STATUS kvgpumgrGetVgpuFbUsage(struct OBJGPU *pGpu, NVA081_CTRL_VGPU_CONFIG_GET_VGPU_FB_USAGE_PARAMS *pParams); NV_STATUS @@ -368,6 +373,13 @@ NvBool kvgpumgrIsHeterogeneousVgpuSupported(void); +NV_STATUS +kvgpumgrGetHostVgpuDeviceFromGfid(NvU32 gpuPciId, NvU32 gfid, + KERNEL_HOST_VGPU_DEVICE** ppHostVgpuDevice); +NV_STATUS +kvgpuMgrRestoreSmcExecPart(struct OBJGPU *pGpu,KERNEL_HOST_VGPU_DEVICE *pKernelHostVgpuDevice, + KERNEL_MIG_GPU_INSTANCE *pKernelMIGGpuInstance); + #endif // __kernel_vgpu_mgr_h__ #ifdef __cplusplus diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/generated/g_mem_desc_nvoc.h nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_mem_desc_nvoc.h --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/generated/g_mem_desc_nvoc.h 2023-10-25 20:27:11.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_mem_desc_nvoc.h 2024-03-05 22:18:33.000000000 +0000 @@ -7,7 +7,7 @@ #endif /* - * SPDX-FileCopyrightText: Copyright (c) 1993-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 1993-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -89,6 +89,7 @@ #define ADDR_REGMEM 3 // NV register memory space #define ADDR_VIRTUAL 4 // Virtual address space only #define ADDR_FABRIC_V2 6 // Fabric address space for the FLA based addressing. Will replace ADDR_FABRIC. +#define ADDR_EGM 7 // Extended GPU Memory (EGM) #define ADDR_FABRIC_MC 8 // Multicast fabric address space (MCFLA) // @@ -215,7 +216,7 @@ NvU64 _flags; // Size of mapping used for this allocation. Multiple mappings on Fermi must always use the same page size. - NvU32 _pageSize; + NvU64 _pageSize; // Size of the memory allocation in pages NvU64 PageCount; @@ -500,7 +501,7 @@ // Fill in a MEMORY_DESCRIPTOR with the physical page addresses returned by PMA. // It should already be initialized with memdescCreate*(). void memdescFillPages(MEMORY_DESCRIPTOR *pMemDesc, NvU32 offset, - NvU64 *pPages, NvU32 pageCount, NvU32 pageSize); + NvU64 *pPages, NvU32 pageCount, NvU64 pageSize); // Create a MEMORY_DESCRIPTOR for a subset of an existing memory allocation. // The new MEMORY_DESCRIPTOR must be freed with memdescDestroy. @@ -577,7 +578,7 @@ void memdescPrintMemdesc(MEMORY_DESCRIPTOR *pMemDesc, NvBool bPrintIndividualPages, const char *pPrefixMessage); // Get the page offset for an arbitrary power of two page size -NvU64 memdescGetPageOffset(MEMORY_DESCRIPTOR *pMemDesc, NvU32 pageSize); +NvU64 memdescGetPageOffset(MEMORY_DESCRIPTOR *pMemDesc, NvU64 pageSize); // // Internal APIs for the IOVASPACE to manage IOMMU mappings in a memdesc. @@ -647,11 +648,12 @@ void memdescSetContiguity(PMEMORY_DESCRIPTOR pMemDesc, ADDRESS_TRANSLATION addressTranslation, NvBool isContiguous); NvBool memdescCheckContiguity(PMEMORY_DESCRIPTOR pMemDesc, ADDRESS_TRANSLATION addressTranslation); NV_ADDRESS_SPACE memdescGetAddressSpace(PMEMORY_DESCRIPTOR pMemDesc); -NvU32 memdescGetPageSize(MEMORY_DESCRIPTOR *pMemDesc, ADDRESS_TRANSLATION addressTranslation); -void memdescSetPageSize(MEMORY_DESCRIPTOR *pMemDesc, ADDRESS_TRANSLATION addressTranslation, NvU32 pageSize); +NvU64 memdescGetPageSize(MEMORY_DESCRIPTOR *pMemDesc, ADDRESS_TRANSLATION addressTranslation); +void memdescSetPageSize(MEMORY_DESCRIPTOR *pMemDesc, ADDRESS_TRANSLATION addressTranslation, NvU64 pageSize); PMEMORY_DESCRIPTOR memdescGetRootMemDesc(PMEMORY_DESCRIPTOR pMemDesc, NvU64 *pRootOffset); void memdescSetCustomHeap(PMEMORY_DESCRIPTOR); NvBool memdescGetCustomHeap(PMEMORY_DESCRIPTOR); +NV_STATUS memdescSetPageArrayGranularity(MEMORY_DESCRIPTOR *pMemDesc, NvU64 pageArrayGranularity); NvBool memdescAcquireRmExclusiveUse(MEMORY_DESCRIPTOR *pMemDesc); @@ -946,7 +948,7 @@ /*! * @brief Set the name of the surface. - * + * * @param[in] pGpu OBJGPU pointer. * @param[in] pMemDesc MEMORY_DESCRIPTOR pointer that the name is to be set for. * @param[in] name const char pointer to the name to be set. @@ -1122,6 +1124,11 @@ // against RM internal sysmem allocation // #define MEMDESC_FLAGS_SYSMEM_OWNED_BY_CLIENT NVBIT64(44) +// +// Clients (including RM) should set this flag to request allocations in +// unprotected memory. This is required for Confidential Compute cases +// +#define MEMDESC_FLAGS_ALLOC_IN_UNPROTECTED_MEMORY NVBIT64(45) // // The following is a special use case for sharing memory between @@ -1140,7 +1147,7 @@ // // Specical case to allocate the runlists for Guests from its GPA // In MODS, VM's GPA allocated from subheap so using this define to -// Forcing memdesc to allocated from subheap +// Forcing memdesc to allocated from subheap // #define MEMDESC_FLAGS_FORCE_ALLOC_FROM_SUBHEAP NVBIT64(48) diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/generated/g_mem_fabric_nvoc.c nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_mem_fabric_nvoc.c --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/generated/g_mem_fabric_nvoc.c 2023-10-25 20:27:12.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_mem_fabric_nvoc.c 2024-03-05 22:18:33.000000000 +0000 @@ -105,40 +105,24 @@ return memCheckMemInterUnmap((struct Memory *)(((unsigned char *)pMemory) + __nvoc_rtti_MemoryFabric_Memory.offset), bSubdeviceHandleProvided); } -static NV_STATUS __nvoc_thunk_Memory_memoryfabricUnmap(struct MemoryFabric *pMemory, CALL_CONTEXT *pCallContext, RsCpuMapping *pCpuMapping) { - return memUnmap((struct Memory *)(((unsigned char *)pMemory) + __nvoc_rtti_MemoryFabric_Memory.offset), pCallContext, pCpuMapping); -} - -static NV_STATUS __nvoc_thunk_Memory_memoryfabricGetMemInterMapParams(struct MemoryFabric *pMemory, RMRES_MEM_INTER_MAP_PARAMS *pParams) { - return memGetMemInterMapParams((struct Memory *)(((unsigned char *)pMemory) + __nvoc_rtti_MemoryFabric_Memory.offset), pParams); -} - -static NV_STATUS __nvoc_thunk_Memory_memoryfabricGetMemoryMappingDescriptor(struct MemoryFabric *pMemory, MEMORY_DESCRIPTOR **ppMemDesc) { - return memGetMemoryMappingDescriptor((struct Memory *)(((unsigned char *)pMemory) + __nvoc_rtti_MemoryFabric_Memory.offset), ppMemDesc); -} - -static NV_STATUS __nvoc_thunk_Memory_memoryfabricGetMapAddrSpace(struct MemoryFabric *pMemory, CALL_CONTEXT *pCallContext, NvU32 mapFlags, NV_ADDRESS_SPACE *pAddrSpace) { - return memGetMapAddrSpace((struct Memory *)(((unsigned char *)pMemory) + __nvoc_rtti_MemoryFabric_Memory.offset), pCallContext, mapFlags, pAddrSpace); -} - static NvBool __nvoc_thunk_RmResource_memoryfabricShareCallback(struct MemoryFabric *pResource, struct RsClient *pInvokingClient, struct RsResourceRef *pParentRef, RS_SHARE_POLICY *pSharePolicy) { return rmresShareCallback((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_MemoryFabric_RmResource.offset), pInvokingClient, pParentRef, pSharePolicy); } -static NV_STATUS __nvoc_thunk_RsResource_memoryfabricControlFilter(struct MemoryFabric *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { - return resControlFilter((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_MemoryFabric_RsResource.offset), pCallContext, pParams); +static NV_STATUS __nvoc_thunk_RsResource_memoryfabricMapTo(struct MemoryFabric *pResource, RS_RES_MAP_TO_PARAMS *pParams) { + return resMapTo((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_MemoryFabric_RsResource.offset), pParams); } -static void __nvoc_thunk_RsResource_memoryfabricAddAdditionalDependants(struct RsClient *pClient, struct MemoryFabric *pResource, RsResourceRef *pReference) { - resAddAdditionalDependants(pClient, (struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_MemoryFabric_RsResource.offset), pReference); +static NV_STATUS __nvoc_thunk_Memory_memoryfabricGetMapAddrSpace(struct MemoryFabric *pMemory, CALL_CONTEXT *pCallContext, NvU32 mapFlags, NV_ADDRESS_SPACE *pAddrSpace) { + return memGetMapAddrSpace((struct Memory *)(((unsigned char *)pMemory) + __nvoc_rtti_MemoryFabric_Memory.offset), pCallContext, mapFlags, pAddrSpace); } static NvU32 __nvoc_thunk_RsResource_memoryfabricGetRefCount(struct MemoryFabric *pResource) { return resGetRefCount((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_MemoryFabric_RsResource.offset)); } -static NV_STATUS __nvoc_thunk_RsResource_memoryfabricMapTo(struct MemoryFabric *pResource, RS_RES_MAP_TO_PARAMS *pParams) { - return resMapTo((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_MemoryFabric_RsResource.offset), pParams); +static void __nvoc_thunk_RsResource_memoryfabricAddAdditionalDependants(struct RsClient *pClient, struct MemoryFabric *pResource, RsResourceRef *pReference) { + resAddAdditionalDependants(pClient, (struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_MemoryFabric_RsResource.offset), pReference); } static NV_STATUS __nvoc_thunk_RmResource_memoryfabricControl_Prologue(struct MemoryFabric *pResource, CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { @@ -149,12 +133,44 @@ return memIsGpuMapAllowed((struct Memory *)(((unsigned char *)pMemory) + __nvoc_rtti_MemoryFabric_Memory.offset), pGpu); } +static NV_STATUS __nvoc_thunk_RsResource_memoryfabricUnmapFrom(struct MemoryFabric *pResource, RS_RES_UNMAP_FROM_PARAMS *pParams) { + return resUnmapFrom((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_MemoryFabric_RsResource.offset), pParams); +} + +static void __nvoc_thunk_RmResource_memoryfabricControl_Epilogue(struct MemoryFabric *pResource, CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + rmresControl_Epilogue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_MemoryFabric_RmResource.offset), pCallContext, pParams); +} + +static NV_STATUS __nvoc_thunk_RsResource_memoryfabricControlLookup(struct MemoryFabric *pResource, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams, const struct NVOC_EXPORTED_METHOD_DEF **ppEntry) { + return resControlLookup((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_MemoryFabric_RsResource.offset), pParams, ppEntry); +} + +static NV_STATUS __nvoc_thunk_Memory_memoryfabricUnmap(struct MemoryFabric *pMemory, CALL_CONTEXT *pCallContext, RsCpuMapping *pCpuMapping) { + return memUnmap((struct Memory *)(((unsigned char *)pMemory) + __nvoc_rtti_MemoryFabric_Memory.offset), pCallContext, pCpuMapping); +} + +static NV_STATUS __nvoc_thunk_Memory_memoryfabricGetMemInterMapParams(struct MemoryFabric *pMemory, RMRES_MEM_INTER_MAP_PARAMS *pParams) { + return memGetMemInterMapParams((struct Memory *)(((unsigned char *)pMemory) + __nvoc_rtti_MemoryFabric_Memory.offset), pParams); +} + +static NV_STATUS __nvoc_thunk_Memory_memoryfabricGetMemoryMappingDescriptor(struct MemoryFabric *pMemory, MEMORY_DESCRIPTOR **ppMemDesc) { + return memGetMemoryMappingDescriptor((struct Memory *)(((unsigned char *)pMemory) + __nvoc_rtti_MemoryFabric_Memory.offset), ppMemDesc); +} + +static NV_STATUS __nvoc_thunk_RsResource_memoryfabricControlFilter(struct MemoryFabric *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return resControlFilter((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_MemoryFabric_RsResource.offset), pCallContext, pParams); +} + +static NV_STATUS __nvoc_thunk_RmResource_memoryfabricControlSerialization_Prologue(struct MemoryFabric *pResource, CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return rmresControlSerialization_Prologue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_MemoryFabric_RmResource.offset), pCallContext, pParams); +} + static NV_STATUS __nvoc_thunk_Memory_memoryfabricIsReady(struct MemoryFabric *pMemory, NvBool bCopyConstructorContext) { return memIsReady((struct Memory *)(((unsigned char *)pMemory) + __nvoc_rtti_MemoryFabric_Memory.offset), bCopyConstructorContext); } -static NV_STATUS __nvoc_thunk_Memory_memoryfabricCheckCopyPermissions(struct MemoryFabric *pMemory, struct OBJGPU *pDstGpu, NvHandle hDstClientNvBool) { - return memCheckCopyPermissions((struct Memory *)(((unsigned char *)pMemory) + __nvoc_rtti_MemoryFabric_Memory.offset), pDstGpu, hDstClientNvBool); +static NV_STATUS __nvoc_thunk_Memory_memoryfabricCheckCopyPermissions(struct MemoryFabric *pMemory, struct OBJGPU *pDstGpu, struct Device *pDstDevice) { + return memCheckCopyPermissions((struct Memory *)(((unsigned char *)pMemory) + __nvoc_rtti_MemoryFabric_Memory.offset), pDstGpu, pDstDevice); } static void __nvoc_thunk_RsResource_memoryfabricPreDestruct(struct MemoryFabric *pResource) { @@ -165,16 +181,8 @@ return memIsDuplicate((struct Memory *)(((unsigned char *)pMemory) + __nvoc_rtti_MemoryFabric_Memory.offset), hMemory, pDuplicate); } -static NV_STATUS __nvoc_thunk_RsResource_memoryfabricUnmapFrom(struct MemoryFabric *pResource, RS_RES_UNMAP_FROM_PARAMS *pParams) { - return resUnmapFrom((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_MemoryFabric_RsResource.offset), pParams); -} - -static void __nvoc_thunk_RmResource_memoryfabricControl_Epilogue(struct MemoryFabric *pResource, CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { - rmresControl_Epilogue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_MemoryFabric_RmResource.offset), pCallContext, pParams); -} - -static NV_STATUS __nvoc_thunk_RsResource_memoryfabricControlLookup(struct MemoryFabric *pResource, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams, const struct NVOC_EXPORTED_METHOD_DEF **ppEntry) { - return resControlLookup((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_MemoryFabric_RsResource.offset), pParams, ppEntry); +static void __nvoc_thunk_RmResource_memoryfabricControlSerialization_Epilogue(struct MemoryFabric *pResource, CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + rmresControlSerialization_Epilogue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_MemoryFabric_RmResource.offset), pCallContext, pParams); } static NV_STATUS __nvoc_thunk_Memory_memoryfabricMap(struct MemoryFabric *pMemory, CALL_CONTEXT *pCallContext, struct RS_CPU_MAP_PARAMS *pParams, RsCpuMapping *pCpuMapping) { @@ -251,12 +259,57 @@ /*func=*/ "memoryfabricCtrlDetachMem" #endif }, + { /* [4] */ +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x850u) + /*pFunc=*/ (void (*)(void)) NULL, +#else + /*pFunc=*/ (void (*)(void)) memoryfabricCtrlGetNumAttachedMem_IMPL, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x850u) + /*flags=*/ 0x850u, + /*accessRight=*/0x0u, + /*methodId=*/ 0xf80105u, + /*paramSize=*/ sizeof(NV00F8_CTRL_GET_NUM_ATTACHED_MEM_PARAMS), + /*pClassInfo=*/ &(__nvoc_class_def_MemoryFabric.classInfo), +#if NV_PRINTF_STRINGS_ALLOWED + /*func=*/ "memoryfabricCtrlGetNumAttachedMem" +#endif + }, + { /* [5] */ +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x810u) + /*pFunc=*/ (void (*)(void)) NULL, +#else + /*pFunc=*/ (void (*)(void)) memoryfabricCtrlGetAttachedMem_IMPL, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x810u) + /*flags=*/ 0x810u, + /*accessRight=*/0x0u, + /*methodId=*/ 0xf80106u, + /*paramSize=*/ sizeof(NV00F8_CTRL_GET_ATTACHED_MEM_PARAMS), + /*pClassInfo=*/ &(__nvoc_class_def_MemoryFabric.classInfo), +#if NV_PRINTF_STRINGS_ALLOWED + /*func=*/ "memoryfabricCtrlGetAttachedMem" +#endif + }, + { /* [6] */ +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x840u) + /*pFunc=*/ (void (*)(void)) NULL, +#else + /*pFunc=*/ (void (*)(void)) memoryfabricCtrlGetPageLevelInfo_IMPL, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x840u) + /*flags=*/ 0x840u, + /*accessRight=*/0x0u, + /*methodId=*/ 0xf80107u, + /*paramSize=*/ sizeof(NV00F8_CTRL_GET_PAGE_LEVEL_INFO_PARAMS), + /*pClassInfo=*/ &(__nvoc_class_def_MemoryFabric.classInfo), +#if NV_PRINTF_STRINGS_ALLOWED + /*func=*/ "memoryfabricCtrlGetPageLevelInfo" +#endif + }, }; const struct NVOC_EXPORT_INFO __nvoc_export_info_MemoryFabric = { - /*numEntries=*/ 4, + /*numEntries=*/ 7, /*pExportEntries=*/ __nvoc_exported_method_def_MemoryFabric }; @@ -315,34 +368,54 @@ pThis->__memoryfabricCtrlDetachMem__ = &memoryfabricCtrlDetachMem_IMPL; #endif - pThis->__nvoc_base_Memory.__nvoc_base_RmResource.__nvoc_base_RsResource.__resCanCopy__ = &__nvoc_thunk_MemoryFabric_resCanCopy; - - pThis->__nvoc_base_Memory.__memControl__ = &__nvoc_thunk_MemoryFabric_memControl; +#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x850u) + pThis->__memoryfabricCtrlGetNumAttachedMem__ = &memoryfabricCtrlGetNumAttachedMem_IMPL; +#endif - pThis->__memoryfabricCheckMemInterUnmap__ = &__nvoc_thunk_Memory_memoryfabricCheckMemInterUnmap; +#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x810u) + pThis->__memoryfabricCtrlGetAttachedMem__ = &memoryfabricCtrlGetAttachedMem_IMPL; +#endif - pThis->__memoryfabricUnmap__ = &__nvoc_thunk_Memory_memoryfabricUnmap; +#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x840u) + pThis->__memoryfabricCtrlGetPageLevelInfo__ = &memoryfabricCtrlGetPageLevelInfo_IMPL; +#endif - pThis->__memoryfabricGetMemInterMapParams__ = &__nvoc_thunk_Memory_memoryfabricGetMemInterMapParams; + pThis->__nvoc_base_Memory.__nvoc_base_RmResource.__nvoc_base_RsResource.__resCanCopy__ = &__nvoc_thunk_MemoryFabric_resCanCopy; - pThis->__memoryfabricGetMemoryMappingDescriptor__ = &__nvoc_thunk_Memory_memoryfabricGetMemoryMappingDescriptor; + pThis->__nvoc_base_Memory.__memControl__ = &__nvoc_thunk_MemoryFabric_memControl; - pThis->__memoryfabricGetMapAddrSpace__ = &__nvoc_thunk_Memory_memoryfabricGetMapAddrSpace; + pThis->__memoryfabricCheckMemInterUnmap__ = &__nvoc_thunk_Memory_memoryfabricCheckMemInterUnmap; pThis->__memoryfabricShareCallback__ = &__nvoc_thunk_RmResource_memoryfabricShareCallback; - pThis->__memoryfabricControlFilter__ = &__nvoc_thunk_RsResource_memoryfabricControlFilter; + pThis->__memoryfabricMapTo__ = &__nvoc_thunk_RsResource_memoryfabricMapTo; - pThis->__memoryfabricAddAdditionalDependants__ = &__nvoc_thunk_RsResource_memoryfabricAddAdditionalDependants; + pThis->__memoryfabricGetMapAddrSpace__ = &__nvoc_thunk_Memory_memoryfabricGetMapAddrSpace; pThis->__memoryfabricGetRefCount__ = &__nvoc_thunk_RsResource_memoryfabricGetRefCount; - pThis->__memoryfabricMapTo__ = &__nvoc_thunk_RsResource_memoryfabricMapTo; + pThis->__memoryfabricAddAdditionalDependants__ = &__nvoc_thunk_RsResource_memoryfabricAddAdditionalDependants; pThis->__memoryfabricControl_Prologue__ = &__nvoc_thunk_RmResource_memoryfabricControl_Prologue; pThis->__memoryfabricIsGpuMapAllowed__ = &__nvoc_thunk_Memory_memoryfabricIsGpuMapAllowed; + pThis->__memoryfabricUnmapFrom__ = &__nvoc_thunk_RsResource_memoryfabricUnmapFrom; + + pThis->__memoryfabricControl_Epilogue__ = &__nvoc_thunk_RmResource_memoryfabricControl_Epilogue; + + pThis->__memoryfabricControlLookup__ = &__nvoc_thunk_RsResource_memoryfabricControlLookup; + + pThis->__memoryfabricUnmap__ = &__nvoc_thunk_Memory_memoryfabricUnmap; + + pThis->__memoryfabricGetMemInterMapParams__ = &__nvoc_thunk_Memory_memoryfabricGetMemInterMapParams; + + pThis->__memoryfabricGetMemoryMappingDescriptor__ = &__nvoc_thunk_Memory_memoryfabricGetMemoryMappingDescriptor; + + pThis->__memoryfabricControlFilter__ = &__nvoc_thunk_RsResource_memoryfabricControlFilter; + + pThis->__memoryfabricControlSerialization_Prologue__ = &__nvoc_thunk_RmResource_memoryfabricControlSerialization_Prologue; + pThis->__memoryfabricIsReady__ = &__nvoc_thunk_Memory_memoryfabricIsReady; pThis->__memoryfabricCheckCopyPermissions__ = &__nvoc_thunk_Memory_memoryfabricCheckCopyPermissions; @@ -351,11 +424,7 @@ pThis->__memoryfabricIsDuplicate__ = &__nvoc_thunk_Memory_memoryfabricIsDuplicate; - pThis->__memoryfabricUnmapFrom__ = &__nvoc_thunk_RsResource_memoryfabricUnmapFrom; - - pThis->__memoryfabricControl_Epilogue__ = &__nvoc_thunk_RmResource_memoryfabricControl_Epilogue; - - pThis->__memoryfabricControlLookup__ = &__nvoc_thunk_RsResource_memoryfabricControlLookup; + pThis->__memoryfabricControlSerialization_Epilogue__ = &__nvoc_thunk_RmResource_memoryfabricControlSerialization_Epilogue; pThis->__memoryfabricMap__ = &__nvoc_thunk_Memory_memoryfabricMap; @@ -383,13 +452,16 @@ Object *pParentObj; MemoryFabric *pThis; - pThis = portMemAllocNonPaged(sizeof(MemoryFabric)); - if (pThis == NULL) return NV_ERR_NO_MEMORY; + status = __nvoc_handleObjCreateMemAlloc(createFlags, sizeof(MemoryFabric), (void**)&pThis, (void**)ppThis); + if (status != NV_OK) + return status; portMemSet(pThis, 0, sizeof(MemoryFabric)); __nvoc_initRtti(staticCast(pThis, Dynamic), &__nvoc_class_def_MemoryFabric); + pThis->__nvoc_base_Memory.__nvoc_base_RmResource.__nvoc_base_RsResource.__nvoc_base_Object.createFlags = createFlags; + if (pParent != NULL && !(createFlags & NVOC_OBJ_CREATE_FLAGS_PARENT_HALSPEC_ONLY)) { pParentObj = dynamicCast(pParent, Object); @@ -405,11 +477,17 @@ if (status != NV_OK) goto __nvoc_objCreate_MemoryFabric_cleanup; *ppThis = pThis; + return NV_OK; __nvoc_objCreate_MemoryFabric_cleanup: // do not call destructors here since the constructor already called them - portMemFree(pThis); + if (createFlags & NVOC_OBJ_CREATE_FLAGS_IN_PLACE_CONSTRUCT) + portMemSet(pThis, 0, sizeof(MemoryFabric)); + else + portMemFree(pThis); + + // coverity[leaked_storage:FALSE] return status; } diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/generated/g_mem_fabric_nvoc.h nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_mem_fabric_nvoc.h --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/generated/g_mem_fabric_nvoc.h 2023-10-25 20:27:12.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_mem_fabric_nvoc.h 2024-03-05 22:18:33.000000000 +0000 @@ -7,7 +7,7 @@ #endif /* - * SPDX-FileCopyrightText: Copyright (c) 2021-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2021-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -73,25 +73,30 @@ NV_STATUS (*__memoryfabricCtrlCmdDescribe__)(struct MemoryFabric *, NV00F8_CTRL_DESCRIBE_PARAMS *); NV_STATUS (*__memoryfabricCtrlAttachMem__)(struct MemoryFabric *, NV00F8_CTRL_ATTACH_MEM_PARAMS *); NV_STATUS (*__memoryfabricCtrlDetachMem__)(struct MemoryFabric *, NV00F8_CTRL_DETACH_MEM_PARAMS *); + NV_STATUS (*__memoryfabricCtrlGetNumAttachedMem__)(struct MemoryFabric *, NV00F8_CTRL_GET_NUM_ATTACHED_MEM_PARAMS *); + NV_STATUS (*__memoryfabricCtrlGetAttachedMem__)(struct MemoryFabric *, NV00F8_CTRL_GET_ATTACHED_MEM_PARAMS *); + NV_STATUS (*__memoryfabricCtrlGetPageLevelInfo__)(struct MemoryFabric *, NV00F8_CTRL_GET_PAGE_LEVEL_INFO_PARAMS *); NV_STATUS (*__memoryfabricCheckMemInterUnmap__)(struct MemoryFabric *, NvBool); - NV_STATUS (*__memoryfabricUnmap__)(struct MemoryFabric *, CALL_CONTEXT *, RsCpuMapping *); - NV_STATUS (*__memoryfabricGetMemInterMapParams__)(struct MemoryFabric *, RMRES_MEM_INTER_MAP_PARAMS *); - NV_STATUS (*__memoryfabricGetMemoryMappingDescriptor__)(struct MemoryFabric *, MEMORY_DESCRIPTOR **); - NV_STATUS (*__memoryfabricGetMapAddrSpace__)(struct MemoryFabric *, CALL_CONTEXT *, NvU32, NV_ADDRESS_SPACE *); NvBool (*__memoryfabricShareCallback__)(struct MemoryFabric *, struct RsClient *, struct RsResourceRef *, RS_SHARE_POLICY *); - NV_STATUS (*__memoryfabricControlFilter__)(struct MemoryFabric *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); - void (*__memoryfabricAddAdditionalDependants__)(struct RsClient *, struct MemoryFabric *, RsResourceRef *); - NvU32 (*__memoryfabricGetRefCount__)(struct MemoryFabric *); NV_STATUS (*__memoryfabricMapTo__)(struct MemoryFabric *, RS_RES_MAP_TO_PARAMS *); + NV_STATUS (*__memoryfabricGetMapAddrSpace__)(struct MemoryFabric *, CALL_CONTEXT *, NvU32, NV_ADDRESS_SPACE *); + NvU32 (*__memoryfabricGetRefCount__)(struct MemoryFabric *); + void (*__memoryfabricAddAdditionalDependants__)(struct RsClient *, struct MemoryFabric *, RsResourceRef *); NV_STATUS (*__memoryfabricControl_Prologue__)(struct MemoryFabric *, CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); NvBool (*__memoryfabricIsGpuMapAllowed__)(struct MemoryFabric *, struct OBJGPU *); - NV_STATUS (*__memoryfabricIsReady__)(struct MemoryFabric *, NvBool); - NV_STATUS (*__memoryfabricCheckCopyPermissions__)(struct MemoryFabric *, struct OBJGPU *, NvHandle); - void (*__memoryfabricPreDestruct__)(struct MemoryFabric *); - NV_STATUS (*__memoryfabricIsDuplicate__)(struct MemoryFabric *, NvHandle, NvBool *); NV_STATUS (*__memoryfabricUnmapFrom__)(struct MemoryFabric *, RS_RES_UNMAP_FROM_PARAMS *); void (*__memoryfabricControl_Epilogue__)(struct MemoryFabric *, CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); NV_STATUS (*__memoryfabricControlLookup__)(struct MemoryFabric *, struct RS_RES_CONTROL_PARAMS_INTERNAL *, const struct NVOC_EXPORTED_METHOD_DEF **); + NV_STATUS (*__memoryfabricUnmap__)(struct MemoryFabric *, CALL_CONTEXT *, RsCpuMapping *); + NV_STATUS (*__memoryfabricGetMemInterMapParams__)(struct MemoryFabric *, RMRES_MEM_INTER_MAP_PARAMS *); + NV_STATUS (*__memoryfabricGetMemoryMappingDescriptor__)(struct MemoryFabric *, MEMORY_DESCRIPTOR **); + NV_STATUS (*__memoryfabricControlFilter__)(struct MemoryFabric *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); + NV_STATUS (*__memoryfabricControlSerialization_Prologue__)(struct MemoryFabric *, CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); + NV_STATUS (*__memoryfabricIsReady__)(struct MemoryFabric *, NvBool); + NV_STATUS (*__memoryfabricCheckCopyPermissions__)(struct MemoryFabric *, struct OBJGPU *, struct Device *); + void (*__memoryfabricPreDestruct__)(struct MemoryFabric *); + NV_STATUS (*__memoryfabricIsDuplicate__)(struct MemoryFabric *, NvHandle, NvBool *); + void (*__memoryfabricControlSerialization_Epilogue__)(struct MemoryFabric *, CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); NV_STATUS (*__memoryfabricMap__)(struct MemoryFabric *, CALL_CONTEXT *, struct RS_CPU_MAP_PARAMS *, RsCpuMapping *); NvBool (*__memoryfabricAccessCallback__)(struct MemoryFabric *, struct RsClient *, void *, RsAccessRight); }; @@ -131,25 +136,30 @@ #define memoryfabricCtrlCmdDescribe(pMemoryFabric, pParams) memoryfabricCtrlCmdDescribe_DISPATCH(pMemoryFabric, pParams) #define memoryfabricCtrlAttachMem(pMemoryFabric, pParams) memoryfabricCtrlAttachMem_DISPATCH(pMemoryFabric, pParams) #define memoryfabricCtrlDetachMem(pMemoryFabric, pParams) memoryfabricCtrlDetachMem_DISPATCH(pMemoryFabric, pParams) +#define memoryfabricCtrlGetNumAttachedMem(pMemoryFabric, pParams) memoryfabricCtrlGetNumAttachedMem_DISPATCH(pMemoryFabric, pParams) +#define memoryfabricCtrlGetAttachedMem(pMemoryFabric, pParams) memoryfabricCtrlGetAttachedMem_DISPATCH(pMemoryFabric, pParams) +#define memoryfabricCtrlGetPageLevelInfo(pMemoryFabric, pParams) memoryfabricCtrlGetPageLevelInfo_DISPATCH(pMemoryFabric, pParams) #define memoryfabricCheckMemInterUnmap(pMemory, bSubdeviceHandleProvided) memoryfabricCheckMemInterUnmap_DISPATCH(pMemory, bSubdeviceHandleProvided) -#define memoryfabricUnmap(pMemory, pCallContext, pCpuMapping) memoryfabricUnmap_DISPATCH(pMemory, pCallContext, pCpuMapping) -#define memoryfabricGetMemInterMapParams(pMemory, pParams) memoryfabricGetMemInterMapParams_DISPATCH(pMemory, pParams) -#define memoryfabricGetMemoryMappingDescriptor(pMemory, ppMemDesc) memoryfabricGetMemoryMappingDescriptor_DISPATCH(pMemory, ppMemDesc) -#define memoryfabricGetMapAddrSpace(pMemory, pCallContext, mapFlags, pAddrSpace) memoryfabricGetMapAddrSpace_DISPATCH(pMemory, pCallContext, mapFlags, pAddrSpace) #define memoryfabricShareCallback(pResource, pInvokingClient, pParentRef, pSharePolicy) memoryfabricShareCallback_DISPATCH(pResource, pInvokingClient, pParentRef, pSharePolicy) -#define memoryfabricControlFilter(pResource, pCallContext, pParams) memoryfabricControlFilter_DISPATCH(pResource, pCallContext, pParams) -#define memoryfabricAddAdditionalDependants(pClient, pResource, pReference) memoryfabricAddAdditionalDependants_DISPATCH(pClient, pResource, pReference) -#define memoryfabricGetRefCount(pResource) memoryfabricGetRefCount_DISPATCH(pResource) #define memoryfabricMapTo(pResource, pParams) memoryfabricMapTo_DISPATCH(pResource, pParams) +#define memoryfabricGetMapAddrSpace(pMemory, pCallContext, mapFlags, pAddrSpace) memoryfabricGetMapAddrSpace_DISPATCH(pMemory, pCallContext, mapFlags, pAddrSpace) +#define memoryfabricGetRefCount(pResource) memoryfabricGetRefCount_DISPATCH(pResource) +#define memoryfabricAddAdditionalDependants(pClient, pResource, pReference) memoryfabricAddAdditionalDependants_DISPATCH(pClient, pResource, pReference) #define memoryfabricControl_Prologue(pResource, pCallContext, pParams) memoryfabricControl_Prologue_DISPATCH(pResource, pCallContext, pParams) #define memoryfabricIsGpuMapAllowed(pMemory, pGpu) memoryfabricIsGpuMapAllowed_DISPATCH(pMemory, pGpu) -#define memoryfabricIsReady(pMemory, bCopyConstructorContext) memoryfabricIsReady_DISPATCH(pMemory, bCopyConstructorContext) -#define memoryfabricCheckCopyPermissions(pMemory, pDstGpu, hDstClientNvBool) memoryfabricCheckCopyPermissions_DISPATCH(pMemory, pDstGpu, hDstClientNvBool) -#define memoryfabricPreDestruct(pResource) memoryfabricPreDestruct_DISPATCH(pResource) -#define memoryfabricIsDuplicate(pMemory, hMemory, pDuplicate) memoryfabricIsDuplicate_DISPATCH(pMemory, hMemory, pDuplicate) #define memoryfabricUnmapFrom(pResource, pParams) memoryfabricUnmapFrom_DISPATCH(pResource, pParams) #define memoryfabricControl_Epilogue(pResource, pCallContext, pParams) memoryfabricControl_Epilogue_DISPATCH(pResource, pCallContext, pParams) #define memoryfabricControlLookup(pResource, pParams, ppEntry) memoryfabricControlLookup_DISPATCH(pResource, pParams, ppEntry) +#define memoryfabricUnmap(pMemory, pCallContext, pCpuMapping) memoryfabricUnmap_DISPATCH(pMemory, pCallContext, pCpuMapping) +#define memoryfabricGetMemInterMapParams(pMemory, pParams) memoryfabricGetMemInterMapParams_DISPATCH(pMemory, pParams) +#define memoryfabricGetMemoryMappingDescriptor(pMemory, ppMemDesc) memoryfabricGetMemoryMappingDescriptor_DISPATCH(pMemory, ppMemDesc) +#define memoryfabricControlFilter(pResource, pCallContext, pParams) memoryfabricControlFilter_DISPATCH(pResource, pCallContext, pParams) +#define memoryfabricControlSerialization_Prologue(pResource, pCallContext, pParams) memoryfabricControlSerialization_Prologue_DISPATCH(pResource, pCallContext, pParams) +#define memoryfabricIsReady(pMemory, bCopyConstructorContext) memoryfabricIsReady_DISPATCH(pMemory, bCopyConstructorContext) +#define memoryfabricCheckCopyPermissions(pMemory, pDstGpu, pDstDevice) memoryfabricCheckCopyPermissions_DISPATCH(pMemory, pDstGpu, pDstDevice) +#define memoryfabricPreDestruct(pResource) memoryfabricPreDestruct_DISPATCH(pResource) +#define memoryfabricIsDuplicate(pMemory, hMemory, pDuplicate) memoryfabricIsDuplicate_DISPATCH(pMemory, hMemory, pDuplicate) +#define memoryfabricControlSerialization_Epilogue(pResource, pCallContext, pParams) memoryfabricControlSerialization_Epilogue_DISPATCH(pResource, pCallContext, pParams) #define memoryfabricMap(pMemory, pCallContext, pParams, pCpuMapping) memoryfabricMap_DISPATCH(pMemory, pCallContext, pParams, pCpuMapping) #define memoryfabricAccessCallback(pResource, pInvokingClient, pAllocParams, accessRight) memoryfabricAccessCallback_DISPATCH(pResource, pInvokingClient, pAllocParams, accessRight) NvBool memoryfabricCanCopy_IMPL(struct MemoryFabric *pMemoryFabric); @@ -194,44 +204,46 @@ return pMemoryFabric->__memoryfabricCtrlDetachMem__(pMemoryFabric, pParams); } -static inline NV_STATUS memoryfabricCheckMemInterUnmap_DISPATCH(struct MemoryFabric *pMemory, NvBool bSubdeviceHandleProvided) { - return pMemory->__memoryfabricCheckMemInterUnmap__(pMemory, bSubdeviceHandleProvided); -} +NV_STATUS memoryfabricCtrlGetNumAttachedMem_IMPL(struct MemoryFabric *pMemoryFabric, NV00F8_CTRL_GET_NUM_ATTACHED_MEM_PARAMS *pParams); -static inline NV_STATUS memoryfabricUnmap_DISPATCH(struct MemoryFabric *pMemory, CALL_CONTEXT *pCallContext, RsCpuMapping *pCpuMapping) { - return pMemory->__memoryfabricUnmap__(pMemory, pCallContext, pCpuMapping); +static inline NV_STATUS memoryfabricCtrlGetNumAttachedMem_DISPATCH(struct MemoryFabric *pMemoryFabric, NV00F8_CTRL_GET_NUM_ATTACHED_MEM_PARAMS *pParams) { + return pMemoryFabric->__memoryfabricCtrlGetNumAttachedMem__(pMemoryFabric, pParams); } -static inline NV_STATUS memoryfabricGetMemInterMapParams_DISPATCH(struct MemoryFabric *pMemory, RMRES_MEM_INTER_MAP_PARAMS *pParams) { - return pMemory->__memoryfabricGetMemInterMapParams__(pMemory, pParams); +NV_STATUS memoryfabricCtrlGetAttachedMem_IMPL(struct MemoryFabric *pMemoryFabric, NV00F8_CTRL_GET_ATTACHED_MEM_PARAMS *pParams); + +static inline NV_STATUS memoryfabricCtrlGetAttachedMem_DISPATCH(struct MemoryFabric *pMemoryFabric, NV00F8_CTRL_GET_ATTACHED_MEM_PARAMS *pParams) { + return pMemoryFabric->__memoryfabricCtrlGetAttachedMem__(pMemoryFabric, pParams); } -static inline NV_STATUS memoryfabricGetMemoryMappingDescriptor_DISPATCH(struct MemoryFabric *pMemory, MEMORY_DESCRIPTOR **ppMemDesc) { - return pMemory->__memoryfabricGetMemoryMappingDescriptor__(pMemory, ppMemDesc); +NV_STATUS memoryfabricCtrlGetPageLevelInfo_IMPL(struct MemoryFabric *pMemoryFabric, NV00F8_CTRL_GET_PAGE_LEVEL_INFO_PARAMS *pParams); + +static inline NV_STATUS memoryfabricCtrlGetPageLevelInfo_DISPATCH(struct MemoryFabric *pMemoryFabric, NV00F8_CTRL_GET_PAGE_LEVEL_INFO_PARAMS *pParams) { + return pMemoryFabric->__memoryfabricCtrlGetPageLevelInfo__(pMemoryFabric, pParams); } -static inline NV_STATUS memoryfabricGetMapAddrSpace_DISPATCH(struct MemoryFabric *pMemory, CALL_CONTEXT *pCallContext, NvU32 mapFlags, NV_ADDRESS_SPACE *pAddrSpace) { - return pMemory->__memoryfabricGetMapAddrSpace__(pMemory, pCallContext, mapFlags, pAddrSpace); +static inline NV_STATUS memoryfabricCheckMemInterUnmap_DISPATCH(struct MemoryFabric *pMemory, NvBool bSubdeviceHandleProvided) { + return pMemory->__memoryfabricCheckMemInterUnmap__(pMemory, bSubdeviceHandleProvided); } static inline NvBool memoryfabricShareCallback_DISPATCH(struct MemoryFabric *pResource, struct RsClient *pInvokingClient, struct RsResourceRef *pParentRef, RS_SHARE_POLICY *pSharePolicy) { return pResource->__memoryfabricShareCallback__(pResource, pInvokingClient, pParentRef, pSharePolicy); } -static inline NV_STATUS memoryfabricControlFilter_DISPATCH(struct MemoryFabric *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { - return pResource->__memoryfabricControlFilter__(pResource, pCallContext, pParams); +static inline NV_STATUS memoryfabricMapTo_DISPATCH(struct MemoryFabric *pResource, RS_RES_MAP_TO_PARAMS *pParams) { + return pResource->__memoryfabricMapTo__(pResource, pParams); } -static inline void memoryfabricAddAdditionalDependants_DISPATCH(struct RsClient *pClient, struct MemoryFabric *pResource, RsResourceRef *pReference) { - pResource->__memoryfabricAddAdditionalDependants__(pClient, pResource, pReference); +static inline NV_STATUS memoryfabricGetMapAddrSpace_DISPATCH(struct MemoryFabric *pMemory, CALL_CONTEXT *pCallContext, NvU32 mapFlags, NV_ADDRESS_SPACE *pAddrSpace) { + return pMemory->__memoryfabricGetMapAddrSpace__(pMemory, pCallContext, mapFlags, pAddrSpace); } static inline NvU32 memoryfabricGetRefCount_DISPATCH(struct MemoryFabric *pResource) { return pResource->__memoryfabricGetRefCount__(pResource); } -static inline NV_STATUS memoryfabricMapTo_DISPATCH(struct MemoryFabric *pResource, RS_RES_MAP_TO_PARAMS *pParams) { - return pResource->__memoryfabricMapTo__(pResource, pParams); +static inline void memoryfabricAddAdditionalDependants_DISPATCH(struct RsClient *pClient, struct MemoryFabric *pResource, RsResourceRef *pReference) { + pResource->__memoryfabricAddAdditionalDependants__(pClient, pResource, pReference); } static inline NV_STATUS memoryfabricControl_Prologue_DISPATCH(struct MemoryFabric *pResource, CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { @@ -242,12 +254,44 @@ return pMemory->__memoryfabricIsGpuMapAllowed__(pMemory, pGpu); } +static inline NV_STATUS memoryfabricUnmapFrom_DISPATCH(struct MemoryFabric *pResource, RS_RES_UNMAP_FROM_PARAMS *pParams) { + return pResource->__memoryfabricUnmapFrom__(pResource, pParams); +} + +static inline void memoryfabricControl_Epilogue_DISPATCH(struct MemoryFabric *pResource, CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + pResource->__memoryfabricControl_Epilogue__(pResource, pCallContext, pParams); +} + +static inline NV_STATUS memoryfabricControlLookup_DISPATCH(struct MemoryFabric *pResource, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams, const struct NVOC_EXPORTED_METHOD_DEF **ppEntry) { + return pResource->__memoryfabricControlLookup__(pResource, pParams, ppEntry); +} + +static inline NV_STATUS memoryfabricUnmap_DISPATCH(struct MemoryFabric *pMemory, CALL_CONTEXT *pCallContext, RsCpuMapping *pCpuMapping) { + return pMemory->__memoryfabricUnmap__(pMemory, pCallContext, pCpuMapping); +} + +static inline NV_STATUS memoryfabricGetMemInterMapParams_DISPATCH(struct MemoryFabric *pMemory, RMRES_MEM_INTER_MAP_PARAMS *pParams) { + return pMemory->__memoryfabricGetMemInterMapParams__(pMemory, pParams); +} + +static inline NV_STATUS memoryfabricGetMemoryMappingDescriptor_DISPATCH(struct MemoryFabric *pMemory, MEMORY_DESCRIPTOR **ppMemDesc) { + return pMemory->__memoryfabricGetMemoryMappingDescriptor__(pMemory, ppMemDesc); +} + +static inline NV_STATUS memoryfabricControlFilter_DISPATCH(struct MemoryFabric *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return pResource->__memoryfabricControlFilter__(pResource, pCallContext, pParams); +} + +static inline NV_STATUS memoryfabricControlSerialization_Prologue_DISPATCH(struct MemoryFabric *pResource, CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return pResource->__memoryfabricControlSerialization_Prologue__(pResource, pCallContext, pParams); +} + static inline NV_STATUS memoryfabricIsReady_DISPATCH(struct MemoryFabric *pMemory, NvBool bCopyConstructorContext) { return pMemory->__memoryfabricIsReady__(pMemory, bCopyConstructorContext); } -static inline NV_STATUS memoryfabricCheckCopyPermissions_DISPATCH(struct MemoryFabric *pMemory, struct OBJGPU *pDstGpu, NvHandle hDstClientNvBool) { - return pMemory->__memoryfabricCheckCopyPermissions__(pMemory, pDstGpu, hDstClientNvBool); +static inline NV_STATUS memoryfabricCheckCopyPermissions_DISPATCH(struct MemoryFabric *pMemory, struct OBJGPU *pDstGpu, struct Device *pDstDevice) { + return pMemory->__memoryfabricCheckCopyPermissions__(pMemory, pDstGpu, pDstDevice); } static inline void memoryfabricPreDestruct_DISPATCH(struct MemoryFabric *pResource) { @@ -258,16 +302,8 @@ return pMemory->__memoryfabricIsDuplicate__(pMemory, hMemory, pDuplicate); } -static inline NV_STATUS memoryfabricUnmapFrom_DISPATCH(struct MemoryFabric *pResource, RS_RES_UNMAP_FROM_PARAMS *pParams) { - return pResource->__memoryfabricUnmapFrom__(pResource, pParams); -} - -static inline void memoryfabricControl_Epilogue_DISPATCH(struct MemoryFabric *pResource, CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { - pResource->__memoryfabricControl_Epilogue__(pResource, pCallContext, pParams); -} - -static inline NV_STATUS memoryfabricControlLookup_DISPATCH(struct MemoryFabric *pResource, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams, const struct NVOC_EXPORTED_METHOD_DEF **ppEntry) { - return pResource->__memoryfabricControlLookup__(pResource, pParams, ppEntry); +static inline void memoryfabricControlSerialization_Epilogue_DISPATCH(struct MemoryFabric *pResource, CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + pResource->__memoryfabricControlSerialization_Epilogue__(pResource, pCallContext, pParams); } static inline NV_STATUS memoryfabricMap_DISPATCH(struct MemoryFabric *pMemory, CALL_CONTEXT *pCallContext, struct RS_CPU_MAP_PARAMS *pParams, RsCpuMapping *pCpuMapping) { @@ -290,6 +326,7 @@ typedef struct { MEMORY_DESCRIPTOR *pPhysMemDesc; + NvU64 physMapOffset; NvU64 physMapLength; NvHandle hDupedPhysMem; NODE node; diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/generated/g_mem_list_nvoc.c nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_mem_list_nvoc.c --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/generated/g_mem_list_nvoc.c 2023-10-25 20:27:12.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_mem_list_nvoc.c 2024-03-05 22:18:33.000000000 +0000 @@ -101,60 +101,76 @@ return memCheckMemInterUnmap((struct Memory *)(((unsigned char *)pMemory) + __nvoc_rtti_MemoryList_Memory.offset), bSubdeviceHandleProvided); } -static NV_STATUS __nvoc_thunk_Memory_memlistControl(struct MemoryList *pMemory, CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { - return memControl((struct Memory *)(((unsigned char *)pMemory) + __nvoc_rtti_MemoryList_Memory.offset), pCallContext, pParams); +static NvBool __nvoc_thunk_RmResource_memlistShareCallback(struct MemoryList *pResource, struct RsClient *pInvokingClient, struct RsResourceRef *pParentRef, RS_SHARE_POLICY *pSharePolicy) { + return rmresShareCallback((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_MemoryList_RmResource.offset), pInvokingClient, pParentRef, pSharePolicy); } -static NV_STATUS __nvoc_thunk_Memory_memlistUnmap(struct MemoryList *pMemory, CALL_CONTEXT *pCallContext, RsCpuMapping *pCpuMapping) { - return memUnmap((struct Memory *)(((unsigned char *)pMemory) + __nvoc_rtti_MemoryList_Memory.offset), pCallContext, pCpuMapping); +static NV_STATUS __nvoc_thunk_RsResource_memlistMapTo(struct MemoryList *pResource, RS_RES_MAP_TO_PARAMS *pParams) { + return resMapTo((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_MemoryList_RsResource.offset), pParams); } -static NV_STATUS __nvoc_thunk_Memory_memlistGetMemInterMapParams(struct MemoryList *pMemory, RMRES_MEM_INTER_MAP_PARAMS *pParams) { - return memGetMemInterMapParams((struct Memory *)(((unsigned char *)pMemory) + __nvoc_rtti_MemoryList_Memory.offset), pParams); +static NV_STATUS __nvoc_thunk_Memory_memlistGetMapAddrSpace(struct MemoryList *pMemory, CALL_CONTEXT *pCallContext, NvU32 mapFlags, NV_ADDRESS_SPACE *pAddrSpace) { + return memGetMapAddrSpace((struct Memory *)(((unsigned char *)pMemory) + __nvoc_rtti_MemoryList_Memory.offset), pCallContext, mapFlags, pAddrSpace); } -static NV_STATUS __nvoc_thunk_Memory_memlistGetMemoryMappingDescriptor(struct MemoryList *pMemory, MEMORY_DESCRIPTOR **ppMemDesc) { - return memGetMemoryMappingDescriptor((struct Memory *)(((unsigned char *)pMemory) + __nvoc_rtti_MemoryList_Memory.offset), ppMemDesc); +static NvU32 __nvoc_thunk_RsResource_memlistGetRefCount(struct MemoryList *pResource) { + return resGetRefCount((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_MemoryList_RsResource.offset)); } -static NV_STATUS __nvoc_thunk_Memory_memlistGetMapAddrSpace(struct MemoryList *pMemory, CALL_CONTEXT *pCallContext, NvU32 mapFlags, NV_ADDRESS_SPACE *pAddrSpace) { - return memGetMapAddrSpace((struct Memory *)(((unsigned char *)pMemory) + __nvoc_rtti_MemoryList_Memory.offset), pCallContext, mapFlags, pAddrSpace); +static void __nvoc_thunk_RsResource_memlistAddAdditionalDependants(struct RsClient *pClient, struct MemoryList *pResource, RsResourceRef *pReference) { + resAddAdditionalDependants(pClient, (struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_MemoryList_RsResource.offset), pReference); } -static NvBool __nvoc_thunk_RmResource_memlistShareCallback(struct MemoryList *pResource, struct RsClient *pInvokingClient, struct RsResourceRef *pParentRef, RS_SHARE_POLICY *pSharePolicy) { - return rmresShareCallback((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_MemoryList_RmResource.offset), pInvokingClient, pParentRef, pSharePolicy); +static NV_STATUS __nvoc_thunk_RmResource_memlistControl_Prologue(struct MemoryList *pResource, CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return rmresControl_Prologue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_MemoryList_RmResource.offset), pCallContext, pParams); } -static NV_STATUS __nvoc_thunk_RsResource_memlistControlFilter(struct MemoryList *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { - return resControlFilter((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_MemoryList_RsResource.offset), pCallContext, pParams); +static NvBool __nvoc_thunk_Memory_memlistIsGpuMapAllowed(struct MemoryList *pMemory, struct OBJGPU *pGpu) { + return memIsGpuMapAllowed((struct Memory *)(((unsigned char *)pMemory) + __nvoc_rtti_MemoryList_Memory.offset), pGpu); } -static void __nvoc_thunk_RsResource_memlistAddAdditionalDependants(struct RsClient *pClient, struct MemoryList *pResource, RsResourceRef *pReference) { - resAddAdditionalDependants(pClient, (struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_MemoryList_RsResource.offset), pReference); +static NV_STATUS __nvoc_thunk_RsResource_memlistUnmapFrom(struct MemoryList *pResource, RS_RES_UNMAP_FROM_PARAMS *pParams) { + return resUnmapFrom((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_MemoryList_RsResource.offset), pParams); } -static NvU32 __nvoc_thunk_RsResource_memlistGetRefCount(struct MemoryList *pResource) { - return resGetRefCount((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_MemoryList_RsResource.offset)); +static void __nvoc_thunk_RmResource_memlistControl_Epilogue(struct MemoryList *pResource, CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + rmresControl_Epilogue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_MemoryList_RmResource.offset), pCallContext, pParams); } -static NV_STATUS __nvoc_thunk_RsResource_memlistMapTo(struct MemoryList *pResource, RS_RES_MAP_TO_PARAMS *pParams) { - return resMapTo((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_MemoryList_RsResource.offset), pParams); +static NV_STATUS __nvoc_thunk_RsResource_memlistControlLookup(struct MemoryList *pResource, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams, const struct NVOC_EXPORTED_METHOD_DEF **ppEntry) { + return resControlLookup((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_MemoryList_RsResource.offset), pParams, ppEntry); } -static NV_STATUS __nvoc_thunk_RmResource_memlistControl_Prologue(struct MemoryList *pResource, CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { - return rmresControl_Prologue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_MemoryList_RmResource.offset), pCallContext, pParams); +static NV_STATUS __nvoc_thunk_Memory_memlistControl(struct MemoryList *pMemory, CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return memControl((struct Memory *)(((unsigned char *)pMemory) + __nvoc_rtti_MemoryList_Memory.offset), pCallContext, pParams); } -static NvBool __nvoc_thunk_Memory_memlistIsGpuMapAllowed(struct MemoryList *pMemory, struct OBJGPU *pGpu) { - return memIsGpuMapAllowed((struct Memory *)(((unsigned char *)pMemory) + __nvoc_rtti_MemoryList_Memory.offset), pGpu); +static NV_STATUS __nvoc_thunk_Memory_memlistUnmap(struct MemoryList *pMemory, CALL_CONTEXT *pCallContext, RsCpuMapping *pCpuMapping) { + return memUnmap((struct Memory *)(((unsigned char *)pMemory) + __nvoc_rtti_MemoryList_Memory.offset), pCallContext, pCpuMapping); +} + +static NV_STATUS __nvoc_thunk_Memory_memlistGetMemInterMapParams(struct MemoryList *pMemory, RMRES_MEM_INTER_MAP_PARAMS *pParams) { + return memGetMemInterMapParams((struct Memory *)(((unsigned char *)pMemory) + __nvoc_rtti_MemoryList_Memory.offset), pParams); +} + +static NV_STATUS __nvoc_thunk_Memory_memlistGetMemoryMappingDescriptor(struct MemoryList *pMemory, MEMORY_DESCRIPTOR **ppMemDesc) { + return memGetMemoryMappingDescriptor((struct Memory *)(((unsigned char *)pMemory) + __nvoc_rtti_MemoryList_Memory.offset), ppMemDesc); +} + +static NV_STATUS __nvoc_thunk_RsResource_memlistControlFilter(struct MemoryList *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return resControlFilter((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_MemoryList_RsResource.offset), pCallContext, pParams); +} + +static NV_STATUS __nvoc_thunk_RmResource_memlistControlSerialization_Prologue(struct MemoryList *pResource, CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return rmresControlSerialization_Prologue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_MemoryList_RmResource.offset), pCallContext, pParams); } static NV_STATUS __nvoc_thunk_Memory_memlistIsReady(struct MemoryList *pMemory, NvBool bCopyConstructorContext) { return memIsReady((struct Memory *)(((unsigned char *)pMemory) + __nvoc_rtti_MemoryList_Memory.offset), bCopyConstructorContext); } -static NV_STATUS __nvoc_thunk_Memory_memlistCheckCopyPermissions(struct MemoryList *pMemory, struct OBJGPU *pDstGpu, NvHandle hDstClientNvBool) { - return memCheckCopyPermissions((struct Memory *)(((unsigned char *)pMemory) + __nvoc_rtti_MemoryList_Memory.offset), pDstGpu, hDstClientNvBool); +static NV_STATUS __nvoc_thunk_Memory_memlistCheckCopyPermissions(struct MemoryList *pMemory, struct OBJGPU *pDstGpu, struct Device *pDstDevice) { + return memCheckCopyPermissions((struct Memory *)(((unsigned char *)pMemory) + __nvoc_rtti_MemoryList_Memory.offset), pDstGpu, pDstDevice); } static void __nvoc_thunk_RsResource_memlistPreDestruct(struct MemoryList *pResource) { @@ -165,16 +181,8 @@ return memIsDuplicate((struct Memory *)(((unsigned char *)pMemory) + __nvoc_rtti_MemoryList_Memory.offset), hMemory, pDuplicate); } -static NV_STATUS __nvoc_thunk_RsResource_memlistUnmapFrom(struct MemoryList *pResource, RS_RES_UNMAP_FROM_PARAMS *pParams) { - return resUnmapFrom((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_MemoryList_RsResource.offset), pParams); -} - -static void __nvoc_thunk_RmResource_memlistControl_Epilogue(struct MemoryList *pResource, CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { - rmresControl_Epilogue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_MemoryList_RmResource.offset), pCallContext, pParams); -} - -static NV_STATUS __nvoc_thunk_RsResource_memlistControlLookup(struct MemoryList *pResource, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams, const struct NVOC_EXPORTED_METHOD_DEF **ppEntry) { - return resControlLookup((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_MemoryList_RsResource.offset), pParams, ppEntry); +static void __nvoc_thunk_RmResource_memlistControlSerialization_Epilogue(struct MemoryList *pResource, CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + rmresControlSerialization_Epilogue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_MemoryList_RmResource.offset), pCallContext, pParams); } static NV_STATUS __nvoc_thunk_Memory_memlistMap(struct MemoryList *pMemory, CALL_CONTEXT *pCallContext, struct RS_CPU_MAP_PARAMS *pParams, RsCpuMapping *pCpuMapping) { @@ -229,29 +237,37 @@ pThis->__memlistCheckMemInterUnmap__ = &__nvoc_thunk_Memory_memlistCheckMemInterUnmap; - pThis->__memlistControl__ = &__nvoc_thunk_Memory_memlistControl; + pThis->__memlistShareCallback__ = &__nvoc_thunk_RmResource_memlistShareCallback; - pThis->__memlistUnmap__ = &__nvoc_thunk_Memory_memlistUnmap; + pThis->__memlistMapTo__ = &__nvoc_thunk_RsResource_memlistMapTo; - pThis->__memlistGetMemInterMapParams__ = &__nvoc_thunk_Memory_memlistGetMemInterMapParams; + pThis->__memlistGetMapAddrSpace__ = &__nvoc_thunk_Memory_memlistGetMapAddrSpace; - pThis->__memlistGetMemoryMappingDescriptor__ = &__nvoc_thunk_Memory_memlistGetMemoryMappingDescriptor; + pThis->__memlistGetRefCount__ = &__nvoc_thunk_RsResource_memlistGetRefCount; - pThis->__memlistGetMapAddrSpace__ = &__nvoc_thunk_Memory_memlistGetMapAddrSpace; + pThis->__memlistAddAdditionalDependants__ = &__nvoc_thunk_RsResource_memlistAddAdditionalDependants; - pThis->__memlistShareCallback__ = &__nvoc_thunk_RmResource_memlistShareCallback; + pThis->__memlistControl_Prologue__ = &__nvoc_thunk_RmResource_memlistControl_Prologue; - pThis->__memlistControlFilter__ = &__nvoc_thunk_RsResource_memlistControlFilter; + pThis->__memlistIsGpuMapAllowed__ = &__nvoc_thunk_Memory_memlistIsGpuMapAllowed; - pThis->__memlistAddAdditionalDependants__ = &__nvoc_thunk_RsResource_memlistAddAdditionalDependants; + pThis->__memlistUnmapFrom__ = &__nvoc_thunk_RsResource_memlistUnmapFrom; - pThis->__memlistGetRefCount__ = &__nvoc_thunk_RsResource_memlistGetRefCount; + pThis->__memlistControl_Epilogue__ = &__nvoc_thunk_RmResource_memlistControl_Epilogue; - pThis->__memlistMapTo__ = &__nvoc_thunk_RsResource_memlistMapTo; + pThis->__memlistControlLookup__ = &__nvoc_thunk_RsResource_memlistControlLookup; - pThis->__memlistControl_Prologue__ = &__nvoc_thunk_RmResource_memlistControl_Prologue; + pThis->__memlistControl__ = &__nvoc_thunk_Memory_memlistControl; - pThis->__memlistIsGpuMapAllowed__ = &__nvoc_thunk_Memory_memlistIsGpuMapAllowed; + pThis->__memlistUnmap__ = &__nvoc_thunk_Memory_memlistUnmap; + + pThis->__memlistGetMemInterMapParams__ = &__nvoc_thunk_Memory_memlistGetMemInterMapParams; + + pThis->__memlistGetMemoryMappingDescriptor__ = &__nvoc_thunk_Memory_memlistGetMemoryMappingDescriptor; + + pThis->__memlistControlFilter__ = &__nvoc_thunk_RsResource_memlistControlFilter; + + pThis->__memlistControlSerialization_Prologue__ = &__nvoc_thunk_RmResource_memlistControlSerialization_Prologue; pThis->__memlistIsReady__ = &__nvoc_thunk_Memory_memlistIsReady; @@ -261,11 +277,7 @@ pThis->__memlistIsDuplicate__ = &__nvoc_thunk_Memory_memlistIsDuplicate; - pThis->__memlistUnmapFrom__ = &__nvoc_thunk_RsResource_memlistUnmapFrom; - - pThis->__memlistControl_Epilogue__ = &__nvoc_thunk_RmResource_memlistControl_Epilogue; - - pThis->__memlistControlLookup__ = &__nvoc_thunk_RsResource_memlistControlLookup; + pThis->__memlistControlSerialization_Epilogue__ = &__nvoc_thunk_RmResource_memlistControlSerialization_Epilogue; pThis->__memlistMap__ = &__nvoc_thunk_Memory_memlistMap; @@ -293,13 +305,16 @@ Object *pParentObj; MemoryList *pThis; - pThis = portMemAllocNonPaged(sizeof(MemoryList)); - if (pThis == NULL) return NV_ERR_NO_MEMORY; + status = __nvoc_handleObjCreateMemAlloc(createFlags, sizeof(MemoryList), (void**)&pThis, (void**)ppThis); + if (status != NV_OK) + return status; portMemSet(pThis, 0, sizeof(MemoryList)); __nvoc_initRtti(staticCast(pThis, Dynamic), &__nvoc_class_def_MemoryList); + pThis->__nvoc_base_Memory.__nvoc_base_RmResource.__nvoc_base_RsResource.__nvoc_base_Object.createFlags = createFlags; + if (pParent != NULL && !(createFlags & NVOC_OBJ_CREATE_FLAGS_PARENT_HALSPEC_ONLY)) { pParentObj = dynamicCast(pParent, Object); @@ -315,11 +330,17 @@ if (status != NV_OK) goto __nvoc_objCreate_MemoryList_cleanup; *ppThis = pThis; + return NV_OK; __nvoc_objCreate_MemoryList_cleanup: // do not call destructors here since the constructor already called them - portMemFree(pThis); + if (createFlags & NVOC_OBJ_CREATE_FLAGS_IN_PLACE_CONSTRUCT) + portMemSet(pThis, 0, sizeof(MemoryList)); + else + portMemFree(pThis); + + // coverity[leaked_storage:FALSE] return status; } diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/generated/g_mem_list_nvoc.h nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_mem_list_nvoc.h --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/generated/g_mem_list_nvoc.h 2023-10-25 20:27:12.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_mem_list_nvoc.h 2024-03-05 22:18:33.000000000 +0000 @@ -56,25 +56,27 @@ struct MemoryList *__nvoc_pbase_MemoryList; NvBool (*__memlistCanCopy__)(struct MemoryList *); NV_STATUS (*__memlistCheckMemInterUnmap__)(struct MemoryList *, NvBool); + NvBool (*__memlistShareCallback__)(struct MemoryList *, struct RsClient *, struct RsResourceRef *, RS_SHARE_POLICY *); + NV_STATUS (*__memlistMapTo__)(struct MemoryList *, RS_RES_MAP_TO_PARAMS *); + NV_STATUS (*__memlistGetMapAddrSpace__)(struct MemoryList *, CALL_CONTEXT *, NvU32, NV_ADDRESS_SPACE *); + NvU32 (*__memlistGetRefCount__)(struct MemoryList *); + void (*__memlistAddAdditionalDependants__)(struct RsClient *, struct MemoryList *, RsResourceRef *); + NV_STATUS (*__memlistControl_Prologue__)(struct MemoryList *, CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); + NvBool (*__memlistIsGpuMapAllowed__)(struct MemoryList *, struct OBJGPU *); + NV_STATUS (*__memlistUnmapFrom__)(struct MemoryList *, RS_RES_UNMAP_FROM_PARAMS *); + void (*__memlistControl_Epilogue__)(struct MemoryList *, CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); + NV_STATUS (*__memlistControlLookup__)(struct MemoryList *, struct RS_RES_CONTROL_PARAMS_INTERNAL *, const struct NVOC_EXPORTED_METHOD_DEF **); NV_STATUS (*__memlistControl__)(struct MemoryList *, CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); NV_STATUS (*__memlistUnmap__)(struct MemoryList *, CALL_CONTEXT *, RsCpuMapping *); NV_STATUS (*__memlistGetMemInterMapParams__)(struct MemoryList *, RMRES_MEM_INTER_MAP_PARAMS *); NV_STATUS (*__memlistGetMemoryMappingDescriptor__)(struct MemoryList *, MEMORY_DESCRIPTOR **); - NV_STATUS (*__memlistGetMapAddrSpace__)(struct MemoryList *, CALL_CONTEXT *, NvU32, NV_ADDRESS_SPACE *); - NvBool (*__memlistShareCallback__)(struct MemoryList *, struct RsClient *, struct RsResourceRef *, RS_SHARE_POLICY *); NV_STATUS (*__memlistControlFilter__)(struct MemoryList *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); - void (*__memlistAddAdditionalDependants__)(struct RsClient *, struct MemoryList *, RsResourceRef *); - NvU32 (*__memlistGetRefCount__)(struct MemoryList *); - NV_STATUS (*__memlistMapTo__)(struct MemoryList *, RS_RES_MAP_TO_PARAMS *); - NV_STATUS (*__memlistControl_Prologue__)(struct MemoryList *, CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); - NvBool (*__memlistIsGpuMapAllowed__)(struct MemoryList *, struct OBJGPU *); + NV_STATUS (*__memlistControlSerialization_Prologue__)(struct MemoryList *, CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); NV_STATUS (*__memlistIsReady__)(struct MemoryList *, NvBool); - NV_STATUS (*__memlistCheckCopyPermissions__)(struct MemoryList *, struct OBJGPU *, NvHandle); + NV_STATUS (*__memlistCheckCopyPermissions__)(struct MemoryList *, struct OBJGPU *, struct Device *); void (*__memlistPreDestruct__)(struct MemoryList *); NV_STATUS (*__memlistIsDuplicate__)(struct MemoryList *, NvHandle, NvBool *); - NV_STATUS (*__memlistUnmapFrom__)(struct MemoryList *, RS_RES_UNMAP_FROM_PARAMS *); - void (*__memlistControl_Epilogue__)(struct MemoryList *, CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); - NV_STATUS (*__memlistControlLookup__)(struct MemoryList *, struct RS_RES_CONTROL_PARAMS_INTERNAL *, const struct NVOC_EXPORTED_METHOD_DEF **); + void (*__memlistControlSerialization_Epilogue__)(struct MemoryList *, CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); NV_STATUS (*__memlistMap__)(struct MemoryList *, CALL_CONTEXT *, struct RS_CPU_MAP_PARAMS *, RsCpuMapping *); NvBool (*__memlistAccessCallback__)(struct MemoryList *, struct RsClient *, void *, RsAccessRight); }; @@ -109,25 +111,27 @@ #define memlistCanCopy(pMemoryList) memlistCanCopy_DISPATCH(pMemoryList) #define memlistCheckMemInterUnmap(pMemory, bSubdeviceHandleProvided) memlistCheckMemInterUnmap_DISPATCH(pMemory, bSubdeviceHandleProvided) +#define memlistShareCallback(pResource, pInvokingClient, pParentRef, pSharePolicy) memlistShareCallback_DISPATCH(pResource, pInvokingClient, pParentRef, pSharePolicy) +#define memlistMapTo(pResource, pParams) memlistMapTo_DISPATCH(pResource, pParams) +#define memlistGetMapAddrSpace(pMemory, pCallContext, mapFlags, pAddrSpace) memlistGetMapAddrSpace_DISPATCH(pMemory, pCallContext, mapFlags, pAddrSpace) +#define memlistGetRefCount(pResource) memlistGetRefCount_DISPATCH(pResource) +#define memlistAddAdditionalDependants(pClient, pResource, pReference) memlistAddAdditionalDependants_DISPATCH(pClient, pResource, pReference) +#define memlistControl_Prologue(pResource, pCallContext, pParams) memlistControl_Prologue_DISPATCH(pResource, pCallContext, pParams) +#define memlistIsGpuMapAllowed(pMemory, pGpu) memlistIsGpuMapAllowed_DISPATCH(pMemory, pGpu) +#define memlistUnmapFrom(pResource, pParams) memlistUnmapFrom_DISPATCH(pResource, pParams) +#define memlistControl_Epilogue(pResource, pCallContext, pParams) memlistControl_Epilogue_DISPATCH(pResource, pCallContext, pParams) +#define memlistControlLookup(pResource, pParams, ppEntry) memlistControlLookup_DISPATCH(pResource, pParams, ppEntry) #define memlistControl(pMemory, pCallContext, pParams) memlistControl_DISPATCH(pMemory, pCallContext, pParams) #define memlistUnmap(pMemory, pCallContext, pCpuMapping) memlistUnmap_DISPATCH(pMemory, pCallContext, pCpuMapping) #define memlistGetMemInterMapParams(pMemory, pParams) memlistGetMemInterMapParams_DISPATCH(pMemory, pParams) #define memlistGetMemoryMappingDescriptor(pMemory, ppMemDesc) memlistGetMemoryMappingDescriptor_DISPATCH(pMemory, ppMemDesc) -#define memlistGetMapAddrSpace(pMemory, pCallContext, mapFlags, pAddrSpace) memlistGetMapAddrSpace_DISPATCH(pMemory, pCallContext, mapFlags, pAddrSpace) -#define memlistShareCallback(pResource, pInvokingClient, pParentRef, pSharePolicy) memlistShareCallback_DISPATCH(pResource, pInvokingClient, pParentRef, pSharePolicy) #define memlistControlFilter(pResource, pCallContext, pParams) memlistControlFilter_DISPATCH(pResource, pCallContext, pParams) -#define memlistAddAdditionalDependants(pClient, pResource, pReference) memlistAddAdditionalDependants_DISPATCH(pClient, pResource, pReference) -#define memlistGetRefCount(pResource) memlistGetRefCount_DISPATCH(pResource) -#define memlistMapTo(pResource, pParams) memlistMapTo_DISPATCH(pResource, pParams) -#define memlistControl_Prologue(pResource, pCallContext, pParams) memlistControl_Prologue_DISPATCH(pResource, pCallContext, pParams) -#define memlistIsGpuMapAllowed(pMemory, pGpu) memlistIsGpuMapAllowed_DISPATCH(pMemory, pGpu) +#define memlistControlSerialization_Prologue(pResource, pCallContext, pParams) memlistControlSerialization_Prologue_DISPATCH(pResource, pCallContext, pParams) #define memlistIsReady(pMemory, bCopyConstructorContext) memlistIsReady_DISPATCH(pMemory, bCopyConstructorContext) -#define memlistCheckCopyPermissions(pMemory, pDstGpu, hDstClientNvBool) memlistCheckCopyPermissions_DISPATCH(pMemory, pDstGpu, hDstClientNvBool) +#define memlistCheckCopyPermissions(pMemory, pDstGpu, pDstDevice) memlistCheckCopyPermissions_DISPATCH(pMemory, pDstGpu, pDstDevice) #define memlistPreDestruct(pResource) memlistPreDestruct_DISPATCH(pResource) #define memlistIsDuplicate(pMemory, hMemory, pDuplicate) memlistIsDuplicate_DISPATCH(pMemory, hMemory, pDuplicate) -#define memlistUnmapFrom(pResource, pParams) memlistUnmapFrom_DISPATCH(pResource, pParams) -#define memlistControl_Epilogue(pResource, pCallContext, pParams) memlistControl_Epilogue_DISPATCH(pResource, pCallContext, pParams) -#define memlistControlLookup(pResource, pParams, ppEntry) memlistControlLookup_DISPATCH(pResource, pParams, ppEntry) +#define memlistControlSerialization_Epilogue(pResource, pCallContext, pParams) memlistControlSerialization_Epilogue_DISPATCH(pResource, pCallContext, pParams) #define memlistMap(pMemory, pCallContext, pParams, pCpuMapping) memlistMap_DISPATCH(pMemory, pCallContext, pParams, pCpuMapping) #define memlistAccessCallback(pResource, pInvokingClient, pAllocParams, accessRight) memlistAccessCallback_DISPATCH(pResource, pInvokingClient, pAllocParams, accessRight) NvBool memlistCanCopy_IMPL(struct MemoryList *pMemoryList); @@ -140,60 +144,76 @@ return pMemory->__memlistCheckMemInterUnmap__(pMemory, bSubdeviceHandleProvided); } -static inline NV_STATUS memlistControl_DISPATCH(struct MemoryList *pMemory, CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { - return pMemory->__memlistControl__(pMemory, pCallContext, pParams); +static inline NvBool memlistShareCallback_DISPATCH(struct MemoryList *pResource, struct RsClient *pInvokingClient, struct RsResourceRef *pParentRef, RS_SHARE_POLICY *pSharePolicy) { + return pResource->__memlistShareCallback__(pResource, pInvokingClient, pParentRef, pSharePolicy); } -static inline NV_STATUS memlistUnmap_DISPATCH(struct MemoryList *pMemory, CALL_CONTEXT *pCallContext, RsCpuMapping *pCpuMapping) { - return pMemory->__memlistUnmap__(pMemory, pCallContext, pCpuMapping); +static inline NV_STATUS memlistMapTo_DISPATCH(struct MemoryList *pResource, RS_RES_MAP_TO_PARAMS *pParams) { + return pResource->__memlistMapTo__(pResource, pParams); } -static inline NV_STATUS memlistGetMemInterMapParams_DISPATCH(struct MemoryList *pMemory, RMRES_MEM_INTER_MAP_PARAMS *pParams) { - return pMemory->__memlistGetMemInterMapParams__(pMemory, pParams); +static inline NV_STATUS memlistGetMapAddrSpace_DISPATCH(struct MemoryList *pMemory, CALL_CONTEXT *pCallContext, NvU32 mapFlags, NV_ADDRESS_SPACE *pAddrSpace) { + return pMemory->__memlistGetMapAddrSpace__(pMemory, pCallContext, mapFlags, pAddrSpace); } -static inline NV_STATUS memlistGetMemoryMappingDescriptor_DISPATCH(struct MemoryList *pMemory, MEMORY_DESCRIPTOR **ppMemDesc) { - return pMemory->__memlistGetMemoryMappingDescriptor__(pMemory, ppMemDesc); +static inline NvU32 memlistGetRefCount_DISPATCH(struct MemoryList *pResource) { + return pResource->__memlistGetRefCount__(pResource); } -static inline NV_STATUS memlistGetMapAddrSpace_DISPATCH(struct MemoryList *pMemory, CALL_CONTEXT *pCallContext, NvU32 mapFlags, NV_ADDRESS_SPACE *pAddrSpace) { - return pMemory->__memlistGetMapAddrSpace__(pMemory, pCallContext, mapFlags, pAddrSpace); +static inline void memlistAddAdditionalDependants_DISPATCH(struct RsClient *pClient, struct MemoryList *pResource, RsResourceRef *pReference) { + pResource->__memlistAddAdditionalDependants__(pClient, pResource, pReference); } -static inline NvBool memlistShareCallback_DISPATCH(struct MemoryList *pResource, struct RsClient *pInvokingClient, struct RsResourceRef *pParentRef, RS_SHARE_POLICY *pSharePolicy) { - return pResource->__memlistShareCallback__(pResource, pInvokingClient, pParentRef, pSharePolicy); +static inline NV_STATUS memlistControl_Prologue_DISPATCH(struct MemoryList *pResource, CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return pResource->__memlistControl_Prologue__(pResource, pCallContext, pParams); } -static inline NV_STATUS memlistControlFilter_DISPATCH(struct MemoryList *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { - return pResource->__memlistControlFilter__(pResource, pCallContext, pParams); +static inline NvBool memlistIsGpuMapAllowed_DISPATCH(struct MemoryList *pMemory, struct OBJGPU *pGpu) { + return pMemory->__memlistIsGpuMapAllowed__(pMemory, pGpu); } -static inline void memlistAddAdditionalDependants_DISPATCH(struct RsClient *pClient, struct MemoryList *pResource, RsResourceRef *pReference) { - pResource->__memlistAddAdditionalDependants__(pClient, pResource, pReference); +static inline NV_STATUS memlistUnmapFrom_DISPATCH(struct MemoryList *pResource, RS_RES_UNMAP_FROM_PARAMS *pParams) { + return pResource->__memlistUnmapFrom__(pResource, pParams); } -static inline NvU32 memlistGetRefCount_DISPATCH(struct MemoryList *pResource) { - return pResource->__memlistGetRefCount__(pResource); +static inline void memlistControl_Epilogue_DISPATCH(struct MemoryList *pResource, CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + pResource->__memlistControl_Epilogue__(pResource, pCallContext, pParams); } -static inline NV_STATUS memlistMapTo_DISPATCH(struct MemoryList *pResource, RS_RES_MAP_TO_PARAMS *pParams) { - return pResource->__memlistMapTo__(pResource, pParams); +static inline NV_STATUS memlistControlLookup_DISPATCH(struct MemoryList *pResource, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams, const struct NVOC_EXPORTED_METHOD_DEF **ppEntry) { + return pResource->__memlistControlLookup__(pResource, pParams, ppEntry); } -static inline NV_STATUS memlistControl_Prologue_DISPATCH(struct MemoryList *pResource, CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { - return pResource->__memlistControl_Prologue__(pResource, pCallContext, pParams); +static inline NV_STATUS memlistControl_DISPATCH(struct MemoryList *pMemory, CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return pMemory->__memlistControl__(pMemory, pCallContext, pParams); } -static inline NvBool memlistIsGpuMapAllowed_DISPATCH(struct MemoryList *pMemory, struct OBJGPU *pGpu) { - return pMemory->__memlistIsGpuMapAllowed__(pMemory, pGpu); +static inline NV_STATUS memlistUnmap_DISPATCH(struct MemoryList *pMemory, CALL_CONTEXT *pCallContext, RsCpuMapping *pCpuMapping) { + return pMemory->__memlistUnmap__(pMemory, pCallContext, pCpuMapping); +} + +static inline NV_STATUS memlistGetMemInterMapParams_DISPATCH(struct MemoryList *pMemory, RMRES_MEM_INTER_MAP_PARAMS *pParams) { + return pMemory->__memlistGetMemInterMapParams__(pMemory, pParams); +} + +static inline NV_STATUS memlistGetMemoryMappingDescriptor_DISPATCH(struct MemoryList *pMemory, MEMORY_DESCRIPTOR **ppMemDesc) { + return pMemory->__memlistGetMemoryMappingDescriptor__(pMemory, ppMemDesc); +} + +static inline NV_STATUS memlistControlFilter_DISPATCH(struct MemoryList *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return pResource->__memlistControlFilter__(pResource, pCallContext, pParams); +} + +static inline NV_STATUS memlistControlSerialization_Prologue_DISPATCH(struct MemoryList *pResource, CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return pResource->__memlistControlSerialization_Prologue__(pResource, pCallContext, pParams); } static inline NV_STATUS memlistIsReady_DISPATCH(struct MemoryList *pMemory, NvBool bCopyConstructorContext) { return pMemory->__memlistIsReady__(pMemory, bCopyConstructorContext); } -static inline NV_STATUS memlistCheckCopyPermissions_DISPATCH(struct MemoryList *pMemory, struct OBJGPU *pDstGpu, NvHandle hDstClientNvBool) { - return pMemory->__memlistCheckCopyPermissions__(pMemory, pDstGpu, hDstClientNvBool); +static inline NV_STATUS memlistCheckCopyPermissions_DISPATCH(struct MemoryList *pMemory, struct OBJGPU *pDstGpu, struct Device *pDstDevice) { + return pMemory->__memlistCheckCopyPermissions__(pMemory, pDstGpu, pDstDevice); } static inline void memlistPreDestruct_DISPATCH(struct MemoryList *pResource) { @@ -204,16 +224,8 @@ return pMemory->__memlistIsDuplicate__(pMemory, hMemory, pDuplicate); } -static inline NV_STATUS memlistUnmapFrom_DISPATCH(struct MemoryList *pResource, RS_RES_UNMAP_FROM_PARAMS *pParams) { - return pResource->__memlistUnmapFrom__(pResource, pParams); -} - -static inline void memlistControl_Epilogue_DISPATCH(struct MemoryList *pResource, CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { - pResource->__memlistControl_Epilogue__(pResource, pCallContext, pParams); -} - -static inline NV_STATUS memlistControlLookup_DISPATCH(struct MemoryList *pResource, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams, const struct NVOC_EXPORTED_METHOD_DEF **ppEntry) { - return pResource->__memlistControlLookup__(pResource, pParams, ppEntry); +static inline void memlistControlSerialization_Epilogue_DISPATCH(struct MemoryList *pResource, CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + pResource->__memlistControlSerialization_Epilogue__(pResource, pCallContext, pParams); } static inline NV_STATUS memlistMap_DISPATCH(struct MemoryList *pMemory, CALL_CONTEXT *pCallContext, struct RS_CPU_MAP_PARAMS *pParams, RsCpuMapping *pCpuMapping) { diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/generated/g_mem_mapper_nvoc.c nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_mem_mapper_nvoc.c --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/generated/g_mem_mapper_nvoc.c 2023-10-25 20:27:12.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_mem_mapper_nvoc.c 2024-03-05 22:18:33.000000000 +0000 @@ -97,84 +97,92 @@ return gpuresShareCallback((struct GpuResource *)(((unsigned char *)pGpuResource) + __nvoc_rtti_MemoryMapper_GpuResource.offset), pInvokingClient, pParentRef, pSharePolicy); } -static NV_STATUS __nvoc_thunk_GpuResource_memmapperControl(struct MemoryMapper *pGpuResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { - return gpuresControl((struct GpuResource *)(((unsigned char *)pGpuResource) + __nvoc_rtti_MemoryMapper_GpuResource.offset), pCallContext, pParams); +static NV_STATUS __nvoc_thunk_RmResource_memmapperCheckMemInterUnmap(struct MemoryMapper *pRmResource, NvBool bSubdeviceHandleProvided) { + return rmresCheckMemInterUnmap((struct RmResource *)(((unsigned char *)pRmResource) + __nvoc_rtti_MemoryMapper_RmResource.offset), bSubdeviceHandleProvided); } -static NV_STATUS __nvoc_thunk_GpuResource_memmapperUnmap(struct MemoryMapper *pGpuResource, struct CALL_CONTEXT *pCallContext, struct RsCpuMapping *pCpuMapping) { - return gpuresUnmap((struct GpuResource *)(((unsigned char *)pGpuResource) + __nvoc_rtti_MemoryMapper_GpuResource.offset), pCallContext, pCpuMapping); +static NV_STATUS __nvoc_thunk_RsResource_memmapperMapTo(struct MemoryMapper *pResource, RS_RES_MAP_TO_PARAMS *pParams) { + return resMapTo((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_MemoryMapper_RsResource.offset), pParams); } -static NV_STATUS __nvoc_thunk_RmResource_memmapperGetMemInterMapParams(struct MemoryMapper *pRmResource, RMRES_MEM_INTER_MAP_PARAMS *pParams) { - return rmresGetMemInterMapParams((struct RmResource *)(((unsigned char *)pRmResource) + __nvoc_rtti_MemoryMapper_RmResource.offset), pParams); +static NV_STATUS __nvoc_thunk_GpuResource_memmapperGetMapAddrSpace(struct MemoryMapper *pGpuResource, struct CALL_CONTEXT *pCallContext, NvU32 mapFlags, NV_ADDRESS_SPACE *pAddrSpace) { + return gpuresGetMapAddrSpace((struct GpuResource *)(((unsigned char *)pGpuResource) + __nvoc_rtti_MemoryMapper_GpuResource.offset), pCallContext, mapFlags, pAddrSpace); } -static NV_STATUS __nvoc_thunk_RmResource_memmapperGetMemoryMappingDescriptor(struct MemoryMapper *pRmResource, struct MEMORY_DESCRIPTOR **ppMemDesc) { - return rmresGetMemoryMappingDescriptor((struct RmResource *)(((unsigned char *)pRmResource) + __nvoc_rtti_MemoryMapper_RmResource.offset), ppMemDesc); +static NvU32 __nvoc_thunk_RsResource_memmapperGetRefCount(struct MemoryMapper *pResource) { + return resGetRefCount((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_MemoryMapper_RsResource.offset)); } -static NV_STATUS __nvoc_thunk_GpuResource_memmapperGetMapAddrSpace(struct MemoryMapper *pGpuResource, struct CALL_CONTEXT *pCallContext, NvU32 mapFlags, NV_ADDRESS_SPACE *pAddrSpace) { - return gpuresGetMapAddrSpace((struct GpuResource *)(((unsigned char *)pGpuResource) + __nvoc_rtti_MemoryMapper_GpuResource.offset), pCallContext, mapFlags, pAddrSpace); +static void __nvoc_thunk_RsResource_memmapperAddAdditionalDependants(struct RsClient *pClient, struct MemoryMapper *pResource, RsResourceRef *pReference) { + resAddAdditionalDependants(pClient, (struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_MemoryMapper_RsResource.offset), pReference); } -static NvHandle __nvoc_thunk_GpuResource_memmapperGetInternalObjectHandle(struct MemoryMapper *pGpuResource) { - return gpuresGetInternalObjectHandle((struct GpuResource *)(((unsigned char *)pGpuResource) + __nvoc_rtti_MemoryMapper_GpuResource.offset)); +static NV_STATUS __nvoc_thunk_RmResource_memmapperControl_Prologue(struct MemoryMapper *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return rmresControl_Prologue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_MemoryMapper_RmResource.offset), pCallContext, pParams); } -static NV_STATUS __nvoc_thunk_RsResource_memmapperControlFilter(struct MemoryMapper *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { - return resControlFilter((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_MemoryMapper_RsResource.offset), pCallContext, pParams); +static NV_STATUS __nvoc_thunk_GpuResource_memmapperGetRegBaseOffsetAndSize(struct MemoryMapper *pGpuResource, struct OBJGPU *pGpu, NvU32 *pOffset, NvU32 *pSize) { + return gpuresGetRegBaseOffsetAndSize((struct GpuResource *)(((unsigned char *)pGpuResource) + __nvoc_rtti_MemoryMapper_GpuResource.offset), pGpu, pOffset, pSize); } -static void __nvoc_thunk_RsResource_memmapperAddAdditionalDependants(struct RsClient *pClient, struct MemoryMapper *pResource, RsResourceRef *pReference) { - resAddAdditionalDependants(pClient, (struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_MemoryMapper_RsResource.offset), pReference); +static NV_STATUS __nvoc_thunk_GpuResource_memmapperInternalControlForward(struct MemoryMapper *pGpuResource, NvU32 command, void *pParams, NvU32 size) { + return gpuresInternalControlForward((struct GpuResource *)(((unsigned char *)pGpuResource) + __nvoc_rtti_MemoryMapper_GpuResource.offset), command, pParams, size); } -static NvU32 __nvoc_thunk_RsResource_memmapperGetRefCount(struct MemoryMapper *pResource) { - return resGetRefCount((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_MemoryMapper_RsResource.offset)); +static NV_STATUS __nvoc_thunk_RsResource_memmapperUnmapFrom(struct MemoryMapper *pResource, RS_RES_UNMAP_FROM_PARAMS *pParams) { + return resUnmapFrom((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_MemoryMapper_RsResource.offset), pParams); } -static NV_STATUS __nvoc_thunk_RmResource_memmapperCheckMemInterUnmap(struct MemoryMapper *pRmResource, NvBool bSubdeviceHandleProvided) { - return rmresCheckMemInterUnmap((struct RmResource *)(((unsigned char *)pRmResource) + __nvoc_rtti_MemoryMapper_RmResource.offset), bSubdeviceHandleProvided); +static void __nvoc_thunk_RmResource_memmapperControl_Epilogue(struct MemoryMapper *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + rmresControl_Epilogue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_MemoryMapper_RmResource.offset), pCallContext, pParams); } -static NV_STATUS __nvoc_thunk_RsResource_memmapperMapTo(struct MemoryMapper *pResource, RS_RES_MAP_TO_PARAMS *pParams) { - return resMapTo((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_MemoryMapper_RsResource.offset), pParams); +static NV_STATUS __nvoc_thunk_RsResource_memmapperControlLookup(struct MemoryMapper *pResource, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams, const struct NVOC_EXPORTED_METHOD_DEF **ppEntry) { + return resControlLookup((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_MemoryMapper_RsResource.offset), pParams, ppEntry); } -static NV_STATUS __nvoc_thunk_RmResource_memmapperControl_Prologue(struct MemoryMapper *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { - return rmresControl_Prologue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_MemoryMapper_RmResource.offset), pCallContext, pParams); +static NvHandle __nvoc_thunk_GpuResource_memmapperGetInternalObjectHandle(struct MemoryMapper *pGpuResource) { + return gpuresGetInternalObjectHandle((struct GpuResource *)(((unsigned char *)pGpuResource) + __nvoc_rtti_MemoryMapper_GpuResource.offset)); } -static NV_STATUS __nvoc_thunk_GpuResource_memmapperGetRegBaseOffsetAndSize(struct MemoryMapper *pGpuResource, struct OBJGPU *pGpu, NvU32 *pOffset, NvU32 *pSize) { - return gpuresGetRegBaseOffsetAndSize((struct GpuResource *)(((unsigned char *)pGpuResource) + __nvoc_rtti_MemoryMapper_GpuResource.offset), pGpu, pOffset, pSize); +static NV_STATUS __nvoc_thunk_GpuResource_memmapperControl(struct MemoryMapper *pGpuResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return gpuresControl((struct GpuResource *)(((unsigned char *)pGpuResource) + __nvoc_rtti_MemoryMapper_GpuResource.offset), pCallContext, pParams); } -static NvBool __nvoc_thunk_RsResource_memmapperCanCopy(struct MemoryMapper *pResource) { - return resCanCopy((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_MemoryMapper_RsResource.offset)); +static NV_STATUS __nvoc_thunk_GpuResource_memmapperUnmap(struct MemoryMapper *pGpuResource, struct CALL_CONTEXT *pCallContext, struct RsCpuMapping *pCpuMapping) { + return gpuresUnmap((struct GpuResource *)(((unsigned char *)pGpuResource) + __nvoc_rtti_MemoryMapper_GpuResource.offset), pCallContext, pCpuMapping); } -static NV_STATUS __nvoc_thunk_GpuResource_memmapperInternalControlForward(struct MemoryMapper *pGpuResource, NvU32 command, void *pParams, NvU32 size) { - return gpuresInternalControlForward((struct GpuResource *)(((unsigned char *)pGpuResource) + __nvoc_rtti_MemoryMapper_GpuResource.offset), command, pParams, size); +static NV_STATUS __nvoc_thunk_RmResource_memmapperGetMemInterMapParams(struct MemoryMapper *pRmResource, RMRES_MEM_INTER_MAP_PARAMS *pParams) { + return rmresGetMemInterMapParams((struct RmResource *)(((unsigned char *)pRmResource) + __nvoc_rtti_MemoryMapper_RmResource.offset), pParams); } -static void __nvoc_thunk_RsResource_memmapperPreDestruct(struct MemoryMapper *pResource) { - resPreDestruct((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_MemoryMapper_RsResource.offset)); +static NV_STATUS __nvoc_thunk_RmResource_memmapperGetMemoryMappingDescriptor(struct MemoryMapper *pRmResource, struct MEMORY_DESCRIPTOR **ppMemDesc) { + return rmresGetMemoryMappingDescriptor((struct RmResource *)(((unsigned char *)pRmResource) + __nvoc_rtti_MemoryMapper_RmResource.offset), ppMemDesc); } -static NV_STATUS __nvoc_thunk_RsResource_memmapperUnmapFrom(struct MemoryMapper *pResource, RS_RES_UNMAP_FROM_PARAMS *pParams) { - return resUnmapFrom((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_MemoryMapper_RsResource.offset), pParams); +static NV_STATUS __nvoc_thunk_RsResource_memmapperControlFilter(struct MemoryMapper *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return resControlFilter((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_MemoryMapper_RsResource.offset), pCallContext, pParams); } -static NV_STATUS __nvoc_thunk_RsResource_memmapperIsDuplicate(struct MemoryMapper *pResource, NvHandle hMemory, NvBool *pDuplicate) { - return resIsDuplicate((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_MemoryMapper_RsResource.offset), hMemory, pDuplicate); +static NV_STATUS __nvoc_thunk_RmResource_memmapperControlSerialization_Prologue(struct MemoryMapper *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return rmresControlSerialization_Prologue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_MemoryMapper_RmResource.offset), pCallContext, pParams); } -static void __nvoc_thunk_RmResource_memmapperControl_Epilogue(struct MemoryMapper *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { - rmresControl_Epilogue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_MemoryMapper_RmResource.offset), pCallContext, pParams); +static NvBool __nvoc_thunk_RsResource_memmapperCanCopy(struct MemoryMapper *pResource) { + return resCanCopy((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_MemoryMapper_RsResource.offset)); } -static NV_STATUS __nvoc_thunk_RsResource_memmapperControlLookup(struct MemoryMapper *pResource, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams, const struct NVOC_EXPORTED_METHOD_DEF **ppEntry) { - return resControlLookup((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_MemoryMapper_RsResource.offset), pParams, ppEntry); +static void __nvoc_thunk_RsResource_memmapperPreDestruct(struct MemoryMapper *pResource) { + resPreDestruct((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_MemoryMapper_RsResource.offset)); +} + +static NV_STATUS __nvoc_thunk_RsResource_memmapperIsDuplicate(struct MemoryMapper *pResource, NvHandle hMemory, NvBool *pDuplicate) { + return resIsDuplicate((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_MemoryMapper_RsResource.offset), hMemory, pDuplicate); +} + +static void __nvoc_thunk_RmResource_memmapperControlSerialization_Epilogue(struct MemoryMapper *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + rmresControlSerialization_Epilogue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_MemoryMapper_RmResource.offset), pCallContext, pParams); } static NV_STATUS __nvoc_thunk_GpuResource_memmapperMap(struct MemoryMapper *pGpuResource, struct CALL_CONTEXT *pCallContext, struct RS_CPU_MAP_PARAMS *pParams, struct RsCpuMapping *pCpuMapping) { @@ -253,45 +261,49 @@ pThis->__memmapperShareCallback__ = &__nvoc_thunk_GpuResource_memmapperShareCallback; - pThis->__memmapperControl__ = &__nvoc_thunk_GpuResource_memmapperControl; + pThis->__memmapperCheckMemInterUnmap__ = &__nvoc_thunk_RmResource_memmapperCheckMemInterUnmap; - pThis->__memmapperUnmap__ = &__nvoc_thunk_GpuResource_memmapperUnmap; + pThis->__memmapperMapTo__ = &__nvoc_thunk_RsResource_memmapperMapTo; - pThis->__memmapperGetMemInterMapParams__ = &__nvoc_thunk_RmResource_memmapperGetMemInterMapParams; + pThis->__memmapperGetMapAddrSpace__ = &__nvoc_thunk_GpuResource_memmapperGetMapAddrSpace; - pThis->__memmapperGetMemoryMappingDescriptor__ = &__nvoc_thunk_RmResource_memmapperGetMemoryMappingDescriptor; + pThis->__memmapperGetRefCount__ = &__nvoc_thunk_RsResource_memmapperGetRefCount; - pThis->__memmapperGetMapAddrSpace__ = &__nvoc_thunk_GpuResource_memmapperGetMapAddrSpace; + pThis->__memmapperAddAdditionalDependants__ = &__nvoc_thunk_RsResource_memmapperAddAdditionalDependants; - pThis->__memmapperGetInternalObjectHandle__ = &__nvoc_thunk_GpuResource_memmapperGetInternalObjectHandle; + pThis->__memmapperControl_Prologue__ = &__nvoc_thunk_RmResource_memmapperControl_Prologue; - pThis->__memmapperControlFilter__ = &__nvoc_thunk_RsResource_memmapperControlFilter; + pThis->__memmapperGetRegBaseOffsetAndSize__ = &__nvoc_thunk_GpuResource_memmapperGetRegBaseOffsetAndSize; - pThis->__memmapperAddAdditionalDependants__ = &__nvoc_thunk_RsResource_memmapperAddAdditionalDependants; + pThis->__memmapperInternalControlForward__ = &__nvoc_thunk_GpuResource_memmapperInternalControlForward; - pThis->__memmapperGetRefCount__ = &__nvoc_thunk_RsResource_memmapperGetRefCount; + pThis->__memmapperUnmapFrom__ = &__nvoc_thunk_RsResource_memmapperUnmapFrom; - pThis->__memmapperCheckMemInterUnmap__ = &__nvoc_thunk_RmResource_memmapperCheckMemInterUnmap; + pThis->__memmapperControl_Epilogue__ = &__nvoc_thunk_RmResource_memmapperControl_Epilogue; - pThis->__memmapperMapTo__ = &__nvoc_thunk_RsResource_memmapperMapTo; + pThis->__memmapperControlLookup__ = &__nvoc_thunk_RsResource_memmapperControlLookup; - pThis->__memmapperControl_Prologue__ = &__nvoc_thunk_RmResource_memmapperControl_Prologue; + pThis->__memmapperGetInternalObjectHandle__ = &__nvoc_thunk_GpuResource_memmapperGetInternalObjectHandle; - pThis->__memmapperGetRegBaseOffsetAndSize__ = &__nvoc_thunk_GpuResource_memmapperGetRegBaseOffsetAndSize; + pThis->__memmapperControl__ = &__nvoc_thunk_GpuResource_memmapperControl; - pThis->__memmapperCanCopy__ = &__nvoc_thunk_RsResource_memmapperCanCopy; + pThis->__memmapperUnmap__ = &__nvoc_thunk_GpuResource_memmapperUnmap; - pThis->__memmapperInternalControlForward__ = &__nvoc_thunk_GpuResource_memmapperInternalControlForward; + pThis->__memmapperGetMemInterMapParams__ = &__nvoc_thunk_RmResource_memmapperGetMemInterMapParams; - pThis->__memmapperPreDestruct__ = &__nvoc_thunk_RsResource_memmapperPreDestruct; + pThis->__memmapperGetMemoryMappingDescriptor__ = &__nvoc_thunk_RmResource_memmapperGetMemoryMappingDescriptor; - pThis->__memmapperUnmapFrom__ = &__nvoc_thunk_RsResource_memmapperUnmapFrom; + pThis->__memmapperControlFilter__ = &__nvoc_thunk_RsResource_memmapperControlFilter; - pThis->__memmapperIsDuplicate__ = &__nvoc_thunk_RsResource_memmapperIsDuplicate; + pThis->__memmapperControlSerialization_Prologue__ = &__nvoc_thunk_RmResource_memmapperControlSerialization_Prologue; - pThis->__memmapperControl_Epilogue__ = &__nvoc_thunk_RmResource_memmapperControl_Epilogue; + pThis->__memmapperCanCopy__ = &__nvoc_thunk_RsResource_memmapperCanCopy; - pThis->__memmapperControlLookup__ = &__nvoc_thunk_RsResource_memmapperControlLookup; + pThis->__memmapperPreDestruct__ = &__nvoc_thunk_RsResource_memmapperPreDestruct; + + pThis->__memmapperIsDuplicate__ = &__nvoc_thunk_RsResource_memmapperIsDuplicate; + + pThis->__memmapperControlSerialization_Epilogue__ = &__nvoc_thunk_RmResource_memmapperControlSerialization_Epilogue; pThis->__memmapperMap__ = &__nvoc_thunk_GpuResource_memmapperMap; @@ -319,13 +331,16 @@ Object *pParentObj; MemoryMapper *pThis; - pThis = portMemAllocNonPaged(sizeof(MemoryMapper)); - if (pThis == NULL) return NV_ERR_NO_MEMORY; + status = __nvoc_handleObjCreateMemAlloc(createFlags, sizeof(MemoryMapper), (void**)&pThis, (void**)ppThis); + if (status != NV_OK) + return status; portMemSet(pThis, 0, sizeof(MemoryMapper)); __nvoc_initRtti(staticCast(pThis, Dynamic), &__nvoc_class_def_MemoryMapper); + pThis->__nvoc_base_GpuResource.__nvoc_base_RmResource.__nvoc_base_RsResource.__nvoc_base_Object.createFlags = createFlags; + if (pParent != NULL && !(createFlags & NVOC_OBJ_CREATE_FLAGS_PARENT_HALSPEC_ONLY)) { pParentObj = dynamicCast(pParent, Object); @@ -341,11 +356,17 @@ if (status != NV_OK) goto __nvoc_objCreate_MemoryMapper_cleanup; *ppThis = pThis; + return NV_OK; __nvoc_objCreate_MemoryMapper_cleanup: // do not call destructors here since the constructor already called them - portMemFree(pThis); + if (createFlags & NVOC_OBJ_CREATE_FLAGS_IN_PLACE_CONSTRUCT) + portMemSet(pThis, 0, sizeof(MemoryMapper)); + else + portMemFree(pThis); + + // coverity[leaked_storage:FALSE] return status; } diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/generated/g_mem_mapper_nvoc.h nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_mem_mapper_nvoc.h --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/generated/g_mem_mapper_nvoc.h 2023-10-25 20:27:12.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_mem_mapper_nvoc.h 2024-03-05 22:18:34.000000000 +0000 @@ -86,26 +86,28 @@ struct MemoryMapper *__nvoc_pbase_MemoryMapper; NV_STATUS (*__memmapperCtrlCmdSubmitPagingOperations__)(struct MemoryMapper *, NV00FE_CTRL_SUBMIT_PAGING_OPERATIONS_PARAMS *); NvBool (*__memmapperShareCallback__)(struct MemoryMapper *, struct RsClient *, struct RsResourceRef *, RS_SHARE_POLICY *); - NV_STATUS (*__memmapperControl__)(struct MemoryMapper *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); - NV_STATUS (*__memmapperUnmap__)(struct MemoryMapper *, struct CALL_CONTEXT *, struct RsCpuMapping *); - NV_STATUS (*__memmapperGetMemInterMapParams__)(struct MemoryMapper *, RMRES_MEM_INTER_MAP_PARAMS *); - NV_STATUS (*__memmapperGetMemoryMappingDescriptor__)(struct MemoryMapper *, struct MEMORY_DESCRIPTOR **); - NV_STATUS (*__memmapperGetMapAddrSpace__)(struct MemoryMapper *, struct CALL_CONTEXT *, NvU32, NV_ADDRESS_SPACE *); - NvHandle (*__memmapperGetInternalObjectHandle__)(struct MemoryMapper *); - NV_STATUS (*__memmapperControlFilter__)(struct MemoryMapper *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); - void (*__memmapperAddAdditionalDependants__)(struct RsClient *, struct MemoryMapper *, RsResourceRef *); - NvU32 (*__memmapperGetRefCount__)(struct MemoryMapper *); NV_STATUS (*__memmapperCheckMemInterUnmap__)(struct MemoryMapper *, NvBool); NV_STATUS (*__memmapperMapTo__)(struct MemoryMapper *, RS_RES_MAP_TO_PARAMS *); + NV_STATUS (*__memmapperGetMapAddrSpace__)(struct MemoryMapper *, struct CALL_CONTEXT *, NvU32, NV_ADDRESS_SPACE *); + NvU32 (*__memmapperGetRefCount__)(struct MemoryMapper *); + void (*__memmapperAddAdditionalDependants__)(struct RsClient *, struct MemoryMapper *, RsResourceRef *); NV_STATUS (*__memmapperControl_Prologue__)(struct MemoryMapper *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); NV_STATUS (*__memmapperGetRegBaseOffsetAndSize__)(struct MemoryMapper *, struct OBJGPU *, NvU32 *, NvU32 *); - NvBool (*__memmapperCanCopy__)(struct MemoryMapper *); NV_STATUS (*__memmapperInternalControlForward__)(struct MemoryMapper *, NvU32, void *, NvU32); - void (*__memmapperPreDestruct__)(struct MemoryMapper *); NV_STATUS (*__memmapperUnmapFrom__)(struct MemoryMapper *, RS_RES_UNMAP_FROM_PARAMS *); - NV_STATUS (*__memmapperIsDuplicate__)(struct MemoryMapper *, NvHandle, NvBool *); void (*__memmapperControl_Epilogue__)(struct MemoryMapper *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); NV_STATUS (*__memmapperControlLookup__)(struct MemoryMapper *, struct RS_RES_CONTROL_PARAMS_INTERNAL *, const struct NVOC_EXPORTED_METHOD_DEF **); + NvHandle (*__memmapperGetInternalObjectHandle__)(struct MemoryMapper *); + NV_STATUS (*__memmapperControl__)(struct MemoryMapper *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); + NV_STATUS (*__memmapperUnmap__)(struct MemoryMapper *, struct CALL_CONTEXT *, struct RsCpuMapping *); + NV_STATUS (*__memmapperGetMemInterMapParams__)(struct MemoryMapper *, RMRES_MEM_INTER_MAP_PARAMS *); + NV_STATUS (*__memmapperGetMemoryMappingDescriptor__)(struct MemoryMapper *, struct MEMORY_DESCRIPTOR **); + NV_STATUS (*__memmapperControlFilter__)(struct MemoryMapper *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); + NV_STATUS (*__memmapperControlSerialization_Prologue__)(struct MemoryMapper *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); + NvBool (*__memmapperCanCopy__)(struct MemoryMapper *); + void (*__memmapperPreDestruct__)(struct MemoryMapper *); + NV_STATUS (*__memmapperIsDuplicate__)(struct MemoryMapper *, NvHandle, NvBool *); + void (*__memmapperControlSerialization_Epilogue__)(struct MemoryMapper *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); NV_STATUS (*__memmapperMap__)(struct MemoryMapper *, struct CALL_CONTEXT *, struct RS_CPU_MAP_PARAMS *, struct RsCpuMapping *); NvBool (*__memmapperAccessCallback__)(struct MemoryMapper *, struct RsClient *, void *, RsAccessRight); struct Subdevice *pSubDevice; @@ -141,26 +143,28 @@ #define memmapperCtrlCmdSubmitPagingOperations(pMemoryMapper, pParams) memmapperCtrlCmdSubmitPagingOperations_DISPATCH(pMemoryMapper, pParams) #define memmapperShareCallback(pGpuResource, pInvokingClient, pParentRef, pSharePolicy) memmapperShareCallback_DISPATCH(pGpuResource, pInvokingClient, pParentRef, pSharePolicy) -#define memmapperControl(pGpuResource, pCallContext, pParams) memmapperControl_DISPATCH(pGpuResource, pCallContext, pParams) -#define memmapperUnmap(pGpuResource, pCallContext, pCpuMapping) memmapperUnmap_DISPATCH(pGpuResource, pCallContext, pCpuMapping) -#define memmapperGetMemInterMapParams(pRmResource, pParams) memmapperGetMemInterMapParams_DISPATCH(pRmResource, pParams) -#define memmapperGetMemoryMappingDescriptor(pRmResource, ppMemDesc) memmapperGetMemoryMappingDescriptor_DISPATCH(pRmResource, ppMemDesc) -#define memmapperGetMapAddrSpace(pGpuResource, pCallContext, mapFlags, pAddrSpace) memmapperGetMapAddrSpace_DISPATCH(pGpuResource, pCallContext, mapFlags, pAddrSpace) -#define memmapperGetInternalObjectHandle(pGpuResource) memmapperGetInternalObjectHandle_DISPATCH(pGpuResource) -#define memmapperControlFilter(pResource, pCallContext, pParams) memmapperControlFilter_DISPATCH(pResource, pCallContext, pParams) -#define memmapperAddAdditionalDependants(pClient, pResource, pReference) memmapperAddAdditionalDependants_DISPATCH(pClient, pResource, pReference) -#define memmapperGetRefCount(pResource) memmapperGetRefCount_DISPATCH(pResource) #define memmapperCheckMemInterUnmap(pRmResource, bSubdeviceHandleProvided) memmapperCheckMemInterUnmap_DISPATCH(pRmResource, bSubdeviceHandleProvided) #define memmapperMapTo(pResource, pParams) memmapperMapTo_DISPATCH(pResource, pParams) +#define memmapperGetMapAddrSpace(pGpuResource, pCallContext, mapFlags, pAddrSpace) memmapperGetMapAddrSpace_DISPATCH(pGpuResource, pCallContext, mapFlags, pAddrSpace) +#define memmapperGetRefCount(pResource) memmapperGetRefCount_DISPATCH(pResource) +#define memmapperAddAdditionalDependants(pClient, pResource, pReference) memmapperAddAdditionalDependants_DISPATCH(pClient, pResource, pReference) #define memmapperControl_Prologue(pResource, pCallContext, pParams) memmapperControl_Prologue_DISPATCH(pResource, pCallContext, pParams) #define memmapperGetRegBaseOffsetAndSize(pGpuResource, pGpu, pOffset, pSize) memmapperGetRegBaseOffsetAndSize_DISPATCH(pGpuResource, pGpu, pOffset, pSize) -#define memmapperCanCopy(pResource) memmapperCanCopy_DISPATCH(pResource) #define memmapperInternalControlForward(pGpuResource, command, pParams, size) memmapperInternalControlForward_DISPATCH(pGpuResource, command, pParams, size) -#define memmapperPreDestruct(pResource) memmapperPreDestruct_DISPATCH(pResource) #define memmapperUnmapFrom(pResource, pParams) memmapperUnmapFrom_DISPATCH(pResource, pParams) -#define memmapperIsDuplicate(pResource, hMemory, pDuplicate) memmapperIsDuplicate_DISPATCH(pResource, hMemory, pDuplicate) #define memmapperControl_Epilogue(pResource, pCallContext, pParams) memmapperControl_Epilogue_DISPATCH(pResource, pCallContext, pParams) #define memmapperControlLookup(pResource, pParams, ppEntry) memmapperControlLookup_DISPATCH(pResource, pParams, ppEntry) +#define memmapperGetInternalObjectHandle(pGpuResource) memmapperGetInternalObjectHandle_DISPATCH(pGpuResource) +#define memmapperControl(pGpuResource, pCallContext, pParams) memmapperControl_DISPATCH(pGpuResource, pCallContext, pParams) +#define memmapperUnmap(pGpuResource, pCallContext, pCpuMapping) memmapperUnmap_DISPATCH(pGpuResource, pCallContext, pCpuMapping) +#define memmapperGetMemInterMapParams(pRmResource, pParams) memmapperGetMemInterMapParams_DISPATCH(pRmResource, pParams) +#define memmapperGetMemoryMappingDescriptor(pRmResource, ppMemDesc) memmapperGetMemoryMappingDescriptor_DISPATCH(pRmResource, ppMemDesc) +#define memmapperControlFilter(pResource, pCallContext, pParams) memmapperControlFilter_DISPATCH(pResource, pCallContext, pParams) +#define memmapperControlSerialization_Prologue(pResource, pCallContext, pParams) memmapperControlSerialization_Prologue_DISPATCH(pResource, pCallContext, pParams) +#define memmapperCanCopy(pResource) memmapperCanCopy_DISPATCH(pResource) +#define memmapperPreDestruct(pResource) memmapperPreDestruct_DISPATCH(pResource) +#define memmapperIsDuplicate(pResource, hMemory, pDuplicate) memmapperIsDuplicate_DISPATCH(pResource, hMemory, pDuplicate) +#define memmapperControlSerialization_Epilogue(pResource, pCallContext, pParams) memmapperControlSerialization_Epilogue_DISPATCH(pResource, pCallContext, pParams) #define memmapperMap(pGpuResource, pCallContext, pParams, pCpuMapping) memmapperMap_DISPATCH(pGpuResource, pCallContext, pParams, pCpuMapping) #define memmapperAccessCallback(pResource, pInvokingClient, pAllocParams, accessRight) memmapperAccessCallback_DISPATCH(pResource, pInvokingClient, pAllocParams, accessRight) NV_STATUS memmapperCtrlCmdSubmitPagingOperations_IMPL(struct MemoryMapper *pMemoryMapper, NV00FE_CTRL_SUBMIT_PAGING_OPERATIONS_PARAMS *pParams); @@ -173,84 +177,92 @@ return pGpuResource->__memmapperShareCallback__(pGpuResource, pInvokingClient, pParentRef, pSharePolicy); } -static inline NV_STATUS memmapperControl_DISPATCH(struct MemoryMapper *pGpuResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { - return pGpuResource->__memmapperControl__(pGpuResource, pCallContext, pParams); +static inline NV_STATUS memmapperCheckMemInterUnmap_DISPATCH(struct MemoryMapper *pRmResource, NvBool bSubdeviceHandleProvided) { + return pRmResource->__memmapperCheckMemInterUnmap__(pRmResource, bSubdeviceHandleProvided); } -static inline NV_STATUS memmapperUnmap_DISPATCH(struct MemoryMapper *pGpuResource, struct CALL_CONTEXT *pCallContext, struct RsCpuMapping *pCpuMapping) { - return pGpuResource->__memmapperUnmap__(pGpuResource, pCallContext, pCpuMapping); +static inline NV_STATUS memmapperMapTo_DISPATCH(struct MemoryMapper *pResource, RS_RES_MAP_TO_PARAMS *pParams) { + return pResource->__memmapperMapTo__(pResource, pParams); } -static inline NV_STATUS memmapperGetMemInterMapParams_DISPATCH(struct MemoryMapper *pRmResource, RMRES_MEM_INTER_MAP_PARAMS *pParams) { - return pRmResource->__memmapperGetMemInterMapParams__(pRmResource, pParams); +static inline NV_STATUS memmapperGetMapAddrSpace_DISPATCH(struct MemoryMapper *pGpuResource, struct CALL_CONTEXT *pCallContext, NvU32 mapFlags, NV_ADDRESS_SPACE *pAddrSpace) { + return pGpuResource->__memmapperGetMapAddrSpace__(pGpuResource, pCallContext, mapFlags, pAddrSpace); } -static inline NV_STATUS memmapperGetMemoryMappingDescriptor_DISPATCH(struct MemoryMapper *pRmResource, struct MEMORY_DESCRIPTOR **ppMemDesc) { - return pRmResource->__memmapperGetMemoryMappingDescriptor__(pRmResource, ppMemDesc); +static inline NvU32 memmapperGetRefCount_DISPATCH(struct MemoryMapper *pResource) { + return pResource->__memmapperGetRefCount__(pResource); } -static inline NV_STATUS memmapperGetMapAddrSpace_DISPATCH(struct MemoryMapper *pGpuResource, struct CALL_CONTEXT *pCallContext, NvU32 mapFlags, NV_ADDRESS_SPACE *pAddrSpace) { - return pGpuResource->__memmapperGetMapAddrSpace__(pGpuResource, pCallContext, mapFlags, pAddrSpace); +static inline void memmapperAddAdditionalDependants_DISPATCH(struct RsClient *pClient, struct MemoryMapper *pResource, RsResourceRef *pReference) { + pResource->__memmapperAddAdditionalDependants__(pClient, pResource, pReference); } -static inline NvHandle memmapperGetInternalObjectHandle_DISPATCH(struct MemoryMapper *pGpuResource) { - return pGpuResource->__memmapperGetInternalObjectHandle__(pGpuResource); +static inline NV_STATUS memmapperControl_Prologue_DISPATCH(struct MemoryMapper *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return pResource->__memmapperControl_Prologue__(pResource, pCallContext, pParams); } -static inline NV_STATUS memmapperControlFilter_DISPATCH(struct MemoryMapper *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { - return pResource->__memmapperControlFilter__(pResource, pCallContext, pParams); +static inline NV_STATUS memmapperGetRegBaseOffsetAndSize_DISPATCH(struct MemoryMapper *pGpuResource, struct OBJGPU *pGpu, NvU32 *pOffset, NvU32 *pSize) { + return pGpuResource->__memmapperGetRegBaseOffsetAndSize__(pGpuResource, pGpu, pOffset, pSize); } -static inline void memmapperAddAdditionalDependants_DISPATCH(struct RsClient *pClient, struct MemoryMapper *pResource, RsResourceRef *pReference) { - pResource->__memmapperAddAdditionalDependants__(pClient, pResource, pReference); +static inline NV_STATUS memmapperInternalControlForward_DISPATCH(struct MemoryMapper *pGpuResource, NvU32 command, void *pParams, NvU32 size) { + return pGpuResource->__memmapperInternalControlForward__(pGpuResource, command, pParams, size); } -static inline NvU32 memmapperGetRefCount_DISPATCH(struct MemoryMapper *pResource) { - return pResource->__memmapperGetRefCount__(pResource); +static inline NV_STATUS memmapperUnmapFrom_DISPATCH(struct MemoryMapper *pResource, RS_RES_UNMAP_FROM_PARAMS *pParams) { + return pResource->__memmapperUnmapFrom__(pResource, pParams); } -static inline NV_STATUS memmapperCheckMemInterUnmap_DISPATCH(struct MemoryMapper *pRmResource, NvBool bSubdeviceHandleProvided) { - return pRmResource->__memmapperCheckMemInterUnmap__(pRmResource, bSubdeviceHandleProvided); +static inline void memmapperControl_Epilogue_DISPATCH(struct MemoryMapper *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + pResource->__memmapperControl_Epilogue__(pResource, pCallContext, pParams); } -static inline NV_STATUS memmapperMapTo_DISPATCH(struct MemoryMapper *pResource, RS_RES_MAP_TO_PARAMS *pParams) { - return pResource->__memmapperMapTo__(pResource, pParams); +static inline NV_STATUS memmapperControlLookup_DISPATCH(struct MemoryMapper *pResource, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams, const struct NVOC_EXPORTED_METHOD_DEF **ppEntry) { + return pResource->__memmapperControlLookup__(pResource, pParams, ppEntry); } -static inline NV_STATUS memmapperControl_Prologue_DISPATCH(struct MemoryMapper *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { - return pResource->__memmapperControl_Prologue__(pResource, pCallContext, pParams); +static inline NvHandle memmapperGetInternalObjectHandle_DISPATCH(struct MemoryMapper *pGpuResource) { + return pGpuResource->__memmapperGetInternalObjectHandle__(pGpuResource); } -static inline NV_STATUS memmapperGetRegBaseOffsetAndSize_DISPATCH(struct MemoryMapper *pGpuResource, struct OBJGPU *pGpu, NvU32 *pOffset, NvU32 *pSize) { - return pGpuResource->__memmapperGetRegBaseOffsetAndSize__(pGpuResource, pGpu, pOffset, pSize); +static inline NV_STATUS memmapperControl_DISPATCH(struct MemoryMapper *pGpuResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return pGpuResource->__memmapperControl__(pGpuResource, pCallContext, pParams); } -static inline NvBool memmapperCanCopy_DISPATCH(struct MemoryMapper *pResource) { - return pResource->__memmapperCanCopy__(pResource); +static inline NV_STATUS memmapperUnmap_DISPATCH(struct MemoryMapper *pGpuResource, struct CALL_CONTEXT *pCallContext, struct RsCpuMapping *pCpuMapping) { + return pGpuResource->__memmapperUnmap__(pGpuResource, pCallContext, pCpuMapping); } -static inline NV_STATUS memmapperInternalControlForward_DISPATCH(struct MemoryMapper *pGpuResource, NvU32 command, void *pParams, NvU32 size) { - return pGpuResource->__memmapperInternalControlForward__(pGpuResource, command, pParams, size); +static inline NV_STATUS memmapperGetMemInterMapParams_DISPATCH(struct MemoryMapper *pRmResource, RMRES_MEM_INTER_MAP_PARAMS *pParams) { + return pRmResource->__memmapperGetMemInterMapParams__(pRmResource, pParams); } -static inline void memmapperPreDestruct_DISPATCH(struct MemoryMapper *pResource) { - pResource->__memmapperPreDestruct__(pResource); +static inline NV_STATUS memmapperGetMemoryMappingDescriptor_DISPATCH(struct MemoryMapper *pRmResource, struct MEMORY_DESCRIPTOR **ppMemDesc) { + return pRmResource->__memmapperGetMemoryMappingDescriptor__(pRmResource, ppMemDesc); } -static inline NV_STATUS memmapperUnmapFrom_DISPATCH(struct MemoryMapper *pResource, RS_RES_UNMAP_FROM_PARAMS *pParams) { - return pResource->__memmapperUnmapFrom__(pResource, pParams); +static inline NV_STATUS memmapperControlFilter_DISPATCH(struct MemoryMapper *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return pResource->__memmapperControlFilter__(pResource, pCallContext, pParams); } -static inline NV_STATUS memmapperIsDuplicate_DISPATCH(struct MemoryMapper *pResource, NvHandle hMemory, NvBool *pDuplicate) { - return pResource->__memmapperIsDuplicate__(pResource, hMemory, pDuplicate); +static inline NV_STATUS memmapperControlSerialization_Prologue_DISPATCH(struct MemoryMapper *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return pResource->__memmapperControlSerialization_Prologue__(pResource, pCallContext, pParams); } -static inline void memmapperControl_Epilogue_DISPATCH(struct MemoryMapper *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { - pResource->__memmapperControl_Epilogue__(pResource, pCallContext, pParams); +static inline NvBool memmapperCanCopy_DISPATCH(struct MemoryMapper *pResource) { + return pResource->__memmapperCanCopy__(pResource); } -static inline NV_STATUS memmapperControlLookup_DISPATCH(struct MemoryMapper *pResource, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams, const struct NVOC_EXPORTED_METHOD_DEF **ppEntry) { - return pResource->__memmapperControlLookup__(pResource, pParams, ppEntry); +static inline void memmapperPreDestruct_DISPATCH(struct MemoryMapper *pResource) { + pResource->__memmapperPreDestruct__(pResource); +} + +static inline NV_STATUS memmapperIsDuplicate_DISPATCH(struct MemoryMapper *pResource, NvHandle hMemory, NvBool *pDuplicate) { + return pResource->__memmapperIsDuplicate__(pResource, hMemory, pDuplicate); +} + +static inline void memmapperControlSerialization_Epilogue_DISPATCH(struct MemoryMapper *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + pResource->__memmapperControlSerialization_Epilogue__(pResource, pCallContext, pParams); } static inline NV_STATUS memmapperMap_DISPATCH(struct MemoryMapper *pGpuResource, struct CALL_CONTEXT *pCallContext, struct RS_CPU_MAP_PARAMS *pParams, struct RsCpuMapping *pCpuMapping) { diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/generated/g_mem_mgr_nvoc.c nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_mem_mgr_nvoc.c --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/generated/g_mem_mgr_nvoc.c 2023-10-25 20:27:12.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_mem_mgr_nvoc.c 2024-03-05 22:18:34.000000000 +0000 @@ -82,6 +82,10 @@ return memmgrStateLoad(pGpu, (struct MemoryManager *)(((unsigned char *)pMemoryManager) - __nvoc_rtti_MemoryManager_OBJENGSTATE.offset), arg0); } +static NV_STATUS __nvoc_thunk_MemoryManager_engstateStatePostLoad(OBJGPU *pGpu, struct OBJENGSTATE *pMemoryManager, NvU32 arg0) { + return memmgrStatePostLoad(pGpu, (struct MemoryManager *)(((unsigned char *)pMemoryManager) - __nvoc_rtti_MemoryManager_OBJENGSTATE.offset), arg0); +} + static NV_STATUS __nvoc_thunk_MemoryManager_engstateStatePreUnload(OBJGPU *pGpu, struct OBJENGSTATE *pMemoryManager, NvU32 arg0) { return memmgrStatePreUnload(pGpu, (struct MemoryManager *)(((unsigned char *)pMemoryManager) - __nvoc_rtti_MemoryManager_OBJENGSTATE.offset), arg0); } @@ -94,10 +98,6 @@ memmgrStateDestroy(pGpu, (struct MemoryManager *)(((unsigned char *)pMemoryManager) - __nvoc_rtti_MemoryManager_OBJENGSTATE.offset)); } -static NV_STATUS __nvoc_thunk_OBJENGSTATE_memmgrReconcileTunableState(POBJGPU pGpu, struct MemoryManager *pEngstate, void *pTunableState) { - return engstateReconcileTunableState(pGpu, (struct OBJENGSTATE *)(((unsigned char *)pEngstate) + __nvoc_rtti_MemoryManager_OBJENGSTATE.offset), pTunableState); -} - static NV_STATUS __nvoc_thunk_OBJENGSTATE_memmgrStatePreLoad(POBJGPU pGpu, struct MemoryManager *pEngstate, NvU32 arg0) { return engstateStatePreLoad(pGpu, (struct OBJENGSTATE *)(((unsigned char *)pEngstate) + __nvoc_rtti_MemoryManager_OBJENGSTATE.offset), arg0); } @@ -118,30 +118,6 @@ return engstateStatePreInitUnlocked(pGpu, (struct OBJENGSTATE *)(((unsigned char *)pEngstate) + __nvoc_rtti_MemoryManager_OBJENGSTATE.offset)); } -static NV_STATUS __nvoc_thunk_OBJENGSTATE_memmgrGetTunableState(POBJGPU pGpu, struct MemoryManager *pEngstate, void *pTunableState) { - return engstateGetTunableState(pGpu, (struct OBJENGSTATE *)(((unsigned char *)pEngstate) + __nvoc_rtti_MemoryManager_OBJENGSTATE.offset), pTunableState); -} - -static NV_STATUS __nvoc_thunk_OBJENGSTATE_memmgrCompareTunableState(POBJGPU pGpu, struct MemoryManager *pEngstate, void *pTunables1, void *pTunables2) { - return engstateCompareTunableState(pGpu, (struct OBJENGSTATE *)(((unsigned char *)pEngstate) + __nvoc_rtti_MemoryManager_OBJENGSTATE.offset), pTunables1, pTunables2); -} - -static void __nvoc_thunk_OBJENGSTATE_memmgrFreeTunableState(POBJGPU pGpu, struct MemoryManager *pEngstate, void *pTunableState) { - engstateFreeTunableState(pGpu, (struct OBJENGSTATE *)(((unsigned char *)pEngstate) + __nvoc_rtti_MemoryManager_OBJENGSTATE.offset), pTunableState); -} - -static NV_STATUS __nvoc_thunk_OBJENGSTATE_memmgrStatePostLoad(POBJGPU pGpu, struct MemoryManager *pEngstate, NvU32 arg0) { - return engstateStatePostLoad(pGpu, (struct OBJENGSTATE *)(((unsigned char *)pEngstate) + __nvoc_rtti_MemoryManager_OBJENGSTATE.offset), arg0); -} - -static NV_STATUS __nvoc_thunk_OBJENGSTATE_memmgrAllocTunableState(POBJGPU pGpu, struct MemoryManager *pEngstate, void **ppTunableState) { - return engstateAllocTunableState(pGpu, (struct OBJENGSTATE *)(((unsigned char *)pEngstate) + __nvoc_rtti_MemoryManager_OBJENGSTATE.offset), ppTunableState); -} - -static NV_STATUS __nvoc_thunk_OBJENGSTATE_memmgrSetTunableState(POBJGPU pGpu, struct MemoryManager *pEngstate, void *pTunableState) { - return engstateSetTunableState(pGpu, (struct OBJENGSTATE *)(((unsigned char *)pEngstate) + __nvoc_rtti_MemoryManager_OBJENGSTATE.offset), pTunableState); -} - static NvBool __nvoc_thunk_OBJENGSTATE_memmgrIsPresent(POBJGPU pGpu, struct MemoryManager *pEngstate) { return engstateIsPresent(pGpu, (struct OBJENGSTATE *)(((unsigned char *)pEngstate) + __nvoc_rtti_MemoryManager_OBJENGSTATE.offset)); } @@ -237,6 +213,8 @@ pThis->bVgpuPmaSupport = ((NvBool)(0 != 0)); } + pThis->bScrubChannelSetupInProgress = ((NvBool)(0 != 0)); + pThis->bEnableDynamicGranularityPageArrays = ((NvBool)(0 != 0)); // Hal field -- bAllowNoncontiguousAllocation @@ -245,6 +223,17 @@ pThis->bAllowNoncontiguousAllocation = ((NvBool)(0 == 0)); } + // Hal field -- bLocalEgmSupported + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ + { + pThis->bLocalEgmSupported = ((NvBool)(0 == 0)); + } + // default + else + { + pThis->bLocalEgmSupported = ((NvBool)(0 != 0)); + } + // Hal field -- bScrubOnFreeEnabled if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x11f0ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 | GH100 */ { @@ -262,6 +251,22 @@ pThis->bFastScrubberEnabled = ((NvBool)(0 != 0)); } + // Hal field -- bMonitoredFenceSupported + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x11f0ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 | GH100 */ + { + pThis->bMonitoredFenceSupported = ((NvBool)(0 == 0)); + } + + // Hal field -- b64BitSemaphoresSupported + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x11f0f800UL) )) /* ChipHal: GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 | GH100 */ + { + pThis->b64BitSemaphoresSupported = ((NvBool)(0 == 0)); + } + else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x000007e0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 */ + { + pThis->b64BitSemaphoresSupported = ((NvBool)(0 != 0)); + } + // Hal field -- bGenericKindSupport if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x11f0ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 | GH100 */ { @@ -303,18 +308,31 @@ pThis->__memmgrStateLoad__ = &memmgrStateLoad_IMPL; + pThis->__memmgrStatePostLoad__ = &memmgrStatePostLoad_IMPL; + pThis->__memmgrStatePreUnload__ = &memmgrStatePreUnload_IMPL; pThis->__memmgrStateUnload__ = &memmgrStateUnload_IMPL; pThis->__memmgrStateDestroy__ = &memmgrStateDestroy_IMPL; + // Hal function -- memmgrMemUtilsSec2CtxInit + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ + { + pThis->__memmgrMemUtilsSec2CtxInit__ = &memmgrMemUtilsSec2CtxInit_GH100; + } + // default + else + { + pThis->__memmgrMemUtilsSec2CtxInit__ = &memmgrMemUtilsSec2CtxInit_46f6a7; + } + // Hal function -- memmgrMemUtilsCheckMemoryFastScrubEnable if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ { pThis->__memmgrMemUtilsCheckMemoryFastScrubEnable__ = &memmgrMemUtilsCheckMemoryFastScrubEnable_GH100; } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x01f0ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 */ + else { pThis->__memmgrMemUtilsCheckMemoryFastScrubEnable__ = &memmgrMemUtilsCheckMemoryFastScrubEnable_491d52; } @@ -324,7 +342,7 @@ { pThis->__memmgrAllocDetermineAlignment__ = &memmgrAllocDetermineAlignment_GM107; } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x11f0fc00UL) )) /* ChipHal: GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 | GH100 */ + else { pThis->__memmgrAllocDetermineAlignment__ = &memmgrAllocDetermineAlignment_GA100; } @@ -334,63 +352,74 @@ { pThis->__memmgrGetMaxContextSize__ = &memmgrGetMaxContextSize_TU102; } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x1000fc00UL) )) /* ChipHal: GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | GH100 */ - { - pThis->__memmgrGetMaxContextSize__ = &memmgrGetMaxContextSize_GA100; - } else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x01f00000UL) )) /* ChipHal: AD102 | AD103 | AD104 | AD106 | AD107 */ { pThis->__memmgrGetMaxContextSize__ = &memmgrGetMaxContextSize_AD102; } + else + { + pThis->__memmgrGetMaxContextSize__ = &memmgrGetMaxContextSize_GA100; + } // Hal function -- memmgrScrubRegistryOverrides if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x000003e0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 */ { pThis->__memmgrScrubRegistryOverrides__ = &memmgrScrubRegistryOverrides_GM107; } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x11f0fc00UL) )) /* ChipHal: GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 | GH100 */ + else { pThis->__memmgrScrubRegistryOverrides__ = &memmgrScrubRegistryOverrides_GA100; } // Hal function -- memmgrGetPteKindBl - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x01f0ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 */ + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ { - pThis->__memmgrGetPteKindBl__ = &memmgrGetPteKindBl_GM107; + pThis->__memmgrGetPteKindBl__ = &memmgrGetPteKindBl_474d46; } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ + else { - pThis->__memmgrGetPteKindBl__ = &memmgrGetPteKindBl_474d46; + pThis->__memmgrGetPteKindBl__ = &memmgrGetPteKindBl_GM107; } // Hal function -- memmgrGetPteKindPitch - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x01f0ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 */ + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ { - pThis->__memmgrGetPteKindPitch__ = &memmgrGetPteKindPitch_GM107; + pThis->__memmgrGetPteKindPitch__ = &memmgrGetPteKindPitch_474d46; } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ + else { - pThis->__memmgrGetPteKindPitch__ = &memmgrGetPteKindPitch_474d46; + pThis->__memmgrGetPteKindPitch__ = &memmgrGetPteKindPitch_GM107; } // Hal function -- memmgrChooseKindCompressC - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x01f0ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 */ + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ { - pThis->__memmgrChooseKindCompressC__ = &memmgrChooseKindCompressC_GP100; + pThis->__memmgrChooseKindCompressC__ = &memmgrChooseKindCompressC_474d46; } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ + else { - pThis->__memmgrChooseKindCompressC__ = &memmgrChooseKindCompressC_474d46; + pThis->__memmgrChooseKindCompressC__ = &memmgrChooseKindCompressC_GP100; } // Hal function -- memmgrGetFlaKind - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x11f0fc00UL) )) /* ChipHal: GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 | GH100 */ + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x000003e0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 */ + { + pThis->__memmgrGetFlaKind__ = &memmgrGetFlaKind_46f6a7; + } + else { pThis->__memmgrGetFlaKind__ = &memmgrGetFlaKind_GA100; } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x000003e0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 */ + + // Hal function -- memmgrIsApertureSupportedByFla + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x11f0fc00UL) )) /* ChipHal: GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 | GH100 */ { - pThis->__memmgrGetFlaKind__ = &memmgrGetFlaKind_46f6a7; + pThis->__memmgrIsApertureSupportedByFla__ = &memmgrIsApertureSupportedByFla_GA100; + } + // default + else + { + pThis->__memmgrIsApertureSupportedByFla__ = &memmgrIsApertureSupportedByFla_46f6a7; } // Hal function -- memmgrDetermineComptag @@ -398,7 +427,7 @@ { pThis->__memmgrDetermineComptag__ = &memmgrDetermineComptag_TU102; } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x11f0fc00UL) )) /* ChipHal: GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 | GH100 */ + else { pThis->__memmgrDetermineComptag__ = &memmgrDetermineComptag_13cd8d; } @@ -419,7 +448,7 @@ { pThis->__memmgrReadMmuLock__ = &memmgrReadMmuLock_GA100; } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x11f0fbe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 | GH100 */ + else { pThis->__memmgrReadMmuLock__ = &memmgrReadMmuLock_e133c0; } @@ -429,7 +458,7 @@ { pThis->__memmgrBlockMemLockedMemory__ = &memmgrBlockMemLockedMemory_GA100; } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x11f0fbe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 | GH100 */ + else { pThis->__memmgrBlockMemLockedMemory__ = &memmgrBlockMemLockedMemory_56cd7a; } @@ -439,19 +468,19 @@ { pThis->__memmgrInsertUnprotectedRegionAtBottomOfFb__ = &memmgrInsertUnprotectedRegionAtBottomOfFb_GA100; } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x11f0fbe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 | GH100 */ + else { pThis->__memmgrInsertUnprotectedRegionAtBottomOfFb__ = &memmgrInsertUnprotectedRegionAtBottomOfFb_56cd7a; } // Hal function -- memmgrGetDisablePlcKind - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x11f0fc00UL) )) /* ChipHal: GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 | GH100 */ + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x000003e0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 */ { - pThis->__memmgrGetDisablePlcKind__ = &memmgrGetDisablePlcKind_GA100; + pThis->__memmgrGetDisablePlcKind__ = &memmgrGetDisablePlcKind_b3696a; } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x000003e0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 */ + else { - pThis->__memmgrGetDisablePlcKind__ = &memmgrGetDisablePlcKind_b3696a; + pThis->__memmgrGetDisablePlcKind__ = &memmgrGetDisablePlcKind_GA100; } // Hal function -- memmgrEnableDynamicPageOfflining @@ -459,21 +488,21 @@ { pThis->__memmgrEnableDynamicPageOfflining__ = &memmgrEnableDynamicPageOfflining_GA100; } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x11f0f800UL) )) /* ChipHal: GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 | GH100 */ - { - pThis->__memmgrEnableDynamicPageOfflining__ = &memmgrEnableDynamicPageOfflining_GA102; - } else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x000003e0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 */ { pThis->__memmgrEnableDynamicPageOfflining__ = &memmgrEnableDynamicPageOfflining_b3696a; } + else + { + pThis->__memmgrEnableDynamicPageOfflining__ = &memmgrEnableDynamicPageOfflining_GA102; + } // Hal function -- memmgrGetBlackListPages if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x000003e0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 */ { pThis->__memmgrGetBlackListPages__ = &memmgrGetBlackListPages_GM107; } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x11f0fc00UL) )) /* ChipHal: GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 | GH100 */ + else { pThis->__memmgrGetBlackListPages__ = &memmgrGetBlackListPages_GA100; } @@ -486,14 +515,14 @@ pThis->__nvoc_base_OBJENGSTATE.__engstateStateLoad__ = &__nvoc_thunk_MemoryManager_engstateStateLoad; + pThis->__nvoc_base_OBJENGSTATE.__engstateStatePostLoad__ = &__nvoc_thunk_MemoryManager_engstateStatePostLoad; + pThis->__nvoc_base_OBJENGSTATE.__engstateStatePreUnload__ = &__nvoc_thunk_MemoryManager_engstateStatePreUnload; pThis->__nvoc_base_OBJENGSTATE.__engstateStateUnload__ = &__nvoc_thunk_MemoryManager_engstateStateUnload; pThis->__nvoc_base_OBJENGSTATE.__engstateStateDestroy__ = &__nvoc_thunk_MemoryManager_engstateStateDestroy; - pThis->__memmgrReconcileTunableState__ = &__nvoc_thunk_OBJENGSTATE_memmgrReconcileTunableState; - pThis->__memmgrStatePreLoad__ = &__nvoc_thunk_OBJENGSTATE_memmgrStatePreLoad; pThis->__memmgrStatePostUnload__ = &__nvoc_thunk_OBJENGSTATE_memmgrStatePostUnload; @@ -504,18 +533,6 @@ pThis->__memmgrStatePreInitUnlocked__ = &__nvoc_thunk_OBJENGSTATE_memmgrStatePreInitUnlocked; - pThis->__memmgrGetTunableState__ = &__nvoc_thunk_OBJENGSTATE_memmgrGetTunableState; - - pThis->__memmgrCompareTunableState__ = &__nvoc_thunk_OBJENGSTATE_memmgrCompareTunableState; - - pThis->__memmgrFreeTunableState__ = &__nvoc_thunk_OBJENGSTATE_memmgrFreeTunableState; - - pThis->__memmgrStatePostLoad__ = &__nvoc_thunk_OBJENGSTATE_memmgrStatePostLoad; - - pThis->__memmgrAllocTunableState__ = &__nvoc_thunk_OBJENGSTATE_memmgrAllocTunableState; - - pThis->__memmgrSetTunableState__ = &__nvoc_thunk_OBJENGSTATE_memmgrSetTunableState; - pThis->__memmgrIsPresent__ = &__nvoc_thunk_OBJENGSTATE_memmgrIsPresent; } @@ -538,13 +555,16 @@ MemoryManager *pThis; RmHalspecOwner *pRmhalspecowner; - pThis = portMemAllocNonPaged(sizeof(MemoryManager)); - if (pThis == NULL) return NV_ERR_NO_MEMORY; + status = __nvoc_handleObjCreateMemAlloc(createFlags, sizeof(MemoryManager), (void**)&pThis, (void**)ppThis); + if (status != NV_OK) + return status; portMemSet(pThis, 0, sizeof(MemoryManager)); __nvoc_initRtti(staticCast(pThis, Dynamic), &__nvoc_class_def_MemoryManager); + pThis->__nvoc_base_OBJENGSTATE.__nvoc_base_Object.createFlags = createFlags; + if (pParent != NULL && !(createFlags & NVOC_OBJ_CREATE_FLAGS_PARENT_HALSPEC_ONLY)) { pParentObj = dynamicCast(pParent, Object); @@ -564,11 +584,17 @@ if (status != NV_OK) goto __nvoc_objCreate_MemoryManager_cleanup; *ppThis = pThis; + return NV_OK; __nvoc_objCreate_MemoryManager_cleanup: // do not call destructors here since the constructor already called them - portMemFree(pThis); + if (createFlags & NVOC_OBJ_CREATE_FLAGS_IN_PLACE_CONSTRUCT) + portMemSet(pThis, 0, sizeof(MemoryManager)); + else + portMemFree(pThis); + + // coverity[leaked_storage:FALSE] return status; } diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/generated/g_mem_mgr_nvoc.h nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_mem_mgr_nvoc.h --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/generated/g_mem_mgr_nvoc.h 2023-10-25 20:27:12.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_mem_mgr_nvoc.h 2024-03-05 22:18:34.000000000 +0000 @@ -7,7 +7,7 @@ #endif /* - * SPDX-FileCopyrightText: Copyright (c) 1993-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 1993-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -52,6 +52,19 @@ #include "gpu/mem_mgr/phys_mem_allocator/phys_mem_allocator.h" +struct CeUtils; + +#ifndef __NVOC_CLASS_CeUtils_TYPEDEF__ +#define __NVOC_CLASS_CeUtils_TYPEDEF__ +typedef struct CeUtils CeUtils; +#endif /* __NVOC_CLASS_CeUtils_TYPEDEF__ */ + +#ifndef __nvoc_class_id_CeUtils +#define __nvoc_class_id_CeUtils 0x8b8bae +#endif /* __nvoc_class_id_CeUtils */ + + + typedef volatile struct _cl906f_tag1 Nv906fControl; typedef struct KERNEL_MIG_GPU_INSTANCE KERNEL_MIG_GPU_INSTANCE; @@ -75,6 +88,11 @@ #define TRANSFER_FLAGS_SHADOW_INIT_MEM NVBIT32(2) // Applicable only for non-PROCESSOR transfers #define TRANSFER_FLAGS_PERSISTENT_CPU_MAPPING NVBIT32(3) // Require long lived PROCESSOR mapping #define TRANSFER_FLAGS_DESTROY_MAPPING NVBIT32(4) // Destroy any cached mappings when complete +#define TRANSFER_FLAGS_USE_BAR1 NVBIT32(5) // Use only BAR1 for PROCESSOR transfers + +// Protection flags: at most 1 may be set, none means READ_WRITE by default +#define TRANSFER_FLAGS_MAP_PROTECT_READABLE NVBIT32(6) // Transfer is only reading data +#define TRANSFER_FLAGS_MAP_PROTECT_WRITEABLE NVBIT32(7) // Transfer is only writing data typedef struct { @@ -157,9 +175,10 @@ #define MEMUTIL_SCRUB_LINE_LENGTH_ALIGNMENT (4 * 1024) typedef enum { - SCRUBBER_CHANNEL, + CE_SCRUBBER_CHANNEL, FAST_SCRUBBER_CHANNEL, COPY_CHANNEL, + SWL_SCRUBBER_CHANNEL, MAX_CHANNEL_TYPE } CHANNEL_KIND; @@ -172,7 +191,7 @@ NvHandle subdeviceId; // Subdevice Handle NvHandle errNotifierIdVirt; NvHandle errNotifierIdPhys; - NvHandle copyObjectId; + NvHandle engineObjectId; NvHandle eventId; NvHandle pushBufferId; NvHandle bitMapSemPhysId; @@ -189,6 +208,7 @@ NvU32 methodSizePerBlock; NvU32 semaOffset; NvU32 finishPayloadOffset; + NvU32 authTagBufSemaOffset; NvU32 finishPayload; NvBool isChannelSynchronized; NvBool isProgressChecked; @@ -215,6 +235,9 @@ NvU64 pbGpuVA; NvU64 pbGpuBitMapVA; NvU64 pbGpuNotifierVA; + MEMORY_DESCRIPTOR *pUserdMemdesc; + MEMORY_DESCRIPTOR *pChannelBufferMemdesc; + MEMORY_DESCRIPTOR *pErrNotifierMemdesc; NvU8 *pbCpuVA; NvU8 *pbBitMapVA; Nv906fControl *pControlGPFifo; @@ -222,6 +245,7 @@ NVOS10_EVENT_KERNEL_CALLBACK_EX callback; NvU32 state; NvU32 hTdCopyClass; + NvU32 sec2Class; NvU32 minBlockSize; NvU32 maxBlockSize; NvU32 channelPutOffset; @@ -255,7 +279,7 @@ // NvBool bManageBAR2; OBJGPU *pGpu; - struct KernelCE *pKCe; + NvU32 ceId; // Used by Partition Scrubber KERNEL_MIG_GPU_INSTANCE *pKernelMIGGpuInstance; @@ -402,9 +426,11 @@ NV_STATUS (*__memmgrStatePreInitLocked__)(OBJGPU *, struct MemoryManager *); NV_STATUS (*__memmgrStateInitLocked__)(OBJGPU *, struct MemoryManager *); NV_STATUS (*__memmgrStateLoad__)(OBJGPU *, struct MemoryManager *, NvU32); + NV_STATUS (*__memmgrStatePostLoad__)(OBJGPU *, struct MemoryManager *, NvU32); NV_STATUS (*__memmgrStatePreUnload__)(OBJGPU *, struct MemoryManager *, NvU32); NV_STATUS (*__memmgrStateUnload__)(OBJGPU *, struct MemoryManager *, NvU32); void (*__memmgrStateDestroy__)(OBJGPU *, struct MemoryManager *); + NV_STATUS (*__memmgrMemUtilsSec2CtxInit__)(OBJGPU *, struct MemoryManager *, OBJCHANNEL *); NvBool (*__memmgrMemUtilsCheckMemoryFastScrubEnable__)(OBJGPU *, struct MemoryManager *, NvU32, NvBool, RmPhysAddr, NvU32, NV_ADDRESS_SPACE); NV_STATUS (*__memmgrAllocDetermineAlignment__)(OBJGPU *, struct MemoryManager *, NvU64 *, NvU64 *, NvU64, NvU32, NvU32, NvU32, NvU64); NvU64 (*__memmgrGetMaxContextSize__)(OBJGPU *, struct MemoryManager *); @@ -413,6 +439,7 @@ NvU32 (*__memmgrGetPteKindPitch__)(OBJGPU *, struct MemoryManager *); NvU32 (*__memmgrChooseKindCompressC__)(OBJGPU *, struct MemoryManager *, FB_ALLOC_PAGE_FORMAT *); NV_STATUS (*__memmgrGetFlaKind__)(OBJGPU *, struct MemoryManager *, NvU32 *); + NvBool (*__memmgrIsApertureSupportedByFla__)(OBJGPU *, struct MemoryManager *, NV_ADDRESS_SPACE); NvU32 (*__memmgrDetermineComptag__)(OBJGPU *, struct MemoryManager *, RmPhysAddr); NV_STATUS (*__memmgrCheckReservedMemorySize__)(OBJGPU *, struct MemoryManager *); NV_STATUS (*__memmgrReadMmuLock__)(OBJGPU *, struct MemoryManager *, NvBool *, NvU64 *, NvU64 *); @@ -421,18 +448,11 @@ void (*__memmgrGetDisablePlcKind__)(struct MemoryManager *, NvU32 *); void (*__memmgrEnableDynamicPageOfflining__)(OBJGPU *, struct MemoryManager *); NV_STATUS (*__memmgrGetBlackListPages__)(OBJGPU *, struct MemoryManager *, BLACKLIST_ADDRESS *, NvU32 *); - NV_STATUS (*__memmgrReconcileTunableState__)(POBJGPU, struct MemoryManager *, void *); NV_STATUS (*__memmgrStatePreLoad__)(POBJGPU, struct MemoryManager *, NvU32); NV_STATUS (*__memmgrStatePostUnload__)(POBJGPU, struct MemoryManager *, NvU32); NV_STATUS (*__memmgrStateInitUnlocked__)(POBJGPU, struct MemoryManager *); void (*__memmgrInitMissing__)(POBJGPU, struct MemoryManager *); NV_STATUS (*__memmgrStatePreInitUnlocked__)(POBJGPU, struct MemoryManager *); - NV_STATUS (*__memmgrGetTunableState__)(POBJGPU, struct MemoryManager *, void *); - NV_STATUS (*__memmgrCompareTunableState__)(POBJGPU, struct MemoryManager *, void *, void *); - void (*__memmgrFreeTunableState__)(POBJGPU, struct MemoryManager *, void *); - NV_STATUS (*__memmgrStatePostLoad__)(POBJGPU, struct MemoryManager *, NvU32); - NV_STATUS (*__memmgrAllocTunableState__)(POBJGPU, struct MemoryManager *, void **); - NV_STATUS (*__memmgrSetTunableState__)(POBJGPU, struct MemoryManager *, void *); NvBool (*__memmgrIsPresent__)(POBJGPU, struct MemoryManager *); NvBool bFbsrWddmModeEnabled; NvBool bFbRegionsSupported; @@ -440,7 +460,6 @@ NvBool bPmaEnabled; NvBool bPmaInitialized; NvBool bPmaForcePersistence; - NvBool bPmaAddrTree; NvBool bClientPageTablesPmaManaged; NvBool bScanoutSysmem; NvBool bMixedDensityFbp; @@ -457,13 +476,20 @@ NvBool bEnableFbsrFileMode; NvBool bEnableDynamicPageOfflining; NvBool bVgpuPmaSupport; + NvBool bScrubChannelSetupInProgress; NvBool bEnableDynamicGranularityPageArrays; NvBool bAllowNoncontiguousAllocation; + NvBool bLocalEgmSupported; + NvBool bLocalEgmEnabled; + NvU32 localEgmPeerId; + NvS32 localEgmNodeId; + NvU64 localEgmBasePhysAddr; + NvU64 localEgmSize; NvBool bEccInterleavedVidmemScrub; NvBool bScrubberInitialized; NvBool bAllowSysmemHugePages; NvBool bEccScrubOverride; - NvU32 sysmemPageSize; + NvU64 sysmemPageSize; struct Heap *pHeap; NvBool bScrubOnFreeEnabled; NvBool bFastScrubberEnabled; @@ -474,6 +500,7 @@ NvU64 heapStartOffset; NvU64 rsvdMemoryBase; NvU32 rsvdMemorySize; + struct CeUtils *pCeUtils; OBJSCRUB eccScrubberState; struct __nvoc_inner_struc_MemoryManager_1__ Ram; NvU32 PteKindOverride; @@ -481,7 +508,6 @@ NvU32 zbcSurfaces; NvU64 overrideInitHeapMin; NvU64 overrideHeapMax; - NvU64 fbOverrideStartKb; NvU64 rsvdMemorySizeIncrement; struct OBJFBSR *pFbsr[8]; struct OBJFBSR *pActiveFbsr; @@ -496,6 +522,8 @@ NvHandle hDevice; NvHandle hSubdevice; NvHandle hThirdPartyP2P; + NvBool bMonitoredFenceSupported; + NvBool b64BitSemaphoresSupported; NvBool bGenericKindSupport; }; @@ -533,9 +561,12 @@ #define memmgrStatePreInitLocked(pGpu, pMemoryManager) memmgrStatePreInitLocked_DISPATCH(pGpu, pMemoryManager) #define memmgrStateInitLocked(pGpu, pMemoryManager) memmgrStateInitLocked_DISPATCH(pGpu, pMemoryManager) #define memmgrStateLoad(pGpu, pMemoryManager, arg0) memmgrStateLoad_DISPATCH(pGpu, pMemoryManager, arg0) +#define memmgrStatePostLoad(pGpu, pMemoryManager, arg0) memmgrStatePostLoad_DISPATCH(pGpu, pMemoryManager, arg0) #define memmgrStatePreUnload(pGpu, pMemoryManager, arg0) memmgrStatePreUnload_DISPATCH(pGpu, pMemoryManager, arg0) #define memmgrStateUnload(pGpu, pMemoryManager, arg0) memmgrStateUnload_DISPATCH(pGpu, pMemoryManager, arg0) #define memmgrStateDestroy(pGpu, pMemoryManager) memmgrStateDestroy_DISPATCH(pGpu, pMemoryManager) +#define memmgrMemUtilsSec2CtxInit(pGpu, pMemoryManager, arg0) memmgrMemUtilsSec2CtxInit_DISPATCH(pGpu, pMemoryManager, arg0) +#define memmgrMemUtilsSec2CtxInit_HAL(pGpu, pMemoryManager, arg0) memmgrMemUtilsSec2CtxInit_DISPATCH(pGpu, pMemoryManager, arg0) #define memmgrMemUtilsCheckMemoryFastScrubEnable(pGpu, pMemoryManager, arg0, arg1, arg2, arg3, arg4) memmgrMemUtilsCheckMemoryFastScrubEnable_DISPATCH(pGpu, pMemoryManager, arg0, arg1, arg2, arg3, arg4) #define memmgrMemUtilsCheckMemoryFastScrubEnable_HAL(pGpu, pMemoryManager, arg0, arg1, arg2, arg3, arg4) memmgrMemUtilsCheckMemoryFastScrubEnable_DISPATCH(pGpu, pMemoryManager, arg0, arg1, arg2, arg3, arg4) #define memmgrAllocDetermineAlignment(pGpu, pMemoryManager, pMemSize, pAlign, alignPad, allocFlags, retAttr, retAttr2, hwAlignment) memmgrAllocDetermineAlignment_DISPATCH(pGpu, pMemoryManager, pMemSize, pAlign, alignPad, allocFlags, retAttr, retAttr2, hwAlignment) @@ -552,6 +583,8 @@ #define memmgrChooseKindCompressC_HAL(pGpu, pMemoryManager, arg0) memmgrChooseKindCompressC_DISPATCH(pGpu, pMemoryManager, arg0) #define memmgrGetFlaKind(pGpu, pMemoryManager, arg0) memmgrGetFlaKind_DISPATCH(pGpu, pMemoryManager, arg0) #define memmgrGetFlaKind_HAL(pGpu, pMemoryManager, arg0) memmgrGetFlaKind_DISPATCH(pGpu, pMemoryManager, arg0) +#define memmgrIsApertureSupportedByFla(pGpu, pMemoryManager, arg0) memmgrIsApertureSupportedByFla_DISPATCH(pGpu, pMemoryManager, arg0) +#define memmgrIsApertureSupportedByFla_HAL(pGpu, pMemoryManager, arg0) memmgrIsApertureSupportedByFla_DISPATCH(pGpu, pMemoryManager, arg0) #define memmgrDetermineComptag(pGpu, pMemoryManager, arg0) memmgrDetermineComptag_DISPATCH(pGpu, pMemoryManager, arg0) #define memmgrDetermineComptag_HAL(pGpu, pMemoryManager, arg0) memmgrDetermineComptag_DISPATCH(pGpu, pMemoryManager, arg0) #define memmgrCheckReservedMemorySize(pGpu, pMemoryManager) memmgrCheckReservedMemorySize_DISPATCH(pGpu, pMemoryManager) @@ -568,18 +601,11 @@ #define memmgrEnableDynamicPageOfflining_HAL(pGpu, pMemoryManager) memmgrEnableDynamicPageOfflining_DISPATCH(pGpu, pMemoryManager) #define memmgrGetBlackListPages(pGpu, pMemoryManager, pBlAddrs, pCount) memmgrGetBlackListPages_DISPATCH(pGpu, pMemoryManager, pBlAddrs, pCount) #define memmgrGetBlackListPages_HAL(pGpu, pMemoryManager, pBlAddrs, pCount) memmgrGetBlackListPages_DISPATCH(pGpu, pMemoryManager, pBlAddrs, pCount) -#define memmgrReconcileTunableState(pGpu, pEngstate, pTunableState) memmgrReconcileTunableState_DISPATCH(pGpu, pEngstate, pTunableState) #define memmgrStatePreLoad(pGpu, pEngstate, arg0) memmgrStatePreLoad_DISPATCH(pGpu, pEngstate, arg0) #define memmgrStatePostUnload(pGpu, pEngstate, arg0) memmgrStatePostUnload_DISPATCH(pGpu, pEngstate, arg0) #define memmgrStateInitUnlocked(pGpu, pEngstate) memmgrStateInitUnlocked_DISPATCH(pGpu, pEngstate) #define memmgrInitMissing(pGpu, pEngstate) memmgrInitMissing_DISPATCH(pGpu, pEngstate) #define memmgrStatePreInitUnlocked(pGpu, pEngstate) memmgrStatePreInitUnlocked_DISPATCH(pGpu, pEngstate) -#define memmgrGetTunableState(pGpu, pEngstate, pTunableState) memmgrGetTunableState_DISPATCH(pGpu, pEngstate, pTunableState) -#define memmgrCompareTunableState(pGpu, pEngstate, pTunables1, pTunables2) memmgrCompareTunableState_DISPATCH(pGpu, pEngstate, pTunables1, pTunables2) -#define memmgrFreeTunableState(pGpu, pEngstate, pTunableState) memmgrFreeTunableState_DISPATCH(pGpu, pEngstate, pTunableState) -#define memmgrStatePostLoad(pGpu, pEngstate, arg0) memmgrStatePostLoad_DISPATCH(pGpu, pEngstate, arg0) -#define memmgrAllocTunableState(pGpu, pEngstate, ppTunableState) memmgrAllocTunableState_DISPATCH(pGpu, pEngstate, ppTunableState) -#define memmgrSetTunableState(pGpu, pEngstate, pTunableState) memmgrSetTunableState_DISPATCH(pGpu, pEngstate, pTunableState) #define memmgrIsPresent(pGpu, pEngstate) memmgrIsPresent_DISPATCH(pGpu, pEngstate) NV_STATUS memmgrSavePowerMgmtState_KERNEL(OBJGPU *pGpu, struct MemoryManager *pMemoryManager); @@ -609,11 +635,11 @@ #define memmgrRestorePowerMgmtState_HAL(pGpu, pMemoryManager) memmgrRestorePowerMgmtState(pGpu, pMemoryManager) -NvU32 memmgrDeterminePageSize_IMPL(struct MemoryManager *pMemoryManager, NvHandle hClient, NvU64 memSize, NvU32 memFormat, NvU32 pageFormatFlags, NvU32 *pRetAttr, NvU32 *pRetAttr2); +NvU64 memmgrDeterminePageSize_IMPL(struct MemoryManager *pMemoryManager, NvHandle hClient, NvU64 memSize, NvU32 memFormat, NvU32 pageFormatFlags, NvU32 *pRetAttr, NvU32 *pRetAttr2); #ifdef __nvoc_mem_mgr_h_disabled -static inline NvU32 memmgrDeterminePageSize(struct MemoryManager *pMemoryManager, NvHandle hClient, NvU64 memSize, NvU32 memFormat, NvU32 pageFormatFlags, NvU32 *pRetAttr, NvU32 *pRetAttr2) { +static inline NvU64 memmgrDeterminePageSize(struct MemoryManager *pMemoryManager, NvHandle hClient, NvU64 memSize, NvU32 memFormat, NvU32 pageFormatFlags, NvU32 *pRetAttr, NvU32 *pRetAttr2) { NV_ASSERT_FAILED_PRECOMP("MemoryManager was disabled!"); return 0; } @@ -1072,19 +1098,19 @@ #define memmgrFinishHandleSizeOverrides_HAL(pGpu, pMemoryManager) memmgrFinishHandleSizeOverrides(pGpu, pMemoryManager) -NV_STATUS memmgrGetBAR1InfoForClient_GM107(OBJGPU *pGpu, struct MemoryManager *pMemoryManager, NvHandle arg0, PGETBAR1INFO bar1Info); +NV_STATUS memmgrGetBAR1InfoForDevice_GM107(OBJGPU *pGpu, struct MemoryManager *pMemoryManager, struct Device *pDevice, PGETBAR1INFO bar1Info); #ifdef __nvoc_mem_mgr_h_disabled -static inline NV_STATUS memmgrGetBAR1InfoForClient(OBJGPU *pGpu, struct MemoryManager *pMemoryManager, NvHandle arg0, PGETBAR1INFO bar1Info) { +static inline NV_STATUS memmgrGetBAR1InfoForDevice(OBJGPU *pGpu, struct MemoryManager *pMemoryManager, struct Device *pDevice, PGETBAR1INFO bar1Info) { NV_ASSERT_FAILED_PRECOMP("MemoryManager was disabled!"); return NV_ERR_NOT_SUPPORTED; } #else //__nvoc_mem_mgr_h_disabled -#define memmgrGetBAR1InfoForClient(pGpu, pMemoryManager, arg0, bar1Info) memmgrGetBAR1InfoForClient_GM107(pGpu, pMemoryManager, arg0, bar1Info) +#define memmgrGetBAR1InfoForDevice(pGpu, pMemoryManager, pDevice, bar1Info) memmgrGetBAR1InfoForDevice_GM107(pGpu, pMemoryManager, pDevice, bar1Info) #endif //__nvoc_mem_mgr_h_disabled -#define memmgrGetBAR1InfoForClient_HAL(pGpu, pMemoryManager, arg0, bar1Info) memmgrGetBAR1InfoForClient(pGpu, pMemoryManager, arg0, bar1Info) +#define memmgrGetBAR1InfoForDevice_HAL(pGpu, pMemoryManager, pDevice, bar1Info) memmgrGetBAR1InfoForDevice(pGpu, pMemoryManager, pDevice, bar1Info) static inline NvU64 memmgrGetFbTaxSize_4a4dee(OBJGPU *pGpu, struct MemoryManager *pMemoryManager) { return 0; @@ -1761,23 +1787,53 @@ #define memmgrFreeFbsrMemory_HAL(pGpu, pMemoryManager) memmgrFreeFbsrMemory(pGpu, pMemoryManager) -static inline NV_STATUS memmgrCreateVgaWorkspaceMemDesc_46f6a7(OBJGPU *pGpu, struct MemoryManager *pMemoryManager) { +static inline NV_STATUS memmgrReserveVgaWorkspaceMemDescForFbsr_46f6a7(OBJGPU *pGpu, struct MemoryManager *pMemoryManager) { return NV_ERR_NOT_SUPPORTED; } -NV_STATUS memmgrCreateVgaWorkspaceMemDesc_TU102(OBJGPU *pGpu, struct MemoryManager *pMemoryManager); +NV_STATUS memmgrReserveVgaWorkspaceMemDescForFbsr_TU102(OBJGPU *pGpu, struct MemoryManager *pMemoryManager); + + +#ifdef __nvoc_mem_mgr_h_disabled +static inline NV_STATUS memmgrReserveVgaWorkspaceMemDescForFbsr(OBJGPU *pGpu, struct MemoryManager *pMemoryManager) { + NV_ASSERT_FAILED_PRECOMP("MemoryManager was disabled!"); + return NV_ERR_NOT_SUPPORTED; +} +#else //__nvoc_mem_mgr_h_disabled +#define memmgrReserveVgaWorkspaceMemDescForFbsr(pGpu, pMemoryManager) memmgrReserveVgaWorkspaceMemDescForFbsr_46f6a7(pGpu, pMemoryManager) +#endif //__nvoc_mem_mgr_h_disabled + +#define memmgrReserveVgaWorkspaceMemDescForFbsr_HAL(pGpu, pMemoryManager) memmgrReserveVgaWorkspaceMemDescForFbsr(pGpu, pMemoryManager) + +static inline NV_STATUS memmgrCalculateHeapOffsetWithGSP_46f6a7(OBJGPU *pGpu, struct MemoryManager *pMemoryManager, NvU32 *offset) { + return NV_ERR_NOT_SUPPORTED; +} #ifdef __nvoc_mem_mgr_h_disabled -static inline NV_STATUS memmgrCreateVgaWorkspaceMemDesc(OBJGPU *pGpu, struct MemoryManager *pMemoryManager) { +static inline NV_STATUS memmgrCalculateHeapOffsetWithGSP(OBJGPU *pGpu, struct MemoryManager *pMemoryManager, NvU32 *offset) { NV_ASSERT_FAILED_PRECOMP("MemoryManager was disabled!"); return NV_ERR_NOT_SUPPORTED; } #else //__nvoc_mem_mgr_h_disabled -#define memmgrCreateVgaWorkspaceMemDesc(pGpu, pMemoryManager) memmgrCreateVgaWorkspaceMemDesc_46f6a7(pGpu, pMemoryManager) +#define memmgrCalculateHeapOffsetWithGSP(pGpu, pMemoryManager, offset) memmgrCalculateHeapOffsetWithGSP_46f6a7(pGpu, pMemoryManager, offset) +#endif //__nvoc_mem_mgr_h_disabled + +#define memmgrCalculateHeapOffsetWithGSP_HAL(pGpu, pMemoryManager, offset) memmgrCalculateHeapOffsetWithGSP(pGpu, pMemoryManager, offset) + +NvBool memmgrIsGspOwnedMemory_KERNEL(OBJGPU *pGpu, struct MemoryManager *pMemoryManager, MEMORY_DESCRIPTOR *pMemDesc); + + +#ifdef __nvoc_mem_mgr_h_disabled +static inline NvBool memmgrIsGspOwnedMemory(OBJGPU *pGpu, struct MemoryManager *pMemoryManager, MEMORY_DESCRIPTOR *pMemDesc) { + NV_ASSERT_FAILED_PRECOMP("MemoryManager was disabled!"); + return NV_FALSE; +} +#else //__nvoc_mem_mgr_h_disabled +#define memmgrIsGspOwnedMemory(pGpu, pMemoryManager, pMemDesc) memmgrIsGspOwnedMemory_KERNEL(pGpu, pMemoryManager, pMemDesc) #endif //__nvoc_mem_mgr_h_disabled -#define memmgrCreateVgaWorkspaceMemDesc_HAL(pGpu, pMemoryManager) memmgrCreateVgaWorkspaceMemDesc(pGpu, pMemoryManager) +#define memmgrIsGspOwnedMemory_HAL(pGpu, pMemoryManager, pMemDesc) memmgrIsGspOwnedMemory(pGpu, pMemoryManager, pMemDesc) NV_STATUS memmgrConstructEngine_IMPL(OBJGPU *pGpu, struct MemoryManager *pMemoryManager, ENGDESCRIPTOR arg0); @@ -1803,6 +1859,12 @@ return pMemoryManager->__memmgrStateLoad__(pGpu, pMemoryManager, arg0); } +NV_STATUS memmgrStatePostLoad_IMPL(OBJGPU *pGpu, struct MemoryManager *pMemoryManager, NvU32 arg0); + +static inline NV_STATUS memmgrStatePostLoad_DISPATCH(OBJGPU *pGpu, struct MemoryManager *pMemoryManager, NvU32 arg0) { + return pMemoryManager->__memmgrStatePostLoad__(pGpu, pMemoryManager, arg0); +} + NV_STATUS memmgrStatePreUnload_IMPL(OBJGPU *pGpu, struct MemoryManager *pMemoryManager, NvU32 arg0); static inline NV_STATUS memmgrStatePreUnload_DISPATCH(OBJGPU *pGpu, struct MemoryManager *pMemoryManager, NvU32 arg0) { @@ -1821,6 +1883,16 @@ pMemoryManager->__memmgrStateDestroy__(pGpu, pMemoryManager); } +NV_STATUS memmgrMemUtilsSec2CtxInit_GH100(OBJGPU *pGpu, struct MemoryManager *pMemoryManager, OBJCHANNEL *arg0); + +static inline NV_STATUS memmgrMemUtilsSec2CtxInit_46f6a7(OBJGPU *pGpu, struct MemoryManager *pMemoryManager, OBJCHANNEL *arg0) { + return NV_ERR_NOT_SUPPORTED; +} + +static inline NV_STATUS memmgrMemUtilsSec2CtxInit_DISPATCH(OBJGPU *pGpu, struct MemoryManager *pMemoryManager, OBJCHANNEL *arg0) { + return pMemoryManager->__memmgrMemUtilsSec2CtxInit__(pGpu, pMemoryManager, arg0); +} + NvBool memmgrMemUtilsCheckMemoryFastScrubEnable_GH100(OBJGPU *pGpu, struct MemoryManager *pMemoryManager, NvU32 arg0, NvBool arg1, RmPhysAddr arg2, NvU32 arg3, NV_ADDRESS_SPACE arg4); static inline NvBool memmgrMemUtilsCheckMemoryFastScrubEnable_491d52(OBJGPU *pGpu, struct MemoryManager *pMemoryManager, NvU32 arg0, NvBool arg1, RmPhysAddr arg2, NvU32 arg3, NV_ADDRESS_SPACE arg4) { @@ -1897,6 +1969,16 @@ return pMemoryManager->__memmgrGetFlaKind__(pGpu, pMemoryManager, arg0); } +NvBool memmgrIsApertureSupportedByFla_GA100(OBJGPU *pGpu, struct MemoryManager *pMemoryManager, NV_ADDRESS_SPACE arg0); + +static inline NvBool memmgrIsApertureSupportedByFla_46f6a7(OBJGPU *pGpu, struct MemoryManager *pMemoryManager, NV_ADDRESS_SPACE arg0) { + return NV_ERR_NOT_SUPPORTED; +} + +static inline NvBool memmgrIsApertureSupportedByFla_DISPATCH(OBJGPU *pGpu, struct MemoryManager *pMemoryManager, NV_ADDRESS_SPACE arg0) { + return pMemoryManager->__memmgrIsApertureSupportedByFla__(pGpu, pMemoryManager, arg0); +} + NvU32 memmgrDetermineComptag_TU102(OBJGPU *pGpu, struct MemoryManager *pMemoryManager, RmPhysAddr arg0); static inline NvU32 memmgrDetermineComptag_13cd8d(OBJGPU *pGpu, struct MemoryManager *pMemoryManager, RmPhysAddr arg0) { @@ -1979,10 +2061,6 @@ return pMemoryManager->__memmgrGetBlackListPages__(pGpu, pMemoryManager, pBlAddrs, pCount); } -static inline NV_STATUS memmgrReconcileTunableState_DISPATCH(POBJGPU pGpu, struct MemoryManager *pEngstate, void *pTunableState) { - return pEngstate->__memmgrReconcileTunableState__(pGpu, pEngstate, pTunableState); -} - static inline NV_STATUS memmgrStatePreLoad_DISPATCH(POBJGPU pGpu, struct MemoryManager *pEngstate, NvU32 arg0) { return pEngstate->__memmgrStatePreLoad__(pGpu, pEngstate, arg0); } @@ -2003,32 +2081,16 @@ return pEngstate->__memmgrStatePreInitUnlocked__(pGpu, pEngstate); } -static inline NV_STATUS memmgrGetTunableState_DISPATCH(POBJGPU pGpu, struct MemoryManager *pEngstate, void *pTunableState) { - return pEngstate->__memmgrGetTunableState__(pGpu, pEngstate, pTunableState); -} - -static inline NV_STATUS memmgrCompareTunableState_DISPATCH(POBJGPU pGpu, struct MemoryManager *pEngstate, void *pTunables1, void *pTunables2) { - return pEngstate->__memmgrCompareTunableState__(pGpu, pEngstate, pTunables1, pTunables2); -} - -static inline void memmgrFreeTunableState_DISPATCH(POBJGPU pGpu, struct MemoryManager *pEngstate, void *pTunableState) { - pEngstate->__memmgrFreeTunableState__(pGpu, pEngstate, pTunableState); -} - -static inline NV_STATUS memmgrStatePostLoad_DISPATCH(POBJGPU pGpu, struct MemoryManager *pEngstate, NvU32 arg0) { - return pEngstate->__memmgrStatePostLoad__(pGpu, pEngstate, arg0); -} - -static inline NV_STATUS memmgrAllocTunableState_DISPATCH(POBJGPU pGpu, struct MemoryManager *pEngstate, void **ppTunableState) { - return pEngstate->__memmgrAllocTunableState__(pGpu, pEngstate, ppTunableState); +static inline NvBool memmgrIsPresent_DISPATCH(POBJGPU pGpu, struct MemoryManager *pEngstate) { + return pEngstate->__memmgrIsPresent__(pGpu, pEngstate); } -static inline NV_STATUS memmgrSetTunableState_DISPATCH(POBJGPU pGpu, struct MemoryManager *pEngstate, void *pTunableState) { - return pEngstate->__memmgrSetTunableState__(pGpu, pEngstate, pTunableState); +static inline NvBool memmgrIsLocalEgmSupported(struct MemoryManager *pMemoryManager) { + return pMemoryManager->bLocalEgmSupported; } -static inline NvBool memmgrIsPresent_DISPATCH(POBJGPU pGpu, struct MemoryManager *pEngstate) { - return pEngstate->__memmgrIsPresent__(pGpu, pEngstate); +static inline NvBool memmgrIsLocalEgmEnabled(struct MemoryManager *pMemoryManager) { + return pMemoryManager->bLocalEgmEnabled; } static inline NvBool memmgrIsScrubOnFreeEnabled(struct MemoryManager *pMemoryManager) { @@ -2087,10 +2149,6 @@ pMemoryManager->bClientPageTablesPmaManaged = val; } -static inline NvBool memmgrIsPmaAddrTree(struct MemoryManager *pMemoryManager) { - return pMemoryManager->bPmaAddrTree; -} - static inline NvU64 memmgrGetRsvdMemoryBase(struct MemoryManager *pMemoryManager) { return pMemoryManager->rsvdMemoryBase; } @@ -2510,32 +2568,32 @@ #define memmgrMemUtilsSetupChannelBufferSizes(pMemoryManager, arg0, arg1) memmgrMemUtilsSetupChannelBufferSizes_IMPL(pMemoryManager, arg0, arg1) #endif //__nvoc_mem_mgr_h_disabled -NV_STATUS memmgrGetKindComprFromMemDesc_IMPL(struct MemoryManager *pMemoryManager, MEMORY_DESCRIPTOR *arg0, NvU64 offset, NvU32 *kind, COMPR_INFO *pComprInfo); +NV_STATUS memmgrMemUtilsChannelSchedulingSetup_IMPL(OBJGPU *pGpu, struct MemoryManager *pMemoryManager, OBJCHANNEL *arg0); #ifdef __nvoc_mem_mgr_h_disabled -static inline NV_STATUS memmgrGetKindComprFromMemDesc(struct MemoryManager *pMemoryManager, MEMORY_DESCRIPTOR *arg0, NvU64 offset, NvU32 *kind, COMPR_INFO *pComprInfo) { +static inline NV_STATUS memmgrMemUtilsChannelSchedulingSetup(OBJGPU *pGpu, struct MemoryManager *pMemoryManager, OBJCHANNEL *arg0) { NV_ASSERT_FAILED_PRECOMP("MemoryManager was disabled!"); return NV_ERR_NOT_SUPPORTED; } #else //__nvoc_mem_mgr_h_disabled -#define memmgrGetKindComprFromMemDesc(pMemoryManager, arg0, offset, kind, pComprInfo) memmgrGetKindComprFromMemDesc_IMPL(pMemoryManager, arg0, offset, kind, pComprInfo) +#define memmgrMemUtilsChannelSchedulingSetup(pGpu, pMemoryManager, arg0) memmgrMemUtilsChannelSchedulingSetup_IMPL(pGpu, pMemoryManager, arg0) #endif //__nvoc_mem_mgr_h_disabled -NvBool memmgrIsCompressible_IMPL(struct MemoryManager *pMemoryManager, MEMORY_DESCRIPTOR *arg0); +NV_STATUS memmgrGetKindComprFromMemDesc_IMPL(struct MemoryManager *pMemoryManager, MEMORY_DESCRIPTOR *arg0, NvU64 offset, NvU32 *kind, COMPR_INFO *pComprInfo); #ifdef __nvoc_mem_mgr_h_disabled -static inline NvBool memmgrIsCompressible(struct MemoryManager *pMemoryManager, MEMORY_DESCRIPTOR *arg0) { +static inline NV_STATUS memmgrGetKindComprFromMemDesc(struct MemoryManager *pMemoryManager, MEMORY_DESCRIPTOR *arg0, NvU64 offset, NvU32 *kind, COMPR_INFO *pComprInfo) { NV_ASSERT_FAILED_PRECOMP("MemoryManager was disabled!"); - return NV_FALSE; + return NV_ERR_NOT_SUPPORTED; } #else //__nvoc_mem_mgr_h_disabled -#define memmgrIsCompressible(pMemoryManager, arg0) memmgrIsCompressible_IMPL(pMemoryManager, arg0) +#define memmgrGetKindComprFromMemDesc(pMemoryManager, arg0, offset, kind, pComprInfo) memmgrGetKindComprFromMemDesc_IMPL(pMemoryManager, arg0, offset, kind, pComprInfo) #endif //__nvoc_mem_mgr_h_disabled -NV_STATUS memmgrFillComprInfo_IMPL(OBJGPU *pGpu, struct MemoryManager *pMemoryManager, NvU32 arg0, NvU32 arg1, NvU32 arg2, NvU64 arg3, NvU32 arg4, COMPR_INFO *arg5); +NV_STATUS memmgrFillComprInfo_IMPL(OBJGPU *pGpu, struct MemoryManager *pMemoryManager, NvU64 arg0, NvU32 arg1, NvU32 arg2, NvU64 arg3, NvU32 arg4, COMPR_INFO *arg5); #ifdef __nvoc_mem_mgr_h_disabled -static inline NV_STATUS memmgrFillComprInfo(OBJGPU *pGpu, struct MemoryManager *pMemoryManager, NvU32 arg0, NvU32 arg1, NvU32 arg2, NvU64 arg3, NvU32 arg4, COMPR_INFO *arg5) { +static inline NV_STATUS memmgrFillComprInfo(OBJGPU *pGpu, struct MemoryManager *pMemoryManager, NvU64 arg0, NvU32 arg1, NvU32 arg2, NvU64 arg3, NvU32 arg4, COMPR_INFO *arg5) { NV_ASSERT_FAILED_PRECOMP("MemoryManager was disabled!"); return NV_ERR_NOT_SUPPORTED; } @@ -2585,6 +2643,27 @@ #define memmgrPmaRegisterRegions(pGpu, pMemoryManager, pHeap, pPma) memmgrPmaRegisterRegions_IMPL(pGpu, pMemoryManager, pHeap, pPma) #endif //__nvoc_mem_mgr_h_disabled +NV_STATUS memmgrInitCeUtils_IMPL(struct MemoryManager *pMemoryManager, NvBool bFifoLite); + +#ifdef __nvoc_mem_mgr_h_disabled +static inline NV_STATUS memmgrInitCeUtils(struct MemoryManager *pMemoryManager, NvBool bFifoLite) { + NV_ASSERT_FAILED_PRECOMP("MemoryManager was disabled!"); + return NV_ERR_NOT_SUPPORTED; +} +#else //__nvoc_mem_mgr_h_disabled +#define memmgrInitCeUtils(pMemoryManager, bFifoLite) memmgrInitCeUtils_IMPL(pMemoryManager, bFifoLite) +#endif //__nvoc_mem_mgr_h_disabled + +void memmgrDestroyCeUtils_IMPL(struct MemoryManager *pMemoryManager); + +#ifdef __nvoc_mem_mgr_h_disabled +static inline void memmgrDestroyCeUtils(struct MemoryManager *pMemoryManager) { + NV_ASSERT_FAILED_PRECOMP("MemoryManager was disabled!"); +} +#else //__nvoc_mem_mgr_h_disabled +#define memmgrDestroyCeUtils(pMemoryManager) memmgrDestroyCeUtils_IMPL(pMemoryManager) +#endif //__nvoc_mem_mgr_h_disabled + NV_STATUS memmgrSetMIGPartitionableBAR1Range_IMPL(OBJGPU *arg0, struct MemoryManager *arg1); #ifdef __nvoc_mem_mgr_h_disabled @@ -2706,6 +2785,16 @@ #define memmgrGetFreeMemoryForAllMIGGPUInstances(pGpu, pMemoryManager, pBytes) memmgrGetFreeMemoryForAllMIGGPUInstances_IMPL(pGpu, pMemoryManager, pBytes) #endif //__nvoc_mem_mgr_h_disabled +void memmgrGetTotalMemoryForAllMIGGPUInstances_IMPL(OBJGPU *pGpu, struct MemoryManager *pMemoryManager, NvU64 *pBytes); + +#ifdef __nvoc_mem_mgr_h_disabled +static inline void memmgrGetTotalMemoryForAllMIGGPUInstances(OBJGPU *pGpu, struct MemoryManager *pMemoryManager, NvU64 *pBytes) { + NV_ASSERT_FAILED_PRECOMP("MemoryManager was disabled!"); +} +#else //__nvoc_mem_mgr_h_disabled +#define memmgrGetTotalMemoryForAllMIGGPUInstances(pGpu, pMemoryManager, pBytes) memmgrGetTotalMemoryForAllMIGGPUInstances_IMPL(pGpu, pMemoryManager, pBytes) +#endif //__nvoc_mem_mgr_h_disabled + void memmgrGetTopLevelScrubberStatus_IMPL(OBJGPU *arg0, struct MemoryManager *arg1, NvBool *pbTopLevelScrubberEnabled, NvBool *pbTopLevelScrubberConstructed); #ifdef __nvoc_mem_mgr_h_disabled @@ -2738,6 +2827,28 @@ #define memmgrInitSavedTopLevelScrubber(arg0, arg1) memmgrInitSavedTopLevelScrubber_IMPL(arg0, arg1) #endif //__nvoc_mem_mgr_h_disabled +MEMORY_DESCRIPTOR *memmgrMemUtilsGetMemDescFromHandle_IMPL(struct MemoryManager *pMemoryManager, NvHandle hClient, NvHandle hMemory); + +#ifdef __nvoc_mem_mgr_h_disabled +static inline MEMORY_DESCRIPTOR *memmgrMemUtilsGetMemDescFromHandle(struct MemoryManager *pMemoryManager, NvHandle hClient, NvHandle hMemory) { + NV_ASSERT_FAILED_PRECOMP("MemoryManager was disabled!"); + return NULL; +} +#else //__nvoc_mem_mgr_h_disabled +#define memmgrMemUtilsGetMemDescFromHandle(pMemoryManager, hClient, hMemory) memmgrMemUtilsGetMemDescFromHandle_IMPL(pMemoryManager, hClient, hMemory) +#endif //__nvoc_mem_mgr_h_disabled + +NV_STATUS memmgrVerifyGspDmaOps_IMPL(OBJGPU *arg0, struct MemoryManager *arg1); + +#ifdef __nvoc_mem_mgr_h_disabled +static inline NV_STATUS memmgrVerifyGspDmaOps(OBJGPU *arg0, struct MemoryManager *arg1) { + NV_ASSERT_FAILED_PRECOMP("MemoryManager was disabled!"); + return NV_ERR_NOT_SUPPORTED; +} +#else //__nvoc_mem_mgr_h_disabled +#define memmgrVerifyGspDmaOps(arg0, arg1) memmgrVerifyGspDmaOps_IMPL(arg0, arg1) +#endif //__nvoc_mem_mgr_h_disabled + NV_STATUS memmgrReserveMemoryForFsp_IMPL(OBJGPU *pGpu, struct MemoryManager *pMemoryManager); #ifdef __nvoc_mem_mgr_h_disabled diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/generated/g_mem_multicast_fabric_nvoc.c nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_mem_multicast_fabric_nvoc.c --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/generated/g_mem_multicast_fabric_nvoc.c 2023-10-25 20:27:13.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_mem_multicast_fabric_nvoc.c 2024-03-05 22:18:34.000000000 +0000 @@ -105,10 +105,6 @@ return memorymulticastfabricControl((struct MemoryMulticastFabric *)(((unsigned char *)pMemoryMulticastFabric) - __nvoc_rtti_MemoryMulticastFabric_Memory.offset), pCallContext, pParams); } -static NV_STATUS __nvoc_thunk_MemoryMulticastFabric_rmresControl_Prologue(struct RmResource *pMemoryMulticastFabric, CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { - return memorymulticastfabricControl_Prologue((struct MemoryMulticastFabric *)(((unsigned char *)pMemoryMulticastFabric) - __nvoc_rtti_MemoryMulticastFabric_RmResource.offset), pCallContext, pParams); -} - static NvBool __nvoc_thunk_MemoryMulticastFabric_memIsGpuMapAllowed(struct Memory *pMemoryMulticastFabric, struct OBJGPU *pGpu) { return memorymulticastfabricIsGpuMapAllowed((struct MemoryMulticastFabric *)(((unsigned char *)pMemoryMulticastFabric) - __nvoc_rtti_MemoryMulticastFabric_Memory.offset), pGpu); } @@ -121,6 +117,38 @@ return memCheckMemInterUnmap((struct Memory *)(((unsigned char *)pMemory) + __nvoc_rtti_MemoryMulticastFabric_Memory.offset), bSubdeviceHandleProvided); } +static NvBool __nvoc_thunk_RmResource_memorymulticastfabricShareCallback(struct MemoryMulticastFabric *pResource, struct RsClient *pInvokingClient, struct RsResourceRef *pParentRef, RS_SHARE_POLICY *pSharePolicy) { + return rmresShareCallback((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_MemoryMulticastFabric_RmResource.offset), pInvokingClient, pParentRef, pSharePolicy); +} + +static NV_STATUS __nvoc_thunk_RsResource_memorymulticastfabricMapTo(struct MemoryMulticastFabric *pResource, RS_RES_MAP_TO_PARAMS *pParams) { + return resMapTo((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_MemoryMulticastFabric_RsResource.offset), pParams); +} + +static NvU32 __nvoc_thunk_RsResource_memorymulticastfabricGetRefCount(struct MemoryMulticastFabric *pResource) { + return resGetRefCount((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_MemoryMulticastFabric_RsResource.offset)); +} + +static void __nvoc_thunk_RsResource_memorymulticastfabricAddAdditionalDependants(struct RsClient *pClient, struct MemoryMulticastFabric *pResource, RsResourceRef *pReference) { + resAddAdditionalDependants(pClient, (struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_MemoryMulticastFabric_RsResource.offset), pReference); +} + +static NV_STATUS __nvoc_thunk_RmResource_memorymulticastfabricControl_Prologue(struct MemoryMulticastFabric *pResource, CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return rmresControl_Prologue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_MemoryMulticastFabric_RmResource.offset), pCallContext, pParams); +} + +static NV_STATUS __nvoc_thunk_RsResource_memorymulticastfabricUnmapFrom(struct MemoryMulticastFabric *pResource, RS_RES_UNMAP_FROM_PARAMS *pParams) { + return resUnmapFrom((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_MemoryMulticastFabric_RsResource.offset), pParams); +} + +static void __nvoc_thunk_RmResource_memorymulticastfabricControl_Epilogue(struct MemoryMulticastFabric *pResource, CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + rmresControl_Epilogue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_MemoryMulticastFabric_RmResource.offset), pCallContext, pParams); +} + +static NV_STATUS __nvoc_thunk_RsResource_memorymulticastfabricControlLookup(struct MemoryMulticastFabric *pResource, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams, const struct NVOC_EXPORTED_METHOD_DEF **ppEntry) { + return resControlLookup((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_MemoryMulticastFabric_RsResource.offset), pParams, ppEntry); +} + static NV_STATUS __nvoc_thunk_Memory_memorymulticastfabricUnmap(struct MemoryMulticastFabric *pMemory, CALL_CONTEXT *pCallContext, RsCpuMapping *pCpuMapping) { return memUnmap((struct Memory *)(((unsigned char *)pMemory) + __nvoc_rtti_MemoryMulticastFabric_Memory.offset), pCallContext, pCpuMapping); } @@ -133,28 +161,16 @@ return memGetMemoryMappingDescriptor((struct Memory *)(((unsigned char *)pMemory) + __nvoc_rtti_MemoryMulticastFabric_Memory.offset), ppMemDesc); } -static NvBool __nvoc_thunk_RmResource_memorymulticastfabricShareCallback(struct MemoryMulticastFabric *pResource, struct RsClient *pInvokingClient, struct RsResourceRef *pParentRef, RS_SHARE_POLICY *pSharePolicy) { - return rmresShareCallback((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_MemoryMulticastFabric_RmResource.offset), pInvokingClient, pParentRef, pSharePolicy); -} - static NV_STATUS __nvoc_thunk_RsResource_memorymulticastfabricControlFilter(struct MemoryMulticastFabric *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { return resControlFilter((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_MemoryMulticastFabric_RsResource.offset), pCallContext, pParams); } -static void __nvoc_thunk_RsResource_memorymulticastfabricAddAdditionalDependants(struct RsClient *pClient, struct MemoryMulticastFabric *pResource, RsResourceRef *pReference) { - resAddAdditionalDependants(pClient, (struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_MemoryMulticastFabric_RsResource.offset), pReference); -} - -static NvU32 __nvoc_thunk_RsResource_memorymulticastfabricGetRefCount(struct MemoryMulticastFabric *pResource) { - return resGetRefCount((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_MemoryMulticastFabric_RsResource.offset)); -} - -static NV_STATUS __nvoc_thunk_RsResource_memorymulticastfabricMapTo(struct MemoryMulticastFabric *pResource, RS_RES_MAP_TO_PARAMS *pParams) { - return resMapTo((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_MemoryMulticastFabric_RsResource.offset), pParams); +static NV_STATUS __nvoc_thunk_RmResource_memorymulticastfabricControlSerialization_Prologue(struct MemoryMulticastFabric *pResource, CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return rmresControlSerialization_Prologue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_MemoryMulticastFabric_RmResource.offset), pCallContext, pParams); } -static NV_STATUS __nvoc_thunk_Memory_memorymulticastfabricCheckCopyPermissions(struct MemoryMulticastFabric *pMemory, struct OBJGPU *pDstGpu, NvHandle hDstClientNvBool) { - return memCheckCopyPermissions((struct Memory *)(((unsigned char *)pMemory) + __nvoc_rtti_MemoryMulticastFabric_Memory.offset), pDstGpu, hDstClientNvBool); +static NV_STATUS __nvoc_thunk_Memory_memorymulticastfabricCheckCopyPermissions(struct MemoryMulticastFabric *pMemory, struct OBJGPU *pDstGpu, struct Device *pDstDevice) { + return memCheckCopyPermissions((struct Memory *)(((unsigned char *)pMemory) + __nvoc_rtti_MemoryMulticastFabric_Memory.offset), pDstGpu, pDstDevice); } static void __nvoc_thunk_RsResource_memorymulticastfabricPreDestruct(struct MemoryMulticastFabric *pResource) { @@ -165,16 +181,8 @@ return memIsDuplicate((struct Memory *)(((unsigned char *)pMemory) + __nvoc_rtti_MemoryMulticastFabric_Memory.offset), hMemory, pDuplicate); } -static NV_STATUS __nvoc_thunk_RsResource_memorymulticastfabricUnmapFrom(struct MemoryMulticastFabric *pResource, RS_RES_UNMAP_FROM_PARAMS *pParams) { - return resUnmapFrom((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_MemoryMulticastFabric_RsResource.offset), pParams); -} - -static void __nvoc_thunk_RmResource_memorymulticastfabricControl_Epilogue(struct MemoryMulticastFabric *pResource, CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { - rmresControl_Epilogue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_MemoryMulticastFabric_RmResource.offset), pCallContext, pParams); -} - -static NV_STATUS __nvoc_thunk_RsResource_memorymulticastfabricControlLookup(struct MemoryMulticastFabric *pResource, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams, const struct NVOC_EXPORTED_METHOD_DEF **ppEntry) { - return resControlLookup((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_MemoryMulticastFabric_RsResource.offset), pParams, ppEntry); +static void __nvoc_thunk_RmResource_memorymulticastfabricControlSerialization_Epilogue(struct MemoryMulticastFabric *pResource, CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + rmresControlSerialization_Epilogue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_MemoryMulticastFabric_RmResource.offset), pCallContext, pParams); } static NV_STATUS __nvoc_thunk_Memory_memorymulticastfabricMap(struct MemoryMulticastFabric *pMemory, CALL_CONTEXT *pCallContext, struct RS_CPU_MAP_PARAMS *pParams, RsCpuMapping *pCpuMapping) { @@ -207,12 +215,12 @@ #endif }, { /* [1] */ -#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x811u) +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x810u) /*pFunc=*/ (void (*)(void)) NULL, #else /*pFunc=*/ (void (*)(void)) memorymulticastfabricCtrlAttachMem_IMPL, -#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x811u) - /*flags=*/ 0x811u, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x810u) + /*flags=*/ 0x810u, /*accessRight=*/0x0u, /*methodId=*/ 0xfd0102u, /*paramSize=*/ sizeof(NV00FD_CTRL_ATTACH_MEM_PARAMS), @@ -236,12 +244,42 @@ /*func=*/ "memorymulticastfabricCtrlRegisterEvent" #endif }, + { /* [3] */ +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x810u) + /*pFunc=*/ (void (*)(void)) NULL, +#else + /*pFunc=*/ (void (*)(void)) memorymulticastfabricCtrlAttachGpu_IMPL, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x810u) + /*flags=*/ 0x810u, + /*accessRight=*/0x0u, + /*methodId=*/ 0xfd0104u, + /*paramSize=*/ sizeof(NV00FD_CTRL_ATTACH_GPU_PARAMS), + /*pClassInfo=*/ &(__nvoc_class_def_MemoryMulticastFabric.classInfo), +#if NV_PRINTF_STRINGS_ALLOWED + /*func=*/ "memorymulticastfabricCtrlAttachGpu" +#endif + }, + { /* [4] */ +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x810u) + /*pFunc=*/ (void (*)(void)) NULL, +#else + /*pFunc=*/ (void (*)(void)) memorymulticastfabricCtrlDetachMem_IMPL, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x810u) + /*flags=*/ 0x810u, + /*accessRight=*/0x0u, + /*methodId=*/ 0xfd0105u, + /*paramSize=*/ sizeof(NV00FD_CTRL_DETACH_MEM_PARAMS), + /*pClassInfo=*/ &(__nvoc_class_def_MemoryMulticastFabric.classInfo), +#if NV_PRINTF_STRINGS_ALLOWED + /*func=*/ "memorymulticastfabricCtrlDetachMem" +#endif + }, }; const struct NVOC_EXPORT_INFO __nvoc_export_info_MemoryMulticastFabric = { - /*numEntries=*/ 3, + /*numEntries=*/ 5, /*pExportEntries=*/ __nvoc_exported_method_def_MemoryMulticastFabric }; @@ -286,8 +324,6 @@ pThis->__memorymulticastfabricControl__ = &memorymulticastfabricControl_IMPL; - pThis->__memorymulticastfabricControl_Prologue__ = &memorymulticastfabricControl_Prologue_IMPL; - pThis->__memorymulticastfabricIsGpuMapAllowed__ = &memorymulticastfabricIsGpuMapAllowed_IMPL; pThis->__memorymulticastfabricGetMapAddrSpace__ = &memorymulticastfabricGetMapAddrSpace_IMPL; @@ -296,10 +332,18 @@ pThis->__memorymulticastfabricCtrlGetInfo__ = &memorymulticastfabricCtrlGetInfo_IMPL; #endif -#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x811u) +#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x810u) pThis->__memorymulticastfabricCtrlAttachMem__ = &memorymulticastfabricCtrlAttachMem_IMPL; #endif +#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x810u) + pThis->__memorymulticastfabricCtrlDetachMem__ = &memorymulticastfabricCtrlDetachMem_IMPL; +#endif + +#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x810u) + pThis->__memorymulticastfabricCtrlAttachGpu__ = &memorymulticastfabricCtrlAttachGpu_IMPL; +#endif + #if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x811u) pThis->__memorymulticastfabricCtrlRegisterEvent__ = &memorymulticastfabricCtrlRegisterEvent_IMPL; #endif @@ -310,29 +354,37 @@ pThis->__nvoc_base_Memory.__memControl__ = &__nvoc_thunk_MemoryMulticastFabric_memControl; - pThis->__nvoc_base_Memory.__nvoc_base_RmResource.__rmresControl_Prologue__ = &__nvoc_thunk_MemoryMulticastFabric_rmresControl_Prologue; - pThis->__nvoc_base_Memory.__memIsGpuMapAllowed__ = &__nvoc_thunk_MemoryMulticastFabric_memIsGpuMapAllowed; pThis->__nvoc_base_Memory.__memGetMapAddrSpace__ = &__nvoc_thunk_MemoryMulticastFabric_memGetMapAddrSpace; pThis->__memorymulticastfabricCheckMemInterUnmap__ = &__nvoc_thunk_Memory_memorymulticastfabricCheckMemInterUnmap; + pThis->__memorymulticastfabricShareCallback__ = &__nvoc_thunk_RmResource_memorymulticastfabricShareCallback; + + pThis->__memorymulticastfabricMapTo__ = &__nvoc_thunk_RsResource_memorymulticastfabricMapTo; + + pThis->__memorymulticastfabricGetRefCount__ = &__nvoc_thunk_RsResource_memorymulticastfabricGetRefCount; + + pThis->__memorymulticastfabricAddAdditionalDependants__ = &__nvoc_thunk_RsResource_memorymulticastfabricAddAdditionalDependants; + + pThis->__memorymulticastfabricControl_Prologue__ = &__nvoc_thunk_RmResource_memorymulticastfabricControl_Prologue; + + pThis->__memorymulticastfabricUnmapFrom__ = &__nvoc_thunk_RsResource_memorymulticastfabricUnmapFrom; + + pThis->__memorymulticastfabricControl_Epilogue__ = &__nvoc_thunk_RmResource_memorymulticastfabricControl_Epilogue; + + pThis->__memorymulticastfabricControlLookup__ = &__nvoc_thunk_RsResource_memorymulticastfabricControlLookup; + pThis->__memorymulticastfabricUnmap__ = &__nvoc_thunk_Memory_memorymulticastfabricUnmap; pThis->__memorymulticastfabricGetMemInterMapParams__ = &__nvoc_thunk_Memory_memorymulticastfabricGetMemInterMapParams; pThis->__memorymulticastfabricGetMemoryMappingDescriptor__ = &__nvoc_thunk_Memory_memorymulticastfabricGetMemoryMappingDescriptor; - pThis->__memorymulticastfabricShareCallback__ = &__nvoc_thunk_RmResource_memorymulticastfabricShareCallback; - pThis->__memorymulticastfabricControlFilter__ = &__nvoc_thunk_RsResource_memorymulticastfabricControlFilter; - pThis->__memorymulticastfabricAddAdditionalDependants__ = &__nvoc_thunk_RsResource_memorymulticastfabricAddAdditionalDependants; - - pThis->__memorymulticastfabricGetRefCount__ = &__nvoc_thunk_RsResource_memorymulticastfabricGetRefCount; - - pThis->__memorymulticastfabricMapTo__ = &__nvoc_thunk_RsResource_memorymulticastfabricMapTo; + pThis->__memorymulticastfabricControlSerialization_Prologue__ = &__nvoc_thunk_RmResource_memorymulticastfabricControlSerialization_Prologue; pThis->__memorymulticastfabricCheckCopyPermissions__ = &__nvoc_thunk_Memory_memorymulticastfabricCheckCopyPermissions; @@ -340,11 +392,7 @@ pThis->__memorymulticastfabricIsDuplicate__ = &__nvoc_thunk_Memory_memorymulticastfabricIsDuplicate; - pThis->__memorymulticastfabricUnmapFrom__ = &__nvoc_thunk_RsResource_memorymulticastfabricUnmapFrom; - - pThis->__memorymulticastfabricControl_Epilogue__ = &__nvoc_thunk_RmResource_memorymulticastfabricControl_Epilogue; - - pThis->__memorymulticastfabricControlLookup__ = &__nvoc_thunk_RsResource_memorymulticastfabricControlLookup; + pThis->__memorymulticastfabricControlSerialization_Epilogue__ = &__nvoc_thunk_RmResource_memorymulticastfabricControlSerialization_Epilogue; pThis->__memorymulticastfabricMap__ = &__nvoc_thunk_Memory_memorymulticastfabricMap; @@ -372,13 +420,16 @@ Object *pParentObj; MemoryMulticastFabric *pThis; - pThis = portMemAllocNonPaged(sizeof(MemoryMulticastFabric)); - if (pThis == NULL) return NV_ERR_NO_MEMORY; + status = __nvoc_handleObjCreateMemAlloc(createFlags, sizeof(MemoryMulticastFabric), (void**)&pThis, (void**)ppThis); + if (status != NV_OK) + return status; portMemSet(pThis, 0, sizeof(MemoryMulticastFabric)); __nvoc_initRtti(staticCast(pThis, Dynamic), &__nvoc_class_def_MemoryMulticastFabric); + pThis->__nvoc_base_Memory.__nvoc_base_RmResource.__nvoc_base_RsResource.__nvoc_base_Object.createFlags = createFlags; + if (pParent != NULL && !(createFlags & NVOC_OBJ_CREATE_FLAGS_PARENT_HALSPEC_ONLY)) { pParentObj = dynamicCast(pParent, Object); @@ -394,11 +445,17 @@ if (status != NV_OK) goto __nvoc_objCreate_MemoryMulticastFabric_cleanup; *ppThis = pThis; + return NV_OK; __nvoc_objCreate_MemoryMulticastFabric_cleanup: // do not call destructors here since the constructor already called them - portMemFree(pThis); + if (createFlags & NVOC_OBJ_CREATE_FLAGS_IN_PLACE_CONSTRUCT) + portMemSet(pThis, 0, sizeof(MemoryMulticastFabric)); + else + portMemFree(pThis); + + // coverity[leaked_storage:FALSE] return status; } diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/generated/g_mem_multicast_fabric_nvoc.h nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_mem_multicast_fabric_nvoc.h --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/generated/g_mem_multicast_fabric_nvoc.h 2023-10-25 20:27:13.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_mem_multicast_fabric_nvoc.h 2024-03-05 22:18:34.000000000 +0000 @@ -7,7 +7,7 @@ #endif /* - * SPDX-FileCopyrightText: Copyright (c) 2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2022-23 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -53,17 +53,14 @@ // **************************************************************************** // Type Definitions // **************************************************************************** -typedef struct mem_multicast_fabric_attach_mem_info + +typedef struct mem_multicast_fabric_attach_mem_info_node { - NvU64 offset; - NvU64 mapOffset; - NvU64 mapLength; - NvU32 flags; - OBJGPU *pGpu; MEMORY_DESCRIPTOR *pPhysMemDesc; NvHandle hDupedPhysMem; - NvU64 gpuProbeHandle; -} MEM_MULTICAST_FABRIC_ATTACH_MEM_INFO; + NvU64 physMapLength; + NODE node; +} MEM_MULTICAST_FABRIC_ATTACH_MEM_INFO_NODE; typedef struct mem_multicast_fabric_client_info { @@ -71,16 +68,20 @@ struct Memory *pMemory; } MEM_MULTICAST_FABRIC_CLIENT_INFO; -typedef struct mem_multicast_fabric_gpu_os_info +typedef struct mem_multicast_fabric_gpu_info { - void *gpuOsInfo; -} MEM_MULTICAST_FABRIC_GPU_OS_INFO; - -MAKE_LIST(MemMulticastFabricAttachMemInfoList, MEM_MULTICAST_FABRIC_ATTACH_MEM_INFO); + void *pGpuOsInfo; + OBJGPU *pGpu; + NvU64 gpuProbeHandle; + NvBool bMcflaAlloc; + + // Tracks memory attached using NV00FD_CTRL_CMD_ATTACH_MEM + PNODE pAttachMemInfoTree; +} MEM_MULTICAST_FABRIC_GPU_INFO; MAKE_LIST(MemMulticastFabricClientInfoList, MEM_MULTICAST_FABRIC_CLIENT_INFO); -MAKE_LIST(MemMulticastFabricGpuOsInfoList, MEM_MULTICAST_FABRIC_GPU_OS_INFO); +MAKE_LIST(MemMulticastFabricGpuInfoList, MEM_MULTICAST_FABRIC_GPU_INFO); typedef enum { @@ -96,14 +97,11 @@ // List of clients waiting on this object to be ready MemMulticastFabricClientInfoList waitingClientsList; - // List of attach mem info of GPUs already attached to the mutlicast object - MemMulticastFabricAttachMemInfoList attachMemInfoList; - // Mask representing the list of attached GPUs NvU32 attachedGpusMask; - // List of GPU OS Info - MemMulticastFabricGpuOsInfoList gpuOsInfoList; + // List of attached GPU info + MemMulticastFabricGpuInfoList gpuInfoList; // Boolean to be set when pMemDesc is installed NvBool bMemdescInstalled; @@ -130,7 +128,7 @@ NvU64 allocSize; // Page size for the multicast FLA - NvU32 pageSize; + NvU64 pageSize; // Multicast FLA allocation flags NvU32 allocFlags; @@ -160,27 +158,31 @@ NV_STATUS (*__memorymulticastfabricCopyConstruct__)(struct MemoryMulticastFabric *, CALL_CONTEXT *, struct RS_RES_ALLOC_PARAMS_INTERNAL *); NV_STATUS (*__memorymulticastfabricIsReady__)(struct MemoryMulticastFabric *, NvBool); NV_STATUS (*__memorymulticastfabricControl__)(struct MemoryMulticastFabric *, CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); - NV_STATUS (*__memorymulticastfabricControl_Prologue__)(struct MemoryMulticastFabric *, CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); NvBool (*__memorymulticastfabricIsGpuMapAllowed__)(struct MemoryMulticastFabric *, struct OBJGPU *); NV_STATUS (*__memorymulticastfabricGetMapAddrSpace__)(struct MemoryMulticastFabric *, CALL_CONTEXT *, NvU32, NV_ADDRESS_SPACE *); NV_STATUS (*__memorymulticastfabricCtrlGetInfo__)(struct MemoryMulticastFabric *, NV00FD_CTRL_GET_INFO_PARAMS *); NV_STATUS (*__memorymulticastfabricCtrlAttachMem__)(struct MemoryMulticastFabric *, NV00FD_CTRL_ATTACH_MEM_PARAMS *); + NV_STATUS (*__memorymulticastfabricCtrlDetachMem__)(struct MemoryMulticastFabric *, NV00FD_CTRL_DETACH_MEM_PARAMS *); + NV_STATUS (*__memorymulticastfabricCtrlAttachGpu__)(struct MemoryMulticastFabric *, NV00FD_CTRL_ATTACH_GPU_PARAMS *); NV_STATUS (*__memorymulticastfabricCtrlRegisterEvent__)(struct MemoryMulticastFabric *, NV00FD_CTRL_REGISTER_EVENT_PARAMS *); NV_STATUS (*__memorymulticastfabricCheckMemInterUnmap__)(struct MemoryMulticastFabric *, NvBool); + NvBool (*__memorymulticastfabricShareCallback__)(struct MemoryMulticastFabric *, struct RsClient *, struct RsResourceRef *, RS_SHARE_POLICY *); + NV_STATUS (*__memorymulticastfabricMapTo__)(struct MemoryMulticastFabric *, RS_RES_MAP_TO_PARAMS *); + NvU32 (*__memorymulticastfabricGetRefCount__)(struct MemoryMulticastFabric *); + void (*__memorymulticastfabricAddAdditionalDependants__)(struct RsClient *, struct MemoryMulticastFabric *, RsResourceRef *); + NV_STATUS (*__memorymulticastfabricControl_Prologue__)(struct MemoryMulticastFabric *, CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); + NV_STATUS (*__memorymulticastfabricUnmapFrom__)(struct MemoryMulticastFabric *, RS_RES_UNMAP_FROM_PARAMS *); + void (*__memorymulticastfabricControl_Epilogue__)(struct MemoryMulticastFabric *, CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); + NV_STATUS (*__memorymulticastfabricControlLookup__)(struct MemoryMulticastFabric *, struct RS_RES_CONTROL_PARAMS_INTERNAL *, const struct NVOC_EXPORTED_METHOD_DEF **); NV_STATUS (*__memorymulticastfabricUnmap__)(struct MemoryMulticastFabric *, CALL_CONTEXT *, RsCpuMapping *); NV_STATUS (*__memorymulticastfabricGetMemInterMapParams__)(struct MemoryMulticastFabric *, RMRES_MEM_INTER_MAP_PARAMS *); NV_STATUS (*__memorymulticastfabricGetMemoryMappingDescriptor__)(struct MemoryMulticastFabric *, MEMORY_DESCRIPTOR **); - NvBool (*__memorymulticastfabricShareCallback__)(struct MemoryMulticastFabric *, struct RsClient *, struct RsResourceRef *, RS_SHARE_POLICY *); NV_STATUS (*__memorymulticastfabricControlFilter__)(struct MemoryMulticastFabric *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); - void (*__memorymulticastfabricAddAdditionalDependants__)(struct RsClient *, struct MemoryMulticastFabric *, RsResourceRef *); - NvU32 (*__memorymulticastfabricGetRefCount__)(struct MemoryMulticastFabric *); - NV_STATUS (*__memorymulticastfabricMapTo__)(struct MemoryMulticastFabric *, RS_RES_MAP_TO_PARAMS *); - NV_STATUS (*__memorymulticastfabricCheckCopyPermissions__)(struct MemoryMulticastFabric *, struct OBJGPU *, NvHandle); + NV_STATUS (*__memorymulticastfabricControlSerialization_Prologue__)(struct MemoryMulticastFabric *, CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); + NV_STATUS (*__memorymulticastfabricCheckCopyPermissions__)(struct MemoryMulticastFabric *, struct OBJGPU *, struct Device *); void (*__memorymulticastfabricPreDestruct__)(struct MemoryMulticastFabric *); NV_STATUS (*__memorymulticastfabricIsDuplicate__)(struct MemoryMulticastFabric *, NvHandle, NvBool *); - NV_STATUS (*__memorymulticastfabricUnmapFrom__)(struct MemoryMulticastFabric *, RS_RES_UNMAP_FROM_PARAMS *); - void (*__memorymulticastfabricControl_Epilogue__)(struct MemoryMulticastFabric *, CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); - NV_STATUS (*__memorymulticastfabricControlLookup__)(struct MemoryMulticastFabric *, struct RS_RES_CONTROL_PARAMS_INTERNAL *, const struct NVOC_EXPORTED_METHOD_DEF **); + void (*__memorymulticastfabricControlSerialization_Epilogue__)(struct MemoryMulticastFabric *, CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); NV_STATUS (*__memorymulticastfabricMap__)(struct MemoryMulticastFabric *, CALL_CONTEXT *, struct RS_CPU_MAP_PARAMS *, RsCpuMapping *); NvBool (*__memorymulticastfabricAccessCallback__)(struct MemoryMulticastFabric *, struct RsClient *, void *, RsAccessRight); MEM_MULTICAST_FABRIC_DESCRIPTOR *pMulticastFabricDesc; @@ -218,27 +220,31 @@ #define memorymulticastfabricCopyConstruct(pMemoryMulticastFabric, pCallContext, pParams) memorymulticastfabricCopyConstruct_DISPATCH(pMemoryMulticastFabric, pCallContext, pParams) #define memorymulticastfabricIsReady(pMemoryMulticastFabric, bCopyConstructorContext) memorymulticastfabricIsReady_DISPATCH(pMemoryMulticastFabric, bCopyConstructorContext) #define memorymulticastfabricControl(pMemoryMulticastFabric, pCallContext, pParams) memorymulticastfabricControl_DISPATCH(pMemoryMulticastFabric, pCallContext, pParams) -#define memorymulticastfabricControl_Prologue(pMemoryMulticastFabric, pCallContext, pParams) memorymulticastfabricControl_Prologue_DISPATCH(pMemoryMulticastFabric, pCallContext, pParams) #define memorymulticastfabricIsGpuMapAllowed(pMemoryMulticastFabric, pGpu) memorymulticastfabricIsGpuMapAllowed_DISPATCH(pMemoryMulticastFabric, pGpu) #define memorymulticastfabricGetMapAddrSpace(pMemoryMulticastFabric, pCallContext, mapFlags, pAddrSpace) memorymulticastfabricGetMapAddrSpace_DISPATCH(pMemoryMulticastFabric, pCallContext, mapFlags, pAddrSpace) #define memorymulticastfabricCtrlGetInfo(pMemoryMulticastFabric, pParams) memorymulticastfabricCtrlGetInfo_DISPATCH(pMemoryMulticastFabric, pParams) #define memorymulticastfabricCtrlAttachMem(pMemoryMulticastFabric, pParams) memorymulticastfabricCtrlAttachMem_DISPATCH(pMemoryMulticastFabric, pParams) +#define memorymulticastfabricCtrlDetachMem(pMemoryMulticastFabric, pParams) memorymulticastfabricCtrlDetachMem_DISPATCH(pMemoryMulticastFabric, pParams) +#define memorymulticastfabricCtrlAttachGpu(pMemoryMulticastFabric, pParams) memorymulticastfabricCtrlAttachGpu_DISPATCH(pMemoryMulticastFabric, pParams) #define memorymulticastfabricCtrlRegisterEvent(pMemoryMulticastFabric, pParams) memorymulticastfabricCtrlRegisterEvent_DISPATCH(pMemoryMulticastFabric, pParams) #define memorymulticastfabricCheckMemInterUnmap(pMemory, bSubdeviceHandleProvided) memorymulticastfabricCheckMemInterUnmap_DISPATCH(pMemory, bSubdeviceHandleProvided) +#define memorymulticastfabricShareCallback(pResource, pInvokingClient, pParentRef, pSharePolicy) memorymulticastfabricShareCallback_DISPATCH(pResource, pInvokingClient, pParentRef, pSharePolicy) +#define memorymulticastfabricMapTo(pResource, pParams) memorymulticastfabricMapTo_DISPATCH(pResource, pParams) +#define memorymulticastfabricGetRefCount(pResource) memorymulticastfabricGetRefCount_DISPATCH(pResource) +#define memorymulticastfabricAddAdditionalDependants(pClient, pResource, pReference) memorymulticastfabricAddAdditionalDependants_DISPATCH(pClient, pResource, pReference) +#define memorymulticastfabricControl_Prologue(pResource, pCallContext, pParams) memorymulticastfabricControl_Prologue_DISPATCH(pResource, pCallContext, pParams) +#define memorymulticastfabricUnmapFrom(pResource, pParams) memorymulticastfabricUnmapFrom_DISPATCH(pResource, pParams) +#define memorymulticastfabricControl_Epilogue(pResource, pCallContext, pParams) memorymulticastfabricControl_Epilogue_DISPATCH(pResource, pCallContext, pParams) +#define memorymulticastfabricControlLookup(pResource, pParams, ppEntry) memorymulticastfabricControlLookup_DISPATCH(pResource, pParams, ppEntry) #define memorymulticastfabricUnmap(pMemory, pCallContext, pCpuMapping) memorymulticastfabricUnmap_DISPATCH(pMemory, pCallContext, pCpuMapping) #define memorymulticastfabricGetMemInterMapParams(pMemory, pParams) memorymulticastfabricGetMemInterMapParams_DISPATCH(pMemory, pParams) #define memorymulticastfabricGetMemoryMappingDescriptor(pMemory, ppMemDesc) memorymulticastfabricGetMemoryMappingDescriptor_DISPATCH(pMemory, ppMemDesc) -#define memorymulticastfabricShareCallback(pResource, pInvokingClient, pParentRef, pSharePolicy) memorymulticastfabricShareCallback_DISPATCH(pResource, pInvokingClient, pParentRef, pSharePolicy) #define memorymulticastfabricControlFilter(pResource, pCallContext, pParams) memorymulticastfabricControlFilter_DISPATCH(pResource, pCallContext, pParams) -#define memorymulticastfabricAddAdditionalDependants(pClient, pResource, pReference) memorymulticastfabricAddAdditionalDependants_DISPATCH(pClient, pResource, pReference) -#define memorymulticastfabricGetRefCount(pResource) memorymulticastfabricGetRefCount_DISPATCH(pResource) -#define memorymulticastfabricMapTo(pResource, pParams) memorymulticastfabricMapTo_DISPATCH(pResource, pParams) -#define memorymulticastfabricCheckCopyPermissions(pMemory, pDstGpu, hDstClientNvBool) memorymulticastfabricCheckCopyPermissions_DISPATCH(pMemory, pDstGpu, hDstClientNvBool) +#define memorymulticastfabricControlSerialization_Prologue(pResource, pCallContext, pParams) memorymulticastfabricControlSerialization_Prologue_DISPATCH(pResource, pCallContext, pParams) +#define memorymulticastfabricCheckCopyPermissions(pMemory, pDstGpu, pDstDevice) memorymulticastfabricCheckCopyPermissions_DISPATCH(pMemory, pDstGpu, pDstDevice) #define memorymulticastfabricPreDestruct(pResource) memorymulticastfabricPreDestruct_DISPATCH(pResource) #define memorymulticastfabricIsDuplicate(pMemory, hMemory, pDuplicate) memorymulticastfabricIsDuplicate_DISPATCH(pMemory, hMemory, pDuplicate) -#define memorymulticastfabricUnmapFrom(pResource, pParams) memorymulticastfabricUnmapFrom_DISPATCH(pResource, pParams) -#define memorymulticastfabricControl_Epilogue(pResource, pCallContext, pParams) memorymulticastfabricControl_Epilogue_DISPATCH(pResource, pCallContext, pParams) -#define memorymulticastfabricControlLookup(pResource, pParams, ppEntry) memorymulticastfabricControlLookup_DISPATCH(pResource, pParams, ppEntry) +#define memorymulticastfabricControlSerialization_Epilogue(pResource, pCallContext, pParams) memorymulticastfabricControlSerialization_Epilogue_DISPATCH(pResource, pCallContext, pParams) #define memorymulticastfabricMap(pMemory, pCallContext, pParams, pCpuMapping) memorymulticastfabricMap_DISPATCH(pMemory, pCallContext, pParams, pCpuMapping) #define memorymulticastfabricAccessCallback(pResource, pInvokingClient, pAllocParams, accessRight) memorymulticastfabricAccessCallback_DISPATCH(pResource, pInvokingClient, pAllocParams, accessRight) NvBool memorymulticastfabricCanCopy_IMPL(struct MemoryMulticastFabric *pMemoryMulticastFabric); @@ -265,12 +271,6 @@ return pMemoryMulticastFabric->__memorymulticastfabricControl__(pMemoryMulticastFabric, pCallContext, pParams); } -NV_STATUS memorymulticastfabricControl_Prologue_IMPL(struct MemoryMulticastFabric *pMemoryMulticastFabric, CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams); - -static inline NV_STATUS memorymulticastfabricControl_Prologue_DISPATCH(struct MemoryMulticastFabric *pMemoryMulticastFabric, CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { - return pMemoryMulticastFabric->__memorymulticastfabricControl_Prologue__(pMemoryMulticastFabric, pCallContext, pParams); -} - NvBool memorymulticastfabricIsGpuMapAllowed_IMPL(struct MemoryMulticastFabric *pMemoryMulticastFabric, struct OBJGPU *pGpu); static inline NvBool memorymulticastfabricIsGpuMapAllowed_DISPATCH(struct MemoryMulticastFabric *pMemoryMulticastFabric, struct OBJGPU *pGpu) { @@ -295,6 +295,18 @@ return pMemoryMulticastFabric->__memorymulticastfabricCtrlAttachMem__(pMemoryMulticastFabric, pParams); } +NV_STATUS memorymulticastfabricCtrlDetachMem_IMPL(struct MemoryMulticastFabric *pMemoryMulticastFabric, NV00FD_CTRL_DETACH_MEM_PARAMS *pParams); + +static inline NV_STATUS memorymulticastfabricCtrlDetachMem_DISPATCH(struct MemoryMulticastFabric *pMemoryMulticastFabric, NV00FD_CTRL_DETACH_MEM_PARAMS *pParams) { + return pMemoryMulticastFabric->__memorymulticastfabricCtrlDetachMem__(pMemoryMulticastFabric, pParams); +} + +NV_STATUS memorymulticastfabricCtrlAttachGpu_IMPL(struct MemoryMulticastFabric *pMemoryMulticastFabric, NV00FD_CTRL_ATTACH_GPU_PARAMS *pParams); + +static inline NV_STATUS memorymulticastfabricCtrlAttachGpu_DISPATCH(struct MemoryMulticastFabric *pMemoryMulticastFabric, NV00FD_CTRL_ATTACH_GPU_PARAMS *pParams) { + return pMemoryMulticastFabric->__memorymulticastfabricCtrlAttachGpu__(pMemoryMulticastFabric, pParams); +} + NV_STATUS memorymulticastfabricCtrlRegisterEvent_IMPL(struct MemoryMulticastFabric *pMemoryMulticastFabric, NV00FD_CTRL_REGISTER_EVENT_PARAMS *pParams); static inline NV_STATUS memorymulticastfabricCtrlRegisterEvent_DISPATCH(struct MemoryMulticastFabric *pMemoryMulticastFabric, NV00FD_CTRL_REGISTER_EVENT_PARAMS *pParams) { @@ -305,6 +317,38 @@ return pMemory->__memorymulticastfabricCheckMemInterUnmap__(pMemory, bSubdeviceHandleProvided); } +static inline NvBool memorymulticastfabricShareCallback_DISPATCH(struct MemoryMulticastFabric *pResource, struct RsClient *pInvokingClient, struct RsResourceRef *pParentRef, RS_SHARE_POLICY *pSharePolicy) { + return pResource->__memorymulticastfabricShareCallback__(pResource, pInvokingClient, pParentRef, pSharePolicy); +} + +static inline NV_STATUS memorymulticastfabricMapTo_DISPATCH(struct MemoryMulticastFabric *pResource, RS_RES_MAP_TO_PARAMS *pParams) { + return pResource->__memorymulticastfabricMapTo__(pResource, pParams); +} + +static inline NvU32 memorymulticastfabricGetRefCount_DISPATCH(struct MemoryMulticastFabric *pResource) { + return pResource->__memorymulticastfabricGetRefCount__(pResource); +} + +static inline void memorymulticastfabricAddAdditionalDependants_DISPATCH(struct RsClient *pClient, struct MemoryMulticastFabric *pResource, RsResourceRef *pReference) { + pResource->__memorymulticastfabricAddAdditionalDependants__(pClient, pResource, pReference); +} + +static inline NV_STATUS memorymulticastfabricControl_Prologue_DISPATCH(struct MemoryMulticastFabric *pResource, CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return pResource->__memorymulticastfabricControl_Prologue__(pResource, pCallContext, pParams); +} + +static inline NV_STATUS memorymulticastfabricUnmapFrom_DISPATCH(struct MemoryMulticastFabric *pResource, RS_RES_UNMAP_FROM_PARAMS *pParams) { + return pResource->__memorymulticastfabricUnmapFrom__(pResource, pParams); +} + +static inline void memorymulticastfabricControl_Epilogue_DISPATCH(struct MemoryMulticastFabric *pResource, CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + pResource->__memorymulticastfabricControl_Epilogue__(pResource, pCallContext, pParams); +} + +static inline NV_STATUS memorymulticastfabricControlLookup_DISPATCH(struct MemoryMulticastFabric *pResource, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams, const struct NVOC_EXPORTED_METHOD_DEF **ppEntry) { + return pResource->__memorymulticastfabricControlLookup__(pResource, pParams, ppEntry); +} + static inline NV_STATUS memorymulticastfabricUnmap_DISPATCH(struct MemoryMulticastFabric *pMemory, CALL_CONTEXT *pCallContext, RsCpuMapping *pCpuMapping) { return pMemory->__memorymulticastfabricUnmap__(pMemory, pCallContext, pCpuMapping); } @@ -317,28 +361,16 @@ return pMemory->__memorymulticastfabricGetMemoryMappingDescriptor__(pMemory, ppMemDesc); } -static inline NvBool memorymulticastfabricShareCallback_DISPATCH(struct MemoryMulticastFabric *pResource, struct RsClient *pInvokingClient, struct RsResourceRef *pParentRef, RS_SHARE_POLICY *pSharePolicy) { - return pResource->__memorymulticastfabricShareCallback__(pResource, pInvokingClient, pParentRef, pSharePolicy); -} - static inline NV_STATUS memorymulticastfabricControlFilter_DISPATCH(struct MemoryMulticastFabric *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { return pResource->__memorymulticastfabricControlFilter__(pResource, pCallContext, pParams); } -static inline void memorymulticastfabricAddAdditionalDependants_DISPATCH(struct RsClient *pClient, struct MemoryMulticastFabric *pResource, RsResourceRef *pReference) { - pResource->__memorymulticastfabricAddAdditionalDependants__(pClient, pResource, pReference); -} - -static inline NvU32 memorymulticastfabricGetRefCount_DISPATCH(struct MemoryMulticastFabric *pResource) { - return pResource->__memorymulticastfabricGetRefCount__(pResource); -} - -static inline NV_STATUS memorymulticastfabricMapTo_DISPATCH(struct MemoryMulticastFabric *pResource, RS_RES_MAP_TO_PARAMS *pParams) { - return pResource->__memorymulticastfabricMapTo__(pResource, pParams); +static inline NV_STATUS memorymulticastfabricControlSerialization_Prologue_DISPATCH(struct MemoryMulticastFabric *pResource, CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return pResource->__memorymulticastfabricControlSerialization_Prologue__(pResource, pCallContext, pParams); } -static inline NV_STATUS memorymulticastfabricCheckCopyPermissions_DISPATCH(struct MemoryMulticastFabric *pMemory, struct OBJGPU *pDstGpu, NvHandle hDstClientNvBool) { - return pMemory->__memorymulticastfabricCheckCopyPermissions__(pMemory, pDstGpu, hDstClientNvBool); +static inline NV_STATUS memorymulticastfabricCheckCopyPermissions_DISPATCH(struct MemoryMulticastFabric *pMemory, struct OBJGPU *pDstGpu, struct Device *pDstDevice) { + return pMemory->__memorymulticastfabricCheckCopyPermissions__(pMemory, pDstGpu, pDstDevice); } static inline void memorymulticastfabricPreDestruct_DISPATCH(struct MemoryMulticastFabric *pResource) { @@ -349,16 +381,8 @@ return pMemory->__memorymulticastfabricIsDuplicate__(pMemory, hMemory, pDuplicate); } -static inline NV_STATUS memorymulticastfabricUnmapFrom_DISPATCH(struct MemoryMulticastFabric *pResource, RS_RES_UNMAP_FROM_PARAMS *pParams) { - return pResource->__memorymulticastfabricUnmapFrom__(pResource, pParams); -} - -static inline void memorymulticastfabricControl_Epilogue_DISPATCH(struct MemoryMulticastFabric *pResource, CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { - pResource->__memorymulticastfabricControl_Epilogue__(pResource, pCallContext, pParams); -} - -static inline NV_STATUS memorymulticastfabricControlLookup_DISPATCH(struct MemoryMulticastFabric *pResource, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams, const struct NVOC_EXPORTED_METHOD_DEF **ppEntry) { - return pResource->__memorymulticastfabricControlLookup__(pResource, pParams, ppEntry); +static inline void memorymulticastfabricControlSerialization_Epilogue_DISPATCH(struct MemoryMulticastFabric *pResource, CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + pResource->__memorymulticastfabricControlSerialization_Epilogue__(pResource, pCallContext, pParams); } static inline NV_STATUS memorymulticastfabricMap_DISPATCH(struct MemoryMulticastFabric *pMemory, CALL_CONTEXT *pCallContext, struct RS_CPU_MAP_PARAMS *pParams, RsCpuMapping *pCpuMapping) { @@ -378,8 +402,8 @@ #undef PRIVATE_FIELD -void memorymulticastfabricTeamSetupResponseCallback(OBJGPU *pGpu, - NV2080_CTRL_NVLINK_INBAND_RECEIVED_DATA_PARAMS *pMessage); +NV_STATUS memorymulticastfabricTeamSetupResponseCallback(NvU32 gpuInstance, + NV2080_CTRL_NVLINK_INBAND_RECEIVED_DATA_PARAMS *pMessage); #endif // _MEMORYMULTICASTFABRIC_H_ diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/generated/g_mem_nvoc.c nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_mem_nvoc.c --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/generated/g_mem_nvoc.c 2023-10-25 20:27:13.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_mem_nvoc.c 2024-03-05 22:18:34.000000000 +0000 @@ -128,6 +128,14 @@ resAddAdditionalDependants(pClient, (struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_Memory_RsResource.offset), pReference); } +static NV_STATUS __nvoc_thunk_RsResource_memUnmapFrom(struct Memory *pResource, RS_RES_UNMAP_FROM_PARAMS *pParams) { + return resUnmapFrom((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_Memory_RsResource.offset), pParams); +} + +static NV_STATUS __nvoc_thunk_RmResource_memControlSerialization_Prologue(struct Memory *pResource, CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return rmresControlSerialization_Prologue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_Memory_RmResource.offset), pCallContext, pParams); +} + static NV_STATUS __nvoc_thunk_RmResource_memControl_Prologue(struct Memory *pResource, CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { return rmresControl_Prologue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_Memory_RmResource.offset), pCallContext, pParams); } @@ -136,16 +144,16 @@ return resCanCopy((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_Memory_RsResource.offset)); } -static NV_STATUS __nvoc_thunk_RsResource_memMapTo(struct Memory *pResource, RS_RES_MAP_TO_PARAMS *pParams) { - return resMapTo((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_Memory_RsResource.offset), pParams); -} - static void __nvoc_thunk_RsResource_memPreDestruct(struct Memory *pResource) { resPreDestruct((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_Memory_RsResource.offset)); } -static NV_STATUS __nvoc_thunk_RsResource_memUnmapFrom(struct Memory *pResource, RS_RES_UNMAP_FROM_PARAMS *pParams) { - return resUnmapFrom((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_Memory_RsResource.offset), pParams); +static NV_STATUS __nvoc_thunk_RsResource_memMapTo(struct Memory *pResource, RS_RES_MAP_TO_PARAMS *pParams) { + return resMapTo((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_Memory_RsResource.offset), pParams); +} + +static void __nvoc_thunk_RmResource_memControlSerialization_Epilogue(struct Memory *pResource, CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + rmresControlSerialization_Epilogue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_Memory_RmResource.offset), pCallContext, pParams); } static void __nvoc_thunk_RmResource_memControl_Epilogue(struct Memory *pResource, CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { @@ -366,15 +374,19 @@ pThis->__memAddAdditionalDependants__ = &__nvoc_thunk_RsResource_memAddAdditionalDependants; + pThis->__memUnmapFrom__ = &__nvoc_thunk_RsResource_memUnmapFrom; + + pThis->__memControlSerialization_Prologue__ = &__nvoc_thunk_RmResource_memControlSerialization_Prologue; + pThis->__memControl_Prologue__ = &__nvoc_thunk_RmResource_memControl_Prologue; pThis->__memCanCopy__ = &__nvoc_thunk_RsResource_memCanCopy; - pThis->__memMapTo__ = &__nvoc_thunk_RsResource_memMapTo; - pThis->__memPreDestruct__ = &__nvoc_thunk_RsResource_memPreDestruct; - pThis->__memUnmapFrom__ = &__nvoc_thunk_RsResource_memUnmapFrom; + pThis->__memMapTo__ = &__nvoc_thunk_RsResource_memMapTo; + + pThis->__memControlSerialization_Epilogue__ = &__nvoc_thunk_RmResource_memControlSerialization_Epilogue; pThis->__memControl_Epilogue__ = &__nvoc_thunk_RmResource_memControl_Epilogue; @@ -403,13 +415,16 @@ Object *pParentObj; Memory *pThis; - pThis = portMemAllocNonPaged(sizeof(Memory)); - if (pThis == NULL) return NV_ERR_NO_MEMORY; + status = __nvoc_handleObjCreateMemAlloc(createFlags, sizeof(Memory), (void**)&pThis, (void**)ppThis); + if (status != NV_OK) + return status; portMemSet(pThis, 0, sizeof(Memory)); __nvoc_initRtti(staticCast(pThis, Dynamic), &__nvoc_class_def_Memory); + pThis->__nvoc_base_RmResource.__nvoc_base_RsResource.__nvoc_base_Object.createFlags = createFlags; + if (pParent != NULL && !(createFlags & NVOC_OBJ_CREATE_FLAGS_PARENT_HALSPEC_ONLY)) { pParentObj = dynamicCast(pParent, Object); @@ -425,11 +440,17 @@ if (status != NV_OK) goto __nvoc_objCreate_Memory_cleanup; *ppThis = pThis; + return NV_OK; __nvoc_objCreate_Memory_cleanup: // do not call destructors here since the constructor already called them - portMemFree(pThis); + if (createFlags & NVOC_OBJ_CREATE_FLAGS_IN_PLACE_CONSTRUCT) + portMemSet(pThis, 0, sizeof(Memory)); + else + portMemFree(pThis); + + // coverity[leaked_storage:FALSE] return status; } diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/generated/g_mem_nvoc.h nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_mem_nvoc.h --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/generated/g_mem_nvoc.h 2023-10-25 20:27:13.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_mem_nvoc.h 2024-03-05 22:18:34.000000000 +0000 @@ -7,7 +7,7 @@ #endif /* - * SPDX-FileCopyrightText: Copyright (c) 1993-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 1993-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -120,7 +120,6 @@ NvU64 guestMSIAddr; // MSI address allocated by guest OS NvU32 guestMSIData; // MSI data value set by guest OS void *pVgpuVfioRef; // Reference to vgpu device in nvidia-vgpu-vfio module - void *pVmBusHostChannel; // VmBus Host channel to communicated the event with the Guest void *pEventDpc; // DPC event to pass the interrupt } VGPU_NS_INTR; @@ -157,7 +156,7 @@ NV_STATUS (*__memGetMemInterMapParams__)(struct Memory *, RMRES_MEM_INTER_MAP_PARAMS *); NV_STATUS (*__memCheckMemInterUnmap__)(struct Memory *, NvBool); NV_STATUS (*__memGetMemoryMappingDescriptor__)(struct Memory *, MEMORY_DESCRIPTOR **); - NV_STATUS (*__memCheckCopyPermissions__)(struct Memory *, struct OBJGPU *, NvHandle); + NV_STATUS (*__memCheckCopyPermissions__)(struct Memory *, struct OBJGPU *, struct Device *); NV_STATUS (*__memIsReady__)(struct Memory *, NvBool); NvBool (*__memIsGpuMapAllowed__)(struct Memory *, struct OBJGPU *); NV_STATUS (*__memCtrlCmdGetSurfaceCompressionCoverageLvm__)(struct Memory *, NV0041_CTRL_GET_SURFACE_COMPRESSION_COVERAGE_PARAMS *); @@ -170,11 +169,13 @@ NvU32 (*__memGetRefCount__)(struct Memory *); NV_STATUS (*__memControlFilter__)(struct Memory *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); void (*__memAddAdditionalDependants__)(struct RsClient *, struct Memory *, RsResourceRef *); + NV_STATUS (*__memUnmapFrom__)(struct Memory *, RS_RES_UNMAP_FROM_PARAMS *); + NV_STATUS (*__memControlSerialization_Prologue__)(struct Memory *, CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); NV_STATUS (*__memControl_Prologue__)(struct Memory *, CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); NvBool (*__memCanCopy__)(struct Memory *); - NV_STATUS (*__memMapTo__)(struct Memory *, RS_RES_MAP_TO_PARAMS *); void (*__memPreDestruct__)(struct Memory *); - NV_STATUS (*__memUnmapFrom__)(struct Memory *, RS_RES_UNMAP_FROM_PARAMS *); + NV_STATUS (*__memMapTo__)(struct Memory *, RS_RES_MAP_TO_PARAMS *); + void (*__memControlSerialization_Epilogue__)(struct Memory *, CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); void (*__memControl_Epilogue__)(struct Memory *, CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); NV_STATUS (*__memControlLookup__)(struct Memory *, struct RS_RES_CONTROL_PARAMS_INTERNAL *, const struct NVOC_EXPORTED_METHOD_DEF **); NvBool (*__memAccessCallback__)(struct Memory *, struct RsClient *, void *, RsAccessRight); @@ -243,7 +244,7 @@ #define memGetMemInterMapParams(pMemory, pParams) memGetMemInterMapParams_DISPATCH(pMemory, pParams) #define memCheckMemInterUnmap(pMemory, bSubdeviceHandleProvided) memCheckMemInterUnmap_DISPATCH(pMemory, bSubdeviceHandleProvided) #define memGetMemoryMappingDescriptor(pMemory, ppMemDesc) memGetMemoryMappingDescriptor_DISPATCH(pMemory, ppMemDesc) -#define memCheckCopyPermissions(pMemory, pDstGpu, hDstClientNvBool) memCheckCopyPermissions_DISPATCH(pMemory, pDstGpu, hDstClientNvBool) +#define memCheckCopyPermissions(pMemory, pDstGpu, pDstDevice) memCheckCopyPermissions_DISPATCH(pMemory, pDstGpu, pDstDevice) #define memIsReady(pMemory, bCopyConstructorContext) memIsReady_DISPATCH(pMemory, bCopyConstructorContext) #define memIsGpuMapAllowed(pMemory, pGpu) memIsGpuMapAllowed_DISPATCH(pMemory, pGpu) #define memCtrlCmdGetSurfaceCompressionCoverageLvm(pMemory, pParams) memCtrlCmdGetSurfaceCompressionCoverageLvm_DISPATCH(pMemory, pParams) @@ -256,11 +257,13 @@ #define memGetRefCount(pResource) memGetRefCount_DISPATCH(pResource) #define memControlFilter(pResource, pCallContext, pParams) memControlFilter_DISPATCH(pResource, pCallContext, pParams) #define memAddAdditionalDependants(pClient, pResource, pReference) memAddAdditionalDependants_DISPATCH(pClient, pResource, pReference) +#define memUnmapFrom(pResource, pParams) memUnmapFrom_DISPATCH(pResource, pParams) +#define memControlSerialization_Prologue(pResource, pCallContext, pParams) memControlSerialization_Prologue_DISPATCH(pResource, pCallContext, pParams) #define memControl_Prologue(pResource, pCallContext, pParams) memControl_Prologue_DISPATCH(pResource, pCallContext, pParams) #define memCanCopy(pResource) memCanCopy_DISPATCH(pResource) -#define memMapTo(pResource, pParams) memMapTo_DISPATCH(pResource, pParams) #define memPreDestruct(pResource) memPreDestruct_DISPATCH(pResource) -#define memUnmapFrom(pResource, pParams) memUnmapFrom_DISPATCH(pResource, pParams) +#define memMapTo(pResource, pParams) memMapTo_DISPATCH(pResource, pParams) +#define memControlSerialization_Epilogue(pResource, pCallContext, pParams) memControlSerialization_Epilogue_DISPATCH(pResource, pCallContext, pParams) #define memControl_Epilogue(pResource, pCallContext, pParams) memControl_Epilogue_DISPATCH(pResource, pCallContext, pParams) #define memControlLookup(pResource, pParams, ppEntry) memControlLookup_DISPATCH(pResource, pParams, ppEntry) #define memAccessCallback(pResource, pInvokingClient, pAllocParams, accessRight) memAccessCallback_DISPATCH(pResource, pInvokingClient, pAllocParams, accessRight) @@ -314,12 +317,12 @@ return pMemory->__memGetMemoryMappingDescriptor__(pMemory, ppMemDesc); } -static inline NV_STATUS memCheckCopyPermissions_ac1694(struct Memory *pMemory, struct OBJGPU *pDstGpu, NvHandle hDstClientNvBool) { +static inline NV_STATUS memCheckCopyPermissions_ac1694(struct Memory *pMemory, struct OBJGPU *pDstGpu, struct Device *pDstDevice) { return NV_OK; } -static inline NV_STATUS memCheckCopyPermissions_DISPATCH(struct Memory *pMemory, struct OBJGPU *pDstGpu, NvHandle hDstClientNvBool) { - return pMemory->__memCheckCopyPermissions__(pMemory, pDstGpu, hDstClientNvBool); +static inline NV_STATUS memCheckCopyPermissions_DISPATCH(struct Memory *pMemory, struct OBJGPU *pDstGpu, struct Device *pDstDevice) { + return pMemory->__memCheckCopyPermissions__(pMemory, pDstGpu, pDstDevice); } NV_STATUS memIsReady_IMPL(struct Memory *pMemory, NvBool bCopyConstructorContext); @@ -388,6 +391,14 @@ pResource->__memAddAdditionalDependants__(pClient, pResource, pReference); } +static inline NV_STATUS memUnmapFrom_DISPATCH(struct Memory *pResource, RS_RES_UNMAP_FROM_PARAMS *pParams) { + return pResource->__memUnmapFrom__(pResource, pParams); +} + +static inline NV_STATUS memControlSerialization_Prologue_DISPATCH(struct Memory *pResource, CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return pResource->__memControlSerialization_Prologue__(pResource, pCallContext, pParams); +} + static inline NV_STATUS memControl_Prologue_DISPATCH(struct Memory *pResource, CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { return pResource->__memControl_Prologue__(pResource, pCallContext, pParams); } @@ -396,16 +407,16 @@ return pResource->__memCanCopy__(pResource); } -static inline NV_STATUS memMapTo_DISPATCH(struct Memory *pResource, RS_RES_MAP_TO_PARAMS *pParams) { - return pResource->__memMapTo__(pResource, pParams); -} - static inline void memPreDestruct_DISPATCH(struct Memory *pResource) { pResource->__memPreDestruct__(pResource); } -static inline NV_STATUS memUnmapFrom_DISPATCH(struct Memory *pResource, RS_RES_UNMAP_FROM_PARAMS *pParams) { - return pResource->__memUnmapFrom__(pResource, pParams); +static inline NV_STATUS memMapTo_DISPATCH(struct Memory *pResource, RS_RES_MAP_TO_PARAMS *pParams) { + return pResource->__memMapTo__(pResource, pParams); +} + +static inline void memControlSerialization_Epilogue_DISPATCH(struct Memory *pResource, CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + pResource->__memControlSerialization_Epilogue__(pResource, pCallContext, pParams); } static inline void memControl_Epilogue_DISPATCH(struct Memory *pResource, CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/generated/g_mig_config_session_nvoc.c nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_mig_config_session_nvoc.c --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/generated/g_mig_config_session_nvoc.c 2023-10-25 20:27:13.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_mig_config_session_nvoc.c 2024-03-05 22:18:35.000000000 +0000 @@ -116,8 +116,12 @@ resAddAdditionalDependants(pClient, (struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_MIGConfigSession_RsResource.offset), pReference); } -static NV_STATUS __nvoc_thunk_RsResource_migconfigsessionUnmap(struct MIGConfigSession *pResource, struct CALL_CONTEXT *pCallContext, RsCpuMapping *pCpuMapping) { - return resUnmap((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_MIGConfigSession_RsResource.offset), pCallContext, pCpuMapping); +static NV_STATUS __nvoc_thunk_RsResource_migconfigsessionUnmapFrom(struct MIGConfigSession *pResource, RS_RES_UNMAP_FROM_PARAMS *pParams) { + return resUnmapFrom((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_MIGConfigSession_RsResource.offset), pParams); +} + +static NV_STATUS __nvoc_thunk_RmResource_migconfigsessionControlSerialization_Prologue(struct MIGConfigSession *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return rmresControlSerialization_Prologue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_MIGConfigSession_RmResource.offset), pCallContext, pParams); } static NV_STATUS __nvoc_thunk_RmResource_migconfigsessionControl_Prologue(struct MIGConfigSession *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { @@ -128,22 +132,26 @@ return resCanCopy((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_MIGConfigSession_RsResource.offset)); } -static NV_STATUS __nvoc_thunk_RsResource_migconfigsessionMapTo(struct MIGConfigSession *pResource, RS_RES_MAP_TO_PARAMS *pParams) { - return resMapTo((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_MIGConfigSession_RsResource.offset), pParams); +static NV_STATUS __nvoc_thunk_RsResource_migconfigsessionUnmap(struct MIGConfigSession *pResource, struct CALL_CONTEXT *pCallContext, RsCpuMapping *pCpuMapping) { + return resUnmap((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_MIGConfigSession_RsResource.offset), pCallContext, pCpuMapping); } static void __nvoc_thunk_RsResource_migconfigsessionPreDestruct(struct MIGConfigSession *pResource) { resPreDestruct((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_MIGConfigSession_RsResource.offset)); } -static NV_STATUS __nvoc_thunk_RsResource_migconfigsessionUnmapFrom(struct MIGConfigSession *pResource, RS_RES_UNMAP_FROM_PARAMS *pParams) { - return resUnmapFrom((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_MIGConfigSession_RsResource.offset), pParams); +static NV_STATUS __nvoc_thunk_RsResource_migconfigsessionMapTo(struct MIGConfigSession *pResource, RS_RES_MAP_TO_PARAMS *pParams) { + return resMapTo((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_MIGConfigSession_RsResource.offset), pParams); } static NV_STATUS __nvoc_thunk_RsResource_migconfigsessionIsDuplicate(struct MIGConfigSession *pResource, NvHandle hMemory, NvBool *pDuplicate) { return resIsDuplicate((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_MIGConfigSession_RsResource.offset), hMemory, pDuplicate); } +static void __nvoc_thunk_RmResource_migconfigsessionControlSerialization_Epilogue(struct MIGConfigSession *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + rmresControlSerialization_Epilogue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_MIGConfigSession_RmResource.offset), pCallContext, pParams); +} + static void __nvoc_thunk_RmResource_migconfigsessionControl_Epilogue(struct MIGConfigSession *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { rmresControl_Epilogue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_MIGConfigSession_RmResource.offset), pCallContext, pParams); } @@ -215,20 +223,24 @@ pThis->__migconfigsessionAddAdditionalDependants__ = &__nvoc_thunk_RsResource_migconfigsessionAddAdditionalDependants; - pThis->__migconfigsessionUnmap__ = &__nvoc_thunk_RsResource_migconfigsessionUnmap; + pThis->__migconfigsessionUnmapFrom__ = &__nvoc_thunk_RsResource_migconfigsessionUnmapFrom; + + pThis->__migconfigsessionControlSerialization_Prologue__ = &__nvoc_thunk_RmResource_migconfigsessionControlSerialization_Prologue; pThis->__migconfigsessionControl_Prologue__ = &__nvoc_thunk_RmResource_migconfigsessionControl_Prologue; pThis->__migconfigsessionCanCopy__ = &__nvoc_thunk_RsResource_migconfigsessionCanCopy; - pThis->__migconfigsessionMapTo__ = &__nvoc_thunk_RsResource_migconfigsessionMapTo; + pThis->__migconfigsessionUnmap__ = &__nvoc_thunk_RsResource_migconfigsessionUnmap; pThis->__migconfigsessionPreDestruct__ = &__nvoc_thunk_RsResource_migconfigsessionPreDestruct; - pThis->__migconfigsessionUnmapFrom__ = &__nvoc_thunk_RsResource_migconfigsessionUnmapFrom; + pThis->__migconfigsessionMapTo__ = &__nvoc_thunk_RsResource_migconfigsessionMapTo; pThis->__migconfigsessionIsDuplicate__ = &__nvoc_thunk_RsResource_migconfigsessionIsDuplicate; + pThis->__migconfigsessionControlSerialization_Epilogue__ = &__nvoc_thunk_RmResource_migconfigsessionControlSerialization_Epilogue; + pThis->__migconfigsessionControl_Epilogue__ = &__nvoc_thunk_RmResource_migconfigsessionControl_Epilogue; pThis->__migconfigsessionControlLookup__ = &__nvoc_thunk_RsResource_migconfigsessionControlLookup; @@ -258,13 +270,16 @@ Object *pParentObj; MIGConfigSession *pThis; - pThis = portMemAllocNonPaged(sizeof(MIGConfigSession)); - if (pThis == NULL) return NV_ERR_NO_MEMORY; + status = __nvoc_handleObjCreateMemAlloc(createFlags, sizeof(MIGConfigSession), (void**)&pThis, (void**)ppThis); + if (status != NV_OK) + return status; portMemSet(pThis, 0, sizeof(MIGConfigSession)); __nvoc_initRtti(staticCast(pThis, Dynamic), &__nvoc_class_def_MIGConfigSession); + pThis->__nvoc_base_RmResource.__nvoc_base_RsResource.__nvoc_base_Object.createFlags = createFlags; + if (pParent != NULL && !(createFlags & NVOC_OBJ_CREATE_FLAGS_PARENT_HALSPEC_ONLY)) { pParentObj = dynamicCast(pParent, Object); @@ -280,11 +295,17 @@ if (status != NV_OK) goto __nvoc_objCreate_MIGConfigSession_cleanup; *ppThis = pThis; + return NV_OK; __nvoc_objCreate_MIGConfigSession_cleanup: // do not call destructors here since the constructor already called them - portMemFree(pThis); + if (createFlags & NVOC_OBJ_CREATE_FLAGS_IN_PLACE_CONSTRUCT) + portMemSet(pThis, 0, sizeof(MIGConfigSession)); + else + portMemFree(pThis); + + // coverity[leaked_storage:FALSE] return status; } diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/generated/g_mig_config_session_nvoc.h nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_mig_config_session_nvoc.h --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/generated/g_mig_config_session_nvoc.h 2023-10-25 20:27:13.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_mig_config_session_nvoc.h 2024-03-05 22:18:35.000000000 +0000 @@ -7,7 +7,7 @@ #endif /* - * SPDX-FileCopyrightText: Copyright (c) 2019-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2019-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -73,18 +73,20 @@ NvU32 (*__migconfigsessionGetRefCount__)(struct MIGConfigSession *); NV_STATUS (*__migconfigsessionControlFilter__)(struct MIGConfigSession *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); void (*__migconfigsessionAddAdditionalDependants__)(struct RsClient *, struct MIGConfigSession *, RsResourceRef *); - NV_STATUS (*__migconfigsessionUnmap__)(struct MIGConfigSession *, struct CALL_CONTEXT *, RsCpuMapping *); + NV_STATUS (*__migconfigsessionUnmapFrom__)(struct MIGConfigSession *, RS_RES_UNMAP_FROM_PARAMS *); + NV_STATUS (*__migconfigsessionControlSerialization_Prologue__)(struct MIGConfigSession *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); NV_STATUS (*__migconfigsessionControl_Prologue__)(struct MIGConfigSession *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); NvBool (*__migconfigsessionCanCopy__)(struct MIGConfigSession *); - NV_STATUS (*__migconfigsessionMapTo__)(struct MIGConfigSession *, RS_RES_MAP_TO_PARAMS *); + NV_STATUS (*__migconfigsessionUnmap__)(struct MIGConfigSession *, struct CALL_CONTEXT *, RsCpuMapping *); void (*__migconfigsessionPreDestruct__)(struct MIGConfigSession *); - NV_STATUS (*__migconfigsessionUnmapFrom__)(struct MIGConfigSession *, RS_RES_UNMAP_FROM_PARAMS *); + NV_STATUS (*__migconfigsessionMapTo__)(struct MIGConfigSession *, RS_RES_MAP_TO_PARAMS *); NV_STATUS (*__migconfigsessionIsDuplicate__)(struct MIGConfigSession *, NvHandle, NvBool *); + void (*__migconfigsessionControlSerialization_Epilogue__)(struct MIGConfigSession *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); void (*__migconfigsessionControl_Epilogue__)(struct MIGConfigSession *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); NV_STATUS (*__migconfigsessionControlLookup__)(struct MIGConfigSession *, struct RS_RES_CONTROL_PARAMS_INTERNAL *, const struct NVOC_EXPORTED_METHOD_DEF **); NV_STATUS (*__migconfigsessionMap__)(struct MIGConfigSession *, struct CALL_CONTEXT *, RS_CPU_MAP_PARAMS *, RsCpuMapping *); NvBool (*__migconfigsessionAccessCallback__)(struct MIGConfigSession *, struct RsClient *, void *, RsAccessRight); - NvU64 dupedCapDescriptor; + NvU64 PRIVATE_FIELD(dupedCapDescriptor); }; #ifndef __NVOC_CLASS_MIGConfigSession_TYPEDEF__ @@ -123,13 +125,15 @@ #define migconfigsessionGetRefCount(pResource) migconfigsessionGetRefCount_DISPATCH(pResource) #define migconfigsessionControlFilter(pResource, pCallContext, pParams) migconfigsessionControlFilter_DISPATCH(pResource, pCallContext, pParams) #define migconfigsessionAddAdditionalDependants(pClient, pResource, pReference) migconfigsessionAddAdditionalDependants_DISPATCH(pClient, pResource, pReference) -#define migconfigsessionUnmap(pResource, pCallContext, pCpuMapping) migconfigsessionUnmap_DISPATCH(pResource, pCallContext, pCpuMapping) +#define migconfigsessionUnmapFrom(pResource, pParams) migconfigsessionUnmapFrom_DISPATCH(pResource, pParams) +#define migconfigsessionControlSerialization_Prologue(pResource, pCallContext, pParams) migconfigsessionControlSerialization_Prologue_DISPATCH(pResource, pCallContext, pParams) #define migconfigsessionControl_Prologue(pResource, pCallContext, pParams) migconfigsessionControl_Prologue_DISPATCH(pResource, pCallContext, pParams) #define migconfigsessionCanCopy(pResource) migconfigsessionCanCopy_DISPATCH(pResource) -#define migconfigsessionMapTo(pResource, pParams) migconfigsessionMapTo_DISPATCH(pResource, pParams) +#define migconfigsessionUnmap(pResource, pCallContext, pCpuMapping) migconfigsessionUnmap_DISPATCH(pResource, pCallContext, pCpuMapping) #define migconfigsessionPreDestruct(pResource) migconfigsessionPreDestruct_DISPATCH(pResource) -#define migconfigsessionUnmapFrom(pResource, pParams) migconfigsessionUnmapFrom_DISPATCH(pResource, pParams) +#define migconfigsessionMapTo(pResource, pParams) migconfigsessionMapTo_DISPATCH(pResource, pParams) #define migconfigsessionIsDuplicate(pResource, hMemory, pDuplicate) migconfigsessionIsDuplicate_DISPATCH(pResource, hMemory, pDuplicate) +#define migconfigsessionControlSerialization_Epilogue(pResource, pCallContext, pParams) migconfigsessionControlSerialization_Epilogue_DISPATCH(pResource, pCallContext, pParams) #define migconfigsessionControl_Epilogue(pResource, pCallContext, pParams) migconfigsessionControl_Epilogue_DISPATCH(pResource, pCallContext, pParams) #define migconfigsessionControlLookup(pResource, pParams, ppEntry) migconfigsessionControlLookup_DISPATCH(pResource, pParams, ppEntry) #define migconfigsessionMap(pResource, pCallContext, pParams, pCpuMapping) migconfigsessionMap_DISPATCH(pResource, pCallContext, pParams, pCpuMapping) @@ -166,8 +170,12 @@ pResource->__migconfigsessionAddAdditionalDependants__(pClient, pResource, pReference); } -static inline NV_STATUS migconfigsessionUnmap_DISPATCH(struct MIGConfigSession *pResource, struct CALL_CONTEXT *pCallContext, RsCpuMapping *pCpuMapping) { - return pResource->__migconfigsessionUnmap__(pResource, pCallContext, pCpuMapping); +static inline NV_STATUS migconfigsessionUnmapFrom_DISPATCH(struct MIGConfigSession *pResource, RS_RES_UNMAP_FROM_PARAMS *pParams) { + return pResource->__migconfigsessionUnmapFrom__(pResource, pParams); +} + +static inline NV_STATUS migconfigsessionControlSerialization_Prologue_DISPATCH(struct MIGConfigSession *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return pResource->__migconfigsessionControlSerialization_Prologue__(pResource, pCallContext, pParams); } static inline NV_STATUS migconfigsessionControl_Prologue_DISPATCH(struct MIGConfigSession *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { @@ -178,22 +186,26 @@ return pResource->__migconfigsessionCanCopy__(pResource); } -static inline NV_STATUS migconfigsessionMapTo_DISPATCH(struct MIGConfigSession *pResource, RS_RES_MAP_TO_PARAMS *pParams) { - return pResource->__migconfigsessionMapTo__(pResource, pParams); +static inline NV_STATUS migconfigsessionUnmap_DISPATCH(struct MIGConfigSession *pResource, struct CALL_CONTEXT *pCallContext, RsCpuMapping *pCpuMapping) { + return pResource->__migconfigsessionUnmap__(pResource, pCallContext, pCpuMapping); } static inline void migconfigsessionPreDestruct_DISPATCH(struct MIGConfigSession *pResource) { pResource->__migconfigsessionPreDestruct__(pResource); } -static inline NV_STATUS migconfigsessionUnmapFrom_DISPATCH(struct MIGConfigSession *pResource, RS_RES_UNMAP_FROM_PARAMS *pParams) { - return pResource->__migconfigsessionUnmapFrom__(pResource, pParams); +static inline NV_STATUS migconfigsessionMapTo_DISPATCH(struct MIGConfigSession *pResource, RS_RES_MAP_TO_PARAMS *pParams) { + return pResource->__migconfigsessionMapTo__(pResource, pParams); } static inline NV_STATUS migconfigsessionIsDuplicate_DISPATCH(struct MIGConfigSession *pResource, NvHandle hMemory, NvBool *pDuplicate) { return pResource->__migconfigsessionIsDuplicate__(pResource, hMemory, pDuplicate); } +static inline void migconfigsessionControlSerialization_Epilogue_DISPATCH(struct MIGConfigSession *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + pResource->__migconfigsessionControlSerialization_Epilogue__(pResource, pCallContext, pParams); +} + static inline void migconfigsessionControl_Epilogue_DISPATCH(struct MIGConfigSession *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { pResource->__migconfigsessionControl_Epilogue__(pResource, pCallContext, pParams); } diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/generated/g_mig_monitor_session_nvoc.c nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_mig_monitor_session_nvoc.c --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/generated/g_mig_monitor_session_nvoc.c 2023-10-25 20:27:13.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_mig_monitor_session_nvoc.c 2024-03-05 22:18:35.000000000 +0000 @@ -116,8 +116,12 @@ resAddAdditionalDependants(pClient, (struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_MIGMonitorSession_RsResource.offset), pReference); } -static NV_STATUS __nvoc_thunk_RsResource_migmonitorsessionUnmap(struct MIGMonitorSession *pResource, struct CALL_CONTEXT *pCallContext, RsCpuMapping *pCpuMapping) { - return resUnmap((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_MIGMonitorSession_RsResource.offset), pCallContext, pCpuMapping); +static NV_STATUS __nvoc_thunk_RsResource_migmonitorsessionUnmapFrom(struct MIGMonitorSession *pResource, RS_RES_UNMAP_FROM_PARAMS *pParams) { + return resUnmapFrom((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_MIGMonitorSession_RsResource.offset), pParams); +} + +static NV_STATUS __nvoc_thunk_RmResource_migmonitorsessionControlSerialization_Prologue(struct MIGMonitorSession *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return rmresControlSerialization_Prologue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_MIGMonitorSession_RmResource.offset), pCallContext, pParams); } static NV_STATUS __nvoc_thunk_RmResource_migmonitorsessionControl_Prologue(struct MIGMonitorSession *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { @@ -128,22 +132,26 @@ return resCanCopy((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_MIGMonitorSession_RsResource.offset)); } -static NV_STATUS __nvoc_thunk_RsResource_migmonitorsessionMapTo(struct MIGMonitorSession *pResource, RS_RES_MAP_TO_PARAMS *pParams) { - return resMapTo((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_MIGMonitorSession_RsResource.offset), pParams); +static NV_STATUS __nvoc_thunk_RsResource_migmonitorsessionUnmap(struct MIGMonitorSession *pResource, struct CALL_CONTEXT *pCallContext, RsCpuMapping *pCpuMapping) { + return resUnmap((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_MIGMonitorSession_RsResource.offset), pCallContext, pCpuMapping); } static void __nvoc_thunk_RsResource_migmonitorsessionPreDestruct(struct MIGMonitorSession *pResource) { resPreDestruct((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_MIGMonitorSession_RsResource.offset)); } -static NV_STATUS __nvoc_thunk_RsResource_migmonitorsessionUnmapFrom(struct MIGMonitorSession *pResource, RS_RES_UNMAP_FROM_PARAMS *pParams) { - return resUnmapFrom((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_MIGMonitorSession_RsResource.offset), pParams); +static NV_STATUS __nvoc_thunk_RsResource_migmonitorsessionMapTo(struct MIGMonitorSession *pResource, RS_RES_MAP_TO_PARAMS *pParams) { + return resMapTo((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_MIGMonitorSession_RsResource.offset), pParams); } static NV_STATUS __nvoc_thunk_RsResource_migmonitorsessionIsDuplicate(struct MIGMonitorSession *pResource, NvHandle hMemory, NvBool *pDuplicate) { return resIsDuplicate((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_MIGMonitorSession_RsResource.offset), hMemory, pDuplicate); } +static void __nvoc_thunk_RmResource_migmonitorsessionControlSerialization_Epilogue(struct MIGMonitorSession *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + rmresControlSerialization_Epilogue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_MIGMonitorSession_RmResource.offset), pCallContext, pParams); +} + static void __nvoc_thunk_RmResource_migmonitorsessionControl_Epilogue(struct MIGMonitorSession *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { rmresControl_Epilogue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_MIGMonitorSession_RmResource.offset), pCallContext, pParams); } @@ -215,20 +223,24 @@ pThis->__migmonitorsessionAddAdditionalDependants__ = &__nvoc_thunk_RsResource_migmonitorsessionAddAdditionalDependants; - pThis->__migmonitorsessionUnmap__ = &__nvoc_thunk_RsResource_migmonitorsessionUnmap; + pThis->__migmonitorsessionUnmapFrom__ = &__nvoc_thunk_RsResource_migmonitorsessionUnmapFrom; + + pThis->__migmonitorsessionControlSerialization_Prologue__ = &__nvoc_thunk_RmResource_migmonitorsessionControlSerialization_Prologue; pThis->__migmonitorsessionControl_Prologue__ = &__nvoc_thunk_RmResource_migmonitorsessionControl_Prologue; pThis->__migmonitorsessionCanCopy__ = &__nvoc_thunk_RsResource_migmonitorsessionCanCopy; - pThis->__migmonitorsessionMapTo__ = &__nvoc_thunk_RsResource_migmonitorsessionMapTo; + pThis->__migmonitorsessionUnmap__ = &__nvoc_thunk_RsResource_migmonitorsessionUnmap; pThis->__migmonitorsessionPreDestruct__ = &__nvoc_thunk_RsResource_migmonitorsessionPreDestruct; - pThis->__migmonitorsessionUnmapFrom__ = &__nvoc_thunk_RsResource_migmonitorsessionUnmapFrom; + pThis->__migmonitorsessionMapTo__ = &__nvoc_thunk_RsResource_migmonitorsessionMapTo; pThis->__migmonitorsessionIsDuplicate__ = &__nvoc_thunk_RsResource_migmonitorsessionIsDuplicate; + pThis->__migmonitorsessionControlSerialization_Epilogue__ = &__nvoc_thunk_RmResource_migmonitorsessionControlSerialization_Epilogue; + pThis->__migmonitorsessionControl_Epilogue__ = &__nvoc_thunk_RmResource_migmonitorsessionControl_Epilogue; pThis->__migmonitorsessionControlLookup__ = &__nvoc_thunk_RsResource_migmonitorsessionControlLookup; @@ -258,13 +270,16 @@ Object *pParentObj; MIGMonitorSession *pThis; - pThis = portMemAllocNonPaged(sizeof(MIGMonitorSession)); - if (pThis == NULL) return NV_ERR_NO_MEMORY; + status = __nvoc_handleObjCreateMemAlloc(createFlags, sizeof(MIGMonitorSession), (void**)&pThis, (void**)ppThis); + if (status != NV_OK) + return status; portMemSet(pThis, 0, sizeof(MIGMonitorSession)); __nvoc_initRtti(staticCast(pThis, Dynamic), &__nvoc_class_def_MIGMonitorSession); + pThis->__nvoc_base_RmResource.__nvoc_base_RsResource.__nvoc_base_Object.createFlags = createFlags; + if (pParent != NULL && !(createFlags & NVOC_OBJ_CREATE_FLAGS_PARENT_HALSPEC_ONLY)) { pParentObj = dynamicCast(pParent, Object); @@ -280,11 +295,17 @@ if (status != NV_OK) goto __nvoc_objCreate_MIGMonitorSession_cleanup; *ppThis = pThis; + return NV_OK; __nvoc_objCreate_MIGMonitorSession_cleanup: // do not call destructors here since the constructor already called them - portMemFree(pThis); + if (createFlags & NVOC_OBJ_CREATE_FLAGS_IN_PLACE_CONSTRUCT) + portMemSet(pThis, 0, sizeof(MIGMonitorSession)); + else + portMemFree(pThis); + + // coverity[leaked_storage:FALSE] return status; } diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/generated/g_mig_monitor_session_nvoc.h nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_mig_monitor_session_nvoc.h --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/generated/g_mig_monitor_session_nvoc.h 2023-10-25 20:27:13.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_mig_monitor_session_nvoc.h 2024-03-05 22:18:35.000000000 +0000 @@ -7,7 +7,7 @@ #endif /* - * SPDX-FileCopyrightText: Copyright (c) 2020-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2020-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -74,18 +74,20 @@ NvU32 (*__migmonitorsessionGetRefCount__)(struct MIGMonitorSession *); NV_STATUS (*__migmonitorsessionControlFilter__)(struct MIGMonitorSession *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); void (*__migmonitorsessionAddAdditionalDependants__)(struct RsClient *, struct MIGMonitorSession *, RsResourceRef *); - NV_STATUS (*__migmonitorsessionUnmap__)(struct MIGMonitorSession *, struct CALL_CONTEXT *, RsCpuMapping *); + NV_STATUS (*__migmonitorsessionUnmapFrom__)(struct MIGMonitorSession *, RS_RES_UNMAP_FROM_PARAMS *); + NV_STATUS (*__migmonitorsessionControlSerialization_Prologue__)(struct MIGMonitorSession *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); NV_STATUS (*__migmonitorsessionControl_Prologue__)(struct MIGMonitorSession *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); NvBool (*__migmonitorsessionCanCopy__)(struct MIGMonitorSession *); - NV_STATUS (*__migmonitorsessionMapTo__)(struct MIGMonitorSession *, RS_RES_MAP_TO_PARAMS *); + NV_STATUS (*__migmonitorsessionUnmap__)(struct MIGMonitorSession *, struct CALL_CONTEXT *, RsCpuMapping *); void (*__migmonitorsessionPreDestruct__)(struct MIGMonitorSession *); - NV_STATUS (*__migmonitorsessionUnmapFrom__)(struct MIGMonitorSession *, RS_RES_UNMAP_FROM_PARAMS *); + NV_STATUS (*__migmonitorsessionMapTo__)(struct MIGMonitorSession *, RS_RES_MAP_TO_PARAMS *); NV_STATUS (*__migmonitorsessionIsDuplicate__)(struct MIGMonitorSession *, NvHandle, NvBool *); + void (*__migmonitorsessionControlSerialization_Epilogue__)(struct MIGMonitorSession *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); void (*__migmonitorsessionControl_Epilogue__)(struct MIGMonitorSession *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); NV_STATUS (*__migmonitorsessionControlLookup__)(struct MIGMonitorSession *, struct RS_RES_CONTROL_PARAMS_INTERNAL *, const struct NVOC_EXPORTED_METHOD_DEF **); NV_STATUS (*__migmonitorsessionMap__)(struct MIGMonitorSession *, struct CALL_CONTEXT *, RS_CPU_MAP_PARAMS *, RsCpuMapping *); NvBool (*__migmonitorsessionAccessCallback__)(struct MIGMonitorSession *, struct RsClient *, void *, RsAccessRight); - NvU64 dupedCapDescriptor; + NvU64 PRIVATE_FIELD(dupedCapDescriptor); }; #ifndef __NVOC_CLASS_MIGMonitorSession_TYPEDEF__ @@ -124,13 +126,15 @@ #define migmonitorsessionGetRefCount(pResource) migmonitorsessionGetRefCount_DISPATCH(pResource) #define migmonitorsessionControlFilter(pResource, pCallContext, pParams) migmonitorsessionControlFilter_DISPATCH(pResource, pCallContext, pParams) #define migmonitorsessionAddAdditionalDependants(pClient, pResource, pReference) migmonitorsessionAddAdditionalDependants_DISPATCH(pClient, pResource, pReference) -#define migmonitorsessionUnmap(pResource, pCallContext, pCpuMapping) migmonitorsessionUnmap_DISPATCH(pResource, pCallContext, pCpuMapping) +#define migmonitorsessionUnmapFrom(pResource, pParams) migmonitorsessionUnmapFrom_DISPATCH(pResource, pParams) +#define migmonitorsessionControlSerialization_Prologue(pResource, pCallContext, pParams) migmonitorsessionControlSerialization_Prologue_DISPATCH(pResource, pCallContext, pParams) #define migmonitorsessionControl_Prologue(pResource, pCallContext, pParams) migmonitorsessionControl_Prologue_DISPATCH(pResource, pCallContext, pParams) #define migmonitorsessionCanCopy(pResource) migmonitorsessionCanCopy_DISPATCH(pResource) -#define migmonitorsessionMapTo(pResource, pParams) migmonitorsessionMapTo_DISPATCH(pResource, pParams) +#define migmonitorsessionUnmap(pResource, pCallContext, pCpuMapping) migmonitorsessionUnmap_DISPATCH(pResource, pCallContext, pCpuMapping) #define migmonitorsessionPreDestruct(pResource) migmonitorsessionPreDestruct_DISPATCH(pResource) -#define migmonitorsessionUnmapFrom(pResource, pParams) migmonitorsessionUnmapFrom_DISPATCH(pResource, pParams) +#define migmonitorsessionMapTo(pResource, pParams) migmonitorsessionMapTo_DISPATCH(pResource, pParams) #define migmonitorsessionIsDuplicate(pResource, hMemory, pDuplicate) migmonitorsessionIsDuplicate_DISPATCH(pResource, hMemory, pDuplicate) +#define migmonitorsessionControlSerialization_Epilogue(pResource, pCallContext, pParams) migmonitorsessionControlSerialization_Epilogue_DISPATCH(pResource, pCallContext, pParams) #define migmonitorsessionControl_Epilogue(pResource, pCallContext, pParams) migmonitorsessionControl_Epilogue_DISPATCH(pResource, pCallContext, pParams) #define migmonitorsessionControlLookup(pResource, pParams, ppEntry) migmonitorsessionControlLookup_DISPATCH(pResource, pParams, ppEntry) #define migmonitorsessionMap(pResource, pCallContext, pParams, pCpuMapping) migmonitorsessionMap_DISPATCH(pResource, pCallContext, pParams, pCpuMapping) @@ -167,8 +171,12 @@ pResource->__migmonitorsessionAddAdditionalDependants__(pClient, pResource, pReference); } -static inline NV_STATUS migmonitorsessionUnmap_DISPATCH(struct MIGMonitorSession *pResource, struct CALL_CONTEXT *pCallContext, RsCpuMapping *pCpuMapping) { - return pResource->__migmonitorsessionUnmap__(pResource, pCallContext, pCpuMapping); +static inline NV_STATUS migmonitorsessionUnmapFrom_DISPATCH(struct MIGMonitorSession *pResource, RS_RES_UNMAP_FROM_PARAMS *pParams) { + return pResource->__migmonitorsessionUnmapFrom__(pResource, pParams); +} + +static inline NV_STATUS migmonitorsessionControlSerialization_Prologue_DISPATCH(struct MIGMonitorSession *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return pResource->__migmonitorsessionControlSerialization_Prologue__(pResource, pCallContext, pParams); } static inline NV_STATUS migmonitorsessionControl_Prologue_DISPATCH(struct MIGMonitorSession *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { @@ -179,22 +187,26 @@ return pResource->__migmonitorsessionCanCopy__(pResource); } -static inline NV_STATUS migmonitorsessionMapTo_DISPATCH(struct MIGMonitorSession *pResource, RS_RES_MAP_TO_PARAMS *pParams) { - return pResource->__migmonitorsessionMapTo__(pResource, pParams); +static inline NV_STATUS migmonitorsessionUnmap_DISPATCH(struct MIGMonitorSession *pResource, struct CALL_CONTEXT *pCallContext, RsCpuMapping *pCpuMapping) { + return pResource->__migmonitorsessionUnmap__(pResource, pCallContext, pCpuMapping); } static inline void migmonitorsessionPreDestruct_DISPATCH(struct MIGMonitorSession *pResource) { pResource->__migmonitorsessionPreDestruct__(pResource); } -static inline NV_STATUS migmonitorsessionUnmapFrom_DISPATCH(struct MIGMonitorSession *pResource, RS_RES_UNMAP_FROM_PARAMS *pParams) { - return pResource->__migmonitorsessionUnmapFrom__(pResource, pParams); +static inline NV_STATUS migmonitorsessionMapTo_DISPATCH(struct MIGMonitorSession *pResource, RS_RES_MAP_TO_PARAMS *pParams) { + return pResource->__migmonitorsessionMapTo__(pResource, pParams); } static inline NV_STATUS migmonitorsessionIsDuplicate_DISPATCH(struct MIGMonitorSession *pResource, NvHandle hMemory, NvBool *pDuplicate) { return pResource->__migmonitorsessionIsDuplicate__(pResource, hMemory, pDuplicate); } +static inline void migmonitorsessionControlSerialization_Epilogue_DISPATCH(struct MIGMonitorSession *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + pResource->__migmonitorsessionControlSerialization_Epilogue__(pResource, pCallContext, pParams); +} + static inline void migmonitorsessionControl_Epilogue_DISPATCH(struct MIGMonitorSession *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { pResource->__migmonitorsessionControl_Epilogue__(pResource, pCallContext, pParams); } diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/generated/g_mmu_fault_buffer_nvoc.c nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_mmu_fault_buffer_nvoc.c --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/generated/g_mmu_fault_buffer_nvoc.c 2023-10-25 20:27:13.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_mmu_fault_buffer_nvoc.c 2024-03-05 22:18:35.000000000 +0000 @@ -127,16 +127,16 @@ return gpuresShareCallback((struct GpuResource *)(((unsigned char *)pGpuResource) + __nvoc_rtti_MmuFaultBuffer_GpuResource.offset), pInvokingClient, pParentRef, pSharePolicy); } -static NV_STATUS __nvoc_thunk_RsResource_faultbufMapTo(struct MmuFaultBuffer *pResource, RS_RES_MAP_TO_PARAMS *pParams) { - return resMapTo((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_MmuFaultBuffer_RsResource.offset), pParams); +static NV_STATUS __nvoc_thunk_RmResource_faultbufCheckMemInterUnmap(struct MmuFaultBuffer *pRmResource, NvBool bSubdeviceHandleProvided) { + return rmresCheckMemInterUnmap((struct RmResource *)(((unsigned char *)pRmResource) + __nvoc_rtti_MmuFaultBuffer_RmResource.offset), bSubdeviceHandleProvided); } static NV_STATUS __nvoc_thunk_Notifier_faultbufGetOrAllocNotifShare(struct MmuFaultBuffer *pNotifier, NvHandle hNotifierClient, NvHandle hNotifierResource, struct NotifShare **ppNotifShare) { return notifyGetOrAllocNotifShare((struct Notifier *)(((unsigned char *)pNotifier) + __nvoc_rtti_MmuFaultBuffer_Notifier.offset), hNotifierClient, hNotifierResource, ppNotifShare); } -static NV_STATUS __nvoc_thunk_RmResource_faultbufCheckMemInterUnmap(struct MmuFaultBuffer *pRmResource, NvBool bSubdeviceHandleProvided) { - return rmresCheckMemInterUnmap((struct RmResource *)(((unsigned char *)pRmResource) + __nvoc_rtti_MmuFaultBuffer_RmResource.offset), bSubdeviceHandleProvided); +static NV_STATUS __nvoc_thunk_RsResource_faultbufMapTo(struct MmuFaultBuffer *pResource, RS_RES_MAP_TO_PARAMS *pParams) { + return resMapTo((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_MmuFaultBuffer_RsResource.offset), pParams); } static void __nvoc_thunk_Notifier_faultbufSetNotificationShare(struct MmuFaultBuffer *pNotifier, struct NotifShare *pNotifShare) { @@ -199,6 +199,10 @@ return notifyUnregisterEvent((struct Notifier *)(((unsigned char *)pNotifier) + __nvoc_rtti_MmuFaultBuffer_Notifier.offset), hNotifierClient, hNotifierResource, hEventClient, hEvent); } +static NV_STATUS __nvoc_thunk_RmResource_faultbufControlSerialization_Prologue(struct MmuFaultBuffer *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return rmresControlSerialization_Prologue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_MmuFaultBuffer_RmResource.offset), pCallContext, pParams); +} + static NvBool __nvoc_thunk_RsResource_faultbufCanCopy(struct MmuFaultBuffer *pResource) { return resCanCopy((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_MmuFaultBuffer_RsResource.offset)); } @@ -211,6 +215,10 @@ return resIsDuplicate((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_MmuFaultBuffer_RsResource.offset), hMemory, pDuplicate); } +static void __nvoc_thunk_RmResource_faultbufControlSerialization_Epilogue(struct MmuFaultBuffer *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + rmresControlSerialization_Epilogue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_MmuFaultBuffer_RmResource.offset), pCallContext, pParams); +} + static PEVENTNOTIFICATION *__nvoc_thunk_Notifier_faultbufGetNotificationListPtr(struct MmuFaultBuffer *pNotifier) { return notifyGetNotificationListPtr((struct Notifier *)(((unsigned char *)pNotifier) + __nvoc_rtti_MmuFaultBuffer_Notifier.offset)); } @@ -289,12 +297,42 @@ /*func=*/ "faultbufCtrlCmdMmuFaultBufferUnregisterNonReplayBuf" #endif }, + { /* [4] */ +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x0u) + /*pFunc=*/ (void (*)(void)) NULL, +#else + /*pFunc=*/ (void (*)(void)) faultbufCtrlCmdMmuFaultBufferRegisterReplayBuf_IMPL, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x0u) + /*flags=*/ 0x0u, + /*accessRight=*/0x0u, + /*methodId=*/ 0xc3690103u, + /*paramSize=*/ sizeof(NVC369_CTRL_MMU_FAULT_BUFFER_REGISTER_REPLAY_BUF_PARAMS), + /*pClassInfo=*/ &(__nvoc_class_def_MmuFaultBuffer.classInfo), +#if NV_PRINTF_STRINGS_ALLOWED + /*func=*/ "faultbufCtrlCmdMmuFaultBufferRegisterReplayBuf" +#endif + }, + { /* [5] */ +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x0u) + /*pFunc=*/ (void (*)(void)) NULL, +#else + /*pFunc=*/ (void (*)(void)) faultbufCtrlCmdMmuFaultBufferUnregisterReplayBuf_IMPL, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x0u) + /*flags=*/ 0x0u, + /*accessRight=*/0x0u, + /*methodId=*/ 0xc3690104u, + /*paramSize=*/ sizeof(NVC369_CTRL_MMU_FAULT_BUFFER_UNREGISTER_REPLAY_BUF_PARAMS), + /*pClassInfo=*/ &(__nvoc_class_def_MmuFaultBuffer.classInfo), +#if NV_PRINTF_STRINGS_ALLOWED + /*func=*/ "faultbufCtrlCmdMmuFaultBufferUnregisterReplayBuf" +#endif + }, }; const struct NVOC_EXPORT_INFO __nvoc_export_info_MmuFaultBuffer = { - /*numEntries=*/ 4, + /*numEntries=*/ 6, /*pExportEntries=*/ __nvoc_exported_method_def_MmuFaultBuffer }; @@ -360,6 +398,14 @@ pThis->__faultbufCtrlCmdMmuFaultBufferUnregisterNonReplayBuf__ = &faultbufCtrlCmdMmuFaultBufferUnregisterNonReplayBuf_IMPL; #endif +#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x0u) + pThis->__faultbufCtrlCmdMmuFaultBufferRegisterReplayBuf__ = &faultbufCtrlCmdMmuFaultBufferRegisterReplayBuf_IMPL; +#endif + +#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x0u) + pThis->__faultbufCtrlCmdMmuFaultBufferUnregisterReplayBuf__ = &faultbufCtrlCmdMmuFaultBufferUnregisterReplayBuf_IMPL; +#endif + pThis->__nvoc_base_GpuResource.__gpuresMap__ = &__nvoc_thunk_MmuFaultBuffer_gpuresMap; pThis->__nvoc_base_GpuResource.__gpuresUnmap__ = &__nvoc_thunk_MmuFaultBuffer_gpuresUnmap; @@ -368,11 +414,11 @@ pThis->__faultbufShareCallback__ = &__nvoc_thunk_GpuResource_faultbufShareCallback; - pThis->__faultbufMapTo__ = &__nvoc_thunk_RsResource_faultbufMapTo; + pThis->__faultbufCheckMemInterUnmap__ = &__nvoc_thunk_RmResource_faultbufCheckMemInterUnmap; pThis->__faultbufGetOrAllocNotifShare__ = &__nvoc_thunk_Notifier_faultbufGetOrAllocNotifShare; - pThis->__faultbufCheckMemInterUnmap__ = &__nvoc_thunk_RmResource_faultbufCheckMemInterUnmap; + pThis->__faultbufMapTo__ = &__nvoc_thunk_RsResource_faultbufMapTo; pThis->__faultbufSetNotificationShare__ = &__nvoc_thunk_Notifier_faultbufSetNotificationShare; @@ -404,12 +450,16 @@ pThis->__faultbufUnregisterEvent__ = &__nvoc_thunk_Notifier_faultbufUnregisterEvent; + pThis->__faultbufControlSerialization_Prologue__ = &__nvoc_thunk_RmResource_faultbufControlSerialization_Prologue; + pThis->__faultbufCanCopy__ = &__nvoc_thunk_RsResource_faultbufCanCopy; pThis->__faultbufPreDestruct__ = &__nvoc_thunk_RsResource_faultbufPreDestruct; pThis->__faultbufIsDuplicate__ = &__nvoc_thunk_RsResource_faultbufIsDuplicate; + pThis->__faultbufControlSerialization_Epilogue__ = &__nvoc_thunk_RmResource_faultbufControlSerialization_Epilogue; + pThis->__faultbufGetNotificationListPtr__ = &__nvoc_thunk_Notifier_faultbufGetNotificationListPtr; pThis->__faultbufGetNotificationShare__ = &__nvoc_thunk_Notifier_faultbufGetNotificationShare; @@ -442,13 +492,16 @@ Object *pParentObj; MmuFaultBuffer *pThis; - pThis = portMemAllocNonPaged(sizeof(MmuFaultBuffer)); - if (pThis == NULL) return NV_ERR_NO_MEMORY; + status = __nvoc_handleObjCreateMemAlloc(createFlags, sizeof(MmuFaultBuffer), (void**)&pThis, (void**)ppThis); + if (status != NV_OK) + return status; portMemSet(pThis, 0, sizeof(MmuFaultBuffer)); __nvoc_initRtti(staticCast(pThis, Dynamic), &__nvoc_class_def_MmuFaultBuffer); + pThis->__nvoc_base_GpuResource.__nvoc_base_RmResource.__nvoc_base_RsResource.__nvoc_base_Object.createFlags = createFlags; + if (pParent != NULL && !(createFlags & NVOC_OBJ_CREATE_FLAGS_PARENT_HALSPEC_ONLY)) { pParentObj = dynamicCast(pParent, Object); @@ -464,11 +517,17 @@ if (status != NV_OK) goto __nvoc_objCreate_MmuFaultBuffer_cleanup; *ppThis = pThis; + return NV_OK; __nvoc_objCreate_MmuFaultBuffer_cleanup: // do not call destructors here since the constructor already called them - portMemFree(pThis); + if (createFlags & NVOC_OBJ_CREATE_FLAGS_IN_PLACE_CONSTRUCT) + portMemSet(pThis, 0, sizeof(MmuFaultBuffer)); + else + portMemFree(pThis); + + // coverity[leaked_storage:FALSE] return status; } diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/generated/g_mmu_fault_buffer_nvoc.h nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_mmu_fault_buffer_nvoc.h --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/generated/g_mmu_fault_buffer_nvoc.h 2023-10-25 20:27:13.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_mmu_fault_buffer_nvoc.h 2024-03-05 22:18:35.000000000 +0000 @@ -7,7 +7,7 @@ #endif /* - * SPDX-FileCopyrightText: Copyright (c) 2010-2021 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2010-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -67,10 +67,12 @@ NV_STATUS (*__faultbufCtrlCmdFaultbufferGetRegisterMappings__)(struct MmuFaultBuffer *, NVB069_CTRL_CMD_FAULTBUFFER_GET_REGISTER_MAPPINGS_PARAMS *); NV_STATUS (*__faultbufCtrlCmdMmuFaultBufferRegisterNonReplayBuf__)(struct MmuFaultBuffer *, NVC369_CTRL_MMU_FAULT_BUFFER_REGISTER_NON_REPLAY_BUF_PARAMS *); NV_STATUS (*__faultbufCtrlCmdMmuFaultBufferUnregisterNonReplayBuf__)(struct MmuFaultBuffer *, NVC369_CTRL_MMU_FAULT_BUFFER_UNREGISTER_NON_REPLAY_BUF_PARAMS *); + NV_STATUS (*__faultbufCtrlCmdMmuFaultBufferRegisterReplayBuf__)(struct MmuFaultBuffer *, NVC369_CTRL_MMU_FAULT_BUFFER_REGISTER_REPLAY_BUF_PARAMS *); + NV_STATUS (*__faultbufCtrlCmdMmuFaultBufferUnregisterReplayBuf__)(struct MmuFaultBuffer *, NVC369_CTRL_MMU_FAULT_BUFFER_UNREGISTER_REPLAY_BUF_PARAMS *); NvBool (*__faultbufShareCallback__)(struct MmuFaultBuffer *, struct RsClient *, struct RsResourceRef *, RS_SHARE_POLICY *); - NV_STATUS (*__faultbufMapTo__)(struct MmuFaultBuffer *, RS_RES_MAP_TO_PARAMS *); - NV_STATUS (*__faultbufGetOrAllocNotifShare__)(struct MmuFaultBuffer *, NvHandle, NvHandle, struct NotifShare **); NV_STATUS (*__faultbufCheckMemInterUnmap__)(struct MmuFaultBuffer *, NvBool); + NV_STATUS (*__faultbufGetOrAllocNotifShare__)(struct MmuFaultBuffer *, NvHandle, NvHandle, struct NotifShare **); + NV_STATUS (*__faultbufMapTo__)(struct MmuFaultBuffer *, RS_RES_MAP_TO_PARAMS *); void (*__faultbufSetNotificationShare__)(struct MmuFaultBuffer *, struct NotifShare *); NvU32 (*__faultbufGetRefCount__)(struct MmuFaultBuffer *); void (*__faultbufAddAdditionalDependants__)(struct RsClient *, struct MmuFaultBuffer *, RsResourceRef *); @@ -86,9 +88,11 @@ NV_STATUS (*__faultbufGetMemoryMappingDescriptor__)(struct MmuFaultBuffer *, struct MEMORY_DESCRIPTOR **); NV_STATUS (*__faultbufControlFilter__)(struct MmuFaultBuffer *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); NV_STATUS (*__faultbufUnregisterEvent__)(struct MmuFaultBuffer *, NvHandle, NvHandle, NvHandle, NvHandle); + NV_STATUS (*__faultbufControlSerialization_Prologue__)(struct MmuFaultBuffer *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); NvBool (*__faultbufCanCopy__)(struct MmuFaultBuffer *); void (*__faultbufPreDestruct__)(struct MmuFaultBuffer *); NV_STATUS (*__faultbufIsDuplicate__)(struct MmuFaultBuffer *, NvHandle, NvBool *); + void (*__faultbufControlSerialization_Epilogue__)(struct MmuFaultBuffer *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); PEVENTNOTIFICATION *(*__faultbufGetNotificationListPtr__)(struct MmuFaultBuffer *); struct NotifShare *(*__faultbufGetNotificationShare__)(struct MmuFaultBuffer *); NvBool (*__faultbufAccessCallback__)(struct MmuFaultBuffer *, struct RsClient *, void *, RsAccessRight); @@ -129,10 +133,12 @@ #define faultbufCtrlCmdFaultbufferGetRegisterMappings(pMmuFaultBuffer, pParams) faultbufCtrlCmdFaultbufferGetRegisterMappings_DISPATCH(pMmuFaultBuffer, pParams) #define faultbufCtrlCmdMmuFaultBufferRegisterNonReplayBuf(pMmuFaultBuffer, pParams) faultbufCtrlCmdMmuFaultBufferRegisterNonReplayBuf_DISPATCH(pMmuFaultBuffer, pParams) #define faultbufCtrlCmdMmuFaultBufferUnregisterNonReplayBuf(pMmuFaultBuffer, pParams) faultbufCtrlCmdMmuFaultBufferUnregisterNonReplayBuf_DISPATCH(pMmuFaultBuffer, pParams) +#define faultbufCtrlCmdMmuFaultBufferRegisterReplayBuf(pMmuFaultBuffer, pParams) faultbufCtrlCmdMmuFaultBufferRegisterReplayBuf_DISPATCH(pMmuFaultBuffer, pParams) +#define faultbufCtrlCmdMmuFaultBufferUnregisterReplayBuf(pMmuFaultBuffer, pParams) faultbufCtrlCmdMmuFaultBufferUnregisterReplayBuf_DISPATCH(pMmuFaultBuffer, pParams) #define faultbufShareCallback(pGpuResource, pInvokingClient, pParentRef, pSharePolicy) faultbufShareCallback_DISPATCH(pGpuResource, pInvokingClient, pParentRef, pSharePolicy) -#define faultbufMapTo(pResource, pParams) faultbufMapTo_DISPATCH(pResource, pParams) -#define faultbufGetOrAllocNotifShare(pNotifier, hNotifierClient, hNotifierResource, ppNotifShare) faultbufGetOrAllocNotifShare_DISPATCH(pNotifier, hNotifierClient, hNotifierResource, ppNotifShare) #define faultbufCheckMemInterUnmap(pRmResource, bSubdeviceHandleProvided) faultbufCheckMemInterUnmap_DISPATCH(pRmResource, bSubdeviceHandleProvided) +#define faultbufGetOrAllocNotifShare(pNotifier, hNotifierClient, hNotifierResource, ppNotifShare) faultbufGetOrAllocNotifShare_DISPATCH(pNotifier, hNotifierClient, hNotifierResource, ppNotifShare) +#define faultbufMapTo(pResource, pParams) faultbufMapTo_DISPATCH(pResource, pParams) #define faultbufSetNotificationShare(pNotifier, pNotifShare) faultbufSetNotificationShare_DISPATCH(pNotifier, pNotifShare) #define faultbufGetRefCount(pResource) faultbufGetRefCount_DISPATCH(pResource) #define faultbufAddAdditionalDependants(pClient, pResource, pReference) faultbufAddAdditionalDependants_DISPATCH(pClient, pResource, pReference) @@ -148,9 +154,11 @@ #define faultbufGetMemoryMappingDescriptor(pRmResource, ppMemDesc) faultbufGetMemoryMappingDescriptor_DISPATCH(pRmResource, ppMemDesc) #define faultbufControlFilter(pResource, pCallContext, pParams) faultbufControlFilter_DISPATCH(pResource, pCallContext, pParams) #define faultbufUnregisterEvent(pNotifier, hNotifierClient, hNotifierResource, hEventClient, hEvent) faultbufUnregisterEvent_DISPATCH(pNotifier, hNotifierClient, hNotifierResource, hEventClient, hEvent) +#define faultbufControlSerialization_Prologue(pResource, pCallContext, pParams) faultbufControlSerialization_Prologue_DISPATCH(pResource, pCallContext, pParams) #define faultbufCanCopy(pResource) faultbufCanCopy_DISPATCH(pResource) #define faultbufPreDestruct(pResource) faultbufPreDestruct_DISPATCH(pResource) #define faultbufIsDuplicate(pResource, hMemory, pDuplicate) faultbufIsDuplicate_DISPATCH(pResource, hMemory, pDuplicate) +#define faultbufControlSerialization_Epilogue(pResource, pCallContext, pParams) faultbufControlSerialization_Epilogue_DISPATCH(pResource, pCallContext, pParams) #define faultbufGetNotificationListPtr(pNotifier) faultbufGetNotificationListPtr_DISPATCH(pNotifier) #define faultbufGetNotificationShare(pNotifier) faultbufGetNotificationShare_DISPATCH(pNotifier) #define faultbufAccessCallback(pResource, pInvokingClient, pAllocParams, accessRight) faultbufAccessCallback_DISPATCH(pResource, pInvokingClient, pAllocParams, accessRight) @@ -196,20 +204,32 @@ return pMmuFaultBuffer->__faultbufCtrlCmdMmuFaultBufferUnregisterNonReplayBuf__(pMmuFaultBuffer, pParams); } +NV_STATUS faultbufCtrlCmdMmuFaultBufferRegisterReplayBuf_IMPL(struct MmuFaultBuffer *pMmuFaultBuffer, NVC369_CTRL_MMU_FAULT_BUFFER_REGISTER_REPLAY_BUF_PARAMS *pParams); + +static inline NV_STATUS faultbufCtrlCmdMmuFaultBufferRegisterReplayBuf_DISPATCH(struct MmuFaultBuffer *pMmuFaultBuffer, NVC369_CTRL_MMU_FAULT_BUFFER_REGISTER_REPLAY_BUF_PARAMS *pParams) { + return pMmuFaultBuffer->__faultbufCtrlCmdMmuFaultBufferRegisterReplayBuf__(pMmuFaultBuffer, pParams); +} + +NV_STATUS faultbufCtrlCmdMmuFaultBufferUnregisterReplayBuf_IMPL(struct MmuFaultBuffer *pMmuFaultBuffer, NVC369_CTRL_MMU_FAULT_BUFFER_UNREGISTER_REPLAY_BUF_PARAMS *pParams); + +static inline NV_STATUS faultbufCtrlCmdMmuFaultBufferUnregisterReplayBuf_DISPATCH(struct MmuFaultBuffer *pMmuFaultBuffer, NVC369_CTRL_MMU_FAULT_BUFFER_UNREGISTER_REPLAY_BUF_PARAMS *pParams) { + return pMmuFaultBuffer->__faultbufCtrlCmdMmuFaultBufferUnregisterReplayBuf__(pMmuFaultBuffer, pParams); +} + static inline NvBool faultbufShareCallback_DISPATCH(struct MmuFaultBuffer *pGpuResource, struct RsClient *pInvokingClient, struct RsResourceRef *pParentRef, RS_SHARE_POLICY *pSharePolicy) { return pGpuResource->__faultbufShareCallback__(pGpuResource, pInvokingClient, pParentRef, pSharePolicy); } -static inline NV_STATUS faultbufMapTo_DISPATCH(struct MmuFaultBuffer *pResource, RS_RES_MAP_TO_PARAMS *pParams) { - return pResource->__faultbufMapTo__(pResource, pParams); +static inline NV_STATUS faultbufCheckMemInterUnmap_DISPATCH(struct MmuFaultBuffer *pRmResource, NvBool bSubdeviceHandleProvided) { + return pRmResource->__faultbufCheckMemInterUnmap__(pRmResource, bSubdeviceHandleProvided); } static inline NV_STATUS faultbufGetOrAllocNotifShare_DISPATCH(struct MmuFaultBuffer *pNotifier, NvHandle hNotifierClient, NvHandle hNotifierResource, struct NotifShare **ppNotifShare) { return pNotifier->__faultbufGetOrAllocNotifShare__(pNotifier, hNotifierClient, hNotifierResource, ppNotifShare); } -static inline NV_STATUS faultbufCheckMemInterUnmap_DISPATCH(struct MmuFaultBuffer *pRmResource, NvBool bSubdeviceHandleProvided) { - return pRmResource->__faultbufCheckMemInterUnmap__(pRmResource, bSubdeviceHandleProvided); +static inline NV_STATUS faultbufMapTo_DISPATCH(struct MmuFaultBuffer *pResource, RS_RES_MAP_TO_PARAMS *pParams) { + return pResource->__faultbufMapTo__(pResource, pParams); } static inline void faultbufSetNotificationShare_DISPATCH(struct MmuFaultBuffer *pNotifier, struct NotifShare *pNotifShare) { @@ -272,6 +292,10 @@ return pNotifier->__faultbufUnregisterEvent__(pNotifier, hNotifierClient, hNotifierResource, hEventClient, hEvent); } +static inline NV_STATUS faultbufControlSerialization_Prologue_DISPATCH(struct MmuFaultBuffer *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return pResource->__faultbufControlSerialization_Prologue__(pResource, pCallContext, pParams); +} + static inline NvBool faultbufCanCopy_DISPATCH(struct MmuFaultBuffer *pResource) { return pResource->__faultbufCanCopy__(pResource); } @@ -284,6 +308,10 @@ return pResource->__faultbufIsDuplicate__(pResource, hMemory, pDuplicate); } +static inline void faultbufControlSerialization_Epilogue_DISPATCH(struct MmuFaultBuffer *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + pResource->__faultbufControlSerialization_Epilogue__(pResource, pCallContext, pParams); +} + static inline PEVENTNOTIFICATION *faultbufGetNotificationListPtr_DISPATCH(struct MmuFaultBuffer *pNotifier) { return pNotifier->__faultbufGetNotificationListPtr__(pNotifier); } diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/generated/g_mps_api_nvoc.c nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_mps_api_nvoc.c --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/generated/g_mps_api_nvoc.c 2023-10-25 20:27:14.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_mps_api_nvoc.c 2024-03-05 22:18:35.000000000 +0000 @@ -116,8 +116,12 @@ resAddAdditionalDependants(pClient, (struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_MpsApi_RsResource.offset), pReference); } -static NV_STATUS __nvoc_thunk_RsResource_mpsApiUnmap(struct MpsApi *pResource, struct CALL_CONTEXT *pCallContext, RsCpuMapping *pCpuMapping) { - return resUnmap((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_MpsApi_RsResource.offset), pCallContext, pCpuMapping); +static NV_STATUS __nvoc_thunk_RsResource_mpsApiUnmapFrom(struct MpsApi *pResource, RS_RES_UNMAP_FROM_PARAMS *pParams) { + return resUnmapFrom((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_MpsApi_RsResource.offset), pParams); +} + +static NV_STATUS __nvoc_thunk_RmResource_mpsApiControlSerialization_Prologue(struct MpsApi *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return rmresControlSerialization_Prologue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_MpsApi_RmResource.offset), pCallContext, pParams); } static NV_STATUS __nvoc_thunk_RmResource_mpsApiControl_Prologue(struct MpsApi *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { @@ -128,22 +132,26 @@ return resCanCopy((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_MpsApi_RsResource.offset)); } -static NV_STATUS __nvoc_thunk_RsResource_mpsApiMapTo(struct MpsApi *pResource, RS_RES_MAP_TO_PARAMS *pParams) { - return resMapTo((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_MpsApi_RsResource.offset), pParams); +static NV_STATUS __nvoc_thunk_RsResource_mpsApiUnmap(struct MpsApi *pResource, struct CALL_CONTEXT *pCallContext, RsCpuMapping *pCpuMapping) { + return resUnmap((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_MpsApi_RsResource.offset), pCallContext, pCpuMapping); } static void __nvoc_thunk_RsResource_mpsApiPreDestruct(struct MpsApi *pResource) { resPreDestruct((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_MpsApi_RsResource.offset)); } -static NV_STATUS __nvoc_thunk_RsResource_mpsApiUnmapFrom(struct MpsApi *pResource, RS_RES_UNMAP_FROM_PARAMS *pParams) { - return resUnmapFrom((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_MpsApi_RsResource.offset), pParams); +static NV_STATUS __nvoc_thunk_RsResource_mpsApiMapTo(struct MpsApi *pResource, RS_RES_MAP_TO_PARAMS *pParams) { + return resMapTo((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_MpsApi_RsResource.offset), pParams); } static NV_STATUS __nvoc_thunk_RsResource_mpsApiIsDuplicate(struct MpsApi *pResource, NvHandle hMemory, NvBool *pDuplicate) { return resIsDuplicate((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_MpsApi_RsResource.offset), hMemory, pDuplicate); } +static void __nvoc_thunk_RmResource_mpsApiControlSerialization_Epilogue(struct MpsApi *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + rmresControlSerialization_Epilogue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_MpsApi_RmResource.offset), pCallContext, pParams); +} + static void __nvoc_thunk_RmResource_mpsApiControl_Epilogue(struct MpsApi *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { rmresControl_Epilogue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_MpsApi_RmResource.offset), pCallContext, pParams); } @@ -215,20 +223,24 @@ pThis->__mpsApiAddAdditionalDependants__ = &__nvoc_thunk_RsResource_mpsApiAddAdditionalDependants; - pThis->__mpsApiUnmap__ = &__nvoc_thunk_RsResource_mpsApiUnmap; + pThis->__mpsApiUnmapFrom__ = &__nvoc_thunk_RsResource_mpsApiUnmapFrom; + + pThis->__mpsApiControlSerialization_Prologue__ = &__nvoc_thunk_RmResource_mpsApiControlSerialization_Prologue; pThis->__mpsApiControl_Prologue__ = &__nvoc_thunk_RmResource_mpsApiControl_Prologue; pThis->__mpsApiCanCopy__ = &__nvoc_thunk_RsResource_mpsApiCanCopy; - pThis->__mpsApiMapTo__ = &__nvoc_thunk_RsResource_mpsApiMapTo; + pThis->__mpsApiUnmap__ = &__nvoc_thunk_RsResource_mpsApiUnmap; pThis->__mpsApiPreDestruct__ = &__nvoc_thunk_RsResource_mpsApiPreDestruct; - pThis->__mpsApiUnmapFrom__ = &__nvoc_thunk_RsResource_mpsApiUnmapFrom; + pThis->__mpsApiMapTo__ = &__nvoc_thunk_RsResource_mpsApiMapTo; pThis->__mpsApiIsDuplicate__ = &__nvoc_thunk_RsResource_mpsApiIsDuplicate; + pThis->__mpsApiControlSerialization_Epilogue__ = &__nvoc_thunk_RmResource_mpsApiControlSerialization_Epilogue; + pThis->__mpsApiControl_Epilogue__ = &__nvoc_thunk_RmResource_mpsApiControl_Epilogue; pThis->__mpsApiControlLookup__ = &__nvoc_thunk_RsResource_mpsApiControlLookup; @@ -258,13 +270,16 @@ Object *pParentObj; MpsApi *pThis; - pThis = portMemAllocNonPaged(sizeof(MpsApi)); - if (pThis == NULL) return NV_ERR_NO_MEMORY; + status = __nvoc_handleObjCreateMemAlloc(createFlags, sizeof(MpsApi), (void**)&pThis, (void**)ppThis); + if (status != NV_OK) + return status; portMemSet(pThis, 0, sizeof(MpsApi)); __nvoc_initRtti(staticCast(pThis, Dynamic), &__nvoc_class_def_MpsApi); + pThis->__nvoc_base_RmResource.__nvoc_base_RsResource.__nvoc_base_Object.createFlags = createFlags; + if (pParent != NULL && !(createFlags & NVOC_OBJ_CREATE_FLAGS_PARENT_HALSPEC_ONLY)) { pParentObj = dynamicCast(pParent, Object); @@ -280,11 +295,17 @@ if (status != NV_OK) goto __nvoc_objCreate_MpsApi_cleanup; *ppThis = pThis; + return NV_OK; __nvoc_objCreate_MpsApi_cleanup: // do not call destructors here since the constructor already called them - portMemFree(pThis); + if (createFlags & NVOC_OBJ_CREATE_FLAGS_IN_PLACE_CONSTRUCT) + portMemSet(pThis, 0, sizeof(MpsApi)); + else + portMemFree(pThis); + + // coverity[leaked_storage:FALSE] return status; } diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/generated/g_mps_api_nvoc.h nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_mps_api_nvoc.h --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/generated/g_mps_api_nvoc.h 2023-10-25 20:27:14.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_mps_api_nvoc.h 2024-03-05 22:18:35.000000000 +0000 @@ -78,13 +78,15 @@ NvU32 (*__mpsApiGetRefCount__)(struct MpsApi *); NV_STATUS (*__mpsApiControlFilter__)(struct MpsApi *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); void (*__mpsApiAddAdditionalDependants__)(struct RsClient *, struct MpsApi *, RsResourceRef *); - NV_STATUS (*__mpsApiUnmap__)(struct MpsApi *, struct CALL_CONTEXT *, RsCpuMapping *); + NV_STATUS (*__mpsApiUnmapFrom__)(struct MpsApi *, RS_RES_UNMAP_FROM_PARAMS *); + NV_STATUS (*__mpsApiControlSerialization_Prologue__)(struct MpsApi *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); NV_STATUS (*__mpsApiControl_Prologue__)(struct MpsApi *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); NvBool (*__mpsApiCanCopy__)(struct MpsApi *); - NV_STATUS (*__mpsApiMapTo__)(struct MpsApi *, RS_RES_MAP_TO_PARAMS *); + NV_STATUS (*__mpsApiUnmap__)(struct MpsApi *, struct CALL_CONTEXT *, RsCpuMapping *); void (*__mpsApiPreDestruct__)(struct MpsApi *); - NV_STATUS (*__mpsApiUnmapFrom__)(struct MpsApi *, RS_RES_UNMAP_FROM_PARAMS *); + NV_STATUS (*__mpsApiMapTo__)(struct MpsApi *, RS_RES_MAP_TO_PARAMS *); NV_STATUS (*__mpsApiIsDuplicate__)(struct MpsApi *, NvHandle, NvBool *); + void (*__mpsApiControlSerialization_Epilogue__)(struct MpsApi *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); void (*__mpsApiControl_Epilogue__)(struct MpsApi *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); NV_STATUS (*__mpsApiControlLookup__)(struct MpsApi *, struct RS_RES_CONTROL_PARAMS_INTERNAL *, const struct NVOC_EXPORTED_METHOD_DEF **); NV_STATUS (*__mpsApiMap__)(struct MpsApi *, struct CALL_CONTEXT *, RS_CPU_MAP_PARAMS *, RsCpuMapping *); @@ -127,13 +129,15 @@ #define mpsApiGetRefCount(pResource) mpsApiGetRefCount_DISPATCH(pResource) #define mpsApiControlFilter(pResource, pCallContext, pParams) mpsApiControlFilter_DISPATCH(pResource, pCallContext, pParams) #define mpsApiAddAdditionalDependants(pClient, pResource, pReference) mpsApiAddAdditionalDependants_DISPATCH(pClient, pResource, pReference) -#define mpsApiUnmap(pResource, pCallContext, pCpuMapping) mpsApiUnmap_DISPATCH(pResource, pCallContext, pCpuMapping) +#define mpsApiUnmapFrom(pResource, pParams) mpsApiUnmapFrom_DISPATCH(pResource, pParams) +#define mpsApiControlSerialization_Prologue(pResource, pCallContext, pParams) mpsApiControlSerialization_Prologue_DISPATCH(pResource, pCallContext, pParams) #define mpsApiControl_Prologue(pResource, pCallContext, pParams) mpsApiControl_Prologue_DISPATCH(pResource, pCallContext, pParams) #define mpsApiCanCopy(pResource) mpsApiCanCopy_DISPATCH(pResource) -#define mpsApiMapTo(pResource, pParams) mpsApiMapTo_DISPATCH(pResource, pParams) +#define mpsApiUnmap(pResource, pCallContext, pCpuMapping) mpsApiUnmap_DISPATCH(pResource, pCallContext, pCpuMapping) #define mpsApiPreDestruct(pResource) mpsApiPreDestruct_DISPATCH(pResource) -#define mpsApiUnmapFrom(pResource, pParams) mpsApiUnmapFrom_DISPATCH(pResource, pParams) +#define mpsApiMapTo(pResource, pParams) mpsApiMapTo_DISPATCH(pResource, pParams) #define mpsApiIsDuplicate(pResource, hMemory, pDuplicate) mpsApiIsDuplicate_DISPATCH(pResource, hMemory, pDuplicate) +#define mpsApiControlSerialization_Epilogue(pResource, pCallContext, pParams) mpsApiControlSerialization_Epilogue_DISPATCH(pResource, pCallContext, pParams) #define mpsApiControl_Epilogue(pResource, pCallContext, pParams) mpsApiControl_Epilogue_DISPATCH(pResource, pCallContext, pParams) #define mpsApiControlLookup(pResource, pParams, ppEntry) mpsApiControlLookup_DISPATCH(pResource, pParams, ppEntry) #define mpsApiMap(pResource, pCallContext, pParams, pCpuMapping) mpsApiMap_DISPATCH(pResource, pCallContext, pParams, pCpuMapping) @@ -170,8 +174,12 @@ pResource->__mpsApiAddAdditionalDependants__(pClient, pResource, pReference); } -static inline NV_STATUS mpsApiUnmap_DISPATCH(struct MpsApi *pResource, struct CALL_CONTEXT *pCallContext, RsCpuMapping *pCpuMapping) { - return pResource->__mpsApiUnmap__(pResource, pCallContext, pCpuMapping); +static inline NV_STATUS mpsApiUnmapFrom_DISPATCH(struct MpsApi *pResource, RS_RES_UNMAP_FROM_PARAMS *pParams) { + return pResource->__mpsApiUnmapFrom__(pResource, pParams); +} + +static inline NV_STATUS mpsApiControlSerialization_Prologue_DISPATCH(struct MpsApi *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return pResource->__mpsApiControlSerialization_Prologue__(pResource, pCallContext, pParams); } static inline NV_STATUS mpsApiControl_Prologue_DISPATCH(struct MpsApi *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { @@ -182,22 +190,26 @@ return pResource->__mpsApiCanCopy__(pResource); } -static inline NV_STATUS mpsApiMapTo_DISPATCH(struct MpsApi *pResource, RS_RES_MAP_TO_PARAMS *pParams) { - return pResource->__mpsApiMapTo__(pResource, pParams); +static inline NV_STATUS mpsApiUnmap_DISPATCH(struct MpsApi *pResource, struct CALL_CONTEXT *pCallContext, RsCpuMapping *pCpuMapping) { + return pResource->__mpsApiUnmap__(pResource, pCallContext, pCpuMapping); } static inline void mpsApiPreDestruct_DISPATCH(struct MpsApi *pResource) { pResource->__mpsApiPreDestruct__(pResource); } -static inline NV_STATUS mpsApiUnmapFrom_DISPATCH(struct MpsApi *pResource, RS_RES_UNMAP_FROM_PARAMS *pParams) { - return pResource->__mpsApiUnmapFrom__(pResource, pParams); +static inline NV_STATUS mpsApiMapTo_DISPATCH(struct MpsApi *pResource, RS_RES_MAP_TO_PARAMS *pParams) { + return pResource->__mpsApiMapTo__(pResource, pParams); } static inline NV_STATUS mpsApiIsDuplicate_DISPATCH(struct MpsApi *pResource, NvHandle hMemory, NvBool *pDuplicate) { return pResource->__mpsApiIsDuplicate__(pResource, hMemory, pDuplicate); } +static inline void mpsApiControlSerialization_Epilogue_DISPATCH(struct MpsApi *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + pResource->__mpsApiControlSerialization_Epilogue__(pResource, pCallContext, pParams); +} + static inline void mpsApiControl_Epilogue_DISPATCH(struct MpsApi *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { pResource->__mpsApiControl_Epilogue__(pResource, pCallContext, pParams); } diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/generated/g_no_device_mem_nvoc.c nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_no_device_mem_nvoc.c --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/generated/g_no_device_mem_nvoc.c 2023-10-25 20:27:14.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_no_device_mem_nvoc.c 2024-03-05 22:18:35.000000000 +0000 @@ -101,48 +101,64 @@ return memCheckMemInterUnmap((struct Memory *)(((unsigned char *)pMemory) + __nvoc_rtti_NoDeviceMemory_Memory.offset), bSubdeviceHandleProvided); } -static NV_STATUS __nvoc_thunk_Memory_nodevicememControl(struct NoDeviceMemory *pMemory, CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { - return memControl((struct Memory *)(((unsigned char *)pMemory) + __nvoc_rtti_NoDeviceMemory_Memory.offset), pCallContext, pParams); +static NvBool __nvoc_thunk_RmResource_nodevicememShareCallback(struct NoDeviceMemory *pResource, struct RsClient *pInvokingClient, struct RsResourceRef *pParentRef, RS_SHARE_POLICY *pSharePolicy) { + return rmresShareCallback((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_NoDeviceMemory_RmResource.offset), pInvokingClient, pParentRef, pSharePolicy); } -static NV_STATUS __nvoc_thunk_Memory_nodevicememUnmap(struct NoDeviceMemory *pMemory, CALL_CONTEXT *pCallContext, RsCpuMapping *pCpuMapping) { - return memUnmap((struct Memory *)(((unsigned char *)pMemory) + __nvoc_rtti_NoDeviceMemory_Memory.offset), pCallContext, pCpuMapping); +static NV_STATUS __nvoc_thunk_RsResource_nodevicememMapTo(struct NoDeviceMemory *pResource, RS_RES_MAP_TO_PARAMS *pParams) { + return resMapTo((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_NoDeviceMemory_RsResource.offset), pParams); } -static NV_STATUS __nvoc_thunk_Memory_nodevicememGetMemInterMapParams(struct NoDeviceMemory *pMemory, RMRES_MEM_INTER_MAP_PARAMS *pParams) { - return memGetMemInterMapParams((struct Memory *)(((unsigned char *)pMemory) + __nvoc_rtti_NoDeviceMemory_Memory.offset), pParams); +static NvU32 __nvoc_thunk_RsResource_nodevicememGetRefCount(struct NoDeviceMemory *pResource) { + return resGetRefCount((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_NoDeviceMemory_RsResource.offset)); } -static NV_STATUS __nvoc_thunk_Memory_nodevicememGetMemoryMappingDescriptor(struct NoDeviceMemory *pMemory, MEMORY_DESCRIPTOR **ppMemDesc) { - return memGetMemoryMappingDescriptor((struct Memory *)(((unsigned char *)pMemory) + __nvoc_rtti_NoDeviceMemory_Memory.offset), ppMemDesc); +static void __nvoc_thunk_RsResource_nodevicememAddAdditionalDependants(struct RsClient *pClient, struct NoDeviceMemory *pResource, RsResourceRef *pReference) { + resAddAdditionalDependants(pClient, (struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_NoDeviceMemory_RsResource.offset), pReference); } -static NvBool __nvoc_thunk_RmResource_nodevicememShareCallback(struct NoDeviceMemory *pResource, struct RsClient *pInvokingClient, struct RsResourceRef *pParentRef, RS_SHARE_POLICY *pSharePolicy) { - return rmresShareCallback((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_NoDeviceMemory_RmResource.offset), pInvokingClient, pParentRef, pSharePolicy); +static NV_STATUS __nvoc_thunk_RmResource_nodevicememControl_Prologue(struct NoDeviceMemory *pResource, CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return rmresControl_Prologue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_NoDeviceMemory_RmResource.offset), pCallContext, pParams); } -static NV_STATUS __nvoc_thunk_RsResource_nodevicememControlFilter(struct NoDeviceMemory *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { - return resControlFilter((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_NoDeviceMemory_RsResource.offset), pCallContext, pParams); +static NvBool __nvoc_thunk_Memory_nodevicememIsGpuMapAllowed(struct NoDeviceMemory *pMemory, struct OBJGPU *pGpu) { + return memIsGpuMapAllowed((struct Memory *)(((unsigned char *)pMemory) + __nvoc_rtti_NoDeviceMemory_Memory.offset), pGpu); } -static void __nvoc_thunk_RsResource_nodevicememAddAdditionalDependants(struct RsClient *pClient, struct NoDeviceMemory *pResource, RsResourceRef *pReference) { - resAddAdditionalDependants(pClient, (struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_NoDeviceMemory_RsResource.offset), pReference); +static NV_STATUS __nvoc_thunk_RsResource_nodevicememUnmapFrom(struct NoDeviceMemory *pResource, RS_RES_UNMAP_FROM_PARAMS *pParams) { + return resUnmapFrom((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_NoDeviceMemory_RsResource.offset), pParams); } -static NvU32 __nvoc_thunk_RsResource_nodevicememGetRefCount(struct NoDeviceMemory *pResource) { - return resGetRefCount((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_NoDeviceMemory_RsResource.offset)); +static void __nvoc_thunk_RmResource_nodevicememControl_Epilogue(struct NoDeviceMemory *pResource, CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + rmresControl_Epilogue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_NoDeviceMemory_RmResource.offset), pCallContext, pParams); } -static NV_STATUS __nvoc_thunk_RsResource_nodevicememMapTo(struct NoDeviceMemory *pResource, RS_RES_MAP_TO_PARAMS *pParams) { - return resMapTo((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_NoDeviceMemory_RsResource.offset), pParams); +static NV_STATUS __nvoc_thunk_RsResource_nodevicememControlLookup(struct NoDeviceMemory *pResource, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams, const struct NVOC_EXPORTED_METHOD_DEF **ppEntry) { + return resControlLookup((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_NoDeviceMemory_RsResource.offset), pParams, ppEntry); } -static NV_STATUS __nvoc_thunk_RmResource_nodevicememControl_Prologue(struct NoDeviceMemory *pResource, CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { - return rmresControl_Prologue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_NoDeviceMemory_RmResource.offset), pCallContext, pParams); +static NV_STATUS __nvoc_thunk_Memory_nodevicememControl(struct NoDeviceMemory *pMemory, CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return memControl((struct Memory *)(((unsigned char *)pMemory) + __nvoc_rtti_NoDeviceMemory_Memory.offset), pCallContext, pParams); } -static NvBool __nvoc_thunk_Memory_nodevicememIsGpuMapAllowed(struct NoDeviceMemory *pMemory, struct OBJGPU *pGpu) { - return memIsGpuMapAllowed((struct Memory *)(((unsigned char *)pMemory) + __nvoc_rtti_NoDeviceMemory_Memory.offset), pGpu); +static NV_STATUS __nvoc_thunk_Memory_nodevicememUnmap(struct NoDeviceMemory *pMemory, CALL_CONTEXT *pCallContext, RsCpuMapping *pCpuMapping) { + return memUnmap((struct Memory *)(((unsigned char *)pMemory) + __nvoc_rtti_NoDeviceMemory_Memory.offset), pCallContext, pCpuMapping); +} + +static NV_STATUS __nvoc_thunk_Memory_nodevicememGetMemInterMapParams(struct NoDeviceMemory *pMemory, RMRES_MEM_INTER_MAP_PARAMS *pParams) { + return memGetMemInterMapParams((struct Memory *)(((unsigned char *)pMemory) + __nvoc_rtti_NoDeviceMemory_Memory.offset), pParams); +} + +static NV_STATUS __nvoc_thunk_Memory_nodevicememGetMemoryMappingDescriptor(struct NoDeviceMemory *pMemory, MEMORY_DESCRIPTOR **ppMemDesc) { + return memGetMemoryMappingDescriptor((struct Memory *)(((unsigned char *)pMemory) + __nvoc_rtti_NoDeviceMemory_Memory.offset), ppMemDesc); +} + +static NV_STATUS __nvoc_thunk_RsResource_nodevicememControlFilter(struct NoDeviceMemory *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return resControlFilter((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_NoDeviceMemory_RsResource.offset), pCallContext, pParams); +} + +static NV_STATUS __nvoc_thunk_RmResource_nodevicememControlSerialization_Prologue(struct NoDeviceMemory *pResource, CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return rmresControlSerialization_Prologue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_NoDeviceMemory_RmResource.offset), pCallContext, pParams); } static NvBool __nvoc_thunk_RsResource_nodevicememCanCopy(struct NoDeviceMemory *pResource) { @@ -153,8 +169,8 @@ return memIsReady((struct Memory *)(((unsigned char *)pMemory) + __nvoc_rtti_NoDeviceMemory_Memory.offset), bCopyConstructorContext); } -static NV_STATUS __nvoc_thunk_Memory_nodevicememCheckCopyPermissions(struct NoDeviceMemory *pMemory, struct OBJGPU *pDstGpu, NvHandle hDstClientNvBool) { - return memCheckCopyPermissions((struct Memory *)(((unsigned char *)pMemory) + __nvoc_rtti_NoDeviceMemory_Memory.offset), pDstGpu, hDstClientNvBool); +static NV_STATUS __nvoc_thunk_Memory_nodevicememCheckCopyPermissions(struct NoDeviceMemory *pMemory, struct OBJGPU *pDstGpu, struct Device *pDstDevice) { + return memCheckCopyPermissions((struct Memory *)(((unsigned char *)pMemory) + __nvoc_rtti_NoDeviceMemory_Memory.offset), pDstGpu, pDstDevice); } static void __nvoc_thunk_RsResource_nodevicememPreDestruct(struct NoDeviceMemory *pResource) { @@ -165,16 +181,8 @@ return memIsDuplicate((struct Memory *)(((unsigned char *)pMemory) + __nvoc_rtti_NoDeviceMemory_Memory.offset), hMemory, pDuplicate); } -static NV_STATUS __nvoc_thunk_RsResource_nodevicememUnmapFrom(struct NoDeviceMemory *pResource, RS_RES_UNMAP_FROM_PARAMS *pParams) { - return resUnmapFrom((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_NoDeviceMemory_RsResource.offset), pParams); -} - -static void __nvoc_thunk_RmResource_nodevicememControl_Epilogue(struct NoDeviceMemory *pResource, CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { - rmresControl_Epilogue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_NoDeviceMemory_RmResource.offset), pCallContext, pParams); -} - -static NV_STATUS __nvoc_thunk_RsResource_nodevicememControlLookup(struct NoDeviceMemory *pResource, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams, const struct NVOC_EXPORTED_METHOD_DEF **ppEntry) { - return resControlLookup((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_NoDeviceMemory_RsResource.offset), pParams, ppEntry); +static void __nvoc_thunk_RmResource_nodevicememControlSerialization_Epilogue(struct NoDeviceMemory *pResource, CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + rmresControlSerialization_Epilogue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_NoDeviceMemory_RmResource.offset), pCallContext, pParams); } static NV_STATUS __nvoc_thunk_Memory_nodevicememMap(struct NoDeviceMemory *pMemory, CALL_CONTEXT *pCallContext, struct RS_CPU_MAP_PARAMS *pParams, RsCpuMapping *pCpuMapping) { @@ -230,27 +238,35 @@ pThis->__nodevicememCheckMemInterUnmap__ = &__nvoc_thunk_Memory_nodevicememCheckMemInterUnmap; - pThis->__nodevicememControl__ = &__nvoc_thunk_Memory_nodevicememControl; + pThis->__nodevicememShareCallback__ = &__nvoc_thunk_RmResource_nodevicememShareCallback; - pThis->__nodevicememUnmap__ = &__nvoc_thunk_Memory_nodevicememUnmap; + pThis->__nodevicememMapTo__ = &__nvoc_thunk_RsResource_nodevicememMapTo; - pThis->__nodevicememGetMemInterMapParams__ = &__nvoc_thunk_Memory_nodevicememGetMemInterMapParams; + pThis->__nodevicememGetRefCount__ = &__nvoc_thunk_RsResource_nodevicememGetRefCount; - pThis->__nodevicememGetMemoryMappingDescriptor__ = &__nvoc_thunk_Memory_nodevicememGetMemoryMappingDescriptor; + pThis->__nodevicememAddAdditionalDependants__ = &__nvoc_thunk_RsResource_nodevicememAddAdditionalDependants; - pThis->__nodevicememShareCallback__ = &__nvoc_thunk_RmResource_nodevicememShareCallback; + pThis->__nodevicememControl_Prologue__ = &__nvoc_thunk_RmResource_nodevicememControl_Prologue; - pThis->__nodevicememControlFilter__ = &__nvoc_thunk_RsResource_nodevicememControlFilter; + pThis->__nodevicememIsGpuMapAllowed__ = &__nvoc_thunk_Memory_nodevicememIsGpuMapAllowed; - pThis->__nodevicememAddAdditionalDependants__ = &__nvoc_thunk_RsResource_nodevicememAddAdditionalDependants; + pThis->__nodevicememUnmapFrom__ = &__nvoc_thunk_RsResource_nodevicememUnmapFrom; - pThis->__nodevicememGetRefCount__ = &__nvoc_thunk_RsResource_nodevicememGetRefCount; + pThis->__nodevicememControl_Epilogue__ = &__nvoc_thunk_RmResource_nodevicememControl_Epilogue; - pThis->__nodevicememMapTo__ = &__nvoc_thunk_RsResource_nodevicememMapTo; + pThis->__nodevicememControlLookup__ = &__nvoc_thunk_RsResource_nodevicememControlLookup; - pThis->__nodevicememControl_Prologue__ = &__nvoc_thunk_RmResource_nodevicememControl_Prologue; + pThis->__nodevicememControl__ = &__nvoc_thunk_Memory_nodevicememControl; - pThis->__nodevicememIsGpuMapAllowed__ = &__nvoc_thunk_Memory_nodevicememIsGpuMapAllowed; + pThis->__nodevicememUnmap__ = &__nvoc_thunk_Memory_nodevicememUnmap; + + pThis->__nodevicememGetMemInterMapParams__ = &__nvoc_thunk_Memory_nodevicememGetMemInterMapParams; + + pThis->__nodevicememGetMemoryMappingDescriptor__ = &__nvoc_thunk_Memory_nodevicememGetMemoryMappingDescriptor; + + pThis->__nodevicememControlFilter__ = &__nvoc_thunk_RsResource_nodevicememControlFilter; + + pThis->__nodevicememControlSerialization_Prologue__ = &__nvoc_thunk_RmResource_nodevicememControlSerialization_Prologue; pThis->__nodevicememCanCopy__ = &__nvoc_thunk_RsResource_nodevicememCanCopy; @@ -262,11 +278,7 @@ pThis->__nodevicememIsDuplicate__ = &__nvoc_thunk_Memory_nodevicememIsDuplicate; - pThis->__nodevicememUnmapFrom__ = &__nvoc_thunk_RsResource_nodevicememUnmapFrom; - - pThis->__nodevicememControl_Epilogue__ = &__nvoc_thunk_RmResource_nodevicememControl_Epilogue; - - pThis->__nodevicememControlLookup__ = &__nvoc_thunk_RsResource_nodevicememControlLookup; + pThis->__nodevicememControlSerialization_Epilogue__ = &__nvoc_thunk_RmResource_nodevicememControlSerialization_Epilogue; pThis->__nodevicememMap__ = &__nvoc_thunk_Memory_nodevicememMap; @@ -294,13 +306,16 @@ Object *pParentObj; NoDeviceMemory *pThis; - pThis = portMemAllocNonPaged(sizeof(NoDeviceMemory)); - if (pThis == NULL) return NV_ERR_NO_MEMORY; + status = __nvoc_handleObjCreateMemAlloc(createFlags, sizeof(NoDeviceMemory), (void**)&pThis, (void**)ppThis); + if (status != NV_OK) + return status; portMemSet(pThis, 0, sizeof(NoDeviceMemory)); __nvoc_initRtti(staticCast(pThis, Dynamic), &__nvoc_class_def_NoDeviceMemory); + pThis->__nvoc_base_Memory.__nvoc_base_RmResource.__nvoc_base_RsResource.__nvoc_base_Object.createFlags = createFlags; + if (pParent != NULL && !(createFlags & NVOC_OBJ_CREATE_FLAGS_PARENT_HALSPEC_ONLY)) { pParentObj = dynamicCast(pParent, Object); @@ -316,11 +331,17 @@ if (status != NV_OK) goto __nvoc_objCreate_NoDeviceMemory_cleanup; *ppThis = pThis; + return NV_OK; __nvoc_objCreate_NoDeviceMemory_cleanup: // do not call destructors here since the constructor already called them - portMemFree(pThis); + if (createFlags & NVOC_OBJ_CREATE_FLAGS_IN_PLACE_CONSTRUCT) + portMemSet(pThis, 0, sizeof(NoDeviceMemory)); + else + portMemFree(pThis); + + // coverity[leaked_storage:FALSE] return status; } diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/generated/g_no_device_mem_nvoc.h nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_no_device_mem_nvoc.h --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/generated/g_no_device_mem_nvoc.h 2023-10-25 20:27:14.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_no_device_mem_nvoc.h 2024-03-05 22:18:36.000000000 +0000 @@ -57,25 +57,27 @@ struct NoDeviceMemory *__nvoc_pbase_NoDeviceMemory; NV_STATUS (*__nodevicememGetMapAddrSpace__)(struct NoDeviceMemory *, CALL_CONTEXT *, NvU32, NV_ADDRESS_SPACE *); NV_STATUS (*__nodevicememCheckMemInterUnmap__)(struct NoDeviceMemory *, NvBool); + NvBool (*__nodevicememShareCallback__)(struct NoDeviceMemory *, struct RsClient *, struct RsResourceRef *, RS_SHARE_POLICY *); + NV_STATUS (*__nodevicememMapTo__)(struct NoDeviceMemory *, RS_RES_MAP_TO_PARAMS *); + NvU32 (*__nodevicememGetRefCount__)(struct NoDeviceMemory *); + void (*__nodevicememAddAdditionalDependants__)(struct RsClient *, struct NoDeviceMemory *, RsResourceRef *); + NV_STATUS (*__nodevicememControl_Prologue__)(struct NoDeviceMemory *, CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); + NvBool (*__nodevicememIsGpuMapAllowed__)(struct NoDeviceMemory *, struct OBJGPU *); + NV_STATUS (*__nodevicememUnmapFrom__)(struct NoDeviceMemory *, RS_RES_UNMAP_FROM_PARAMS *); + void (*__nodevicememControl_Epilogue__)(struct NoDeviceMemory *, CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); + NV_STATUS (*__nodevicememControlLookup__)(struct NoDeviceMemory *, struct RS_RES_CONTROL_PARAMS_INTERNAL *, const struct NVOC_EXPORTED_METHOD_DEF **); NV_STATUS (*__nodevicememControl__)(struct NoDeviceMemory *, CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); NV_STATUS (*__nodevicememUnmap__)(struct NoDeviceMemory *, CALL_CONTEXT *, RsCpuMapping *); NV_STATUS (*__nodevicememGetMemInterMapParams__)(struct NoDeviceMemory *, RMRES_MEM_INTER_MAP_PARAMS *); NV_STATUS (*__nodevicememGetMemoryMappingDescriptor__)(struct NoDeviceMemory *, MEMORY_DESCRIPTOR **); - NvBool (*__nodevicememShareCallback__)(struct NoDeviceMemory *, struct RsClient *, struct RsResourceRef *, RS_SHARE_POLICY *); NV_STATUS (*__nodevicememControlFilter__)(struct NoDeviceMemory *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); - void (*__nodevicememAddAdditionalDependants__)(struct RsClient *, struct NoDeviceMemory *, RsResourceRef *); - NvU32 (*__nodevicememGetRefCount__)(struct NoDeviceMemory *); - NV_STATUS (*__nodevicememMapTo__)(struct NoDeviceMemory *, RS_RES_MAP_TO_PARAMS *); - NV_STATUS (*__nodevicememControl_Prologue__)(struct NoDeviceMemory *, CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); - NvBool (*__nodevicememIsGpuMapAllowed__)(struct NoDeviceMemory *, struct OBJGPU *); + NV_STATUS (*__nodevicememControlSerialization_Prologue__)(struct NoDeviceMemory *, CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); NvBool (*__nodevicememCanCopy__)(struct NoDeviceMemory *); NV_STATUS (*__nodevicememIsReady__)(struct NoDeviceMemory *, NvBool); - NV_STATUS (*__nodevicememCheckCopyPermissions__)(struct NoDeviceMemory *, struct OBJGPU *, NvHandle); + NV_STATUS (*__nodevicememCheckCopyPermissions__)(struct NoDeviceMemory *, struct OBJGPU *, struct Device *); void (*__nodevicememPreDestruct__)(struct NoDeviceMemory *); NV_STATUS (*__nodevicememIsDuplicate__)(struct NoDeviceMemory *, NvHandle, NvBool *); - NV_STATUS (*__nodevicememUnmapFrom__)(struct NoDeviceMemory *, RS_RES_UNMAP_FROM_PARAMS *); - void (*__nodevicememControl_Epilogue__)(struct NoDeviceMemory *, CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); - NV_STATUS (*__nodevicememControlLookup__)(struct NoDeviceMemory *, struct RS_RES_CONTROL_PARAMS_INTERNAL *, const struct NVOC_EXPORTED_METHOD_DEF **); + void (*__nodevicememControlSerialization_Epilogue__)(struct NoDeviceMemory *, CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); NV_STATUS (*__nodevicememMap__)(struct NoDeviceMemory *, CALL_CONTEXT *, struct RS_CPU_MAP_PARAMS *, RsCpuMapping *); NvBool (*__nodevicememAccessCallback__)(struct NoDeviceMemory *, struct RsClient *, void *, RsAccessRight); }; @@ -110,25 +112,27 @@ #define nodevicememGetMapAddrSpace(pNoDeviceMemory, pCallContext, mapFlags, pAddrSpace) nodevicememGetMapAddrSpace_DISPATCH(pNoDeviceMemory, pCallContext, mapFlags, pAddrSpace) #define nodevicememCheckMemInterUnmap(pMemory, bSubdeviceHandleProvided) nodevicememCheckMemInterUnmap_DISPATCH(pMemory, bSubdeviceHandleProvided) +#define nodevicememShareCallback(pResource, pInvokingClient, pParentRef, pSharePolicy) nodevicememShareCallback_DISPATCH(pResource, pInvokingClient, pParentRef, pSharePolicy) +#define nodevicememMapTo(pResource, pParams) nodevicememMapTo_DISPATCH(pResource, pParams) +#define nodevicememGetRefCount(pResource) nodevicememGetRefCount_DISPATCH(pResource) +#define nodevicememAddAdditionalDependants(pClient, pResource, pReference) nodevicememAddAdditionalDependants_DISPATCH(pClient, pResource, pReference) +#define nodevicememControl_Prologue(pResource, pCallContext, pParams) nodevicememControl_Prologue_DISPATCH(pResource, pCallContext, pParams) +#define nodevicememIsGpuMapAllowed(pMemory, pGpu) nodevicememIsGpuMapAllowed_DISPATCH(pMemory, pGpu) +#define nodevicememUnmapFrom(pResource, pParams) nodevicememUnmapFrom_DISPATCH(pResource, pParams) +#define nodevicememControl_Epilogue(pResource, pCallContext, pParams) nodevicememControl_Epilogue_DISPATCH(pResource, pCallContext, pParams) +#define nodevicememControlLookup(pResource, pParams, ppEntry) nodevicememControlLookup_DISPATCH(pResource, pParams, ppEntry) #define nodevicememControl(pMemory, pCallContext, pParams) nodevicememControl_DISPATCH(pMemory, pCallContext, pParams) #define nodevicememUnmap(pMemory, pCallContext, pCpuMapping) nodevicememUnmap_DISPATCH(pMemory, pCallContext, pCpuMapping) #define nodevicememGetMemInterMapParams(pMemory, pParams) nodevicememGetMemInterMapParams_DISPATCH(pMemory, pParams) #define nodevicememGetMemoryMappingDescriptor(pMemory, ppMemDesc) nodevicememGetMemoryMappingDescriptor_DISPATCH(pMemory, ppMemDesc) -#define nodevicememShareCallback(pResource, pInvokingClient, pParentRef, pSharePolicy) nodevicememShareCallback_DISPATCH(pResource, pInvokingClient, pParentRef, pSharePolicy) #define nodevicememControlFilter(pResource, pCallContext, pParams) nodevicememControlFilter_DISPATCH(pResource, pCallContext, pParams) -#define nodevicememAddAdditionalDependants(pClient, pResource, pReference) nodevicememAddAdditionalDependants_DISPATCH(pClient, pResource, pReference) -#define nodevicememGetRefCount(pResource) nodevicememGetRefCount_DISPATCH(pResource) -#define nodevicememMapTo(pResource, pParams) nodevicememMapTo_DISPATCH(pResource, pParams) -#define nodevicememControl_Prologue(pResource, pCallContext, pParams) nodevicememControl_Prologue_DISPATCH(pResource, pCallContext, pParams) -#define nodevicememIsGpuMapAllowed(pMemory, pGpu) nodevicememIsGpuMapAllowed_DISPATCH(pMemory, pGpu) +#define nodevicememControlSerialization_Prologue(pResource, pCallContext, pParams) nodevicememControlSerialization_Prologue_DISPATCH(pResource, pCallContext, pParams) #define nodevicememCanCopy(pResource) nodevicememCanCopy_DISPATCH(pResource) #define nodevicememIsReady(pMemory, bCopyConstructorContext) nodevicememIsReady_DISPATCH(pMemory, bCopyConstructorContext) -#define nodevicememCheckCopyPermissions(pMemory, pDstGpu, hDstClientNvBool) nodevicememCheckCopyPermissions_DISPATCH(pMemory, pDstGpu, hDstClientNvBool) +#define nodevicememCheckCopyPermissions(pMemory, pDstGpu, pDstDevice) nodevicememCheckCopyPermissions_DISPATCH(pMemory, pDstGpu, pDstDevice) #define nodevicememPreDestruct(pResource) nodevicememPreDestruct_DISPATCH(pResource) #define nodevicememIsDuplicate(pMemory, hMemory, pDuplicate) nodevicememIsDuplicate_DISPATCH(pMemory, hMemory, pDuplicate) -#define nodevicememUnmapFrom(pResource, pParams) nodevicememUnmapFrom_DISPATCH(pResource, pParams) -#define nodevicememControl_Epilogue(pResource, pCallContext, pParams) nodevicememControl_Epilogue_DISPATCH(pResource, pCallContext, pParams) -#define nodevicememControlLookup(pResource, pParams, ppEntry) nodevicememControlLookup_DISPATCH(pResource, pParams, ppEntry) +#define nodevicememControlSerialization_Epilogue(pResource, pCallContext, pParams) nodevicememControlSerialization_Epilogue_DISPATCH(pResource, pCallContext, pParams) #define nodevicememMap(pMemory, pCallContext, pParams, pCpuMapping) nodevicememMap_DISPATCH(pMemory, pCallContext, pParams, pCpuMapping) #define nodevicememAccessCallback(pResource, pInvokingClient, pAllocParams, accessRight) nodevicememAccessCallback_DISPATCH(pResource, pInvokingClient, pAllocParams, accessRight) NV_STATUS nodevicememGetMapAddrSpace_IMPL(struct NoDeviceMemory *pNoDeviceMemory, CALL_CONTEXT *pCallContext, NvU32 mapFlags, NV_ADDRESS_SPACE *pAddrSpace); @@ -141,48 +145,64 @@ return pMemory->__nodevicememCheckMemInterUnmap__(pMemory, bSubdeviceHandleProvided); } -static inline NV_STATUS nodevicememControl_DISPATCH(struct NoDeviceMemory *pMemory, CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { - return pMemory->__nodevicememControl__(pMemory, pCallContext, pParams); +static inline NvBool nodevicememShareCallback_DISPATCH(struct NoDeviceMemory *pResource, struct RsClient *pInvokingClient, struct RsResourceRef *pParentRef, RS_SHARE_POLICY *pSharePolicy) { + return pResource->__nodevicememShareCallback__(pResource, pInvokingClient, pParentRef, pSharePolicy); } -static inline NV_STATUS nodevicememUnmap_DISPATCH(struct NoDeviceMemory *pMemory, CALL_CONTEXT *pCallContext, RsCpuMapping *pCpuMapping) { - return pMemory->__nodevicememUnmap__(pMemory, pCallContext, pCpuMapping); +static inline NV_STATUS nodevicememMapTo_DISPATCH(struct NoDeviceMemory *pResource, RS_RES_MAP_TO_PARAMS *pParams) { + return pResource->__nodevicememMapTo__(pResource, pParams); } -static inline NV_STATUS nodevicememGetMemInterMapParams_DISPATCH(struct NoDeviceMemory *pMemory, RMRES_MEM_INTER_MAP_PARAMS *pParams) { - return pMemory->__nodevicememGetMemInterMapParams__(pMemory, pParams); +static inline NvU32 nodevicememGetRefCount_DISPATCH(struct NoDeviceMemory *pResource) { + return pResource->__nodevicememGetRefCount__(pResource); } -static inline NV_STATUS nodevicememGetMemoryMappingDescriptor_DISPATCH(struct NoDeviceMemory *pMemory, MEMORY_DESCRIPTOR **ppMemDesc) { - return pMemory->__nodevicememGetMemoryMappingDescriptor__(pMemory, ppMemDesc); +static inline void nodevicememAddAdditionalDependants_DISPATCH(struct RsClient *pClient, struct NoDeviceMemory *pResource, RsResourceRef *pReference) { + pResource->__nodevicememAddAdditionalDependants__(pClient, pResource, pReference); } -static inline NvBool nodevicememShareCallback_DISPATCH(struct NoDeviceMemory *pResource, struct RsClient *pInvokingClient, struct RsResourceRef *pParentRef, RS_SHARE_POLICY *pSharePolicy) { - return pResource->__nodevicememShareCallback__(pResource, pInvokingClient, pParentRef, pSharePolicy); +static inline NV_STATUS nodevicememControl_Prologue_DISPATCH(struct NoDeviceMemory *pResource, CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return pResource->__nodevicememControl_Prologue__(pResource, pCallContext, pParams); } -static inline NV_STATUS nodevicememControlFilter_DISPATCH(struct NoDeviceMemory *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { - return pResource->__nodevicememControlFilter__(pResource, pCallContext, pParams); +static inline NvBool nodevicememIsGpuMapAllowed_DISPATCH(struct NoDeviceMemory *pMemory, struct OBJGPU *pGpu) { + return pMemory->__nodevicememIsGpuMapAllowed__(pMemory, pGpu); } -static inline void nodevicememAddAdditionalDependants_DISPATCH(struct RsClient *pClient, struct NoDeviceMemory *pResource, RsResourceRef *pReference) { - pResource->__nodevicememAddAdditionalDependants__(pClient, pResource, pReference); +static inline NV_STATUS nodevicememUnmapFrom_DISPATCH(struct NoDeviceMemory *pResource, RS_RES_UNMAP_FROM_PARAMS *pParams) { + return pResource->__nodevicememUnmapFrom__(pResource, pParams); } -static inline NvU32 nodevicememGetRefCount_DISPATCH(struct NoDeviceMemory *pResource) { - return pResource->__nodevicememGetRefCount__(pResource); +static inline void nodevicememControl_Epilogue_DISPATCH(struct NoDeviceMemory *pResource, CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + pResource->__nodevicememControl_Epilogue__(pResource, pCallContext, pParams); } -static inline NV_STATUS nodevicememMapTo_DISPATCH(struct NoDeviceMemory *pResource, RS_RES_MAP_TO_PARAMS *pParams) { - return pResource->__nodevicememMapTo__(pResource, pParams); +static inline NV_STATUS nodevicememControlLookup_DISPATCH(struct NoDeviceMemory *pResource, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams, const struct NVOC_EXPORTED_METHOD_DEF **ppEntry) { + return pResource->__nodevicememControlLookup__(pResource, pParams, ppEntry); } -static inline NV_STATUS nodevicememControl_Prologue_DISPATCH(struct NoDeviceMemory *pResource, CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { - return pResource->__nodevicememControl_Prologue__(pResource, pCallContext, pParams); +static inline NV_STATUS nodevicememControl_DISPATCH(struct NoDeviceMemory *pMemory, CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return pMemory->__nodevicememControl__(pMemory, pCallContext, pParams); } -static inline NvBool nodevicememIsGpuMapAllowed_DISPATCH(struct NoDeviceMemory *pMemory, struct OBJGPU *pGpu) { - return pMemory->__nodevicememIsGpuMapAllowed__(pMemory, pGpu); +static inline NV_STATUS nodevicememUnmap_DISPATCH(struct NoDeviceMemory *pMemory, CALL_CONTEXT *pCallContext, RsCpuMapping *pCpuMapping) { + return pMemory->__nodevicememUnmap__(pMemory, pCallContext, pCpuMapping); +} + +static inline NV_STATUS nodevicememGetMemInterMapParams_DISPATCH(struct NoDeviceMemory *pMemory, RMRES_MEM_INTER_MAP_PARAMS *pParams) { + return pMemory->__nodevicememGetMemInterMapParams__(pMemory, pParams); +} + +static inline NV_STATUS nodevicememGetMemoryMappingDescriptor_DISPATCH(struct NoDeviceMemory *pMemory, MEMORY_DESCRIPTOR **ppMemDesc) { + return pMemory->__nodevicememGetMemoryMappingDescriptor__(pMemory, ppMemDesc); +} + +static inline NV_STATUS nodevicememControlFilter_DISPATCH(struct NoDeviceMemory *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return pResource->__nodevicememControlFilter__(pResource, pCallContext, pParams); +} + +static inline NV_STATUS nodevicememControlSerialization_Prologue_DISPATCH(struct NoDeviceMemory *pResource, CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return pResource->__nodevicememControlSerialization_Prologue__(pResource, pCallContext, pParams); } static inline NvBool nodevicememCanCopy_DISPATCH(struct NoDeviceMemory *pResource) { @@ -193,8 +213,8 @@ return pMemory->__nodevicememIsReady__(pMemory, bCopyConstructorContext); } -static inline NV_STATUS nodevicememCheckCopyPermissions_DISPATCH(struct NoDeviceMemory *pMemory, struct OBJGPU *pDstGpu, NvHandle hDstClientNvBool) { - return pMemory->__nodevicememCheckCopyPermissions__(pMemory, pDstGpu, hDstClientNvBool); +static inline NV_STATUS nodevicememCheckCopyPermissions_DISPATCH(struct NoDeviceMemory *pMemory, struct OBJGPU *pDstGpu, struct Device *pDstDevice) { + return pMemory->__nodevicememCheckCopyPermissions__(pMemory, pDstGpu, pDstDevice); } static inline void nodevicememPreDestruct_DISPATCH(struct NoDeviceMemory *pResource) { @@ -205,16 +225,8 @@ return pMemory->__nodevicememIsDuplicate__(pMemory, hMemory, pDuplicate); } -static inline NV_STATUS nodevicememUnmapFrom_DISPATCH(struct NoDeviceMemory *pResource, RS_RES_UNMAP_FROM_PARAMS *pParams) { - return pResource->__nodevicememUnmapFrom__(pResource, pParams); -} - -static inline void nodevicememControl_Epilogue_DISPATCH(struct NoDeviceMemory *pResource, CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { - pResource->__nodevicememControl_Epilogue__(pResource, pCallContext, pParams); -} - -static inline NV_STATUS nodevicememControlLookup_DISPATCH(struct NoDeviceMemory *pResource, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams, const struct NVOC_EXPORTED_METHOD_DEF **ppEntry) { - return pResource->__nodevicememControlLookup__(pResource, pParams, ppEntry); +static inline void nodevicememControlSerialization_Epilogue_DISPATCH(struct NoDeviceMemory *pResource, CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + pResource->__nodevicememControlSerialization_Epilogue__(pResource, pCallContext, pParams); } static inline NV_STATUS nodevicememMap_DISPATCH(struct NoDeviceMemory *pMemory, CALL_CONTEXT *pCallContext, struct RS_CPU_MAP_PARAMS *pParams, RsCpuMapping *pCpuMapping) { diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/generated/g_nv_debug_dump_nvoc.c nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_nv_debug_dump_nvoc.c --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/generated/g_nv_debug_dump_nvoc.c 2023-10-25 20:27:14.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_nv_debug_dump_nvoc.c 2024-03-05 22:18:36.000000000 +0000 @@ -74,10 +74,6 @@ return nvdStateInitLocked(pGpu, (struct NvDebugDump *)(((unsigned char *)pNvd) - __nvoc_rtti_NvDebugDump_OBJENGSTATE.offset)); } -static NV_STATUS __nvoc_thunk_OBJENGSTATE_nvdReconcileTunableState(POBJGPU pGpu, struct NvDebugDump *pEngstate, void *pTunableState) { - return engstateReconcileTunableState(pGpu, (struct OBJENGSTATE *)(((unsigned char *)pEngstate) + __nvoc_rtti_NvDebugDump_OBJENGSTATE.offset), pTunableState); -} - static NV_STATUS __nvoc_thunk_OBJENGSTATE_nvdStateLoad(POBJGPU pGpu, struct NvDebugDump *pEngstate, NvU32 arg0) { return engstateStateLoad(pGpu, (struct OBJENGSTATE *)(((unsigned char *)pEngstate) + __nvoc_rtti_NvDebugDump_OBJENGSTATE.offset), arg0); } @@ -118,30 +114,10 @@ return engstateStatePreInitUnlocked(pGpu, (struct OBJENGSTATE *)(((unsigned char *)pEngstate) + __nvoc_rtti_NvDebugDump_OBJENGSTATE.offset)); } -static NV_STATUS __nvoc_thunk_OBJENGSTATE_nvdGetTunableState(POBJGPU pGpu, struct NvDebugDump *pEngstate, void *pTunableState) { - return engstateGetTunableState(pGpu, (struct OBJENGSTATE *)(((unsigned char *)pEngstate) + __nvoc_rtti_NvDebugDump_OBJENGSTATE.offset), pTunableState); -} - -static NV_STATUS __nvoc_thunk_OBJENGSTATE_nvdCompareTunableState(POBJGPU pGpu, struct NvDebugDump *pEngstate, void *pTunables1, void *pTunables2) { - return engstateCompareTunableState(pGpu, (struct OBJENGSTATE *)(((unsigned char *)pEngstate) + __nvoc_rtti_NvDebugDump_OBJENGSTATE.offset), pTunables1, pTunables2); -} - -static void __nvoc_thunk_OBJENGSTATE_nvdFreeTunableState(POBJGPU pGpu, struct NvDebugDump *pEngstate, void *pTunableState) { - engstateFreeTunableState(pGpu, (struct OBJENGSTATE *)(((unsigned char *)pEngstate) + __nvoc_rtti_NvDebugDump_OBJENGSTATE.offset), pTunableState); -} - static NV_STATUS __nvoc_thunk_OBJENGSTATE_nvdStatePostLoad(POBJGPU pGpu, struct NvDebugDump *pEngstate, NvU32 arg0) { return engstateStatePostLoad(pGpu, (struct OBJENGSTATE *)(((unsigned char *)pEngstate) + __nvoc_rtti_NvDebugDump_OBJENGSTATE.offset), arg0); } -static NV_STATUS __nvoc_thunk_OBJENGSTATE_nvdAllocTunableState(POBJGPU pGpu, struct NvDebugDump *pEngstate, void **ppTunableState) { - return engstateAllocTunableState(pGpu, (struct OBJENGSTATE *)(((unsigned char *)pEngstate) + __nvoc_rtti_NvDebugDump_OBJENGSTATE.offset), ppTunableState); -} - -static NV_STATUS __nvoc_thunk_OBJENGSTATE_nvdSetTunableState(POBJGPU pGpu, struct NvDebugDump *pEngstate, void *pTunableState) { - return engstateSetTunableState(pGpu, (struct OBJENGSTATE *)(((unsigned char *)pEngstate) + __nvoc_rtti_NvDebugDump_OBJENGSTATE.offset), pTunableState); -} - static NvBool __nvoc_thunk_OBJENGSTATE_nvdIsPresent(POBJGPU pGpu, struct NvDebugDump *pEngstate) { return engstateIsPresent(pGpu, (struct OBJENGSTATE *)(((unsigned char *)pEngstate) + __nvoc_rtti_NvDebugDump_OBJENGSTATE.offset)); } @@ -188,8 +164,6 @@ pThis->__nvoc_base_OBJENGSTATE.__engstateStateInitLocked__ = &__nvoc_thunk_NvDebugDump_engstateStateInitLocked; - pThis->__nvdReconcileTunableState__ = &__nvoc_thunk_OBJENGSTATE_nvdReconcileTunableState; - pThis->__nvdStateLoad__ = &__nvoc_thunk_OBJENGSTATE_nvdStateLoad; pThis->__nvdStateUnload__ = &__nvoc_thunk_OBJENGSTATE_nvdStateUnload; @@ -210,18 +184,8 @@ pThis->__nvdStatePreInitUnlocked__ = &__nvoc_thunk_OBJENGSTATE_nvdStatePreInitUnlocked; - pThis->__nvdGetTunableState__ = &__nvoc_thunk_OBJENGSTATE_nvdGetTunableState; - - pThis->__nvdCompareTunableState__ = &__nvoc_thunk_OBJENGSTATE_nvdCompareTunableState; - - pThis->__nvdFreeTunableState__ = &__nvoc_thunk_OBJENGSTATE_nvdFreeTunableState; - pThis->__nvdStatePostLoad__ = &__nvoc_thunk_OBJENGSTATE_nvdStatePostLoad; - pThis->__nvdAllocTunableState__ = &__nvoc_thunk_OBJENGSTATE_nvdAllocTunableState; - - pThis->__nvdSetTunableState__ = &__nvoc_thunk_OBJENGSTATE_nvdSetTunableState; - pThis->__nvdIsPresent__ = &__nvoc_thunk_OBJENGSTATE_nvdIsPresent; } @@ -243,13 +207,16 @@ Object *pParentObj; NvDebugDump *pThis; - pThis = portMemAllocNonPaged(sizeof(NvDebugDump)); - if (pThis == NULL) return NV_ERR_NO_MEMORY; + status = __nvoc_handleObjCreateMemAlloc(createFlags, sizeof(NvDebugDump), (void**)&pThis, (void**)ppThis); + if (status != NV_OK) + return status; portMemSet(pThis, 0, sizeof(NvDebugDump)); __nvoc_initRtti(staticCast(pThis, Dynamic), &__nvoc_class_def_NvDebugDump); + pThis->__nvoc_base_OBJENGSTATE.__nvoc_base_Object.createFlags = createFlags; + if (pParent != NULL && !(createFlags & NVOC_OBJ_CREATE_FLAGS_PARENT_HALSPEC_ONLY)) { pParentObj = dynamicCast(pParent, Object); @@ -265,11 +232,17 @@ if (status != NV_OK) goto __nvoc_objCreate_NvDebugDump_cleanup; *ppThis = pThis; + return NV_OK; __nvoc_objCreate_NvDebugDump_cleanup: // do not call destructors here since the constructor already called them - portMemFree(pThis); + if (createFlags & NVOC_OBJ_CREATE_FLAGS_IN_PLACE_CONSTRUCT) + portMemSet(pThis, 0, sizeof(NvDebugDump)); + else + portMemFree(pThis); + + // coverity[leaked_storage:FALSE] return status; } diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/generated/g_nv_debug_dump_nvoc.h nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_nv_debug_dump_nvoc.h --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/generated/g_nv_debug_dump_nvoc.h 2023-10-25 20:27:14.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_nv_debug_dump_nvoc.h 2024-03-05 22:18:36.000000000 +0000 @@ -59,7 +59,7 @@ #define NV_NVD_ERROR_CODE_MAJOR 31:16 #define NV_NVD_ERROR_CODE_MINOR 15:0 -#define NVD_ERROR_CODE(Major, Minor) \ +#define NVD_ERROR_CODE(Major, Minor) \ (DRF_NUM(_NVD, _ERROR_CODE, _MAJOR, Major) | \ DRF_NUM(_NVD, _ERROR_CODE, _MINOR, Minor)) @@ -86,7 +86,7 @@ #define NV_NVD_ENGINE_STEP_MAJOR 31:16 #define NV_NVD_ENGINE_STEP_MINOR 15:0 -#define NVD_ENGINE_STEP(Major, Minor) \ +#define NVD_ENGINE_STEP(Major, Minor) \ (DRF_NUM(_NVD, _ENGINE_STEP, _MAJOR, Major) | \ DRF_NUM(_NVD, _ENGINE_STEP, _MINOR, Minor)) @@ -165,7 +165,6 @@ struct NvDebugDump *__nvoc_pbase_NvDebugDump; NV_STATUS (*__nvdConstructEngine__)(struct OBJGPU *, struct NvDebugDump *, ENGDESCRIPTOR); NV_STATUS (*__nvdStateInitLocked__)(struct OBJGPU *, struct NvDebugDump *); - NV_STATUS (*__nvdReconcileTunableState__)(POBJGPU, struct NvDebugDump *, void *); NV_STATUS (*__nvdStateLoad__)(POBJGPU, struct NvDebugDump *, NvU32); NV_STATUS (*__nvdStateUnload__)(POBJGPU, struct NvDebugDump *, NvU32); NV_STATUS (*__nvdStatePreLoad__)(POBJGPU, struct NvDebugDump *, NvU32); @@ -176,12 +175,7 @@ void (*__nvdInitMissing__)(POBJGPU, struct NvDebugDump *); NV_STATUS (*__nvdStatePreInitLocked__)(POBJGPU, struct NvDebugDump *); NV_STATUS (*__nvdStatePreInitUnlocked__)(POBJGPU, struct NvDebugDump *); - NV_STATUS (*__nvdGetTunableState__)(POBJGPU, struct NvDebugDump *, void *); - NV_STATUS (*__nvdCompareTunableState__)(POBJGPU, struct NvDebugDump *, void *, void *); - void (*__nvdFreeTunableState__)(POBJGPU, struct NvDebugDump *, void *); NV_STATUS (*__nvdStatePostLoad__)(POBJGPU, struct NvDebugDump *, NvU32); - NV_STATUS (*__nvdAllocTunableState__)(POBJGPU, struct NvDebugDump *, void **); - NV_STATUS (*__nvdSetTunableState__)(POBJGPU, struct NvDebugDump *, void *); NvBool (*__nvdIsPresent__)(POBJGPU, struct NvDebugDump *); NVD_DEBUG_BUFFER *pHeadDebugBuffer; NVD_ENGINE_CALLBACK *pCallbacks; @@ -219,7 +213,6 @@ #define nvdConstructEngine(pGpu, pNvd, arg0) nvdConstructEngine_DISPATCH(pGpu, pNvd, arg0) #define nvdStateInitLocked(pGpu, pNvd) nvdStateInitLocked_DISPATCH(pGpu, pNvd) -#define nvdReconcileTunableState(pGpu, pEngstate, pTunableState) nvdReconcileTunableState_DISPATCH(pGpu, pEngstate, pTunableState) #define nvdStateLoad(pGpu, pEngstate, arg0) nvdStateLoad_DISPATCH(pGpu, pEngstate, arg0) #define nvdStateUnload(pGpu, pEngstate, arg0) nvdStateUnload_DISPATCH(pGpu, pEngstate, arg0) #define nvdStatePreLoad(pGpu, pEngstate, arg0) nvdStatePreLoad_DISPATCH(pGpu, pEngstate, arg0) @@ -230,12 +223,7 @@ #define nvdInitMissing(pGpu, pEngstate) nvdInitMissing_DISPATCH(pGpu, pEngstate) #define nvdStatePreInitLocked(pGpu, pEngstate) nvdStatePreInitLocked_DISPATCH(pGpu, pEngstate) #define nvdStatePreInitUnlocked(pGpu, pEngstate) nvdStatePreInitUnlocked_DISPATCH(pGpu, pEngstate) -#define nvdGetTunableState(pGpu, pEngstate, pTunableState) nvdGetTunableState_DISPATCH(pGpu, pEngstate, pTunableState) -#define nvdCompareTunableState(pGpu, pEngstate, pTunables1, pTunables2) nvdCompareTunableState_DISPATCH(pGpu, pEngstate, pTunables1, pTunables2) -#define nvdFreeTunableState(pGpu, pEngstate, pTunableState) nvdFreeTunableState_DISPATCH(pGpu, pEngstate, pTunableState) #define nvdStatePostLoad(pGpu, pEngstate, arg0) nvdStatePostLoad_DISPATCH(pGpu, pEngstate, arg0) -#define nvdAllocTunableState(pGpu, pEngstate, ppTunableState) nvdAllocTunableState_DISPATCH(pGpu, pEngstate, ppTunableState) -#define nvdSetTunableState(pGpu, pEngstate, pTunableState) nvdSetTunableState_DISPATCH(pGpu, pEngstate, pTunableState) #define nvdIsPresent(pGpu, pEngstate) nvdIsPresent_DISPATCH(pGpu, pEngstate) NV_STATUS nvdConstructEngine_IMPL(struct OBJGPU *pGpu, struct NvDebugDump *pNvd, ENGDESCRIPTOR arg0); @@ -249,10 +237,6 @@ return pNvd->__nvdStateInitLocked__(pGpu, pNvd); } -static inline NV_STATUS nvdReconcileTunableState_DISPATCH(POBJGPU pGpu, struct NvDebugDump *pEngstate, void *pTunableState) { - return pEngstate->__nvdReconcileTunableState__(pGpu, pEngstate, pTunableState); -} - static inline NV_STATUS nvdStateLoad_DISPATCH(POBJGPU pGpu, struct NvDebugDump *pEngstate, NvU32 arg0) { return pEngstate->__nvdStateLoad__(pGpu, pEngstate, arg0); } @@ -293,30 +277,10 @@ return pEngstate->__nvdStatePreInitUnlocked__(pGpu, pEngstate); } -static inline NV_STATUS nvdGetTunableState_DISPATCH(POBJGPU pGpu, struct NvDebugDump *pEngstate, void *pTunableState) { - return pEngstate->__nvdGetTunableState__(pGpu, pEngstate, pTunableState); -} - -static inline NV_STATUS nvdCompareTunableState_DISPATCH(POBJGPU pGpu, struct NvDebugDump *pEngstate, void *pTunables1, void *pTunables2) { - return pEngstate->__nvdCompareTunableState__(pGpu, pEngstate, pTunables1, pTunables2); -} - -static inline void nvdFreeTunableState_DISPATCH(POBJGPU pGpu, struct NvDebugDump *pEngstate, void *pTunableState) { - pEngstate->__nvdFreeTunableState__(pGpu, pEngstate, pTunableState); -} - static inline NV_STATUS nvdStatePostLoad_DISPATCH(POBJGPU pGpu, struct NvDebugDump *pEngstate, NvU32 arg0) { return pEngstate->__nvdStatePostLoad__(pGpu, pEngstate, arg0); } -static inline NV_STATUS nvdAllocTunableState_DISPATCH(POBJGPU pGpu, struct NvDebugDump *pEngstate, void **ppTunableState) { - return pEngstate->__nvdAllocTunableState__(pGpu, pEngstate, ppTunableState); -} - -static inline NV_STATUS nvdSetTunableState_DISPATCH(POBJGPU pGpu, struct NvDebugDump *pEngstate, void *pTunableState) { - return pEngstate->__nvdSetTunableState__(pGpu, pEngstate, pTunableState); -} - static inline NvBool nvdIsPresent_DISPATCH(POBJGPU pGpu, struct NvDebugDump *pEngstate) { return pEngstate->__nvdIsPresent__(pGpu, pEngstate); } diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/generated/g_nv_name_released.h nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_nv_name_released.h --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/generated/g_nv_name_released.h 2023-10-25 20:27:33.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_nv_name_released.h 2024-03-05 22:18:54.000000000 +0000 @@ -57,7 +57,6 @@ { 0x1349, 0x36d1, 0x17aa, "NVIDIA GeForce 930A" }, { 0x1349, 0x36d8, 0x17aa, "NVIDIA GeForce 930A" }, { 0x134B, 0x0000, 0x0000, "NVIDIA GeForce 940MX" }, - { 0x134B, 0x0008, 0x1414, "NVIDIA GeForce GPU" }, { 0x134D, 0x0000, 0x0000, "NVIDIA GeForce 940MX" }, { 0x134E, 0x0000, 0x0000, "NVIDIA GeForce 930MX" }, { 0x134F, 0x0000, 0x0000, "NVIDIA GeForce 920MX" }, @@ -817,6 +816,7 @@ { 0x20B7, 0x1532, 0x10de, "NVIDIA A30" }, { 0x20B7, 0x1804, 0x10de, "NVIDIA A30" }, { 0x20B7, 0x1852, 0x10de, "NVIDIA A30" }, + { 0x20BD, 0x17f4, 0x10de, "NVIDIA A800-SXM4-40GB" }, { 0x20F1, 0x145f, 0x10de, "NVIDIA A100-PCIE-40GB" }, { 0x20F3, 0x179b, 0x10de, "NVIDIA A800-SXM4-80GB" }, { 0x20F3, 0x179c, 0x10de, "NVIDIA A800-SXM4-80GB" }, @@ -828,6 +828,11 @@ { 0x20F3, 0x17a2, 0x10de, "NVIDIA A800-SXM4-80GB" }, { 0x20F5, 0x1799, 0x10de, "NVIDIA A800 80GB PCIe" }, { 0x20F5, 0x179a, 0x10de, "NVIDIA A800 80GB PCIe LC" }, + { 0x20F6, 0x180a, 0x1028, "NVIDIA A800 40GB Active" }, + { 0x20F6, 0x180a, 0x103c, "NVIDIA A800 40GB Active" }, + { 0x20F6, 0x180a, 0x10de, "NVIDIA A800 40GB Active" }, + { 0x20F6, 0x180a, 0x17aa, "NVIDIA A800 40GB Active" }, + { 0x20FD, 0x17f8, 0x10de, "NVIDIA AX800" }, { 0x2182, 0x0000, 0x0000, "NVIDIA GeForce GTX 1660 Ti" }, { 0x2184, 0x0000, 0x0000, "NVIDIA GeForce GTX 1660" }, { 0x2187, 0x0000, 0x0000, "NVIDIA GeForce GTX 1650 SUPER" }, @@ -887,13 +892,20 @@ { 0x2236, 0x1482, 0x10de, "NVIDIA A10" }, { 0x2237, 0x152f, 0x10de, "NVIDIA A10G" }, { 0x2238, 0x1677, 0x10de, "NVIDIA A10M" }, + { 0x2321, 0x1839, 0x10de, "NVIDIA H100 NVL" }, { 0x2322, 0x17a4, 0x10de, "NVIDIA H800 PCIe" }, { 0x2324, 0x17a6, 0x10de, "NVIDIA H800" }, { 0x2324, 0x17a8, 0x10de, "NVIDIA H800" }, + { 0x2329, 0x198b, 0x10de, "NVIDIA H20" }, + { 0x2329, 0x198c, 0x10de, "NVIDIA H20" }, { 0x2330, 0x16c0, 0x10de, "NVIDIA H100 80GB HBM3" }, { 0x2330, 0x16c1, 0x10de, "NVIDIA H100 80GB HBM3" }, { 0x2331, 0x1626, 0x10de, "NVIDIA H100 PCIe" }, { 0x2339, 0x17fc, 0x10de, "NVIDIA H100" }, + { 0x233A, 0x183a, 0x10de, "NVIDIA H800 NVL" }, + { 0x2342, 0x16eb, 0x10de, "NVIDIA GH200 120GB" }, + { 0x2342, 0x1805, 0x10de, "NVIDIA GH200 120GB" }, + { 0x2342, 0x1809, 0x10de, "NVIDIA GH200 480GB" }, { 0x2414, 0x0000, 0x0000, "NVIDIA GeForce RTX 3060 Ti" }, { 0x2420, 0x0000, 0x0000, "NVIDIA GeForce RTX 3080 Ti Laptop GPU" }, { 0x2438, 0x0000, 0x0000, "NVIDIA RTX A5500 Laptop GPU" }, @@ -946,6 +958,7 @@ { 0x2571, 0x1611, 0x10de, "NVIDIA RTX A2000 12GB" }, { 0x2571, 0x1611, 0x17aa, "NVIDIA RTX A2000 12GB" }, { 0x2582, 0x0000, 0x0000, "NVIDIA GeForce RTX 3050" }, + { 0x2584, 0x0000, 0x0000, "NVIDIA GeForce RTX 3050" }, { 0x25A0, 0x0000, 0x0000, "NVIDIA GeForce RTX 3050 Ti Laptop GPU" }, { 0x25A0, 0x8928, 0x103c, "NVIDIA GeForce RTX 3050Ti Laptop GPU" }, { 0x25A0, 0x89f9, 0x103c, "NVIDIA GeForce RTX 3050Ti Laptop GPU" }, @@ -982,8 +995,17 @@ { 0x26B1, 0x16a1, 0x103c, "NVIDIA RTX 6000 Ada Generation" }, { 0x26B1, 0x16a1, 0x10de, "NVIDIA RTX 6000 Ada Generation" }, { 0x26B1, 0x16a1, 0x17aa, "NVIDIA RTX 6000 Ada Generation" }, + { 0x26B2, 0x17fa, 0x1028, "NVIDIA RTX 5000 Ada Generation" }, + { 0x26B2, 0x17fa, 0x103c, "NVIDIA RTX 5000 Ada Generation" }, + { 0x26B2, 0x17fa, 0x10de, "NVIDIA RTX 5000 Ada Generation" }, + { 0x26B2, 0x17fa, 0x17aa, "NVIDIA RTX 5000 Ada Generation" }, + { 0x26B3, 0x1934, 0x103c, "NVIDIA RTX 5880 Ada Generation" }, + { 0x26B3, 0x1934, 0x10de, "NVIDIA RTX 5880 Ada Generation" }, { 0x26B5, 0x169d, 0x10de, "NVIDIA L40" }, { 0x26B5, 0x17da, 0x10de, "NVIDIA L40" }, + { 0x26B9, 0x1851, 0x10de, "NVIDIA L40S" }, + { 0x26B9, 0x18cf, 0x10de, "NVIDIA L40S" }, + { 0x26BA, 0x1957, 0x10de, "NVIDIA L20" }, { 0x2704, 0x0000, 0x0000, "NVIDIA GeForce RTX 4080" }, { 0x2717, 0x0000, 0x0000, "NVIDIA GeForce RTX 4090 Laptop GPU" }, { 0x2730, 0x0000, 0x0000, "NVIDIA RTX 5000 Ada Generation Laptop GPU" }, @@ -996,11 +1018,21 @@ { 0x27B0, 0x16fa, 0x103c, "NVIDIA RTX 4000 SFF Ada Generation" }, { 0x27B0, 0x16fa, 0x10de, "NVIDIA RTX 4000 SFF Ada Generation" }, { 0x27B0, 0x16fa, 0x17aa, "NVIDIA RTX 4000 SFF Ada Generation" }, + { 0x27B1, 0x180c, 0x1028, "NVIDIA RTX 4500 Ada Generation" }, + { 0x27B1, 0x180c, 0x103c, "NVIDIA RTX 4500 Ada Generation" }, + { 0x27B1, 0x180c, 0x10de, "NVIDIA RTX 4500 Ada Generation" }, + { 0x27B1, 0x180c, 0x17aa, "NVIDIA RTX 4500 Ada Generation" }, + { 0x27B2, 0x181b, 0x1028, "NVIDIA RTX 4000 Ada Generation" }, + { 0x27B2, 0x181b, 0x103c, "NVIDIA RTX 4000 Ada Generation" }, + { 0x27B2, 0x181b, 0x10de, "NVIDIA RTX 4000 Ada Generation" }, + { 0x27B2, 0x181b, 0x17aa, "NVIDIA RTX 4000 Ada Generation" }, + { 0x27B6, 0x1933, 0x10de, "NVIDIA L2" }, { 0x27B8, 0x16ca, 0x10de, "NVIDIA L4" }, { 0x27B8, 0x16ee, 0x10de, "NVIDIA L4" }, { 0x27BA, 0x0000, 0x0000, "NVIDIA RTX 4000 Ada Generation Laptop GPU" }, { 0x27BB, 0x0000, 0x0000, "NVIDIA RTX 3500 Ada Generation Laptop GPU" }, { 0x27E0, 0x0000, 0x0000, "NVIDIA GeForce RTX 4080 Laptop GPU" }, + { 0x27FB, 0x0000, 0x0000, "NVIDIA RTX 3500 Ada Generation Embedded GPU" }, { 0x2803, 0x0000, 0x0000, "NVIDIA GeForce RTX 4060 Ti" }, { 0x2805, 0x0000, 0x0000, "NVIDIA GeForce RTX 4060 Ti" }, { 0x2820, 0x0000, 0x0000, "NVIDIA GeForce RTX 4070 Laptop GPU" }, @@ -1356,9 +1388,8 @@ { 0x1E37, 0x13a7, 0x10DE, "GRID RTX T10x-2" }, { 0x1E37, 0x13a8, 0x10DE, "GRID RTX T10x-4" }, { 0x1E37, 0x13a9, 0x10DE, "GRID RTX T10x-8" }, - { 0x1E37, 0x148a, 0x10DE, "GRID RTX T10-2" }, - { 0x1E37, 0x148b, 0x10DE, "GRID RTX T10-1" }, - { 0x1E37, 0x148c, 0x10DE, "GRID RTX T10-0" }, + { 0x1E37, 0x180d, 0x10DE, "NVIDIA GeForce GTX 1060" }, + { 0x1E37, 0x1820, 0x10DE, "NVIDIA GeForce RTX 2080" }, { 0x1E78, 0x13f7, 0x10DE, "GRID RTX6000P-1B" }, { 0x1E78, 0x13f8, 0x10DE, "GRID RTX6000P-2B" }, { 0x1E78, 0x13f9, 0x10DE, "GRID RTX6000P-1Q" }, @@ -1439,9 +1470,6 @@ { 0x1EB8, 0x1375, 0x10DE, "GRID T4-16C" }, { 0x1EB8, 0x139a, 0x10DE, "GRID T4-4C" }, { 0x1EB8, 0x139b, 0x10DE, "GRID T4-8C" }, - { 0x1EB8, 0x148d, 0x10DE, "GRID RTX T4-2" }, - { 0x1EB8, 0x148e, 0x10DE, "GRID RTX T4-1" }, - { 0x1EB8, 0x148f, 0x10DE, "GRID RTX T4-0" }, { 0x20B0, 0x146f, 0x10DE, "GRID A100X-1-5C" }, { 0x20B0, 0x1470, 0x10DE, "GRID A100X-2-10C" }, { 0x20B0, 0x1471, 0x10DE, "GRID A100X-3-20C" }, @@ -1454,6 +1482,7 @@ { 0x20B0, 0x1478, 0x10DE, "GRID A100X-20C" }, { 0x20B0, 0x1479, 0x10DE, "GRID A100X-40C" }, { 0x20B0, 0x160c, 0x10DE, "GRID A100X-1-5CME" }, + { 0x20B0, 0x1840, 0x10DE, "GRID A100X-1-10C" }, { 0x20B2, 0x1523, 0x10DE, "GRID A100DX-1-10C" }, { 0x20B2, 0x1524, 0x10DE, "GRID A100DX-2-20C" }, { 0x20B2, 0x1525, 0x10DE, "GRID A100DX-3-40C" }, @@ -1467,6 +1496,7 @@ { 0x20B2, 0x152d, 0x10DE, "GRID A100DX-40C" }, { 0x20B2, 0x152e, 0x10DE, "GRID A100DX-80C" }, { 0x20B2, 0x160d, 0x10DE, "GRID A100DX-1-10CME" }, + { 0x20B2, 0x1841, 0x10DE, "GRID A100DX-1-20C" }, { 0x20B5, 0x1591, 0x10DE, "GRID A100D-1-10C" }, { 0x20B5, 0x1592, 0x10DE, "GRID A100D-2-20C" }, { 0x20B5, 0x1593, 0x10DE, "GRID A100D-3-40C" }, @@ -1480,6 +1510,7 @@ { 0x20B5, 0x159b, 0x10DE, "GRID A100D-40C" }, { 0x20B5, 0x159c, 0x10DE, "GRID A100D-80C" }, { 0x20B5, 0x160f, 0x10DE, "GRID A100D-1-10CME" }, + { 0x20B5, 0x183e, 0x10DE, "GRID A100D-1-20C" }, { 0x20B7, 0x1589, 0x10DE, "NVIDIA A30-1-6C" }, { 0x20B7, 0x158a, 0x10DE, "NVIDIA A30-2-12C" }, { 0x20B7, 0x158b, 0x10DE, "NVIDIA A30-4-24C" }, @@ -1489,17 +1520,7 @@ { 0x20B7, 0x158f, 0x10DE, "NVIDIA A30-12C" }, { 0x20B7, 0x1590, 0x10DE, "NVIDIA A30-24C" }, { 0x20B7, 0x1610, 0x10DE, "NVIDIA A30-1-6CME" }, - { 0x20BF, 0x4450, 0x10DE, "GRID A100B-4C" }, - { 0x20BF, 0x4451, 0x10DE, "GRID A100B-5C" }, - { 0x20BF, 0x4452, 0x10DE, "GRID A100B-8C" }, - { 0x20BF, 0x4453, 0x10DE, "GRID A100B-10C" }, - { 0x20BF, 0x4454, 0x10DE, "GRID A100B-20C" }, - { 0x20BF, 0x4455, 0x10DE, "GRID A100B-40C" }, - { 0x20BF, 0x5560, 0x10DE, "GRID A100B-1-5C" }, - { 0x20BF, 0x5561, 0x10DE, "GRID A100B-2-10C" }, - { 0x20BF, 0x5562, 0x10DE, "GRID A100B-3-20C" }, - { 0x20BF, 0x5563, 0x10DE, "GRID A100B-4-20C" }, - { 0x20BF, 0x5564, 0x10DE, "GRID A100B-7-40C" }, + { 0x20B7, 0x183c, 0x10DE, "NVIDIA A30-2-12CME" }, { 0x20F1, 0x1493, 0x10DE, "GRID A100-1-5C" }, { 0x20F1, 0x1494, 0x10DE, "GRID A100-2-10C" }, { 0x20F1, 0x1495, 0x10DE, "GRID A100-3-20C" }, @@ -1512,6 +1533,7 @@ { 0x20F1, 0x149c, 0x10DE, "GRID A100-20C" }, { 0x20F1, 0x149d, 0x10DE, "GRID A100-40C" }, { 0x20F1, 0x160e, 0x10DE, "GRID A100-1-5CME" }, + { 0x20F1, 0x183d, 0x10DE, "GRID A100-1-10C" }, { 0x20F3, 0x17b2, 0x10DE, "GRID A800DX-1-10CME" }, { 0x20F3, 0x17b3, 0x10DE, "GRID A800DX-1-10C" }, { 0x20F3, 0x17b4, 0x10DE, "GRID A800DX-2-20C" }, @@ -1525,6 +1547,7 @@ { 0x20F3, 0x17bc, 0x10DE, "GRID A800DX-20C" }, { 0x20F3, 0x17bd, 0x10DE, "GRID A800DX-40C" }, { 0x20F3, 0x17be, 0x10DE, "GRID A800DX-80C" }, + { 0x20F3, 0x1842, 0x10DE, "GRID A800DX-1-20C" }, { 0x20F5, 0x17bf, 0x10DE, "GRID A800D-1-10CME" }, { 0x20F5, 0x17c0, 0x10DE, "GRID A800D-1-10C" }, { 0x20F5, 0x17c1, 0x10DE, "GRID A800D-2-20C" }, @@ -1538,6 +1561,20 @@ { 0x20F5, 0x17c9, 0x10DE, "GRID A800D-20C" }, { 0x20F5, 0x17ca, 0x10DE, "GRID A800D-40C" }, { 0x20F5, 0x17cb, 0x10DE, "GRID A800D-80C" }, + { 0x20F5, 0x183f, 0x10DE, "GRID A800D-1-20C" }, + { 0x20F6, 0x17cc, 0x10DE, "GRID A800-1-5CME" }, + { 0x20F6, 0x17cd, 0x10DE, "GRID A800-1-5C" }, + { 0x20F6, 0x17ce, 0x10DE, "GRID A800-2-10C" }, + { 0x20F6, 0x17cf, 0x10DE, "GRID A800-3-20C" }, + { 0x20F6, 0x17d0, 0x10DE, "GRID A800-4-20C" }, + { 0x20F6, 0x17d1, 0x10DE, "GRID A800-7-40C" }, + { 0x20F6, 0x17d2, 0x10DE, "GRID A800-4C" }, + { 0x20F6, 0x17d3, 0x10DE, "GRID A800-5C" }, + { 0x20F6, 0x17d4, 0x10DE, "GRID A800-8C" }, + { 0x20F6, 0x17d5, 0x10DE, "GRID A800-10C" }, + { 0x20F6, 0x17d6, 0x10DE, "GRID A800-20C" }, + { 0x20F6, 0x17d7, 0x10DE, "GRID A800-40C" }, + { 0x20F6, 0x1843, 0x10DE, "GRID A800-1-10C" }, { 0x2230, 0x14fa, 0x10DE, "NVIDIA RTXA6000-1B" }, { 0x2230, 0x14fb, 0x10DE, "NVIDIA RTXA6000-2B" }, { 0x2230, 0x14fc, 0x10DE, "NVIDIA RTXA6000-1Q" }, @@ -1721,6 +1758,8 @@ { 0x2237, 0x1639, 0x10DE, "NVIDIA A10G-8A" }, { 0x2237, 0x163a, 0x10DE, "NVIDIA A10G-12A" }, { 0x2237, 0x163b, 0x10DE, "NVIDIA A10G-24A" }, + { 0x2237, 0x1810, 0x10DE, "NVIDIA GeForce RTX 3050" }, + { 0x2237, 0x1811, 0x10DE, "NVIDIA GeForce RTX 3060" }, { 0x2238, 0x16a3, 0x10DE, "NVIDIA A10M-1B" }, { 0x2238, 0x16a4, 0x10DE, "NVIDIA A10M-2B" }, { 0x2238, 0x16a5, 0x10DE, "NVIDIA A10M-1Q" }, @@ -1745,6 +1784,20 @@ { 0x2238, 0x16b8, 0x10DE, "NVIDIA A10M-10C" }, { 0x2238, 0x16b9, 0x10DE, "NVIDIA A10M-20C" }, { 0x2238, 0x16e6, 0x10DE, "NVIDIA A10M-1" }, + { 0x2321, 0x1853, 0x10DE, "NVIDIA H100L-1-12CME" }, + { 0x2321, 0x1854, 0x10DE, "NVIDIA H100L-1-12C" }, + { 0x2321, 0x1855, 0x10DE, "NVIDIA H100L-1-24C" }, + { 0x2321, 0x1856, 0x10DE, "NVIDIA H100L-2-24C" }, + { 0x2321, 0x1857, 0x10DE, "NVIDIA H100L-3-47C" }, + { 0x2321, 0x1858, 0x10DE, "NVIDIA H100L-4-47C" }, + { 0x2321, 0x1859, 0x10DE, "NVIDIA H100L-7-94C" }, + { 0x2321, 0x185a, 0x10DE, "NVIDIA H100L-4C" }, + { 0x2321, 0x185b, 0x10DE, "NVIDIA H100L-6C" }, + { 0x2321, 0x185c, 0x10DE, "NVIDIA H100L-11C" }, + { 0x2321, 0x185d, 0x10DE, "NVIDIA H100L-15C" }, + { 0x2321, 0x185e, 0x10DE, "NVIDIA H100L-23C" }, + { 0x2321, 0x185f, 0x10DE, "NVIDIA H100L-47C" }, + { 0x2321, 0x1860, 0x10DE, "NVIDIA H100L-94C" }, { 0x2322, 0x17e2, 0x10DE, "NVIDIA H800-1-10CME" }, { 0x2322, 0x17e3, 0x10DE, "NVIDIA H800-1-10C" }, { 0x2322, 0x17e4, 0x10DE, "NVIDIA H800-2-20C" }, @@ -1759,6 +1812,7 @@ { 0x2322, 0x17ed, 0x10DE, "NVIDIA H800-20C" }, { 0x2322, 0x17ee, 0x10DE, "NVIDIA H800-40C" }, { 0x2322, 0x17ef, 0x10DE, "NVIDIA H800-80C" }, + { 0x2322, 0x1845, 0x10DE, "NVIDIA H800-1-20C" }, { 0x2331, 0x16d3, 0x10DE, "NVIDIA H100-1-10C" }, { 0x2331, 0x16d4, 0x10DE, "NVIDIA H100-2-20C" }, { 0x2331, 0x16d5, 0x10DE, "NVIDIA H100-3-40C" }, @@ -1773,6 +1827,21 @@ { 0x2331, 0x16de, 0x10DE, "NVIDIA H100-80C" }, { 0x2331, 0x1798, 0x10DE, "NVIDIA H100-5C" }, { 0x2331, 0x17f0, 0x10DE, "NVIDIA H100-1-10CME" }, + { 0x2331, 0x1844, 0x10DE, "NVIDIA H100-1-20C" }, + { 0x233A, 0x1861, 0x10DE, "NVIDIA H800L-1-12CME" }, + { 0x233A, 0x1862, 0x10DE, "NVIDIA H800L-1-12C" }, + { 0x233A, 0x1863, 0x10DE, "NVIDIA H800L-1-24C" }, + { 0x233A, 0x1864, 0x10DE, "NVIDIA H800L-2-24C" }, + { 0x233A, 0x1865, 0x10DE, "NVIDIA H800L-3-47C" }, + { 0x233A, 0x1866, 0x10DE, "NVIDIA H800L-4-47C" }, + { 0x233A, 0x1867, 0x10DE, "NVIDIA H800L-7-94C" }, + { 0x233A, 0x1868, 0x10DE, "NVIDIA H800L-4C" }, + { 0x233A, 0x1869, 0x10DE, "NVIDIA H800L-6C" }, + { 0x233A, 0x186a, 0x10DE, "NVIDIA H800L-11C" }, + { 0x233A, 0x186b, 0x10DE, "NVIDIA H800L-15C" }, + { 0x233A, 0x186c, 0x10DE, "NVIDIA H800L-23C" }, + { 0x233A, 0x186d, 0x10DE, "NVIDIA H800L-47C" }, + { 0x233A, 0x186e, 0x10DE, "NVIDIA H800L-94C" }, { 0x25B6, 0x159d, 0x10DE, "NVIDIA A16-1B" }, { 0x25B6, 0x159e, 0x10DE, "NVIDIA A16-2B" }, { 0x25B6, 0x159f, 0x10DE, "NVIDIA A16-1Q" }, @@ -1845,6 +1914,30 @@ { 0x26B1, 0x172c, 0x10DE, "NVIDIA RTX6000-Ada-16C" }, { 0x26B1, 0x172d, 0x10DE, "NVIDIA RTX6000-Ada-24C" }, { 0x26B1, 0x172e, 0x10DE, "NVIDIA RTX6000-Ada-48C" }, + { 0x26B2, 0x1821, 0x10DE, "NVIDIA RTX5000-Ada-1B" }, + { 0x26B2, 0x1822, 0x10DE, "NVIDIA RTX5000-Ada-2B" }, + { 0x26B2, 0x1823, 0x10DE, "NVIDIA RTX5000-Ada-1Q" }, + { 0x26B2, 0x1824, 0x10DE, "NVIDIA RTX5000-Ada-2Q" }, + { 0x26B2, 0x1825, 0x10DE, "NVIDIA RTX5000-Ada-4Q" }, + { 0x26B2, 0x1826, 0x10DE, "NVIDIA RTX5000-Ada-8Q" }, + { 0x26B2, 0x1827, 0x10DE, "NVIDIA RTX5000-Ada-16Q" }, + { 0x26B2, 0x1828, 0x10DE, "NVIDIA RTX5000-Ada-32Q" }, + { 0x26B2, 0x1829, 0x10DE, "NVIDIA RTX5000-Ada-1A" }, + { 0x26B2, 0x182a, 0x10DE, "NVIDIA RTX5000-Ada-2A" }, + { 0x26B2, 0x182b, 0x10DE, "NVIDIA RTX5000-Ada-4A" }, + { 0x26B2, 0x182c, 0x10DE, "NVIDIA RTX5000-Ada-8A" }, + { 0x26B2, 0x182d, 0x10DE, "NVIDIA RTX5000-Ada-16A" }, + { 0x26B2, 0x182e, 0x10DE, "NVIDIA RTX5000-Ada-32A" }, + { 0x26B2, 0x182f, 0x10DE, "NVIDIA RTX5000-Ada-1" }, + { 0x26B2, 0x1830, 0x10DE, "NVIDIA RTX5000-Ada-2" }, + { 0x26B2, 0x1831, 0x10DE, "NVIDIA RTX5000-Ada-4" }, + { 0x26B2, 0x1832, 0x10DE, "NVIDIA RTX5000-Ada-8" }, + { 0x26B2, 0x1833, 0x10DE, "NVIDIA RTX5000-Ada-16" }, + { 0x26B2, 0x1834, 0x10DE, "NVIDIA RTX5000-Ada-32" }, + { 0x26B2, 0x1835, 0x10DE, "NVIDIA RTX5000-Ada-4C" }, + { 0x26B2, 0x1836, 0x10DE, "NVIDIA RTX5000-Ada-8C" }, + { 0x26B2, 0x1837, 0x10DE, "NVIDIA RTX5000-Ada-16C" }, + { 0x26B2, 0x1838, 0x10DE, "NVIDIA RTX5000-Ada-32C" }, { 0x26B5, 0x176d, 0x10DE, "NVIDIA L40-1B" }, { 0x26B5, 0x176e, 0x10DE, "NVIDIA L40-2B" }, { 0x26B5, 0x176f, 0x10DE, "NVIDIA L40-1Q" }, @@ -1884,6 +1977,8 @@ { 0x26B5, 0x1791, 0x10DE, "NVIDIA L40-16C" }, { 0x26B5, 0x1792, 0x10DE, "NVIDIA L40-24C" }, { 0x26B5, 0x1793, 0x10DE, "NVIDIA L40-48C" }, + { 0x26B5, 0x1818, 0x10DE, "NVIDIA GeForce RTX 3060" }, + { 0x26B5, 0x181a, 0x10DE, "NVIDIA GeForce RTX 3050" }, { 0x26B8, 0x174e, 0x10DE, "NVIDIA L40G-1B" }, { 0x26B8, 0x174f, 0x10DE, "NVIDIA L40G-2B" }, { 0x26B8, 0x1750, 0x10DE, "NVIDIA L40G-1Q" }, @@ -1915,6 +2010,121 @@ { 0x26B8, 0x176a, 0x10DE, "NVIDIA L40G-8C" }, { 0x26B8, 0x176b, 0x10DE, "NVIDIA L40G-12C" }, { 0x26B8, 0x176c, 0x10DE, "NVIDIA L40G-24C" }, + { 0x26B8, 0x181c, 0x10DE, "NVIDIA GeForce RTX 3060" }, + { 0x26B8, 0x181e, 0x10DE, "NVIDIA GeForce RTX 3050" }, + { 0x26B9, 0x1889, 0x10DE, "NVIDIA L40S-1B" }, + { 0x26B9, 0x188a, 0x10DE, "NVIDIA L40S-2B" }, + { 0x26B9, 0x188b, 0x10DE, "NVIDIA L40S-1Q" }, + { 0x26B9, 0x188c, 0x10DE, "NVIDIA L40S-2Q" }, + { 0x26B9, 0x188d, 0x10DE, "NVIDIA L40S-3Q" }, + { 0x26B9, 0x188e, 0x10DE, "NVIDIA L40S-4Q" }, + { 0x26B9, 0x188f, 0x10DE, "NVIDIA L40S-6Q" }, + { 0x26B9, 0x1890, 0x10DE, "NVIDIA L40S-8Q" }, + { 0x26B9, 0x1891, 0x10DE, "NVIDIA L40S-12Q" }, + { 0x26B9, 0x1892, 0x10DE, "NVIDIA L40S-16Q" }, + { 0x26B9, 0x1893, 0x10DE, "NVIDIA L40S-24Q" }, + { 0x26B9, 0x1894, 0x10DE, "NVIDIA L40S-48Q" }, + { 0x26B9, 0x1895, 0x10DE, "NVIDIA L40S-1A" }, + { 0x26B9, 0x1896, 0x10DE, "NVIDIA L40S-2A" }, + { 0x26B9, 0x1897, 0x10DE, "NVIDIA L40S-3A" }, + { 0x26B9, 0x1898, 0x10DE, "NVIDIA L40S-4A" }, + { 0x26B9, 0x1899, 0x10DE, "NVIDIA L40S-6A" }, + { 0x26B9, 0x189a, 0x10DE, "NVIDIA L40S-8A" }, + { 0x26B9, 0x189b, 0x10DE, "NVIDIA L40S-12A" }, + { 0x26B9, 0x189c, 0x10DE, "NVIDIA L40S-16A" }, + { 0x26B9, 0x189d, 0x10DE, "NVIDIA L40S-24A" }, + { 0x26B9, 0x189e, 0x10DE, "NVIDIA L40S-48A" }, + { 0x26B9, 0x189f, 0x10DE, "NVIDIA GeForce RTX 3050" }, + { 0x26B9, 0x18a0, 0x10DE, "NVIDIA GeForce RTX 3060" }, + { 0x26B9, 0x18a1, 0x10DE, "NVIDIA L40S-1" }, + { 0x26B9, 0x18a2, 0x10DE, "NVIDIA L40S-2" }, + { 0x26B9, 0x18a3, 0x10DE, "NVIDIA L40S-3" }, + { 0x26B9, 0x18a4, 0x10DE, "NVIDIA L40S-4" }, + { 0x26B9, 0x18a5, 0x10DE, "NVIDIA L40S-6" }, + { 0x26B9, 0x18a6, 0x10DE, "NVIDIA L40S-8" }, + { 0x26B9, 0x18a7, 0x10DE, "NVIDIA L40S-12" }, + { 0x26B9, 0x18a8, 0x10DE, "NVIDIA L40S-16" }, + { 0x26B9, 0x18a9, 0x10DE, "NVIDIA L40S-24" }, + { 0x26B9, 0x18aa, 0x10DE, "NVIDIA L40S-48" }, + { 0x26B9, 0x18ab, 0x10DE, "NVIDIA L40S-4C" }, + { 0x26B9, 0x18ac, 0x10DE, "NVIDIA L40S-6C" }, + { 0x26B9, 0x18ad, 0x10DE, "NVIDIA L40S-8C" }, + { 0x26B9, 0x18ae, 0x10DE, "NVIDIA L40S-12C" }, + { 0x26B9, 0x18af, 0x10DE, "NVIDIA L40S-16C" }, + { 0x26B9, 0x18b0, 0x10DE, "NVIDIA L40S-24C" }, + { 0x26B9, 0x18b1, 0x10DE, "NVIDIA L40S-48C" }, + { 0x26BA, 0x1909, 0x10DE, "NVIDIA L20-1B" }, + { 0x26BA, 0x190a, 0x10DE, "NVIDIA L20-2B" }, + { 0x26BA, 0x190b, 0x10DE, "NVIDIA L20-1Q" }, + { 0x26BA, 0x190c, 0x10DE, "NVIDIA L20-2Q" }, + { 0x26BA, 0x190d, 0x10DE, "NVIDIA L20-3Q" }, + { 0x26BA, 0x190e, 0x10DE, "NVIDIA L20-4Q" }, + { 0x26BA, 0x190f, 0x10DE, "NVIDIA L20-6Q" }, + { 0x26BA, 0x1910, 0x10DE, "NVIDIA L20-8Q" }, + { 0x26BA, 0x1911, 0x10DE, "NVIDIA L20-12Q" }, + { 0x26BA, 0x1912, 0x10DE, "NVIDIA L20-16Q" }, + { 0x26BA, 0x1913, 0x10DE, "NVIDIA L20-24Q" }, + { 0x26BA, 0x1914, 0x10DE, "NVIDIA L20-48Q" }, + { 0x26BA, 0x1915, 0x10DE, "NVIDIA L20-1A" }, + { 0x26BA, 0x1916, 0x10DE, "NVIDIA L20-2A" }, + { 0x26BA, 0x1917, 0x10DE, "NVIDIA L20-3A" }, + { 0x26BA, 0x1918, 0x10DE, "NVIDIA L20-4A" }, + { 0x26BA, 0x1919, 0x10DE, "NVIDIA L20-6A" }, + { 0x26BA, 0x191a, 0x10DE, "NVIDIA L20-8A" }, + { 0x26BA, 0x191b, 0x10DE, "NVIDIA L20-12A" }, + { 0x26BA, 0x191c, 0x10DE, "NVIDIA L20-16A" }, + { 0x26BA, 0x191d, 0x10DE, "NVIDIA L20-24A" }, + { 0x26BA, 0x191e, 0x10DE, "NVIDIA L20-48A" }, + { 0x26BA, 0x191f, 0x10DE, "NVIDIA GeForce RTX 3050" }, + { 0x26BA, 0x1920, 0x10DE, "NVIDIA GeForce RTX 3060" }, + { 0x26BA, 0x1921, 0x10DE, "NVIDIA L20-1" }, + { 0x26BA, 0x1922, 0x10DE, "NVIDIA L20-2" }, + { 0x26BA, 0x1923, 0x10DE, "NVIDIA L20-3" }, + { 0x26BA, 0x1924, 0x10DE, "NVIDIA L20-4" }, + { 0x26BA, 0x1925, 0x10DE, "NVIDIA L20-6" }, + { 0x26BA, 0x1926, 0x10DE, "NVIDIA L20-8" }, + { 0x26BA, 0x1927, 0x10DE, "NVIDIA L20-12" }, + { 0x26BA, 0x1928, 0x10DE, "NVIDIA L20-16" }, + { 0x26BA, 0x1929, 0x10DE, "NVIDIA L20-24" }, + { 0x26BA, 0x192a, 0x10DE, "NVIDIA L20-48" }, + { 0x26BA, 0x192b, 0x10DE, "NVIDIA L20-4C" }, + { 0x26BA, 0x192c, 0x10DE, "NVIDIA L20-6C" }, + { 0x26BA, 0x192d, 0x10DE, "NVIDIA L20-8C" }, + { 0x26BA, 0x192e, 0x10DE, "NVIDIA L20-12C" }, + { 0x26BA, 0x192f, 0x10DE, "NVIDIA L20-16C" }, + { 0x26BA, 0x1930, 0x10DE, "NVIDIA L20-24C" }, + { 0x26BA, 0x1931, 0x10DE, "NVIDIA L20-48C" }, + { 0x27B6, 0x1938, 0x10DE, "NVIDIA L2-1B" }, + { 0x27B6, 0x1939, 0x10DE, "NVIDIA L2-2B" }, + { 0x27B6, 0x193a, 0x10DE, "NVIDIA L2-1Q" }, + { 0x27B6, 0x193b, 0x10DE, "NVIDIA L2-2Q" }, + { 0x27B6, 0x193c, 0x10DE, "NVIDIA L2-3Q" }, + { 0x27B6, 0x193d, 0x10DE, "NVIDIA L2-4Q" }, + { 0x27B6, 0x193e, 0x10DE, "NVIDIA L2-6Q" }, + { 0x27B6, 0x193f, 0x10DE, "NVIDIA L2-8Q" }, + { 0x27B6, 0x1940, 0x10DE, "NVIDIA L2-12Q" }, + { 0x27B6, 0x1941, 0x10DE, "NVIDIA L2-24Q" }, + { 0x27B6, 0x1942, 0x10DE, "NVIDIA L2-1A" }, + { 0x27B6, 0x1943, 0x10DE, "NVIDIA L2-2A" }, + { 0x27B6, 0x1944, 0x10DE, "NVIDIA L2-3A" }, + { 0x27B6, 0x1945, 0x10DE, "NVIDIA L2-4A" }, + { 0x27B6, 0x1946, 0x10DE, "NVIDIA L2-6A" }, + { 0x27B6, 0x1947, 0x10DE, "NVIDIA L2-8A" }, + { 0x27B6, 0x1948, 0x10DE, "NVIDIA L2-12A" }, + { 0x27B6, 0x1949, 0x10DE, "NVIDIA L2-24A" }, + { 0x27B6, 0x194a, 0x10DE, "NVIDIA L2-1" }, + { 0x27B6, 0x194b, 0x10DE, "NVIDIA L2-2" }, + { 0x27B6, 0x194c, 0x10DE, "NVIDIA L2-3" }, + { 0x27B6, 0x194d, 0x10DE, "NVIDIA L2-4" }, + { 0x27B6, 0x194e, 0x10DE, "NVIDIA L2-6" }, + { 0x27B6, 0x194f, 0x10DE, "NVIDIA L2-8" }, + { 0x27B6, 0x1950, 0x10DE, "NVIDIA L2-12" }, + { 0x27B6, 0x1951, 0x10DE, "NVIDIA L2-24" }, + { 0x27B6, 0x1952, 0x10DE, "NVIDIA L2-4C" }, + { 0x27B6, 0x1953, 0x10DE, "NVIDIA L2-6C" }, + { 0x27B6, 0x1954, 0x10DE, "NVIDIA L2-8C" }, + { 0x27B6, 0x1955, 0x10DE, "NVIDIA L2-12C" }, + { 0x27B6, 0x1956, 0x10DE, "NVIDIA L2-24C" }, { 0x27B8, 0x172f, 0x10DE, "NVIDIA L4-1B" }, { 0x27B8, 0x1730, 0x10DE, "NVIDIA L4-2B" }, { 0x27B8, 0x1731, 0x10DE, "NVIDIA L4-1Q" }, diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/generated/g_object_nvoc.c nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_object_nvoc.c --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/generated/g_object_nvoc.c 2023-10-25 20:27:14.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_object_nvoc.c 2024-03-05 22:18:36.000000000 +0000 @@ -90,13 +90,16 @@ Object *pParentObj; Object *pThis; - pThis = portMemAllocNonPaged(sizeof(Object)); - if (pThis == NULL) return NV_ERR_NO_MEMORY; + status = __nvoc_handleObjCreateMemAlloc(createFlags, sizeof(Object), (void**)&pThis, (void**)ppThis); + if (status != NV_OK) + return status; portMemSet(pThis, 0, sizeof(Object)); __nvoc_initRtti(staticCast(pThis, Dynamic), &__nvoc_class_def_Object); + pThis->createFlags = createFlags; + if (pParent != NULL && !(createFlags & NVOC_OBJ_CREATE_FLAGS_PARENT_HALSPEC_ONLY)) { pParentObj = dynamicCast(pParent, Object); @@ -112,11 +115,17 @@ if (status != NV_OK) goto __nvoc_objCreate_Object_cleanup; *ppThis = pThis; + return NV_OK; __nvoc_objCreate_Object_cleanup: // do not call destructors here since the constructor already called them - portMemFree(pThis); + if (createFlags & NVOC_OBJ_CREATE_FLAGS_IN_PLACE_CONSTRUCT) + portMemSet(pThis, 0, sizeof(Object)); + else + portMemFree(pThis); + + // coverity[leaked_storage:FALSE] return status; } diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/generated/g_object_nvoc.h nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_object_nvoc.h --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/generated/g_object_nvoc.h 2023-10-25 20:27:14.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_object_nvoc.h 2024-03-05 22:18:36.000000000 +0000 @@ -79,6 +79,7 @@ struct Object *pParent; struct NVOC_CHILD_TREE childTree; NvU32 ipVersion; + NvU32 createFlags; }; #ifndef __NVOC_CLASS_Object_TYPEDEF__ @@ -165,10 +166,10 @@ #undef PRIVATE_FIELD -// -// IP versioning definitions are temporary until NVOC halspec support is -// finished. -// +// +// IP versioning definitions are temporary until NVOC halspec support is +// finished. +// // IP_VERSION format as defined by the hardware engines. // A _MAJOR value of 0 means the object has no version number. // @@ -179,8 +180,6 @@ #define NV_ODB_IP_VER_MAJOR 31:24 /* R-IVF */ #define IPVersion(pObj) staticCast((pObj), Object)->ipVersion -#define IsIPVersionValid(pObj) (DRF_VAL(_ODB, _IP_VER, _MAJOR, IPVersion(pObj)) != 0) -#define IsIPVersionOrLater(pObj, v0) (IPVersion(pObj) >= (v0)) // v0 .. v1 inclusive #define IsIPVersionInRange(pObj, v0, v1) ((IPVersion(pObj) >= (v0)) && (IPVersion(pObj) <= (v1))) diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/generated/g_objgpumon_nvoc.c nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_objgpumon_nvoc.c --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/generated/g_objgpumon_nvoc.c 2023-10-25 20:27:15.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_objgpumon_nvoc.c 2024-03-05 22:18:36.000000000 +0000 @@ -66,10 +66,6 @@ /*pExportInfo=*/ &__nvoc_export_info_OBJGPUMON }; -static NV_STATUS __nvoc_thunk_OBJENGSTATE_gpumonReconcileTunableState(POBJGPU pGpu, struct OBJGPUMON *pEngstate, void *pTunableState) { - return engstateReconcileTunableState(pGpu, (struct OBJENGSTATE *)(((unsigned char *)pEngstate) + __nvoc_rtti_OBJGPUMON_OBJENGSTATE.offset), pTunableState); -} - static NV_STATUS __nvoc_thunk_OBJENGSTATE_gpumonStateLoad(POBJGPU pGpu, struct OBJGPUMON *pEngstate, NvU32 arg0) { return engstateStateLoad(pGpu, (struct OBJENGSTATE *)(((unsigned char *)pEngstate) + __nvoc_rtti_OBJGPUMON_OBJENGSTATE.offset), arg0); } @@ -114,30 +110,10 @@ return engstateStatePreInitUnlocked(pGpu, (struct OBJENGSTATE *)(((unsigned char *)pEngstate) + __nvoc_rtti_OBJGPUMON_OBJENGSTATE.offset)); } -static NV_STATUS __nvoc_thunk_OBJENGSTATE_gpumonGetTunableState(POBJGPU pGpu, struct OBJGPUMON *pEngstate, void *pTunableState) { - return engstateGetTunableState(pGpu, (struct OBJENGSTATE *)(((unsigned char *)pEngstate) + __nvoc_rtti_OBJGPUMON_OBJENGSTATE.offset), pTunableState); -} - -static NV_STATUS __nvoc_thunk_OBJENGSTATE_gpumonCompareTunableState(POBJGPU pGpu, struct OBJGPUMON *pEngstate, void *pTunables1, void *pTunables2) { - return engstateCompareTunableState(pGpu, (struct OBJENGSTATE *)(((unsigned char *)pEngstate) + __nvoc_rtti_OBJGPUMON_OBJENGSTATE.offset), pTunables1, pTunables2); -} - -static void __nvoc_thunk_OBJENGSTATE_gpumonFreeTunableState(POBJGPU pGpu, struct OBJGPUMON *pEngstate, void *pTunableState) { - engstateFreeTunableState(pGpu, (struct OBJENGSTATE *)(((unsigned char *)pEngstate) + __nvoc_rtti_OBJGPUMON_OBJENGSTATE.offset), pTunableState); -} - static NV_STATUS __nvoc_thunk_OBJENGSTATE_gpumonStatePostLoad(POBJGPU pGpu, struct OBJGPUMON *pEngstate, NvU32 arg0) { return engstateStatePostLoad(pGpu, (struct OBJENGSTATE *)(((unsigned char *)pEngstate) + __nvoc_rtti_OBJGPUMON_OBJENGSTATE.offset), arg0); } -static NV_STATUS __nvoc_thunk_OBJENGSTATE_gpumonAllocTunableState(POBJGPU pGpu, struct OBJGPUMON *pEngstate, void **ppTunableState) { - return engstateAllocTunableState(pGpu, (struct OBJENGSTATE *)(((unsigned char *)pEngstate) + __nvoc_rtti_OBJGPUMON_OBJENGSTATE.offset), ppTunableState); -} - -static NV_STATUS __nvoc_thunk_OBJENGSTATE_gpumonSetTunableState(POBJGPU pGpu, struct OBJGPUMON *pEngstate, void *pTunableState) { - return engstateSetTunableState(pGpu, (struct OBJENGSTATE *)(((unsigned char *)pEngstate) + __nvoc_rtti_OBJGPUMON_OBJENGSTATE.offset), pTunableState); -} - static NV_STATUS __nvoc_thunk_OBJENGSTATE_gpumonConstructEngine(POBJGPU pGpu, struct OBJGPUMON *pEngstate, ENGDESCRIPTOR arg0) { return engstateConstructEngine(pGpu, (struct OBJENGSTATE *)(((unsigned char *)pEngstate) + __nvoc_rtti_OBJGPUMON_OBJENGSTATE.offset), arg0); } @@ -189,8 +165,6 @@ PORT_UNREFERENCED_VARIABLE(chipHal); PORT_UNREFERENCED_VARIABLE(chipHal_HalVarIdx); - pThis->__gpumonReconcileTunableState__ = &__nvoc_thunk_OBJENGSTATE_gpumonReconcileTunableState; - pThis->__gpumonStateLoad__ = &__nvoc_thunk_OBJENGSTATE_gpumonStateLoad; pThis->__gpumonStateUnload__ = &__nvoc_thunk_OBJENGSTATE_gpumonStateUnload; @@ -213,18 +187,8 @@ pThis->__gpumonStatePreInitUnlocked__ = &__nvoc_thunk_OBJENGSTATE_gpumonStatePreInitUnlocked; - pThis->__gpumonGetTunableState__ = &__nvoc_thunk_OBJENGSTATE_gpumonGetTunableState; - - pThis->__gpumonCompareTunableState__ = &__nvoc_thunk_OBJENGSTATE_gpumonCompareTunableState; - - pThis->__gpumonFreeTunableState__ = &__nvoc_thunk_OBJENGSTATE_gpumonFreeTunableState; - pThis->__gpumonStatePostLoad__ = &__nvoc_thunk_OBJENGSTATE_gpumonStatePostLoad; - pThis->__gpumonAllocTunableState__ = &__nvoc_thunk_OBJENGSTATE_gpumonAllocTunableState; - - pThis->__gpumonSetTunableState__ = &__nvoc_thunk_OBJENGSTATE_gpumonSetTunableState; - pThis->__gpumonConstructEngine__ = &__nvoc_thunk_OBJENGSTATE_gpumonConstructEngine; pThis->__gpumonIsPresent__ = &__nvoc_thunk_OBJENGSTATE_gpumonIsPresent; @@ -249,13 +213,16 @@ OBJGPUMON *pThis; RmHalspecOwner *pRmhalspecowner; - pThis = portMemAllocNonPaged(sizeof(OBJGPUMON)); - if (pThis == NULL) return NV_ERR_NO_MEMORY; + status = __nvoc_handleObjCreateMemAlloc(createFlags, sizeof(OBJGPUMON), (void**)&pThis, (void**)ppThis); + if (status != NV_OK) + return status; portMemSet(pThis, 0, sizeof(OBJGPUMON)); __nvoc_initRtti(staticCast(pThis, Dynamic), &__nvoc_class_def_OBJGPUMON); + pThis->__nvoc_base_OBJENGSTATE.__nvoc_base_Object.createFlags = createFlags; + if (pParent != NULL && !(createFlags & NVOC_OBJ_CREATE_FLAGS_PARENT_HALSPEC_ONLY)) { pParentObj = dynamicCast(pParent, Object); @@ -275,11 +242,17 @@ if (status != NV_OK) goto __nvoc_objCreate_OBJGPUMON_cleanup; *ppThis = pThis; + return NV_OK; __nvoc_objCreate_OBJGPUMON_cleanup: // do not call destructors here since the constructor already called them - portMemFree(pThis); + if (createFlags & NVOC_OBJ_CREATE_FLAGS_IN_PLACE_CONSTRUCT) + portMemSet(pThis, 0, sizeof(OBJGPUMON)); + else + portMemFree(pThis); + + // coverity[leaked_storage:FALSE] return status; } diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/generated/g_objgpumon_nvoc.h nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_objgpumon_nvoc.h --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/generated/g_objgpumon_nvoc.h 2023-10-25 20:27:15.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_objgpumon_nvoc.h 2024-03-05 22:18:36.000000000 +0000 @@ -59,7 +59,6 @@ struct Object *__nvoc_pbase_Object; struct OBJENGSTATE *__nvoc_pbase_OBJENGSTATE; struct OBJGPUMON *__nvoc_pbase_OBJGPUMON; - NV_STATUS (*__gpumonReconcileTunableState__)(POBJGPU, struct OBJGPUMON *, void *); NV_STATUS (*__gpumonStateLoad__)(POBJGPU, struct OBJGPUMON *, NvU32); NV_STATUS (*__gpumonStateUnload__)(POBJGPU, struct OBJGPUMON *, NvU32); NV_STATUS (*__gpumonStateInitLocked__)(POBJGPU, struct OBJGPUMON *); @@ -71,12 +70,7 @@ void (*__gpumonInitMissing__)(POBJGPU, struct OBJGPUMON *); NV_STATUS (*__gpumonStatePreInitLocked__)(POBJGPU, struct OBJGPUMON *); NV_STATUS (*__gpumonStatePreInitUnlocked__)(POBJGPU, struct OBJGPUMON *); - NV_STATUS (*__gpumonGetTunableState__)(POBJGPU, struct OBJGPUMON *, void *); - NV_STATUS (*__gpumonCompareTunableState__)(POBJGPU, struct OBJGPUMON *, void *, void *); - void (*__gpumonFreeTunableState__)(POBJGPU, struct OBJGPUMON *, void *); NV_STATUS (*__gpumonStatePostLoad__)(POBJGPU, struct OBJGPUMON *, NvU32); - NV_STATUS (*__gpumonAllocTunableState__)(POBJGPU, struct OBJGPUMON *, void **); - NV_STATUS (*__gpumonSetTunableState__)(POBJGPU, struct OBJGPUMON *, void *); NV_STATUS (*__gpumonConstructEngine__)(POBJGPU, struct OBJGPUMON *, ENGDESCRIPTOR); NvBool (*__gpumonIsPresent__)(POBJGPU, struct OBJGPUMON *); }; @@ -111,7 +105,6 @@ #define __objCreate_OBJGPUMON(ppNewObj, pParent, createFlags) \ __nvoc_objCreate_OBJGPUMON((ppNewObj), staticCast((pParent), Dynamic), (createFlags)) -#define gpumonReconcileTunableState(pGpu, pEngstate, pTunableState) gpumonReconcileTunableState_DISPATCH(pGpu, pEngstate, pTunableState) #define gpumonStateLoad(pGpu, pEngstate, arg0) gpumonStateLoad_DISPATCH(pGpu, pEngstate, arg0) #define gpumonStateUnload(pGpu, pEngstate, arg0) gpumonStateUnload_DISPATCH(pGpu, pEngstate, arg0) #define gpumonStateInitLocked(pGpu, pEngstate) gpumonStateInitLocked_DISPATCH(pGpu, pEngstate) @@ -123,12 +116,7 @@ #define gpumonInitMissing(pGpu, pEngstate) gpumonInitMissing_DISPATCH(pGpu, pEngstate) #define gpumonStatePreInitLocked(pGpu, pEngstate) gpumonStatePreInitLocked_DISPATCH(pGpu, pEngstate) #define gpumonStatePreInitUnlocked(pGpu, pEngstate) gpumonStatePreInitUnlocked_DISPATCH(pGpu, pEngstate) -#define gpumonGetTunableState(pGpu, pEngstate, pTunableState) gpumonGetTunableState_DISPATCH(pGpu, pEngstate, pTunableState) -#define gpumonCompareTunableState(pGpu, pEngstate, pTunables1, pTunables2) gpumonCompareTunableState_DISPATCH(pGpu, pEngstate, pTunables1, pTunables2) -#define gpumonFreeTunableState(pGpu, pEngstate, pTunableState) gpumonFreeTunableState_DISPATCH(pGpu, pEngstate, pTunableState) #define gpumonStatePostLoad(pGpu, pEngstate, arg0) gpumonStatePostLoad_DISPATCH(pGpu, pEngstate, arg0) -#define gpumonAllocTunableState(pGpu, pEngstate, ppTunableState) gpumonAllocTunableState_DISPATCH(pGpu, pEngstate, ppTunableState) -#define gpumonSetTunableState(pGpu, pEngstate, pTunableState) gpumonSetTunableState_DISPATCH(pGpu, pEngstate, pTunableState) #define gpumonConstructEngine(pGpu, pEngstate, arg0) gpumonConstructEngine_DISPATCH(pGpu, pEngstate, arg0) #define gpumonIsPresent(pGpu, pEngstate) gpumonIsPresent_DISPATCH(pGpu, pEngstate) void gpumonGetContextProcessInfo_GM107(struct OBJGPU *pGpu, struct OBJGPUMON *pGpumon, RM_ENGINE_TYPE rmEngineTypeBegin, RM_ENGINE_TYPE rmEngineTypeEnd, NvU32 context, NvU32 *pProcID, NvU32 *pSubProcessID, const char **pSubProcessName); @@ -144,10 +132,6 @@ #define gpumonGetContextProcessInfo_HAL(pGpu, pGpumon, rmEngineTypeBegin, rmEngineTypeEnd, context, pProcID, pSubProcessID, pSubProcessName) gpumonGetContextProcessInfo(pGpu, pGpumon, rmEngineTypeBegin, rmEngineTypeEnd, context, pProcID, pSubProcessID, pSubProcessName) -static inline NV_STATUS gpumonReconcileTunableState_DISPATCH(POBJGPU pGpu, struct OBJGPUMON *pEngstate, void *pTunableState) { - return pEngstate->__gpumonReconcileTunableState__(pGpu, pEngstate, pTunableState); -} - static inline NV_STATUS gpumonStateLoad_DISPATCH(POBJGPU pGpu, struct OBJGPUMON *pEngstate, NvU32 arg0) { return pEngstate->__gpumonStateLoad__(pGpu, pEngstate, arg0); } @@ -192,30 +176,10 @@ return pEngstate->__gpumonStatePreInitUnlocked__(pGpu, pEngstate); } -static inline NV_STATUS gpumonGetTunableState_DISPATCH(POBJGPU pGpu, struct OBJGPUMON *pEngstate, void *pTunableState) { - return pEngstate->__gpumonGetTunableState__(pGpu, pEngstate, pTunableState); -} - -static inline NV_STATUS gpumonCompareTunableState_DISPATCH(POBJGPU pGpu, struct OBJGPUMON *pEngstate, void *pTunables1, void *pTunables2) { - return pEngstate->__gpumonCompareTunableState__(pGpu, pEngstate, pTunables1, pTunables2); -} - -static inline void gpumonFreeTunableState_DISPATCH(POBJGPU pGpu, struct OBJGPUMON *pEngstate, void *pTunableState) { - pEngstate->__gpumonFreeTunableState__(pGpu, pEngstate, pTunableState); -} - static inline NV_STATUS gpumonStatePostLoad_DISPATCH(POBJGPU pGpu, struct OBJGPUMON *pEngstate, NvU32 arg0) { return pEngstate->__gpumonStatePostLoad__(pGpu, pEngstate, arg0); } -static inline NV_STATUS gpumonAllocTunableState_DISPATCH(POBJGPU pGpu, struct OBJGPUMON *pEngstate, void **ppTunableState) { - return pEngstate->__gpumonAllocTunableState__(pGpu, pEngstate, ppTunableState); -} - -static inline NV_STATUS gpumonSetTunableState_DISPATCH(POBJGPU pGpu, struct OBJGPUMON *pEngstate, void *pTunableState) { - return pEngstate->__gpumonSetTunableState__(pGpu, pEngstate, pTunableState); -} - static inline NV_STATUS gpumonConstructEngine_DISPATCH(POBJGPU pGpu, struct OBJGPUMON *pEngstate, ENGDESCRIPTOR arg0) { return pEngstate->__gpumonConstructEngine__(pGpu, pEngstate, arg0); } diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/generated/g_objsweng_nvoc.c nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_objsweng_nvoc.c --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/generated/g_objsweng_nvoc.c 2023-10-25 20:27:15.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_objsweng_nvoc.c 2024-03-05 22:18:36.000000000 +0000 @@ -70,10 +70,6 @@ return swengConstructEngine(pGpu, (struct OBJSWENG *)(((unsigned char *)pSweng) - __nvoc_rtti_OBJSWENG_OBJENGSTATE.offset), arg0); } -static NV_STATUS __nvoc_thunk_OBJENGSTATE_swengReconcileTunableState(POBJGPU pGpu, struct OBJSWENG *pEngstate, void *pTunableState) { - return engstateReconcileTunableState(pGpu, (struct OBJENGSTATE *)(((unsigned char *)pEngstate) + __nvoc_rtti_OBJSWENG_OBJENGSTATE.offset), pTunableState); -} - static NV_STATUS __nvoc_thunk_OBJENGSTATE_swengStateLoad(POBJGPU pGpu, struct OBJSWENG *pEngstate, NvU32 arg0) { return engstateStateLoad(pGpu, (struct OBJENGSTATE *)(((unsigned char *)pEngstate) + __nvoc_rtti_OBJSWENG_OBJENGSTATE.offset), arg0); } @@ -118,30 +114,10 @@ return engstateStatePreInitUnlocked(pGpu, (struct OBJENGSTATE *)(((unsigned char *)pEngstate) + __nvoc_rtti_OBJSWENG_OBJENGSTATE.offset)); } -static NV_STATUS __nvoc_thunk_OBJENGSTATE_swengGetTunableState(POBJGPU pGpu, struct OBJSWENG *pEngstate, void *pTunableState) { - return engstateGetTunableState(pGpu, (struct OBJENGSTATE *)(((unsigned char *)pEngstate) + __nvoc_rtti_OBJSWENG_OBJENGSTATE.offset), pTunableState); -} - -static NV_STATUS __nvoc_thunk_OBJENGSTATE_swengCompareTunableState(POBJGPU pGpu, struct OBJSWENG *pEngstate, void *pTunables1, void *pTunables2) { - return engstateCompareTunableState(pGpu, (struct OBJENGSTATE *)(((unsigned char *)pEngstate) + __nvoc_rtti_OBJSWENG_OBJENGSTATE.offset), pTunables1, pTunables2); -} - -static void __nvoc_thunk_OBJENGSTATE_swengFreeTunableState(POBJGPU pGpu, struct OBJSWENG *pEngstate, void *pTunableState) { - engstateFreeTunableState(pGpu, (struct OBJENGSTATE *)(((unsigned char *)pEngstate) + __nvoc_rtti_OBJSWENG_OBJENGSTATE.offset), pTunableState); -} - static NV_STATUS __nvoc_thunk_OBJENGSTATE_swengStatePostLoad(POBJGPU pGpu, struct OBJSWENG *pEngstate, NvU32 arg0) { return engstateStatePostLoad(pGpu, (struct OBJENGSTATE *)(((unsigned char *)pEngstate) + __nvoc_rtti_OBJSWENG_OBJENGSTATE.offset), arg0); } -static NV_STATUS __nvoc_thunk_OBJENGSTATE_swengAllocTunableState(POBJGPU pGpu, struct OBJSWENG *pEngstate, void **ppTunableState) { - return engstateAllocTunableState(pGpu, (struct OBJENGSTATE *)(((unsigned char *)pEngstate) + __nvoc_rtti_OBJSWENG_OBJENGSTATE.offset), ppTunableState); -} - -static NV_STATUS __nvoc_thunk_OBJENGSTATE_swengSetTunableState(POBJGPU pGpu, struct OBJSWENG *pEngstate, void *pTunableState) { - return engstateSetTunableState(pGpu, (struct OBJENGSTATE *)(((unsigned char *)pEngstate) + __nvoc_rtti_OBJSWENG_OBJENGSTATE.offset), pTunableState); -} - static NvBool __nvoc_thunk_OBJENGSTATE_swengIsPresent(POBJGPU pGpu, struct OBJSWENG *pEngstate) { return engstateIsPresent(pGpu, (struct OBJENGSTATE *)(((unsigned char *)pEngstate) + __nvoc_rtti_OBJSWENG_OBJENGSTATE.offset)); } @@ -183,8 +159,6 @@ pThis->__nvoc_base_OBJENGSTATE.__engstateConstructEngine__ = &__nvoc_thunk_OBJSWENG_engstateConstructEngine; - pThis->__swengReconcileTunableState__ = &__nvoc_thunk_OBJENGSTATE_swengReconcileTunableState; - pThis->__swengStateLoad__ = &__nvoc_thunk_OBJENGSTATE_swengStateLoad; pThis->__swengStateUnload__ = &__nvoc_thunk_OBJENGSTATE_swengStateUnload; @@ -207,18 +181,8 @@ pThis->__swengStatePreInitUnlocked__ = &__nvoc_thunk_OBJENGSTATE_swengStatePreInitUnlocked; - pThis->__swengGetTunableState__ = &__nvoc_thunk_OBJENGSTATE_swengGetTunableState; - - pThis->__swengCompareTunableState__ = &__nvoc_thunk_OBJENGSTATE_swengCompareTunableState; - - pThis->__swengFreeTunableState__ = &__nvoc_thunk_OBJENGSTATE_swengFreeTunableState; - pThis->__swengStatePostLoad__ = &__nvoc_thunk_OBJENGSTATE_swengStatePostLoad; - pThis->__swengAllocTunableState__ = &__nvoc_thunk_OBJENGSTATE_swengAllocTunableState; - - pThis->__swengSetTunableState__ = &__nvoc_thunk_OBJENGSTATE_swengSetTunableState; - pThis->__swengIsPresent__ = &__nvoc_thunk_OBJENGSTATE_swengIsPresent; } @@ -240,13 +204,16 @@ Object *pParentObj; OBJSWENG *pThis; - pThis = portMemAllocNonPaged(sizeof(OBJSWENG)); - if (pThis == NULL) return NV_ERR_NO_MEMORY; + status = __nvoc_handleObjCreateMemAlloc(createFlags, sizeof(OBJSWENG), (void**)&pThis, (void**)ppThis); + if (status != NV_OK) + return status; portMemSet(pThis, 0, sizeof(OBJSWENG)); __nvoc_initRtti(staticCast(pThis, Dynamic), &__nvoc_class_def_OBJSWENG); + pThis->__nvoc_base_OBJENGSTATE.__nvoc_base_Object.createFlags = createFlags; + if (pParent != NULL && !(createFlags & NVOC_OBJ_CREATE_FLAGS_PARENT_HALSPEC_ONLY)) { pParentObj = dynamicCast(pParent, Object); @@ -262,11 +229,17 @@ if (status != NV_OK) goto __nvoc_objCreate_OBJSWENG_cleanup; *ppThis = pThis; + return NV_OK; __nvoc_objCreate_OBJSWENG_cleanup: // do not call destructors here since the constructor already called them - portMemFree(pThis); + if (createFlags & NVOC_OBJ_CREATE_FLAGS_IN_PLACE_CONSTRUCT) + portMemSet(pThis, 0, sizeof(OBJSWENG)); + else + portMemFree(pThis); + + // coverity[leaked_storage:FALSE] return status; } diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/generated/g_objsweng_nvoc.h nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_objsweng_nvoc.h --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/generated/g_objsweng_nvoc.h 2023-10-25 20:27:15.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_objsweng_nvoc.h 2024-03-05 22:18:37.000000000 +0000 @@ -59,7 +59,6 @@ struct OBJENGSTATE *__nvoc_pbase_OBJENGSTATE; struct OBJSWENG *__nvoc_pbase_OBJSWENG; NV_STATUS (*__swengConstructEngine__)(struct OBJGPU *, struct OBJSWENG *, ENGDESCRIPTOR); - NV_STATUS (*__swengReconcileTunableState__)(POBJGPU, struct OBJSWENG *, void *); NV_STATUS (*__swengStateLoad__)(POBJGPU, struct OBJSWENG *, NvU32); NV_STATUS (*__swengStateUnload__)(POBJGPU, struct OBJSWENG *, NvU32); NV_STATUS (*__swengStateInitLocked__)(POBJGPU, struct OBJSWENG *); @@ -71,12 +70,7 @@ void (*__swengInitMissing__)(POBJGPU, struct OBJSWENG *); NV_STATUS (*__swengStatePreInitLocked__)(POBJGPU, struct OBJSWENG *); NV_STATUS (*__swengStatePreInitUnlocked__)(POBJGPU, struct OBJSWENG *); - NV_STATUS (*__swengGetTunableState__)(POBJGPU, struct OBJSWENG *, void *); - NV_STATUS (*__swengCompareTunableState__)(POBJGPU, struct OBJSWENG *, void *, void *); - void (*__swengFreeTunableState__)(POBJGPU, struct OBJSWENG *, void *); NV_STATUS (*__swengStatePostLoad__)(POBJGPU, struct OBJSWENG *, NvU32); - NV_STATUS (*__swengAllocTunableState__)(POBJGPU, struct OBJSWENG *, void **); - NV_STATUS (*__swengSetTunableState__)(POBJGPU, struct OBJSWENG *, void *); NvBool (*__swengIsPresent__)(POBJGPU, struct OBJSWENG *); }; @@ -111,7 +105,6 @@ __nvoc_objCreate_OBJSWENG((ppNewObj), staticCast((pParent), Dynamic), (createFlags)) #define swengConstructEngine(pGpu, pSweng, arg0) swengConstructEngine_DISPATCH(pGpu, pSweng, arg0) -#define swengReconcileTunableState(pGpu, pEngstate, pTunableState) swengReconcileTunableState_DISPATCH(pGpu, pEngstate, pTunableState) #define swengStateLoad(pGpu, pEngstate, arg0) swengStateLoad_DISPATCH(pGpu, pEngstate, arg0) #define swengStateUnload(pGpu, pEngstate, arg0) swengStateUnload_DISPATCH(pGpu, pEngstate, arg0) #define swengStateInitLocked(pGpu, pEngstate) swengStateInitLocked_DISPATCH(pGpu, pEngstate) @@ -123,12 +116,7 @@ #define swengInitMissing(pGpu, pEngstate) swengInitMissing_DISPATCH(pGpu, pEngstate) #define swengStatePreInitLocked(pGpu, pEngstate) swengStatePreInitLocked_DISPATCH(pGpu, pEngstate) #define swengStatePreInitUnlocked(pGpu, pEngstate) swengStatePreInitUnlocked_DISPATCH(pGpu, pEngstate) -#define swengGetTunableState(pGpu, pEngstate, pTunableState) swengGetTunableState_DISPATCH(pGpu, pEngstate, pTunableState) -#define swengCompareTunableState(pGpu, pEngstate, pTunables1, pTunables2) swengCompareTunableState_DISPATCH(pGpu, pEngstate, pTunables1, pTunables2) -#define swengFreeTunableState(pGpu, pEngstate, pTunableState) swengFreeTunableState_DISPATCH(pGpu, pEngstate, pTunableState) #define swengStatePostLoad(pGpu, pEngstate, arg0) swengStatePostLoad_DISPATCH(pGpu, pEngstate, arg0) -#define swengAllocTunableState(pGpu, pEngstate, ppTunableState) swengAllocTunableState_DISPATCH(pGpu, pEngstate, ppTunableState) -#define swengSetTunableState(pGpu, pEngstate, pTunableState) swengSetTunableState_DISPATCH(pGpu, pEngstate, pTunableState) #define swengIsPresent(pGpu, pEngstate) swengIsPresent_DISPATCH(pGpu, pEngstate) NV_STATUS swengConstructEngine_IMPL(struct OBJGPU *pGpu, struct OBJSWENG *pSweng, ENGDESCRIPTOR arg0); @@ -136,10 +124,6 @@ return pSweng->__swengConstructEngine__(pGpu, pSweng, arg0); } -static inline NV_STATUS swengReconcileTunableState_DISPATCH(POBJGPU pGpu, struct OBJSWENG *pEngstate, void *pTunableState) { - return pEngstate->__swengReconcileTunableState__(pGpu, pEngstate, pTunableState); -} - static inline NV_STATUS swengStateLoad_DISPATCH(POBJGPU pGpu, struct OBJSWENG *pEngstate, NvU32 arg0) { return pEngstate->__swengStateLoad__(pGpu, pEngstate, arg0); } @@ -184,30 +168,10 @@ return pEngstate->__swengStatePreInitUnlocked__(pGpu, pEngstate); } -static inline NV_STATUS swengGetTunableState_DISPATCH(POBJGPU pGpu, struct OBJSWENG *pEngstate, void *pTunableState) { - return pEngstate->__swengGetTunableState__(pGpu, pEngstate, pTunableState); -} - -static inline NV_STATUS swengCompareTunableState_DISPATCH(POBJGPU pGpu, struct OBJSWENG *pEngstate, void *pTunables1, void *pTunables2) { - return pEngstate->__swengCompareTunableState__(pGpu, pEngstate, pTunables1, pTunables2); -} - -static inline void swengFreeTunableState_DISPATCH(POBJGPU pGpu, struct OBJSWENG *pEngstate, void *pTunableState) { - pEngstate->__swengFreeTunableState__(pGpu, pEngstate, pTunableState); -} - static inline NV_STATUS swengStatePostLoad_DISPATCH(POBJGPU pGpu, struct OBJSWENG *pEngstate, NvU32 arg0) { return pEngstate->__swengStatePostLoad__(pGpu, pEngstate, arg0); } -static inline NV_STATUS swengAllocTunableState_DISPATCH(POBJGPU pGpu, struct OBJSWENG *pEngstate, void **ppTunableState) { - return pEngstate->__swengAllocTunableState__(pGpu, pEngstate, ppTunableState); -} - -static inline NV_STATUS swengSetTunableState_DISPATCH(POBJGPU pGpu, struct OBJSWENG *pEngstate, void *pTunableState) { - return pEngstate->__swengSetTunableState__(pGpu, pEngstate, pTunableState); -} - static inline NvBool swengIsPresent_DISPATCH(POBJGPU pGpu, struct OBJSWENG *pEngstate) { return pEngstate->__swengIsPresent__(pGpu, pEngstate); } diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/generated/g_objtmr_nvoc.c nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_objtmr_nvoc.c --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/generated/g_objtmr_nvoc.c 2023-10-25 20:27:15.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_objtmr_nvoc.c 2024-03-05 22:18:37.000000000 +0000 @@ -75,7 +75,7 @@ /*pExportInfo=*/ &__nvoc_export_info_OBJTMR }; -static void __nvoc_thunk_OBJTMR_intrservRegisterIntrService(OBJGPU *pGpu, struct IntrService *pTmr, IntrServiceRecord pRecords[163]) { +static void __nvoc_thunk_OBJTMR_intrservRegisterIntrService(OBJGPU *pGpu, struct IntrService *pTmr, IntrServiceRecord pRecords[167]) { tmrRegisterIntrService(pGpu, (struct OBJTMR *)(((unsigned char *)pTmr) - __nvoc_rtti_OBJTMR_IntrService.offset), pRecords); } @@ -111,10 +111,6 @@ tmrStateDestroy(pGpu, (struct OBJTMR *)(((unsigned char *)pTmr) - __nvoc_rtti_OBJTMR_OBJENGSTATE.offset)); } -static NV_STATUS __nvoc_thunk_OBJENGSTATE_tmrReconcileTunableState(POBJGPU pGpu, struct OBJTMR *pEngstate, void *pTunableState) { - return engstateReconcileTunableState(pGpu, (struct OBJENGSTATE *)(((unsigned char *)pEngstate) + __nvoc_rtti_OBJTMR_OBJENGSTATE.offset), pTunableState); -} - static NV_STATUS __nvoc_thunk_IntrService_tmrServiceNotificationInterrupt(OBJGPU *pGpu, struct OBJTMR *pIntrService, IntrServiceServiceNotificationInterruptArguments *pParams) { return intrservServiceNotificationInterrupt(pGpu, (struct IntrService *)(((unsigned char *)pIntrService) + __nvoc_rtti_OBJTMR_IntrService.offset), pParams); } @@ -143,30 +139,10 @@ return engstateStatePreInitUnlocked(pGpu, (struct OBJENGSTATE *)(((unsigned char *)pEngstate) + __nvoc_rtti_OBJTMR_OBJENGSTATE.offset)); } -static NV_STATUS __nvoc_thunk_OBJENGSTATE_tmrGetTunableState(POBJGPU pGpu, struct OBJTMR *pEngstate, void *pTunableState) { - return engstateGetTunableState(pGpu, (struct OBJENGSTATE *)(((unsigned char *)pEngstate) + __nvoc_rtti_OBJTMR_OBJENGSTATE.offset), pTunableState); -} - -static NV_STATUS __nvoc_thunk_OBJENGSTATE_tmrCompareTunableState(POBJGPU pGpu, struct OBJTMR *pEngstate, void *pTunables1, void *pTunables2) { - return engstateCompareTunableState(pGpu, (struct OBJENGSTATE *)(((unsigned char *)pEngstate) + __nvoc_rtti_OBJTMR_OBJENGSTATE.offset), pTunables1, pTunables2); -} - -static void __nvoc_thunk_OBJENGSTATE_tmrFreeTunableState(POBJGPU pGpu, struct OBJTMR *pEngstate, void *pTunableState) { - engstateFreeTunableState(pGpu, (struct OBJENGSTATE *)(((unsigned char *)pEngstate) + __nvoc_rtti_OBJTMR_OBJENGSTATE.offset), pTunableState); -} - static NV_STATUS __nvoc_thunk_OBJENGSTATE_tmrStatePostLoad(POBJGPU pGpu, struct OBJTMR *pEngstate, NvU32 arg0) { return engstateStatePostLoad(pGpu, (struct OBJENGSTATE *)(((unsigned char *)pEngstate) + __nvoc_rtti_OBJTMR_OBJENGSTATE.offset), arg0); } -static NV_STATUS __nvoc_thunk_OBJENGSTATE_tmrAllocTunableState(POBJGPU pGpu, struct OBJTMR *pEngstate, void **ppTunableState) { - return engstateAllocTunableState(pGpu, (struct OBJENGSTATE *)(((unsigned char *)pEngstate) + __nvoc_rtti_OBJTMR_OBJENGSTATE.offset), ppTunableState); -} - -static NV_STATUS __nvoc_thunk_OBJENGSTATE_tmrSetTunableState(POBJGPU pGpu, struct OBJTMR *pEngstate, void *pTunableState) { - return engstateSetTunableState(pGpu, (struct OBJENGSTATE *)(((unsigned char *)pEngstate) + __nvoc_rtti_OBJTMR_OBJENGSTATE.offset), pTunableState); -} - static NvBool __nvoc_thunk_OBJENGSTATE_tmrIsPresent(POBJGPU pGpu, struct OBJTMR *pEngstate) { return engstateIsPresent(pGpu, (struct OBJENGSTATE *)(((unsigned char *)pEngstate) + __nvoc_rtti_OBJTMR_OBJENGSTATE.offset)); } @@ -271,10 +247,7 @@ pThis->__tmrClearInterrupt__ = &tmrClearInterrupt_IMPL; // Hal function -- tmrServiceInterrupt - if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000002UL) )) /* RmVariantHal: PF_KERNEL_ONLY */ - { - pThis->__tmrServiceInterrupt__ = &tmrServiceInterrupt_56cd7a; - } + pThis->__tmrServiceInterrupt__ = &tmrServiceInterrupt_56cd7a; pThis->__tmrConstructEngine__ = &tmrConstructEngine_IMPL; @@ -289,59 +262,53 @@ pThis->__tmrStateDestroy__ = &tmrStateDestroy_IMPL; // Hal function -- tmrSetCurrentTime - if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000002UL) )) /* RmVariantHal: PF_KERNEL_ONLY */ + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ { - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x01f0ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 */ - { - pThis->__tmrSetCurrentTime__ = &tmrSetCurrentTime_GV100; - } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ - { - pThis->__tmrSetCurrentTime__ = &tmrSetCurrentTime_GH100; - } + pThis->__tmrSetCurrentTime__ = &tmrSetCurrentTime_GH100; + } + else + { + pThis->__tmrSetCurrentTime__ = &tmrSetCurrentTime_GV100; } // Hal function -- tmrGetTimeEx - if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000002UL) )) /* RmVariantHal: PF_KERNEL_ONLY */ + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ + { + pThis->__tmrGetTimeEx__ = &tmrGetTimeEx_GH100; + } + else { - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x01f0ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 */ - { - pThis->__tmrGetTimeEx__ = &tmrGetTimeEx_GM107; - } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ - { - pThis->__tmrGetTimeEx__ = &tmrGetTimeEx_GH100; - } + pThis->__tmrGetTimeEx__ = &tmrGetTimeEx_GM107; } // Hal function -- tmrSetCountdownIntrDisable - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x01f0ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 */ + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ { - pThis->__tmrSetCountdownIntrDisable__ = &tmrSetCountdownIntrDisable_GM200; + pThis->__tmrSetCountdownIntrDisable__ = &tmrSetCountdownIntrDisable_56cd7a; } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ + else { - pThis->__tmrSetCountdownIntrDisable__ = &tmrSetCountdownIntrDisable_56cd7a; + pThis->__tmrSetCountdownIntrDisable__ = &tmrSetCountdownIntrDisable_GM200; } // Hal function -- tmrSetCountdown - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x01f0ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 */ + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ { - pThis->__tmrSetCountdown__ = &tmrSetCountdown_TU102; + pThis->__tmrSetCountdown__ = &tmrSetCountdown_GH100; } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ + else { - pThis->__tmrSetCountdown__ = &tmrSetCountdown_GH100; + pThis->__tmrSetCountdown__ = &tmrSetCountdown_TU102; } // Hal function -- tmrGrTickFreqChange - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x01f0ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 */ + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ { - pThis->__tmrGrTickFreqChange__ = &tmrGrTickFreqChange_GM107; + pThis->__tmrGrTickFreqChange__ = &tmrGrTickFreqChange_46f6a7; } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ + else { - pThis->__tmrGrTickFreqChange__ = &tmrGrTickFreqChange_46f6a7; + pThis->__tmrGrTickFreqChange__ = &tmrGrTickFreqChange_GM107; } // Hal function -- tmrGetGpuPtimerOffset @@ -349,7 +316,7 @@ { pThis->__tmrGetGpuPtimerOffset__ = &tmrGetGpuPtimerOffset_TU102; } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x11f0fc00UL) )) /* ChipHal: GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 | GH100 */ + else { pThis->__tmrGetGpuPtimerOffset__ = &tmrGetGpuPtimerOffset_GA100; } @@ -372,8 +339,6 @@ pThis->__nvoc_base_OBJENGSTATE.__engstateStateDestroy__ = &__nvoc_thunk_OBJTMR_engstateStateDestroy; - pThis->__tmrReconcileTunableState__ = &__nvoc_thunk_OBJENGSTATE_tmrReconcileTunableState; - pThis->__tmrServiceNotificationInterrupt__ = &__nvoc_thunk_IntrService_tmrServiceNotificationInterrupt; pThis->__tmrStatePreLoad__ = &__nvoc_thunk_OBJENGSTATE_tmrStatePreLoad; @@ -388,18 +353,8 @@ pThis->__tmrStatePreInitUnlocked__ = &__nvoc_thunk_OBJENGSTATE_tmrStatePreInitUnlocked; - pThis->__tmrGetTunableState__ = &__nvoc_thunk_OBJENGSTATE_tmrGetTunableState; - - pThis->__tmrCompareTunableState__ = &__nvoc_thunk_OBJENGSTATE_tmrCompareTunableState; - - pThis->__tmrFreeTunableState__ = &__nvoc_thunk_OBJENGSTATE_tmrFreeTunableState; - pThis->__tmrStatePostLoad__ = &__nvoc_thunk_OBJENGSTATE_tmrStatePostLoad; - pThis->__tmrAllocTunableState__ = &__nvoc_thunk_OBJENGSTATE_tmrAllocTunableState; - - pThis->__tmrSetTunableState__ = &__nvoc_thunk_OBJENGSTATE_tmrSetTunableState; - pThis->__tmrIsPresent__ = &__nvoc_thunk_OBJENGSTATE_tmrIsPresent; } @@ -425,13 +380,16 @@ OBJTMR *pThis; RmHalspecOwner *pRmhalspecowner; - pThis = portMemAllocNonPaged(sizeof(OBJTMR)); - if (pThis == NULL) return NV_ERR_NO_MEMORY; + status = __nvoc_handleObjCreateMemAlloc(createFlags, sizeof(OBJTMR), (void**)&pThis, (void**)ppThis); + if (status != NV_OK) + return status; portMemSet(pThis, 0, sizeof(OBJTMR)); __nvoc_initRtti(staticCast(pThis, Dynamic), &__nvoc_class_def_OBJTMR); + pThis->__nvoc_base_OBJENGSTATE.__nvoc_base_Object.createFlags = createFlags; + if (pParent != NULL && !(createFlags & NVOC_OBJ_CREATE_FLAGS_PARENT_HALSPEC_ONLY)) { pParentObj = dynamicCast(pParent, Object); @@ -451,11 +409,17 @@ if (status != NV_OK) goto __nvoc_objCreate_OBJTMR_cleanup; *ppThis = pThis; + return NV_OK; __nvoc_objCreate_OBJTMR_cleanup: // do not call destructors here since the constructor already called them - portMemFree(pThis); + if (createFlags & NVOC_OBJ_CREATE_FLAGS_IN_PLACE_CONSTRUCT) + portMemSet(pThis, 0, sizeof(OBJTMR)); + else + portMemFree(pThis); + + // coverity[leaked_storage:FALSE] return status; } diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/generated/g_objtmr_nvoc.h nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_objtmr_nvoc.h --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/generated/g_objtmr_nvoc.h 2023-10-25 20:27:15.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_objtmr_nvoc.h 2024-03-05 22:18:37.000000000 +0000 @@ -7,7 +7,7 @@ #endif /* - * SPDX-FileCopyrightText: Copyright (c) 1993-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 1993-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -58,16 +58,26 @@ // Callback scheduled without any explicit flags set. #define TMR_FLAGS_NONE 0x00000000 +// // Automatically reschedule the callback, so that it repeats. // Otherwise, callback is scheduled for one-shot execution. +// #define TMR_FLAG_RECUR NVBIT(0) +// // Indicate that the implementation of the callback function will/can release // a GPU semaphore. This allows fifoIdleChannels to query this information, // and hence not bail out early if channels are blocked on semaphores that // will in fact be released. - // !!NOTE: This is OBSOLETE, it should be moved directly to FIFO, where it's needed +// !!NOTE: This is OBSOLETE, it should be moved directly to FIFO, where it's needed +// #define TMR_FLAG_RELEASE_SEMAPHORE NVBIT(1) #define TMR_FLAG_OS_TIMER_QUEUED NVBIT(2) +// +// Normally, it should not be necessary to use the TMR_FLAG_USE_OS_TIMER flag, +// because the OS timer is selected automatically by the default +// PDB_PROP_TMR_USE_OS_TIMER_FOR_CALLBACKS setting. +// Note that the OS timer is not supported in all environments (such as GSP-RM). +// #define TMR_FLAG_USE_OS_TIMER NVBIT(3) #define TMR_GET_GPU(p) ENG_GET_GPU(p) @@ -130,13 +140,14 @@ TMR_EVENT super; // Legacy Fields, soon to be obsoleted. - NvBool bLegacy; //__tmrRegisterIntrService__(pGpu, pTmr, pRecords); } @@ -855,10 +855,6 @@ return pTmr->__tmrGetGpuPtimerOffset__(pGpu, pTmr, arg0, arg1); } -static inline NV_STATUS tmrReconcileTunableState_DISPATCH(POBJGPU pGpu, struct OBJTMR *pEngstate, void *pTunableState) { - return pEngstate->__tmrReconcileTunableState__(pGpu, pEngstate, pTunableState); -} - static inline NV_STATUS tmrServiceNotificationInterrupt_DISPATCH(OBJGPU *pGpu, struct OBJTMR *pIntrService, IntrServiceServiceNotificationInterruptArguments *pParams) { return pIntrService->__tmrServiceNotificationInterrupt__(pGpu, pIntrService, pParams); } @@ -887,30 +883,10 @@ return pEngstate->__tmrStatePreInitUnlocked__(pGpu, pEngstate); } -static inline NV_STATUS tmrGetTunableState_DISPATCH(POBJGPU pGpu, struct OBJTMR *pEngstate, void *pTunableState) { - return pEngstate->__tmrGetTunableState__(pGpu, pEngstate, pTunableState); -} - -static inline NV_STATUS tmrCompareTunableState_DISPATCH(POBJGPU pGpu, struct OBJTMR *pEngstate, void *pTunables1, void *pTunables2) { - return pEngstate->__tmrCompareTunableState__(pGpu, pEngstate, pTunables1, pTunables2); -} - -static inline void tmrFreeTunableState_DISPATCH(POBJGPU pGpu, struct OBJTMR *pEngstate, void *pTunableState) { - pEngstate->__tmrFreeTunableState__(pGpu, pEngstate, pTunableState); -} - static inline NV_STATUS tmrStatePostLoad_DISPATCH(POBJGPU pGpu, struct OBJTMR *pEngstate, NvU32 arg0) { return pEngstate->__tmrStatePostLoad__(pGpu, pEngstate, arg0); } -static inline NV_STATUS tmrAllocTunableState_DISPATCH(POBJGPU pGpu, struct OBJTMR *pEngstate, void **ppTunableState) { - return pEngstate->__tmrAllocTunableState__(pGpu, pEngstate, ppTunableState); -} - -static inline NV_STATUS tmrSetTunableState_DISPATCH(POBJGPU pGpu, struct OBJTMR *pEngstate, void *pTunableState) { - return pEngstate->__tmrSetTunableState__(pGpu, pEngstate, pTunableState); -} - static inline NvBool tmrIsPresent_DISPATCH(POBJGPU pGpu, struct OBJTMR *pEngstate) { return pEngstate->__tmrIsPresent__(pGpu, pEngstate); } @@ -1105,6 +1081,17 @@ #define tmrEventOnList(pTmr, pEvent) tmrEventOnList_IMPL(pTmr, pEvent) #endif //__nvoc_objtmr_h_disabled +NV_STATUS tmrEventServiceTimer_IMPL(OBJGPU *pGpu, struct OBJTMR *pTmr, PTMR_EVENT pEvent); + +#ifdef __nvoc_objtmr_h_disabled +static inline NV_STATUS tmrEventServiceTimer(OBJGPU *pGpu, struct OBJTMR *pTmr, PTMR_EVENT pEvent) { + NV_ASSERT_FAILED_PRECOMP("OBJTMR was disabled!"); + return NV_ERR_NOT_SUPPORTED; +} +#else //__nvoc_objtmr_h_disabled +#define tmrEventServiceTimer(pGpu, pTmr, pEvent) tmrEventServiceTimer_IMPL(pGpu, pTmr, pEvent) +#endif //__nvoc_objtmr_h_disabled + NvBool tmrCallbackOnList_IMPL(struct OBJTMR *pTmr, TIMEPROC_OBSOLETE arg0, void *arg1); #ifdef __nvoc_objtmr_h_disabled diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/generated/g_os_desc_mem_nvoc.c nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_os_desc_mem_nvoc.c --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/generated/g_os_desc_mem_nvoc.c 2023-10-25 20:27:15.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_os_desc_mem_nvoc.c 2024-03-05 22:18:37.000000000 +0000 @@ -101,60 +101,76 @@ return memCheckMemInterUnmap((struct Memory *)(((unsigned char *)pMemory) + __nvoc_rtti_OsDescMemory_Memory.offset), bSubdeviceHandleProvided); } -static NV_STATUS __nvoc_thunk_Memory_osdescControl(struct OsDescMemory *pMemory, CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { - return memControl((struct Memory *)(((unsigned char *)pMemory) + __nvoc_rtti_OsDescMemory_Memory.offset), pCallContext, pParams); +static NvBool __nvoc_thunk_RmResource_osdescShareCallback(struct OsDescMemory *pResource, struct RsClient *pInvokingClient, struct RsResourceRef *pParentRef, RS_SHARE_POLICY *pSharePolicy) { + return rmresShareCallback((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_OsDescMemory_RmResource.offset), pInvokingClient, pParentRef, pSharePolicy); } -static NV_STATUS __nvoc_thunk_Memory_osdescUnmap(struct OsDescMemory *pMemory, CALL_CONTEXT *pCallContext, RsCpuMapping *pCpuMapping) { - return memUnmap((struct Memory *)(((unsigned char *)pMemory) + __nvoc_rtti_OsDescMemory_Memory.offset), pCallContext, pCpuMapping); +static NV_STATUS __nvoc_thunk_RsResource_osdescMapTo(struct OsDescMemory *pResource, RS_RES_MAP_TO_PARAMS *pParams) { + return resMapTo((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_OsDescMemory_RsResource.offset), pParams); } -static NV_STATUS __nvoc_thunk_Memory_osdescGetMemInterMapParams(struct OsDescMemory *pMemory, RMRES_MEM_INTER_MAP_PARAMS *pParams) { - return memGetMemInterMapParams((struct Memory *)(((unsigned char *)pMemory) + __nvoc_rtti_OsDescMemory_Memory.offset), pParams); +static NV_STATUS __nvoc_thunk_Memory_osdescGetMapAddrSpace(struct OsDescMemory *pMemory, CALL_CONTEXT *pCallContext, NvU32 mapFlags, NV_ADDRESS_SPACE *pAddrSpace) { + return memGetMapAddrSpace((struct Memory *)(((unsigned char *)pMemory) + __nvoc_rtti_OsDescMemory_Memory.offset), pCallContext, mapFlags, pAddrSpace); } -static NV_STATUS __nvoc_thunk_Memory_osdescGetMemoryMappingDescriptor(struct OsDescMemory *pMemory, MEMORY_DESCRIPTOR **ppMemDesc) { - return memGetMemoryMappingDescriptor((struct Memory *)(((unsigned char *)pMemory) + __nvoc_rtti_OsDescMemory_Memory.offset), ppMemDesc); +static NvU32 __nvoc_thunk_RsResource_osdescGetRefCount(struct OsDescMemory *pResource) { + return resGetRefCount((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_OsDescMemory_RsResource.offset)); } -static NV_STATUS __nvoc_thunk_Memory_osdescGetMapAddrSpace(struct OsDescMemory *pMemory, CALL_CONTEXT *pCallContext, NvU32 mapFlags, NV_ADDRESS_SPACE *pAddrSpace) { - return memGetMapAddrSpace((struct Memory *)(((unsigned char *)pMemory) + __nvoc_rtti_OsDescMemory_Memory.offset), pCallContext, mapFlags, pAddrSpace); +static void __nvoc_thunk_RsResource_osdescAddAdditionalDependants(struct RsClient *pClient, struct OsDescMemory *pResource, RsResourceRef *pReference) { + resAddAdditionalDependants(pClient, (struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_OsDescMemory_RsResource.offset), pReference); } -static NvBool __nvoc_thunk_RmResource_osdescShareCallback(struct OsDescMemory *pResource, struct RsClient *pInvokingClient, struct RsResourceRef *pParentRef, RS_SHARE_POLICY *pSharePolicy) { - return rmresShareCallback((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_OsDescMemory_RmResource.offset), pInvokingClient, pParentRef, pSharePolicy); +static NV_STATUS __nvoc_thunk_RmResource_osdescControl_Prologue(struct OsDescMemory *pResource, CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return rmresControl_Prologue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_OsDescMemory_RmResource.offset), pCallContext, pParams); } -static NV_STATUS __nvoc_thunk_RsResource_osdescControlFilter(struct OsDescMemory *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { - return resControlFilter((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_OsDescMemory_RsResource.offset), pCallContext, pParams); +static NvBool __nvoc_thunk_Memory_osdescIsGpuMapAllowed(struct OsDescMemory *pMemory, struct OBJGPU *pGpu) { + return memIsGpuMapAllowed((struct Memory *)(((unsigned char *)pMemory) + __nvoc_rtti_OsDescMemory_Memory.offset), pGpu); } -static void __nvoc_thunk_RsResource_osdescAddAdditionalDependants(struct RsClient *pClient, struct OsDescMemory *pResource, RsResourceRef *pReference) { - resAddAdditionalDependants(pClient, (struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_OsDescMemory_RsResource.offset), pReference); +static NV_STATUS __nvoc_thunk_RsResource_osdescUnmapFrom(struct OsDescMemory *pResource, RS_RES_UNMAP_FROM_PARAMS *pParams) { + return resUnmapFrom((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_OsDescMemory_RsResource.offset), pParams); } -static NvU32 __nvoc_thunk_RsResource_osdescGetRefCount(struct OsDescMemory *pResource) { - return resGetRefCount((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_OsDescMemory_RsResource.offset)); +static void __nvoc_thunk_RmResource_osdescControl_Epilogue(struct OsDescMemory *pResource, CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + rmresControl_Epilogue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_OsDescMemory_RmResource.offset), pCallContext, pParams); } -static NV_STATUS __nvoc_thunk_RsResource_osdescMapTo(struct OsDescMemory *pResource, RS_RES_MAP_TO_PARAMS *pParams) { - return resMapTo((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_OsDescMemory_RsResource.offset), pParams); +static NV_STATUS __nvoc_thunk_RsResource_osdescControlLookup(struct OsDescMemory *pResource, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams, const struct NVOC_EXPORTED_METHOD_DEF **ppEntry) { + return resControlLookup((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_OsDescMemory_RsResource.offset), pParams, ppEntry); } -static NV_STATUS __nvoc_thunk_RmResource_osdescControl_Prologue(struct OsDescMemory *pResource, CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { - return rmresControl_Prologue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_OsDescMemory_RmResource.offset), pCallContext, pParams); +static NV_STATUS __nvoc_thunk_Memory_osdescControl(struct OsDescMemory *pMemory, CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return memControl((struct Memory *)(((unsigned char *)pMemory) + __nvoc_rtti_OsDescMemory_Memory.offset), pCallContext, pParams); } -static NvBool __nvoc_thunk_Memory_osdescIsGpuMapAllowed(struct OsDescMemory *pMemory, struct OBJGPU *pGpu) { - return memIsGpuMapAllowed((struct Memory *)(((unsigned char *)pMemory) + __nvoc_rtti_OsDescMemory_Memory.offset), pGpu); +static NV_STATUS __nvoc_thunk_Memory_osdescUnmap(struct OsDescMemory *pMemory, CALL_CONTEXT *pCallContext, RsCpuMapping *pCpuMapping) { + return memUnmap((struct Memory *)(((unsigned char *)pMemory) + __nvoc_rtti_OsDescMemory_Memory.offset), pCallContext, pCpuMapping); +} + +static NV_STATUS __nvoc_thunk_Memory_osdescGetMemInterMapParams(struct OsDescMemory *pMemory, RMRES_MEM_INTER_MAP_PARAMS *pParams) { + return memGetMemInterMapParams((struct Memory *)(((unsigned char *)pMemory) + __nvoc_rtti_OsDescMemory_Memory.offset), pParams); +} + +static NV_STATUS __nvoc_thunk_Memory_osdescGetMemoryMappingDescriptor(struct OsDescMemory *pMemory, MEMORY_DESCRIPTOR **ppMemDesc) { + return memGetMemoryMappingDescriptor((struct Memory *)(((unsigned char *)pMemory) + __nvoc_rtti_OsDescMemory_Memory.offset), ppMemDesc); +} + +static NV_STATUS __nvoc_thunk_RsResource_osdescControlFilter(struct OsDescMemory *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return resControlFilter((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_OsDescMemory_RsResource.offset), pCallContext, pParams); +} + +static NV_STATUS __nvoc_thunk_RmResource_osdescControlSerialization_Prologue(struct OsDescMemory *pResource, CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return rmresControlSerialization_Prologue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_OsDescMemory_RmResource.offset), pCallContext, pParams); } static NV_STATUS __nvoc_thunk_Memory_osdescIsReady(struct OsDescMemory *pMemory, NvBool bCopyConstructorContext) { return memIsReady((struct Memory *)(((unsigned char *)pMemory) + __nvoc_rtti_OsDescMemory_Memory.offset), bCopyConstructorContext); } -static NV_STATUS __nvoc_thunk_Memory_osdescCheckCopyPermissions(struct OsDescMemory *pMemory, struct OBJGPU *pDstGpu, NvHandle hDstClientNvBool) { - return memCheckCopyPermissions((struct Memory *)(((unsigned char *)pMemory) + __nvoc_rtti_OsDescMemory_Memory.offset), pDstGpu, hDstClientNvBool); +static NV_STATUS __nvoc_thunk_Memory_osdescCheckCopyPermissions(struct OsDescMemory *pMemory, struct OBJGPU *pDstGpu, struct Device *pDstDevice) { + return memCheckCopyPermissions((struct Memory *)(((unsigned char *)pMemory) + __nvoc_rtti_OsDescMemory_Memory.offset), pDstGpu, pDstDevice); } static void __nvoc_thunk_RsResource_osdescPreDestruct(struct OsDescMemory *pResource) { @@ -165,16 +181,8 @@ return memIsDuplicate((struct Memory *)(((unsigned char *)pMemory) + __nvoc_rtti_OsDescMemory_Memory.offset), hMemory, pDuplicate); } -static NV_STATUS __nvoc_thunk_RsResource_osdescUnmapFrom(struct OsDescMemory *pResource, RS_RES_UNMAP_FROM_PARAMS *pParams) { - return resUnmapFrom((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_OsDescMemory_RsResource.offset), pParams); -} - -static void __nvoc_thunk_RmResource_osdescControl_Epilogue(struct OsDescMemory *pResource, CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { - rmresControl_Epilogue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_OsDescMemory_RmResource.offset), pCallContext, pParams); -} - -static NV_STATUS __nvoc_thunk_RsResource_osdescControlLookup(struct OsDescMemory *pResource, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams, const struct NVOC_EXPORTED_METHOD_DEF **ppEntry) { - return resControlLookup((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_OsDescMemory_RsResource.offset), pParams, ppEntry); +static void __nvoc_thunk_RmResource_osdescControlSerialization_Epilogue(struct OsDescMemory *pResource, CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + rmresControlSerialization_Epilogue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_OsDescMemory_RmResource.offset), pCallContext, pParams); } static NV_STATUS __nvoc_thunk_Memory_osdescMap(struct OsDescMemory *pMemory, CALL_CONTEXT *pCallContext, struct RS_CPU_MAP_PARAMS *pParams, RsCpuMapping *pCpuMapping) { @@ -229,29 +237,37 @@ pThis->__osdescCheckMemInterUnmap__ = &__nvoc_thunk_Memory_osdescCheckMemInterUnmap; - pThis->__osdescControl__ = &__nvoc_thunk_Memory_osdescControl; + pThis->__osdescShareCallback__ = &__nvoc_thunk_RmResource_osdescShareCallback; - pThis->__osdescUnmap__ = &__nvoc_thunk_Memory_osdescUnmap; + pThis->__osdescMapTo__ = &__nvoc_thunk_RsResource_osdescMapTo; - pThis->__osdescGetMemInterMapParams__ = &__nvoc_thunk_Memory_osdescGetMemInterMapParams; + pThis->__osdescGetMapAddrSpace__ = &__nvoc_thunk_Memory_osdescGetMapAddrSpace; - pThis->__osdescGetMemoryMappingDescriptor__ = &__nvoc_thunk_Memory_osdescGetMemoryMappingDescriptor; + pThis->__osdescGetRefCount__ = &__nvoc_thunk_RsResource_osdescGetRefCount; - pThis->__osdescGetMapAddrSpace__ = &__nvoc_thunk_Memory_osdescGetMapAddrSpace; + pThis->__osdescAddAdditionalDependants__ = &__nvoc_thunk_RsResource_osdescAddAdditionalDependants; - pThis->__osdescShareCallback__ = &__nvoc_thunk_RmResource_osdescShareCallback; + pThis->__osdescControl_Prologue__ = &__nvoc_thunk_RmResource_osdescControl_Prologue; - pThis->__osdescControlFilter__ = &__nvoc_thunk_RsResource_osdescControlFilter; + pThis->__osdescIsGpuMapAllowed__ = &__nvoc_thunk_Memory_osdescIsGpuMapAllowed; - pThis->__osdescAddAdditionalDependants__ = &__nvoc_thunk_RsResource_osdescAddAdditionalDependants; + pThis->__osdescUnmapFrom__ = &__nvoc_thunk_RsResource_osdescUnmapFrom; - pThis->__osdescGetRefCount__ = &__nvoc_thunk_RsResource_osdescGetRefCount; + pThis->__osdescControl_Epilogue__ = &__nvoc_thunk_RmResource_osdescControl_Epilogue; - pThis->__osdescMapTo__ = &__nvoc_thunk_RsResource_osdescMapTo; + pThis->__osdescControlLookup__ = &__nvoc_thunk_RsResource_osdescControlLookup; - pThis->__osdescControl_Prologue__ = &__nvoc_thunk_RmResource_osdescControl_Prologue; + pThis->__osdescControl__ = &__nvoc_thunk_Memory_osdescControl; - pThis->__osdescIsGpuMapAllowed__ = &__nvoc_thunk_Memory_osdescIsGpuMapAllowed; + pThis->__osdescUnmap__ = &__nvoc_thunk_Memory_osdescUnmap; + + pThis->__osdescGetMemInterMapParams__ = &__nvoc_thunk_Memory_osdescGetMemInterMapParams; + + pThis->__osdescGetMemoryMappingDescriptor__ = &__nvoc_thunk_Memory_osdescGetMemoryMappingDescriptor; + + pThis->__osdescControlFilter__ = &__nvoc_thunk_RsResource_osdescControlFilter; + + pThis->__osdescControlSerialization_Prologue__ = &__nvoc_thunk_RmResource_osdescControlSerialization_Prologue; pThis->__osdescIsReady__ = &__nvoc_thunk_Memory_osdescIsReady; @@ -261,11 +277,7 @@ pThis->__osdescIsDuplicate__ = &__nvoc_thunk_Memory_osdescIsDuplicate; - pThis->__osdescUnmapFrom__ = &__nvoc_thunk_RsResource_osdescUnmapFrom; - - pThis->__osdescControl_Epilogue__ = &__nvoc_thunk_RmResource_osdescControl_Epilogue; - - pThis->__osdescControlLookup__ = &__nvoc_thunk_RsResource_osdescControlLookup; + pThis->__osdescControlSerialization_Epilogue__ = &__nvoc_thunk_RmResource_osdescControlSerialization_Epilogue; pThis->__osdescMap__ = &__nvoc_thunk_Memory_osdescMap; @@ -293,13 +305,16 @@ Object *pParentObj; OsDescMemory *pThis; - pThis = portMemAllocNonPaged(sizeof(OsDescMemory)); - if (pThis == NULL) return NV_ERR_NO_MEMORY; + status = __nvoc_handleObjCreateMemAlloc(createFlags, sizeof(OsDescMemory), (void**)&pThis, (void**)ppThis); + if (status != NV_OK) + return status; portMemSet(pThis, 0, sizeof(OsDescMemory)); __nvoc_initRtti(staticCast(pThis, Dynamic), &__nvoc_class_def_OsDescMemory); + pThis->__nvoc_base_Memory.__nvoc_base_RmResource.__nvoc_base_RsResource.__nvoc_base_Object.createFlags = createFlags; + if (pParent != NULL && !(createFlags & NVOC_OBJ_CREATE_FLAGS_PARENT_HALSPEC_ONLY)) { pParentObj = dynamicCast(pParent, Object); @@ -315,11 +330,17 @@ if (status != NV_OK) goto __nvoc_objCreate_OsDescMemory_cleanup; *ppThis = pThis; + return NV_OK; __nvoc_objCreate_OsDescMemory_cleanup: // do not call destructors here since the constructor already called them - portMemFree(pThis); + if (createFlags & NVOC_OBJ_CREATE_FLAGS_IN_PLACE_CONSTRUCT) + portMemSet(pThis, 0, sizeof(OsDescMemory)); + else + portMemFree(pThis); + + // coverity[leaked_storage:FALSE] return status; } diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/generated/g_os_desc_mem_nvoc.h nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_os_desc_mem_nvoc.h --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/generated/g_os_desc_mem_nvoc.h 2023-10-25 20:27:15.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_os_desc_mem_nvoc.h 2024-03-05 22:18:37.000000000 +0000 @@ -55,25 +55,27 @@ struct OsDescMemory *__nvoc_pbase_OsDescMemory; NvBool (*__osdescCanCopy__)(struct OsDescMemory *); NV_STATUS (*__osdescCheckMemInterUnmap__)(struct OsDescMemory *, NvBool); + NvBool (*__osdescShareCallback__)(struct OsDescMemory *, struct RsClient *, struct RsResourceRef *, RS_SHARE_POLICY *); + NV_STATUS (*__osdescMapTo__)(struct OsDescMemory *, RS_RES_MAP_TO_PARAMS *); + NV_STATUS (*__osdescGetMapAddrSpace__)(struct OsDescMemory *, CALL_CONTEXT *, NvU32, NV_ADDRESS_SPACE *); + NvU32 (*__osdescGetRefCount__)(struct OsDescMemory *); + void (*__osdescAddAdditionalDependants__)(struct RsClient *, struct OsDescMemory *, RsResourceRef *); + NV_STATUS (*__osdescControl_Prologue__)(struct OsDescMemory *, CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); + NvBool (*__osdescIsGpuMapAllowed__)(struct OsDescMemory *, struct OBJGPU *); + NV_STATUS (*__osdescUnmapFrom__)(struct OsDescMemory *, RS_RES_UNMAP_FROM_PARAMS *); + void (*__osdescControl_Epilogue__)(struct OsDescMemory *, CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); + NV_STATUS (*__osdescControlLookup__)(struct OsDescMemory *, struct RS_RES_CONTROL_PARAMS_INTERNAL *, const struct NVOC_EXPORTED_METHOD_DEF **); NV_STATUS (*__osdescControl__)(struct OsDescMemory *, CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); NV_STATUS (*__osdescUnmap__)(struct OsDescMemory *, CALL_CONTEXT *, RsCpuMapping *); NV_STATUS (*__osdescGetMemInterMapParams__)(struct OsDescMemory *, RMRES_MEM_INTER_MAP_PARAMS *); NV_STATUS (*__osdescGetMemoryMappingDescriptor__)(struct OsDescMemory *, MEMORY_DESCRIPTOR **); - NV_STATUS (*__osdescGetMapAddrSpace__)(struct OsDescMemory *, CALL_CONTEXT *, NvU32, NV_ADDRESS_SPACE *); - NvBool (*__osdescShareCallback__)(struct OsDescMemory *, struct RsClient *, struct RsResourceRef *, RS_SHARE_POLICY *); NV_STATUS (*__osdescControlFilter__)(struct OsDescMemory *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); - void (*__osdescAddAdditionalDependants__)(struct RsClient *, struct OsDescMemory *, RsResourceRef *); - NvU32 (*__osdescGetRefCount__)(struct OsDescMemory *); - NV_STATUS (*__osdescMapTo__)(struct OsDescMemory *, RS_RES_MAP_TO_PARAMS *); - NV_STATUS (*__osdescControl_Prologue__)(struct OsDescMemory *, CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); - NvBool (*__osdescIsGpuMapAllowed__)(struct OsDescMemory *, struct OBJGPU *); + NV_STATUS (*__osdescControlSerialization_Prologue__)(struct OsDescMemory *, CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); NV_STATUS (*__osdescIsReady__)(struct OsDescMemory *, NvBool); - NV_STATUS (*__osdescCheckCopyPermissions__)(struct OsDescMemory *, struct OBJGPU *, NvHandle); + NV_STATUS (*__osdescCheckCopyPermissions__)(struct OsDescMemory *, struct OBJGPU *, struct Device *); void (*__osdescPreDestruct__)(struct OsDescMemory *); NV_STATUS (*__osdescIsDuplicate__)(struct OsDescMemory *, NvHandle, NvBool *); - NV_STATUS (*__osdescUnmapFrom__)(struct OsDescMemory *, RS_RES_UNMAP_FROM_PARAMS *); - void (*__osdescControl_Epilogue__)(struct OsDescMemory *, CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); - NV_STATUS (*__osdescControlLookup__)(struct OsDescMemory *, struct RS_RES_CONTROL_PARAMS_INTERNAL *, const struct NVOC_EXPORTED_METHOD_DEF **); + void (*__osdescControlSerialization_Epilogue__)(struct OsDescMemory *, CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); NV_STATUS (*__osdescMap__)(struct OsDescMemory *, CALL_CONTEXT *, struct RS_CPU_MAP_PARAMS *, RsCpuMapping *); NvBool (*__osdescAccessCallback__)(struct OsDescMemory *, struct RsClient *, void *, RsAccessRight); }; @@ -108,25 +110,27 @@ #define osdescCanCopy(pOsDescMemory) osdescCanCopy_DISPATCH(pOsDescMemory) #define osdescCheckMemInterUnmap(pMemory, bSubdeviceHandleProvided) osdescCheckMemInterUnmap_DISPATCH(pMemory, bSubdeviceHandleProvided) +#define osdescShareCallback(pResource, pInvokingClient, pParentRef, pSharePolicy) osdescShareCallback_DISPATCH(pResource, pInvokingClient, pParentRef, pSharePolicy) +#define osdescMapTo(pResource, pParams) osdescMapTo_DISPATCH(pResource, pParams) +#define osdescGetMapAddrSpace(pMemory, pCallContext, mapFlags, pAddrSpace) osdescGetMapAddrSpace_DISPATCH(pMemory, pCallContext, mapFlags, pAddrSpace) +#define osdescGetRefCount(pResource) osdescGetRefCount_DISPATCH(pResource) +#define osdescAddAdditionalDependants(pClient, pResource, pReference) osdescAddAdditionalDependants_DISPATCH(pClient, pResource, pReference) +#define osdescControl_Prologue(pResource, pCallContext, pParams) osdescControl_Prologue_DISPATCH(pResource, pCallContext, pParams) +#define osdescIsGpuMapAllowed(pMemory, pGpu) osdescIsGpuMapAllowed_DISPATCH(pMemory, pGpu) +#define osdescUnmapFrom(pResource, pParams) osdescUnmapFrom_DISPATCH(pResource, pParams) +#define osdescControl_Epilogue(pResource, pCallContext, pParams) osdescControl_Epilogue_DISPATCH(pResource, pCallContext, pParams) +#define osdescControlLookup(pResource, pParams, ppEntry) osdescControlLookup_DISPATCH(pResource, pParams, ppEntry) #define osdescControl(pMemory, pCallContext, pParams) osdescControl_DISPATCH(pMemory, pCallContext, pParams) #define osdescUnmap(pMemory, pCallContext, pCpuMapping) osdescUnmap_DISPATCH(pMemory, pCallContext, pCpuMapping) #define osdescGetMemInterMapParams(pMemory, pParams) osdescGetMemInterMapParams_DISPATCH(pMemory, pParams) #define osdescGetMemoryMappingDescriptor(pMemory, ppMemDesc) osdescGetMemoryMappingDescriptor_DISPATCH(pMemory, ppMemDesc) -#define osdescGetMapAddrSpace(pMemory, pCallContext, mapFlags, pAddrSpace) osdescGetMapAddrSpace_DISPATCH(pMemory, pCallContext, mapFlags, pAddrSpace) -#define osdescShareCallback(pResource, pInvokingClient, pParentRef, pSharePolicy) osdescShareCallback_DISPATCH(pResource, pInvokingClient, pParentRef, pSharePolicy) #define osdescControlFilter(pResource, pCallContext, pParams) osdescControlFilter_DISPATCH(pResource, pCallContext, pParams) -#define osdescAddAdditionalDependants(pClient, pResource, pReference) osdescAddAdditionalDependants_DISPATCH(pClient, pResource, pReference) -#define osdescGetRefCount(pResource) osdescGetRefCount_DISPATCH(pResource) -#define osdescMapTo(pResource, pParams) osdescMapTo_DISPATCH(pResource, pParams) -#define osdescControl_Prologue(pResource, pCallContext, pParams) osdescControl_Prologue_DISPATCH(pResource, pCallContext, pParams) -#define osdescIsGpuMapAllowed(pMemory, pGpu) osdescIsGpuMapAllowed_DISPATCH(pMemory, pGpu) +#define osdescControlSerialization_Prologue(pResource, pCallContext, pParams) osdescControlSerialization_Prologue_DISPATCH(pResource, pCallContext, pParams) #define osdescIsReady(pMemory, bCopyConstructorContext) osdescIsReady_DISPATCH(pMemory, bCopyConstructorContext) -#define osdescCheckCopyPermissions(pMemory, pDstGpu, hDstClientNvBool) osdescCheckCopyPermissions_DISPATCH(pMemory, pDstGpu, hDstClientNvBool) +#define osdescCheckCopyPermissions(pMemory, pDstGpu, pDstDevice) osdescCheckCopyPermissions_DISPATCH(pMemory, pDstGpu, pDstDevice) #define osdescPreDestruct(pResource) osdescPreDestruct_DISPATCH(pResource) #define osdescIsDuplicate(pMemory, hMemory, pDuplicate) osdescIsDuplicate_DISPATCH(pMemory, hMemory, pDuplicate) -#define osdescUnmapFrom(pResource, pParams) osdescUnmapFrom_DISPATCH(pResource, pParams) -#define osdescControl_Epilogue(pResource, pCallContext, pParams) osdescControl_Epilogue_DISPATCH(pResource, pCallContext, pParams) -#define osdescControlLookup(pResource, pParams, ppEntry) osdescControlLookup_DISPATCH(pResource, pParams, ppEntry) +#define osdescControlSerialization_Epilogue(pResource, pCallContext, pParams) osdescControlSerialization_Epilogue_DISPATCH(pResource, pCallContext, pParams) #define osdescMap(pMemory, pCallContext, pParams, pCpuMapping) osdescMap_DISPATCH(pMemory, pCallContext, pParams, pCpuMapping) #define osdescAccessCallback(pResource, pInvokingClient, pAllocParams, accessRight) osdescAccessCallback_DISPATCH(pResource, pInvokingClient, pAllocParams, accessRight) NvBool osdescCanCopy_IMPL(struct OsDescMemory *pOsDescMemory); @@ -139,60 +143,76 @@ return pMemory->__osdescCheckMemInterUnmap__(pMemory, bSubdeviceHandleProvided); } -static inline NV_STATUS osdescControl_DISPATCH(struct OsDescMemory *pMemory, CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { - return pMemory->__osdescControl__(pMemory, pCallContext, pParams); +static inline NvBool osdescShareCallback_DISPATCH(struct OsDescMemory *pResource, struct RsClient *pInvokingClient, struct RsResourceRef *pParentRef, RS_SHARE_POLICY *pSharePolicy) { + return pResource->__osdescShareCallback__(pResource, pInvokingClient, pParentRef, pSharePolicy); } -static inline NV_STATUS osdescUnmap_DISPATCH(struct OsDescMemory *pMemory, CALL_CONTEXT *pCallContext, RsCpuMapping *pCpuMapping) { - return pMemory->__osdescUnmap__(pMemory, pCallContext, pCpuMapping); +static inline NV_STATUS osdescMapTo_DISPATCH(struct OsDescMemory *pResource, RS_RES_MAP_TO_PARAMS *pParams) { + return pResource->__osdescMapTo__(pResource, pParams); } -static inline NV_STATUS osdescGetMemInterMapParams_DISPATCH(struct OsDescMemory *pMemory, RMRES_MEM_INTER_MAP_PARAMS *pParams) { - return pMemory->__osdescGetMemInterMapParams__(pMemory, pParams); +static inline NV_STATUS osdescGetMapAddrSpace_DISPATCH(struct OsDescMemory *pMemory, CALL_CONTEXT *pCallContext, NvU32 mapFlags, NV_ADDRESS_SPACE *pAddrSpace) { + return pMemory->__osdescGetMapAddrSpace__(pMemory, pCallContext, mapFlags, pAddrSpace); } -static inline NV_STATUS osdescGetMemoryMappingDescriptor_DISPATCH(struct OsDescMemory *pMemory, MEMORY_DESCRIPTOR **ppMemDesc) { - return pMemory->__osdescGetMemoryMappingDescriptor__(pMemory, ppMemDesc); +static inline NvU32 osdescGetRefCount_DISPATCH(struct OsDescMemory *pResource) { + return pResource->__osdescGetRefCount__(pResource); } -static inline NV_STATUS osdescGetMapAddrSpace_DISPATCH(struct OsDescMemory *pMemory, CALL_CONTEXT *pCallContext, NvU32 mapFlags, NV_ADDRESS_SPACE *pAddrSpace) { - return pMemory->__osdescGetMapAddrSpace__(pMemory, pCallContext, mapFlags, pAddrSpace); +static inline void osdescAddAdditionalDependants_DISPATCH(struct RsClient *pClient, struct OsDescMemory *pResource, RsResourceRef *pReference) { + pResource->__osdescAddAdditionalDependants__(pClient, pResource, pReference); } -static inline NvBool osdescShareCallback_DISPATCH(struct OsDescMemory *pResource, struct RsClient *pInvokingClient, struct RsResourceRef *pParentRef, RS_SHARE_POLICY *pSharePolicy) { - return pResource->__osdescShareCallback__(pResource, pInvokingClient, pParentRef, pSharePolicy); +static inline NV_STATUS osdescControl_Prologue_DISPATCH(struct OsDescMemory *pResource, CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return pResource->__osdescControl_Prologue__(pResource, pCallContext, pParams); } -static inline NV_STATUS osdescControlFilter_DISPATCH(struct OsDescMemory *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { - return pResource->__osdescControlFilter__(pResource, pCallContext, pParams); +static inline NvBool osdescIsGpuMapAllowed_DISPATCH(struct OsDescMemory *pMemory, struct OBJGPU *pGpu) { + return pMemory->__osdescIsGpuMapAllowed__(pMemory, pGpu); } -static inline void osdescAddAdditionalDependants_DISPATCH(struct RsClient *pClient, struct OsDescMemory *pResource, RsResourceRef *pReference) { - pResource->__osdescAddAdditionalDependants__(pClient, pResource, pReference); +static inline NV_STATUS osdescUnmapFrom_DISPATCH(struct OsDescMemory *pResource, RS_RES_UNMAP_FROM_PARAMS *pParams) { + return pResource->__osdescUnmapFrom__(pResource, pParams); } -static inline NvU32 osdescGetRefCount_DISPATCH(struct OsDescMemory *pResource) { - return pResource->__osdescGetRefCount__(pResource); +static inline void osdescControl_Epilogue_DISPATCH(struct OsDescMemory *pResource, CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + pResource->__osdescControl_Epilogue__(pResource, pCallContext, pParams); } -static inline NV_STATUS osdescMapTo_DISPATCH(struct OsDescMemory *pResource, RS_RES_MAP_TO_PARAMS *pParams) { - return pResource->__osdescMapTo__(pResource, pParams); +static inline NV_STATUS osdescControlLookup_DISPATCH(struct OsDescMemory *pResource, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams, const struct NVOC_EXPORTED_METHOD_DEF **ppEntry) { + return pResource->__osdescControlLookup__(pResource, pParams, ppEntry); } -static inline NV_STATUS osdescControl_Prologue_DISPATCH(struct OsDescMemory *pResource, CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { - return pResource->__osdescControl_Prologue__(pResource, pCallContext, pParams); +static inline NV_STATUS osdescControl_DISPATCH(struct OsDescMemory *pMemory, CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return pMemory->__osdescControl__(pMemory, pCallContext, pParams); } -static inline NvBool osdescIsGpuMapAllowed_DISPATCH(struct OsDescMemory *pMemory, struct OBJGPU *pGpu) { - return pMemory->__osdescIsGpuMapAllowed__(pMemory, pGpu); +static inline NV_STATUS osdescUnmap_DISPATCH(struct OsDescMemory *pMemory, CALL_CONTEXT *pCallContext, RsCpuMapping *pCpuMapping) { + return pMemory->__osdescUnmap__(pMemory, pCallContext, pCpuMapping); +} + +static inline NV_STATUS osdescGetMemInterMapParams_DISPATCH(struct OsDescMemory *pMemory, RMRES_MEM_INTER_MAP_PARAMS *pParams) { + return pMemory->__osdescGetMemInterMapParams__(pMemory, pParams); +} + +static inline NV_STATUS osdescGetMemoryMappingDescriptor_DISPATCH(struct OsDescMemory *pMemory, MEMORY_DESCRIPTOR **ppMemDesc) { + return pMemory->__osdescGetMemoryMappingDescriptor__(pMemory, ppMemDesc); +} + +static inline NV_STATUS osdescControlFilter_DISPATCH(struct OsDescMemory *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return pResource->__osdescControlFilter__(pResource, pCallContext, pParams); +} + +static inline NV_STATUS osdescControlSerialization_Prologue_DISPATCH(struct OsDescMemory *pResource, CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return pResource->__osdescControlSerialization_Prologue__(pResource, pCallContext, pParams); } static inline NV_STATUS osdescIsReady_DISPATCH(struct OsDescMemory *pMemory, NvBool bCopyConstructorContext) { return pMemory->__osdescIsReady__(pMemory, bCopyConstructorContext); } -static inline NV_STATUS osdescCheckCopyPermissions_DISPATCH(struct OsDescMemory *pMemory, struct OBJGPU *pDstGpu, NvHandle hDstClientNvBool) { - return pMemory->__osdescCheckCopyPermissions__(pMemory, pDstGpu, hDstClientNvBool); +static inline NV_STATUS osdescCheckCopyPermissions_DISPATCH(struct OsDescMemory *pMemory, struct OBJGPU *pDstGpu, struct Device *pDstDevice) { + return pMemory->__osdescCheckCopyPermissions__(pMemory, pDstGpu, pDstDevice); } static inline void osdescPreDestruct_DISPATCH(struct OsDescMemory *pResource) { @@ -203,16 +223,8 @@ return pMemory->__osdescIsDuplicate__(pMemory, hMemory, pDuplicate); } -static inline NV_STATUS osdescUnmapFrom_DISPATCH(struct OsDescMemory *pResource, RS_RES_UNMAP_FROM_PARAMS *pParams) { - return pResource->__osdescUnmapFrom__(pResource, pParams); -} - -static inline void osdescControl_Epilogue_DISPATCH(struct OsDescMemory *pResource, CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { - pResource->__osdescControl_Epilogue__(pResource, pCallContext, pParams); -} - -static inline NV_STATUS osdescControlLookup_DISPATCH(struct OsDescMemory *pResource, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams, const struct NVOC_EXPORTED_METHOD_DEF **ppEntry) { - return pResource->__osdescControlLookup__(pResource, pParams, ppEntry); +static inline void osdescControlSerialization_Epilogue_DISPATCH(struct OsDescMemory *pResource, CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + pResource->__osdescControlSerialization_Epilogue__(pResource, pCallContext, pParams); } static inline NV_STATUS osdescMap_DISPATCH(struct OsDescMemory *pMemory, CALL_CONTEXT *pCallContext, struct RS_CPU_MAP_PARAMS *pParams, RsCpuMapping *pCpuMapping) { diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/generated/g_os_nvoc.c nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_os_nvoc.c --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/generated/g_os_nvoc.c 2023-10-25 20:27:15.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_os_nvoc.c 2024-03-05 22:18:37.000000000 +0000 @@ -109,13 +109,16 @@ Object *pParentObj; OBJOS *pThis; - pThis = portMemAllocNonPaged(sizeof(OBJOS)); - if (pThis == NULL) return NV_ERR_NO_MEMORY; + status = __nvoc_handleObjCreateMemAlloc(createFlags, sizeof(OBJOS), (void**)&pThis, (void**)ppThis); + if (status != NV_OK) + return status; portMemSet(pThis, 0, sizeof(OBJOS)); __nvoc_initRtti(staticCast(pThis, Dynamic), &__nvoc_class_def_OBJOS); + pThis->__nvoc_base_Object.createFlags = createFlags; + if (pParent != NULL && !(createFlags & NVOC_OBJ_CREATE_FLAGS_PARENT_HALSPEC_ONLY)) { pParentObj = dynamicCast(pParent, Object); @@ -131,11 +134,17 @@ if (status != NV_OK) goto __nvoc_objCreate_OBJOS_cleanup; *ppThis = pThis; + return NV_OK; __nvoc_objCreate_OBJOS_cleanup: // do not call destructors here since the constructor already called them - portMemFree(pThis); + if (createFlags & NVOC_OBJ_CREATE_FLAGS_IN_PLACE_CONSTRUCT) + portMemSet(pThis, 0, sizeof(OBJOS)); + else + portMemFree(pThis); + + // coverity[leaked_storage:FALSE] return status; } diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/generated/g_os_nvoc.h nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_os_nvoc.h --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/generated/g_os_nvoc.h 2023-10-25 20:27:16.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_os_nvoc.h 2024-03-05 22:18:37.000000000 +0000 @@ -7,7 +7,7 @@ #endif /* - * SPDX-FileCopyrightText: Copyright (c) 1993-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 1993-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -69,19 +69,19 @@ -// -// The OS module should NOT depend on RM modules. The only exception is +// +// The OS module should NOT depend on RM modules. The only exception is // core/core.h. -// -// DO NOT ADD INCLUDES TO RM MODULE HEADERS FROM THIS FILE. OS module should be -// a leaf module. Dependencies on RM headers in this files results in circular +// +// DO NOT ADD INCLUDES TO RM MODULE HEADERS FROM THIS FILE. OS module should be +// a leaf module. Dependencies on RM headers in this files results in circular // dependencies as most modules depend on the OS module. -// -// Ideally, all types used by the OS module's interface are from the SDK, -// resman/interface or self-contained within the OS module header. For now, +// +// Ideally, all types used by the OS module's interface are from the SDK, +// resman/interface or self-contained within the OS module header. For now, // since the OS module depends on a few RM internal types we forward declare to -// avoid the need to pull in headers from across RM. -// +// avoid the need to pull in headers from across RM. +// typedef struct SYS_STATIC_CONFIG SYS_STATIC_CONFIG; typedef struct MEMORY_DESCRIPTOR MEMORY_DESCRIPTOR; typedef struct IOVAMAPPING *PIOVAMAPPING; @@ -95,10 +95,10 @@ // // Forward declare OS_GPU_INFO type -// +// // TODO - We shouldn't need a special definition per-OS. OS implementations // should use a consistent type -// +// typedef struct nv_state_t OS_GPU_INFO; /* ------------------------ OS Interface ------------------------------------ */ @@ -198,7 +198,7 @@ #define OS_BUG_CHECK_BUGCODE_ECC_DBE (3) #define OS_BUG_CHECK_BUGCODE_NVLINK_TL_ERR (4) #define OS_BUG_CHECK_BUGCODE_PAGED_SEGMENT (5) -#define OS_BUG_CHECK_BUGCODE_BDOD_ON_ASSERT (6) +#define OS_BUG_CHECK_BUGCODE_BSOD_ON_ASSERT (6) #define OS_BUG_CHECK_BUGCODE_DISPLAY_UNDERFLOW (7) #define OS_BUG_CHECK_BUGCODE_LAST OS_BUG_CHECK_BUGCODE_DISPLAY_UNDERFLOW @@ -216,7 +216,7 @@ // Flags needed by OSAllocPagesNode #define OS_ALLOC_PAGES_NODE_NONE 0x0 -#define OS_ALLOC_PAGES_NODE_SKIP_RECLAIM 0x1 +#define OS_ALLOC_PAGES_NODE_SKIP_RECLAIM 0x1 // // Structures for osPackageRegistry and osUnpackageRegistry @@ -276,7 +276,6 @@ typedef NV_STATUS OSUnlockMem(MEMORY_DESCRIPTOR *); typedef NV_STATUS NV_FORCERESULTCHECK OSMapGPU(OBJGPU *, RS_PRIV_LEVEL, NvU64, NvU64, NvU32, NvP64 *, NvP64 *); typedef void OSUnmapGPU(OS_GPU_INFO *, RS_PRIV_LEVEL, NvP64, NvU64, NvP64); -typedef NV_STATUS NV_FORCERESULTCHECK OSDeviceClassToDeviceName(NvU32, NvU8 *); typedef NV_STATUS NV_FORCERESULTCHECK OSNotifyEvent(OBJGPU *, PEVENTNOTIFICATION, NvU32, NvU32, NV_STATUS); typedef NV_STATUS OSReadRegistryString(OBJGPU *, const char *, NvU8 *, NvU32 *); typedef NV_STATUS OSWriteRegistryBinary(OBJGPU *, const char *, NvU8 *, NvU32); @@ -295,11 +294,12 @@ typedef NV_STATUS OSNumaMemblockSize(NvU64 *); typedef NvBool OSNumaOnliningEnabled(OS_GPU_INFO *); typedef NV_STATUS OSAllocPagesNode(NvS32, NvLength, NvU32, NvU64 *); -typedef NV_STATUS OSAllocAcquirePage(NvU64); -typedef NV_STATUS OSAllocReleasePage(NvU64); +typedef void OSAllocAcquirePage(NvU64, NvU32); +typedef void OSAllocReleasePage(NvU64, NvU32); typedef NvU32 OSGetPageRefcount(NvU64); typedef NvU32 OSCountTailPages(NvU64); -typedef NvU32 OSGetPageSize(void); +typedef NvU64 OSGetPageSize(void); +typedef NvU8 OSGetPageShift(void); // We use osAcquireRmSema to catch "unported" sema code to new lock model @@ -390,42 +390,37 @@ typedef NV_STATUS OSQueueSystemWorkItem(OSSystemWorkItemFunction, void *); // MXM ACPI calls -typedef NV_STATUS OSCallACPI_MXMX(OBJGPU *, NvU32, NvU8 *); -typedef NV_STATUS OSCallACPI_DDC(OBJGPU *, NvU32, NvU8*,NvU32*, NvBool); -typedef NV_STATUS OSCallACPI_BCL(OBJGPU *, NvU32, NvU32 *, NvU16 *); +NV_STATUS osCallACPI_MXMX(OBJGPU *, NvU32, NvU8 *); +NV_STATUS osCallACPI_DDC(OBJGPU *, NvU32, NvU8*,NvU32*, NvBool); +NV_STATUS osCallACPI_BCL(OBJGPU *, NvU32, NvU32 *, NvU16 *); // Display MUX ACPI calls -typedef NV_STATUS OSCallACPI_MXDS(OBJGPU *, NvU32, NvU32 *); -typedef NV_STATUS OSCallACPI_MXDM(OBJGPU *, NvU32, NvU32 *); -typedef NV_STATUS OSCallACPI_MXID(OBJGPU *, NvU32, NvU32 *); -typedef NV_STATUS OSCallACPI_LRST(OBJGPU *, NvU32, NvU32 *); +NV_STATUS osCallACPI_MXDS(OBJGPU *, NvU32, NvU32 *); +NV_STATUS osCallACPI_MXDM(OBJGPU *, NvU32, NvU32 *); +NV_STATUS osCallACPI_MXID(OBJGPU *, NvU32, NvU32 *); +NV_STATUS osCallACPI_LRST(OBJGPU *, NvU32, NvU32 *); // Hybrid GPU ACPI calls -typedef NV_STATUS OSCallACPI_NVHG_GPUON(OBJGPU *, NvU32 *); -typedef NV_STATUS OSCallACPI_NVHG_GPUOFF(OBJGPU *, NvU32 *); +NV_STATUS osCallACPI_NVHG_GPUON(OBJGPU *, NvU32 *); +NV_STATUS osCallACPI_NVHG_GPUOFF(OBJGPU *, NvU32 *); typedef NV_STATUS OSCallACPI_NVHG_GPUSTA(OBJGPU *, NvU32 *); typedef NV_STATUS OSCallACPI_NVHG_MXDS(OBJGPU *, NvU32, NvU32 *); typedef NV_STATUS OSCallACPI_NVHG_MXMX(OBJGPU *, NvU32, NvU32 *); typedef NV_STATUS OSCallACPI_NVHG_DOS(OBJGPU *, NvU32, NvU32 *); -typedef NV_STATUS OSCallACPI_NVHG_ROM(OBJGPU *, NvU32 *, NvU32 *); +NV_STATUS osCallACPI_NVHG_ROM(OBJGPU *, NvU32 *, NvU32 *); typedef NV_STATUS OSCallACPI_NVHG_DCS(OBJGPU *, NvU32, NvU32 *); -typedef NV_STATUS OSCallACPI_DOD(OBJGPU *, NvU32 *, NvU32 *); +NV_STATUS osCallACPI_DOD(OBJGPU *, NvU32 *, NvU32 *); // Tegra ACPI calls -typedef NV_STATUS OSCallACPI_SUB(OBJGPU *, NvU8 *, NvU32 *); -typedef NV_STATUS OSCallACPI_ON(OBJGPU *, NvU32); -typedef NV_STATUS OSCallACPI_OFF(OBJGPU *, NvU32); - -// Notebook Power Balancing ACPI calls -typedef NV_STATUS OSCallACPI_NBPS(OBJGPU *, NvU8 *, NvU32 *); -typedef NV_STATUS OSCallACPI_NBSL(OBJGPU *, NvU32); +NV_STATUS osCallACPI_ON(OBJGPU *, NvU32); +NV_STATUS osCallACPI_OFF(OBJGPU *, NvU32); // Optimus WMI ACPI calls -typedef NV_STATUS OSCallACPI_OPTM_GPUON(OBJGPU *); +NV_STATUS osCallACPI_OPTM_GPUON(OBJGPU *); // Generic ACPI _DSM call -typedef NV_STATUS OSCallACPI_DSM(OBJGPU *pGpu, ACPI_DSM_FUNCTION acpiDSMFunction, - NvU32 NVHGDSMSubfunction, NvU32 *pInOut, NvU16 *size); +NV_STATUS osCallACPI_DSM(OBJGPU *pGpu, ACPI_DSM_FUNCTION acpiDSMFunction, + NvU32 NVHGDSMSubfunction, NvU32 *pInOut, NvU16 *size); // UEFI variable calls typedef NV_STATUS OSGetUefiVariable(OBJGPU *, char *, LPGUID, NvU8 *, NvU32 *, NvU32 *); @@ -631,32 +626,14 @@ OSSimEscapeReadBuffer *osSimEscapeReadBuffer; OSRmInitRm *osRmInitRm; OSGetSimulationMode *osGetSimulationMode; - OSCallACPI_MXMX *osCallACPI_MXMX; - OSCallACPI_DDC *osCallACPI_DDC; - OSCallACPI_BCL *osCallACPI_BCL; - OSCallACPI_MXDS *osCallACPI_MXDS; - OSCallACPI_MXDM *osCallACPI_MXDM; - OSCallACPI_MXID *osCallACPI_MXID; - OSCallACPI_LRST *osCallACPI_LRST; - OSCallACPI_NVHG_GPUON *osCallACPI_NVHG_GPUON; - OSCallACPI_NVHG_GPUOFF *osCallACPI_NVHG_GPUOFF; OSCallACPI_NVHG_GPUSTA *osCallACPI_NVHG_GPUSTA; OSCallACPI_NVHG_MXDS *osCallACPI_NVHG_MXDS; OSCallACPI_NVHG_MXMX *osCallACPI_NVHG_MXMX; OSCallACPI_NVHG_DOS *osCallACPI_NVHG_DOS; - OSCallACPI_NVHG_ROM *osCallACPI_NVHG_ROM; OSCallACPI_NVHG_DCS *osCallACPI_NVHG_DCS; - OSCallACPI_DOD *osCallACPI_DOD; - OSCallACPI_SUB *osCallACPI_SUB; - OSCallACPI_ON *osCallACPI_ON; - OSCallACPI_OFF *osCallACPI_OFF; - OSCallACPI_DSM *osCallACPI_DSM; OSGetUefiVariable *osGetUefiVariable; OSCheckCallback *osCheckCallback; OSRCCallback *osRCCallback; - OSCallACPI_NBPS *osCallACPI_NBPS; - OSCallACPI_NBSL *osCallACPI_NBSL; - OSCallACPI_OPTM_GPUON *osCallACPI_OPTM_GPUON; OSSetupVBlank *osSetupVBlank; OSPexRecoveryCallback *osPexRecoveryCallback; OSInternalReserveAllocCallback *osInternalReserveAllocCallback; @@ -743,6 +720,14 @@ NV_STATUS osTegraSocPmPowergate(OS_GPU_INFO *pOsGpuInfo); NV_STATUS osTegraSocPmUnpowergate(OS_GPU_INFO *pOsGpuInfo); NV_STATUS osTegraSocDeviceReset(OS_GPU_INFO *pOsGpuInfo); +NV_STATUS osTegraSocBpmpSendMrq(OS_GPU_INFO *pOsGpuInfo, + NvU32 mrq, + const void *pRequestData, + NvU32 requestDataSize, + void *pResponseData, + NvU32 responseDataSize, + NvS32 *pRet, + NvS32 *pApiRet); NV_STATUS osTegraSocGetImpImportData(TEGRA_IMP_IMPORT_DATA *pTegraImpImportData); NV_STATUS osTegraSocEnableDisableRfl(OS_GPU_INFO *pOsGpuInfo, NvBool bEnable); NV_STATUS osTegraAllocateDisplayBandwidth(OS_GPU_INFO *pOsGpuInfo, @@ -821,6 +806,10 @@ NV_STATUS osGetFbNumaInfo(OBJGPU *pGpu, NvU64 *pAddrPhys, NvS32 *pNodeId); +NV_STATUS osGetEgmInfo(OBJGPU *pGpu, + NvU64 *pPhysAddr, + NvU64 *pSize, + NvS32 *pNodeId); NV_STATUS osGetForcedNVLinkConnection(OBJGPU *pGpu, NvU32 maxLinks, NvU32 *pLinkConnection); @@ -840,8 +829,7 @@ NV_STATUS osVgpuInjectInterrupt(void *pArg1); NV_STATUS osVgpuRegisterMdev(OS_GPU_INFO *pArg1); NV_STATUS osIsVgpuVfioPresent(void); -NV_STATUS osVgpuAllocVmbusEventDpc(void **ppArg1); -void osVgpuScheduleVmbusEventDpc(void *pArg1, void *pArg2); +NV_STATUS osIsVfioPciCorePresent(void); NV_STATUS rm_is_vgpu_supported_device(OS_GPU_INFO *pNv, NvU32 pmc_boot_1); NV_STATUS osLockPageableDataSection(RM_PAGEABLE_SECTION *pSection); NV_STATUS osUnlockPageableDataSection(RM_PAGEABLE_SECTION *pSection); @@ -892,6 +880,10 @@ NvU64 maxSectionSize); void osReleaseCpuAddressSpaceUpperBound(void *pSectionHandle); +void* osGetPidInfo(void); +void osPutPidInfo(void *pOsPidInfo); +NV_STATUS osFindNsPid(void *pOsPidInfo, NvU32 *pNsPid); + // OS Tegra IPC functions NV_STATUS osTegraDceRegisterIpcClient(NvU32 interfaceType, void *usrCtx, NvU32 *clientId); @@ -904,7 +896,7 @@ // CLKWHICH, avoids upwards dependency from OS interface on higher level // RM modules // -typedef NvU32 OS_CLKWHICH; +typedef NvU32 OS_CLKWHICH; NV_STATUS osTegraSocEnableClk(OS_GPU_INFO *pOsGpuInfo, OS_CLKWHICH whichClkRM); NV_STATUS osTegraSocDisableClk(OS_GPU_INFO *pOsGpuInfo, OS_CLKWHICH whichClkRM); @@ -1014,6 +1006,9 @@ NV_STATUS osInitGetAcpiTable(void); +// Read NvGlobal regkey +NV_STATUS osGetNvGlobalRegistryDword(OBJGPU *, const char *pRegParmStr, NvU32 *pData); + NV_STATUS osGetIbmnpuGenregInfo(OS_GPU_INFO *pArg1, NvU64 *pArg2, NvU64 *pArg3); @@ -1109,6 +1104,20 @@ NvU32 osTegraSocFuseRegRead(NvU32 addr); +typedef void (*osTegraTsecCbFunc)(void*, void*); + +NvU32 osTegraSocTsecSendCmd(void* cmd, osTegraTsecCbFunc cbFunc, void* cbContext); + +NvU32 osTegraSocTsecEventRegister(osTegraTsecCbFunc cbFunc, void* cbContext, NvBool isInitEvent); + +NvU32 osTegraSocTsecEventUnRegister(NvBool isInitEvent); + +void* osTegraSocTsecAllocMemDesc(NvU32 numBytes, NvU32 *flcnAddr); + +void osTegraSocTsecFreeMemDesc(void *memDesc); + +NV_STATUS osTegraSocHspSemaphoreAcquire(NvU32 ownerId, NvBool bAcquire, NvU64 timeout); + NV_STATUS osTegraSocDpUphyPllInit(OS_GPU_INFO *pArg1, NvU32, NvU32); NV_STATUS osTegraSocDpUphyPllDeInit(OS_GPU_INFO *pArg1); @@ -1122,6 +1131,8 @@ NV_STATUS osSetTegraBrightnessLevel(OS_GPU_INFO *pArg1, NvU32 arg2); +NvBool osTegraSocGetHdcpEnabled(OS_GPU_INFO *pOsGpuInfo); + NvBool osIsVga(OS_GPU_INFO *pArg1, NvBool bIsGpuPrimaryDevice); @@ -1242,11 +1253,15 @@ #define OS_PCIE_CAP_MASK_REQ_ATOMICS_64 NVBIT(1) #define OS_PCIE_CAP_MASK_REQ_ATOMICS_128 NVBIT(2) +void osGetNumaMemoryUsage(NvS32 numaId, NvU64 *free_memory_bytes, NvU64 *total_memory_bytes); + NV_STATUS osNumaAddGpuMemory(OS_GPU_INFO *pOsGpuInfo, NvU64 offset, NvU64 size, NvU32 *pNumaNodeId); void osNumaRemoveGpuMemory(OS_GPU_INFO *pOsGpuInfo, NvU64 offset, NvU64 size, NvU32 numaNodeId); +NV_STATUS osOfflinePageAtAddress(NvU64 address); + // Os 1Hz timer callback functions NV_STATUS osInit1HzCallbacks(OBJTMR *pTmr); NV_STATUS osDestroy1HzCallbacks(OBJTMR *pTmr); @@ -1291,7 +1306,6 @@ OSObjectEventNotification osObjectEventNotification; OSNotifyEvent osNotifyEvent; OSFlushCpuWriteCombineBuffer osFlushCpuWriteCombineBuffer; -OSDeviceClassToDeviceName osDeviceClassToDeviceName; OSDelay osDelay; OSSpinLoop osSpinLoop; OSDelayUs osDelayUs; @@ -1311,6 +1325,7 @@ OSFreePagesInternal osFreePagesInternal; OSGetPageSize osGetPageSize; +OSGetPageShift osGetPageShift; OSNumaMemblockSize osNumaMemblockSize; OSNumaOnliningEnabled osNumaOnliningEnabled; OSAllocPagesNode osAllocPagesNode; @@ -1467,16 +1482,16 @@ // Notify callback action #define NV_OS_WRITE_THEN_AWAKEN 0x00000001 -// -// Include per-OS definitions -// -// #ifdef out for nvoctrans, this hides include to system headers which +// +// Include per-OS definitions +// +// #ifdef out for nvoctrans, this hides include to system headers which // breaks the tool. -// -// TODO - we should delete the per-OS os_custom.h files exposed to -// OS-agnostic code. Cross-OS code shouldn't pull in per-OS headers or -// per-OS definitions. -// +// +// TODO - we should delete the per-OS os_custom.h files exposed to +// OS-agnostic code. Cross-OS code shouldn't pull in per-OS headers or +// per-OS definitions. +// #include "os_custom.h" #define NV_SEMA_RELEASE_SUCCEED 0 // lock released, no waiting thread to notify diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/generated/g_p2p_api_nvoc.c nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_p2p_api_nvoc.c --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/generated/g_p2p_api_nvoc.c 2023-10-25 20:27:16.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_p2p_api_nvoc.c 2024-03-05 22:18:37.000000000 +0000 @@ -116,8 +116,12 @@ resAddAdditionalDependants(pClient, (struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_P2PApi_RsResource.offset), pReference); } -static NV_STATUS __nvoc_thunk_RsResource_p2papiUnmap(struct P2PApi *pResource, struct CALL_CONTEXT *pCallContext, RsCpuMapping *pCpuMapping) { - return resUnmap((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_P2PApi_RsResource.offset), pCallContext, pCpuMapping); +static NV_STATUS __nvoc_thunk_RsResource_p2papiUnmapFrom(struct P2PApi *pResource, RS_RES_UNMAP_FROM_PARAMS *pParams) { + return resUnmapFrom((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_P2PApi_RsResource.offset), pParams); +} + +static NV_STATUS __nvoc_thunk_RmResource_p2papiControlSerialization_Prologue(struct P2PApi *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return rmresControlSerialization_Prologue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_P2PApi_RmResource.offset), pCallContext, pParams); } static NV_STATUS __nvoc_thunk_RmResource_p2papiControl_Prologue(struct P2PApi *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { @@ -128,22 +132,26 @@ return resCanCopy((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_P2PApi_RsResource.offset)); } -static NV_STATUS __nvoc_thunk_RsResource_p2papiMapTo(struct P2PApi *pResource, RS_RES_MAP_TO_PARAMS *pParams) { - return resMapTo((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_P2PApi_RsResource.offset), pParams); +static NV_STATUS __nvoc_thunk_RsResource_p2papiUnmap(struct P2PApi *pResource, struct CALL_CONTEXT *pCallContext, RsCpuMapping *pCpuMapping) { + return resUnmap((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_P2PApi_RsResource.offset), pCallContext, pCpuMapping); } static void __nvoc_thunk_RsResource_p2papiPreDestruct(struct P2PApi *pResource) { resPreDestruct((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_P2PApi_RsResource.offset)); } -static NV_STATUS __nvoc_thunk_RsResource_p2papiUnmapFrom(struct P2PApi *pResource, RS_RES_UNMAP_FROM_PARAMS *pParams) { - return resUnmapFrom((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_P2PApi_RsResource.offset), pParams); +static NV_STATUS __nvoc_thunk_RsResource_p2papiMapTo(struct P2PApi *pResource, RS_RES_MAP_TO_PARAMS *pParams) { + return resMapTo((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_P2PApi_RsResource.offset), pParams); } static NV_STATUS __nvoc_thunk_RsResource_p2papiIsDuplicate(struct P2PApi *pResource, NvHandle hMemory, NvBool *pDuplicate) { return resIsDuplicate((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_P2PApi_RsResource.offset), hMemory, pDuplicate); } +static void __nvoc_thunk_RmResource_p2papiControlSerialization_Epilogue(struct P2PApi *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + rmresControlSerialization_Epilogue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_P2PApi_RmResource.offset), pCallContext, pParams); +} + static void __nvoc_thunk_RmResource_p2papiControl_Epilogue(struct P2PApi *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { rmresControl_Epilogue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_P2PApi_RmResource.offset), pCallContext, pParams); } @@ -215,20 +223,24 @@ pThis->__p2papiAddAdditionalDependants__ = &__nvoc_thunk_RsResource_p2papiAddAdditionalDependants; - pThis->__p2papiUnmap__ = &__nvoc_thunk_RsResource_p2papiUnmap; + pThis->__p2papiUnmapFrom__ = &__nvoc_thunk_RsResource_p2papiUnmapFrom; + + pThis->__p2papiControlSerialization_Prologue__ = &__nvoc_thunk_RmResource_p2papiControlSerialization_Prologue; pThis->__p2papiControl_Prologue__ = &__nvoc_thunk_RmResource_p2papiControl_Prologue; pThis->__p2papiCanCopy__ = &__nvoc_thunk_RsResource_p2papiCanCopy; - pThis->__p2papiMapTo__ = &__nvoc_thunk_RsResource_p2papiMapTo; + pThis->__p2papiUnmap__ = &__nvoc_thunk_RsResource_p2papiUnmap; pThis->__p2papiPreDestruct__ = &__nvoc_thunk_RsResource_p2papiPreDestruct; - pThis->__p2papiUnmapFrom__ = &__nvoc_thunk_RsResource_p2papiUnmapFrom; + pThis->__p2papiMapTo__ = &__nvoc_thunk_RsResource_p2papiMapTo; pThis->__p2papiIsDuplicate__ = &__nvoc_thunk_RsResource_p2papiIsDuplicate; + pThis->__p2papiControlSerialization_Epilogue__ = &__nvoc_thunk_RmResource_p2papiControlSerialization_Epilogue; + pThis->__p2papiControl_Epilogue__ = &__nvoc_thunk_RmResource_p2papiControl_Epilogue; pThis->__p2papiControlLookup__ = &__nvoc_thunk_RsResource_p2papiControlLookup; @@ -258,13 +270,16 @@ Object *pParentObj; P2PApi *pThis; - pThis = portMemAllocNonPaged(sizeof(P2PApi)); - if (pThis == NULL) return NV_ERR_NO_MEMORY; + status = __nvoc_handleObjCreateMemAlloc(createFlags, sizeof(P2PApi), (void**)&pThis, (void**)ppThis); + if (status != NV_OK) + return status; portMemSet(pThis, 0, sizeof(P2PApi)); __nvoc_initRtti(staticCast(pThis, Dynamic), &__nvoc_class_def_P2PApi); + pThis->__nvoc_base_RmResource.__nvoc_base_RsResource.__nvoc_base_Object.createFlags = createFlags; + if (pParent != NULL && !(createFlags & NVOC_OBJ_CREATE_FLAGS_PARENT_HALSPEC_ONLY)) { pParentObj = dynamicCast(pParent, Object); @@ -280,11 +295,17 @@ if (status != NV_OK) goto __nvoc_objCreate_P2PApi_cleanup; *ppThis = pThis; + return NV_OK; __nvoc_objCreate_P2PApi_cleanup: // do not call destructors here since the constructor already called them - portMemFree(pThis); + if (createFlags & NVOC_OBJ_CREATE_FLAGS_IN_PLACE_CONSTRUCT) + portMemSet(pThis, 0, sizeof(P2PApi)); + else + portMemFree(pThis); + + // coverity[leaked_storage:FALSE] return status; } diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/generated/g_p2p_api_nvoc.h nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_p2p_api_nvoc.h --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/generated/g_p2p_api_nvoc.h 2023-10-25 20:27:16.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_p2p_api_nvoc.h 2024-03-05 22:18:38.000000000 +0000 @@ -31,6 +31,7 @@ #include "g_p2p_api_nvoc.h" + #ifndef _P2P_API_H_ #define _P2P_API_H_ @@ -51,6 +52,9 @@ #define NV_P2PAPI_ATTRIBUTES_LINK_TYPE 4:4 #define NV_P2PAPI_ATTRIBUTES_LINK_TYPE_GPA 0x0 #define NV_P2PAPI_ATTRIBUTES_LINK_TYPE_SPA 0x1 +#define NV_P2PAPI_ATTRIBUTES_REMOTE_EGM 5:5 +#define NV_P2PAPI_ATTRIBUTES_REMOTE_EGM_NO 0x0 +#define NV_P2PAPI_ATTRIBUTES_REMOTE_EGM_YES 0x1 #ifdef NVOC_P2P_API_H_PRIVATE_ACCESS_ALLOWED #define PRIVATE_FIELD(x) x @@ -73,13 +77,15 @@ NvU32 (*__p2papiGetRefCount__)(struct P2PApi *); NV_STATUS (*__p2papiControlFilter__)(struct P2PApi *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); void (*__p2papiAddAdditionalDependants__)(struct RsClient *, struct P2PApi *, RsResourceRef *); - NV_STATUS (*__p2papiUnmap__)(struct P2PApi *, struct CALL_CONTEXT *, RsCpuMapping *); + NV_STATUS (*__p2papiUnmapFrom__)(struct P2PApi *, RS_RES_UNMAP_FROM_PARAMS *); + NV_STATUS (*__p2papiControlSerialization_Prologue__)(struct P2PApi *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); NV_STATUS (*__p2papiControl_Prologue__)(struct P2PApi *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); NvBool (*__p2papiCanCopy__)(struct P2PApi *); - NV_STATUS (*__p2papiMapTo__)(struct P2PApi *, RS_RES_MAP_TO_PARAMS *); + NV_STATUS (*__p2papiUnmap__)(struct P2PApi *, struct CALL_CONTEXT *, RsCpuMapping *); void (*__p2papiPreDestruct__)(struct P2PApi *); - NV_STATUS (*__p2papiUnmapFrom__)(struct P2PApi *, RS_RES_UNMAP_FROM_PARAMS *); + NV_STATUS (*__p2papiMapTo__)(struct P2PApi *, RS_RES_MAP_TO_PARAMS *); NV_STATUS (*__p2papiIsDuplicate__)(struct P2PApi *, NvHandle, NvBool *); + void (*__p2papiControlSerialization_Epilogue__)(struct P2PApi *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); void (*__p2papiControl_Epilogue__)(struct P2PApi *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); NV_STATUS (*__p2papiControlLookup__)(struct P2PApi *, struct RS_RES_CONTROL_PARAMS_INTERNAL *, const struct NVOC_EXPORTED_METHOD_DEF **); NV_STATUS (*__p2papiMap__)(struct P2PApi *, struct CALL_CONTEXT *, RS_CPU_MAP_PARAMS *, RsCpuMapping *); @@ -90,6 +96,8 @@ NvU32 remoteGfid; NvU32 peerId1; NvU32 peerId2; + NvU32 egmPeerId1; + NvU32 egmPeerId2; NvU32 attributes; }; @@ -129,13 +137,15 @@ #define p2papiGetRefCount(pResource) p2papiGetRefCount_DISPATCH(pResource) #define p2papiControlFilter(pResource, pCallContext, pParams) p2papiControlFilter_DISPATCH(pResource, pCallContext, pParams) #define p2papiAddAdditionalDependants(pClient, pResource, pReference) p2papiAddAdditionalDependants_DISPATCH(pClient, pResource, pReference) -#define p2papiUnmap(pResource, pCallContext, pCpuMapping) p2papiUnmap_DISPATCH(pResource, pCallContext, pCpuMapping) +#define p2papiUnmapFrom(pResource, pParams) p2papiUnmapFrom_DISPATCH(pResource, pParams) +#define p2papiControlSerialization_Prologue(pResource, pCallContext, pParams) p2papiControlSerialization_Prologue_DISPATCH(pResource, pCallContext, pParams) #define p2papiControl_Prologue(pResource, pCallContext, pParams) p2papiControl_Prologue_DISPATCH(pResource, pCallContext, pParams) #define p2papiCanCopy(pResource) p2papiCanCopy_DISPATCH(pResource) -#define p2papiMapTo(pResource, pParams) p2papiMapTo_DISPATCH(pResource, pParams) +#define p2papiUnmap(pResource, pCallContext, pCpuMapping) p2papiUnmap_DISPATCH(pResource, pCallContext, pCpuMapping) #define p2papiPreDestruct(pResource) p2papiPreDestruct_DISPATCH(pResource) -#define p2papiUnmapFrom(pResource, pParams) p2papiUnmapFrom_DISPATCH(pResource, pParams) +#define p2papiMapTo(pResource, pParams) p2papiMapTo_DISPATCH(pResource, pParams) #define p2papiIsDuplicate(pResource, hMemory, pDuplicate) p2papiIsDuplicate_DISPATCH(pResource, hMemory, pDuplicate) +#define p2papiControlSerialization_Epilogue(pResource, pCallContext, pParams) p2papiControlSerialization_Epilogue_DISPATCH(pResource, pCallContext, pParams) #define p2papiControl_Epilogue(pResource, pCallContext, pParams) p2papiControl_Epilogue_DISPATCH(pResource, pCallContext, pParams) #define p2papiControlLookup(pResource, pParams, ppEntry) p2papiControlLookup_DISPATCH(pResource, pParams, ppEntry) #define p2papiMap(pResource, pCallContext, pParams, pCpuMapping) p2papiMap_DISPATCH(pResource, pCallContext, pParams, pCpuMapping) @@ -172,8 +182,12 @@ pResource->__p2papiAddAdditionalDependants__(pClient, pResource, pReference); } -static inline NV_STATUS p2papiUnmap_DISPATCH(struct P2PApi *pResource, struct CALL_CONTEXT *pCallContext, RsCpuMapping *pCpuMapping) { - return pResource->__p2papiUnmap__(pResource, pCallContext, pCpuMapping); +static inline NV_STATUS p2papiUnmapFrom_DISPATCH(struct P2PApi *pResource, RS_RES_UNMAP_FROM_PARAMS *pParams) { + return pResource->__p2papiUnmapFrom__(pResource, pParams); +} + +static inline NV_STATUS p2papiControlSerialization_Prologue_DISPATCH(struct P2PApi *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return pResource->__p2papiControlSerialization_Prologue__(pResource, pCallContext, pParams); } static inline NV_STATUS p2papiControl_Prologue_DISPATCH(struct P2PApi *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { @@ -184,22 +198,26 @@ return pResource->__p2papiCanCopy__(pResource); } -static inline NV_STATUS p2papiMapTo_DISPATCH(struct P2PApi *pResource, RS_RES_MAP_TO_PARAMS *pParams) { - return pResource->__p2papiMapTo__(pResource, pParams); +static inline NV_STATUS p2papiUnmap_DISPATCH(struct P2PApi *pResource, struct CALL_CONTEXT *pCallContext, RsCpuMapping *pCpuMapping) { + return pResource->__p2papiUnmap__(pResource, pCallContext, pCpuMapping); } static inline void p2papiPreDestruct_DISPATCH(struct P2PApi *pResource) { pResource->__p2papiPreDestruct__(pResource); } -static inline NV_STATUS p2papiUnmapFrom_DISPATCH(struct P2PApi *pResource, RS_RES_UNMAP_FROM_PARAMS *pParams) { - return pResource->__p2papiUnmapFrom__(pResource, pParams); +static inline NV_STATUS p2papiMapTo_DISPATCH(struct P2PApi *pResource, RS_RES_MAP_TO_PARAMS *pParams) { + return pResource->__p2papiMapTo__(pResource, pParams); } static inline NV_STATUS p2papiIsDuplicate_DISPATCH(struct P2PApi *pResource, NvHandle hMemory, NvBool *pDuplicate) { return pResource->__p2papiIsDuplicate__(pResource, hMemory, pDuplicate); } +static inline void p2papiControlSerialization_Epilogue_DISPATCH(struct P2PApi *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + pResource->__p2papiControlSerialization_Epilogue__(pResource, pCallContext, pParams); +} + static inline void p2papiControl_Epilogue_DISPATCH(struct P2PApi *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { pResource->__p2papiControl_Epilogue__(pResource, pCallContext, pParams); } diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/generated/g_phys_mem_nvoc.c nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_phys_mem_nvoc.c --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/generated/g_phys_mem_nvoc.c 2023-10-25 20:27:16.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_phys_mem_nvoc.c 2024-03-05 22:18:38.000000000 +0000 @@ -101,60 +101,76 @@ return memCheckMemInterUnmap((struct Memory *)(((unsigned char *)pMemory) + __nvoc_rtti_PhysicalMemory_Memory.offset), bSubdeviceHandleProvided); } -static NV_STATUS __nvoc_thunk_Memory_physmemControl(struct PhysicalMemory *pMemory, CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { - return memControl((struct Memory *)(((unsigned char *)pMemory) + __nvoc_rtti_PhysicalMemory_Memory.offset), pCallContext, pParams); +static NvBool __nvoc_thunk_RmResource_physmemShareCallback(struct PhysicalMemory *pResource, struct RsClient *pInvokingClient, struct RsResourceRef *pParentRef, RS_SHARE_POLICY *pSharePolicy) { + return rmresShareCallback((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_PhysicalMemory_RmResource.offset), pInvokingClient, pParentRef, pSharePolicy); } -static NV_STATUS __nvoc_thunk_Memory_physmemUnmap(struct PhysicalMemory *pMemory, CALL_CONTEXT *pCallContext, RsCpuMapping *pCpuMapping) { - return memUnmap((struct Memory *)(((unsigned char *)pMemory) + __nvoc_rtti_PhysicalMemory_Memory.offset), pCallContext, pCpuMapping); +static NV_STATUS __nvoc_thunk_RsResource_physmemMapTo(struct PhysicalMemory *pResource, RS_RES_MAP_TO_PARAMS *pParams) { + return resMapTo((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_PhysicalMemory_RsResource.offset), pParams); } -static NV_STATUS __nvoc_thunk_Memory_physmemGetMemInterMapParams(struct PhysicalMemory *pMemory, RMRES_MEM_INTER_MAP_PARAMS *pParams) { - return memGetMemInterMapParams((struct Memory *)(((unsigned char *)pMemory) + __nvoc_rtti_PhysicalMemory_Memory.offset), pParams); +static NV_STATUS __nvoc_thunk_Memory_physmemGetMapAddrSpace(struct PhysicalMemory *pMemory, CALL_CONTEXT *pCallContext, NvU32 mapFlags, NV_ADDRESS_SPACE *pAddrSpace) { + return memGetMapAddrSpace((struct Memory *)(((unsigned char *)pMemory) + __nvoc_rtti_PhysicalMemory_Memory.offset), pCallContext, mapFlags, pAddrSpace); } -static NV_STATUS __nvoc_thunk_Memory_physmemGetMemoryMappingDescriptor(struct PhysicalMemory *pMemory, MEMORY_DESCRIPTOR **ppMemDesc) { - return memGetMemoryMappingDescriptor((struct Memory *)(((unsigned char *)pMemory) + __nvoc_rtti_PhysicalMemory_Memory.offset), ppMemDesc); +static NvU32 __nvoc_thunk_RsResource_physmemGetRefCount(struct PhysicalMemory *pResource) { + return resGetRefCount((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_PhysicalMemory_RsResource.offset)); } -static NV_STATUS __nvoc_thunk_Memory_physmemGetMapAddrSpace(struct PhysicalMemory *pMemory, CALL_CONTEXT *pCallContext, NvU32 mapFlags, NV_ADDRESS_SPACE *pAddrSpace) { - return memGetMapAddrSpace((struct Memory *)(((unsigned char *)pMemory) + __nvoc_rtti_PhysicalMemory_Memory.offset), pCallContext, mapFlags, pAddrSpace); +static void __nvoc_thunk_RsResource_physmemAddAdditionalDependants(struct RsClient *pClient, struct PhysicalMemory *pResource, RsResourceRef *pReference) { + resAddAdditionalDependants(pClient, (struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_PhysicalMemory_RsResource.offset), pReference); } -static NvBool __nvoc_thunk_RmResource_physmemShareCallback(struct PhysicalMemory *pResource, struct RsClient *pInvokingClient, struct RsResourceRef *pParentRef, RS_SHARE_POLICY *pSharePolicy) { - return rmresShareCallback((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_PhysicalMemory_RmResource.offset), pInvokingClient, pParentRef, pSharePolicy); +static NV_STATUS __nvoc_thunk_RmResource_physmemControl_Prologue(struct PhysicalMemory *pResource, CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return rmresControl_Prologue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_PhysicalMemory_RmResource.offset), pCallContext, pParams); } -static NV_STATUS __nvoc_thunk_RsResource_physmemControlFilter(struct PhysicalMemory *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { - return resControlFilter((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_PhysicalMemory_RsResource.offset), pCallContext, pParams); +static NvBool __nvoc_thunk_Memory_physmemIsGpuMapAllowed(struct PhysicalMemory *pMemory, struct OBJGPU *pGpu) { + return memIsGpuMapAllowed((struct Memory *)(((unsigned char *)pMemory) + __nvoc_rtti_PhysicalMemory_Memory.offset), pGpu); } -static void __nvoc_thunk_RsResource_physmemAddAdditionalDependants(struct RsClient *pClient, struct PhysicalMemory *pResource, RsResourceRef *pReference) { - resAddAdditionalDependants(pClient, (struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_PhysicalMemory_RsResource.offset), pReference); +static NV_STATUS __nvoc_thunk_RsResource_physmemUnmapFrom(struct PhysicalMemory *pResource, RS_RES_UNMAP_FROM_PARAMS *pParams) { + return resUnmapFrom((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_PhysicalMemory_RsResource.offset), pParams); } -static NvU32 __nvoc_thunk_RsResource_physmemGetRefCount(struct PhysicalMemory *pResource) { - return resGetRefCount((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_PhysicalMemory_RsResource.offset)); +static void __nvoc_thunk_RmResource_physmemControl_Epilogue(struct PhysicalMemory *pResource, CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + rmresControl_Epilogue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_PhysicalMemory_RmResource.offset), pCallContext, pParams); } -static NV_STATUS __nvoc_thunk_RsResource_physmemMapTo(struct PhysicalMemory *pResource, RS_RES_MAP_TO_PARAMS *pParams) { - return resMapTo((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_PhysicalMemory_RsResource.offset), pParams); +static NV_STATUS __nvoc_thunk_RsResource_physmemControlLookup(struct PhysicalMemory *pResource, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams, const struct NVOC_EXPORTED_METHOD_DEF **ppEntry) { + return resControlLookup((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_PhysicalMemory_RsResource.offset), pParams, ppEntry); } -static NV_STATUS __nvoc_thunk_RmResource_physmemControl_Prologue(struct PhysicalMemory *pResource, CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { - return rmresControl_Prologue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_PhysicalMemory_RmResource.offset), pCallContext, pParams); +static NV_STATUS __nvoc_thunk_Memory_physmemControl(struct PhysicalMemory *pMemory, CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return memControl((struct Memory *)(((unsigned char *)pMemory) + __nvoc_rtti_PhysicalMemory_Memory.offset), pCallContext, pParams); } -static NvBool __nvoc_thunk_Memory_physmemIsGpuMapAllowed(struct PhysicalMemory *pMemory, struct OBJGPU *pGpu) { - return memIsGpuMapAllowed((struct Memory *)(((unsigned char *)pMemory) + __nvoc_rtti_PhysicalMemory_Memory.offset), pGpu); +static NV_STATUS __nvoc_thunk_Memory_physmemUnmap(struct PhysicalMemory *pMemory, CALL_CONTEXT *pCallContext, RsCpuMapping *pCpuMapping) { + return memUnmap((struct Memory *)(((unsigned char *)pMemory) + __nvoc_rtti_PhysicalMemory_Memory.offset), pCallContext, pCpuMapping); +} + +static NV_STATUS __nvoc_thunk_Memory_physmemGetMemInterMapParams(struct PhysicalMemory *pMemory, RMRES_MEM_INTER_MAP_PARAMS *pParams) { + return memGetMemInterMapParams((struct Memory *)(((unsigned char *)pMemory) + __nvoc_rtti_PhysicalMemory_Memory.offset), pParams); +} + +static NV_STATUS __nvoc_thunk_Memory_physmemGetMemoryMappingDescriptor(struct PhysicalMemory *pMemory, MEMORY_DESCRIPTOR **ppMemDesc) { + return memGetMemoryMappingDescriptor((struct Memory *)(((unsigned char *)pMemory) + __nvoc_rtti_PhysicalMemory_Memory.offset), ppMemDesc); +} + +static NV_STATUS __nvoc_thunk_RsResource_physmemControlFilter(struct PhysicalMemory *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return resControlFilter((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_PhysicalMemory_RsResource.offset), pCallContext, pParams); +} + +static NV_STATUS __nvoc_thunk_RmResource_physmemControlSerialization_Prologue(struct PhysicalMemory *pResource, CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return rmresControlSerialization_Prologue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_PhysicalMemory_RmResource.offset), pCallContext, pParams); } static NV_STATUS __nvoc_thunk_Memory_physmemIsReady(struct PhysicalMemory *pMemory, NvBool bCopyConstructorContext) { return memIsReady((struct Memory *)(((unsigned char *)pMemory) + __nvoc_rtti_PhysicalMemory_Memory.offset), bCopyConstructorContext); } -static NV_STATUS __nvoc_thunk_Memory_physmemCheckCopyPermissions(struct PhysicalMemory *pMemory, struct OBJGPU *pDstGpu, NvHandle hDstClientNvBool) { - return memCheckCopyPermissions((struct Memory *)(((unsigned char *)pMemory) + __nvoc_rtti_PhysicalMemory_Memory.offset), pDstGpu, hDstClientNvBool); +static NV_STATUS __nvoc_thunk_Memory_physmemCheckCopyPermissions(struct PhysicalMemory *pMemory, struct OBJGPU *pDstGpu, struct Device *pDstDevice) { + return memCheckCopyPermissions((struct Memory *)(((unsigned char *)pMemory) + __nvoc_rtti_PhysicalMemory_Memory.offset), pDstGpu, pDstDevice); } static void __nvoc_thunk_RsResource_physmemPreDestruct(struct PhysicalMemory *pResource) { @@ -165,16 +181,8 @@ return memIsDuplicate((struct Memory *)(((unsigned char *)pMemory) + __nvoc_rtti_PhysicalMemory_Memory.offset), hMemory, pDuplicate); } -static NV_STATUS __nvoc_thunk_RsResource_physmemUnmapFrom(struct PhysicalMemory *pResource, RS_RES_UNMAP_FROM_PARAMS *pParams) { - return resUnmapFrom((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_PhysicalMemory_RsResource.offset), pParams); -} - -static void __nvoc_thunk_RmResource_physmemControl_Epilogue(struct PhysicalMemory *pResource, CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { - rmresControl_Epilogue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_PhysicalMemory_RmResource.offset), pCallContext, pParams); -} - -static NV_STATUS __nvoc_thunk_RsResource_physmemControlLookup(struct PhysicalMemory *pResource, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams, const struct NVOC_EXPORTED_METHOD_DEF **ppEntry) { - return resControlLookup((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_PhysicalMemory_RsResource.offset), pParams, ppEntry); +static void __nvoc_thunk_RmResource_physmemControlSerialization_Epilogue(struct PhysicalMemory *pResource, CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + rmresControlSerialization_Epilogue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_PhysicalMemory_RmResource.offset), pCallContext, pParams); } static NV_STATUS __nvoc_thunk_Memory_physmemMap(struct PhysicalMemory *pMemory, CALL_CONTEXT *pCallContext, struct RS_CPU_MAP_PARAMS *pParams, RsCpuMapping *pCpuMapping) { @@ -229,29 +237,37 @@ pThis->__physmemCheckMemInterUnmap__ = &__nvoc_thunk_Memory_physmemCheckMemInterUnmap; - pThis->__physmemControl__ = &__nvoc_thunk_Memory_physmemControl; + pThis->__physmemShareCallback__ = &__nvoc_thunk_RmResource_physmemShareCallback; - pThis->__physmemUnmap__ = &__nvoc_thunk_Memory_physmemUnmap; + pThis->__physmemMapTo__ = &__nvoc_thunk_RsResource_physmemMapTo; - pThis->__physmemGetMemInterMapParams__ = &__nvoc_thunk_Memory_physmemGetMemInterMapParams; + pThis->__physmemGetMapAddrSpace__ = &__nvoc_thunk_Memory_physmemGetMapAddrSpace; - pThis->__physmemGetMemoryMappingDescriptor__ = &__nvoc_thunk_Memory_physmemGetMemoryMappingDescriptor; + pThis->__physmemGetRefCount__ = &__nvoc_thunk_RsResource_physmemGetRefCount; - pThis->__physmemGetMapAddrSpace__ = &__nvoc_thunk_Memory_physmemGetMapAddrSpace; + pThis->__physmemAddAdditionalDependants__ = &__nvoc_thunk_RsResource_physmemAddAdditionalDependants; - pThis->__physmemShareCallback__ = &__nvoc_thunk_RmResource_physmemShareCallback; + pThis->__physmemControl_Prologue__ = &__nvoc_thunk_RmResource_physmemControl_Prologue; - pThis->__physmemControlFilter__ = &__nvoc_thunk_RsResource_physmemControlFilter; + pThis->__physmemIsGpuMapAllowed__ = &__nvoc_thunk_Memory_physmemIsGpuMapAllowed; - pThis->__physmemAddAdditionalDependants__ = &__nvoc_thunk_RsResource_physmemAddAdditionalDependants; + pThis->__physmemUnmapFrom__ = &__nvoc_thunk_RsResource_physmemUnmapFrom; - pThis->__physmemGetRefCount__ = &__nvoc_thunk_RsResource_physmemGetRefCount; + pThis->__physmemControl_Epilogue__ = &__nvoc_thunk_RmResource_physmemControl_Epilogue; - pThis->__physmemMapTo__ = &__nvoc_thunk_RsResource_physmemMapTo; + pThis->__physmemControlLookup__ = &__nvoc_thunk_RsResource_physmemControlLookup; - pThis->__physmemControl_Prologue__ = &__nvoc_thunk_RmResource_physmemControl_Prologue; + pThis->__physmemControl__ = &__nvoc_thunk_Memory_physmemControl; - pThis->__physmemIsGpuMapAllowed__ = &__nvoc_thunk_Memory_physmemIsGpuMapAllowed; + pThis->__physmemUnmap__ = &__nvoc_thunk_Memory_physmemUnmap; + + pThis->__physmemGetMemInterMapParams__ = &__nvoc_thunk_Memory_physmemGetMemInterMapParams; + + pThis->__physmemGetMemoryMappingDescriptor__ = &__nvoc_thunk_Memory_physmemGetMemoryMappingDescriptor; + + pThis->__physmemControlFilter__ = &__nvoc_thunk_RsResource_physmemControlFilter; + + pThis->__physmemControlSerialization_Prologue__ = &__nvoc_thunk_RmResource_physmemControlSerialization_Prologue; pThis->__physmemIsReady__ = &__nvoc_thunk_Memory_physmemIsReady; @@ -261,11 +277,7 @@ pThis->__physmemIsDuplicate__ = &__nvoc_thunk_Memory_physmemIsDuplicate; - pThis->__physmemUnmapFrom__ = &__nvoc_thunk_RsResource_physmemUnmapFrom; - - pThis->__physmemControl_Epilogue__ = &__nvoc_thunk_RmResource_physmemControl_Epilogue; - - pThis->__physmemControlLookup__ = &__nvoc_thunk_RsResource_physmemControlLookup; + pThis->__physmemControlSerialization_Epilogue__ = &__nvoc_thunk_RmResource_physmemControlSerialization_Epilogue; pThis->__physmemMap__ = &__nvoc_thunk_Memory_physmemMap; @@ -293,13 +305,16 @@ Object *pParentObj; PhysicalMemory *pThis; - pThis = portMemAllocNonPaged(sizeof(PhysicalMemory)); - if (pThis == NULL) return NV_ERR_NO_MEMORY; + status = __nvoc_handleObjCreateMemAlloc(createFlags, sizeof(PhysicalMemory), (void**)&pThis, (void**)ppThis); + if (status != NV_OK) + return status; portMemSet(pThis, 0, sizeof(PhysicalMemory)); __nvoc_initRtti(staticCast(pThis, Dynamic), &__nvoc_class_def_PhysicalMemory); + pThis->__nvoc_base_Memory.__nvoc_base_RmResource.__nvoc_base_RsResource.__nvoc_base_Object.createFlags = createFlags; + if (pParent != NULL && !(createFlags & NVOC_OBJ_CREATE_FLAGS_PARENT_HALSPEC_ONLY)) { pParentObj = dynamicCast(pParent, Object); @@ -315,11 +330,17 @@ if (status != NV_OK) goto __nvoc_objCreate_PhysicalMemory_cleanup; *ppThis = pThis; + return NV_OK; __nvoc_objCreate_PhysicalMemory_cleanup: // do not call destructors here since the constructor already called them - portMemFree(pThis); + if (createFlags & NVOC_OBJ_CREATE_FLAGS_IN_PLACE_CONSTRUCT) + portMemSet(pThis, 0, sizeof(PhysicalMemory)); + else + portMemFree(pThis); + + // coverity[leaked_storage:FALSE] return status; } diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/generated/g_phys_mem_nvoc.h nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_phys_mem_nvoc.h --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/generated/g_phys_mem_nvoc.h 2023-10-25 20:27:16.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_phys_mem_nvoc.h 2024-03-05 22:18:38.000000000 +0000 @@ -57,25 +57,27 @@ struct PhysicalMemory *__nvoc_pbase_PhysicalMemory; NvBool (*__physmemCanCopy__)(struct PhysicalMemory *); NV_STATUS (*__physmemCheckMemInterUnmap__)(struct PhysicalMemory *, NvBool); + NvBool (*__physmemShareCallback__)(struct PhysicalMemory *, struct RsClient *, struct RsResourceRef *, RS_SHARE_POLICY *); + NV_STATUS (*__physmemMapTo__)(struct PhysicalMemory *, RS_RES_MAP_TO_PARAMS *); + NV_STATUS (*__physmemGetMapAddrSpace__)(struct PhysicalMemory *, CALL_CONTEXT *, NvU32, NV_ADDRESS_SPACE *); + NvU32 (*__physmemGetRefCount__)(struct PhysicalMemory *); + void (*__physmemAddAdditionalDependants__)(struct RsClient *, struct PhysicalMemory *, RsResourceRef *); + NV_STATUS (*__physmemControl_Prologue__)(struct PhysicalMemory *, CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); + NvBool (*__physmemIsGpuMapAllowed__)(struct PhysicalMemory *, struct OBJGPU *); + NV_STATUS (*__physmemUnmapFrom__)(struct PhysicalMemory *, RS_RES_UNMAP_FROM_PARAMS *); + void (*__physmemControl_Epilogue__)(struct PhysicalMemory *, CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); + NV_STATUS (*__physmemControlLookup__)(struct PhysicalMemory *, struct RS_RES_CONTROL_PARAMS_INTERNAL *, const struct NVOC_EXPORTED_METHOD_DEF **); NV_STATUS (*__physmemControl__)(struct PhysicalMemory *, CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); NV_STATUS (*__physmemUnmap__)(struct PhysicalMemory *, CALL_CONTEXT *, RsCpuMapping *); NV_STATUS (*__physmemGetMemInterMapParams__)(struct PhysicalMemory *, RMRES_MEM_INTER_MAP_PARAMS *); NV_STATUS (*__physmemGetMemoryMappingDescriptor__)(struct PhysicalMemory *, MEMORY_DESCRIPTOR **); - NV_STATUS (*__physmemGetMapAddrSpace__)(struct PhysicalMemory *, CALL_CONTEXT *, NvU32, NV_ADDRESS_SPACE *); - NvBool (*__physmemShareCallback__)(struct PhysicalMemory *, struct RsClient *, struct RsResourceRef *, RS_SHARE_POLICY *); NV_STATUS (*__physmemControlFilter__)(struct PhysicalMemory *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); - void (*__physmemAddAdditionalDependants__)(struct RsClient *, struct PhysicalMemory *, RsResourceRef *); - NvU32 (*__physmemGetRefCount__)(struct PhysicalMemory *); - NV_STATUS (*__physmemMapTo__)(struct PhysicalMemory *, RS_RES_MAP_TO_PARAMS *); - NV_STATUS (*__physmemControl_Prologue__)(struct PhysicalMemory *, CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); - NvBool (*__physmemIsGpuMapAllowed__)(struct PhysicalMemory *, struct OBJGPU *); + NV_STATUS (*__physmemControlSerialization_Prologue__)(struct PhysicalMemory *, CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); NV_STATUS (*__physmemIsReady__)(struct PhysicalMemory *, NvBool); - NV_STATUS (*__physmemCheckCopyPermissions__)(struct PhysicalMemory *, struct OBJGPU *, NvHandle); + NV_STATUS (*__physmemCheckCopyPermissions__)(struct PhysicalMemory *, struct OBJGPU *, struct Device *); void (*__physmemPreDestruct__)(struct PhysicalMemory *); NV_STATUS (*__physmemIsDuplicate__)(struct PhysicalMemory *, NvHandle, NvBool *); - NV_STATUS (*__physmemUnmapFrom__)(struct PhysicalMemory *, RS_RES_UNMAP_FROM_PARAMS *); - void (*__physmemControl_Epilogue__)(struct PhysicalMemory *, CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); - NV_STATUS (*__physmemControlLookup__)(struct PhysicalMemory *, struct RS_RES_CONTROL_PARAMS_INTERNAL *, const struct NVOC_EXPORTED_METHOD_DEF **); + void (*__physmemControlSerialization_Epilogue__)(struct PhysicalMemory *, CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); NV_STATUS (*__physmemMap__)(struct PhysicalMemory *, CALL_CONTEXT *, struct RS_CPU_MAP_PARAMS *, RsCpuMapping *); NvBool (*__physmemAccessCallback__)(struct PhysicalMemory *, struct RsClient *, void *, RsAccessRight); }; @@ -110,25 +112,27 @@ #define physmemCanCopy(pPhysicalMemory) physmemCanCopy_DISPATCH(pPhysicalMemory) #define physmemCheckMemInterUnmap(pMemory, bSubdeviceHandleProvided) physmemCheckMemInterUnmap_DISPATCH(pMemory, bSubdeviceHandleProvided) +#define physmemShareCallback(pResource, pInvokingClient, pParentRef, pSharePolicy) physmemShareCallback_DISPATCH(pResource, pInvokingClient, pParentRef, pSharePolicy) +#define physmemMapTo(pResource, pParams) physmemMapTo_DISPATCH(pResource, pParams) +#define physmemGetMapAddrSpace(pMemory, pCallContext, mapFlags, pAddrSpace) physmemGetMapAddrSpace_DISPATCH(pMemory, pCallContext, mapFlags, pAddrSpace) +#define physmemGetRefCount(pResource) physmemGetRefCount_DISPATCH(pResource) +#define physmemAddAdditionalDependants(pClient, pResource, pReference) physmemAddAdditionalDependants_DISPATCH(pClient, pResource, pReference) +#define physmemControl_Prologue(pResource, pCallContext, pParams) physmemControl_Prologue_DISPATCH(pResource, pCallContext, pParams) +#define physmemIsGpuMapAllowed(pMemory, pGpu) physmemIsGpuMapAllowed_DISPATCH(pMemory, pGpu) +#define physmemUnmapFrom(pResource, pParams) physmemUnmapFrom_DISPATCH(pResource, pParams) +#define physmemControl_Epilogue(pResource, pCallContext, pParams) physmemControl_Epilogue_DISPATCH(pResource, pCallContext, pParams) +#define physmemControlLookup(pResource, pParams, ppEntry) physmemControlLookup_DISPATCH(pResource, pParams, ppEntry) #define physmemControl(pMemory, pCallContext, pParams) physmemControl_DISPATCH(pMemory, pCallContext, pParams) #define physmemUnmap(pMemory, pCallContext, pCpuMapping) physmemUnmap_DISPATCH(pMemory, pCallContext, pCpuMapping) #define physmemGetMemInterMapParams(pMemory, pParams) physmemGetMemInterMapParams_DISPATCH(pMemory, pParams) #define physmemGetMemoryMappingDescriptor(pMemory, ppMemDesc) physmemGetMemoryMappingDescriptor_DISPATCH(pMemory, ppMemDesc) -#define physmemGetMapAddrSpace(pMemory, pCallContext, mapFlags, pAddrSpace) physmemGetMapAddrSpace_DISPATCH(pMemory, pCallContext, mapFlags, pAddrSpace) -#define physmemShareCallback(pResource, pInvokingClient, pParentRef, pSharePolicy) physmemShareCallback_DISPATCH(pResource, pInvokingClient, pParentRef, pSharePolicy) #define physmemControlFilter(pResource, pCallContext, pParams) physmemControlFilter_DISPATCH(pResource, pCallContext, pParams) -#define physmemAddAdditionalDependants(pClient, pResource, pReference) physmemAddAdditionalDependants_DISPATCH(pClient, pResource, pReference) -#define physmemGetRefCount(pResource) physmemGetRefCount_DISPATCH(pResource) -#define physmemMapTo(pResource, pParams) physmemMapTo_DISPATCH(pResource, pParams) -#define physmemControl_Prologue(pResource, pCallContext, pParams) physmemControl_Prologue_DISPATCH(pResource, pCallContext, pParams) -#define physmemIsGpuMapAllowed(pMemory, pGpu) physmemIsGpuMapAllowed_DISPATCH(pMemory, pGpu) +#define physmemControlSerialization_Prologue(pResource, pCallContext, pParams) physmemControlSerialization_Prologue_DISPATCH(pResource, pCallContext, pParams) #define physmemIsReady(pMemory, bCopyConstructorContext) physmemIsReady_DISPATCH(pMemory, bCopyConstructorContext) -#define physmemCheckCopyPermissions(pMemory, pDstGpu, hDstClientNvBool) physmemCheckCopyPermissions_DISPATCH(pMemory, pDstGpu, hDstClientNvBool) +#define physmemCheckCopyPermissions(pMemory, pDstGpu, pDstDevice) physmemCheckCopyPermissions_DISPATCH(pMemory, pDstGpu, pDstDevice) #define physmemPreDestruct(pResource) physmemPreDestruct_DISPATCH(pResource) #define physmemIsDuplicate(pMemory, hMemory, pDuplicate) physmemIsDuplicate_DISPATCH(pMemory, hMemory, pDuplicate) -#define physmemUnmapFrom(pResource, pParams) physmemUnmapFrom_DISPATCH(pResource, pParams) -#define physmemControl_Epilogue(pResource, pCallContext, pParams) physmemControl_Epilogue_DISPATCH(pResource, pCallContext, pParams) -#define physmemControlLookup(pResource, pParams, ppEntry) physmemControlLookup_DISPATCH(pResource, pParams, ppEntry) +#define physmemControlSerialization_Epilogue(pResource, pCallContext, pParams) physmemControlSerialization_Epilogue_DISPATCH(pResource, pCallContext, pParams) #define physmemMap(pMemory, pCallContext, pParams, pCpuMapping) physmemMap_DISPATCH(pMemory, pCallContext, pParams, pCpuMapping) #define physmemAccessCallback(pResource, pInvokingClient, pAllocParams, accessRight) physmemAccessCallback_DISPATCH(pResource, pInvokingClient, pAllocParams, accessRight) NvBool physmemCanCopy_IMPL(struct PhysicalMemory *pPhysicalMemory); @@ -141,60 +145,76 @@ return pMemory->__physmemCheckMemInterUnmap__(pMemory, bSubdeviceHandleProvided); } -static inline NV_STATUS physmemControl_DISPATCH(struct PhysicalMemory *pMemory, CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { - return pMemory->__physmemControl__(pMemory, pCallContext, pParams); +static inline NvBool physmemShareCallback_DISPATCH(struct PhysicalMemory *pResource, struct RsClient *pInvokingClient, struct RsResourceRef *pParentRef, RS_SHARE_POLICY *pSharePolicy) { + return pResource->__physmemShareCallback__(pResource, pInvokingClient, pParentRef, pSharePolicy); } -static inline NV_STATUS physmemUnmap_DISPATCH(struct PhysicalMemory *pMemory, CALL_CONTEXT *pCallContext, RsCpuMapping *pCpuMapping) { - return pMemory->__physmemUnmap__(pMemory, pCallContext, pCpuMapping); +static inline NV_STATUS physmemMapTo_DISPATCH(struct PhysicalMemory *pResource, RS_RES_MAP_TO_PARAMS *pParams) { + return pResource->__physmemMapTo__(pResource, pParams); } -static inline NV_STATUS physmemGetMemInterMapParams_DISPATCH(struct PhysicalMemory *pMemory, RMRES_MEM_INTER_MAP_PARAMS *pParams) { - return pMemory->__physmemGetMemInterMapParams__(pMemory, pParams); +static inline NV_STATUS physmemGetMapAddrSpace_DISPATCH(struct PhysicalMemory *pMemory, CALL_CONTEXT *pCallContext, NvU32 mapFlags, NV_ADDRESS_SPACE *pAddrSpace) { + return pMemory->__physmemGetMapAddrSpace__(pMemory, pCallContext, mapFlags, pAddrSpace); } -static inline NV_STATUS physmemGetMemoryMappingDescriptor_DISPATCH(struct PhysicalMemory *pMemory, MEMORY_DESCRIPTOR **ppMemDesc) { - return pMemory->__physmemGetMemoryMappingDescriptor__(pMemory, ppMemDesc); +static inline NvU32 physmemGetRefCount_DISPATCH(struct PhysicalMemory *pResource) { + return pResource->__physmemGetRefCount__(pResource); } -static inline NV_STATUS physmemGetMapAddrSpace_DISPATCH(struct PhysicalMemory *pMemory, CALL_CONTEXT *pCallContext, NvU32 mapFlags, NV_ADDRESS_SPACE *pAddrSpace) { - return pMemory->__physmemGetMapAddrSpace__(pMemory, pCallContext, mapFlags, pAddrSpace); +static inline void physmemAddAdditionalDependants_DISPATCH(struct RsClient *pClient, struct PhysicalMemory *pResource, RsResourceRef *pReference) { + pResource->__physmemAddAdditionalDependants__(pClient, pResource, pReference); } -static inline NvBool physmemShareCallback_DISPATCH(struct PhysicalMemory *pResource, struct RsClient *pInvokingClient, struct RsResourceRef *pParentRef, RS_SHARE_POLICY *pSharePolicy) { - return pResource->__physmemShareCallback__(pResource, pInvokingClient, pParentRef, pSharePolicy); +static inline NV_STATUS physmemControl_Prologue_DISPATCH(struct PhysicalMemory *pResource, CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return pResource->__physmemControl_Prologue__(pResource, pCallContext, pParams); } -static inline NV_STATUS physmemControlFilter_DISPATCH(struct PhysicalMemory *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { - return pResource->__physmemControlFilter__(pResource, pCallContext, pParams); +static inline NvBool physmemIsGpuMapAllowed_DISPATCH(struct PhysicalMemory *pMemory, struct OBJGPU *pGpu) { + return pMemory->__physmemIsGpuMapAllowed__(pMemory, pGpu); } -static inline void physmemAddAdditionalDependants_DISPATCH(struct RsClient *pClient, struct PhysicalMemory *pResource, RsResourceRef *pReference) { - pResource->__physmemAddAdditionalDependants__(pClient, pResource, pReference); +static inline NV_STATUS physmemUnmapFrom_DISPATCH(struct PhysicalMemory *pResource, RS_RES_UNMAP_FROM_PARAMS *pParams) { + return pResource->__physmemUnmapFrom__(pResource, pParams); } -static inline NvU32 physmemGetRefCount_DISPATCH(struct PhysicalMemory *pResource) { - return pResource->__physmemGetRefCount__(pResource); +static inline void physmemControl_Epilogue_DISPATCH(struct PhysicalMemory *pResource, CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + pResource->__physmemControl_Epilogue__(pResource, pCallContext, pParams); } -static inline NV_STATUS physmemMapTo_DISPATCH(struct PhysicalMemory *pResource, RS_RES_MAP_TO_PARAMS *pParams) { - return pResource->__physmemMapTo__(pResource, pParams); +static inline NV_STATUS physmemControlLookup_DISPATCH(struct PhysicalMemory *pResource, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams, const struct NVOC_EXPORTED_METHOD_DEF **ppEntry) { + return pResource->__physmemControlLookup__(pResource, pParams, ppEntry); } -static inline NV_STATUS physmemControl_Prologue_DISPATCH(struct PhysicalMemory *pResource, CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { - return pResource->__physmemControl_Prologue__(pResource, pCallContext, pParams); +static inline NV_STATUS physmemControl_DISPATCH(struct PhysicalMemory *pMemory, CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return pMemory->__physmemControl__(pMemory, pCallContext, pParams); } -static inline NvBool physmemIsGpuMapAllowed_DISPATCH(struct PhysicalMemory *pMemory, struct OBJGPU *pGpu) { - return pMemory->__physmemIsGpuMapAllowed__(pMemory, pGpu); +static inline NV_STATUS physmemUnmap_DISPATCH(struct PhysicalMemory *pMemory, CALL_CONTEXT *pCallContext, RsCpuMapping *pCpuMapping) { + return pMemory->__physmemUnmap__(pMemory, pCallContext, pCpuMapping); +} + +static inline NV_STATUS physmemGetMemInterMapParams_DISPATCH(struct PhysicalMemory *pMemory, RMRES_MEM_INTER_MAP_PARAMS *pParams) { + return pMemory->__physmemGetMemInterMapParams__(pMemory, pParams); +} + +static inline NV_STATUS physmemGetMemoryMappingDescriptor_DISPATCH(struct PhysicalMemory *pMemory, MEMORY_DESCRIPTOR **ppMemDesc) { + return pMemory->__physmemGetMemoryMappingDescriptor__(pMemory, ppMemDesc); +} + +static inline NV_STATUS physmemControlFilter_DISPATCH(struct PhysicalMemory *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return pResource->__physmemControlFilter__(pResource, pCallContext, pParams); +} + +static inline NV_STATUS physmemControlSerialization_Prologue_DISPATCH(struct PhysicalMemory *pResource, CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return pResource->__physmemControlSerialization_Prologue__(pResource, pCallContext, pParams); } static inline NV_STATUS physmemIsReady_DISPATCH(struct PhysicalMemory *pMemory, NvBool bCopyConstructorContext) { return pMemory->__physmemIsReady__(pMemory, bCopyConstructorContext); } -static inline NV_STATUS physmemCheckCopyPermissions_DISPATCH(struct PhysicalMemory *pMemory, struct OBJGPU *pDstGpu, NvHandle hDstClientNvBool) { - return pMemory->__physmemCheckCopyPermissions__(pMemory, pDstGpu, hDstClientNvBool); +static inline NV_STATUS physmemCheckCopyPermissions_DISPATCH(struct PhysicalMemory *pMemory, struct OBJGPU *pDstGpu, struct Device *pDstDevice) { + return pMemory->__physmemCheckCopyPermissions__(pMemory, pDstGpu, pDstDevice); } static inline void physmemPreDestruct_DISPATCH(struct PhysicalMemory *pResource) { @@ -205,16 +225,8 @@ return pMemory->__physmemIsDuplicate__(pMemory, hMemory, pDuplicate); } -static inline NV_STATUS physmemUnmapFrom_DISPATCH(struct PhysicalMemory *pResource, RS_RES_UNMAP_FROM_PARAMS *pParams) { - return pResource->__physmemUnmapFrom__(pResource, pParams); -} - -static inline void physmemControl_Epilogue_DISPATCH(struct PhysicalMemory *pResource, CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { - pResource->__physmemControl_Epilogue__(pResource, pCallContext, pParams); -} - -static inline NV_STATUS physmemControlLookup_DISPATCH(struct PhysicalMemory *pResource, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams, const struct NVOC_EXPORTED_METHOD_DEF **ppEntry) { - return pResource->__physmemControlLookup__(pResource, pParams, ppEntry); +static inline void physmemControlSerialization_Epilogue_DISPATCH(struct PhysicalMemory *pResource, CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + pResource->__physmemControlSerialization_Epilogue__(pResource, pCallContext, pParams); } static inline NV_STATUS physmemMap_DISPATCH(struct PhysicalMemory *pMemory, CALL_CONTEXT *pCallContext, struct RS_CPU_MAP_PARAMS *pParams, RsCpuMapping *pCpuMapping) { diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/generated/g_platform_nvoc.c nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_platform_nvoc.c --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/generated/g_platform_nvoc.c 2023-10-25 20:27:16.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_platform_nvoc.c 2024-03-05 22:18:38.000000000 +0000 @@ -115,13 +115,16 @@ Object *pParentObj; OBJPFM *pThis; - pThis = portMemAllocNonPaged(sizeof(OBJPFM)); - if (pThis == NULL) return NV_ERR_NO_MEMORY; + status = __nvoc_handleObjCreateMemAlloc(createFlags, sizeof(OBJPFM), (void**)&pThis, (void**)ppThis); + if (status != NV_OK) + return status; portMemSet(pThis, 0, sizeof(OBJPFM)); __nvoc_initRtti(staticCast(pThis, Dynamic), &__nvoc_class_def_OBJPFM); + pThis->__nvoc_base_Object.createFlags = createFlags; + if (pParent != NULL && !(createFlags & NVOC_OBJ_CREATE_FLAGS_PARENT_HALSPEC_ONLY)) { pParentObj = dynamicCast(pParent, Object); @@ -137,11 +140,17 @@ if (status != NV_OK) goto __nvoc_objCreate_OBJPFM_cleanup; *ppThis = pThis; + return NV_OK; __nvoc_objCreate_OBJPFM_cleanup: // do not call destructors here since the constructor already called them - portMemFree(pThis); + if (createFlags & NVOC_OBJ_CREATE_FLAGS_IN_PLACE_CONSTRUCT) + portMemSet(pThis, 0, sizeof(OBJPFM)); + else + portMemFree(pThis); + + // coverity[leaked_storage:FALSE] return status; } diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/generated/g_platform_request_handler_nvoc.c nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_platform_request_handler_nvoc.c --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/generated/g_platform_request_handler_nvoc.c 1970-01-01 00:00:00.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_platform_request_handler_nvoc.c 2024-03-05 22:18:39.000000000 +0000 @@ -0,0 +1,162 @@ +#define NVOC_PLATFORM_REQUEST_HANDLER_H_PRIVATE_ACCESS_ALLOWED +#include "nvoc/runtime.h" +#include "nvoc/rtti.h" +#include "nvtypes.h" +#include "nvport/nvport.h" +#include "nvport/inline/util_valist.h" +#include "utils/nvassert.h" +#include "g_platform_request_handler_nvoc.h" + +#ifdef DEBUG +char __nvoc_class_id_uniqueness_check_0x641a7f = 1; +#endif + +extern const struct NVOC_CLASS_DEF __nvoc_class_def_PlatformRequestHandler; + +extern const struct NVOC_CLASS_DEF __nvoc_class_def_Object; + +void __nvoc_init_PlatformRequestHandler(PlatformRequestHandler*); +void __nvoc_init_funcTable_PlatformRequestHandler(PlatformRequestHandler*); +NV_STATUS __nvoc_ctor_PlatformRequestHandler(PlatformRequestHandler*); +void __nvoc_init_dataField_PlatformRequestHandler(PlatformRequestHandler*); +void __nvoc_dtor_PlatformRequestHandler(PlatformRequestHandler*); +extern const struct NVOC_EXPORT_INFO __nvoc_export_info_PlatformRequestHandler; + +static const struct NVOC_RTTI __nvoc_rtti_PlatformRequestHandler_PlatformRequestHandler = { + /*pClassDef=*/ &__nvoc_class_def_PlatformRequestHandler, + /*dtor=*/ (NVOC_DYNAMIC_DTOR) &__nvoc_dtor_PlatformRequestHandler, + /*offset=*/ 0, +}; + +static const struct NVOC_RTTI __nvoc_rtti_PlatformRequestHandler_Object = { + /*pClassDef=*/ &__nvoc_class_def_Object, + /*dtor=*/ &__nvoc_destructFromBase, + /*offset=*/ NV_OFFSETOF(PlatformRequestHandler, __nvoc_base_Object), +}; + +static const struct NVOC_CASTINFO __nvoc_castinfo_PlatformRequestHandler = { + /*numRelatives=*/ 2, + /*relatives=*/ { + &__nvoc_rtti_PlatformRequestHandler_PlatformRequestHandler, + &__nvoc_rtti_PlatformRequestHandler_Object, + }, +}; + +const struct NVOC_CLASS_DEF __nvoc_class_def_PlatformRequestHandler = +{ + /*classInfo=*/ { + /*size=*/ sizeof(PlatformRequestHandler), + /*classId=*/ classId(PlatformRequestHandler), + /*providerId=*/ &__nvoc_rtti_provider, +#if NV_PRINTF_STRINGS_ALLOWED + /*name=*/ "PlatformRequestHandler", +#endif + }, + /*objCreatefn=*/ (NVOC_DYNAMIC_OBJ_CREATE) &__nvoc_objCreateDynamic_PlatformRequestHandler, + /*pCastInfo=*/ &__nvoc_castinfo_PlatformRequestHandler, + /*pExportInfo=*/ &__nvoc_export_info_PlatformRequestHandler +}; + +const struct NVOC_EXPORT_INFO __nvoc_export_info_PlatformRequestHandler = +{ + /*numEntries=*/ 0, + /*pExportEntries=*/ 0 +}; + +void __nvoc_dtor_Object(Object*); +void __nvoc_dtor_PlatformRequestHandler(PlatformRequestHandler *pThis) { + __nvoc_dtor_Object(&pThis->__nvoc_base_Object); + PORT_UNREFERENCED_VARIABLE(pThis); +} + +void __nvoc_init_dataField_PlatformRequestHandler(PlatformRequestHandler *pThis) { + PORT_UNREFERENCED_VARIABLE(pThis); +} + +NV_STATUS __nvoc_ctor_Object(Object* ); +NV_STATUS __nvoc_ctor_PlatformRequestHandler(PlatformRequestHandler *pThis) { + NV_STATUS status = NV_OK; + status = __nvoc_ctor_Object(&pThis->__nvoc_base_Object); + if (status != NV_OK) goto __nvoc_ctor_PlatformRequestHandler_fail_Object; + __nvoc_init_dataField_PlatformRequestHandler(pThis); + + status = __nvoc_pfmreqhndlrConstruct(pThis); + if (status != NV_OK) goto __nvoc_ctor_PlatformRequestHandler_fail__init; + goto __nvoc_ctor_PlatformRequestHandler_exit; // Success + +__nvoc_ctor_PlatformRequestHandler_fail__init: + __nvoc_dtor_Object(&pThis->__nvoc_base_Object); +__nvoc_ctor_PlatformRequestHandler_fail_Object: +__nvoc_ctor_PlatformRequestHandler_exit: + + return status; +} + +static void __nvoc_init_funcTable_PlatformRequestHandler_1(PlatformRequestHandler *pThis) { + PORT_UNREFERENCED_VARIABLE(pThis); +} + +void __nvoc_init_funcTable_PlatformRequestHandler(PlatformRequestHandler *pThis) { + __nvoc_init_funcTable_PlatformRequestHandler_1(pThis); +} + +void __nvoc_init_Object(Object*); +void __nvoc_init_PlatformRequestHandler(PlatformRequestHandler *pThis) { + pThis->__nvoc_pbase_PlatformRequestHandler = pThis; + pThis->__nvoc_pbase_Object = &pThis->__nvoc_base_Object; + __nvoc_init_Object(&pThis->__nvoc_base_Object); + __nvoc_init_funcTable_PlatformRequestHandler(pThis); +} + +NV_STATUS __nvoc_objCreate_PlatformRequestHandler(PlatformRequestHandler **ppThis, Dynamic *pParent, NvU32 createFlags) { + NV_STATUS status; + Object *pParentObj; + PlatformRequestHandler *pThis; + + status = __nvoc_handleObjCreateMemAlloc(createFlags, sizeof(PlatformRequestHandler), (void**)&pThis, (void**)ppThis); + if (status != NV_OK) + return status; + + portMemSet(pThis, 0, sizeof(PlatformRequestHandler)); + + __nvoc_initRtti(staticCast(pThis, Dynamic), &__nvoc_class_def_PlatformRequestHandler); + + pThis->__nvoc_base_Object.createFlags = createFlags; + + if (pParent != NULL && !(createFlags & NVOC_OBJ_CREATE_FLAGS_PARENT_HALSPEC_ONLY)) + { + pParentObj = dynamicCast(pParent, Object); + objAddChild(pParentObj, &pThis->__nvoc_base_Object); + } + else + { + pThis->__nvoc_base_Object.pParent = NULL; + } + + __nvoc_init_PlatformRequestHandler(pThis); + status = __nvoc_ctor_PlatformRequestHandler(pThis); + if (status != NV_OK) goto __nvoc_objCreate_PlatformRequestHandler_cleanup; + + *ppThis = pThis; + + return NV_OK; + +__nvoc_objCreate_PlatformRequestHandler_cleanup: + // do not call destructors here since the constructor already called them + if (createFlags & NVOC_OBJ_CREATE_FLAGS_IN_PLACE_CONSTRUCT) + portMemSet(pThis, 0, sizeof(PlatformRequestHandler)); + else + portMemFree(pThis); + + // coverity[leaked_storage:FALSE] + return status; +} + +NV_STATUS __nvoc_objCreateDynamic_PlatformRequestHandler(PlatformRequestHandler **ppThis, Dynamic *pParent, NvU32 createFlags, va_list args) { + NV_STATUS status; + + status = __nvoc_objCreate_PlatformRequestHandler(ppThis, pParent, createFlags); + + return status; +} + diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/generated/g_platform_request_handler_nvoc.h nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_platform_request_handler_nvoc.h --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/generated/g_platform_request_handler_nvoc.h 2023-10-25 20:27:16.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_platform_request_handler_nvoc.h 2024-03-05 22:18:39.000000000 +0000 @@ -7,7 +7,7 @@ #endif /* - * SPDX-FileCopyrightText: Copyright (c) 2015-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2015-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -49,12 +49,13 @@ #include "platform/platform_request_handler_utils.h" #include "ctrl/ctrl0000/ctrl0000system.h" #include "ctrl/ctrl2080/ctrl2080internal.h" +#include "nvfixedtypes.h" /* ------------------------ Macros ----------------------------------------- */ // // Macro to check if SW ACPI version 2X or not // -#define PFM_REQ_HNDLR_IS_ACPI_VERSION_SW_2X(pPlatformRequestHandler) \ +#define PFM_REQ_HNDLR_IS_ACPI_VERSION_SW_2X(pPlatformRequestHandler) \ (pPlatformRequestHandler->sensorData.PFMREQHNDLRACPIData.acpiVersionSw == \ NV0000_CTRL_PFM_REQ_HNDLR_ACPI_REVISION_SW_2X) @@ -75,7 +76,7 @@ #define PFM_REQ_HNDLR_CTGP_SENSOR NV0000_CTRL_SYSTEM_PARAM_CTGP #define PFM_REQ_HNDLR_PPMD_SENSOR NV0000_CTRL_SYSTEM_PARAM_PPMD #define PFM_REQ_HNDLR_PSHAREPARAMS_COUNT (9U) -#define PFM_REQ_HNDLR_CURR_BASE (2) +#define PFM_REQ_HNDLR_CURR_BASE (2U) #define PFM_REQ_HNDLR_CURR_VALUE(s) (PFM_REQ_HNDLR_CURR_BASE + ((s)%PFM_REQ_HNDLR_PSHAREPARAMS_COUNT)) #define PFM_REQ_HNDLR_LIMIT_BASE (PFM_REQ_HNDLR_CURR_BASE + PFM_REQ_HNDLR_PSHAREPARAMS_COUNT) #define PFM_REQ_HNDLR_LIMIT(s) (PFM_REQ_HNDLR_LIMIT_BASE + ((s)%PFM_REQ_HNDLR_PSHAREPARAMS_COUNT)) @@ -89,12 +90,22 @@ #define PFM_REQ_HNDLR_PM1_STATE_AVAIL (74U) #define PFM_REQ_HNDLR_TDP_IDX (96U) #define PFM_REQ_HNDLR_VPS_PS20_SUPPORT (97U) -#define PFM_REQ_HNDLR_RESERVED_COUNTER (100U) // This should be the last counter, update as needed. +#define PFM_REQ_HNDLR_RESERVED_COUNTER (100U) // This should be the last counter, update as needed. #define PFM_REQ_HNDLR_NUM_COUNTERS (PFM_REQ_HNDLR_RESERVED_COUNTER + 1) #define PFM_REQ_HNDLR_DEFAULT_COUNTER_HOLD_PERIOD_MS (20U) +// +// PRH internal handling of a temp 0C from a platform request. +// +#define PFM_REQ_HNDLR_TEMP_0_C NV_TYPES_CELSIUS_TO_NV_TEMP(0) + +// +// PRH handling for an invalid VP state index. +// +#define PFM_REQ_HNDLR_VPSTATE_INDEX_INVALID NV_U8_MAX + // Header to sensor structure typedef struct { @@ -133,6 +144,7 @@ NvBool bPlatformUserConfigTGPSupport; // reflects SBIOS static requests to override power delta for User Configurable TGP mode NvU32 platformLimitDeltamW; // Cached limit from platform custimization NvU32 prevSbiosVPStateLimit; // reflects previous VPState requested to be set by SBIOS. + NvU32 platformEdppLimit; // Cached last EDPp limit request from platform NvU32 acpiVersionSw; // mapping between spec and supported sw state } PFM_REQ_HNDLR_ACPI_CACHE; @@ -186,6 +198,32 @@ } PFM_REQ_HNDLR_PPM_DATA; /*! + * EDPPeak control data + */ +typedef struct +{ + /*! + * Set while OS workitem is pending execution. + */ + NvBool bWorkItemPending; + + /*! + * EDPpeak limit info data status. + */ + NvBool bDifferPlatformEdppLimit; + + /*! + * EDPpeak limit info data status. + */ + NV_STATUS status; + + /*! + * EDPpeak info data. + */ + NV0000_CTRL_PFM_REQ_HNDLR_EDPP_LIMIT_INFO_V1 edppLimitInfo; +} PFM_REQ_HNDLR_EDPP_DATA; + +/*! * Control tracking and cache limits from SBIOS */ typedef struct @@ -202,6 +240,9 @@ // Current status of platform customized and applied user configurable TGP delta NvBool bPlatformUserConfigTGPmodeEnabled; + + // Current EDPPeak limit control + PFM_REQ_HNDLR_EDPP_DATA edppLimit; } PFM_REQ_HNDLR_CONTROL_DATA; /*! @@ -407,6 +448,39 @@ #define pfmreqhndlrHandleEdppeakLimitUpdate(pPlatformRequestHandler, pGpu, bEnable) pfmreqhndlrHandleEdppeakLimitUpdate_IMPL(pPlatformRequestHandler, pGpu, bEnable) #endif //__nvoc_platform_request_handler_h_disabled +NV_STATUS pfmreqhndlrHandlePlatformEdppLimitUpdate_IMPL(struct PlatformRequestHandler *pPlatformRequestHandler, OBJGPU *pGpu, NvU32 platformEdppLimit); + +#ifdef __nvoc_platform_request_handler_h_disabled +static inline NV_STATUS pfmreqhndlrHandlePlatformEdppLimitUpdate(struct PlatformRequestHandler *pPlatformRequestHandler, OBJGPU *pGpu, NvU32 platformEdppLimit) { + NV_ASSERT_FAILED_PRECOMP("PlatformRequestHandler was disabled!"); + return NV_ERR_NOT_SUPPORTED; +} +#else //__nvoc_platform_request_handler_h_disabled +#define pfmreqhndlrHandlePlatformEdppLimitUpdate(pPlatformRequestHandler, pGpu, platformEdppLimit) pfmreqhndlrHandlePlatformEdppLimitUpdate_IMPL(pPlatformRequestHandler, pGpu, platformEdppLimit) +#endif //__nvoc_platform_request_handler_h_disabled + +NV_STATUS pfmreqhndlrHandlePlatformGetEdppLimit_IMPL(struct PlatformRequestHandler *pPlatformRequestHandler, OBJGPU *pGpu, NvU32 *pPlatformEdppLimit); + +#ifdef __nvoc_platform_request_handler_h_disabled +static inline NV_STATUS pfmreqhndlrHandlePlatformGetEdppLimit(struct PlatformRequestHandler *pPlatformRequestHandler, OBJGPU *pGpu, NvU32 *pPlatformEdppLimit) { + NV_ASSERT_FAILED_PRECOMP("PlatformRequestHandler was disabled!"); + return NV_ERR_NOT_SUPPORTED; +} +#else //__nvoc_platform_request_handler_h_disabled +#define pfmreqhndlrHandlePlatformGetEdppLimit(pPlatformRequestHandler, pGpu, pPlatformEdppLimit) pfmreqhndlrHandlePlatformGetEdppLimit_IMPL(pPlatformRequestHandler, pGpu, pPlatformEdppLimit) +#endif //__nvoc_platform_request_handler_h_disabled + +NV_STATUS pfmreqhndlrHandlePlatformSetEdppLimitInfo_IMPL(struct PlatformRequestHandler *pPlatformRequestHandler, OBJGPU *pGpu); + +#ifdef __nvoc_platform_request_handler_h_disabled +static inline NV_STATUS pfmreqhndlrHandlePlatformSetEdppLimitInfo(struct PlatformRequestHandler *pPlatformRequestHandler, OBJGPU *pGpu) { + NV_ASSERT_FAILED_PRECOMP("PlatformRequestHandler was disabled!"); + return NV_ERR_NOT_SUPPORTED; +} +#else //__nvoc_platform_request_handler_h_disabled +#define pfmreqhndlrHandlePlatformSetEdppLimitInfo(pPlatformRequestHandler, pGpu) pfmreqhndlrHandlePlatformSetEdppLimitInfo_IMPL(pPlatformRequestHandler, pGpu) +#endif //__nvoc_platform_request_handler_h_disabled + NV_STATUS pfmreqhndlrHandleUserConfigurableTgpMode_IMPL(struct PlatformRequestHandler *pPlatformRequestHandler, OBJGPU *pGpu, NvBool bEnable); #ifdef __nvoc_platform_request_handler_h_disabled diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/generated/g_prereq_tracker_nvoc.c nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_prereq_tracker_nvoc.c --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/generated/g_prereq_tracker_nvoc.c 2023-10-25 20:27:16.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_prereq_tracker_nvoc.c 2024-03-05 22:18:39.000000000 +0000 @@ -114,13 +114,16 @@ Object *pParentObj; PrereqTracker *pThis; - pThis = portMemAllocNonPaged(sizeof(PrereqTracker)); - if (pThis == NULL) return NV_ERR_NO_MEMORY; + status = __nvoc_handleObjCreateMemAlloc(createFlags, sizeof(PrereqTracker), (void**)&pThis, (void**)ppThis); + if (status != NV_OK) + return status; portMemSet(pThis, 0, sizeof(PrereqTracker)); __nvoc_initRtti(staticCast(pThis, Dynamic), &__nvoc_class_def_PrereqTracker); + pThis->__nvoc_base_Object.createFlags = createFlags; + if (pParent != NULL && !(createFlags & NVOC_OBJ_CREATE_FLAGS_PARENT_HALSPEC_ONLY)) { pParentObj = dynamicCast(pParent, Object); @@ -136,11 +139,17 @@ if (status != NV_OK) goto __nvoc_objCreate_PrereqTracker_cleanup; *ppThis = pThis; + return NV_OK; __nvoc_objCreate_PrereqTracker_cleanup: // do not call destructors here since the constructor already called them - portMemFree(pThis); + if (createFlags & NVOC_OBJ_CREATE_FLAGS_IN_PLACE_CONSTRUCT) + portMemSet(pThis, 0, sizeof(PrereqTracker)); + else + portMemFree(pThis); + + // coverity[leaked_storage:FALSE] return status; } diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/generated/g_profiler_v1_nvoc.c nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_profiler_v1_nvoc.c --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/generated/g_profiler_v1_nvoc.c 2023-10-25 20:27:17.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_profiler_v1_nvoc.c 2024-03-05 22:18:40.000000000 +0000 @@ -101,44 +101,24 @@ return gpuresShareCallback((struct GpuResource *)(((unsigned char *)pGpuResource) + __nvoc_rtti_Profiler_GpuResource.offset), pInvokingClient, pParentRef, pSharePolicy); } -static NV_STATUS __nvoc_thunk_GpuResource_profilerUnmap(struct Profiler *pGpuResource, struct CALL_CONTEXT *pCallContext, struct RsCpuMapping *pCpuMapping) { - return gpuresUnmap((struct GpuResource *)(((unsigned char *)pGpuResource) + __nvoc_rtti_Profiler_GpuResource.offset), pCallContext, pCpuMapping); -} - -static NV_STATUS __nvoc_thunk_RmResource_profilerGetMemInterMapParams(struct Profiler *pRmResource, RMRES_MEM_INTER_MAP_PARAMS *pParams) { - return rmresGetMemInterMapParams((struct RmResource *)(((unsigned char *)pRmResource) + __nvoc_rtti_Profiler_RmResource.offset), pParams); +static NV_STATUS __nvoc_thunk_RmResource_profilerCheckMemInterUnmap(struct Profiler *pRmResource, NvBool bSubdeviceHandleProvided) { + return rmresCheckMemInterUnmap((struct RmResource *)(((unsigned char *)pRmResource) + __nvoc_rtti_Profiler_RmResource.offset), bSubdeviceHandleProvided); } -static NV_STATUS __nvoc_thunk_RmResource_profilerGetMemoryMappingDescriptor(struct Profiler *pRmResource, struct MEMORY_DESCRIPTOR **ppMemDesc) { - return rmresGetMemoryMappingDescriptor((struct RmResource *)(((unsigned char *)pRmResource) + __nvoc_rtti_Profiler_RmResource.offset), ppMemDesc); +static NV_STATUS __nvoc_thunk_RsResource_profilerMapTo(struct Profiler *pResource, RS_RES_MAP_TO_PARAMS *pParams) { + return resMapTo((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_Profiler_RsResource.offset), pParams); } static NV_STATUS __nvoc_thunk_GpuResource_profilerGetMapAddrSpace(struct Profiler *pGpuResource, struct CALL_CONTEXT *pCallContext, NvU32 mapFlags, NV_ADDRESS_SPACE *pAddrSpace) { return gpuresGetMapAddrSpace((struct GpuResource *)(((unsigned char *)pGpuResource) + __nvoc_rtti_Profiler_GpuResource.offset), pCallContext, mapFlags, pAddrSpace); } -static NvHandle __nvoc_thunk_GpuResource_profilerGetInternalObjectHandle(struct Profiler *pGpuResource) { - return gpuresGetInternalObjectHandle((struct GpuResource *)(((unsigned char *)pGpuResource) + __nvoc_rtti_Profiler_GpuResource.offset)); -} - -static NV_STATUS __nvoc_thunk_RsResource_profilerControlFilter(struct Profiler *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { - return resControlFilter((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_Profiler_RsResource.offset), pCallContext, pParams); -} - -static void __nvoc_thunk_RsResource_profilerAddAdditionalDependants(struct RsClient *pClient, struct Profiler *pResource, RsResourceRef *pReference) { - resAddAdditionalDependants(pClient, (struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_Profiler_RsResource.offset), pReference); -} - static NvU32 __nvoc_thunk_RsResource_profilerGetRefCount(struct Profiler *pResource) { return resGetRefCount((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_Profiler_RsResource.offset)); } -static NV_STATUS __nvoc_thunk_RmResource_profilerCheckMemInterUnmap(struct Profiler *pRmResource, NvBool bSubdeviceHandleProvided) { - return rmresCheckMemInterUnmap((struct RmResource *)(((unsigned char *)pRmResource) + __nvoc_rtti_Profiler_RmResource.offset), bSubdeviceHandleProvided); -} - -static NV_STATUS __nvoc_thunk_RsResource_profilerMapTo(struct Profiler *pResource, RS_RES_MAP_TO_PARAMS *pParams) { - return resMapTo((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_Profiler_RsResource.offset), pParams); +static void __nvoc_thunk_RsResource_profilerAddAdditionalDependants(struct RsClient *pClient, struct Profiler *pResource, RsResourceRef *pReference) { + resAddAdditionalDependants(pClient, (struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_Profiler_RsResource.offset), pReference); } static NV_STATUS __nvoc_thunk_RmResource_profilerControl_Prologue(struct Profiler *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { @@ -149,26 +129,14 @@ return gpuresGetRegBaseOffsetAndSize((struct GpuResource *)(((unsigned char *)pGpuResource) + __nvoc_rtti_Profiler_GpuResource.offset), pGpu, pOffset, pSize); } -static NvBool __nvoc_thunk_RsResource_profilerCanCopy(struct Profiler *pResource) { - return resCanCopy((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_Profiler_RsResource.offset)); -} - static NV_STATUS __nvoc_thunk_GpuResource_profilerInternalControlForward(struct Profiler *pGpuResource, NvU32 command, void *pParams, NvU32 size) { return gpuresInternalControlForward((struct GpuResource *)(((unsigned char *)pGpuResource) + __nvoc_rtti_Profiler_GpuResource.offset), command, pParams, size); } -static void __nvoc_thunk_RsResource_profilerPreDestruct(struct Profiler *pResource) { - resPreDestruct((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_Profiler_RsResource.offset)); -} - static NV_STATUS __nvoc_thunk_RsResource_profilerUnmapFrom(struct Profiler *pResource, RS_RES_UNMAP_FROM_PARAMS *pParams) { return resUnmapFrom((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_Profiler_RsResource.offset), pParams); } -static NV_STATUS __nvoc_thunk_RsResource_profilerIsDuplicate(struct Profiler *pResource, NvHandle hMemory, NvBool *pDuplicate) { - return resIsDuplicate((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_Profiler_RsResource.offset), hMemory, pDuplicate); -} - static void __nvoc_thunk_RmResource_profilerControl_Epilogue(struct Profiler *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { rmresControl_Epilogue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_Profiler_RmResource.offset), pCallContext, pParams); } @@ -177,6 +145,46 @@ return resControlLookup((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_Profiler_RsResource.offset), pParams, ppEntry); } +static NvHandle __nvoc_thunk_GpuResource_profilerGetInternalObjectHandle(struct Profiler *pGpuResource) { + return gpuresGetInternalObjectHandle((struct GpuResource *)(((unsigned char *)pGpuResource) + __nvoc_rtti_Profiler_GpuResource.offset)); +} + +static NV_STATUS __nvoc_thunk_GpuResource_profilerUnmap(struct Profiler *pGpuResource, struct CALL_CONTEXT *pCallContext, struct RsCpuMapping *pCpuMapping) { + return gpuresUnmap((struct GpuResource *)(((unsigned char *)pGpuResource) + __nvoc_rtti_Profiler_GpuResource.offset), pCallContext, pCpuMapping); +} + +static NV_STATUS __nvoc_thunk_RmResource_profilerGetMemInterMapParams(struct Profiler *pRmResource, RMRES_MEM_INTER_MAP_PARAMS *pParams) { + return rmresGetMemInterMapParams((struct RmResource *)(((unsigned char *)pRmResource) + __nvoc_rtti_Profiler_RmResource.offset), pParams); +} + +static NV_STATUS __nvoc_thunk_RmResource_profilerGetMemoryMappingDescriptor(struct Profiler *pRmResource, struct MEMORY_DESCRIPTOR **ppMemDesc) { + return rmresGetMemoryMappingDescriptor((struct RmResource *)(((unsigned char *)pRmResource) + __nvoc_rtti_Profiler_RmResource.offset), ppMemDesc); +} + +static NV_STATUS __nvoc_thunk_RsResource_profilerControlFilter(struct Profiler *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return resControlFilter((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_Profiler_RsResource.offset), pCallContext, pParams); +} + +static NV_STATUS __nvoc_thunk_RmResource_profilerControlSerialization_Prologue(struct Profiler *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return rmresControlSerialization_Prologue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_Profiler_RmResource.offset), pCallContext, pParams); +} + +static NvBool __nvoc_thunk_RsResource_profilerCanCopy(struct Profiler *pResource) { + return resCanCopy((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_Profiler_RsResource.offset)); +} + +static void __nvoc_thunk_RsResource_profilerPreDestruct(struct Profiler *pResource) { + resPreDestruct((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_Profiler_RsResource.offset)); +} + +static NV_STATUS __nvoc_thunk_RsResource_profilerIsDuplicate(struct Profiler *pResource, NvHandle hMemory, NvBool *pDuplicate) { + return resIsDuplicate((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_Profiler_RsResource.offset), hMemory, pDuplicate); +} + +static void __nvoc_thunk_RmResource_profilerControlSerialization_Epilogue(struct Profiler *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + rmresControlSerialization_Epilogue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_Profiler_RmResource.offset), pCallContext, pParams); +} + static NV_STATUS __nvoc_thunk_GpuResource_profilerMap(struct Profiler *pGpuResource, struct CALL_CONTEXT *pCallContext, struct RS_CPU_MAP_PARAMS *pParams, struct RsCpuMapping *pCpuMapping) { return gpuresMap((struct GpuResource *)(((unsigned char *)pGpuResource) + __nvoc_rtti_Profiler_GpuResource.offset), pCallContext, pParams, pCpuMapping); } @@ -344,44 +352,48 @@ pThis->__profilerShareCallback__ = &__nvoc_thunk_GpuResource_profilerShareCallback; - pThis->__profilerUnmap__ = &__nvoc_thunk_GpuResource_profilerUnmap; - - pThis->__profilerGetMemInterMapParams__ = &__nvoc_thunk_RmResource_profilerGetMemInterMapParams; + pThis->__profilerCheckMemInterUnmap__ = &__nvoc_thunk_RmResource_profilerCheckMemInterUnmap; - pThis->__profilerGetMemoryMappingDescriptor__ = &__nvoc_thunk_RmResource_profilerGetMemoryMappingDescriptor; + pThis->__profilerMapTo__ = &__nvoc_thunk_RsResource_profilerMapTo; pThis->__profilerGetMapAddrSpace__ = &__nvoc_thunk_GpuResource_profilerGetMapAddrSpace; - pThis->__profilerGetInternalObjectHandle__ = &__nvoc_thunk_GpuResource_profilerGetInternalObjectHandle; - - pThis->__profilerControlFilter__ = &__nvoc_thunk_RsResource_profilerControlFilter; - - pThis->__profilerAddAdditionalDependants__ = &__nvoc_thunk_RsResource_profilerAddAdditionalDependants; - pThis->__profilerGetRefCount__ = &__nvoc_thunk_RsResource_profilerGetRefCount; - pThis->__profilerCheckMemInterUnmap__ = &__nvoc_thunk_RmResource_profilerCheckMemInterUnmap; - - pThis->__profilerMapTo__ = &__nvoc_thunk_RsResource_profilerMapTo; + pThis->__profilerAddAdditionalDependants__ = &__nvoc_thunk_RsResource_profilerAddAdditionalDependants; pThis->__profilerControl_Prologue__ = &__nvoc_thunk_RmResource_profilerControl_Prologue; pThis->__profilerGetRegBaseOffsetAndSize__ = &__nvoc_thunk_GpuResource_profilerGetRegBaseOffsetAndSize; - pThis->__profilerCanCopy__ = &__nvoc_thunk_RsResource_profilerCanCopy; - pThis->__profilerInternalControlForward__ = &__nvoc_thunk_GpuResource_profilerInternalControlForward; - pThis->__profilerPreDestruct__ = &__nvoc_thunk_RsResource_profilerPreDestruct; - pThis->__profilerUnmapFrom__ = &__nvoc_thunk_RsResource_profilerUnmapFrom; - pThis->__profilerIsDuplicate__ = &__nvoc_thunk_RsResource_profilerIsDuplicate; - pThis->__profilerControl_Epilogue__ = &__nvoc_thunk_RmResource_profilerControl_Epilogue; pThis->__profilerControlLookup__ = &__nvoc_thunk_RsResource_profilerControlLookup; + pThis->__profilerGetInternalObjectHandle__ = &__nvoc_thunk_GpuResource_profilerGetInternalObjectHandle; + + pThis->__profilerUnmap__ = &__nvoc_thunk_GpuResource_profilerUnmap; + + pThis->__profilerGetMemInterMapParams__ = &__nvoc_thunk_RmResource_profilerGetMemInterMapParams; + + pThis->__profilerGetMemoryMappingDescriptor__ = &__nvoc_thunk_RmResource_profilerGetMemoryMappingDescriptor; + + pThis->__profilerControlFilter__ = &__nvoc_thunk_RsResource_profilerControlFilter; + + pThis->__profilerControlSerialization_Prologue__ = &__nvoc_thunk_RmResource_profilerControlSerialization_Prologue; + + pThis->__profilerCanCopy__ = &__nvoc_thunk_RsResource_profilerCanCopy; + + pThis->__profilerPreDestruct__ = &__nvoc_thunk_RsResource_profilerPreDestruct; + + pThis->__profilerIsDuplicate__ = &__nvoc_thunk_RsResource_profilerIsDuplicate; + + pThis->__profilerControlSerialization_Epilogue__ = &__nvoc_thunk_RmResource_profilerControlSerialization_Epilogue; + pThis->__profilerMap__ = &__nvoc_thunk_GpuResource_profilerMap; pThis->__profilerAccessCallback__ = &__nvoc_thunk_RmResource_profilerAccessCallback; @@ -409,13 +421,16 @@ Profiler *pThis; RmHalspecOwner *pRmhalspecowner; - pThis = portMemAllocNonPaged(sizeof(Profiler)); - if (pThis == NULL) return NV_ERR_NO_MEMORY; + status = __nvoc_handleObjCreateMemAlloc(createFlags, sizeof(Profiler), (void**)&pThis, (void**)ppThis); + if (status != NV_OK) + return status; portMemSet(pThis, 0, sizeof(Profiler)); __nvoc_initRtti(staticCast(pThis, Dynamic), &__nvoc_class_def_Profiler); + pThis->__nvoc_base_GpuResource.__nvoc_base_RmResource.__nvoc_base_RsResource.__nvoc_base_Object.createFlags = createFlags; + if (pParent != NULL && !(createFlags & NVOC_OBJ_CREATE_FLAGS_PARENT_HALSPEC_ONLY)) { pParentObj = dynamicCast(pParent, Object); @@ -435,11 +450,17 @@ if (status != NV_OK) goto __nvoc_objCreate_Profiler_cleanup; *ppThis = pThis; + return NV_OK; __nvoc_objCreate_Profiler_cleanup: // do not call destructors here since the constructor already called them - portMemFree(pThis); + if (createFlags & NVOC_OBJ_CREATE_FLAGS_IN_PLACE_CONSTRUCT) + portMemSet(pThis, 0, sizeof(Profiler)); + else + portMemFree(pThis); + + // coverity[leaked_storage:FALSE] return status; } diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/generated/g_profiler_v1_nvoc.h nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_profiler_v1_nvoc.h --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/generated/g_profiler_v1_nvoc.h 2023-10-25 20:27:17.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_profiler_v1_nvoc.h 2024-03-05 22:18:40.000000000 +0000 @@ -63,25 +63,27 @@ NV_STATUS (*__profilerCtrlCmdProfilerRequestCgControls__)(struct Profiler *, NV90CC_CTRL_POWER_REQUEST_FEATURES_PARAMS *); NV_STATUS (*__profilerCtrlCmdProfilerReleaseCgControls__)(struct Profiler *, NV90CC_CTRL_POWER_RELEASE_FEATURES_PARAMS *); NvBool (*__profilerShareCallback__)(struct Profiler *, struct RsClient *, struct RsResourceRef *, RS_SHARE_POLICY *); - NV_STATUS (*__profilerUnmap__)(struct Profiler *, struct CALL_CONTEXT *, struct RsCpuMapping *); - NV_STATUS (*__profilerGetMemInterMapParams__)(struct Profiler *, RMRES_MEM_INTER_MAP_PARAMS *); - NV_STATUS (*__profilerGetMemoryMappingDescriptor__)(struct Profiler *, struct MEMORY_DESCRIPTOR **); - NV_STATUS (*__profilerGetMapAddrSpace__)(struct Profiler *, struct CALL_CONTEXT *, NvU32, NV_ADDRESS_SPACE *); - NvHandle (*__profilerGetInternalObjectHandle__)(struct Profiler *); - NV_STATUS (*__profilerControlFilter__)(struct Profiler *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); - void (*__profilerAddAdditionalDependants__)(struct RsClient *, struct Profiler *, RsResourceRef *); - NvU32 (*__profilerGetRefCount__)(struct Profiler *); NV_STATUS (*__profilerCheckMemInterUnmap__)(struct Profiler *, NvBool); NV_STATUS (*__profilerMapTo__)(struct Profiler *, RS_RES_MAP_TO_PARAMS *); + NV_STATUS (*__profilerGetMapAddrSpace__)(struct Profiler *, struct CALL_CONTEXT *, NvU32, NV_ADDRESS_SPACE *); + NvU32 (*__profilerGetRefCount__)(struct Profiler *); + void (*__profilerAddAdditionalDependants__)(struct RsClient *, struct Profiler *, RsResourceRef *); NV_STATUS (*__profilerControl_Prologue__)(struct Profiler *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); NV_STATUS (*__profilerGetRegBaseOffsetAndSize__)(struct Profiler *, struct OBJGPU *, NvU32 *, NvU32 *); - NvBool (*__profilerCanCopy__)(struct Profiler *); NV_STATUS (*__profilerInternalControlForward__)(struct Profiler *, NvU32, void *, NvU32); - void (*__profilerPreDestruct__)(struct Profiler *); NV_STATUS (*__profilerUnmapFrom__)(struct Profiler *, RS_RES_UNMAP_FROM_PARAMS *); - NV_STATUS (*__profilerIsDuplicate__)(struct Profiler *, NvHandle, NvBool *); void (*__profilerControl_Epilogue__)(struct Profiler *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); NV_STATUS (*__profilerControlLookup__)(struct Profiler *, struct RS_RES_CONTROL_PARAMS_INTERNAL *, const struct NVOC_EXPORTED_METHOD_DEF **); + NvHandle (*__profilerGetInternalObjectHandle__)(struct Profiler *); + NV_STATUS (*__profilerUnmap__)(struct Profiler *, struct CALL_CONTEXT *, struct RsCpuMapping *); + NV_STATUS (*__profilerGetMemInterMapParams__)(struct Profiler *, RMRES_MEM_INTER_MAP_PARAMS *); + NV_STATUS (*__profilerGetMemoryMappingDescriptor__)(struct Profiler *, struct MEMORY_DESCRIPTOR **); + NV_STATUS (*__profilerControlFilter__)(struct Profiler *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); + NV_STATUS (*__profilerControlSerialization_Prologue__)(struct Profiler *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); + NvBool (*__profilerCanCopy__)(struct Profiler *); + void (*__profilerPreDestruct__)(struct Profiler *); + NV_STATUS (*__profilerIsDuplicate__)(struct Profiler *, NvHandle, NvBool *); + void (*__profilerControlSerialization_Epilogue__)(struct Profiler *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); NV_STATUS (*__profilerMap__)(struct Profiler *, struct CALL_CONTEXT *, struct RS_CPU_MAP_PARAMS *, struct RsCpuMapping *); NvBool (*__profilerAccessCallback__)(struct Profiler *, struct RsClient *, void *, RsAccessRight); }; @@ -121,25 +123,27 @@ #define profilerCtrlCmdProfilerRequestCgControls(pProfiler, pParams) profilerCtrlCmdProfilerRequestCgControls_DISPATCH(pProfiler, pParams) #define profilerCtrlCmdProfilerReleaseCgControls(pProfiler, pParams) profilerCtrlCmdProfilerReleaseCgControls_DISPATCH(pProfiler, pParams) #define profilerShareCallback(pGpuResource, pInvokingClient, pParentRef, pSharePolicy) profilerShareCallback_DISPATCH(pGpuResource, pInvokingClient, pParentRef, pSharePolicy) -#define profilerUnmap(pGpuResource, pCallContext, pCpuMapping) profilerUnmap_DISPATCH(pGpuResource, pCallContext, pCpuMapping) -#define profilerGetMemInterMapParams(pRmResource, pParams) profilerGetMemInterMapParams_DISPATCH(pRmResource, pParams) -#define profilerGetMemoryMappingDescriptor(pRmResource, ppMemDesc) profilerGetMemoryMappingDescriptor_DISPATCH(pRmResource, ppMemDesc) -#define profilerGetMapAddrSpace(pGpuResource, pCallContext, mapFlags, pAddrSpace) profilerGetMapAddrSpace_DISPATCH(pGpuResource, pCallContext, mapFlags, pAddrSpace) -#define profilerGetInternalObjectHandle(pGpuResource) profilerGetInternalObjectHandle_DISPATCH(pGpuResource) -#define profilerControlFilter(pResource, pCallContext, pParams) profilerControlFilter_DISPATCH(pResource, pCallContext, pParams) -#define profilerAddAdditionalDependants(pClient, pResource, pReference) profilerAddAdditionalDependants_DISPATCH(pClient, pResource, pReference) -#define profilerGetRefCount(pResource) profilerGetRefCount_DISPATCH(pResource) #define profilerCheckMemInterUnmap(pRmResource, bSubdeviceHandleProvided) profilerCheckMemInterUnmap_DISPATCH(pRmResource, bSubdeviceHandleProvided) #define profilerMapTo(pResource, pParams) profilerMapTo_DISPATCH(pResource, pParams) +#define profilerGetMapAddrSpace(pGpuResource, pCallContext, mapFlags, pAddrSpace) profilerGetMapAddrSpace_DISPATCH(pGpuResource, pCallContext, mapFlags, pAddrSpace) +#define profilerGetRefCount(pResource) profilerGetRefCount_DISPATCH(pResource) +#define profilerAddAdditionalDependants(pClient, pResource, pReference) profilerAddAdditionalDependants_DISPATCH(pClient, pResource, pReference) #define profilerControl_Prologue(pResource, pCallContext, pParams) profilerControl_Prologue_DISPATCH(pResource, pCallContext, pParams) #define profilerGetRegBaseOffsetAndSize(pGpuResource, pGpu, pOffset, pSize) profilerGetRegBaseOffsetAndSize_DISPATCH(pGpuResource, pGpu, pOffset, pSize) -#define profilerCanCopy(pResource) profilerCanCopy_DISPATCH(pResource) #define profilerInternalControlForward(pGpuResource, command, pParams, size) profilerInternalControlForward_DISPATCH(pGpuResource, command, pParams, size) -#define profilerPreDestruct(pResource) profilerPreDestruct_DISPATCH(pResource) #define profilerUnmapFrom(pResource, pParams) profilerUnmapFrom_DISPATCH(pResource, pParams) -#define profilerIsDuplicate(pResource, hMemory, pDuplicate) profilerIsDuplicate_DISPATCH(pResource, hMemory, pDuplicate) #define profilerControl_Epilogue(pResource, pCallContext, pParams) profilerControl_Epilogue_DISPATCH(pResource, pCallContext, pParams) #define profilerControlLookup(pResource, pParams, ppEntry) profilerControlLookup_DISPATCH(pResource, pParams, ppEntry) +#define profilerGetInternalObjectHandle(pGpuResource) profilerGetInternalObjectHandle_DISPATCH(pGpuResource) +#define profilerUnmap(pGpuResource, pCallContext, pCpuMapping) profilerUnmap_DISPATCH(pGpuResource, pCallContext, pCpuMapping) +#define profilerGetMemInterMapParams(pRmResource, pParams) profilerGetMemInterMapParams_DISPATCH(pRmResource, pParams) +#define profilerGetMemoryMappingDescriptor(pRmResource, ppMemDesc) profilerGetMemoryMappingDescriptor_DISPATCH(pRmResource, ppMemDesc) +#define profilerControlFilter(pResource, pCallContext, pParams) profilerControlFilter_DISPATCH(pResource, pCallContext, pParams) +#define profilerControlSerialization_Prologue(pResource, pCallContext, pParams) profilerControlSerialization_Prologue_DISPATCH(pResource, pCallContext, pParams) +#define profilerCanCopy(pResource) profilerCanCopy_DISPATCH(pResource) +#define profilerPreDestruct(pResource) profilerPreDestruct_DISPATCH(pResource) +#define profilerIsDuplicate(pResource, hMemory, pDuplicate) profilerIsDuplicate_DISPATCH(pResource, hMemory, pDuplicate) +#define profilerControlSerialization_Epilogue(pResource, pCallContext, pParams) profilerControlSerialization_Epilogue_DISPATCH(pResource, pCallContext, pParams) #define profilerMap(pGpuResource, pCallContext, pParams, pCpuMapping) profilerMap_DISPATCH(pGpuResource, pCallContext, pParams, pCpuMapping) #define profilerAccessCallback(pResource, pInvokingClient, pAllocParams, accessRight) profilerAccessCallback_DISPATCH(pResource, pInvokingClient, pAllocParams, accessRight) NvBool profilerIsProfilingPermitted_IMPL(struct Profiler *pProfiler); @@ -234,44 +238,24 @@ return pGpuResource->__profilerShareCallback__(pGpuResource, pInvokingClient, pParentRef, pSharePolicy); } -static inline NV_STATUS profilerUnmap_DISPATCH(struct Profiler *pGpuResource, struct CALL_CONTEXT *pCallContext, struct RsCpuMapping *pCpuMapping) { - return pGpuResource->__profilerUnmap__(pGpuResource, pCallContext, pCpuMapping); -} - -static inline NV_STATUS profilerGetMemInterMapParams_DISPATCH(struct Profiler *pRmResource, RMRES_MEM_INTER_MAP_PARAMS *pParams) { - return pRmResource->__profilerGetMemInterMapParams__(pRmResource, pParams); +static inline NV_STATUS profilerCheckMemInterUnmap_DISPATCH(struct Profiler *pRmResource, NvBool bSubdeviceHandleProvided) { + return pRmResource->__profilerCheckMemInterUnmap__(pRmResource, bSubdeviceHandleProvided); } -static inline NV_STATUS profilerGetMemoryMappingDescriptor_DISPATCH(struct Profiler *pRmResource, struct MEMORY_DESCRIPTOR **ppMemDesc) { - return pRmResource->__profilerGetMemoryMappingDescriptor__(pRmResource, ppMemDesc); +static inline NV_STATUS profilerMapTo_DISPATCH(struct Profiler *pResource, RS_RES_MAP_TO_PARAMS *pParams) { + return pResource->__profilerMapTo__(pResource, pParams); } static inline NV_STATUS profilerGetMapAddrSpace_DISPATCH(struct Profiler *pGpuResource, struct CALL_CONTEXT *pCallContext, NvU32 mapFlags, NV_ADDRESS_SPACE *pAddrSpace) { return pGpuResource->__profilerGetMapAddrSpace__(pGpuResource, pCallContext, mapFlags, pAddrSpace); } -static inline NvHandle profilerGetInternalObjectHandle_DISPATCH(struct Profiler *pGpuResource) { - return pGpuResource->__profilerGetInternalObjectHandle__(pGpuResource); -} - -static inline NV_STATUS profilerControlFilter_DISPATCH(struct Profiler *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { - return pResource->__profilerControlFilter__(pResource, pCallContext, pParams); -} - -static inline void profilerAddAdditionalDependants_DISPATCH(struct RsClient *pClient, struct Profiler *pResource, RsResourceRef *pReference) { - pResource->__profilerAddAdditionalDependants__(pClient, pResource, pReference); -} - static inline NvU32 profilerGetRefCount_DISPATCH(struct Profiler *pResource) { return pResource->__profilerGetRefCount__(pResource); } -static inline NV_STATUS profilerCheckMemInterUnmap_DISPATCH(struct Profiler *pRmResource, NvBool bSubdeviceHandleProvided) { - return pRmResource->__profilerCheckMemInterUnmap__(pRmResource, bSubdeviceHandleProvided); -} - -static inline NV_STATUS profilerMapTo_DISPATCH(struct Profiler *pResource, RS_RES_MAP_TO_PARAMS *pParams) { - return pResource->__profilerMapTo__(pResource, pParams); +static inline void profilerAddAdditionalDependants_DISPATCH(struct RsClient *pClient, struct Profiler *pResource, RsResourceRef *pReference) { + pResource->__profilerAddAdditionalDependants__(pClient, pResource, pReference); } static inline NV_STATUS profilerControl_Prologue_DISPATCH(struct Profiler *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { @@ -282,26 +266,14 @@ return pGpuResource->__profilerGetRegBaseOffsetAndSize__(pGpuResource, pGpu, pOffset, pSize); } -static inline NvBool profilerCanCopy_DISPATCH(struct Profiler *pResource) { - return pResource->__profilerCanCopy__(pResource); -} - static inline NV_STATUS profilerInternalControlForward_DISPATCH(struct Profiler *pGpuResource, NvU32 command, void *pParams, NvU32 size) { return pGpuResource->__profilerInternalControlForward__(pGpuResource, command, pParams, size); } -static inline void profilerPreDestruct_DISPATCH(struct Profiler *pResource) { - pResource->__profilerPreDestruct__(pResource); -} - static inline NV_STATUS profilerUnmapFrom_DISPATCH(struct Profiler *pResource, RS_RES_UNMAP_FROM_PARAMS *pParams) { return pResource->__profilerUnmapFrom__(pResource, pParams); } -static inline NV_STATUS profilerIsDuplicate_DISPATCH(struct Profiler *pResource, NvHandle hMemory, NvBool *pDuplicate) { - return pResource->__profilerIsDuplicate__(pResource, hMemory, pDuplicate); -} - static inline void profilerControl_Epilogue_DISPATCH(struct Profiler *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { pResource->__profilerControl_Epilogue__(pResource, pCallContext, pParams); } @@ -310,6 +282,46 @@ return pResource->__profilerControlLookup__(pResource, pParams, ppEntry); } +static inline NvHandle profilerGetInternalObjectHandle_DISPATCH(struct Profiler *pGpuResource) { + return pGpuResource->__profilerGetInternalObjectHandle__(pGpuResource); +} + +static inline NV_STATUS profilerUnmap_DISPATCH(struct Profiler *pGpuResource, struct CALL_CONTEXT *pCallContext, struct RsCpuMapping *pCpuMapping) { + return pGpuResource->__profilerUnmap__(pGpuResource, pCallContext, pCpuMapping); +} + +static inline NV_STATUS profilerGetMemInterMapParams_DISPATCH(struct Profiler *pRmResource, RMRES_MEM_INTER_MAP_PARAMS *pParams) { + return pRmResource->__profilerGetMemInterMapParams__(pRmResource, pParams); +} + +static inline NV_STATUS profilerGetMemoryMappingDescriptor_DISPATCH(struct Profiler *pRmResource, struct MEMORY_DESCRIPTOR **ppMemDesc) { + return pRmResource->__profilerGetMemoryMappingDescriptor__(pRmResource, ppMemDesc); +} + +static inline NV_STATUS profilerControlFilter_DISPATCH(struct Profiler *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return pResource->__profilerControlFilter__(pResource, pCallContext, pParams); +} + +static inline NV_STATUS profilerControlSerialization_Prologue_DISPATCH(struct Profiler *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return pResource->__profilerControlSerialization_Prologue__(pResource, pCallContext, pParams); +} + +static inline NvBool profilerCanCopy_DISPATCH(struct Profiler *pResource) { + return pResource->__profilerCanCopy__(pResource); +} + +static inline void profilerPreDestruct_DISPATCH(struct Profiler *pResource) { + pResource->__profilerPreDestruct__(pResource); +} + +static inline NV_STATUS profilerIsDuplicate_DISPATCH(struct Profiler *pResource, NvHandle hMemory, NvBool *pDuplicate) { + return pResource->__profilerIsDuplicate__(pResource, hMemory, pDuplicate); +} + +static inline void profilerControlSerialization_Epilogue_DISPATCH(struct Profiler *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + pResource->__profilerControlSerialization_Epilogue__(pResource, pCallContext, pParams); +} + static inline NV_STATUS profilerMap_DISPATCH(struct Profiler *pGpuResource, struct CALL_CONTEXT *pCallContext, struct RS_CPU_MAP_PARAMS *pParams, struct RsCpuMapping *pCpuMapping) { return pGpuResource->__profilerMap__(pGpuResource, pCallContext, pParams, pCpuMapping); } diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/generated/g_profiler_v2_nvoc.c nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_profiler_v2_nvoc.c --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/generated/g_profiler_v2_nvoc.c 2023-10-25 20:27:17.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_profiler_v2_nvoc.c 2024-03-05 22:18:41.000000000 +0000 @@ -97,84 +97,92 @@ return gpuresShareCallback((struct GpuResource *)(((unsigned char *)pGpuResource) + __nvoc_rtti_ProfilerBase_GpuResource.offset), pInvokingClient, pParentRef, pSharePolicy); } -static NV_STATUS __nvoc_thunk_GpuResource_profilerBaseControl(struct ProfilerBase *pGpuResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { - return gpuresControl((struct GpuResource *)(((unsigned char *)pGpuResource) + __nvoc_rtti_ProfilerBase_GpuResource.offset), pCallContext, pParams); +static NV_STATUS __nvoc_thunk_RmResource_profilerBaseCheckMemInterUnmap(struct ProfilerBase *pRmResource, NvBool bSubdeviceHandleProvided) { + return rmresCheckMemInterUnmap((struct RmResource *)(((unsigned char *)pRmResource) + __nvoc_rtti_ProfilerBase_RmResource.offset), bSubdeviceHandleProvided); } -static NV_STATUS __nvoc_thunk_GpuResource_profilerBaseUnmap(struct ProfilerBase *pGpuResource, struct CALL_CONTEXT *pCallContext, struct RsCpuMapping *pCpuMapping) { - return gpuresUnmap((struct GpuResource *)(((unsigned char *)pGpuResource) + __nvoc_rtti_ProfilerBase_GpuResource.offset), pCallContext, pCpuMapping); +static NV_STATUS __nvoc_thunk_RsResource_profilerBaseMapTo(struct ProfilerBase *pResource, RS_RES_MAP_TO_PARAMS *pParams) { + return resMapTo((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_ProfilerBase_RsResource.offset), pParams); } -static NV_STATUS __nvoc_thunk_RmResource_profilerBaseGetMemInterMapParams(struct ProfilerBase *pRmResource, RMRES_MEM_INTER_MAP_PARAMS *pParams) { - return rmresGetMemInterMapParams((struct RmResource *)(((unsigned char *)pRmResource) + __nvoc_rtti_ProfilerBase_RmResource.offset), pParams); +static NV_STATUS __nvoc_thunk_GpuResource_profilerBaseGetMapAddrSpace(struct ProfilerBase *pGpuResource, struct CALL_CONTEXT *pCallContext, NvU32 mapFlags, NV_ADDRESS_SPACE *pAddrSpace) { + return gpuresGetMapAddrSpace((struct GpuResource *)(((unsigned char *)pGpuResource) + __nvoc_rtti_ProfilerBase_GpuResource.offset), pCallContext, mapFlags, pAddrSpace); } -static NV_STATUS __nvoc_thunk_RmResource_profilerBaseGetMemoryMappingDescriptor(struct ProfilerBase *pRmResource, struct MEMORY_DESCRIPTOR **ppMemDesc) { - return rmresGetMemoryMappingDescriptor((struct RmResource *)(((unsigned char *)pRmResource) + __nvoc_rtti_ProfilerBase_RmResource.offset), ppMemDesc); +static NvU32 __nvoc_thunk_RsResource_profilerBaseGetRefCount(struct ProfilerBase *pResource) { + return resGetRefCount((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_ProfilerBase_RsResource.offset)); } -static NV_STATUS __nvoc_thunk_GpuResource_profilerBaseGetMapAddrSpace(struct ProfilerBase *pGpuResource, struct CALL_CONTEXT *pCallContext, NvU32 mapFlags, NV_ADDRESS_SPACE *pAddrSpace) { - return gpuresGetMapAddrSpace((struct GpuResource *)(((unsigned char *)pGpuResource) + __nvoc_rtti_ProfilerBase_GpuResource.offset), pCallContext, mapFlags, pAddrSpace); +static void __nvoc_thunk_RsResource_profilerBaseAddAdditionalDependants(struct RsClient *pClient, struct ProfilerBase *pResource, RsResourceRef *pReference) { + resAddAdditionalDependants(pClient, (struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_ProfilerBase_RsResource.offset), pReference); } -static NvHandle __nvoc_thunk_GpuResource_profilerBaseGetInternalObjectHandle(struct ProfilerBase *pGpuResource) { - return gpuresGetInternalObjectHandle((struct GpuResource *)(((unsigned char *)pGpuResource) + __nvoc_rtti_ProfilerBase_GpuResource.offset)); +static NV_STATUS __nvoc_thunk_RmResource_profilerBaseControl_Prologue(struct ProfilerBase *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return rmresControl_Prologue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_ProfilerBase_RmResource.offset), pCallContext, pParams); } -static NV_STATUS __nvoc_thunk_RsResource_profilerBaseControlFilter(struct ProfilerBase *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { - return resControlFilter((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_ProfilerBase_RsResource.offset), pCallContext, pParams); +static NV_STATUS __nvoc_thunk_GpuResource_profilerBaseGetRegBaseOffsetAndSize(struct ProfilerBase *pGpuResource, struct OBJGPU *pGpu, NvU32 *pOffset, NvU32 *pSize) { + return gpuresGetRegBaseOffsetAndSize((struct GpuResource *)(((unsigned char *)pGpuResource) + __nvoc_rtti_ProfilerBase_GpuResource.offset), pGpu, pOffset, pSize); } -static void __nvoc_thunk_RsResource_profilerBaseAddAdditionalDependants(struct RsClient *pClient, struct ProfilerBase *pResource, RsResourceRef *pReference) { - resAddAdditionalDependants(pClient, (struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_ProfilerBase_RsResource.offset), pReference); +static NV_STATUS __nvoc_thunk_GpuResource_profilerBaseInternalControlForward(struct ProfilerBase *pGpuResource, NvU32 command, void *pParams, NvU32 size) { + return gpuresInternalControlForward((struct GpuResource *)(((unsigned char *)pGpuResource) + __nvoc_rtti_ProfilerBase_GpuResource.offset), command, pParams, size); } -static NvU32 __nvoc_thunk_RsResource_profilerBaseGetRefCount(struct ProfilerBase *pResource) { - return resGetRefCount((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_ProfilerBase_RsResource.offset)); +static NV_STATUS __nvoc_thunk_RsResource_profilerBaseUnmapFrom(struct ProfilerBase *pResource, RS_RES_UNMAP_FROM_PARAMS *pParams) { + return resUnmapFrom((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_ProfilerBase_RsResource.offset), pParams); } -static NV_STATUS __nvoc_thunk_RmResource_profilerBaseCheckMemInterUnmap(struct ProfilerBase *pRmResource, NvBool bSubdeviceHandleProvided) { - return rmresCheckMemInterUnmap((struct RmResource *)(((unsigned char *)pRmResource) + __nvoc_rtti_ProfilerBase_RmResource.offset), bSubdeviceHandleProvided); +static void __nvoc_thunk_RmResource_profilerBaseControl_Epilogue(struct ProfilerBase *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + rmresControl_Epilogue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_ProfilerBase_RmResource.offset), pCallContext, pParams); } -static NV_STATUS __nvoc_thunk_RsResource_profilerBaseMapTo(struct ProfilerBase *pResource, RS_RES_MAP_TO_PARAMS *pParams) { - return resMapTo((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_ProfilerBase_RsResource.offset), pParams); +static NV_STATUS __nvoc_thunk_RsResource_profilerBaseControlLookup(struct ProfilerBase *pResource, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams, const struct NVOC_EXPORTED_METHOD_DEF **ppEntry) { + return resControlLookup((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_ProfilerBase_RsResource.offset), pParams, ppEntry); } -static NV_STATUS __nvoc_thunk_RmResource_profilerBaseControl_Prologue(struct ProfilerBase *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { - return rmresControl_Prologue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_ProfilerBase_RmResource.offset), pCallContext, pParams); +static NvHandle __nvoc_thunk_GpuResource_profilerBaseGetInternalObjectHandle(struct ProfilerBase *pGpuResource) { + return gpuresGetInternalObjectHandle((struct GpuResource *)(((unsigned char *)pGpuResource) + __nvoc_rtti_ProfilerBase_GpuResource.offset)); } -static NV_STATUS __nvoc_thunk_GpuResource_profilerBaseGetRegBaseOffsetAndSize(struct ProfilerBase *pGpuResource, struct OBJGPU *pGpu, NvU32 *pOffset, NvU32 *pSize) { - return gpuresGetRegBaseOffsetAndSize((struct GpuResource *)(((unsigned char *)pGpuResource) + __nvoc_rtti_ProfilerBase_GpuResource.offset), pGpu, pOffset, pSize); +static NV_STATUS __nvoc_thunk_GpuResource_profilerBaseControl(struct ProfilerBase *pGpuResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return gpuresControl((struct GpuResource *)(((unsigned char *)pGpuResource) + __nvoc_rtti_ProfilerBase_GpuResource.offset), pCallContext, pParams); } -static NvBool __nvoc_thunk_RsResource_profilerBaseCanCopy(struct ProfilerBase *pResource) { - return resCanCopy((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_ProfilerBase_RsResource.offset)); +static NV_STATUS __nvoc_thunk_GpuResource_profilerBaseUnmap(struct ProfilerBase *pGpuResource, struct CALL_CONTEXT *pCallContext, struct RsCpuMapping *pCpuMapping) { + return gpuresUnmap((struct GpuResource *)(((unsigned char *)pGpuResource) + __nvoc_rtti_ProfilerBase_GpuResource.offset), pCallContext, pCpuMapping); } -static NV_STATUS __nvoc_thunk_GpuResource_profilerBaseInternalControlForward(struct ProfilerBase *pGpuResource, NvU32 command, void *pParams, NvU32 size) { - return gpuresInternalControlForward((struct GpuResource *)(((unsigned char *)pGpuResource) + __nvoc_rtti_ProfilerBase_GpuResource.offset), command, pParams, size); +static NV_STATUS __nvoc_thunk_RmResource_profilerBaseGetMemInterMapParams(struct ProfilerBase *pRmResource, RMRES_MEM_INTER_MAP_PARAMS *pParams) { + return rmresGetMemInterMapParams((struct RmResource *)(((unsigned char *)pRmResource) + __nvoc_rtti_ProfilerBase_RmResource.offset), pParams); } -static void __nvoc_thunk_RsResource_profilerBasePreDestruct(struct ProfilerBase *pResource) { - resPreDestruct((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_ProfilerBase_RsResource.offset)); +static NV_STATUS __nvoc_thunk_RmResource_profilerBaseGetMemoryMappingDescriptor(struct ProfilerBase *pRmResource, struct MEMORY_DESCRIPTOR **ppMemDesc) { + return rmresGetMemoryMappingDescriptor((struct RmResource *)(((unsigned char *)pRmResource) + __nvoc_rtti_ProfilerBase_RmResource.offset), ppMemDesc); } -static NV_STATUS __nvoc_thunk_RsResource_profilerBaseUnmapFrom(struct ProfilerBase *pResource, RS_RES_UNMAP_FROM_PARAMS *pParams) { - return resUnmapFrom((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_ProfilerBase_RsResource.offset), pParams); +static NV_STATUS __nvoc_thunk_RsResource_profilerBaseControlFilter(struct ProfilerBase *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return resControlFilter((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_ProfilerBase_RsResource.offset), pCallContext, pParams); } -static NV_STATUS __nvoc_thunk_RsResource_profilerBaseIsDuplicate(struct ProfilerBase *pResource, NvHandle hMemory, NvBool *pDuplicate) { - return resIsDuplicate((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_ProfilerBase_RsResource.offset), hMemory, pDuplicate); +static NV_STATUS __nvoc_thunk_RmResource_profilerBaseControlSerialization_Prologue(struct ProfilerBase *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return rmresControlSerialization_Prologue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_ProfilerBase_RmResource.offset), pCallContext, pParams); } -static void __nvoc_thunk_RmResource_profilerBaseControl_Epilogue(struct ProfilerBase *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { - rmresControl_Epilogue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_ProfilerBase_RmResource.offset), pCallContext, pParams); +static NvBool __nvoc_thunk_RsResource_profilerBaseCanCopy(struct ProfilerBase *pResource) { + return resCanCopy((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_ProfilerBase_RsResource.offset)); } -static NV_STATUS __nvoc_thunk_RsResource_profilerBaseControlLookup(struct ProfilerBase *pResource, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams, const struct NVOC_EXPORTED_METHOD_DEF **ppEntry) { - return resControlLookup((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_ProfilerBase_RsResource.offset), pParams, ppEntry); +static void __nvoc_thunk_RsResource_profilerBasePreDestruct(struct ProfilerBase *pResource) { + resPreDestruct((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_ProfilerBase_RsResource.offset)); +} + +static NV_STATUS __nvoc_thunk_RsResource_profilerBaseIsDuplicate(struct ProfilerBase *pResource, NvHandle hMemory, NvBool *pDuplicate) { + return resIsDuplicate((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_ProfilerBase_RsResource.offset), hMemory, pDuplicate); +} + +static void __nvoc_thunk_RmResource_profilerBaseControlSerialization_Epilogue(struct ProfilerBase *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + rmresControlSerialization_Epilogue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_ProfilerBase_RmResource.offset), pCallContext, pParams); } static NV_STATUS __nvoc_thunk_GpuResource_profilerBaseMap(struct ProfilerBase *pGpuResource, struct CALL_CONTEXT *pCallContext, struct RS_CPU_MAP_PARAMS *pParams, struct RsCpuMapping *pCpuMapping) { @@ -417,21 +425,66 @@ #endif }, { /* [15] */ -#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x610u) +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) /*pFunc=*/ (void (*)(void)) NULL, #else - /*pFunc=*/ (void (*)(void)) profilerBaseCtrlCmdInternalAllocPmaStream_IMPL, -#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x610u) - /*flags=*/ 0x610u, + /*pFunc=*/ (void (*)(void)) profilerBaseCtrlCmdReserveHes_IMPL, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) + /*flags=*/ 0x210u, /*accessRight=*/0x0u, - /*methodId=*/ 0xb0cc0200u, - /*paramSize=*/ sizeof(NVB0CC_CTRL_ALLOC_PMA_STREAM_PARAMS), + /*methodId=*/ 0xb0cc0113u, + /*paramSize=*/ sizeof(NVB0CC_CTRL_RESERVE_HES_PARAMS), /*pClassInfo=*/ &(__nvoc_class_def_ProfilerBase.classInfo), #if NV_PRINTF_STRINGS_ALLOWED - /*func=*/ "profilerBaseCtrlCmdInternalAllocPmaStream" + /*func=*/ "profilerBaseCtrlCmdReserveHes" #endif }, { /* [16] */ +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) + /*pFunc=*/ (void (*)(void)) NULL, +#else + /*pFunc=*/ (void (*)(void)) profilerBaseCtrlCmdReleaseHes_IMPL, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) + /*flags=*/ 0x210u, + /*accessRight=*/0x0u, + /*methodId=*/ 0xb0cc0114u, + /*paramSize=*/ sizeof(NVB0CC_CTRL_RELEASE_HES_PARAMS), + /*pClassInfo=*/ &(__nvoc_class_def_ProfilerBase.classInfo), +#if NV_PRINTF_STRINGS_ALLOWED + /*func=*/ "profilerBaseCtrlCmdReleaseHes" +#endif + }, + { /* [17] */ +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) + /*pFunc=*/ (void (*)(void)) NULL, +#else + /*pFunc=*/ (void (*)(void)) profilerBaseCtrlCmdDisableDynamicMMABoost_IMPL, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) + /*flags=*/ 0x210u, + /*accessRight=*/0x0u, + /*methodId=*/ 0xb0cc0117u, + /*paramSize=*/ sizeof(NVB0CC_CTRL_DISABLE_DYNAMIC_MMA_BOOST_PARAMS), + /*pClassInfo=*/ &(__nvoc_class_def_ProfilerBase.classInfo), +#if NV_PRINTF_STRINGS_ALLOWED + /*func=*/ "profilerBaseCtrlCmdDisableDynamicMMABoost" +#endif + }, + { /* [18] */ +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) + /*pFunc=*/ (void (*)(void)) NULL, +#else + /*pFunc=*/ (void (*)(void)) profilerBaseCtrlCmdGetDynamicMMABoostStatus_IMPL, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) + /*flags=*/ 0x210u, + /*accessRight=*/0x0u, + /*methodId=*/ 0xb0cc0118u, + /*paramSize=*/ sizeof(NVB0CC_CTRL_GET_DYNAMIC_MMA_BOOST_STATUS_PARAMS), + /*pClassInfo=*/ &(__nvoc_class_def_ProfilerBase.classInfo), +#if NV_PRINTF_STRINGS_ALLOWED + /*func=*/ "profilerBaseCtrlCmdGetDynamicMMABoostStatus" +#endif + }, + { /* [19] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x610u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -446,7 +499,22 @@ /*func=*/ "profilerBaseCtrlCmdInternalPermissionsInit" #endif }, - { /* [17] */ + { /* [20] */ +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x610u) + /*pFunc=*/ (void (*)(void)) NULL, +#else + /*pFunc=*/ (void (*)(void)) profilerBaseCtrlCmdInternalAllocPmaStream_IMPL, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x610u) + /*flags=*/ 0x610u, + /*accessRight=*/0x0u, + /*methodId=*/ 0xb0cc0204u, + /*paramSize=*/ sizeof(NVB0CC_CTRL_INTERNAL_ALLOC_PMA_STREAM_PARAMS), + /*pClassInfo=*/ &(__nvoc_class_def_ProfilerBase.classInfo), +#if NV_PRINTF_STRINGS_ALLOWED + /*func=*/ "profilerBaseCtrlCmdInternalAllocPmaStream" +#endif + }, + { /* [21] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x610u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -461,7 +529,7 @@ /*func=*/ "profilerBaseCtrlCmdInternalFreePmaStream" #endif }, - { /* [18] */ + { /* [22] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x610u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -476,7 +544,7 @@ /*func=*/ "profilerBaseCtrlCmdInternalGetMaxPmas" #endif }, - { /* [19] */ + { /* [23] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x610u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -491,7 +559,7 @@ /*func=*/ "profilerBaseCtrlCmdInternalBindPmResources" #endif }, - { /* [20] */ + { /* [24] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x610u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -506,7 +574,7 @@ /*func=*/ "profilerBaseCtrlCmdInternalUnbindPmResources" #endif }, - { /* [21] */ + { /* [25] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x610u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -521,12 +589,42 @@ /*func=*/ "profilerBaseCtrlCmdInternalReserveHwpmLegacy" #endif }, + { /* [26] */ +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) + /*pFunc=*/ (void (*)(void)) NULL, +#else + /*pFunc=*/ (void (*)(void)) profilerBaseCtrlCmdRequestCgControls_IMPL, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) + /*flags=*/ 0x210u, + /*accessRight=*/0x0u, + /*methodId=*/ 0xb0cc0301u, + /*paramSize=*/ sizeof(NVB0CC_CTRL_POWER_REQUEST_FEATURES_PARAMS), + /*pClassInfo=*/ &(__nvoc_class_def_ProfilerBase.classInfo), +#if NV_PRINTF_STRINGS_ALLOWED + /*func=*/ "profilerBaseCtrlCmdRequestCgControls" +#endif + }, + { /* [27] */ +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) + /*pFunc=*/ (void (*)(void)) NULL, +#else + /*pFunc=*/ (void (*)(void)) profilerBaseCtrlCmdReleaseCgControls_IMPL, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) + /*flags=*/ 0x210u, + /*accessRight=*/0x0u, + /*methodId=*/ 0xb0cc0302u, + /*paramSize=*/ sizeof(NVB0CC_CTRL_POWER_RELEASE_FEATURES_PARAMS), + /*pClassInfo=*/ &(__nvoc_class_def_ProfilerBase.classInfo), +#if NV_PRINTF_STRINGS_ALLOWED + /*func=*/ "profilerBaseCtrlCmdReleaseCgControls" +#endif + }, }; const struct NVOC_EXPORT_INFO __nvoc_export_info_ProfilerBase = { - /*numEntries=*/ 22, + /*numEntries=*/ 28, /*pExportEntries=*/ __nvoc_exported_method_def_ProfilerBase }; @@ -661,48 +759,76 @@ pThis->__profilerBaseCtrlCmdSetHsCredits__ = &profilerBaseCtrlCmdSetHsCredits_IMPL; #endif - pThis->__profilerBaseShareCallback__ = &__nvoc_thunk_GpuResource_profilerBaseShareCallback; +#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) + pThis->__profilerBaseCtrlCmdReserveHes__ = &profilerBaseCtrlCmdReserveHes_IMPL; +#endif - pThis->__profilerBaseControl__ = &__nvoc_thunk_GpuResource_profilerBaseControl; +#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) + pThis->__profilerBaseCtrlCmdReleaseHes__ = &profilerBaseCtrlCmdReleaseHes_IMPL; +#endif - pThis->__profilerBaseUnmap__ = &__nvoc_thunk_GpuResource_profilerBaseUnmap; +#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) + pThis->__profilerBaseCtrlCmdRequestCgControls__ = &profilerBaseCtrlCmdRequestCgControls_IMPL; +#endif - pThis->__profilerBaseGetMemInterMapParams__ = &__nvoc_thunk_RmResource_profilerBaseGetMemInterMapParams; +#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) + pThis->__profilerBaseCtrlCmdReleaseCgControls__ = &profilerBaseCtrlCmdReleaseCgControls_IMPL; +#endif - pThis->__profilerBaseGetMemoryMappingDescriptor__ = &__nvoc_thunk_RmResource_profilerBaseGetMemoryMappingDescriptor; +#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) + pThis->__profilerBaseCtrlCmdDisableDynamicMMABoost__ = &profilerBaseCtrlCmdDisableDynamicMMABoost_IMPL; +#endif - pThis->__profilerBaseGetMapAddrSpace__ = &__nvoc_thunk_GpuResource_profilerBaseGetMapAddrSpace; +#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) + pThis->__profilerBaseCtrlCmdGetDynamicMMABoostStatus__ = &profilerBaseCtrlCmdGetDynamicMMABoostStatus_IMPL; +#endif - pThis->__profilerBaseGetInternalObjectHandle__ = &__nvoc_thunk_GpuResource_profilerBaseGetInternalObjectHandle; + pThis->__profilerBaseShareCallback__ = &__nvoc_thunk_GpuResource_profilerBaseShareCallback; - pThis->__profilerBaseControlFilter__ = &__nvoc_thunk_RsResource_profilerBaseControlFilter; + pThis->__profilerBaseCheckMemInterUnmap__ = &__nvoc_thunk_RmResource_profilerBaseCheckMemInterUnmap; - pThis->__profilerBaseAddAdditionalDependants__ = &__nvoc_thunk_RsResource_profilerBaseAddAdditionalDependants; + pThis->__profilerBaseMapTo__ = &__nvoc_thunk_RsResource_profilerBaseMapTo; - pThis->__profilerBaseGetRefCount__ = &__nvoc_thunk_RsResource_profilerBaseGetRefCount; + pThis->__profilerBaseGetMapAddrSpace__ = &__nvoc_thunk_GpuResource_profilerBaseGetMapAddrSpace; - pThis->__profilerBaseCheckMemInterUnmap__ = &__nvoc_thunk_RmResource_profilerBaseCheckMemInterUnmap; + pThis->__profilerBaseGetRefCount__ = &__nvoc_thunk_RsResource_profilerBaseGetRefCount; - pThis->__profilerBaseMapTo__ = &__nvoc_thunk_RsResource_profilerBaseMapTo; + pThis->__profilerBaseAddAdditionalDependants__ = &__nvoc_thunk_RsResource_profilerBaseAddAdditionalDependants; pThis->__profilerBaseControl_Prologue__ = &__nvoc_thunk_RmResource_profilerBaseControl_Prologue; pThis->__profilerBaseGetRegBaseOffsetAndSize__ = &__nvoc_thunk_GpuResource_profilerBaseGetRegBaseOffsetAndSize; - pThis->__profilerBaseCanCopy__ = &__nvoc_thunk_RsResource_profilerBaseCanCopy; - pThis->__profilerBaseInternalControlForward__ = &__nvoc_thunk_GpuResource_profilerBaseInternalControlForward; - pThis->__profilerBasePreDestruct__ = &__nvoc_thunk_RsResource_profilerBasePreDestruct; - pThis->__profilerBaseUnmapFrom__ = &__nvoc_thunk_RsResource_profilerBaseUnmapFrom; - pThis->__profilerBaseIsDuplicate__ = &__nvoc_thunk_RsResource_profilerBaseIsDuplicate; - pThis->__profilerBaseControl_Epilogue__ = &__nvoc_thunk_RmResource_profilerBaseControl_Epilogue; pThis->__profilerBaseControlLookup__ = &__nvoc_thunk_RsResource_profilerBaseControlLookup; + pThis->__profilerBaseGetInternalObjectHandle__ = &__nvoc_thunk_GpuResource_profilerBaseGetInternalObjectHandle; + + pThis->__profilerBaseControl__ = &__nvoc_thunk_GpuResource_profilerBaseControl; + + pThis->__profilerBaseUnmap__ = &__nvoc_thunk_GpuResource_profilerBaseUnmap; + + pThis->__profilerBaseGetMemInterMapParams__ = &__nvoc_thunk_RmResource_profilerBaseGetMemInterMapParams; + + pThis->__profilerBaseGetMemoryMappingDescriptor__ = &__nvoc_thunk_RmResource_profilerBaseGetMemoryMappingDescriptor; + + pThis->__profilerBaseControlFilter__ = &__nvoc_thunk_RsResource_profilerBaseControlFilter; + + pThis->__profilerBaseControlSerialization_Prologue__ = &__nvoc_thunk_RmResource_profilerBaseControlSerialization_Prologue; + + pThis->__profilerBaseCanCopy__ = &__nvoc_thunk_RsResource_profilerBaseCanCopy; + + pThis->__profilerBasePreDestruct__ = &__nvoc_thunk_RsResource_profilerBasePreDestruct; + + pThis->__profilerBaseIsDuplicate__ = &__nvoc_thunk_RsResource_profilerBaseIsDuplicate; + + pThis->__profilerBaseControlSerialization_Epilogue__ = &__nvoc_thunk_RmResource_profilerBaseControlSerialization_Epilogue; + pThis->__profilerBaseMap__ = &__nvoc_thunk_GpuResource_profilerBaseMap; pThis->__profilerBaseAccessCallback__ = &__nvoc_thunk_RmResource_profilerBaseAccessCallback; @@ -730,13 +856,16 @@ ProfilerBase *pThis; RmHalspecOwner *pRmhalspecowner; - pThis = portMemAllocNonPaged(sizeof(ProfilerBase)); - if (pThis == NULL) return NV_ERR_NO_MEMORY; + status = __nvoc_handleObjCreateMemAlloc(createFlags, sizeof(ProfilerBase), (void**)&pThis, (void**)ppThis); + if (status != NV_OK) + return status; portMemSet(pThis, 0, sizeof(ProfilerBase)); __nvoc_initRtti(staticCast(pThis, Dynamic), &__nvoc_class_def_ProfilerBase); + pThis->__nvoc_base_GpuResource.__nvoc_base_RmResource.__nvoc_base_RsResource.__nvoc_base_Object.createFlags = createFlags; + if (pParent != NULL && !(createFlags & NVOC_OBJ_CREATE_FLAGS_PARENT_HALSPEC_ONLY)) { pParentObj = dynamicCast(pParent, Object); @@ -756,11 +885,17 @@ if (status != NV_OK) goto __nvoc_objCreate_ProfilerBase_cleanup; *ppThis = pThis; + return NV_OK; __nvoc_objCreate_ProfilerBase_cleanup: // do not call destructors here since the constructor already called them - portMemFree(pThis); + if (createFlags & NVOC_OBJ_CREATE_FLAGS_IN_PLACE_CONSTRUCT) + portMemSet(pThis, 0, sizeof(ProfilerBase)); + else + portMemFree(pThis); + + // coverity[leaked_storage:FALSE] return status; } @@ -873,84 +1008,92 @@ return gpuresShareCallback((struct GpuResource *)(((unsigned char *)pGpuResource) + __nvoc_rtti_ProfilerDev_GpuResource.offset), pInvokingClient, pParentRef, pSharePolicy); } -static NV_STATUS __nvoc_thunk_GpuResource_profilerDevControl(struct ProfilerDev *pGpuResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { - return gpuresControl((struct GpuResource *)(((unsigned char *)pGpuResource) + __nvoc_rtti_ProfilerDev_GpuResource.offset), pCallContext, pParams); +static NV_STATUS __nvoc_thunk_RmResource_profilerDevCheckMemInterUnmap(struct ProfilerDev *pRmResource, NvBool bSubdeviceHandleProvided) { + return rmresCheckMemInterUnmap((struct RmResource *)(((unsigned char *)pRmResource) + __nvoc_rtti_ProfilerDev_RmResource.offset), bSubdeviceHandleProvided); } -static NV_STATUS __nvoc_thunk_GpuResource_profilerDevUnmap(struct ProfilerDev *pGpuResource, struct CALL_CONTEXT *pCallContext, struct RsCpuMapping *pCpuMapping) { - return gpuresUnmap((struct GpuResource *)(((unsigned char *)pGpuResource) + __nvoc_rtti_ProfilerDev_GpuResource.offset), pCallContext, pCpuMapping); +static NV_STATUS __nvoc_thunk_RsResource_profilerDevMapTo(struct ProfilerDev *pResource, RS_RES_MAP_TO_PARAMS *pParams) { + return resMapTo((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_ProfilerDev_RsResource.offset), pParams); } -static NV_STATUS __nvoc_thunk_RmResource_profilerDevGetMemInterMapParams(struct ProfilerDev *pRmResource, RMRES_MEM_INTER_MAP_PARAMS *pParams) { - return rmresGetMemInterMapParams((struct RmResource *)(((unsigned char *)pRmResource) + __nvoc_rtti_ProfilerDev_RmResource.offset), pParams); +static NV_STATUS __nvoc_thunk_GpuResource_profilerDevGetMapAddrSpace(struct ProfilerDev *pGpuResource, struct CALL_CONTEXT *pCallContext, NvU32 mapFlags, NV_ADDRESS_SPACE *pAddrSpace) { + return gpuresGetMapAddrSpace((struct GpuResource *)(((unsigned char *)pGpuResource) + __nvoc_rtti_ProfilerDev_GpuResource.offset), pCallContext, mapFlags, pAddrSpace); } -static NV_STATUS __nvoc_thunk_RmResource_profilerDevGetMemoryMappingDescriptor(struct ProfilerDev *pRmResource, struct MEMORY_DESCRIPTOR **ppMemDesc) { - return rmresGetMemoryMappingDescriptor((struct RmResource *)(((unsigned char *)pRmResource) + __nvoc_rtti_ProfilerDev_RmResource.offset), ppMemDesc); +static NvU32 __nvoc_thunk_RsResource_profilerDevGetRefCount(struct ProfilerDev *pResource) { + return resGetRefCount((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_ProfilerDev_RsResource.offset)); } -static NV_STATUS __nvoc_thunk_GpuResource_profilerDevGetMapAddrSpace(struct ProfilerDev *pGpuResource, struct CALL_CONTEXT *pCallContext, NvU32 mapFlags, NV_ADDRESS_SPACE *pAddrSpace) { - return gpuresGetMapAddrSpace((struct GpuResource *)(((unsigned char *)pGpuResource) + __nvoc_rtti_ProfilerDev_GpuResource.offset), pCallContext, mapFlags, pAddrSpace); +static void __nvoc_thunk_RsResource_profilerDevAddAdditionalDependants(struct RsClient *pClient, struct ProfilerDev *pResource, RsResourceRef *pReference) { + resAddAdditionalDependants(pClient, (struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_ProfilerDev_RsResource.offset), pReference); } -static NvHandle __nvoc_thunk_GpuResource_profilerDevGetInternalObjectHandle(struct ProfilerDev *pGpuResource) { - return gpuresGetInternalObjectHandle((struct GpuResource *)(((unsigned char *)pGpuResource) + __nvoc_rtti_ProfilerDev_GpuResource.offset)); +static NV_STATUS __nvoc_thunk_RmResource_profilerDevControl_Prologue(struct ProfilerDev *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return rmresControl_Prologue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_ProfilerDev_RmResource.offset), pCallContext, pParams); } -static NV_STATUS __nvoc_thunk_RsResource_profilerDevControlFilter(struct ProfilerDev *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { - return resControlFilter((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_ProfilerDev_RsResource.offset), pCallContext, pParams); +static NV_STATUS __nvoc_thunk_GpuResource_profilerDevGetRegBaseOffsetAndSize(struct ProfilerDev *pGpuResource, struct OBJGPU *pGpu, NvU32 *pOffset, NvU32 *pSize) { + return gpuresGetRegBaseOffsetAndSize((struct GpuResource *)(((unsigned char *)pGpuResource) + __nvoc_rtti_ProfilerDev_GpuResource.offset), pGpu, pOffset, pSize); } -static void __nvoc_thunk_RsResource_profilerDevAddAdditionalDependants(struct RsClient *pClient, struct ProfilerDev *pResource, RsResourceRef *pReference) { - resAddAdditionalDependants(pClient, (struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_ProfilerDev_RsResource.offset), pReference); +static NV_STATUS __nvoc_thunk_GpuResource_profilerDevInternalControlForward(struct ProfilerDev *pGpuResource, NvU32 command, void *pParams, NvU32 size) { + return gpuresInternalControlForward((struct GpuResource *)(((unsigned char *)pGpuResource) + __nvoc_rtti_ProfilerDev_GpuResource.offset), command, pParams, size); } -static NvU32 __nvoc_thunk_RsResource_profilerDevGetRefCount(struct ProfilerDev *pResource) { - return resGetRefCount((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_ProfilerDev_RsResource.offset)); +static NV_STATUS __nvoc_thunk_RsResource_profilerDevUnmapFrom(struct ProfilerDev *pResource, RS_RES_UNMAP_FROM_PARAMS *pParams) { + return resUnmapFrom((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_ProfilerDev_RsResource.offset), pParams); } -static NV_STATUS __nvoc_thunk_RmResource_profilerDevCheckMemInterUnmap(struct ProfilerDev *pRmResource, NvBool bSubdeviceHandleProvided) { - return rmresCheckMemInterUnmap((struct RmResource *)(((unsigned char *)pRmResource) + __nvoc_rtti_ProfilerDev_RmResource.offset), bSubdeviceHandleProvided); +static void __nvoc_thunk_RmResource_profilerDevControl_Epilogue(struct ProfilerDev *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + rmresControl_Epilogue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_ProfilerDev_RmResource.offset), pCallContext, pParams); } -static NV_STATUS __nvoc_thunk_RsResource_profilerDevMapTo(struct ProfilerDev *pResource, RS_RES_MAP_TO_PARAMS *pParams) { - return resMapTo((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_ProfilerDev_RsResource.offset), pParams); +static NV_STATUS __nvoc_thunk_RsResource_profilerDevControlLookup(struct ProfilerDev *pResource, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams, const struct NVOC_EXPORTED_METHOD_DEF **ppEntry) { + return resControlLookup((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_ProfilerDev_RsResource.offset), pParams, ppEntry); } -static NV_STATUS __nvoc_thunk_RmResource_profilerDevControl_Prologue(struct ProfilerDev *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { - return rmresControl_Prologue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_ProfilerDev_RmResource.offset), pCallContext, pParams); +static NvHandle __nvoc_thunk_GpuResource_profilerDevGetInternalObjectHandle(struct ProfilerDev *pGpuResource) { + return gpuresGetInternalObjectHandle((struct GpuResource *)(((unsigned char *)pGpuResource) + __nvoc_rtti_ProfilerDev_GpuResource.offset)); } -static NV_STATUS __nvoc_thunk_GpuResource_profilerDevGetRegBaseOffsetAndSize(struct ProfilerDev *pGpuResource, struct OBJGPU *pGpu, NvU32 *pOffset, NvU32 *pSize) { - return gpuresGetRegBaseOffsetAndSize((struct GpuResource *)(((unsigned char *)pGpuResource) + __nvoc_rtti_ProfilerDev_GpuResource.offset), pGpu, pOffset, pSize); +static NV_STATUS __nvoc_thunk_GpuResource_profilerDevControl(struct ProfilerDev *pGpuResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return gpuresControl((struct GpuResource *)(((unsigned char *)pGpuResource) + __nvoc_rtti_ProfilerDev_GpuResource.offset), pCallContext, pParams); } -static NvBool __nvoc_thunk_RsResource_profilerDevCanCopy(struct ProfilerDev *pResource) { - return resCanCopy((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_ProfilerDev_RsResource.offset)); +static NV_STATUS __nvoc_thunk_GpuResource_profilerDevUnmap(struct ProfilerDev *pGpuResource, struct CALL_CONTEXT *pCallContext, struct RsCpuMapping *pCpuMapping) { + return gpuresUnmap((struct GpuResource *)(((unsigned char *)pGpuResource) + __nvoc_rtti_ProfilerDev_GpuResource.offset), pCallContext, pCpuMapping); } -static NV_STATUS __nvoc_thunk_GpuResource_profilerDevInternalControlForward(struct ProfilerDev *pGpuResource, NvU32 command, void *pParams, NvU32 size) { - return gpuresInternalControlForward((struct GpuResource *)(((unsigned char *)pGpuResource) + __nvoc_rtti_ProfilerDev_GpuResource.offset), command, pParams, size); +static NV_STATUS __nvoc_thunk_RmResource_profilerDevGetMemInterMapParams(struct ProfilerDev *pRmResource, RMRES_MEM_INTER_MAP_PARAMS *pParams) { + return rmresGetMemInterMapParams((struct RmResource *)(((unsigned char *)pRmResource) + __nvoc_rtti_ProfilerDev_RmResource.offset), pParams); } -static void __nvoc_thunk_RsResource_profilerDevPreDestruct(struct ProfilerDev *pResource) { - resPreDestruct((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_ProfilerDev_RsResource.offset)); +static NV_STATUS __nvoc_thunk_RmResource_profilerDevGetMemoryMappingDescriptor(struct ProfilerDev *pRmResource, struct MEMORY_DESCRIPTOR **ppMemDesc) { + return rmresGetMemoryMappingDescriptor((struct RmResource *)(((unsigned char *)pRmResource) + __nvoc_rtti_ProfilerDev_RmResource.offset), ppMemDesc); } -static NV_STATUS __nvoc_thunk_RsResource_profilerDevUnmapFrom(struct ProfilerDev *pResource, RS_RES_UNMAP_FROM_PARAMS *pParams) { - return resUnmapFrom((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_ProfilerDev_RsResource.offset), pParams); +static NV_STATUS __nvoc_thunk_RsResource_profilerDevControlFilter(struct ProfilerDev *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return resControlFilter((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_ProfilerDev_RsResource.offset), pCallContext, pParams); } -static NV_STATUS __nvoc_thunk_RsResource_profilerDevIsDuplicate(struct ProfilerDev *pResource, NvHandle hMemory, NvBool *pDuplicate) { - return resIsDuplicate((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_ProfilerDev_RsResource.offset), hMemory, pDuplicate); +static NV_STATUS __nvoc_thunk_RmResource_profilerDevControlSerialization_Prologue(struct ProfilerDev *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return rmresControlSerialization_Prologue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_ProfilerDev_RmResource.offset), pCallContext, pParams); } -static void __nvoc_thunk_RmResource_profilerDevControl_Epilogue(struct ProfilerDev *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { - rmresControl_Epilogue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_ProfilerDev_RmResource.offset), pCallContext, pParams); +static NvBool __nvoc_thunk_RsResource_profilerDevCanCopy(struct ProfilerDev *pResource) { + return resCanCopy((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_ProfilerDev_RsResource.offset)); } -static NV_STATUS __nvoc_thunk_RsResource_profilerDevControlLookup(struct ProfilerDev *pResource, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams, const struct NVOC_EXPORTED_METHOD_DEF **ppEntry) { - return resControlLookup((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_ProfilerDev_RsResource.offset), pParams, ppEntry); +static void __nvoc_thunk_RsResource_profilerDevPreDestruct(struct ProfilerDev *pResource) { + resPreDestruct((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_ProfilerDev_RsResource.offset)); +} + +static NV_STATUS __nvoc_thunk_RsResource_profilerDevIsDuplicate(struct ProfilerDev *pResource, NvHandle hMemory, NvBool *pDuplicate) { + return resIsDuplicate((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_ProfilerDev_RsResource.offset), hMemory, pDuplicate); +} + +static void __nvoc_thunk_RmResource_profilerDevControlSerialization_Epilogue(struct ProfilerDev *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + rmresControlSerialization_Epilogue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_ProfilerDev_RmResource.offset), pCallContext, pParams); } static NV_STATUS __nvoc_thunk_GpuResource_profilerDevMap(struct ProfilerDev *pGpuResource, struct CALL_CONTEXT *pCallContext, struct RS_CPU_MAP_PARAMS *pParams, struct RsCpuMapping *pCpuMapping) { @@ -1012,45 +1155,49 @@ pThis->__profilerDevShareCallback__ = &__nvoc_thunk_GpuResource_profilerDevShareCallback; - pThis->__profilerDevControl__ = &__nvoc_thunk_GpuResource_profilerDevControl; + pThis->__profilerDevCheckMemInterUnmap__ = &__nvoc_thunk_RmResource_profilerDevCheckMemInterUnmap; - pThis->__profilerDevUnmap__ = &__nvoc_thunk_GpuResource_profilerDevUnmap; + pThis->__profilerDevMapTo__ = &__nvoc_thunk_RsResource_profilerDevMapTo; - pThis->__profilerDevGetMemInterMapParams__ = &__nvoc_thunk_RmResource_profilerDevGetMemInterMapParams; + pThis->__profilerDevGetMapAddrSpace__ = &__nvoc_thunk_GpuResource_profilerDevGetMapAddrSpace; - pThis->__profilerDevGetMemoryMappingDescriptor__ = &__nvoc_thunk_RmResource_profilerDevGetMemoryMappingDescriptor; + pThis->__profilerDevGetRefCount__ = &__nvoc_thunk_RsResource_profilerDevGetRefCount; - pThis->__profilerDevGetMapAddrSpace__ = &__nvoc_thunk_GpuResource_profilerDevGetMapAddrSpace; + pThis->__profilerDevAddAdditionalDependants__ = &__nvoc_thunk_RsResource_profilerDevAddAdditionalDependants; - pThis->__profilerDevGetInternalObjectHandle__ = &__nvoc_thunk_GpuResource_profilerDevGetInternalObjectHandle; + pThis->__profilerDevControl_Prologue__ = &__nvoc_thunk_RmResource_profilerDevControl_Prologue; - pThis->__profilerDevControlFilter__ = &__nvoc_thunk_RsResource_profilerDevControlFilter; + pThis->__profilerDevGetRegBaseOffsetAndSize__ = &__nvoc_thunk_GpuResource_profilerDevGetRegBaseOffsetAndSize; - pThis->__profilerDevAddAdditionalDependants__ = &__nvoc_thunk_RsResource_profilerDevAddAdditionalDependants; + pThis->__profilerDevInternalControlForward__ = &__nvoc_thunk_GpuResource_profilerDevInternalControlForward; - pThis->__profilerDevGetRefCount__ = &__nvoc_thunk_RsResource_profilerDevGetRefCount; + pThis->__profilerDevUnmapFrom__ = &__nvoc_thunk_RsResource_profilerDevUnmapFrom; - pThis->__profilerDevCheckMemInterUnmap__ = &__nvoc_thunk_RmResource_profilerDevCheckMemInterUnmap; + pThis->__profilerDevControl_Epilogue__ = &__nvoc_thunk_RmResource_profilerDevControl_Epilogue; - pThis->__profilerDevMapTo__ = &__nvoc_thunk_RsResource_profilerDevMapTo; + pThis->__profilerDevControlLookup__ = &__nvoc_thunk_RsResource_profilerDevControlLookup; - pThis->__profilerDevControl_Prologue__ = &__nvoc_thunk_RmResource_profilerDevControl_Prologue; + pThis->__profilerDevGetInternalObjectHandle__ = &__nvoc_thunk_GpuResource_profilerDevGetInternalObjectHandle; - pThis->__profilerDevGetRegBaseOffsetAndSize__ = &__nvoc_thunk_GpuResource_profilerDevGetRegBaseOffsetAndSize; + pThis->__profilerDevControl__ = &__nvoc_thunk_GpuResource_profilerDevControl; - pThis->__profilerDevCanCopy__ = &__nvoc_thunk_RsResource_profilerDevCanCopy; + pThis->__profilerDevUnmap__ = &__nvoc_thunk_GpuResource_profilerDevUnmap; - pThis->__profilerDevInternalControlForward__ = &__nvoc_thunk_GpuResource_profilerDevInternalControlForward; + pThis->__profilerDevGetMemInterMapParams__ = &__nvoc_thunk_RmResource_profilerDevGetMemInterMapParams; - pThis->__profilerDevPreDestruct__ = &__nvoc_thunk_RsResource_profilerDevPreDestruct; + pThis->__profilerDevGetMemoryMappingDescriptor__ = &__nvoc_thunk_RmResource_profilerDevGetMemoryMappingDescriptor; - pThis->__profilerDevUnmapFrom__ = &__nvoc_thunk_RsResource_profilerDevUnmapFrom; + pThis->__profilerDevControlFilter__ = &__nvoc_thunk_RsResource_profilerDevControlFilter; - pThis->__profilerDevIsDuplicate__ = &__nvoc_thunk_RsResource_profilerDevIsDuplicate; + pThis->__profilerDevControlSerialization_Prologue__ = &__nvoc_thunk_RmResource_profilerDevControlSerialization_Prologue; - pThis->__profilerDevControl_Epilogue__ = &__nvoc_thunk_RmResource_profilerDevControl_Epilogue; + pThis->__profilerDevCanCopy__ = &__nvoc_thunk_RsResource_profilerDevCanCopy; - pThis->__profilerDevControlLookup__ = &__nvoc_thunk_RsResource_profilerDevControlLookup; + pThis->__profilerDevPreDestruct__ = &__nvoc_thunk_RsResource_profilerDevPreDestruct; + + pThis->__profilerDevIsDuplicate__ = &__nvoc_thunk_RsResource_profilerDevIsDuplicate; + + pThis->__profilerDevControlSerialization_Epilogue__ = &__nvoc_thunk_RmResource_profilerDevControlSerialization_Epilogue; pThis->__profilerDevMap__ = &__nvoc_thunk_GpuResource_profilerDevMap; @@ -1080,13 +1227,16 @@ ProfilerDev *pThis; RmHalspecOwner *pRmhalspecowner; - pThis = portMemAllocNonPaged(sizeof(ProfilerDev)); - if (pThis == NULL) return NV_ERR_NO_MEMORY; + status = __nvoc_handleObjCreateMemAlloc(createFlags, sizeof(ProfilerDev), (void**)&pThis, (void**)ppThis); + if (status != NV_OK) + return status; portMemSet(pThis, 0, sizeof(ProfilerDev)); __nvoc_initRtti(staticCast(pThis, Dynamic), &__nvoc_class_def_ProfilerDev); + pThis->__nvoc_base_ProfilerBase.__nvoc_base_GpuResource.__nvoc_base_RmResource.__nvoc_base_RsResource.__nvoc_base_Object.createFlags = createFlags; + if (pParent != NULL && !(createFlags & NVOC_OBJ_CREATE_FLAGS_PARENT_HALSPEC_ONLY)) { pParentObj = dynamicCast(pParent, Object); @@ -1106,11 +1256,17 @@ if (status != NV_OK) goto __nvoc_objCreate_ProfilerDev_cleanup; *ppThis = pThis; + return NV_OK; __nvoc_objCreate_ProfilerDev_cleanup: // do not call destructors here since the constructor already called them - portMemFree(pThis); + if (createFlags & NVOC_OBJ_CREATE_FLAGS_IN_PLACE_CONSTRUCT) + portMemSet(pThis, 0, sizeof(ProfilerDev)); + else + portMemFree(pThis); + + // coverity[leaked_storage:FALSE] return status; } diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/generated/g_profiler_v2_nvoc.h nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_profiler_v2_nvoc.h --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/generated/g_profiler_v2_nvoc.h 2023-10-25 20:27:17.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_profiler_v2_nvoc.h 2024-03-05 22:18:42.000000000 +0000 @@ -7,7 +7,7 @@ #endif /* - * SPDX-FileCopyrightText: Copyright (c) 2018-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2018-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -81,34 +81,42 @@ NV_STATUS (*__profilerBaseCtrlCmdInternalUnbindPmResources__)(struct ProfilerBase *); NV_STATUS (*__profilerBaseCtrlCmdPmaStreamUpdateGetPut__)(struct ProfilerBase *, NVB0CC_CTRL_PMA_STREAM_UPDATE_GET_PUT_PARAMS *); NV_STATUS (*__profilerBaseCtrlCmdExecRegops__)(struct ProfilerBase *, NVB0CC_CTRL_EXEC_REG_OPS_PARAMS *); - NV_STATUS (*__profilerBaseCtrlCmdInternalAllocPmaStream__)(struct ProfilerBase *, NVB0CC_CTRL_ALLOC_PMA_STREAM_PARAMS *); + NV_STATUS (*__profilerBaseCtrlCmdInternalAllocPmaStream__)(struct ProfilerBase *, NVB0CC_CTRL_INTERNAL_ALLOC_PMA_STREAM_PARAMS *); NV_STATUS (*__profilerBaseCtrlCmdInternalPermissionsInit__)(struct ProfilerBase *, NVB0CC_CTRL_INTERNAL_PERMISSIONS_INIT_PARAMS *); NV_STATUS (*__profilerBaseCtrlCmdReservePmAreaPcSampler__)(struct ProfilerBase *); NV_STATUS (*__profilerBaseCtrlCmdReleasePmAreaPcSampler__)(struct ProfilerBase *); NV_STATUS (*__profilerBaseCtrlCmdGetTotalHsCredits__)(struct ProfilerBase *, NVB0CC_CTRL_GET_TOTAL_HS_CREDITS_PARAMS *); NV_STATUS (*__profilerBaseCtrlCmdGetHsCredits__)(struct ProfilerBase *, NVB0CC_CTRL_GET_HS_CREDITS_PARAMS *); NV_STATUS (*__profilerBaseCtrlCmdSetHsCredits__)(struct ProfilerBase *, NVB0CC_CTRL_SET_HS_CREDITS_PARAMS *); + NV_STATUS (*__profilerBaseCtrlCmdReserveHes__)(struct ProfilerBase *, NVB0CC_CTRL_RESERVE_HES_PARAMS *); + NV_STATUS (*__profilerBaseCtrlCmdReleaseHes__)(struct ProfilerBase *, NVB0CC_CTRL_RELEASE_HES_PARAMS *); + NV_STATUS (*__profilerBaseCtrlCmdRequestCgControls__)(struct ProfilerBase *, NVB0CC_CTRL_POWER_REQUEST_FEATURES_PARAMS *); + NV_STATUS (*__profilerBaseCtrlCmdReleaseCgControls__)(struct ProfilerBase *, NVB0CC_CTRL_POWER_RELEASE_FEATURES_PARAMS *); + NV_STATUS (*__profilerBaseCtrlCmdDisableDynamicMMABoost__)(struct ProfilerBase *, NVB0CC_CTRL_DISABLE_DYNAMIC_MMA_BOOST_PARAMS *); + NV_STATUS (*__profilerBaseCtrlCmdGetDynamicMMABoostStatus__)(struct ProfilerBase *, NVB0CC_CTRL_GET_DYNAMIC_MMA_BOOST_STATUS_PARAMS *); NvBool (*__profilerBaseShareCallback__)(struct ProfilerBase *, struct RsClient *, struct RsResourceRef *, RS_SHARE_POLICY *); - NV_STATUS (*__profilerBaseControl__)(struct ProfilerBase *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); - NV_STATUS (*__profilerBaseUnmap__)(struct ProfilerBase *, struct CALL_CONTEXT *, struct RsCpuMapping *); - NV_STATUS (*__profilerBaseGetMemInterMapParams__)(struct ProfilerBase *, RMRES_MEM_INTER_MAP_PARAMS *); - NV_STATUS (*__profilerBaseGetMemoryMappingDescriptor__)(struct ProfilerBase *, struct MEMORY_DESCRIPTOR **); - NV_STATUS (*__profilerBaseGetMapAddrSpace__)(struct ProfilerBase *, struct CALL_CONTEXT *, NvU32, NV_ADDRESS_SPACE *); - NvHandle (*__profilerBaseGetInternalObjectHandle__)(struct ProfilerBase *); - NV_STATUS (*__profilerBaseControlFilter__)(struct ProfilerBase *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); - void (*__profilerBaseAddAdditionalDependants__)(struct RsClient *, struct ProfilerBase *, RsResourceRef *); - NvU32 (*__profilerBaseGetRefCount__)(struct ProfilerBase *); NV_STATUS (*__profilerBaseCheckMemInterUnmap__)(struct ProfilerBase *, NvBool); NV_STATUS (*__profilerBaseMapTo__)(struct ProfilerBase *, RS_RES_MAP_TO_PARAMS *); + NV_STATUS (*__profilerBaseGetMapAddrSpace__)(struct ProfilerBase *, struct CALL_CONTEXT *, NvU32, NV_ADDRESS_SPACE *); + NvU32 (*__profilerBaseGetRefCount__)(struct ProfilerBase *); + void (*__profilerBaseAddAdditionalDependants__)(struct RsClient *, struct ProfilerBase *, RsResourceRef *); NV_STATUS (*__profilerBaseControl_Prologue__)(struct ProfilerBase *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); NV_STATUS (*__profilerBaseGetRegBaseOffsetAndSize__)(struct ProfilerBase *, struct OBJGPU *, NvU32 *, NvU32 *); - NvBool (*__profilerBaseCanCopy__)(struct ProfilerBase *); NV_STATUS (*__profilerBaseInternalControlForward__)(struct ProfilerBase *, NvU32, void *, NvU32); - void (*__profilerBasePreDestruct__)(struct ProfilerBase *); NV_STATUS (*__profilerBaseUnmapFrom__)(struct ProfilerBase *, RS_RES_UNMAP_FROM_PARAMS *); - NV_STATUS (*__profilerBaseIsDuplicate__)(struct ProfilerBase *, NvHandle, NvBool *); void (*__profilerBaseControl_Epilogue__)(struct ProfilerBase *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); NV_STATUS (*__profilerBaseControlLookup__)(struct ProfilerBase *, struct RS_RES_CONTROL_PARAMS_INTERNAL *, const struct NVOC_EXPORTED_METHOD_DEF **); + NvHandle (*__profilerBaseGetInternalObjectHandle__)(struct ProfilerBase *); + NV_STATUS (*__profilerBaseControl__)(struct ProfilerBase *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); + NV_STATUS (*__profilerBaseUnmap__)(struct ProfilerBase *, struct CALL_CONTEXT *, struct RsCpuMapping *); + NV_STATUS (*__profilerBaseGetMemInterMapParams__)(struct ProfilerBase *, RMRES_MEM_INTER_MAP_PARAMS *); + NV_STATUS (*__profilerBaseGetMemoryMappingDescriptor__)(struct ProfilerBase *, struct MEMORY_DESCRIPTOR **); + NV_STATUS (*__profilerBaseControlFilter__)(struct ProfilerBase *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); + NV_STATUS (*__profilerBaseControlSerialization_Prologue__)(struct ProfilerBase *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); + NvBool (*__profilerBaseCanCopy__)(struct ProfilerBase *); + void (*__profilerBasePreDestruct__)(struct ProfilerBase *); + NV_STATUS (*__profilerBaseIsDuplicate__)(struct ProfilerBase *, NvHandle, NvBool *); + void (*__profilerBaseControlSerialization_Epilogue__)(struct ProfilerBase *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); NV_STATUS (*__profilerBaseMap__)(struct ProfilerBase *, struct CALL_CONTEXT *, struct RS_CPU_MAP_PARAMS *, struct RsCpuMapping *); NvBool (*__profilerBaseAccessCallback__)(struct ProfilerBase *, struct RsClient *, void *, RsAccessRight); NvU32 maxPmaChannels; @@ -170,27 +178,35 @@ #define profilerBaseCtrlCmdGetTotalHsCredits(pProfiler, pParams) profilerBaseCtrlCmdGetTotalHsCredits_DISPATCH(pProfiler, pParams) #define profilerBaseCtrlCmdGetHsCredits(pProfiler, pParams) profilerBaseCtrlCmdGetHsCredits_DISPATCH(pProfiler, pParams) #define profilerBaseCtrlCmdSetHsCredits(pProfiler, pParams) profilerBaseCtrlCmdSetHsCredits_DISPATCH(pProfiler, pParams) +#define profilerBaseCtrlCmdReserveHes(pProfiler, pParams) profilerBaseCtrlCmdReserveHes_DISPATCH(pProfiler, pParams) +#define profilerBaseCtrlCmdReleaseHes(pProfiler, pParams) profilerBaseCtrlCmdReleaseHes_DISPATCH(pProfiler, pParams) +#define profilerBaseCtrlCmdRequestCgControls(pProfiler, pParams) profilerBaseCtrlCmdRequestCgControls_DISPATCH(pProfiler, pParams) +#define profilerBaseCtrlCmdReleaseCgControls(pProfiler, pParams) profilerBaseCtrlCmdReleaseCgControls_DISPATCH(pProfiler, pParams) +#define profilerBaseCtrlCmdDisableDynamicMMABoost(pProfiler, pParams) profilerBaseCtrlCmdDisableDynamicMMABoost_DISPATCH(pProfiler, pParams) +#define profilerBaseCtrlCmdGetDynamicMMABoostStatus(pProfiler, pParams) profilerBaseCtrlCmdGetDynamicMMABoostStatus_DISPATCH(pProfiler, pParams) #define profilerBaseShareCallback(pGpuResource, pInvokingClient, pParentRef, pSharePolicy) profilerBaseShareCallback_DISPATCH(pGpuResource, pInvokingClient, pParentRef, pSharePolicy) -#define profilerBaseControl(pGpuResource, pCallContext, pParams) profilerBaseControl_DISPATCH(pGpuResource, pCallContext, pParams) -#define profilerBaseUnmap(pGpuResource, pCallContext, pCpuMapping) profilerBaseUnmap_DISPATCH(pGpuResource, pCallContext, pCpuMapping) -#define profilerBaseGetMemInterMapParams(pRmResource, pParams) profilerBaseGetMemInterMapParams_DISPATCH(pRmResource, pParams) -#define profilerBaseGetMemoryMappingDescriptor(pRmResource, ppMemDesc) profilerBaseGetMemoryMappingDescriptor_DISPATCH(pRmResource, ppMemDesc) -#define profilerBaseGetMapAddrSpace(pGpuResource, pCallContext, mapFlags, pAddrSpace) profilerBaseGetMapAddrSpace_DISPATCH(pGpuResource, pCallContext, mapFlags, pAddrSpace) -#define profilerBaseGetInternalObjectHandle(pGpuResource) profilerBaseGetInternalObjectHandle_DISPATCH(pGpuResource) -#define profilerBaseControlFilter(pResource, pCallContext, pParams) profilerBaseControlFilter_DISPATCH(pResource, pCallContext, pParams) -#define profilerBaseAddAdditionalDependants(pClient, pResource, pReference) profilerBaseAddAdditionalDependants_DISPATCH(pClient, pResource, pReference) -#define profilerBaseGetRefCount(pResource) profilerBaseGetRefCount_DISPATCH(pResource) #define profilerBaseCheckMemInterUnmap(pRmResource, bSubdeviceHandleProvided) profilerBaseCheckMemInterUnmap_DISPATCH(pRmResource, bSubdeviceHandleProvided) #define profilerBaseMapTo(pResource, pParams) profilerBaseMapTo_DISPATCH(pResource, pParams) +#define profilerBaseGetMapAddrSpace(pGpuResource, pCallContext, mapFlags, pAddrSpace) profilerBaseGetMapAddrSpace_DISPATCH(pGpuResource, pCallContext, mapFlags, pAddrSpace) +#define profilerBaseGetRefCount(pResource) profilerBaseGetRefCount_DISPATCH(pResource) +#define profilerBaseAddAdditionalDependants(pClient, pResource, pReference) profilerBaseAddAdditionalDependants_DISPATCH(pClient, pResource, pReference) #define profilerBaseControl_Prologue(pResource, pCallContext, pParams) profilerBaseControl_Prologue_DISPATCH(pResource, pCallContext, pParams) #define profilerBaseGetRegBaseOffsetAndSize(pGpuResource, pGpu, pOffset, pSize) profilerBaseGetRegBaseOffsetAndSize_DISPATCH(pGpuResource, pGpu, pOffset, pSize) -#define profilerBaseCanCopy(pResource) profilerBaseCanCopy_DISPATCH(pResource) #define profilerBaseInternalControlForward(pGpuResource, command, pParams, size) profilerBaseInternalControlForward_DISPATCH(pGpuResource, command, pParams, size) -#define profilerBasePreDestruct(pResource) profilerBasePreDestruct_DISPATCH(pResource) #define profilerBaseUnmapFrom(pResource, pParams) profilerBaseUnmapFrom_DISPATCH(pResource, pParams) -#define profilerBaseIsDuplicate(pResource, hMemory, pDuplicate) profilerBaseIsDuplicate_DISPATCH(pResource, hMemory, pDuplicate) #define profilerBaseControl_Epilogue(pResource, pCallContext, pParams) profilerBaseControl_Epilogue_DISPATCH(pResource, pCallContext, pParams) #define profilerBaseControlLookup(pResource, pParams, ppEntry) profilerBaseControlLookup_DISPATCH(pResource, pParams, ppEntry) +#define profilerBaseGetInternalObjectHandle(pGpuResource) profilerBaseGetInternalObjectHandle_DISPATCH(pGpuResource) +#define profilerBaseControl(pGpuResource, pCallContext, pParams) profilerBaseControl_DISPATCH(pGpuResource, pCallContext, pParams) +#define profilerBaseUnmap(pGpuResource, pCallContext, pCpuMapping) profilerBaseUnmap_DISPATCH(pGpuResource, pCallContext, pCpuMapping) +#define profilerBaseGetMemInterMapParams(pRmResource, pParams) profilerBaseGetMemInterMapParams_DISPATCH(pRmResource, pParams) +#define profilerBaseGetMemoryMappingDescriptor(pRmResource, ppMemDesc) profilerBaseGetMemoryMappingDescriptor_DISPATCH(pRmResource, ppMemDesc) +#define profilerBaseControlFilter(pResource, pCallContext, pParams) profilerBaseControlFilter_DISPATCH(pResource, pCallContext, pParams) +#define profilerBaseControlSerialization_Prologue(pResource, pCallContext, pParams) profilerBaseControlSerialization_Prologue_DISPATCH(pResource, pCallContext, pParams) +#define profilerBaseCanCopy(pResource) profilerBaseCanCopy_DISPATCH(pResource) +#define profilerBasePreDestruct(pResource) profilerBasePreDestruct_DISPATCH(pResource) +#define profilerBaseIsDuplicate(pResource, hMemory, pDuplicate) profilerBaseIsDuplicate_DISPATCH(pResource, hMemory, pDuplicate) +#define profilerBaseControlSerialization_Epilogue(pResource, pCallContext, pParams) profilerBaseControlSerialization_Epilogue_DISPATCH(pResource, pCallContext, pParams) #define profilerBaseMap(pGpuResource, pCallContext, pParams, pCpuMapping) profilerBaseMap_DISPATCH(pGpuResource, pCallContext, pParams, pCpuMapping) #define profilerBaseAccessCallback(pResource, pInvokingClient, pAllocParams, accessRight) profilerBaseAccessCallback_DISPATCH(pResource, pInvokingClient, pAllocParams, accessRight) static inline NV_STATUS profilerBaseConstructState_56cd7a(struct ProfilerBase *pProf, struct CALL_CONTEXT *pCallContext, struct RS_RES_ALLOC_PARAMS_INTERNAL *pParams) { @@ -314,9 +330,9 @@ return pProfiler->__profilerBaseCtrlCmdExecRegops__(pProfiler, pParams); } -NV_STATUS profilerBaseCtrlCmdInternalAllocPmaStream_IMPL(struct ProfilerBase *pProfiler, NVB0CC_CTRL_ALLOC_PMA_STREAM_PARAMS *pParams); +NV_STATUS profilerBaseCtrlCmdInternalAllocPmaStream_IMPL(struct ProfilerBase *pProfiler, NVB0CC_CTRL_INTERNAL_ALLOC_PMA_STREAM_PARAMS *pParams); -static inline NV_STATUS profilerBaseCtrlCmdInternalAllocPmaStream_DISPATCH(struct ProfilerBase *pProfiler, NVB0CC_CTRL_ALLOC_PMA_STREAM_PARAMS *pParams) { +static inline NV_STATUS profilerBaseCtrlCmdInternalAllocPmaStream_DISPATCH(struct ProfilerBase *pProfiler, NVB0CC_CTRL_INTERNAL_ALLOC_PMA_STREAM_PARAMS *pParams) { return pProfiler->__profilerBaseCtrlCmdInternalAllocPmaStream__(pProfiler, pParams); } @@ -356,44 +372,44 @@ return pProfiler->__profilerBaseCtrlCmdSetHsCredits__(pProfiler, pParams); } -static inline NvBool profilerBaseShareCallback_DISPATCH(struct ProfilerBase *pGpuResource, struct RsClient *pInvokingClient, struct RsResourceRef *pParentRef, RS_SHARE_POLICY *pSharePolicy) { - return pGpuResource->__profilerBaseShareCallback__(pGpuResource, pInvokingClient, pParentRef, pSharePolicy); -} +NV_STATUS profilerBaseCtrlCmdReserveHes_IMPL(struct ProfilerBase *pProfiler, NVB0CC_CTRL_RESERVE_HES_PARAMS *pParams); -static inline NV_STATUS profilerBaseControl_DISPATCH(struct ProfilerBase *pGpuResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { - return pGpuResource->__profilerBaseControl__(pGpuResource, pCallContext, pParams); +static inline NV_STATUS profilerBaseCtrlCmdReserveHes_DISPATCH(struct ProfilerBase *pProfiler, NVB0CC_CTRL_RESERVE_HES_PARAMS *pParams) { + return pProfiler->__profilerBaseCtrlCmdReserveHes__(pProfiler, pParams); } -static inline NV_STATUS profilerBaseUnmap_DISPATCH(struct ProfilerBase *pGpuResource, struct CALL_CONTEXT *pCallContext, struct RsCpuMapping *pCpuMapping) { - return pGpuResource->__profilerBaseUnmap__(pGpuResource, pCallContext, pCpuMapping); -} +NV_STATUS profilerBaseCtrlCmdReleaseHes_IMPL(struct ProfilerBase *pProfiler, NVB0CC_CTRL_RELEASE_HES_PARAMS *pParams); -static inline NV_STATUS profilerBaseGetMemInterMapParams_DISPATCH(struct ProfilerBase *pRmResource, RMRES_MEM_INTER_MAP_PARAMS *pParams) { - return pRmResource->__profilerBaseGetMemInterMapParams__(pRmResource, pParams); +static inline NV_STATUS profilerBaseCtrlCmdReleaseHes_DISPATCH(struct ProfilerBase *pProfiler, NVB0CC_CTRL_RELEASE_HES_PARAMS *pParams) { + return pProfiler->__profilerBaseCtrlCmdReleaseHes__(pProfiler, pParams); } -static inline NV_STATUS profilerBaseGetMemoryMappingDescriptor_DISPATCH(struct ProfilerBase *pRmResource, struct MEMORY_DESCRIPTOR **ppMemDesc) { - return pRmResource->__profilerBaseGetMemoryMappingDescriptor__(pRmResource, ppMemDesc); -} +NV_STATUS profilerBaseCtrlCmdRequestCgControls_IMPL(struct ProfilerBase *pProfiler, NVB0CC_CTRL_POWER_REQUEST_FEATURES_PARAMS *pParams); -static inline NV_STATUS profilerBaseGetMapAddrSpace_DISPATCH(struct ProfilerBase *pGpuResource, struct CALL_CONTEXT *pCallContext, NvU32 mapFlags, NV_ADDRESS_SPACE *pAddrSpace) { - return pGpuResource->__profilerBaseGetMapAddrSpace__(pGpuResource, pCallContext, mapFlags, pAddrSpace); +static inline NV_STATUS profilerBaseCtrlCmdRequestCgControls_DISPATCH(struct ProfilerBase *pProfiler, NVB0CC_CTRL_POWER_REQUEST_FEATURES_PARAMS *pParams) { + return pProfiler->__profilerBaseCtrlCmdRequestCgControls__(pProfiler, pParams); } -static inline NvHandle profilerBaseGetInternalObjectHandle_DISPATCH(struct ProfilerBase *pGpuResource) { - return pGpuResource->__profilerBaseGetInternalObjectHandle__(pGpuResource); +NV_STATUS profilerBaseCtrlCmdReleaseCgControls_IMPL(struct ProfilerBase *pProfiler, NVB0CC_CTRL_POWER_RELEASE_FEATURES_PARAMS *pParams); + +static inline NV_STATUS profilerBaseCtrlCmdReleaseCgControls_DISPATCH(struct ProfilerBase *pProfiler, NVB0CC_CTRL_POWER_RELEASE_FEATURES_PARAMS *pParams) { + return pProfiler->__profilerBaseCtrlCmdReleaseCgControls__(pProfiler, pParams); } -static inline NV_STATUS profilerBaseControlFilter_DISPATCH(struct ProfilerBase *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { - return pResource->__profilerBaseControlFilter__(pResource, pCallContext, pParams); +NV_STATUS profilerBaseCtrlCmdDisableDynamicMMABoost_IMPL(struct ProfilerBase *pProfiler, NVB0CC_CTRL_DISABLE_DYNAMIC_MMA_BOOST_PARAMS *pParams); + +static inline NV_STATUS profilerBaseCtrlCmdDisableDynamicMMABoost_DISPATCH(struct ProfilerBase *pProfiler, NVB0CC_CTRL_DISABLE_DYNAMIC_MMA_BOOST_PARAMS *pParams) { + return pProfiler->__profilerBaseCtrlCmdDisableDynamicMMABoost__(pProfiler, pParams); } -static inline void profilerBaseAddAdditionalDependants_DISPATCH(struct RsClient *pClient, struct ProfilerBase *pResource, RsResourceRef *pReference) { - pResource->__profilerBaseAddAdditionalDependants__(pClient, pResource, pReference); +NV_STATUS profilerBaseCtrlCmdGetDynamicMMABoostStatus_IMPL(struct ProfilerBase *pProfiler, NVB0CC_CTRL_GET_DYNAMIC_MMA_BOOST_STATUS_PARAMS *pParams); + +static inline NV_STATUS profilerBaseCtrlCmdGetDynamicMMABoostStatus_DISPATCH(struct ProfilerBase *pProfiler, NVB0CC_CTRL_GET_DYNAMIC_MMA_BOOST_STATUS_PARAMS *pParams) { + return pProfiler->__profilerBaseCtrlCmdGetDynamicMMABoostStatus__(pProfiler, pParams); } -static inline NvU32 profilerBaseGetRefCount_DISPATCH(struct ProfilerBase *pResource) { - return pResource->__profilerBaseGetRefCount__(pResource); +static inline NvBool profilerBaseShareCallback_DISPATCH(struct ProfilerBase *pGpuResource, struct RsClient *pInvokingClient, struct RsResourceRef *pParentRef, RS_SHARE_POLICY *pSharePolicy) { + return pGpuResource->__profilerBaseShareCallback__(pGpuResource, pInvokingClient, pParentRef, pSharePolicy); } static inline NV_STATUS profilerBaseCheckMemInterUnmap_DISPATCH(struct ProfilerBase *pRmResource, NvBool bSubdeviceHandleProvided) { @@ -404,6 +420,18 @@ return pResource->__profilerBaseMapTo__(pResource, pParams); } +static inline NV_STATUS profilerBaseGetMapAddrSpace_DISPATCH(struct ProfilerBase *pGpuResource, struct CALL_CONTEXT *pCallContext, NvU32 mapFlags, NV_ADDRESS_SPACE *pAddrSpace) { + return pGpuResource->__profilerBaseGetMapAddrSpace__(pGpuResource, pCallContext, mapFlags, pAddrSpace); +} + +static inline NvU32 profilerBaseGetRefCount_DISPATCH(struct ProfilerBase *pResource) { + return pResource->__profilerBaseGetRefCount__(pResource); +} + +static inline void profilerBaseAddAdditionalDependants_DISPATCH(struct RsClient *pClient, struct ProfilerBase *pResource, RsResourceRef *pReference) { + pResource->__profilerBaseAddAdditionalDependants__(pClient, pResource, pReference); +} + static inline NV_STATUS profilerBaseControl_Prologue_DISPATCH(struct ProfilerBase *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { return pResource->__profilerBaseControl_Prologue__(pResource, pCallContext, pParams); } @@ -412,26 +440,14 @@ return pGpuResource->__profilerBaseGetRegBaseOffsetAndSize__(pGpuResource, pGpu, pOffset, pSize); } -static inline NvBool profilerBaseCanCopy_DISPATCH(struct ProfilerBase *pResource) { - return pResource->__profilerBaseCanCopy__(pResource); -} - static inline NV_STATUS profilerBaseInternalControlForward_DISPATCH(struct ProfilerBase *pGpuResource, NvU32 command, void *pParams, NvU32 size) { return pGpuResource->__profilerBaseInternalControlForward__(pGpuResource, command, pParams, size); } -static inline void profilerBasePreDestruct_DISPATCH(struct ProfilerBase *pResource) { - pResource->__profilerBasePreDestruct__(pResource); -} - static inline NV_STATUS profilerBaseUnmapFrom_DISPATCH(struct ProfilerBase *pResource, RS_RES_UNMAP_FROM_PARAMS *pParams) { return pResource->__profilerBaseUnmapFrom__(pResource, pParams); } -static inline NV_STATUS profilerBaseIsDuplicate_DISPATCH(struct ProfilerBase *pResource, NvHandle hMemory, NvBool *pDuplicate) { - return pResource->__profilerBaseIsDuplicate__(pResource, hMemory, pDuplicate); -} - static inline void profilerBaseControl_Epilogue_DISPATCH(struct ProfilerBase *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { pResource->__profilerBaseControl_Epilogue__(pResource, pCallContext, pParams); } @@ -440,6 +456,50 @@ return pResource->__profilerBaseControlLookup__(pResource, pParams, ppEntry); } +static inline NvHandle profilerBaseGetInternalObjectHandle_DISPATCH(struct ProfilerBase *pGpuResource) { + return pGpuResource->__profilerBaseGetInternalObjectHandle__(pGpuResource); +} + +static inline NV_STATUS profilerBaseControl_DISPATCH(struct ProfilerBase *pGpuResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return pGpuResource->__profilerBaseControl__(pGpuResource, pCallContext, pParams); +} + +static inline NV_STATUS profilerBaseUnmap_DISPATCH(struct ProfilerBase *pGpuResource, struct CALL_CONTEXT *pCallContext, struct RsCpuMapping *pCpuMapping) { + return pGpuResource->__profilerBaseUnmap__(pGpuResource, pCallContext, pCpuMapping); +} + +static inline NV_STATUS profilerBaseGetMemInterMapParams_DISPATCH(struct ProfilerBase *pRmResource, RMRES_MEM_INTER_MAP_PARAMS *pParams) { + return pRmResource->__profilerBaseGetMemInterMapParams__(pRmResource, pParams); +} + +static inline NV_STATUS profilerBaseGetMemoryMappingDescriptor_DISPATCH(struct ProfilerBase *pRmResource, struct MEMORY_DESCRIPTOR **ppMemDesc) { + return pRmResource->__profilerBaseGetMemoryMappingDescriptor__(pRmResource, ppMemDesc); +} + +static inline NV_STATUS profilerBaseControlFilter_DISPATCH(struct ProfilerBase *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return pResource->__profilerBaseControlFilter__(pResource, pCallContext, pParams); +} + +static inline NV_STATUS profilerBaseControlSerialization_Prologue_DISPATCH(struct ProfilerBase *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return pResource->__profilerBaseControlSerialization_Prologue__(pResource, pCallContext, pParams); +} + +static inline NvBool profilerBaseCanCopy_DISPATCH(struct ProfilerBase *pResource) { + return pResource->__profilerBaseCanCopy__(pResource); +} + +static inline void profilerBasePreDestruct_DISPATCH(struct ProfilerBase *pResource) { + pResource->__profilerBasePreDestruct__(pResource); +} + +static inline NV_STATUS profilerBaseIsDuplicate_DISPATCH(struct ProfilerBase *pResource, NvHandle hMemory, NvBool *pDuplicate) { + return pResource->__profilerBaseIsDuplicate__(pResource, hMemory, pDuplicate); +} + +static inline void profilerBaseControlSerialization_Epilogue_DISPATCH(struct ProfilerBase *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + pResource->__profilerBaseControlSerialization_Epilogue__(pResource, pCallContext, pParams); +} + static inline NV_STATUS profilerBaseMap_DISPATCH(struct ProfilerBase *pGpuResource, struct CALL_CONTEXT *pCallContext, struct RS_CPU_MAP_PARAMS *pParams, struct RsCpuMapping *pCpuMapping) { return pGpuResource->__profilerBaseMap__(pGpuResource, pCallContext, pParams, pCpuMapping); } @@ -473,26 +533,28 @@ struct ProfilerBase *__nvoc_pbase_ProfilerBase; struct ProfilerDev *__nvoc_pbase_ProfilerDev; NvBool (*__profilerDevShareCallback__)(struct ProfilerDev *, struct RsClient *, struct RsResourceRef *, RS_SHARE_POLICY *); - NV_STATUS (*__profilerDevControl__)(struct ProfilerDev *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); - NV_STATUS (*__profilerDevUnmap__)(struct ProfilerDev *, struct CALL_CONTEXT *, struct RsCpuMapping *); - NV_STATUS (*__profilerDevGetMemInterMapParams__)(struct ProfilerDev *, RMRES_MEM_INTER_MAP_PARAMS *); - NV_STATUS (*__profilerDevGetMemoryMappingDescriptor__)(struct ProfilerDev *, struct MEMORY_DESCRIPTOR **); - NV_STATUS (*__profilerDevGetMapAddrSpace__)(struct ProfilerDev *, struct CALL_CONTEXT *, NvU32, NV_ADDRESS_SPACE *); - NvHandle (*__profilerDevGetInternalObjectHandle__)(struct ProfilerDev *); - NV_STATUS (*__profilerDevControlFilter__)(struct ProfilerDev *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); - void (*__profilerDevAddAdditionalDependants__)(struct RsClient *, struct ProfilerDev *, RsResourceRef *); - NvU32 (*__profilerDevGetRefCount__)(struct ProfilerDev *); NV_STATUS (*__profilerDevCheckMemInterUnmap__)(struct ProfilerDev *, NvBool); NV_STATUS (*__profilerDevMapTo__)(struct ProfilerDev *, RS_RES_MAP_TO_PARAMS *); + NV_STATUS (*__profilerDevGetMapAddrSpace__)(struct ProfilerDev *, struct CALL_CONTEXT *, NvU32, NV_ADDRESS_SPACE *); + NvU32 (*__profilerDevGetRefCount__)(struct ProfilerDev *); + void (*__profilerDevAddAdditionalDependants__)(struct RsClient *, struct ProfilerDev *, RsResourceRef *); NV_STATUS (*__profilerDevControl_Prologue__)(struct ProfilerDev *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); NV_STATUS (*__profilerDevGetRegBaseOffsetAndSize__)(struct ProfilerDev *, struct OBJGPU *, NvU32 *, NvU32 *); - NvBool (*__profilerDevCanCopy__)(struct ProfilerDev *); NV_STATUS (*__profilerDevInternalControlForward__)(struct ProfilerDev *, NvU32, void *, NvU32); - void (*__profilerDevPreDestruct__)(struct ProfilerDev *); NV_STATUS (*__profilerDevUnmapFrom__)(struct ProfilerDev *, RS_RES_UNMAP_FROM_PARAMS *); - NV_STATUS (*__profilerDevIsDuplicate__)(struct ProfilerDev *, NvHandle, NvBool *); void (*__profilerDevControl_Epilogue__)(struct ProfilerDev *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); NV_STATUS (*__profilerDevControlLookup__)(struct ProfilerDev *, struct RS_RES_CONTROL_PARAMS_INTERNAL *, const struct NVOC_EXPORTED_METHOD_DEF **); + NvHandle (*__profilerDevGetInternalObjectHandle__)(struct ProfilerDev *); + NV_STATUS (*__profilerDevControl__)(struct ProfilerDev *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); + NV_STATUS (*__profilerDevUnmap__)(struct ProfilerDev *, struct CALL_CONTEXT *, struct RsCpuMapping *); + NV_STATUS (*__profilerDevGetMemInterMapParams__)(struct ProfilerDev *, RMRES_MEM_INTER_MAP_PARAMS *); + NV_STATUS (*__profilerDevGetMemoryMappingDescriptor__)(struct ProfilerDev *, struct MEMORY_DESCRIPTOR **); + NV_STATUS (*__profilerDevControlFilter__)(struct ProfilerDev *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); + NV_STATUS (*__profilerDevControlSerialization_Prologue__)(struct ProfilerDev *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); + NvBool (*__profilerDevCanCopy__)(struct ProfilerDev *); + void (*__profilerDevPreDestruct__)(struct ProfilerDev *); + NV_STATUS (*__profilerDevIsDuplicate__)(struct ProfilerDev *, NvHandle, NvBool *); + void (*__profilerDevControlSerialization_Epilogue__)(struct ProfilerDev *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); NV_STATUS (*__profilerDevMap__)(struct ProfilerDev *, struct CALL_CONTEXT *, struct RS_CPU_MAP_PARAMS *, struct RsCpuMapping *); NvBool (*__profilerDevAccessCallback__)(struct ProfilerDev *, struct RsClient *, void *, RsAccessRight); }; @@ -526,26 +588,28 @@ __nvoc_objCreate_ProfilerDev((ppNewObj), staticCast((pParent), Dynamic), (createFlags), arg_pCallContext, arg_pParams) #define profilerDevShareCallback(pGpuResource, pInvokingClient, pParentRef, pSharePolicy) profilerDevShareCallback_DISPATCH(pGpuResource, pInvokingClient, pParentRef, pSharePolicy) -#define profilerDevControl(pGpuResource, pCallContext, pParams) profilerDevControl_DISPATCH(pGpuResource, pCallContext, pParams) -#define profilerDevUnmap(pGpuResource, pCallContext, pCpuMapping) profilerDevUnmap_DISPATCH(pGpuResource, pCallContext, pCpuMapping) -#define profilerDevGetMemInterMapParams(pRmResource, pParams) profilerDevGetMemInterMapParams_DISPATCH(pRmResource, pParams) -#define profilerDevGetMemoryMappingDescriptor(pRmResource, ppMemDesc) profilerDevGetMemoryMappingDescriptor_DISPATCH(pRmResource, ppMemDesc) -#define profilerDevGetMapAddrSpace(pGpuResource, pCallContext, mapFlags, pAddrSpace) profilerDevGetMapAddrSpace_DISPATCH(pGpuResource, pCallContext, mapFlags, pAddrSpace) -#define profilerDevGetInternalObjectHandle(pGpuResource) profilerDevGetInternalObjectHandle_DISPATCH(pGpuResource) -#define profilerDevControlFilter(pResource, pCallContext, pParams) profilerDevControlFilter_DISPATCH(pResource, pCallContext, pParams) -#define profilerDevAddAdditionalDependants(pClient, pResource, pReference) profilerDevAddAdditionalDependants_DISPATCH(pClient, pResource, pReference) -#define profilerDevGetRefCount(pResource) profilerDevGetRefCount_DISPATCH(pResource) #define profilerDevCheckMemInterUnmap(pRmResource, bSubdeviceHandleProvided) profilerDevCheckMemInterUnmap_DISPATCH(pRmResource, bSubdeviceHandleProvided) #define profilerDevMapTo(pResource, pParams) profilerDevMapTo_DISPATCH(pResource, pParams) +#define profilerDevGetMapAddrSpace(pGpuResource, pCallContext, mapFlags, pAddrSpace) profilerDevGetMapAddrSpace_DISPATCH(pGpuResource, pCallContext, mapFlags, pAddrSpace) +#define profilerDevGetRefCount(pResource) profilerDevGetRefCount_DISPATCH(pResource) +#define profilerDevAddAdditionalDependants(pClient, pResource, pReference) profilerDevAddAdditionalDependants_DISPATCH(pClient, pResource, pReference) #define profilerDevControl_Prologue(pResource, pCallContext, pParams) profilerDevControl_Prologue_DISPATCH(pResource, pCallContext, pParams) #define profilerDevGetRegBaseOffsetAndSize(pGpuResource, pGpu, pOffset, pSize) profilerDevGetRegBaseOffsetAndSize_DISPATCH(pGpuResource, pGpu, pOffset, pSize) -#define profilerDevCanCopy(pResource) profilerDevCanCopy_DISPATCH(pResource) #define profilerDevInternalControlForward(pGpuResource, command, pParams, size) profilerDevInternalControlForward_DISPATCH(pGpuResource, command, pParams, size) -#define profilerDevPreDestruct(pResource) profilerDevPreDestruct_DISPATCH(pResource) #define profilerDevUnmapFrom(pResource, pParams) profilerDevUnmapFrom_DISPATCH(pResource, pParams) -#define profilerDevIsDuplicate(pResource, hMemory, pDuplicate) profilerDevIsDuplicate_DISPATCH(pResource, hMemory, pDuplicate) #define profilerDevControl_Epilogue(pResource, pCallContext, pParams) profilerDevControl_Epilogue_DISPATCH(pResource, pCallContext, pParams) #define profilerDevControlLookup(pResource, pParams, ppEntry) profilerDevControlLookup_DISPATCH(pResource, pParams, ppEntry) +#define profilerDevGetInternalObjectHandle(pGpuResource) profilerDevGetInternalObjectHandle_DISPATCH(pGpuResource) +#define profilerDevControl(pGpuResource, pCallContext, pParams) profilerDevControl_DISPATCH(pGpuResource, pCallContext, pParams) +#define profilerDevUnmap(pGpuResource, pCallContext, pCpuMapping) profilerDevUnmap_DISPATCH(pGpuResource, pCallContext, pCpuMapping) +#define profilerDevGetMemInterMapParams(pRmResource, pParams) profilerDevGetMemInterMapParams_DISPATCH(pRmResource, pParams) +#define profilerDevGetMemoryMappingDescriptor(pRmResource, ppMemDesc) profilerDevGetMemoryMappingDescriptor_DISPATCH(pRmResource, ppMemDesc) +#define profilerDevControlFilter(pResource, pCallContext, pParams) profilerDevControlFilter_DISPATCH(pResource, pCallContext, pParams) +#define profilerDevControlSerialization_Prologue(pResource, pCallContext, pParams) profilerDevControlSerialization_Prologue_DISPATCH(pResource, pCallContext, pParams) +#define profilerDevCanCopy(pResource) profilerDevCanCopy_DISPATCH(pResource) +#define profilerDevPreDestruct(pResource) profilerDevPreDestruct_DISPATCH(pResource) +#define profilerDevIsDuplicate(pResource, hMemory, pDuplicate) profilerDevIsDuplicate_DISPATCH(pResource, hMemory, pDuplicate) +#define profilerDevControlSerialization_Epilogue(pResource, pCallContext, pParams) profilerDevControlSerialization_Epilogue_DISPATCH(pResource, pCallContext, pParams) #define profilerDevMap(pGpuResource, pCallContext, pParams, pCpuMapping) profilerDevMap_DISPATCH(pGpuResource, pCallContext, pParams, pCpuMapping) #define profilerDevAccessCallback(pResource, pInvokingClient, pAllocParams, accessRight) profilerDevAccessCallback_DISPATCH(pResource, pInvokingClient, pAllocParams, accessRight) NV_STATUS profilerDevConstructState_IMPL(struct ProfilerDev *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_ALLOC_PARAMS_INTERNAL *pParams, PROFILER_CLIENT_PERMISSIONS clientPermissions); @@ -637,84 +701,92 @@ return pGpuResource->__profilerDevShareCallback__(pGpuResource, pInvokingClient, pParentRef, pSharePolicy); } -static inline NV_STATUS profilerDevControl_DISPATCH(struct ProfilerDev *pGpuResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { - return pGpuResource->__profilerDevControl__(pGpuResource, pCallContext, pParams); +static inline NV_STATUS profilerDevCheckMemInterUnmap_DISPATCH(struct ProfilerDev *pRmResource, NvBool bSubdeviceHandleProvided) { + return pRmResource->__profilerDevCheckMemInterUnmap__(pRmResource, bSubdeviceHandleProvided); } -static inline NV_STATUS profilerDevUnmap_DISPATCH(struct ProfilerDev *pGpuResource, struct CALL_CONTEXT *pCallContext, struct RsCpuMapping *pCpuMapping) { - return pGpuResource->__profilerDevUnmap__(pGpuResource, pCallContext, pCpuMapping); +static inline NV_STATUS profilerDevMapTo_DISPATCH(struct ProfilerDev *pResource, RS_RES_MAP_TO_PARAMS *pParams) { + return pResource->__profilerDevMapTo__(pResource, pParams); } -static inline NV_STATUS profilerDevGetMemInterMapParams_DISPATCH(struct ProfilerDev *pRmResource, RMRES_MEM_INTER_MAP_PARAMS *pParams) { - return pRmResource->__profilerDevGetMemInterMapParams__(pRmResource, pParams); +static inline NV_STATUS profilerDevGetMapAddrSpace_DISPATCH(struct ProfilerDev *pGpuResource, struct CALL_CONTEXT *pCallContext, NvU32 mapFlags, NV_ADDRESS_SPACE *pAddrSpace) { + return pGpuResource->__profilerDevGetMapAddrSpace__(pGpuResource, pCallContext, mapFlags, pAddrSpace); } -static inline NV_STATUS profilerDevGetMemoryMappingDescriptor_DISPATCH(struct ProfilerDev *pRmResource, struct MEMORY_DESCRIPTOR **ppMemDesc) { - return pRmResource->__profilerDevGetMemoryMappingDescriptor__(pRmResource, ppMemDesc); +static inline NvU32 profilerDevGetRefCount_DISPATCH(struct ProfilerDev *pResource) { + return pResource->__profilerDevGetRefCount__(pResource); } -static inline NV_STATUS profilerDevGetMapAddrSpace_DISPATCH(struct ProfilerDev *pGpuResource, struct CALL_CONTEXT *pCallContext, NvU32 mapFlags, NV_ADDRESS_SPACE *pAddrSpace) { - return pGpuResource->__profilerDevGetMapAddrSpace__(pGpuResource, pCallContext, mapFlags, pAddrSpace); +static inline void profilerDevAddAdditionalDependants_DISPATCH(struct RsClient *pClient, struct ProfilerDev *pResource, RsResourceRef *pReference) { + pResource->__profilerDevAddAdditionalDependants__(pClient, pResource, pReference); } -static inline NvHandle profilerDevGetInternalObjectHandle_DISPATCH(struct ProfilerDev *pGpuResource) { - return pGpuResource->__profilerDevGetInternalObjectHandle__(pGpuResource); +static inline NV_STATUS profilerDevControl_Prologue_DISPATCH(struct ProfilerDev *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return pResource->__profilerDevControl_Prologue__(pResource, pCallContext, pParams); } -static inline NV_STATUS profilerDevControlFilter_DISPATCH(struct ProfilerDev *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { - return pResource->__profilerDevControlFilter__(pResource, pCallContext, pParams); +static inline NV_STATUS profilerDevGetRegBaseOffsetAndSize_DISPATCH(struct ProfilerDev *pGpuResource, struct OBJGPU *pGpu, NvU32 *pOffset, NvU32 *pSize) { + return pGpuResource->__profilerDevGetRegBaseOffsetAndSize__(pGpuResource, pGpu, pOffset, pSize); } -static inline void profilerDevAddAdditionalDependants_DISPATCH(struct RsClient *pClient, struct ProfilerDev *pResource, RsResourceRef *pReference) { - pResource->__profilerDevAddAdditionalDependants__(pClient, pResource, pReference); +static inline NV_STATUS profilerDevInternalControlForward_DISPATCH(struct ProfilerDev *pGpuResource, NvU32 command, void *pParams, NvU32 size) { + return pGpuResource->__profilerDevInternalControlForward__(pGpuResource, command, pParams, size); } -static inline NvU32 profilerDevGetRefCount_DISPATCH(struct ProfilerDev *pResource) { - return pResource->__profilerDevGetRefCount__(pResource); +static inline NV_STATUS profilerDevUnmapFrom_DISPATCH(struct ProfilerDev *pResource, RS_RES_UNMAP_FROM_PARAMS *pParams) { + return pResource->__profilerDevUnmapFrom__(pResource, pParams); } -static inline NV_STATUS profilerDevCheckMemInterUnmap_DISPATCH(struct ProfilerDev *pRmResource, NvBool bSubdeviceHandleProvided) { - return pRmResource->__profilerDevCheckMemInterUnmap__(pRmResource, bSubdeviceHandleProvided); +static inline void profilerDevControl_Epilogue_DISPATCH(struct ProfilerDev *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + pResource->__profilerDevControl_Epilogue__(pResource, pCallContext, pParams); } -static inline NV_STATUS profilerDevMapTo_DISPATCH(struct ProfilerDev *pResource, RS_RES_MAP_TO_PARAMS *pParams) { - return pResource->__profilerDevMapTo__(pResource, pParams); +static inline NV_STATUS profilerDevControlLookup_DISPATCH(struct ProfilerDev *pResource, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams, const struct NVOC_EXPORTED_METHOD_DEF **ppEntry) { + return pResource->__profilerDevControlLookup__(pResource, pParams, ppEntry); } -static inline NV_STATUS profilerDevControl_Prologue_DISPATCH(struct ProfilerDev *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { - return pResource->__profilerDevControl_Prologue__(pResource, pCallContext, pParams); +static inline NvHandle profilerDevGetInternalObjectHandle_DISPATCH(struct ProfilerDev *pGpuResource) { + return pGpuResource->__profilerDevGetInternalObjectHandle__(pGpuResource); } -static inline NV_STATUS profilerDevGetRegBaseOffsetAndSize_DISPATCH(struct ProfilerDev *pGpuResource, struct OBJGPU *pGpu, NvU32 *pOffset, NvU32 *pSize) { - return pGpuResource->__profilerDevGetRegBaseOffsetAndSize__(pGpuResource, pGpu, pOffset, pSize); +static inline NV_STATUS profilerDevControl_DISPATCH(struct ProfilerDev *pGpuResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return pGpuResource->__profilerDevControl__(pGpuResource, pCallContext, pParams); } -static inline NvBool profilerDevCanCopy_DISPATCH(struct ProfilerDev *pResource) { - return pResource->__profilerDevCanCopy__(pResource); +static inline NV_STATUS profilerDevUnmap_DISPATCH(struct ProfilerDev *pGpuResource, struct CALL_CONTEXT *pCallContext, struct RsCpuMapping *pCpuMapping) { + return pGpuResource->__profilerDevUnmap__(pGpuResource, pCallContext, pCpuMapping); } -static inline NV_STATUS profilerDevInternalControlForward_DISPATCH(struct ProfilerDev *pGpuResource, NvU32 command, void *pParams, NvU32 size) { - return pGpuResource->__profilerDevInternalControlForward__(pGpuResource, command, pParams, size); +static inline NV_STATUS profilerDevGetMemInterMapParams_DISPATCH(struct ProfilerDev *pRmResource, RMRES_MEM_INTER_MAP_PARAMS *pParams) { + return pRmResource->__profilerDevGetMemInterMapParams__(pRmResource, pParams); } -static inline void profilerDevPreDestruct_DISPATCH(struct ProfilerDev *pResource) { - pResource->__profilerDevPreDestruct__(pResource); +static inline NV_STATUS profilerDevGetMemoryMappingDescriptor_DISPATCH(struct ProfilerDev *pRmResource, struct MEMORY_DESCRIPTOR **ppMemDesc) { + return pRmResource->__profilerDevGetMemoryMappingDescriptor__(pRmResource, ppMemDesc); } -static inline NV_STATUS profilerDevUnmapFrom_DISPATCH(struct ProfilerDev *pResource, RS_RES_UNMAP_FROM_PARAMS *pParams) { - return pResource->__profilerDevUnmapFrom__(pResource, pParams); +static inline NV_STATUS profilerDevControlFilter_DISPATCH(struct ProfilerDev *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return pResource->__profilerDevControlFilter__(pResource, pCallContext, pParams); } -static inline NV_STATUS profilerDevIsDuplicate_DISPATCH(struct ProfilerDev *pResource, NvHandle hMemory, NvBool *pDuplicate) { - return pResource->__profilerDevIsDuplicate__(pResource, hMemory, pDuplicate); +static inline NV_STATUS profilerDevControlSerialization_Prologue_DISPATCH(struct ProfilerDev *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return pResource->__profilerDevControlSerialization_Prologue__(pResource, pCallContext, pParams); } -static inline void profilerDevControl_Epilogue_DISPATCH(struct ProfilerDev *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { - pResource->__profilerDevControl_Epilogue__(pResource, pCallContext, pParams); +static inline NvBool profilerDevCanCopy_DISPATCH(struct ProfilerDev *pResource) { + return pResource->__profilerDevCanCopy__(pResource); } -static inline NV_STATUS profilerDevControlLookup_DISPATCH(struct ProfilerDev *pResource, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams, const struct NVOC_EXPORTED_METHOD_DEF **ppEntry) { - return pResource->__profilerDevControlLookup__(pResource, pParams, ppEntry); +static inline void profilerDevPreDestruct_DISPATCH(struct ProfilerDev *pResource) { + pResource->__profilerDevPreDestruct__(pResource); +} + +static inline NV_STATUS profilerDevIsDuplicate_DISPATCH(struct ProfilerDev *pResource, NvHandle hMemory, NvBool *pDuplicate) { + return pResource->__profilerDevIsDuplicate__(pResource, hMemory, pDuplicate); +} + +static inline void profilerDevControlSerialization_Epilogue_DISPATCH(struct ProfilerDev *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + pResource->__profilerDevControlSerialization_Epilogue__(pResource, pCallContext, pParams); } static inline NV_STATUS profilerDevMap_DISPATCH(struct ProfilerDev *pGpuResource, struct CALL_CONTEXT *pCallContext, struct RS_CPU_MAP_PARAMS *pParams, struct RsCpuMapping *pCpuMapping) { diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/generated/g_ref_count_nvoc.c nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_ref_count_nvoc.c --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/generated/g_ref_count_nvoc.c 2023-10-25 20:27:17.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_ref_count_nvoc.c 2024-03-05 22:18:42.000000000 +0000 @@ -114,13 +114,16 @@ Object *pParentObj; OBJREFCNT *pThis; - pThis = portMemAllocNonPaged(sizeof(OBJREFCNT)); - if (pThis == NULL) return NV_ERR_NO_MEMORY; + status = __nvoc_handleObjCreateMemAlloc(createFlags, sizeof(OBJREFCNT), (void**)&pThis, (void**)ppThis); + if (status != NV_OK) + return status; portMemSet(pThis, 0, sizeof(OBJREFCNT)); __nvoc_initRtti(staticCast(pThis, Dynamic), &__nvoc_class_def_OBJREFCNT); + pThis->__nvoc_base_Object.createFlags = createFlags; + if (pParent != NULL && !(createFlags & NVOC_OBJ_CREATE_FLAGS_PARENT_HALSPEC_ONLY)) { pParentObj = dynamicCast(pParent, Object); @@ -136,11 +139,17 @@ if (status != NV_OK) goto __nvoc_objCreate_OBJREFCNT_cleanup; *ppThis = pThis; + return NV_OK; __nvoc_objCreate_OBJREFCNT_cleanup: // do not call destructors here since the constructor already called them - portMemFree(pThis); + if (createFlags & NVOC_OBJ_CREATE_FLAGS_IN_PLACE_CONSTRUCT) + portMemSet(pThis, 0, sizeof(OBJREFCNT)); + else + portMemFree(pThis); + + // coverity[leaked_storage:FALSE] return status; } diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/generated/g_reg_mem_nvoc.c nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_reg_mem_nvoc.c --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/generated/g_reg_mem_nvoc.c 2023-10-25 20:27:17.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_reg_mem_nvoc.c 2024-03-05 22:18:42.000000000 +0000 @@ -101,60 +101,76 @@ return memCheckMemInterUnmap((struct Memory *)(((unsigned char *)pMemory) + __nvoc_rtti_RegisterMemory_Memory.offset), bSubdeviceHandleProvided); } -static NV_STATUS __nvoc_thunk_Memory_regmemControl(struct RegisterMemory *pMemory, CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { - return memControl((struct Memory *)(((unsigned char *)pMemory) + __nvoc_rtti_RegisterMemory_Memory.offset), pCallContext, pParams); +static NvBool __nvoc_thunk_RmResource_regmemShareCallback(struct RegisterMemory *pResource, struct RsClient *pInvokingClient, struct RsResourceRef *pParentRef, RS_SHARE_POLICY *pSharePolicy) { + return rmresShareCallback((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_RegisterMemory_RmResource.offset), pInvokingClient, pParentRef, pSharePolicy); } -static NV_STATUS __nvoc_thunk_Memory_regmemUnmap(struct RegisterMemory *pMemory, CALL_CONTEXT *pCallContext, RsCpuMapping *pCpuMapping) { - return memUnmap((struct Memory *)(((unsigned char *)pMemory) + __nvoc_rtti_RegisterMemory_Memory.offset), pCallContext, pCpuMapping); +static NV_STATUS __nvoc_thunk_RsResource_regmemMapTo(struct RegisterMemory *pResource, RS_RES_MAP_TO_PARAMS *pParams) { + return resMapTo((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_RegisterMemory_RsResource.offset), pParams); } -static NV_STATUS __nvoc_thunk_Memory_regmemGetMemInterMapParams(struct RegisterMemory *pMemory, RMRES_MEM_INTER_MAP_PARAMS *pParams) { - return memGetMemInterMapParams((struct Memory *)(((unsigned char *)pMemory) + __nvoc_rtti_RegisterMemory_Memory.offset), pParams); +static NV_STATUS __nvoc_thunk_Memory_regmemGetMapAddrSpace(struct RegisterMemory *pMemory, CALL_CONTEXT *pCallContext, NvU32 mapFlags, NV_ADDRESS_SPACE *pAddrSpace) { + return memGetMapAddrSpace((struct Memory *)(((unsigned char *)pMemory) + __nvoc_rtti_RegisterMemory_Memory.offset), pCallContext, mapFlags, pAddrSpace); } -static NV_STATUS __nvoc_thunk_Memory_regmemGetMemoryMappingDescriptor(struct RegisterMemory *pMemory, MEMORY_DESCRIPTOR **ppMemDesc) { - return memGetMemoryMappingDescriptor((struct Memory *)(((unsigned char *)pMemory) + __nvoc_rtti_RegisterMemory_Memory.offset), ppMemDesc); +static NvU32 __nvoc_thunk_RsResource_regmemGetRefCount(struct RegisterMemory *pResource) { + return resGetRefCount((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_RegisterMemory_RsResource.offset)); } -static NV_STATUS __nvoc_thunk_Memory_regmemGetMapAddrSpace(struct RegisterMemory *pMemory, CALL_CONTEXT *pCallContext, NvU32 mapFlags, NV_ADDRESS_SPACE *pAddrSpace) { - return memGetMapAddrSpace((struct Memory *)(((unsigned char *)pMemory) + __nvoc_rtti_RegisterMemory_Memory.offset), pCallContext, mapFlags, pAddrSpace); +static void __nvoc_thunk_RsResource_regmemAddAdditionalDependants(struct RsClient *pClient, struct RegisterMemory *pResource, RsResourceRef *pReference) { + resAddAdditionalDependants(pClient, (struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_RegisterMemory_RsResource.offset), pReference); } -static NvBool __nvoc_thunk_RmResource_regmemShareCallback(struct RegisterMemory *pResource, struct RsClient *pInvokingClient, struct RsResourceRef *pParentRef, RS_SHARE_POLICY *pSharePolicy) { - return rmresShareCallback((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_RegisterMemory_RmResource.offset), pInvokingClient, pParentRef, pSharePolicy); +static NV_STATUS __nvoc_thunk_RmResource_regmemControl_Prologue(struct RegisterMemory *pResource, CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return rmresControl_Prologue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_RegisterMemory_RmResource.offset), pCallContext, pParams); } -static NV_STATUS __nvoc_thunk_RsResource_regmemControlFilter(struct RegisterMemory *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { - return resControlFilter((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_RegisterMemory_RsResource.offset), pCallContext, pParams); +static NvBool __nvoc_thunk_Memory_regmemIsGpuMapAllowed(struct RegisterMemory *pMemory, struct OBJGPU *pGpu) { + return memIsGpuMapAllowed((struct Memory *)(((unsigned char *)pMemory) + __nvoc_rtti_RegisterMemory_Memory.offset), pGpu); } -static void __nvoc_thunk_RsResource_regmemAddAdditionalDependants(struct RsClient *pClient, struct RegisterMemory *pResource, RsResourceRef *pReference) { - resAddAdditionalDependants(pClient, (struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_RegisterMemory_RsResource.offset), pReference); +static NV_STATUS __nvoc_thunk_RsResource_regmemUnmapFrom(struct RegisterMemory *pResource, RS_RES_UNMAP_FROM_PARAMS *pParams) { + return resUnmapFrom((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_RegisterMemory_RsResource.offset), pParams); } -static NvU32 __nvoc_thunk_RsResource_regmemGetRefCount(struct RegisterMemory *pResource) { - return resGetRefCount((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_RegisterMemory_RsResource.offset)); +static void __nvoc_thunk_RmResource_regmemControl_Epilogue(struct RegisterMemory *pResource, CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + rmresControl_Epilogue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_RegisterMemory_RmResource.offset), pCallContext, pParams); } -static NV_STATUS __nvoc_thunk_RsResource_regmemMapTo(struct RegisterMemory *pResource, RS_RES_MAP_TO_PARAMS *pParams) { - return resMapTo((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_RegisterMemory_RsResource.offset), pParams); +static NV_STATUS __nvoc_thunk_RsResource_regmemControlLookup(struct RegisterMemory *pResource, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams, const struct NVOC_EXPORTED_METHOD_DEF **ppEntry) { + return resControlLookup((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_RegisterMemory_RsResource.offset), pParams, ppEntry); } -static NV_STATUS __nvoc_thunk_RmResource_regmemControl_Prologue(struct RegisterMemory *pResource, CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { - return rmresControl_Prologue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_RegisterMemory_RmResource.offset), pCallContext, pParams); +static NV_STATUS __nvoc_thunk_Memory_regmemControl(struct RegisterMemory *pMemory, CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return memControl((struct Memory *)(((unsigned char *)pMemory) + __nvoc_rtti_RegisterMemory_Memory.offset), pCallContext, pParams); } -static NvBool __nvoc_thunk_Memory_regmemIsGpuMapAllowed(struct RegisterMemory *pMemory, struct OBJGPU *pGpu) { - return memIsGpuMapAllowed((struct Memory *)(((unsigned char *)pMemory) + __nvoc_rtti_RegisterMemory_Memory.offset), pGpu); +static NV_STATUS __nvoc_thunk_Memory_regmemUnmap(struct RegisterMemory *pMemory, CALL_CONTEXT *pCallContext, RsCpuMapping *pCpuMapping) { + return memUnmap((struct Memory *)(((unsigned char *)pMemory) + __nvoc_rtti_RegisterMemory_Memory.offset), pCallContext, pCpuMapping); +} + +static NV_STATUS __nvoc_thunk_Memory_regmemGetMemInterMapParams(struct RegisterMemory *pMemory, RMRES_MEM_INTER_MAP_PARAMS *pParams) { + return memGetMemInterMapParams((struct Memory *)(((unsigned char *)pMemory) + __nvoc_rtti_RegisterMemory_Memory.offset), pParams); +} + +static NV_STATUS __nvoc_thunk_Memory_regmemGetMemoryMappingDescriptor(struct RegisterMemory *pMemory, MEMORY_DESCRIPTOR **ppMemDesc) { + return memGetMemoryMappingDescriptor((struct Memory *)(((unsigned char *)pMemory) + __nvoc_rtti_RegisterMemory_Memory.offset), ppMemDesc); +} + +static NV_STATUS __nvoc_thunk_RsResource_regmemControlFilter(struct RegisterMemory *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return resControlFilter((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_RegisterMemory_RsResource.offset), pCallContext, pParams); +} + +static NV_STATUS __nvoc_thunk_RmResource_regmemControlSerialization_Prologue(struct RegisterMemory *pResource, CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return rmresControlSerialization_Prologue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_RegisterMemory_RmResource.offset), pCallContext, pParams); } static NV_STATUS __nvoc_thunk_Memory_regmemIsReady(struct RegisterMemory *pMemory, NvBool bCopyConstructorContext) { return memIsReady((struct Memory *)(((unsigned char *)pMemory) + __nvoc_rtti_RegisterMemory_Memory.offset), bCopyConstructorContext); } -static NV_STATUS __nvoc_thunk_Memory_regmemCheckCopyPermissions(struct RegisterMemory *pMemory, struct OBJGPU *pDstGpu, NvHandle hDstClientNvBool) { - return memCheckCopyPermissions((struct Memory *)(((unsigned char *)pMemory) + __nvoc_rtti_RegisterMemory_Memory.offset), pDstGpu, hDstClientNvBool); +static NV_STATUS __nvoc_thunk_Memory_regmemCheckCopyPermissions(struct RegisterMemory *pMemory, struct OBJGPU *pDstGpu, struct Device *pDstDevice) { + return memCheckCopyPermissions((struct Memory *)(((unsigned char *)pMemory) + __nvoc_rtti_RegisterMemory_Memory.offset), pDstGpu, pDstDevice); } static void __nvoc_thunk_RsResource_regmemPreDestruct(struct RegisterMemory *pResource) { @@ -165,16 +181,8 @@ return memIsDuplicate((struct Memory *)(((unsigned char *)pMemory) + __nvoc_rtti_RegisterMemory_Memory.offset), hMemory, pDuplicate); } -static NV_STATUS __nvoc_thunk_RsResource_regmemUnmapFrom(struct RegisterMemory *pResource, RS_RES_UNMAP_FROM_PARAMS *pParams) { - return resUnmapFrom((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_RegisterMemory_RsResource.offset), pParams); -} - -static void __nvoc_thunk_RmResource_regmemControl_Epilogue(struct RegisterMemory *pResource, CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { - rmresControl_Epilogue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_RegisterMemory_RmResource.offset), pCallContext, pParams); -} - -static NV_STATUS __nvoc_thunk_RsResource_regmemControlLookup(struct RegisterMemory *pResource, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams, const struct NVOC_EXPORTED_METHOD_DEF **ppEntry) { - return resControlLookup((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_RegisterMemory_RsResource.offset), pParams, ppEntry); +static void __nvoc_thunk_RmResource_regmemControlSerialization_Epilogue(struct RegisterMemory *pResource, CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + rmresControlSerialization_Epilogue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_RegisterMemory_RmResource.offset), pCallContext, pParams); } static NV_STATUS __nvoc_thunk_Memory_regmemMap(struct RegisterMemory *pMemory, CALL_CONTEXT *pCallContext, struct RS_CPU_MAP_PARAMS *pParams, RsCpuMapping *pCpuMapping) { @@ -229,29 +237,37 @@ pThis->__regmemCheckMemInterUnmap__ = &__nvoc_thunk_Memory_regmemCheckMemInterUnmap; - pThis->__regmemControl__ = &__nvoc_thunk_Memory_regmemControl; + pThis->__regmemShareCallback__ = &__nvoc_thunk_RmResource_regmemShareCallback; - pThis->__regmemUnmap__ = &__nvoc_thunk_Memory_regmemUnmap; + pThis->__regmemMapTo__ = &__nvoc_thunk_RsResource_regmemMapTo; - pThis->__regmemGetMemInterMapParams__ = &__nvoc_thunk_Memory_regmemGetMemInterMapParams; + pThis->__regmemGetMapAddrSpace__ = &__nvoc_thunk_Memory_regmemGetMapAddrSpace; - pThis->__regmemGetMemoryMappingDescriptor__ = &__nvoc_thunk_Memory_regmemGetMemoryMappingDescriptor; + pThis->__regmemGetRefCount__ = &__nvoc_thunk_RsResource_regmemGetRefCount; - pThis->__regmemGetMapAddrSpace__ = &__nvoc_thunk_Memory_regmemGetMapAddrSpace; + pThis->__regmemAddAdditionalDependants__ = &__nvoc_thunk_RsResource_regmemAddAdditionalDependants; - pThis->__regmemShareCallback__ = &__nvoc_thunk_RmResource_regmemShareCallback; + pThis->__regmemControl_Prologue__ = &__nvoc_thunk_RmResource_regmemControl_Prologue; - pThis->__regmemControlFilter__ = &__nvoc_thunk_RsResource_regmemControlFilter; + pThis->__regmemIsGpuMapAllowed__ = &__nvoc_thunk_Memory_regmemIsGpuMapAllowed; - pThis->__regmemAddAdditionalDependants__ = &__nvoc_thunk_RsResource_regmemAddAdditionalDependants; + pThis->__regmemUnmapFrom__ = &__nvoc_thunk_RsResource_regmemUnmapFrom; - pThis->__regmemGetRefCount__ = &__nvoc_thunk_RsResource_regmemGetRefCount; + pThis->__regmemControl_Epilogue__ = &__nvoc_thunk_RmResource_regmemControl_Epilogue; - pThis->__regmemMapTo__ = &__nvoc_thunk_RsResource_regmemMapTo; + pThis->__regmemControlLookup__ = &__nvoc_thunk_RsResource_regmemControlLookup; - pThis->__regmemControl_Prologue__ = &__nvoc_thunk_RmResource_regmemControl_Prologue; + pThis->__regmemControl__ = &__nvoc_thunk_Memory_regmemControl; - pThis->__regmemIsGpuMapAllowed__ = &__nvoc_thunk_Memory_regmemIsGpuMapAllowed; + pThis->__regmemUnmap__ = &__nvoc_thunk_Memory_regmemUnmap; + + pThis->__regmemGetMemInterMapParams__ = &__nvoc_thunk_Memory_regmemGetMemInterMapParams; + + pThis->__regmemGetMemoryMappingDescriptor__ = &__nvoc_thunk_Memory_regmemGetMemoryMappingDescriptor; + + pThis->__regmemControlFilter__ = &__nvoc_thunk_RsResource_regmemControlFilter; + + pThis->__regmemControlSerialization_Prologue__ = &__nvoc_thunk_RmResource_regmemControlSerialization_Prologue; pThis->__regmemIsReady__ = &__nvoc_thunk_Memory_regmemIsReady; @@ -261,11 +277,7 @@ pThis->__regmemIsDuplicate__ = &__nvoc_thunk_Memory_regmemIsDuplicate; - pThis->__regmemUnmapFrom__ = &__nvoc_thunk_RsResource_regmemUnmapFrom; - - pThis->__regmemControl_Epilogue__ = &__nvoc_thunk_RmResource_regmemControl_Epilogue; - - pThis->__regmemControlLookup__ = &__nvoc_thunk_RsResource_regmemControlLookup; + pThis->__regmemControlSerialization_Epilogue__ = &__nvoc_thunk_RmResource_regmemControlSerialization_Epilogue; pThis->__regmemMap__ = &__nvoc_thunk_Memory_regmemMap; @@ -293,13 +305,16 @@ Object *pParentObj; RegisterMemory *pThis; - pThis = portMemAllocNonPaged(sizeof(RegisterMemory)); - if (pThis == NULL) return NV_ERR_NO_MEMORY; + status = __nvoc_handleObjCreateMemAlloc(createFlags, sizeof(RegisterMemory), (void**)&pThis, (void**)ppThis); + if (status != NV_OK) + return status; portMemSet(pThis, 0, sizeof(RegisterMemory)); __nvoc_initRtti(staticCast(pThis, Dynamic), &__nvoc_class_def_RegisterMemory); + pThis->__nvoc_base_Memory.__nvoc_base_RmResource.__nvoc_base_RsResource.__nvoc_base_Object.createFlags = createFlags; + if (pParent != NULL && !(createFlags & NVOC_OBJ_CREATE_FLAGS_PARENT_HALSPEC_ONLY)) { pParentObj = dynamicCast(pParent, Object); @@ -315,11 +330,17 @@ if (status != NV_OK) goto __nvoc_objCreate_RegisterMemory_cleanup; *ppThis = pThis; + return NV_OK; __nvoc_objCreate_RegisterMemory_cleanup: // do not call destructors here since the constructor already called them - portMemFree(pThis); + if (createFlags & NVOC_OBJ_CREATE_FLAGS_IN_PLACE_CONSTRUCT) + portMemSet(pThis, 0, sizeof(RegisterMemory)); + else + portMemFree(pThis); + + // coverity[leaked_storage:FALSE] return status; } diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/generated/g_reg_mem_nvoc.h nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_reg_mem_nvoc.h --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/generated/g_reg_mem_nvoc.h 2023-10-25 20:27:17.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_reg_mem_nvoc.h 2024-03-05 22:18:42.000000000 +0000 @@ -57,25 +57,27 @@ struct RegisterMemory *__nvoc_pbase_RegisterMemory; NvBool (*__regmemCanCopy__)(struct RegisterMemory *); NV_STATUS (*__regmemCheckMemInterUnmap__)(struct RegisterMemory *, NvBool); + NvBool (*__regmemShareCallback__)(struct RegisterMemory *, struct RsClient *, struct RsResourceRef *, RS_SHARE_POLICY *); + NV_STATUS (*__regmemMapTo__)(struct RegisterMemory *, RS_RES_MAP_TO_PARAMS *); + NV_STATUS (*__regmemGetMapAddrSpace__)(struct RegisterMemory *, CALL_CONTEXT *, NvU32, NV_ADDRESS_SPACE *); + NvU32 (*__regmemGetRefCount__)(struct RegisterMemory *); + void (*__regmemAddAdditionalDependants__)(struct RsClient *, struct RegisterMemory *, RsResourceRef *); + NV_STATUS (*__regmemControl_Prologue__)(struct RegisterMemory *, CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); + NvBool (*__regmemIsGpuMapAllowed__)(struct RegisterMemory *, struct OBJGPU *); + NV_STATUS (*__regmemUnmapFrom__)(struct RegisterMemory *, RS_RES_UNMAP_FROM_PARAMS *); + void (*__regmemControl_Epilogue__)(struct RegisterMemory *, CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); + NV_STATUS (*__regmemControlLookup__)(struct RegisterMemory *, struct RS_RES_CONTROL_PARAMS_INTERNAL *, const struct NVOC_EXPORTED_METHOD_DEF **); NV_STATUS (*__regmemControl__)(struct RegisterMemory *, CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); NV_STATUS (*__regmemUnmap__)(struct RegisterMemory *, CALL_CONTEXT *, RsCpuMapping *); NV_STATUS (*__regmemGetMemInterMapParams__)(struct RegisterMemory *, RMRES_MEM_INTER_MAP_PARAMS *); NV_STATUS (*__regmemGetMemoryMappingDescriptor__)(struct RegisterMemory *, MEMORY_DESCRIPTOR **); - NV_STATUS (*__regmemGetMapAddrSpace__)(struct RegisterMemory *, CALL_CONTEXT *, NvU32, NV_ADDRESS_SPACE *); - NvBool (*__regmemShareCallback__)(struct RegisterMemory *, struct RsClient *, struct RsResourceRef *, RS_SHARE_POLICY *); NV_STATUS (*__regmemControlFilter__)(struct RegisterMemory *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); - void (*__regmemAddAdditionalDependants__)(struct RsClient *, struct RegisterMemory *, RsResourceRef *); - NvU32 (*__regmemGetRefCount__)(struct RegisterMemory *); - NV_STATUS (*__regmemMapTo__)(struct RegisterMemory *, RS_RES_MAP_TO_PARAMS *); - NV_STATUS (*__regmemControl_Prologue__)(struct RegisterMemory *, CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); - NvBool (*__regmemIsGpuMapAllowed__)(struct RegisterMemory *, struct OBJGPU *); + NV_STATUS (*__regmemControlSerialization_Prologue__)(struct RegisterMemory *, CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); NV_STATUS (*__regmemIsReady__)(struct RegisterMemory *, NvBool); - NV_STATUS (*__regmemCheckCopyPermissions__)(struct RegisterMemory *, struct OBJGPU *, NvHandle); + NV_STATUS (*__regmemCheckCopyPermissions__)(struct RegisterMemory *, struct OBJGPU *, struct Device *); void (*__regmemPreDestruct__)(struct RegisterMemory *); NV_STATUS (*__regmemIsDuplicate__)(struct RegisterMemory *, NvHandle, NvBool *); - NV_STATUS (*__regmemUnmapFrom__)(struct RegisterMemory *, RS_RES_UNMAP_FROM_PARAMS *); - void (*__regmemControl_Epilogue__)(struct RegisterMemory *, CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); - NV_STATUS (*__regmemControlLookup__)(struct RegisterMemory *, struct RS_RES_CONTROL_PARAMS_INTERNAL *, const struct NVOC_EXPORTED_METHOD_DEF **); + void (*__regmemControlSerialization_Epilogue__)(struct RegisterMemory *, CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); NV_STATUS (*__regmemMap__)(struct RegisterMemory *, CALL_CONTEXT *, struct RS_CPU_MAP_PARAMS *, RsCpuMapping *); NvBool (*__regmemAccessCallback__)(struct RegisterMemory *, struct RsClient *, void *, RsAccessRight); }; @@ -110,25 +112,27 @@ #define regmemCanCopy(pRegisterMemory) regmemCanCopy_DISPATCH(pRegisterMemory) #define regmemCheckMemInterUnmap(pMemory, bSubdeviceHandleProvided) regmemCheckMemInterUnmap_DISPATCH(pMemory, bSubdeviceHandleProvided) +#define regmemShareCallback(pResource, pInvokingClient, pParentRef, pSharePolicy) regmemShareCallback_DISPATCH(pResource, pInvokingClient, pParentRef, pSharePolicy) +#define regmemMapTo(pResource, pParams) regmemMapTo_DISPATCH(pResource, pParams) +#define regmemGetMapAddrSpace(pMemory, pCallContext, mapFlags, pAddrSpace) regmemGetMapAddrSpace_DISPATCH(pMemory, pCallContext, mapFlags, pAddrSpace) +#define regmemGetRefCount(pResource) regmemGetRefCount_DISPATCH(pResource) +#define regmemAddAdditionalDependants(pClient, pResource, pReference) regmemAddAdditionalDependants_DISPATCH(pClient, pResource, pReference) +#define regmemControl_Prologue(pResource, pCallContext, pParams) regmemControl_Prologue_DISPATCH(pResource, pCallContext, pParams) +#define regmemIsGpuMapAllowed(pMemory, pGpu) regmemIsGpuMapAllowed_DISPATCH(pMemory, pGpu) +#define regmemUnmapFrom(pResource, pParams) regmemUnmapFrom_DISPATCH(pResource, pParams) +#define regmemControl_Epilogue(pResource, pCallContext, pParams) regmemControl_Epilogue_DISPATCH(pResource, pCallContext, pParams) +#define regmemControlLookup(pResource, pParams, ppEntry) regmemControlLookup_DISPATCH(pResource, pParams, ppEntry) #define regmemControl(pMemory, pCallContext, pParams) regmemControl_DISPATCH(pMemory, pCallContext, pParams) #define regmemUnmap(pMemory, pCallContext, pCpuMapping) regmemUnmap_DISPATCH(pMemory, pCallContext, pCpuMapping) #define regmemGetMemInterMapParams(pMemory, pParams) regmemGetMemInterMapParams_DISPATCH(pMemory, pParams) #define regmemGetMemoryMappingDescriptor(pMemory, ppMemDesc) regmemGetMemoryMappingDescriptor_DISPATCH(pMemory, ppMemDesc) -#define regmemGetMapAddrSpace(pMemory, pCallContext, mapFlags, pAddrSpace) regmemGetMapAddrSpace_DISPATCH(pMemory, pCallContext, mapFlags, pAddrSpace) -#define regmemShareCallback(pResource, pInvokingClient, pParentRef, pSharePolicy) regmemShareCallback_DISPATCH(pResource, pInvokingClient, pParentRef, pSharePolicy) #define regmemControlFilter(pResource, pCallContext, pParams) regmemControlFilter_DISPATCH(pResource, pCallContext, pParams) -#define regmemAddAdditionalDependants(pClient, pResource, pReference) regmemAddAdditionalDependants_DISPATCH(pClient, pResource, pReference) -#define regmemGetRefCount(pResource) regmemGetRefCount_DISPATCH(pResource) -#define regmemMapTo(pResource, pParams) regmemMapTo_DISPATCH(pResource, pParams) -#define regmemControl_Prologue(pResource, pCallContext, pParams) regmemControl_Prologue_DISPATCH(pResource, pCallContext, pParams) -#define regmemIsGpuMapAllowed(pMemory, pGpu) regmemIsGpuMapAllowed_DISPATCH(pMemory, pGpu) +#define regmemControlSerialization_Prologue(pResource, pCallContext, pParams) regmemControlSerialization_Prologue_DISPATCH(pResource, pCallContext, pParams) #define regmemIsReady(pMemory, bCopyConstructorContext) regmemIsReady_DISPATCH(pMemory, bCopyConstructorContext) -#define regmemCheckCopyPermissions(pMemory, pDstGpu, hDstClientNvBool) regmemCheckCopyPermissions_DISPATCH(pMemory, pDstGpu, hDstClientNvBool) +#define regmemCheckCopyPermissions(pMemory, pDstGpu, pDstDevice) regmemCheckCopyPermissions_DISPATCH(pMemory, pDstGpu, pDstDevice) #define regmemPreDestruct(pResource) regmemPreDestruct_DISPATCH(pResource) #define regmemIsDuplicate(pMemory, hMemory, pDuplicate) regmemIsDuplicate_DISPATCH(pMemory, hMemory, pDuplicate) -#define regmemUnmapFrom(pResource, pParams) regmemUnmapFrom_DISPATCH(pResource, pParams) -#define regmemControl_Epilogue(pResource, pCallContext, pParams) regmemControl_Epilogue_DISPATCH(pResource, pCallContext, pParams) -#define regmemControlLookup(pResource, pParams, ppEntry) regmemControlLookup_DISPATCH(pResource, pParams, ppEntry) +#define regmemControlSerialization_Epilogue(pResource, pCallContext, pParams) regmemControlSerialization_Epilogue_DISPATCH(pResource, pCallContext, pParams) #define regmemMap(pMemory, pCallContext, pParams, pCpuMapping) regmemMap_DISPATCH(pMemory, pCallContext, pParams, pCpuMapping) #define regmemAccessCallback(pResource, pInvokingClient, pAllocParams, accessRight) regmemAccessCallback_DISPATCH(pResource, pInvokingClient, pAllocParams, accessRight) NvBool regmemCanCopy_IMPL(struct RegisterMemory *pRegisterMemory); @@ -141,60 +145,76 @@ return pMemory->__regmemCheckMemInterUnmap__(pMemory, bSubdeviceHandleProvided); } -static inline NV_STATUS regmemControl_DISPATCH(struct RegisterMemory *pMemory, CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { - return pMemory->__regmemControl__(pMemory, pCallContext, pParams); +static inline NvBool regmemShareCallback_DISPATCH(struct RegisterMemory *pResource, struct RsClient *pInvokingClient, struct RsResourceRef *pParentRef, RS_SHARE_POLICY *pSharePolicy) { + return pResource->__regmemShareCallback__(pResource, pInvokingClient, pParentRef, pSharePolicy); } -static inline NV_STATUS regmemUnmap_DISPATCH(struct RegisterMemory *pMemory, CALL_CONTEXT *pCallContext, RsCpuMapping *pCpuMapping) { - return pMemory->__regmemUnmap__(pMemory, pCallContext, pCpuMapping); +static inline NV_STATUS regmemMapTo_DISPATCH(struct RegisterMemory *pResource, RS_RES_MAP_TO_PARAMS *pParams) { + return pResource->__regmemMapTo__(pResource, pParams); } -static inline NV_STATUS regmemGetMemInterMapParams_DISPATCH(struct RegisterMemory *pMemory, RMRES_MEM_INTER_MAP_PARAMS *pParams) { - return pMemory->__regmemGetMemInterMapParams__(pMemory, pParams); +static inline NV_STATUS regmemGetMapAddrSpace_DISPATCH(struct RegisterMemory *pMemory, CALL_CONTEXT *pCallContext, NvU32 mapFlags, NV_ADDRESS_SPACE *pAddrSpace) { + return pMemory->__regmemGetMapAddrSpace__(pMemory, pCallContext, mapFlags, pAddrSpace); } -static inline NV_STATUS regmemGetMemoryMappingDescriptor_DISPATCH(struct RegisterMemory *pMemory, MEMORY_DESCRIPTOR **ppMemDesc) { - return pMemory->__regmemGetMemoryMappingDescriptor__(pMemory, ppMemDesc); +static inline NvU32 regmemGetRefCount_DISPATCH(struct RegisterMemory *pResource) { + return pResource->__regmemGetRefCount__(pResource); } -static inline NV_STATUS regmemGetMapAddrSpace_DISPATCH(struct RegisterMemory *pMemory, CALL_CONTEXT *pCallContext, NvU32 mapFlags, NV_ADDRESS_SPACE *pAddrSpace) { - return pMemory->__regmemGetMapAddrSpace__(pMemory, pCallContext, mapFlags, pAddrSpace); +static inline void regmemAddAdditionalDependants_DISPATCH(struct RsClient *pClient, struct RegisterMemory *pResource, RsResourceRef *pReference) { + pResource->__regmemAddAdditionalDependants__(pClient, pResource, pReference); } -static inline NvBool regmemShareCallback_DISPATCH(struct RegisterMemory *pResource, struct RsClient *pInvokingClient, struct RsResourceRef *pParentRef, RS_SHARE_POLICY *pSharePolicy) { - return pResource->__regmemShareCallback__(pResource, pInvokingClient, pParentRef, pSharePolicy); +static inline NV_STATUS regmemControl_Prologue_DISPATCH(struct RegisterMemory *pResource, CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return pResource->__regmemControl_Prologue__(pResource, pCallContext, pParams); } -static inline NV_STATUS regmemControlFilter_DISPATCH(struct RegisterMemory *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { - return pResource->__regmemControlFilter__(pResource, pCallContext, pParams); +static inline NvBool regmemIsGpuMapAllowed_DISPATCH(struct RegisterMemory *pMemory, struct OBJGPU *pGpu) { + return pMemory->__regmemIsGpuMapAllowed__(pMemory, pGpu); } -static inline void regmemAddAdditionalDependants_DISPATCH(struct RsClient *pClient, struct RegisterMemory *pResource, RsResourceRef *pReference) { - pResource->__regmemAddAdditionalDependants__(pClient, pResource, pReference); +static inline NV_STATUS regmemUnmapFrom_DISPATCH(struct RegisterMemory *pResource, RS_RES_UNMAP_FROM_PARAMS *pParams) { + return pResource->__regmemUnmapFrom__(pResource, pParams); } -static inline NvU32 regmemGetRefCount_DISPATCH(struct RegisterMemory *pResource) { - return pResource->__regmemGetRefCount__(pResource); +static inline void regmemControl_Epilogue_DISPATCH(struct RegisterMemory *pResource, CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + pResource->__regmemControl_Epilogue__(pResource, pCallContext, pParams); } -static inline NV_STATUS regmemMapTo_DISPATCH(struct RegisterMemory *pResource, RS_RES_MAP_TO_PARAMS *pParams) { - return pResource->__regmemMapTo__(pResource, pParams); +static inline NV_STATUS regmemControlLookup_DISPATCH(struct RegisterMemory *pResource, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams, const struct NVOC_EXPORTED_METHOD_DEF **ppEntry) { + return pResource->__regmemControlLookup__(pResource, pParams, ppEntry); } -static inline NV_STATUS regmemControl_Prologue_DISPATCH(struct RegisterMemory *pResource, CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { - return pResource->__regmemControl_Prologue__(pResource, pCallContext, pParams); +static inline NV_STATUS regmemControl_DISPATCH(struct RegisterMemory *pMemory, CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return pMemory->__regmemControl__(pMemory, pCallContext, pParams); } -static inline NvBool regmemIsGpuMapAllowed_DISPATCH(struct RegisterMemory *pMemory, struct OBJGPU *pGpu) { - return pMemory->__regmemIsGpuMapAllowed__(pMemory, pGpu); +static inline NV_STATUS regmemUnmap_DISPATCH(struct RegisterMemory *pMemory, CALL_CONTEXT *pCallContext, RsCpuMapping *pCpuMapping) { + return pMemory->__regmemUnmap__(pMemory, pCallContext, pCpuMapping); +} + +static inline NV_STATUS regmemGetMemInterMapParams_DISPATCH(struct RegisterMemory *pMemory, RMRES_MEM_INTER_MAP_PARAMS *pParams) { + return pMemory->__regmemGetMemInterMapParams__(pMemory, pParams); +} + +static inline NV_STATUS regmemGetMemoryMappingDescriptor_DISPATCH(struct RegisterMemory *pMemory, MEMORY_DESCRIPTOR **ppMemDesc) { + return pMemory->__regmemGetMemoryMappingDescriptor__(pMemory, ppMemDesc); +} + +static inline NV_STATUS regmemControlFilter_DISPATCH(struct RegisterMemory *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return pResource->__regmemControlFilter__(pResource, pCallContext, pParams); +} + +static inline NV_STATUS regmemControlSerialization_Prologue_DISPATCH(struct RegisterMemory *pResource, CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return pResource->__regmemControlSerialization_Prologue__(pResource, pCallContext, pParams); } static inline NV_STATUS regmemIsReady_DISPATCH(struct RegisterMemory *pMemory, NvBool bCopyConstructorContext) { return pMemory->__regmemIsReady__(pMemory, bCopyConstructorContext); } -static inline NV_STATUS regmemCheckCopyPermissions_DISPATCH(struct RegisterMemory *pMemory, struct OBJGPU *pDstGpu, NvHandle hDstClientNvBool) { - return pMemory->__regmemCheckCopyPermissions__(pMemory, pDstGpu, hDstClientNvBool); +static inline NV_STATUS regmemCheckCopyPermissions_DISPATCH(struct RegisterMemory *pMemory, struct OBJGPU *pDstGpu, struct Device *pDstDevice) { + return pMemory->__regmemCheckCopyPermissions__(pMemory, pDstGpu, pDstDevice); } static inline void regmemPreDestruct_DISPATCH(struct RegisterMemory *pResource) { @@ -205,16 +225,8 @@ return pMemory->__regmemIsDuplicate__(pMemory, hMemory, pDuplicate); } -static inline NV_STATUS regmemUnmapFrom_DISPATCH(struct RegisterMemory *pResource, RS_RES_UNMAP_FROM_PARAMS *pParams) { - return pResource->__regmemUnmapFrom__(pResource, pParams); -} - -static inline void regmemControl_Epilogue_DISPATCH(struct RegisterMemory *pResource, CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { - pResource->__regmemControl_Epilogue__(pResource, pCallContext, pParams); -} - -static inline NV_STATUS regmemControlLookup_DISPATCH(struct RegisterMemory *pResource, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams, const struct NVOC_EXPORTED_METHOD_DEF **ppEntry) { - return pResource->__regmemControlLookup__(pResource, pParams, ppEntry); +static inline void regmemControlSerialization_Epilogue_DISPATCH(struct RegisterMemory *pResource, CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + pResource->__regmemControlSerialization_Epilogue__(pResource, pCallContext, pParams); } static inline NV_STATUS regmemMap_DISPATCH(struct RegisterMemory *pMemory, CALL_CONTEXT *pCallContext, struct RS_CPU_MAP_PARAMS *pParams, RsCpuMapping *pCpuMapping) { diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/generated/g_resource_fwd_decls_nvoc.h nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_resource_fwd_decls_nvoc.h --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/generated/g_resource_fwd_decls_nvoc.h 2023-10-25 20:27:18.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_resource_fwd_decls_nvoc.h 2024-03-05 22:18:42.000000000 +0000 @@ -310,6 +310,17 @@ #define __nvoc_class_id_EventBuffer 0x63502b #endif /* __nvoc_class_id_EventBuffer */ +struct SemaphoreSurface; + +#ifndef __NVOC_CLASS_SemaphoreSurface_TYPEDEF__ +#define __NVOC_CLASS_SemaphoreSurface_TYPEDEF__ +typedef struct SemaphoreSurface SemaphoreSurface; +#endif /* __NVOC_CLASS_SemaphoreSurface_TYPEDEF__ */ + +#ifndef __nvoc_class_id_SemaphoreSurface +#define __nvoc_class_id_SemaphoreSurface 0xeabc69 +#endif /* __nvoc_class_id_SemaphoreSurface */ + struct P2PApi; #ifndef __NVOC_CLASS_P2PApi_TYPEDEF__ @@ -508,6 +519,17 @@ #define __nvoc_class_id_VideoMemory 0xed948f #endif /* __nvoc_class_id_VideoMemory */ +struct ExtendedGpuMemory; + +#ifndef __NVOC_CLASS_ExtendedGpuMemory_TYPEDEF__ +#define __NVOC_CLASS_ExtendedGpuMemory_TYPEDEF__ +typedef struct ExtendedGpuMemory ExtendedGpuMemory; +#endif /* __NVOC_CLASS_ExtendedGpuMemory_TYPEDEF__ */ + +#ifndef __nvoc_class_id_ExtendedGpuMemory +#define __nvoc_class_id_ExtendedGpuMemory 0xeffa5c +#endif /* __nvoc_class_id_ExtendedGpuMemory */ + struct PhysicalMemory; #ifndef __NVOC_CLASS_PhysicalMemory_TYPEDEF__ @@ -805,6 +827,17 @@ #define __nvoc_class_id_AccessCounterBuffer 0x1f0074 #endif /* __nvoc_class_id_AccessCounterBuffer */ +struct VidmemAccessBitBuffer; + +#ifndef __NVOC_CLASS_VidmemAccessBitBuffer_TYPEDEF__ +#define __NVOC_CLASS_VidmemAccessBitBuffer_TYPEDEF__ +typedef struct VidmemAccessBitBuffer VidmemAccessBitBuffer; +#endif /* __NVOC_CLASS_VidmemAccessBitBuffer_TYPEDEF__ */ + +#ifndef __nvoc_class_id_VidmemAccessBitBuffer +#define __nvoc_class_id_VidmemAccessBitBuffer 0xebb6da +#endif /* __nvoc_class_id_VidmemAccessBitBuffer */ + struct GPUInstanceSubscription; #ifndef __NVOC_CLASS_GPUInstanceSubscription_TYPEDEF__ @@ -1025,6 +1058,17 @@ #define __nvoc_class_id_MsencContext 0x88c92a #endif /* __nvoc_class_id_MsencContext */ +struct Sec2Context; + +#ifndef __NVOC_CLASS_Sec2Context_TYPEDEF__ +#define __NVOC_CLASS_Sec2Context_TYPEDEF__ +typedef struct Sec2Context Sec2Context; +#endif /* __NVOC_CLASS_Sec2Context_TYPEDEF__ */ + +#ifndef __nvoc_class_id_Sec2Context +#define __nvoc_class_id_Sec2Context 0x4c3439 +#endif /* __nvoc_class_id_Sec2Context */ + struct KernelGraphicsObject; #ifndef __NVOC_CLASS_KernelGraphicsObject_TYPEDEF__ @@ -1058,6 +1102,17 @@ #define __nvoc_class_id_Event 0xa4ecfc #endif /* __nvoc_class_id_Event */ +struct ConfidentialComputeApi; + +#ifndef __NVOC_CLASS_ConfidentialComputeApi_TYPEDEF__ +#define __NVOC_CLASS_ConfidentialComputeApi_TYPEDEF__ +typedef struct ConfidentialComputeApi ConfidentialComputeApi; +#endif /* __NVOC_CLASS_ConfidentialComputeApi_TYPEDEF__ */ + +#ifndef __nvoc_class_id_ConfidentialComputeApi +#define __nvoc_class_id_ConfidentialComputeApi 0xea5cb0 +#endif /* __nvoc_class_id_ConfidentialComputeApi */ + struct KernelCcuApi; #ifndef __NVOC_CLASS_KernelCcuApi_TYPEDEF__ @@ -1080,6 +1135,7 @@ struct FmSessionApi *PRIVATE_FIELD(FmSessionApi_FABRIC_MANAGER_SESSION); struct GpuManagementApi *PRIVATE_FIELD(GpuManagementApi_NV0020_GPU_MANAGEMENT); struct EventBuffer *PRIVATE_FIELD(EventBuffer_NV_EVENT_BUFFER); + struct SemaphoreSurface *PRIVATE_FIELD(SemaphoreSurface_NV_SEMAPHORE_SURFACE); struct P2PApi *PRIVATE_FIELD(P2PApi_NV50_P2P); struct SyncGpuBoost *PRIVATE_FIELD(SyncGpuBoost_NV0060_SYNC_GPU_BOOST); struct Device *PRIVATE_FIELD(Device_NV01_DEVICE_0); @@ -1107,6 +1163,7 @@ struct KernelChannelGroupApi *PRIVATE_FIELD(KernelChannelGroupApi_KEPLER_CHANNEL_GROUP_A); struct RegisterMemory *PRIVATE_FIELD(RegisterMemory_NV01_MEMORY_LOCAL_PRIVILEGED); struct VideoMemory *PRIVATE_FIELD(VideoMemory_NV01_MEMORY_LOCAL_USER); + struct ExtendedGpuMemory *PRIVATE_FIELD(ExtendedGpuMemory_NV_MEMORY_EXTENDED_USER); struct PhysicalMemory *PRIVATE_FIELD(PhysicalMemory_NV01_MEMORY_LOCAL_PHYSICAL); struct VirtualMemory *PRIVATE_FIELD(VirtualMemory_NV50_MEMORY_VIRTUAL); struct SystemMemory *PRIVATE_FIELD(SystemMemory_NV01_MEMORY_SYSTEM); @@ -1127,6 +1184,7 @@ struct KernelHostVgpuDeviceApi *PRIVATE_FIELD(KernelHostVgpuDeviceApi_NVA084_KERNEL_HOST_VGPU_DEVICE); struct ThirdPartyP2P *PRIVATE_FIELD(ThirdPartyP2P_NV50_THIRD_PARTY_P2P); struct GenericEngineApi *PRIVATE_FIELD(GenericEngineApi_GF100_SUBDEVICE_MASTER); + struct GenericEngineApi *PRIVATE_FIELD(GenericEngineApi_GF100_SUBDEVICE_INFOROM); struct TimerApi *PRIVATE_FIELD(TimerApi_NV01_TIMER); struct I2cApi *PRIVATE_FIELD(I2cApi_NV40_I2C); struct DiagApi *PRIVATE_FIELD(DiagApi_NV20_SUBDEVICE_DIAG); @@ -1142,6 +1200,7 @@ struct DispSfUser *PRIVATE_FIELD(DispSfUser_NVC771_DISP_SF_USER); struct MmuFaultBuffer *PRIVATE_FIELD(MmuFaultBuffer_MMU_FAULT_BUFFER); struct AccessCounterBuffer *PRIVATE_FIELD(AccessCounterBuffer_ACCESS_COUNTER_NOTIFY_BUFFER); + struct VidmemAccessBitBuffer *PRIVATE_FIELD(VidmemAccessBitBuffer_MMU_VIDMEM_ACCESS_BIT_BUFFER); struct GPUInstanceSubscription *PRIVATE_FIELD(GPUInstanceSubscription_AMPERE_SMC_PARTITION_REF); struct ComputeInstanceSubscription *PRIVATE_FIELD(ComputeInstanceSubscription_AMPERE_SMC_EXEC_PARTITION_REF); struct MIGConfigSession *PRIVATE_FIELD(MIGConfigSession_AMPERE_SMC_CONFIG_SESSION); @@ -1193,6 +1252,7 @@ struct MsencContext *PRIVATE_FIELD(MsencContext_NVB4B7_VIDEO_ENCODER); struct MsencContext *PRIVATE_FIELD(MsencContext_NVC7B7_VIDEO_ENCODER); struct MsencContext *PRIVATE_FIELD(MsencContext_NVC9B7_VIDEO_ENCODER); + struct Sec2Context *PRIVATE_FIELD(Sec2Context_HOPPER_SEC2_WORK_LAUNCH_A); struct KernelGraphicsObject *PRIVATE_FIELD(KernelGraphicsObject_AMPERE_A); struct KernelGraphicsObject *PRIVATE_FIELD(KernelGraphicsObject_AMPERE_COMPUTE_A); struct KernelGraphicsObject *PRIVATE_FIELD(KernelGraphicsObject_AMPERE_B); @@ -1210,6 +1270,7 @@ struct Event *PRIVATE_FIELD(Event_NV01_EVENT_OS_EVENT); struct Event *PRIVATE_FIELD(Event_NV01_EVENT_KERNEL_CALLBACK); struct Event *PRIVATE_FIELD(Event_NV01_EVENT_KERNEL_CALLBACK_EX); + struct ConfidentialComputeApi *PRIVATE_FIELD(ConfidentialComputeApi_NV_CONFIDENTIAL_COMPUTE); struct KernelCcuApi *PRIVATE_FIELD(KernelCcuApi_NV_COUNTER_COLLECTION_UNIT); }; diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/generated/g_resource_nvoc.c nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_resource_nvoc.c --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/generated/g_resource_nvoc.c 2023-10-25 20:27:18.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_resource_nvoc.c 2024-03-05 22:18:43.000000000 +0000 @@ -166,6 +166,14 @@ return rmresShareCallback((struct RmResource *)(((unsigned char *)pResource) - __nvoc_rtti_RmResource_RsResource.offset), pInvokingClient, pParentRef, pSharePolicy); } +static NV_STATUS __nvoc_thunk_RmResource_resControlSerialization_Prologue(struct RsResource *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return rmresControlSerialization_Prologue((struct RmResource *)(((unsigned char *)pResource) - __nvoc_rtti_RmResource_RsResource.offset), pCallContext, pParams); +} + +static void __nvoc_thunk_RmResource_resControlSerialization_Epilogue(struct RsResource *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + rmresControlSerialization_Epilogue((struct RmResource *)(((unsigned char *)pResource) - __nvoc_rtti_RmResource_RsResource.offset), pCallContext, pParams); +} + static NV_STATUS __nvoc_thunk_RmResource_resControl_Prologue(struct RsResource *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { return rmresControl_Prologue((struct RmResource *)(((unsigned char *)pResource) - __nvoc_rtti_RmResource_RsResource.offset), pCallContext, pParams); } @@ -277,6 +285,10 @@ pThis->__rmresGetMemoryMappingDescriptor__ = &rmresGetMemoryMappingDescriptor_IMPL; + pThis->__rmresControlSerialization_Prologue__ = &rmresControlSerialization_Prologue_IMPL; + + pThis->__rmresControlSerialization_Epilogue__ = &rmresControlSerialization_Epilogue_IMPL; + pThis->__rmresControl_Prologue__ = &rmresControl_Prologue_IMPL; pThis->__rmresControl_Epilogue__ = &rmresControl_Epilogue_IMPL; @@ -285,6 +297,10 @@ pThis->__nvoc_base_RsResource.__resShareCallback__ = &__nvoc_thunk_RmResource_resShareCallback; + pThis->__nvoc_base_RsResource.__resControlSerialization_Prologue__ = &__nvoc_thunk_RmResource_resControlSerialization_Prologue; + + pThis->__nvoc_base_RsResource.__resControlSerialization_Epilogue__ = &__nvoc_thunk_RmResource_resControlSerialization_Epilogue; + pThis->__nvoc_base_RsResource.__resControl_Prologue__ = &__nvoc_thunk_RmResource_resControl_Prologue; pThis->__nvoc_base_RsResource.__resControl_Epilogue__ = &__nvoc_thunk_RmResource_resControl_Epilogue; @@ -335,13 +351,16 @@ Object *pParentObj; RmResource *pThis; - pThis = portMemAllocNonPaged(sizeof(RmResource)); - if (pThis == NULL) return NV_ERR_NO_MEMORY; + status = __nvoc_handleObjCreateMemAlloc(createFlags, sizeof(RmResource), (void**)&pThis, (void**)ppThis); + if (status != NV_OK) + return status; portMemSet(pThis, 0, sizeof(RmResource)); __nvoc_initRtti(staticCast(pThis, Dynamic), &__nvoc_class_def_RmResource); + pThis->__nvoc_base_RsResource.__nvoc_base_Object.createFlags = createFlags; + if (pParent != NULL && !(createFlags & NVOC_OBJ_CREATE_FLAGS_PARENT_HALSPEC_ONLY)) { pParentObj = dynamicCast(pParent, Object); @@ -357,11 +376,17 @@ if (status != NV_OK) goto __nvoc_objCreate_RmResource_cleanup; *ppThis = pThis; + return NV_OK; __nvoc_objCreate_RmResource_cleanup: // do not call destructors here since the constructor already called them - portMemFree(pThis); + if (createFlags & NVOC_OBJ_CREATE_FLAGS_IN_PLACE_CONSTRUCT) + portMemSet(pThis, 0, sizeof(RmResource)); + else + portMemFree(pThis); + + // coverity[leaked_storage:FALSE] return status; } diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/generated/g_resource_nvoc.h nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_resource_nvoc.h --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/generated/g_resource_nvoc.h 2023-10-25 20:27:18.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_resource_nvoc.h 2024-03-05 22:18:43.000000000 +0000 @@ -193,6 +193,8 @@ NV_STATUS (*__rmresGetMemInterMapParams__)(struct RmResource *, RMRES_MEM_INTER_MAP_PARAMS *); NV_STATUS (*__rmresCheckMemInterUnmap__)(struct RmResource *, NvBool); NV_STATUS (*__rmresGetMemoryMappingDescriptor__)(struct RmResource *, struct MEMORY_DESCRIPTOR **); + NV_STATUS (*__rmresControlSerialization_Prologue__)(struct RmResource *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); + void (*__rmresControlSerialization_Epilogue__)(struct RmResource *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); NV_STATUS (*__rmresControl_Prologue__)(struct RmResource *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); void (*__rmresControl_Epilogue__)(struct RmResource *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); NV_STATUS (*__rmresControl__)(struct RmResource *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); @@ -244,6 +246,8 @@ #define rmresGetMemInterMapParams(pRmResource, pParams) rmresGetMemInterMapParams_DISPATCH(pRmResource, pParams) #define rmresCheckMemInterUnmap(pRmResource, bSubdeviceHandleProvided) rmresCheckMemInterUnmap_DISPATCH(pRmResource, bSubdeviceHandleProvided) #define rmresGetMemoryMappingDescriptor(pRmResource, ppMemDesc) rmresGetMemoryMappingDescriptor_DISPATCH(pRmResource, ppMemDesc) +#define rmresControlSerialization_Prologue(pResource, pCallContext, pParams) rmresControlSerialization_Prologue_DISPATCH(pResource, pCallContext, pParams) +#define rmresControlSerialization_Epilogue(pResource, pCallContext, pParams) rmresControlSerialization_Epilogue_DISPATCH(pResource, pCallContext, pParams) #define rmresControl_Prologue(pResource, pCallContext, pParams) rmresControl_Prologue_DISPATCH(pResource, pCallContext, pParams) #define rmresControl_Epilogue(pResource, pCallContext, pParams) rmresControl_Epilogue_DISPATCH(pResource, pCallContext, pParams) #define rmresControl(pResource, pCallContext, pParams) rmresControl_DISPATCH(pResource, pCallContext, pParams) @@ -288,6 +292,18 @@ return pRmResource->__rmresGetMemoryMappingDescriptor__(pRmResource, ppMemDesc); } +NV_STATUS rmresControlSerialization_Prologue_IMPL(struct RmResource *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams); + +static inline NV_STATUS rmresControlSerialization_Prologue_DISPATCH(struct RmResource *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return pResource->__rmresControlSerialization_Prologue__(pResource, pCallContext, pParams); +} + +void rmresControlSerialization_Epilogue_IMPL(struct RmResource *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams); + +static inline void rmresControlSerialization_Epilogue_DISPATCH(struct RmResource *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + pResource->__rmresControlSerialization_Epilogue__(pResource, pCallContext, pParams); +} + NV_STATUS rmresControl_Prologue_IMPL(struct RmResource *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams); static inline NV_STATUS rmresControl_Prologue_DISPATCH(struct RmResource *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/generated/g_resserv_nvoc.h nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_resserv_nvoc.h --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/generated/g_resserv_nvoc.h 2023-10-25 20:27:18.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_resserv_nvoc.h 2024-03-05 22:18:43.000000000 +0000 @@ -211,6 +211,7 @@ #define RS_LOCK_FLAGS_NO_CUSTOM_LOCK_3 NVBIT(4) #define RS_LOCK_FLAGS_NO_DEPENDANT_SESSION_LOCK NVBIT(5) #define RS_LOCK_FLAGS_FREE_SESSION_LOCK NVBIT(6) +#define RS_LOCK_FLAGS_LOW_PRIORITY NVBIT(7) /// RS_LOCK_STATE #define RS_LOCK_STATE_TOP_LOCK_ACQUIRED NVBIT(0) @@ -230,7 +231,7 @@ #define RS_LOCK_RELEASE_SESSION_LOCK NVBIT(5) /// API enumerations used for locking knobs -typedef enum +typedef enum { RS_LOCK_CLIENT =0, RS_LOCK_TOP =1, @@ -238,7 +239,7 @@ RS_LOCK_CUSTOM_3 =3, } RS_LOCK_ENUM; -typedef enum +typedef enum { RS_API_ALLOC_CLIENT = 0, RS_API_ALLOC_RESOURCE = 1, @@ -317,6 +318,13 @@ RS_LOCK_INFO *pLockInfo; ///< Saved locking context information for the call API_SECURITY_INFO secInfo; RS_RES_CONTROL_PARAMS_INTERNAL *pControlParams; ///< parameters of the call [optional] + + void *pSerializedParams; ///< Serialized version of the params + void *pDeserializedParams; ///< Deserialized version of the params + NvU32 serializedSize; ///< Serialized size + NvU32 deserializedSize; ///< Deserialized size + NvBool bReserialize; ///< Reserialize before calling into GSP + NvBool bLocalSerialization; ///< Serialized internally }; typedef enum { @@ -395,7 +403,7 @@ } while(0) #else -#define RS_LOCK_VALIDATOR_INIT(lock, lockClass, inst) +#define RS_LOCK_VALIDATOR_INIT(lock, lockClass, inst) #define RS_RWLOCK_ACQUIRE_READ(lock, validator) do { portSyncRwLockAcquireRead((lock)); } while(0) #define RS_RWLOCK_ACQUIRE_WRITE(lock, validator) do { portSyncRwLockAcquireWrite((lock)); } while(0) #define RS_RWLOCK_RELEASE_READ_EXT(lock, validator, bOutOfOrder) do { portSyncRwLockReleaseRead((lock)); } while(0) diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/generated/g_rg_line_callback_nvoc.c nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_rg_line_callback_nvoc.c --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/generated/g_rg_line_callback_nvoc.c 2023-10-25 20:27:18.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_rg_line_callback_nvoc.c 2024-03-05 22:18:43.000000000 +0000 @@ -97,84 +97,92 @@ return gpuresShareCallback((struct GpuResource *)(((unsigned char *)pGpuResource) + __nvoc_rtti_RgLineCallback_GpuResource.offset), pInvokingClient, pParentRef, pSharePolicy); } -static NV_STATUS __nvoc_thunk_GpuResource_rglcbControl(struct RgLineCallback *pGpuResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { - return gpuresControl((struct GpuResource *)(((unsigned char *)pGpuResource) + __nvoc_rtti_RgLineCallback_GpuResource.offset), pCallContext, pParams); +static NV_STATUS __nvoc_thunk_RmResource_rglcbCheckMemInterUnmap(struct RgLineCallback *pRmResource, NvBool bSubdeviceHandleProvided) { + return rmresCheckMemInterUnmap((struct RmResource *)(((unsigned char *)pRmResource) + __nvoc_rtti_RgLineCallback_RmResource.offset), bSubdeviceHandleProvided); } -static NV_STATUS __nvoc_thunk_GpuResource_rglcbUnmap(struct RgLineCallback *pGpuResource, struct CALL_CONTEXT *pCallContext, struct RsCpuMapping *pCpuMapping) { - return gpuresUnmap((struct GpuResource *)(((unsigned char *)pGpuResource) + __nvoc_rtti_RgLineCallback_GpuResource.offset), pCallContext, pCpuMapping); +static NV_STATUS __nvoc_thunk_RsResource_rglcbMapTo(struct RgLineCallback *pResource, RS_RES_MAP_TO_PARAMS *pParams) { + return resMapTo((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_RgLineCallback_RsResource.offset), pParams); } -static NV_STATUS __nvoc_thunk_RmResource_rglcbGetMemInterMapParams(struct RgLineCallback *pRmResource, RMRES_MEM_INTER_MAP_PARAMS *pParams) { - return rmresGetMemInterMapParams((struct RmResource *)(((unsigned char *)pRmResource) + __nvoc_rtti_RgLineCallback_RmResource.offset), pParams); +static NV_STATUS __nvoc_thunk_GpuResource_rglcbGetMapAddrSpace(struct RgLineCallback *pGpuResource, struct CALL_CONTEXT *pCallContext, NvU32 mapFlags, NV_ADDRESS_SPACE *pAddrSpace) { + return gpuresGetMapAddrSpace((struct GpuResource *)(((unsigned char *)pGpuResource) + __nvoc_rtti_RgLineCallback_GpuResource.offset), pCallContext, mapFlags, pAddrSpace); } -static NV_STATUS __nvoc_thunk_RmResource_rglcbGetMemoryMappingDescriptor(struct RgLineCallback *pRmResource, struct MEMORY_DESCRIPTOR **ppMemDesc) { - return rmresGetMemoryMappingDescriptor((struct RmResource *)(((unsigned char *)pRmResource) + __nvoc_rtti_RgLineCallback_RmResource.offset), ppMemDesc); +static NvU32 __nvoc_thunk_RsResource_rglcbGetRefCount(struct RgLineCallback *pResource) { + return resGetRefCount((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_RgLineCallback_RsResource.offset)); } -static NV_STATUS __nvoc_thunk_GpuResource_rglcbGetMapAddrSpace(struct RgLineCallback *pGpuResource, struct CALL_CONTEXT *pCallContext, NvU32 mapFlags, NV_ADDRESS_SPACE *pAddrSpace) { - return gpuresGetMapAddrSpace((struct GpuResource *)(((unsigned char *)pGpuResource) + __nvoc_rtti_RgLineCallback_GpuResource.offset), pCallContext, mapFlags, pAddrSpace); +static void __nvoc_thunk_RsResource_rglcbAddAdditionalDependants(struct RsClient *pClient, struct RgLineCallback *pResource, RsResourceRef *pReference) { + resAddAdditionalDependants(pClient, (struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_RgLineCallback_RsResource.offset), pReference); } -static NvHandle __nvoc_thunk_GpuResource_rglcbGetInternalObjectHandle(struct RgLineCallback *pGpuResource) { - return gpuresGetInternalObjectHandle((struct GpuResource *)(((unsigned char *)pGpuResource) + __nvoc_rtti_RgLineCallback_GpuResource.offset)); +static NV_STATUS __nvoc_thunk_RmResource_rglcbControl_Prologue(struct RgLineCallback *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return rmresControl_Prologue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_RgLineCallback_RmResource.offset), pCallContext, pParams); } -static NV_STATUS __nvoc_thunk_RsResource_rglcbControlFilter(struct RgLineCallback *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { - return resControlFilter((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_RgLineCallback_RsResource.offset), pCallContext, pParams); +static NV_STATUS __nvoc_thunk_GpuResource_rglcbGetRegBaseOffsetAndSize(struct RgLineCallback *pGpuResource, struct OBJGPU *pGpu, NvU32 *pOffset, NvU32 *pSize) { + return gpuresGetRegBaseOffsetAndSize((struct GpuResource *)(((unsigned char *)pGpuResource) + __nvoc_rtti_RgLineCallback_GpuResource.offset), pGpu, pOffset, pSize); } -static void __nvoc_thunk_RsResource_rglcbAddAdditionalDependants(struct RsClient *pClient, struct RgLineCallback *pResource, RsResourceRef *pReference) { - resAddAdditionalDependants(pClient, (struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_RgLineCallback_RsResource.offset), pReference); +static NV_STATUS __nvoc_thunk_GpuResource_rglcbInternalControlForward(struct RgLineCallback *pGpuResource, NvU32 command, void *pParams, NvU32 size) { + return gpuresInternalControlForward((struct GpuResource *)(((unsigned char *)pGpuResource) + __nvoc_rtti_RgLineCallback_GpuResource.offset), command, pParams, size); } -static NvU32 __nvoc_thunk_RsResource_rglcbGetRefCount(struct RgLineCallback *pResource) { - return resGetRefCount((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_RgLineCallback_RsResource.offset)); +static NV_STATUS __nvoc_thunk_RsResource_rglcbUnmapFrom(struct RgLineCallback *pResource, RS_RES_UNMAP_FROM_PARAMS *pParams) { + return resUnmapFrom((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_RgLineCallback_RsResource.offset), pParams); } -static NV_STATUS __nvoc_thunk_RmResource_rglcbCheckMemInterUnmap(struct RgLineCallback *pRmResource, NvBool bSubdeviceHandleProvided) { - return rmresCheckMemInterUnmap((struct RmResource *)(((unsigned char *)pRmResource) + __nvoc_rtti_RgLineCallback_RmResource.offset), bSubdeviceHandleProvided); +static void __nvoc_thunk_RmResource_rglcbControl_Epilogue(struct RgLineCallback *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + rmresControl_Epilogue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_RgLineCallback_RmResource.offset), pCallContext, pParams); } -static NV_STATUS __nvoc_thunk_RsResource_rglcbMapTo(struct RgLineCallback *pResource, RS_RES_MAP_TO_PARAMS *pParams) { - return resMapTo((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_RgLineCallback_RsResource.offset), pParams); +static NV_STATUS __nvoc_thunk_RsResource_rglcbControlLookup(struct RgLineCallback *pResource, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams, const struct NVOC_EXPORTED_METHOD_DEF **ppEntry) { + return resControlLookup((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_RgLineCallback_RsResource.offset), pParams, ppEntry); } -static NV_STATUS __nvoc_thunk_RmResource_rglcbControl_Prologue(struct RgLineCallback *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { - return rmresControl_Prologue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_RgLineCallback_RmResource.offset), pCallContext, pParams); +static NvHandle __nvoc_thunk_GpuResource_rglcbGetInternalObjectHandle(struct RgLineCallback *pGpuResource) { + return gpuresGetInternalObjectHandle((struct GpuResource *)(((unsigned char *)pGpuResource) + __nvoc_rtti_RgLineCallback_GpuResource.offset)); } -static NV_STATUS __nvoc_thunk_GpuResource_rglcbGetRegBaseOffsetAndSize(struct RgLineCallback *pGpuResource, struct OBJGPU *pGpu, NvU32 *pOffset, NvU32 *pSize) { - return gpuresGetRegBaseOffsetAndSize((struct GpuResource *)(((unsigned char *)pGpuResource) + __nvoc_rtti_RgLineCallback_GpuResource.offset), pGpu, pOffset, pSize); +static NV_STATUS __nvoc_thunk_GpuResource_rglcbControl(struct RgLineCallback *pGpuResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return gpuresControl((struct GpuResource *)(((unsigned char *)pGpuResource) + __nvoc_rtti_RgLineCallback_GpuResource.offset), pCallContext, pParams); } -static NvBool __nvoc_thunk_RsResource_rglcbCanCopy(struct RgLineCallback *pResource) { - return resCanCopy((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_RgLineCallback_RsResource.offset)); +static NV_STATUS __nvoc_thunk_GpuResource_rglcbUnmap(struct RgLineCallback *pGpuResource, struct CALL_CONTEXT *pCallContext, struct RsCpuMapping *pCpuMapping) { + return gpuresUnmap((struct GpuResource *)(((unsigned char *)pGpuResource) + __nvoc_rtti_RgLineCallback_GpuResource.offset), pCallContext, pCpuMapping); } -static NV_STATUS __nvoc_thunk_GpuResource_rglcbInternalControlForward(struct RgLineCallback *pGpuResource, NvU32 command, void *pParams, NvU32 size) { - return gpuresInternalControlForward((struct GpuResource *)(((unsigned char *)pGpuResource) + __nvoc_rtti_RgLineCallback_GpuResource.offset), command, pParams, size); +static NV_STATUS __nvoc_thunk_RmResource_rglcbGetMemInterMapParams(struct RgLineCallback *pRmResource, RMRES_MEM_INTER_MAP_PARAMS *pParams) { + return rmresGetMemInterMapParams((struct RmResource *)(((unsigned char *)pRmResource) + __nvoc_rtti_RgLineCallback_RmResource.offset), pParams); } -static void __nvoc_thunk_RsResource_rglcbPreDestruct(struct RgLineCallback *pResource) { - resPreDestruct((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_RgLineCallback_RsResource.offset)); +static NV_STATUS __nvoc_thunk_RmResource_rglcbGetMemoryMappingDescriptor(struct RgLineCallback *pRmResource, struct MEMORY_DESCRIPTOR **ppMemDesc) { + return rmresGetMemoryMappingDescriptor((struct RmResource *)(((unsigned char *)pRmResource) + __nvoc_rtti_RgLineCallback_RmResource.offset), ppMemDesc); } -static NV_STATUS __nvoc_thunk_RsResource_rglcbUnmapFrom(struct RgLineCallback *pResource, RS_RES_UNMAP_FROM_PARAMS *pParams) { - return resUnmapFrom((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_RgLineCallback_RsResource.offset), pParams); +static NV_STATUS __nvoc_thunk_RsResource_rglcbControlFilter(struct RgLineCallback *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return resControlFilter((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_RgLineCallback_RsResource.offset), pCallContext, pParams); } -static NV_STATUS __nvoc_thunk_RsResource_rglcbIsDuplicate(struct RgLineCallback *pResource, NvHandle hMemory, NvBool *pDuplicate) { - return resIsDuplicate((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_RgLineCallback_RsResource.offset), hMemory, pDuplicate); +static NV_STATUS __nvoc_thunk_RmResource_rglcbControlSerialization_Prologue(struct RgLineCallback *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return rmresControlSerialization_Prologue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_RgLineCallback_RmResource.offset), pCallContext, pParams); } -static void __nvoc_thunk_RmResource_rglcbControl_Epilogue(struct RgLineCallback *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { - rmresControl_Epilogue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_RgLineCallback_RmResource.offset), pCallContext, pParams); +static NvBool __nvoc_thunk_RsResource_rglcbCanCopy(struct RgLineCallback *pResource) { + return resCanCopy((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_RgLineCallback_RsResource.offset)); } -static NV_STATUS __nvoc_thunk_RsResource_rglcbControlLookup(struct RgLineCallback *pResource, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams, const struct NVOC_EXPORTED_METHOD_DEF **ppEntry) { - return resControlLookup((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_RgLineCallback_RsResource.offset), pParams, ppEntry); +static void __nvoc_thunk_RsResource_rglcbPreDestruct(struct RgLineCallback *pResource) { + resPreDestruct((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_RgLineCallback_RsResource.offset)); +} + +static NV_STATUS __nvoc_thunk_RsResource_rglcbIsDuplicate(struct RgLineCallback *pResource, NvHandle hMemory, NvBool *pDuplicate) { + return resIsDuplicate((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_RgLineCallback_RsResource.offset), hMemory, pDuplicate); +} + +static void __nvoc_thunk_RmResource_rglcbControlSerialization_Epilogue(struct RgLineCallback *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + rmresControlSerialization_Epilogue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_RgLineCallback_RmResource.offset), pCallContext, pParams); } static NV_STATUS __nvoc_thunk_GpuResource_rglcbMap(struct RgLineCallback *pGpuResource, struct CALL_CONTEXT *pCallContext, struct RS_CPU_MAP_PARAMS *pParams, struct RsCpuMapping *pCpuMapping) { @@ -226,45 +234,49 @@ pThis->__rglcbShareCallback__ = &__nvoc_thunk_GpuResource_rglcbShareCallback; - pThis->__rglcbControl__ = &__nvoc_thunk_GpuResource_rglcbControl; + pThis->__rglcbCheckMemInterUnmap__ = &__nvoc_thunk_RmResource_rglcbCheckMemInterUnmap; - pThis->__rglcbUnmap__ = &__nvoc_thunk_GpuResource_rglcbUnmap; + pThis->__rglcbMapTo__ = &__nvoc_thunk_RsResource_rglcbMapTo; - pThis->__rglcbGetMemInterMapParams__ = &__nvoc_thunk_RmResource_rglcbGetMemInterMapParams; + pThis->__rglcbGetMapAddrSpace__ = &__nvoc_thunk_GpuResource_rglcbGetMapAddrSpace; - pThis->__rglcbGetMemoryMappingDescriptor__ = &__nvoc_thunk_RmResource_rglcbGetMemoryMappingDescriptor; + pThis->__rglcbGetRefCount__ = &__nvoc_thunk_RsResource_rglcbGetRefCount; - pThis->__rglcbGetMapAddrSpace__ = &__nvoc_thunk_GpuResource_rglcbGetMapAddrSpace; + pThis->__rglcbAddAdditionalDependants__ = &__nvoc_thunk_RsResource_rglcbAddAdditionalDependants; - pThis->__rglcbGetInternalObjectHandle__ = &__nvoc_thunk_GpuResource_rglcbGetInternalObjectHandle; + pThis->__rglcbControl_Prologue__ = &__nvoc_thunk_RmResource_rglcbControl_Prologue; - pThis->__rglcbControlFilter__ = &__nvoc_thunk_RsResource_rglcbControlFilter; + pThis->__rglcbGetRegBaseOffsetAndSize__ = &__nvoc_thunk_GpuResource_rglcbGetRegBaseOffsetAndSize; - pThis->__rglcbAddAdditionalDependants__ = &__nvoc_thunk_RsResource_rglcbAddAdditionalDependants; + pThis->__rglcbInternalControlForward__ = &__nvoc_thunk_GpuResource_rglcbInternalControlForward; - pThis->__rglcbGetRefCount__ = &__nvoc_thunk_RsResource_rglcbGetRefCount; + pThis->__rglcbUnmapFrom__ = &__nvoc_thunk_RsResource_rglcbUnmapFrom; - pThis->__rglcbCheckMemInterUnmap__ = &__nvoc_thunk_RmResource_rglcbCheckMemInterUnmap; + pThis->__rglcbControl_Epilogue__ = &__nvoc_thunk_RmResource_rglcbControl_Epilogue; - pThis->__rglcbMapTo__ = &__nvoc_thunk_RsResource_rglcbMapTo; + pThis->__rglcbControlLookup__ = &__nvoc_thunk_RsResource_rglcbControlLookup; - pThis->__rglcbControl_Prologue__ = &__nvoc_thunk_RmResource_rglcbControl_Prologue; + pThis->__rglcbGetInternalObjectHandle__ = &__nvoc_thunk_GpuResource_rglcbGetInternalObjectHandle; - pThis->__rglcbGetRegBaseOffsetAndSize__ = &__nvoc_thunk_GpuResource_rglcbGetRegBaseOffsetAndSize; + pThis->__rglcbControl__ = &__nvoc_thunk_GpuResource_rglcbControl; - pThis->__rglcbCanCopy__ = &__nvoc_thunk_RsResource_rglcbCanCopy; + pThis->__rglcbUnmap__ = &__nvoc_thunk_GpuResource_rglcbUnmap; - pThis->__rglcbInternalControlForward__ = &__nvoc_thunk_GpuResource_rglcbInternalControlForward; + pThis->__rglcbGetMemInterMapParams__ = &__nvoc_thunk_RmResource_rglcbGetMemInterMapParams; - pThis->__rglcbPreDestruct__ = &__nvoc_thunk_RsResource_rglcbPreDestruct; + pThis->__rglcbGetMemoryMappingDescriptor__ = &__nvoc_thunk_RmResource_rglcbGetMemoryMappingDescriptor; - pThis->__rglcbUnmapFrom__ = &__nvoc_thunk_RsResource_rglcbUnmapFrom; + pThis->__rglcbControlFilter__ = &__nvoc_thunk_RsResource_rglcbControlFilter; - pThis->__rglcbIsDuplicate__ = &__nvoc_thunk_RsResource_rglcbIsDuplicate; + pThis->__rglcbControlSerialization_Prologue__ = &__nvoc_thunk_RmResource_rglcbControlSerialization_Prologue; - pThis->__rglcbControl_Epilogue__ = &__nvoc_thunk_RmResource_rglcbControl_Epilogue; + pThis->__rglcbCanCopy__ = &__nvoc_thunk_RsResource_rglcbCanCopy; - pThis->__rglcbControlLookup__ = &__nvoc_thunk_RsResource_rglcbControlLookup; + pThis->__rglcbPreDestruct__ = &__nvoc_thunk_RsResource_rglcbPreDestruct; + + pThis->__rglcbIsDuplicate__ = &__nvoc_thunk_RsResource_rglcbIsDuplicate; + + pThis->__rglcbControlSerialization_Epilogue__ = &__nvoc_thunk_RmResource_rglcbControlSerialization_Epilogue; pThis->__rglcbMap__ = &__nvoc_thunk_GpuResource_rglcbMap; @@ -292,13 +304,16 @@ Object *pParentObj; RgLineCallback *pThis; - pThis = portMemAllocNonPaged(sizeof(RgLineCallback)); - if (pThis == NULL) return NV_ERR_NO_MEMORY; + status = __nvoc_handleObjCreateMemAlloc(createFlags, sizeof(RgLineCallback), (void**)&pThis, (void**)ppThis); + if (status != NV_OK) + return status; portMemSet(pThis, 0, sizeof(RgLineCallback)); __nvoc_initRtti(staticCast(pThis, Dynamic), &__nvoc_class_def_RgLineCallback); + pThis->__nvoc_base_GpuResource.__nvoc_base_RmResource.__nvoc_base_RsResource.__nvoc_base_Object.createFlags = createFlags; + if (pParent != NULL && !(createFlags & NVOC_OBJ_CREATE_FLAGS_PARENT_HALSPEC_ONLY)) { pParentObj = dynamicCast(pParent, Object); @@ -314,11 +329,17 @@ if (status != NV_OK) goto __nvoc_objCreate_RgLineCallback_cleanup; *ppThis = pThis; + return NV_OK; __nvoc_objCreate_RgLineCallback_cleanup: // do not call destructors here since the constructor already called them - portMemFree(pThis); + if (createFlags & NVOC_OBJ_CREATE_FLAGS_IN_PLACE_CONSTRUCT) + portMemSet(pThis, 0, sizeof(RgLineCallback)); + else + portMemFree(pThis); + + // coverity[leaked_storage:FALSE] return status; } diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/generated/g_rg_line_callback_nvoc.h nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_rg_line_callback_nvoc.h --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/generated/g_rg_line_callback_nvoc.h 2023-10-25 20:27:18.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_rg_line_callback_nvoc.h 2024-03-05 22:18:44.000000000 +0000 @@ -68,26 +68,28 @@ struct GpuResource *__nvoc_pbase_GpuResource; struct RgLineCallback *__nvoc_pbase_RgLineCallback; NvBool (*__rglcbShareCallback__)(struct RgLineCallback *, struct RsClient *, struct RsResourceRef *, RS_SHARE_POLICY *); - NV_STATUS (*__rglcbControl__)(struct RgLineCallback *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); - NV_STATUS (*__rglcbUnmap__)(struct RgLineCallback *, struct CALL_CONTEXT *, struct RsCpuMapping *); - NV_STATUS (*__rglcbGetMemInterMapParams__)(struct RgLineCallback *, RMRES_MEM_INTER_MAP_PARAMS *); - NV_STATUS (*__rglcbGetMemoryMappingDescriptor__)(struct RgLineCallback *, struct MEMORY_DESCRIPTOR **); - NV_STATUS (*__rglcbGetMapAddrSpace__)(struct RgLineCallback *, struct CALL_CONTEXT *, NvU32, NV_ADDRESS_SPACE *); - NvHandle (*__rglcbGetInternalObjectHandle__)(struct RgLineCallback *); - NV_STATUS (*__rglcbControlFilter__)(struct RgLineCallback *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); - void (*__rglcbAddAdditionalDependants__)(struct RsClient *, struct RgLineCallback *, RsResourceRef *); - NvU32 (*__rglcbGetRefCount__)(struct RgLineCallback *); NV_STATUS (*__rglcbCheckMemInterUnmap__)(struct RgLineCallback *, NvBool); NV_STATUS (*__rglcbMapTo__)(struct RgLineCallback *, RS_RES_MAP_TO_PARAMS *); + NV_STATUS (*__rglcbGetMapAddrSpace__)(struct RgLineCallback *, struct CALL_CONTEXT *, NvU32, NV_ADDRESS_SPACE *); + NvU32 (*__rglcbGetRefCount__)(struct RgLineCallback *); + void (*__rglcbAddAdditionalDependants__)(struct RsClient *, struct RgLineCallback *, RsResourceRef *); NV_STATUS (*__rglcbControl_Prologue__)(struct RgLineCallback *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); NV_STATUS (*__rglcbGetRegBaseOffsetAndSize__)(struct RgLineCallback *, struct OBJGPU *, NvU32 *, NvU32 *); - NvBool (*__rglcbCanCopy__)(struct RgLineCallback *); NV_STATUS (*__rglcbInternalControlForward__)(struct RgLineCallback *, NvU32, void *, NvU32); - void (*__rglcbPreDestruct__)(struct RgLineCallback *); NV_STATUS (*__rglcbUnmapFrom__)(struct RgLineCallback *, RS_RES_UNMAP_FROM_PARAMS *); - NV_STATUS (*__rglcbIsDuplicate__)(struct RgLineCallback *, NvHandle, NvBool *); void (*__rglcbControl_Epilogue__)(struct RgLineCallback *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); NV_STATUS (*__rglcbControlLookup__)(struct RgLineCallback *, struct RS_RES_CONTROL_PARAMS_INTERNAL *, const struct NVOC_EXPORTED_METHOD_DEF **); + NvHandle (*__rglcbGetInternalObjectHandle__)(struct RgLineCallback *); + NV_STATUS (*__rglcbControl__)(struct RgLineCallback *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); + NV_STATUS (*__rglcbUnmap__)(struct RgLineCallback *, struct CALL_CONTEXT *, struct RsCpuMapping *); + NV_STATUS (*__rglcbGetMemInterMapParams__)(struct RgLineCallback *, RMRES_MEM_INTER_MAP_PARAMS *); + NV_STATUS (*__rglcbGetMemoryMappingDescriptor__)(struct RgLineCallback *, struct MEMORY_DESCRIPTOR **); + NV_STATUS (*__rglcbControlFilter__)(struct RgLineCallback *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); + NV_STATUS (*__rglcbControlSerialization_Prologue__)(struct RgLineCallback *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); + NvBool (*__rglcbCanCopy__)(struct RgLineCallback *); + void (*__rglcbPreDestruct__)(struct RgLineCallback *); + NV_STATUS (*__rglcbIsDuplicate__)(struct RgLineCallback *, NvHandle, NvBool *); + void (*__rglcbControlSerialization_Epilogue__)(struct RgLineCallback *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); NV_STATUS (*__rglcbMap__)(struct RgLineCallback *, struct CALL_CONTEXT *, struct RS_CPU_MAP_PARAMS *, struct RsCpuMapping *); NvBool (*__rglcbAccessCallback__)(struct RgLineCallback *, struct RsClient *, void *, RsAccessRight); NvU32 subDeviceInstance; @@ -128,110 +130,120 @@ __nvoc_objCreate_RgLineCallback((ppNewObj), staticCast((pParent), Dynamic), (createFlags), arg_pCallContext, arg_pParams) #define rglcbShareCallback(pGpuResource, pInvokingClient, pParentRef, pSharePolicy) rglcbShareCallback_DISPATCH(pGpuResource, pInvokingClient, pParentRef, pSharePolicy) -#define rglcbControl(pGpuResource, pCallContext, pParams) rglcbControl_DISPATCH(pGpuResource, pCallContext, pParams) -#define rglcbUnmap(pGpuResource, pCallContext, pCpuMapping) rglcbUnmap_DISPATCH(pGpuResource, pCallContext, pCpuMapping) -#define rglcbGetMemInterMapParams(pRmResource, pParams) rglcbGetMemInterMapParams_DISPATCH(pRmResource, pParams) -#define rglcbGetMemoryMappingDescriptor(pRmResource, ppMemDesc) rglcbGetMemoryMappingDescriptor_DISPATCH(pRmResource, ppMemDesc) -#define rglcbGetMapAddrSpace(pGpuResource, pCallContext, mapFlags, pAddrSpace) rglcbGetMapAddrSpace_DISPATCH(pGpuResource, pCallContext, mapFlags, pAddrSpace) -#define rglcbGetInternalObjectHandle(pGpuResource) rglcbGetInternalObjectHandle_DISPATCH(pGpuResource) -#define rglcbControlFilter(pResource, pCallContext, pParams) rglcbControlFilter_DISPATCH(pResource, pCallContext, pParams) -#define rglcbAddAdditionalDependants(pClient, pResource, pReference) rglcbAddAdditionalDependants_DISPATCH(pClient, pResource, pReference) -#define rglcbGetRefCount(pResource) rglcbGetRefCount_DISPATCH(pResource) #define rglcbCheckMemInterUnmap(pRmResource, bSubdeviceHandleProvided) rglcbCheckMemInterUnmap_DISPATCH(pRmResource, bSubdeviceHandleProvided) #define rglcbMapTo(pResource, pParams) rglcbMapTo_DISPATCH(pResource, pParams) +#define rglcbGetMapAddrSpace(pGpuResource, pCallContext, mapFlags, pAddrSpace) rglcbGetMapAddrSpace_DISPATCH(pGpuResource, pCallContext, mapFlags, pAddrSpace) +#define rglcbGetRefCount(pResource) rglcbGetRefCount_DISPATCH(pResource) +#define rglcbAddAdditionalDependants(pClient, pResource, pReference) rglcbAddAdditionalDependants_DISPATCH(pClient, pResource, pReference) #define rglcbControl_Prologue(pResource, pCallContext, pParams) rglcbControl_Prologue_DISPATCH(pResource, pCallContext, pParams) #define rglcbGetRegBaseOffsetAndSize(pGpuResource, pGpu, pOffset, pSize) rglcbGetRegBaseOffsetAndSize_DISPATCH(pGpuResource, pGpu, pOffset, pSize) -#define rglcbCanCopy(pResource) rglcbCanCopy_DISPATCH(pResource) #define rglcbInternalControlForward(pGpuResource, command, pParams, size) rglcbInternalControlForward_DISPATCH(pGpuResource, command, pParams, size) -#define rglcbPreDestruct(pResource) rglcbPreDestruct_DISPATCH(pResource) #define rglcbUnmapFrom(pResource, pParams) rglcbUnmapFrom_DISPATCH(pResource, pParams) -#define rglcbIsDuplicate(pResource, hMemory, pDuplicate) rglcbIsDuplicate_DISPATCH(pResource, hMemory, pDuplicate) #define rglcbControl_Epilogue(pResource, pCallContext, pParams) rglcbControl_Epilogue_DISPATCH(pResource, pCallContext, pParams) #define rglcbControlLookup(pResource, pParams, ppEntry) rglcbControlLookup_DISPATCH(pResource, pParams, ppEntry) +#define rglcbGetInternalObjectHandle(pGpuResource) rglcbGetInternalObjectHandle_DISPATCH(pGpuResource) +#define rglcbControl(pGpuResource, pCallContext, pParams) rglcbControl_DISPATCH(pGpuResource, pCallContext, pParams) +#define rglcbUnmap(pGpuResource, pCallContext, pCpuMapping) rglcbUnmap_DISPATCH(pGpuResource, pCallContext, pCpuMapping) +#define rglcbGetMemInterMapParams(pRmResource, pParams) rglcbGetMemInterMapParams_DISPATCH(pRmResource, pParams) +#define rglcbGetMemoryMappingDescriptor(pRmResource, ppMemDesc) rglcbGetMemoryMappingDescriptor_DISPATCH(pRmResource, ppMemDesc) +#define rglcbControlFilter(pResource, pCallContext, pParams) rglcbControlFilter_DISPATCH(pResource, pCallContext, pParams) +#define rglcbControlSerialization_Prologue(pResource, pCallContext, pParams) rglcbControlSerialization_Prologue_DISPATCH(pResource, pCallContext, pParams) +#define rglcbCanCopy(pResource) rglcbCanCopy_DISPATCH(pResource) +#define rglcbPreDestruct(pResource) rglcbPreDestruct_DISPATCH(pResource) +#define rglcbIsDuplicate(pResource, hMemory, pDuplicate) rglcbIsDuplicate_DISPATCH(pResource, hMemory, pDuplicate) +#define rglcbControlSerialization_Epilogue(pResource, pCallContext, pParams) rglcbControlSerialization_Epilogue_DISPATCH(pResource, pCallContext, pParams) #define rglcbMap(pGpuResource, pCallContext, pParams, pCpuMapping) rglcbMap_DISPATCH(pGpuResource, pCallContext, pParams, pCpuMapping) #define rglcbAccessCallback(pResource, pInvokingClient, pAllocParams, accessRight) rglcbAccessCallback_DISPATCH(pResource, pInvokingClient, pAllocParams, accessRight) static inline NvBool rglcbShareCallback_DISPATCH(struct RgLineCallback *pGpuResource, struct RsClient *pInvokingClient, struct RsResourceRef *pParentRef, RS_SHARE_POLICY *pSharePolicy) { return pGpuResource->__rglcbShareCallback__(pGpuResource, pInvokingClient, pParentRef, pSharePolicy); } -static inline NV_STATUS rglcbControl_DISPATCH(struct RgLineCallback *pGpuResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { - return pGpuResource->__rglcbControl__(pGpuResource, pCallContext, pParams); +static inline NV_STATUS rglcbCheckMemInterUnmap_DISPATCH(struct RgLineCallback *pRmResource, NvBool bSubdeviceHandleProvided) { + return pRmResource->__rglcbCheckMemInterUnmap__(pRmResource, bSubdeviceHandleProvided); } -static inline NV_STATUS rglcbUnmap_DISPATCH(struct RgLineCallback *pGpuResource, struct CALL_CONTEXT *pCallContext, struct RsCpuMapping *pCpuMapping) { - return pGpuResource->__rglcbUnmap__(pGpuResource, pCallContext, pCpuMapping); +static inline NV_STATUS rglcbMapTo_DISPATCH(struct RgLineCallback *pResource, RS_RES_MAP_TO_PARAMS *pParams) { + return pResource->__rglcbMapTo__(pResource, pParams); } -static inline NV_STATUS rglcbGetMemInterMapParams_DISPATCH(struct RgLineCallback *pRmResource, RMRES_MEM_INTER_MAP_PARAMS *pParams) { - return pRmResource->__rglcbGetMemInterMapParams__(pRmResource, pParams); +static inline NV_STATUS rglcbGetMapAddrSpace_DISPATCH(struct RgLineCallback *pGpuResource, struct CALL_CONTEXT *pCallContext, NvU32 mapFlags, NV_ADDRESS_SPACE *pAddrSpace) { + return pGpuResource->__rglcbGetMapAddrSpace__(pGpuResource, pCallContext, mapFlags, pAddrSpace); } -static inline NV_STATUS rglcbGetMemoryMappingDescriptor_DISPATCH(struct RgLineCallback *pRmResource, struct MEMORY_DESCRIPTOR **ppMemDesc) { - return pRmResource->__rglcbGetMemoryMappingDescriptor__(pRmResource, ppMemDesc); +static inline NvU32 rglcbGetRefCount_DISPATCH(struct RgLineCallback *pResource) { + return pResource->__rglcbGetRefCount__(pResource); } -static inline NV_STATUS rglcbGetMapAddrSpace_DISPATCH(struct RgLineCallback *pGpuResource, struct CALL_CONTEXT *pCallContext, NvU32 mapFlags, NV_ADDRESS_SPACE *pAddrSpace) { - return pGpuResource->__rglcbGetMapAddrSpace__(pGpuResource, pCallContext, mapFlags, pAddrSpace); +static inline void rglcbAddAdditionalDependants_DISPATCH(struct RsClient *pClient, struct RgLineCallback *pResource, RsResourceRef *pReference) { + pResource->__rglcbAddAdditionalDependants__(pClient, pResource, pReference); } -static inline NvHandle rglcbGetInternalObjectHandle_DISPATCH(struct RgLineCallback *pGpuResource) { - return pGpuResource->__rglcbGetInternalObjectHandle__(pGpuResource); +static inline NV_STATUS rglcbControl_Prologue_DISPATCH(struct RgLineCallback *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return pResource->__rglcbControl_Prologue__(pResource, pCallContext, pParams); } -static inline NV_STATUS rglcbControlFilter_DISPATCH(struct RgLineCallback *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { - return pResource->__rglcbControlFilter__(pResource, pCallContext, pParams); +static inline NV_STATUS rglcbGetRegBaseOffsetAndSize_DISPATCH(struct RgLineCallback *pGpuResource, struct OBJGPU *pGpu, NvU32 *pOffset, NvU32 *pSize) { + return pGpuResource->__rglcbGetRegBaseOffsetAndSize__(pGpuResource, pGpu, pOffset, pSize); } -static inline void rglcbAddAdditionalDependants_DISPATCH(struct RsClient *pClient, struct RgLineCallback *pResource, RsResourceRef *pReference) { - pResource->__rglcbAddAdditionalDependants__(pClient, pResource, pReference); +static inline NV_STATUS rglcbInternalControlForward_DISPATCH(struct RgLineCallback *pGpuResource, NvU32 command, void *pParams, NvU32 size) { + return pGpuResource->__rglcbInternalControlForward__(pGpuResource, command, pParams, size); } -static inline NvU32 rglcbGetRefCount_DISPATCH(struct RgLineCallback *pResource) { - return pResource->__rglcbGetRefCount__(pResource); +static inline NV_STATUS rglcbUnmapFrom_DISPATCH(struct RgLineCallback *pResource, RS_RES_UNMAP_FROM_PARAMS *pParams) { + return pResource->__rglcbUnmapFrom__(pResource, pParams); } -static inline NV_STATUS rglcbCheckMemInterUnmap_DISPATCH(struct RgLineCallback *pRmResource, NvBool bSubdeviceHandleProvided) { - return pRmResource->__rglcbCheckMemInterUnmap__(pRmResource, bSubdeviceHandleProvided); +static inline void rglcbControl_Epilogue_DISPATCH(struct RgLineCallback *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + pResource->__rglcbControl_Epilogue__(pResource, pCallContext, pParams); } -static inline NV_STATUS rglcbMapTo_DISPATCH(struct RgLineCallback *pResource, RS_RES_MAP_TO_PARAMS *pParams) { - return pResource->__rglcbMapTo__(pResource, pParams); +static inline NV_STATUS rglcbControlLookup_DISPATCH(struct RgLineCallback *pResource, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams, const struct NVOC_EXPORTED_METHOD_DEF **ppEntry) { + return pResource->__rglcbControlLookup__(pResource, pParams, ppEntry); } -static inline NV_STATUS rglcbControl_Prologue_DISPATCH(struct RgLineCallback *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { - return pResource->__rglcbControl_Prologue__(pResource, pCallContext, pParams); +static inline NvHandle rglcbGetInternalObjectHandle_DISPATCH(struct RgLineCallback *pGpuResource) { + return pGpuResource->__rglcbGetInternalObjectHandle__(pGpuResource); } -static inline NV_STATUS rglcbGetRegBaseOffsetAndSize_DISPATCH(struct RgLineCallback *pGpuResource, struct OBJGPU *pGpu, NvU32 *pOffset, NvU32 *pSize) { - return pGpuResource->__rglcbGetRegBaseOffsetAndSize__(pGpuResource, pGpu, pOffset, pSize); +static inline NV_STATUS rglcbControl_DISPATCH(struct RgLineCallback *pGpuResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return pGpuResource->__rglcbControl__(pGpuResource, pCallContext, pParams); } -static inline NvBool rglcbCanCopy_DISPATCH(struct RgLineCallback *pResource) { - return pResource->__rglcbCanCopy__(pResource); +static inline NV_STATUS rglcbUnmap_DISPATCH(struct RgLineCallback *pGpuResource, struct CALL_CONTEXT *pCallContext, struct RsCpuMapping *pCpuMapping) { + return pGpuResource->__rglcbUnmap__(pGpuResource, pCallContext, pCpuMapping); } -static inline NV_STATUS rglcbInternalControlForward_DISPATCH(struct RgLineCallback *pGpuResource, NvU32 command, void *pParams, NvU32 size) { - return pGpuResource->__rglcbInternalControlForward__(pGpuResource, command, pParams, size); +static inline NV_STATUS rglcbGetMemInterMapParams_DISPATCH(struct RgLineCallback *pRmResource, RMRES_MEM_INTER_MAP_PARAMS *pParams) { + return pRmResource->__rglcbGetMemInterMapParams__(pRmResource, pParams); } -static inline void rglcbPreDestruct_DISPATCH(struct RgLineCallback *pResource) { - pResource->__rglcbPreDestruct__(pResource); +static inline NV_STATUS rglcbGetMemoryMappingDescriptor_DISPATCH(struct RgLineCallback *pRmResource, struct MEMORY_DESCRIPTOR **ppMemDesc) { + return pRmResource->__rglcbGetMemoryMappingDescriptor__(pRmResource, ppMemDesc); } -static inline NV_STATUS rglcbUnmapFrom_DISPATCH(struct RgLineCallback *pResource, RS_RES_UNMAP_FROM_PARAMS *pParams) { - return pResource->__rglcbUnmapFrom__(pResource, pParams); +static inline NV_STATUS rglcbControlFilter_DISPATCH(struct RgLineCallback *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return pResource->__rglcbControlFilter__(pResource, pCallContext, pParams); } -static inline NV_STATUS rglcbIsDuplicate_DISPATCH(struct RgLineCallback *pResource, NvHandle hMemory, NvBool *pDuplicate) { - return pResource->__rglcbIsDuplicate__(pResource, hMemory, pDuplicate); +static inline NV_STATUS rglcbControlSerialization_Prologue_DISPATCH(struct RgLineCallback *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return pResource->__rglcbControlSerialization_Prologue__(pResource, pCallContext, pParams); } -static inline void rglcbControl_Epilogue_DISPATCH(struct RgLineCallback *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { - pResource->__rglcbControl_Epilogue__(pResource, pCallContext, pParams); +static inline NvBool rglcbCanCopy_DISPATCH(struct RgLineCallback *pResource) { + return pResource->__rglcbCanCopy__(pResource); } -static inline NV_STATUS rglcbControlLookup_DISPATCH(struct RgLineCallback *pResource, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams, const struct NVOC_EXPORTED_METHOD_DEF **ppEntry) { - return pResource->__rglcbControlLookup__(pResource, pParams, ppEntry); +static inline void rglcbPreDestruct_DISPATCH(struct RgLineCallback *pResource) { + pResource->__rglcbPreDestruct__(pResource); +} + +static inline NV_STATUS rglcbIsDuplicate_DISPATCH(struct RgLineCallback *pResource, NvHandle hMemory, NvBool *pDuplicate) { + return pResource->__rglcbIsDuplicate__(pResource, hMemory, pDuplicate); +} + +static inline void rglcbControlSerialization_Epilogue_DISPATCH(struct RgLineCallback *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + pResource->__rglcbControlSerialization_Epilogue__(pResource, pCallContext, pParams); } static inline NV_STATUS rglcbMap_DISPATCH(struct RgLineCallback *pGpuResource, struct CALL_CONTEXT *pCallContext, struct RS_CPU_MAP_PARAMS *pParams, struct RsCpuMapping *pCpuMapping) { diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/generated/g_rpc-structures.h nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_rpc-structures.h --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/generated/g_rpc-structures.h 2023-10-25 20:23:07.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_rpc-structures.h 2024-03-05 22:15:57.000000000 +0000 @@ -104,7 +104,7 @@ typedef struct rpc_unloading_guest_driver_v1F_07 { - NvBool bSuspend; + NvBool bInPMTransition; NvBool bGc6Entering; NvU32 newLevel; } rpc_unloading_guest_driver_v1F_07; @@ -233,6 +233,8 @@ NvU32 hClass; NvU32 status; NvU32 paramsSize; + NvU32 flags; + NvU8 reserved[4]; NvU8 params[]; } rpc_gsp_rm_alloc_v03_00; @@ -245,9 +247,7 @@ NvU32 cmd; NvU32 status; NvU32 paramsSize; - NvBool serialized; - NvBool copyOutOnError; - NvU8 reserved[2]; + NvU32 flags; NvU8 params[]; } rpc_gsp_rm_control_v03_00; @@ -282,6 +282,7 @@ NvHandle hEvent; NvU32 notifyIndex; NvU32 data; + NvU16 info16; NvU32 status; NvU32 eventDataSize; NvBool bNotifyList; @@ -297,6 +298,8 @@ NvU32 exceptType; NvU32 scope; NvU16 partitionAttributionId; + NvU32 rcJournalBufferSize; + NvU8 rcJournalBuffer[]; } rpc_rc_triggered_v17_02; typedef rpc_rc_triggered_v17_02 rpc_rc_triggered_v; @@ -480,6 +483,13 @@ typedef rpc_nvlink_is_gpu_degraded_v17_00 rpc_nvlink_is_gpu_degraded_v; +typedef struct rpc_gsp_send_user_shared_data_v17_00 +{ + NvU32 data; +} rpc_gsp_send_user_shared_data_v17_00; + +typedef rpc_gsp_send_user_shared_data_v17_00 rpc_gsp_send_user_shared_data_v; + typedef struct rpc_set_sysmem_dirty_page_tracking_buffer_v20_00 { NvU32 sysmemPfnBitmapRing; @@ -506,6 +516,16 @@ typedef rpc_pfm_req_hndlr_state_sync_callback_v21_04 rpc_pfm_req_hndlr_state_sync_callback_v; +typedef struct rpc_vgpu_gsp_mig_ci_config_v21_03 +{ + NvU32 execPartCount; + NvU32 execPartId[NVC637_CTRL_MAX_EXEC_PARTITIONS]; + NvU32 gfid; + NvBool bDelete; +} rpc_vgpu_gsp_mig_ci_config_v21_03; + +typedef rpc_vgpu_gsp_mig_ci_config_v21_03 rpc_vgpu_gsp_mig_ci_config_v; + typedef struct rpc_gsp_lockdown_notice_v17_00 { NvBool bLockdownEngaging; @@ -614,7 +634,7 @@ #if (defined(DEBUG) || defined(DEVELOP)) .name = "rpc_set_guest_system_info", #endif - .header_length = NV_SIZEOF32(rpc_set_guest_system_info_v03_00), + .header_length = sizeof(rpc_set_guest_system_info_v03_00), .fdesc = vmiopd_fdesc_t_rpc_set_guest_system_info_v03_00 }; #endif @@ -700,7 +720,7 @@ #if (defined(DEBUG) || defined(DEVELOP)) .name = "rpc_alloc_memory", #endif - .header_length = NV_SIZEOF32(rpc_alloc_memory_v13_01), + .header_length = sizeof(rpc_alloc_memory_v13_01), .fdesc = vmiopd_fdesc_t_rpc_alloc_memory_v13_01 }; #endif @@ -723,7 +743,7 @@ #if (defined(DEBUG) || defined(DEVELOP)) .name = "rpc_free", #endif - .header_length = NV_SIZEOF32(rpc_free_v03_00), + .header_length = sizeof(rpc_free_v03_00), .fdesc = vmiopd_fdesc_t_rpc_free_v03_00 }; #endif @@ -746,7 +766,7 @@ #if (defined(DEBUG) || defined(DEVELOP)) .name = "rpc_map_memory_dma", #endif - .header_length = NV_SIZEOF32(rpc_map_memory_dma_v03_00), + .header_length = sizeof(rpc_map_memory_dma_v03_00), .fdesc = vmiopd_fdesc_t_rpc_map_memory_dma_v03_00 }; #endif @@ -769,7 +789,7 @@ #if (defined(DEBUG) || defined(DEVELOP)) .name = "rpc_unmap_memory_dma", #endif - .header_length = NV_SIZEOF32(rpc_unmap_memory_dma_v03_00), + .header_length = sizeof(rpc_unmap_memory_dma_v03_00), .fdesc = vmiopd_fdesc_t_rpc_unmap_memory_dma_v03_00 }; #endif @@ -792,7 +812,7 @@ #if (defined(DEBUG) || defined(DEVELOP)) .name = "rpc_dup_object", #endif - .header_length = NV_SIZEOF32(rpc_dup_object_v03_00), + .header_length = sizeof(rpc_dup_object_v03_00), .fdesc = vmiopd_fdesc_t_rpc_dup_object_v03_00 }; #endif @@ -838,7 +858,7 @@ #if (defined(DEBUG) || defined(DEVELOP)) .name = "rpc_idle_channels", #endif - .header_length = NV_SIZEOF32(rpc_idle_channels_v03_00), + .header_length = sizeof(rpc_idle_channels_v03_00), .fdesc = vmiopd_fdesc_t_rpc_idle_channels_v03_00 }; #endif @@ -862,9 +882,9 @@ static vmiopd_fdesc_t vmiopd_fdesc_t_rpc_unloading_guest_driver_v1F_07[] = { { .vtype = vtype_NvBool, - .offset = NV_OFFSETOF(rpc_unloading_guest_driver_v1F_07, bSuspend), + .offset = NV_OFFSETOF(rpc_unloading_guest_driver_v1F_07, bInPMTransition), #if (defined(DEBUG) || defined(DEVELOP)) - .name = "bSuspend" + .name = "bInPMTransition" #endif }, { @@ -890,7 +910,7 @@ #if (defined(DEBUG) || defined(DEVELOP)) .name = "rpc_unloading_guest_driver", #endif - .header_length = NV_SIZEOF32(rpc_unloading_guest_driver_v1F_07), + .header_length = sizeof(rpc_unloading_guest_driver_v1F_07), .fdesc = vmiopd_fdesc_t_rpc_unloading_guest_driver_v1F_07 }; #endif @@ -927,7 +947,7 @@ #if (defined(DEBUG) || defined(DEVELOP)) .name = "rpc_gpu_exec_reg_ops", #endif - .header_length = NV_SIZEOF32(rpc_gpu_exec_reg_ops_v12_01), + .header_length = sizeof(rpc_gpu_exec_reg_ops_v12_01), .fdesc = vmiopd_fdesc_t_rpc_gpu_exec_reg_ops_v12_01 }; #endif @@ -971,7 +991,7 @@ #if (defined(DEBUG) || defined(DEVELOP)) .name = "rpc_set_page_directory", #endif - .header_length = NV_SIZEOF32(rpc_set_page_directory_v1E_05), + .header_length = sizeof(rpc_set_page_directory_v1E_05), .fdesc = vmiopd_fdesc_t_rpc_set_page_directory_v1E_05 }; #endif @@ -1008,7 +1028,7 @@ #if (defined(DEBUG) || defined(DEVELOP)) .name = "rpc_set_page_directory", #endif - .header_length = NV_SIZEOF32(rpc_set_page_directory_v03_00), + .header_length = sizeof(rpc_set_page_directory_v03_00), .fdesc = vmiopd_fdesc_t_rpc_set_page_directory_v03_00 }; #endif @@ -1045,7 +1065,7 @@ #if (defined(DEBUG) || defined(DEVELOP)) .name = "rpc_unset_page_directory", #endif - .header_length = NV_SIZEOF32(rpc_unset_page_directory_v1E_05), + .header_length = sizeof(rpc_unset_page_directory_v1E_05), .fdesc = vmiopd_fdesc_t_rpc_unset_page_directory_v1E_05 }; #endif @@ -1082,7 +1102,7 @@ #if (defined(DEBUG) || defined(DEVELOP)) .name = "rpc_unset_page_directory", #endif - .header_length = NV_SIZEOF32(rpc_unset_page_directory_v03_00), + .header_length = sizeof(rpc_unset_page_directory_v03_00), .fdesc = vmiopd_fdesc_t_rpc_unset_page_directory_v03_00 }; #endif @@ -1105,7 +1125,7 @@ #if (defined(DEBUG) || defined(DEVELOP)) .name = "rpc_get_gsp_static_info", #endif - .header_length = NV_SIZEOF32(rpc_get_gsp_static_info_v14_00), + .header_length = sizeof(rpc_get_gsp_static_info_v14_00), .fdesc = vmiopd_fdesc_t_rpc_get_gsp_static_info_v14_00 }; #endif @@ -1128,7 +1148,7 @@ #if (defined(DEBUG) || defined(DEVELOP)) .name = "rpc_update_bar_pde", #endif - .header_length = NV_SIZEOF32(rpc_update_bar_pde_v15_00), + .header_length = sizeof(rpc_update_bar_pde_v15_00), .fdesc = vmiopd_fdesc_t_rpc_update_bar_pde_v15_00 }; #endif @@ -1165,7 +1185,7 @@ #if (defined(DEBUG) || defined(DEVELOP)) .name = "rpc_vgpu_pf_reg_read32", #endif - .header_length = NV_SIZEOF32(rpc_vgpu_pf_reg_read32_v15_00), + .header_length = sizeof(rpc_vgpu_pf_reg_read32_v15_00), .fdesc = vmiopd_fdesc_t_rpc_vgpu_pf_reg_read32_v15_00 }; #endif @@ -1188,7 +1208,7 @@ #if (defined(DEBUG) || defined(DEVELOP)) .name = "rpc_ctrl_subdevice_get_p2p_caps", #endif - .header_length = NV_SIZEOF32(rpc_ctrl_subdevice_get_p2p_caps_v21_02), + .header_length = sizeof(rpc_ctrl_subdevice_get_p2p_caps_v21_02), .fdesc = vmiopd_fdesc_t_rpc_ctrl_subdevice_get_p2p_caps_v21_02 }; #endif @@ -1225,7 +1245,7 @@ #if (defined(DEBUG) || defined(DEVELOP)) .name = "rpc_ctrl_bus_set_p2p_mapping", #endif - .header_length = NV_SIZEOF32(rpc_ctrl_bus_set_p2p_mapping_v21_03), + .header_length = sizeof(rpc_ctrl_bus_set_p2p_mapping_v21_03), .fdesc = vmiopd_fdesc_t_rpc_ctrl_bus_set_p2p_mapping_v21_03 }; #endif @@ -1262,7 +1282,7 @@ #if (defined(DEBUG) || defined(DEVELOP)) .name = "rpc_ctrl_bus_unset_p2p_mapping", #endif - .header_length = NV_SIZEOF32(rpc_ctrl_bus_unset_p2p_mapping_v21_03), + .header_length = sizeof(rpc_ctrl_bus_unset_p2p_mapping_v21_03), .fdesc = vmiopd_fdesc_t_rpc_ctrl_bus_unset_p2p_mapping_v21_03 }; #endif @@ -1285,7 +1305,7 @@ #if (defined(DEBUG) || defined(DEVELOP)) .name = "rpc_rmfs_init", #endif - .header_length = NV_SIZEOF32(rpc_rmfs_init_v15_00), + .header_length = sizeof(rpc_rmfs_init_v15_00), .fdesc = vmiopd_fdesc_t_rpc_rmfs_init_v15_00 }; #endif @@ -1359,11 +1379,26 @@ #if (defined(DEBUG) || defined(DEVELOP)) .name = "rpc_rmfs_test", #endif - .header_length = NV_SIZEOF32(rpc_rmfs_test_v15_00), + .header_length = sizeof(rpc_rmfs_test_v15_00), .fdesc = vmiopd_fdesc_t_rpc_rmfs_test_v15_00 }; #endif +#ifndef SKIP_PRINT_rpc_ecc_notifier_write_ack_v23_05 +static vmiopd_fdesc_t vmiopd_fdesc_t_rpc_ecc_notifier_write_ack_v23_05[] = { + { + .vtype = vt_end + } +}; + +static vmiopd_mdesc_t vmiopd_mdesc_t_rpc_ecc_notifier_write_ack_v23_05 = { + #if (defined(DEBUG) || defined(DEVELOP)) + .name = "rpc_ecc_notifier_write_ack", + #endif + .fdesc = vmiopd_fdesc_t_rpc_ecc_notifier_write_ack_v23_05 +}; +#endif + #ifndef SKIP_PRINT_rpc_gsp_set_system_info_v17_00 static vmiopd_fdesc_t vmiopd_fdesc_t_rpc_gsp_set_system_info_v17_00[] = { { @@ -1382,7 +1417,7 @@ #if (defined(DEBUG) || defined(DEVELOP)) .name = "rpc_gsp_set_system_info", #endif - .header_length = NV_SIZEOF32(rpc_gsp_set_system_info_v17_00), + .header_length = sizeof(rpc_gsp_set_system_info_v17_00), .fdesc = vmiopd_fdesc_t_rpc_gsp_set_system_info_v17_00 }; #endif @@ -1447,6 +1482,21 @@ #endif }, { + .vtype = vtype_NvU32, + .offset = NV_OFFSETOF(rpc_gsp_rm_alloc_v03_00, flags), + #if (defined(DEBUG) || defined(DEVELOP)) + .name = "flags" + #endif + }, + { + .vtype = vtype_NvU8_array, + .offset = NV_OFFSETOF(rpc_gsp_rm_alloc_v03_00, reserved), + .array_length = 4, + #if (defined(DEBUG) || defined(DEVELOP)) + .name = "reserved" + #endif + }, + { .vtype = vtype_NvU8_array, .offset = NV_OFFSETOF(rpc_gsp_rm_alloc_v03_00, params), .array_length = 0, @@ -1463,7 +1513,7 @@ #if (defined(DEBUG) || defined(DEVELOP)) .name = "rpc_gsp_rm_alloc", #endif - .header_length = NV_SIZEOF32(rpc_gsp_rm_alloc_v03_00), + .header_length = sizeof(rpc_gsp_rm_alloc_v03_00), .fdesc = vmiopd_fdesc_t_rpc_gsp_rm_alloc_v03_00 }; #endif @@ -1506,25 +1556,10 @@ #endif }, { - .vtype = vtype_NvBool, - .offset = NV_OFFSETOF(rpc_gsp_rm_control_v03_00, serialized), - #if (defined(DEBUG) || defined(DEVELOP)) - .name = "serialized" - #endif - }, - { - .vtype = vtype_NvBool, - .offset = NV_OFFSETOF(rpc_gsp_rm_control_v03_00, copyOutOnError), - #if (defined(DEBUG) || defined(DEVELOP)) - .name = "copyOutOnError" - #endif - }, - { - .vtype = vtype_NvU8_array, - .offset = NV_OFFSETOF(rpc_gsp_rm_control_v03_00, reserved), - .array_length = 2, + .vtype = vtype_NvU32, + .offset = NV_OFFSETOF(rpc_gsp_rm_control_v03_00, flags), #if (defined(DEBUG) || defined(DEVELOP)) - .name = "reserved" + .name = "flags" #endif }, { @@ -1544,7 +1579,7 @@ #if (defined(DEBUG) || defined(DEVELOP)) .name = "rpc_gsp_rm_control", #endif - .header_length = NV_SIZEOF32(rpc_gsp_rm_control_v03_00), + .header_length = sizeof(rpc_gsp_rm_control_v03_00), .fdesc = vmiopd_fdesc_t_rpc_gsp_rm_control_v03_00 }; #endif @@ -1610,7 +1645,7 @@ #if (defined(DEBUG) || defined(DEVELOP)) .name = "rpc_dump_protobuf_component", #endif - .header_length = NV_SIZEOF32(rpc_dump_protobuf_component_v18_12), + .header_length = sizeof(rpc_dump_protobuf_component_v18_12), .fdesc = vmiopd_fdesc_t_rpc_dump_protobuf_component_v18_12 }; #endif @@ -1656,7 +1691,7 @@ #if (defined(DEBUG) || defined(DEVELOP)) .name = "rpc_run_cpu_sequencer", #endif - .header_length = NV_SIZEOF32(rpc_run_cpu_sequencer_v17_00), + .header_length = sizeof(rpc_run_cpu_sequencer_v17_00), .fdesc = vmiopd_fdesc_t_rpc_run_cpu_sequencer_v17_00 }; #endif @@ -1692,6 +1727,13 @@ #endif }, { + .vtype = vtype_NvU16, + .offset = NV_OFFSETOF(rpc_post_event_v17_00, info16), + #if (defined(DEBUG) || defined(DEVELOP)) + .name = "info16" + #endif + }, + { .vtype = vtype_NvU32, .offset = NV_OFFSETOF(rpc_post_event_v17_00, status), #if (defined(DEBUG) || defined(DEVELOP)) @@ -1729,7 +1771,7 @@ #if (defined(DEBUG) || defined(DEVELOP)) .name = "rpc_post_event", #endif - .header_length = NV_SIZEOF32(rpc_post_event_v17_00), + .header_length = sizeof(rpc_post_event_v17_00), .fdesc = vmiopd_fdesc_t_rpc_post_event_v17_00 }; #endif @@ -1772,6 +1814,21 @@ #endif }, { + .vtype = vtype_NvU32, + .offset = NV_OFFSETOF(rpc_rc_triggered_v17_02, rcJournalBufferSize), + #if (defined(DEBUG) || defined(DEVELOP)) + .name = "rcJournalBufferSize" + #endif + }, + { + .vtype = vtype_NvU8_array, + .offset = NV_OFFSETOF(rpc_rc_triggered_v17_02, rcJournalBuffer), + .array_length = 0, + #if (defined(DEBUG) || defined(DEVELOP)) + .name = "rcJournalBuffer" + #endif + }, + { .vtype = vt_end } }; @@ -1780,7 +1837,7 @@ #if (defined(DEBUG) || defined(DEVELOP)) .name = "rpc_rc_triggered", #endif - .header_length = NV_SIZEOF32(rpc_rc_triggered_v17_02), + .header_length = sizeof(rpc_rc_triggered_v17_02), .fdesc = vmiopd_fdesc_t_rpc_rc_triggered_v17_02 }; #endif @@ -1825,7 +1882,7 @@ #if (defined(DEBUG) || defined(DEVELOP)) .name = "rpc_os_error_log", #endif - .header_length = NV_SIZEOF32(rpc_os_error_log_v17_00), + .header_length = sizeof(rpc_os_error_log_v17_00), .fdesc = vmiopd_fdesc_t_rpc_os_error_log_v17_00 }; #endif @@ -1855,7 +1912,7 @@ #if (defined(DEBUG) || defined(DEVELOP)) .name = "rpc_rg_line_intr", #endif - .header_length = NV_SIZEOF32(rpc_rg_line_intr_v17_00), + .header_length = sizeof(rpc_rg_line_intr_v17_00), .fdesc = vmiopd_fdesc_t_rpc_rg_line_intr_v17_00 }; #endif @@ -1892,7 +1949,7 @@ #if (defined(DEBUG) || defined(DEVELOP)) .name = "rpc_display_modeset", #endif - .header_length = NV_SIZEOF32(rpc_display_modeset_v01_00), + .header_length = sizeof(rpc_display_modeset_v01_00), .fdesc = vmiopd_fdesc_t_rpc_display_modeset_v01_00 }; #endif @@ -1915,7 +1972,7 @@ #if (defined(DEBUG) || defined(DEVELOP)) .name = "rpc_gpuacct_perfmon_util_samples", #endif - .header_length = NV_SIZEOF32(rpc_gpuacct_perfmon_util_samples_v17_00), + .header_length = sizeof(rpc_gpuacct_perfmon_util_samples_v17_00), .fdesc = vmiopd_fdesc_t_rpc_gpuacct_perfmon_util_samples_v17_00 }; #endif @@ -1945,7 +2002,7 @@ #if (defined(DEBUG) || defined(DEVELOP)) .name = "rpc_vgpu_gsp_plugin_triggered", #endif - .header_length = NV_SIZEOF32(rpc_vgpu_gsp_plugin_triggered_v17_00), + .header_length = sizeof(rpc_vgpu_gsp_plugin_triggered_v17_00), .fdesc = vmiopd_fdesc_t_rpc_vgpu_gsp_plugin_triggered_v17_00 }; #endif @@ -1968,7 +2025,7 @@ #if (defined(DEBUG) || defined(DEVELOP)) .name = "rpc_vgpu_config_event", #endif - .header_length = NV_SIZEOF32(rpc_vgpu_config_event_v17_00), + .header_length = sizeof(rpc_vgpu_config_event_v17_00), .fdesc = vmiopd_fdesc_t_rpc_vgpu_config_event_v17_00 }; #endif @@ -1991,7 +2048,7 @@ #if (defined(DEBUG) || defined(DEVELOP)) .name = "rpc_dce_rm_init", #endif - .header_length = NV_SIZEOF32(rpc_dce_rm_init_v01_00), + .header_length = sizeof(rpc_dce_rm_init_v01_00), .fdesc = vmiopd_fdesc_t_rpc_dce_rm_init_v01_00 }; #endif @@ -2029,7 +2086,7 @@ #if (defined(DEBUG) || defined(DEVELOP)) .name = "rpc_sim_read", #endif - .header_length = NV_SIZEOF32(rpc_sim_read_v1E_01), + .header_length = sizeof(rpc_sim_read_v1E_01), .fdesc = vmiopd_fdesc_t_rpc_sim_read_v1E_01 }; #endif @@ -2074,7 +2131,7 @@ #if (defined(DEBUG) || defined(DEVELOP)) .name = "rpc_sim_write", #endif - .header_length = NV_SIZEOF32(rpc_sim_write_v1E_01), + .header_length = sizeof(rpc_sim_write_v1E_01), .fdesc = vmiopd_fdesc_t_rpc_sim_write_v1E_01 }; #endif @@ -2112,7 +2169,7 @@ #if (defined(DEBUG) || defined(DEVELOP)) .name = "rpc_ucode_libos_print", #endif - .header_length = NV_SIZEOF32(rpc_ucode_libos_print_v1E_08), + .header_length = sizeof(rpc_ucode_libos_print_v1E_08), .fdesc = vmiopd_fdesc_t_rpc_ucode_libos_print_v1E_08 }; #endif @@ -2135,7 +2192,7 @@ #if (defined(DEBUG) || defined(DEVELOP)) .name = "rpc_init_done", #endif - .header_length = NV_SIZEOF32(rpc_init_done_v17_00), + .header_length = sizeof(rpc_init_done_v17_00), .fdesc = vmiopd_fdesc_t_rpc_init_done_v17_00 }; #endif @@ -2200,7 +2257,7 @@ #if (defined(DEBUG) || defined(DEVELOP)) .name = "rpc_semaphore_schedule_callback", #endif - .header_length = NV_SIZEOF32(rpc_semaphore_schedule_callback_v17_00), + .header_length = sizeof(rpc_semaphore_schedule_callback_v17_00), .fdesc = vmiopd_fdesc_t_rpc_semaphore_schedule_callback_v17_00 }; #endif @@ -2258,7 +2315,7 @@ #if (defined(DEBUG) || defined(DEVELOP)) .name = "rpc_timed_semaphore_release", #endif - .header_length = NV_SIZEOF32(rpc_timed_semaphore_release_v01_00), + .header_length = sizeof(rpc_timed_semaphore_release_v01_00), .fdesc = vmiopd_fdesc_t_rpc_timed_semaphore_release_v01_00 }; #endif @@ -2281,7 +2338,7 @@ #if (defined(DEBUG) || defined(DEVELOP)) .name = "rpc_perf_gpu_boost_sync_limits_callback", #endif - .header_length = NV_SIZEOF32(rpc_perf_gpu_boost_sync_limits_callback_v17_00), + .header_length = sizeof(rpc_perf_gpu_boost_sync_limits_callback_v17_00), .fdesc = vmiopd_fdesc_t_rpc_perf_gpu_boost_sync_limits_callback_v17_00 }; #endif @@ -2304,7 +2361,7 @@ #if (defined(DEBUG) || defined(DEVELOP)) .name = "rpc_perf_bridgeless_info_update", #endif - .header_length = NV_SIZEOF32(rpc_perf_bridgeless_info_update_v17_00), + .header_length = sizeof(rpc_perf_bridgeless_info_update_v17_00), .fdesc = vmiopd_fdesc_t_rpc_perf_bridgeless_info_update_v17_00 }; #endif @@ -2327,7 +2384,7 @@ #if (defined(DEBUG) || defined(DEVELOP)) .name = "rpc_nvlink_fault_up", #endif - .header_length = NV_SIZEOF32(rpc_nvlink_fault_up_v17_00), + .header_length = sizeof(rpc_nvlink_fault_up_v17_00), .fdesc = vmiopd_fdesc_t_rpc_nvlink_fault_up_v17_00 }; #endif @@ -2350,7 +2407,7 @@ #if (defined(DEBUG) || defined(DEVELOP)) .name = "rpc_nvlink_inband_received_data_256", #endif - .header_length = NV_SIZEOF32(rpc_nvlink_inband_received_data_256_v17_00), + .header_length = sizeof(rpc_nvlink_inband_received_data_256_v17_00), .fdesc = vmiopd_fdesc_t_rpc_nvlink_inband_received_data_256_v17_00 }; #endif @@ -2373,7 +2430,7 @@ #if (defined(DEBUG) || defined(DEVELOP)) .name = "rpc_nvlink_inband_received_data_512", #endif - .header_length = NV_SIZEOF32(rpc_nvlink_inband_received_data_512_v17_00), + .header_length = sizeof(rpc_nvlink_inband_received_data_512_v17_00), .fdesc = vmiopd_fdesc_t_rpc_nvlink_inband_received_data_512_v17_00 }; #endif @@ -2396,7 +2453,7 @@ #if (defined(DEBUG) || defined(DEVELOP)) .name = "rpc_nvlink_inband_received_data_1024", #endif - .header_length = NV_SIZEOF32(rpc_nvlink_inband_received_data_1024_v17_00), + .header_length = sizeof(rpc_nvlink_inband_received_data_1024_v17_00), .fdesc = vmiopd_fdesc_t_rpc_nvlink_inband_received_data_1024_v17_00 }; #endif @@ -2419,7 +2476,7 @@ #if (defined(DEBUG) || defined(DEVELOP)) .name = "rpc_nvlink_inband_received_data_2048", #endif - .header_length = NV_SIZEOF32(rpc_nvlink_inband_received_data_2048_v17_00), + .header_length = sizeof(rpc_nvlink_inband_received_data_2048_v17_00), .fdesc = vmiopd_fdesc_t_rpc_nvlink_inband_received_data_2048_v17_00 }; #endif @@ -2442,7 +2499,7 @@ #if (defined(DEBUG) || defined(DEVELOP)) .name = "rpc_nvlink_inband_received_data_4096", #endif - .header_length = NV_SIZEOF32(rpc_nvlink_inband_received_data_4096_v17_00), + .header_length = sizeof(rpc_nvlink_inband_received_data_4096_v17_00), .fdesc = vmiopd_fdesc_t_rpc_nvlink_inband_received_data_4096_v17_00 }; #endif @@ -2465,11 +2522,34 @@ #if (defined(DEBUG) || defined(DEVELOP)) .name = "rpc_nvlink_is_gpu_degraded", #endif - .header_length = NV_SIZEOF32(rpc_nvlink_is_gpu_degraded_v17_00), + .header_length = sizeof(rpc_nvlink_is_gpu_degraded_v17_00), .fdesc = vmiopd_fdesc_t_rpc_nvlink_is_gpu_degraded_v17_00 }; #endif +#ifndef SKIP_PRINT_rpc_gsp_send_user_shared_data_v17_00 +static vmiopd_fdesc_t vmiopd_fdesc_t_rpc_gsp_send_user_shared_data_v17_00[] = { + { + .vtype = vtype_NvU32, + .offset = NV_OFFSETOF(rpc_gsp_send_user_shared_data_v17_00, data), + #if (defined(DEBUG) || defined(DEVELOP)) + .name = "data" + #endif + }, + { + .vtype = vt_end + } +}; + +static vmiopd_mdesc_t vmiopd_mdesc_t_rpc_gsp_send_user_shared_data_v17_00 = { + #if (defined(DEBUG) || defined(DEVELOP)) + .name = "rpc_gsp_send_user_shared_data", + #endif + .header_length = sizeof(rpc_gsp_send_user_shared_data_v17_00), + .fdesc = vmiopd_fdesc_t_rpc_gsp_send_user_shared_data_v17_00 +}; +#endif + #ifndef SKIP_PRINT_rpc_set_sysmem_dirty_page_tracking_buffer_v20_00 static vmiopd_fdesc_t vmiopd_fdesc_t_rpc_set_sysmem_dirty_page_tracking_buffer_v20_00[] = { { @@ -2502,7 +2582,7 @@ #if (defined(DEBUG) || defined(DEVELOP)) .name = "rpc_set_sysmem_dirty_page_tracking_buffer", #endif - .header_length = NV_SIZEOF32(rpc_set_sysmem_dirty_page_tracking_buffer_v20_00), + .header_length = sizeof(rpc_set_sysmem_dirty_page_tracking_buffer_v20_00), .fdesc = vmiopd_fdesc_t_rpc_set_sysmem_dirty_page_tracking_buffer_v20_00 }; #endif @@ -2546,7 +2626,7 @@ #if (defined(DEBUG) || defined(DEVELOP)) .name = "rpc_extdev_intr_service", #endif - .header_length = NV_SIZEOF32(rpc_extdev_intr_service_v17_00), + .header_length = sizeof(rpc_extdev_intr_service_v17_00), .fdesc = vmiopd_fdesc_t_rpc_extdev_intr_service_v17_00 }; #endif @@ -2569,11 +2649,56 @@ #if (defined(DEBUG) || defined(DEVELOP)) .name = "rpc_pfm_req_hndlr_state_sync_callback", #endif - .header_length = NV_SIZEOF32(rpc_pfm_req_hndlr_state_sync_callback_v21_04), + .header_length = sizeof(rpc_pfm_req_hndlr_state_sync_callback_v21_04), .fdesc = vmiopd_fdesc_t_rpc_pfm_req_hndlr_state_sync_callback_v21_04 }; #endif +#ifndef SKIP_PRINT_rpc_vgpu_gsp_mig_ci_config_v21_03 +static vmiopd_fdesc_t vmiopd_fdesc_t_rpc_vgpu_gsp_mig_ci_config_v21_03[] = { + { + .vtype = vtype_NvU32, + .offset = NV_OFFSETOF(rpc_vgpu_gsp_mig_ci_config_v21_03, execPartCount), + #if (defined(DEBUG) || defined(DEVELOP)) + .name = "execPartCount" + #endif + }, + { + .vtype = vtype_NvU32_array, + .offset = NV_OFFSETOF(rpc_vgpu_gsp_mig_ci_config_v21_03, execPartId), + .array_length = NVC637_CTRL_MAX_EXEC_PARTITIONS, + #if (defined(DEBUG) || defined(DEVELOP)) + .name = "execPartId" + #endif + }, + { + .vtype = vtype_NvU32, + .offset = NV_OFFSETOF(rpc_vgpu_gsp_mig_ci_config_v21_03, gfid), + #if (defined(DEBUG) || defined(DEVELOP)) + .name = "gfid" + #endif + }, + { + .vtype = vtype_NvBool, + .offset = NV_OFFSETOF(rpc_vgpu_gsp_mig_ci_config_v21_03, bDelete), + #if (defined(DEBUG) || defined(DEVELOP)) + .name = "bDelete" + #endif + }, + { + .vtype = vt_end + } +}; + +static vmiopd_mdesc_t vmiopd_mdesc_t_rpc_vgpu_gsp_mig_ci_config_v21_03 = { + #if (defined(DEBUG) || defined(DEVELOP)) + .name = "rpc_vgpu_gsp_mig_ci_config", + #endif + .header_length = sizeof(rpc_vgpu_gsp_mig_ci_config_v21_03), + .fdesc = vmiopd_fdesc_t_rpc_vgpu_gsp_mig_ci_config_v21_03 +}; +#endif + #ifndef SKIP_PRINT_rpc_gsp_lockdown_notice_v17_00 static vmiopd_fdesc_t vmiopd_fdesc_t_rpc_gsp_lockdown_notice_v17_00[] = { { @@ -2592,7 +2717,7 @@ #if (defined(DEBUG) || defined(DEVELOP)) .name = "rpc_gsp_lockdown_notice", #endif - .header_length = NV_SIZEOF32(rpc_gsp_lockdown_notice_v17_00), + .header_length = sizeof(rpc_gsp_lockdown_notice_v17_00), .fdesc = vmiopd_fdesc_t_rpc_gsp_lockdown_notice_v17_00 }; #endif @@ -2779,6 +2904,13 @@ } #endif +#ifndef SKIP_PRINT_rpc_ecc_notifier_write_ack_v23_05 +vmiopd_mdesc_t *rpcdebugEccNotifierWriteAck_v23_05(void) +{ + return &vmiopd_mdesc_t_rpc_ecc_notifier_write_ack_v23_05; +} +#endif + #ifndef SKIP_PRINT_rpc_gsp_set_system_info_v17_00 vmiopd_mdesc_t *rpcdebugGspSetSystemInfo_v17_00(void) { @@ -2989,6 +3121,13 @@ } #endif +#ifndef SKIP_PRINT_rpc_gsp_send_user_shared_data_v17_00 +vmiopd_mdesc_t *rpcdebugGspSendUserSharedData_v17_00(void) +{ + return &vmiopd_mdesc_t_rpc_gsp_send_user_shared_data_v17_00; +} +#endif + #ifndef SKIP_PRINT_rpc_set_sysmem_dirty_page_tracking_buffer_v20_00 vmiopd_mdesc_t *rpcdebugSetSysmemDirtyPageTrackingBuffer_v20_00(void) { @@ -3010,6 +3149,13 @@ } #endif +#ifndef SKIP_PRINT_rpc_vgpu_gsp_mig_ci_config_v21_03 +vmiopd_mdesc_t *rpcdebugVgpuGspMigCiConfig_v21_03(void) +{ + return &vmiopd_mdesc_t_rpc_vgpu_gsp_mig_ci_config_v21_03; +} +#endif + #ifndef SKIP_PRINT_rpc_gsp_lockdown_notice_v17_00 vmiopd_mdesc_t *rpcdebugGspLockdownNotice_v17_00(void) { @@ -3121,12 +3267,16 @@ rpc_nvlink_inband_received_data_4096_v nvlink_inband_received_data_4096_v; rpc_nvlink_is_gpu_degraded_v17_00 nvlink_is_gpu_degraded_v17_00; rpc_nvlink_is_gpu_degraded_v nvlink_is_gpu_degraded_v; + rpc_gsp_send_user_shared_data_v17_00 gsp_send_user_shared_data_v17_00; + rpc_gsp_send_user_shared_data_v gsp_send_user_shared_data_v; rpc_set_sysmem_dirty_page_tracking_buffer_v20_00 set_sysmem_dirty_page_tracking_buffer_v20_00; rpc_set_sysmem_dirty_page_tracking_buffer_v set_sysmem_dirty_page_tracking_buffer_v; rpc_extdev_intr_service_v17_00 extdev_intr_service_v17_00; rpc_extdev_intr_service_v extdev_intr_service_v; rpc_pfm_req_hndlr_state_sync_callback_v21_04 pfm_req_hndlr_state_sync_callback_v21_04; rpc_pfm_req_hndlr_state_sync_callback_v pfm_req_hndlr_state_sync_callback_v; + rpc_vgpu_gsp_mig_ci_config_v21_03 vgpu_gsp_mig_ci_config_v21_03; + rpc_vgpu_gsp_mig_ci_config_v vgpu_gsp_mig_ci_config_v; rpc_gsp_lockdown_notice_v17_00 gsp_lockdown_notice_v17_00; rpc_gsp_lockdown_notice_v gsp_lockdown_notice_v; } rpc_generic_union; diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/generated/g_rpc_hal.h nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_rpc_hal.h --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/generated/g_rpc_hal.h 2023-10-25 20:19:43.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_rpc_hal.h 2024-03-05 22:11:42.000000000 +0000 @@ -66,6 +66,7 @@ typedef NV_STATUS RpcVgpuPfRegRead32(POBJGPU, POBJRPC, NvU64, NvU32*, NvU32); typedef NV_STATUS RpcDumpProtobufComponent(POBJGPU, POBJRPC, PRB_ENCODER *pPrbEnc, NVD_STATE *pNvDumpState, NVDUMP_COMPONENT component); +typedef NV_STATUS RpcEccNotifierWriteAck(POBJGPU, POBJRPC); typedef NV_STATUS RpcAllocMemory(POBJGPU, POBJRPC, NvHandle, NvHandle, NvHandle, NvU32, NvU32, MEMORY_DESCRIPTOR*); typedef NV_STATUS RpcGpuExecRegOps(POBJGPU, POBJRPC, NvHandle, NvHandle, @@ -100,6 +101,7 @@ typedef struct RPC_HAL_IFACES { RpcVgpuPfRegRead32 *rpcVgpuPfRegRead32; /* Read reg value from plugin */ RpcDumpProtobufComponent *rpcDumpProtobufComponent; /* Dump a GSP component into the protobuf. */ + RpcEccNotifierWriteAck *rpcEccNotifierWriteAck; /* ECC_NOTIFIER_WRITE_ACK */ RpcAllocMemory *rpcAllocMemory; /* ALLOC_MEMORY */ RpcGpuExecRegOps *rpcGpuExecRegOps; /* GPU_EXEC_REG_OPS */ RpcRmfsInit *rpcRmfsInit; /* Resman File Streaming Init */ @@ -130,6 +132,8 @@ (_pRpc)->_hal.rpcVgpuPfRegRead32(_pGpu, _pRpc, _arg0, _pArg1, _arg2) #define rpcDumpProtobufComponent_HAL(_pGpu, _pRpc, _pPrbEnc, _pNvDumpState, _component) \ (_pRpc)->_hal.rpcDumpProtobufComponent(_pGpu, _pRpc, _pPrbEnc, _pNvDumpState, _component) +#define rpcEccNotifierWriteAck_HAL(_pGpu, _pRpc) \ + (_pRpc)->_hal.rpcEccNotifierWriteAck(_pGpu, _pRpc) #define rpcAllocMemory_HAL(_pGpu, _pRpc, _arg0, _arg1, _arg2, _arg3, _arg4, _pArg5) \ (_pRpc)->_hal.rpcAllocMemory(_pGpu, _pRpc, _arg0, _arg1, _arg2, _arg3, _arg4, _pArg5) #define rpcGpuExecRegOps_HAL(_pGpu, _pRpc, _arg0, _arg1, _pArg2, _pArg3) \ diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/generated/g_rpc_iom.c nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_rpc_iom.c --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/generated/g_rpc_iom.c 2023-10-25 20:19:43.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_rpc_iom.c 2024-03-05 22:11:42.000000000 +0000 @@ -41,7 +41,7 @@ // pRpcMethods->__rpcRecvPollUvm__ = rpcRecvPollUvm_IMPL; # ONLY_IF => VIRTUALIZATION } -void +static void rpcSetPropertiesSpecial ( POBJRPC pRpc diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/generated/g_rpc_private.h nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_rpc_private.h --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/generated/g_rpc_private.h 2023-10-25 20:19:43.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_rpc_private.h 2024-03-05 22:11:42.000000000 +0000 @@ -21,6 +21,10 @@ RpcDumpProtobufComponent rpcDumpProtobufComponent_v18_12; RpcDumpProtobufComponent rpcDumpProtobufComponent_STUB; // TU10X, GA100, GA102, GA103, GA104, GA106, GA107, AD102, AD103, AD104, AD106, AD107, GH10X + // RPC:ECC_NOTIFIER_WRITE_ACK +RpcEccNotifierWriteAck rpcEccNotifierWriteAck_v23_05; +RpcEccNotifierWriteAck rpcEccNotifierWriteAck_STUB; // TU10X, GA100, GA102, GA103, GA104, GA106, GA107, AD102, AD103, AD104, AD106, AD107, GH10X + // RPC:ALLOC_MEMORY RpcAllocMemory rpcAllocMemory_v13_01; RpcAllocMemory rpcAllocMemory_STUB; // TU10X, GA100, GA102, GA103, GA104, GA106, GA107, AD102, AD103, AD104, AD106, AD107, GH10X @@ -2351,6 +2355,91 @@ #endif // } +// No enabled chips use this variant provider +static void rpc_iGrp_ipVersions_Install_v22_01(IGRP_IP_VERSIONS_TABLE_INFO *pInfo) +{ +#if 0 + + POBJGPU pGpu = pInfo->pGpu; + OBJRPC *pRpc = (OBJRPC *) pInfo->pDynamic; + RPC_HAL_IFACES *pRpcHal = &pRpc->_hal; + + // avoid possible unused warnings + pGpu += 0; + pRpcHal += 0; + + +#endif // +} + +// No enabled chips use this variant provider +static void rpc_iGrp_ipVersions_Install_v23_02(IGRP_IP_VERSIONS_TABLE_INFO *pInfo) +{ +#if 0 + + POBJGPU pGpu = pInfo->pGpu; + OBJRPC *pRpc = (OBJRPC *) pInfo->pDynamic; + RPC_HAL_IFACES *pRpcHal = &pRpc->_hal; + + // avoid possible unused warnings + pGpu += 0; + pRpcHal += 0; + + +#endif // +} + +// No enabled chips use this variant provider +static void rpc_iGrp_ipVersions_Install_v23_03(IGRP_IP_VERSIONS_TABLE_INFO *pInfo) +{ +#if 0 + + POBJGPU pGpu = pInfo->pGpu; + OBJRPC *pRpc = (OBJRPC *) pInfo->pDynamic; + RPC_HAL_IFACES *pRpcHal = &pRpc->_hal; + + // avoid possible unused warnings + pGpu += 0; + pRpcHal += 0; + + +#endif // +} + +// No enabled chips use this variant provider +static void rpc_iGrp_ipVersions_Install_v23_04(IGRP_IP_VERSIONS_TABLE_INFO *pInfo) +{ +#if 0 + + POBJGPU pGpu = pInfo->pGpu; + OBJRPC *pRpc = (OBJRPC *) pInfo->pDynamic; + RPC_HAL_IFACES *pRpcHal = &pRpc->_hal; + + // avoid possible unused warnings + pGpu += 0; + pRpcHal += 0; + + +#endif // +} + +// No enabled chips use this variant provider +static void rpc_iGrp_ipVersions_Install_v23_05(IGRP_IP_VERSIONS_TABLE_INFO *pInfo) +{ +#if 0 + + POBJGPU pGpu = pInfo->pGpu; + OBJRPC *pRpc = (OBJRPC *) pInfo->pDynamic; + RPC_HAL_IFACES *pRpcHal = &pRpc->_hal; + + // avoid possible unused warnings + pGpu += 0; + pRpcHal += 0; + + +#endif // +} + @@ -2371,6 +2460,8 @@ pRpcHal->rpcVgpuPfRegRead32 = rpcVgpuPfRegRead32_v15_00; if (IsIPVersionInRange(pRpc, 0x18120000, 0xFFFFFFFF)) pRpcHal->rpcDumpProtobufComponent = rpcDumpProtobufComponent_v18_12; + if (IsIPVersionInRange(pRpc, 0x23050000, 0xFFFFFFFF)) + pRpcHal->rpcEccNotifierWriteAck = rpcEccNotifierWriteAck_v23_05; if (IsIPVersionInRange(pRpc, 0x13010000, 0xFFFFFFFF)) pRpcHal->rpcAllocMemory = rpcAllocMemory_v13_01; if (IsIPVersionInRange(pRpc, 0x12010000, 0xFFFFFFFF)) @@ -2441,6 +2532,7 @@ _RPC_HAL_VERIFY_INTERFACE(pRpcHal->rpcVgpuPfRegRead32); _RPC_HAL_VERIFY_INTERFACE(pRpcHal->rpcDumpProtobufComponent); + _RPC_HAL_VERIFY_INTERFACE(pRpcHal->rpcEccNotifierWriteAck); _RPC_HAL_VERIFY_INTERFACE(pRpcHal->rpcAllocMemory); _RPC_HAL_VERIFY_INTERFACE(pRpcHal->rpcGpuExecRegOps); _RPC_HAL_VERIFY_INTERFACE(pRpcHal->rpcRmfsInit); @@ -2860,6 +2952,21 @@ static const IGRP_IP_VERSION_RANGE RPC_IGRP_IP_VERSIONS_RANGES_v21_0B[] = { { 0x210B0000, 0xFFFFFFFF, }, // }; + static const IGRP_IP_VERSION_RANGE RPC_IGRP_IP_VERSIONS_RANGES_v22_01[] = { + { 0x22010000, 0xFFFFFFFF, }, // + }; + static const IGRP_IP_VERSION_RANGE RPC_IGRP_IP_VERSIONS_RANGES_v23_02[] = { + { 0x23020000, 0xFFFFFFFF, }, // + }; + static const IGRP_IP_VERSION_RANGE RPC_IGRP_IP_VERSIONS_RANGES_v23_03[] = { + { 0x23030000, 0xFFFFFFFF, }, // + }; + static const IGRP_IP_VERSION_RANGE RPC_IGRP_IP_VERSIONS_RANGES_v23_04[] = { + { 0x23040000, 0xFFFFFFFF, }, // + }; + static const IGRP_IP_VERSION_RANGE RPC_IGRP_IP_VERSIONS_RANGES_v23_05[] = { + { 0x23050000, 0xFFFFFFFF, }, // + }; #define _RPC_HAL_IGRP_ENTRY_INIT(v) \ { RPC_IGRP_IP_VERSIONS_RANGES_##v, NV_ARRAY_ELEMENTS(RPC_IGRP_IP_VERSIONS_RANGES_##v), rpc_iGrp_ipVersions_Install_##v, } @@ -2996,6 +3103,11 @@ _RPC_HAL_IGRP_ENTRY_INIT(v21_09), // _RPC_HAL_IGRP_ENTRY_INIT(v21_0A), // _RPC_HAL_IGRP_ENTRY_INIT(v21_0B), // + _RPC_HAL_IGRP_ENTRY_INIT(v22_01), // + _RPC_HAL_IGRP_ENTRY_INIT(v23_02), // + _RPC_HAL_IGRP_ENTRY_INIT(v23_03), // + _RPC_HAL_IGRP_ENTRY_INIT(v23_04), // + _RPC_HAL_IGRP_ENTRY_INIT(v23_05), // }; #undef _RPC_HAL_IGRP_ENTRY_INIT @@ -3022,6 +3134,7 @@ { rpcVgpuPfRegRead32_STUB, // rpcVgpuPfRegRead32 rpcDumpProtobufComponent_STUB, // rpcDumpProtobufComponent + rpcEccNotifierWriteAck_STUB, // rpcEccNotifierWriteAck rpcAllocMemory_STUB, // rpcAllocMemory rpcGpuExecRegOps_STUB, // rpcGpuExecRegOps rpcRmfsInit_STUB, // rpcRmfsInit @@ -3095,6 +3208,7 @@ { rpcVgpuPfRegRead32_STUB, // rpcVgpuPfRegRead32 rpcDumpProtobufComponent_STUB, // rpcDumpProtobufComponent + rpcEccNotifierWriteAck_STUB, // rpcEccNotifierWriteAck rpcAllocMemory_STUB, // rpcAllocMemory rpcGpuExecRegOps_STUB, // rpcGpuExecRegOps rpcRmfsInit_STUB, // rpcRmfsInit @@ -3178,6 +3292,7 @@ { rpcVgpuPfRegRead32_STUB, // rpcVgpuPfRegRead32 rpcDumpProtobufComponent_STUB, // rpcDumpProtobufComponent + rpcEccNotifierWriteAck_STUB, // rpcEccNotifierWriteAck rpcAllocMemory_STUB, // rpcAllocMemory rpcGpuExecRegOps_STUB, // rpcGpuExecRegOps rpcRmfsInit_STUB, // rpcRmfsInit @@ -3251,6 +3366,7 @@ { rpcVgpuPfRegRead32_STUB, // rpcVgpuPfRegRead32 rpcDumpProtobufComponent_STUB, // rpcDumpProtobufComponent + rpcEccNotifierWriteAck_STUB, // rpcEccNotifierWriteAck rpcAllocMemory_STUB, // rpcAllocMemory rpcGpuExecRegOps_STUB, // rpcGpuExecRegOps rpcRmfsInit_STUB, // rpcRmfsInit diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/generated/g_rs_client_nvoc.c nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_rs_client_nvoc.c --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/generated/g_rs_client_nvoc.c 2023-10-25 20:27:18.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_rs_client_nvoc.c 2024-03-05 22:18:44.000000000 +0000 @@ -136,13 +136,16 @@ Object *pParentObj; RsClient *pThis; - pThis = portMemAllocNonPaged(sizeof(RsClient)); - if (pThis == NULL) return NV_ERR_NO_MEMORY; + status = __nvoc_handleObjCreateMemAlloc(createFlags, sizeof(RsClient), (void**)&pThis, (void**)ppThis); + if (status != NV_OK) + return status; portMemSet(pThis, 0, sizeof(RsClient)); __nvoc_initRtti(staticCast(pThis, Dynamic), &__nvoc_class_def_RsClient); + pThis->__nvoc_base_Object.createFlags = createFlags; + if (pParent != NULL && !(createFlags & NVOC_OBJ_CREATE_FLAGS_PARENT_HALSPEC_ONLY)) { pParentObj = dynamicCast(pParent, Object); @@ -158,11 +161,17 @@ if (status != NV_OK) goto __nvoc_objCreate_RsClient_cleanup; *ppThis = pThis; + return NV_OK; __nvoc_objCreate_RsClient_cleanup: // do not call destructors here since the constructor already called them - portMemFree(pThis); + if (createFlags & NVOC_OBJ_CREATE_FLAGS_IN_PLACE_CONSTRUCT) + portMemSet(pThis, 0, sizeof(RsClient)); + else + portMemFree(pThis); + + // coverity[leaked_storage:FALSE] return status; } @@ -263,6 +272,10 @@ resAddAdditionalDependants(pClient, (struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_RsClientResource_RsResource.offset), pReference); } +static NV_STATUS __nvoc_thunk_RsResource_clientresControlSerialization_Prologue(struct RsClientResource *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return resControlSerialization_Prologue((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_RsClientResource_RsResource.offset), pCallContext, pParams); +} + static NvBool __nvoc_thunk_RsResource_clientresCanCopy(struct RsClientResource *pResource) { return resCanCopy((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_RsClientResource_RsResource.offset)); } @@ -283,6 +296,10 @@ return resIsDuplicate((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_RsClientResource_RsResource.offset), hMemory, pDuplicate); } +static void __nvoc_thunk_RsResource_clientresControlSerialization_Epilogue(struct RsClientResource *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + resControlSerialization_Epilogue((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_RsClientResource_RsResource.offset), pCallContext, pParams); +} + static void __nvoc_thunk_RsResource_clientresControl_Epilogue(struct RsClientResource *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { resControl_Epilogue((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_RsClientResource_RsResource.offset), pCallContext, pParams); } @@ -352,6 +369,8 @@ pThis->__clientresAddAdditionalDependants__ = &__nvoc_thunk_RsResource_clientresAddAdditionalDependants; + pThis->__clientresControlSerialization_Prologue__ = &__nvoc_thunk_RsResource_clientresControlSerialization_Prologue; + pThis->__clientresCanCopy__ = &__nvoc_thunk_RsResource_clientresCanCopy; pThis->__clientresControl_Prologue__ = &__nvoc_thunk_RsResource_clientresControl_Prologue; @@ -362,6 +381,8 @@ pThis->__clientresIsDuplicate__ = &__nvoc_thunk_RsResource_clientresIsDuplicate; + pThis->__clientresControlSerialization_Epilogue__ = &__nvoc_thunk_RsResource_clientresControlSerialization_Epilogue; + pThis->__clientresControl_Epilogue__ = &__nvoc_thunk_RsResource_clientresControl_Epilogue; pThis->__clientresControlLookup__ = &__nvoc_thunk_RsResource_clientresControlLookup; @@ -389,13 +410,16 @@ Object *pParentObj; RsClientResource *pThis; - pThis = portMemAllocNonPaged(sizeof(RsClientResource)); - if (pThis == NULL) return NV_ERR_NO_MEMORY; + status = __nvoc_handleObjCreateMemAlloc(createFlags, sizeof(RsClientResource), (void**)&pThis, (void**)ppThis); + if (status != NV_OK) + return status; portMemSet(pThis, 0, sizeof(RsClientResource)); __nvoc_initRtti(staticCast(pThis, Dynamic), &__nvoc_class_def_RsClientResource); + pThis->__nvoc_base_RsResource.__nvoc_base_Object.createFlags = createFlags; + if (pParent != NULL && !(createFlags & NVOC_OBJ_CREATE_FLAGS_PARENT_HALSPEC_ONLY)) { pParentObj = dynamicCast(pParent, Object); @@ -411,11 +435,17 @@ if (status != NV_OK) goto __nvoc_objCreate_RsClientResource_cleanup; *ppThis = pThis; + return NV_OK; __nvoc_objCreate_RsClientResource_cleanup: // do not call destructors here since the constructor already called them - portMemFree(pThis); + if (createFlags & NVOC_OBJ_CREATE_FLAGS_IN_PLACE_CONSTRUCT) + portMemSet(pThis, 0, sizeof(RsClientResource)); + else + portMemFree(pThis); + + // coverity[leaked_storage:FALSE] return status; } diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/generated/g_rs_client_nvoc.h nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_rs_client_nvoc.h --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/generated/g_rs_client_nvoc.h 2023-10-25 20:27:18.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_rs_client_nvoc.h 2024-03-05 22:18:44.000000000 +0000 @@ -94,6 +94,8 @@ CLIENT_TYPE type; NvBool bActive; NvBool bResourceWarning; + NvBool bDisabled; + NvBool bHighPriorityFreeDone; RsRefMap resourceMap; AccessBackRefList accessBackRefList; NvHandle handleRangeStart; @@ -102,6 +104,7 @@ NvHandle handleGenIdx; RsRefFreeList pendingFreeList; struct RS_FREE_STACK *pFreeStack; + struct ListNode disabledClientNode; }; #ifndef __NVOC_CLASS_RsClient_TYPEDEF__ @@ -392,6 +395,7 @@ #undef PRIVATE_FIELD +MAKE_INTRUSIVE_LIST(RsDisabledClientList, RsClient, disabledClientNode); /** * Get an iterator to the elements in the client's resource map @@ -434,6 +438,14 @@ */ NvBool clientRefOrderedIterNext(struct RsClient *pClient, RS_ORDERED_ITERATOR *pIt); +/** + * Release all CPU address mappings for a resource + * + * @param[in] pClient Client that owns the resource + * @param[in] pCallContext Caller information (which includes the resource reference whose mappings will be freed) + * @param[in] pLockInfo Information about which locks are already held, for recursive calls + */ +NV_STATUS clientUnmapResourceRefMappings(struct RsClient *pClient, CALL_CONTEXT *pCallContext, RS_LOCK_INFO *pLockInfo); /** * RsResource interface to a RsClient @@ -467,11 +479,13 @@ NvU32 (*__clientresGetRefCount__)(struct RsClientResource *); NV_STATUS (*__clientresControlFilter__)(struct RsClientResource *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); void (*__clientresAddAdditionalDependants__)(struct RsClient *, struct RsClientResource *, RsResourceRef *); + NV_STATUS (*__clientresControlSerialization_Prologue__)(struct RsClientResource *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); NvBool (*__clientresCanCopy__)(struct RsClientResource *); NV_STATUS (*__clientresControl_Prologue__)(struct RsClientResource *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); void (*__clientresPreDestruct__)(struct RsClientResource *); NV_STATUS (*__clientresUnmapFrom__)(struct RsClientResource *, RS_RES_UNMAP_FROM_PARAMS *); NV_STATUS (*__clientresIsDuplicate__)(struct RsClientResource *, NvHandle, NvBool *); + void (*__clientresControlSerialization_Epilogue__)(struct RsClientResource *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); void (*__clientresControl_Epilogue__)(struct RsClientResource *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); NV_STATUS (*__clientresControlLookup__)(struct RsClientResource *, struct RS_RES_CONTROL_PARAMS_INTERNAL *, const struct NVOC_EXPORTED_METHOD_DEF **); NV_STATUS (*__clientresMap__)(struct RsClientResource *, struct CALL_CONTEXT *, RS_CPU_MAP_PARAMS *, RsCpuMapping *); @@ -514,11 +528,13 @@ #define clientresGetRefCount(pResource) clientresGetRefCount_DISPATCH(pResource) #define clientresControlFilter(pResource, pCallContext, pParams) clientresControlFilter_DISPATCH(pResource, pCallContext, pParams) #define clientresAddAdditionalDependants(pClient, pResource, pReference) clientresAddAdditionalDependants_DISPATCH(pClient, pResource, pReference) +#define clientresControlSerialization_Prologue(pResource, pCallContext, pParams) clientresControlSerialization_Prologue_DISPATCH(pResource, pCallContext, pParams) #define clientresCanCopy(pResource) clientresCanCopy_DISPATCH(pResource) #define clientresControl_Prologue(pResource, pCallContext, pParams) clientresControl_Prologue_DISPATCH(pResource, pCallContext, pParams) #define clientresPreDestruct(pResource) clientresPreDestruct_DISPATCH(pResource) #define clientresUnmapFrom(pResource, pParams) clientresUnmapFrom_DISPATCH(pResource, pParams) #define clientresIsDuplicate(pResource, hMemory, pDuplicate) clientresIsDuplicate_DISPATCH(pResource, hMemory, pDuplicate) +#define clientresControlSerialization_Epilogue(pResource, pCallContext, pParams) clientresControlSerialization_Epilogue_DISPATCH(pResource, pCallContext, pParams) #define clientresControl_Epilogue(pResource, pCallContext, pParams) clientresControl_Epilogue_DISPATCH(pResource, pCallContext, pParams) #define clientresControlLookup(pResource, pParams, ppEntry) clientresControlLookup_DISPATCH(pResource, pParams, ppEntry) #define clientresMap(pResource, pCallContext, pParams, pCpuMapping) clientresMap_DISPATCH(pResource, pCallContext, pParams, pCpuMapping) @@ -551,6 +567,10 @@ pResource->__clientresAddAdditionalDependants__(pClient, pResource, pReference); } +static inline NV_STATUS clientresControlSerialization_Prologue_DISPATCH(struct RsClientResource *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return pResource->__clientresControlSerialization_Prologue__(pResource, pCallContext, pParams); +} + static inline NvBool clientresCanCopy_DISPATCH(struct RsClientResource *pResource) { return pResource->__clientresCanCopy__(pResource); } @@ -571,6 +591,10 @@ return pResource->__clientresIsDuplicate__(pResource, hMemory, pDuplicate); } +static inline void clientresControlSerialization_Epilogue_DISPATCH(struct RsClientResource *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + pResource->__clientresControlSerialization_Epilogue__(pResource, pCallContext, pParams); +} + static inline void clientresControl_Epilogue_DISPATCH(struct RsClientResource *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { pResource->__clientresControl_Epilogue__(pResource, pCallContext, pParams); } @@ -604,6 +628,7 @@ NvHandle hDomain; ///< [in] The parent domain NvHandle hClient; ///< [in] The client handle NvBool bHiPriOnly; ///< [in] Only free high priority resources + NvBool bDisableOnly; ///< [in] Only disable the listed clients, do not free them yet NvU32 state; ///< [in] User-defined state RS_RES_FREE_PARAMS_INTERNAL *pResFreeParams; ///< [in] Necessary for locking state diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/generated/g_rs_resource_nvoc.c nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_rs_resource_nvoc.c --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/generated/g_rs_resource_nvoc.c 2023-10-25 20:27:18.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_rs_resource_nvoc.c 2024-03-05 22:18:44.000000000 +0000 @@ -108,6 +108,10 @@ pThis->__resControlFilter__ = &resControlFilter_IMPL; + pThis->__resControlSerialization_Prologue__ = &resControlSerialization_Prologue_IMPL; + + pThis->__resControlSerialization_Epilogue__ = &resControlSerialization_Epilogue_IMPL; + pThis->__resControl_Prologue__ = &resControl_Prologue_IMPL; pThis->__resControl_Epilogue__ = &resControl_Epilogue_IMPL; @@ -146,13 +150,16 @@ Object *pParentObj; RsResource *pThis; - pThis = portMemAllocNonPaged(sizeof(RsResource)); - if (pThis == NULL) return NV_ERR_NO_MEMORY; + status = __nvoc_handleObjCreateMemAlloc(createFlags, sizeof(RsResource), (void**)&pThis, (void**)ppThis); + if (status != NV_OK) + return status; portMemSet(pThis, 0, sizeof(RsResource)); __nvoc_initRtti(staticCast(pThis, Dynamic), &__nvoc_class_def_RsResource); + pThis->__nvoc_base_Object.createFlags = createFlags; + if (pParent != NULL && !(createFlags & NVOC_OBJ_CREATE_FLAGS_PARENT_HALSPEC_ONLY)) { pParentObj = dynamicCast(pParent, Object); @@ -168,11 +175,17 @@ if (status != NV_OK) goto __nvoc_objCreate_RsResource_cleanup; *ppThis = pThis; + return NV_OK; __nvoc_objCreate_RsResource_cleanup: // do not call destructors here since the constructor already called them - portMemFree(pThis); + if (createFlags & NVOC_OBJ_CREATE_FLAGS_IN_PLACE_CONSTRUCT) + portMemSet(pThis, 0, sizeof(RsResource)); + else + portMemFree(pThis); + + // coverity[leaked_storage:FALSE] return status; } diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/generated/g_rs_resource_nvoc.h nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_rs_resource_nvoc.h --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/generated/g_rs_resource_nvoc.h 2023-10-25 20:27:19.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_rs_resource_nvoc.h 2024-03-05 22:18:44.000000000 +0000 @@ -109,6 +109,7 @@ API_SECURITY_INFO *pSecInfo; void *pAllocParams; ///< [in] Copied-in allocation parameters + NvU32 paramsSize; ///< [in] Copied-in allocation parameters size // ... Dupe alloc struct RsClient *pSrcClient; ///< The client that is sharing the resource @@ -159,6 +160,7 @@ // Internal use only NvBool bHiPriOnly; ///< [in] Only free if this is a high priority resources + NvBool bDisableOnly; ///< [in] Disable the target instead of freeing it (only applies to clients) RS_LOCK_INFO *pLockInfo; ///< [inout] Locking flags and state NvU32 freeFlags; ///< [in] Flags for the free operation NvU32 freeState; ///< [inout] Free state @@ -249,6 +251,8 @@ NV_STATUS (*__resControlLookup__)(struct RsResource *, struct RS_RES_CONTROL_PARAMS_INTERNAL *, const struct NVOC_EXPORTED_METHOD_DEF **); NV_STATUS (*__resControl__)(struct RsResource *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); NV_STATUS (*__resControlFilter__)(struct RsResource *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); + NV_STATUS (*__resControlSerialization_Prologue__)(struct RsResource *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); + void (*__resControlSerialization_Epilogue__)(struct RsResource *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); NV_STATUS (*__resControl_Prologue__)(struct RsResource *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); void (*__resControl_Epilogue__)(struct RsResource *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); NV_STATUS (*__resMap__)(struct RsResource *, struct CALL_CONTEXT *, RS_CPU_MAP_PARAMS *, RsCpuMapping *); @@ -298,6 +302,8 @@ #define resControlLookup(pResource, pParams, ppEntry) resControlLookup_DISPATCH(pResource, pParams, ppEntry) #define resControl(pResource, pCallContext, pParams) resControl_DISPATCH(pResource, pCallContext, pParams) #define resControlFilter(pResource, pCallContext, pParams) resControlFilter_DISPATCH(pResource, pCallContext, pParams) +#define resControlSerialization_Prologue(pResource, pCallContext, pParams) resControlSerialization_Prologue_DISPATCH(pResource, pCallContext, pParams) +#define resControlSerialization_Epilogue(pResource, pCallContext, pParams) resControlSerialization_Epilogue_DISPATCH(pResource, pCallContext, pParams) #define resControl_Prologue(pResource, pCallContext, pParams) resControl_Prologue_DISPATCH(pResource, pCallContext, pParams) #define resControl_Epilogue(pResource, pCallContext, pParams) resControl_Epilogue_DISPATCH(pResource, pCallContext, pParams) #define resMap(pResource, pCallContext, pParams, pCpuMapping) resMap_DISPATCH(pResource, pCallContext, pParams, pCpuMapping) @@ -344,6 +350,18 @@ return pResource->__resControlFilter__(pResource, pCallContext, pParams); } +NV_STATUS resControlSerialization_Prologue_IMPL(struct RsResource *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams); + +static inline NV_STATUS resControlSerialization_Prologue_DISPATCH(struct RsResource *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return pResource->__resControlSerialization_Prologue__(pResource, pCallContext, pParams); +} + +void resControlSerialization_Epilogue_IMPL(struct RsResource *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams); + +static inline void resControlSerialization_Epilogue_DISPATCH(struct RsResource *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + pResource->__resControlSerialization_Epilogue__(pResource, pCallContext, pParams); +} + NV_STATUS resControl_Prologue_IMPL(struct RsResource *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams); static inline NV_STATUS resControl_Prologue_DISPATCH(struct RsResource *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { @@ -821,7 +839,7 @@ /** * Remove the dependency between this resource reference and a dependent resource reference. */ -NV_STATUS refRemoveDependant(RsResourceRef *pResourceRef, RsResourceRef *pDependantRef); +void refRemoveDependant(RsResourceRef *pResourceRef, RsResourceRef *pDependantRef); /** * Find, Add, or Remove an inter-mapping between two resources to the Mapper's list of inter-mappings diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/generated/g_rs_server_nvoc.c nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_rs_server_nvoc.c --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/generated/g_rs_server_nvoc.c 2023-10-25 20:27:35.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_rs_server_nvoc.c 2024-03-05 22:18:54.000000000 +0000 @@ -114,13 +114,16 @@ Object *pParentObj; RsShared *pThis; - pThis = portMemAllocNonPaged(sizeof(RsShared)); - if (pThis == NULL) return NV_ERR_NO_MEMORY; + status = __nvoc_handleObjCreateMemAlloc(createFlags, sizeof(RsShared), (void**)&pThis, (void**)ppThis); + if (status != NV_OK) + return status; portMemSet(pThis, 0, sizeof(RsShared)); __nvoc_initRtti(staticCast(pThis, Dynamic), &__nvoc_class_def_RsShared); + pThis->__nvoc_base_Object.createFlags = createFlags; + if (pParent != NULL && !(createFlags & NVOC_OBJ_CREATE_FLAGS_PARENT_HALSPEC_ONLY)) { pParentObj = dynamicCast(pParent, Object); @@ -136,11 +139,17 @@ if (status != NV_OK) goto __nvoc_objCreate_RsShared_cleanup; *ppThis = pThis; + return NV_OK; __nvoc_objCreate_RsShared_cleanup: // do not call destructors here since the constructor already called them - portMemFree(pThis); + if (createFlags & NVOC_OBJ_CREATE_FLAGS_IN_PLACE_CONSTRUCT) + portMemSet(pThis, 0, sizeof(RsShared)); + else + portMemFree(pThis); + + // coverity[leaked_storage:FALSE] return status; } @@ -273,13 +282,16 @@ Object *pParentObj; RsSession *pThis; - pThis = portMemAllocNonPaged(sizeof(RsSession)); - if (pThis == NULL) return NV_ERR_NO_MEMORY; + status = __nvoc_handleObjCreateMemAlloc(createFlags, sizeof(RsSession), (void**)&pThis, (void**)ppThis); + if (status != NV_OK) + return status; portMemSet(pThis, 0, sizeof(RsSession)); __nvoc_initRtti(staticCast(pThis, Dynamic), &__nvoc_class_def_RsSession); + pThis->__nvoc_base_RsShared.__nvoc_base_Object.createFlags = createFlags; + if (pParent != NULL && !(createFlags & NVOC_OBJ_CREATE_FLAGS_PARENT_HALSPEC_ONLY)) { pParentObj = dynamicCast(pParent, Object); @@ -295,11 +307,17 @@ if (status != NV_OK) goto __nvoc_objCreate_RsSession_cleanup; *ppThis = pThis; + return NV_OK; __nvoc_objCreate_RsSession_cleanup: // do not call destructors here since the constructor already called them - portMemFree(pThis); + if (createFlags & NVOC_OBJ_CREATE_FLAGS_IN_PLACE_CONSTRUCT) + portMemSet(pThis, 0, sizeof(RsSession)); + else + portMemFree(pThis); + + // coverity[leaked_storage:FALSE] return status; } diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/generated/g_rs_server_nvoc.h nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_rs_server_nvoc.h --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/generated/g_rs_server_nvoc.h 2023-10-25 20:27:19.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_rs_server_nvoc.h 2024-03-05 22:18:44.000000000 +0000 @@ -36,6 +36,7 @@ #include "nvport/nvport.h" #include "resserv/resserv.h" +#include "resserv/rs_client.h" #include "nvoc/runtime.h" #ifdef __cplusplus @@ -135,8 +136,8 @@ struct Object *__nvoc_pbase_Object; struct RsShared *__nvoc_pbase_RsShared; struct RsSession *__nvoc_pbase_RsSession; - void (*__sessionRemoveDependant__)(struct RsSession *, RsResourceRef *); - void (*__sessionRemoveDependency__)(struct RsSession *, RsResourceRef *); + void (*__sessionRemoveDependant__)(struct RsSession *, struct RsResourceRef *); + void (*__sessionRemoveDependency__)(struct RsSession *, struct RsResourceRef *); PORT_RWLOCK *pLock; NvBool bValid; RsResourceRefList dependencies; @@ -173,15 +174,15 @@ #define sessionRemoveDependant(pSession, pResourceRef) sessionRemoveDependant_DISPATCH(pSession, pResourceRef) #define sessionRemoveDependency(pSession, pResourceRef) sessionRemoveDependency_DISPATCH(pSession, pResourceRef) -void sessionRemoveDependant_IMPL(struct RsSession *pSession, RsResourceRef *pResourceRef); +void sessionRemoveDependant_IMPL(struct RsSession *pSession, struct RsResourceRef *pResourceRef); -static inline void sessionRemoveDependant_DISPATCH(struct RsSession *pSession, RsResourceRef *pResourceRef) { +static inline void sessionRemoveDependant_DISPATCH(struct RsSession *pSession, struct RsResourceRef *pResourceRef) { pSession->__sessionRemoveDependant__(pSession, pResourceRef); } -void sessionRemoveDependency_IMPL(struct RsSession *pSession, RsResourceRef *pResourceRef); +void sessionRemoveDependency_IMPL(struct RsSession *pSession, struct RsResourceRef *pResourceRef); -static inline void sessionRemoveDependency_DISPATCH(struct RsSession *pSession, RsResourceRef *pResourceRef) { +static inline void sessionRemoveDependency_DISPATCH(struct RsSession *pSession, struct RsResourceRef *pResourceRef) { pSession->__sessionRemoveDependency__(pSession, pResourceRef); } @@ -191,10 +192,10 @@ void sessionDestruct_IMPL(struct RsSession *pSession); #define __nvoc_sessionDestruct(pSession) sessionDestruct_IMPL(pSession) -NV_STATUS sessionAddDependant_IMPL(struct RsSession *pSession, RsResourceRef *pResourceRef); +NV_STATUS sessionAddDependant_IMPL(struct RsSession *pSession, struct RsResourceRef *pResourceRef); #ifdef __nvoc_rs_server_h_disabled -static inline NV_STATUS sessionAddDependant(struct RsSession *pSession, RsResourceRef *pResourceRef) { +static inline NV_STATUS sessionAddDependant(struct RsSession *pSession, struct RsResourceRef *pResourceRef) { NV_ASSERT_FAILED_PRECOMP("RsSession was disabled!"); return NV_ERR_NOT_SUPPORTED; } @@ -202,10 +203,10 @@ #define sessionAddDependant(pSession, pResourceRef) sessionAddDependant_IMPL(pSession, pResourceRef) #endif //__nvoc_rs_server_h_disabled -NV_STATUS sessionAddDependency_IMPL(struct RsSession *pSession, RsResourceRef *pResourceRef); +NV_STATUS sessionAddDependency_IMPL(struct RsSession *pSession, struct RsResourceRef *pResourceRef); #ifdef __nvoc_rs_server_h_disabled -static inline NV_STATUS sessionAddDependency(struct RsSession *pSession, RsResourceRef *pResourceRef) { +static inline NV_STATUS sessionAddDependency(struct RsSession *pSession, struct RsResourceRef *pResourceRef) { NV_ASSERT_FAILED_PRECOMP("RsSession was disabled!"); return NV_ERR_NOT_SUPPORTED; } @@ -213,10 +214,10 @@ #define sessionAddDependency(pSession, pResourceRef) sessionAddDependency_IMPL(pSession, pResourceRef) #endif //__nvoc_rs_server_h_disabled -NV_STATUS sessionCheckLocksForAdd_IMPL(struct RsSession *pSession, RsResourceRef *pResourceRef); +NV_STATUS sessionCheckLocksForAdd_IMPL(struct RsSession *pSession, struct RsResourceRef *pResourceRef); #ifdef __nvoc_rs_server_h_disabled -static inline NV_STATUS sessionCheckLocksForAdd(struct RsSession *pSession, RsResourceRef *pResourceRef) { +static inline NV_STATUS sessionCheckLocksForAdd(struct RsSession *pSession, struct RsResourceRef *pResourceRef) { NV_ASSERT_FAILED_PRECOMP("RsSession was disabled!"); return NV_ERR_NOT_SUPPORTED; } @@ -224,10 +225,10 @@ #define sessionCheckLocksForAdd(pSession, pResourceRef) sessionCheckLocksForAdd_IMPL(pSession, pResourceRef) #endif //__nvoc_rs_server_h_disabled -void sessionCheckLocksForRemove_IMPL(struct RsSession *pSession, RsResourceRef *pResourceRef); +void sessionCheckLocksForRemove_IMPL(struct RsSession *pSession, struct RsResourceRef *pResourceRef); #ifdef __nvoc_rs_server_h_disabled -static inline void sessionCheckLocksForRemove(struct RsSession *pSession, RsResourceRef *pResourceRef) { +static inline void sessionCheckLocksForRemove(struct RsSession *pSession, struct RsResourceRef *pResourceRef) { NV_ASSERT_FAILED_PRECOMP("RsSession was disabled!"); } #else //__nvoc_rs_server_h_disabled @@ -318,6 +319,11 @@ NvU32 activeClientCount; NvU64 activeResourceCount; + + /// List of clients that are de-activated and pending free + RsDisabledClientList disabledClientList; + struct RsClient *pNextDisabledClient; + PORT_SPINLOCK *pDisabledClientListLock; }; /** @@ -399,20 +405,35 @@ NV_STATUS serverFreeClient(RsServer *pServer, RS_CLIENT_FREE_PARAMS* pParams); /** - * Free a list of client handles. All resources references owned by the client will be - * freed. All priority resources will be freed first across all listed clients. + * Mark a list of client handles as disabled. All CPU mappings owned by that + * client will be unmapped immediate, and the client will be marked as disabled. + * A call to @ref serverFreeDisabledClients will then free all such clients. * * It is invalid to attempt to free a client from a user other than the one * that allocated it. * * @param[in] pServer This server instance - * @param[in] phClientList The list of client handles to free + * @param[in] phClientList The list of client handles to disable * @param[in] numClients The number of clients in the list * @param[in] freeState User-defined free state * @param[in] pSecInfo Security Info * */ -NV_STATUS serverFreeClientList(RsServer *pServer, NvHandle *phClientList, NvU32 numClients, NvU32 freeState, API_SECURITY_INFO *pSecInfo); +NV_STATUS serverMarkClientListDisabled(RsServer *pServer, NvHandle *phClientList, NvU32 numClients, NvU32 freeState, API_SECURITY_INFO *pSecInfo); + +/** + * Frees all currently disabled clients. All resources references owned by + * any of the clients will be freed. + * All priority resources will be freed first across all listed clients. + * + * NOTE: may return NV_WARN_MORE_PROCESSING_REQUIRED if not all clients were freed + * + * @param[in] pServer This server instance + * @param[in] freeState User-defined free state + * @param[in] limit Max number of iterations to make returning; 0 means no limit + * + */ +NV_STATUS serverFreeDisabledClients(RsServer *pServer, NvU32 freeState, NvU32 limit); /** * Allocate a resource. @@ -488,8 +509,111 @@ * @param[in] pServer * @param[in] clientHandleBase */ - NV_STATUS serverSetClientHandleBase(RsServer *pServer, NvU32 clientHandleBase); +NV_STATUS serverSetClientHandleBase(RsServer *pServer, NvU32 clientHandleBase); + +/** + * Deserialize parameters for servicing command + * + * @param[in] pCallContext + * @param[in] cmd + * @param[in/out] ppParams + * @param[in/out] pParamsSize + * @param[in] flags + */ +NV_STATUS serverDeserializeCtrlDown(CALL_CONTEXT *pCallContext, NvU32 cmd, void **ppParams, NvU32 *pParamsSize, NvU32 *flags); + +/** + * Serialize parameters for servicing command + * + * @param[in] pCallContext + * @param[in] cmd + * @param[in/out] ppParams + * @param[in/out] pParamsSize + * @param[in] flags + */ +NV_STATUS serverSerializeCtrlDown(CALL_CONTEXT *pCallContext, NvU32 cmd, void **ppParams, NvU32 *pParamsSize, NvU32 *flags); + +/** + * Deserialize parameters for returning from command + * + * @param[in] pCallContext + * @param[in] cmd + * @param[out] ppParams + * @param[out] pParamsSize + * @param[in] flags + */ +NV_STATUS serverDeserializeCtrlUp(CALL_CONTEXT *pCallContext, NvU32 cmd, void **ppParams, NvU32 *pParamsSize, NvU32 *flags); + +/** + * Serialize parameters for returning from command + * + * @param[in] pCallContext + * @param[in] cmd + * @param[out] ppParams + * @param[out] pParamsSize + * @param[in] flags + */ +NV_STATUS serverSerializeCtrlUp(CALL_CONTEXT *pCallContext, NvU32 cmd, void **ppParams, NvU32 *pParamsSize, NvU32 *flags); +/** + * Unset flag for reserializing control before going to GSP + * Used if kernel control servicing passes params to GSP without changing them + * + * @param[in] pCallContext + */ +void serverDisableReserializeControl(CALL_CONTEXT *pCallContext); + +/** + * Serialize parameters for allocating + * + * @param[in] pCallContext + * @param[in] classId + * @param[in/out] ppParams + * @param[out] pParamsSize + * @param[in] flags + */ +NV_STATUS serverSerializeAllocDown(CALL_CONTEXT *pCallContext, NvU32 classId, void **ppParams, NvU32 *pParamsSize, NvU32 *flags); + +/** + * Deserialize parameters for allocating + * + * @param[in] pCallContext + * @param[in] classId + * @param[in/out] ppParams + * @param[in/out] pParamsSize + * @param[in] flags + */ +NV_STATUS serverDeserializeAllocDown(CALL_CONTEXT *pCallContext, NvU32 classId, void **ppParams, NvU32 *pParamsSize, NvU32 *flags); + +/** + * Serialize parameters for returning from allocating + * + * @param[in] pCallContext + * @param[in] classId + * @param[out] ppParams + * @param[out] pParamsSize + * @param[in] flags + */ +NV_STATUS serverSerializeAllocUp(CALL_CONTEXT *pCallContext, NvU32 classId, void **ppParams, NvU32 *pParamsSize, NvU32 *flags); + +/** + * Deserialize parameters for returning from allocating + * + * @param[in] pCallContext + * @param[in] classId + * @param[out] ppParams + * @param[out] pParamsSize + * @param[in] flags + */ +NV_STATUS serverDeserializeAllocUp(CALL_CONTEXT *pCallContext, NvU32 classId, void **ppParams, NvU32 *pParamsSize, NvU32 *flags); + +/** + * Free finn structures allocated for serializing/deserializing + * + * @param[in] pCallContext + * @param[in] pParams + */ +void serverFreeSerializeStructures(CALL_CONTEXT *pCallContext, void *pParams); /** * Return an available client handle for new client allocation diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/generated/g_sdk-structures.h nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_sdk-structures.h --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/generated/g_sdk-structures.h 2023-10-25 20:23:07.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_sdk-structures.h 2024-03-05 22:15:58.000000000 +0000 @@ -464,6 +464,17 @@ typedef NV2080_CTRL_CE_GET_ALL_CAPS_PARAMS_v21_0A NV2080_CTRL_CE_GET_ALL_CAPS_PARAMS_v; +typedef struct NV2080_CTRL_CMD_BUS_GET_C2C_INFO_PARAMS_v22_01 +{ + NvBool bIsLinkUp; + NvU32 nrLinks; + NvU32 linkMask; + NvU32 perLinkBwMBps; + NvU32 remoteType; +} NV2080_CTRL_CMD_BUS_GET_C2C_INFO_PARAMS_v22_01; + +typedef NV2080_CTRL_CMD_BUS_GET_C2C_INFO_PARAMS_v22_01 NV2080_CTRL_CMD_BUS_GET_C2C_INFO_PARAMS_v; + typedef struct NV2080_CTRL_INTERNAL_PFM_REQ_HNDLR_STATE_SYNC_DATA_SMBPBI_v21_04 { NvU32 sensorId; diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/generated/g_sec2_context_nvoc.c nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_sec2_context_nvoc.c --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/generated/g_sec2_context_nvoc.c 1970-01-01 00:00:00.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_sec2_context_nvoc.c 2024-03-05 22:18:44.000000000 +0000 @@ -0,0 +1,442 @@ +#define NVOC_SEC2_CONTEXT_H_PRIVATE_ACCESS_ALLOWED +#include "nvoc/runtime.h" +#include "nvoc/rtti.h" +#include "nvtypes.h" +#include "nvport/nvport.h" +#include "nvport/inline/util_valist.h" +#include "utils/nvassert.h" +#include "g_sec2_context_nvoc.h" + +#ifdef DEBUG +char __nvoc_class_id_uniqueness_check_0x4c3439 = 1; +#endif + +extern const struct NVOC_CLASS_DEF __nvoc_class_def_Sec2Context; + +extern const struct NVOC_CLASS_DEF __nvoc_class_def_Object; + +extern const struct NVOC_CLASS_DEF __nvoc_class_def_RsResource; + +extern const struct NVOC_CLASS_DEF __nvoc_class_def_RmResourceCommon; + +extern const struct NVOC_CLASS_DEF __nvoc_class_def_RmResource; + +extern const struct NVOC_CLASS_DEF __nvoc_class_def_GpuResource; + +extern const struct NVOC_CLASS_DEF __nvoc_class_def_INotifier; + +extern const struct NVOC_CLASS_DEF __nvoc_class_def_Notifier; + +extern const struct NVOC_CLASS_DEF __nvoc_class_def_ChannelDescendant; + +void __nvoc_init_Sec2Context(Sec2Context*, RmHalspecOwner* ); +void __nvoc_init_funcTable_Sec2Context(Sec2Context*, RmHalspecOwner* ); +NV_STATUS __nvoc_ctor_Sec2Context(Sec2Context*, RmHalspecOwner* , struct CALL_CONTEXT * arg_pCallContext, struct RS_RES_ALLOC_PARAMS_INTERNAL * arg_pParams); +void __nvoc_init_dataField_Sec2Context(Sec2Context*, RmHalspecOwner* ); +void __nvoc_dtor_Sec2Context(Sec2Context*); +extern const struct NVOC_EXPORT_INFO __nvoc_export_info_Sec2Context; + +static const struct NVOC_RTTI __nvoc_rtti_Sec2Context_Sec2Context = { + /*pClassDef=*/ &__nvoc_class_def_Sec2Context, + /*dtor=*/ (NVOC_DYNAMIC_DTOR) &__nvoc_dtor_Sec2Context, + /*offset=*/ 0, +}; + +static const struct NVOC_RTTI __nvoc_rtti_Sec2Context_Object = { + /*pClassDef=*/ &__nvoc_class_def_Object, + /*dtor=*/ &__nvoc_destructFromBase, + /*offset=*/ NV_OFFSETOF(Sec2Context, __nvoc_base_ChannelDescendant.__nvoc_base_GpuResource.__nvoc_base_RmResource.__nvoc_base_RsResource.__nvoc_base_Object), +}; + +static const struct NVOC_RTTI __nvoc_rtti_Sec2Context_RsResource = { + /*pClassDef=*/ &__nvoc_class_def_RsResource, + /*dtor=*/ &__nvoc_destructFromBase, + /*offset=*/ NV_OFFSETOF(Sec2Context, __nvoc_base_ChannelDescendant.__nvoc_base_GpuResource.__nvoc_base_RmResource.__nvoc_base_RsResource), +}; + +static const struct NVOC_RTTI __nvoc_rtti_Sec2Context_RmResourceCommon = { + /*pClassDef=*/ &__nvoc_class_def_RmResourceCommon, + /*dtor=*/ &__nvoc_destructFromBase, + /*offset=*/ NV_OFFSETOF(Sec2Context, __nvoc_base_ChannelDescendant.__nvoc_base_GpuResource.__nvoc_base_RmResource.__nvoc_base_RmResourceCommon), +}; + +static const struct NVOC_RTTI __nvoc_rtti_Sec2Context_RmResource = { + /*pClassDef=*/ &__nvoc_class_def_RmResource, + /*dtor=*/ &__nvoc_destructFromBase, + /*offset=*/ NV_OFFSETOF(Sec2Context, __nvoc_base_ChannelDescendant.__nvoc_base_GpuResource.__nvoc_base_RmResource), +}; + +static const struct NVOC_RTTI __nvoc_rtti_Sec2Context_GpuResource = { + /*pClassDef=*/ &__nvoc_class_def_GpuResource, + /*dtor=*/ &__nvoc_destructFromBase, + /*offset=*/ NV_OFFSETOF(Sec2Context, __nvoc_base_ChannelDescendant.__nvoc_base_GpuResource), +}; + +static const struct NVOC_RTTI __nvoc_rtti_Sec2Context_INotifier = { + /*pClassDef=*/ &__nvoc_class_def_INotifier, + /*dtor=*/ &__nvoc_destructFromBase, + /*offset=*/ NV_OFFSETOF(Sec2Context, __nvoc_base_ChannelDescendant.__nvoc_base_Notifier.__nvoc_base_INotifier), +}; + +static const struct NVOC_RTTI __nvoc_rtti_Sec2Context_Notifier = { + /*pClassDef=*/ &__nvoc_class_def_Notifier, + /*dtor=*/ &__nvoc_destructFromBase, + /*offset=*/ NV_OFFSETOF(Sec2Context, __nvoc_base_ChannelDescendant.__nvoc_base_Notifier), +}; + +static const struct NVOC_RTTI __nvoc_rtti_Sec2Context_ChannelDescendant = { + /*pClassDef=*/ &__nvoc_class_def_ChannelDescendant, + /*dtor=*/ &__nvoc_destructFromBase, + /*offset=*/ NV_OFFSETOF(Sec2Context, __nvoc_base_ChannelDescendant), +}; + +static const struct NVOC_CASTINFO __nvoc_castinfo_Sec2Context = { + /*numRelatives=*/ 9, + /*relatives=*/ { + &__nvoc_rtti_Sec2Context_Sec2Context, + &__nvoc_rtti_Sec2Context_ChannelDescendant, + &__nvoc_rtti_Sec2Context_Notifier, + &__nvoc_rtti_Sec2Context_INotifier, + &__nvoc_rtti_Sec2Context_GpuResource, + &__nvoc_rtti_Sec2Context_RmResource, + &__nvoc_rtti_Sec2Context_RmResourceCommon, + &__nvoc_rtti_Sec2Context_RsResource, + &__nvoc_rtti_Sec2Context_Object, + }, +}; + +const struct NVOC_CLASS_DEF __nvoc_class_def_Sec2Context = +{ + /*classInfo=*/ { + /*size=*/ sizeof(Sec2Context), + /*classId=*/ classId(Sec2Context), + /*providerId=*/ &__nvoc_rtti_provider, +#if NV_PRINTF_STRINGS_ALLOWED + /*name=*/ "Sec2Context", +#endif + }, + /*objCreatefn=*/ (NVOC_DYNAMIC_OBJ_CREATE) &__nvoc_objCreateDynamic_Sec2Context, + /*pCastInfo=*/ &__nvoc_castinfo_Sec2Context, + /*pExportInfo=*/ &__nvoc_export_info_Sec2Context +}; + +static NV_STATUS __nvoc_thunk_ChannelDescendant_sec2ctxCheckMemInterUnmap(struct Sec2Context *pChannelDescendant, NvBool bSubdeviceHandleProvided) { + return chandesCheckMemInterUnmap((struct ChannelDescendant *)(((unsigned char *)pChannelDescendant) + __nvoc_rtti_Sec2Context_ChannelDescendant.offset), bSubdeviceHandleProvided); +} + +static NvBool __nvoc_thunk_GpuResource_sec2ctxShareCallback(struct Sec2Context *pGpuResource, struct RsClient *pInvokingClient, struct RsResourceRef *pParentRef, RS_SHARE_POLICY *pSharePolicy) { + return gpuresShareCallback((struct GpuResource *)(((unsigned char *)pGpuResource) + __nvoc_rtti_Sec2Context_GpuResource.offset), pInvokingClient, pParentRef, pSharePolicy); +} + +static NvBool __nvoc_thunk_RmResource_sec2ctxAccessCallback(struct Sec2Context *pResource, struct RsClient *pInvokingClient, void *pAllocParams, RsAccessRight accessRight) { + return rmresAccessCallback((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_Sec2Context_RmResource.offset), pInvokingClient, pAllocParams, accessRight); +} + +static NV_STATUS __nvoc_thunk_RsResource_sec2ctxMapTo(struct Sec2Context *pResource, RS_RES_MAP_TO_PARAMS *pParams) { + return resMapTo((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_Sec2Context_RsResource.offset), pParams); +} + +static NV_STATUS __nvoc_thunk_GpuResource_sec2ctxGetMapAddrSpace(struct Sec2Context *pGpuResource, struct CALL_CONTEXT *pCallContext, NvU32 mapFlags, NV_ADDRESS_SPACE *pAddrSpace) { + return gpuresGetMapAddrSpace((struct GpuResource *)(((unsigned char *)pGpuResource) + __nvoc_rtti_Sec2Context_GpuResource.offset), pCallContext, mapFlags, pAddrSpace); +} + +static void __nvoc_thunk_Notifier_sec2ctxSetNotificationShare(struct Sec2Context *pNotifier, struct NotifShare *pNotifShare) { + notifySetNotificationShare((struct Notifier *)(((unsigned char *)pNotifier) + __nvoc_rtti_Sec2Context_Notifier.offset), pNotifShare); +} + +static NvU32 __nvoc_thunk_RsResource_sec2ctxGetRefCount(struct Sec2Context *pResource) { + return resGetRefCount((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_Sec2Context_RsResource.offset)); +} + +static void __nvoc_thunk_RsResource_sec2ctxAddAdditionalDependants(struct RsClient *pClient, struct Sec2Context *pResource, RsResourceRef *pReference) { + resAddAdditionalDependants(pClient, (struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_Sec2Context_RsResource.offset), pReference); +} + +static NV_STATUS __nvoc_thunk_RmResource_sec2ctxControl_Prologue(struct Sec2Context *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return rmresControl_Prologue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_Sec2Context_RmResource.offset), pCallContext, pParams); +} + +static NV_STATUS __nvoc_thunk_GpuResource_sec2ctxGetRegBaseOffsetAndSize(struct Sec2Context *pGpuResource, struct OBJGPU *pGpu, NvU32 *pOffset, NvU32 *pSize) { + return gpuresGetRegBaseOffsetAndSize((struct GpuResource *)(((unsigned char *)pGpuResource) + __nvoc_rtti_Sec2Context_GpuResource.offset), pGpu, pOffset, pSize); +} + +static NV_STATUS __nvoc_thunk_GpuResource_sec2ctxInternalControlForward(struct Sec2Context *pGpuResource, NvU32 command, void *pParams, NvU32 size) { + return gpuresInternalControlForward((struct GpuResource *)(((unsigned char *)pGpuResource) + __nvoc_rtti_Sec2Context_GpuResource.offset), command, pParams, size); +} + +static NV_STATUS __nvoc_thunk_RsResource_sec2ctxUnmapFrom(struct Sec2Context *pResource, RS_RES_UNMAP_FROM_PARAMS *pParams) { + return resUnmapFrom((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_Sec2Context_RsResource.offset), pParams); +} + +static void __nvoc_thunk_RmResource_sec2ctxControl_Epilogue(struct Sec2Context *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + rmresControl_Epilogue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_Sec2Context_RmResource.offset), pCallContext, pParams); +} + +static NV_STATUS __nvoc_thunk_RsResource_sec2ctxControlLookup(struct Sec2Context *pResource, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams, const struct NVOC_EXPORTED_METHOD_DEF **ppEntry) { + return resControlLookup((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_Sec2Context_RsResource.offset), pParams, ppEntry); +} + +static NV_STATUS __nvoc_thunk_ChannelDescendant_sec2ctxGetSwMethods(struct Sec2Context *pChannelDescendant, const METHOD **ppMethods, NvU32 *pNumMethods) { + return chandesGetSwMethods((struct ChannelDescendant *)(((unsigned char *)pChannelDescendant) + __nvoc_rtti_Sec2Context_ChannelDescendant.offset), ppMethods, pNumMethods); +} + +static NvHandle __nvoc_thunk_GpuResource_sec2ctxGetInternalObjectHandle(struct Sec2Context *pGpuResource) { + return gpuresGetInternalObjectHandle((struct GpuResource *)(((unsigned char *)pGpuResource) + __nvoc_rtti_Sec2Context_GpuResource.offset)); +} + +static NV_STATUS __nvoc_thunk_GpuResource_sec2ctxControl(struct Sec2Context *pGpuResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return gpuresControl((struct GpuResource *)(((unsigned char *)pGpuResource) + __nvoc_rtti_Sec2Context_GpuResource.offset), pCallContext, pParams); +} + +static NV_STATUS __nvoc_thunk_GpuResource_sec2ctxUnmap(struct Sec2Context *pGpuResource, struct CALL_CONTEXT *pCallContext, struct RsCpuMapping *pCpuMapping) { + return gpuresUnmap((struct GpuResource *)(((unsigned char *)pGpuResource) + __nvoc_rtti_Sec2Context_GpuResource.offset), pCallContext, pCpuMapping); +} + +static NV_STATUS __nvoc_thunk_RmResource_sec2ctxGetMemInterMapParams(struct Sec2Context *pRmResource, RMRES_MEM_INTER_MAP_PARAMS *pParams) { + return rmresGetMemInterMapParams((struct RmResource *)(((unsigned char *)pRmResource) + __nvoc_rtti_Sec2Context_RmResource.offset), pParams); +} + +static NV_STATUS __nvoc_thunk_RmResource_sec2ctxGetMemoryMappingDescriptor(struct Sec2Context *pRmResource, struct MEMORY_DESCRIPTOR **ppMemDesc) { + return rmresGetMemoryMappingDescriptor((struct RmResource *)(((unsigned char *)pRmResource) + __nvoc_rtti_Sec2Context_RmResource.offset), ppMemDesc); +} + +static NvBool __nvoc_thunk_ChannelDescendant_sec2ctxIsSwMethodStalling(struct Sec2Context *pChannelDescendant, NvU32 hHandle) { + return chandesIsSwMethodStalling((struct ChannelDescendant *)(((unsigned char *)pChannelDescendant) + __nvoc_rtti_Sec2Context_ChannelDescendant.offset), hHandle); +} + +static NV_STATUS __nvoc_thunk_RsResource_sec2ctxControlFilter(struct Sec2Context *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return resControlFilter((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_Sec2Context_RsResource.offset), pCallContext, pParams); +} + +static NV_STATUS __nvoc_thunk_Notifier_sec2ctxUnregisterEvent(struct Sec2Context *pNotifier, NvHandle hNotifierClient, NvHandle hNotifierResource, NvHandle hEventClient, NvHandle hEvent) { + return notifyUnregisterEvent((struct Notifier *)(((unsigned char *)pNotifier) + __nvoc_rtti_Sec2Context_Notifier.offset), hNotifierClient, hNotifierResource, hEventClient, hEvent); +} + +static NV_STATUS __nvoc_thunk_RmResource_sec2ctxControlSerialization_Prologue(struct Sec2Context *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return rmresControlSerialization_Prologue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_Sec2Context_RmResource.offset), pCallContext, pParams); +} + +static NvBool __nvoc_thunk_RsResource_sec2ctxCanCopy(struct Sec2Context *pResource) { + return resCanCopy((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_Sec2Context_RsResource.offset)); +} + +static void __nvoc_thunk_RsResource_sec2ctxPreDestruct(struct Sec2Context *pResource) { + resPreDestruct((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_Sec2Context_RsResource.offset)); +} + +static NV_STATUS __nvoc_thunk_RsResource_sec2ctxIsDuplicate(struct Sec2Context *pResource, NvHandle hMemory, NvBool *pDuplicate) { + return resIsDuplicate((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_Sec2Context_RsResource.offset), hMemory, pDuplicate); +} + +static void __nvoc_thunk_RmResource_sec2ctxControlSerialization_Epilogue(struct Sec2Context *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + rmresControlSerialization_Epilogue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_Sec2Context_RmResource.offset), pCallContext, pParams); +} + +static PEVENTNOTIFICATION *__nvoc_thunk_Notifier_sec2ctxGetNotificationListPtr(struct Sec2Context *pNotifier) { + return notifyGetNotificationListPtr((struct Notifier *)(((unsigned char *)pNotifier) + __nvoc_rtti_Sec2Context_Notifier.offset)); +} + +static struct NotifShare *__nvoc_thunk_Notifier_sec2ctxGetNotificationShare(struct Sec2Context *pNotifier) { + return notifyGetNotificationShare((struct Notifier *)(((unsigned char *)pNotifier) + __nvoc_rtti_Sec2Context_Notifier.offset)); +} + +static NV_STATUS __nvoc_thunk_GpuResource_sec2ctxMap(struct Sec2Context *pGpuResource, struct CALL_CONTEXT *pCallContext, struct RS_CPU_MAP_PARAMS *pParams, struct RsCpuMapping *pCpuMapping) { + return gpuresMap((struct GpuResource *)(((unsigned char *)pGpuResource) + __nvoc_rtti_Sec2Context_GpuResource.offset), pCallContext, pParams, pCpuMapping); +} + +static NV_STATUS __nvoc_thunk_Notifier_sec2ctxGetOrAllocNotifShare(struct Sec2Context *pNotifier, NvHandle hNotifierClient, NvHandle hNotifierResource, struct NotifShare **ppNotifShare) { + return notifyGetOrAllocNotifShare((struct Notifier *)(((unsigned char *)pNotifier) + __nvoc_rtti_Sec2Context_Notifier.offset), hNotifierClient, hNotifierResource, ppNotifShare); +} + +const struct NVOC_EXPORT_INFO __nvoc_export_info_Sec2Context = +{ + /*numEntries=*/ 0, + /*pExportEntries=*/ 0 +}; + +void __nvoc_dtor_ChannelDescendant(ChannelDescendant*); +void __nvoc_dtor_Sec2Context(Sec2Context *pThis) { + __nvoc_sec2ctxDestruct(pThis); + __nvoc_dtor_ChannelDescendant(&pThis->__nvoc_base_ChannelDescendant); + PORT_UNREFERENCED_VARIABLE(pThis); +} + +void __nvoc_init_dataField_Sec2Context(Sec2Context *pThis, RmHalspecOwner *pRmhalspecowner) { + RmVariantHal *rmVariantHal = &pRmhalspecowner->rmVariantHal; + const unsigned long rmVariantHal_HalVarIdx = (unsigned long)rmVariantHal->__nvoc_HalVarIdx; + PORT_UNREFERENCED_VARIABLE(pThis); + PORT_UNREFERENCED_VARIABLE(pRmhalspecowner); + PORT_UNREFERENCED_VARIABLE(rmVariantHal); + PORT_UNREFERENCED_VARIABLE(rmVariantHal_HalVarIdx); +} + +NV_STATUS __nvoc_ctor_ChannelDescendant(ChannelDescendant* , RmHalspecOwner* , struct CALL_CONTEXT *, struct RS_RES_ALLOC_PARAMS_INTERNAL *, PARAM_TO_ENGDESC_FUNCTION *); +NV_STATUS __nvoc_ctor_Sec2Context(Sec2Context *pThis, RmHalspecOwner *pRmhalspecowner, struct CALL_CONTEXT * arg_pCallContext, struct RS_RES_ALLOC_PARAMS_INTERNAL * arg_pParams) { + NV_STATUS status = NV_OK; + status = __nvoc_ctor_ChannelDescendant(&pThis->__nvoc_base_ChannelDescendant, pRmhalspecowner, arg_pCallContext, arg_pParams, ((void *)0)); + if (status != NV_OK) goto __nvoc_ctor_Sec2Context_fail_ChannelDescendant; + __nvoc_init_dataField_Sec2Context(pThis, pRmhalspecowner); + + status = __nvoc_sec2ctxConstruct(pThis, arg_pCallContext, arg_pParams); + if (status != NV_OK) goto __nvoc_ctor_Sec2Context_fail__init; + goto __nvoc_ctor_Sec2Context_exit; // Success + +__nvoc_ctor_Sec2Context_fail__init: + __nvoc_dtor_ChannelDescendant(&pThis->__nvoc_base_ChannelDescendant); +__nvoc_ctor_Sec2Context_fail_ChannelDescendant: +__nvoc_ctor_Sec2Context_exit: + + return status; +} + +static void __nvoc_init_funcTable_Sec2Context_1(Sec2Context *pThis, RmHalspecOwner *pRmhalspecowner) { + RmVariantHal *rmVariantHal = &pRmhalspecowner->rmVariantHal; + const unsigned long rmVariantHal_HalVarIdx = (unsigned long)rmVariantHal->__nvoc_HalVarIdx; + PORT_UNREFERENCED_VARIABLE(pThis); + PORT_UNREFERENCED_VARIABLE(pRmhalspecowner); + PORT_UNREFERENCED_VARIABLE(rmVariantHal); + PORT_UNREFERENCED_VARIABLE(rmVariantHal_HalVarIdx); + + pThis->__sec2ctxCheckMemInterUnmap__ = &__nvoc_thunk_ChannelDescendant_sec2ctxCheckMemInterUnmap; + + pThis->__sec2ctxShareCallback__ = &__nvoc_thunk_GpuResource_sec2ctxShareCallback; + + pThis->__sec2ctxAccessCallback__ = &__nvoc_thunk_RmResource_sec2ctxAccessCallback; + + pThis->__sec2ctxMapTo__ = &__nvoc_thunk_RsResource_sec2ctxMapTo; + + pThis->__sec2ctxGetMapAddrSpace__ = &__nvoc_thunk_GpuResource_sec2ctxGetMapAddrSpace; + + pThis->__sec2ctxSetNotificationShare__ = &__nvoc_thunk_Notifier_sec2ctxSetNotificationShare; + + pThis->__sec2ctxGetRefCount__ = &__nvoc_thunk_RsResource_sec2ctxGetRefCount; + + pThis->__sec2ctxAddAdditionalDependants__ = &__nvoc_thunk_RsResource_sec2ctxAddAdditionalDependants; + + pThis->__sec2ctxControl_Prologue__ = &__nvoc_thunk_RmResource_sec2ctxControl_Prologue; + + pThis->__sec2ctxGetRegBaseOffsetAndSize__ = &__nvoc_thunk_GpuResource_sec2ctxGetRegBaseOffsetAndSize; + + pThis->__sec2ctxInternalControlForward__ = &__nvoc_thunk_GpuResource_sec2ctxInternalControlForward; + + pThis->__sec2ctxUnmapFrom__ = &__nvoc_thunk_RsResource_sec2ctxUnmapFrom; + + pThis->__sec2ctxControl_Epilogue__ = &__nvoc_thunk_RmResource_sec2ctxControl_Epilogue; + + pThis->__sec2ctxControlLookup__ = &__nvoc_thunk_RsResource_sec2ctxControlLookup; + + pThis->__sec2ctxGetSwMethods__ = &__nvoc_thunk_ChannelDescendant_sec2ctxGetSwMethods; + + pThis->__sec2ctxGetInternalObjectHandle__ = &__nvoc_thunk_GpuResource_sec2ctxGetInternalObjectHandle; + + pThis->__sec2ctxControl__ = &__nvoc_thunk_GpuResource_sec2ctxControl; + + pThis->__sec2ctxUnmap__ = &__nvoc_thunk_GpuResource_sec2ctxUnmap; + + pThis->__sec2ctxGetMemInterMapParams__ = &__nvoc_thunk_RmResource_sec2ctxGetMemInterMapParams; + + pThis->__sec2ctxGetMemoryMappingDescriptor__ = &__nvoc_thunk_RmResource_sec2ctxGetMemoryMappingDescriptor; + + pThis->__sec2ctxIsSwMethodStalling__ = &__nvoc_thunk_ChannelDescendant_sec2ctxIsSwMethodStalling; + + pThis->__sec2ctxControlFilter__ = &__nvoc_thunk_RsResource_sec2ctxControlFilter; + + pThis->__sec2ctxUnregisterEvent__ = &__nvoc_thunk_Notifier_sec2ctxUnregisterEvent; + + pThis->__sec2ctxControlSerialization_Prologue__ = &__nvoc_thunk_RmResource_sec2ctxControlSerialization_Prologue; + + pThis->__sec2ctxCanCopy__ = &__nvoc_thunk_RsResource_sec2ctxCanCopy; + + pThis->__sec2ctxPreDestruct__ = &__nvoc_thunk_RsResource_sec2ctxPreDestruct; + + pThis->__sec2ctxIsDuplicate__ = &__nvoc_thunk_RsResource_sec2ctxIsDuplicate; + + pThis->__sec2ctxControlSerialization_Epilogue__ = &__nvoc_thunk_RmResource_sec2ctxControlSerialization_Epilogue; + + pThis->__sec2ctxGetNotificationListPtr__ = &__nvoc_thunk_Notifier_sec2ctxGetNotificationListPtr; + + pThis->__sec2ctxGetNotificationShare__ = &__nvoc_thunk_Notifier_sec2ctxGetNotificationShare; + + pThis->__sec2ctxMap__ = &__nvoc_thunk_GpuResource_sec2ctxMap; + + pThis->__sec2ctxGetOrAllocNotifShare__ = &__nvoc_thunk_Notifier_sec2ctxGetOrAllocNotifShare; +} + +void __nvoc_init_funcTable_Sec2Context(Sec2Context *pThis, RmHalspecOwner *pRmhalspecowner) { + __nvoc_init_funcTable_Sec2Context_1(pThis, pRmhalspecowner); +} + +void __nvoc_init_ChannelDescendant(ChannelDescendant*, RmHalspecOwner* ); +void __nvoc_init_Sec2Context(Sec2Context *pThis, RmHalspecOwner *pRmhalspecowner) { + pThis->__nvoc_pbase_Sec2Context = pThis; + pThis->__nvoc_pbase_Object = &pThis->__nvoc_base_ChannelDescendant.__nvoc_base_GpuResource.__nvoc_base_RmResource.__nvoc_base_RsResource.__nvoc_base_Object; + pThis->__nvoc_pbase_RsResource = &pThis->__nvoc_base_ChannelDescendant.__nvoc_base_GpuResource.__nvoc_base_RmResource.__nvoc_base_RsResource; + pThis->__nvoc_pbase_RmResourceCommon = &pThis->__nvoc_base_ChannelDescendant.__nvoc_base_GpuResource.__nvoc_base_RmResource.__nvoc_base_RmResourceCommon; + pThis->__nvoc_pbase_RmResource = &pThis->__nvoc_base_ChannelDescendant.__nvoc_base_GpuResource.__nvoc_base_RmResource; + pThis->__nvoc_pbase_GpuResource = &pThis->__nvoc_base_ChannelDescendant.__nvoc_base_GpuResource; + pThis->__nvoc_pbase_INotifier = &pThis->__nvoc_base_ChannelDescendant.__nvoc_base_Notifier.__nvoc_base_INotifier; + pThis->__nvoc_pbase_Notifier = &pThis->__nvoc_base_ChannelDescendant.__nvoc_base_Notifier; + pThis->__nvoc_pbase_ChannelDescendant = &pThis->__nvoc_base_ChannelDescendant; + __nvoc_init_ChannelDescendant(&pThis->__nvoc_base_ChannelDescendant, pRmhalspecowner); + __nvoc_init_funcTable_Sec2Context(pThis, pRmhalspecowner); +} + +NV_STATUS __nvoc_objCreate_Sec2Context(Sec2Context **ppThis, Dynamic *pParent, NvU32 createFlags, struct CALL_CONTEXT * arg_pCallContext, struct RS_RES_ALLOC_PARAMS_INTERNAL * arg_pParams) { + NV_STATUS status; + Object *pParentObj; + Sec2Context *pThis; + RmHalspecOwner *pRmhalspecowner; + + status = __nvoc_handleObjCreateMemAlloc(createFlags, sizeof(Sec2Context), (void**)&pThis, (void**)ppThis); + if (status != NV_OK) + return status; + + portMemSet(pThis, 0, sizeof(Sec2Context)); + + __nvoc_initRtti(staticCast(pThis, Dynamic), &__nvoc_class_def_Sec2Context); + + pThis->__nvoc_base_ChannelDescendant.__nvoc_base_GpuResource.__nvoc_base_RmResource.__nvoc_base_RsResource.__nvoc_base_Object.createFlags = createFlags; + + if (pParent != NULL && !(createFlags & NVOC_OBJ_CREATE_FLAGS_PARENT_HALSPEC_ONLY)) + { + pParentObj = dynamicCast(pParent, Object); + objAddChild(pParentObj, &pThis->__nvoc_base_ChannelDescendant.__nvoc_base_GpuResource.__nvoc_base_RmResource.__nvoc_base_RsResource.__nvoc_base_Object); + } + else + { + pThis->__nvoc_base_ChannelDescendant.__nvoc_base_GpuResource.__nvoc_base_RmResource.__nvoc_base_RsResource.__nvoc_base_Object.pParent = NULL; + } + + if ((pRmhalspecowner = dynamicCast(pParent, RmHalspecOwner)) == NULL) + pRmhalspecowner = objFindAncestorOfType(RmHalspecOwner, pParent); + NV_ASSERT_OR_RETURN(pRmhalspecowner != NULL, NV_ERR_INVALID_ARGUMENT); + + __nvoc_init_Sec2Context(pThis, pRmhalspecowner); + status = __nvoc_ctor_Sec2Context(pThis, pRmhalspecowner, arg_pCallContext, arg_pParams); + if (status != NV_OK) goto __nvoc_objCreate_Sec2Context_cleanup; + + *ppThis = pThis; + + return NV_OK; + +__nvoc_objCreate_Sec2Context_cleanup: + // do not call destructors here since the constructor already called them + if (createFlags & NVOC_OBJ_CREATE_FLAGS_IN_PLACE_CONSTRUCT) + portMemSet(pThis, 0, sizeof(Sec2Context)); + else + portMemFree(pThis); + + // coverity[leaked_storage:FALSE] + return status; +} + +NV_STATUS __nvoc_objCreateDynamic_Sec2Context(Sec2Context **ppThis, Dynamic *pParent, NvU32 createFlags, va_list args) { + NV_STATUS status; + struct CALL_CONTEXT * arg_pCallContext = va_arg(args, struct CALL_CONTEXT *); + struct RS_RES_ALLOC_PARAMS_INTERNAL * arg_pParams = va_arg(args, struct RS_RES_ALLOC_PARAMS_INTERNAL *); + + status = __nvoc_objCreate_Sec2Context(ppThis, pParent, createFlags, arg_pCallContext, arg_pParams); + + return status; +} + diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/generated/g_sec2_context_nvoc.h nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_sec2_context_nvoc.h --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/generated/g_sec2_context_nvoc.h 1970-01-01 00:00:00.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_sec2_context_nvoc.h 2024-03-05 22:18:44.000000000 +0000 @@ -0,0 +1,327 @@ +#ifndef _G_SEC2_CONTEXT_NVOC_H_ +#define _G_SEC2_CONTEXT_NVOC_H_ +#include "nvoc/runtime.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/* + * SPDX-FileCopyrightText: Copyright (c) 2021-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#include "g_sec2_context_nvoc.h" + +#ifndef SEC2_CONTEXT_H +#define SEC2_CONTEXT_H + +#include "core/bin_data.h" +#include "core/core.h" +#include "kernel/gpu/fifo/channel_descendant.h" + +/*! + * RM internal class representing NVXXXX_TSEC. Class is used for channel work + * submission. + */ +#ifdef NVOC_SEC2_CONTEXT_H_PRIVATE_ACCESS_ALLOWED +#define PRIVATE_FIELD(x) x +#else +#define PRIVATE_FIELD(x) NVOC_PRIVATE_FIELD(x) +#endif +struct Sec2Context { + const struct NVOC_RTTI *__nvoc_rtti; + struct ChannelDescendant __nvoc_base_ChannelDescendant; + struct Object *__nvoc_pbase_Object; + struct RsResource *__nvoc_pbase_RsResource; + struct RmResourceCommon *__nvoc_pbase_RmResourceCommon; + struct RmResource *__nvoc_pbase_RmResource; + struct GpuResource *__nvoc_pbase_GpuResource; + struct INotifier *__nvoc_pbase_INotifier; + struct Notifier *__nvoc_pbase_Notifier; + struct ChannelDescendant *__nvoc_pbase_ChannelDescendant; + struct Sec2Context *__nvoc_pbase_Sec2Context; + NV_STATUS (*__sec2ctxCheckMemInterUnmap__)(struct Sec2Context *, NvBool); + NvBool (*__sec2ctxShareCallback__)(struct Sec2Context *, struct RsClient *, struct RsResourceRef *, RS_SHARE_POLICY *); + NvBool (*__sec2ctxAccessCallback__)(struct Sec2Context *, struct RsClient *, void *, RsAccessRight); + NV_STATUS (*__sec2ctxMapTo__)(struct Sec2Context *, RS_RES_MAP_TO_PARAMS *); + NV_STATUS (*__sec2ctxGetMapAddrSpace__)(struct Sec2Context *, struct CALL_CONTEXT *, NvU32, NV_ADDRESS_SPACE *); + void (*__sec2ctxSetNotificationShare__)(struct Sec2Context *, struct NotifShare *); + NvU32 (*__sec2ctxGetRefCount__)(struct Sec2Context *); + void (*__sec2ctxAddAdditionalDependants__)(struct RsClient *, struct Sec2Context *, RsResourceRef *); + NV_STATUS (*__sec2ctxControl_Prologue__)(struct Sec2Context *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); + NV_STATUS (*__sec2ctxGetRegBaseOffsetAndSize__)(struct Sec2Context *, struct OBJGPU *, NvU32 *, NvU32 *); + NV_STATUS (*__sec2ctxInternalControlForward__)(struct Sec2Context *, NvU32, void *, NvU32); + NV_STATUS (*__sec2ctxUnmapFrom__)(struct Sec2Context *, RS_RES_UNMAP_FROM_PARAMS *); + void (*__sec2ctxControl_Epilogue__)(struct Sec2Context *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); + NV_STATUS (*__sec2ctxControlLookup__)(struct Sec2Context *, struct RS_RES_CONTROL_PARAMS_INTERNAL *, const struct NVOC_EXPORTED_METHOD_DEF **); + NV_STATUS (*__sec2ctxGetSwMethods__)(struct Sec2Context *, const METHOD **, NvU32 *); + NvHandle (*__sec2ctxGetInternalObjectHandle__)(struct Sec2Context *); + NV_STATUS (*__sec2ctxControl__)(struct Sec2Context *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); + NV_STATUS (*__sec2ctxUnmap__)(struct Sec2Context *, struct CALL_CONTEXT *, struct RsCpuMapping *); + NV_STATUS (*__sec2ctxGetMemInterMapParams__)(struct Sec2Context *, RMRES_MEM_INTER_MAP_PARAMS *); + NV_STATUS (*__sec2ctxGetMemoryMappingDescriptor__)(struct Sec2Context *, struct MEMORY_DESCRIPTOR **); + NvBool (*__sec2ctxIsSwMethodStalling__)(struct Sec2Context *, NvU32); + NV_STATUS (*__sec2ctxControlFilter__)(struct Sec2Context *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); + NV_STATUS (*__sec2ctxUnregisterEvent__)(struct Sec2Context *, NvHandle, NvHandle, NvHandle, NvHandle); + NV_STATUS (*__sec2ctxControlSerialization_Prologue__)(struct Sec2Context *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); + NvBool (*__sec2ctxCanCopy__)(struct Sec2Context *); + void (*__sec2ctxPreDestruct__)(struct Sec2Context *); + NV_STATUS (*__sec2ctxIsDuplicate__)(struct Sec2Context *, NvHandle, NvBool *); + void (*__sec2ctxControlSerialization_Epilogue__)(struct Sec2Context *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); + PEVENTNOTIFICATION *(*__sec2ctxGetNotificationListPtr__)(struct Sec2Context *); + struct NotifShare *(*__sec2ctxGetNotificationShare__)(struct Sec2Context *); + NV_STATUS (*__sec2ctxMap__)(struct Sec2Context *, struct CALL_CONTEXT *, struct RS_CPU_MAP_PARAMS *, struct RsCpuMapping *); + NV_STATUS (*__sec2ctxGetOrAllocNotifShare__)(struct Sec2Context *, NvHandle, NvHandle, struct NotifShare **); +}; + +#ifndef __NVOC_CLASS_Sec2Context_TYPEDEF__ +#define __NVOC_CLASS_Sec2Context_TYPEDEF__ +typedef struct Sec2Context Sec2Context; +#endif /* __NVOC_CLASS_Sec2Context_TYPEDEF__ */ + +#ifndef __nvoc_class_id_Sec2Context +#define __nvoc_class_id_Sec2Context 0x4c3439 +#endif /* __nvoc_class_id_Sec2Context */ + +extern const struct NVOC_CLASS_DEF __nvoc_class_def_Sec2Context; + +#define __staticCast_Sec2Context(pThis) \ + ((pThis)->__nvoc_pbase_Sec2Context) + +#ifdef __nvoc_sec2_context_h_disabled +#define __dynamicCast_Sec2Context(pThis) ((Sec2Context*)NULL) +#else //__nvoc_sec2_context_h_disabled +#define __dynamicCast_Sec2Context(pThis) \ + ((Sec2Context*)__nvoc_dynamicCast(staticCast((pThis), Dynamic), classInfo(Sec2Context))) +#endif //__nvoc_sec2_context_h_disabled + + +NV_STATUS __nvoc_objCreateDynamic_Sec2Context(Sec2Context**, Dynamic*, NvU32, va_list); + +NV_STATUS __nvoc_objCreate_Sec2Context(Sec2Context**, Dynamic*, NvU32, struct CALL_CONTEXT * arg_pCallContext, struct RS_RES_ALLOC_PARAMS_INTERNAL * arg_pParams); +#define __objCreate_Sec2Context(ppNewObj, pParent, createFlags, arg_pCallContext, arg_pParams) \ + __nvoc_objCreate_Sec2Context((ppNewObj), staticCast((pParent), Dynamic), (createFlags), arg_pCallContext, arg_pParams) + +#define sec2ctxCheckMemInterUnmap(pChannelDescendant, bSubdeviceHandleProvided) sec2ctxCheckMemInterUnmap_DISPATCH(pChannelDescendant, bSubdeviceHandleProvided) +#define sec2ctxShareCallback(pGpuResource, pInvokingClient, pParentRef, pSharePolicy) sec2ctxShareCallback_DISPATCH(pGpuResource, pInvokingClient, pParentRef, pSharePolicy) +#define sec2ctxAccessCallback(pResource, pInvokingClient, pAllocParams, accessRight) sec2ctxAccessCallback_DISPATCH(pResource, pInvokingClient, pAllocParams, accessRight) +#define sec2ctxMapTo(pResource, pParams) sec2ctxMapTo_DISPATCH(pResource, pParams) +#define sec2ctxGetMapAddrSpace(pGpuResource, pCallContext, mapFlags, pAddrSpace) sec2ctxGetMapAddrSpace_DISPATCH(pGpuResource, pCallContext, mapFlags, pAddrSpace) +#define sec2ctxSetNotificationShare(pNotifier, pNotifShare) sec2ctxSetNotificationShare_DISPATCH(pNotifier, pNotifShare) +#define sec2ctxGetRefCount(pResource) sec2ctxGetRefCount_DISPATCH(pResource) +#define sec2ctxAddAdditionalDependants(pClient, pResource, pReference) sec2ctxAddAdditionalDependants_DISPATCH(pClient, pResource, pReference) +#define sec2ctxControl_Prologue(pResource, pCallContext, pParams) sec2ctxControl_Prologue_DISPATCH(pResource, pCallContext, pParams) +#define sec2ctxGetRegBaseOffsetAndSize(pGpuResource, pGpu, pOffset, pSize) sec2ctxGetRegBaseOffsetAndSize_DISPATCH(pGpuResource, pGpu, pOffset, pSize) +#define sec2ctxInternalControlForward(pGpuResource, command, pParams, size) sec2ctxInternalControlForward_DISPATCH(pGpuResource, command, pParams, size) +#define sec2ctxUnmapFrom(pResource, pParams) sec2ctxUnmapFrom_DISPATCH(pResource, pParams) +#define sec2ctxControl_Epilogue(pResource, pCallContext, pParams) sec2ctxControl_Epilogue_DISPATCH(pResource, pCallContext, pParams) +#define sec2ctxControlLookup(pResource, pParams, ppEntry) sec2ctxControlLookup_DISPATCH(pResource, pParams, ppEntry) +#define sec2ctxGetSwMethods(pChannelDescendant, ppMethods, pNumMethods) sec2ctxGetSwMethods_DISPATCH(pChannelDescendant, ppMethods, pNumMethods) +#define sec2ctxGetInternalObjectHandle(pGpuResource) sec2ctxGetInternalObjectHandle_DISPATCH(pGpuResource) +#define sec2ctxControl(pGpuResource, pCallContext, pParams) sec2ctxControl_DISPATCH(pGpuResource, pCallContext, pParams) +#define sec2ctxUnmap(pGpuResource, pCallContext, pCpuMapping) sec2ctxUnmap_DISPATCH(pGpuResource, pCallContext, pCpuMapping) +#define sec2ctxGetMemInterMapParams(pRmResource, pParams) sec2ctxGetMemInterMapParams_DISPATCH(pRmResource, pParams) +#define sec2ctxGetMemoryMappingDescriptor(pRmResource, ppMemDesc) sec2ctxGetMemoryMappingDescriptor_DISPATCH(pRmResource, ppMemDesc) +#define sec2ctxIsSwMethodStalling(pChannelDescendant, hHandle) sec2ctxIsSwMethodStalling_DISPATCH(pChannelDescendant, hHandle) +#define sec2ctxControlFilter(pResource, pCallContext, pParams) sec2ctxControlFilter_DISPATCH(pResource, pCallContext, pParams) +#define sec2ctxUnregisterEvent(pNotifier, hNotifierClient, hNotifierResource, hEventClient, hEvent) sec2ctxUnregisterEvent_DISPATCH(pNotifier, hNotifierClient, hNotifierResource, hEventClient, hEvent) +#define sec2ctxControlSerialization_Prologue(pResource, pCallContext, pParams) sec2ctxControlSerialization_Prologue_DISPATCH(pResource, pCallContext, pParams) +#define sec2ctxCanCopy(pResource) sec2ctxCanCopy_DISPATCH(pResource) +#define sec2ctxPreDestruct(pResource) sec2ctxPreDestruct_DISPATCH(pResource) +#define sec2ctxIsDuplicate(pResource, hMemory, pDuplicate) sec2ctxIsDuplicate_DISPATCH(pResource, hMemory, pDuplicate) +#define sec2ctxControlSerialization_Epilogue(pResource, pCallContext, pParams) sec2ctxControlSerialization_Epilogue_DISPATCH(pResource, pCallContext, pParams) +#define sec2ctxGetNotificationListPtr(pNotifier) sec2ctxGetNotificationListPtr_DISPATCH(pNotifier) +#define sec2ctxGetNotificationShare(pNotifier) sec2ctxGetNotificationShare_DISPATCH(pNotifier) +#define sec2ctxMap(pGpuResource, pCallContext, pParams, pCpuMapping) sec2ctxMap_DISPATCH(pGpuResource, pCallContext, pParams, pCpuMapping) +#define sec2ctxGetOrAllocNotifShare(pNotifier, hNotifierClient, hNotifierResource, ppNotifShare) sec2ctxGetOrAllocNotifShare_DISPATCH(pNotifier, hNotifierClient, hNotifierResource, ppNotifShare) +NV_STATUS sec2ctxConstructHal_KERNEL(struct Sec2Context *pSec2Context, struct CALL_CONTEXT *pCallContext, struct RS_RES_ALLOC_PARAMS_INTERNAL *pParams); + + +#ifdef __nvoc_sec2_context_h_disabled +static inline NV_STATUS sec2ctxConstructHal(struct Sec2Context *pSec2Context, struct CALL_CONTEXT *pCallContext, struct RS_RES_ALLOC_PARAMS_INTERNAL *pParams) { + NV_ASSERT_FAILED_PRECOMP("Sec2Context was disabled!"); + return NV_ERR_NOT_SUPPORTED; +} +#else //__nvoc_sec2_context_h_disabled +#define sec2ctxConstructHal(pSec2Context, pCallContext, pParams) sec2ctxConstructHal_KERNEL(pSec2Context, pCallContext, pParams) +#endif //__nvoc_sec2_context_h_disabled + +#define sec2ctxConstructHal_HAL(pSec2Context, pCallContext, pParams) sec2ctxConstructHal(pSec2Context, pCallContext, pParams) + +void sec2ctxDestructHal_KERNEL(struct Sec2Context *pSec2Context); + + +#ifdef __nvoc_sec2_context_h_disabled +static inline void sec2ctxDestructHal(struct Sec2Context *pSec2Context) { + NV_ASSERT_FAILED_PRECOMP("Sec2Context was disabled!"); +} +#else //__nvoc_sec2_context_h_disabled +#define sec2ctxDestructHal(pSec2Context) sec2ctxDestructHal_KERNEL(pSec2Context) +#endif //__nvoc_sec2_context_h_disabled + +#define sec2ctxDestructHal_HAL(pSec2Context) sec2ctxDestructHal(pSec2Context) + +static inline NV_STATUS sec2ctxCheckMemInterUnmap_DISPATCH(struct Sec2Context *pChannelDescendant, NvBool bSubdeviceHandleProvided) { + return pChannelDescendant->__sec2ctxCheckMemInterUnmap__(pChannelDescendant, bSubdeviceHandleProvided); +} + +static inline NvBool sec2ctxShareCallback_DISPATCH(struct Sec2Context *pGpuResource, struct RsClient *pInvokingClient, struct RsResourceRef *pParentRef, RS_SHARE_POLICY *pSharePolicy) { + return pGpuResource->__sec2ctxShareCallback__(pGpuResource, pInvokingClient, pParentRef, pSharePolicy); +} + +static inline NvBool sec2ctxAccessCallback_DISPATCH(struct Sec2Context *pResource, struct RsClient *pInvokingClient, void *pAllocParams, RsAccessRight accessRight) { + return pResource->__sec2ctxAccessCallback__(pResource, pInvokingClient, pAllocParams, accessRight); +} + +static inline NV_STATUS sec2ctxMapTo_DISPATCH(struct Sec2Context *pResource, RS_RES_MAP_TO_PARAMS *pParams) { + return pResource->__sec2ctxMapTo__(pResource, pParams); +} + +static inline NV_STATUS sec2ctxGetMapAddrSpace_DISPATCH(struct Sec2Context *pGpuResource, struct CALL_CONTEXT *pCallContext, NvU32 mapFlags, NV_ADDRESS_SPACE *pAddrSpace) { + return pGpuResource->__sec2ctxGetMapAddrSpace__(pGpuResource, pCallContext, mapFlags, pAddrSpace); +} + +static inline void sec2ctxSetNotificationShare_DISPATCH(struct Sec2Context *pNotifier, struct NotifShare *pNotifShare) { + pNotifier->__sec2ctxSetNotificationShare__(pNotifier, pNotifShare); +} + +static inline NvU32 sec2ctxGetRefCount_DISPATCH(struct Sec2Context *pResource) { + return pResource->__sec2ctxGetRefCount__(pResource); +} + +static inline void sec2ctxAddAdditionalDependants_DISPATCH(struct RsClient *pClient, struct Sec2Context *pResource, RsResourceRef *pReference) { + pResource->__sec2ctxAddAdditionalDependants__(pClient, pResource, pReference); +} + +static inline NV_STATUS sec2ctxControl_Prologue_DISPATCH(struct Sec2Context *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return pResource->__sec2ctxControl_Prologue__(pResource, pCallContext, pParams); +} + +static inline NV_STATUS sec2ctxGetRegBaseOffsetAndSize_DISPATCH(struct Sec2Context *pGpuResource, struct OBJGPU *pGpu, NvU32 *pOffset, NvU32 *pSize) { + return pGpuResource->__sec2ctxGetRegBaseOffsetAndSize__(pGpuResource, pGpu, pOffset, pSize); +} + +static inline NV_STATUS sec2ctxInternalControlForward_DISPATCH(struct Sec2Context *pGpuResource, NvU32 command, void *pParams, NvU32 size) { + return pGpuResource->__sec2ctxInternalControlForward__(pGpuResource, command, pParams, size); +} + +static inline NV_STATUS sec2ctxUnmapFrom_DISPATCH(struct Sec2Context *pResource, RS_RES_UNMAP_FROM_PARAMS *pParams) { + return pResource->__sec2ctxUnmapFrom__(pResource, pParams); +} + +static inline void sec2ctxControl_Epilogue_DISPATCH(struct Sec2Context *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + pResource->__sec2ctxControl_Epilogue__(pResource, pCallContext, pParams); +} + +static inline NV_STATUS sec2ctxControlLookup_DISPATCH(struct Sec2Context *pResource, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams, const struct NVOC_EXPORTED_METHOD_DEF **ppEntry) { + return pResource->__sec2ctxControlLookup__(pResource, pParams, ppEntry); +} + +static inline NV_STATUS sec2ctxGetSwMethods_DISPATCH(struct Sec2Context *pChannelDescendant, const METHOD **ppMethods, NvU32 *pNumMethods) { + return pChannelDescendant->__sec2ctxGetSwMethods__(pChannelDescendant, ppMethods, pNumMethods); +} + +static inline NvHandle sec2ctxGetInternalObjectHandle_DISPATCH(struct Sec2Context *pGpuResource) { + return pGpuResource->__sec2ctxGetInternalObjectHandle__(pGpuResource); +} + +static inline NV_STATUS sec2ctxControl_DISPATCH(struct Sec2Context *pGpuResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return pGpuResource->__sec2ctxControl__(pGpuResource, pCallContext, pParams); +} + +static inline NV_STATUS sec2ctxUnmap_DISPATCH(struct Sec2Context *pGpuResource, struct CALL_CONTEXT *pCallContext, struct RsCpuMapping *pCpuMapping) { + return pGpuResource->__sec2ctxUnmap__(pGpuResource, pCallContext, pCpuMapping); +} + +static inline NV_STATUS sec2ctxGetMemInterMapParams_DISPATCH(struct Sec2Context *pRmResource, RMRES_MEM_INTER_MAP_PARAMS *pParams) { + return pRmResource->__sec2ctxGetMemInterMapParams__(pRmResource, pParams); +} + +static inline NV_STATUS sec2ctxGetMemoryMappingDescriptor_DISPATCH(struct Sec2Context *pRmResource, struct MEMORY_DESCRIPTOR **ppMemDesc) { + return pRmResource->__sec2ctxGetMemoryMappingDescriptor__(pRmResource, ppMemDesc); +} + +static inline NvBool sec2ctxIsSwMethodStalling_DISPATCH(struct Sec2Context *pChannelDescendant, NvU32 hHandle) { + return pChannelDescendant->__sec2ctxIsSwMethodStalling__(pChannelDescendant, hHandle); +} + +static inline NV_STATUS sec2ctxControlFilter_DISPATCH(struct Sec2Context *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return pResource->__sec2ctxControlFilter__(pResource, pCallContext, pParams); +} + +static inline NV_STATUS sec2ctxUnregisterEvent_DISPATCH(struct Sec2Context *pNotifier, NvHandle hNotifierClient, NvHandle hNotifierResource, NvHandle hEventClient, NvHandle hEvent) { + return pNotifier->__sec2ctxUnregisterEvent__(pNotifier, hNotifierClient, hNotifierResource, hEventClient, hEvent); +} + +static inline NV_STATUS sec2ctxControlSerialization_Prologue_DISPATCH(struct Sec2Context *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return pResource->__sec2ctxControlSerialization_Prologue__(pResource, pCallContext, pParams); +} + +static inline NvBool sec2ctxCanCopy_DISPATCH(struct Sec2Context *pResource) { + return pResource->__sec2ctxCanCopy__(pResource); +} + +static inline void sec2ctxPreDestruct_DISPATCH(struct Sec2Context *pResource) { + pResource->__sec2ctxPreDestruct__(pResource); +} + +static inline NV_STATUS sec2ctxIsDuplicate_DISPATCH(struct Sec2Context *pResource, NvHandle hMemory, NvBool *pDuplicate) { + return pResource->__sec2ctxIsDuplicate__(pResource, hMemory, pDuplicate); +} + +static inline void sec2ctxControlSerialization_Epilogue_DISPATCH(struct Sec2Context *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + pResource->__sec2ctxControlSerialization_Epilogue__(pResource, pCallContext, pParams); +} + +static inline PEVENTNOTIFICATION *sec2ctxGetNotificationListPtr_DISPATCH(struct Sec2Context *pNotifier) { + return pNotifier->__sec2ctxGetNotificationListPtr__(pNotifier); +} + +static inline struct NotifShare *sec2ctxGetNotificationShare_DISPATCH(struct Sec2Context *pNotifier) { + return pNotifier->__sec2ctxGetNotificationShare__(pNotifier); +} + +static inline NV_STATUS sec2ctxMap_DISPATCH(struct Sec2Context *pGpuResource, struct CALL_CONTEXT *pCallContext, struct RS_CPU_MAP_PARAMS *pParams, struct RsCpuMapping *pCpuMapping) { + return pGpuResource->__sec2ctxMap__(pGpuResource, pCallContext, pParams, pCpuMapping); +} + +static inline NV_STATUS sec2ctxGetOrAllocNotifShare_DISPATCH(struct Sec2Context *pNotifier, NvHandle hNotifierClient, NvHandle hNotifierResource, struct NotifShare **ppNotifShare) { + return pNotifier->__sec2ctxGetOrAllocNotifShare__(pNotifier, hNotifierClient, hNotifierResource, ppNotifShare); +} + +static inline NV_STATUS __nvoc_sec2ctxConstruct(struct Sec2Context *arg_pSec2Context, struct CALL_CONTEXT *arg_pCallContext, struct RS_RES_ALLOC_PARAMS_INTERNAL *arg_pParams) { + return sec2ctxConstructHal(arg_pSec2Context, arg_pCallContext, arg_pParams); +} + +static inline void __nvoc_sec2ctxDestruct(struct Sec2Context *pSec2Context) { + sec2ctxDestructHal(pSec2Context); +} + +#undef PRIVATE_FIELD + + +#endif // SEC2_CONTEXT_H + +#ifdef __cplusplus +} // extern "C" +#endif +#endif // _G_SEC2_CONTEXT_NVOC_H_ diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/generated/g_sec2_utils_nvoc.c nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_sec2_utils_nvoc.c --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/generated/g_sec2_utils_nvoc.c 1970-01-01 00:00:00.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_sec2_utils_nvoc.c 2024-03-05 22:18:45.000000000 +0000 @@ -0,0 +1,165 @@ +#define NVOC_SEC2_UTILS_H_PRIVATE_ACCESS_ALLOWED +#include "nvoc/runtime.h" +#include "nvoc/rtti.h" +#include "nvtypes.h" +#include "nvport/nvport.h" +#include "nvport/inline/util_valist.h" +#include "utils/nvassert.h" +#include "g_sec2_utils_nvoc.h" + +#ifdef DEBUG +char __nvoc_class_id_uniqueness_check_0x7716b1 = 1; +#endif + +extern const struct NVOC_CLASS_DEF __nvoc_class_def_Sec2Utils; + +extern const struct NVOC_CLASS_DEF __nvoc_class_def_Object; + +void __nvoc_init_Sec2Utils(Sec2Utils*); +void __nvoc_init_funcTable_Sec2Utils(Sec2Utils*); +NV_STATUS __nvoc_ctor_Sec2Utils(Sec2Utils*, struct OBJGPU * arg_pGpu, KERNEL_MIG_GPU_INSTANCE * arg_pKernelMIGGPUInstance); +void __nvoc_init_dataField_Sec2Utils(Sec2Utils*); +void __nvoc_dtor_Sec2Utils(Sec2Utils*); +extern const struct NVOC_EXPORT_INFO __nvoc_export_info_Sec2Utils; + +static const struct NVOC_RTTI __nvoc_rtti_Sec2Utils_Sec2Utils = { + /*pClassDef=*/ &__nvoc_class_def_Sec2Utils, + /*dtor=*/ (NVOC_DYNAMIC_DTOR) &__nvoc_dtor_Sec2Utils, + /*offset=*/ 0, +}; + +static const struct NVOC_RTTI __nvoc_rtti_Sec2Utils_Object = { + /*pClassDef=*/ &__nvoc_class_def_Object, + /*dtor=*/ &__nvoc_destructFromBase, + /*offset=*/ NV_OFFSETOF(Sec2Utils, __nvoc_base_Object), +}; + +static const struct NVOC_CASTINFO __nvoc_castinfo_Sec2Utils = { + /*numRelatives=*/ 2, + /*relatives=*/ { + &__nvoc_rtti_Sec2Utils_Sec2Utils, + &__nvoc_rtti_Sec2Utils_Object, + }, +}; + +const struct NVOC_CLASS_DEF __nvoc_class_def_Sec2Utils = +{ + /*classInfo=*/ { + /*size=*/ sizeof(Sec2Utils), + /*classId=*/ classId(Sec2Utils), + /*providerId=*/ &__nvoc_rtti_provider, +#if NV_PRINTF_STRINGS_ALLOWED + /*name=*/ "Sec2Utils", +#endif + }, + /*objCreatefn=*/ (NVOC_DYNAMIC_OBJ_CREATE) &__nvoc_objCreateDynamic_Sec2Utils, + /*pCastInfo=*/ &__nvoc_castinfo_Sec2Utils, + /*pExportInfo=*/ &__nvoc_export_info_Sec2Utils +}; + +const struct NVOC_EXPORT_INFO __nvoc_export_info_Sec2Utils = +{ + /*numEntries=*/ 0, + /*pExportEntries=*/ 0 +}; + +void __nvoc_dtor_Object(Object*); +void __nvoc_dtor_Sec2Utils(Sec2Utils *pThis) { + __nvoc_sec2utilsDestruct(pThis); + __nvoc_dtor_Object(&pThis->__nvoc_base_Object); + PORT_UNREFERENCED_VARIABLE(pThis); +} + +void __nvoc_init_dataField_Sec2Utils(Sec2Utils *pThis) { + PORT_UNREFERENCED_VARIABLE(pThis); +} + +NV_STATUS __nvoc_ctor_Object(Object* ); +NV_STATUS __nvoc_ctor_Sec2Utils(Sec2Utils *pThis, struct OBJGPU * arg_pGpu, KERNEL_MIG_GPU_INSTANCE * arg_pKernelMIGGPUInstance) { + NV_STATUS status = NV_OK; + status = __nvoc_ctor_Object(&pThis->__nvoc_base_Object); + if (status != NV_OK) goto __nvoc_ctor_Sec2Utils_fail_Object; + __nvoc_init_dataField_Sec2Utils(pThis); + + status = __nvoc_sec2utilsConstruct(pThis, arg_pGpu, arg_pKernelMIGGPUInstance); + if (status != NV_OK) goto __nvoc_ctor_Sec2Utils_fail__init; + goto __nvoc_ctor_Sec2Utils_exit; // Success + +__nvoc_ctor_Sec2Utils_fail__init: + __nvoc_dtor_Object(&pThis->__nvoc_base_Object); +__nvoc_ctor_Sec2Utils_fail_Object: +__nvoc_ctor_Sec2Utils_exit: + + return status; +} + +static void __nvoc_init_funcTable_Sec2Utils_1(Sec2Utils *pThis) { + PORT_UNREFERENCED_VARIABLE(pThis); +} + +void __nvoc_init_funcTable_Sec2Utils(Sec2Utils *pThis) { + __nvoc_init_funcTable_Sec2Utils_1(pThis); +} + +void __nvoc_init_Object(Object*); +void __nvoc_init_Sec2Utils(Sec2Utils *pThis) { + pThis->__nvoc_pbase_Sec2Utils = pThis; + pThis->__nvoc_pbase_Object = &pThis->__nvoc_base_Object; + __nvoc_init_Object(&pThis->__nvoc_base_Object); + __nvoc_init_funcTable_Sec2Utils(pThis); +} + +NV_STATUS __nvoc_objCreate_Sec2Utils(Sec2Utils **ppThis, Dynamic *pParent, NvU32 createFlags, struct OBJGPU * arg_pGpu, KERNEL_MIG_GPU_INSTANCE * arg_pKernelMIGGPUInstance) { + NV_STATUS status; + Object *pParentObj; + Sec2Utils *pThis; + + status = __nvoc_handleObjCreateMemAlloc(createFlags, sizeof(Sec2Utils), (void**)&pThis, (void**)ppThis); + if (status != NV_OK) + return status; + + portMemSet(pThis, 0, sizeof(Sec2Utils)); + + __nvoc_initRtti(staticCast(pThis, Dynamic), &__nvoc_class_def_Sec2Utils); + + pThis->__nvoc_base_Object.createFlags = createFlags; + + if (pParent != NULL && !(createFlags & NVOC_OBJ_CREATE_FLAGS_PARENT_HALSPEC_ONLY)) + { + pParentObj = dynamicCast(pParent, Object); + objAddChild(pParentObj, &pThis->__nvoc_base_Object); + } + else + { + pThis->__nvoc_base_Object.pParent = NULL; + } + + __nvoc_init_Sec2Utils(pThis); + status = __nvoc_ctor_Sec2Utils(pThis, arg_pGpu, arg_pKernelMIGGPUInstance); + if (status != NV_OK) goto __nvoc_objCreate_Sec2Utils_cleanup; + + *ppThis = pThis; + + return NV_OK; + +__nvoc_objCreate_Sec2Utils_cleanup: + // do not call destructors here since the constructor already called them + if (createFlags & NVOC_OBJ_CREATE_FLAGS_IN_PLACE_CONSTRUCT) + portMemSet(pThis, 0, sizeof(Sec2Utils)); + else + portMemFree(pThis); + + // coverity[leaked_storage:FALSE] + return status; +} + +NV_STATUS __nvoc_objCreateDynamic_Sec2Utils(Sec2Utils **ppThis, Dynamic *pParent, NvU32 createFlags, va_list args) { + NV_STATUS status; + struct OBJGPU * arg_pGpu = va_arg(args, struct OBJGPU *); + KERNEL_MIG_GPU_INSTANCE * arg_pKernelMIGGPUInstance = va_arg(args, KERNEL_MIG_GPU_INSTANCE *); + + status = __nvoc_objCreate_Sec2Utils(ppThis, pParent, createFlags, arg_pGpu, arg_pKernelMIGGPUInstance); + + return status; +} + diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/generated/g_sec2_utils_nvoc.h nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_sec2_utils_nvoc.h --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/generated/g_sec2_utils_nvoc.h 1970-01-01 00:00:00.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_sec2_utils_nvoc.h 2024-03-05 22:18:45.000000000 +0000 @@ -0,0 +1,163 @@ +#ifndef _G_SEC2_UTILS_NVOC_H_ +#define _G_SEC2_UTILS_NVOC_H_ +#include "nvoc/runtime.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/* + * SPDX-FileCopyrightText: Copyright (c) 2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#include "g_sec2_utils_nvoc.h" + +#ifndef SEC2_UTILS_H +#define SEC2_UTILS_H + +#include "gpu/gpu_resource.h" // GpuResource + +#include "kernel/gpu/mem_mgr/channel_utils.h" + +#include "kernel/gpu/conf_compute/ccsl_context.h" + +#define SEC2_AUTH_TAG_BUF_SIZE_BYTES (16) +#define SHA_256_HASH_SIZE_BYTES (32) + +typedef struct +{ + MEMORY_DESCRIPTOR *pMemDesc; + NvU64 offset; + NvU64 length; + NvU64 submittedWorkId; +} SEC2UTILS_MEMSET_PARAMS; + +typedef struct +{ + NvHandle hPhysMem; + NvHandle hVirtMem; + NvHandle hVASpace; + NvU64 gpuVA; + NvU64 size; + MEMORY_DESCRIPTOR *pMemDesc; +} SEC2UTILS_BUFFER_INFO; + +#ifdef NVOC_SEC2_UTILS_H_PRIVATE_ACCESS_ALLOWED +#define PRIVATE_FIELD(x) x +#else +#define PRIVATE_FIELD(x) NVOC_PRIVATE_FIELD(x) +#endif +struct Sec2Utils { + const struct NVOC_RTTI *__nvoc_rtti; + struct Object __nvoc_base_Object; + struct Object *__nvoc_pbase_Object; + struct Sec2Utils *__nvoc_pbase_Sec2Utils; + NvHandle hClient; + NvHandle hDevice; + NvHandle hSubdevice; + OBJCHANNEL *pChannel; + struct OBJGPU *pGpu; + NvU32 sec2Class; + NvU64 lastSubmittedPayload; + NvU64 lastCompletedPayload; + CCSL_CONTEXT *pCcslCtx; + SEC2UTILS_BUFFER_INFO scrubMthdAuthTagBuf; + SEC2UTILS_BUFFER_INFO semaMthdAuthTagBuf; + NvU32 authTagPutIndex; + NvU32 authTagGetIndex; +}; + +#ifndef __NVOC_CLASS_Sec2Utils_TYPEDEF__ +#define __NVOC_CLASS_Sec2Utils_TYPEDEF__ +typedef struct Sec2Utils Sec2Utils; +#endif /* __NVOC_CLASS_Sec2Utils_TYPEDEF__ */ + +#ifndef __nvoc_class_id_Sec2Utils +#define __nvoc_class_id_Sec2Utils 0x7716b1 +#endif /* __nvoc_class_id_Sec2Utils */ + +extern const struct NVOC_CLASS_DEF __nvoc_class_def_Sec2Utils; + +#define __staticCast_Sec2Utils(pThis) \ + ((pThis)->__nvoc_pbase_Sec2Utils) + +#ifdef __nvoc_sec2_utils_h_disabled +#define __dynamicCast_Sec2Utils(pThis) ((Sec2Utils*)NULL) +#else //__nvoc_sec2_utils_h_disabled +#define __dynamicCast_Sec2Utils(pThis) \ + ((Sec2Utils*)__nvoc_dynamicCast(staticCast((pThis), Dynamic), classInfo(Sec2Utils))) +#endif //__nvoc_sec2_utils_h_disabled + + +NV_STATUS __nvoc_objCreateDynamic_Sec2Utils(Sec2Utils**, Dynamic*, NvU32, va_list); + +NV_STATUS __nvoc_objCreate_Sec2Utils(Sec2Utils**, Dynamic*, NvU32, struct OBJGPU * arg_pGpu, KERNEL_MIG_GPU_INSTANCE * arg_pKernelMIGGPUInstance); +#define __objCreate_Sec2Utils(ppNewObj, pParent, createFlags, arg_pGpu, arg_pKernelMIGGPUInstance) \ + __nvoc_objCreate_Sec2Utils((ppNewObj), staticCast((pParent), Dynamic), (createFlags), arg_pGpu, arg_pKernelMIGGPUInstance) + +NV_STATUS sec2utilsConstruct_IMPL(struct Sec2Utils *arg_psec2utils, struct OBJGPU *arg_pGpu, KERNEL_MIG_GPU_INSTANCE *arg_pKernelMIGGPUInstance); + +#define __nvoc_sec2utilsConstruct(arg_psec2utils, arg_pGpu, arg_pKernelMIGGPUInstance) sec2utilsConstruct_IMPL(arg_psec2utils, arg_pGpu, arg_pKernelMIGGPUInstance) +void sec2utilsDestruct_IMPL(struct Sec2Utils *psec2utils); + +#define __nvoc_sec2utilsDestruct(psec2utils) sec2utilsDestruct_IMPL(psec2utils) +NV_STATUS sec2utilsMemset_IMPL(struct Sec2Utils *psec2utils, SEC2UTILS_MEMSET_PARAMS *pParams); + +#ifdef __nvoc_sec2_utils_h_disabled +static inline NV_STATUS sec2utilsMemset(struct Sec2Utils *psec2utils, SEC2UTILS_MEMSET_PARAMS *pParams) { + NV_ASSERT_FAILED_PRECOMP("Sec2Utils was disabled!"); + return NV_ERR_NOT_SUPPORTED; +} +#else //__nvoc_sec2_utils_h_disabled +#define sec2utilsMemset(psec2utils, pParams) sec2utilsMemset_IMPL(psec2utils, pParams) +#endif //__nvoc_sec2_utils_h_disabled + +NvU64 sec2utilsUpdateProgress_IMPL(struct Sec2Utils *psec2utils); + +#ifdef __nvoc_sec2_utils_h_disabled +static inline NvU64 sec2utilsUpdateProgress(struct Sec2Utils *psec2utils) { + NV_ASSERT_FAILED_PRECOMP("Sec2Utils was disabled!"); + return 0; +} +#else //__nvoc_sec2_utils_h_disabled +#define sec2utilsUpdateProgress(psec2utils) sec2utilsUpdateProgress_IMPL(psec2utils) +#endif //__nvoc_sec2_utils_h_disabled + +void sec2utilsServiceInterrupts_IMPL(struct Sec2Utils *psec2utils); + +#ifdef __nvoc_sec2_utils_h_disabled +static inline void sec2utilsServiceInterrupts(struct Sec2Utils *psec2utils) { + NV_ASSERT_FAILED_PRECOMP("Sec2Utils was disabled!"); +} +#else //__nvoc_sec2_utils_h_disabled +#define sec2utilsServiceInterrupts(psec2utils) sec2utilsServiceInterrupts_IMPL(psec2utils) +#endif //__nvoc_sec2_utils_h_disabled + +#undef PRIVATE_FIELD + + +#endif // SEC2_UTILS_H + +#ifdef __cplusplus +} // extern "C" +#endif +#endif // _G_SEC2_UTILS_NVOC_H_ diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/generated/g_sem_surf_nvoc.c nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_sem_surf_nvoc.c --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/generated/g_sem_surf_nvoc.c 1970-01-01 00:00:00.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_sem_surf_nvoc.c 2024-03-05 22:18:45.000000000 +0000 @@ -0,0 +1,461 @@ +#define NVOC_SEM_SURF_H_PRIVATE_ACCESS_ALLOWED +#include "nvoc/runtime.h" +#include "nvoc/rtti.h" +#include "nvtypes.h" +#include "nvport/nvport.h" +#include "nvport/inline/util_valist.h" +#include "utils/nvassert.h" +#include "g_sem_surf_nvoc.h" + +#ifdef DEBUG +char __nvoc_class_id_uniqueness_check_0xeabc69 = 1; +#endif + +extern const struct NVOC_CLASS_DEF __nvoc_class_def_SemaphoreSurface; + +extern const struct NVOC_CLASS_DEF __nvoc_class_def_Object; + +extern const struct NVOC_CLASS_DEF __nvoc_class_def_RsResource; + +extern const struct NVOC_CLASS_DEF __nvoc_class_def_RmResourceCommon; + +extern const struct NVOC_CLASS_DEF __nvoc_class_def_RmResource; + +extern const struct NVOC_CLASS_DEF __nvoc_class_def_GpuResource; + +void __nvoc_init_SemaphoreSurface(SemaphoreSurface*); +void __nvoc_init_funcTable_SemaphoreSurface(SemaphoreSurface*); +NV_STATUS __nvoc_ctor_SemaphoreSurface(SemaphoreSurface*, CALL_CONTEXT * arg_pCallContext, struct RS_RES_ALLOC_PARAMS_INTERNAL * arg_pParams); +void __nvoc_init_dataField_SemaphoreSurface(SemaphoreSurface*); +void __nvoc_dtor_SemaphoreSurface(SemaphoreSurface*); +extern const struct NVOC_EXPORT_INFO __nvoc_export_info_SemaphoreSurface; + +static const struct NVOC_RTTI __nvoc_rtti_SemaphoreSurface_SemaphoreSurface = { + /*pClassDef=*/ &__nvoc_class_def_SemaphoreSurface, + /*dtor=*/ (NVOC_DYNAMIC_DTOR) &__nvoc_dtor_SemaphoreSurface, + /*offset=*/ 0, +}; + +static const struct NVOC_RTTI __nvoc_rtti_SemaphoreSurface_Object = { + /*pClassDef=*/ &__nvoc_class_def_Object, + /*dtor=*/ &__nvoc_destructFromBase, + /*offset=*/ NV_OFFSETOF(SemaphoreSurface, __nvoc_base_GpuResource.__nvoc_base_RmResource.__nvoc_base_RsResource.__nvoc_base_Object), +}; + +static const struct NVOC_RTTI __nvoc_rtti_SemaphoreSurface_RsResource = { + /*pClassDef=*/ &__nvoc_class_def_RsResource, + /*dtor=*/ &__nvoc_destructFromBase, + /*offset=*/ NV_OFFSETOF(SemaphoreSurface, __nvoc_base_GpuResource.__nvoc_base_RmResource.__nvoc_base_RsResource), +}; + +static const struct NVOC_RTTI __nvoc_rtti_SemaphoreSurface_RmResourceCommon = { + /*pClassDef=*/ &__nvoc_class_def_RmResourceCommon, + /*dtor=*/ &__nvoc_destructFromBase, + /*offset=*/ NV_OFFSETOF(SemaphoreSurface, __nvoc_base_GpuResource.__nvoc_base_RmResource.__nvoc_base_RmResourceCommon), +}; + +static const struct NVOC_RTTI __nvoc_rtti_SemaphoreSurface_RmResource = { + /*pClassDef=*/ &__nvoc_class_def_RmResource, + /*dtor=*/ &__nvoc_destructFromBase, + /*offset=*/ NV_OFFSETOF(SemaphoreSurface, __nvoc_base_GpuResource.__nvoc_base_RmResource), +}; + +static const struct NVOC_RTTI __nvoc_rtti_SemaphoreSurface_GpuResource = { + /*pClassDef=*/ &__nvoc_class_def_GpuResource, + /*dtor=*/ &__nvoc_destructFromBase, + /*offset=*/ NV_OFFSETOF(SemaphoreSurface, __nvoc_base_GpuResource), +}; + +static const struct NVOC_CASTINFO __nvoc_castinfo_SemaphoreSurface = { + /*numRelatives=*/ 6, + /*relatives=*/ { + &__nvoc_rtti_SemaphoreSurface_SemaphoreSurface, + &__nvoc_rtti_SemaphoreSurface_GpuResource, + &__nvoc_rtti_SemaphoreSurface_RmResource, + &__nvoc_rtti_SemaphoreSurface_RmResourceCommon, + &__nvoc_rtti_SemaphoreSurface_RsResource, + &__nvoc_rtti_SemaphoreSurface_Object, + }, +}; + +const struct NVOC_CLASS_DEF __nvoc_class_def_SemaphoreSurface = +{ + /*classInfo=*/ { + /*size=*/ sizeof(SemaphoreSurface), + /*classId=*/ classId(SemaphoreSurface), + /*providerId=*/ &__nvoc_rtti_provider, +#if NV_PRINTF_STRINGS_ALLOWED + /*name=*/ "SemaphoreSurface", +#endif + }, + /*objCreatefn=*/ (NVOC_DYNAMIC_OBJ_CREATE) &__nvoc_objCreateDynamic_SemaphoreSurface, + /*pCastInfo=*/ &__nvoc_castinfo_SemaphoreSurface, + /*pExportInfo=*/ &__nvoc_export_info_SemaphoreSurface +}; + +static NvBool __nvoc_thunk_SemaphoreSurface_resCanCopy(struct RsResource *pSemSurf) { + return semsurfCanCopy((struct SemaphoreSurface *)(((unsigned char *)pSemSurf) - __nvoc_rtti_SemaphoreSurface_RsResource.offset)); +} + +static NvBool __nvoc_thunk_GpuResource_semsurfShareCallback(struct SemaphoreSurface *pGpuResource, struct RsClient *pInvokingClient, struct RsResourceRef *pParentRef, RS_SHARE_POLICY *pSharePolicy) { + return gpuresShareCallback((struct GpuResource *)(((unsigned char *)pGpuResource) + __nvoc_rtti_SemaphoreSurface_GpuResource.offset), pInvokingClient, pParentRef, pSharePolicy); +} + +static NV_STATUS __nvoc_thunk_RmResource_semsurfCheckMemInterUnmap(struct SemaphoreSurface *pRmResource, NvBool bSubdeviceHandleProvided) { + return rmresCheckMemInterUnmap((struct RmResource *)(((unsigned char *)pRmResource) + __nvoc_rtti_SemaphoreSurface_RmResource.offset), bSubdeviceHandleProvided); +} + +static NV_STATUS __nvoc_thunk_RsResource_semsurfMapTo(struct SemaphoreSurface *pResource, RS_RES_MAP_TO_PARAMS *pParams) { + return resMapTo((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_SemaphoreSurface_RsResource.offset), pParams); +} + +static NV_STATUS __nvoc_thunk_GpuResource_semsurfGetMapAddrSpace(struct SemaphoreSurface *pGpuResource, struct CALL_CONTEXT *pCallContext, NvU32 mapFlags, NV_ADDRESS_SPACE *pAddrSpace) { + return gpuresGetMapAddrSpace((struct GpuResource *)(((unsigned char *)pGpuResource) + __nvoc_rtti_SemaphoreSurface_GpuResource.offset), pCallContext, mapFlags, pAddrSpace); +} + +static NvU32 __nvoc_thunk_RsResource_semsurfGetRefCount(struct SemaphoreSurface *pResource) { + return resGetRefCount((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_SemaphoreSurface_RsResource.offset)); +} + +static void __nvoc_thunk_RsResource_semsurfAddAdditionalDependants(struct RsClient *pClient, struct SemaphoreSurface *pResource, RsResourceRef *pReference) { + resAddAdditionalDependants(pClient, (struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_SemaphoreSurface_RsResource.offset), pReference); +} + +static NV_STATUS __nvoc_thunk_RmResource_semsurfControl_Prologue(struct SemaphoreSurface *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return rmresControl_Prologue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_SemaphoreSurface_RmResource.offset), pCallContext, pParams); +} + +static NV_STATUS __nvoc_thunk_GpuResource_semsurfGetRegBaseOffsetAndSize(struct SemaphoreSurface *pGpuResource, struct OBJGPU *pGpu, NvU32 *pOffset, NvU32 *pSize) { + return gpuresGetRegBaseOffsetAndSize((struct GpuResource *)(((unsigned char *)pGpuResource) + __nvoc_rtti_SemaphoreSurface_GpuResource.offset), pGpu, pOffset, pSize); +} + +static NV_STATUS __nvoc_thunk_GpuResource_semsurfInternalControlForward(struct SemaphoreSurface *pGpuResource, NvU32 command, void *pParams, NvU32 size) { + return gpuresInternalControlForward((struct GpuResource *)(((unsigned char *)pGpuResource) + __nvoc_rtti_SemaphoreSurface_GpuResource.offset), command, pParams, size); +} + +static NV_STATUS __nvoc_thunk_RsResource_semsurfUnmapFrom(struct SemaphoreSurface *pResource, RS_RES_UNMAP_FROM_PARAMS *pParams) { + return resUnmapFrom((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_SemaphoreSurface_RsResource.offset), pParams); +} + +static void __nvoc_thunk_RmResource_semsurfControl_Epilogue(struct SemaphoreSurface *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + rmresControl_Epilogue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_SemaphoreSurface_RmResource.offset), pCallContext, pParams); +} + +static NV_STATUS __nvoc_thunk_RsResource_semsurfControlLookup(struct SemaphoreSurface *pResource, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams, const struct NVOC_EXPORTED_METHOD_DEF **ppEntry) { + return resControlLookup((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_SemaphoreSurface_RsResource.offset), pParams, ppEntry); +} + +static NvHandle __nvoc_thunk_GpuResource_semsurfGetInternalObjectHandle(struct SemaphoreSurface *pGpuResource) { + return gpuresGetInternalObjectHandle((struct GpuResource *)(((unsigned char *)pGpuResource) + __nvoc_rtti_SemaphoreSurface_GpuResource.offset)); +} + +static NV_STATUS __nvoc_thunk_GpuResource_semsurfControl(struct SemaphoreSurface *pGpuResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return gpuresControl((struct GpuResource *)(((unsigned char *)pGpuResource) + __nvoc_rtti_SemaphoreSurface_GpuResource.offset), pCallContext, pParams); +} + +static NV_STATUS __nvoc_thunk_GpuResource_semsurfUnmap(struct SemaphoreSurface *pGpuResource, struct CALL_CONTEXT *pCallContext, struct RsCpuMapping *pCpuMapping) { + return gpuresUnmap((struct GpuResource *)(((unsigned char *)pGpuResource) + __nvoc_rtti_SemaphoreSurface_GpuResource.offset), pCallContext, pCpuMapping); +} + +static NV_STATUS __nvoc_thunk_RmResource_semsurfGetMemInterMapParams(struct SemaphoreSurface *pRmResource, RMRES_MEM_INTER_MAP_PARAMS *pParams) { + return rmresGetMemInterMapParams((struct RmResource *)(((unsigned char *)pRmResource) + __nvoc_rtti_SemaphoreSurface_RmResource.offset), pParams); +} + +static NV_STATUS __nvoc_thunk_RmResource_semsurfGetMemoryMappingDescriptor(struct SemaphoreSurface *pRmResource, struct MEMORY_DESCRIPTOR **ppMemDesc) { + return rmresGetMemoryMappingDescriptor((struct RmResource *)(((unsigned char *)pRmResource) + __nvoc_rtti_SemaphoreSurface_RmResource.offset), ppMemDesc); +} + +static NV_STATUS __nvoc_thunk_RsResource_semsurfControlFilter(struct SemaphoreSurface *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return resControlFilter((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_SemaphoreSurface_RsResource.offset), pCallContext, pParams); +} + +static NV_STATUS __nvoc_thunk_RmResource_semsurfControlSerialization_Prologue(struct SemaphoreSurface *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return rmresControlSerialization_Prologue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_SemaphoreSurface_RmResource.offset), pCallContext, pParams); +} + +static void __nvoc_thunk_RsResource_semsurfPreDestruct(struct SemaphoreSurface *pResource) { + resPreDestruct((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_SemaphoreSurface_RsResource.offset)); +} + +static NV_STATUS __nvoc_thunk_RsResource_semsurfIsDuplicate(struct SemaphoreSurface *pResource, NvHandle hMemory, NvBool *pDuplicate) { + return resIsDuplicate((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_SemaphoreSurface_RsResource.offset), hMemory, pDuplicate); +} + +static void __nvoc_thunk_RmResource_semsurfControlSerialization_Epilogue(struct SemaphoreSurface *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + rmresControlSerialization_Epilogue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_SemaphoreSurface_RmResource.offset), pCallContext, pParams); +} + +static NV_STATUS __nvoc_thunk_GpuResource_semsurfMap(struct SemaphoreSurface *pGpuResource, struct CALL_CONTEXT *pCallContext, struct RS_CPU_MAP_PARAMS *pParams, struct RsCpuMapping *pCpuMapping) { + return gpuresMap((struct GpuResource *)(((unsigned char *)pGpuResource) + __nvoc_rtti_SemaphoreSurface_GpuResource.offset), pCallContext, pParams, pCpuMapping); +} + +static NvBool __nvoc_thunk_RmResource_semsurfAccessCallback(struct SemaphoreSurface *pResource, struct RsClient *pInvokingClient, void *pAllocParams, RsAccessRight accessRight) { + return rmresAccessCallback((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_SemaphoreSurface_RmResource.offset), pInvokingClient, pAllocParams, accessRight); +} + +#if !defined(NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG) +#define NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(x) (0) +#endif + +static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_SemaphoreSurface[] = +{ + { /* [0] */ +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) + /*pFunc=*/ (void (*)(void)) NULL, +#else + /*pFunc=*/ (void (*)(void)) semsurfCtrlCmdRefMemory_IMPL, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) + /*flags=*/ 0x10u, + /*accessRight=*/0x0u, + /*methodId=*/ 0xda0001u, + /*paramSize=*/ sizeof(NV_SEMAPHORE_SURFACE_CTRL_REF_MEMORY_PARAMS), + /*pClassInfo=*/ &(__nvoc_class_def_SemaphoreSurface.classInfo), +#if NV_PRINTF_STRINGS_ALLOWED + /*func=*/ "semsurfCtrlCmdRefMemory" +#endif + }, + { /* [1] */ +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x810u) + /*pFunc=*/ (void (*)(void)) NULL, +#else + /*pFunc=*/ (void (*)(void)) semsurfCtrlCmdBindChannel_IMPL, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x810u) + /*flags=*/ 0x810u, + /*accessRight=*/0x0u, + /*methodId=*/ 0xda0002u, + /*paramSize=*/ sizeof(NV_SEMAPHORE_SURFACE_CTRL_BIND_CHANNEL_PARAMS), + /*pClassInfo=*/ &(__nvoc_class_def_SemaphoreSurface.classInfo), +#if NV_PRINTF_STRINGS_ALLOWED + /*func=*/ "semsurfCtrlCmdBindChannel" +#endif + }, + { /* [2] */ +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x811u) + /*pFunc=*/ (void (*)(void)) NULL, +#else + /*pFunc=*/ (void (*)(void)) semsurfCtrlCmdRegisterWaiter_IMPL, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x811u) + /*flags=*/ 0x811u, + /*accessRight=*/0x0u, + /*methodId=*/ 0xda0003u, + /*paramSize=*/ sizeof(NV_SEMAPHORE_SURFACE_CTRL_REGISTER_WAITER_PARAMS), + /*pClassInfo=*/ &(__nvoc_class_def_SemaphoreSurface.classInfo), +#if NV_PRINTF_STRINGS_ALLOWED + /*func=*/ "semsurfCtrlCmdRegisterWaiter" +#endif + }, + { /* [3] */ +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x811u) + /*pFunc=*/ (void (*)(void)) NULL, +#else + /*pFunc=*/ (void (*)(void)) semsurfCtrlCmdSetValue_IMPL, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x811u) + /*flags=*/ 0x811u, + /*accessRight=*/0x0u, + /*methodId=*/ 0xda0004u, + /*paramSize=*/ sizeof(NV_SEMAPHORE_SURFACE_CTRL_SET_VALUE_PARAMS), + /*pClassInfo=*/ &(__nvoc_class_def_SemaphoreSurface.classInfo), +#if NV_PRINTF_STRINGS_ALLOWED + /*func=*/ "semsurfCtrlCmdSetValue" +#endif + }, + { /* [4] */ +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x811u) + /*pFunc=*/ (void (*)(void)) NULL, +#else + /*pFunc=*/ (void (*)(void)) semsurfCtrlCmdUnregisterWaiter_IMPL, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x811u) + /*flags=*/ 0x811u, + /*accessRight=*/0x0u, + /*methodId=*/ 0xda0005u, + /*paramSize=*/ sizeof(NV_SEMAPHORE_SURFACE_CTRL_UNREGISTER_WAITER_PARAMS), + /*pClassInfo=*/ &(__nvoc_class_def_SemaphoreSurface.classInfo), +#if NV_PRINTF_STRINGS_ALLOWED + /*func=*/ "semsurfCtrlCmdUnregisterWaiter" +#endif + }, + +}; + +const struct NVOC_EXPORT_INFO __nvoc_export_info_SemaphoreSurface = +{ + /*numEntries=*/ 5, + /*pExportEntries=*/ __nvoc_exported_method_def_SemaphoreSurface +}; + +void __nvoc_dtor_GpuResource(GpuResource*); +void __nvoc_dtor_SemaphoreSurface(SemaphoreSurface *pThis) { + __nvoc_semsurfDestruct(pThis); + __nvoc_dtor_GpuResource(&pThis->__nvoc_base_GpuResource); + PORT_UNREFERENCED_VARIABLE(pThis); +} + +void __nvoc_init_dataField_SemaphoreSurface(SemaphoreSurface *pThis) { + PORT_UNREFERENCED_VARIABLE(pThis); +} + +NV_STATUS __nvoc_ctor_GpuResource(GpuResource* , CALL_CONTEXT *, struct RS_RES_ALLOC_PARAMS_INTERNAL *); +NV_STATUS __nvoc_ctor_SemaphoreSurface(SemaphoreSurface *pThis, CALL_CONTEXT * arg_pCallContext, struct RS_RES_ALLOC_PARAMS_INTERNAL * arg_pParams) { + NV_STATUS status = NV_OK; + status = __nvoc_ctor_GpuResource(&pThis->__nvoc_base_GpuResource, arg_pCallContext, arg_pParams); + if (status != NV_OK) goto __nvoc_ctor_SemaphoreSurface_fail_GpuResource; + __nvoc_init_dataField_SemaphoreSurface(pThis); + + status = __nvoc_semsurfConstruct(pThis, arg_pCallContext, arg_pParams); + if (status != NV_OK) goto __nvoc_ctor_SemaphoreSurface_fail__init; + goto __nvoc_ctor_SemaphoreSurface_exit; // Success + +__nvoc_ctor_SemaphoreSurface_fail__init: + __nvoc_dtor_GpuResource(&pThis->__nvoc_base_GpuResource); +__nvoc_ctor_SemaphoreSurface_fail_GpuResource: +__nvoc_ctor_SemaphoreSurface_exit: + + return status; +} + +static void __nvoc_init_funcTable_SemaphoreSurface_1(SemaphoreSurface *pThis) { + PORT_UNREFERENCED_VARIABLE(pThis); + + pThis->__semsurfCanCopy__ = &semsurfCanCopy_0c883b; + +#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) + pThis->__semsurfCtrlCmdRefMemory__ = &semsurfCtrlCmdRefMemory_IMPL; +#endif + +#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x810u) + pThis->__semsurfCtrlCmdBindChannel__ = &semsurfCtrlCmdBindChannel_IMPL; +#endif + +#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x811u) + pThis->__semsurfCtrlCmdRegisterWaiter__ = &semsurfCtrlCmdRegisterWaiter_IMPL; +#endif + +#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x811u) + pThis->__semsurfCtrlCmdSetValue__ = &semsurfCtrlCmdSetValue_IMPL; +#endif + +#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x811u) + pThis->__semsurfCtrlCmdUnregisterWaiter__ = &semsurfCtrlCmdUnregisterWaiter_IMPL; +#endif + + pThis->__nvoc_base_GpuResource.__nvoc_base_RmResource.__nvoc_base_RsResource.__resCanCopy__ = &__nvoc_thunk_SemaphoreSurface_resCanCopy; + + pThis->__semsurfShareCallback__ = &__nvoc_thunk_GpuResource_semsurfShareCallback; + + pThis->__semsurfCheckMemInterUnmap__ = &__nvoc_thunk_RmResource_semsurfCheckMemInterUnmap; + + pThis->__semsurfMapTo__ = &__nvoc_thunk_RsResource_semsurfMapTo; + + pThis->__semsurfGetMapAddrSpace__ = &__nvoc_thunk_GpuResource_semsurfGetMapAddrSpace; + + pThis->__semsurfGetRefCount__ = &__nvoc_thunk_RsResource_semsurfGetRefCount; + + pThis->__semsurfAddAdditionalDependants__ = &__nvoc_thunk_RsResource_semsurfAddAdditionalDependants; + + pThis->__semsurfControl_Prologue__ = &__nvoc_thunk_RmResource_semsurfControl_Prologue; + + pThis->__semsurfGetRegBaseOffsetAndSize__ = &__nvoc_thunk_GpuResource_semsurfGetRegBaseOffsetAndSize; + + pThis->__semsurfInternalControlForward__ = &__nvoc_thunk_GpuResource_semsurfInternalControlForward; + + pThis->__semsurfUnmapFrom__ = &__nvoc_thunk_RsResource_semsurfUnmapFrom; + + pThis->__semsurfControl_Epilogue__ = &__nvoc_thunk_RmResource_semsurfControl_Epilogue; + + pThis->__semsurfControlLookup__ = &__nvoc_thunk_RsResource_semsurfControlLookup; + + pThis->__semsurfGetInternalObjectHandle__ = &__nvoc_thunk_GpuResource_semsurfGetInternalObjectHandle; + + pThis->__semsurfControl__ = &__nvoc_thunk_GpuResource_semsurfControl; + + pThis->__semsurfUnmap__ = &__nvoc_thunk_GpuResource_semsurfUnmap; + + pThis->__semsurfGetMemInterMapParams__ = &__nvoc_thunk_RmResource_semsurfGetMemInterMapParams; + + pThis->__semsurfGetMemoryMappingDescriptor__ = &__nvoc_thunk_RmResource_semsurfGetMemoryMappingDescriptor; + + pThis->__semsurfControlFilter__ = &__nvoc_thunk_RsResource_semsurfControlFilter; + + pThis->__semsurfControlSerialization_Prologue__ = &__nvoc_thunk_RmResource_semsurfControlSerialization_Prologue; + + pThis->__semsurfPreDestruct__ = &__nvoc_thunk_RsResource_semsurfPreDestruct; + + pThis->__semsurfIsDuplicate__ = &__nvoc_thunk_RsResource_semsurfIsDuplicate; + + pThis->__semsurfControlSerialization_Epilogue__ = &__nvoc_thunk_RmResource_semsurfControlSerialization_Epilogue; + + pThis->__semsurfMap__ = &__nvoc_thunk_GpuResource_semsurfMap; + + pThis->__semsurfAccessCallback__ = &__nvoc_thunk_RmResource_semsurfAccessCallback; +} + +void __nvoc_init_funcTable_SemaphoreSurface(SemaphoreSurface *pThis) { + __nvoc_init_funcTable_SemaphoreSurface_1(pThis); +} + +void __nvoc_init_GpuResource(GpuResource*); +void __nvoc_init_SemaphoreSurface(SemaphoreSurface *pThis) { + pThis->__nvoc_pbase_SemaphoreSurface = pThis; + pThis->__nvoc_pbase_Object = &pThis->__nvoc_base_GpuResource.__nvoc_base_RmResource.__nvoc_base_RsResource.__nvoc_base_Object; + pThis->__nvoc_pbase_RsResource = &pThis->__nvoc_base_GpuResource.__nvoc_base_RmResource.__nvoc_base_RsResource; + pThis->__nvoc_pbase_RmResourceCommon = &pThis->__nvoc_base_GpuResource.__nvoc_base_RmResource.__nvoc_base_RmResourceCommon; + pThis->__nvoc_pbase_RmResource = &pThis->__nvoc_base_GpuResource.__nvoc_base_RmResource; + pThis->__nvoc_pbase_GpuResource = &pThis->__nvoc_base_GpuResource; + __nvoc_init_GpuResource(&pThis->__nvoc_base_GpuResource); + __nvoc_init_funcTable_SemaphoreSurface(pThis); +} + +NV_STATUS __nvoc_objCreate_SemaphoreSurface(SemaphoreSurface **ppThis, Dynamic *pParent, NvU32 createFlags, CALL_CONTEXT * arg_pCallContext, struct RS_RES_ALLOC_PARAMS_INTERNAL * arg_pParams) { + NV_STATUS status; + Object *pParentObj; + SemaphoreSurface *pThis; + + status = __nvoc_handleObjCreateMemAlloc(createFlags, sizeof(SemaphoreSurface), (void**)&pThis, (void**)ppThis); + if (status != NV_OK) + return status; + + portMemSet(pThis, 0, sizeof(SemaphoreSurface)); + + __nvoc_initRtti(staticCast(pThis, Dynamic), &__nvoc_class_def_SemaphoreSurface); + + pThis->__nvoc_base_GpuResource.__nvoc_base_RmResource.__nvoc_base_RsResource.__nvoc_base_Object.createFlags = createFlags; + + if (pParent != NULL && !(createFlags & NVOC_OBJ_CREATE_FLAGS_PARENT_HALSPEC_ONLY)) + { + pParentObj = dynamicCast(pParent, Object); + objAddChild(pParentObj, &pThis->__nvoc_base_GpuResource.__nvoc_base_RmResource.__nvoc_base_RsResource.__nvoc_base_Object); + } + else + { + pThis->__nvoc_base_GpuResource.__nvoc_base_RmResource.__nvoc_base_RsResource.__nvoc_base_Object.pParent = NULL; + } + + __nvoc_init_SemaphoreSurface(pThis); + status = __nvoc_ctor_SemaphoreSurface(pThis, arg_pCallContext, arg_pParams); + if (status != NV_OK) goto __nvoc_objCreate_SemaphoreSurface_cleanup; + + *ppThis = pThis; + + return NV_OK; + +__nvoc_objCreate_SemaphoreSurface_cleanup: + // do not call destructors here since the constructor already called them + if (createFlags & NVOC_OBJ_CREATE_FLAGS_IN_PLACE_CONSTRUCT) + portMemSet(pThis, 0, sizeof(SemaphoreSurface)); + else + portMemFree(pThis); + + // coverity[leaked_storage:FALSE] + return status; +} + +NV_STATUS __nvoc_objCreateDynamic_SemaphoreSurface(SemaphoreSurface **ppThis, Dynamic *pParent, NvU32 createFlags, va_list args) { + NV_STATUS status; + CALL_CONTEXT * arg_pCallContext = va_arg(args, CALL_CONTEXT *); + struct RS_RES_ALLOC_PARAMS_INTERNAL * arg_pParams = va_arg(args, struct RS_RES_ALLOC_PARAMS_INTERNAL *); + + status = __nvoc_objCreate_SemaphoreSurface(ppThis, pParent, createFlags, arg_pCallContext, arg_pParams); + + return status; +} + diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/generated/g_sem_surf_nvoc.h nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_sem_surf_nvoc.h --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/generated/g_sem_surf_nvoc.h 1970-01-01 00:00:00.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_sem_surf_nvoc.h 2024-03-05 22:18:45.000000000 +0000 @@ -0,0 +1,363 @@ +#ifndef _G_SEM_SURF_NVOC_H_ +#define _G_SEM_SURF_NVOC_H_ +#include "nvoc/runtime.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/* + * SPDX-FileCopyrightText: Copyright (c) 2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#include "g_sem_surf_nvoc.h" + +#ifndef SEM_SURF_H +#define SEM_SURF_H + +#include "gpu/gpu_resource.h" // GpuResource +#include "mem_mgr/mem.h" +#include "rmapi/event.h" // EVENTNOTIFICATION + +#include "class/cl00da.h" // NV_SEMAPHORE_SURFACE +#include "ctrl/ctrl00da.h" // NV_SEMAPHORE_SURFACE_CTRL_* +#include "ctrl/ctrl2080/ctrl2080fb.h" // NV2080_CTRL_FB_GET_SEMAPHORE_SURFACE_LAYOUT_PARAMS + +typedef struct { + /* Value being waited for by pListeners list */ + NvU64 value; + + /* Value to set the semaphore to after wait value is reached */ + NvU64 newValue; + + /* Index of this value listener in the semaphore surface */ + NvU64 index; + + /* List of listeners waiting for the value */ + EVENTNOTIFICATION *pListeners; + + ListNode valueListEntry; + ListNode pendingNotificationsEntry; +} SEM_VALUE_LISTENERS_NODE; + +MAKE_INTRUSIVE_LIST(SEM_VALUE_LISTENERS, SEM_VALUE_LISTENERS_NODE, valueListEntry); +MAKE_INTRUSIVE_LIST(SEM_PENDING_NOTIFICATIONS, SEM_VALUE_LISTENERS_NODE, pendingNotificationsEntry); + +typedef struct { + /* List of values being listened for at this index, ordered by value. */ + SEM_VALUE_LISTENERS listeners; + + MapNode node; +} SEM_INDEX_LISTENERS_NODE; + +MAKE_INTRUSIVE_MAP(SEM_INDEX_LISTENERS, + SEM_INDEX_LISTENERS_NODE, + node); + +typedef struct { + PORT_SPINLOCK *pSpinlock; + + /* Internal interrupt handler callback data */ + NvHandle hClient; + NvHandle hDevice; + NvHandle hSubDevice; + NvHandle hSemaphoreMem; + NvHandle hMaxSubmittedMem; + NvHandle hEvent; + NVOS10_EVENT_KERNEL_CALLBACK_EX callback; + + /* The client-mappable semaphore memory region and associated data */ + NV2080_CTRL_FB_GET_SEMAPHORE_SURFACE_LAYOUT_PARAMS layout; + struct Memory* pSemaphoreMem; + struct Memory* pMaxSubmittedMem; + NvP64 semKernAddr; + NvP64 maxSubmittedKernAddr; + NvU8 *pSem; + NvU8 *pMaxSubmitted; + + /* Client active CPU waiters list XXX Should be per (offset,value) pair */ + SEM_INDEX_LISTENERS listenerMap; + + /* Number of semaphore surface objects sharing this data */ + NvU32 refCount; + + /* True if this semaphore surface supports 64-bit semaphores */ + NvBool bIs64Bit; + + /* True if the GPU supports conditional traps/monitored fence */ + NvBool bHasMonitoredFence; +} SEM_SHARED_DATA; + +#ifdef NVOC_SEM_SURF_H_PRIVATE_ACCESS_ALLOWED +#define PRIVATE_FIELD(x) x +#else +#define PRIVATE_FIELD(x) NVOC_PRIVATE_FIELD(x) +#endif +struct SemaphoreSurface { + const struct NVOC_RTTI *__nvoc_rtti; + struct GpuResource __nvoc_base_GpuResource; + struct Object *__nvoc_pbase_Object; + struct RsResource *__nvoc_pbase_RsResource; + struct RmResourceCommon *__nvoc_pbase_RmResourceCommon; + struct RmResource *__nvoc_pbase_RmResource; + struct GpuResource *__nvoc_pbase_GpuResource; + struct SemaphoreSurface *__nvoc_pbase_SemaphoreSurface; + NvBool (*__semsurfCanCopy__)(struct SemaphoreSurface *); + NV_STATUS (*__semsurfCtrlCmdRefMemory__)(struct SemaphoreSurface *, NV_SEMAPHORE_SURFACE_CTRL_REF_MEMORY_PARAMS *); + NV_STATUS (*__semsurfCtrlCmdBindChannel__)(struct SemaphoreSurface *, NV_SEMAPHORE_SURFACE_CTRL_BIND_CHANNEL_PARAMS *); + NV_STATUS (*__semsurfCtrlCmdRegisterWaiter__)(struct SemaphoreSurface *, NV_SEMAPHORE_SURFACE_CTRL_REGISTER_WAITER_PARAMS *); + NV_STATUS (*__semsurfCtrlCmdSetValue__)(struct SemaphoreSurface *, NV_SEMAPHORE_SURFACE_CTRL_SET_VALUE_PARAMS *); + NV_STATUS (*__semsurfCtrlCmdUnregisterWaiter__)(struct SemaphoreSurface *, NV_SEMAPHORE_SURFACE_CTRL_UNREGISTER_WAITER_PARAMS *); + NvBool (*__semsurfShareCallback__)(struct SemaphoreSurface *, struct RsClient *, struct RsResourceRef *, RS_SHARE_POLICY *); + NV_STATUS (*__semsurfCheckMemInterUnmap__)(struct SemaphoreSurface *, NvBool); + NV_STATUS (*__semsurfMapTo__)(struct SemaphoreSurface *, RS_RES_MAP_TO_PARAMS *); + NV_STATUS (*__semsurfGetMapAddrSpace__)(struct SemaphoreSurface *, struct CALL_CONTEXT *, NvU32, NV_ADDRESS_SPACE *); + NvU32 (*__semsurfGetRefCount__)(struct SemaphoreSurface *); + void (*__semsurfAddAdditionalDependants__)(struct RsClient *, struct SemaphoreSurface *, RsResourceRef *); + NV_STATUS (*__semsurfControl_Prologue__)(struct SemaphoreSurface *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); + NV_STATUS (*__semsurfGetRegBaseOffsetAndSize__)(struct SemaphoreSurface *, struct OBJGPU *, NvU32 *, NvU32 *); + NV_STATUS (*__semsurfInternalControlForward__)(struct SemaphoreSurface *, NvU32, void *, NvU32); + NV_STATUS (*__semsurfUnmapFrom__)(struct SemaphoreSurface *, RS_RES_UNMAP_FROM_PARAMS *); + void (*__semsurfControl_Epilogue__)(struct SemaphoreSurface *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); + NV_STATUS (*__semsurfControlLookup__)(struct SemaphoreSurface *, struct RS_RES_CONTROL_PARAMS_INTERNAL *, const struct NVOC_EXPORTED_METHOD_DEF **); + NvHandle (*__semsurfGetInternalObjectHandle__)(struct SemaphoreSurface *); + NV_STATUS (*__semsurfControl__)(struct SemaphoreSurface *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); + NV_STATUS (*__semsurfUnmap__)(struct SemaphoreSurface *, struct CALL_CONTEXT *, struct RsCpuMapping *); + NV_STATUS (*__semsurfGetMemInterMapParams__)(struct SemaphoreSurface *, RMRES_MEM_INTER_MAP_PARAMS *); + NV_STATUS (*__semsurfGetMemoryMappingDescriptor__)(struct SemaphoreSurface *, struct MEMORY_DESCRIPTOR **); + NV_STATUS (*__semsurfControlFilter__)(struct SemaphoreSurface *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); + NV_STATUS (*__semsurfControlSerialization_Prologue__)(struct SemaphoreSurface *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); + void (*__semsurfPreDestruct__)(struct SemaphoreSurface *); + NV_STATUS (*__semsurfIsDuplicate__)(struct SemaphoreSurface *, NvHandle, NvBool *); + void (*__semsurfControlSerialization_Epilogue__)(struct SemaphoreSurface *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); + NV_STATUS (*__semsurfMap__)(struct SemaphoreSurface *, struct CALL_CONTEXT *, struct RS_CPU_MAP_PARAMS *, struct RsCpuMapping *); + NvBool (*__semsurfAccessCallback__)(struct SemaphoreSurface *, struct RsClient *, void *, RsAccessRight); + SEM_SHARED_DATA *pShared; +}; + +#ifndef __NVOC_CLASS_SemaphoreSurface_TYPEDEF__ +#define __NVOC_CLASS_SemaphoreSurface_TYPEDEF__ +typedef struct SemaphoreSurface SemaphoreSurface; +#endif /* __NVOC_CLASS_SemaphoreSurface_TYPEDEF__ */ + +#ifndef __nvoc_class_id_SemaphoreSurface +#define __nvoc_class_id_SemaphoreSurface 0xeabc69 +#endif /* __nvoc_class_id_SemaphoreSurface */ + +extern const struct NVOC_CLASS_DEF __nvoc_class_def_SemaphoreSurface; + +#define __staticCast_SemaphoreSurface(pThis) \ + ((pThis)->__nvoc_pbase_SemaphoreSurface) + +#ifdef __nvoc_sem_surf_h_disabled +#define __dynamicCast_SemaphoreSurface(pThis) ((SemaphoreSurface*)NULL) +#else //__nvoc_sem_surf_h_disabled +#define __dynamicCast_SemaphoreSurface(pThis) \ + ((SemaphoreSurface*)__nvoc_dynamicCast(staticCast((pThis), Dynamic), classInfo(SemaphoreSurface))) +#endif //__nvoc_sem_surf_h_disabled + + +NV_STATUS __nvoc_objCreateDynamic_SemaphoreSurface(SemaphoreSurface**, Dynamic*, NvU32, va_list); + +NV_STATUS __nvoc_objCreate_SemaphoreSurface(SemaphoreSurface**, Dynamic*, NvU32, CALL_CONTEXT * arg_pCallContext, struct RS_RES_ALLOC_PARAMS_INTERNAL * arg_pParams); +#define __objCreate_SemaphoreSurface(ppNewObj, pParent, createFlags, arg_pCallContext, arg_pParams) \ + __nvoc_objCreate_SemaphoreSurface((ppNewObj), staticCast((pParent), Dynamic), (createFlags), arg_pCallContext, arg_pParams) + +#define semsurfCanCopy(pSemSurf) semsurfCanCopy_DISPATCH(pSemSurf) +#define semsurfCtrlCmdRefMemory(pSemaphoreSurf, pParams) semsurfCtrlCmdRefMemory_DISPATCH(pSemaphoreSurf, pParams) +#define semsurfCtrlCmdBindChannel(pSemaphoreSurf, pParams) semsurfCtrlCmdBindChannel_DISPATCH(pSemaphoreSurf, pParams) +#define semsurfCtrlCmdRegisterWaiter(pSemaphoreSurf, pParams) semsurfCtrlCmdRegisterWaiter_DISPATCH(pSemaphoreSurf, pParams) +#define semsurfCtrlCmdSetValue(pSemaphoreSurf, pParams) semsurfCtrlCmdSetValue_DISPATCH(pSemaphoreSurf, pParams) +#define semsurfCtrlCmdUnregisterWaiter(pSemaphoreSurf, pParams) semsurfCtrlCmdUnregisterWaiter_DISPATCH(pSemaphoreSurf, pParams) +#define semsurfShareCallback(pGpuResource, pInvokingClient, pParentRef, pSharePolicy) semsurfShareCallback_DISPATCH(pGpuResource, pInvokingClient, pParentRef, pSharePolicy) +#define semsurfCheckMemInterUnmap(pRmResource, bSubdeviceHandleProvided) semsurfCheckMemInterUnmap_DISPATCH(pRmResource, bSubdeviceHandleProvided) +#define semsurfMapTo(pResource, pParams) semsurfMapTo_DISPATCH(pResource, pParams) +#define semsurfGetMapAddrSpace(pGpuResource, pCallContext, mapFlags, pAddrSpace) semsurfGetMapAddrSpace_DISPATCH(pGpuResource, pCallContext, mapFlags, pAddrSpace) +#define semsurfGetRefCount(pResource) semsurfGetRefCount_DISPATCH(pResource) +#define semsurfAddAdditionalDependants(pClient, pResource, pReference) semsurfAddAdditionalDependants_DISPATCH(pClient, pResource, pReference) +#define semsurfControl_Prologue(pResource, pCallContext, pParams) semsurfControl_Prologue_DISPATCH(pResource, pCallContext, pParams) +#define semsurfGetRegBaseOffsetAndSize(pGpuResource, pGpu, pOffset, pSize) semsurfGetRegBaseOffsetAndSize_DISPATCH(pGpuResource, pGpu, pOffset, pSize) +#define semsurfInternalControlForward(pGpuResource, command, pParams, size) semsurfInternalControlForward_DISPATCH(pGpuResource, command, pParams, size) +#define semsurfUnmapFrom(pResource, pParams) semsurfUnmapFrom_DISPATCH(pResource, pParams) +#define semsurfControl_Epilogue(pResource, pCallContext, pParams) semsurfControl_Epilogue_DISPATCH(pResource, pCallContext, pParams) +#define semsurfControlLookup(pResource, pParams, ppEntry) semsurfControlLookup_DISPATCH(pResource, pParams, ppEntry) +#define semsurfGetInternalObjectHandle(pGpuResource) semsurfGetInternalObjectHandle_DISPATCH(pGpuResource) +#define semsurfControl(pGpuResource, pCallContext, pParams) semsurfControl_DISPATCH(pGpuResource, pCallContext, pParams) +#define semsurfUnmap(pGpuResource, pCallContext, pCpuMapping) semsurfUnmap_DISPATCH(pGpuResource, pCallContext, pCpuMapping) +#define semsurfGetMemInterMapParams(pRmResource, pParams) semsurfGetMemInterMapParams_DISPATCH(pRmResource, pParams) +#define semsurfGetMemoryMappingDescriptor(pRmResource, ppMemDesc) semsurfGetMemoryMappingDescriptor_DISPATCH(pRmResource, ppMemDesc) +#define semsurfControlFilter(pResource, pCallContext, pParams) semsurfControlFilter_DISPATCH(pResource, pCallContext, pParams) +#define semsurfControlSerialization_Prologue(pResource, pCallContext, pParams) semsurfControlSerialization_Prologue_DISPATCH(pResource, pCallContext, pParams) +#define semsurfPreDestruct(pResource) semsurfPreDestruct_DISPATCH(pResource) +#define semsurfIsDuplicate(pResource, hMemory, pDuplicate) semsurfIsDuplicate_DISPATCH(pResource, hMemory, pDuplicate) +#define semsurfControlSerialization_Epilogue(pResource, pCallContext, pParams) semsurfControlSerialization_Epilogue_DISPATCH(pResource, pCallContext, pParams) +#define semsurfMap(pGpuResource, pCallContext, pParams, pCpuMapping) semsurfMap_DISPATCH(pGpuResource, pCallContext, pParams, pCpuMapping) +#define semsurfAccessCallback(pResource, pInvokingClient, pAllocParams, accessRight) semsurfAccessCallback_DISPATCH(pResource, pInvokingClient, pAllocParams, accessRight) +static inline NvBool semsurfCanCopy_0c883b(struct SemaphoreSurface *pSemSurf) { + return ((NvBool)(0 == 0)); +} + +static inline NvBool semsurfCanCopy_DISPATCH(struct SemaphoreSurface *pSemSurf) { + return pSemSurf->__semsurfCanCopy__(pSemSurf); +} + +NV_STATUS semsurfCtrlCmdRefMemory_IMPL(struct SemaphoreSurface *pSemaphoreSurf, NV_SEMAPHORE_SURFACE_CTRL_REF_MEMORY_PARAMS *pParams); + +static inline NV_STATUS semsurfCtrlCmdRefMemory_DISPATCH(struct SemaphoreSurface *pSemaphoreSurf, NV_SEMAPHORE_SURFACE_CTRL_REF_MEMORY_PARAMS *pParams) { + return pSemaphoreSurf->__semsurfCtrlCmdRefMemory__(pSemaphoreSurf, pParams); +} + +NV_STATUS semsurfCtrlCmdBindChannel_IMPL(struct SemaphoreSurface *pSemaphoreSurf, NV_SEMAPHORE_SURFACE_CTRL_BIND_CHANNEL_PARAMS *pParams); + +static inline NV_STATUS semsurfCtrlCmdBindChannel_DISPATCH(struct SemaphoreSurface *pSemaphoreSurf, NV_SEMAPHORE_SURFACE_CTRL_BIND_CHANNEL_PARAMS *pParams) { + return pSemaphoreSurf->__semsurfCtrlCmdBindChannel__(pSemaphoreSurf, pParams); +} + +NV_STATUS semsurfCtrlCmdRegisterWaiter_IMPL(struct SemaphoreSurface *pSemaphoreSurf, NV_SEMAPHORE_SURFACE_CTRL_REGISTER_WAITER_PARAMS *pParams); + +static inline NV_STATUS semsurfCtrlCmdRegisterWaiter_DISPATCH(struct SemaphoreSurface *pSemaphoreSurf, NV_SEMAPHORE_SURFACE_CTRL_REGISTER_WAITER_PARAMS *pParams) { + return pSemaphoreSurf->__semsurfCtrlCmdRegisterWaiter__(pSemaphoreSurf, pParams); +} + +NV_STATUS semsurfCtrlCmdSetValue_IMPL(struct SemaphoreSurface *pSemaphoreSurf, NV_SEMAPHORE_SURFACE_CTRL_SET_VALUE_PARAMS *pParams); + +static inline NV_STATUS semsurfCtrlCmdSetValue_DISPATCH(struct SemaphoreSurface *pSemaphoreSurf, NV_SEMAPHORE_SURFACE_CTRL_SET_VALUE_PARAMS *pParams) { + return pSemaphoreSurf->__semsurfCtrlCmdSetValue__(pSemaphoreSurf, pParams); +} + +NV_STATUS semsurfCtrlCmdUnregisterWaiter_IMPL(struct SemaphoreSurface *pSemaphoreSurf, NV_SEMAPHORE_SURFACE_CTRL_UNREGISTER_WAITER_PARAMS *pParams); + +static inline NV_STATUS semsurfCtrlCmdUnregisterWaiter_DISPATCH(struct SemaphoreSurface *pSemaphoreSurf, NV_SEMAPHORE_SURFACE_CTRL_UNREGISTER_WAITER_PARAMS *pParams) { + return pSemaphoreSurf->__semsurfCtrlCmdUnregisterWaiter__(pSemaphoreSurf, pParams); +} + +static inline NvBool semsurfShareCallback_DISPATCH(struct SemaphoreSurface *pGpuResource, struct RsClient *pInvokingClient, struct RsResourceRef *pParentRef, RS_SHARE_POLICY *pSharePolicy) { + return pGpuResource->__semsurfShareCallback__(pGpuResource, pInvokingClient, pParentRef, pSharePolicy); +} + +static inline NV_STATUS semsurfCheckMemInterUnmap_DISPATCH(struct SemaphoreSurface *pRmResource, NvBool bSubdeviceHandleProvided) { + return pRmResource->__semsurfCheckMemInterUnmap__(pRmResource, bSubdeviceHandleProvided); +} + +static inline NV_STATUS semsurfMapTo_DISPATCH(struct SemaphoreSurface *pResource, RS_RES_MAP_TO_PARAMS *pParams) { + return pResource->__semsurfMapTo__(pResource, pParams); +} + +static inline NV_STATUS semsurfGetMapAddrSpace_DISPATCH(struct SemaphoreSurface *pGpuResource, struct CALL_CONTEXT *pCallContext, NvU32 mapFlags, NV_ADDRESS_SPACE *pAddrSpace) { + return pGpuResource->__semsurfGetMapAddrSpace__(pGpuResource, pCallContext, mapFlags, pAddrSpace); +} + +static inline NvU32 semsurfGetRefCount_DISPATCH(struct SemaphoreSurface *pResource) { + return pResource->__semsurfGetRefCount__(pResource); +} + +static inline void semsurfAddAdditionalDependants_DISPATCH(struct RsClient *pClient, struct SemaphoreSurface *pResource, RsResourceRef *pReference) { + pResource->__semsurfAddAdditionalDependants__(pClient, pResource, pReference); +} + +static inline NV_STATUS semsurfControl_Prologue_DISPATCH(struct SemaphoreSurface *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return pResource->__semsurfControl_Prologue__(pResource, pCallContext, pParams); +} + +static inline NV_STATUS semsurfGetRegBaseOffsetAndSize_DISPATCH(struct SemaphoreSurface *pGpuResource, struct OBJGPU *pGpu, NvU32 *pOffset, NvU32 *pSize) { + return pGpuResource->__semsurfGetRegBaseOffsetAndSize__(pGpuResource, pGpu, pOffset, pSize); +} + +static inline NV_STATUS semsurfInternalControlForward_DISPATCH(struct SemaphoreSurface *pGpuResource, NvU32 command, void *pParams, NvU32 size) { + return pGpuResource->__semsurfInternalControlForward__(pGpuResource, command, pParams, size); +} + +static inline NV_STATUS semsurfUnmapFrom_DISPATCH(struct SemaphoreSurface *pResource, RS_RES_UNMAP_FROM_PARAMS *pParams) { + return pResource->__semsurfUnmapFrom__(pResource, pParams); +} + +static inline void semsurfControl_Epilogue_DISPATCH(struct SemaphoreSurface *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + pResource->__semsurfControl_Epilogue__(pResource, pCallContext, pParams); +} + +static inline NV_STATUS semsurfControlLookup_DISPATCH(struct SemaphoreSurface *pResource, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams, const struct NVOC_EXPORTED_METHOD_DEF **ppEntry) { + return pResource->__semsurfControlLookup__(pResource, pParams, ppEntry); +} + +static inline NvHandle semsurfGetInternalObjectHandle_DISPATCH(struct SemaphoreSurface *pGpuResource) { + return pGpuResource->__semsurfGetInternalObjectHandle__(pGpuResource); +} + +static inline NV_STATUS semsurfControl_DISPATCH(struct SemaphoreSurface *pGpuResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return pGpuResource->__semsurfControl__(pGpuResource, pCallContext, pParams); +} + +static inline NV_STATUS semsurfUnmap_DISPATCH(struct SemaphoreSurface *pGpuResource, struct CALL_CONTEXT *pCallContext, struct RsCpuMapping *pCpuMapping) { + return pGpuResource->__semsurfUnmap__(pGpuResource, pCallContext, pCpuMapping); +} + +static inline NV_STATUS semsurfGetMemInterMapParams_DISPATCH(struct SemaphoreSurface *pRmResource, RMRES_MEM_INTER_MAP_PARAMS *pParams) { + return pRmResource->__semsurfGetMemInterMapParams__(pRmResource, pParams); +} + +static inline NV_STATUS semsurfGetMemoryMappingDescriptor_DISPATCH(struct SemaphoreSurface *pRmResource, struct MEMORY_DESCRIPTOR **ppMemDesc) { + return pRmResource->__semsurfGetMemoryMappingDescriptor__(pRmResource, ppMemDesc); +} + +static inline NV_STATUS semsurfControlFilter_DISPATCH(struct SemaphoreSurface *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return pResource->__semsurfControlFilter__(pResource, pCallContext, pParams); +} + +static inline NV_STATUS semsurfControlSerialization_Prologue_DISPATCH(struct SemaphoreSurface *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return pResource->__semsurfControlSerialization_Prologue__(pResource, pCallContext, pParams); +} + +static inline void semsurfPreDestruct_DISPATCH(struct SemaphoreSurface *pResource) { + pResource->__semsurfPreDestruct__(pResource); +} + +static inline NV_STATUS semsurfIsDuplicate_DISPATCH(struct SemaphoreSurface *pResource, NvHandle hMemory, NvBool *pDuplicate) { + return pResource->__semsurfIsDuplicate__(pResource, hMemory, pDuplicate); +} + +static inline void semsurfControlSerialization_Epilogue_DISPATCH(struct SemaphoreSurface *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + pResource->__semsurfControlSerialization_Epilogue__(pResource, pCallContext, pParams); +} + +static inline NV_STATUS semsurfMap_DISPATCH(struct SemaphoreSurface *pGpuResource, struct CALL_CONTEXT *pCallContext, struct RS_CPU_MAP_PARAMS *pParams, struct RsCpuMapping *pCpuMapping) { + return pGpuResource->__semsurfMap__(pGpuResource, pCallContext, pParams, pCpuMapping); +} + +static inline NvBool semsurfAccessCallback_DISPATCH(struct SemaphoreSurface *pResource, struct RsClient *pInvokingClient, void *pAllocParams, RsAccessRight accessRight) { + return pResource->__semsurfAccessCallback__(pResource, pInvokingClient, pAllocParams, accessRight); +} + +NV_STATUS semsurfConstruct_IMPL(struct SemaphoreSurface *arg_semaphoreSurf, CALL_CONTEXT *arg_pCallContext, struct RS_RES_ALLOC_PARAMS_INTERNAL *arg_pParams); + +#define __nvoc_semsurfConstruct(arg_semaphoreSurf, arg_pCallContext, arg_pParams) semsurfConstruct_IMPL(arg_semaphoreSurf, arg_pCallContext, arg_pParams) +void semsurfDestruct_IMPL(struct SemaphoreSurface *pSemSurf); + +#define __nvoc_semsurfDestruct(pSemSurf) semsurfDestruct_IMPL(pSemSurf) +#undef PRIVATE_FIELD + + +#endif // SEM_SURF_H + +#ifdef __cplusplus +} // extern "C" +#endif +#endif // _G_SEM_SURF_NVOC_H_ diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/generated/g_spdm_nvoc.c nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_spdm_nvoc.c --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/generated/g_spdm_nvoc.c 1970-01-01 00:00:00.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_spdm_nvoc.c 2024-03-05 22:18:45.000000000 +0000 @@ -0,0 +1,266 @@ +#define NVOC_SPDM_H_PRIVATE_ACCESS_ALLOWED +#include "nvoc/runtime.h" +#include "nvoc/rtti.h" +#include "nvtypes.h" +#include "nvport/nvport.h" +#include "nvport/inline/util_valist.h" +#include "utils/nvassert.h" +#include "g_spdm_nvoc.h" + +#ifdef DEBUG +char __nvoc_class_id_uniqueness_check_0x261ee8 = 1; +#endif + +extern const struct NVOC_CLASS_DEF __nvoc_class_def_Spdm; + +extern const struct NVOC_CLASS_DEF __nvoc_class_def_Object; + +void __nvoc_init_Spdm(Spdm*, RmHalspecOwner* ); +void __nvoc_init_funcTable_Spdm(Spdm*, RmHalspecOwner* ); +NV_STATUS __nvoc_ctor_Spdm(Spdm*, RmHalspecOwner* ); +void __nvoc_init_dataField_Spdm(Spdm*, RmHalspecOwner* ); +void __nvoc_dtor_Spdm(Spdm*); +extern const struct NVOC_EXPORT_INFO __nvoc_export_info_Spdm; + +static const struct NVOC_RTTI __nvoc_rtti_Spdm_Spdm = { + /*pClassDef=*/ &__nvoc_class_def_Spdm, + /*dtor=*/ (NVOC_DYNAMIC_DTOR) &__nvoc_dtor_Spdm, + /*offset=*/ 0, +}; + +static const struct NVOC_RTTI __nvoc_rtti_Spdm_Object = { + /*pClassDef=*/ &__nvoc_class_def_Object, + /*dtor=*/ &__nvoc_destructFromBase, + /*offset=*/ NV_OFFSETOF(Spdm, __nvoc_base_Object), +}; + +static const struct NVOC_CASTINFO __nvoc_castinfo_Spdm = { + /*numRelatives=*/ 2, + /*relatives=*/ { + &__nvoc_rtti_Spdm_Spdm, + &__nvoc_rtti_Spdm_Object, + }, +}; + +const struct NVOC_CLASS_DEF __nvoc_class_def_Spdm = +{ + /*classInfo=*/ { + /*size=*/ sizeof(Spdm), + /*classId=*/ classId(Spdm), + /*providerId=*/ &__nvoc_rtti_provider, +#if NV_PRINTF_STRINGS_ALLOWED + /*name=*/ "Spdm", +#endif + }, + /*objCreatefn=*/ (NVOC_DYNAMIC_OBJ_CREATE) &__nvoc_objCreateDynamic_Spdm, + /*pCastInfo=*/ &__nvoc_castinfo_Spdm, + /*pExportInfo=*/ &__nvoc_export_info_Spdm +}; + +const struct NVOC_EXPORT_INFO __nvoc_export_info_Spdm = +{ + /*numEntries=*/ 0, + /*pExportEntries=*/ 0 +}; + +void __nvoc_dtor_Object(Object*); +void __nvoc_dtor_Spdm(Spdm *pThis) { + __nvoc_spdmDestruct(pThis); + __nvoc_dtor_Object(&pThis->__nvoc_base_Object); + PORT_UNREFERENCED_VARIABLE(pThis); +} + +void __nvoc_init_dataField_Spdm(Spdm *pThis, RmHalspecOwner *pRmhalspecowner) { + ChipHal *chipHal = &pRmhalspecowner->chipHal; + const unsigned long chipHal_HalVarIdx = (unsigned long)chipHal->__nvoc_HalVarIdx; + PORT_UNREFERENCED_VARIABLE(pThis); + PORT_UNREFERENCED_VARIABLE(pRmhalspecowner); + PORT_UNREFERENCED_VARIABLE(chipHal); + PORT_UNREFERENCED_VARIABLE(chipHal_HalVarIdx); +} + +NV_STATUS __nvoc_ctor_Object(Object* ); +NV_STATUS __nvoc_ctor_Spdm(Spdm *pThis, RmHalspecOwner *pRmhalspecowner) { + NV_STATUS status = NV_OK; + status = __nvoc_ctor_Object(&pThis->__nvoc_base_Object); + if (status != NV_OK) goto __nvoc_ctor_Spdm_fail_Object; + __nvoc_init_dataField_Spdm(pThis, pRmhalspecowner); + + status = __nvoc_spdmConstruct(pThis); + if (status != NV_OK) goto __nvoc_ctor_Spdm_fail__init; + goto __nvoc_ctor_Spdm_exit; // Success + +__nvoc_ctor_Spdm_fail__init: + __nvoc_dtor_Object(&pThis->__nvoc_base_Object); +__nvoc_ctor_Spdm_fail_Object: +__nvoc_ctor_Spdm_exit: + + return status; +} + +static void __nvoc_init_funcTable_Spdm_1(Spdm *pThis, RmHalspecOwner *pRmhalspecowner) { + ChipHal *chipHal = &pRmhalspecowner->chipHal; + const unsigned long chipHal_HalVarIdx = (unsigned long)chipHal->__nvoc_HalVarIdx; + PORT_UNREFERENCED_VARIABLE(pThis); + PORT_UNREFERENCED_VARIABLE(pRmhalspecowner); + PORT_UNREFERENCED_VARIABLE(chipHal); + PORT_UNREFERENCED_VARIABLE(chipHal_HalVarIdx); + + // Hal function -- spdmGetCertChains + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ + { + pThis->__spdmGetCertChains__ = &spdmGetCertChains_GH100; + } + // default + else + { + pThis->__spdmGetCertChains__ = &spdmGetCertChains_46f6a7; + } + + // Hal function -- spdmGetAttestationReport + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ + { + pThis->__spdmGetAttestationReport__ = &spdmGetAttestationReport_GH100; + } + // default + else + { + pThis->__spdmGetAttestationReport__ = &spdmGetAttestationReport_46f6a7; + } + + // Hal function -- spdmDeviceInit + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ + { + pThis->__spdmDeviceInit__ = &spdmDeviceInit_GH100; + } + // default + else + { + pThis->__spdmDeviceInit__ = &spdmDeviceInit_46f6a7; + } + + // Hal function -- spdmDeviceDeinit + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ + { + pThis->__spdmDeviceDeinit__ = &spdmDeviceDeinit_GH100; + } + // default + else + { + pThis->__spdmDeviceDeinit__ = &spdmDeviceDeinit_46f6a7; + } + + // Hal function -- spdmDeviceSecuredSessionSupported + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ + { + pThis->__spdmDeviceSecuredSessionSupported__ = &spdmDeviceSecuredSessionSupported_GH100; + } + // default + else + { + pThis->__spdmDeviceSecuredSessionSupported__ = &spdmDeviceSecuredSessionSupported_46f6a7; + } + + // Hal function -- spdmCheckConnection + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ + { + pThis->__spdmCheckConnection__ = &spdmCheckConnection_GH100; + } + // default + else + { + pThis->__spdmCheckConnection__ = &spdmCheckConnection_46f6a7; + } + + // Hal function -- spdmMessageProcess + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ + { + pThis->__spdmMessageProcess__ = &spdmMessageProcess_GH100; + } + // default + else + { + pThis->__spdmMessageProcess__ = &spdmMessageProcess_46f6a7; + } + + // Hal function -- spdmGetCertificates + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ + { + pThis->__spdmGetCertificates__ = &spdmGetCertificates_GH100; + } + // default + else + { + pThis->__spdmGetCertificates__ = &spdmGetCertificates_46f6a7; + } +} + +void __nvoc_init_funcTable_Spdm(Spdm *pThis, RmHalspecOwner *pRmhalspecowner) { + __nvoc_init_funcTable_Spdm_1(pThis, pRmhalspecowner); +} + +void __nvoc_init_Object(Object*); +void __nvoc_init_Spdm(Spdm *pThis, RmHalspecOwner *pRmhalspecowner) { + pThis->__nvoc_pbase_Spdm = pThis; + pThis->__nvoc_pbase_Object = &pThis->__nvoc_base_Object; + __nvoc_init_Object(&pThis->__nvoc_base_Object); + __nvoc_init_funcTable_Spdm(pThis, pRmhalspecowner); +} + +NV_STATUS __nvoc_objCreate_Spdm(Spdm **ppThis, Dynamic *pParent, NvU32 createFlags) { + NV_STATUS status; + Object *pParentObj; + Spdm *pThis; + RmHalspecOwner *pRmhalspecowner; + + status = __nvoc_handleObjCreateMemAlloc(createFlags, sizeof(Spdm), (void**)&pThis, (void**)ppThis); + if (status != NV_OK) + return status; + + portMemSet(pThis, 0, sizeof(Spdm)); + + __nvoc_initRtti(staticCast(pThis, Dynamic), &__nvoc_class_def_Spdm); + + pThis->__nvoc_base_Object.createFlags = createFlags; + + if (pParent != NULL && !(createFlags & NVOC_OBJ_CREATE_FLAGS_PARENT_HALSPEC_ONLY)) + { + pParentObj = dynamicCast(pParent, Object); + objAddChild(pParentObj, &pThis->__nvoc_base_Object); + } + else + { + pThis->__nvoc_base_Object.pParent = NULL; + } + + if ((pRmhalspecowner = dynamicCast(pParent, RmHalspecOwner)) == NULL) + pRmhalspecowner = objFindAncestorOfType(RmHalspecOwner, pParent); + NV_ASSERT_OR_RETURN(pRmhalspecowner != NULL, NV_ERR_INVALID_ARGUMENT); + + __nvoc_init_Spdm(pThis, pRmhalspecowner); + status = __nvoc_ctor_Spdm(pThis, pRmhalspecowner); + if (status != NV_OK) goto __nvoc_objCreate_Spdm_cleanup; + + *ppThis = pThis; + + return NV_OK; + +__nvoc_objCreate_Spdm_cleanup: + // do not call destructors here since the constructor already called them + if (createFlags & NVOC_OBJ_CREATE_FLAGS_IN_PLACE_CONSTRUCT) + portMemSet(pThis, 0, sizeof(Spdm)); + else + portMemFree(pThis); + + // coverity[leaked_storage:FALSE] + return status; +} + +NV_STATUS __nvoc_objCreateDynamic_Spdm(Spdm **ppThis, Dynamic *pParent, NvU32 createFlags, va_list args) { + NV_STATUS status; + + status = __nvoc_objCreate_Spdm(ppThis, pParent, createFlags); + + return status; +} + diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/generated/g_spdm_nvoc.h nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_spdm_nvoc.h --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/generated/g_spdm_nvoc.h 1970-01-01 00:00:00.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_spdm_nvoc.h 2024-03-05 22:18:45.000000000 +0000 @@ -0,0 +1,291 @@ +#ifndef _G_SPDM_NVOC_H_ +#define _G_SPDM_NVOC_H_ +#include "nvoc/runtime.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/* + * SPDX-FileCopyrightText: Copyright (c) 2021-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#include "g_spdm_nvoc.h" + +#ifndef NV_SPDM_H +#define NV_SPDM_H +// SPDM_H may conflict with libspdm headers. + +#include "gpu/gpu.h" +#include "nvport/nvport.h" + +/****************************************************************************\ + * * + * SPDM module header. * + * * + ****************************************************************************/ + +/* ------------------------ Macros ----------------------------------------- */ +#define HAL_MAPPING_ONLY_IF_SPDM_SUPPORTED_IMPL \ + { \ + default: _IMPL; \ + } +#define HAL_MAPPING_ONLY_IF_SPDM_SUPPORTED_HAL \ + { \ + GH100 : _GH100; \ + default : return NV_ERR_NOT_SUPPORTED; \ + } +#define HAL_MAPPING_ONLY_IF_SPDM_SUPPORTED_VOID \ + { \ + default: _IMPL; \ + } + +#ifdef NVOC_SPDM_H_PRIVATE_ACCESS_ALLOWED +#define PRIVATE_FIELD(x) x +#else +#define PRIVATE_FIELD(x) NVOC_PRIVATE_FIELD(x) +#endif +struct Spdm { + const struct NVOC_RTTI *__nvoc_rtti; + struct Object __nvoc_base_Object; + struct Object *__nvoc_pbase_Object; + struct Spdm *__nvoc_pbase_Spdm; + NV_STATUS (*__spdmGetCertChains__)(struct OBJGPU *, struct Spdm *, void *, NvU32 *, void *, NvU32 *); + NV_STATUS (*__spdmGetAttestationReport__)(struct OBJGPU *, struct Spdm *, NvU8 *, void *, NvU32 *, NvBool *, void *, NvU32 *); + NV_STATUS (*__spdmDeviceInit__)(struct OBJGPU *, struct Spdm *); + NV_STATUS (*__spdmDeviceDeinit__)(struct OBJGPU *, struct Spdm *, NvBool); + NV_STATUS (*__spdmDeviceSecuredSessionSupported__)(struct OBJGPU *, struct Spdm *); + NV_STATUS (*__spdmCheckConnection__)(struct OBJGPU *, struct Spdm *); + NV_STATUS (*__spdmMessageProcess__)(struct OBJGPU *, struct Spdm *, NvU8 *, NvU32, NvU8 *, NvU32 *); + NV_STATUS (*__spdmGetCertificates__)(struct OBJGPU *, struct Spdm *); + void *pLibspdmContext; + NvU32 libspdmContextSize; + void *pLibspdmScratch; + NvU32 libspdmScratchSize; + NvU32 sessionId; + NvU32 guestId; + NvU32 endpointId; + NvU8 *pAttestationCertChain; + size_t attestationCertChainSize; + void *pDeviceIOContext; + void *pLastExchange; + size_t lastExchangeSize; + NvBool bExportSecretCleared; +}; + +#ifndef __NVOC_CLASS_Spdm_TYPEDEF__ +#define __NVOC_CLASS_Spdm_TYPEDEF__ +typedef struct Spdm Spdm; +#endif /* __NVOC_CLASS_Spdm_TYPEDEF__ */ + +#ifndef __nvoc_class_id_Spdm +#define __nvoc_class_id_Spdm 0x261ee8 +#endif /* __nvoc_class_id_Spdm */ + +extern const struct NVOC_CLASS_DEF __nvoc_class_def_Spdm; + +#define __staticCast_Spdm(pThis) \ + ((pThis)->__nvoc_pbase_Spdm) + +#ifdef __nvoc_spdm_h_disabled +#define __dynamicCast_Spdm(pThis) ((Spdm*)NULL) +#else //__nvoc_spdm_h_disabled +#define __dynamicCast_Spdm(pThis) \ + ((Spdm*)__nvoc_dynamicCast(staticCast((pThis), Dynamic), classInfo(Spdm))) +#endif //__nvoc_spdm_h_disabled + + +NV_STATUS __nvoc_objCreateDynamic_Spdm(Spdm**, Dynamic*, NvU32, va_list); + +NV_STATUS __nvoc_objCreate_Spdm(Spdm**, Dynamic*, NvU32); +#define __objCreate_Spdm(ppNewObj, pParent, createFlags) \ + __nvoc_objCreate_Spdm((ppNewObj), staticCast((pParent), Dynamic), (createFlags)) + +#define spdmGetCertChains(pGpu, pSpdm, pKeyExCertChain, pKeyExCertChainSize, pAttestationCertChain, pAttestationCertChainSize) spdmGetCertChains_DISPATCH(pGpu, pSpdm, pKeyExCertChain, pKeyExCertChainSize, pAttestationCertChain, pAttestationCertChainSize) +#define spdmGetCertChains_HAL(pGpu, pSpdm, pKeyExCertChain, pKeyExCertChainSize, pAttestationCertChain, pAttestationCertChainSize) spdmGetCertChains_DISPATCH(pGpu, pSpdm, pKeyExCertChain, pKeyExCertChainSize, pAttestationCertChain, pAttestationCertChainSize) +#define spdmGetAttestationReport(pGpu, pSpdm, pNonce, pAttestationReport, pAttestationReportSize, pbIsCecAttestationReportPresent, pCecAttestationReport, pCecAttestationReportSize) spdmGetAttestationReport_DISPATCH(pGpu, pSpdm, pNonce, pAttestationReport, pAttestationReportSize, pbIsCecAttestationReportPresent, pCecAttestationReport, pCecAttestationReportSize) +#define spdmGetAttestationReport_HAL(pGpu, pSpdm, pNonce, pAttestationReport, pAttestationReportSize, pbIsCecAttestationReportPresent, pCecAttestationReport, pCecAttestationReportSize) spdmGetAttestationReport_DISPATCH(pGpu, pSpdm, pNonce, pAttestationReport, pAttestationReportSize, pbIsCecAttestationReportPresent, pCecAttestationReport, pCecAttestationReportSize) +#define spdmDeviceInit(pGpu, pSpdm) spdmDeviceInit_DISPATCH(pGpu, pSpdm) +#define spdmDeviceInit_HAL(pGpu, pSpdm) spdmDeviceInit_DISPATCH(pGpu, pSpdm) +#define spdmDeviceDeinit(pGpu, pSpdm, bForceClear) spdmDeviceDeinit_DISPATCH(pGpu, pSpdm, bForceClear) +#define spdmDeviceDeinit_HAL(pGpu, pSpdm, bForceClear) spdmDeviceDeinit_DISPATCH(pGpu, pSpdm, bForceClear) +#define spdmDeviceSecuredSessionSupported(pGpu, pSpdm) spdmDeviceSecuredSessionSupported_DISPATCH(pGpu, pSpdm) +#define spdmDeviceSecuredSessionSupported_HAL(pGpu, pSpdm) spdmDeviceSecuredSessionSupported_DISPATCH(pGpu, pSpdm) +#define spdmCheckConnection(pGpu, pSpdm) spdmCheckConnection_DISPATCH(pGpu, pSpdm) +#define spdmCheckConnection_HAL(pGpu, pSpdm) spdmCheckConnection_DISPATCH(pGpu, pSpdm) +#define spdmMessageProcess(pGpu, pSpdm, pRequest, requestSize, pResponse, pResponseSize) spdmMessageProcess_DISPATCH(pGpu, pSpdm, pRequest, requestSize, pResponse, pResponseSize) +#define spdmMessageProcess_HAL(pGpu, pSpdm, pRequest, requestSize, pResponse, pResponseSize) spdmMessageProcess_DISPATCH(pGpu, pSpdm, pRequest, requestSize, pResponse, pResponseSize) +#define spdmGetCertificates(pGpu, pSpdm) spdmGetCertificates_DISPATCH(pGpu, pSpdm) +#define spdmGetCertificates_HAL(pGpu, pSpdm) spdmGetCertificates_DISPATCH(pGpu, pSpdm) +NV_STATUS spdmConstruct_IMPL(struct Spdm *arg_pSpdm); + + +#define __nvoc_spdmConstruct(arg_pSpdm) spdmConstruct_IMPL(arg_pSpdm) +void spdmDestruct_IMPL(struct Spdm *pSpdm); + + +#define __nvoc_spdmDestruct(pSpdm) spdmDestruct_IMPL(pSpdm) +NV_STATUS spdmContextInit_IMPL(struct OBJGPU *pGpu, struct Spdm *pSpdm); + + +#ifdef __nvoc_spdm_h_disabled +static inline NV_STATUS spdmContextInit(struct OBJGPU *pGpu, struct Spdm *pSpdm) { + NV_ASSERT_FAILED_PRECOMP("Spdm was disabled!"); + return NV_ERR_NOT_SUPPORTED; +} +#else //__nvoc_spdm_h_disabled +#define spdmContextInit(pGpu, pSpdm) spdmContextInit_IMPL(pGpu, pSpdm) +#endif //__nvoc_spdm_h_disabled + +#define spdmContextInit_HAL(pGpu, pSpdm) spdmContextInit(pGpu, pSpdm) + +NV_STATUS spdmContextDeinit_IMPL(struct OBJGPU *pGpu, struct Spdm *pSpdm, NvBool bForceClear); + + +#ifdef __nvoc_spdm_h_disabled +static inline NV_STATUS spdmContextDeinit(struct OBJGPU *pGpu, struct Spdm *pSpdm, NvBool bForceClear) { + NV_ASSERT_FAILED_PRECOMP("Spdm was disabled!"); + return NV_ERR_NOT_SUPPORTED; +} +#else //__nvoc_spdm_h_disabled +#define spdmContextDeinit(pGpu, pSpdm, bForceClear) spdmContextDeinit_IMPL(pGpu, pSpdm, bForceClear) +#endif //__nvoc_spdm_h_disabled + +#define spdmContextDeinit_HAL(pGpu, pSpdm, bForceClear) spdmContextDeinit(pGpu, pSpdm, bForceClear) + +NV_STATUS spdmStart_IMPL(struct OBJGPU *pGpu, struct Spdm *pSpdm); + + +#ifdef __nvoc_spdm_h_disabled +static inline NV_STATUS spdmStart(struct OBJGPU *pGpu, struct Spdm *pSpdm) { + NV_ASSERT_FAILED_PRECOMP("Spdm was disabled!"); + return NV_ERR_NOT_SUPPORTED; +} +#else //__nvoc_spdm_h_disabled +#define spdmStart(pGpu, pSpdm) spdmStart_IMPL(pGpu, pSpdm) +#endif //__nvoc_spdm_h_disabled + +#define spdmStart_HAL(pGpu, pSpdm) spdmStart(pGpu, pSpdm) + +NV_STATUS spdmRetrieveExportSecret_IMPL(struct OBJGPU *pGpu, struct Spdm *pSpdm, NvU32 keySize, NvU8 *pKeyOut); + + +#ifdef __nvoc_spdm_h_disabled +static inline NV_STATUS spdmRetrieveExportSecret(struct OBJGPU *pGpu, struct Spdm *pSpdm, NvU32 keySize, NvU8 *pKeyOut) { + NV_ASSERT_FAILED_PRECOMP("Spdm was disabled!"); + return NV_ERR_NOT_SUPPORTED; +} +#else //__nvoc_spdm_h_disabled +#define spdmRetrieveExportSecret(pGpu, pSpdm, keySize, pKeyOut) spdmRetrieveExportSecret_IMPL(pGpu, pSpdm, keySize, pKeyOut) +#endif //__nvoc_spdm_h_disabled + +#define spdmRetrieveExportSecret_HAL(pGpu, pSpdm, keySize, pKeyOut) spdmRetrieveExportSecret(pGpu, pSpdm, keySize, pKeyOut) + +NV_STATUS spdmGetCertChains_GH100(struct OBJGPU *pGpu, struct Spdm *pSpdm, void *pKeyExCertChain, NvU32 *pKeyExCertChainSize, void *pAttestationCertChain, NvU32 *pAttestationCertChainSize); + +static inline NV_STATUS spdmGetCertChains_46f6a7(struct OBJGPU *pGpu, struct Spdm *pSpdm, void *pKeyExCertChain, NvU32 *pKeyExCertChainSize, void *pAttestationCertChain, NvU32 *pAttestationCertChainSize) { + return NV_ERR_NOT_SUPPORTED; +} + +static inline NV_STATUS spdmGetCertChains_DISPATCH(struct OBJGPU *pGpu, struct Spdm *pSpdm, void *pKeyExCertChain, NvU32 *pKeyExCertChainSize, void *pAttestationCertChain, NvU32 *pAttestationCertChainSize) { + return pSpdm->__spdmGetCertChains__(pGpu, pSpdm, pKeyExCertChain, pKeyExCertChainSize, pAttestationCertChain, pAttestationCertChainSize); +} + +NV_STATUS spdmGetAttestationReport_GH100(struct OBJGPU *pGpu, struct Spdm *pSpdm, NvU8 *pNonce, void *pAttestationReport, NvU32 *pAttestationReportSize, NvBool *pbIsCecAttestationReportPresent, void *pCecAttestationReport, NvU32 *pCecAttestationReportSize); + +static inline NV_STATUS spdmGetAttestationReport_46f6a7(struct OBJGPU *pGpu, struct Spdm *pSpdm, NvU8 *pNonce, void *pAttestationReport, NvU32 *pAttestationReportSize, NvBool *pbIsCecAttestationReportPresent, void *pCecAttestationReport, NvU32 *pCecAttestationReportSize) { + return NV_ERR_NOT_SUPPORTED; +} + +static inline NV_STATUS spdmGetAttestationReport_DISPATCH(struct OBJGPU *pGpu, struct Spdm *pSpdm, NvU8 *pNonce, void *pAttestationReport, NvU32 *pAttestationReportSize, NvBool *pbIsCecAttestationReportPresent, void *pCecAttestationReport, NvU32 *pCecAttestationReportSize) { + return pSpdm->__spdmGetAttestationReport__(pGpu, pSpdm, pNonce, pAttestationReport, pAttestationReportSize, pbIsCecAttestationReportPresent, pCecAttestationReport, pCecAttestationReportSize); +} + +NV_STATUS spdmDeviceInit_GH100(struct OBJGPU *pGpu, struct Spdm *pSpdm); + +static inline NV_STATUS spdmDeviceInit_46f6a7(struct OBJGPU *pGpu, struct Spdm *pSpdm) { + return NV_ERR_NOT_SUPPORTED; +} + +static inline NV_STATUS spdmDeviceInit_DISPATCH(struct OBJGPU *pGpu, struct Spdm *pSpdm) { + return pSpdm->__spdmDeviceInit__(pGpu, pSpdm); +} + +NV_STATUS spdmDeviceDeinit_GH100(struct OBJGPU *pGpu, struct Spdm *pSpdm, NvBool bForceClear); + +static inline NV_STATUS spdmDeviceDeinit_46f6a7(struct OBJGPU *pGpu, struct Spdm *pSpdm, NvBool bForceClear) { + return NV_ERR_NOT_SUPPORTED; +} + +static inline NV_STATUS spdmDeviceDeinit_DISPATCH(struct OBJGPU *pGpu, struct Spdm *pSpdm, NvBool bForceClear) { + return pSpdm->__spdmDeviceDeinit__(pGpu, pSpdm, bForceClear); +} + +NV_STATUS spdmDeviceSecuredSessionSupported_GH100(struct OBJGPU *pGpu, struct Spdm *pSpdm); + +static inline NV_STATUS spdmDeviceSecuredSessionSupported_46f6a7(struct OBJGPU *pGpu, struct Spdm *pSpdm) { + return NV_ERR_NOT_SUPPORTED; +} + +static inline NV_STATUS spdmDeviceSecuredSessionSupported_DISPATCH(struct OBJGPU *pGpu, struct Spdm *pSpdm) { + return pSpdm->__spdmDeviceSecuredSessionSupported__(pGpu, pSpdm); +} + +NV_STATUS spdmCheckConnection_GH100(struct OBJGPU *pGpu, struct Spdm *pSpdm); + +static inline NV_STATUS spdmCheckConnection_46f6a7(struct OBJGPU *pGpu, struct Spdm *pSpdm) { + return NV_ERR_NOT_SUPPORTED; +} + +static inline NV_STATUS spdmCheckConnection_DISPATCH(struct OBJGPU *pGpu, struct Spdm *pSpdm) { + return pSpdm->__spdmCheckConnection__(pGpu, pSpdm); +} + +NV_STATUS spdmMessageProcess_GH100(struct OBJGPU *pGpu, struct Spdm *pSpdm, NvU8 *pRequest, NvU32 requestSize, NvU8 *pResponse, NvU32 *pResponseSize); + +static inline NV_STATUS spdmMessageProcess_46f6a7(struct OBJGPU *pGpu, struct Spdm *pSpdm, NvU8 *pRequest, NvU32 requestSize, NvU8 *pResponse, NvU32 *pResponseSize) { + return NV_ERR_NOT_SUPPORTED; +} + +static inline NV_STATUS spdmMessageProcess_DISPATCH(struct OBJGPU *pGpu, struct Spdm *pSpdm, NvU8 *pRequest, NvU32 requestSize, NvU8 *pResponse, NvU32 *pResponseSize) { + return pSpdm->__spdmMessageProcess__(pGpu, pSpdm, pRequest, requestSize, pResponse, pResponseSize); +} + +NV_STATUS spdmGetCertificates_GH100(struct OBJGPU *pGpu, struct Spdm *pSpdm); + +static inline NV_STATUS spdmGetCertificates_46f6a7(struct OBJGPU *pGpu, struct Spdm *pSpdm) { + return NV_ERR_NOT_SUPPORTED; +} + +static inline NV_STATUS spdmGetCertificates_DISPATCH(struct OBJGPU *pGpu, struct Spdm *pSpdm) { + return pSpdm->__spdmGetCertificates__(pGpu, pSpdm); +} + +#undef PRIVATE_FIELD + + +#endif // NV_SPDM_H + +#ifdef __cplusplus +} // extern "C" +#endif +#endif // _G_SPDM_NVOC_H_ diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/generated/g_standard_mem_nvoc.c nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_standard_mem_nvoc.c --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/generated/g_standard_mem_nvoc.c 2023-10-25 20:27:19.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_standard_mem_nvoc.c 2024-03-05 22:18:45.000000000 +0000 @@ -101,60 +101,76 @@ return memCheckMemInterUnmap((struct Memory *)(((unsigned char *)pMemory) + __nvoc_rtti_StandardMemory_Memory.offset), bSubdeviceHandleProvided); } -static NV_STATUS __nvoc_thunk_Memory_stdmemControl(struct StandardMemory *pMemory, CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { - return memControl((struct Memory *)(((unsigned char *)pMemory) + __nvoc_rtti_StandardMemory_Memory.offset), pCallContext, pParams); +static NvBool __nvoc_thunk_RmResource_stdmemShareCallback(struct StandardMemory *pResource, struct RsClient *pInvokingClient, struct RsResourceRef *pParentRef, RS_SHARE_POLICY *pSharePolicy) { + return rmresShareCallback((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_StandardMemory_RmResource.offset), pInvokingClient, pParentRef, pSharePolicy); } -static NV_STATUS __nvoc_thunk_Memory_stdmemUnmap(struct StandardMemory *pMemory, CALL_CONTEXT *pCallContext, RsCpuMapping *pCpuMapping) { - return memUnmap((struct Memory *)(((unsigned char *)pMemory) + __nvoc_rtti_StandardMemory_Memory.offset), pCallContext, pCpuMapping); +static NV_STATUS __nvoc_thunk_RsResource_stdmemMapTo(struct StandardMemory *pResource, RS_RES_MAP_TO_PARAMS *pParams) { + return resMapTo((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_StandardMemory_RsResource.offset), pParams); } -static NV_STATUS __nvoc_thunk_Memory_stdmemGetMemInterMapParams(struct StandardMemory *pMemory, RMRES_MEM_INTER_MAP_PARAMS *pParams) { - return memGetMemInterMapParams((struct Memory *)(((unsigned char *)pMemory) + __nvoc_rtti_StandardMemory_Memory.offset), pParams); +static NV_STATUS __nvoc_thunk_Memory_stdmemGetMapAddrSpace(struct StandardMemory *pMemory, CALL_CONTEXT *pCallContext, NvU32 mapFlags, NV_ADDRESS_SPACE *pAddrSpace) { + return memGetMapAddrSpace((struct Memory *)(((unsigned char *)pMemory) + __nvoc_rtti_StandardMemory_Memory.offset), pCallContext, mapFlags, pAddrSpace); } -static NV_STATUS __nvoc_thunk_Memory_stdmemGetMemoryMappingDescriptor(struct StandardMemory *pMemory, MEMORY_DESCRIPTOR **ppMemDesc) { - return memGetMemoryMappingDescriptor((struct Memory *)(((unsigned char *)pMemory) + __nvoc_rtti_StandardMemory_Memory.offset), ppMemDesc); +static NvU32 __nvoc_thunk_RsResource_stdmemGetRefCount(struct StandardMemory *pResource) { + return resGetRefCount((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_StandardMemory_RsResource.offset)); } -static NV_STATUS __nvoc_thunk_Memory_stdmemGetMapAddrSpace(struct StandardMemory *pMemory, CALL_CONTEXT *pCallContext, NvU32 mapFlags, NV_ADDRESS_SPACE *pAddrSpace) { - return memGetMapAddrSpace((struct Memory *)(((unsigned char *)pMemory) + __nvoc_rtti_StandardMemory_Memory.offset), pCallContext, mapFlags, pAddrSpace); +static void __nvoc_thunk_RsResource_stdmemAddAdditionalDependants(struct RsClient *pClient, struct StandardMemory *pResource, RsResourceRef *pReference) { + resAddAdditionalDependants(pClient, (struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_StandardMemory_RsResource.offset), pReference); } -static NvBool __nvoc_thunk_RmResource_stdmemShareCallback(struct StandardMemory *pResource, struct RsClient *pInvokingClient, struct RsResourceRef *pParentRef, RS_SHARE_POLICY *pSharePolicy) { - return rmresShareCallback((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_StandardMemory_RmResource.offset), pInvokingClient, pParentRef, pSharePolicy); +static NV_STATUS __nvoc_thunk_RmResource_stdmemControl_Prologue(struct StandardMemory *pResource, CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return rmresControl_Prologue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_StandardMemory_RmResource.offset), pCallContext, pParams); } -static NV_STATUS __nvoc_thunk_RsResource_stdmemControlFilter(struct StandardMemory *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { - return resControlFilter((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_StandardMemory_RsResource.offset), pCallContext, pParams); +static NvBool __nvoc_thunk_Memory_stdmemIsGpuMapAllowed(struct StandardMemory *pMemory, struct OBJGPU *pGpu) { + return memIsGpuMapAllowed((struct Memory *)(((unsigned char *)pMemory) + __nvoc_rtti_StandardMemory_Memory.offset), pGpu); } -static void __nvoc_thunk_RsResource_stdmemAddAdditionalDependants(struct RsClient *pClient, struct StandardMemory *pResource, RsResourceRef *pReference) { - resAddAdditionalDependants(pClient, (struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_StandardMemory_RsResource.offset), pReference); +static NV_STATUS __nvoc_thunk_RsResource_stdmemUnmapFrom(struct StandardMemory *pResource, RS_RES_UNMAP_FROM_PARAMS *pParams) { + return resUnmapFrom((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_StandardMemory_RsResource.offset), pParams); } -static NvU32 __nvoc_thunk_RsResource_stdmemGetRefCount(struct StandardMemory *pResource) { - return resGetRefCount((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_StandardMemory_RsResource.offset)); +static void __nvoc_thunk_RmResource_stdmemControl_Epilogue(struct StandardMemory *pResource, CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + rmresControl_Epilogue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_StandardMemory_RmResource.offset), pCallContext, pParams); } -static NV_STATUS __nvoc_thunk_RsResource_stdmemMapTo(struct StandardMemory *pResource, RS_RES_MAP_TO_PARAMS *pParams) { - return resMapTo((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_StandardMemory_RsResource.offset), pParams); +static NV_STATUS __nvoc_thunk_RsResource_stdmemControlLookup(struct StandardMemory *pResource, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams, const struct NVOC_EXPORTED_METHOD_DEF **ppEntry) { + return resControlLookup((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_StandardMemory_RsResource.offset), pParams, ppEntry); } -static NV_STATUS __nvoc_thunk_RmResource_stdmemControl_Prologue(struct StandardMemory *pResource, CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { - return rmresControl_Prologue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_StandardMemory_RmResource.offset), pCallContext, pParams); +static NV_STATUS __nvoc_thunk_Memory_stdmemControl(struct StandardMemory *pMemory, CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return memControl((struct Memory *)(((unsigned char *)pMemory) + __nvoc_rtti_StandardMemory_Memory.offset), pCallContext, pParams); } -static NvBool __nvoc_thunk_Memory_stdmemIsGpuMapAllowed(struct StandardMemory *pMemory, struct OBJGPU *pGpu) { - return memIsGpuMapAllowed((struct Memory *)(((unsigned char *)pMemory) + __nvoc_rtti_StandardMemory_Memory.offset), pGpu); +static NV_STATUS __nvoc_thunk_Memory_stdmemUnmap(struct StandardMemory *pMemory, CALL_CONTEXT *pCallContext, RsCpuMapping *pCpuMapping) { + return memUnmap((struct Memory *)(((unsigned char *)pMemory) + __nvoc_rtti_StandardMemory_Memory.offset), pCallContext, pCpuMapping); +} + +static NV_STATUS __nvoc_thunk_Memory_stdmemGetMemInterMapParams(struct StandardMemory *pMemory, RMRES_MEM_INTER_MAP_PARAMS *pParams) { + return memGetMemInterMapParams((struct Memory *)(((unsigned char *)pMemory) + __nvoc_rtti_StandardMemory_Memory.offset), pParams); +} + +static NV_STATUS __nvoc_thunk_Memory_stdmemGetMemoryMappingDescriptor(struct StandardMemory *pMemory, MEMORY_DESCRIPTOR **ppMemDesc) { + return memGetMemoryMappingDescriptor((struct Memory *)(((unsigned char *)pMemory) + __nvoc_rtti_StandardMemory_Memory.offset), ppMemDesc); +} + +static NV_STATUS __nvoc_thunk_RsResource_stdmemControlFilter(struct StandardMemory *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return resControlFilter((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_StandardMemory_RsResource.offset), pCallContext, pParams); +} + +static NV_STATUS __nvoc_thunk_RmResource_stdmemControlSerialization_Prologue(struct StandardMemory *pResource, CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return rmresControlSerialization_Prologue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_StandardMemory_RmResource.offset), pCallContext, pParams); } static NV_STATUS __nvoc_thunk_Memory_stdmemIsReady(struct StandardMemory *pMemory, NvBool bCopyConstructorContext) { return memIsReady((struct Memory *)(((unsigned char *)pMemory) + __nvoc_rtti_StandardMemory_Memory.offset), bCopyConstructorContext); } -static NV_STATUS __nvoc_thunk_Memory_stdmemCheckCopyPermissions(struct StandardMemory *pMemory, struct OBJGPU *pDstGpu, NvHandle hDstClientNvBool) { - return memCheckCopyPermissions((struct Memory *)(((unsigned char *)pMemory) + __nvoc_rtti_StandardMemory_Memory.offset), pDstGpu, hDstClientNvBool); +static NV_STATUS __nvoc_thunk_Memory_stdmemCheckCopyPermissions(struct StandardMemory *pMemory, struct OBJGPU *pDstGpu, struct Device *pDstDevice) { + return memCheckCopyPermissions((struct Memory *)(((unsigned char *)pMemory) + __nvoc_rtti_StandardMemory_Memory.offset), pDstGpu, pDstDevice); } static void __nvoc_thunk_RsResource_stdmemPreDestruct(struct StandardMemory *pResource) { @@ -165,16 +181,8 @@ return memIsDuplicate((struct Memory *)(((unsigned char *)pMemory) + __nvoc_rtti_StandardMemory_Memory.offset), hMemory, pDuplicate); } -static NV_STATUS __nvoc_thunk_RsResource_stdmemUnmapFrom(struct StandardMemory *pResource, RS_RES_UNMAP_FROM_PARAMS *pParams) { - return resUnmapFrom((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_StandardMemory_RsResource.offset), pParams); -} - -static void __nvoc_thunk_RmResource_stdmemControl_Epilogue(struct StandardMemory *pResource, CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { - rmresControl_Epilogue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_StandardMemory_RmResource.offset), pCallContext, pParams); -} - -static NV_STATUS __nvoc_thunk_RsResource_stdmemControlLookup(struct StandardMemory *pResource, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams, const struct NVOC_EXPORTED_METHOD_DEF **ppEntry) { - return resControlLookup((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_StandardMemory_RsResource.offset), pParams, ppEntry); +static void __nvoc_thunk_RmResource_stdmemControlSerialization_Epilogue(struct StandardMemory *pResource, CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + rmresControlSerialization_Epilogue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_StandardMemory_RmResource.offset), pCallContext, pParams); } static NV_STATUS __nvoc_thunk_Memory_stdmemMap(struct StandardMemory *pMemory, CALL_CONTEXT *pCallContext, struct RS_CPU_MAP_PARAMS *pParams, RsCpuMapping *pCpuMapping) { @@ -229,29 +237,37 @@ pThis->__stdmemCheckMemInterUnmap__ = &__nvoc_thunk_Memory_stdmemCheckMemInterUnmap; - pThis->__stdmemControl__ = &__nvoc_thunk_Memory_stdmemControl; + pThis->__stdmemShareCallback__ = &__nvoc_thunk_RmResource_stdmemShareCallback; - pThis->__stdmemUnmap__ = &__nvoc_thunk_Memory_stdmemUnmap; + pThis->__stdmemMapTo__ = &__nvoc_thunk_RsResource_stdmemMapTo; - pThis->__stdmemGetMemInterMapParams__ = &__nvoc_thunk_Memory_stdmemGetMemInterMapParams; + pThis->__stdmemGetMapAddrSpace__ = &__nvoc_thunk_Memory_stdmemGetMapAddrSpace; - pThis->__stdmemGetMemoryMappingDescriptor__ = &__nvoc_thunk_Memory_stdmemGetMemoryMappingDescriptor; + pThis->__stdmemGetRefCount__ = &__nvoc_thunk_RsResource_stdmemGetRefCount; - pThis->__stdmemGetMapAddrSpace__ = &__nvoc_thunk_Memory_stdmemGetMapAddrSpace; + pThis->__stdmemAddAdditionalDependants__ = &__nvoc_thunk_RsResource_stdmemAddAdditionalDependants; - pThis->__stdmemShareCallback__ = &__nvoc_thunk_RmResource_stdmemShareCallback; + pThis->__stdmemControl_Prologue__ = &__nvoc_thunk_RmResource_stdmemControl_Prologue; - pThis->__stdmemControlFilter__ = &__nvoc_thunk_RsResource_stdmemControlFilter; + pThis->__stdmemIsGpuMapAllowed__ = &__nvoc_thunk_Memory_stdmemIsGpuMapAllowed; - pThis->__stdmemAddAdditionalDependants__ = &__nvoc_thunk_RsResource_stdmemAddAdditionalDependants; + pThis->__stdmemUnmapFrom__ = &__nvoc_thunk_RsResource_stdmemUnmapFrom; - pThis->__stdmemGetRefCount__ = &__nvoc_thunk_RsResource_stdmemGetRefCount; + pThis->__stdmemControl_Epilogue__ = &__nvoc_thunk_RmResource_stdmemControl_Epilogue; - pThis->__stdmemMapTo__ = &__nvoc_thunk_RsResource_stdmemMapTo; + pThis->__stdmemControlLookup__ = &__nvoc_thunk_RsResource_stdmemControlLookup; - pThis->__stdmemControl_Prologue__ = &__nvoc_thunk_RmResource_stdmemControl_Prologue; + pThis->__stdmemControl__ = &__nvoc_thunk_Memory_stdmemControl; - pThis->__stdmemIsGpuMapAllowed__ = &__nvoc_thunk_Memory_stdmemIsGpuMapAllowed; + pThis->__stdmemUnmap__ = &__nvoc_thunk_Memory_stdmemUnmap; + + pThis->__stdmemGetMemInterMapParams__ = &__nvoc_thunk_Memory_stdmemGetMemInterMapParams; + + pThis->__stdmemGetMemoryMappingDescriptor__ = &__nvoc_thunk_Memory_stdmemGetMemoryMappingDescriptor; + + pThis->__stdmemControlFilter__ = &__nvoc_thunk_RsResource_stdmemControlFilter; + + pThis->__stdmemControlSerialization_Prologue__ = &__nvoc_thunk_RmResource_stdmemControlSerialization_Prologue; pThis->__stdmemIsReady__ = &__nvoc_thunk_Memory_stdmemIsReady; @@ -261,11 +277,7 @@ pThis->__stdmemIsDuplicate__ = &__nvoc_thunk_Memory_stdmemIsDuplicate; - pThis->__stdmemUnmapFrom__ = &__nvoc_thunk_RsResource_stdmemUnmapFrom; - - pThis->__stdmemControl_Epilogue__ = &__nvoc_thunk_RmResource_stdmemControl_Epilogue; - - pThis->__stdmemControlLookup__ = &__nvoc_thunk_RsResource_stdmemControlLookup; + pThis->__stdmemControlSerialization_Epilogue__ = &__nvoc_thunk_RmResource_stdmemControlSerialization_Epilogue; pThis->__stdmemMap__ = &__nvoc_thunk_Memory_stdmemMap; @@ -293,13 +305,16 @@ Object *pParentObj; StandardMemory *pThis; - pThis = portMemAllocNonPaged(sizeof(StandardMemory)); - if (pThis == NULL) return NV_ERR_NO_MEMORY; + status = __nvoc_handleObjCreateMemAlloc(createFlags, sizeof(StandardMemory), (void**)&pThis, (void**)ppThis); + if (status != NV_OK) + return status; portMemSet(pThis, 0, sizeof(StandardMemory)); __nvoc_initRtti(staticCast(pThis, Dynamic), &__nvoc_class_def_StandardMemory); + pThis->__nvoc_base_Memory.__nvoc_base_RmResource.__nvoc_base_RsResource.__nvoc_base_Object.createFlags = createFlags; + if (pParent != NULL && !(createFlags & NVOC_OBJ_CREATE_FLAGS_PARENT_HALSPEC_ONLY)) { pParentObj = dynamicCast(pParent, Object); @@ -315,11 +330,17 @@ if (status != NV_OK) goto __nvoc_objCreate_StandardMemory_cleanup; *ppThis = pThis; + return NV_OK; __nvoc_objCreate_StandardMemory_cleanup: // do not call destructors here since the constructor already called them - portMemFree(pThis); + if (createFlags & NVOC_OBJ_CREATE_FLAGS_IN_PLACE_CONSTRUCT) + portMemSet(pThis, 0, sizeof(StandardMemory)); + else + portMemFree(pThis); + + // coverity[leaked_storage:FALSE] return status; } diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/generated/g_standard_mem_nvoc.h nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_standard_mem_nvoc.h --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/generated/g_standard_mem_nvoc.h 2023-10-25 20:27:19.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_standard_mem_nvoc.h 2024-03-05 22:18:45.000000000 +0000 @@ -71,25 +71,27 @@ struct StandardMemory *__nvoc_pbase_StandardMemory; NvBool (*__stdmemCanCopy__)(struct StandardMemory *); NV_STATUS (*__stdmemCheckMemInterUnmap__)(struct StandardMemory *, NvBool); + NvBool (*__stdmemShareCallback__)(struct StandardMemory *, struct RsClient *, struct RsResourceRef *, RS_SHARE_POLICY *); + NV_STATUS (*__stdmemMapTo__)(struct StandardMemory *, RS_RES_MAP_TO_PARAMS *); + NV_STATUS (*__stdmemGetMapAddrSpace__)(struct StandardMemory *, CALL_CONTEXT *, NvU32, NV_ADDRESS_SPACE *); + NvU32 (*__stdmemGetRefCount__)(struct StandardMemory *); + void (*__stdmemAddAdditionalDependants__)(struct RsClient *, struct StandardMemory *, RsResourceRef *); + NV_STATUS (*__stdmemControl_Prologue__)(struct StandardMemory *, CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); + NvBool (*__stdmemIsGpuMapAllowed__)(struct StandardMemory *, struct OBJGPU *); + NV_STATUS (*__stdmemUnmapFrom__)(struct StandardMemory *, RS_RES_UNMAP_FROM_PARAMS *); + void (*__stdmemControl_Epilogue__)(struct StandardMemory *, CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); + NV_STATUS (*__stdmemControlLookup__)(struct StandardMemory *, struct RS_RES_CONTROL_PARAMS_INTERNAL *, const struct NVOC_EXPORTED_METHOD_DEF **); NV_STATUS (*__stdmemControl__)(struct StandardMemory *, CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); NV_STATUS (*__stdmemUnmap__)(struct StandardMemory *, CALL_CONTEXT *, RsCpuMapping *); NV_STATUS (*__stdmemGetMemInterMapParams__)(struct StandardMemory *, RMRES_MEM_INTER_MAP_PARAMS *); NV_STATUS (*__stdmemGetMemoryMappingDescriptor__)(struct StandardMemory *, MEMORY_DESCRIPTOR **); - NV_STATUS (*__stdmemGetMapAddrSpace__)(struct StandardMemory *, CALL_CONTEXT *, NvU32, NV_ADDRESS_SPACE *); - NvBool (*__stdmemShareCallback__)(struct StandardMemory *, struct RsClient *, struct RsResourceRef *, RS_SHARE_POLICY *); NV_STATUS (*__stdmemControlFilter__)(struct StandardMemory *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); - void (*__stdmemAddAdditionalDependants__)(struct RsClient *, struct StandardMemory *, RsResourceRef *); - NvU32 (*__stdmemGetRefCount__)(struct StandardMemory *); - NV_STATUS (*__stdmemMapTo__)(struct StandardMemory *, RS_RES_MAP_TO_PARAMS *); - NV_STATUS (*__stdmemControl_Prologue__)(struct StandardMemory *, CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); - NvBool (*__stdmemIsGpuMapAllowed__)(struct StandardMemory *, struct OBJGPU *); + NV_STATUS (*__stdmemControlSerialization_Prologue__)(struct StandardMemory *, CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); NV_STATUS (*__stdmemIsReady__)(struct StandardMemory *, NvBool); - NV_STATUS (*__stdmemCheckCopyPermissions__)(struct StandardMemory *, struct OBJGPU *, NvHandle); + NV_STATUS (*__stdmemCheckCopyPermissions__)(struct StandardMemory *, struct OBJGPU *, struct Device *); void (*__stdmemPreDestruct__)(struct StandardMemory *); NV_STATUS (*__stdmemIsDuplicate__)(struct StandardMemory *, NvHandle, NvBool *); - NV_STATUS (*__stdmemUnmapFrom__)(struct StandardMemory *, RS_RES_UNMAP_FROM_PARAMS *); - void (*__stdmemControl_Epilogue__)(struct StandardMemory *, CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); - NV_STATUS (*__stdmemControlLookup__)(struct StandardMemory *, struct RS_RES_CONTROL_PARAMS_INTERNAL *, const struct NVOC_EXPORTED_METHOD_DEF **); + void (*__stdmemControlSerialization_Epilogue__)(struct StandardMemory *, CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); NV_STATUS (*__stdmemMap__)(struct StandardMemory *, CALL_CONTEXT *, struct RS_CPU_MAP_PARAMS *, RsCpuMapping *); NvBool (*__stdmemAccessCallback__)(struct StandardMemory *, struct RsClient *, void *, RsAccessRight); }; @@ -124,32 +126,34 @@ #define stdmemCanCopy(pStandardMemory) stdmemCanCopy_DISPATCH(pStandardMemory) #define stdmemCheckMemInterUnmap(pMemory, bSubdeviceHandleProvided) stdmemCheckMemInterUnmap_DISPATCH(pMemory, bSubdeviceHandleProvided) +#define stdmemShareCallback(pResource, pInvokingClient, pParentRef, pSharePolicy) stdmemShareCallback_DISPATCH(pResource, pInvokingClient, pParentRef, pSharePolicy) +#define stdmemMapTo(pResource, pParams) stdmemMapTo_DISPATCH(pResource, pParams) +#define stdmemGetMapAddrSpace(pMemory, pCallContext, mapFlags, pAddrSpace) stdmemGetMapAddrSpace_DISPATCH(pMemory, pCallContext, mapFlags, pAddrSpace) +#define stdmemGetRefCount(pResource) stdmemGetRefCount_DISPATCH(pResource) +#define stdmemAddAdditionalDependants(pClient, pResource, pReference) stdmemAddAdditionalDependants_DISPATCH(pClient, pResource, pReference) +#define stdmemControl_Prologue(pResource, pCallContext, pParams) stdmemControl_Prologue_DISPATCH(pResource, pCallContext, pParams) +#define stdmemIsGpuMapAllowed(pMemory, pGpu) stdmemIsGpuMapAllowed_DISPATCH(pMemory, pGpu) +#define stdmemUnmapFrom(pResource, pParams) stdmemUnmapFrom_DISPATCH(pResource, pParams) +#define stdmemControl_Epilogue(pResource, pCallContext, pParams) stdmemControl_Epilogue_DISPATCH(pResource, pCallContext, pParams) +#define stdmemControlLookup(pResource, pParams, ppEntry) stdmemControlLookup_DISPATCH(pResource, pParams, ppEntry) #define stdmemControl(pMemory, pCallContext, pParams) stdmemControl_DISPATCH(pMemory, pCallContext, pParams) #define stdmemUnmap(pMemory, pCallContext, pCpuMapping) stdmemUnmap_DISPATCH(pMemory, pCallContext, pCpuMapping) #define stdmemGetMemInterMapParams(pMemory, pParams) stdmemGetMemInterMapParams_DISPATCH(pMemory, pParams) #define stdmemGetMemoryMappingDescriptor(pMemory, ppMemDesc) stdmemGetMemoryMappingDescriptor_DISPATCH(pMemory, ppMemDesc) -#define stdmemGetMapAddrSpace(pMemory, pCallContext, mapFlags, pAddrSpace) stdmemGetMapAddrSpace_DISPATCH(pMemory, pCallContext, mapFlags, pAddrSpace) -#define stdmemShareCallback(pResource, pInvokingClient, pParentRef, pSharePolicy) stdmemShareCallback_DISPATCH(pResource, pInvokingClient, pParentRef, pSharePolicy) #define stdmemControlFilter(pResource, pCallContext, pParams) stdmemControlFilter_DISPATCH(pResource, pCallContext, pParams) -#define stdmemAddAdditionalDependants(pClient, pResource, pReference) stdmemAddAdditionalDependants_DISPATCH(pClient, pResource, pReference) -#define stdmemGetRefCount(pResource) stdmemGetRefCount_DISPATCH(pResource) -#define stdmemMapTo(pResource, pParams) stdmemMapTo_DISPATCH(pResource, pParams) -#define stdmemControl_Prologue(pResource, pCallContext, pParams) stdmemControl_Prologue_DISPATCH(pResource, pCallContext, pParams) -#define stdmemIsGpuMapAllowed(pMemory, pGpu) stdmemIsGpuMapAllowed_DISPATCH(pMemory, pGpu) +#define stdmemControlSerialization_Prologue(pResource, pCallContext, pParams) stdmemControlSerialization_Prologue_DISPATCH(pResource, pCallContext, pParams) #define stdmemIsReady(pMemory, bCopyConstructorContext) stdmemIsReady_DISPATCH(pMemory, bCopyConstructorContext) -#define stdmemCheckCopyPermissions(pMemory, pDstGpu, hDstClientNvBool) stdmemCheckCopyPermissions_DISPATCH(pMemory, pDstGpu, hDstClientNvBool) +#define stdmemCheckCopyPermissions(pMemory, pDstGpu, pDstDevice) stdmemCheckCopyPermissions_DISPATCH(pMemory, pDstGpu, pDstDevice) #define stdmemPreDestruct(pResource) stdmemPreDestruct_DISPATCH(pResource) #define stdmemIsDuplicate(pMemory, hMemory, pDuplicate) stdmemIsDuplicate_DISPATCH(pMemory, hMemory, pDuplicate) -#define stdmemUnmapFrom(pResource, pParams) stdmemUnmapFrom_DISPATCH(pResource, pParams) -#define stdmemControl_Epilogue(pResource, pCallContext, pParams) stdmemControl_Epilogue_DISPATCH(pResource, pCallContext, pParams) -#define stdmemControlLookup(pResource, pParams, ppEntry) stdmemControlLookup_DISPATCH(pResource, pParams, ppEntry) +#define stdmemControlSerialization_Epilogue(pResource, pCallContext, pParams) stdmemControlSerialization_Epilogue_DISPATCH(pResource, pCallContext, pParams) #define stdmemMap(pMemory, pCallContext, pParams, pCpuMapping) stdmemMap_DISPATCH(pMemory, pCallContext, pParams, pCpuMapping) #define stdmemAccessCallback(pResource, pInvokingClient, pAllocParams, accessRight) stdmemAccessCallback_DISPATCH(pResource, pInvokingClient, pAllocParams, accessRight) -NvU32 stdmemGetSysmemPageSize_IMPL(struct OBJGPU *pGpu, struct StandardMemory *pMemory); +NvU64 stdmemGetSysmemPageSize_IMPL(struct OBJGPU *pGpu, struct StandardMemory *pMemory); #ifdef __nvoc_standard_mem_h_disabled -static inline NvU32 stdmemGetSysmemPageSize(struct OBJGPU *pGpu, struct StandardMemory *pMemory) { +static inline NvU64 stdmemGetSysmemPageSize(struct OBJGPU *pGpu, struct StandardMemory *pMemory) { NV_ASSERT_FAILED_PRECOMP("StandardMemory was disabled!"); return 0; } @@ -169,60 +173,76 @@ return pMemory->__stdmemCheckMemInterUnmap__(pMemory, bSubdeviceHandleProvided); } -static inline NV_STATUS stdmemControl_DISPATCH(struct StandardMemory *pMemory, CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { - return pMemory->__stdmemControl__(pMemory, pCallContext, pParams); +static inline NvBool stdmemShareCallback_DISPATCH(struct StandardMemory *pResource, struct RsClient *pInvokingClient, struct RsResourceRef *pParentRef, RS_SHARE_POLICY *pSharePolicy) { + return pResource->__stdmemShareCallback__(pResource, pInvokingClient, pParentRef, pSharePolicy); } -static inline NV_STATUS stdmemUnmap_DISPATCH(struct StandardMemory *pMemory, CALL_CONTEXT *pCallContext, RsCpuMapping *pCpuMapping) { - return pMemory->__stdmemUnmap__(pMemory, pCallContext, pCpuMapping); +static inline NV_STATUS stdmemMapTo_DISPATCH(struct StandardMemory *pResource, RS_RES_MAP_TO_PARAMS *pParams) { + return pResource->__stdmemMapTo__(pResource, pParams); } -static inline NV_STATUS stdmemGetMemInterMapParams_DISPATCH(struct StandardMemory *pMemory, RMRES_MEM_INTER_MAP_PARAMS *pParams) { - return pMemory->__stdmemGetMemInterMapParams__(pMemory, pParams); +static inline NV_STATUS stdmemGetMapAddrSpace_DISPATCH(struct StandardMemory *pMemory, CALL_CONTEXT *pCallContext, NvU32 mapFlags, NV_ADDRESS_SPACE *pAddrSpace) { + return pMemory->__stdmemGetMapAddrSpace__(pMemory, pCallContext, mapFlags, pAddrSpace); } -static inline NV_STATUS stdmemGetMemoryMappingDescriptor_DISPATCH(struct StandardMemory *pMemory, MEMORY_DESCRIPTOR **ppMemDesc) { - return pMemory->__stdmemGetMemoryMappingDescriptor__(pMemory, ppMemDesc); +static inline NvU32 stdmemGetRefCount_DISPATCH(struct StandardMemory *pResource) { + return pResource->__stdmemGetRefCount__(pResource); } -static inline NV_STATUS stdmemGetMapAddrSpace_DISPATCH(struct StandardMemory *pMemory, CALL_CONTEXT *pCallContext, NvU32 mapFlags, NV_ADDRESS_SPACE *pAddrSpace) { - return pMemory->__stdmemGetMapAddrSpace__(pMemory, pCallContext, mapFlags, pAddrSpace); +static inline void stdmemAddAdditionalDependants_DISPATCH(struct RsClient *pClient, struct StandardMemory *pResource, RsResourceRef *pReference) { + pResource->__stdmemAddAdditionalDependants__(pClient, pResource, pReference); } -static inline NvBool stdmemShareCallback_DISPATCH(struct StandardMemory *pResource, struct RsClient *pInvokingClient, struct RsResourceRef *pParentRef, RS_SHARE_POLICY *pSharePolicy) { - return pResource->__stdmemShareCallback__(pResource, pInvokingClient, pParentRef, pSharePolicy); +static inline NV_STATUS stdmemControl_Prologue_DISPATCH(struct StandardMemory *pResource, CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return pResource->__stdmemControl_Prologue__(pResource, pCallContext, pParams); } -static inline NV_STATUS stdmemControlFilter_DISPATCH(struct StandardMemory *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { - return pResource->__stdmemControlFilter__(pResource, pCallContext, pParams); +static inline NvBool stdmemIsGpuMapAllowed_DISPATCH(struct StandardMemory *pMemory, struct OBJGPU *pGpu) { + return pMemory->__stdmemIsGpuMapAllowed__(pMemory, pGpu); } -static inline void stdmemAddAdditionalDependants_DISPATCH(struct RsClient *pClient, struct StandardMemory *pResource, RsResourceRef *pReference) { - pResource->__stdmemAddAdditionalDependants__(pClient, pResource, pReference); +static inline NV_STATUS stdmemUnmapFrom_DISPATCH(struct StandardMemory *pResource, RS_RES_UNMAP_FROM_PARAMS *pParams) { + return pResource->__stdmemUnmapFrom__(pResource, pParams); } -static inline NvU32 stdmemGetRefCount_DISPATCH(struct StandardMemory *pResource) { - return pResource->__stdmemGetRefCount__(pResource); +static inline void stdmemControl_Epilogue_DISPATCH(struct StandardMemory *pResource, CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + pResource->__stdmemControl_Epilogue__(pResource, pCallContext, pParams); } -static inline NV_STATUS stdmemMapTo_DISPATCH(struct StandardMemory *pResource, RS_RES_MAP_TO_PARAMS *pParams) { - return pResource->__stdmemMapTo__(pResource, pParams); +static inline NV_STATUS stdmemControlLookup_DISPATCH(struct StandardMemory *pResource, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams, const struct NVOC_EXPORTED_METHOD_DEF **ppEntry) { + return pResource->__stdmemControlLookup__(pResource, pParams, ppEntry); } -static inline NV_STATUS stdmemControl_Prologue_DISPATCH(struct StandardMemory *pResource, CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { - return pResource->__stdmemControl_Prologue__(pResource, pCallContext, pParams); +static inline NV_STATUS stdmemControl_DISPATCH(struct StandardMemory *pMemory, CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return pMemory->__stdmemControl__(pMemory, pCallContext, pParams); } -static inline NvBool stdmemIsGpuMapAllowed_DISPATCH(struct StandardMemory *pMemory, struct OBJGPU *pGpu) { - return pMemory->__stdmemIsGpuMapAllowed__(pMemory, pGpu); +static inline NV_STATUS stdmemUnmap_DISPATCH(struct StandardMemory *pMemory, CALL_CONTEXT *pCallContext, RsCpuMapping *pCpuMapping) { + return pMemory->__stdmemUnmap__(pMemory, pCallContext, pCpuMapping); +} + +static inline NV_STATUS stdmemGetMemInterMapParams_DISPATCH(struct StandardMemory *pMemory, RMRES_MEM_INTER_MAP_PARAMS *pParams) { + return pMemory->__stdmemGetMemInterMapParams__(pMemory, pParams); +} + +static inline NV_STATUS stdmemGetMemoryMappingDescriptor_DISPATCH(struct StandardMemory *pMemory, MEMORY_DESCRIPTOR **ppMemDesc) { + return pMemory->__stdmemGetMemoryMappingDescriptor__(pMemory, ppMemDesc); +} + +static inline NV_STATUS stdmemControlFilter_DISPATCH(struct StandardMemory *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return pResource->__stdmemControlFilter__(pResource, pCallContext, pParams); +} + +static inline NV_STATUS stdmemControlSerialization_Prologue_DISPATCH(struct StandardMemory *pResource, CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return pResource->__stdmemControlSerialization_Prologue__(pResource, pCallContext, pParams); } static inline NV_STATUS stdmemIsReady_DISPATCH(struct StandardMemory *pMemory, NvBool bCopyConstructorContext) { return pMemory->__stdmemIsReady__(pMemory, bCopyConstructorContext); } -static inline NV_STATUS stdmemCheckCopyPermissions_DISPATCH(struct StandardMemory *pMemory, struct OBJGPU *pDstGpu, NvHandle hDstClientNvBool) { - return pMemory->__stdmemCheckCopyPermissions__(pMemory, pDstGpu, hDstClientNvBool); +static inline NV_STATUS stdmemCheckCopyPermissions_DISPATCH(struct StandardMemory *pMemory, struct OBJGPU *pDstGpu, struct Device *pDstDevice) { + return pMemory->__stdmemCheckCopyPermissions__(pMemory, pDstGpu, pDstDevice); } static inline void stdmemPreDestruct_DISPATCH(struct StandardMemory *pResource) { @@ -233,16 +253,8 @@ return pMemory->__stdmemIsDuplicate__(pMemory, hMemory, pDuplicate); } -static inline NV_STATUS stdmemUnmapFrom_DISPATCH(struct StandardMemory *pResource, RS_RES_UNMAP_FROM_PARAMS *pParams) { - return pResource->__stdmemUnmapFrom__(pResource, pParams); -} - -static inline void stdmemControl_Epilogue_DISPATCH(struct StandardMemory *pResource, CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { - pResource->__stdmemControl_Epilogue__(pResource, pCallContext, pParams); -} - -static inline NV_STATUS stdmemControlLookup_DISPATCH(struct StandardMemory *pResource, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams, const struct NVOC_EXPORTED_METHOD_DEF **ppEntry) { - return pResource->__stdmemControlLookup__(pResource, pParams, ppEntry); +static inline void stdmemControlSerialization_Epilogue_DISPATCH(struct StandardMemory *pResource, CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + pResource->__stdmemControlSerialization_Epilogue__(pResource, pCallContext, pParams); } static inline NV_STATUS stdmemMap_DISPATCH(struct StandardMemory *pMemory, CALL_CONTEXT *pCallContext, struct RS_CPU_MAP_PARAMS *pParams, RsCpuMapping *pCpuMapping) { @@ -265,7 +277,7 @@ void stdmemDumpOutputAllocParams_IMPL(NV_MEMORY_ALLOCATION_PARAMS *pAllocData); #define stdmemDumpOutputAllocParams(pAllocData) stdmemDumpOutputAllocParams_IMPL(pAllocData) -NvU32 stdmemQueryPageSize_IMPL(struct MemoryManager *pMemoryManager, NvHandle hClient, NV_MEMORY_ALLOCATION_PARAMS *pAllocData); +NvU64 stdmemQueryPageSize_IMPL(struct MemoryManager *pMemoryManager, NvHandle hClient, NV_MEMORY_ALLOCATION_PARAMS *pAllocData); #define stdmemQueryPageSize(pMemoryManager, hClient, pAllocData) stdmemQueryPageSize_IMPL(pMemoryManager, hClient, pAllocData) #undef PRIVATE_FIELD diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/generated/g_subdevice_diag_nvoc.c nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_subdevice_diag_nvoc.c --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/generated/g_subdevice_diag_nvoc.c 2023-10-25 20:27:19.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_subdevice_diag_nvoc.c 2024-03-05 22:18:45.000000000 +0000 @@ -123,16 +123,16 @@ return gpuresShareCallback((struct GpuResource *)(((unsigned char *)pGpuResource) + __nvoc_rtti_DiagApi_GpuResource.offset), pInvokingClient, pParentRef, pSharePolicy); } -static NV_STATUS __nvoc_thunk_RsResource_diagapiMapTo(struct DiagApi *pResource, RS_RES_MAP_TO_PARAMS *pParams) { - return resMapTo((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_DiagApi_RsResource.offset), pParams); +static NV_STATUS __nvoc_thunk_RmResource_diagapiCheckMemInterUnmap(struct DiagApi *pRmResource, NvBool bSubdeviceHandleProvided) { + return rmresCheckMemInterUnmap((struct RmResource *)(((unsigned char *)pRmResource) + __nvoc_rtti_DiagApi_RmResource.offset), bSubdeviceHandleProvided); } static NV_STATUS __nvoc_thunk_Notifier_diagapiGetOrAllocNotifShare(struct DiagApi *pNotifier, NvHandle hNotifierClient, NvHandle hNotifierResource, struct NotifShare **ppNotifShare) { return notifyGetOrAllocNotifShare((struct Notifier *)(((unsigned char *)pNotifier) + __nvoc_rtti_DiagApi_Notifier.offset), hNotifierClient, hNotifierResource, ppNotifShare); } -static NV_STATUS __nvoc_thunk_RmResource_diagapiCheckMemInterUnmap(struct DiagApi *pRmResource, NvBool bSubdeviceHandleProvided) { - return rmresCheckMemInterUnmap((struct RmResource *)(((unsigned char *)pRmResource) + __nvoc_rtti_DiagApi_RmResource.offset), bSubdeviceHandleProvided); +static NV_STATUS __nvoc_thunk_RsResource_diagapiMapTo(struct DiagApi *pResource, RS_RES_MAP_TO_PARAMS *pParams) { + return resMapTo((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_DiagApi_RsResource.offset), pParams); } static NV_STATUS __nvoc_thunk_GpuResource_diagapiGetMapAddrSpace(struct DiagApi *pGpuResource, struct CALL_CONTEXT *pCallContext, NvU32 mapFlags, NV_ADDRESS_SPACE *pAddrSpace) { @@ -195,6 +195,10 @@ return notifyUnregisterEvent((struct Notifier *)(((unsigned char *)pNotifier) + __nvoc_rtti_DiagApi_Notifier.offset), hNotifierClient, hNotifierResource, hEventClient, hEvent); } +static NV_STATUS __nvoc_thunk_RmResource_diagapiControlSerialization_Prologue(struct DiagApi *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return rmresControlSerialization_Prologue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_DiagApi_RmResource.offset), pCallContext, pParams); +} + static NvBool __nvoc_thunk_RsResource_diagapiCanCopy(struct DiagApi *pResource) { return resCanCopy((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_DiagApi_RsResource.offset)); } @@ -207,6 +211,10 @@ return resIsDuplicate((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_DiagApi_RsResource.offset), hMemory, pDuplicate); } +static void __nvoc_thunk_RmResource_diagapiControlSerialization_Epilogue(struct DiagApi *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + rmresControlSerialization_Epilogue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_DiagApi_RmResource.offset), pCallContext, pParams); +} + static PEVENTNOTIFICATION *__nvoc_thunk_Notifier_diagapiGetNotificationListPtr(struct DiagApi *pNotifier) { return notifyGetNotificationListPtr((struct Notifier *)(((unsigned char *)pNotifier) + __nvoc_rtti_DiagApi_Notifier.offset)); } @@ -534,11 +542,11 @@ pThis->__diagapiShareCallback__ = &__nvoc_thunk_GpuResource_diagapiShareCallback; - pThis->__diagapiMapTo__ = &__nvoc_thunk_RsResource_diagapiMapTo; + pThis->__diagapiCheckMemInterUnmap__ = &__nvoc_thunk_RmResource_diagapiCheckMemInterUnmap; pThis->__diagapiGetOrAllocNotifShare__ = &__nvoc_thunk_Notifier_diagapiGetOrAllocNotifShare; - pThis->__diagapiCheckMemInterUnmap__ = &__nvoc_thunk_RmResource_diagapiCheckMemInterUnmap; + pThis->__diagapiMapTo__ = &__nvoc_thunk_RsResource_diagapiMapTo; pThis->__diagapiGetMapAddrSpace__ = &__nvoc_thunk_GpuResource_diagapiGetMapAddrSpace; @@ -570,12 +578,16 @@ pThis->__diagapiUnregisterEvent__ = &__nvoc_thunk_Notifier_diagapiUnregisterEvent; + pThis->__diagapiControlSerialization_Prologue__ = &__nvoc_thunk_RmResource_diagapiControlSerialization_Prologue; + pThis->__diagapiCanCopy__ = &__nvoc_thunk_RsResource_diagapiCanCopy; pThis->__diagapiPreDestruct__ = &__nvoc_thunk_RsResource_diagapiPreDestruct; pThis->__diagapiIsDuplicate__ = &__nvoc_thunk_RsResource_diagapiIsDuplicate; + pThis->__diagapiControlSerialization_Epilogue__ = &__nvoc_thunk_RmResource_diagapiControlSerialization_Epilogue; + pThis->__diagapiGetNotificationListPtr__ = &__nvoc_thunk_Notifier_diagapiGetNotificationListPtr; pThis->__diagapiGetNotificationShare__ = &__nvoc_thunk_Notifier_diagapiGetNotificationShare; @@ -610,13 +622,16 @@ Object *pParentObj; DiagApi *pThis; - pThis = portMemAllocNonPaged(sizeof(DiagApi)); - if (pThis == NULL) return NV_ERR_NO_MEMORY; + status = __nvoc_handleObjCreateMemAlloc(createFlags, sizeof(DiagApi), (void**)&pThis, (void**)ppThis); + if (status != NV_OK) + return status; portMemSet(pThis, 0, sizeof(DiagApi)); __nvoc_initRtti(staticCast(pThis, Dynamic), &__nvoc_class_def_DiagApi); + pThis->__nvoc_base_GpuResource.__nvoc_base_RmResource.__nvoc_base_RsResource.__nvoc_base_Object.createFlags = createFlags; + if (pParent != NULL && !(createFlags & NVOC_OBJ_CREATE_FLAGS_PARENT_HALSPEC_ONLY)) { pParentObj = dynamicCast(pParent, Object); @@ -632,11 +647,17 @@ if (status != NV_OK) goto __nvoc_objCreate_DiagApi_cleanup; *ppThis = pThis; + return NV_OK; __nvoc_objCreate_DiagApi_cleanup: // do not call destructors here since the constructor already called them - portMemFree(pThis); + if (createFlags & NVOC_OBJ_CREATE_FLAGS_IN_PLACE_CONSTRUCT) + portMemSet(pThis, 0, sizeof(DiagApi)); + else + portMemFree(pThis); + + // coverity[leaked_storage:FALSE] return status; } diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/generated/g_subdevice_diag_nvoc.h nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_subdevice_diag_nvoc.h --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/generated/g_subdevice_diag_nvoc.h 2023-10-25 20:27:19.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_subdevice_diag_nvoc.h 2024-03-05 22:18:46.000000000 +0000 @@ -77,9 +77,9 @@ NV_STATUS (*__diagapiCtrlCmdBifConfigRegWrite__)(struct DiagApi *, NV208F_CTRL_BIF_CONFIG_REG_WRITE_PARAMS *); NV_STATUS (*__diagapiCtrlCmdBifInfo__)(struct DiagApi *, NV208F_CTRL_BIF_INFO_PARAMS *); NvBool (*__diagapiShareCallback__)(struct DiagApi *, struct RsClient *, struct RsResourceRef *, RS_SHARE_POLICY *); - NV_STATUS (*__diagapiMapTo__)(struct DiagApi *, RS_RES_MAP_TO_PARAMS *); - NV_STATUS (*__diagapiGetOrAllocNotifShare__)(struct DiagApi *, NvHandle, NvHandle, struct NotifShare **); NV_STATUS (*__diagapiCheckMemInterUnmap__)(struct DiagApi *, NvBool); + NV_STATUS (*__diagapiGetOrAllocNotifShare__)(struct DiagApi *, NvHandle, NvHandle, struct NotifShare **); + NV_STATUS (*__diagapiMapTo__)(struct DiagApi *, RS_RES_MAP_TO_PARAMS *); NV_STATUS (*__diagapiGetMapAddrSpace__)(struct DiagApi *, struct CALL_CONTEXT *, NvU32, NV_ADDRESS_SPACE *); void (*__diagapiSetNotificationShare__)(struct DiagApi *, struct NotifShare *); NvU32 (*__diagapiGetRefCount__)(struct DiagApi *); @@ -95,9 +95,11 @@ NV_STATUS (*__diagapiGetMemInterMapParams__)(struct DiagApi *, RMRES_MEM_INTER_MAP_PARAMS *); NV_STATUS (*__diagapiGetMemoryMappingDescriptor__)(struct DiagApi *, struct MEMORY_DESCRIPTOR **); NV_STATUS (*__diagapiUnregisterEvent__)(struct DiagApi *, NvHandle, NvHandle, NvHandle, NvHandle); + NV_STATUS (*__diagapiControlSerialization_Prologue__)(struct DiagApi *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); NvBool (*__diagapiCanCopy__)(struct DiagApi *); void (*__diagapiPreDestruct__)(struct DiagApi *); NV_STATUS (*__diagapiIsDuplicate__)(struct DiagApi *, NvHandle, NvBool *); + void (*__diagapiControlSerialization_Epilogue__)(struct DiagApi *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); PEVENTNOTIFICATION *(*__diagapiGetNotificationListPtr__)(struct DiagApi *); struct NotifShare *(*__diagapiGetNotificationShare__)(struct DiagApi *); NV_STATUS (*__diagapiMap__)(struct DiagApi *, struct CALL_CONTEXT *, struct RS_CPU_MAP_PARAMS *, struct RsCpuMapping *); @@ -149,9 +151,9 @@ #define diagapiCtrlCmdBifConfigRegWrite(pDiagApi, pWriteConfigReg) diagapiCtrlCmdBifConfigRegWrite_DISPATCH(pDiagApi, pWriteConfigReg) #define diagapiCtrlCmdBifInfo(pDiagApi, pInfo) diagapiCtrlCmdBifInfo_DISPATCH(pDiagApi, pInfo) #define diagapiShareCallback(pGpuResource, pInvokingClient, pParentRef, pSharePolicy) diagapiShareCallback_DISPATCH(pGpuResource, pInvokingClient, pParentRef, pSharePolicy) -#define diagapiMapTo(pResource, pParams) diagapiMapTo_DISPATCH(pResource, pParams) -#define diagapiGetOrAllocNotifShare(pNotifier, hNotifierClient, hNotifierResource, ppNotifShare) diagapiGetOrAllocNotifShare_DISPATCH(pNotifier, hNotifierClient, hNotifierResource, ppNotifShare) #define diagapiCheckMemInterUnmap(pRmResource, bSubdeviceHandleProvided) diagapiCheckMemInterUnmap_DISPATCH(pRmResource, bSubdeviceHandleProvided) +#define diagapiGetOrAllocNotifShare(pNotifier, hNotifierClient, hNotifierResource, ppNotifShare) diagapiGetOrAllocNotifShare_DISPATCH(pNotifier, hNotifierClient, hNotifierResource, ppNotifShare) +#define diagapiMapTo(pResource, pParams) diagapiMapTo_DISPATCH(pResource, pParams) #define diagapiGetMapAddrSpace(pGpuResource, pCallContext, mapFlags, pAddrSpace) diagapiGetMapAddrSpace_DISPATCH(pGpuResource, pCallContext, mapFlags, pAddrSpace) #define diagapiSetNotificationShare(pNotifier, pNotifShare) diagapiSetNotificationShare_DISPATCH(pNotifier, pNotifShare) #define diagapiGetRefCount(pResource) diagapiGetRefCount_DISPATCH(pResource) @@ -167,9 +169,11 @@ #define diagapiGetMemInterMapParams(pRmResource, pParams) diagapiGetMemInterMapParams_DISPATCH(pRmResource, pParams) #define diagapiGetMemoryMappingDescriptor(pRmResource, ppMemDesc) diagapiGetMemoryMappingDescriptor_DISPATCH(pRmResource, ppMemDesc) #define diagapiUnregisterEvent(pNotifier, hNotifierClient, hNotifierResource, hEventClient, hEvent) diagapiUnregisterEvent_DISPATCH(pNotifier, hNotifierClient, hNotifierResource, hEventClient, hEvent) +#define diagapiControlSerialization_Prologue(pResource, pCallContext, pParams) diagapiControlSerialization_Prologue_DISPATCH(pResource, pCallContext, pParams) #define diagapiCanCopy(pResource) diagapiCanCopy_DISPATCH(pResource) #define diagapiPreDestruct(pResource) diagapiPreDestruct_DISPATCH(pResource) #define diagapiIsDuplicate(pResource, hMemory, pDuplicate) diagapiIsDuplicate_DISPATCH(pResource, hMemory, pDuplicate) +#define diagapiControlSerialization_Epilogue(pResource, pCallContext, pParams) diagapiControlSerialization_Epilogue_DISPATCH(pResource, pCallContext, pParams) #define diagapiGetNotificationListPtr(pNotifier) diagapiGetNotificationListPtr_DISPATCH(pNotifier) #define diagapiGetNotificationShare(pNotifier) diagapiGetNotificationShare_DISPATCH(pNotifier) #define diagapiMap(pGpuResource, pCallContext, pParams, pCpuMapping) diagapiMap_DISPATCH(pGpuResource, pCallContext, pParams, pCpuMapping) @@ -268,16 +272,16 @@ return pGpuResource->__diagapiShareCallback__(pGpuResource, pInvokingClient, pParentRef, pSharePolicy); } -static inline NV_STATUS diagapiMapTo_DISPATCH(struct DiagApi *pResource, RS_RES_MAP_TO_PARAMS *pParams) { - return pResource->__diagapiMapTo__(pResource, pParams); +static inline NV_STATUS diagapiCheckMemInterUnmap_DISPATCH(struct DiagApi *pRmResource, NvBool bSubdeviceHandleProvided) { + return pRmResource->__diagapiCheckMemInterUnmap__(pRmResource, bSubdeviceHandleProvided); } static inline NV_STATUS diagapiGetOrAllocNotifShare_DISPATCH(struct DiagApi *pNotifier, NvHandle hNotifierClient, NvHandle hNotifierResource, struct NotifShare **ppNotifShare) { return pNotifier->__diagapiGetOrAllocNotifShare__(pNotifier, hNotifierClient, hNotifierResource, ppNotifShare); } -static inline NV_STATUS diagapiCheckMemInterUnmap_DISPATCH(struct DiagApi *pRmResource, NvBool bSubdeviceHandleProvided) { - return pRmResource->__diagapiCheckMemInterUnmap__(pRmResource, bSubdeviceHandleProvided); +static inline NV_STATUS diagapiMapTo_DISPATCH(struct DiagApi *pResource, RS_RES_MAP_TO_PARAMS *pParams) { + return pResource->__diagapiMapTo__(pResource, pParams); } static inline NV_STATUS diagapiGetMapAddrSpace_DISPATCH(struct DiagApi *pGpuResource, struct CALL_CONTEXT *pCallContext, NvU32 mapFlags, NV_ADDRESS_SPACE *pAddrSpace) { @@ -340,6 +344,10 @@ return pNotifier->__diagapiUnregisterEvent__(pNotifier, hNotifierClient, hNotifierResource, hEventClient, hEvent); } +static inline NV_STATUS diagapiControlSerialization_Prologue_DISPATCH(struct DiagApi *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return pResource->__diagapiControlSerialization_Prologue__(pResource, pCallContext, pParams); +} + static inline NvBool diagapiCanCopy_DISPATCH(struct DiagApi *pResource) { return pResource->__diagapiCanCopy__(pResource); } @@ -352,6 +360,10 @@ return pResource->__diagapiIsDuplicate__(pResource, hMemory, pDuplicate); } +static inline void diagapiControlSerialization_Epilogue_DISPATCH(struct DiagApi *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + pResource->__diagapiControlSerialization_Epilogue__(pResource, pCallContext, pParams); +} + static inline PEVENTNOTIFICATION *diagapiGetNotificationListPtr_DISPATCH(struct DiagApi *pNotifier) { return pNotifier->__diagapiGetNotificationListPtr__(pNotifier); } diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/generated/g_subdevice_nvoc.c nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_subdevice_nvoc.c --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/generated/g_subdevice_nvoc.c 2023-10-25 20:27:19.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_subdevice_nvoc.c 2024-03-05 22:18:46.000000000 +0000 @@ -127,16 +127,16 @@ return gpuresShareCallback((struct GpuResource *)(((unsigned char *)pGpuResource) + __nvoc_rtti_Subdevice_GpuResource.offset), pInvokingClient, pParentRef, pSharePolicy); } -static NV_STATUS __nvoc_thunk_RsResource_subdeviceMapTo(struct Subdevice *pResource, RS_RES_MAP_TO_PARAMS *pParams) { - return resMapTo((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_Subdevice_RsResource.offset), pParams); +static NV_STATUS __nvoc_thunk_RmResource_subdeviceCheckMemInterUnmap(struct Subdevice *pRmResource, NvBool bSubdeviceHandleProvided) { + return rmresCheckMemInterUnmap((struct RmResource *)(((unsigned char *)pRmResource) + __nvoc_rtti_Subdevice_RmResource.offset), bSubdeviceHandleProvided); } static NV_STATUS __nvoc_thunk_Notifier_subdeviceGetOrAllocNotifShare(struct Subdevice *pNotifier, NvHandle hNotifierClient, NvHandle hNotifierResource, struct NotifShare **ppNotifShare) { return notifyGetOrAllocNotifShare((struct Notifier *)(((unsigned char *)pNotifier) + __nvoc_rtti_Subdevice_Notifier.offset), hNotifierClient, hNotifierResource, ppNotifShare); } -static NV_STATUS __nvoc_thunk_RmResource_subdeviceCheckMemInterUnmap(struct Subdevice *pRmResource, NvBool bSubdeviceHandleProvided) { - return rmresCheckMemInterUnmap((struct RmResource *)(((unsigned char *)pRmResource) + __nvoc_rtti_Subdevice_RmResource.offset), bSubdeviceHandleProvided); +static NV_STATUS __nvoc_thunk_RsResource_subdeviceMapTo(struct Subdevice *pResource, RS_RES_MAP_TO_PARAMS *pParams) { + return resMapTo((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_Subdevice_RsResource.offset), pParams); } static NV_STATUS __nvoc_thunk_GpuResource_subdeviceGetMapAddrSpace(struct Subdevice *pGpuResource, struct CALL_CONTEXT *pCallContext, NvU32 mapFlags, NV_ADDRESS_SPACE *pAddrSpace) { @@ -199,6 +199,10 @@ return notifyUnregisterEvent((struct Notifier *)(((unsigned char *)pNotifier) + __nvoc_rtti_Subdevice_Notifier.offset), hNotifierClient, hNotifierResource, hEventClient, hEvent); } +static NV_STATUS __nvoc_thunk_RmResource_subdeviceControlSerialization_Prologue(struct Subdevice *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return rmresControlSerialization_Prologue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_Subdevice_RmResource.offset), pCallContext, pParams); +} + static NvBool __nvoc_thunk_RsResource_subdeviceCanCopy(struct Subdevice *pResource) { return resCanCopy((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_Subdevice_RsResource.offset)); } @@ -207,6 +211,10 @@ return resIsDuplicate((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_Subdevice_RsResource.offset), hMemory, pDuplicate); } +static void __nvoc_thunk_RmResource_subdeviceControlSerialization_Epilogue(struct Subdevice *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + rmresControlSerialization_Epilogue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_Subdevice_RmResource.offset), pCallContext, pParams); +} + static PEVENTNOTIFICATION *__nvoc_thunk_Notifier_subdeviceGetNotificationListPtr(struct Subdevice *pNotifier) { return notifyGetNotificationListPtr((struct Notifier *)(((unsigned char *)pNotifier) + __nvoc_rtti_Subdevice_Notifier.offset)); } @@ -230,12 +238,12 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevice[] = { { /* [0] */ -#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x850u) +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x200850u) /*pFunc=*/ (void (*)(void)) NULL, #else /*pFunc=*/ (void (*)(void)) subdeviceCtrlCmdGpuGetInfoV2_IMPL, -#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x850u) - /*flags=*/ 0x850u, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x200850u) + /*flags=*/ 0x200850u, /*accessRight=*/0x0u, /*methodId=*/ 0x20800102u, /*paramSize=*/ sizeof(NV2080_CTRL_GPU_GET_INFO_V2_PARAMS), @@ -245,12 +253,12 @@ #endif }, { /* [1] */ -#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0xa12u) +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x200a12u) /*pFunc=*/ (void (*)(void)) NULL, #else /*pFunc=*/ (void (*)(void)) subdeviceCtrlCmdGpuGetNameString_IMPL, -#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0xa12u) - /*flags=*/ 0xa12u, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x200a12u) + /*flags=*/ 0x200a12u, /*accessRight=*/0x0u, /*methodId=*/ 0x20800110u, /*paramSize=*/ sizeof(NV2080_CTRL_GPU_GET_NAME_STRING_PARAMS), @@ -305,12 +313,12 @@ #endif }, { /* [5] */ -#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x813u) +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x4813u) /*pFunc=*/ (void (*)(void)) NULL, #else /*pFunc=*/ (void (*)(void)) subdeviceCtrlCmdGpuGetSimulationInfo_IMPL, -#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x813u) - /*flags=*/ 0x813u, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x4813u) + /*flags=*/ 0x4813u, /*accessRight=*/0x0u, /*methodId=*/ 0x20800119u, /*paramSize=*/ sizeof(NV2080_CTRL_GPU_GET_SIMULATION_INFO_PARAMS), @@ -335,12 +343,12 @@ #endif }, { /* [7] */ -#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x850u) /*pFunc=*/ (void (*)(void)) NULL, #else /*pFunc=*/ (void (*)(void)) subdeviceCtrlCmdGpuExecRegOps_IMPL, -#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) - /*flags=*/ 0x10u, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x850u) + /*flags=*/ 0x850u, /*accessRight=*/0x0u, /*methodId=*/ 0x20800122u, /*paramSize=*/ sizeof(NV2080_CTRL_GPU_EXEC_REG_OPS_PARAMS), @@ -485,12 +493,12 @@ #endif }, { /* [17] */ -#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x11u) +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x811u) /*pFunc=*/ (void (*)(void)) NULL, #else /*pFunc=*/ (void (*)(void)) subdeviceCtrlCmdGpuQueryComputeModeRules_IMPL, -#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x11u) - /*flags=*/ 0x11u, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x811u) + /*flags=*/ 0x811u, /*accessRight=*/0x0u, /*methodId=*/ 0x20800131u, /*paramSize=*/ sizeof(NV2080_CTRL_GPU_QUERY_COMPUTE_MODE_RULES_PARAMS), @@ -575,12 +583,12 @@ #endif }, { /* [23] */ -#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x850u) /*pFunc=*/ (void (*)(void)) NULL, #else /*pFunc=*/ (void (*)(void)) subdeviceCtrlCmdGpuGetFermiZcullInfo_IMPL, -#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) - /*flags=*/ 0x10u, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x850u) + /*flags=*/ 0x850u, /*accessRight=*/0x0u, /*methodId=*/ 0x20800139u, /*paramSize=*/ sizeof(NV2080_CTRL_GPU_GET_FERMI_ZCULL_INFO_PARAMS), @@ -620,12 +628,12 @@ #endif }, { /* [26] */ -#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x11u) +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x850u) /*pFunc=*/ (void (*)(void)) NULL, #else /*pFunc=*/ (void (*)(void)) subdeviceCtrlCmdGpuAcquireComputeModeReservation_IMPL, -#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x11u) - /*flags=*/ 0x11u, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x850u) + /*flags=*/ 0x850u, /*accessRight=*/0x0u, /*methodId=*/ 0x20800145u, /*paramSize=*/ 0, @@ -635,12 +643,12 @@ #endif }, { /* [27] */ -#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x11u) +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x850u) /*pFunc=*/ (void (*)(void)) NULL, #else /*pFunc=*/ (void (*)(void)) subdeviceCtrlCmdGpuReleaseComputeModeReservation_IMPL, -#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x11u) - /*flags=*/ 0x11u, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x850u) + /*flags=*/ 0x850u, /*accessRight=*/0x0u, /*methodId=*/ 0x20800146u, /*paramSize=*/ 0, @@ -860,12 +868,12 @@ #endif }, { /* [42] */ -#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x13u) +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x3u) /*pFunc=*/ (void (*)(void)) NULL, #else /*pFunc=*/ (void (*)(void)) subdeviceCtrlCmdGpuHandleGpuSR_IMPL, -#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x13u) - /*flags=*/ 0x13u, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x3u) + /*flags=*/ 0x3u, /*accessRight=*/0x0u, /*methodId=*/ 0x20800167u, /*paramSize=*/ 0, @@ -1115,6 +1123,21 @@ #endif }, { /* [59] */ +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x4210u) + /*pFunc=*/ (void (*)(void)) NULL, +#else + /*pFunc=*/ (void (*)(void)) subdeviceCtrlCmdGpuGetVmmuSegmentSize_IMPL, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x4210u) + /*flags=*/ 0x4210u, + /*accessRight=*/0x0u, + /*methodId=*/ 0x2080017eu, + /*paramSize=*/ sizeof(NV2080_CTRL_GPU_GET_VMMU_SEGMENT_SIZE_PARAMS), + /*pClassInfo=*/ &(__nvoc_class_def_Subdevice.classInfo), +#if NV_PRINTF_STRINGS_ALLOWED + /*func=*/ "subdeviceCtrlCmdGpuGetVmmuSegmentSize" +#endif + }, + { /* [60] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -1129,7 +1152,7 @@ /*func=*/ "subdeviceCtrlCmdGpuGetPartitionCapacity" #endif }, - { /* [60] */ + { /* [61] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x813u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -1144,7 +1167,7 @@ /*func=*/ "subdeviceCtrlCmdGpuGetCachedInfo" #endif }, - { /* [61] */ + { /* [62] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x4u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -1159,7 +1182,7 @@ /*func=*/ "subdeviceCtrlCmdGpuSetPartitioningMode" #endif }, - { /* [62] */ + { /* [63] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -1174,7 +1197,7 @@ /*func=*/ "subdeviceCtrlCmdGpuDescribePartitions" #endif }, - { /* [63] */ + { /* [64] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x50u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -1189,7 +1212,7 @@ /*func=*/ "subdeviceCtrlCmdGpuGetMaxSupportedPageSize" #endif }, - { /* [64] */ + { /* [65] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -1204,7 +1227,7 @@ /*func=*/ "subdeviceCtrlCmdGpuGetActivePartitionIds" #endif }, - { /* [65] */ + { /* [66] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -1219,7 +1242,7 @@ /*func=*/ "subdeviceCtrlCmdGpuGetPids" #endif }, - { /* [66] */ + { /* [67] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -1234,7 +1257,7 @@ /*func=*/ "subdeviceCtrlCmdGpuGetPidInfo" #endif }, - { /* [67] */ + { /* [68] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x2210u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -1249,13 +1272,13 @@ /*func=*/ "subdeviceCtrlCmdGpuHandleVfPriFault" #endif }, - { /* [68] */ -#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x4u) + { /* [69] */ +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x807u) /*pFunc=*/ (void (*)(void)) NULL, #else /*pFunc=*/ (void (*)(void)) subdeviceCtrlCmdGpuSetComputePolicyConfig_IMPL, -#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x4u) - /*flags=*/ 0x4u, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x807u) + /*flags=*/ 0x807u, /*accessRight=*/0x0u, /*methodId=*/ 0x20800194u, /*paramSize=*/ sizeof(NV2080_CTRL_GPU_SET_COMPUTE_POLICY_CONFIG_PARAMS), @@ -1264,13 +1287,13 @@ /*func=*/ "subdeviceCtrlCmdGpuSetComputePolicyConfig" #endif }, - { /* [69] */ -#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) + { /* [70] */ +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x813u) /*pFunc=*/ (void (*)(void)) NULL, #else /*pFunc=*/ (void (*)(void)) subdeviceCtrlCmdGpuGetComputePolicyConfig_IMPL, -#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) - /*flags=*/ 0x10u, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x813u) + /*flags=*/ 0x813u, /*accessRight=*/0x0u, /*methodId=*/ 0x20800195u, /*paramSize=*/ sizeof(NV2080_CTRL_GPU_GET_COMPUTE_POLICY_CONFIG_PARAMS), @@ -1279,7 +1302,7 @@ /*func=*/ "subdeviceCtrlCmdGpuGetComputePolicyConfig" #endif }, - { /* [70] */ + { /* [71] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -1294,7 +1317,7 @@ /*func=*/ "subdeviceCtrlCmdGpuGetGfid" #endif }, - { /* [71] */ + { /* [72] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x4u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -1309,13 +1332,13 @@ /*func=*/ "subdeviceCtrlCmdUpdateGfidP2pCapability" #endif }, - { /* [72] */ -#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x0u) + { /* [73] */ +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x840u) /*pFunc=*/ (void (*)(void)) NULL, #else /*pFunc=*/ (void (*)(void)) subdeviceCtrlCmdValidateMemMapRequest_IMPL, -#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x0u) - /*flags=*/ 0x0u, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x840u) + /*flags=*/ 0x840u, /*accessRight=*/0x0u, /*methodId=*/ 0x20800198u, /*paramSize=*/ sizeof(NV2080_CTRL_GPU_VALIDATE_MEM_MAP_REQUEST_PARAMS), @@ -1324,7 +1347,22 @@ /*func=*/ "subdeviceCtrlCmdValidateMemMapRequest" #endif }, - { /* [73] */ + { /* [74] */ +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) + /*pFunc=*/ (void (*)(void)) NULL, +#else + /*pFunc=*/ (void (*)(void)) subdeviceCtrlCmdGpuSetEgmGpaFabricAddr_IMPL, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) + /*flags=*/ 0x10u, + /*accessRight=*/0x0u, + /*methodId=*/ 0x20800199u, + /*paramSize=*/ sizeof(NV2080_CTRL_GPU_SET_EGM_GPA_FABRIC_BASE_ADDR_PARAMS), + /*pClassInfo=*/ &(__nvoc_class_def_Subdevice.classInfo), +#if NV_PRINTF_STRINGS_ALLOWED + /*func=*/ "subdeviceCtrlCmdGpuSetEgmGpaFabricAddr" +#endif + }, + { /* [75] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x12u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -1339,7 +1377,7 @@ /*func=*/ "subdeviceCtrlCmdGpuGetEngineLoadTimes" #endif }, - { /* [74] */ + { /* [76] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -1354,7 +1392,7 @@ /*func=*/ "subdeviceCtrlCmdGetP2pCaps" #endif }, - { /* [75] */ + { /* [77] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -1369,13 +1407,13 @@ /*func=*/ "subdeviceCtrlCmdGpuGetComputeProfiles" #endif }, - { /* [76] */ -#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x50u) + { /* [78] */ +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x850u) /*pFunc=*/ (void (*)(void)) NULL, #else /*pFunc=*/ (void (*)(void)) subdeviceCtrlCmdGetGpuFabricProbeInfo_IMPL, -#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x50u) - /*flags=*/ 0x50u, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x850u) + /*flags=*/ 0x850u, /*accessRight=*/0x0u, /*methodId=*/ 0x208001a3u, /*paramSize=*/ sizeof(NV2080_CTRL_CMD_GET_GPU_FABRIC_PROBE_INFO_PARAMS), @@ -1384,7 +1422,7 @@ /*func=*/ "subdeviceCtrlCmdGetGpuFabricProbeInfo" #endif }, - { /* [77] */ + { /* [79] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x4210u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -1399,13 +1437,13 @@ /*func=*/ "subdeviceCtrlCmdGpuGetChipDetails" #endif }, - { /* [78] */ -#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) + { /* [80] */ +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x850u) /*pFunc=*/ (void (*)(void)) NULL, #else /*pFunc=*/ (void (*)(void)) subdeviceCtrlCmdGpuMigratableOps_IMPL, -#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) - /*flags=*/ 0x10u, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x850u) + /*flags=*/ 0x850u, /*accessRight=*/0x0u, /*methodId=*/ 0x208001a6u, /*paramSize=*/ sizeof(NV2080_CTRL_GPU_MIGRATABLE_OPS_PARAMS), @@ -1414,7 +1452,37 @@ /*func=*/ "subdeviceCtrlCmdGpuMigratableOps" #endif }, - { /* [79] */ + { /* [81] */ +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) + /*pFunc=*/ (void (*)(void)) NULL, +#else + /*pFunc=*/ (void (*)(void)) subdeviceCtrlCmdGpuGetResetStatus_IMPL, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) + /*flags=*/ 0x210u, + /*accessRight=*/0x0u, + /*methodId=*/ 0x208001abu, + /*paramSize=*/ sizeof(NV2080_CTRL_GPU_GET_RESET_STATUS_PARAMS), + /*pClassInfo=*/ &(__nvoc_class_def_Subdevice.classInfo), +#if NV_PRINTF_STRINGS_ALLOWED + /*func=*/ "subdeviceCtrlCmdGpuGetResetStatus" +#endif + }, + { /* [82] */ +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) + /*pFunc=*/ (void (*)(void)) NULL, +#else + /*pFunc=*/ (void (*)(void)) subdeviceCtrlCmdGpuGetDrainAndResetStatus_IMPL, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) + /*flags=*/ 0x210u, + /*accessRight=*/0x0u, + /*methodId=*/ 0x208001aeu, + /*paramSize=*/ sizeof(NV2080_CTRL_GPU_GET_DRAIN_AND_RESET_STATUS_PARAMS), + /*pClassInfo=*/ &(__nvoc_class_def_Subdevice.classInfo), +#if NV_PRINTF_STRINGS_ALLOWED + /*func=*/ "subdeviceCtrlCmdGpuGetDrainAndResetStatus" +#endif + }, + { /* [83] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -1422,14 +1490,29 @@ #endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) /*flags=*/ 0x210u, /*accessRight=*/0x0u, - /*methodId=*/ 0x208001a9u, + /*methodId=*/ 0x208001afu, /*paramSize=*/ sizeof(NV2080_CTRL_GPU_GET_NVENC_SW_SESSION_INFO_V2_PARAMS), /*pClassInfo=*/ &(__nvoc_class_def_Subdevice.classInfo), #if NV_PRINTF_STRINGS_ALLOWED /*func=*/ "subdeviceCtrlCmdGpuGetNvencSwSessionInfoV2" #endif }, - { /* [80] */ + { /* [84] */ +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) + /*pFunc=*/ (void (*)(void)) NULL, +#else + /*pFunc=*/ (void (*)(void)) subdeviceCtrlCmdInternalConfComputeEncryptionControl_IMPL, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) + /*flags=*/ 0x600u, + /*accessRight=*/0x0u, + /*methodId=*/ 0x208001b2u, + /*paramSize=*/ sizeof(NV2080_CTRL_CMD_INTERNAL_CONF_COMPUTE_ENCRYPTION_CONTROL_PARAMS), + /*pClassInfo=*/ &(__nvoc_class_def_Subdevice.classInfo), +#if NV_PRINTF_STRINGS_ALLOWED + /*func=*/ "subdeviceCtrlCmdInternalConfComputeEncryptionControl" +#endif + }, + { /* [85] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -1444,7 +1527,7 @@ /*func=*/ "subdeviceCtrlCmdEventSetNotification" #endif }, - { /* [81] */ + { /* [86] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -1459,7 +1542,7 @@ /*func=*/ "subdeviceCtrlCmdEventSetTrigger" #endif }, - { /* [82] */ + { /* [87] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -1474,7 +1557,7 @@ /*func=*/ "subdeviceCtrlCmdEventSetMemoryNotifies" #endif }, - { /* [83] */ + { /* [88] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -1489,7 +1572,7 @@ /*func=*/ "subdeviceCtrlCmdEventSetSemaphoreMemory" #endif }, - { /* [84] */ + { /* [89] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -1504,7 +1587,7 @@ /*func=*/ "subdeviceCtrlCmdEventSetSemaMemValidation" #endif }, - { /* [85] */ + { /* [90] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x11u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -1519,7 +1602,7 @@ /*func=*/ "subdeviceCtrlCmdEventSetTriggerFifo" #endif }, - { /* [86] */ + { /* [91] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -1534,7 +1617,7 @@ /*func=*/ "subdeviceCtrlCmdTimerSchedule" #endif }, - { /* [87] */ + { /* [92] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -1549,7 +1632,7 @@ /*func=*/ "subdeviceCtrlCmdTimerCancel" #endif }, - { /* [88] */ + { /* [93] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -1564,7 +1647,7 @@ /*func=*/ "subdeviceCtrlCmdTimerGetTime" #endif }, - { /* [89] */ + { /* [94] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x11u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -1579,7 +1662,7 @@ /*func=*/ "subdeviceCtrlCmdTimerGetRegisterOffset" #endif }, - { /* [90] */ + { /* [95] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -1594,7 +1677,7 @@ /*func=*/ "subdeviceCtrlCmdTimerGetGpuCpuTimeCorrelationInfo" #endif }, - { /* [91] */ + { /* [96] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x2010u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -1609,7 +1692,7 @@ /*func=*/ "subdeviceCtrlCmdTimerSetGrTickFreq" #endif }, - { /* [92] */ + { /* [97] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -1624,7 +1707,7 @@ /*func=*/ "subdeviceCtrlCmdI2cReadBuffer" #endif }, - { /* [93] */ + { /* [98] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -1639,7 +1722,7 @@ /*func=*/ "subdeviceCtrlCmdI2cWriteBuffer" #endif }, - { /* [94] */ + { /* [99] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -1654,7 +1737,7 @@ /*func=*/ "subdeviceCtrlCmdI2cReadReg" #endif }, - { /* [95] */ + { /* [100] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -1669,13 +1752,13 @@ /*func=*/ "subdeviceCtrlCmdI2cWriteReg" #endif }, - { /* [96] */ -#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) + { /* [101] */ +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x212u) /*pFunc=*/ (void (*)(void)) NULL, #else /*pFunc=*/ (void (*)(void)) subdeviceCtrlCmdBiosGetSKUInfo_IMPL, -#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) - /*flags=*/ 0x210u, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x212u) + /*flags=*/ 0x212u, /*accessRight=*/0x0u, /*methodId=*/ 0x20800808u, /*paramSize=*/ sizeof(NV2080_CTRL_BIOS_GET_SKU_INFO_PARAMS), @@ -1684,7 +1767,7 @@ /*func=*/ "subdeviceCtrlCmdBiosGetSKUInfo" #endif }, - { /* [97] */ + { /* [102] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -1699,7 +1782,7 @@ /*func=*/ "subdeviceCtrlCmdBiosGetPostTime" #endif }, - { /* [98] */ + { /* [103] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -1714,7 +1797,7 @@ /*func=*/ "subdeviceCtrlCmdBiosGetUefiSupport" #endif }, - { /* [99] */ + { /* [104] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -1729,7 +1812,7 @@ /*func=*/ "subdeviceCtrlCmdBiosGetNbsiV2" #endif }, - { /* [100] */ + { /* [105] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -1744,7 +1827,7 @@ /*func=*/ "subdeviceCtrlCmdBiosGetInfoV2" #endif }, - { /* [101] */ + { /* [106] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -1759,7 +1842,7 @@ /*func=*/ "subdeviceCtrlCmdDisplayGetStaticInfo" #endif }, - { /* [102] */ + { /* [107] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -1774,7 +1857,7 @@ /*func=*/ "subdeviceCtrlCmdMemSysGetStaticConfig" #endif }, - { /* [103] */ + { /* [108] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -1789,7 +1872,7 @@ /*func=*/ "subdeviceCtrlCmdInternalUvmRegisterAccessCntrBuffer" #endif }, - { /* [104] */ + { /* [109] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -1798,19 +1881,19 @@ /*flags=*/ 0x600u, /*accessRight=*/0x0u, /*methodId=*/ 0x20800a1eu, - /*paramSize=*/ 0, + /*paramSize=*/ sizeof(NV2080_CTRL_INTERNAL_UVM_UNREGISTER_ACCESS_CNTR_BUFFER_PARAMS), /*pClassInfo=*/ &(__nvoc_class_def_Subdevice.classInfo), #if NV_PRINTF_STRINGS_ALLOWED /*func=*/ "subdeviceCtrlCmdInternalUvmUnregisterAccessCntrBuffer" #endif }, - { /* [105] */ -#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x2600u) + { /* [110] */ +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x102600u) /*pFunc=*/ (void (*)(void)) NULL, #else /*pFunc=*/ (void (*)(void)) subdeviceCtrlCmdKGrInternalStaticGetCaps_IMPL, -#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x2600u) - /*flags=*/ 0x2600u, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x102600u) + /*flags=*/ 0x102600u, /*accessRight=*/0x0u, /*methodId=*/ 0x20800a1fu, /*paramSize=*/ sizeof(NV2080_CTRL_INTERNAL_STATIC_GR_GET_CAPS_PARAMS), @@ -1819,22 +1902,7 @@ /*func=*/ "subdeviceCtrlCmdKGrInternalStaticGetCaps" #endif }, - { /* [106] */ -#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) - /*pFunc=*/ (void (*)(void)) NULL, -#else - /*pFunc=*/ (void (*)(void)) subdeviceCtrlCmdInternalUvmServiceAccessCntrBuffer_IMPL, -#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) - /*flags=*/ 0x600u, - /*accessRight=*/0x0u, - /*methodId=*/ 0x20800a21u, - /*paramSize=*/ 0, - /*pClassInfo=*/ &(__nvoc_class_def_Subdevice.classInfo), -#if NV_PRINTF_STRINGS_ALLOWED - /*func=*/ "subdeviceCtrlCmdInternalUvmServiceAccessCntrBuffer" -#endif - }, - { /* [107] */ + { /* [111] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x1c2600u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -1849,7 +1917,7 @@ /*func=*/ "subdeviceCtrlCmdKGrInternalStaticGetGlobalSmOrder" #endif }, - { /* [108] */ + { /* [112] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x4600u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -1864,7 +1932,7 @@ /*func=*/ "subdeviceCtrlCmdMsencGetCaps" #endif }, - { /* [109] */ + { /* [113] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x1c2600u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -1879,7 +1947,7 @@ /*func=*/ "subdeviceCtrlCmdKGrInternalStaticGetFloorsweepingMasks" #endif }, - { /* [110] */ + { /* [114] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x80000u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -1894,22 +1962,7 @@ /*func=*/ "subdeviceCtrlCmdKGrGetCtxBufferPtes" #endif }, - { /* [111] */ -#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) - /*pFunc=*/ (void (*)(void)) NULL, -#else - /*pFunc=*/ (void (*)(void)) subdeviceCtrlCmdInternalUvmGetAccessCntrBufferSize_IMPL, -#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) - /*flags=*/ 0x600u, - /*accessRight=*/0x0u, - /*methodId=*/ 0x20800a29u, - /*paramSize=*/ sizeof(NV2080_CTRL_INTERNAL_UVM_GET_ACCESS_CNTR_BUFFER_SIZE_PARAMS), - /*pClassInfo=*/ &(__nvoc_class_def_Subdevice.classInfo), -#if NV_PRINTF_STRINGS_ALLOWED - /*func=*/ "subdeviceCtrlCmdInternalUvmGetAccessCntrBufferSize" -#endif - }, - { /* [112] */ + { /* [115] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x1c2600u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -1924,7 +1977,7 @@ /*func=*/ "subdeviceCtrlCmdKGrInternalStaticGetInfo" #endif }, - { /* [113] */ + { /* [116] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x1c2600u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -1939,7 +1992,7 @@ /*func=*/ "subdeviceCtrlCmdKGrInternalStaticGetZcullInfo" #endif }, - { /* [114] */ + { /* [117] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x1c2600u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -1954,7 +2007,7 @@ /*func=*/ "subdeviceCtrlCmdKGrInternalStaticGetRopInfo" #endif }, - { /* [115] */ + { /* [118] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x1c2600u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -1969,7 +2022,7 @@ /*func=*/ "subdeviceCtrlCmdKGrInternalStaticGetPpcMasks" #endif }, - { /* [116] */ + { /* [119] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x1c2600u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -1984,7 +2037,7 @@ /*func=*/ "subdeviceCtrlCmdKGrInternalStaticGetContextBuffersInfo" #endif }, - { /* [117] */ + { /* [120] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x1c2600u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -1999,7 +2052,7 @@ /*func=*/ "subdeviceCtrlCmdKGrInternalStaticGetSmIssueRateModifier" #endif }, - { /* [118] */ + { /* [121] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x4600u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -2014,7 +2067,7 @@ /*func=*/ "subdeviceCtrlCmdInternalGetChipInfo" #endif }, - { /* [119] */ + { /* [122] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x1c2600u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -2029,7 +2082,7 @@ /*func=*/ "subdeviceCtrlCmdKGrInternalStaticGetFecsRecordSize" #endif }, - { /* [120] */ + { /* [123] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x1c2600u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -2044,7 +2097,7 @@ /*func=*/ "subdeviceCtrlCmdKGrInternalStaticGetFecsTraceDefines" #endif }, - { /* [121] */ + { /* [124] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x4600u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -2059,7 +2112,7 @@ /*func=*/ "subdeviceCtrlCmdInternalGetDeviceInfoTable" #endif }, - { /* [122] */ + { /* [125] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x4600u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -2074,7 +2127,7 @@ /*func=*/ "subdeviceCtrlCmdInternalGetUserRegisterAccessMap" #endif }, - { /* [123] */ + { /* [126] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -2089,7 +2142,22 @@ /*func=*/ "subdeviceCtrlCmdInternalGetConstructedFalconInfo" #endif }, - { /* [124] */ + { /* [127] */ +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x2600u) + /*pFunc=*/ (void (*)(void)) NULL, +#else + /*pFunc=*/ (void (*)(void)) subdeviceCtrlCmdInternalKMIGmgrPromoteGpuInstanceMemRange_IMPL, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x2600u) + /*flags=*/ 0x2600u, + /*accessRight=*/0x0u, + /*methodId=*/ 0x20800a44u, + /*paramSize=*/ sizeof(NV2080_CTRL_INTERNAL_KMIGMGR_PROMOTE_GPU_INSTANCE_MEM_RANGE_PARAMS), + /*pClassInfo=*/ &(__nvoc_class_def_Subdevice.classInfo), +#if NV_PRINTF_STRINGS_ALLOWED + /*func=*/ "subdeviceCtrlCmdInternalKMIGmgrPromoteGpuInstanceMemRange" +#endif + }, + { /* [128] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x1c2600u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -2104,7 +2172,7 @@ /*func=*/ "subdeviceCtrlCmdKGrInternalStaticGetPdbProperties" #endif }, - { /* [125] */ + { /* [129] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -2119,7 +2187,7 @@ /*func=*/ "subdeviceCtrlCmdDisplayWriteInstMem" #endif }, - { /* [126] */ + { /* [130] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -2134,7 +2202,7 @@ /*func=*/ "subdeviceCtrlCmdInternalRecoverAllComputeContexts" #endif }, - { /* [127] */ + { /* [131] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -2149,7 +2217,7 @@ /*func=*/ "subdeviceCtrlCmdDisplayGetIpVersion" #endif }, - { /* [128] */ + { /* [132] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -2164,7 +2232,7 @@ /*func=*/ "subdeviceCtrlCmdInternalGetSmcMode" #endif }, - { /* [129] */ + { /* [133] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -2179,7 +2247,7 @@ /*func=*/ "subdeviceCtrlCmdDisplaySetupRgLineIntr" #endif }, - { /* [130] */ + { /* [134] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -2194,7 +2262,7 @@ /*func=*/ "subdeviceCtrlCmdMemSysSetPartitionableMem" #endif }, - { /* [131] */ + { /* [135] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x2600u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -2209,7 +2277,7 @@ /*func=*/ "subdeviceCtrlCmdInternalFifoPromoteRunlistBuffers" #endif }, - { /* [132] */ + { /* [136] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -2224,7 +2292,22 @@ /*func=*/ "subdeviceCtrlCmdDisplaySetImportedImpData" #endif }, - { /* [133] */ + { /* [137] */ +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) + /*pFunc=*/ (void (*)(void)) NULL, +#else + /*pFunc=*/ (void (*)(void)) subdeviceCtrlCmdInternalVmmuGetSpaForGpaEntries_IMPL, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) + /*flags=*/ 0x600u, + /*accessRight=*/0x0u, + /*methodId=*/ 0x20800a57u, + /*paramSize=*/ sizeof(NV2080_CTRL_INTERNAL_VMMU_GET_SPA_FOR_GPA_ENTRIES_PARAMS), + /*pClassInfo=*/ &(__nvoc_class_def_Subdevice.classInfo), +#if NV_PRINTF_STRINGS_ALLOWED + /*func=*/ "subdeviceCtrlCmdInternalVmmuGetSpaForGpaEntries" +#endif + }, + { /* [138] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -2239,7 +2322,7 @@ /*func=*/ "subdeviceCtrlCmdDisplaySetChannelPushbuffer" #endif }, - { /* [134] */ + { /* [139] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -2254,7 +2337,7 @@ /*func=*/ "subdeviceCtrlCmdGmmuGetStaticInfo" #endif }, - { /* [135] */ + { /* [140] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x2600u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -2269,7 +2352,7 @@ /*func=*/ "subdeviceCtrlCmdFbGetHeapReservationSize" #endif }, - { /* [136] */ + { /* [141] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -2284,7 +2367,7 @@ /*func=*/ "subdeviceCtrlCmdIntrGetKernelTable" #endif }, - { /* [137] */ + { /* [142] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -2299,13 +2382,13 @@ /*func=*/ "subdeviceCtrlCmdDisplayGetDisplayMask" #endif }, - { /* [138] */ -#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x2610u) + { /* [143] */ +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x2e50u) /*pFunc=*/ (void (*)(void)) NULL, #else /*pFunc=*/ (void (*)(void)) subdeviceCtrlCmdInternalFifoGetNumChannels_IMPL, -#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x2610u) - /*flags=*/ 0x2610u, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x2e50u) + /*flags=*/ 0x2e50u, /*accessRight=*/0x0u, /*methodId=*/ 0x20800a61u, /*paramSize=*/ sizeof(NV2080_CTRL_INTERNAL_FIFO_GET_NUM_CHANNELS_PARAMS), @@ -2314,7 +2397,7 @@ /*func=*/ "subdeviceCtrlCmdInternalFifoGetNumChannels" #endif }, - { /* [139] */ + { /* [144] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x2600u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -2329,7 +2412,7 @@ /*func=*/ "subdeviceCtrlCmdInternalStaticKMIGmgrGetProfiles" #endif }, - { /* [140] */ + { /* [145] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x2600u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -2344,7 +2427,7 @@ /*func=*/ "subdeviceCtrlCmdInternalStaticKMIGmgrGetPartitionableEngines" #endif }, - { /* [141] */ + { /* [146] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x2600u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -2359,7 +2442,7 @@ /*func=*/ "subdeviceCtrlCmdInternalStaticKMIGmgrGetSwizzIdFbMemPageRanges" #endif }, - { /* [142] */ + { /* [147] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -2374,7 +2457,7 @@ /*func=*/ "subdeviceCtrlCmdKMemSysGetMIGMemoryConfig" #endif }, - { /* [143] */ + { /* [148] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -2389,7 +2472,7 @@ /*func=*/ "subdeviceCtrlCmdFbSetZbcReferenced" #endif }, - { /* [144] */ + { /* [149] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -2404,7 +2487,7 @@ /*func=*/ "subdeviceCtrlCmdInternalRcWatchdogTimeout" #endif }, - { /* [145] */ + { /* [150] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -2419,7 +2502,7 @@ /*func=*/ "subdeviceCtrlCmdMemSysGetMIGMemoryPartitionTable" #endif }, - { /* [146] */ + { /* [151] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -2434,7 +2517,7 @@ /*func=*/ "subdeviceCtrlCmdMemSysL2InvalidateEvict" #endif }, - { /* [147] */ + { /* [152] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -2449,7 +2532,7 @@ /*func=*/ "subdeviceCtrlCmdMemSysFlushL2AllRamsAndCaches" #endif }, - { /* [148] */ + { /* [153] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -2464,7 +2547,7 @@ /*func=*/ "subdeviceCtrlCmdMemSysDisableNvlinkPeers" #endif }, - { /* [149] */ + { /* [154] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -2479,7 +2562,7 @@ /*func=*/ "subdeviceCtrlCmdMemSysProgramRawCompressionMode" #endif }, - { /* [150] */ + { /* [155] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -2494,7 +2577,7 @@ /*func=*/ "subdeviceCtrlCmdInternalBusFlushWithSysmembar" #endif }, - { /* [151] */ + { /* [156] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -2509,7 +2592,7 @@ /*func=*/ "subdeviceCtrlCmdInternalBusSetupP2pMailboxLocal" #endif }, - { /* [152] */ + { /* [157] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -2524,7 +2607,7 @@ /*func=*/ "subdeviceCtrlCmdInternalBusSetupP2pMailboxRemote" #endif }, - { /* [153] */ + { /* [158] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -2539,7 +2622,7 @@ /*func=*/ "subdeviceCtrlCmdInternalBusDestroyP2pMailbox" #endif }, - { /* [154] */ + { /* [159] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -2554,7 +2637,7 @@ /*func=*/ "subdeviceCtrlCmdInternalBusCreateC2cPeerMapping" #endif }, - { /* [155] */ + { /* [160] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -2569,7 +2652,37 @@ /*func=*/ "subdeviceCtrlCmdInternalBusRemoveC2cPeerMapping" #endif }, - { /* [156] */ + { /* [161] */ +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) + /*pFunc=*/ (void (*)(void)) NULL, +#else + /*pFunc=*/ (void (*)(void)) subdeviceCtrlCmdDisplayUnixConsole_IMPL, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) + /*flags=*/ 0x600u, + /*accessRight=*/0x0u, + /*methodId=*/ 0x20800a76u, + /*paramSize=*/ sizeof(NV2080_CTRL_CMD_INTERNAL_DISPLAY_UNIX_CONSOLE_PARAMS), + /*pClassInfo=*/ &(__nvoc_class_def_Subdevice.classInfo), +#if NV_PRINTF_STRINGS_ALLOWED + /*func=*/ "subdeviceCtrlCmdDisplayUnixConsole" +#endif + }, + { /* [162] */ +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) + /*pFunc=*/ (void (*)(void)) NULL, +#else + /*pFunc=*/ (void (*)(void)) subdeviceCtrlCmdDisplayPostVgaRestore_IMPL, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) + /*flags=*/ 0x600u, + /*accessRight=*/0x0u, + /*methodId=*/ 0x20800a77u, + /*paramSize=*/ sizeof(NV2080_CTRL_CMD_INTERNAL_DISPLAY_POST_RESTORE_PARAMS), + /*pClassInfo=*/ &(__nvoc_class_def_Subdevice.classInfo), +#if NV_PRINTF_STRINGS_ALLOWED + /*func=*/ "subdeviceCtrlCmdDisplayPostVgaRestore" +#endif + }, + { /* [163] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x610u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -2584,7 +2697,7 @@ /*func=*/ "subdeviceCtrlCmdInternalPerfCudaLimitDisable" #endif }, - { /* [157] */ + { /* [164] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -2599,7 +2712,7 @@ /*func=*/ "subdeviceCtrlCmdInternalPmgrUnsetDynamicBoostLimit" #endif }, - { /* [158] */ + { /* [165] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -2614,7 +2727,7 @@ /*func=*/ "subdeviceCtrlCmdInternalPerfOptpCliClear" #endif }, - { /* [159] */ + { /* [166] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -2629,7 +2742,7 @@ /*func=*/ "subdeviceCtrlCmdInternalPerfGpuBoostSyncSetControl" #endif }, - { /* [160] */ + { /* [167] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -2644,7 +2757,7 @@ /*func=*/ "subdeviceCtrlCmdInternalPerfSyncGpuBoostSetLimits" #endif }, - { /* [161] */ + { /* [168] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -2659,7 +2772,7 @@ /*func=*/ "subdeviceCtrlCmdInternalPerfGpuBoostSyncGetInfo" #endif }, - { /* [162] */ + { /* [169] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -2674,7 +2787,7 @@ /*func=*/ "subdeviceCtrlCmdInternalPerfGetAuxPowerState" #endif }, - { /* [163] */ + { /* [170] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -2689,7 +2802,7 @@ /*func=*/ "subdeviceCtrlCmdHshubPeerConnConfig" #endif }, - { /* [164] */ + { /* [171] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -2704,7 +2817,7 @@ /*func=*/ "subdeviceCtrlCmdHshubFirstLinkPeerId" #endif }, - { /* [165] */ + { /* [172] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -2719,7 +2832,7 @@ /*func=*/ "subdeviceCtrlCmdHshubGetHshubIdForLinks" #endif }, - { /* [166] */ + { /* [173] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -2734,7 +2847,7 @@ /*func=*/ "subdeviceCtrlCmdHshubGetNumUnits" #endif }, - { /* [167] */ + { /* [174] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -2749,7 +2862,22 @@ /*func=*/ "subdeviceCtrlCmdHshubNextHshubId" #endif }, - { /* [168] */ + { /* [175] */ +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) + /*pFunc=*/ (void (*)(void)) NULL, +#else + /*pFunc=*/ (void (*)(void)) subdeviceCtrlCmdHshubEgmConfig_IMPL, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) + /*flags=*/ 0x600u, + /*accessRight=*/0x0u, + /*methodId=*/ 0x20800a8du, + /*paramSize=*/ sizeof(NV2080_CTRL_INTERNAL_HSHUB_EGM_CONFIG_PARAMS), + /*pClassInfo=*/ &(__nvoc_class_def_Subdevice.classInfo), +#if NV_PRINTF_STRINGS_ALLOWED + /*func=*/ "subdeviceCtrlCmdHshubEgmConfig" +#endif + }, + { /* [176] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x610u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -2764,7 +2892,7 @@ /*func=*/ "subdeviceCtrlCmdInternalPerfPerfmonClientReservationCheck" #endif }, - { /* [169] */ + { /* [177] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x610u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -2779,7 +2907,7 @@ /*func=*/ "subdeviceCtrlCmdInternalPerfPerfmonClientReservationSet" #endif }, - { /* [170] */ + { /* [178] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x610u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -2794,7 +2922,7 @@ /*func=*/ "subdeviceCtrlCmdInternalPerfBoostSet_2x" #endif }, - { /* [171] */ + { /* [179] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -2809,7 +2937,7 @@ /*func=*/ "subdeviceCtrlCmdInternalGmmuRegisterFaultBuffer" #endif }, - { /* [172] */ + { /* [180] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -2824,7 +2952,7 @@ /*func=*/ "subdeviceCtrlCmdInternalGmmuUnregisterFaultBuffer" #endif }, - { /* [173] */ + { /* [181] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -2839,7 +2967,7 @@ /*func=*/ "subdeviceCtrlCmdInternalGmmuRegisterClientShadowFaultBuffer" #endif }, - { /* [174] */ + { /* [182] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -2848,13 +2976,13 @@ /*flags=*/ 0x600u, /*accessRight=*/0x0u, /*methodId=*/ 0x20800a9eu, - /*paramSize=*/ 0, + /*paramSize=*/ sizeof(NV2080_CTRL_INTERNAL_GMMU_UNREGISTER_CLIENT_SHADOW_FAULT_BUFFER_PARAMS), /*pClassInfo=*/ &(__nvoc_class_def_Subdevice.classInfo), #if NV_PRINTF_STRINGS_ALLOWED /*func=*/ "subdeviceCtrlCmdInternalGmmuUnregisterClientShadowFaultBuffer" #endif }, - { /* [175] */ + { /* [183] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -2869,7 +2997,7 @@ /*func=*/ "subdeviceCtrlCmdInternalGmmuCopyReservedSplitGVASpacePdesServer" #endif }, - { /* [176] */ + { /* [184] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x610u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -2884,7 +3012,7 @@ /*func=*/ "subdeviceCtrlCmdInternalPerfBoostSet_3x" #endif }, - { /* [177] */ + { /* [185] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x610u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -2899,7 +3027,7 @@ /*func=*/ "subdeviceCtrlCmdInternalPerfBoostClear_3x" #endif }, - { /* [178] */ + { /* [186] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x400u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -2914,7 +3042,7 @@ /*func=*/ "subdeviceCtrlCmdInternalKMIGmgrExportGPUInstance" #endif }, - { /* [179] */ + { /* [187] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x400u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -2929,7 +3057,7 @@ /*func=*/ "subdeviceCtrlCmdInternalKMIGmgrImportGPUInstance" #endif }, - { /* [180] */ + { /* [188] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -2944,7 +3072,7 @@ /*func=*/ "subdeviceCtrlCmdBifGetStaticInfo" #endif }, - { /* [181] */ + { /* [189] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -2959,7 +3087,7 @@ /*func=*/ "subdeviceCtrlCmdInternalNvlinkEnableComputePeerAddr" #endif }, - { /* [182] */ + { /* [190] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -2974,13 +3102,13 @@ /*func=*/ "subdeviceCtrlCmdInternalNvlinkGetSetNvswitchFabricAddr" #endif }, - { /* [183] */ -#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) + { /* [191] */ +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0xe40u) /*pFunc=*/ (void (*)(void)) NULL, #else /*pFunc=*/ (void (*)(void)) subdeviceCtrlCmdBifGetAspmL1Flags_IMPL, -#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) - /*flags=*/ 0x600u, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0xe40u) + /*flags=*/ 0xe40u, /*accessRight=*/0x0u, /*methodId=*/ 0x20800ab0u, /*paramSize=*/ sizeof(NV2080_CTRL_INTERNAL_BIF_GET_ASPM_L1_FLAGS_PARAMS), @@ -2989,7 +3117,7 @@ /*func=*/ "subdeviceCtrlCmdBifGetAspmL1Flags" #endif }, - { /* [184] */ + { /* [192] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -3004,7 +3132,7 @@ /*func=*/ "subdeviceCtrlCmdInternalPerfCfControllerSetMaxVGpuVMCount" #endif }, - { /* [185] */ + { /* [193] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -3019,7 +3147,7 @@ /*func=*/ "subdeviceCtrlCmdCcuMap" #endif }, - { /* [186] */ + { /* [194] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -3034,7 +3162,7 @@ /*func=*/ "subdeviceCtrlCmdCcuUnmap" #endif }, - { /* [187] */ + { /* [195] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -3049,7 +3177,7 @@ /*func=*/ "subdeviceCtrlCmdInternalSetP2pCaps" #endif }, - { /* [188] */ + { /* [196] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -3064,7 +3192,7 @@ /*func=*/ "subdeviceCtrlCmdInternalRemoveP2pCaps" #endif }, - { /* [189] */ + { /* [197] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -3079,7 +3207,7 @@ /*func=*/ "subdeviceCtrlCmdInternalGetPcieP2pCaps" #endif }, - { /* [190] */ + { /* [198] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -3094,7 +3222,7 @@ /*func=*/ "subdeviceCtrlCmdBifSetPcieRo" #endif }, - { /* [191] */ + { /* [199] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x2600u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -3109,7 +3237,7 @@ /*func=*/ "subdeviceCtrlCmdInternalStaticKMIGmgrGetComputeInstanceProfiles" #endif }, - { /* [192] */ + { /* [200] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -3124,7 +3252,7 @@ /*func=*/ "subdeviceCtrlCmdCcuSetStreamState" #endif }, - { /* [193] */ + { /* [201] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -3139,7 +3267,7 @@ /*func=*/ "subdeviceCtrlCmdInternalInitGpuIntr" #endif }, - { /* [194] */ + { /* [202] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -3154,7 +3282,7 @@ /*func=*/ "subdeviceCtrlCmdInternalGsyncOptimizeTiming" #endif }, - { /* [195] */ + { /* [203] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -3169,7 +3297,7 @@ /*func=*/ "subdeviceCtrlCmdInternalGsyncGetDisplayIds" #endif }, - { /* [196] */ + { /* [204] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -3184,7 +3312,7 @@ /*func=*/ "subdeviceCtrlCmdInternalGsyncSetStereoSync" #endif }, - { /* [197] */ + { /* [205] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -3199,7 +3327,7 @@ /*func=*/ "subdeviceCtrlCmdInternalFbsrInit" #endif }, - { /* [198] */ + { /* [206] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -3214,7 +3342,7 @@ /*func=*/ "subdeviceCtrlCmdInternalFbsrSendRegionInfo" #endif }, - { /* [199] */ + { /* [207] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -3229,7 +3357,7 @@ /*func=*/ "subdeviceCtrlCmdInternalGsyncGetVactiveLines" #endif }, - { /* [200] */ + { /* [208] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x610u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -3244,7 +3372,7 @@ /*func=*/ "subdeviceCtrlCmdInternalMemmgrGetVgpuHostRmReservedFb" #endif }, - { /* [201] */ + { /* [209] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -3259,13 +3387,13 @@ /*func=*/ "subdeviceCtrlCmdInternalPostInitBrightcStateLoad" #endif }, - { /* [202] */ -#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) + { /* [210] */ +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x100600u) /*pFunc=*/ (void (*)(void)) NULL, #else /*pFunc=*/ (void (*)(void)) subdeviceCtrlCmdInternalNvlinkGetNumActiveLinksPerIoctrl_IMPL, -#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) - /*flags=*/ 0x600u, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x100600u) + /*flags=*/ 0x100600u, /*accessRight=*/0x0u, /*methodId=*/ 0x20800ac7u, /*paramSize=*/ sizeof(NV2080_CTRL_INTERNAL_NVLINK_GET_NUM_ACTIVE_LINK_PER_IOCTRL_PARAMS), @@ -3274,13 +3402,13 @@ /*func=*/ "subdeviceCtrlCmdInternalNvlinkGetNumActiveLinksPerIoctrl" #endif }, - { /* [203] */ -#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) + { /* [211] */ +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x100600u) /*pFunc=*/ (void (*)(void)) NULL, #else /*pFunc=*/ (void (*)(void)) subdeviceCtrlCmdInternalNvlinkGetTotalNumLinksPerIoctrl_IMPL, -#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) - /*flags=*/ 0x600u, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x100600u) + /*flags=*/ 0x100600u, /*accessRight=*/0x0u, /*methodId=*/ 0x20800ac8u, /*paramSize=*/ sizeof(NV2080_CTRL_INTERNAL_NVLINK_GET_TOTAL_NUM_LINK_PER_IOCTRL_PARAMS), @@ -3289,7 +3417,7 @@ /*func=*/ "subdeviceCtrlCmdInternalNvlinkGetTotalNumLinksPerIoctrl" #endif }, - { /* [204] */ + { /* [212] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -3304,7 +3432,7 @@ /*func=*/ "subdeviceCtrlCmdInternalGsyncIsDisplayIdValid" #endif }, - { /* [205] */ + { /* [213] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -3319,7 +3447,217 @@ /*func=*/ "subdeviceCtrlCmdInternalGsyncSetOrRestoreGpioRasterSync" #endif }, - { /* [206] */ + { /* [214] */ +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) + /*pFunc=*/ (void (*)(void)) NULL, +#else + /*pFunc=*/ (void (*)(void)) subdeviceCtrlCmdInternalSmbpbiPfmReqHndlrCapUpdate_IMPL, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) + /*flags=*/ 0x600u, + /*accessRight=*/0x0u, + /*methodId=*/ 0x20800acbu, + /*paramSize=*/ sizeof(NV2080_CTRL_INTERNAL_SMBPBI_PFM_REQ_HNDLR_CAP_UPDATE_PARAMS), + /*pClassInfo=*/ &(__nvoc_class_def_Subdevice.classInfo), +#if NV_PRINTF_STRINGS_ALLOWED + /*func=*/ "subdeviceCtrlCmdInternalSmbpbiPfmReqHndlrCapUpdate" +#endif + }, + { /* [215] */ +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) + /*pFunc=*/ (void (*)(void)) NULL, +#else + /*pFunc=*/ (void (*)(void)) subdeviceCtrlCmdInternalPmgrPfmReqHndlrStateLoadSync_IMPL, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) + /*flags=*/ 0x600u, + /*accessRight=*/0x0u, + /*methodId=*/ 0x20800accu, + /*paramSize=*/ sizeof(NV2080_CTRL_INTERNAL_PFM_REQ_HNDLR_STATE_SYNC_PARAMS), + /*pClassInfo=*/ &(__nvoc_class_def_Subdevice.classInfo), +#if NV_PRINTF_STRINGS_ALLOWED + /*func=*/ "subdeviceCtrlCmdInternalPmgrPfmReqHndlrStateLoadSync" +#endif + }, + { /* [216] */ +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) + /*pFunc=*/ (void (*)(void)) NULL, +#else + /*pFunc=*/ (void (*)(void)) subdeviceCtrlCmdInternalThermPfmReqHndlrStateInitSync_IMPL, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) + /*flags=*/ 0x600u, + /*accessRight=*/0x0u, + /*methodId=*/ 0x20800acdu, + /*paramSize=*/ sizeof(NV2080_CTRL_INTERNAL_PFM_REQ_HNDLR_STATE_SYNC_PARAMS), + /*pClassInfo=*/ &(__nvoc_class_def_Subdevice.classInfo), +#if NV_PRINTF_STRINGS_ALLOWED + /*func=*/ "subdeviceCtrlCmdInternalThermPfmReqHndlrStateInitSync" +#endif + }, + { /* [217] */ +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) + /*pFunc=*/ (void (*)(void)) NULL, +#else + /*pFunc=*/ (void (*)(void)) subdeviceCtrlCmdInternalPerfPfmReqHndlrGetPm1State_IMPL, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) + /*flags=*/ 0x600u, + /*accessRight=*/0x0u, + /*methodId=*/ 0x20800aceu, + /*paramSize=*/ sizeof(NV2080_CTRL_CMD_INTERNAL_PERF_PFM_REQ_HNDLR_GET_PM1_STATE_PARAMS), + /*pClassInfo=*/ &(__nvoc_class_def_Subdevice.classInfo), +#if NV_PRINTF_STRINGS_ALLOWED + /*func=*/ "subdeviceCtrlCmdInternalPerfPfmReqHndlrGetPm1State" +#endif + }, + { /* [218] */ +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) + /*pFunc=*/ (void (*)(void)) NULL, +#else + /*pFunc=*/ (void (*)(void)) subdeviceCtrlCmdInternalPerfPfmReqHndlrSetPm1State_IMPL, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) + /*flags=*/ 0x600u, + /*accessRight=*/0x0u, + /*methodId=*/ 0x20800acfu, + /*paramSize=*/ sizeof(NV2080_CTRL_CMD_INTERNAL_PERF_PFM_REQ_HNDLR_SET_PM1_STATE_PARAMS), + /*pClassInfo=*/ &(__nvoc_class_def_Subdevice.classInfo), +#if NV_PRINTF_STRINGS_ALLOWED + /*func=*/ "subdeviceCtrlCmdInternalPerfPfmReqHndlrSetPm1State" +#endif + }, + { /* [219] */ +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) + /*pFunc=*/ (void (*)(void)) NULL, +#else + /*pFunc=*/ (void (*)(void)) subdeviceCtrlCmdInternalPmgrPfmReqHndlrUpdateEdppLimit_IMPL, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) + /*flags=*/ 0x600u, + /*accessRight=*/0x0u, + /*methodId=*/ 0x20800ad0u, + /*paramSize=*/ sizeof(NV2080_CTRL_CMD_INTERNAL_PMGR_PFM_REQ_HNDLR_UPDATE_EDPP_LIMIT_PARAMS), + /*pClassInfo=*/ &(__nvoc_class_def_Subdevice.classInfo), +#if NV_PRINTF_STRINGS_ALLOWED + /*func=*/ "subdeviceCtrlCmdInternalPmgrPfmReqHndlrUpdateEdppLimit" +#endif + }, + { /* [220] */ +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) + /*pFunc=*/ (void (*)(void)) NULL, +#else + /*pFunc=*/ (void (*)(void)) subdeviceCtrlCmdInternalThermPfmReqHndlrUpdateTgpuLimit_IMPL, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) + /*flags=*/ 0x600u, + /*accessRight=*/0x0u, + /*methodId=*/ 0x20800ad1u, + /*paramSize=*/ sizeof(NV2080_CTRL_CMD_INTERNAL_THERM_PFM_REQ_HNDLR_UPDATE_TGPU_LIMIT_PARAMS), + /*pClassInfo=*/ &(__nvoc_class_def_Subdevice.classInfo), +#if NV_PRINTF_STRINGS_ALLOWED + /*func=*/ "subdeviceCtrlCmdInternalThermPfmReqHndlrUpdateTgpuLimit" +#endif + }, + { /* [221] */ +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) + /*pFunc=*/ (void (*)(void)) NULL, +#else + /*pFunc=*/ (void (*)(void)) subdeviceCtrlCmdInternalPmgrPfmReqHndlrConfigureTgpMode_IMPL, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) + /*flags=*/ 0x600u, + /*accessRight=*/0x0u, + /*methodId=*/ 0x20800ad2u, + /*paramSize=*/ sizeof(NV2080_CTRL_CMD_INTERNAL_PMGR_PFM_REQ_HNDLR_CONFIGURE_TGP_MODE_PARAMS), + /*pClassInfo=*/ &(__nvoc_class_def_Subdevice.classInfo), +#if NV_PRINTF_STRINGS_ALLOWED + /*func=*/ "subdeviceCtrlCmdInternalPmgrPfmReqHndlrConfigureTgpMode" +#endif + }, + { /* [222] */ +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) + /*pFunc=*/ (void (*)(void)) NULL, +#else + /*pFunc=*/ (void (*)(void)) subdeviceCtrlCmdInternalPmgrPfmReqHndlrConfigureTurboV2_IMPL, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) + /*flags=*/ 0x600u, + /*accessRight=*/0x0u, + /*methodId=*/ 0x20800ad3u, + /*paramSize=*/ sizeof(NV2080_CTRL_CMD_INTERNAL_PMGR_PFM_REQ_HNDLR_CONFIGURE_TURBO_V2_PARAMS), + /*pClassInfo=*/ &(__nvoc_class_def_Subdevice.classInfo), +#if NV_PRINTF_STRINGS_ALLOWED + /*func=*/ "subdeviceCtrlCmdInternalPmgrPfmReqHndlrConfigureTurboV2" +#endif + }, + { /* [223] */ +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) + /*pFunc=*/ (void (*)(void)) NULL, +#else + /*pFunc=*/ (void (*)(void)) subdeviceCtrlCmdInternalPerfPfmReqHndlrGetVpstateInfo_IMPL, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) + /*flags=*/ 0x600u, + /*accessRight=*/0x0u, + /*methodId=*/ 0x20800ad4u, + /*paramSize=*/ sizeof(NV2080_CTRL_CMD_INTERNAL_PERF_PFM_REQ_HNDLR_GET_VPSTATE_INFO_PARAMS), + /*pClassInfo=*/ &(__nvoc_class_def_Subdevice.classInfo), +#if NV_PRINTF_STRINGS_ALLOWED + /*func=*/ "subdeviceCtrlCmdInternalPerfPfmReqHndlrGetVpstateInfo" +#endif + }, + { /* [224] */ +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) + /*pFunc=*/ (void (*)(void)) NULL, +#else + /*pFunc=*/ (void (*)(void)) subdeviceCtrlCmdInternalPerfPfmReqHndlrGetVpstateMapping_IMPL, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) + /*flags=*/ 0x600u, + /*accessRight=*/0x0u, + /*methodId=*/ 0x20800ad5u, + /*paramSize=*/ sizeof(NV2080_CTRL_CMD_INTERNAL_PERF_PFM_REQ_HNDLR_GET_VPSTATE_MAPPING_PARAMS), + /*pClassInfo=*/ &(__nvoc_class_def_Subdevice.classInfo), +#if NV_PRINTF_STRINGS_ALLOWED + /*func=*/ "subdeviceCtrlCmdInternalPerfPfmReqHndlrGetVpstateMapping" +#endif + }, + { /* [225] */ +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) + /*pFunc=*/ (void (*)(void)) NULL, +#else + /*pFunc=*/ (void (*)(void)) subdeviceCtrlCmdInternalPerfPfmReqHndlrSetVpstate_IMPL, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) + /*flags=*/ 0x600u, + /*accessRight=*/0x0u, + /*methodId=*/ 0x20800ad6u, + /*paramSize=*/ sizeof(NV2080_CTRL_CMD_INTERNAL_PERF_PFM_REQ_HNDLR_SET_VPSTATE_PARAMS), + /*pClassInfo=*/ &(__nvoc_class_def_Subdevice.classInfo), +#if NV_PRINTF_STRINGS_ALLOWED + /*func=*/ "subdeviceCtrlCmdInternalPerfPfmReqHndlrSetVpstate" +#endif + }, + { /* [226] */ +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x2610u) + /*pFunc=*/ (void (*)(void)) NULL, +#else + /*pFunc=*/ (void (*)(void)) subdeviceCtrlCmdInternalFifoGetNumSecureChannels_IMPL, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x2610u) + /*flags=*/ 0x2610u, + /*accessRight=*/0x0u, + /*methodId=*/ 0x20800ad8u, + /*paramSize=*/ sizeof(NV2080_CTRL_INTERNAL_FIFO_GET_NUM_SECURE_CHANNELS_PARAMS), + /*pClassInfo=*/ &(__nvoc_class_def_Subdevice.classInfo), +#if NV_PRINTF_STRINGS_ALLOWED + /*func=*/ "subdeviceCtrlCmdInternalFifoGetNumSecureChannels" +#endif + }, + { /* [227] */ +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) + /*pFunc=*/ (void (*)(void)) NULL, +#else + /*pFunc=*/ (void (*)(void)) subdeviceCtrlCmdSpdmPartition_IMPL, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) + /*flags=*/ 0x600u, + /*accessRight=*/0x0u, + /*methodId=*/ 0x20800ad9u, + /*paramSize=*/ sizeof(NV2080_CTRL_INTERNAL_SPDM_PARTITION_PARAMS), + /*pClassInfo=*/ &(__nvoc_class_def_Subdevice.classInfo), +#if NV_PRINTF_STRINGS_ALLOWED + /*func=*/ "subdeviceCtrlCmdSpdmPartition" +#endif + }, + { /* [228] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -3334,7 +3672,232 @@ /*func=*/ "subdeviceCtrlCmdInternalGetCoherentFbApertureSize" #endif }, - { /* [207] */ + { /* [229] */ +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) + /*pFunc=*/ (void (*)(void)) NULL, +#else + /*pFunc=*/ (void (*)(void)) subdeviceCtrlCmdBifDisableSystemMemoryAccess_IMPL, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) + /*flags=*/ 0x600u, + /*accessRight=*/0x0u, + /*methodId=*/ 0x20800adbu, + /*paramSize=*/ sizeof(NV2080_CTRL_INTERNAL_BIF_DISABLE_SYSTEM_MEMORY_ACCESS_PARAMS), + /*pClassInfo=*/ &(__nvoc_class_def_Subdevice.classInfo), +#if NV_PRINTF_STRINGS_ALLOWED + /*func=*/ "subdeviceCtrlCmdBifDisableSystemMemoryAccess" +#endif + }, + { /* [230] */ +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) + /*pFunc=*/ (void (*)(void)) NULL, +#else + /*pFunc=*/ (void (*)(void)) subdeviceCtrlCmdDisplayPinsetsToLockpins_IMPL, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) + /*flags=*/ 0x600u, + /*accessRight=*/0x0u, + /*methodId=*/ 0x20800adcu, + /*paramSize=*/ sizeof(NV2080_CTRL_INTERNAL_DISP_PINSETS_TO_LOCKPINS_PARAMS), + /*pClassInfo=*/ &(__nvoc_class_def_Subdevice.classInfo), +#if NV_PRINTF_STRINGS_ALLOWED + /*func=*/ "subdeviceCtrlCmdDisplayPinsetsToLockpins" +#endif + }, + { /* [231] */ +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) + /*pFunc=*/ (void (*)(void)) NULL, +#else + /*pFunc=*/ (void (*)(void)) subdeviceCtrlCmdInternalDetectHsVideoBridge_IMPL, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) + /*flags=*/ 0x600u, + /*accessRight=*/0x0u, + /*methodId=*/ 0x20800addu, + /*paramSize=*/ 0, + /*pClassInfo=*/ &(__nvoc_class_def_Subdevice.classInfo), +#if NV_PRINTF_STRINGS_ALLOWED + /*func=*/ "subdeviceCtrlCmdInternalDetectHsVideoBridge" +#endif + }, + { /* [232] */ +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) + /*pFunc=*/ (void (*)(void)) NULL, +#else + /*pFunc=*/ (void (*)(void)) subdeviceCtrlCmdDisplaySetSliLinkGpioSwControl_IMPL, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) + /*flags=*/ 0x600u, + /*accessRight=*/0x0u, + /*methodId=*/ 0x20800adeu, + /*paramSize=*/ sizeof(NV2080_CTRL_INTERNAL_DISP_SET_SLI_LINK_GPIO_SW_CONTROL_PARAMS), + /*pClassInfo=*/ &(__nvoc_class_def_Subdevice.classInfo), +#if NV_PRINTF_STRINGS_ALLOWED + /*func=*/ "subdeviceCtrlCmdDisplaySetSliLinkGpioSwControl" +#endif + }, + { /* [233] */ +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) + /*pFunc=*/ (void (*)(void)) NULL, +#else + /*pFunc=*/ (void (*)(void)) subdeviceCtrlCmdInternalSetStaticEdidData_IMPL, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) + /*flags=*/ 0x600u, + /*accessRight=*/0x0u, + /*methodId=*/ 0x20800adfu, + /*paramSize=*/ sizeof(NV2080_CTRL_CMD_INTERNAL_SET_STATIC_EDID_DATA_PARAMS), + /*pClassInfo=*/ &(__nvoc_class_def_Subdevice.classInfo), +#if NV_PRINTF_STRINGS_ALLOWED + /*func=*/ "subdeviceCtrlCmdInternalSetStaticEdidData" +#endif + }, + { /* [234] */ +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) + /*pFunc=*/ (void (*)(void)) NULL, +#else + /*pFunc=*/ (void (*)(void)) subdeviceCtrlCmdInternalConfComputeDeriveSwlKeys_IMPL, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) + /*flags=*/ 0x600u, + /*accessRight=*/0x0u, + /*methodId=*/ 0x20800ae1u, + /*paramSize=*/ sizeof(NV2080_CTRL_INTERNAL_CONF_COMPUTE_DERIVE_SWL_KEYS_PARAMS), + /*pClassInfo=*/ &(__nvoc_class_def_Subdevice.classInfo), +#if NV_PRINTF_STRINGS_ALLOWED + /*func=*/ "subdeviceCtrlCmdInternalConfComputeDeriveSwlKeys" +#endif + }, + { /* [235] */ +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) + /*pFunc=*/ (void (*)(void)) NULL, +#else + /*pFunc=*/ (void (*)(void)) subdeviceCtrlCmdInternalConfComputeDeriveLceKeys_IMPL, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) + /*flags=*/ 0x600u, + /*accessRight=*/0x0u, + /*methodId=*/ 0x20800ae2u, + /*paramSize=*/ sizeof(NV2080_CTRL_INTERNAL_CONF_COMPUTE_DERIVE_LCE_KEYS_PARAMS), + /*pClassInfo=*/ &(__nvoc_class_def_Subdevice.classInfo), +#if NV_PRINTF_STRINGS_ALLOWED + /*func=*/ "subdeviceCtrlCmdInternalConfComputeDeriveLceKeys" +#endif + }, + { /* [236] */ +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) + /*pFunc=*/ (void (*)(void)) NULL, +#else + /*pFunc=*/ (void (*)(void)) subdeviceCtrlCmdInternalDisplayAcpiSubsytemActivated_IMPL, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) + /*flags=*/ 0x600u, + /*accessRight=*/0x0u, + /*methodId=*/ 0x20800af0u, + /*paramSize=*/ 0, + /*pClassInfo=*/ &(__nvoc_class_def_Subdevice.classInfo), +#if NV_PRINTF_STRINGS_ALLOWED + /*func=*/ "subdeviceCtrlCmdInternalDisplayAcpiSubsytemActivated" +#endif + }, + { /* [237] */ +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) + /*pFunc=*/ (void (*)(void)) NULL, +#else + /*pFunc=*/ (void (*)(void)) subdeviceCtrlCmdInternalDisplayPreModeSet_IMPL, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) + /*flags=*/ 0x600u, + /*accessRight=*/0x0u, + /*methodId=*/ 0x20800af1u, + /*paramSize=*/ 0, + /*pClassInfo=*/ &(__nvoc_class_def_Subdevice.classInfo), +#if NV_PRINTF_STRINGS_ALLOWED + /*func=*/ "subdeviceCtrlCmdInternalDisplayPreModeSet" +#endif + }, + { /* [238] */ +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) + /*pFunc=*/ (void (*)(void)) NULL, +#else + /*pFunc=*/ (void (*)(void)) subdeviceCtrlCmdInternalDisplayPostModeSet_IMPL, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) + /*flags=*/ 0x600u, + /*accessRight=*/0x0u, + /*methodId=*/ 0x20800af2u, + /*paramSize=*/ 0, + /*pClassInfo=*/ &(__nvoc_class_def_Subdevice.classInfo), +#if NV_PRINTF_STRINGS_ALLOWED + /*func=*/ "subdeviceCtrlCmdInternalDisplayPostModeSet" +#endif + }, + { /* [239] */ +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) + /*pFunc=*/ (void (*)(void)) NULL, +#else + /*pFunc=*/ (void (*)(void)) subdeviceCtrlCmdInternalConfComputeGetStaticInfo_IMPL, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) + /*flags=*/ 0x600u, + /*accessRight=*/0x0u, + /*methodId=*/ 0x20800af3u, + /*paramSize=*/ sizeof(NV2080_CTRL_INTERNAL_CONF_COMPUTE_GET_STATIC_INFO_PARAMS), + /*pClassInfo=*/ &(__nvoc_class_def_Subdevice.classInfo), +#if NV_PRINTF_STRINGS_ALLOWED + /*func=*/ "subdeviceCtrlCmdInternalConfComputeGetStaticInfo" +#endif + }, + { /* [240] */ +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) + /*pFunc=*/ (void (*)(void)) NULL, +#else + /*pFunc=*/ (void (*)(void)) subdeviceCtrlCmdInternalMemmgrMemoryTransferWithGsp_DISPATCH, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) + /*flags=*/ 0x600u, + /*accessRight=*/0x0u, + /*methodId=*/ 0x20800afau, + /*paramSize=*/ sizeof(NV2080_CTRL_INTERNAL_MEMMGR_MEMORY_TRANSFER_WITH_GSP_PARAMS), + /*pClassInfo=*/ &(__nvoc_class_def_Subdevice.classInfo), +#if NV_PRINTF_STRINGS_ALLOWED + /*func=*/ "subdeviceCtrlCmdInternalMemmgrMemoryTransferWithGsp" +#endif + }, + { /* [241] */ +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) + /*pFunc=*/ (void (*)(void)) NULL, +#else + /*pFunc=*/ (void (*)(void)) subdeviceCtrlCmdInternalGetLocalAtsConfig_IMPL, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) + /*flags=*/ 0x600u, + /*accessRight=*/0x0u, + /*methodId=*/ 0x20800afbu, + /*paramSize=*/ sizeof(NV2080_CTRL_INTERNAL_MEMSYS_GET_LOCAL_ATS_CONFIG_PARAMS), + /*pClassInfo=*/ &(__nvoc_class_def_Subdevice.classInfo), +#if NV_PRINTF_STRINGS_ALLOWED + /*func=*/ "subdeviceCtrlCmdInternalGetLocalAtsConfig" +#endif + }, + { /* [242] */ +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) + /*pFunc=*/ (void (*)(void)) NULL, +#else + /*pFunc=*/ (void (*)(void)) subdeviceCtrlCmdInternalSetPeerAtsConfig_IMPL, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) + /*flags=*/ 0x600u, + /*accessRight=*/0x0u, + /*methodId=*/ 0x20800afcu, + /*paramSize=*/ sizeof(NV2080_CTRL_INTERNAL_MEMSYS_SET_PEER_ATS_CONFIG_PARAMS), + /*pClassInfo=*/ &(__nvoc_class_def_Subdevice.classInfo), +#if NV_PRINTF_STRINGS_ALLOWED + /*func=*/ "subdeviceCtrlCmdInternalSetPeerAtsConfig" +#endif + }, + { /* [243] */ +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) + /*pFunc=*/ (void (*)(void)) NULL, +#else + /*pFunc=*/ (void (*)(void)) subdeviceCtrlCmdInternalPmgrPfmReqHndlrGetEdppLimitInfo_IMPL, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) + /*flags=*/ 0x600u, + /*accessRight=*/0x0u, + /*methodId=*/ 0x20800afdu, + /*paramSize=*/ sizeof(NV2080_CTRL_CMD_INTERNAL_PMGR_PFM_REQ_HNDLR_GET_EDPP_LIMIT_INFO_PARAMS), + /*pClassInfo=*/ &(__nvoc_class_def_Subdevice.classInfo), +#if NV_PRINTF_STRINGS_ALLOWED + /*func=*/ "subdeviceCtrlCmdInternalPmgrPfmReqHndlrGetEdppLimitInfo" +#endif + }, + { /* [244] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x2210u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -3349,7 +3912,7 @@ /*func=*/ "subdeviceCtrlCmdSetGpfifo" #endif }, - { /* [208] */ + { /* [245] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x2210u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -3364,7 +3927,7 @@ /*func=*/ "subdeviceCtrlCmdFifoBindEngines" #endif }, - { /* [209] */ + { /* [246] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x2204u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -3379,13 +3942,13 @@ /*func=*/ "subdeviceCtrlCmdSetOperationalProperties" #endif }, - { /* [210] */ -#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) + { /* [247] */ +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x850u) /*pFunc=*/ (void (*)(void)) NULL, #else /*pFunc=*/ (void (*)(void)) subdeviceCtrlCmdGetPhysicalChannelCount_IMPL, -#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) - /*flags=*/ 0x10u, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x850u) + /*flags=*/ 0x850u, /*accessRight=*/0x0u, /*methodId=*/ 0x20801108u, /*paramSize=*/ sizeof(NV2080_CTRL_FIFO_GET_PHYSICAL_CHANNEL_COUNT_PARAMS), @@ -3394,13 +3957,13 @@ /*func=*/ "subdeviceCtrlCmdGetPhysicalChannelCount" #endif }, - { /* [211] */ -#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) + { /* [248] */ +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x200010u) /*pFunc=*/ (void (*)(void)) NULL, #else /*pFunc=*/ (void (*)(void)) subdeviceCtrlCmdFifoGetInfo_IMPL, -#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) - /*flags=*/ 0x10u, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x200010u) + /*flags=*/ 0x200010u, /*accessRight=*/0x0u, /*methodId=*/ 0x20801109u, /*paramSize=*/ sizeof(NV2080_CTRL_FIFO_GET_INFO_PARAMS), @@ -3409,13 +3972,13 @@ /*func=*/ "subdeviceCtrlCmdFifoGetInfo" #endif }, - { /* [212] */ -#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) + { /* [249] */ +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x810u) /*pFunc=*/ (void (*)(void)) NULL, #else /*pFunc=*/ (void (*)(void)) subdeviceCtrlCmdFifoDisableChannels_IMPL, -#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) - /*flags=*/ 0x10u, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x810u) + /*flags=*/ 0x810u, /*accessRight=*/0x0u, /*methodId=*/ 0x2080110bu, /*paramSize=*/ sizeof(NV2080_CTRL_FIFO_DISABLE_CHANNELS_PARAMS), @@ -3424,7 +3987,7 @@ /*func=*/ "subdeviceCtrlCmdFifoDisableChannels" #endif }, - { /* [213] */ + { /* [250] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x4u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -3439,7 +4002,7 @@ /*func=*/ "subdeviceCtrlCmdFifoGetChannelMemInfo" #endif }, - { /* [214] */ + { /* [251] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -3454,7 +4017,7 @@ /*func=*/ "subdeviceCtrlCmdFifoGetUserdLocation" #endif }, - { /* [215] */ + { /* [252] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x1c2200u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -3469,7 +4032,7 @@ /*func=*/ "subdeviceCtrlCmdFifoGetDeviceInfoTable" #endif }, - { /* [216] */ + { /* [253] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x2204u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -3484,7 +4047,7 @@ /*func=*/ "subdeviceCtrlCmdFifoClearFaultedBit" #endif }, - { /* [217] */ + { /* [254] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x2310u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -3499,7 +4062,7 @@ /*func=*/ "subdeviceCtrlCmdFifoRunlistSetSchedPolicy" #endif }, - { /* [218] */ + { /* [255] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x4u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -3514,7 +4077,7 @@ /*func=*/ "subdeviceCtrlCmdFifoUpdateChannelInfo" #endif }, - { /* [219] */ + { /* [256] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x2200u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -3529,7 +4092,7 @@ /*func=*/ "subdeviceCtrlCmdFifoDisableUsermodeChannels" #endif }, - { /* [220] */ + { /* [257] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x2210u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -3544,7 +4107,7 @@ /*func=*/ "subdeviceCtrlCmdFifoSetupVfZombieSubctxPdb" #endif }, - { /* [221] */ + { /* [258] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x4u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -3559,7 +4122,7 @@ /*func=*/ "subdeviceCtrlCmdFifoGetAllocatedChannels" #endif }, - { /* [222] */ + { /* [259] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x50u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -3574,7 +4137,7 @@ /*func=*/ "subdeviceCtrlCmdKGrGetInfo" #endif }, - { /* [223] */ + { /* [260] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x2210u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -3589,7 +4152,7 @@ /*func=*/ "subdeviceCtrlCmdKGrCtxswZcullMode" #endif }, - { /* [224] */ + { /* [261] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x11u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -3604,7 +4167,7 @@ /*func=*/ "subdeviceCtrlCmdKGrGetZcullInfo" #endif }, - { /* [225] */ + { /* [262] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x2010u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -3619,7 +4182,7 @@ /*func=*/ "subdeviceCtrlCmdKGrCtxswPmMode" #endif }, - { /* [226] */ + { /* [263] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x2210u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -3634,7 +4197,7 @@ /*func=*/ "subdeviceCtrlCmdKGrCtxswZcullBind" #endif }, - { /* [227] */ + { /* [264] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x2210u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -3649,7 +4212,7 @@ /*func=*/ "subdeviceCtrlCmdKGrCtxswPmBind" #endif }, - { /* [228] */ + { /* [265] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x2210u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -3664,7 +4227,7 @@ /*func=*/ "subdeviceCtrlCmdKGrSetGpcTileMap" #endif }, - { /* [229] */ + { /* [266] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x2210u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -3679,7 +4242,7 @@ /*func=*/ "subdeviceCtrlCmdKGrCtxswSmpcMode" #endif }, - { /* [230] */ + { /* [267] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -3694,7 +4257,7 @@ /*func=*/ "subdeviceCtrlCmdKGrGetSmToGpcTpcMappings" #endif }, - { /* [231] */ + { /* [268] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x2210u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -3709,7 +4272,7 @@ /*func=*/ "subdeviceCtrlCmdKGrSetCtxswPreemptionMode" #endif }, - { /* [232] */ + { /* [269] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x2210u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -3724,7 +4287,7 @@ /*func=*/ "subdeviceCtrlCmdKGrCtxswPreemptionBind" #endif }, - { /* [233] */ + { /* [270] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x2210u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -3739,7 +4302,7 @@ /*func=*/ "subdeviceCtrlCmdKGrPcSamplingMode" #endif }, - { /* [234] */ + { /* [271] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -3754,7 +4317,7 @@ /*func=*/ "subdeviceCtrlCmdKGrGetROPInfo" #endif }, - { /* [235] */ + { /* [272] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x2210u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -3769,7 +4332,7 @@ /*func=*/ "subdeviceCtrlCmdKGrGetCtxswStats" #endif }, - { /* [236] */ + { /* [273] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x50u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -3784,7 +4347,7 @@ /*func=*/ "subdeviceCtrlCmdKGrGetCtxBufferSize" #endif }, - { /* [237] */ + { /* [274] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x80000u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -3799,7 +4362,7 @@ /*func=*/ "subdeviceCtrlCmdKGrGetCtxBufferInfo" #endif }, - { /* [238] */ + { /* [275] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x850u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -3814,7 +4377,7 @@ /*func=*/ "subdeviceCtrlCmdKGrGetGlobalSmOrder" #endif }, - { /* [239] */ + { /* [276] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x2210u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -3823,13 +4386,13 @@ /*flags=*/ 0x2210u, /*accessRight=*/0x0u, /*methodId=*/ 0x2080121cu, - /*paramSize=*/ sizeof(NV2080_CTRL_CMD_GR_GET_CURRENT_RESIDENT_CHANNEL_PARAMS), + /*paramSize=*/ sizeof(NV2080_CTRL_GR_GET_CURRENT_RESIDENT_CHANNEL_PARAMS), /*pClassInfo=*/ &(__nvoc_class_def_Subdevice.classInfo), #if NV_PRINTF_STRINGS_ALLOWED /*func=*/ "subdeviceCtrlCmdKGrGetCurrentResidentChannel" #endif }, - { /* [240] */ + { /* [277] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x2210u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -3844,7 +4407,7 @@ /*func=*/ "subdeviceCtrlCmdKGrGetVatAlarmData" #endif }, - { /* [241] */ + { /* [278] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -3859,7 +4422,7 @@ /*func=*/ "subdeviceCtrlCmdKGrGetAttributeBufferSize" #endif }, - { /* [242] */ + { /* [279] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x2200u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -3874,7 +4437,7 @@ /*func=*/ "subdeviceCtrlCmdKGrGfxPoolQuerySize" #endif }, - { /* [243] */ + { /* [280] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x2200u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -3889,7 +4452,7 @@ /*func=*/ "subdeviceCtrlCmdKGrGfxPoolInitialize" #endif }, - { /* [244] */ + { /* [281] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x2200u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -3904,7 +4467,7 @@ /*func=*/ "subdeviceCtrlCmdKGrGfxPoolAddSlots" #endif }, - { /* [245] */ + { /* [282] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x2200u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -3919,7 +4482,7 @@ /*func=*/ "subdeviceCtrlCmdKGrGfxPoolRemoveSlots" #endif }, - { /* [246] */ + { /* [283] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x812u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -3934,7 +4497,7 @@ /*func=*/ "subdeviceCtrlCmdKGrGetCapsV2" #endif }, - { /* [247] */ + { /* [284] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x50u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -3949,7 +4512,7 @@ /*func=*/ "subdeviceCtrlCmdKGrGetInfoV2" #endif }, - { /* [248] */ + { /* [285] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x50u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -3964,7 +4527,7 @@ /*func=*/ "subdeviceCtrlCmdKGrGetGpcMask" #endif }, - { /* [249] */ + { /* [286] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -3979,7 +4542,7 @@ /*func=*/ "subdeviceCtrlCmdKGrGetTpcMask" #endif }, - { /* [250] */ + { /* [287] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x2210u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -3994,7 +4557,7 @@ /*func=*/ "subdeviceCtrlCmdKGrSetTpcPartitionMode" #endif }, - { /* [251] */ + { /* [288] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -4009,7 +4572,7 @@ /*func=*/ "subdeviceCtrlCmdKGrGetEngineContextProperties" #endif }, - { /* [252] */ + { /* [289] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -4024,7 +4587,7 @@ /*func=*/ "subdeviceCtrlCmdKGrGetSmIssueRateModifier" #endif }, - { /* [253] */ + { /* [290] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -4039,7 +4602,7 @@ /*func=*/ "subdeviceCtrlCmdKGrFecsBindEvtbufForUid" #endif }, - { /* [254] */ + { /* [291] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x44u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -4054,7 +4617,7 @@ /*func=*/ "subdeviceCtrlCmdKGrGetPhysGpcMask" #endif }, - { /* [255] */ + { /* [292] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -4069,7 +4632,7 @@ /*func=*/ "subdeviceCtrlCmdKGrGetPpcMask" #endif }, - { /* [256] */ + { /* [293] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -4084,7 +4647,7 @@ /*func=*/ "subdeviceCtrlCmdKGrGetNumTpcsForGpc" #endif }, - { /* [257] */ + { /* [294] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x2210u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -4099,7 +4662,7 @@ /*func=*/ "subdeviceCtrlCmdKGrGetCtxswModes" #endif }, - { /* [258] */ + { /* [295] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x2210u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -4114,7 +4677,7 @@ /*func=*/ "subdeviceCtrlCmdKGrGetGpcTileMap" #endif }, - { /* [259] */ + { /* [296] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x50u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -4129,7 +4692,7 @@ /*func=*/ "subdeviceCtrlCmdKGrGetZcullMask" #endif }, - { /* [260] */ + { /* [297] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x8010u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -4144,7 +4707,7 @@ /*func=*/ "subdeviceCtrlCmdKGrFecsBindEvtbufForUidV2" #endif }, - { /* [261] */ + { /* [298] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -4159,7 +4722,7 @@ /*func=*/ "subdeviceCtrlCmdKGrGetGfxGpcAndTpcInfo" #endif }, - { /* [262] */ + { /* [299] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x850u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -4174,7 +4737,7 @@ /*func=*/ "subdeviceCtrlCmdFbGetInfo" #endif }, - { /* [263] */ + { /* [300] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x850u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -4189,7 +4752,7 @@ /*func=*/ "subdeviceCtrlCmdFbGetInfoV2" #endif }, - { /* [264] */ + { /* [301] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -4204,7 +4767,7 @@ /*func=*/ "subdeviceCtrlCmdFbGetCarveoutAddressInfo" #endif }, - { /* [265] */ + { /* [302] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -4219,7 +4782,7 @@ /*func=*/ "subdeviceCtrlCmdFbGetCalibrationLockFailed" #endif }, - { /* [266] */ + { /* [303] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -4234,7 +4797,7 @@ /*func=*/ "subdeviceCtrlCmdFbFlushGpuCache" #endif }, - { /* [267] */ + { /* [304] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -4249,7 +4812,7 @@ /*func=*/ "subdeviceCtrlCmdFbSetGpuCacheAllocPolicy" #endif }, - { /* [268] */ + { /* [305] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -4264,7 +4827,7 @@ /*func=*/ "subdeviceCtrlCmdFbGetBar1Offset" #endif }, - { /* [269] */ + { /* [306] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -4279,7 +4842,7 @@ /*func=*/ "subdeviceCtrlCmdFbGetGpuCacheAllocPolicy" #endif }, - { /* [270] */ + { /* [307] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x11u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -4294,7 +4857,7 @@ /*func=*/ "subdeviceCtrlCmdFbIsKind" #endif }, - { /* [271] */ + { /* [308] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -4309,7 +4872,7 @@ /*func=*/ "subdeviceCtrlCmdFbGetGpuCacheInfo" #endif }, - { /* [272] */ + { /* [309] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -4324,7 +4887,7 @@ /*func=*/ "subdeviceCtrlCmdFbSetGpuCacheAllocPolicyV2" #endif }, - { /* [273] */ + { /* [310] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -4339,7 +4902,7 @@ /*func=*/ "subdeviceCtrlCmdFbGetGpuCacheAllocPolicyV2" #endif }, - { /* [274] */ + { /* [311] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -4354,7 +4917,7 @@ /*func=*/ "subdeviceCtrlCmdFbGetFBRegionInfo" #endif }, - { /* [275] */ + { /* [312] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -4369,7 +4932,7 @@ /*func=*/ "subdeviceCtrlCmdFbGetOfflinedPages" #endif }, - { /* [276] */ + { /* [313] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0xa50u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -4384,7 +4947,7 @@ /*func=*/ "subdeviceCtrlCmdFbGetLTCInfoForFBP" #endif }, - { /* [277] */ + { /* [314] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x204u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -4399,7 +4962,7 @@ /*func=*/ "subdeviceCtrlCmdFbCBCOp" #endif }, - { /* [278] */ + { /* [315] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x204u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -4414,7 +4977,7 @@ /*func=*/ "subdeviceCtrlCmdFbGetCtagsForCbcEviction" #endif }, - { /* [279] */ + { /* [316] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x200u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -4429,7 +4992,7 @@ /*func=*/ "subdeviceCtrlCmdFbSetupVprRegion" #endif }, - { /* [280] */ + { /* [317] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x4u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -4444,7 +5007,7 @@ /*func=*/ "subdeviceCtrlCmdFbGetCliManagedOfflinedPages" #endif }, - { /* [281] */ + { /* [318] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x204u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -4459,7 +5022,7 @@ /*func=*/ "subdeviceCtrlCmdFbGetCompBitCopyConstructInfo" #endif }, - { /* [282] */ + { /* [319] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x204u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -4474,7 +5037,7 @@ /*func=*/ "subdeviceCtrlCmdFbSetRrd" #endif }, - { /* [283] */ + { /* [320] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x204u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -4489,7 +5052,7 @@ /*func=*/ "subdeviceCtrlCmdFbSetReadLimit" #endif }, - { /* [284] */ + { /* [321] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x204u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -4504,7 +5067,7 @@ /*func=*/ "subdeviceCtrlCmdFbSetWriteLimit" #endif }, - { /* [285] */ + { /* [322] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x204u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -4519,7 +5082,7 @@ /*func=*/ "subdeviceCtrlCmdFbPatchPbrForMining" #endif }, - { /* [286] */ + { /* [323] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x50u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -4534,7 +5097,7 @@ /*func=*/ "subdeviceCtrlCmdFbGetMemAlignment" #endif }, - { /* [287] */ + { /* [324] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -4549,7 +5112,7 @@ /*func=*/ "subdeviceCtrlCmdFbGetRemappedRows" #endif }, - { /* [288] */ + { /* [325] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -4564,7 +5127,7 @@ /*func=*/ "subdeviceCtrlCmdFbGetFsInfo" #endif }, - { /* [289] */ + { /* [326] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -4579,7 +5142,7 @@ /*func=*/ "subdeviceCtrlCmdFbGetRowRemapperHistogram" #endif }, - { /* [290] */ + { /* [327] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x2210u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -4594,7 +5157,7 @@ /*func=*/ "subdeviceCtrlCmdFbGetDynamicOfflinedPages" #endif }, - { /* [291] */ + { /* [328] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x0u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -4609,7 +5172,7 @@ /*func=*/ "subdeviceCtrlCmdFbUpdateNumaStatus" #endif }, - { /* [292] */ + { /* [329] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x0u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -4624,13 +5187,28 @@ /*func=*/ "subdeviceCtrlCmdFbGetNumaInfo" #endif }, - { /* [293] */ -#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x812u) + { /* [330] */ +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) + /*pFunc=*/ (void (*)(void)) NULL, +#else + /*pFunc=*/ (void (*)(void)) subdeviceCtrlCmdGbGetSemaphoreSurfaceLayout_IMPL, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) + /*flags=*/ 0x10u, + /*accessRight=*/0x0u, + /*methodId=*/ 0x20801352u, + /*paramSize=*/ sizeof(NV2080_CTRL_FB_GET_SEMAPHORE_SURFACE_LAYOUT_PARAMS), + /*pClassInfo=*/ &(__nvoc_class_def_Subdevice.classInfo), +#if NV_PRINTF_STRINGS_ALLOWED + /*func=*/ "subdeviceCtrlCmdGbGetSemaphoreSurfaceLayout" +#endif + }, + { /* [331] */ +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x4813u) /*pFunc=*/ (void (*)(void)) NULL, #else /*pFunc=*/ (void (*)(void)) subdeviceCtrlCmdMcGetArchInfo_IMPL, -#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x812u) - /*flags=*/ 0x812u, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x4813u) + /*flags=*/ 0x4813u, /*accessRight=*/0x0u, /*methodId=*/ 0x20801701u, /*paramSize=*/ sizeof(NV2080_CTRL_MC_GET_ARCH_INFO_PARAMS), @@ -4639,13 +5217,13 @@ /*func=*/ "subdeviceCtrlCmdMcGetArchInfo" #endif }, - { /* [294] */ -#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) + { /* [332] */ +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x850u) /*pFunc=*/ (void (*)(void)) NULL, #else /*pFunc=*/ (void (*)(void)) subdeviceCtrlCmdMcServiceInterrupts_IMPL, -#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) - /*flags=*/ 0x10u, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x850u) + /*flags=*/ 0x850u, /*accessRight=*/0x0u, /*methodId=*/ 0x20801702u, /*paramSize=*/ sizeof(NV2080_CTRL_MC_SERVICE_INTERRUPTS_PARAMS), @@ -4654,7 +5232,7 @@ /*func=*/ "subdeviceCtrlCmdMcServiceInterrupts" #endif }, - { /* [295] */ + { /* [333] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -4669,7 +5247,7 @@ /*func=*/ "subdeviceCtrlCmdMcGetManufacturer" #endif }, - { /* [296] */ + { /* [334] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -4684,7 +5262,7 @@ /*func=*/ "subdeviceCtrlCmdMcQueryHostclkSlowdownStatus" #endif }, - { /* [297] */ + { /* [335] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -4699,7 +5277,7 @@ /*func=*/ "subdeviceCtrlCmdMcSetHostclkSlowdownStatus" #endif }, - { /* [298] */ + { /* [336] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x4u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -4714,13 +5292,13 @@ /*func=*/ "subdeviceCtrlCmdMcChangeReplayableFaultOwnership" #endif }, - { /* [299] */ -#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x850u) + { /* [337] */ +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x4850u) /*pFunc=*/ (void (*)(void)) NULL, #else /*pFunc=*/ (void (*)(void)) subdeviceCtrlCmdBusGetPciInfo_IMPL, -#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x850u) - /*flags=*/ 0x850u, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x4850u) + /*flags=*/ 0x4850u, /*accessRight=*/0x0u, /*methodId=*/ 0x20801801u, /*paramSize=*/ sizeof(NV2080_CTRL_BUS_GET_PCI_INFO_PARAMS), @@ -4729,7 +5307,7 @@ /*func=*/ "subdeviceCtrlCmdBusGetPciInfo" #endif }, - { /* [300] */ + { /* [338] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x850u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -4744,13 +5322,13 @@ /*func=*/ "subdeviceCtrlCmdBusGetInfo" #endif }, - { /* [301] */ -#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x850u) + { /* [339] */ +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x4850u) /*pFunc=*/ (void (*)(void)) NULL, #else /*pFunc=*/ (void (*)(void)) subdeviceCtrlCmdBusGetPciBarInfo_IMPL, -#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x850u) - /*flags=*/ 0x850u, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x4850u) + /*flags=*/ 0x4850u, /*accessRight=*/0x0u, /*methodId=*/ 0x20801803u, /*paramSize=*/ sizeof(NV2080_CTRL_BUS_GET_PCI_BAR_INFO_PARAMS), @@ -4759,7 +5337,7 @@ /*func=*/ "subdeviceCtrlCmdBusGetPciBarInfo" #endif }, - { /* [302] */ + { /* [340] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x204u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -4774,7 +5352,7 @@ /*func=*/ "subdeviceCtrlCmdBusSetPcieLinkWidth" #endif }, - { /* [303] */ + { /* [341] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x204u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -4789,7 +5367,7 @@ /*func=*/ "subdeviceCtrlCmdBusSetPcieSpeed" #endif }, - { /* [304] */ + { /* [342] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -4804,7 +5382,7 @@ /*func=*/ "subdeviceCtrlCmdBusSetHwbcUpstreamPcieSpeed" #endif }, - { /* [305] */ + { /* [343] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -4819,7 +5397,7 @@ /*func=*/ "subdeviceCtrlCmdBusGetHwbcUpstreamPcieSpeed" #endif }, - { /* [306] */ + { /* [344] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -4834,7 +5412,7 @@ /*func=*/ "subdeviceCtrlCmdBusHWBCGetUpstreamBAR0" #endif }, - { /* [307] */ + { /* [345] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -4849,7 +5427,7 @@ /*func=*/ "subdeviceCtrlCmdBusServiceGpuMultifunctionState" #endif }, - { /* [308] */ + { /* [346] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -4864,7 +5442,7 @@ /*func=*/ "subdeviceCtrlCmdBusGetPexCounters" #endif }, - { /* [309] */ + { /* [347] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -4879,7 +5457,7 @@ /*func=*/ "subdeviceCtrlCmdBusClearPexCounters" #endif }, - { /* [310] */ + { /* [348] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -4894,7 +5472,7 @@ /*func=*/ "subdeviceCtrlCmdBusFreezePexCounters" #endif }, - { /* [311] */ + { /* [349] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -4909,7 +5487,7 @@ /*func=*/ "subdeviceCtrlCmdBusGetPexLaneCounters" #endif }, - { /* [312] */ + { /* [350] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -4924,7 +5502,7 @@ /*func=*/ "subdeviceCtrlCmdBusGetPcieLtrLatency" #endif }, - { /* [313] */ + { /* [351] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -4939,7 +5517,7 @@ /*func=*/ "subdeviceCtrlCmdBusSetPcieLtrLatency" #endif }, - { /* [314] */ + { /* [352] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -4954,7 +5532,7 @@ /*func=*/ "subdeviceCtrlCmdBusGetPexUtilCounters" #endif }, - { /* [315] */ + { /* [353] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -4969,7 +5547,7 @@ /*func=*/ "subdeviceCtrlCmdBusClearPexUtilCounters" #endif }, - { /* [316] */ + { /* [354] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -4984,13 +5562,13 @@ /*func=*/ "subdeviceCtrlCmdBusGetBFD" #endif }, - { /* [317] */ -#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) + { /* [355] */ +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x850u) /*pFunc=*/ (void (*)(void)) NULL, #else /*pFunc=*/ (void (*)(void)) subdeviceCtrlCmdBusGetAspmDisableFlags_IMPL, -#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) - /*flags=*/ 0x10u, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x850u) + /*flags=*/ 0x850u, /*accessRight=*/0x0u, /*methodId=*/ 0x20801822u, /*paramSize=*/ sizeof(NV2080_CTRL_BUS_GET_ASPM_DISABLE_FLAGS_PARAMS), @@ -4999,13 +5577,13 @@ /*func=*/ "subdeviceCtrlCmdBusGetAspmDisableFlags" #endif }, - { /* [318] */ -#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x850u) + { /* [356] */ +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x200850u) /*pFunc=*/ (void (*)(void)) NULL, #else /*pFunc=*/ (void (*)(void)) subdeviceCtrlCmdBusGetInfoV2_IMPL, -#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x850u) - /*flags=*/ 0x850u, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x200850u) + /*flags=*/ 0x200850u, /*accessRight=*/0x0u, /*methodId=*/ 0x20801823u, /*paramSize=*/ sizeof(NV2080_CTRL_BUS_GET_INFO_V2_PARAMS), @@ -5014,7 +5592,7 @@ /*func=*/ "subdeviceCtrlCmdBusGetInfoV2" #endif }, - { /* [319] */ + { /* [357] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -5029,13 +5607,13 @@ /*func=*/ "subdeviceCtrlCmdBusControlPublicAspmBits" #endif }, - { /* [320] */ -#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) + { /* [358] */ +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x810u) /*pFunc=*/ (void (*)(void)) NULL, #else /*pFunc=*/ (void (*)(void)) subdeviceCtrlCmdBusGetNvlinkPeerIdMask_IMPL, -#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) - /*flags=*/ 0x10u, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x810u) + /*flags=*/ 0x810u, /*accessRight=*/0x0u, /*methodId=*/ 0x20801825u, /*paramSize=*/ sizeof(NV2080_CTRL_BUS_GET_NVLINK_PEER_ID_MASK_PARAMS), @@ -5044,7 +5622,7 @@ /*func=*/ "subdeviceCtrlCmdBusGetNvlinkPeerIdMask" #endif }, - { /* [321] */ + { /* [359] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -5059,7 +5637,7 @@ /*func=*/ "subdeviceCtrlCmdBusSetEomParameters" #endif }, - { /* [322] */ + { /* [360] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -5074,7 +5652,7 @@ /*func=*/ "subdeviceCtrlCmdBusGetUphyDlnCfgSpace" #endif }, - { /* [323] */ + { /* [361] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -5089,13 +5667,13 @@ /*func=*/ "subdeviceCtrlCmdBusGetEomStatus" #endif }, - { /* [324] */ -#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x6210u) + { /* [362] */ +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x4210u) /*pFunc=*/ (void (*)(void)) NULL, #else - /*pFunc=*/ (void (*)(void)) subdeviceCtrlCmdBusGetPcieReqAtomicsCaps_IMPL, -#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x6210u) - /*flags=*/ 0x6210u, + /*pFunc=*/ (void (*)(void)) subdeviceCtrlCmdBusGetPcieReqAtomicsCaps_DISPATCH, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x4210u) + /*flags=*/ 0x4210u, /*accessRight=*/0x0u, /*methodId=*/ 0x20801829u, /*paramSize=*/ sizeof(NV2080_CTRL_CMD_BUS_GET_PCIE_REQ_ATOMICS_CAPS_PARAMS), @@ -5104,7 +5682,7 @@ /*func=*/ "subdeviceCtrlCmdBusGetPcieReqAtomicsCaps" #endif }, - { /* [325] */ + { /* [363] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x6210u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -5119,7 +5697,7 @@ /*func=*/ "subdeviceCtrlCmdBusGetPcieSupportedGpuAtomics" #endif }, - { /* [326] */ + { /* [364] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -5134,13 +5712,13 @@ /*func=*/ "subdeviceCtrlCmdBusGetC2CInfo" #endif }, - { /* [327] */ -#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10200u) + { /* [365] */ +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10000u) /*pFunc=*/ (void (*)(void)) NULL, #else /*pFunc=*/ (void (*)(void)) subdeviceCtrlCmdBusSysmemAccess_IMPL, -#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10200u) - /*flags=*/ 0x10200u, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10000u) + /*flags=*/ 0x10000u, /*accessRight=*/0x0u, /*methodId=*/ 0x2080182cu, /*paramSize=*/ sizeof(NV2080_CTRL_BUS_SYSMEM_ACCESS_PARAMS), @@ -5149,7 +5727,7 @@ /*func=*/ "subdeviceCtrlCmdBusSysmemAccess" #endif }, - { /* [328] */ + { /* [366] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -5164,7 +5742,7 @@ /*func=*/ "subdeviceCtrlCmdBusGetC2CErrorInfo" #endif }, - { /* [329] */ + { /* [367] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x100200u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -5179,7 +5757,7 @@ /*func=*/ "subdeviceCtrlCmdBusSetP2pMapping" #endif }, - { /* [330] */ + { /* [368] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x100200u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -5194,13 +5772,13 @@ /*func=*/ "subdeviceCtrlCmdBusUnsetP2pMapping" #endif }, - { /* [331] */ -#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x810u) + { /* [369] */ +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x850u) /*pFunc=*/ (void (*)(void)) NULL, #else /*pFunc=*/ (void (*)(void)) subdeviceCtrlCmdKPerfBoost_IMPL, -#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x810u) - /*flags=*/ 0x810u, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x850u) + /*flags=*/ 0x850u, /*accessRight=*/0x0u, /*methodId=*/ 0x2080200au, /*paramSize=*/ sizeof(NV2080_CTRL_PERF_BOOST_PARAMS), @@ -5209,7 +5787,7 @@ /*func=*/ "subdeviceCtrlCmdKPerfBoost" #endif }, - { /* [332] */ + { /* [370] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -5224,7 +5802,7 @@ /*func=*/ "subdeviceCtrlCmdPerfSetPowerstate" #endif }, - { /* [333] */ + { /* [371] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x212u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -5239,7 +5817,7 @@ /*func=*/ "subdeviceCtrlCmdPerfRatedTdpGetControl" #endif }, - { /* [334] */ + { /* [372] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -5254,7 +5832,7 @@ /*func=*/ "subdeviceCtrlCmdPerfRatedTdpSetControl" #endif }, - { /* [335] */ + { /* [373] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -5269,13 +5847,13 @@ /*func=*/ "subdeviceCtrlCmdPerfSetAuxPowerState" #endif }, - { /* [336] */ -#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) + { /* [374] */ +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x50u) /*pFunc=*/ (void (*)(void)) NULL, #else /*pFunc=*/ (void (*)(void)) subdeviceCtrlCmdPerfReservePerfmonHw_DISPATCH, -#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) - /*flags=*/ 0x10u, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x50u) + /*flags=*/ 0x50u, /*accessRight=*/0x0u, /*methodId=*/ 0x20802093u, /*paramSize=*/ sizeof(NV2080_CTRL_PERF_RESERVE_PERFMON_HW_PARAMS), @@ -5284,7 +5862,7 @@ /*func=*/ "subdeviceCtrlCmdPerfReservePerfmonHw" #endif }, - { /* [337] */ + { /* [375] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -5299,7 +5877,7 @@ /*func=*/ "subdeviceCtrlCmdPerfGetGpumonPerfmonUtilSamplesV2" #endif }, - { /* [338] */ + { /* [376] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x0u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -5314,7 +5892,7 @@ /*func=*/ "subdeviceCtrlCmdRcReadVirtualMem" #endif }, - { /* [339] */ + { /* [377] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -5329,7 +5907,7 @@ /*func=*/ "subdeviceCtrlCmdRcGetErrorCount" #endif }, - { /* [340] */ + { /* [378] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x204u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -5344,13 +5922,13 @@ /*func=*/ "subdeviceCtrlCmdRcSetCleanErrorHistory" #endif }, - { /* [341] */ -#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) + { /* [379] */ +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x850u) /*pFunc=*/ (void (*)(void)) NULL, #else /*pFunc=*/ (void (*)(void)) subdeviceCtrlCmdRcGetWatchdogInfo_IMPL, -#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) - /*flags=*/ 0x10u, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x850u) + /*flags=*/ 0x850u, /*accessRight=*/0x0u, /*methodId=*/ 0x20802209u, /*paramSize=*/ sizeof(NV2080_CTRL_RC_GET_WATCHDOG_INFO_PARAMS), @@ -5359,13 +5937,13 @@ /*func=*/ "subdeviceCtrlCmdRcGetWatchdogInfo" #endif }, - { /* [342] */ -#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) + { /* [380] */ +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x50u) /*pFunc=*/ (void (*)(void)) NULL, #else /*pFunc=*/ (void (*)(void)) subdeviceCtrlCmdRcDisableWatchdog_IMPL, -#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) - /*flags=*/ 0x10u, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x50u) + /*flags=*/ 0x50u, /*accessRight=*/0x0u, /*methodId=*/ 0x2080220au, /*paramSize=*/ 0, @@ -5374,13 +5952,13 @@ /*func=*/ "subdeviceCtrlCmdRcDisableWatchdog" #endif }, - { /* [343] */ -#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) + { /* [381] */ +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x50u) /*pFunc=*/ (void (*)(void)) NULL, #else /*pFunc=*/ (void (*)(void)) subdeviceCtrlCmdRcEnableWatchdog_IMPL, -#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) - /*flags=*/ 0x10u, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x50u) + /*flags=*/ 0x50u, /*accessRight=*/0x0u, /*methodId=*/ 0x2080220bu, /*paramSize=*/ 0, @@ -5389,13 +5967,13 @@ /*func=*/ "subdeviceCtrlCmdRcEnableWatchdog" #endif }, - { /* [344] */ -#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) + { /* [382] */ +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x50u) /*pFunc=*/ (void (*)(void)) NULL, #else /*pFunc=*/ (void (*)(void)) subdeviceCtrlCmdRcReleaseWatchdogRequests_IMPL, -#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) - /*flags=*/ 0x10u, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x50u) + /*flags=*/ 0x50u, /*accessRight=*/0x0u, /*methodId=*/ 0x2080220cu, /*paramSize=*/ 0, @@ -5404,7 +5982,7 @@ /*func=*/ "subdeviceCtrlCmdRcReleaseWatchdogRequests" #endif }, - { /* [345] */ + { /* [383] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x204u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -5419,7 +5997,7 @@ /*func=*/ "subdeviceCtrlCmdSetRcRecovery" #endif }, - { /* [346] */ + { /* [384] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x204u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -5434,13 +6012,13 @@ /*func=*/ "subdeviceCtrlCmdGetRcRecovery" #endif }, - { /* [347] */ -#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) + { /* [385] */ +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x50u) /*pFunc=*/ (void (*)(void)) NULL, #else /*pFunc=*/ (void (*)(void)) subdeviceCtrlCmdRcSoftDisableWatchdog_IMPL, -#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) - /*flags=*/ 0x10u, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x50u) + /*flags=*/ 0x50u, /*accessRight=*/0x0u, /*methodId=*/ 0x20802210u, /*paramSize=*/ 0, @@ -5449,7 +6027,7 @@ /*func=*/ "subdeviceCtrlCmdRcSoftDisableWatchdog" #endif }, - { /* [348] */ + { /* [386] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x204u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -5464,7 +6042,7 @@ /*func=*/ "subdeviceCtrlCmdSetRcInfo" #endif }, - { /* [349] */ + { /* [387] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x204u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -5479,7 +6057,7 @@ /*func=*/ "subdeviceCtrlCmdGetRcInfo" #endif }, - { /* [350] */ + { /* [388] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -5494,7 +6072,67 @@ /*func=*/ "subdeviceCtrlCmdRcGetErrorV2" #endif }, - { /* [351] */ + { /* [389] */ +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) + /*pFunc=*/ (void (*)(void)) NULL, +#else + /*pFunc=*/ (void (*)(void)) subdeviceCtrlCmdInternalGpioProgramDirection_IMPL, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) + /*flags=*/ 0x600u, + /*accessRight=*/0x0u, + /*methodId=*/ 0x20802300u, + /*paramSize=*/ sizeof(NV2080_CTRL_INTERNAL_GPIO_PROGRAM_DIRECTION_PARAMS), + /*pClassInfo=*/ &(__nvoc_class_def_Subdevice.classInfo), +#if NV_PRINTF_STRINGS_ALLOWED + /*func=*/ "subdeviceCtrlCmdInternalGpioProgramDirection" +#endif + }, + { /* [390] */ +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) + /*pFunc=*/ (void (*)(void)) NULL, +#else + /*pFunc=*/ (void (*)(void)) subdeviceCtrlCmdInternalGpioProgramOutput_IMPL, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) + /*flags=*/ 0x600u, + /*accessRight=*/0x0u, + /*methodId=*/ 0x20802301u, + /*paramSize=*/ sizeof(NV2080_CTRL_INTERNAL_GPIO_PROGRAM_OUTPUT_PARAMS), + /*pClassInfo=*/ &(__nvoc_class_def_Subdevice.classInfo), +#if NV_PRINTF_STRINGS_ALLOWED + /*func=*/ "subdeviceCtrlCmdInternalGpioProgramOutput" +#endif + }, + { /* [391] */ +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) + /*pFunc=*/ (void (*)(void)) NULL, +#else + /*pFunc=*/ (void (*)(void)) subdeviceCtrlCmdInternalGpioReadInput_IMPL, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) + /*flags=*/ 0x600u, + /*accessRight=*/0x0u, + /*methodId=*/ 0x20802302u, + /*paramSize=*/ sizeof(NV2080_CTRL_INTERNAL_GPIO_READ_INPUT_PARAMS), + /*pClassInfo=*/ &(__nvoc_class_def_Subdevice.classInfo), +#if NV_PRINTF_STRINGS_ALLOWED + /*func=*/ "subdeviceCtrlCmdInternalGpioReadInput" +#endif + }, + { /* [392] */ +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) + /*pFunc=*/ (void (*)(void)) NULL, +#else + /*pFunc=*/ (void (*)(void)) subdeviceCtrlCmdInternalGpioActivateHwFunction_IMPL, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) + /*flags=*/ 0x600u, + /*accessRight=*/0x0u, + /*methodId=*/ 0x20802303u, + /*paramSize=*/ sizeof(NV2080_CTRL_INTERNAL_GPIO_ACTIVATE_HW_FUNCTION_PARAMS), + /*pClassInfo=*/ &(__nvoc_class_def_Subdevice.classInfo), +#if NV_PRINTF_STRINGS_ALLOWED + /*func=*/ "subdeviceCtrlCmdInternalGpioActivateHwFunction" +#endif + }, + { /* [393] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -5509,7 +6147,7 @@ /*func=*/ "subdeviceCtrlCmdNvdGetDumpSize" #endif }, - { /* [352] */ + { /* [394] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x4u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -5524,7 +6162,7 @@ /*func=*/ "subdeviceCtrlCmdNvdGetDump" #endif }, - { /* [353] */ + { /* [395] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x7u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -5539,7 +6177,7 @@ /*func=*/ "subdeviceCtrlCmdNvdGetNocatJournalRpt" #endif }, - { /* [354] */ + { /* [396] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x7u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -5554,7 +6192,7 @@ /*func=*/ "subdeviceCtrlCmdNvdSetNocatJournalData" #endif }, - { /* [355] */ + { /* [397] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -5569,7 +6207,7 @@ /*func=*/ "subdeviceCtrlCmdDmaInvalidateTLB" #endif }, - { /* [356] */ + { /* [398] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -5584,7 +6222,7 @@ /*func=*/ "subdeviceCtrlCmdDmaGetInfo" #endif }, - { /* [357] */ + { /* [399] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0xa50u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -5599,7 +6237,7 @@ /*func=*/ "subdeviceCtrlCmdPmgrGetModuleInfo" #endif }, - { /* [358] */ + { /* [400] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x204u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -5614,7 +6252,7 @@ /*func=*/ "subdeviceCtrlCmdLpwrDifrCtrl" #endif }, - { /* [359] */ + { /* [401] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x200u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -5629,7 +6267,7 @@ /*func=*/ "subdeviceCtrlCmdLpwrDifrPrefetchResponse" #endif }, - { /* [360] */ + { /* [402] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x850u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -5644,13 +6282,13 @@ /*func=*/ "subdeviceCtrlCmdCeGetCaps" #endif }, - { /* [361] */ -#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x211u) + { /* [403] */ +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x2211u) /*pFunc=*/ (void (*)(void)) NULL, #else /*pFunc=*/ (void (*)(void)) subdeviceCtrlCmdCeGetCePceMask_IMPL, -#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x211u) - /*flags=*/ 0x211u, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x2211u) + /*flags=*/ 0x2211u, /*accessRight=*/0x0u, /*methodId=*/ 0x20802a02u, /*paramSize=*/ sizeof(NV2080_CTRL_CE_GET_CE_PCE_MASK_PARAMS), @@ -5659,13 +6297,13 @@ /*func=*/ "subdeviceCtrlCmdCeGetCePceMask" #endif }, - { /* [362] */ -#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x850u) + { /* [404] */ +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x2850u) /*pFunc=*/ (void (*)(void)) NULL, #else /*pFunc=*/ (void (*)(void)) subdeviceCtrlCmdCeGetCapsV2_IMPL, -#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x850u) - /*flags=*/ 0x850u, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x2850u) + /*flags=*/ 0x2850u, /*accessRight=*/0x0u, /*methodId=*/ 0x20802a03u, /*paramSize=*/ sizeof(NV2080_CTRL_CE_GET_CAPS_V2_PARAMS), @@ -5674,7 +6312,7 @@ /*func=*/ "subdeviceCtrlCmdCeGetCapsV2" #endif }, - { /* [363] */ + { /* [405] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x204u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -5689,7 +6327,7 @@ /*func=*/ "subdeviceCtrlCmdCeUpdatePceLceMappings" #endif }, - { /* [364] */ + { /* [406] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -5704,7 +6342,7 @@ /*func=*/ "subdeviceCtrlCmdCeUpdateClassDB" #endif }, - { /* [365] */ + { /* [407] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x100e40u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -5719,7 +6357,7 @@ /*func=*/ "subdeviceCtrlCmdCeGetPhysicalCaps" #endif }, - { /* [366] */ + { /* [408] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x1c0200u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -5734,7 +6372,7 @@ /*func=*/ "subdeviceCtrlCmdCeGetFaultMethodBufferSize" #endif }, - { /* [367] */ + { /* [409] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x4600u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -5749,13 +6387,13 @@ /*func=*/ "subdeviceCtrlCmdCeGetHubPceMask" #endif }, - { /* [368] */ -#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x2850u) + { /* [410] */ +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x2810u) /*pFunc=*/ (void (*)(void)) NULL, #else /*pFunc=*/ (void (*)(void)) subdeviceCtrlCmdCeGetAllCaps_IMPL, -#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x2850u) - /*flags=*/ 0x2850u, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x2810u) + /*flags=*/ 0x2810u, /*accessRight=*/0x0u, /*methodId=*/ 0x20802a0au, /*paramSize=*/ sizeof(NV2080_CTRL_CE_GET_ALL_CAPS_PARAMS), @@ -5764,7 +6402,7 @@ /*func=*/ "subdeviceCtrlCmdCeGetAllCaps" #endif }, - { /* [369] */ + { /* [411] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0xe40u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -5779,7 +6417,7 @@ /*func=*/ "subdeviceCtrlCmdCeGetAllPhysicalCaps" #endif }, - { /* [370] */ + { /* [412] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x850u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -5794,7 +6432,7 @@ /*func=*/ "subdeviceCtrlCmdBusGetNvlinkCaps" #endif }, - { /* [371] */ + { /* [413] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x810u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -5809,7 +6447,7 @@ /*func=*/ "subdeviceCtrlCmdBusGetNvlinkStatus" #endif }, - { /* [372] */ + { /* [414] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -5824,7 +6462,7 @@ /*func=*/ "subdeviceCtrlCmdBusGetNvlinkErrInfo" #endif }, - { /* [373] */ + { /* [415] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -5839,7 +6477,7 @@ /*func=*/ "subdeviceCtrlCmdGetNvlinkCounters" #endif }, - { /* [374] */ + { /* [416] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x204u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -5854,7 +6492,7 @@ /*func=*/ "subdeviceCtrlCmdClearNvlinkCounters" #endif }, - { /* [375] */ + { /* [417] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -5869,7 +6507,7 @@ /*func=*/ "subdeviceCtrlCmdNvlinkGetLinkFatalErrorCounts" #endif }, - { /* [376] */ + { /* [418] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x200u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -5884,7 +6522,7 @@ /*func=*/ "subdeviceCtrlCmdNvlinkSetupEom" #endif }, - { /* [377] */ + { /* [419] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -5899,7 +6537,7 @@ /*func=*/ "subdeviceCtrlCmdNvlinkGetPowerState" #endif }, - { /* [378] */ + { /* [420] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x204u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -5914,7 +6552,7 @@ /*func=*/ "subdeviceCtrlCmdNvlinGetLinkFomValues" #endif }, - { /* [379] */ + { /* [421] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x204u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -5929,7 +6567,7 @@ /*func=*/ "subdeviceCtrlCmdNvlinkGetNvlinkEccErrors" #endif }, - { /* [380] */ + { /* [422] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -5944,7 +6582,7 @@ /*func=*/ "subdeviceCtrlCmdNvlinkReadTpCounters" #endif }, - { /* [381] */ + { /* [423] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x201u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -5959,7 +6597,7 @@ /*func=*/ "subdeviceCtrlCmdNvlinkEnableNvlinkPeer" #endif }, - { /* [382] */ + { /* [424] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -5974,7 +6612,7 @@ /*func=*/ "subdeviceCtrlCmdNvlinkGetLpCounters" #endif }, - { /* [383] */ + { /* [425] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x201u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -5989,7 +6627,7 @@ /*func=*/ "subdeviceCtrlCmdNvlinkCoreCallback" #endif }, - { /* [384] */ + { /* [426] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x200u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -6004,7 +6642,7 @@ /*func=*/ "subdeviceCtrlCmdNvlinkGetAliEnabled" #endif }, - { /* [385] */ + { /* [427] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x201u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -6019,7 +6657,7 @@ /*func=*/ "subdeviceCtrlCmdNvlinkUpdateRemoteLocalSid" #endif }, - { /* [386] */ + { /* [428] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x201u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -6034,7 +6672,7 @@ /*func=*/ "subdeviceCtrlCmdNvlinkUpdateHshubMux" #endif }, - { /* [387] */ + { /* [429] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x201u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -6049,7 +6687,7 @@ /*func=*/ "subdeviceCtrlCmdNvlinkPreSetupNvlinkPeer" #endif }, - { /* [388] */ + { /* [430] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x201u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -6064,7 +6702,7 @@ /*func=*/ "subdeviceCtrlCmdNvlinkPostSetupNvlinkPeer" #endif }, - { /* [389] */ + { /* [431] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x201u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -6079,7 +6717,7 @@ /*func=*/ "subdeviceCtrlCmdNvlinkRemoveNvlinkMapping" #endif }, - { /* [390] */ + { /* [432] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x201u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -6094,7 +6732,7 @@ /*func=*/ "subdeviceCtrlCmdNvlinkSaveRestoreHshubState" #endif }, - { /* [391] */ + { /* [433] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x201u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -6109,7 +6747,7 @@ /*func=*/ "subdeviceCtrlCmdNvlinkProgramBufferready" #endif }, - { /* [392] */ + { /* [434] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x201u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -6124,7 +6762,7 @@ /*func=*/ "subdeviceCtrlCmdNvlinkUpdateCurrentConfig" #endif }, - { /* [393] */ + { /* [435] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x200u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -6139,7 +6777,7 @@ /*func=*/ "subdeviceCtrlCmdNvlinkSetLoopbackMode" #endif }, - { /* [394] */ + { /* [436] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x201u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -6154,7 +6792,7 @@ /*func=*/ "subdeviceCtrlCmdNvlinkUpdatePeerLinkMask" #endif }, - { /* [395] */ + { /* [437] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x201u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -6169,7 +6807,7 @@ /*func=*/ "subdeviceCtrlCmdNvlinkUpdateLinkConnection" #endif }, - { /* [396] */ + { /* [438] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x201u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -6184,7 +6822,7 @@ /*func=*/ "subdeviceCtrlCmdNvlinkEnableLinksPostTopology" #endif }, - { /* [397] */ + { /* [439] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x200u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -6199,7 +6837,7 @@ /*func=*/ "subdeviceCtrlCmdNvlinkPreLinkTrainAli" #endif }, - { /* [398] */ + { /* [440] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x200u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -6214,7 +6852,7 @@ /*func=*/ "subdeviceCtrlCmdNvlinkGetRefreshCounters" #endif }, - { /* [399] */ + { /* [441] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x200u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -6229,13 +6867,13 @@ /*func=*/ "subdeviceCtrlCmdNvlinkClearRefreshCounters" #endif }, - { /* [400] */ -#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x201u) + { /* [442] */ +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x100201u) /*pFunc=*/ (void (*)(void)) NULL, #else /*pFunc=*/ (void (*)(void)) subdeviceCtrlCmdNvlinkGetLinkMaskPostRxDet_IMPL, -#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x201u) - /*flags=*/ 0x201u, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x100201u) + /*flags=*/ 0x100201u, /*accessRight=*/0x0u, /*methodId=*/ 0x2080302au, /*paramSize=*/ sizeof(NV2080_CTRL_NVLINK_GET_LINK_MASK_POST_RX_DET_PARAMS), @@ -6244,7 +6882,7 @@ /*func=*/ "subdeviceCtrlCmdNvlinkGetLinkMaskPostRxDet" #endif }, - { /* [401] */ + { /* [443] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x200u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -6259,7 +6897,7 @@ /*func=*/ "subdeviceCtrlCmdNvlinkLinkTrainAli" #endif }, - { /* [402] */ + { /* [444] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x200u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -6274,7 +6912,7 @@ /*func=*/ "subdeviceCtrlCmdNvlinkGetNvlinkDeviceInfo" #endif }, - { /* [403] */ + { /* [445] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x200u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -6289,7 +6927,7 @@ /*func=*/ "subdeviceCtrlCmdNvlinkGetIoctrlDeviceInfo" #endif }, - { /* [404] */ + { /* [446] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x200u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -6304,7 +6942,7 @@ /*func=*/ "subdeviceCtrlCmdNvlinkProgramLinkSpeed" #endif }, - { /* [405] */ + { /* [447] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x201u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -6319,7 +6957,7 @@ /*func=*/ "subdeviceCtrlCmdNvlinkAreLinksTrained" #endif }, - { /* [406] */ + { /* [448] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x200u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -6334,7 +6972,7 @@ /*func=*/ "subdeviceCtrlCmdNvlinkResetLinks" #endif }, - { /* [407] */ + { /* [449] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x200u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -6349,7 +6987,7 @@ /*func=*/ "subdeviceCtrlCmdNvlinkDisableDlInterrupts" #endif }, - { /* [408] */ + { /* [450] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x201u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -6364,7 +7002,7 @@ /*func=*/ "subdeviceCtrlCmdNvlinkGetLinkAndClockInfo" #endif }, - { /* [409] */ + { /* [451] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x200u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -6379,7 +7017,7 @@ /*func=*/ "subdeviceCtrlCmdNvlinkSetupNvlinkSysmem" #endif }, - { /* [410] */ + { /* [452] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x200u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -6394,7 +7032,7 @@ /*func=*/ "subdeviceCtrlCmdNvlinkProcessForcedConfigs" #endif }, - { /* [411] */ + { /* [453] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x200u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -6409,7 +7047,7 @@ /*func=*/ "subdeviceCtrlCmdNvlinkSyncLaneShutdownProps" #endif }, - { /* [412] */ + { /* [454] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x200u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -6424,7 +7062,7 @@ /*func=*/ "subdeviceCtrlCmdNvlinkEnableSysmemNvlinkAts" #endif }, - { /* [413] */ + { /* [455] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x201u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -6439,7 +7077,7 @@ /*func=*/ "subdeviceCtrlCmdNvlinkHshubGetSysmemNvlinkMask" #endif }, - { /* [414] */ + { /* [456] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x200u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -6454,7 +7092,7 @@ /*func=*/ "subdeviceCtrlCmdNvlinkGetSetNvswitchFlaAddr" #endif }, - { /* [415] */ + { /* [457] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x100201u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -6469,7 +7107,7 @@ /*func=*/ "subdeviceCtrlCmdNvlinkSyncLinkMasksAndVbiosInfo" #endif }, - { /* [416] */ + { /* [458] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x200u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -6484,7 +7122,7 @@ /*func=*/ "subdeviceCtrlCmdNvlinkEnableLinks" #endif }, - { /* [417] */ + { /* [459] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x200u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -6499,7 +7137,7 @@ /*func=*/ "subdeviceCtrlCmdNvlinkProcessInitDisabledLinks" #endif }, - { /* [418] */ + { /* [460] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x200u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -6514,7 +7152,7 @@ /*func=*/ "subdeviceCtrlCmdNvlinkEomControl" #endif }, - { /* [419] */ + { /* [461] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x204u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -6529,7 +7167,7 @@ /*func=*/ "subdeviceCtrlCmdNvlinkSetL1Threshold" #endif }, - { /* [420] */ + { /* [462] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -6544,7 +7182,7 @@ /*func=*/ "subdeviceCtrlCmdNvlinkGetL1Threshold" #endif }, - { /* [421] */ + { /* [463] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x1240u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -6559,7 +7197,7 @@ /*func=*/ "subdeviceCtrlCmdNvlinkInbandSendData" #endif }, - { /* [422] */ + { /* [464] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -6574,7 +7212,7 @@ /*func=*/ "subdeviceCtrlCmdNvlinkDirectConnectCheck" #endif }, - { /* [423] */ + { /* [465] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x200u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -6589,7 +7227,7 @@ /*func=*/ "subdeviceCtrlCmdNvlinkPostFaultUp" #endif }, - { /* [424] */ + { /* [466] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x200u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -6604,7 +7242,7 @@ /*func=*/ "subdeviceCtrlCmdIsNvlinkReducedConfig" #endif }, - { /* [425] */ + { /* [467] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -6619,7 +7257,7 @@ /*func=*/ "subdeviceCtrlCmdFlcnGetDmemUsage" #endif }, - { /* [426] */ + { /* [468] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -6634,7 +7272,7 @@ /*func=*/ "subdeviceCtrlCmdFlcnGetEngineArch" #endif }, - { /* [427] */ + { /* [469] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -6649,7 +7287,7 @@ /*func=*/ "subdeviceCtrlCmdFlcnUstreamerQueueInfo" #endif }, - { /* [428] */ + { /* [470] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -6664,7 +7302,7 @@ /*func=*/ "subdeviceCtrlCmdFlcnUstreamerControlGet" #endif }, - { /* [429] */ + { /* [471] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x204u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -6679,13 +7317,13 @@ /*func=*/ "subdeviceCtrlCmdFlcnUstreamerControlSet" #endif }, - { /* [430] */ -#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x200u) + { /* [472] */ +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x0u) /*pFunc=*/ (void (*)(void)) NULL, #else /*pFunc=*/ (void (*)(void)) subdeviceCtrlCmdFlcnGetCtxBufferInfo_IMPL, -#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x200u) - /*flags=*/ 0x200u, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x0u) + /*flags=*/ 0x0u, /*accessRight=*/0x0u, /*methodId=*/ 0x20803124u, /*paramSize=*/ sizeof(NV2080_CTRL_FLCN_GET_CTX_BUFFER_INFO_PARAMS), @@ -6694,13 +7332,13 @@ /*func=*/ "subdeviceCtrlCmdFlcnGetCtxBufferInfo" #endif }, - { /* [431] */ -#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) + { /* [473] */ +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) /*pFunc=*/ (void (*)(void)) NULL, #else /*pFunc=*/ (void (*)(void)) subdeviceCtrlCmdFlcnGetCtxBufferSize_IMPL, -#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) - /*flags=*/ 0x210u, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) + /*flags=*/ 0x10u, /*accessRight=*/0x0u, /*methodId=*/ 0x20803125u, /*paramSize=*/ sizeof(NV2080_CTRL_FLCN_GET_CTX_BUFFER_SIZE_PARAMS), @@ -6709,7 +7347,7 @@ /*func=*/ "subdeviceCtrlCmdFlcnGetCtxBufferSize" #endif }, - { /* [432] */ + { /* [474] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -6724,7 +7362,37 @@ /*func=*/ "subdeviceCtrlCmdEccGetClientExposedCounters" #endif }, - { /* [433] */ + { /* [475] */ +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) + /*pFunc=*/ (void (*)(void)) NULL, +#else + /*pFunc=*/ (void (*)(void)) subdeviceCtrlCmdEccGetEciCounters_IMPL, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) + /*flags=*/ 0x210u, + /*accessRight=*/0x0u, + /*methodId=*/ 0x20803401u, + /*paramSize=*/ sizeof(NV2080_CTRL_ECC_GET_ECI_COUNTERS_PARAMS), + /*pClassInfo=*/ &(__nvoc_class_def_Subdevice.classInfo), +#if NV_PRINTF_STRINGS_ALLOWED + /*func=*/ "subdeviceCtrlCmdEccGetEciCounters" +#endif + }, + { /* [476] */ +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) + /*pFunc=*/ (void (*)(void)) NULL, +#else + /*pFunc=*/ (void (*)(void)) subdeviceCtrlCmdEccGetVolatileCounts_IMPL, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) + /*flags=*/ 0x210u, + /*accessRight=*/0x0u, + /*methodId=*/ 0x20803402u, + /*paramSize=*/ sizeof(NV2080_CTRL_ECC_GET_VOLATILE_COUNTS_PARAMS), + /*pClassInfo=*/ &(__nvoc_class_def_Subdevice.classInfo), +#if NV_PRINTF_STRINGS_ALLOWED + /*func=*/ "subdeviceCtrlCmdEccGetVolatileCounts" +#endif + }, + { /* [477] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x810u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -6739,7 +7407,7 @@ /*func=*/ "subdeviceCtrlCmdFlaRange" #endif }, - { /* [434] */ + { /* [478] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x102204u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -6754,7 +7422,7 @@ /*func=*/ "subdeviceCtrlCmdFlaSetupInstanceMemBlock" #endif }, - { /* [435] */ + { /* [479] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x100004u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -6769,7 +7437,7 @@ /*func=*/ "subdeviceCtrlCmdFlaGetRange" #endif }, - { /* [436] */ + { /* [480] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x1810u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -6784,13 +7452,13 @@ /*func=*/ "subdeviceCtrlCmdFlaGetFabricMemStats" #endif }, - { /* [437] */ -#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x211u) + { /* [481] */ +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x4211u) /*pFunc=*/ (void (*)(void)) NULL, #else /*pFunc=*/ (void (*)(void)) subdeviceCtrlCmdGspGetFeatures_IMPL, -#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x211u) - /*flags=*/ 0x211u, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x4211u) + /*flags=*/ 0x4211u, /*accessRight=*/0x0u, /*methodId=*/ 0x20803601u, /*paramSize=*/ sizeof(NV2080_CTRL_GSP_GET_FEATURES_PARAMS), @@ -6799,7 +7467,22 @@ /*func=*/ "subdeviceCtrlCmdGspGetFeatures" #endif }, - { /* [438] */ + { /* [482] */ +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) + /*pFunc=*/ (void (*)(void)) NULL, +#else + /*pFunc=*/ (void (*)(void)) subdeviceCtrlCmdGspGetRmHeapStats_IMPL, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) + /*flags=*/ 0x210u, + /*accessRight=*/0x0u, + /*methodId=*/ 0x20803602u, + /*paramSize=*/ sizeof(NV2080_CTRL_GSP_GET_RM_HEAP_STATS_PARAMS), + /*pClassInfo=*/ &(__nvoc_class_def_Subdevice.classInfo), +#if NV_PRINTF_STRINGS_ALLOWED + /*func=*/ "subdeviceCtrlCmdGspGetRmHeapStats" +#endif + }, + { /* [483] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x2210u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -6814,7 +7497,7 @@ /*func=*/ "subdeviceCtrlCmdGrmgrGetGrFsInfo" #endif }, - { /* [439] */ + { /* [484] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x3u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -6829,7 +7512,7 @@ /*func=*/ "subdeviceCtrlCmdOsUnixGc6BlockerRefCnt" #endif }, - { /* [440] */ + { /* [485] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x11u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -6844,7 +7527,7 @@ /*func=*/ "subdeviceCtrlCmdOsUnixAllowDisallowGcoff" #endif }, - { /* [441] */ + { /* [486] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x1u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -6859,7 +7542,7 @@ /*func=*/ "subdeviceCtrlCmdOsUnixAudioDynamicPower" #endif }, - { /* [442] */ + { /* [487] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x13u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -6874,7 +7557,7 @@ /*func=*/ "subdeviceCtrlCmdOsUnixVidmemPersistenceStatus" #endif }, - { /* [443] */ + { /* [488] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x7u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -6889,7 +7572,7 @@ /*func=*/ "subdeviceCtrlCmdOsUnixUpdateTgpStatus" #endif }, - { /* [444] */ + { /* [489] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -6904,7 +7587,7 @@ /*func=*/ "subdeviceCtrlCmdVgpuMgrInternalBootloadGspVgpuPluginTask" #endif }, - { /* [445] */ + { /* [490] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -6919,7 +7602,7 @@ /*func=*/ "subdeviceCtrlCmdVgpuMgrInternalShutdownGspVgpuPluginTask" #endif }, - { /* [446] */ + { /* [491] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -6934,7 +7617,7 @@ /*func=*/ "subdeviceCtrlCmdVgpuMgrInternalPgpuAddVgpuType" #endif }, - { /* [447] */ + { /* [492] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -6949,7 +7632,7 @@ /*func=*/ "subdeviceCtrlCmdVgpuMgrInternalEnumerateVgpuPerPgpu" #endif }, - { /* [448] */ + { /* [493] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -6964,7 +7647,7 @@ /*func=*/ "subdeviceCtrlCmdVgpuMgrInternalClearGuestVmInfo" #endif }, - { /* [449] */ + { /* [494] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -6979,7 +7662,7 @@ /*func=*/ "subdeviceCtrlCmdVgpuMgrInternalGetVgpuFbUsage" #endif }, - { /* [450] */ + { /* [495] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -6994,7 +7677,7 @@ /*func=*/ "subdeviceCtrlCmdVgpuMgrInternalSetVgpuEncoderCapacity" #endif }, - { /* [451] */ + { /* [496] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -7009,7 +7692,7 @@ /*func=*/ "subdeviceCtrlCmdVgpuMgrInternalCleanupGspVgpuPluginResources" #endif }, - { /* [452] */ + { /* [497] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -7024,7 +7707,7 @@ /*func=*/ "subdeviceCtrlCmdVgpuMgrInternalGetPgpuFsEncoding" #endif }, - { /* [453] */ + { /* [498] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -7039,7 +7722,7 @@ /*func=*/ "subdeviceCtrlCmdVgpuMgrInternalGetPgpuMigrationSupport" #endif }, - { /* [454] */ + { /* [499] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -7054,7 +7737,7 @@ /*func=*/ "subdeviceCtrlCmdVgpuMgrInternalSetVgpuMgrConfig" #endif }, - { /* [455] */ + { /* [500] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0xa50u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -7069,7 +7752,7 @@ /*func=*/ "subdeviceCtrlCmdGetAvailableHshubMask" #endif }, - { /* [456] */ + { /* [501] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -7084,12 +7767,27 @@ /*func=*/ "subdeviceCtrlCmdPerfGetGpumonPerfmonUtilSamples" #endif }, + { /* [502] */ +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) + /*pFunc=*/ (void (*)(void)) NULL, +#else + /*pFunc=*/ (void (*)(void)) subdeviceCtrlCmdInternalGc6EntryPrerequisite_IMPL, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) + /*flags=*/ 0x600u, + /*accessRight=*/0x0u, + /*methodId=*/ 0x2080a7d7u, + /*paramSize=*/ sizeof(NV2080_CTRL_INTERNAL_GC6_ENTRY_PREREQUISITE_PARAMS), + /*pClassInfo=*/ &(__nvoc_class_def_Subdevice.classInfo), +#if NV_PRINTF_STRINGS_ALLOWED + /*func=*/ "subdeviceCtrlCmdInternalGc6EntryPrerequisite" +#endif + }, }; const struct NVOC_EXPORT_INFO __nvoc_export_info_Subdevice = { - /*numEntries=*/ 457, + /*numEntries=*/ 503, /*pExportEntries=*/ __nvoc_exported_method_def_Subdevice }; @@ -7157,7 +7855,7 @@ pThis->__subdeviceCtrlCmdBiosGetNbsiV2__ = &subdeviceCtrlCmdBiosGetNbsiV2_IMPL; #endif -#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) +#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x212u) pThis->__subdeviceCtrlCmdBiosGetSKUInfo__ = &subdeviceCtrlCmdBiosGetSKUInfo_IMPL; #endif @@ -7169,7 +7867,7 @@ pThis->__subdeviceCtrlCmdBiosGetUefiSupport__ = &subdeviceCtrlCmdBiosGetUefiSupport_IMPL; #endif -#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x812u) +#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x4813u) pThis->__subdeviceCtrlCmdMcGetArchInfo__ = &subdeviceCtrlCmdMcGetArchInfo_IMPL; #endif @@ -7189,7 +7887,7 @@ pThis->__subdeviceCtrlCmdMcChangeReplayableFaultOwnership__ = &subdeviceCtrlCmdMcChangeReplayableFaultOwnership_IMPL; #endif -#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) +#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x850u) pThis->__subdeviceCtrlCmdMcServiceInterrupts__ = &subdeviceCtrlCmdMcServiceInterrupts_IMPL; #endif @@ -7201,7 +7899,7 @@ pThis->__subdeviceCtrlCmdDmaGetInfo__ = &subdeviceCtrlCmdDmaGetInfo_IMPL; #endif -#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x850u) +#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x4850u) pThis->__subdeviceCtrlCmdBusGetPciInfo__ = &subdeviceCtrlCmdBusGetPciInfo_IMPL; #endif @@ -7209,11 +7907,11 @@ pThis->__subdeviceCtrlCmdBusGetInfo__ = &subdeviceCtrlCmdBusGetInfo_IMPL; #endif -#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x850u) +#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x200850u) pThis->__subdeviceCtrlCmdBusGetInfoV2__ = &subdeviceCtrlCmdBusGetInfoV2_IMPL; #endif -#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x850u) +#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x4850u) pThis->__subdeviceCtrlCmdBusGetPciBarInfo__ = &subdeviceCtrlCmdBusGetPciBarInfo_IMPL; #endif @@ -7249,7 +7947,7 @@ pThis->__subdeviceCtrlCmdBusGetBFD__ = &subdeviceCtrlCmdBusGetBFD_IMPL; #endif -#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) +#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x850u) pThis->__subdeviceCtrlCmdBusGetAspmDisableFlags__ = &subdeviceCtrlCmdBusGetAspmDisableFlags_IMPL; #endif @@ -7285,7 +7983,7 @@ pThis->__subdeviceCtrlCmdBusSetPcieLtrLatency__ = &subdeviceCtrlCmdBusSetPcieLtrLatency_IMPL; #endif -#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) +#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x810u) pThis->__subdeviceCtrlCmdBusGetNvlinkPeerIdMask__ = &subdeviceCtrlCmdBusGetNvlinkPeerIdMask_IMPL; #endif @@ -7301,9 +7999,8 @@ pThis->__subdeviceCtrlCmdBusGetEomStatus__ = &subdeviceCtrlCmdBusGetEomStatus_IMPL; #endif -#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x6210u) - pThis->__subdeviceCtrlCmdBusGetPcieReqAtomicsCaps__ = &subdeviceCtrlCmdBusGetPcieReqAtomicsCaps_IMPL; -#endif + // Hal function -- subdeviceCtrlCmdBusGetPcieReqAtomicsCaps + pThis->__subdeviceCtrlCmdBusGetPcieReqAtomicsCaps__ = &subdeviceCtrlCmdBusGetPcieReqAtomicsCaps_92bfc3; #if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x6210u) pThis->__subdeviceCtrlCmdBusGetPcieSupportedGpuAtomics__ = &subdeviceCtrlCmdBusGetPcieSupportedGpuAtomics_IMPL; @@ -7317,7 +8014,7 @@ pThis->__subdeviceCtrlCmdBusGetC2CErrorInfo__ = &subdeviceCtrlCmdBusGetC2CErrorInfo_IMPL; #endif -#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10200u) +#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10000u) pThis->__subdeviceCtrlCmdBusSysmemAccess__ = &subdeviceCtrlCmdBusSysmemAccess_IMPL; #endif @@ -7449,7 +8146,7 @@ pThis->__subdeviceCtrlCmdNvlinkClearRefreshCounters__ = &subdeviceCtrlCmdNvlinkClearRefreshCounters_IMPL; #endif -#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x201u) +#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x100201u) pThis->__subdeviceCtrlCmdNvlinkGetLinkMaskPostRxDet__ = &subdeviceCtrlCmdNvlinkGetLinkMaskPostRxDet_IMPL; #endif @@ -7578,30 +8275,18 @@ #endif // Hal function -- subdeviceCtrlCmdPerfRatedTdpSetControl - if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000002UL) )) /* RmVariantHal: PF_KERNEL_ONLY */ - { - pThis->__subdeviceCtrlCmdPerfRatedTdpSetControl__ = &subdeviceCtrlCmdPerfRatedTdpSetControl_KERNEL; - } + pThis->__subdeviceCtrlCmdPerfRatedTdpSetControl__ = &subdeviceCtrlCmdPerfRatedTdpSetControl_KERNEL; // Hal function -- subdeviceCtrlCmdPerfReservePerfmonHw - if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000002UL) )) /* RmVariantHal: PF_KERNEL_ONLY */ - { - pThis->__subdeviceCtrlCmdPerfReservePerfmonHw__ = &subdeviceCtrlCmdPerfReservePerfmonHw_KERNEL; - } + pThis->__subdeviceCtrlCmdPerfReservePerfmonHw__ = &subdeviceCtrlCmdPerfReservePerfmonHw_KERNEL; // Hal function -- subdeviceCtrlCmdPerfSetAuxPowerState - if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000002UL) )) /* RmVariantHal: PF_KERNEL_ONLY */ - { - pThis->__subdeviceCtrlCmdPerfSetAuxPowerState__ = &subdeviceCtrlCmdPerfSetAuxPowerState_KERNEL; - } + pThis->__subdeviceCtrlCmdPerfSetAuxPowerState__ = &subdeviceCtrlCmdPerfSetAuxPowerState_KERNEL; // Hal function -- subdeviceCtrlCmdPerfSetPowerstate - if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000002UL) )) /* RmVariantHal: PF_KERNEL_ONLY */ - { - pThis->__subdeviceCtrlCmdPerfSetPowerstate__ = &subdeviceCtrlCmdPerfSetPowerstate_KERNEL; - } + pThis->__subdeviceCtrlCmdPerfSetPowerstate__ = &subdeviceCtrlCmdPerfSetPowerstate_KERNEL; -#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x810u) +#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x850u) pThis->__subdeviceCtrlCmdKPerfBoost__ = &subdeviceCtrlCmdKPerfBoost_IMPL; #endif @@ -7629,6 +8314,13 @@ pThis->__subdeviceCtrlCmdInternalMemmgrGetVgpuHostRmReservedFb__ = &subdeviceCtrlCmdInternalMemmgrGetVgpuHostRmReservedFb_IMPL; #endif +#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) + pThis->__subdeviceCtrlCmdGbGetSemaphoreSurfaceLayout__ = &subdeviceCtrlCmdGbGetSemaphoreSurfaceLayout_IMPL; +#endif + + // Hal function -- subdeviceCtrlCmdInternalMemmgrMemoryTransferWithGsp + pThis->__subdeviceCtrlCmdInternalMemmgrMemoryTransferWithGsp__ = &subdeviceCtrlCmdInternalMemmgrMemoryTransferWithGsp_46f6a7; + #if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x850u) pThis->__subdeviceCtrlCmdFbGetInfo__ = &subdeviceCtrlCmdFbGetInfo_IMPL; #endif @@ -7785,15 +8477,15 @@ pThis->__subdeviceCtrlCmdFifoBindEngines__ = &subdeviceCtrlCmdFifoBindEngines_IMPL; #endif -#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) +#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x850u) pThis->__subdeviceCtrlCmdGetPhysicalChannelCount__ = &subdeviceCtrlCmdGetPhysicalChannelCount_IMPL; #endif -#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) +#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x200010u) pThis->__subdeviceCtrlCmdFifoGetInfo__ = &subdeviceCtrlCmdFifoGetInfo_IMPL; #endif -#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) +#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x810u) pThis->__subdeviceCtrlCmdFifoDisableChannels__ = &subdeviceCtrlCmdFifoDisableChannels_IMPL; #endif @@ -7833,7 +8525,7 @@ pThis->__subdeviceCtrlCmdInternalFifoPromoteRunlistBuffers__ = &subdeviceCtrlCmdInternalFifoPromoteRunlistBuffers_IMPL; #endif -#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x2610u) +#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x2e50u) pThis->__subdeviceCtrlCmdInternalFifoGetNumChannels__ = &subdeviceCtrlCmdInternalFifoGetNumChannels_IMPL; #endif @@ -7841,6 +8533,10 @@ pThis->__subdeviceCtrlCmdFifoGetAllocatedChannels__ = &subdeviceCtrlCmdFifoGetAllocatedChannels_IMPL; #endif +#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x2610u) + pThis->__subdeviceCtrlCmdInternalFifoGetNumSecureChannels__ = &subdeviceCtrlCmdInternalFifoGetNumSecureChannels_IMPL; +#endif + #if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x50u) pThis->__subdeviceCtrlCmdKGrGetInfo__ = &subdeviceCtrlCmdKGrGetInfo_IMPL; #endif @@ -8009,7 +8705,7 @@ pThis->__subdeviceCtrlCmdKGrInternalStaticGetInfo__ = &subdeviceCtrlCmdKGrInternalStaticGetInfo_IMPL; #endif -#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x2600u) +#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x102600u) pThis->__subdeviceCtrlCmdKGrInternalStaticGetCaps__ = &subdeviceCtrlCmdKGrInternalStaticGetCaps_IMPL; #endif @@ -8057,7 +8753,7 @@ pThis->__subdeviceCtrlCmdGpuGetCachedInfo__ = &subdeviceCtrlCmdGpuGetCachedInfo_IMPL; #endif -#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x850u) +#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x200850u) pThis->__subdeviceCtrlCmdGpuGetInfoV2__ = &subdeviceCtrlCmdGpuGetInfoV2_IMPL; #endif @@ -8077,7 +8773,7 @@ pThis->__subdeviceCtrlCmdGpuSetOptimusInfo__ = &subdeviceCtrlCmdGpuSetOptimusInfo_IMPL; #endif -#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0xa12u) +#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x200a12u) pThis->__subdeviceCtrlCmdGpuGetNameString__ = &subdeviceCtrlCmdGpuGetNameString_IMPL; #endif @@ -8113,6 +8809,10 @@ pThis->__subdeviceCtrlCmdGpuSetFabricAddr__ = &subdeviceCtrlCmdGpuSetFabricAddr_IMPL; #endif +#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) + pThis->__subdeviceCtrlCmdGpuSetEgmGpaFabricAddr__ = &subdeviceCtrlCmdGpuSetEgmGpaFabricAddr_IMPL; +#endif + #if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) pThis->__subdeviceCtrlCmdGpuSetPower__ = &subdeviceCtrlCmdGpuSetPower_IMPL; #endif @@ -8125,7 +8825,7 @@ pThis->__subdeviceCtrlCmdGpuSetSdm__ = &subdeviceCtrlCmdGpuSetSdm_IMPL; #endif -#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x813u) +#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x4813u) pThis->__subdeviceCtrlCmdGpuGetSimulationInfo__ = &subdeviceCtrlCmdGpuGetSimulationInfo_IMPL; #endif @@ -8153,7 +8853,7 @@ pThis->__subdeviceCtrlCmdGpuGetFermiTpcInfo__ = &subdeviceCtrlCmdGpuGetFermiTpcInfo_IMPL; #endif -#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) +#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x850u) pThis->__subdeviceCtrlCmdGpuGetFermiZcullInfo__ = &subdeviceCtrlCmdGpuGetFermiZcullInfo_IMPL; #endif @@ -8161,11 +8861,11 @@ pThis->__subdeviceCtrlCmdGpuGetPesInfo__ = &subdeviceCtrlCmdGpuGetPesInfo_IMPL; #endif -#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) +#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x850u) pThis->__subdeviceCtrlCmdGpuExecRegOps__ = &subdeviceCtrlCmdGpuExecRegOps_IMPL; #endif -#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) +#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x850u) pThis->__subdeviceCtrlCmdGpuMigratableOps__ = &subdeviceCtrlCmdGpuMigratableOps_IMPL; #endif @@ -8184,6 +8884,15 @@ #if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) pThis->__subdeviceCtrlCmdGpuQueryInforomEccSupport__ = &subdeviceCtrlCmdGpuQueryInforomEccSupport_IMPL; #endif +} + +static void __nvoc_init_funcTable_Subdevice_2(Subdevice *pThis, RmHalspecOwner *pRmhalspecowner) { + RmVariantHal *rmVariantHal = &pRmhalspecowner->rmVariantHal; + const unsigned long rmVariantHal_HalVarIdx = (unsigned long)rmVariantHal->__nvoc_HalVarIdx; + PORT_UNREFERENCED_VARIABLE(pThis); + PORT_UNREFERENCED_VARIABLE(pRmhalspecowner); + PORT_UNREFERENCED_VARIABLE(rmVariantHal); + PORT_UNREFERENCED_VARIABLE(rmVariantHal_HalVarIdx); #if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0xa50u) pThis->__subdeviceCtrlCmdGpuQueryEccStatus__ = &subdeviceCtrlCmdGpuQueryEccStatus_IMPL; @@ -8200,17 +8909,8 @@ #if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x4210u) pThis->__subdeviceCtrlCmdGpuGetOEMInfo__ = &subdeviceCtrlCmdGpuGetOEMInfo_IMPL; #endif -} - -static void __nvoc_init_funcTable_Subdevice_2(Subdevice *pThis, RmHalspecOwner *pRmhalspecowner) { - RmVariantHal *rmVariantHal = &pRmhalspecowner->rmVariantHal; - const unsigned long rmVariantHal_HalVarIdx = (unsigned long)rmVariantHal->__nvoc_HalVarIdx; - PORT_UNREFERENCED_VARIABLE(pThis); - PORT_UNREFERENCED_VARIABLE(pRmhalspecowner); - PORT_UNREFERENCED_VARIABLE(rmVariantHal); - PORT_UNREFERENCED_VARIABLE(rmVariantHal_HalVarIdx); -#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x13u) +#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x3u) pThis->__subdeviceCtrlCmdGpuHandleGpuSR__ = &subdeviceCtrlCmdGpuHandleGpuSR_IMPL; #endif @@ -8218,15 +8918,15 @@ pThis->__subdeviceCtrlCmdGpuSetComputeModeRules__ = &subdeviceCtrlCmdGpuSetComputeModeRules_IMPL; #endif -#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x11u) +#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x811u) pThis->__subdeviceCtrlCmdGpuQueryComputeModeRules__ = &subdeviceCtrlCmdGpuQueryComputeModeRules_IMPL; #endif -#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x11u) +#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x850u) pThis->__subdeviceCtrlCmdGpuAcquireComputeModeReservation__ = &subdeviceCtrlCmdGpuAcquireComputeModeReservation_IMPL; #endif -#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x11u) +#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x850u) pThis->__subdeviceCtrlCmdGpuReleaseComputeModeReservation__ = &subdeviceCtrlCmdGpuReleaseComputeModeReservation_IMPL; #endif @@ -8302,6 +9002,10 @@ pThis->__subdeviceCtrlCmdGpuGetHwEngineId__ = &subdeviceCtrlCmdGpuGetHwEngineId_IMPL; #endif +#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x4210u) + pThis->__subdeviceCtrlCmdGpuGetVmmuSegmentSize__ = &subdeviceCtrlCmdGpuGetVmmuSegmentSize_IMPL; +#endif + #if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x50u) pThis->__subdeviceCtrlCmdGpuGetMaxSupportedPageSize__ = &subdeviceCtrlCmdGpuGetMaxSupportedPageSize_IMPL; #endif @@ -8310,15 +9014,15 @@ pThis->__subdeviceCtrlCmdGpuHandleVfPriFault__ = &subdeviceCtrlCmdGpuHandleVfPriFault_IMPL; #endif -#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x4u) +#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x807u) pThis->__subdeviceCtrlCmdGpuSetComputePolicyConfig__ = &subdeviceCtrlCmdGpuSetComputePolicyConfig_IMPL; #endif -#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) +#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x813u) pThis->__subdeviceCtrlCmdGpuGetComputePolicyConfig__ = &subdeviceCtrlCmdGpuGetComputePolicyConfig_IMPL; #endif -#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x0u) +#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x840u) pThis->__subdeviceCtrlCmdValidateMemMapRequest__ = &subdeviceCtrlCmdValidateMemMapRequest_IMPL; #endif @@ -8338,10 +9042,18 @@ pThis->__subdeviceCtrlCmdGetP2pCaps__ = &subdeviceCtrlCmdGetP2pCaps_IMPL; #endif -#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x50u) +#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x850u) pThis->__subdeviceCtrlCmdGetGpuFabricProbeInfo__ = &subdeviceCtrlCmdGetGpuFabricProbeInfo_IMPL; #endif +#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) + pThis->__subdeviceCtrlCmdGpuGetResetStatus__ = &subdeviceCtrlCmdGpuGetResetStatus_IMPL; +#endif + +#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) + pThis->__subdeviceCtrlCmdGpuGetDrainAndResetStatus__ = &subdeviceCtrlCmdGpuGetDrainAndResetStatus_IMPL; +#endif + #if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) pThis->__subdeviceCtrlCmdEventSetTrigger__ = &subdeviceCtrlCmdEventSetTrigger_IMPL; #endif @@ -8406,23 +9118,23 @@ pThis->__subdeviceCtrlCmdRcSetCleanErrorHistory__ = &subdeviceCtrlCmdRcSetCleanErrorHistory_IMPL; #endif -#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) +#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x850u) pThis->__subdeviceCtrlCmdRcGetWatchdogInfo__ = &subdeviceCtrlCmdRcGetWatchdogInfo_IMPL; #endif -#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) +#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x50u) pThis->__subdeviceCtrlCmdRcDisableWatchdog__ = &subdeviceCtrlCmdRcDisableWatchdog_IMPL; #endif -#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) +#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x50u) pThis->__subdeviceCtrlCmdRcSoftDisableWatchdog__ = &subdeviceCtrlCmdRcSoftDisableWatchdog_IMPL; #endif -#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) +#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x50u) pThis->__subdeviceCtrlCmdRcEnableWatchdog__ = &subdeviceCtrlCmdRcEnableWatchdog_IMPL; #endif -#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) +#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x50u) pThis->__subdeviceCtrlCmdRcReleaseWatchdogRequests__ = &subdeviceCtrlCmdRcReleaseWatchdogRequests_IMPL; #endif @@ -8478,7 +9190,7 @@ pThis->__subdeviceCtrlCmdCeGetCaps__ = &subdeviceCtrlCmdCeGetCaps_IMPL; #endif -#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x211u) +#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x2211u) pThis->__subdeviceCtrlCmdCeGetCePceMask__ = &subdeviceCtrlCmdCeGetCePceMask_IMPL; #endif @@ -8486,11 +9198,11 @@ pThis->__subdeviceCtrlCmdCeUpdatePceLceMappings__ = &subdeviceCtrlCmdCeUpdatePceLceMappings_IMPL; #endif -#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x850u) +#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x2850u) pThis->__subdeviceCtrlCmdCeGetCapsV2__ = &subdeviceCtrlCmdCeGetCapsV2_IMPL; #endif -#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x2850u) +#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x2810u) pThis->__subdeviceCtrlCmdCeGetAllCaps__ = &subdeviceCtrlCmdCeGetAllCaps_IMPL; #endif @@ -8514,11 +9226,11 @@ pThis->__subdeviceCtrlCmdFlcnUstreamerControlSet__ = &subdeviceCtrlCmdFlcnUstreamerControlSet_IMPL; #endif -#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x200u) +#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x0u) pThis->__subdeviceCtrlCmdFlcnGetCtxBufferInfo__ = &subdeviceCtrlCmdFlcnGetCtxBufferInfo_IMPL; #endif -#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) +#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) pThis->__subdeviceCtrlCmdFlcnGetCtxBufferSize__ = &subdeviceCtrlCmdFlcnGetCtxBufferSize_IMPL; #endif @@ -8527,6 +9239,14 @@ #endif #if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) + pThis->__subdeviceCtrlCmdEccGetEciCounters__ = &subdeviceCtrlCmdEccGetEciCounters_IMPL; +#endif + +#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) + pThis->__subdeviceCtrlCmdEccGetVolatileCounts__ = &subdeviceCtrlCmdEccGetVolatileCounts_IMPL; +#endif + +#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) pThis->__subdeviceCtrlCmdGpuQueryEccConfiguration__ = &subdeviceCtrlCmdGpuQueryEccConfiguration_IMPL; #endif @@ -8554,10 +9274,14 @@ pThis->__subdeviceCtrlCmdFlaGetFabricMemStats__ = &subdeviceCtrlCmdFlaGetFabricMemStats_IMPL; #endif -#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x211u) +#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x4211u) pThis->__subdeviceCtrlCmdGspGetFeatures__ = &subdeviceCtrlCmdGspGetFeatures_IMPL; #endif +#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) + pThis->__subdeviceCtrlCmdGspGetRmHeapStats__ = &subdeviceCtrlCmdGspGetRmHeapStats_IMPL; +#endif + #if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) pThis->__subdeviceCtrlCmdGpuGetActivePartitionIds__ = &subdeviceCtrlCmdGpuGetActivePartitionIds_IMPL; #endif @@ -8614,6 +9338,10 @@ pThis->__subdeviceCtrlCmdInternalKMIGmgrImportGPUInstance__ = &subdeviceCtrlCmdInternalKMIGmgrImportGPUInstance_IMPL; #endif +#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x2600u) + pThis->__subdeviceCtrlCmdInternalKMIGmgrPromoteGpuInstanceMemRange__ = &subdeviceCtrlCmdInternalKMIGmgrPromoteGpuInstanceMemRange_IMPL; +#endif + #if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x3u) pThis->__subdeviceCtrlCmdOsUnixGc6BlockerRefCnt__ = &subdeviceCtrlCmdOsUnixGc6BlockerRefCnt_IMPL; #endif @@ -8662,24 +9390,60 @@ pThis->__subdeviceCtrlCmdDisplayGetDisplayMask__ = &subdeviceCtrlCmdDisplayGetDisplayMask_IMPL; #endif -#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x4600u) - pThis->__subdeviceCtrlCmdMsencGetCaps__ = &subdeviceCtrlCmdMsencGetCaps_IMPL; +#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) + pThis->__subdeviceCtrlCmdDisplayPinsetsToLockpins__ = &subdeviceCtrlCmdDisplayPinsetsToLockpins_IMPL; #endif #if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) - pThis->__subdeviceCtrlCmdInternalUvmRegisterAccessCntrBuffer__ = &subdeviceCtrlCmdInternalUvmRegisterAccessCntrBuffer_IMPL; + pThis->__subdeviceCtrlCmdDisplaySetSliLinkGpioSwControl__ = &subdeviceCtrlCmdDisplaySetSliLinkGpioSwControl_IMPL; #endif #if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) - pThis->__subdeviceCtrlCmdInternalUvmUnregisterAccessCntrBuffer__ = &subdeviceCtrlCmdInternalUvmUnregisterAccessCntrBuffer_IMPL; + pThis->__subdeviceCtrlCmdInternalGpioProgramDirection__ = &subdeviceCtrlCmdInternalGpioProgramDirection_IMPL; +#endif + +#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) + pThis->__subdeviceCtrlCmdInternalGpioProgramOutput__ = &subdeviceCtrlCmdInternalGpioProgramOutput_IMPL; +#endif + +#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) + pThis->__subdeviceCtrlCmdInternalGpioReadInput__ = &subdeviceCtrlCmdInternalGpioReadInput_IMPL; +#endif + +#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) + pThis->__subdeviceCtrlCmdInternalGpioActivateHwFunction__ = &subdeviceCtrlCmdInternalGpioActivateHwFunction_IMPL; +#endif + +#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) + pThis->__subdeviceCtrlCmdInternalDisplayAcpiSubsytemActivated__ = &subdeviceCtrlCmdInternalDisplayAcpiSubsytemActivated_IMPL; +#endif + +#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) + pThis->__subdeviceCtrlCmdInternalDisplayPreModeSet__ = &subdeviceCtrlCmdInternalDisplayPreModeSet_IMPL; +#endif + +#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) + pThis->__subdeviceCtrlCmdInternalDisplayPostModeSet__ = &subdeviceCtrlCmdInternalDisplayPostModeSet_IMPL; +#endif + +#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) + pThis->__subdeviceCtrlCmdDisplayUnixConsole__ = &subdeviceCtrlCmdDisplayUnixConsole_IMPL; +#endif + +#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) + pThis->__subdeviceCtrlCmdDisplayPostVgaRestore__ = &subdeviceCtrlCmdDisplayPostVgaRestore_IMPL; +#endif + +#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x4600u) + pThis->__subdeviceCtrlCmdMsencGetCaps__ = &subdeviceCtrlCmdMsencGetCaps_IMPL; #endif #if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) - pThis->__subdeviceCtrlCmdInternalUvmServiceAccessCntrBuffer__ = &subdeviceCtrlCmdInternalUvmServiceAccessCntrBuffer_IMPL; + pThis->__subdeviceCtrlCmdInternalUvmRegisterAccessCntrBuffer__ = &subdeviceCtrlCmdInternalUvmRegisterAccessCntrBuffer_IMPL; #endif #if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) - pThis->__subdeviceCtrlCmdInternalUvmGetAccessCntrBufferSize__ = &subdeviceCtrlCmdInternalUvmGetAccessCntrBufferSize_IMPL; + pThis->__subdeviceCtrlCmdInternalUvmUnregisterAccessCntrBuffer__ = &subdeviceCtrlCmdInternalUvmUnregisterAccessCntrBuffer_IMPL; #endif #if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x4600u) @@ -8731,6 +9495,10 @@ #endif #if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) + pThis->__subdeviceCtrlCmdInternalVmmuGetSpaForGpaEntries__ = &subdeviceCtrlCmdInternalVmmuGetSpaForGpaEntries_IMPL; +#endif + +#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) pThis->__subdeviceCtrlCmdGmmuGetStaticInfo__ = &subdeviceCtrlCmdGmmuGetStaticInfo_IMPL; #endif @@ -8827,10 +9595,14 @@ #endif #if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) - pThis->__subdeviceCtrlCmdBifGetStaticInfo__ = &subdeviceCtrlCmdBifGetStaticInfo_IMPL; + pThis->__subdeviceCtrlCmdInternalGc6EntryPrerequisite__ = &subdeviceCtrlCmdInternalGc6EntryPrerequisite_IMPL; #endif #if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) + pThis->__subdeviceCtrlCmdBifGetStaticInfo__ = &subdeviceCtrlCmdBifGetStaticInfo_IMPL; +#endif + +#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0xe40u) pThis->__subdeviceCtrlCmdBifGetAspmL1Flags__ = &subdeviceCtrlCmdBifGetAspmL1Flags_IMPL; #endif @@ -8839,6 +9611,10 @@ #endif #if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) + pThis->__subdeviceCtrlCmdBifDisableSystemMemoryAccess__ = &subdeviceCtrlCmdBifDisableSystemMemoryAccess_IMPL; +#endif + +#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) pThis->__subdeviceCtrlCmdHshubPeerConnConfig__ = &subdeviceCtrlCmdHshubPeerConnConfig_IMPL; #endif @@ -8859,6 +9635,10 @@ #endif #if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) + pThis->__subdeviceCtrlCmdHshubEgmConfig__ = &subdeviceCtrlCmdHshubEgmConfig_IMPL; +#endif + +#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) pThis->__subdeviceCtrlCmdInternalNvlinkEnableComputePeerAddr__ = &subdeviceCtrlCmdInternalNvlinkEnableComputePeerAddr_IMPL; #endif @@ -8866,11 +9646,11 @@ pThis->__subdeviceCtrlCmdInternalNvlinkGetSetNvswitchFabricAddr__ = &subdeviceCtrlCmdInternalNvlinkGetSetNvswitchFabricAddr_IMPL; #endif -#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) +#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x100600u) pThis->__subdeviceCtrlCmdInternalNvlinkGetNumActiveLinksPerIoctrl__ = &subdeviceCtrlCmdInternalNvlinkGetNumActiveLinksPerIoctrl_IMPL; #endif -#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) +#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x100600u) pThis->__subdeviceCtrlCmdInternalNvlinkGetTotalNumLinksPerIoctrl__ = &subdeviceCtrlCmdInternalNvlinkGetTotalNumLinksPerIoctrl_IMPL; #endif @@ -8891,6 +9671,14 @@ #endif #if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) + pThis->__subdeviceCtrlCmdInternalGetLocalAtsConfig__ = &subdeviceCtrlCmdInternalGetLocalAtsConfig_IMPL; +#endif + +#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) + pThis->__subdeviceCtrlCmdInternalSetPeerAtsConfig__ = &subdeviceCtrlCmdInternalSetPeerAtsConfig_IMPL; +#endif + +#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) pThis->__subdeviceCtrlCmdInternalInitGpuIntr__ = &subdeviceCtrlCmdInternalInitGpuIntr_IMPL; #endif @@ -8931,10 +9719,86 @@ #endif #if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) + pThis->__subdeviceCtrlCmdInternalSetStaticEdidData__ = &subdeviceCtrlCmdInternalSetStaticEdidData_IMPL; +#endif + +#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) + pThis->__subdeviceCtrlCmdInternalSmbpbiPfmReqHndlrCapUpdate__ = &subdeviceCtrlCmdInternalSmbpbiPfmReqHndlrCapUpdate_IMPL; +#endif + +#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) + pThis->__subdeviceCtrlCmdInternalPmgrPfmReqHndlrStateLoadSync__ = &subdeviceCtrlCmdInternalPmgrPfmReqHndlrStateLoadSync_IMPL; +#endif + +#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) + pThis->__subdeviceCtrlCmdInternalThermPfmReqHndlrStateInitSync__ = &subdeviceCtrlCmdInternalThermPfmReqHndlrStateInitSync_IMPL; +#endif + +#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) + pThis->__subdeviceCtrlCmdInternalPerfPfmReqHndlrGetPm1State__ = &subdeviceCtrlCmdInternalPerfPfmReqHndlrGetPm1State_IMPL; +#endif + +#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) + pThis->__subdeviceCtrlCmdInternalPerfPfmReqHndlrSetPm1State__ = &subdeviceCtrlCmdInternalPerfPfmReqHndlrSetPm1State_IMPL; +#endif + +#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) + pThis->__subdeviceCtrlCmdInternalPmgrPfmReqHndlrUpdateEdppLimit__ = &subdeviceCtrlCmdInternalPmgrPfmReqHndlrUpdateEdppLimit_IMPL; +#endif + +#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) + pThis->__subdeviceCtrlCmdInternalPmgrPfmReqHndlrGetEdppLimitInfo__ = &subdeviceCtrlCmdInternalPmgrPfmReqHndlrGetEdppLimitInfo_IMPL; +#endif + +#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) + pThis->__subdeviceCtrlCmdInternalThermPfmReqHndlrUpdateTgpuLimit__ = &subdeviceCtrlCmdInternalThermPfmReqHndlrUpdateTgpuLimit_IMPL; +#endif + +#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) + pThis->__subdeviceCtrlCmdInternalPmgrPfmReqHndlrConfigureTgpMode__ = &subdeviceCtrlCmdInternalPmgrPfmReqHndlrConfigureTgpMode_IMPL; +#endif + +#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) + pThis->__subdeviceCtrlCmdInternalPmgrPfmReqHndlrConfigureTurboV2__ = &subdeviceCtrlCmdInternalPmgrPfmReqHndlrConfigureTurboV2_IMPL; +#endif + +#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) + pThis->__subdeviceCtrlCmdInternalPerfPfmReqHndlrGetVpstateInfo__ = &subdeviceCtrlCmdInternalPerfPfmReqHndlrGetVpstateInfo_IMPL; +#endif + +#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) + pThis->__subdeviceCtrlCmdInternalPerfPfmReqHndlrGetVpstateMapping__ = &subdeviceCtrlCmdInternalPerfPfmReqHndlrGetVpstateMapping_IMPL; +#endif + +#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) + pThis->__subdeviceCtrlCmdInternalPerfPfmReqHndlrSetVpstate__ = &subdeviceCtrlCmdInternalPerfPfmReqHndlrSetVpstate_IMPL; +#endif + +#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) pThis->__subdeviceCtrlCmdInternalPmgrUnsetDynamicBoostLimit__ = &subdeviceCtrlCmdInternalPmgrUnsetDynamicBoostLimit_IMPL; #endif #if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) + pThis->__subdeviceCtrlCmdInternalDetectHsVideoBridge__ = &subdeviceCtrlCmdInternalDetectHsVideoBridge_IMPL; +#endif + +#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) + pThis->__subdeviceCtrlCmdInternalConfComputeGetStaticInfo__ = &subdeviceCtrlCmdInternalConfComputeGetStaticInfo_IMPL; +#endif + +#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) + pThis->__subdeviceCtrlCmdInternalConfComputeEncryptionControl__ = &subdeviceCtrlCmdInternalConfComputeEncryptionControl_IMPL; +#endif + +#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) + pThis->__subdeviceCtrlCmdInternalConfComputeDeriveSwlKeys__ = &subdeviceCtrlCmdInternalConfComputeDeriveSwlKeys_IMPL; +#endif + +#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) + pThis->__subdeviceCtrlCmdInternalConfComputeDeriveLceKeys__ = &subdeviceCtrlCmdInternalConfComputeDeriveLceKeys_IMPL; +#endif + +#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) pThis->__subdeviceCtrlCmdVgpuMgrInternalBootloadGspVgpuPluginTask__ = &subdeviceCtrlCmdVgpuMgrInternalBootloadGspVgpuPluginTask_IMPL; #endif @@ -8994,6 +9858,10 @@ pThis->__subdeviceCtrlCmdCcuSetStreamState__ = &subdeviceCtrlCmdCcuSetStreamState_IMPL; #endif +#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) + pThis->__subdeviceCtrlCmdSpdmPartition__ = &subdeviceCtrlCmdSpdmPartition_IMPL; +#endif + pThis->__nvoc_base_GpuResource.__nvoc_base_RmResource.__nvoc_base_RsResource.__resPreDestruct__ = &__nvoc_thunk_Subdevice_resPreDestruct; pThis->__nvoc_base_GpuResource.__gpuresInternalControlForward__ = &__nvoc_thunk_Subdevice_gpuresInternalControlForward; @@ -9002,11 +9870,11 @@ pThis->__subdeviceShareCallback__ = &__nvoc_thunk_GpuResource_subdeviceShareCallback; - pThis->__subdeviceMapTo__ = &__nvoc_thunk_RsResource_subdeviceMapTo; + pThis->__subdeviceCheckMemInterUnmap__ = &__nvoc_thunk_RmResource_subdeviceCheckMemInterUnmap; pThis->__subdeviceGetOrAllocNotifShare__ = &__nvoc_thunk_Notifier_subdeviceGetOrAllocNotifShare; - pThis->__subdeviceCheckMemInterUnmap__ = &__nvoc_thunk_RmResource_subdeviceCheckMemInterUnmap; + pThis->__subdeviceMapTo__ = &__nvoc_thunk_RsResource_subdeviceMapTo; pThis->__subdeviceGetMapAddrSpace__ = &__nvoc_thunk_GpuResource_subdeviceGetMapAddrSpace; @@ -9037,11 +9905,24 @@ pThis->__subdeviceGetMemoryMappingDescriptor__ = &__nvoc_thunk_RmResource_subdeviceGetMemoryMappingDescriptor; pThis->__subdeviceUnregisterEvent__ = &__nvoc_thunk_Notifier_subdeviceUnregisterEvent; +} + +static void __nvoc_init_funcTable_Subdevice_3(Subdevice *pThis, RmHalspecOwner *pRmhalspecowner) { + RmVariantHal *rmVariantHal = &pRmhalspecowner->rmVariantHal; + const unsigned long rmVariantHal_HalVarIdx = (unsigned long)rmVariantHal->__nvoc_HalVarIdx; + PORT_UNREFERENCED_VARIABLE(pThis); + PORT_UNREFERENCED_VARIABLE(pRmhalspecowner); + PORT_UNREFERENCED_VARIABLE(rmVariantHal); + PORT_UNREFERENCED_VARIABLE(rmVariantHal_HalVarIdx); + + pThis->__subdeviceControlSerialization_Prologue__ = &__nvoc_thunk_RmResource_subdeviceControlSerialization_Prologue; pThis->__subdeviceCanCopy__ = &__nvoc_thunk_RsResource_subdeviceCanCopy; pThis->__subdeviceIsDuplicate__ = &__nvoc_thunk_RsResource_subdeviceIsDuplicate; + pThis->__subdeviceControlSerialization_Epilogue__ = &__nvoc_thunk_RmResource_subdeviceControlSerialization_Epilogue; + pThis->__subdeviceGetNotificationListPtr__ = &__nvoc_thunk_Notifier_subdeviceGetNotificationListPtr; pThis->__subdeviceGetNotificationShare__ = &__nvoc_thunk_Notifier_subdeviceGetNotificationShare; @@ -9054,6 +9935,7 @@ void __nvoc_init_funcTable_Subdevice(Subdevice *pThis, RmHalspecOwner *pRmhalspecowner) { __nvoc_init_funcTable_Subdevice_1(pThis, pRmhalspecowner); __nvoc_init_funcTable_Subdevice_2(pThis, pRmhalspecowner); + __nvoc_init_funcTable_Subdevice_3(pThis, pRmhalspecowner); } void __nvoc_init_GpuResource(GpuResource*); @@ -9078,13 +9960,16 @@ Subdevice *pThis; RmHalspecOwner *pRmhalspecowner; - pThis = portMemAllocNonPaged(sizeof(Subdevice)); - if (pThis == NULL) return NV_ERR_NO_MEMORY; + status = __nvoc_handleObjCreateMemAlloc(createFlags, sizeof(Subdevice), (void**)&pThis, (void**)ppThis); + if (status != NV_OK) + return status; portMemSet(pThis, 0, sizeof(Subdevice)); __nvoc_initRtti(staticCast(pThis, Dynamic), &__nvoc_class_def_Subdevice); + pThis->__nvoc_base_GpuResource.__nvoc_base_RmResource.__nvoc_base_RsResource.__nvoc_base_Object.createFlags = createFlags; + if (pParent != NULL && !(createFlags & NVOC_OBJ_CREATE_FLAGS_PARENT_HALSPEC_ONLY)) { pParentObj = dynamicCast(pParent, Object); @@ -9104,11 +9989,17 @@ if (status != NV_OK) goto __nvoc_objCreate_Subdevice_cleanup; *ppThis = pThis; + return NV_OK; __nvoc_objCreate_Subdevice_cleanup: // do not call destructors here since the constructor already called them - portMemFree(pThis); + if (createFlags & NVOC_OBJ_CREATE_FLAGS_IN_PLACE_CONSTRUCT) + portMemSet(pThis, 0, sizeof(Subdevice)); + else + portMemFree(pThis); + + // coverity[leaked_storage:FALSE] return status; } diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/generated/g_subdevice_nvoc.h nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_subdevice_nvoc.h --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/generated/g_subdevice_nvoc.h 2023-10-25 20:27:20.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_subdevice_nvoc.h 2024-03-05 22:18:46.000000000 +0000 @@ -7,7 +7,7 @@ #endif /* - * SPDX-FileCopyrightText: Copyright (c) 1993-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 1993-2024 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -237,6 +237,8 @@ NV_STATUS (*__subdeviceCtrlCmdFbGetMemAlignment__)(struct Subdevice *, NV2080_CTRL_FB_GET_MEM_ALIGNMENT_PARAMS *); NV_STATUS (*__subdeviceCtrlCmdFbGetHeapReservationSize__)(struct Subdevice *, NV2080_CTRL_INTERNAL_FB_GET_HEAP_RESERVATION_SIZE_PARAMS *); NV_STATUS (*__subdeviceCtrlCmdInternalMemmgrGetVgpuHostRmReservedFb__)(struct Subdevice *, NV2080_CTRL_INTERNAL_MEMMGR_GET_VGPU_CONFIG_HOST_RESERVED_FB_PARAMS *); + NV_STATUS (*__subdeviceCtrlCmdGbGetSemaphoreSurfaceLayout__)(struct Subdevice *, NV2080_CTRL_FB_GET_SEMAPHORE_SURFACE_LAYOUT_PARAMS *); + NV_STATUS (*__subdeviceCtrlCmdInternalMemmgrMemoryTransferWithGsp__)(struct Subdevice *, NV2080_CTRL_INTERNAL_MEMMGR_MEMORY_TRANSFER_WITH_GSP_PARAMS *); NV_STATUS (*__subdeviceCtrlCmdFbGetInfo__)(struct Subdevice *, NV2080_CTRL_FB_GET_INFO_PARAMS *); NV_STATUS (*__subdeviceCtrlCmdFbGetInfoV2__)(struct Subdevice *, NV2080_CTRL_FB_GET_INFO_V2_PARAMS *); NV_STATUS (*__subdeviceCtrlCmdFbGetCarveoutAddressInfo__)(struct Subdevice *, NV2080_CTRL_FB_GET_SYSTEM_CARVEOUT_ADDRESS_SPACE_INFO *); @@ -290,6 +292,7 @@ NV_STATUS (*__subdeviceCtrlCmdInternalFifoPromoteRunlistBuffers__)(struct Subdevice *, NV2080_CTRL_INTERNAL_FIFO_PROMOTE_RUNLIST_BUFFERS_PARAMS *); NV_STATUS (*__subdeviceCtrlCmdInternalFifoGetNumChannels__)(struct Subdevice *, NV2080_CTRL_INTERNAL_FIFO_GET_NUM_CHANNELS_PARAMS *); NV_STATUS (*__subdeviceCtrlCmdFifoGetAllocatedChannels__)(struct Subdevice *, NV2080_CTRL_FIFO_GET_ALLOCATED_CHANNELS_PARAMS *); + NV_STATUS (*__subdeviceCtrlCmdInternalFifoGetNumSecureChannels__)(struct Subdevice *, NV2080_CTRL_INTERNAL_FIFO_GET_NUM_SECURE_CHANNELS_PARAMS *); NV_STATUS (*__subdeviceCtrlCmdKGrGetInfo__)(struct Subdevice *, NV2080_CTRL_GR_GET_INFO_PARAMS *); NV_STATUS (*__subdeviceCtrlCmdKGrGetInfoV2__)(struct Subdevice *, NV2080_CTRL_GR_GET_INFO_V2_PARAMS *); NV_STATUS (*__subdeviceCtrlCmdKGrGetCapsV2__)(struct Subdevice *, NV2080_CTRL_GR_GET_CAPS_V2_PARAMS *); @@ -311,7 +314,7 @@ NV_STATUS (*__subdeviceCtrlCmdKGrGetCtxBufferSize__)(struct Subdevice *, NV2080_CTRL_GR_GET_CTX_BUFFER_SIZE_PARAMS *); NV_STATUS (*__subdeviceCtrlCmdKGrGetCtxBufferInfo__)(struct Subdevice *, NV2080_CTRL_GR_GET_CTX_BUFFER_INFO_PARAMS *); NV_STATUS (*__subdeviceCtrlCmdKGrGetCtxBufferPtes__)(struct Subdevice *, NV2080_CTRL_KGR_GET_CTX_BUFFER_PTES_PARAMS *); - NV_STATUS (*__subdeviceCtrlCmdKGrGetCurrentResidentChannel__)(struct Subdevice *, NV2080_CTRL_CMD_GR_GET_CURRENT_RESIDENT_CHANNEL_PARAMS *); + NV_STATUS (*__subdeviceCtrlCmdKGrGetCurrentResidentChannel__)(struct Subdevice *, NV2080_CTRL_GR_GET_CURRENT_RESIDENT_CHANNEL_PARAMS *); NV_STATUS (*__subdeviceCtrlCmdKGrGetVatAlarmData__)(struct Subdevice *, NV2080_CTRL_GR_GET_VAT_ALARM_DATA_PARAMS *); NV_STATUS (*__subdeviceCtrlCmdKGrGetAttributeBufferSize__)(struct Subdevice *, NV2080_CTRL_GR_GET_ATTRIBUTE_BUFFER_SIZE_PARAMS *); NV_STATUS (*__subdeviceCtrlCmdKGrGfxPoolQuerySize__)(struct Subdevice *, NV2080_CTRL_GR_GFX_POOL_QUERY_SIZE_PARAMS *); @@ -358,6 +361,7 @@ NV_STATUS (*__subdeviceCtrlCmdGpuGetNvfbcSwSessionStats__)(struct Subdevice *, NV2080_CTRL_GPU_GET_NVFBC_SW_SESSION_STATS_PARAMS *); NV_STATUS (*__subdeviceCtrlCmdGpuGetNvfbcSwSessionInfo__)(struct Subdevice *, NV2080_CTRL_GPU_GET_NVFBC_SW_SESSION_INFO_PARAMS *); NV_STATUS (*__subdeviceCtrlCmdGpuSetFabricAddr__)(struct Subdevice *, NV2080_CTRL_GPU_SET_FABRIC_BASE_ADDR_PARAMS *); + NV_STATUS (*__subdeviceCtrlCmdGpuSetEgmGpaFabricAddr__)(struct Subdevice *, NV2080_CTRL_GPU_SET_EGM_GPA_FABRIC_BASE_ADDR_PARAMS *); NV_STATUS (*__subdeviceCtrlCmdGpuSetPower__)(struct Subdevice *, NV2080_CTRL_GPU_SET_POWER_PARAMS *); NV_STATUS (*__subdeviceCtrlCmdGpuGetSdm__)(struct Subdevice *, NV2080_CTRL_GPU_GET_SDM_PARAMS *); NV_STATUS (*__subdeviceCtrlCmdGpuSetSdm__)(struct Subdevice *, NV2080_CTRL_GPU_SET_SDM_PARAMS *); @@ -403,6 +407,7 @@ NV_STATUS (*__subdeviceCtrlCmdGpuGetEngineFaultInfo__)(struct Subdevice *, NV2080_CTRL_GPU_GET_ENGINE_FAULT_INFO_PARAMS *); NV_STATUS (*__subdeviceCtrlCmdGpuGetEngineRunlistPriBase__)(struct Subdevice *, NV2080_CTRL_GPU_GET_ENGINE_RUNLIST_PRI_BASE_PARAMS *); NV_STATUS (*__subdeviceCtrlCmdGpuGetHwEngineId__)(struct Subdevice *, NV2080_CTRL_GPU_GET_HW_ENGINE_ID_PARAMS *); + NV_STATUS (*__subdeviceCtrlCmdGpuGetVmmuSegmentSize__)(struct Subdevice *, NV2080_CTRL_GPU_GET_VMMU_SEGMENT_SIZE_PARAMS *); NV_STATUS (*__subdeviceCtrlCmdGpuGetMaxSupportedPageSize__)(struct Subdevice *, NV2080_CTRL_GPU_GET_MAX_SUPPORTED_PAGE_SIZE_PARAMS *); NV_STATUS (*__subdeviceCtrlCmdGpuHandleVfPriFault__)(struct Subdevice *, NV2080_CTRL_CMD_GPU_HANDLE_VF_PRI_FAULT_PARAMS *); NV_STATUS (*__subdeviceCtrlCmdGpuSetComputePolicyConfig__)(struct Subdevice *, NV2080_CTRL_GPU_SET_COMPUTE_POLICY_CONFIG_PARAMS *); @@ -413,6 +418,8 @@ NV_STATUS (*__subdeviceCtrlCmdGpuGetEngineLoadTimes__)(struct Subdevice *, NV2080_CTRL_GPU_GET_ENGINE_LOAD_TIMES_PARAMS *); NV_STATUS (*__subdeviceCtrlCmdGetP2pCaps__)(struct Subdevice *, NV2080_CTRL_GET_P2P_CAPS_PARAMS *); NV_STATUS (*__subdeviceCtrlCmdGetGpuFabricProbeInfo__)(struct Subdevice *, NV2080_CTRL_CMD_GET_GPU_FABRIC_PROBE_INFO_PARAMS *); + NV_STATUS (*__subdeviceCtrlCmdGpuGetResetStatus__)(struct Subdevice *, NV2080_CTRL_GPU_GET_RESET_STATUS_PARAMS *); + NV_STATUS (*__subdeviceCtrlCmdGpuGetDrainAndResetStatus__)(struct Subdevice *, NV2080_CTRL_GPU_GET_DRAIN_AND_RESET_STATUS_PARAMS *); NV_STATUS (*__subdeviceCtrlCmdEventSetTrigger__)(struct Subdevice *); NV_STATUS (*__subdeviceCtrlCmdEventSetTriggerFifo__)(struct Subdevice *, NV2080_CTRL_EVENT_SET_TRIGGER_FIFO_PARAMS *); NV_STATUS (*__subdeviceCtrlCmdEventSetNotification__)(struct Subdevice *, NV2080_CTRL_EVENT_SET_NOTIFICATION_PARAMS *); @@ -459,6 +466,8 @@ NV_STATUS (*__subdeviceCtrlCmdFlcnGetCtxBufferInfo__)(struct Subdevice *, NV2080_CTRL_FLCN_GET_CTX_BUFFER_INFO_PARAMS *); NV_STATUS (*__subdeviceCtrlCmdFlcnGetCtxBufferSize__)(struct Subdevice *, NV2080_CTRL_FLCN_GET_CTX_BUFFER_SIZE_PARAMS *); NV_STATUS (*__subdeviceCtrlCmdEccGetClientExposedCounters__)(struct Subdevice *, NV2080_CTRL_ECC_GET_CLIENT_EXPOSED_COUNTERS_PARAMS *); + NV_STATUS (*__subdeviceCtrlCmdEccGetEciCounters__)(struct Subdevice *, NV2080_CTRL_ECC_GET_ECI_COUNTERS_PARAMS *); + NV_STATUS (*__subdeviceCtrlCmdEccGetVolatileCounts__)(struct Subdevice *, NV2080_CTRL_ECC_GET_VOLATILE_COUNTS_PARAMS *); NV_STATUS (*__subdeviceCtrlCmdGpuQueryEccConfiguration__)(struct Subdevice *, NV2080_CTRL_GPU_QUERY_ECC_CONFIGURATION_PARAMS *); NV_STATUS (*__subdeviceCtrlCmdGpuSetEccConfiguration__)(struct Subdevice *, NV2080_CTRL_GPU_SET_ECC_CONFIGURATION_PARAMS *); NV_STATUS (*__subdeviceCtrlCmdGpuResetEccErrorStatus__)(struct Subdevice *, NV2080_CTRL_GPU_RESET_ECC_ERROR_STATUS_PARAMS *); @@ -467,6 +476,7 @@ NV_STATUS (*__subdeviceCtrlCmdFlaGetRange__)(struct Subdevice *, NV2080_CTRL_FLA_GET_RANGE_PARAMS *); NV_STATUS (*__subdeviceCtrlCmdFlaGetFabricMemStats__)(struct Subdevice *, NV2080_CTRL_FLA_GET_FABRIC_MEM_STATS_PARAMS *); NV_STATUS (*__subdeviceCtrlCmdGspGetFeatures__)(struct Subdevice *, NV2080_CTRL_GSP_GET_FEATURES_PARAMS *); + NV_STATUS (*__subdeviceCtrlCmdGspGetRmHeapStats__)(struct Subdevice *, NV2080_CTRL_GSP_GET_RM_HEAP_STATS_PARAMS *); NV_STATUS (*__subdeviceCtrlCmdGpuGetActivePartitionIds__)(struct Subdevice *, NV2080_CTRL_GPU_GET_ACTIVE_PARTITION_IDS_PARAMS *); NV_STATUS (*__subdeviceCtrlCmdGpuGetPartitionCapacity__)(struct Subdevice *, NV2080_CTRL_GPU_GET_PARTITION_CAPACITY_PARAMS *); NV_STATUS (*__subdeviceCtrlCmdGpuDescribePartitions__)(struct Subdevice *, NV2080_CTRL_GPU_DESCRIBE_PARTITIONS_PARAMS *); @@ -481,6 +491,7 @@ NV_STATUS (*__subdeviceCtrlCmdInternalStaticKMIGmgrGetComputeInstanceProfiles__)(struct Subdevice *, NV2080_CTRL_INTERNAL_STATIC_MIGMGR_GET_COMPUTE_PROFILES_PARAMS *); NV_STATUS (*__subdeviceCtrlCmdInternalKMIGmgrExportGPUInstance__)(struct Subdevice *, NV2080_CTRL_INTERNAL_KMIGMGR_IMPORT_EXPORT_GPU_INSTANCE_PARAMS *); NV_STATUS (*__subdeviceCtrlCmdInternalKMIGmgrImportGPUInstance__)(struct Subdevice *, NV2080_CTRL_INTERNAL_KMIGMGR_IMPORT_EXPORT_GPU_INSTANCE_PARAMS *); + NV_STATUS (*__subdeviceCtrlCmdInternalKMIGmgrPromoteGpuInstanceMemRange__)(struct Subdevice *, NV2080_CTRL_INTERNAL_KMIGMGR_PROMOTE_GPU_INSTANCE_MEM_RANGE_PARAMS *); NV_STATUS (*__subdeviceCtrlCmdOsUnixGc6BlockerRefCnt__)(struct Subdevice *, NV2080_CTRL_OS_UNIX_GC6_BLOCKER_REFCNT_PARAMS *); NV_STATUS (*__subdeviceCtrlCmdOsUnixAllowDisallowGcoff__)(struct Subdevice *, NV2080_CTRL_OS_UNIX_ALLOW_DISALLOW_GCOFF_PARAMS *); NV_STATUS (*__subdeviceCtrlCmdOsUnixAudioDynamicPower__)(struct Subdevice *, NV2080_CTRL_OS_UNIX_AUDIO_DYNAMIC_POWER_PARAMS *); @@ -493,11 +504,20 @@ NV_STATUS (*__subdeviceCtrlCmdDisplaySetupRgLineIntr__)(struct Subdevice *, NV2080_CTRL_INTERNAL_DISPLAY_SETUP_RG_LINE_INTR_PARAMS *); NV_STATUS (*__subdeviceCtrlCmdDisplaySetImportedImpData__)(struct Subdevice *, NV2080_CTRL_INTERNAL_DISPLAY_SET_IMP_INIT_INFO_PARAMS *); NV_STATUS (*__subdeviceCtrlCmdDisplayGetDisplayMask__)(struct Subdevice *, NV2080_CTRL_INTERNAL_DISPLAY_GET_ACTIVE_DISPLAY_DEVICES_PARAMS *); + NV_STATUS (*__subdeviceCtrlCmdDisplayPinsetsToLockpins__)(struct Subdevice *, NV2080_CTRL_INTERNAL_DISP_PINSETS_TO_LOCKPINS_PARAMS *); + NV_STATUS (*__subdeviceCtrlCmdDisplaySetSliLinkGpioSwControl__)(struct Subdevice *, NV2080_CTRL_INTERNAL_DISP_SET_SLI_LINK_GPIO_SW_CONTROL_PARAMS *); + NV_STATUS (*__subdeviceCtrlCmdInternalGpioProgramDirection__)(struct Subdevice *, NV2080_CTRL_INTERNAL_GPIO_PROGRAM_DIRECTION_PARAMS *); + NV_STATUS (*__subdeviceCtrlCmdInternalGpioProgramOutput__)(struct Subdevice *, NV2080_CTRL_INTERNAL_GPIO_PROGRAM_OUTPUT_PARAMS *); + NV_STATUS (*__subdeviceCtrlCmdInternalGpioReadInput__)(struct Subdevice *, NV2080_CTRL_INTERNAL_GPIO_READ_INPUT_PARAMS *); + NV_STATUS (*__subdeviceCtrlCmdInternalGpioActivateHwFunction__)(struct Subdevice *, NV2080_CTRL_INTERNAL_GPIO_ACTIVATE_HW_FUNCTION_PARAMS *); + NV_STATUS (*__subdeviceCtrlCmdInternalDisplayAcpiSubsytemActivated__)(struct Subdevice *); + NV_STATUS (*__subdeviceCtrlCmdInternalDisplayPreModeSet__)(struct Subdevice *); + NV_STATUS (*__subdeviceCtrlCmdInternalDisplayPostModeSet__)(struct Subdevice *); + NV_STATUS (*__subdeviceCtrlCmdDisplayUnixConsole__)(struct Subdevice *, NV2080_CTRL_CMD_INTERNAL_DISPLAY_UNIX_CONSOLE_PARAMS *); + NV_STATUS (*__subdeviceCtrlCmdDisplayPostVgaRestore__)(struct Subdevice *, NV2080_CTRL_CMD_INTERNAL_DISPLAY_POST_RESTORE_PARAMS *); NV_STATUS (*__subdeviceCtrlCmdMsencGetCaps__)(struct Subdevice *, NV2080_CTRL_INTERNAL_MSENC_GET_CAPS_PARAMS *); NV_STATUS (*__subdeviceCtrlCmdInternalUvmRegisterAccessCntrBuffer__)(struct Subdevice *, NV2080_CTRL_INTERNAL_UVM_REGISTER_ACCESS_CNTR_BUFFER_PARAMS *); - NV_STATUS (*__subdeviceCtrlCmdInternalUvmUnregisterAccessCntrBuffer__)(struct Subdevice *); - NV_STATUS (*__subdeviceCtrlCmdInternalUvmServiceAccessCntrBuffer__)(struct Subdevice *); - NV_STATUS (*__subdeviceCtrlCmdInternalUvmGetAccessCntrBufferSize__)(struct Subdevice *, NV2080_CTRL_INTERNAL_UVM_GET_ACCESS_CNTR_BUFFER_SIZE_PARAMS *); + NV_STATUS (*__subdeviceCtrlCmdInternalUvmUnregisterAccessCntrBuffer__)(struct Subdevice *, NV2080_CTRL_INTERNAL_UVM_UNREGISTER_ACCESS_CNTR_BUFFER_PARAMS *); NV_STATUS (*__subdeviceCtrlCmdInternalGetChipInfo__)(struct Subdevice *, NV2080_CTRL_INTERNAL_GPU_GET_CHIP_INFO_PARAMS *); NV_STATUS (*__subdeviceCtrlCmdInternalGetUserRegisterAccessMap__)(struct Subdevice *, NV2080_CTRL_INTERNAL_GPU_GET_USER_REGISTER_ACCESS_MAP_PARAMS *); NV_STATUS (*__subdeviceCtrlCmdInternalGetDeviceInfoTable__)(struct Subdevice *, NV2080_CTRL_INTERNAL_GET_DEVICE_INFO_TABLE_PARAMS *); @@ -510,11 +530,12 @@ NV_STATUS (*__subdeviceCtrlCmdInternalBusDestroyP2pMailbox__)(struct Subdevice *, NV2080_CTRL_INTERNAL_BUS_DESTROY_P2P_MAILBOX_PARAMS *); NV_STATUS (*__subdeviceCtrlCmdInternalBusCreateC2cPeerMapping__)(struct Subdevice *, NV2080_CTRL_INTERNAL_BUS_CREATE_C2C_PEER_MAPPING_PARAMS *); NV_STATUS (*__subdeviceCtrlCmdInternalBusRemoveC2cPeerMapping__)(struct Subdevice *, NV2080_CTRL_INTERNAL_BUS_REMOVE_C2C_PEER_MAPPING_PARAMS *); + NV_STATUS (*__subdeviceCtrlCmdInternalVmmuGetSpaForGpaEntries__)(struct Subdevice *, NV2080_CTRL_INTERNAL_VMMU_GET_SPA_FOR_GPA_ENTRIES_PARAMS *); NV_STATUS (*__subdeviceCtrlCmdGmmuGetStaticInfo__)(struct Subdevice *, NV2080_CTRL_INTERNAL_GMMU_GET_STATIC_INFO_PARAMS *); NV_STATUS (*__subdeviceCtrlCmdInternalGmmuRegisterFaultBuffer__)(struct Subdevice *, NV2080_CTRL_INTERNAL_GMMU_REGISTER_FAULT_BUFFER_PARAMS *); NV_STATUS (*__subdeviceCtrlCmdInternalGmmuUnregisterFaultBuffer__)(struct Subdevice *); NV_STATUS (*__subdeviceCtrlCmdInternalGmmuRegisterClientShadowFaultBuffer__)(struct Subdevice *, NV2080_CTRL_INTERNAL_GMMU_REGISTER_CLIENT_SHADOW_FAULT_BUFFER_PARAMS *); - NV_STATUS (*__subdeviceCtrlCmdInternalGmmuUnregisterClientShadowFaultBuffer__)(struct Subdevice *); + NV_STATUS (*__subdeviceCtrlCmdInternalGmmuUnregisterClientShadowFaultBuffer__)(struct Subdevice *, NV2080_CTRL_INTERNAL_GMMU_UNREGISTER_CLIENT_SHADOW_FAULT_BUFFER_PARAMS *); NV_STATUS (*__subdeviceCtrlCmdInternalGmmuCopyReservedSplitGVASpacePdesServer__)(struct Subdevice *, NV2080_CTRL_INTERNAL_GMMU_COPY_RESERVED_SPLIT_GVASPACE_PDES_TO_SERVER_PARAMS *); NV_STATUS (*__subdeviceCtrlCmdCeGetPhysicalCaps__)(struct Subdevice *, NV2080_CTRL_CE_GET_CAPS_V2_PARAMS *); NV_STATUS (*__subdeviceCtrlCmdCeGetAllPhysicalCaps__)(struct Subdevice *, NV2080_CTRL_CE_GET_ALL_CAPS_PARAMS *); @@ -534,14 +555,17 @@ NV_STATUS (*__subdeviceCtrlCmdInternalPerfPerfmonClientReservationSet__)(struct Subdevice *, NV2080_CTRL_INTERNAL_PERF_PERFMON_CLIENT_RESERVATION_SET_PARAMS *); NV_STATUS (*__subdeviceCtrlCmdInternalPerfCfControllerSetMaxVGpuVMCount__)(struct Subdevice *, NV2080_CTRL_INTERNAL_PERF_CF_CONTROLLERS_SET_MAX_VGPU_VM_COUNT_PARAMS *); NV_STATUS (*__subdeviceCtrlCmdInternalPerfGetAuxPowerState__)(struct Subdevice *, NV2080_CTRL_INTERNAL_PERF_GET_AUX_POWER_STATE_PARAMS *); + NV_STATUS (*__subdeviceCtrlCmdInternalGc6EntryPrerequisite__)(struct Subdevice *, NV2080_CTRL_INTERNAL_GC6_ENTRY_PREREQUISITE_PARAMS *); NV_STATUS (*__subdeviceCtrlCmdBifGetStaticInfo__)(struct Subdevice *, NV2080_CTRL_INTERNAL_BIF_GET_STATIC_INFO_PARAMS *); NV_STATUS (*__subdeviceCtrlCmdBifGetAspmL1Flags__)(struct Subdevice *, NV2080_CTRL_INTERNAL_BIF_GET_ASPM_L1_FLAGS_PARAMS *); NV_STATUS (*__subdeviceCtrlCmdBifSetPcieRo__)(struct Subdevice *, NV2080_CTRL_INTERNAL_BIF_SET_PCIE_RO_PARAMS *); + NV_STATUS (*__subdeviceCtrlCmdBifDisableSystemMemoryAccess__)(struct Subdevice *, NV2080_CTRL_INTERNAL_BIF_DISABLE_SYSTEM_MEMORY_ACCESS_PARAMS *); NV_STATUS (*__subdeviceCtrlCmdHshubPeerConnConfig__)(struct Subdevice *, NV2080_CTRL_INTERNAL_HSHUB_PEER_CONN_CONFIG_PARAMS *); NV_STATUS (*__subdeviceCtrlCmdHshubFirstLinkPeerId__)(struct Subdevice *, NV2080_CTRL_INTERNAL_HSHUB_FIRST_LINK_PEER_ID_PARAMS *); NV_STATUS (*__subdeviceCtrlCmdHshubGetHshubIdForLinks__)(struct Subdevice *, NV2080_CTRL_INTERNAL_HSHUB_GET_HSHUB_ID_FOR_LINKS_PARAMS *); NV_STATUS (*__subdeviceCtrlCmdHshubGetNumUnits__)(struct Subdevice *, NV2080_CTRL_INTERNAL_HSHUB_GET_NUM_UNITS_PARAMS *); NV_STATUS (*__subdeviceCtrlCmdHshubNextHshubId__)(struct Subdevice *, NV2080_CTRL_INTERNAL_HSHUB_NEXT_HSHUB_ID_PARAMS *); + NV_STATUS (*__subdeviceCtrlCmdHshubEgmConfig__)(struct Subdevice *, NV2080_CTRL_INTERNAL_HSHUB_EGM_CONFIG_PARAMS *); NV_STATUS (*__subdeviceCtrlCmdInternalNvlinkEnableComputePeerAddr__)(struct Subdevice *); NV_STATUS (*__subdeviceCtrlCmdInternalNvlinkGetSetNvswitchFabricAddr__)(struct Subdevice *, NV2080_CTRL_INTERNAL_NVLINK_GET_SET_NVSWITCH_FABRIC_ADDR_PARAMS *); NV_STATUS (*__subdeviceCtrlCmdInternalNvlinkGetNumActiveLinksPerIoctrl__)(struct Subdevice *, NV2080_CTRL_INTERNAL_NVLINK_GET_NUM_ACTIVE_LINK_PER_IOCTRL_PARAMS *); @@ -550,6 +574,8 @@ NV_STATUS (*__subdeviceCtrlCmdInternalRemoveP2pCaps__)(struct Subdevice *, NV2080_CTRL_INTERNAL_REMOVE_P2P_CAPS_PARAMS *); NV_STATUS (*__subdeviceCtrlCmdInternalGetPcieP2pCaps__)(struct Subdevice *, NV2080_CTRL_INTERNAL_GET_PCIE_P2P_CAPS_PARAMS *); NV_STATUS (*__subdeviceCtrlCmdInternalGetCoherentFbApertureSize__)(struct Subdevice *, NV2080_CTRL_INTERNAL_GET_COHERENT_FB_APERTURE_SIZE_PARAMS *); + NV_STATUS (*__subdeviceCtrlCmdInternalGetLocalAtsConfig__)(struct Subdevice *, NV2080_CTRL_INTERNAL_MEMSYS_GET_LOCAL_ATS_CONFIG_PARAMS *); + NV_STATUS (*__subdeviceCtrlCmdInternalSetPeerAtsConfig__)(struct Subdevice *, NV2080_CTRL_INTERNAL_MEMSYS_SET_PEER_ATS_CONFIG_PARAMS *); NV_STATUS (*__subdeviceCtrlCmdInternalInitGpuIntr__)(struct Subdevice *, NV2080_CTRL_INTERNAL_GSYNC_ATTACH_AND_INIT_PARAMS *); NV_STATUS (*__subdeviceCtrlCmdInternalGsyncOptimizeTiming__)(struct Subdevice *, NV2080_CTRL_INTERNAL_GSYNC_OPTIMIZE_TIMING_PARAMETERS_PARAMS *); NV_STATUS (*__subdeviceCtrlCmdInternalGsyncGetDisplayIds__)(struct Subdevice *, NV2080_CTRL_INTERNAL_GSYNC_GET_DISPLAY_IDS_PARAMS *); @@ -560,7 +586,26 @@ NV_STATUS (*__subdeviceCtrlCmdInternalFbsrInit__)(struct Subdevice *, NV2080_CTRL_INTERNAL_FBSR_INIT_PARAMS *); NV_STATUS (*__subdeviceCtrlCmdInternalFbsrSendRegionInfo__)(struct Subdevice *, NV2080_CTRL_INTERNAL_FBSR_SEND_REGION_INFO_PARAMS *); NV_STATUS (*__subdeviceCtrlCmdInternalPostInitBrightcStateLoad__)(struct Subdevice *, NV2080_CTRL_INTERNAL_INIT_BRIGHTC_STATE_LOAD_PARAMS *); + NV_STATUS (*__subdeviceCtrlCmdInternalSetStaticEdidData__)(struct Subdevice *, NV2080_CTRL_CMD_INTERNAL_SET_STATIC_EDID_DATA_PARAMS *); + NV_STATUS (*__subdeviceCtrlCmdInternalSmbpbiPfmReqHndlrCapUpdate__)(struct Subdevice *, NV2080_CTRL_INTERNAL_SMBPBI_PFM_REQ_HNDLR_CAP_UPDATE_PARAMS *); + NV_STATUS (*__subdeviceCtrlCmdInternalPmgrPfmReqHndlrStateLoadSync__)(struct Subdevice *, NV2080_CTRL_INTERNAL_PFM_REQ_HNDLR_STATE_SYNC_PARAMS *); + NV_STATUS (*__subdeviceCtrlCmdInternalThermPfmReqHndlrStateInitSync__)(struct Subdevice *, NV2080_CTRL_INTERNAL_PFM_REQ_HNDLR_STATE_SYNC_PARAMS *); + NV_STATUS (*__subdeviceCtrlCmdInternalPerfPfmReqHndlrGetPm1State__)(struct Subdevice *, NV2080_CTRL_CMD_INTERNAL_PERF_PFM_REQ_HNDLR_GET_PM1_STATE_PARAMS *); + NV_STATUS (*__subdeviceCtrlCmdInternalPerfPfmReqHndlrSetPm1State__)(struct Subdevice *, NV2080_CTRL_CMD_INTERNAL_PERF_PFM_REQ_HNDLR_SET_PM1_STATE_PARAMS *); + NV_STATUS (*__subdeviceCtrlCmdInternalPmgrPfmReqHndlrUpdateEdppLimit__)(struct Subdevice *, NV2080_CTRL_CMD_INTERNAL_PMGR_PFM_REQ_HNDLR_UPDATE_EDPP_LIMIT_PARAMS *); + NV_STATUS (*__subdeviceCtrlCmdInternalPmgrPfmReqHndlrGetEdppLimitInfo__)(struct Subdevice *, NV2080_CTRL_CMD_INTERNAL_PMGR_PFM_REQ_HNDLR_GET_EDPP_LIMIT_INFO_PARAMS *); + NV_STATUS (*__subdeviceCtrlCmdInternalThermPfmReqHndlrUpdateTgpuLimit__)(struct Subdevice *, NV2080_CTRL_CMD_INTERNAL_THERM_PFM_REQ_HNDLR_UPDATE_TGPU_LIMIT_PARAMS *); + NV_STATUS (*__subdeviceCtrlCmdInternalPmgrPfmReqHndlrConfigureTgpMode__)(struct Subdevice *, NV2080_CTRL_CMD_INTERNAL_PMGR_PFM_REQ_HNDLR_CONFIGURE_TGP_MODE_PARAMS *); + NV_STATUS (*__subdeviceCtrlCmdInternalPmgrPfmReqHndlrConfigureTurboV2__)(struct Subdevice *, NV2080_CTRL_CMD_INTERNAL_PMGR_PFM_REQ_HNDLR_CONFIGURE_TURBO_V2_PARAMS *); + NV_STATUS (*__subdeviceCtrlCmdInternalPerfPfmReqHndlrGetVpstateInfo__)(struct Subdevice *, NV2080_CTRL_CMD_INTERNAL_PERF_PFM_REQ_HNDLR_GET_VPSTATE_INFO_PARAMS *); + NV_STATUS (*__subdeviceCtrlCmdInternalPerfPfmReqHndlrGetVpstateMapping__)(struct Subdevice *, NV2080_CTRL_CMD_INTERNAL_PERF_PFM_REQ_HNDLR_GET_VPSTATE_MAPPING_PARAMS *); + NV_STATUS (*__subdeviceCtrlCmdInternalPerfPfmReqHndlrSetVpstate__)(struct Subdevice *, NV2080_CTRL_CMD_INTERNAL_PERF_PFM_REQ_HNDLR_SET_VPSTATE_PARAMS *); NV_STATUS (*__subdeviceCtrlCmdInternalPmgrUnsetDynamicBoostLimit__)(struct Subdevice *); + NV_STATUS (*__subdeviceCtrlCmdInternalDetectHsVideoBridge__)(struct Subdevice *); + NV_STATUS (*__subdeviceCtrlCmdInternalConfComputeGetStaticInfo__)(struct Subdevice *, NV2080_CTRL_INTERNAL_CONF_COMPUTE_GET_STATIC_INFO_PARAMS *); + NV_STATUS (*__subdeviceCtrlCmdInternalConfComputeEncryptionControl__)(struct Subdevice *, NV2080_CTRL_CMD_INTERNAL_CONF_COMPUTE_ENCRYPTION_CONTROL_PARAMS *); + NV_STATUS (*__subdeviceCtrlCmdInternalConfComputeDeriveSwlKeys__)(struct Subdevice *, NV2080_CTRL_INTERNAL_CONF_COMPUTE_DERIVE_SWL_KEYS_PARAMS *); + NV_STATUS (*__subdeviceCtrlCmdInternalConfComputeDeriveLceKeys__)(struct Subdevice *, NV2080_CTRL_INTERNAL_CONF_COMPUTE_DERIVE_LCE_KEYS_PARAMS *); NV_STATUS (*__subdeviceCtrlCmdVgpuMgrInternalBootloadGspVgpuPluginTask__)(struct Subdevice *, NV2080_CTRL_VGPU_MGR_INTERNAL_BOOTLOAD_GSP_VGPU_PLUGIN_TASK_PARAMS *); NV_STATUS (*__subdeviceCtrlCmdVgpuMgrInternalShutdownGspVgpuPluginTask__)(struct Subdevice *, NV2080_CTRL_VGPU_MGR_INTERNAL_SHUTDOWN_GSP_VGPU_PLUGIN_TASK_PARAMS *); NV_STATUS (*__subdeviceCtrlCmdVgpuMgrInternalPgpuAddVgpuType__)(struct Subdevice *, NV2080_CTRL_VGPU_MGR_INTERNAL_PGPU_ADD_VGPU_TYPE_PARAMS *); @@ -576,10 +621,11 @@ NV_STATUS (*__subdeviceCtrlCmdCcuMap__)(struct Subdevice *, NV2080_CTRL_INTERNAL_CCU_MAP_INFO_PARAMS *); NV_STATUS (*__subdeviceCtrlCmdCcuUnmap__)(struct Subdevice *, NV2080_CTRL_INTERNAL_CCU_UNMAP_INFO_PARAMS *); NV_STATUS (*__subdeviceCtrlCmdCcuSetStreamState__)(struct Subdevice *, NV2080_CTRL_INTERNAL_CCU_STREAM_STATE_PARAMS *); + NV_STATUS (*__subdeviceCtrlCmdSpdmPartition__)(struct Subdevice *, NV2080_CTRL_INTERNAL_SPDM_PARTITION_PARAMS *); NvBool (*__subdeviceShareCallback__)(struct Subdevice *, struct RsClient *, struct RsResourceRef *, RS_SHARE_POLICY *); - NV_STATUS (*__subdeviceMapTo__)(struct Subdevice *, RS_RES_MAP_TO_PARAMS *); - NV_STATUS (*__subdeviceGetOrAllocNotifShare__)(struct Subdevice *, NvHandle, NvHandle, struct NotifShare **); NV_STATUS (*__subdeviceCheckMemInterUnmap__)(struct Subdevice *, NvBool); + NV_STATUS (*__subdeviceGetOrAllocNotifShare__)(struct Subdevice *, NvHandle, NvHandle, struct NotifShare **); + NV_STATUS (*__subdeviceMapTo__)(struct Subdevice *, RS_RES_MAP_TO_PARAMS *); NV_STATUS (*__subdeviceGetMapAddrSpace__)(struct Subdevice *, struct CALL_CONTEXT *, NvU32, NV_ADDRESS_SPACE *); void (*__subdeviceSetNotificationShare__)(struct Subdevice *, struct NotifShare *); NvU32 (*__subdeviceGetRefCount__)(struct Subdevice *); @@ -595,8 +641,10 @@ NV_STATUS (*__subdeviceGetMemInterMapParams__)(struct Subdevice *, RMRES_MEM_INTER_MAP_PARAMS *); NV_STATUS (*__subdeviceGetMemoryMappingDescriptor__)(struct Subdevice *, struct MEMORY_DESCRIPTOR **); NV_STATUS (*__subdeviceUnregisterEvent__)(struct Subdevice *, NvHandle, NvHandle, NvHandle, NvHandle); + NV_STATUS (*__subdeviceControlSerialization_Prologue__)(struct Subdevice *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); NvBool (*__subdeviceCanCopy__)(struct Subdevice *); NV_STATUS (*__subdeviceIsDuplicate__)(struct Subdevice *, NvHandle, NvBool *); + void (*__subdeviceControlSerialization_Epilogue__)(struct Subdevice *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); PEVENTNOTIFICATION *(*__subdeviceGetNotificationListPtr__)(struct Subdevice *); struct NotifShare *(*__subdeviceGetNotificationShare__)(struct Subdevice *); NV_STATUS (*__subdeviceMap__)(struct Subdevice *, struct CALL_CONTEXT *, struct RS_CPU_MAP_PARAMS *, struct RsCpuMapping *); @@ -606,7 +654,7 @@ struct Device *pDevice; NvBool bMaxGrTickFreqRequested; NvU64 P2PfbMappedBytes; - NvU32 notifyActions[179]; + NvU32 notifyActions[181]; NvHandle hNotifierMemory; struct Memory *pNotifierMemory; NvHandle hSemMemory; @@ -629,6 +677,7 @@ NvBool bSchedPolicySet; NvBool bGcoffDisallowed; NvBool bUpdateTGP; + NvBool bVFRefCntIncRequested; }; #ifndef __NVOC_CLASS_Subdevice_TYPEDEF__ @@ -701,6 +750,7 @@ #define subdeviceCtrlCmdBusGetUphyDlnCfgSpace(pSubdevice, pParams) subdeviceCtrlCmdBusGetUphyDlnCfgSpace_DISPATCH(pSubdevice, pParams) #define subdeviceCtrlCmdBusGetEomStatus(pSubdevice, pParams) subdeviceCtrlCmdBusGetEomStatus_DISPATCH(pSubdevice, pParams) #define subdeviceCtrlCmdBusGetPcieReqAtomicsCaps(pSubdevice, pParams) subdeviceCtrlCmdBusGetPcieReqAtomicsCaps_DISPATCH(pSubdevice, pParams) +#define subdeviceCtrlCmdBusGetPcieReqAtomicsCaps_HAL(pSubdevice, pParams) subdeviceCtrlCmdBusGetPcieReqAtomicsCaps_DISPATCH(pSubdevice, pParams) #define subdeviceCtrlCmdBusGetPcieSupportedGpuAtomics(pSubdevice, pParams) subdeviceCtrlCmdBusGetPcieSupportedGpuAtomics_DISPATCH(pSubdevice, pParams) #define subdeviceCtrlCmdBusGetC2CInfo(pSubdevice, pParams) subdeviceCtrlCmdBusGetC2CInfo_DISPATCH(pSubdevice, pParams) #define subdeviceCtrlCmdBusGetC2CErrorInfo(pSubdevice, pParams) subdeviceCtrlCmdBusGetC2CErrorInfo_DISPATCH(pSubdevice, pParams) @@ -784,6 +834,9 @@ #define subdeviceCtrlCmdFbGetMemAlignment(pSubdevice, pParams) subdeviceCtrlCmdFbGetMemAlignment_DISPATCH(pSubdevice, pParams) #define subdeviceCtrlCmdFbGetHeapReservationSize(pSubdevice, pParams) subdeviceCtrlCmdFbGetHeapReservationSize_DISPATCH(pSubdevice, pParams) #define subdeviceCtrlCmdInternalMemmgrGetVgpuHostRmReservedFb(pSubdevice, pParams) subdeviceCtrlCmdInternalMemmgrGetVgpuHostRmReservedFb_DISPATCH(pSubdevice, pParams) +#define subdeviceCtrlCmdGbGetSemaphoreSurfaceLayout(pSubdevice, pParams) subdeviceCtrlCmdGbGetSemaphoreSurfaceLayout_DISPATCH(pSubdevice, pParams) +#define subdeviceCtrlCmdInternalMemmgrMemoryTransferWithGsp(pSubdevice, pParams) subdeviceCtrlCmdInternalMemmgrMemoryTransferWithGsp_DISPATCH(pSubdevice, pParams) +#define subdeviceCtrlCmdInternalMemmgrMemoryTransferWithGsp_HAL(pSubdevice, pParams) subdeviceCtrlCmdInternalMemmgrMemoryTransferWithGsp_DISPATCH(pSubdevice, pParams) #define subdeviceCtrlCmdFbGetInfo(pSubdevice, pFbInfoParams) subdeviceCtrlCmdFbGetInfo_DISPATCH(pSubdevice, pFbInfoParams) #define subdeviceCtrlCmdFbGetInfoV2(pSubdevice, pFbInfoParams) subdeviceCtrlCmdFbGetInfoV2_DISPATCH(pSubdevice, pFbInfoParams) #define subdeviceCtrlCmdFbGetCarveoutAddressInfo(pSubdevice, pParams) subdeviceCtrlCmdFbGetCarveoutAddressInfo_DISPATCH(pSubdevice, pParams) @@ -837,6 +890,7 @@ #define subdeviceCtrlCmdInternalFifoPromoteRunlistBuffers(pSubdevice, pParams) subdeviceCtrlCmdInternalFifoPromoteRunlistBuffers_DISPATCH(pSubdevice, pParams) #define subdeviceCtrlCmdInternalFifoGetNumChannels(pSubdevice, pNumChannelsParams) subdeviceCtrlCmdInternalFifoGetNumChannels_DISPATCH(pSubdevice, pNumChannelsParams) #define subdeviceCtrlCmdFifoGetAllocatedChannels(pSubdevice, pParams) subdeviceCtrlCmdFifoGetAllocatedChannels_DISPATCH(pSubdevice, pParams) +#define subdeviceCtrlCmdInternalFifoGetNumSecureChannels(pSubdevice, pNumSecureChannelsParams) subdeviceCtrlCmdInternalFifoGetNumSecureChannels_DISPATCH(pSubdevice, pNumSecureChannelsParams) #define subdeviceCtrlCmdKGrGetInfo(pSubdevice, pParams) subdeviceCtrlCmdKGrGetInfo_DISPATCH(pSubdevice, pParams) #define subdeviceCtrlCmdKGrGetInfoV2(pSubdevice, pParams) subdeviceCtrlCmdKGrGetInfoV2_DISPATCH(pSubdevice, pParams) #define subdeviceCtrlCmdKGrGetCapsV2(pSubdevice, pGrCapsParams) subdeviceCtrlCmdKGrGetCapsV2_DISPATCH(pSubdevice, pGrCapsParams) @@ -905,6 +959,7 @@ #define subdeviceCtrlCmdGpuGetNvfbcSwSessionStats(pSubdevice, params) subdeviceCtrlCmdGpuGetNvfbcSwSessionStats_DISPATCH(pSubdevice, params) #define subdeviceCtrlCmdGpuGetNvfbcSwSessionInfo(pSubdevice, params) subdeviceCtrlCmdGpuGetNvfbcSwSessionInfo_DISPATCH(pSubdevice, params) #define subdeviceCtrlCmdGpuSetFabricAddr(pSubdevice, pParams) subdeviceCtrlCmdGpuSetFabricAddr_DISPATCH(pSubdevice, pParams) +#define subdeviceCtrlCmdGpuSetEgmGpaFabricAddr(pSubdevice, pParams) subdeviceCtrlCmdGpuSetEgmGpaFabricAddr_DISPATCH(pSubdevice, pParams) #define subdeviceCtrlCmdGpuSetPower(pSubdevice, pSetPowerParams) subdeviceCtrlCmdGpuSetPower_DISPATCH(pSubdevice, pSetPowerParams) #define subdeviceCtrlCmdGpuGetSdm(pSubdevice, pSdmParams) subdeviceCtrlCmdGpuGetSdm_DISPATCH(pSubdevice, pSdmParams) #define subdeviceCtrlCmdGpuSetSdm(pSubdevice, pSdmParams) subdeviceCtrlCmdGpuSetSdm_DISPATCH(pSubdevice, pSdmParams) @@ -950,6 +1005,7 @@ #define subdeviceCtrlCmdGpuGetEngineFaultInfo(pSubdevice, pParams) subdeviceCtrlCmdGpuGetEngineFaultInfo_DISPATCH(pSubdevice, pParams) #define subdeviceCtrlCmdGpuGetEngineRunlistPriBase(pSubdevice, pParams) subdeviceCtrlCmdGpuGetEngineRunlistPriBase_DISPATCH(pSubdevice, pParams) #define subdeviceCtrlCmdGpuGetHwEngineId(pSubdevice, pParams) subdeviceCtrlCmdGpuGetHwEngineId_DISPATCH(pSubdevice, pParams) +#define subdeviceCtrlCmdGpuGetVmmuSegmentSize(pSubdevice, pParams) subdeviceCtrlCmdGpuGetVmmuSegmentSize_DISPATCH(pSubdevice, pParams) #define subdeviceCtrlCmdGpuGetMaxSupportedPageSize(pSubdevice, pParams) subdeviceCtrlCmdGpuGetMaxSupportedPageSize_DISPATCH(pSubdevice, pParams) #define subdeviceCtrlCmdGpuHandleVfPriFault(pSubdevice, pParams) subdeviceCtrlCmdGpuHandleVfPriFault_DISPATCH(pSubdevice, pParams) #define subdeviceCtrlCmdGpuSetComputePolicyConfig(pSubdevice, pParams) subdeviceCtrlCmdGpuSetComputePolicyConfig_DISPATCH(pSubdevice, pParams) @@ -960,6 +1016,8 @@ #define subdeviceCtrlCmdGpuGetEngineLoadTimes(pSubdevice, pParams) subdeviceCtrlCmdGpuGetEngineLoadTimes_DISPATCH(pSubdevice, pParams) #define subdeviceCtrlCmdGetP2pCaps(pSubdevice, pParams) subdeviceCtrlCmdGetP2pCaps_DISPATCH(pSubdevice, pParams) #define subdeviceCtrlCmdGetGpuFabricProbeInfo(pSubdevice, pParams) subdeviceCtrlCmdGetGpuFabricProbeInfo_DISPATCH(pSubdevice, pParams) +#define subdeviceCtrlCmdGpuGetResetStatus(pSubdevice, pParams) subdeviceCtrlCmdGpuGetResetStatus_DISPATCH(pSubdevice, pParams) +#define subdeviceCtrlCmdGpuGetDrainAndResetStatus(pSubdevice, pParams) subdeviceCtrlCmdGpuGetDrainAndResetStatus_DISPATCH(pSubdevice, pParams) #define subdeviceCtrlCmdEventSetTrigger(pSubdevice) subdeviceCtrlCmdEventSetTrigger_DISPATCH(pSubdevice) #define subdeviceCtrlCmdEventSetTriggerFifo(pSubdevice, pTriggerFifoParams) subdeviceCtrlCmdEventSetTriggerFifo_DISPATCH(pSubdevice, pTriggerFifoParams) #define subdeviceCtrlCmdEventSetNotification(pSubdevice, pSetEventParams) subdeviceCtrlCmdEventSetNotification_DISPATCH(pSubdevice, pSetEventParams) @@ -1006,6 +1064,8 @@ #define subdeviceCtrlCmdFlcnGetCtxBufferInfo(pSubdevice, pParams) subdeviceCtrlCmdFlcnGetCtxBufferInfo_DISPATCH(pSubdevice, pParams) #define subdeviceCtrlCmdFlcnGetCtxBufferSize(pSubdevice, pParams) subdeviceCtrlCmdFlcnGetCtxBufferSize_DISPATCH(pSubdevice, pParams) #define subdeviceCtrlCmdEccGetClientExposedCounters(pSubdevice, pParams) subdeviceCtrlCmdEccGetClientExposedCounters_DISPATCH(pSubdevice, pParams) +#define subdeviceCtrlCmdEccGetEciCounters(pSubdevice, pParams) subdeviceCtrlCmdEccGetEciCounters_DISPATCH(pSubdevice, pParams) +#define subdeviceCtrlCmdEccGetVolatileCounts(pSubdevice, pParams) subdeviceCtrlCmdEccGetVolatileCounts_DISPATCH(pSubdevice, pParams) #define subdeviceCtrlCmdGpuQueryEccConfiguration(pSubdevice, pConfig) subdeviceCtrlCmdGpuQueryEccConfiguration_DISPATCH(pSubdevice, pConfig) #define subdeviceCtrlCmdGpuSetEccConfiguration(pSubdevice, pConfig) subdeviceCtrlCmdGpuSetEccConfiguration_DISPATCH(pSubdevice, pConfig) #define subdeviceCtrlCmdGpuResetEccErrorStatus(pSubdevice, pParams) subdeviceCtrlCmdGpuResetEccErrorStatus_DISPATCH(pSubdevice, pParams) @@ -1014,6 +1074,7 @@ #define subdeviceCtrlCmdFlaGetRange(pSubdevice, pParams) subdeviceCtrlCmdFlaGetRange_DISPATCH(pSubdevice, pParams) #define subdeviceCtrlCmdFlaGetFabricMemStats(pSubdevice, pParams) subdeviceCtrlCmdFlaGetFabricMemStats_DISPATCH(pSubdevice, pParams) #define subdeviceCtrlCmdGspGetFeatures(pSubdevice, pGspFeaturesParams) subdeviceCtrlCmdGspGetFeatures_DISPATCH(pSubdevice, pGspFeaturesParams) +#define subdeviceCtrlCmdGspGetRmHeapStats(pSubdevice, pGspRmHeapStatsParams) subdeviceCtrlCmdGspGetRmHeapStats_DISPATCH(pSubdevice, pGspRmHeapStatsParams) #define subdeviceCtrlCmdGpuGetActivePartitionIds(pSubdevice, pParams) subdeviceCtrlCmdGpuGetActivePartitionIds_DISPATCH(pSubdevice, pParams) #define subdeviceCtrlCmdGpuGetPartitionCapacity(pSubdevice, pParams) subdeviceCtrlCmdGpuGetPartitionCapacity_DISPATCH(pSubdevice, pParams) #define subdeviceCtrlCmdGpuDescribePartitions(pSubdevice, pParams) subdeviceCtrlCmdGpuDescribePartitions_DISPATCH(pSubdevice, pParams) @@ -1028,6 +1089,7 @@ #define subdeviceCtrlCmdInternalStaticKMIGmgrGetComputeInstanceProfiles(pSubdevice, pParams) subdeviceCtrlCmdInternalStaticKMIGmgrGetComputeInstanceProfiles_DISPATCH(pSubdevice, pParams) #define subdeviceCtrlCmdInternalKMIGmgrExportGPUInstance(pSubdevice, pParams) subdeviceCtrlCmdInternalKMIGmgrExportGPUInstance_DISPATCH(pSubdevice, pParams) #define subdeviceCtrlCmdInternalKMIGmgrImportGPUInstance(pSubdevice, pParams) subdeviceCtrlCmdInternalKMIGmgrImportGPUInstance_DISPATCH(pSubdevice, pParams) +#define subdeviceCtrlCmdInternalKMIGmgrPromoteGpuInstanceMemRange(pSubdevice, pParams) subdeviceCtrlCmdInternalKMIGmgrPromoteGpuInstanceMemRange_DISPATCH(pSubdevice, pParams) #define subdeviceCtrlCmdOsUnixGc6BlockerRefCnt(pSubdevice, pParams) subdeviceCtrlCmdOsUnixGc6BlockerRefCnt_DISPATCH(pSubdevice, pParams) #define subdeviceCtrlCmdOsUnixAllowDisallowGcoff(pSubdevice, pParams) subdeviceCtrlCmdOsUnixAllowDisallowGcoff_DISPATCH(pSubdevice, pParams) #define subdeviceCtrlCmdOsUnixAudioDynamicPower(pSubdevice, pParams) subdeviceCtrlCmdOsUnixAudioDynamicPower_DISPATCH(pSubdevice, pParams) @@ -1040,11 +1102,20 @@ #define subdeviceCtrlCmdDisplaySetupRgLineIntr(pSubdevice, pParams) subdeviceCtrlCmdDisplaySetupRgLineIntr_DISPATCH(pSubdevice, pParams) #define subdeviceCtrlCmdDisplaySetImportedImpData(pSubdevice, pParams) subdeviceCtrlCmdDisplaySetImportedImpData_DISPATCH(pSubdevice, pParams) #define subdeviceCtrlCmdDisplayGetDisplayMask(pSubdevice, pParams) subdeviceCtrlCmdDisplayGetDisplayMask_DISPATCH(pSubdevice, pParams) +#define subdeviceCtrlCmdDisplayPinsetsToLockpins(pSubdevice, pParams) subdeviceCtrlCmdDisplayPinsetsToLockpins_DISPATCH(pSubdevice, pParams) +#define subdeviceCtrlCmdDisplaySetSliLinkGpioSwControl(pSubdevice, pParams) subdeviceCtrlCmdDisplaySetSliLinkGpioSwControl_DISPATCH(pSubdevice, pParams) +#define subdeviceCtrlCmdInternalGpioProgramDirection(pSubdevice, pParams) subdeviceCtrlCmdInternalGpioProgramDirection_DISPATCH(pSubdevice, pParams) +#define subdeviceCtrlCmdInternalGpioProgramOutput(pSubdevice, pParams) subdeviceCtrlCmdInternalGpioProgramOutput_DISPATCH(pSubdevice, pParams) +#define subdeviceCtrlCmdInternalGpioReadInput(pSubdevice, pParams) subdeviceCtrlCmdInternalGpioReadInput_DISPATCH(pSubdevice, pParams) +#define subdeviceCtrlCmdInternalGpioActivateHwFunction(pSubdevice, pParams) subdeviceCtrlCmdInternalGpioActivateHwFunction_DISPATCH(pSubdevice, pParams) +#define subdeviceCtrlCmdInternalDisplayAcpiSubsytemActivated(pSubdevice) subdeviceCtrlCmdInternalDisplayAcpiSubsytemActivated_DISPATCH(pSubdevice) +#define subdeviceCtrlCmdInternalDisplayPreModeSet(pSubdevice) subdeviceCtrlCmdInternalDisplayPreModeSet_DISPATCH(pSubdevice) +#define subdeviceCtrlCmdInternalDisplayPostModeSet(pSubdevice) subdeviceCtrlCmdInternalDisplayPostModeSet_DISPATCH(pSubdevice) +#define subdeviceCtrlCmdDisplayUnixConsole(pSubdevice, pParams) subdeviceCtrlCmdDisplayUnixConsole_DISPATCH(pSubdevice, pParams) +#define subdeviceCtrlCmdDisplayPostVgaRestore(pSubdevice, pParams) subdeviceCtrlCmdDisplayPostVgaRestore_DISPATCH(pSubdevice, pParams) #define subdeviceCtrlCmdMsencGetCaps(pSubdevice, pParams) subdeviceCtrlCmdMsencGetCaps_DISPATCH(pSubdevice, pParams) #define subdeviceCtrlCmdInternalUvmRegisterAccessCntrBuffer(pSubdevice, pParams) subdeviceCtrlCmdInternalUvmRegisterAccessCntrBuffer_DISPATCH(pSubdevice, pParams) -#define subdeviceCtrlCmdInternalUvmUnregisterAccessCntrBuffer(pSubdevice) subdeviceCtrlCmdInternalUvmUnregisterAccessCntrBuffer_DISPATCH(pSubdevice) -#define subdeviceCtrlCmdInternalUvmServiceAccessCntrBuffer(pSubdevice) subdeviceCtrlCmdInternalUvmServiceAccessCntrBuffer_DISPATCH(pSubdevice) -#define subdeviceCtrlCmdInternalUvmGetAccessCntrBufferSize(pSubdevice, pParams) subdeviceCtrlCmdInternalUvmGetAccessCntrBufferSize_DISPATCH(pSubdevice, pParams) +#define subdeviceCtrlCmdInternalUvmUnregisterAccessCntrBuffer(pSubdevice, pParams) subdeviceCtrlCmdInternalUvmUnregisterAccessCntrBuffer_DISPATCH(pSubdevice, pParams) #define subdeviceCtrlCmdInternalGetChipInfo(pSubdevice, pParams) subdeviceCtrlCmdInternalGetChipInfo_DISPATCH(pSubdevice, pParams) #define subdeviceCtrlCmdInternalGetUserRegisterAccessMap(pSubdevice, pParams) subdeviceCtrlCmdInternalGetUserRegisterAccessMap_DISPATCH(pSubdevice, pParams) #define subdeviceCtrlCmdInternalGetDeviceInfoTable(pSubdevice, pParams) subdeviceCtrlCmdInternalGetDeviceInfoTable_DISPATCH(pSubdevice, pParams) @@ -1057,11 +1128,12 @@ #define subdeviceCtrlCmdInternalBusDestroyP2pMailbox(pSubdevice, pParams) subdeviceCtrlCmdInternalBusDestroyP2pMailbox_DISPATCH(pSubdevice, pParams) #define subdeviceCtrlCmdInternalBusCreateC2cPeerMapping(pSubdevice, pParams) subdeviceCtrlCmdInternalBusCreateC2cPeerMapping_DISPATCH(pSubdevice, pParams) #define subdeviceCtrlCmdInternalBusRemoveC2cPeerMapping(pSubdevice, pParams) subdeviceCtrlCmdInternalBusRemoveC2cPeerMapping_DISPATCH(pSubdevice, pParams) +#define subdeviceCtrlCmdInternalVmmuGetSpaForGpaEntries(pSubdevice, pParams) subdeviceCtrlCmdInternalVmmuGetSpaForGpaEntries_DISPATCH(pSubdevice, pParams) #define subdeviceCtrlCmdGmmuGetStaticInfo(pSubdevice, pParams) subdeviceCtrlCmdGmmuGetStaticInfo_DISPATCH(pSubdevice, pParams) #define subdeviceCtrlCmdInternalGmmuRegisterFaultBuffer(pSubdevice, pParams) subdeviceCtrlCmdInternalGmmuRegisterFaultBuffer_DISPATCH(pSubdevice, pParams) #define subdeviceCtrlCmdInternalGmmuUnregisterFaultBuffer(pSubdevice) subdeviceCtrlCmdInternalGmmuUnregisterFaultBuffer_DISPATCH(pSubdevice) #define subdeviceCtrlCmdInternalGmmuRegisterClientShadowFaultBuffer(pSubdevice, pParams) subdeviceCtrlCmdInternalGmmuRegisterClientShadowFaultBuffer_DISPATCH(pSubdevice, pParams) -#define subdeviceCtrlCmdInternalGmmuUnregisterClientShadowFaultBuffer(pSubdevice) subdeviceCtrlCmdInternalGmmuUnregisterClientShadowFaultBuffer_DISPATCH(pSubdevice) +#define subdeviceCtrlCmdInternalGmmuUnregisterClientShadowFaultBuffer(pSubdevice, pParams) subdeviceCtrlCmdInternalGmmuUnregisterClientShadowFaultBuffer_DISPATCH(pSubdevice, pParams) #define subdeviceCtrlCmdInternalGmmuCopyReservedSplitGVASpacePdesServer(pSubdevice, pCopyServerReservedPdesParams) subdeviceCtrlCmdInternalGmmuCopyReservedSplitGVASpacePdesServer_DISPATCH(pSubdevice, pCopyServerReservedPdesParams) #define subdeviceCtrlCmdCeGetPhysicalCaps(pSubdevice, pCeCapsParams) subdeviceCtrlCmdCeGetPhysicalCaps_DISPATCH(pSubdevice, pCeCapsParams) #define subdeviceCtrlCmdCeGetAllPhysicalCaps(pSubdevice, pCeCapsParams) subdeviceCtrlCmdCeGetAllPhysicalCaps_DISPATCH(pSubdevice, pCeCapsParams) @@ -1081,14 +1153,17 @@ #define subdeviceCtrlCmdInternalPerfPerfmonClientReservationSet(pSubdevice, pParams) subdeviceCtrlCmdInternalPerfPerfmonClientReservationSet_DISPATCH(pSubdevice, pParams) #define subdeviceCtrlCmdInternalPerfCfControllerSetMaxVGpuVMCount(pSubdevice, pParams) subdeviceCtrlCmdInternalPerfCfControllerSetMaxVGpuVMCount_DISPATCH(pSubdevice, pParams) #define subdeviceCtrlCmdInternalPerfGetAuxPowerState(pSubdevice, pParams) subdeviceCtrlCmdInternalPerfGetAuxPowerState_DISPATCH(pSubdevice, pParams) +#define subdeviceCtrlCmdInternalGc6EntryPrerequisite(pSubdevice, pG6EntryPrerequisite) subdeviceCtrlCmdInternalGc6EntryPrerequisite_DISPATCH(pSubdevice, pG6EntryPrerequisite) #define subdeviceCtrlCmdBifGetStaticInfo(pSubdevice, pParams) subdeviceCtrlCmdBifGetStaticInfo_DISPATCH(pSubdevice, pParams) #define subdeviceCtrlCmdBifGetAspmL1Flags(pSubdevice, pParams) subdeviceCtrlCmdBifGetAspmL1Flags_DISPATCH(pSubdevice, pParams) #define subdeviceCtrlCmdBifSetPcieRo(pSubdevice, pParams) subdeviceCtrlCmdBifSetPcieRo_DISPATCH(pSubdevice, pParams) +#define subdeviceCtrlCmdBifDisableSystemMemoryAccess(pSubdevice, pParams) subdeviceCtrlCmdBifDisableSystemMemoryAccess_DISPATCH(pSubdevice, pParams) #define subdeviceCtrlCmdHshubPeerConnConfig(pSubdevice, pParams) subdeviceCtrlCmdHshubPeerConnConfig_DISPATCH(pSubdevice, pParams) #define subdeviceCtrlCmdHshubFirstLinkPeerId(pSubdevice, pParams) subdeviceCtrlCmdHshubFirstLinkPeerId_DISPATCH(pSubdevice, pParams) #define subdeviceCtrlCmdHshubGetHshubIdForLinks(pSubdevice, pParams) subdeviceCtrlCmdHshubGetHshubIdForLinks_DISPATCH(pSubdevice, pParams) #define subdeviceCtrlCmdHshubGetNumUnits(pSubdevice, pParams) subdeviceCtrlCmdHshubGetNumUnits_DISPATCH(pSubdevice, pParams) #define subdeviceCtrlCmdHshubNextHshubId(pSubdevice, pParams) subdeviceCtrlCmdHshubNextHshubId_DISPATCH(pSubdevice, pParams) +#define subdeviceCtrlCmdHshubEgmConfig(pSubdevice, pParams) subdeviceCtrlCmdHshubEgmConfig_DISPATCH(pSubdevice, pParams) #define subdeviceCtrlCmdInternalNvlinkEnableComputePeerAddr(pSubdevice) subdeviceCtrlCmdInternalNvlinkEnableComputePeerAddr_DISPATCH(pSubdevice) #define subdeviceCtrlCmdInternalNvlinkGetSetNvswitchFabricAddr(pSubdevice, pParams) subdeviceCtrlCmdInternalNvlinkGetSetNvswitchFabricAddr_DISPATCH(pSubdevice, pParams) #define subdeviceCtrlCmdInternalNvlinkGetNumActiveLinksPerIoctrl(pSubdevice, pParams) subdeviceCtrlCmdInternalNvlinkGetNumActiveLinksPerIoctrl_DISPATCH(pSubdevice, pParams) @@ -1097,6 +1172,8 @@ #define subdeviceCtrlCmdInternalRemoveP2pCaps(pSubdevice, pParams) subdeviceCtrlCmdInternalRemoveP2pCaps_DISPATCH(pSubdevice, pParams) #define subdeviceCtrlCmdInternalGetPcieP2pCaps(pSubdevice, pParams) subdeviceCtrlCmdInternalGetPcieP2pCaps_DISPATCH(pSubdevice, pParams) #define subdeviceCtrlCmdInternalGetCoherentFbApertureSize(pSubdevice, pParams) subdeviceCtrlCmdInternalGetCoherentFbApertureSize_DISPATCH(pSubdevice, pParams) +#define subdeviceCtrlCmdInternalGetLocalAtsConfig(pSubdevice, pParams) subdeviceCtrlCmdInternalGetLocalAtsConfig_DISPATCH(pSubdevice, pParams) +#define subdeviceCtrlCmdInternalSetPeerAtsConfig(pSubdevice, pParams) subdeviceCtrlCmdInternalSetPeerAtsConfig_DISPATCH(pSubdevice, pParams) #define subdeviceCtrlCmdInternalInitGpuIntr(pSubdevice, pAttachParams) subdeviceCtrlCmdInternalInitGpuIntr_DISPATCH(pSubdevice, pAttachParams) #define subdeviceCtrlCmdInternalGsyncOptimizeTiming(pSubdevice, pAttachParams) subdeviceCtrlCmdInternalGsyncOptimizeTiming_DISPATCH(pSubdevice, pAttachParams) #define subdeviceCtrlCmdInternalGsyncGetDisplayIds(pSubdevice, pAttachParams) subdeviceCtrlCmdInternalGsyncGetDisplayIds_DISPATCH(pSubdevice, pAttachParams) @@ -1107,7 +1184,26 @@ #define subdeviceCtrlCmdInternalFbsrInit(pSubdevice, pParams) subdeviceCtrlCmdInternalFbsrInit_DISPATCH(pSubdevice, pParams) #define subdeviceCtrlCmdInternalFbsrSendRegionInfo(pSubdevice, pParams) subdeviceCtrlCmdInternalFbsrSendRegionInfo_DISPATCH(pSubdevice, pParams) #define subdeviceCtrlCmdInternalPostInitBrightcStateLoad(pSubdevice, pParams) subdeviceCtrlCmdInternalPostInitBrightcStateLoad_DISPATCH(pSubdevice, pParams) +#define subdeviceCtrlCmdInternalSetStaticEdidData(pSubdevice, pParams) subdeviceCtrlCmdInternalSetStaticEdidData_DISPATCH(pSubdevice, pParams) +#define subdeviceCtrlCmdInternalSmbpbiPfmReqHndlrCapUpdate(pSubdevice, pParams) subdeviceCtrlCmdInternalSmbpbiPfmReqHndlrCapUpdate_DISPATCH(pSubdevice, pParams) +#define subdeviceCtrlCmdInternalPmgrPfmReqHndlrStateLoadSync(pSubdevice, pParams) subdeviceCtrlCmdInternalPmgrPfmReqHndlrStateLoadSync_DISPATCH(pSubdevice, pParams) +#define subdeviceCtrlCmdInternalThermPfmReqHndlrStateInitSync(pSubdevice, pParams) subdeviceCtrlCmdInternalThermPfmReqHndlrStateInitSync_DISPATCH(pSubdevice, pParams) +#define subdeviceCtrlCmdInternalPerfPfmReqHndlrGetPm1State(pSubdevice, pParams) subdeviceCtrlCmdInternalPerfPfmReqHndlrGetPm1State_DISPATCH(pSubdevice, pParams) +#define subdeviceCtrlCmdInternalPerfPfmReqHndlrSetPm1State(pSubdevice, pParams) subdeviceCtrlCmdInternalPerfPfmReqHndlrSetPm1State_DISPATCH(pSubdevice, pParams) +#define subdeviceCtrlCmdInternalPmgrPfmReqHndlrUpdateEdppLimit(pSubdevice, pParams) subdeviceCtrlCmdInternalPmgrPfmReqHndlrUpdateEdppLimit_DISPATCH(pSubdevice, pParams) +#define subdeviceCtrlCmdInternalPmgrPfmReqHndlrGetEdppLimitInfo(pSubdevice, pParams) subdeviceCtrlCmdInternalPmgrPfmReqHndlrGetEdppLimitInfo_DISPATCH(pSubdevice, pParams) +#define subdeviceCtrlCmdInternalThermPfmReqHndlrUpdateTgpuLimit(pSubdevice, pParams) subdeviceCtrlCmdInternalThermPfmReqHndlrUpdateTgpuLimit_DISPATCH(pSubdevice, pParams) +#define subdeviceCtrlCmdInternalPmgrPfmReqHndlrConfigureTgpMode(pSubdevice, pParams) subdeviceCtrlCmdInternalPmgrPfmReqHndlrConfigureTgpMode_DISPATCH(pSubdevice, pParams) +#define subdeviceCtrlCmdInternalPmgrPfmReqHndlrConfigureTurboV2(pSubdevice, pParams) subdeviceCtrlCmdInternalPmgrPfmReqHndlrConfigureTurboV2_DISPATCH(pSubdevice, pParams) +#define subdeviceCtrlCmdInternalPerfPfmReqHndlrGetVpstateInfo(pSubdevice, pParams) subdeviceCtrlCmdInternalPerfPfmReqHndlrGetVpstateInfo_DISPATCH(pSubdevice, pParams) +#define subdeviceCtrlCmdInternalPerfPfmReqHndlrGetVpstateMapping(pSubdevice, pParams) subdeviceCtrlCmdInternalPerfPfmReqHndlrGetVpstateMapping_DISPATCH(pSubdevice, pParams) +#define subdeviceCtrlCmdInternalPerfPfmReqHndlrSetVpstate(pSubdevice, pParams) subdeviceCtrlCmdInternalPerfPfmReqHndlrSetVpstate_DISPATCH(pSubdevice, pParams) #define subdeviceCtrlCmdInternalPmgrUnsetDynamicBoostLimit(pSubdevice) subdeviceCtrlCmdInternalPmgrUnsetDynamicBoostLimit_DISPATCH(pSubdevice) +#define subdeviceCtrlCmdInternalDetectHsVideoBridge(pSubdevice) subdeviceCtrlCmdInternalDetectHsVideoBridge_DISPATCH(pSubdevice) +#define subdeviceCtrlCmdInternalConfComputeGetStaticInfo(pSubdevice, pParams) subdeviceCtrlCmdInternalConfComputeGetStaticInfo_DISPATCH(pSubdevice, pParams) +#define subdeviceCtrlCmdInternalConfComputeEncryptionControl(pSubdevice, pParams) subdeviceCtrlCmdInternalConfComputeEncryptionControl_DISPATCH(pSubdevice, pParams) +#define subdeviceCtrlCmdInternalConfComputeDeriveSwlKeys(pSubdevice, pParams) subdeviceCtrlCmdInternalConfComputeDeriveSwlKeys_DISPATCH(pSubdevice, pParams) +#define subdeviceCtrlCmdInternalConfComputeDeriveLceKeys(pSubdevice, pParams) subdeviceCtrlCmdInternalConfComputeDeriveLceKeys_DISPATCH(pSubdevice, pParams) #define subdeviceCtrlCmdVgpuMgrInternalBootloadGspVgpuPluginTask(pSubdevice, pParams) subdeviceCtrlCmdVgpuMgrInternalBootloadGspVgpuPluginTask_DISPATCH(pSubdevice, pParams) #define subdeviceCtrlCmdVgpuMgrInternalShutdownGspVgpuPluginTask(pSubdevice, pParams) subdeviceCtrlCmdVgpuMgrInternalShutdownGspVgpuPluginTask_DISPATCH(pSubdevice, pParams) #define subdeviceCtrlCmdVgpuMgrInternalPgpuAddVgpuType(pSubdevice, pParams) subdeviceCtrlCmdVgpuMgrInternalPgpuAddVgpuType_DISPATCH(pSubdevice, pParams) @@ -1123,10 +1219,11 @@ #define subdeviceCtrlCmdCcuMap(pSubdevice, pParams) subdeviceCtrlCmdCcuMap_DISPATCH(pSubdevice, pParams) #define subdeviceCtrlCmdCcuUnmap(pSubdevice, pParams) subdeviceCtrlCmdCcuUnmap_DISPATCH(pSubdevice, pParams) #define subdeviceCtrlCmdCcuSetStreamState(pSubdevice, pParams) subdeviceCtrlCmdCcuSetStreamState_DISPATCH(pSubdevice, pParams) +#define subdeviceCtrlCmdSpdmPartition(pSubdevice, pSpdmPartitionParams) subdeviceCtrlCmdSpdmPartition_DISPATCH(pSubdevice, pSpdmPartitionParams) #define subdeviceShareCallback(pGpuResource, pInvokingClient, pParentRef, pSharePolicy) subdeviceShareCallback_DISPATCH(pGpuResource, pInvokingClient, pParentRef, pSharePolicy) -#define subdeviceMapTo(pResource, pParams) subdeviceMapTo_DISPATCH(pResource, pParams) -#define subdeviceGetOrAllocNotifShare(pNotifier, hNotifierClient, hNotifierResource, ppNotifShare) subdeviceGetOrAllocNotifShare_DISPATCH(pNotifier, hNotifierClient, hNotifierResource, ppNotifShare) #define subdeviceCheckMemInterUnmap(pRmResource, bSubdeviceHandleProvided) subdeviceCheckMemInterUnmap_DISPATCH(pRmResource, bSubdeviceHandleProvided) +#define subdeviceGetOrAllocNotifShare(pNotifier, hNotifierClient, hNotifierResource, ppNotifShare) subdeviceGetOrAllocNotifShare_DISPATCH(pNotifier, hNotifierClient, hNotifierResource, ppNotifShare) +#define subdeviceMapTo(pResource, pParams) subdeviceMapTo_DISPATCH(pResource, pParams) #define subdeviceGetMapAddrSpace(pGpuResource, pCallContext, mapFlags, pAddrSpace) subdeviceGetMapAddrSpace_DISPATCH(pGpuResource, pCallContext, mapFlags, pAddrSpace) #define subdeviceSetNotificationShare(pNotifier, pNotifShare) subdeviceSetNotificationShare_DISPATCH(pNotifier, pNotifShare) #define subdeviceGetRefCount(pResource) subdeviceGetRefCount_DISPATCH(pResource) @@ -1142,8 +1239,10 @@ #define subdeviceGetMemInterMapParams(pRmResource, pParams) subdeviceGetMemInterMapParams_DISPATCH(pRmResource, pParams) #define subdeviceGetMemoryMappingDescriptor(pRmResource, ppMemDesc) subdeviceGetMemoryMappingDescriptor_DISPATCH(pRmResource, ppMemDesc) #define subdeviceUnregisterEvent(pNotifier, hNotifierClient, hNotifierResource, hEventClient, hEvent) subdeviceUnregisterEvent_DISPATCH(pNotifier, hNotifierClient, hNotifierResource, hEventClient, hEvent) +#define subdeviceControlSerialization_Prologue(pResource, pCallContext, pParams) subdeviceControlSerialization_Prologue_DISPATCH(pResource, pCallContext, pParams) #define subdeviceCanCopy(pResource) subdeviceCanCopy_DISPATCH(pResource) #define subdeviceIsDuplicate(pResource, hMemory, pDuplicate) subdeviceIsDuplicate_DISPATCH(pResource, hMemory, pDuplicate) +#define subdeviceControlSerialization_Epilogue(pResource, pCallContext, pParams) subdeviceControlSerialization_Epilogue_DISPATCH(pResource, pCallContext, pParams) #define subdeviceGetNotificationListPtr(pNotifier) subdeviceGetNotificationListPtr_DISPATCH(pNotifier) #define subdeviceGetNotificationShare(pNotifier) subdeviceGetNotificationShare_DISPATCH(pNotifier) #define subdeviceMap(pGpuResource, pCallContext, pParams, pCpuMapping) subdeviceMap_DISPATCH(pGpuResource, pCallContext, pParams, pCpuMapping) @@ -1394,7 +1493,10 @@ return pSubdevice->__subdeviceCtrlCmdBusGetEomStatus__(pSubdevice, pParams); } -NV_STATUS subdeviceCtrlCmdBusGetPcieReqAtomicsCaps_IMPL(struct Subdevice *pSubdevice, NV2080_CTRL_CMD_BUS_GET_PCIE_REQ_ATOMICS_CAPS_PARAMS *pParams); +static inline NV_STATUS subdeviceCtrlCmdBusGetPcieReqAtomicsCaps_92bfc3(struct Subdevice *pSubdevice, NV2080_CTRL_CMD_BUS_GET_PCIE_REQ_ATOMICS_CAPS_PARAMS *pParams) { + NV_ASSERT_PRECOMP(0); + return NV_ERR_NOT_SUPPORTED; +} static inline NV_STATUS subdeviceCtrlCmdBusGetPcieReqAtomicsCaps_DISPATCH(struct Subdevice *pSubdevice, NV2080_CTRL_CMD_BUS_GET_PCIE_REQ_ATOMICS_CAPS_PARAMS *pParams) { return pSubdevice->__subdeviceCtrlCmdBusGetPcieReqAtomicsCaps__(pSubdevice, pParams); @@ -1874,6 +1976,20 @@ return pSubdevice->__subdeviceCtrlCmdInternalMemmgrGetVgpuHostRmReservedFb__(pSubdevice, pParams); } +NV_STATUS subdeviceCtrlCmdGbGetSemaphoreSurfaceLayout_IMPL(struct Subdevice *pSubdevice, NV2080_CTRL_FB_GET_SEMAPHORE_SURFACE_LAYOUT_PARAMS *pParams); + +static inline NV_STATUS subdeviceCtrlCmdGbGetSemaphoreSurfaceLayout_DISPATCH(struct Subdevice *pSubdevice, NV2080_CTRL_FB_GET_SEMAPHORE_SURFACE_LAYOUT_PARAMS *pParams) { + return pSubdevice->__subdeviceCtrlCmdGbGetSemaphoreSurfaceLayout__(pSubdevice, pParams); +} + +static inline NV_STATUS subdeviceCtrlCmdInternalMemmgrMemoryTransferWithGsp_46f6a7(struct Subdevice *pSubdevice, NV2080_CTRL_INTERNAL_MEMMGR_MEMORY_TRANSFER_WITH_GSP_PARAMS *pParams) { + return NV_ERR_NOT_SUPPORTED; +} + +static inline NV_STATUS subdeviceCtrlCmdInternalMemmgrMemoryTransferWithGsp_DISPATCH(struct Subdevice *pSubdevice, NV2080_CTRL_INTERNAL_MEMMGR_MEMORY_TRANSFER_WITH_GSP_PARAMS *pParams) { + return pSubdevice->__subdeviceCtrlCmdInternalMemmgrMemoryTransferWithGsp__(pSubdevice, pParams); +} + NV_STATUS subdeviceCtrlCmdFbGetInfo_IMPL(struct Subdevice *pSubdevice, NV2080_CTRL_FB_GET_INFO_PARAMS *pFbInfoParams); static inline NV_STATUS subdeviceCtrlCmdFbGetInfo_DISPATCH(struct Subdevice *pSubdevice, NV2080_CTRL_FB_GET_INFO_PARAMS *pFbInfoParams) { @@ -2194,6 +2310,12 @@ return pSubdevice->__subdeviceCtrlCmdFifoGetAllocatedChannels__(pSubdevice, pParams); } +NV_STATUS subdeviceCtrlCmdInternalFifoGetNumSecureChannels_IMPL(struct Subdevice *pSubdevice, NV2080_CTRL_INTERNAL_FIFO_GET_NUM_SECURE_CHANNELS_PARAMS *pNumSecureChannelsParams); + +static inline NV_STATUS subdeviceCtrlCmdInternalFifoGetNumSecureChannels_DISPATCH(struct Subdevice *pSubdevice, NV2080_CTRL_INTERNAL_FIFO_GET_NUM_SECURE_CHANNELS_PARAMS *pNumSecureChannelsParams) { + return pSubdevice->__subdeviceCtrlCmdInternalFifoGetNumSecureChannels__(pSubdevice, pNumSecureChannelsParams); +} + NV_STATUS subdeviceCtrlCmdKGrGetInfo_IMPL(struct Subdevice *pSubdevice, NV2080_CTRL_GR_GET_INFO_PARAMS *pParams); static inline NV_STATUS subdeviceCtrlCmdKGrGetInfo_DISPATCH(struct Subdevice *pSubdevice, NV2080_CTRL_GR_GET_INFO_PARAMS *pParams) { @@ -2320,9 +2442,9 @@ return pSubdevice->__subdeviceCtrlCmdKGrGetCtxBufferPtes__(pSubdevice, pParams); } -NV_STATUS subdeviceCtrlCmdKGrGetCurrentResidentChannel_IMPL(struct Subdevice *pSubdevice, NV2080_CTRL_CMD_GR_GET_CURRENT_RESIDENT_CHANNEL_PARAMS *pParams); +NV_STATUS subdeviceCtrlCmdKGrGetCurrentResidentChannel_IMPL(struct Subdevice *pSubdevice, NV2080_CTRL_GR_GET_CURRENT_RESIDENT_CHANNEL_PARAMS *pParams); -static inline NV_STATUS subdeviceCtrlCmdKGrGetCurrentResidentChannel_DISPATCH(struct Subdevice *pSubdevice, NV2080_CTRL_CMD_GR_GET_CURRENT_RESIDENT_CHANNEL_PARAMS *pParams) { +static inline NV_STATUS subdeviceCtrlCmdKGrGetCurrentResidentChannel_DISPATCH(struct Subdevice *pSubdevice, NV2080_CTRL_GR_GET_CURRENT_RESIDENT_CHANNEL_PARAMS *pParams) { return pSubdevice->__subdeviceCtrlCmdKGrGetCurrentResidentChannel__(pSubdevice, pParams); } @@ -2602,6 +2724,12 @@ return pSubdevice->__subdeviceCtrlCmdGpuSetFabricAddr__(pSubdevice, pParams); } +NV_STATUS subdeviceCtrlCmdGpuSetEgmGpaFabricAddr_IMPL(struct Subdevice *pSubdevice, NV2080_CTRL_GPU_SET_EGM_GPA_FABRIC_BASE_ADDR_PARAMS *pParams); + +static inline NV_STATUS subdeviceCtrlCmdGpuSetEgmGpaFabricAddr_DISPATCH(struct Subdevice *pSubdevice, NV2080_CTRL_GPU_SET_EGM_GPA_FABRIC_BASE_ADDR_PARAMS *pParams) { + return pSubdevice->__subdeviceCtrlCmdGpuSetEgmGpaFabricAddr__(pSubdevice, pParams); +} + NV_STATUS subdeviceCtrlCmdGpuSetPower_IMPL(struct Subdevice *pSubdevice, NV2080_CTRL_GPU_SET_POWER_PARAMS *pSetPowerParams); static inline NV_STATUS subdeviceCtrlCmdGpuSetPower_DISPATCH(struct Subdevice *pSubdevice, NV2080_CTRL_GPU_SET_POWER_PARAMS *pSetPowerParams) { @@ -2872,6 +3000,12 @@ return pSubdevice->__subdeviceCtrlCmdGpuGetHwEngineId__(pSubdevice, pParams); } +NV_STATUS subdeviceCtrlCmdGpuGetVmmuSegmentSize_IMPL(struct Subdevice *pSubdevice, NV2080_CTRL_GPU_GET_VMMU_SEGMENT_SIZE_PARAMS *pParams); + +static inline NV_STATUS subdeviceCtrlCmdGpuGetVmmuSegmentSize_DISPATCH(struct Subdevice *pSubdevice, NV2080_CTRL_GPU_GET_VMMU_SEGMENT_SIZE_PARAMS *pParams) { + return pSubdevice->__subdeviceCtrlCmdGpuGetVmmuSegmentSize__(pSubdevice, pParams); +} + NV_STATUS subdeviceCtrlCmdGpuGetMaxSupportedPageSize_IMPL(struct Subdevice *pSubdevice, NV2080_CTRL_GPU_GET_MAX_SUPPORTED_PAGE_SIZE_PARAMS *pParams); static inline NV_STATUS subdeviceCtrlCmdGpuGetMaxSupportedPageSize_DISPATCH(struct Subdevice *pSubdevice, NV2080_CTRL_GPU_GET_MAX_SUPPORTED_PAGE_SIZE_PARAMS *pParams) { @@ -2932,6 +3066,18 @@ return pSubdevice->__subdeviceCtrlCmdGetGpuFabricProbeInfo__(pSubdevice, pParams); } +NV_STATUS subdeviceCtrlCmdGpuGetResetStatus_IMPL(struct Subdevice *pSubdevice, NV2080_CTRL_GPU_GET_RESET_STATUS_PARAMS *pParams); + +static inline NV_STATUS subdeviceCtrlCmdGpuGetResetStatus_DISPATCH(struct Subdevice *pSubdevice, NV2080_CTRL_GPU_GET_RESET_STATUS_PARAMS *pParams) { + return pSubdevice->__subdeviceCtrlCmdGpuGetResetStatus__(pSubdevice, pParams); +} + +NV_STATUS subdeviceCtrlCmdGpuGetDrainAndResetStatus_IMPL(struct Subdevice *pSubdevice, NV2080_CTRL_GPU_GET_DRAIN_AND_RESET_STATUS_PARAMS *pParams); + +static inline NV_STATUS subdeviceCtrlCmdGpuGetDrainAndResetStatus_DISPATCH(struct Subdevice *pSubdevice, NV2080_CTRL_GPU_GET_DRAIN_AND_RESET_STATUS_PARAMS *pParams) { + return pSubdevice->__subdeviceCtrlCmdGpuGetDrainAndResetStatus__(pSubdevice, pParams); +} + NV_STATUS subdeviceCtrlCmdEventSetTrigger_IMPL(struct Subdevice *pSubdevice); static inline NV_STATUS subdeviceCtrlCmdEventSetTrigger_DISPATCH(struct Subdevice *pSubdevice) { @@ -3208,6 +3354,18 @@ return pSubdevice->__subdeviceCtrlCmdEccGetClientExposedCounters__(pSubdevice, pParams); } +NV_STATUS subdeviceCtrlCmdEccGetEciCounters_IMPL(struct Subdevice *pSubdevice, NV2080_CTRL_ECC_GET_ECI_COUNTERS_PARAMS *pParams); + +static inline NV_STATUS subdeviceCtrlCmdEccGetEciCounters_DISPATCH(struct Subdevice *pSubdevice, NV2080_CTRL_ECC_GET_ECI_COUNTERS_PARAMS *pParams) { + return pSubdevice->__subdeviceCtrlCmdEccGetEciCounters__(pSubdevice, pParams); +} + +NV_STATUS subdeviceCtrlCmdEccGetVolatileCounts_IMPL(struct Subdevice *pSubdevice, NV2080_CTRL_ECC_GET_VOLATILE_COUNTS_PARAMS *pParams); + +static inline NV_STATUS subdeviceCtrlCmdEccGetVolatileCounts_DISPATCH(struct Subdevice *pSubdevice, NV2080_CTRL_ECC_GET_VOLATILE_COUNTS_PARAMS *pParams) { + return pSubdevice->__subdeviceCtrlCmdEccGetVolatileCounts__(pSubdevice, pParams); +} + NV_STATUS subdeviceCtrlCmdGpuQueryEccConfiguration_IMPL(struct Subdevice *pSubdevice, NV2080_CTRL_GPU_QUERY_ECC_CONFIGURATION_PARAMS *pConfig); static inline NV_STATUS subdeviceCtrlCmdGpuQueryEccConfiguration_DISPATCH(struct Subdevice *pSubdevice, NV2080_CTRL_GPU_QUERY_ECC_CONFIGURATION_PARAMS *pConfig) { @@ -3256,6 +3414,12 @@ return pSubdevice->__subdeviceCtrlCmdGspGetFeatures__(pSubdevice, pGspFeaturesParams); } +NV_STATUS subdeviceCtrlCmdGspGetRmHeapStats_IMPL(struct Subdevice *pSubdevice, NV2080_CTRL_GSP_GET_RM_HEAP_STATS_PARAMS *pGspRmHeapStatsParams); + +static inline NV_STATUS subdeviceCtrlCmdGspGetRmHeapStats_DISPATCH(struct Subdevice *pSubdevice, NV2080_CTRL_GSP_GET_RM_HEAP_STATS_PARAMS *pGspRmHeapStatsParams) { + return pSubdevice->__subdeviceCtrlCmdGspGetRmHeapStats__(pSubdevice, pGspRmHeapStatsParams); +} + NV_STATUS subdeviceCtrlCmdGpuGetActivePartitionIds_IMPL(struct Subdevice *pSubdevice, NV2080_CTRL_GPU_GET_ACTIVE_PARTITION_IDS_PARAMS *pParams); static inline NV_STATUS subdeviceCtrlCmdGpuGetActivePartitionIds_DISPATCH(struct Subdevice *pSubdevice, NV2080_CTRL_GPU_GET_ACTIVE_PARTITION_IDS_PARAMS *pParams) { @@ -3340,6 +3504,12 @@ return pSubdevice->__subdeviceCtrlCmdInternalKMIGmgrImportGPUInstance__(pSubdevice, pParams); } +NV_STATUS subdeviceCtrlCmdInternalKMIGmgrPromoteGpuInstanceMemRange_IMPL(struct Subdevice *pSubdevice, NV2080_CTRL_INTERNAL_KMIGMGR_PROMOTE_GPU_INSTANCE_MEM_RANGE_PARAMS *pParams); + +static inline NV_STATUS subdeviceCtrlCmdInternalKMIGmgrPromoteGpuInstanceMemRange_DISPATCH(struct Subdevice *pSubdevice, NV2080_CTRL_INTERNAL_KMIGMGR_PROMOTE_GPU_INSTANCE_MEM_RANGE_PARAMS *pParams) { + return pSubdevice->__subdeviceCtrlCmdInternalKMIGmgrPromoteGpuInstanceMemRange__(pSubdevice, pParams); +} + NV_STATUS subdeviceCtrlCmdOsUnixGc6BlockerRefCnt_IMPL(struct Subdevice *pSubdevice, NV2080_CTRL_OS_UNIX_GC6_BLOCKER_REFCNT_PARAMS *pParams); static inline NV_STATUS subdeviceCtrlCmdOsUnixGc6BlockerRefCnt_DISPATCH(struct Subdevice *pSubdevice, NV2080_CTRL_OS_UNIX_GC6_BLOCKER_REFCNT_PARAMS *pParams) { @@ -3412,34 +3582,88 @@ return pSubdevice->__subdeviceCtrlCmdDisplayGetDisplayMask__(pSubdevice, pParams); } -NV_STATUS subdeviceCtrlCmdMsencGetCaps_IMPL(struct Subdevice *pSubdevice, NV2080_CTRL_INTERNAL_MSENC_GET_CAPS_PARAMS *pParams); +NV_STATUS subdeviceCtrlCmdDisplayPinsetsToLockpins_IMPL(struct Subdevice *pSubdevice, NV2080_CTRL_INTERNAL_DISP_PINSETS_TO_LOCKPINS_PARAMS *pParams); -static inline NV_STATUS subdeviceCtrlCmdMsencGetCaps_DISPATCH(struct Subdevice *pSubdevice, NV2080_CTRL_INTERNAL_MSENC_GET_CAPS_PARAMS *pParams) { - return pSubdevice->__subdeviceCtrlCmdMsencGetCaps__(pSubdevice, pParams); +static inline NV_STATUS subdeviceCtrlCmdDisplayPinsetsToLockpins_DISPATCH(struct Subdevice *pSubdevice, NV2080_CTRL_INTERNAL_DISP_PINSETS_TO_LOCKPINS_PARAMS *pParams) { + return pSubdevice->__subdeviceCtrlCmdDisplayPinsetsToLockpins__(pSubdevice, pParams); } -NV_STATUS subdeviceCtrlCmdInternalUvmRegisterAccessCntrBuffer_IMPL(struct Subdevice *pSubdevice, NV2080_CTRL_INTERNAL_UVM_REGISTER_ACCESS_CNTR_BUFFER_PARAMS *pParams); +NV_STATUS subdeviceCtrlCmdDisplaySetSliLinkGpioSwControl_IMPL(struct Subdevice *pSubdevice, NV2080_CTRL_INTERNAL_DISP_SET_SLI_LINK_GPIO_SW_CONTROL_PARAMS *pParams); -static inline NV_STATUS subdeviceCtrlCmdInternalUvmRegisterAccessCntrBuffer_DISPATCH(struct Subdevice *pSubdevice, NV2080_CTRL_INTERNAL_UVM_REGISTER_ACCESS_CNTR_BUFFER_PARAMS *pParams) { - return pSubdevice->__subdeviceCtrlCmdInternalUvmRegisterAccessCntrBuffer__(pSubdevice, pParams); +static inline NV_STATUS subdeviceCtrlCmdDisplaySetSliLinkGpioSwControl_DISPATCH(struct Subdevice *pSubdevice, NV2080_CTRL_INTERNAL_DISP_SET_SLI_LINK_GPIO_SW_CONTROL_PARAMS *pParams) { + return pSubdevice->__subdeviceCtrlCmdDisplaySetSliLinkGpioSwControl__(pSubdevice, pParams); +} + +NV_STATUS subdeviceCtrlCmdInternalGpioProgramDirection_IMPL(struct Subdevice *pSubdevice, NV2080_CTRL_INTERNAL_GPIO_PROGRAM_DIRECTION_PARAMS *pParams); + +static inline NV_STATUS subdeviceCtrlCmdInternalGpioProgramDirection_DISPATCH(struct Subdevice *pSubdevice, NV2080_CTRL_INTERNAL_GPIO_PROGRAM_DIRECTION_PARAMS *pParams) { + return pSubdevice->__subdeviceCtrlCmdInternalGpioProgramDirection__(pSubdevice, pParams); +} + +NV_STATUS subdeviceCtrlCmdInternalGpioProgramOutput_IMPL(struct Subdevice *pSubdevice, NV2080_CTRL_INTERNAL_GPIO_PROGRAM_OUTPUT_PARAMS *pParams); + +static inline NV_STATUS subdeviceCtrlCmdInternalGpioProgramOutput_DISPATCH(struct Subdevice *pSubdevice, NV2080_CTRL_INTERNAL_GPIO_PROGRAM_OUTPUT_PARAMS *pParams) { + return pSubdevice->__subdeviceCtrlCmdInternalGpioProgramOutput__(pSubdevice, pParams); +} + +NV_STATUS subdeviceCtrlCmdInternalGpioReadInput_IMPL(struct Subdevice *pSubdevice, NV2080_CTRL_INTERNAL_GPIO_READ_INPUT_PARAMS *pParams); + +static inline NV_STATUS subdeviceCtrlCmdInternalGpioReadInput_DISPATCH(struct Subdevice *pSubdevice, NV2080_CTRL_INTERNAL_GPIO_READ_INPUT_PARAMS *pParams) { + return pSubdevice->__subdeviceCtrlCmdInternalGpioReadInput__(pSubdevice, pParams); +} + +NV_STATUS subdeviceCtrlCmdInternalGpioActivateHwFunction_IMPL(struct Subdevice *pSubdevice, NV2080_CTRL_INTERNAL_GPIO_ACTIVATE_HW_FUNCTION_PARAMS *pParams); + +static inline NV_STATUS subdeviceCtrlCmdInternalGpioActivateHwFunction_DISPATCH(struct Subdevice *pSubdevice, NV2080_CTRL_INTERNAL_GPIO_ACTIVATE_HW_FUNCTION_PARAMS *pParams) { + return pSubdevice->__subdeviceCtrlCmdInternalGpioActivateHwFunction__(pSubdevice, pParams); +} + +NV_STATUS subdeviceCtrlCmdInternalDisplayAcpiSubsytemActivated_IMPL(struct Subdevice *pSubdevice); + +static inline NV_STATUS subdeviceCtrlCmdInternalDisplayAcpiSubsytemActivated_DISPATCH(struct Subdevice *pSubdevice) { + return pSubdevice->__subdeviceCtrlCmdInternalDisplayAcpiSubsytemActivated__(pSubdevice); +} + +NV_STATUS subdeviceCtrlCmdInternalDisplayPreModeSet_IMPL(struct Subdevice *pSubdevice); + +static inline NV_STATUS subdeviceCtrlCmdInternalDisplayPreModeSet_DISPATCH(struct Subdevice *pSubdevice) { + return pSubdevice->__subdeviceCtrlCmdInternalDisplayPreModeSet__(pSubdevice); +} + +NV_STATUS subdeviceCtrlCmdInternalDisplayPostModeSet_IMPL(struct Subdevice *pSubdevice); + +static inline NV_STATUS subdeviceCtrlCmdInternalDisplayPostModeSet_DISPATCH(struct Subdevice *pSubdevice) { + return pSubdevice->__subdeviceCtrlCmdInternalDisplayPostModeSet__(pSubdevice); } -NV_STATUS subdeviceCtrlCmdInternalUvmUnregisterAccessCntrBuffer_IMPL(struct Subdevice *pSubdevice); +NV_STATUS subdeviceCtrlCmdDisplayUnixConsole_IMPL(struct Subdevice *pSubdevice, NV2080_CTRL_CMD_INTERNAL_DISPLAY_UNIX_CONSOLE_PARAMS *pParams); -static inline NV_STATUS subdeviceCtrlCmdInternalUvmUnregisterAccessCntrBuffer_DISPATCH(struct Subdevice *pSubdevice) { - return pSubdevice->__subdeviceCtrlCmdInternalUvmUnregisterAccessCntrBuffer__(pSubdevice); +static inline NV_STATUS subdeviceCtrlCmdDisplayUnixConsole_DISPATCH(struct Subdevice *pSubdevice, NV2080_CTRL_CMD_INTERNAL_DISPLAY_UNIX_CONSOLE_PARAMS *pParams) { + return pSubdevice->__subdeviceCtrlCmdDisplayUnixConsole__(pSubdevice, pParams); } -NV_STATUS subdeviceCtrlCmdInternalUvmServiceAccessCntrBuffer_IMPL(struct Subdevice *pSubdevice); +NV_STATUS subdeviceCtrlCmdDisplayPostVgaRestore_IMPL(struct Subdevice *pSubdevice, NV2080_CTRL_CMD_INTERNAL_DISPLAY_POST_RESTORE_PARAMS *pParams); -static inline NV_STATUS subdeviceCtrlCmdInternalUvmServiceAccessCntrBuffer_DISPATCH(struct Subdevice *pSubdevice) { - return pSubdevice->__subdeviceCtrlCmdInternalUvmServiceAccessCntrBuffer__(pSubdevice); +static inline NV_STATUS subdeviceCtrlCmdDisplayPostVgaRestore_DISPATCH(struct Subdevice *pSubdevice, NV2080_CTRL_CMD_INTERNAL_DISPLAY_POST_RESTORE_PARAMS *pParams) { + return pSubdevice->__subdeviceCtrlCmdDisplayPostVgaRestore__(pSubdevice, pParams); } -NV_STATUS subdeviceCtrlCmdInternalUvmGetAccessCntrBufferSize_IMPL(struct Subdevice *pSubdevice, NV2080_CTRL_INTERNAL_UVM_GET_ACCESS_CNTR_BUFFER_SIZE_PARAMS *pParams); +NV_STATUS subdeviceCtrlCmdMsencGetCaps_IMPL(struct Subdevice *pSubdevice, NV2080_CTRL_INTERNAL_MSENC_GET_CAPS_PARAMS *pParams); + +static inline NV_STATUS subdeviceCtrlCmdMsencGetCaps_DISPATCH(struct Subdevice *pSubdevice, NV2080_CTRL_INTERNAL_MSENC_GET_CAPS_PARAMS *pParams) { + return pSubdevice->__subdeviceCtrlCmdMsencGetCaps__(pSubdevice, pParams); +} + +NV_STATUS subdeviceCtrlCmdInternalUvmRegisterAccessCntrBuffer_IMPL(struct Subdevice *pSubdevice, NV2080_CTRL_INTERNAL_UVM_REGISTER_ACCESS_CNTR_BUFFER_PARAMS *pParams); + +static inline NV_STATUS subdeviceCtrlCmdInternalUvmRegisterAccessCntrBuffer_DISPATCH(struct Subdevice *pSubdevice, NV2080_CTRL_INTERNAL_UVM_REGISTER_ACCESS_CNTR_BUFFER_PARAMS *pParams) { + return pSubdevice->__subdeviceCtrlCmdInternalUvmRegisterAccessCntrBuffer__(pSubdevice, pParams); +} + +NV_STATUS subdeviceCtrlCmdInternalUvmUnregisterAccessCntrBuffer_IMPL(struct Subdevice *pSubdevice, NV2080_CTRL_INTERNAL_UVM_UNREGISTER_ACCESS_CNTR_BUFFER_PARAMS *pParams); -static inline NV_STATUS subdeviceCtrlCmdInternalUvmGetAccessCntrBufferSize_DISPATCH(struct Subdevice *pSubdevice, NV2080_CTRL_INTERNAL_UVM_GET_ACCESS_CNTR_BUFFER_SIZE_PARAMS *pParams) { - return pSubdevice->__subdeviceCtrlCmdInternalUvmGetAccessCntrBufferSize__(pSubdevice, pParams); +static inline NV_STATUS subdeviceCtrlCmdInternalUvmUnregisterAccessCntrBuffer_DISPATCH(struct Subdevice *pSubdevice, NV2080_CTRL_INTERNAL_UVM_UNREGISTER_ACCESS_CNTR_BUFFER_PARAMS *pParams) { + return pSubdevice->__subdeviceCtrlCmdInternalUvmUnregisterAccessCntrBuffer__(pSubdevice, pParams); } NV_STATUS subdeviceCtrlCmdInternalGetChipInfo_IMPL(struct Subdevice *pSubdevice, NV2080_CTRL_INTERNAL_GPU_GET_CHIP_INFO_PARAMS *pParams); @@ -3514,6 +3738,12 @@ return pSubdevice->__subdeviceCtrlCmdInternalBusRemoveC2cPeerMapping__(pSubdevice, pParams); } +NV_STATUS subdeviceCtrlCmdInternalVmmuGetSpaForGpaEntries_IMPL(struct Subdevice *pSubdevice, NV2080_CTRL_INTERNAL_VMMU_GET_SPA_FOR_GPA_ENTRIES_PARAMS *pParams); + +static inline NV_STATUS subdeviceCtrlCmdInternalVmmuGetSpaForGpaEntries_DISPATCH(struct Subdevice *pSubdevice, NV2080_CTRL_INTERNAL_VMMU_GET_SPA_FOR_GPA_ENTRIES_PARAMS *pParams) { + return pSubdevice->__subdeviceCtrlCmdInternalVmmuGetSpaForGpaEntries__(pSubdevice, pParams); +} + NV_STATUS subdeviceCtrlCmdGmmuGetStaticInfo_IMPL(struct Subdevice *pSubdevice, NV2080_CTRL_INTERNAL_GMMU_GET_STATIC_INFO_PARAMS *pParams); static inline NV_STATUS subdeviceCtrlCmdGmmuGetStaticInfo_DISPATCH(struct Subdevice *pSubdevice, NV2080_CTRL_INTERNAL_GMMU_GET_STATIC_INFO_PARAMS *pParams) { @@ -3538,10 +3768,10 @@ return pSubdevice->__subdeviceCtrlCmdInternalGmmuRegisterClientShadowFaultBuffer__(pSubdevice, pParams); } -NV_STATUS subdeviceCtrlCmdInternalGmmuUnregisterClientShadowFaultBuffer_IMPL(struct Subdevice *pSubdevice); +NV_STATUS subdeviceCtrlCmdInternalGmmuUnregisterClientShadowFaultBuffer_IMPL(struct Subdevice *pSubdevice, NV2080_CTRL_INTERNAL_GMMU_UNREGISTER_CLIENT_SHADOW_FAULT_BUFFER_PARAMS *pParams); -static inline NV_STATUS subdeviceCtrlCmdInternalGmmuUnregisterClientShadowFaultBuffer_DISPATCH(struct Subdevice *pSubdevice) { - return pSubdevice->__subdeviceCtrlCmdInternalGmmuUnregisterClientShadowFaultBuffer__(pSubdevice); +static inline NV_STATUS subdeviceCtrlCmdInternalGmmuUnregisterClientShadowFaultBuffer_DISPATCH(struct Subdevice *pSubdevice, NV2080_CTRL_INTERNAL_GMMU_UNREGISTER_CLIENT_SHADOW_FAULT_BUFFER_PARAMS *pParams) { + return pSubdevice->__subdeviceCtrlCmdInternalGmmuUnregisterClientShadowFaultBuffer__(pSubdevice, pParams); } NV_STATUS subdeviceCtrlCmdInternalGmmuCopyReservedSplitGVASpacePdesServer_IMPL(struct Subdevice *pSubdevice, NV2080_CTRL_INTERNAL_GMMU_COPY_RESERVED_SPLIT_GVASPACE_PDES_TO_SERVER_PARAMS *pCopyServerReservedPdesParams); @@ -3658,6 +3888,12 @@ return pSubdevice->__subdeviceCtrlCmdInternalPerfGetAuxPowerState__(pSubdevice, pParams); } +NV_STATUS subdeviceCtrlCmdInternalGc6EntryPrerequisite_IMPL(struct Subdevice *pSubdevice, NV2080_CTRL_INTERNAL_GC6_ENTRY_PREREQUISITE_PARAMS *pG6EntryPrerequisite); + +static inline NV_STATUS subdeviceCtrlCmdInternalGc6EntryPrerequisite_DISPATCH(struct Subdevice *pSubdevice, NV2080_CTRL_INTERNAL_GC6_ENTRY_PREREQUISITE_PARAMS *pG6EntryPrerequisite) { + return pSubdevice->__subdeviceCtrlCmdInternalGc6EntryPrerequisite__(pSubdevice, pG6EntryPrerequisite); +} + NV_STATUS subdeviceCtrlCmdBifGetStaticInfo_IMPL(struct Subdevice *pSubdevice, NV2080_CTRL_INTERNAL_BIF_GET_STATIC_INFO_PARAMS *pParams); static inline NV_STATUS subdeviceCtrlCmdBifGetStaticInfo_DISPATCH(struct Subdevice *pSubdevice, NV2080_CTRL_INTERNAL_BIF_GET_STATIC_INFO_PARAMS *pParams) { @@ -3676,6 +3912,12 @@ return pSubdevice->__subdeviceCtrlCmdBifSetPcieRo__(pSubdevice, pParams); } +NV_STATUS subdeviceCtrlCmdBifDisableSystemMemoryAccess_IMPL(struct Subdevice *pSubdevice, NV2080_CTRL_INTERNAL_BIF_DISABLE_SYSTEM_MEMORY_ACCESS_PARAMS *pParams); + +static inline NV_STATUS subdeviceCtrlCmdBifDisableSystemMemoryAccess_DISPATCH(struct Subdevice *pSubdevice, NV2080_CTRL_INTERNAL_BIF_DISABLE_SYSTEM_MEMORY_ACCESS_PARAMS *pParams) { + return pSubdevice->__subdeviceCtrlCmdBifDisableSystemMemoryAccess__(pSubdevice, pParams); +} + NV_STATUS subdeviceCtrlCmdHshubPeerConnConfig_IMPL(struct Subdevice *pSubdevice, NV2080_CTRL_INTERNAL_HSHUB_PEER_CONN_CONFIG_PARAMS *pParams); static inline NV_STATUS subdeviceCtrlCmdHshubPeerConnConfig_DISPATCH(struct Subdevice *pSubdevice, NV2080_CTRL_INTERNAL_HSHUB_PEER_CONN_CONFIG_PARAMS *pParams) { @@ -3706,6 +3948,12 @@ return pSubdevice->__subdeviceCtrlCmdHshubNextHshubId__(pSubdevice, pParams); } +NV_STATUS subdeviceCtrlCmdHshubEgmConfig_IMPL(struct Subdevice *pSubdevice, NV2080_CTRL_INTERNAL_HSHUB_EGM_CONFIG_PARAMS *pParams); + +static inline NV_STATUS subdeviceCtrlCmdHshubEgmConfig_DISPATCH(struct Subdevice *pSubdevice, NV2080_CTRL_INTERNAL_HSHUB_EGM_CONFIG_PARAMS *pParams) { + return pSubdevice->__subdeviceCtrlCmdHshubEgmConfig__(pSubdevice, pParams); +} + NV_STATUS subdeviceCtrlCmdInternalNvlinkEnableComputePeerAddr_IMPL(struct Subdevice *pSubdevice); static inline NV_STATUS subdeviceCtrlCmdInternalNvlinkEnableComputePeerAddr_DISPATCH(struct Subdevice *pSubdevice) { @@ -3754,6 +4002,18 @@ return pSubdevice->__subdeviceCtrlCmdInternalGetCoherentFbApertureSize__(pSubdevice, pParams); } +NV_STATUS subdeviceCtrlCmdInternalGetLocalAtsConfig_IMPL(struct Subdevice *pSubdevice, NV2080_CTRL_INTERNAL_MEMSYS_GET_LOCAL_ATS_CONFIG_PARAMS *pParams); + +static inline NV_STATUS subdeviceCtrlCmdInternalGetLocalAtsConfig_DISPATCH(struct Subdevice *pSubdevice, NV2080_CTRL_INTERNAL_MEMSYS_GET_LOCAL_ATS_CONFIG_PARAMS *pParams) { + return pSubdevice->__subdeviceCtrlCmdInternalGetLocalAtsConfig__(pSubdevice, pParams); +} + +NV_STATUS subdeviceCtrlCmdInternalSetPeerAtsConfig_IMPL(struct Subdevice *pSubdevice, NV2080_CTRL_INTERNAL_MEMSYS_SET_PEER_ATS_CONFIG_PARAMS *pParams); + +static inline NV_STATUS subdeviceCtrlCmdInternalSetPeerAtsConfig_DISPATCH(struct Subdevice *pSubdevice, NV2080_CTRL_INTERNAL_MEMSYS_SET_PEER_ATS_CONFIG_PARAMS *pParams) { + return pSubdevice->__subdeviceCtrlCmdInternalSetPeerAtsConfig__(pSubdevice, pParams); +} + NV_STATUS subdeviceCtrlCmdInternalInitGpuIntr_IMPL(struct Subdevice *pSubdevice, NV2080_CTRL_INTERNAL_GSYNC_ATTACH_AND_INIT_PARAMS *pAttachParams); static inline NV_STATUS subdeviceCtrlCmdInternalInitGpuIntr_DISPATCH(struct Subdevice *pSubdevice, NV2080_CTRL_INTERNAL_GSYNC_ATTACH_AND_INIT_PARAMS *pAttachParams) { @@ -3814,12 +4074,126 @@ return pSubdevice->__subdeviceCtrlCmdInternalPostInitBrightcStateLoad__(pSubdevice, pParams); } +NV_STATUS subdeviceCtrlCmdInternalSetStaticEdidData_IMPL(struct Subdevice *pSubdevice, NV2080_CTRL_CMD_INTERNAL_SET_STATIC_EDID_DATA_PARAMS *pParams); + +static inline NV_STATUS subdeviceCtrlCmdInternalSetStaticEdidData_DISPATCH(struct Subdevice *pSubdevice, NV2080_CTRL_CMD_INTERNAL_SET_STATIC_EDID_DATA_PARAMS *pParams) { + return pSubdevice->__subdeviceCtrlCmdInternalSetStaticEdidData__(pSubdevice, pParams); +} + +NV_STATUS subdeviceCtrlCmdInternalSmbpbiPfmReqHndlrCapUpdate_IMPL(struct Subdevice *pSubdevice, NV2080_CTRL_INTERNAL_SMBPBI_PFM_REQ_HNDLR_CAP_UPDATE_PARAMS *pParams); + +static inline NV_STATUS subdeviceCtrlCmdInternalSmbpbiPfmReqHndlrCapUpdate_DISPATCH(struct Subdevice *pSubdevice, NV2080_CTRL_INTERNAL_SMBPBI_PFM_REQ_HNDLR_CAP_UPDATE_PARAMS *pParams) { + return pSubdevice->__subdeviceCtrlCmdInternalSmbpbiPfmReqHndlrCapUpdate__(pSubdevice, pParams); +} + +NV_STATUS subdeviceCtrlCmdInternalPmgrPfmReqHndlrStateLoadSync_IMPL(struct Subdevice *pSubdevice, NV2080_CTRL_INTERNAL_PFM_REQ_HNDLR_STATE_SYNC_PARAMS *pParams); + +static inline NV_STATUS subdeviceCtrlCmdInternalPmgrPfmReqHndlrStateLoadSync_DISPATCH(struct Subdevice *pSubdevice, NV2080_CTRL_INTERNAL_PFM_REQ_HNDLR_STATE_SYNC_PARAMS *pParams) { + return pSubdevice->__subdeviceCtrlCmdInternalPmgrPfmReqHndlrStateLoadSync__(pSubdevice, pParams); +} + +NV_STATUS subdeviceCtrlCmdInternalThermPfmReqHndlrStateInitSync_IMPL(struct Subdevice *pSubdevice, NV2080_CTRL_INTERNAL_PFM_REQ_HNDLR_STATE_SYNC_PARAMS *pParams); + +static inline NV_STATUS subdeviceCtrlCmdInternalThermPfmReqHndlrStateInitSync_DISPATCH(struct Subdevice *pSubdevice, NV2080_CTRL_INTERNAL_PFM_REQ_HNDLR_STATE_SYNC_PARAMS *pParams) { + return pSubdevice->__subdeviceCtrlCmdInternalThermPfmReqHndlrStateInitSync__(pSubdevice, pParams); +} + +NV_STATUS subdeviceCtrlCmdInternalPerfPfmReqHndlrGetPm1State_IMPL(struct Subdevice *pSubdevice, NV2080_CTRL_CMD_INTERNAL_PERF_PFM_REQ_HNDLR_GET_PM1_STATE_PARAMS *pParams); + +static inline NV_STATUS subdeviceCtrlCmdInternalPerfPfmReqHndlrGetPm1State_DISPATCH(struct Subdevice *pSubdevice, NV2080_CTRL_CMD_INTERNAL_PERF_PFM_REQ_HNDLR_GET_PM1_STATE_PARAMS *pParams) { + return pSubdevice->__subdeviceCtrlCmdInternalPerfPfmReqHndlrGetPm1State__(pSubdevice, pParams); +} + +NV_STATUS subdeviceCtrlCmdInternalPerfPfmReqHndlrSetPm1State_IMPL(struct Subdevice *pSubdevice, NV2080_CTRL_CMD_INTERNAL_PERF_PFM_REQ_HNDLR_SET_PM1_STATE_PARAMS *pParams); + +static inline NV_STATUS subdeviceCtrlCmdInternalPerfPfmReqHndlrSetPm1State_DISPATCH(struct Subdevice *pSubdevice, NV2080_CTRL_CMD_INTERNAL_PERF_PFM_REQ_HNDLR_SET_PM1_STATE_PARAMS *pParams) { + return pSubdevice->__subdeviceCtrlCmdInternalPerfPfmReqHndlrSetPm1State__(pSubdevice, pParams); +} + +NV_STATUS subdeviceCtrlCmdInternalPmgrPfmReqHndlrUpdateEdppLimit_IMPL(struct Subdevice *pSubdevice, NV2080_CTRL_CMD_INTERNAL_PMGR_PFM_REQ_HNDLR_UPDATE_EDPP_LIMIT_PARAMS *pParams); + +static inline NV_STATUS subdeviceCtrlCmdInternalPmgrPfmReqHndlrUpdateEdppLimit_DISPATCH(struct Subdevice *pSubdevice, NV2080_CTRL_CMD_INTERNAL_PMGR_PFM_REQ_HNDLR_UPDATE_EDPP_LIMIT_PARAMS *pParams) { + return pSubdevice->__subdeviceCtrlCmdInternalPmgrPfmReqHndlrUpdateEdppLimit__(pSubdevice, pParams); +} + +NV_STATUS subdeviceCtrlCmdInternalPmgrPfmReqHndlrGetEdppLimitInfo_IMPL(struct Subdevice *pSubdevice, NV2080_CTRL_CMD_INTERNAL_PMGR_PFM_REQ_HNDLR_GET_EDPP_LIMIT_INFO_PARAMS *pParams); + +static inline NV_STATUS subdeviceCtrlCmdInternalPmgrPfmReqHndlrGetEdppLimitInfo_DISPATCH(struct Subdevice *pSubdevice, NV2080_CTRL_CMD_INTERNAL_PMGR_PFM_REQ_HNDLR_GET_EDPP_LIMIT_INFO_PARAMS *pParams) { + return pSubdevice->__subdeviceCtrlCmdInternalPmgrPfmReqHndlrGetEdppLimitInfo__(pSubdevice, pParams); +} + +NV_STATUS subdeviceCtrlCmdInternalThermPfmReqHndlrUpdateTgpuLimit_IMPL(struct Subdevice *pSubdevice, NV2080_CTRL_CMD_INTERNAL_THERM_PFM_REQ_HNDLR_UPDATE_TGPU_LIMIT_PARAMS *pParams); + +static inline NV_STATUS subdeviceCtrlCmdInternalThermPfmReqHndlrUpdateTgpuLimit_DISPATCH(struct Subdevice *pSubdevice, NV2080_CTRL_CMD_INTERNAL_THERM_PFM_REQ_HNDLR_UPDATE_TGPU_LIMIT_PARAMS *pParams) { + return pSubdevice->__subdeviceCtrlCmdInternalThermPfmReqHndlrUpdateTgpuLimit__(pSubdevice, pParams); +} + +NV_STATUS subdeviceCtrlCmdInternalPmgrPfmReqHndlrConfigureTgpMode_IMPL(struct Subdevice *pSubdevice, NV2080_CTRL_CMD_INTERNAL_PMGR_PFM_REQ_HNDLR_CONFIGURE_TGP_MODE_PARAMS *pParams); + +static inline NV_STATUS subdeviceCtrlCmdInternalPmgrPfmReqHndlrConfigureTgpMode_DISPATCH(struct Subdevice *pSubdevice, NV2080_CTRL_CMD_INTERNAL_PMGR_PFM_REQ_HNDLR_CONFIGURE_TGP_MODE_PARAMS *pParams) { + return pSubdevice->__subdeviceCtrlCmdInternalPmgrPfmReqHndlrConfigureTgpMode__(pSubdevice, pParams); +} + +NV_STATUS subdeviceCtrlCmdInternalPmgrPfmReqHndlrConfigureTurboV2_IMPL(struct Subdevice *pSubdevice, NV2080_CTRL_CMD_INTERNAL_PMGR_PFM_REQ_HNDLR_CONFIGURE_TURBO_V2_PARAMS *pParams); + +static inline NV_STATUS subdeviceCtrlCmdInternalPmgrPfmReqHndlrConfigureTurboV2_DISPATCH(struct Subdevice *pSubdevice, NV2080_CTRL_CMD_INTERNAL_PMGR_PFM_REQ_HNDLR_CONFIGURE_TURBO_V2_PARAMS *pParams) { + return pSubdevice->__subdeviceCtrlCmdInternalPmgrPfmReqHndlrConfigureTurboV2__(pSubdevice, pParams); +} + +NV_STATUS subdeviceCtrlCmdInternalPerfPfmReqHndlrGetVpstateInfo_IMPL(struct Subdevice *pSubdevice, NV2080_CTRL_CMD_INTERNAL_PERF_PFM_REQ_HNDLR_GET_VPSTATE_INFO_PARAMS *pParams); + +static inline NV_STATUS subdeviceCtrlCmdInternalPerfPfmReqHndlrGetVpstateInfo_DISPATCH(struct Subdevice *pSubdevice, NV2080_CTRL_CMD_INTERNAL_PERF_PFM_REQ_HNDLR_GET_VPSTATE_INFO_PARAMS *pParams) { + return pSubdevice->__subdeviceCtrlCmdInternalPerfPfmReqHndlrGetVpstateInfo__(pSubdevice, pParams); +} + +NV_STATUS subdeviceCtrlCmdInternalPerfPfmReqHndlrGetVpstateMapping_IMPL(struct Subdevice *pSubdevice, NV2080_CTRL_CMD_INTERNAL_PERF_PFM_REQ_HNDLR_GET_VPSTATE_MAPPING_PARAMS *pParams); + +static inline NV_STATUS subdeviceCtrlCmdInternalPerfPfmReqHndlrGetVpstateMapping_DISPATCH(struct Subdevice *pSubdevice, NV2080_CTRL_CMD_INTERNAL_PERF_PFM_REQ_HNDLR_GET_VPSTATE_MAPPING_PARAMS *pParams) { + return pSubdevice->__subdeviceCtrlCmdInternalPerfPfmReqHndlrGetVpstateMapping__(pSubdevice, pParams); +} + +NV_STATUS subdeviceCtrlCmdInternalPerfPfmReqHndlrSetVpstate_IMPL(struct Subdevice *pSubdevice, NV2080_CTRL_CMD_INTERNAL_PERF_PFM_REQ_HNDLR_SET_VPSTATE_PARAMS *pParams); + +static inline NV_STATUS subdeviceCtrlCmdInternalPerfPfmReqHndlrSetVpstate_DISPATCH(struct Subdevice *pSubdevice, NV2080_CTRL_CMD_INTERNAL_PERF_PFM_REQ_HNDLR_SET_VPSTATE_PARAMS *pParams) { + return pSubdevice->__subdeviceCtrlCmdInternalPerfPfmReqHndlrSetVpstate__(pSubdevice, pParams); +} + NV_STATUS subdeviceCtrlCmdInternalPmgrUnsetDynamicBoostLimit_IMPL(struct Subdevice *pSubdevice); static inline NV_STATUS subdeviceCtrlCmdInternalPmgrUnsetDynamicBoostLimit_DISPATCH(struct Subdevice *pSubdevice) { return pSubdevice->__subdeviceCtrlCmdInternalPmgrUnsetDynamicBoostLimit__(pSubdevice); } +NV_STATUS subdeviceCtrlCmdInternalDetectHsVideoBridge_IMPL(struct Subdevice *pSubdevice); + +static inline NV_STATUS subdeviceCtrlCmdInternalDetectHsVideoBridge_DISPATCH(struct Subdevice *pSubdevice) { + return pSubdevice->__subdeviceCtrlCmdInternalDetectHsVideoBridge__(pSubdevice); +} + +NV_STATUS subdeviceCtrlCmdInternalConfComputeGetStaticInfo_IMPL(struct Subdevice *pSubdevice, NV2080_CTRL_INTERNAL_CONF_COMPUTE_GET_STATIC_INFO_PARAMS *pParams); + +static inline NV_STATUS subdeviceCtrlCmdInternalConfComputeGetStaticInfo_DISPATCH(struct Subdevice *pSubdevice, NV2080_CTRL_INTERNAL_CONF_COMPUTE_GET_STATIC_INFO_PARAMS *pParams) { + return pSubdevice->__subdeviceCtrlCmdInternalConfComputeGetStaticInfo__(pSubdevice, pParams); +} + +NV_STATUS subdeviceCtrlCmdInternalConfComputeEncryptionControl_IMPL(struct Subdevice *pSubdevice, NV2080_CTRL_CMD_INTERNAL_CONF_COMPUTE_ENCRYPTION_CONTROL_PARAMS *pParams); + +static inline NV_STATUS subdeviceCtrlCmdInternalConfComputeEncryptionControl_DISPATCH(struct Subdevice *pSubdevice, NV2080_CTRL_CMD_INTERNAL_CONF_COMPUTE_ENCRYPTION_CONTROL_PARAMS *pParams) { + return pSubdevice->__subdeviceCtrlCmdInternalConfComputeEncryptionControl__(pSubdevice, pParams); +} + +NV_STATUS subdeviceCtrlCmdInternalConfComputeDeriveSwlKeys_IMPL(struct Subdevice *pSubdevice, NV2080_CTRL_INTERNAL_CONF_COMPUTE_DERIVE_SWL_KEYS_PARAMS *pParams); + +static inline NV_STATUS subdeviceCtrlCmdInternalConfComputeDeriveSwlKeys_DISPATCH(struct Subdevice *pSubdevice, NV2080_CTRL_INTERNAL_CONF_COMPUTE_DERIVE_SWL_KEYS_PARAMS *pParams) { + return pSubdevice->__subdeviceCtrlCmdInternalConfComputeDeriveSwlKeys__(pSubdevice, pParams); +} + +NV_STATUS subdeviceCtrlCmdInternalConfComputeDeriveLceKeys_IMPL(struct Subdevice *pSubdevice, NV2080_CTRL_INTERNAL_CONF_COMPUTE_DERIVE_LCE_KEYS_PARAMS *pParams); + +static inline NV_STATUS subdeviceCtrlCmdInternalConfComputeDeriveLceKeys_DISPATCH(struct Subdevice *pSubdevice, NV2080_CTRL_INTERNAL_CONF_COMPUTE_DERIVE_LCE_KEYS_PARAMS *pParams) { + return pSubdevice->__subdeviceCtrlCmdInternalConfComputeDeriveLceKeys__(pSubdevice, pParams); +} + NV_STATUS subdeviceCtrlCmdVgpuMgrInternalBootloadGspVgpuPluginTask_IMPL(struct Subdevice *pSubdevice, NV2080_CTRL_VGPU_MGR_INTERNAL_BOOTLOAD_GSP_VGPU_PLUGIN_TASK_PARAMS *pParams); static inline NV_STATUS subdeviceCtrlCmdVgpuMgrInternalBootloadGspVgpuPluginTask_DISPATCH(struct Subdevice *pSubdevice, NV2080_CTRL_VGPU_MGR_INTERNAL_BOOTLOAD_GSP_VGPU_PLUGIN_TASK_PARAMS *pParams) { @@ -3910,20 +4284,26 @@ return pSubdevice->__subdeviceCtrlCmdCcuSetStreamState__(pSubdevice, pParams); } +NV_STATUS subdeviceCtrlCmdSpdmPartition_IMPL(struct Subdevice *pSubdevice, NV2080_CTRL_INTERNAL_SPDM_PARTITION_PARAMS *pSpdmPartitionParams); + +static inline NV_STATUS subdeviceCtrlCmdSpdmPartition_DISPATCH(struct Subdevice *pSubdevice, NV2080_CTRL_INTERNAL_SPDM_PARTITION_PARAMS *pSpdmPartitionParams) { + return pSubdevice->__subdeviceCtrlCmdSpdmPartition__(pSubdevice, pSpdmPartitionParams); +} + static inline NvBool subdeviceShareCallback_DISPATCH(struct Subdevice *pGpuResource, struct RsClient *pInvokingClient, struct RsResourceRef *pParentRef, RS_SHARE_POLICY *pSharePolicy) { return pGpuResource->__subdeviceShareCallback__(pGpuResource, pInvokingClient, pParentRef, pSharePolicy); } -static inline NV_STATUS subdeviceMapTo_DISPATCH(struct Subdevice *pResource, RS_RES_MAP_TO_PARAMS *pParams) { - return pResource->__subdeviceMapTo__(pResource, pParams); +static inline NV_STATUS subdeviceCheckMemInterUnmap_DISPATCH(struct Subdevice *pRmResource, NvBool bSubdeviceHandleProvided) { + return pRmResource->__subdeviceCheckMemInterUnmap__(pRmResource, bSubdeviceHandleProvided); } static inline NV_STATUS subdeviceGetOrAllocNotifShare_DISPATCH(struct Subdevice *pNotifier, NvHandle hNotifierClient, NvHandle hNotifierResource, struct NotifShare **ppNotifShare) { return pNotifier->__subdeviceGetOrAllocNotifShare__(pNotifier, hNotifierClient, hNotifierResource, ppNotifShare); } -static inline NV_STATUS subdeviceCheckMemInterUnmap_DISPATCH(struct Subdevice *pRmResource, NvBool bSubdeviceHandleProvided) { - return pRmResource->__subdeviceCheckMemInterUnmap__(pRmResource, bSubdeviceHandleProvided); +static inline NV_STATUS subdeviceMapTo_DISPATCH(struct Subdevice *pResource, RS_RES_MAP_TO_PARAMS *pParams) { + return pResource->__subdeviceMapTo__(pResource, pParams); } static inline NV_STATUS subdeviceGetMapAddrSpace_DISPATCH(struct Subdevice *pGpuResource, struct CALL_CONTEXT *pCallContext, NvU32 mapFlags, NV_ADDRESS_SPACE *pAddrSpace) { @@ -3986,6 +4366,10 @@ return pNotifier->__subdeviceUnregisterEvent__(pNotifier, hNotifierClient, hNotifierResource, hEventClient, hEvent); } +static inline NV_STATUS subdeviceControlSerialization_Prologue_DISPATCH(struct Subdevice *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return pResource->__subdeviceControlSerialization_Prologue__(pResource, pCallContext, pParams); +} + static inline NvBool subdeviceCanCopy_DISPATCH(struct Subdevice *pResource) { return pResource->__subdeviceCanCopy__(pResource); } @@ -3994,6 +4378,10 @@ return pResource->__subdeviceIsDuplicate__(pResource, hMemory, pDuplicate); } +static inline void subdeviceControlSerialization_Epilogue_DISPATCH(struct Subdevice *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + pResource->__subdeviceControlSerialization_Epilogue__(pResource, pCallContext, pParams); +} + static inline PEVENTNOTIFICATION *subdeviceGetNotificationListPtr_DISPATCH(struct Subdevice *pNotifier) { return pNotifier->__subdeviceGetNotificationListPtr__(pNotifier); } @@ -4026,6 +4414,10 @@ return; } +static inline void subdeviceRestoreVF(struct Subdevice *pSubdevice, struct CALL_CONTEXT *pCallContext) { + return; +} + static inline void subdeviceReleaseNvlinkErrorInjectionMode(struct Subdevice *pSubdevice, struct CALL_CONTEXT *pCallContext) { return; } @@ -4103,33 +4495,6 @@ * RES_GET_HANDLE */ NV_STATUS CliGetSubDeviceHandleFromGpu(NvHandle, struct OBJGPU*, NvHandle *); - -/** - * WARNING: This function is deprecated and use is *strongly* discouraged - * (especially for new code!) - * - * From the function name (CliSetSubDeviceContext) it appears as a simple - * accessor but violates expectations by modifying the SLI BC threadstate (calls - * to GPU_RES_SET_THREAD_BC_STATE). This can be dangerous if not carefully - * managed by the caller. - * - * Instead of using this routine, please use subdeviceGetByHandle then call - * GPU_RES_GET_GPU, RES_GET_HANDLE, GPU_RES_SET_THREAD_BC_STATE as needed. - * - * Note that GPU_RES_GET_GPU supports returning a pGpu for both pDevice, - * pSubdevice, the base pResource type, and any resource that inherits from - * GpuResource. That is, instead of using CliSetGpuContext or - * CliSetSubDeviceContext, please use following pattern to look up the pGpu: - * - * OBJGPU *pGpu = GPU_RES_GET_GPU(pResource or pResourceRef->pResource) - * - * To set the threadstate, please use: - * - * GPU_RES_SET_THREAD_BC_STATE(pResource or pResourceRef->pResource); - */ -NV_STATUS CliSetSubDeviceContext(NvHandle hClient, NvHandle hSubdevice, NvHandle *phDevice, - struct OBJGPU **ppGpu); - #endif #ifdef __cplusplus diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/generated/g_sw_test_nvoc.c nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_sw_test_nvoc.c --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/generated/g_sw_test_nvoc.c 2023-10-25 20:27:20.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_sw_test_nvoc.c 2024-03-05 22:18:46.000000000 +0000 @@ -120,7 +120,7 @@ /*pExportInfo=*/ &__nvoc_export_info_SoftwareMethodTest }; -static NV_STATUS __nvoc_thunk_SoftwareMethodTest_chandesGetSwMethods(struct ChannelDescendant *pSwTest, METHOD **ppMethods, NvU32 *pNumMethods) { +static NV_STATUS __nvoc_thunk_SoftwareMethodTest_chandesGetSwMethods(struct ChannelDescendant *pSwTest, const METHOD **ppMethods, NvU32 *pNumMethods) { return swtestGetSwMethods((struct SoftwareMethodTest *)(((unsigned char *)pSwTest) - __nvoc_rtti_SoftwareMethodTest_ChannelDescendant.offset), ppMethods, pNumMethods); } @@ -212,6 +212,10 @@ return notifyUnregisterEvent((struct Notifier *)(((unsigned char *)pNotifier) + __nvoc_rtti_SoftwareMethodTest_Notifier.offset), hNotifierClient, hNotifierResource, hEventClient, hEvent); } +static NV_STATUS __nvoc_thunk_RmResource_swtestControlSerialization_Prologue(struct SoftwareMethodTest *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return rmresControlSerialization_Prologue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_SoftwareMethodTest_RmResource.offset), pCallContext, pParams); +} + static NvBool __nvoc_thunk_RsResource_swtestCanCopy(struct SoftwareMethodTest *pResource) { return resCanCopy((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_SoftwareMethodTest_RsResource.offset)); } @@ -224,6 +228,10 @@ return resIsDuplicate((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_SoftwareMethodTest_RsResource.offset), hMemory, pDuplicate); } +static void __nvoc_thunk_RmResource_swtestControlSerialization_Epilogue(struct SoftwareMethodTest *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + rmresControlSerialization_Epilogue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_SoftwareMethodTest_RmResource.offset), pCallContext, pParams); +} + static PEVENTNOTIFICATION *__nvoc_thunk_Notifier_swtestGetNotificationListPtr(struct SoftwareMethodTest *pNotifier) { return notifyGetNotificationListPtr((struct Notifier *)(((unsigned char *)pNotifier) + __nvoc_rtti_SoftwareMethodTest_Notifier.offset)); } @@ -327,12 +335,16 @@ pThis->__swtestUnregisterEvent__ = &__nvoc_thunk_Notifier_swtestUnregisterEvent; + pThis->__swtestControlSerialization_Prologue__ = &__nvoc_thunk_RmResource_swtestControlSerialization_Prologue; + pThis->__swtestCanCopy__ = &__nvoc_thunk_RsResource_swtestCanCopy; pThis->__swtestPreDestruct__ = &__nvoc_thunk_RsResource_swtestPreDestruct; pThis->__swtestIsDuplicate__ = &__nvoc_thunk_RsResource_swtestIsDuplicate; + pThis->__swtestControlSerialization_Epilogue__ = &__nvoc_thunk_RmResource_swtestControlSerialization_Epilogue; + pThis->__swtestGetNotificationListPtr__ = &__nvoc_thunk_Notifier_swtestGetNotificationListPtr; pThis->__swtestGetNotificationShare__ = &__nvoc_thunk_Notifier_swtestGetNotificationShare; @@ -367,13 +379,16 @@ SoftwareMethodTest *pThis; RmHalspecOwner *pRmhalspecowner; - pThis = portMemAllocNonPaged(sizeof(SoftwareMethodTest)); - if (pThis == NULL) return NV_ERR_NO_MEMORY; + status = __nvoc_handleObjCreateMemAlloc(createFlags, sizeof(SoftwareMethodTest), (void**)&pThis, (void**)ppThis); + if (status != NV_OK) + return status; portMemSet(pThis, 0, sizeof(SoftwareMethodTest)); __nvoc_initRtti(staticCast(pThis, Dynamic), &__nvoc_class_def_SoftwareMethodTest); + pThis->__nvoc_base_ChannelDescendant.__nvoc_base_GpuResource.__nvoc_base_RmResource.__nvoc_base_RsResource.__nvoc_base_Object.createFlags = createFlags; + if (pParent != NULL && !(createFlags & NVOC_OBJ_CREATE_FLAGS_PARENT_HALSPEC_ONLY)) { pParentObj = dynamicCast(pParent, Object); @@ -393,11 +408,17 @@ if (status != NV_OK) goto __nvoc_objCreate_SoftwareMethodTest_cleanup; *ppThis = pThis; + return NV_OK; __nvoc_objCreate_SoftwareMethodTest_cleanup: // do not call destructors here since the constructor already called them - portMemFree(pThis); + if (createFlags & NVOC_OBJ_CREATE_FLAGS_IN_PLACE_CONSTRUCT) + portMemSet(pThis, 0, sizeof(SoftwareMethodTest)); + else + portMemFree(pThis); + + // coverity[leaked_storage:FALSE] return status; } diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/generated/g_sw_test_nvoc.h nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_sw_test_nvoc.h --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/generated/g_sw_test_nvoc.h 2023-10-25 20:27:20.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_sw_test_nvoc.h 2024-03-05 22:18:46.000000000 +0000 @@ -57,7 +57,7 @@ struct Notifier *__nvoc_pbase_Notifier; struct ChannelDescendant *__nvoc_pbase_ChannelDescendant; struct SoftwareMethodTest *__nvoc_pbase_SoftwareMethodTest; - NV_STATUS (*__swtestGetSwMethods__)(struct SoftwareMethodTest *, METHOD **, NvU32 *); + NV_STATUS (*__swtestGetSwMethods__)(struct SoftwareMethodTest *, const METHOD **, NvU32 *); NV_STATUS (*__swtestCheckMemInterUnmap__)(struct SoftwareMethodTest *, NvBool); NvBool (*__swtestShareCallback__)(struct SoftwareMethodTest *, struct RsClient *, struct RsResourceRef *, RS_SHARE_POLICY *); NvBool (*__swtestAccessCallback__)(struct SoftwareMethodTest *, struct RsClient *, void *, RsAccessRight); @@ -80,9 +80,11 @@ NvBool (*__swtestIsSwMethodStalling__)(struct SoftwareMethodTest *, NvU32); NV_STATUS (*__swtestControlFilter__)(struct SoftwareMethodTest *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); NV_STATUS (*__swtestUnregisterEvent__)(struct SoftwareMethodTest *, NvHandle, NvHandle, NvHandle, NvHandle); + NV_STATUS (*__swtestControlSerialization_Prologue__)(struct SoftwareMethodTest *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); NvBool (*__swtestCanCopy__)(struct SoftwareMethodTest *); void (*__swtestPreDestruct__)(struct SoftwareMethodTest *); NV_STATUS (*__swtestIsDuplicate__)(struct SoftwareMethodTest *, NvHandle, NvBool *); + void (*__swtestControlSerialization_Epilogue__)(struct SoftwareMethodTest *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); PEVENTNOTIFICATION *(*__swtestGetNotificationListPtr__)(struct SoftwareMethodTest *); struct NotifShare *(*__swtestGetNotificationShare__)(struct SoftwareMethodTest *); NV_STATUS (*__swtestMap__)(struct SoftwareMethodTest *, struct CALL_CONTEXT *, struct RS_CPU_MAP_PARAMS *, struct RsCpuMapping *); @@ -140,16 +142,18 @@ #define swtestIsSwMethodStalling(pChannelDescendant, hHandle) swtestIsSwMethodStalling_DISPATCH(pChannelDescendant, hHandle) #define swtestControlFilter(pResource, pCallContext, pParams) swtestControlFilter_DISPATCH(pResource, pCallContext, pParams) #define swtestUnregisterEvent(pNotifier, hNotifierClient, hNotifierResource, hEventClient, hEvent) swtestUnregisterEvent_DISPATCH(pNotifier, hNotifierClient, hNotifierResource, hEventClient, hEvent) +#define swtestControlSerialization_Prologue(pResource, pCallContext, pParams) swtestControlSerialization_Prologue_DISPATCH(pResource, pCallContext, pParams) #define swtestCanCopy(pResource) swtestCanCopy_DISPATCH(pResource) #define swtestPreDestruct(pResource) swtestPreDestruct_DISPATCH(pResource) #define swtestIsDuplicate(pResource, hMemory, pDuplicate) swtestIsDuplicate_DISPATCH(pResource, hMemory, pDuplicate) +#define swtestControlSerialization_Epilogue(pResource, pCallContext, pParams) swtestControlSerialization_Epilogue_DISPATCH(pResource, pCallContext, pParams) #define swtestGetNotificationListPtr(pNotifier) swtestGetNotificationListPtr_DISPATCH(pNotifier) #define swtestGetNotificationShare(pNotifier) swtestGetNotificationShare_DISPATCH(pNotifier) #define swtestMap(pGpuResource, pCallContext, pParams, pCpuMapping) swtestMap_DISPATCH(pGpuResource, pCallContext, pParams, pCpuMapping) #define swtestGetOrAllocNotifShare(pNotifier, hNotifierClient, hNotifierResource, ppNotifShare) swtestGetOrAllocNotifShare_DISPATCH(pNotifier, hNotifierClient, hNotifierResource, ppNotifShare) -NV_STATUS swtestGetSwMethods_IMPL(struct SoftwareMethodTest *pSwTest, METHOD **ppMethods, NvU32 *pNumMethods); +NV_STATUS swtestGetSwMethods_IMPL(struct SoftwareMethodTest *pSwTest, const METHOD **ppMethods, NvU32 *pNumMethods); -static inline NV_STATUS swtestGetSwMethods_DISPATCH(struct SoftwareMethodTest *pSwTest, METHOD **ppMethods, NvU32 *pNumMethods) { +static inline NV_STATUS swtestGetSwMethods_DISPATCH(struct SoftwareMethodTest *pSwTest, const METHOD **ppMethods, NvU32 *pNumMethods) { return pSwTest->__swtestGetSwMethods__(pSwTest, ppMethods, pNumMethods); } @@ -241,6 +245,10 @@ return pNotifier->__swtestUnregisterEvent__(pNotifier, hNotifierClient, hNotifierResource, hEventClient, hEvent); } +static inline NV_STATUS swtestControlSerialization_Prologue_DISPATCH(struct SoftwareMethodTest *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return pResource->__swtestControlSerialization_Prologue__(pResource, pCallContext, pParams); +} + static inline NvBool swtestCanCopy_DISPATCH(struct SoftwareMethodTest *pResource) { return pResource->__swtestCanCopy__(pResource); } @@ -253,6 +261,10 @@ return pResource->__swtestIsDuplicate__(pResource, hMemory, pDuplicate); } +static inline void swtestControlSerialization_Epilogue_DISPATCH(struct SoftwareMethodTest *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + pResource->__swtestControlSerialization_Epilogue__(pResource, pCallContext, pParams); +} + static inline PEVENTNOTIFICATION *swtestGetNotificationListPtr_DISPATCH(struct SoftwareMethodTest *pNotifier) { return pNotifier->__swtestGetNotificationListPtr__(pNotifier); } diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/generated/g_swintr_nvoc.c nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_swintr_nvoc.c --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/generated/g_swintr_nvoc.c 2023-10-25 20:27:20.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_swintr_nvoc.c 2024-03-05 22:18:47.000000000 +0000 @@ -75,7 +75,7 @@ /*pExportInfo=*/ &__nvoc_export_info_SwIntr }; -static void __nvoc_thunk_SwIntr_intrservRegisterIntrService(OBJGPU *pGpu, struct IntrService *pSwIntr, IntrServiceRecord pRecords[163]) { +static void __nvoc_thunk_SwIntr_intrservRegisterIntrService(OBJGPU *pGpu, struct IntrService *pSwIntr, IntrServiceRecord pRecords[167]) { swintrRegisterIntrService(pGpu, (struct SwIntr *)(((unsigned char *)pSwIntr) - __nvoc_rtti_SwIntr_IntrService.offset), pRecords); } @@ -83,10 +83,6 @@ return swintrServiceInterrupt(pGpu, (struct SwIntr *)(((unsigned char *)pSwIntr) - __nvoc_rtti_SwIntr_IntrService.offset), pParams); } -static NV_STATUS __nvoc_thunk_OBJENGSTATE_swintrReconcileTunableState(POBJGPU pGpu, struct SwIntr *pEngstate, void *pTunableState) { - return engstateReconcileTunableState(pGpu, (struct OBJENGSTATE *)(((unsigned char *)pEngstate) + __nvoc_rtti_SwIntr_OBJENGSTATE.offset), pTunableState); -} - static NV_STATUS __nvoc_thunk_OBJENGSTATE_swintrStateLoad(POBJGPU pGpu, struct SwIntr *pEngstate, NvU32 arg0) { return engstateStateLoad(pGpu, (struct OBJENGSTATE *)(((unsigned char *)pEngstate) + __nvoc_rtti_SwIntr_OBJENGSTATE.offset), arg0); } @@ -135,18 +131,6 @@ return engstateStatePreInitUnlocked(pGpu, (struct OBJENGSTATE *)(((unsigned char *)pEngstate) + __nvoc_rtti_SwIntr_OBJENGSTATE.offset)); } -static NV_STATUS __nvoc_thunk_OBJENGSTATE_swintrGetTunableState(POBJGPU pGpu, struct SwIntr *pEngstate, void *pTunableState) { - return engstateGetTunableState(pGpu, (struct OBJENGSTATE *)(((unsigned char *)pEngstate) + __nvoc_rtti_SwIntr_OBJENGSTATE.offset), pTunableState); -} - -static NV_STATUS __nvoc_thunk_OBJENGSTATE_swintrCompareTunableState(POBJGPU pGpu, struct SwIntr *pEngstate, void *pTunables1, void *pTunables2) { - return engstateCompareTunableState(pGpu, (struct OBJENGSTATE *)(((unsigned char *)pEngstate) + __nvoc_rtti_SwIntr_OBJENGSTATE.offset), pTunables1, pTunables2); -} - -static void __nvoc_thunk_OBJENGSTATE_swintrFreeTunableState(POBJGPU pGpu, struct SwIntr *pEngstate, void *pTunableState) { - engstateFreeTunableState(pGpu, (struct OBJENGSTATE *)(((unsigned char *)pEngstate) + __nvoc_rtti_SwIntr_OBJENGSTATE.offset), pTunableState); -} - static NvBool __nvoc_thunk_IntrService_swintrClearInterrupt(OBJGPU *pGpu, struct SwIntr *pIntrService, IntrServiceClearInterruptArguments *pParams) { return intrservClearInterrupt(pGpu, (struct IntrService *)(((unsigned char *)pIntrService) + __nvoc_rtti_SwIntr_IntrService.offset), pParams); } @@ -155,14 +139,6 @@ return engstateStatePostLoad(pGpu, (struct OBJENGSTATE *)(((unsigned char *)pEngstate) + __nvoc_rtti_SwIntr_OBJENGSTATE.offset), arg0); } -static NV_STATUS __nvoc_thunk_OBJENGSTATE_swintrAllocTunableState(POBJGPU pGpu, struct SwIntr *pEngstate, void **ppTunableState) { - return engstateAllocTunableState(pGpu, (struct OBJENGSTATE *)(((unsigned char *)pEngstate) + __nvoc_rtti_SwIntr_OBJENGSTATE.offset), ppTunableState); -} - -static NV_STATUS __nvoc_thunk_OBJENGSTATE_swintrSetTunableState(POBJGPU pGpu, struct SwIntr *pEngstate, void *pTunableState) { - return engstateSetTunableState(pGpu, (struct OBJENGSTATE *)(((unsigned char *)pEngstate) + __nvoc_rtti_SwIntr_OBJENGSTATE.offset), pTunableState); -} - static NV_STATUS __nvoc_thunk_OBJENGSTATE_swintrConstructEngine(POBJGPU pGpu, struct SwIntr *pEngstate, ENGDESCRIPTOR arg0) { return engstateConstructEngine(pGpu, (struct OBJENGSTATE *)(((unsigned char *)pEngstate) + __nvoc_rtti_SwIntr_OBJENGSTATE.offset), arg0); } @@ -219,8 +195,6 @@ pThis->__nvoc_base_IntrService.__intrservServiceInterrupt__ = &__nvoc_thunk_SwIntr_intrservServiceInterrupt; - pThis->__swintrReconcileTunableState__ = &__nvoc_thunk_OBJENGSTATE_swintrReconcileTunableState; - pThis->__swintrStateLoad__ = &__nvoc_thunk_OBJENGSTATE_swintrStateLoad; pThis->__swintrStateUnload__ = &__nvoc_thunk_OBJENGSTATE_swintrStateUnload; @@ -245,20 +219,10 @@ pThis->__swintrStatePreInitUnlocked__ = &__nvoc_thunk_OBJENGSTATE_swintrStatePreInitUnlocked; - pThis->__swintrGetTunableState__ = &__nvoc_thunk_OBJENGSTATE_swintrGetTunableState; - - pThis->__swintrCompareTunableState__ = &__nvoc_thunk_OBJENGSTATE_swintrCompareTunableState; - - pThis->__swintrFreeTunableState__ = &__nvoc_thunk_OBJENGSTATE_swintrFreeTunableState; - pThis->__swintrClearInterrupt__ = &__nvoc_thunk_IntrService_swintrClearInterrupt; pThis->__swintrStatePostLoad__ = &__nvoc_thunk_OBJENGSTATE_swintrStatePostLoad; - pThis->__swintrAllocTunableState__ = &__nvoc_thunk_OBJENGSTATE_swintrAllocTunableState; - - pThis->__swintrSetTunableState__ = &__nvoc_thunk_OBJENGSTATE_swintrSetTunableState; - pThis->__swintrConstructEngine__ = &__nvoc_thunk_OBJENGSTATE_swintrConstructEngine; pThis->__swintrIsPresent__ = &__nvoc_thunk_OBJENGSTATE_swintrIsPresent; @@ -285,13 +249,16 @@ Object *pParentObj; SwIntr *pThis; - pThis = portMemAllocNonPaged(sizeof(SwIntr)); - if (pThis == NULL) return NV_ERR_NO_MEMORY; + status = __nvoc_handleObjCreateMemAlloc(createFlags, sizeof(SwIntr), (void**)&pThis, (void**)ppThis); + if (status != NV_OK) + return status; portMemSet(pThis, 0, sizeof(SwIntr)); __nvoc_initRtti(staticCast(pThis, Dynamic), &__nvoc_class_def_SwIntr); + pThis->__nvoc_base_OBJENGSTATE.__nvoc_base_Object.createFlags = createFlags; + if (pParent != NULL && !(createFlags & NVOC_OBJ_CREATE_FLAGS_PARENT_HALSPEC_ONLY)) { pParentObj = dynamicCast(pParent, Object); @@ -307,11 +274,17 @@ if (status != NV_OK) goto __nvoc_objCreate_SwIntr_cleanup; *ppThis = pThis; + return NV_OK; __nvoc_objCreate_SwIntr_cleanup: // do not call destructors here since the constructor already called them - portMemFree(pThis); + if (createFlags & NVOC_OBJ_CREATE_FLAGS_IN_PLACE_CONSTRUCT) + portMemSet(pThis, 0, sizeof(SwIntr)); + else + portMemFree(pThis); + + // coverity[leaked_storage:FALSE] return status; } diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/generated/g_swintr_nvoc.h nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_swintr_nvoc.h --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/generated/g_swintr_nvoc.h 2023-10-25 20:27:20.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_swintr_nvoc.h 2024-03-05 22:18:47.000000000 +0000 @@ -59,7 +59,6 @@ struct SwIntr *__nvoc_pbase_SwIntr; void (*__swintrRegisterIntrService__)(OBJGPU *, struct SwIntr *, IntrServiceRecord *); NvU32 (*__swintrServiceInterrupt__)(OBJGPU *, struct SwIntr *, IntrServiceServiceInterruptArguments *); - NV_STATUS (*__swintrReconcileTunableState__)(POBJGPU, struct SwIntr *, void *); NV_STATUS (*__swintrStateLoad__)(POBJGPU, struct SwIntr *, NvU32); NV_STATUS (*__swintrStateUnload__)(POBJGPU, struct SwIntr *, NvU32); NV_STATUS (*__swintrServiceNotificationInterrupt__)(OBJGPU *, struct SwIntr *, IntrServiceServiceNotificationInterruptArguments *); @@ -72,13 +71,8 @@ void (*__swintrInitMissing__)(POBJGPU, struct SwIntr *); NV_STATUS (*__swintrStatePreInitLocked__)(POBJGPU, struct SwIntr *); NV_STATUS (*__swintrStatePreInitUnlocked__)(POBJGPU, struct SwIntr *); - NV_STATUS (*__swintrGetTunableState__)(POBJGPU, struct SwIntr *, void *); - NV_STATUS (*__swintrCompareTunableState__)(POBJGPU, struct SwIntr *, void *, void *); - void (*__swintrFreeTunableState__)(POBJGPU, struct SwIntr *, void *); NvBool (*__swintrClearInterrupt__)(OBJGPU *, struct SwIntr *, IntrServiceClearInterruptArguments *); NV_STATUS (*__swintrStatePostLoad__)(POBJGPU, struct SwIntr *, NvU32); - NV_STATUS (*__swintrAllocTunableState__)(POBJGPU, struct SwIntr *, void **); - NV_STATUS (*__swintrSetTunableState__)(POBJGPU, struct SwIntr *, void *); NV_STATUS (*__swintrConstructEngine__)(POBJGPU, struct SwIntr *, ENGDESCRIPTOR); NvBool (*__swintrIsPresent__)(POBJGPU, struct SwIntr *); }; @@ -115,7 +109,6 @@ #define swintrRegisterIntrService(pGpu, pSwIntr, pRecords) swintrRegisterIntrService_DISPATCH(pGpu, pSwIntr, pRecords) #define swintrServiceInterrupt(pGpu, pSwIntr, pParams) swintrServiceInterrupt_DISPATCH(pGpu, pSwIntr, pParams) -#define swintrReconcileTunableState(pGpu, pEngstate, pTunableState) swintrReconcileTunableState_DISPATCH(pGpu, pEngstate, pTunableState) #define swintrStateLoad(pGpu, pEngstate, arg0) swintrStateLoad_DISPATCH(pGpu, pEngstate, arg0) #define swintrStateUnload(pGpu, pEngstate, arg0) swintrStateUnload_DISPATCH(pGpu, pEngstate, arg0) #define swintrServiceNotificationInterrupt(pGpu, pIntrService, pParams) swintrServiceNotificationInterrupt_DISPATCH(pGpu, pIntrService, pParams) @@ -128,18 +121,13 @@ #define swintrInitMissing(pGpu, pEngstate) swintrInitMissing_DISPATCH(pGpu, pEngstate) #define swintrStatePreInitLocked(pGpu, pEngstate) swintrStatePreInitLocked_DISPATCH(pGpu, pEngstate) #define swintrStatePreInitUnlocked(pGpu, pEngstate) swintrStatePreInitUnlocked_DISPATCH(pGpu, pEngstate) -#define swintrGetTunableState(pGpu, pEngstate, pTunableState) swintrGetTunableState_DISPATCH(pGpu, pEngstate, pTunableState) -#define swintrCompareTunableState(pGpu, pEngstate, pTunables1, pTunables2) swintrCompareTunableState_DISPATCH(pGpu, pEngstate, pTunables1, pTunables2) -#define swintrFreeTunableState(pGpu, pEngstate, pTunableState) swintrFreeTunableState_DISPATCH(pGpu, pEngstate, pTunableState) #define swintrClearInterrupt(pGpu, pIntrService, pParams) swintrClearInterrupt_DISPATCH(pGpu, pIntrService, pParams) #define swintrStatePostLoad(pGpu, pEngstate, arg0) swintrStatePostLoad_DISPATCH(pGpu, pEngstate, arg0) -#define swintrAllocTunableState(pGpu, pEngstate, ppTunableState) swintrAllocTunableState_DISPATCH(pGpu, pEngstate, ppTunableState) -#define swintrSetTunableState(pGpu, pEngstate, pTunableState) swintrSetTunableState_DISPATCH(pGpu, pEngstate, pTunableState) #define swintrConstructEngine(pGpu, pEngstate, arg0) swintrConstructEngine_DISPATCH(pGpu, pEngstate, arg0) #define swintrIsPresent(pGpu, pEngstate) swintrIsPresent_DISPATCH(pGpu, pEngstate) -void swintrRegisterIntrService_IMPL(OBJGPU *pGpu, struct SwIntr *pSwIntr, IntrServiceRecord pRecords[163]); +void swintrRegisterIntrService_IMPL(OBJGPU *pGpu, struct SwIntr *pSwIntr, IntrServiceRecord pRecords[167]); -static inline void swintrRegisterIntrService_DISPATCH(OBJGPU *pGpu, struct SwIntr *pSwIntr, IntrServiceRecord pRecords[163]) { +static inline void swintrRegisterIntrService_DISPATCH(OBJGPU *pGpu, struct SwIntr *pSwIntr, IntrServiceRecord pRecords[167]) { pSwIntr->__swintrRegisterIntrService__(pGpu, pSwIntr, pRecords); } @@ -149,10 +137,6 @@ return pSwIntr->__swintrServiceInterrupt__(pGpu, pSwIntr, pParams); } -static inline NV_STATUS swintrReconcileTunableState_DISPATCH(POBJGPU pGpu, struct SwIntr *pEngstate, void *pTunableState) { - return pEngstate->__swintrReconcileTunableState__(pGpu, pEngstate, pTunableState); -} - static inline NV_STATUS swintrStateLoad_DISPATCH(POBJGPU pGpu, struct SwIntr *pEngstate, NvU32 arg0) { return pEngstate->__swintrStateLoad__(pGpu, pEngstate, arg0); } @@ -201,18 +185,6 @@ return pEngstate->__swintrStatePreInitUnlocked__(pGpu, pEngstate); } -static inline NV_STATUS swintrGetTunableState_DISPATCH(POBJGPU pGpu, struct SwIntr *pEngstate, void *pTunableState) { - return pEngstate->__swintrGetTunableState__(pGpu, pEngstate, pTunableState); -} - -static inline NV_STATUS swintrCompareTunableState_DISPATCH(POBJGPU pGpu, struct SwIntr *pEngstate, void *pTunables1, void *pTunables2) { - return pEngstate->__swintrCompareTunableState__(pGpu, pEngstate, pTunables1, pTunables2); -} - -static inline void swintrFreeTunableState_DISPATCH(POBJGPU pGpu, struct SwIntr *pEngstate, void *pTunableState) { - pEngstate->__swintrFreeTunableState__(pGpu, pEngstate, pTunableState); -} - static inline NvBool swintrClearInterrupt_DISPATCH(OBJGPU *pGpu, struct SwIntr *pIntrService, IntrServiceClearInterruptArguments *pParams) { return pIntrService->__swintrClearInterrupt__(pGpu, pIntrService, pParams); } @@ -221,14 +193,6 @@ return pEngstate->__swintrStatePostLoad__(pGpu, pEngstate, arg0); } -static inline NV_STATUS swintrAllocTunableState_DISPATCH(POBJGPU pGpu, struct SwIntr *pEngstate, void **ppTunableState) { - return pEngstate->__swintrAllocTunableState__(pGpu, pEngstate, ppTunableState); -} - -static inline NV_STATUS swintrSetTunableState_DISPATCH(POBJGPU pGpu, struct SwIntr *pEngstate, void *pTunableState) { - return pEngstate->__swintrSetTunableState__(pGpu, pEngstate, pTunableState); -} - static inline NV_STATUS swintrConstructEngine_DISPATCH(POBJGPU pGpu, struct SwIntr *pEngstate, ENGDESCRIPTOR arg0) { return pEngstate->__swintrConstructEngine__(pGpu, pEngstate, arg0); } diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/generated/g_syncgpuboost_nvoc.c nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_syncgpuboost_nvoc.c --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/generated/g_syncgpuboost_nvoc.c 2023-10-25 20:27:20.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_syncgpuboost_nvoc.c 2024-03-05 22:18:47.000000000 +0000 @@ -116,8 +116,12 @@ resAddAdditionalDependants(pClient, (struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_SyncGpuBoost_RsResource.offset), pReference); } -static NV_STATUS __nvoc_thunk_RsResource_syncgpuboostUnmap(struct SyncGpuBoost *pResource, struct CALL_CONTEXT *pCallContext, RsCpuMapping *pCpuMapping) { - return resUnmap((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_SyncGpuBoost_RsResource.offset), pCallContext, pCpuMapping); +static NV_STATUS __nvoc_thunk_RsResource_syncgpuboostUnmapFrom(struct SyncGpuBoost *pResource, RS_RES_UNMAP_FROM_PARAMS *pParams) { + return resUnmapFrom((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_SyncGpuBoost_RsResource.offset), pParams); +} + +static NV_STATUS __nvoc_thunk_RmResource_syncgpuboostControlSerialization_Prologue(struct SyncGpuBoost *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return rmresControlSerialization_Prologue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_SyncGpuBoost_RmResource.offset), pCallContext, pParams); } static NV_STATUS __nvoc_thunk_RmResource_syncgpuboostControl_Prologue(struct SyncGpuBoost *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { @@ -128,22 +132,26 @@ return resCanCopy((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_SyncGpuBoost_RsResource.offset)); } -static NV_STATUS __nvoc_thunk_RsResource_syncgpuboostMapTo(struct SyncGpuBoost *pResource, RS_RES_MAP_TO_PARAMS *pParams) { - return resMapTo((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_SyncGpuBoost_RsResource.offset), pParams); +static NV_STATUS __nvoc_thunk_RsResource_syncgpuboostUnmap(struct SyncGpuBoost *pResource, struct CALL_CONTEXT *pCallContext, RsCpuMapping *pCpuMapping) { + return resUnmap((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_SyncGpuBoost_RsResource.offset), pCallContext, pCpuMapping); } static void __nvoc_thunk_RsResource_syncgpuboostPreDestruct(struct SyncGpuBoost *pResource) { resPreDestruct((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_SyncGpuBoost_RsResource.offset)); } -static NV_STATUS __nvoc_thunk_RsResource_syncgpuboostUnmapFrom(struct SyncGpuBoost *pResource, RS_RES_UNMAP_FROM_PARAMS *pParams) { - return resUnmapFrom((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_SyncGpuBoost_RsResource.offset), pParams); +static NV_STATUS __nvoc_thunk_RsResource_syncgpuboostMapTo(struct SyncGpuBoost *pResource, RS_RES_MAP_TO_PARAMS *pParams) { + return resMapTo((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_SyncGpuBoost_RsResource.offset), pParams); } static NV_STATUS __nvoc_thunk_RsResource_syncgpuboostIsDuplicate(struct SyncGpuBoost *pResource, NvHandle hMemory, NvBool *pDuplicate) { return resIsDuplicate((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_SyncGpuBoost_RsResource.offset), hMemory, pDuplicate); } +static void __nvoc_thunk_RmResource_syncgpuboostControlSerialization_Epilogue(struct SyncGpuBoost *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + rmresControlSerialization_Epilogue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_SyncGpuBoost_RmResource.offset), pCallContext, pParams); +} + static void __nvoc_thunk_RmResource_syncgpuboostControl_Epilogue(struct SyncGpuBoost *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { rmresControl_Epilogue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_SyncGpuBoost_RmResource.offset), pCallContext, pParams); } @@ -215,20 +223,24 @@ pThis->__syncgpuboostAddAdditionalDependants__ = &__nvoc_thunk_RsResource_syncgpuboostAddAdditionalDependants; - pThis->__syncgpuboostUnmap__ = &__nvoc_thunk_RsResource_syncgpuboostUnmap; + pThis->__syncgpuboostUnmapFrom__ = &__nvoc_thunk_RsResource_syncgpuboostUnmapFrom; + + pThis->__syncgpuboostControlSerialization_Prologue__ = &__nvoc_thunk_RmResource_syncgpuboostControlSerialization_Prologue; pThis->__syncgpuboostControl_Prologue__ = &__nvoc_thunk_RmResource_syncgpuboostControl_Prologue; pThis->__syncgpuboostCanCopy__ = &__nvoc_thunk_RsResource_syncgpuboostCanCopy; - pThis->__syncgpuboostMapTo__ = &__nvoc_thunk_RsResource_syncgpuboostMapTo; + pThis->__syncgpuboostUnmap__ = &__nvoc_thunk_RsResource_syncgpuboostUnmap; pThis->__syncgpuboostPreDestruct__ = &__nvoc_thunk_RsResource_syncgpuboostPreDestruct; - pThis->__syncgpuboostUnmapFrom__ = &__nvoc_thunk_RsResource_syncgpuboostUnmapFrom; + pThis->__syncgpuboostMapTo__ = &__nvoc_thunk_RsResource_syncgpuboostMapTo; pThis->__syncgpuboostIsDuplicate__ = &__nvoc_thunk_RsResource_syncgpuboostIsDuplicate; + pThis->__syncgpuboostControlSerialization_Epilogue__ = &__nvoc_thunk_RmResource_syncgpuboostControlSerialization_Epilogue; + pThis->__syncgpuboostControl_Epilogue__ = &__nvoc_thunk_RmResource_syncgpuboostControl_Epilogue; pThis->__syncgpuboostControlLookup__ = &__nvoc_thunk_RsResource_syncgpuboostControlLookup; @@ -258,13 +270,16 @@ Object *pParentObj; SyncGpuBoost *pThis; - pThis = portMemAllocNonPaged(sizeof(SyncGpuBoost)); - if (pThis == NULL) return NV_ERR_NO_MEMORY; + status = __nvoc_handleObjCreateMemAlloc(createFlags, sizeof(SyncGpuBoost), (void**)&pThis, (void**)ppThis); + if (status != NV_OK) + return status; portMemSet(pThis, 0, sizeof(SyncGpuBoost)); __nvoc_initRtti(staticCast(pThis, Dynamic), &__nvoc_class_def_SyncGpuBoost); + pThis->__nvoc_base_RmResource.__nvoc_base_RsResource.__nvoc_base_Object.createFlags = createFlags; + if (pParent != NULL && !(createFlags & NVOC_OBJ_CREATE_FLAGS_PARENT_HALSPEC_ONLY)) { pParentObj = dynamicCast(pParent, Object); @@ -280,11 +295,17 @@ if (status != NV_OK) goto __nvoc_objCreate_SyncGpuBoost_cleanup; *ppThis = pThis; + return NV_OK; __nvoc_objCreate_SyncGpuBoost_cleanup: // do not call destructors here since the constructor already called them - portMemFree(pThis); + if (createFlags & NVOC_OBJ_CREATE_FLAGS_IN_PLACE_CONSTRUCT) + portMemSet(pThis, 0, sizeof(SyncGpuBoost)); + else + portMemFree(pThis); + + // coverity[leaked_storage:FALSE] return status; } diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/generated/g_syncgpuboost_nvoc.h nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_syncgpuboost_nvoc.h --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/generated/g_syncgpuboost_nvoc.h 2023-10-25 20:27:20.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_syncgpuboost_nvoc.h 2024-03-05 22:18:47.000000000 +0000 @@ -60,13 +60,15 @@ NvU32 (*__syncgpuboostGetRefCount__)(struct SyncGpuBoost *); NV_STATUS (*__syncgpuboostControlFilter__)(struct SyncGpuBoost *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); void (*__syncgpuboostAddAdditionalDependants__)(struct RsClient *, struct SyncGpuBoost *, RsResourceRef *); - NV_STATUS (*__syncgpuboostUnmap__)(struct SyncGpuBoost *, struct CALL_CONTEXT *, RsCpuMapping *); + NV_STATUS (*__syncgpuboostUnmapFrom__)(struct SyncGpuBoost *, RS_RES_UNMAP_FROM_PARAMS *); + NV_STATUS (*__syncgpuboostControlSerialization_Prologue__)(struct SyncGpuBoost *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); NV_STATUS (*__syncgpuboostControl_Prologue__)(struct SyncGpuBoost *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); NvBool (*__syncgpuboostCanCopy__)(struct SyncGpuBoost *); - NV_STATUS (*__syncgpuboostMapTo__)(struct SyncGpuBoost *, RS_RES_MAP_TO_PARAMS *); + NV_STATUS (*__syncgpuboostUnmap__)(struct SyncGpuBoost *, struct CALL_CONTEXT *, RsCpuMapping *); void (*__syncgpuboostPreDestruct__)(struct SyncGpuBoost *); - NV_STATUS (*__syncgpuboostUnmapFrom__)(struct SyncGpuBoost *, RS_RES_UNMAP_FROM_PARAMS *); + NV_STATUS (*__syncgpuboostMapTo__)(struct SyncGpuBoost *, RS_RES_MAP_TO_PARAMS *); NV_STATUS (*__syncgpuboostIsDuplicate__)(struct SyncGpuBoost *, NvHandle, NvBool *); + void (*__syncgpuboostControlSerialization_Epilogue__)(struct SyncGpuBoost *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); void (*__syncgpuboostControl_Epilogue__)(struct SyncGpuBoost *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); NV_STATUS (*__syncgpuboostControlLookup__)(struct SyncGpuBoost *, struct RS_RES_CONTROL_PARAMS_INTERNAL *, const struct NVOC_EXPORTED_METHOD_DEF **); NV_STATUS (*__syncgpuboostMap__)(struct SyncGpuBoost *, struct CALL_CONTEXT *, RS_CPU_MAP_PARAMS *, RsCpuMapping *); @@ -110,13 +112,15 @@ #define syncgpuboostGetRefCount(pResource) syncgpuboostGetRefCount_DISPATCH(pResource) #define syncgpuboostControlFilter(pResource, pCallContext, pParams) syncgpuboostControlFilter_DISPATCH(pResource, pCallContext, pParams) #define syncgpuboostAddAdditionalDependants(pClient, pResource, pReference) syncgpuboostAddAdditionalDependants_DISPATCH(pClient, pResource, pReference) -#define syncgpuboostUnmap(pResource, pCallContext, pCpuMapping) syncgpuboostUnmap_DISPATCH(pResource, pCallContext, pCpuMapping) +#define syncgpuboostUnmapFrom(pResource, pParams) syncgpuboostUnmapFrom_DISPATCH(pResource, pParams) +#define syncgpuboostControlSerialization_Prologue(pResource, pCallContext, pParams) syncgpuboostControlSerialization_Prologue_DISPATCH(pResource, pCallContext, pParams) #define syncgpuboostControl_Prologue(pResource, pCallContext, pParams) syncgpuboostControl_Prologue_DISPATCH(pResource, pCallContext, pParams) #define syncgpuboostCanCopy(pResource) syncgpuboostCanCopy_DISPATCH(pResource) -#define syncgpuboostMapTo(pResource, pParams) syncgpuboostMapTo_DISPATCH(pResource, pParams) +#define syncgpuboostUnmap(pResource, pCallContext, pCpuMapping) syncgpuboostUnmap_DISPATCH(pResource, pCallContext, pCpuMapping) #define syncgpuboostPreDestruct(pResource) syncgpuboostPreDestruct_DISPATCH(pResource) -#define syncgpuboostUnmapFrom(pResource, pParams) syncgpuboostUnmapFrom_DISPATCH(pResource, pParams) +#define syncgpuboostMapTo(pResource, pParams) syncgpuboostMapTo_DISPATCH(pResource, pParams) #define syncgpuboostIsDuplicate(pResource, hMemory, pDuplicate) syncgpuboostIsDuplicate_DISPATCH(pResource, hMemory, pDuplicate) +#define syncgpuboostControlSerialization_Epilogue(pResource, pCallContext, pParams) syncgpuboostControlSerialization_Epilogue_DISPATCH(pResource, pCallContext, pParams) #define syncgpuboostControl_Epilogue(pResource, pCallContext, pParams) syncgpuboostControl_Epilogue_DISPATCH(pResource, pCallContext, pParams) #define syncgpuboostControlLookup(pResource, pParams, ppEntry) syncgpuboostControlLookup_DISPATCH(pResource, pParams, ppEntry) #define syncgpuboostMap(pResource, pCallContext, pParams, pCpuMapping) syncgpuboostMap_DISPATCH(pResource, pCallContext, pParams, pCpuMapping) @@ -153,8 +157,12 @@ pResource->__syncgpuboostAddAdditionalDependants__(pClient, pResource, pReference); } -static inline NV_STATUS syncgpuboostUnmap_DISPATCH(struct SyncGpuBoost *pResource, struct CALL_CONTEXT *pCallContext, RsCpuMapping *pCpuMapping) { - return pResource->__syncgpuboostUnmap__(pResource, pCallContext, pCpuMapping); +static inline NV_STATUS syncgpuboostUnmapFrom_DISPATCH(struct SyncGpuBoost *pResource, RS_RES_UNMAP_FROM_PARAMS *pParams) { + return pResource->__syncgpuboostUnmapFrom__(pResource, pParams); +} + +static inline NV_STATUS syncgpuboostControlSerialization_Prologue_DISPATCH(struct SyncGpuBoost *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return pResource->__syncgpuboostControlSerialization_Prologue__(pResource, pCallContext, pParams); } static inline NV_STATUS syncgpuboostControl_Prologue_DISPATCH(struct SyncGpuBoost *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { @@ -165,22 +173,26 @@ return pResource->__syncgpuboostCanCopy__(pResource); } -static inline NV_STATUS syncgpuboostMapTo_DISPATCH(struct SyncGpuBoost *pResource, RS_RES_MAP_TO_PARAMS *pParams) { - return pResource->__syncgpuboostMapTo__(pResource, pParams); +static inline NV_STATUS syncgpuboostUnmap_DISPATCH(struct SyncGpuBoost *pResource, struct CALL_CONTEXT *pCallContext, RsCpuMapping *pCpuMapping) { + return pResource->__syncgpuboostUnmap__(pResource, pCallContext, pCpuMapping); } static inline void syncgpuboostPreDestruct_DISPATCH(struct SyncGpuBoost *pResource) { pResource->__syncgpuboostPreDestruct__(pResource); } -static inline NV_STATUS syncgpuboostUnmapFrom_DISPATCH(struct SyncGpuBoost *pResource, RS_RES_UNMAP_FROM_PARAMS *pParams) { - return pResource->__syncgpuboostUnmapFrom__(pResource, pParams); +static inline NV_STATUS syncgpuboostMapTo_DISPATCH(struct SyncGpuBoost *pResource, RS_RES_MAP_TO_PARAMS *pParams) { + return pResource->__syncgpuboostMapTo__(pResource, pParams); } static inline NV_STATUS syncgpuboostIsDuplicate_DISPATCH(struct SyncGpuBoost *pResource, NvHandle hMemory, NvBool *pDuplicate) { return pResource->__syncgpuboostIsDuplicate__(pResource, hMemory, pDuplicate); } +static inline void syncgpuboostControlSerialization_Epilogue_DISPATCH(struct SyncGpuBoost *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + pResource->__syncgpuboostControlSerialization_Epilogue__(pResource, pCallContext, pParams); +} + static inline void syncgpuboostControl_Epilogue_DISPATCH(struct SyncGpuBoost *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { pResource->__syncgpuboostControl_Epilogue__(pResource, pCallContext, pParams); } diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/generated/g_system_mem_nvoc.c nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_system_mem_nvoc.c --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/generated/g_system_mem_nvoc.c 2023-10-25 20:27:20.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_system_mem_nvoc.c 2024-03-05 22:18:47.000000000 +0000 @@ -106,64 +106,80 @@ return memCheckMemInterUnmap((struct Memory *)(((unsigned char *)pMemory) + __nvoc_rtti_SystemMemory_Memory.offset), bSubdeviceHandleProvided); } -static NV_STATUS __nvoc_thunk_Memory_sysmemControl(struct SystemMemory *pMemory, CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { - return memControl((struct Memory *)(((unsigned char *)pMemory) + __nvoc_rtti_SystemMemory_Memory.offset), pCallContext, pParams); +static NvBool __nvoc_thunk_RmResource_sysmemShareCallback(struct SystemMemory *pResource, struct RsClient *pInvokingClient, struct RsResourceRef *pParentRef, RS_SHARE_POLICY *pSharePolicy) { + return rmresShareCallback((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_SystemMemory_RmResource.offset), pInvokingClient, pParentRef, pSharePolicy); } -static NV_STATUS __nvoc_thunk_Memory_sysmemUnmap(struct SystemMemory *pMemory, CALL_CONTEXT *pCallContext, RsCpuMapping *pCpuMapping) { - return memUnmap((struct Memory *)(((unsigned char *)pMemory) + __nvoc_rtti_SystemMemory_Memory.offset), pCallContext, pCpuMapping); +static NV_STATUS __nvoc_thunk_RsResource_sysmemMapTo(struct SystemMemory *pResource, RS_RES_MAP_TO_PARAMS *pParams) { + return resMapTo((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_SystemMemory_RsResource.offset), pParams); } -static NV_STATUS __nvoc_thunk_Memory_sysmemGetMemInterMapParams(struct SystemMemory *pMemory, RMRES_MEM_INTER_MAP_PARAMS *pParams) { - return memGetMemInterMapParams((struct Memory *)(((unsigned char *)pMemory) + __nvoc_rtti_SystemMemory_Memory.offset), pParams); +static NV_STATUS __nvoc_thunk_Memory_sysmemGetMapAddrSpace(struct SystemMemory *pMemory, CALL_CONTEXT *pCallContext, NvU32 mapFlags, NV_ADDRESS_SPACE *pAddrSpace) { + return memGetMapAddrSpace((struct Memory *)(((unsigned char *)pMemory) + __nvoc_rtti_SystemMemory_Memory.offset), pCallContext, mapFlags, pAddrSpace); } -static NV_STATUS __nvoc_thunk_Memory_sysmemGetMemoryMappingDescriptor(struct SystemMemory *pMemory, MEMORY_DESCRIPTOR **ppMemDesc) { - return memGetMemoryMappingDescriptor((struct Memory *)(((unsigned char *)pMemory) + __nvoc_rtti_SystemMemory_Memory.offset), ppMemDesc); +static NvU32 __nvoc_thunk_RsResource_sysmemGetRefCount(struct SystemMemory *pResource) { + return resGetRefCount((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_SystemMemory_RsResource.offset)); } -static NV_STATUS __nvoc_thunk_Memory_sysmemGetMapAddrSpace(struct SystemMemory *pMemory, CALL_CONTEXT *pCallContext, NvU32 mapFlags, NV_ADDRESS_SPACE *pAddrSpace) { - return memGetMapAddrSpace((struct Memory *)(((unsigned char *)pMemory) + __nvoc_rtti_SystemMemory_Memory.offset), pCallContext, mapFlags, pAddrSpace); +static void __nvoc_thunk_RsResource_sysmemAddAdditionalDependants(struct RsClient *pClient, struct SystemMemory *pResource, RsResourceRef *pReference) { + resAddAdditionalDependants(pClient, (struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_SystemMemory_RsResource.offset), pReference); } -static NvBool __nvoc_thunk_RmResource_sysmemShareCallback(struct SystemMemory *pResource, struct RsClient *pInvokingClient, struct RsResourceRef *pParentRef, RS_SHARE_POLICY *pSharePolicy) { - return rmresShareCallback((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_SystemMemory_RmResource.offset), pInvokingClient, pParentRef, pSharePolicy); +static NV_STATUS __nvoc_thunk_RmResource_sysmemControl_Prologue(struct SystemMemory *pResource, CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return rmresControl_Prologue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_SystemMemory_RmResource.offset), pCallContext, pParams); } -static NV_STATUS __nvoc_thunk_RsResource_sysmemControlFilter(struct SystemMemory *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { - return resControlFilter((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_SystemMemory_RsResource.offset), pCallContext, pParams); +static NvBool __nvoc_thunk_Memory_sysmemIsGpuMapAllowed(struct SystemMemory *pMemory, struct OBJGPU *pGpu) { + return memIsGpuMapAllowed((struct Memory *)(((unsigned char *)pMemory) + __nvoc_rtti_SystemMemory_Memory.offset), pGpu); } -static void __nvoc_thunk_RsResource_sysmemAddAdditionalDependants(struct RsClient *pClient, struct SystemMemory *pResource, RsResourceRef *pReference) { - resAddAdditionalDependants(pClient, (struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_SystemMemory_RsResource.offset), pReference); +static NV_STATUS __nvoc_thunk_RsResource_sysmemUnmapFrom(struct SystemMemory *pResource, RS_RES_UNMAP_FROM_PARAMS *pParams) { + return resUnmapFrom((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_SystemMemory_RsResource.offset), pParams); } -static NvU32 __nvoc_thunk_RsResource_sysmemGetRefCount(struct SystemMemory *pResource) { - return resGetRefCount((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_SystemMemory_RsResource.offset)); +static void __nvoc_thunk_RmResource_sysmemControl_Epilogue(struct SystemMemory *pResource, CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + rmresControl_Epilogue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_SystemMemory_RmResource.offset), pCallContext, pParams); } -static NV_STATUS __nvoc_thunk_RsResource_sysmemMapTo(struct SystemMemory *pResource, RS_RES_MAP_TO_PARAMS *pParams) { - return resMapTo((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_SystemMemory_RsResource.offset), pParams); +static NV_STATUS __nvoc_thunk_RsResource_sysmemControlLookup(struct SystemMemory *pResource, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams, const struct NVOC_EXPORTED_METHOD_DEF **ppEntry) { + return resControlLookup((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_SystemMemory_RsResource.offset), pParams, ppEntry); } -static NvBool __nvoc_thunk_StandardMemory_sysmemCanCopy(struct SystemMemory *pStandardMemory) { - return stdmemCanCopy((struct StandardMemory *)(((unsigned char *)pStandardMemory) + __nvoc_rtti_SystemMemory_StandardMemory.offset)); +static NV_STATUS __nvoc_thunk_Memory_sysmemControl(struct SystemMemory *pMemory, CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return memControl((struct Memory *)(((unsigned char *)pMemory) + __nvoc_rtti_SystemMemory_Memory.offset), pCallContext, pParams); } -static NvBool __nvoc_thunk_Memory_sysmemIsGpuMapAllowed(struct SystemMemory *pMemory, struct OBJGPU *pGpu) { - return memIsGpuMapAllowed((struct Memory *)(((unsigned char *)pMemory) + __nvoc_rtti_SystemMemory_Memory.offset), pGpu); +static NV_STATUS __nvoc_thunk_Memory_sysmemUnmap(struct SystemMemory *pMemory, CALL_CONTEXT *pCallContext, RsCpuMapping *pCpuMapping) { + return memUnmap((struct Memory *)(((unsigned char *)pMemory) + __nvoc_rtti_SystemMemory_Memory.offset), pCallContext, pCpuMapping); } -static NV_STATUS __nvoc_thunk_RmResource_sysmemControl_Prologue(struct SystemMemory *pResource, CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { - return rmresControl_Prologue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_SystemMemory_RmResource.offset), pCallContext, pParams); +static NV_STATUS __nvoc_thunk_Memory_sysmemGetMemInterMapParams(struct SystemMemory *pMemory, RMRES_MEM_INTER_MAP_PARAMS *pParams) { + return memGetMemInterMapParams((struct Memory *)(((unsigned char *)pMemory) + __nvoc_rtti_SystemMemory_Memory.offset), pParams); +} + +static NV_STATUS __nvoc_thunk_Memory_sysmemGetMemoryMappingDescriptor(struct SystemMemory *pMemory, MEMORY_DESCRIPTOR **ppMemDesc) { + return memGetMemoryMappingDescriptor((struct Memory *)(((unsigned char *)pMemory) + __nvoc_rtti_SystemMemory_Memory.offset), ppMemDesc); +} + +static NV_STATUS __nvoc_thunk_RsResource_sysmemControlFilter(struct SystemMemory *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return resControlFilter((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_SystemMemory_RsResource.offset), pCallContext, pParams); +} + +static NV_STATUS __nvoc_thunk_RmResource_sysmemControlSerialization_Prologue(struct SystemMemory *pResource, CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return rmresControlSerialization_Prologue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_SystemMemory_RmResource.offset), pCallContext, pParams); +} + +static NvBool __nvoc_thunk_StandardMemory_sysmemCanCopy(struct SystemMemory *pStandardMemory) { + return stdmemCanCopy((struct StandardMemory *)(((unsigned char *)pStandardMemory) + __nvoc_rtti_SystemMemory_StandardMemory.offset)); } static NV_STATUS __nvoc_thunk_Memory_sysmemIsReady(struct SystemMemory *pMemory, NvBool bCopyConstructorContext) { return memIsReady((struct Memory *)(((unsigned char *)pMemory) + __nvoc_rtti_SystemMemory_Memory.offset), bCopyConstructorContext); } -static NV_STATUS __nvoc_thunk_Memory_sysmemCheckCopyPermissions(struct SystemMemory *pMemory, struct OBJGPU *pDstGpu, NvHandle hDstClientNvBool) { - return memCheckCopyPermissions((struct Memory *)(((unsigned char *)pMemory) + __nvoc_rtti_SystemMemory_Memory.offset), pDstGpu, hDstClientNvBool); +static NV_STATUS __nvoc_thunk_Memory_sysmemCheckCopyPermissions(struct SystemMemory *pMemory, struct OBJGPU *pDstGpu, struct Device *pDstDevice) { + return memCheckCopyPermissions((struct Memory *)(((unsigned char *)pMemory) + __nvoc_rtti_SystemMemory_Memory.offset), pDstGpu, pDstDevice); } static void __nvoc_thunk_RsResource_sysmemPreDestruct(struct SystemMemory *pResource) { @@ -174,16 +190,8 @@ return memIsDuplicate((struct Memory *)(((unsigned char *)pMemory) + __nvoc_rtti_SystemMemory_Memory.offset), hMemory, pDuplicate); } -static NV_STATUS __nvoc_thunk_RsResource_sysmemUnmapFrom(struct SystemMemory *pResource, RS_RES_UNMAP_FROM_PARAMS *pParams) { - return resUnmapFrom((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_SystemMemory_RsResource.offset), pParams); -} - -static void __nvoc_thunk_RmResource_sysmemControl_Epilogue(struct SystemMemory *pResource, CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { - rmresControl_Epilogue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_SystemMemory_RmResource.offset), pCallContext, pParams); -} - -static NV_STATUS __nvoc_thunk_RsResource_sysmemControlLookup(struct SystemMemory *pResource, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams, const struct NVOC_EXPORTED_METHOD_DEF **ppEntry) { - return resControlLookup((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_SystemMemory_RsResource.offset), pParams, ppEntry); +static void __nvoc_thunk_RmResource_sysmemControlSerialization_Epilogue(struct SystemMemory *pResource, CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + rmresControlSerialization_Epilogue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_SystemMemory_RmResource.offset), pCallContext, pParams); } static NV_STATUS __nvoc_thunk_Memory_sysmemMap(struct SystemMemory *pMemory, CALL_CONTEXT *pCallContext, struct RS_CPU_MAP_PARAMS *pParams, RsCpuMapping *pCpuMapping) { @@ -281,31 +289,39 @@ pThis->__sysmemCheckMemInterUnmap__ = &__nvoc_thunk_Memory_sysmemCheckMemInterUnmap; - pThis->__sysmemControl__ = &__nvoc_thunk_Memory_sysmemControl; + pThis->__sysmemShareCallback__ = &__nvoc_thunk_RmResource_sysmemShareCallback; - pThis->__sysmemUnmap__ = &__nvoc_thunk_Memory_sysmemUnmap; + pThis->__sysmemMapTo__ = &__nvoc_thunk_RsResource_sysmemMapTo; - pThis->__sysmemGetMemInterMapParams__ = &__nvoc_thunk_Memory_sysmemGetMemInterMapParams; + pThis->__sysmemGetMapAddrSpace__ = &__nvoc_thunk_Memory_sysmemGetMapAddrSpace; - pThis->__sysmemGetMemoryMappingDescriptor__ = &__nvoc_thunk_Memory_sysmemGetMemoryMappingDescriptor; + pThis->__sysmemGetRefCount__ = &__nvoc_thunk_RsResource_sysmemGetRefCount; - pThis->__sysmemGetMapAddrSpace__ = &__nvoc_thunk_Memory_sysmemGetMapAddrSpace; + pThis->__sysmemAddAdditionalDependants__ = &__nvoc_thunk_RsResource_sysmemAddAdditionalDependants; - pThis->__sysmemShareCallback__ = &__nvoc_thunk_RmResource_sysmemShareCallback; + pThis->__sysmemControl_Prologue__ = &__nvoc_thunk_RmResource_sysmemControl_Prologue; - pThis->__sysmemControlFilter__ = &__nvoc_thunk_RsResource_sysmemControlFilter; + pThis->__sysmemIsGpuMapAllowed__ = &__nvoc_thunk_Memory_sysmemIsGpuMapAllowed; - pThis->__sysmemAddAdditionalDependants__ = &__nvoc_thunk_RsResource_sysmemAddAdditionalDependants; + pThis->__sysmemUnmapFrom__ = &__nvoc_thunk_RsResource_sysmemUnmapFrom; - pThis->__sysmemGetRefCount__ = &__nvoc_thunk_RsResource_sysmemGetRefCount; + pThis->__sysmemControl_Epilogue__ = &__nvoc_thunk_RmResource_sysmemControl_Epilogue; - pThis->__sysmemMapTo__ = &__nvoc_thunk_RsResource_sysmemMapTo; + pThis->__sysmemControlLookup__ = &__nvoc_thunk_RsResource_sysmemControlLookup; - pThis->__sysmemCanCopy__ = &__nvoc_thunk_StandardMemory_sysmemCanCopy; + pThis->__sysmemControl__ = &__nvoc_thunk_Memory_sysmemControl; - pThis->__sysmemIsGpuMapAllowed__ = &__nvoc_thunk_Memory_sysmemIsGpuMapAllowed; + pThis->__sysmemUnmap__ = &__nvoc_thunk_Memory_sysmemUnmap; - pThis->__sysmemControl_Prologue__ = &__nvoc_thunk_RmResource_sysmemControl_Prologue; + pThis->__sysmemGetMemInterMapParams__ = &__nvoc_thunk_Memory_sysmemGetMemInterMapParams; + + pThis->__sysmemGetMemoryMappingDescriptor__ = &__nvoc_thunk_Memory_sysmemGetMemoryMappingDescriptor; + + pThis->__sysmemControlFilter__ = &__nvoc_thunk_RsResource_sysmemControlFilter; + + pThis->__sysmemControlSerialization_Prologue__ = &__nvoc_thunk_RmResource_sysmemControlSerialization_Prologue; + + pThis->__sysmemCanCopy__ = &__nvoc_thunk_StandardMemory_sysmemCanCopy; pThis->__sysmemIsReady__ = &__nvoc_thunk_Memory_sysmemIsReady; @@ -315,11 +331,7 @@ pThis->__sysmemIsDuplicate__ = &__nvoc_thunk_Memory_sysmemIsDuplicate; - pThis->__sysmemUnmapFrom__ = &__nvoc_thunk_RsResource_sysmemUnmapFrom; - - pThis->__sysmemControl_Epilogue__ = &__nvoc_thunk_RmResource_sysmemControl_Epilogue; - - pThis->__sysmemControlLookup__ = &__nvoc_thunk_RsResource_sysmemControlLookup; + pThis->__sysmemControlSerialization_Epilogue__ = &__nvoc_thunk_RmResource_sysmemControlSerialization_Epilogue; pThis->__sysmemMap__ = &__nvoc_thunk_Memory_sysmemMap; @@ -348,13 +360,16 @@ Object *pParentObj; SystemMemory *pThis; - pThis = portMemAllocNonPaged(sizeof(SystemMemory)); - if (pThis == NULL) return NV_ERR_NO_MEMORY; + status = __nvoc_handleObjCreateMemAlloc(createFlags, sizeof(SystemMemory), (void**)&pThis, (void**)ppThis); + if (status != NV_OK) + return status; portMemSet(pThis, 0, sizeof(SystemMemory)); __nvoc_initRtti(staticCast(pThis, Dynamic), &__nvoc_class_def_SystemMemory); + pThis->__nvoc_base_StandardMemory.__nvoc_base_Memory.__nvoc_base_RmResource.__nvoc_base_RsResource.__nvoc_base_Object.createFlags = createFlags; + if (pParent != NULL && !(createFlags & NVOC_OBJ_CREATE_FLAGS_PARENT_HALSPEC_ONLY)) { pParentObj = dynamicCast(pParent, Object); @@ -370,11 +385,17 @@ if (status != NV_OK) goto __nvoc_objCreate_SystemMemory_cleanup; *ppThis = pThis; + return NV_OK; __nvoc_objCreate_SystemMemory_cleanup: // do not call destructors here since the constructor already called them - portMemFree(pThis); + if (createFlags & NVOC_OBJ_CREATE_FLAGS_IN_PLACE_CONSTRUCT) + portMemSet(pThis, 0, sizeof(SystemMemory)); + else + portMemFree(pThis); + + // coverity[leaked_storage:FALSE] return status; } diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/generated/g_system_mem_nvoc.h nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_system_mem_nvoc.h --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/generated/g_system_mem_nvoc.h 2023-10-25 20:27:20.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_system_mem_nvoc.h 2024-03-05 22:18:47.000000000 +0000 @@ -55,26 +55,28 @@ NV_STATUS (*__sysmemCtrlCmdGetSurfaceNumPhysPages__)(struct SystemMemory *, NV003E_CTRL_GET_SURFACE_NUM_PHYS_PAGES_PARAMS *); NV_STATUS (*__sysmemCtrlCmdGetSurfacePhysPages__)(struct SystemMemory *, NV003E_CTRL_GET_SURFACE_PHYS_PAGES_PARAMS *); NV_STATUS (*__sysmemCheckMemInterUnmap__)(struct SystemMemory *, NvBool); + NvBool (*__sysmemShareCallback__)(struct SystemMemory *, struct RsClient *, struct RsResourceRef *, RS_SHARE_POLICY *); + NV_STATUS (*__sysmemMapTo__)(struct SystemMemory *, RS_RES_MAP_TO_PARAMS *); + NV_STATUS (*__sysmemGetMapAddrSpace__)(struct SystemMemory *, CALL_CONTEXT *, NvU32, NV_ADDRESS_SPACE *); + NvU32 (*__sysmemGetRefCount__)(struct SystemMemory *); + void (*__sysmemAddAdditionalDependants__)(struct RsClient *, struct SystemMemory *, RsResourceRef *); + NV_STATUS (*__sysmemControl_Prologue__)(struct SystemMemory *, CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); + NvBool (*__sysmemIsGpuMapAllowed__)(struct SystemMemory *, struct OBJGPU *); + NV_STATUS (*__sysmemUnmapFrom__)(struct SystemMemory *, RS_RES_UNMAP_FROM_PARAMS *); + void (*__sysmemControl_Epilogue__)(struct SystemMemory *, CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); + NV_STATUS (*__sysmemControlLookup__)(struct SystemMemory *, struct RS_RES_CONTROL_PARAMS_INTERNAL *, const struct NVOC_EXPORTED_METHOD_DEF **); NV_STATUS (*__sysmemControl__)(struct SystemMemory *, CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); NV_STATUS (*__sysmemUnmap__)(struct SystemMemory *, CALL_CONTEXT *, RsCpuMapping *); NV_STATUS (*__sysmemGetMemInterMapParams__)(struct SystemMemory *, RMRES_MEM_INTER_MAP_PARAMS *); NV_STATUS (*__sysmemGetMemoryMappingDescriptor__)(struct SystemMemory *, MEMORY_DESCRIPTOR **); - NV_STATUS (*__sysmemGetMapAddrSpace__)(struct SystemMemory *, CALL_CONTEXT *, NvU32, NV_ADDRESS_SPACE *); - NvBool (*__sysmemShareCallback__)(struct SystemMemory *, struct RsClient *, struct RsResourceRef *, RS_SHARE_POLICY *); NV_STATUS (*__sysmemControlFilter__)(struct SystemMemory *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); - void (*__sysmemAddAdditionalDependants__)(struct RsClient *, struct SystemMemory *, RsResourceRef *); - NvU32 (*__sysmemGetRefCount__)(struct SystemMemory *); - NV_STATUS (*__sysmemMapTo__)(struct SystemMemory *, RS_RES_MAP_TO_PARAMS *); + NV_STATUS (*__sysmemControlSerialization_Prologue__)(struct SystemMemory *, CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); NvBool (*__sysmemCanCopy__)(struct SystemMemory *); - NvBool (*__sysmemIsGpuMapAllowed__)(struct SystemMemory *, struct OBJGPU *); - NV_STATUS (*__sysmemControl_Prologue__)(struct SystemMemory *, CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); NV_STATUS (*__sysmemIsReady__)(struct SystemMemory *, NvBool); - NV_STATUS (*__sysmemCheckCopyPermissions__)(struct SystemMemory *, struct OBJGPU *, NvHandle); + NV_STATUS (*__sysmemCheckCopyPermissions__)(struct SystemMemory *, struct OBJGPU *, struct Device *); void (*__sysmemPreDestruct__)(struct SystemMemory *); NV_STATUS (*__sysmemIsDuplicate__)(struct SystemMemory *, NvHandle, NvBool *); - NV_STATUS (*__sysmemUnmapFrom__)(struct SystemMemory *, RS_RES_UNMAP_FROM_PARAMS *); - void (*__sysmemControl_Epilogue__)(struct SystemMemory *, CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); - NV_STATUS (*__sysmemControlLookup__)(struct SystemMemory *, struct RS_RES_CONTROL_PARAMS_INTERNAL *, const struct NVOC_EXPORTED_METHOD_DEF **); + void (*__sysmemControlSerialization_Epilogue__)(struct SystemMemory *, CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); NV_STATUS (*__sysmemMap__)(struct SystemMemory *, CALL_CONTEXT *, struct RS_CPU_MAP_PARAMS *, RsCpuMapping *); NvBool (*__sysmemAccessCallback__)(struct SystemMemory *, struct RsClient *, void *, RsAccessRight); }; @@ -110,26 +112,28 @@ #define sysmemCtrlCmdGetSurfaceNumPhysPages(pStandardMemory, pParams) sysmemCtrlCmdGetSurfaceNumPhysPages_DISPATCH(pStandardMemory, pParams) #define sysmemCtrlCmdGetSurfacePhysPages(pStandardMemory, pParams) sysmemCtrlCmdGetSurfacePhysPages_DISPATCH(pStandardMemory, pParams) #define sysmemCheckMemInterUnmap(pMemory, bSubdeviceHandleProvided) sysmemCheckMemInterUnmap_DISPATCH(pMemory, bSubdeviceHandleProvided) +#define sysmemShareCallback(pResource, pInvokingClient, pParentRef, pSharePolicy) sysmemShareCallback_DISPATCH(pResource, pInvokingClient, pParentRef, pSharePolicy) +#define sysmemMapTo(pResource, pParams) sysmemMapTo_DISPATCH(pResource, pParams) +#define sysmemGetMapAddrSpace(pMemory, pCallContext, mapFlags, pAddrSpace) sysmemGetMapAddrSpace_DISPATCH(pMemory, pCallContext, mapFlags, pAddrSpace) +#define sysmemGetRefCount(pResource) sysmemGetRefCount_DISPATCH(pResource) +#define sysmemAddAdditionalDependants(pClient, pResource, pReference) sysmemAddAdditionalDependants_DISPATCH(pClient, pResource, pReference) +#define sysmemControl_Prologue(pResource, pCallContext, pParams) sysmemControl_Prologue_DISPATCH(pResource, pCallContext, pParams) +#define sysmemIsGpuMapAllowed(pMemory, pGpu) sysmemIsGpuMapAllowed_DISPATCH(pMemory, pGpu) +#define sysmemUnmapFrom(pResource, pParams) sysmemUnmapFrom_DISPATCH(pResource, pParams) +#define sysmemControl_Epilogue(pResource, pCallContext, pParams) sysmemControl_Epilogue_DISPATCH(pResource, pCallContext, pParams) +#define sysmemControlLookup(pResource, pParams, ppEntry) sysmemControlLookup_DISPATCH(pResource, pParams, ppEntry) #define sysmemControl(pMemory, pCallContext, pParams) sysmemControl_DISPATCH(pMemory, pCallContext, pParams) #define sysmemUnmap(pMemory, pCallContext, pCpuMapping) sysmemUnmap_DISPATCH(pMemory, pCallContext, pCpuMapping) #define sysmemGetMemInterMapParams(pMemory, pParams) sysmemGetMemInterMapParams_DISPATCH(pMemory, pParams) #define sysmemGetMemoryMappingDescriptor(pMemory, ppMemDesc) sysmemGetMemoryMappingDescriptor_DISPATCH(pMemory, ppMemDesc) -#define sysmemGetMapAddrSpace(pMemory, pCallContext, mapFlags, pAddrSpace) sysmemGetMapAddrSpace_DISPATCH(pMemory, pCallContext, mapFlags, pAddrSpace) -#define sysmemShareCallback(pResource, pInvokingClient, pParentRef, pSharePolicy) sysmemShareCallback_DISPATCH(pResource, pInvokingClient, pParentRef, pSharePolicy) #define sysmemControlFilter(pResource, pCallContext, pParams) sysmemControlFilter_DISPATCH(pResource, pCallContext, pParams) -#define sysmemAddAdditionalDependants(pClient, pResource, pReference) sysmemAddAdditionalDependants_DISPATCH(pClient, pResource, pReference) -#define sysmemGetRefCount(pResource) sysmemGetRefCount_DISPATCH(pResource) -#define sysmemMapTo(pResource, pParams) sysmemMapTo_DISPATCH(pResource, pParams) +#define sysmemControlSerialization_Prologue(pResource, pCallContext, pParams) sysmemControlSerialization_Prologue_DISPATCH(pResource, pCallContext, pParams) #define sysmemCanCopy(pStandardMemory) sysmemCanCopy_DISPATCH(pStandardMemory) -#define sysmemIsGpuMapAllowed(pMemory, pGpu) sysmemIsGpuMapAllowed_DISPATCH(pMemory, pGpu) -#define sysmemControl_Prologue(pResource, pCallContext, pParams) sysmemControl_Prologue_DISPATCH(pResource, pCallContext, pParams) #define sysmemIsReady(pMemory, bCopyConstructorContext) sysmemIsReady_DISPATCH(pMemory, bCopyConstructorContext) -#define sysmemCheckCopyPermissions(pMemory, pDstGpu, hDstClientNvBool) sysmemCheckCopyPermissions_DISPATCH(pMemory, pDstGpu, hDstClientNvBool) +#define sysmemCheckCopyPermissions(pMemory, pDstGpu, pDstDevice) sysmemCheckCopyPermissions_DISPATCH(pMemory, pDstGpu, pDstDevice) #define sysmemPreDestruct(pResource) sysmemPreDestruct_DISPATCH(pResource) #define sysmemIsDuplicate(pMemory, hMemory, pDuplicate) sysmemIsDuplicate_DISPATCH(pMemory, hMemory, pDuplicate) -#define sysmemUnmapFrom(pResource, pParams) sysmemUnmapFrom_DISPATCH(pResource, pParams) -#define sysmemControl_Epilogue(pResource, pCallContext, pParams) sysmemControl_Epilogue_DISPATCH(pResource, pCallContext, pParams) -#define sysmemControlLookup(pResource, pParams, ppEntry) sysmemControlLookup_DISPATCH(pResource, pParams, ppEntry) +#define sysmemControlSerialization_Epilogue(pResource, pCallContext, pParams) sysmemControlSerialization_Epilogue_DISPATCH(pResource, pCallContext, pParams) #define sysmemMap(pMemory, pCallContext, pParams, pCpuMapping) sysmemMap_DISPATCH(pMemory, pCallContext, pParams, pCpuMapping) #define sysmemAccessCallback(pResource, pInvokingClient, pAllocParams, accessRight) sysmemAccessCallback_DISPATCH(pResource, pInvokingClient, pAllocParams, accessRight) NV_STATUS sysmemInitAllocRequest_HMM(struct OBJGPU *pGpu, struct SystemMemory *pSystemMemory, MEMORY_ALLOCATION_REQUEST *pAllocRequest); @@ -162,64 +166,80 @@ return pMemory->__sysmemCheckMemInterUnmap__(pMemory, bSubdeviceHandleProvided); } -static inline NV_STATUS sysmemControl_DISPATCH(struct SystemMemory *pMemory, CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { - return pMemory->__sysmemControl__(pMemory, pCallContext, pParams); +static inline NvBool sysmemShareCallback_DISPATCH(struct SystemMemory *pResource, struct RsClient *pInvokingClient, struct RsResourceRef *pParentRef, RS_SHARE_POLICY *pSharePolicy) { + return pResource->__sysmemShareCallback__(pResource, pInvokingClient, pParentRef, pSharePolicy); } -static inline NV_STATUS sysmemUnmap_DISPATCH(struct SystemMemory *pMemory, CALL_CONTEXT *pCallContext, RsCpuMapping *pCpuMapping) { - return pMemory->__sysmemUnmap__(pMemory, pCallContext, pCpuMapping); +static inline NV_STATUS sysmemMapTo_DISPATCH(struct SystemMemory *pResource, RS_RES_MAP_TO_PARAMS *pParams) { + return pResource->__sysmemMapTo__(pResource, pParams); } -static inline NV_STATUS sysmemGetMemInterMapParams_DISPATCH(struct SystemMemory *pMemory, RMRES_MEM_INTER_MAP_PARAMS *pParams) { - return pMemory->__sysmemGetMemInterMapParams__(pMemory, pParams); +static inline NV_STATUS sysmemGetMapAddrSpace_DISPATCH(struct SystemMemory *pMemory, CALL_CONTEXT *pCallContext, NvU32 mapFlags, NV_ADDRESS_SPACE *pAddrSpace) { + return pMemory->__sysmemGetMapAddrSpace__(pMemory, pCallContext, mapFlags, pAddrSpace); } -static inline NV_STATUS sysmemGetMemoryMappingDescriptor_DISPATCH(struct SystemMemory *pMemory, MEMORY_DESCRIPTOR **ppMemDesc) { - return pMemory->__sysmemGetMemoryMappingDescriptor__(pMemory, ppMemDesc); +static inline NvU32 sysmemGetRefCount_DISPATCH(struct SystemMemory *pResource) { + return pResource->__sysmemGetRefCount__(pResource); } -static inline NV_STATUS sysmemGetMapAddrSpace_DISPATCH(struct SystemMemory *pMemory, CALL_CONTEXT *pCallContext, NvU32 mapFlags, NV_ADDRESS_SPACE *pAddrSpace) { - return pMemory->__sysmemGetMapAddrSpace__(pMemory, pCallContext, mapFlags, pAddrSpace); +static inline void sysmemAddAdditionalDependants_DISPATCH(struct RsClient *pClient, struct SystemMemory *pResource, RsResourceRef *pReference) { + pResource->__sysmemAddAdditionalDependants__(pClient, pResource, pReference); } -static inline NvBool sysmemShareCallback_DISPATCH(struct SystemMemory *pResource, struct RsClient *pInvokingClient, struct RsResourceRef *pParentRef, RS_SHARE_POLICY *pSharePolicy) { - return pResource->__sysmemShareCallback__(pResource, pInvokingClient, pParentRef, pSharePolicy); +static inline NV_STATUS sysmemControl_Prologue_DISPATCH(struct SystemMemory *pResource, CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return pResource->__sysmemControl_Prologue__(pResource, pCallContext, pParams); } -static inline NV_STATUS sysmemControlFilter_DISPATCH(struct SystemMemory *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { - return pResource->__sysmemControlFilter__(pResource, pCallContext, pParams); +static inline NvBool sysmemIsGpuMapAllowed_DISPATCH(struct SystemMemory *pMemory, struct OBJGPU *pGpu) { + return pMemory->__sysmemIsGpuMapAllowed__(pMemory, pGpu); } -static inline void sysmemAddAdditionalDependants_DISPATCH(struct RsClient *pClient, struct SystemMemory *pResource, RsResourceRef *pReference) { - pResource->__sysmemAddAdditionalDependants__(pClient, pResource, pReference); +static inline NV_STATUS sysmemUnmapFrom_DISPATCH(struct SystemMemory *pResource, RS_RES_UNMAP_FROM_PARAMS *pParams) { + return pResource->__sysmemUnmapFrom__(pResource, pParams); } -static inline NvU32 sysmemGetRefCount_DISPATCH(struct SystemMemory *pResource) { - return pResource->__sysmemGetRefCount__(pResource); +static inline void sysmemControl_Epilogue_DISPATCH(struct SystemMemory *pResource, CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + pResource->__sysmemControl_Epilogue__(pResource, pCallContext, pParams); } -static inline NV_STATUS sysmemMapTo_DISPATCH(struct SystemMemory *pResource, RS_RES_MAP_TO_PARAMS *pParams) { - return pResource->__sysmemMapTo__(pResource, pParams); +static inline NV_STATUS sysmemControlLookup_DISPATCH(struct SystemMemory *pResource, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams, const struct NVOC_EXPORTED_METHOD_DEF **ppEntry) { + return pResource->__sysmemControlLookup__(pResource, pParams, ppEntry); } -static inline NvBool sysmemCanCopy_DISPATCH(struct SystemMemory *pStandardMemory) { - return pStandardMemory->__sysmemCanCopy__(pStandardMemory); +static inline NV_STATUS sysmemControl_DISPATCH(struct SystemMemory *pMemory, CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return pMemory->__sysmemControl__(pMemory, pCallContext, pParams); } -static inline NvBool sysmemIsGpuMapAllowed_DISPATCH(struct SystemMemory *pMemory, struct OBJGPU *pGpu) { - return pMemory->__sysmemIsGpuMapAllowed__(pMemory, pGpu); +static inline NV_STATUS sysmemUnmap_DISPATCH(struct SystemMemory *pMemory, CALL_CONTEXT *pCallContext, RsCpuMapping *pCpuMapping) { + return pMemory->__sysmemUnmap__(pMemory, pCallContext, pCpuMapping); } -static inline NV_STATUS sysmemControl_Prologue_DISPATCH(struct SystemMemory *pResource, CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { - return pResource->__sysmemControl_Prologue__(pResource, pCallContext, pParams); +static inline NV_STATUS sysmemGetMemInterMapParams_DISPATCH(struct SystemMemory *pMemory, RMRES_MEM_INTER_MAP_PARAMS *pParams) { + return pMemory->__sysmemGetMemInterMapParams__(pMemory, pParams); +} + +static inline NV_STATUS sysmemGetMemoryMappingDescriptor_DISPATCH(struct SystemMemory *pMemory, MEMORY_DESCRIPTOR **ppMemDesc) { + return pMemory->__sysmemGetMemoryMappingDescriptor__(pMemory, ppMemDesc); +} + +static inline NV_STATUS sysmemControlFilter_DISPATCH(struct SystemMemory *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return pResource->__sysmemControlFilter__(pResource, pCallContext, pParams); +} + +static inline NV_STATUS sysmemControlSerialization_Prologue_DISPATCH(struct SystemMemory *pResource, CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return pResource->__sysmemControlSerialization_Prologue__(pResource, pCallContext, pParams); +} + +static inline NvBool sysmemCanCopy_DISPATCH(struct SystemMemory *pStandardMemory) { + return pStandardMemory->__sysmemCanCopy__(pStandardMemory); } static inline NV_STATUS sysmemIsReady_DISPATCH(struct SystemMemory *pMemory, NvBool bCopyConstructorContext) { return pMemory->__sysmemIsReady__(pMemory, bCopyConstructorContext); } -static inline NV_STATUS sysmemCheckCopyPermissions_DISPATCH(struct SystemMemory *pMemory, struct OBJGPU *pDstGpu, NvHandle hDstClientNvBool) { - return pMemory->__sysmemCheckCopyPermissions__(pMemory, pDstGpu, hDstClientNvBool); +static inline NV_STATUS sysmemCheckCopyPermissions_DISPATCH(struct SystemMemory *pMemory, struct OBJGPU *pDstGpu, struct Device *pDstDevice) { + return pMemory->__sysmemCheckCopyPermissions__(pMemory, pDstGpu, pDstDevice); } static inline void sysmemPreDestruct_DISPATCH(struct SystemMemory *pResource) { @@ -230,16 +250,8 @@ return pMemory->__sysmemIsDuplicate__(pMemory, hMemory, pDuplicate); } -static inline NV_STATUS sysmemUnmapFrom_DISPATCH(struct SystemMemory *pResource, RS_RES_UNMAP_FROM_PARAMS *pParams) { - return pResource->__sysmemUnmapFrom__(pResource, pParams); -} - -static inline void sysmemControl_Epilogue_DISPATCH(struct SystemMemory *pResource, CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { - pResource->__sysmemControl_Epilogue__(pResource, pCallContext, pParams); -} - -static inline NV_STATUS sysmemControlLookup_DISPATCH(struct SystemMemory *pResource, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams, const struct NVOC_EXPORTED_METHOD_DEF **ppEntry) { - return pResource->__sysmemControlLookup__(pResource, pParams, ppEntry); +static inline void sysmemControlSerialization_Epilogue_DISPATCH(struct SystemMemory *pResource, CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + pResource->__sysmemControlSerialization_Epilogue__(pResource, pCallContext, pParams); } static inline NV_STATUS sysmemMap_DISPATCH(struct SystemMemory *pMemory, CALL_CONTEXT *pCallContext, struct RS_CPU_MAP_PARAMS *pParams, RsCpuMapping *pCpuMapping) { diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/generated/g_system_nvoc.c nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_system_nvoc.c --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/generated/g_system_nvoc.c 2023-10-25 20:27:20.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_system_nvoc.c 2024-03-05 22:18:47.000000000 +0000 @@ -90,8 +90,12 @@ pThis->setProperty(pThis, PDB_PROP_SYS_IS_AGGRESSIVE_GC6_ENABLED, (0)); pThis->setProperty(pThis, PDB_PROP_SYS_PRIORITY_BOOST, (0)); pThis->setProperty(pThis, PDB_PROP_SYS_PRIORITY_THROTTLE_DELAY_US, 16 * 1000); - pThis->setProperty(pThis, PDB_PROP_SYS_CLIENT_HANDLE_LOOKUP, ((NvBool)(0 != 0))); + pThis->setProperty(pThis, PDB_PROP_SYS_CLIENT_HANDLE_LOOKUP, ((NvBool)(0 == 0))); pThis->setProperty(pThis, PDB_PROP_SYS_ROUTE_TO_PHYSICAL_LOCK_BYPASS, ((NvBool)(0 == 0))); + + pThis->bUseDeferredClientListFree = ((NvBool)(0 != 0)); + + pThis->clientListDeferredFreeLimit = 0; } NV_STATUS __nvoc_ctor_Object(Object* ); @@ -144,13 +148,16 @@ Object *pParentObj; OBJSYS *pThis; - pThis = portMemAllocNonPaged(sizeof(OBJSYS)); - if (pThis == NULL) return NV_ERR_NO_MEMORY; + status = __nvoc_handleObjCreateMemAlloc(createFlags, sizeof(OBJSYS), (void**)&pThis, (void**)ppThis); + if (status != NV_OK) + return status; portMemSet(pThis, 0, sizeof(OBJSYS)); __nvoc_initRtti(staticCast(pThis, Dynamic), &__nvoc_class_def_OBJSYS); + pThis->__nvoc_base_Object.createFlags = createFlags; + if (pParent != NULL && !(createFlags & NVOC_OBJ_CREATE_FLAGS_PARENT_HALSPEC_ONLY)) { pParentObj = dynamicCast(pParent, Object); @@ -166,11 +173,17 @@ if (status != NV_OK) goto __nvoc_objCreate_OBJSYS_cleanup; *ppThis = pThis; + return NV_OK; __nvoc_objCreate_OBJSYS_cleanup: // do not call destructors here since the constructor already called them - portMemFree(pThis); + if (createFlags & NVOC_OBJ_CREATE_FLAGS_IN_PLACE_CONSTRUCT) + portMemSet(pThis, 0, sizeof(OBJSYS)); + else + portMemFree(pThis); + + // coverity[leaked_storage:FALSE] return status; } diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/generated/g_system_nvoc.h nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_system_nvoc.h --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/generated/g_system_nvoc.h 2023-10-25 20:27:21.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_system_nvoc.h 2024-03-05 22:18:47.000000000 +0000 @@ -315,14 +315,14 @@ /*! Indicates the type of OS flavor */ NvU32 osType; - /*! AMD SEV (AMD's Secure Encrypted Virtualization) Status */ - NvU32 osSevStatus; + /*! Indicates confidentail compute OS support is enabled or not */ + NvBool bOsCCEnabled; - /*! Indicates AMD SEV is enabled or not */ - NvBool bOsSevEnabled; + /*! Indicates Intel TDX confidentail compute OS support is enabled or not */ + NvBool bOsCCTdxEnabled; } SYS_STATIC_CONFIG; -typedef enum +typedef enum { CPU_VENDOR_UNKNOWN = 0, CPU_VENDOR_INTEL, @@ -342,7 +342,7 @@ NvU32 l1DataCacheSize; // L1 data (or unified) cache size (KB) NvU32 l2DataCacheSize; // L2 data (or unified) cache size (KB) NvU32 dataCacheLineSize; // Bytes per line in the L1 data cache - NvU32 hostPageSize; // Native host os page size (4k/64k/etc) + NvU64 hostPageSize; // Native host os page size (4k/64k/etc) NvU32 numPhysicalCpus; // Number of physical cpus NvU32 numLogicalCpus; // Total number of logical cpus NvU32 maxLogicalCpus; // Max Number of Cores on the System @@ -412,7 +412,6 @@ NvU32 gpuLockModuleMask; NvBool PDB_PROP_SYS_ROUTE_TO_PHYSICAL_LOCK_BYPASS; NvU32 pwrTransitionTimeoutOverride; - NvBool bMulticastFlaEnabled; SYS_STATIC_CONFIG staticConfig; NvU32 debugFlags; NvU32 backtraceStackDepth; @@ -426,6 +425,8 @@ NvBool PDB_PROP_SYS_IS_QSYNC_FW_REVISION_CHECK_DISABLED; NvU64 rmInstanceId; NvU32 currentCid; + NvBool bUseDeferredClientListFree; + NvU32 clientListDeferredFreeLimit; OS_RM_CAPS *pOsRmCaps; struct OBJGPUMGR *pGpuMgr; struct OBJGSYNCMGR *pGsyncMgr; diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/generated/g_third_party_p2p_nvoc.c nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_third_party_p2p_nvoc.c --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/generated/g_third_party_p2p_nvoc.c 2023-10-25 20:27:21.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_third_party_p2p_nvoc.c 2024-03-05 22:18:47.000000000 +0000 @@ -124,13 +124,16 @@ Object *pParentObj; P2PTokenShare *pThis; - pThis = portMemAllocNonPaged(sizeof(P2PTokenShare)); - if (pThis == NULL) return NV_ERR_NO_MEMORY; + status = __nvoc_handleObjCreateMemAlloc(createFlags, sizeof(P2PTokenShare), (void**)&pThis, (void**)ppThis); + if (status != NV_OK) + return status; portMemSet(pThis, 0, sizeof(P2PTokenShare)); __nvoc_initRtti(staticCast(pThis, Dynamic), &__nvoc_class_def_P2PTokenShare); + pThis->__nvoc_base_RsShared.__nvoc_base_Object.createFlags = createFlags; + if (pParent != NULL && !(createFlags & NVOC_OBJ_CREATE_FLAGS_PARENT_HALSPEC_ONLY)) { pParentObj = dynamicCast(pParent, Object); @@ -146,11 +149,17 @@ if (status != NV_OK) goto __nvoc_objCreate_P2PTokenShare_cleanup; *ppThis = pThis; + return NV_OK; __nvoc_objCreate_P2PTokenShare_cleanup: // do not call destructors here since the constructor already called them - portMemFree(pThis); + if (createFlags & NVOC_OBJ_CREATE_FLAGS_IN_PLACE_CONSTRUCT) + portMemSet(pThis, 0, sizeof(P2PTokenShare)); + else + portMemFree(pThis); + + // coverity[leaked_storage:FALSE] return status; } @@ -252,84 +261,92 @@ return gpuresShareCallback((struct GpuResource *)(((unsigned char *)pGpuResource) + __nvoc_rtti_ThirdPartyP2P_GpuResource.offset), pInvokingClient, pParentRef, pSharePolicy); } -static NV_STATUS __nvoc_thunk_GpuResource_thirdpartyp2pControl(struct ThirdPartyP2P *pGpuResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { - return gpuresControl((struct GpuResource *)(((unsigned char *)pGpuResource) + __nvoc_rtti_ThirdPartyP2P_GpuResource.offset), pCallContext, pParams); +static NV_STATUS __nvoc_thunk_RmResource_thirdpartyp2pCheckMemInterUnmap(struct ThirdPartyP2P *pRmResource, NvBool bSubdeviceHandleProvided) { + return rmresCheckMemInterUnmap((struct RmResource *)(((unsigned char *)pRmResource) + __nvoc_rtti_ThirdPartyP2P_RmResource.offset), bSubdeviceHandleProvided); } -static NV_STATUS __nvoc_thunk_GpuResource_thirdpartyp2pUnmap(struct ThirdPartyP2P *pGpuResource, struct CALL_CONTEXT *pCallContext, struct RsCpuMapping *pCpuMapping) { - return gpuresUnmap((struct GpuResource *)(((unsigned char *)pGpuResource) + __nvoc_rtti_ThirdPartyP2P_GpuResource.offset), pCallContext, pCpuMapping); +static NV_STATUS __nvoc_thunk_RsResource_thirdpartyp2pMapTo(struct ThirdPartyP2P *pResource, RS_RES_MAP_TO_PARAMS *pParams) { + return resMapTo((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_ThirdPartyP2P_RsResource.offset), pParams); } -static NV_STATUS __nvoc_thunk_RmResource_thirdpartyp2pGetMemInterMapParams(struct ThirdPartyP2P *pRmResource, RMRES_MEM_INTER_MAP_PARAMS *pParams) { - return rmresGetMemInterMapParams((struct RmResource *)(((unsigned char *)pRmResource) + __nvoc_rtti_ThirdPartyP2P_RmResource.offset), pParams); +static NV_STATUS __nvoc_thunk_GpuResource_thirdpartyp2pGetMapAddrSpace(struct ThirdPartyP2P *pGpuResource, struct CALL_CONTEXT *pCallContext, NvU32 mapFlags, NV_ADDRESS_SPACE *pAddrSpace) { + return gpuresGetMapAddrSpace((struct GpuResource *)(((unsigned char *)pGpuResource) + __nvoc_rtti_ThirdPartyP2P_GpuResource.offset), pCallContext, mapFlags, pAddrSpace); } -static NV_STATUS __nvoc_thunk_RmResource_thirdpartyp2pGetMemoryMappingDescriptor(struct ThirdPartyP2P *pRmResource, struct MEMORY_DESCRIPTOR **ppMemDesc) { - return rmresGetMemoryMappingDescriptor((struct RmResource *)(((unsigned char *)pRmResource) + __nvoc_rtti_ThirdPartyP2P_RmResource.offset), ppMemDesc); +static NvU32 __nvoc_thunk_RsResource_thirdpartyp2pGetRefCount(struct ThirdPartyP2P *pResource) { + return resGetRefCount((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_ThirdPartyP2P_RsResource.offset)); } -static NV_STATUS __nvoc_thunk_GpuResource_thirdpartyp2pGetMapAddrSpace(struct ThirdPartyP2P *pGpuResource, struct CALL_CONTEXT *pCallContext, NvU32 mapFlags, NV_ADDRESS_SPACE *pAddrSpace) { - return gpuresGetMapAddrSpace((struct GpuResource *)(((unsigned char *)pGpuResource) + __nvoc_rtti_ThirdPartyP2P_GpuResource.offset), pCallContext, mapFlags, pAddrSpace); +static void __nvoc_thunk_RsResource_thirdpartyp2pAddAdditionalDependants(struct RsClient *pClient, struct ThirdPartyP2P *pResource, RsResourceRef *pReference) { + resAddAdditionalDependants(pClient, (struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_ThirdPartyP2P_RsResource.offset), pReference); } -static NvHandle __nvoc_thunk_GpuResource_thirdpartyp2pGetInternalObjectHandle(struct ThirdPartyP2P *pGpuResource) { - return gpuresGetInternalObjectHandle((struct GpuResource *)(((unsigned char *)pGpuResource) + __nvoc_rtti_ThirdPartyP2P_GpuResource.offset)); +static NV_STATUS __nvoc_thunk_RmResource_thirdpartyp2pControl_Prologue(struct ThirdPartyP2P *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return rmresControl_Prologue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_ThirdPartyP2P_RmResource.offset), pCallContext, pParams); } -static NV_STATUS __nvoc_thunk_RsResource_thirdpartyp2pControlFilter(struct ThirdPartyP2P *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { - return resControlFilter((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_ThirdPartyP2P_RsResource.offset), pCallContext, pParams); +static NV_STATUS __nvoc_thunk_GpuResource_thirdpartyp2pGetRegBaseOffsetAndSize(struct ThirdPartyP2P *pGpuResource, struct OBJGPU *pGpu, NvU32 *pOffset, NvU32 *pSize) { + return gpuresGetRegBaseOffsetAndSize((struct GpuResource *)(((unsigned char *)pGpuResource) + __nvoc_rtti_ThirdPartyP2P_GpuResource.offset), pGpu, pOffset, pSize); } -static void __nvoc_thunk_RsResource_thirdpartyp2pAddAdditionalDependants(struct RsClient *pClient, struct ThirdPartyP2P *pResource, RsResourceRef *pReference) { - resAddAdditionalDependants(pClient, (struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_ThirdPartyP2P_RsResource.offset), pReference); +static NV_STATUS __nvoc_thunk_GpuResource_thirdpartyp2pInternalControlForward(struct ThirdPartyP2P *pGpuResource, NvU32 command, void *pParams, NvU32 size) { + return gpuresInternalControlForward((struct GpuResource *)(((unsigned char *)pGpuResource) + __nvoc_rtti_ThirdPartyP2P_GpuResource.offset), command, pParams, size); } -static NvU32 __nvoc_thunk_RsResource_thirdpartyp2pGetRefCount(struct ThirdPartyP2P *pResource) { - return resGetRefCount((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_ThirdPartyP2P_RsResource.offset)); +static NV_STATUS __nvoc_thunk_RsResource_thirdpartyp2pUnmapFrom(struct ThirdPartyP2P *pResource, RS_RES_UNMAP_FROM_PARAMS *pParams) { + return resUnmapFrom((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_ThirdPartyP2P_RsResource.offset), pParams); } -static NV_STATUS __nvoc_thunk_RmResource_thirdpartyp2pCheckMemInterUnmap(struct ThirdPartyP2P *pRmResource, NvBool bSubdeviceHandleProvided) { - return rmresCheckMemInterUnmap((struct RmResource *)(((unsigned char *)pRmResource) + __nvoc_rtti_ThirdPartyP2P_RmResource.offset), bSubdeviceHandleProvided); +static void __nvoc_thunk_RmResource_thirdpartyp2pControl_Epilogue(struct ThirdPartyP2P *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + rmresControl_Epilogue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_ThirdPartyP2P_RmResource.offset), pCallContext, pParams); } -static NV_STATUS __nvoc_thunk_RsResource_thirdpartyp2pMapTo(struct ThirdPartyP2P *pResource, RS_RES_MAP_TO_PARAMS *pParams) { - return resMapTo((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_ThirdPartyP2P_RsResource.offset), pParams); +static NV_STATUS __nvoc_thunk_RsResource_thirdpartyp2pControlLookup(struct ThirdPartyP2P *pResource, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams, const struct NVOC_EXPORTED_METHOD_DEF **ppEntry) { + return resControlLookup((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_ThirdPartyP2P_RsResource.offset), pParams, ppEntry); } -static NV_STATUS __nvoc_thunk_RmResource_thirdpartyp2pControl_Prologue(struct ThirdPartyP2P *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { - return rmresControl_Prologue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_ThirdPartyP2P_RmResource.offset), pCallContext, pParams); +static NvHandle __nvoc_thunk_GpuResource_thirdpartyp2pGetInternalObjectHandle(struct ThirdPartyP2P *pGpuResource) { + return gpuresGetInternalObjectHandle((struct GpuResource *)(((unsigned char *)pGpuResource) + __nvoc_rtti_ThirdPartyP2P_GpuResource.offset)); } -static NV_STATUS __nvoc_thunk_GpuResource_thirdpartyp2pGetRegBaseOffsetAndSize(struct ThirdPartyP2P *pGpuResource, struct OBJGPU *pGpu, NvU32 *pOffset, NvU32 *pSize) { - return gpuresGetRegBaseOffsetAndSize((struct GpuResource *)(((unsigned char *)pGpuResource) + __nvoc_rtti_ThirdPartyP2P_GpuResource.offset), pGpu, pOffset, pSize); +static NV_STATUS __nvoc_thunk_GpuResource_thirdpartyp2pControl(struct ThirdPartyP2P *pGpuResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return gpuresControl((struct GpuResource *)(((unsigned char *)pGpuResource) + __nvoc_rtti_ThirdPartyP2P_GpuResource.offset), pCallContext, pParams); } -static NvBool __nvoc_thunk_RsResource_thirdpartyp2pCanCopy(struct ThirdPartyP2P *pResource) { - return resCanCopy((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_ThirdPartyP2P_RsResource.offset)); +static NV_STATUS __nvoc_thunk_GpuResource_thirdpartyp2pUnmap(struct ThirdPartyP2P *pGpuResource, struct CALL_CONTEXT *pCallContext, struct RsCpuMapping *pCpuMapping) { + return gpuresUnmap((struct GpuResource *)(((unsigned char *)pGpuResource) + __nvoc_rtti_ThirdPartyP2P_GpuResource.offset), pCallContext, pCpuMapping); } -static NV_STATUS __nvoc_thunk_GpuResource_thirdpartyp2pInternalControlForward(struct ThirdPartyP2P *pGpuResource, NvU32 command, void *pParams, NvU32 size) { - return gpuresInternalControlForward((struct GpuResource *)(((unsigned char *)pGpuResource) + __nvoc_rtti_ThirdPartyP2P_GpuResource.offset), command, pParams, size); +static NV_STATUS __nvoc_thunk_RmResource_thirdpartyp2pGetMemInterMapParams(struct ThirdPartyP2P *pRmResource, RMRES_MEM_INTER_MAP_PARAMS *pParams) { + return rmresGetMemInterMapParams((struct RmResource *)(((unsigned char *)pRmResource) + __nvoc_rtti_ThirdPartyP2P_RmResource.offset), pParams); } -static void __nvoc_thunk_RsResource_thirdpartyp2pPreDestruct(struct ThirdPartyP2P *pResource) { - resPreDestruct((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_ThirdPartyP2P_RsResource.offset)); +static NV_STATUS __nvoc_thunk_RmResource_thirdpartyp2pGetMemoryMappingDescriptor(struct ThirdPartyP2P *pRmResource, struct MEMORY_DESCRIPTOR **ppMemDesc) { + return rmresGetMemoryMappingDescriptor((struct RmResource *)(((unsigned char *)pRmResource) + __nvoc_rtti_ThirdPartyP2P_RmResource.offset), ppMemDesc); } -static NV_STATUS __nvoc_thunk_RsResource_thirdpartyp2pUnmapFrom(struct ThirdPartyP2P *pResource, RS_RES_UNMAP_FROM_PARAMS *pParams) { - return resUnmapFrom((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_ThirdPartyP2P_RsResource.offset), pParams); +static NV_STATUS __nvoc_thunk_RsResource_thirdpartyp2pControlFilter(struct ThirdPartyP2P *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return resControlFilter((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_ThirdPartyP2P_RsResource.offset), pCallContext, pParams); } -static NV_STATUS __nvoc_thunk_RsResource_thirdpartyp2pIsDuplicate(struct ThirdPartyP2P *pResource, NvHandle hMemory, NvBool *pDuplicate) { - return resIsDuplicate((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_ThirdPartyP2P_RsResource.offset), hMemory, pDuplicate); +static NV_STATUS __nvoc_thunk_RmResource_thirdpartyp2pControlSerialization_Prologue(struct ThirdPartyP2P *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return rmresControlSerialization_Prologue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_ThirdPartyP2P_RmResource.offset), pCallContext, pParams); } -static void __nvoc_thunk_RmResource_thirdpartyp2pControl_Epilogue(struct ThirdPartyP2P *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { - rmresControl_Epilogue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_ThirdPartyP2P_RmResource.offset), pCallContext, pParams); +static NvBool __nvoc_thunk_RsResource_thirdpartyp2pCanCopy(struct ThirdPartyP2P *pResource) { + return resCanCopy((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_ThirdPartyP2P_RsResource.offset)); } -static NV_STATUS __nvoc_thunk_RsResource_thirdpartyp2pControlLookup(struct ThirdPartyP2P *pResource, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams, const struct NVOC_EXPORTED_METHOD_DEF **ppEntry) { - return resControlLookup((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_ThirdPartyP2P_RsResource.offset), pParams, ppEntry); +static void __nvoc_thunk_RsResource_thirdpartyp2pPreDestruct(struct ThirdPartyP2P *pResource) { + resPreDestruct((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_ThirdPartyP2P_RsResource.offset)); +} + +static NV_STATUS __nvoc_thunk_RsResource_thirdpartyp2pIsDuplicate(struct ThirdPartyP2P *pResource, NvHandle hMemory, NvBool *pDuplicate) { + return resIsDuplicate((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_ThirdPartyP2P_RsResource.offset), hMemory, pDuplicate); +} + +static void __nvoc_thunk_RmResource_thirdpartyp2pControlSerialization_Epilogue(struct ThirdPartyP2P *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + rmresControlSerialization_Epilogue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_ThirdPartyP2P_RmResource.offset), pCallContext, pParams); } static NV_STATUS __nvoc_thunk_GpuResource_thirdpartyp2pMap(struct ThirdPartyP2P *pGpuResource, struct CALL_CONTEXT *pCallContext, struct RS_CPU_MAP_PARAMS *pParams, struct RsCpuMapping *pCpuMapping) { @@ -485,45 +502,49 @@ pThis->__thirdpartyp2pShareCallback__ = &__nvoc_thunk_GpuResource_thirdpartyp2pShareCallback; - pThis->__thirdpartyp2pControl__ = &__nvoc_thunk_GpuResource_thirdpartyp2pControl; + pThis->__thirdpartyp2pCheckMemInterUnmap__ = &__nvoc_thunk_RmResource_thirdpartyp2pCheckMemInterUnmap; - pThis->__thirdpartyp2pUnmap__ = &__nvoc_thunk_GpuResource_thirdpartyp2pUnmap; + pThis->__thirdpartyp2pMapTo__ = &__nvoc_thunk_RsResource_thirdpartyp2pMapTo; - pThis->__thirdpartyp2pGetMemInterMapParams__ = &__nvoc_thunk_RmResource_thirdpartyp2pGetMemInterMapParams; + pThis->__thirdpartyp2pGetMapAddrSpace__ = &__nvoc_thunk_GpuResource_thirdpartyp2pGetMapAddrSpace; - pThis->__thirdpartyp2pGetMemoryMappingDescriptor__ = &__nvoc_thunk_RmResource_thirdpartyp2pGetMemoryMappingDescriptor; + pThis->__thirdpartyp2pGetRefCount__ = &__nvoc_thunk_RsResource_thirdpartyp2pGetRefCount; - pThis->__thirdpartyp2pGetMapAddrSpace__ = &__nvoc_thunk_GpuResource_thirdpartyp2pGetMapAddrSpace; + pThis->__thirdpartyp2pAddAdditionalDependants__ = &__nvoc_thunk_RsResource_thirdpartyp2pAddAdditionalDependants; - pThis->__thirdpartyp2pGetInternalObjectHandle__ = &__nvoc_thunk_GpuResource_thirdpartyp2pGetInternalObjectHandle; + pThis->__thirdpartyp2pControl_Prologue__ = &__nvoc_thunk_RmResource_thirdpartyp2pControl_Prologue; - pThis->__thirdpartyp2pControlFilter__ = &__nvoc_thunk_RsResource_thirdpartyp2pControlFilter; + pThis->__thirdpartyp2pGetRegBaseOffsetAndSize__ = &__nvoc_thunk_GpuResource_thirdpartyp2pGetRegBaseOffsetAndSize; - pThis->__thirdpartyp2pAddAdditionalDependants__ = &__nvoc_thunk_RsResource_thirdpartyp2pAddAdditionalDependants; + pThis->__thirdpartyp2pInternalControlForward__ = &__nvoc_thunk_GpuResource_thirdpartyp2pInternalControlForward; - pThis->__thirdpartyp2pGetRefCount__ = &__nvoc_thunk_RsResource_thirdpartyp2pGetRefCount; + pThis->__thirdpartyp2pUnmapFrom__ = &__nvoc_thunk_RsResource_thirdpartyp2pUnmapFrom; - pThis->__thirdpartyp2pCheckMemInterUnmap__ = &__nvoc_thunk_RmResource_thirdpartyp2pCheckMemInterUnmap; + pThis->__thirdpartyp2pControl_Epilogue__ = &__nvoc_thunk_RmResource_thirdpartyp2pControl_Epilogue; - pThis->__thirdpartyp2pMapTo__ = &__nvoc_thunk_RsResource_thirdpartyp2pMapTo; + pThis->__thirdpartyp2pControlLookup__ = &__nvoc_thunk_RsResource_thirdpartyp2pControlLookup; - pThis->__thirdpartyp2pControl_Prologue__ = &__nvoc_thunk_RmResource_thirdpartyp2pControl_Prologue; + pThis->__thirdpartyp2pGetInternalObjectHandle__ = &__nvoc_thunk_GpuResource_thirdpartyp2pGetInternalObjectHandle; - pThis->__thirdpartyp2pGetRegBaseOffsetAndSize__ = &__nvoc_thunk_GpuResource_thirdpartyp2pGetRegBaseOffsetAndSize; + pThis->__thirdpartyp2pControl__ = &__nvoc_thunk_GpuResource_thirdpartyp2pControl; - pThis->__thirdpartyp2pCanCopy__ = &__nvoc_thunk_RsResource_thirdpartyp2pCanCopy; + pThis->__thirdpartyp2pUnmap__ = &__nvoc_thunk_GpuResource_thirdpartyp2pUnmap; - pThis->__thirdpartyp2pInternalControlForward__ = &__nvoc_thunk_GpuResource_thirdpartyp2pInternalControlForward; + pThis->__thirdpartyp2pGetMemInterMapParams__ = &__nvoc_thunk_RmResource_thirdpartyp2pGetMemInterMapParams; - pThis->__thirdpartyp2pPreDestruct__ = &__nvoc_thunk_RsResource_thirdpartyp2pPreDestruct; + pThis->__thirdpartyp2pGetMemoryMappingDescriptor__ = &__nvoc_thunk_RmResource_thirdpartyp2pGetMemoryMappingDescriptor; - pThis->__thirdpartyp2pUnmapFrom__ = &__nvoc_thunk_RsResource_thirdpartyp2pUnmapFrom; + pThis->__thirdpartyp2pControlFilter__ = &__nvoc_thunk_RsResource_thirdpartyp2pControlFilter; - pThis->__thirdpartyp2pIsDuplicate__ = &__nvoc_thunk_RsResource_thirdpartyp2pIsDuplicate; + pThis->__thirdpartyp2pControlSerialization_Prologue__ = &__nvoc_thunk_RmResource_thirdpartyp2pControlSerialization_Prologue; - pThis->__thirdpartyp2pControl_Epilogue__ = &__nvoc_thunk_RmResource_thirdpartyp2pControl_Epilogue; + pThis->__thirdpartyp2pCanCopy__ = &__nvoc_thunk_RsResource_thirdpartyp2pCanCopy; - pThis->__thirdpartyp2pControlLookup__ = &__nvoc_thunk_RsResource_thirdpartyp2pControlLookup; + pThis->__thirdpartyp2pPreDestruct__ = &__nvoc_thunk_RsResource_thirdpartyp2pPreDestruct; + + pThis->__thirdpartyp2pIsDuplicate__ = &__nvoc_thunk_RsResource_thirdpartyp2pIsDuplicate; + + pThis->__thirdpartyp2pControlSerialization_Epilogue__ = &__nvoc_thunk_RmResource_thirdpartyp2pControlSerialization_Epilogue; pThis->__thirdpartyp2pMap__ = &__nvoc_thunk_GpuResource_thirdpartyp2pMap; @@ -551,13 +572,16 @@ Object *pParentObj; ThirdPartyP2P *pThis; - pThis = portMemAllocNonPaged(sizeof(ThirdPartyP2P)); - if (pThis == NULL) return NV_ERR_NO_MEMORY; + status = __nvoc_handleObjCreateMemAlloc(createFlags, sizeof(ThirdPartyP2P), (void**)&pThis, (void**)ppThis); + if (status != NV_OK) + return status; portMemSet(pThis, 0, sizeof(ThirdPartyP2P)); __nvoc_initRtti(staticCast(pThis, Dynamic), &__nvoc_class_def_ThirdPartyP2P); + pThis->__nvoc_base_GpuResource.__nvoc_base_RmResource.__nvoc_base_RsResource.__nvoc_base_Object.createFlags = createFlags; + if (pParent != NULL && !(createFlags & NVOC_OBJ_CREATE_FLAGS_PARENT_HALSPEC_ONLY)) { pParentObj = dynamicCast(pParent, Object); @@ -573,11 +597,17 @@ if (status != NV_OK) goto __nvoc_objCreate_ThirdPartyP2P_cleanup; *ppThis = pThis; + return NV_OK; __nvoc_objCreate_ThirdPartyP2P_cleanup: // do not call destructors here since the constructor already called them - portMemFree(pThis); + if (createFlags & NVOC_OBJ_CREATE_FLAGS_IN_PLACE_CONSTRUCT) + portMemSet(pThis, 0, sizeof(ThirdPartyP2P)); + else + portMemFree(pThis); + + // coverity[leaked_storage:FALSE] return status; } diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/generated/g_third_party_p2p_nvoc.h nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_third_party_p2p_nvoc.h --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/generated/g_third_party_p2p_nvoc.h 2023-10-25 20:27:21.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_third_party_p2p_nvoc.h 2024-03-05 22:18:48.000000000 +0000 @@ -262,26 +262,28 @@ NV_STATUS (*__thirdpartyp2pCtrlCmdUnregisterVidmem__)(struct ThirdPartyP2P *, NV503C_CTRL_UNREGISTER_VIDMEM_PARAMS *); NV_STATUS (*__thirdpartyp2pCtrlCmdRegisterPid__)(struct ThirdPartyP2P *, NV503C_CTRL_REGISTER_PID_PARAMS *); NvBool (*__thirdpartyp2pShareCallback__)(struct ThirdPartyP2P *, struct RsClient *, struct RsResourceRef *, RS_SHARE_POLICY *); - NV_STATUS (*__thirdpartyp2pControl__)(struct ThirdPartyP2P *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); - NV_STATUS (*__thirdpartyp2pUnmap__)(struct ThirdPartyP2P *, struct CALL_CONTEXT *, struct RsCpuMapping *); - NV_STATUS (*__thirdpartyp2pGetMemInterMapParams__)(struct ThirdPartyP2P *, RMRES_MEM_INTER_MAP_PARAMS *); - NV_STATUS (*__thirdpartyp2pGetMemoryMappingDescriptor__)(struct ThirdPartyP2P *, struct MEMORY_DESCRIPTOR **); - NV_STATUS (*__thirdpartyp2pGetMapAddrSpace__)(struct ThirdPartyP2P *, struct CALL_CONTEXT *, NvU32, NV_ADDRESS_SPACE *); - NvHandle (*__thirdpartyp2pGetInternalObjectHandle__)(struct ThirdPartyP2P *); - NV_STATUS (*__thirdpartyp2pControlFilter__)(struct ThirdPartyP2P *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); - void (*__thirdpartyp2pAddAdditionalDependants__)(struct RsClient *, struct ThirdPartyP2P *, RsResourceRef *); - NvU32 (*__thirdpartyp2pGetRefCount__)(struct ThirdPartyP2P *); NV_STATUS (*__thirdpartyp2pCheckMemInterUnmap__)(struct ThirdPartyP2P *, NvBool); NV_STATUS (*__thirdpartyp2pMapTo__)(struct ThirdPartyP2P *, RS_RES_MAP_TO_PARAMS *); + NV_STATUS (*__thirdpartyp2pGetMapAddrSpace__)(struct ThirdPartyP2P *, struct CALL_CONTEXT *, NvU32, NV_ADDRESS_SPACE *); + NvU32 (*__thirdpartyp2pGetRefCount__)(struct ThirdPartyP2P *); + void (*__thirdpartyp2pAddAdditionalDependants__)(struct RsClient *, struct ThirdPartyP2P *, RsResourceRef *); NV_STATUS (*__thirdpartyp2pControl_Prologue__)(struct ThirdPartyP2P *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); NV_STATUS (*__thirdpartyp2pGetRegBaseOffsetAndSize__)(struct ThirdPartyP2P *, struct OBJGPU *, NvU32 *, NvU32 *); - NvBool (*__thirdpartyp2pCanCopy__)(struct ThirdPartyP2P *); NV_STATUS (*__thirdpartyp2pInternalControlForward__)(struct ThirdPartyP2P *, NvU32, void *, NvU32); - void (*__thirdpartyp2pPreDestruct__)(struct ThirdPartyP2P *); NV_STATUS (*__thirdpartyp2pUnmapFrom__)(struct ThirdPartyP2P *, RS_RES_UNMAP_FROM_PARAMS *); - NV_STATUS (*__thirdpartyp2pIsDuplicate__)(struct ThirdPartyP2P *, NvHandle, NvBool *); void (*__thirdpartyp2pControl_Epilogue__)(struct ThirdPartyP2P *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); NV_STATUS (*__thirdpartyp2pControlLookup__)(struct ThirdPartyP2P *, struct RS_RES_CONTROL_PARAMS_INTERNAL *, const struct NVOC_EXPORTED_METHOD_DEF **); + NvHandle (*__thirdpartyp2pGetInternalObjectHandle__)(struct ThirdPartyP2P *); + NV_STATUS (*__thirdpartyp2pControl__)(struct ThirdPartyP2P *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); + NV_STATUS (*__thirdpartyp2pUnmap__)(struct ThirdPartyP2P *, struct CALL_CONTEXT *, struct RsCpuMapping *); + NV_STATUS (*__thirdpartyp2pGetMemInterMapParams__)(struct ThirdPartyP2P *, RMRES_MEM_INTER_MAP_PARAMS *); + NV_STATUS (*__thirdpartyp2pGetMemoryMappingDescriptor__)(struct ThirdPartyP2P *, struct MEMORY_DESCRIPTOR **); + NV_STATUS (*__thirdpartyp2pControlFilter__)(struct ThirdPartyP2P *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); + NV_STATUS (*__thirdpartyp2pControlSerialization_Prologue__)(struct ThirdPartyP2P *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); + NvBool (*__thirdpartyp2pCanCopy__)(struct ThirdPartyP2P *); + void (*__thirdpartyp2pPreDestruct__)(struct ThirdPartyP2P *); + NV_STATUS (*__thirdpartyp2pIsDuplicate__)(struct ThirdPartyP2P *, NvHandle, NvBool *); + void (*__thirdpartyp2pControlSerialization_Epilogue__)(struct ThirdPartyP2P *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); NV_STATUS (*__thirdpartyp2pMap__)(struct ThirdPartyP2P *, struct CALL_CONTEXT *, struct RS_CPU_MAP_PARAMS *, struct RsCpuMapping *); NvBool (*__thirdpartyp2pAccessCallback__)(struct ThirdPartyP2P *, struct RsClient *, void *, RsAccessRight); NODE Node; @@ -335,26 +337,28 @@ #define thirdpartyp2pCtrlCmdUnregisterVidmem(pThirdPartyP2P, pUnregisterVidmemParams) thirdpartyp2pCtrlCmdUnregisterVidmem_DISPATCH(pThirdPartyP2P, pUnregisterVidmemParams) #define thirdpartyp2pCtrlCmdRegisterPid(pThirdPartyP2P, pParams) thirdpartyp2pCtrlCmdRegisterPid_DISPATCH(pThirdPartyP2P, pParams) #define thirdpartyp2pShareCallback(pGpuResource, pInvokingClient, pParentRef, pSharePolicy) thirdpartyp2pShareCallback_DISPATCH(pGpuResource, pInvokingClient, pParentRef, pSharePolicy) -#define thirdpartyp2pControl(pGpuResource, pCallContext, pParams) thirdpartyp2pControl_DISPATCH(pGpuResource, pCallContext, pParams) -#define thirdpartyp2pUnmap(pGpuResource, pCallContext, pCpuMapping) thirdpartyp2pUnmap_DISPATCH(pGpuResource, pCallContext, pCpuMapping) -#define thirdpartyp2pGetMemInterMapParams(pRmResource, pParams) thirdpartyp2pGetMemInterMapParams_DISPATCH(pRmResource, pParams) -#define thirdpartyp2pGetMemoryMappingDescriptor(pRmResource, ppMemDesc) thirdpartyp2pGetMemoryMappingDescriptor_DISPATCH(pRmResource, ppMemDesc) -#define thirdpartyp2pGetMapAddrSpace(pGpuResource, pCallContext, mapFlags, pAddrSpace) thirdpartyp2pGetMapAddrSpace_DISPATCH(pGpuResource, pCallContext, mapFlags, pAddrSpace) -#define thirdpartyp2pGetInternalObjectHandle(pGpuResource) thirdpartyp2pGetInternalObjectHandle_DISPATCH(pGpuResource) -#define thirdpartyp2pControlFilter(pResource, pCallContext, pParams) thirdpartyp2pControlFilter_DISPATCH(pResource, pCallContext, pParams) -#define thirdpartyp2pAddAdditionalDependants(pClient, pResource, pReference) thirdpartyp2pAddAdditionalDependants_DISPATCH(pClient, pResource, pReference) -#define thirdpartyp2pGetRefCount(pResource) thirdpartyp2pGetRefCount_DISPATCH(pResource) #define thirdpartyp2pCheckMemInterUnmap(pRmResource, bSubdeviceHandleProvided) thirdpartyp2pCheckMemInterUnmap_DISPATCH(pRmResource, bSubdeviceHandleProvided) #define thirdpartyp2pMapTo(pResource, pParams) thirdpartyp2pMapTo_DISPATCH(pResource, pParams) +#define thirdpartyp2pGetMapAddrSpace(pGpuResource, pCallContext, mapFlags, pAddrSpace) thirdpartyp2pGetMapAddrSpace_DISPATCH(pGpuResource, pCallContext, mapFlags, pAddrSpace) +#define thirdpartyp2pGetRefCount(pResource) thirdpartyp2pGetRefCount_DISPATCH(pResource) +#define thirdpartyp2pAddAdditionalDependants(pClient, pResource, pReference) thirdpartyp2pAddAdditionalDependants_DISPATCH(pClient, pResource, pReference) #define thirdpartyp2pControl_Prologue(pResource, pCallContext, pParams) thirdpartyp2pControl_Prologue_DISPATCH(pResource, pCallContext, pParams) #define thirdpartyp2pGetRegBaseOffsetAndSize(pGpuResource, pGpu, pOffset, pSize) thirdpartyp2pGetRegBaseOffsetAndSize_DISPATCH(pGpuResource, pGpu, pOffset, pSize) -#define thirdpartyp2pCanCopy(pResource) thirdpartyp2pCanCopy_DISPATCH(pResource) #define thirdpartyp2pInternalControlForward(pGpuResource, command, pParams, size) thirdpartyp2pInternalControlForward_DISPATCH(pGpuResource, command, pParams, size) -#define thirdpartyp2pPreDestruct(pResource) thirdpartyp2pPreDestruct_DISPATCH(pResource) #define thirdpartyp2pUnmapFrom(pResource, pParams) thirdpartyp2pUnmapFrom_DISPATCH(pResource, pParams) -#define thirdpartyp2pIsDuplicate(pResource, hMemory, pDuplicate) thirdpartyp2pIsDuplicate_DISPATCH(pResource, hMemory, pDuplicate) #define thirdpartyp2pControl_Epilogue(pResource, pCallContext, pParams) thirdpartyp2pControl_Epilogue_DISPATCH(pResource, pCallContext, pParams) #define thirdpartyp2pControlLookup(pResource, pParams, ppEntry) thirdpartyp2pControlLookup_DISPATCH(pResource, pParams, ppEntry) +#define thirdpartyp2pGetInternalObjectHandle(pGpuResource) thirdpartyp2pGetInternalObjectHandle_DISPATCH(pGpuResource) +#define thirdpartyp2pControl(pGpuResource, pCallContext, pParams) thirdpartyp2pControl_DISPATCH(pGpuResource, pCallContext, pParams) +#define thirdpartyp2pUnmap(pGpuResource, pCallContext, pCpuMapping) thirdpartyp2pUnmap_DISPATCH(pGpuResource, pCallContext, pCpuMapping) +#define thirdpartyp2pGetMemInterMapParams(pRmResource, pParams) thirdpartyp2pGetMemInterMapParams_DISPATCH(pRmResource, pParams) +#define thirdpartyp2pGetMemoryMappingDescriptor(pRmResource, ppMemDesc) thirdpartyp2pGetMemoryMappingDescriptor_DISPATCH(pRmResource, ppMemDesc) +#define thirdpartyp2pControlFilter(pResource, pCallContext, pParams) thirdpartyp2pControlFilter_DISPATCH(pResource, pCallContext, pParams) +#define thirdpartyp2pControlSerialization_Prologue(pResource, pCallContext, pParams) thirdpartyp2pControlSerialization_Prologue_DISPATCH(pResource, pCallContext, pParams) +#define thirdpartyp2pCanCopy(pResource) thirdpartyp2pCanCopy_DISPATCH(pResource) +#define thirdpartyp2pPreDestruct(pResource) thirdpartyp2pPreDestruct_DISPATCH(pResource) +#define thirdpartyp2pIsDuplicate(pResource, hMemory, pDuplicate) thirdpartyp2pIsDuplicate_DISPATCH(pResource, hMemory, pDuplicate) +#define thirdpartyp2pControlSerialization_Epilogue(pResource, pCallContext, pParams) thirdpartyp2pControlSerialization_Epilogue_DISPATCH(pResource, pCallContext, pParams) #define thirdpartyp2pMap(pGpuResource, pCallContext, pParams, pCpuMapping) thirdpartyp2pMap_DISPATCH(pGpuResource, pCallContext, pParams, pCpuMapping) #define thirdpartyp2pAccessCallback(pResource, pInvokingClient, pAllocParams, accessRight) thirdpartyp2pAccessCallback_DISPATCH(pResource, pInvokingClient, pAllocParams, accessRight) NV_STATUS thirdpartyp2pCtrlCmdRegisterVaSpace_IMPL(struct ThirdPartyP2P *pThirdPartyP2P, NV503C_CTRL_REGISTER_VA_SPACE_PARAMS *pRegisterVaSpaceParams); @@ -391,84 +395,92 @@ return pGpuResource->__thirdpartyp2pShareCallback__(pGpuResource, pInvokingClient, pParentRef, pSharePolicy); } -static inline NV_STATUS thirdpartyp2pControl_DISPATCH(struct ThirdPartyP2P *pGpuResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { - return pGpuResource->__thirdpartyp2pControl__(pGpuResource, pCallContext, pParams); +static inline NV_STATUS thirdpartyp2pCheckMemInterUnmap_DISPATCH(struct ThirdPartyP2P *pRmResource, NvBool bSubdeviceHandleProvided) { + return pRmResource->__thirdpartyp2pCheckMemInterUnmap__(pRmResource, bSubdeviceHandleProvided); } -static inline NV_STATUS thirdpartyp2pUnmap_DISPATCH(struct ThirdPartyP2P *pGpuResource, struct CALL_CONTEXT *pCallContext, struct RsCpuMapping *pCpuMapping) { - return pGpuResource->__thirdpartyp2pUnmap__(pGpuResource, pCallContext, pCpuMapping); +static inline NV_STATUS thirdpartyp2pMapTo_DISPATCH(struct ThirdPartyP2P *pResource, RS_RES_MAP_TO_PARAMS *pParams) { + return pResource->__thirdpartyp2pMapTo__(pResource, pParams); } -static inline NV_STATUS thirdpartyp2pGetMemInterMapParams_DISPATCH(struct ThirdPartyP2P *pRmResource, RMRES_MEM_INTER_MAP_PARAMS *pParams) { - return pRmResource->__thirdpartyp2pGetMemInterMapParams__(pRmResource, pParams); +static inline NV_STATUS thirdpartyp2pGetMapAddrSpace_DISPATCH(struct ThirdPartyP2P *pGpuResource, struct CALL_CONTEXT *pCallContext, NvU32 mapFlags, NV_ADDRESS_SPACE *pAddrSpace) { + return pGpuResource->__thirdpartyp2pGetMapAddrSpace__(pGpuResource, pCallContext, mapFlags, pAddrSpace); } -static inline NV_STATUS thirdpartyp2pGetMemoryMappingDescriptor_DISPATCH(struct ThirdPartyP2P *pRmResource, struct MEMORY_DESCRIPTOR **ppMemDesc) { - return pRmResource->__thirdpartyp2pGetMemoryMappingDescriptor__(pRmResource, ppMemDesc); +static inline NvU32 thirdpartyp2pGetRefCount_DISPATCH(struct ThirdPartyP2P *pResource) { + return pResource->__thirdpartyp2pGetRefCount__(pResource); } -static inline NV_STATUS thirdpartyp2pGetMapAddrSpace_DISPATCH(struct ThirdPartyP2P *pGpuResource, struct CALL_CONTEXT *pCallContext, NvU32 mapFlags, NV_ADDRESS_SPACE *pAddrSpace) { - return pGpuResource->__thirdpartyp2pGetMapAddrSpace__(pGpuResource, pCallContext, mapFlags, pAddrSpace); +static inline void thirdpartyp2pAddAdditionalDependants_DISPATCH(struct RsClient *pClient, struct ThirdPartyP2P *pResource, RsResourceRef *pReference) { + pResource->__thirdpartyp2pAddAdditionalDependants__(pClient, pResource, pReference); } -static inline NvHandle thirdpartyp2pGetInternalObjectHandle_DISPATCH(struct ThirdPartyP2P *pGpuResource) { - return pGpuResource->__thirdpartyp2pGetInternalObjectHandle__(pGpuResource); +static inline NV_STATUS thirdpartyp2pControl_Prologue_DISPATCH(struct ThirdPartyP2P *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return pResource->__thirdpartyp2pControl_Prologue__(pResource, pCallContext, pParams); } -static inline NV_STATUS thirdpartyp2pControlFilter_DISPATCH(struct ThirdPartyP2P *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { - return pResource->__thirdpartyp2pControlFilter__(pResource, pCallContext, pParams); +static inline NV_STATUS thirdpartyp2pGetRegBaseOffsetAndSize_DISPATCH(struct ThirdPartyP2P *pGpuResource, struct OBJGPU *pGpu, NvU32 *pOffset, NvU32 *pSize) { + return pGpuResource->__thirdpartyp2pGetRegBaseOffsetAndSize__(pGpuResource, pGpu, pOffset, pSize); } -static inline void thirdpartyp2pAddAdditionalDependants_DISPATCH(struct RsClient *pClient, struct ThirdPartyP2P *pResource, RsResourceRef *pReference) { - pResource->__thirdpartyp2pAddAdditionalDependants__(pClient, pResource, pReference); +static inline NV_STATUS thirdpartyp2pInternalControlForward_DISPATCH(struct ThirdPartyP2P *pGpuResource, NvU32 command, void *pParams, NvU32 size) { + return pGpuResource->__thirdpartyp2pInternalControlForward__(pGpuResource, command, pParams, size); } -static inline NvU32 thirdpartyp2pGetRefCount_DISPATCH(struct ThirdPartyP2P *pResource) { - return pResource->__thirdpartyp2pGetRefCount__(pResource); +static inline NV_STATUS thirdpartyp2pUnmapFrom_DISPATCH(struct ThirdPartyP2P *pResource, RS_RES_UNMAP_FROM_PARAMS *pParams) { + return pResource->__thirdpartyp2pUnmapFrom__(pResource, pParams); } -static inline NV_STATUS thirdpartyp2pCheckMemInterUnmap_DISPATCH(struct ThirdPartyP2P *pRmResource, NvBool bSubdeviceHandleProvided) { - return pRmResource->__thirdpartyp2pCheckMemInterUnmap__(pRmResource, bSubdeviceHandleProvided); +static inline void thirdpartyp2pControl_Epilogue_DISPATCH(struct ThirdPartyP2P *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + pResource->__thirdpartyp2pControl_Epilogue__(pResource, pCallContext, pParams); } -static inline NV_STATUS thirdpartyp2pMapTo_DISPATCH(struct ThirdPartyP2P *pResource, RS_RES_MAP_TO_PARAMS *pParams) { - return pResource->__thirdpartyp2pMapTo__(pResource, pParams); +static inline NV_STATUS thirdpartyp2pControlLookup_DISPATCH(struct ThirdPartyP2P *pResource, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams, const struct NVOC_EXPORTED_METHOD_DEF **ppEntry) { + return pResource->__thirdpartyp2pControlLookup__(pResource, pParams, ppEntry); } -static inline NV_STATUS thirdpartyp2pControl_Prologue_DISPATCH(struct ThirdPartyP2P *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { - return pResource->__thirdpartyp2pControl_Prologue__(pResource, pCallContext, pParams); +static inline NvHandle thirdpartyp2pGetInternalObjectHandle_DISPATCH(struct ThirdPartyP2P *pGpuResource) { + return pGpuResource->__thirdpartyp2pGetInternalObjectHandle__(pGpuResource); } -static inline NV_STATUS thirdpartyp2pGetRegBaseOffsetAndSize_DISPATCH(struct ThirdPartyP2P *pGpuResource, struct OBJGPU *pGpu, NvU32 *pOffset, NvU32 *pSize) { - return pGpuResource->__thirdpartyp2pGetRegBaseOffsetAndSize__(pGpuResource, pGpu, pOffset, pSize); +static inline NV_STATUS thirdpartyp2pControl_DISPATCH(struct ThirdPartyP2P *pGpuResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return pGpuResource->__thirdpartyp2pControl__(pGpuResource, pCallContext, pParams); } -static inline NvBool thirdpartyp2pCanCopy_DISPATCH(struct ThirdPartyP2P *pResource) { - return pResource->__thirdpartyp2pCanCopy__(pResource); +static inline NV_STATUS thirdpartyp2pUnmap_DISPATCH(struct ThirdPartyP2P *pGpuResource, struct CALL_CONTEXT *pCallContext, struct RsCpuMapping *pCpuMapping) { + return pGpuResource->__thirdpartyp2pUnmap__(pGpuResource, pCallContext, pCpuMapping); } -static inline NV_STATUS thirdpartyp2pInternalControlForward_DISPATCH(struct ThirdPartyP2P *pGpuResource, NvU32 command, void *pParams, NvU32 size) { - return pGpuResource->__thirdpartyp2pInternalControlForward__(pGpuResource, command, pParams, size); +static inline NV_STATUS thirdpartyp2pGetMemInterMapParams_DISPATCH(struct ThirdPartyP2P *pRmResource, RMRES_MEM_INTER_MAP_PARAMS *pParams) { + return pRmResource->__thirdpartyp2pGetMemInterMapParams__(pRmResource, pParams); } -static inline void thirdpartyp2pPreDestruct_DISPATCH(struct ThirdPartyP2P *pResource) { - pResource->__thirdpartyp2pPreDestruct__(pResource); +static inline NV_STATUS thirdpartyp2pGetMemoryMappingDescriptor_DISPATCH(struct ThirdPartyP2P *pRmResource, struct MEMORY_DESCRIPTOR **ppMemDesc) { + return pRmResource->__thirdpartyp2pGetMemoryMappingDescriptor__(pRmResource, ppMemDesc); } -static inline NV_STATUS thirdpartyp2pUnmapFrom_DISPATCH(struct ThirdPartyP2P *pResource, RS_RES_UNMAP_FROM_PARAMS *pParams) { - return pResource->__thirdpartyp2pUnmapFrom__(pResource, pParams); +static inline NV_STATUS thirdpartyp2pControlFilter_DISPATCH(struct ThirdPartyP2P *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return pResource->__thirdpartyp2pControlFilter__(pResource, pCallContext, pParams); } -static inline NV_STATUS thirdpartyp2pIsDuplicate_DISPATCH(struct ThirdPartyP2P *pResource, NvHandle hMemory, NvBool *pDuplicate) { - return pResource->__thirdpartyp2pIsDuplicate__(pResource, hMemory, pDuplicate); +static inline NV_STATUS thirdpartyp2pControlSerialization_Prologue_DISPATCH(struct ThirdPartyP2P *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return pResource->__thirdpartyp2pControlSerialization_Prologue__(pResource, pCallContext, pParams); } -static inline void thirdpartyp2pControl_Epilogue_DISPATCH(struct ThirdPartyP2P *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { - pResource->__thirdpartyp2pControl_Epilogue__(pResource, pCallContext, pParams); +static inline NvBool thirdpartyp2pCanCopy_DISPATCH(struct ThirdPartyP2P *pResource) { + return pResource->__thirdpartyp2pCanCopy__(pResource); } -static inline NV_STATUS thirdpartyp2pControlLookup_DISPATCH(struct ThirdPartyP2P *pResource, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams, const struct NVOC_EXPORTED_METHOD_DEF **ppEntry) { - return pResource->__thirdpartyp2pControlLookup__(pResource, pParams, ppEntry); +static inline void thirdpartyp2pPreDestruct_DISPATCH(struct ThirdPartyP2P *pResource) { + pResource->__thirdpartyp2pPreDestruct__(pResource); +} + +static inline NV_STATUS thirdpartyp2pIsDuplicate_DISPATCH(struct ThirdPartyP2P *pResource, NvHandle hMemory, NvBool *pDuplicate) { + return pResource->__thirdpartyp2pIsDuplicate__(pResource, hMemory, pDuplicate); +} + +static inline void thirdpartyp2pControlSerialization_Epilogue_DISPATCH(struct ThirdPartyP2P *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + pResource->__thirdpartyp2pControlSerialization_Epilogue__(pResource, pCallContext, pParams); } static inline NV_STATUS thirdpartyp2pMap_DISPATCH(struct ThirdPartyP2P *pGpuResource, struct CALL_CONTEXT *pCallContext, struct RS_CPU_MAP_PARAMS *pParams, struct RsCpuMapping *pCpuMapping) { @@ -549,15 +561,6 @@ // Functions prototypes // **************************************************************************** -// Create and add/register a third-party P2P object -NV_STATUS CliAddThirdPartyP2P (NvHandle, NvHandle, struct Subdevice *, NvU32, NvU64); - -// Delete the specified third-party P2P object -NV_STATUS CliDelThirdPartyP2P (NvHandle, NvHandle); - -// Get third-party P2P info given client/object handles -NV_STATUS CliGetThirdPartyP2PInfo (NvHandle, NvHandle, PCLI_THIRD_PARTY_P2P_INFO *); - // Get registered third-party P2P info from pid. Also match the provided client handle if provided. NV_STATUS CliNextThirdPartyP2PInfoWithPid (struct OBJGPU *, NvU32, NvHandle, struct RmClient**, PCLI_THIRD_PARTY_P2P_INFO *); @@ -565,13 +568,13 @@ NV_STATUS CliGetThirdPartyP2PInfoFromToken (NvU64, PCLI_THIRD_PARTY_P2P_INFO *); // Register an address space with a third-party P2P object -NV_STATUS CliAddThirdPartyP2PVASpace (NvHandle, NvHandle, NvHandle, NvU32 *); +NV_STATUS CliAddThirdPartyP2PVASpace (struct ThirdPartyP2P*, NvHandle, NvU32 *); // Unregister an address space from a third-party P2P object NV_STATUS CliDelThirdPartyP2PVASpace (struct ThirdPartyP2P*, NvHandle); // Register video memory with a third-party P2P object -NV_STATUS CliAddThirdPartyP2PVidmemInfo (NvHandle, NvHandle, NvHandle, NvU64, NvU64, NvU64, struct Memory *); +NV_STATUS CliAddThirdPartyP2PVidmemInfo (struct ThirdPartyP2P*, NvHandle, NvU64, NvU64, NvU64, struct Memory *); // Unregister video memory from a third-party P2P object NV_STATUS CliDelThirdPartyP2PVidmemInfo (struct ThirdPartyP2P*, NvHandle); @@ -580,19 +583,19 @@ void CliDelThirdPartyP2PVidmemInfoPersistent (struct ThirdPartyP2P*, CLI_THIRD_PARTY_P2P_VIDMEM_INFO*); // Find registered video memory given an address -NV_STATUS CliGetThirdPartyP2PVidmemInfoFromAddress (NvHandle, NvHandle, NvU64, NvU64, NvU64 *, PCLI_THIRD_PARTY_P2P_VIDMEM_INFO *); +NV_STATUS CliGetThirdPartyP2PVidmemInfoFromAddress (struct ThirdPartyP2P*, NvU64, NvU64, NvU64 *, PCLI_THIRD_PARTY_P2P_VIDMEM_INFO *); // Find registered video memory given a VidmemInfo ID -NV_STATUS CliGetThirdPartyP2PVidmemInfoFromId(NvHandle, NvHandle, NvU64, CLI_THIRD_PARTY_P2P_VIDMEM_INFO **); +NV_STATUS CliGetThirdPartyP2PVidmemInfoFromId(struct ThirdPartyP2P*, NvU64, CLI_THIRD_PARTY_P2P_VIDMEM_INFO **); // Find platformData given a P2PInfo object NV_STATUS CliGetThirdPartyP2PPlatformData (PCLI_THIRD_PARTY_P2P_INFO, void *); // Associate a P2P mapping with registered video memory -NV_STATUS CliAddThirdPartyP2PMappingInfo (NvHandle, NvHandle, NvHandle, void *, THIRD_PARTY_P2P_VIDMEM_FREE_CALLBACK *, void *, PCLI_THIRD_PARTY_P2P_MAPPING_INFO *); +NV_STATUS CliAddThirdPartyP2PMappingInfo (struct ThirdPartyP2P*, NvHandle, void *, THIRD_PARTY_P2P_VIDMEM_FREE_CALLBACK *, void *, PCLI_THIRD_PARTY_P2P_MAPPING_INFO *); // Find a P2P mapping given its platform specific data -NV_STATUS CliGetThirdPartyP2PMappingInfoFromKey (NvHandle, NvHandle, NvHandle, void *, PCLI_THIRD_PARTY_P2P_MAPPING_INFO *); +NV_STATUS CliGetThirdPartyP2PMappingInfoFromKey (struct ThirdPartyP2P*, NvHandle, void *, PCLI_THIRD_PARTY_P2P_MAPPING_INFO *); // Register pid & client with a third-party P2P Info object NV_STATUS CliAddThirdPartyP2PClientPid (NvHandle, NvHandle, NvU32, NvU32); @@ -604,7 +607,7 @@ NV_STATUS CliUnregisterFromThirdPartyP2P (struct RmClient*); // Register a free callback -NV_STATUS CliRegisterThirdPartyP2PMappingCallback (NvHandle, NvHandle, NvHandle, void *, THIRD_PARTY_P2P_VIDMEM_FREE_CALLBACK *, void *); +NV_STATUS CliRegisterThirdPartyP2PMappingCallback (struct ThirdPartyP2P*, NvHandle, void *, THIRD_PARTY_P2P_VIDMEM_FREE_CALLBACK *, void *); // Unregister memory from a third-party P2P Info object void CliUnregisterMemoryFromThirdPartyP2P(struct Memory *pMemory); diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/generated/g_timed_sema_nvoc.c nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_timed_sema_nvoc.c --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/generated/g_timed_sema_nvoc.c 2023-10-25 20:27:21.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_timed_sema_nvoc.c 2024-03-05 22:18:48.000000000 +0000 @@ -120,7 +120,7 @@ /*pExportInfo=*/ &__nvoc_export_info_TimedSemaSwObject }; -static NV_STATUS __nvoc_thunk_TimedSemaSwObject_chandesGetSwMethods(struct ChannelDescendant *pTimedSemSw, METHOD **ppMethods, NvU32 *pNumMethods) { +static NV_STATUS __nvoc_thunk_TimedSemaSwObject_chandesGetSwMethods(struct ChannelDescendant *pTimedSemSw, const METHOD **ppMethods, NvU32 *pNumMethods) { return tsemaGetSwMethods((struct TimedSemaSwObject *)(((unsigned char *)pTimedSemSw) - __nvoc_rtti_TimedSemaSwObject_ChannelDescendant.offset), ppMethods, pNumMethods); } @@ -212,6 +212,10 @@ return notifyUnregisterEvent((struct Notifier *)(((unsigned char *)pNotifier) + __nvoc_rtti_TimedSemaSwObject_Notifier.offset), hNotifierClient, hNotifierResource, hEventClient, hEvent); } +static NV_STATUS __nvoc_thunk_RmResource_tsemaControlSerialization_Prologue(struct TimedSemaSwObject *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return rmresControlSerialization_Prologue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_TimedSemaSwObject_RmResource.offset), pCallContext, pParams); +} + static NvBool __nvoc_thunk_RsResource_tsemaCanCopy(struct TimedSemaSwObject *pResource) { return resCanCopy((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_TimedSemaSwObject_RsResource.offset)); } @@ -224,6 +228,10 @@ return resIsDuplicate((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_TimedSemaSwObject_RsResource.offset), hMemory, pDuplicate); } +static void __nvoc_thunk_RmResource_tsemaControlSerialization_Epilogue(struct TimedSemaSwObject *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + rmresControlSerialization_Epilogue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_TimedSemaSwObject_RmResource.offset), pCallContext, pParams); +} + static PEVENTNOTIFICATION *__nvoc_thunk_Notifier_tsemaGetNotificationListPtr(struct TimedSemaSwObject *pNotifier) { return notifyGetNotificationListPtr((struct Notifier *)(((unsigned char *)pNotifier) + __nvoc_rtti_TimedSemaSwObject_Notifier.offset)); } @@ -393,12 +401,16 @@ pThis->__tsemaUnregisterEvent__ = &__nvoc_thunk_Notifier_tsemaUnregisterEvent; + pThis->__tsemaControlSerialization_Prologue__ = &__nvoc_thunk_RmResource_tsemaControlSerialization_Prologue; + pThis->__tsemaCanCopy__ = &__nvoc_thunk_RsResource_tsemaCanCopy; pThis->__tsemaPreDestruct__ = &__nvoc_thunk_RsResource_tsemaPreDestruct; pThis->__tsemaIsDuplicate__ = &__nvoc_thunk_RsResource_tsemaIsDuplicate; + pThis->__tsemaControlSerialization_Epilogue__ = &__nvoc_thunk_RmResource_tsemaControlSerialization_Epilogue; + pThis->__tsemaGetNotificationListPtr__ = &__nvoc_thunk_Notifier_tsemaGetNotificationListPtr; pThis->__tsemaGetNotificationShare__ = &__nvoc_thunk_Notifier_tsemaGetNotificationShare; @@ -433,13 +445,16 @@ TimedSemaSwObject *pThis; RmHalspecOwner *pRmhalspecowner; - pThis = portMemAllocNonPaged(sizeof(TimedSemaSwObject)); - if (pThis == NULL) return NV_ERR_NO_MEMORY; + status = __nvoc_handleObjCreateMemAlloc(createFlags, sizeof(TimedSemaSwObject), (void**)&pThis, (void**)ppThis); + if (status != NV_OK) + return status; portMemSet(pThis, 0, sizeof(TimedSemaSwObject)); __nvoc_initRtti(staticCast(pThis, Dynamic), &__nvoc_class_def_TimedSemaSwObject); + pThis->__nvoc_base_ChannelDescendant.__nvoc_base_GpuResource.__nvoc_base_RmResource.__nvoc_base_RsResource.__nvoc_base_Object.createFlags = createFlags; + if (pParent != NULL && !(createFlags & NVOC_OBJ_CREATE_FLAGS_PARENT_HALSPEC_ONLY)) { pParentObj = dynamicCast(pParent, Object); @@ -459,11 +474,17 @@ if (status != NV_OK) goto __nvoc_objCreate_TimedSemaSwObject_cleanup; *ppThis = pThis; + return NV_OK; __nvoc_objCreate_TimedSemaSwObject_cleanup: // do not call destructors here since the constructor already called them - portMemFree(pThis); + if (createFlags & NVOC_OBJ_CREATE_FLAGS_IN_PLACE_CONSTRUCT) + portMemSet(pThis, 0, sizeof(TimedSemaSwObject)); + else + portMemFree(pThis); + + // coverity[leaked_storage:FALSE] return status; } diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/generated/g_timed_sema_nvoc.h nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_timed_sema_nvoc.h --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/generated/g_timed_sema_nvoc.h 2023-10-25 20:27:21.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_timed_sema_nvoc.h 2024-03-05 22:18:48.000000000 +0000 @@ -69,7 +69,7 @@ struct Notifier *__nvoc_pbase_Notifier; struct ChannelDescendant *__nvoc_pbase_ChannelDescendant; struct TimedSemaSwObject *__nvoc_pbase_TimedSemaSwObject; - NV_STATUS (*__tsemaGetSwMethods__)(struct TimedSemaSwObject *, METHOD **, NvU32 *); + NV_STATUS (*__tsemaGetSwMethods__)(struct TimedSemaSwObject *, const METHOD **, NvU32 *); NV_STATUS (*__tsemaCtrlCmdFlush__)(struct TimedSemaSwObject *, NV9074_CTRL_CMD_FLUSH_PARAMS *); NV_STATUS (*__tsemaCtrlCmdGetTime__)(struct TimedSemaSwObject *, NV9074_CTRL_CMD_GET_TIME_PARAMS *); NV_STATUS (*__tsemaCtrlCmdRelease__)(struct TimedSemaSwObject *, NV9074_CTRL_CMD_RELEASE_PARAMS *); @@ -95,9 +95,11 @@ NvBool (*__tsemaIsSwMethodStalling__)(struct TimedSemaSwObject *, NvU32); NV_STATUS (*__tsemaControlFilter__)(struct TimedSemaSwObject *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); NV_STATUS (*__tsemaUnregisterEvent__)(struct TimedSemaSwObject *, NvHandle, NvHandle, NvHandle, NvHandle); + NV_STATUS (*__tsemaControlSerialization_Prologue__)(struct TimedSemaSwObject *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); NvBool (*__tsemaCanCopy__)(struct TimedSemaSwObject *); void (*__tsemaPreDestruct__)(struct TimedSemaSwObject *); NV_STATUS (*__tsemaIsDuplicate__)(struct TimedSemaSwObject *, NvHandle, NvBool *); + void (*__tsemaControlSerialization_Epilogue__)(struct TimedSemaSwObject *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); PEVENTNOTIFICATION *(*__tsemaGetNotificationListPtr__)(struct TimedSemaSwObject *); struct NotifShare *(*__tsemaGetNotificationShare__)(struct TimedSemaSwObject *); NV_STATUS (*__tsemaMap__)(struct TimedSemaSwObject *, struct CALL_CONTEXT *, struct RS_CPU_MAP_PARAMS *, struct RsCpuMapping *); @@ -171,22 +173,24 @@ #define tsemaIsSwMethodStalling(pChannelDescendant, hHandle) tsemaIsSwMethodStalling_DISPATCH(pChannelDescendant, hHandle) #define tsemaControlFilter(pResource, pCallContext, pParams) tsemaControlFilter_DISPATCH(pResource, pCallContext, pParams) #define tsemaUnregisterEvent(pNotifier, hNotifierClient, hNotifierResource, hEventClient, hEvent) tsemaUnregisterEvent_DISPATCH(pNotifier, hNotifierClient, hNotifierResource, hEventClient, hEvent) +#define tsemaControlSerialization_Prologue(pResource, pCallContext, pParams) tsemaControlSerialization_Prologue_DISPATCH(pResource, pCallContext, pParams) #define tsemaCanCopy(pResource) tsemaCanCopy_DISPATCH(pResource) #define tsemaPreDestruct(pResource) tsemaPreDestruct_DISPATCH(pResource) #define tsemaIsDuplicate(pResource, hMemory, pDuplicate) tsemaIsDuplicate_DISPATCH(pResource, hMemory, pDuplicate) +#define tsemaControlSerialization_Epilogue(pResource, pCallContext, pParams) tsemaControlSerialization_Epilogue_DISPATCH(pResource, pCallContext, pParams) #define tsemaGetNotificationListPtr(pNotifier) tsemaGetNotificationListPtr_DISPATCH(pNotifier) #define tsemaGetNotificationShare(pNotifier) tsemaGetNotificationShare_DISPATCH(pNotifier) #define tsemaMap(pGpuResource, pCallContext, pParams, pCpuMapping) tsemaMap_DISPATCH(pGpuResource, pCallContext, pParams, pCpuMapping) #define tsemaGetOrAllocNotifShare(pNotifier, hNotifierClient, hNotifierResource, ppNotifShare) tsemaGetOrAllocNotifShare_DISPATCH(pNotifier, hNotifierClient, hNotifierResource, ppNotifShare) -NV_STATUS tsemaRelease_KERNEL(struct OBJGPU *pGpu, NvU64 semaphoreVA, NvU64 notifierVA, NvU32 hVASpace, NvU32 releasevalue, NvU32 completionStatus, NvHandle hClient); +NV_STATUS tsemaRelease_KERNEL(struct OBJGPU *pGpu, NvU64 semaphoreVA, NvU64 notifierVA, NvU32 hVASpace, NvU32 releasevalue, NvU32 completionStatus, struct RsClient *pClient); -#define tsemaRelease(pGpu, semaphoreVA, notifierVA, hVASpace, releasevalue, completionStatus, hClient) tsemaRelease_KERNEL(pGpu, semaphoreVA, notifierVA, hVASpace, releasevalue, completionStatus, hClient) -#define tsemaRelease_HAL(pGpu, semaphoreVA, notifierVA, hVASpace, releasevalue, completionStatus, hClient) tsemaRelease(pGpu, semaphoreVA, notifierVA, hVASpace, releasevalue, completionStatus, hClient) +#define tsemaRelease(pGpu, semaphoreVA, notifierVA, hVASpace, releasevalue, completionStatus, pClient) tsemaRelease_KERNEL(pGpu, semaphoreVA, notifierVA, hVASpace, releasevalue, completionStatus, pClient) +#define tsemaRelease_HAL(pGpu, semaphoreVA, notifierVA, hVASpace, releasevalue, completionStatus, pClient) tsemaRelease(pGpu, semaphoreVA, notifierVA, hVASpace, releasevalue, completionStatus, pClient) -NV_STATUS tsemaGetSwMethods_IMPL(struct TimedSemaSwObject *pTimedSemSw, METHOD **ppMethods, NvU32 *pNumMethods); +NV_STATUS tsemaGetSwMethods_IMPL(struct TimedSemaSwObject *pTimedSemSw, const METHOD **ppMethods, NvU32 *pNumMethods); -static inline NV_STATUS tsemaGetSwMethods_DISPATCH(struct TimedSemaSwObject *pTimedSemSw, METHOD **ppMethods, NvU32 *pNumMethods) { +static inline NV_STATUS tsemaGetSwMethods_DISPATCH(struct TimedSemaSwObject *pTimedSemSw, const METHOD **ppMethods, NvU32 *pNumMethods) { return pTimedSemSw->__tsemaGetSwMethods__(pTimedSemSw, ppMethods, pNumMethods); } @@ -296,6 +300,10 @@ return pNotifier->__tsemaUnregisterEvent__(pNotifier, hNotifierClient, hNotifierResource, hEventClient, hEvent); } +static inline NV_STATUS tsemaControlSerialization_Prologue_DISPATCH(struct TimedSemaSwObject *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return pResource->__tsemaControlSerialization_Prologue__(pResource, pCallContext, pParams); +} + static inline NvBool tsemaCanCopy_DISPATCH(struct TimedSemaSwObject *pResource) { return pResource->__tsemaCanCopy__(pResource); } @@ -308,6 +316,10 @@ return pResource->__tsemaIsDuplicate__(pResource, hMemory, pDuplicate); } +static inline void tsemaControlSerialization_Epilogue_DISPATCH(struct TimedSemaSwObject *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + pResource->__tsemaControlSerialization_Epilogue__(pResource, pCallContext, pParams); +} + static inline PEVENTNOTIFICATION *tsemaGetNotificationListPtr_DISPATCH(struct TimedSemaSwObject *pNotifier) { return pNotifier->__tsemaGetNotificationListPtr__(pNotifier); } diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/generated/g_tmr_nvoc.c nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_tmr_nvoc.c --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/generated/g_tmr_nvoc.c 2023-10-25 20:27:21.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_tmr_nvoc.c 2024-03-05 22:18:48.000000000 +0000 @@ -119,16 +119,16 @@ return gpuresShareCallback((struct GpuResource *)(((unsigned char *)pGpuResource) + __nvoc_rtti_TimerApi_GpuResource.offset), pInvokingClient, pParentRef, pSharePolicy); } -static NV_STATUS __nvoc_thunk_RsResource_tmrapiMapTo(struct TimerApi *pResource, RS_RES_MAP_TO_PARAMS *pParams) { - return resMapTo((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_TimerApi_RsResource.offset), pParams); +static NV_STATUS __nvoc_thunk_RmResource_tmrapiCheckMemInterUnmap(struct TimerApi *pRmResource, NvBool bSubdeviceHandleProvided) { + return rmresCheckMemInterUnmap((struct RmResource *)(((unsigned char *)pRmResource) + __nvoc_rtti_TimerApi_RmResource.offset), bSubdeviceHandleProvided); } static NV_STATUS __nvoc_thunk_Notifier_tmrapiGetOrAllocNotifShare(struct TimerApi *pNotifier, NvHandle hNotifierClient, NvHandle hNotifierResource, struct NotifShare **ppNotifShare) { return notifyGetOrAllocNotifShare((struct Notifier *)(((unsigned char *)pNotifier) + __nvoc_rtti_TimerApi_Notifier.offset), hNotifierClient, hNotifierResource, ppNotifShare); } -static NV_STATUS __nvoc_thunk_RmResource_tmrapiCheckMemInterUnmap(struct TimerApi *pRmResource, NvBool bSubdeviceHandleProvided) { - return rmresCheckMemInterUnmap((struct RmResource *)(((unsigned char *)pRmResource) + __nvoc_rtti_TimerApi_RmResource.offset), bSubdeviceHandleProvided); +static NV_STATUS __nvoc_thunk_RsResource_tmrapiMapTo(struct TimerApi *pResource, RS_RES_MAP_TO_PARAMS *pParams) { + return resMapTo((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_TimerApi_RsResource.offset), pParams); } static NV_STATUS __nvoc_thunk_GpuResource_tmrapiGetMapAddrSpace(struct TimerApi *pGpuResource, struct CALL_CONTEXT *pCallContext, NvU32 mapFlags, NV_ADDRESS_SPACE *pAddrSpace) { @@ -195,6 +195,10 @@ return notifyUnregisterEvent((struct Notifier *)(((unsigned char *)pNotifier) + __nvoc_rtti_TimerApi_Notifier.offset), hNotifierClient, hNotifierResource, hEventClient, hEvent); } +static NV_STATUS __nvoc_thunk_RmResource_tmrapiControlSerialization_Prologue(struct TimerApi *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return rmresControlSerialization_Prologue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_TimerApi_RmResource.offset), pCallContext, pParams); +} + static NvBool __nvoc_thunk_RsResource_tmrapiCanCopy(struct TimerApi *pResource) { return resCanCopy((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_TimerApi_RsResource.offset)); } @@ -207,6 +211,10 @@ return resIsDuplicate((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_TimerApi_RsResource.offset), hMemory, pDuplicate); } +static void __nvoc_thunk_RmResource_tmrapiControlSerialization_Epilogue(struct TimerApi *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + rmresControlSerialization_Epilogue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_TimerApi_RmResource.offset), pCallContext, pParams); +} + static PEVENTNOTIFICATION *__nvoc_thunk_Notifier_tmrapiGetNotificationListPtr(struct TimerApi *pNotifier) { return notifyGetNotificationListPtr((struct Notifier *)(((unsigned char *)pNotifier) + __nvoc_rtti_TimerApi_Notifier.offset)); } @@ -303,11 +311,11 @@ pThis->__tmrapiShareCallback__ = &__nvoc_thunk_GpuResource_tmrapiShareCallback; - pThis->__tmrapiMapTo__ = &__nvoc_thunk_RsResource_tmrapiMapTo; + pThis->__tmrapiCheckMemInterUnmap__ = &__nvoc_thunk_RmResource_tmrapiCheckMemInterUnmap; pThis->__tmrapiGetOrAllocNotifShare__ = &__nvoc_thunk_Notifier_tmrapiGetOrAllocNotifShare; - pThis->__tmrapiCheckMemInterUnmap__ = &__nvoc_thunk_RmResource_tmrapiCheckMemInterUnmap; + pThis->__tmrapiMapTo__ = &__nvoc_thunk_RsResource_tmrapiMapTo; pThis->__tmrapiGetMapAddrSpace__ = &__nvoc_thunk_GpuResource_tmrapiGetMapAddrSpace; @@ -341,12 +349,16 @@ pThis->__tmrapiUnregisterEvent__ = &__nvoc_thunk_Notifier_tmrapiUnregisterEvent; + pThis->__tmrapiControlSerialization_Prologue__ = &__nvoc_thunk_RmResource_tmrapiControlSerialization_Prologue; + pThis->__tmrapiCanCopy__ = &__nvoc_thunk_RsResource_tmrapiCanCopy; pThis->__tmrapiPreDestruct__ = &__nvoc_thunk_RsResource_tmrapiPreDestruct; pThis->__tmrapiIsDuplicate__ = &__nvoc_thunk_RsResource_tmrapiIsDuplicate; + pThis->__tmrapiControlSerialization_Epilogue__ = &__nvoc_thunk_RmResource_tmrapiControlSerialization_Epilogue; + pThis->__tmrapiGetNotificationListPtr__ = &__nvoc_thunk_Notifier_tmrapiGetNotificationListPtr; pThis->__tmrapiGetNotificationShare__ = &__nvoc_thunk_Notifier_tmrapiGetNotificationShare; @@ -381,13 +393,16 @@ Object *pParentObj; TimerApi *pThis; - pThis = portMemAllocNonPaged(sizeof(TimerApi)); - if (pThis == NULL) return NV_ERR_NO_MEMORY; + status = __nvoc_handleObjCreateMemAlloc(createFlags, sizeof(TimerApi), (void**)&pThis, (void**)ppThis); + if (status != NV_OK) + return status; portMemSet(pThis, 0, sizeof(TimerApi)); __nvoc_initRtti(staticCast(pThis, Dynamic), &__nvoc_class_def_TimerApi); + pThis->__nvoc_base_GpuResource.__nvoc_base_RmResource.__nvoc_base_RsResource.__nvoc_base_Object.createFlags = createFlags; + if (pParent != NULL && !(createFlags & NVOC_OBJ_CREATE_FLAGS_PARENT_HALSPEC_ONLY)) { pParentObj = dynamicCast(pParent, Object); @@ -403,11 +418,17 @@ if (status != NV_OK) goto __nvoc_objCreate_TimerApi_cleanup; *ppThis = pThis; + return NV_OK; __nvoc_objCreate_TimerApi_cleanup: // do not call destructors here since the constructor already called them - portMemFree(pThis); + if (createFlags & NVOC_OBJ_CREATE_FLAGS_IN_PLACE_CONSTRUCT) + portMemSet(pThis, 0, sizeof(TimerApi)); + else + portMemFree(pThis); + + // coverity[leaked_storage:FALSE] return status; } diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/generated/g_tmr_nvoc.h nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_tmr_nvoc.h --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/generated/g_tmr_nvoc.h 2023-10-25 20:27:21.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_tmr_nvoc.h 2024-03-05 22:18:48.000000000 +0000 @@ -100,9 +100,9 @@ NV_STATUS (*__tmrapiGetRegBaseOffsetAndSize__)(struct TimerApi *, struct OBJGPU *, NvU32 *, NvU32 *); NV_STATUS (*__tmrapiCtrlCmdTmrSetAlarmNotify__)(struct TimerApi *, NV0004_CTRL_TMR_SET_ALARM_NOTIFY_PARAMS *); NvBool (*__tmrapiShareCallback__)(struct TimerApi *, struct RsClient *, struct RsResourceRef *, RS_SHARE_POLICY *); - NV_STATUS (*__tmrapiMapTo__)(struct TimerApi *, RS_RES_MAP_TO_PARAMS *); - NV_STATUS (*__tmrapiGetOrAllocNotifShare__)(struct TimerApi *, NvHandle, NvHandle, struct NotifShare **); NV_STATUS (*__tmrapiCheckMemInterUnmap__)(struct TimerApi *, NvBool); + NV_STATUS (*__tmrapiGetOrAllocNotifShare__)(struct TimerApi *, NvHandle, NvHandle, struct NotifShare **); + NV_STATUS (*__tmrapiMapTo__)(struct TimerApi *, RS_RES_MAP_TO_PARAMS *); NV_STATUS (*__tmrapiGetMapAddrSpace__)(struct TimerApi *, struct CALL_CONTEXT *, NvU32, NV_ADDRESS_SPACE *); void (*__tmrapiSetNotificationShare__)(struct TimerApi *, struct NotifShare *); NvU32 (*__tmrapiGetRefCount__)(struct TimerApi *); @@ -119,9 +119,11 @@ NV_STATUS (*__tmrapiGetMemoryMappingDescriptor__)(struct TimerApi *, struct MEMORY_DESCRIPTOR **); NV_STATUS (*__tmrapiControlFilter__)(struct TimerApi *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); NV_STATUS (*__tmrapiUnregisterEvent__)(struct TimerApi *, NvHandle, NvHandle, NvHandle, NvHandle); + NV_STATUS (*__tmrapiControlSerialization_Prologue__)(struct TimerApi *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); NvBool (*__tmrapiCanCopy__)(struct TimerApi *); void (*__tmrapiPreDestruct__)(struct TimerApi *); NV_STATUS (*__tmrapiIsDuplicate__)(struct TimerApi *, NvHandle, NvBool *); + void (*__tmrapiControlSerialization_Epilogue__)(struct TimerApi *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); PEVENTNOTIFICATION *(*__tmrapiGetNotificationListPtr__)(struct TimerApi *); struct NotifShare *(*__tmrapiGetNotificationShare__)(struct TimerApi *); NV_STATUS (*__tmrapiMap__)(struct TimerApi *, struct CALL_CONTEXT *, struct RS_CPU_MAP_PARAMS *, struct RsCpuMapping *); @@ -159,9 +161,9 @@ #define tmrapiGetRegBaseOffsetAndSize(pTimerApi, pGpu, pOffset, pSize) tmrapiGetRegBaseOffsetAndSize_DISPATCH(pTimerApi, pGpu, pOffset, pSize) #define tmrapiCtrlCmdTmrSetAlarmNotify(pTimerApi, pParams) tmrapiCtrlCmdTmrSetAlarmNotify_DISPATCH(pTimerApi, pParams) #define tmrapiShareCallback(pGpuResource, pInvokingClient, pParentRef, pSharePolicy) tmrapiShareCallback_DISPATCH(pGpuResource, pInvokingClient, pParentRef, pSharePolicy) -#define tmrapiMapTo(pResource, pParams) tmrapiMapTo_DISPATCH(pResource, pParams) -#define tmrapiGetOrAllocNotifShare(pNotifier, hNotifierClient, hNotifierResource, ppNotifShare) tmrapiGetOrAllocNotifShare_DISPATCH(pNotifier, hNotifierClient, hNotifierResource, ppNotifShare) #define tmrapiCheckMemInterUnmap(pRmResource, bSubdeviceHandleProvided) tmrapiCheckMemInterUnmap_DISPATCH(pRmResource, bSubdeviceHandleProvided) +#define tmrapiGetOrAllocNotifShare(pNotifier, hNotifierClient, hNotifierResource, ppNotifShare) tmrapiGetOrAllocNotifShare_DISPATCH(pNotifier, hNotifierClient, hNotifierResource, ppNotifShare) +#define tmrapiMapTo(pResource, pParams) tmrapiMapTo_DISPATCH(pResource, pParams) #define tmrapiGetMapAddrSpace(pGpuResource, pCallContext, mapFlags, pAddrSpace) tmrapiGetMapAddrSpace_DISPATCH(pGpuResource, pCallContext, mapFlags, pAddrSpace) #define tmrapiSetNotificationShare(pNotifier, pNotifShare) tmrapiSetNotificationShare_DISPATCH(pNotifier, pNotifShare) #define tmrapiGetRefCount(pResource) tmrapiGetRefCount_DISPATCH(pResource) @@ -178,9 +180,11 @@ #define tmrapiGetMemoryMappingDescriptor(pRmResource, ppMemDesc) tmrapiGetMemoryMappingDescriptor_DISPATCH(pRmResource, ppMemDesc) #define tmrapiControlFilter(pResource, pCallContext, pParams) tmrapiControlFilter_DISPATCH(pResource, pCallContext, pParams) #define tmrapiUnregisterEvent(pNotifier, hNotifierClient, hNotifierResource, hEventClient, hEvent) tmrapiUnregisterEvent_DISPATCH(pNotifier, hNotifierClient, hNotifierResource, hEventClient, hEvent) +#define tmrapiControlSerialization_Prologue(pResource, pCallContext, pParams) tmrapiControlSerialization_Prologue_DISPATCH(pResource, pCallContext, pParams) #define tmrapiCanCopy(pResource) tmrapiCanCopy_DISPATCH(pResource) #define tmrapiPreDestruct(pResource) tmrapiPreDestruct_DISPATCH(pResource) #define tmrapiIsDuplicate(pResource, hMemory, pDuplicate) tmrapiIsDuplicate_DISPATCH(pResource, hMemory, pDuplicate) +#define tmrapiControlSerialization_Epilogue(pResource, pCallContext, pParams) tmrapiControlSerialization_Epilogue_DISPATCH(pResource, pCallContext, pParams) #define tmrapiGetNotificationListPtr(pNotifier) tmrapiGetNotificationListPtr_DISPATCH(pNotifier) #define tmrapiGetNotificationShare(pNotifier) tmrapiGetNotificationShare_DISPATCH(pNotifier) #define tmrapiMap(pGpuResource, pCallContext, pParams, pCpuMapping) tmrapiMap_DISPATCH(pGpuResource, pCallContext, pParams, pCpuMapping) @@ -201,16 +205,16 @@ return pGpuResource->__tmrapiShareCallback__(pGpuResource, pInvokingClient, pParentRef, pSharePolicy); } -static inline NV_STATUS tmrapiMapTo_DISPATCH(struct TimerApi *pResource, RS_RES_MAP_TO_PARAMS *pParams) { - return pResource->__tmrapiMapTo__(pResource, pParams); +static inline NV_STATUS tmrapiCheckMemInterUnmap_DISPATCH(struct TimerApi *pRmResource, NvBool bSubdeviceHandleProvided) { + return pRmResource->__tmrapiCheckMemInterUnmap__(pRmResource, bSubdeviceHandleProvided); } static inline NV_STATUS tmrapiGetOrAllocNotifShare_DISPATCH(struct TimerApi *pNotifier, NvHandle hNotifierClient, NvHandle hNotifierResource, struct NotifShare **ppNotifShare) { return pNotifier->__tmrapiGetOrAllocNotifShare__(pNotifier, hNotifierClient, hNotifierResource, ppNotifShare); } -static inline NV_STATUS tmrapiCheckMemInterUnmap_DISPATCH(struct TimerApi *pRmResource, NvBool bSubdeviceHandleProvided) { - return pRmResource->__tmrapiCheckMemInterUnmap__(pRmResource, bSubdeviceHandleProvided); +static inline NV_STATUS tmrapiMapTo_DISPATCH(struct TimerApi *pResource, RS_RES_MAP_TO_PARAMS *pParams) { + return pResource->__tmrapiMapTo__(pResource, pParams); } static inline NV_STATUS tmrapiGetMapAddrSpace_DISPATCH(struct TimerApi *pGpuResource, struct CALL_CONTEXT *pCallContext, NvU32 mapFlags, NV_ADDRESS_SPACE *pAddrSpace) { @@ -277,6 +281,10 @@ return pNotifier->__tmrapiUnregisterEvent__(pNotifier, hNotifierClient, hNotifierResource, hEventClient, hEvent); } +static inline NV_STATUS tmrapiControlSerialization_Prologue_DISPATCH(struct TimerApi *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return pResource->__tmrapiControlSerialization_Prologue__(pResource, pCallContext, pParams); +} + static inline NvBool tmrapiCanCopy_DISPATCH(struct TimerApi *pResource) { return pResource->__tmrapiCanCopy__(pResource); } @@ -289,6 +297,10 @@ return pResource->__tmrapiIsDuplicate__(pResource, hMemory, pDuplicate); } +static inline void tmrapiControlSerialization_Epilogue_DISPATCH(struct TimerApi *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + pResource->__tmrapiControlSerialization_Epilogue__(pResource, pCallContext, pParams); +} + static inline PEVENTNOTIFICATION *tmrapiGetNotificationListPtr_DISPATCH(struct TimerApi *pNotifier) { return pNotifier->__tmrapiGetNotificationListPtr__(pNotifier); } diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/generated/g_usermode_api_nvoc.c nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_usermode_api_nvoc.c --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/generated/g_usermode_api_nvoc.c 2023-10-25 20:27:21.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_usermode_api_nvoc.c 2024-03-05 22:18:49.000000000 +0000 @@ -23,10 +23,10 @@ extern const struct NVOC_CLASS_DEF __nvoc_class_def_Memory; -void __nvoc_init_UserModeApi(UserModeApi*, RmHalspecOwner* ); -void __nvoc_init_funcTable_UserModeApi(UserModeApi*, RmHalspecOwner* ); -NV_STATUS __nvoc_ctor_UserModeApi(UserModeApi*, RmHalspecOwner* , CALL_CONTEXT * arg_pCallContext, struct RS_RES_ALLOC_PARAMS_INTERNAL * arg_pParams); -void __nvoc_init_dataField_UserModeApi(UserModeApi*, RmHalspecOwner* ); +void __nvoc_init_UserModeApi(UserModeApi*); +void __nvoc_init_funcTable_UserModeApi(UserModeApi*); +NV_STATUS __nvoc_ctor_UserModeApi(UserModeApi*, CALL_CONTEXT * arg_pCallContext, struct RS_RES_ALLOC_PARAMS_INTERNAL * arg_pParams); +void __nvoc_init_dataField_UserModeApi(UserModeApi*); void __nvoc_dtor_UserModeApi(UserModeApi*); extern const struct NVOC_EXPORT_INFO __nvoc_export_info_UserModeApi; @@ -101,60 +101,76 @@ return memCheckMemInterUnmap((struct Memory *)(((unsigned char *)pMemory) + __nvoc_rtti_UserModeApi_Memory.offset), bSubdeviceHandleProvided); } -static NV_STATUS __nvoc_thunk_Memory_usrmodeControl(struct UserModeApi *pMemory, CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { - return memControl((struct Memory *)(((unsigned char *)pMemory) + __nvoc_rtti_UserModeApi_Memory.offset), pCallContext, pParams); +static NvBool __nvoc_thunk_RmResource_usrmodeShareCallback(struct UserModeApi *pResource, struct RsClient *pInvokingClient, struct RsResourceRef *pParentRef, RS_SHARE_POLICY *pSharePolicy) { + return rmresShareCallback((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_UserModeApi_RmResource.offset), pInvokingClient, pParentRef, pSharePolicy); } -static NV_STATUS __nvoc_thunk_Memory_usrmodeUnmap(struct UserModeApi *pMemory, CALL_CONTEXT *pCallContext, RsCpuMapping *pCpuMapping) { - return memUnmap((struct Memory *)(((unsigned char *)pMemory) + __nvoc_rtti_UserModeApi_Memory.offset), pCallContext, pCpuMapping); +static NV_STATUS __nvoc_thunk_RsResource_usrmodeMapTo(struct UserModeApi *pResource, RS_RES_MAP_TO_PARAMS *pParams) { + return resMapTo((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_UserModeApi_RsResource.offset), pParams); } -static NV_STATUS __nvoc_thunk_Memory_usrmodeGetMemInterMapParams(struct UserModeApi *pMemory, RMRES_MEM_INTER_MAP_PARAMS *pParams) { - return memGetMemInterMapParams((struct Memory *)(((unsigned char *)pMemory) + __nvoc_rtti_UserModeApi_Memory.offset), pParams); +static NV_STATUS __nvoc_thunk_Memory_usrmodeGetMapAddrSpace(struct UserModeApi *pMemory, CALL_CONTEXT *pCallContext, NvU32 mapFlags, NV_ADDRESS_SPACE *pAddrSpace) { + return memGetMapAddrSpace((struct Memory *)(((unsigned char *)pMemory) + __nvoc_rtti_UserModeApi_Memory.offset), pCallContext, mapFlags, pAddrSpace); } -static NV_STATUS __nvoc_thunk_Memory_usrmodeGetMemoryMappingDescriptor(struct UserModeApi *pMemory, MEMORY_DESCRIPTOR **ppMemDesc) { - return memGetMemoryMappingDescriptor((struct Memory *)(((unsigned char *)pMemory) + __nvoc_rtti_UserModeApi_Memory.offset), ppMemDesc); +static NvU32 __nvoc_thunk_RsResource_usrmodeGetRefCount(struct UserModeApi *pResource) { + return resGetRefCount((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_UserModeApi_RsResource.offset)); } -static NV_STATUS __nvoc_thunk_Memory_usrmodeGetMapAddrSpace(struct UserModeApi *pMemory, CALL_CONTEXT *pCallContext, NvU32 mapFlags, NV_ADDRESS_SPACE *pAddrSpace) { - return memGetMapAddrSpace((struct Memory *)(((unsigned char *)pMemory) + __nvoc_rtti_UserModeApi_Memory.offset), pCallContext, mapFlags, pAddrSpace); +static void __nvoc_thunk_RsResource_usrmodeAddAdditionalDependants(struct RsClient *pClient, struct UserModeApi *pResource, RsResourceRef *pReference) { + resAddAdditionalDependants(pClient, (struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_UserModeApi_RsResource.offset), pReference); } -static NvBool __nvoc_thunk_RmResource_usrmodeShareCallback(struct UserModeApi *pResource, struct RsClient *pInvokingClient, struct RsResourceRef *pParentRef, RS_SHARE_POLICY *pSharePolicy) { - return rmresShareCallback((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_UserModeApi_RmResource.offset), pInvokingClient, pParentRef, pSharePolicy); +static NV_STATUS __nvoc_thunk_RmResource_usrmodeControl_Prologue(struct UserModeApi *pResource, CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return rmresControl_Prologue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_UserModeApi_RmResource.offset), pCallContext, pParams); } -static NV_STATUS __nvoc_thunk_RsResource_usrmodeControlFilter(struct UserModeApi *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { - return resControlFilter((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_UserModeApi_RsResource.offset), pCallContext, pParams); +static NvBool __nvoc_thunk_Memory_usrmodeIsGpuMapAllowed(struct UserModeApi *pMemory, struct OBJGPU *pGpu) { + return memIsGpuMapAllowed((struct Memory *)(((unsigned char *)pMemory) + __nvoc_rtti_UserModeApi_Memory.offset), pGpu); } -static void __nvoc_thunk_RsResource_usrmodeAddAdditionalDependants(struct RsClient *pClient, struct UserModeApi *pResource, RsResourceRef *pReference) { - resAddAdditionalDependants(pClient, (struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_UserModeApi_RsResource.offset), pReference); +static NV_STATUS __nvoc_thunk_RsResource_usrmodeUnmapFrom(struct UserModeApi *pResource, RS_RES_UNMAP_FROM_PARAMS *pParams) { + return resUnmapFrom((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_UserModeApi_RsResource.offset), pParams); } -static NvU32 __nvoc_thunk_RsResource_usrmodeGetRefCount(struct UserModeApi *pResource) { - return resGetRefCount((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_UserModeApi_RsResource.offset)); +static void __nvoc_thunk_RmResource_usrmodeControl_Epilogue(struct UserModeApi *pResource, CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + rmresControl_Epilogue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_UserModeApi_RmResource.offset), pCallContext, pParams); } -static NV_STATUS __nvoc_thunk_RsResource_usrmodeMapTo(struct UserModeApi *pResource, RS_RES_MAP_TO_PARAMS *pParams) { - return resMapTo((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_UserModeApi_RsResource.offset), pParams); +static NV_STATUS __nvoc_thunk_RsResource_usrmodeControlLookup(struct UserModeApi *pResource, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams, const struct NVOC_EXPORTED_METHOD_DEF **ppEntry) { + return resControlLookup((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_UserModeApi_RsResource.offset), pParams, ppEntry); } -static NV_STATUS __nvoc_thunk_RmResource_usrmodeControl_Prologue(struct UserModeApi *pResource, CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { - return rmresControl_Prologue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_UserModeApi_RmResource.offset), pCallContext, pParams); +static NV_STATUS __nvoc_thunk_Memory_usrmodeControl(struct UserModeApi *pMemory, CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return memControl((struct Memory *)(((unsigned char *)pMemory) + __nvoc_rtti_UserModeApi_Memory.offset), pCallContext, pParams); } -static NvBool __nvoc_thunk_Memory_usrmodeIsGpuMapAllowed(struct UserModeApi *pMemory, struct OBJGPU *pGpu) { - return memIsGpuMapAllowed((struct Memory *)(((unsigned char *)pMemory) + __nvoc_rtti_UserModeApi_Memory.offset), pGpu); +static NV_STATUS __nvoc_thunk_Memory_usrmodeUnmap(struct UserModeApi *pMemory, CALL_CONTEXT *pCallContext, RsCpuMapping *pCpuMapping) { + return memUnmap((struct Memory *)(((unsigned char *)pMemory) + __nvoc_rtti_UserModeApi_Memory.offset), pCallContext, pCpuMapping); +} + +static NV_STATUS __nvoc_thunk_Memory_usrmodeGetMemInterMapParams(struct UserModeApi *pMemory, RMRES_MEM_INTER_MAP_PARAMS *pParams) { + return memGetMemInterMapParams((struct Memory *)(((unsigned char *)pMemory) + __nvoc_rtti_UserModeApi_Memory.offset), pParams); +} + +static NV_STATUS __nvoc_thunk_Memory_usrmodeGetMemoryMappingDescriptor(struct UserModeApi *pMemory, MEMORY_DESCRIPTOR **ppMemDesc) { + return memGetMemoryMappingDescriptor((struct Memory *)(((unsigned char *)pMemory) + __nvoc_rtti_UserModeApi_Memory.offset), ppMemDesc); +} + +static NV_STATUS __nvoc_thunk_RsResource_usrmodeControlFilter(struct UserModeApi *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return resControlFilter((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_UserModeApi_RsResource.offset), pCallContext, pParams); +} + +static NV_STATUS __nvoc_thunk_RmResource_usrmodeControlSerialization_Prologue(struct UserModeApi *pResource, CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return rmresControlSerialization_Prologue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_UserModeApi_RmResource.offset), pCallContext, pParams); } static NV_STATUS __nvoc_thunk_Memory_usrmodeIsReady(struct UserModeApi *pMemory, NvBool bCopyConstructorContext) { return memIsReady((struct Memory *)(((unsigned char *)pMemory) + __nvoc_rtti_UserModeApi_Memory.offset), bCopyConstructorContext); } -static NV_STATUS __nvoc_thunk_Memory_usrmodeCheckCopyPermissions(struct UserModeApi *pMemory, struct OBJGPU *pDstGpu, NvHandle hDstClientNvBool) { - return memCheckCopyPermissions((struct Memory *)(((unsigned char *)pMemory) + __nvoc_rtti_UserModeApi_Memory.offset), pDstGpu, hDstClientNvBool); +static NV_STATUS __nvoc_thunk_Memory_usrmodeCheckCopyPermissions(struct UserModeApi *pMemory, struct OBJGPU *pDstGpu, struct Device *pDstDevice) { + return memCheckCopyPermissions((struct Memory *)(((unsigned char *)pMemory) + __nvoc_rtti_UserModeApi_Memory.offset), pDstGpu, pDstDevice); } static void __nvoc_thunk_RsResource_usrmodePreDestruct(struct UserModeApi *pResource) { @@ -165,16 +181,8 @@ return memIsDuplicate((struct Memory *)(((unsigned char *)pMemory) + __nvoc_rtti_UserModeApi_Memory.offset), hMemory, pDuplicate); } -static NV_STATUS __nvoc_thunk_RsResource_usrmodeUnmapFrom(struct UserModeApi *pResource, RS_RES_UNMAP_FROM_PARAMS *pParams) { - return resUnmapFrom((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_UserModeApi_RsResource.offset), pParams); -} - -static void __nvoc_thunk_RmResource_usrmodeControl_Epilogue(struct UserModeApi *pResource, CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { - rmresControl_Epilogue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_UserModeApi_RmResource.offset), pCallContext, pParams); -} - -static NV_STATUS __nvoc_thunk_RsResource_usrmodeControlLookup(struct UserModeApi *pResource, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams, const struct NVOC_EXPORTED_METHOD_DEF **ppEntry) { - return resControlLookup((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_UserModeApi_RsResource.offset), pParams, ppEntry); +static void __nvoc_thunk_RmResource_usrmodeControlSerialization_Epilogue(struct UserModeApi *pResource, CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + rmresControlSerialization_Epilogue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_UserModeApi_RmResource.offset), pCallContext, pParams); } static NV_STATUS __nvoc_thunk_Memory_usrmodeMap(struct UserModeApi *pMemory, CALL_CONTEXT *pCallContext, struct RS_CPU_MAP_PARAMS *pParams, RsCpuMapping *pCpuMapping) { @@ -197,21 +205,16 @@ PORT_UNREFERENCED_VARIABLE(pThis); } -void __nvoc_init_dataField_UserModeApi(UserModeApi *pThis, RmHalspecOwner *pRmhalspecowner) { - ChipHal *chipHal = &pRmhalspecowner->chipHal; - const unsigned long chipHal_HalVarIdx = (unsigned long)chipHal->__nvoc_HalVarIdx; +void __nvoc_init_dataField_UserModeApi(UserModeApi *pThis) { PORT_UNREFERENCED_VARIABLE(pThis); - PORT_UNREFERENCED_VARIABLE(pRmhalspecowner); - PORT_UNREFERENCED_VARIABLE(chipHal); - PORT_UNREFERENCED_VARIABLE(chipHal_HalVarIdx); } NV_STATUS __nvoc_ctor_Memory(Memory* , CALL_CONTEXT *, struct RS_RES_ALLOC_PARAMS_INTERNAL *); -NV_STATUS __nvoc_ctor_UserModeApi(UserModeApi *pThis, RmHalspecOwner *pRmhalspecowner, CALL_CONTEXT * arg_pCallContext, struct RS_RES_ALLOC_PARAMS_INTERNAL * arg_pParams) { +NV_STATUS __nvoc_ctor_UserModeApi(UserModeApi *pThis, CALL_CONTEXT * arg_pCallContext, struct RS_RES_ALLOC_PARAMS_INTERNAL * arg_pParams) { NV_STATUS status = NV_OK; status = __nvoc_ctor_Memory(&pThis->__nvoc_base_Memory, arg_pCallContext, arg_pParams); if (status != NV_OK) goto __nvoc_ctor_UserModeApi_fail_Memory; - __nvoc_init_dataField_UserModeApi(pThis, pRmhalspecowner); + __nvoc_init_dataField_UserModeApi(pThis); status = __nvoc_usrmodeConstruct(pThis, arg_pCallContext, arg_pParams); if (status != NV_OK) goto __nvoc_ctor_UserModeApi_fail__init; @@ -225,23 +228,8 @@ return status; } -static void __nvoc_init_funcTable_UserModeApi_1(UserModeApi *pThis, RmHalspecOwner *pRmhalspecowner) { - ChipHal *chipHal = &pRmhalspecowner->chipHal; - const unsigned long chipHal_HalVarIdx = (unsigned long)chipHal->__nvoc_HalVarIdx; +static void __nvoc_init_funcTable_UserModeApi_1(UserModeApi *pThis) { PORT_UNREFERENCED_VARIABLE(pThis); - PORT_UNREFERENCED_VARIABLE(pRmhalspecowner); - PORT_UNREFERENCED_VARIABLE(chipHal); - PORT_UNREFERENCED_VARIABLE(chipHal_HalVarIdx); - - // Hal function -- usrmodeConstructHal - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x01f0ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 */ - { - pThis->__usrmodeConstructHal__ = &usrmodeConstructHal_GV100; - } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ - { - pThis->__usrmodeConstructHal__ = &usrmodeConstructHal_GH100; - } pThis->__usrmodeCanCopy__ = &usrmodeCanCopy_IMPL; @@ -249,29 +237,37 @@ pThis->__usrmodeCheckMemInterUnmap__ = &__nvoc_thunk_Memory_usrmodeCheckMemInterUnmap; - pThis->__usrmodeControl__ = &__nvoc_thunk_Memory_usrmodeControl; + pThis->__usrmodeShareCallback__ = &__nvoc_thunk_RmResource_usrmodeShareCallback; - pThis->__usrmodeUnmap__ = &__nvoc_thunk_Memory_usrmodeUnmap; + pThis->__usrmodeMapTo__ = &__nvoc_thunk_RsResource_usrmodeMapTo; - pThis->__usrmodeGetMemInterMapParams__ = &__nvoc_thunk_Memory_usrmodeGetMemInterMapParams; + pThis->__usrmodeGetMapAddrSpace__ = &__nvoc_thunk_Memory_usrmodeGetMapAddrSpace; - pThis->__usrmodeGetMemoryMappingDescriptor__ = &__nvoc_thunk_Memory_usrmodeGetMemoryMappingDescriptor; + pThis->__usrmodeGetRefCount__ = &__nvoc_thunk_RsResource_usrmodeGetRefCount; - pThis->__usrmodeGetMapAddrSpace__ = &__nvoc_thunk_Memory_usrmodeGetMapAddrSpace; + pThis->__usrmodeAddAdditionalDependants__ = &__nvoc_thunk_RsResource_usrmodeAddAdditionalDependants; - pThis->__usrmodeShareCallback__ = &__nvoc_thunk_RmResource_usrmodeShareCallback; + pThis->__usrmodeControl_Prologue__ = &__nvoc_thunk_RmResource_usrmodeControl_Prologue; - pThis->__usrmodeControlFilter__ = &__nvoc_thunk_RsResource_usrmodeControlFilter; + pThis->__usrmodeIsGpuMapAllowed__ = &__nvoc_thunk_Memory_usrmodeIsGpuMapAllowed; - pThis->__usrmodeAddAdditionalDependants__ = &__nvoc_thunk_RsResource_usrmodeAddAdditionalDependants; + pThis->__usrmodeUnmapFrom__ = &__nvoc_thunk_RsResource_usrmodeUnmapFrom; - pThis->__usrmodeGetRefCount__ = &__nvoc_thunk_RsResource_usrmodeGetRefCount; + pThis->__usrmodeControl_Epilogue__ = &__nvoc_thunk_RmResource_usrmodeControl_Epilogue; - pThis->__usrmodeMapTo__ = &__nvoc_thunk_RsResource_usrmodeMapTo; + pThis->__usrmodeControlLookup__ = &__nvoc_thunk_RsResource_usrmodeControlLookup; - pThis->__usrmodeControl_Prologue__ = &__nvoc_thunk_RmResource_usrmodeControl_Prologue; + pThis->__usrmodeControl__ = &__nvoc_thunk_Memory_usrmodeControl; - pThis->__usrmodeIsGpuMapAllowed__ = &__nvoc_thunk_Memory_usrmodeIsGpuMapAllowed; + pThis->__usrmodeUnmap__ = &__nvoc_thunk_Memory_usrmodeUnmap; + + pThis->__usrmodeGetMemInterMapParams__ = &__nvoc_thunk_Memory_usrmodeGetMemInterMapParams; + + pThis->__usrmodeGetMemoryMappingDescriptor__ = &__nvoc_thunk_Memory_usrmodeGetMemoryMappingDescriptor; + + pThis->__usrmodeControlFilter__ = &__nvoc_thunk_RsResource_usrmodeControlFilter; + + pThis->__usrmodeControlSerialization_Prologue__ = &__nvoc_thunk_RmResource_usrmodeControlSerialization_Prologue; pThis->__usrmodeIsReady__ = &__nvoc_thunk_Memory_usrmodeIsReady; @@ -281,23 +277,19 @@ pThis->__usrmodeIsDuplicate__ = &__nvoc_thunk_Memory_usrmodeIsDuplicate; - pThis->__usrmodeUnmapFrom__ = &__nvoc_thunk_RsResource_usrmodeUnmapFrom; - - pThis->__usrmodeControl_Epilogue__ = &__nvoc_thunk_RmResource_usrmodeControl_Epilogue; - - pThis->__usrmodeControlLookup__ = &__nvoc_thunk_RsResource_usrmodeControlLookup; + pThis->__usrmodeControlSerialization_Epilogue__ = &__nvoc_thunk_RmResource_usrmodeControlSerialization_Epilogue; pThis->__usrmodeMap__ = &__nvoc_thunk_Memory_usrmodeMap; pThis->__usrmodeAccessCallback__ = &__nvoc_thunk_RmResource_usrmodeAccessCallback; } -void __nvoc_init_funcTable_UserModeApi(UserModeApi *pThis, RmHalspecOwner *pRmhalspecowner) { - __nvoc_init_funcTable_UserModeApi_1(pThis, pRmhalspecowner); +void __nvoc_init_funcTable_UserModeApi(UserModeApi *pThis) { + __nvoc_init_funcTable_UserModeApi_1(pThis); } void __nvoc_init_Memory(Memory*); -void __nvoc_init_UserModeApi(UserModeApi *pThis, RmHalspecOwner *pRmhalspecowner) { +void __nvoc_init_UserModeApi(UserModeApi *pThis) { pThis->__nvoc_pbase_UserModeApi = pThis; pThis->__nvoc_pbase_Object = &pThis->__nvoc_base_Memory.__nvoc_base_RmResource.__nvoc_base_RsResource.__nvoc_base_Object; pThis->__nvoc_pbase_RsResource = &pThis->__nvoc_base_Memory.__nvoc_base_RmResource.__nvoc_base_RsResource; @@ -305,22 +297,24 @@ pThis->__nvoc_pbase_RmResource = &pThis->__nvoc_base_Memory.__nvoc_base_RmResource; pThis->__nvoc_pbase_Memory = &pThis->__nvoc_base_Memory; __nvoc_init_Memory(&pThis->__nvoc_base_Memory); - __nvoc_init_funcTable_UserModeApi(pThis, pRmhalspecowner); + __nvoc_init_funcTable_UserModeApi(pThis); } NV_STATUS __nvoc_objCreate_UserModeApi(UserModeApi **ppThis, Dynamic *pParent, NvU32 createFlags, CALL_CONTEXT * arg_pCallContext, struct RS_RES_ALLOC_PARAMS_INTERNAL * arg_pParams) { NV_STATUS status; Object *pParentObj; UserModeApi *pThis; - RmHalspecOwner *pRmhalspecowner; - pThis = portMemAllocNonPaged(sizeof(UserModeApi)); - if (pThis == NULL) return NV_ERR_NO_MEMORY; + status = __nvoc_handleObjCreateMemAlloc(createFlags, sizeof(UserModeApi), (void**)&pThis, (void**)ppThis); + if (status != NV_OK) + return status; portMemSet(pThis, 0, sizeof(UserModeApi)); __nvoc_initRtti(staticCast(pThis, Dynamic), &__nvoc_class_def_UserModeApi); + pThis->__nvoc_base_Memory.__nvoc_base_RmResource.__nvoc_base_RsResource.__nvoc_base_Object.createFlags = createFlags; + if (pParent != NULL && !(createFlags & NVOC_OBJ_CREATE_FLAGS_PARENT_HALSPEC_ONLY)) { pParentObj = dynamicCast(pParent, Object); @@ -331,20 +325,22 @@ pThis->__nvoc_base_Memory.__nvoc_base_RmResource.__nvoc_base_RsResource.__nvoc_base_Object.pParent = NULL; } - if ((pRmhalspecowner = dynamicCast(pParent, RmHalspecOwner)) == NULL) - pRmhalspecowner = objFindAncestorOfType(RmHalspecOwner, pParent); - NV_ASSERT_OR_RETURN(pRmhalspecowner != NULL, NV_ERR_INVALID_ARGUMENT); - - __nvoc_init_UserModeApi(pThis, pRmhalspecowner); - status = __nvoc_ctor_UserModeApi(pThis, pRmhalspecowner, arg_pCallContext, arg_pParams); + __nvoc_init_UserModeApi(pThis); + status = __nvoc_ctor_UserModeApi(pThis, arg_pCallContext, arg_pParams); if (status != NV_OK) goto __nvoc_objCreate_UserModeApi_cleanup; *ppThis = pThis; + return NV_OK; __nvoc_objCreate_UserModeApi_cleanup: // do not call destructors here since the constructor already called them - portMemFree(pThis); + if (createFlags & NVOC_OBJ_CREATE_FLAGS_IN_PLACE_CONSTRUCT) + portMemSet(pThis, 0, sizeof(UserModeApi)); + else + portMemFree(pThis); + + // coverity[leaked_storage:FALSE] return status; } diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/generated/g_usermode_api_nvoc.h nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_usermode_api_nvoc.h --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/generated/g_usermode_api_nvoc.h 2023-10-25 20:27:22.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_usermode_api_nvoc.h 2024-03-05 22:18:49.000000000 +0000 @@ -58,28 +58,29 @@ struct RmResource *__nvoc_pbase_RmResource; struct Memory *__nvoc_pbase_Memory; struct UserModeApi *__nvoc_pbase_UserModeApi; - NV_STATUS (*__usrmodeConstructHal__)(struct UserModeApi *, CALL_CONTEXT *, struct RS_RES_ALLOC_PARAMS_INTERNAL *); NvBool (*__usrmodeCanCopy__)(struct UserModeApi *); NV_STATUS (*__usrmodeCheckMemInterUnmap__)(struct UserModeApi *, NvBool); + NvBool (*__usrmodeShareCallback__)(struct UserModeApi *, struct RsClient *, struct RsResourceRef *, RS_SHARE_POLICY *); + NV_STATUS (*__usrmodeMapTo__)(struct UserModeApi *, RS_RES_MAP_TO_PARAMS *); + NV_STATUS (*__usrmodeGetMapAddrSpace__)(struct UserModeApi *, CALL_CONTEXT *, NvU32, NV_ADDRESS_SPACE *); + NvU32 (*__usrmodeGetRefCount__)(struct UserModeApi *); + void (*__usrmodeAddAdditionalDependants__)(struct RsClient *, struct UserModeApi *, RsResourceRef *); + NV_STATUS (*__usrmodeControl_Prologue__)(struct UserModeApi *, CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); + NvBool (*__usrmodeIsGpuMapAllowed__)(struct UserModeApi *, struct OBJGPU *); + NV_STATUS (*__usrmodeUnmapFrom__)(struct UserModeApi *, RS_RES_UNMAP_FROM_PARAMS *); + void (*__usrmodeControl_Epilogue__)(struct UserModeApi *, CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); + NV_STATUS (*__usrmodeControlLookup__)(struct UserModeApi *, struct RS_RES_CONTROL_PARAMS_INTERNAL *, const struct NVOC_EXPORTED_METHOD_DEF **); NV_STATUS (*__usrmodeControl__)(struct UserModeApi *, CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); NV_STATUS (*__usrmodeUnmap__)(struct UserModeApi *, CALL_CONTEXT *, RsCpuMapping *); NV_STATUS (*__usrmodeGetMemInterMapParams__)(struct UserModeApi *, RMRES_MEM_INTER_MAP_PARAMS *); NV_STATUS (*__usrmodeGetMemoryMappingDescriptor__)(struct UserModeApi *, MEMORY_DESCRIPTOR **); - NV_STATUS (*__usrmodeGetMapAddrSpace__)(struct UserModeApi *, CALL_CONTEXT *, NvU32, NV_ADDRESS_SPACE *); - NvBool (*__usrmodeShareCallback__)(struct UserModeApi *, struct RsClient *, struct RsResourceRef *, RS_SHARE_POLICY *); NV_STATUS (*__usrmodeControlFilter__)(struct UserModeApi *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); - void (*__usrmodeAddAdditionalDependants__)(struct RsClient *, struct UserModeApi *, RsResourceRef *); - NvU32 (*__usrmodeGetRefCount__)(struct UserModeApi *); - NV_STATUS (*__usrmodeMapTo__)(struct UserModeApi *, RS_RES_MAP_TO_PARAMS *); - NV_STATUS (*__usrmodeControl_Prologue__)(struct UserModeApi *, CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); - NvBool (*__usrmodeIsGpuMapAllowed__)(struct UserModeApi *, struct OBJGPU *); + NV_STATUS (*__usrmodeControlSerialization_Prologue__)(struct UserModeApi *, CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); NV_STATUS (*__usrmodeIsReady__)(struct UserModeApi *, NvBool); - NV_STATUS (*__usrmodeCheckCopyPermissions__)(struct UserModeApi *, struct OBJGPU *, NvHandle); + NV_STATUS (*__usrmodeCheckCopyPermissions__)(struct UserModeApi *, struct OBJGPU *, struct Device *); void (*__usrmodePreDestruct__)(struct UserModeApi *); NV_STATUS (*__usrmodeIsDuplicate__)(struct UserModeApi *, NvHandle, NvBool *); - NV_STATUS (*__usrmodeUnmapFrom__)(struct UserModeApi *, RS_RES_UNMAP_FROM_PARAMS *); - void (*__usrmodeControl_Epilogue__)(struct UserModeApi *, CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); - NV_STATUS (*__usrmodeControlLookup__)(struct UserModeApi *, struct RS_RES_CONTROL_PARAMS_INTERNAL *, const struct NVOC_EXPORTED_METHOD_DEF **); + void (*__usrmodeControlSerialization_Epilogue__)(struct UserModeApi *, CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); NV_STATUS (*__usrmodeMap__)(struct UserModeApi *, CALL_CONTEXT *, struct RS_CPU_MAP_PARAMS *, RsCpuMapping *); NvBool (*__usrmodeAccessCallback__)(struct UserModeApi *, struct RsClient *, void *, RsAccessRight); }; @@ -112,39 +113,31 @@ #define __objCreate_UserModeApi(ppNewObj, pParent, createFlags, arg_pCallContext, arg_pParams) \ __nvoc_objCreate_UserModeApi((ppNewObj), staticCast((pParent), Dynamic), (createFlags), arg_pCallContext, arg_pParams) -#define usrmodeConstructHal(pUserModeApi, pCallContext, pParams) usrmodeConstructHal_DISPATCH(pUserModeApi, pCallContext, pParams) -#define usrmodeConstructHal_HAL(pUserModeApi, pCallContext, pParams) usrmodeConstructHal_DISPATCH(pUserModeApi, pCallContext, pParams) #define usrmodeCanCopy(pUserModeApi) usrmodeCanCopy_DISPATCH(pUserModeApi) #define usrmodeCheckMemInterUnmap(pMemory, bSubdeviceHandleProvided) usrmodeCheckMemInterUnmap_DISPATCH(pMemory, bSubdeviceHandleProvided) +#define usrmodeShareCallback(pResource, pInvokingClient, pParentRef, pSharePolicy) usrmodeShareCallback_DISPATCH(pResource, pInvokingClient, pParentRef, pSharePolicy) +#define usrmodeMapTo(pResource, pParams) usrmodeMapTo_DISPATCH(pResource, pParams) +#define usrmodeGetMapAddrSpace(pMemory, pCallContext, mapFlags, pAddrSpace) usrmodeGetMapAddrSpace_DISPATCH(pMemory, pCallContext, mapFlags, pAddrSpace) +#define usrmodeGetRefCount(pResource) usrmodeGetRefCount_DISPATCH(pResource) +#define usrmodeAddAdditionalDependants(pClient, pResource, pReference) usrmodeAddAdditionalDependants_DISPATCH(pClient, pResource, pReference) +#define usrmodeControl_Prologue(pResource, pCallContext, pParams) usrmodeControl_Prologue_DISPATCH(pResource, pCallContext, pParams) +#define usrmodeIsGpuMapAllowed(pMemory, pGpu) usrmodeIsGpuMapAllowed_DISPATCH(pMemory, pGpu) +#define usrmodeUnmapFrom(pResource, pParams) usrmodeUnmapFrom_DISPATCH(pResource, pParams) +#define usrmodeControl_Epilogue(pResource, pCallContext, pParams) usrmodeControl_Epilogue_DISPATCH(pResource, pCallContext, pParams) +#define usrmodeControlLookup(pResource, pParams, ppEntry) usrmodeControlLookup_DISPATCH(pResource, pParams, ppEntry) #define usrmodeControl(pMemory, pCallContext, pParams) usrmodeControl_DISPATCH(pMemory, pCallContext, pParams) #define usrmodeUnmap(pMemory, pCallContext, pCpuMapping) usrmodeUnmap_DISPATCH(pMemory, pCallContext, pCpuMapping) #define usrmodeGetMemInterMapParams(pMemory, pParams) usrmodeGetMemInterMapParams_DISPATCH(pMemory, pParams) #define usrmodeGetMemoryMappingDescriptor(pMemory, ppMemDesc) usrmodeGetMemoryMappingDescriptor_DISPATCH(pMemory, ppMemDesc) -#define usrmodeGetMapAddrSpace(pMemory, pCallContext, mapFlags, pAddrSpace) usrmodeGetMapAddrSpace_DISPATCH(pMemory, pCallContext, mapFlags, pAddrSpace) -#define usrmodeShareCallback(pResource, pInvokingClient, pParentRef, pSharePolicy) usrmodeShareCallback_DISPATCH(pResource, pInvokingClient, pParentRef, pSharePolicy) #define usrmodeControlFilter(pResource, pCallContext, pParams) usrmodeControlFilter_DISPATCH(pResource, pCallContext, pParams) -#define usrmodeAddAdditionalDependants(pClient, pResource, pReference) usrmodeAddAdditionalDependants_DISPATCH(pClient, pResource, pReference) -#define usrmodeGetRefCount(pResource) usrmodeGetRefCount_DISPATCH(pResource) -#define usrmodeMapTo(pResource, pParams) usrmodeMapTo_DISPATCH(pResource, pParams) -#define usrmodeControl_Prologue(pResource, pCallContext, pParams) usrmodeControl_Prologue_DISPATCH(pResource, pCallContext, pParams) -#define usrmodeIsGpuMapAllowed(pMemory, pGpu) usrmodeIsGpuMapAllowed_DISPATCH(pMemory, pGpu) +#define usrmodeControlSerialization_Prologue(pResource, pCallContext, pParams) usrmodeControlSerialization_Prologue_DISPATCH(pResource, pCallContext, pParams) #define usrmodeIsReady(pMemory, bCopyConstructorContext) usrmodeIsReady_DISPATCH(pMemory, bCopyConstructorContext) -#define usrmodeCheckCopyPermissions(pMemory, pDstGpu, hDstClientNvBool) usrmodeCheckCopyPermissions_DISPATCH(pMemory, pDstGpu, hDstClientNvBool) +#define usrmodeCheckCopyPermissions(pMemory, pDstGpu, pDstDevice) usrmodeCheckCopyPermissions_DISPATCH(pMemory, pDstGpu, pDstDevice) #define usrmodePreDestruct(pResource) usrmodePreDestruct_DISPATCH(pResource) #define usrmodeIsDuplicate(pMemory, hMemory, pDuplicate) usrmodeIsDuplicate_DISPATCH(pMemory, hMemory, pDuplicate) -#define usrmodeUnmapFrom(pResource, pParams) usrmodeUnmapFrom_DISPATCH(pResource, pParams) -#define usrmodeControl_Epilogue(pResource, pCallContext, pParams) usrmodeControl_Epilogue_DISPATCH(pResource, pCallContext, pParams) -#define usrmodeControlLookup(pResource, pParams, ppEntry) usrmodeControlLookup_DISPATCH(pResource, pParams, ppEntry) +#define usrmodeControlSerialization_Epilogue(pResource, pCallContext, pParams) usrmodeControlSerialization_Epilogue_DISPATCH(pResource, pCallContext, pParams) #define usrmodeMap(pMemory, pCallContext, pParams, pCpuMapping) usrmodeMap_DISPATCH(pMemory, pCallContext, pParams, pCpuMapping) #define usrmodeAccessCallback(pResource, pInvokingClient, pAllocParams, accessRight) usrmodeAccessCallback_DISPATCH(pResource, pInvokingClient, pAllocParams, accessRight) -NV_STATUS usrmodeConstructHal_GV100(struct UserModeApi *pUserModeApi, CALL_CONTEXT *pCallContext, struct RS_RES_ALLOC_PARAMS_INTERNAL *pParams); - -NV_STATUS usrmodeConstructHal_GH100(struct UserModeApi *pUserModeApi, CALL_CONTEXT *pCallContext, struct RS_RES_ALLOC_PARAMS_INTERNAL *pParams); - -static inline NV_STATUS usrmodeConstructHal_DISPATCH(struct UserModeApi *pUserModeApi, CALL_CONTEXT *pCallContext, struct RS_RES_ALLOC_PARAMS_INTERNAL *pParams) { - return pUserModeApi->__usrmodeConstructHal__(pUserModeApi, pCallContext, pParams); -} - NvBool usrmodeCanCopy_IMPL(struct UserModeApi *pUserModeApi); static inline NvBool usrmodeCanCopy_DISPATCH(struct UserModeApi *pUserModeApi) { @@ -155,60 +148,76 @@ return pMemory->__usrmodeCheckMemInterUnmap__(pMemory, bSubdeviceHandleProvided); } -static inline NV_STATUS usrmodeControl_DISPATCH(struct UserModeApi *pMemory, CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { - return pMemory->__usrmodeControl__(pMemory, pCallContext, pParams); +static inline NvBool usrmodeShareCallback_DISPATCH(struct UserModeApi *pResource, struct RsClient *pInvokingClient, struct RsResourceRef *pParentRef, RS_SHARE_POLICY *pSharePolicy) { + return pResource->__usrmodeShareCallback__(pResource, pInvokingClient, pParentRef, pSharePolicy); } -static inline NV_STATUS usrmodeUnmap_DISPATCH(struct UserModeApi *pMemory, CALL_CONTEXT *pCallContext, RsCpuMapping *pCpuMapping) { - return pMemory->__usrmodeUnmap__(pMemory, pCallContext, pCpuMapping); +static inline NV_STATUS usrmodeMapTo_DISPATCH(struct UserModeApi *pResource, RS_RES_MAP_TO_PARAMS *pParams) { + return pResource->__usrmodeMapTo__(pResource, pParams); } -static inline NV_STATUS usrmodeGetMemInterMapParams_DISPATCH(struct UserModeApi *pMemory, RMRES_MEM_INTER_MAP_PARAMS *pParams) { - return pMemory->__usrmodeGetMemInterMapParams__(pMemory, pParams); +static inline NV_STATUS usrmodeGetMapAddrSpace_DISPATCH(struct UserModeApi *pMemory, CALL_CONTEXT *pCallContext, NvU32 mapFlags, NV_ADDRESS_SPACE *pAddrSpace) { + return pMemory->__usrmodeGetMapAddrSpace__(pMemory, pCallContext, mapFlags, pAddrSpace); } -static inline NV_STATUS usrmodeGetMemoryMappingDescriptor_DISPATCH(struct UserModeApi *pMemory, MEMORY_DESCRIPTOR **ppMemDesc) { - return pMemory->__usrmodeGetMemoryMappingDescriptor__(pMemory, ppMemDesc); +static inline NvU32 usrmodeGetRefCount_DISPATCH(struct UserModeApi *pResource) { + return pResource->__usrmodeGetRefCount__(pResource); } -static inline NV_STATUS usrmodeGetMapAddrSpace_DISPATCH(struct UserModeApi *pMemory, CALL_CONTEXT *pCallContext, NvU32 mapFlags, NV_ADDRESS_SPACE *pAddrSpace) { - return pMemory->__usrmodeGetMapAddrSpace__(pMemory, pCallContext, mapFlags, pAddrSpace); +static inline void usrmodeAddAdditionalDependants_DISPATCH(struct RsClient *pClient, struct UserModeApi *pResource, RsResourceRef *pReference) { + pResource->__usrmodeAddAdditionalDependants__(pClient, pResource, pReference); } -static inline NvBool usrmodeShareCallback_DISPATCH(struct UserModeApi *pResource, struct RsClient *pInvokingClient, struct RsResourceRef *pParentRef, RS_SHARE_POLICY *pSharePolicy) { - return pResource->__usrmodeShareCallback__(pResource, pInvokingClient, pParentRef, pSharePolicy); +static inline NV_STATUS usrmodeControl_Prologue_DISPATCH(struct UserModeApi *pResource, CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return pResource->__usrmodeControl_Prologue__(pResource, pCallContext, pParams); } -static inline NV_STATUS usrmodeControlFilter_DISPATCH(struct UserModeApi *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { - return pResource->__usrmodeControlFilter__(pResource, pCallContext, pParams); +static inline NvBool usrmodeIsGpuMapAllowed_DISPATCH(struct UserModeApi *pMemory, struct OBJGPU *pGpu) { + return pMemory->__usrmodeIsGpuMapAllowed__(pMemory, pGpu); } -static inline void usrmodeAddAdditionalDependants_DISPATCH(struct RsClient *pClient, struct UserModeApi *pResource, RsResourceRef *pReference) { - pResource->__usrmodeAddAdditionalDependants__(pClient, pResource, pReference); +static inline NV_STATUS usrmodeUnmapFrom_DISPATCH(struct UserModeApi *pResource, RS_RES_UNMAP_FROM_PARAMS *pParams) { + return pResource->__usrmodeUnmapFrom__(pResource, pParams); } -static inline NvU32 usrmodeGetRefCount_DISPATCH(struct UserModeApi *pResource) { - return pResource->__usrmodeGetRefCount__(pResource); +static inline void usrmodeControl_Epilogue_DISPATCH(struct UserModeApi *pResource, CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + pResource->__usrmodeControl_Epilogue__(pResource, pCallContext, pParams); } -static inline NV_STATUS usrmodeMapTo_DISPATCH(struct UserModeApi *pResource, RS_RES_MAP_TO_PARAMS *pParams) { - return pResource->__usrmodeMapTo__(pResource, pParams); +static inline NV_STATUS usrmodeControlLookup_DISPATCH(struct UserModeApi *pResource, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams, const struct NVOC_EXPORTED_METHOD_DEF **ppEntry) { + return pResource->__usrmodeControlLookup__(pResource, pParams, ppEntry); } -static inline NV_STATUS usrmodeControl_Prologue_DISPATCH(struct UserModeApi *pResource, CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { - return pResource->__usrmodeControl_Prologue__(pResource, pCallContext, pParams); +static inline NV_STATUS usrmodeControl_DISPATCH(struct UserModeApi *pMemory, CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return pMemory->__usrmodeControl__(pMemory, pCallContext, pParams); } -static inline NvBool usrmodeIsGpuMapAllowed_DISPATCH(struct UserModeApi *pMemory, struct OBJGPU *pGpu) { - return pMemory->__usrmodeIsGpuMapAllowed__(pMemory, pGpu); +static inline NV_STATUS usrmodeUnmap_DISPATCH(struct UserModeApi *pMemory, CALL_CONTEXT *pCallContext, RsCpuMapping *pCpuMapping) { + return pMemory->__usrmodeUnmap__(pMemory, pCallContext, pCpuMapping); +} + +static inline NV_STATUS usrmodeGetMemInterMapParams_DISPATCH(struct UserModeApi *pMemory, RMRES_MEM_INTER_MAP_PARAMS *pParams) { + return pMemory->__usrmodeGetMemInterMapParams__(pMemory, pParams); +} + +static inline NV_STATUS usrmodeGetMemoryMappingDescriptor_DISPATCH(struct UserModeApi *pMemory, MEMORY_DESCRIPTOR **ppMemDesc) { + return pMemory->__usrmodeGetMemoryMappingDescriptor__(pMemory, ppMemDesc); +} + +static inline NV_STATUS usrmodeControlFilter_DISPATCH(struct UserModeApi *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return pResource->__usrmodeControlFilter__(pResource, pCallContext, pParams); +} + +static inline NV_STATUS usrmodeControlSerialization_Prologue_DISPATCH(struct UserModeApi *pResource, CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return pResource->__usrmodeControlSerialization_Prologue__(pResource, pCallContext, pParams); } static inline NV_STATUS usrmodeIsReady_DISPATCH(struct UserModeApi *pMemory, NvBool bCopyConstructorContext) { return pMemory->__usrmodeIsReady__(pMemory, bCopyConstructorContext); } -static inline NV_STATUS usrmodeCheckCopyPermissions_DISPATCH(struct UserModeApi *pMemory, struct OBJGPU *pDstGpu, NvHandle hDstClientNvBool) { - return pMemory->__usrmodeCheckCopyPermissions__(pMemory, pDstGpu, hDstClientNvBool); +static inline NV_STATUS usrmodeCheckCopyPermissions_DISPATCH(struct UserModeApi *pMemory, struct OBJGPU *pDstGpu, struct Device *pDstDevice) { + return pMemory->__usrmodeCheckCopyPermissions__(pMemory, pDstGpu, pDstDevice); } static inline void usrmodePreDestruct_DISPATCH(struct UserModeApi *pResource) { @@ -219,16 +228,8 @@ return pMemory->__usrmodeIsDuplicate__(pMemory, hMemory, pDuplicate); } -static inline NV_STATUS usrmodeUnmapFrom_DISPATCH(struct UserModeApi *pResource, RS_RES_UNMAP_FROM_PARAMS *pParams) { - return pResource->__usrmodeUnmapFrom__(pResource, pParams); -} - -static inline void usrmodeControl_Epilogue_DISPATCH(struct UserModeApi *pResource, CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { - pResource->__usrmodeControl_Epilogue__(pResource, pCallContext, pParams); -} - -static inline NV_STATUS usrmodeControlLookup_DISPATCH(struct UserModeApi *pResource, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams, const struct NVOC_EXPORTED_METHOD_DEF **ppEntry) { - return pResource->__usrmodeControlLookup__(pResource, pParams, ppEntry); +static inline void usrmodeControlSerialization_Epilogue_DISPATCH(struct UserModeApi *pResource, CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + pResource->__usrmodeControlSerialization_Epilogue__(pResource, pCallContext, pParams); } static inline NV_STATUS usrmodeMap_DISPATCH(struct UserModeApi *pMemory, CALL_CONTEXT *pCallContext, struct RS_CPU_MAP_PARAMS *pParams, RsCpuMapping *pCpuMapping) { diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/generated/g_uvm_channel_retainer_nvoc.c nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_uvm_channel_retainer_nvoc.c --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/generated/g_uvm_channel_retainer_nvoc.c 2023-10-25 20:27:22.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_uvm_channel_retainer_nvoc.c 2024-03-05 22:18:49.000000000 +0000 @@ -97,84 +97,92 @@ return gpuresShareCallback((struct GpuResource *)(((unsigned char *)pGpuResource) + __nvoc_rtti_UvmChannelRetainer_GpuResource.offset), pInvokingClient, pParentRef, pSharePolicy); } -static NV_STATUS __nvoc_thunk_GpuResource_uvmchanrtnrControl(struct UvmChannelRetainer *pGpuResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { - return gpuresControl((struct GpuResource *)(((unsigned char *)pGpuResource) + __nvoc_rtti_UvmChannelRetainer_GpuResource.offset), pCallContext, pParams); +static NV_STATUS __nvoc_thunk_RmResource_uvmchanrtnrCheckMemInterUnmap(struct UvmChannelRetainer *pRmResource, NvBool bSubdeviceHandleProvided) { + return rmresCheckMemInterUnmap((struct RmResource *)(((unsigned char *)pRmResource) + __nvoc_rtti_UvmChannelRetainer_RmResource.offset), bSubdeviceHandleProvided); } -static NV_STATUS __nvoc_thunk_GpuResource_uvmchanrtnrUnmap(struct UvmChannelRetainer *pGpuResource, struct CALL_CONTEXT *pCallContext, struct RsCpuMapping *pCpuMapping) { - return gpuresUnmap((struct GpuResource *)(((unsigned char *)pGpuResource) + __nvoc_rtti_UvmChannelRetainer_GpuResource.offset), pCallContext, pCpuMapping); +static NV_STATUS __nvoc_thunk_RsResource_uvmchanrtnrMapTo(struct UvmChannelRetainer *pResource, RS_RES_MAP_TO_PARAMS *pParams) { + return resMapTo((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_UvmChannelRetainer_RsResource.offset), pParams); } -static NV_STATUS __nvoc_thunk_RmResource_uvmchanrtnrGetMemInterMapParams(struct UvmChannelRetainer *pRmResource, RMRES_MEM_INTER_MAP_PARAMS *pParams) { - return rmresGetMemInterMapParams((struct RmResource *)(((unsigned char *)pRmResource) + __nvoc_rtti_UvmChannelRetainer_RmResource.offset), pParams); +static NV_STATUS __nvoc_thunk_GpuResource_uvmchanrtnrGetMapAddrSpace(struct UvmChannelRetainer *pGpuResource, struct CALL_CONTEXT *pCallContext, NvU32 mapFlags, NV_ADDRESS_SPACE *pAddrSpace) { + return gpuresGetMapAddrSpace((struct GpuResource *)(((unsigned char *)pGpuResource) + __nvoc_rtti_UvmChannelRetainer_GpuResource.offset), pCallContext, mapFlags, pAddrSpace); } -static NV_STATUS __nvoc_thunk_RmResource_uvmchanrtnrGetMemoryMappingDescriptor(struct UvmChannelRetainer *pRmResource, struct MEMORY_DESCRIPTOR **ppMemDesc) { - return rmresGetMemoryMappingDescriptor((struct RmResource *)(((unsigned char *)pRmResource) + __nvoc_rtti_UvmChannelRetainer_RmResource.offset), ppMemDesc); +static NvU32 __nvoc_thunk_RsResource_uvmchanrtnrGetRefCount(struct UvmChannelRetainer *pResource) { + return resGetRefCount((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_UvmChannelRetainer_RsResource.offset)); } -static NV_STATUS __nvoc_thunk_GpuResource_uvmchanrtnrGetMapAddrSpace(struct UvmChannelRetainer *pGpuResource, struct CALL_CONTEXT *pCallContext, NvU32 mapFlags, NV_ADDRESS_SPACE *pAddrSpace) { - return gpuresGetMapAddrSpace((struct GpuResource *)(((unsigned char *)pGpuResource) + __nvoc_rtti_UvmChannelRetainer_GpuResource.offset), pCallContext, mapFlags, pAddrSpace); +static void __nvoc_thunk_RsResource_uvmchanrtnrAddAdditionalDependants(struct RsClient *pClient, struct UvmChannelRetainer *pResource, RsResourceRef *pReference) { + resAddAdditionalDependants(pClient, (struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_UvmChannelRetainer_RsResource.offset), pReference); } -static NvHandle __nvoc_thunk_GpuResource_uvmchanrtnrGetInternalObjectHandle(struct UvmChannelRetainer *pGpuResource) { - return gpuresGetInternalObjectHandle((struct GpuResource *)(((unsigned char *)pGpuResource) + __nvoc_rtti_UvmChannelRetainer_GpuResource.offset)); +static NV_STATUS __nvoc_thunk_RmResource_uvmchanrtnrControl_Prologue(struct UvmChannelRetainer *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return rmresControl_Prologue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_UvmChannelRetainer_RmResource.offset), pCallContext, pParams); } -static NV_STATUS __nvoc_thunk_RsResource_uvmchanrtnrControlFilter(struct UvmChannelRetainer *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { - return resControlFilter((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_UvmChannelRetainer_RsResource.offset), pCallContext, pParams); +static NV_STATUS __nvoc_thunk_GpuResource_uvmchanrtnrGetRegBaseOffsetAndSize(struct UvmChannelRetainer *pGpuResource, struct OBJGPU *pGpu, NvU32 *pOffset, NvU32 *pSize) { + return gpuresGetRegBaseOffsetAndSize((struct GpuResource *)(((unsigned char *)pGpuResource) + __nvoc_rtti_UvmChannelRetainer_GpuResource.offset), pGpu, pOffset, pSize); } -static void __nvoc_thunk_RsResource_uvmchanrtnrAddAdditionalDependants(struct RsClient *pClient, struct UvmChannelRetainer *pResource, RsResourceRef *pReference) { - resAddAdditionalDependants(pClient, (struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_UvmChannelRetainer_RsResource.offset), pReference); +static NV_STATUS __nvoc_thunk_GpuResource_uvmchanrtnrInternalControlForward(struct UvmChannelRetainer *pGpuResource, NvU32 command, void *pParams, NvU32 size) { + return gpuresInternalControlForward((struct GpuResource *)(((unsigned char *)pGpuResource) + __nvoc_rtti_UvmChannelRetainer_GpuResource.offset), command, pParams, size); } -static NvU32 __nvoc_thunk_RsResource_uvmchanrtnrGetRefCount(struct UvmChannelRetainer *pResource) { - return resGetRefCount((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_UvmChannelRetainer_RsResource.offset)); +static NV_STATUS __nvoc_thunk_RsResource_uvmchanrtnrUnmapFrom(struct UvmChannelRetainer *pResource, RS_RES_UNMAP_FROM_PARAMS *pParams) { + return resUnmapFrom((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_UvmChannelRetainer_RsResource.offset), pParams); } -static NV_STATUS __nvoc_thunk_RmResource_uvmchanrtnrCheckMemInterUnmap(struct UvmChannelRetainer *pRmResource, NvBool bSubdeviceHandleProvided) { - return rmresCheckMemInterUnmap((struct RmResource *)(((unsigned char *)pRmResource) + __nvoc_rtti_UvmChannelRetainer_RmResource.offset), bSubdeviceHandleProvided); +static void __nvoc_thunk_RmResource_uvmchanrtnrControl_Epilogue(struct UvmChannelRetainer *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + rmresControl_Epilogue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_UvmChannelRetainer_RmResource.offset), pCallContext, pParams); } -static NV_STATUS __nvoc_thunk_RsResource_uvmchanrtnrMapTo(struct UvmChannelRetainer *pResource, RS_RES_MAP_TO_PARAMS *pParams) { - return resMapTo((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_UvmChannelRetainer_RsResource.offset), pParams); +static NV_STATUS __nvoc_thunk_RsResource_uvmchanrtnrControlLookup(struct UvmChannelRetainer *pResource, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams, const struct NVOC_EXPORTED_METHOD_DEF **ppEntry) { + return resControlLookup((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_UvmChannelRetainer_RsResource.offset), pParams, ppEntry); } -static NV_STATUS __nvoc_thunk_RmResource_uvmchanrtnrControl_Prologue(struct UvmChannelRetainer *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { - return rmresControl_Prologue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_UvmChannelRetainer_RmResource.offset), pCallContext, pParams); +static NvHandle __nvoc_thunk_GpuResource_uvmchanrtnrGetInternalObjectHandle(struct UvmChannelRetainer *pGpuResource) { + return gpuresGetInternalObjectHandle((struct GpuResource *)(((unsigned char *)pGpuResource) + __nvoc_rtti_UvmChannelRetainer_GpuResource.offset)); } -static NV_STATUS __nvoc_thunk_GpuResource_uvmchanrtnrGetRegBaseOffsetAndSize(struct UvmChannelRetainer *pGpuResource, struct OBJGPU *pGpu, NvU32 *pOffset, NvU32 *pSize) { - return gpuresGetRegBaseOffsetAndSize((struct GpuResource *)(((unsigned char *)pGpuResource) + __nvoc_rtti_UvmChannelRetainer_GpuResource.offset), pGpu, pOffset, pSize); +static NV_STATUS __nvoc_thunk_GpuResource_uvmchanrtnrControl(struct UvmChannelRetainer *pGpuResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return gpuresControl((struct GpuResource *)(((unsigned char *)pGpuResource) + __nvoc_rtti_UvmChannelRetainer_GpuResource.offset), pCallContext, pParams); } -static NvBool __nvoc_thunk_RsResource_uvmchanrtnrCanCopy(struct UvmChannelRetainer *pResource) { - return resCanCopy((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_UvmChannelRetainer_RsResource.offset)); +static NV_STATUS __nvoc_thunk_GpuResource_uvmchanrtnrUnmap(struct UvmChannelRetainer *pGpuResource, struct CALL_CONTEXT *pCallContext, struct RsCpuMapping *pCpuMapping) { + return gpuresUnmap((struct GpuResource *)(((unsigned char *)pGpuResource) + __nvoc_rtti_UvmChannelRetainer_GpuResource.offset), pCallContext, pCpuMapping); } -static NV_STATUS __nvoc_thunk_GpuResource_uvmchanrtnrInternalControlForward(struct UvmChannelRetainer *pGpuResource, NvU32 command, void *pParams, NvU32 size) { - return gpuresInternalControlForward((struct GpuResource *)(((unsigned char *)pGpuResource) + __nvoc_rtti_UvmChannelRetainer_GpuResource.offset), command, pParams, size); +static NV_STATUS __nvoc_thunk_RmResource_uvmchanrtnrGetMemInterMapParams(struct UvmChannelRetainer *pRmResource, RMRES_MEM_INTER_MAP_PARAMS *pParams) { + return rmresGetMemInterMapParams((struct RmResource *)(((unsigned char *)pRmResource) + __nvoc_rtti_UvmChannelRetainer_RmResource.offset), pParams); } -static void __nvoc_thunk_RsResource_uvmchanrtnrPreDestruct(struct UvmChannelRetainer *pResource) { - resPreDestruct((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_UvmChannelRetainer_RsResource.offset)); +static NV_STATUS __nvoc_thunk_RmResource_uvmchanrtnrGetMemoryMappingDescriptor(struct UvmChannelRetainer *pRmResource, struct MEMORY_DESCRIPTOR **ppMemDesc) { + return rmresGetMemoryMappingDescriptor((struct RmResource *)(((unsigned char *)pRmResource) + __nvoc_rtti_UvmChannelRetainer_RmResource.offset), ppMemDesc); } -static NV_STATUS __nvoc_thunk_RsResource_uvmchanrtnrUnmapFrom(struct UvmChannelRetainer *pResource, RS_RES_UNMAP_FROM_PARAMS *pParams) { - return resUnmapFrom((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_UvmChannelRetainer_RsResource.offset), pParams); +static NV_STATUS __nvoc_thunk_RsResource_uvmchanrtnrControlFilter(struct UvmChannelRetainer *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return resControlFilter((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_UvmChannelRetainer_RsResource.offset), pCallContext, pParams); } -static NV_STATUS __nvoc_thunk_RsResource_uvmchanrtnrIsDuplicate(struct UvmChannelRetainer *pResource, NvHandle hMemory, NvBool *pDuplicate) { - return resIsDuplicate((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_UvmChannelRetainer_RsResource.offset), hMemory, pDuplicate); +static NV_STATUS __nvoc_thunk_RmResource_uvmchanrtnrControlSerialization_Prologue(struct UvmChannelRetainer *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return rmresControlSerialization_Prologue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_UvmChannelRetainer_RmResource.offset), pCallContext, pParams); } -static void __nvoc_thunk_RmResource_uvmchanrtnrControl_Epilogue(struct UvmChannelRetainer *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { - rmresControl_Epilogue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_UvmChannelRetainer_RmResource.offset), pCallContext, pParams); +static NvBool __nvoc_thunk_RsResource_uvmchanrtnrCanCopy(struct UvmChannelRetainer *pResource) { + return resCanCopy((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_UvmChannelRetainer_RsResource.offset)); } -static NV_STATUS __nvoc_thunk_RsResource_uvmchanrtnrControlLookup(struct UvmChannelRetainer *pResource, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams, const struct NVOC_EXPORTED_METHOD_DEF **ppEntry) { - return resControlLookup((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_UvmChannelRetainer_RsResource.offset), pParams, ppEntry); +static void __nvoc_thunk_RsResource_uvmchanrtnrPreDestruct(struct UvmChannelRetainer *pResource) { + resPreDestruct((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_UvmChannelRetainer_RsResource.offset)); +} + +static NV_STATUS __nvoc_thunk_RsResource_uvmchanrtnrIsDuplicate(struct UvmChannelRetainer *pResource, NvHandle hMemory, NvBool *pDuplicate) { + return resIsDuplicate((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_UvmChannelRetainer_RsResource.offset), hMemory, pDuplicate); +} + +static void __nvoc_thunk_RmResource_uvmchanrtnrControlSerialization_Epilogue(struct UvmChannelRetainer *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + rmresControlSerialization_Epilogue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_UvmChannelRetainer_RmResource.offset), pCallContext, pParams); } static NV_STATUS __nvoc_thunk_GpuResource_uvmchanrtnrMap(struct UvmChannelRetainer *pGpuResource, struct CALL_CONTEXT *pCallContext, struct RS_CPU_MAP_PARAMS *pParams, struct RsCpuMapping *pCpuMapping) { @@ -236,45 +244,49 @@ pThis->__uvmchanrtnrShareCallback__ = &__nvoc_thunk_GpuResource_uvmchanrtnrShareCallback; - pThis->__uvmchanrtnrControl__ = &__nvoc_thunk_GpuResource_uvmchanrtnrControl; + pThis->__uvmchanrtnrCheckMemInterUnmap__ = &__nvoc_thunk_RmResource_uvmchanrtnrCheckMemInterUnmap; - pThis->__uvmchanrtnrUnmap__ = &__nvoc_thunk_GpuResource_uvmchanrtnrUnmap; + pThis->__uvmchanrtnrMapTo__ = &__nvoc_thunk_RsResource_uvmchanrtnrMapTo; - pThis->__uvmchanrtnrGetMemInterMapParams__ = &__nvoc_thunk_RmResource_uvmchanrtnrGetMemInterMapParams; + pThis->__uvmchanrtnrGetMapAddrSpace__ = &__nvoc_thunk_GpuResource_uvmchanrtnrGetMapAddrSpace; - pThis->__uvmchanrtnrGetMemoryMappingDescriptor__ = &__nvoc_thunk_RmResource_uvmchanrtnrGetMemoryMappingDescriptor; + pThis->__uvmchanrtnrGetRefCount__ = &__nvoc_thunk_RsResource_uvmchanrtnrGetRefCount; - pThis->__uvmchanrtnrGetMapAddrSpace__ = &__nvoc_thunk_GpuResource_uvmchanrtnrGetMapAddrSpace; + pThis->__uvmchanrtnrAddAdditionalDependants__ = &__nvoc_thunk_RsResource_uvmchanrtnrAddAdditionalDependants; - pThis->__uvmchanrtnrGetInternalObjectHandle__ = &__nvoc_thunk_GpuResource_uvmchanrtnrGetInternalObjectHandle; + pThis->__uvmchanrtnrControl_Prologue__ = &__nvoc_thunk_RmResource_uvmchanrtnrControl_Prologue; - pThis->__uvmchanrtnrControlFilter__ = &__nvoc_thunk_RsResource_uvmchanrtnrControlFilter; + pThis->__uvmchanrtnrGetRegBaseOffsetAndSize__ = &__nvoc_thunk_GpuResource_uvmchanrtnrGetRegBaseOffsetAndSize; - pThis->__uvmchanrtnrAddAdditionalDependants__ = &__nvoc_thunk_RsResource_uvmchanrtnrAddAdditionalDependants; + pThis->__uvmchanrtnrInternalControlForward__ = &__nvoc_thunk_GpuResource_uvmchanrtnrInternalControlForward; - pThis->__uvmchanrtnrGetRefCount__ = &__nvoc_thunk_RsResource_uvmchanrtnrGetRefCount; + pThis->__uvmchanrtnrUnmapFrom__ = &__nvoc_thunk_RsResource_uvmchanrtnrUnmapFrom; - pThis->__uvmchanrtnrCheckMemInterUnmap__ = &__nvoc_thunk_RmResource_uvmchanrtnrCheckMemInterUnmap; + pThis->__uvmchanrtnrControl_Epilogue__ = &__nvoc_thunk_RmResource_uvmchanrtnrControl_Epilogue; - pThis->__uvmchanrtnrMapTo__ = &__nvoc_thunk_RsResource_uvmchanrtnrMapTo; + pThis->__uvmchanrtnrControlLookup__ = &__nvoc_thunk_RsResource_uvmchanrtnrControlLookup; - pThis->__uvmchanrtnrControl_Prologue__ = &__nvoc_thunk_RmResource_uvmchanrtnrControl_Prologue; + pThis->__uvmchanrtnrGetInternalObjectHandle__ = &__nvoc_thunk_GpuResource_uvmchanrtnrGetInternalObjectHandle; - pThis->__uvmchanrtnrGetRegBaseOffsetAndSize__ = &__nvoc_thunk_GpuResource_uvmchanrtnrGetRegBaseOffsetAndSize; + pThis->__uvmchanrtnrControl__ = &__nvoc_thunk_GpuResource_uvmchanrtnrControl; - pThis->__uvmchanrtnrCanCopy__ = &__nvoc_thunk_RsResource_uvmchanrtnrCanCopy; + pThis->__uvmchanrtnrUnmap__ = &__nvoc_thunk_GpuResource_uvmchanrtnrUnmap; - pThis->__uvmchanrtnrInternalControlForward__ = &__nvoc_thunk_GpuResource_uvmchanrtnrInternalControlForward; + pThis->__uvmchanrtnrGetMemInterMapParams__ = &__nvoc_thunk_RmResource_uvmchanrtnrGetMemInterMapParams; - pThis->__uvmchanrtnrPreDestruct__ = &__nvoc_thunk_RsResource_uvmchanrtnrPreDestruct; + pThis->__uvmchanrtnrGetMemoryMappingDescriptor__ = &__nvoc_thunk_RmResource_uvmchanrtnrGetMemoryMappingDescriptor; - pThis->__uvmchanrtnrUnmapFrom__ = &__nvoc_thunk_RsResource_uvmchanrtnrUnmapFrom; + pThis->__uvmchanrtnrControlFilter__ = &__nvoc_thunk_RsResource_uvmchanrtnrControlFilter; - pThis->__uvmchanrtnrIsDuplicate__ = &__nvoc_thunk_RsResource_uvmchanrtnrIsDuplicate; + pThis->__uvmchanrtnrControlSerialization_Prologue__ = &__nvoc_thunk_RmResource_uvmchanrtnrControlSerialization_Prologue; - pThis->__uvmchanrtnrControl_Epilogue__ = &__nvoc_thunk_RmResource_uvmchanrtnrControl_Epilogue; + pThis->__uvmchanrtnrCanCopy__ = &__nvoc_thunk_RsResource_uvmchanrtnrCanCopy; - pThis->__uvmchanrtnrControlLookup__ = &__nvoc_thunk_RsResource_uvmchanrtnrControlLookup; + pThis->__uvmchanrtnrPreDestruct__ = &__nvoc_thunk_RsResource_uvmchanrtnrPreDestruct; + + pThis->__uvmchanrtnrIsDuplicate__ = &__nvoc_thunk_RsResource_uvmchanrtnrIsDuplicate; + + pThis->__uvmchanrtnrControlSerialization_Epilogue__ = &__nvoc_thunk_RmResource_uvmchanrtnrControlSerialization_Epilogue; pThis->__uvmchanrtnrMap__ = &__nvoc_thunk_GpuResource_uvmchanrtnrMap; @@ -303,13 +315,16 @@ UvmChannelRetainer *pThis; RmHalspecOwner *pRmhalspecowner; - pThis = portMemAllocNonPaged(sizeof(UvmChannelRetainer)); - if (pThis == NULL) return NV_ERR_NO_MEMORY; + status = __nvoc_handleObjCreateMemAlloc(createFlags, sizeof(UvmChannelRetainer), (void**)&pThis, (void**)ppThis); + if (status != NV_OK) + return status; portMemSet(pThis, 0, sizeof(UvmChannelRetainer)); __nvoc_initRtti(staticCast(pThis, Dynamic), &__nvoc_class_def_UvmChannelRetainer); + pThis->__nvoc_base_GpuResource.__nvoc_base_RmResource.__nvoc_base_RsResource.__nvoc_base_Object.createFlags = createFlags; + if (pParent != NULL && !(createFlags & NVOC_OBJ_CREATE_FLAGS_PARENT_HALSPEC_ONLY)) { pParentObj = dynamicCast(pParent, Object); @@ -329,11 +344,17 @@ if (status != NV_OK) goto __nvoc_objCreate_UvmChannelRetainer_cleanup; *ppThis = pThis; + return NV_OK; __nvoc_objCreate_UvmChannelRetainer_cleanup: // do not call destructors here since the constructor already called them - portMemFree(pThis); + if (createFlags & NVOC_OBJ_CREATE_FLAGS_IN_PLACE_CONSTRUCT) + portMemSet(pThis, 0, sizeof(UvmChannelRetainer)); + else + portMemFree(pThis); + + // coverity[leaked_storage:FALSE] return status; } diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/generated/g_uvm_channel_retainer_nvoc.h nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_uvm_channel_retainer_nvoc.h --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/generated/g_uvm_channel_retainer_nvoc.h 2023-10-25 20:27:22.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_uvm_channel_retainer_nvoc.h 2024-03-05 22:18:49.000000000 +0000 @@ -69,26 +69,28 @@ struct GpuResource *__nvoc_pbase_GpuResource; struct UvmChannelRetainer *__nvoc_pbase_UvmChannelRetainer; NvBool (*__uvmchanrtnrShareCallback__)(struct UvmChannelRetainer *, struct RsClient *, struct RsResourceRef *, RS_SHARE_POLICY *); - NV_STATUS (*__uvmchanrtnrControl__)(struct UvmChannelRetainer *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); - NV_STATUS (*__uvmchanrtnrUnmap__)(struct UvmChannelRetainer *, struct CALL_CONTEXT *, struct RsCpuMapping *); - NV_STATUS (*__uvmchanrtnrGetMemInterMapParams__)(struct UvmChannelRetainer *, RMRES_MEM_INTER_MAP_PARAMS *); - NV_STATUS (*__uvmchanrtnrGetMemoryMappingDescriptor__)(struct UvmChannelRetainer *, struct MEMORY_DESCRIPTOR **); - NV_STATUS (*__uvmchanrtnrGetMapAddrSpace__)(struct UvmChannelRetainer *, struct CALL_CONTEXT *, NvU32, NV_ADDRESS_SPACE *); - NvHandle (*__uvmchanrtnrGetInternalObjectHandle__)(struct UvmChannelRetainer *); - NV_STATUS (*__uvmchanrtnrControlFilter__)(struct UvmChannelRetainer *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); - void (*__uvmchanrtnrAddAdditionalDependants__)(struct RsClient *, struct UvmChannelRetainer *, RsResourceRef *); - NvU32 (*__uvmchanrtnrGetRefCount__)(struct UvmChannelRetainer *); NV_STATUS (*__uvmchanrtnrCheckMemInterUnmap__)(struct UvmChannelRetainer *, NvBool); NV_STATUS (*__uvmchanrtnrMapTo__)(struct UvmChannelRetainer *, RS_RES_MAP_TO_PARAMS *); + NV_STATUS (*__uvmchanrtnrGetMapAddrSpace__)(struct UvmChannelRetainer *, struct CALL_CONTEXT *, NvU32, NV_ADDRESS_SPACE *); + NvU32 (*__uvmchanrtnrGetRefCount__)(struct UvmChannelRetainer *); + void (*__uvmchanrtnrAddAdditionalDependants__)(struct RsClient *, struct UvmChannelRetainer *, RsResourceRef *); NV_STATUS (*__uvmchanrtnrControl_Prologue__)(struct UvmChannelRetainer *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); NV_STATUS (*__uvmchanrtnrGetRegBaseOffsetAndSize__)(struct UvmChannelRetainer *, struct OBJGPU *, NvU32 *, NvU32 *); - NvBool (*__uvmchanrtnrCanCopy__)(struct UvmChannelRetainer *); NV_STATUS (*__uvmchanrtnrInternalControlForward__)(struct UvmChannelRetainer *, NvU32, void *, NvU32); - void (*__uvmchanrtnrPreDestruct__)(struct UvmChannelRetainer *); NV_STATUS (*__uvmchanrtnrUnmapFrom__)(struct UvmChannelRetainer *, RS_RES_UNMAP_FROM_PARAMS *); - NV_STATUS (*__uvmchanrtnrIsDuplicate__)(struct UvmChannelRetainer *, NvHandle, NvBool *); void (*__uvmchanrtnrControl_Epilogue__)(struct UvmChannelRetainer *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); NV_STATUS (*__uvmchanrtnrControlLookup__)(struct UvmChannelRetainer *, struct RS_RES_CONTROL_PARAMS_INTERNAL *, const struct NVOC_EXPORTED_METHOD_DEF **); + NvHandle (*__uvmchanrtnrGetInternalObjectHandle__)(struct UvmChannelRetainer *); + NV_STATUS (*__uvmchanrtnrControl__)(struct UvmChannelRetainer *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); + NV_STATUS (*__uvmchanrtnrUnmap__)(struct UvmChannelRetainer *, struct CALL_CONTEXT *, struct RsCpuMapping *); + NV_STATUS (*__uvmchanrtnrGetMemInterMapParams__)(struct UvmChannelRetainer *, RMRES_MEM_INTER_MAP_PARAMS *); + NV_STATUS (*__uvmchanrtnrGetMemoryMappingDescriptor__)(struct UvmChannelRetainer *, struct MEMORY_DESCRIPTOR **); + NV_STATUS (*__uvmchanrtnrControlFilter__)(struct UvmChannelRetainer *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); + NV_STATUS (*__uvmchanrtnrControlSerialization_Prologue__)(struct UvmChannelRetainer *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); + NvBool (*__uvmchanrtnrCanCopy__)(struct UvmChannelRetainer *); + void (*__uvmchanrtnrPreDestruct__)(struct UvmChannelRetainer *); + NV_STATUS (*__uvmchanrtnrIsDuplicate__)(struct UvmChannelRetainer *, NvHandle, NvBool *); + void (*__uvmchanrtnrControlSerialization_Epilogue__)(struct UvmChannelRetainer *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); NV_STATUS (*__uvmchanrtnrMap__)(struct UvmChannelRetainer *, struct CALL_CONTEXT *, struct RS_CPU_MAP_PARAMS *, struct RsCpuMapping *); NvBool (*__uvmchanrtnrAccessCallback__)(struct UvmChannelRetainer *, struct RsClient *, void *, RsAccessRight); MEMORY_DESCRIPTOR *pInstMemDesc; @@ -125,26 +127,28 @@ __nvoc_objCreate_UvmChannelRetainer((ppNewObj), staticCast((pParent), Dynamic), (createFlags), arg_pCallContext, arg_pParams) #define uvmchanrtnrShareCallback(pGpuResource, pInvokingClient, pParentRef, pSharePolicy) uvmchanrtnrShareCallback_DISPATCH(pGpuResource, pInvokingClient, pParentRef, pSharePolicy) -#define uvmchanrtnrControl(pGpuResource, pCallContext, pParams) uvmchanrtnrControl_DISPATCH(pGpuResource, pCallContext, pParams) -#define uvmchanrtnrUnmap(pGpuResource, pCallContext, pCpuMapping) uvmchanrtnrUnmap_DISPATCH(pGpuResource, pCallContext, pCpuMapping) -#define uvmchanrtnrGetMemInterMapParams(pRmResource, pParams) uvmchanrtnrGetMemInterMapParams_DISPATCH(pRmResource, pParams) -#define uvmchanrtnrGetMemoryMappingDescriptor(pRmResource, ppMemDesc) uvmchanrtnrGetMemoryMappingDescriptor_DISPATCH(pRmResource, ppMemDesc) -#define uvmchanrtnrGetMapAddrSpace(pGpuResource, pCallContext, mapFlags, pAddrSpace) uvmchanrtnrGetMapAddrSpace_DISPATCH(pGpuResource, pCallContext, mapFlags, pAddrSpace) -#define uvmchanrtnrGetInternalObjectHandle(pGpuResource) uvmchanrtnrGetInternalObjectHandle_DISPATCH(pGpuResource) -#define uvmchanrtnrControlFilter(pResource, pCallContext, pParams) uvmchanrtnrControlFilter_DISPATCH(pResource, pCallContext, pParams) -#define uvmchanrtnrAddAdditionalDependants(pClient, pResource, pReference) uvmchanrtnrAddAdditionalDependants_DISPATCH(pClient, pResource, pReference) -#define uvmchanrtnrGetRefCount(pResource) uvmchanrtnrGetRefCount_DISPATCH(pResource) #define uvmchanrtnrCheckMemInterUnmap(pRmResource, bSubdeviceHandleProvided) uvmchanrtnrCheckMemInterUnmap_DISPATCH(pRmResource, bSubdeviceHandleProvided) #define uvmchanrtnrMapTo(pResource, pParams) uvmchanrtnrMapTo_DISPATCH(pResource, pParams) +#define uvmchanrtnrGetMapAddrSpace(pGpuResource, pCallContext, mapFlags, pAddrSpace) uvmchanrtnrGetMapAddrSpace_DISPATCH(pGpuResource, pCallContext, mapFlags, pAddrSpace) +#define uvmchanrtnrGetRefCount(pResource) uvmchanrtnrGetRefCount_DISPATCH(pResource) +#define uvmchanrtnrAddAdditionalDependants(pClient, pResource, pReference) uvmchanrtnrAddAdditionalDependants_DISPATCH(pClient, pResource, pReference) #define uvmchanrtnrControl_Prologue(pResource, pCallContext, pParams) uvmchanrtnrControl_Prologue_DISPATCH(pResource, pCallContext, pParams) #define uvmchanrtnrGetRegBaseOffsetAndSize(pGpuResource, pGpu, pOffset, pSize) uvmchanrtnrGetRegBaseOffsetAndSize_DISPATCH(pGpuResource, pGpu, pOffset, pSize) -#define uvmchanrtnrCanCopy(pResource) uvmchanrtnrCanCopy_DISPATCH(pResource) #define uvmchanrtnrInternalControlForward(pGpuResource, command, pParams, size) uvmchanrtnrInternalControlForward_DISPATCH(pGpuResource, command, pParams, size) -#define uvmchanrtnrPreDestruct(pResource) uvmchanrtnrPreDestruct_DISPATCH(pResource) #define uvmchanrtnrUnmapFrom(pResource, pParams) uvmchanrtnrUnmapFrom_DISPATCH(pResource, pParams) -#define uvmchanrtnrIsDuplicate(pResource, hMemory, pDuplicate) uvmchanrtnrIsDuplicate_DISPATCH(pResource, hMemory, pDuplicate) #define uvmchanrtnrControl_Epilogue(pResource, pCallContext, pParams) uvmchanrtnrControl_Epilogue_DISPATCH(pResource, pCallContext, pParams) #define uvmchanrtnrControlLookup(pResource, pParams, ppEntry) uvmchanrtnrControlLookup_DISPATCH(pResource, pParams, ppEntry) +#define uvmchanrtnrGetInternalObjectHandle(pGpuResource) uvmchanrtnrGetInternalObjectHandle_DISPATCH(pGpuResource) +#define uvmchanrtnrControl(pGpuResource, pCallContext, pParams) uvmchanrtnrControl_DISPATCH(pGpuResource, pCallContext, pParams) +#define uvmchanrtnrUnmap(pGpuResource, pCallContext, pCpuMapping) uvmchanrtnrUnmap_DISPATCH(pGpuResource, pCallContext, pCpuMapping) +#define uvmchanrtnrGetMemInterMapParams(pRmResource, pParams) uvmchanrtnrGetMemInterMapParams_DISPATCH(pRmResource, pParams) +#define uvmchanrtnrGetMemoryMappingDescriptor(pRmResource, ppMemDesc) uvmchanrtnrGetMemoryMappingDescriptor_DISPATCH(pRmResource, ppMemDesc) +#define uvmchanrtnrControlFilter(pResource, pCallContext, pParams) uvmchanrtnrControlFilter_DISPATCH(pResource, pCallContext, pParams) +#define uvmchanrtnrControlSerialization_Prologue(pResource, pCallContext, pParams) uvmchanrtnrControlSerialization_Prologue_DISPATCH(pResource, pCallContext, pParams) +#define uvmchanrtnrCanCopy(pResource) uvmchanrtnrCanCopy_DISPATCH(pResource) +#define uvmchanrtnrPreDestruct(pResource) uvmchanrtnrPreDestruct_DISPATCH(pResource) +#define uvmchanrtnrIsDuplicate(pResource, hMemory, pDuplicate) uvmchanrtnrIsDuplicate_DISPATCH(pResource, hMemory, pDuplicate) +#define uvmchanrtnrControlSerialization_Epilogue(pResource, pCallContext, pParams) uvmchanrtnrControlSerialization_Epilogue_DISPATCH(pResource, pCallContext, pParams) #define uvmchanrtnrMap(pGpuResource, pCallContext, pParams, pCpuMapping) uvmchanrtnrMap_DISPATCH(pGpuResource, pCallContext, pParams, pCpuMapping) #define uvmchanrtnrAccessCallback(pResource, pInvokingClient, pAllocParams, accessRight) uvmchanrtnrAccessCallback_DISPATCH(pResource, pInvokingClient, pAllocParams, accessRight) NvBool uvmchanrtnrIsAllocationAllowed_IMPL(struct UvmChannelRetainer *pUvmChannelRetainer, CALL_CONTEXT *pCallContext, struct KernelChannel *pKernelChannel); @@ -165,84 +169,92 @@ return pGpuResource->__uvmchanrtnrShareCallback__(pGpuResource, pInvokingClient, pParentRef, pSharePolicy); } -static inline NV_STATUS uvmchanrtnrControl_DISPATCH(struct UvmChannelRetainer *pGpuResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { - return pGpuResource->__uvmchanrtnrControl__(pGpuResource, pCallContext, pParams); +static inline NV_STATUS uvmchanrtnrCheckMemInterUnmap_DISPATCH(struct UvmChannelRetainer *pRmResource, NvBool bSubdeviceHandleProvided) { + return pRmResource->__uvmchanrtnrCheckMemInterUnmap__(pRmResource, bSubdeviceHandleProvided); } -static inline NV_STATUS uvmchanrtnrUnmap_DISPATCH(struct UvmChannelRetainer *pGpuResource, struct CALL_CONTEXT *pCallContext, struct RsCpuMapping *pCpuMapping) { - return pGpuResource->__uvmchanrtnrUnmap__(pGpuResource, pCallContext, pCpuMapping); +static inline NV_STATUS uvmchanrtnrMapTo_DISPATCH(struct UvmChannelRetainer *pResource, RS_RES_MAP_TO_PARAMS *pParams) { + return pResource->__uvmchanrtnrMapTo__(pResource, pParams); } -static inline NV_STATUS uvmchanrtnrGetMemInterMapParams_DISPATCH(struct UvmChannelRetainer *pRmResource, RMRES_MEM_INTER_MAP_PARAMS *pParams) { - return pRmResource->__uvmchanrtnrGetMemInterMapParams__(pRmResource, pParams); +static inline NV_STATUS uvmchanrtnrGetMapAddrSpace_DISPATCH(struct UvmChannelRetainer *pGpuResource, struct CALL_CONTEXT *pCallContext, NvU32 mapFlags, NV_ADDRESS_SPACE *pAddrSpace) { + return pGpuResource->__uvmchanrtnrGetMapAddrSpace__(pGpuResource, pCallContext, mapFlags, pAddrSpace); } -static inline NV_STATUS uvmchanrtnrGetMemoryMappingDescriptor_DISPATCH(struct UvmChannelRetainer *pRmResource, struct MEMORY_DESCRIPTOR **ppMemDesc) { - return pRmResource->__uvmchanrtnrGetMemoryMappingDescriptor__(pRmResource, ppMemDesc); +static inline NvU32 uvmchanrtnrGetRefCount_DISPATCH(struct UvmChannelRetainer *pResource) { + return pResource->__uvmchanrtnrGetRefCount__(pResource); } -static inline NV_STATUS uvmchanrtnrGetMapAddrSpace_DISPATCH(struct UvmChannelRetainer *pGpuResource, struct CALL_CONTEXT *pCallContext, NvU32 mapFlags, NV_ADDRESS_SPACE *pAddrSpace) { - return pGpuResource->__uvmchanrtnrGetMapAddrSpace__(pGpuResource, pCallContext, mapFlags, pAddrSpace); +static inline void uvmchanrtnrAddAdditionalDependants_DISPATCH(struct RsClient *pClient, struct UvmChannelRetainer *pResource, RsResourceRef *pReference) { + pResource->__uvmchanrtnrAddAdditionalDependants__(pClient, pResource, pReference); } -static inline NvHandle uvmchanrtnrGetInternalObjectHandle_DISPATCH(struct UvmChannelRetainer *pGpuResource) { - return pGpuResource->__uvmchanrtnrGetInternalObjectHandle__(pGpuResource); +static inline NV_STATUS uvmchanrtnrControl_Prologue_DISPATCH(struct UvmChannelRetainer *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return pResource->__uvmchanrtnrControl_Prologue__(pResource, pCallContext, pParams); } -static inline NV_STATUS uvmchanrtnrControlFilter_DISPATCH(struct UvmChannelRetainer *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { - return pResource->__uvmchanrtnrControlFilter__(pResource, pCallContext, pParams); +static inline NV_STATUS uvmchanrtnrGetRegBaseOffsetAndSize_DISPATCH(struct UvmChannelRetainer *pGpuResource, struct OBJGPU *pGpu, NvU32 *pOffset, NvU32 *pSize) { + return pGpuResource->__uvmchanrtnrGetRegBaseOffsetAndSize__(pGpuResource, pGpu, pOffset, pSize); } -static inline void uvmchanrtnrAddAdditionalDependants_DISPATCH(struct RsClient *pClient, struct UvmChannelRetainer *pResource, RsResourceRef *pReference) { - pResource->__uvmchanrtnrAddAdditionalDependants__(pClient, pResource, pReference); +static inline NV_STATUS uvmchanrtnrInternalControlForward_DISPATCH(struct UvmChannelRetainer *pGpuResource, NvU32 command, void *pParams, NvU32 size) { + return pGpuResource->__uvmchanrtnrInternalControlForward__(pGpuResource, command, pParams, size); } -static inline NvU32 uvmchanrtnrGetRefCount_DISPATCH(struct UvmChannelRetainer *pResource) { - return pResource->__uvmchanrtnrGetRefCount__(pResource); +static inline NV_STATUS uvmchanrtnrUnmapFrom_DISPATCH(struct UvmChannelRetainer *pResource, RS_RES_UNMAP_FROM_PARAMS *pParams) { + return pResource->__uvmchanrtnrUnmapFrom__(pResource, pParams); } -static inline NV_STATUS uvmchanrtnrCheckMemInterUnmap_DISPATCH(struct UvmChannelRetainer *pRmResource, NvBool bSubdeviceHandleProvided) { - return pRmResource->__uvmchanrtnrCheckMemInterUnmap__(pRmResource, bSubdeviceHandleProvided); +static inline void uvmchanrtnrControl_Epilogue_DISPATCH(struct UvmChannelRetainer *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + pResource->__uvmchanrtnrControl_Epilogue__(pResource, pCallContext, pParams); } -static inline NV_STATUS uvmchanrtnrMapTo_DISPATCH(struct UvmChannelRetainer *pResource, RS_RES_MAP_TO_PARAMS *pParams) { - return pResource->__uvmchanrtnrMapTo__(pResource, pParams); +static inline NV_STATUS uvmchanrtnrControlLookup_DISPATCH(struct UvmChannelRetainer *pResource, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams, const struct NVOC_EXPORTED_METHOD_DEF **ppEntry) { + return pResource->__uvmchanrtnrControlLookup__(pResource, pParams, ppEntry); } -static inline NV_STATUS uvmchanrtnrControl_Prologue_DISPATCH(struct UvmChannelRetainer *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { - return pResource->__uvmchanrtnrControl_Prologue__(pResource, pCallContext, pParams); +static inline NvHandle uvmchanrtnrGetInternalObjectHandle_DISPATCH(struct UvmChannelRetainer *pGpuResource) { + return pGpuResource->__uvmchanrtnrGetInternalObjectHandle__(pGpuResource); } -static inline NV_STATUS uvmchanrtnrGetRegBaseOffsetAndSize_DISPATCH(struct UvmChannelRetainer *pGpuResource, struct OBJGPU *pGpu, NvU32 *pOffset, NvU32 *pSize) { - return pGpuResource->__uvmchanrtnrGetRegBaseOffsetAndSize__(pGpuResource, pGpu, pOffset, pSize); +static inline NV_STATUS uvmchanrtnrControl_DISPATCH(struct UvmChannelRetainer *pGpuResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return pGpuResource->__uvmchanrtnrControl__(pGpuResource, pCallContext, pParams); } -static inline NvBool uvmchanrtnrCanCopy_DISPATCH(struct UvmChannelRetainer *pResource) { - return pResource->__uvmchanrtnrCanCopy__(pResource); +static inline NV_STATUS uvmchanrtnrUnmap_DISPATCH(struct UvmChannelRetainer *pGpuResource, struct CALL_CONTEXT *pCallContext, struct RsCpuMapping *pCpuMapping) { + return pGpuResource->__uvmchanrtnrUnmap__(pGpuResource, pCallContext, pCpuMapping); } -static inline NV_STATUS uvmchanrtnrInternalControlForward_DISPATCH(struct UvmChannelRetainer *pGpuResource, NvU32 command, void *pParams, NvU32 size) { - return pGpuResource->__uvmchanrtnrInternalControlForward__(pGpuResource, command, pParams, size); +static inline NV_STATUS uvmchanrtnrGetMemInterMapParams_DISPATCH(struct UvmChannelRetainer *pRmResource, RMRES_MEM_INTER_MAP_PARAMS *pParams) { + return pRmResource->__uvmchanrtnrGetMemInterMapParams__(pRmResource, pParams); } -static inline void uvmchanrtnrPreDestruct_DISPATCH(struct UvmChannelRetainer *pResource) { - pResource->__uvmchanrtnrPreDestruct__(pResource); +static inline NV_STATUS uvmchanrtnrGetMemoryMappingDescriptor_DISPATCH(struct UvmChannelRetainer *pRmResource, struct MEMORY_DESCRIPTOR **ppMemDesc) { + return pRmResource->__uvmchanrtnrGetMemoryMappingDescriptor__(pRmResource, ppMemDesc); } -static inline NV_STATUS uvmchanrtnrUnmapFrom_DISPATCH(struct UvmChannelRetainer *pResource, RS_RES_UNMAP_FROM_PARAMS *pParams) { - return pResource->__uvmchanrtnrUnmapFrom__(pResource, pParams); +static inline NV_STATUS uvmchanrtnrControlFilter_DISPATCH(struct UvmChannelRetainer *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return pResource->__uvmchanrtnrControlFilter__(pResource, pCallContext, pParams); } -static inline NV_STATUS uvmchanrtnrIsDuplicate_DISPATCH(struct UvmChannelRetainer *pResource, NvHandle hMemory, NvBool *pDuplicate) { - return pResource->__uvmchanrtnrIsDuplicate__(pResource, hMemory, pDuplicate); +static inline NV_STATUS uvmchanrtnrControlSerialization_Prologue_DISPATCH(struct UvmChannelRetainer *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return pResource->__uvmchanrtnrControlSerialization_Prologue__(pResource, pCallContext, pParams); } -static inline void uvmchanrtnrControl_Epilogue_DISPATCH(struct UvmChannelRetainer *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { - pResource->__uvmchanrtnrControl_Epilogue__(pResource, pCallContext, pParams); +static inline NvBool uvmchanrtnrCanCopy_DISPATCH(struct UvmChannelRetainer *pResource) { + return pResource->__uvmchanrtnrCanCopy__(pResource); } -static inline NV_STATUS uvmchanrtnrControlLookup_DISPATCH(struct UvmChannelRetainer *pResource, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams, const struct NVOC_EXPORTED_METHOD_DEF **ppEntry) { - return pResource->__uvmchanrtnrControlLookup__(pResource, pParams, ppEntry); +static inline void uvmchanrtnrPreDestruct_DISPATCH(struct UvmChannelRetainer *pResource) { + pResource->__uvmchanrtnrPreDestruct__(pResource); +} + +static inline NV_STATUS uvmchanrtnrIsDuplicate_DISPATCH(struct UvmChannelRetainer *pResource, NvHandle hMemory, NvBool *pDuplicate) { + return pResource->__uvmchanrtnrIsDuplicate__(pResource, hMemory, pDuplicate); +} + +static inline void uvmchanrtnrControlSerialization_Epilogue_DISPATCH(struct UvmChannelRetainer *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + pResource->__uvmchanrtnrControlSerialization_Epilogue__(pResource, pCallContext, pParams); } static inline NV_STATUS uvmchanrtnrMap_DISPATCH(struct UvmChannelRetainer *pGpuResource, struct CALL_CONTEXT *pCallContext, struct RS_CPU_MAP_PARAMS *pParams, struct RsCpuMapping *pCpuMapping) { diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/generated/g_uvm_nvoc.c nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_uvm_nvoc.c --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/generated/g_uvm_nvoc.c 2023-10-25 20:27:22.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_uvm_nvoc.c 2024-03-05 22:18:49.000000000 +0000 @@ -83,7 +83,7 @@ return uvmStateInitUnlocked(pGpu, (struct OBJUVM *)(((unsigned char *)pUvm) - __nvoc_rtti_OBJUVM_OBJENGSTATE.offset)); } -static void __nvoc_thunk_OBJUVM_intrservRegisterIntrService(OBJGPU *arg0, struct IntrService *pUvm, IntrServiceRecord arg1[163]) { +static void __nvoc_thunk_OBJUVM_intrservRegisterIntrService(OBJGPU *arg0, struct IntrService *pUvm, IntrServiceRecord arg1[167]) { uvmRegisterIntrService(arg0, (struct OBJUVM *)(((unsigned char *)pUvm) - __nvoc_rtti_OBJUVM_IntrService.offset), arg1); } @@ -91,10 +91,6 @@ return uvmServiceInterrupt(arg0, (struct OBJUVM *)(((unsigned char *)pUvm) - __nvoc_rtti_OBJUVM_IntrService.offset), arg1); } -static NV_STATUS __nvoc_thunk_OBJENGSTATE_uvmReconcileTunableState(POBJGPU pGpu, struct OBJUVM *pEngstate, void *pTunableState) { - return engstateReconcileTunableState(pGpu, (struct OBJENGSTATE *)(((unsigned char *)pEngstate) + __nvoc_rtti_OBJUVM_OBJENGSTATE.offset), pTunableState); -} - static NV_STATUS __nvoc_thunk_OBJENGSTATE_uvmStateLoad(POBJGPU pGpu, struct OBJUVM *pEngstate, NvU32 arg0) { return engstateStateLoad(pGpu, (struct OBJENGSTATE *)(((unsigned char *)pEngstate) + __nvoc_rtti_OBJUVM_OBJENGSTATE.offset), arg0); } @@ -135,18 +131,6 @@ return engstateStatePreInitUnlocked(pGpu, (struct OBJENGSTATE *)(((unsigned char *)pEngstate) + __nvoc_rtti_OBJUVM_OBJENGSTATE.offset)); } -static NV_STATUS __nvoc_thunk_OBJENGSTATE_uvmGetTunableState(POBJGPU pGpu, struct OBJUVM *pEngstate, void *pTunableState) { - return engstateGetTunableState(pGpu, (struct OBJENGSTATE *)(((unsigned char *)pEngstate) + __nvoc_rtti_OBJUVM_OBJENGSTATE.offset), pTunableState); -} - -static NV_STATUS __nvoc_thunk_OBJENGSTATE_uvmCompareTunableState(POBJGPU pGpu, struct OBJUVM *pEngstate, void *pTunables1, void *pTunables2) { - return engstateCompareTunableState(pGpu, (struct OBJENGSTATE *)(((unsigned char *)pEngstate) + __nvoc_rtti_OBJUVM_OBJENGSTATE.offset), pTunables1, pTunables2); -} - -static void __nvoc_thunk_OBJENGSTATE_uvmFreeTunableState(POBJGPU pGpu, struct OBJUVM *pEngstate, void *pTunableState) { - engstateFreeTunableState(pGpu, (struct OBJENGSTATE *)(((unsigned char *)pEngstate) + __nvoc_rtti_OBJUVM_OBJENGSTATE.offset), pTunableState); -} - static NvBool __nvoc_thunk_IntrService_uvmClearInterrupt(OBJGPU *pGpu, struct OBJUVM *pIntrService, IntrServiceClearInterruptArguments *pParams) { return intrservClearInterrupt(pGpu, (struct IntrService *)(((unsigned char *)pIntrService) + __nvoc_rtti_OBJUVM_IntrService.offset), pParams); } @@ -155,14 +139,6 @@ return engstateStatePostLoad(pGpu, (struct OBJENGSTATE *)(((unsigned char *)pEngstate) + __nvoc_rtti_OBJUVM_OBJENGSTATE.offset), arg0); } -static NV_STATUS __nvoc_thunk_OBJENGSTATE_uvmAllocTunableState(POBJGPU pGpu, struct OBJUVM *pEngstate, void **ppTunableState) { - return engstateAllocTunableState(pGpu, (struct OBJENGSTATE *)(((unsigned char *)pEngstate) + __nvoc_rtti_OBJUVM_OBJENGSTATE.offset), ppTunableState); -} - -static NV_STATUS __nvoc_thunk_OBJENGSTATE_uvmSetTunableState(POBJGPU pGpu, struct OBJUVM *pEngstate, void *pTunableState) { - return engstateSetTunableState(pGpu, (struct OBJENGSTATE *)(((unsigned char *)pEngstate) + __nvoc_rtti_OBJUVM_OBJENGSTATE.offset), pTunableState); -} - static NV_STATUS __nvoc_thunk_OBJENGSTATE_uvmConstructEngine(POBJGPU pGpu, struct OBJUVM *pEngstate, ENGDESCRIPTOR arg0) { return engstateConstructEngine(pGpu, (struct OBJENGSTATE *)(((unsigned char *)pEngstate) + __nvoc_rtti_OBJUVM_OBJENGSTATE.offset), arg0); } @@ -245,8 +221,6 @@ pThis->__nvoc_base_IntrService.__intrservServiceInterrupt__ = &__nvoc_thunk_OBJUVM_intrservServiceInterrupt; - pThis->__uvmReconcileTunableState__ = &__nvoc_thunk_OBJENGSTATE_uvmReconcileTunableState; - pThis->__uvmStateLoad__ = &__nvoc_thunk_OBJENGSTATE_uvmStateLoad; pThis->__uvmStateUnload__ = &__nvoc_thunk_OBJENGSTATE_uvmStateUnload; @@ -267,20 +241,10 @@ pThis->__uvmStatePreInitUnlocked__ = &__nvoc_thunk_OBJENGSTATE_uvmStatePreInitUnlocked; - pThis->__uvmGetTunableState__ = &__nvoc_thunk_OBJENGSTATE_uvmGetTunableState; - - pThis->__uvmCompareTunableState__ = &__nvoc_thunk_OBJENGSTATE_uvmCompareTunableState; - - pThis->__uvmFreeTunableState__ = &__nvoc_thunk_OBJENGSTATE_uvmFreeTunableState; - pThis->__uvmClearInterrupt__ = &__nvoc_thunk_IntrService_uvmClearInterrupt; pThis->__uvmStatePostLoad__ = &__nvoc_thunk_OBJENGSTATE_uvmStatePostLoad; - pThis->__uvmAllocTunableState__ = &__nvoc_thunk_OBJENGSTATE_uvmAllocTunableState; - - pThis->__uvmSetTunableState__ = &__nvoc_thunk_OBJENGSTATE_uvmSetTunableState; - pThis->__uvmConstructEngine__ = &__nvoc_thunk_OBJENGSTATE_uvmConstructEngine; pThis->__uvmIsPresent__ = &__nvoc_thunk_OBJENGSTATE_uvmIsPresent; @@ -308,13 +272,16 @@ OBJUVM *pThis; RmHalspecOwner *pRmhalspecowner; - pThis = portMemAllocNonPaged(sizeof(OBJUVM)); - if (pThis == NULL) return NV_ERR_NO_MEMORY; + status = __nvoc_handleObjCreateMemAlloc(createFlags, sizeof(OBJUVM), (void**)&pThis, (void**)ppThis); + if (status != NV_OK) + return status; portMemSet(pThis, 0, sizeof(OBJUVM)); __nvoc_initRtti(staticCast(pThis, Dynamic), &__nvoc_class_def_OBJUVM); + pThis->__nvoc_base_OBJENGSTATE.__nvoc_base_Object.createFlags = createFlags; + if (pParent != NULL && !(createFlags & NVOC_OBJ_CREATE_FLAGS_PARENT_HALSPEC_ONLY)) { pParentObj = dynamicCast(pParent, Object); @@ -334,11 +301,17 @@ if (status != NV_OK) goto __nvoc_objCreate_OBJUVM_cleanup; *ppThis = pThis; + return NV_OK; __nvoc_objCreate_OBJUVM_cleanup: // do not call destructors here since the constructor already called them - portMemFree(pThis); + if (createFlags & NVOC_OBJ_CREATE_FLAGS_IN_PLACE_CONSTRUCT) + portMemSet(pThis, 0, sizeof(OBJUVM)); + else + portMemFree(pThis); + + // coverity[leaked_storage:FALSE] return status; } diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/generated/g_uvm_nvoc.h nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_uvm_nvoc.h --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/generated/g_uvm_nvoc.h 2023-10-25 20:27:22.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_uvm_nvoc.h 2024-03-05 22:18:49.000000000 +0000 @@ -61,23 +61,33 @@ * Contains the Unified Virtual Memory (UVM) feature related data. */ +struct AccessCounterBuffer; + +#ifndef __NVOC_CLASS_AccessCounterBuffer_TYPEDEF__ +#define __NVOC_CLASS_AccessCounterBuffer_TYPEDEF__ +typedef struct AccessCounterBuffer AccessCounterBuffer; +#endif /* __NVOC_CLASS_AccessCounterBuffer_TYPEDEF__ */ + +#ifndef __nvoc_class_id_AccessCounterBuffer +#define __nvoc_class_id_AccessCounterBuffer 0x1f0074 +#endif /* __nvoc_class_id_AccessCounterBuffer */ + + /* * This structure is used to store all the necessary information concerning the access counter buffer. * It is contained within the UVM object. */ -struct ACCESS_CNTR_BUFFER +typedef struct { + // kernel fields + struct AccessCounterBuffer *pAccessCounterBuffer; // AccessCounterBuffer object + + // physical fields NvU64 bar2UvmAccessCntrBufferAddr; //This is the bar2 VA that is used by the gpu in // order to access the buffer - NvP64 hAccessCntrBufferCpuMapping; //This is a handle to the CPU mapping - MEMORY_DESCRIPTOR *pUvmAccessCntrAllocMemDesc; // Memory descriptor of the access counter buffer allocation MEMORY_DESCRIPTOR *pUvmAccessCntrMemDesc; // Memory descriptor of the reconstructed access counter buffer - NvHandle hAccessCntrBufferObject; // This is a unique object handle - NvHandle hAccessCntrBufferClient; // This is a unique client handle - NvU32 accessCntrBufferSize; //This represents the size of the buffer (the maximum size that - // can be used before the buffer gets full) -}; +} ACCESS_CNTR_BUFFER; typedef enum { @@ -105,7 +115,6 @@ NV_STATUS (*__uvmStateInitUnlocked__)(OBJGPU *, struct OBJUVM *); void (*__uvmRegisterIntrService__)(OBJGPU *, struct OBJUVM *, IntrServiceRecord *); NvU32 (*__uvmServiceInterrupt__)(OBJGPU *, struct OBJUVM *, IntrServiceServiceInterruptArguments *); - NV_STATUS (*__uvmReconcileTunableState__)(POBJGPU, struct OBJUVM *, void *); NV_STATUS (*__uvmStateLoad__)(POBJGPU, struct OBJUVM *, NvU32); NV_STATUS (*__uvmStateUnload__)(POBJGPU, struct OBJUVM *, NvU32); NV_STATUS (*__uvmServiceNotificationInterrupt__)(OBJGPU *, struct OBJUVM *, IntrServiceServiceNotificationInterruptArguments *); @@ -116,16 +125,12 @@ void (*__uvmInitMissing__)(POBJGPU, struct OBJUVM *); NV_STATUS (*__uvmStatePreInitLocked__)(POBJGPU, struct OBJUVM *); NV_STATUS (*__uvmStatePreInitUnlocked__)(POBJGPU, struct OBJUVM *); - NV_STATUS (*__uvmGetTunableState__)(POBJGPU, struct OBJUVM *, void *); - NV_STATUS (*__uvmCompareTunableState__)(POBJGPU, struct OBJUVM *, void *, void *); - void (*__uvmFreeTunableState__)(POBJGPU, struct OBJUVM *, void *); NvBool (*__uvmClearInterrupt__)(OBJGPU *, struct OBJUVM *, IntrServiceClearInterruptArguments *); NV_STATUS (*__uvmStatePostLoad__)(POBJGPU, struct OBJUVM *, NvU32); - NV_STATUS (*__uvmAllocTunableState__)(POBJGPU, struct OBJUVM *, void **); - NV_STATUS (*__uvmSetTunableState__)(POBJGPU, struct OBJUVM *, void *); NV_STATUS (*__uvmConstructEngine__)(POBJGPU, struct OBJUVM *, ENGDESCRIPTOR); NvBool (*__uvmIsPresent__)(POBJGPU, struct OBJUVM *); - struct ACCESS_CNTR_BUFFER accessCntrBuffer; + ACCESS_CNTR_BUFFER *pAccessCounterBuffers; + NvU32 accessCounterBufferCount; NvHandle hClient; NvHandle hSubdevice; RM_API *pRmApi; @@ -165,7 +170,6 @@ #define uvmStateInitUnlocked(pGpu, pUvm) uvmStateInitUnlocked_DISPATCH(pGpu, pUvm) #define uvmRegisterIntrService(arg0, pUvm, arg1) uvmRegisterIntrService_DISPATCH(arg0, pUvm, arg1) #define uvmServiceInterrupt(arg0, pUvm, arg1) uvmServiceInterrupt_DISPATCH(arg0, pUvm, arg1) -#define uvmReconcileTunableState(pGpu, pEngstate, pTunableState) uvmReconcileTunableState_DISPATCH(pGpu, pEngstate, pTunableState) #define uvmStateLoad(pGpu, pEngstate, arg0) uvmStateLoad_DISPATCH(pGpu, pEngstate, arg0) #define uvmStateUnload(pGpu, pEngstate, arg0) uvmStateUnload_DISPATCH(pGpu, pEngstate, arg0) #define uvmServiceNotificationInterrupt(pGpu, pIntrService, pParams) uvmServiceNotificationInterrupt_DISPATCH(pGpu, pIntrService, pParams) @@ -176,270 +180,265 @@ #define uvmInitMissing(pGpu, pEngstate) uvmInitMissing_DISPATCH(pGpu, pEngstate) #define uvmStatePreInitLocked(pGpu, pEngstate) uvmStatePreInitLocked_DISPATCH(pGpu, pEngstate) #define uvmStatePreInitUnlocked(pGpu, pEngstate) uvmStatePreInitUnlocked_DISPATCH(pGpu, pEngstate) -#define uvmGetTunableState(pGpu, pEngstate, pTunableState) uvmGetTunableState_DISPATCH(pGpu, pEngstate, pTunableState) -#define uvmCompareTunableState(pGpu, pEngstate, pTunables1, pTunables2) uvmCompareTunableState_DISPATCH(pGpu, pEngstate, pTunables1, pTunables2) -#define uvmFreeTunableState(pGpu, pEngstate, pTunableState) uvmFreeTunableState_DISPATCH(pGpu, pEngstate, pTunableState) #define uvmClearInterrupt(pGpu, pIntrService, pParams) uvmClearInterrupt_DISPATCH(pGpu, pIntrService, pParams) #define uvmStatePostLoad(pGpu, pEngstate, arg0) uvmStatePostLoad_DISPATCH(pGpu, pEngstate, arg0) -#define uvmAllocTunableState(pGpu, pEngstate, ppTunableState) uvmAllocTunableState_DISPATCH(pGpu, pEngstate, ppTunableState) -#define uvmSetTunableState(pGpu, pEngstate, pTunableState) uvmSetTunableState_DISPATCH(pGpu, pEngstate, pTunableState) #define uvmConstructEngine(pGpu, pEngstate, arg0) uvmConstructEngine_DISPATCH(pGpu, pEngstate, arg0) #define uvmIsPresent(pGpu, pEngstate) uvmIsPresent_DISPATCH(pGpu, pEngstate) -NV_STATUS uvmInitializeAccessCntrBuffer_IMPL(OBJGPU *pGpu, struct OBJUVM *pUvm); +NV_STATUS uvmInitializeAccessCntrBuffer_IMPL(OBJGPU *pGpu, struct OBJUVM *pUvm, struct AccessCounterBuffer *pAccessCounterBuffer); #ifdef __nvoc_uvm_h_disabled -static inline NV_STATUS uvmInitializeAccessCntrBuffer(OBJGPU *pGpu, struct OBJUVM *pUvm) { +static inline NV_STATUS uvmInitializeAccessCntrBuffer(OBJGPU *pGpu, struct OBJUVM *pUvm, struct AccessCounterBuffer *pAccessCounterBuffer) { NV_ASSERT_FAILED_PRECOMP("OBJUVM was disabled!"); return NV_ERR_NOT_SUPPORTED; } #else //__nvoc_uvm_h_disabled -#define uvmInitializeAccessCntrBuffer(pGpu, pUvm) uvmInitializeAccessCntrBuffer_IMPL(pGpu, pUvm) +#define uvmInitializeAccessCntrBuffer(pGpu, pUvm, pAccessCounterBuffer) uvmInitializeAccessCntrBuffer_IMPL(pGpu, pUvm, pAccessCounterBuffer) #endif //__nvoc_uvm_h_disabled -#define uvmInitializeAccessCntrBuffer_HAL(pGpu, pUvm) uvmInitializeAccessCntrBuffer(pGpu, pUvm) +#define uvmInitializeAccessCntrBuffer_HAL(pGpu, pUvm, pAccessCounterBuffer) uvmInitializeAccessCntrBuffer(pGpu, pUvm, pAccessCounterBuffer) -NV_STATUS uvmTerminateAccessCntrBuffer_IMPL(OBJGPU *pGpu, struct OBJUVM *pUvm); +NV_STATUS uvmTerminateAccessCntrBuffer_IMPL(OBJGPU *pGpu, struct OBJUVM *pUvm, struct AccessCounterBuffer *pAccessCounterBuffer); #ifdef __nvoc_uvm_h_disabled -static inline NV_STATUS uvmTerminateAccessCntrBuffer(OBJGPU *pGpu, struct OBJUVM *pUvm) { +static inline NV_STATUS uvmTerminateAccessCntrBuffer(OBJGPU *pGpu, struct OBJUVM *pUvm, struct AccessCounterBuffer *pAccessCounterBuffer) { NV_ASSERT_FAILED_PRECOMP("OBJUVM was disabled!"); return NV_ERR_NOT_SUPPORTED; } #else //__nvoc_uvm_h_disabled -#define uvmTerminateAccessCntrBuffer(pGpu, pUvm) uvmTerminateAccessCntrBuffer_IMPL(pGpu, pUvm) +#define uvmTerminateAccessCntrBuffer(pGpu, pUvm, pAccessCounterBuffer) uvmTerminateAccessCntrBuffer_IMPL(pGpu, pUvm, pAccessCounterBuffer) #endif //__nvoc_uvm_h_disabled -#define uvmTerminateAccessCntrBuffer_HAL(pGpu, pUvm) uvmTerminateAccessCntrBuffer(pGpu, pUvm) +#define uvmTerminateAccessCntrBuffer_HAL(pGpu, pUvm, pAccessCounterBuffer) uvmTerminateAccessCntrBuffer(pGpu, pUvm, pAccessCounterBuffer) -NV_STATUS uvmInitAccessCntrBuffer_GV100(OBJGPU *pGpu, struct OBJUVM *pUvm); +NV_STATUS uvmInitAccessCntrBuffer_GV100(OBJGPU *pGpu, struct OBJUVM *pUvm, struct AccessCounterBuffer *pAccessCounterBuffer); #ifdef __nvoc_uvm_h_disabled -static inline NV_STATUS uvmInitAccessCntrBuffer(OBJGPU *pGpu, struct OBJUVM *pUvm) { +static inline NV_STATUS uvmInitAccessCntrBuffer(OBJGPU *pGpu, struct OBJUVM *pUvm, struct AccessCounterBuffer *pAccessCounterBuffer) { NV_ASSERT_FAILED_PRECOMP("OBJUVM was disabled!"); return NV_ERR_NOT_SUPPORTED; } #else //__nvoc_uvm_h_disabled -#define uvmInitAccessCntrBuffer(pGpu, pUvm) uvmInitAccessCntrBuffer_GV100(pGpu, pUvm) +#define uvmInitAccessCntrBuffer(pGpu, pUvm, pAccessCounterBuffer) uvmInitAccessCntrBuffer_GV100(pGpu, pUvm, pAccessCounterBuffer) #endif //__nvoc_uvm_h_disabled -#define uvmInitAccessCntrBuffer_HAL(pGpu, pUvm) uvmInitAccessCntrBuffer(pGpu, pUvm) +#define uvmInitAccessCntrBuffer_HAL(pGpu, pUvm, pAccessCounterBuffer) uvmInitAccessCntrBuffer(pGpu, pUvm, pAccessCounterBuffer) -NV_STATUS uvmDestroyAccessCntrBuffer_GV100(OBJGPU *pGpu, struct OBJUVM *pUvm); +NV_STATUS uvmDestroyAccessCntrBuffer_GV100(OBJGPU *pGpu, struct OBJUVM *pUvm, struct AccessCounterBuffer *pAccessCounterBuffer); #ifdef __nvoc_uvm_h_disabled -static inline NV_STATUS uvmDestroyAccessCntrBuffer(OBJGPU *pGpu, struct OBJUVM *pUvm) { +static inline NV_STATUS uvmDestroyAccessCntrBuffer(OBJGPU *pGpu, struct OBJUVM *pUvm, struct AccessCounterBuffer *pAccessCounterBuffer) { NV_ASSERT_FAILED_PRECOMP("OBJUVM was disabled!"); return NV_ERR_NOT_SUPPORTED; } #else //__nvoc_uvm_h_disabled -#define uvmDestroyAccessCntrBuffer(pGpu, pUvm) uvmDestroyAccessCntrBuffer_GV100(pGpu, pUvm) +#define uvmDestroyAccessCntrBuffer(pGpu, pUvm, pAccessCounterBuffer) uvmDestroyAccessCntrBuffer_GV100(pGpu, pUvm, pAccessCounterBuffer) #endif //__nvoc_uvm_h_disabled -#define uvmDestroyAccessCntrBuffer_HAL(pGpu, pUvm) uvmDestroyAccessCntrBuffer(pGpu, pUvm) +#define uvmDestroyAccessCntrBuffer_HAL(pGpu, pUvm, pAccessCounterBuffer) uvmDestroyAccessCntrBuffer(pGpu, pUvm, pAccessCounterBuffer) -static inline NV_STATUS uvmAccessCntrBufferUnregister_ac1694(OBJGPU *arg0, struct OBJUVM *arg1) { +static inline NV_STATUS uvmAccessCntrBufferUnregister_ac1694(OBJGPU *arg0, struct OBJUVM *arg1, NvU32 accessCounterIndex) { return NV_OK; } #ifdef __nvoc_uvm_h_disabled -static inline NV_STATUS uvmAccessCntrBufferUnregister(OBJGPU *arg0, struct OBJUVM *arg1) { +static inline NV_STATUS uvmAccessCntrBufferUnregister(OBJGPU *arg0, struct OBJUVM *arg1, NvU32 accessCounterIndex) { NV_ASSERT_FAILED_PRECOMP("OBJUVM was disabled!"); return NV_ERR_NOT_SUPPORTED; } #else //__nvoc_uvm_h_disabled -#define uvmAccessCntrBufferUnregister(arg0, arg1) uvmAccessCntrBufferUnregister_ac1694(arg0, arg1) +#define uvmAccessCntrBufferUnregister(arg0, arg1, accessCounterIndex) uvmAccessCntrBufferUnregister_ac1694(arg0, arg1, accessCounterIndex) #endif //__nvoc_uvm_h_disabled -#define uvmAccessCntrBufferUnregister_HAL(arg0, arg1) uvmAccessCntrBufferUnregister(arg0, arg1) +#define uvmAccessCntrBufferUnregister_HAL(arg0, arg1, accessCounterIndex) uvmAccessCntrBufferUnregister(arg0, arg1, accessCounterIndex) -static inline NV_STATUS uvmAccessCntrBufferRegister_ac1694(OBJGPU *arg0, struct OBJUVM *arg1, NvU32 arg2, RmPhysAddr *arg3) { +static inline NV_STATUS uvmAccessCntrBufferRegister_ac1694(OBJGPU *arg0, struct OBJUVM *arg1, NvU32 accessCounterIndex, NvU32 arg2, RmPhysAddr *arg3) { return NV_OK; } #ifdef __nvoc_uvm_h_disabled -static inline NV_STATUS uvmAccessCntrBufferRegister(OBJGPU *arg0, struct OBJUVM *arg1, NvU32 arg2, RmPhysAddr *arg3) { +static inline NV_STATUS uvmAccessCntrBufferRegister(OBJGPU *arg0, struct OBJUVM *arg1, NvU32 accessCounterIndex, NvU32 arg2, RmPhysAddr *arg3) { NV_ASSERT_FAILED_PRECOMP("OBJUVM was disabled!"); return NV_ERR_NOT_SUPPORTED; } #else //__nvoc_uvm_h_disabled -#define uvmAccessCntrBufferRegister(arg0, arg1, arg2, arg3) uvmAccessCntrBufferRegister_ac1694(arg0, arg1, arg2, arg3) +#define uvmAccessCntrBufferRegister(arg0, arg1, accessCounterIndex, arg2, arg3) uvmAccessCntrBufferRegister_ac1694(arg0, arg1, accessCounterIndex, arg2, arg3) #endif //__nvoc_uvm_h_disabled -#define uvmAccessCntrBufferRegister_HAL(arg0, arg1, arg2, arg3) uvmAccessCntrBufferRegister(arg0, arg1, arg2, arg3) +#define uvmAccessCntrBufferRegister_HAL(arg0, arg1, accessCounterIndex, arg2, arg3) uvmAccessCntrBufferRegister(arg0, arg1, accessCounterIndex, arg2, arg3) -NV_STATUS uvmUnloadAccessCntrBuffer_GV100(OBJGPU *pGpu, struct OBJUVM *pUvm); +NV_STATUS uvmUnloadAccessCntrBuffer_GV100(OBJGPU *pGpu, struct OBJUVM *pUvm, NvU32 accessCounterIndex); #ifdef __nvoc_uvm_h_disabled -static inline NV_STATUS uvmUnloadAccessCntrBuffer(OBJGPU *pGpu, struct OBJUVM *pUvm) { +static inline NV_STATUS uvmUnloadAccessCntrBuffer(OBJGPU *pGpu, struct OBJUVM *pUvm, NvU32 accessCounterIndex) { NV_ASSERT_FAILED_PRECOMP("OBJUVM was disabled!"); return NV_ERR_NOT_SUPPORTED; } #else //__nvoc_uvm_h_disabled -#define uvmUnloadAccessCntrBuffer(pGpu, pUvm) uvmUnloadAccessCntrBuffer_GV100(pGpu, pUvm) +#define uvmUnloadAccessCntrBuffer(pGpu, pUvm, accessCounterIndex) uvmUnloadAccessCntrBuffer_GV100(pGpu, pUvm, accessCounterIndex) #endif //__nvoc_uvm_h_disabled -#define uvmUnloadAccessCntrBuffer_HAL(pGpu, pUvm) uvmUnloadAccessCntrBuffer(pGpu, pUvm) +#define uvmUnloadAccessCntrBuffer_HAL(pGpu, pUvm, accessCounterIndex) uvmUnloadAccessCntrBuffer(pGpu, pUvm, accessCounterIndex) -NV_STATUS uvmSetupAccessCntrBuffer_GV100(OBJGPU *pGpu, struct OBJUVM *pUvm); +NV_STATUS uvmSetupAccessCntrBuffer_GV100(OBJGPU *pGpu, struct OBJUVM *pUvm, NvU32 accessCounterIndex); #ifdef __nvoc_uvm_h_disabled -static inline NV_STATUS uvmSetupAccessCntrBuffer(OBJGPU *pGpu, struct OBJUVM *pUvm) { +static inline NV_STATUS uvmSetupAccessCntrBuffer(OBJGPU *pGpu, struct OBJUVM *pUvm, NvU32 accessCounterIndex) { NV_ASSERT_FAILED_PRECOMP("OBJUVM was disabled!"); return NV_ERR_NOT_SUPPORTED; } #else //__nvoc_uvm_h_disabled -#define uvmSetupAccessCntrBuffer(pGpu, pUvm) uvmSetupAccessCntrBuffer_GV100(pGpu, pUvm) +#define uvmSetupAccessCntrBuffer(pGpu, pUvm, accessCounterIndex) uvmSetupAccessCntrBuffer_GV100(pGpu, pUvm, accessCounterIndex) #endif //__nvoc_uvm_h_disabled -#define uvmSetupAccessCntrBuffer_HAL(pGpu, pUvm) uvmSetupAccessCntrBuffer(pGpu, pUvm) +#define uvmSetupAccessCntrBuffer_HAL(pGpu, pUvm, accessCounterIndex) uvmSetupAccessCntrBuffer(pGpu, pUvm, accessCounterIndex) -NV_STATUS uvmReadAccessCntrBufferPutPtr_TU102(OBJGPU *pGpu, struct OBJUVM *pUvm, NvU32 *arg0); +NV_STATUS uvmReadAccessCntrBufferPutPtr_TU102(OBJGPU *pGpu, struct OBJUVM *pUvm, NvU32 accessCounterIndex, NvU32 *arg0); #ifdef __nvoc_uvm_h_disabled -static inline NV_STATUS uvmReadAccessCntrBufferPutPtr(OBJGPU *pGpu, struct OBJUVM *pUvm, NvU32 *arg0) { +static inline NV_STATUS uvmReadAccessCntrBufferPutPtr(OBJGPU *pGpu, struct OBJUVM *pUvm, NvU32 accessCounterIndex, NvU32 *arg0) { NV_ASSERT_FAILED_PRECOMP("OBJUVM was disabled!"); return NV_ERR_NOT_SUPPORTED; } #else //__nvoc_uvm_h_disabled -#define uvmReadAccessCntrBufferPutPtr(pGpu, pUvm, arg0) uvmReadAccessCntrBufferPutPtr_TU102(pGpu, pUvm, arg0) +#define uvmReadAccessCntrBufferPutPtr(pGpu, pUvm, accessCounterIndex, arg0) uvmReadAccessCntrBufferPutPtr_TU102(pGpu, pUvm, accessCounterIndex, arg0) #endif //__nvoc_uvm_h_disabled -#define uvmReadAccessCntrBufferPutPtr_HAL(pGpu, pUvm, arg0) uvmReadAccessCntrBufferPutPtr(pGpu, pUvm, arg0) +#define uvmReadAccessCntrBufferPutPtr_HAL(pGpu, pUvm, accessCounterIndex, arg0) uvmReadAccessCntrBufferPutPtr(pGpu, pUvm, accessCounterIndex, arg0) -NV_STATUS uvmReadAccessCntrBufferGetPtr_TU102(OBJGPU *pGpu, struct OBJUVM *pUvm, NvU32 *arg0); +NV_STATUS uvmReadAccessCntrBufferGetPtr_TU102(OBJGPU *pGpu, struct OBJUVM *pUvm, NvU32 accessCounterIndex, NvU32 *arg0); #ifdef __nvoc_uvm_h_disabled -static inline NV_STATUS uvmReadAccessCntrBufferGetPtr(OBJGPU *pGpu, struct OBJUVM *pUvm, NvU32 *arg0) { +static inline NV_STATUS uvmReadAccessCntrBufferGetPtr(OBJGPU *pGpu, struct OBJUVM *pUvm, NvU32 accessCounterIndex, NvU32 *arg0) { NV_ASSERT_FAILED_PRECOMP("OBJUVM was disabled!"); return NV_ERR_NOT_SUPPORTED; } #else //__nvoc_uvm_h_disabled -#define uvmReadAccessCntrBufferGetPtr(pGpu, pUvm, arg0) uvmReadAccessCntrBufferGetPtr_TU102(pGpu, pUvm, arg0) +#define uvmReadAccessCntrBufferGetPtr(pGpu, pUvm, accessCounterIndex, arg0) uvmReadAccessCntrBufferGetPtr_TU102(pGpu, pUvm, accessCounterIndex, arg0) #endif //__nvoc_uvm_h_disabled -#define uvmReadAccessCntrBufferGetPtr_HAL(pGpu, pUvm, arg0) uvmReadAccessCntrBufferGetPtr(pGpu, pUvm, arg0) +#define uvmReadAccessCntrBufferGetPtr_HAL(pGpu, pUvm, accessCounterIndex, arg0) uvmReadAccessCntrBufferGetPtr(pGpu, pUvm, accessCounterIndex, arg0) -NV_STATUS uvmReadAccessCntrBufferFullPtr_TU102(OBJGPU *pGpu, struct OBJUVM *pUvm, NvBool *arg0); +NV_STATUS uvmReadAccessCntrBufferFullPtr_TU102(OBJGPU *pGpu, struct OBJUVM *pUvm, NvU32 accessCounterIndex, NvBool *arg0); #ifdef __nvoc_uvm_h_disabled -static inline NV_STATUS uvmReadAccessCntrBufferFullPtr(OBJGPU *pGpu, struct OBJUVM *pUvm, NvBool *arg0) { +static inline NV_STATUS uvmReadAccessCntrBufferFullPtr(OBJGPU *pGpu, struct OBJUVM *pUvm, NvU32 accessCounterIndex, NvBool *arg0) { NV_ASSERT_FAILED_PRECOMP("OBJUVM was disabled!"); return NV_ERR_NOT_SUPPORTED; } #else //__nvoc_uvm_h_disabled -#define uvmReadAccessCntrBufferFullPtr(pGpu, pUvm, arg0) uvmReadAccessCntrBufferFullPtr_TU102(pGpu, pUvm, arg0) +#define uvmReadAccessCntrBufferFullPtr(pGpu, pUvm, accessCounterIndex, arg0) uvmReadAccessCntrBufferFullPtr_TU102(pGpu, pUvm, accessCounterIndex, arg0) #endif //__nvoc_uvm_h_disabled -#define uvmReadAccessCntrBufferFullPtr_HAL(pGpu, pUvm, arg0) uvmReadAccessCntrBufferFullPtr(pGpu, pUvm, arg0) +#define uvmReadAccessCntrBufferFullPtr_HAL(pGpu, pUvm, accessCounterIndex, arg0) uvmReadAccessCntrBufferFullPtr(pGpu, pUvm, accessCounterIndex, arg0) -NV_STATUS uvmResetAccessCntrBuffer_GV100(OBJGPU *pGpu, struct OBJUVM *pUvm, NvU32 arg0); +NV_STATUS uvmResetAccessCntrBuffer_GV100(OBJGPU *pGpu, struct OBJUVM *pUvm, NvU32 accessCounterIndex, NvU32 arg0); #ifdef __nvoc_uvm_h_disabled -static inline NV_STATUS uvmResetAccessCntrBuffer(OBJGPU *pGpu, struct OBJUVM *pUvm, NvU32 arg0) { +static inline NV_STATUS uvmResetAccessCntrBuffer(OBJGPU *pGpu, struct OBJUVM *pUvm, NvU32 accessCounterIndex, NvU32 arg0) { NV_ASSERT_FAILED_PRECOMP("OBJUVM was disabled!"); return NV_ERR_NOT_SUPPORTED; } #else //__nvoc_uvm_h_disabled -#define uvmResetAccessCntrBuffer(pGpu, pUvm, arg0) uvmResetAccessCntrBuffer_GV100(pGpu, pUvm, arg0) +#define uvmResetAccessCntrBuffer(pGpu, pUvm, accessCounterIndex, arg0) uvmResetAccessCntrBuffer_GV100(pGpu, pUvm, accessCounterIndex, arg0) #endif //__nvoc_uvm_h_disabled -#define uvmResetAccessCntrBuffer_HAL(pGpu, pUvm, arg0) uvmResetAccessCntrBuffer(pGpu, pUvm, arg0) +#define uvmResetAccessCntrBuffer_HAL(pGpu, pUvm, accessCounterIndex, arg0) uvmResetAccessCntrBuffer(pGpu, pUvm, accessCounterIndex, arg0) -NV_STATUS uvmAccessCntrSetGranularity_TU102(OBJGPU *pGpu, struct OBJUVM *pUvm, ACCESS_CNTR_TYPE arg0, NvU32 arg1); +NV_STATUS uvmAccessCntrSetGranularity_TU102(OBJGPU *pGpu, struct OBJUVM *pUvm, NvU32 accessCounterIndex, ACCESS_CNTR_TYPE arg0, NvU32 arg1); #ifdef __nvoc_uvm_h_disabled -static inline NV_STATUS uvmAccessCntrSetGranularity(OBJGPU *pGpu, struct OBJUVM *pUvm, ACCESS_CNTR_TYPE arg0, NvU32 arg1) { +static inline NV_STATUS uvmAccessCntrSetGranularity(OBJGPU *pGpu, struct OBJUVM *pUvm, NvU32 accessCounterIndex, ACCESS_CNTR_TYPE arg0, NvU32 arg1) { NV_ASSERT_FAILED_PRECOMP("OBJUVM was disabled!"); return NV_ERR_NOT_SUPPORTED; } #else //__nvoc_uvm_h_disabled -#define uvmAccessCntrSetGranularity(pGpu, pUvm, arg0, arg1) uvmAccessCntrSetGranularity_TU102(pGpu, pUvm, arg0, arg1) +#define uvmAccessCntrSetGranularity(pGpu, pUvm, accessCounterIndex, arg0, arg1) uvmAccessCntrSetGranularity_TU102(pGpu, pUvm, accessCounterIndex, arg0, arg1) #endif //__nvoc_uvm_h_disabled -#define uvmAccessCntrSetGranularity_HAL(pGpu, pUvm, arg0, arg1) uvmAccessCntrSetGranularity(pGpu, pUvm, arg0, arg1) +#define uvmAccessCntrSetGranularity_HAL(pGpu, pUvm, accessCounterIndex, arg0, arg1) uvmAccessCntrSetGranularity(pGpu, pUvm, accessCounterIndex, arg0, arg1) -NV_STATUS uvmAccessCntrSetThreshold_TU102(OBJGPU *pGpu, struct OBJUVM *pUvm, NvU32 arg0); +NV_STATUS uvmAccessCntrSetThreshold_TU102(OBJGPU *pGpu, struct OBJUVM *pUvm, NvU32 accessCounterIndex, NvU32 arg0); #ifdef __nvoc_uvm_h_disabled -static inline NV_STATUS uvmAccessCntrSetThreshold(OBJGPU *pGpu, struct OBJUVM *pUvm, NvU32 arg0) { +static inline NV_STATUS uvmAccessCntrSetThreshold(OBJGPU *pGpu, struct OBJUVM *pUvm, NvU32 accessCounterIndex, NvU32 arg0) { NV_ASSERT_FAILED_PRECOMP("OBJUVM was disabled!"); return NV_ERR_NOT_SUPPORTED; } #else //__nvoc_uvm_h_disabled -#define uvmAccessCntrSetThreshold(pGpu, pUvm, arg0) uvmAccessCntrSetThreshold_TU102(pGpu, pUvm, arg0) +#define uvmAccessCntrSetThreshold(pGpu, pUvm, accessCounterIndex, arg0) uvmAccessCntrSetThreshold_TU102(pGpu, pUvm, accessCounterIndex, arg0) #endif //__nvoc_uvm_h_disabled -#define uvmAccessCntrSetThreshold_HAL(pGpu, pUvm, arg0) uvmAccessCntrSetThreshold(pGpu, pUvm, arg0) +#define uvmAccessCntrSetThreshold_HAL(pGpu, pUvm, accessCounterIndex, arg0) uvmAccessCntrSetThreshold(pGpu, pUvm, accessCounterIndex, arg0) -NV_STATUS uvmAccessCntrSetCounterLimit_GV100(OBJGPU *pGpu, struct OBJUVM *pUvm, NvU32 arg0, NvU32 arg1); +NV_STATUS uvmAccessCntrSetCounterLimit_GV100(OBJGPU *pGpu, struct OBJUVM *pUvm, NvU32 accessCounterIndex, NvU32 arg0, NvU32 arg1); #ifdef __nvoc_uvm_h_disabled -static inline NV_STATUS uvmAccessCntrSetCounterLimit(OBJGPU *pGpu, struct OBJUVM *pUvm, NvU32 arg0, NvU32 arg1) { +static inline NV_STATUS uvmAccessCntrSetCounterLimit(OBJGPU *pGpu, struct OBJUVM *pUvm, NvU32 accessCounterIndex, NvU32 arg0, NvU32 arg1) { NV_ASSERT_FAILED_PRECOMP("OBJUVM was disabled!"); return NV_ERR_NOT_SUPPORTED; } #else //__nvoc_uvm_h_disabled -#define uvmAccessCntrSetCounterLimit(pGpu, pUvm, arg0, arg1) uvmAccessCntrSetCounterLimit_GV100(pGpu, pUvm, arg0, arg1) +#define uvmAccessCntrSetCounterLimit(pGpu, pUvm, accessCounterIndex, arg0, arg1) uvmAccessCntrSetCounterLimit_GV100(pGpu, pUvm, accessCounterIndex, arg0, arg1) #endif //__nvoc_uvm_h_disabled -#define uvmAccessCntrSetCounterLimit_HAL(pGpu, pUvm, arg0, arg1) uvmAccessCntrSetCounterLimit(pGpu, pUvm, arg0, arg1) +#define uvmAccessCntrSetCounterLimit_HAL(pGpu, pUvm, accessCounterIndex, arg0, arg1) uvmAccessCntrSetCounterLimit(pGpu, pUvm, accessCounterIndex, arg0, arg1) -NV_STATUS uvmWriteAccessCntrBufferGetPtr_TU102(OBJGPU *pGpu, struct OBJUVM *pUvm, NvU32 arg0); +NV_STATUS uvmWriteAccessCntrBufferGetPtr_TU102(OBJGPU *pGpu, struct OBJUVM *pUvm, NvU32 accessCounterIndex, NvU32 arg0); #ifdef __nvoc_uvm_h_disabled -static inline NV_STATUS uvmWriteAccessCntrBufferGetPtr(OBJGPU *pGpu, struct OBJUVM *pUvm, NvU32 arg0) { +static inline NV_STATUS uvmWriteAccessCntrBufferGetPtr(OBJGPU *pGpu, struct OBJUVM *pUvm, NvU32 accessCounterIndex, NvU32 arg0) { NV_ASSERT_FAILED_PRECOMP("OBJUVM was disabled!"); return NV_ERR_NOT_SUPPORTED; } #else //__nvoc_uvm_h_disabled -#define uvmWriteAccessCntrBufferGetPtr(pGpu, pUvm, arg0) uvmWriteAccessCntrBufferGetPtr_TU102(pGpu, pUvm, arg0) +#define uvmWriteAccessCntrBufferGetPtr(pGpu, pUvm, accessCounterIndex, arg0) uvmWriteAccessCntrBufferGetPtr_TU102(pGpu, pUvm, accessCounterIndex, arg0) #endif //__nvoc_uvm_h_disabled -#define uvmWriteAccessCntrBufferGetPtr_HAL(pGpu, pUvm, arg0) uvmWriteAccessCntrBufferGetPtr(pGpu, pUvm, arg0) +#define uvmWriteAccessCntrBufferGetPtr_HAL(pGpu, pUvm, accessCounterIndex, arg0) uvmWriteAccessCntrBufferGetPtr(pGpu, pUvm, accessCounterIndex, arg0) -NV_STATUS uvmEnableAccessCntr_TU102(OBJGPU *pGpu, struct OBJUVM *pUvm, NvBool arg0); +NV_STATUS uvmEnableAccessCntr_TU102(OBJGPU *pGpu, struct OBJUVM *pUvm, NvU32 accessCounterIndex, NvBool arg0); #ifdef __nvoc_uvm_h_disabled -static inline NV_STATUS uvmEnableAccessCntr(OBJGPU *pGpu, struct OBJUVM *pUvm, NvBool arg0) { +static inline NV_STATUS uvmEnableAccessCntr(OBJGPU *pGpu, struct OBJUVM *pUvm, NvU32 accessCounterIndex, NvBool arg0) { NV_ASSERT_FAILED_PRECOMP("OBJUVM was disabled!"); return NV_ERR_NOT_SUPPORTED; } #else //__nvoc_uvm_h_disabled -#define uvmEnableAccessCntr(pGpu, pUvm, arg0) uvmEnableAccessCntr_TU102(pGpu, pUvm, arg0) +#define uvmEnableAccessCntr(pGpu, pUvm, accessCounterIndex, arg0) uvmEnableAccessCntr_TU102(pGpu, pUvm, accessCounterIndex, arg0) #endif //__nvoc_uvm_h_disabled -#define uvmEnableAccessCntr_HAL(pGpu, pUvm, arg0) uvmEnableAccessCntr(pGpu, pUvm, arg0) +#define uvmEnableAccessCntr_HAL(pGpu, pUvm, accessCounterIndex, arg0) uvmEnableAccessCntr(pGpu, pUvm, accessCounterIndex, arg0) -NV_STATUS uvmDisableAccessCntr_GV100(OBJGPU *pGpu, struct OBJUVM *pUvm, NvBool arg0); +NV_STATUS uvmDisableAccessCntr_GV100(OBJGPU *pGpu, struct OBJUVM *pUvm, NvU32 accessCounterIndex, NvBool arg0); #ifdef __nvoc_uvm_h_disabled -static inline NV_STATUS uvmDisableAccessCntr(OBJGPU *pGpu, struct OBJUVM *pUvm, NvBool arg0) { +static inline NV_STATUS uvmDisableAccessCntr(OBJGPU *pGpu, struct OBJUVM *pUvm, NvU32 accessCounterIndex, NvBool arg0) { NV_ASSERT_FAILED_PRECOMP("OBJUVM was disabled!"); return NV_ERR_NOT_SUPPORTED; } #else //__nvoc_uvm_h_disabled -#define uvmDisableAccessCntr(pGpu, pUvm, arg0) uvmDisableAccessCntr_GV100(pGpu, pUvm, arg0) +#define uvmDisableAccessCntr(pGpu, pUvm, accessCounterIndex, arg0) uvmDisableAccessCntr_GV100(pGpu, pUvm, accessCounterIndex, arg0) #endif //__nvoc_uvm_h_disabled -#define uvmDisableAccessCntr_HAL(pGpu, pUvm, arg0) uvmDisableAccessCntr(pGpu, pUvm, arg0) +#define uvmDisableAccessCntr_HAL(pGpu, pUvm, accessCounterIndex, arg0) uvmDisableAccessCntr(pGpu, pUvm, accessCounterIndex, arg0) NV_STATUS uvmEnableAccessCntrIntr_TU102(OBJGPU *pGpu, struct OBJUVM *pUvm, NvU32 arg0); @@ -469,19 +468,19 @@ #define uvmDisableAccessCntrIntr_HAL(pGpu, pUvm) uvmDisableAccessCntrIntr(pGpu, pUvm) -NV_STATUS uvmGetAccessCntrRegisterMappings_TU102(OBJGPU *pGpu, struct OBJUVM *pUvm, NvP64 *arg0, NvP64 *arg1, NvP64 *arg2, NvP64 *arg3, NvP64 *arg4, NvP64 *arg5, NvU32 *arg6); +NV_STATUS uvmGetAccessCntrRegisterMappings_TU102(OBJGPU *pGpu, struct OBJUVM *pUvm, NvU32 accessCounterIndex, NvP64 *arg0, NvP64 *arg1, NvP64 *arg2, NvP64 *arg3, NvP64 *arg4, NvP64 *arg5, NvU32 *arg6); #ifdef __nvoc_uvm_h_disabled -static inline NV_STATUS uvmGetAccessCntrRegisterMappings(OBJGPU *pGpu, struct OBJUVM *pUvm, NvP64 *arg0, NvP64 *arg1, NvP64 *arg2, NvP64 *arg3, NvP64 *arg4, NvP64 *arg5, NvU32 *arg6) { +static inline NV_STATUS uvmGetAccessCntrRegisterMappings(OBJGPU *pGpu, struct OBJUVM *pUvm, NvU32 accessCounterIndex, NvP64 *arg0, NvP64 *arg1, NvP64 *arg2, NvP64 *arg3, NvP64 *arg4, NvP64 *arg5, NvU32 *arg6) { NV_ASSERT_FAILED_PRECOMP("OBJUVM was disabled!"); return NV_ERR_NOT_SUPPORTED; } #else //__nvoc_uvm_h_disabled -#define uvmGetAccessCntrRegisterMappings(pGpu, pUvm, arg0, arg1, arg2, arg3, arg4, arg5, arg6) uvmGetAccessCntrRegisterMappings_TU102(pGpu, pUvm, arg0, arg1, arg2, arg3, arg4, arg5, arg6) +#define uvmGetAccessCntrRegisterMappings(pGpu, pUvm, accessCounterIndex, arg0, arg1, arg2, arg3, arg4, arg5, arg6) uvmGetAccessCntrRegisterMappings_TU102(pGpu, pUvm, accessCounterIndex, arg0, arg1, arg2, arg3, arg4, arg5, arg6) #endif //__nvoc_uvm_h_disabled -#define uvmGetAccessCntrRegisterMappings_HAL(pGpu, pUvm, arg0, arg1, arg2, arg3, arg4, arg5, arg6) uvmGetAccessCntrRegisterMappings(pGpu, pUvm, arg0, arg1, arg2, arg3, arg4, arg5, arg6) +#define uvmGetAccessCntrRegisterMappings_HAL(pGpu, pUvm, accessCounterIndex, arg0, arg1, arg2, arg3, arg4, arg5, arg6) uvmGetAccessCntrRegisterMappings(pGpu, pUvm, accessCounterIndex, arg0, arg1, arg2, arg3, arg4, arg5, arg6) NV_STATUS uvmAccessCntrService_TU102(OBJGPU *pGpu, struct OBJUVM *pUvm); @@ -497,73 +496,171 @@ #define uvmAccessCntrService_HAL(pGpu, pUvm) uvmAccessCntrService(pGpu, pUvm) -NvU32 uvmGetAccessCounterBufferSize_TU102(OBJGPU *pGpu, struct OBJUVM *pUvm); +NvU32 uvmGetAccessCounterBufferSize_TU102(OBJGPU *pGpu, struct OBJUVM *pUvm, NvU32 accessCounterIndex); #ifdef __nvoc_uvm_h_disabled -static inline NvU32 uvmGetAccessCounterBufferSize(OBJGPU *pGpu, struct OBJUVM *pUvm) { +static inline NvU32 uvmGetAccessCounterBufferSize(OBJGPU *pGpu, struct OBJUVM *pUvm, NvU32 accessCounterIndex) { NV_ASSERT_FAILED_PRECOMP("OBJUVM was disabled!"); return 0; } #else //__nvoc_uvm_h_disabled -#define uvmGetAccessCounterBufferSize(pGpu, pUvm) uvmGetAccessCounterBufferSize_TU102(pGpu, pUvm) +#define uvmGetAccessCounterBufferSize(pGpu, pUvm, accessCounterIndex) uvmGetAccessCounterBufferSize_TU102(pGpu, pUvm, accessCounterIndex) #endif //__nvoc_uvm_h_disabled -#define uvmGetAccessCounterBufferSize_HAL(pGpu, pUvm) uvmGetAccessCounterBufferSize(pGpu, pUvm) +#define uvmGetAccessCounterBufferSize_HAL(pGpu, pUvm, accessCounterIndex) uvmGetAccessCounterBufferSize(pGpu, pUvm, accessCounterIndex) -void uvmProgramWriteAccessCntrBufferAddress_TU102(OBJGPU *pGpu, struct OBJUVM *pUvm, NvU64 addr); +void uvmProgramWriteAccessCntrBufferAddress_TU102(OBJGPU *pGpu, struct OBJUVM *pUvm, NvU32 accessCounterIndex, NvU64 addr); #ifdef __nvoc_uvm_h_disabled -static inline void uvmProgramWriteAccessCntrBufferAddress(OBJGPU *pGpu, struct OBJUVM *pUvm, NvU64 addr) { +static inline void uvmProgramWriteAccessCntrBufferAddress(OBJGPU *pGpu, struct OBJUVM *pUvm, NvU32 accessCounterIndex, NvU64 addr) { NV_ASSERT_FAILED_PRECOMP("OBJUVM was disabled!"); } #else //__nvoc_uvm_h_disabled -#define uvmProgramWriteAccessCntrBufferAddress(pGpu, pUvm, addr) uvmProgramWriteAccessCntrBufferAddress_TU102(pGpu, pUvm, addr) +#define uvmProgramWriteAccessCntrBufferAddress(pGpu, pUvm, accessCounterIndex, addr) uvmProgramWriteAccessCntrBufferAddress_TU102(pGpu, pUvm, accessCounterIndex, addr) #endif //__nvoc_uvm_h_disabled -#define uvmProgramWriteAccessCntrBufferAddress_HAL(pGpu, pUvm, addr) uvmProgramWriteAccessCntrBufferAddress(pGpu, pUvm, addr) +#define uvmProgramWriteAccessCntrBufferAddress_HAL(pGpu, pUvm, accessCounterIndex, addr) uvmProgramWriteAccessCntrBufferAddress(pGpu, pUvm, accessCounterIndex, addr) -void uvmProgramAccessCntrBufferEnabled_TU102(OBJGPU *pGpu, struct OBJUVM *pUvm, NvBool bEn); +void uvmProgramAccessCntrBufferEnabled_TU102(OBJGPU *pGpu, struct OBJUVM *pUvm, NvU32 accessCounterIndex, NvBool bEn); #ifdef __nvoc_uvm_h_disabled -static inline void uvmProgramAccessCntrBufferEnabled(OBJGPU *pGpu, struct OBJUVM *pUvm, NvBool bEn) { +static inline void uvmProgramAccessCntrBufferEnabled(OBJGPU *pGpu, struct OBJUVM *pUvm, NvU32 accessCounterIndex, NvBool bEn) { NV_ASSERT_FAILED_PRECOMP("OBJUVM was disabled!"); } #else //__nvoc_uvm_h_disabled -#define uvmProgramAccessCntrBufferEnabled(pGpu, pUvm, bEn) uvmProgramAccessCntrBufferEnabled_TU102(pGpu, pUvm, bEn) +#define uvmProgramAccessCntrBufferEnabled(pGpu, pUvm, accessCounterIndex, bEn) uvmProgramAccessCntrBufferEnabled_TU102(pGpu, pUvm, accessCounterIndex, bEn) #endif //__nvoc_uvm_h_disabled -#define uvmProgramAccessCntrBufferEnabled_HAL(pGpu, pUvm, bEn) uvmProgramAccessCntrBufferEnabled(pGpu, pUvm, bEn) +#define uvmProgramAccessCntrBufferEnabled_HAL(pGpu, pUvm, accessCounterIndex, bEn) uvmProgramAccessCntrBufferEnabled(pGpu, pUvm, accessCounterIndex, bEn) -NvBool uvmIsAccessCntrBufferEnabled_TU102(OBJGPU *pGpu, struct OBJUVM *pUvm); +NvBool uvmIsAccessCntrBufferEnabled_TU102(OBJGPU *pGpu, struct OBJUVM *pUvm, NvU32 accessCounterIndex); #ifdef __nvoc_uvm_h_disabled -static inline NvBool uvmIsAccessCntrBufferEnabled(OBJGPU *pGpu, struct OBJUVM *pUvm) { +static inline NvBool uvmIsAccessCntrBufferEnabled(OBJGPU *pGpu, struct OBJUVM *pUvm, NvU32 accessCounterIndex) { NV_ASSERT_FAILED_PRECOMP("OBJUVM was disabled!"); return NV_FALSE; } #else //__nvoc_uvm_h_disabled -#define uvmIsAccessCntrBufferEnabled(pGpu, pUvm) uvmIsAccessCntrBufferEnabled_TU102(pGpu, pUvm) +#define uvmIsAccessCntrBufferEnabled(pGpu, pUvm, accessCounterIndex) uvmIsAccessCntrBufferEnabled_TU102(pGpu, pUvm, accessCounterIndex) #endif //__nvoc_uvm_h_disabled -#define uvmIsAccessCntrBufferEnabled_HAL(pGpu, pUvm) uvmIsAccessCntrBufferEnabled(pGpu, pUvm) +#define uvmIsAccessCntrBufferEnabled_HAL(pGpu, pUvm, accessCounterIndex) uvmIsAccessCntrBufferEnabled(pGpu, pUvm, accessCounterIndex) -NvBool uvmIsAccessCntrBufferPushed_TU102(OBJGPU *pGpu, struct OBJUVM *pUvm); +NvBool uvmIsAccessCntrBufferPushed_TU102(OBJGPU *pGpu, struct OBJUVM *pUvm, NvU32 accessCounterIndex); #ifdef __nvoc_uvm_h_disabled -static inline NvBool uvmIsAccessCntrBufferPushed(OBJGPU *pGpu, struct OBJUVM *pUvm) { +static inline NvBool uvmIsAccessCntrBufferPushed(OBJGPU *pGpu, struct OBJUVM *pUvm, NvU32 accessCounterIndex) { NV_ASSERT_FAILED_PRECOMP("OBJUVM was disabled!"); return NV_FALSE; } #else //__nvoc_uvm_h_disabled -#define uvmIsAccessCntrBufferPushed(pGpu, pUvm) uvmIsAccessCntrBufferPushed_TU102(pGpu, pUvm) +#define uvmIsAccessCntrBufferPushed(pGpu, pUvm, accessCounterIndex) uvmIsAccessCntrBufferPushed_TU102(pGpu, pUvm, accessCounterIndex) +#endif //__nvoc_uvm_h_disabled + +#define uvmIsAccessCntrBufferPushed_HAL(pGpu, pUvm, accessCounterIndex) uvmIsAccessCntrBufferPushed(pGpu, pUvm, accessCounterIndex) + +NvU32 uvmGetRegOffsetAccessCntrBufferPut_TU102(struct OBJUVM *pUvm, NvU32 accessCounterIndex); + + +#ifdef __nvoc_uvm_h_disabled +static inline NvU32 uvmGetRegOffsetAccessCntrBufferPut(struct OBJUVM *pUvm, NvU32 accessCounterIndex) { + NV_ASSERT_FAILED_PRECOMP("OBJUVM was disabled!"); + return 0; +} +#else //__nvoc_uvm_h_disabled +#define uvmGetRegOffsetAccessCntrBufferPut(pUvm, accessCounterIndex) uvmGetRegOffsetAccessCntrBufferPut_TU102(pUvm, accessCounterIndex) +#endif //__nvoc_uvm_h_disabled + +#define uvmGetRegOffsetAccessCntrBufferPut_HAL(pUvm, accessCounterIndex) uvmGetRegOffsetAccessCntrBufferPut(pUvm, accessCounterIndex) + +NvU32 uvmGetRegOffsetAccessCntrBufferGet_TU102(struct OBJUVM *pUvm, NvU32 accessCounterIndex); + + +#ifdef __nvoc_uvm_h_disabled +static inline NvU32 uvmGetRegOffsetAccessCntrBufferGet(struct OBJUVM *pUvm, NvU32 accessCounterIndex) { + NV_ASSERT_FAILED_PRECOMP("OBJUVM was disabled!"); + return 0; +} +#else //__nvoc_uvm_h_disabled +#define uvmGetRegOffsetAccessCntrBufferGet(pUvm, accessCounterIndex) uvmGetRegOffsetAccessCntrBufferGet_TU102(pUvm, accessCounterIndex) +#endif //__nvoc_uvm_h_disabled + +#define uvmGetRegOffsetAccessCntrBufferGet_HAL(pUvm, accessCounterIndex) uvmGetRegOffsetAccessCntrBufferGet(pUvm, accessCounterIndex) + +NvU32 uvmGetRegOffsetAccessCntrBufferHi_TU102(struct OBJUVM *pUvm, NvU32 accessCounterIndex); + + +#ifdef __nvoc_uvm_h_disabled +static inline NvU32 uvmGetRegOffsetAccessCntrBufferHi(struct OBJUVM *pUvm, NvU32 accessCounterIndex) { + NV_ASSERT_FAILED_PRECOMP("OBJUVM was disabled!"); + return 0; +} +#else //__nvoc_uvm_h_disabled +#define uvmGetRegOffsetAccessCntrBufferHi(pUvm, accessCounterIndex) uvmGetRegOffsetAccessCntrBufferHi_TU102(pUvm, accessCounterIndex) #endif //__nvoc_uvm_h_disabled -#define uvmIsAccessCntrBufferPushed_HAL(pGpu, pUvm) uvmIsAccessCntrBufferPushed(pGpu, pUvm) +#define uvmGetRegOffsetAccessCntrBufferHi_HAL(pUvm, accessCounterIndex) uvmGetRegOffsetAccessCntrBufferHi(pUvm, accessCounterIndex) + +NvU32 uvmGetRegOffsetAccessCntrBufferLo_TU102(struct OBJUVM *pUvm, NvU32 accessCounterIndex); + + +#ifdef __nvoc_uvm_h_disabled +static inline NvU32 uvmGetRegOffsetAccessCntrBufferLo(struct OBJUVM *pUvm, NvU32 accessCounterIndex) { + NV_ASSERT_FAILED_PRECOMP("OBJUVM was disabled!"); + return 0; +} +#else //__nvoc_uvm_h_disabled +#define uvmGetRegOffsetAccessCntrBufferLo(pUvm, accessCounterIndex) uvmGetRegOffsetAccessCntrBufferLo_TU102(pUvm, accessCounterIndex) +#endif //__nvoc_uvm_h_disabled + +#define uvmGetRegOffsetAccessCntrBufferLo_HAL(pUvm, accessCounterIndex) uvmGetRegOffsetAccessCntrBufferLo(pUvm, accessCounterIndex) + +NvU32 uvmGetRegOffsetAccessCntrBufferConfig_TU102(struct OBJUVM *pUvm, NvU32 accessCounterIndex); + + +#ifdef __nvoc_uvm_h_disabled +static inline NvU32 uvmGetRegOffsetAccessCntrBufferConfig(struct OBJUVM *pUvm, NvU32 accessCounterIndex) { + NV_ASSERT_FAILED_PRECOMP("OBJUVM was disabled!"); + return 0; +} +#else //__nvoc_uvm_h_disabled +#define uvmGetRegOffsetAccessCntrBufferConfig(pUvm, accessCounterIndex) uvmGetRegOffsetAccessCntrBufferConfig_TU102(pUvm, accessCounterIndex) +#endif //__nvoc_uvm_h_disabled + +#define uvmGetRegOffsetAccessCntrBufferConfig_HAL(pUvm, accessCounterIndex) uvmGetRegOffsetAccessCntrBufferConfig(pUvm, accessCounterIndex) + +NvU32 uvmGetRegOffsetAccessCntrBufferInfo_TU102(struct OBJUVM *pUvm, NvU32 accessCounterIndex); + + +#ifdef __nvoc_uvm_h_disabled +static inline NvU32 uvmGetRegOffsetAccessCntrBufferInfo(struct OBJUVM *pUvm, NvU32 accessCounterIndex) { + NV_ASSERT_FAILED_PRECOMP("OBJUVM was disabled!"); + return 0; +} +#else //__nvoc_uvm_h_disabled +#define uvmGetRegOffsetAccessCntrBufferInfo(pUvm, accessCounterIndex) uvmGetRegOffsetAccessCntrBufferInfo_TU102(pUvm, accessCounterIndex) +#endif //__nvoc_uvm_h_disabled + +#define uvmGetRegOffsetAccessCntrBufferInfo_HAL(pUvm, accessCounterIndex) uvmGetRegOffsetAccessCntrBufferInfo(pUvm, accessCounterIndex) + +NvU32 uvmGetRegOffsetAccessCntrBufferSize_TU102(struct OBJUVM *pUvm, NvU32 accessCounterIndex); + + +#ifdef __nvoc_uvm_h_disabled +static inline NvU32 uvmGetRegOffsetAccessCntrBufferSize(struct OBJUVM *pUvm, NvU32 accessCounterIndex) { + NV_ASSERT_FAILED_PRECOMP("OBJUVM was disabled!"); + return 0; +} +#else //__nvoc_uvm_h_disabled +#define uvmGetRegOffsetAccessCntrBufferSize(pUvm, accessCounterIndex) uvmGetRegOffsetAccessCntrBufferSize_TU102(pUvm, accessCounterIndex) +#endif //__nvoc_uvm_h_disabled + +#define uvmGetRegOffsetAccessCntrBufferSize_HAL(pUvm, accessCounterIndex) uvmGetRegOffsetAccessCntrBufferSize(pUvm, accessCounterIndex) void uvmStateDestroy_IMPL(OBJGPU *pGpu, struct OBJUVM *pUvm); @@ -577,9 +674,9 @@ return pUvm->__uvmStateInitUnlocked__(pGpu, pUvm); } -void uvmRegisterIntrService_IMPL(OBJGPU *arg0, struct OBJUVM *pUvm, IntrServiceRecord arg1[163]); +void uvmRegisterIntrService_IMPL(OBJGPU *arg0, struct OBJUVM *pUvm, IntrServiceRecord arg1[167]); -static inline void uvmRegisterIntrService_DISPATCH(OBJGPU *arg0, struct OBJUVM *pUvm, IntrServiceRecord arg1[163]) { +static inline void uvmRegisterIntrService_DISPATCH(OBJGPU *arg0, struct OBJUVM *pUvm, IntrServiceRecord arg1[167]) { pUvm->__uvmRegisterIntrService__(arg0, pUvm, arg1); } @@ -589,10 +686,6 @@ return pUvm->__uvmServiceInterrupt__(arg0, pUvm, arg1); } -static inline NV_STATUS uvmReconcileTunableState_DISPATCH(POBJGPU pGpu, struct OBJUVM *pEngstate, void *pTunableState) { - return pEngstate->__uvmReconcileTunableState__(pGpu, pEngstate, pTunableState); -} - static inline NV_STATUS uvmStateLoad_DISPATCH(POBJGPU pGpu, struct OBJUVM *pEngstate, NvU32 arg0) { return pEngstate->__uvmStateLoad__(pGpu, pEngstate, arg0); } @@ -633,18 +726,6 @@ return pEngstate->__uvmStatePreInitUnlocked__(pGpu, pEngstate); } -static inline NV_STATUS uvmGetTunableState_DISPATCH(POBJGPU pGpu, struct OBJUVM *pEngstate, void *pTunableState) { - return pEngstate->__uvmGetTunableState__(pGpu, pEngstate, pTunableState); -} - -static inline NV_STATUS uvmCompareTunableState_DISPATCH(POBJGPU pGpu, struct OBJUVM *pEngstate, void *pTunables1, void *pTunables2) { - return pEngstate->__uvmCompareTunableState__(pGpu, pEngstate, pTunables1, pTunables2); -} - -static inline void uvmFreeTunableState_DISPATCH(POBJGPU pGpu, struct OBJUVM *pEngstate, void *pTunableState) { - pEngstate->__uvmFreeTunableState__(pGpu, pEngstate, pTunableState); -} - static inline NvBool uvmClearInterrupt_DISPATCH(OBJGPU *pGpu, struct OBJUVM *pIntrService, IntrServiceClearInterruptArguments *pParams) { return pIntrService->__uvmClearInterrupt__(pGpu, pIntrService, pParams); } @@ -653,14 +734,6 @@ return pEngstate->__uvmStatePostLoad__(pGpu, pEngstate, arg0); } -static inline NV_STATUS uvmAllocTunableState_DISPATCH(POBJGPU pGpu, struct OBJUVM *pEngstate, void **ppTunableState) { - return pEngstate->__uvmAllocTunableState__(pGpu, pEngstate, ppTunableState); -} - -static inline NV_STATUS uvmSetTunableState_DISPATCH(POBJGPU pGpu, struct OBJUVM *pEngstate, void *pTunableState) { - return pEngstate->__uvmSetTunableState__(pGpu, pEngstate, pTunableState); -} - static inline NV_STATUS uvmConstructEngine_DISPATCH(POBJGPU pGpu, struct OBJUVM *pEngstate, ENGDESCRIPTOR arg0) { return pEngstate->__uvmConstructEngine__(pGpu, pEngstate, arg0); } diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/generated/g_uvm_sw_nvoc.c nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_uvm_sw_nvoc.c --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/generated/g_uvm_sw_nvoc.c 2023-10-25 20:27:22.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_uvm_sw_nvoc.c 2024-03-05 22:18:50.000000000 +0000 @@ -120,7 +120,7 @@ /*pExportInfo=*/ &__nvoc_export_info_UvmSwObject }; -static NV_STATUS __nvoc_thunk_UvmSwObject_chandesGetSwMethods(struct ChannelDescendant *pUvmSw, METHOD **ppMethods, NvU32 *pNumMethods) { +static NV_STATUS __nvoc_thunk_UvmSwObject_chandesGetSwMethods(struct ChannelDescendant *pUvmSw, const METHOD **ppMethods, NvU32 *pNumMethods) { return uvmswGetSwMethods((struct UvmSwObject *)(((unsigned char *)pUvmSw) - __nvoc_rtti_UvmSwObject_ChannelDescendant.offset), ppMethods, pNumMethods); } @@ -212,6 +212,10 @@ return notifyUnregisterEvent((struct Notifier *)(((unsigned char *)pNotifier) + __nvoc_rtti_UvmSwObject_Notifier.offset), hNotifierClient, hNotifierResource, hEventClient, hEvent); } +static NV_STATUS __nvoc_thunk_RmResource_uvmswControlSerialization_Prologue(struct UvmSwObject *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return rmresControlSerialization_Prologue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_UvmSwObject_RmResource.offset), pCallContext, pParams); +} + static NvBool __nvoc_thunk_RsResource_uvmswCanCopy(struct UvmSwObject *pResource) { return resCanCopy((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_UvmSwObject_RsResource.offset)); } @@ -224,6 +228,10 @@ return resIsDuplicate((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_UvmSwObject_RsResource.offset), hMemory, pDuplicate); } +static void __nvoc_thunk_RmResource_uvmswControlSerialization_Epilogue(struct UvmSwObject *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + rmresControlSerialization_Epilogue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_UvmSwObject_RmResource.offset), pCallContext, pParams); +} + static PEVENTNOTIFICATION *__nvoc_thunk_Notifier_uvmswGetNotificationListPtr(struct UvmSwObject *pNotifier) { return notifyGetNotificationListPtr((struct Notifier *)(((unsigned char *)pNotifier) + __nvoc_rtti_UvmSwObject_Notifier.offset)); } @@ -290,10 +298,7 @@ PORT_UNREFERENCED_VARIABLE(rmVariantHal_HalVarIdx); // Hal function -- uvmswGetSwMethods - if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000002UL) )) /* RmVariantHal: PF_KERNEL_ONLY */ - { - pThis->__uvmswGetSwMethods__ = &uvmswGetSwMethods_56cd7a; - } + pThis->__uvmswGetSwMethods__ = &uvmswGetSwMethods_56cd7a; pThis->__nvoc_base_ChannelDescendant.__chandesGetSwMethods__ = &__nvoc_thunk_UvmSwObject_chandesGetSwMethods; @@ -341,12 +346,16 @@ pThis->__uvmswUnregisterEvent__ = &__nvoc_thunk_Notifier_uvmswUnregisterEvent; + pThis->__uvmswControlSerialization_Prologue__ = &__nvoc_thunk_RmResource_uvmswControlSerialization_Prologue; + pThis->__uvmswCanCopy__ = &__nvoc_thunk_RsResource_uvmswCanCopy; pThis->__uvmswPreDestruct__ = &__nvoc_thunk_RsResource_uvmswPreDestruct; pThis->__uvmswIsDuplicate__ = &__nvoc_thunk_RsResource_uvmswIsDuplicate; + pThis->__uvmswControlSerialization_Epilogue__ = &__nvoc_thunk_RmResource_uvmswControlSerialization_Epilogue; + pThis->__uvmswGetNotificationListPtr__ = &__nvoc_thunk_Notifier_uvmswGetNotificationListPtr; pThis->__uvmswGetNotificationShare__ = &__nvoc_thunk_Notifier_uvmswGetNotificationShare; @@ -381,13 +390,16 @@ UvmSwObject *pThis; RmHalspecOwner *pRmhalspecowner; - pThis = portMemAllocNonPaged(sizeof(UvmSwObject)); - if (pThis == NULL) return NV_ERR_NO_MEMORY; + status = __nvoc_handleObjCreateMemAlloc(createFlags, sizeof(UvmSwObject), (void**)&pThis, (void**)ppThis); + if (status != NV_OK) + return status; portMemSet(pThis, 0, sizeof(UvmSwObject)); __nvoc_initRtti(staticCast(pThis, Dynamic), &__nvoc_class_def_UvmSwObject); + pThis->__nvoc_base_ChannelDescendant.__nvoc_base_GpuResource.__nvoc_base_RmResource.__nvoc_base_RsResource.__nvoc_base_Object.createFlags = createFlags; + if (pParent != NULL && !(createFlags & NVOC_OBJ_CREATE_FLAGS_PARENT_HALSPEC_ONLY)) { pParentObj = dynamicCast(pParent, Object); @@ -407,11 +419,17 @@ if (status != NV_OK) goto __nvoc_objCreate_UvmSwObject_cleanup; *ppThis = pThis; + return NV_OK; __nvoc_objCreate_UvmSwObject_cleanup: // do not call destructors here since the constructor already called them - portMemFree(pThis); + if (createFlags & NVOC_OBJ_CREATE_FLAGS_IN_PLACE_CONSTRUCT) + portMemSet(pThis, 0, sizeof(UvmSwObject)); + else + portMemFree(pThis); + + // coverity[leaked_storage:FALSE] return status; } diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/generated/g_uvm_sw_nvoc.h nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_uvm_sw_nvoc.h --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/generated/g_uvm_sw_nvoc.h 2023-10-25 20:27:22.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_uvm_sw_nvoc.h 2024-03-05 22:18:50.000000000 +0000 @@ -57,7 +57,7 @@ struct Notifier *__nvoc_pbase_Notifier; struct ChannelDescendant *__nvoc_pbase_ChannelDescendant; struct UvmSwObject *__nvoc_pbase_UvmSwObject; - NV_STATUS (*__uvmswGetSwMethods__)(struct UvmSwObject *, METHOD **, NvU32 *); + NV_STATUS (*__uvmswGetSwMethods__)(struct UvmSwObject *, const METHOD **, NvU32 *); NV_STATUS (*__uvmswCheckMemInterUnmap__)(struct UvmSwObject *, NvBool); NvBool (*__uvmswShareCallback__)(struct UvmSwObject *, struct RsClient *, struct RsResourceRef *, RS_SHARE_POLICY *); NvBool (*__uvmswAccessCallback__)(struct UvmSwObject *, struct RsClient *, void *, RsAccessRight); @@ -80,9 +80,11 @@ NvBool (*__uvmswIsSwMethodStalling__)(struct UvmSwObject *, NvU32); NV_STATUS (*__uvmswControlFilter__)(struct UvmSwObject *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); NV_STATUS (*__uvmswUnregisterEvent__)(struct UvmSwObject *, NvHandle, NvHandle, NvHandle, NvHandle); + NV_STATUS (*__uvmswControlSerialization_Prologue__)(struct UvmSwObject *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); NvBool (*__uvmswCanCopy__)(struct UvmSwObject *); void (*__uvmswPreDestruct__)(struct UvmSwObject *); NV_STATUS (*__uvmswIsDuplicate__)(struct UvmSwObject *, NvHandle, NvBool *); + void (*__uvmswControlSerialization_Epilogue__)(struct UvmSwObject *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); PEVENTNOTIFICATION *(*__uvmswGetNotificationListPtr__)(struct UvmSwObject *); struct NotifShare *(*__uvmswGetNotificationShare__)(struct UvmSwObject *); NV_STATUS (*__uvmswMap__)(struct UvmSwObject *, struct CALL_CONTEXT *, struct RS_CPU_MAP_PARAMS *, struct RsCpuMapping *); @@ -146,18 +148,20 @@ #define uvmswIsSwMethodStalling(pChannelDescendant, hHandle) uvmswIsSwMethodStalling_DISPATCH(pChannelDescendant, hHandle) #define uvmswControlFilter(pResource, pCallContext, pParams) uvmswControlFilter_DISPATCH(pResource, pCallContext, pParams) #define uvmswUnregisterEvent(pNotifier, hNotifierClient, hNotifierResource, hEventClient, hEvent) uvmswUnregisterEvent_DISPATCH(pNotifier, hNotifierClient, hNotifierResource, hEventClient, hEvent) +#define uvmswControlSerialization_Prologue(pResource, pCallContext, pParams) uvmswControlSerialization_Prologue_DISPATCH(pResource, pCallContext, pParams) #define uvmswCanCopy(pResource) uvmswCanCopy_DISPATCH(pResource) #define uvmswPreDestruct(pResource) uvmswPreDestruct_DISPATCH(pResource) #define uvmswIsDuplicate(pResource, hMemory, pDuplicate) uvmswIsDuplicate_DISPATCH(pResource, hMemory, pDuplicate) +#define uvmswControlSerialization_Epilogue(pResource, pCallContext, pParams) uvmswControlSerialization_Epilogue_DISPATCH(pResource, pCallContext, pParams) #define uvmswGetNotificationListPtr(pNotifier) uvmswGetNotificationListPtr_DISPATCH(pNotifier) #define uvmswGetNotificationShare(pNotifier) uvmswGetNotificationShare_DISPATCH(pNotifier) #define uvmswMap(pGpuResource, pCallContext, pParams, pCpuMapping) uvmswMap_DISPATCH(pGpuResource, pCallContext, pParams, pCpuMapping) #define uvmswGetOrAllocNotifShare(pNotifier, hNotifierClient, hNotifierResource, ppNotifShare) uvmswGetOrAllocNotifShare_DISPATCH(pNotifier, hNotifierClient, hNotifierResource, ppNotifShare) -static inline NV_STATUS uvmswGetSwMethods_56cd7a(struct UvmSwObject *pUvmSw, METHOD **ppMethods, NvU32 *pNumMethods) { +static inline NV_STATUS uvmswGetSwMethods_56cd7a(struct UvmSwObject *pUvmSw, const METHOD **ppMethods, NvU32 *pNumMethods) { return NV_OK; } -static inline NV_STATUS uvmswGetSwMethods_DISPATCH(struct UvmSwObject *pUvmSw, METHOD **ppMethods, NvU32 *pNumMethods) { +static inline NV_STATUS uvmswGetSwMethods_DISPATCH(struct UvmSwObject *pUvmSw, const METHOD **ppMethods, NvU32 *pNumMethods) { return pUvmSw->__uvmswGetSwMethods__(pUvmSw, ppMethods, pNumMethods); } @@ -249,6 +253,10 @@ return pNotifier->__uvmswUnregisterEvent__(pNotifier, hNotifierClient, hNotifierResource, hEventClient, hEvent); } +static inline NV_STATUS uvmswControlSerialization_Prologue_DISPATCH(struct UvmSwObject *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return pResource->__uvmswControlSerialization_Prologue__(pResource, pCallContext, pParams); +} + static inline NvBool uvmswCanCopy_DISPATCH(struct UvmSwObject *pResource) { return pResource->__uvmswCanCopy__(pResource); } @@ -261,6 +269,10 @@ return pResource->__uvmswIsDuplicate__(pResource, hMemory, pDuplicate); } +static inline void uvmswControlSerialization_Epilogue_DISPATCH(struct UvmSwObject *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + pResource->__uvmswControlSerialization_Epilogue__(pResource, pCallContext, pParams); +} + static inline PEVENTNOTIFICATION *uvmswGetNotificationListPtr_DISPATCH(struct UvmSwObject *pNotifier) { return pNotifier->__uvmswGetNotificationListPtr__(pNotifier); } diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/generated/g_vaspace_api_nvoc.c nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_vaspace_api_nvoc.c --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/generated/g_vaspace_api_nvoc.c 2023-10-25 20:27:22.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_vaspace_api_nvoc.c 2024-03-05 22:18:50.000000000 +0000 @@ -101,48 +101,24 @@ return gpuresShareCallback((struct GpuResource *)(((unsigned char *)pGpuResource) + __nvoc_rtti_VaSpaceApi_GpuResource.offset), pInvokingClient, pParentRef, pSharePolicy); } -static NV_STATUS __nvoc_thunk_GpuResource_vaspaceapiControl(struct VaSpaceApi *pGpuResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { - return gpuresControl((struct GpuResource *)(((unsigned char *)pGpuResource) + __nvoc_rtti_VaSpaceApi_GpuResource.offset), pCallContext, pParams); -} - -static NV_STATUS __nvoc_thunk_GpuResource_vaspaceapiUnmap(struct VaSpaceApi *pGpuResource, struct CALL_CONTEXT *pCallContext, struct RsCpuMapping *pCpuMapping) { - return gpuresUnmap((struct GpuResource *)(((unsigned char *)pGpuResource) + __nvoc_rtti_VaSpaceApi_GpuResource.offset), pCallContext, pCpuMapping); -} - -static NV_STATUS __nvoc_thunk_RmResource_vaspaceapiGetMemInterMapParams(struct VaSpaceApi *pRmResource, RMRES_MEM_INTER_MAP_PARAMS *pParams) { - return rmresGetMemInterMapParams((struct RmResource *)(((unsigned char *)pRmResource) + __nvoc_rtti_VaSpaceApi_RmResource.offset), pParams); +static NV_STATUS __nvoc_thunk_RmResource_vaspaceapiCheckMemInterUnmap(struct VaSpaceApi *pRmResource, NvBool bSubdeviceHandleProvided) { + return rmresCheckMemInterUnmap((struct RmResource *)(((unsigned char *)pRmResource) + __nvoc_rtti_VaSpaceApi_RmResource.offset), bSubdeviceHandleProvided); } -static NV_STATUS __nvoc_thunk_RmResource_vaspaceapiGetMemoryMappingDescriptor(struct VaSpaceApi *pRmResource, struct MEMORY_DESCRIPTOR **ppMemDesc) { - return rmresGetMemoryMappingDescriptor((struct RmResource *)(((unsigned char *)pRmResource) + __nvoc_rtti_VaSpaceApi_RmResource.offset), ppMemDesc); +static NV_STATUS __nvoc_thunk_RsResource_vaspaceapiMapTo(struct VaSpaceApi *pResource, RS_RES_MAP_TO_PARAMS *pParams) { + return resMapTo((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_VaSpaceApi_RsResource.offset), pParams); } static NV_STATUS __nvoc_thunk_GpuResource_vaspaceapiGetMapAddrSpace(struct VaSpaceApi *pGpuResource, struct CALL_CONTEXT *pCallContext, NvU32 mapFlags, NV_ADDRESS_SPACE *pAddrSpace) { return gpuresGetMapAddrSpace((struct GpuResource *)(((unsigned char *)pGpuResource) + __nvoc_rtti_VaSpaceApi_GpuResource.offset), pCallContext, mapFlags, pAddrSpace); } -static NvHandle __nvoc_thunk_GpuResource_vaspaceapiGetInternalObjectHandle(struct VaSpaceApi *pGpuResource) { - return gpuresGetInternalObjectHandle((struct GpuResource *)(((unsigned char *)pGpuResource) + __nvoc_rtti_VaSpaceApi_GpuResource.offset)); -} - -static NV_STATUS __nvoc_thunk_RsResource_vaspaceapiControlFilter(struct VaSpaceApi *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { - return resControlFilter((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_VaSpaceApi_RsResource.offset), pCallContext, pParams); -} - -static void __nvoc_thunk_RsResource_vaspaceapiAddAdditionalDependants(struct RsClient *pClient, struct VaSpaceApi *pResource, RsResourceRef *pReference) { - resAddAdditionalDependants(pClient, (struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_VaSpaceApi_RsResource.offset), pReference); -} - static NvU32 __nvoc_thunk_RsResource_vaspaceapiGetRefCount(struct VaSpaceApi *pResource) { return resGetRefCount((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_VaSpaceApi_RsResource.offset)); } -static NV_STATUS __nvoc_thunk_RmResource_vaspaceapiCheckMemInterUnmap(struct VaSpaceApi *pRmResource, NvBool bSubdeviceHandleProvided) { - return rmresCheckMemInterUnmap((struct RmResource *)(((unsigned char *)pRmResource) + __nvoc_rtti_VaSpaceApi_RmResource.offset), bSubdeviceHandleProvided); -} - -static NV_STATUS __nvoc_thunk_RsResource_vaspaceapiMapTo(struct VaSpaceApi *pResource, RS_RES_MAP_TO_PARAMS *pParams) { - return resMapTo((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_VaSpaceApi_RsResource.offset), pParams); +static void __nvoc_thunk_RsResource_vaspaceapiAddAdditionalDependants(struct RsClient *pClient, struct VaSpaceApi *pResource, RsResourceRef *pReference) { + resAddAdditionalDependants(pClient, (struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_VaSpaceApi_RsResource.offset), pReference); } static NV_STATUS __nvoc_thunk_RmResource_vaspaceapiControl_Prologue(struct VaSpaceApi *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { @@ -157,18 +133,10 @@ return gpuresInternalControlForward((struct GpuResource *)(((unsigned char *)pGpuResource) + __nvoc_rtti_VaSpaceApi_GpuResource.offset), command, pParams, size); } -static void __nvoc_thunk_RsResource_vaspaceapiPreDestruct(struct VaSpaceApi *pResource) { - resPreDestruct((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_VaSpaceApi_RsResource.offset)); -} - static NV_STATUS __nvoc_thunk_RsResource_vaspaceapiUnmapFrom(struct VaSpaceApi *pResource, RS_RES_UNMAP_FROM_PARAMS *pParams) { return resUnmapFrom((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_VaSpaceApi_RsResource.offset), pParams); } -static NV_STATUS __nvoc_thunk_RsResource_vaspaceapiIsDuplicate(struct VaSpaceApi *pResource, NvHandle hMemory, NvBool *pDuplicate) { - return resIsDuplicate((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_VaSpaceApi_RsResource.offset), hMemory, pDuplicate); -} - static void __nvoc_thunk_RmResource_vaspaceapiControl_Epilogue(struct VaSpaceApi *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { rmresControl_Epilogue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_VaSpaceApi_RmResource.offset), pCallContext, pParams); } @@ -177,6 +145,46 @@ return resControlLookup((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_VaSpaceApi_RsResource.offset), pParams, ppEntry); } +static NvHandle __nvoc_thunk_GpuResource_vaspaceapiGetInternalObjectHandle(struct VaSpaceApi *pGpuResource) { + return gpuresGetInternalObjectHandle((struct GpuResource *)(((unsigned char *)pGpuResource) + __nvoc_rtti_VaSpaceApi_GpuResource.offset)); +} + +static NV_STATUS __nvoc_thunk_GpuResource_vaspaceapiControl(struct VaSpaceApi *pGpuResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return gpuresControl((struct GpuResource *)(((unsigned char *)pGpuResource) + __nvoc_rtti_VaSpaceApi_GpuResource.offset), pCallContext, pParams); +} + +static NV_STATUS __nvoc_thunk_GpuResource_vaspaceapiUnmap(struct VaSpaceApi *pGpuResource, struct CALL_CONTEXT *pCallContext, struct RsCpuMapping *pCpuMapping) { + return gpuresUnmap((struct GpuResource *)(((unsigned char *)pGpuResource) + __nvoc_rtti_VaSpaceApi_GpuResource.offset), pCallContext, pCpuMapping); +} + +static NV_STATUS __nvoc_thunk_RmResource_vaspaceapiGetMemInterMapParams(struct VaSpaceApi *pRmResource, RMRES_MEM_INTER_MAP_PARAMS *pParams) { + return rmresGetMemInterMapParams((struct RmResource *)(((unsigned char *)pRmResource) + __nvoc_rtti_VaSpaceApi_RmResource.offset), pParams); +} + +static NV_STATUS __nvoc_thunk_RmResource_vaspaceapiGetMemoryMappingDescriptor(struct VaSpaceApi *pRmResource, struct MEMORY_DESCRIPTOR **ppMemDesc) { + return rmresGetMemoryMappingDescriptor((struct RmResource *)(((unsigned char *)pRmResource) + __nvoc_rtti_VaSpaceApi_RmResource.offset), ppMemDesc); +} + +static NV_STATUS __nvoc_thunk_RsResource_vaspaceapiControlFilter(struct VaSpaceApi *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return resControlFilter((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_VaSpaceApi_RsResource.offset), pCallContext, pParams); +} + +static NV_STATUS __nvoc_thunk_RmResource_vaspaceapiControlSerialization_Prologue(struct VaSpaceApi *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return rmresControlSerialization_Prologue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_VaSpaceApi_RmResource.offset), pCallContext, pParams); +} + +static void __nvoc_thunk_RsResource_vaspaceapiPreDestruct(struct VaSpaceApi *pResource) { + resPreDestruct((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_VaSpaceApi_RsResource.offset)); +} + +static NV_STATUS __nvoc_thunk_RsResource_vaspaceapiIsDuplicate(struct VaSpaceApi *pResource, NvHandle hMemory, NvBool *pDuplicate) { + return resIsDuplicate((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_VaSpaceApi_RsResource.offset), hMemory, pDuplicate); +} + +static void __nvoc_thunk_RmResource_vaspaceapiControlSerialization_Epilogue(struct VaSpaceApi *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + rmresControlSerialization_Epilogue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_VaSpaceApi_RmResource.offset), pCallContext, pParams); +} + static NV_STATUS __nvoc_thunk_GpuResource_vaspaceapiMap(struct VaSpaceApi *pGpuResource, struct CALL_CONTEXT *pCallContext, struct RS_CPU_MAP_PARAMS *pParams, struct RsCpuMapping *pCpuMapping) { return gpuresMap((struct GpuResource *)(((unsigned char *)pGpuResource) + __nvoc_rtti_VaSpaceApi_GpuResource.offset), pCallContext, pParams, pCpuMapping); } @@ -334,27 +342,15 @@ pThis->__vaspaceapiShareCallback__ = &__nvoc_thunk_GpuResource_vaspaceapiShareCallback; - pThis->__vaspaceapiControl__ = &__nvoc_thunk_GpuResource_vaspaceapiControl; - - pThis->__vaspaceapiUnmap__ = &__nvoc_thunk_GpuResource_vaspaceapiUnmap; - - pThis->__vaspaceapiGetMemInterMapParams__ = &__nvoc_thunk_RmResource_vaspaceapiGetMemInterMapParams; + pThis->__vaspaceapiCheckMemInterUnmap__ = &__nvoc_thunk_RmResource_vaspaceapiCheckMemInterUnmap; - pThis->__vaspaceapiGetMemoryMappingDescriptor__ = &__nvoc_thunk_RmResource_vaspaceapiGetMemoryMappingDescriptor; + pThis->__vaspaceapiMapTo__ = &__nvoc_thunk_RsResource_vaspaceapiMapTo; pThis->__vaspaceapiGetMapAddrSpace__ = &__nvoc_thunk_GpuResource_vaspaceapiGetMapAddrSpace; - pThis->__vaspaceapiGetInternalObjectHandle__ = &__nvoc_thunk_GpuResource_vaspaceapiGetInternalObjectHandle; - - pThis->__vaspaceapiControlFilter__ = &__nvoc_thunk_RsResource_vaspaceapiControlFilter; - - pThis->__vaspaceapiAddAdditionalDependants__ = &__nvoc_thunk_RsResource_vaspaceapiAddAdditionalDependants; - pThis->__vaspaceapiGetRefCount__ = &__nvoc_thunk_RsResource_vaspaceapiGetRefCount; - pThis->__vaspaceapiCheckMemInterUnmap__ = &__nvoc_thunk_RmResource_vaspaceapiCheckMemInterUnmap; - - pThis->__vaspaceapiMapTo__ = &__nvoc_thunk_RsResource_vaspaceapiMapTo; + pThis->__vaspaceapiAddAdditionalDependants__ = &__nvoc_thunk_RsResource_vaspaceapiAddAdditionalDependants; pThis->__vaspaceapiControl_Prologue__ = &__nvoc_thunk_RmResource_vaspaceapiControl_Prologue; @@ -362,16 +358,32 @@ pThis->__vaspaceapiInternalControlForward__ = &__nvoc_thunk_GpuResource_vaspaceapiInternalControlForward; - pThis->__vaspaceapiPreDestruct__ = &__nvoc_thunk_RsResource_vaspaceapiPreDestruct; - pThis->__vaspaceapiUnmapFrom__ = &__nvoc_thunk_RsResource_vaspaceapiUnmapFrom; - pThis->__vaspaceapiIsDuplicate__ = &__nvoc_thunk_RsResource_vaspaceapiIsDuplicate; - pThis->__vaspaceapiControl_Epilogue__ = &__nvoc_thunk_RmResource_vaspaceapiControl_Epilogue; pThis->__vaspaceapiControlLookup__ = &__nvoc_thunk_RsResource_vaspaceapiControlLookup; + pThis->__vaspaceapiGetInternalObjectHandle__ = &__nvoc_thunk_GpuResource_vaspaceapiGetInternalObjectHandle; + + pThis->__vaspaceapiControl__ = &__nvoc_thunk_GpuResource_vaspaceapiControl; + + pThis->__vaspaceapiUnmap__ = &__nvoc_thunk_GpuResource_vaspaceapiUnmap; + + pThis->__vaspaceapiGetMemInterMapParams__ = &__nvoc_thunk_RmResource_vaspaceapiGetMemInterMapParams; + + pThis->__vaspaceapiGetMemoryMappingDescriptor__ = &__nvoc_thunk_RmResource_vaspaceapiGetMemoryMappingDescriptor; + + pThis->__vaspaceapiControlFilter__ = &__nvoc_thunk_RsResource_vaspaceapiControlFilter; + + pThis->__vaspaceapiControlSerialization_Prologue__ = &__nvoc_thunk_RmResource_vaspaceapiControlSerialization_Prologue; + + pThis->__vaspaceapiPreDestruct__ = &__nvoc_thunk_RsResource_vaspaceapiPreDestruct; + + pThis->__vaspaceapiIsDuplicate__ = &__nvoc_thunk_RsResource_vaspaceapiIsDuplicate; + + pThis->__vaspaceapiControlSerialization_Epilogue__ = &__nvoc_thunk_RmResource_vaspaceapiControlSerialization_Epilogue; + pThis->__vaspaceapiMap__ = &__nvoc_thunk_GpuResource_vaspaceapiMap; pThis->__vaspaceapiAccessCallback__ = &__nvoc_thunk_RmResource_vaspaceapiAccessCallback; @@ -398,13 +410,16 @@ Object *pParentObj; VaSpaceApi *pThis; - pThis = portMemAllocNonPaged(sizeof(VaSpaceApi)); - if (pThis == NULL) return NV_ERR_NO_MEMORY; + status = __nvoc_handleObjCreateMemAlloc(createFlags, sizeof(VaSpaceApi), (void**)&pThis, (void**)ppThis); + if (status != NV_OK) + return status; portMemSet(pThis, 0, sizeof(VaSpaceApi)); __nvoc_initRtti(staticCast(pThis, Dynamic), &__nvoc_class_def_VaSpaceApi); + pThis->__nvoc_base_GpuResource.__nvoc_base_RmResource.__nvoc_base_RsResource.__nvoc_base_Object.createFlags = createFlags; + if (pParent != NULL && !(createFlags & NVOC_OBJ_CREATE_FLAGS_PARENT_HALSPEC_ONLY)) { pParentObj = dynamicCast(pParent, Object); @@ -420,11 +435,17 @@ if (status != NV_OK) goto __nvoc_objCreate_VaSpaceApi_cleanup; *ppThis = pThis; + return NV_OK; __nvoc_objCreate_VaSpaceApi_cleanup: // do not call destructors here since the constructor already called them - portMemFree(pThis); + if (createFlags & NVOC_OBJ_CREATE_FLAGS_IN_PLACE_CONSTRUCT) + portMemSet(pThis, 0, sizeof(VaSpaceApi)); + else + portMemFree(pThis); + + // coverity[leaked_storage:FALSE] return status; } diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/generated/g_vaspace_api_nvoc.h nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_vaspace_api_nvoc.h --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/generated/g_vaspace_api_nvoc.h 2023-10-25 20:27:22.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_vaspace_api_nvoc.h 2024-03-05 22:18:50.000000000 +0000 @@ -28,7 +28,7 @@ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * DEALINGS IN THE SOFTWARE. */ - + #include "g_vaspace_api_nvoc.h" #ifndef VASPACE_API_H @@ -74,25 +74,27 @@ NV_STATUS (*__vaspaceapiCtrlCmdVaspaceReleaseEntries__)(struct VaSpaceApi *, NV90F1_CTRL_VASPACE_RELEASE_ENTRIES_PARAMS *); NV_STATUS (*__vaspaceapiCtrlCmdVaspaceCopyServerReservedPdes__)(struct VaSpaceApi *, NV90F1_CTRL_VASPACE_COPY_SERVER_RESERVED_PDES_PARAMS *); NvBool (*__vaspaceapiShareCallback__)(struct VaSpaceApi *, struct RsClient *, struct RsResourceRef *, RS_SHARE_POLICY *); - NV_STATUS (*__vaspaceapiControl__)(struct VaSpaceApi *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); - NV_STATUS (*__vaspaceapiUnmap__)(struct VaSpaceApi *, struct CALL_CONTEXT *, struct RsCpuMapping *); - NV_STATUS (*__vaspaceapiGetMemInterMapParams__)(struct VaSpaceApi *, RMRES_MEM_INTER_MAP_PARAMS *); - NV_STATUS (*__vaspaceapiGetMemoryMappingDescriptor__)(struct VaSpaceApi *, struct MEMORY_DESCRIPTOR **); - NV_STATUS (*__vaspaceapiGetMapAddrSpace__)(struct VaSpaceApi *, struct CALL_CONTEXT *, NvU32, NV_ADDRESS_SPACE *); - NvHandle (*__vaspaceapiGetInternalObjectHandle__)(struct VaSpaceApi *); - NV_STATUS (*__vaspaceapiControlFilter__)(struct VaSpaceApi *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); - void (*__vaspaceapiAddAdditionalDependants__)(struct RsClient *, struct VaSpaceApi *, RsResourceRef *); - NvU32 (*__vaspaceapiGetRefCount__)(struct VaSpaceApi *); NV_STATUS (*__vaspaceapiCheckMemInterUnmap__)(struct VaSpaceApi *, NvBool); NV_STATUS (*__vaspaceapiMapTo__)(struct VaSpaceApi *, RS_RES_MAP_TO_PARAMS *); + NV_STATUS (*__vaspaceapiGetMapAddrSpace__)(struct VaSpaceApi *, struct CALL_CONTEXT *, NvU32, NV_ADDRESS_SPACE *); + NvU32 (*__vaspaceapiGetRefCount__)(struct VaSpaceApi *); + void (*__vaspaceapiAddAdditionalDependants__)(struct RsClient *, struct VaSpaceApi *, RsResourceRef *); NV_STATUS (*__vaspaceapiControl_Prologue__)(struct VaSpaceApi *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); NV_STATUS (*__vaspaceapiGetRegBaseOffsetAndSize__)(struct VaSpaceApi *, struct OBJGPU *, NvU32 *, NvU32 *); NV_STATUS (*__vaspaceapiInternalControlForward__)(struct VaSpaceApi *, NvU32, void *, NvU32); - void (*__vaspaceapiPreDestruct__)(struct VaSpaceApi *); NV_STATUS (*__vaspaceapiUnmapFrom__)(struct VaSpaceApi *, RS_RES_UNMAP_FROM_PARAMS *); - NV_STATUS (*__vaspaceapiIsDuplicate__)(struct VaSpaceApi *, NvHandle, NvBool *); void (*__vaspaceapiControl_Epilogue__)(struct VaSpaceApi *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); NV_STATUS (*__vaspaceapiControlLookup__)(struct VaSpaceApi *, struct RS_RES_CONTROL_PARAMS_INTERNAL *, const struct NVOC_EXPORTED_METHOD_DEF **); + NvHandle (*__vaspaceapiGetInternalObjectHandle__)(struct VaSpaceApi *); + NV_STATUS (*__vaspaceapiControl__)(struct VaSpaceApi *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); + NV_STATUS (*__vaspaceapiUnmap__)(struct VaSpaceApi *, struct CALL_CONTEXT *, struct RsCpuMapping *); + NV_STATUS (*__vaspaceapiGetMemInterMapParams__)(struct VaSpaceApi *, RMRES_MEM_INTER_MAP_PARAMS *); + NV_STATUS (*__vaspaceapiGetMemoryMappingDescriptor__)(struct VaSpaceApi *, struct MEMORY_DESCRIPTOR **); + NV_STATUS (*__vaspaceapiControlFilter__)(struct VaSpaceApi *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); + NV_STATUS (*__vaspaceapiControlSerialization_Prologue__)(struct VaSpaceApi *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); + void (*__vaspaceapiPreDestruct__)(struct VaSpaceApi *); + NV_STATUS (*__vaspaceapiIsDuplicate__)(struct VaSpaceApi *, NvHandle, NvBool *); + void (*__vaspaceapiControlSerialization_Epilogue__)(struct VaSpaceApi *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); NV_STATUS (*__vaspaceapiMap__)(struct VaSpaceApi *, struct CALL_CONTEXT *, struct RS_CPU_MAP_PARAMS *, struct RsCpuMapping *); NvBool (*__vaspaceapiAccessCallback__)(struct VaSpaceApi *, struct RsClient *, void *, RsAccessRight); struct OBJVASPACE *pVASpace; @@ -134,25 +136,27 @@ #define vaspaceapiCtrlCmdVaspaceReleaseEntries(pVaspaceApi, pReleaseEntriesParams) vaspaceapiCtrlCmdVaspaceReleaseEntries_DISPATCH(pVaspaceApi, pReleaseEntriesParams) #define vaspaceapiCtrlCmdVaspaceCopyServerReservedPdes(pVaspaceApi, pCopyServerReservedPdesParams) vaspaceapiCtrlCmdVaspaceCopyServerReservedPdes_DISPATCH(pVaspaceApi, pCopyServerReservedPdesParams) #define vaspaceapiShareCallback(pGpuResource, pInvokingClient, pParentRef, pSharePolicy) vaspaceapiShareCallback_DISPATCH(pGpuResource, pInvokingClient, pParentRef, pSharePolicy) -#define vaspaceapiControl(pGpuResource, pCallContext, pParams) vaspaceapiControl_DISPATCH(pGpuResource, pCallContext, pParams) -#define vaspaceapiUnmap(pGpuResource, pCallContext, pCpuMapping) vaspaceapiUnmap_DISPATCH(pGpuResource, pCallContext, pCpuMapping) -#define vaspaceapiGetMemInterMapParams(pRmResource, pParams) vaspaceapiGetMemInterMapParams_DISPATCH(pRmResource, pParams) -#define vaspaceapiGetMemoryMappingDescriptor(pRmResource, ppMemDesc) vaspaceapiGetMemoryMappingDescriptor_DISPATCH(pRmResource, ppMemDesc) -#define vaspaceapiGetMapAddrSpace(pGpuResource, pCallContext, mapFlags, pAddrSpace) vaspaceapiGetMapAddrSpace_DISPATCH(pGpuResource, pCallContext, mapFlags, pAddrSpace) -#define vaspaceapiGetInternalObjectHandle(pGpuResource) vaspaceapiGetInternalObjectHandle_DISPATCH(pGpuResource) -#define vaspaceapiControlFilter(pResource, pCallContext, pParams) vaspaceapiControlFilter_DISPATCH(pResource, pCallContext, pParams) -#define vaspaceapiAddAdditionalDependants(pClient, pResource, pReference) vaspaceapiAddAdditionalDependants_DISPATCH(pClient, pResource, pReference) -#define vaspaceapiGetRefCount(pResource) vaspaceapiGetRefCount_DISPATCH(pResource) #define vaspaceapiCheckMemInterUnmap(pRmResource, bSubdeviceHandleProvided) vaspaceapiCheckMemInterUnmap_DISPATCH(pRmResource, bSubdeviceHandleProvided) #define vaspaceapiMapTo(pResource, pParams) vaspaceapiMapTo_DISPATCH(pResource, pParams) +#define vaspaceapiGetMapAddrSpace(pGpuResource, pCallContext, mapFlags, pAddrSpace) vaspaceapiGetMapAddrSpace_DISPATCH(pGpuResource, pCallContext, mapFlags, pAddrSpace) +#define vaspaceapiGetRefCount(pResource) vaspaceapiGetRefCount_DISPATCH(pResource) +#define vaspaceapiAddAdditionalDependants(pClient, pResource, pReference) vaspaceapiAddAdditionalDependants_DISPATCH(pClient, pResource, pReference) #define vaspaceapiControl_Prologue(pResource, pCallContext, pParams) vaspaceapiControl_Prologue_DISPATCH(pResource, pCallContext, pParams) #define vaspaceapiGetRegBaseOffsetAndSize(pGpuResource, pGpu, pOffset, pSize) vaspaceapiGetRegBaseOffsetAndSize_DISPATCH(pGpuResource, pGpu, pOffset, pSize) #define vaspaceapiInternalControlForward(pGpuResource, command, pParams, size) vaspaceapiInternalControlForward_DISPATCH(pGpuResource, command, pParams, size) -#define vaspaceapiPreDestruct(pResource) vaspaceapiPreDestruct_DISPATCH(pResource) #define vaspaceapiUnmapFrom(pResource, pParams) vaspaceapiUnmapFrom_DISPATCH(pResource, pParams) -#define vaspaceapiIsDuplicate(pResource, hMemory, pDuplicate) vaspaceapiIsDuplicate_DISPATCH(pResource, hMemory, pDuplicate) #define vaspaceapiControl_Epilogue(pResource, pCallContext, pParams) vaspaceapiControl_Epilogue_DISPATCH(pResource, pCallContext, pParams) #define vaspaceapiControlLookup(pResource, pParams, ppEntry) vaspaceapiControlLookup_DISPATCH(pResource, pParams, ppEntry) +#define vaspaceapiGetInternalObjectHandle(pGpuResource) vaspaceapiGetInternalObjectHandle_DISPATCH(pGpuResource) +#define vaspaceapiControl(pGpuResource, pCallContext, pParams) vaspaceapiControl_DISPATCH(pGpuResource, pCallContext, pParams) +#define vaspaceapiUnmap(pGpuResource, pCallContext, pCpuMapping) vaspaceapiUnmap_DISPATCH(pGpuResource, pCallContext, pCpuMapping) +#define vaspaceapiGetMemInterMapParams(pRmResource, pParams) vaspaceapiGetMemInterMapParams_DISPATCH(pRmResource, pParams) +#define vaspaceapiGetMemoryMappingDescriptor(pRmResource, ppMemDesc) vaspaceapiGetMemoryMappingDescriptor_DISPATCH(pRmResource, ppMemDesc) +#define vaspaceapiControlFilter(pResource, pCallContext, pParams) vaspaceapiControlFilter_DISPATCH(pResource, pCallContext, pParams) +#define vaspaceapiControlSerialization_Prologue(pResource, pCallContext, pParams) vaspaceapiControlSerialization_Prologue_DISPATCH(pResource, pCallContext, pParams) +#define vaspaceapiPreDestruct(pResource) vaspaceapiPreDestruct_DISPATCH(pResource) +#define vaspaceapiIsDuplicate(pResource, hMemory, pDuplicate) vaspaceapiIsDuplicate_DISPATCH(pResource, hMemory, pDuplicate) +#define vaspaceapiControlSerialization_Epilogue(pResource, pCallContext, pParams) vaspaceapiControlSerialization_Epilogue_DISPATCH(pResource, pCallContext, pParams) #define vaspaceapiMap(pGpuResource, pCallContext, pParams, pCpuMapping) vaspaceapiMap_DISPATCH(pGpuResource, pCallContext, pParams, pCpuMapping) #define vaspaceapiAccessCallback(pResource, pInvokingClient, pAllocParams, accessRight) vaspaceapiAccessCallback_DISPATCH(pResource, pInvokingClient, pAllocParams, accessRight) NvBool vaspaceapiCanCopy_IMPL(struct VaSpaceApi *pResource); @@ -195,48 +199,24 @@ return pGpuResource->__vaspaceapiShareCallback__(pGpuResource, pInvokingClient, pParentRef, pSharePolicy); } -static inline NV_STATUS vaspaceapiControl_DISPATCH(struct VaSpaceApi *pGpuResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { - return pGpuResource->__vaspaceapiControl__(pGpuResource, pCallContext, pParams); -} - -static inline NV_STATUS vaspaceapiUnmap_DISPATCH(struct VaSpaceApi *pGpuResource, struct CALL_CONTEXT *pCallContext, struct RsCpuMapping *pCpuMapping) { - return pGpuResource->__vaspaceapiUnmap__(pGpuResource, pCallContext, pCpuMapping); -} - -static inline NV_STATUS vaspaceapiGetMemInterMapParams_DISPATCH(struct VaSpaceApi *pRmResource, RMRES_MEM_INTER_MAP_PARAMS *pParams) { - return pRmResource->__vaspaceapiGetMemInterMapParams__(pRmResource, pParams); +static inline NV_STATUS vaspaceapiCheckMemInterUnmap_DISPATCH(struct VaSpaceApi *pRmResource, NvBool bSubdeviceHandleProvided) { + return pRmResource->__vaspaceapiCheckMemInterUnmap__(pRmResource, bSubdeviceHandleProvided); } -static inline NV_STATUS vaspaceapiGetMemoryMappingDescriptor_DISPATCH(struct VaSpaceApi *pRmResource, struct MEMORY_DESCRIPTOR **ppMemDesc) { - return pRmResource->__vaspaceapiGetMemoryMappingDescriptor__(pRmResource, ppMemDesc); +static inline NV_STATUS vaspaceapiMapTo_DISPATCH(struct VaSpaceApi *pResource, RS_RES_MAP_TO_PARAMS *pParams) { + return pResource->__vaspaceapiMapTo__(pResource, pParams); } static inline NV_STATUS vaspaceapiGetMapAddrSpace_DISPATCH(struct VaSpaceApi *pGpuResource, struct CALL_CONTEXT *pCallContext, NvU32 mapFlags, NV_ADDRESS_SPACE *pAddrSpace) { return pGpuResource->__vaspaceapiGetMapAddrSpace__(pGpuResource, pCallContext, mapFlags, pAddrSpace); } -static inline NvHandle vaspaceapiGetInternalObjectHandle_DISPATCH(struct VaSpaceApi *pGpuResource) { - return pGpuResource->__vaspaceapiGetInternalObjectHandle__(pGpuResource); -} - -static inline NV_STATUS vaspaceapiControlFilter_DISPATCH(struct VaSpaceApi *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { - return pResource->__vaspaceapiControlFilter__(pResource, pCallContext, pParams); -} - -static inline void vaspaceapiAddAdditionalDependants_DISPATCH(struct RsClient *pClient, struct VaSpaceApi *pResource, RsResourceRef *pReference) { - pResource->__vaspaceapiAddAdditionalDependants__(pClient, pResource, pReference); -} - static inline NvU32 vaspaceapiGetRefCount_DISPATCH(struct VaSpaceApi *pResource) { return pResource->__vaspaceapiGetRefCount__(pResource); } -static inline NV_STATUS vaspaceapiCheckMemInterUnmap_DISPATCH(struct VaSpaceApi *pRmResource, NvBool bSubdeviceHandleProvided) { - return pRmResource->__vaspaceapiCheckMemInterUnmap__(pRmResource, bSubdeviceHandleProvided); -} - -static inline NV_STATUS vaspaceapiMapTo_DISPATCH(struct VaSpaceApi *pResource, RS_RES_MAP_TO_PARAMS *pParams) { - return pResource->__vaspaceapiMapTo__(pResource, pParams); +static inline void vaspaceapiAddAdditionalDependants_DISPATCH(struct RsClient *pClient, struct VaSpaceApi *pResource, RsResourceRef *pReference) { + pResource->__vaspaceapiAddAdditionalDependants__(pClient, pResource, pReference); } static inline NV_STATUS vaspaceapiControl_Prologue_DISPATCH(struct VaSpaceApi *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { @@ -251,18 +231,10 @@ return pGpuResource->__vaspaceapiInternalControlForward__(pGpuResource, command, pParams, size); } -static inline void vaspaceapiPreDestruct_DISPATCH(struct VaSpaceApi *pResource) { - pResource->__vaspaceapiPreDestruct__(pResource); -} - static inline NV_STATUS vaspaceapiUnmapFrom_DISPATCH(struct VaSpaceApi *pResource, RS_RES_UNMAP_FROM_PARAMS *pParams) { return pResource->__vaspaceapiUnmapFrom__(pResource, pParams); } -static inline NV_STATUS vaspaceapiIsDuplicate_DISPATCH(struct VaSpaceApi *pResource, NvHandle hMemory, NvBool *pDuplicate) { - return pResource->__vaspaceapiIsDuplicate__(pResource, hMemory, pDuplicate); -} - static inline void vaspaceapiControl_Epilogue_DISPATCH(struct VaSpaceApi *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { pResource->__vaspaceapiControl_Epilogue__(pResource, pCallContext, pParams); } @@ -271,6 +243,46 @@ return pResource->__vaspaceapiControlLookup__(pResource, pParams, ppEntry); } +static inline NvHandle vaspaceapiGetInternalObjectHandle_DISPATCH(struct VaSpaceApi *pGpuResource) { + return pGpuResource->__vaspaceapiGetInternalObjectHandle__(pGpuResource); +} + +static inline NV_STATUS vaspaceapiControl_DISPATCH(struct VaSpaceApi *pGpuResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return pGpuResource->__vaspaceapiControl__(pGpuResource, pCallContext, pParams); +} + +static inline NV_STATUS vaspaceapiUnmap_DISPATCH(struct VaSpaceApi *pGpuResource, struct CALL_CONTEXT *pCallContext, struct RsCpuMapping *pCpuMapping) { + return pGpuResource->__vaspaceapiUnmap__(pGpuResource, pCallContext, pCpuMapping); +} + +static inline NV_STATUS vaspaceapiGetMemInterMapParams_DISPATCH(struct VaSpaceApi *pRmResource, RMRES_MEM_INTER_MAP_PARAMS *pParams) { + return pRmResource->__vaspaceapiGetMemInterMapParams__(pRmResource, pParams); +} + +static inline NV_STATUS vaspaceapiGetMemoryMappingDescriptor_DISPATCH(struct VaSpaceApi *pRmResource, struct MEMORY_DESCRIPTOR **ppMemDesc) { + return pRmResource->__vaspaceapiGetMemoryMappingDescriptor__(pRmResource, ppMemDesc); +} + +static inline NV_STATUS vaspaceapiControlFilter_DISPATCH(struct VaSpaceApi *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return pResource->__vaspaceapiControlFilter__(pResource, pCallContext, pParams); +} + +static inline NV_STATUS vaspaceapiControlSerialization_Prologue_DISPATCH(struct VaSpaceApi *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return pResource->__vaspaceapiControlSerialization_Prologue__(pResource, pCallContext, pParams); +} + +static inline void vaspaceapiPreDestruct_DISPATCH(struct VaSpaceApi *pResource) { + pResource->__vaspaceapiPreDestruct__(pResource); +} + +static inline NV_STATUS vaspaceapiIsDuplicate_DISPATCH(struct VaSpaceApi *pResource, NvHandle hMemory, NvBool *pDuplicate) { + return pResource->__vaspaceapiIsDuplicate__(pResource, hMemory, pDuplicate); +} + +static inline void vaspaceapiControlSerialization_Epilogue_DISPATCH(struct VaSpaceApi *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + pResource->__vaspaceapiControlSerialization_Epilogue__(pResource, pCallContext, pParams); +} + static inline NV_STATUS vaspaceapiMap_DISPATCH(struct VaSpaceApi *pGpuResource, struct CALL_CONTEXT *pCallContext, struct RS_CPU_MAP_PARAMS *pParams, struct RsCpuMapping *pCpuMapping) { return pGpuResource->__vaspaceapiMap__(pGpuResource, pCallContext, pParams, pCpuMapping); } diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/generated/g_vaspace_nvoc.h nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_vaspace_nvoc.h --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/generated/g_vaspace_nvoc.h 2023-10-25 20:27:22.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_vaspace_nvoc.h 2024-03-05 22:18:50.000000000 +0000 @@ -255,8 +255,8 @@ void (*__vaspaceUnmap__)(struct OBJVASPACE *, struct OBJGPU *, const NvU64, const NvU64); NV_STATUS (*__vaspaceReserveMempool__)(struct OBJVASPACE *, struct OBJGPU *, NvHandle, NvU64, NvU64, NvU32); struct OBJEHEAP *(*__vaspaceGetHeap__)(struct OBJVASPACE *); - NvU32 (*__vaspaceGetMapPageSize__)(struct OBJVASPACE *, struct OBJGPU *, EMEMBLOCK *); - NvU32 (*__vaspaceGetBigPageSize__)(struct OBJVASPACE *); + NvU64 (*__vaspaceGetMapPageSize__)(struct OBJVASPACE *, struct OBJGPU *, EMEMBLOCK *); + NvU64 (*__vaspaceGetBigPageSize__)(struct OBJVASPACE *); NvBool (*__vaspaceIsMirrored__)(struct OBJVASPACE *); NvBool (*__vaspaceIsFaultCapable__)(struct OBJVASPACE *); NvBool (*__vaspaceIsExternallyOwned__)(struct OBJVASPACE *); @@ -426,21 +426,21 @@ return pVAS->__vaspaceGetHeap__(pVAS); } -static inline NvU32 vaspaceGetMapPageSize_07238a(struct OBJVASPACE *pVAS, struct OBJGPU *pGpu, EMEMBLOCK *pMemBlock) { +static inline NvU64 vaspaceGetMapPageSize_07238a(struct OBJVASPACE *pVAS, struct OBJGPU *pGpu, EMEMBLOCK *pMemBlock) { NV_ASSERT_PRECOMP(((NvBool)(0 != 0))); return 0U; } -static inline NvU32 vaspaceGetMapPageSize_DISPATCH(struct OBJVASPACE *pVAS, struct OBJGPU *pGpu, EMEMBLOCK *pMemBlock) { +static inline NvU64 vaspaceGetMapPageSize_DISPATCH(struct OBJVASPACE *pVAS, struct OBJGPU *pGpu, EMEMBLOCK *pMemBlock) { return pVAS->__vaspaceGetMapPageSize__(pVAS, pGpu, pMemBlock); } -static inline NvU32 vaspaceGetBigPageSize_07238a(struct OBJVASPACE *pVAS) { +static inline NvU64 vaspaceGetBigPageSize_07238a(struct OBJVASPACE *pVAS) { NV_ASSERT_PRECOMP(((NvBool)(0 != 0))); return 0U; } -static inline NvU32 vaspaceGetBigPageSize_DISPATCH(struct OBJVASPACE *pVAS) { +static inline NvU64 vaspaceGetBigPageSize_DISPATCH(struct OBJVASPACE *pVAS) { return pVAS->__vaspaceGetBigPageSize__(pVAS); } diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/generated/g_vblank_callback_nvoc.c nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_vblank_callback_nvoc.c --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/generated/g_vblank_callback_nvoc.c 2023-10-25 20:27:23.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_vblank_callback_nvoc.c 2024-03-05 22:18:50.000000000 +0000 @@ -97,84 +97,92 @@ return gpuresShareCallback((struct GpuResource *)(((unsigned char *)pGpuResource) + __nvoc_rtti_VblankCallback_GpuResource.offset), pInvokingClient, pParentRef, pSharePolicy); } -static NV_STATUS __nvoc_thunk_GpuResource_vblcbControl(struct VblankCallback *pGpuResource, CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { - return gpuresControl((struct GpuResource *)(((unsigned char *)pGpuResource) + __nvoc_rtti_VblankCallback_GpuResource.offset), pCallContext, pParams); +static NV_STATUS __nvoc_thunk_RmResource_vblcbCheckMemInterUnmap(struct VblankCallback *pRmResource, NvBool bSubdeviceHandleProvided) { + return rmresCheckMemInterUnmap((struct RmResource *)(((unsigned char *)pRmResource) + __nvoc_rtti_VblankCallback_RmResource.offset), bSubdeviceHandleProvided); } -static NV_STATUS __nvoc_thunk_GpuResource_vblcbUnmap(struct VblankCallback *pGpuResource, CALL_CONTEXT *pCallContext, RsCpuMapping *pCpuMapping) { - return gpuresUnmap((struct GpuResource *)(((unsigned char *)pGpuResource) + __nvoc_rtti_VblankCallback_GpuResource.offset), pCallContext, pCpuMapping); +static NV_STATUS __nvoc_thunk_RsResource_vblcbMapTo(struct VblankCallback *pResource, RS_RES_MAP_TO_PARAMS *pParams) { + return resMapTo((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_VblankCallback_RsResource.offset), pParams); } -static NV_STATUS __nvoc_thunk_RmResource_vblcbGetMemInterMapParams(struct VblankCallback *pRmResource, RMRES_MEM_INTER_MAP_PARAMS *pParams) { - return rmresGetMemInterMapParams((struct RmResource *)(((unsigned char *)pRmResource) + __nvoc_rtti_VblankCallback_RmResource.offset), pParams); +static NV_STATUS __nvoc_thunk_GpuResource_vblcbGetMapAddrSpace(struct VblankCallback *pGpuResource, CALL_CONTEXT *pCallContext, NvU32 mapFlags, NV_ADDRESS_SPACE *pAddrSpace) { + return gpuresGetMapAddrSpace((struct GpuResource *)(((unsigned char *)pGpuResource) + __nvoc_rtti_VblankCallback_GpuResource.offset), pCallContext, mapFlags, pAddrSpace); } -static NV_STATUS __nvoc_thunk_RmResource_vblcbGetMemoryMappingDescriptor(struct VblankCallback *pRmResource, struct MEMORY_DESCRIPTOR **ppMemDesc) { - return rmresGetMemoryMappingDescriptor((struct RmResource *)(((unsigned char *)pRmResource) + __nvoc_rtti_VblankCallback_RmResource.offset), ppMemDesc); +static NvU32 __nvoc_thunk_RsResource_vblcbGetRefCount(struct VblankCallback *pResource) { + return resGetRefCount((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_VblankCallback_RsResource.offset)); } -static NV_STATUS __nvoc_thunk_GpuResource_vblcbGetMapAddrSpace(struct VblankCallback *pGpuResource, CALL_CONTEXT *pCallContext, NvU32 mapFlags, NV_ADDRESS_SPACE *pAddrSpace) { - return gpuresGetMapAddrSpace((struct GpuResource *)(((unsigned char *)pGpuResource) + __nvoc_rtti_VblankCallback_GpuResource.offset), pCallContext, mapFlags, pAddrSpace); +static void __nvoc_thunk_RsResource_vblcbAddAdditionalDependants(struct RsClient *pClient, struct VblankCallback *pResource, RsResourceRef *pReference) { + resAddAdditionalDependants(pClient, (struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_VblankCallback_RsResource.offset), pReference); } -static NvHandle __nvoc_thunk_GpuResource_vblcbGetInternalObjectHandle(struct VblankCallback *pGpuResource) { - return gpuresGetInternalObjectHandle((struct GpuResource *)(((unsigned char *)pGpuResource) + __nvoc_rtti_VblankCallback_GpuResource.offset)); +static NV_STATUS __nvoc_thunk_RmResource_vblcbControl_Prologue(struct VblankCallback *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return rmresControl_Prologue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_VblankCallback_RmResource.offset), pCallContext, pParams); } -static NV_STATUS __nvoc_thunk_RsResource_vblcbControlFilter(struct VblankCallback *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { - return resControlFilter((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_VblankCallback_RsResource.offset), pCallContext, pParams); +static NV_STATUS __nvoc_thunk_GpuResource_vblcbGetRegBaseOffsetAndSize(struct VblankCallback *pGpuResource, struct OBJGPU *pGpu, NvU32 *pOffset, NvU32 *pSize) { + return gpuresGetRegBaseOffsetAndSize((struct GpuResource *)(((unsigned char *)pGpuResource) + __nvoc_rtti_VblankCallback_GpuResource.offset), pGpu, pOffset, pSize); } -static void __nvoc_thunk_RsResource_vblcbAddAdditionalDependants(struct RsClient *pClient, struct VblankCallback *pResource, RsResourceRef *pReference) { - resAddAdditionalDependants(pClient, (struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_VblankCallback_RsResource.offset), pReference); +static NV_STATUS __nvoc_thunk_GpuResource_vblcbInternalControlForward(struct VblankCallback *pGpuResource, NvU32 command, void *pParams, NvU32 size) { + return gpuresInternalControlForward((struct GpuResource *)(((unsigned char *)pGpuResource) + __nvoc_rtti_VblankCallback_GpuResource.offset), command, pParams, size); } -static NvU32 __nvoc_thunk_RsResource_vblcbGetRefCount(struct VblankCallback *pResource) { - return resGetRefCount((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_VblankCallback_RsResource.offset)); +static NV_STATUS __nvoc_thunk_RsResource_vblcbUnmapFrom(struct VblankCallback *pResource, RS_RES_UNMAP_FROM_PARAMS *pParams) { + return resUnmapFrom((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_VblankCallback_RsResource.offset), pParams); } -static NV_STATUS __nvoc_thunk_RmResource_vblcbCheckMemInterUnmap(struct VblankCallback *pRmResource, NvBool bSubdeviceHandleProvided) { - return rmresCheckMemInterUnmap((struct RmResource *)(((unsigned char *)pRmResource) + __nvoc_rtti_VblankCallback_RmResource.offset), bSubdeviceHandleProvided); +static void __nvoc_thunk_RmResource_vblcbControl_Epilogue(struct VblankCallback *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + rmresControl_Epilogue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_VblankCallback_RmResource.offset), pCallContext, pParams); } -static NV_STATUS __nvoc_thunk_RsResource_vblcbMapTo(struct VblankCallback *pResource, RS_RES_MAP_TO_PARAMS *pParams) { - return resMapTo((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_VblankCallback_RsResource.offset), pParams); +static NV_STATUS __nvoc_thunk_RsResource_vblcbControlLookup(struct VblankCallback *pResource, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams, const struct NVOC_EXPORTED_METHOD_DEF **ppEntry) { + return resControlLookup((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_VblankCallback_RsResource.offset), pParams, ppEntry); } -static NV_STATUS __nvoc_thunk_RmResource_vblcbControl_Prologue(struct VblankCallback *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { - return rmresControl_Prologue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_VblankCallback_RmResource.offset), pCallContext, pParams); +static NvHandle __nvoc_thunk_GpuResource_vblcbGetInternalObjectHandle(struct VblankCallback *pGpuResource) { + return gpuresGetInternalObjectHandle((struct GpuResource *)(((unsigned char *)pGpuResource) + __nvoc_rtti_VblankCallback_GpuResource.offset)); } -static NV_STATUS __nvoc_thunk_GpuResource_vblcbGetRegBaseOffsetAndSize(struct VblankCallback *pGpuResource, struct OBJGPU *pGpu, NvU32 *pOffset, NvU32 *pSize) { - return gpuresGetRegBaseOffsetAndSize((struct GpuResource *)(((unsigned char *)pGpuResource) + __nvoc_rtti_VblankCallback_GpuResource.offset), pGpu, pOffset, pSize); +static NV_STATUS __nvoc_thunk_GpuResource_vblcbControl(struct VblankCallback *pGpuResource, CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return gpuresControl((struct GpuResource *)(((unsigned char *)pGpuResource) + __nvoc_rtti_VblankCallback_GpuResource.offset), pCallContext, pParams); } -static NvBool __nvoc_thunk_RsResource_vblcbCanCopy(struct VblankCallback *pResource) { - return resCanCopy((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_VblankCallback_RsResource.offset)); +static NV_STATUS __nvoc_thunk_GpuResource_vblcbUnmap(struct VblankCallback *pGpuResource, CALL_CONTEXT *pCallContext, RsCpuMapping *pCpuMapping) { + return gpuresUnmap((struct GpuResource *)(((unsigned char *)pGpuResource) + __nvoc_rtti_VblankCallback_GpuResource.offset), pCallContext, pCpuMapping); } -static NV_STATUS __nvoc_thunk_GpuResource_vblcbInternalControlForward(struct VblankCallback *pGpuResource, NvU32 command, void *pParams, NvU32 size) { - return gpuresInternalControlForward((struct GpuResource *)(((unsigned char *)pGpuResource) + __nvoc_rtti_VblankCallback_GpuResource.offset), command, pParams, size); +static NV_STATUS __nvoc_thunk_RmResource_vblcbGetMemInterMapParams(struct VblankCallback *pRmResource, RMRES_MEM_INTER_MAP_PARAMS *pParams) { + return rmresGetMemInterMapParams((struct RmResource *)(((unsigned char *)pRmResource) + __nvoc_rtti_VblankCallback_RmResource.offset), pParams); } -static void __nvoc_thunk_RsResource_vblcbPreDestruct(struct VblankCallback *pResource) { - resPreDestruct((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_VblankCallback_RsResource.offset)); +static NV_STATUS __nvoc_thunk_RmResource_vblcbGetMemoryMappingDescriptor(struct VblankCallback *pRmResource, struct MEMORY_DESCRIPTOR **ppMemDesc) { + return rmresGetMemoryMappingDescriptor((struct RmResource *)(((unsigned char *)pRmResource) + __nvoc_rtti_VblankCallback_RmResource.offset), ppMemDesc); } -static NV_STATUS __nvoc_thunk_RsResource_vblcbUnmapFrom(struct VblankCallback *pResource, RS_RES_UNMAP_FROM_PARAMS *pParams) { - return resUnmapFrom((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_VblankCallback_RsResource.offset), pParams); +static NV_STATUS __nvoc_thunk_RsResource_vblcbControlFilter(struct VblankCallback *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return resControlFilter((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_VblankCallback_RsResource.offset), pCallContext, pParams); } -static NV_STATUS __nvoc_thunk_RsResource_vblcbIsDuplicate(struct VblankCallback *pResource, NvHandle hMemory, NvBool *pDuplicate) { - return resIsDuplicate((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_VblankCallback_RsResource.offset), hMemory, pDuplicate); +static NV_STATUS __nvoc_thunk_RmResource_vblcbControlSerialization_Prologue(struct VblankCallback *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return rmresControlSerialization_Prologue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_VblankCallback_RmResource.offset), pCallContext, pParams); } -static void __nvoc_thunk_RmResource_vblcbControl_Epilogue(struct VblankCallback *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { - rmresControl_Epilogue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_VblankCallback_RmResource.offset), pCallContext, pParams); +static NvBool __nvoc_thunk_RsResource_vblcbCanCopy(struct VblankCallback *pResource) { + return resCanCopy((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_VblankCallback_RsResource.offset)); } -static NV_STATUS __nvoc_thunk_RsResource_vblcbControlLookup(struct VblankCallback *pResource, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams, const struct NVOC_EXPORTED_METHOD_DEF **ppEntry) { - return resControlLookup((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_VblankCallback_RsResource.offset), pParams, ppEntry); +static void __nvoc_thunk_RsResource_vblcbPreDestruct(struct VblankCallback *pResource) { + resPreDestruct((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_VblankCallback_RsResource.offset)); +} + +static NV_STATUS __nvoc_thunk_RsResource_vblcbIsDuplicate(struct VblankCallback *pResource, NvHandle hMemory, NvBool *pDuplicate) { + return resIsDuplicate((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_VblankCallback_RsResource.offset), hMemory, pDuplicate); +} + +static void __nvoc_thunk_RmResource_vblcbControlSerialization_Epilogue(struct VblankCallback *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + rmresControlSerialization_Epilogue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_VblankCallback_RmResource.offset), pCallContext, pParams); } static NV_STATUS __nvoc_thunk_GpuResource_vblcbMap(struct VblankCallback *pGpuResource, CALL_CONTEXT *pCallContext, struct RS_CPU_MAP_PARAMS *pParams, RsCpuMapping *pCpuMapping) { @@ -254,45 +262,49 @@ pThis->__vblcbShareCallback__ = &__nvoc_thunk_GpuResource_vblcbShareCallback; - pThis->__vblcbControl__ = &__nvoc_thunk_GpuResource_vblcbControl; + pThis->__vblcbCheckMemInterUnmap__ = &__nvoc_thunk_RmResource_vblcbCheckMemInterUnmap; - pThis->__vblcbUnmap__ = &__nvoc_thunk_GpuResource_vblcbUnmap; + pThis->__vblcbMapTo__ = &__nvoc_thunk_RsResource_vblcbMapTo; - pThis->__vblcbGetMemInterMapParams__ = &__nvoc_thunk_RmResource_vblcbGetMemInterMapParams; + pThis->__vblcbGetMapAddrSpace__ = &__nvoc_thunk_GpuResource_vblcbGetMapAddrSpace; - pThis->__vblcbGetMemoryMappingDescriptor__ = &__nvoc_thunk_RmResource_vblcbGetMemoryMappingDescriptor; + pThis->__vblcbGetRefCount__ = &__nvoc_thunk_RsResource_vblcbGetRefCount; - pThis->__vblcbGetMapAddrSpace__ = &__nvoc_thunk_GpuResource_vblcbGetMapAddrSpace; + pThis->__vblcbAddAdditionalDependants__ = &__nvoc_thunk_RsResource_vblcbAddAdditionalDependants; - pThis->__vblcbGetInternalObjectHandle__ = &__nvoc_thunk_GpuResource_vblcbGetInternalObjectHandle; + pThis->__vblcbControl_Prologue__ = &__nvoc_thunk_RmResource_vblcbControl_Prologue; - pThis->__vblcbControlFilter__ = &__nvoc_thunk_RsResource_vblcbControlFilter; + pThis->__vblcbGetRegBaseOffsetAndSize__ = &__nvoc_thunk_GpuResource_vblcbGetRegBaseOffsetAndSize; - pThis->__vblcbAddAdditionalDependants__ = &__nvoc_thunk_RsResource_vblcbAddAdditionalDependants; + pThis->__vblcbInternalControlForward__ = &__nvoc_thunk_GpuResource_vblcbInternalControlForward; - pThis->__vblcbGetRefCount__ = &__nvoc_thunk_RsResource_vblcbGetRefCount; + pThis->__vblcbUnmapFrom__ = &__nvoc_thunk_RsResource_vblcbUnmapFrom; - pThis->__vblcbCheckMemInterUnmap__ = &__nvoc_thunk_RmResource_vblcbCheckMemInterUnmap; + pThis->__vblcbControl_Epilogue__ = &__nvoc_thunk_RmResource_vblcbControl_Epilogue; - pThis->__vblcbMapTo__ = &__nvoc_thunk_RsResource_vblcbMapTo; + pThis->__vblcbControlLookup__ = &__nvoc_thunk_RsResource_vblcbControlLookup; - pThis->__vblcbControl_Prologue__ = &__nvoc_thunk_RmResource_vblcbControl_Prologue; + pThis->__vblcbGetInternalObjectHandle__ = &__nvoc_thunk_GpuResource_vblcbGetInternalObjectHandle; - pThis->__vblcbGetRegBaseOffsetAndSize__ = &__nvoc_thunk_GpuResource_vblcbGetRegBaseOffsetAndSize; + pThis->__vblcbControl__ = &__nvoc_thunk_GpuResource_vblcbControl; - pThis->__vblcbCanCopy__ = &__nvoc_thunk_RsResource_vblcbCanCopy; + pThis->__vblcbUnmap__ = &__nvoc_thunk_GpuResource_vblcbUnmap; - pThis->__vblcbInternalControlForward__ = &__nvoc_thunk_GpuResource_vblcbInternalControlForward; + pThis->__vblcbGetMemInterMapParams__ = &__nvoc_thunk_RmResource_vblcbGetMemInterMapParams; - pThis->__vblcbPreDestruct__ = &__nvoc_thunk_RsResource_vblcbPreDestruct; + pThis->__vblcbGetMemoryMappingDescriptor__ = &__nvoc_thunk_RmResource_vblcbGetMemoryMappingDescriptor; - pThis->__vblcbUnmapFrom__ = &__nvoc_thunk_RsResource_vblcbUnmapFrom; + pThis->__vblcbControlFilter__ = &__nvoc_thunk_RsResource_vblcbControlFilter; - pThis->__vblcbIsDuplicate__ = &__nvoc_thunk_RsResource_vblcbIsDuplicate; + pThis->__vblcbControlSerialization_Prologue__ = &__nvoc_thunk_RmResource_vblcbControlSerialization_Prologue; - pThis->__vblcbControl_Epilogue__ = &__nvoc_thunk_RmResource_vblcbControl_Epilogue; + pThis->__vblcbCanCopy__ = &__nvoc_thunk_RsResource_vblcbCanCopy; - pThis->__vblcbControlLookup__ = &__nvoc_thunk_RsResource_vblcbControlLookup; + pThis->__vblcbPreDestruct__ = &__nvoc_thunk_RsResource_vblcbPreDestruct; + + pThis->__vblcbIsDuplicate__ = &__nvoc_thunk_RsResource_vblcbIsDuplicate; + + pThis->__vblcbControlSerialization_Epilogue__ = &__nvoc_thunk_RmResource_vblcbControlSerialization_Epilogue; pThis->__vblcbMap__ = &__nvoc_thunk_GpuResource_vblcbMap; @@ -320,13 +332,16 @@ Object *pParentObj; VblankCallback *pThis; - pThis = portMemAllocNonPaged(sizeof(VblankCallback)); - if (pThis == NULL) return NV_ERR_NO_MEMORY; + status = __nvoc_handleObjCreateMemAlloc(createFlags, sizeof(VblankCallback), (void**)&pThis, (void**)ppThis); + if (status != NV_OK) + return status; portMemSet(pThis, 0, sizeof(VblankCallback)); __nvoc_initRtti(staticCast(pThis, Dynamic), &__nvoc_class_def_VblankCallback); + pThis->__nvoc_base_GpuResource.__nvoc_base_RmResource.__nvoc_base_RsResource.__nvoc_base_Object.createFlags = createFlags; + if (pParent != NULL && !(createFlags & NVOC_OBJ_CREATE_FLAGS_PARENT_HALSPEC_ONLY)) { pParentObj = dynamicCast(pParent, Object); @@ -342,11 +357,17 @@ if (status != NV_OK) goto __nvoc_objCreate_VblankCallback_cleanup; *ppThis = pThis; + return NV_OK; __nvoc_objCreate_VblankCallback_cleanup: // do not call destructors here since the constructor already called them - portMemFree(pThis); + if (createFlags & NVOC_OBJ_CREATE_FLAGS_IN_PLACE_CONSTRUCT) + portMemSet(pThis, 0, sizeof(VblankCallback)); + else + portMemFree(pThis); + + // coverity[leaked_storage:FALSE] return status; } diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/generated/g_vblank_callback_nvoc.h nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_vblank_callback_nvoc.h --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/generated/g_vblank_callback_nvoc.h 2023-10-25 20:27:23.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_vblank_callback_nvoc.h 2024-03-05 22:18:51.000000000 +0000 @@ -64,26 +64,28 @@ struct VblankCallback *__nvoc_pbase_VblankCallback; NV_STATUS (*__vblcbCtrlSetVBlankNotification__)(struct VblankCallback *, NV9010_CTRL_CMD_SET_VBLANK_NOTIFICATION_PARAMS *); NvBool (*__vblcbShareCallback__)(struct VblankCallback *, struct RsClient *, struct RsResourceRef *, RS_SHARE_POLICY *); - NV_STATUS (*__vblcbControl__)(struct VblankCallback *, CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); - NV_STATUS (*__vblcbUnmap__)(struct VblankCallback *, CALL_CONTEXT *, RsCpuMapping *); - NV_STATUS (*__vblcbGetMemInterMapParams__)(struct VblankCallback *, RMRES_MEM_INTER_MAP_PARAMS *); - NV_STATUS (*__vblcbGetMemoryMappingDescriptor__)(struct VblankCallback *, struct MEMORY_DESCRIPTOR **); - NV_STATUS (*__vblcbGetMapAddrSpace__)(struct VblankCallback *, CALL_CONTEXT *, NvU32, NV_ADDRESS_SPACE *); - NvHandle (*__vblcbGetInternalObjectHandle__)(struct VblankCallback *); - NV_STATUS (*__vblcbControlFilter__)(struct VblankCallback *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); - void (*__vblcbAddAdditionalDependants__)(struct RsClient *, struct VblankCallback *, RsResourceRef *); - NvU32 (*__vblcbGetRefCount__)(struct VblankCallback *); NV_STATUS (*__vblcbCheckMemInterUnmap__)(struct VblankCallback *, NvBool); NV_STATUS (*__vblcbMapTo__)(struct VblankCallback *, RS_RES_MAP_TO_PARAMS *); + NV_STATUS (*__vblcbGetMapAddrSpace__)(struct VblankCallback *, CALL_CONTEXT *, NvU32, NV_ADDRESS_SPACE *); + NvU32 (*__vblcbGetRefCount__)(struct VblankCallback *); + void (*__vblcbAddAdditionalDependants__)(struct RsClient *, struct VblankCallback *, RsResourceRef *); NV_STATUS (*__vblcbControl_Prologue__)(struct VblankCallback *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); NV_STATUS (*__vblcbGetRegBaseOffsetAndSize__)(struct VblankCallback *, struct OBJGPU *, NvU32 *, NvU32 *); - NvBool (*__vblcbCanCopy__)(struct VblankCallback *); NV_STATUS (*__vblcbInternalControlForward__)(struct VblankCallback *, NvU32, void *, NvU32); - void (*__vblcbPreDestruct__)(struct VblankCallback *); NV_STATUS (*__vblcbUnmapFrom__)(struct VblankCallback *, RS_RES_UNMAP_FROM_PARAMS *); - NV_STATUS (*__vblcbIsDuplicate__)(struct VblankCallback *, NvHandle, NvBool *); void (*__vblcbControl_Epilogue__)(struct VblankCallback *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); NV_STATUS (*__vblcbControlLookup__)(struct VblankCallback *, struct RS_RES_CONTROL_PARAMS_INTERNAL *, const struct NVOC_EXPORTED_METHOD_DEF **); + NvHandle (*__vblcbGetInternalObjectHandle__)(struct VblankCallback *); + NV_STATUS (*__vblcbControl__)(struct VblankCallback *, CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); + NV_STATUS (*__vblcbUnmap__)(struct VblankCallback *, CALL_CONTEXT *, RsCpuMapping *); + NV_STATUS (*__vblcbGetMemInterMapParams__)(struct VblankCallback *, RMRES_MEM_INTER_MAP_PARAMS *); + NV_STATUS (*__vblcbGetMemoryMappingDescriptor__)(struct VblankCallback *, struct MEMORY_DESCRIPTOR **); + NV_STATUS (*__vblcbControlFilter__)(struct VblankCallback *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); + NV_STATUS (*__vblcbControlSerialization_Prologue__)(struct VblankCallback *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); + NvBool (*__vblcbCanCopy__)(struct VblankCallback *); + void (*__vblcbPreDestruct__)(struct VblankCallback *); + NV_STATUS (*__vblcbIsDuplicate__)(struct VblankCallback *, NvHandle, NvBool *); + void (*__vblcbControlSerialization_Epilogue__)(struct VblankCallback *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); NV_STATUS (*__vblcbMap__)(struct VblankCallback *, CALL_CONTEXT *, struct RS_CPU_MAP_PARAMS *, RsCpuMapping *); NvBool (*__vblcbAccessCallback__)(struct VblankCallback *, struct RsClient *, void *, RsAccessRight); VBLANKCALLBACK CallBack; @@ -123,26 +125,28 @@ #define vblcbCtrlSetVBlankNotification(pVblankCallback, pParams) vblcbCtrlSetVBlankNotification_DISPATCH(pVblankCallback, pParams) #define vblcbShareCallback(pGpuResource, pInvokingClient, pParentRef, pSharePolicy) vblcbShareCallback_DISPATCH(pGpuResource, pInvokingClient, pParentRef, pSharePolicy) -#define vblcbControl(pGpuResource, pCallContext, pParams) vblcbControl_DISPATCH(pGpuResource, pCallContext, pParams) -#define vblcbUnmap(pGpuResource, pCallContext, pCpuMapping) vblcbUnmap_DISPATCH(pGpuResource, pCallContext, pCpuMapping) -#define vblcbGetMemInterMapParams(pRmResource, pParams) vblcbGetMemInterMapParams_DISPATCH(pRmResource, pParams) -#define vblcbGetMemoryMappingDescriptor(pRmResource, ppMemDesc) vblcbGetMemoryMappingDescriptor_DISPATCH(pRmResource, ppMemDesc) -#define vblcbGetMapAddrSpace(pGpuResource, pCallContext, mapFlags, pAddrSpace) vblcbGetMapAddrSpace_DISPATCH(pGpuResource, pCallContext, mapFlags, pAddrSpace) -#define vblcbGetInternalObjectHandle(pGpuResource) vblcbGetInternalObjectHandle_DISPATCH(pGpuResource) -#define vblcbControlFilter(pResource, pCallContext, pParams) vblcbControlFilter_DISPATCH(pResource, pCallContext, pParams) -#define vblcbAddAdditionalDependants(pClient, pResource, pReference) vblcbAddAdditionalDependants_DISPATCH(pClient, pResource, pReference) -#define vblcbGetRefCount(pResource) vblcbGetRefCount_DISPATCH(pResource) #define vblcbCheckMemInterUnmap(pRmResource, bSubdeviceHandleProvided) vblcbCheckMemInterUnmap_DISPATCH(pRmResource, bSubdeviceHandleProvided) #define vblcbMapTo(pResource, pParams) vblcbMapTo_DISPATCH(pResource, pParams) +#define vblcbGetMapAddrSpace(pGpuResource, pCallContext, mapFlags, pAddrSpace) vblcbGetMapAddrSpace_DISPATCH(pGpuResource, pCallContext, mapFlags, pAddrSpace) +#define vblcbGetRefCount(pResource) vblcbGetRefCount_DISPATCH(pResource) +#define vblcbAddAdditionalDependants(pClient, pResource, pReference) vblcbAddAdditionalDependants_DISPATCH(pClient, pResource, pReference) #define vblcbControl_Prologue(pResource, pCallContext, pParams) vblcbControl_Prologue_DISPATCH(pResource, pCallContext, pParams) #define vblcbGetRegBaseOffsetAndSize(pGpuResource, pGpu, pOffset, pSize) vblcbGetRegBaseOffsetAndSize_DISPATCH(pGpuResource, pGpu, pOffset, pSize) -#define vblcbCanCopy(pResource) vblcbCanCopy_DISPATCH(pResource) #define vblcbInternalControlForward(pGpuResource, command, pParams, size) vblcbInternalControlForward_DISPATCH(pGpuResource, command, pParams, size) -#define vblcbPreDestruct(pResource) vblcbPreDestruct_DISPATCH(pResource) #define vblcbUnmapFrom(pResource, pParams) vblcbUnmapFrom_DISPATCH(pResource, pParams) -#define vblcbIsDuplicate(pResource, hMemory, pDuplicate) vblcbIsDuplicate_DISPATCH(pResource, hMemory, pDuplicate) #define vblcbControl_Epilogue(pResource, pCallContext, pParams) vblcbControl_Epilogue_DISPATCH(pResource, pCallContext, pParams) #define vblcbControlLookup(pResource, pParams, ppEntry) vblcbControlLookup_DISPATCH(pResource, pParams, ppEntry) +#define vblcbGetInternalObjectHandle(pGpuResource) vblcbGetInternalObjectHandle_DISPATCH(pGpuResource) +#define vblcbControl(pGpuResource, pCallContext, pParams) vblcbControl_DISPATCH(pGpuResource, pCallContext, pParams) +#define vblcbUnmap(pGpuResource, pCallContext, pCpuMapping) vblcbUnmap_DISPATCH(pGpuResource, pCallContext, pCpuMapping) +#define vblcbGetMemInterMapParams(pRmResource, pParams) vblcbGetMemInterMapParams_DISPATCH(pRmResource, pParams) +#define vblcbGetMemoryMappingDescriptor(pRmResource, ppMemDesc) vblcbGetMemoryMappingDescriptor_DISPATCH(pRmResource, ppMemDesc) +#define vblcbControlFilter(pResource, pCallContext, pParams) vblcbControlFilter_DISPATCH(pResource, pCallContext, pParams) +#define vblcbControlSerialization_Prologue(pResource, pCallContext, pParams) vblcbControlSerialization_Prologue_DISPATCH(pResource, pCallContext, pParams) +#define vblcbCanCopy(pResource) vblcbCanCopy_DISPATCH(pResource) +#define vblcbPreDestruct(pResource) vblcbPreDestruct_DISPATCH(pResource) +#define vblcbIsDuplicate(pResource, hMemory, pDuplicate) vblcbIsDuplicate_DISPATCH(pResource, hMemory, pDuplicate) +#define vblcbControlSerialization_Epilogue(pResource, pCallContext, pParams) vblcbControlSerialization_Epilogue_DISPATCH(pResource, pCallContext, pParams) #define vblcbMap(pGpuResource, pCallContext, pParams, pCpuMapping) vblcbMap_DISPATCH(pGpuResource, pCallContext, pParams, pCpuMapping) #define vblcbAccessCallback(pResource, pInvokingClient, pAllocParams, accessRight) vblcbAccessCallback_DISPATCH(pResource, pInvokingClient, pAllocParams, accessRight) NV_STATUS vblcbCtrlSetVBlankNotification_IMPL(struct VblankCallback *pVblankCallback, NV9010_CTRL_CMD_SET_VBLANK_NOTIFICATION_PARAMS *pParams); @@ -155,84 +159,92 @@ return pGpuResource->__vblcbShareCallback__(pGpuResource, pInvokingClient, pParentRef, pSharePolicy); } -static inline NV_STATUS vblcbControl_DISPATCH(struct VblankCallback *pGpuResource, CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { - return pGpuResource->__vblcbControl__(pGpuResource, pCallContext, pParams); +static inline NV_STATUS vblcbCheckMemInterUnmap_DISPATCH(struct VblankCallback *pRmResource, NvBool bSubdeviceHandleProvided) { + return pRmResource->__vblcbCheckMemInterUnmap__(pRmResource, bSubdeviceHandleProvided); } -static inline NV_STATUS vblcbUnmap_DISPATCH(struct VblankCallback *pGpuResource, CALL_CONTEXT *pCallContext, RsCpuMapping *pCpuMapping) { - return pGpuResource->__vblcbUnmap__(pGpuResource, pCallContext, pCpuMapping); +static inline NV_STATUS vblcbMapTo_DISPATCH(struct VblankCallback *pResource, RS_RES_MAP_TO_PARAMS *pParams) { + return pResource->__vblcbMapTo__(pResource, pParams); } -static inline NV_STATUS vblcbGetMemInterMapParams_DISPATCH(struct VblankCallback *pRmResource, RMRES_MEM_INTER_MAP_PARAMS *pParams) { - return pRmResource->__vblcbGetMemInterMapParams__(pRmResource, pParams); +static inline NV_STATUS vblcbGetMapAddrSpace_DISPATCH(struct VblankCallback *pGpuResource, CALL_CONTEXT *pCallContext, NvU32 mapFlags, NV_ADDRESS_SPACE *pAddrSpace) { + return pGpuResource->__vblcbGetMapAddrSpace__(pGpuResource, pCallContext, mapFlags, pAddrSpace); } -static inline NV_STATUS vblcbGetMemoryMappingDescriptor_DISPATCH(struct VblankCallback *pRmResource, struct MEMORY_DESCRIPTOR **ppMemDesc) { - return pRmResource->__vblcbGetMemoryMappingDescriptor__(pRmResource, ppMemDesc); +static inline NvU32 vblcbGetRefCount_DISPATCH(struct VblankCallback *pResource) { + return pResource->__vblcbGetRefCount__(pResource); } -static inline NV_STATUS vblcbGetMapAddrSpace_DISPATCH(struct VblankCallback *pGpuResource, CALL_CONTEXT *pCallContext, NvU32 mapFlags, NV_ADDRESS_SPACE *pAddrSpace) { - return pGpuResource->__vblcbGetMapAddrSpace__(pGpuResource, pCallContext, mapFlags, pAddrSpace); +static inline void vblcbAddAdditionalDependants_DISPATCH(struct RsClient *pClient, struct VblankCallback *pResource, RsResourceRef *pReference) { + pResource->__vblcbAddAdditionalDependants__(pClient, pResource, pReference); } -static inline NvHandle vblcbGetInternalObjectHandle_DISPATCH(struct VblankCallback *pGpuResource) { - return pGpuResource->__vblcbGetInternalObjectHandle__(pGpuResource); +static inline NV_STATUS vblcbControl_Prologue_DISPATCH(struct VblankCallback *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return pResource->__vblcbControl_Prologue__(pResource, pCallContext, pParams); } -static inline NV_STATUS vblcbControlFilter_DISPATCH(struct VblankCallback *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { - return pResource->__vblcbControlFilter__(pResource, pCallContext, pParams); +static inline NV_STATUS vblcbGetRegBaseOffsetAndSize_DISPATCH(struct VblankCallback *pGpuResource, struct OBJGPU *pGpu, NvU32 *pOffset, NvU32 *pSize) { + return pGpuResource->__vblcbGetRegBaseOffsetAndSize__(pGpuResource, pGpu, pOffset, pSize); } -static inline void vblcbAddAdditionalDependants_DISPATCH(struct RsClient *pClient, struct VblankCallback *pResource, RsResourceRef *pReference) { - pResource->__vblcbAddAdditionalDependants__(pClient, pResource, pReference); +static inline NV_STATUS vblcbInternalControlForward_DISPATCH(struct VblankCallback *pGpuResource, NvU32 command, void *pParams, NvU32 size) { + return pGpuResource->__vblcbInternalControlForward__(pGpuResource, command, pParams, size); } -static inline NvU32 vblcbGetRefCount_DISPATCH(struct VblankCallback *pResource) { - return pResource->__vblcbGetRefCount__(pResource); +static inline NV_STATUS vblcbUnmapFrom_DISPATCH(struct VblankCallback *pResource, RS_RES_UNMAP_FROM_PARAMS *pParams) { + return pResource->__vblcbUnmapFrom__(pResource, pParams); } -static inline NV_STATUS vblcbCheckMemInterUnmap_DISPATCH(struct VblankCallback *pRmResource, NvBool bSubdeviceHandleProvided) { - return pRmResource->__vblcbCheckMemInterUnmap__(pRmResource, bSubdeviceHandleProvided); +static inline void vblcbControl_Epilogue_DISPATCH(struct VblankCallback *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + pResource->__vblcbControl_Epilogue__(pResource, pCallContext, pParams); } -static inline NV_STATUS vblcbMapTo_DISPATCH(struct VblankCallback *pResource, RS_RES_MAP_TO_PARAMS *pParams) { - return pResource->__vblcbMapTo__(pResource, pParams); +static inline NV_STATUS vblcbControlLookup_DISPATCH(struct VblankCallback *pResource, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams, const struct NVOC_EXPORTED_METHOD_DEF **ppEntry) { + return pResource->__vblcbControlLookup__(pResource, pParams, ppEntry); } -static inline NV_STATUS vblcbControl_Prologue_DISPATCH(struct VblankCallback *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { - return pResource->__vblcbControl_Prologue__(pResource, pCallContext, pParams); +static inline NvHandle vblcbGetInternalObjectHandle_DISPATCH(struct VblankCallback *pGpuResource) { + return pGpuResource->__vblcbGetInternalObjectHandle__(pGpuResource); } -static inline NV_STATUS vblcbGetRegBaseOffsetAndSize_DISPATCH(struct VblankCallback *pGpuResource, struct OBJGPU *pGpu, NvU32 *pOffset, NvU32 *pSize) { - return pGpuResource->__vblcbGetRegBaseOffsetAndSize__(pGpuResource, pGpu, pOffset, pSize); +static inline NV_STATUS vblcbControl_DISPATCH(struct VblankCallback *pGpuResource, CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return pGpuResource->__vblcbControl__(pGpuResource, pCallContext, pParams); } -static inline NvBool vblcbCanCopy_DISPATCH(struct VblankCallback *pResource) { - return pResource->__vblcbCanCopy__(pResource); +static inline NV_STATUS vblcbUnmap_DISPATCH(struct VblankCallback *pGpuResource, CALL_CONTEXT *pCallContext, RsCpuMapping *pCpuMapping) { + return pGpuResource->__vblcbUnmap__(pGpuResource, pCallContext, pCpuMapping); } -static inline NV_STATUS vblcbInternalControlForward_DISPATCH(struct VblankCallback *pGpuResource, NvU32 command, void *pParams, NvU32 size) { - return pGpuResource->__vblcbInternalControlForward__(pGpuResource, command, pParams, size); +static inline NV_STATUS vblcbGetMemInterMapParams_DISPATCH(struct VblankCallback *pRmResource, RMRES_MEM_INTER_MAP_PARAMS *pParams) { + return pRmResource->__vblcbGetMemInterMapParams__(pRmResource, pParams); } -static inline void vblcbPreDestruct_DISPATCH(struct VblankCallback *pResource) { - pResource->__vblcbPreDestruct__(pResource); +static inline NV_STATUS vblcbGetMemoryMappingDescriptor_DISPATCH(struct VblankCallback *pRmResource, struct MEMORY_DESCRIPTOR **ppMemDesc) { + return pRmResource->__vblcbGetMemoryMappingDescriptor__(pRmResource, ppMemDesc); } -static inline NV_STATUS vblcbUnmapFrom_DISPATCH(struct VblankCallback *pResource, RS_RES_UNMAP_FROM_PARAMS *pParams) { - return pResource->__vblcbUnmapFrom__(pResource, pParams); +static inline NV_STATUS vblcbControlFilter_DISPATCH(struct VblankCallback *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return pResource->__vblcbControlFilter__(pResource, pCallContext, pParams); } -static inline NV_STATUS vblcbIsDuplicate_DISPATCH(struct VblankCallback *pResource, NvHandle hMemory, NvBool *pDuplicate) { - return pResource->__vblcbIsDuplicate__(pResource, hMemory, pDuplicate); +static inline NV_STATUS vblcbControlSerialization_Prologue_DISPATCH(struct VblankCallback *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return pResource->__vblcbControlSerialization_Prologue__(pResource, pCallContext, pParams); } -static inline void vblcbControl_Epilogue_DISPATCH(struct VblankCallback *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { - pResource->__vblcbControl_Epilogue__(pResource, pCallContext, pParams); +static inline NvBool vblcbCanCopy_DISPATCH(struct VblankCallback *pResource) { + return pResource->__vblcbCanCopy__(pResource); } -static inline NV_STATUS vblcbControlLookup_DISPATCH(struct VblankCallback *pResource, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams, const struct NVOC_EXPORTED_METHOD_DEF **ppEntry) { - return pResource->__vblcbControlLookup__(pResource, pParams, ppEntry); +static inline void vblcbPreDestruct_DISPATCH(struct VblankCallback *pResource) { + pResource->__vblcbPreDestruct__(pResource); +} + +static inline NV_STATUS vblcbIsDuplicate_DISPATCH(struct VblankCallback *pResource, NvHandle hMemory, NvBool *pDuplicate) { + return pResource->__vblcbIsDuplicate__(pResource, hMemory, pDuplicate); +} + +static inline void vblcbControlSerialization_Epilogue_DISPATCH(struct VblankCallback *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + pResource->__vblcbControlSerialization_Epilogue__(pResource, pCallContext, pParams); } static inline NV_STATUS vblcbMap_DISPATCH(struct VblankCallback *pGpuResource, CALL_CONTEXT *pCallContext, struct RS_CPU_MAP_PARAMS *pParams, RsCpuMapping *pCpuMapping) { diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/generated/g_vgpuconfigapi_nvoc.c nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_vgpuconfigapi_nvoc.c --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/generated/g_vgpuconfigapi_nvoc.c 2023-10-25 20:27:23.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_vgpuconfigapi_nvoc.c 2024-03-05 22:18:51.000000000 +0000 @@ -115,16 +115,16 @@ return gpuresShareCallback((struct GpuResource *)(((unsigned char *)pGpuResource) + __nvoc_rtti_VgpuConfigApi_GpuResource.offset), pInvokingClient, pParentRef, pSharePolicy); } -static NV_STATUS __nvoc_thunk_RsResource_vgpuconfigapiMapTo(struct VgpuConfigApi *pResource, RS_RES_MAP_TO_PARAMS *pParams) { - return resMapTo((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_VgpuConfigApi_RsResource.offset), pParams); +static NV_STATUS __nvoc_thunk_RmResource_vgpuconfigapiCheckMemInterUnmap(struct VgpuConfigApi *pRmResource, NvBool bSubdeviceHandleProvided) { + return rmresCheckMemInterUnmap((struct RmResource *)(((unsigned char *)pRmResource) + __nvoc_rtti_VgpuConfigApi_RmResource.offset), bSubdeviceHandleProvided); } static NV_STATUS __nvoc_thunk_Notifier_vgpuconfigapiGetOrAllocNotifShare(struct VgpuConfigApi *pNotifier, NvHandle hNotifierClient, NvHandle hNotifierResource, struct NotifShare **ppNotifShare) { return notifyGetOrAllocNotifShare((struct Notifier *)(((unsigned char *)pNotifier) + __nvoc_rtti_VgpuConfigApi_Notifier.offset), hNotifierClient, hNotifierResource, ppNotifShare); } -static NV_STATUS __nvoc_thunk_RmResource_vgpuconfigapiCheckMemInterUnmap(struct VgpuConfigApi *pRmResource, NvBool bSubdeviceHandleProvided) { - return rmresCheckMemInterUnmap((struct RmResource *)(((unsigned char *)pRmResource) + __nvoc_rtti_VgpuConfigApi_RmResource.offset), bSubdeviceHandleProvided); +static NV_STATUS __nvoc_thunk_RsResource_vgpuconfigapiMapTo(struct VgpuConfigApi *pResource, RS_RES_MAP_TO_PARAMS *pParams) { + return resMapTo((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_VgpuConfigApi_RsResource.offset), pParams); } static NV_STATUS __nvoc_thunk_GpuResource_vgpuconfigapiGetMapAddrSpace(struct VgpuConfigApi *pGpuResource, struct CALL_CONTEXT *pCallContext, NvU32 mapFlags, NV_ADDRESS_SPACE *pAddrSpace) { @@ -195,6 +195,10 @@ return notifyUnregisterEvent((struct Notifier *)(((unsigned char *)pNotifier) + __nvoc_rtti_VgpuConfigApi_Notifier.offset), hNotifierClient, hNotifierResource, hEventClient, hEvent); } +static NV_STATUS __nvoc_thunk_RmResource_vgpuconfigapiControlSerialization_Prologue(struct VgpuConfigApi *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return rmresControlSerialization_Prologue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_VgpuConfigApi_RmResource.offset), pCallContext, pParams); +} + static NvBool __nvoc_thunk_RsResource_vgpuconfigapiCanCopy(struct VgpuConfigApi *pResource) { return resCanCopy((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_VgpuConfigApi_RsResource.offset)); } @@ -207,6 +211,10 @@ return resIsDuplicate((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_VgpuConfigApi_RsResource.offset), hMemory, pDuplicate); } +static void __nvoc_thunk_RmResource_vgpuconfigapiControlSerialization_Epilogue(struct VgpuConfigApi *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + rmresControlSerialization_Epilogue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_VgpuConfigApi_RmResource.offset), pCallContext, pParams); +} + static PEVENTNOTIFICATION *__nvoc_thunk_Notifier_vgpuconfigapiGetNotificationListPtr(struct VgpuConfigApi *pNotifier) { return notifyGetNotificationListPtr((struct Notifier *)(((unsigned char *)pNotifier) + __nvoc_rtti_VgpuConfigApi_Notifier.offset)); } @@ -499,12 +507,27 @@ /*func=*/ "vgpuconfigapiCtrlCmdVgpuConfigSetPgpuInfo" #endif }, + { /* [18] */ +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x4u) + /*pFunc=*/ (void (*)(void)) NULL, +#else + /*pFunc=*/ (void (*)(void)) vgpuconfigapiCtrlCmdVgpuConfigValidateSwizzId_IMPL, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x4u) + /*flags=*/ 0x4u, + /*accessRight=*/0x0u, + /*methodId=*/ 0xa081011au, + /*paramSize=*/ sizeof(NVA081_CTRL_VGPU_CONFIG_VALIDATE_SWIZZID_PARAMS), + /*pClassInfo=*/ &(__nvoc_class_def_VgpuConfigApi.classInfo), +#if NV_PRINTF_STRINGS_ALLOWED + /*func=*/ "vgpuconfigapiCtrlCmdVgpuConfigValidateSwizzId" +#endif + }, }; const struct NVOC_EXPORT_INFO __nvoc_export_info_VgpuConfigApi = { - /*numEntries=*/ 18, + /*numEntries=*/ 19, /*pExportEntries=*/ __nvoc_exported_method_def_VgpuConfigApi }; @@ -620,13 +643,17 @@ pThis->__vgpuconfigapiCtrlCmdVgpuConfigSetPgpuInfo__ = &vgpuconfigapiCtrlCmdVgpuConfigSetPgpuInfo_IMPL; #endif +#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x4u) + pThis->__vgpuconfigapiCtrlCmdVgpuConfigValidateSwizzId__ = &vgpuconfigapiCtrlCmdVgpuConfigValidateSwizzId_IMPL; +#endif + pThis->__vgpuconfigapiShareCallback__ = &__nvoc_thunk_GpuResource_vgpuconfigapiShareCallback; - pThis->__vgpuconfigapiMapTo__ = &__nvoc_thunk_RsResource_vgpuconfigapiMapTo; + pThis->__vgpuconfigapiCheckMemInterUnmap__ = &__nvoc_thunk_RmResource_vgpuconfigapiCheckMemInterUnmap; pThis->__vgpuconfigapiGetOrAllocNotifShare__ = &__nvoc_thunk_Notifier_vgpuconfigapiGetOrAllocNotifShare; - pThis->__vgpuconfigapiCheckMemInterUnmap__ = &__nvoc_thunk_RmResource_vgpuconfigapiCheckMemInterUnmap; + pThis->__vgpuconfigapiMapTo__ = &__nvoc_thunk_RsResource_vgpuconfigapiMapTo; pThis->__vgpuconfigapiGetMapAddrSpace__ = &__nvoc_thunk_GpuResource_vgpuconfigapiGetMapAddrSpace; @@ -662,12 +689,16 @@ pThis->__vgpuconfigapiUnregisterEvent__ = &__nvoc_thunk_Notifier_vgpuconfigapiUnregisterEvent; + pThis->__vgpuconfigapiControlSerialization_Prologue__ = &__nvoc_thunk_RmResource_vgpuconfigapiControlSerialization_Prologue; + pThis->__vgpuconfigapiCanCopy__ = &__nvoc_thunk_RsResource_vgpuconfigapiCanCopy; pThis->__vgpuconfigapiPreDestruct__ = &__nvoc_thunk_RsResource_vgpuconfigapiPreDestruct; pThis->__vgpuconfigapiIsDuplicate__ = &__nvoc_thunk_RsResource_vgpuconfigapiIsDuplicate; + pThis->__vgpuconfigapiControlSerialization_Epilogue__ = &__nvoc_thunk_RmResource_vgpuconfigapiControlSerialization_Epilogue; + pThis->__vgpuconfigapiGetNotificationListPtr__ = &__nvoc_thunk_Notifier_vgpuconfigapiGetNotificationListPtr; pThis->__vgpuconfigapiGetNotificationShare__ = &__nvoc_thunk_Notifier_vgpuconfigapiGetNotificationShare; @@ -702,13 +733,16 @@ Object *pParentObj; VgpuConfigApi *pThis; - pThis = portMemAllocNonPaged(sizeof(VgpuConfigApi)); - if (pThis == NULL) return NV_ERR_NO_MEMORY; + status = __nvoc_handleObjCreateMemAlloc(createFlags, sizeof(VgpuConfigApi), (void**)&pThis, (void**)ppThis); + if (status != NV_OK) + return status; portMemSet(pThis, 0, sizeof(VgpuConfigApi)); __nvoc_initRtti(staticCast(pThis, Dynamic), &__nvoc_class_def_VgpuConfigApi); + pThis->__nvoc_base_GpuResource.__nvoc_base_RmResource.__nvoc_base_RsResource.__nvoc_base_Object.createFlags = createFlags; + if (pParent != NULL && !(createFlags & NVOC_OBJ_CREATE_FLAGS_PARENT_HALSPEC_ONLY)) { pParentObj = dynamicCast(pParent, Object); @@ -724,11 +758,17 @@ if (status != NV_OK) goto __nvoc_objCreate_VgpuConfigApi_cleanup; *ppThis = pThis; + return NV_OK; __nvoc_objCreate_VgpuConfigApi_cleanup: // do not call destructors here since the constructor already called them - portMemFree(pThis); + if (createFlags & NVOC_OBJ_CREATE_FLAGS_IN_PLACE_CONSTRUCT) + portMemSet(pThis, 0, sizeof(VgpuConfigApi)); + else + portMemFree(pThis); + + // coverity[leaked_storage:FALSE] return status; } diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/generated/g_vgpuconfigapi_nvoc.h nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_vgpuconfigapi_nvoc.h --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/generated/g_vgpuconfigapi_nvoc.h 2023-10-25 20:27:23.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_vgpuconfigapi_nvoc.h 2024-03-05 22:18:51.000000000 +0000 @@ -80,10 +80,11 @@ NV_STATUS (*__vgpuconfigapiCtrlCmdPgpuGetMultiVgpuSupportInfo__)(struct VgpuConfigApi *, NVA081_CTRL_PGPU_GET_MULTI_VGPU_SUPPORT_INFO_PARAMS *); NV_STATUS (*__vgpuconfigapiCtrlCmdGetVgpuDriversCaps__)(struct VgpuConfigApi *, NVA081_CTRL_GET_VGPU_DRIVER_CAPS_PARAMS *); NV_STATUS (*__vgpuconfigapiCtrlCmdVgpuConfigSetPgpuInfo__)(struct VgpuConfigApi *, NVA081_CTRL_VGPU_CONFIG_SET_PGPU_INFO_PARAMS *); + NV_STATUS (*__vgpuconfigapiCtrlCmdVgpuConfigValidateSwizzId__)(struct VgpuConfigApi *, NVA081_CTRL_VGPU_CONFIG_VALIDATE_SWIZZID_PARAMS *); NvBool (*__vgpuconfigapiShareCallback__)(struct VgpuConfigApi *, struct RsClient *, struct RsResourceRef *, RS_SHARE_POLICY *); - NV_STATUS (*__vgpuconfigapiMapTo__)(struct VgpuConfigApi *, RS_RES_MAP_TO_PARAMS *); - NV_STATUS (*__vgpuconfigapiGetOrAllocNotifShare__)(struct VgpuConfigApi *, NvHandle, NvHandle, struct NotifShare **); NV_STATUS (*__vgpuconfigapiCheckMemInterUnmap__)(struct VgpuConfigApi *, NvBool); + NV_STATUS (*__vgpuconfigapiGetOrAllocNotifShare__)(struct VgpuConfigApi *, NvHandle, NvHandle, struct NotifShare **); + NV_STATUS (*__vgpuconfigapiMapTo__)(struct VgpuConfigApi *, RS_RES_MAP_TO_PARAMS *); NV_STATUS (*__vgpuconfigapiGetMapAddrSpace__)(struct VgpuConfigApi *, struct CALL_CONTEXT *, NvU32, NV_ADDRESS_SPACE *); void (*__vgpuconfigapiSetNotificationShare__)(struct VgpuConfigApi *, struct NotifShare *); NvU32 (*__vgpuconfigapiGetRefCount__)(struct VgpuConfigApi *); @@ -101,9 +102,11 @@ NV_STATUS (*__vgpuconfigapiGetMemoryMappingDescriptor__)(struct VgpuConfigApi *, struct MEMORY_DESCRIPTOR **); NV_STATUS (*__vgpuconfigapiControlFilter__)(struct VgpuConfigApi *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); NV_STATUS (*__vgpuconfigapiUnregisterEvent__)(struct VgpuConfigApi *, NvHandle, NvHandle, NvHandle, NvHandle); + NV_STATUS (*__vgpuconfigapiControlSerialization_Prologue__)(struct VgpuConfigApi *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); NvBool (*__vgpuconfigapiCanCopy__)(struct VgpuConfigApi *); void (*__vgpuconfigapiPreDestruct__)(struct VgpuConfigApi *); NV_STATUS (*__vgpuconfigapiIsDuplicate__)(struct VgpuConfigApi *, NvHandle, NvBool *); + void (*__vgpuconfigapiControlSerialization_Epilogue__)(struct VgpuConfigApi *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); PEVENTNOTIFICATION *(*__vgpuconfigapiGetNotificationListPtr__)(struct VgpuConfigApi *); struct NotifShare *(*__vgpuconfigapiGetNotificationShare__)(struct VgpuConfigApi *); NV_STATUS (*__vgpuconfigapiMap__)(struct VgpuConfigApi *, struct CALL_CONTEXT *, struct RS_CPU_MAP_PARAMS *, struct RsCpuMapping *); @@ -157,10 +160,11 @@ #define vgpuconfigapiCtrlCmdPgpuGetMultiVgpuSupportInfo(pVgpuConfigApi, pParams) vgpuconfigapiCtrlCmdPgpuGetMultiVgpuSupportInfo_DISPATCH(pVgpuConfigApi, pParams) #define vgpuconfigapiCtrlCmdGetVgpuDriversCaps(pVgpuConfigApi, pParams) vgpuconfigapiCtrlCmdGetVgpuDriversCaps_DISPATCH(pVgpuConfigApi, pParams) #define vgpuconfigapiCtrlCmdVgpuConfigSetPgpuInfo(pVgpuConfigApi, pParams) vgpuconfigapiCtrlCmdVgpuConfigSetPgpuInfo_DISPATCH(pVgpuConfigApi, pParams) +#define vgpuconfigapiCtrlCmdVgpuConfigValidateSwizzId(pVgpuConfigApi, pParams) vgpuconfigapiCtrlCmdVgpuConfigValidateSwizzId_DISPATCH(pVgpuConfigApi, pParams) #define vgpuconfigapiShareCallback(pGpuResource, pInvokingClient, pParentRef, pSharePolicy) vgpuconfigapiShareCallback_DISPATCH(pGpuResource, pInvokingClient, pParentRef, pSharePolicy) -#define vgpuconfigapiMapTo(pResource, pParams) vgpuconfigapiMapTo_DISPATCH(pResource, pParams) -#define vgpuconfigapiGetOrAllocNotifShare(pNotifier, hNotifierClient, hNotifierResource, ppNotifShare) vgpuconfigapiGetOrAllocNotifShare_DISPATCH(pNotifier, hNotifierClient, hNotifierResource, ppNotifShare) #define vgpuconfigapiCheckMemInterUnmap(pRmResource, bSubdeviceHandleProvided) vgpuconfigapiCheckMemInterUnmap_DISPATCH(pRmResource, bSubdeviceHandleProvided) +#define vgpuconfigapiGetOrAllocNotifShare(pNotifier, hNotifierClient, hNotifierResource, ppNotifShare) vgpuconfigapiGetOrAllocNotifShare_DISPATCH(pNotifier, hNotifierClient, hNotifierResource, ppNotifShare) +#define vgpuconfigapiMapTo(pResource, pParams) vgpuconfigapiMapTo_DISPATCH(pResource, pParams) #define vgpuconfigapiGetMapAddrSpace(pGpuResource, pCallContext, mapFlags, pAddrSpace) vgpuconfigapiGetMapAddrSpace_DISPATCH(pGpuResource, pCallContext, mapFlags, pAddrSpace) #define vgpuconfigapiSetNotificationShare(pNotifier, pNotifShare) vgpuconfigapiSetNotificationShare_DISPATCH(pNotifier, pNotifShare) #define vgpuconfigapiGetRefCount(pResource) vgpuconfigapiGetRefCount_DISPATCH(pResource) @@ -178,9 +182,11 @@ #define vgpuconfigapiGetMemoryMappingDescriptor(pRmResource, ppMemDesc) vgpuconfigapiGetMemoryMappingDescriptor_DISPATCH(pRmResource, ppMemDesc) #define vgpuconfigapiControlFilter(pResource, pCallContext, pParams) vgpuconfigapiControlFilter_DISPATCH(pResource, pCallContext, pParams) #define vgpuconfigapiUnregisterEvent(pNotifier, hNotifierClient, hNotifierResource, hEventClient, hEvent) vgpuconfigapiUnregisterEvent_DISPATCH(pNotifier, hNotifierClient, hNotifierResource, hEventClient, hEvent) +#define vgpuconfigapiControlSerialization_Prologue(pResource, pCallContext, pParams) vgpuconfigapiControlSerialization_Prologue_DISPATCH(pResource, pCallContext, pParams) #define vgpuconfigapiCanCopy(pResource) vgpuconfigapiCanCopy_DISPATCH(pResource) #define vgpuconfigapiPreDestruct(pResource) vgpuconfigapiPreDestruct_DISPATCH(pResource) #define vgpuconfigapiIsDuplicate(pResource, hMemory, pDuplicate) vgpuconfigapiIsDuplicate_DISPATCH(pResource, hMemory, pDuplicate) +#define vgpuconfigapiControlSerialization_Epilogue(pResource, pCallContext, pParams) vgpuconfigapiControlSerialization_Epilogue_DISPATCH(pResource, pCallContext, pParams) #define vgpuconfigapiGetNotificationListPtr(pNotifier) vgpuconfigapiGetNotificationListPtr_DISPATCH(pNotifier) #define vgpuconfigapiGetNotificationShare(pNotifier) vgpuconfigapiGetNotificationShare_DISPATCH(pNotifier) #define vgpuconfigapiMap(pGpuResource, pCallContext, pParams, pCpuMapping) vgpuconfigapiMap_DISPATCH(pGpuResource, pCallContext, pParams, pCpuMapping) @@ -293,20 +299,26 @@ return pVgpuConfigApi->__vgpuconfigapiCtrlCmdVgpuConfigSetPgpuInfo__(pVgpuConfigApi, pParams); } +NV_STATUS vgpuconfigapiCtrlCmdVgpuConfigValidateSwizzId_IMPL(struct VgpuConfigApi *pVgpuConfigApi, NVA081_CTRL_VGPU_CONFIG_VALIDATE_SWIZZID_PARAMS *pParams); + +static inline NV_STATUS vgpuconfigapiCtrlCmdVgpuConfigValidateSwizzId_DISPATCH(struct VgpuConfigApi *pVgpuConfigApi, NVA081_CTRL_VGPU_CONFIG_VALIDATE_SWIZZID_PARAMS *pParams) { + return pVgpuConfigApi->__vgpuconfigapiCtrlCmdVgpuConfigValidateSwizzId__(pVgpuConfigApi, pParams); +} + static inline NvBool vgpuconfigapiShareCallback_DISPATCH(struct VgpuConfigApi *pGpuResource, struct RsClient *pInvokingClient, struct RsResourceRef *pParentRef, RS_SHARE_POLICY *pSharePolicy) { return pGpuResource->__vgpuconfigapiShareCallback__(pGpuResource, pInvokingClient, pParentRef, pSharePolicy); } -static inline NV_STATUS vgpuconfigapiMapTo_DISPATCH(struct VgpuConfigApi *pResource, RS_RES_MAP_TO_PARAMS *pParams) { - return pResource->__vgpuconfigapiMapTo__(pResource, pParams); +static inline NV_STATUS vgpuconfigapiCheckMemInterUnmap_DISPATCH(struct VgpuConfigApi *pRmResource, NvBool bSubdeviceHandleProvided) { + return pRmResource->__vgpuconfigapiCheckMemInterUnmap__(pRmResource, bSubdeviceHandleProvided); } static inline NV_STATUS vgpuconfigapiGetOrAllocNotifShare_DISPATCH(struct VgpuConfigApi *pNotifier, NvHandle hNotifierClient, NvHandle hNotifierResource, struct NotifShare **ppNotifShare) { return pNotifier->__vgpuconfigapiGetOrAllocNotifShare__(pNotifier, hNotifierClient, hNotifierResource, ppNotifShare); } -static inline NV_STATUS vgpuconfigapiCheckMemInterUnmap_DISPATCH(struct VgpuConfigApi *pRmResource, NvBool bSubdeviceHandleProvided) { - return pRmResource->__vgpuconfigapiCheckMemInterUnmap__(pRmResource, bSubdeviceHandleProvided); +static inline NV_STATUS vgpuconfigapiMapTo_DISPATCH(struct VgpuConfigApi *pResource, RS_RES_MAP_TO_PARAMS *pParams) { + return pResource->__vgpuconfigapiMapTo__(pResource, pParams); } static inline NV_STATUS vgpuconfigapiGetMapAddrSpace_DISPATCH(struct VgpuConfigApi *pGpuResource, struct CALL_CONTEXT *pCallContext, NvU32 mapFlags, NV_ADDRESS_SPACE *pAddrSpace) { @@ -377,6 +389,10 @@ return pNotifier->__vgpuconfigapiUnregisterEvent__(pNotifier, hNotifierClient, hNotifierResource, hEventClient, hEvent); } +static inline NV_STATUS vgpuconfigapiControlSerialization_Prologue_DISPATCH(struct VgpuConfigApi *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return pResource->__vgpuconfigapiControlSerialization_Prologue__(pResource, pCallContext, pParams); +} + static inline NvBool vgpuconfigapiCanCopy_DISPATCH(struct VgpuConfigApi *pResource) { return pResource->__vgpuconfigapiCanCopy__(pResource); } @@ -389,6 +405,10 @@ return pResource->__vgpuconfigapiIsDuplicate__(pResource, hMemory, pDuplicate); } +static inline void vgpuconfigapiControlSerialization_Epilogue_DISPATCH(struct VgpuConfigApi *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + pResource->__vgpuconfigapiControlSerialization_Epilogue__(pResource, pCallContext, pParams); +} + static inline PEVENTNOTIFICATION *vgpuconfigapiGetNotificationListPtr_DISPATCH(struct VgpuConfigApi *pNotifier) { return pNotifier->__vgpuconfigapiGetNotificationListPtr__(pNotifier); } diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/generated/g_video_mem_nvoc.c nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_video_mem_nvoc.c --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/generated/g_video_mem_nvoc.c 2023-10-25 20:27:23.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_video_mem_nvoc.c 2024-03-05 22:18:51.000000000 +0000 @@ -102,64 +102,80 @@ /*pExportInfo=*/ &__nvoc_export_info_VideoMemory }; -static NV_STATUS __nvoc_thunk_VideoMemory_memCheckCopyPermissions(struct Memory *pVideoMemory, struct OBJGPU *pDstGpu, NvHandle hDstClientNvBool) { - return vidmemCheckCopyPermissions((struct VideoMemory *)(((unsigned char *)pVideoMemory) - __nvoc_rtti_VideoMemory_Memory.offset), pDstGpu, hDstClientNvBool); +static NV_STATUS __nvoc_thunk_VideoMemory_memCheckCopyPermissions(struct Memory *pVideoMemory, struct OBJGPU *pDstGpu, struct Device *pDstDevice) { + return vidmemCheckCopyPermissions((struct VideoMemory *)(((unsigned char *)pVideoMemory) - __nvoc_rtti_VideoMemory_Memory.offset), pDstGpu, pDstDevice); } static NV_STATUS __nvoc_thunk_Memory_vidmemCheckMemInterUnmap(struct VideoMemory *pMemory, NvBool bSubdeviceHandleProvided) { return memCheckMemInterUnmap((struct Memory *)(((unsigned char *)pMemory) + __nvoc_rtti_VideoMemory_Memory.offset), bSubdeviceHandleProvided); } -static NV_STATUS __nvoc_thunk_Memory_vidmemControl(struct VideoMemory *pMemory, CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { - return memControl((struct Memory *)(((unsigned char *)pMemory) + __nvoc_rtti_VideoMemory_Memory.offset), pCallContext, pParams); +static NvBool __nvoc_thunk_RmResource_vidmemShareCallback(struct VideoMemory *pResource, struct RsClient *pInvokingClient, struct RsResourceRef *pParentRef, RS_SHARE_POLICY *pSharePolicy) { + return rmresShareCallback((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_VideoMemory_RmResource.offset), pInvokingClient, pParentRef, pSharePolicy); } -static NV_STATUS __nvoc_thunk_Memory_vidmemUnmap(struct VideoMemory *pMemory, CALL_CONTEXT *pCallContext, RsCpuMapping *pCpuMapping) { - return memUnmap((struct Memory *)(((unsigned char *)pMemory) + __nvoc_rtti_VideoMemory_Memory.offset), pCallContext, pCpuMapping); +static NV_STATUS __nvoc_thunk_RsResource_vidmemMapTo(struct VideoMemory *pResource, RS_RES_MAP_TO_PARAMS *pParams) { + return resMapTo((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_VideoMemory_RsResource.offset), pParams); } -static NV_STATUS __nvoc_thunk_Memory_vidmemGetMemInterMapParams(struct VideoMemory *pMemory, RMRES_MEM_INTER_MAP_PARAMS *pParams) { - return memGetMemInterMapParams((struct Memory *)(((unsigned char *)pMemory) + __nvoc_rtti_VideoMemory_Memory.offset), pParams); +static NV_STATUS __nvoc_thunk_Memory_vidmemGetMapAddrSpace(struct VideoMemory *pMemory, CALL_CONTEXT *pCallContext, NvU32 mapFlags, NV_ADDRESS_SPACE *pAddrSpace) { + return memGetMapAddrSpace((struct Memory *)(((unsigned char *)pMemory) + __nvoc_rtti_VideoMemory_Memory.offset), pCallContext, mapFlags, pAddrSpace); } -static NV_STATUS __nvoc_thunk_Memory_vidmemGetMemoryMappingDescriptor(struct VideoMemory *pMemory, MEMORY_DESCRIPTOR **ppMemDesc) { - return memGetMemoryMappingDescriptor((struct Memory *)(((unsigned char *)pMemory) + __nvoc_rtti_VideoMemory_Memory.offset), ppMemDesc); +static NvU32 __nvoc_thunk_RsResource_vidmemGetRefCount(struct VideoMemory *pResource) { + return resGetRefCount((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_VideoMemory_RsResource.offset)); } -static NV_STATUS __nvoc_thunk_Memory_vidmemGetMapAddrSpace(struct VideoMemory *pMemory, CALL_CONTEXT *pCallContext, NvU32 mapFlags, NV_ADDRESS_SPACE *pAddrSpace) { - return memGetMapAddrSpace((struct Memory *)(((unsigned char *)pMemory) + __nvoc_rtti_VideoMemory_Memory.offset), pCallContext, mapFlags, pAddrSpace); +static void __nvoc_thunk_RsResource_vidmemAddAdditionalDependants(struct RsClient *pClient, struct VideoMemory *pResource, RsResourceRef *pReference) { + resAddAdditionalDependants(pClient, (struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_VideoMemory_RsResource.offset), pReference); } -static NvBool __nvoc_thunk_RmResource_vidmemShareCallback(struct VideoMemory *pResource, struct RsClient *pInvokingClient, struct RsResourceRef *pParentRef, RS_SHARE_POLICY *pSharePolicy) { - return rmresShareCallback((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_VideoMemory_RmResource.offset), pInvokingClient, pParentRef, pSharePolicy); +static NV_STATUS __nvoc_thunk_RmResource_vidmemControl_Prologue(struct VideoMemory *pResource, CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return rmresControl_Prologue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_VideoMemory_RmResource.offset), pCallContext, pParams); } -static NV_STATUS __nvoc_thunk_RsResource_vidmemControlFilter(struct VideoMemory *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { - return resControlFilter((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_VideoMemory_RsResource.offset), pCallContext, pParams); +static NvBool __nvoc_thunk_Memory_vidmemIsGpuMapAllowed(struct VideoMemory *pMemory, struct OBJGPU *pGpu) { + return memIsGpuMapAllowed((struct Memory *)(((unsigned char *)pMemory) + __nvoc_rtti_VideoMemory_Memory.offset), pGpu); } -static void __nvoc_thunk_RsResource_vidmemAddAdditionalDependants(struct RsClient *pClient, struct VideoMemory *pResource, RsResourceRef *pReference) { - resAddAdditionalDependants(pClient, (struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_VideoMemory_RsResource.offset), pReference); +static NV_STATUS __nvoc_thunk_RsResource_vidmemUnmapFrom(struct VideoMemory *pResource, RS_RES_UNMAP_FROM_PARAMS *pParams) { + return resUnmapFrom((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_VideoMemory_RsResource.offset), pParams); } -static NvU32 __nvoc_thunk_RsResource_vidmemGetRefCount(struct VideoMemory *pResource) { - return resGetRefCount((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_VideoMemory_RsResource.offset)); +static void __nvoc_thunk_RmResource_vidmemControl_Epilogue(struct VideoMemory *pResource, CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + rmresControl_Epilogue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_VideoMemory_RmResource.offset), pCallContext, pParams); } -static NV_STATUS __nvoc_thunk_RsResource_vidmemMapTo(struct VideoMemory *pResource, RS_RES_MAP_TO_PARAMS *pParams) { - return resMapTo((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_VideoMemory_RsResource.offset), pParams); +static NV_STATUS __nvoc_thunk_RsResource_vidmemControlLookup(struct VideoMemory *pResource, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams, const struct NVOC_EXPORTED_METHOD_DEF **ppEntry) { + return resControlLookup((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_VideoMemory_RsResource.offset), pParams, ppEntry); } -static NvBool __nvoc_thunk_StandardMemory_vidmemCanCopy(struct VideoMemory *pStandardMemory) { - return stdmemCanCopy((struct StandardMemory *)(((unsigned char *)pStandardMemory) + __nvoc_rtti_VideoMemory_StandardMemory.offset)); +static NV_STATUS __nvoc_thunk_Memory_vidmemControl(struct VideoMemory *pMemory, CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return memControl((struct Memory *)(((unsigned char *)pMemory) + __nvoc_rtti_VideoMemory_Memory.offset), pCallContext, pParams); } -static NvBool __nvoc_thunk_Memory_vidmemIsGpuMapAllowed(struct VideoMemory *pMemory, struct OBJGPU *pGpu) { - return memIsGpuMapAllowed((struct Memory *)(((unsigned char *)pMemory) + __nvoc_rtti_VideoMemory_Memory.offset), pGpu); +static NV_STATUS __nvoc_thunk_Memory_vidmemUnmap(struct VideoMemory *pMemory, CALL_CONTEXT *pCallContext, RsCpuMapping *pCpuMapping) { + return memUnmap((struct Memory *)(((unsigned char *)pMemory) + __nvoc_rtti_VideoMemory_Memory.offset), pCallContext, pCpuMapping); } -static NV_STATUS __nvoc_thunk_RmResource_vidmemControl_Prologue(struct VideoMemory *pResource, CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { - return rmresControl_Prologue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_VideoMemory_RmResource.offset), pCallContext, pParams); +static NV_STATUS __nvoc_thunk_Memory_vidmemGetMemInterMapParams(struct VideoMemory *pMemory, RMRES_MEM_INTER_MAP_PARAMS *pParams) { + return memGetMemInterMapParams((struct Memory *)(((unsigned char *)pMemory) + __nvoc_rtti_VideoMemory_Memory.offset), pParams); +} + +static NV_STATUS __nvoc_thunk_Memory_vidmemGetMemoryMappingDescriptor(struct VideoMemory *pMemory, MEMORY_DESCRIPTOR **ppMemDesc) { + return memGetMemoryMappingDescriptor((struct Memory *)(((unsigned char *)pMemory) + __nvoc_rtti_VideoMemory_Memory.offset), ppMemDesc); +} + +static NV_STATUS __nvoc_thunk_RsResource_vidmemControlFilter(struct VideoMemory *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return resControlFilter((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_VideoMemory_RsResource.offset), pCallContext, pParams); +} + +static NV_STATUS __nvoc_thunk_RmResource_vidmemControlSerialization_Prologue(struct VideoMemory *pResource, CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return rmresControlSerialization_Prologue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_VideoMemory_RmResource.offset), pCallContext, pParams); +} + +static NvBool __nvoc_thunk_StandardMemory_vidmemCanCopy(struct VideoMemory *pStandardMemory) { + return stdmemCanCopy((struct StandardMemory *)(((unsigned char *)pStandardMemory) + __nvoc_rtti_VideoMemory_StandardMemory.offset)); } static NV_STATUS __nvoc_thunk_Memory_vidmemIsReady(struct VideoMemory *pMemory, NvBool bCopyConstructorContext) { @@ -174,16 +190,8 @@ return memIsDuplicate((struct Memory *)(((unsigned char *)pMemory) + __nvoc_rtti_VideoMemory_Memory.offset), hMemory, pDuplicate); } -static NV_STATUS __nvoc_thunk_RsResource_vidmemUnmapFrom(struct VideoMemory *pResource, RS_RES_UNMAP_FROM_PARAMS *pParams) { - return resUnmapFrom((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_VideoMemory_RsResource.offset), pParams); -} - -static void __nvoc_thunk_RmResource_vidmemControl_Epilogue(struct VideoMemory *pResource, CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { - rmresControl_Epilogue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_VideoMemory_RmResource.offset), pCallContext, pParams); -} - -static NV_STATUS __nvoc_thunk_RsResource_vidmemControlLookup(struct VideoMemory *pResource, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams, const struct NVOC_EXPORTED_METHOD_DEF **ppEntry) { - return resControlLookup((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_VideoMemory_RsResource.offset), pParams, ppEntry); +static void __nvoc_thunk_RmResource_vidmemControlSerialization_Epilogue(struct VideoMemory *pResource, CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + rmresControlSerialization_Epilogue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_VideoMemory_RmResource.offset), pCallContext, pParams); } static NV_STATUS __nvoc_thunk_Memory_vidmemMap(struct VideoMemory *pMemory, CALL_CONTEXT *pCallContext, struct RS_CPU_MAP_PARAMS *pParams, RsCpuMapping *pCpuMapping) { @@ -239,31 +247,39 @@ pThis->__vidmemCheckMemInterUnmap__ = &__nvoc_thunk_Memory_vidmemCheckMemInterUnmap; - pThis->__vidmemControl__ = &__nvoc_thunk_Memory_vidmemControl; + pThis->__vidmemShareCallback__ = &__nvoc_thunk_RmResource_vidmemShareCallback; - pThis->__vidmemUnmap__ = &__nvoc_thunk_Memory_vidmemUnmap; + pThis->__vidmemMapTo__ = &__nvoc_thunk_RsResource_vidmemMapTo; - pThis->__vidmemGetMemInterMapParams__ = &__nvoc_thunk_Memory_vidmemGetMemInterMapParams; + pThis->__vidmemGetMapAddrSpace__ = &__nvoc_thunk_Memory_vidmemGetMapAddrSpace; - pThis->__vidmemGetMemoryMappingDescriptor__ = &__nvoc_thunk_Memory_vidmemGetMemoryMappingDescriptor; + pThis->__vidmemGetRefCount__ = &__nvoc_thunk_RsResource_vidmemGetRefCount; - pThis->__vidmemGetMapAddrSpace__ = &__nvoc_thunk_Memory_vidmemGetMapAddrSpace; + pThis->__vidmemAddAdditionalDependants__ = &__nvoc_thunk_RsResource_vidmemAddAdditionalDependants; - pThis->__vidmemShareCallback__ = &__nvoc_thunk_RmResource_vidmemShareCallback; + pThis->__vidmemControl_Prologue__ = &__nvoc_thunk_RmResource_vidmemControl_Prologue; - pThis->__vidmemControlFilter__ = &__nvoc_thunk_RsResource_vidmemControlFilter; + pThis->__vidmemIsGpuMapAllowed__ = &__nvoc_thunk_Memory_vidmemIsGpuMapAllowed; - pThis->__vidmemAddAdditionalDependants__ = &__nvoc_thunk_RsResource_vidmemAddAdditionalDependants; + pThis->__vidmemUnmapFrom__ = &__nvoc_thunk_RsResource_vidmemUnmapFrom; - pThis->__vidmemGetRefCount__ = &__nvoc_thunk_RsResource_vidmemGetRefCount; + pThis->__vidmemControl_Epilogue__ = &__nvoc_thunk_RmResource_vidmemControl_Epilogue; - pThis->__vidmemMapTo__ = &__nvoc_thunk_RsResource_vidmemMapTo; + pThis->__vidmemControlLookup__ = &__nvoc_thunk_RsResource_vidmemControlLookup; - pThis->__vidmemCanCopy__ = &__nvoc_thunk_StandardMemory_vidmemCanCopy; + pThis->__vidmemControl__ = &__nvoc_thunk_Memory_vidmemControl; - pThis->__vidmemIsGpuMapAllowed__ = &__nvoc_thunk_Memory_vidmemIsGpuMapAllowed; + pThis->__vidmemUnmap__ = &__nvoc_thunk_Memory_vidmemUnmap; - pThis->__vidmemControl_Prologue__ = &__nvoc_thunk_RmResource_vidmemControl_Prologue; + pThis->__vidmemGetMemInterMapParams__ = &__nvoc_thunk_Memory_vidmemGetMemInterMapParams; + + pThis->__vidmemGetMemoryMappingDescriptor__ = &__nvoc_thunk_Memory_vidmemGetMemoryMappingDescriptor; + + pThis->__vidmemControlFilter__ = &__nvoc_thunk_RsResource_vidmemControlFilter; + + pThis->__vidmemControlSerialization_Prologue__ = &__nvoc_thunk_RmResource_vidmemControlSerialization_Prologue; + + pThis->__vidmemCanCopy__ = &__nvoc_thunk_StandardMemory_vidmemCanCopy; pThis->__vidmemIsReady__ = &__nvoc_thunk_Memory_vidmemIsReady; @@ -271,11 +287,7 @@ pThis->__vidmemIsDuplicate__ = &__nvoc_thunk_Memory_vidmemIsDuplicate; - pThis->__vidmemUnmapFrom__ = &__nvoc_thunk_RsResource_vidmemUnmapFrom; - - pThis->__vidmemControl_Epilogue__ = &__nvoc_thunk_RmResource_vidmemControl_Epilogue; - - pThis->__vidmemControlLookup__ = &__nvoc_thunk_RsResource_vidmemControlLookup; + pThis->__vidmemControlSerialization_Epilogue__ = &__nvoc_thunk_RmResource_vidmemControlSerialization_Epilogue; pThis->__vidmemMap__ = &__nvoc_thunk_Memory_vidmemMap; @@ -304,13 +316,16 @@ Object *pParentObj; VideoMemory *pThis; - pThis = portMemAllocNonPaged(sizeof(VideoMemory)); - if (pThis == NULL) return NV_ERR_NO_MEMORY; + status = __nvoc_handleObjCreateMemAlloc(createFlags, sizeof(VideoMemory), (void**)&pThis, (void**)ppThis); + if (status != NV_OK) + return status; portMemSet(pThis, 0, sizeof(VideoMemory)); __nvoc_initRtti(staticCast(pThis, Dynamic), &__nvoc_class_def_VideoMemory); + pThis->__nvoc_base_StandardMemory.__nvoc_base_Memory.__nvoc_base_RmResource.__nvoc_base_RsResource.__nvoc_base_Object.createFlags = createFlags; + if (pParent != NULL && !(createFlags & NVOC_OBJ_CREATE_FLAGS_PARENT_HALSPEC_ONLY)) { pParentObj = dynamicCast(pParent, Object); @@ -326,11 +341,17 @@ if (status != NV_OK) goto __nvoc_objCreate_VideoMemory_cleanup; *ppThis = pThis; + return NV_OK; __nvoc_objCreate_VideoMemory_cleanup: // do not call destructors here since the constructor already called them - portMemFree(pThis); + if (createFlags & NVOC_OBJ_CREATE_FLAGS_IN_PLACE_CONSTRUCT) + portMemSet(pThis, 0, sizeof(VideoMemory)); + else + portMemFree(pThis); + + // coverity[leaked_storage:FALSE] return status; } diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/generated/g_video_mem_nvoc.h nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_video_mem_nvoc.h --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/generated/g_video_mem_nvoc.h 2023-10-25 20:27:23.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_video_mem_nvoc.h 2024-03-05 22:18:51.000000000 +0000 @@ -7,7 +7,7 @@ #endif /* - * SPDX-FileCopyrightText: Copyright (c) 2020-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2020-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -38,6 +38,18 @@ #include "gpu/mem_mgr/heap_base.h" typedef struct PMA_ALLOC_INFO PMA_ALLOC_INFO; +struct Device; + +#ifndef __NVOC_CLASS_Device_TYPEDEF__ +#define __NVOC_CLASS_Device_TYPEDEF__ +typedef struct Device Device; +#endif /* __NVOC_CLASS_Device_TYPEDEF__ */ + +#ifndef __nvoc_class_id_Device +#define __nvoc_class_id_Device 0xe0ac20 +#endif /* __nvoc_class_id_Device */ + + #ifdef NVOC_VIDEO_MEM_H_PRIVATE_ACCESS_ALLOWED #define PRIVATE_FIELD(x) x @@ -54,27 +66,29 @@ struct Memory *__nvoc_pbase_Memory; struct StandardMemory *__nvoc_pbase_StandardMemory; struct VideoMemory *__nvoc_pbase_VideoMemory; - NV_STATUS (*__vidmemCheckCopyPermissions__)(struct VideoMemory *, struct OBJGPU *, NvHandle); + NV_STATUS (*__vidmemCheckCopyPermissions__)(struct VideoMemory *, struct OBJGPU *, struct Device *); NV_STATUS (*__vidmemCheckMemInterUnmap__)(struct VideoMemory *, NvBool); + NvBool (*__vidmemShareCallback__)(struct VideoMemory *, struct RsClient *, struct RsResourceRef *, RS_SHARE_POLICY *); + NV_STATUS (*__vidmemMapTo__)(struct VideoMemory *, RS_RES_MAP_TO_PARAMS *); + NV_STATUS (*__vidmemGetMapAddrSpace__)(struct VideoMemory *, CALL_CONTEXT *, NvU32, NV_ADDRESS_SPACE *); + NvU32 (*__vidmemGetRefCount__)(struct VideoMemory *); + void (*__vidmemAddAdditionalDependants__)(struct RsClient *, struct VideoMemory *, RsResourceRef *); + NV_STATUS (*__vidmemControl_Prologue__)(struct VideoMemory *, CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); + NvBool (*__vidmemIsGpuMapAllowed__)(struct VideoMemory *, struct OBJGPU *); + NV_STATUS (*__vidmemUnmapFrom__)(struct VideoMemory *, RS_RES_UNMAP_FROM_PARAMS *); + void (*__vidmemControl_Epilogue__)(struct VideoMemory *, CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); + NV_STATUS (*__vidmemControlLookup__)(struct VideoMemory *, struct RS_RES_CONTROL_PARAMS_INTERNAL *, const struct NVOC_EXPORTED_METHOD_DEF **); NV_STATUS (*__vidmemControl__)(struct VideoMemory *, CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); NV_STATUS (*__vidmemUnmap__)(struct VideoMemory *, CALL_CONTEXT *, RsCpuMapping *); NV_STATUS (*__vidmemGetMemInterMapParams__)(struct VideoMemory *, RMRES_MEM_INTER_MAP_PARAMS *); NV_STATUS (*__vidmemGetMemoryMappingDescriptor__)(struct VideoMemory *, MEMORY_DESCRIPTOR **); - NV_STATUS (*__vidmemGetMapAddrSpace__)(struct VideoMemory *, CALL_CONTEXT *, NvU32, NV_ADDRESS_SPACE *); - NvBool (*__vidmemShareCallback__)(struct VideoMemory *, struct RsClient *, struct RsResourceRef *, RS_SHARE_POLICY *); NV_STATUS (*__vidmemControlFilter__)(struct VideoMemory *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); - void (*__vidmemAddAdditionalDependants__)(struct RsClient *, struct VideoMemory *, RsResourceRef *); - NvU32 (*__vidmemGetRefCount__)(struct VideoMemory *); - NV_STATUS (*__vidmemMapTo__)(struct VideoMemory *, RS_RES_MAP_TO_PARAMS *); + NV_STATUS (*__vidmemControlSerialization_Prologue__)(struct VideoMemory *, CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); NvBool (*__vidmemCanCopy__)(struct VideoMemory *); - NvBool (*__vidmemIsGpuMapAllowed__)(struct VideoMemory *, struct OBJGPU *); - NV_STATUS (*__vidmemControl_Prologue__)(struct VideoMemory *, CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); NV_STATUS (*__vidmemIsReady__)(struct VideoMemory *, NvBool); void (*__vidmemPreDestruct__)(struct VideoMemory *); NV_STATUS (*__vidmemIsDuplicate__)(struct VideoMemory *, NvHandle, NvBool *); - NV_STATUS (*__vidmemUnmapFrom__)(struct VideoMemory *, RS_RES_UNMAP_FROM_PARAMS *); - void (*__vidmemControl_Epilogue__)(struct VideoMemory *, CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); - NV_STATUS (*__vidmemControlLookup__)(struct VideoMemory *, struct RS_RES_CONTROL_PARAMS_INTERNAL *, const struct NVOC_EXPORTED_METHOD_DEF **); + void (*__vidmemControlSerialization_Epilogue__)(struct VideoMemory *, CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); NV_STATUS (*__vidmemMap__)(struct VideoMemory *, CALL_CONTEXT *, struct RS_CPU_MAP_PARAMS *, RsCpuMapping *); NvBool (*__vidmemAccessCallback__)(struct VideoMemory *, struct RsClient *, void *, RsAccessRight); }; @@ -107,89 +121,107 @@ #define __objCreate_VideoMemory(ppNewObj, pParent, createFlags, arg_pCallContext, arg_pParams) \ __nvoc_objCreate_VideoMemory((ppNewObj), staticCast((pParent), Dynamic), (createFlags), arg_pCallContext, arg_pParams) -#define vidmemCheckCopyPermissions(pVideoMemory, pDstGpu, hDstClientNvBool) vidmemCheckCopyPermissions_DISPATCH(pVideoMemory, pDstGpu, hDstClientNvBool) +#define vidmemCheckCopyPermissions(pVideoMemory, pDstGpu, pDstDevice) vidmemCheckCopyPermissions_DISPATCH(pVideoMemory, pDstGpu, pDstDevice) #define vidmemCheckMemInterUnmap(pMemory, bSubdeviceHandleProvided) vidmemCheckMemInterUnmap_DISPATCH(pMemory, bSubdeviceHandleProvided) +#define vidmemShareCallback(pResource, pInvokingClient, pParentRef, pSharePolicy) vidmemShareCallback_DISPATCH(pResource, pInvokingClient, pParentRef, pSharePolicy) +#define vidmemMapTo(pResource, pParams) vidmemMapTo_DISPATCH(pResource, pParams) +#define vidmemGetMapAddrSpace(pMemory, pCallContext, mapFlags, pAddrSpace) vidmemGetMapAddrSpace_DISPATCH(pMemory, pCallContext, mapFlags, pAddrSpace) +#define vidmemGetRefCount(pResource) vidmemGetRefCount_DISPATCH(pResource) +#define vidmemAddAdditionalDependants(pClient, pResource, pReference) vidmemAddAdditionalDependants_DISPATCH(pClient, pResource, pReference) +#define vidmemControl_Prologue(pResource, pCallContext, pParams) vidmemControl_Prologue_DISPATCH(pResource, pCallContext, pParams) +#define vidmemIsGpuMapAllowed(pMemory, pGpu) vidmemIsGpuMapAllowed_DISPATCH(pMemory, pGpu) +#define vidmemUnmapFrom(pResource, pParams) vidmemUnmapFrom_DISPATCH(pResource, pParams) +#define vidmemControl_Epilogue(pResource, pCallContext, pParams) vidmemControl_Epilogue_DISPATCH(pResource, pCallContext, pParams) +#define vidmemControlLookup(pResource, pParams, ppEntry) vidmemControlLookup_DISPATCH(pResource, pParams, ppEntry) #define vidmemControl(pMemory, pCallContext, pParams) vidmemControl_DISPATCH(pMemory, pCallContext, pParams) #define vidmemUnmap(pMemory, pCallContext, pCpuMapping) vidmemUnmap_DISPATCH(pMemory, pCallContext, pCpuMapping) #define vidmemGetMemInterMapParams(pMemory, pParams) vidmemGetMemInterMapParams_DISPATCH(pMemory, pParams) #define vidmemGetMemoryMappingDescriptor(pMemory, ppMemDesc) vidmemGetMemoryMappingDescriptor_DISPATCH(pMemory, ppMemDesc) -#define vidmemGetMapAddrSpace(pMemory, pCallContext, mapFlags, pAddrSpace) vidmemGetMapAddrSpace_DISPATCH(pMemory, pCallContext, mapFlags, pAddrSpace) -#define vidmemShareCallback(pResource, pInvokingClient, pParentRef, pSharePolicy) vidmemShareCallback_DISPATCH(pResource, pInvokingClient, pParentRef, pSharePolicy) #define vidmemControlFilter(pResource, pCallContext, pParams) vidmemControlFilter_DISPATCH(pResource, pCallContext, pParams) -#define vidmemAddAdditionalDependants(pClient, pResource, pReference) vidmemAddAdditionalDependants_DISPATCH(pClient, pResource, pReference) -#define vidmemGetRefCount(pResource) vidmemGetRefCount_DISPATCH(pResource) -#define vidmemMapTo(pResource, pParams) vidmemMapTo_DISPATCH(pResource, pParams) +#define vidmemControlSerialization_Prologue(pResource, pCallContext, pParams) vidmemControlSerialization_Prologue_DISPATCH(pResource, pCallContext, pParams) #define vidmemCanCopy(pStandardMemory) vidmemCanCopy_DISPATCH(pStandardMemory) -#define vidmemIsGpuMapAllowed(pMemory, pGpu) vidmemIsGpuMapAllowed_DISPATCH(pMemory, pGpu) -#define vidmemControl_Prologue(pResource, pCallContext, pParams) vidmemControl_Prologue_DISPATCH(pResource, pCallContext, pParams) #define vidmemIsReady(pMemory, bCopyConstructorContext) vidmemIsReady_DISPATCH(pMemory, bCopyConstructorContext) #define vidmemPreDestruct(pResource) vidmemPreDestruct_DISPATCH(pResource) #define vidmemIsDuplicate(pMemory, hMemory, pDuplicate) vidmemIsDuplicate_DISPATCH(pMemory, hMemory, pDuplicate) -#define vidmemUnmapFrom(pResource, pParams) vidmemUnmapFrom_DISPATCH(pResource, pParams) -#define vidmemControl_Epilogue(pResource, pCallContext, pParams) vidmemControl_Epilogue_DISPATCH(pResource, pCallContext, pParams) -#define vidmemControlLookup(pResource, pParams, ppEntry) vidmemControlLookup_DISPATCH(pResource, pParams, ppEntry) +#define vidmemControlSerialization_Epilogue(pResource, pCallContext, pParams) vidmemControlSerialization_Epilogue_DISPATCH(pResource, pCallContext, pParams) #define vidmemMap(pMemory, pCallContext, pParams, pCpuMapping) vidmemMap_DISPATCH(pMemory, pCallContext, pParams, pCpuMapping) #define vidmemAccessCallback(pResource, pInvokingClient, pAllocParams, accessRight) vidmemAccessCallback_DISPATCH(pResource, pInvokingClient, pAllocParams, accessRight) -NV_STATUS vidmemCheckCopyPermissions_IMPL(struct VideoMemory *pVideoMemory, struct OBJGPU *pDstGpu, NvHandle hDstClientNvBool); +NV_STATUS vidmemCheckCopyPermissions_IMPL(struct VideoMemory *pVideoMemory, struct OBJGPU *pDstGpu, struct Device *pDstDevice); -static inline NV_STATUS vidmemCheckCopyPermissions_DISPATCH(struct VideoMemory *pVideoMemory, struct OBJGPU *pDstGpu, NvHandle hDstClientNvBool) { - return pVideoMemory->__vidmemCheckCopyPermissions__(pVideoMemory, pDstGpu, hDstClientNvBool); +static inline NV_STATUS vidmemCheckCopyPermissions_DISPATCH(struct VideoMemory *pVideoMemory, struct OBJGPU *pDstGpu, struct Device *pDstDevice) { + return pVideoMemory->__vidmemCheckCopyPermissions__(pVideoMemory, pDstGpu, pDstDevice); } static inline NV_STATUS vidmemCheckMemInterUnmap_DISPATCH(struct VideoMemory *pMemory, NvBool bSubdeviceHandleProvided) { return pMemory->__vidmemCheckMemInterUnmap__(pMemory, bSubdeviceHandleProvided); } -static inline NV_STATUS vidmemControl_DISPATCH(struct VideoMemory *pMemory, CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { - return pMemory->__vidmemControl__(pMemory, pCallContext, pParams); +static inline NvBool vidmemShareCallback_DISPATCH(struct VideoMemory *pResource, struct RsClient *pInvokingClient, struct RsResourceRef *pParentRef, RS_SHARE_POLICY *pSharePolicy) { + return pResource->__vidmemShareCallback__(pResource, pInvokingClient, pParentRef, pSharePolicy); } -static inline NV_STATUS vidmemUnmap_DISPATCH(struct VideoMemory *pMemory, CALL_CONTEXT *pCallContext, RsCpuMapping *pCpuMapping) { - return pMemory->__vidmemUnmap__(pMemory, pCallContext, pCpuMapping); +static inline NV_STATUS vidmemMapTo_DISPATCH(struct VideoMemory *pResource, RS_RES_MAP_TO_PARAMS *pParams) { + return pResource->__vidmemMapTo__(pResource, pParams); } -static inline NV_STATUS vidmemGetMemInterMapParams_DISPATCH(struct VideoMemory *pMemory, RMRES_MEM_INTER_MAP_PARAMS *pParams) { - return pMemory->__vidmemGetMemInterMapParams__(pMemory, pParams); +static inline NV_STATUS vidmemGetMapAddrSpace_DISPATCH(struct VideoMemory *pMemory, CALL_CONTEXT *pCallContext, NvU32 mapFlags, NV_ADDRESS_SPACE *pAddrSpace) { + return pMemory->__vidmemGetMapAddrSpace__(pMemory, pCallContext, mapFlags, pAddrSpace); } -static inline NV_STATUS vidmemGetMemoryMappingDescriptor_DISPATCH(struct VideoMemory *pMemory, MEMORY_DESCRIPTOR **ppMemDesc) { - return pMemory->__vidmemGetMemoryMappingDescriptor__(pMemory, ppMemDesc); +static inline NvU32 vidmemGetRefCount_DISPATCH(struct VideoMemory *pResource) { + return pResource->__vidmemGetRefCount__(pResource); } -static inline NV_STATUS vidmemGetMapAddrSpace_DISPATCH(struct VideoMemory *pMemory, CALL_CONTEXT *pCallContext, NvU32 mapFlags, NV_ADDRESS_SPACE *pAddrSpace) { - return pMemory->__vidmemGetMapAddrSpace__(pMemory, pCallContext, mapFlags, pAddrSpace); +static inline void vidmemAddAdditionalDependants_DISPATCH(struct RsClient *pClient, struct VideoMemory *pResource, RsResourceRef *pReference) { + pResource->__vidmemAddAdditionalDependants__(pClient, pResource, pReference); } -static inline NvBool vidmemShareCallback_DISPATCH(struct VideoMemory *pResource, struct RsClient *pInvokingClient, struct RsResourceRef *pParentRef, RS_SHARE_POLICY *pSharePolicy) { - return pResource->__vidmemShareCallback__(pResource, pInvokingClient, pParentRef, pSharePolicy); +static inline NV_STATUS vidmemControl_Prologue_DISPATCH(struct VideoMemory *pResource, CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return pResource->__vidmemControl_Prologue__(pResource, pCallContext, pParams); } -static inline NV_STATUS vidmemControlFilter_DISPATCH(struct VideoMemory *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { - return pResource->__vidmemControlFilter__(pResource, pCallContext, pParams); +static inline NvBool vidmemIsGpuMapAllowed_DISPATCH(struct VideoMemory *pMemory, struct OBJGPU *pGpu) { + return pMemory->__vidmemIsGpuMapAllowed__(pMemory, pGpu); } -static inline void vidmemAddAdditionalDependants_DISPATCH(struct RsClient *pClient, struct VideoMemory *pResource, RsResourceRef *pReference) { - pResource->__vidmemAddAdditionalDependants__(pClient, pResource, pReference); +static inline NV_STATUS vidmemUnmapFrom_DISPATCH(struct VideoMemory *pResource, RS_RES_UNMAP_FROM_PARAMS *pParams) { + return pResource->__vidmemUnmapFrom__(pResource, pParams); } -static inline NvU32 vidmemGetRefCount_DISPATCH(struct VideoMemory *pResource) { - return pResource->__vidmemGetRefCount__(pResource); +static inline void vidmemControl_Epilogue_DISPATCH(struct VideoMemory *pResource, CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + pResource->__vidmemControl_Epilogue__(pResource, pCallContext, pParams); } -static inline NV_STATUS vidmemMapTo_DISPATCH(struct VideoMemory *pResource, RS_RES_MAP_TO_PARAMS *pParams) { - return pResource->__vidmemMapTo__(pResource, pParams); +static inline NV_STATUS vidmemControlLookup_DISPATCH(struct VideoMemory *pResource, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams, const struct NVOC_EXPORTED_METHOD_DEF **ppEntry) { + return pResource->__vidmemControlLookup__(pResource, pParams, ppEntry); } -static inline NvBool vidmemCanCopy_DISPATCH(struct VideoMemory *pStandardMemory) { - return pStandardMemory->__vidmemCanCopy__(pStandardMemory); +static inline NV_STATUS vidmemControl_DISPATCH(struct VideoMemory *pMemory, CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return pMemory->__vidmemControl__(pMemory, pCallContext, pParams); } -static inline NvBool vidmemIsGpuMapAllowed_DISPATCH(struct VideoMemory *pMemory, struct OBJGPU *pGpu) { - return pMemory->__vidmemIsGpuMapAllowed__(pMemory, pGpu); +static inline NV_STATUS vidmemUnmap_DISPATCH(struct VideoMemory *pMemory, CALL_CONTEXT *pCallContext, RsCpuMapping *pCpuMapping) { + return pMemory->__vidmemUnmap__(pMemory, pCallContext, pCpuMapping); } -static inline NV_STATUS vidmemControl_Prologue_DISPATCH(struct VideoMemory *pResource, CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { - return pResource->__vidmemControl_Prologue__(pResource, pCallContext, pParams); +static inline NV_STATUS vidmemGetMemInterMapParams_DISPATCH(struct VideoMemory *pMemory, RMRES_MEM_INTER_MAP_PARAMS *pParams) { + return pMemory->__vidmemGetMemInterMapParams__(pMemory, pParams); +} + +static inline NV_STATUS vidmemGetMemoryMappingDescriptor_DISPATCH(struct VideoMemory *pMemory, MEMORY_DESCRIPTOR **ppMemDesc) { + return pMemory->__vidmemGetMemoryMappingDescriptor__(pMemory, ppMemDesc); +} + +static inline NV_STATUS vidmemControlFilter_DISPATCH(struct VideoMemory *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return pResource->__vidmemControlFilter__(pResource, pCallContext, pParams); +} + +static inline NV_STATUS vidmemControlSerialization_Prologue_DISPATCH(struct VideoMemory *pResource, CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return pResource->__vidmemControlSerialization_Prologue__(pResource, pCallContext, pParams); +} + +static inline NvBool vidmemCanCopy_DISPATCH(struct VideoMemory *pStandardMemory) { + return pStandardMemory->__vidmemCanCopy__(pStandardMemory); } static inline NV_STATUS vidmemIsReady_DISPATCH(struct VideoMemory *pMemory, NvBool bCopyConstructorContext) { @@ -204,16 +236,8 @@ return pMemory->__vidmemIsDuplicate__(pMemory, hMemory, pDuplicate); } -static inline NV_STATUS vidmemUnmapFrom_DISPATCH(struct VideoMemory *pResource, RS_RES_UNMAP_FROM_PARAMS *pParams) { - return pResource->__vidmemUnmapFrom__(pResource, pParams); -} - -static inline void vidmemControl_Epilogue_DISPATCH(struct VideoMemory *pResource, CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { - pResource->__vidmemControl_Epilogue__(pResource, pCallContext, pParams); -} - -static inline NV_STATUS vidmemControlLookup_DISPATCH(struct VideoMemory *pResource, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams, const struct NVOC_EXPORTED_METHOD_DEF **ppEntry) { - return pResource->__vidmemControlLookup__(pResource, pParams, ppEntry); +static inline void vidmemControlSerialization_Epilogue_DISPATCH(struct VideoMemory *pResource, CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + pResource->__vidmemControlSerialization_Epilogue__(pResource, pCallContext, pParams); } static inline NV_STATUS vidmemMap_DISPATCH(struct VideoMemory *pMemory, CALL_CONTEXT *pCallContext, struct RS_CPU_MAP_PARAMS *pParams, RsCpuMapping *pCpuMapping) { @@ -230,9 +254,9 @@ void vidmemDestruct_IMPL(struct VideoMemory *pVideoMemory); #define __nvoc_vidmemDestruct(pVideoMemory) vidmemDestruct_IMPL(pVideoMemory) -struct Heap *vidmemGetHeap_IMPL(struct OBJGPU *pGpu, NvHandle hClient, NvBool bSubheap); +struct Heap *vidmemGetHeap_IMPL(struct OBJGPU *pGpu, struct Device *pDevice, NvBool bSubheap); -#define vidmemGetHeap(pGpu, hClient, bSubheap) vidmemGetHeap_IMPL(pGpu, hClient, bSubheap) +#define vidmemGetHeap(pGpu, pDevice, bSubheap) vidmemGetHeap_IMPL(pGpu, pDevice, bSubheap) #undef PRIVATE_FIELD diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/generated/g_vidmem_access_bit_buffer_nvoc.c nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_vidmem_access_bit_buffer_nvoc.c --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/generated/g_vidmem_access_bit_buffer_nvoc.c 1970-01-01 00:00:00.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_vidmem_access_bit_buffer_nvoc.c 2024-03-05 22:18:51.000000000 +0000 @@ -0,0 +1,457 @@ +#define NVOC_VIDMEM_ACCESS_BIT_BUFFER_H_PRIVATE_ACCESS_ALLOWED +#include "nvoc/runtime.h" +#include "nvoc/rtti.h" +#include "nvtypes.h" +#include "nvport/nvport.h" +#include "nvport/inline/util_valist.h" +#include "utils/nvassert.h" +#include "g_vidmem_access_bit_buffer_nvoc.h" + +#ifdef DEBUG +char __nvoc_class_id_uniqueness_check_0xebb6da = 1; +#endif + +extern const struct NVOC_CLASS_DEF __nvoc_class_def_VidmemAccessBitBuffer; + +extern const struct NVOC_CLASS_DEF __nvoc_class_def_Object; + +extern const struct NVOC_CLASS_DEF __nvoc_class_def_RsResource; + +extern const struct NVOC_CLASS_DEF __nvoc_class_def_RmResourceCommon; + +extern const struct NVOC_CLASS_DEF __nvoc_class_def_RmResource; + +extern const struct NVOC_CLASS_DEF __nvoc_class_def_GpuResource; + +extern const struct NVOC_CLASS_DEF __nvoc_class_def_INotifier; + +extern const struct NVOC_CLASS_DEF __nvoc_class_def_Notifier; + +void __nvoc_init_VidmemAccessBitBuffer(VidmemAccessBitBuffer*, RmHalspecOwner* ); +void __nvoc_init_funcTable_VidmemAccessBitBuffer(VidmemAccessBitBuffer*, RmHalspecOwner* ); +NV_STATUS __nvoc_ctor_VidmemAccessBitBuffer(VidmemAccessBitBuffer*, RmHalspecOwner* , CALL_CONTEXT * arg_pCallContext, struct RS_RES_ALLOC_PARAMS_INTERNAL * arg_pParams); +void __nvoc_init_dataField_VidmemAccessBitBuffer(VidmemAccessBitBuffer*, RmHalspecOwner* ); +void __nvoc_dtor_VidmemAccessBitBuffer(VidmemAccessBitBuffer*); +extern const struct NVOC_EXPORT_INFO __nvoc_export_info_VidmemAccessBitBuffer; + +static const struct NVOC_RTTI __nvoc_rtti_VidmemAccessBitBuffer_VidmemAccessBitBuffer = { + /*pClassDef=*/ &__nvoc_class_def_VidmemAccessBitBuffer, + /*dtor=*/ (NVOC_DYNAMIC_DTOR) &__nvoc_dtor_VidmemAccessBitBuffer, + /*offset=*/ 0, +}; + +static const struct NVOC_RTTI __nvoc_rtti_VidmemAccessBitBuffer_Object = { + /*pClassDef=*/ &__nvoc_class_def_Object, + /*dtor=*/ &__nvoc_destructFromBase, + /*offset=*/ NV_OFFSETOF(VidmemAccessBitBuffer, __nvoc_base_GpuResource.__nvoc_base_RmResource.__nvoc_base_RsResource.__nvoc_base_Object), +}; + +static const struct NVOC_RTTI __nvoc_rtti_VidmemAccessBitBuffer_RsResource = { + /*pClassDef=*/ &__nvoc_class_def_RsResource, + /*dtor=*/ &__nvoc_destructFromBase, + /*offset=*/ NV_OFFSETOF(VidmemAccessBitBuffer, __nvoc_base_GpuResource.__nvoc_base_RmResource.__nvoc_base_RsResource), +}; + +static const struct NVOC_RTTI __nvoc_rtti_VidmemAccessBitBuffer_RmResourceCommon = { + /*pClassDef=*/ &__nvoc_class_def_RmResourceCommon, + /*dtor=*/ &__nvoc_destructFromBase, + /*offset=*/ NV_OFFSETOF(VidmemAccessBitBuffer, __nvoc_base_GpuResource.__nvoc_base_RmResource.__nvoc_base_RmResourceCommon), +}; + +static const struct NVOC_RTTI __nvoc_rtti_VidmemAccessBitBuffer_RmResource = { + /*pClassDef=*/ &__nvoc_class_def_RmResource, + /*dtor=*/ &__nvoc_destructFromBase, + /*offset=*/ NV_OFFSETOF(VidmemAccessBitBuffer, __nvoc_base_GpuResource.__nvoc_base_RmResource), +}; + +static const struct NVOC_RTTI __nvoc_rtti_VidmemAccessBitBuffer_GpuResource = { + /*pClassDef=*/ &__nvoc_class_def_GpuResource, + /*dtor=*/ &__nvoc_destructFromBase, + /*offset=*/ NV_OFFSETOF(VidmemAccessBitBuffer, __nvoc_base_GpuResource), +}; + +static const struct NVOC_RTTI __nvoc_rtti_VidmemAccessBitBuffer_INotifier = { + /*pClassDef=*/ &__nvoc_class_def_INotifier, + /*dtor=*/ &__nvoc_destructFromBase, + /*offset=*/ NV_OFFSETOF(VidmemAccessBitBuffer, __nvoc_base_Notifier.__nvoc_base_INotifier), +}; + +static const struct NVOC_RTTI __nvoc_rtti_VidmemAccessBitBuffer_Notifier = { + /*pClassDef=*/ &__nvoc_class_def_Notifier, + /*dtor=*/ &__nvoc_destructFromBase, + /*offset=*/ NV_OFFSETOF(VidmemAccessBitBuffer, __nvoc_base_Notifier), +}; + +static const struct NVOC_CASTINFO __nvoc_castinfo_VidmemAccessBitBuffer = { + /*numRelatives=*/ 8, + /*relatives=*/ { + &__nvoc_rtti_VidmemAccessBitBuffer_VidmemAccessBitBuffer, + &__nvoc_rtti_VidmemAccessBitBuffer_Notifier, + &__nvoc_rtti_VidmemAccessBitBuffer_INotifier, + &__nvoc_rtti_VidmemAccessBitBuffer_GpuResource, + &__nvoc_rtti_VidmemAccessBitBuffer_RmResource, + &__nvoc_rtti_VidmemAccessBitBuffer_RmResourceCommon, + &__nvoc_rtti_VidmemAccessBitBuffer_RsResource, + &__nvoc_rtti_VidmemAccessBitBuffer_Object, + }, +}; + +const struct NVOC_CLASS_DEF __nvoc_class_def_VidmemAccessBitBuffer = +{ + /*classInfo=*/ { + /*size=*/ sizeof(VidmemAccessBitBuffer), + /*classId=*/ classId(VidmemAccessBitBuffer), + /*providerId=*/ &__nvoc_rtti_provider, +#if NV_PRINTF_STRINGS_ALLOWED + /*name=*/ "VidmemAccessBitBuffer", +#endif + }, + /*objCreatefn=*/ (NVOC_DYNAMIC_OBJ_CREATE) &__nvoc_objCreateDynamic_VidmemAccessBitBuffer, + /*pCastInfo=*/ &__nvoc_castinfo_VidmemAccessBitBuffer, + /*pExportInfo=*/ &__nvoc_export_info_VidmemAccessBitBuffer +}; + +static NvBool __nvoc_thunk_GpuResource_vidmemAccessBitBufShareCallback(struct VidmemAccessBitBuffer *pGpuResource, struct RsClient *pInvokingClient, struct RsResourceRef *pParentRef, RS_SHARE_POLICY *pSharePolicy) { + return gpuresShareCallback((struct GpuResource *)(((unsigned char *)pGpuResource) + __nvoc_rtti_VidmemAccessBitBuffer_GpuResource.offset), pInvokingClient, pParentRef, pSharePolicy); +} + +static NV_STATUS __nvoc_thunk_RmResource_vidmemAccessBitBufCheckMemInterUnmap(struct VidmemAccessBitBuffer *pRmResource, NvBool bSubdeviceHandleProvided) { + return rmresCheckMemInterUnmap((struct RmResource *)(((unsigned char *)pRmResource) + __nvoc_rtti_VidmemAccessBitBuffer_RmResource.offset), bSubdeviceHandleProvided); +} + +static NV_STATUS __nvoc_thunk_Notifier_vidmemAccessBitBufGetOrAllocNotifShare(struct VidmemAccessBitBuffer *pNotifier, NvHandle hNotifierClient, NvHandle hNotifierResource, struct NotifShare **ppNotifShare) { + return notifyGetOrAllocNotifShare((struct Notifier *)(((unsigned char *)pNotifier) + __nvoc_rtti_VidmemAccessBitBuffer_Notifier.offset), hNotifierClient, hNotifierResource, ppNotifShare); +} + +static NV_STATUS __nvoc_thunk_RsResource_vidmemAccessBitBufMapTo(struct VidmemAccessBitBuffer *pResource, RS_RES_MAP_TO_PARAMS *pParams) { + return resMapTo((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_VidmemAccessBitBuffer_RsResource.offset), pParams); +} + +static NV_STATUS __nvoc_thunk_GpuResource_vidmemAccessBitBufGetMapAddrSpace(struct VidmemAccessBitBuffer *pGpuResource, CALL_CONTEXT *pCallContext, NvU32 mapFlags, NV_ADDRESS_SPACE *pAddrSpace) { + return gpuresGetMapAddrSpace((struct GpuResource *)(((unsigned char *)pGpuResource) + __nvoc_rtti_VidmemAccessBitBuffer_GpuResource.offset), pCallContext, mapFlags, pAddrSpace); +} + +static void __nvoc_thunk_Notifier_vidmemAccessBitBufSetNotificationShare(struct VidmemAccessBitBuffer *pNotifier, struct NotifShare *pNotifShare) { + notifySetNotificationShare((struct Notifier *)(((unsigned char *)pNotifier) + __nvoc_rtti_VidmemAccessBitBuffer_Notifier.offset), pNotifShare); +} + +static NvU32 __nvoc_thunk_RsResource_vidmemAccessBitBufGetRefCount(struct VidmemAccessBitBuffer *pResource) { + return resGetRefCount((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_VidmemAccessBitBuffer_RsResource.offset)); +} + +static void __nvoc_thunk_RsResource_vidmemAccessBitBufAddAdditionalDependants(struct RsClient *pClient, struct VidmemAccessBitBuffer *pResource, RsResourceRef *pReference) { + resAddAdditionalDependants(pClient, (struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_VidmemAccessBitBuffer_RsResource.offset), pReference); +} + +static NV_STATUS __nvoc_thunk_RmResource_vidmemAccessBitBufControl_Prologue(struct VidmemAccessBitBuffer *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return rmresControl_Prologue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_VidmemAccessBitBuffer_RmResource.offset), pCallContext, pParams); +} + +static NV_STATUS __nvoc_thunk_GpuResource_vidmemAccessBitBufGetRegBaseOffsetAndSize(struct VidmemAccessBitBuffer *pGpuResource, struct OBJGPU *pGpu, NvU32 *pOffset, NvU32 *pSize) { + return gpuresGetRegBaseOffsetAndSize((struct GpuResource *)(((unsigned char *)pGpuResource) + __nvoc_rtti_VidmemAccessBitBuffer_GpuResource.offset), pGpu, pOffset, pSize); +} + +static NV_STATUS __nvoc_thunk_GpuResource_vidmemAccessBitBufInternalControlForward(struct VidmemAccessBitBuffer *pGpuResource, NvU32 command, void *pParams, NvU32 size) { + return gpuresInternalControlForward((struct GpuResource *)(((unsigned char *)pGpuResource) + __nvoc_rtti_VidmemAccessBitBuffer_GpuResource.offset), command, pParams, size); +} + +static NV_STATUS __nvoc_thunk_RsResource_vidmemAccessBitBufUnmapFrom(struct VidmemAccessBitBuffer *pResource, RS_RES_UNMAP_FROM_PARAMS *pParams) { + return resUnmapFrom((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_VidmemAccessBitBuffer_RsResource.offset), pParams); +} + +static void __nvoc_thunk_RmResource_vidmemAccessBitBufControl_Epilogue(struct VidmemAccessBitBuffer *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + rmresControl_Epilogue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_VidmemAccessBitBuffer_RmResource.offset), pCallContext, pParams); +} + +static NV_STATUS __nvoc_thunk_RsResource_vidmemAccessBitBufControlLookup(struct VidmemAccessBitBuffer *pResource, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams, const struct NVOC_EXPORTED_METHOD_DEF **ppEntry) { + return resControlLookup((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_VidmemAccessBitBuffer_RsResource.offset), pParams, ppEntry); +} + +static NvHandle __nvoc_thunk_GpuResource_vidmemAccessBitBufGetInternalObjectHandle(struct VidmemAccessBitBuffer *pGpuResource) { + return gpuresGetInternalObjectHandle((struct GpuResource *)(((unsigned char *)pGpuResource) + __nvoc_rtti_VidmemAccessBitBuffer_GpuResource.offset)); +} + +static NV_STATUS __nvoc_thunk_GpuResource_vidmemAccessBitBufControl(struct VidmemAccessBitBuffer *pGpuResource, CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return gpuresControl((struct GpuResource *)(((unsigned char *)pGpuResource) + __nvoc_rtti_VidmemAccessBitBuffer_GpuResource.offset), pCallContext, pParams); +} + +static NV_STATUS __nvoc_thunk_GpuResource_vidmemAccessBitBufUnmap(struct VidmemAccessBitBuffer *pGpuResource, CALL_CONTEXT *pCallContext, RsCpuMapping *pCpuMapping) { + return gpuresUnmap((struct GpuResource *)(((unsigned char *)pGpuResource) + __nvoc_rtti_VidmemAccessBitBuffer_GpuResource.offset), pCallContext, pCpuMapping); +} + +static NV_STATUS __nvoc_thunk_RmResource_vidmemAccessBitBufGetMemInterMapParams(struct VidmemAccessBitBuffer *pRmResource, RMRES_MEM_INTER_MAP_PARAMS *pParams) { + return rmresGetMemInterMapParams((struct RmResource *)(((unsigned char *)pRmResource) + __nvoc_rtti_VidmemAccessBitBuffer_RmResource.offset), pParams); +} + +static NV_STATUS __nvoc_thunk_RmResource_vidmemAccessBitBufGetMemoryMappingDescriptor(struct VidmemAccessBitBuffer *pRmResource, struct MEMORY_DESCRIPTOR **ppMemDesc) { + return rmresGetMemoryMappingDescriptor((struct RmResource *)(((unsigned char *)pRmResource) + __nvoc_rtti_VidmemAccessBitBuffer_RmResource.offset), ppMemDesc); +} + +static NV_STATUS __nvoc_thunk_RsResource_vidmemAccessBitBufControlFilter(struct VidmemAccessBitBuffer *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return resControlFilter((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_VidmemAccessBitBuffer_RsResource.offset), pCallContext, pParams); +} + +static NV_STATUS __nvoc_thunk_Notifier_vidmemAccessBitBufUnregisterEvent(struct VidmemAccessBitBuffer *pNotifier, NvHandle hNotifierClient, NvHandle hNotifierResource, NvHandle hEventClient, NvHandle hEvent) { + return notifyUnregisterEvent((struct Notifier *)(((unsigned char *)pNotifier) + __nvoc_rtti_VidmemAccessBitBuffer_Notifier.offset), hNotifierClient, hNotifierResource, hEventClient, hEvent); +} + +static NV_STATUS __nvoc_thunk_RmResource_vidmemAccessBitBufControlSerialization_Prologue(struct VidmemAccessBitBuffer *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return rmresControlSerialization_Prologue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_VidmemAccessBitBuffer_RmResource.offset), pCallContext, pParams); +} + +static NvBool __nvoc_thunk_RsResource_vidmemAccessBitBufCanCopy(struct VidmemAccessBitBuffer *pResource) { + return resCanCopy((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_VidmemAccessBitBuffer_RsResource.offset)); +} + +static void __nvoc_thunk_RsResource_vidmemAccessBitBufPreDestruct(struct VidmemAccessBitBuffer *pResource) { + resPreDestruct((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_VidmemAccessBitBuffer_RsResource.offset)); +} + +static NV_STATUS __nvoc_thunk_RsResource_vidmemAccessBitBufIsDuplicate(struct VidmemAccessBitBuffer *pResource, NvHandle hMemory, NvBool *pDuplicate) { + return resIsDuplicate((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_VidmemAccessBitBuffer_RsResource.offset), hMemory, pDuplicate); +} + +static void __nvoc_thunk_RmResource_vidmemAccessBitBufControlSerialization_Epilogue(struct VidmemAccessBitBuffer *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + rmresControlSerialization_Epilogue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_VidmemAccessBitBuffer_RmResource.offset), pCallContext, pParams); +} + +static PEVENTNOTIFICATION *__nvoc_thunk_Notifier_vidmemAccessBitBufGetNotificationListPtr(struct VidmemAccessBitBuffer *pNotifier) { + return notifyGetNotificationListPtr((struct Notifier *)(((unsigned char *)pNotifier) + __nvoc_rtti_VidmemAccessBitBuffer_Notifier.offset)); +} + +static struct NotifShare *__nvoc_thunk_Notifier_vidmemAccessBitBufGetNotificationShare(struct VidmemAccessBitBuffer *pNotifier) { + return notifyGetNotificationShare((struct Notifier *)(((unsigned char *)pNotifier) + __nvoc_rtti_VidmemAccessBitBuffer_Notifier.offset)); +} + +static NV_STATUS __nvoc_thunk_GpuResource_vidmemAccessBitBufMap(struct VidmemAccessBitBuffer *pGpuResource, CALL_CONTEXT *pCallContext, struct RS_CPU_MAP_PARAMS *pParams, RsCpuMapping *pCpuMapping) { + return gpuresMap((struct GpuResource *)(((unsigned char *)pGpuResource) + __nvoc_rtti_VidmemAccessBitBuffer_GpuResource.offset), pCallContext, pParams, pCpuMapping); +} + +static NvBool __nvoc_thunk_RmResource_vidmemAccessBitBufAccessCallback(struct VidmemAccessBitBuffer *pResource, struct RsClient *pInvokingClient, void *pAllocParams, RsAccessRight accessRight) { + return rmresAccessCallback((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_VidmemAccessBitBuffer_RmResource.offset), pInvokingClient, pAllocParams, accessRight); +} + +#if !defined(NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG) +#define NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(x) (0) +#endif + +static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_VidmemAccessBitBuffer[] = +{ + { /* [0] */ +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x160200u) + /*pFunc=*/ (void (*)(void)) NULL, +#else + /*pFunc=*/ (void (*)(void)) vidmemAccessBitBufCtrlCmdVidmemAccessBitDump_IMPL, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x160200u) + /*flags=*/ 0x160200u, + /*accessRight=*/0x0u, + /*methodId=*/ 0xc7630103u, + /*paramSize=*/ sizeof(NVC763_CTRL_VIDMEM_ACCESS_BIT_BUFFER_DUMP_PARAMS), + /*pClassInfo=*/ &(__nvoc_class_def_VidmemAccessBitBuffer.classInfo), +#if NV_PRINTF_STRINGS_ALLOWED + /*func=*/ "vidmemAccessBitBufCtrlCmdVidmemAccessBitDump" +#endif + }, + +}; + +const struct NVOC_EXPORT_INFO __nvoc_export_info_VidmemAccessBitBuffer = +{ + /*numEntries=*/ 1, + /*pExportEntries=*/ __nvoc_exported_method_def_VidmemAccessBitBuffer +}; + +void __nvoc_dtor_GpuResource(GpuResource*); +void __nvoc_dtor_Notifier(Notifier*); +void __nvoc_dtor_VidmemAccessBitBuffer(VidmemAccessBitBuffer *pThis) { + __nvoc_vidmemAccessBitBufDestruct(pThis); + __nvoc_dtor_GpuResource(&pThis->__nvoc_base_GpuResource); + __nvoc_dtor_Notifier(&pThis->__nvoc_base_Notifier); + PORT_UNREFERENCED_VARIABLE(pThis); +} + +void __nvoc_init_dataField_VidmemAccessBitBuffer(VidmemAccessBitBuffer *pThis, RmHalspecOwner *pRmhalspecowner) { + RmVariantHal *rmVariantHal = &pRmhalspecowner->rmVariantHal; + const unsigned long rmVariantHal_HalVarIdx = (unsigned long)rmVariantHal->__nvoc_HalVarIdx; + PORT_UNREFERENCED_VARIABLE(pThis); + PORT_UNREFERENCED_VARIABLE(pRmhalspecowner); + PORT_UNREFERENCED_VARIABLE(rmVariantHal); + PORT_UNREFERENCED_VARIABLE(rmVariantHal_HalVarIdx); +} + +NV_STATUS __nvoc_ctor_GpuResource(GpuResource* , CALL_CONTEXT *, struct RS_RES_ALLOC_PARAMS_INTERNAL *); +NV_STATUS __nvoc_ctor_Notifier(Notifier* , CALL_CONTEXT *); +NV_STATUS __nvoc_ctor_VidmemAccessBitBuffer(VidmemAccessBitBuffer *pThis, RmHalspecOwner *pRmhalspecowner, CALL_CONTEXT * arg_pCallContext, struct RS_RES_ALLOC_PARAMS_INTERNAL * arg_pParams) { + NV_STATUS status = NV_OK; + status = __nvoc_ctor_GpuResource(&pThis->__nvoc_base_GpuResource, arg_pCallContext, arg_pParams); + if (status != NV_OK) goto __nvoc_ctor_VidmemAccessBitBuffer_fail_GpuResource; + status = __nvoc_ctor_Notifier(&pThis->__nvoc_base_Notifier, arg_pCallContext); + if (status != NV_OK) goto __nvoc_ctor_VidmemAccessBitBuffer_fail_Notifier; + __nvoc_init_dataField_VidmemAccessBitBuffer(pThis, pRmhalspecowner); + + status = __nvoc_vidmemAccessBitBufConstruct(pThis, arg_pCallContext, arg_pParams); + if (status != NV_OK) goto __nvoc_ctor_VidmemAccessBitBuffer_fail__init; + goto __nvoc_ctor_VidmemAccessBitBuffer_exit; // Success + +__nvoc_ctor_VidmemAccessBitBuffer_fail__init: + __nvoc_dtor_Notifier(&pThis->__nvoc_base_Notifier); +__nvoc_ctor_VidmemAccessBitBuffer_fail_Notifier: + __nvoc_dtor_GpuResource(&pThis->__nvoc_base_GpuResource); +__nvoc_ctor_VidmemAccessBitBuffer_fail_GpuResource: +__nvoc_ctor_VidmemAccessBitBuffer_exit: + + return status; +} + +static void __nvoc_init_funcTable_VidmemAccessBitBuffer_1(VidmemAccessBitBuffer *pThis, RmHalspecOwner *pRmhalspecowner) { + RmVariantHal *rmVariantHal = &pRmhalspecowner->rmVariantHal; + const unsigned long rmVariantHal_HalVarIdx = (unsigned long)rmVariantHal->__nvoc_HalVarIdx; + PORT_UNREFERENCED_VARIABLE(pThis); + PORT_UNREFERENCED_VARIABLE(pRmhalspecowner); + PORT_UNREFERENCED_VARIABLE(rmVariantHal); + PORT_UNREFERENCED_VARIABLE(rmVariantHal_HalVarIdx); + +#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x160200u) + pThis->__vidmemAccessBitBufCtrlCmdVidmemAccessBitDump__ = &vidmemAccessBitBufCtrlCmdVidmemAccessBitDump_IMPL; +#endif + + pThis->__vidmemAccessBitBufShareCallback__ = &__nvoc_thunk_GpuResource_vidmemAccessBitBufShareCallback; + + pThis->__vidmemAccessBitBufCheckMemInterUnmap__ = &__nvoc_thunk_RmResource_vidmemAccessBitBufCheckMemInterUnmap; + + pThis->__vidmemAccessBitBufGetOrAllocNotifShare__ = &__nvoc_thunk_Notifier_vidmemAccessBitBufGetOrAllocNotifShare; + + pThis->__vidmemAccessBitBufMapTo__ = &__nvoc_thunk_RsResource_vidmemAccessBitBufMapTo; + + pThis->__vidmemAccessBitBufGetMapAddrSpace__ = &__nvoc_thunk_GpuResource_vidmemAccessBitBufGetMapAddrSpace; + + pThis->__vidmemAccessBitBufSetNotificationShare__ = &__nvoc_thunk_Notifier_vidmemAccessBitBufSetNotificationShare; + + pThis->__vidmemAccessBitBufGetRefCount__ = &__nvoc_thunk_RsResource_vidmemAccessBitBufGetRefCount; + + pThis->__vidmemAccessBitBufAddAdditionalDependants__ = &__nvoc_thunk_RsResource_vidmemAccessBitBufAddAdditionalDependants; + + pThis->__vidmemAccessBitBufControl_Prologue__ = &__nvoc_thunk_RmResource_vidmemAccessBitBufControl_Prologue; + + pThis->__vidmemAccessBitBufGetRegBaseOffsetAndSize__ = &__nvoc_thunk_GpuResource_vidmemAccessBitBufGetRegBaseOffsetAndSize; + + pThis->__vidmemAccessBitBufInternalControlForward__ = &__nvoc_thunk_GpuResource_vidmemAccessBitBufInternalControlForward; + + pThis->__vidmemAccessBitBufUnmapFrom__ = &__nvoc_thunk_RsResource_vidmemAccessBitBufUnmapFrom; + + pThis->__vidmemAccessBitBufControl_Epilogue__ = &__nvoc_thunk_RmResource_vidmemAccessBitBufControl_Epilogue; + + pThis->__vidmemAccessBitBufControlLookup__ = &__nvoc_thunk_RsResource_vidmemAccessBitBufControlLookup; + + pThis->__vidmemAccessBitBufGetInternalObjectHandle__ = &__nvoc_thunk_GpuResource_vidmemAccessBitBufGetInternalObjectHandle; + + pThis->__vidmemAccessBitBufControl__ = &__nvoc_thunk_GpuResource_vidmemAccessBitBufControl; + + pThis->__vidmemAccessBitBufUnmap__ = &__nvoc_thunk_GpuResource_vidmemAccessBitBufUnmap; + + pThis->__vidmemAccessBitBufGetMemInterMapParams__ = &__nvoc_thunk_RmResource_vidmemAccessBitBufGetMemInterMapParams; + + pThis->__vidmemAccessBitBufGetMemoryMappingDescriptor__ = &__nvoc_thunk_RmResource_vidmemAccessBitBufGetMemoryMappingDescriptor; + + pThis->__vidmemAccessBitBufControlFilter__ = &__nvoc_thunk_RsResource_vidmemAccessBitBufControlFilter; + + pThis->__vidmemAccessBitBufUnregisterEvent__ = &__nvoc_thunk_Notifier_vidmemAccessBitBufUnregisterEvent; + + pThis->__vidmemAccessBitBufControlSerialization_Prologue__ = &__nvoc_thunk_RmResource_vidmemAccessBitBufControlSerialization_Prologue; + + pThis->__vidmemAccessBitBufCanCopy__ = &__nvoc_thunk_RsResource_vidmemAccessBitBufCanCopy; + + pThis->__vidmemAccessBitBufPreDestruct__ = &__nvoc_thunk_RsResource_vidmemAccessBitBufPreDestruct; + + pThis->__vidmemAccessBitBufIsDuplicate__ = &__nvoc_thunk_RsResource_vidmemAccessBitBufIsDuplicate; + + pThis->__vidmemAccessBitBufControlSerialization_Epilogue__ = &__nvoc_thunk_RmResource_vidmemAccessBitBufControlSerialization_Epilogue; + + pThis->__vidmemAccessBitBufGetNotificationListPtr__ = &__nvoc_thunk_Notifier_vidmemAccessBitBufGetNotificationListPtr; + + pThis->__vidmemAccessBitBufGetNotificationShare__ = &__nvoc_thunk_Notifier_vidmemAccessBitBufGetNotificationShare; + + pThis->__vidmemAccessBitBufMap__ = &__nvoc_thunk_GpuResource_vidmemAccessBitBufMap; + + pThis->__vidmemAccessBitBufAccessCallback__ = &__nvoc_thunk_RmResource_vidmemAccessBitBufAccessCallback; +} + +void __nvoc_init_funcTable_VidmemAccessBitBuffer(VidmemAccessBitBuffer *pThis, RmHalspecOwner *pRmhalspecowner) { + __nvoc_init_funcTable_VidmemAccessBitBuffer_1(pThis, pRmhalspecowner); +} + +void __nvoc_init_GpuResource(GpuResource*); +void __nvoc_init_Notifier(Notifier*); +void __nvoc_init_VidmemAccessBitBuffer(VidmemAccessBitBuffer *pThis, RmHalspecOwner *pRmhalspecowner) { + pThis->__nvoc_pbase_VidmemAccessBitBuffer = pThis; + pThis->__nvoc_pbase_Object = &pThis->__nvoc_base_GpuResource.__nvoc_base_RmResource.__nvoc_base_RsResource.__nvoc_base_Object; + pThis->__nvoc_pbase_RsResource = &pThis->__nvoc_base_GpuResource.__nvoc_base_RmResource.__nvoc_base_RsResource; + pThis->__nvoc_pbase_RmResourceCommon = &pThis->__nvoc_base_GpuResource.__nvoc_base_RmResource.__nvoc_base_RmResourceCommon; + pThis->__nvoc_pbase_RmResource = &pThis->__nvoc_base_GpuResource.__nvoc_base_RmResource; + pThis->__nvoc_pbase_GpuResource = &pThis->__nvoc_base_GpuResource; + pThis->__nvoc_pbase_INotifier = &pThis->__nvoc_base_Notifier.__nvoc_base_INotifier; + pThis->__nvoc_pbase_Notifier = &pThis->__nvoc_base_Notifier; + __nvoc_init_GpuResource(&pThis->__nvoc_base_GpuResource); + __nvoc_init_Notifier(&pThis->__nvoc_base_Notifier); + __nvoc_init_funcTable_VidmemAccessBitBuffer(pThis, pRmhalspecowner); +} + +NV_STATUS __nvoc_objCreate_VidmemAccessBitBuffer(VidmemAccessBitBuffer **ppThis, Dynamic *pParent, NvU32 createFlags, CALL_CONTEXT * arg_pCallContext, struct RS_RES_ALLOC_PARAMS_INTERNAL * arg_pParams) { + NV_STATUS status; + Object *pParentObj; + VidmemAccessBitBuffer *pThis; + RmHalspecOwner *pRmhalspecowner; + + status = __nvoc_handleObjCreateMemAlloc(createFlags, sizeof(VidmemAccessBitBuffer), (void**)&pThis, (void**)ppThis); + if (status != NV_OK) + return status; + + portMemSet(pThis, 0, sizeof(VidmemAccessBitBuffer)); + + __nvoc_initRtti(staticCast(pThis, Dynamic), &__nvoc_class_def_VidmemAccessBitBuffer); + + pThis->__nvoc_base_GpuResource.__nvoc_base_RmResource.__nvoc_base_RsResource.__nvoc_base_Object.createFlags = createFlags; + + if (pParent != NULL && !(createFlags & NVOC_OBJ_CREATE_FLAGS_PARENT_HALSPEC_ONLY)) + { + pParentObj = dynamicCast(pParent, Object); + objAddChild(pParentObj, &pThis->__nvoc_base_GpuResource.__nvoc_base_RmResource.__nvoc_base_RsResource.__nvoc_base_Object); + } + else + { + pThis->__nvoc_base_GpuResource.__nvoc_base_RmResource.__nvoc_base_RsResource.__nvoc_base_Object.pParent = NULL; + } + + if ((pRmhalspecowner = dynamicCast(pParent, RmHalspecOwner)) == NULL) + pRmhalspecowner = objFindAncestorOfType(RmHalspecOwner, pParent); + NV_ASSERT_OR_RETURN(pRmhalspecowner != NULL, NV_ERR_INVALID_ARGUMENT); + + __nvoc_init_VidmemAccessBitBuffer(pThis, pRmhalspecowner); + status = __nvoc_ctor_VidmemAccessBitBuffer(pThis, pRmhalspecowner, arg_pCallContext, arg_pParams); + if (status != NV_OK) goto __nvoc_objCreate_VidmemAccessBitBuffer_cleanup; + + *ppThis = pThis; + + return NV_OK; + +__nvoc_objCreate_VidmemAccessBitBuffer_cleanup: + // do not call destructors here since the constructor already called them + if (createFlags & NVOC_OBJ_CREATE_FLAGS_IN_PLACE_CONSTRUCT) + portMemSet(pThis, 0, sizeof(VidmemAccessBitBuffer)); + else + portMemFree(pThis); + + // coverity[leaked_storage:FALSE] + return status; +} + +NV_STATUS __nvoc_objCreateDynamic_VidmemAccessBitBuffer(VidmemAccessBitBuffer **ppThis, Dynamic *pParent, NvU32 createFlags, va_list args) { + NV_STATUS status; + CALL_CONTEXT * arg_pCallContext = va_arg(args, CALL_CONTEXT *); + struct RS_RES_ALLOC_PARAMS_INTERNAL * arg_pParams = va_arg(args, struct RS_RES_ALLOC_PARAMS_INTERNAL *); + + status = __nvoc_objCreate_VidmemAccessBitBuffer(ppThis, pParent, createFlags, arg_pCallContext, arg_pParams); + + return status; +} + diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/generated/g_vidmem_access_bit_buffer_nvoc.h nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_vidmem_access_bit_buffer_nvoc.h --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/generated/g_vidmem_access_bit_buffer_nvoc.h 2023-10-25 20:27:23.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_vidmem_access_bit_buffer_nvoc.h 2024-03-05 22:18:51.000000000 +0000 @@ -93,12 +93,11 @@ struct INotifier *__nvoc_pbase_INotifier; struct Notifier *__nvoc_pbase_Notifier; struct VidmemAccessBitBuffer *__nvoc_pbase_VidmemAccessBitBuffer; - NV_STATUS (*__vidmemAccessBitBufCopyConstruct__)(struct VidmemAccessBitBuffer *, CALL_CONTEXT *, struct RS_RES_ALLOC_PARAMS_INTERNAL *); NV_STATUS (*__vidmemAccessBitBufCtrlCmdVidmemAccessBitDump__)(struct VidmemAccessBitBuffer *, NVC763_CTRL_VIDMEM_ACCESS_BIT_BUFFER_DUMP_PARAMS *); NvBool (*__vidmemAccessBitBufShareCallback__)(struct VidmemAccessBitBuffer *, struct RsClient *, struct RsResourceRef *, RS_SHARE_POLICY *); - NV_STATUS (*__vidmemAccessBitBufMapTo__)(struct VidmemAccessBitBuffer *, RS_RES_MAP_TO_PARAMS *); - NV_STATUS (*__vidmemAccessBitBufGetOrAllocNotifShare__)(struct VidmemAccessBitBuffer *, NvHandle, NvHandle, struct NotifShare **); NV_STATUS (*__vidmemAccessBitBufCheckMemInterUnmap__)(struct VidmemAccessBitBuffer *, NvBool); + NV_STATUS (*__vidmemAccessBitBufGetOrAllocNotifShare__)(struct VidmemAccessBitBuffer *, NvHandle, NvHandle, struct NotifShare **); + NV_STATUS (*__vidmemAccessBitBufMapTo__)(struct VidmemAccessBitBuffer *, RS_RES_MAP_TO_PARAMS *); NV_STATUS (*__vidmemAccessBitBufGetMapAddrSpace__)(struct VidmemAccessBitBuffer *, CALL_CONTEXT *, NvU32, NV_ADDRESS_SPACE *); void (*__vidmemAccessBitBufSetNotificationShare__)(struct VidmemAccessBitBuffer *, struct NotifShare *); NvU32 (*__vidmemAccessBitBufGetRefCount__)(struct VidmemAccessBitBuffer *); @@ -116,9 +115,11 @@ NV_STATUS (*__vidmemAccessBitBufGetMemoryMappingDescriptor__)(struct VidmemAccessBitBuffer *, struct MEMORY_DESCRIPTOR **); NV_STATUS (*__vidmemAccessBitBufControlFilter__)(struct VidmemAccessBitBuffer *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); NV_STATUS (*__vidmemAccessBitBufUnregisterEvent__)(struct VidmemAccessBitBuffer *, NvHandle, NvHandle, NvHandle, NvHandle); + NV_STATUS (*__vidmemAccessBitBufControlSerialization_Prologue__)(struct VidmemAccessBitBuffer *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); NvBool (*__vidmemAccessBitBufCanCopy__)(struct VidmemAccessBitBuffer *); void (*__vidmemAccessBitBufPreDestruct__)(struct VidmemAccessBitBuffer *); NV_STATUS (*__vidmemAccessBitBufIsDuplicate__)(struct VidmemAccessBitBuffer *, NvHandle, NvBool *); + void (*__vidmemAccessBitBufControlSerialization_Epilogue__)(struct VidmemAccessBitBuffer *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); PEVENTNOTIFICATION *(*__vidmemAccessBitBufGetNotificationListPtr__)(struct VidmemAccessBitBuffer *); struct NotifShare *(*__vidmemAccessBitBufGetNotificationShare__)(struct VidmemAccessBitBuffer *); NV_STATUS (*__vidmemAccessBitBufMap__)(struct VidmemAccessBitBuffer *, CALL_CONTEXT *, struct RS_CPU_MAP_PARAMS *, RsCpuMapping *); @@ -153,13 +154,11 @@ #define __objCreate_VidmemAccessBitBuffer(ppNewObj, pParent, createFlags, arg_pCallContext, arg_pParams) \ __nvoc_objCreate_VidmemAccessBitBuffer((ppNewObj), staticCast((pParent), Dynamic), (createFlags), arg_pCallContext, arg_pParams) -#define vidmemAccessBitBufCopyConstruct(pVidmemAccessBitBuffer, pCallContext, pParams) vidmemAccessBitBufCopyConstruct_DISPATCH(pVidmemAccessBitBuffer, pCallContext, pParams) -#define vidmemAccessBitBufCopyConstruct_HAL(pVidmemAccessBitBuffer, pCallContext, pParams) vidmemAccessBitBufCopyConstruct_DISPATCH(pVidmemAccessBitBuffer, pCallContext, pParams) #define vidmemAccessBitBufCtrlCmdVidmemAccessBitDump(pVidmemAccessBitBuffer, pParams) vidmemAccessBitBufCtrlCmdVidmemAccessBitDump_DISPATCH(pVidmemAccessBitBuffer, pParams) #define vidmemAccessBitBufShareCallback(pGpuResource, pInvokingClient, pParentRef, pSharePolicy) vidmemAccessBitBufShareCallback_DISPATCH(pGpuResource, pInvokingClient, pParentRef, pSharePolicy) -#define vidmemAccessBitBufMapTo(pResource, pParams) vidmemAccessBitBufMapTo_DISPATCH(pResource, pParams) -#define vidmemAccessBitBufGetOrAllocNotifShare(pNotifier, hNotifierClient, hNotifierResource, ppNotifShare) vidmemAccessBitBufGetOrAllocNotifShare_DISPATCH(pNotifier, hNotifierClient, hNotifierResource, ppNotifShare) #define vidmemAccessBitBufCheckMemInterUnmap(pRmResource, bSubdeviceHandleProvided) vidmemAccessBitBufCheckMemInterUnmap_DISPATCH(pRmResource, bSubdeviceHandleProvided) +#define vidmemAccessBitBufGetOrAllocNotifShare(pNotifier, hNotifierClient, hNotifierResource, ppNotifShare) vidmemAccessBitBufGetOrAllocNotifShare_DISPATCH(pNotifier, hNotifierClient, hNotifierResource, ppNotifShare) +#define vidmemAccessBitBufMapTo(pResource, pParams) vidmemAccessBitBufMapTo_DISPATCH(pResource, pParams) #define vidmemAccessBitBufGetMapAddrSpace(pGpuResource, pCallContext, mapFlags, pAddrSpace) vidmemAccessBitBufGetMapAddrSpace_DISPATCH(pGpuResource, pCallContext, mapFlags, pAddrSpace) #define vidmemAccessBitBufSetNotificationShare(pNotifier, pNotifShare) vidmemAccessBitBufSetNotificationShare_DISPATCH(pNotifier, pNotifShare) #define vidmemAccessBitBufGetRefCount(pResource) vidmemAccessBitBufGetRefCount_DISPATCH(pResource) @@ -177,9 +176,11 @@ #define vidmemAccessBitBufGetMemoryMappingDescriptor(pRmResource, ppMemDesc) vidmemAccessBitBufGetMemoryMappingDescriptor_DISPATCH(pRmResource, ppMemDesc) #define vidmemAccessBitBufControlFilter(pResource, pCallContext, pParams) vidmemAccessBitBufControlFilter_DISPATCH(pResource, pCallContext, pParams) #define vidmemAccessBitBufUnregisterEvent(pNotifier, hNotifierClient, hNotifierResource, hEventClient, hEvent) vidmemAccessBitBufUnregisterEvent_DISPATCH(pNotifier, hNotifierClient, hNotifierResource, hEventClient, hEvent) +#define vidmemAccessBitBufControlSerialization_Prologue(pResource, pCallContext, pParams) vidmemAccessBitBufControlSerialization_Prologue_DISPATCH(pResource, pCallContext, pParams) #define vidmemAccessBitBufCanCopy(pResource) vidmemAccessBitBufCanCopy_DISPATCH(pResource) #define vidmemAccessBitBufPreDestruct(pResource) vidmemAccessBitBufPreDestruct_DISPATCH(pResource) #define vidmemAccessBitBufIsDuplicate(pResource, hMemory, pDuplicate) vidmemAccessBitBufIsDuplicate_DISPATCH(pResource, hMemory, pDuplicate) +#define vidmemAccessBitBufControlSerialization_Epilogue(pResource, pCallContext, pParams) vidmemAccessBitBufControlSerialization_Epilogue_DISPATCH(pResource, pCallContext, pParams) #define vidmemAccessBitBufGetNotificationListPtr(pNotifier) vidmemAccessBitBufGetNotificationListPtr_DISPATCH(pNotifier) #define vidmemAccessBitBufGetNotificationShare(pNotifier) vidmemAccessBitBufGetNotificationShare_DISPATCH(pNotifier) #define vidmemAccessBitBufMap(pGpuResource, pCallContext, pParams, pCpuMapping) vidmemAccessBitBufMap_DISPATCH(pGpuResource, pCallContext, pParams, pCpuMapping) @@ -204,14 +205,6 @@ #define __nvoc_vidmemAccessBitBufDestruct(pVidmemAccessBitBuffer) vidmemAccessBitBufDestruct_b3696a(pVidmemAccessBitBuffer) -static inline NV_STATUS vidmemAccessBitBufCopyConstruct_56cd7a(struct VidmemAccessBitBuffer *pVidmemAccessBitBuffer, CALL_CONTEXT *pCallContext, struct RS_RES_ALLOC_PARAMS_INTERNAL *pParams) { - return NV_OK; -} - -static inline NV_STATUS vidmemAccessBitBufCopyConstruct_DISPATCH(struct VidmemAccessBitBuffer *pVidmemAccessBitBuffer, CALL_CONTEXT *pCallContext, struct RS_RES_ALLOC_PARAMS_INTERNAL *pParams) { - return pVidmemAccessBitBuffer->__vidmemAccessBitBufCopyConstruct__(pVidmemAccessBitBuffer, pCallContext, pParams); -} - NV_STATUS vidmemAccessBitBufCtrlCmdVidmemAccessBitDump_IMPL(struct VidmemAccessBitBuffer *pVidmemAccessBitBuffer, NVC763_CTRL_VIDMEM_ACCESS_BIT_BUFFER_DUMP_PARAMS *pParams); static inline NV_STATUS vidmemAccessBitBufCtrlCmdVidmemAccessBitDump_DISPATCH(struct VidmemAccessBitBuffer *pVidmemAccessBitBuffer, NVC763_CTRL_VIDMEM_ACCESS_BIT_BUFFER_DUMP_PARAMS *pParams) { @@ -222,16 +215,16 @@ return pGpuResource->__vidmemAccessBitBufShareCallback__(pGpuResource, pInvokingClient, pParentRef, pSharePolicy); } -static inline NV_STATUS vidmemAccessBitBufMapTo_DISPATCH(struct VidmemAccessBitBuffer *pResource, RS_RES_MAP_TO_PARAMS *pParams) { - return pResource->__vidmemAccessBitBufMapTo__(pResource, pParams); +static inline NV_STATUS vidmemAccessBitBufCheckMemInterUnmap_DISPATCH(struct VidmemAccessBitBuffer *pRmResource, NvBool bSubdeviceHandleProvided) { + return pRmResource->__vidmemAccessBitBufCheckMemInterUnmap__(pRmResource, bSubdeviceHandleProvided); } static inline NV_STATUS vidmemAccessBitBufGetOrAllocNotifShare_DISPATCH(struct VidmemAccessBitBuffer *pNotifier, NvHandle hNotifierClient, NvHandle hNotifierResource, struct NotifShare **ppNotifShare) { return pNotifier->__vidmemAccessBitBufGetOrAllocNotifShare__(pNotifier, hNotifierClient, hNotifierResource, ppNotifShare); } -static inline NV_STATUS vidmemAccessBitBufCheckMemInterUnmap_DISPATCH(struct VidmemAccessBitBuffer *pRmResource, NvBool bSubdeviceHandleProvided) { - return pRmResource->__vidmemAccessBitBufCheckMemInterUnmap__(pRmResource, bSubdeviceHandleProvided); +static inline NV_STATUS vidmemAccessBitBufMapTo_DISPATCH(struct VidmemAccessBitBuffer *pResource, RS_RES_MAP_TO_PARAMS *pParams) { + return pResource->__vidmemAccessBitBufMapTo__(pResource, pParams); } static inline NV_STATUS vidmemAccessBitBufGetMapAddrSpace_DISPATCH(struct VidmemAccessBitBuffer *pGpuResource, CALL_CONTEXT *pCallContext, NvU32 mapFlags, NV_ADDRESS_SPACE *pAddrSpace) { @@ -302,6 +295,10 @@ return pNotifier->__vidmemAccessBitBufUnregisterEvent__(pNotifier, hNotifierClient, hNotifierResource, hEventClient, hEvent); } +static inline NV_STATUS vidmemAccessBitBufControlSerialization_Prologue_DISPATCH(struct VidmemAccessBitBuffer *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return pResource->__vidmemAccessBitBufControlSerialization_Prologue__(pResource, pCallContext, pParams); +} + static inline NvBool vidmemAccessBitBufCanCopy_DISPATCH(struct VidmemAccessBitBuffer *pResource) { return pResource->__vidmemAccessBitBufCanCopy__(pResource); } @@ -314,6 +311,10 @@ return pResource->__vidmemAccessBitBufIsDuplicate__(pResource, hMemory, pDuplicate); } +static inline void vidmemAccessBitBufControlSerialization_Epilogue_DISPATCH(struct VidmemAccessBitBuffer *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + pResource->__vidmemAccessBitBufControlSerialization_Epilogue__(pResource, pCallContext, pParams); +} + static inline PEVENTNOTIFICATION *vidmemAccessBitBufGetNotificationListPtr_DISPATCH(struct VidmemAccessBitBuffer *pNotifier) { return pNotifier->__vidmemAccessBitBufGetNotificationListPtr__(pNotifier); } diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/generated/g_virt_mem_allocator_nvoc.c nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_virt_mem_allocator_nvoc.c --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/generated/g_virt_mem_allocator_nvoc.c 2023-10-25 20:27:23.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_virt_mem_allocator_nvoc.c 2024-03-05 22:18:52.000000000 +0000 @@ -78,10 +78,6 @@ return dmaStatePostLoad(pGpu, (struct VirtMemAllocator *)(((unsigned char *)pDma) - __nvoc_rtti_VirtMemAllocator_OBJENGSTATE.offset), arg0); } -static NV_STATUS __nvoc_thunk_OBJENGSTATE_dmaReconcileTunableState(POBJGPU pGpu, struct VirtMemAllocator *pEngstate, void *pTunableState) { - return engstateReconcileTunableState(pGpu, (struct OBJENGSTATE *)(((unsigned char *)pEngstate) + __nvoc_rtti_VirtMemAllocator_OBJENGSTATE.offset), pTunableState); -} - static NV_STATUS __nvoc_thunk_OBJENGSTATE_dmaStateLoad(POBJGPU pGpu, struct VirtMemAllocator *pEngstate, NvU32 arg0) { return engstateStateLoad(pGpu, (struct OBJENGSTATE *)(((unsigned char *)pEngstate) + __nvoc_rtti_VirtMemAllocator_OBJENGSTATE.offset), arg0); } @@ -122,26 +118,6 @@ return engstateStatePreInitUnlocked(pGpu, (struct OBJENGSTATE *)(((unsigned char *)pEngstate) + __nvoc_rtti_VirtMemAllocator_OBJENGSTATE.offset)); } -static NV_STATUS __nvoc_thunk_OBJENGSTATE_dmaGetTunableState(POBJGPU pGpu, struct VirtMemAllocator *pEngstate, void *pTunableState) { - return engstateGetTunableState(pGpu, (struct OBJENGSTATE *)(((unsigned char *)pEngstate) + __nvoc_rtti_VirtMemAllocator_OBJENGSTATE.offset), pTunableState); -} - -static NV_STATUS __nvoc_thunk_OBJENGSTATE_dmaCompareTunableState(POBJGPU pGpu, struct VirtMemAllocator *pEngstate, void *pTunables1, void *pTunables2) { - return engstateCompareTunableState(pGpu, (struct OBJENGSTATE *)(((unsigned char *)pEngstate) + __nvoc_rtti_VirtMemAllocator_OBJENGSTATE.offset), pTunables1, pTunables2); -} - -static void __nvoc_thunk_OBJENGSTATE_dmaFreeTunableState(POBJGPU pGpu, struct VirtMemAllocator *pEngstate, void *pTunableState) { - engstateFreeTunableState(pGpu, (struct OBJENGSTATE *)(((unsigned char *)pEngstate) + __nvoc_rtti_VirtMemAllocator_OBJENGSTATE.offset), pTunableState); -} - -static NV_STATUS __nvoc_thunk_OBJENGSTATE_dmaAllocTunableState(POBJGPU pGpu, struct VirtMemAllocator *pEngstate, void **ppTunableState) { - return engstateAllocTunableState(pGpu, (struct OBJENGSTATE *)(((unsigned char *)pEngstate) + __nvoc_rtti_VirtMemAllocator_OBJENGSTATE.offset), ppTunableState); -} - -static NV_STATUS __nvoc_thunk_OBJENGSTATE_dmaSetTunableState(POBJGPU pGpu, struct VirtMemAllocator *pEngstate, void *pTunableState) { - return engstateSetTunableState(pGpu, (struct OBJENGSTATE *)(((unsigned char *)pEngstate) + __nvoc_rtti_VirtMemAllocator_OBJENGSTATE.offset), pTunableState); -} - static NvBool __nvoc_thunk_OBJENGSTATE_dmaIsPresent(POBJGPU pGpu, struct VirtMemAllocator *pEngstate) { return engstateIsPresent(pGpu, (struct OBJENGSTATE *)(((unsigned char *)pEngstate) + __nvoc_rtti_VirtMemAllocator_OBJENGSTATE.offset)); } @@ -255,10 +231,7 @@ } // Hal function -- dmaStatePostLoad - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x11f0ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 | GH100 */ - { - pThis->__dmaStatePostLoad__ = &dmaStatePostLoad_GM107; - } + pThis->__dmaStatePostLoad__ = &dmaStatePostLoad_GM107; pThis->__nvoc_base_OBJENGSTATE.__engstateConstructEngine__ = &__nvoc_thunk_VirtMemAllocator_engstateConstructEngine; @@ -266,8 +239,6 @@ pThis->__nvoc_base_OBJENGSTATE.__engstateStatePostLoad__ = &__nvoc_thunk_VirtMemAllocator_engstateStatePostLoad; - pThis->__dmaReconcileTunableState__ = &__nvoc_thunk_OBJENGSTATE_dmaReconcileTunableState; - pThis->__dmaStateLoad__ = &__nvoc_thunk_OBJENGSTATE_dmaStateLoad; pThis->__dmaStateUnload__ = &__nvoc_thunk_OBJENGSTATE_dmaStateUnload; @@ -288,16 +259,6 @@ pThis->__dmaStatePreInitUnlocked__ = &__nvoc_thunk_OBJENGSTATE_dmaStatePreInitUnlocked; - pThis->__dmaGetTunableState__ = &__nvoc_thunk_OBJENGSTATE_dmaGetTunableState; - - pThis->__dmaCompareTunableState__ = &__nvoc_thunk_OBJENGSTATE_dmaCompareTunableState; - - pThis->__dmaFreeTunableState__ = &__nvoc_thunk_OBJENGSTATE_dmaFreeTunableState; - - pThis->__dmaAllocTunableState__ = &__nvoc_thunk_OBJENGSTATE_dmaAllocTunableState; - - pThis->__dmaSetTunableState__ = &__nvoc_thunk_OBJENGSTATE_dmaSetTunableState; - pThis->__dmaIsPresent__ = &__nvoc_thunk_OBJENGSTATE_dmaIsPresent; } @@ -320,13 +281,16 @@ VirtMemAllocator *pThis; RmHalspecOwner *pRmhalspecowner; - pThis = portMemAllocNonPaged(sizeof(VirtMemAllocator)); - if (pThis == NULL) return NV_ERR_NO_MEMORY; + status = __nvoc_handleObjCreateMemAlloc(createFlags, sizeof(VirtMemAllocator), (void**)&pThis, (void**)ppThis); + if (status != NV_OK) + return status; portMemSet(pThis, 0, sizeof(VirtMemAllocator)); __nvoc_initRtti(staticCast(pThis, Dynamic), &__nvoc_class_def_VirtMemAllocator); + pThis->__nvoc_base_OBJENGSTATE.__nvoc_base_Object.createFlags = createFlags; + if (pParent != NULL && !(createFlags & NVOC_OBJ_CREATE_FLAGS_PARENT_HALSPEC_ONLY)) { pParentObj = dynamicCast(pParent, Object); @@ -346,11 +310,17 @@ if (status != NV_OK) goto __nvoc_objCreate_VirtMemAllocator_cleanup; *ppThis = pThis; + return NV_OK; __nvoc_objCreate_VirtMemAllocator_cleanup: // do not call destructors here since the constructor already called them - portMemFree(pThis); + if (createFlags & NVOC_OBJ_CREATE_FLAGS_IN_PLACE_CONSTRUCT) + portMemSet(pThis, 0, sizeof(VirtMemAllocator)); + else + portMemFree(pThis); + + // coverity[leaked_storage:FALSE] return status; } diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/generated/g_virt_mem_allocator_nvoc.h nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_virt_mem_allocator_nvoc.h --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/generated/g_virt_mem_allocator_nvoc.h 2023-10-25 20:27:24.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_virt_mem_allocator_nvoc.h 2024-03-05 22:18:52.000000000 +0000 @@ -104,7 +104,6 @@ NV_STATUS (*__dmaAllocBar1P2PMapping__)(struct OBJGPU *, struct VirtMemAllocator *, DMA_BAR1P2P_MAPPING_PRARAMS *); void (*__dmaFreeBar1P2PMapping__)(struct VirtMemAllocator *, CLI_DMA_MAPPING_INFO *); NV_STATUS (*__dmaStatePostLoad__)(struct OBJGPU *, struct VirtMemAllocator *, NvU32); - NV_STATUS (*__dmaReconcileTunableState__)(POBJGPU, struct VirtMemAllocator *, void *); NV_STATUS (*__dmaStateLoad__)(POBJGPU, struct VirtMemAllocator *, NvU32); NV_STATUS (*__dmaStateUnload__)(POBJGPU, struct VirtMemAllocator *, NvU32); NV_STATUS (*__dmaStatePreLoad__)(POBJGPU, struct VirtMemAllocator *, NvU32); @@ -115,11 +114,6 @@ void (*__dmaInitMissing__)(POBJGPU, struct VirtMemAllocator *); NV_STATUS (*__dmaStatePreInitLocked__)(POBJGPU, struct VirtMemAllocator *); NV_STATUS (*__dmaStatePreInitUnlocked__)(POBJGPU, struct VirtMemAllocator *); - NV_STATUS (*__dmaGetTunableState__)(POBJGPU, struct VirtMemAllocator *, void *); - NV_STATUS (*__dmaCompareTunableState__)(POBJGPU, struct VirtMemAllocator *, void *, void *); - void (*__dmaFreeTunableState__)(POBJGPU, struct VirtMemAllocator *, void *); - NV_STATUS (*__dmaAllocTunableState__)(POBJGPU, struct VirtMemAllocator *, void **); - NV_STATUS (*__dmaSetTunableState__)(POBJGPU, struct VirtMemAllocator *, void *); NvBool (*__dmaIsPresent__)(POBJGPU, struct VirtMemAllocator *); NvBool PDB_PROP_DMA_MMU_INVALIDATE_DISABLE; NvBool PDB_PROP_DMA_ENFORCE_32BIT_POINTER; @@ -189,7 +183,6 @@ #define dmaFreeBar1P2PMapping_HAL(pDma, arg0) dmaFreeBar1P2PMapping_DISPATCH(pDma, arg0) #define dmaStatePostLoad(pGpu, pDma, arg0) dmaStatePostLoad_DISPATCH(pGpu, pDma, arg0) #define dmaStatePostLoad_HAL(pGpu, pDma, arg0) dmaStatePostLoad_DISPATCH(pGpu, pDma, arg0) -#define dmaReconcileTunableState(pGpu, pEngstate, pTunableState) dmaReconcileTunableState_DISPATCH(pGpu, pEngstate, pTunableState) #define dmaStateLoad(pGpu, pEngstate, arg0) dmaStateLoad_DISPATCH(pGpu, pEngstate, arg0) #define dmaStateUnload(pGpu, pEngstate, arg0) dmaStateUnload_DISPATCH(pGpu, pEngstate, arg0) #define dmaStatePreLoad(pGpu, pEngstate, arg0) dmaStatePreLoad_DISPATCH(pGpu, pEngstate, arg0) @@ -200,11 +193,6 @@ #define dmaInitMissing(pGpu, pEngstate) dmaInitMissing_DISPATCH(pGpu, pEngstate) #define dmaStatePreInitLocked(pGpu, pEngstate) dmaStatePreInitLocked_DISPATCH(pGpu, pEngstate) #define dmaStatePreInitUnlocked(pGpu, pEngstate) dmaStatePreInitUnlocked_DISPATCH(pGpu, pEngstate) -#define dmaGetTunableState(pGpu, pEngstate, pTunableState) dmaGetTunableState_DISPATCH(pGpu, pEngstate, pTunableState) -#define dmaCompareTunableState(pGpu, pEngstate, pTunables1, pTunables2) dmaCompareTunableState_DISPATCH(pGpu, pEngstate, pTunables1, pTunables2) -#define dmaFreeTunableState(pGpu, pEngstate, pTunableState) dmaFreeTunableState_DISPATCH(pGpu, pEngstate, pTunableState) -#define dmaAllocTunableState(pGpu, pEngstate, ppTunableState) dmaAllocTunableState_DISPATCH(pGpu, pEngstate, ppTunableState) -#define dmaSetTunableState(pGpu, pEngstate, pTunableState) dmaSetTunableState_DISPATCH(pGpu, pEngstate, pTunableState) #define dmaIsPresent(pGpu, pEngstate) dmaIsPresent_DISPATCH(pGpu, pEngstate) NV_STATUS dmaInit_GM107(struct OBJGPU *pGpu, struct VirtMemAllocator *pDma); @@ -284,11 +272,11 @@ #define dmaFreeMapping_HAL(pGpu, pDma, arg0, arg1, arg2, arg3, arg4) dmaFreeMapping(pGpu, pDma, arg0, arg1, arg2, arg3, arg4) -NV_STATUS dmaUpdateVASpace_GF100(struct OBJGPU *pGpu, struct VirtMemAllocator *pDma, struct OBJVASPACE *pVAS, MEMORY_DESCRIPTOR *pMemDesc, NvU8 *tgtPteMem, NvU64 vAddr, NvU64 vAddrLimit, NvU32 flags, DMA_PAGE_ARRAY *pPageArray, NvU32 overmapPteMod, COMPR_INFO *pComprInfo, NvU64 surfaceOffset, NvU32 valid, NvU32 aperture, NvU32 peer, NvU64 fabricAddr, NvU32 deferInvalidate, NvBool bSparse, NvU32 pageSize); +NV_STATUS dmaUpdateVASpace_GF100(struct OBJGPU *pGpu, struct VirtMemAllocator *pDma, struct OBJVASPACE *pVAS, MEMORY_DESCRIPTOR *pMemDesc, NvU8 *tgtPteMem, NvU64 vAddr, NvU64 vAddrLimit, NvU32 flags, DMA_PAGE_ARRAY *pPageArray, NvU32 overmapPteMod, COMPR_INFO *pComprInfo, NvU64 surfaceOffset, NvU32 valid, NvU32 aperture, NvU32 peer, NvU64 fabricAddr, NvU32 deferInvalidate, NvBool bSparse, NvU64 pageSize); #ifdef __nvoc_virt_mem_allocator_h_disabled -static inline NV_STATUS dmaUpdateVASpace(struct OBJGPU *pGpu, struct VirtMemAllocator *pDma, struct OBJVASPACE *pVAS, MEMORY_DESCRIPTOR *pMemDesc, NvU8 *tgtPteMem, NvU64 vAddr, NvU64 vAddrLimit, NvU32 flags, DMA_PAGE_ARRAY *pPageArray, NvU32 overmapPteMod, COMPR_INFO *pComprInfo, NvU64 surfaceOffset, NvU32 valid, NvU32 aperture, NvU32 peer, NvU64 fabricAddr, NvU32 deferInvalidate, NvBool bSparse, NvU32 pageSize) { +static inline NV_STATUS dmaUpdateVASpace(struct OBJGPU *pGpu, struct VirtMemAllocator *pDma, struct OBJVASPACE *pVAS, MEMORY_DESCRIPTOR *pMemDesc, NvU8 *tgtPteMem, NvU64 vAddr, NvU64 vAddrLimit, NvU32 flags, DMA_PAGE_ARRAY *pPageArray, NvU32 overmapPteMod, COMPR_INFO *pComprInfo, NvU64 surfaceOffset, NvU32 valid, NvU32 aperture, NvU32 peer, NvU64 fabricAddr, NvU32 deferInvalidate, NvBool bSparse, NvU64 pageSize) { NV_ASSERT_FAILED_PRECOMP("VirtMemAllocator was disabled!"); return NV_ERR_NOT_SUPPORTED; } @@ -421,10 +409,6 @@ return pDma->__dmaStatePostLoad__(pGpu, pDma, arg0); } -static inline NV_STATUS dmaReconcileTunableState_DISPATCH(POBJGPU pGpu, struct VirtMemAllocator *pEngstate, void *pTunableState) { - return pEngstate->__dmaReconcileTunableState__(pGpu, pEngstate, pTunableState); -} - static inline NV_STATUS dmaStateLoad_DISPATCH(POBJGPU pGpu, struct VirtMemAllocator *pEngstate, NvU32 arg0) { return pEngstate->__dmaStateLoad__(pGpu, pEngstate, arg0); } @@ -465,26 +449,6 @@ return pEngstate->__dmaStatePreInitUnlocked__(pGpu, pEngstate); } -static inline NV_STATUS dmaGetTunableState_DISPATCH(POBJGPU pGpu, struct VirtMemAllocator *pEngstate, void *pTunableState) { - return pEngstate->__dmaGetTunableState__(pGpu, pEngstate, pTunableState); -} - -static inline NV_STATUS dmaCompareTunableState_DISPATCH(POBJGPU pGpu, struct VirtMemAllocator *pEngstate, void *pTunables1, void *pTunables2) { - return pEngstate->__dmaCompareTunableState__(pGpu, pEngstate, pTunables1, pTunables2); -} - -static inline void dmaFreeTunableState_DISPATCH(POBJGPU pGpu, struct VirtMemAllocator *pEngstate, void *pTunableState) { - pEngstate->__dmaFreeTunableState__(pGpu, pEngstate, pTunableState); -} - -static inline NV_STATUS dmaAllocTunableState_DISPATCH(POBJGPU pGpu, struct VirtMemAllocator *pEngstate, void **ppTunableState) { - return pEngstate->__dmaAllocTunableState__(pGpu, pEngstate, ppTunableState); -} - -static inline NV_STATUS dmaSetTunableState_DISPATCH(POBJGPU pGpu, struct VirtMemAllocator *pEngstate, void *pTunableState) { - return pEngstate->__dmaSetTunableState__(pGpu, pEngstate, pTunableState); -} - static inline NvBool dmaIsPresent_DISPATCH(POBJGPU pGpu, struct VirtMemAllocator *pEngstate) { return pEngstate->__dmaIsPresent__(pGpu, pEngstate); } @@ -527,7 +491,6 @@ #define VAS_PAGESIZE_IDX_BIG 1 #define VAS_PAGESIZE_IDX_HUGE 2 #define VAS_PAGESIZE_IDX_512M 3 -#define VAS_PAGESIZE_IDX_MAX 4 // VMM-TODO Used by old VAS Object #define VAS_NUM_PAGESIZE_TYPES VAS_PAGESIZE_IDX_BIG+1 @@ -608,10 +571,15 @@ // // hal.dmaAllocVASpace() flags // -#define DMA_ALLOC_VASPACE_NONE 0 -#define DMA_VA_LIMIT_49B NVBIT(0) -#define DMA_VA_LIMIT_57B NVBIT(1) -#define DMA_ALLOC_VASPACE_SIZE_ALIGNED NVBIT(9) +#define DMA_ALLOC_VASPACE_NONE 0 +#define DMA_VA_LIMIT_49B NVBIT(0) +#define DMA_VA_LIMIT_57B NVBIT(1) +#define DMA_ALLOC_VASPACE_SIZE_ALIGNED NVBIT(9) +// +// Bug 3610538 For unlinked SLI, clients want to restrict internal buffers to +// Internal VA range, so that SLI vaspaces can mirror each other. +// +#define DMA_ALLOC_VASPACE_USE_RM_INTERNAL_VALIMITS NVBIT(10) // // Internal device allocation flags diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/generated/g_virt_mem_mgr_nvoc.c nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_virt_mem_mgr_nvoc.c --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/generated/g_virt_mem_mgr_nvoc.c 2023-10-25 20:27:24.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_virt_mem_mgr_nvoc.c 2024-03-05 22:18:52.000000000 +0000 @@ -108,13 +108,16 @@ Object *pParentObj; OBJVMM *pThis; - pThis = portMemAllocNonPaged(sizeof(OBJVMM)); - if (pThis == NULL) return NV_ERR_NO_MEMORY; + status = __nvoc_handleObjCreateMemAlloc(createFlags, sizeof(OBJVMM), (void**)&pThis, (void**)ppThis); + if (status != NV_OK) + return status; portMemSet(pThis, 0, sizeof(OBJVMM)); __nvoc_initRtti(staticCast(pThis, Dynamic), &__nvoc_class_def_OBJVMM); + pThis->__nvoc_base_Object.createFlags = createFlags; + if (pParent != NULL && !(createFlags & NVOC_OBJ_CREATE_FLAGS_PARENT_HALSPEC_ONLY)) { pParentObj = dynamicCast(pParent, Object); @@ -130,11 +133,17 @@ if (status != NV_OK) goto __nvoc_objCreate_OBJVMM_cleanup; *ppThis = pThis; + return NV_OK; __nvoc_objCreate_OBJVMM_cleanup: // do not call destructors here since the constructor already called them - portMemFree(pThis); + if (createFlags & NVOC_OBJ_CREATE_FLAGS_IN_PLACE_CONSTRUCT) + portMemSet(pThis, 0, sizeof(OBJVMM)); + else + portMemFree(pThis); + + // coverity[leaked_storage:FALSE] return status; } diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/generated/g_virt_mem_range_nvoc.c nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_virt_mem_range_nvoc.c --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/generated/g_virt_mem_range_nvoc.c 2023-10-25 20:27:24.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_virt_mem_range_nvoc.c 2024-03-05 22:18:52.000000000 +0000 @@ -119,80 +119,88 @@ return virtmemMapTo((struct VirtualMemory *)(((unsigned char *)pVirtualMemory) + __nvoc_rtti_VirtualMemoryRange_VirtualMemory.offset), pParams); } -static NV_STATUS __nvoc_thunk_Memory_vmrangeControl(struct VirtualMemoryRange *pMemory, CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { - return memControl((struct Memory *)(((unsigned char *)pMemory) + __nvoc_rtti_VirtualMemoryRange_Memory.offset), pCallContext, pParams); +static NvBool __nvoc_thunk_RmResource_vmrangeShareCallback(struct VirtualMemoryRange *pResource, struct RsClient *pInvokingClient, struct RsResourceRef *pParentRef, RS_SHARE_POLICY *pSharePolicy) { + return rmresShareCallback((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_VirtualMemoryRange_RmResource.offset), pInvokingClient, pParentRef, pSharePolicy); } -static NV_STATUS __nvoc_thunk_Memory_vmrangeGetMemInterMapParams(struct VirtualMemoryRange *pMemory, RMRES_MEM_INTER_MAP_PARAMS *pParams) { - return memGetMemInterMapParams((struct Memory *)(((unsigned char *)pMemory) + __nvoc_rtti_VirtualMemoryRange_Memory.offset), pParams); +static NV_STATUS __nvoc_thunk_Memory_vmrangeGetMapAddrSpace(struct VirtualMemoryRange *pMemory, CALL_CONTEXT *pCallContext, NvU32 mapFlags, NV_ADDRESS_SPACE *pAddrSpace) { + return memGetMapAddrSpace((struct Memory *)(((unsigned char *)pMemory) + __nvoc_rtti_VirtualMemoryRange_Memory.offset), pCallContext, mapFlags, pAddrSpace); } -static NV_STATUS __nvoc_thunk_Memory_vmrangeUnmap(struct VirtualMemoryRange *pMemory, CALL_CONTEXT *pCallContext, RsCpuMapping *pCpuMapping) { - return memUnmap((struct Memory *)(((unsigned char *)pMemory) + __nvoc_rtti_VirtualMemoryRange_Memory.offset), pCallContext, pCpuMapping); +static NvU32 __nvoc_thunk_RsResource_vmrangeGetRefCount(struct VirtualMemoryRange *pResource) { + return resGetRefCount((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_VirtualMemoryRange_RsResource.offset)); } -static NV_STATUS __nvoc_thunk_Memory_vmrangeGetMapAddrSpace(struct VirtualMemoryRange *pMemory, CALL_CONTEXT *pCallContext, NvU32 mapFlags, NV_ADDRESS_SPACE *pAddrSpace) { - return memGetMapAddrSpace((struct Memory *)(((unsigned char *)pMemory) + __nvoc_rtti_VirtualMemoryRange_Memory.offset), pCallContext, mapFlags, pAddrSpace); +static void __nvoc_thunk_RsResource_vmrangeAddAdditionalDependants(struct RsClient *pClient, struct VirtualMemoryRange *pResource, RsResourceRef *pReference) { + resAddAdditionalDependants(pClient, (struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_VirtualMemoryRange_RsResource.offset), pReference); } -static NvBool __nvoc_thunk_RmResource_vmrangeShareCallback(struct VirtualMemoryRange *pResource, struct RsClient *pInvokingClient, struct RsResourceRef *pParentRef, RS_SHARE_POLICY *pSharePolicy) { - return rmresShareCallback((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_VirtualMemoryRange_RmResource.offset), pInvokingClient, pParentRef, pSharePolicy); +static NV_STATUS __nvoc_thunk_RmResource_vmrangeControl_Prologue(struct VirtualMemoryRange *pResource, CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return rmresControl_Prologue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_VirtualMemoryRange_RmResource.offset), pCallContext, pParams); } -static NV_STATUS __nvoc_thunk_Memory_vmrangeGetMemoryMappingDescriptor(struct VirtualMemoryRange *pMemory, MEMORY_DESCRIPTOR **ppMemDesc) { - return memGetMemoryMappingDescriptor((struct Memory *)(((unsigned char *)pMemory) + __nvoc_rtti_VirtualMemoryRange_Memory.offset), ppMemDesc); +static NvBool __nvoc_thunk_Memory_vmrangeIsGpuMapAllowed(struct VirtualMemoryRange *pMemory, struct OBJGPU *pGpu) { + return memIsGpuMapAllowed((struct Memory *)(((unsigned char *)pMemory) + __nvoc_rtti_VirtualMemoryRange_Memory.offset), pGpu); } -static NV_STATUS __nvoc_thunk_RsResource_vmrangeControlFilter(struct VirtualMemoryRange *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { - return resControlFilter((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_VirtualMemoryRange_RsResource.offset), pCallContext, pParams); +static NV_STATUS __nvoc_thunk_VirtualMemory_vmrangeUnmapFrom(struct VirtualMemoryRange *pVirtualMemory, struct RS_RES_UNMAP_FROM_PARAMS *pParams) { + return virtmemUnmapFrom((struct VirtualMemory *)(((unsigned char *)pVirtualMemory) + __nvoc_rtti_VirtualMemoryRange_VirtualMemory.offset), pParams); } -static NvU32 __nvoc_thunk_RsResource_vmrangeGetRefCount(struct VirtualMemoryRange *pResource) { - return resGetRefCount((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_VirtualMemoryRange_RsResource.offset)); +static void __nvoc_thunk_RmResource_vmrangeControl_Epilogue(struct VirtualMemoryRange *pResource, CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + rmresControl_Epilogue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_VirtualMemoryRange_RmResource.offset), pCallContext, pParams); } -static void __nvoc_thunk_RsResource_vmrangeAddAdditionalDependants(struct RsClient *pClient, struct VirtualMemoryRange *pResource, RsResourceRef *pReference) { - resAddAdditionalDependants(pClient, (struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_VirtualMemoryRange_RsResource.offset), pReference); +static NV_STATUS __nvoc_thunk_RsResource_vmrangeControlLookup(struct VirtualMemoryRange *pResource, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams, const struct NVOC_EXPORTED_METHOD_DEF **ppEntry) { + return resControlLookup((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_VirtualMemoryRange_RsResource.offset), pParams, ppEntry); } -static NvBool __nvoc_thunk_StandardMemory_vmrangeCanCopy(struct VirtualMemoryRange *pStandardMemory) { - return stdmemCanCopy((struct StandardMemory *)(((unsigned char *)pStandardMemory) + __nvoc_rtti_VirtualMemoryRange_StandardMemory.offset)); +static NV_STATUS __nvoc_thunk_Memory_vmrangeControl(struct VirtualMemoryRange *pMemory, CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return memControl((struct Memory *)(((unsigned char *)pMemory) + __nvoc_rtti_VirtualMemoryRange_Memory.offset), pCallContext, pParams); } -static NvBool __nvoc_thunk_Memory_vmrangeIsGpuMapAllowed(struct VirtualMemoryRange *pMemory, struct OBJGPU *pGpu) { - return memIsGpuMapAllowed((struct Memory *)(((unsigned char *)pMemory) + __nvoc_rtti_VirtualMemoryRange_Memory.offset), pGpu); +static NV_STATUS __nvoc_thunk_Memory_vmrangeUnmap(struct VirtualMemoryRange *pMemory, CALL_CONTEXT *pCallContext, RsCpuMapping *pCpuMapping) { + return memUnmap((struct Memory *)(((unsigned char *)pMemory) + __nvoc_rtti_VirtualMemoryRange_Memory.offset), pCallContext, pCpuMapping); } -static NV_STATUS __nvoc_thunk_RmResource_vmrangeControl_Prologue(struct VirtualMemoryRange *pResource, CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { - return rmresControl_Prologue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_VirtualMemoryRange_RmResource.offset), pCallContext, pParams); +static NV_STATUS __nvoc_thunk_Memory_vmrangeGetMemInterMapParams(struct VirtualMemoryRange *pMemory, RMRES_MEM_INTER_MAP_PARAMS *pParams) { + return memGetMemInterMapParams((struct Memory *)(((unsigned char *)pMemory) + __nvoc_rtti_VirtualMemoryRange_Memory.offset), pParams); } -static NV_STATUS __nvoc_thunk_Memory_vmrangeIsReady(struct VirtualMemoryRange *pMemory, NvBool bCopyConstructorContext) { - return memIsReady((struct Memory *)(((unsigned char *)pMemory) + __nvoc_rtti_VirtualMemoryRange_Memory.offset), bCopyConstructorContext); +static NV_STATUS __nvoc_thunk_Memory_vmrangeGetMemoryMappingDescriptor(struct VirtualMemoryRange *pMemory, MEMORY_DESCRIPTOR **ppMemDesc) { + return memGetMemoryMappingDescriptor((struct Memory *)(((unsigned char *)pMemory) + __nvoc_rtti_VirtualMemoryRange_Memory.offset), ppMemDesc); } -static NV_STATUS __nvoc_thunk_VirtualMemory_vmrangeUnmapFrom(struct VirtualMemoryRange *pVirtualMemory, struct RS_RES_UNMAP_FROM_PARAMS *pParams) { - return virtmemUnmapFrom((struct VirtualMemory *)(((unsigned char *)pVirtualMemory) + __nvoc_rtti_VirtualMemoryRange_VirtualMemory.offset), pParams); +static NV_STATUS __nvoc_thunk_RsResource_vmrangeControlFilter(struct VirtualMemoryRange *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return resControlFilter((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_VirtualMemoryRange_RsResource.offset), pCallContext, pParams); } -static NV_STATUS __nvoc_thunk_Memory_vmrangeCheckCopyPermissions(struct VirtualMemoryRange *pMemory, struct OBJGPU *pDstGpu, NvHandle hDstClientNvBool) { - return memCheckCopyPermissions((struct Memory *)(((unsigned char *)pMemory) + __nvoc_rtti_VirtualMemoryRange_Memory.offset), pDstGpu, hDstClientNvBool); +static NV_STATUS __nvoc_thunk_RmResource_vmrangeControlSerialization_Prologue(struct VirtualMemoryRange *pResource, CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return rmresControlSerialization_Prologue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_VirtualMemoryRange_RmResource.offset), pCallContext, pParams); } -static NV_STATUS __nvoc_thunk_Memory_vmrangeIsDuplicate(struct VirtualMemoryRange *pMemory, NvHandle hMemory, NvBool *pDuplicate) { - return memIsDuplicate((struct Memory *)(((unsigned char *)pMemory) + __nvoc_rtti_VirtualMemoryRange_Memory.offset), hMemory, pDuplicate); +static NvBool __nvoc_thunk_StandardMemory_vmrangeCanCopy(struct VirtualMemoryRange *pStandardMemory) { + return stdmemCanCopy((struct StandardMemory *)(((unsigned char *)pStandardMemory) + __nvoc_rtti_VirtualMemoryRange_StandardMemory.offset)); +} + +static NV_STATUS __nvoc_thunk_Memory_vmrangeIsReady(struct VirtualMemoryRange *pMemory, NvBool bCopyConstructorContext) { + return memIsReady((struct Memory *)(((unsigned char *)pMemory) + __nvoc_rtti_VirtualMemoryRange_Memory.offset), bCopyConstructorContext); +} + +static NV_STATUS __nvoc_thunk_Memory_vmrangeCheckCopyPermissions(struct VirtualMemoryRange *pMemory, struct OBJGPU *pDstGpu, struct Device *pDstDevice) { + return memCheckCopyPermissions((struct Memory *)(((unsigned char *)pMemory) + __nvoc_rtti_VirtualMemoryRange_Memory.offset), pDstGpu, pDstDevice); } static void __nvoc_thunk_RsResource_vmrangePreDestruct(struct VirtualMemoryRange *pResource) { resPreDestruct((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_VirtualMemoryRange_RsResource.offset)); } -static void __nvoc_thunk_RmResource_vmrangeControl_Epilogue(struct VirtualMemoryRange *pResource, CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { - rmresControl_Epilogue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_VirtualMemoryRange_RmResource.offset), pCallContext, pParams); +static NV_STATUS __nvoc_thunk_Memory_vmrangeIsDuplicate(struct VirtualMemoryRange *pMemory, NvHandle hMemory, NvBool *pDuplicate) { + return memIsDuplicate((struct Memory *)(((unsigned char *)pMemory) + __nvoc_rtti_VirtualMemoryRange_Memory.offset), hMemory, pDuplicate); } -static NV_STATUS __nvoc_thunk_RsResource_vmrangeControlLookup(struct VirtualMemoryRange *pResource, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams, const struct NVOC_EXPORTED_METHOD_DEF **ppEntry) { - return resControlLookup((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_VirtualMemoryRange_RsResource.offset), pParams, ppEntry); +static void __nvoc_thunk_RmResource_vmrangeControlSerialization_Epilogue(struct VirtualMemoryRange *pResource, CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + rmresControlSerialization_Epilogue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_VirtualMemoryRange_RmResource.offset), pCallContext, pParams); } static NV_STATUS __nvoc_thunk_Memory_vmrangeMap(struct VirtualMemoryRange *pMemory, CALL_CONTEXT *pCallContext, struct RS_CPU_MAP_PARAMS *pParams, RsCpuMapping *pCpuMapping) { @@ -245,43 +253,47 @@ pThis->__vmrangeMapTo__ = &__nvoc_thunk_VirtualMemory_vmrangeMapTo; - pThis->__vmrangeControl__ = &__nvoc_thunk_Memory_vmrangeControl; + pThis->__vmrangeShareCallback__ = &__nvoc_thunk_RmResource_vmrangeShareCallback; - pThis->__vmrangeGetMemInterMapParams__ = &__nvoc_thunk_Memory_vmrangeGetMemInterMapParams; + pThis->__vmrangeGetMapAddrSpace__ = &__nvoc_thunk_Memory_vmrangeGetMapAddrSpace; - pThis->__vmrangeUnmap__ = &__nvoc_thunk_Memory_vmrangeUnmap; + pThis->__vmrangeGetRefCount__ = &__nvoc_thunk_RsResource_vmrangeGetRefCount; - pThis->__vmrangeGetMapAddrSpace__ = &__nvoc_thunk_Memory_vmrangeGetMapAddrSpace; + pThis->__vmrangeAddAdditionalDependants__ = &__nvoc_thunk_RsResource_vmrangeAddAdditionalDependants; - pThis->__vmrangeShareCallback__ = &__nvoc_thunk_RmResource_vmrangeShareCallback; + pThis->__vmrangeControl_Prologue__ = &__nvoc_thunk_RmResource_vmrangeControl_Prologue; - pThis->__vmrangeGetMemoryMappingDescriptor__ = &__nvoc_thunk_Memory_vmrangeGetMemoryMappingDescriptor; + pThis->__vmrangeIsGpuMapAllowed__ = &__nvoc_thunk_Memory_vmrangeIsGpuMapAllowed; - pThis->__vmrangeControlFilter__ = &__nvoc_thunk_RsResource_vmrangeControlFilter; + pThis->__vmrangeUnmapFrom__ = &__nvoc_thunk_VirtualMemory_vmrangeUnmapFrom; - pThis->__vmrangeGetRefCount__ = &__nvoc_thunk_RsResource_vmrangeGetRefCount; + pThis->__vmrangeControl_Epilogue__ = &__nvoc_thunk_RmResource_vmrangeControl_Epilogue; - pThis->__vmrangeAddAdditionalDependants__ = &__nvoc_thunk_RsResource_vmrangeAddAdditionalDependants; + pThis->__vmrangeControlLookup__ = &__nvoc_thunk_RsResource_vmrangeControlLookup; - pThis->__vmrangeCanCopy__ = &__nvoc_thunk_StandardMemory_vmrangeCanCopy; + pThis->__vmrangeControl__ = &__nvoc_thunk_Memory_vmrangeControl; - pThis->__vmrangeIsGpuMapAllowed__ = &__nvoc_thunk_Memory_vmrangeIsGpuMapAllowed; + pThis->__vmrangeUnmap__ = &__nvoc_thunk_Memory_vmrangeUnmap; - pThis->__vmrangeControl_Prologue__ = &__nvoc_thunk_RmResource_vmrangeControl_Prologue; + pThis->__vmrangeGetMemInterMapParams__ = &__nvoc_thunk_Memory_vmrangeGetMemInterMapParams; - pThis->__vmrangeIsReady__ = &__nvoc_thunk_Memory_vmrangeIsReady; + pThis->__vmrangeGetMemoryMappingDescriptor__ = &__nvoc_thunk_Memory_vmrangeGetMemoryMappingDescriptor; - pThis->__vmrangeUnmapFrom__ = &__nvoc_thunk_VirtualMemory_vmrangeUnmapFrom; + pThis->__vmrangeControlFilter__ = &__nvoc_thunk_RsResource_vmrangeControlFilter; - pThis->__vmrangeCheckCopyPermissions__ = &__nvoc_thunk_Memory_vmrangeCheckCopyPermissions; + pThis->__vmrangeControlSerialization_Prologue__ = &__nvoc_thunk_RmResource_vmrangeControlSerialization_Prologue; - pThis->__vmrangeIsDuplicate__ = &__nvoc_thunk_Memory_vmrangeIsDuplicate; + pThis->__vmrangeCanCopy__ = &__nvoc_thunk_StandardMemory_vmrangeCanCopy; + + pThis->__vmrangeIsReady__ = &__nvoc_thunk_Memory_vmrangeIsReady; + + pThis->__vmrangeCheckCopyPermissions__ = &__nvoc_thunk_Memory_vmrangeCheckCopyPermissions; pThis->__vmrangePreDestruct__ = &__nvoc_thunk_RsResource_vmrangePreDestruct; - pThis->__vmrangeControl_Epilogue__ = &__nvoc_thunk_RmResource_vmrangeControl_Epilogue; + pThis->__vmrangeIsDuplicate__ = &__nvoc_thunk_Memory_vmrangeIsDuplicate; - pThis->__vmrangeControlLookup__ = &__nvoc_thunk_RsResource_vmrangeControlLookup; + pThis->__vmrangeControlSerialization_Epilogue__ = &__nvoc_thunk_RmResource_vmrangeControlSerialization_Epilogue; pThis->__vmrangeMap__ = &__nvoc_thunk_Memory_vmrangeMap; @@ -311,13 +323,16 @@ Object *pParentObj; VirtualMemoryRange *pThis; - pThis = portMemAllocNonPaged(sizeof(VirtualMemoryRange)); - if (pThis == NULL) return NV_ERR_NO_MEMORY; + status = __nvoc_handleObjCreateMemAlloc(createFlags, sizeof(VirtualMemoryRange), (void**)&pThis, (void**)ppThis); + if (status != NV_OK) + return status; portMemSet(pThis, 0, sizeof(VirtualMemoryRange)); __nvoc_initRtti(staticCast(pThis, Dynamic), &__nvoc_class_def_VirtualMemoryRange); + pThis->__nvoc_base_VirtualMemory.__nvoc_base_StandardMemory.__nvoc_base_Memory.__nvoc_base_RmResource.__nvoc_base_RsResource.__nvoc_base_Object.createFlags = createFlags; + if (pParent != NULL && !(createFlags & NVOC_OBJ_CREATE_FLAGS_PARENT_HALSPEC_ONLY)) { pParentObj = dynamicCast(pParent, Object); @@ -333,11 +348,17 @@ if (status != NV_OK) goto __nvoc_objCreate_VirtualMemoryRange_cleanup; *ppThis = pThis; + return NV_OK; __nvoc_objCreate_VirtualMemoryRange_cleanup: // do not call destructors here since the constructor already called them - portMemFree(pThis); + if (createFlags & NVOC_OBJ_CREATE_FLAGS_IN_PLACE_CONSTRUCT) + portMemSet(pThis, 0, sizeof(VirtualMemoryRange)); + else + portMemFree(pThis); + + // coverity[leaked_storage:FALSE] return status; } diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/generated/g_virt_mem_range_nvoc.h nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_virt_mem_range_nvoc.h --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/generated/g_virt_mem_range_nvoc.h 2023-10-25 20:27:24.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_virt_mem_range_nvoc.h 2024-03-05 22:18:52.000000000 +0000 @@ -60,25 +60,27 @@ struct VirtualMemoryRange *__nvoc_pbase_VirtualMemoryRange; NV_STATUS (*__vmrangeCheckMemInterUnmap__)(struct VirtualMemoryRange *, NvBool); NV_STATUS (*__vmrangeMapTo__)(struct VirtualMemoryRange *, struct RS_RES_MAP_TO_PARAMS *); - NV_STATUS (*__vmrangeControl__)(struct VirtualMemoryRange *, CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); - NV_STATUS (*__vmrangeGetMemInterMapParams__)(struct VirtualMemoryRange *, RMRES_MEM_INTER_MAP_PARAMS *); - NV_STATUS (*__vmrangeUnmap__)(struct VirtualMemoryRange *, CALL_CONTEXT *, RsCpuMapping *); - NV_STATUS (*__vmrangeGetMapAddrSpace__)(struct VirtualMemoryRange *, CALL_CONTEXT *, NvU32, NV_ADDRESS_SPACE *); NvBool (*__vmrangeShareCallback__)(struct VirtualMemoryRange *, struct RsClient *, struct RsResourceRef *, RS_SHARE_POLICY *); - NV_STATUS (*__vmrangeGetMemoryMappingDescriptor__)(struct VirtualMemoryRange *, MEMORY_DESCRIPTOR **); - NV_STATUS (*__vmrangeControlFilter__)(struct VirtualMemoryRange *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); + NV_STATUS (*__vmrangeGetMapAddrSpace__)(struct VirtualMemoryRange *, CALL_CONTEXT *, NvU32, NV_ADDRESS_SPACE *); NvU32 (*__vmrangeGetRefCount__)(struct VirtualMemoryRange *); void (*__vmrangeAddAdditionalDependants__)(struct RsClient *, struct VirtualMemoryRange *, RsResourceRef *); - NvBool (*__vmrangeCanCopy__)(struct VirtualMemoryRange *); - NvBool (*__vmrangeIsGpuMapAllowed__)(struct VirtualMemoryRange *, struct OBJGPU *); NV_STATUS (*__vmrangeControl_Prologue__)(struct VirtualMemoryRange *, CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); - NV_STATUS (*__vmrangeIsReady__)(struct VirtualMemoryRange *, NvBool); + NvBool (*__vmrangeIsGpuMapAllowed__)(struct VirtualMemoryRange *, struct OBJGPU *); NV_STATUS (*__vmrangeUnmapFrom__)(struct VirtualMemoryRange *, struct RS_RES_UNMAP_FROM_PARAMS *); - NV_STATUS (*__vmrangeCheckCopyPermissions__)(struct VirtualMemoryRange *, struct OBJGPU *, NvHandle); - NV_STATUS (*__vmrangeIsDuplicate__)(struct VirtualMemoryRange *, NvHandle, NvBool *); - void (*__vmrangePreDestruct__)(struct VirtualMemoryRange *); void (*__vmrangeControl_Epilogue__)(struct VirtualMemoryRange *, CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); NV_STATUS (*__vmrangeControlLookup__)(struct VirtualMemoryRange *, struct RS_RES_CONTROL_PARAMS_INTERNAL *, const struct NVOC_EXPORTED_METHOD_DEF **); + NV_STATUS (*__vmrangeControl__)(struct VirtualMemoryRange *, CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); + NV_STATUS (*__vmrangeUnmap__)(struct VirtualMemoryRange *, CALL_CONTEXT *, RsCpuMapping *); + NV_STATUS (*__vmrangeGetMemInterMapParams__)(struct VirtualMemoryRange *, RMRES_MEM_INTER_MAP_PARAMS *); + NV_STATUS (*__vmrangeGetMemoryMappingDescriptor__)(struct VirtualMemoryRange *, MEMORY_DESCRIPTOR **); + NV_STATUS (*__vmrangeControlFilter__)(struct VirtualMemoryRange *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); + NV_STATUS (*__vmrangeControlSerialization_Prologue__)(struct VirtualMemoryRange *, CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); + NvBool (*__vmrangeCanCopy__)(struct VirtualMemoryRange *); + NV_STATUS (*__vmrangeIsReady__)(struct VirtualMemoryRange *, NvBool); + NV_STATUS (*__vmrangeCheckCopyPermissions__)(struct VirtualMemoryRange *, struct OBJGPU *, struct Device *); + void (*__vmrangePreDestruct__)(struct VirtualMemoryRange *); + NV_STATUS (*__vmrangeIsDuplicate__)(struct VirtualMemoryRange *, NvHandle, NvBool *); + void (*__vmrangeControlSerialization_Epilogue__)(struct VirtualMemoryRange *, CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); NV_STATUS (*__vmrangeMap__)(struct VirtualMemoryRange *, CALL_CONTEXT *, struct RS_CPU_MAP_PARAMS *, RsCpuMapping *); NvBool (*__vmrangeAccessCallback__)(struct VirtualMemoryRange *, struct RsClient *, void *, RsAccessRight); }; @@ -113,25 +115,27 @@ #define vmrangeCheckMemInterUnmap(pMemory, bSubdeviceHandleProvided) vmrangeCheckMemInterUnmap_DISPATCH(pMemory, bSubdeviceHandleProvided) #define vmrangeMapTo(pVirtualMemory, pParams) vmrangeMapTo_DISPATCH(pVirtualMemory, pParams) -#define vmrangeControl(pMemory, pCallContext, pParams) vmrangeControl_DISPATCH(pMemory, pCallContext, pParams) -#define vmrangeGetMemInterMapParams(pMemory, pParams) vmrangeGetMemInterMapParams_DISPATCH(pMemory, pParams) -#define vmrangeUnmap(pMemory, pCallContext, pCpuMapping) vmrangeUnmap_DISPATCH(pMemory, pCallContext, pCpuMapping) -#define vmrangeGetMapAddrSpace(pMemory, pCallContext, mapFlags, pAddrSpace) vmrangeGetMapAddrSpace_DISPATCH(pMemory, pCallContext, mapFlags, pAddrSpace) #define vmrangeShareCallback(pResource, pInvokingClient, pParentRef, pSharePolicy) vmrangeShareCallback_DISPATCH(pResource, pInvokingClient, pParentRef, pSharePolicy) -#define vmrangeGetMemoryMappingDescriptor(pMemory, ppMemDesc) vmrangeGetMemoryMappingDescriptor_DISPATCH(pMemory, ppMemDesc) -#define vmrangeControlFilter(pResource, pCallContext, pParams) vmrangeControlFilter_DISPATCH(pResource, pCallContext, pParams) +#define vmrangeGetMapAddrSpace(pMemory, pCallContext, mapFlags, pAddrSpace) vmrangeGetMapAddrSpace_DISPATCH(pMemory, pCallContext, mapFlags, pAddrSpace) #define vmrangeGetRefCount(pResource) vmrangeGetRefCount_DISPATCH(pResource) #define vmrangeAddAdditionalDependants(pClient, pResource, pReference) vmrangeAddAdditionalDependants_DISPATCH(pClient, pResource, pReference) -#define vmrangeCanCopy(pStandardMemory) vmrangeCanCopy_DISPATCH(pStandardMemory) -#define vmrangeIsGpuMapAllowed(pMemory, pGpu) vmrangeIsGpuMapAllowed_DISPATCH(pMemory, pGpu) #define vmrangeControl_Prologue(pResource, pCallContext, pParams) vmrangeControl_Prologue_DISPATCH(pResource, pCallContext, pParams) -#define vmrangeIsReady(pMemory, bCopyConstructorContext) vmrangeIsReady_DISPATCH(pMemory, bCopyConstructorContext) +#define vmrangeIsGpuMapAllowed(pMemory, pGpu) vmrangeIsGpuMapAllowed_DISPATCH(pMemory, pGpu) #define vmrangeUnmapFrom(pVirtualMemory, pParams) vmrangeUnmapFrom_DISPATCH(pVirtualMemory, pParams) -#define vmrangeCheckCopyPermissions(pMemory, pDstGpu, hDstClientNvBool) vmrangeCheckCopyPermissions_DISPATCH(pMemory, pDstGpu, hDstClientNvBool) -#define vmrangeIsDuplicate(pMemory, hMemory, pDuplicate) vmrangeIsDuplicate_DISPATCH(pMemory, hMemory, pDuplicate) -#define vmrangePreDestruct(pResource) vmrangePreDestruct_DISPATCH(pResource) #define vmrangeControl_Epilogue(pResource, pCallContext, pParams) vmrangeControl_Epilogue_DISPATCH(pResource, pCallContext, pParams) #define vmrangeControlLookup(pResource, pParams, ppEntry) vmrangeControlLookup_DISPATCH(pResource, pParams, ppEntry) +#define vmrangeControl(pMemory, pCallContext, pParams) vmrangeControl_DISPATCH(pMemory, pCallContext, pParams) +#define vmrangeUnmap(pMemory, pCallContext, pCpuMapping) vmrangeUnmap_DISPATCH(pMemory, pCallContext, pCpuMapping) +#define vmrangeGetMemInterMapParams(pMemory, pParams) vmrangeGetMemInterMapParams_DISPATCH(pMemory, pParams) +#define vmrangeGetMemoryMappingDescriptor(pMemory, ppMemDesc) vmrangeGetMemoryMappingDescriptor_DISPATCH(pMemory, ppMemDesc) +#define vmrangeControlFilter(pResource, pCallContext, pParams) vmrangeControlFilter_DISPATCH(pResource, pCallContext, pParams) +#define vmrangeControlSerialization_Prologue(pResource, pCallContext, pParams) vmrangeControlSerialization_Prologue_DISPATCH(pResource, pCallContext, pParams) +#define vmrangeCanCopy(pStandardMemory) vmrangeCanCopy_DISPATCH(pStandardMemory) +#define vmrangeIsReady(pMemory, bCopyConstructorContext) vmrangeIsReady_DISPATCH(pMemory, bCopyConstructorContext) +#define vmrangeCheckCopyPermissions(pMemory, pDstGpu, pDstDevice) vmrangeCheckCopyPermissions_DISPATCH(pMemory, pDstGpu, pDstDevice) +#define vmrangePreDestruct(pResource) vmrangePreDestruct_DISPATCH(pResource) +#define vmrangeIsDuplicate(pMemory, hMemory, pDuplicate) vmrangeIsDuplicate_DISPATCH(pMemory, hMemory, pDuplicate) +#define vmrangeControlSerialization_Epilogue(pResource, pCallContext, pParams) vmrangeControlSerialization_Epilogue_DISPATCH(pResource, pCallContext, pParams) #define vmrangeMap(pMemory, pCallContext, pParams, pCpuMapping) vmrangeMap_DISPATCH(pMemory, pCallContext, pParams, pCpuMapping) #define vmrangeAccessCallback(pResource, pInvokingClient, pAllocParams, accessRight) vmrangeAccessCallback_DISPATCH(pResource, pInvokingClient, pAllocParams, accessRight) static inline NV_STATUS vmrangeCheckMemInterUnmap_DISPATCH(struct VirtualMemoryRange *pMemory, NvBool bSubdeviceHandleProvided) { @@ -142,80 +146,88 @@ return pVirtualMemory->__vmrangeMapTo__(pVirtualMemory, pParams); } -static inline NV_STATUS vmrangeControl_DISPATCH(struct VirtualMemoryRange *pMemory, CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { - return pMemory->__vmrangeControl__(pMemory, pCallContext, pParams); +static inline NvBool vmrangeShareCallback_DISPATCH(struct VirtualMemoryRange *pResource, struct RsClient *pInvokingClient, struct RsResourceRef *pParentRef, RS_SHARE_POLICY *pSharePolicy) { + return pResource->__vmrangeShareCallback__(pResource, pInvokingClient, pParentRef, pSharePolicy); } -static inline NV_STATUS vmrangeGetMemInterMapParams_DISPATCH(struct VirtualMemoryRange *pMemory, RMRES_MEM_INTER_MAP_PARAMS *pParams) { - return pMemory->__vmrangeGetMemInterMapParams__(pMemory, pParams); +static inline NV_STATUS vmrangeGetMapAddrSpace_DISPATCH(struct VirtualMemoryRange *pMemory, CALL_CONTEXT *pCallContext, NvU32 mapFlags, NV_ADDRESS_SPACE *pAddrSpace) { + return pMemory->__vmrangeGetMapAddrSpace__(pMemory, pCallContext, mapFlags, pAddrSpace); } -static inline NV_STATUS vmrangeUnmap_DISPATCH(struct VirtualMemoryRange *pMemory, CALL_CONTEXT *pCallContext, RsCpuMapping *pCpuMapping) { - return pMemory->__vmrangeUnmap__(pMemory, pCallContext, pCpuMapping); +static inline NvU32 vmrangeGetRefCount_DISPATCH(struct VirtualMemoryRange *pResource) { + return pResource->__vmrangeGetRefCount__(pResource); } -static inline NV_STATUS vmrangeGetMapAddrSpace_DISPATCH(struct VirtualMemoryRange *pMemory, CALL_CONTEXT *pCallContext, NvU32 mapFlags, NV_ADDRESS_SPACE *pAddrSpace) { - return pMemory->__vmrangeGetMapAddrSpace__(pMemory, pCallContext, mapFlags, pAddrSpace); +static inline void vmrangeAddAdditionalDependants_DISPATCH(struct RsClient *pClient, struct VirtualMemoryRange *pResource, RsResourceRef *pReference) { + pResource->__vmrangeAddAdditionalDependants__(pClient, pResource, pReference); } -static inline NvBool vmrangeShareCallback_DISPATCH(struct VirtualMemoryRange *pResource, struct RsClient *pInvokingClient, struct RsResourceRef *pParentRef, RS_SHARE_POLICY *pSharePolicy) { - return pResource->__vmrangeShareCallback__(pResource, pInvokingClient, pParentRef, pSharePolicy); +static inline NV_STATUS vmrangeControl_Prologue_DISPATCH(struct VirtualMemoryRange *pResource, CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return pResource->__vmrangeControl_Prologue__(pResource, pCallContext, pParams); } -static inline NV_STATUS vmrangeGetMemoryMappingDescriptor_DISPATCH(struct VirtualMemoryRange *pMemory, MEMORY_DESCRIPTOR **ppMemDesc) { - return pMemory->__vmrangeGetMemoryMappingDescriptor__(pMemory, ppMemDesc); +static inline NvBool vmrangeIsGpuMapAllowed_DISPATCH(struct VirtualMemoryRange *pMemory, struct OBJGPU *pGpu) { + return pMemory->__vmrangeIsGpuMapAllowed__(pMemory, pGpu); } -static inline NV_STATUS vmrangeControlFilter_DISPATCH(struct VirtualMemoryRange *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { - return pResource->__vmrangeControlFilter__(pResource, pCallContext, pParams); +static inline NV_STATUS vmrangeUnmapFrom_DISPATCH(struct VirtualMemoryRange *pVirtualMemory, struct RS_RES_UNMAP_FROM_PARAMS *pParams) { + return pVirtualMemory->__vmrangeUnmapFrom__(pVirtualMemory, pParams); } -static inline NvU32 vmrangeGetRefCount_DISPATCH(struct VirtualMemoryRange *pResource) { - return pResource->__vmrangeGetRefCount__(pResource); +static inline void vmrangeControl_Epilogue_DISPATCH(struct VirtualMemoryRange *pResource, CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + pResource->__vmrangeControl_Epilogue__(pResource, pCallContext, pParams); } -static inline void vmrangeAddAdditionalDependants_DISPATCH(struct RsClient *pClient, struct VirtualMemoryRange *pResource, RsResourceRef *pReference) { - pResource->__vmrangeAddAdditionalDependants__(pClient, pResource, pReference); +static inline NV_STATUS vmrangeControlLookup_DISPATCH(struct VirtualMemoryRange *pResource, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams, const struct NVOC_EXPORTED_METHOD_DEF **ppEntry) { + return pResource->__vmrangeControlLookup__(pResource, pParams, ppEntry); } -static inline NvBool vmrangeCanCopy_DISPATCH(struct VirtualMemoryRange *pStandardMemory) { - return pStandardMemory->__vmrangeCanCopy__(pStandardMemory); +static inline NV_STATUS vmrangeControl_DISPATCH(struct VirtualMemoryRange *pMemory, CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return pMemory->__vmrangeControl__(pMemory, pCallContext, pParams); } -static inline NvBool vmrangeIsGpuMapAllowed_DISPATCH(struct VirtualMemoryRange *pMemory, struct OBJGPU *pGpu) { - return pMemory->__vmrangeIsGpuMapAllowed__(pMemory, pGpu); +static inline NV_STATUS vmrangeUnmap_DISPATCH(struct VirtualMemoryRange *pMemory, CALL_CONTEXT *pCallContext, RsCpuMapping *pCpuMapping) { + return pMemory->__vmrangeUnmap__(pMemory, pCallContext, pCpuMapping); } -static inline NV_STATUS vmrangeControl_Prologue_DISPATCH(struct VirtualMemoryRange *pResource, CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { - return pResource->__vmrangeControl_Prologue__(pResource, pCallContext, pParams); +static inline NV_STATUS vmrangeGetMemInterMapParams_DISPATCH(struct VirtualMemoryRange *pMemory, RMRES_MEM_INTER_MAP_PARAMS *pParams) { + return pMemory->__vmrangeGetMemInterMapParams__(pMemory, pParams); } -static inline NV_STATUS vmrangeIsReady_DISPATCH(struct VirtualMemoryRange *pMemory, NvBool bCopyConstructorContext) { - return pMemory->__vmrangeIsReady__(pMemory, bCopyConstructorContext); +static inline NV_STATUS vmrangeGetMemoryMappingDescriptor_DISPATCH(struct VirtualMemoryRange *pMemory, MEMORY_DESCRIPTOR **ppMemDesc) { + return pMemory->__vmrangeGetMemoryMappingDescriptor__(pMemory, ppMemDesc); } -static inline NV_STATUS vmrangeUnmapFrom_DISPATCH(struct VirtualMemoryRange *pVirtualMemory, struct RS_RES_UNMAP_FROM_PARAMS *pParams) { - return pVirtualMemory->__vmrangeUnmapFrom__(pVirtualMemory, pParams); +static inline NV_STATUS vmrangeControlFilter_DISPATCH(struct VirtualMemoryRange *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return pResource->__vmrangeControlFilter__(pResource, pCallContext, pParams); } -static inline NV_STATUS vmrangeCheckCopyPermissions_DISPATCH(struct VirtualMemoryRange *pMemory, struct OBJGPU *pDstGpu, NvHandle hDstClientNvBool) { - return pMemory->__vmrangeCheckCopyPermissions__(pMemory, pDstGpu, hDstClientNvBool); +static inline NV_STATUS vmrangeControlSerialization_Prologue_DISPATCH(struct VirtualMemoryRange *pResource, CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return pResource->__vmrangeControlSerialization_Prologue__(pResource, pCallContext, pParams); } -static inline NV_STATUS vmrangeIsDuplicate_DISPATCH(struct VirtualMemoryRange *pMemory, NvHandle hMemory, NvBool *pDuplicate) { - return pMemory->__vmrangeIsDuplicate__(pMemory, hMemory, pDuplicate); +static inline NvBool vmrangeCanCopy_DISPATCH(struct VirtualMemoryRange *pStandardMemory) { + return pStandardMemory->__vmrangeCanCopy__(pStandardMemory); +} + +static inline NV_STATUS vmrangeIsReady_DISPATCH(struct VirtualMemoryRange *pMemory, NvBool bCopyConstructorContext) { + return pMemory->__vmrangeIsReady__(pMemory, bCopyConstructorContext); +} + +static inline NV_STATUS vmrangeCheckCopyPermissions_DISPATCH(struct VirtualMemoryRange *pMemory, struct OBJGPU *pDstGpu, struct Device *pDstDevice) { + return pMemory->__vmrangeCheckCopyPermissions__(pMemory, pDstGpu, pDstDevice); } static inline void vmrangePreDestruct_DISPATCH(struct VirtualMemoryRange *pResource) { pResource->__vmrangePreDestruct__(pResource); } -static inline void vmrangeControl_Epilogue_DISPATCH(struct VirtualMemoryRange *pResource, CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { - pResource->__vmrangeControl_Epilogue__(pResource, pCallContext, pParams); +static inline NV_STATUS vmrangeIsDuplicate_DISPATCH(struct VirtualMemoryRange *pMemory, NvHandle hMemory, NvBool *pDuplicate) { + return pMemory->__vmrangeIsDuplicate__(pMemory, hMemory, pDuplicate); } -static inline NV_STATUS vmrangeControlLookup_DISPATCH(struct VirtualMemoryRange *pResource, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams, const struct NVOC_EXPORTED_METHOD_DEF **ppEntry) { - return pResource->__vmrangeControlLookup__(pResource, pParams, ppEntry); +static inline void vmrangeControlSerialization_Epilogue_DISPATCH(struct VirtualMemoryRange *pResource, CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + pResource->__vmrangeControlSerialization_Epilogue__(pResource, pCallContext, pParams); } static inline NV_STATUS vmrangeMap_DISPATCH(struct VirtualMemoryRange *pMemory, CALL_CONTEXT *pCallContext, struct RS_CPU_MAP_PARAMS *pParams, RsCpuMapping *pCpuMapping) { diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/generated/g_virtual_mem_nvoc.c nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_virtual_mem_nvoc.c --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/generated/g_virtual_mem_nvoc.c 2023-10-25 20:27:24.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_virtual_mem_nvoc.c 2024-03-05 22:18:53.000000000 +0000 @@ -114,6 +114,38 @@ return memCheckMemInterUnmap((struct Memory *)(((unsigned char *)pMemory) + __nvoc_rtti_VirtualMemory_Memory.offset), bSubdeviceHandleProvided); } +static NvBool __nvoc_thunk_RmResource_virtmemShareCallback(struct VirtualMemory *pResource, struct RsClient *pInvokingClient, struct RsResourceRef *pParentRef, RS_SHARE_POLICY *pSharePolicy) { + return rmresShareCallback((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_VirtualMemory_RmResource.offset), pInvokingClient, pParentRef, pSharePolicy); +} + +static NV_STATUS __nvoc_thunk_Memory_virtmemGetMapAddrSpace(struct VirtualMemory *pMemory, CALL_CONTEXT *pCallContext, NvU32 mapFlags, NV_ADDRESS_SPACE *pAddrSpace) { + return memGetMapAddrSpace((struct Memory *)(((unsigned char *)pMemory) + __nvoc_rtti_VirtualMemory_Memory.offset), pCallContext, mapFlags, pAddrSpace); +} + +static NvU32 __nvoc_thunk_RsResource_virtmemGetRefCount(struct VirtualMemory *pResource) { + return resGetRefCount((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_VirtualMemory_RsResource.offset)); +} + +static void __nvoc_thunk_RsResource_virtmemAddAdditionalDependants(struct RsClient *pClient, struct VirtualMemory *pResource, RsResourceRef *pReference) { + resAddAdditionalDependants(pClient, (struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_VirtualMemory_RsResource.offset), pReference); +} + +static NV_STATUS __nvoc_thunk_RmResource_virtmemControl_Prologue(struct VirtualMemory *pResource, CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return rmresControl_Prologue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_VirtualMemory_RmResource.offset), pCallContext, pParams); +} + +static NvBool __nvoc_thunk_Memory_virtmemIsGpuMapAllowed(struct VirtualMemory *pMemory, struct OBJGPU *pGpu) { + return memIsGpuMapAllowed((struct Memory *)(((unsigned char *)pMemory) + __nvoc_rtti_VirtualMemory_Memory.offset), pGpu); +} + +static void __nvoc_thunk_RmResource_virtmemControl_Epilogue(struct VirtualMemory *pResource, CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + rmresControl_Epilogue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_VirtualMemory_RmResource.offset), pCallContext, pParams); +} + +static NV_STATUS __nvoc_thunk_RsResource_virtmemControlLookup(struct VirtualMemory *pResource, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams, const struct NVOC_EXPORTED_METHOD_DEF **ppEntry) { + return resControlLookup((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_VirtualMemory_RsResource.offset), pParams, ppEntry); +} + static NV_STATUS __nvoc_thunk_Memory_virtmemControl(struct VirtualMemory *pMemory, CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { return memControl((struct Memory *)(((unsigned char *)pMemory) + __nvoc_rtti_VirtualMemory_Memory.offset), pCallContext, pParams); } @@ -130,44 +162,24 @@ return memGetMemoryMappingDescriptor((struct Memory *)(((unsigned char *)pMemory) + __nvoc_rtti_VirtualMemory_Memory.offset), ppMemDesc); } -static NV_STATUS __nvoc_thunk_Memory_virtmemGetMapAddrSpace(struct VirtualMemory *pMemory, CALL_CONTEXT *pCallContext, NvU32 mapFlags, NV_ADDRESS_SPACE *pAddrSpace) { - return memGetMapAddrSpace((struct Memory *)(((unsigned char *)pMemory) + __nvoc_rtti_VirtualMemory_Memory.offset), pCallContext, mapFlags, pAddrSpace); -} - -static NvBool __nvoc_thunk_RmResource_virtmemShareCallback(struct VirtualMemory *pResource, struct RsClient *pInvokingClient, struct RsResourceRef *pParentRef, RS_SHARE_POLICY *pSharePolicy) { - return rmresShareCallback((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_VirtualMemory_RmResource.offset), pInvokingClient, pParentRef, pSharePolicy); -} - static NV_STATUS __nvoc_thunk_RsResource_virtmemControlFilter(struct VirtualMemory *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { return resControlFilter((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_VirtualMemory_RsResource.offset), pCallContext, pParams); } -static void __nvoc_thunk_RsResource_virtmemAddAdditionalDependants(struct RsClient *pClient, struct VirtualMemory *pResource, RsResourceRef *pReference) { - resAddAdditionalDependants(pClient, (struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_VirtualMemory_RsResource.offset), pReference); -} - -static NvU32 __nvoc_thunk_RsResource_virtmemGetRefCount(struct VirtualMemory *pResource) { - return resGetRefCount((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_VirtualMemory_RsResource.offset)); +static NV_STATUS __nvoc_thunk_RmResource_virtmemControlSerialization_Prologue(struct VirtualMemory *pResource, CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return rmresControlSerialization_Prologue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_VirtualMemory_RmResource.offset), pCallContext, pParams); } static NvBool __nvoc_thunk_StandardMemory_virtmemCanCopy(struct VirtualMemory *pStandardMemory) { return stdmemCanCopy((struct StandardMemory *)(((unsigned char *)pStandardMemory) + __nvoc_rtti_VirtualMemory_StandardMemory.offset)); } -static NvBool __nvoc_thunk_Memory_virtmemIsGpuMapAllowed(struct VirtualMemory *pMemory, struct OBJGPU *pGpu) { - return memIsGpuMapAllowed((struct Memory *)(((unsigned char *)pMemory) + __nvoc_rtti_VirtualMemory_Memory.offset), pGpu); -} - -static NV_STATUS __nvoc_thunk_RmResource_virtmemControl_Prologue(struct VirtualMemory *pResource, CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { - return rmresControl_Prologue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_VirtualMemory_RmResource.offset), pCallContext, pParams); -} - static NV_STATUS __nvoc_thunk_Memory_virtmemIsReady(struct VirtualMemory *pMemory, NvBool bCopyConstructorContext) { return memIsReady((struct Memory *)(((unsigned char *)pMemory) + __nvoc_rtti_VirtualMemory_Memory.offset), bCopyConstructorContext); } -static NV_STATUS __nvoc_thunk_Memory_virtmemCheckCopyPermissions(struct VirtualMemory *pMemory, struct OBJGPU *pDstGpu, NvHandle hDstClientNvBool) { - return memCheckCopyPermissions((struct Memory *)(((unsigned char *)pMemory) + __nvoc_rtti_VirtualMemory_Memory.offset), pDstGpu, hDstClientNvBool); +static NV_STATUS __nvoc_thunk_Memory_virtmemCheckCopyPermissions(struct VirtualMemory *pMemory, struct OBJGPU *pDstGpu, struct Device *pDstDevice) { + return memCheckCopyPermissions((struct Memory *)(((unsigned char *)pMemory) + __nvoc_rtti_VirtualMemory_Memory.offset), pDstGpu, pDstDevice); } static void __nvoc_thunk_RsResource_virtmemPreDestruct(struct VirtualMemory *pResource) { @@ -178,12 +190,8 @@ return memIsDuplicate((struct Memory *)(((unsigned char *)pMemory) + __nvoc_rtti_VirtualMemory_Memory.offset), hMemory, pDuplicate); } -static void __nvoc_thunk_RmResource_virtmemControl_Epilogue(struct VirtualMemory *pResource, CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { - rmresControl_Epilogue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_VirtualMemory_RmResource.offset), pCallContext, pParams); -} - -static NV_STATUS __nvoc_thunk_RsResource_virtmemControlLookup(struct VirtualMemory *pResource, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams, const struct NVOC_EXPORTED_METHOD_DEF **ppEntry) { - return resControlLookup((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_VirtualMemory_RsResource.offset), pParams, ppEntry); +static void __nvoc_thunk_RmResource_virtmemControlSerialization_Epilogue(struct VirtualMemory *pResource, CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + rmresControlSerialization_Epilogue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_VirtualMemory_RmResource.offset), pCallContext, pParams); } static NV_STATUS __nvoc_thunk_Memory_virtmemMap(struct VirtualMemory *pMemory, CALL_CONTEXT *pCallContext, struct RS_CPU_MAP_PARAMS *pParams, RsCpuMapping *pCpuMapping) { @@ -243,6 +251,22 @@ pThis->__virtmemCheckMemInterUnmap__ = &__nvoc_thunk_Memory_virtmemCheckMemInterUnmap; + pThis->__virtmemShareCallback__ = &__nvoc_thunk_RmResource_virtmemShareCallback; + + pThis->__virtmemGetMapAddrSpace__ = &__nvoc_thunk_Memory_virtmemGetMapAddrSpace; + + pThis->__virtmemGetRefCount__ = &__nvoc_thunk_RsResource_virtmemGetRefCount; + + pThis->__virtmemAddAdditionalDependants__ = &__nvoc_thunk_RsResource_virtmemAddAdditionalDependants; + + pThis->__virtmemControl_Prologue__ = &__nvoc_thunk_RmResource_virtmemControl_Prologue; + + pThis->__virtmemIsGpuMapAllowed__ = &__nvoc_thunk_Memory_virtmemIsGpuMapAllowed; + + pThis->__virtmemControl_Epilogue__ = &__nvoc_thunk_RmResource_virtmemControl_Epilogue; + + pThis->__virtmemControlLookup__ = &__nvoc_thunk_RsResource_virtmemControlLookup; + pThis->__virtmemControl__ = &__nvoc_thunk_Memory_virtmemControl; pThis->__virtmemUnmap__ = &__nvoc_thunk_Memory_virtmemUnmap; @@ -251,22 +275,12 @@ pThis->__virtmemGetMemoryMappingDescriptor__ = &__nvoc_thunk_Memory_virtmemGetMemoryMappingDescriptor; - pThis->__virtmemGetMapAddrSpace__ = &__nvoc_thunk_Memory_virtmemGetMapAddrSpace; - - pThis->__virtmemShareCallback__ = &__nvoc_thunk_RmResource_virtmemShareCallback; - pThis->__virtmemControlFilter__ = &__nvoc_thunk_RsResource_virtmemControlFilter; - pThis->__virtmemAddAdditionalDependants__ = &__nvoc_thunk_RsResource_virtmemAddAdditionalDependants; - - pThis->__virtmemGetRefCount__ = &__nvoc_thunk_RsResource_virtmemGetRefCount; + pThis->__virtmemControlSerialization_Prologue__ = &__nvoc_thunk_RmResource_virtmemControlSerialization_Prologue; pThis->__virtmemCanCopy__ = &__nvoc_thunk_StandardMemory_virtmemCanCopy; - pThis->__virtmemIsGpuMapAllowed__ = &__nvoc_thunk_Memory_virtmemIsGpuMapAllowed; - - pThis->__virtmemControl_Prologue__ = &__nvoc_thunk_RmResource_virtmemControl_Prologue; - pThis->__virtmemIsReady__ = &__nvoc_thunk_Memory_virtmemIsReady; pThis->__virtmemCheckCopyPermissions__ = &__nvoc_thunk_Memory_virtmemCheckCopyPermissions; @@ -275,9 +289,7 @@ pThis->__virtmemIsDuplicate__ = &__nvoc_thunk_Memory_virtmemIsDuplicate; - pThis->__virtmemControl_Epilogue__ = &__nvoc_thunk_RmResource_virtmemControl_Epilogue; - - pThis->__virtmemControlLookup__ = &__nvoc_thunk_RsResource_virtmemControlLookup; + pThis->__virtmemControlSerialization_Epilogue__ = &__nvoc_thunk_RmResource_virtmemControlSerialization_Epilogue; pThis->__virtmemMap__ = &__nvoc_thunk_Memory_virtmemMap; @@ -306,13 +318,16 @@ Object *pParentObj; VirtualMemory *pThis; - pThis = portMemAllocNonPaged(sizeof(VirtualMemory)); - if (pThis == NULL) return NV_ERR_NO_MEMORY; + status = __nvoc_handleObjCreateMemAlloc(createFlags, sizeof(VirtualMemory), (void**)&pThis, (void**)ppThis); + if (status != NV_OK) + return status; portMemSet(pThis, 0, sizeof(VirtualMemory)); __nvoc_initRtti(staticCast(pThis, Dynamic), &__nvoc_class_def_VirtualMemory); + pThis->__nvoc_base_StandardMemory.__nvoc_base_Memory.__nvoc_base_RmResource.__nvoc_base_RsResource.__nvoc_base_Object.createFlags = createFlags; + if (pParent != NULL && !(createFlags & NVOC_OBJ_CREATE_FLAGS_PARENT_HALSPEC_ONLY)) { pParentObj = dynamicCast(pParent, Object); @@ -328,11 +343,17 @@ if (status != NV_OK) goto __nvoc_objCreate_VirtualMemory_cleanup; *ppThis = pThis; + return NV_OK; __nvoc_objCreate_VirtualMemory_cleanup: // do not call destructors here since the constructor already called them - portMemFree(pThis); + if (createFlags & NVOC_OBJ_CREATE_FLAGS_IN_PLACE_CONSTRUCT) + portMemSet(pThis, 0, sizeof(VirtualMemory)); + else + portMemFree(pThis); + + // coverity[leaked_storage:FALSE] return status; } diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/generated/g_virtual_mem_nvoc.h nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_virtual_mem_nvoc.h --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/generated/g_virtual_mem_nvoc.h 2023-10-25 20:27:24.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_virtual_mem_nvoc.h 2024-03-05 22:18:53.000000000 +0000 @@ -63,24 +63,26 @@ NV_STATUS (*__virtmemMapTo__)(struct VirtualMemory *, struct RS_RES_MAP_TO_PARAMS *); NV_STATUS (*__virtmemUnmapFrom__)(struct VirtualMemory *, struct RS_RES_UNMAP_FROM_PARAMS *); NV_STATUS (*__virtmemCheckMemInterUnmap__)(struct VirtualMemory *, NvBool); + NvBool (*__virtmemShareCallback__)(struct VirtualMemory *, struct RsClient *, struct RsResourceRef *, RS_SHARE_POLICY *); + NV_STATUS (*__virtmemGetMapAddrSpace__)(struct VirtualMemory *, CALL_CONTEXT *, NvU32, NV_ADDRESS_SPACE *); + NvU32 (*__virtmemGetRefCount__)(struct VirtualMemory *); + void (*__virtmemAddAdditionalDependants__)(struct RsClient *, struct VirtualMemory *, RsResourceRef *); + NV_STATUS (*__virtmemControl_Prologue__)(struct VirtualMemory *, CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); + NvBool (*__virtmemIsGpuMapAllowed__)(struct VirtualMemory *, struct OBJGPU *); + void (*__virtmemControl_Epilogue__)(struct VirtualMemory *, CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); + NV_STATUS (*__virtmemControlLookup__)(struct VirtualMemory *, struct RS_RES_CONTROL_PARAMS_INTERNAL *, const struct NVOC_EXPORTED_METHOD_DEF **); NV_STATUS (*__virtmemControl__)(struct VirtualMemory *, CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); NV_STATUS (*__virtmemUnmap__)(struct VirtualMemory *, CALL_CONTEXT *, RsCpuMapping *); NV_STATUS (*__virtmemGetMemInterMapParams__)(struct VirtualMemory *, RMRES_MEM_INTER_MAP_PARAMS *); NV_STATUS (*__virtmemGetMemoryMappingDescriptor__)(struct VirtualMemory *, MEMORY_DESCRIPTOR **); - NV_STATUS (*__virtmemGetMapAddrSpace__)(struct VirtualMemory *, CALL_CONTEXT *, NvU32, NV_ADDRESS_SPACE *); - NvBool (*__virtmemShareCallback__)(struct VirtualMemory *, struct RsClient *, struct RsResourceRef *, RS_SHARE_POLICY *); NV_STATUS (*__virtmemControlFilter__)(struct VirtualMemory *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); - void (*__virtmemAddAdditionalDependants__)(struct RsClient *, struct VirtualMemory *, RsResourceRef *); - NvU32 (*__virtmemGetRefCount__)(struct VirtualMemory *); + NV_STATUS (*__virtmemControlSerialization_Prologue__)(struct VirtualMemory *, CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); NvBool (*__virtmemCanCopy__)(struct VirtualMemory *); - NvBool (*__virtmemIsGpuMapAllowed__)(struct VirtualMemory *, struct OBJGPU *); - NV_STATUS (*__virtmemControl_Prologue__)(struct VirtualMemory *, CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); NV_STATUS (*__virtmemIsReady__)(struct VirtualMemory *, NvBool); - NV_STATUS (*__virtmemCheckCopyPermissions__)(struct VirtualMemory *, struct OBJGPU *, NvHandle); + NV_STATUS (*__virtmemCheckCopyPermissions__)(struct VirtualMemory *, struct OBJGPU *, struct Device *); void (*__virtmemPreDestruct__)(struct VirtualMemory *); NV_STATUS (*__virtmemIsDuplicate__)(struct VirtualMemory *, NvHandle, NvBool *); - void (*__virtmemControl_Epilogue__)(struct VirtualMemory *, CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); - NV_STATUS (*__virtmemControlLookup__)(struct VirtualMemory *, struct RS_RES_CONTROL_PARAMS_INTERNAL *, const struct NVOC_EXPORTED_METHOD_DEF **); + void (*__virtmemControlSerialization_Epilogue__)(struct VirtualMemory *, CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); NV_STATUS (*__virtmemMap__)(struct VirtualMemory *, CALL_CONTEXT *, struct RS_CPU_MAP_PARAMS *, RsCpuMapping *); NvBool (*__virtmemAccessCallback__)(struct VirtualMemory *, struct RsClient *, void *, RsAccessRight); NvHandle hVASpace; @@ -123,24 +125,26 @@ #define virtmemMapTo(pVirtualMemory, pParams) virtmemMapTo_DISPATCH(pVirtualMemory, pParams) #define virtmemUnmapFrom(pVirtualMemory, pParams) virtmemUnmapFrom_DISPATCH(pVirtualMemory, pParams) #define virtmemCheckMemInterUnmap(pMemory, bSubdeviceHandleProvided) virtmemCheckMemInterUnmap_DISPATCH(pMemory, bSubdeviceHandleProvided) +#define virtmemShareCallback(pResource, pInvokingClient, pParentRef, pSharePolicy) virtmemShareCallback_DISPATCH(pResource, pInvokingClient, pParentRef, pSharePolicy) +#define virtmemGetMapAddrSpace(pMemory, pCallContext, mapFlags, pAddrSpace) virtmemGetMapAddrSpace_DISPATCH(pMemory, pCallContext, mapFlags, pAddrSpace) +#define virtmemGetRefCount(pResource) virtmemGetRefCount_DISPATCH(pResource) +#define virtmemAddAdditionalDependants(pClient, pResource, pReference) virtmemAddAdditionalDependants_DISPATCH(pClient, pResource, pReference) +#define virtmemControl_Prologue(pResource, pCallContext, pParams) virtmemControl_Prologue_DISPATCH(pResource, pCallContext, pParams) +#define virtmemIsGpuMapAllowed(pMemory, pGpu) virtmemIsGpuMapAllowed_DISPATCH(pMemory, pGpu) +#define virtmemControl_Epilogue(pResource, pCallContext, pParams) virtmemControl_Epilogue_DISPATCH(pResource, pCallContext, pParams) +#define virtmemControlLookup(pResource, pParams, ppEntry) virtmemControlLookup_DISPATCH(pResource, pParams, ppEntry) #define virtmemControl(pMemory, pCallContext, pParams) virtmemControl_DISPATCH(pMemory, pCallContext, pParams) #define virtmemUnmap(pMemory, pCallContext, pCpuMapping) virtmemUnmap_DISPATCH(pMemory, pCallContext, pCpuMapping) #define virtmemGetMemInterMapParams(pMemory, pParams) virtmemGetMemInterMapParams_DISPATCH(pMemory, pParams) #define virtmemGetMemoryMappingDescriptor(pMemory, ppMemDesc) virtmemGetMemoryMappingDescriptor_DISPATCH(pMemory, ppMemDesc) -#define virtmemGetMapAddrSpace(pMemory, pCallContext, mapFlags, pAddrSpace) virtmemGetMapAddrSpace_DISPATCH(pMemory, pCallContext, mapFlags, pAddrSpace) -#define virtmemShareCallback(pResource, pInvokingClient, pParentRef, pSharePolicy) virtmemShareCallback_DISPATCH(pResource, pInvokingClient, pParentRef, pSharePolicy) #define virtmemControlFilter(pResource, pCallContext, pParams) virtmemControlFilter_DISPATCH(pResource, pCallContext, pParams) -#define virtmemAddAdditionalDependants(pClient, pResource, pReference) virtmemAddAdditionalDependants_DISPATCH(pClient, pResource, pReference) -#define virtmemGetRefCount(pResource) virtmemGetRefCount_DISPATCH(pResource) +#define virtmemControlSerialization_Prologue(pResource, pCallContext, pParams) virtmemControlSerialization_Prologue_DISPATCH(pResource, pCallContext, pParams) #define virtmemCanCopy(pStandardMemory) virtmemCanCopy_DISPATCH(pStandardMemory) -#define virtmemIsGpuMapAllowed(pMemory, pGpu) virtmemIsGpuMapAllowed_DISPATCH(pMemory, pGpu) -#define virtmemControl_Prologue(pResource, pCallContext, pParams) virtmemControl_Prologue_DISPATCH(pResource, pCallContext, pParams) #define virtmemIsReady(pMemory, bCopyConstructorContext) virtmemIsReady_DISPATCH(pMemory, bCopyConstructorContext) -#define virtmemCheckCopyPermissions(pMemory, pDstGpu, hDstClientNvBool) virtmemCheckCopyPermissions_DISPATCH(pMemory, pDstGpu, hDstClientNvBool) +#define virtmemCheckCopyPermissions(pMemory, pDstGpu, pDstDevice) virtmemCheckCopyPermissions_DISPATCH(pMemory, pDstGpu, pDstDevice) #define virtmemPreDestruct(pResource) virtmemPreDestruct_DISPATCH(pResource) #define virtmemIsDuplicate(pMemory, hMemory, pDuplicate) virtmemIsDuplicate_DISPATCH(pMemory, hMemory, pDuplicate) -#define virtmemControl_Epilogue(pResource, pCallContext, pParams) virtmemControl_Epilogue_DISPATCH(pResource, pCallContext, pParams) -#define virtmemControlLookup(pResource, pParams, ppEntry) virtmemControlLookup_DISPATCH(pResource, pParams, ppEntry) +#define virtmemControlSerialization_Epilogue(pResource, pCallContext, pParams) virtmemControlSerialization_Epilogue_DISPATCH(pResource, pCallContext, pParams) #define virtmemMap(pMemory, pCallContext, pParams, pCpuMapping) virtmemMap_DISPATCH(pMemory, pCallContext, pParams, pCpuMapping) #define virtmemAccessCallback(pResource, pInvokingClient, pAllocParams, accessRight) virtmemAccessCallback_DISPATCH(pResource, pInvokingClient, pAllocParams, accessRight) NV_STATUS virtmemMapTo_IMPL(struct VirtualMemory *pVirtualMemory, struct RS_RES_MAP_TO_PARAMS *pParams); @@ -159,6 +163,38 @@ return pMemory->__virtmemCheckMemInterUnmap__(pMemory, bSubdeviceHandleProvided); } +static inline NvBool virtmemShareCallback_DISPATCH(struct VirtualMemory *pResource, struct RsClient *pInvokingClient, struct RsResourceRef *pParentRef, RS_SHARE_POLICY *pSharePolicy) { + return pResource->__virtmemShareCallback__(pResource, pInvokingClient, pParentRef, pSharePolicy); +} + +static inline NV_STATUS virtmemGetMapAddrSpace_DISPATCH(struct VirtualMemory *pMemory, CALL_CONTEXT *pCallContext, NvU32 mapFlags, NV_ADDRESS_SPACE *pAddrSpace) { + return pMemory->__virtmemGetMapAddrSpace__(pMemory, pCallContext, mapFlags, pAddrSpace); +} + +static inline NvU32 virtmemGetRefCount_DISPATCH(struct VirtualMemory *pResource) { + return pResource->__virtmemGetRefCount__(pResource); +} + +static inline void virtmemAddAdditionalDependants_DISPATCH(struct RsClient *pClient, struct VirtualMemory *pResource, RsResourceRef *pReference) { + pResource->__virtmemAddAdditionalDependants__(pClient, pResource, pReference); +} + +static inline NV_STATUS virtmemControl_Prologue_DISPATCH(struct VirtualMemory *pResource, CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return pResource->__virtmemControl_Prologue__(pResource, pCallContext, pParams); +} + +static inline NvBool virtmemIsGpuMapAllowed_DISPATCH(struct VirtualMemory *pMemory, struct OBJGPU *pGpu) { + return pMemory->__virtmemIsGpuMapAllowed__(pMemory, pGpu); +} + +static inline void virtmemControl_Epilogue_DISPATCH(struct VirtualMemory *pResource, CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + pResource->__virtmemControl_Epilogue__(pResource, pCallContext, pParams); +} + +static inline NV_STATUS virtmemControlLookup_DISPATCH(struct VirtualMemory *pResource, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams, const struct NVOC_EXPORTED_METHOD_DEF **ppEntry) { + return pResource->__virtmemControlLookup__(pResource, pParams, ppEntry); +} + static inline NV_STATUS virtmemControl_DISPATCH(struct VirtualMemory *pMemory, CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { return pMemory->__virtmemControl__(pMemory, pCallContext, pParams); } @@ -175,44 +211,24 @@ return pMemory->__virtmemGetMemoryMappingDescriptor__(pMemory, ppMemDesc); } -static inline NV_STATUS virtmemGetMapAddrSpace_DISPATCH(struct VirtualMemory *pMemory, CALL_CONTEXT *pCallContext, NvU32 mapFlags, NV_ADDRESS_SPACE *pAddrSpace) { - return pMemory->__virtmemGetMapAddrSpace__(pMemory, pCallContext, mapFlags, pAddrSpace); -} - -static inline NvBool virtmemShareCallback_DISPATCH(struct VirtualMemory *pResource, struct RsClient *pInvokingClient, struct RsResourceRef *pParentRef, RS_SHARE_POLICY *pSharePolicy) { - return pResource->__virtmemShareCallback__(pResource, pInvokingClient, pParentRef, pSharePolicy); -} - static inline NV_STATUS virtmemControlFilter_DISPATCH(struct VirtualMemory *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { return pResource->__virtmemControlFilter__(pResource, pCallContext, pParams); } -static inline void virtmemAddAdditionalDependants_DISPATCH(struct RsClient *pClient, struct VirtualMemory *pResource, RsResourceRef *pReference) { - pResource->__virtmemAddAdditionalDependants__(pClient, pResource, pReference); -} - -static inline NvU32 virtmemGetRefCount_DISPATCH(struct VirtualMemory *pResource) { - return pResource->__virtmemGetRefCount__(pResource); +static inline NV_STATUS virtmemControlSerialization_Prologue_DISPATCH(struct VirtualMemory *pResource, CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return pResource->__virtmemControlSerialization_Prologue__(pResource, pCallContext, pParams); } static inline NvBool virtmemCanCopy_DISPATCH(struct VirtualMemory *pStandardMemory) { return pStandardMemory->__virtmemCanCopy__(pStandardMemory); } -static inline NvBool virtmemIsGpuMapAllowed_DISPATCH(struct VirtualMemory *pMemory, struct OBJGPU *pGpu) { - return pMemory->__virtmemIsGpuMapAllowed__(pMemory, pGpu); -} - -static inline NV_STATUS virtmemControl_Prologue_DISPATCH(struct VirtualMemory *pResource, CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { - return pResource->__virtmemControl_Prologue__(pResource, pCallContext, pParams); -} - static inline NV_STATUS virtmemIsReady_DISPATCH(struct VirtualMemory *pMemory, NvBool bCopyConstructorContext) { return pMemory->__virtmemIsReady__(pMemory, bCopyConstructorContext); } -static inline NV_STATUS virtmemCheckCopyPermissions_DISPATCH(struct VirtualMemory *pMemory, struct OBJGPU *pDstGpu, NvHandle hDstClientNvBool) { - return pMemory->__virtmemCheckCopyPermissions__(pMemory, pDstGpu, hDstClientNvBool); +static inline NV_STATUS virtmemCheckCopyPermissions_DISPATCH(struct VirtualMemory *pMemory, struct OBJGPU *pDstGpu, struct Device *pDstDevice) { + return pMemory->__virtmemCheckCopyPermissions__(pMemory, pDstGpu, pDstDevice); } static inline void virtmemPreDestruct_DISPATCH(struct VirtualMemory *pResource) { @@ -223,12 +239,8 @@ return pMemory->__virtmemIsDuplicate__(pMemory, hMemory, pDuplicate); } -static inline void virtmemControl_Epilogue_DISPATCH(struct VirtualMemory *pResource, CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { - pResource->__virtmemControl_Epilogue__(pResource, pCallContext, pParams); -} - -static inline NV_STATUS virtmemControlLookup_DISPATCH(struct VirtualMemory *pResource, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams, const struct NVOC_EXPORTED_METHOD_DEF **ppEntry) { - return pResource->__virtmemControlLookup__(pResource, pParams, ppEntry); +static inline void virtmemControlSerialization_Epilogue_DISPATCH(struct VirtualMemory *pResource, CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + pResource->__virtmemControlSerialization_Epilogue__(pResource, pCallContext, pParams); } static inline NV_STATUS virtmemMap_DISPATCH(struct VirtualMemory *pMemory, CALL_CONTEXT *pCallContext, struct RS_CPU_MAP_PARAMS *pParams, RsCpuMapping *pCpuMapping) { @@ -245,10 +257,10 @@ void virtmemDestruct_IMPL(struct VirtualMemory *pVirtualMemory); #define __nvoc_virtmemDestruct(pVirtualMemory) virtmemDestruct_IMPL(pVirtualMemory) -NV_STATUS virtmemReserveMempool_IMPL(struct VirtualMemory *pVirtualMemory, struct OBJGPU *arg0, NvHandle hDevice, NvU64 size, NvU32 pageSizeMask); +NV_STATUS virtmemReserveMempool_IMPL(struct VirtualMemory *pVirtualMemory, struct OBJGPU *arg0, NvHandle hDevice, NvU64 size, NvU64 pageSizeMask); #ifdef __nvoc_virtual_mem_h_disabled -static inline NV_STATUS virtmemReserveMempool(struct VirtualMemory *pVirtualMemory, struct OBJGPU *arg0, NvHandle hDevice, NvU64 size, NvU32 pageSizeMask) { +static inline NV_STATUS virtmemReserveMempool(struct VirtualMemory *pVirtualMemory, struct OBJGPU *arg0, NvHandle hDevice, NvU64 size, NvU64 pageSizeMask) { NV_ASSERT_FAILED_PRECOMP("VirtualMemory was disabled!"); return NV_ERR_NOT_SUPPORTED; } diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/generated/g_zbc_api_nvoc.c nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_zbc_api_nvoc.c --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/generated/g_zbc_api_nvoc.c 2023-10-25 20:27:24.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_zbc_api_nvoc.c 2024-03-05 22:18:53.000000000 +0000 @@ -97,84 +97,92 @@ return gpuresShareCallback((struct GpuResource *)(((unsigned char *)pGpuResource) + __nvoc_rtti_ZbcApi_GpuResource.offset), pInvokingClient, pParentRef, pSharePolicy); } -static NV_STATUS __nvoc_thunk_GpuResource_zbcapiControl(struct ZbcApi *pGpuResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { - return gpuresControl((struct GpuResource *)(((unsigned char *)pGpuResource) + __nvoc_rtti_ZbcApi_GpuResource.offset), pCallContext, pParams); +static NV_STATUS __nvoc_thunk_RmResource_zbcapiCheckMemInterUnmap(struct ZbcApi *pRmResource, NvBool bSubdeviceHandleProvided) { + return rmresCheckMemInterUnmap((struct RmResource *)(((unsigned char *)pRmResource) + __nvoc_rtti_ZbcApi_RmResource.offset), bSubdeviceHandleProvided); } -static NV_STATUS __nvoc_thunk_GpuResource_zbcapiUnmap(struct ZbcApi *pGpuResource, struct CALL_CONTEXT *pCallContext, struct RsCpuMapping *pCpuMapping) { - return gpuresUnmap((struct GpuResource *)(((unsigned char *)pGpuResource) + __nvoc_rtti_ZbcApi_GpuResource.offset), pCallContext, pCpuMapping); +static NV_STATUS __nvoc_thunk_RsResource_zbcapiMapTo(struct ZbcApi *pResource, RS_RES_MAP_TO_PARAMS *pParams) { + return resMapTo((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_ZbcApi_RsResource.offset), pParams); } -static NV_STATUS __nvoc_thunk_RmResource_zbcapiGetMemInterMapParams(struct ZbcApi *pRmResource, RMRES_MEM_INTER_MAP_PARAMS *pParams) { - return rmresGetMemInterMapParams((struct RmResource *)(((unsigned char *)pRmResource) + __nvoc_rtti_ZbcApi_RmResource.offset), pParams); +static NV_STATUS __nvoc_thunk_GpuResource_zbcapiGetMapAddrSpace(struct ZbcApi *pGpuResource, struct CALL_CONTEXT *pCallContext, NvU32 mapFlags, NV_ADDRESS_SPACE *pAddrSpace) { + return gpuresGetMapAddrSpace((struct GpuResource *)(((unsigned char *)pGpuResource) + __nvoc_rtti_ZbcApi_GpuResource.offset), pCallContext, mapFlags, pAddrSpace); } -static NV_STATUS __nvoc_thunk_RmResource_zbcapiGetMemoryMappingDescriptor(struct ZbcApi *pRmResource, struct MEMORY_DESCRIPTOR **ppMemDesc) { - return rmresGetMemoryMappingDescriptor((struct RmResource *)(((unsigned char *)pRmResource) + __nvoc_rtti_ZbcApi_RmResource.offset), ppMemDesc); +static NvU32 __nvoc_thunk_RsResource_zbcapiGetRefCount(struct ZbcApi *pResource) { + return resGetRefCount((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_ZbcApi_RsResource.offset)); } -static NV_STATUS __nvoc_thunk_GpuResource_zbcapiGetMapAddrSpace(struct ZbcApi *pGpuResource, struct CALL_CONTEXT *pCallContext, NvU32 mapFlags, NV_ADDRESS_SPACE *pAddrSpace) { - return gpuresGetMapAddrSpace((struct GpuResource *)(((unsigned char *)pGpuResource) + __nvoc_rtti_ZbcApi_GpuResource.offset), pCallContext, mapFlags, pAddrSpace); +static void __nvoc_thunk_RsResource_zbcapiAddAdditionalDependants(struct RsClient *pClient, struct ZbcApi *pResource, RsResourceRef *pReference) { + resAddAdditionalDependants(pClient, (struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_ZbcApi_RsResource.offset), pReference); } -static NvHandle __nvoc_thunk_GpuResource_zbcapiGetInternalObjectHandle(struct ZbcApi *pGpuResource) { - return gpuresGetInternalObjectHandle((struct GpuResource *)(((unsigned char *)pGpuResource) + __nvoc_rtti_ZbcApi_GpuResource.offset)); +static NV_STATUS __nvoc_thunk_RmResource_zbcapiControl_Prologue(struct ZbcApi *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return rmresControl_Prologue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_ZbcApi_RmResource.offset), pCallContext, pParams); } -static NV_STATUS __nvoc_thunk_RsResource_zbcapiControlFilter(struct ZbcApi *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { - return resControlFilter((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_ZbcApi_RsResource.offset), pCallContext, pParams); +static NV_STATUS __nvoc_thunk_GpuResource_zbcapiGetRegBaseOffsetAndSize(struct ZbcApi *pGpuResource, struct OBJGPU *pGpu, NvU32 *pOffset, NvU32 *pSize) { + return gpuresGetRegBaseOffsetAndSize((struct GpuResource *)(((unsigned char *)pGpuResource) + __nvoc_rtti_ZbcApi_GpuResource.offset), pGpu, pOffset, pSize); } -static void __nvoc_thunk_RsResource_zbcapiAddAdditionalDependants(struct RsClient *pClient, struct ZbcApi *pResource, RsResourceRef *pReference) { - resAddAdditionalDependants(pClient, (struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_ZbcApi_RsResource.offset), pReference); +static NV_STATUS __nvoc_thunk_GpuResource_zbcapiInternalControlForward(struct ZbcApi *pGpuResource, NvU32 command, void *pParams, NvU32 size) { + return gpuresInternalControlForward((struct GpuResource *)(((unsigned char *)pGpuResource) + __nvoc_rtti_ZbcApi_GpuResource.offset), command, pParams, size); } -static NvU32 __nvoc_thunk_RsResource_zbcapiGetRefCount(struct ZbcApi *pResource) { - return resGetRefCount((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_ZbcApi_RsResource.offset)); +static NV_STATUS __nvoc_thunk_RsResource_zbcapiUnmapFrom(struct ZbcApi *pResource, RS_RES_UNMAP_FROM_PARAMS *pParams) { + return resUnmapFrom((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_ZbcApi_RsResource.offset), pParams); } -static NV_STATUS __nvoc_thunk_RmResource_zbcapiCheckMemInterUnmap(struct ZbcApi *pRmResource, NvBool bSubdeviceHandleProvided) { - return rmresCheckMemInterUnmap((struct RmResource *)(((unsigned char *)pRmResource) + __nvoc_rtti_ZbcApi_RmResource.offset), bSubdeviceHandleProvided); +static void __nvoc_thunk_RmResource_zbcapiControl_Epilogue(struct ZbcApi *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + rmresControl_Epilogue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_ZbcApi_RmResource.offset), pCallContext, pParams); } -static NV_STATUS __nvoc_thunk_RsResource_zbcapiMapTo(struct ZbcApi *pResource, RS_RES_MAP_TO_PARAMS *pParams) { - return resMapTo((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_ZbcApi_RsResource.offset), pParams); +static NV_STATUS __nvoc_thunk_RsResource_zbcapiControlLookup(struct ZbcApi *pResource, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams, const struct NVOC_EXPORTED_METHOD_DEF **ppEntry) { + return resControlLookup((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_ZbcApi_RsResource.offset), pParams, ppEntry); } -static NV_STATUS __nvoc_thunk_RmResource_zbcapiControl_Prologue(struct ZbcApi *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { - return rmresControl_Prologue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_ZbcApi_RmResource.offset), pCallContext, pParams); +static NvHandle __nvoc_thunk_GpuResource_zbcapiGetInternalObjectHandle(struct ZbcApi *pGpuResource) { + return gpuresGetInternalObjectHandle((struct GpuResource *)(((unsigned char *)pGpuResource) + __nvoc_rtti_ZbcApi_GpuResource.offset)); } -static NV_STATUS __nvoc_thunk_GpuResource_zbcapiGetRegBaseOffsetAndSize(struct ZbcApi *pGpuResource, struct OBJGPU *pGpu, NvU32 *pOffset, NvU32 *pSize) { - return gpuresGetRegBaseOffsetAndSize((struct GpuResource *)(((unsigned char *)pGpuResource) + __nvoc_rtti_ZbcApi_GpuResource.offset), pGpu, pOffset, pSize); +static NV_STATUS __nvoc_thunk_GpuResource_zbcapiControl(struct ZbcApi *pGpuResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return gpuresControl((struct GpuResource *)(((unsigned char *)pGpuResource) + __nvoc_rtti_ZbcApi_GpuResource.offset), pCallContext, pParams); } -static NvBool __nvoc_thunk_RsResource_zbcapiCanCopy(struct ZbcApi *pResource) { - return resCanCopy((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_ZbcApi_RsResource.offset)); +static NV_STATUS __nvoc_thunk_GpuResource_zbcapiUnmap(struct ZbcApi *pGpuResource, struct CALL_CONTEXT *pCallContext, struct RsCpuMapping *pCpuMapping) { + return gpuresUnmap((struct GpuResource *)(((unsigned char *)pGpuResource) + __nvoc_rtti_ZbcApi_GpuResource.offset), pCallContext, pCpuMapping); } -static NV_STATUS __nvoc_thunk_GpuResource_zbcapiInternalControlForward(struct ZbcApi *pGpuResource, NvU32 command, void *pParams, NvU32 size) { - return gpuresInternalControlForward((struct GpuResource *)(((unsigned char *)pGpuResource) + __nvoc_rtti_ZbcApi_GpuResource.offset), command, pParams, size); +static NV_STATUS __nvoc_thunk_RmResource_zbcapiGetMemInterMapParams(struct ZbcApi *pRmResource, RMRES_MEM_INTER_MAP_PARAMS *pParams) { + return rmresGetMemInterMapParams((struct RmResource *)(((unsigned char *)pRmResource) + __nvoc_rtti_ZbcApi_RmResource.offset), pParams); } -static void __nvoc_thunk_RsResource_zbcapiPreDestruct(struct ZbcApi *pResource) { - resPreDestruct((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_ZbcApi_RsResource.offset)); +static NV_STATUS __nvoc_thunk_RmResource_zbcapiGetMemoryMappingDescriptor(struct ZbcApi *pRmResource, struct MEMORY_DESCRIPTOR **ppMemDesc) { + return rmresGetMemoryMappingDescriptor((struct RmResource *)(((unsigned char *)pRmResource) + __nvoc_rtti_ZbcApi_RmResource.offset), ppMemDesc); } -static NV_STATUS __nvoc_thunk_RsResource_zbcapiUnmapFrom(struct ZbcApi *pResource, RS_RES_UNMAP_FROM_PARAMS *pParams) { - return resUnmapFrom((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_ZbcApi_RsResource.offset), pParams); +static NV_STATUS __nvoc_thunk_RsResource_zbcapiControlFilter(struct ZbcApi *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return resControlFilter((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_ZbcApi_RsResource.offset), pCallContext, pParams); } -static NV_STATUS __nvoc_thunk_RsResource_zbcapiIsDuplicate(struct ZbcApi *pResource, NvHandle hMemory, NvBool *pDuplicate) { - return resIsDuplicate((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_ZbcApi_RsResource.offset), hMemory, pDuplicate); +static NV_STATUS __nvoc_thunk_RmResource_zbcapiControlSerialization_Prologue(struct ZbcApi *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return rmresControlSerialization_Prologue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_ZbcApi_RmResource.offset), pCallContext, pParams); } -static void __nvoc_thunk_RmResource_zbcapiControl_Epilogue(struct ZbcApi *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { - rmresControl_Epilogue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_ZbcApi_RmResource.offset), pCallContext, pParams); +static NvBool __nvoc_thunk_RsResource_zbcapiCanCopy(struct ZbcApi *pResource) { + return resCanCopy((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_ZbcApi_RsResource.offset)); } -static NV_STATUS __nvoc_thunk_RsResource_zbcapiControlLookup(struct ZbcApi *pResource, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams, const struct NVOC_EXPORTED_METHOD_DEF **ppEntry) { - return resControlLookup((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_ZbcApi_RsResource.offset), pParams, ppEntry); +static void __nvoc_thunk_RsResource_zbcapiPreDestruct(struct ZbcApi *pResource) { + resPreDestruct((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_ZbcApi_RsResource.offset)); +} + +static NV_STATUS __nvoc_thunk_RsResource_zbcapiIsDuplicate(struct ZbcApi *pResource, NvHandle hMemory, NvBool *pDuplicate) { + return resIsDuplicate((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_ZbcApi_RsResource.offset), hMemory, pDuplicate); +} + +static void __nvoc_thunk_RmResource_zbcapiControlSerialization_Epilogue(struct ZbcApi *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + rmresControlSerialization_Epilogue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_ZbcApi_RmResource.offset), pCallContext, pParams); } static NV_STATUS __nvoc_thunk_GpuResource_zbcapiMap(struct ZbcApi *pGpuResource, struct CALL_CONTEXT *pCallContext, struct RS_CPU_MAP_PARAMS *pParams, struct RsCpuMapping *pCpuMapping) { @@ -378,45 +386,49 @@ pThis->__zbcapiShareCallback__ = &__nvoc_thunk_GpuResource_zbcapiShareCallback; - pThis->__zbcapiControl__ = &__nvoc_thunk_GpuResource_zbcapiControl; + pThis->__zbcapiCheckMemInterUnmap__ = &__nvoc_thunk_RmResource_zbcapiCheckMemInterUnmap; - pThis->__zbcapiUnmap__ = &__nvoc_thunk_GpuResource_zbcapiUnmap; + pThis->__zbcapiMapTo__ = &__nvoc_thunk_RsResource_zbcapiMapTo; - pThis->__zbcapiGetMemInterMapParams__ = &__nvoc_thunk_RmResource_zbcapiGetMemInterMapParams; + pThis->__zbcapiGetMapAddrSpace__ = &__nvoc_thunk_GpuResource_zbcapiGetMapAddrSpace; - pThis->__zbcapiGetMemoryMappingDescriptor__ = &__nvoc_thunk_RmResource_zbcapiGetMemoryMappingDescriptor; + pThis->__zbcapiGetRefCount__ = &__nvoc_thunk_RsResource_zbcapiGetRefCount; - pThis->__zbcapiGetMapAddrSpace__ = &__nvoc_thunk_GpuResource_zbcapiGetMapAddrSpace; + pThis->__zbcapiAddAdditionalDependants__ = &__nvoc_thunk_RsResource_zbcapiAddAdditionalDependants; - pThis->__zbcapiGetInternalObjectHandle__ = &__nvoc_thunk_GpuResource_zbcapiGetInternalObjectHandle; + pThis->__zbcapiControl_Prologue__ = &__nvoc_thunk_RmResource_zbcapiControl_Prologue; - pThis->__zbcapiControlFilter__ = &__nvoc_thunk_RsResource_zbcapiControlFilter; + pThis->__zbcapiGetRegBaseOffsetAndSize__ = &__nvoc_thunk_GpuResource_zbcapiGetRegBaseOffsetAndSize; - pThis->__zbcapiAddAdditionalDependants__ = &__nvoc_thunk_RsResource_zbcapiAddAdditionalDependants; + pThis->__zbcapiInternalControlForward__ = &__nvoc_thunk_GpuResource_zbcapiInternalControlForward; - pThis->__zbcapiGetRefCount__ = &__nvoc_thunk_RsResource_zbcapiGetRefCount; + pThis->__zbcapiUnmapFrom__ = &__nvoc_thunk_RsResource_zbcapiUnmapFrom; - pThis->__zbcapiCheckMemInterUnmap__ = &__nvoc_thunk_RmResource_zbcapiCheckMemInterUnmap; + pThis->__zbcapiControl_Epilogue__ = &__nvoc_thunk_RmResource_zbcapiControl_Epilogue; - pThis->__zbcapiMapTo__ = &__nvoc_thunk_RsResource_zbcapiMapTo; + pThis->__zbcapiControlLookup__ = &__nvoc_thunk_RsResource_zbcapiControlLookup; - pThis->__zbcapiControl_Prologue__ = &__nvoc_thunk_RmResource_zbcapiControl_Prologue; + pThis->__zbcapiGetInternalObjectHandle__ = &__nvoc_thunk_GpuResource_zbcapiGetInternalObjectHandle; - pThis->__zbcapiGetRegBaseOffsetAndSize__ = &__nvoc_thunk_GpuResource_zbcapiGetRegBaseOffsetAndSize; + pThis->__zbcapiControl__ = &__nvoc_thunk_GpuResource_zbcapiControl; - pThis->__zbcapiCanCopy__ = &__nvoc_thunk_RsResource_zbcapiCanCopy; + pThis->__zbcapiUnmap__ = &__nvoc_thunk_GpuResource_zbcapiUnmap; - pThis->__zbcapiInternalControlForward__ = &__nvoc_thunk_GpuResource_zbcapiInternalControlForward; + pThis->__zbcapiGetMemInterMapParams__ = &__nvoc_thunk_RmResource_zbcapiGetMemInterMapParams; - pThis->__zbcapiPreDestruct__ = &__nvoc_thunk_RsResource_zbcapiPreDestruct; + pThis->__zbcapiGetMemoryMappingDescriptor__ = &__nvoc_thunk_RmResource_zbcapiGetMemoryMappingDescriptor; - pThis->__zbcapiUnmapFrom__ = &__nvoc_thunk_RsResource_zbcapiUnmapFrom; + pThis->__zbcapiControlFilter__ = &__nvoc_thunk_RsResource_zbcapiControlFilter; - pThis->__zbcapiIsDuplicate__ = &__nvoc_thunk_RsResource_zbcapiIsDuplicate; + pThis->__zbcapiControlSerialization_Prologue__ = &__nvoc_thunk_RmResource_zbcapiControlSerialization_Prologue; - pThis->__zbcapiControl_Epilogue__ = &__nvoc_thunk_RmResource_zbcapiControl_Epilogue; + pThis->__zbcapiCanCopy__ = &__nvoc_thunk_RsResource_zbcapiCanCopy; - pThis->__zbcapiControlLookup__ = &__nvoc_thunk_RsResource_zbcapiControlLookup; + pThis->__zbcapiPreDestruct__ = &__nvoc_thunk_RsResource_zbcapiPreDestruct; + + pThis->__zbcapiIsDuplicate__ = &__nvoc_thunk_RsResource_zbcapiIsDuplicate; + + pThis->__zbcapiControlSerialization_Epilogue__ = &__nvoc_thunk_RmResource_zbcapiControlSerialization_Epilogue; pThis->__zbcapiMap__ = &__nvoc_thunk_GpuResource_zbcapiMap; @@ -445,13 +457,16 @@ ZbcApi *pThis; RmHalspecOwner *pRmhalspecowner; - pThis = portMemAllocNonPaged(sizeof(ZbcApi)); - if (pThis == NULL) return NV_ERR_NO_MEMORY; + status = __nvoc_handleObjCreateMemAlloc(createFlags, sizeof(ZbcApi), (void**)&pThis, (void**)ppThis); + if (status != NV_OK) + return status; portMemSet(pThis, 0, sizeof(ZbcApi)); __nvoc_initRtti(staticCast(pThis, Dynamic), &__nvoc_class_def_ZbcApi); + pThis->__nvoc_base_GpuResource.__nvoc_base_RmResource.__nvoc_base_RsResource.__nvoc_base_Object.createFlags = createFlags; + if (pParent != NULL && !(createFlags & NVOC_OBJ_CREATE_FLAGS_PARENT_HALSPEC_ONLY)) { pParentObj = dynamicCast(pParent, Object); @@ -471,11 +486,17 @@ if (status != NV_OK) goto __nvoc_objCreate_ZbcApi_cleanup; *ppThis = pThis; + return NV_OK; __nvoc_objCreate_ZbcApi_cleanup: // do not call destructors here since the constructor already called them - portMemFree(pThis); + if (createFlags & NVOC_OBJ_CREATE_FLAGS_IN_PLACE_CONSTRUCT) + portMemSet(pThis, 0, sizeof(ZbcApi)); + else + portMemFree(pThis); + + // coverity[leaked_storage:FALSE] return status; } diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/generated/g_zbc_api_nvoc.h nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_zbc_api_nvoc.h --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/generated/g_zbc_api_nvoc.h 2023-10-25 20:27:24.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/g_zbc_api_nvoc.h 2024-03-05 22:18:53.000000000 +0000 @@ -64,26 +64,28 @@ NV_STATUS (*__zbcapiCtrlCmdGetZbcClearTableSize__)(struct ZbcApi *, NV9096_CTRL_GET_ZBC_CLEAR_TABLE_SIZE_PARAMS *); NV_STATUS (*__zbcapiCtrlCmdGetZbcClearTableEntry__)(struct ZbcApi *, NV9096_CTRL_GET_ZBC_CLEAR_TABLE_ENTRY_PARAMS *); NvBool (*__zbcapiShareCallback__)(struct ZbcApi *, struct RsClient *, struct RsResourceRef *, RS_SHARE_POLICY *); - NV_STATUS (*__zbcapiControl__)(struct ZbcApi *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); - NV_STATUS (*__zbcapiUnmap__)(struct ZbcApi *, struct CALL_CONTEXT *, struct RsCpuMapping *); - NV_STATUS (*__zbcapiGetMemInterMapParams__)(struct ZbcApi *, RMRES_MEM_INTER_MAP_PARAMS *); - NV_STATUS (*__zbcapiGetMemoryMappingDescriptor__)(struct ZbcApi *, struct MEMORY_DESCRIPTOR **); - NV_STATUS (*__zbcapiGetMapAddrSpace__)(struct ZbcApi *, struct CALL_CONTEXT *, NvU32, NV_ADDRESS_SPACE *); - NvHandle (*__zbcapiGetInternalObjectHandle__)(struct ZbcApi *); - NV_STATUS (*__zbcapiControlFilter__)(struct ZbcApi *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); - void (*__zbcapiAddAdditionalDependants__)(struct RsClient *, struct ZbcApi *, RsResourceRef *); - NvU32 (*__zbcapiGetRefCount__)(struct ZbcApi *); NV_STATUS (*__zbcapiCheckMemInterUnmap__)(struct ZbcApi *, NvBool); NV_STATUS (*__zbcapiMapTo__)(struct ZbcApi *, RS_RES_MAP_TO_PARAMS *); + NV_STATUS (*__zbcapiGetMapAddrSpace__)(struct ZbcApi *, struct CALL_CONTEXT *, NvU32, NV_ADDRESS_SPACE *); + NvU32 (*__zbcapiGetRefCount__)(struct ZbcApi *); + void (*__zbcapiAddAdditionalDependants__)(struct RsClient *, struct ZbcApi *, RsResourceRef *); NV_STATUS (*__zbcapiControl_Prologue__)(struct ZbcApi *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); NV_STATUS (*__zbcapiGetRegBaseOffsetAndSize__)(struct ZbcApi *, struct OBJGPU *, NvU32 *, NvU32 *); - NvBool (*__zbcapiCanCopy__)(struct ZbcApi *); NV_STATUS (*__zbcapiInternalControlForward__)(struct ZbcApi *, NvU32, void *, NvU32); - void (*__zbcapiPreDestruct__)(struct ZbcApi *); NV_STATUS (*__zbcapiUnmapFrom__)(struct ZbcApi *, RS_RES_UNMAP_FROM_PARAMS *); - NV_STATUS (*__zbcapiIsDuplicate__)(struct ZbcApi *, NvHandle, NvBool *); void (*__zbcapiControl_Epilogue__)(struct ZbcApi *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); NV_STATUS (*__zbcapiControlLookup__)(struct ZbcApi *, struct RS_RES_CONTROL_PARAMS_INTERNAL *, const struct NVOC_EXPORTED_METHOD_DEF **); + NvHandle (*__zbcapiGetInternalObjectHandle__)(struct ZbcApi *); + NV_STATUS (*__zbcapiControl__)(struct ZbcApi *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); + NV_STATUS (*__zbcapiUnmap__)(struct ZbcApi *, struct CALL_CONTEXT *, struct RsCpuMapping *); + NV_STATUS (*__zbcapiGetMemInterMapParams__)(struct ZbcApi *, RMRES_MEM_INTER_MAP_PARAMS *); + NV_STATUS (*__zbcapiGetMemoryMappingDescriptor__)(struct ZbcApi *, struct MEMORY_DESCRIPTOR **); + NV_STATUS (*__zbcapiControlFilter__)(struct ZbcApi *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); + NV_STATUS (*__zbcapiControlSerialization_Prologue__)(struct ZbcApi *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); + NvBool (*__zbcapiCanCopy__)(struct ZbcApi *); + void (*__zbcapiPreDestruct__)(struct ZbcApi *); + NV_STATUS (*__zbcapiIsDuplicate__)(struct ZbcApi *, NvHandle, NvBool *); + void (*__zbcapiControlSerialization_Epilogue__)(struct ZbcApi *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); NV_STATUS (*__zbcapiMap__)(struct ZbcApi *, struct CALL_CONTEXT *, struct RS_CPU_MAP_PARAMS *, struct RsCpuMapping *); NvBool (*__zbcapiAccessCallback__)(struct ZbcApi *, struct RsClient *, void *, RsAccessRight); NvBool bZbcUsed; @@ -125,26 +127,28 @@ #define zbcapiCtrlCmdGetZbcClearTableSize(pZbcApi, pGetZBCClearTableSizeParams) zbcapiCtrlCmdGetZbcClearTableSize_DISPATCH(pZbcApi, pGetZBCClearTableSizeParams) #define zbcapiCtrlCmdGetZbcClearTableEntry(pZbcApi, pGetZBCClearTableEntryParams) zbcapiCtrlCmdGetZbcClearTableEntry_DISPATCH(pZbcApi, pGetZBCClearTableEntryParams) #define zbcapiShareCallback(pGpuResource, pInvokingClient, pParentRef, pSharePolicy) zbcapiShareCallback_DISPATCH(pGpuResource, pInvokingClient, pParentRef, pSharePolicy) -#define zbcapiControl(pGpuResource, pCallContext, pParams) zbcapiControl_DISPATCH(pGpuResource, pCallContext, pParams) -#define zbcapiUnmap(pGpuResource, pCallContext, pCpuMapping) zbcapiUnmap_DISPATCH(pGpuResource, pCallContext, pCpuMapping) -#define zbcapiGetMemInterMapParams(pRmResource, pParams) zbcapiGetMemInterMapParams_DISPATCH(pRmResource, pParams) -#define zbcapiGetMemoryMappingDescriptor(pRmResource, ppMemDesc) zbcapiGetMemoryMappingDescriptor_DISPATCH(pRmResource, ppMemDesc) -#define zbcapiGetMapAddrSpace(pGpuResource, pCallContext, mapFlags, pAddrSpace) zbcapiGetMapAddrSpace_DISPATCH(pGpuResource, pCallContext, mapFlags, pAddrSpace) -#define zbcapiGetInternalObjectHandle(pGpuResource) zbcapiGetInternalObjectHandle_DISPATCH(pGpuResource) -#define zbcapiControlFilter(pResource, pCallContext, pParams) zbcapiControlFilter_DISPATCH(pResource, pCallContext, pParams) -#define zbcapiAddAdditionalDependants(pClient, pResource, pReference) zbcapiAddAdditionalDependants_DISPATCH(pClient, pResource, pReference) -#define zbcapiGetRefCount(pResource) zbcapiGetRefCount_DISPATCH(pResource) #define zbcapiCheckMemInterUnmap(pRmResource, bSubdeviceHandleProvided) zbcapiCheckMemInterUnmap_DISPATCH(pRmResource, bSubdeviceHandleProvided) #define zbcapiMapTo(pResource, pParams) zbcapiMapTo_DISPATCH(pResource, pParams) +#define zbcapiGetMapAddrSpace(pGpuResource, pCallContext, mapFlags, pAddrSpace) zbcapiGetMapAddrSpace_DISPATCH(pGpuResource, pCallContext, mapFlags, pAddrSpace) +#define zbcapiGetRefCount(pResource) zbcapiGetRefCount_DISPATCH(pResource) +#define zbcapiAddAdditionalDependants(pClient, pResource, pReference) zbcapiAddAdditionalDependants_DISPATCH(pClient, pResource, pReference) #define zbcapiControl_Prologue(pResource, pCallContext, pParams) zbcapiControl_Prologue_DISPATCH(pResource, pCallContext, pParams) #define zbcapiGetRegBaseOffsetAndSize(pGpuResource, pGpu, pOffset, pSize) zbcapiGetRegBaseOffsetAndSize_DISPATCH(pGpuResource, pGpu, pOffset, pSize) -#define zbcapiCanCopy(pResource) zbcapiCanCopy_DISPATCH(pResource) #define zbcapiInternalControlForward(pGpuResource, command, pParams, size) zbcapiInternalControlForward_DISPATCH(pGpuResource, command, pParams, size) -#define zbcapiPreDestruct(pResource) zbcapiPreDestruct_DISPATCH(pResource) #define zbcapiUnmapFrom(pResource, pParams) zbcapiUnmapFrom_DISPATCH(pResource, pParams) -#define zbcapiIsDuplicate(pResource, hMemory, pDuplicate) zbcapiIsDuplicate_DISPATCH(pResource, hMemory, pDuplicate) #define zbcapiControl_Epilogue(pResource, pCallContext, pParams) zbcapiControl_Epilogue_DISPATCH(pResource, pCallContext, pParams) #define zbcapiControlLookup(pResource, pParams, ppEntry) zbcapiControlLookup_DISPATCH(pResource, pParams, ppEntry) +#define zbcapiGetInternalObjectHandle(pGpuResource) zbcapiGetInternalObjectHandle_DISPATCH(pGpuResource) +#define zbcapiControl(pGpuResource, pCallContext, pParams) zbcapiControl_DISPATCH(pGpuResource, pCallContext, pParams) +#define zbcapiUnmap(pGpuResource, pCallContext, pCpuMapping) zbcapiUnmap_DISPATCH(pGpuResource, pCallContext, pCpuMapping) +#define zbcapiGetMemInterMapParams(pRmResource, pParams) zbcapiGetMemInterMapParams_DISPATCH(pRmResource, pParams) +#define zbcapiGetMemoryMappingDescriptor(pRmResource, ppMemDesc) zbcapiGetMemoryMappingDescriptor_DISPATCH(pRmResource, ppMemDesc) +#define zbcapiControlFilter(pResource, pCallContext, pParams) zbcapiControlFilter_DISPATCH(pResource, pCallContext, pParams) +#define zbcapiControlSerialization_Prologue(pResource, pCallContext, pParams) zbcapiControlSerialization_Prologue_DISPATCH(pResource, pCallContext, pParams) +#define zbcapiCanCopy(pResource) zbcapiCanCopy_DISPATCH(pResource) +#define zbcapiPreDestruct(pResource) zbcapiPreDestruct_DISPATCH(pResource) +#define zbcapiIsDuplicate(pResource, hMemory, pDuplicate) zbcapiIsDuplicate_DISPATCH(pResource, hMemory, pDuplicate) +#define zbcapiControlSerialization_Epilogue(pResource, pCallContext, pParams) zbcapiControlSerialization_Epilogue_DISPATCH(pResource, pCallContext, pParams) #define zbcapiMap(pGpuResource, pCallContext, pParams, pCpuMapping) zbcapiMap_DISPATCH(pGpuResource, pCallContext, pParams, pCpuMapping) #define zbcapiAccessCallback(pResource, pInvokingClient, pAllocParams, accessRight) zbcapiAccessCallback_DISPATCH(pResource, pInvokingClient, pAllocParams, accessRight) static inline NV_STATUS zbcapiConstructHal_56cd7a(struct ZbcApi *pZbcApi, struct CALL_CONTEXT *pCallContext, struct RS_RES_ALLOC_PARAMS_INTERNAL *pParams) { @@ -215,84 +219,92 @@ return pGpuResource->__zbcapiShareCallback__(pGpuResource, pInvokingClient, pParentRef, pSharePolicy); } -static inline NV_STATUS zbcapiControl_DISPATCH(struct ZbcApi *pGpuResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { - return pGpuResource->__zbcapiControl__(pGpuResource, pCallContext, pParams); +static inline NV_STATUS zbcapiCheckMemInterUnmap_DISPATCH(struct ZbcApi *pRmResource, NvBool bSubdeviceHandleProvided) { + return pRmResource->__zbcapiCheckMemInterUnmap__(pRmResource, bSubdeviceHandleProvided); } -static inline NV_STATUS zbcapiUnmap_DISPATCH(struct ZbcApi *pGpuResource, struct CALL_CONTEXT *pCallContext, struct RsCpuMapping *pCpuMapping) { - return pGpuResource->__zbcapiUnmap__(pGpuResource, pCallContext, pCpuMapping); +static inline NV_STATUS zbcapiMapTo_DISPATCH(struct ZbcApi *pResource, RS_RES_MAP_TO_PARAMS *pParams) { + return pResource->__zbcapiMapTo__(pResource, pParams); } -static inline NV_STATUS zbcapiGetMemInterMapParams_DISPATCH(struct ZbcApi *pRmResource, RMRES_MEM_INTER_MAP_PARAMS *pParams) { - return pRmResource->__zbcapiGetMemInterMapParams__(pRmResource, pParams); +static inline NV_STATUS zbcapiGetMapAddrSpace_DISPATCH(struct ZbcApi *pGpuResource, struct CALL_CONTEXT *pCallContext, NvU32 mapFlags, NV_ADDRESS_SPACE *pAddrSpace) { + return pGpuResource->__zbcapiGetMapAddrSpace__(pGpuResource, pCallContext, mapFlags, pAddrSpace); } -static inline NV_STATUS zbcapiGetMemoryMappingDescriptor_DISPATCH(struct ZbcApi *pRmResource, struct MEMORY_DESCRIPTOR **ppMemDesc) { - return pRmResource->__zbcapiGetMemoryMappingDescriptor__(pRmResource, ppMemDesc); +static inline NvU32 zbcapiGetRefCount_DISPATCH(struct ZbcApi *pResource) { + return pResource->__zbcapiGetRefCount__(pResource); } -static inline NV_STATUS zbcapiGetMapAddrSpace_DISPATCH(struct ZbcApi *pGpuResource, struct CALL_CONTEXT *pCallContext, NvU32 mapFlags, NV_ADDRESS_SPACE *pAddrSpace) { - return pGpuResource->__zbcapiGetMapAddrSpace__(pGpuResource, pCallContext, mapFlags, pAddrSpace); +static inline void zbcapiAddAdditionalDependants_DISPATCH(struct RsClient *pClient, struct ZbcApi *pResource, RsResourceRef *pReference) { + pResource->__zbcapiAddAdditionalDependants__(pClient, pResource, pReference); } -static inline NvHandle zbcapiGetInternalObjectHandle_DISPATCH(struct ZbcApi *pGpuResource) { - return pGpuResource->__zbcapiGetInternalObjectHandle__(pGpuResource); +static inline NV_STATUS zbcapiControl_Prologue_DISPATCH(struct ZbcApi *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return pResource->__zbcapiControl_Prologue__(pResource, pCallContext, pParams); } -static inline NV_STATUS zbcapiControlFilter_DISPATCH(struct ZbcApi *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { - return pResource->__zbcapiControlFilter__(pResource, pCallContext, pParams); +static inline NV_STATUS zbcapiGetRegBaseOffsetAndSize_DISPATCH(struct ZbcApi *pGpuResource, struct OBJGPU *pGpu, NvU32 *pOffset, NvU32 *pSize) { + return pGpuResource->__zbcapiGetRegBaseOffsetAndSize__(pGpuResource, pGpu, pOffset, pSize); } -static inline void zbcapiAddAdditionalDependants_DISPATCH(struct RsClient *pClient, struct ZbcApi *pResource, RsResourceRef *pReference) { - pResource->__zbcapiAddAdditionalDependants__(pClient, pResource, pReference); +static inline NV_STATUS zbcapiInternalControlForward_DISPATCH(struct ZbcApi *pGpuResource, NvU32 command, void *pParams, NvU32 size) { + return pGpuResource->__zbcapiInternalControlForward__(pGpuResource, command, pParams, size); } -static inline NvU32 zbcapiGetRefCount_DISPATCH(struct ZbcApi *pResource) { - return pResource->__zbcapiGetRefCount__(pResource); +static inline NV_STATUS zbcapiUnmapFrom_DISPATCH(struct ZbcApi *pResource, RS_RES_UNMAP_FROM_PARAMS *pParams) { + return pResource->__zbcapiUnmapFrom__(pResource, pParams); } -static inline NV_STATUS zbcapiCheckMemInterUnmap_DISPATCH(struct ZbcApi *pRmResource, NvBool bSubdeviceHandleProvided) { - return pRmResource->__zbcapiCheckMemInterUnmap__(pRmResource, bSubdeviceHandleProvided); +static inline void zbcapiControl_Epilogue_DISPATCH(struct ZbcApi *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + pResource->__zbcapiControl_Epilogue__(pResource, pCallContext, pParams); } -static inline NV_STATUS zbcapiMapTo_DISPATCH(struct ZbcApi *pResource, RS_RES_MAP_TO_PARAMS *pParams) { - return pResource->__zbcapiMapTo__(pResource, pParams); +static inline NV_STATUS zbcapiControlLookup_DISPATCH(struct ZbcApi *pResource, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams, const struct NVOC_EXPORTED_METHOD_DEF **ppEntry) { + return pResource->__zbcapiControlLookup__(pResource, pParams, ppEntry); } -static inline NV_STATUS zbcapiControl_Prologue_DISPATCH(struct ZbcApi *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { - return pResource->__zbcapiControl_Prologue__(pResource, pCallContext, pParams); +static inline NvHandle zbcapiGetInternalObjectHandle_DISPATCH(struct ZbcApi *pGpuResource) { + return pGpuResource->__zbcapiGetInternalObjectHandle__(pGpuResource); } -static inline NV_STATUS zbcapiGetRegBaseOffsetAndSize_DISPATCH(struct ZbcApi *pGpuResource, struct OBJGPU *pGpu, NvU32 *pOffset, NvU32 *pSize) { - return pGpuResource->__zbcapiGetRegBaseOffsetAndSize__(pGpuResource, pGpu, pOffset, pSize); +static inline NV_STATUS zbcapiControl_DISPATCH(struct ZbcApi *pGpuResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return pGpuResource->__zbcapiControl__(pGpuResource, pCallContext, pParams); } -static inline NvBool zbcapiCanCopy_DISPATCH(struct ZbcApi *pResource) { - return pResource->__zbcapiCanCopy__(pResource); +static inline NV_STATUS zbcapiUnmap_DISPATCH(struct ZbcApi *pGpuResource, struct CALL_CONTEXT *pCallContext, struct RsCpuMapping *pCpuMapping) { + return pGpuResource->__zbcapiUnmap__(pGpuResource, pCallContext, pCpuMapping); } -static inline NV_STATUS zbcapiInternalControlForward_DISPATCH(struct ZbcApi *pGpuResource, NvU32 command, void *pParams, NvU32 size) { - return pGpuResource->__zbcapiInternalControlForward__(pGpuResource, command, pParams, size); +static inline NV_STATUS zbcapiGetMemInterMapParams_DISPATCH(struct ZbcApi *pRmResource, RMRES_MEM_INTER_MAP_PARAMS *pParams) { + return pRmResource->__zbcapiGetMemInterMapParams__(pRmResource, pParams); } -static inline void zbcapiPreDestruct_DISPATCH(struct ZbcApi *pResource) { - pResource->__zbcapiPreDestruct__(pResource); +static inline NV_STATUS zbcapiGetMemoryMappingDescriptor_DISPATCH(struct ZbcApi *pRmResource, struct MEMORY_DESCRIPTOR **ppMemDesc) { + return pRmResource->__zbcapiGetMemoryMappingDescriptor__(pRmResource, ppMemDesc); } -static inline NV_STATUS zbcapiUnmapFrom_DISPATCH(struct ZbcApi *pResource, RS_RES_UNMAP_FROM_PARAMS *pParams) { - return pResource->__zbcapiUnmapFrom__(pResource, pParams); +static inline NV_STATUS zbcapiControlFilter_DISPATCH(struct ZbcApi *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return pResource->__zbcapiControlFilter__(pResource, pCallContext, pParams); } -static inline NV_STATUS zbcapiIsDuplicate_DISPATCH(struct ZbcApi *pResource, NvHandle hMemory, NvBool *pDuplicate) { - return pResource->__zbcapiIsDuplicate__(pResource, hMemory, pDuplicate); +static inline NV_STATUS zbcapiControlSerialization_Prologue_DISPATCH(struct ZbcApi *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return pResource->__zbcapiControlSerialization_Prologue__(pResource, pCallContext, pParams); } -static inline void zbcapiControl_Epilogue_DISPATCH(struct ZbcApi *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { - pResource->__zbcapiControl_Epilogue__(pResource, pCallContext, pParams); +static inline NvBool zbcapiCanCopy_DISPATCH(struct ZbcApi *pResource) { + return pResource->__zbcapiCanCopy__(pResource); } -static inline NV_STATUS zbcapiControlLookup_DISPATCH(struct ZbcApi *pResource, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams, const struct NVOC_EXPORTED_METHOD_DEF **ppEntry) { - return pResource->__zbcapiControlLookup__(pResource, pParams, ppEntry); +static inline void zbcapiPreDestruct_DISPATCH(struct ZbcApi *pResource) { + pResource->__zbcapiPreDestruct__(pResource); +} + +static inline NV_STATUS zbcapiIsDuplicate_DISPATCH(struct ZbcApi *pResource, NvHandle hMemory, NvBool *pDuplicate) { + return pResource->__zbcapiIsDuplicate__(pResource, hMemory, pDuplicate); +} + +static inline void zbcapiControlSerialization_Epilogue_DISPATCH(struct ZbcApi *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + pResource->__zbcapiControlSerialization_Epilogue__(pResource, pCallContext, pParams); } static inline NV_STATUS zbcapiMap_DISPATCH(struct ZbcApi *pGpuResource, struct CALL_CONTEXT *pCallContext, struct RS_CPU_MAP_PARAMS *pParams, struct RsCpuMapping *pCpuMapping) { diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/generated/rmconfig.h nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/rmconfig.h --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/generated/rmconfig.h 2023-10-25 20:19:43.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/generated/rmconfig.h 2024-03-05 22:11:43.000000000 +0000 @@ -245,6 +245,7 @@ #define RMCFG_FEATURE_ORIN_PHYSICAL_RM 1 // Physical layer of RM, disabled only on Orin #define RMCFG_FEATURE_VGPU_GSP_PLUGIN_OFFLOAD 1 // vGPU GSP plugin offload #define RMCFG_FEATURE_LIBOS_3_X 1 // Enable Libos-3.x feature +#define RMCFG_FEATURE_SLINEXT 1 #define RMCFG_FEATURE_NOTEBOOK 1 // Notebook support #define RMCFG_FEATURE_EXTDEV 1 // Daughter boards connected to Quadro GPUs #define RMCFG_FEATURE_EXTDEV_GSYNC 1 // Quadro Sync (QSYNC) board for Quadro GPUs @@ -254,7 +255,6 @@ #define RMCFG_FEATURE_ONSEMI_NB7NQ621M 1 // ONSEMI_NB7NQ621M Redriver Support #define RMCFG_FEATURE_DCB_0X 1 // Fallback DCB routines #define RMCFG_FEATURE_DCB_4X 1 // DCB4x (used on G8x and later) -#define RMCFG_FEATURE_XAPI 0 // Use XAPI for resman api calls #define RMCFG_FEATURE_RMAPI_GRAVEYARD 1 // Use RMAPI Graveyard to translate deprecated APIs #define RMCFG_FEATURE_HOTPLUG_POLLING 0 // HotPlug polling #define RMCFG_FEATURE_MULTI_GPU 1 // Multiple GPUs managed by same RM instance @@ -270,6 +270,7 @@ #define RMCFG_FEATURE_PAGE_RETIREMENT 1 // Offlining bad memory pages from the FB heap #define RMCFG_FEATURE_PMA 1 // Physical memory allocator #define RMCFG_FEATURE_DEVINIT_SCRIPT 0 // VBIOS scripting engine for sharing register sequences +#define RMCFG_FEATURE_UNIX_CONSOLE_STATE 1 // Unix console state management and display programming #define RMCFG_FEATURE_OLD_DAC 1 // Legacy display support with dac code #define RMCFG_FEATURE_CRC_POLLING 1 // GPU supports CRC Polling #define RMCFG_FEATURE_DSI_INFO 0 // DSI information structures support @@ -290,8 +291,10 @@ #define RMCFG_FEATURE_TEGRA_SOC_NVDISPLAY 0 // Tegra SOC NvDisplay Driver #define RMCFG_FEATURE_TEGRA_SOC_NVDISPLAY_MINIMAL 0 // Enable only those parts of display code which are needed for Tegra SOC NvDisplay Driver #define RMCFG_FEATURE_HEAD_REGIONAL_CRC 0 // Display Head Regional CRC support +#define RMCFG_FEATURE_FEATURE_GH180 1 // RMconfig to encapsulate GH180 features #define RMCFG_FEATURE_MULTICAST_FABRIC 1 // Support for MULTICAST_FABRIC #define RMCFG_FEATURE_NVLINK_ERROR_THRESHOLD 1 // Support for NVLINK_ERROR_THRESHOLD +#define RMCFG_FEATURE_FABRIC_LINEAR_ADDRESSING 1 // Unicast fabric memory management @@ -323,6 +326,7 @@ #define RMCFG_CLASS_NV1_MEMORY_LOCAL_USER 1 // aka NV01_MEMORY_LOCAL_USER #define RMCFG_CLASS_NV01_MEMORY_USER 1 // aka NV01_MEMORY_LOCAL_USER #define RMCFG_CLASS_NV1_MEMORY_USER 1 // aka NV01_MEMORY_LOCAL_USER +#define RMCFG_CLASS_NV_MEMORY_EXTENDED_USER 1 // Extended GPU Memory #define RMCFG_CLASS_NV01_MEMORY_VIRTUAL 1 #define RMCFG_CLASS_NV01_MEMORY_SYSTEM_DYNAMIC 1 // aka NV01_MEMORY_VIRTUAL #define RMCFG_CLASS_NV1_MEMORY_SYSTEM_DYNAMIC 1 // aka NV01_MEMORY_VIRTUAL @@ -339,6 +343,7 @@ #define RMCFG_CLASS_NV_IMEX_SESSION 0 #define RMCFG_CLASS_NV01_MEMORY_FLA 1 #define RMCFG_CLASS_NV_MEMORY_FABRIC_EXPORT_V2 0 +#define RMCFG_CLASS_NV_CE_UTILS 1 #define RMCFG_CLASS_NV_MEMORY_FABRIC 1 #define RMCFG_CLASS_NV_MEMORY_FABRIC_IMPORT_V2 0 #define RMCFG_CLASS_NV_MEMORY_FABRIC_EXPORTED_REF 0 @@ -407,6 +412,7 @@ #define RMCFG_CLASS_MAXWELL_PROFILER 1 // Base Profiler Class #define RMCFG_CLASS_MAXWELL_PROFILER_DEVICE 1 // Device level Profiler Client Support #define RMCFG_CLASS_GF100_SUBDEVICE_MASTER 1 +#define RMCFG_CLASS_GF100_SUBDEVICE_INFOROM 1 // Inforom interface #define RMCFG_CLASS_GF100_ZBC_CLEAR 1 #define RMCFG_CLASS_GF100_DISP_SW 1 #define RMCFG_CLASS_GF100_TIMED_SEMAPHORE_SW 1 @@ -416,6 +422,7 @@ #define RMCFG_CLASS_NV50_THIRD_PARTY_P2P 1 #define RMCFG_CLASS_FERMI_TWOD_A 1 // FERMI Graphics 2D #define RMCFG_CLASS_FERMI_VASPACE_A 1 // FERMI virtual address space +#define RMCFG_CLASS_HOPPER_SEC2_WORK_LAUNCH_A 1 // Confidential Computing Work Launch #define RMCFG_CLASS_GF100_HDACODEC 1 #define RMCFG_CLASS_NVB8B0_VIDEO_DECODER 1 // Decoder Class for Hopper #define RMCFG_CLASS_NVC4B0_VIDEO_DECODER 1 // Decoder Class for Turing @@ -444,6 +451,7 @@ #define RMCFG_CLASS_MAXWELL_DMA_COPY_A 1 #define RMCFG_CLASS_ACCESS_COUNTER_NOTIFY_BUFFER 1 // Access Cntr Buffer for Gr #define RMCFG_CLASS_MMU_FAULT_BUFFER 1 // Volta Fault Buffer for Gr +#define RMCFG_CLASS_MMU_VIDMEM_ACCESS_BIT_BUFFER 1 // Ampere Vidmem Access Bit Buffer #define RMCFG_CLASS_TURING_A 1 // Turing Graphics #define RMCFG_CLASS_TURING_COMPUTE_A 1 // Turing Graphics Compute #define RMCFG_CLASS_AMPERE_A 1 // AmpereA (Graphics) @@ -469,7 +477,9 @@ #define RMCFG_CLASS_NV0060_SYNC_GPU_BOOST 1 // Synchronized GPU Boost Class. Defines a set of GPUs for Synchronized Boost #define RMCFG_CLASS_GP100_UVM_SW 1 // UVM SW class to support SW methods for fault cancel #define RMCFG_CLASS_NV_EVENT_BUFFER 1 // Event buffer class used to share event data with UMD +#define RMCFG_CLASS_NV_CONFIDENTIAL_COMPUTE 1 // Confidential Computing Class #define RMCFG_CLASS_NV_COUNTER_COLLECTION_UNIT 1 // Counter Collection Unit Class +#define RMCFG_CLASS_NV_SEMAPHORE_SURFACE 1 // GPU Semaphore encapsulation class @@ -482,7 +492,8 @@ #define RMCFG_MODULE_ENGSTATE 1 // Base class for engines with generic constructors, StateLoad, etc. #define RMCFG_MODULE_HOSTENG 1 // Base class for host engines #define RMCFG_MODULE_FLCNABLE 0 // Base class for engines requiring falcon -#define RMCFG_MODULE_PMUCLIENT 0 // Base class for engines that use PMU engine +#define RMCFG_MODULE_PMUCLIENT 0 // Base class for implementations of behavior to interact with the PMU engine +#define RMCFG_MODULE_PMU_CLIENT_IMPLEMENTER 0 // Base class for engines that use PMU engine #define RMCFG_MODULE_INTRABLE 0 // Base class to generate and service top-level interrupts #define RMCFG_MODULE_MUTEXABLE 0 // Base class for engines that implements mutex #define RMCFG_MODULE_GpuMutexMgr 0 // GPU Mutex Manager @@ -566,7 +577,7 @@ #define RMCFG_MODULE_KERNEL_CE 1 // Kernel Copy Engine #define RMCFG_MODULE_PMU 0 // PMU peregrine core #define RMCFG_MODULE_KERNEL_PMU 1 // PMU peregrine core on Kernel(CPU) RM -#define RMCFG_MODULE_PLATFORM_REQUEST_HANDLER 0 // Platform Request Handler on Kernel(CPU) RM +#define RMCFG_MODULE_PLATFORM_REQUEST_HANDLER 1 // Platform Request Handler on Kernel(CPU) RM #define RMCFG_MODULE_MSENC 0 // Video Encoder (MSENC) Engine #define RMCFG_MODULE_KERNEL_NVENC 1 #define RMCFG_MODULE_HDA 0 // High Definition Audio (HDA) Engine @@ -662,9 +673,11 @@ #define RMCFG_MODULE_DCECLIENTRM 0 // DCE Client RM #define RMCFG_MODULE_DCB 0 // Display Control Block for all display related data in VBIOS/DCB Image #define RMCFG_MODULE_DISPMACRO 0 // DispMacro RM infrastructure for IED removal from VBIOS +#define RMCFG_MODULE_CONF_COMPUTE 1 // Confidential Compute #define RMCFG_MODULE_DISP_MGR 0 // Lid- and dock-related disp code for NOTEBOOK #define RMCFG_MODULE_PLATFORM 1 // Object for platform related features #define RMCFG_MODULE_KERNEL_CCU 1 // Counter Collection Unit Kernel(CPU) RM +#define RMCFG_MODULE_SPDM 1 // Secure Protocol and Data Management (SPDM) on Kernel(CPU) RM diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/inc/kernel/core/locks.h nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/inc/kernel/core/locks.h --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/inc/kernel/core/locks.h 2023-10-25 20:20:31.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/inc/kernel/core/locks.h 2024-03-05 22:12:51.000000000 +0000 @@ -79,17 +79,17 @@ NvU32 index; } LOCK_TRACE_INFO; -#define INSERT_LOCK_TRACE(plti, ra, t, d16, d32, ti, irql, pr, ts) \ -{ \ - (plti)->entries[(plti)->index].callerRA = (NvUPtr)ra; \ - (plti)->entries[(plti)->index].type = t; \ - (plti)->entries[(plti)->index].data16.value = d16; \ - (plti)->entries[(plti)->index].data32.value = d32; \ - (plti)->entries[(plti)->index].threadId = ti; \ - (plti)->entries[(plti)->index].timestamp = ts; \ - (plti)->entries[(plti)->index].bHighIrql = irql; \ - (plti)->entries[(plti)->index].priority = pr; \ - (plti)->index = ((plti)->index + 1) % MAX_TRACE_LOCK_CALLS; \ +#define INSERT_LOCK_TRACE(plti, ra, t, d16, d32, ti, irql, pr, ts) \ +{ \ + (plti)->entries[(plti)->index].callerRA = (NvUPtr)ra; \ + (plti)->entries[(plti)->index].type = t; \ + (plti)->entries[(plti)->index].data16.value = d16; \ + (plti)->entries[(plti)->index].data32.value = d32; \ + (plti)->entries[(plti)->index].threadId = ti; \ + (plti)->entries[(plti)->index].timestamp = ts; \ + (plti)->entries[(plti)->index].bHighIrql = irql; \ + (plti)->entries[(plti)->index].priority = pr; \ + (plti)->index = ((plti)->index + 1) % MAX_TRACE_LOCK_CALLS; \ } // diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/inc/kernel/core/prelude.h nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/inc/kernel/core/prelude.h --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/inc/kernel/core/prelude.h 2023-10-25 20:20:31.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/inc/kernel/core/prelude.h 2024-03-05 22:12:51.000000000 +0000 @@ -81,11 +81,7 @@ #define NV_ROUNDUP(a,b) ((NV_CEIL(a,b))*(b)) #define NV_ROUND_TO_QUANTA(a, quanta) (((quanta) == 0) ? (a): ((((a) + ((quanta) >> 1)) / (quanta)) * (quanta))) #define NV_FLOOR_TO_QUANTA(a, quanta) (((a) / (quanta)) * (quanta)) -#ifndef NV_SIZEOF32 -#define NV_SIZEOF32(x) (sizeof(x)) -#endif #define NV_ARRAY_ELEMENTS(x) ((sizeof(x)/sizeof((x)[0]))) -#define NV_ARRAY_ELEMENTS32(x) ((NV_SIZEOF32(x)/NV_SIZEOF32((x)[0]))) #define NV_BYTESWAP16(a) ((((a) & 0xff00)>>8) | \ (((a) & 0x00ff)<<8)) #define NV_BYTESWAP32(a) ((((a) & 0xff000000)>>24) | \ diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/inc/kernel/core/printf.h nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/inc/kernel/core/printf.h --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/inc/kernel/core/printf.h 2023-10-25 20:20:31.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/inc/kernel/core/printf.h 2024-03-05 22:12:51.000000000 +0000 @@ -118,12 +118,12 @@ #if !NVCPU_IS_RISCV64 -#define DBG_BREAKPOINT_EX(PGPU, LEVEL) \ - do \ - { \ - NV_PRINTF(LEVEL_ERROR, "bp @ " NV_FILE_FMT ":%d\n", NV_FILE, __LINE__);\ - osFlushLog(); \ - DBG_ROUTINE(); \ +#define DBG_BREAKPOINT_EX(PGPU, LEVEL) \ + do \ + { \ + NV_PRINTF(LEVEL_ERROR, "bp @ " NV_FILE_FMT ":%d\n", NV_FILE, __LINE__); \ + osFlushLog(); \ + DBG_ROUTINE(); \ } while (0) #else // !NVCPU_IS_RISCV64 @@ -172,7 +172,7 @@ #include "utils/nvprintf.h" -#define MAX_ERROR_STRING 256 +#define MAX_ERROR_STRING 512 #ifndef NVPORT_CHECK_PRINTF_ARGUMENTS #define NVPORT_CHECK_PRINTF_ARGUMENTS(x,c) #endif @@ -247,48 +247,48 @@ // and return NOT_FULL_POWER. See bug 1679965. // // -#define API_GPU_FULL_POWER_SANITY_CHECK(pGpu, bGpuAccess, bAllowWithoutSysmemAccess) \ - if ((!gpuIsGpuFullPower(pGpu)) && \ - (!(pGpu)->getProperty((pGpu), \ - PDB_PROP_GPU_IN_PM_RESUME_CODEPATH))) \ - { \ - DBG_BREAKPOINT(); \ - if (bGpuAccess || (!gpuIsSurpriseRemovalSupported(pGpu))) \ - { \ - return NV_ERR_GPU_NOT_FULL_POWER; \ - } \ - else if (gpuIsSurpriseRemovalSupported(pGpu) && \ - (pGpu)->getProperty((pGpu), PDB_PROP_GPU_IS_CONNECTED)) \ - { \ - return NV_ERR_GPU_NOT_FULL_POWER; \ - } \ - } \ - if (!(bAllowWithoutSysmemAccess) && !gpuCheckSysmemAccess(pGpu)) \ - { \ - return NV_ERR_GPU_NOT_FULL_POWER; \ +#define API_GPU_FULL_POWER_SANITY_CHECK(pGpu, bGpuAccess, bAllowWithoutSysmemAccess) \ + if ((!gpuIsGpuFullPower(pGpu)) && \ + (!(pGpu)->getProperty((pGpu), \ + PDB_PROP_GPU_IN_PM_RESUME_CODEPATH))) \ + { \ + DBG_BREAKPOINT(); \ + if (bGpuAccess || (!gpuIsSurpriseRemovalSupported(pGpu))) \ + { \ + return NV_ERR_GPU_NOT_FULL_POWER; \ + } \ + else if (gpuIsSurpriseRemovalSupported(pGpu) && \ + (pGpu)->getProperty((pGpu), PDB_PROP_GPU_IS_CONNECTED)) \ + { \ + return NV_ERR_GPU_NOT_FULL_POWER; \ + } \ + } \ + if (!(bAllowWithoutSysmemAccess) && !gpuCheckSysmemAccess(pGpu)) \ + { \ + return NV_ERR_GPU_NOT_FULL_POWER; \ } #define API_GPU_FULL_POWER_SANITY_CHECK_OR_GOTO(pGpu, bGpuAccess, bAllowWithoutSysmemAccess, status, tag) \ - if ((!gpuIsGpuFullPower(pGpu)) && \ - (!(pGpu)->getProperty((pGpu), \ - PDB_PROP_GPU_IN_PM_RESUME_CODEPATH))) \ - { \ - DBG_BREAKPOINT(); \ - if (bGpuAccess || (!gpuIsSurpriseRemovalSupported(pGpu))) \ - { \ - status = NV_ERR_GPU_NOT_FULL_POWER; \ - goto tag; \ - } \ - else if (gpuIsSurpriseRemovalSupported(pGpu) && \ - (pGpu)->getProperty((pGpu), PDB_PROP_GPU_IS_CONNECTED)) \ - { \ - status = NV_ERR_GPU_NOT_FULL_POWER; \ - goto tag; \ - } \ - } \ - if (!(bAllowWithoutSysmemAccess) && !gpuCheckSysmemAccess(pGpu)) \ - { \ - return NV_ERR_GPU_NOT_FULL_POWER; \ + if ((!gpuIsGpuFullPower(pGpu)) && \ + (!(pGpu)->getProperty((pGpu), \ + PDB_PROP_GPU_IN_PM_RESUME_CODEPATH))) \ + { \ + DBG_BREAKPOINT(); \ + if (bGpuAccess || (!gpuIsSurpriseRemovalSupported(pGpu))) \ + { \ + status = NV_ERR_GPU_NOT_FULL_POWER; \ + goto tag; \ + } \ + else if (gpuIsSurpriseRemovalSupported(pGpu) && \ + (pGpu)->getProperty((pGpu), PDB_PROP_GPU_IS_CONNECTED)) \ + { \ + status = NV_ERR_GPU_NOT_FULL_POWER; \ + goto tag; \ + } \ + } \ + if (!(bAllowWithoutSysmemAccess) && !gpuCheckSysmemAccess(pGpu)) \ + { \ + return NV_ERR_GPU_NOT_FULL_POWER; \ } @@ -301,6 +301,15 @@ #define DBG_VAL_PTR(p) #endif +#define NV_ERROR_LOG(pGpu, num, fmt, ...) \ + nvErrorLog_va((void*)pGpu, num, fmt, ##__VA_ARGS__); \ + NVLOG_PRINTF(NV_PRINTF_MODULE, NVLOG_ROUTE_RM, LEVEL_ERROR, \ + NV_PRINTF_ADD_PREFIX("Xid %d: " fmt), num, ##__VA_ARGS__) + +#define NV_ERROR_LOG_DATA(pGpu, num, fmt, ...) \ + portDbgPrintf(NV_PRINTF_ADD_PREFIX(fmt), ##__VA_ARGS__); \ + NVLOG_PRINTF(NV_PRINTF_MODULE, NVLOG_ROUTE_RM, LEVEL_ERROR, \ + NV_PRINTF_ADD_PREFIX(fmt), ##__VA_ARGS__) void nvErrorLog(void *pVoid, NvU32 num, const char *pFormat, va_list arglist); void nvErrorLog_va(void * pGpu, NvU32 num, const char * pFormat, ...); diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/inc/kernel/core/thread_state.h nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/inc/kernel/core/thread_state.h --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/inc/kernel/core/thread_state.h 2023-10-25 20:20:31.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/inc/kernel/core/thread_state.h 2024-03-05 22:12:51.000000000 +0000 @@ -149,7 +149,7 @@ // // The normal power transition requirement for Windows is 4 seconds. -// Use longer time to let OS fire timeout and ask recovery. +// Use longer time to let OS fire timeout and ask recovery. // #define TIMEOUT_WDDM_POWER_TRANSITION_INTERVAL_MS 9800 diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/inc/kernel/gpu/ce/kernel_ce_private.h nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/inc/kernel/gpu/ce/kernel_ce_private.h --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/inc/kernel/gpu/ce/kernel_ce_private.h 2023-10-25 20:20:32.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/inc/kernel/gpu/ce/kernel_ce_private.h 2024-03-05 22:12:52.000000000 +0000 @@ -39,7 +39,7 @@ * @return NV_OK if the conversion is successful. */ static NV_INLINE -NV_STATUS ceIndexFromType(OBJGPU *pGpu, NvHandle hClient, RM_ENGINE_TYPE rmEngineType, NvU32 *ceIdx) +NV_STATUS ceIndexFromType(OBJGPU *pGpu, Device *pDevice, RM_ENGINE_TYPE rmEngineType, NvU32 *ceIdx) { NV_STATUS status = NV_OK; RM_ENGINE_TYPE localRmEngType = rmEngineType; @@ -56,7 +56,7 @@ KernelMIGManager *pKernelMIGManager = GPU_GET_KERNEL_MIG_MANAGER(pGpu); MIG_INSTANCE_REF ref; - status = kmigmgrGetInstanceRefFromClient(pGpu, pKernelMIGManager, hClient, &ref); + status = kmigmgrGetInstanceRefFromDevice(pGpu, pKernelMIGManager, pDevice, &ref); if (status != NV_OK) return status; diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/inc/kernel/gpu/conf_compute/ccsl.h nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/inc/kernel/gpu/conf_compute/ccsl.h --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/inc/kernel/gpu/conf_compute/ccsl.h 1970-01-01 00:00:00.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/inc/kernel/gpu/conf_compute/ccsl.h 2024-03-05 22:11:21.000000000 +0000 @@ -0,0 +1,3 @@ + +#include "g_ccsl_nvoc.h" + diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/inc/kernel/gpu/conf_compute/ccsl_context.h nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/inc/kernel/gpu/conf_compute/ccsl_context.h --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/inc/kernel/gpu/conf_compute/ccsl_context.h 1970-01-01 00:00:00.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/inc/kernel/gpu/conf_compute/ccsl_context.h 2024-03-05 22:12:52.000000000 +0000 @@ -0,0 +1,61 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef CCSL_CONTEXT_H +#define CCSL_CONTEXT_H + +#include "nvtypes.h" +#include "cc_drv.h" + +struct ccslContext_t +{ + NvHandle hClient; + NvHandle hChannel; + + enum {CSL_MSG_CTR_32, CSL_MSG_CTR_64} msgCounterSize; + + NvU8 keyIn[CC_AES_256_GCM_KEY_SIZE_BYTES]; + union + { + struct + { + NvU8 ivIn[CC_AES_256_GCM_IV_SIZE_BYTES]; + NvU8 ivMaskIn[CC_AES_256_GCM_IV_SIZE_BYTES]; + }; + NvU8 nonce[CC_HMAC_NONCE_SIZE_BYTES]; + }; + + NvU8 keyOut[CC_AES_256_GCM_KEY_SIZE_BYTES]; + NvU8 ivOut[CC_AES_256_GCM_IV_SIZE_BYTES]; + NvU8 ivMaskOut[CC_AES_256_GCM_IV_SIZE_BYTES]; + + NvU64 keyHandleIn; + NvU64 keyHandleOut; + + void *openrmCtx; +}; + +typedef struct ccslContext_t *pCcslContext; +typedef struct ccslContext_t CCSL_CONTEXT; + +#endif // CCSL_CONTEXT_H diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/inc/kernel/gpu/conf_compute/conf_compute.h nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/inc/kernel/gpu/conf_compute/conf_compute.h --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/inc/kernel/gpu/conf_compute/conf_compute.h 1970-01-01 00:00:00.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/inc/kernel/gpu/conf_compute/conf_compute.h 2024-03-05 22:11:22.000000000 +0000 @@ -0,0 +1,3 @@ + +#include "g_conf_compute_nvoc.h" + diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/inc/kernel/gpu/conf_compute/conf_compute_api.h nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/inc/kernel/gpu/conf_compute/conf_compute_api.h --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/inc/kernel/gpu/conf_compute/conf_compute_api.h 1970-01-01 00:00:00.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/inc/kernel/gpu/conf_compute/conf_compute_api.h 2024-03-05 22:11:22.000000000 +0000 @@ -0,0 +1,3 @@ + +#include "g_conf_compute_api_nvoc.h" + diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/inc/kernel/gpu/conf_compute/conf_compute_keystore.h nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/inc/kernel/gpu/conf_compute/conf_compute_keystore.h --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/inc/kernel/gpu/conf_compute/conf_compute_keystore.h 1970-01-01 00:00:00.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/inc/kernel/gpu/conf_compute/conf_compute_keystore.h 2024-03-05 22:12:52.000000000 +0000 @@ -0,0 +1,96 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2021-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef CONF_COMPUTE_KEYSTORE_H +#define CONF_COMPUTE_KEYSTORE_H + +#include "nvtypes.h" +#include "nvstatus.h" +#include "cc_drv.h" +#include "kernel/gpu/fifo/kernel_channel.h" + +// Named values for ccKeyStoreDeposit()'s slotNumber parameter. +#define KEYSTORE_SLOT_GSP 0 +#define KEYSTORE_SLOT_SEC2 1 +// LCE index can range from 0 to 7 inclusive. +#define KEYSTORE_SLOT_LCE_UMD(index) (2 + (index) * 3) +#define KEYSTORE_SLOT_LCE_KMD(index) (3 + (index) * 3) +#define KEYSTORE_SLOT_LCE_MGPU(index) (4 + (index) * 3) + +/*! + * @brief Initialize the keystore. + * + * @param[in] pGpu Pointer to GPU object. + * + * @return NV_ERR_INVALID_STATE if system is not in Confidential Compute mode. + */ +NV_STATUS +ccKeyStoreInit (OBJGPU *pGpu); + +/*! + * @brief Deposits a KMB into a keystore slot. + * + * @param[in] slotNumber Slot number into which the KMB will be deposited. + * @param[in] keyMaterialBundle Pair of key / IV / IV mask tuples. IV will be set to 0 by function. + * + * @return NV_ERR_INVALID_INDEX if slotNumber is illegal, NV_OK otherwise. + */ +NV_STATUS +ccKeyStoreDeposit +( + NvU32 slotNumber, + CC_KMB keyMaterialBundle +); + +/*! + * @brief Retrieves a KMB based on the channel. The keystore uses channel + information such as engine type and the associated privilege mode + to determine which KMB to fetch. + * The IV's channel counter for the given direction is pre-incremented. + * + * @param[in] pKernelChannel + * @param[in] rotateOperation Either: + ROTATE_IV_ENCRYPT + ROTATE_IV_DECRYPT + ROTATE_IV_ALL_VALID + * @param[out] keyMaterialBundle The KMB for the given channel. + * + * @return NV_ERR_INSUFFICIENT_RESOURCES if channel counter overflow would occur. + NV_ERR_GENERIC for other errors. + * NV_OK otherwise. + */ +NV_STATUS +ccKeyStoreRetrieveViaChannel +( + KernelChannel *pKernelChannel, + ROTATE_IV_TYPE rotateOperation, + PCC_KMB keyMaterialBundle +); + +/*! + * @brief Clears the contents of the keystore. + */ +void +cckeyStoreClear (void); + +#endif // CONF_COMPUTE_KEYSTORE_H diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/inc/kernel/gpu/external_device/dac_p2060.h nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/inc/kernel/gpu/external_device/dac_p2060.h --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/inc/kernel/gpu/external_device/dac_p2060.h 2023-10-25 20:20:32.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/inc/kernel/gpu/external_device/dac_p2060.h 2024-03-05 22:12:52.000000000 +0000 @@ -116,6 +116,7 @@ NvU32 tSwapRdyHiLsrMinTime; /* Value of LSR_MIN_TIME in accordance to the time (in us) * swap ready line will remain high.(Provided via a regkey) */ + NV30F1_CTRL_GSYNC_MULTIPLY_DIVIDE_SETTINGS mulDivSettings; // Cached multiplier-divider settings NvU32 syncSkewResolutionInNs; // resolution in ns NvU32 syncSkewMax; // max syncSkew setting in raw units @@ -248,6 +249,8 @@ NV_STATUS gsyncSetStereoLockMode_P2060 (OBJGPU *, PDACEXTERNALDEVICE, NvU32); NV_STATUS gsyncSetMosaic_P2060 (OBJGPU *, PDACEXTERNALDEVICE, NV30F1_CTRL_GSYNC_SET_LOCAL_SYNC_PARAMS *); NV_STATUS gsyncConfigFlashGsync_P2060 (OBJGPU *, PDACEXTERNALDEVICE, NvU32); +NV_STATUS gsyncGetMulDiv_P2060 (OBJGPU *, DACEXTERNALDEVICE *, NV30F1_CTRL_GSYNC_MULTIPLY_DIVIDE_SETTINGS *); +NV_STATUS gsyncSetMulDiv_P2060 (OBJGPU *, DACEXTERNALDEVICE *, NV30F1_CTRL_GSYNC_MULTIPLY_DIVIDE_SETTINGS *); NvBool gsyncSupportsLargeSyncSkew_P2060 (DACEXTERNALDEVICE *); #endif diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/inc/kernel/gpu/falcon/kernel_crashcat_engine.h nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/inc/kernel/gpu/falcon/kernel_crashcat_engine.h --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/inc/kernel/gpu/falcon/kernel_crashcat_engine.h 1970-01-01 00:00:00.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/inc/kernel/gpu/falcon/kernel_crashcat_engine.h 2024-03-05 22:11:30.000000000 +0000 @@ -0,0 +1,3 @@ + +#include "g_kernel_crashcat_engine_nvoc.h" + diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/inc/kernel/gpu/gpu_access.h nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/inc/kernel/gpu/gpu_access.h --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/inc/kernel/gpu/gpu_access.h 2023-10-25 20:20:33.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/inc/kernel/gpu/gpu_access.h 2024-03-05 22:11:26.000000000 +0000 @@ -1,381 +1,3 @@ -/* - * SPDX-FileCopyrightText: Copyright (c) 2004-2021 NVIDIA CORPORATION & AFFILIATES. All rights reserved. - * SPDX-License-Identifier: MIT - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER - * DEALINGS IN THE SOFTWARE. - */ -#ifndef _GPU_ACCESS_H_ -#define _GPU_ACCESS_H_ -#include "ioaccess/ioaccess.h" -#include "gpu/gpu_device_mapping.h" +#include "g_gpu_access_nvoc.h" -// Go straight at the memory or hardware. -#define MEM_RD08(a) (*(const volatile NvU8 *)(a)) -#define MEM_RD16(a) (*(const volatile NvU16 *)(a)) -#define MEM_RD32(a) (*(const volatile NvU32 *)(a)) -#define MEM_WR08(a, d) do { *(volatile NvU8 *)(a) = (d); } while (0) -#define MEM_WR16(a, d) do { *(volatile NvU16 *)(a) = (d); } while (0) -#define MEM_WR32(a, d) do { *(volatile NvU32 *)(a) = (d); } while (0) -#define MEM_WR64(a, d) do { *(volatile NvU64 *)(a) = (d); } while (0) - -// -// Define the signature of the register filter callback function -// -// flags can be optionally used for filters to decide whether to actually -// touch HW or not. flags should be OR'ed every time a new filter is found. (see objgpu.c) -// -typedef void (*GpuWriteRegCallback)(OBJGPU *, void *, NvU32 addr, NvU32 val, NvU32 accessSize, NvU32 flags); -typedef NvU32 (*GpuReadRegCallback)(OBJGPU *, void *, NvU32 addr, NvU32 accessSize, NvU32 flags); - -union GPUHWREG -{ - volatile NvV8 Reg008[1]; - volatile NvV16 Reg016[1]; - volatile NvV32 Reg032[1]; -}; - -typedef union GPUHWREG GPUHWREG; - -// -// Register filter record -// -// If REGISTER_FILTER_FLAGS_READ is set, then that means that the base RegRead -// function will not read the register, so the provided read callback function -// is expected to read the register and return the value. -// -// If REGISTER_FILTER_FLAGS_WRITE is set, then that means that the base RegWrite -// function will not write the register, so the provided callback write function -// is expected to write the given value to the register. -// -// It is an error to specify REGISTER_FILTER_FLAGS_READ and not provide a -// read callback function. -// -// It is an error to specify REGISTER_FILTER_FLAGS_WRITE and not provide a -// write callback function. -// -#define REGISTER_FILTER_FLAGS_READ (NVBIT(0)) -#define REGISTER_FILTER_FLAGS_WRITE (NVBIT(1)) -// filter is in the list but it is invalid and should be removed -#define REGISTER_FILTER_FLAGS_INVALID (NVBIT(2)) - -#define REGISTER_FILTER_FLAGS_VIRTUAL (0) -#define REGISTER_FILTER_FLAGS_READ_WRITE (REGISTER_FILTER_FLAGS_READ | REGISTER_FILTER_FLAGS_WRITE) - -typedef struct REGISTER_FILTER REGISTER_FILTER; - -struct REGISTER_FILTER -{ - REGISTER_FILTER *pNext; //!< pointer to next filter - NvU32 flags; //!< attributes of this filter - DEVICE_INDEX devIndex; //!< filter device - NvU32 devInstance; //!< filter device instance - NvU32 rangeStart; //!< filter range start (can overlap) - NvU32 rangeEnd; //!< filter range end (can overlap) - GpuWriteRegCallback pWriteCallback; //!< callback for write - GpuReadRegCallback pReadCallback; //!< callback for read - void *pParam; //!< pointer to param which gets passed to callbacks -}; - -typedef struct { - REGISTER_FILTER *pRegFilterList; // Active filters - REGISTER_FILTER *pRegFilterRecycleList; // Inactive filters - PORT_SPINLOCK * pRegFilterLock; // Thread-safe list management - NvU32 regFilterRefCnt; // Thread-safe list management - NvBool bRegFilterNeedRemove; // Thread-safe list garbage collection -} DEVICE_REGFILTER_INFO; - -typedef struct DEVICE_MAPPING -{ - GPUHWREG *gpuNvAddr; // CPU Virtual Address - RmPhysAddr gpuNvPAddr; // Physical Base Address - NvU32 gpuNvLength; // Length of the Aperture - NvU32 gpuNvSaveLength; - NvU32 gpuDeviceEnum; // Device ID NV_DEVID_* - NvU32 refCount; // refCount for the device map. - DEVICE_REGFILTER_INFO devRegFilterInfo; // register filter range list -} DEVICE_MAPPING; - -typedef struct -{ - IO_DEVICE parent; - OBJGPU *pGpu; - DEVICE_INDEX deviceIndex; - NvU32 instance; - // The following members are initialized in objgpu.c, - // but are not used anywhere. gpuApertureReg* functions - // fall back to DEVICE_MAPPING instead - GPUHWREG *gpuNvAddr; // CPU Virtual Address - RmPhysAddr gpuNvPAddr; // Physical Base Address - NvU32 gpuNvLength; // Length of Aperture - NvU32 gpuDeviceEnum; // Device ID NV_DEVID_* - NvU32 refCount; // refCount for the device map. - DEVICE_REGFILTER_INFO devRegFilterInfo; // register filter range list -} GPU_IO_DEVICE; - -typedef struct -{ - // Pointer to GPU linked to this RegisterAccess object - OBJGPU *pGpu; - - // HW register access tools - GPUHWREG *gpuFbAddr; - GPUHWREG *gpuInstAddr; - - // Register access profiling - NvU32 regReadCount; - NvU32 regWriteCount; -} RegisterAccess; - -/*! Init register IO access path */ -NV_STATUS regAccessConstruct(RegisterAccess *, OBJGPU *pGpu); - -/*! Shutdown register IO access path */ -void regAccessDestruct(RegisterAccess *); - -/*! Writes to 8 bit register */ -void regWrite008(RegisterAccess *, DEVICE_INDEX, NvU32, NvU32, NvV8); - -/*! Writes to 16 bit register */ -void regWrite016(RegisterAccess *, DEVICE_INDEX, NvU32, NvU32, NvV16); - -/*! Writes to 32 bit register, with thread state on the stack */ -void regWrite032(RegisterAccess *, DEVICE_INDEX, NvU32, NvU32, NvV32, THREAD_STATE_NODE *); - -/*! Unicast register access, with thread state on the stack */ -void regWrite032Unicast(RegisterAccess *, DEVICE_INDEX, NvU32, NvU32, NvV32, THREAD_STATE_NODE *); - -/*! Reads from 8 bit register */ -NvU8 regRead008(RegisterAccess *, DEVICE_INDEX, NvU32, NvU32); - -/*! Reads from 16 bit register */ -NvU16 regRead016(RegisterAccess *, DEVICE_INDEX, NvU32, NvU32); - -/*! Reads from 32 bit register, with thread state on the stack */ -NvU32 regRead032(RegisterAccess *, DEVICE_INDEX, NvU32, NvU32, THREAD_STATE_NODE *); - -/*! Reads from 32 bit register and checks bit mask, with thread state on the stack */ -NvU32 regCheckRead032(RegisterAccess *, NvU32, NvU32, THREAD_STATE_NODE *); - -/*! Reads 32 bit register and polls bit field for specific value */ -NV_STATUS regRead032_AndPoll(RegisterAccess *, DEVICE_INDEX, NvU32, NvU32, NvU32); - -/*! Adds a register filter */ -NV_STATUS regAddRegisterFilter(RegisterAccess *, NvU32, DEVICE_INDEX, NvU32, NvU32, NvU32, GpuWriteRegCallback, GpuReadRegCallback, void *, REGISTER_FILTER **); - -/*! Removes register filter */ -void regRemoveRegisterFilter(RegisterAccess *, REGISTER_FILTER *); - -/*! Check status of read return value for GPU/bus errors */ -void regCheckAndLogReadFailure(RegisterAccess *, NvU32 addr, NvU32 mask, NvU32 value); - -// -// GPU register I/O macros. -// - -// -// GPU neutral macros typically used for register I/O. -// -#define GPU_DRF_SHIFT(drf) ((0?drf) % 32) -#define GPU_DRF_MASK(drf) (0xFFFFFFFF>>(31-((1?drf) % 32)+((0?drf) % 32))) -#define GPU_DRF_DEF(d,r,f,c) ((NV ## d ## r ## f ## c)<>GPU_DRF_SHIFT(NV ## d ## r ## f))&GPU_DRF_MASK(NV ## d ## r ## f)) -#define GPU_DRF_SHIFTMASK(drf) (GPU_DRF_MASK(drf)<<(GPU_DRF_SHIFT(drf))) -#define GPU_DRF_WIDTH(drf) ((1?drf) - (0?drf) + 1) - - -// Device independent macros -// Multiple device instance macros - -#define REG_INST_RD08(g,dev,inst,a) regRead008(GPU_GET_REGISTER_ACCESS(g), DEVICE_INDEX_##dev, inst, a) -#define REG_INST_RD16(g,dev,inst,a) regRead016(GPU_GET_REGISTER_ACCESS(g), DEVICE_INDEX_##dev, inst, a) -#define REG_INST_RD32(g,dev,inst,a) regRead032(GPU_GET_REGISTER_ACCESS(g), DEVICE_INDEX_##dev, inst, a, NULL) - -#define REG_INST_WR08(g,dev,inst,a,v) regWrite008(GPU_GET_REGISTER_ACCESS(g), DEVICE_INDEX_##dev, inst, a, v) -#define REG_INST_WR16(g,dev,inst,a,v) regWrite016(GPU_GET_REGISTER_ACCESS(g), DEVICE_INDEX_##dev, inst, a, v) -#define REG_INST_WR32(g,dev,inst,a,v) regWrite032(GPU_GET_REGISTER_ACCESS(g), DEVICE_INDEX_##dev, inst, a, v, NULL) -#define REG_INST_WR32_UC(g,dev,inst,a,v) regWrite032Unicast(GPU_GET_REGISTER_ACCESS(g), DEVICE_INDEX_##dev, inst, a, v, NULL) - -#define REG_INST_RD32_EX(g,dev,inst,a,t) regRead032(GPU_GET_REGISTER_ACCESS(g), DEVICE_INDEX_##dev, inst, a, t) -#define REG_INST_WR32_EX(g,dev,inst,a,v,t) regWrite032(GPU_GET_REGISTER_ACCESS(g), DEVICE_INDEX_##dev, inst, a, v, t) - -#define REG_INST_DEVIDX_RD32_EX(g,devidx,inst,a,t) regRead032(GPU_GET_REGISTER_ACCESS(g), devidx, inst, a, t) -#define REG_INST_DEVIDX_WR32_EX(g,devidx,inst,a,v,t) regWrite032(GPU_GET_REGISTER_ACCESS(g), devidx, inst, a, v, t) - -// GPU macros defined in terms of DEV_ macros -#define GPU_REG_RD08(g,a) REG_INST_RD08(g,GPU,0,a) -#define GPU_REG_RD16(g,a) REG_INST_RD16(g,GPU,0,a) -#define GPU_REG_RD32(g,a) REG_INST_RD32(g,GPU,0,a) -#define GPU_CHECK_REG_RD32(g,a,m) regCheckRead032(GPU_GET_REGISTER_ACCESS(g),a,m,NULL) -#define GPU_REG_RD32_AND_POLL(g,r,m,v) regRead032_AndPoll(GPU_GET_REGISTER_ACCESS(g), DEVICE_INDEX_GPU, r, m, v) - -#define GPU_REG_WR08(g,a,v) REG_INST_WR08(g,GPU,0,a,v) -#define GPU_REG_WR16(g,a,v) REG_INST_WR16(g,GPU,0,a,v) -#define GPU_REG_WR32(g,a,v) REG_INST_WR32(g,GPU,0,a,v) -#define GPU_REG_WR32_UC(g,a,v) REG_INST_WR32_UC(g,GPU,0,a,v) - -// GPU macros for SR-IOV -#define GPU_VREG_RD32(g, a) GPU_REG_RD32(g, g->sriovState.virtualRegPhysOffset + a) -#define GPU_VREG_WR32(g, a, v) GPU_REG_WR32(g, g->sriovState.virtualRegPhysOffset + a, v) -#define GPU_VREG_RD32_EX(g,a,t) REG_INST_RD32_EX(g, GPU, 0, g->sriovState.virtualRegPhysOffset + a, t) -#define GPU_VREG_WR32_EX(g,a,v,t) REG_INST_WR32_EX(g, GPU, 0, g->sriovState.virtualRegPhysOffset + a, v, t) -#define GPU_VREG_FLD_WR_DRF_DEF(g,d,r,f,c) GPU_VREG_WR32(g, NV##d##r,(GPU_VREG_RD32(g,NV##d##r)&~(GPU_DRF_MASK(NV##d##r##f)<>GPU_DRF_SHIFT(NV ## d ## r ## f))&GPU_DRF_MASK(NV ## d ## r ## f)) - -#define VREG_INST_RD32(g,dev,inst,a) regRead032(GPU_GET_REGISTER_ACCESS(g), DEVICE_INDEX_##dev, inst, g->sriovState.virtualRegPhysOffset + a, NULL) -#define VREG_INST_WR32(g,dev,inst,a,v) regWrite032(GPU_GET_REGISTER_ACCESS(g), DEVICE_INDEX_##dev, inst, g->sriovState.virtualRegPhysOffset + a, v, NULL) -#define GPU_VREG_FLD_WR_DRF_NUM(g,d,r,f,n) VREG_INST_WR32(g,GPU,0,NV##d##r,(VREG_INST_RD32(g,GPU,0,NV##d##r)&~(GPU_DRF_MASK(NV##d##r##f)<sriovState.virtualRegPhysOffset + a) - -#define GPU_VREG_IDX_RD_DRF(g,d,r,i,f) (((GPU_VREG_RD32(g, NV ## d ## r(i)))>>GPU_DRF_SHIFT(NV ## d ## r ## f))&GPU_DRF_MASK(NV ## d ## r ## f)) -#define GPU_VREG_FLD_IDX_WR_DRF_DEF(g,d,r,i,f,c) GPU_VREG_WR32(g, NV##d##r(i),(GPU_VREG_RD32(g,NV##d##r(i))&~(GPU_DRF_MASK(NV##d##r##f)<sriovState.virtualRegPhysOffset + a) -#define GPU_VREG_WR32(g, a, v) gpuRegWr32_dumpinfo(__FUNCTION__,#a,"(VREG)",g, g->sriovState.virtualRegPhysOffset + a, v) - -#endif // GPU_REGISTER_ACCESS_DUMP - -// -// Macros for register I/O -// -#define GPU_FLD_WR_DRF_NUM(g,d,r,f,n) REG_INST_WR32(g,GPU,0,NV##d##r,(REG_INST_RD32(g,GPU,0,NV##d##r)&~(GPU_DRF_MASK(NV##d##r##f)<>GPU_DRF_SHIFT(NV ## d ## r ## f))&GPU_DRF_MASK(NV ## d ## r ## f)) -#define GPU_FLD_TEST_DRF_DEF(g,d,r,f,c) (GPU_REG_RD_DRF(g, d, r, f) == NV##d##r##f##c) -#define GPU_FLD_TEST_DRF_NUM(g,d,r,f,n) (GPU_REG_RD_DRF(g, d, r, f) == n) -#define GPU_FLD_IDX_TEST_DRF_DEF(g,d,r,f,c,i) (GPU_REG_IDX_RD_DRF(g, d, r, i, f) == NV##d##r##f##c) -#define GPU_FLD_2IDX_TEST_DRF_DEF(g,d,r,f,c,i,j) (GPU_REG_2IDX_RD_DRF(g, d, r, i, j, f) == NV##d##r##f##c) - -#define GPU_REG_RD_DRF_EX(g,d,r,f,t) (((GPU_REG_RD32_EX(g, NV ## d ## r, t))>>GPU_DRF_SHIFT(NV ## d ## r ## f))&GPU_DRF_MASK(NV ## d ## r ## f)) - -#define GPU_FLD_WR_DRF_NUM_EX(g,d,r,f,n,t) REG_INST_WR32_EX(g,GPU,0,NV##d##r,(REG_INST_RD32_EX(g,GPU,0,NV##d##r,t)&~(GPU_DRF_MASK(NV##d##r##f)<>GPU_DRF_SHIFT(NV ## d ## r ## f))&GPU_DRF_MASK(NV ## d ## r ## f)) -#define GPU_REG_2IDX_RD_DRF(g,d,r,i,j,f) (((GPU_REG_RD32(g, NV ## d ## r(i, j)))>>GPU_DRF_SHIFT(NV ## d ## r ## f))&GPU_DRF_MASK(NV ## d ## r ## f)) -#define GPU_REG_RD_DRF_IDX(g,d,r,f,i) (((GPU_REG_RD32(g, NV ## d ## r))>>GPU_DRF_SHIFT(NV ## d ## r ## f(i)))&GPU_DRF_MASK(NV ## d ## r ## f(i))) -#define GPU_REG_IDX_OFFSET_RD_DRF(g,d,r,i,o,f) (((GPU_REG_RD32(g, NV ## d ## r(i,o)))>>GPU_DRF_SHIFT(NV ## d ## r ## f))&GPU_DRF_MASK(NV ## d ## r ## f)) - -// -// Macros that abstract the use of bif object to access GPU bus config registers -// This is the preferred set >= NV50 -// -#define GPU_BUS_CFG_RD32(g,r,d) gpuReadBusConfigReg_HAL(g, r, d) -#define GPU_BUS_CFG_WR32(g,r,d) gpuWriteBusConfigReg_HAL(g, r, d) -#define GPU_BUS_CFG_FLD_WR_DRF_DEF(g,x,d,r,f,c) GPU_BUS_CFG_WR32(g, NV##d##r,(x &~(GPU_DRF_MASK(NV##d##r##f)<>(31-(1?sf)+(0?sf))) -#define SF_SHIFTMASK(sf) (SF_MASK(sf) << SF_SHIFT(sf)) -#define SF_DEF(s,f,c) ((NV ## s ## f ## c)<>SF_SHIFT(NV ## s ## f))&SF_MASK(NV ## s ## f)) -#define SF_WIDTH(sf) ((1?sf) - (0?sf) + 1) -// This macro parses multi-word/array defines -#define SF_ARR32_VAL(s,f,arr) \ - (((arr)[SF_INDEX(NV ## s ## f)] >> SF_SHIFT(NV ## s ## f)) & SF_MASK(NV ## s ## f)) -#define FLD_SF_DEF(s,f,d,l) ((l)&~(SF_MASK(NV##s##f) << SF_SHIFT(NV##s##f)))| SF_DEF(s,f,d) -#define FLD_SF_NUM(s,f,n,l) ((l)&~(SF_MASK(NV##s##f) << SF_SHIFT(NV##s##f)))| SF_NUM(s,f,n) -#define FLD_SF_IDX_DEF(s,f,c,i,l) (((l) & ~SF_SHIFTMASK(NV ## s ## f(i))) | SF_IDX_DEF(s,f,c,i)) -#define FLD_SF_IDX_NUM(s,f,n,i,l) (((l) & ~SF_SHIFTMASK(NV ## s ## f(i))) | SF_IDX_NUM(s,f,n,i)) - -#endif // _GPU_ACCESS_H_ diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/inc/kernel/gpu/gpu_acpi_data.h nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/inc/kernel/gpu/gpu_acpi_data.h --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/inc/kernel/gpu/gpu_acpi_data.h 2023-10-25 20:20:33.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/inc/kernel/gpu/gpu_acpi_data.h 2024-03-05 22:12:53.000000000 +0000 @@ -71,8 +71,9 @@ typedef struct JT_METHOD_DATA { NV_STATUS status; - NvU16 jtRevId; NvU32 jtCaps; + NvU16 jtRevId; + NvBool bSBIOSCaps; } JT_METHOD_DATA; typedef struct MUX_METHOD_DATA_ELEMENT diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/inc/kernel/gpu/gpu_child_class_defs.h nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/inc/kernel/gpu/gpu_child_class_defs.h --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/inc/kernel/gpu/gpu_child_class_defs.h 1970-01-01 00:00:00.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/inc/kernel/gpu/gpu_child_class_defs.h 2024-03-05 22:12:53.000000000 +0000 @@ -0,0 +1,47 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2004-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef GPU_CHILD_CLASS_DEFS_H +#define GPU_CHILD_CLASS_DEFS_H + +/*! + * @file + * @details Provides the class definitions for every GPU child class without the + * need to include every individual header. + */ + +#include "core/prelude.h" + +#define GPU_CHILD_CLASS_DEFS_GPU_CHILD(className, accessorName, numInstances, bConstructEarly, gpuField) \ + extern const struct NVOC_CLASS_DEF NV_CONCATENATE(__nvoc_class_def_, className); + +#define GPU_CHILD \ + GPU_CHILD_CLASS_DEFS_GPU_CHILD +#include "gpu/gpu_child_list.h" + +// Sub-classes of GPU children +// Pmu sub-classes +extern const struct NVOC_CLASS_DEF __nvoc_class_def_Pmu10; +extern const struct NVOC_CLASS_DEF __nvoc_class_def_Pmu20; + +#endif // GPU_CHILD_CLASS_DEFS_H diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/inc/kernel/gpu/gpu_child_list.h nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/inc/kernel/gpu/gpu_child_list.h --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/inc/kernel/gpu/gpu_child_list.h 2023-10-25 20:20:33.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/inc/kernel/gpu/gpu_child_list.h 2024-03-05 22:12:53.000000000 +0000 @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 2004-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2004-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -53,252 +53,255 @@ #define GPU_CHILD_MODULE(_rmcfgModule) RMCFG_MODULE_ENABLED(_rmcfgModule) #endif - /* Class Name Accessor Name Max Instances bConstructEarly bAlwaysCreate OBJGPU Field */ + /* Class Name Accessor Name Max Instances bConstructEarly OBJGPU Field */ #if GPU_CHILD_MODULE(FUSE) - GPU_CHILD_SINGLE_INST( OBJFUSE, GPU_GET_FUSE, 1, NV_TRUE, NV_TRUE, pFuse ) + GPU_CHILD_SINGLE_INST( OBJFUSE, GPU_GET_FUSE, 1, NV_TRUE, pFuse ) #endif #if GPU_CHILD_MODULE(BIF) - GPU_CHILD_SINGLE_INST( OBJBIF, GPU_GET_BIF, 1, NV_TRUE, NV_FALSE, pBif ) + GPU_CHILD_SINGLE_INST( OBJBIF, GPU_GET_BIF, 1, NV_TRUE, pBif ) #endif #if GPU_CHILD_MODULE(KERNEL_BIF) - GPU_CHILD_SINGLE_INST( KernelBif, GPU_GET_KERNEL_BIF, 1, NV_TRUE, NV_FALSE, pKernelBif ) + GPU_CHILD_SINGLE_INST( KernelBif, GPU_GET_KERNEL_BIF, 1, NV_TRUE, pKernelBif ) #endif #if GPU_CHILD_MODULE(NNE) - GPU_CHILD_SINGLE_INST( OBJNNE, GPU_GET_NNE, 1, NV_TRUE, NV_FALSE, pNne ) + GPU_CHILD_SINGLE_INST( Nne, GPU_GET_NNE, 1, NV_TRUE, pNne ) #endif #if GPU_CHILD_MODULE(MC) - GPU_CHILD_SINGLE_INST( OBJMC, GPU_GET_MC, 1, NV_FALSE, NV_FALSE, pMc ) + GPU_CHILD_SINGLE_INST( OBJMC, GPU_GET_MC, 1, NV_FALSE, pMc ) #endif #if GPU_CHILD_MODULE(KERNEL_MC) - GPU_CHILD_SINGLE_INST( KernelMc, GPU_GET_KERNEL_MC, 1, NV_FALSE, NV_FALSE, pKernelMc ) + GPU_CHILD_SINGLE_INST( KernelMc, GPU_GET_KERNEL_MC, 1, NV_FALSE, pKernelMc ) #endif #if GPU_CHILD_MODULE(PRIV_RING) - GPU_CHILD_SINGLE_INST( PrivRing, GPU_GET_PRIV_RING, 1, NV_FALSE, NV_FALSE, pPrivRing ) + GPU_CHILD_SINGLE_INST( PrivRing, GPU_GET_PRIV_RING, 1, NV_FALSE, pPrivRing ) #endif #if GPU_CHILD_MODULE(INTR) - GPU_CHILD_SINGLE_INST( SwIntr, GPU_GET_SW_INTR, 1, NV_FALSE, NV_FALSE, pSwIntr ) + GPU_CHILD_SINGLE_INST( SwIntr, GPU_GET_SW_INTR, 1, NV_FALSE, pSwIntr ) #endif #if GPU_CHILD_MODULE(MEMORY_SYSTEM) - GPU_CHILD_SINGLE_INST( MemorySystem, GPU_GET_MEMORY_SYSTEM, 1, NV_FALSE, NV_FALSE, pMemorySystem ) + GPU_CHILD_SINGLE_INST( MemorySystem, GPU_GET_MEMORY_SYSTEM, 1, NV_FALSE, pMemorySystem ) #endif #if GPU_CHILD_MODULE(KERNEL_MEMORY_SYSTEM) - GPU_CHILD_SINGLE_INST( KernelMemorySystem, GPU_GET_KERNEL_MEMORY_SYSTEM, 1, NV_FALSE, NV_FALSE, pKernelMemorySystem ) + GPU_CHILD_SINGLE_INST( KernelMemorySystem, GPU_GET_KERNEL_MEMORY_SYSTEM, 1, NV_FALSE, pKernelMemorySystem ) #endif #if GPU_CHILD_MODULE(MEMORY_MANAGER) - GPU_CHILD_SINGLE_INST( MemoryManager, GPU_GET_MEMORY_MANAGER, 1, NV_FALSE, NV_FALSE, pMemoryManager ) + GPU_CHILD_SINGLE_INST( MemoryManager, GPU_GET_MEMORY_MANAGER, 1, NV_FALSE, pMemoryManager ) #endif #if GPU_CHILD_MODULE(FBFLCN) - GPU_CHILD_SINGLE_INST( OBJFBFLCN, GPU_GET_FBFLCN, 1, NV_FALSE, NV_FALSE, pFbflcn ) + GPU_CHILD_SINGLE_INST( OBJFBFLCN, GPU_GET_FBFLCN, 1, NV_FALSE, pFbflcn ) #endif #if GPU_CHILD_MODULE(HSHUBMANAGER) - GPU_CHILD_SINGLE_INST( OBJHSHUBMANAGER, GPU_GET_HSHUBMANAGER, 1, NV_FALSE, NV_FALSE, pHshMgr ) + GPU_CHILD_SINGLE_INST( OBJHSHUBMANAGER, GPU_GET_HSHUBMANAGER, 1, NV_FALSE, pHshMgr ) #endif #if GPU_CHILD_MODULE(HSHUB) - GPU_CHILD_MULTI_INST ( Hshub, GPU_GET_HSHUB, GPU_MAX_HSHUBS, NV_FALSE, NV_FALSE, pHshub ) + GPU_CHILD_MULTI_INST ( Hshub, GPU_GET_HSHUB, GPU_MAX_HSHUBS, NV_FALSE, pHshub ) #endif #if GPU_CHILD_MODULE(SEQ) - GPU_CHILD_SINGLE_INST( OBJSEQ, GPU_GET_SEQ, 1, NV_FALSE, NV_TRUE, pSeq ) + GPU_CHILD_SINGLE_INST( OBJSEQ, GPU_GET_SEQ, 1, NV_FALSE, pSeq ) #endif #if GPU_CHILD_MODULE(GpuMutexMgr) - GPU_CHILD_SINGLE_INST( GpuMutexMgr, GPU_GET_MUTEX_MGR, 1, NV_FALSE, NV_TRUE, pMutexMgr ) + GPU_CHILD_SINGLE_INST( GpuMutexMgr, GPU_GET_MUTEX_MGR, 1, NV_FALSE, pMutexMgr ) #endif #if GPU_CHILD_MODULE(KERNEL_DISPLAY) - GPU_CHILD_SINGLE_INST( KernelDisplay, GPU_GET_KERNEL_DISPLAY, 1, NV_FALSE, NV_FALSE, pKernelDisplay ) -#endif -#if GPU_CHILD_MODULE(DISP) - GPU_CHILD_SINGLE_INST( OBJDISP, GPU_GET_DISP, 1, NV_FALSE, NV_FALSE, pDisp ) + GPU_CHILD_SINGLE_INST( KernelDisplay, GPU_GET_KERNEL_DISPLAY, 1, NV_FALSE, pKernelDisplay ) #endif #if GPU_CHILD_MODULE(TMR) - GPU_CHILD_SINGLE_INST( OBJTMR, GPU_GET_TIMER, 1, NV_TRUE, NV_TRUE, pTmr ) + GPU_CHILD_SINGLE_INST( OBJTMR, GPU_GET_TIMER, 1, NV_TRUE, pTmr ) +#endif +#if GPU_CHILD_MODULE(DISP) + GPU_CHILD_SINGLE_INST( OBJDISP, GPU_GET_DISP, 1, NV_FALSE, pDisp ) #endif #if GPU_CHILD_MODULE(BUS) - GPU_CHILD_SINGLE_INST( OBJBUS, GPU_GET_BUS, 1, NV_FALSE, NV_FALSE, pBus ) + GPU_CHILD_SINGLE_INST( OBJBUS, GPU_GET_BUS, 1, NV_FALSE, pBus ) #endif #if GPU_CHILD_MODULE(KERNEL_BUS) - GPU_CHILD_SINGLE_INST( KernelBus, GPU_GET_KERNEL_BUS, 1, NV_FALSE, NV_FALSE, pKernelBus ) + GPU_CHILD_SINGLE_INST( KernelBus, GPU_GET_KERNEL_BUS, 1, NV_FALSE, pKernelBus ) #endif #if GPU_CHILD_MODULE(GMMU) - GPU_CHILD_SINGLE_INST( OBJGMMU, GPU_GET_GMMU, 1, NV_FALSE, NV_FALSE, pGmmu ) + GPU_CHILD_SINGLE_INST( OBJGMMU, GPU_GET_GMMU, 1, NV_FALSE, pGmmu ) #endif #if GPU_CHILD_MODULE(KERNEL_GMMU) - GPU_CHILD_SINGLE_INST( KernelGmmu, GPU_GET_KERNEL_GMMU, 1, NV_FALSE, NV_FALSE, pKernelGmmu ) + GPU_CHILD_SINGLE_INST( KernelGmmu, GPU_GET_KERNEL_GMMU, 1, NV_FALSE, pKernelGmmu ) #endif #if GPU_CHILD_MODULE(KERNEL_SEC2) - GPU_CHILD_SINGLE_INST( KernelSec2, GPU_GET_KERNEL_SEC2, 1, NV_FALSE, NV_FALSE, pKernelSec2 ) + GPU_CHILD_SINGLE_INST( KernelSec2, GPU_GET_KERNEL_SEC2, 1, NV_FALSE, pKernelSec2 ) #endif #if GPU_CHILD_MODULE(KERNEL_GSP) - GPU_CHILD_SINGLE_INST( KernelGsp, GPU_GET_KERNEL_GSP, 1, NV_FALSE, NV_FALSE, pKernelGsp ) + GPU_CHILD_SINGLE_INST( KernelGsp, GPU_GET_KERNEL_GSP, 1, NV_FALSE, pKernelGsp ) #endif #if GPU_CHILD_MODULE(DCECLIENTRM) - GPU_CHILD_SINGLE_INST( OBJDCECLIENTRM, GPU_GET_DCECLIENTRM, 1, NV_FALSE, NV_FALSE, pDceclientrm ) + GPU_CHILD_SINGLE_INST( OBJDCECLIENTRM, GPU_GET_DCECLIENTRM, 1, NV_FALSE, pDceclientrm ) #endif #if GPU_CHILD_MODULE(VIRT_MEM_ALLOCATOR) - GPU_CHILD_SINGLE_INST( VirtMemAllocator, GPU_GET_DMA, 1, NV_FALSE, NV_FALSE, pDma ) + GPU_CHILD_SINGLE_INST( VirtMemAllocator, GPU_GET_DMA, 1, NV_FALSE, pDma ) #endif #if GPU_CHILD_MODULE(GRMGR) - GPU_CHILD_SINGLE_INST( GraphicsManager, GPU_GET_GRMGR, 1, NV_FALSE, NV_TRUE, pGrMgr ) + GPU_CHILD_SINGLE_INST( GraphicsManager, GPU_GET_GRMGR, 1, NV_FALSE, pGrMgr ) #endif #if GPU_CHILD_MODULE(MIG_MANAGER) - GPU_CHILD_SINGLE_INST( MIGManager, GPU_GET_MIG_MANAGER, 1, NV_FALSE, NV_TRUE, pMIGManager ) + GPU_CHILD_SINGLE_INST( MIGManager, GPU_GET_MIG_MANAGER, 1, NV_FALSE, pMIGManager ) #endif #if GPU_CHILD_MODULE(KERNEL_MIG_MANAGER) - GPU_CHILD_SINGLE_INST( KernelMIGManager, GPU_GET_KERNEL_MIG_MANAGER, 1, NV_FALSE, NV_TRUE, pKernelMIGManager ) + GPU_CHILD_SINGLE_INST( KernelMIGManager, GPU_GET_KERNEL_MIG_MANAGER, 1, NV_FALSE, pKernelMIGManager ) #endif #if GPU_CHILD_MODULE(KERNEL_GRAPHICS_MANAGER) - GPU_CHILD_SINGLE_INST( KernelGraphicsManager, GPU_GET_KERNEL_GRAPHICS_MANAGER, 1, NV_FALSE, NV_TRUE, pKernelGraphicsManager ) + GPU_CHILD_SINGLE_INST( KernelGraphicsManager, GPU_GET_KERNEL_GRAPHICS_MANAGER, 1, NV_FALSE, pKernelGraphicsManager ) #endif #if GPU_CHILD_MODULE(GR) - GPU_CHILD_MULTI_INST ( Graphics, GPU_GET_GR_UNSAFE, GPU_MAX_GRS, NV_FALSE, NV_FALSE, pGr ) + GPU_CHILD_MULTI_INST ( Graphics, GPU_GET_GR_UNSAFE, GPU_MAX_GRS, NV_FALSE, pGr ) #endif #if GPU_CHILD_MODULE(KERNEL_GRAPHICS) - GPU_CHILD_MULTI_INST ( KernelGraphics, GPU_GET_KERNEL_GRAPHICS, GPU_MAX_GRS, NV_FALSE, NV_FALSE, pKernelGraphics ) + GPU_CHILD_MULTI_INST ( KernelGraphics, GPU_GET_KERNEL_GRAPHICS, GPU_MAX_GRS, NV_FALSE, pKernelGraphics ) #endif #if GPU_CHILD_MODULE(ClockManager) - GPU_CHILD_SINGLE_INST( ClockManager, GPU_GET_CLK_MGR, 1, NV_FALSE, NV_FALSE, pClk ) + GPU_CHILD_SINGLE_INST( ClockManager, GPU_GET_CLK_MGR, 1, NV_FALSE, pClk ) #endif #if GPU_CHILD_MODULE(FAN) - GPU_CHILD_SINGLE_INST( Fan, GPU_GET_FAN, 1, NV_FALSE, NV_FALSE, pFan ) + GPU_CHILD_SINGLE_INST( Fan, GPU_GET_FAN, 1, NV_FALSE, pFan ) #endif #if GPU_CHILD_MODULE(PERF) - GPU_CHILD_SINGLE_INST( Perf, GPU_GET_PERF, 1, NV_FALSE, NV_FALSE, pPerf ) + GPU_CHILD_SINGLE_INST( Perf, GPU_GET_PERF, 1, NV_FALSE, pPerf ) #endif #if GPU_CHILD_MODULE(KERNEL_PERF) - GPU_CHILD_SINGLE_INST( KernelPerf, GPU_GET_KERNEL_PERF, 1, NV_FALSE, NV_FALSE, pKernelPerf ) + GPU_CHILD_SINGLE_INST( KernelPerf, GPU_GET_KERNEL_PERF, 1, NV_FALSE, pKernelPerf ) #endif #if GPU_CHILD_MODULE(THERM) - GPU_CHILD_SINGLE_INST( Therm, GPU_GET_THERM, 1, NV_FALSE, NV_FALSE, pTherm ) + GPU_CHILD_SINGLE_INST( Therm, GPU_GET_THERM, 1, NV_FALSE, pTherm ) #endif #if GPU_CHILD_MODULE(BSP) - GPU_CHILD_MULTI_INST ( OBJBSP, GPU_GET_BSP, GPU_MAX_NVDECS, NV_FALSE, NV_FALSE, pBsp ) + GPU_CHILD_MULTI_INST ( OBJBSP, GPU_GET_BSP, GPU_MAX_NVDECS, NV_FALSE, pBsp ) #endif #if GPU_CHILD_MODULE(CIPHER) - GPU_CHILD_SINGLE_INST( OBJCIPHER, GPU_GET_CIPHER, 1, NV_FALSE, NV_FALSE, pCipher ) + GPU_CHILD_SINGLE_INST( OBJCIPHER, GPU_GET_CIPHER, 1, NV_FALSE, pCipher ) #endif #if GPU_CHILD_MODULE(VBIOS) - GPU_CHILD_SINGLE_INST( OBJVBIOS, GPU_GET_VBIOS, 1, NV_FALSE, NV_TRUE, pVbios ) + GPU_CHILD_SINGLE_INST( OBJVBIOS, GPU_GET_VBIOS, 1, NV_FALSE, pVbios ) #endif #if GPU_CHILD_MODULE(DCB) - GPU_CHILD_SINGLE_INST( OBJDCB, GPU_GET_DCB, 1, NV_FALSE, NV_TRUE, pDcb ) + GPU_CHILD_SINGLE_INST( OBJDCB, GPU_GET_DCB, 1, NV_FALSE, pDcb ) #endif #if GPU_CHILD_MODULE(GPIO) - GPU_CHILD_SINGLE_INST( OBJGPIO, GPU_GET_GPIO, 1, NV_FALSE, NV_TRUE, pGpio ) + GPU_CHILD_SINGLE_INST( OBJGPIO, GPU_GET_GPIO, 1, NV_FALSE, pGpio ) #endif #if GPU_CHILD_MODULE(VOLT) - GPU_CHILD_SINGLE_INST( OBJVOLT, GPU_GET_VOLT, 1, NV_FALSE, NV_FALSE, pVolt ) + GPU_CHILD_SINGLE_INST( OBJVOLT, GPU_GET_VOLT, 1, NV_FALSE, pVolt ) #endif #if GPU_CHILD_MODULE(I2C) - GPU_CHILD_SINGLE_INST( I2c, GPU_GET_I2C, 1, NV_FALSE, NV_TRUE, pI2c ) + GPU_CHILD_SINGLE_INST( I2c, GPU_GET_I2C, 1, NV_FALSE, pI2c ) #endif #if GPU_CHILD_MODULE(SPI) - GPU_CHILD_SINGLE_INST( Spi, GPU_GET_SPI, 1, NV_FALSE, NV_TRUE, pSpi ) + GPU_CHILD_SINGLE_INST( Spi, GPU_GET_SPI, 1, NV_FALSE, pSpi ) #endif #if GPU_CHILD_MODULE(KERNEL_RC) - GPU_CHILD_SINGLE_INST( KernelRc, GPU_GET_KERNEL_RC, 1, NV_FALSE, NV_TRUE, pKernelRc ) + GPU_CHILD_SINGLE_INST( KernelRc, GPU_GET_KERNEL_RC, 1, NV_FALSE, pKernelRc ) #endif #if GPU_CHILD_MODULE(RC) - GPU_CHILD_SINGLE_INST( OBJRC, GPU_GET_RC, 1, NV_FALSE, NV_TRUE, pRC ) + GPU_CHILD_SINGLE_INST( OBJRC, GPU_GET_RC, 1, NV_FALSE, pRC ) #endif #if GPU_CHILD_MODULE(STEREO) - GPU_CHILD_SINGLE_INST( OBJSTEREO, GPU_GET_STEREO, 1, NV_FALSE, NV_TRUE, pStereo ) + GPU_CHILD_SINGLE_INST( OBJSTEREO, GPU_GET_STEREO, 1, NV_FALSE, pStereo ) #endif #if GPU_CHILD_MODULE(INTR) - GPU_CHILD_SINGLE_INST( Intr, GPU_GET_INTR, 1, NV_FALSE, NV_TRUE, pIntr ) + GPU_CHILD_SINGLE_INST( Intr, GPU_GET_INTR, 1, NV_FALSE, pIntr ) #endif #if GPU_CHILD_MODULE(DPAUX) - GPU_CHILD_SINGLE_INST( OBJDPAUX, GPU_GET_DPAUX, 1, NV_FALSE, NV_FALSE, pDpAux ) + GPU_CHILD_SINGLE_INST( OBJDPAUX, GPU_GET_DPAUX, 1, NV_FALSE, pDpAux ) #endif #if GPU_CHILD_MODULE(PMU) - GPU_CHILD_SINGLE_INST( Pmu, GPU_GET_PMU, 1, NV_FALSE, NV_FALSE, pPmu ) + GPU_CHILD_SINGLE_INST( Pmu, GPU_GET_PMU, 1, NV_FALSE, pPmu ) #endif #if GPU_CHILD_MODULE(KERNEL_PMU) - GPU_CHILD_SINGLE_INST( KernelPmu, GPU_GET_KERNEL_PMU, 1, NV_FALSE, NV_FALSE, pKernelPmu ) + GPU_CHILD_SINGLE_INST( KernelPmu, GPU_GET_KERNEL_PMU, 1, NV_FALSE, pKernelPmu ) #endif #if GPU_CHILD_MODULE(CE) - GPU_CHILD_MULTI_INST ( OBJCE, GPU_GET_CE, GPU_MAX_CES, NV_FALSE, NV_FALSE, pCe ) + GPU_CHILD_MULTI_INST ( OBJCE, GPU_GET_CE, GPU_MAX_CES, NV_FALSE, pCe ) #endif #if GPU_CHILD_MODULE(KERNEL_CE) - GPU_CHILD_MULTI_INST ( KernelCE, GPU_GET_KCE, GPU_MAX_CES, NV_FALSE, NV_FALSE, pKCe ) + GPU_CHILD_MULTI_INST ( KernelCE, GPU_GET_KCE, GPU_MAX_CES, NV_FALSE, pKCe ) #endif #if GPU_CHILD_MODULE(MSENC) - GPU_CHILD_MULTI_INST ( OBJMSENC, GPU_GET_MSENC, GPU_MAX_MSENCS, NV_FALSE, NV_FALSE, pMsenc ) + GPU_CHILD_MULTI_INST ( OBJMSENC, GPU_GET_MSENC, GPU_MAX_MSENCS, NV_FALSE, pMsenc ) #endif #if GPU_CHILD_MODULE(HDA) - GPU_CHILD_SINGLE_INST( OBJHDA, GPU_GET_HDA, 1, NV_FALSE, NV_FALSE, pHda ) + GPU_CHILD_SINGLE_INST( OBJHDA, GPU_GET_HDA, 1, NV_FALSE, pHda ) #endif #if GPU_CHILD_MODULE(HDACODEC) - GPU_CHILD_SINGLE_INST( OBJHDACODEC, GPU_GET_HDACODEC, 1, NV_FALSE, NV_FALSE, pHdacodec ) + GPU_CHILD_SINGLE_INST( OBJHDACODEC, GPU_GET_HDACODEC, 1, NV_FALSE, pHdacodec ) #endif #if GPU_CHILD_MODULE(LPWR) - GPU_CHILD_SINGLE_INST( Lpwr, GPU_GET_LPWR, 1, NV_FALSE, NV_FALSE, pLpwr ) + GPU_CHILD_SINGLE_INST( Lpwr, GPU_GET_LPWR, 1, NV_FALSE, pLpwr ) #endif #if GPU_CHILD_MODULE(KERNEL_FIFO) - GPU_CHILD_SINGLE_INST( KernelFifo, GPU_GET_KERNEL_FIFO_UC, 1, NV_FALSE, NV_FALSE, pKernelFifo ) + GPU_CHILD_SINGLE_INST( KernelFifo, GPU_GET_KERNEL_FIFO_UC, 1, NV_FALSE, pKernelFifo ) #endif #if GPU_CHILD_MODULE(FIFO) - GPU_CHILD_SINGLE_INST( OBJFIFO, GPU_GET_FIFO_UC, 1, NV_FALSE, NV_FALSE, pFifo ) + GPU_CHILD_SINGLE_INST( OBJFIFO, GPU_GET_FIFO_UC, 1, NV_FALSE, pFifo ) #endif #if GPU_CHILD_MODULE(INFOROM) - GPU_CHILD_SINGLE_INST( OBJINFOROM, GPU_GET_INFOROM, 1, NV_FALSE, NV_TRUE, pInforom ) + GPU_CHILD_SINGLE_INST( OBJINFOROM, GPU_GET_INFOROM, 1, NV_FALSE, pInforom ) #endif #if GPU_CHILD_MODULE(PMGR) - GPU_CHILD_SINGLE_INST( Pmgr, GPU_GET_PMGR, 1, NV_FALSE, NV_FALSE, pPmgr ) + GPU_CHILD_SINGLE_INST( Pmgr, GPU_GET_PMGR, 1, NV_FALSE, pPmgr ) #endif #if GPU_CHILD_MODULE(UVM) - GPU_CHILD_SINGLE_INST( OBJUVM, GPU_GET_UVM, 1, NV_FALSE, NV_FALSE, pUvm ) + GPU_CHILD_SINGLE_INST( OBJUVM, GPU_GET_UVM, 1, NV_FALSE, pUvm ) #endif #if GPU_CHILD_MODULE(NV_DEBUG_DUMP) - GPU_CHILD_SINGLE_INST( NvDebugDump, GPU_GET_NVD, 1, NV_FALSE, NV_TRUE, pNvd ) + GPU_CHILD_SINGLE_INST( NvDebugDump, GPU_GET_NVD, 1, NV_FALSE, pNvd ) #endif #if GPU_CHILD_MODULE(GRDBG) - GPU_CHILD_SINGLE_INST( SMDebugger, GPU_GET_GRDBG, 1, NV_FALSE, NV_TRUE, pGrdbg ) + GPU_CHILD_SINGLE_INST( SMDebugger, GPU_GET_GRDBG, 1, NV_FALSE, pGrdbg ) #endif #if GPU_CHILD_MODULE(SEC2) - GPU_CHILD_SINGLE_INST( OBJSEC2, GPU_GET_SEC2, 1, NV_FALSE, NV_FALSE, pSec2 ) + GPU_CHILD_SINGLE_INST( OBJSEC2, GPU_GET_SEC2, 1, NV_FALSE, pSec2 ) #endif #if GPU_CHILD_MODULE(LSFM) - GPU_CHILD_SINGLE_INST( OBJLSFM, GPU_GET_LSFM, 1, NV_FALSE, NV_FALSE, pLsfm ) + GPU_CHILD_SINGLE_INST( OBJLSFM, GPU_GET_LSFM, 1, NV_FALSE, pLsfm ) #endif #if GPU_CHILD_MODULE(ACR) - GPU_CHILD_SINGLE_INST( OBJACR, GPU_GET_ACR, 1, NV_FALSE, NV_FALSE, pAcr ) + GPU_CHILD_SINGLE_INST( OBJACR, GPU_GET_ACR, 1, NV_FALSE, pAcr ) #endif #if GPU_CHILD_MODULE(KERNEL_NVLINK) - GPU_CHILD_SINGLE_INST( KernelNvlink, GPU_GET_KERNEL_NVLINK, 1, NV_FALSE, NV_FALSE, pKernelNvlink ) + GPU_CHILD_SINGLE_INST( KernelNvlink, GPU_GET_KERNEL_NVLINK, 1, NV_FALSE, pKernelNvlink ) #endif #if GPU_CHILD_MODULE(NVLINK) - GPU_CHILD_SINGLE_INST( Nvlink, GPU_GET_NVLINK, 1, NV_FALSE, NV_FALSE, pNvLink ) + GPU_CHILD_SINGLE_INST( Nvlink, GPU_GET_NVLINK, 1, NV_FALSE, pNvLink ) #endif #if GPU_CHILD_MODULE(GPULOG) - GPU_CHILD_SINGLE_INST( OBJGPULOG, GPU_GET_GPULOG, 1, NV_FALSE, NV_TRUE, pGpuLog ) + GPU_CHILD_SINGLE_INST( OBJGPULOG, GPU_GET_GPULOG, 1, NV_FALSE, pGpuLog ) #endif #if GPU_CHILD_MODULE(GPUMON) - GPU_CHILD_SINGLE_INST( OBJGPUMON, GPU_GET_GPUMON, 1, NV_FALSE, NV_TRUE, pGpuMon ) + GPU_CHILD_SINGLE_INST( OBJGPUMON, GPU_GET_GPUMON, 1, NV_FALSE, pGpuMon ) #endif #if GPU_CHILD_MODULE(HWPM) - GPU_CHILD_SINGLE_INST( OBJHWPM, GPU_GET_HWPM, 1, NV_FALSE, NV_FALSE, pHwpm ) + GPU_CHILD_SINGLE_INST( OBJHWPM, GPU_GET_HWPM, 1, NV_FALSE, pHwpm ) #endif #if GPU_CHILD_MODULE(GRIDDISPLAYLESS) - GPU_CHILD_SINGLE_INST( OBJGRIDDISPLAYLESS, GPU_GET_GRIDDISPLAYLESS, 1, NV_FALSE, NV_FALSE, pGridDisplayless ) + GPU_CHILD_SINGLE_INST( OBJGRIDDISPLAYLESS, GPU_GET_GRIDDISPLAYLESS, 1, NV_FALSE, pGridDisplayless ) #endif #if GPU_CHILD_MODULE(SWENG) - GPU_CHILD_SINGLE_INST( OBJSWENG, GPU_GET_SWENG, 1, NV_FALSE, NV_FALSE, pSwEng ) + GPU_CHILD_SINGLE_INST( OBJSWENG, GPU_GET_SWENG, 1, NV_FALSE, pSwEng ) #endif #if GPU_CHILD_MODULE(VMMU) - GPU_CHILD_SINGLE_INST( OBJVMMU, GPU_GET_VMMU, 1, NV_FALSE, NV_FALSE, pVmmu ) + GPU_CHILD_SINGLE_INST( OBJVMMU, GPU_GET_VMMU, 1, NV_FALSE, pVmmu ) #endif #if GPU_CHILD_MODULE(NVJPG) - GPU_CHILD_MULTI_INST( OBJNVJPG, GPU_GET_NVJPG, GPU_MAX_NVJPGS, NV_FALSE, NV_FALSE, pNvjpg ) + GPU_CHILD_MULTI_INST( OBJNVJPG, GPU_GET_NVJPG, GPU_MAX_NVJPGS, NV_FALSE, pNvjpg ) #endif #if GPU_CHILD_MODULE(GSP) - GPU_CHILD_SINGLE_INST( Gsp, GPU_GET_GSP, 1, NV_FALSE, NV_FALSE, pGsp ) + GPU_CHILD_SINGLE_INST( Gsp, GPU_GET_GSP, 1, NV_FALSE, pGsp ) #endif #if RMCFG_MODULE_KERNEL_FSP && GPU_CHILD_MODULE(KERNEL_FSP) - GPU_CHILD_SINGLE_INST( KernelFsp, GPU_GET_KERNEL_FSP, 1, NV_FALSE, NV_FALSE, pKernelFsp ) + GPU_CHILD_SINGLE_INST( KernelFsp, GPU_GET_KERNEL_FSP, 1, NV_FALSE, pKernelFsp ) #endif #if GPU_CHILD_MODULE(OFA) - GPU_CHILD_SINGLE_INST( OBJOFA, GPU_GET_OFA, 1, NV_FALSE, NV_FALSE, pOfa ) + GPU_CHILD_SINGLE_INST( OBJOFA, GPU_GET_OFA, 1, NV_FALSE, pOfa ) +#endif +#if RMCFG_MODULE_CONF_COMPUTE && GPU_CHILD_MODULE(CONF_COMPUTE) + GPU_CHILD_SINGLE_INST( ConfidentialCompute, GPU_GET_CONF_COMPUTE, 1, NV_TRUE, pConfCompute ) #endif #if RMCFG_MODULE_KERNEL_CCU && GPU_CHILD_MODULE(KERNEL_CCU) - GPU_CHILD_SINGLE_INST( KernelCcu, GPU_GET_KERNEL_CCU, 1, NV_FALSE, NV_FALSE, pKernelCcu ) + GPU_CHILD_SINGLE_INST( KernelCcu, GPU_GET_KERNEL_CCU, 1, NV_FALSE, pKernelCcu ) #endif // Undefine the entry macros to simplify call sites diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/inc/kernel/gpu/gpu_engine_type.h nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/inc/kernel/gpu/gpu_engine_type.h --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/inc/kernel/gpu/gpu_engine_type.h 2023-10-25 20:20:33.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/inc/kernel/gpu/gpu_engine_type.h 2024-03-05 22:12:53.000000000 +0000 @@ -99,6 +99,7 @@ #define RM_ENGINE_TYPE_NVENC_SIZE 3 #define RM_ENGINE_TYPE_NVJPEG_SIZE 8 #define RM_ENGINE_TYPE_NVDEC_SIZE 8 +#define RM_ENGINE_TYPE_OFA_SIZE 1 #define RM_ENGINE_TYPE_GR_SIZE 8 // Indexed engines @@ -118,6 +119,15 @@ #define RM_ENGINE_TYPE_IS_NVJPEG(i) (((i) >= RM_ENGINE_TYPE_NVJPEG0) && ((i) < RM_ENGINE_TYPE_NVJPEG(RM_ENGINE_TYPE_NVJPEG_SIZE))) #define RM_ENGINE_TYPE_NVJPEG_IDX(i) ((i) - RM_ENGINE_TYPE_NVJPEG0) +#define RM_ENGINE_TYPE_OFA(i) (RM_ENGINE_TYPE_OFA+(i)) +#define RM_ENGINE_TYPE_IS_OFA(i) (((i) >= RM_ENGINE_TYPE_OFA) && ((i) < RM_ENGINE_TYPE_OFA(RM_ENGINE_TYPE_OFA_SIZE))) +#define RM_ENGINE_TYPE_OFA_IDX(i) ((i) - RM_ENGINE_TYPE_OFA) + +#define RM_ENGINE_TYPE_IS_VIDEO(i) (RM_ENGINE_TYPE_IS_NVENC(i) | \ + RM_ENGINE_TYPE_IS_NVDEC(i) | \ + RM_ENGINE_TYPE_IS_NVJPEG(i) | \ + RM_ENGINE_TYPE_IS_OFA(i)) + #define RM_ENGINE_TYPE_GR(i) (RM_ENGINE_TYPE_GR0 + (i)) #define RM_ENGINE_TYPE_IS_GR(i) (((i) >= RM_ENGINE_TYPE_GR0) && ((i) < RM_ENGINE_TYPE_GR(RM_ENGINE_TYPE_GR_SIZE))) #define RM_ENGINE_TYPE_GR_IDX(i) ((i) - RM_ENGINE_TYPE_GR0) diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/inc/kernel/gpu/gpu_fabric_probe.h nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/inc/kernel/gpu/gpu_fabric_probe.h --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/inc/kernel/gpu/gpu_fabric_probe.h 2023-10-25 20:20:33.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/inc/kernel/gpu/gpu_fabric_probe.h 2024-03-05 22:12:54.000000000 +0000 @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 1993-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 1993-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -33,28 +33,31 @@ #define GPU_FABRIC_PROBE_DEFAULT_PROBE_SLOWDOWN_THRESHOLD 10 -typedef struct GPU_FABRIC_PROBE_INFO GPU_FABRIC_PROBE_INFO; +typedef struct GPU_FABRIC_PROBE_INFO_KERNEL GPU_FABRIC_PROBE_INFO_KERNEL; NV_STATUS gpuFabricProbeStart(OBJGPU *pGpu, - GPU_FABRIC_PROBE_INFO **ppGpuFabricProbeInfo); -void gpuFabricProbeStop(GPU_FABRIC_PROBE_INFO *pGpuFabricProbeInfo); + GPU_FABRIC_PROBE_INFO_KERNEL **ppGpuFabricProbeInfoKernel); +void gpuFabricProbeStop(GPU_FABRIC_PROBE_INFO_KERNEL *pGpuFabricProbeInfoKernel); -void gpuFabricProbeSuspend(GPU_FABRIC_PROBE_INFO *pGpuFabricProbeInfo); -NV_STATUS gpuFabricProbeResume(GPU_FABRIC_PROBE_INFO *pGpuFabricProbeInfo); +void gpuFabricProbeSuspend(GPU_FABRIC_PROBE_INFO_KERNEL *pGpuFabricProbeInfoKernel); +NV_STATUS gpuFabricProbeResume(GPU_FABRIC_PROBE_INFO_KERNEL *pGpuFabricProbeInfoKernel); -NV_STATUS gpuFabricProbeGetGpuFabricHandle(GPU_FABRIC_PROBE_INFO *pInfo, NvU64 *pHandle); -NV_STATUS gpuFabricProbeGetGfId(GPU_FABRIC_PROBE_INFO *pInfo, NvU32 *pGfId); -NV_STATUS gpuFabricProbeGetfmCaps(GPU_FABRIC_PROBE_INFO *pInfo, NvU64 *pFmCaps); -NV_STATUS gpuFabricProbeGetClusterUuid(GPU_FABRIC_PROBE_INFO *pInfo, NvUuid *pClusterUuid); -NV_STATUS gpuFabricProbeGetFabricPartitionId(GPU_FABRIC_PROBE_INFO *pInfo, NvU16 *pFabricPartitionId); -NV_STATUS gpuFabricProbeGetGpaAddress(GPU_FABRIC_PROBE_INFO *pInfo, NvU64 *pGpaAddress); -NV_STATUS gpuFabricProbeGetGpaAddressRange(GPU_FABRIC_PROBE_INFO *pInfo, NvU64 *pGpaAddressRange); -NV_STATUS gpuFabricProbeGetFlaAddress(GPU_FABRIC_PROBE_INFO *pInfo, NvU64 *pFlaAddress); -NV_STATUS gpuFabricProbeGetFlaAddressRange(GPU_FABRIC_PROBE_INFO *pInfo, NvU64 *pFlaAddressRange); -NV_STATUS gpuFabricProbeGetNumProbeReqs(GPU_FABRIC_PROBE_INFO *pInfo, NvU64 *numProbes); - -NvBool gpuFabricProbeIsReceived(GPU_FABRIC_PROBE_INFO *pGpuFabricProbeInfo); -NvBool gpuFabricProbeIsSuccess(GPU_FABRIC_PROBE_INFO *pGpuFabricProbeInfo); -NV_STATUS gpuFabricProbeGetFmStatus(GPU_FABRIC_PROBE_INFO *pGpuFabricProbeInfo); +NV_STATUS gpuFabricProbeGetGpuFabricHandle(GPU_FABRIC_PROBE_INFO_KERNEL *pInfo, NvU64 *pHandle); +NV_STATUS gpuFabricProbeGetGfId(GPU_FABRIC_PROBE_INFO_KERNEL *pInfo, NvU32 *pGfId); +NV_STATUS gpuFabricProbeGetfmCaps(GPU_FABRIC_PROBE_INFO_KERNEL *pInfo, NvU64 *pFmCaps); +NV_STATUS gpuFabricProbeGetClusterUuid(GPU_FABRIC_PROBE_INFO_KERNEL *pInfo, NvUuid *pClusterUuid); +NV_STATUS gpuFabricProbeGetFabricPartitionId(GPU_FABRIC_PROBE_INFO_KERNEL *pInfo, NvU16 *pFabricPartitionId); +NV_STATUS gpuFabricProbeGetGpaAddress(GPU_FABRIC_PROBE_INFO_KERNEL *pInfo, NvU64 *pGpaAddress); +NV_STATUS gpuFabricProbeGetGpaAddressRange(GPU_FABRIC_PROBE_INFO_KERNEL *pInfo, NvU64 *pGpaAddressRange); +NV_STATUS gpuFabricProbeGetFlaAddress(GPU_FABRIC_PROBE_INFO_KERNEL *pInfo, NvU64 *pFlaAddress); +NV_STATUS gpuFabricProbeGetFlaAddressRange(GPU_FABRIC_PROBE_INFO_KERNEL *pInfo, NvU64 *pFlaAddressRange); +NV_STATUS gpuFabricProbeGetNumProbeReqs(GPU_FABRIC_PROBE_INFO_KERNEL *pInfo, NvU64 *numProbes); + +NvBool gpuFabricProbeIsReceived(GPU_FABRIC_PROBE_INFO_KERNEL *pGpuFabricProbeInfoKernel); +NvBool gpuFabricProbeIsSuccess(GPU_FABRIC_PROBE_INFO_KERNEL *pGpuFabricProbeInfoKernel); +NV_STATUS gpuFabricProbeGetFmStatus(GPU_FABRIC_PROBE_INFO_KERNEL *pGpuFabricProbeInfoKernel); NvBool gpuFabricProbeIsSupported(OBJGPU *pGpu); +NV_STATUS gpuFabricProbeSetBwMode(NvU8 mode); +NV_STATUS gpuFabricProbeGetlinkMaskToBeReduced(GPU_FABRIC_PROBE_INFO_KERNEL *pGpuFabricProbeInfoKernel, + NvU32 *linkMaskToBeReduced); #endif // GPU_FABRIC_PROBE_H diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/inc/kernel/gpu/gpu_shared_data_map.h nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/inc/kernel/gpu/gpu_shared_data_map.h --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/inc/kernel/gpu/gpu_shared_data_map.h 2023-10-25 20:20:34.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/inc/kernel/gpu/gpu_shared_data_map.h 2024-03-05 22:12:54.000000000 +0000 @@ -41,7 +41,16 @@ NV00DE_SHARED_DATA data; } GpuSharedDataMap; -// Start data write, returns data struct to write into +typedef struct GspUserSharedData { + NvU32 gspAssertCount; +} GspUserSharedData; + +/** + * Start data write, returns data struct to write into + * + * After updating data in the returned NV00DE_SHARED_DATA struct, + * call gpushareddataWriteFinish to push the new data into the user mapping + */ NV00DE_SHARED_DATA * gpushareddataWriteStart(OBJGPU *pGpu); // Finish data write, pushes data cached by above into mapped data void gpushareddataWriteFinish(OBJGPU *pGpu); diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/inc/kernel/gpu/gpu_timeout.h nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/inc/kernel/gpu/gpu_timeout.h --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/inc/kernel/gpu/gpu_timeout.h 2023-10-25 20:20:34.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/inc/kernel/gpu/gpu_timeout.h 2024-03-05 22:12:54.000000000 +0000 @@ -139,6 +139,10 @@ #define gpuScaleTimeout(g,a) timeoutApplyScale(&(g)->timeoutData, a) #define gpuTimeoutCondWait(g,a,b,t) timeoutCondWait(&(g)->timeoutData, t, a, b, __LINE__) -#define GPU_ENG_RESET_TIMEOUT_VALUE(g, t) (t) +// +// In SCSIM simulation platform, both CPU and GPU are simulated and the reg write/read itself +// takes more time. This helper macro handles it with increased timeout value. +// +#define GPU_ENG_RESET_TIMEOUT_VALUE(g, t) ((gpuIsSelfHosted(g) && IS_SIMULATION(g)) ? 1000 : (t)) #endif // _GPU_TIMEOUT_H_ diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/inc/kernel/gpu/gr/kernel_graphics_context_buffers.h nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/inc/kernel/gpu/gr/kernel_graphics_context_buffers.h --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/inc/kernel/gpu/gr/kernel_graphics_context_buffers.h 2023-10-25 20:20:34.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/inc/kernel/gpu/gr/kernel_graphics_context_buffers.h 2024-03-05 22:12:54.000000000 +0000 @@ -34,7 +34,7 @@ * * Not all buffer types are supported on every GPU. */ -#define GR_GLOBALCTX_BUFFER_DEF(x) \ +#define GR_GLOBALCTX_BUFFER_DEF(x) \ NV_ENUM_ENTRY(x, GR_GLOBALCTX_BUFFER_BUNDLE_CB, 0x00000000) \ NV_ENUM_ENTRY(x, GR_GLOBALCTX_BUFFER_PAGEPOOL, 0x00000001) \ NV_ENUM_ENTRY(x, GR_GLOBALCTX_BUFFER_ATTRIBUTE_CB, 0x00000002) \ @@ -50,7 +50,7 @@ #define GR_GLOBALCTX_BUFFER_COUNT NV_ENUM_SIZE(GR_GLOBALCTX_BUFFER) -#define GR_CTX_BUFFER_DEF(x) \ +#define GR_CTX_BUFFER_DEF(x) \ NV_ENUM_ENTRY(x, GR_CTX_BUFFER_MAIN, 0x00000000) \ NV_ENUM_ENTRY(x, GR_CTX_BUFFER_ZCULL, 0x00000001) \ NV_ENUM_ENTRY(x, GR_CTX_BUFFER_PM, 0x00000002) \ diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/inc/kernel/gpu/gsp/gsp_fw_heap.h nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/inc/kernel/gpu/gsp/gsp_fw_heap.h --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/inc/kernel/gpu/gsp/gsp_fw_heap.h 1970-01-01 00:00:00.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/inc/kernel/gpu/gsp/gsp_fw_heap.h 2024-03-05 22:12:54.000000000 +0000 @@ -0,0 +1,79 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2022-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef GSP_FW_HEAP_H +#define GSP_FW_HEAP_H + +// Static defines for the GSP FW WPR Heap +#define GSP_FW_HEAP_PARAM_OS_SIZE_LIBOS2 (0 << 20) // No FB heap usage +#define GSP_FW_HEAP_PARAM_OS_SIZE_LIBOS3 (20 << 20) + +// +// Calibrated by observing RM init heap usage - the amount of GSP-RM heap memory +// used during GSP-RM boot and Kernel RM initialization, up to and including the +// first client subdevice allocation. +// +#define GSP_FW_HEAP_PARAM_BASE_RM_SIZE_TU10X (8 << 20) // Turing thru Ada +#define GSP_FW_HEAP_PARAM_BASE_RM_SIZE_GH100 (14 << 20) // Hopper+ + +// +// Calibrated by observing RM init heap usage on GPUs with various FB sizes. +// This seems to fit the data fairly well, but is likely inaccurate (differences +// in heap usage are more likely correlate with GPU architecture than FB size). +// TODO: this requires more detailed profiling and tuning. +// +#define GSP_FW_HEAP_PARAM_SIZE_PER_GB_FB (96 << 10) // All architectures + +// +// This number is calibrated by profiling the WPR heap usage of a single +// client channel allocation. In practice, channel allocations on newer +// architectures are around 44KB-46KB (depending on internal memory +// tracking overhead configured in GSP-RM). +// +// Note: Turing supports 4096 channels vs 2048 on Ampere+, but the heap is +// sized to support only 2048 channels - otherwise the Turing heap balloons +// to 176MB+ on already small-FB parts. +// +// Note: The 2048 channel limit is per-runlist. GSP-RM currently uses only +// a single ChID space across all engines, because per-runlist channel RAM is +// disabled by default in most configurations. If/once per-runlist ChID spaces +// are used on GSP-RM, this will likely no longer be sufficient/relevant as +// the memory that could be needed for client channel allocations will far +// exceed the amount we can carve out for GSP-RM's heap (max ChID will no longer +// be the limiter). +// +#define GSP_FW_HEAP_PARAM_CLIENT_ALLOC_SIZE ((48 << 10) * 2048) // Support 2048 channels + +#define GSP_FW_HEAP_SIZE_VGPU_DEFAULT (549 << 20) // Default for all VGPU configs + +// Min/max bounds for heap size override by regkey +#define GSP_FW_HEAP_SIZE_OVERRIDE_LIBOS2_MIN_MB (64u) +#define GSP_FW_HEAP_SIZE_OVERRIDE_LIBOS2_MAX_MB (256u) + +#define GSP_FW_HEAP_SIZE_OVERRIDE_LIBOS3_BAREMETAL_MIN_MB (84u) +#define GSP_FW_HEAP_SIZE_OVERRIDE_LIBOS3_BAREMETAL_MAX_MB (276u) + +#define GSP_FW_HEAP_SIZE_OVERRIDE_LIBOS3_VGPU_MIN_MB (549u) +#define GSP_FW_HEAP_SIZE_OVERRIDE_LIBOS3_VGPU_MAX_MB (1024u) + +#endif // GSP_FW_HEAP_H diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/inc/kernel/gpu/gsp/gsp_init_args.h nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/inc/kernel/gpu/gsp/gsp_init_args.h --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/inc/kernel/gpu/gsp/gsp_init_args.h 2023-10-25 20:20:34.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/inc/kernel/gpu/gsp/gsp_init_args.h 2024-03-05 22:12:54.000000000 +0000 @@ -35,6 +35,8 @@ NvU32 pageTableEntryCount; NvLength cmdQueueOffset; NvLength statQueueOffset; + NvLength locklessCmdQueueOffset; + NvLength locklessStatQueueOffset; } MESSAGE_QUEUE_INIT_ARGUMENTS; typedef struct { @@ -51,6 +53,12 @@ MESSAGE_QUEUE_INIT_ARGUMENTS messageQueueInitArguments; GSP_SR_INIT_ARGUMENTS srInitArguments; NvU32 gpuInstance; + + struct + { + NvU64 pa; + NvU64 size; + } profilerArgs; } GSP_ARGUMENTS_CACHED; #endif // GSP_INIT_ARGS_H diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/inc/kernel/gpu/gsp/gsp_static_config.h nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/inc/kernel/gpu/gsp/gsp_static_config.h --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/inc/kernel/gpu/gsp/gsp_static_config.h 2023-10-25 20:20:34.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/inc/kernel/gpu/gsp/gsp_static_config.h 2024-03-05 22:12:54.000000000 +0000 @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 2019-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2019-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -88,7 +88,7 @@ GspSMInfo SM_info; NvBool poisonFuseEnabled; - + NvU64 fb_length; NvU32 fbio_mask; NvU32 fb_bus_width; @@ -111,6 +111,9 @@ NvBool bIsTitan; NvBool bIsTesla; NvBool bIsMobile; + NvBool bIsGc6Rtd3Allowed; + NvBool bIsGcOffRtd3Allowed; + NvBool bIsGcoffLegacyAllowed; NvU64 bar1PdeBase; NvU64 bar2PdeBase; @@ -138,7 +141,10 @@ // Subdevice handle for internal RMAPI control. NvHandle hInternalSubdevice; + NvBool bSelfHostedMode; NvBool bAtsSupported; + + NvBool bIsGpuUefi; } GspStaticConfigInfo; // Pushed from CPU-RM to GSP-RM @@ -158,6 +164,7 @@ NvU64 clPdbProperties; NvU32 Chipset; NvBool bGpuBehindBridge; + NvBool bMnocAvailable; NvBool bUpstreamL0sUnsupported; NvBool bUpstreamL1Unsupported; NvBool bUpstreamL1PorSupported; @@ -166,6 +173,8 @@ BUSINFO FHBBusInfo; BUSINFO chipsetIDInfo; ACPI_METHOD_DATA acpiMethodData; + NvU32 hypervisorType; + NvBool bIsPassthru; NvU64 sysTimerOffsetNs; GSP_VF_INFO gspVFInfo; } GspSystemInfo; diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/inc/kernel/gpu/gsp/message_queue.h nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/inc/kernel/gpu/gsp/message_queue.h --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/inc/kernel/gpu/gsp/message_queue.h 2023-10-25 20:20:34.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/inc/kernel/gpu/gsp/message_queue.h 2024-03-05 22:12:55.000000000 +0000 @@ -27,13 +27,19 @@ #ifndef _MESSAGE_QUEUE_H_ #define _MESSAGE_QUEUE_H_ +// Used for indexing into the MESSAGE_QUEUE_COLLECTION array. +#define RPC_TASK_RM_QUEUE_IDX 0 +#define RPC_TASK_ISR_QUEUE_IDX 1 +#define RPC_QUEUE_COUNT 2 + typedef struct _message_queue_info MESSAGE_QUEUE_INFO; +typedef struct MESSAGE_QUEUE_COLLECTION MESSAGE_QUEUE_COLLECTION; // CPU-side calls -NV_STATUS GspMsgQueueInit(OBJGPU *pGpu, MESSAGE_QUEUE_INFO **ppMQI); +NV_STATUS GspMsgQueuesInit(OBJGPU *pGpu, MESSAGE_QUEUE_COLLECTION **ppMQCollection); +void GspMsgQueuesCleanup(MESSAGE_QUEUE_COLLECTION **ppMQCollection); NV_STATUS GspStatusQueueInit(OBJGPU *pGpu, MESSAGE_QUEUE_INFO **ppMQI); -void GspMsgQueueCleanup(MESSAGE_QUEUE_INFO **ppMQI); NV_STATUS GspMsgQueueSendCommand(MESSAGE_QUEUE_INFO *pMQI, OBJGPU *pGpu); -NV_STATUS GspMsgQueueReceiveStatus(MESSAGE_QUEUE_INFO *pMQI); +NV_STATUS GspMsgQueueReceiveStatus(MESSAGE_QUEUE_INFO *pMQI, OBJGPU *pGpu); #endif // _MESSAGE_QUEUE_H_ diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/inc/kernel/gpu/gsp/message_queue_priv.h nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/inc/kernel/gpu/gsp/message_queue_priv.h --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/inc/kernel/gpu/gsp/message_queue_priv.h 2023-10-25 20:20:34.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/inc/kernel/gpu/gsp/message_queue_priv.h 2024-03-05 22:12:55.000000000 +0000 @@ -42,29 +42,25 @@ typedef struct GSP_MSG_QUEUE_ELEMENT { - NvU32 checkSum; // Set to value needed to make checksum always zero. - NvU32 seqNum; // Sequence number maintained by the message queue. - rpc_message_header_v rpc; + NvU8 authTagBuffer[16]; // Authentication tag buffer. + NvU8 aadBuffer[16]; // AAD buffer. + NvU32 checkSum; // Set to value needed to make checksum always zero. + NvU32 seqNum; // Sequence number maintained by the message queue. + NvU32 elemCount; // Number of message queue elements this message has. + NV_DECLARE_ALIGNED(rpc_message_header_v rpc, 8); } GSP_MSG_QUEUE_ELEMENT; typedef struct _message_queue_info { // Parameters - NvLength pageTableEntryCount; - NvLength pageTableSize; NvLength commandQueueSize; NvLength statusQueueSize; // Shared memory area. - MEMORY_DESCRIPTOR *pSharedMemDesc; - RmPhysAddr sharedMemPA; // Page table for all of shared mem. void *pCommandQueue; void *pStatusQueue; rpc_message_header_v *pRpcMsgBuf; // RPC message buffer VA. - void *pInitMsgBuf; // RPC message buffer VA. - RmPhysAddr initMsgBufPA; // RPC message buffer PA. - // Other CPU-side fields void *pWorkArea; GSP_MSG_QUEUE_ELEMENT *pCmdQueueElement; // Working copy of command queue element. @@ -73,8 +69,22 @@ NvU32 txSeqNum; // Next sequence number for tx. NvU32 rxSeqNum; // Next sequence number for rx. NvU32 txBufferFull; + NvU32 queueIdx; // QueueIndex used to identify which task the message is supposed to be sent to. } MESSAGE_QUEUE_INFO; +typedef struct MESSAGE_QUEUE_COLLECTION +{ + // Parameters + NvLength pageTableEntryCount; + NvLength pageTableSize; + + // Shared memory area. + MEMORY_DESCRIPTOR *pSharedMemDesc; + RmPhysAddr sharedMemPA; // Page table for all of shared mem. + + MESSAGE_QUEUE_INFO rpcQueues[RPC_QUEUE_COUNT]; +} MESSAGE_QUEUE_COLLECTION; + // // Most of the following defines resolve to compile-time constants. // diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/inc/kernel/gpu/intr/engine_idx.h nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/inc/kernel/gpu/intr/engine_idx.h --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/inc/kernel/gpu/intr/engine_idx.h 2023-10-25 20:20:34.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/inc/kernel/gpu/intr/engine_idx.h 2024-03-05 22:12:55.000000000 +0000 @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 1993-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 1993-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -61,6 +61,7 @@ #define MC_ENGINE_IDX_CE7 22 #define MC_ENGINE_IDX_CE8 23 #define MC_ENGINE_IDX_CE9 24 +#define MC_ENGINE_IDX_CE_MAX MC_ENGINE_IDX_CE9 #define MC_ENGINE_IDX_VIC 35 #define MC_ENGINE_IDX_ISOHUB 36 #define MC_ENGINE_IDX_VGPU 37 @@ -133,7 +134,11 @@ #define MC_ENGINE_IDX_GR6_FECS_LOG 160 #define MC_ENGINE_IDX_GR7_FECS_LOG 161 #define MC_ENGINE_IDX_TMR_SWRL 162 -#define MC_ENGINE_IDX_MAX 163 // This must be kept as the max bit if +#define MC_ENGINE_IDX_DISP_GSP 163 +#define MC_ENGINE_IDX_REPLAYABLE_FAULT_CPU 164 +#define MC_ENGINE_IDX_NON_REPLAYABLE_FAULT_CPU 165 +#define MC_ENGINE_IDX_PXUC 166 +#define MC_ENGINE_IDX_MAX 167 // This must be kept as the max bit if // we need to add more engines #define MC_ENGINE_IDX_INVALID 0xFFFFFFFF @@ -156,6 +161,9 @@ // Index ESCHED reference #define MC_ENGINE_IDX_ESCHEDn(x) (MC_ENGINE_IDX_ESCHED + (x)) +#define MC_ENGINE_IDX_IS_CE(x) \ + ((MC_ENGINE_IDX_CE(0) <= (x)) && ((x) <= MC_ENGINE_IDX_CE_MAX)) + MAKE_BITVECTOR(MC_ENGINE_BITVECTOR, MC_ENGINE_IDX_MAX); typedef MC_ENGINE_BITVECTOR *PMC_ENGINE_BITVECTOR; diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/inc/kernel/gpu/intr/intr_common.h nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/inc/kernel/gpu/intr/intr_common.h --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/inc/kernel/gpu/intr/intr_common.h 1970-01-01 00:00:00.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/inc/kernel/gpu/intr/intr_common.h 2024-03-05 22:12:55.000000000 +0000 @@ -0,0 +1,43 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef INTR_COMMON_H +#define INTR_COMMON_H 1 +/*! Common defines used by both Intr and OBJINTRABLE */ + + +/*! Kinds of interrupts that a unit can have. */ +typedef enum { + /*! + * Legacy concept of "stalling" interrupts. + * + * These may have a RETRIGGER mechanism. + */ + INTR_KIND_INTERRUPT, + /*! Notification "non-stalling" interrupts. */ + INTR_KIND_NOTIFICATION, + INTR_KIND_COUNT +} INTR_KIND; + + +#endif /* ifndef INTR_COMMON_H */ diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/inc/kernel/gpu/kern_gpu_power.h nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/inc/kernel/gpu/kern_gpu_power.h --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/inc/kernel/gpu/kern_gpu_power.h 1970-01-01 00:00:00.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/inc/kernel/gpu/kern_gpu_power.h 2024-03-05 22:12:55.000000000 +0000 @@ -0,0 +1,92 @@ + /* + * SPDX-FileCopyrightText: Copyright (c) 2004-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef KERN_GPU_POWER_H +#define KERN_GPU_POWER_H + +#include "ctrl/ctrl2080/ctrl2080power.h" // NV2080_CTRL_GC6_FLAVOR_ID_MAX +#include "diagnostics/profiler.h" + +typedef enum +{ + GPU_GC6_STATE_POWERED_ON = 0 , + GPU_GC6_STATE_EXITED = GPU_GC6_STATE_POWERED_ON , + GPU_GC6_STATE_ENTERING , + GPU_GC6_STATE_ENTERING_FAILED , + GPU_GC6_STATE_ENTERED , + GPU_GC6_STATE_EXITING , + GPU_GC6_STATE_EXITING_FAILED , +} GPU_GC6_STATE; + +// TODO-SC use mask for the bool variables +typedef struct +{ + GPU_GC6_STATE currentState; + NvU32 executedStepMask; // step mask executed during entry sequence + NvU32 stepMask[NV2080_CTRL_GC6_FLAVOR_ID_MAX]; // step mask cache +} _GPU_GC6_STATE; + +// GPU event mask operation +#define GC6_REFCOUNT_MASK_SET(pGpu, refCountBit) \ + do \ + { \ + if (pGpu != NULL) \ + { \ + ((pGpu->gc6State.refCountMask) |= (NVBIT(refCountBit))); \ + } \ + } while(0) + +#define GC6_REFCOUNT_MASK_CLEAR(pGpu, refCountBit) \ + do \ + { \ + if (pGpu != NULL) \ + { \ + ((pGpu->gc6State.refCountMask) &= ~(NVBIT(refCountBit))); \ + } \ + } while(0) + +#define GC6_REFCOUNT_MASK_GET_FROM_EVENT(event) ((event / 2)) + +// GC6 related defines +#define GC6_FB_CLAMP_TIMEOUT_MS 10 + +// Macros for GPU_GC6_STATE +#define IS_GPU_GC6_STATE_POWERED_ON(obj) (obj->gc6State.currentState == GPU_GC6_STATE_POWERED_ON) +#define IS_GPU_GC6_STATE_EXITED(obj) (obj->gc6State.currentState == GPU_GC6_STATE_EXITED) +#define IS_GPU_GC6_STATE_ENTERING(obj) (obj->gc6State.currentState == GPU_GC6_STATE_ENTERING) +#define IS_GPU_GC6_STATE_ENTERED(obj) (obj->gc6State.currentState == GPU_GC6_STATE_ENTERED) +#define IS_GPU_GC6_STATE_EXITING(obj) (obj->gc6State.currentState == GPU_GC6_STATE_EXITING) + +#define SET_GPU_GC6_STATE(obj, state) (obj->gc6State.currentState = state) +#define SET_GPU_GC6_STATE_AND_LOG(obj, state) \ + do { \ + SET_GPU_GC6_STATE(obj, state); \ + RMTRACE_GPU(_GC6_STATE, obj->gpuId, state, 0, 0, 0, 0, 0, 0); \ + } while(0) + +//Macro to check is a given GC6 step id is set +#define GPU_IS_GC6_STEP_ID_SET(stepId, stepMask) \ + ((NVBIT(NV2080_CTRL_GC6_STEP_ID_##stepId) & (stepMask)) != 0) + + +#endif // KERN_GPU_POWER_H diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/inc/kernel/gpu/mem_mgr/ce_utils.h nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/inc/kernel/gpu/mem_mgr/ce_utils.h --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/inc/kernel/gpu/mem_mgr/ce_utils.h 1970-01-01 00:00:00.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/inc/kernel/gpu/mem_mgr/ce_utils.h 2024-03-05 22:12:55.000000000 +0000 @@ -0,0 +1,117 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#include "g_ce_utils_nvoc.h" + +#ifndef CE_UTILS_H +#define CE_UTILS_H + +#include "gpu/gpu_resource.h" // GpuResource +#include "class/cl0050.h" +#include "ctrl/ctrl0050.h" + +#include "kernel/gpu/mem_mgr/channel_utils.h" + +typedef struct +{ + MEMORY_DESCRIPTOR *pMemDesc; + NvU64 offset; + NvU64 length; + NvU32 pattern; + NvU64 flags; + NvU64 submittedWorkId; // Payload to poll for async completion +} CEUTILS_MEMSET_PARAMS; + +typedef struct +{ + MEMORY_DESCRIPTOR *pSrcMemDesc; + MEMORY_DESCRIPTOR *pDstMemDesc; + NvU64 dstOffset; + NvU64 srcOffset; + NvU64 length; + NvU64 flags; + NvU64 submittedWorkId; // Payload to poll for async completion +} CEUTILS_MEMCOPY_PARAMS; + + +NVOC_PREFIX(ceutils) class CeUtils : Object +{ +public: + NV_STATUS ceutilsConstruct(CeUtils *pCeUtils, OBJGPU *pGpu, KERNEL_MIG_GPU_INSTANCE *pKernelMIGGPUInstance, + NV0050_ALLOCATION_PARAMETERS *pAllocParams); + void ceutilsDestruct(CeUtils *pCeUtils); + + NV_STATUS ceutilsMemset(CeUtils *pCeUtils, CEUTILS_MEMSET_PARAMS *pParams); + NV_STATUS ceutilsMemcopy(CeUtils *pCeUtils, CEUTILS_MEMCOPY_PARAMS *pParams); + + NvU64 ceutilsUpdateProgress(CeUtils *pCeUtils); + void ceutilsServiceInterrupts(CeUtils *pCeUtils); + + // + // Internal states + // + + NvHandle hClient; + NvHandle hDevice; + NvHandle hSubdevice; + + OBJCHANNEL *pChannel; + OBJGPU *pGpu; + + KernelCE *pKCe; + NvBool bUseVasForCeCopy; + NvU32 hTdCopyClass; + NvU64 lastSubmittedPayload; + NvU64 lastCompletedPayload; +}; + + +#if defined(DEBUG) || defined (DEVELOP) +NVOC_PREFIX(ceutilsapi) class CeUtilsApi : GpuResource +{ +public: + NV_STATUS ceutilsapiConstruct(CeUtilsApi *pCeUtilsApi, CALL_CONTEXT *pCallContext, + RS_RES_ALLOC_PARAMS_INTERNAL *pParams) + : GpuResource(pCallContext, pParams); + + void ceutilsapiDestruct(CeUtilsApi *pCeUtilsApi); + + // + // Below APIs are only provided for SRT testing, thus only available for debug or + // develop driver builds + // + // + RMCTRL_EXPORT(NV0050_CTRL_CMD_MEMSET, RMCTRL_FLAGS(PRIVILEGED, API_LOCK_READONLY)) + NV_STATUS ceutilsapiCtrlCmdMemset(CeUtilsApi *pCeUtilsApi, NV0050_CTRL_MEMSET_PARAMS *pParams); + + RMCTRL_EXPORT(NV0050_CTRL_CMD_MEMCOPY, RMCTRL_FLAGS(PRIVILEGED, API_LOCK_READONLY)) + NV_STATUS ceutilsapiCtrlCmdMemcopy(CeUtilsApi *pCeUtilsApi, NV0050_CTRL_MEMCOPY_PARAMS *pParams); + + RMCTRL_EXPORT(NV0050_CTRL_CMD_CHECK_PROGRESS, RMCTRL_FLAGS(PRIVILEGED, API_LOCK_READONLY)) + NV_STATUS ceutilsapiCtrlCmdCheckProgress(CeUtilsApi *pCeUtilsApi, NV0050_CTRL_CHECK_PROGRESS_PARAMS *pParams); + + CeUtils *pCeUtils; +}; +#endif + +#endif // CE_UTILS_H diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/inc/kernel/gpu/mem_mgr/ce_utils_sizes.h nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/inc/kernel/gpu/mem_mgr/ce_utils_sizes.h --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/inc/kernel/gpu/mem_mgr/ce_utils_sizes.h 1970-01-01 00:00:00.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/inc/kernel/gpu/mem_mgr/ce_utils_sizes.h 2024-03-05 22:12:55.000000000 +0000 @@ -0,0 +1,42 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef _CE_UTILS_SIZES_H +#define _CE_UTILS_SIZES_H + +#define NUM_COPY_BLOCKS 4096 +#define CHANNEL_HOST_SEMAPHORE_SIZE 4 +#define CHANNEL_ENGINE_SEMAPHORE_SIZE 4 +#define GPFIFO_SIZE NV906F_GP_ENTRY__SIZE * NUM_COPY_BLOCKS +#define CHANNEL_NOTIFIER_SIZE (sizeof(NvNotification) * \ + NV_CHANNELGPFIFO_NOTIFICATION_TYPE__SIZE_1) + +#define CE_MAX_BYTES_PER_LINE 0xffffffffULL +#define CE_METHOD_SIZE_PER_BLOCK 0x64 +#define FAST_SCRUBBER_METHOD_SIZE_PER_BLOCK 0x78 + +// number of bytes per sec2 method-stream (including host methods) +#define SEC2_METHOD_SIZE_PER_BLOCK 0x94 +#define SEC2_AUTH_TAG_BUF_SEMAPHORE_SIZE 4 + +#endif // _CE_UTILS_SIZES_H diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/inc/kernel/gpu/mem_mgr/channel_utils.h nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/inc/kernel/gpu/mem_mgr/channel_utils.h --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/inc/kernel/gpu/mem_mgr/channel_utils.h 1970-01-01 00:00:00.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/inc/kernel/gpu/mem_mgr/channel_utils.h 2024-03-05 22:12:55.000000000 +0000 @@ -0,0 +1,159 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef _CHANNEL_UTILS_H_ +#define _CHANNEL_UTILS_H_ + +#include "core/core.h" +#include "gpu/gpu.h" +#include "gpu/mem_mgr/mem_mgr.h" +#include "gpu/ce/kernel_ce.h" +#include "gpu/bus/kern_bus.h" +#include "core/prelude.h" +#include "rmapi/rs_utils.h" +#include "nvos.h" + +#include "class/cl906f.h" +#include "class/cl906f.h" +#include "class/cl906fsw.h" + +#include "class/clb0b5.h" // MAXWELL_DMA_COPY_A +#include "class/clc0b5.h" // PASCAL_DMA_COPY_A +#include "class/clc1b5.h" // PASCAL_DMA_COPY_B +#include "class/clc3b5.h" // VOLTA_DMA_COPY_A +#include "class/clc5b5.h" // TURING_DMA_COPY_A +#include "class/clc6b5.h" // AMPERE_DMA_COPY_A +#include "class/clc7b5.h" // AMPERE_DMA_COPY_B + +#include "class/clc8b5.h" // HOPPER_DMA_COPY_A + +#include "class/clc86f.h" // HOPPER_CHANNEL_GPFIFO_A + +#include "gpu/conf_compute/ccsl.h" + +#include "nvctassert.h" +#include "vgpu/vgpu_guest_pma_scrubber.h" + +#define RM_SUBCHANNEL 0x0 + +#define NV_PUSH_METHOD(OpType, SubCh, Method, Count) \ + (DRF_DEF(906F, _DMA, _SEC_OP, OpType) | \ + DRF_NUM(906F, _DMA, _METHOD_ADDRESS, (Method) >> 2) | \ + DRF_NUM(906F, _DMA, _METHOD_SUBCHANNEL, (SubCh)) | \ + DRF_NUM(906F, _DMA, _METHOD_COUNT, (Count))) + +#define _NV_ASSERT_CONTIGUOUS_METHOD(a1, a2) NV_ASSERT((a2) - (a1) == 4) + +#define NV_PUSH_DATA(Data) MEM_WR32(pPtr++, (Data)) + +#define _NV_PUSH_INC_1U(SubCh, a1, d1, Count) \ + do \ + { \ + NV_PUSH_DATA(NV_PUSH_METHOD(_INC_METHOD, SubCh, a1, Count)); \ + NV_PUSH_DATA(d1); \ + } while (0) + +#define NV_PUSH_INC_1U(SubCh, a1, d1) \ + do \ + { \ + _NV_PUSH_INC_1U (SubCh, a1, d1, 1); \ + } while (0) + +#define NV_PUSH_INC_2U(SubCh, a1, d1, a2, d2) \ + do \ + { \ + _NV_ASSERT_CONTIGUOUS_METHOD(a1, a2); \ + _NV_PUSH_INC_1U(SubCh, a1, d1, 2); \ + NV_PUSH_DATA(d2); \ + } while (0) + +#define NV_PUSH_INC_3U(SubCh, a1, d1, a2, d2, a3, d3) \ + do \ + { \ + _NV_ASSERT_CONTIGUOUS_METHOD(a1, a2); \ + _NV_ASSERT_CONTIGUOUS_METHOD(a2, a3); \ + _NV_PUSH_INC_1U(SubCh, a1, d1, 3); \ + NV_PUSH_DATA(d2); \ + NV_PUSH_DATA(d3); \ + } while (0) + +#define NV_PUSH_INC_4U(SubCh, a1, d1, a2, d2, a3, d3, a4, d4) \ + do \ + { \ + _NV_ASSERT_CONTIGUOUS_METHOD(a1, a2); \ + _NV_ASSERT_CONTIGUOUS_METHOD(a2, a3); \ + _NV_ASSERT_CONTIGUOUS_METHOD(a3, a4); \ + _NV_PUSH_INC_1U(SubCh, a1, d1, 4); \ + NV_PUSH_DATA(d2); \ + NV_PUSH_DATA(d3); \ + NV_PUSH_DATA(d4); \ + } while (0) + +#define READ_CHANNEL_PAYLOAD_SEMA(channel) channelReadChannelMemdesc(channel, channel->finishPayloadOffset) +#define READ_CHANNEL_PB_SEMA(channel) channelReadChannelMemdesc(channel, channel->semaOffset) + +// +// This struct contains parameters needed to send a pushbuffer for a CE +// operation. This interface only supports contiguous operations. +// +typedef struct +{ + NvBool bCeMemcopy; // Whether this is a CE memcopy; + // If set to false, this will be a memset operation + NvU64 dstAddr; // Physical address of the source address + NvU64 srcAddr; // Physical address of the source address; only valid for memcopy + NvU32 size; + NvU32 pattern; // Fixed pattern to memset to. Only valid for memset + NvU32 payload; // Payload value used to release semaphore + NvU64 clientSemaAddr; + NV_ADDRESS_SPACE dstAddressSpace; + NV_ADDRESS_SPACE srcAddressSpace; + NvU32 dstCpuCacheAttrib; + NvU32 srcCpuCacheAttrib; +} CHANNEL_PB_INFO; + +NV_STATUS channelSetupIDs(OBJCHANNEL *pChannel, OBJGPU *pGpu, NvBool bUseVasForCeCopy, NvBool bMIGInUse); +void channelSetupChannelBufferSizes(OBJCHANNEL *pChannel); +NvU32 channelReadChannelMemdesc(OBJCHANNEL *pChannel, NvU32 offset); + +// Needed for pushbuffer management +NV_STATUS channelWaitForFreeEntry(OBJCHANNEL *pChannel, NvU32 *pPutIndex); +NV_STATUS channelFillGpFifo(OBJCHANNEL *pChannel, NvU32 putIndex, NvU32 methodsLength); +NvU32 channelFillCePb(OBJCHANNEL *pChannel, NvU32 putIndex, NvBool bPipelined, + NvBool bInsertFinishPayload, CHANNEL_PB_INFO *pChannelPbInfo); +NvU32 channelFillPbFastScrub(OBJCHANNEL *pChannel, NvU32 putIndex, NvBool bPipelined, + NvBool bInsertFinishPayload, CHANNEL_PB_INFO *pChannelPbInfo); + +NV_STATUS channelFillSec2Pb(OBJCHANNEL *pChannel, NvU32 putIndex, NvBool bInsertFinishPayload, + CHANNEL_PB_INFO *pChannelPbInfo, CCSL_CONTEXT *pCcslCtx, + MEMORY_DESCRIPTOR *pScrubMemDesc, MEMORY_DESCRIPTOR *pSemaMemDesc, + NvU64 scrubMthdAuthTagBufGpuVA, NvU32 scrubAuthTagBufIndex, + NvU64 semaMthdAuthTagBufGpuVA, NvU32 semaAuthTagBufIndex, NvU32* methodLength); + +// Needed for work tracking +NV_STATUS channelWaitForFinishPayload(OBJCHANNEL *pChannel, NvU64 targetPayload); +NvU64 channelGetFinishPayload(OBJCHANNEL *pChannel); + +void channelServiceScrubberInterrupts(OBJCHANNEL *pChannel); + +#endif // _CHANNEL_UTILS_H_ diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/inc/kernel/gpu/mem_mgr/heap_base.h nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/inc/kernel/gpu/mem_mgr/heap_base.h --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/inc/kernel/gpu/mem_mgr/heap_base.h 2023-10-25 20:20:35.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/inc/kernel/gpu/mem_mgr/heap_base.h 2024-03-05 22:12:55.000000000 +0000 @@ -125,7 +125,7 @@ { NvBool bContig; NvU32 pageCount; - NvU32 pageSize; + NvU64 pageSize; NvU32 refCount; NvU64 allocSize; NvU32 flags; diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/inc/kernel/gpu/mem_mgr/mem_scrub.h nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/inc/kernel/gpu/mem_mgr/mem_scrub.h --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/inc/kernel/gpu/mem_mgr/mem_scrub.h 2023-10-25 20:20:35.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/inc/kernel/gpu/mem_mgr/mem_scrub.h 2024-03-05 22:12:56.000000000 +0000 @@ -34,16 +34,19 @@ #include "nvctassert.h" #include "vgpu/vgpu_guest_pma_scrubber.h" +#if !defined(SRT_BUILD) +#include "gpu/mem_mgr/ce_utils.h" +#include "gpu/mem_mgr/sec2_utils.h" +#endif struct OBJGPU; struct Heap; struct OBJCHANNEL; -#define RM_SUBCHANNEL 0x0 #define MEMSET_PATTERN 0x00000000 #define SCRUBBER_NUM_PAYLOAD_SEMAPHORES (2) #define SCRUBBER_SEMAPHORE_SIZE_INBYTES (4) -#define SCRUBBER_CHANNEL_SEMAPHORE_SIZE (SCRUBBER_SEMAPHORE_SIZE_INBYTES *\ +#define SCRUBBER_CHANNEL_SEMAPHORE_SIZE (SCRUBBER_SEMAPHORE_SIZE_INBYTES * \ SCRUBBER_NUM_PAYLOAD_SEMAPHORES) #define SCRUBBER_CHANNEL_NOTIFIER_SIZE (sizeof(NvNotification) * NV_CHANNELGPFIFO_NOTIFICATION_TYPE__SIZE_1) @@ -52,67 +55,6 @@ #define SCRUB_MAX_BYTES_PER_LINE 0xffffffffULL #define MAX_SCRUB_ITEMS 4096 // 4K scrub items -#define READ_SCRUBBER_PAYLOAD_SEMA(channel) MEM_RD32((NvU8*)channel->pbCpuVA +\ - channel->finishPayloadOffset) - -#define READ_SCRUBBER_PB_SEMA(channel) MEM_RD32((NvU8*)channel->pbCpuVA +\ - channel->semaOffset) - -#define WRITE_SCRUBBER_PB_SEMA(channel, val) MEM_WR32((NvU8*)channel->pbCpuVA +\ - channel->semaOffset, val); - -#define WRITE_SCRUBBER_PAYLOAD_SEMA(channel,val) MEM_WR32((NvU8*)channel->pbCpuVA +\ - channel->finishPayloadOffset, val); -// Use Incrementing Methods to save the PB Space -#define _NV_ASSERT_CONTIGUOUS_METHODS(a1, a2) NV_ASSERT((a2) - (a1) == 4) - -#define NV_PUSH_METHOD(OpType, SubCh, Method, Count) \ - (DRF_DEF(906F, _DMA, _SEC_OP, OpType) |\ - DRF_NUM(906F, _DMA, _METHOD_ADDRESS, (Method) >> 2) |\ - DRF_NUM(906F, _DMA, _METHOD_SUBCHANNEL, (SubCh)) |\ - DRF_NUM(906F, _DMA, _METHOD_COUNT, (Count))) - -#define NV_PUSH_DATA(Data) MEM_WR32(pPtr++, (Data)) - -#define _NV_PUSH_INC_1U(SubCh, a1,d1, Count) \ - do{ \ - NV_PUSH_DATA(NV_PUSH_METHOD(_INC_METHOD, SubCh, a1, Count));\ - NV_PUSH_DATA(d1); \ - } while(0) - -#define NV_PUSH_INC_1U(SubCh, a1,d1) \ - do{ \ - _NV_PUSH_INC_1U (SubCh, a1,d1, 1);\ - } while(0) - -#define NV_PUSH_INC_2U(SubCh, a1,d1, a2,d2) \ - do{ \ - _NV_ASSERT_CONTIGUOUS_METHODS(a1, a2);\ - _NV_PUSH_INC_1U(SubCh, a1,d1, 2); \ - NV_PUSH_DATA(d2); \ - } while(0) - -#define NV_PUSH_INC_3U(SubCh, a1,d1, a2,d2, a3,d3) \ - do{ \ - _NV_ASSERT_CONTIGUOUS_METHODS(a1,a2);\ - _NV_ASSERT_CONTIGUOUS_METHODS(a2,a3);\ - _NV_PUSH_INC_1U(SubCh, a1,d1, 3); \ - NV_PUSH_DATA(d2); \ - NV_PUSH_DATA(d3); \ - } while(0) - -#define NV_PUSH_INC_4U(SubCh, a1,d1, a2,d2, a3,d3, a4,d4) \ - do{ \ - _NV_ASSERT_CONTIGUOUS_METHODS(a1,a2);\ - _NV_ASSERT_CONTIGUOUS_METHODS(a2,a3);\ - _NV_ASSERT_CONTIGUOUS_METHODS(a3,a4);\ - _NV_PUSH_INC_1U(SubCh, a1,d1, 4); \ - NV_PUSH_DATA(d2); \ - NV_PUSH_DATA(d3); \ - NV_PUSH_DATA(d4); \ - } while(0) - - // structure to store the details of a scrubbing work typedef struct SCRUB_NODE { // The 64 bit ID assigned to each work @@ -144,8 +86,16 @@ NvLength scrubListSize; // Pre-allocated Free Scrub List PSCRUB_NODE pScrubList; - // Scrubber Channel - struct OBJCHANNEL *pChannel; +#if !defined(SRT_BUILD) + // Scrubber uses ceUtils to manage CE channel + CeUtils *pCeUtils; + + // Scrubber uses sec2Utils to manage SEC2 channel + Sec2Utils *pSec2Utils; +#endif // !defined(SRT_BUILD) + // Engine used for scrubbing + NvU32 engineType; + struct OBJGPU *pGpu; VGPU_GUEST_PMA_SCRUB_BUFFER_RING vgpuScrubBuffRing; NvBool bVgpuScrubberEnabled; diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/inc/kernel/gpu/mem_mgr/mem_utils.h nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/inc/kernel/gpu/mem_mgr/mem_utils.h --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/inc/kernel/gpu/mem_mgr/mem_utils.h 2023-10-25 20:20:35.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/inc/kernel/gpu/mem_mgr/mem_utils.h 2024-03-05 22:12:56.000000000 +0000 @@ -26,12 +26,12 @@ #include "core/prelude.h" -#define CLEAR_HAL_ATTR(a) \ +#define CLEAR_HAL_ATTR(a) \ a = (a &~(DRF_NUM(OS32, _ATTR, _COMPR, 0x3) | \ DRF_NUM(OS32, _ATTR, _TILED, 0x3) | \ DRF_NUM(OS32, _ATTR, _ZCULL, 0x3))); -#define CLEAR_HAL_ATTR2(a) \ +#define CLEAR_HAL_ATTR2(a) \ a = (a & ~(DRF_SHIFTMASK(NVOS32_ATTR2_ZBC) | \ DRF_SHIFTMASK(NVOS32_ATTR2_GPU_CACHEABLE))); diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/inc/kernel/gpu/mem_mgr/phys_mem_allocator/addrtree.h nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/inc/kernel/gpu/mem_mgr/phys_mem_allocator/addrtree.h --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/inc/kernel/gpu/mem_mgr/phys_mem_allocator/addrtree.h 2023-10-25 20:20:35.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/inc/kernel/gpu/mem_mgr/phys_mem_allocator/addrtree.h 1970-01-01 00:00:00.000000000 +0000 @@ -1,227 +0,0 @@ -/* - * SPDX-FileCopyrightText: Copyright (c) 2015-2021 NVIDIA CORPORATION & AFFILIATES. All rights reserved. - * SPDX-License-Identifier: MIT - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER - * DEALINGS IN THE SOFTWARE. - */ - -/*! - * @brief Implement PMA address tree - * - */ - -#ifndef ADDRTREE_H -#define ADDRTREE_H - -#ifdef __cplusplus -extern "C" { -#endif - -#include "map_defines.h" - -// Declare this before its definition because it refers to itself -typedef struct addrtree_node ADDRTREE_NODE; - -struct addrtree_node -{ - NvU32 level; // The level this node belongs to - NvU32 numChildren; // The number of children in the children array - NvU64 frame; // The first frame this node holds - NvU64 state[PMA_BITS_PER_PAGE]; // Tracks the actual state for each map - NvU64 seeChild[PMA_BITS_PER_PAGE]; // Whether this node is partially allocated - // If it is partially allocated, we must go to the children - // to find the correct information. - - ADDRTREE_NODE *parent; // The node's parent - ADDRTREE_NODE *children; // Pointer to an array of children -}; - -typedef struct addrtree_level -{ - NvU64 nodeCount; // Count of total number of nodes on this level - ADDRTREE_NODE *pNodeList; // Pointer to the start of the list of nodes on this level - NvU32 pageSizeShift; // Page size this level is tracking - NvU32 maxFramesPerNode; // The max number of this level frames per node -} ADDRTREE_LEVEL; - -typedef struct pma_addrtree -{ - NvU64 totalFrames; // Total number of 64KB frames being tracked - NvU32 levelCount; // Number of levels in this tree - ADDRTREE_LEVEL *levels; // List of levels in the tree - ADDRTREE_NODE *root; // Start of the node list - NvU64 numPaddingFrames; // Number of 64KB frames needed for padding for alignment - - NvU64 frameEvictionsInProcess; // Count of frame evictions in-process - PMA_STATS *pPmaStats; // Point back to the public struct in PMA structure - NvBool bProtected; // The memory segment tracked by this tree is protected (VPR/CPR) -} PMA_ADDRTREE; - -/*! - * @brief Initializes the addrtree for PMA uses - * - * Allocates the address tree structure for all the pages being managed in this tree. - * Address Tree implementation will use a default configuration for its own level - * structures. - * - * @param[in] numPages The number of pages being managed in this tree - * @param[in] addrBase The base address of this region. Required for addrtree alignment - * @param[in] pPmaStats Pointer to the PMA-wide stats structure - * @param[in] bProtected The tree tracks pages in protected memory - * - * @return PMA_ADDRTREE Pointer to the addrtree if succeeded, NULL otherwise - */ -void *pmaAddrtreeInit(NvU64 numFrames, NvU64 addrBase, PMA_STATS *pPmaStats, NvBool bProtected); - -/*! - * @brief Destroys the addrtree and free the memory - * - * @param[in] pMap The addrtree to destroy - * - * @return void - */ -void pmaAddrtreeDestroy(void *pMap); - -/*! - * @brief Get/set number of evicting frames - * Used for sanity checking in PMA layer as well as performance optimization - * for the map layer to scan faster. - */ -NvU64 pmaAddrtreeGetEvictingFrames(void *pMap); -void pmaAddrtreeSetEvictingFrames(void *pMap, NvU64 frameEvictionsInProcess); - - -/*! - * @brief Scans the addrtree for contiguous space that has the certain status. - * - * @param[in] pMap The addrtree to be scanned - * @param[in] addrBase The base address of this region - * @param[in] rangeStart The start of the restricted range - * @param[in] rangeEnd The end of the restricted range - * @param[in] numPages The number of pages we are scanning for - * @param[out] freeList A list of free frame numbers -- contains only 1 element - * @param[in] pageSize Size of one page - * @param[in] alignment Alignment requested by client - * @param[out] pagesAllocated Number of pages this call allocated - * @param[in] bSkipEvict Whether it's ok to skip the scan for evictable pages - * - * @return NV_OK if succeeded - * @return NV_ERR_IN_USE if found pages that can be evicted - * @return NV_ERR_NO_MEMORY if no available pages could be found - */ -NV_STATUS pmaAddrtreeScanContiguous( - void *pMap, NvU64 addrBase, NvU64 rangeStart, NvU64 rangeEnd, - NvU64 numPages, NvU64 *freelist, NvU32 pageSize, NvU64 alignment, - NvU64 *pagesAllocated, NvBool bSkipEvict, NvBool bReverseAlloc); - -NV_STATUS pmaAddrtreeScanDiscontiguous( - void *pMap, NvU64 addrBase, NvU64 rangeStart, NvU64 rangeEnd, - NvU64 numPages, NvU64 *freelist, NvU32 pageSize, NvU64 alignment, - NvU64 *pagesAllocated, NvBool bSkipEvict, NvBool bReverseAlloc); - -void pmaAddrtreePrintTree(void *pMap, const char* str); - - -/*! - * @brief Changes the state & attrib bits specified by mask - * - * Changes the state of the bits given the physical frame number - * TODO: all four interfaces need to be merged from PMA level so we can remove them! - * - * @param[in] pMap The addrtree to change - * @param[in] frameNum The frame number to change - * @param[in] newState The new state to change to - * @param[in] newStateMask Specific bits to write - * - * @return void - */ -void pmaAddrtreeChangeState(void *pMap, NvU64 frameNum, PMA_PAGESTATUS newState); -void pmaAddrtreeChangeStateAttrib(void *pMap, NvU64 frameNum, PMA_PAGESTATUS newState, NvBool writeAttrib); -void pmaAddrtreeChangeStateAttribEx(void *pMap, NvU64 frameNum, PMA_PAGESTATUS newState,PMA_PAGESTATUS newStateMask); -void pmaAddrtreeChangePageStateAttrib(void * pMap, NvU64 startFrame, NvU32 pageSize, - PMA_PAGESTATUS newState, NvBool writeAttrib); - -/*! - * @brief Read the page state & attrib bits - * - * Read the state of the page given the physical frame number - * - * @param[in] pMap The addrtree to read - * @param[in] frameNum The frame number to read - * @param[in] readAttrib Read attribute bits as well - * - * @return PAGESTATUS of the frame - */ -PMA_PAGESTATUS pmaAddrtreeRead(void *pMap, NvU64 frameNum, NvBool readAttrib); - - -/*! - * @brief Gets the total size of specified PMA managed region. - * - * Gets the total size of current PMA managed region in the FB. - * - * @param[in] pMap Pointer to the addrtree for the region - * @param[in] pBytesTotal Pointer that will return total bytes for current region. - * - */ -void pmaAddrtreeGetSize(void *pMap, NvU64 *pBytesTotal); - - -/*! - * @brief Gets the size of the maximum free chunk of memory in specified region. - * - * Gets the size of the maximum free chunk of memory in the specified PMA managed - * region of the FB. - * - * @param[in] pMap Pointer to the addrtree for the region - * @param[in] pLargestFree Pointer that will return largest free in current region. - * - */ -void pmaAddrtreeGetLargestFree(void *pMap, NvU64 *pLargestFree); - -/*! - * @brief Returns the address range that is completely available for eviction. - * - Should be ALLOC_UNPIN. - * In NUMA, OS manages memory and PMA will only track allocated memory in ALLOC_PIN - * and ALLOC_UNPIN state. FREE memory is managed by OS and cannot be tracked by PMA - * and hence PMA cannot consider FREE memory for eviction and can only consider frames - * in known state to PMA or eviction. ALLOC_PIN cannot be evicted and hence only ALLOC_UNPIN - * can be evictable. - * - * - * @param[in] pMap Pointer to the regmap for the region - * @param[in] addrBase Base address of the region - * @param[in] actualSize Size of the eviction range - * @param[in] pageSize Pagesize - * @param[out] evictStart Starting address of the eviction range - * @param[out] evictEnd End address of the eviction range. - * - * Returns: - * - NV_OK If there is evictable range of given size : actualSize - * - * - NV_ERR_NO_MEMORY if no contiguous range is evictable. - */ -NV_STATUS pmaAddrtreeScanContiguousNumaEviction(void *pMap, NvU64 addrBase, - NvLength actualSize, NvU64 pageSize, NvU64 *evictStart, NvU64 *evictEnd); - -#ifdef __cplusplus -} -#endif - -#endif // ADDRTREE_H diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/inc/kernel/gpu/mem_mgr/phys_mem_allocator/map_defines.h nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/inc/kernel/gpu/mem_mgr/phys_mem_allocator/map_defines.h --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/inc/kernel/gpu/mem_mgr/phys_mem_allocator/map_defines.h 2023-10-25 20:20:35.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/inc/kernel/gpu/mem_mgr/phys_mem_allocator/map_defines.h 2024-03-05 22:12:56.000000000 +0000 @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 2015-2021 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2015-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -22,7 +22,7 @@ */ /*! - * @brief Contains common defines between addrtree and regmap + * @brief Contains common defines for regmap */ #ifndef MAP_DEFINES_H @@ -90,7 +90,7 @@ #define ATTRIB_PERSISTENT NVBIT(MAP_IDX_PERSISTENT) #define ATTRIB_NUMA_REUSE NVBIT(MAP_IDX_NUMA_REUSE) #define ATTRIB_BLACKLIST NVBIT(MAP_IDX_BLACKLIST) -#define ATTRIB_MASK (ATTRIB_EVICTING | ATTRIB_SCRUBBING \ +#define ATTRIB_MASK (ATTRIB_EVICTING | ATTRIB_SCRUBBING \ | ATTRIB_PERSISTENT | ATTRIB_NUMA_REUSE \ | ATTRIB_BLACKLIST) @@ -114,6 +114,9 @@ NvU64 numFreeFrames; // PMA-wide free 64KB frame count NvU64 numFree2mbPages; // PMA-wide free 2MB pages count #if !defined(NVWATCH) + NvU64 num2mbPagesProtected; // PMA-wide total number of 2MB pages in protected memory + NvU64 numFreeFramesProtected; // PMA-wide free 64KB frame count in protected memory + NvU64 numFree2mbPagesProtected; // PMA-wide free 2MB pages count in protected memory #endif // !defined(NVWATCH) } PMA_STATS; diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/inc/kernel/gpu/mem_mgr/phys_mem_allocator/numa.h nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/inc/kernel/gpu/mem_mgr/phys_mem_allocator/numa.h --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/inc/kernel/gpu/mem_mgr/phys_mem_allocator/numa.h 2023-10-25 20:20:35.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/inc/kernel/gpu/mem_mgr/phys_mem_allocator/numa.h 2024-03-05 22:12:56.000000000 +0000 @@ -59,7 +59,7 @@ * is used for allocations coming from the Linux kernel. * The perf implication is under further study. See bug #1999793. */ -NV_STATUS pmaNumaAllocate(PMA *pPma, NvLength allocationCount, NvU32 pageSize, +NV_STATUS pmaNumaAllocate(PMA *pPma, NvLength allocationCount, NvU64 pageSize, PMA_ALLOCATION_OPTIONS *allocationOptions, NvU64 *pPages); /*! diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/inc/kernel/gpu/mem_mgr/phys_mem_allocator/phys_mem_allocator.h nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/inc/kernel/gpu/mem_mgr/phys_mem_allocator/phys_mem_allocator.h --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/inc/kernel/gpu/mem_mgr/phys_mem_allocator/phys_mem_allocator.h 2023-10-25 20:20:35.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/inc/kernel/gpu/mem_mgr/phys_mem_allocator/phys_mem_allocator.h 2024-03-05 22:12:56.000000000 +0000 @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 2015-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2015-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -42,7 +42,6 @@ #include "nvport/nvport.h" #include "regmap.h" -#include "addrtree.h" #include "nvmisc.h" #if defined(SRT_BUILD) @@ -72,7 +71,8 @@ #define PMA_INIT_NUMA NVBIT(2) #define PMA_INIT_INTERNAL NVBIT(3) // Used after heap is removed #define PMA_INIT_FORCE_PERSISTENCE NVBIT(4) -#define PMA_INIT_ADDRTREE NVBIT(5) +// unused +#define PMA_INIT_NUMA_AUTO_ONLINE NVBIT(6) // These flags are used for querying PMA's config and/or state. #define PMA_QUERY_SCRUB_ENABLED NVBIT(0) @@ -166,7 +166,7 @@ /*! * @brief Callbacks to UVM for eviction */ -typedef NV_STATUS (*pmaEvictPagesCb_t)(void *ctxPtr, NvU32 pageSize, NvU64 *pPages, +typedef NV_STATUS (*pmaEvictPagesCb_t)(void *ctxPtr, NvU64 pageSize, NvU64 *pPages, NvU32 count, NvU64 physBegin, NvU64 physEnd, MEMORY_PROTECTION prot); typedef NV_STATUS (*pmaEvictRangeCb_t)(void *ctxPtr, NvU64 physBegin, NvU64 physEnd, @@ -177,16 +177,15 @@ */ typedef void *(*pmaMapInit_t)(NvU64 numFrames, NvU64 addrBase, PMA_STATS *pPmaStats, NvBool bProtected); typedef void (*pmaMapDestroy_t)(void *pMap); -typedef void (*pmaMapChangeState_t)(void *pMap, NvU64 frameNum, PMA_PAGESTATUS newState); -typedef void (*pmaMapChangeStateAttrib_t)(void *pMap, NvU64 frameNum, PMA_PAGESTATUS newState, NvBool writeAttrib); typedef void (*pmaMapChangeStateAttribEx_t)(void *pMap, NvU64 frameNum, PMA_PAGESTATUS newState, PMA_PAGESTATUS newStateMask); -typedef void (*pmaMapChangePageStateAttrib_t)(void *pMap, NvU64 startFrame, NvU32 pageSize, PMA_PAGESTATUS newState, NvBool writeAttrib); +typedef void (*pmaMapChangePageStateAttribEx_t)(void *pMap, NvU64 startFrame, NvU64 pageSize, PMA_PAGESTATUS newState, PMA_PAGESTATUS newStateMask); +typedef void (*pmaMapChangeBlockStateAttrib_t)(void *pMap, NvU64 frameNum, NvU64 numFrames, PMA_PAGESTATUS newState, PMA_PAGESTATUS newStateMask); typedef PMA_PAGESTATUS (*pmaMapRead_t)(void *pMap, NvU64 frameNum, NvBool readAttrib); typedef NV_STATUS (*pmaMapScanContiguous_t)(void *pMap, NvU64 addrBase, NvU64 rangeStart, NvU64 rangeEnd, - NvU64 numPages, NvU64 *freelist, NvU32 pageSize, NvU64 alignment, + NvU64 numPages, NvU64 *freelist, NvU64 pageSize, NvU64 alignment, NvU64 *pagesAllocated, NvBool bSkipEvict, NvBool bReverseAlloc); typedef NV_STATUS (*pmaMapScanDiscontiguous_t)(void *pMap, NvU64 addrBase, NvU64 rangeStart, NvU64 rangeEnd, - NvU64 numPages, NvU64 *freelist, NvU32 pageSize, NvU64 alignment, + NvU64 numPages, NvU64 *freelist, NvU64 pageSize, NvU64 alignment, NvU64 *pagesAllocated, NvBool bSkipEvict, NvBool bReverseAlloc); typedef void (*pmaMapGetSize_t)(void *pMap, NvU64 *pBytesTotal); typedef void (*pmaMapGetLargestFree_t)(void *pMap, NvU64 *pLargestFree); @@ -200,10 +199,9 @@ NvU32 mode; pmaMapInit_t pmaMapInit; pmaMapDestroy_t pmaMapDestroy; - pmaMapChangeState_t pmaMapChangeState; - pmaMapChangeStateAttrib_t pmaMapChangeStateAttrib; pmaMapChangeStateAttribEx_t pmaMapChangeStateAttribEx; - pmaMapChangePageStateAttrib_t pmaMapChangePageStateAttrib; + pmaMapChangePageStateAttribEx_t pmaMapChangePageStateAttribEx; + pmaMapChangeBlockStateAttrib_t pmaMapChangeBlockStateAttrib; pmaMapRead_t pmaMapRead; pmaMapScanContiguous_t pmaMapScanContiguous; pmaMapScanDiscontiguous_t pmaMapScanDiscontiguous; @@ -251,6 +249,7 @@ NvU64 coherentCpuFbBase; // Used to calculate FB offset from bus address NvU64 coherentCpuFbSize; // Used for error checking only NvU32 numaReclaimSkipThreshold; // percent value below which __GFP_RECLAIM will not be used. + NvBool bNumaAutoOnline; // If NUMA memory is auto-onlined // Blacklist related states PMA_BLACKLIST_CHUNK *pBlacklistChunks; // Tracking for blacklist pages @@ -433,12 +432,12 @@ * code,because it is not very informative. * */ -NV_STATUS pmaAllocatePages(PMA *pPma, NvLength pageCount, NvU32 pageSize, +NV_STATUS pmaAllocatePages(PMA *pPma, NvLength pageCount, NvU64 pageSize, PMA_ALLOCATION_OPTIONS *pAllocationOptions, NvU64 *pPages); // allocate on multiple GPU, thus pmaCount NV_STATUS pmaAllocatePagesBroadcast(PMA **pPma, NvU32 pmaCount, NvLength allocationCount, - NvU32 pageSize, PMA_ALLOCATION_OPTIONS *pAllocationOptions, NvU64 *pPages); + NvU64 pageSize, PMA_ALLOCATION_OPTIONS *pAllocationOptions, NvU64 *pPages); /*! @@ -472,7 +471,7 @@ * TODO some error for rollback * */ -NV_STATUS pmaPinPages(PMA *pPma, NvU64 *pPages, NvLength pageCount, NvU32 pageSize); +NV_STATUS pmaPinPages(PMA *pPma, NvU64 *pPages, NvLength pageCount, NvU64 pageSize); /*! @@ -498,7 +497,7 @@ * TODO some error for rollback * */ -NV_STATUS pmaUnpinPages(PMA *pPma, NvU64 *pPages, NvLength pageCount, NvU32 pageSize); +NV_STATUS pmaUnpinPages(PMA *pPma, NvU64 *pPages, NvLength pageCount, NvU64 pageSize); /*! @@ -815,7 +814,7 @@ * @return * void */ -void pmaGetClientBlacklistedPages(PMA *pPma, NvU64 *pChunks, NvU32 *pPageSize, NvU32 *pNumChunks); +void pmaGetClientBlacklistedPages(PMA *pPma, NvU64 *pChunks, NvU64 *pPageSize, NvU32 *pNumChunks); /*! * @brief Returns the PMA blacklist size in bytes for @@ -865,6 +864,54 @@ */ NV_STATUS pmaAddToBlacklistTracking(PMA *pPma, NvU64 physBase); +/*! + * @brief Returns total protected video memory. + * + * @param[in] pPma PMA pointer + * @param[in] pBytesTotal Pointer that will return the total FB memory size. + * + * @return + * void + */ +void pmaGetTotalProtectedMemory(PMA *pPma, NvU64 *pBytesTotal); + +/*! + * @brief Returns total unprotected video memory. + * + * @param[in] pPma PMA pointer + * @param[in] pBytesTotal Pointer that will return the total FB memory size. + * + * @return + * void + */ +void pmaGetTotalUnprotectedMemory(PMA *pPma, NvU64 *pBytesTotal); + +/*! + * @brief Returns information about the total free protected FB memory. + * In confidential compute use cases, memory will be split into + * protected and unprotected regions + * + * @param[in] pPma PMA pointer + * @param[in] pBytesFree Pointer that will return the free protected memory size. + * + * @return + * void + */ +void pmaGetFreeProtectedMemory(PMA *pPma, NvU64 *pBytesFree); + +/*! + * @brief Returns information about the total free unprotected FB memory. + * In confidential compute use cases, memory will be split into + * protected and unprotected regions + * + * @param[in] pPma PMA pointer + * @param[in] pBytesFree Pointer that will return the free unprotected memory size. + * + * @return + * void + */ +void pmaGetFreeUnprotectedMemory(PMA *pPma, NvU64 *pBytesFree); + #ifdef __cplusplus } #endif diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/inc/kernel/gpu/mem_mgr/phys_mem_allocator/phys_mem_allocator_util.h nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/inc/kernel/gpu/mem_mgr/phys_mem_allocator/phys_mem_allocator_util.h --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/inc/kernel/gpu/mem_mgr/phys_mem_allocator/phys_mem_allocator_util.h 2023-10-25 20:20:35.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/inc/kernel/gpu/mem_mgr/phys_mem_allocator/phys_mem_allocator_util.h 2024-03-05 22:12:56.000000000 +0000 @@ -45,11 +45,11 @@ NV_STATUS _pmaEvictContiguous(PMA *pPma, void *pMap, NvU64 evictStart, NvU64 evictEnd, MEMORY_PROTECTION prot); NV_STATUS _pmaEvictPages(PMA *pPma, void *pMap, NvU64 *evictPages, NvU64 evictPageCount, - NvU64 *allocPages, NvU64 allocPageCount, NvU32 pageSize, + NvU64 *allocPages, NvU64 allocPageCount, NvU64 pageSize, NvU64 physBegin, NvU64 physEnd, MEMORY_PROTECTION prot); void _pmaClearScrubBit(PMA *pPma, SCRUB_NODE *pPmaScrubList, NvU64 count); NV_STATUS _pmaCheckScrubbedPages(PMA *pPma, NvU64 chunkSize, NvU64 *pPages, NvU32 pageCount); -NV_STATUS _pmaPredictOutOfMemory(PMA *pPma, NvLength allocationCount, NvU32 pageSize, +NV_STATUS _pmaPredictOutOfMemory(PMA *pPma, NvLength allocationCount, NvU64 pageSize, PMA_ALLOCATION_OPTIONS *allocationOptions); NV_STATUS pmaSelector(PMA *pPma, PMA_ALLOCATION_OPTIONS *allocationOptions, NvS32 *regionList); void _pmaReallocBlacklistPages (PMA *pPma, NvU32 regId, NvU64 rangeBegin, NvU64 rangeSize); diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/inc/kernel/gpu/mem_mgr/phys_mem_allocator/regmap.h nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/inc/kernel/gpu/mem_mgr/phys_mem_allocator/regmap.h --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/inc/kernel/gpu/mem_mgr/phys_mem_allocator/regmap.h 2023-10-25 20:20:35.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/inc/kernel/gpu/mem_mgr/phys_mem_allocator/regmap.h 2024-03-05 22:12:56.000000000 +0000 @@ -90,34 +90,6 @@ void pmaRegmapSetEvictingFrames(void *pMap, NvU64 frameEvictionsInProcess); /*! - * @brief Changes the recorded state bits - * - * Changes the state of the bits given the physical frame number - * - * @param[in] pMap The regmap to change - * @param[in] frameNum The frame number to change - * @param[in] newState The new state to change to - * - * @return void - */ -void pmaRegmapChangeState(void *pMap, NvU64 frameNum, PMA_PAGESTATUS newState); - -/*! - * @brief Changes the recorded state & attrib bits - * - * Changes the state of the bits given the physical frame number - * - * @param[in] pMap The regmap to change - * @param[in] frameNum The frame number to change - * @param[in] newState The new state to change to - * @param[in] writeAttrib Write attribute bits as well - * - * @return void - */ -void pmaRegmapChangeStateAttrib(void *pMap, NvU64 frameNum, - PMA_PAGESTATUS newState, NvBool writeAttrib); - -/*! * @brief Changes the recorded state & attrib bits for an entire page * * Changes the state of the bits for an entire page given the physical @@ -131,8 +103,8 @@ * * @return void */ -void pmaRegmapChangePageStateAttrib(void * pMap, NvU64 frameNumStart, NvU32 pageSize, - PMA_PAGESTATUS newState, NvBool writeAttrib); +void pmaRegmapChangePageStateAttribEx(void * pMap, NvU64 frameNumStart, NvU64 pageSize, + PMA_PAGESTATUS newState, PMA_PAGESTATUS newStateMask); /*! * @brief Changes the state & attrib bits specified by mask @@ -151,6 +123,25 @@ PMA_PAGESTATUS newStateMask); /*! + * @brief Changes the state & attrib bits specified by mask + * + * Changes the state of the bits given the physical frame number + * and the number of frames to change + * + * @param[in] pMap The regmap to change + * @param[in] frameNum The frame number to change + * @param[in] numFrames The number of frames to change + * @param[in] newState The new state to change to + * @param[in] newStateMask Specific bits to write + * + * @return void + */ +void pmaRegmapChangeBlockStateAttrib(void *pMap, NvU64 frameNum, + NvU64 numFrames, + PMA_PAGESTATUS newState, + PMA_PAGESTATUS newStateMask); + +/*! * @brief Read the page state & attrib bits * * Read the state of the page given the physical frame number @@ -188,7 +179,7 @@ */ NV_STATUS pmaRegmapScanContiguous( void *pMap, NvU64 addrBase, NvU64 rangeStart, NvU64 rangeEnd, - NvU64 numPages, NvU64 *freelist, NvU32 pageSize, NvU64 alignment, + NvU64 numPages, NvU64 *freelist, NvU64 pageSize, NvU64 alignment, NvU64 *pagesAllocated, NvBool bSkipEvict, NvBool bReverseAlloc); /*! @@ -215,7 +206,7 @@ */ NV_STATUS pmaRegmapScanDiscontiguous( void *pMap, NvU64 addrBase, NvU64 rangeStart, NvU64 rangeEnd, - NvU64 numPages, NvU64 *freelist, NvU32 pageSize, NvU64 alignment, + NvU64 numPages, NvU64 *freelist, NvU64 pageSize, NvU64 alignment, NvU64 *pagesAllocated, NvBool bSkipEvict, NvBool bReverseAlloc); /*! diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/inc/kernel/gpu/mem_mgr/rm_page_size.h nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/inc/kernel/gpu/mem_mgr/rm_page_size.h --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/inc/kernel/gpu/mem_mgr/rm_page_size.h 1970-01-01 00:00:00.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/inc/kernel/gpu/mem_mgr/rm_page_size.h 2024-03-05 22:12:56.000000000 +0000 @@ -0,0 +1,80 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 1993-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef RM_PAGE_SIZE_H +#define RM_PAGE_SIZE_H + + + +//--------------------------------------------------------------------------- +// +// Memory page defines. +// +// These correspond to the granularity understood by the hardware +// for address mapping; the system page size can be larger. +// +//--------------------------------------------------------------------------- +#define RM_PAGE_SIZE_INVALID 0 +#define RM_PAGE_SIZE 4096 +#define RM_PAGE_SIZE_64K (64 * 1024) +#define RM_PAGE_SIZE_128K (128 * 1024) +#define RM_PAGE_MASK 0x0FFF +#define RM_PAGE_SHIFT 12 +#define RM_PAGE_SHIFT_64K 16 +#define RM_PAGE_SHIFT_128K 17 +#define RM_PAGE_SHIFT_2M 21 +#define RM_PAGE_SIZE_2M (1 << RM_PAGE_SHIFT_2M) + +// Huge page size is 2 MB +#define RM_PAGE_SHIFT_HUGE RM_PAGE_SHIFT_2M +#define RM_PAGE_SIZE_HUGE (1ULL << RM_PAGE_SHIFT_HUGE) +#define RM_PAGE_MASK_HUGE ((1ULL << RM_PAGE_SHIFT_HUGE) - 1) + +// 512MB page size +#define RM_PAGE_SHIFT_512M 29 +#define RM_PAGE_SIZE_512M (1ULL << RM_PAGE_SHIFT_512M) +#define RM_PAGE_MASK_512M (RM_PAGE_SIZE_512M - 1) + +//--------------------------------------------------------------------------- +// +// Memory page attributes. +// +// These attributes are used by software for page size mapping; +// Big pages can be of 64/128KB[Fermi/Kepler/Pascal] +// Huge page is 2 MB[Pascal+] +// 512MB page is Ampere+ +// Default page attribute lets driver decide the optimal page size +// +//--------------------------------------------------------------------------- +typedef enum +{ + RM_ATTR_PAGE_SIZE_DEFAULT, + RM_ATTR_PAGE_SIZE_4KB, + RM_ATTR_PAGE_SIZE_BIG, + RM_ATTR_PAGE_SIZE_HUGE, + RM_ATTR_PAGE_SIZE_512MB, + RM_ATTR_PAGE_SIZE_INVALID +} +RM_ATTR_PAGE_SIZE; + +#endif // RM_PAGE_SIZE_H diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/inc/kernel/gpu/mem_mgr/sec2_utils.h nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/inc/kernel/gpu/mem_mgr/sec2_utils.h --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/inc/kernel/gpu/mem_mgr/sec2_utils.h 1970-01-01 00:00:00.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/inc/kernel/gpu/mem_mgr/sec2_utils.h 2024-03-05 22:12:56.000000000 +0000 @@ -0,0 +1,112 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#include "g_sec2_utils_nvoc.h" + +#ifndef SEC2_UTILS_H +#define SEC2_UTILS_H + +#include "gpu/gpu_resource.h" // GpuResource + +#include "kernel/gpu/mem_mgr/channel_utils.h" + +#include "kernel/gpu/conf_compute/ccsl_context.h" + +#define SEC2_AUTH_TAG_BUF_SIZE_BYTES (16) +#define SHA_256_HASH_SIZE_BYTES (32) + +typedef struct +{ + MEMORY_DESCRIPTOR *pMemDesc; + NvU64 offset; + NvU64 length; + NvU64 submittedWorkId; +} SEC2UTILS_MEMSET_PARAMS; + +typedef struct +{ + NvHandle hPhysMem; + NvHandle hVirtMem; + NvHandle hVASpace; + NvU64 gpuVA; + NvU64 size; + MEMORY_DESCRIPTOR *pMemDesc; +} SEC2UTILS_BUFFER_INFO; + +NVOC_PREFIX(sec2utils) class Sec2Utils : Object +{ +public: + NV_STATUS sec2utilsConstruct(Sec2Utils *psec2utils, OBJGPU *pGpu, KERNEL_MIG_GPU_INSTANCE *pKernelMIGGPUInstance); + + void sec2utilsDestruct(Sec2Utils *psec2utils); + + NV_STATUS sec2utilsMemset(Sec2Utils *psec2utils, SEC2UTILS_MEMSET_PARAMS *pParams); + + NvU64 sec2utilsUpdateProgress(Sec2Utils *psec2utils); + void sec2utilsServiceInterrupts(Sec2Utils *psec2utils); + + // + // Internal states + // + + NvHandle hClient; + NvHandle hDevice; + NvHandle hSubdevice; + + OBJCHANNEL *pChannel; + OBJGPU *pGpu; + + NvU32 sec2Class; + NvU64 lastSubmittedPayload; + NvU64 lastCompletedPayload; + + CCSL_CONTEXT *pCcslCtx; + + // + // 4K page consisting of 128 auth tag buffers. + // One buffer is used per sec2 method stream. + // RM scrubber can submit multiple scrub method streams per sec2 operation. + // + SEC2UTILS_BUFFER_INFO scrubMthdAuthTagBuf; + + // + // 4K page consisting of 128 auth tag buffers. + // One buffer is used per scrubber operation (not per sec2 scrub method stream). + // One scrub op corresponds to one call to sec2UtilsMemSet + // + SEC2UTILS_BUFFER_INFO semaMthdAuthTagBuf; + + // + // Updated by RM to point to current auth tag buffer index (0-127) + // so its incremented for every scrub method stream. + // + NvU32 authTagPutIndex; + + // + // Updated by SEC2 engine to point to last used/ last "seen" auth tag buffer index. + // This is updated based on completion of every scrub method stream. + // + NvU32 authTagGetIndex; +}; + +#endif // SEC2_UTILS_H diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/inc/kernel/gpu/mem_mgr/sem_surf.h nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/inc/kernel/gpu/mem_mgr/sem_surf.h --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/inc/kernel/gpu/mem_mgr/sem_surf.h 1970-01-01 00:00:00.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/inc/kernel/gpu/mem_mgr/sem_surf.h 2024-03-05 22:11:36.000000000 +0000 @@ -0,0 +1,3 @@ + +#include "g_sem_surf_nvoc.h" + diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/inc/kernel/gpu/mem_mgr/virt_mem_allocator_common.h nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/inc/kernel/gpu/mem_mgr/virt_mem_allocator_common.h --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/inc/kernel/gpu/mem_mgr/virt_mem_allocator_common.h 2023-10-25 20:20:35.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/inc/kernel/gpu/mem_mgr/virt_mem_allocator_common.h 2024-03-05 22:12:56.000000000 +0000 @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 1993-2021 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 1993-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -33,59 +33,14 @@ #include "nvtypes.h" #include "nvgputypes.h" #include "nvstatus.h" +#include "resserv/rs_client.h" +#include "gpu/mem_mgr/rm_page_size.h" typedef struct OBJGPU OBJGPU; typedef struct ChannelDescendant ChannelDescendant; typedef struct ContextDma ContextDma; typedef struct Memory Memory; typedef struct EVENTNOTIFICATION EVENTNOTIFICATION; -//--------------------------------------------------------------------------- -// -// Memory page defines. -// -// These correspond to the granularity understood by the hardware -// for address mapping; the system page size can be larger. -// -//--------------------------------------------------------------------------- -#define RM_PAGE_SIZE 4096 -#define RM_PAGE_SIZE_64K (64 * 1024) -#define RM_PAGE_SIZE_128K (128 * 1024) -#define RM_PAGE_MASK 0x0FFF -#define RM_PAGE_SHIFT 12 -#define RM_PAGE_SHIFT_64K 16 -#define RM_PAGE_SHIFT_128K 17 - -// Huge page size is 2 MB -#define RM_PAGE_SHIFT_HUGE 21 -#define RM_PAGE_SIZE_HUGE (1 << RM_PAGE_SHIFT_HUGE) -#define RM_PAGE_MASK_HUGE ((1 << RM_PAGE_SHIFT_HUGE) - 1) - -// 512MB page size -#define RM_PAGE_SHIFT_512M 29 -#define RM_PAGE_SIZE_512M (1 << RM_PAGE_SHIFT_512M) -#define RM_PAGE_MASK_512M (RM_PAGE_SIZE_512M - 1) - -//--------------------------------------------------------------------------- -// -// Memory page attributes. -// -// These attributes are used by software for page size mapping; -// Big pages can be of 64/128KB[Fermi/Kepler/Pascal] -// Huge page is 2 MB[Pascal+] -// 512MB page is Ampere+ -// Default page attribute lets driver decide the optimal page size -// -//--------------------------------------------------------------------------- -typedef enum -{ - RM_ATTR_PAGE_SIZE_DEFAULT = 0x0, - RM_ATTR_PAGE_SIZE_4KB = 0x1, - RM_ATTR_PAGE_SIZE_BIG = 0x2, - RM_ATTR_PAGE_SIZE_HUGE = 0x3, - RM_ATTR_PAGE_SIZE_512MB = 0x4, - RM_ATTR_PAGE_SIZE_INVALID = 0x5 -} -RM_ATTR_PAGE_SIZE; //--------------------------------------------------------------------------- // @@ -132,8 +87,8 @@ NV_STATUS CompletionStatus, NvBool TimeSupplied, NvU64 Time); -NV_STATUS notifyFillNotifierGPUVA (OBJGPU*, NvHandle, NvHandle, NvU64, NvV32, NvV16, NV_STATUS, NvU32); -NV_STATUS notifyFillNotifierGPUVATimestamp (OBJGPU*, NvHandle, NvHandle, NvU64, NvV32, NvV16, NV_STATUS, NvU32, NvU64); +NV_STATUS notifyFillNotifierGPUVA (OBJGPU*, RsClient*, NvHandle, NvU64, NvV32, NvV16, NV_STATUS, NvU32); +NV_STATUS notifyFillNotifierGPUVATimestamp (OBJGPU*, RsClient*, NvHandle, NvU64, NvV32, NvV16, NV_STATUS, NvU32, NvU64); NV_STATUS notifyFillNotifierMemory (OBJGPU*, Memory *, NvV32, NvV16, NV_STATUS, NvU32); NV_STATUS notifyFillNotifierMemoryTimestamp(OBJGPU*, Memory *, NvV32, NvV16, NV_STATUS, NvU32, NvU64); void notifyFillNvNotification(OBJGPU *pGpu, @@ -144,8 +99,8 @@ NvBool TimeSupplied, NvU64 Time); -NV_STATUS semaphoreFillGPUVA (OBJGPU*, NvHandle, NvHandle, NvU64, NvV32, NvV32, NvBool); -NV_STATUS semaphoreFillGPUVATimestamp(OBJGPU*, NvHandle, NvHandle, NvU64, NvV32, NvV32, NvBool, NvU64); +NV_STATUS semaphoreFillGPUVA (OBJGPU*, RsClient*, NvHandle, NvU64, NvV32, NvV32, NvBool); +NV_STATUS semaphoreFillGPUVATimestamp(OBJGPU*, RsClient*, NvHandle, NvU64, NvV32, NvV32, NvBool, NvU64); RM_ATTR_PAGE_SIZE dmaNvos32ToPageSizeAttr(NvU32 attr, NvU32 attr2); diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/inc/kernel/gpu/mmu/vidmem_access_bit_buffer.h nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/inc/kernel/gpu/mmu/vidmem_access_bit_buffer.h --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/inc/kernel/gpu/mmu/vidmem_access_bit_buffer.h 1970-01-01 00:00:00.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/inc/kernel/gpu/mmu/vidmem_access_bit_buffer.h 2024-03-05 22:11:41.000000000 +0000 @@ -0,0 +1,3 @@ + +#include "g_vidmem_access_bit_buffer_nvoc.h" + diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/inc/kernel/gpu/perf/kern_perf_boost.h nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/inc/kernel/gpu/perf/kern_perf_boost.h --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/inc/kernel/gpu/perf/kern_perf_boost.h 2023-10-25 20:20:36.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/inc/kernel/gpu/perf/kern_perf_boost.h 2024-03-05 22:12:57.000000000 +0000 @@ -67,7 +67,7 @@ NvU32 flags; /*! - * Specifies number of clients who requested + * Specifies number of clients who requested * CUDA boost. This is used only in case of the CUDA clients. */ NvU32 refCount; diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/inc/kernel/gpu/perf/kern_perf_gpuboostsync.h nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/inc/kernel/gpu/perf/kern_perf_gpuboostsync.h --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/inc/kernel/gpu/perf/kern_perf_gpuboostsync.h 2023-10-25 20:20:36.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/inc/kernel/gpu/perf/kern_perf_gpuboostsync.h 2024-03-05 22:12:58.000000000 +0000 @@ -50,7 +50,7 @@ */ NvBool bHystersisEnable; - /*! + /*! * SLI GPU Boost feature is enabled. */ NvBool bSliGpuBoostSyncEnable; diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/inc/kernel/gpu/rc/kernel_rc_watchdog_private.h nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/inc/kernel/gpu/rc/kernel_rc_watchdog_private.h --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/inc/kernel/gpu/rc/kernel_rc_watchdog_private.h 2023-10-25 20:20:36.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/inc/kernel/gpu/rc/kernel_rc_watchdog_private.h 2024-03-05 22:12:58.000000000 +0000 @@ -79,6 +79,7 @@ NvNotification *notifiers[NV_MAX_SUBDEVICES]; NvNotification *errorContext; NvNotification *notifierToken; + NvBool bHandleValid; } KernelWatchdog; diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/inc/kernel/gpu/sec2/sec2_context.h nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/inc/kernel/gpu/sec2/sec2_context.h --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/inc/kernel/gpu/sec2/sec2_context.h 1970-01-01 00:00:00.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/inc/kernel/gpu/sec2/sec2_context.h 2024-03-05 22:11:36.000000000 +0000 @@ -0,0 +1,3 @@ + +#include "g_sec2_context_nvoc.h" + diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/inc/kernel/gpu/spdm/libspdm_includes.h nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/inc/kernel/gpu/spdm/libspdm_includes.h --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/inc/kernel/gpu/spdm/libspdm_includes.h 1970-01-01 00:00:00.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/inc/kernel/gpu/spdm/libspdm_includes.h 2024-03-05 22:12:58.000000000 +0000 @@ -0,0 +1,74 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2021-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef LIBSPDM_INCLUDES_H +#define LIBSPDM_INCLUDES_H + +// +// Dedicated header file to centralize all libspdm-related includes and defines. +// This allows us to minimize the amount of headers (and sources) that have direct +// libspdm dependency, and allowing shared macros & types for dependent source. +// + +/* ------------------------ Includes --------------------------------------- */ +#include "internal/libspdm_common_lib.h" +#include "internal/libspdm_secured_message_lib.h" +#include "library/spdm_requester_lib.h" + +/* ------------------------ Macros and Defines ----------------------------- */ +// +// As libspdm has its own RETURN_STATUS define, we need to ensure we do not +// accidentally compare it against NV_STATUS. Use macro for consistent libspdm +// error handling. +// +#define CHECK_SPDM_STATUS(expr) do { \ + libspdm_return_t __spdmStatus; \ + __spdmStatus = (expr); \ + if (LIBSPDM_STATUS_IS_ERROR(__spdmStatus)) \ + { \ + NV_PRINTF(LEVEL_ERROR, "SPDM failed with status 0x%0x\n", \ + __spdmStatus); \ + status = NV_ERR_GENERIC; \ + goto ErrorExit; \ + } \ + } while (NV_FALSE) + +// Check for any critical issues caused by data size mismatches. +ct_assert(sizeof(NvU8) == sizeof(uint8_t)); +ct_assert(sizeof(NvU16) == sizeof(uint16_t)); +ct_assert(sizeof(NvU32) == sizeof(uint32_t)); +ct_assert(sizeof(NvU64) == sizeof(uint64_t)); + +typedef struct _SPDM_ALGO_CHECK_ENTRY +{ + libspdm_data_type_t dataType; + uint32_t expectedAlgo; +} SPDM_ALGO_CHECK_ENTRY, *PSPDM_ALGO_CHECK_ENTRY; + +// +// Check for assert in libspdm code, indicating a fatal condition. +// Returns false if assert was hit. +// +bool nvspdm_check_and_clear_libspdm_assert(void); + +#endif // LIBSPDM_INCLUDES_H diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/inc/kernel/gpu/spdm/spdm.h nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/inc/kernel/gpu/spdm/spdm.h --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/inc/kernel/gpu/spdm/spdm.h 1970-01-01 00:00:00.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/inc/kernel/gpu/spdm/spdm.h 2024-03-05 22:11:36.000000000 +0000 @@ -0,0 +1,3 @@ + +#include "g_spdm_nvoc.h" + diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/inc/kernel/gpu/subdevice/subdevice_ctrl_rc.h nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/inc/kernel/gpu/subdevice/subdevice_ctrl_rc.h --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/inc/kernel/gpu/subdevice/subdevice_ctrl_rc.h 2023-10-25 20:20:36.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/inc/kernel/gpu/subdevice/subdevice_ctrl_rc.h 2024-03-05 22:12:58.000000000 +0000 @@ -51,24 +51,24 @@ NV_STATUS subdeviceCtrlCmdRcSetCleanErrorHistory(Subdevice *pSubdevice); RMCTRL_EXPORT(NV2080_CTRL_CMD_RC_GET_WATCHDOG_INFO, - RMCTRL_FLAGS(NON_PRIVILEGED)) + RMCTRL_FLAGS(NON_PRIVILEGED, GPU_LOCK_DEVICE_ONLY, API_LOCK_READONLY)) NV_STATUS subdeviceCtrlCmdRcGetWatchdogInfo(Subdevice *pSubdevice, NV2080_CTRL_RC_GET_WATCHDOG_INFO_PARAMS *pWatchdogInfoParams); RMCTRL_EXPORT(NV2080_CTRL_CMD_RC_DISABLE_WATCHDOG, - RMCTRL_FLAGS(NON_PRIVILEGED)) + RMCTRL_FLAGS(NON_PRIVILEGED, GPU_LOCK_DEVICE_ONLY)) NV_STATUS subdeviceCtrlCmdRcDisableWatchdog(Subdevice *pSubdevice); RMCTRL_EXPORT(NV2080_CTRL_CMD_RC_SOFT_DISABLE_WATCHDOG, - RMCTRL_FLAGS(NON_PRIVILEGED)) + RMCTRL_FLAGS(NON_PRIVILEGED, GPU_LOCK_DEVICE_ONLY)) NV_STATUS subdeviceCtrlCmdRcSoftDisableWatchdog(Subdevice *pSubdevice); RMCTRL_EXPORT(NV2080_CTRL_CMD_RC_ENABLE_WATCHDOG, - RMCTRL_FLAGS(NON_PRIVILEGED)) + RMCTRL_FLAGS(NON_PRIVILEGED, GPU_LOCK_DEVICE_ONLY)) NV_STATUS subdeviceCtrlCmdRcEnableWatchdog(Subdevice *pSubdevice); RMCTRL_EXPORT(NV2080_CTRL_CMD_RC_RELEASE_WATCHDOG_REQUESTS, - RMCTRL_FLAGS(NON_PRIVILEGED)) + RMCTRL_FLAGS(NON_PRIVILEGED, GPU_LOCK_DEVICE_ONLY)) NV_STATUS subdeviceCtrlCmdRcReleaseWatchdogRequests(Subdevice *pSubdevice); RMCTRL_EXPORT(NV2080_CTRL_CMD_INTERNAL_RC_WATCHDOG_TIMEOUT, diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/inc/kernel/gpu_mgr/gpu_mgr_sli.h nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/inc/kernel/gpu_mgr/gpu_mgr_sli.h --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/inc/kernel/gpu_mgr/gpu_mgr_sli.h 1970-01-01 00:00:00.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/inc/kernel/gpu_mgr/gpu_mgr_sli.h 2024-03-05 22:12:58.000000000 +0000 @@ -0,0 +1,59 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2012-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef _RMSLIGPUMGR_H_ +#define _RMSLIGPUMGR_H_ + +void gpumgrDetectSliLinkFromGpus(NvBool, NvU32, NvU32, NvU32 *, NvU32 *, NvBool *, NvU32 *, NvU32 *); +NvBool gpumgrDetectHighSpeedVideoBridges(NvU32 linkOutputMask); +NvBool gpumgrUpdateSliLinkRouting(OBJGPU *pGpuParent, OBJGPU *pGpuChild, + NvU32 bridgeType, + NvU32 parentPinsetIndex, NvU32 childPinsetIndex, + NvBool bForceUpdate); +NV_STATUS gpumgrPinsetToPinsetTableIndex(NvU32 pinset, NvU32 *pPinsetIndex); +NV_STATUS gpumgrGetSliLinks(NV0000_CTRL_GPU_GET_VIDEO_LINKS_PARAMS *); + +#define drPinSet_None 0x0 +#define drPinSet_A 0x1 +#define drPinSet_B 0x2 +#define DR_PINSET_COUNT 2 + +//// Broadcast device defines +// +// These next defines are for the OBJGPUMGR.gpuSliLinkRoute array. +#define NV_SLILINK_ROUTE_INPUT 1:0 +#define NV_SLILINK_ROUTE_INPUT_UNTESTED 0x00 +#define NV_SLILINK_ROUTE_INPUT_IDENTITY 0x01 +#define NV_SLILINK_ROUTE_INPUT_FAILED 0x02 +#define NV_SLILINK_ROUTE_INPUT_PASSED 0x03 +#define NV_SLILINK_ROUTE_OUTPUT 3:2 +#define NV_SLILINK_ROUTE_OUTPUT_UNTESTED 0x00 +#define NV_SLILINK_ROUTE_OUTPUT_IDENTITY 0x01 +#define NV_SLILINK_ROUTE_OUTPUT_FAILED 0x02 +#define NV_SLILINK_ROUTE_OUTPUT_PASSED 0x03 +#define NV_SLILINK_ROUTE_INPUT_CHILD_PORT 7:4 +#define NV_SLILINK_ROUTE_NVLINK 8:8 +#define NV_SLILINK_ROUTE_NVLINK_TRUE 0x01 +#define NV_SLILINK_ROUTE_NVLINK_FALSE 0x02 + +#endif //_RMSLIGPUMGR_H_ diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/inc/kernel/mem_mgr/ctx_buf_pool.h nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/inc/kernel/mem_mgr/ctx_buf_pool.h --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/inc/kernel/mem_mgr/ctx_buf_pool.h 2023-10-25 20:20:37.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/inc/kernel/mem_mgr/ctx_buf_pool.h 2024-03-05 22:12:59.000000000 +0000 @@ -77,7 +77,7 @@ void ctxBufPoolRelease(CTX_BUF_POOL_INFO *pCtxBufPool); void ctxBufPoolDestroy(CTX_BUF_POOL_INFO **ppCtxBufPool); NvBool ctxBufPoolIsSupported(OBJGPU *pGpu); -NV_STATUS ctxBufPoolGetSizeAndPageSize(CTX_BUF_POOL_INFO *pCtxBufPool, OBJGPU *pGpu, NvU64 alignment, RM_ATTR_PAGE_SIZE attr, NvBool bContig, NvU64 *pSize, NvU32 *pPageSize); +NV_STATUS ctxBufPoolGetSizeAndPageSize(CTX_BUF_POOL_INFO *pCtxBufPool, OBJGPU *pGpu, NvU64 alignment, RM_ATTR_PAGE_SIZE attr, NvBool bContig, NvU64 *pSize, NvU64 *pPageSize); NV_STATUS ctxBufPoolGetGlobalPool(OBJGPU *pGpu, CTX_BUF_ID bufId, RM_ENGINE_TYPE rmEngineType, CTX_BUF_POOL_INFO **ppCtxBufPool); NvBool ctxBufPoolIsScrubSkipped(CTX_BUF_POOL_INFO *pCtxBufPool); void ctxBufPoolSetScrubSkip(CTX_BUF_POOL_INFO *pCtxBufPool, NvBool bSkipScrub); diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/inc/kernel/mem_mgr/egm_mem.h nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/inc/kernel/mem_mgr/egm_mem.h --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/inc/kernel/mem_mgr/egm_mem.h 1970-01-01 00:00:00.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/inc/kernel/mem_mgr/egm_mem.h 2024-03-05 22:11:24.000000000 +0000 @@ -0,0 +1,3 @@ + +#include "g_egm_mem_nvoc.h" + diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/inc/kernel/mem_mgr/pool_alloc.h nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/inc/kernel/mem_mgr/pool_alloc.h --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/inc/kernel/mem_mgr/pool_alloc.h 2023-10-25 20:20:37.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/inc/kernel/mem_mgr/pool_alloc.h 2024-03-05 22:12:59.000000000 +0000 @@ -46,13 +46,13 @@ typedef enum { - POOL_CONFIG_GMMU_FMT_1 = 0, // configure pool for client page tables with version = GMMU_FMT_VERSION_1 - POOL_CONFIG_GMMU_FMT_2 = 1, // configure pool for client page tables with version = GMMU_FMT_VERSION_2 - POOL_CONFIG_CTXBUF_512M = 2, // configure pool for RM internal allocations like ctx buffers with 512MB page size - POOL_CONFIG_CTXBUF_2M = 3, // configure pool for RM internal allocations like ctx buffers with 2MB page size - POOL_CONFIG_CTXBUF_64K = 4, // configure pool for RM internal allocations like ctx buffers with 64KB page size - POOL_CONFIG_CTXBUF_4K = 5, // configure pool for RM internal allocations like ctx buffers with 4KB page size - POOL_CONFIG_MAX_SUPPORTED = 6 + POOL_CONFIG_GMMU_FMT_1, // configure pool for client page tables with version = GMMU_FMT_VERSION_1 + POOL_CONFIG_GMMU_FMT_2, // configure pool for client page tables with version = GMMU_FMT_VERSION_2 + POOL_CONFIG_CTXBUF_512M, // configure pool for RM internal allocations like ctx buffers with 512MB page size + POOL_CONFIG_CTXBUF_2M, // configure pool for RM internal allocations like ctx buffers with 2MB page size + POOL_CONFIG_CTXBUF_64K, // configure pool for RM internal allocations like ctx buffers with 64KB page size + POOL_CONFIG_CTXBUF_4K, // configure pool for RM internal allocations like ctx buffers with 4KB page size + POOL_CONFIG_MAX_SUPPORTED }POOL_CONFIG_MODE; /* ------------------------------------ Datatypes ---------------------------------- */ @@ -196,7 +196,7 @@ * NV_ERR_INVALID_ARGUMENT * NV_OK */ -NV_STATUS rmMemPoolGetChunkAndPageSize(RM_POOL_ALLOC_MEM_RESERVE_INFO *pMemReserveInfo, NvU64*, NvU32*); +NV_STATUS rmMemPoolGetChunkAndPageSize(RM_POOL_ALLOC_MEM_RESERVE_INFO *pMemReserveInfo, NvU64*, NvU64*); /*! * @brief Indicate that pool should be allocated in protected video memory in diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/inc/kernel/os/os_stub.h nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/inc/kernel/os/os_stub.h --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/inc/kernel/os/os_stub.h 2023-10-25 20:20:38.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/inc/kernel/os/os_stub.h 2024-03-05 22:12:59.000000000 +0000 @@ -53,36 +53,19 @@ OSSimEscapeRead stubOsSimEscapeRead; OSSimEscapeReadBuffer stubOsSimEscapeReadBuffer; OSSetSurfaceName stubOsSetSurfaceName; -OSCallACPI_MXMX stubOsCallACPI_MXMX; -OSCallACPI_DSM stubOsCallACPI_DSM; -OSCallACPI_DDC stubOsCallACPI_DDC; -OSCallACPI_BCL stubOsCallACPI_BCL; -OSCallACPI_ON stubOsCallACPI_ON; -OSCallACPI_OFF stubOsCallACPI_OFF; -OSCallACPI_NVHG_GPUON stubOsCallWMI_NVHG_GPUON; -OSCallACPI_NVHG_GPUOFF stubOsCallWMI_NVHG_GPUOFF; OSCallACPI_NVHG_GPUSTA stubOsCallWMI_NVHG_GPUSTA; OSCallACPI_NVHG_MXDS stubOsCallWMI_NVHG_MXDS; OSCallACPI_NVHG_MXMX stubOsCallWMI_NVHG_MXMX; OSCallACPI_NVHG_DOS stubOsCallWMI_NVHG_DOS; -OSCallACPI_NVHG_ROM stubOsCallWMI_NVHG_ROM; OSCallACPI_NVHG_DCS stubOsCallWMI_NVHG_DCS; -OSCallACPI_DOD stubOsCallWMI_DOD; OSCheckCallback stubOsCheckCallback; OSRCCallback stubOsRCCallback; -OSCallACPI_NBPS stubOsCallACPI_NBPS; -OSCallACPI_NBSL stubOsCallACPI_NBSL; -OSCallACPI_OPTM_GPUON stubOsCallWMI_OPTM_GPUON; OSSetupVBlank stubOsSetupVBlank; OSObjectEventNotification stubOsObjectEventNotification; OSPageArrayGetPhysAddr stubOsPageArrayGetPhysAddr; OSInternalReserveFreeCallback stubOsInternalReserveFreeCallback; OSInternalReserveAllocCallback stubOsInternalReserveAllocCallback; OSGetUefiVariable stubOsGetUefiVariable; -OSCallACPI_MXDS stubOsCallACPI_MXDS; -OSCallACPI_MXDM stubOsCallACPI_MXDM; -OSCallACPI_MXID stubOsCallACPI_MXID; -OSCallACPI_LRST stubOsCallACPI_LRST; #endif // OS_STUB_H diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/inc/kernel/platform/nbsi/nbsi_table.h nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/inc/kernel/platform/nbsi/nbsi_table.h --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/inc/kernel/platform/nbsi/nbsi_table.h 2023-10-25 20:20:38.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/inc/kernel/platform/nbsi/nbsi_table.h 2024-03-05 22:13:00.000000000 +0000 @@ -47,9 +47,9 @@ #define NBSI_TBL_SOURCE_MAX 6 // number of NBSI_TBL_SOURCES entries (not including BEST FIT) #define NBSI_TBL_SOURCE_ALL (NBSI_TBL_SOURCE_REGISTRY | \ - NBSI_TBL_SOURCE_VBIOS | \ - NBSI_TBL_SOURCE_SBIOS | \ - NBSI_TBL_SOURCE_ACPI | \ + NBSI_TBL_SOURCE_VBIOS | \ + NBSI_TBL_SOURCE_SBIOS | \ + NBSI_TBL_SOURCE_ACPI | \ NBSI_TBL_SOURCE_UEFI) #define NBSI_TBL_SOURCE_NONE 0 diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/inc/kernel/platform/pci_exp_table.h nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/inc/kernel/platform/pci_exp_table.h --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/inc/kernel/platform/pci_exp_table.h 2023-10-25 20:20:38.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/inc/kernel/platform/pci_exp_table.h 2024-03-05 22:13:00.000000000 +0000 @@ -31,7 +31,7 @@ #define PCI_EXP_ROM_SIGNATURE 0xaa55 #define PCI_EXP_ROM_SIGNATURE_NV 0x4e56 // "VN" in word format #define PCI_EXP_ROM_SIGNATURE_NV2 0xbb77 -#define IS_VALID_PCI_ROM_SIG(sig) ((sig == PCI_EXP_ROM_SIGNATURE) || \ +#define IS_VALID_PCI_ROM_SIG(sig) ((sig == PCI_EXP_ROM_SIGNATURE) || \ (sig == PCI_EXP_ROM_SIGNATURE_NV) || \ (sig == PCI_EXP_ROM_SIGNATURE_NV2)) @@ -68,7 +68,7 @@ #define PCI_DATA_STRUCT_SIGNATURE 0x52494350 // "PCIR" in dword format #define PCI_DATA_STRUCT_SIGNATURE_NV 0x5344504E // "NPDS" in dword format #define PCI_DATA_STRUCT_SIGNATURE_NV2 0x53494752 // "RGIS" in dword format -#define IS_VALID_PCI_DATA_SIG(sig) ((sig == PCI_DATA_STRUCT_SIGNATURE) || \ +#define IS_VALID_PCI_DATA_SIG(sig) ((sig == PCI_DATA_STRUCT_SIGNATURE) || \ (sig == PCI_DATA_STRUCT_SIGNATURE_NV) || \ (sig == PCI_DATA_STRUCT_SIGNATURE_NV2)) diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/inc/kernel/platform/platform_request_handler_utils.h nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/inc/kernel/platform/platform_request_handler_utils.h --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/inc/kernel/platform/platform_request_handler_utils.h 2023-10-25 20:20:38.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/inc/kernel/platform/platform_request_handler_utils.h 2024-03-05 22:13:01.000000000 +0000 @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 2011-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2011-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -54,6 +54,42 @@ #define NV_PB_PFM_REQ_HNDLR_PCTRL_BIT_31 31:31 #define NV_PB_PFM_REQ_HNDLR_PCTRL_BIT_31_ZERO (0) +/* + * NV0000_CTRL_PFM_REQ_HNDLR_EDPP_LIMIT_INFO + * + * GPU EDPpeak Limit information for platform + * + * ulVersion + * (Major(16 bits):Minor(16 bits), current v1.0) + * Little endian format 0x00, 0x00, 0x01, 0x00 + * limitLast + * last requested platform limit + * limitMin + * Minimum allowed limit value on EDPp policy on both AC and DC + * limitRated + * Rated/default allowed limit value on EDPp policy on AC + * limitMax + * Maximum allowed limit value on EDPp policy on AC + * limitCurr + * Current resultant limit effective on EDPp policy on AC and DC + * limitBattRated + * Default/rated allowed limit on EDPp policy on DC + * limitBattMax + * Maximum allowed limit on EDPp policy on DC + * rsvd + * Reserved + */ +typedef struct NV0000_CTRL_PFM_REQ_HNDLR_EDPP_LIMIT_INFO_V1 { + NvU32 ulVersion; + NvU32 limitLast; + NvU32 limitMin; + NvU32 limitRated; + NvU32 limitMax; + NvU32 limitCurr; + NvU32 limitBattRated; + NvU32 limitBattMax; + NvU32 rsvd; +} NV0000_CTRL_PFM_REQ_HNDLR_EDPP_LIMIT_INFO_V1, *PNV0000_CTRL_PFM_REQ_HNDLR_EDPP_LIMIT_INFO_V1; /* * NV0000_CTRL_PFM_REQ_HNDLR_PSHAREDATA @@ -159,7 +195,7 @@ * Used for PPL and TRL calls, which have up to three input DWORDs and three * output DWORDs. */ -#define NV0000_CTRL_PFM_REQ_HNDLR_CALL_ACPI_PARAMS_EX_MAX_SZ (3) +#define NV0000_CTRL_PFM_REQ_HNDLR_CALL_ACPI_PARAMS_EX_MAX_SZ (3U) typedef struct _NV0000_CTRL_PFM_REQ_HNDLR_CALL_ACPI_PARAMS_EX { @@ -170,29 +206,33 @@ NvU32 output[NV0000_CTRL_PFM_REQ_HNDLR_CALL_ACPI_PARAMS_EX_MAX_SZ]; } NV0000_CTRL_PFM_REQ_HNDLR_CALL_ACPI_PARAMS_EX; -#define NV0000_CTRL_PFM_REQ_HNDLR_CALL_ACPI_CMD_TYPE 8:0 -#define NV0000_CTRL_PFM_REQ_HNDLR_CALL_ACPI_CMD_SUPPORT (GPS_FUNC_SUPPORT) -#define NV0000_CTRL_PFM_REQ_HNDLR_CALL_ACPI_CMD_PCONTROL (GPS_FUNC_PCONTROL) -#define NV0000_CTRL_PFM_REQ_HNDLR_CALL_ACPI_CMD_PSHARESTATUS (GPS_FUNC_PSHARESTATUS) -#define NV0000_CTRL_PFM_REQ_HNDLR_CALL_ACPI_CMD_GETPPL (GPS_FUNC_GETPPL) -#define NV0000_CTRL_PFM_REQ_HNDLR_CALL_ACPI_CMD_SETPPL (GPS_FUNC_SETPPL) -#define NV0000_CTRL_PFM_REQ_HNDLR_CALL_ACPI_CMD_GETTRL (GPS_FUNC_GETTRL) -#define NV0000_CTRL_PFM_REQ_HNDLR_CALL_ACPI_CMD_SETTRL (GPS_FUNC_SETTRL) -#define NV0000_CTRL_PFM_REQ_HNDLR_CALL_ACPI_CMD_GETPPM (GPS_FUNC_GETPPM) -#define NV0000_CTRL_PFM_REQ_HNDLR_CALL_ACPI_CMD_SETPPM (GPS_FUNC_SETPPM) -#define NV0000_CTRL_PFM_REQ_HNDLR_CALL_ACPI_CMD_PSHAREPARAMS (GPS_FUNC_PSHAREPARAMS) +#define NV0000_CTRL_PFM_REQ_HNDLR_CALL_ACPI_CMD_TYPE 8:0 +#define NV0000_CTRL_PFM_REQ_HNDLR_CALL_ACPI_CMD_SUPPORT (GPS_FUNC_SUPPORT) +#define NV0000_CTRL_PFM_REQ_HNDLR_CALL_ACPI_CMD_PCONTROL (GPS_FUNC_PCONTROL) +#define NV0000_CTRL_PFM_REQ_HNDLR_CALL_ACPI_CMD_PSHARESTATUS (GPS_FUNC_PSHARESTATUS) +#define NV0000_CTRL_PFM_REQ_HNDLR_CALL_ACPI_CMD_GETPPL (GPS_FUNC_GETPPL) +#define NV0000_CTRL_PFM_REQ_HNDLR_CALL_ACPI_CMD_SETPPL (GPS_FUNC_SETPPL) +#define NV0000_CTRL_PFM_REQ_HNDLR_CALL_ACPI_CMD_GETTRL (GPS_FUNC_GETTRL) +#define NV0000_CTRL_PFM_REQ_HNDLR_CALL_ACPI_CMD_SETTRL (GPS_FUNC_SETTRL) +#define NV0000_CTRL_PFM_REQ_HNDLR_CALL_ACPI_CMD_GETPPM (GPS_FUNC_GETPPM) +#define NV0000_CTRL_PFM_REQ_HNDLR_CALL_ACPI_CMD_SETPPM (GPS_FUNC_SETPPM) +#define NV0000_CTRL_PFM_REQ_HNDLR_CALL_ACPI_CMD_PSHAREPARAMS (GPS_FUNC_PSHAREPARAMS) +#define NV0000_CTRL_PFM_REQ_HNDLR_CALL_ACPI_CMD_SETEDPPLIMITINFO (GPS_FUNC_SETEDPPLIMITINFO) +#define NV0000_CTRL_PFM_REQ_HNDLR_CALL_ACPI_CMD_GETEDPPLIMIT (GPS_FUNC_GETEDPPLIMIT) // PFM_REQ_HNDLR_SUPPORT output -#define NV0000_CTRL_PFM_REQ_HNDLR_SUPPORTED_SUPPORT_AVAIL 0:0 -#define NV0000_CTRL_PFM_REQ_HNDLR_SUPPORTED_PCONTROL_AVAIL 28:28 -#define NV0000_CTRL_PFM_REQ_HNDLR_SUPPORTED_PSHARESTATUS_AVAIL 32:32 -#define NV0000_CTRL_PFM_REQ_HNDLR_SUPPORTED_GETPPL_AVAIL 36:36 -#define NV0000_CTRL_PFM_REQ_HNDLR_SUPPORTED_SETPPL_AVAIL 37:37 -#define NV0000_CTRL_PFM_REQ_HNDLR_SUPPORTED_GETTRL_AVAIL 38:38 -#define NV0000_CTRL_PFM_REQ_HNDLR_SUPPORTED_SETTRL_AVAIL 39:39 -#define NV0000_CTRL_PFM_REQ_HNDLR_SUPPORTED_GETPPM_AVAIL 40:40 -#define NV0000_CTRL_PFM_REQ_HNDLR_SUPPORTED_SETPPM_AVAIL 41:41 -#define NV0000_CTRL_PFM_REQ_HNDLR_SUPPORTED_PSHAREPARAMS_AVAIL 42:42 +#define NV0000_CTRL_PFM_REQ_HNDLR_SUPPORTED_SUPPORT_AVAIL 0:0 +#define NV0000_CTRL_PFM_REQ_HNDLR_SUPPORTED_PCONTROL_AVAIL 28:28 +#define NV0000_CTRL_PFM_REQ_HNDLR_SUPPORTED_PSHARESTATUS_AVAIL 32:32 +#define NV0000_CTRL_PFM_REQ_HNDLR_SUPPORTED_GETPPL_AVAIL 36:36 +#define NV0000_CTRL_PFM_REQ_HNDLR_SUPPORTED_SETPPL_AVAIL 37:37 +#define NV0000_CTRL_PFM_REQ_HNDLR_SUPPORTED_GETTRL_AVAIL 38:38 +#define NV0000_CTRL_PFM_REQ_HNDLR_SUPPORTED_SETTRL_AVAIL 39:39 +#define NV0000_CTRL_PFM_REQ_HNDLR_SUPPORTED_GETPPM_AVAIL 40:40 +#define NV0000_CTRL_PFM_REQ_HNDLR_SUPPORTED_SETPPM_AVAIL 41:41 +#define NV0000_CTRL_PFM_REQ_HNDLR_SUPPORTED_PSHAREPARAMS_AVAIL 42:42 +#define NV0000_CTRL_PFM_REQ_HNDLR_SUPPORTED_INFOEDPPLIMIT_AVAIL 43:43 +#define NV0000_CTRL_PFM_REQ_HNDLR_SUPPORTED_SETEDPPLIMIT_AVAIL 44:44 // PFM_REQ_HNDLR_PCONTROL #define NV0000_CTRL_PFM_REQ_HNDLR_PCONTROL_REQ_TYPE 3:0 @@ -209,25 +249,30 @@ // PFM_REQ_HNDLR_PSHARESTATUS #define NV0000_CTRL_PFM_REQ_HNDLR_PSHARESTATUS_UPDATE_LIMIT 0:0 // output only -#define NV0000_CTRL_PFM_REQ_HNDLR_PSHARESTATUS_UPDATE_LIMIT_NOT_PENDING (0) -#define NV0000_CTRL_PFM_REQ_HNDLR_PSHARESTATUS_UPDATE_LIMIT_PENDING (1) +#define NV0000_CTRL_PFM_REQ_HNDLR_PSHARESTATUS_UPDATE_LIMIT_NOT_PENDING (0) +#define NV0000_CTRL_PFM_REQ_HNDLR_PSHARESTATUS_UPDATE_LIMIT_PENDING (1) #define NV0000_CTRL_PFM_REQ_HNDLR_PSHARESTATUS_DO_NOT_USE 19:1 #define NV0000_CTRL_PFM_REQ_HNDLR_PSHARESTATUS_PLAT_USER_CONFIG_TGP_MODE_SUPPORT 20:20 // output only -#define NV0000_CTRL_PFM_REQ_HNDLR_PSHARESTATUS_PLAT_USER_CONFIG_TGP_MODE_SUPPORT_DISABLE (0) -#define NV0000_CTRL_PFM_REQ_HNDLR_PSHARESTATUS_PLAT_USER_CONFIG_TGP_MODE_SUPPORT_ENABLE (1) +#define NV0000_CTRL_PFM_REQ_HNDLR_PSHARESTATUS_PLAT_USER_CONFIG_TGP_MODE_SUPPORT_DISABLE (0) +#define NV0000_CTRL_PFM_REQ_HNDLR_PSHARESTATUS_PLAT_USER_CONFIG_TGP_MODE_SUPPORT_ENABLE (1) #define NV0000_CTRL_PFM_REQ_HNDLR_PSHARESTATUS_EDPPEAK_LIMIT_UPDATE 21:21 // output only -#define NV0000_CTRL_PFM_REQ_HNDLR_PSHARESTATUS_EDPPEAK_LIMIT_UPDATE_FALSE (0) -#define NV0000_CTRL_PFM_REQ_HNDLR_PSHARESTATUS_EDPPEAK_LIMIT_UPDATE_TRUE (1) +#define NV0000_CTRL_PFM_REQ_HNDLR_PSHARESTATUS_EDPPEAK_LIMIT_UPDATE_FALSE (0) +#define NV0000_CTRL_PFM_REQ_HNDLR_PSHARESTATUS_EDPPEAK_LIMIT_UPDATE_TRUE (1) #define NV0000_CTRL_PFM_REQ_HNDLR_PSHARESTATUS_USER_CONFIG_TGP_MODE 22:22 // output only -#define NV0000_CTRL_PFM_REQ_HNDLR_PSHARESTATUS_USER_CONFIG_TGP_MODE_DISABLE (0) -#define NV0000_CTRL_PFM_REQ_HNDLR_PSHARESTATUS_USER_CONFIG_TGP_MODE_ENABLE (1) - +#define NV0000_CTRL_PFM_REQ_HNDLR_PSHARESTATUS_USER_CONFIG_TGP_MODE_DISABLE (0) +#define NV0000_CTRL_PFM_REQ_HNDLR_PSHARESTATUS_USER_CONFIG_TGP_MODE_ENABLE (1) +#define NV0000_CTRL_PFM_REQ_HNDLR_PSHARESTATUS_PLATFORM_GETEDPPEAKLIMIT_SET 25:25 // output only +#define NV0000_CTRL_PFM_REQ_HNDLR_PSHARESTATUS_PLATFORM_GETEDPPEAKLIMIT_SET_FALSE (0U) +#define NV0000_CTRL_PFM_REQ_HNDLR_PSHARESTATUS_PLATFORM_GETEDPPEAKLIMIT_SET_TRUE (1U) +#define NV0000_CTRL_PFM_REQ_HNDLR_PSHARESTATUS_PLATFORM_SETEDPPEAKLIMITINFO_SET 26:26 // output only +#define NV0000_CTRL_PFM_REQ_HNDLR_PSHARESTATUS_PLATFORM_SETEDPPEAKLIMITINFO_SET_FALSE (0U) +#define NV0000_CTRL_PFM_REQ_HNDLR_PSHARESTATUS_PLATFORM_SETEDPPEAKLIMITINFO_SET_TRUE (1U) // Shared by GETPPL, SETPPL #define NV0000_CTRL_PFM_REQ_HNDLR_PPL_ARGS_COUNT (3) #define NV0000_CTRL_PFM_REQ_HNDLR_PPL_ARGS_VERSION_IDX (0) -#define NV0000_CTRL_PFM_REQ_HNDLR_PPL_ARG0_VERSION_MINOR 15:0 // input & output -#define NV0000_CTRL_PFM_REQ_HNDLR_PPL_ARG0_VERSION_MAJOR 31:16 // input & output +#define NV0000_CTRL_PFM_REQ_HNDLR_PPL_ARG0_VERSION_MINOR 15:0 // input & output +#define NV0000_CTRL_PFM_REQ_HNDLR_PPL_ARG0_VERSION_MAJOR 31:16 // input & output #define NV0000_CTRL_PFM_REQ_HNDLR_PPL_ARG0_VERSION_MAJOR_V1 (1) // input & output #define NV0000_CTRL_PFM_REQ_HNDLR_PPL_ARGS_LIMIT1_IDX (1) // input & output #define NV0000_CTRL_PFM_REQ_HNDLR_PPL_ARGS_LIMIT2_IDX (2) // input & output @@ -235,21 +280,24 @@ // Shared by GETTRL, SETTRL #define NV0000_CTRL_PFM_REQ_HNDLR_TRL_ARGS_COUNT (2) #define NV0000_CTRL_PFM_REQ_HNDLR_TRL_ARGS_VERSION_IDX (0) -#define NV0000_CTRL_PFM_REQ_HNDLR_TRL_ARG0_VERSION_MINOR 15:0 // input & output -#define NV0000_CTRL_PFM_REQ_HNDLR_TRL_ARG0_VERSION_MAJOR 31:16 // input & output +#define NV0000_CTRL_PFM_REQ_HNDLR_TRL_ARG0_VERSION_MINOR 15:0 // input & output +#define NV0000_CTRL_PFM_REQ_HNDLR_TRL_ARG0_VERSION_MAJOR 31:16 // input & output #define NV0000_CTRL_PFM_REQ_HNDLR_TRL_ARG0_VERSION_MAJOR_V1 (1) // input & output #define NV0000_CTRL_PFM_REQ_HNDLR_TRL_ARGS_FREQ_MHZ_IDX (1) // input & output // Shared by GETPPM, SETPPM #define NV0000_CTRL_PFM_REQ_HNDLR_PPM_ARGS_COUNT (2) #define NV0000_CTRL_PFM_REQ_HNDLR_PPM_ARGS_VERSION_IDX (0) -#define NV0000_CTRL_PFM_REQ_HNDLR_PPM_ARG0_VERSION_MINOR 15:0 // input & output -#define NV0000_CTRL_PFM_REQ_HNDLR_PPM_ARG0_VERSION_MAJOR 31:16 // input & output +#define NV0000_CTRL_PFM_REQ_HNDLR_PPM_ARG0_VERSION_MINOR 15:0 // input & output +#define NV0000_CTRL_PFM_REQ_HNDLR_PPM_ARG0_VERSION_MAJOR 31:16 // input & output #define NV0000_CTRL_PFM_REQ_HNDLR_PPM_ARG0_VERSION_MAJOR_V1 (1) // input & output #define NV0000_CTRL_PFM_REQ_HNDLR_PPM_ARGS_IDX (1) // input & output -#define NV0000_CTRL_PFM_REQ_HNDLR_PPM_ARGS_INDEX 7:0 // output +#define NV0000_CTRL_PFM_REQ_HNDLR_PPM_ARGS_INDEX 7:0 // output #define NV0000_CTRL_PFM_REQ_HNDLR_PPM_ARGS_AVAILABLE_MASK 15:8 // output +// Shared by INFOEDPPLIMIT and SETEDPPLIMIT +#define NV0000_CTRL_PFM_REQ_HNDLR_EDPP_VERSION_V10 (0x10000U) // input & output + // // PFM_REQ_HNDLR_PSHARE_PARAMS // status bits @@ -262,10 +310,10 @@ #define NV0000_CTRL_PFM_REQ_HNDLR_PSHARE_PARAMS_STATUS_TGPU_FALSE (0) #define NV0000_CTRL_PFM_REQ_HNDLR_PSHARE_PARAMS_STATUS_TGPU_TRUE (1) #define NV0000_CTRL_PFM_REQ_HNDLR_PSHARE_PARAMS_STATUS_DO_NOT_USE 14:9 // input & output -#define NV0000_CTRL_PFM_REQ_HNDLR_PSHARE_PARAMS_STATUS_CTGP 15:15 // input & output +#define NV0000_CTRL_PFM_REQ_HNDLR_PSHARE_PARAMS_STATUS_CTGP 15:15 // input & output #define NV0000_CTRL_PFM_REQ_HNDLR_PSHARE_PARAMS_STATUS_CTGP_FALSE (0) #define NV0000_CTRL_PFM_REQ_HNDLR_PSHARE_PARAMS_STATUS_CTGP_TRUE (1) -#define NV0000_CTRL_PFM_REQ_HNDLR_PSHARE_PARAMS_STATUS_PPMD 16:16 // input & output +#define NV0000_CTRL_PFM_REQ_HNDLR_PSHARE_PARAMS_STATUS_PPMD 16:16 // input & output #define NV0000_CTRL_PFM_REQ_HNDLR_PSHARE_PARAMS_STATUS_PPMD_FALSE (0) #define NV0000_CTRL_PFM_REQ_HNDLR_PSHARE_PARAMS_STATUS_PPMD_TRUE (1) diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/inc/kernel/platform/sli/sli.h nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/inc/kernel/platform/sli/sli.h --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/inc/kernel/platform/sli/sli.h 2023-10-25 20:20:38.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/inc/kernel/platform/sli/sli.h 2024-03-05 22:13:01.000000000 +0000 @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 2000-2020 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2000-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -38,6 +38,8 @@ // Unlinked SLI is implemented in RM clients #define IsUnlinkedSLIEnabled(p) ((p)->getProperty((p), PDB_PROP_GPU_RM_UNLINKED_SLI)) +void RmInitScalability(OBJGPU *pGpu); + #define IsSLIEnabled(p) 0 #define NumSubDevices(p) 0 diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/inc/kernel/rmapi/control.h nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/inc/kernel/rmapi/control.h --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/inc/kernel/rmapi/control.h 2023-10-25 20:20:39.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/inc/kernel/rmapi/control.h 2024-03-05 22:13:02.000000000 +0000 @@ -37,8 +37,8 @@ // RMCTRL_API_COPPY_FLAGS is used to specify control api copy behavior. #define RMCTRL_API_COPY_FLAGS_NONE 0x00000000 -// skip memory copy in api copy in -#define RMCTRL_API_COPY_FLAGS_SKIP_COPYIN NVBIT(0) +// skip memory copy in api copy in and zero the buffer +#define RMCTRL_API_COPY_FLAGS_SKIP_COPYIN_ZERO_BUFFER NVBIT(0) // set control cache on api copy out #define RMCTRL_API_COPY_FLAGS_SET_CONTROL_CACHE NVBIT(1) @@ -99,20 +99,20 @@ #define RMCTRL_CLEAR_CAP(tbl,cap,field) ((tbl[((1?cap##field)>=cap##_TBL_SIZE) ? 0/0 : (1?cap##field)]) &= ~(0?cap##field)) // macros to AND/OR caps between two tables -#define RMCTRL_AND_CAP(finaltbl,tmptbl,tmp,cap,field) \ +#define RMCTRL_AND_CAP(finaltbl,tmptbl,tmp,cap,field) \ tmp = ((finaltbl[((1?cap##field)>=cap##_TBL_SIZE) ? 0/0 : (1?cap##field)] & tmptbl[((1?cap##field)>=cap##_TBL_SIZE) ? 0/0 : (1?cap##field)]) & (0?cap##field)); \ - finaltbl[((1?cap##field)>=cap##_TBL_SIZE) ? 0/0 : (1?cap##field)] &= ~(0?cap##field); \ + finaltbl[((1?cap##field)>=cap##_TBL_SIZE) ? 0/0 : (1?cap##field)] &= ~(0?cap##field); \ finaltbl[((1?cap##field)>=cap##_TBL_SIZE) ? 0/0 : (1?cap##field)] |= tmp; -#define RMCTRL_OR_CAP(finaltbl,tmptbl,tmp,cap,field) \ +#define RMCTRL_OR_CAP(finaltbl,tmptbl,tmp,cap,field) \ tmp = ((finaltbl[((1?cap##field)>=cap##_TBL_SIZE) ? 0/0 : (1?cap##field)] | tmptbl[((1?cap##field)>=cap##_TBL_SIZE) ? 0/0 : (1?cap##field)]) & (0?cap##field)); \ - finaltbl[((1?cap##field)>=cap##_TBL_SIZE) ? 0/0 : (1?cap##field)] &= ~(0?cap##field); \ + finaltbl[((1?cap##field)>=cap##_TBL_SIZE) ? 0/0 : (1?cap##field)] &= ~(0?cap##field); \ finaltbl[((1?cap##field)>=cap##_TBL_SIZE) ? 0/0 : (1?cap##field)] |= tmp; // Whether the command ID is a NULL command? // We allow NVXXXX_CTRL_CMD_NULL (0x00000000) as well as the // per-class NULL cmd ( _CATEGORY==0x00 and _INDEX==0x00 ) -#define RMCTRL_IS_NULL_CMD(cmd) ((cmd == NVXXXX_CTRL_CMD_NULL) || \ +#define RMCTRL_IS_NULL_CMD(cmd) ((cmd == NVXXXX_CTRL_CMD_NULL) || \ (FLD_TEST_DRF_NUM(XXXX, _CTRL_CMD, _CATEGORY, 0x00, cmd) && \ FLD_TEST_DRF_NUM(XXXX, _CTRL_CMD, _INDEX, 0x00, cmd))) @@ -141,11 +141,8 @@ #define _RMCTRL_PREP_ACCESS_ARG(x) | NVBIT(NV_CONCATENATE(RS_ACCESS_, x)) #define ACCESS_RIGHTS(...) (0 NV_FOREACH_ARG_NOCOMMA(_RMCTRL_PREP_ACCESS_ARG, __VA_ARGS__)) -#define NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(ctrlFlags) \ - ( \ - (ctrlFlags & RMCTRL_FLAGS_ROUTE_TO_PHYSICAL) && \ - !RMCFG_FEATURE_PHYSICAL_RM \ - ) +#define NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(ctrlFlags) \ + (ctrlFlags & RMCTRL_FLAGS_ROUTE_TO_PHYSICAL) // // 'FLAGS' Attribute @@ -292,6 +289,17 @@ #define RMCTRL_FLAGS_GSP_PLUGIN_FOR_VGPU_GSP 0x000100000 // +// This flag specifies that the control output depends on the input +// parameters but can be cached on receiving end. Since the control +// result depends on the input and the input varifies with controls, +// the cache should be handled in a per-control bases. +// +#define RMCTRL_FLAGS_CACHEABLE_BY_INPUT 0x000200000 + +// The combination of cacheable flags +#define RMCTRL_FLAGS_CACHEABLE_ANY (RMCTRL_FLAGS_CACHEABLE | RMCTRL_FLAGS_CACHEABLE_BY_INPUT) + +// // 'ACCESS_RIGHTS' Attribute // ------------------------ // diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/inc/kernel/rmapi/mapping_list.h nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/inc/kernel/rmapi/mapping_list.h --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/inc/kernel/rmapi/mapping_list.h 2023-10-25 20:20:39.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/inc/kernel/rmapi/mapping_list.h 2024-03-05 22:13:02.000000000 +0000 @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 1993-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 1993-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -50,7 +50,6 @@ // struct _def_client_dma_mapping_info { - NvHandle hDevice; NvU64 DmaOffset; void* KernelVAddr[NV_MAX_SUBDEVICES]; // Kernel's virtual address, if required void* KernelPriv; // Token required to unmap the kernel mapping @@ -60,11 +59,11 @@ NvU32 Flags; NvBool bP2P; NvU32 gpuMask; + NvU64 mapPageSize; // Page size at which the memory is mapped. ADDRESS_TRANSLATION addressTranslation; MEMORY_DESCRIPTOR *pBar1P2PVirtMemDesc; // The peer GPU mapped BAR1 region MEMORY_DESCRIPTOR *pBar1P2PPhysMemDesc; // The peer GPU vidmem sub region - PCLI_DMA_MAPPING_INFO Next; - PCLI_DMA_MAPPING_INFO Prev; + CLI_DMA_MAPPING_INFO *pNext; }; // @@ -72,8 +71,7 @@ // struct _def_client_dma_mapping_info_iterator { - PNODE pDmaMappingList; // list of hDevices - PNODE pCurrentList; // current hDevice list entry, is list of pDmaMappings + PNODE pDmaMappingList; // list of pDmaMappings PNODE pNextDmaMapping; // next pDmaMapping while iterating over the DmaOffsets }; @@ -159,16 +157,14 @@ RsCpuMapping *CliFindMappingInClient (NvHandle, NvHandle, NvP64); // DMA Mappings -NV_STATUS intermapCreateDmaMapping (RsClient *, RsResourceRef *, NvHandle, NvHandle, PCLI_DMA_MAPPING_INFO *, NvU32); -NV_STATUS intermapRegisterDmaMapping (RsClient *, NvHandle, NvHandle, PCLI_DMA_MAPPING_INFO, NvU64, NvU32); -NV_STATUS intermapDelDmaMapping (RsClient *, NvHandle, NvHandle, NvU64, NvU32, NvBool*); +NV_STATUS intermapCreateDmaMapping (RsClient *, VirtualMemory *, PCLI_DMA_MAPPING_INFO *, NvU32); +NV_STATUS intermapRegisterDmaMapping (RsClient *, VirtualMemory *, PCLI_DMA_MAPPING_INFO, NvU64, NvU32); +NV_STATUS intermapDelDmaMapping (RsClient *, VirtualMemory *, NvU64, NvU32); void intermapFreeDmaMapping (PCLI_DMA_MAPPING_INFO); +CLI_DMA_MAPPING_INFO *intermapGetDmaMapping (VirtualMemory *pVirtualMemory, NvU64 dmaOffset, NvU32 gpuMask); -NvBool CliGetDmaMappingInfo (NvHandle, NvHandle, NvHandle, NvU64, NvU32, PCLI_DMA_MAPPING_INFO*); +NvBool CliGetDmaMappingInfo (RsClient *, NvHandle, NvHandle, NvU64, NvU32, PCLI_DMA_MAPPING_INFO*); void CliGetDmaMappingIterator (PCLI_DMA_MAPPING_INFO *, PCLI_DMA_MAPPING_INFO_ITERATOR, PNODE pDmaMappingList); void CliGetDmaMappingNext (PCLI_DMA_MAPPING_INFO *, PCLI_DMA_MAPPING_INFO_ITERATOR); -// Unmap all DMA mappings between a memory resource and any DynamicMemory -NV_STATUS intermapUnmapDeviceMemoryDma (RsClient *, RsResourceRef *, NvHandle); - #endif diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/inc/kernel/rmapi/nv_gpu_ops.h nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/inc/kernel/rmapi/nv_gpu_ops.h --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/inc/kernel/rmapi/nv_gpu_ops.h 2023-10-25 20:20:39.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/inc/kernel/rmapi/nv_gpu_ops.h 2024-03-05 22:13:02.000000000 +0000 @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 2013-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2013-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -39,6 +39,7 @@ typedef struct gpuSession *gpuSessionHandle; typedef struct gpuDevice *gpuDeviceHandle; typedef struct gpuAddressSpace *gpuAddressSpaceHandle; +typedef struct gpuTsg *gpuTsgHandle; typedef struct gpuChannel *gpuChannelHandle; typedef struct gpuObject *gpuObjectHandle; @@ -76,28 +77,32 @@ NV_STATUS nvGpuOpsPmaAllocPages(void *pPma, NvLength pageCount, - NvU32 pageSize, + NvU64 pageSize, gpuPmaAllocationOptions *pPmaAllocOptions, NvU64 *pPages); void nvGpuOpsPmaFreePages(void *pPma, NvU64 *pPages, NvLength pageCount, - NvU32 pageSize, + NvU64 pageSize, NvU32 flags); NV_STATUS nvGpuOpsPmaPinPages(void *pPma, NvU64 *pPages, NvLength pageCount, - NvU32 pageSize, + NvU64 pageSize, NvU32 flags); NV_STATUS nvGpuOpsPmaUnpinPages(void *pPma, NvU64 *pPages, NvLength pageCount, - NvU32 pageSize); + NvU64 pageSize); -NV_STATUS nvGpuOpsChannelAllocate(gpuAddressSpaceHandle vaSpace, +NV_STATUS nvGpuOpsTsgAllocate(gpuAddressSpaceHandle vaSpace, + const gpuTsgAllocParams *params, + gpuTsgHandle *tsgHandle); + +NV_STATUS nvGpuOpsChannelAllocate(const gpuTsgHandle tsgHandle, const gpuChannelAllocParams *params, gpuChannelHandle *channelHandle, gpuChannelInfo *channelInfo); @@ -105,6 +110,8 @@ NV_STATUS nvGpuOpsMemoryReopen(struct gpuAddressSpace *vaSpace, NvHandle hSrcClient, NvHandle hSrcAllocation, NvLength length, NvU64 *gpuOffset); +void nvGpuOpsTsgDestroy(struct gpuTsg *tsg); + void nvGpuOpsChannelDestroy(struct gpuChannel *channel); void nvGpuOpsMemoryFree(gpuAddressSpaceHandle vaSpace, @@ -112,7 +119,7 @@ NV_STATUS nvGpuOpsMemoryCpuMap(gpuAddressSpaceHandle vaSpace, NvU64 memory, NvLength length, - void **cpuPtr, NvU32 pageSize); + void **cpuPtr, NvU64 pageSize); void nvGpuOpsMemoryCpuUnMap(gpuAddressSpaceHandle vaSpace, void* cpuPtr); @@ -196,7 +203,7 @@ void **pPma, const UvmPmaStatistics **pPmaPubStats); -NV_STATUS nvGpuOpsInitAccessCntrInfo(struct gpuDevice *device, gpuAccessCntrInfo *pAccessCntrInfo); +NV_STATUS nvGpuOpsInitAccessCntrInfo(struct gpuDevice *device, gpuAccessCntrInfo *pAccessCntrInfo, NvU32 accessCntrIndex); NV_STATUS nvGpuOpsDestroyAccessCntrInfo(struct gpuDevice *device, gpuAccessCntrInfo *pAccessCntrInfo); @@ -270,4 +277,44 @@ char *methodStream, NvU32 methodStreamSize); +NV_STATUS nvGpuOpsFlushReplayableFaultBuffer(struct gpuDevice *device); + +// Interface used for CCSL + +NV_STATUS nvGpuOpsCcslContextInit(struct ccslContext_t **ctx, + gpuChannelHandle channel); +NV_STATUS nvGpuOpsCcslContextClear(struct ccslContext_t *ctx); +NV_STATUS nvGpuOpsCcslRotateIv(struct ccslContext_t *ctx, + NvU8 direction); +NV_STATUS nvGpuOpsCcslEncrypt(struct ccslContext_t *ctx, + NvU32 bufferSize, + NvU8 const *inputBuffer, + NvU8 *outputBuffer, + NvU8 *authTagBuffer); +NV_STATUS nvGpuOpsCcslEncryptWithIv(struct ccslContext_t *ctx, + NvU32 bufferSize, + NvU8 const *inputBuffer, + NvU8 *encryptIv, + NvU8 *outputBuffer, + NvU8 *authTagBuffer); +NV_STATUS nvGpuOpsCcslDecrypt(struct ccslContext_t *ctx, + NvU32 bufferSize, + NvU8 const *inputBuffer, + NvU8 const *decryptIv, + NvU8 *outputBuffer, + NvU8 const *addAuthData, + NvU32 addAuthDataSize, + NvU8 const *authTagBuffer); +NV_STATUS nvGpuOpsCcslSign(struct ccslContext_t *ctx, + NvU32 bufferSize, + NvU8 const *inputBuffer, + NvU8 *authTagBuffer); +NV_STATUS nvGpuOpsQueryMessagePool(struct ccslContext_t *ctx, + NvU8 direction, + NvU64 *messageNum); +NV_STATUS nvGpuOpsIncrementIv(struct ccslContext_t *ctx, + NvU8 direction, + NvU64 increment, + NvU8 *iv); + #endif /* _NV_GPU_OPS_H_*/ diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/inc/kernel/rmapi/param_copy.h nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/inc/kernel/rmapi/param_copy.h --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/inc/kernel/rmapi/param_copy.h 2023-10-25 20:20:39.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/inc/kernel/rmapi/param_copy.h 2024-03-05 22:13:02.000000000 +0000 @@ -77,12 +77,12 @@ // this initialization, there is no need to make it return a status and // duplicate error checking. // -#define RMAPI_PARAM_COPY_INIT(paramCopy, pKernelParams, theUserParams, numElems, sizeOfElem) \ - do { \ - RMAPI_PARAM_COPY_SET_MSG_TAG((paramCopy), __FUNCTION__); \ - (paramCopy).ppKernelParams = (void **) &(pKernelParams); \ - (paramCopy).pUserParams = (theUserParams); \ - (paramCopy).flags = RMAPI_PARAM_COPY_FLAGS_NONE; \ +#define RMAPI_PARAM_COPY_INIT(paramCopy, pKernelParams, theUserParams, numElems, sizeOfElem) \ + do { \ + RMAPI_PARAM_COPY_SET_MSG_TAG((paramCopy), __FUNCTION__); \ + (paramCopy).ppKernelParams = (void **) &(pKernelParams); \ + (paramCopy).pUserParams = (theUserParams); \ + (paramCopy).flags = RMAPI_PARAM_COPY_FLAGS_NONE; \ (paramCopy).bSizeValid = portSafeMulU32((numElems), (sizeOfElem), &(paramCopy).paramsSize); \ } while(0) diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/inc/kernel/rmapi/rmapi.h nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/inc/kernel/rmapi/rmapi.h --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/inc/kernel/rmapi/rmapi.h 2023-10-25 20:20:39.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/inc/kernel/rmapi/rmapi.h 2024-03-05 22:13:02.000000000 +0000 @@ -63,6 +63,7 @@ // already held then return error #define RMAPI_LOCK_FLAGS_READ NVBIT(1) // Acquire API lock for READ #define RMAPI_LOCK_FLAGS_WRITE (0x00000000) // Acquire API lock for WRITE - Default +#define RMAPI_LOCK_FLAGS_LOW_PRIORITY NVBIT(2) // Deprioritize lock acquire /** * Acquire the RM API Lock @@ -113,10 +114,16 @@ // Flags for RM_API::Alloc #define RMAPI_ALLOC_FLAGS_NONE 0 #define RMAPI_ALLOC_FLAGS_SKIP_RPC NVBIT(0) +#define RMAPI_ALLOC_FLAGS_SERIALIZED NVBIT(1) // Flags for RM_API::Free #define RMAPI_FREE_FLAGS_NONE 0 +// Flags for RM_API RPC's +#define RMAPI_RPC_FLAGS_NONE 0 +#define RMAPI_RPC_FLAGS_COPYOUT_ON_ERROR NVBIT(0) +#define RMAPI_RPC_FLAGS_SERIALIZED NVBIT(1) + /** * Interface for performing operations through the RM API exposed to client * drivers. Interface provides consistent view to the RM API while abstracting @@ -128,16 +135,16 @@ { // Allocate a resource with default security attributes and local pointers (no NvP64) NV_STATUS (*Alloc)(struct _RM_API *pRmApi, NvHandle hClient, NvHandle hParent, - NvHandle *phObject, NvU32 hClass, void *pAllocParams); + NvHandle *phObject, NvU32 hClass, void *pAllocParams, NvU32 paramsSize); // Allocate a resource with default security attributes and local pointers (no NvP64) // and client assigned handle NV_STATUS (*AllocWithHandle)(struct _RM_API *pRmApi, NvHandle hClient, NvHandle hParent, - NvHandle hObject, NvU32 hClass, void *pAllocParams); + NvHandle hObject, NvU32 hClass, void *pAllocParams, NvU32 paramsSize); // Allocate a resource NV_STATUS (*AllocWithSecInfo)(struct _RM_API *pRmApi, NvHandle hClient, NvHandle hParent, - NvHandle *phObject, NvU32 hClass, NvP64 pAllocParams, + NvHandle *phObject, NvU32 hClass, NvP64 pAllocParams, NvU32 paramsSize, NvU32 flags, NvP64 pRightsRequested, API_SECURITY_INFO *pSecInfo); // Free a resource with default security attributes @@ -147,11 +154,11 @@ NV_STATUS (*FreeWithSecInfo)(struct _RM_API *pRmApi, NvHandle hClient, NvHandle hObject, NvU32 flags, API_SECURITY_INFO *pSecInfo); - // Free a list of clients with default security attributes - NV_STATUS (*FreeClientList)(struct _RM_API *pRmApi, NvHandle *phClientList, NvU32 numClients); + // Disables all clients in the list, with default security attributes + NV_STATUS (*DisableClients)(struct _RM_API *pRmApi, NvHandle *phClientList, NvU32 numClients); - // Free a list of clients - NV_STATUS (*FreeClientListWithSecInfo)(struct _RM_API *pRmApi, NvHandle *phClientList, + // Disables all clients in the list + NV_STATUS (*DisableClientsWithSecInfo)(struct _RM_API *pRmApi, NvHandle *phClientList, NvU32 numClients, API_SECURITY_INFO *pSecInfo); // Invoke a control with default security attributes and local pointers (no NvP64) @@ -269,7 +276,7 @@ NV_STATUS rmapiControlCacheGet(NvHandle hClient, NvHandle hObject, NvU32 cmd, void* params, NvU32 paramsSize); NV_STATUS rmapiControlCacheSet(NvHandle hClient, NvHandle hObject, NvU32 cmd, - const void* params, NvU32 paramsSize); + void* params, NvU32 paramsSize); NV_STATUS rmapiControlCacheSetGpuInstForObject(NvHandle hClient, NvHandle hObject, NvU32 gpuInst); void rmapiControlCacheFreeAllCacheForGpu(NvU32 gpuInst); void rmapiControlCacheSetMode(NvU32 mode); @@ -302,7 +309,7 @@ RM_API_CONTEXT *pContext ); -void +void rmapiInitLockInfo ( RM_API *pRmApi, @@ -314,7 +321,7 @@ // RM locking modules: 24-bit group bitmask, 8-bit subgroup id // // Lock acquires are tagged with a RM_LOCK_MODULE_* in order to partition -// the acquires into groups, which allows read-only locks to be +// the acquires into groups, which allows read-only locks to be // enabled / disabled on a per-group basis (via apiLockMask and gpuLockMask // in OBJSYS.) // diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/inc/kernel/rmapi/rmapi_utils.h nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/inc/kernel/rmapi/rmapi_utils.h --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/inc/kernel/rmapi/rmapi_utils.h 2023-10-25 20:20:39.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/inc/kernel/rmapi/rmapi_utils.h 2024-03-05 22:13:03.000000000 +0000 @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 2020-2020 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2020-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -25,6 +25,7 @@ #include "rmapi/rmapi.h" + // // Alloc a client, device and subdevice handle for a gpu // @@ -58,6 +59,7 @@ // // Return the flags and access right associated with this RM control command // -NV_STATUS rmapiutilGetControlInfo(NvU32 cmd, NvU32 *pFlags, NvU32 *pAccessRight); +NV_STATUS rmapiutilGetControlInfo(NvU32 cmd, NvU32 *pFlags, + NvU32 *pAccessRight, NvU32 *pParamsSize); #endif /* RMAPI_UTILS_H */ diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/inc/kernel/rmapi/rs_utils.h nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/inc/kernel/rmapi/rs_utils.h --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/inc/kernel/rmapi/rs_utils.h 2023-10-25 20:20:39.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/inc/kernel/rmapi/rs_utils.h 2024-03-05 22:13:03.000000000 +0000 @@ -46,11 +46,11 @@ MAKE_LIST(ClientHandlesList, NvHandle); #define serverutilGetDerived(pRmClient, hResource, ppBaseRes, type) \ - (clientGetResource(staticCast((pRmClient), RsClient), \ - (hResource), \ - classId(type), \ - (ppBaseRes)) != NV_OK) \ - ? NULL \ + (clientGetResource(staticCast((pRmClient), RsClient), \ + (hResource), \ + classId(type), \ + (ppBaseRes)) != NV_OK) \ + ? NULL \ : dynamicCast(*(ppBaseRes), type) /** @@ -119,9 +119,8 @@ * Get a client pointer from a client handle without taking any locks. * * @param[in] hClient The client to acquire - * @param[out] ppClient Pointer to the RmClient */ -NV_STATUS serverutilGetClientUnderLock(NvHandle hClient, RmClient **ppClient); +RmClient *serverutilGetClientUnderLock(NvHandle hClient); /** * Get a client pointer from a client handle and lock it. diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/inc/kernel/virtualization/common_vgpu_mgr.h nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/inc/kernel/virtualization/common_vgpu_mgr.h --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/inc/kernel/virtualization/common_vgpu_mgr.h 2023-10-25 20:20:39.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/inc/kernel/virtualization/common_vgpu_mgr.h 2024-03-05 22:13:03.000000000 +0000 @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 1993-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 1993-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -36,8 +36,20 @@ #define VGPU_UUID_SIZE NVA081_VM_UUID_SIZE #define VGPU_MAX_GFID 64 #define VGPU_SIGNATURE_SIZE NVA081_VGPU_SIGNATURE_SIZE +#define VGPU_MAX_PLUGIN_CHANNELS 5 #define MAX_VGPU_DEVICES_PER_PGPU NVA081_MAX_VGPU_PER_PGPU +#define SET_GUEST_ID_ACTION_SET 0 +#define SET_GUEST_ID_ACTION_UNSET 1 + +typedef struct +{ + NvU8 action; + NvU32 vmPid; + VM_ID_TYPE vmIdType; + VM_ID guestVmId; +} SET_GUEST_ID_PARAMS; + /* This structure represents the vGPU type's attributes */ typedef struct { @@ -83,6 +95,7 @@ VGPU_TYPE *vgpuTypeInfo, NvU32 gfid, NvU32 *pChidOffset, + NvU32 *pChannelCount, NvHandle hClient, NvU32 numChannels, NvU32 engineFifoListNumEntries, @@ -92,6 +105,7 @@ vgpuMgrFreeSystemChannelIDs(OBJGPU *pGpu, NvU32 gfid, NvU32 *pChidOffset, + NvU32 *pChannelCount, NvHandle hClient, NvU32 engineFifoListNumEntries, FIFO_ENGINE_LIST *engineFifoList); diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/inc/lib/base_utils.h nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/inc/lib/base_utils.h --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/inc/lib/base_utils.h 2023-10-25 20:20:39.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/inc/lib/base_utils.h 2024-03-05 22:13:03.000000000 +0000 @@ -68,6 +68,9 @@ // char * nvU32ToStr(NvU32 value, char *string, NvU32 radix); +/*! Converts unsigned long long hex int to string */ +char * nvU64ToStr(NvU64 value, char *string, NvU32 targedStrLen); + // // Find the string length // diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/inc/lib/protobuf/prb_util.h nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/inc/lib/protobuf/prb_util.h --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/inc/lib/protobuf/prb_util.h 2023-10-25 20:20:40.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/inc/lib/protobuf/prb_util.h 2024-03-05 22:13:03.000000000 +0000 @@ -70,13 +70,13 @@ // #define PRB_REGS_MSG_OVERHEAD 13 -NV_STATUS prbEncGpuRegs(OBJGPU *pGpu, IO_APERTURE *pAperture, NvU64 offset, NvU32 numEntries, PRB_ENCODER *pPrbEnc, const PRB_FIELD_DESC *fieldDesc); +NV_STATUS prbEncGpuRegs(OBJGPU *pGpu, IoAperture *pAperture, NvU64 offset, NvU32 numEntries, PRB_ENCODER *pPrbEnc, const PRB_FIELD_DESC *fieldDesc); NV_STATUS prbEncGpuRegImm(OBJGPU *pGpu, NvU64 offset, NvU32 reg, PRB_ENCODER *pPrbEnc, const PRB_FIELD_DESC *fieldDesc); -NV_STATUS prbEncGpuRegOffset(OBJGPU *pGpu, IO_APERTURE *pAperture, const NvU32 *pOffset, NvU32 numEntries, PRB_ENCODER *pPrbEnc, const PRB_FIELD_DESC *fieldDesc); -NV_STATUS prbEncGpuRegSliceOffset(OBJGPU *pGpu, IO_APERTURE *pAperture, const NvU32 *pOffset, NvU32 numEntries, NvU32 base, PRB_ENCODER *pPrbEnc, const PRB_FIELD_DESC *fieldDesc); -NV_STATUS prbEncGpuRegTbl(OBJGPU *pGpu, IO_APERTURE *pAperture, const PRB_GPU_REG_TABLE *pTbl, NvU32 numEntries, PRB_ENCODER *pPrbEnc, const PRB_FIELD_DESC *fieldDesc); -NV_STATUS prbEncGpuRegSliceTbl(OBJGPU *pGpu, IO_APERTURE *pAperture, const PRB_GPU_REG_TABLE *pTbl, NvU32 numEntries, NvU32 base, PRB_ENCODER *pPrbEnc, const PRB_FIELD_DESC *fieldDesc); -NV_STATUS prbEncGpuRegSliceIndexedTbl(OBJGPU *pGpu, IO_APERTURE *pAperture, const PRB_GPU_REG_INDEXED_TABLE *pTbl, NvU32 numEntries, NvU32 base, NvU32 index, PRB_ENCODER *pPrbEnc, const PRB_FIELD_DESC *fieldDesc); +NV_STATUS prbEncGpuRegOffset(OBJGPU *pGpu, IoAperture *pAperture, const NvU32 *pOffset, NvU32 numEntries, PRB_ENCODER *pPrbEnc, const PRB_FIELD_DESC *fieldDesc); +NV_STATUS prbEncGpuRegSliceOffset(OBJGPU *pGpu, IoAperture *pAperture, const NvU32 *pOffset, NvU32 numEntries, NvU32 base, PRB_ENCODER *pPrbEnc, const PRB_FIELD_DESC *fieldDesc); +NV_STATUS prbEncGpuRegTbl(OBJGPU *pGpu, IoAperture *pAperture, const PRB_GPU_REG_TABLE *pTbl, NvU32 numEntries, PRB_ENCODER *pPrbEnc, const PRB_FIELD_DESC *fieldDesc); +NV_STATUS prbEncGpuRegSliceTbl(OBJGPU *pGpu, IoAperture *pAperture, const PRB_GPU_REG_TABLE *pTbl, NvU32 numEntries, NvU32 base, PRB_ENCODER *pPrbEnc, const PRB_FIELD_DESC *fieldDesc); +NV_STATUS prbEncGpuRegSliceIndexedTbl(OBJGPU *pGpu, IoAperture *pAperture, const PRB_GPU_REG_INDEXED_TABLE *pTbl, NvU32 numEntries, NvU32 base, NvU32 index, PRB_ENCODER *pPrbEnc, const PRB_FIELD_DESC *fieldDesc); NV_STATUS prbEncMem(NvU64 offset, NvU32 numRegs, PRB_ENCODER *pPrbEnc, const PRB_FIELD_DESC *fieldDesc); NV_STATUS prbEncInstMem(NvU64 physAddr, NvU8 *pVirtAddr, NvU32 numWords, PRB_ENCODER *pPrbEnc, const PRB_FIELD_DESC *fieldDesc); NV_STATUS prbEncInstMemImm(NvU64 physAddr, NvU32 data, PRB_ENCODER *pPrbEnc, const PRB_FIELD_DESC *fieldDesc); diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/inc/libraries/containers/btree.h nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/inc/libraries/containers/btree.h --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/inc/libraries/containers/btree.h 2023-10-25 20:20:40.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/inc/libraries/containers/btree.h 2024-03-05 22:13:03.000000000 +0000 @@ -43,7 +43,7 @@ NvU64 keyStart; NvU64 keyEnd; - // private: + // private: NvBool isRed; // !IsRed == IsBlack struct NODE *parent; // tree links struct NODE *left; diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/inc/libraries/containers/list.h nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/inc/libraries/containers/list.h --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/inc/libraries/containers/list.h 2023-10-25 20:20:40.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/inc/libraries/containers/list.h 2024-03-05 22:13:04.000000000 +0000 @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 2015-2015 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2015-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -288,9 +288,11 @@ void *listInsertNew_IMPL(NonIntrusiveList *pList, void *pNext); void *listAppendNew_IMPL(NonIntrusiveList *pList); void *listPrependNew_IMPL(NonIntrusiveList *pList); -void *listInsertValue_IMPL(NonIntrusiveList *pList, void *pNext, void *pValue); -void *listAppendValue_IMPL(NonIntrusiveList *pList, void *pValue); -void *listPrependValue_IMPL(NonIntrusiveList *pList, void *pValue); +void *listInsertValue_IMPL(NonIntrusiveList *pList, + void *pNext, + const void *pValue); +void *listAppendValue_IMPL(NonIntrusiveList *pList, const void *pValue); +void *listPrependValue_IMPL(NonIntrusiveList *pList, const void *pValue); void listInsertExisting_IMPL(IntrusiveList *pList, void *pNext, void *pValue); void listAppendExisting_IMPL(IntrusiveList *pList, void *pValue); void listPrependExisting_IMPL(IntrusiveList *pList, void *pValue); diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/inc/libraries/containers/map.h nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/inc/libraries/containers/map.h --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/inc/libraries/containers/map.h 2023-10-25 20:20:40.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/inc/libraries/containers/map.h 2024-03-05 22:13:04.000000000 +0000 @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 2015-2015 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2015-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -261,7 +261,7 @@ NvU64 mapKey_IMPL(MapBase *pMap, void *pValue); void *mapInsertNew_IMPL(NonIntrusiveMap *pMap, NvU64 key); -void *mapInsertValue_IMPL(NonIntrusiveMap *pMap, NvU64 key, void *pValue); +void *mapInsertValue_IMPL(NonIntrusiveMap *pMap, NvU64 key, const void *pValue); NvBool mapInsertExisting_IMPL(IntrusiveMap *pMap, NvU64 key, void *pValue); void mapRemove_IMPL(NonIntrusiveMap *pMap, void *pValue); void mapRemoveIntrusive_IMPL(MapBase *pMap, void *pValue); diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/inc/libraries/containers/multimap.h nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/inc/libraries/containers/multimap.h --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/inc/libraries/containers/multimap.h 2023-10-25 20:20:40.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/inc/libraries/containers/multimap.h 2024-03-05 22:13:04.000000000 +0000 @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 2018-2018 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2018-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -60,33 +60,33 @@ * */ -#define MAKE_MULTIMAP(multimapTypeName, dataType) \ - typedef struct multimapTypeName##Leaf \ - { \ - dataType data; \ - MultimapNode node; \ - } multimapTypeName##Leaf; \ - MAKE_INTRUSIVE_MAP(multimapTypeName##Submap, multimapTypeName##Leaf, \ - node.submapNode); \ - MAKE_MAP(multimapTypeName##Supermap, multimapTypeName##Submap); \ - typedef union multimapTypeName##Iter \ - { \ - dataType *pValue; \ - MultimapIterBase iter; \ - } multimapTypeName##Iter; \ - typedef union multimapTypeName \ - { \ - CONT_TAG_TYPE(MultimapBase, dataType, multimapTypeName##Iter); \ - struct { MultimapBase base; } real; \ - struct \ - { \ - /* This field simply aligns map with the one in MultimapBase */ \ - CONT_VTABLE_FIELD(MultimapBase); \ - multimapTypeName##Supermap map; \ - } type; \ - CONT_TAG_NON_INTRUSIVE(dataType); \ +#define MAKE_MULTIMAP(multimapTypeName, dataType) \ + typedef struct multimapTypeName##Leaf \ + { \ + dataType data; \ + MultimapNode node; \ + } multimapTypeName##Leaf; \ + MAKE_INTRUSIVE_MAP(multimapTypeName##Submap, multimapTypeName##Leaf, \ + node.submapNode); \ + MAKE_MAP(multimapTypeName##Supermap, multimapTypeName##Submap); \ + typedef union multimapTypeName##Iter \ + { \ + dataType *pValue; \ + MultimapIterBase iter; \ + } multimapTypeName##Iter; \ + typedef union multimapTypeName \ + { \ + CONT_TAG_TYPE(MultimapBase, dataType, multimapTypeName##Iter); \ + struct { MultimapBase base; } real; \ + struct \ + { \ + /* This field simply aligns map with the one in MultimapBase */ \ + CONT_VTABLE_FIELD(MultimapBase); \ + multimapTypeName##Supermap map; \ + } type; \ + CONT_TAG_NON_INTRUSIVE(dataType); \ struct {char _[NV_OFFSETOF(multimapTypeName##Leaf, node)];} *nodeOffset; \ - struct {char _[sizeof(multimapTypeName##Submap)];} *submapSize; \ + struct {char _[sizeof(multimapTypeName##Submap)];} *submapSize; \ } multimapTypeName; #define DECLARE_MULTIMAP(multimapTypeName) \ @@ -214,7 +214,7 @@ multimapItemIterRange(pMultimap, \ multimapFirstItem(pMultimap), multimapLastItem(pMultimap)) -#define multimapItemIterRange(pMultimap, pFirst, pLast) \ +#define multimapItemIterRange(pMultimap, pFirst, pLast) \ CONT_ITER_RANGE(pMultimap, multimapItemIterRange_IMPL, \ CONT_CHECK_ARG(pMultimap, pFirst), CONT_CHECK_ARG(pMultimap, pLast), multimapIsValid_IMPL) @@ -254,8 +254,10 @@ void *multimapInsertItemNew_IMPL(MultimapBase *pBase, NvU64 submapKey, NvU64 itemKey); -void *multimapInsertItemValue_IMPL(MultimapBase *pBase, NvU64 submapKey, - NvU64 itemKey, void *pValue); +void *multimapInsertItemValue_IMPL(MultimapBase *pBase, + NvU64 submapKey, + NvU64 itemKey, + const void *pValue); void *multimapFindItem_IMPL(MultimapBase *pBase, NvU64 submapKey, NvU64 itemKey); diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/inc/libraries/containers/queue.h nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/inc/libraries/containers/queue.h --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/inc/libraries/containers/queue.h 2023-10-25 20:20:40.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/inc/libraries/containers/queue.h 2024-03-05 22:13:04.000000000 +0000 @@ -26,7 +26,7 @@ #include "containers/type_safety.h" #include "nvtypes.h" #include "nvmisc.h" -#include "nvport/nvport.h" +#include "nvport/nvport.h" #include "utils/nvassert.h" #ifdef __cplusplus @@ -96,7 +96,7 @@ circularQueueCapacity_IMPL(&((pQueue)->real)) #define queueIsEmpty(pQueue) \ - circularQueueIsEmpty_IMPL(&((pQueue)->real)) + circularQueueIsEmpty_IMPL(&((pQueue)->real)) #define queuePush(pQueue, pElements, numElements) \ circularQueuePush_IMPL(&(pQueue)->real, \ diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/inc/libraries/containers/ringbuf.h nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/inc/libraries/containers/ringbuf.h --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/inc/libraries/containers/ringbuf.h 1970-01-01 00:00:00.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/inc/libraries/containers/ringbuf.h 2024-03-05 22:13:04.000000000 +0000 @@ -0,0 +1,169 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2022-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ +#ifndef NV_CONTAINERS_RINGBUF_H +#define NV_CONTAINERS_RINGBUF_H + +#include "nvtypes.h" +#include "nvstatus.h" +#include "nvmisc.h" +#include "nvctassert.h" +#include "utils/nvassert.h" +#include "nvport/nvport.h" +#include "containers/type_safety.h" + +typedef struct RingBufBase +{ + NvU64 head; + NvU64 tail; + NvU64 logSz; + NvU8 *arr; +} RingBufBase; + +#define RINGBUF_ARRAY_SIZE(pBuf) (1llu << ((pBuf)->logSz)) + +#define RINGBUF_ARRAY_MASK(pBuf) (RINGBUF_ARRAY_SIZE(pBuf) - 1llu) + +#define MAKE_RINGBUF(containedType, outputType, logSz) \ + typedef struct outputType { \ + union { \ + RingBufBase base; \ + PORT_MEM_ALLOCATOR *pAllocator; \ + }; \ + union { \ + containedType elem[1llu << (logSz)]; \ + NvU8 lgSz[((logSz) < 64) ? (logSz) : -1]; /* Ternary to ensure we get CT error when logSz >= 64 */ \ + }; \ + } outputType + +#define MAKE_RINGBUF_DYNAMIC(containedType, outputType) \ + typedef union outputType { \ + struct { \ + RingBufBase base; \ + PORT_MEM_ALLOCATOR *pAllocator; \ + }; \ + containedType *elem; \ + } outputType + +#if NV_TYPEOF_SUPPORTED + +#define FOR_EACH_IN_RINGBUF(pBuf, idx, ptr) \ + { \ + (idx) = (pBuf)->base.tail; \ + while((idx) != (pBuf)->base.head) \ + { \ + (ptr) = (typeof(&((pBuf)->elem)[0])) &(pBuf)->base.arr[((idx) & RINGBUF_ARRAY_MASK(&((pBuf)->base))) * \ + sizeof(*((pBuf)->elem))]; \ + (idx)++; + +#else + +#define FOR_EACH_IN_RINGBUF(pBuf, idx, ptr) \ + { \ + (idx) = (pBuf)->base.tail; \ + while((idx) != (pBuf)->base.head) \ + { \ + (ptr) = (void *)&(pBuf)->base.arr[((idx) & RINGBUF_ARRAY_MASK(&((pBuf)->base))) * \ + sizeof(*((pBuf)->elem))]; \ + (idx)++; + +#endif // NV_TYPEOF_SUPPORTED + +#define FOR_EACH_END_RINGBUF() \ + } \ + } + + +#define ringbufConstructDynamic(pBuf, logSz, pAlloc) \ + (pBuf->pAllocator = pAlloc, ringbufConstructDynamic_IMPL(&((pBuf)->base), logSz, sizeof(*((pBuf)->elem)), pAlloc)) + +#define ringbufConstruct(pBuf) \ + ringbufConstruct_IMPL(&((pBuf)->base), sizeof((pBuf)->lgSz), (void*)((pBuf)->elem)) + +#define ringbufDestruct(pBuf) \ + ringbufDestruct_IMPL(&((pBuf)->base), ((void*)&((pBuf)->pAllocator)) == ((void*)&((pBuf)->base)) ? NULL : ((pBuf)->pAllocator) ) + +#if NV_TYPEOF_SUPPORTED + +#define ringbufPopN(pBuf, pMax) \ + (typeof(&((pBuf)->elem)[0])) ringbufPopN_IMPL(&((pBuf)->base), sizeof(*((pBuf)->elem)), pMax) + +#define ringbufPeekN(pBuf, pMax) \ + (typeof(&((pBuf)->elem)[0])) ringbufPeekN_IMPL(&((pBuf)->base), sizeof(*((pBuf)->elem)), pMax) + +#define ringbufAppendN(pBuf, pEles, num, bOver) \ + ringbufAppendN_IMPL(&((pBuf)->base), sizeof(*((pBuf)->elem)), (NvU8*)pEles, num, bOver) + +#define ringbufPop(pBuf) \ + (typeof(&((pBuf)->elem)[0])) ringbufPop_IMPL(&((pBuf)->base), sizeof(*((pBuf)->elem))) + +#define ringbufPeek(pBuf) \ + (typeof(&((pBuf)->elem)[0])) ringbufPeek_IMPL(&((pBuf)->base), sizeof(*((pBuf)->elem))) + +#else + +#define ringbufPopN(pBuf, pMax) \ + (void *)ringbufPopN_IMPL(&((pBuf)->base), sizeof(*((pBuf)->elem)), pMax) + +#define ringbufPeekN(pBuf, pMax) \ + (void *)ringbufPeekN_IMPL(&((pBuf)->base), sizeof(*((pBuf)->elem)), pMax) + +#define ringbufAppendN(pBuf, pEles, num, bOver) \ + ringbufAppendN_IMPL(&((pBuf)->base), sizeof(*((pBuf)->elem)), (NvU8*)pEles, num, bOver) + +#define ringbufPop(pBuf) \ + (void *)ringbufPop_IMPL(&((pBuf)->base), sizeof(*((pBuf)->elem))) + +#define ringbufPeek(pBuf) \ + (void *)ringbufPeek_IMPL(&((pBuf)->base), sizeof(*((pBuf)->elem))) + +#endif // NV_TYPEOF_SUPPORTED + +#define ringbufAppend(pBuf, pEle, bOver) \ + ringbufAppend_IMPL(&((pBuf)->base), sizeof(*((pBuf)->elem)), (NvU8*)pEle, bOver) + +#define ringbufCurrentSize(pBuf) \ + ringbufCurrentSize_IMPL(&((pBuf)->base)) + +NvBool ringbufConstructDynamic_IMPL(RingBufBase *pBase, NvU64 logSz, NvU64 eleSz, PORT_MEM_ALLOCATOR *pAlloc); +NvBool ringbufConstruct_IMPL(RingBufBase *pBase, NvU64 logSz, void *arr); +void ringbufDestruct_IMPL(RingBufBase *pBase, void *alloc); +void *ringbufPopN_IMPL(RingBufBase *pBase, NvU64 eleSz, NvU64 *pMax); +void *ringbufPeekN_IMPL(RingBufBase *pBase, NvU64 eleSz, NvU64 *pMax); +NvBool ringbufAppendN_IMPL(RingBufBase *pBase, NvU64 eleSz, NvU8 *pEle, NvU64 num, NvBool bOverwrite); +NvU64 ringbufCurrentSize_IMPL(RingBufBase *pBase); + +static inline void *ringbufPeek_IMPL(RingBufBase *pBase, NvU64 eleSz) +{ + NvU64 max = 1; + return ringbufPeekN_IMPL(pBase, eleSz, &max); +} +static inline void *ringbufPop_IMPL(RingBufBase *pBase, NvU64 eleSz) +{ + NvU64 max = 1; + return ringbufPopN_IMPL(pBase, eleSz, &max); +} +static inline NvBool ringbufAppend_IMPL(RingBufBase *pBase, NvU64 eleSz, NvU8 *pEle, NvBool bOverwrite) +{ + return ringbufAppendN_IMPL(pBase, eleSz, pEle, 1, bOverwrite); +} +#endif diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/inc/libraries/containers/type_safety.h nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/inc/libraries/containers/type_safety.h --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/inc/libraries/containers/type_safety.h 2023-10-25 20:20:40.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/inc/libraries/containers/type_safety.h 2024-03-05 22:13:04.000000000 +0000 @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 2015-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2015-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -147,9 +147,15 @@ elemType *elem; \ iterType *iter -// Argument check uses sizeof to get error message without runtime overhead. +// +// sizeof forces this expression to be evaluated at compile-time only. +// +// The ternary will always evalute true and passthrough the original pValue. +// However, the pointer comparison will generate a compile time warning if +// pValue type differs from the container's element type +// #define CONT_CHECK_ARG(pCont, pValue) \ - (sizeof((pCont)->elem = (pValue)) ? (pValue) : NULL) + (sizeof((pCont)->elem == (pValue)) ? (pValue) : NULL) // // Return checks are more problematic, but typeof is perfect when available. @@ -207,13 +213,13 @@ #else -#define CONT_VTABLE_DECL(contType, iterType) \ - typedef struct \ - { \ - void *(*checkRet)(void *pValue); \ - iterType (*iterRange)(contType *pCont, void *pFirst, void *pLast); \ - iterType (*iterRangeIndex)(contType *pCont, NvU64 first, NvU64 last);\ - } contType##_VTABLE; \ +#define CONT_VTABLE_DECL(contType, iterType) \ + typedef struct \ + { \ + void *(*checkRet)(void *pValue); \ + iterType (*iterRange)(contType *pCont, void *pFirst, void *pLast); \ + iterType (*iterRangeIndex)(contType *pCont, NvU64 first, NvU64 last); \ + } contType##_VTABLE; \ #define CONT_VTABLE_DEFN(contType, contIterRange, contIterRangeIndex) \ static const contType##_VTABLE g_##contType##_VTABLE = \ @@ -223,12 +229,12 @@ contIterRangeIndex, \ } -#define CONT_VTABLE_TAG(contType, elemType, iterType) \ - const struct \ - { \ - elemType *(*checkRet)(void *pValue); \ - iterType (*iterRange)(contType *pCont, void *pFirst, void *pLast); \ - iterType (*iterRangeIndex)(contType *pCont, NvU64 first, NvU64 last);\ +#define CONT_VTABLE_TAG(contType, elemType, iterType) \ + const struct \ + { \ + elemType *(*checkRet)(void *pValue); \ + iterType (*iterRange)(contType *pCont, void *pFirst, void *pLast); \ + iterType (*iterRangeIndex)(contType *pCont, NvU64 first, NvU64 last); \ } *vtable #define CONT_VTABLE_FIELD(contType) const contType##_VTABLE *vtable diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/inc/libraries/containers/vector.h nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/inc/libraries/containers/vector.h --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/inc/libraries/containers/vector.h 1970-01-01 00:00:00.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/inc/libraries/containers/vector.h 2024-03-05 22:13:04.000000000 +0000 @@ -0,0 +1,201 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2015-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ +#ifndef NV_CONTAINERS_VECTOR_H +#define NV_CONTAINERS_VECTOR_H 1 + +#include "containers/type_safety.h" +#include "nvtypes.h" +#include "nvmisc.h" +#include "nvport/nvport.h" +#include "utils/nvassert.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @defgroup NV_CONTAINERS_VECTOR Vector + * + * @brief Sequence of user-defined values. + * + * @details Order of values is not necessarily increasing or sorted, but order is + * preserved across mutation. Please see + * https://en.wikipedia.org/wiki/Sequence for a formal definition. + * + * - Time Complexity: + * * Operations are \b O(1), + * * Unless stated otherwise. + * + * - Memory Usage: + * * \b O(N) memory is required for N values. + * * See @ref mem-ownership for further details. + * + * - Synchronization: + * * \b None. The container is not thread-safe. + * * Locking must be handled by the user if required. + * + */ + +#define MAKE_VECTOR(vectTypeName, dataType) \ + typedef union vectTypeName##Iter \ + { \ + dataType *pValue; \ + VectorIterBase iter; \ + } vectTypeName##Iter; \ + typedef union vectTypeName \ + { \ + VectorWrapper real; \ + CONT_TAG_TYPE(Vector, dataType, vectTypeName##Iter); \ + CONT_TAG_NON_INTRUSIVE(dataType); \ + } vectTypeName + +#define DECLARE_VECTOR(vectTypeName) \ + typedef union vectTypeName##Iter vectTypeName##Iter; \ + typedef union vectTypeName vectTypeName + +typedef struct Vector Vector; +typedef struct VectorIterBase VectorIterBase; +typedef struct VectorWrapper VectorWrapper; + +/** + * Note that the vector values are NvU32 and Iterator values are NvS32, + * so in case there is a need for a vector with over ~2 billion entries + * this might not work. + */ +struct VectorIterBase +{ + void *pValue; + Vector *pVector; + NvS32 nextIndex; + NvS32 prevIndex; + NvS32 firstIndex; + NvS32 lastIndex; + NvBool bForward; +#if PORT_IS_CHECKED_BUILD + NvU32 versionNumber; +#endif +}; + +VectorIterBase vectIterRange_IMPL(Vector *pVector, void *pFirst, void *pLast); +CONT_VTABLE_DECL(Vector, VectorIterBase); + +struct Vector +{ + CONT_VTABLE_FIELD(Vector); + void *pHead; + PORT_MEM_ALLOCATOR *pAllocator; + NvU32 valueSize; + NvU32 capacity; + NvU32 size; +#if PORT_IS_CHECKED_BUILD + NvU32 versionNumber; +#endif +}; + +struct VectorWrapper +{ + Vector base; +}; + +#define vectInit(pVector, pAllocator, capacity) \ + vectInit_IMPL(&((pVector)->real.base), \ + pAllocator, \ + capacity, \ + sizeof(*(pVector)->valueSize)) +#define vectDestroy(pVector) vectDestroy_IMPL(&((pVector)->real.base)) +#define vectCount(pVector) vectCount_IMPL(&((pVector)->real.base)) +#define vectCapacity(pVector) vectCapacity_IMPL(&((pVector)->real.base)) +#define vectIsEmpty(pVector) vectIsEmpty_IMPL(&((pVector)->real.base)) +#define vectAt(pVector, index) \ + CONT_CAST_ELEM((pVector), \ + vectAt_IMPL(&((pVector)->real.base), index), \ + vectIsValid_IMPL) +#define vectInsert(pVector, index, pValue) \ + CONT_CAST_ELEM((pVector), \ + vectInsert_IMPL(&(pVector)->real.base, \ + index, \ + CONT_CHECK_ARG(pVector, pValue)), \ + vectIsValid_IMPL) +#define vectRemove(pVector, index) \ + vectRemove_IMPL(&((pVector)->real.base), index) +#define vectClear(pVector) vectDestroy(pVector) +#define vectAppend(pVector, pValue) \ + CONT_CAST_ELEM((pVector), \ + vectAppend_IMPL(&(pVector)->real.base, \ + CONT_CHECK_ARG(pVector, pValue)), \ + vectIsValid_IMPL) +#define vectPrepend(pVector, pValue) \ + CONT_CAST_ELEM((pVector), \ + vectPrepend_IMPL(&(pVector)->real.base, \ + CONT_CHECK_ARG(pVector, pValue)), \ + vectIsValid_IMPL) +#define vectReserve(pVector, size) \ + vectReserve_IMPL(&((pVector)->real.base), size) +#define vectTrim(pVector, size) vectTrim_IMPL(&((pVector)->real.base), size) + +#define vectIterAll(pVector) \ + vectIterRangeIndex(pVector, 0, vectCount(pVector) - 1) +#define vectIterRangeIndex(pVector, firstIndex, lastIndex) \ + vectIterRange(pVector, \ + vectAt(pVector, firstIndex), \ + vectAt(pVector, lastIndex)) +#define vectIterRange(pVector, pFirst, pLast) \ + CONT_ITER_RANGE(pVector, \ + &vectIterRange_IMPL, \ + CONT_CHECK_ARG(pVector, pFirst), \ + CONT_CHECK_ARG(pVector, pLast), \ + vectIsValid_IMPL) +#define vectIterNext(pIterator) \ + vectIterNext_IMPL(&((pIterator)->iter), (void **)&(pIterator)->pValue) +#define vectIterPrev(pIterator) \ + vectIterPrev_IMPL(&((pIterator)->iter), (void **)&(pIterator)->pValue) + +NV_STATUS vectInit_IMPL(Vector *pVector, + PORT_MEM_ALLOCATOR *pAllocator, + NvU32 capacity, + NvU32 valueSize); +void vectDestroy_IMPL(Vector *pVector); +NvU32 vectCount_IMPL(Vector *pVector); +NvU32 vectCapacity_IMPL(Vector *pVector); +NvBool vectIsEmpty_IMPL(Vector *pVector); + +void *vectAt_IMPL(Vector *pVector, NvU32 index); +void *vectInsert_IMPL(Vector *pVector, NvU32 index, const void *pData); +void vectRemove_IMPL(Vector *pVector, NvU32 index); +void *vectAppend_IMPL(Vector *pVector, const void *pData); +void *vectPrepend_IMPL(Vector *pvector, const void *pData); + +NV_STATUS vectReserve_IMPL(Vector *pVector, NvU32 n); +NV_STATUS vectTrim_IMPL(Vector *pvector, NvU32 n); + +VectorIterBase vectIterRange_IMPL(Vector *pVector, void *pFirst, void *pLast); +NvBool vectIterNext_IMPL(VectorIterBase *pIter, void **ppValue); +NvBool vectIterPrev_IMPL(VectorIterBase *pIter, void **ppValue); + +NvBool vectIsValid_IMPL(void *pVect); + +#ifdef __cplusplus +} +#endif + +#endif // NV_CONTAINERS_VECTOR_H diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/inc/libraries/crashcat/crashcat_engine.h nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/inc/libraries/crashcat/crashcat_engine.h --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/inc/libraries/crashcat/crashcat_engine.h 1970-01-01 00:00:00.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/inc/libraries/crashcat/crashcat_engine.h 2024-03-05 22:11:22.000000000 +0000 @@ -0,0 +1,3 @@ + +#include "g_crashcat_engine_nvoc.h" + diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/inc/libraries/crashcat/crashcat_queue.h nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/inc/libraries/crashcat/crashcat_queue.h --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/inc/libraries/crashcat/crashcat_queue.h 1970-01-01 00:00:00.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/inc/libraries/crashcat/crashcat_queue.h 2024-03-05 22:11:22.000000000 +0000 @@ -0,0 +1,3 @@ + +#include "g_crashcat_queue_nvoc.h" + diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/inc/libraries/crashcat/crashcat_report.h nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/inc/libraries/crashcat/crashcat_report.h --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/inc/libraries/crashcat/crashcat_report.h 1970-01-01 00:00:00.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/inc/libraries/crashcat/crashcat_report.h 2024-03-05 22:11:22.000000000 +0000 @@ -0,0 +1,3 @@ + +#include "g_crashcat_report_nvoc.h" + diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/inc/libraries/crashcat/crashcat_wayfinder.h nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/inc/libraries/crashcat/crashcat_wayfinder.h --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/inc/libraries/crashcat/crashcat_wayfinder.h 1970-01-01 00:00:00.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/inc/libraries/crashcat/crashcat_wayfinder.h 2024-03-05 22:11:22.000000000 +0000 @@ -0,0 +1,3 @@ + +#include "g_crashcat_wayfinder_nvoc.h" + diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/inc/libraries/field_desc.h nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/inc/libraries/field_desc.h --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/inc/libraries/field_desc.h 2023-10-25 20:20:41.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/inc/libraries/field_desc.h 2024-03-05 22:13:04.000000000 +0000 @@ -175,17 +175,17 @@ #define BEGIN_DISCONTIG_FIELD_DESC64(pField) \ pField->regionCount = 0; -#define DRF_DISCONTIG_FIELD_DESC64(pField, drf) \ - do { \ +#define DRF_DISCONTIG_FIELD_DESC64(pField, drf) \ + do { \ NV_ASSERT_CHECKED_PRECOMP(pField->regionCount < NV_FIELD_DESC64_MAX_DISCONTIG_REGIONS); \ - (pField)->regions[pField->regionCount].maskPos = DRF_SHIFTMASK64(drf); \ - (pField)->regions[pField->regionCount].width = (1?drf) - (0?drf) + 1; \ - (pField)->regions[pField->regionCount].shift = DRF_SHIFT64(drf); \ - (pField)->regions[pField->regionCount].offset = DRF_OFFSET64(drf); \ - pField->regionCount ++; \ + (pField)->regions[pField->regionCount].maskPos = DRF_SHIFTMASK64(drf); \ + (pField)->regions[pField->regionCount].width = (1?drf) - (0?drf) + 1; \ + (pField)->regions[pField->regionCount].shift = DRF_SHIFT64(drf); \ + (pField)->regions[pField->regionCount].offset = DRF_OFFSET64(drf); \ + pField->regionCount ++; \ } while(0); -#define END_FIELD_DESC64_DISCONTIGUOUS(pField) +#define END_FIELD_DESC64_DISCONTIGUOUS(pField) #define INIT_FIELD_ENUM(pEnum, drf, count, pEntries) \ diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/inc/libraries/ioaccess/ioaccess.h nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/inc/libraries/ioaccess/ioaccess.h --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/inc/libraries/ioaccess/ioaccess.h 2023-10-25 20:20:41.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/inc/libraries/ioaccess/ioaccess.h 2024-03-05 22:13:04.000000000 +0000 @@ -20,22 +20,18 @@ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * DEALINGS IN THE SOFTWARE. */ +#if (defined(NVRM) || defined(RMCFG_FEATURE_PLATFORM_GSP)) && !defined(NVWATCH) +#include "g_ioaccess_nvoc.h" +#endif + #ifndef _IO_ACCESS_H_ #define _IO_ACCESS_H_ #include "nvtypes.h" #include "nvstatus.h" - -typedef struct IO_DEVICE IO_DEVICE, *PIO_DEVICE; -typedef struct IO_APERTURE IO_APERTURE, *PIO_APERTURE; - -typedef NvU8 ReadReg008Fn(PIO_APERTURE a, NvU32 addr); -typedef NvU16 ReadReg016Fn(PIO_APERTURE a, NvU32 addr); -typedef NvU32 ReadReg032Fn(PIO_APERTURE a, NvU32 addr); -typedef void WriteReg008Fn(PIO_APERTURE a, NvU32 addr, NvV8 value); -typedef void WriteReg016Fn(PIO_APERTURE a, NvU32 addr, NvV16 value); -typedef void WriteReg032Fn(PIO_APERTURE a, NvU32 addr, NvV32 value); -typedef NvBool ValidRegFn(PIO_APERTURE a, NvU32 addr); +#if (defined(NVRM) || defined(RMCFG_FEATURE_PLATFORM_GSP)) && !defined(NVWATCH) +#include "nvoc/prelude.h" +#endif #define REG_DRF_SHIFT(drf) ((0?drf) % 32) #define REG_DRF_MASK(drf) (0xFFFFFFFF>>(31-((1?drf) % 32)+((0?drf) % 32))) @@ -45,6 +41,48 @@ #define REG_DRF_SHIFTMASK(drf) (REG_DRF_MASK(drf)<<(REG_DRF_SHIFT(drf))) #define REG_DRF_WIDTH(drf) ((1?drf) - (0?drf) + 1) +#if (defined(NVRM) || defined(RMCFG_FEATURE_PLATFORM_GSP)) && !defined(NVWATCH) +#define REG_RD08(ap, addr) regaprtReadReg08 (staticCast(ap, RegisterAperture), addr) +#define REG_RD16(ap, addr) regaprtReadReg16 (staticCast(ap, RegisterAperture), addr) +#define REG_RD32(ap, addr) regaprtReadReg32 (staticCast(ap, RegisterAperture), addr) +#define REG_WR08(ap, addr, val) regaprtWriteReg08 (staticCast(ap, RegisterAperture), addr, val) +#define REG_WR16(ap, addr, val) regaprtWriteReg16 (staticCast(ap, RegisterAperture), addr, val) +#define REG_WR32(ap, addr, val) regaprtWriteReg32 (staticCast(ap, RegisterAperture), addr, val) +#define REG_WR32_UC(ap, addr, val) regaprtWriteReg32Uc(staticCast(ap, RegisterAperture), addr, val) +#define REG_VALID(ap, addr) regaprtIsRegValid (staticCast(ap, RegisterAperture), addr) + +NVOC_PREFIX(regaprt) +class RegisterAperture +{ +public: + virtual NvU8 regaprtReadReg08 (RegisterAperture *pAperture, NvU32 addr) = 0; + virtual NvU16 regaprtReadReg16 (RegisterAperture *pAperture, NvU32 addr) = 0; + virtual NvU32 regaprtReadReg32 (RegisterAperture *pAperture, NvU32 addr) = 0; + virtual void regaprtWriteReg08 (RegisterAperture *pAperture, NvU32 addr, NvV8 value) = 0; + virtual void regaprtWriteReg16 (RegisterAperture *pAperture, NvU32 addr, NvV16 value) = 0; + virtual void regaprtWriteReg32 (RegisterAperture *pAperture, NvU32 addr, NvV32 value) = 0; + virtual void regaprtWriteReg32Uc(RegisterAperture *pAperture, NvU32 addr, NvV32 value) = 0; + virtual NvBool regaprtIsRegValid (RegisterAperture *pAperture, NvU32 addr) = 0; +}; + +// +// TODO: Remove the wrapper structure WAR once NVOC supports in-place object construction +// The proxy structure was introduced to avoid major refactoring until the feature is implemented +// Also fix IoAperture getters +// Use the interface class in NVWATCH once NVOC is enabled there +// +#else // (defined(NVRM) || defined(RMCFG_FEATURE_PLATFORM_GSP)) && !defined(NVWATCH) +typedef struct IO_DEVICE IO_DEVICE; +typedef struct IO_APERTURE IO_APERTURE; + +typedef NvU8 ReadReg008Fn(IO_APERTURE *a, NvU32 addr); +typedef NvU16 ReadReg016Fn(IO_APERTURE *a, NvU32 addr); +typedef NvU32 ReadReg032Fn(IO_APERTURE *a, NvU32 addr); +typedef void WriteReg008Fn(IO_APERTURE *a, NvU32 addr, NvV8 value); +typedef void WriteReg016Fn(IO_APERTURE *a, NvU32 addr, NvV16 value); +typedef void WriteReg032Fn(IO_APERTURE *a, NvU32 addr, NvV32 value); +typedef NvBool ValidRegFn(IO_APERTURE *a, NvU32 addr); + #define REG_RD08(ap, addr) (ap)->pDevice->pReadReg008Fn((ap), (addr)) #define REG_RD16(ap, addr) (ap)->pDevice->pReadReg016Fn((ap), (addr)) #define REG_RD32(ap, addr) (ap)->pDevice->pReadReg032Fn((ap), (addr)) @@ -57,26 +95,6 @@ // Get the address of a register given the Aperture and offset. #define REG_GET_ADDR(ap, offset) ((ap)->baseAddress + (offset)) -// -// Macros for register I/O -// - -#define REG_FLD_WR_DRF_NUM(ap,d,r,f,n) REG_WR32(ap,NV##d##r,(REG_RD32(ap,NV##d##r)&~(REG_DRF_MASK(NV##d##r##f)<>REG_DRF_SHIFT(NV ## d ## r ## f))®_DRF_MASK(NV ## d ## r ## f)) -#define REG_FLD_TEST_DRF_DEF(ap,d,r,f,c) (REG_RD_DRF(ap,d, r, f) == NV##d##r##f##c) -#define REG_FLD_TEST_DRF_NUM(ap,d,r,f,n) (REG_RD_DRF(ap,d, r, f) == n) -#define REG_FLD_IDX_TEST_DRF_DEF(ap,d,r,f,c,i) (REG_IDX_RD_DRF(ap, d, r, i, f) == NV##d##r##f##c) - -// Read/write a field or entire register of which there are several copies each accessed via an index -#define REG_IDX_WR_DRF_NUM(ap,d,r,i,f,n) REG_WR32(ap,NV ## d ## r(i), REG_DRF_NUM(d,r,f,n)) -#define REG_IDX_WR_DRF_DEF(ap,d,r,i,f,c) REG_WR32(ap,NV ## d ## r(i), REG_DRF_DEF(d,r,f,c)) -#define REG_FLD_IDX_WR_DRF_NUM(ap,d,r,i,f,n) REG_WR32(ap,NV##d##r(i),(REG_RD32(ap,NV##d##r(i))&~(REG_DRF_MASK(NV##d##r##f)<>REG_DRF_SHIFT(NV ## d ## r ## f))®_DRF_MASK(NV ## d ## r ## f)) -#define REG_RD_DRF_IDX(ap,d,r,f,i) (((REG_RD32(ap,NV ## d ## r))>>REG_DRF_SHIFT(NV ## d ## r ## f(i)))®_DRF_MASK(NV ## d ## r ## f(i))) -#define REG_IDX_OFFSET_RD_DRF(ap,d,r,i,o,f) (((REG_RD32(ap,NV ## d ## r(i,o)))>>REG_DRF_SHIFT(NV ## d ## r ## f))®_DRF_MASK(NV ## d ## r ## f)) - struct IO_DEVICE { ReadReg008Fn *pReadReg008Fn; @@ -91,35 +109,40 @@ struct IO_APERTURE { - PIO_DEVICE pDevice; // Pointer to module specific IO_DEVICE - NvU32 baseAddress; // register base address - NvU32 length; // length of aperture + IO_DEVICE *pDevice; // Pointer to module specific IO_DEVICE + NvU32 baseAddress; // register base address + NvU32 length; // length of aperture }; -//--------------------------------------------------------------------------- -// -// Function prototypes. -// -//--------------------------------------------------------------------------- - -NV_STATUS ioaccessCreateIOAperture -( - IO_APERTURE **ppAperture, - IO_APERTURE *pParentAperture, - IO_DEVICE *pDevice, - NvU32 offset, - NvU32 length -); - NV_STATUS ioaccessInitIOAperture ( IO_APERTURE *pAperture, IO_APERTURE *pParentAperture, - IO_DEVICE *pDevice, + IO_DEVICE *pDevice, NvU32 offset, NvU32 length ); +#endif // (defined(NVRM) || defined(RMCFG_FEATURE_PLATFORM_GSP)) && !defined(NVWATCH) + -void ioaccessDestroyIOAperture(IO_APERTURE *pAperture); +// +// Macros for register I/O +// + +#define REG_FLD_WR_DRF_NUM(ap,d,r,f,n) REG_WR32(ap,NV##d##r,(REG_RD32(ap,NV##d##r)&~(REG_DRF_MASK(NV##d##r##f)<>REG_DRF_SHIFT(NV ## d ## r ## f))®_DRF_MASK(NV ## d ## r ## f)) +#define REG_FLD_TEST_DRF_DEF(ap,d,r,f,c) (REG_RD_DRF(ap,d, r, f) == NV##d##r##f##c) +#define REG_FLD_TEST_DRF_NUM(ap,d,r,f,n) (REG_RD_DRF(ap,d, r, f) == n) +#define REG_FLD_IDX_TEST_DRF_DEF(ap,d,r,f,c,i) (REG_IDX_RD_DRF(ap, d, r, i, f) == NV##d##r##f##c) + +// Read/write a field or entire register of which there are several copies each accessed via an index +#define REG_IDX_WR_DRF_NUM(ap,d,r,i,f,n) REG_WR32(ap,NV ## d ## r(i), REG_DRF_NUM(d,r,f,n)) +#define REG_IDX_WR_DRF_DEF(ap,d,r,i,f,c) REG_WR32(ap,NV ## d ## r(i), REG_DRF_DEF(d,r,f,c)) +#define REG_FLD_IDX_WR_DRF_NUM(ap,d,r,i,f,n) REG_WR32(ap,NV##d##r(i),(REG_RD32(ap,NV##d##r(i))&~(REG_DRF_MASK(NV##d##r##f)<>REG_DRF_SHIFT(NV ## d ## r ## f))®_DRF_MASK(NV ## d ## r ## f)) +#define REG_RD_DRF_IDX(ap,d,r,f,i) (((REG_RD32(ap,NV ## d ## r))>>REG_DRF_SHIFT(NV ## d ## r ## f(i)))®_DRF_MASK(NV ## d ## r ## f(i))) +#define REG_IDX_OFFSET_RD_DRF(ap,d,r,i,o,f) (((REG_RD32(ap,NV ## d ## r(i,o)))>>REG_DRF_SHIFT(NV ## d ## r ## f))®_DRF_MASK(NV ## d ## r ## f)) #endif // _IO_ACCESS_H_ diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/inc/libraries/mmu/gmmu_fmt.h nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/inc/libraries/mmu/gmmu_fmt.h --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/inc/libraries/mmu/gmmu_fmt.h 2023-10-25 20:20:41.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/inc/libraries/mmu/gmmu_fmt.h 2024-03-05 22:13:04.000000000 +0000 @@ -411,7 +411,7 @@ * Should be always the same as version in GMMU_FMT above. */ NvU32 version; - + /*! * Aperture field indicating which physical address space the sublevel resides. */ @@ -441,7 +441,7 @@ * TODO: Wiki link to explain arch differences. */ NV_FIELD_BOOL fldVolatile; - + /*! * PDE_PCF field for V3 format. */ diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/inc/libraries/mmu/mmu_fmt.h nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/inc/libraries/mmu/mmu_fmt.h --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/inc/libraries/mmu/mmu_fmt.h 2023-10-25 20:20:41.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/inc/libraries/mmu/mmu_fmt.h 2024-03-05 22:13:04.000000000 +0000 @@ -41,7 +41,7 @@ // // Separate files for the types as they're included by CTRL definitions -// +// #include "mmu_fmt_types.h" /*! @@ -105,7 +105,7 @@ /*! * Return a level description from the format. Used for Verif. - * + * * @returns const char* string description of the level. */ const char* diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/inc/libraries/mmu/mmu_walk.h nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/inc/libraries/mmu/mmu_walk.h --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/inc/libraries/mmu/mmu_walk.h 2023-10-25 20:20:41.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/inc/libraries/mmu/mmu_walk.h 2024-03-05 22:13:04.000000000 +0000 @@ -152,7 +152,7 @@ /** * No valid aligned 4K PTE state for a 64K PTE * 64K big PTE state indicating that there is no valid 4K aligned PTEs - * + * * @note This is not supported pre Volta. */ MMU_WALK_FILL_NV4K, @@ -376,7 +376,7 @@ * copied. * @param[in] tableSize Size of the current level of PD/PT, in * entries. The offsets into the staging - * buffer are the entry indices taken + * buffer are the entry indices taken * modulo tableSize. * @param[in] entrySize Size of each entry, in bytes */ @@ -509,7 +509,7 @@ * Callback to map the batch of entries. */ MmuWalkCBMapNextEntries *MapNextEntries; - + /*! * Page array granularity of the physical target memory */ @@ -669,7 +669,7 @@ * * Traverse the walker and rewrite the PDEs from the SW state. * This won't trigger any new PDE allocations or state change. - * + * * This call won't affect the PTEs. If needed, support can be added later. * * The VA range must be aligned to the MMU's smallest page size and @@ -750,11 +750,11 @@ NvU32 *pMemSize ); -/*! +/*! * Force frees all page level instances. We may have to force free page levels - * in case of surprise removal. In the surprise removal case, we may end up + * in case of surprise removal. In the surprise removal case, we may end up * with many failed unmappings once the GPU is off the bus. This might leave - * some of the MMU_WALK_LEVEL and MMU_WALK_LEVEL_INST objects to be in an + * some of the MMU_WALK_LEVEL and MMU_WALK_LEVEL_INST objects to be in an * allocated state. This function just iterates over the level instances at * each level and force frees everything ignoring any outstanding valid, sparse * and reserved entries.. diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/inc/libraries/nvlog/nvlog.h nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/inc/libraries/nvlog/nvlog.h --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/inc/libraries/nvlog/nvlog.h 2023-10-25 20:20:41.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/inc/libraries/nvlog/nvlog.h 2024-03-05 22:13:04.000000000 +0000 @@ -188,7 +188,7 @@ /** * @brief Dumps all logs into the the kernel print log * - * @note this will write to the log even if all other prints are disabled, + * @note this will write to the log even if all other prints are disabled, * including external release builds. The output will be base64 encoded and * not decodable without the database, and pollute the logs. Use with caution. * diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/inc/libraries/nvlog/nvlog_printf.h nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/inc/libraries/nvlog/nvlog_printf.h --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/inc/libraries/nvlog/nvlog_printf.h 2023-10-25 20:20:41.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/inc/libraries/nvlog/nvlog_printf.h 2024-03-05 22:13:04.000000000 +0000 @@ -60,12 +60,12 @@ * * @param tag - An identifier to help with offline filtering. Doesn't need to * be defined anywhere. - * @param route - 8bit mask of buffers the print will be routed to. + * @param route - 8bit mask of buffers the print will be routed to. * Use NVLOG_BUFFER_XXX constants * @param level - Level at which to print. Calls with level < NVLOG_LEVEL will * be compiled out. * @param format - printf-like format string - * @param ... - printf arguments + * @param ... - printf arguments */ #define NVLOG_PRINTF(tag, route, level, format, ...) _NVLOG_PRINTF(tag, route, level, format, __VA_ARGS__) diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/inc/libraries/nvoc/object.h nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/inc/libraries/nvoc/object.h --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/inc/libraries/nvoc/object.h 2023-10-25 20:20:42.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/inc/libraries/nvoc/object.h 2024-03-05 22:13:04.000000000 +0000 @@ -62,6 +62,9 @@ //! IP Version value. Temporary until NVOC-style HALs are rolled out. NvU32 ipVersion; + //! flags used to create the object. + NvU32 createFlags; + /*! * @brief Add pChild as a child of this object. * @@ -104,10 +107,10 @@ Object *objGetDirectParent(Object *pObj); }; -// -// IP versioning definitions are temporary until NVOC halspec support is -// finished. -// +// +// IP versioning definitions are temporary until NVOC halspec support is +// finished. +// // IP_VERSION format as defined by the hardware engines. // A _MAJOR value of 0 means the object has no version number. // @@ -118,8 +121,6 @@ #define NV_ODB_IP_VER_MAJOR 31:24 /* R-IVF */ #define IPVersion(pObj) staticCast((pObj), Object)->ipVersion -#define IsIPVersionValid(pObj) (DRF_VAL(_ODB, _IP_VER, _MAJOR, IPVersion(pObj)) != 0) -#define IsIPVersionOrLater(pObj, v0) (IPVersion(pObj) >= (v0)) // v0 .. v1 inclusive #define IsIPVersionInRange(pObj, v0, v1) ((IPVersion(pObj) >= (v0)) && (IPVersion(pObj) <= (v1))) diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/inc/libraries/nvoc/prelude.h nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/inc/libraries/nvoc/prelude.h --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/inc/libraries/nvoc/prelude.h 2023-10-25 20:20:42.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/inc/libraries/nvoc/prelude.h 2024-03-05 22:13:04.000000000 +0000 @@ -106,9 +106,13 @@ * Default behavior * NVOC_OBJ_CREATE_FLAGS_PARENT_HALSPEC_ONLY * Use halspec from parent without adding the new created object the child tree + * NVOC_OBJ_CREATE_FLAGS_IN_PLACE_CONSTRUCT + * Skip memory allocation on object create, assume the argument points to memory + * already allocated. */ #define NVOC_OBJ_CREATE_FLAGS_NONE 0x0000u #define NVOC_OBJ_CREATE_FLAGS_PARENT_HALSPEC_ONLY 0x0001u +#define NVOC_OBJ_CREATE_FLAGS_IN_PLACE_CONSTRUCT 0x0002u /*! * @brief Create and construct a new object by class name. @@ -166,7 +170,7 @@ __nvoc_objCreateDynamic((ppNewObj), staticCast((pParent), Dynamic), \ (pClassInfo), (NVOC_OBJ_CREATE_FLAGS_NONE), ##__VA_ARGS__) #define objCreateDynamicWithFlags(ppNewObj, pParent, pClassInfo, flags, ...) \ - __nvoc_objCreateDynamic((ppNewObj), staticCast((pParent), Dynamic), \ + __nvoc_objCreateDynamic((ppNewObj), staticCast((pParent), Dynamic), \ (pClassInfo), (flags), ##__VA_ARGS__) /*! diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/inc/libraries/nvoc/runtime.h nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/inc/libraries/nvoc/runtime.h --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/inc/libraries/nvoc/runtime.h 2023-10-25 20:20:42.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/inc/libraries/nvoc/runtime.h 2024-03-05 22:13:05.000000000 +0000 @@ -44,6 +44,8 @@ void __nvoc_objDelete(Dynamic *pDynamic); +NV_STATUS __nvoc_handleObjCreateMemAlloc(NvU32 createFlags, NvU32 allocSize, void **ppLocalPtr, void **ppThis); + NV_STATUS __nvoc_objCreateDynamic( Dynamic **pNewObject, Dynamic *pParent, diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/inc/libraries/nvport/cpu.h nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/inc/libraries/nvport/cpu.h --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/inc/libraries/nvport/cpu.h 2023-10-25 20:20:42.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/inc/libraries/nvport/cpu.h 2024-03-05 22:13:05.000000000 +0000 @@ -107,7 +107,7 @@ NvU32 SDBG : 1; /**< IA32_DEBUG_INTERFACE MSR for silicon debug.*/ NvU32 FMA : 1; /**< FMA extensions using YMM state.*/ NvU32 CMPXCHG16B : 1; /**< CMPXCHG8B/CMPXCHG16B Compare and Exchange Bytes*/ - NvU32 xTPRUpdateControl : 1; /** supports changing + NvU32 xTPRUpdateControl : 1; /** supports changing IA32_MISC_ENABLE[bit 23].*/ NvU32 PDCM : 1; /**< Perfmon and Debug Capability: supports the performance and debug feature indication MSR IA32_PERF_CAPABILITIES.*/ @@ -139,7 +139,7 @@ NvU32 DE : 1; /**< Debugging Extensions.*/ NvU32 PSE : 1; /**< Page Size Extension.*/ NvU32 TSC : 1; /**< Time Stamp Counter.*/ - NvU32 MSR : 1; /**< Model Specific Registers RDMSR and WRMSR + NvU32 MSR : 1; /**< Model Specific Registers RDMSR and WRMSR Instructions.*/ NvU32 PAE : 1; /**< Physical Address Extension.*/ NvU32 MCE : 1; /**< Machine Check Exception.*/ @@ -180,7 +180,7 @@ /** * @brief Enum representing Intel family 6 processor model information. - * + * */ typedef enum PORT_CPU_INTEL_FAMILY_6_MODEL { @@ -237,19 +237,19 @@ /// @{ NvU32 DTS : 1; /**< Digital Temperature Sensor is supported if set.*/ NvU32 IntelTurboBoost : 1; /**< Intel Turbo Boost Technology available.*/ - NvU32 ARAT : 1; /**< APIC-Timer-always-running feature is supported + NvU32 ARAT : 1; /**< APIC-Timer-always-running feature is supported if set.*/ - NvU32 PLN : 1; /**< Power limit notification controls are supported + NvU32 PLN : 1; /**< Power limit notification controls are supported if set.*/ - NvU32 ECMD : 1; /**< Clock modulation duty cycle extension is supported + NvU32 ECMD : 1; /**< Clock modulation duty cycle extension is supported if set.*/ NvU32 PTM : 1; /**< Package thermal management is supported if set.*/ - NvU32 HWP : 1; /**< HWP base registers (IA32_PM_ENABLE[bit 0], - IA32_HWP_CAPABILITIES, IA32_HWP_REQUEST, IA32_HWP_STATUS) + NvU32 HWP : 1; /**< HWP base registers (IA32_PM_ENABLE[bit 0], + IA32_HWP_CAPABILITIES, IA32_HWP_REQUEST, IA32_HWP_STATUS) are supported if set.*/ - NvU32 HWPNotification : 1; /**< IA32_HWP_INTERRUPT MSR is supported + NvU32 HWPNotification : 1; /**< IA32_HWP_INTERRUPT MSR is supported if set.*/ - NvU32 HWPActivityWindow : 1; /**< IA32_HWP_REQUEST[bits 41:32] is + NvU32 HWPActivityWindow : 1; /**< IA32_HWP_REQUEST[bits 41:32] is supported if set.*/ NvU32 HWPEPP : 1; /**< HWP_Energy_Performance_Preference. IA32_HWP_REQUEST[bits 31:24] is supported if set.*/ @@ -263,13 +263,13 @@ if set.*/ NvU32 HWPPECI : 1; /**< HWP PECI override is supported if set.*/ NvU32 FLEXHWP : 1; /**< Flexible HWP is supported if set.*/ - NvU32 FAM : 1; /**< Fast access mode for the IA32_HWP_REQUEST MSR is + NvU32 FAM : 1; /**< Fast access mode for the IA32_HWP_REQUEST MSR is supported if set.*/ NvU32 ILPHWPRequest : 1; /**< Ignoring Idle Logical Processor HWP request is supported if set.*/ NvU32 NoOfInterruptThresholdsInDTS : 4; /**< Number of Interrupt Thresholds in Digital Thermal Sensor.*/ - NvU32 HCFC : 1; /**< Hardware Coordination Feedback Capability + NvU32 HCFC : 1; /**< Hardware Coordination Feedback Capability (Presence of IA32_MPERF and IA32_APERF). The capability to provide a measure of delivered processor performance (since last reset of the counters), as a percentage of the @@ -283,7 +283,7 @@ } PORT_CPU_INTEL_TPM_FEATURES; /** - * @brief Structure representing Intel Processor's Architecture Performance + * @brief Structure representing Intel Processor's Architecture Performance * monitering features broken down into individual bit fields. */ typedef struct PORT_CPU_INTEL_ARCH_PERF_MONITOR @@ -296,10 +296,10 @@ NvU32 bitWidthOfGPCounters; /** Bit width of general-purpose, performance monitoring counter.*/ NvU32 coreCycleEvent : 1; /**< Core cycle event available if 1.*/ - NvU32 instructionRetiredEvent : 1; /**< Instruction retired event + NvU32 instructionRetiredEvent : 1; /**< Instruction retired event available if 1.*/ NvU32 referenceCycelEvent : 1; /**< Reference cycles event available if 1.*/ - NvU32 lastLevelCacheRefEvent : 1; /**< Last-level cache reference event + NvU32 lastLevelCacheRefEvent : 1; /**< Last-level cache reference event available if 1.*/ NvU32 lastLevelCacheMissEvent : 1; /**< Last-level cache misses event not available if 1.*/ @@ -309,8 +309,8 @@ not available if 1.*/ NvU32 noOfFixedFuncPerfCounters; /**< Number of fixed-function performance counters (if Version ID > 1).*/ - NvU32 bitWidthOfFixedFuncPerfCounters; /**< Bit width of fixed-function - performance counters + NvU32 bitWidthOfFixedFuncPerfCounters; /**< Bit width of fixed-function + performance counters (if Version ID > 1).*/ /// @} } PORT_CPU_INTEL_ARCH_PERF_MONITOR; @@ -335,7 +335,7 @@ PORT_CPU_INTEL_X86_FEATURES features; /**< General Features.*/ PORT_CPU_INTEL_TPM_FEATURES tpmFeatures; /**< Thermal and Power Management Features.*/ - PORT_CPU_INTEL_ARCH_PERF_MONITOR archPerfMonitor; /**< Architecture + PORT_CPU_INTEL_ARCH_PERF_MONITOR archPerfMonitor; /**< Architecture Performance Monitoring Features.*/ /// @} @@ -526,7 +526,7 @@ /** * @brief Retrieve the current value and frequency of the performance counter * - * @param[out] pFreq A pointer to a variable to which this routine writes the + * @param[out] pFreq A pointer to a variable to which this routine writes the * performance counter frequency, in ticks per second. * This parameter is optional and can be NULL if the caller * does not need the counter frequency value. diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/inc/libraries/nvport/crypto.h nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/inc/libraries/nvport/crypto.h --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/inc/libraries/nvport/crypto.h 2023-10-25 20:20:42.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/inc/libraries/nvport/crypto.h 2024-03-05 22:13:05.000000000 +0000 @@ -46,21 +46,21 @@ * * True random numbers are generated from hardware, and as such are completely * nondeterministic. There is no support for setting a seed, and you can expect - * the output to always be different. Unlike pseudorandom numbers, true random + * the output to always be different. Unlike pseudorandom numbers, true random * output will always vary across different platforms. * * These numbers are suitable for security sensitive and cryptography operations. * * In case of kernelmode code, the entropy pool will contain bits that are not * available to usermode clients. As a consequence, a usermode client cannot - * deplete the entropy pool to lower the security + * deplete the entropy pool to lower the security * - * @note Unless ending with the "-Blocking" suffix, all functions are - * non-blocking. With regards to True Random numbers, this has a consequence + * @note Unless ending with the "-Blocking" suffix, all functions are + * non-blocking. With regards to True Random numbers, this has a consequence * that if there are insufficient bits in the entropy pool, they will be used - * to seed a custom PRNG which will provide the final output. A blocking + * to seed a custom PRNG which will provide the final output. A blocking * version of some functions may be available as an extended function. - * + * * @note As a general rule, you should always use the non-blocking version of a * function, unless ALL the following conditions are satisfied: * - First time booting a clean OS @@ -114,8 +114,8 @@ * @warning These objects are not Cryptographically Secure, and thus not * appropriate for any security sensitive operations. Use "True" random instead. * - * The same seed will always result in the same sequence returned by - * @ref portCryptoPseudoRandomGeneratorGetU32, + * The same seed will always result in the same sequence returned by + * @ref portCryptoPseudoRandomGeneratorGetU32, * @ref portCryptoPseudoRandomGeneratorGetU64 and * @ref portCryptoPseudoRandomGeneratorFillBuffer. This behavior is consistent * across all platforms. The following code will always print the same thing: @@ -131,10 +131,10 @@ * * @return NULL if the construction failed, a PRNG object otherwise. * - */ -PORT_CRYPTO_PRNG *portCryptoPseudoRandomGeneratorCreate(NvU64 seed); + */ +PORT_CRYPTO_PRNG *portCryptoPseudoRandomGeneratorCreate(NvU64 seed); /** - * @brief Destroys an object created with + * @brief Destroys an object created with * @ref portCryptoPseudoRandomGeneratorCreate * */ @@ -153,7 +153,7 @@ * @brief Returns a 64bit pseudorandom number from a given PRNG. * * @warning The numbers generated in this way are not appropriate for security - * sensitive operations. Use @ref portCryptoExTrueRandomGetU64 instead. + * sensitive operations. Use @ref portCryptoExTrueRandomGetU64 instead. * * @param [in] pPrng - Generator object. If NULL, the default one will be used * @@ -164,7 +164,7 @@ * PRNG * * @warning The numbers generated in this way are not appropriate for security - * sensitive operations. Use @ref portCryptoExTrueRandomFillBuffer instead. + * sensitive operations. Use @ref portCryptoExTrueRandomFillBuffer instead. * * @param [in] pPrng - Generator object. If NULL, the default one will be used * @@ -177,7 +177,7 @@ /** * @brief Sets the PRNG seed of the global generator * - * The same seed will always result in the same sequence returned by + * The same seed will always result in the same sequence returned by * @ref portCryptoPseudoRandomGetU32, @ref portCryptoPseudoRandomGetU64 and * @ref portCryptoPseudoRandomFillBuffer. This behavior is consistent across * all platforms. The following code will print the same thing on all platforms: @@ -197,7 +197,7 @@ * a NULL generator object. * * @warning The numbers generated in this way are not appropriate for security - * sensitive operations. Use @ref portCryptoExTrueRandomGetU32 instead. + * sensitive operations. Use @ref portCryptoExTrueRandomGetU32 instead. * */ NvU32 portCryptoPseudoRandomGetU32(void); @@ -208,7 +208,7 @@ * a NULL generator object. * * @warning The numbers generated in this way are not appropriate for security - * sensitive operations. Use @ref portCryptoExTrueRandomGetU64 instead. + * sensitive operations. Use @ref portCryptoExTrueRandomGetU64 instead. * */ NvU64 portCryptoPseudoRandomGetU64(void); @@ -219,7 +219,7 @@ * with a NULL generator object. * * @warning The numbers generated in this way are not appropriate for security - * sensitive operations. Use @ref portCryptoExTrueRandomFillBuffear instead. + * sensitive operations. Use @ref portCryptoExTrueRandomFillBuffear instead. * * @return NV_OK if successful; * NV_ERR_INVALID_POINTER if pBuffer is NULL; @@ -276,8 +276,8 @@ * * @note This function does not block, but rather combines the bits from the * entropy pool with a PRNG to produce a random output of desired width. - * This is considered safe for most cryptographic applications. You can use - * @ref portCryptoExTrueRandomGetU32Blocking for a guaranteed high entropy output. + * This is considered safe for most cryptographic applications. You can use + * @ref portCryptoExTrueRandomGetU32Blocking for a guaranteed high entropy output. */ NvU32 portCryptoExTrueRandomGetU32(void); #define portCryptoExTrueRandomGetU32_SUPPORTED 0 @@ -285,9 +285,9 @@ * @brief Returns a 64bit random number * * @note This function does not block, but rather combines the bits from the - * entropy pool with a PRNG to produce a random output of desired width. + * entropy pool with a PRNG to produce a random output of desired width. * This is considered safe for most cryptographic applications. You can use - * @ref portCryptoExTrueRandomGetU64Blocking for a guaranteed high entropy output. + * @ref portCryptoExTrueRandomGetU64Blocking for a guaranteed high entropy output. */ NvU64 portCryptoExTrueRandomGetU64(void); #define portCryptoExTrueRandomGetU64_SUPPORTED 0 @@ -296,9 +296,9 @@ * * @note This function does not block, but rather combines the bits from the * entropy pool with a PRNG to produce a random output of desired width. This is - * considered safe for most cryptographic applications. You can use + * considered safe for most cryptographic applications. You can use * @ref portCryptoExTrueRandomFillBufferBlocking for a guaranteed high entropy - * output. + * output. * * @return NV_OK if successful; * NV_ERR_INVALID_POINTER if pBuffer is NULL; diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/inc/libraries/nvport/inline/memory_tracking.h nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/inc/libraries/nvport/inline/memory_tracking.h --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/inc/libraries/nvport/inline/memory_tracking.h 2023-10-25 20:20:43.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/inc/libraries/nvport/inline/memory_tracking.h 2024-03-05 22:13:05.000000000 +0000 @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 2014-2020 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2014-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -32,6 +32,24 @@ #ifndef _NVPORT_MEMORY_INTERNAL_H_ #define _NVPORT_MEMORY_INTERNAL_H_ +#define portMemExTrackingGetActiveStats_SUPPORTED PORT_MEM_TRACK_USE_COUNTER +#define portMemExTrackingGetTotalStats_SUPPORTED PORT_MEM_TRACK_USE_COUNTER +#define portMemExTrackingGetPeakStats_SUPPORTED PORT_MEM_TRACK_USE_COUNTER +#define portMemExTrackingGetNext_SUPPORTED \ + (PORT_MEM_TRACK_USE_FENCEPOSTS & PORT_MEM_TRACK_USE_ALLOCLIST) +#define portMemExTrackingGetHeapSize_SUPPORTED (NVOS_IS_LIBOS) +// +// portMemExTrackingGetAllocUsableSize provides higher-fidelity tracking at the +// expense of higher runtime overhead, due to additional function calls in the +// portMemAlloc path. It is only enabled by default in debug ("checked") builds for +// this reason. +// +#define portMemExTrackingGetAllocUsableSize_SUPPORTED (PORT_IS_CHECKED_BUILD && NVOS_IS_LIBOS) + +#define portMemExValidate_SUPPORTED 0 +#define portMemExValidateAllocations_SUPPORTED 0 +#define portMemExFreeAll_SUPPORTED 0 + /** @brief Untracked paged memory allocation, platform specific */ void *_portMemAllocPagedUntracked(NvLength lengthBytes); /** @brief Untracked nonpaged memory allocation, platform specific */ @@ -45,7 +63,7 @@ #if PORT_MEM_TRACK_USE_LIMIT /** @brief Initialize per VF tracking limit **/ -void portMemInitializeAllocatorTrackingLimit(NvU32 pid, NvU64 heapSize, NvBool bLimitEnabled); +void portMemInitializeAllocatorTrackingLimit(NvU32 pid, NvLength limit, NvBool bLimitEnabled); #endif typedef struct PORT_MEM_COUNTER @@ -61,7 +79,6 @@ typedef struct PORT_MEM_FENCE_HEAD { PORT_MEM_ALLOCATOR *pAllocator; - NvLength blockSize; NvU32 magic; } PORT_MEM_FENCE_HEAD; @@ -80,8 +97,8 @@ #if PORT_MEM_TRACK_USE_CALLERINFO_IP -typedef NvU64 PORT_MEM_CALLERINFO; -#define PORT_MEM_CALLERINFO_MAKE ((NvU64)portUtilGetIPAddress()) +typedef NvUPtr PORT_MEM_CALLERINFO; +#define PORT_MEM_CALLERINFO_MAKE portUtilGetIPAddress() #else // PORT_MEM_TRACK_USE_CALLERINFO_IP @@ -141,8 +158,8 @@ #define portMemAllocatorCreateOnExistingBlock(pMem, size) \ portMemAllocatorCreateOnExistingBlock_CallerInfo(pMem, size, PORT_MEM_CALLERINFO_MAKE) #if portMemExAllocatorCreateLockedOnExistingBlock_SUPPORTED -#define portMemExAllocatorCreateLockedOnExistingBlock(pMem, size, pLock) \ - portMemExAllocatorCreateLockedOnExistingBlock_CallerInfo(pMem, size, pLock,\ +#define portMemExAllocatorCreateLockedOnExistingBlock(pMem, size, pLock) \ + portMemExAllocatorCreateLockedOnExistingBlock_CallerInfo(pMem, size, pLock, \ PORT_MEM_CALLERINFO_MAKE) #endif //portMemExAllocatorCreateLockedOnExistingBlock_SUPPORTED #else @@ -151,8 +168,30 @@ #if PORT_MEM_TRACK_USE_FENCEPOSTS || PORT_MEM_TRACK_USE_ALLOCLIST || PORT_MEM_TRACK_USE_CALLERINFO || PORT_MEM_TRACK_USE_LIMIT + +// +// The blockSize of the allocation can be tracked in 1 of 2 places, +// depending on build configuration. To reduce per-alloc memory waste in +// allocating multiple fields for the same data, the following is the +// order in which they are preferred at compile time: +// +// 1. portMemExTrackingGetAllocUsableSize - the underlying malloc +// implementation has a function to get the allocation size from allocated +// pointer. No memory will be allocated in the PORT_MEM_HEADER to track the +// block size. +// 2. PORT_MEM_HEADER::blockSize - used when fenceposts or per-GFID limit +// tracking is enabled and portMemExTrackingGetAllocUsableSize is not +// available. +// +#define PORT_MEM_HEADER_HAS_BLOCK_SIZE \ + !PORT_IS_FUNC_SUPPORTED(portMemExTrackingGetAllocUsableSize) && \ + (PORT_MEM_TRACK_USE_FENCEPOSTS || PORT_MEM_TRACK_USE_LIMIT) + typedef struct PORT_MEM_HEADER { +#if PORT_MEM_HEADER_HAS_BLOCK_SIZE + NvLength blockSize; +#endif #if PORT_MEM_TRACK_USE_CALLERINFO PORT_MEM_CALLERINFO callerInfo; #endif @@ -163,8 +202,7 @@ PORT_MEM_FENCE_HEAD fence; #endif #if PORT_MEM_TRACK_USE_LIMIT - NvU64 blockSize; - NvU32 pid; + NV_DECLARE_ALIGNED(NvU32 pid, 8); #endif } PORT_MEM_HEADER; @@ -178,13 +216,18 @@ #define PORT_MEM_ADD_HEADER_PTR(p) ((PORT_MEM_HEADER*)p + 1) #define PORT_MEM_SUB_HEADER_PTR(p) ((PORT_MEM_HEADER*)p - 1) #define PORT_MEM_STAGING_SIZE (sizeof(PORT_MEM_HEADER)+sizeof(PORT_MEM_FOOTER)) - #else -#define PORT_MEM_ADD_HEADER_PTR(p) p -#define PORT_MEM_SUB_HEADER_PTR(p) p -#define PORT_MEM_STAGING_SIZE 0 +#define PORT_MEM_ADD_HEADER_PTR(p) p +#define PORT_MEM_SUB_HEADER_PTR(p) p +#define PORT_MEM_STAGING_SIZE 0 +#define PORT_MEM_HEADER_HAS_BLOCK_SIZE 0 #endif +#define PORT_MEM_TRACK_ALLOC_SIZE \ + PORT_MEM_TRACK_USE_COUNTER && \ + (PORT_IS_FUNC_SUPPORTED(portMemExTrackingGetAllocUsableSize) || \ + PORT_MEM_HEADER_HAS_BLOCK_SIZE) + struct PORT_MEM_ALLOCATOR_TRACKING { PORT_MEM_ALLOCATOR *pAllocator; @@ -203,17 +246,6 @@ #endif }; - -#define portMemExTrackingGetActiveStats_SUPPORTED PORT_MEM_TRACK_USE_COUNTER -#define portMemExTrackingGetTotalStats_SUPPORTED PORT_MEM_TRACK_USE_COUNTER -#define portMemExTrackingGetPeakStats_SUPPORTED PORT_MEM_TRACK_USE_COUNTER -#define portMemExTrackingGetNext_SUPPORTED \ - (PORT_MEM_TRACK_USE_FENCEPOSTS & PORT_MEM_TRACK_USE_ALLOCLIST) - -#define portMemExValidate_SUPPORTED 0 -#define portMemExValidateAllocations_SUPPORTED 0 -#define portMemExFreeAll_SUPPORTED 0 - /// @brief Actual size of an allocator structure, including internals #define PORT_MEM_ALLOCATOR_SIZE \ (sizeof(PORT_MEM_ALLOCATOR) + sizeof(PORT_MEM_ALLOCATOR_TRACKING)) @@ -282,11 +314,11 @@ #define _PORT_CEIL_NO_UNDERFLOW(a, b) (NV_DIV_AND_CEIL(b + a, b) - 1) /// @brief Required additional size for a given number of chunks -#define PORT_MEM_PREALLOCATED_BLOCK_SIZE_FOR_NONGRATIS_CHUNKS(num_chunks) \ - ((num_chunks > PORT_MEM_PREALLOCATED_BLOCK_CHUNKS_GRATIS) \ - ? _PORT_CEIL_NO_UNDERFLOW(num_chunks - PORT_MEM_PREALLOCATED_BLOCK_CHUNKS_GRATIS,\ - 4*PORT_MEM_BITVECTOR_CHUNK_SIZE) \ - * PORT_MEM_BITVECTOR_CHUNK_SIZE \ +#define PORT_MEM_PREALLOCATED_BLOCK_SIZE_FOR_NONGRATIS_CHUNKS(num_chunks) \ + ((num_chunks > PORT_MEM_PREALLOCATED_BLOCK_CHUNKS_GRATIS) \ + ? _PORT_CEIL_NO_UNDERFLOW(num_chunks - PORT_MEM_PREALLOCATED_BLOCK_CHUNKS_GRATIS, \ + 4*PORT_MEM_BITVECTOR_CHUNK_SIZE) \ + * PORT_MEM_BITVECTOR_CHUNK_SIZE \ : 0) /// @brief Total required bookkeeping size for a block of given useful size diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/inc/libraries/nvport/inline/safe_generic.h nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/inc/libraries/nvport/inline/safe_generic.h --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/inc/libraries/nvport/inline/safe_generic.h 2023-10-25 20:20:43.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/inc/libraries/nvport/inline/safe_generic.h 2024-03-05 22:13:06.000000000 +0000 @@ -138,20 +138,20 @@ #define PORT_SAFE_CAST(a, b, t) \ ((a < PORT_SAFE_MIN(t) || a > PORT_SAFE_MAX(t)) ? \ - NV_FALSE : \ + NV_FALSE : \ ((b = (Nv##t) a), NV_TRUE)) -#define PORT_SAFE_DEFINE_MATH_FUNC(_op_, _US_, _size_) \ - PORT_SAFE_INLINE NvBool \ - portSafe##_op_##_US_##_size_ \ - ( \ - Nv##_US_##_size_ x, \ - Nv##_US_##_size_ y, \ - Nv##_US_##_size_ *pRes \ - ) \ - { \ - return PORT_EXPAND(PORT_SAFE_##_op_##_IMPL_##_US_)(x, y, pRes, _size_);\ +#define PORT_SAFE_DEFINE_MATH_FUNC(_op_, _US_, _size_) \ + PORT_SAFE_INLINE NvBool \ + portSafe##_op_##_US_##_size_ \ + ( \ + Nv##_US_##_size_ x, \ + Nv##_US_##_size_ y, \ + Nv##_US_##_size_ *pRes \ + ) \ + { \ + return PORT_EXPAND(PORT_SAFE_##_op_##_IMPL_##_US_)(x, y, pRes, _size_); \ } diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/inc/libraries/nvport/inline/sync_tracking.h nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/inc/libraries/nvport/inline/sync_tracking.h --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/inc/libraries/nvport/inline/sync_tracking.h 2023-10-25 20:20:43.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/inc/libraries/nvport/inline/sync_tracking.h 2024-03-05 22:13:06.000000000 +0000 @@ -56,18 +56,18 @@ #else -#define portSyncInitialize() \ - do { \ +#define portSyncInitialize() \ + do { \ portDbgPrintf("SYNC-DBG (%s:%d): portSyncInitialize() ", __FILE__, __LINE__); \ - portSyncInitialize(); \ - portDbgPrintf(" - Done;\n"); \ + portSyncInitialize(); \ + portDbgPrintf(" - Done;\n"); \ } while (0) -#define portSyncShutdown() \ - do { \ +#define portSyncShutdown() \ + do { \ portDbgPrintf("SYNC-DBG (%s:%d): portSyncShutdown() ", __FILE__, __LINE__); \ - portSyncShutdown(); \ - portDbgPrintf(" - Done;\n"); \ + portSyncShutdown(); \ + portDbgPrintf(" - Done;\n"); \ } while (0) @@ -85,125 +85,125 @@ } -#define portSyncSpinlockInitialize(pSpinlock) \ +#define portSyncSpinlockInitialize(pSpinlock) \ (portDbgPrintf("SYNC-DBG (%s:%d): portSyncSpinlockInitialize(%p) - ", \ - __FILE__, __LINE__, pSpinlock),\ + __FILE__, __LINE__, pSpinlock), \ _syncPrintReturnStatus(portSyncSpinlockInitialize(pSpinlock))) -#define portSyncSpinlockCreate(pAllocator) \ +#define portSyncSpinlockCreate(pAllocator) \ (portDbgPrintf("SYNC-DBG (%s:%d): portSyncSpinlockCreate(%p) - ", \ - __FILE__, __LINE__, pAllocator),\ + __FILE__, __LINE__, pAllocator), \ _syncPrintReturnPtr(portSyncSpinlockCreate(pAllocator))) -#define portSyncSpinlockDestroy(pSpinlock) \ - do { \ - portDbgPrintf("SYNC-DBG (%s:%d): portSyncSpinlockDestroy(%p) ",\ - __FILE__, __LINE__, pSpinlock); \ - portSyncSpinlockDestroy(pSpinlock); \ - portDbgPrintf(" - Done;\n"); \ +#define portSyncSpinlockDestroy(pSpinlock) \ + do { \ + portDbgPrintf("SYNC-DBG (%s:%d): portSyncSpinlockDestroy(%p) ", \ + __FILE__, __LINE__, pSpinlock); \ + portSyncSpinlockDestroy(pSpinlock); \ + portDbgPrintf(" - Done;\n"); \ } while (0) -#define portSyncSpinlockAcquire(pSpinlock) \ - do { \ - portDbgPrintf("SYNC-DBG (%s:%d): portSyncSpinlockAcquire(%p) ",\ - __FILE__, __LINE__, pSpinlock); \ - portSyncSpinlockAcquire(pSpinlock); \ - portDbgPrintf(" - Done;\n"); \ +#define portSyncSpinlockAcquire(pSpinlock) \ + do { \ + portDbgPrintf("SYNC-DBG (%s:%d): portSyncSpinlockAcquire(%p) ", \ + __FILE__, __LINE__, pSpinlock); \ + portSyncSpinlockAcquire(pSpinlock); \ + portDbgPrintf(" - Done;\n"); \ } while (0) -#define portSyncSpinlockRelease(pSpinlock) \ - do { \ - portDbgPrintf("SYNC-DBG (%s:%d): portSyncSpinlockRelease(%p) ",\ - __FILE__, __LINE__, pSpinlock); \ - portSyncSpinlockRelease(pSpinlock); \ - portDbgPrintf(" - Done;\n"); \ +#define portSyncSpinlockRelease(pSpinlock) \ + do { \ + portDbgPrintf("SYNC-DBG (%s:%d): portSyncSpinlockRelease(%p) ", \ + __FILE__, __LINE__, pSpinlock); \ + portSyncSpinlockRelease(pSpinlock); \ + portDbgPrintf(" - Done;\n"); \ } while (0) -#define portSyncMutexInitialize(pMutex) \ +#define portSyncMutexInitialize(pMutex) \ (portDbgPrintf("SYNC-DBG (%s:%d): portSyncMutexInitialize(%p) - ", \ - __FILE__, __LINE__, pMutex),\ + __FILE__, __LINE__, pMutex), \ _syncPrintReturnStatus(portSyncMutexInitialize(pMutex))) -#define portSyncMutexCreate(pAllocator) \ +#define portSyncMutexCreate(pAllocator) \ (portDbgPrintf("SYNC-DBG (%s:%d): portSyncMutexCreate(%p) - ", \ - __FILE__, __LINE__, pAllocator),\ + __FILE__, __LINE__, pAllocator), \ _syncPrintReturnPtr(portSyncMutexCreate(pAllocator))) -#define portSyncMutexDestroy(pMutex) \ - do { \ - portDbgPrintf("SYNC-DBG (%s:%d): portSyncMutexDestroy(%p) ",\ - __FILE__, __LINE__, pMutex); \ - portSyncMutexDestroy(pMutex); \ - portDbgPrintf(" - Done;\n"); \ - } while (0) - -#define portSyncMutexAcquire(pMutex) \ - do { \ - portDbgPrintf("SYNC-DBG (%s:%d): portSyncMutexAcquire(%p) ",\ - __FILE__, __LINE__, pMutex); \ - portSyncMutexAcquire(pMutex); \ - portDbgPrintf(" - Done;\n"); \ - } while (0) - -#define portSyncMutexRelease(pMutex) \ - do { \ - portDbgPrintf("SYNC-DBG (%s:%d): portSyncMutexRelease(%p) ",\ - __FILE__, __LINE__, pMutex); \ - portSyncMutexRelease(pMutex); \ - portDbgPrintf(" - Done;\n"); \ +#define portSyncMutexDestroy(pMutex) \ + do { \ + portDbgPrintf("SYNC-DBG (%s:%d): portSyncMutexDestroy(%p) ", \ + __FILE__, __LINE__, pMutex); \ + portSyncMutexDestroy(pMutex); \ + portDbgPrintf(" - Done;\n"); \ + } while (0) + +#define portSyncMutexAcquire(pMutex) \ + do { \ + portDbgPrintf("SYNC-DBG (%s:%d): portSyncMutexAcquire(%p) ", \ + __FILE__, __LINE__, pMutex); \ + portSyncMutexAcquire(pMutex); \ + portDbgPrintf(" - Done;\n"); \ + } while (0) + +#define portSyncMutexRelease(pMutex) \ + do { \ + portDbgPrintf("SYNC-DBG (%s:%d): portSyncMutexRelease(%p) ", \ + __FILE__, __LINE__, pMutex); \ + portSyncMutexRelease(pMutex); \ + portDbgPrintf(" - Done;\n"); \ } while (0) -#define portSyncMutexAcquireConditional(pMutex) \ +#define portSyncMutexAcquireConditional(pMutex) \ (portDbgPrintf("SYNC-DBG (%s:%d): portSyncMutexAcquireConditional(%p) - ", \ - __FILE__, __LINE__, pMutex),\ - (portSyncMutexAcquireConditional(pMutex) ? \ + __FILE__, __LINE__, pMutex), \ + (portSyncMutexAcquireConditional(pMutex) ? \ (portDbgPrintf("TRUE\n"),NV_TRUE) : (portDbgPrintf("FALSE\n"),NV_FALSE))) -#define portSyncSemaphoreInitialize(pSemaphore, s, l) \ +#define portSyncSemaphoreInitialize(pSemaphore, s, l) \ (portDbgPrintf("SYNC-DBG (%s:%d): portSyncSemaphoreInitialize(%p, %u, %u) - ", \ - __FILE__, __LINE__, pSemaphore, s, l),\ + __FILE__, __LINE__, pSemaphore, s, l), \ _syncPrintReturnStatus(portSyncSemaphoreInitialize(pSemaphore, s, l))) -#define portSyncSemaphoreCreate(pAllocator, s, l) \ +#define portSyncSemaphoreCreate(pAllocator, s, l) \ (portDbgPrintf("SYNC-DBG (%s:%d): portSyncSemaphoreCreate(%p, %u, %u) - ", \ - __FILE__, __LINE__, pAllocator, s, l),\ + __FILE__, __LINE__, pAllocator, s, l), \ _syncPrintReturnPtr(portSyncSemaphoreCreate(pAllocator, s, l))) -#define portSyncSemaphoreDestroy(pSemaphore) \ - do { \ - portDbgPrintf("SYNC-DBG (%s:%d): portSyncSemaphoreDestroy(%p) ",\ - __FILE__, __LINE__, pSemaphore); \ - portSyncSemaphoreDestroy(pSemaphore); \ - portDbgPrintf(" - Done;\n"); \ - } while (0) - -#define portSyncSemaphoreAcquire(pSemaphore) \ - do { \ - portDbgPrintf("SYNC-DBG (%s:%d): portSyncSemaphoreAcquire(%p) ",\ - __FILE__, __LINE__, pSemaphore); \ - portSyncSemaphoreAcquire(pSemaphore); \ - portDbgPrintf(" - Done;\n"); \ - } while (0) - -#define portSyncSemaphoreRelease(pSemaphore) \ - do { \ - portDbgPrintf("SYNC-DBG (%s:%d): portSyncSemaphoreRelease(%p) ",\ - __FILE__, __LINE__, pSemaphore); \ - portSyncSemaphoreRelease(pSemaphore); \ - portDbgPrintf(" - Done;\n"); \ +#define portSyncSemaphoreDestroy(pSemaphore) \ + do { \ + portDbgPrintf("SYNC-DBG (%s:%d): portSyncSemaphoreDestroy(%p) ", \ + __FILE__, __LINE__, pSemaphore); \ + portSyncSemaphoreDestroy(pSemaphore); \ + portDbgPrintf(" - Done;\n"); \ + } while (0) + +#define portSyncSemaphoreAcquire(pSemaphore) \ + do { \ + portDbgPrintf("SYNC-DBG (%s:%d): portSyncSemaphoreAcquire(%p) ", \ + __FILE__, __LINE__, pSemaphore); \ + portSyncSemaphoreAcquire(pSemaphore); \ + portDbgPrintf(" - Done;\n"); \ + } while (0) + +#define portSyncSemaphoreRelease(pSemaphore) \ + do { \ + portDbgPrintf("SYNC-DBG (%s:%d): portSyncSemaphoreRelease(%p) ", \ + __FILE__, __LINE__, pSemaphore); \ + portSyncSemaphoreRelease(pSemaphore); \ + portDbgPrintf(" - Done;\n"); \ } while (0) -#define portSyncSemaphoreAcquireConditional(pSemaphore) \ +#define portSyncSemaphoreAcquireConditional(pSemaphore) \ (portDbgPrintf("SYNC-DBG (%s:%d): portSyncSemaphoreAcquireConditional(%p) - ", \ - __FILE__, __LINE__, pSemaphore),\ - (portSyncSemaphoreAcquireConditional(pSemaphore) ? \ + __FILE__, __LINE__, pSemaphore), \ + (portSyncSemaphoreAcquireConditional(pSemaphore) ? \ (portDbgPrintf("TRUE\n"),NV_TRUE) : (portDbgPrintf("FALSE\n"),NV_FALSE))) diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/inc/libraries/nvport/inline/util_gcc_clang.h nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/inc/libraries/nvport/inline/util_gcc_clang.h --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/inc/libraries/nvport/inline/util_gcc_clang.h 2023-10-25 20:20:43.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/inc/libraries/nvport/inline/util_gcc_clang.h 2024-03-05 22:13:06.000000000 +0000 @@ -49,54 +49,54 @@ #define portUtilGetReturnAddress() (NvUPtr)__builtin_return_address(0) #if NVCPU_IS_X86 || NVCPU_IS_X86_64 -#define NVPORT_DUMMY_LOOP() \ - __asm__ __volatile__ ("pause");\ - __asm__ __volatile__ ("pause");\ - __asm__ __volatile__ ("pause");\ - __asm__ __volatile__ ("pause");\ - __asm__ __volatile__ ("pause");\ - \ - __asm__ __volatile__ ("pause");\ - __asm__ __volatile__ ("pause");\ - __asm__ __volatile__ ("pause");\ - __asm__ __volatile__ ("pause");\ - __asm__ __volatile__ ("pause");\ - \ - __asm__ __volatile__ ("pause");\ - __asm__ __volatile__ ("pause");\ - __asm__ __volatile__ ("pause");\ - __asm__ __volatile__ ("pause");\ - __asm__ __volatile__ ("pause");\ - \ - __asm__ __volatile__ ("pause");\ - __asm__ __volatile__ ("pause");\ - __asm__ __volatile__ ("pause");\ - __asm__ __volatile__ ("pause");\ +#define NVPORT_DUMMY_LOOP() \ + __asm__ __volatile__ ("pause"); \ + __asm__ __volatile__ ("pause"); \ + __asm__ __volatile__ ("pause"); \ + __asm__ __volatile__ ("pause"); \ + __asm__ __volatile__ ("pause"); \ + \ + __asm__ __volatile__ ("pause"); \ + __asm__ __volatile__ ("pause"); \ + __asm__ __volatile__ ("pause"); \ + __asm__ __volatile__ ("pause"); \ + __asm__ __volatile__ ("pause"); \ + \ + __asm__ __volatile__ ("pause"); \ + __asm__ __volatile__ ("pause"); \ + __asm__ __volatile__ ("pause"); \ + __asm__ __volatile__ ("pause"); \ + __asm__ __volatile__ ("pause"); \ + \ + __asm__ __volatile__ ("pause"); \ + __asm__ __volatile__ ("pause"); \ + __asm__ __volatile__ ("pause"); \ + __asm__ __volatile__ ("pause"); \ __asm__ __volatile__ ("pause"); #else -#define NVPORT_DUMMY_LOOP() \ - __asm__ __volatile__ ("nop");\ - __asm__ __volatile__ ("nop");\ - __asm__ __volatile__ ("nop");\ - __asm__ __volatile__ ("nop");\ - __asm__ __volatile__ ("nop");\ - \ - __asm__ __volatile__ ("nop");\ - __asm__ __volatile__ ("nop");\ - __asm__ __volatile__ ("nop");\ - __asm__ __volatile__ ("nop");\ - __asm__ __volatile__ ("nop");\ - \ - __asm__ __volatile__ ("nop");\ - __asm__ __volatile__ ("nop");\ - __asm__ __volatile__ ("nop");\ - __asm__ __volatile__ ("nop");\ - __asm__ __volatile__ ("nop");\ - \ - __asm__ __volatile__ ("nop");\ - __asm__ __volatile__ ("nop");\ - __asm__ __volatile__ ("nop");\ - __asm__ __volatile__ ("nop");\ +#define NVPORT_DUMMY_LOOP() \ + __asm__ __volatile__ ("nop"); \ + __asm__ __volatile__ ("nop"); \ + __asm__ __volatile__ ("nop"); \ + __asm__ __volatile__ ("nop"); \ + __asm__ __volatile__ ("nop"); \ + \ + __asm__ __volatile__ ("nop"); \ + __asm__ __volatile__ ("nop"); \ + __asm__ __volatile__ ("nop"); \ + __asm__ __volatile__ ("nop"); \ + __asm__ __volatile__ ("nop"); \ + \ + __asm__ __volatile__ ("nop"); \ + __asm__ __volatile__ ("nop"); \ + __asm__ __volatile__ ("nop"); \ + __asm__ __volatile__ ("nop"); \ + __asm__ __volatile__ ("nop"); \ + \ + __asm__ __volatile__ ("nop"); \ + __asm__ __volatile__ ("nop"); \ + __asm__ __volatile__ ("nop"); \ + __asm__ __volatile__ ("nop"); \ __asm__ __volatile__ ("nop"); #endif diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/inc/libraries/nvport/memory.h nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/inc/libraries/nvport/memory.h --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/inc/libraries/nvport/memory.h 2023-10-25 20:20:43.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/inc/libraries/nvport/memory.h 2024-03-05 22:13:06.000000000 +0000 @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 2014-2021 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2014-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -505,12 +505,17 @@ PORT_MEM_ALLOCATOR *portMemAllocatorGetGlobalPaged(void); /** * @brief Prints the memory details gathered by whatever tracking mechanism is - * enabled. If pAllocator is NULL, it will print data for all allocators. + * enabled. If pTracking is NULL, aggregate tracking information from all + * allocators will be printed. * - * @note Printing is done using portDbgPrintString, which prints regardless of + * @note Printing is done using portDbgPrintf, which prints regardless of * build type and debug levels. */ -void portMemPrintTrackingInfo(const PORT_MEM_ALLOCATOR *pAllocator); +void portMemPrintTrackingInfo(const PORT_MEM_ALLOCATOR_TRACKING *pTracking); +/** + * @brief Calls @ref portMemPrintTrackingInfo for all current allocator trackers. + */ +void portMemPrintAllTrackingInfo(void); // @} End core functions @@ -568,12 +573,12 @@ /** * @brief Returns the statistics of peak allocations made with the given * allocator since it was created. - * - * Peak data reports each field independently. For example, if the peak data - * reports 100 allocations and 100000 bytes allocated, those two did not - * necessarily happen *at the same time*. It could also be that the allocator - * created 100 allocations of 1 byte each, then freed them and allocated a - * single 100000 bytes block. + * + * Peak data reports the high-water mark based on the maximum size (the peak + * allocations doesn't report the largest number of allocations, it reports + * the number of allocations at the time the peak size was achieved). This is + * done so that the other peak stats, which are derived from peak size and + * peak allocations, are consistent with each other. * * If pAllocator is NULL, it returns stats for all allocators, as well as the * memory allocated with @ref portMemAllocPaged and @ref portMemAllocNonPaged @@ -598,6 +603,16 @@ NV_STATUS portMemExTrackingGetNext(const PORT_MEM_ALLOCATOR *pAllocator, PORT_MEM_TRACK_ALLOC_INFO *pInfo, void **pIterator); /** + * @brief Gets the total size of the underlying heap, in bytes. + */ +NvLength portMemExTrackingGetHeapSize(void); + +/** + * @brief Gets the usable size in bytes (sans metadata/padding) of the given allocation. + */ +NvLength portMemExTrackingGetAllocUsableSize(void *pMem); + +/** * @brief Copies from user memory to kernel memory. * * When accepting data as input from user space it is necessary to take @@ -918,6 +933,9 @@ #endif #endif // !defined(PORT_MEM_TRACK_USE_LIMIT) +// Memory tracking header can redefine some functions declared here. +#include "nvport/inline/memory_tracking.h" + /** @brief Nothing is printed unless @ref portMemPrintTrackingInfo is called */ #define PORT_MEM_TRACK_PRINT_LEVEL_SILENT 0 /** @brief Print when an error occurs and at shutdown */ @@ -926,16 +944,13 @@ #define PORT_MEM_TRACK_PRINT_LEVEL_VERBOSE 2 #if !defined(PORT_MEM_TRACK_PRINT_LEVEL) -#if PORT_IS_CHECKED_BUILD +#if PORT_IS_CHECKED_BUILD || PORT_MEM_TRACK_ALLOC_SIZE #define PORT_MEM_TRACK_PRINT_LEVEL PORT_MEM_TRACK_PRINT_LEVEL_BASIC #else #define PORT_MEM_TRACK_PRINT_LEVEL PORT_MEM_TRACK_PRINT_LEVEL_SILENT #endif // PORT_IS_CHECKED_BUILD #endif // !defined(PORT_MEM_TRACK_PRINT_LEVEL) -// Memory tracking header can redefine some functions declared here. -#include "nvport/inline/memory_tracking.h" - /** * @brief Single allocation description. * diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/inc/libraries/nvport/nvport.h nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/inc/libraries/nvport/nvport.h --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/inc/libraries/nvport/nvport.h 2023-10-25 20:20:44.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/inc/libraries/nvport/nvport.h 2024-03-05 22:13:06.000000000 +0000 @@ -158,7 +158,7 @@ * * This switch will define type and method aliases for object types in NvPort. * The current NvPort style object names are PORT_MODULE_OBJECT, while the - * methods are portModuleObjectMethod(). + * methods are portModuleObjectMethod(). * The update proposal dictates these to be PortModuleObject and objectMethod. * * @todo Currently we just alias the new names to the old ones. Once the coding @@ -174,18 +174,18 @@ * * No compilation errors are reported by any compiler when we use * the following definition. - * + * * #define PORT_UNREFERENCED_VARIABLE(x) ((void)sizeof(&(x))) * * But Coverity reports BAD_SIZEOF error with this definition. - * Adding a Coverity annotation "coverity[bad_sizeof]" near + * Adding a Coverity annotation "coverity[bad_sizeof]" near * the definition does not work. The preprocessor ignores all * the comments and the Coverity annotation is also ignored * as a legal comment. As a result, this annotation never ends * up in the source code where this macro is used. Hence, we use * two definitions of this macro - one for Coverity and the other - * for the rest of the targets. - * + * for the rest of the targets. + * * Coverity does not report any warnings for unused variables. * Hence, we do nothing while building for Coverity. */ diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/inc/libraries/nvport/string.h nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/inc/libraries/nvport/string.h --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/inc/libraries/nvport/string.h 2023-10-25 20:20:44.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/inc/libraries/nvport/string.h 2024-03-05 22:13:06.000000000 +0000 @@ -48,7 +48,7 @@ /** * @brief Compare two strings, character by character. - * + * * Will only compare lengthBytes bytes. Strings are assumed to be at least that * long. * @@ -64,7 +64,7 @@ NvS32 portStringCompare(const char *str1, const char *str2, NvLength length); /** * @brief Copy a string. - * + * * Will copy at most destSize bytes, stopping early if a null-terminator is found * or if srcSize bytes are read from the source. * @@ -82,13 +82,13 @@ NvLength portStringCopy(char *dest, NvLength destSize, const char *src, NvLength srcSize); /** * @brief Concatenate two strings - * + * * Will copy cat string after the end of str. Will copy only until str buffer is * filled. str is assumed to point to a buffer of at least strSize bytes. * * Null character is always written at the end of the string. * - * @return str if concatenation is succeeded. + * @return str if concatenation is succeeded. * * @par Undefined: * Number of allocated bytes in destination buffer are smaller than destSize.
diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/inc/libraries/poolalloc.h nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/inc/libraries/poolalloc.h --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/inc/libraries/poolalloc.h 2023-10-25 20:20:44.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/inc/libraries/poolalloc.h 2024-03-05 22:13:07.000000000 +0000 @@ -48,28 +48,28 @@ typedef struct poolnode POOLNODE; -/*! +/*! * Each node corresponds to one page of upStreamPageSize * The pool allocator sub-allocates from each of these pages. - */ + */ struct poolnode { NvU64 pageAddr; // Address of the page to sub-allocate NvU64 bitmap; // The bit map for this page. Only used if the // node represents a partially allocated node - POOLNODE *pParent; // The upstream pool node in case this node is + POOLNODE *pParent; // The upstream pool node in case this node is // allocated from the upper pool. ListNode node; // For intrusive lists. }; MAKE_INTRUSIVE_LIST(PoolNodeList, POOLNODE, node); -/*! +/*! * The handle contains a generic metadata field that is needed for fast * access. In the case of a linked list implementation of the pool allocator, * the metadata is the pointer to the node that contains the page it was - * sub-allocated from - */ + * sub-allocated from + */ typedef struct poolallocHandle { NvU64 address; // The base address for this chunk @@ -83,10 +83,11 @@ /*! * @brief Callback function to upstream allocators for allocating new pages * - * This function only allocate 1 page at a time right now + * This function can allocate multiple pages at a time * * @param[in] ctxPtr Provides context to upstream allocator - * @param[in] pageSize Not really needed. For debugging only + * @param[in] pageSize Size of page to ask for from upstream + * @param[in] numPages Number of pages to allocate * @param[out] pPage The output page handle from upstream * * @return NV_OK if successfully allocated NvF32 totalTest, doneTest, failTest; the page @@ -96,7 +97,7 @@ * */ typedef NV_STATUS (*allocCallback_t)(void *ctxPtr, NvU64 pageSize, - POOLALLOC_HANDLE *pPage); + NvU64 numPages, POOLALLOC_HANDLE *pPage); /*! * @brief Callback function to upstream allocators for freeing unused pages @@ -110,7 +111,7 @@ */ typedef void (*freeCallback_t)(void *ctxPtr, NvU64 pageSize, POOLALLOC_HANDLE *pPage); -/*! +/*! * Structure representing a pool. */ typedef struct poolalloc @@ -128,14 +129,14 @@ void *pUpstreamCtx; // The context to pass to upstream allocator } callBackInfo; - NvU32 upstreamPageSize; // Page size for upstream allocations - NvU32 allocPageSize; // Page size to give out + NvU64 upstreamPageSize; // Page size for upstream allocations + NvU64 allocPageSize; // Page size to give out NvU32 ratio; // Ratio == upstreamPageSize / allocPageSize NvU32 flags; // POOLALLOC_FLAGS_* } POOLALLOC; -/*! +/*! * Dump the lists maintained by the pools. */ void poolAllocPrint(POOLALLOC *pPool); @@ -169,14 +170,14 @@ * @param[in] freeFun The free for internal structures * @param[in] pAllocCtxPtr The context pointer for the special * allocator - * @param[in] flags POOLALLOC_FLAGS_* + * @param[in] flags POOLALLOC_FLAGS_* * * @return A pointer to a POOLALLOC structure if the initialization * succeeded; NULL otherwise * */ -POOLALLOC *poolInitialize(NvU32 upstreamPageSize, NvU32 allocPageSize, +POOLALLOC *poolInitialize(NvU64 upstreamPageSize, NvU64 allocPageSize, allocCallback_t allocCb, freeCallback_t freeCb, void *pUpstreamCtxPtr, PORT_MEM_ALLOCATOR *pAllocator, NvU32 flags); @@ -276,10 +277,10 @@ */ void poolDestroy(POOLALLOC *pPool); -/*! +/*! * @briefs Returns the lengths of a pool's lists */ -void poolGetListLength(POOLALLOC *pPool, NvU32 *pFreeListLength, +void poolGetListLength(POOLALLOC *pPool, NvU32 *pFreeListLength, NvU32 *pPartialListLength, NvU32 *pFullListLength); #ifdef __cplusplus diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/inc/libraries/resserv/resserv.h nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/inc/libraries/resserv/resserv.h --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/inc/libraries/resserv/resserv.h 2023-10-25 20:20:44.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/inc/libraries/resserv/resserv.h 2024-03-05 22:13:07.000000000 +0000 @@ -170,6 +170,7 @@ #define RS_LOCK_FLAGS_NO_CUSTOM_LOCK_3 NVBIT(4) #define RS_LOCK_FLAGS_NO_DEPENDANT_SESSION_LOCK NVBIT(5) #define RS_LOCK_FLAGS_FREE_SESSION_LOCK NVBIT(6) +#define RS_LOCK_FLAGS_LOW_PRIORITY NVBIT(7) /// RS_LOCK_STATE #define RS_LOCK_STATE_TOP_LOCK_ACQUIRED NVBIT(0) @@ -189,7 +190,7 @@ #define RS_LOCK_RELEASE_SESSION_LOCK NVBIT(5) /// API enumerations used for locking knobs -typedef enum +typedef enum { RS_LOCK_CLIENT =0, RS_LOCK_TOP =1, @@ -197,7 +198,7 @@ RS_LOCK_CUSTOM_3 =3, } RS_LOCK_ENUM; -typedef enum +typedef enum { RS_API_ALLOC_CLIENT = 0, RS_API_ALLOC_RESOURCE = 1, @@ -276,6 +277,13 @@ RS_LOCK_INFO *pLockInfo; ///< Saved locking context information for the call API_SECURITY_INFO secInfo; RS_RES_CONTROL_PARAMS_INTERNAL *pControlParams; ///< parameters of the call [optional] + + void *pSerializedParams; ///< Serialized version of the params + void *pDeserializedParams; ///< Deserialized version of the params + NvU32 serializedSize; ///< Serialized size + NvU32 deserializedSize; ///< Deserialized size + NvBool bReserialize; ///< Reserialize before calling into GSP + NvBool bLocalSerialization; ///< Serialized internally }; typedef enum { @@ -354,7 +362,7 @@ } while(0) #else -#define RS_LOCK_VALIDATOR_INIT(lock, lockClass, inst) +#define RS_LOCK_VALIDATOR_INIT(lock, lockClass, inst) #define RS_RWLOCK_ACQUIRE_READ(lock, validator) do { portSyncRwLockAcquireRead((lock)); } while(0) #define RS_RWLOCK_ACQUIRE_WRITE(lock, validator) do { portSyncRwLockAcquireWrite((lock)); } while(0) #define RS_RWLOCK_RELEASE_READ_EXT(lock, validator, bOutOfOrder) do { portSyncRwLockReleaseRead((lock)); } while(0) diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/inc/libraries/resserv/rs_client.h nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/inc/libraries/resserv/rs_client.h --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/inc/libraries/resserv/rs_client.h 2023-10-25 20:20:45.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/inc/libraries/resserv/rs_client.h 2024-03-05 22:13:07.000000000 +0000 @@ -85,6 +85,16 @@ NvBool bResourceWarning; /** + * True if client is disabled, awaiting free + */ + NvBool bDisabled; + + /** + * True if client's high priority resources were freed + */ + NvBool bHighPriorityFreeDone; + + /** * Maps resource handle -> RsResourceRef */ RsRefMap resourceMap; @@ -141,6 +151,11 @@ RS_FREE_STACK *pFreeStack; /** + * Node for a client's disabled client list + */ + ListNode disabledClientNode; + + /** * Construct a client instance * @param[in] pClient This client * @param[in] pAllocator NvPort memory allocation interface for client memory allocations @@ -412,6 +427,7 @@ */ NV_STATUS clientSetRestrictedRange(RsClient *pClient, NvHandle handleRangeStart, NvU32 handleRangeSize); }; +MAKE_INTRUSIVE_LIST(RsDisabledClientList, RsClient, disabledClientNode); /** * Get an iterator to the elements in the client's resource map @@ -454,6 +470,14 @@ */ NvBool clientRefOrderedIterNext(RsClient *pClient, RS_ORDERED_ITERATOR *pIt); +/** + * Release all CPU address mappings for a resource + * + * @param[in] pClient Client that owns the resource + * @param[in] pCallContext Caller information (which includes the resource reference whose mappings will be freed) + * @param[in] pLockInfo Information about which locks are already held, for recursive calls + */ +NV_STATUS clientUnmapResourceRefMappings(RsClient *pClient, CALL_CONTEXT *pCallContext, RS_LOCK_INFO *pLockInfo); /** * RsResource interface to a RsClient @@ -488,6 +512,7 @@ NvHandle hDomain; ///< [in] The parent domain NvHandle hClient; ///< [in] The client handle NvBool bHiPriOnly; ///< [in] Only free high priority resources + NvBool bDisableOnly; ///< [in] Only disable the listed clients, do not free them yet NvU32 state; ///< [in] User-defined state RS_RES_FREE_PARAMS_INTERNAL *pResFreeParams; ///< [in] Necessary for locking state diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/inc/libraries/resserv/rs_resource.h nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/inc/libraries/resserv/rs_resource.h --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/inc/libraries/resserv/rs_resource.h 2023-10-25 20:20:45.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/inc/libraries/resserv/rs_resource.h 2024-03-05 22:13:07.000000000 +0000 @@ -90,6 +90,7 @@ API_SECURITY_INFO *pSecInfo; void *pAllocParams; ///< [in] Copied-in allocation parameters + NvU32 paramsSize; ///< [in] Copied-in allocation parameters size // ... Dupe alloc RsClient *pSrcClient; ///< The client that is sharing the resource @@ -140,6 +141,7 @@ // Internal use only NvBool bHiPriOnly; ///< [in] Only free if this is a high priority resources + NvBool bDisableOnly; ///< [in] Disable the target instead of freeing it (only applies to clients) RS_LOCK_INFO *pLockInfo; ///< [inout] Locking flags and state NvU32 freeFlags; ///< [in] Flags for the free operation NvU32 freeState; ///< [inout] Free state @@ -297,6 +299,30 @@ RS_RES_CONTROL_PARAMS_INTERNAL *pParams); /** + * Serialize the control parameters if they are going to GSP/Host, not serialized, and support serialization + * Or + * Deserialize the control parameters if necessary and replace the inner params pointer with the deserialized params + * + * @param[in] pResource + * @param[in] pCallContext + * @param[in] pParams + */ + virtual NV_STATUS resControlSerialization_Prologue(RsResource *pResource, CALL_CONTEXT *pCallContext, + RS_RES_CONTROL_PARAMS_INTERNAL *pParams); + + /** + * Deserialize the parameters returned from GSP if client did not pass serialized params + * Or + * Serialize the control parameters if client expects it and restore the original inner params pointer + * + * @param[in] pResource + * @param[in] pCallContext + * @param[in] pParams + */ + virtual void resControlSerialization_Epilogue(RsResource *pResource, CALL_CONTEXT *pCallContext, + RS_RES_CONTROL_PARAMS_INTERNAL *pParams); + + /** * Operations performed right before the control call is executed. Default stubbed. * * @param[in] pResource @@ -788,7 +814,7 @@ /** * Remove the dependency between this resource reference and a dependent resource reference. */ -NV_STATUS refRemoveDependant(RsResourceRef *pResourceRef, RsResourceRef *pDependantRef); +void refRemoveDependant(RsResourceRef *pResourceRef, RsResourceRef *pDependantRef); /** * Find, Add, or Remove an inter-mapping between two resources to the Mapper's list of inter-mappings diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/inc/libraries/resserv/rs_server.h nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/inc/libraries/resserv/rs_server.h --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/inc/libraries/resserv/rs_server.h 2023-10-25 20:20:45.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/inc/libraries/resserv/rs_server.h 2024-03-05 22:13:07.000000000 +0000 @@ -28,6 +28,7 @@ #include "nvport/nvport.h" #include "resserv/resserv.h" +#include "resserv/rs_client.h" #include "nvoc/runtime.h" #ifdef __cplusplus @@ -181,6 +182,11 @@ NvU32 activeClientCount; NvU64 activeResourceCount; + + /// List of clients that are de-activated and pending free + RsDisabledClientList disabledClientList; + RsClient *pNextDisabledClient; + PORT_SPINLOCK *pDisabledClientListLock; }; /** @@ -262,20 +268,35 @@ NV_STATUS serverFreeClient(RsServer *pServer, RS_CLIENT_FREE_PARAMS* pParams); /** - * Free a list of client handles. All resources references owned by the client will be - * freed. All priority resources will be freed first across all listed clients. + * Mark a list of client handles as disabled. All CPU mappings owned by that + * client will be unmapped immediate, and the client will be marked as disabled. + * A call to @ref serverFreeDisabledClients will then free all such clients. * * It is invalid to attempt to free a client from a user other than the one * that allocated it. * * @param[in] pServer This server instance - * @param[in] phClientList The list of client handles to free + * @param[in] phClientList The list of client handles to disable * @param[in] numClients The number of clients in the list * @param[in] freeState User-defined free state * @param[in] pSecInfo Security Info * */ -NV_STATUS serverFreeClientList(RsServer *pServer, NvHandle *phClientList, NvU32 numClients, NvU32 freeState, API_SECURITY_INFO *pSecInfo); +NV_STATUS serverMarkClientListDisabled(RsServer *pServer, NvHandle *phClientList, NvU32 numClients, NvU32 freeState, API_SECURITY_INFO *pSecInfo); + +/** + * Frees all currently disabled clients. All resources references owned by + * any of the clients will be freed. + * All priority resources will be freed first across all listed clients. + * + * NOTE: may return NV_WARN_MORE_PROCESSING_REQUIRED if not all clients were freed + * + * @param[in] pServer This server instance + * @param[in] freeState User-defined free state + * @param[in] limit Max number of iterations to make returning; 0 means no limit + * + */ +NV_STATUS serverFreeDisabledClients(RsServer *pServer, NvU32 freeState, NvU32 limit); /** * Allocate a resource. @@ -351,8 +372,111 @@ * @param[in] pServer * @param[in] clientHandleBase */ - NV_STATUS serverSetClientHandleBase(RsServer *pServer, NvU32 clientHandleBase); +NV_STATUS serverSetClientHandleBase(RsServer *pServer, NvU32 clientHandleBase); + +/** + * Deserialize parameters for servicing command + * + * @param[in] pCallContext + * @param[in] cmd + * @param[in/out] ppParams + * @param[in/out] pParamsSize + * @param[in] flags + */ +NV_STATUS serverDeserializeCtrlDown(CALL_CONTEXT *pCallContext, NvU32 cmd, void **ppParams, NvU32 *pParamsSize, NvU32 *flags); + +/** + * Serialize parameters for servicing command + * + * @param[in] pCallContext + * @param[in] cmd + * @param[in/out] ppParams + * @param[in/out] pParamsSize + * @param[in] flags + */ +NV_STATUS serverSerializeCtrlDown(CALL_CONTEXT *pCallContext, NvU32 cmd, void **ppParams, NvU32 *pParamsSize, NvU32 *flags); + +/** + * Deserialize parameters for returning from command + * + * @param[in] pCallContext + * @param[in] cmd + * @param[out] ppParams + * @param[out] pParamsSize + * @param[in] flags + */ +NV_STATUS serverDeserializeCtrlUp(CALL_CONTEXT *pCallContext, NvU32 cmd, void **ppParams, NvU32 *pParamsSize, NvU32 *flags); + +/** + * Serialize parameters for returning from command + * + * @param[in] pCallContext + * @param[in] cmd + * @param[out] ppParams + * @param[out] pParamsSize + * @param[in] flags + */ +NV_STATUS serverSerializeCtrlUp(CALL_CONTEXT *pCallContext, NvU32 cmd, void **ppParams, NvU32 *pParamsSize, NvU32 *flags); +/** + * Unset flag for reserializing control before going to GSP + * Used if kernel control servicing passes params to GSP without changing them + * + * @param[in] pCallContext + */ +void serverDisableReserializeControl(CALL_CONTEXT *pCallContext); + +/** + * Serialize parameters for allocating + * + * @param[in] pCallContext + * @param[in] classId + * @param[in/out] ppParams + * @param[out] pParamsSize + * @param[in] flags + */ +NV_STATUS serverSerializeAllocDown(CALL_CONTEXT *pCallContext, NvU32 classId, void **ppParams, NvU32 *pParamsSize, NvU32 *flags); + +/** + * Deserialize parameters for allocating + * + * @param[in] pCallContext + * @param[in] classId + * @param[in/out] ppParams + * @param[in/out] pParamsSize + * @param[in] flags + */ +NV_STATUS serverDeserializeAllocDown(CALL_CONTEXT *pCallContext, NvU32 classId, void **ppParams, NvU32 *pParamsSize, NvU32 *flags); + +/** + * Serialize parameters for returning from allocating + * + * @param[in] pCallContext + * @param[in] classId + * @param[out] ppParams + * @param[out] pParamsSize + * @param[in] flags + */ +NV_STATUS serverSerializeAllocUp(CALL_CONTEXT *pCallContext, NvU32 classId, void **ppParams, NvU32 *pParamsSize, NvU32 *flags); + +/** + * Deserialize parameters for returning from allocating + * + * @param[in] pCallContext + * @param[in] classId + * @param[out] ppParams + * @param[out] pParamsSize + * @param[in] flags + */ +NV_STATUS serverDeserializeAllocUp(CALL_CONTEXT *pCallContext, NvU32 classId, void **ppParams, NvU32 *pParamsSize, NvU32 *flags); + +/** + * Free finn structures allocated for serializing/deserializing + * + * @param[in] pCallContext + * @param[in] pParams + */ +void serverFreeSerializeStructures(CALL_CONTEXT *pCallContext, void *pParams); /** * Return an available client handle for new client allocation diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/inc/libraries/tls/tls.h nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/inc/libraries/tls/tls.h --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/inc/libraries/tls/tls.h 2023-10-25 20:20:45.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/inc/libraries/tls/tls.h 2024-03-05 22:13:07.000000000 +0000 @@ -262,7 +262,7 @@ #define TLS_ISR_ALLOCATOR_SIZE 512 #else #if defined(LOCK_VAL_ENABLED) - #define TLS_ISR_ALLOCATOR_SIZE 400 + #define TLS_ISR_ALLOCATOR_SIZE 512 #else #define TLS_ISR_ALLOCATOR_SIZE 256 #endif diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/inc/libraries/utils/nv_enum.h nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/inc/libraries/utils/nv_enum.h --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/inc/libraries/utils/nv_enum.h 2023-10-25 20:20:45.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/inc/libraries/utils/nv_enum.h 2024-03-05 22:13:08.000000000 +0000 @@ -130,7 +130,7 @@ * often. There is no such thing as a meta-macro in the c preprocessor, so * we have defined the operations which we use frequently here. * - * @note instead of LISP-style structured lists which are formatted as + * @note instead of LISP-style structured lists which are formatted as * records containing two elements each (e.g. (car, (cdr, ()))), this tool * uses preprocessor argument lists (e.g. (car, cdr, etc)) because the * former require proper recursion to deal with, which this tool does not @@ -149,8 +149,8 @@ #define NV_CAADR(l) NV_ENUM_APPLY(NV_ENUM_A1, NV_ENUM_APPLY(NV_ENUM_A2, l)) #define NV_CADADR(l) NV_ENUM_APPLY(NV_ENUM_A2, NV_ENUM_APPLY(NV_ENUM_A2, l)) #define NV_CADDADR(l) NV_ENUM_APPLY(NV_ENUM_A3, NV_ENUM_APPLY(NV_ENUM_A2, l)) -#define NV_CADDDADR(l) NV_ENUM_APPLY(NV_ENUM_A4, NV_ENUM_APPLY(NV_ENUM_A2, l)) -#define NV_CADDDDADR(l) NV_ENUM_APPLY(NV_ENUM_A5, NV_ENUM_APPLY(NV_ENUM_A2, l)) +#define NV_CADDDADR(l) NV_ENUM_APPLY(NV_ENUM_A4, NV_ENUM_APPLY(NV_ENUM_A2, l)) +#define NV_CADDDDADR(l) NV_ENUM_APPLY(NV_ENUM_A5, NV_ENUM_APPLY(NV_ENUM_A2, l)) /*! * @brief Performs per-entry generation function, and either expands or extinguishes it @@ -160,7 +160,7 @@ * @param value Integer Literal - Value for this entry * * @return the result of the generation function for this table, - * or nothing if this layer is being filtered (i.e. nested enum) + * or nothing if this layer is being filtered (i.e. nested enum) */ #define NV_ENUM_ENTRY(dat__, name, value) \ NV_ENUM_DAT_ENTRY(dat__) (NV_ENUM_DAT_GEN2(dat__) (dat__, name, value)) @@ -175,7 +175,7 @@ * * @param dat__ Data List - Generation data table * @param name Token - String to append to previous enum name - * @param res_lo Integer Literal - Min value of this nested enum + * @param res_lo Integer Literal - Min value of this nested enum * @param res_hi Integer Literal - Max value of this nested enum * @param entries Macro - Nested Enum Specification */ @@ -189,7 +189,7 @@ entries(NV_ENUM_APPLY(NV_ENUM_DL_POP, NV_ENUM_NV_ENUM_REPLACE_1(NV_ENUM_NV_ENUM_REPLACE_1(NV_ENUM_CONCATENATE(NV_ENUM_DAT_CURR_NAME(dat__), name), NV_ENUM_APPLY(NV_ENUM_A1, dat__)), dat__))) /*! - * @brief Performs all enum generation for the given nested enum specification + * @brief Performs all enum generation for the given nested enum specification * * @note the Current Enum Name is concatenated with parameter `name` * the Nested Enum Name is updated to match the Current Enum Name @@ -200,29 +200,29 @@ * * @param dat__ Data List - Generation data table * @param name Token - String to append to previous enum name - * @param res_lo Integer Literal - Min value of this nested enum + * @param res_lo Integer Literal - Min value of this nested enum * @param res_hi Integer Literal - Max value of this nested enum * @param entries Macro - Nested Enum Specification */ -#define NV_ENUM_NEST_GEN(dat__, name, res_lo, res_hi, entries) \ - NV_ENUM_DAT_GEN1(dat__)( \ - NV_ENUM_APPLY( \ - NV_ENUM_DL_POP, \ - NV_ENUM_NV_ENUM_REPLACE_1( \ - NV_ENUM_REPLACE_4( \ +#define NV_ENUM_NEST_GEN(dat__, name, res_lo, res_hi, entries) \ + NV_ENUM_DAT_GEN1(dat__)( \ + NV_ENUM_APPLY( \ + NV_ENUM_DL_POP, \ + NV_ENUM_NV_ENUM_REPLACE_1( \ + NV_ENUM_REPLACE_4( \ NV_ENUM_CONCATENATE(NV_ENUM_DAT_CURR_NAME(dat__), name), \ NV_ENUM_CONCATENATE(NV_ENUM_DAT_CURR_NAME(dat__), name), \ - res_lo, \ - res_hi, \ - NV_ENUM_APPLY( \ - NV_ENUM_A1, \ - dat__ \ - ) \ - ), \ - dat__ \ - ) \ - ), \ - entries \ + res_lo, \ + res_hi, \ + NV_ENUM_APPLY( \ + NV_ENUM_A1, \ + dat__ \ + ) \ + ), \ + dat__ \ + ) \ + ), \ + entries \ ) /*! @@ -279,37 +279,37 @@ /*! * @brief constructs a data list to be used for generation of the root enum */ -#define NV_ENUM_DEPTH_0(name, prefix, gen1_fn, gen2_fn) \ - ( (name, name, prefix, name, NV_ENUM_MIN, NV_ENUM_MAX) \ +#define NV_ENUM_DEPTH_0(name, prefix, gen1_fn, gen2_fn) \ + ( (name, name, prefix, name, NV_ENUM_MIN, NV_ENUM_MAX) \ , (NV_EXPAND_ONE, NV_ENUM_NEST_EXPAND0, gen1_fn, gen2_fn, unused, unused) \ , (NV_EXPAND_ONE, NV_ENUM_NEST_EXPAND1, gen1_fn, gen2_fn, unused, unused) \ , (NV_EXPAND_ONE, NV_ENUM_NEST_EXPAND2, gen1_fn, gen2_fn, unused, unused) \ , (NV_EXPAND_ONE, NV_ENUM_NEST_EXPAND3, gen1_fn, gen2_fn, unused, unused) \ - , (unused, unused, unused, unused, unused, unused) \ + , (unused, unused, unused, unused, unused, unused) \ ) /*! * @brief constructs a data list to be used for generation of enums at depth 1 */ -#define NV_ENUM_DEPTH_1(name, prefix, gen1_fn, gen2_fn) \ - ( (name, name, prefix, name, NV_ENUM_MIN, NV_ENUM_MAX) \ - , (NV_DISCARD_ONE, NV_ENUM_NEST_GEN, gen1_fn, gen2_fn, unused, unused) \ +#define NV_ENUM_DEPTH_1(name, prefix, gen1_fn, gen2_fn) \ + ( (name, name, prefix, name, NV_ENUM_MIN, NV_ENUM_MAX) \ + , (NV_DISCARD_ONE, NV_ENUM_NEST_GEN, gen1_fn, gen2_fn, unused, unused) \ , (NV_EXPAND_ONE, NV_ENUM_NEST_EXPAND0, gen1_fn, gen2_fn, unused, unused) \ , (NV_EXPAND_ONE, NV_ENUM_NEST_EXPAND1, gen1_fn, gen2_fn, unused, unused) \ , (NV_EXPAND_ONE, NV_ENUM_NEST_EXPAND2, gen1_fn, gen2_fn, unused, unused) \ - , (unused, unused, unused, unused, unused, unused) \ + , (unused, unused, unused, unused, unused, unused) \ ) /*! * @brief constructs a data list to be used for generation of enums at depth 2 */ -#define NV_ENUM_DEPTH_2(name, prefix, gen1_fn, gen2_fn) \ - ( (name, name, prefix, name, NV_ENUM_MIN, NV_ENUM_MAX) \ +#define NV_ENUM_DEPTH_2(name, prefix, gen1_fn, gen2_fn) \ + ( (name, name, prefix, name, NV_ENUM_MIN, NV_ENUM_MAX) \ , (NV_DISCARD_ONE, NV_ENUM_NEST_EXPAND0, gen1_fn, gen2_fn, unused, unused) \ - , (NV_DISCARD_ONE, NV_ENUM_NEST_GEN, gen1_fn, gen2_fn, unused, unused) \ - , (NV_EXPAND_ONE, NV_ENUM_NEST_EXPAND1, gen1_fn, gen2_fn, unused, unused) \ - , (NV_EXPAND_ONE, NV_ENUM_NEST_EXPAND2, gen1_fn, gen2_fn, unused, unused) \ - , (unused, unused, unused, unused, unused, unused) \ + , (NV_DISCARD_ONE, NV_ENUM_NEST_GEN, gen1_fn, gen2_fn, unused, unused) \ + , (NV_EXPAND_ONE, NV_ENUM_NEST_EXPAND1, gen1_fn, gen2_fn, unused, unused) \ + , (NV_EXPAND_ONE, NV_ENUM_NEST_EXPAND2, gen1_fn, gen2_fn, unused, unused) \ + , (unused, unused, unused, unused, unused, unused) \ ) /// @@ -344,47 +344,47 @@ /*! @brief Generates a conversion function from an enum value to string representation. */ -#define NV_ENUM_GEN_STRING(dat__, entries) \ - static inline const char * \ - NV_ENUM_CONCATENATE(NV_ENUM_DAT_CURR_NAME(dat__), _TO_STRING) \ - ( \ - enum NV_ENUM_DAT_ROOT_NAME(dat__) in \ - ) \ - { \ - switch (in) \ - { \ - entries(dat__) \ - default: \ - break; \ - } \ +#define NV_ENUM_GEN_STRING(dat__, entries) \ + static inline const char * \ + NV_ENUM_CONCATENATE(NV_ENUM_DAT_CURR_NAME(dat__), _TO_STRING) \ + ( \ + enum NV_ENUM_DAT_ROOT_NAME(dat__) in \ + ) \ + { \ + switch (in) \ + { \ + entries(dat__) \ + default: \ + break; \ + } \ return NV_ENUM_STRINGIFY(NV_ENUM_CONCATENATE(NV_ENUM_DAT_CURR_NAME(dat__), __UNKNOWN)); \ } /*! @brief Generates a case for the given enum entry, and its string representation. */ -#define NV_ENUM_GEN_STRING_FN(dat__, entry_name, value) \ +#define NV_ENUM_GEN_STRING_FN(dat__, entry_name, value) \ case NV_ENUM_CONCATENATE(NV_ENUM_DAT_PREFIX(dat__), entry_name): \ return NV_ENUM_STRINGIFY(NV_ENUM_CONCATENATE(NV_ENUM_DAT_PREFIX(dat__), entry_name)); /*! @brief Generates a conversion function from NvU32 to enum value. */ -#define NV_ENUM_GEN_FROM(dat__, entries) \ - static inline NV_STATUS \ - NV_ENUM_CONCATENATE(NV_ENUM_DAT_CURR_NAME(dat__), _FROM32) \ - ( \ - NvU32 in, \ - enum NV_ENUM_DAT_ROOT_NAME(dat__) *out \ - ) \ - { \ - switch (in) \ - { \ - entries(dat__) \ - if (out != NULL) \ +#define NV_ENUM_GEN_FROM(dat__, entries) \ + static inline NV_STATUS \ + NV_ENUM_CONCATENATE(NV_ENUM_DAT_CURR_NAME(dat__), _FROM32) \ + ( \ + NvU32 in, \ + enum NV_ENUM_DAT_ROOT_NAME(dat__) *out \ + ) \ + { \ + switch (in) \ + { \ + entries(dat__) \ + if (out != NULL) \ *out = ((enum NV_ENUM_DAT_ROOT_NAME(dat__))in); \ - return NV_OK; \ - default: \ - break; \ - } \ - return NV_ERR_OUT_OF_RANGE; \ + return NV_OK; \ + default: \ + break; \ + } \ + return NV_ERR_OUT_OF_RANGE; \ } /*! @brief Generates a case for the given enum entry. */ @@ -411,11 +411,11 @@ /*! @brief Generates a group of struct constants containing the above generated values. */ -#define NV_ENUM_GEN_META(dat__, entries) \ - typedef struct { char lo[sizeof(((NV_ENUM_CONCATENATE(NV_ENUM_DAT_CURR_NAME(dat__), __LO) *) NULL)->lo)]; \ - char hi[NV_ENUM_CONCATENATE(NV_ENUM_DAT_CURR_NAME(dat__), __SIZE)];\ - char count[sizeof(((NV_ENUM_CONCATENATE(NV_ENUM_DAT_CURR_NAME(dat__), __COUNT) *) NULL)->count)]; \ - char size[NV_ENUM_CONCATENATE(NV_ENUM_DAT_CURR_NAME(dat__), __SIZE)]; \ +#define NV_ENUM_GEN_META(dat__, entries) \ + typedef struct { char lo[sizeof(((NV_ENUM_CONCATENATE(NV_ENUM_DAT_CURR_NAME(dat__), __LO) *) NULL)->lo)]; \ + char hi[NV_ENUM_CONCATENATE(NV_ENUM_DAT_CURR_NAME(dat__), __SIZE)]; \ + char count[sizeof(((NV_ENUM_CONCATENATE(NV_ENUM_DAT_CURR_NAME(dat__), __COUNT) *) NULL)->count)]; \ + char size[NV_ENUM_CONCATENATE(NV_ENUM_DAT_CURR_NAME(dat__), __SIZE)]; \ char bContiguous[(sizeof(((NV_ENUM_CONCATENATE(NV_ENUM_DAT_CURR_NAME(dat__), __COUNT) *) NULL)->count) == (NV_ENUM_CONCATENATE(NV_ENUM_DAT_CURR_NAME(dat__), __SIZE) - sizeof(((NV_ENUM_CONCATENATE(NV_ENUM_DAT_CURR_NAME(dat__), __LO) *) NULL)->lo) + 1)) + 1]; \ } NV_ENUM_CONCATENATE(NV_ENUM_DAT_CURR_NAME(dat__), __META) ; @@ -463,9 +463,9 @@ * @param entries Macro - Enum Specification */ #define NV_ENUM_GENERATOR(fn1, fn2, enum_name, prefix, entries) \ - fn1(NV_ENUM_DEPTH_0(enum_name, prefix, fn1, fn2), entries) \ - entries(NV_ENUM_DEPTH_1(enum_name, prefix, fn1, fn2)) \ - entries(NV_ENUM_DEPTH_2(enum_name, prefix, fn1, fn2)) \ + fn1(NV_ENUM_DEPTH_0(enum_name, prefix, fn1, fn2), entries) \ + entries(NV_ENUM_DEPTH_1(enum_name, prefix, fn1, fn2)) \ + entries(NV_ENUM_DEPTH_2(enum_name, prefix, fn1, fn2)) \ // // Windows preprocessor crashes with "ran out of heap space" errors if the @@ -482,15 +482,15 @@ * @param enum_name Token - Root Enum Name * @param entries Macro - Enum Specification */ -#define NV_ENUM_DEF_PREFIX(prefix, enum_name, entries) \ +#define NV_ENUM_DEF_PREFIX(prefix, enum_name, entries) \ NV_ENUM_GEN_MAIN(NV_ENUM_DEPTH_0(enum_name, prefix, NV_ENUM_GEN_MAIN, NV_ENUM_GEN_MAIN_FN), entries) \ - NV_ENUM_GENERATOR(NV_ENUM_GEN_TYPEDEF, NV_ENUM_GEN_TYPEDEF_FN, enum_name, prefix, entries) \ - NV_ENUM_GENERATOR(NV_ENUM_GEN_SIZE, NV_ENUM_GEN_SIZE_FN, enum_name, prefix, entries) \ - NV_ENUM_GENERATOR(NV_ENUM_GEN_STRING, NV_ENUM_GEN_STRING_FN, enum_name, prefix, entries) \ - NV_ENUM_GENERATOR(NV_ENUM_GEN_FROM, NV_ENUM_GEN_FROM_FN, enum_name, prefix, entries) \ - NV_ENUM_GENERATOR(NV_ENUM_GEN_LO, NV_ENUM_GEN_LO_FN, enum_name, prefix, entries) \ - NV_ENUM_GENERATOR(NV_ENUM_GEN_COUNT, NV_ENUM_GEN_COUNT_FN, enum_name, prefix, entries) \ - NV_ENUM_GENERATOR(NV_ENUM_GEN_META, NV_ENUM_GEN_META_FN, enum_name, prefix, entries) \ + NV_ENUM_GENERATOR(NV_ENUM_GEN_TYPEDEF, NV_ENUM_GEN_TYPEDEF_FN, enum_name, prefix, entries) \ + NV_ENUM_GENERATOR(NV_ENUM_GEN_SIZE, NV_ENUM_GEN_SIZE_FN, enum_name, prefix, entries) \ + NV_ENUM_GENERATOR(NV_ENUM_GEN_STRING, NV_ENUM_GEN_STRING_FN, enum_name, prefix, entries) \ + NV_ENUM_GENERATOR(NV_ENUM_GEN_FROM, NV_ENUM_GEN_FROM_FN, enum_name, prefix, entries) \ + NV_ENUM_GENERATOR(NV_ENUM_GEN_LO, NV_ENUM_GEN_LO_FN, enum_name, prefix, entries) \ + NV_ENUM_GENERATOR(NV_ENUM_GEN_COUNT, NV_ENUM_GEN_COUNT_FN, enum_name, prefix, entries) \ + NV_ENUM_GENERATOR(NV_ENUM_GEN_META, NV_ENUM_GEN_META_FN, enum_name, prefix, entries) \ #else @@ -501,15 +501,15 @@ * @param enum_name Token - Root Enum Name * @param entries Macro - Enum Specification */ -#define NV_ENUM_DEF_PREFIX(prefix, enum_name, entries) \ - NV_ENUM_GEN_MAIN(NV_ENUM_DEPTH_0(enum_name, prefix, NV_ENUM_GEN_MAIN, NV_ENUM_GEN_MAIN_FN), entries) \ - NV_ENUM_GENERATOR(NV_ENUM_GEN_TYPEDEF, NV_ENUM_GEN_TYPEDEF_FN, enum_name, prefix, entries) \ - NV_ENUM_GENERATOR(NV_ENUM_GEN_SIZE, NV_ENUM_GEN_SIZE_FN, enum_name, prefix, entries) \ - NV_ENUM_GENERATOR(NV_ENUM_GEN_STRING, NV_ENUM_GEN_STRING_FN, enum_name, prefix, entries) \ - NV_ENUM_GENERATOR(NV_ENUM_GEN_FROM, NV_ENUM_GEN_FROM_FN, enum_name, prefix, entries) \ - NV_ENUM_GENERATOR(NV_ENUM_GEN_LO, NV_ENUM_GEN_LO_FN, enum_name, prefix, entries) \ - NV_ENUM_GENERATOR(NV_ENUM_GEN_COUNT, NV_ENUM_GEN_COUNT_FN, enum_name, prefix, entries) \ - NV_ENUM_GENERATOR(NV_ENUM_GEN_META, NV_ENUM_GEN_META_FN, enum_name, prefix, entries) \ +#define NV_ENUM_DEF_PREFIX(prefix, enum_name, entries) \ + NV_ENUM_GEN_MAIN(NV_ENUM_DEPTH_0(enum_name, prefix, NV_ENUM_GEN_MAIN, NV_ENUM_GEN_MAIN_FN), entries) \ + NV_ENUM_GENERATOR(NV_ENUM_GEN_TYPEDEF, NV_ENUM_GEN_TYPEDEF_FN, enum_name, prefix, entries) \ + NV_ENUM_GENERATOR(NV_ENUM_GEN_SIZE, NV_ENUM_GEN_SIZE_FN, enum_name, prefix, entries) \ + NV_ENUM_GENERATOR(NV_ENUM_GEN_STRING, NV_ENUM_GEN_STRING_FN, enum_name, prefix, entries) \ + NV_ENUM_GENERATOR(NV_ENUM_GEN_FROM, NV_ENUM_GEN_FROM_FN, enum_name, prefix, entries) \ + NV_ENUM_GENERATOR(NV_ENUM_GEN_LO, NV_ENUM_GEN_LO_FN, enum_name, prefix, entries) \ + NV_ENUM_GENERATOR(NV_ENUM_GEN_COUNT, NV_ENUM_GEN_COUNT_FN, enum_name, prefix, entries) \ + NV_ENUM_GENERATOR(NV_ENUM_GEN_META, NV_ENUM_GEN_META_FN, enum_name, prefix, entries) \ NV_ENUM_GENERATOR(NV_ENUM_GEN_ASSERT_MONOTONIC, NV_ENUM_GEN_ASSERT_MONOTONIC_FN, enum_name, prefix, entries) \ NV_ENUM_GENERATOR(NV_ENUM_GEN_ASSERT_IN_RANGE, NV_ENUM_GEN_ASSERT_IN_RANGE_FN, enum_name, prefix, entries) @@ -638,16 +638,16 @@ * @param[in] type identifier - Enum type name * @param[in] value lvalue - iterator holding current enum value */ -#define FOR_EACH_IN_ENUM(type, value) \ -{ \ - NvU32 localValue; \ +#define FOR_EACH_IN_ENUM(type, value) \ +{ \ + NvU32 localValue; \ for (localValue = value = NV_ENUM_LO(type); localValue <= NV_ENUM_HI(type); (value) = (type) (++localValue)) \ - { \ - if (!NV_ENUM_IS_CONTIGUOUS(type) && !NV_ENUM_IS(type, localValue)) \ + { \ + if (!NV_ENUM_IS_CONTIGUOUS(type) && !NV_ENUM_IS(type, localValue)) \ continue; #define FOR_EACH_IN_ENUM_END \ - } \ + } \ } /*! diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/inc/libraries/utils/nvassert.h nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/inc/libraries/utils/nvassert.h --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/inc/libraries/utils/nvassert.h 2023-10-25 20:20:45.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/inc/libraries/utils/nvassert.h 2024-03-05 22:13:08.000000000 +0000 @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 2015-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2015-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -824,6 +824,20 @@ NV_CHECK_OK_OR_ELSE_STR(status, level, expr, #expr, goto label) /** + * Check that an expression evaluates to NV_TRUE or else goto a label. + * + * @param[in] status The NV_STATUS variable to capture the status + * @param[in] level NV_PRINTF LEVEL to print at + * @param[in] expr Expression that evaluates to either NV_TRUE or NV_FALSE. + * @param[in] error Error to be reflected in @p status when @p expr evaluates + to NV_FALSE. + * @param[in] label Label to jump to when @p expr evaluates to NV_FALSE. +*/ +#define NV_CHECK_TRUE_OR_GOTO(status, level, expr, error, label) \ + NV_CHECK_OK_OR_ELSE_STR(status, level, ((expr) ? NV_OK : (error)), \ + #expr, goto label); + +/** * Check that an expression evaluates to NV_OK or return the status. * * @param[in] level NV_PRINTF LEVEL to print at diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/inc/libraries/utils/nvbitvector.h nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/inc/libraries/utils/nvbitvector.h --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/inc/libraries/utils/nvbitvector.h 2023-10-25 20:20:45.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/inc/libraries/utils/nvbitvector.h 2024-03-05 22:13:08.000000000 +0000 @@ -67,7 +67,7 @@ * .-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-. * 0 |1 | * 1 | 1| - * `-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-' + * `-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-' * * Thus, in order to conceptually model an NV_BITVECTOR horizontally as * a continual ordered list of bits, one would have to write the @@ -240,20 +240,20 @@ } \ } -#define FOR_EACH_IN_BITVECTOR_PAIR(pBitVectorA, indexA, pBitVectorB, indexB)\ - { \ - MAKE_ANON_BITVECTOR(sizeof(((pBitVectorA)->last->_))) localMaskA; \ - bitVectorCopy(&localMaskA, (pBitVectorA)); \ - MAKE_ANON_BITVECTOR(sizeof(((pBitVectorB)->last->_))) localMaskB; \ - bitVectorCopy(&localMaskB, (pBitVectorB)); \ - for ((indexA) = bitVectorCountTrailingZeros(&localMaskA), \ - (indexB) = bitVectorCountTrailingZeros(&localMaskB); \ - !bitVectorTestAllCleared(&localMaskA) && \ - !bitVectorTestAllCleared(&localMaskB); \ - bitVectorClr(&localMaskA, (indexA)), \ - bitVectorClr(&localMaskB, (indexB)), \ - (indexA) = bitVectorCountTrailingZeros(&localMaskA), \ - (indexB) = bitVectorCountTrailingZeros(&localMaskB)) \ +#define FOR_EACH_IN_BITVECTOR_PAIR(pBitVectorA, indexA, pBitVectorB, indexB) \ + { \ + MAKE_ANON_BITVECTOR(sizeof(((pBitVectorA)->last->_))) localMaskA; \ + bitVectorCopy(&localMaskA, (pBitVectorA)); \ + MAKE_ANON_BITVECTOR(sizeof(((pBitVectorB)->last->_))) localMaskB; \ + bitVectorCopy(&localMaskB, (pBitVectorB)); \ + for ((indexA) = bitVectorCountTrailingZeros(&localMaskA), \ + (indexB) = bitVectorCountTrailingZeros(&localMaskB); \ + !bitVectorTestAllCleared(&localMaskA) && \ + !bitVectorTestAllCleared(&localMaskB); \ + bitVectorClr(&localMaskA, (indexA)), \ + bitVectorClr(&localMaskB, (indexB)), \ + (indexA) = bitVectorCountTrailingZeros(&localMaskA), \ + (indexB) = bitVectorCountTrailingZeros(&localMaskB)) \ { #define FOR_EACH_IN_BITVECTOR_PAIR_END() \ diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/inc/libraries/utils/nvmacro.h nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/inc/libraries/utils/nvmacro.h --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/inc/libraries/utils/nvmacro.h 2023-10-25 20:20:45.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/inc/libraries/utils/nvmacro.h 2024-03-05 22:13:08.000000000 +0000 @@ -182,7 +182,7 @@ #define _NV_FOREACH_ARG_15(X, _1, _2, _3, _4, _5, _6, _7, _8, _9, _10, _11, _12, _13, _14, _15) \ X(_1), X(_2), X(_3), X(_4), X(_5), X(_6), X(_7), X(_8), X(_9), X(_10), X(_11), X(_12), X(_13), X(_14), X(_15) #define _NV_FOREACH_ARG_16(X, _1, _2, _3, _4, _5, _6, _7, _8, _9, _10, _11, _12, _13, _14, _15, _16) \ - X(_1), X(_2), X(_3), X(_4), X(_5), X(_6), X(_7), X(_8), X(_9), X(_10), X(_11), X(_12), X(_13), X(_14), X(_15), X(_16) + X(_1), X(_2), X(_3), X(_4), X(_5), X(_6), X(_7), X(_8), X(_9), X(_10), X(_11), X(_12), X(_13), X(_14), X(_15), X(_16) // Iterating over empty list is unsupported. Give a semi-readable error. #define _NV_FOREACH_ARG_NOCOMMA_0(X) NV_FOREACH_NOCOMMA_ERROR_argument_list_emtpy @@ -218,16 +218,16 @@ #define _NV_FOREACH_ARG_NOCOMMA_15(X, _1, _2, _3, _4, _5, _6, _7, _8, _9, _10, _11, _12, _13, _14, _15) \ X(_1) X(_2) X(_3) X(_4) X(_5) X(_6) X(_7) X(_8) X(_9) X(_10) X(_11) X(_12) X(_13) X(_14) X(_15) #define _NV_FOREACH_ARG_NOCOMMA_16(X, _1, _2, _3, _4, _5, _6, _7, _8, _9, _10, _11, _12, _13, _14, _15, _16) \ - X(_1) X(_2) X(_3) X(_4) X(_5) X(_6) X(_7) X(_8) X(_9) X(_10) X(_11) X(_12) X(_13) X(_14) X(_15) X(_16) + X(_1) X(_2) X(_3) X(_4) X(_5) X(_6) X(_7) X(_8) X(_9) X(_10) X(_11) X(_12) X(_13) X(_14) X(_15) X(_16) /// @endcond /// @cond NV_MACROS_COMPILE_TIME_TESTS // -// What follows are a couple of compile time smoke tests that will let us know +// What follows are a couple of compile time smoke tests that will let us know // if the given compiler does not properly implement these macros. // These are disabled by default in the interest of compile time. -// +// #if defined(NVMACRO_DO_COMPILETIME_TESTS) #if NV_NUM_ARGS(a) != 1 #error "[NvMacros CT Test] NV_NUM_ARGS fails when given 1 args" diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/inc/libraries/utils/nvrange.h nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/inc/libraries/utils/nvrange.h --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/inc/libraries/utils/nvrange.h 2023-10-25 20:20:46.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/inc/libraries/utils/nvrange.h 2024-03-05 22:13:08.000000000 +0000 @@ -33,7 +33,7 @@ * \anchor NV_RANGE_1 * @defgroup NV_RANGE NV_RANGE * - * @brief Range is a sequence of unsigned 64 bit integers, represented by its + * @brief Range is a sequence of unsigned 64 bit integers, represented by its * lower and upper bounds, inclusive. * * @details Range is a general purpose data structure utility. @@ -44,15 +44,15 @@ * * @note If a range is declared like Range r = {0x0, 0x2} it consist * of elements 0x0, 0x1 and 0x2 , i.e. Range = [lo, hi] ! - * + * * > There are 4 possible options * > -# (lo, hi) lo+1 .. hi-1 * > -# [lo, hi) lo .. hi-1 * > -# (lo, hi] lo+1 .. hi * > -# [lo, hi] lo .. hi * - * Notice that only option 4 is capable of describing a full range. - * Full range would be 0x0..NvU64_MAX, where + * Notice that only option 4 is capable of describing a full range. + * Full range would be 0x0..NvU64_MAX, where * NvU64_MAX = 0xFFFFFFFFFFFFFFFF. * * @{ @@ -81,8 +81,8 @@ /** * @brief Calculate range length in bytes. * - * @warning If the range is max, i.e. from 0 to NvU64_MAX, calling this - * function would result in overflow since range length is calculated + * @warning If the range is max, i.e. from 0 to NvU64_MAX, calling this + * function would result in overflow since range length is calculated * as hi-lo+1. * * @par Example: @@ -96,12 +96,12 @@ /** * @brief Creates a range * - * @details This is useful since on some compilers the following code won't + * @details This is useful since on some compilers the following code won't * work: `rangeLength({0, 100})`. * However, `rangeLength(rangeMake(0, 100))` will always work. - * - * @Returns Range of elements from and including \a lo to and - * including \a hi, i.e. [lo, hi] + * + * @Returns Range of elements from and including \a lo to and + * including \a hi, i.e. [lo, hi] */ static NV_INLINE NV_RANGE rangeMake(NvU64 lo, NvU64 hi) { @@ -124,7 +124,7 @@ /** * @brief Check if \a range1 contains \a range2. - * + * * @param[in] range1 Container. * @param[in] range2 Containee. * @@ -144,8 +144,8 @@ */ static NV_INLINE NvBool rangeOverlaps(NV_RANGE range1, NV_RANGE range2) { - return (range1.lo <= range2.lo && range2.lo <= range1.hi) - || + return (range1.lo <= range2.lo && range2.lo <= range1.hi) + || (range1.lo <= range2.hi && range2.hi <= range1.hi) || (range2.lo <= range1.lo && range1.lo <= range2.hi) @@ -180,7 +180,7 @@ * <0 - \a range1's lower bound is less than \a range2's lower bound, * >0 - \a range2's lower bound is greater than \a range2's lower bound. * - * @warning If function returns 0 that does not mean that ranges are equal, + * @warning If function returns 0 that does not mean that ranges are equal, * just that their lower bounds are equal! * * @par Example: @@ -198,14 +198,14 @@ /** * @brief Merge two ranges into one. - * - * @returns Merged range. If two ranges have no intersection + * + * @returns Merged range. If two ranges have no intersection * the returned range will be empty. * * @note Empty range is range with lo > hi. * * @par Example: - * @snippet nv_range-test.cpp rangeMergeExample + * @snippet nv_range-test.cpp rangeMergeExample */ static NV_INLINE NV_RANGE rangeMerge(NV_RANGE range1, NV_RANGE range2) { @@ -232,11 +232,11 @@ } /** - * @brief Checks if \a range1 borders with \a range2, i.e. \a range1.lo == + * @brief Checks if \a range1 borders with \a range2, i.e. \a range1.lo == * \a range2.hi+1 or \a range2.lo == \a range1.hi+1 - * + * * @note [a,b] borders with [b+1,c] where a < b < c - * + * */ static NV_INLINE NvBool rangeBorders(NV_RANGE range1, NV_RANGE range2) { @@ -249,7 +249,7 @@ } /** - * @brief Splits \a pBigRange + * @brief Splits \a pBigRange * * @param[in] pBigRange Pointer to starting range. * @param[in] rangeToSplit Range to split the first range over. @@ -258,10 +258,10 @@ * @par Example: * @snippet nv_range-test.cpp rangeSplitExample */ -static NV_INLINE NV_STATUS rangeSplit(NV_RANGE *pBigRange, +static NV_INLINE NV_STATUS rangeSplit(NV_RANGE *pBigRange, NV_RANGE rangeToSplit, NV_RANGE *pSecondPartAfterSplit) { - if (rangeIsEmpty(*pBigRange) || rangeIsEmpty(rangeToSplit) || + if (rangeIsEmpty(*pBigRange) || rangeIsEmpty(rangeToSplit) || !rangeContains(*pBigRange, rangeToSplit)) { return NV_ERR_INVALID_ARGUMENT; diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/interface/deprecated/rmapi_deprecated.h nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/interface/deprecated/rmapi_deprecated.h --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/interface/deprecated/rmapi_deprecated.h 2023-10-25 20:20:46.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/interface/deprecated/rmapi_deprecated.h 2024-03-05 22:13:08.000000000 +0000 @@ -65,7 +65,7 @@ typedef struct _DEPRECATED_CONTEXT { NV_STATUS (*RmAlloc)(struct _DEPRECATED_CONTEXT *pContext, NvHandle hClient, NvHandle hParent, - NvHandle *phObject, NvU32 hClass, void *pAllocParams); + NvHandle *phObject, NvU32 hClass, void *pAllocParams, NvU32 paramsSize); NV_STATUS (*RmControl)(struct _DEPRECATED_CONTEXT *pContext, NvHandle hClient, NvHandle hObject, NvU32 cmd, void *pParams, NvU32 paramsSize); diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/interface/deprecated/rmapi_deprecated_allocmemory.c nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/interface/deprecated/rmapi_deprecated_allocmemory.c --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/interface/deprecated/rmapi_deprecated_allocmemory.c 2023-10-25 20:20:46.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/interface/deprecated/rmapi_deprecated_allocmemory.c 2024-03-05 22:13:08.000000000 +0000 @@ -36,6 +36,8 @@ #include "ctrl/ctrl2080/ctrl2080fb.h" // NV2080_CTRL_FB_INFO +#include + typedef NV_STATUS RmAllocMemoryFunc( DEPRECATED_CONTEXT *pContext, NvHandle hClient, @@ -165,7 +167,7 @@ *pAddress = NvP64_NULL; - status = pContext->RmAlloc(pContext, hClient, hParent, &hMemory, hClass, &allocParams); + status = pContext->RmAlloc(pContext, hClient, hParent, &hMemory, hClass, &allocParams, sizeof(allocParams)); if (status != NV_OK) return status; @@ -214,7 +216,7 @@ // Try with NV01_MEMORY_SYSTEM_DYNAMIC for NV01_DEVICE_0 parents status = pContext->RmAlloc(pContext, hClient, hParent, &hMemory, - NV01_MEMORY_SYSTEM_DYNAMIC, &allocParams); + NV01_MEMORY_SYSTEM_DYNAMIC, &allocParams, sizeof(allocParams)); *pLimit = allocParams.limit; @@ -255,7 +257,7 @@ return NV_ERR_INVALID_FLAGS; } - status = pContext->RmAlloc(pContext, hClient, hParent, &hMemory, hClass, &allocParams); + status = pContext->RmAlloc(pContext, hClient, hParent, &hMemory, hClass, &allocParams, sizeof(allocParams)); return status; } @@ -324,7 +326,7 @@ // // First attempt: try to allocate NV01_MEMORY_LOCAL_PHYSICAL - status = pContext->RmAlloc(pContext, hClient, hParent, &hMemory, NV01_MEMORY_LOCAL_PHYSICAL, &allocParams); + status = pContext->RmAlloc(pContext, hClient, hParent, &hMemory, NV01_MEMORY_LOCAL_PHYSICAL, &allocParams, sizeof(allocParams)); if (status == NV_OK) { @@ -357,7 +359,7 @@ // user-mode clients previously received hMemory of entire FB) // status = pContext->RmAlloc(pContext, hClient, hParent, &hMemory, - NV01_MEMORY_SYSTEM_DYNAMIC, &virtAllocParams); + NV01_MEMORY_SYSTEM_DYNAMIC, &virtAllocParams, sizeof(virtAllocParams)); } return status; @@ -381,7 +383,7 @@ *pLimit = 0xFFFFFFFF; // not used by clients - return pContext->RmAlloc(pContext, hClient, hParent, &hMemory, hClass, 0); + return pContext->RmAlloc(pContext, hClient, hParent, &hMemory, hClass, NULL, 0); } static NV_STATUS @@ -456,7 +458,7 @@ COPY_FIELD(size); COPY_FIELD(align); - status = pContext->RmAlloc(pContext, hClient, hParent, &hMemory, hClass, &allocParams); + status = pContext->RmAlloc(pContext, hClient, hParent, &hMemory, hClass, &allocParams, sizeof(allocParams)); done: if (pPageArray) @@ -513,7 +515,7 @@ COPY_FLA_FIELD(hExportHandle); COPY_FLA_FIELD(hExportClient); - status = pContext->RmAlloc(pContext, hClient, hParent, &hMemory, hClass, &allocParams); + status = pContext->RmAlloc(pContext, hClient, hParent, &hMemory, hClass, &allocParams, sizeof(allocParams)); done: if (pMemoryFla) @@ -541,5 +543,5 @@ NvU64 *pLimit ) { - return pContext->RmAlloc(pContext, hClient, hParent, &hMemory, hClass, 0); + return pContext->RmAlloc(pContext, hClient, hParent, &hMemory, hClass, NULL, 0); } diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/interface/deprecated/rmapi_deprecated_misc.c nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/interface/deprecated/rmapi_deprecated_misc.c --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/interface/deprecated/rmapi_deprecated_misc.c 2023-10-25 20:20:46.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/interface/deprecated/rmapi_deprecated_misc.c 2024-03-05 22:13:09.000000000 +0000 @@ -40,7 +40,7 @@ ) { pArgs->status = pContext->RmAlloc(pContext, pArgs->hRoot, pArgs->hObjectParent, - &pArgs->hObjectNew, pArgs->hClass, 0); + &pArgs->hObjectNew, pArgs->hClass, NULL, 0); } void @@ -62,7 +62,7 @@ vblankArgs.pParm2 = pArgs->pParm2; status = pContext->RmAlloc(pContext, pArgs->hClient, pArgs->hDevice, - &pArgs->hVblank, NV9010_VBLANK_CALLBACK, &vblankArgs); + &pArgs->hVblank, NV9010_VBLANK_CALLBACK, &vblankArgs, sizeof(vblankArgs)); } else { @@ -113,7 +113,8 @@ status = pContext->RmAlloc(pContext, hClient, hCtxDmaParent, &pArgs->hObjectNew, NV01_MEMORY_VIRTUAL, - &allocVirtualParams); + &allocVirtualParams, + sizeof(allocVirtualParams)); goto done; } @@ -124,7 +125,7 @@ allocParams.limit = pArgs->limit; status = pContext->RmAlloc(pContext, hClient, hCtxDmaParent, - &pArgs->hObjectNew, pArgs->hClass, &allocParams); + &pArgs->hObjectNew, pArgs->hClass, &allocParams, sizeof(allocParams)); done: pArgs->status = status; diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/interface/deprecated/rmapi_deprecated_utils.c nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/interface/deprecated/rmapi_deprecated_utils.c --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/interface/deprecated/rmapi_deprecated_utils.c 2023-10-25 20:20:46.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/interface/deprecated/rmapi_deprecated_utils.c 2024-03-05 22:13:09.000000000 +0000 @@ -28,6 +28,8 @@ #include "ctrl/ctrl0080/ctrl0080gpu.h" // NV0080_CTRL_CMD_GPU_FIND_SUBDEVICE_HANDLE #include "nvos.h" +#include + NV_STATUS RmDeprecatedGetHandleParent ( @@ -135,7 +137,7 @@ *pHSubDevice = 0; - status = pContext->RmAlloc(pContext, hClient, hDeviceOrSubDevice, pHSubDevice, NV20_SUBDEVICE_0, 0); + status = pContext->RmAlloc(pContext, hClient, hDeviceOrSubDevice, pHSubDevice, NV20_SUBDEVICE_0, NULL, 0); return status; } @@ -163,10 +165,12 @@ } else { + // // Object does not exist yet, allocate. - void *pAllocParams = (void*)0; // TODO: Fill for classes that need them + // TODO: Fill alloc params for classes that need them + // status = pContext->RmAlloc(pContext, hClient, *pHObject, - pHObject, classId, pAllocParams); + pHObject, classId, NULL, 0); } return status; } diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/interface/deprecated/rmapi_deprecated_vidheapctrl.c nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/interface/deprecated/rmapi_deprecated_vidheapctrl.c --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/interface/deprecated/rmapi_deprecated_vidheapctrl.c 2023-10-25 20:20:47.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/interface/deprecated/rmapi_deprecated_vidheapctrl.c 2024-03-05 22:13:09.000000000 +0000 @@ -29,6 +29,7 @@ #include "class/cl0071.h" // NV01_MEMORY_SYSTEM_OS_DESCRIPTOR #include "class/cl50a0.h" // NV50_MEMORY_VIRTUAL #include "class/cl0040.h" // NV01_MEMORY_LOCAL_USER +#include "class/cl0042.h" // NV_MEMORY_EXTENDED_USER #include "ctrl/ctrl0041.h" // NV04_MEMORY #include "ctrl/ctrl2080/ctrl2080fb.h" // NV2080_CTRL_FB_INFO @@ -41,7 +42,6 @@ } RmVidHeapControlEntry; // forward declarations -static NV_STATUS _nvos32FunctionAllocDepthWidthHeight(DEPRECATED_CONTEXT *, NVOS32_PARAMETERS *); static NV_STATUS _nvos32FunctionAllocSize(DEPRECATED_CONTEXT *, NVOS32_PARAMETERS *); static NV_STATUS _nvos32FunctionAllocSizeRange(DEPRECATED_CONTEXT *, NVOS32_PARAMETERS *); static NV_STATUS _nvos32FunctionAllocTiledPitchHeight(DEPRECATED_CONTEXT *, NVOS32_PARAMETERS *); @@ -56,7 +56,6 @@ static const RmVidHeapControlEntry rmVidHeapControlTable[] = { - { NVOS32_FUNCTION_ALLOC_DEPTH_WIDTH_HEIGHT, _nvos32FunctionAllocDepthWidthHeight }, { NVOS32_FUNCTION_ALLOC_SIZE, _nvos32FunctionAllocSize }, { NVOS32_FUNCTION_ALLOC_SIZE_RANGE, _nvos32FunctionAllocSizeRange }, { NVOS32_FUNCTION_ALLOC_TILED_PITCH_HEIGHT, _nvos32FunctionAllocTiledPitchHeight }, @@ -144,7 +143,7 @@ externalClassId = NV01_MEMORY_SYSTEM; status = pContext->RmAlloc(pContext, hClient, hDevice, phMemory, externalClassId, - pUserParams); + pUserParams, sizeof(*pUserParams)); pArgs->free = 0; pArgs->total = 0; @@ -153,68 +152,6 @@ } static NV_STATUS -_nvos32FunctionAllocDepthWidthHeight -( - DEPRECATED_CONTEXT *pContext, - NVOS32_PARAMETERS *pArgs -) -{ - NV_MEMORY_ALLOCATION_PARAMS allocParams = {0}; - NvU32 byteWidth; - NV_STATUS status = NV_OK; - - // For NV3, scanline alignment is 32 bytes. - byteWidth = ((pArgs->data.AllocDepthWidthHeight.width * pArgs->data.AllocDepthWidthHeight.depth) + 7) >> 3; - pArgs->data.AllocDepthWidthHeight.size = pArgs->data.AllocDepthWidthHeight.height * ((byteWidth + 31) & ~31); - - // Range begin/end are captured only if the appropriate flag bit is set. - if (pArgs->data.AllocDepthWidthHeight.flags & NVOS32_ALLOC_FLAGS_USE_BEGIN_END) - { - allocParams.rangeLo = pArgs->data.AllocDepthWidthHeight.rangeBegin; - allocParams.rangeHi = pArgs->data.AllocDepthWidthHeight.rangeEnd; - } - else - { - allocParams.rangeLo = 0; - allocParams.rangeHi = 0; - } - - #define ALLOC_DEPTH_WIDTH_HEIGHT_PARAMS(_IN, _IN_OUT) \ - _IN(owner, AllocDepthWidthHeight.owner) \ - _IN(type, AllocDepthWidthHeight.type) \ - _IN(flags, AllocDepthWidthHeight.flags) \ - _IN(height, AllocDepthWidthHeight.height) \ - _IN(width, AllocDepthWidthHeight.width) \ - _IN_OUT(size, AllocDepthWidthHeight.size) \ - _IN(alignment, AllocDepthWidthHeight.alignment) \ - _IN_OUT(offset, AllocDepthWidthHeight.offset) \ - _IN_OUT(attr, AllocDepthWidthHeight.attr) \ - _IN_OUT(attr2, AllocDepthWidthHeight.attr2) \ - _IN_OUT(format, AllocDepthWidthHeight.format) \ - _IN_OUT(limit, AllocDepthWidthHeight.limit) \ - _IN_OUT(address, AllocDepthWidthHeight.address) \ - _IN_OUT(comprCovg, AllocDepthWidthHeight.comprCovg) \ - _IN_OUT(zcullCovg, AllocDepthWidthHeight.zcullCovg) \ - _IN_OUT(ctagOffset, AllocDepthWidthHeight.ctagOffset) - - ALLOC_DEPTH_WIDTH_HEIGHT_PARAMS(_COPY_IN, _COPY_IN); - - pArgs->data.AllocDepthWidthHeight.partitionStride = 256; - - // get memory - status = _rmVidHeapControlAllocCommon(pContext, - pArgs, - pArgs->hRoot, - pArgs->hObjectParent, - &pArgs->data.AllocDepthWidthHeight.hMemory, - &allocParams); - - ALLOC_DEPTH_WIDTH_HEIGHT_PARAMS(_NO_COPY, _COPY_OUT); - - return status; -} - -static NV_STATUS _nvos32FunctionAllocSize ( DEPRECATED_CONTEXT *pContext, @@ -603,7 +540,8 @@ pArgs->hObjectParent, &pArgs->data.HwAlloc.allochMemory, NV01_MEMORY_HW_RESOURCES, - &allocParams); + &allocParams, + sizeof(allocParams)); pArgs->data.HwAlloc.hResourceHandle = pArgs->data.HwAlloc.allochMemory; @@ -654,7 +592,8 @@ pArgs->hObjectParent, &pArgs->data.AllocOsDesc.hMemory, NV01_MEMORY_SYSTEM_OS_DESCRIPTOR, - &allocParams); + &allocParams, + sizeof(allocParams)); return status; } diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/interface/deprecated/rmapi_gss_legacy_control.c nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/interface/deprecated/rmapi_gss_legacy_control.c --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/interface/deprecated/rmapi_gss_legacy_control.c 2023-10-25 20:20:47.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/interface/deprecated/rmapi_gss_legacy_control.c 2024-03-05 22:13:09.000000000 +0000 @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 2019-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2019-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -22,10 +22,11 @@ */ #include "deprecated/rmapi_deprecated.h" -#include "finn_rm_api.h" #include "gpu/gpu.h" #include "core/locks.h" +#include "g_finn_rm_api.h" + /*! * Some clients are still making these legacy GSS controls. We no longer support these in RM, * but until all the numerous tools are updated to use alternative APIs, just forward all of them @@ -43,6 +44,7 @@ NV_STATUS status = NV_OK; GPU_MASK gpuMaskRelease = 0; void *pKernelParams = NULL; + NvBool bApiLockTaken = NV_FALSE; NV_ASSERT_OR_RETURN((pArgs->cmd & RM_GSS_LEGACY_MASK), NV_ERR_INVALID_STATE); @@ -53,18 +55,6 @@ return NV_ERR_INSUFFICIENT_PERMISSIONS; } - NV_CHECK_OK_OR_ELSE(status, - LEVEL_ERROR, - serverGetClientUnderLock(&g_resServ, pArgs->hClient, &pClient), - return NV_ERR_INVALID_ARGUMENT); - - NV_CHECK_OK_OR_ELSE(status, - LEVEL_ERROR, - gpuGetByHandle(pClient, pArgs->hObject, NULL, &pGpu), - return NV_ERR_INVALID_ARGUMENT); - - RM_API *pRmApi = GPU_GET_PHYSICAL_RMAPI(pGpu); - if (pSecInfo->paramLocation == PARAM_LOCATION_USER) { pKernelParams = portMemAllocNonPaged(pArgs->paramsSize); @@ -83,6 +73,24 @@ pKernelParams = (void*)pArgs->params; } + status = rmapiLockAcquire(RMAPI_LOCK_FLAGS_READ, RM_LOCK_MODULES_CLIENT); + if (status != NV_OK) + goto done; + + bApiLockTaken = NV_TRUE; + + NV_CHECK_OK_OR_GOTO(status, + LEVEL_ERROR, + serverGetClientUnderLock(&g_resServ, pArgs->hClient, &pClient), + done); + + NV_CHECK_OK_OR_GOTO(status, + LEVEL_ERROR, + gpuGetByHandle(pClient, pArgs->hObject, NULL, &pGpu), + done); + + osRefGpuAccessNeeded(pGpu->pOsGpuInfo); + status = rmGpuGroupLockAcquire(pGpu->gpuInstance, GPU_LOCK_GRP_SUBDEVICE, GPUS_LOCK_FLAGS_NONE, @@ -91,6 +99,7 @@ if (status != NV_OK) goto done; + RM_API *pRmApi = GPU_GET_PHYSICAL_RMAPI(pGpu); status = pRmApi->Control(pRmApi, pArgs->hClient, pArgs->hObject, @@ -104,6 +113,16 @@ rmGpuGroupLockRelease(gpuMaskRelease, GPUS_LOCK_FLAGS_NONE); } + if (bApiLockTaken) + { + if (pGpu != NULL) + { + osUnrefGpuAccessNeeded(pGpu->pOsGpuInfo); + } + + rmapiLockRelease(); + } + if (pSecInfo->paramLocation == PARAM_LOCATION_USER) { if (status == NV_OK) diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/interface/nv-firmware-registry.h nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/interface/nv-firmware-registry.h --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/interface/nv-firmware-registry.h 1970-01-01 00:00:00.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/interface/nv-firmware-registry.h 2024-03-05 22:13:09.000000000 +0000 @@ -0,0 +1,83 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +// +// This file holds GPU firmware related registry key definitions that are +// shared between Windows and Unix +// + +#ifndef NV_FIRMWARE_REGISTRY_H +#define NV_FIRMWARE_REGISTRY_H + +// +// Registry key that when enabled, will enable use of GPU firmware. +// +// Possible mode values: +// 0 - Do not enable GPU firmware +// 1 - Enable GPU firmware +// 2 - (Default) Use the default enablement policy for GPU firmware +// +// Setting this to anything other than 2 will alter driver firmware- +// enablement policies, possibly disabling GPU firmware where it would +// have otherwise been enabled by default. +// +// Policy bits: +// +// POLICY_ALLOW_FALLBACK: +// As the normal behavior is to fail GPU initialization if this registry +// entry is set in such a way that results in an invalid configuration, if +// instead the user would like the driver to automatically try to fallback +// to initializing the failing GPU with firmware disabled, then this bit can +// be set (ex: 0x11 means try to enable GPU firmware but fall back if needed). +// Note that this can result in a mixed mode configuration (ex: GPU0 has +// firmware enabled, but GPU1 does not). +// +#define NV_REG_STR_ENABLE_GPU_FIRMWARE "EnableGpuFirmware" + +#define NV_REG_ENABLE_GPU_FIRMWARE_MODE_MASK 0x0000000F +#define NV_REG_ENABLE_GPU_FIRMWARE_MODE_DISABLED 0x00000000 +#define NV_REG_ENABLE_GPU_FIRMWARE_MODE_ENABLED 0x00000001 +#define NV_REG_ENABLE_GPU_FIRMWARE_MODE_DEFAULT 0x00000002 + +#define NV_REG_ENABLE_GPU_FIRMWARE_POLICY_MASK 0x000000F0 +#define NV_REG_ENABLE_GPU_FIRMWARE_POLICY_ALLOW_FALLBACK 0x00000010 + +#define NV_REG_ENABLE_GPU_FIRMWARE_DEFAULT_VALUE 0x00000012 + +// +// Registry key that when enabled, will send GPU firmware logs +// to the system log, when possible. +// +// Possible values: +// 0 - Do not send GPU firmware logs to the system log +// 1 - Enable sending of GPU firmware logs to the system log +// 2 - (Default) Enable sending of GPU firmware logs to the system log for +// the debug kernel driver build only +// +#define NV_REG_STR_ENABLE_GPU_FIRMWARE_LOGS "EnableGpuFirmwareLogs" + +#define NV_REG_ENABLE_GPU_FIRMWARE_LOGS_DISABLE 0x00000000 +#define NV_REG_ENABLE_GPU_FIRMWARE_LOGS_ENABLE 0x00000001 +#define NV_REG_ENABLE_GPU_FIRMWARE_LOGS_ENABLE_ON_DEBUG 0x00000002 + +#endif // NV_FIRMWARE_REGISTRY_H diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/interface/nv_firmware_types.h nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/interface/nv_firmware_types.h --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/interface/nv_firmware_types.h 2023-10-25 20:20:47.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/interface/nv_firmware_types.h 1970-01-01 00:00:00.000000000 +0000 @@ -1,34 +0,0 @@ -/* - * SPDX-FileCopyrightText: Copyright (c) 2021 NVIDIA CORPORATION & AFFILIATES. All rights reserved. - * SPDX-License-Identifier: MIT - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER - * DEALINGS IN THE SOFTWARE. - */ - -#ifndef NV_FIRMWARE_TYPES_H -#define NV_FIRMWARE_TYPES_H - -typedef enum { - NV_FIRMWARE_MODE_DISABLED = 0, - NV_FIRMWARE_MODE_ENABLED = 1, - NV_FIRMWARE_MODE_DEFAULT = 2, - NV_FIRMWARE_MODE_INVALID = 0xFF -} NvFirmwareMode; - -#endif // NV_FIRMWARE_TYPES_H diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/interface/nv_sriov_defines.h nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/interface/nv_sriov_defines.h --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/interface/nv_sriov_defines.h 2023-10-25 20:20:47.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/interface/nv_sriov_defines.h 2024-03-05 22:13:09.000000000 +0000 @@ -47,14 +47,29 @@ #define NV_DOORBELL_NOTIFY_LEAF_VF_MASK (NVBIT(NV_DOORBELL_NOTIFY_LEAF_VF_RPC_SETUP_HANDLE) | \ NVBIT(NV_DOORBELL_NOTIFY_LEAF_VF_RPC_MESSAGE_HANDLE)) +// Top half serviced interrupts (serviced by both guest and host) + +#define NV_DOORBELL_NOTIFY_LEAF_SERVICE_REPLAYABLE_FAULT_FLUSH_REQUEST 2:2 +#define NV_DOORBELL_NOTIFY_LEAF_SERVICE_REPLAYABLE_FAULT_FLUSH_REQUEST_EN (0x1) +#define NV_DOORBELL_NOTIFY_LEAF_SERVICE_REPLAYABLE_FAULT_FLUSH_REQUEST_DIS (0x0) +#define NV_DOORBELL_NOTIFY_LEAF_SERVICE_REPLAYABLE_FAULT_FLUSH_HANDLE (0 ? NV_DOORBELL_NOTIFY_LEAF_SERVICE_REPLAYABLE_FAULT_FLUSH_REQUEST) + +#define NV_DOORBELL_NOTIFY_LEAF_TOP_HALF_MASK NVBIT(NV_DOORBELL_NOTIFY_LEAF_SERVICE_REPLAYABLE_FAULT_FLUSH_HANDLE) + // Host PF interrupts +#define NV_DOORBELL_NOTIFY_LEAF_SERVICE_TMR_REQUEST 3:3 +#define NV_DOORBELL_NOTIFY_LEAF_SERVICE_TMR_REQUEST_EN (0x1) +#define NV_DOORBELL_NOTIFY_LEAF_SERVICE_TMR_REQUEST_DIS (0x0) +#define NV_DOORBELL_NOTIFY_LEAF_SERVICE_TMR_HANDLE (0 ? NV_DOORBELL_NOTIFY_LEAF_SERVICE_TMR_REQUEST) + #define NV_DOORBELL_NOTIFY_LEAF_SERVICE_NON_REPLAYABLE_FAULT_REQUEST 16:16 #define NV_DOORBELL_NOTIFY_LEAF_SERVICE_NON_REPLAYABLE_FAULT_REQUEST_EN (0x1) #define NV_DOORBELL_NOTIFY_LEAF_SERVICE_NON_REPLAYABLE_FAULT_REQUEST_DIS (0x0) #define NV_DOORBELL_NOTIFY_LEAF_SERVICE_NON_REPLAYABLE_FAULT_HANDLE (0 ? NV_DOORBELL_NOTIFY_LEAF_SERVICE_NON_REPLAYABLE_FAULT_REQUEST) -#define NV_DOORBELL_NOTIFY_LEAF_HOST_PF_MASK NVBIT(NV_DOORBELL_NOTIFY_LEAF_SERVICE_NON_REPLAYABLE_FAULT_HANDLE) +#define NV_DOORBELL_NOTIFY_LEAF_HOST_PF_MASK (NVBIT(NV_DOORBELL_NOTIFY_LEAF_SERVICE_NON_REPLAYABLE_FAULT_HANDLE) | \ + NVBIT(NV_DOORBELL_NOTIFY_LEAF_SERVICE_TMR_HANDLE)) // Host VF interrupts diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/interface/nv_uvm_types.h nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/interface/nv_uvm_types.h --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/interface/nv_uvm_types.h 2023-10-25 20:20:47.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/interface/nv_uvm_types.h 2024-03-05 22:13:09.000000000 +0000 @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 2014-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2014-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -92,6 +92,7 @@ typedef struct uvmGpuSession_tag *uvmGpuSessionHandle; // gpuSessionHandle typedef struct uvmGpuDevice_tag *uvmGpuDeviceHandle; // gpuDeviceHandle typedef struct uvmGpuAddressSpace_tag *uvmGpuAddressSpaceHandle; // gpuAddressSpaceHandle +typedef struct uvmGpuTsg_tag *uvmGpuTsgHandle; // gpuTsgHandle typedef struct uvmGpuChannel_tag *uvmGpuChannelHandle; // gpuChannelHandle typedef struct uvmGpuCopyEngine_tag *uvmGpuCopyEngineHandle; // gpuObjectHandle @@ -110,7 +111,7 @@ NvBool deviceDescendant; // Out: Page size associated with the phys alloc. - NvU32 pageSize; + NvU64 pageSize; // Out: Set to TRUE, if the allocation is contiguous. NvBool contig; @@ -280,6 +281,16 @@ // to kick off the new work. // volatile NvU32 *pWorkSubmissionToken; + + // GPU VAs of both GPFIFO and GPPUT are needed in Confidential Computing + // so a channel can be controlled via another channel (SEC2 or WLC/LCIC) + NvU64 gpFifoGpuVa; + NvU64 gpPutGpuVa; + NvU64 gpGetGpuVa; + // GPU VA of work submission offset is needed in Confidential Computing + // so CE channels can ring doorbell of other channels as required for + // WLC/LCIC work submission + NvU64 workSubmissionOffsetGpuVa; } UvmGpuChannelInfo; typedef enum @@ -292,6 +303,17 @@ UVM_BUFFER_LOCATION_VID = 2, } UVM_BUFFER_LOCATION; +typedef struct UvmGpuTsgAllocParams_tag +{ + // Interpreted as UVM_GPU_CHANNEL_ENGINE_TYPE + NvU32 engineType; + + // Index of the engine the TSG is bound to. + // Ignored if engineType is anything other than + // UVM_GPU_CHANNEL_ENGINE_TYPE_CE. + NvU32 engineIndex; +} UvmGpuTsgAllocParams; + typedef struct UvmGpuChannelAllocParams_tag { NvU32 numGpFifoEntries; @@ -299,13 +321,6 @@ // The next two fields store UVM_BUFFER_LOCATION values NvU32 gpFifoLoc; NvU32 gpPutLoc; - - // Index of the engine the channel will be bound to - // ignored if engineType is anything other than UVM_GPU_CHANNEL_ENGINE_TYPE_CE - NvU32 engineIndex; - - // interpreted as UVM_GPU_CHANNEL_ENGINE_TYPE - NvU32 engineType; } UvmGpuChannelAllocParams; typedef struct UvmGpuPagingChannelAllocParams_tag @@ -376,40 +391,16 @@ typedef struct UvmGpuCaps_tag { - NvU32 sysmemLink; // UVM_LINK_TYPE - NvU32 sysmemLinkRateMBps; // See UvmGpuP2PCapsParams::totalLinkLineRateMBps + // If numaEnabled is NV_TRUE, then the system address of allocated GPU + // memory can be converted to struct pages. See + // UvmGpuInfo::systemMemoryWindowStart. NvBool numaEnabled; NvU32 numaNodeId; - - // On ATS systems, GPUs connected to different CPU sockets can have peer - // traffic. They are called indirect peers. However, indirect peers are - // mapped using sysmem aperture. In order to disambiguate the location of a - // specific memory address, each GPU maps its memory to a different window - // in the System Physical Address (SPA) space. The following fields contain - // the base + size of such window for the GPU. systemMemoryWindowSize - // different than 0 indicates that the window is valid. - // - // - If the window is valid, then we can map GPU memory to the CPU as - // cache-coherent by adding the GPU address to the window start. - // - If numaEnabled is NV_TRUE, then we can also convert the system - // addresses of allocated GPU memory to struct pages. - // - // TODO: Bug 1986868: fix window start computation for SIMICS - NvU64 systemMemoryWindowStart; - NvU64 systemMemoryWindowSize; - - // This tells if the GPU is connected to NVSwitch. On systems with NVSwitch - // all GPUs are connected to it. If connectedToSwitch is NV_TRUE, - // nvswitchMemoryWindowStart tells the base address for the GPU in the - // NVSwitch address space. It is used when creating PTEs of memory mappings - // to NVSwitch peers. - NvBool connectedToSwitch; - NvU64 nvswitchMemoryWindowStart; } UvmGpuCaps; typedef struct UvmGpuAddressSpaceInfo_tag { - NvU32 bigPageSize; + NvU64 bigPageSize; NvBool atsEnabled; @@ -430,12 +421,14 @@ typedef struct UvmGpuAllocInfo_tag { NvU64 gpuPhysOffset; // Returns gpuPhysOffset if contiguous requested - NvU32 pageSize; // default is RM big page size - 64K or 128 K" else use 4K or 2M + NvU64 pageSize; // default is RM big page size - 64K or 128 K" else use 4K or 2M NvU64 alignment; // Virtual alignment NvBool bContiguousPhysAlloc; // Flag to request contiguous physical allocation NvBool bMemGrowsDown; // Causes RM to reserve physical heap from top of FB NvBool bPersistentVidmem; // Causes RM to allocate persistent video memory NvHandle hPhysHandle; // Handle for phys allocation either provided or retrieved + NvBool bUnprotected; // Allocation to be made in unprotected memory whenever + // SEV or GPU CC modes are enabled. Ignored otherwise } UvmGpuAllocInfo; typedef enum @@ -516,6 +509,13 @@ // In: Size of the buffer to store PTEs (in bytes). NvU64 pteBufferSize; + // In: Page size for mapping + // If this field is passed as 0, the page size + // of the allocation is used for mapping. + // nvUvmInterfaceGetExternalAllocPtes must pass + // this field as zero. + NvU64 mappingPageSize; + // In: Pointer to a buffer to store PTEs. // Out: The interface will fill the buffer with PTEs NvU64 *pteBuffer; @@ -566,8 +566,11 @@ // Out: ATS (Address Translation Services) is supported NvBool atsSupported; - // Out: AMD SEV (Secure Encrypted Virtualization) is enabled - NvBool sevEnabled; + // Out: True if HW trusted execution, such as AMD's SEV-SNP or Intel's TDX, + // is enabled in the VM, indicating that Confidential Computing must be + // also enabled in the GPU(s); these two security features are either both + // enabled, or both disabled. + NvBool confComputingEnabled; } UvmPlatformInfo; typedef struct UvmGpuClientInfo_tag @@ -577,6 +580,20 @@ NvHandle hSmcPartRef; } UvmGpuClientInfo; +typedef enum +{ + UVM_GPU_CONF_COMPUTE_MODE_NONE, + UVM_GPU_CONF_COMPUTE_MODE_APM, + UVM_GPU_CONF_COMPUTE_MODE_HCC, + UVM_GPU_CONF_COMPUTE_MODE_COUNT +} UvmGpuConfComputeMode; + +typedef struct UvmGpuConfComputeCaps_tag +{ + // Out: GPU's confidential compute mode + UvmGpuConfComputeMode mode; +} UvmGpuConfComputeCaps; + #define UVM_GPU_NAME_LENGTH 0x40 typedef struct UvmGpuInfo_tag @@ -641,6 +658,31 @@ UvmGpuClientInfo smcUserClientInfo; + // Confidential Compute capabilities of this GPU + UvmGpuConfComputeCaps gpuConfComputeCaps; + + // UVM_LINK_TYPE + NvU32 sysmemLink; + + // See UvmGpuP2PCapsParams::totalLinkLineRateMBps + NvU32 sysmemLinkRateMBps; + + // On coherent systems each GPU maps its memory to a window in the System + // Physical Address (SPA) space. The following fields describe that window. + // + // systemMemoryWindowSize > 0 indicates that the window is valid. meaning + // that GPU memory can be mapped by the CPU as cache-coherent by adding the + // GPU address to the window start. + NvU64 systemMemoryWindowStart; + NvU64 systemMemoryWindowSize; + + // This tells if the GPU is connected to NVSwitch. On systems with NVSwitch + // all GPUs are connected to it. If connectedToSwitch is NV_TRUE, + // nvswitchMemoryWindowStart tells the base address for the GPU in the + // NVSwitch address space. It is used when creating PTEs of memory mappings + // to NVSwitch peers. + NvBool connectedToSwitch; + NvU64 nvswitchMemoryWindowStart; } UvmGpuInfo; typedef struct UvmGpuFbInfo_tag @@ -683,6 +725,9 @@ volatile NvU64 numPages2m; // PMA-wide 2MB pages count across all regions volatile NvU64 numFreePages64k; // PMA-wide free 64KB page count across all regions volatile NvU64 numFreePages2m; // PMA-wide free 2MB pages count across all regions + volatile NvU64 numPages2mProtected; // PMA-wide 2MB pages count in protected memory + volatile NvU64 numFreePages64kProtected; // PMA-wide free 64KB page count in protected memory + volatile NvU64 numFreePages2mProtected; // PMA-wide free 2MB pages count in protected memory } UvmPmaStatistics; /******************************************************************************* @@ -761,24 +806,92 @@ uvmEventIsrTopHalf_t isrTopHalf; }; +#define UVM_CSL_SIGN_AUTH_TAG_SIZE_BYTES 32 +#define UVM_CSL_CRYPT_AUTH_TAG_SIZE_BYTES 16 + +typedef union UvmFaultMetadataPacket_tag +{ + struct { + NvU8 authTag[UVM_CSL_CRYPT_AUTH_TAG_SIZE_BYTES]; + NvBool valid; + }; + // padding to 32Bytes + NvU8 _padding[32]; +} UvmFaultMetadataPacket; + +// This struct shall not be accessed nor modified directly by UVM as it is +// entirely managed by the RM layer +typedef struct UvmCslContext_tag +{ + struct ccslContext_t *ctx; + void *nvidia_stack; +} UvmCslContext; + typedef struct UvmGpuFaultInfo_tag { struct { - // Register mappings obtained from RM + // Fault buffer GET register mapping. + // + // When Confidential Computing is enabled, GET refers to the shadow + // buffer (see bufferAddress below), and not to the actual HW buffer. + // In this setup, writes of GET (by UVM) do not result on re-evaluation + // of any interrupt condition. volatile NvU32* pFaultBufferGet; + + // Fault buffer PUT register mapping. + // + // When Confidential Computing is enabled, PUT refers to the shadow + // buffer (see bufferAddress below), and not to the actual HW buffer. + // In this setup, writes of PUT (by GSP-RM) do not result on + // re-evaluation of any interrupt condition. volatile NvU32* pFaultBufferPut; - // Note: this variable is deprecated since buffer overflow is not a separate - // register from future chips. + + // Note: this variable is deprecated since buffer overflow is not a + // separate register from future chips. volatile NvU32* pFaultBufferInfo; + + // Register mapping used to clear a replayable fault interrupt in + // Turing+ GPUs. volatile NvU32* pPmcIntr; + + // Register mapping used to enable replayable fault interrupts. volatile NvU32* pPmcIntrEnSet; + + // Register mapping used to disable replayable fault interrupts. volatile NvU32* pPmcIntrEnClear; + + // Register used to enable, or disable, faults on prefetches. volatile NvU32* pPrefetchCtrl; + + // Replayable fault interrupt mask identifier. NvU32 replayableFaultMask; - // fault buffer cpu mapping and size - void* bufferAddress; + + // Fault buffer CPU mapping + void* bufferAddress; + // + // When Confidential Computing is disabled, the mapping points to the + // actual HW fault buffer. + // + // When Confidential Computing is enabled, the mapping points to a + // copy of the HW fault buffer. This "shadow buffer" is maintained + // by GSP-RM. + + // Size, in bytes, of the fault buffer pointed by bufferAddress. NvU32 bufferSize; + // Mapping pointing to the start of the fault buffer metadata containing + // a 16Byte authentication tag and a valid byte. Always NULL when + // Confidential Computing is disabled. + UvmFaultMetadataPacket *bufferMetadata; + + // CSL context used for performing decryption of replayable faults when + // Confidential Computing is enabled. + UvmCslContext cslCtx; + + // Indicates whether UVM owns the replayable fault buffer. + // The value of this field is always NV_TRUE When Confidential Computing + // is disabled. + NvBool bUvmOwnsHwFaultBuffer; } replayable; struct { @@ -797,8 +910,20 @@ // Preallocated stack for functions called from the UVM isr bottom half void *isr_bh_sp; + + // Used only when Hopper Confidential Compute is enabled + // Register mappings obtained from RM + volatile NvU32* pFaultBufferPut; + + // Used only when Hopper Confidential Compute is enabled + // Cached get index of the non-replayable shadow buffer + NvU32 shadowBufferGet; + + // See replayable.bufferMetadata + UvmFaultMetadataPacket *shadowBufferMetadata; } nonReplayable; NvHandle faultBufferHandle; + struct Device *pDevice; } UvmGpuFaultInfo; struct Device; @@ -834,12 +959,6 @@ void* bufferAddress; NvU32 bufferSize; NvHandle accessCntrBufferHandle; - - // The Notification address in the access counter notification msg does not - // contain the correct upper bits 63-47 for GPA-based notifications. RM - // provides us with the correct offset to be added. - // See Bug 1803015 - NvU64 baseDmaSysmemAddr; } UvmGpuAccessCntrInfo; typedef enum @@ -882,6 +1001,7 @@ } UVM_PMA_GPU_MEMORY_TYPE; typedef UvmGpuChannelInfo gpuChannelInfo; +typedef UvmGpuTsgAllocParams gpuTsgAllocParams; typedef UvmGpuChannelAllocParams gpuChannelAllocParams; typedef UvmGpuCaps gpuCaps; typedef UvmGpuCopyEngineCaps gpuCeCaps; @@ -906,4 +1026,16 @@ typedef UvmGpuPagingChannelAllocParams gpuPagingChannelAllocParams; typedef UvmPmaAllocationOptions gpuPmaAllocationOptions; +typedef struct UvmCslIv +{ + NvU8 iv[12]; + NvU8 fresh; +} UvmCslIv; + +typedef enum UvmCslOperation +{ + UVM_CSL_OPERATION_ENCRYPT, + UVM_CSL_OPERATION_DECRYPT +} UvmCslOperation; + #endif // _NV_UVM_TYPES_H_ diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/interface/nvrm_registry.h nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/interface/nvrm_registry.h --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/interface/nvrm_registry.h 2023-10-25 20:20:47.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/interface/nvrm_registry.h 2024-03-05 22:13:09.000000000 +0000 @@ -21,6 +21,11 @@ * DEALINGS IN THE SOFTWARE. */ +// +// This file holds NVIDIA Resource Manager registry key definitions that are +// shared between Windows and Unix +// + #ifndef NVRM_REGISTRY_H #define NVRM_REGISTRY_H @@ -442,12 +447,6 @@ #define NV_REG_STR_RM_INST_LOC_4_FECS_EVENT_BUF_NCOH NV_REG_STR_RM_INST_LOC_NCOH #define NV_REG_STR_RM_INST_LOC_4_FECS_EVENT_BUF_VID NV_REG_STR_RM_INST_LOC_VID -#define NV_REG_STR_RM_DISABLE_GSP_OFFLOAD "RmDisableGspOffload" -#define NV_REG_STR_RM_DISABLE_GSP_OFFLOAD_FALSE (0x00000000) -#define NV_REG_STR_RM_DISABLE_GSP_OFFLOAD_TRUE (0x00000001) -// Type DWORD (Boolean) -// Override any other settings and disable GSP-RM offload. - #define NV_REG_STR_RM_GSP_STATUS_QUEUE_SIZE "RmGspStatusQueueSize" // TYPE DWORD // Set the GSP status queue size in KB (for GSP to CPU RPC status and event communication) @@ -728,6 +727,17 @@ // // Type DWORD +// Used to control RM API lock aging for low priority acquires. +// If 0, low priority acquires (e.g. from cleanup when a process dies) +// are disabled and treated like regular ones. +// Otherwise, they will yield the lock this many times to the higher priority +// threads before proceeding. +// Off by default; 3 would be a good starting value if the feature is desired. +// +#define NV_REG_STR_RM_LOCKING_LOW_PRIORITY_AGING "RMLockingLowPriorityAging" + +// +// Type DWORD // This regkey restricts profiling capabilities (creation of profiling objects // and access to profiling-related registers) to admin only. // 0 - (default - disabled) @@ -816,13 +826,6 @@ // // Type DWORD -// Controls enable of Address Tree memory tracking instead of regmap -// for the PMA memory manager. -// -#define NV_REG_STR_RM_ENABLE_ADDRTREE "RMEnableAddrtree" -#define NV_REG_STR_RM_ENABLE_ADDRTREE_YES (0x00000001) -#define NV_REG_STR_RM_ENABLE_ADDRTREE_NO (0x00000000) - #define NV_REG_STR_RM_SCRUB_BLOCK_SHIFT "RMScrubBlockShift" // Type DWORD // Encoding Numeric Value @@ -907,7 +910,7 @@ // will fail in such a case. // // TYPE_DEFAULT let RM to choose a P2P type. The priority is: -// C2C > NVLINK > mailbox P2P > BAR1P2P +// C2C > NVLINK > mailbox P2P > BAR1P2P // // TYPE_C2C to use C2C P2P if it supports // TYPE_NVLINK to use NVLINK P2P, including INDIRECT_NVLINK_P2P if it supports @@ -986,7 +989,7 @@ // RM aperture size. This can result in undefined beahvior in environments that // rely on a virtual bar2 aperture shared between RM and VBIOS for VESA support. -#if defined(DEVELOP) || defined(DEBUG) || defined(NV_MODS) +#if defined(DEVELOP) || defined(DEBUG) || (defined(RMCFG_FEATURE_MODS_FEATURES) && RMCFG_FEATURE_MODS_FEATURES) // // TYPE DWORD // This setting will override the BAR1 Big page size @@ -995,7 +998,7 @@ #define NV_REG_STR_RM_SET_BAR1_ADDRESS_SPACE_BIG_PAGE_SIZE "RMSetBAR1AddressSpaceBigPageSize" #define NV_REG_STR_RM_SET_BAR1_ADDRESS_SPACE_BIG_PAGE_SIZE_64k (64 * 1024) #define NV_REG_STR_RM_SET_BAR1_ADDRESS_SPACE_BIG_PAGE_SIZE_128k (128 * 1024) -#endif //DEVELOP || DEBUG || NV_MODS +#endif //DEVELOP || DEBUG || MODS_FEATURES // This regkey is to disable coherent path CPU->Nvlink/C2C->FB and force BAR path. #define NV_REG_STR_RM_FORCE_BAR_PATH "RMForceBarPath" @@ -1716,15 +1719,46 @@ // period for which swap lock window will remain HIGH for QSYNC III. // -#define NV_REG_STR_RM_MULTICAST_FLA "RMEnableMulticastFla" -#define NV_REG_STR_RM_MULTICAST_FLA_DISABLED 0x00000000 -#define NV_REG_STR_RM_MULTICAST_FLA_ENABLED 0x00000001 +#define NV_REG_STR_RM_NVLINK_BW "RmNvlinkBandwidth" +// Type String +// The option is in the string format. // -// Type: Dword -// Encoding: -// 1 - Multicast FLA Enabled on supported GPU -// 0 - Multicast FLA Disabled on specific GPU +// Possible string values: +// OFF: 0% bandwidth +// MIN: 15%-25% bandwidth depending on the system's NVLink topology +// HALF: 50% bandwidth +// 3QUARTER: 75% bandwidth +// FULL: 100% bandwidth (default) // +// This option is only for Hopper+ GPU with NVLINK version 4.0. + +#define NV_REG_STR_RM_CLIENT_HANDLE_LOOKUP "RmClientHandleLookup" +// Type DWORD (Boolean) +// 1 - Store active RM clients in a multimap to speed up lookups (currently only in thirdpartyp2p) +// 0 - (Default) Linear list search for clients + + +// +// Type: DWORD (Boolean) +// +// 1 - Only invalidate and free CPU mappings immediatelly, then collect GPU resources +// from individual clients under separate lock acquire/release sequences. +// 0 - (Default) Immediately free all clients resources when freeing a client list +#define NV_REG_STR_RM_CLIENT_LIST_DEFERRED_FREE "RMClientListDeferredFree" + +// +// Type: DWORD +// +// Number of clients to free in a single chunk before yielding and scheduling +// a work item to handle the rest. +// +// Only valid if NV_REG_STR_RM_CLIENT_LIST_DEFERRED_FREE is set. +// +// Value of 0 (default) means there is no limit and all clients will be freed +// at once before the process terminates. +// +#define NV_REG_STR_RM_CLIENT_LIST_DEFERRED_FREE_LIMIT "RMClientListDeferredFreeLimit" + // // TYPE Dword // Determines whether or not to emulate VF MMU TLB Invalidation register range @@ -1736,9 +1770,192 @@ #define NV_REG_STR_BUG_3007008_EMULATE_VF_MMU_TLB_INVALIDATE_DISABLE 0x00000000 #define NV_REG_STR_BUG_3007008_EMULATE_VF_MMU_TLB_INVALIDATE_DEFAULT NV_REG_STR_BUG_3007008_EMULATE_VF_MMU_TLB_INVALIDATE_ENABLE -#define NV_REG_STR_RM_CLIENT_HANDLE_LOOKUP "RmClientHandleLookup" +#define NV_REG_STR_RM_POWER_FEATURES "RMPowerFeature" + +// Type DWORD +// This Regkey controls inforom black box data recording. This can be used to +// restrict access to BBX. +// 0 - Enable BBX. (Default) +// COMPLETELY - Enable/Disable BBX access (read/write). +// WRITE_BY_RM - Enable/Disable writes by RM itself. +// WRITE_BY_CLIENT - Enable/Disable writes by clients to RM. +// PERIODIC FLUSH - Enable/Disable periodic flush to inforom (Also enables/disables Power data collection) +// +#define NV_REG_STR_RM_INFOROM_DISABLE_BBX "RmDisableInforomBBX" +#define NV_REG_STR_RM_INFOROM_DISABLE_BBX_NO (0x00000000) +#define NV_REG_STR_RM_INFOROM_DISABLE_BBX_YES (0x00000001) +#define NV_REG_STR_RM_INFOROM_DISABLE_BBX_COMPLETELY 0:0 +#define NV_REG_STR_RM_INFOROM_DISABLE_BBX_COMPLETELY_NO (0x00000000) +#define NV_REG_STR_RM_INFOROM_DISABLE_BBX_COMPLETELY_YES (0x00000001) +#define NV_REG_STR_RM_INFOROM_DISABLE_BBX_WRITE_BY_RM 1:1 +#define NV_REG_STR_RM_INFOROM_DISABLE_BBX_WRITE_BY_RM_NO (0x00000000) +#define NV_REG_STR_RM_INFOROM_DISABLE_BBX_WRITE_BY_RM_YES (0x00000001) +#define NV_REG_STR_RM_INFOROM_DISABLE_BBX_WRITE_BY_CLIENT 2:2 +#define NV_REG_STR_RM_INFOROM_DISABLE_BBX_WRITE_BY_CLIENT_NO (0x00000000) +#define NV_REG_STR_RM_INFOROM_DISABLE_BBX_WRITE_BY_CLIENT_YES (0x00000001) +#define NV_REG_STR_RM_INFOROM_DISABLE_BBX_PERIODIC_FLUSH 3:3 +#define NV_REG_STR_RM_INFOROM_DISABLE_BBX_PERIODIC_FLUSH_YES (0x00000000) +#define NV_REG_STR_RM_INFOROM_DISABLE_BBX_PERIODIC_FLUSH_NO (0x00000001) + +// // Type DWORD (Boolean) -// 1 - Store active RM clients in a multimap to speed up lookups (currently only in thirdpartyp2p) -// 0 - (Default) Linear list search for clients +// RmNvlinkEnablePrivErrorRc +// +// 0 - (default) does not do RC recovery when PRIV_ERROR +// 1 - enable FLA PRIV_ERROR RC recovery +// +#define NV_REG_STR_RM_NVLINK_ENABLE_PRIV_ERROR_RC "RmNvlinkEnablePrivErrorRc" +#define NV_REG_STR_RM_NVLINK_ENABLE_PRIV_ERROR_RC_NO 0 +#define NV_REG_STR_RM_NVLINK_ENABLE_PRIV_ERROR_RC_YES 1 + +// +// Add the conditions to exclude these macros from Orin build, as CONFIDENTIAL_COMPUTE +// is a guardword. The #if could be removed when nvRmReg.h file is trimmed from Orin build. +// +// Enable Disable Confidential Compute and control its various modes of operation +// 0 - Feature Disable +// 1 - Feature Enable +// +#define NV_REG_STR_RM_CONFIDENTIAL_COMPUTE "RmConfidentialCompute" +#define NV_REG_STR_RM_CONFIDENTIAL_COMPUTE_ENABLED 0:0 +#define NV_REG_STR_RM_CONFIDENTIAL_COMPUTE_ENABLED_NO 0x00000000 +#define NV_REG_STR_RM_CONFIDENTIAL_COMPUTE_ENABLED_YES 0x00000001 +#define NV_REG_STR_RM_CONFIDENTIAL_COMPUTE_DEV_MODE_ENABLED 1:1 +#define NV_REG_STR_RM_CONFIDENTIAL_COMPUTE_DEV_MODE_ENABLED_NO 0x00000000 +#define NV_REG_STR_RM_CONFIDENTIAL_COMPUTE_DEV_MODE_ENABLED_YES 0x00000001 +#define NV_REG_STR_RM_CONFIDENTIAL_COMPUTE_GPUS_READY_CHECK 2:2 +#define NV_REG_STR_RM_CONFIDENTIAL_COMPUTE_GPUS_READY_CHECK_DISABLED 0x00000000 +#define NV_REG_STR_RM_CONFIDENTIAL_COMPUTE_GPUS_READY_CHECK_ENABLED 0x00000001 + +#define NV_REG_STR_RM_CONF_COMPUTE_EARLY_INIT "RmConfComputeEarlyInit" +#define NV_REG_STR_RM_CONF_COMPUTE_EARLY_INIT_DISABLED 0x00000000 +#define NV_REG_STR_RM_CONF_COMPUTE_EARLY_INIT_ENABLED 0x00000001 + +// +// Enable/disable SPDM feature in Confidential Compute. SPDM-capable profiles +// may not be loaded by default. This regkey allows us to override the default +// behavior and force SPDM to enabled/disabled. +// +// 0 - Feature disable +// 1 - Feature enable +// +#define NV_REG_STR_RM_CONF_COMPUTE_SPDM_POLICY "RmConfComputeSpdmPolicy" +#define NV_REG_STR_RM_CONF_COMPUTE_SPDM_POLICY_ENABLED 0:0 +#define NV_REG_STR_RM_CONF_COMPUTE_SPDM_POLICY_ENABLED_NO 0x00000000 +#define NV_REG_STR_RM_CONF_COMPUTE_SPDM_POLICY_ENABLED_YES 0x00000001 + +// TYPE Dword +// Encoding boolean +// Regkey based solution to serialize VBlank Aggressive Handling in Top Half using spinlock +// 2 - Enable serialization of aggressive vblank callbacks when HMD is active +// +// +// 1 - Enable serialization of aggressive vblank callbacks in all scenarios +// (even when a HMD is not active) +// +// 0 - (default) Disable WAR +// This regkey settings are enabled when Aggressive Vblanks are enabled, +// if RmDisableAggressiveVblank is set to disable then these regkeys do not have any affect +#define NV_REG_STR_RM_BUG_2089053_WAR "RmBug2089053War" +#define NV_REG_STR_RM_BUG_2089053_WAR_ENABLE_ON_HMD_ACTIVE_ONLY 0x00000002 +#define NV_REG_STR_RM_BUG_2089053_WAR_ENABLE_ALWAYS 0x00000001 +#define NV_REG_STR_RM_BUG_2089053_WAR_DISABLE 0x00000000 +#define NV_REG_STR_RM_BUG_2089053_WAR_DEFAULT (NV_REG_STR_RM_BUG_2089053_WAR_ENABLE_ALWAYS) + +// +// Controls whether GSP-RM profiling is enabled. +// 0 (default): disabled +// 1: enabled +// +#define NV_REG_STR_RM_GSPRM_PROFILING "RmGspRmProfiling" +#define NV_REG_STR_RM_GSPRM_PROFILING_DISABLE 0 +#define NV_REG_STR_RM_GSPRM_PROFILING_ENABLE 1 + +// +// Enable Local EGM HW verification using RM/SW stack. +// Must be specified with a peerID corresponding to local EGM +// +#define NV_REG_STR_RM_ENABLE_LOCAL_EGM_PEER_ID "RMEnableLocalEgmPeerId" + +// +// Overrides the size of the GSP-RM firmware heap in GPU memory. +// The GSP-RM firmware heap is reserved for system use and is not available to +// applications. This regkey can be used to optimize the amount of memory +// reserved for system use for targeted use cases. The default value for this +// regkey is determined to support certain worst case resource allocation +// patterns, but many use cases do not exhibit such resource allocation patterns +// and could benefit from the lesser reserved GPU memory. Other use cases may +// exhibit an even more pathological/stressful resource allocation pattern, +// which can be enabled (up to a limit) with this regkey. +// +// However, NVIDIA does not support setting this registry key, and will require +// that any bugs observed with it set be reproducible with the default setting +// as well. +// +// The value of this regkey is specified in megabytes. A value of 0 indicates to +// use the default value. Values less than the minimum or greater than the +// maximum will be clamped to the nearest optimum. The default values are +// are dynamically computed for each GPU prior to booting GSP-RM. +// +#define NV_REG_STR_GSP_FIRMWARE_HEAP_SIZE_MB "RmGspFirmwareHeapSizeMB" +#define NV_REG_STR_GSP_FIRMWARE_HEAP_SIZE_MB_DEFAULT 0 + +// +// Type DWORD +// This regkey can be used to enable GSP owned fault buffers +// +#define NV_REG_STR_RM_GSP_OWNED_FAULT_BUFFERS_ENABLE "RmGspOwnedFaultBuffersEnable" +#define NV_REG_STR_RM_GSP_OWNED_FAULT_BUFFERS_ENABLE_NO 0x00000000 +#define NV_REG_STR_RM_GSP_OWNED_FAULT_BUFFERS_ENABLE_YES 0x00000001 + +// +// WAR for BlueField3: Bug 4040336 +// BF3's PCI MMIO bus address 0x800000000000 is too high for Ampere to address. +// Due to this, BF3's bus address is now moved to < 4GB. So, the CPU PA is no longer +// the same as the bus address and this regkey adjusts the CPU PA passed in to the +// correct bus address. +// +#define NV_REG_STR_RM_DMA_ADJUST_PEER_MMIO_BF3 "RmDmaAdjustPeerMmioBF3" +#define NV_REG_STR_RM_DMA_ADJUST_PEER_MMIO_BF3_DISABLE 0 +#define NV_REG_STR_RM_DMA_ADJUST_PEER_MMIO_BF3_ENABLE 1 + +// +// Type DWORD +// This regkey force-disables write-combine iomap allocations, used for chipsets where +// write-combine is broken. +// +#define NV_REG_STR_RM_FORCE_DISABLE_IOMAP_WC "RmForceDisableIomapWC" +#define NV_REG_STR_RM_FORCE_DISABLE_IOMAP_WC_YES 0x00000001 +#define NV_REG_STR_RM_FORCE_DISABLE_IOMAP_WC_NO 0x00000000 +#define NV_REG_STR_RM_FORCE_DISABLE_IOMAP_WC_DEFAULT NV_REG_STR_RM_FORCE_DISABLE_IOMAP_WC_NO + +// +// TYPE DWORD +// This regkey will increase the margin after the end of WPR2 when booting GSP-RM. +// +// This margin can be used to help GSP firmware boot in the presence of ECC +// errors which might affect the default GSP firmware image location in the GPU +// framebuffer. If GPU firmware is able to successfully boot with this registry +// key enabled, it should scan the margin area to attempt to handle ECC errors in +// the region, so that the region can be safely used in a subsequent boot. +// +// NV_REG_RM_GSP_WPR_END_MARGIN_MB +// Possible values: +// 0 - (Default) use the default calculated GSP WPR size +// 1+ - size of the end margin in megabytes +// +// NV_REG_RM_GSP_WPR_END_MARGIN_APPLY +// Possible values: +// _ON_RETRY (0) - (Default) only increase the margin to the requested size +// when retrying GSP firmware boot after a failed boot attempt +// _ALWAYS (1) - increase the margin to the requested size for all GSP +// firmware boot attempts, including the first +// +#define NV_REG_STR_RM_GSP_WPR_END_MARGIN "RmGspWprEndMargin" +#define NV_REG_RM_GSP_WPR_END_MARGIN_MB 30:0 +#define NV_REG_RM_GSP_WPR_END_MARGIN_APPLY 31:31 +#define NV_REG_RM_GSP_WPR_END_MARGIN_APPLY_ON_RETRY 0x00000000 +#define NV_REG_RM_GSP_WPR_END_MARGIN_APPLY_ALWAYS 0x00000001 #endif // NVRM_REGISTRY_H + diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/interface/rmapi/src/finn_rm_api.c nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/interface/rmapi/src/finn_rm_api.c --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/interface/rmapi/src/finn_rm_api.c 2023-10-25 20:20:47.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/interface/rmapi/src/finn_rm_api.c 1970-01-01 00:00:00.000000000 +0000 @@ -1,7496 +0,0 @@ -#include "finn_rm_api.h" -#include "ctrl/ctrl0000/ctrl0000nvd.h" -#include "ctrl/ctrl0080/ctrl0080dma.h" -#include "ctrl/ctrl0080/ctrl0080fb.h" -#include "ctrl/ctrl0080/ctrl0080fifo.h" -#include "ctrl/ctrl0080/ctrl0080gpu.h" -#include "ctrl/ctrl0080/ctrl0080gr.h" -#include "ctrl/ctrl0080/ctrl0080host.h" -#include "ctrl/ctrl0080/ctrl0080msenc.h" -#include "ctrl/ctrl2080/ctrl2080ce.h" -#include "ctrl/ctrl2080/ctrl2080gpu.h" -#include "ctrl/ctrl2080/ctrl2080i2c.h" -#include "ctrl/ctrl2080/ctrl2080nvd.h" -#include "ctrl/ctrl2080/ctrl2080perf.h" -#include "ctrl/ctrl2080/ctrl2080rc.h" -#include "ctrl/ctrl2080/ctrl2080ucodefuzzer.h" -#include "ctrl/ctrl208f/ctrl208fgpu.h" -#include "ctrl/ctrl402c.h" -#include "ctrl/ctrl83de/ctrl83dedebug.h" -#include "ctrl/ctrlb06f.h" - -#if defined(NVRM) /* Kernel Mode */ -#include -#include -#include "nvport/nvport.h" -#elif defined(NV_LIBOS) /* LIBOS */ -#include -#include "nvport/nvport.h" -#else /* User Mode */ -#include -#include -#include -#include -#endif - - -// -// This file was generated with FINN, an NVIDIA coding tool. -// - -/* - * Serialization helper macros. These make field copying code more readable. - * Size is provided explicitly for cross-platform compatibility. - */ - -// Allocate memory. -#if defined(FINN_MALLOC) /* Use override from Makefile */ -#elif defined(NVRM) /* Kernel Mode */ -#define FINN_MALLOC(size) portMemAllocNonPaged(size) - -#elif defined(NV_LIBOS) /* LIBOS */ -#define FINN_MALLOC(size) portMemAllocNonPaged(size) - -#else /* User Mode */ -#define FINN_MALLOC(size) malloc(size) -#endif - -// Free allocated memory. -#if defined(FINN_FREE) /* Use override from Makefile */ -#elif defined(NVRM) /* Kernel Mode */ -#define FINN_FREE(buf) portMemFree(buf) - -#elif defined(NV_LIBOS) /* LIBOS */ -#define FINN_FREE(buf) portMemFree(buf) - -#else /* User Mode */ -#define FINN_FREE(buf) free(buf) -#endif - -// Set memory region to all zeroes. -#if defined(FINN_MEMZERO) /* Use override from Makefile */ -#elif defined(NVRM) /* Kernel Mode */ -#define FINN_MEMZERO(buf, size) portMemSet(buf, 0, size) - -#elif defined(NV_LIBOS) /* LIBOS */ -#define FINN_MEMZERO(buf, size) portMemSet(buf, 0, size) - -#else /* User Mode */ -#define FINN_MEMZERO(buf, size) memset(buf, 0, size) -#endif - -// Copy nonoverlapping memory region. -#if defined(FINN_MEMCPY) /* Use override from Makefile */ -#elif defined(NVRM) /* Kernel Mode */ -#define FINN_MEMCPY(dst, src, size) portMemCopy(dst, size, src, size) - -#elif defined(NV_LIBOS) /* LIBOS */ -#define FINN_MEMCPY(dst, src, size) portMemCopy(dst, size, src, size) - -#else /* User Mode */ -#define FINN_MEMCPY(dst, src, size) memcpy(dst, src, size) -#endif - -// Report an error. -#if defined(FINN_ERROR) /* Use override from Makefile */ -#elif defined(NVRM) /* Kernel Mode */ -#define FINN_ERROR(err) /* No-op */ - -#elif defined(NV_LIBOS) /* LIBOS */ -#define FINN_ERROR(err) /* No-op */ - -#else /* User Mode */ -#define FINN_ERROR(err) /* No-op */ -#endif - - - -// -// The purpose of the bit pump is to ensure 64-bit aligned access to the -// buffer while enabling arbitrary bits to be read/written. -// -typedef struct finn_bit_pump_for_read finn_bit_pump_for_read; - -struct finn_bit_pump_for_read -{ - uint64_t accumulator; // Bits not yet read from the data buffer - uint64_t checksum; // Checksum of data - const uint64_t *buffer_position; // Next word within data buffer to be read - const uint64_t *end_of_data; // End of data within buffer - uint8_t remaining_bit_count; // Number of bits remaining in the accumulator -}; - - -// -// Initialize bit pump for reading from the buffer. -// -// WARNING: The buffer start is assumed to be 64-bit aligned for optimal performance. -// `sod` (start of data) and `eod` (end of data) must be multiples of 64 bits -// since this logic is optimized for a 64-bit word size. Caller must check both -// `sod` and `eod`. -// -// `eod` points to the 64-bit word after the data (like most C++ `std` iterators). -// -static inline void finn_open_buffer_for_read(finn_bit_pump_for_read *bp, const uint64_t *sod, const uint64_t *eod) -{ - bp->accumulator = 0U; - bp->checksum = 0U; - bp->buffer_position = sod; - bp->end_of_data = eod; - bp->remaining_bit_count = 0U; -} - - -// -// Read the next several bits. -// -// `bit_size` must be in range of 0 to 64 inclusive; no check is made. -// When `bit_size` is zero, an unsupported use-case, it works as expected by -// returning zero without advancing the pointer. -// -static uint64_t finn_read_buffer(finn_bit_pump_for_read *bp, uint8_t bit_size) -{ - // Value to be deserialized and returned - uint64_t value; - - // Boundary crossing - // Accumulator does not have enough to satisfy the request, - if (bit_size > bp->remaining_bit_count) - { - // Number of bits not yet satisfied - bit_size -= bp->remaining_bit_count; - - // Shift the bits we have into place. - value = bp->accumulator; - - // Return zeroes for unsatisfied bits (if any) at end of data. - if (bp->buffer_position >= bp->end_of_data) - bp->accumulator = 0U; - - // Read the next word from the buffer. - else - bp->accumulator = *(bp->buffer_position++); - - // Update the checksum. - bp->checksum = ((bp->checksum << 1) ^ (bp->checksum & 1U)) ^ bp->accumulator; - - // - // This is the special case where we are reading an entire 64-bit word - // without crossing a boundary (when the accumulator is empty). The - // accumulator remains empty on exit. - // - // The bitwise operations in the normal flow do not work in this case. - // Shifts are not well-defined in C when the right operand exceeds the - // size of the left operand. Also, the right operand of the bitwise-and - // would exceed the 64-bit capacity. However, the needed logic is simple. - // - // 64 is the largest legal value for `bit_size`, so `>=` is equivalent to `==`. - // - if (bit_size >= 64) - { - // The value is the entire word. - value = bp->accumulator; - - // Discard the consumed data from the accumulator. - bp->accumulator = 0U; - - // Under the assumption that `bit_size` is never larger than 64, - // `bit_size == 64` implies `bp->remaining_bit_count == 0` because - // of the above `bit_size -= bp->remaining_bit_count`. As such, there - // is no need to do `bp->remaining_bit_count = 64U - bit_size`. - - // Done - return value; - } - - // OR in the bits since this was a boundary crossing. - // Shift it over by the number of bits we get from the prior word. - value |= (bp->accumulator - & (((uint64_t) 1U << bit_size) - 1U)) - << bp->remaining_bit_count; - - // Logic below subtracts off the bits consumed in the accumulator. - bp->remaining_bit_count = 64U; - } - - else - { - // The accumulator has enough to satisfy the request. - value = bp->accumulator & (((uint64_t) 1U << bit_size) - 1U); - } - - // Discard the consumed bits from the accumulator. - bp->accumulator >>= bit_size; - - // Keep track of the remaining available bits in the accumulator. - bp->remaining_bit_count -= bit_size; - - // Done - return value; -} - - -// Close the read buffer. -// Postcondition: `bp->checksum` is updated to end-of-data. -static inline void finn_close_buffer_for_read(finn_bit_pump_for_read *bp) -{ - // No need to update the bit pump buffer position, - // so use a local for optimal performance. - const uint64_t *p = bp->buffer_position; - - // Apply any unread words to the checksum. - while (p < bp->end_of_data) - bp->checksum = ((bp->checksum << 1U) ^ (bp->checksum & 1U)) ^ (*(p++)); -} - - -typedef struct finn_bit_pump_for_write finn_bit_pump_for_write; - -struct finn_bit_pump_for_write -{ - uint64_t accumulator; // Bits not yet written to the data buffer - uint64_t checksum; // Checksum of data - uint64_t *buffer_position; // Next word within the data buffer to be written - const uint64_t *end_of_buffer; // End of buffer (which may be after end of data) - uint8_t empty_bit_count; // Number of available bits in the accumulator -}; - - -// -// Initialize bit pump for writing to the buffer. -// -// In the general case for writing to the bit pump: -// -// WARNING: The buffer start is assumed to be 64-bit aligned for optimal performance. -// `sod` (start of data) and `eob` (end of buffer) must be multiples of 64 bits -// since this logic is optimized for a 64-bit word size. Caller must check both -// `sod` and `eod`. -// -// `eob` points to the 64-bit word after the buffer, an illegal access. -// -// -// Special case to get the serialized size without writing to the buffer: -// Both `sod` and `eob` are null. -// When closed, `bp->buffer_position` contains the byte count. -// -static inline void finn_open_buffer_for_write(finn_bit_pump_for_write *bp, uint64_t *sod, const uint64_t *eob) -{ - bp->accumulator = 0U; - bp->buffer_position = sod; - bp->end_of_buffer = eob; - bp->checksum = 0U; - bp->empty_bit_count = 64U; -} - -// -// Write several bits to the buffer. -// -// `bit_size` must be in range of 1 to 64 inclusive; no check is made. -// `value` must not have more 1 bits than specified by `bit_size`. -// In other words, bits that are left of `bit_size` must be 0s; no check is made. -// -// Return value is nonzero if the end of buffer is reached, an error. -// -// `bp->end_of_buffer` is null to disable writing to the buffer. -// -static int finn_write_buffer(finn_bit_pump_for_write *bp, uint64_t value, uint8_t bit_size) -{ - // Boundary crossing: Accumulator does not have enough to satisfy the request, - if (bit_size >= bp->empty_bit_count) - { - // Number of bits not yet satisfied - bit_size -= bp->empty_bit_count; - - // OR as many bits as will fit into the accumulator. - bp->accumulator |= value << (64U - bp->empty_bit_count); - - // Discard these bits by setting them to 0s. - // CAUTION: `value` may be unchanged when `bp->empty_bit_count` is 64 - // depending on the processor/ISA. - value >>= bp->empty_bit_count; - - // Write the word to the buffer unless writes are disabled. - if (bp->end_of_buffer) - { - *bp->buffer_position = bp->accumulator; - } - - // Advance to the next word in the buffer. - bp->buffer_position++; - - // Update the checksum. - bp->checksum = ((bp->checksum << 1) ^ (bp->checksum & 1U)) ^ bp->accumulator; - - // Re-initialize the accumulator and the bits filled. - bp->accumulator = 0U; - bp->empty_bit_count = 64U; - } - - // OR the data into the accumulator. - // When `bit_size` and `bp->empty_bit_count` are both 64 above, `bit_size` - // is assigned zero, but `value` may be unchanged. Check `bit_size` here so - // that stale `value` is not ORed into the accumulator again. - if (bit_size) - { - bp->accumulator |= (value << (64U - bp->empty_bit_count)); - } - - // Advance the bit count - bp->empty_bit_count -= bit_size; - - // Return nonzero on buffer overrun. - return bp->end_of_buffer && bp->buffer_position >= bp->end_of_buffer && bit_size; -} - - -// -// Close the write buffer and compute the checksum. -// -// Do NOT call this function if `finn_write_buffer` returned nonzero; no check is made. -// -// In the general case for writing to the bit pump: -// -// Postcondition: `bp->buffer_position` points to the word after the end of the data, -// which can be used to calculate the data size in 64-bit words by subtracting from -// `bp->end_of_buffer`. Buffer data at and after this point is set to zeroes. -// -// Special case to get the serialized size without writing to the buffer: -// Postcondition: ``bp->buffer_position` contains the byte count. -// -// All cases: -// Postcondition: `bp->checksum` contains the checksum of words written to the buffer. -// -static inline void finn_close_buffer_for_write(finn_bit_pump_for_write *bp) -{ - uint64_t *p; - - // The accumulator is not empty. - if (bp->empty_bit_count < 64U) - { - // Update the buffer with the last word. - if (bp->end_of_buffer) - { - *bp->buffer_position = bp->accumulator; - } - - // Advance to the next word to get an accurate word count. - bp->buffer_position++; - - // Update the checksum. - bp->checksum = ((bp->checksum << 1U) ^ (bp->checksum & 1U)) ^ bp->accumulator; - } - - // Zero out the rest of the buffer. - for (p = bp->buffer_position; p < bp->end_of_buffer; ++p) - { - *p = 0u; - } -} - - -static NV_STATUS FinnRmApiSerializeInternal(NvU64 interface, NvU64 message, const char *src, char **dst, size_t dst_size, NvBool seri_up); -static NV_STATUS FinnRmApiSerializeInterface(NvU64 interface, NvU64 message, const char *src, finn_bit_pump_for_write *bp, NvBool seri_up); -static NV_STATUS FinnRmApiDeserializeInternal(const char **src, NvLength src_size, char *dst, NvLength dst_size, NvBool deser_up); -static NV_STATUS FinnRmApiDeserializeInterface(NvU64 interface, NvU64 message, finn_bit_pump_for_read *bp, char *dst, NvLength dst_size, NvBool deser_up); -static NV_STATUS FinnNv01RootNvdSerializeMessage(NvU64 message, const char *src, finn_bit_pump_for_write *bp, NvBool seri_up); -static NV_STATUS FinnNv01RootNvdDeserializeMessage(NvU64 message, finn_bit_pump_for_read *bp, FINN_NV01_ROOT_NVD *dst, NvLength dst_size, NvBool deser_up); -static NvU64 FinnNv01RootNvdGetUnserializedSize(NvU64 message); -static NV_STATUS FinnNv01Device0DmaSerializeMessage(NvU64 message, const char *src, finn_bit_pump_for_write *bp, NvBool seri_up); -static NV_STATUS FinnNv01Device0DmaDeserializeMessage(NvU64 message, finn_bit_pump_for_read *bp, FINN_NV01_DEVICE_0_DMA *dst, NvLength dst_size, NvBool deser_up); -static NvU64 FinnNv01Device0DmaGetUnserializedSize(NvU64 message); -static NV_STATUS FinnNv01Device0FbSerializeMessage(NvU64 message, const char *src, finn_bit_pump_for_write *bp, NvBool seri_up); -static NV_STATUS FinnNv01Device0FbDeserializeMessage(NvU64 message, finn_bit_pump_for_read *bp, FINN_NV01_DEVICE_0_FB *dst, NvLength dst_size, NvBool deser_up); -static NvU64 FinnNv01Device0FbGetUnserializedSize(NvU64 message); -static NV_STATUS FinnNv01Device0FifoSerializeMessage(NvU64 message, const char *src, finn_bit_pump_for_write *bp, NvBool seri_up); -static NV_STATUS FinnNv01Device0FifoDeserializeMessage(NvU64 message, finn_bit_pump_for_read *bp, FINN_NV01_DEVICE_0_FIFO *dst, NvLength dst_size, NvBool deser_up); -static NvU64 FinnNv01Device0FifoGetUnserializedSize(NvU64 message); -static NV_STATUS FinnNv01Device0GpuSerializeMessage(NvU64 message, const char *src, finn_bit_pump_for_write *bp, NvBool seri_up); -static NV_STATUS FinnNv01Device0GpuDeserializeMessage(NvU64 message, finn_bit_pump_for_read *bp, FINN_NV01_DEVICE_0_GPU *dst, NvLength dst_size, NvBool deser_up); -static NvU64 FinnNv01Device0GpuGetUnserializedSize(NvU64 message); -static NV_STATUS FinnNv01Device0GrSerializeMessage(NvU64 message, const char *src, finn_bit_pump_for_write *bp, NvBool seri_up); -static NV_STATUS FinnNv01Device0GrDeserializeMessage(NvU64 message, finn_bit_pump_for_read *bp, FINN_NV01_DEVICE_0_GR *dst, NvLength dst_size, NvBool deser_up); -static NvU64 FinnNv01Device0GrGetUnserializedSize(NvU64 message); -static NV_STATUS FinnNv01Device0HostSerializeMessage(NvU64 message, const char *src, finn_bit_pump_for_write *bp, NvBool seri_up); -static NV_STATUS FinnNv01Device0HostDeserializeMessage(NvU64 message, finn_bit_pump_for_read *bp, FINN_NV01_DEVICE_0_HOST *dst, NvLength dst_size, NvBool deser_up); -static NvU64 FinnNv01Device0HostGetUnserializedSize(NvU64 message); -static NV_STATUS FinnNv01Device0MsencSerializeMessage(NvU64 message, const char *src, finn_bit_pump_for_write *bp, NvBool seri_up); -static NV_STATUS FinnNv01Device0MsencDeserializeMessage(NvU64 message, finn_bit_pump_for_read *bp, FINN_NV01_DEVICE_0_MSENC *dst, NvLength dst_size, NvBool deser_up); -static NvU64 FinnNv01Device0MsencGetUnserializedSize(NvU64 message); -static NV_STATUS FinnNv20Subdevice0CeSerializeMessage(NvU64 message, const char *src, finn_bit_pump_for_write *bp, NvBool seri_up); -static NV_STATUS FinnNv20Subdevice0CeDeserializeMessage(NvU64 message, finn_bit_pump_for_read *bp, FINN_NV20_SUBDEVICE_0_CE *dst, NvLength dst_size, NvBool deser_up); -static NvU64 FinnNv20Subdevice0CeGetUnserializedSize(NvU64 message); -static NV_STATUS FinnNv20Subdevice0GpuSerializeMessage(NvU64 message, const char *src, finn_bit_pump_for_write *bp, NvBool seri_up); -static NV_STATUS FinnNv20Subdevice0GpuDeserializeMessage(NvU64 message, finn_bit_pump_for_read *bp, FINN_NV20_SUBDEVICE_0_GPU *dst, NvLength dst_size, NvBool deser_up); -static NvU64 FinnNv20Subdevice0GpuGetUnserializedSize(NvU64 message); -static NV_STATUS FinnNv20Subdevice0I2cSerializeMessage(NvU64 message, const char *src, finn_bit_pump_for_write *bp, NvBool seri_up); -static NV_STATUS FinnNv20Subdevice0I2cDeserializeMessage(NvU64 message, finn_bit_pump_for_read *bp, FINN_NV20_SUBDEVICE_0_I2C *dst, NvLength dst_size, NvBool deser_up); -static NvU64 FinnNv20Subdevice0I2cGetUnserializedSize(NvU64 message); -static NV_STATUS FinnNv20Subdevice0NvdSerializeMessage(NvU64 message, const char *src, finn_bit_pump_for_write *bp, NvBool seri_up); -static NV_STATUS FinnNv20Subdevice0NvdDeserializeMessage(NvU64 message, finn_bit_pump_for_read *bp, FINN_NV20_SUBDEVICE_0_NVD *dst, NvLength dst_size, NvBool deser_up); -static NvU64 FinnNv20Subdevice0NvdGetUnserializedSize(NvU64 message); -static NV_STATUS FinnNv20Subdevice0PerfSerializeMessage(NvU64 message, const char *src, finn_bit_pump_for_write *bp, NvBool seri_up); -static NV_STATUS FinnNv20Subdevice0PerfDeserializeMessage(NvU64 message, finn_bit_pump_for_read *bp, FINN_NV20_SUBDEVICE_0_PERF *dst, NvLength dst_size, NvBool deser_up); -static NvU64 FinnNv20Subdevice0PerfGetUnserializedSize(NvU64 message); -static NV_STATUS FinnNv20Subdevice0RcSerializeMessage(NvU64 message, const char *src, finn_bit_pump_for_write *bp, NvBool seri_up); -static NV_STATUS FinnNv20Subdevice0RcDeserializeMessage(NvU64 message, finn_bit_pump_for_read *bp, FINN_NV20_SUBDEVICE_0_RC *dst, NvLength dst_size, NvBool deser_up); -static NvU64 FinnNv20Subdevice0RcGetUnserializedSize(NvU64 message); - -static NV_STATUS FinnNv20SubdeviceDiagGpuSerializeMessage(NvU64 message, const char *src, finn_bit_pump_for_write *bp, NvBool seri_up); -static NV_STATUS FinnNv20SubdeviceDiagGpuDeserializeMessage(NvU64 message, finn_bit_pump_for_read *bp, FINN_NV20_SUBDEVICE_DIAG_GPU *dst, NvLength dst_size, NvBool deser_up); -static NvU64 FinnNv20SubdeviceDiagGpuGetUnserializedSize(NvU64 message); -static NV_STATUS FinnNv40I2cI2cSerializeMessage(NvU64 message, const char *src, finn_bit_pump_for_write *bp, NvBool seri_up); -static NV_STATUS FinnNv40I2cI2cDeserializeMessage(NvU64 message, finn_bit_pump_for_read *bp, FINN_NV40_I2C_I2C *dst, NvLength dst_size, NvBool deser_up); -static NvU64 FinnNv40I2cI2cGetUnserializedSize(NvU64 message); -static NV_STATUS FinnGt200DebuggerDebugSerializeMessage(NvU64 message, const char *src, finn_bit_pump_for_write *bp, NvBool seri_up); -static NV_STATUS FinnGt200DebuggerDebugDeserializeMessage(NvU64 message, finn_bit_pump_for_read *bp, FINN_GT200_DEBUGGER_DEBUG *dst, NvLength dst_size, NvBool deser_up); -static NvU64 FinnGt200DebuggerDebugGetUnserializedSize(NvU64 message); -static NV_STATUS FinnMaxwellChannelGpfifoAGpfifoSerializeMessage(NvU64 message, const char *src, finn_bit_pump_for_write *bp, NvBool seri_up); -static NV_STATUS FinnMaxwellChannelGpfifoAGpfifoDeserializeMessage(NvU64 message, finn_bit_pump_for_read *bp, FINN_MAXWELL_CHANNEL_GPFIFO_A_GPFIFO *dst, NvLength dst_size, NvBool deser_up); -static NvU64 FinnMaxwellChannelGpfifoAGpfifoGetUnserializedSize(NvU64 message); - -static NV_STATUS Nv0000CtrlNvdGetDumpParamsSerialize(const NV0000_CTRL_NVD_GET_DUMP_PARAMS *src, finn_bit_pump_for_write *bp, NvBool seri_up); -static NV_STATUS Nv0000CtrlNvdGetDumpParamsDeserialize(finn_bit_pump_for_read *bp, NV0000_CTRL_NVD_GET_DUMP_PARAMS *dst, NvLength dst_size, NvBool deser_up); -static NV_STATUS Nv0080CtrlDmaUpdatePde2PageTableParamsSerialize(const NV0080_CTRL_DMA_UPDATE_PDE_2_PAGE_TABLE_PARAMS *src, finn_bit_pump_for_write *bp, NvBool seri_up); -static NV_STATUS Nv0080CtrlDmaUpdatePde2PageTableParamsDeserialize(finn_bit_pump_for_read *bp, NV0080_CTRL_DMA_UPDATE_PDE_2_PAGE_TABLE_PARAMS *dst, NvLength dst_size, NvBool deser_up); -static NV_STATUS Nv0080CtrlDmaUpdatePde2ParamsSerialize(const NV0080_CTRL_DMA_UPDATE_PDE_2_PARAMS *src, finn_bit_pump_for_write *bp, NvBool seri_up); -static NV_STATUS Nv0080CtrlDmaUpdatePde2ParamsDeserialize(finn_bit_pump_for_read *bp, NV0080_CTRL_DMA_UPDATE_PDE_2_PARAMS *dst, NvLength dst_size, NvBool deser_up); -static NV_STATUS Nv0080CtrlFbGetCapsParamsSerialize(const NV0080_CTRL_FB_GET_CAPS_PARAMS *src, finn_bit_pump_for_write *bp, NvBool seri_up); -static NV_STATUS Nv0080CtrlFbGetCapsParamsDeserialize(finn_bit_pump_for_read *bp, NV0080_CTRL_FB_GET_CAPS_PARAMS *dst, NvLength dst_size, NvBool deser_up); -static NV_STATUS Nv0080CtrlFifoGetCapsParamsSerialize(const NV0080_CTRL_FIFO_GET_CAPS_PARAMS *src, finn_bit_pump_for_write *bp, NvBool seri_up); -static NV_STATUS Nv0080CtrlFifoGetCapsParamsDeserialize(finn_bit_pump_for_read *bp, NV0080_CTRL_FIFO_GET_CAPS_PARAMS *dst, NvLength dst_size, NvBool deser_up); -static NV_STATUS Nv0080CtrlFifoChannelSerialize(const NV0080_CTRL_FIFO_CHANNEL *src, finn_bit_pump_for_write *bp, NvBool seri_up); -static NV_STATUS Nv0080CtrlFifoChannelDeserialize(finn_bit_pump_for_read *bp, NV0080_CTRL_FIFO_CHANNEL *dst, NvLength dst_size, NvBool deser_up); -static NV_STATUS Nv0080CtrlFifoStartSelectedChannelsParamsSerialize(const NV0080_CTRL_FIFO_START_SELECTED_CHANNELS_PARAMS *src, finn_bit_pump_for_write *bp, NvBool seri_up); -static NV_STATUS Nv0080CtrlFifoStartSelectedChannelsParamsDeserialize(finn_bit_pump_for_read *bp, NV0080_CTRL_FIFO_START_SELECTED_CHANNELS_PARAMS *dst, NvLength dst_size, NvBool deser_up); -static NV_STATUS Nv0080CtrlFifoGetChannellistParamsSerialize(const NV0080_CTRL_FIFO_GET_CHANNELLIST_PARAMS *src, finn_bit_pump_for_write *bp, NvBool seri_up); -static NV_STATUS Nv0080CtrlFifoGetChannellistParamsDeserialize(finn_bit_pump_for_read *bp, NV0080_CTRL_FIFO_GET_CHANNELLIST_PARAMS *dst, NvLength dst_size, NvBool deser_up); -static NV_STATUS Nv0080CtrlGpuGetClasslistParamsSerialize(const NV0080_CTRL_GPU_GET_CLASSLIST_PARAMS *src, finn_bit_pump_for_write *bp, NvBool seri_up); -static NV_STATUS Nv0080CtrlGpuGetClasslistParamsDeserialize(finn_bit_pump_for_read *bp, NV0080_CTRL_GPU_GET_CLASSLIST_PARAMS *dst, NvLength dst_size, NvBool deser_up); -static NV_STATUS Nv0080CtrlGrGetCapsParamsSerialize(const NV0080_CTRL_GR_GET_CAPS_PARAMS *src, finn_bit_pump_for_write *bp, NvBool seri_up); -static NV_STATUS Nv0080CtrlGrGetCapsParamsDeserialize(finn_bit_pump_for_read *bp, NV0080_CTRL_GR_GET_CAPS_PARAMS *dst, NvLength dst_size, NvBool deser_up); -static NV_STATUS Nv0080CtrlHostGetCapsParamsSerialize(const NV0080_CTRL_HOST_GET_CAPS_PARAMS *src, finn_bit_pump_for_write *bp, NvBool seri_up); -static NV_STATUS Nv0080CtrlHostGetCapsParamsDeserialize(finn_bit_pump_for_read *bp, NV0080_CTRL_HOST_GET_CAPS_PARAMS *dst, NvLength dst_size, NvBool deser_up); -static NV_STATUS Nv0080CtrlMsencGetCapsParamsSerialize(const NV0080_CTRL_MSENC_GET_CAPS_PARAMS *src, finn_bit_pump_for_write *bp, NvBool seri_up); -static NV_STATUS Nv0080CtrlMsencGetCapsParamsDeserialize(finn_bit_pump_for_read *bp, NV0080_CTRL_MSENC_GET_CAPS_PARAMS *dst, NvLength dst_size, NvBool deser_up); -static NV_STATUS Nv2080CtrlCeGetCapsParamsSerialize(const NV2080_CTRL_CE_GET_CAPS_PARAMS *src, finn_bit_pump_for_write *bp, NvBool seri_up); -static NV_STATUS Nv2080CtrlCeGetCapsParamsDeserialize(finn_bit_pump_for_read *bp, NV2080_CTRL_CE_GET_CAPS_PARAMS *dst, NvLength dst_size, NvBool deser_up); -static NV_STATUS Nv2080CtrlGpuGetEnginesParamsSerialize(const NV2080_CTRL_GPU_GET_ENGINES_PARAMS *src, finn_bit_pump_for_write *bp, NvBool seri_up); -static NV_STATUS Nv2080CtrlGpuGetEnginesParamsDeserialize(finn_bit_pump_for_read *bp, NV2080_CTRL_GPU_GET_ENGINES_PARAMS *dst, NvLength dst_size, NvBool deser_up); -static NV_STATUS Nv2080CtrlGpuGetEngineClasslistParamsSerialize(const NV2080_CTRL_GPU_GET_ENGINE_CLASSLIST_PARAMS *src, finn_bit_pump_for_write *bp, NvBool seri_up); -static NV_STATUS Nv2080CtrlGpuGetEngineClasslistParamsDeserialize(finn_bit_pump_for_read *bp, NV2080_CTRL_GPU_GET_ENGINE_CLASSLIST_PARAMS *dst, NvLength dst_size, NvBool deser_up); -static NV_STATUS Nv2080CtrlGpumonSamplesSerialize(const NV2080_CTRL_GPUMON_SAMPLES *src, finn_bit_pump_for_write *bp, NvBool seri_up); -static NV_STATUS Nv2080CtrlGpumonSamplesDeserialize(finn_bit_pump_for_read *bp, NV2080_CTRL_GPUMON_SAMPLES *dst, NvLength dst_size, NvBool deser_up); -static NV_STATUS Nv2080CtrlI2cAccessParamsSerialize(const NV2080_CTRL_I2C_ACCESS_PARAMS *src, finn_bit_pump_for_write *bp, NvBool seri_up); -static NV_STATUS Nv2080CtrlI2cAccessParamsDeserialize(finn_bit_pump_for_read *bp, NV2080_CTRL_I2C_ACCESS_PARAMS *dst, NvLength dst_size, NvBool deser_up); -static NV_STATUS Nv2080CtrlNvdGetDumpParamsSerialize(const NV2080_CTRL_NVD_GET_DUMP_PARAMS *src, finn_bit_pump_for_write *bp, NvBool seri_up); -static NV_STATUS Nv2080CtrlNvdGetDumpParamsDeserialize(finn_bit_pump_for_read *bp, NV2080_CTRL_NVD_GET_DUMP_PARAMS *dst, NvLength dst_size, NvBool deser_up); -static NV_STATUS Nv2080CtrlRcReadVirtualMemParamsSerialize(const NV2080_CTRL_RC_READ_VIRTUAL_MEM_PARAMS *src, finn_bit_pump_for_write *bp, NvBool seri_up); -static NV_STATUS Nv2080CtrlRcReadVirtualMemParamsDeserialize(finn_bit_pump_for_read *bp, NV2080_CTRL_RC_READ_VIRTUAL_MEM_PARAMS *dst, NvLength dst_size, NvBool deser_up); - -static NV_STATUS Nv402cCtrlI2cIndexedParamsSerialize(const NV402C_CTRL_I2C_INDEXED_PARAMS *src, finn_bit_pump_for_write *bp, NvBool seri_up); -static NV_STATUS Nv402cCtrlI2cIndexedParamsDeserialize(finn_bit_pump_for_read *bp, NV402C_CTRL_I2C_INDEXED_PARAMS *dst, NvLength dst_size, NvBool deser_up); -static NV_STATUS Nv402cCtrlI2cTransactionTypeCheckEnum(NV402C_CTRL_I2C_TRANSACTION_TYPE id); -static NV_STATUS Nv402cCtrlI2cTransactionDataSmbusQuickRwSerialize(const NV402C_CTRL_I2C_TRANSACTION_DATA_SMBUS_QUICK_RW *src, finn_bit_pump_for_write *bp, NvBool seri_up); -static NV_STATUS Nv402cCtrlI2cTransactionDataSmbusQuickRwDeserialize(finn_bit_pump_for_read *bp, NV402C_CTRL_I2C_TRANSACTION_DATA_SMBUS_QUICK_RW *dst, NvLength dst_size, NvBool deser_up); -static NV_STATUS Nv402cCtrlI2cTransactionDataI2cByteRwSerialize(const NV402C_CTRL_I2C_TRANSACTION_DATA_I2C_BYTE_RW *src, finn_bit_pump_for_write *bp, NvBool seri_up); -static NV_STATUS Nv402cCtrlI2cTransactionDataI2cByteRwDeserialize(finn_bit_pump_for_read *bp, NV402C_CTRL_I2C_TRANSACTION_DATA_I2C_BYTE_RW *dst, NvLength dst_size, NvBool deser_up); -static NV_STATUS Nv402cCtrlI2cTransactionDataI2cBlockRwSerialize(const NV402C_CTRL_I2C_TRANSACTION_DATA_I2C_BLOCK_RW *src, finn_bit_pump_for_write *bp, NvBool seri_up); -static NV_STATUS Nv402cCtrlI2cTransactionDataI2cBlockRwDeserialize(finn_bit_pump_for_read *bp, NV402C_CTRL_I2C_TRANSACTION_DATA_I2C_BLOCK_RW *dst, NvLength dst_size, NvBool deser_up); -static NV_STATUS Nv402cCtrlI2cTransactionDataSmbusByteRwSerialize(const NV402C_CTRL_I2C_TRANSACTION_DATA_SMBUS_BYTE_RW *src, finn_bit_pump_for_write *bp, NvBool seri_up); -static NV_STATUS Nv402cCtrlI2cTransactionDataSmbusByteRwDeserialize(finn_bit_pump_for_read *bp, NV402C_CTRL_I2C_TRANSACTION_DATA_SMBUS_BYTE_RW *dst, NvLength dst_size, NvBool deser_up); -static NV_STATUS Nv402cCtrlI2cTransactionDataSmbusWordRwSerialize(const NV402C_CTRL_I2C_TRANSACTION_DATA_SMBUS_WORD_RW *src, finn_bit_pump_for_write *bp, NvBool seri_up); -static NV_STATUS Nv402cCtrlI2cTransactionDataSmbusWordRwDeserialize(finn_bit_pump_for_read *bp, NV402C_CTRL_I2C_TRANSACTION_DATA_SMBUS_WORD_RW *dst, NvLength dst_size, NvBool deser_up); -static NV_STATUS Nv402cCtrlI2cTransactionDataI2cBufferRwSerialize(const NV402C_CTRL_I2C_TRANSACTION_DATA_I2C_BUFFER_RW *src, finn_bit_pump_for_write *bp, NvBool seri_up); -static NV_STATUS Nv402cCtrlI2cTransactionDataI2cBufferRwDeserialize(finn_bit_pump_for_read *bp, NV402C_CTRL_I2C_TRANSACTION_DATA_I2C_BUFFER_RW *dst, NvLength dst_size, NvBool deser_up); -static NV_STATUS Nv402cCtrlI2cTransactionDataSmbusBlockRwSerialize(const NV402C_CTRL_I2C_TRANSACTION_DATA_SMBUS_BLOCK_RW *src, finn_bit_pump_for_write *bp, NvBool seri_up); -static NV_STATUS Nv402cCtrlI2cTransactionDataSmbusBlockRwDeserialize(finn_bit_pump_for_read *bp, NV402C_CTRL_I2C_TRANSACTION_DATA_SMBUS_BLOCK_RW *dst, NvLength dst_size, NvBool deser_up); -static NV_STATUS Nv402cCtrlI2cTransactionDataSmbusProcessCallSerialize(const NV402C_CTRL_I2C_TRANSACTION_DATA_SMBUS_PROCESS_CALL *src, finn_bit_pump_for_write *bp, NvBool seri_up); -static NV_STATUS Nv402cCtrlI2cTransactionDataSmbusProcessCallDeserialize(finn_bit_pump_for_read *bp, NV402C_CTRL_I2C_TRANSACTION_DATA_SMBUS_PROCESS_CALL *dst, NvLength dst_size, NvBool deser_up); -static NV_STATUS Nv402cCtrlI2cTransactionDataSmbusBlockProcessCallSerialize(const NV402C_CTRL_I2C_TRANSACTION_DATA_SMBUS_BLOCK_PROCESS_CALL *src, finn_bit_pump_for_write *bp, NvBool seri_up); -static NV_STATUS Nv402cCtrlI2cTransactionDataSmbusBlockProcessCallDeserialize(finn_bit_pump_for_read *bp, NV402C_CTRL_I2C_TRANSACTION_DATA_SMBUS_BLOCK_PROCESS_CALL *dst, NvLength dst_size, NvBool deser_up); -static NV_STATUS Nv402cCtrlI2cTransactionDataSmbusMultibyteRegisterBlockRwSerialize(const NV402C_CTRL_I2C_TRANSACTION_DATA_SMBUS_MULTIBYTE_REGISTER_BLOCK_RW *src, finn_bit_pump_for_write *bp, NvBool seri_up); -static NV_STATUS Nv402cCtrlI2cTransactionDataSmbusMultibyteRegisterBlockRwDeserialize(finn_bit_pump_for_read *bp, NV402C_CTRL_I2C_TRANSACTION_DATA_SMBUS_MULTIBYTE_REGISTER_BLOCK_RW *dst, NvLength dst_size, NvBool deser_up); -static NV_STATUS Nv402cCtrlI2cTransactionDataReadEdidDdcSerialize(const NV402C_CTRL_I2C_TRANSACTION_DATA_READ_EDID_DDC *src, finn_bit_pump_for_write *bp, NvBool seri_up); -static NV_STATUS Nv402cCtrlI2cTransactionDataReadEdidDdcDeserialize(finn_bit_pump_for_read *bp, NV402C_CTRL_I2C_TRANSACTION_DATA_READ_EDID_DDC *dst, NvLength dst_size, NvBool deser_up); -static NV_STATUS Nv402cCtrlI2cTransactionDataSerialize(const NV402C_CTRL_I2C_TRANSACTION_DATA *src, finn_bit_pump_for_write *bp, NvBool seri_up, NV402C_CTRL_I2C_TRANSACTION_TYPE transType); -static NV_STATUS Nv402cCtrlI2cTransactionDataDeserialize(finn_bit_pump_for_read *bp, NV402C_CTRL_I2C_TRANSACTION_DATA *dst, NvLength dst_size, NvBool deser_up, NV402C_CTRL_I2C_TRANSACTION_TYPE transType); -static NV_STATUS Nv402cCtrlI2cTransactionParamsSerialize(const NV402C_CTRL_I2C_TRANSACTION_PARAMS *src, finn_bit_pump_for_write *bp, NvBool seri_up); -static NV_STATUS Nv402cCtrlI2cTransactionParamsDeserialize(finn_bit_pump_for_read *bp, NV402C_CTRL_I2C_TRANSACTION_PARAMS *dst, NvLength dst_size, NvBool deser_up); -static NV_STATUS Nv83deCtrlDebugReadMemoryParamsSerialize(const NV83DE_CTRL_DEBUG_READ_MEMORY_PARAMS *src, finn_bit_pump_for_write *bp, NvBool seri_up); -static NV_STATUS Nv83deCtrlDebugReadMemoryParamsDeserialize(finn_bit_pump_for_read *bp, NV83DE_CTRL_DEBUG_READ_MEMORY_PARAMS *dst, NvLength dst_size, NvBool deser_up); -static NV_STATUS Nv83deCtrlDebugWriteMemoryParamsSerialize(const NV83DE_CTRL_DEBUG_WRITE_MEMORY_PARAMS *src, finn_bit_pump_for_write *bp, NvBool seri_up); -static NV_STATUS Nv83deCtrlDebugWriteMemoryParamsDeserialize(finn_bit_pump_for_read *bp, NV83DE_CTRL_DEBUG_WRITE_MEMORY_PARAMS *dst, NvLength dst_size, NvBool deser_up); -static NV_STATUS Nvb06fCtrlGetEngineCtxDataParamsSerialize(const NVB06F_CTRL_GET_ENGINE_CTX_DATA_PARAMS *src, finn_bit_pump_for_write *bp, NvBool seri_up); -static NV_STATUS Nvb06fCtrlGetEngineCtxDataParamsDeserialize(finn_bit_pump_for_read *bp, NVB06F_CTRL_GET_ENGINE_CTX_DATA_PARAMS *dst, NvLength dst_size, NvBool deser_up); -static NV_STATUS Nvb06fCtrlCmdMigrateEngineCtxDataFinnParamsSerialize(const NVB06F_CTRL_CMD_MIGRATE_ENGINE_CTX_DATA_FINN_PARAMS *src, finn_bit_pump_for_write *bp, NvBool seri_up); -static NV_STATUS Nvb06fCtrlCmdMigrateEngineCtxDataFinnParamsDeserialize(finn_bit_pump_for_read *bp, NVB06F_CTRL_CMD_MIGRATE_ENGINE_CTX_DATA_FINN_PARAMS *dst, NvLength dst_size, NvBool deser_up); -static NV_STATUS Nvb06fCtrlSaveEngineCtxDataParamsSerialize(const NVB06F_CTRL_SAVE_ENGINE_CTX_DATA_PARAMS *src, finn_bit_pump_for_write *bp, NvBool seri_up); -static NV_STATUS Nvb06fCtrlSaveEngineCtxDataParamsDeserialize(finn_bit_pump_for_read *bp, NVB06F_CTRL_SAVE_ENGINE_CTX_DATA_PARAMS *dst, NvLength dst_size, NvBool deser_up); -static NV_STATUS Nvb06fCtrlCmdRestoreEngineCtxDataFinnParamsSerialize(const NVB06F_CTRL_CMD_RESTORE_ENGINE_CTX_DATA_FINN_PARAMS *src, finn_bit_pump_for_write *bp, NvBool seri_up); -static NV_STATUS Nvb06fCtrlCmdRestoreEngineCtxDataFinnParamsDeserialize(finn_bit_pump_for_read *bp, NVB06F_CTRL_CMD_RESTORE_ENGINE_CTX_DATA_FINN_PARAMS *dst, NvLength dst_size, NvBool deser_up); - -NV_STATUS FinnRmApiSerializeUp(NvU64 interface, NvU64 message, const void *src, NvU8 **dst, NvLength dst_size) -{ - return FinnRmApiSerializeInternal(interface, message, (const char *) src, (char **) dst, dst_size / sizeof(NvU8), NV_TRUE); -} - -NV_STATUS FinnRmApiSerializeDown(NvU64 interface, NvU64 message, const void *src, NvU8 **dst, NvLength dst_size) -{ - return FinnRmApiSerializeInternal(interface, message, (const char *) src, (char **) dst, dst_size / sizeof(NvU8), NV_FALSE); -} - -NV_STATUS FinnRmApiDeserializeDown(NvU8 **src, NvLength src_size, void *dst, NvLength dst_size) -{ - return FinnRmApiDeserializeInternal((const char **) src, src_size / sizeof(NvU8), (char *) dst, dst_size, NV_FALSE); -} - -NV_STATUS FinnRmApiDeserializeUp(NvU8 **src, NvLength src_size, void *dst, NvLength dst_size) -{ - return FinnRmApiDeserializeInternal((const char **) src, src_size / sizeof(NvU8), (char *) dst, dst_size, NV_TRUE); -} - - -static NV_STATUS FinnRmApiSerializeInternal(NvU64 interface, NvU64 message, const char *src, char **dst, size_t dst_size, NvBool seri_up) -{ - // Header - FINN_RM_API *header; - - // Buffer end - // `char` is the C-standrd unit of measure for `sizeof` and `size_t`. - const char *dst_end; - - // Bit pump is used to fill the buffer with serialized data. - finn_bit_pump_for_write bp; - - // Error code returned from serialization - NV_STATUS error_code; - - // Input validation - // Null pointers are not permitted. - // Buffer must begin on an 8-byte boundary. - if (!src || !dst || !(*dst) || !dst_size || (uintptr_t) dst & 0x7u) - { - FINN_ERROR(NV_ERR_INVALID_ARGUMENT); - return NV_ERR_INVALID_ARGUMENT; - } - - // Header is at the start of the buffer. - header = (FINN_RM_API *) *dst; - - // Buffer must end on an 8-byte boundary, so round down. - dst_end = (const char *) ((uintptr_t) (*dst + dst_size) & ~ (uintptr_t) 0x7); - - // Set header data. - header->version = FINN_SERIALIZATION_VERSION; - header->payloadSize = 0; // Zero until completed successfully - header->interface = interface; - header->message = message; - - // Advance past header. - (*dst) += sizeof(FINN_RM_API); - - // Open the bit pump. - finn_open_buffer_for_write(&bp, (uint64_t *) *dst, (const uint64_t *) dst_end); - - // Call the serializer. - error_code = FinnRmApiSerializeInterface(interface, message, src, &bp, seri_up); - - // Close the bit pump. - finn_close_buffer_for_write(&bp); - - // Payload size in bytes - if (error_code == NV_OK) - header->payloadSize = (NvU64) (((const char *) bp.buffer_position) - ((const char *) header)); - - // Indicate the ending location. - *dst = (char *) bp.buffer_position; - - // Done - return error_code; -} - - -static NV_STATUS FinnRmApiSerializeInterface(NvU64 interface, NvU64 message, const char *src, finn_bit_pump_for_write *bp, NvBool seri_up) -{ - - - // Forward to interface-specific serialize routine - switch (interface) - { - case FINN_INTERFACE_ID(FINN_NV01_ROOT_NVD): - return FinnNv01RootNvdSerializeMessage(message, src, bp, seri_up); - case FINN_INTERFACE_ID(FINN_NV01_DEVICE_0_DMA): - return FinnNv01Device0DmaSerializeMessage(message, src, bp, seri_up); - case FINN_INTERFACE_ID(FINN_NV01_DEVICE_0_FB): - return FinnNv01Device0FbSerializeMessage(message, src, bp, seri_up); - case FINN_INTERFACE_ID(FINN_NV01_DEVICE_0_FIFO): - return FinnNv01Device0FifoSerializeMessage(message, src, bp, seri_up); - case FINN_INTERFACE_ID(FINN_NV01_DEVICE_0_GPU): - return FinnNv01Device0GpuSerializeMessage(message, src, bp, seri_up); - case FINN_INTERFACE_ID(FINN_NV01_DEVICE_0_GR): - return FinnNv01Device0GrSerializeMessage(message, src, bp, seri_up); - case FINN_INTERFACE_ID(FINN_NV01_DEVICE_0_HOST): - return FinnNv01Device0HostSerializeMessage(message, src, bp, seri_up); - case FINN_INTERFACE_ID(FINN_NV01_DEVICE_0_MSENC): - return FinnNv01Device0MsencSerializeMessage(message, src, bp, seri_up); - case FINN_INTERFACE_ID(FINN_NV20_SUBDEVICE_0_CE): - return FinnNv20Subdevice0CeSerializeMessage(message, src, bp, seri_up); - case FINN_INTERFACE_ID(FINN_NV20_SUBDEVICE_0_GPU): - return FinnNv20Subdevice0GpuSerializeMessage(message, src, bp, seri_up); - case FINN_INTERFACE_ID(FINN_NV20_SUBDEVICE_0_I2C): - return FinnNv20Subdevice0I2cSerializeMessage(message, src, bp, seri_up); - case FINN_INTERFACE_ID(FINN_NV20_SUBDEVICE_0_NVD): - return FinnNv20Subdevice0NvdSerializeMessage(message, src, bp, seri_up); - case FINN_INTERFACE_ID(FINN_NV20_SUBDEVICE_0_PERF): - return FinnNv20Subdevice0PerfSerializeMessage(message, src, bp, seri_up); - case FINN_INTERFACE_ID(FINN_NV20_SUBDEVICE_0_RC): - return FinnNv20Subdevice0RcSerializeMessage(message, src, bp, seri_up); - case FINN_INTERFACE_ID(FINN_NV20_SUBDEVICE_DIAG_GPU): - return FinnNv20SubdeviceDiagGpuSerializeMessage(message, src, bp, seri_up); - case FINN_INTERFACE_ID(FINN_NV40_I2C_I2C): - return FinnNv40I2cI2cSerializeMessage(message, src, bp, seri_up); - case FINN_INTERFACE_ID(FINN_GT200_DEBUGGER_DEBUG): - return FinnGt200DebuggerDebugSerializeMessage(message, src, bp, seri_up); - case FINN_INTERFACE_ID(FINN_MAXWELL_CHANNEL_GPFIFO_A_GPFIFO): - return FinnMaxwellChannelGpfifoAGpfifoSerializeMessage(message, src, bp, seri_up); - - default: - { - FINN_ERROR(NV_ERR_NOT_SUPPORTED); - return NV_ERR_NOT_SUPPORTED; - } - } -} - - -static NV_STATUS FinnRmApiDeserializeInternal(const char **src, NvLength src_size, char *dst, NvLength dst_size, NvBool deser_up) -{ - // Header - const FINN_RM_API *header; - - // End of data - const char *src_max; - - // Bit pump is used to read the serialized data. - finn_bit_pump_for_read bp; - - // Error code - NV_STATUS status; - - // Input validation - // Null pointers are not permitted. - // Buffer must begin on an 8-byte boundary. - if (!src || !(*src) || !src_size || !dst || !dst_size || (uintptr_t) *src & 0x7u) - { - FINN_ERROR(NV_ERR_INVALID_ARGUMENT); - return NV_ERR_INVALID_ARGUMENT; - } - - // Header data comes first. - header = (const FINN_RM_API *) *src; - - // Check the version. - if (header->version != FINN_SERIALIZATION_VERSION) - { - FINN_ERROR(NV_ERR_LIB_RM_VERSION_MISMATCH); - return NV_ERR_LIB_RM_VERSION_MISMATCH; - } - - // Set src_max for buffer bounds checking. - src_max = *src + src_size; - - // Check that source buffer is large enough. - if (sizeof(FINN_RM_API) > src_size || - header->payloadSize > src_size || - header->payloadSize < sizeof(FINN_RM_API)) - { - *src = (const char *) &header->payloadSize; - FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); - return NV_ERR_BUFFER_TOO_SMALL; - } - - // Open the bit punp, skipping past the header. - finn_open_buffer_for_read(&bp, (const uint64_t *) (*src + sizeof(FINN_RM_API)), (const uint64_t *) (src_max)); - - // Dispatch to interface-specific routine - status = FinnRmApiDeserializeInterface(header->interface, header->message, &bp, dst, dst_size, deser_up); - - // Update the buffer position, error or not. - *(src) = (const char *) bp.buffer_position; - - // Nothing more to do if there was an error. - if (status != NV_OK) - return status; - - // Update the checksum. - finn_close_buffer_for_read(&bp); - - // TODO: Check the checksum - - // Check that the declared size matches the serialization outcome. - if (header->payloadSize != (NvU64) (((const char *) bp.buffer_position) - ((const char *) header))) - { - FINN_ERROR(NV_ERR_INVALID_ARGUMENT); - return NV_ERR_INVALID_ARGUMENT; - } - - // All good - return NV_OK; -} - - -static NV_STATUS FinnRmApiDeserializeInterface(NvU64 interface, NvU64 message, finn_bit_pump_for_read *bp, char *dst, NvLength dst_size, NvBool deser_up) -{ - // Forward to interface-specific routine - switch (interface) - { - case FINN_INTERFACE_ID(FINN_NV01_ROOT_NVD): - return FinnNv01RootNvdDeserializeMessage(message, bp, (FINN_NV01_ROOT_NVD *) dst, dst_size, deser_up); - case FINN_INTERFACE_ID(FINN_NV01_DEVICE_0_DMA): - return FinnNv01Device0DmaDeserializeMessage(message, bp, (FINN_NV01_DEVICE_0_DMA *) dst, dst_size, deser_up); - case FINN_INTERFACE_ID(FINN_NV01_DEVICE_0_FB): - return FinnNv01Device0FbDeserializeMessage(message, bp, (FINN_NV01_DEVICE_0_FB *) dst, dst_size, deser_up); - case FINN_INTERFACE_ID(FINN_NV01_DEVICE_0_FIFO): - return FinnNv01Device0FifoDeserializeMessage(message, bp, (FINN_NV01_DEVICE_0_FIFO *) dst, dst_size, deser_up); - case FINN_INTERFACE_ID(FINN_NV01_DEVICE_0_GPU): - return FinnNv01Device0GpuDeserializeMessage(message, bp, (FINN_NV01_DEVICE_0_GPU *) dst, dst_size, deser_up); - case FINN_INTERFACE_ID(FINN_NV01_DEVICE_0_GR): - return FinnNv01Device0GrDeserializeMessage(message, bp, (FINN_NV01_DEVICE_0_GR *) dst, dst_size, deser_up); - case FINN_INTERFACE_ID(FINN_NV01_DEVICE_0_HOST): - return FinnNv01Device0HostDeserializeMessage(message, bp, (FINN_NV01_DEVICE_0_HOST *) dst, dst_size, deser_up); - case FINN_INTERFACE_ID(FINN_NV01_DEVICE_0_MSENC): - return FinnNv01Device0MsencDeserializeMessage(message, bp, (FINN_NV01_DEVICE_0_MSENC *) dst, dst_size, deser_up); - case FINN_INTERFACE_ID(FINN_NV20_SUBDEVICE_0_CE): - return FinnNv20Subdevice0CeDeserializeMessage(message, bp, (FINN_NV20_SUBDEVICE_0_CE *) dst, dst_size, deser_up); - case FINN_INTERFACE_ID(FINN_NV20_SUBDEVICE_0_GPU): - return FinnNv20Subdevice0GpuDeserializeMessage(message, bp, (FINN_NV20_SUBDEVICE_0_GPU *) dst, dst_size, deser_up); - case FINN_INTERFACE_ID(FINN_NV20_SUBDEVICE_0_I2C): - return FinnNv20Subdevice0I2cDeserializeMessage(message, bp, (FINN_NV20_SUBDEVICE_0_I2C *) dst, dst_size, deser_up); - case FINN_INTERFACE_ID(FINN_NV20_SUBDEVICE_0_NVD): - return FinnNv20Subdevice0NvdDeserializeMessage(message, bp, (FINN_NV20_SUBDEVICE_0_NVD *) dst, dst_size, deser_up); - case FINN_INTERFACE_ID(FINN_NV20_SUBDEVICE_0_PERF): - return FinnNv20Subdevice0PerfDeserializeMessage(message, bp, (FINN_NV20_SUBDEVICE_0_PERF *) dst, dst_size, deser_up); - case FINN_INTERFACE_ID(FINN_NV20_SUBDEVICE_0_RC): - return FinnNv20Subdevice0RcDeserializeMessage(message, bp, (FINN_NV20_SUBDEVICE_0_RC *) dst, dst_size, deser_up); - case FINN_INTERFACE_ID(FINN_NV20_SUBDEVICE_DIAG_GPU): - return FinnNv20SubdeviceDiagGpuDeserializeMessage(message, bp, (FINN_NV20_SUBDEVICE_DIAG_GPU *) dst, dst_size, deser_up); - case FINN_INTERFACE_ID(FINN_NV40_I2C_I2C): - return FinnNv40I2cI2cDeserializeMessage(message, bp, (FINN_NV40_I2C_I2C *) dst, dst_size, deser_up); - case FINN_INTERFACE_ID(FINN_GT200_DEBUGGER_DEBUG): - return FinnGt200DebuggerDebugDeserializeMessage(message, bp, (FINN_GT200_DEBUGGER_DEBUG *) dst, dst_size, deser_up); - case FINN_INTERFACE_ID(FINN_MAXWELL_CHANNEL_GPFIFO_A_GPFIFO): - return FinnMaxwellChannelGpfifoAGpfifoDeserializeMessage(message, bp, (FINN_MAXWELL_CHANNEL_GPFIFO_A_GPFIFO *) dst, dst_size, deser_up); - - default: - { - FINN_ERROR(NV_ERR_NOT_SUPPORTED); - return NV_ERR_NOT_SUPPORTED; - } - } -} - - -NvU64 FinnRmApiGetSerializedSize(NvU64 interface, NvU64 message, const NvP64 src) -{ - // Bit pump with writing disabled. - finn_bit_pump_for_write bp; - finn_open_buffer_for_write(&bp, (uint64_t *) 0, (const uint64_t *) 0); - - // Call the serializer with write-suppressed bit pump. - // The size is the same in bith directions (up/down). - // Eeturn zero on error to indicate that this API is not serialized by FINN. - if (FinnRmApiSerializeInterface(interface, message, (const char *) NvP64_VALUE(src), &bp, 0) != NV_OK) - return 0; - - // Close the bit pump. - finn_close_buffer_for_write(&bp); - - // Add the header size in bytes to the amount of data serialzied. - // `buffer_position` is the payload size (not really the buffer position). - return (NvU64) NV_PTR_TO_NvP64(bp.buffer_position) + sizeof(FINN_RM_API); -} - - -NvU64 FinnRmApiGetUnserializedSize(NvU64 interface, NvU64 message) -{ - // Forward to interface-specific routine - switch (interface) - { - case FINN_INTERFACE_ID(FINN_NV01_ROOT_NVD): - return FinnNv01RootNvdGetUnserializedSize(message); - case FINN_INTERFACE_ID(FINN_NV01_DEVICE_0_DMA): - return FinnNv01Device0DmaGetUnserializedSize(message); - case FINN_INTERFACE_ID(FINN_NV01_DEVICE_0_FB): - return FinnNv01Device0FbGetUnserializedSize(message); - case FINN_INTERFACE_ID(FINN_NV01_DEVICE_0_FIFO): - return FinnNv01Device0FifoGetUnserializedSize(message); - case FINN_INTERFACE_ID(FINN_NV01_DEVICE_0_GPU): - return FinnNv01Device0GpuGetUnserializedSize(message); - case FINN_INTERFACE_ID(FINN_NV01_DEVICE_0_GR): - return FinnNv01Device0GrGetUnserializedSize(message); - case FINN_INTERFACE_ID(FINN_NV01_DEVICE_0_HOST): - return FinnNv01Device0HostGetUnserializedSize(message); - case FINN_INTERFACE_ID(FINN_NV01_DEVICE_0_MSENC): - return FinnNv01Device0MsencGetUnserializedSize(message); - case FINN_INTERFACE_ID(FINN_NV20_SUBDEVICE_0_CE): - return FinnNv20Subdevice0CeGetUnserializedSize(message); - case FINN_INTERFACE_ID(FINN_NV20_SUBDEVICE_0_GPU): - return FinnNv20Subdevice0GpuGetUnserializedSize(message); - case FINN_INTERFACE_ID(FINN_NV20_SUBDEVICE_0_I2C): - return FinnNv20Subdevice0I2cGetUnserializedSize(message); - case FINN_INTERFACE_ID(FINN_NV20_SUBDEVICE_0_NVD): - return FinnNv20Subdevice0NvdGetUnserializedSize(message); - case FINN_INTERFACE_ID(FINN_NV20_SUBDEVICE_0_PERF): - return FinnNv20Subdevice0PerfGetUnserializedSize(message); - case FINN_INTERFACE_ID(FINN_NV20_SUBDEVICE_0_RC): - return FinnNv20Subdevice0RcGetUnserializedSize(message); - case FINN_INTERFACE_ID(FINN_NV20_SUBDEVICE_DIAG_GPU): - return FinnNv20SubdeviceDiagGpuGetUnserializedSize(message); - case FINN_INTERFACE_ID(FINN_NV40_I2C_I2C): - return FinnNv40I2cI2cGetUnserializedSize(message); - case FINN_INTERFACE_ID(FINN_GT200_DEBUGGER_DEBUG): - return FinnGt200DebuggerDebugGetUnserializedSize(message); - case FINN_INTERFACE_ID(FINN_MAXWELL_CHANNEL_GPFIFO_A_GPFIFO): - return FinnMaxwellChannelGpfifoAGpfifoGetUnserializedSize(message); - default: - return 0; - } -} - -static NV_STATUS FinnNv01RootNvdSerializeMessage(NvU64 message, const char *src, finn_bit_pump_for_write *bp, NvBool seri_up) -{ - // Forward to message-specific routine. - switch (message) - { - case FINN_MESSAGE_ID(NV0000_CTRL_NVD_GET_DUMP_PARAMS): - return Nv0000CtrlNvdGetDumpParamsSerialize((const NV0000_CTRL_NVD_GET_DUMP_PARAMS *) src, bp, seri_up); - - // Everything else is unsupported. - default: - { - FINN_ERROR(NV_ERR_NOT_SUPPORTED); - return NV_ERR_NOT_SUPPORTED; - } - } -} - -static NV_STATUS FinnNv01RootNvdDeserializeMessage(NvU64 message, finn_bit_pump_for_read *bp, FINN_NV01_ROOT_NVD *dst, NvLength dst_size, NvBool deser_up) -{ - // Forward to message-specific routine. - switch (message) - { - case FINN_MESSAGE_ID(NV0000_CTRL_NVD_GET_DUMP_PARAMS): - return Nv0000CtrlNvdGetDumpParamsDeserialize(bp, (NV0000_CTRL_NVD_GET_DUMP_PARAMS *) dst, dst_size, deser_up); - - // Everything else is unsupported. - default: - { - FINN_ERROR(NV_ERR_NOT_SUPPORTED); - return NV_ERR_NOT_SUPPORTED; - } - } -} - -static NvU64 FinnNv01RootNvdGetUnserializedSize(NvU64 message) -{ - // Forward to message-specific routine. - switch (message) - { - case FINN_MESSAGE_ID(NV0000_CTRL_NVD_GET_DUMP_PARAMS): - return sizeof(NV0000_CTRL_NVD_GET_DUMP_PARAMS); - default: - return 0; - } -} - -static NV_STATUS FinnNv01Device0DmaSerializeMessage(NvU64 message, const char *src, finn_bit_pump_for_write *bp, NvBool seri_up) -{ - // Forward to message-specific routine. - switch (message) - { - case FINN_MESSAGE_ID(NV0080_CTRL_DMA_UPDATE_PDE_2_PARAMS): - return Nv0080CtrlDmaUpdatePde2ParamsSerialize((const NV0080_CTRL_DMA_UPDATE_PDE_2_PARAMS *) src, bp, seri_up); - - // Everything else is unsupported. - default: - { - FINN_ERROR(NV_ERR_NOT_SUPPORTED); - return NV_ERR_NOT_SUPPORTED; - } - } -} - -static NV_STATUS FinnNv01Device0DmaDeserializeMessage(NvU64 message, finn_bit_pump_for_read *bp, FINN_NV01_DEVICE_0_DMA *dst, NvLength dst_size, NvBool deser_up) -{ - // Forward to message-specific routine. - switch (message) - { - case FINN_MESSAGE_ID(NV0080_CTRL_DMA_UPDATE_PDE_2_PARAMS): - return Nv0080CtrlDmaUpdatePde2ParamsDeserialize(bp, (NV0080_CTRL_DMA_UPDATE_PDE_2_PARAMS *) dst, dst_size, deser_up); - - // Everything else is unsupported. - default: - { - FINN_ERROR(NV_ERR_NOT_SUPPORTED); - return NV_ERR_NOT_SUPPORTED; - } - } -} - -static NvU64 FinnNv01Device0DmaGetUnserializedSize(NvU64 message) -{ - // Forward to message-specific routine. - switch (message) - { - case FINN_MESSAGE_ID(NV0080_CTRL_DMA_UPDATE_PDE_2_PARAMS): - return sizeof(NV0080_CTRL_DMA_UPDATE_PDE_2_PARAMS); - default: - return 0; - } -} - -static NV_STATUS FinnNv01Device0FbSerializeMessage(NvU64 message, const char *src, finn_bit_pump_for_write *bp, NvBool seri_up) -{ - // Forward to message-specific routine. - switch (message) - { - case FINN_MESSAGE_ID(NV0080_CTRL_FB_GET_CAPS_PARAMS): - return Nv0080CtrlFbGetCapsParamsSerialize((const NV0080_CTRL_FB_GET_CAPS_PARAMS *) src, bp, seri_up); - - // Everything else is unsupported. - default: - { - FINN_ERROR(NV_ERR_NOT_SUPPORTED); - return NV_ERR_NOT_SUPPORTED; - } - } -} - -static NV_STATUS FinnNv01Device0FbDeserializeMessage(NvU64 message, finn_bit_pump_for_read *bp, FINN_NV01_DEVICE_0_FB *dst, NvLength dst_size, NvBool deser_up) -{ - // Forward to message-specific routine. - switch (message) - { - case FINN_MESSAGE_ID(NV0080_CTRL_FB_GET_CAPS_PARAMS): - return Nv0080CtrlFbGetCapsParamsDeserialize(bp, (NV0080_CTRL_FB_GET_CAPS_PARAMS *) dst, dst_size, deser_up); - - // Everything else is unsupported. - default: - { - FINN_ERROR(NV_ERR_NOT_SUPPORTED); - return NV_ERR_NOT_SUPPORTED; - } - } -} - -static NvU64 FinnNv01Device0FbGetUnserializedSize(NvU64 message) -{ - // Forward to message-specific routine. - switch (message) - { - case FINN_MESSAGE_ID(NV0080_CTRL_FB_GET_CAPS_PARAMS): - return sizeof(NV0080_CTRL_FB_GET_CAPS_PARAMS); - default: - return 0; - } -} - -static NV_STATUS FinnNv01Device0FifoSerializeMessage(NvU64 message, const char *src, finn_bit_pump_for_write *bp, NvBool seri_up) -{ - // Forward to message-specific routine. - switch (message) - { - case FINN_MESSAGE_ID(NV0080_CTRL_FIFO_GET_CAPS_PARAMS): - return Nv0080CtrlFifoGetCapsParamsSerialize((const NV0080_CTRL_FIFO_GET_CAPS_PARAMS *) src, bp, seri_up); - case FINN_MESSAGE_ID(NV0080_CTRL_FIFO_START_SELECTED_CHANNELS_PARAMS): - return Nv0080CtrlFifoStartSelectedChannelsParamsSerialize((const NV0080_CTRL_FIFO_START_SELECTED_CHANNELS_PARAMS *) src, bp, seri_up); - case FINN_MESSAGE_ID(NV0080_CTRL_FIFO_GET_CHANNELLIST_PARAMS): - return Nv0080CtrlFifoGetChannellistParamsSerialize((const NV0080_CTRL_FIFO_GET_CHANNELLIST_PARAMS *) src, bp, seri_up); - - // Everything else is unsupported. - default: - { - FINN_ERROR(NV_ERR_NOT_SUPPORTED); - return NV_ERR_NOT_SUPPORTED; - } - } -} - -static NV_STATUS FinnNv01Device0FifoDeserializeMessage(NvU64 message, finn_bit_pump_for_read *bp, FINN_NV01_DEVICE_0_FIFO *dst, NvLength dst_size, NvBool deser_up) -{ - // Forward to message-specific routine. - switch (message) - { - case FINN_MESSAGE_ID(NV0080_CTRL_FIFO_GET_CAPS_PARAMS): - return Nv0080CtrlFifoGetCapsParamsDeserialize(bp, (NV0080_CTRL_FIFO_GET_CAPS_PARAMS *) dst, dst_size, deser_up); - case FINN_MESSAGE_ID(NV0080_CTRL_FIFO_START_SELECTED_CHANNELS_PARAMS): - return Nv0080CtrlFifoStartSelectedChannelsParamsDeserialize(bp, (NV0080_CTRL_FIFO_START_SELECTED_CHANNELS_PARAMS *) dst, dst_size, deser_up); - case FINN_MESSAGE_ID(NV0080_CTRL_FIFO_GET_CHANNELLIST_PARAMS): - return Nv0080CtrlFifoGetChannellistParamsDeserialize(bp, (NV0080_CTRL_FIFO_GET_CHANNELLIST_PARAMS *) dst, dst_size, deser_up); - - // Everything else is unsupported. - default: - { - FINN_ERROR(NV_ERR_NOT_SUPPORTED); - return NV_ERR_NOT_SUPPORTED; - } - } -} - -static NvU64 FinnNv01Device0FifoGetUnserializedSize(NvU64 message) -{ - // Forward to message-specific routine. - switch (message) - { - case FINN_MESSAGE_ID(NV0080_CTRL_FIFO_GET_CAPS_PARAMS): - return sizeof(NV0080_CTRL_FIFO_GET_CAPS_PARAMS); - case FINN_MESSAGE_ID(NV0080_CTRL_FIFO_START_SELECTED_CHANNELS_PARAMS): - return sizeof(NV0080_CTRL_FIFO_START_SELECTED_CHANNELS_PARAMS); - case FINN_MESSAGE_ID(NV0080_CTRL_FIFO_GET_CHANNELLIST_PARAMS): - return sizeof(NV0080_CTRL_FIFO_GET_CHANNELLIST_PARAMS); - default: - return 0; - } -} - -static NV_STATUS FinnNv01Device0GpuSerializeMessage(NvU64 message, const char *src, finn_bit_pump_for_write *bp, NvBool seri_up) -{ - // Forward to message-specific routine. - switch (message) - { - case FINN_MESSAGE_ID(NV0080_CTRL_GPU_GET_CLASSLIST_PARAMS): - return Nv0080CtrlGpuGetClasslistParamsSerialize((const NV0080_CTRL_GPU_GET_CLASSLIST_PARAMS *) src, bp, seri_up); - - // Everything else is unsupported. - default: - { - FINN_ERROR(NV_ERR_NOT_SUPPORTED); - return NV_ERR_NOT_SUPPORTED; - } - } -} - -static NV_STATUS FinnNv01Device0GpuDeserializeMessage(NvU64 message, finn_bit_pump_for_read *bp, FINN_NV01_DEVICE_0_GPU *dst, NvLength dst_size, NvBool deser_up) -{ - // Forward to message-specific routine. - switch (message) - { - case FINN_MESSAGE_ID(NV0080_CTRL_GPU_GET_CLASSLIST_PARAMS): - return Nv0080CtrlGpuGetClasslistParamsDeserialize(bp, (NV0080_CTRL_GPU_GET_CLASSLIST_PARAMS *) dst, dst_size, deser_up); - - // Everything else is unsupported. - default: - { - FINN_ERROR(NV_ERR_NOT_SUPPORTED); - return NV_ERR_NOT_SUPPORTED; - } - } -} - -static NvU64 FinnNv01Device0GpuGetUnserializedSize(NvU64 message) -{ - // Forward to message-specific routine. - switch (message) - { - case FINN_MESSAGE_ID(NV0080_CTRL_GPU_GET_CLASSLIST_PARAMS): - return sizeof(NV0080_CTRL_GPU_GET_CLASSLIST_PARAMS); - default: - return 0; - } -} - -static NV_STATUS FinnNv01Device0GrSerializeMessage(NvU64 message, const char *src, finn_bit_pump_for_write *bp, NvBool seri_up) -{ - // Forward to message-specific routine. - switch (message) - { - case FINN_MESSAGE_ID(NV0080_CTRL_GR_GET_CAPS_PARAMS): - return Nv0080CtrlGrGetCapsParamsSerialize((const NV0080_CTRL_GR_GET_CAPS_PARAMS *) src, bp, seri_up); - - // Everything else is unsupported. - default: - { - FINN_ERROR(NV_ERR_NOT_SUPPORTED); - return NV_ERR_NOT_SUPPORTED; - } - } -} - -static NV_STATUS FinnNv01Device0GrDeserializeMessage(NvU64 message, finn_bit_pump_for_read *bp, FINN_NV01_DEVICE_0_GR *dst, NvLength dst_size, NvBool deser_up) -{ - // Forward to message-specific routine. - switch (message) - { - case FINN_MESSAGE_ID(NV0080_CTRL_GR_GET_CAPS_PARAMS): - return Nv0080CtrlGrGetCapsParamsDeserialize(bp, (NV0080_CTRL_GR_GET_CAPS_PARAMS *) dst, dst_size, deser_up); - - // Everything else is unsupported. - default: - { - FINN_ERROR(NV_ERR_NOT_SUPPORTED); - return NV_ERR_NOT_SUPPORTED; - } - } -} - -static NvU64 FinnNv01Device0GrGetUnserializedSize(NvU64 message) -{ - // Forward to message-specific routine. - switch (message) - { - case FINN_MESSAGE_ID(NV0080_CTRL_GR_GET_CAPS_PARAMS): - return sizeof(NV0080_CTRL_GR_GET_CAPS_PARAMS); - default: - return 0; - } -} - -static NV_STATUS FinnNv01Device0HostSerializeMessage(NvU64 message, const char *src, finn_bit_pump_for_write *bp, NvBool seri_up) -{ - // Forward to message-specific routine. - switch (message) - { - case FINN_MESSAGE_ID(NV0080_CTRL_HOST_GET_CAPS_PARAMS): - return Nv0080CtrlHostGetCapsParamsSerialize((const NV0080_CTRL_HOST_GET_CAPS_PARAMS *) src, bp, seri_up); - - // Everything else is unsupported. - default: - { - FINN_ERROR(NV_ERR_NOT_SUPPORTED); - return NV_ERR_NOT_SUPPORTED; - } - } -} - -static NV_STATUS FinnNv01Device0HostDeserializeMessage(NvU64 message, finn_bit_pump_for_read *bp, FINN_NV01_DEVICE_0_HOST *dst, NvLength dst_size, NvBool deser_up) -{ - // Forward to message-specific routine. - switch (message) - { - case FINN_MESSAGE_ID(NV0080_CTRL_HOST_GET_CAPS_PARAMS): - return Nv0080CtrlHostGetCapsParamsDeserialize(bp, (NV0080_CTRL_HOST_GET_CAPS_PARAMS *) dst, dst_size, deser_up); - - // Everything else is unsupported. - default: - { - FINN_ERROR(NV_ERR_NOT_SUPPORTED); - return NV_ERR_NOT_SUPPORTED; - } - } -} - -static NvU64 FinnNv01Device0HostGetUnserializedSize(NvU64 message) -{ - // Forward to message-specific routine. - switch (message) - { - case FINN_MESSAGE_ID(NV0080_CTRL_HOST_GET_CAPS_PARAMS): - return sizeof(NV0080_CTRL_HOST_GET_CAPS_PARAMS); - default: - return 0; - } -} - -static NV_STATUS FinnNv01Device0MsencSerializeMessage(NvU64 message, const char *src, finn_bit_pump_for_write *bp, NvBool seri_up) -{ - // Forward to message-specific routine. - switch (message) - { - case FINN_MESSAGE_ID(NV0080_CTRL_MSENC_GET_CAPS_PARAMS): - return Nv0080CtrlMsencGetCapsParamsSerialize((const NV0080_CTRL_MSENC_GET_CAPS_PARAMS *) src, bp, seri_up); - - // Everything else is unsupported. - default: - { - FINN_ERROR(NV_ERR_NOT_SUPPORTED); - return NV_ERR_NOT_SUPPORTED; - } - } -} - -static NV_STATUS FinnNv01Device0MsencDeserializeMessage(NvU64 message, finn_bit_pump_for_read *bp, FINN_NV01_DEVICE_0_MSENC *dst, NvLength dst_size, NvBool deser_up) -{ - // Forward to message-specific routine. - switch (message) - { - case FINN_MESSAGE_ID(NV0080_CTRL_MSENC_GET_CAPS_PARAMS): - return Nv0080CtrlMsencGetCapsParamsDeserialize(bp, (NV0080_CTRL_MSENC_GET_CAPS_PARAMS *) dst, dst_size, deser_up); - - // Everything else is unsupported. - default: - { - FINN_ERROR(NV_ERR_NOT_SUPPORTED); - return NV_ERR_NOT_SUPPORTED; - } - } -} - -static NvU64 FinnNv01Device0MsencGetUnserializedSize(NvU64 message) -{ - // Forward to message-specific routine. - switch (message) - { - case FINN_MESSAGE_ID(NV0080_CTRL_MSENC_GET_CAPS_PARAMS): - return sizeof(NV0080_CTRL_MSENC_GET_CAPS_PARAMS); - default: - return 0; - } -} - -static NV_STATUS FinnNv20Subdevice0CeSerializeMessage(NvU64 message, const char *src, finn_bit_pump_for_write *bp, NvBool seri_up) -{ - // Forward to message-specific routine. - switch (message) - { - case FINN_MESSAGE_ID(NV2080_CTRL_CE_GET_CAPS_PARAMS): - return Nv2080CtrlCeGetCapsParamsSerialize((const NV2080_CTRL_CE_GET_CAPS_PARAMS *) src, bp, seri_up); - - // Everything else is unsupported. - default: - { - FINN_ERROR(NV_ERR_NOT_SUPPORTED); - return NV_ERR_NOT_SUPPORTED; - } - } -} - -static NV_STATUS FinnNv20Subdevice0CeDeserializeMessage(NvU64 message, finn_bit_pump_for_read *bp, FINN_NV20_SUBDEVICE_0_CE *dst, NvLength dst_size, NvBool deser_up) -{ - // Forward to message-specific routine. - switch (message) - { - case FINN_MESSAGE_ID(NV2080_CTRL_CE_GET_CAPS_PARAMS): - return Nv2080CtrlCeGetCapsParamsDeserialize(bp, (NV2080_CTRL_CE_GET_CAPS_PARAMS *) dst, dst_size, deser_up); - - // Everything else is unsupported. - default: - { - FINN_ERROR(NV_ERR_NOT_SUPPORTED); - return NV_ERR_NOT_SUPPORTED; - } - } -} - -static NvU64 FinnNv20Subdevice0CeGetUnserializedSize(NvU64 message) -{ - // Forward to message-specific routine. - switch (message) - { - case FINN_MESSAGE_ID(NV2080_CTRL_CE_GET_CAPS_PARAMS): - return sizeof(NV2080_CTRL_CE_GET_CAPS_PARAMS); - default: - return 0; - } -} - -static NV_STATUS FinnNv20Subdevice0GpuSerializeMessage(NvU64 message, const char *src, finn_bit_pump_for_write *bp, NvBool seri_up) -{ - // Forward to message-specific routine. - switch (message) - { - case FINN_MESSAGE_ID(NV2080_CTRL_GPU_GET_ENGINES_PARAMS): - return Nv2080CtrlGpuGetEnginesParamsSerialize((const NV2080_CTRL_GPU_GET_ENGINES_PARAMS *) src, bp, seri_up); - case FINN_MESSAGE_ID(NV2080_CTRL_GPU_GET_ENGINE_CLASSLIST_PARAMS): - return Nv2080CtrlGpuGetEngineClasslistParamsSerialize((const NV2080_CTRL_GPU_GET_ENGINE_CLASSLIST_PARAMS *) src, bp, seri_up); - - // Everything else is unsupported. - default: - { - FINN_ERROR(NV_ERR_NOT_SUPPORTED); - return NV_ERR_NOT_SUPPORTED; - } - } -} - -static NV_STATUS FinnNv20Subdevice0GpuDeserializeMessage(NvU64 message, finn_bit_pump_for_read *bp, FINN_NV20_SUBDEVICE_0_GPU *dst, NvLength dst_size, NvBool deser_up) -{ - // Forward to message-specific routine. - switch (message) - { - case FINN_MESSAGE_ID(NV2080_CTRL_GPU_GET_ENGINES_PARAMS): - return Nv2080CtrlGpuGetEnginesParamsDeserialize(bp, (NV2080_CTRL_GPU_GET_ENGINES_PARAMS *) dst, dst_size, deser_up); - case FINN_MESSAGE_ID(NV2080_CTRL_GPU_GET_ENGINE_CLASSLIST_PARAMS): - return Nv2080CtrlGpuGetEngineClasslistParamsDeserialize(bp, (NV2080_CTRL_GPU_GET_ENGINE_CLASSLIST_PARAMS *) dst, dst_size, deser_up); - - // Everything else is unsupported. - default: - { - FINN_ERROR(NV_ERR_NOT_SUPPORTED); - return NV_ERR_NOT_SUPPORTED; - } - } -} - -static NvU64 FinnNv20Subdevice0GpuGetUnserializedSize(NvU64 message) -{ - // Forward to message-specific routine. - switch (message) - { - case FINN_MESSAGE_ID(NV2080_CTRL_GPU_GET_ENGINES_PARAMS): - return sizeof(NV2080_CTRL_GPU_GET_ENGINES_PARAMS); - case FINN_MESSAGE_ID(NV2080_CTRL_GPU_GET_ENGINE_CLASSLIST_PARAMS): - return sizeof(NV2080_CTRL_GPU_GET_ENGINE_CLASSLIST_PARAMS); - default: - return 0; - } -} - -static NV_STATUS FinnNv20Subdevice0I2cSerializeMessage(NvU64 message, const char *src, finn_bit_pump_for_write *bp, NvBool seri_up) -{ - // Forward to message-specific routine. - switch (message) - { - case FINN_MESSAGE_ID(NV2080_CTRL_I2C_ACCESS_PARAMS): - return Nv2080CtrlI2cAccessParamsSerialize((const NV2080_CTRL_I2C_ACCESS_PARAMS *) src, bp, seri_up); - - // Everything else is unsupported. - default: - { - FINN_ERROR(NV_ERR_NOT_SUPPORTED); - return NV_ERR_NOT_SUPPORTED; - } - } -} - -static NV_STATUS FinnNv20Subdevice0I2cDeserializeMessage(NvU64 message, finn_bit_pump_for_read *bp, FINN_NV20_SUBDEVICE_0_I2C *dst, NvLength dst_size, NvBool deser_up) -{ - // Forward to message-specific routine. - switch (message) - { - case FINN_MESSAGE_ID(NV2080_CTRL_I2C_ACCESS_PARAMS): - return Nv2080CtrlI2cAccessParamsDeserialize(bp, (NV2080_CTRL_I2C_ACCESS_PARAMS *) dst, dst_size, deser_up); - - // Everything else is unsupported. - default: - { - FINN_ERROR(NV_ERR_NOT_SUPPORTED); - return NV_ERR_NOT_SUPPORTED; - } - } -} - -static NvU64 FinnNv20Subdevice0I2cGetUnserializedSize(NvU64 message) -{ - // Forward to message-specific routine. - switch (message) - { - case FINN_MESSAGE_ID(NV2080_CTRL_I2C_ACCESS_PARAMS): - return sizeof(NV2080_CTRL_I2C_ACCESS_PARAMS); - default: - return 0; - } -} - -static NV_STATUS FinnNv20Subdevice0NvdSerializeMessage(NvU64 message, const char *src, finn_bit_pump_for_write *bp, NvBool seri_up) -{ - // Forward to message-specific routine. - switch (message) - { - case FINN_MESSAGE_ID(NV2080_CTRL_NVD_GET_DUMP_PARAMS): - return Nv2080CtrlNvdGetDumpParamsSerialize((const NV2080_CTRL_NVD_GET_DUMP_PARAMS *) src, bp, seri_up); - - // Everything else is unsupported. - default: - { - FINN_ERROR(NV_ERR_NOT_SUPPORTED); - return NV_ERR_NOT_SUPPORTED; - } - } -} - -static NV_STATUS FinnNv20Subdevice0NvdDeserializeMessage(NvU64 message, finn_bit_pump_for_read *bp, FINN_NV20_SUBDEVICE_0_NVD *dst, NvLength dst_size, NvBool deser_up) -{ - // Forward to message-specific routine. - switch (message) - { - case FINN_MESSAGE_ID(NV2080_CTRL_NVD_GET_DUMP_PARAMS): - return Nv2080CtrlNvdGetDumpParamsDeserialize(bp, (NV2080_CTRL_NVD_GET_DUMP_PARAMS *) dst, dst_size, deser_up); - - // Everything else is unsupported. - default: - { - FINN_ERROR(NV_ERR_NOT_SUPPORTED); - return NV_ERR_NOT_SUPPORTED; - } - } -} - -static NvU64 FinnNv20Subdevice0NvdGetUnserializedSize(NvU64 message) -{ - // Forward to message-specific routine. - switch (message) - { - case FINN_MESSAGE_ID(NV2080_CTRL_NVD_GET_DUMP_PARAMS): - return sizeof(NV2080_CTRL_NVD_GET_DUMP_PARAMS); - default: - return 0; - } -} - -static NV_STATUS FinnNv20Subdevice0PerfSerializeMessage(NvU64 message, const char *src, finn_bit_pump_for_write *bp, NvBool seri_up) -{ - // Forward to message-specific routine. - switch (message) - { - case FINN_MESSAGE_ID(NV2080_CTRL_PERF_GET_GPUMON_PERFMON_UTIL_SAMPLES_PARAM): - return Nv2080CtrlGpumonSamplesSerialize((const NV2080_CTRL_PERF_GET_GPUMON_PERFMON_UTIL_SAMPLES_PARAM *) src, bp, seri_up); - - // Everything else is unsupported. - default: - { - FINN_ERROR(NV_ERR_NOT_SUPPORTED); - return NV_ERR_NOT_SUPPORTED; - } - } -} - -static NV_STATUS FinnNv20Subdevice0PerfDeserializeMessage(NvU64 message, finn_bit_pump_for_read *bp, FINN_NV20_SUBDEVICE_0_PERF *dst, NvLength dst_size, NvBool deser_up) -{ - // Forward to message-specific routine. - switch (message) - { - case FINN_MESSAGE_ID(NV2080_CTRL_PERF_GET_GPUMON_PERFMON_UTIL_SAMPLES_PARAM): - return Nv2080CtrlGpumonSamplesDeserialize(bp, (NV2080_CTRL_PERF_GET_GPUMON_PERFMON_UTIL_SAMPLES_PARAM *) dst, dst_size, deser_up); - - // Everything else is unsupported. - default: - { - FINN_ERROR(NV_ERR_NOT_SUPPORTED); - return NV_ERR_NOT_SUPPORTED; - } - } -} - -static NvU64 FinnNv20Subdevice0PerfGetUnserializedSize(NvU64 message) -{ - // Forward to message-specific routine. - switch (message) - { - case FINN_MESSAGE_ID(NV2080_CTRL_PERF_GET_GPUMON_PERFMON_UTIL_SAMPLES_PARAM): - return sizeof(NV2080_CTRL_PERF_GET_GPUMON_PERFMON_UTIL_SAMPLES_PARAM); - default: - return 0; - } -} - -static NV_STATUS FinnNv20Subdevice0RcSerializeMessage(NvU64 message, const char *src, finn_bit_pump_for_write *bp, NvBool seri_up) -{ - // Forward to message-specific routine. - switch (message) - { - case FINN_MESSAGE_ID(NV2080_CTRL_RC_READ_VIRTUAL_MEM_PARAMS): - return Nv2080CtrlRcReadVirtualMemParamsSerialize((const NV2080_CTRL_RC_READ_VIRTUAL_MEM_PARAMS *) src, bp, seri_up); - - // Everything else is unsupported. - default: - { - FINN_ERROR(NV_ERR_NOT_SUPPORTED); - return NV_ERR_NOT_SUPPORTED; - } - } -} - -static NV_STATUS FinnNv20Subdevice0RcDeserializeMessage(NvU64 message, finn_bit_pump_for_read *bp, FINN_NV20_SUBDEVICE_0_RC *dst, NvLength dst_size, NvBool deser_up) -{ - // Forward to message-specific routine. - switch (message) - { - case FINN_MESSAGE_ID(NV2080_CTRL_RC_READ_VIRTUAL_MEM_PARAMS): - return Nv2080CtrlRcReadVirtualMemParamsDeserialize(bp, (NV2080_CTRL_RC_READ_VIRTUAL_MEM_PARAMS *) dst, dst_size, deser_up); - - // Everything else is unsupported. - default: - { - FINN_ERROR(NV_ERR_NOT_SUPPORTED); - return NV_ERR_NOT_SUPPORTED; - } - } -} - -static NvU64 FinnNv20Subdevice0RcGetUnserializedSize(NvU64 message) -{ - // Forward to message-specific routine. - switch (message) - { - case FINN_MESSAGE_ID(NV2080_CTRL_RC_READ_VIRTUAL_MEM_PARAMS): - return sizeof(NV2080_CTRL_RC_READ_VIRTUAL_MEM_PARAMS); - default: - return 0; - } -} - -static NV_STATUS FinnNv20SubdeviceDiagGpuSerializeMessage(NvU64 message, const char *src, finn_bit_pump_for_write *bp, NvBool seri_up) -{ - // Forward to message-specific routine. - switch (message) - { - - // Everything else is unsupported. - default: - { - FINN_ERROR(NV_ERR_NOT_SUPPORTED); - return NV_ERR_NOT_SUPPORTED; - } - } -} - -static NV_STATUS FinnNv20SubdeviceDiagGpuDeserializeMessage(NvU64 message, finn_bit_pump_for_read *bp, FINN_NV20_SUBDEVICE_DIAG_GPU *dst, NvLength dst_size, NvBool deser_up) -{ - // Forward to message-specific routine. - switch (message) - { - - // Everything else is unsupported. - default: - { - FINN_ERROR(NV_ERR_NOT_SUPPORTED); - return NV_ERR_NOT_SUPPORTED; - } - } -} - -static NvU64 FinnNv20SubdeviceDiagGpuGetUnserializedSize(NvU64 message) -{ - // Forward to message-specific routine. - switch (message) - { - default: - return 0; - } -} - -static NV_STATUS FinnNv40I2cI2cSerializeMessage(NvU64 message, const char *src, finn_bit_pump_for_write *bp, NvBool seri_up) -{ - // Forward to message-specific routine. - switch (message) - { - case FINN_MESSAGE_ID(NV402C_CTRL_I2C_INDEXED_PARAMS): - return Nv402cCtrlI2cIndexedParamsSerialize((const NV402C_CTRL_I2C_INDEXED_PARAMS *) src, bp, seri_up); - case FINN_MESSAGE_ID(NV402C_CTRL_I2C_TRANSACTION_PARAMS): - return Nv402cCtrlI2cTransactionParamsSerialize((const NV402C_CTRL_I2C_TRANSACTION_PARAMS *) src, bp, seri_up); - - // Everything else is unsupported. - default: - { - FINN_ERROR(NV_ERR_NOT_SUPPORTED); - return NV_ERR_NOT_SUPPORTED; - } - } -} - -static NV_STATUS FinnNv40I2cI2cDeserializeMessage(NvU64 message, finn_bit_pump_for_read *bp, FINN_NV40_I2C_I2C *dst, NvLength dst_size, NvBool deser_up) -{ - // Forward to message-specific routine. - switch (message) - { - case FINN_MESSAGE_ID(NV402C_CTRL_I2C_INDEXED_PARAMS): - return Nv402cCtrlI2cIndexedParamsDeserialize(bp, (NV402C_CTRL_I2C_INDEXED_PARAMS *) dst, dst_size, deser_up); - case FINN_MESSAGE_ID(NV402C_CTRL_I2C_TRANSACTION_PARAMS): - return Nv402cCtrlI2cTransactionParamsDeserialize(bp, (NV402C_CTRL_I2C_TRANSACTION_PARAMS *) dst, dst_size, deser_up); - - // Everything else is unsupported. - default: - { - FINN_ERROR(NV_ERR_NOT_SUPPORTED); - return NV_ERR_NOT_SUPPORTED; - } - } -} - -static NvU64 FinnNv40I2cI2cGetUnserializedSize(NvU64 message) -{ - // Forward to message-specific routine. - switch (message) - { - case FINN_MESSAGE_ID(NV402C_CTRL_I2C_INDEXED_PARAMS): - return sizeof(NV402C_CTRL_I2C_INDEXED_PARAMS); - case FINN_MESSAGE_ID(NV402C_CTRL_I2C_TRANSACTION_PARAMS): - return sizeof(NV402C_CTRL_I2C_TRANSACTION_PARAMS); - default: - return 0; - } -} - -static NV_STATUS FinnGt200DebuggerDebugSerializeMessage(NvU64 message, const char *src, finn_bit_pump_for_write *bp, NvBool seri_up) -{ - // Forward to message-specific routine. - switch (message) - { - case FINN_MESSAGE_ID(NV83DE_CTRL_DEBUG_READ_MEMORY_PARAMS): - return Nv83deCtrlDebugReadMemoryParamsSerialize((const NV83DE_CTRL_DEBUG_READ_MEMORY_PARAMS *) src, bp, seri_up); - case FINN_MESSAGE_ID(NV83DE_CTRL_DEBUG_WRITE_MEMORY_PARAMS): - return Nv83deCtrlDebugWriteMemoryParamsSerialize((const NV83DE_CTRL_DEBUG_WRITE_MEMORY_PARAMS *) src, bp, seri_up); - - // Everything else is unsupported. - default: - { - FINN_ERROR(NV_ERR_NOT_SUPPORTED); - return NV_ERR_NOT_SUPPORTED; - } - } -} - -static NV_STATUS FinnGt200DebuggerDebugDeserializeMessage(NvU64 message, finn_bit_pump_for_read *bp, FINN_GT200_DEBUGGER_DEBUG *dst, NvLength dst_size, NvBool deser_up) -{ - // Forward to message-specific routine. - switch (message) - { - case FINN_MESSAGE_ID(NV83DE_CTRL_DEBUG_READ_MEMORY_PARAMS): - return Nv83deCtrlDebugReadMemoryParamsDeserialize(bp, (NV83DE_CTRL_DEBUG_READ_MEMORY_PARAMS *) dst, dst_size, deser_up); - case FINN_MESSAGE_ID(NV83DE_CTRL_DEBUG_WRITE_MEMORY_PARAMS): - return Nv83deCtrlDebugWriteMemoryParamsDeserialize(bp, (NV83DE_CTRL_DEBUG_WRITE_MEMORY_PARAMS *) dst, dst_size, deser_up); - - // Everything else is unsupported. - default: - { - FINN_ERROR(NV_ERR_NOT_SUPPORTED); - return NV_ERR_NOT_SUPPORTED; - } - } -} - -static NvU64 FinnGt200DebuggerDebugGetUnserializedSize(NvU64 message) -{ - // Forward to message-specific routine. - switch (message) - { - case FINN_MESSAGE_ID(NV83DE_CTRL_DEBUG_READ_MEMORY_PARAMS): - return sizeof(NV83DE_CTRL_DEBUG_READ_MEMORY_PARAMS); - case FINN_MESSAGE_ID(NV83DE_CTRL_DEBUG_WRITE_MEMORY_PARAMS): - return sizeof(NV83DE_CTRL_DEBUG_WRITE_MEMORY_PARAMS); - default: - return 0; - } -} - -static NV_STATUS FinnMaxwellChannelGpfifoAGpfifoSerializeMessage(NvU64 message, const char *src, finn_bit_pump_for_write *bp, NvBool seri_up) -{ - // Forward to message-specific routine. - switch (message) - { - case FINN_MESSAGE_ID(NVB06F_CTRL_GET_ENGINE_CTX_DATA_PARAMS): - return Nvb06fCtrlGetEngineCtxDataParamsSerialize((const NVB06F_CTRL_GET_ENGINE_CTX_DATA_PARAMS *) src, bp, seri_up); - case FINN_MESSAGE_ID(NVB06F_CTRL_CMD_MIGRATE_ENGINE_CTX_DATA_FINN_PARAMS): - return Nvb06fCtrlCmdMigrateEngineCtxDataFinnParamsSerialize((const NVB06F_CTRL_CMD_MIGRATE_ENGINE_CTX_DATA_FINN_PARAMS *) src, bp, seri_up); - case FINN_MESSAGE_ID(NVB06F_CTRL_SAVE_ENGINE_CTX_DATA_PARAMS): - return Nvb06fCtrlSaveEngineCtxDataParamsSerialize((const NVB06F_CTRL_SAVE_ENGINE_CTX_DATA_PARAMS *) src, bp, seri_up); - case FINN_MESSAGE_ID(NVB06F_CTRL_CMD_RESTORE_ENGINE_CTX_DATA_FINN_PARAMS): - return Nvb06fCtrlCmdRestoreEngineCtxDataFinnParamsSerialize((const NVB06F_CTRL_CMD_RESTORE_ENGINE_CTX_DATA_FINN_PARAMS *) src, bp, seri_up); - - // Everything else is unsupported. - default: - { - FINN_ERROR(NV_ERR_NOT_SUPPORTED); - return NV_ERR_NOT_SUPPORTED; - } - } -} - -static NV_STATUS FinnMaxwellChannelGpfifoAGpfifoDeserializeMessage(NvU64 message, finn_bit_pump_for_read *bp, FINN_MAXWELL_CHANNEL_GPFIFO_A_GPFIFO *dst, NvLength dst_size, NvBool deser_up) -{ - // Forward to message-specific routine. - switch (message) - { - case FINN_MESSAGE_ID(NVB06F_CTRL_GET_ENGINE_CTX_DATA_PARAMS): - return Nvb06fCtrlGetEngineCtxDataParamsDeserialize(bp, (NVB06F_CTRL_GET_ENGINE_CTX_DATA_PARAMS *) dst, dst_size, deser_up); - case FINN_MESSAGE_ID(NVB06F_CTRL_CMD_MIGRATE_ENGINE_CTX_DATA_FINN_PARAMS): - return Nvb06fCtrlCmdMigrateEngineCtxDataFinnParamsDeserialize(bp, (NVB06F_CTRL_CMD_MIGRATE_ENGINE_CTX_DATA_FINN_PARAMS *) dst, dst_size, deser_up); - case FINN_MESSAGE_ID(NVB06F_CTRL_SAVE_ENGINE_CTX_DATA_PARAMS): - return Nvb06fCtrlSaveEngineCtxDataParamsDeserialize(bp, (NVB06F_CTRL_SAVE_ENGINE_CTX_DATA_PARAMS *) dst, dst_size, deser_up); - case FINN_MESSAGE_ID(NVB06F_CTRL_CMD_RESTORE_ENGINE_CTX_DATA_FINN_PARAMS): - return Nvb06fCtrlCmdRestoreEngineCtxDataFinnParamsDeserialize(bp, (NVB06F_CTRL_CMD_RESTORE_ENGINE_CTX_DATA_FINN_PARAMS *) dst, dst_size, deser_up); - - // Everything else is unsupported. - default: - { - FINN_ERROR(NV_ERR_NOT_SUPPORTED); - return NV_ERR_NOT_SUPPORTED; - } - } -} - -static NvU64 FinnMaxwellChannelGpfifoAGpfifoGetUnserializedSize(NvU64 message) -{ - // Forward to message-specific routine. - switch (message) - { - case FINN_MESSAGE_ID(NVB06F_CTRL_GET_ENGINE_CTX_DATA_PARAMS): - return sizeof(NVB06F_CTRL_GET_ENGINE_CTX_DATA_PARAMS); - case FINN_MESSAGE_ID(NVB06F_CTRL_CMD_MIGRATE_ENGINE_CTX_DATA_FINN_PARAMS): - return sizeof(NVB06F_CTRL_CMD_MIGRATE_ENGINE_CTX_DATA_FINN_PARAMS); - case FINN_MESSAGE_ID(NVB06F_CTRL_SAVE_ENGINE_CTX_DATA_PARAMS): - return sizeof(NVB06F_CTRL_SAVE_ENGINE_CTX_DATA_PARAMS); - case FINN_MESSAGE_ID(NVB06F_CTRL_CMD_RESTORE_ENGINE_CTX_DATA_FINN_PARAMS): - return sizeof(NVB06F_CTRL_CMD_RESTORE_ENGINE_CTX_DATA_FINN_PARAMS); - default: - return 0; - } -} - -static NV_STATUS Nv0000CtrlNvdGetDumpParamsSerialize(const NV0000_CTRL_NVD_GET_DUMP_PARAMS *src, finn_bit_pump_for_write *bp, NvBool seri_up) -{ - // Local variables - NV_STATUS status = NV_OK; - uint64_t field_presence_mask; - - // Field bitmasks - field_presence_mask = 0x7; - - // Write field-presence indicators. - if (finn_write_buffer(bp, field_presence_mask, 64)) - { - status = NV_ERR_BUFFER_TOO_SMALL; - FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); - goto exit; - } - - // Statically sized fields - // No range check for src->component - // Deserialize 4-byte NvU32 object. - if (finn_write_buffer(bp, src->component, 4 * 8)) - { - status = NV_ERR_BUFFER_TOO_SMALL; - FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); - goto exit; - } - - - if (src->size > NV0000_CTRL_NVD_MAX_DUMP_SIZE) - { - status = NV_ERR_OUT_OF_RANGE; - FINN_ERROR(NV_ERR_OUT_OF_RANGE); - goto exit; - } - - // Deserialize 4-byte NvU32 object. - if (finn_write_buffer(bp, src->size, 4 * 8)) - { - status = NV_ERR_BUFFER_TOO_SMALL; - FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); - goto exit; - } - - - // Unbounded fields - // Set data-presence indicator. - if (finn_write_buffer(bp, !!(src->pBuffer), 1)) - { - status = NV_ERR_BUFFER_TOO_SMALL; - FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); - goto exit; - } - - // Skip if pointer is null. - if (src->pBuffer) - { - - // Serialize each 1-byte NvU8 element. - for (NvU64 j = 0; j < (src->size); ++j) - { - if (finn_write_buffer(bp, ((NvU8 *) NvP64_VALUE(src->pBuffer))[j], 1 * 8)) - { - status = NV_ERR_BUFFER_TOO_SMALL; - FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); - goto exit; - } - } - - // Free memory that was allocated during downward deserialization. - if (seri_up && src->pBuffer) - FINN_FREE(NvP64_VALUE(src->pBuffer)); - } - - goto exit; // Suppress potential not-used warning -exit: - return status; -} - - -static NV_STATUS Nv0000CtrlNvdGetDumpParamsDeserialize(finn_bit_pump_for_read *bp, NV0000_CTRL_NVD_GET_DUMP_PARAMS *dst, NvLength dst_size, NvBool deser_up) -{ - // Local variables - NV_STATUS status = NV_OK; - - // Check that the destination struct fits within the destination buffer - if (sizeof(NV0000_CTRL_NVD_GET_DUMP_PARAMS) > dst_size) - { - status = NV_ERR_BUFFER_TOO_SMALL; - FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); - goto exit; - } - - // Validate the field bitmasks, which must match the expected values for now. - if (finn_read_buffer(bp, 64) != 0x7) - { - status = NV_ERR_LIB_RM_VERSION_MISMATCH; - FINN_ERROR(NV_ERR_LIB_RM_VERSION_MISMATCH); - goto exit; - } - - // Statically sized fields - // Deserialize 4-byte NvU32 object. - dst->component = (NvU32) finn_read_buffer(bp, 4 * 8); - // No range check for dst->component - - - // Deserialize 4-byte NvU32 object. - dst->size = (NvU32) finn_read_buffer(bp, 4 * 8); - if (dst->size > NV0000_CTRL_NVD_MAX_DUMP_SIZE) - { - status = NV_ERR_OUT_OF_RANGE; - FINN_ERROR(NV_ERR_OUT_OF_RANGE); - goto exit; - } - - - - // Unbounded fields - // Skip if data is not present (null pointer). - if (finn_read_buffer(bp, 1)) - { - - // Allocate memory and set pointer when deserializing down. - // (Calling cods is expected to do so when deserializing up.) - if (!deser_up) - { - dst->pBuffer = FINN_MALLOC((dst->size)); - if (!dst->pBuffer) - { - status = NV_ERR_NO_MEMORY; - FINN_ERROR(NV_ERR_NO_MEMORY); - goto exit; - } - - FINN_MEMZERO(dst->pBuffer, (dst->size)); - } - - // Otherwise the pointer must be provided. - else if (!dst->pBuffer) - { - status = NV_ERR_INVALID_POINTER; - FINN_ERROR(NV_ERR_INVALID_POINTER); - goto exit; - } - - // Deserialize each 1-byte NvU8 element. - for (NvU64 j = 0; j < (dst->size); ++j) - { - ((NvU8 *) NvP64_VALUE(dst->pBuffer))[j] = (NvU8) finn_read_buffer(bp, 1 * 8); - } - } - else - { - if (!deser_up) - dst->pBuffer = NULL; - } - -exit: - return status; -} - - -static NV_STATUS Nv0080CtrlDmaUpdatePde2PageTableParamsSerialize(const NV0080_CTRL_DMA_UPDATE_PDE_2_PAGE_TABLE_PARAMS *src, finn_bit_pump_for_write *bp, NvBool seri_up) -{ - // Local variables - NV_STATUS status = NV_OK; - uint64_t field_presence_mask; - - // Field bitmasks - field_presence_mask = 0x7; - - // Write field-presence indicators. - if (finn_write_buffer(bp, field_presence_mask, 64)) - { - status = NV_ERR_BUFFER_TOO_SMALL; - FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); - goto exit; - } - - // Statically sized fields - // No range check for src->physAddr - // Deserialize 8-byte NvU64 object. - if (finn_write_buffer(bp, src->physAddr, 8 * 8)) - { - status = NV_ERR_BUFFER_TOO_SMALL; - FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); - goto exit; - } - - - // No range check for src->numEntries - // Deserialize 4-byte NvU32 object. - if (finn_write_buffer(bp, src->numEntries, 4 * 8)) - { - status = NV_ERR_BUFFER_TOO_SMALL; - FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); - goto exit; - } - - - // No range check for src->aperture - // Deserialize 4-byte NvU32 object. - if (finn_write_buffer(bp, src->aperture, 4 * 8)) - { - status = NV_ERR_BUFFER_TOO_SMALL; - FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); - goto exit; - } - - - goto exit; // Suppress potential not-used warning -exit: - return status; -} - - -static NV_STATUS Nv0080CtrlDmaUpdatePde2PageTableParamsDeserialize(finn_bit_pump_for_read *bp, NV0080_CTRL_DMA_UPDATE_PDE_2_PAGE_TABLE_PARAMS *dst, NvLength dst_size, NvBool deser_up) -{ - // Local variables - NV_STATUS status = NV_OK; - - // Check that the destination struct fits within the destination buffer - if (sizeof(NV0080_CTRL_DMA_UPDATE_PDE_2_PAGE_TABLE_PARAMS) > dst_size) - { - status = NV_ERR_BUFFER_TOO_SMALL; - FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); - goto exit; - } - - // Validate the field bitmasks, which must match the expected values for now. - if (finn_read_buffer(bp, 64) != 0x7) - { - status = NV_ERR_LIB_RM_VERSION_MISMATCH; - FINN_ERROR(NV_ERR_LIB_RM_VERSION_MISMATCH); - goto exit; - } - - // Statically sized fields - // Deserialize 8-byte NvU64 object. - dst->physAddr = (NvU64) finn_read_buffer(bp, 8 * 8); - // No range check for dst->physAddr - - - // Deserialize 4-byte NvU32 object. - dst->numEntries = (NvU32) finn_read_buffer(bp, 4 * 8); - // No range check for dst->numEntries - - - // Deserialize 4-byte NvU32 object. - dst->aperture = (NvU32) finn_read_buffer(bp, 4 * 8); - // No range check for dst->aperture - - -exit: - return status; -} - - -static NV_STATUS Nv0080CtrlDmaUpdatePde2ParamsSerialize(const NV0080_CTRL_DMA_UPDATE_PDE_2_PARAMS *src, finn_bit_pump_for_write *bp, NvBool seri_up) -{ - // Local variables - NV_STATUS status = NV_OK; - uint64_t field_presence_mask; - - // Field bitmasks - field_presence_mask = 0x3f; - - // Write field-presence indicators. - if (finn_write_buffer(bp, field_presence_mask, 64)) - { - status = NV_ERR_BUFFER_TOO_SMALL; - FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); - goto exit; - } - - // Statically sized fields - // No range check for src->pdeIndex - // Deserialize 4-byte NvU32 object. - if (finn_write_buffer(bp, src->pdeIndex, 4 * 8)) - { - status = NV_ERR_BUFFER_TOO_SMALL; - FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); - goto exit; - } - - - // No range check for src->flags - // Deserialize 4-byte NvU32 object. - if (finn_write_buffer(bp, src->flags, 4 * 8)) - { - status = NV_ERR_BUFFER_TOO_SMALL; - FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); - goto exit; - } - - - // No range check for src->hVASpace - // Deserialize 4-byte NvHandle object. - if (finn_write_buffer(bp, src->hVASpace, 4 * 8)) - { - status = NV_ERR_BUFFER_TOO_SMALL; - FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); - goto exit; - } - - - // No range check for src->subDeviceId - // Deserialize 4-byte NvU32 object. - if (finn_write_buffer(bp, src->subDeviceId, 4 * 8)) - { - status = NV_ERR_BUFFER_TOO_SMALL; - FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); - goto exit; - } - - - // Bounded nested fields - for (NvU64 i = 0; i < (NV0080_CTRL_DMA_UPDATE_PDE_2_PT_IDX__SIZE); ++i) - { - status = Nv0080CtrlDmaUpdatePde2PageTableParamsSerialize(&src->ptParams[i], bp, seri_up); - if (status != NV_OK) - goto exit; - } - - // Unbounded fields - // Set data-presence indicator. - if (finn_write_buffer(bp, !!(src->pPdeBuffer), 1)) - { - status = NV_ERR_BUFFER_TOO_SMALL; - FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); - goto exit; - } - - // Skip if pointer is null. - if (src->pPdeBuffer) - { - - // Serialize each 8-byte NvU64 element. - for (NvU64 j = 0; j < 1; ++j) - { - if (finn_write_buffer(bp, ((NvU64 *) NvP64_VALUE(src->pPdeBuffer))[j], 8 * 8)) - { - status = NV_ERR_BUFFER_TOO_SMALL; - FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); - goto exit; - } - } - - // Free memory that was allocated during downward deserialization. - if (seri_up && src->pPdeBuffer) - FINN_FREE(NvP64_VALUE(src->pPdeBuffer)); - } - - goto exit; // Suppress potential not-used warning -exit: - return status; -} - - -static NV_STATUS Nv0080CtrlDmaUpdatePde2ParamsDeserialize(finn_bit_pump_for_read *bp, NV0080_CTRL_DMA_UPDATE_PDE_2_PARAMS *dst, NvLength dst_size, NvBool deser_up) -{ - // Local variables - NV_STATUS status = NV_OK; - - // Check that the destination struct fits within the destination buffer - if (sizeof(NV0080_CTRL_DMA_UPDATE_PDE_2_PARAMS) > dst_size) - { - status = NV_ERR_BUFFER_TOO_SMALL; - FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); - goto exit; - } - - // Validate the field bitmasks, which must match the expected values for now. - if (finn_read_buffer(bp, 64) != 0x3f) - { - status = NV_ERR_LIB_RM_VERSION_MISMATCH; - FINN_ERROR(NV_ERR_LIB_RM_VERSION_MISMATCH); - goto exit; - } - - // Statically sized fields - // Deserialize 4-byte NvU32 object. - dst->pdeIndex = (NvU32) finn_read_buffer(bp, 4 * 8); - // No range check for dst->pdeIndex - - - // Deserialize 4-byte NvU32 object. - dst->flags = (NvU32) finn_read_buffer(bp, 4 * 8); - // No range check for dst->flags - - - // Deserialize 4-byte NvHandle object. - dst->hVASpace = (NvHandle) finn_read_buffer(bp, 4 * 8); - // No range check for dst->hVASpace - - - // Deserialize 4-byte NvU32 object. - dst->subDeviceId = (NvU32) finn_read_buffer(bp, 4 * 8); - // No range check for dst->subDeviceId - - - // Bounded nested fields - for (NvU64 i = 0; i < (NV0080_CTRL_DMA_UPDATE_PDE_2_PT_IDX__SIZE); ++i) - { - status = Nv0080CtrlDmaUpdatePde2PageTableParamsDeserialize(bp, &dst->ptParams[i], dst_size, deser_up); - if (status != NV_OK) - goto exit; - } - - // Unbounded fields - // Skip if data is not present (null pointer). - if (finn_read_buffer(bp, 1)) - { - - // Allocate memory and set pointer when deserializing down. - // (Calling cods is expected to do so when deserializing up.) - if (!deser_up) - { - dst->pPdeBuffer = FINN_MALLOC(8); - if (!dst->pPdeBuffer) - { - status = NV_ERR_NO_MEMORY; - FINN_ERROR(NV_ERR_NO_MEMORY); - goto exit; - } - - FINN_MEMZERO(dst->pPdeBuffer, 8); - } - - // Otherwise the pointer must be provided. - else if (!dst->pPdeBuffer) - { - status = NV_ERR_INVALID_POINTER; - FINN_ERROR(NV_ERR_INVALID_POINTER); - goto exit; - } - - // Deserialize each 8-byte NvU64 element. - for (NvU64 j = 0; j < 1; ++j) - { - ((NvU64 *) NvP64_VALUE(dst->pPdeBuffer))[j] = (NvU64) finn_read_buffer(bp, 8 * 8); - } - } - else - { - if (!deser_up) - dst->pPdeBuffer = NULL; - } - -exit: - return status; -} - - -static NV_STATUS Nv0080CtrlFbGetCapsParamsSerialize(const NV0080_CTRL_FB_GET_CAPS_PARAMS *src, finn_bit_pump_for_write *bp, NvBool seri_up) -{ - // Local variables - NV_STATUS status = NV_OK; - uint64_t field_presence_mask; - - // Field bitmasks - field_presence_mask = 0x3; - - // Write field-presence indicators. - if (finn_write_buffer(bp, field_presence_mask, 64)) - { - status = NV_ERR_BUFFER_TOO_SMALL; - FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); - goto exit; - } - - // Statically sized fields - if (src->capsTblSize > NV0080_CTRL_FB_CAPS_TBL_SIZE) - { - status = NV_ERR_OUT_OF_RANGE; - FINN_ERROR(NV_ERR_OUT_OF_RANGE); - goto exit; - } - - // Deserialize 4-byte NvU32 object. - if (finn_write_buffer(bp, src->capsTblSize, 4 * 8)) - { - status = NV_ERR_BUFFER_TOO_SMALL; - FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); - goto exit; - } - - - // Unbounded fields - // Set data-presence indicator. - if (finn_write_buffer(bp, !!(src->capsTbl), 1)) - { - status = NV_ERR_BUFFER_TOO_SMALL; - FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); - goto exit; - } - - // Skip if pointer is null. - if (src->capsTbl) - { - - // Serialize each 1-byte NvU8 element. - for (NvU64 j = 0; j < (src->capsTblSize); ++j) - { - if (finn_write_buffer(bp, ((NvU8 *) NvP64_VALUE(src->capsTbl))[j], 1 * 8)) - { - status = NV_ERR_BUFFER_TOO_SMALL; - FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); - goto exit; - } - } - - // Free memory that was allocated during downward deserialization. - if (seri_up && src->capsTbl) - FINN_FREE(NvP64_VALUE(src->capsTbl)); - } - - goto exit; // Suppress potential not-used warning -exit: - return status; -} - - -static NV_STATUS Nv0080CtrlFbGetCapsParamsDeserialize(finn_bit_pump_for_read *bp, NV0080_CTRL_FB_GET_CAPS_PARAMS *dst, NvLength dst_size, NvBool deser_up) -{ - // Local variables - NV_STATUS status = NV_OK; - - // Check that the destination struct fits within the destination buffer - if (sizeof(NV0080_CTRL_FB_GET_CAPS_PARAMS) > dst_size) - { - status = NV_ERR_BUFFER_TOO_SMALL; - FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); - goto exit; - } - - // Validate the field bitmasks, which must match the expected values for now. - if (finn_read_buffer(bp, 64) != 0x3) - { - status = NV_ERR_LIB_RM_VERSION_MISMATCH; - FINN_ERROR(NV_ERR_LIB_RM_VERSION_MISMATCH); - goto exit; - } - - // Statically sized fields - // Deserialize 4-byte NvU32 object. - dst->capsTblSize = (NvU32) finn_read_buffer(bp, 4 * 8); - if (dst->capsTblSize > NV0080_CTRL_FB_CAPS_TBL_SIZE) - { - status = NV_ERR_OUT_OF_RANGE; - FINN_ERROR(NV_ERR_OUT_OF_RANGE); - goto exit; - } - - - - // Unbounded fields - // Skip if data is not present (null pointer). - if (finn_read_buffer(bp, 1)) - { - - // Allocate memory and set pointer when deserializing down. - // (Calling cods is expected to do so when deserializing up.) - if (!deser_up) - { - dst->capsTbl = FINN_MALLOC((dst->capsTblSize)); - if (!dst->capsTbl) - { - status = NV_ERR_NO_MEMORY; - FINN_ERROR(NV_ERR_NO_MEMORY); - goto exit; - } - - FINN_MEMZERO(dst->capsTbl, (dst->capsTblSize)); - } - - // Otherwise the pointer must be provided. - else if (!dst->capsTbl) - { - status = NV_ERR_INVALID_POINTER; - FINN_ERROR(NV_ERR_INVALID_POINTER); - goto exit; - } - - // Deserialize each 1-byte NvU8 element. - for (NvU64 j = 0; j < (dst->capsTblSize); ++j) - { - ((NvU8 *) NvP64_VALUE(dst->capsTbl))[j] = (NvU8) finn_read_buffer(bp, 1 * 8); - } - } - else - { - if (!deser_up) - dst->capsTbl = NULL; - } - -exit: - return status; -} - - -static NV_STATUS Nv0080CtrlFifoGetCapsParamsSerialize(const NV0080_CTRL_FIFO_GET_CAPS_PARAMS *src, finn_bit_pump_for_write *bp, NvBool seri_up) -{ - // Local variables - NV_STATUS status = NV_OK; - uint64_t field_presence_mask; - - // Field bitmasks - field_presence_mask = 0x3; - - // Write field-presence indicators. - if (finn_write_buffer(bp, field_presence_mask, 64)) - { - status = NV_ERR_BUFFER_TOO_SMALL; - FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); - goto exit; - } - - // Statically sized fields - if (src->capsTblSize > NV0080_CTRL_FIFO_CAPS_TBL_SIZE) - { - status = NV_ERR_OUT_OF_RANGE; - FINN_ERROR(NV_ERR_OUT_OF_RANGE); - goto exit; - } - - // Deserialize 4-byte NvU32 object. - if (finn_write_buffer(bp, src->capsTblSize, 4 * 8)) - { - status = NV_ERR_BUFFER_TOO_SMALL; - FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); - goto exit; - } - - - // Unbounded fields - // Set data-presence indicator. - if (finn_write_buffer(bp, !!(src->capsTbl), 1)) - { - status = NV_ERR_BUFFER_TOO_SMALL; - FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); - goto exit; - } - - // Skip if pointer is null. - if (src->capsTbl) - { - - // Serialize each 1-byte NvU8 element. - for (NvU64 j = 0; j < (src->capsTblSize); ++j) - { - if (finn_write_buffer(bp, ((NvU8 *) NvP64_VALUE(src->capsTbl))[j], 1 * 8)) - { - status = NV_ERR_BUFFER_TOO_SMALL; - FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); - goto exit; - } - } - - // Free memory that was allocated during downward deserialization. - if (seri_up && src->capsTbl) - FINN_FREE(NvP64_VALUE(src->capsTbl)); - } - - goto exit; // Suppress potential not-used warning -exit: - return status; -} - - -static NV_STATUS Nv0080CtrlFifoGetCapsParamsDeserialize(finn_bit_pump_for_read *bp, NV0080_CTRL_FIFO_GET_CAPS_PARAMS *dst, NvLength dst_size, NvBool deser_up) -{ - // Local variables - NV_STATUS status = NV_OK; - - // Check that the destination struct fits within the destination buffer - if (sizeof(NV0080_CTRL_FIFO_GET_CAPS_PARAMS) > dst_size) - { - status = NV_ERR_BUFFER_TOO_SMALL; - FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); - goto exit; - } - - // Validate the field bitmasks, which must match the expected values for now. - if (finn_read_buffer(bp, 64) != 0x3) - { - status = NV_ERR_LIB_RM_VERSION_MISMATCH; - FINN_ERROR(NV_ERR_LIB_RM_VERSION_MISMATCH); - goto exit; - } - - // Statically sized fields - // Deserialize 4-byte NvU32 object. - dst->capsTblSize = (NvU32) finn_read_buffer(bp, 4 * 8); - if (dst->capsTblSize > NV0080_CTRL_FIFO_CAPS_TBL_SIZE) - { - status = NV_ERR_OUT_OF_RANGE; - FINN_ERROR(NV_ERR_OUT_OF_RANGE); - goto exit; - } - - - - // Unbounded fields - // Skip if data is not present (null pointer). - if (finn_read_buffer(bp, 1)) - { - - // Allocate memory and set pointer when deserializing down. - // (Calling cods is expected to do so when deserializing up.) - if (!deser_up) - { - dst->capsTbl = FINN_MALLOC((dst->capsTblSize)); - if (!dst->capsTbl) - { - status = NV_ERR_NO_MEMORY; - FINN_ERROR(NV_ERR_NO_MEMORY); - goto exit; - } - - FINN_MEMZERO(dst->capsTbl, (dst->capsTblSize)); - } - - // Otherwise the pointer must be provided. - else if (!dst->capsTbl) - { - status = NV_ERR_INVALID_POINTER; - FINN_ERROR(NV_ERR_INVALID_POINTER); - goto exit; - } - - // Deserialize each 1-byte NvU8 element. - for (NvU64 j = 0; j < (dst->capsTblSize); ++j) - { - ((NvU8 *) NvP64_VALUE(dst->capsTbl))[j] = (NvU8) finn_read_buffer(bp, 1 * 8); - } - } - else - { - if (!deser_up) - dst->capsTbl = NULL; - } - -exit: - return status; -} - - -static NV_STATUS Nv0080CtrlFifoChannelSerialize(const NV0080_CTRL_FIFO_CHANNEL *src, finn_bit_pump_for_write *bp, NvBool seri_up) -{ - // Local variables - NV_STATUS status = NV_OK; - uint64_t field_presence_mask; - - // Field bitmasks - field_presence_mask = 0x1; - - // Write field-presence indicators. - if (finn_write_buffer(bp, field_presence_mask, 64)) - { - status = NV_ERR_BUFFER_TOO_SMALL; - FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); - goto exit; - } - - // Statically sized fields - // No range check for src->hChannel - // Deserialize 4-byte NvHandle object. - if (finn_write_buffer(bp, src->hChannel, 4 * 8)) - { - status = NV_ERR_BUFFER_TOO_SMALL; - FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); - goto exit; - } - - - goto exit; // Suppress potential not-used warning -exit: - return status; -} - - -static NV_STATUS Nv0080CtrlFifoChannelDeserialize(finn_bit_pump_for_read *bp, NV0080_CTRL_FIFO_CHANNEL *dst, NvLength dst_size, NvBool deser_up) -{ - // Local variables - NV_STATUS status = NV_OK; - - // Check that the destination struct fits within the destination buffer - if (sizeof(NV0080_CTRL_FIFO_CHANNEL) > dst_size) - { - status = NV_ERR_BUFFER_TOO_SMALL; - FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); - goto exit; - } - - // Validate the field bitmasks, which must match the expected values for now. - if (finn_read_buffer(bp, 64) != 0x1) - { - status = NV_ERR_LIB_RM_VERSION_MISMATCH; - FINN_ERROR(NV_ERR_LIB_RM_VERSION_MISMATCH); - goto exit; - } - - // Statically sized fields - // Deserialize 4-byte NvHandle object. - dst->hChannel = (NvHandle) finn_read_buffer(bp, 4 * 8); - // No range check for dst->hChannel - - -exit: - return status; -} - - -static NV_STATUS Nv0080CtrlFifoStartSelectedChannelsParamsSerialize(const NV0080_CTRL_FIFO_START_SELECTED_CHANNELS_PARAMS *src, finn_bit_pump_for_write *bp, NvBool seri_up) -{ - // Local variables - NV_STATUS status = NV_OK; - uint64_t field_presence_mask; - - // Field bitmasks - field_presence_mask = 0x7; - - // Write field-presence indicators. - if (finn_write_buffer(bp, field_presence_mask, 64)) - { - status = NV_ERR_BUFFER_TOO_SMALL; - FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); - goto exit; - } - - // Statically sized fields - // No range check for src->fifoStartChannelListCount - // Deserialize 4-byte NvU32 object. - if (finn_write_buffer(bp, src->fifoStartChannelListCount, 4 * 8)) - { - status = NV_ERR_BUFFER_TOO_SMALL; - FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); - goto exit; - } - - - for (NvU64 i = 0; i < (8); ++i) - { - // No range check for src->channelHandle[i] - // Deserialize 4-byte NvHandle object. - if (finn_write_buffer(bp, src->channelHandle[i], 4 * 8)) - { - status = NV_ERR_BUFFER_TOO_SMALL; - FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); - goto exit; - } - } - - - // Unbounded fields - // Set data-presence indicator. - if (finn_write_buffer(bp, !!(src->fifoStartChannelList), 1)) - { - status = NV_ERR_BUFFER_TOO_SMALL; - FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); - goto exit; - } - - // Skip if pointer is null. - if (src->fifoStartChannelList) - { - for (NvU64 i = 0; i < (src->fifoStartChannelListCount); ++i) - { - status = Nv0080CtrlFifoChannelSerialize(&(((const NV0080_CTRL_FIFO_CHANNEL *) (NvP64_VALUE(src->fifoStartChannelList)))[i]), bp, seri_up); - - if (status != NV_OK) - goto exit; - } - - // Free memory that was allocated during downward deserialization. - if (seri_up && src->fifoStartChannelList) - FINN_FREE(src->fifoStartChannelList); - } - - - goto exit; // Suppress potential not-used warning -exit: - return status; -} - - -static NV_STATUS Nv0080CtrlFifoStartSelectedChannelsParamsDeserialize(finn_bit_pump_for_read *bp, NV0080_CTRL_FIFO_START_SELECTED_CHANNELS_PARAMS *dst, NvLength dst_size, NvBool deser_up) -{ - // Local variables - NV_STATUS status = NV_OK; - - // Check that the destination struct fits within the destination buffer - if (sizeof(NV0080_CTRL_FIFO_START_SELECTED_CHANNELS_PARAMS) > dst_size) - { - status = NV_ERR_BUFFER_TOO_SMALL; - FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); - goto exit; - } - - // Validate the field bitmasks, which must match the expected values for now. - if (finn_read_buffer(bp, 64) != 0x7) - { - status = NV_ERR_LIB_RM_VERSION_MISMATCH; - FINN_ERROR(NV_ERR_LIB_RM_VERSION_MISMATCH); - goto exit; - } - - // Statically sized fields - // Deserialize 4-byte NvU32 object. - dst->fifoStartChannelListCount = (NvU32) finn_read_buffer(bp, 4 * 8); - // No range check for dst->fifoStartChannelListCount - - - for (NvU64 i = 0; i < (8); ++i) - { - // Deserialize 4-byte NvHandle object. - dst->channelHandle[i] = (NvHandle) finn_read_buffer(bp, 4 * 8); - // No range check for dst->channelHandle[i] - } - - - // Unbounded fields - // Skip if data is not present (null pointer). - if (finn_read_buffer(bp, 1)) - { - // Caller must set up the pointers when deserializing down. - if (!deser_up) - { - // Data-presence indicator should be false if empty. - // Check for integer overflow in the element size variable. - if ((dst->fifoStartChannelListCount) < 1 || - (sizeof(NV0080_CTRL_FIFO_CHANNEL) * (dst->fifoStartChannelListCount)) < sizeof(NV0080_CTRL_FIFO_CHANNEL)) - { - status = NV_ERR_BUFFER_TOO_SMALL; - FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); - goto exit; - } - - // Allocate memory and set pointer when deserializing down. - // (Calling cods is expected to do so when deserializing up.) - dst->fifoStartChannelList = FINN_MALLOC((sizeof(NV0080_CTRL_FIFO_CHANNEL) * (dst->fifoStartChannelListCount))); - if (!dst->fifoStartChannelList) - { - status = NV_ERR_NO_MEMORY; - FINN_ERROR(NV_ERR_NO_MEMORY); - goto exit; - } - - FINN_MEMZERO(dst->fifoStartChannelList, (sizeof(NV0080_CTRL_FIFO_CHANNEL) * (dst->fifoStartChannelListCount))); - } - - // Otherwise the pointer must be provided. - else if (!dst->fifoStartChannelList) - { - status = NV_ERR_INVALID_POINTER; - FINN_ERROR(NV_ERR_INVALID_POINTER); - goto exit; - } - - for (NvU64 i = 0; i < (dst->fifoStartChannelListCount); ++i) - { - // Deserialize each element. - status = Nv0080CtrlFifoChannelDeserialize(bp, &(((NV0080_CTRL_FIFO_CHANNEL *) (NvP64_VALUE(dst->fifoStartChannelList)))[i]), sizeof(NV0080_CTRL_FIFO_CHANNEL), deser_up); - if (status != NV_OK) - goto exit; - } - } - - // Data is not present; set to NULL. - else - { - if (!deser_up) - dst->fifoStartChannelList = NULL; - } - - -exit: - return status; -} - - -static NV_STATUS Nv0080CtrlFifoGetChannellistParamsSerialize(const NV0080_CTRL_FIFO_GET_CHANNELLIST_PARAMS *src, finn_bit_pump_for_write *bp, NvBool seri_up) -{ - // Local variables - NV_STATUS status = NV_OK; - uint64_t field_presence_mask; - - // Field bitmasks - field_presence_mask = 0x7; - - // Write field-presence indicators. - if (finn_write_buffer(bp, field_presence_mask, 64)) - { - status = NV_ERR_BUFFER_TOO_SMALL; - FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); - goto exit; - } - - // Statically sized fields - // No range check for src->numChannels - // Deserialize 4-byte NvU32 object. - if (finn_write_buffer(bp, src->numChannels, 4 * 8)) - { - status = NV_ERR_BUFFER_TOO_SMALL; - FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); - goto exit; - } - - - // Unbounded fields - // Set data-presence indicator. - if (finn_write_buffer(bp, !!(src->pChannelHandleList), 1)) - { - status = NV_ERR_BUFFER_TOO_SMALL; - FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); - goto exit; - } - - // Skip if pointer is null. - if (src->pChannelHandleList) - { - - // Serialize each 4-byte NvU32 element. - for (NvU64 j = 0; j < (src->numChannels); ++j) - { - if (finn_write_buffer(bp, ((NvU32 *) NvP64_VALUE(src->pChannelHandleList))[j], 4 * 8)) - { - status = NV_ERR_BUFFER_TOO_SMALL; - FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); - goto exit; - } - } - - // Free memory that was allocated during downward deserialization. - if (seri_up && src->pChannelHandleList) - FINN_FREE(NvP64_VALUE(src->pChannelHandleList)); - } - - // Set data-presence indicator. - if (finn_write_buffer(bp, !!(src->pChannelList), 1)) - { - status = NV_ERR_BUFFER_TOO_SMALL; - FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); - goto exit; - } - - // Skip if pointer is null. - if (src->pChannelList) - { - - // Serialize each 4-byte NvU32 element. - for (NvU64 j = 0; j < (src->numChannels); ++j) - { - if (finn_write_buffer(bp, ((NvU32 *) NvP64_VALUE(src->pChannelList))[j], 4 * 8)) - { - status = NV_ERR_BUFFER_TOO_SMALL; - FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); - goto exit; - } - } - - // Free memory that was allocated during downward deserialization. - if (seri_up && src->pChannelList) - FINN_FREE(NvP64_VALUE(src->pChannelList)); - } - - goto exit; // Suppress potential not-used warning -exit: - return status; -} - - -static NV_STATUS Nv0080CtrlFifoGetChannellistParamsDeserialize(finn_bit_pump_for_read *bp, NV0080_CTRL_FIFO_GET_CHANNELLIST_PARAMS *dst, NvLength dst_size, NvBool deser_up) -{ - // Local variables - NV_STATUS status = NV_OK; - - // Check that the destination struct fits within the destination buffer - if (sizeof(NV0080_CTRL_FIFO_GET_CHANNELLIST_PARAMS) > dst_size) - { - status = NV_ERR_BUFFER_TOO_SMALL; - FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); - goto exit; - } - - // Validate the field bitmasks, which must match the expected values for now. - if (finn_read_buffer(bp, 64) != 0x7) - { - status = NV_ERR_LIB_RM_VERSION_MISMATCH; - FINN_ERROR(NV_ERR_LIB_RM_VERSION_MISMATCH); - goto exit; - } - - // Statically sized fields - // Deserialize 4-byte NvU32 object. - dst->numChannels = (NvU32) finn_read_buffer(bp, 4 * 8); - // No range check for dst->numChannels - - - // Unbounded fields - // Skip if data is not present (null pointer). - if (finn_read_buffer(bp, 1)) - { - - // Allocate memory and set pointer when deserializing down. - // (Calling cods is expected to do so when deserializing up.) - if (!deser_up) - { - dst->pChannelHandleList = FINN_MALLOC((dst->numChannels) * 4); - if (!dst->pChannelHandleList) - { - status = NV_ERR_NO_MEMORY; - FINN_ERROR(NV_ERR_NO_MEMORY); - goto exit; - } - - FINN_MEMZERO(dst->pChannelHandleList, (dst->numChannels) * 4); - } - - // Otherwise the pointer must be provided. - else if (!dst->pChannelHandleList) - { - status = NV_ERR_INVALID_POINTER; - FINN_ERROR(NV_ERR_INVALID_POINTER); - goto exit; - } - - // Deserialize each 4-byte NvU32 element. - for (NvU64 j = 0; j < (dst->numChannels); ++j) - { - ((NvU32 *) NvP64_VALUE(dst->pChannelHandleList))[j] = (NvU32) finn_read_buffer(bp, 4 * 8); - } - } - else - { - if (!deser_up) - dst->pChannelHandleList = NULL; - } - - // Skip if data is not present (null pointer). - if (finn_read_buffer(bp, 1)) - { - - // Allocate memory and set pointer when deserializing down. - // (Calling cods is expected to do so when deserializing up.) - if (!deser_up) - { - dst->pChannelList = FINN_MALLOC((dst->numChannels) * 4); - if (!dst->pChannelList) - { - status = NV_ERR_NO_MEMORY; - FINN_ERROR(NV_ERR_NO_MEMORY); - goto exit; - } - - FINN_MEMZERO(dst->pChannelList, (dst->numChannels) * 4); - } - - // Otherwise the pointer must be provided. - else if (!dst->pChannelList) - { - status = NV_ERR_INVALID_POINTER; - FINN_ERROR(NV_ERR_INVALID_POINTER); - goto exit; - } - - // Deserialize each 4-byte NvU32 element. - for (NvU64 j = 0; j < (dst->numChannels); ++j) - { - ((NvU32 *) NvP64_VALUE(dst->pChannelList))[j] = (NvU32) finn_read_buffer(bp, 4 * 8); - } - } - else - { - if (!deser_up) - dst->pChannelList = NULL; - } - -exit: - return status; -} - - -static NV_STATUS Nv0080CtrlGpuGetClasslistParamsSerialize(const NV0080_CTRL_GPU_GET_CLASSLIST_PARAMS *src, finn_bit_pump_for_write *bp, NvBool seri_up) -{ - // Local variables - NV_STATUS status = NV_OK; - uint64_t field_presence_mask; - - // Field bitmasks - field_presence_mask = 0x3; - - // Write field-presence indicators. - if (finn_write_buffer(bp, field_presence_mask, 64)) - { - status = NV_ERR_BUFFER_TOO_SMALL; - FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); - goto exit; - } - - // Statically sized fields - // No range check for src->numClasses - // Deserialize 4-byte NvU32 object. - if (finn_write_buffer(bp, src->numClasses, 4 * 8)) - { - status = NV_ERR_BUFFER_TOO_SMALL; - FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); - goto exit; - } - - - // Unbounded fields - // Set data-presence indicator. - if (finn_write_buffer(bp, !!(src->classList), 1)) - { - status = NV_ERR_BUFFER_TOO_SMALL; - FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); - goto exit; - } - - // Skip if pointer is null. - if (src->classList) - { - - // Serialize each 4-byte NvU32 element. - for (NvU64 j = 0; j < (src->numClasses); ++j) - { - if (finn_write_buffer(bp, ((NvU32 *) NvP64_VALUE(src->classList))[j], 4 * 8)) - { - status = NV_ERR_BUFFER_TOO_SMALL; - FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); - goto exit; - } - } - - // Free memory that was allocated during downward deserialization. - if (seri_up && src->classList) - FINN_FREE(NvP64_VALUE(src->classList)); - } - - goto exit; // Suppress potential not-used warning -exit: - return status; -} - - -static NV_STATUS Nv0080CtrlGpuGetClasslistParamsDeserialize(finn_bit_pump_for_read *bp, NV0080_CTRL_GPU_GET_CLASSLIST_PARAMS *dst, NvLength dst_size, NvBool deser_up) -{ - // Local variables - NV_STATUS status = NV_OK; - - // Check that the destination struct fits within the destination buffer - if (sizeof(NV0080_CTRL_GPU_GET_CLASSLIST_PARAMS) > dst_size) - { - status = NV_ERR_BUFFER_TOO_SMALL; - FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); - goto exit; - } - - // Validate the field bitmasks, which must match the expected values for now. - if (finn_read_buffer(bp, 64) != 0x3) - { - status = NV_ERR_LIB_RM_VERSION_MISMATCH; - FINN_ERROR(NV_ERR_LIB_RM_VERSION_MISMATCH); - goto exit; - } - - // Statically sized fields - // Deserialize 4-byte NvU32 object. - dst->numClasses = (NvU32) finn_read_buffer(bp, 4 * 8); - // No range check for dst->numClasses - - - // Unbounded fields - // Skip if data is not present (null pointer). - if (finn_read_buffer(bp, 1)) - { - - // Allocate memory and set pointer when deserializing down. - // (Calling cods is expected to do so when deserializing up.) - if (!deser_up) - { - dst->classList = FINN_MALLOC((dst->numClasses) * 4); - if (!dst->classList) - { - status = NV_ERR_NO_MEMORY; - FINN_ERROR(NV_ERR_NO_MEMORY); - goto exit; - } - - FINN_MEMZERO(dst->classList, (dst->numClasses) * 4); - } - - // Otherwise the pointer must be provided. - else if (!dst->classList) - { - status = NV_ERR_INVALID_POINTER; - FINN_ERROR(NV_ERR_INVALID_POINTER); - goto exit; - } - - // Deserialize each 4-byte NvU32 element. - for (NvU64 j = 0; j < (dst->numClasses); ++j) - { - ((NvU32 *) NvP64_VALUE(dst->classList))[j] = (NvU32) finn_read_buffer(bp, 4 * 8); - } - } - else - { - if (!deser_up) - dst->classList = NULL; - } - -exit: - return status; -} - - -static NV_STATUS Nv0080CtrlGrGetCapsParamsSerialize(const NV0080_CTRL_GR_GET_CAPS_PARAMS *src, finn_bit_pump_for_write *bp, NvBool seri_up) -{ - // Local variables - NV_STATUS status = NV_OK; - uint64_t field_presence_mask; - - // Field bitmasks - field_presence_mask = 0x3; - - // Write field-presence indicators. - if (finn_write_buffer(bp, field_presence_mask, 64)) - { - status = NV_ERR_BUFFER_TOO_SMALL; - FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); - goto exit; - } - - // Statically sized fields - // No range check for src->capsTblSize - // Deserialize 4-byte NvU32 object. - if (finn_write_buffer(bp, src->capsTblSize, 4 * 8)) - { - status = NV_ERR_BUFFER_TOO_SMALL; - FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); - goto exit; - } - - - // Unbounded fields - // Set data-presence indicator. - if (finn_write_buffer(bp, !!(src->capsTbl), 1)) - { - status = NV_ERR_BUFFER_TOO_SMALL; - FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); - goto exit; - } - - // Skip if pointer is null. - if (src->capsTbl) - { - - // Serialize each 1-byte NvU8 element. - for (NvU64 j = 0; j < (src->capsTblSize); ++j) - { - if (finn_write_buffer(bp, ((NvU8 *) NvP64_VALUE(src->capsTbl))[j], 1 * 8)) - { - status = NV_ERR_BUFFER_TOO_SMALL; - FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); - goto exit; - } - } - - // Free memory that was allocated during downward deserialization. - if (seri_up && src->capsTbl) - FINN_FREE(NvP64_VALUE(src->capsTbl)); - } - - goto exit; // Suppress potential not-used warning -exit: - return status; -} - - -static NV_STATUS Nv0080CtrlGrGetCapsParamsDeserialize(finn_bit_pump_for_read *bp, NV0080_CTRL_GR_GET_CAPS_PARAMS *dst, NvLength dst_size, NvBool deser_up) -{ - // Local variables - NV_STATUS status = NV_OK; - - // Check that the destination struct fits within the destination buffer - if (sizeof(NV0080_CTRL_GR_GET_CAPS_PARAMS) > dst_size) - { - status = NV_ERR_BUFFER_TOO_SMALL; - FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); - goto exit; - } - - // Validate the field bitmasks, which must match the expected values for now. - if (finn_read_buffer(bp, 64) != 0x3) - { - status = NV_ERR_LIB_RM_VERSION_MISMATCH; - FINN_ERROR(NV_ERR_LIB_RM_VERSION_MISMATCH); - goto exit; - } - - // Statically sized fields - // Deserialize 4-byte NvU32 object. - dst->capsTblSize = (NvU32) finn_read_buffer(bp, 4 * 8); - // No range check for dst->capsTblSize - - - // Unbounded fields - // Skip if data is not present (null pointer). - if (finn_read_buffer(bp, 1)) - { - - // Allocate memory and set pointer when deserializing down. - // (Calling cods is expected to do so when deserializing up.) - if (!deser_up) - { - dst->capsTbl = FINN_MALLOC((dst->capsTblSize)); - if (!dst->capsTbl) - { - status = NV_ERR_NO_MEMORY; - FINN_ERROR(NV_ERR_NO_MEMORY); - goto exit; - } - - FINN_MEMZERO(dst->capsTbl, (dst->capsTblSize)); - } - - // Otherwise the pointer must be provided. - else if (!dst->capsTbl) - { - status = NV_ERR_INVALID_POINTER; - FINN_ERROR(NV_ERR_INVALID_POINTER); - goto exit; - } - - // Deserialize each 1-byte NvU8 element. - for (NvU64 j = 0; j < (dst->capsTblSize); ++j) - { - ((NvU8 *) NvP64_VALUE(dst->capsTbl))[j] = (NvU8) finn_read_buffer(bp, 1 * 8); - } - } - else - { - if (!deser_up) - dst->capsTbl = NULL; - } - -exit: - return status; -} - - -static NV_STATUS Nv0080CtrlHostGetCapsParamsSerialize(const NV0080_CTRL_HOST_GET_CAPS_PARAMS *src, finn_bit_pump_for_write *bp, NvBool seri_up) -{ - // Local variables - NV_STATUS status = NV_OK; - uint64_t field_presence_mask; - - // Field bitmasks - field_presence_mask = 0x3; - - // Write field-presence indicators. - if (finn_write_buffer(bp, field_presence_mask, 64)) - { - status = NV_ERR_BUFFER_TOO_SMALL; - FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); - goto exit; - } - - // Statically sized fields - if (src->capsTblSize > NV0080_CTRL_HOST_CAPS_TBL_SIZE) - { - status = NV_ERR_OUT_OF_RANGE; - FINN_ERROR(NV_ERR_OUT_OF_RANGE); - goto exit; - } - - // Deserialize 4-byte NvU32 object. - if (finn_write_buffer(bp, src->capsTblSize, 4 * 8)) - { - status = NV_ERR_BUFFER_TOO_SMALL; - FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); - goto exit; - } - - - // Unbounded fields - // Set data-presence indicator. - if (finn_write_buffer(bp, !!(src->capsTbl), 1)) - { - status = NV_ERR_BUFFER_TOO_SMALL; - FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); - goto exit; - } - - // Skip if pointer is null. - if (src->capsTbl) - { - - // Serialize each 1-byte NvU8 element. - for (NvU64 j = 0; j < (src->capsTblSize); ++j) - { - if (finn_write_buffer(bp, ((NvU8 *) NvP64_VALUE(src->capsTbl))[j], 1 * 8)) - { - status = NV_ERR_BUFFER_TOO_SMALL; - FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); - goto exit; - } - } - - // Free memory that was allocated during downward deserialization. - if (seri_up && src->capsTbl) - FINN_FREE(NvP64_VALUE(src->capsTbl)); - } - - goto exit; // Suppress potential not-used warning -exit: - return status; -} - - -static NV_STATUS Nv0080CtrlHostGetCapsParamsDeserialize(finn_bit_pump_for_read *bp, NV0080_CTRL_HOST_GET_CAPS_PARAMS *dst, NvLength dst_size, NvBool deser_up) -{ - // Local variables - NV_STATUS status = NV_OK; - - // Check that the destination struct fits within the destination buffer - if (sizeof(NV0080_CTRL_HOST_GET_CAPS_PARAMS) > dst_size) - { - status = NV_ERR_BUFFER_TOO_SMALL; - FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); - goto exit; - } - - // Validate the field bitmasks, which must match the expected values for now. - if (finn_read_buffer(bp, 64) != 0x3) - { - status = NV_ERR_LIB_RM_VERSION_MISMATCH; - FINN_ERROR(NV_ERR_LIB_RM_VERSION_MISMATCH); - goto exit; - } - - // Statically sized fields - // Deserialize 4-byte NvU32 object. - dst->capsTblSize = (NvU32) finn_read_buffer(bp, 4 * 8); - if (dst->capsTblSize > NV0080_CTRL_HOST_CAPS_TBL_SIZE) - { - status = NV_ERR_OUT_OF_RANGE; - FINN_ERROR(NV_ERR_OUT_OF_RANGE); - goto exit; - } - - - - // Unbounded fields - // Skip if data is not present (null pointer). - if (finn_read_buffer(bp, 1)) - { - - // Allocate memory and set pointer when deserializing down. - // (Calling cods is expected to do so when deserializing up.) - if (!deser_up) - { - dst->capsTbl = FINN_MALLOC((dst->capsTblSize)); - if (!dst->capsTbl) - { - status = NV_ERR_NO_MEMORY; - FINN_ERROR(NV_ERR_NO_MEMORY); - goto exit; - } - - FINN_MEMZERO(dst->capsTbl, (dst->capsTblSize)); - } - - // Otherwise the pointer must be provided. - else if (!dst->capsTbl) - { - status = NV_ERR_INVALID_POINTER; - FINN_ERROR(NV_ERR_INVALID_POINTER); - goto exit; - } - - // Deserialize each 1-byte NvU8 element. - for (NvU64 j = 0; j < (dst->capsTblSize); ++j) - { - ((NvU8 *) NvP64_VALUE(dst->capsTbl))[j] = (NvU8) finn_read_buffer(bp, 1 * 8); - } - } - else - { - if (!deser_up) - dst->capsTbl = NULL; - } - -exit: - return status; -} - - -static NV_STATUS Nv0080CtrlMsencGetCapsParamsSerialize(const NV0080_CTRL_MSENC_GET_CAPS_PARAMS *src, finn_bit_pump_for_write *bp, NvBool seri_up) -{ - // Local variables - NV_STATUS status = NV_OK; - uint64_t field_presence_mask; - - // Field bitmasks - field_presence_mask = 0x3; - - // Write field-presence indicators. - if (finn_write_buffer(bp, field_presence_mask, 64)) - { - status = NV_ERR_BUFFER_TOO_SMALL; - FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); - goto exit; - } - - // Statically sized fields - if (src->capsTblSize > NV0080_CTRL_MSENC_CAPS_TBL_SIZE) - { - status = NV_ERR_OUT_OF_RANGE; - FINN_ERROR(NV_ERR_OUT_OF_RANGE); - goto exit; - } - - // Deserialize 4-byte NvU32 object. - if (finn_write_buffer(bp, src->capsTblSize, 4 * 8)) - { - status = NV_ERR_BUFFER_TOO_SMALL; - FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); - goto exit; - } - - - // Unbounded fields - // Set data-presence indicator. - if (finn_write_buffer(bp, !!(src->capsTbl), 1)) - { - status = NV_ERR_BUFFER_TOO_SMALL; - FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); - goto exit; - } - - // Skip if pointer is null. - if (src->capsTbl) - { - - // Serialize each 1-byte NvU8 element. - for (NvU64 j = 0; j < (src->capsTblSize); ++j) - { - if (finn_write_buffer(bp, ((NvU8 *) NvP64_VALUE(src->capsTbl))[j], 1 * 8)) - { - status = NV_ERR_BUFFER_TOO_SMALL; - FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); - goto exit; - } - } - - // Free memory that was allocated during downward deserialization. - if (seri_up && src->capsTbl) - FINN_FREE(NvP64_VALUE(src->capsTbl)); - } - - goto exit; // Suppress potential not-used warning -exit: - return status; -} - - -static NV_STATUS Nv0080CtrlMsencGetCapsParamsDeserialize(finn_bit_pump_for_read *bp, NV0080_CTRL_MSENC_GET_CAPS_PARAMS *dst, NvLength dst_size, NvBool deser_up) -{ - // Local variables - NV_STATUS status = NV_OK; - - // Check that the destination struct fits within the destination buffer - if (sizeof(NV0080_CTRL_MSENC_GET_CAPS_PARAMS) > dst_size) - { - status = NV_ERR_BUFFER_TOO_SMALL; - FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); - goto exit; - } - - // Validate the field bitmasks, which must match the expected values for now. - if (finn_read_buffer(bp, 64) != 0x3) - { - status = NV_ERR_LIB_RM_VERSION_MISMATCH; - FINN_ERROR(NV_ERR_LIB_RM_VERSION_MISMATCH); - goto exit; - } - - // Statically sized fields - // Deserialize 4-byte NvU32 object. - dst->capsTblSize = (NvU32) finn_read_buffer(bp, 4 * 8); - if (dst->capsTblSize > NV0080_CTRL_MSENC_CAPS_TBL_SIZE) - { - status = NV_ERR_OUT_OF_RANGE; - FINN_ERROR(NV_ERR_OUT_OF_RANGE); - goto exit; - } - - - - // Unbounded fields - // Skip if data is not present (null pointer). - if (finn_read_buffer(bp, 1)) - { - - // Allocate memory and set pointer when deserializing down. - // (Calling cods is expected to do so when deserializing up.) - if (!deser_up) - { - dst->capsTbl = FINN_MALLOC((dst->capsTblSize)); - if (!dst->capsTbl) - { - status = NV_ERR_NO_MEMORY; - FINN_ERROR(NV_ERR_NO_MEMORY); - goto exit; - } - - FINN_MEMZERO(dst->capsTbl, (dst->capsTblSize)); - } - - // Otherwise the pointer must be provided. - else if (!dst->capsTbl) - { - status = NV_ERR_INVALID_POINTER; - FINN_ERROR(NV_ERR_INVALID_POINTER); - goto exit; - } - - // Deserialize each 1-byte NvU8 element. - for (NvU64 j = 0; j < (dst->capsTblSize); ++j) - { - ((NvU8 *) NvP64_VALUE(dst->capsTbl))[j] = (NvU8) finn_read_buffer(bp, 1 * 8); - } - } - else - { - if (!deser_up) - dst->capsTbl = NULL; - } - -exit: - return status; -} - - -static NV_STATUS Nv2080CtrlCeGetCapsParamsSerialize(const NV2080_CTRL_CE_GET_CAPS_PARAMS *src, finn_bit_pump_for_write *bp, NvBool seri_up) -{ - // Local variables - NV_STATUS status = NV_OK; - uint64_t field_presence_mask; - - // Field bitmasks - field_presence_mask = 0x7; - - // Write field-presence indicators. - if (finn_write_buffer(bp, field_presence_mask, 64)) - { - status = NV_ERR_BUFFER_TOO_SMALL; - FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); - goto exit; - } - - // Statically sized fields - // No range check for src->ceEngineType - // Deserialize 4-byte NvU32 object. - if (finn_write_buffer(bp, src->ceEngineType, 4 * 8)) - { - status = NV_ERR_BUFFER_TOO_SMALL; - FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); - goto exit; - } - - - if (src->capsTblSize > NV2080_CTRL_CE_CAPS_TBL_SIZE) - { - status = NV_ERR_OUT_OF_RANGE; - FINN_ERROR(NV_ERR_OUT_OF_RANGE); - goto exit; - } - - // Deserialize 4-byte NvU32 object. - if (finn_write_buffer(bp, src->capsTblSize, 4 * 8)) - { - status = NV_ERR_BUFFER_TOO_SMALL; - FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); - goto exit; - } - - - // Unbounded fields - // Set data-presence indicator. - if (finn_write_buffer(bp, !!(src->capsTbl), 1)) - { - status = NV_ERR_BUFFER_TOO_SMALL; - FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); - goto exit; - } - - // Skip if pointer is null. - if (src->capsTbl) - { - - // Serialize each 1-byte NvU8 element. - for (NvU64 j = 0; j < (src->capsTblSize); ++j) - { - if (finn_write_buffer(bp, ((NvU8 *) NvP64_VALUE(src->capsTbl))[j], 1 * 8)) - { - status = NV_ERR_BUFFER_TOO_SMALL; - FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); - goto exit; - } - } - - // Free memory that was allocated during downward deserialization. - if (seri_up && src->capsTbl) - FINN_FREE(NvP64_VALUE(src->capsTbl)); - } - - goto exit; // Suppress potential not-used warning -exit: - return status; -} - - -static NV_STATUS Nv2080CtrlCeGetCapsParamsDeserialize(finn_bit_pump_for_read *bp, NV2080_CTRL_CE_GET_CAPS_PARAMS *dst, NvLength dst_size, NvBool deser_up) -{ - // Local variables - NV_STATUS status = NV_OK; - - // Check that the destination struct fits within the destination buffer - if (sizeof(NV2080_CTRL_CE_GET_CAPS_PARAMS) > dst_size) - { - status = NV_ERR_BUFFER_TOO_SMALL; - FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); - goto exit; - } - - // Validate the field bitmasks, which must match the expected values for now. - if (finn_read_buffer(bp, 64) != 0x7) - { - status = NV_ERR_LIB_RM_VERSION_MISMATCH; - FINN_ERROR(NV_ERR_LIB_RM_VERSION_MISMATCH); - goto exit; - } - - // Statically sized fields - // Deserialize 4-byte NvU32 object. - dst->ceEngineType = (NvU32) finn_read_buffer(bp, 4 * 8); - // No range check for dst->ceEngineType - - - // Deserialize 4-byte NvU32 object. - dst->capsTblSize = (NvU32) finn_read_buffer(bp, 4 * 8); - if (dst->capsTblSize > NV2080_CTRL_CE_CAPS_TBL_SIZE) - { - status = NV_ERR_OUT_OF_RANGE; - FINN_ERROR(NV_ERR_OUT_OF_RANGE); - goto exit; - } - - - - // Unbounded fields - // Skip if data is not present (null pointer). - if (finn_read_buffer(bp, 1)) - { - - // Allocate memory and set pointer when deserializing down. - // (Calling cods is expected to do so when deserializing up.) - if (!deser_up) - { - dst->capsTbl = FINN_MALLOC((dst->capsTblSize)); - if (!dst->capsTbl) - { - status = NV_ERR_NO_MEMORY; - FINN_ERROR(NV_ERR_NO_MEMORY); - goto exit; - } - - FINN_MEMZERO(dst->capsTbl, (dst->capsTblSize)); - } - - // Otherwise the pointer must be provided. - else if (!dst->capsTbl) - { - status = NV_ERR_INVALID_POINTER; - FINN_ERROR(NV_ERR_INVALID_POINTER); - goto exit; - } - - // Deserialize each 1-byte NvU8 element. - for (NvU64 j = 0; j < (dst->capsTblSize); ++j) - { - ((NvU8 *) NvP64_VALUE(dst->capsTbl))[j] = (NvU8) finn_read_buffer(bp, 1 * 8); - } - } - else - { - if (!deser_up) - dst->capsTbl = NULL; - } - -exit: - return status; -} - - -static NV_STATUS Nv2080CtrlGpuGetEnginesParamsSerialize(const NV2080_CTRL_GPU_GET_ENGINES_PARAMS *src, finn_bit_pump_for_write *bp, NvBool seri_up) -{ - // Local variables - NV_STATUS status = NV_OK; - uint64_t field_presence_mask; - - // Field bitmasks - field_presence_mask = 0x3; - - // Write field-presence indicators. - if (finn_write_buffer(bp, field_presence_mask, 64)) - { - status = NV_ERR_BUFFER_TOO_SMALL; - FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); - goto exit; - } - - // Statically sized fields - // No range check for src->engineCount - // Deserialize 4-byte NvU32 object. - if (finn_write_buffer(bp, src->engineCount, 4 * 8)) - { - status = NV_ERR_BUFFER_TOO_SMALL; - FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); - goto exit; - } - - - // Unbounded fields - // Set data-presence indicator. - if (finn_write_buffer(bp, !!(src->engineList), 1)) - { - status = NV_ERR_BUFFER_TOO_SMALL; - FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); - goto exit; - } - - // Skip if pointer is null. - if (src->engineList) - { - - // Serialize each 4-byte NvU32 element. - for (NvU64 j = 0; j < (src->engineCount); ++j) - { - if (finn_write_buffer(bp, ((NvU32 *) NvP64_VALUE(src->engineList))[j], 4 * 8)) - { - status = NV_ERR_BUFFER_TOO_SMALL; - FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); - goto exit; - } - } - - // Free memory that was allocated during downward deserialization. - if (seri_up && src->engineList) - FINN_FREE(NvP64_VALUE(src->engineList)); - } - - goto exit; // Suppress potential not-used warning -exit: - return status; -} - - -static NV_STATUS Nv2080CtrlGpuGetEnginesParamsDeserialize(finn_bit_pump_for_read *bp, NV2080_CTRL_GPU_GET_ENGINES_PARAMS *dst, NvLength dst_size, NvBool deser_up) -{ - // Local variables - NV_STATUS status = NV_OK; - - // Check that the destination struct fits within the destination buffer - if (sizeof(NV2080_CTRL_GPU_GET_ENGINES_PARAMS) > dst_size) - { - status = NV_ERR_BUFFER_TOO_SMALL; - FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); - goto exit; - } - - // Validate the field bitmasks, which must match the expected values for now. - if (finn_read_buffer(bp, 64) != 0x3) - { - status = NV_ERR_LIB_RM_VERSION_MISMATCH; - FINN_ERROR(NV_ERR_LIB_RM_VERSION_MISMATCH); - goto exit; - } - - // Statically sized fields - // Deserialize 4-byte NvU32 object. - dst->engineCount = (NvU32) finn_read_buffer(bp, 4 * 8); - // No range check for dst->engineCount - - - // Unbounded fields - // Skip if data is not present (null pointer). - if (finn_read_buffer(bp, 1)) - { - - // Allocate memory and set pointer when deserializing down. - // (Calling cods is expected to do so when deserializing up.) - if (!deser_up) - { - dst->engineList = FINN_MALLOC((dst->engineCount) * 4); - if (!dst->engineList) - { - status = NV_ERR_NO_MEMORY; - FINN_ERROR(NV_ERR_NO_MEMORY); - goto exit; - } - - FINN_MEMZERO(dst->engineList, (dst->engineCount) * 4); - } - - // Otherwise the pointer must be provided. - else if (!dst->engineList) - { - status = NV_ERR_INVALID_POINTER; - FINN_ERROR(NV_ERR_INVALID_POINTER); - goto exit; - } - - // Deserialize each 4-byte NvU32 element. - for (NvU64 j = 0; j < (dst->engineCount); ++j) - { - ((NvU32 *) NvP64_VALUE(dst->engineList))[j] = (NvU32) finn_read_buffer(bp, 4 * 8); - } - } - else - { - if (!deser_up) - dst->engineList = NULL; - } - -exit: - return status; -} - - -static NV_STATUS Nv2080CtrlGpuGetEngineClasslistParamsSerialize(const NV2080_CTRL_GPU_GET_ENGINE_CLASSLIST_PARAMS *src, finn_bit_pump_for_write *bp, NvBool seri_up) -{ - // Local variables - NV_STATUS status = NV_OK; - uint64_t field_presence_mask; - - // Field bitmasks - field_presence_mask = 0x7; - - // Write field-presence indicators. - if (finn_write_buffer(bp, field_presence_mask, 64)) - { - status = NV_ERR_BUFFER_TOO_SMALL; - FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); - goto exit; - } - - // Statically sized fields - // No range check for src->engineType - // Deserialize 4-byte NvU32 object. - if (finn_write_buffer(bp, src->engineType, 4 * 8)) - { - status = NV_ERR_BUFFER_TOO_SMALL; - FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); - goto exit; - } - - - // No range check for src->numClasses - // Deserialize 4-byte NvU32 object. - if (finn_write_buffer(bp, src->numClasses, 4 * 8)) - { - status = NV_ERR_BUFFER_TOO_SMALL; - FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); - goto exit; - } - - - // Unbounded fields - // Set data-presence indicator. - if (finn_write_buffer(bp, !!(src->classList), 1)) - { - status = NV_ERR_BUFFER_TOO_SMALL; - FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); - goto exit; - } - - // Skip if pointer is null. - if (src->classList) - { - - // Serialize each 4-byte NvU32 element. - for (NvU64 j = 0; j < (src->numClasses); ++j) - { - if (finn_write_buffer(bp, ((NvU32 *) NvP64_VALUE(src->classList))[j], 4 * 8)) - { - status = NV_ERR_BUFFER_TOO_SMALL; - FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); - goto exit; - } - } - - // Free memory that was allocated during downward deserialization. - if (seri_up && src->classList) - FINN_FREE(NvP64_VALUE(src->classList)); - } - - goto exit; // Suppress potential not-used warning -exit: - return status; -} - - -static NV_STATUS Nv2080CtrlGpuGetEngineClasslistParamsDeserialize(finn_bit_pump_for_read *bp, NV2080_CTRL_GPU_GET_ENGINE_CLASSLIST_PARAMS *dst, NvLength dst_size, NvBool deser_up) -{ - // Local variables - NV_STATUS status = NV_OK; - - // Check that the destination struct fits within the destination buffer - if (sizeof(NV2080_CTRL_GPU_GET_ENGINE_CLASSLIST_PARAMS) > dst_size) - { - status = NV_ERR_BUFFER_TOO_SMALL; - FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); - goto exit; - } - - // Validate the field bitmasks, which must match the expected values for now. - if (finn_read_buffer(bp, 64) != 0x7) - { - status = NV_ERR_LIB_RM_VERSION_MISMATCH; - FINN_ERROR(NV_ERR_LIB_RM_VERSION_MISMATCH); - goto exit; - } - - // Statically sized fields - // Deserialize 4-byte NvU32 object. - dst->engineType = (NvU32) finn_read_buffer(bp, 4 * 8); - // No range check for dst->engineType - - - // Deserialize 4-byte NvU32 object. - dst->numClasses = (NvU32) finn_read_buffer(bp, 4 * 8); - // No range check for dst->numClasses - - - // Unbounded fields - // Skip if data is not present (null pointer). - if (finn_read_buffer(bp, 1)) - { - - // Allocate memory and set pointer when deserializing down. - // (Calling cods is expected to do so when deserializing up.) - if (!deser_up) - { - dst->classList = FINN_MALLOC((dst->numClasses) * 4); - if (!dst->classList) - { - status = NV_ERR_NO_MEMORY; - FINN_ERROR(NV_ERR_NO_MEMORY); - goto exit; - } - - FINN_MEMZERO(dst->classList, (dst->numClasses) * 4); - } - - // Otherwise the pointer must be provided. - else if (!dst->classList) - { - status = NV_ERR_INVALID_POINTER; - FINN_ERROR(NV_ERR_INVALID_POINTER); - goto exit; - } - - // Deserialize each 4-byte NvU32 element. - for (NvU64 j = 0; j < (dst->numClasses); ++j) - { - ((NvU32 *) NvP64_VALUE(dst->classList))[j] = (NvU32) finn_read_buffer(bp, 4 * 8); - } - } - else - { - if (!deser_up) - dst->classList = NULL; - } - -exit: - return status; -} - - -static NV_STATUS Nv2080CtrlGpumonSamplesSerialize(const NV2080_CTRL_GPUMON_SAMPLES *src, finn_bit_pump_for_write *bp, NvBool seri_up) -{ - // Local variables - NV_STATUS status = NV_OK; - uint64_t field_presence_mask; - - // Field bitmasks - field_presence_mask = 0x1f; - - // Write field-presence indicators. - if (finn_write_buffer(bp, field_presence_mask, 64)) - { - status = NV_ERR_BUFFER_TOO_SMALL; - FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); - goto exit; - } - - // Statically sized fields - // No range check for src->bufSize - // Deserialize 4-byte NvU32 object. - if (finn_write_buffer(bp, src->bufSize, 4 * 8)) - { - status = NV_ERR_BUFFER_TOO_SMALL; - FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); - goto exit; - } - - - // No range check for src->count - // Deserialize 4-byte NvU32 object. - if (finn_write_buffer(bp, src->count, 4 * 8)) - { - status = NV_ERR_BUFFER_TOO_SMALL; - FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); - goto exit; - } - - - // No range check for src->tracker - // Deserialize 4-byte NvU32 object. - if (finn_write_buffer(bp, src->tracker, 4 * 8)) - { - status = NV_ERR_BUFFER_TOO_SMALL; - FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); - goto exit; - } - - - // No range check for src->type - // Deserialize 1-byte NvU8 object. - if (finn_write_buffer(bp, src->type, 1 * 8)) - { - status = NV_ERR_BUFFER_TOO_SMALL; - FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); - goto exit; - } - - - // Unbounded fields - // Set data-presence indicator. - if (finn_write_buffer(bp, !!(src->pSamples), 1)) - { - status = NV_ERR_BUFFER_TOO_SMALL; - FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); - goto exit; - } - - // Skip if pointer is null. - if (src->pSamples) - { - - // Serialize each 1-byte NvU8 element. - for (NvU64 j = 0; j < (src->bufSize); ++j) - { - if (finn_write_buffer(bp, ((NvU8 *) NvP64_VALUE(src->pSamples))[j], 1 * 8)) - { - status = NV_ERR_BUFFER_TOO_SMALL; - FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); - goto exit; - } - } - - // Free memory that was allocated during downward deserialization. - if (seri_up && src->pSamples) - FINN_FREE(NvP64_VALUE(src->pSamples)); - } - - goto exit; // Suppress potential not-used warning -exit: - return status; -} - - -static NV_STATUS Nv2080CtrlGpumonSamplesDeserialize(finn_bit_pump_for_read *bp, NV2080_CTRL_GPUMON_SAMPLES *dst, NvLength dst_size, NvBool deser_up) -{ - // Local variables - NV_STATUS status = NV_OK; - - // Check that the destination struct fits within the destination buffer - if (sizeof(NV2080_CTRL_GPUMON_SAMPLES) > dst_size) - { - status = NV_ERR_BUFFER_TOO_SMALL; - FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); - goto exit; - } - - // Validate the field bitmasks, which must match the expected values for now. - if (finn_read_buffer(bp, 64) != 0x1f) - { - status = NV_ERR_LIB_RM_VERSION_MISMATCH; - FINN_ERROR(NV_ERR_LIB_RM_VERSION_MISMATCH); - goto exit; - } - - // Statically sized fields - // Deserialize 4-byte NvU32 object. - dst->bufSize = (NvU32) finn_read_buffer(bp, 4 * 8); - // No range check for dst->bufSize - - - // Deserialize 4-byte NvU32 object. - dst->count = (NvU32) finn_read_buffer(bp, 4 * 8); - // No range check for dst->count - - - // Deserialize 4-byte NvU32 object. - dst->tracker = (NvU32) finn_read_buffer(bp, 4 * 8); - // No range check for dst->tracker - - - // Deserialize 1-byte NvU8 object. - dst->type = (NvU8) finn_read_buffer(bp, 1 * 8); - // No range check for dst->type - - - // Unbounded fields - // Skip if data is not present (null pointer). - if (finn_read_buffer(bp, 1)) - { - - // Allocate memory and set pointer when deserializing down. - // (Calling cods is expected to do so when deserializing up.) - if (!deser_up) - { - dst->pSamples = FINN_MALLOC((dst->bufSize)); - if (!dst->pSamples) - { - status = NV_ERR_NO_MEMORY; - FINN_ERROR(NV_ERR_NO_MEMORY); - goto exit; - } - - FINN_MEMZERO(dst->pSamples, (dst->bufSize)); - } - - // Otherwise the pointer must be provided. - else if (!dst->pSamples) - { - status = NV_ERR_INVALID_POINTER; - FINN_ERROR(NV_ERR_INVALID_POINTER); - goto exit; - } - - // Deserialize each 1-byte NvU8 element. - for (NvU64 j = 0; j < (dst->bufSize); ++j) - { - ((NvU8 *) NvP64_VALUE(dst->pSamples))[j] = (NvU8) finn_read_buffer(bp, 1 * 8); - } - } - else - { - if (!deser_up) - dst->pSamples = NULL; - } - -exit: - return status; -} - - -static NV_STATUS Nv2080CtrlI2cAccessParamsSerialize(const NV2080_CTRL_I2C_ACCESS_PARAMS *src, finn_bit_pump_for_write *bp, NvBool seri_up) -{ - // Local variables - NV_STATUS status = NV_OK; - uint64_t field_presence_mask; - - // Field bitmasks - field_presence_mask = 0x1ff; - - // Write field-presence indicators. - if (finn_write_buffer(bp, field_presence_mask, 64)) - { - status = NV_ERR_BUFFER_TOO_SMALL; - FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); - goto exit; - } - - // Statically sized fields - // No range check for src->token - // Deserialize 4-byte NvU32 object. - if (finn_write_buffer(bp, src->token, 4 * 8)) - { - status = NV_ERR_BUFFER_TOO_SMALL; - FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); - goto exit; - } - - - // No range check for src->cmd - // Deserialize 4-byte NvU32 object. - if (finn_write_buffer(bp, src->cmd, 4 * 8)) - { - status = NV_ERR_BUFFER_TOO_SMALL; - FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); - goto exit; - } - - - // No range check for src->port - // Deserialize 4-byte NvU32 object. - if (finn_write_buffer(bp, src->port, 4 * 8)) - { - status = NV_ERR_BUFFER_TOO_SMALL; - FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); - goto exit; - } - - - // No range check for src->flags - // Deserialize 4-byte NvU32 object. - if (finn_write_buffer(bp, src->flags, 4 * 8)) - { - status = NV_ERR_BUFFER_TOO_SMALL; - FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); - goto exit; - } - - - // No range check for src->status - // Deserialize 4-byte NvU32 object. - if (finn_write_buffer(bp, src->status, 4 * 8)) - { - status = NV_ERR_BUFFER_TOO_SMALL; - FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); - goto exit; - } - - - if (src->dataBuffSize > NV2080_CTRL_I2C_MAX_ENTRIES) - { - status = NV_ERR_OUT_OF_RANGE; - FINN_ERROR(NV_ERR_OUT_OF_RANGE); - goto exit; - } - - // Deserialize 4-byte NvU32 object. - if (finn_write_buffer(bp, src->dataBuffSize, 4 * 8)) - { - status = NV_ERR_BUFFER_TOO_SMALL; - FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); - goto exit; - } - - - // No range check for src->speed - // Deserialize 4-byte NvU32 object. - if (finn_write_buffer(bp, src->speed, 4 * 8)) - { - status = NV_ERR_BUFFER_TOO_SMALL; - FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); - goto exit; - } - - - // No range check for src->encrClientID - // Deserialize 4-byte NvU32 object. - if (finn_write_buffer(bp, src->encrClientID, 4 * 8)) - { - status = NV_ERR_BUFFER_TOO_SMALL; - FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); - goto exit; - } - - - // Unbounded fields - // Set data-presence indicator. - if (finn_write_buffer(bp, !!(src->data), 1)) - { - status = NV_ERR_BUFFER_TOO_SMALL; - FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); - goto exit; - } - - // Skip if pointer is null. - if (src->data) - { - - // Serialize each 1-byte NvU8 element. - for (NvU64 j = 0; j < (src->dataBuffSize); ++j) - { - if (finn_write_buffer(bp, ((NvU8 *) NvP64_VALUE(src->data))[j], 1 * 8)) - { - status = NV_ERR_BUFFER_TOO_SMALL; - FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); - goto exit; - } - } - - // Free memory that was allocated during downward deserialization. - if (seri_up && src->data) - FINN_FREE(NvP64_VALUE(src->data)); - } - - goto exit; // Suppress potential not-used warning -exit: - return status; -} - - -static NV_STATUS Nv2080CtrlI2cAccessParamsDeserialize(finn_bit_pump_for_read *bp, NV2080_CTRL_I2C_ACCESS_PARAMS *dst, NvLength dst_size, NvBool deser_up) -{ - // Local variables - NV_STATUS status = NV_OK; - - // Check that the destination struct fits within the destination buffer - if (sizeof(NV2080_CTRL_I2C_ACCESS_PARAMS) > dst_size) - { - status = NV_ERR_BUFFER_TOO_SMALL; - FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); - goto exit; - } - - // Validate the field bitmasks, which must match the expected values for now. - if (finn_read_buffer(bp, 64) != 0x1ff) - { - status = NV_ERR_LIB_RM_VERSION_MISMATCH; - FINN_ERROR(NV_ERR_LIB_RM_VERSION_MISMATCH); - goto exit; - } - - // Statically sized fields - // Deserialize 4-byte NvU32 object. - dst->token = (NvU32) finn_read_buffer(bp, 4 * 8); - // No range check for dst->token - - - // Deserialize 4-byte NvU32 object. - dst->cmd = (NvU32) finn_read_buffer(bp, 4 * 8); - // No range check for dst->cmd - - - // Deserialize 4-byte NvU32 object. - dst->port = (NvU32) finn_read_buffer(bp, 4 * 8); - // No range check for dst->port - - - // Deserialize 4-byte NvU32 object. - dst->flags = (NvU32) finn_read_buffer(bp, 4 * 8); - // No range check for dst->flags - - - // Deserialize 4-byte NvU32 object. - dst->status = (NvU32) finn_read_buffer(bp, 4 * 8); - // No range check for dst->status - - - // Deserialize 4-byte NvU32 object. - dst->dataBuffSize = (NvU32) finn_read_buffer(bp, 4 * 8); - if (dst->dataBuffSize > NV2080_CTRL_I2C_MAX_ENTRIES) - { - status = NV_ERR_OUT_OF_RANGE; - FINN_ERROR(NV_ERR_OUT_OF_RANGE); - goto exit; - } - - - - // Deserialize 4-byte NvU32 object. - dst->speed = (NvU32) finn_read_buffer(bp, 4 * 8); - // No range check for dst->speed - - - // Deserialize 4-byte NvU32 object. - dst->encrClientID = (NvU32) finn_read_buffer(bp, 4 * 8); - // No range check for dst->encrClientID - - - // Unbounded fields - // Skip if data is not present (null pointer). - if (finn_read_buffer(bp, 1)) - { - - // Allocate memory and set pointer when deserializing down. - // (Calling cods is expected to do so when deserializing up.) - if (!deser_up) - { - dst->data = FINN_MALLOC((dst->dataBuffSize)); - if (!dst->data) - { - status = NV_ERR_NO_MEMORY; - FINN_ERROR(NV_ERR_NO_MEMORY); - goto exit; - } - - FINN_MEMZERO(dst->data, (dst->dataBuffSize)); - } - - // Otherwise the pointer must be provided. - else if (!dst->data) - { - status = NV_ERR_INVALID_POINTER; - FINN_ERROR(NV_ERR_INVALID_POINTER); - goto exit; - } - - // Deserialize each 1-byte NvU8 element. - for (NvU64 j = 0; j < (dst->dataBuffSize); ++j) - { - ((NvU8 *) NvP64_VALUE(dst->data))[j] = (NvU8) finn_read_buffer(bp, 1 * 8); - } - } - else - { - if (!deser_up) - dst->data = NULL; - } - -exit: - return status; -} - - -static NV_STATUS Nv2080CtrlNvdGetDumpParamsSerialize(const NV2080_CTRL_NVD_GET_DUMP_PARAMS *src, finn_bit_pump_for_write *bp, NvBool seri_up) -{ - // Local variables - NV_STATUS status = NV_OK; - uint64_t field_presence_mask; - - // Field bitmasks - field_presence_mask = 0x7; - - // Write field-presence indicators. - if (finn_write_buffer(bp, field_presence_mask, 64)) - { - status = NV_ERR_BUFFER_TOO_SMALL; - FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); - goto exit; - } - - // Statically sized fields - // No range check for src->component - // Deserialize 4-byte NvU32 object. - if (finn_write_buffer(bp, src->component, 4 * 8)) - { - status = NV_ERR_BUFFER_TOO_SMALL; - FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); - goto exit; - } - - - // No range check for src->size - // Deserialize 4-byte NvU32 object. - if (finn_write_buffer(bp, src->size, 4 * 8)) - { - status = NV_ERR_BUFFER_TOO_SMALL; - FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); - goto exit; - } - - - // Unbounded fields - // Set data-presence indicator. - if (finn_write_buffer(bp, !!(src->pBuffer), 1)) - { - status = NV_ERR_BUFFER_TOO_SMALL; - FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); - goto exit; - } - - // Skip if pointer is null. - if (src->pBuffer) - { - - // Serialize each 1-byte NvU8 element. - for (NvU64 j = 0; j < (src->size); ++j) - { - if (finn_write_buffer(bp, ((NvU8 *) NvP64_VALUE(src->pBuffer))[j], 1 * 8)) - { - status = NV_ERR_BUFFER_TOO_SMALL; - FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); - goto exit; - } - } - - // Free memory that was allocated during downward deserialization. - if (seri_up && src->pBuffer) - FINN_FREE(NvP64_VALUE(src->pBuffer)); - } - - goto exit; // Suppress potential not-used warning -exit: - return status; -} - - -static NV_STATUS Nv2080CtrlNvdGetDumpParamsDeserialize(finn_bit_pump_for_read *bp, NV2080_CTRL_NVD_GET_DUMP_PARAMS *dst, NvLength dst_size, NvBool deser_up) -{ - // Local variables - NV_STATUS status = NV_OK; - - // Check that the destination struct fits within the destination buffer - if (sizeof(NV2080_CTRL_NVD_GET_DUMP_PARAMS) > dst_size) - { - status = NV_ERR_BUFFER_TOO_SMALL; - FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); - goto exit; - } - - // Validate the field bitmasks, which must match the expected values for now. - if (finn_read_buffer(bp, 64) != 0x7) - { - status = NV_ERR_LIB_RM_VERSION_MISMATCH; - FINN_ERROR(NV_ERR_LIB_RM_VERSION_MISMATCH); - goto exit; - } - - // Statically sized fields - // Deserialize 4-byte NvU32 object. - dst->component = (NvU32) finn_read_buffer(bp, 4 * 8); - // No range check for dst->component - - - // Deserialize 4-byte NvU32 object. - dst->size = (NvU32) finn_read_buffer(bp, 4 * 8); - // No range check for dst->size - - - // Unbounded fields - // Skip if data is not present (null pointer). - if (finn_read_buffer(bp, 1)) - { - - // Allocate memory and set pointer when deserializing down. - // (Calling cods is expected to do so when deserializing up.) - if (!deser_up) - { - dst->pBuffer = FINN_MALLOC((dst->size)); - if (!dst->pBuffer) - { - status = NV_ERR_NO_MEMORY; - FINN_ERROR(NV_ERR_NO_MEMORY); - goto exit; - } - - FINN_MEMZERO(dst->pBuffer, (dst->size)); - } - - // Otherwise the pointer must be provided. - else if (!dst->pBuffer) - { - status = NV_ERR_INVALID_POINTER; - FINN_ERROR(NV_ERR_INVALID_POINTER); - goto exit; - } - - // Deserialize each 1-byte NvU8 element. - for (NvU64 j = 0; j < (dst->size); ++j) - { - ((NvU8 *) NvP64_VALUE(dst->pBuffer))[j] = (NvU8) finn_read_buffer(bp, 1 * 8); - } - } - else - { - if (!deser_up) - dst->pBuffer = NULL; - } - -exit: - return status; -} - - -static NV_STATUS Nv2080CtrlRcReadVirtualMemParamsSerialize(const NV2080_CTRL_RC_READ_VIRTUAL_MEM_PARAMS *src, finn_bit_pump_for_write *bp, NvBool seri_up) -{ - // Local variables - NV_STATUS status = NV_OK; - uint64_t field_presence_mask; - - // Field bitmasks - field_presence_mask = 0xf; - - // Write field-presence indicators. - if (finn_write_buffer(bp, field_presence_mask, 64)) - { - status = NV_ERR_BUFFER_TOO_SMALL; - FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); - goto exit; - } - - // Statically sized fields - // No range check for src->virtAddress - // Deserialize 8-byte NvU64 object. - if (finn_write_buffer(bp, src->virtAddress, 8 * 8)) - { - status = NV_ERR_BUFFER_TOO_SMALL; - FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); - goto exit; - } - - - // No range check for src->hChannel - // Deserialize 4-byte NvHandle object. - if (finn_write_buffer(bp, src->hChannel, 4 * 8)) - { - status = NV_ERR_BUFFER_TOO_SMALL; - FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); - goto exit; - } - - - // No range check for src->bufferSize - // Deserialize 4-byte NvU32 object. - if (finn_write_buffer(bp, src->bufferSize, 4 * 8)) - { - status = NV_ERR_BUFFER_TOO_SMALL; - FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); - goto exit; - } - - - // Unbounded fields - // Set data-presence indicator. - if (finn_write_buffer(bp, !!(src->bufferPtr), 1)) - { - status = NV_ERR_BUFFER_TOO_SMALL; - FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); - goto exit; - } - - // Skip if pointer is null. - if (src->bufferPtr) - { - - // Serialize each 1-byte NvU8 element. - for (NvU64 j = 0; j < (src->bufferSize); ++j) - { - if (finn_write_buffer(bp, ((NvU8 *) NvP64_VALUE(src->bufferPtr))[j], 1 * 8)) - { - status = NV_ERR_BUFFER_TOO_SMALL; - FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); - goto exit; - } - } - - // Free memory that was allocated during downward deserialization. - if (seri_up && src->bufferPtr) - FINN_FREE(NvP64_VALUE(src->bufferPtr)); - } - - goto exit; // Suppress potential not-used warning -exit: - return status; -} - - -static NV_STATUS Nv2080CtrlRcReadVirtualMemParamsDeserialize(finn_bit_pump_for_read *bp, NV2080_CTRL_RC_READ_VIRTUAL_MEM_PARAMS *dst, NvLength dst_size, NvBool deser_up) -{ - // Local variables - NV_STATUS status = NV_OK; - - // Check that the destination struct fits within the destination buffer - if (sizeof(NV2080_CTRL_RC_READ_VIRTUAL_MEM_PARAMS) > dst_size) - { - status = NV_ERR_BUFFER_TOO_SMALL; - FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); - goto exit; - } - - // Validate the field bitmasks, which must match the expected values for now. - if (finn_read_buffer(bp, 64) != 0xf) - { - status = NV_ERR_LIB_RM_VERSION_MISMATCH; - FINN_ERROR(NV_ERR_LIB_RM_VERSION_MISMATCH); - goto exit; - } - - // Statically sized fields - // Deserialize 8-byte NvU64 object. - dst->virtAddress = (NvU64) finn_read_buffer(bp, 8 * 8); - // No range check for dst->virtAddress - - - // Deserialize 4-byte NvHandle object. - dst->hChannel = (NvHandle) finn_read_buffer(bp, 4 * 8); - // No range check for dst->hChannel - - - // Deserialize 4-byte NvU32 object. - dst->bufferSize = (NvU32) finn_read_buffer(bp, 4 * 8); - // No range check for dst->bufferSize - - - // Unbounded fields - // Skip if data is not present (null pointer). - if (finn_read_buffer(bp, 1)) - { - - // Allocate memory and set pointer when deserializing down. - // (Calling cods is expected to do so when deserializing up.) - if (!deser_up) - { - dst->bufferPtr = FINN_MALLOC((dst->bufferSize)); - if (!dst->bufferPtr) - { - status = NV_ERR_NO_MEMORY; - FINN_ERROR(NV_ERR_NO_MEMORY); - goto exit; - } - - FINN_MEMZERO(dst->bufferPtr, (dst->bufferSize)); - } - - // Otherwise the pointer must be provided. - else if (!dst->bufferPtr) - { - status = NV_ERR_INVALID_POINTER; - FINN_ERROR(NV_ERR_INVALID_POINTER); - goto exit; - } - - // Deserialize each 1-byte NvU8 element. - for (NvU64 j = 0; j < (dst->bufferSize); ++j) - { - ((NvU8 *) NvP64_VALUE(dst->bufferPtr))[j] = (NvU8) finn_read_buffer(bp, 1 * 8); - } - } - else - { - if (!deser_up) - dst->bufferPtr = NULL; - } - -exit: - return status; -} - - -static NV_STATUS Nv402cCtrlI2cIndexedParamsSerialize(const NV402C_CTRL_I2C_INDEXED_PARAMS *src, finn_bit_pump_for_write *bp, NvBool seri_up) -{ - // Local variables - NV_STATUS status = NV_OK; - uint64_t field_presence_mask; - - // Field bitmasks - field_presence_mask = 0xff; - - // Write field-presence indicators. - if (finn_write_buffer(bp, field_presence_mask, 64)) - { - status = NV_ERR_BUFFER_TOO_SMALL; - FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); - goto exit; - } - - // Statically sized fields - // No range check for src->flags - // Deserialize 4-byte NvU32 object. - if (finn_write_buffer(bp, src->flags, 4 * 8)) - { - status = NV_ERR_BUFFER_TOO_SMALL; - FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); - goto exit; - } - - - if (src->indexLength > NV402C_CTRL_I2C_INDEX_LENGTH_MAX) - { - status = NV_ERR_OUT_OF_RANGE; - FINN_ERROR(NV_ERR_OUT_OF_RANGE); - goto exit; - } - - // Deserialize 4-byte NvU32 object. - if (finn_write_buffer(bp, src->indexLength, 4 * 8)) - { - status = NV_ERR_BUFFER_TOO_SMALL; - FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); - goto exit; - } - - - // No range check for src->messageLength - // Deserialize 4-byte NvU32 object. - if (finn_write_buffer(bp, src->messageLength, 4 * 8)) - { - status = NV_ERR_BUFFER_TOO_SMALL; - FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); - goto exit; - } - - - // No range check for src->address - // Deserialize 2-byte NvU16 object. - if (finn_write_buffer(bp, src->address, 2 * 8)) - { - status = NV_ERR_BUFFER_TOO_SMALL; - FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); - goto exit; - } - - - // No range check for src->portId - // Deserialize 1-byte NvU8 object. - if (finn_write_buffer(bp, src->portId, 1 * 8)) - { - status = NV_ERR_BUFFER_TOO_SMALL; - FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); - goto exit; - } - - - // No range check for src->bIsWrite - // Deserialize 1-byte NvU8 object. - if (finn_write_buffer(bp, src->bIsWrite, 1 * 8)) - { - status = NV_ERR_BUFFER_TOO_SMALL; - FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); - goto exit; - } - - - for (NvU64 i = 0; i < (NV402C_CTRL_I2C_INDEX_LENGTH_MAX); ++i) - { - // No range check for src->index[i] - // Deserialize 1-byte NvU8 object. - if (finn_write_buffer(bp, src->index[i], 1 * 8)) - { - status = NV_ERR_BUFFER_TOO_SMALL; - FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); - goto exit; - } - } - - - // Unbounded fields - // Set data-presence indicator. - if (finn_write_buffer(bp, !!(src->pMessage), 1)) - { - status = NV_ERR_BUFFER_TOO_SMALL; - FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); - goto exit; - } - - // Skip if pointer is null. - if (src->pMessage) - { - - // Serialize each 1-byte NvU8 element. - for (NvU64 j = 0; j < (src->messageLength); ++j) - { - if (finn_write_buffer(bp, ((NvU8 *) NvP64_VALUE(src->pMessage))[j], 1 * 8)) - { - status = NV_ERR_BUFFER_TOO_SMALL; - FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); - goto exit; - } - } - - // Free memory that was allocated during downward deserialization. - if (seri_up && src->pMessage) - FINN_FREE(NvP64_VALUE(src->pMessage)); - } - - goto exit; // Suppress potential not-used warning -exit: - return status; -} - - -static NV_STATUS Nv402cCtrlI2cIndexedParamsDeserialize(finn_bit_pump_for_read *bp, NV402C_CTRL_I2C_INDEXED_PARAMS *dst, NvLength dst_size, NvBool deser_up) -{ - // Local variables - NV_STATUS status = NV_OK; - - // Check that the destination struct fits within the destination buffer - if (sizeof(NV402C_CTRL_I2C_INDEXED_PARAMS) > dst_size) - { - status = NV_ERR_BUFFER_TOO_SMALL; - FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); - goto exit; - } - - // Validate the field bitmasks, which must match the expected values for now. - if (finn_read_buffer(bp, 64) != 0xff) - { - status = NV_ERR_LIB_RM_VERSION_MISMATCH; - FINN_ERROR(NV_ERR_LIB_RM_VERSION_MISMATCH); - goto exit; - } - - // Statically sized fields - // Deserialize 4-byte NvU32 object. - dst->flags = (NvU32) finn_read_buffer(bp, 4 * 8); - // No range check for dst->flags - - - // Deserialize 4-byte NvU32 object. - dst->indexLength = (NvU32) finn_read_buffer(bp, 4 * 8); - if (dst->indexLength > NV402C_CTRL_I2C_INDEX_LENGTH_MAX) - { - status = NV_ERR_OUT_OF_RANGE; - FINN_ERROR(NV_ERR_OUT_OF_RANGE); - goto exit; - } - - - - // Deserialize 4-byte NvU32 object. - dst->messageLength = (NvU32) finn_read_buffer(bp, 4 * 8); - // No range check for dst->messageLength - - - // Deserialize 2-byte NvU16 object. - dst->address = (NvU16) finn_read_buffer(bp, 2 * 8); - // No range check for dst->address - - - // Deserialize 1-byte NvU8 object. - dst->portId = (NvU8) finn_read_buffer(bp, 1 * 8); - // No range check for dst->portId - - - // Deserialize 1-byte NvU8 object. - dst->bIsWrite = (NvU8) finn_read_buffer(bp, 1 * 8); - // No range check for dst->bIsWrite - - - for (NvU64 i = 0; i < (NV402C_CTRL_I2C_INDEX_LENGTH_MAX); ++i) - { - // Deserialize 1-byte NvU8 object. - dst->index[i] = (NvU8) finn_read_buffer(bp, 1 * 8); - // No range check for dst->index[i] - } - - - // Unbounded fields - // Skip if data is not present (null pointer). - if (finn_read_buffer(bp, 1)) - { - - // Allocate memory and set pointer when deserializing down. - // (Calling cods is expected to do so when deserializing up.) - if (!deser_up) - { - dst->pMessage = FINN_MALLOC((dst->messageLength)); - if (!dst->pMessage) - { - status = NV_ERR_NO_MEMORY; - FINN_ERROR(NV_ERR_NO_MEMORY); - goto exit; - } - - FINN_MEMZERO(dst->pMessage, (dst->messageLength)); - } - - // Otherwise the pointer must be provided. - else if (!dst->pMessage) - { - status = NV_ERR_INVALID_POINTER; - FINN_ERROR(NV_ERR_INVALID_POINTER); - goto exit; - } - - // Deserialize each 1-byte NvU8 element. - for (NvU64 j = 0; j < (dst->messageLength); ++j) - { - ((NvU8 *) NvP64_VALUE(dst->pMessage))[j] = (NvU8) finn_read_buffer(bp, 1 * 8); - } - } - else - { - if (!deser_up) - dst->pMessage = NULL; - } - -exit: - return status; -} - - -static NV_STATUS Nv402cCtrlI2cTransactionTypeCheckEnum(NV402C_CTRL_I2C_TRANSACTION_TYPE id) -{ - switch (id) - { - case NV402C_CTRL_I2C_TRANSACTION_TYPE_SMBUS_QUICK_RW: - case NV402C_CTRL_I2C_TRANSACTION_TYPE_I2C_BYTE_RW: - case NV402C_CTRL_I2C_TRANSACTION_TYPE_I2C_BLOCK_RW: - case NV402C_CTRL_I2C_TRANSACTION_TYPE_I2C_BUFFER_RW: - case NV402C_CTRL_I2C_TRANSACTION_TYPE_SMBUS_BYTE_RW: - case NV402C_CTRL_I2C_TRANSACTION_TYPE_SMBUS_WORD_RW: - case NV402C_CTRL_I2C_TRANSACTION_TYPE_SMBUS_BLOCK_RW: - case NV402C_CTRL_I2C_TRANSACTION_TYPE_SMBUS_PROCESS_CALL: - case NV402C_CTRL_I2C_TRANSACTION_TYPE_SMBUS_BLOCK_PROCESS_CALL: - case NV402C_CTRL_I2C_TRANSACTION_TYPE_SMBUS_MULTIBYTE_REGISTER_BLOCK_RW: - case NV402C_CTRL_I2C_TRANSACTION_TYPE_READ_EDID_DDC: - return NV_OK; // okay - } - - FINN_ERROR(NV_ERR_INVALID_ARGUMENT); - return NV_ERR_INVALID_ARGUMENT; -} -static NV_STATUS Nv402cCtrlI2cTransactionDataSmbusQuickRwSerialize(const NV402C_CTRL_I2C_TRANSACTION_DATA_SMBUS_QUICK_RW *src, finn_bit_pump_for_write *bp, NvBool seri_up) -{ - // Local variables - NV_STATUS status = NV_OK; - uint64_t field_presence_mask; - - // Field bitmasks - field_presence_mask = 0x3; - - // Write field-presence indicators. - if (finn_write_buffer(bp, field_presence_mask, 64)) - { - status = NV_ERR_BUFFER_TOO_SMALL; - FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); - goto exit; - } - - // Statically sized fields - // No range check for src->warFlags - // Deserialize 4-byte NvU32 object. - if (finn_write_buffer(bp, src->warFlags, 4 * 8)) - { - status = NV_ERR_BUFFER_TOO_SMALL; - FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); - goto exit; - } - - - // No range check for src->bWrite - // Deserialize 1-byte NvBool object. - if (finn_write_buffer(bp, src->bWrite, 1 * 8)) - { - status = NV_ERR_BUFFER_TOO_SMALL; - FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); - goto exit; - } - - - goto exit; // Suppress potential not-used warning -exit: - return status; -} - - -static NV_STATUS Nv402cCtrlI2cTransactionDataSmbusQuickRwDeserialize(finn_bit_pump_for_read *bp, NV402C_CTRL_I2C_TRANSACTION_DATA_SMBUS_QUICK_RW *dst, NvLength dst_size, NvBool deser_up) -{ - // Local variables - NV_STATUS status = NV_OK; - - // Check that the destination struct fits within the destination buffer - if (sizeof(NV402C_CTRL_I2C_TRANSACTION_DATA_SMBUS_QUICK_RW) > dst_size) - { - status = NV_ERR_BUFFER_TOO_SMALL; - FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); - goto exit; - } - - // Validate the field bitmasks, which must match the expected values for now. - if (finn_read_buffer(bp, 64) != 0x3) - { - status = NV_ERR_LIB_RM_VERSION_MISMATCH; - FINN_ERROR(NV_ERR_LIB_RM_VERSION_MISMATCH); - goto exit; - } - - // Statically sized fields - // Deserialize 4-byte NvU32 object. - dst->warFlags = (NvU32) finn_read_buffer(bp, 4 * 8); - // No range check for dst->warFlags - - - // Deserialize 1-byte NvBool object. - dst->bWrite = (NvBool) finn_read_buffer(bp, 1 * 8); - // No range check for dst->bWrite - - -exit: - return status; -} - - -static NV_STATUS Nv402cCtrlI2cTransactionDataI2cByteRwSerialize(const NV402C_CTRL_I2C_TRANSACTION_DATA_I2C_BYTE_RW *src, finn_bit_pump_for_write *bp, NvBool seri_up) -{ - // Local variables - NV_STATUS status = NV_OK; - uint64_t field_presence_mask; - - // Field bitmasks - field_presence_mask = 0x3; - - // Write field-presence indicators. - if (finn_write_buffer(bp, field_presence_mask, 64)) - { - status = NV_ERR_BUFFER_TOO_SMALL; - FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); - goto exit; - } - - // Statically sized fields - // No range check for src->bWrite - // Deserialize 1-byte NvBool object. - if (finn_write_buffer(bp, src->bWrite, 1 * 8)) - { - status = NV_ERR_BUFFER_TOO_SMALL; - FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); - goto exit; - } - - - // No range check for src->message - // Deserialize 1-byte NvU8 object. - if (finn_write_buffer(bp, src->message, 1 * 8)) - { - status = NV_ERR_BUFFER_TOO_SMALL; - FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); - goto exit; - } - - - goto exit; // Suppress potential not-used warning -exit: - return status; -} - - -static NV_STATUS Nv402cCtrlI2cTransactionDataI2cByteRwDeserialize(finn_bit_pump_for_read *bp, NV402C_CTRL_I2C_TRANSACTION_DATA_I2C_BYTE_RW *dst, NvLength dst_size, NvBool deser_up) -{ - // Local variables - NV_STATUS status = NV_OK; - - // Check that the destination struct fits within the destination buffer - if (sizeof(NV402C_CTRL_I2C_TRANSACTION_DATA_I2C_BYTE_RW) > dst_size) - { - status = NV_ERR_BUFFER_TOO_SMALL; - FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); - goto exit; - } - - // Validate the field bitmasks, which must match the expected values for now. - if (finn_read_buffer(bp, 64) != 0x3) - { - status = NV_ERR_LIB_RM_VERSION_MISMATCH; - FINN_ERROR(NV_ERR_LIB_RM_VERSION_MISMATCH); - goto exit; - } - - // Statically sized fields - // Deserialize 1-byte NvBool object. - dst->bWrite = (NvBool) finn_read_buffer(bp, 1 * 8); - // No range check for dst->bWrite - - - // Deserialize 1-byte NvU8 object. - dst->message = (NvU8) finn_read_buffer(bp, 1 * 8); - // No range check for dst->message - - -exit: - return status; -} - - -static NV_STATUS Nv402cCtrlI2cTransactionDataI2cBlockRwSerialize(const NV402C_CTRL_I2C_TRANSACTION_DATA_I2C_BLOCK_RW *src, finn_bit_pump_for_write *bp, NvBool seri_up) -{ - // Local variables - NV_STATUS status = NV_OK; - uint64_t field_presence_mask; - - // Field bitmasks - field_presence_mask = 0x7; - - // Write field-presence indicators. - if (finn_write_buffer(bp, field_presence_mask, 64)) - { - status = NV_ERR_BUFFER_TOO_SMALL; - FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); - goto exit; - } - - // Statically sized fields - // No range check for src->messageLength - // Deserialize 4-byte NvU32 object. - if (finn_write_buffer(bp, src->messageLength, 4 * 8)) - { - status = NV_ERR_BUFFER_TOO_SMALL; - FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); - goto exit; - } - - - // No range check for src->bWrite - // Deserialize 1-byte NvBool object. - if (finn_write_buffer(bp, src->bWrite, 1 * 8)) - { - status = NV_ERR_BUFFER_TOO_SMALL; - FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); - goto exit; - } - - - // Unbounded fields - // Set data-presence indicator. - if (finn_write_buffer(bp, !!(src->pMessage), 1)) - { - status = NV_ERR_BUFFER_TOO_SMALL; - FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); - goto exit; - } - - // Skip if pointer is null. - if (src->pMessage) - { - - // Serialize each 1-byte NvU8 element. - for (NvU64 j = 0; j < (src->messageLength); ++j) - { - if (finn_write_buffer(bp, ((NvU8 *) NvP64_VALUE(src->pMessage))[j], 1 * 8)) - { - status = NV_ERR_BUFFER_TOO_SMALL; - FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); - goto exit; - } - } - - // Free memory that was allocated during downward deserialization. - if (seri_up && src->pMessage) - FINN_FREE(NvP64_VALUE(src->pMessage)); - } - - goto exit; // Suppress potential not-used warning -exit: - return status; -} - - -static NV_STATUS Nv402cCtrlI2cTransactionDataI2cBlockRwDeserialize(finn_bit_pump_for_read *bp, NV402C_CTRL_I2C_TRANSACTION_DATA_I2C_BLOCK_RW *dst, NvLength dst_size, NvBool deser_up) -{ - // Local variables - NV_STATUS status = NV_OK; - - // Check that the destination struct fits within the destination buffer - if (sizeof(NV402C_CTRL_I2C_TRANSACTION_DATA_I2C_BLOCK_RW) > dst_size) - { - status = NV_ERR_BUFFER_TOO_SMALL; - FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); - goto exit; - } - - // Validate the field bitmasks, which must match the expected values for now. - if (finn_read_buffer(bp, 64) != 0x7) - { - status = NV_ERR_LIB_RM_VERSION_MISMATCH; - FINN_ERROR(NV_ERR_LIB_RM_VERSION_MISMATCH); - goto exit; - } - - // Statically sized fields - // Deserialize 4-byte NvU32 object. - dst->messageLength = (NvU32) finn_read_buffer(bp, 4 * 8); - // No range check for dst->messageLength - - - // Deserialize 1-byte NvBool object. - dst->bWrite = (NvBool) finn_read_buffer(bp, 1 * 8); - // No range check for dst->bWrite - - - // Unbounded fields - // Skip if data is not present (null pointer). - if (finn_read_buffer(bp, 1)) - { - - // Allocate memory and set pointer when deserializing down. - // (Calling cods is expected to do so when deserializing up.) - if (!deser_up) - { - dst->pMessage = FINN_MALLOC((dst->messageLength)); - if (!dst->pMessage) - { - status = NV_ERR_NO_MEMORY; - FINN_ERROR(NV_ERR_NO_MEMORY); - goto exit; - } - - FINN_MEMZERO(dst->pMessage, (dst->messageLength)); - } - - // Otherwise the pointer must be provided. - else if (!dst->pMessage) - { - status = NV_ERR_INVALID_POINTER; - FINN_ERROR(NV_ERR_INVALID_POINTER); - goto exit; - } - - // Deserialize each 1-byte NvU8 element. - for (NvU64 j = 0; j < (dst->messageLength); ++j) - { - ((NvU8 *) NvP64_VALUE(dst->pMessage))[j] = (NvU8) finn_read_buffer(bp, 1 * 8); - } - } - else - { - if (!deser_up) - dst->pMessage = NULL; - } - -exit: - return status; -} - - -static NV_STATUS Nv402cCtrlI2cTransactionDataSmbusByteRwSerialize(const NV402C_CTRL_I2C_TRANSACTION_DATA_SMBUS_BYTE_RW *src, finn_bit_pump_for_write *bp, NvBool seri_up) -{ - // Local variables - NV_STATUS status = NV_OK; - uint64_t field_presence_mask; - - // Field bitmasks - field_presence_mask = 0x7; - - // Write field-presence indicators. - if (finn_write_buffer(bp, field_presence_mask, 64)) - { - status = NV_ERR_BUFFER_TOO_SMALL; - FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); - goto exit; - } - - // Statically sized fields - // No range check for src->bWrite - // Deserialize 1-byte NvBool object. - if (finn_write_buffer(bp, src->bWrite, 1 * 8)) - { - status = NV_ERR_BUFFER_TOO_SMALL; - FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); - goto exit; - } - - - // No range check for src->registerAddress - // Deserialize 1-byte NvU8 object. - if (finn_write_buffer(bp, src->registerAddress, 1 * 8)) - { - status = NV_ERR_BUFFER_TOO_SMALL; - FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); - goto exit; - } - - - // No range check for src->message - // Deserialize 1-byte NvU8 object. - if (finn_write_buffer(bp, src->message, 1 * 8)) - { - status = NV_ERR_BUFFER_TOO_SMALL; - FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); - goto exit; - } - - - goto exit; // Suppress potential not-used warning -exit: - return status; -} - - -static NV_STATUS Nv402cCtrlI2cTransactionDataSmbusByteRwDeserialize(finn_bit_pump_for_read *bp, NV402C_CTRL_I2C_TRANSACTION_DATA_SMBUS_BYTE_RW *dst, NvLength dst_size, NvBool deser_up) -{ - // Local variables - NV_STATUS status = NV_OK; - - // Check that the destination struct fits within the destination buffer - if (sizeof(NV402C_CTRL_I2C_TRANSACTION_DATA_SMBUS_BYTE_RW) > dst_size) - { - status = NV_ERR_BUFFER_TOO_SMALL; - FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); - goto exit; - } - - // Validate the field bitmasks, which must match the expected values for now. - if (finn_read_buffer(bp, 64) != 0x7) - { - status = NV_ERR_LIB_RM_VERSION_MISMATCH; - FINN_ERROR(NV_ERR_LIB_RM_VERSION_MISMATCH); - goto exit; - } - - // Statically sized fields - // Deserialize 1-byte NvBool object. - dst->bWrite = (NvBool) finn_read_buffer(bp, 1 * 8); - // No range check for dst->bWrite - - - // Deserialize 1-byte NvU8 object. - dst->registerAddress = (NvU8) finn_read_buffer(bp, 1 * 8); - // No range check for dst->registerAddress - - - // Deserialize 1-byte NvU8 object. - dst->message = (NvU8) finn_read_buffer(bp, 1 * 8); - // No range check for dst->message - - -exit: - return status; -} - - -static NV_STATUS Nv402cCtrlI2cTransactionDataSmbusWordRwSerialize(const NV402C_CTRL_I2C_TRANSACTION_DATA_SMBUS_WORD_RW *src, finn_bit_pump_for_write *bp, NvBool seri_up) -{ - // Local variables - NV_STATUS status = NV_OK; - uint64_t field_presence_mask; - - // Field bitmasks - field_presence_mask = 0x7; - - // Write field-presence indicators. - if (finn_write_buffer(bp, field_presence_mask, 64)) - { - status = NV_ERR_BUFFER_TOO_SMALL; - FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); - goto exit; - } - - // Statically sized fields - // No range check for src->message - // Deserialize 2-byte NvU16 object. - if (finn_write_buffer(bp, src->message, 2 * 8)) - { - status = NV_ERR_BUFFER_TOO_SMALL; - FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); - goto exit; - } - - - // No range check for src->bWrite - // Deserialize 1-byte NvBool object. - if (finn_write_buffer(bp, src->bWrite, 1 * 8)) - { - status = NV_ERR_BUFFER_TOO_SMALL; - FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); - goto exit; - } - - - // No range check for src->registerAddress - // Deserialize 1-byte NvU8 object. - if (finn_write_buffer(bp, src->registerAddress, 1 * 8)) - { - status = NV_ERR_BUFFER_TOO_SMALL; - FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); - goto exit; - } - - - goto exit; // Suppress potential not-used warning -exit: - return status; -} - - -static NV_STATUS Nv402cCtrlI2cTransactionDataSmbusWordRwDeserialize(finn_bit_pump_for_read *bp, NV402C_CTRL_I2C_TRANSACTION_DATA_SMBUS_WORD_RW *dst, NvLength dst_size, NvBool deser_up) -{ - // Local variables - NV_STATUS status = NV_OK; - - // Check that the destination struct fits within the destination buffer - if (sizeof(NV402C_CTRL_I2C_TRANSACTION_DATA_SMBUS_WORD_RW) > dst_size) - { - status = NV_ERR_BUFFER_TOO_SMALL; - FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); - goto exit; - } - - // Validate the field bitmasks, which must match the expected values for now. - if (finn_read_buffer(bp, 64) != 0x7) - { - status = NV_ERR_LIB_RM_VERSION_MISMATCH; - FINN_ERROR(NV_ERR_LIB_RM_VERSION_MISMATCH); - goto exit; - } - - // Statically sized fields - // Deserialize 2-byte NvU16 object. - dst->message = (NvU16) finn_read_buffer(bp, 2 * 8); - // No range check for dst->message - - - // Deserialize 1-byte NvBool object. - dst->bWrite = (NvBool) finn_read_buffer(bp, 1 * 8); - // No range check for dst->bWrite - - - // Deserialize 1-byte NvU8 object. - dst->registerAddress = (NvU8) finn_read_buffer(bp, 1 * 8); - // No range check for dst->registerAddress - - -exit: - return status; -} - - -static NV_STATUS Nv402cCtrlI2cTransactionDataI2cBufferRwSerialize(const NV402C_CTRL_I2C_TRANSACTION_DATA_I2C_BUFFER_RW *src, finn_bit_pump_for_write *bp, NvBool seri_up) -{ - // Local variables - NV_STATUS status = NV_OK; - uint64_t field_presence_mask; - - // Field bitmasks - field_presence_mask = 0x1f; - - // Write field-presence indicators. - if (finn_write_buffer(bp, field_presence_mask, 64)) - { - status = NV_ERR_BUFFER_TOO_SMALL; - FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); - goto exit; - } - - // Statically sized fields - // No range check for src->warFlags - // Deserialize 4-byte NvU32 object. - if (finn_write_buffer(bp, src->warFlags, 4 * 8)) - { - status = NV_ERR_BUFFER_TOO_SMALL; - FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); - goto exit; - } - - - // No range check for src->messageLength - // Deserialize 4-byte NvU32 object. - if (finn_write_buffer(bp, src->messageLength, 4 * 8)) - { - status = NV_ERR_BUFFER_TOO_SMALL; - FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); - goto exit; - } - - - // No range check for src->bWrite - // Deserialize 1-byte NvBool object. - if (finn_write_buffer(bp, src->bWrite, 1 * 8)) - { - status = NV_ERR_BUFFER_TOO_SMALL; - FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); - goto exit; - } - - - // No range check for src->registerAddress - // Deserialize 1-byte NvU8 object. - if (finn_write_buffer(bp, src->registerAddress, 1 * 8)) - { - status = NV_ERR_BUFFER_TOO_SMALL; - FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); - goto exit; - } - - - // Unbounded fields - // Set data-presence indicator. - if (finn_write_buffer(bp, !!(src->pMessage), 1)) - { - status = NV_ERR_BUFFER_TOO_SMALL; - FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); - goto exit; - } - - // Skip if pointer is null. - if (src->pMessage) - { - - // Serialize each 1-byte NvU8 element. - for (NvU64 j = 0; j < (src->messageLength); ++j) - { - if (finn_write_buffer(bp, ((NvU8 *) NvP64_VALUE(src->pMessage))[j], 1 * 8)) - { - status = NV_ERR_BUFFER_TOO_SMALL; - FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); - goto exit; - } - } - - // Free memory that was allocated during downward deserialization. - if (seri_up && src->pMessage) - FINN_FREE(NvP64_VALUE(src->pMessage)); - } - - goto exit; // Suppress potential not-used warning -exit: - return status; -} - - -static NV_STATUS Nv402cCtrlI2cTransactionDataI2cBufferRwDeserialize(finn_bit_pump_for_read *bp, NV402C_CTRL_I2C_TRANSACTION_DATA_I2C_BUFFER_RW *dst, NvLength dst_size, NvBool deser_up) -{ - // Local variables - NV_STATUS status = NV_OK; - - // Check that the destination struct fits within the destination buffer - if (sizeof(NV402C_CTRL_I2C_TRANSACTION_DATA_I2C_BUFFER_RW) > dst_size) - { - status = NV_ERR_BUFFER_TOO_SMALL; - FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); - goto exit; - } - - // Validate the field bitmasks, which must match the expected values for now. - if (finn_read_buffer(bp, 64) != 0x1f) - { - status = NV_ERR_LIB_RM_VERSION_MISMATCH; - FINN_ERROR(NV_ERR_LIB_RM_VERSION_MISMATCH); - goto exit; - } - - // Statically sized fields - // Deserialize 4-byte NvU32 object. - dst->warFlags = (NvU32) finn_read_buffer(bp, 4 * 8); - // No range check for dst->warFlags - - - // Deserialize 4-byte NvU32 object. - dst->messageLength = (NvU32) finn_read_buffer(bp, 4 * 8); - // No range check for dst->messageLength - - - // Deserialize 1-byte NvBool object. - dst->bWrite = (NvBool) finn_read_buffer(bp, 1 * 8); - // No range check for dst->bWrite - - - // Deserialize 1-byte NvU8 object. - dst->registerAddress = (NvU8) finn_read_buffer(bp, 1 * 8); - // No range check for dst->registerAddress - - - // Unbounded fields - // Skip if data is not present (null pointer). - if (finn_read_buffer(bp, 1)) - { - - // Allocate memory and set pointer when deserializing down. - // (Calling cods is expected to do so when deserializing up.) - if (!deser_up) - { - dst->pMessage = FINN_MALLOC((dst->messageLength)); - if (!dst->pMessage) - { - status = NV_ERR_NO_MEMORY; - FINN_ERROR(NV_ERR_NO_MEMORY); - goto exit; - } - - FINN_MEMZERO(dst->pMessage, (dst->messageLength)); - } - - // Otherwise the pointer must be provided. - else if (!dst->pMessage) - { - status = NV_ERR_INVALID_POINTER; - FINN_ERROR(NV_ERR_INVALID_POINTER); - goto exit; - } - - // Deserialize each 1-byte NvU8 element. - for (NvU64 j = 0; j < (dst->messageLength); ++j) - { - ((NvU8 *) NvP64_VALUE(dst->pMessage))[j] = (NvU8) finn_read_buffer(bp, 1 * 8); - } - } - else - { - if (!deser_up) - dst->pMessage = NULL; - } - -exit: - return status; -} - - -static NV_STATUS Nv402cCtrlI2cTransactionDataSmbusBlockRwSerialize(const NV402C_CTRL_I2C_TRANSACTION_DATA_SMBUS_BLOCK_RW *src, finn_bit_pump_for_write *bp, NvBool seri_up) -{ - // Local variables - NV_STATUS status = NV_OK; - uint64_t field_presence_mask; - - // Field bitmasks - field_presence_mask = 0xf; - - // Write field-presence indicators. - if (finn_write_buffer(bp, field_presence_mask, 64)) - { - status = NV_ERR_BUFFER_TOO_SMALL; - FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); - goto exit; - } - - // Statically sized fields - // No range check for src->messageLength - // Deserialize 4-byte NvU32 object. - if (finn_write_buffer(bp, src->messageLength, 4 * 8)) - { - status = NV_ERR_BUFFER_TOO_SMALL; - FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); - goto exit; - } - - - // No range check for src->bWrite - // Deserialize 1-byte NvBool object. - if (finn_write_buffer(bp, src->bWrite, 1 * 8)) - { - status = NV_ERR_BUFFER_TOO_SMALL; - FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); - goto exit; - } - - - // No range check for src->registerAddress - // Deserialize 1-byte NvU8 object. - if (finn_write_buffer(bp, src->registerAddress, 1 * 8)) - { - status = NV_ERR_BUFFER_TOO_SMALL; - FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); - goto exit; - } - - - // Unbounded fields - // Set data-presence indicator. - if (finn_write_buffer(bp, !!(src->pMessage), 1)) - { - status = NV_ERR_BUFFER_TOO_SMALL; - FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); - goto exit; - } - - // Skip if pointer is null. - if (src->pMessage) - { - - // Serialize each 1-byte NvU8 element. - for (NvU64 j = 0; j < (src->messageLength); ++j) - { - if (finn_write_buffer(bp, ((NvU8 *) NvP64_VALUE(src->pMessage))[j], 1 * 8)) - { - status = NV_ERR_BUFFER_TOO_SMALL; - FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); - goto exit; - } - } - - // Free memory that was allocated during downward deserialization. - if (seri_up && src->pMessage) - FINN_FREE(NvP64_VALUE(src->pMessage)); - } - - goto exit; // Suppress potential not-used warning -exit: - return status; -} - - -static NV_STATUS Nv402cCtrlI2cTransactionDataSmbusBlockRwDeserialize(finn_bit_pump_for_read *bp, NV402C_CTRL_I2C_TRANSACTION_DATA_SMBUS_BLOCK_RW *dst, NvLength dst_size, NvBool deser_up) -{ - // Local variables - NV_STATUS status = NV_OK; - - // Check that the destination struct fits within the destination buffer - if (sizeof(NV402C_CTRL_I2C_TRANSACTION_DATA_SMBUS_BLOCK_RW) > dst_size) - { - status = NV_ERR_BUFFER_TOO_SMALL; - FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); - goto exit; - } - - // Validate the field bitmasks, which must match the expected values for now. - if (finn_read_buffer(bp, 64) != 0xf) - { - status = NV_ERR_LIB_RM_VERSION_MISMATCH; - FINN_ERROR(NV_ERR_LIB_RM_VERSION_MISMATCH); - goto exit; - } - - // Statically sized fields - // Deserialize 4-byte NvU32 object. - dst->messageLength = (NvU32) finn_read_buffer(bp, 4 * 8); - // No range check for dst->messageLength - - - // Deserialize 1-byte NvBool object. - dst->bWrite = (NvBool) finn_read_buffer(bp, 1 * 8); - // No range check for dst->bWrite - - - // Deserialize 1-byte NvU8 object. - dst->registerAddress = (NvU8) finn_read_buffer(bp, 1 * 8); - // No range check for dst->registerAddress - - - // Unbounded fields - // Skip if data is not present (null pointer). - if (finn_read_buffer(bp, 1)) - { - - // Allocate memory and set pointer when deserializing down. - // (Calling cods is expected to do so when deserializing up.) - if (!deser_up) - { - dst->pMessage = FINN_MALLOC((dst->messageLength)); - if (!dst->pMessage) - { - status = NV_ERR_NO_MEMORY; - FINN_ERROR(NV_ERR_NO_MEMORY); - goto exit; - } - - FINN_MEMZERO(dst->pMessage, (dst->messageLength)); - } - - // Otherwise the pointer must be provided. - else if (!dst->pMessage) - { - status = NV_ERR_INVALID_POINTER; - FINN_ERROR(NV_ERR_INVALID_POINTER); - goto exit; - } - - // Deserialize each 1-byte NvU8 element. - for (NvU64 j = 0; j < (dst->messageLength); ++j) - { - ((NvU8 *) NvP64_VALUE(dst->pMessage))[j] = (NvU8) finn_read_buffer(bp, 1 * 8); - } - } - else - { - if (!deser_up) - dst->pMessage = NULL; - } - -exit: - return status; -} - - -static NV_STATUS Nv402cCtrlI2cTransactionDataSmbusProcessCallSerialize(const NV402C_CTRL_I2C_TRANSACTION_DATA_SMBUS_PROCESS_CALL *src, finn_bit_pump_for_write *bp, NvBool seri_up) -{ - // Local variables - NV_STATUS status = NV_OK; - uint64_t field_presence_mask; - - // Field bitmasks - field_presence_mask = 0x7; - - // Write field-presence indicators. - if (finn_write_buffer(bp, field_presence_mask, 64)) - { - status = NV_ERR_BUFFER_TOO_SMALL; - FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); - goto exit; - } - - // Statically sized fields - // No range check for src->writeMessage - // Deserialize 2-byte NvU16 object. - if (finn_write_buffer(bp, src->writeMessage, 2 * 8)) - { - status = NV_ERR_BUFFER_TOO_SMALL; - FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); - goto exit; - } - - - // No range check for src->readMessage - // Deserialize 2-byte NvU16 object. - if (finn_write_buffer(bp, src->readMessage, 2 * 8)) - { - status = NV_ERR_BUFFER_TOO_SMALL; - FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); - goto exit; - } - - - // No range check for src->registerAddress - // Deserialize 1-byte NvU8 object. - if (finn_write_buffer(bp, src->registerAddress, 1 * 8)) - { - status = NV_ERR_BUFFER_TOO_SMALL; - FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); - goto exit; - } - - - goto exit; // Suppress potential not-used warning -exit: - return status; -} - - -static NV_STATUS Nv402cCtrlI2cTransactionDataSmbusProcessCallDeserialize(finn_bit_pump_for_read *bp, NV402C_CTRL_I2C_TRANSACTION_DATA_SMBUS_PROCESS_CALL *dst, NvLength dst_size, NvBool deser_up) -{ - // Local variables - NV_STATUS status = NV_OK; - - // Check that the destination struct fits within the destination buffer - if (sizeof(NV402C_CTRL_I2C_TRANSACTION_DATA_SMBUS_PROCESS_CALL) > dst_size) - { - status = NV_ERR_BUFFER_TOO_SMALL; - FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); - goto exit; - } - - // Validate the field bitmasks, which must match the expected values for now. - if (finn_read_buffer(bp, 64) != 0x7) - { - status = NV_ERR_LIB_RM_VERSION_MISMATCH; - FINN_ERROR(NV_ERR_LIB_RM_VERSION_MISMATCH); - goto exit; - } - - // Statically sized fields - // Deserialize 2-byte NvU16 object. - dst->writeMessage = (NvU16) finn_read_buffer(bp, 2 * 8); - // No range check for dst->writeMessage - - - // Deserialize 2-byte NvU16 object. - dst->readMessage = (NvU16) finn_read_buffer(bp, 2 * 8); - // No range check for dst->readMessage - - - // Deserialize 1-byte NvU8 object. - dst->registerAddress = (NvU8) finn_read_buffer(bp, 1 * 8); - // No range check for dst->registerAddress - - -exit: - return status; -} - - -static NV_STATUS Nv402cCtrlI2cTransactionDataSmbusBlockProcessCallSerialize(const NV402C_CTRL_I2C_TRANSACTION_DATA_SMBUS_BLOCK_PROCESS_CALL *src, finn_bit_pump_for_write *bp, NvBool seri_up) -{ - // Local variables - NV_STATUS status = NV_OK; - uint64_t field_presence_mask; - - // Field bitmasks - field_presence_mask = 0x1f; - - // Write field-presence indicators. - if (finn_write_buffer(bp, field_presence_mask, 64)) - { - status = NV_ERR_BUFFER_TOO_SMALL; - FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); - goto exit; - } - - // Statically sized fields - if (src->writeMessageLength > NV402C_CTRL_I2C_BLOCK_PROCESS_PROTOCOL_MAX) - { - status = NV_ERR_OUT_OF_RANGE; - FINN_ERROR(NV_ERR_OUT_OF_RANGE); - goto exit; - } - - // Deserialize 4-byte NvU32 object. - if (finn_write_buffer(bp, src->writeMessageLength, 4 * 8)) - { - status = NV_ERR_BUFFER_TOO_SMALL; - FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); - goto exit; - } - - - if (src->readMessageLength > NV402C_CTRL_I2C_BLOCK_PROCESS_PROTOCOL_MAX) - { - status = NV_ERR_OUT_OF_RANGE; - FINN_ERROR(NV_ERR_OUT_OF_RANGE); - goto exit; - } - - // Deserialize 4-byte NvU32 object. - if (finn_write_buffer(bp, src->readMessageLength, 4 * 8)) - { - status = NV_ERR_BUFFER_TOO_SMALL; - FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); - goto exit; - } - - - // No range check for src->registerAddress - // Deserialize 1-byte NvU8 object. - if (finn_write_buffer(bp, src->registerAddress, 1 * 8)) - { - status = NV_ERR_BUFFER_TOO_SMALL; - FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); - goto exit; - } - - - for (NvU64 i = 0; i < (NV402C_CTRL_I2C_BLOCK_PROCESS_PROTOCOL_MAX); ++i) - { - // No range check for src->writeMessage[i] - // Deserialize 1-byte NvU8 object. - if (finn_write_buffer(bp, src->writeMessage[i], 1 * 8)) - { - status = NV_ERR_BUFFER_TOO_SMALL; - FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); - goto exit; - } - } - - - for (NvU64 i = 0; i < (NV402C_CTRL_I2C_BLOCK_PROCESS_PROTOCOL_MAX); ++i) - { - // No range check for src->readMessage[i] - // Deserialize 1-byte NvU8 object. - if (finn_write_buffer(bp, src->readMessage[i], 1 * 8)) - { - status = NV_ERR_BUFFER_TOO_SMALL; - FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); - goto exit; - } - } - - - goto exit; // Suppress potential not-used warning -exit: - return status; -} - - -static NV_STATUS Nv402cCtrlI2cTransactionDataSmbusBlockProcessCallDeserialize(finn_bit_pump_for_read *bp, NV402C_CTRL_I2C_TRANSACTION_DATA_SMBUS_BLOCK_PROCESS_CALL *dst, NvLength dst_size, NvBool deser_up) -{ - // Local variables - NV_STATUS status = NV_OK; - - // Check that the destination struct fits within the destination buffer - if (sizeof(NV402C_CTRL_I2C_TRANSACTION_DATA_SMBUS_BLOCK_PROCESS_CALL) > dst_size) - { - status = NV_ERR_BUFFER_TOO_SMALL; - FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); - goto exit; - } - - // Validate the field bitmasks, which must match the expected values for now. - if (finn_read_buffer(bp, 64) != 0x1f) - { - status = NV_ERR_LIB_RM_VERSION_MISMATCH; - FINN_ERROR(NV_ERR_LIB_RM_VERSION_MISMATCH); - goto exit; - } - - // Statically sized fields - // Deserialize 4-byte NvU32 object. - dst->writeMessageLength = (NvU32) finn_read_buffer(bp, 4 * 8); - if (dst->writeMessageLength > NV402C_CTRL_I2C_BLOCK_PROCESS_PROTOCOL_MAX) - { - status = NV_ERR_OUT_OF_RANGE; - FINN_ERROR(NV_ERR_OUT_OF_RANGE); - goto exit; - } - - - - // Deserialize 4-byte NvU32 object. - dst->readMessageLength = (NvU32) finn_read_buffer(bp, 4 * 8); - if (dst->readMessageLength > NV402C_CTRL_I2C_BLOCK_PROCESS_PROTOCOL_MAX) - { - status = NV_ERR_OUT_OF_RANGE; - FINN_ERROR(NV_ERR_OUT_OF_RANGE); - goto exit; - } - - - - // Deserialize 1-byte NvU8 object. - dst->registerAddress = (NvU8) finn_read_buffer(bp, 1 * 8); - // No range check for dst->registerAddress - - - for (NvU64 i = 0; i < (NV402C_CTRL_I2C_BLOCK_PROCESS_PROTOCOL_MAX); ++i) - { - // Deserialize 1-byte NvU8 object. - dst->writeMessage[i] = (NvU8) finn_read_buffer(bp, 1 * 8); - // No range check for dst->writeMessage[i] - } - - - for (NvU64 i = 0; i < (NV402C_CTRL_I2C_BLOCK_PROCESS_PROTOCOL_MAX); ++i) - { - // Deserialize 1-byte NvU8 object. - dst->readMessage[i] = (NvU8) finn_read_buffer(bp, 1 * 8); - // No range check for dst->readMessage[i] - } - - -exit: - return status; -} - - -static NV_STATUS Nv402cCtrlI2cTransactionDataSmbusMultibyteRegisterBlockRwSerialize(const NV402C_CTRL_I2C_TRANSACTION_DATA_SMBUS_MULTIBYTE_REGISTER_BLOCK_RW *src, finn_bit_pump_for_write *bp, NvBool seri_up) -{ - // Local variables - NV_STATUS status = NV_OK; - uint64_t field_presence_mask; - - // Field bitmasks - field_presence_mask = 0x3f; - - // Write field-presence indicators. - if (finn_write_buffer(bp, field_presence_mask, 64)) - { - status = NV_ERR_BUFFER_TOO_SMALL; - FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); - goto exit; - } - - // Statically sized fields - // No range check for src->warFlags - // Deserialize 4-byte NvU32 object. - if (finn_write_buffer(bp, src->warFlags, 4 * 8)) - { - status = NV_ERR_BUFFER_TOO_SMALL; - FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); - goto exit; - } - - - if (src->indexLength > NV402C_CTRL_I2C_INDEX_LENGTH_MAX) - { - status = NV_ERR_OUT_OF_RANGE; - FINN_ERROR(NV_ERR_OUT_OF_RANGE); - goto exit; - } - - // Deserialize 4-byte NvU32 object. - if (finn_write_buffer(bp, src->indexLength, 4 * 8)) - { - status = NV_ERR_BUFFER_TOO_SMALL; - FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); - goto exit; - } - - - // No range check for src->messageLength - // Deserialize 4-byte NvU32 object. - if (finn_write_buffer(bp, src->messageLength, 4 * 8)) - { - status = NV_ERR_BUFFER_TOO_SMALL; - FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); - goto exit; - } - - - // No range check for src->bWrite - // Deserialize 1-byte NvBool object. - if (finn_write_buffer(bp, src->bWrite, 1 * 8)) - { - status = NV_ERR_BUFFER_TOO_SMALL; - FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); - goto exit; - } - - - for (NvU64 i = 0; i < (NV402C_CTRL_I2C_INDEX_LENGTH_MAX); ++i) - { - // No range check for src->index[i] - // Deserialize 1-byte NvU8 object. - if (finn_write_buffer(bp, src->index[i], 1 * 8)) - { - status = NV_ERR_BUFFER_TOO_SMALL; - FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); - goto exit; - } - } - - - // Unbounded fields - // Set data-presence indicator. - if (finn_write_buffer(bp, !!(src->pMessage), 1)) - { - status = NV_ERR_BUFFER_TOO_SMALL; - FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); - goto exit; - } - - // Skip if pointer is null. - if (src->pMessage) - { - - // Serialize each 1-byte NvU8 element. - for (NvU64 j = 0; j < (src->messageLength); ++j) - { - if (finn_write_buffer(bp, ((NvU8 *) NvP64_VALUE(src->pMessage))[j], 1 * 8)) - { - status = NV_ERR_BUFFER_TOO_SMALL; - FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); - goto exit; - } - } - - // Free memory that was allocated during downward deserialization. - if (seri_up && src->pMessage) - FINN_FREE(NvP64_VALUE(src->pMessage)); - } - - goto exit; // Suppress potential not-used warning -exit: - return status; -} - - -static NV_STATUS Nv402cCtrlI2cTransactionDataSmbusMultibyteRegisterBlockRwDeserialize(finn_bit_pump_for_read *bp, NV402C_CTRL_I2C_TRANSACTION_DATA_SMBUS_MULTIBYTE_REGISTER_BLOCK_RW *dst, NvLength dst_size, NvBool deser_up) -{ - // Local variables - NV_STATUS status = NV_OK; - - // Check that the destination struct fits within the destination buffer - if (sizeof(NV402C_CTRL_I2C_TRANSACTION_DATA_SMBUS_MULTIBYTE_REGISTER_BLOCK_RW) > dst_size) - { - status = NV_ERR_BUFFER_TOO_SMALL; - FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); - goto exit; - } - - // Validate the field bitmasks, which must match the expected values for now. - if (finn_read_buffer(bp, 64) != 0x3f) - { - status = NV_ERR_LIB_RM_VERSION_MISMATCH; - FINN_ERROR(NV_ERR_LIB_RM_VERSION_MISMATCH); - goto exit; - } - - // Statically sized fields - // Deserialize 4-byte NvU32 object. - dst->warFlags = (NvU32) finn_read_buffer(bp, 4 * 8); - // No range check for dst->warFlags - - - // Deserialize 4-byte NvU32 object. - dst->indexLength = (NvU32) finn_read_buffer(bp, 4 * 8); - if (dst->indexLength > NV402C_CTRL_I2C_INDEX_LENGTH_MAX) - { - status = NV_ERR_OUT_OF_RANGE; - FINN_ERROR(NV_ERR_OUT_OF_RANGE); - goto exit; - } - - - - // Deserialize 4-byte NvU32 object. - dst->messageLength = (NvU32) finn_read_buffer(bp, 4 * 8); - // No range check for dst->messageLength - - - // Deserialize 1-byte NvBool object. - dst->bWrite = (NvBool) finn_read_buffer(bp, 1 * 8); - // No range check for dst->bWrite - - - for (NvU64 i = 0; i < (NV402C_CTRL_I2C_INDEX_LENGTH_MAX); ++i) - { - // Deserialize 1-byte NvU8 object. - dst->index[i] = (NvU8) finn_read_buffer(bp, 1 * 8); - // No range check for dst->index[i] - } - - - // Unbounded fields - // Skip if data is not present (null pointer). - if (finn_read_buffer(bp, 1)) - { - - // Allocate memory and set pointer when deserializing down. - // (Calling cods is expected to do so when deserializing up.) - if (!deser_up) - { - dst->pMessage = FINN_MALLOC((dst->messageLength)); - if (!dst->pMessage) - { - status = NV_ERR_NO_MEMORY; - FINN_ERROR(NV_ERR_NO_MEMORY); - goto exit; - } - - FINN_MEMZERO(dst->pMessage, (dst->messageLength)); - } - - // Otherwise the pointer must be provided. - else if (!dst->pMessage) - { - status = NV_ERR_INVALID_POINTER; - FINN_ERROR(NV_ERR_INVALID_POINTER); - goto exit; - } - - // Deserialize each 1-byte NvU8 element. - for (NvU64 j = 0; j < (dst->messageLength); ++j) - { - ((NvU8 *) NvP64_VALUE(dst->pMessage))[j] = (NvU8) finn_read_buffer(bp, 1 * 8); - } - } - else - { - if (!deser_up) - dst->pMessage = NULL; - } - -exit: - return status; -} - - -static NV_STATUS Nv402cCtrlI2cTransactionDataReadEdidDdcSerialize(const NV402C_CTRL_I2C_TRANSACTION_DATA_READ_EDID_DDC *src, finn_bit_pump_for_write *bp, NvBool seri_up) -{ - // Local variables - NV_STATUS status = NV_OK; - uint64_t field_presence_mask; - - // Field bitmasks - field_presence_mask = 0xf; - - // Write field-presence indicators. - if (finn_write_buffer(bp, field_presence_mask, 64)) - { - status = NV_ERR_BUFFER_TOO_SMALL; - FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); - goto exit; - } - - // Statically sized fields - // No range check for src->messageLength - // Deserialize 4-byte NvU32 object. - if (finn_write_buffer(bp, src->messageLength, 4 * 8)) - { - status = NV_ERR_BUFFER_TOO_SMALL; - FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); - goto exit; - } - - - // No range check for src->segmentNumber - // Deserialize 1-byte NvU8 object. - if (finn_write_buffer(bp, src->segmentNumber, 1 * 8)) - { - status = NV_ERR_BUFFER_TOO_SMALL; - FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); - goto exit; - } - - - // No range check for src->registerAddress - // Deserialize 1-byte NvU8 object. - if (finn_write_buffer(bp, src->registerAddress, 1 * 8)) - { - status = NV_ERR_BUFFER_TOO_SMALL; - FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); - goto exit; - } - - - // Unbounded fields - // Set data-presence indicator. - if (finn_write_buffer(bp, !!(src->pMessage), 1)) - { - status = NV_ERR_BUFFER_TOO_SMALL; - FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); - goto exit; - } - - // Skip if pointer is null. - if (src->pMessage) - { - - // Serialize each 1-byte NvU8 element. - for (NvU64 j = 0; j < (src->messageLength); ++j) - { - if (finn_write_buffer(bp, ((NvU8 *) NvP64_VALUE(src->pMessage))[j], 1 * 8)) - { - status = NV_ERR_BUFFER_TOO_SMALL; - FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); - goto exit; - } - } - - // Free memory that was allocated during downward deserialization. - if (seri_up && src->pMessage) - FINN_FREE(NvP64_VALUE(src->pMessage)); - } - - goto exit; // Suppress potential not-used warning -exit: - return status; -} - - -static NV_STATUS Nv402cCtrlI2cTransactionDataReadEdidDdcDeserialize(finn_bit_pump_for_read *bp, NV402C_CTRL_I2C_TRANSACTION_DATA_READ_EDID_DDC *dst, NvLength dst_size, NvBool deser_up) -{ - // Local variables - NV_STATUS status = NV_OK; - - // Check that the destination struct fits within the destination buffer - if (sizeof(NV402C_CTRL_I2C_TRANSACTION_DATA_READ_EDID_DDC) > dst_size) - { - status = NV_ERR_BUFFER_TOO_SMALL; - FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); - goto exit; - } - - // Validate the field bitmasks, which must match the expected values for now. - if (finn_read_buffer(bp, 64) != 0xf) - { - status = NV_ERR_LIB_RM_VERSION_MISMATCH; - FINN_ERROR(NV_ERR_LIB_RM_VERSION_MISMATCH); - goto exit; - } - - // Statically sized fields - // Deserialize 4-byte NvU32 object. - dst->messageLength = (NvU32) finn_read_buffer(bp, 4 * 8); - // No range check for dst->messageLength - - - // Deserialize 1-byte NvU8 object. - dst->segmentNumber = (NvU8) finn_read_buffer(bp, 1 * 8); - // No range check for dst->segmentNumber - - - // Deserialize 1-byte NvU8 object. - dst->registerAddress = (NvU8) finn_read_buffer(bp, 1 * 8); - // No range check for dst->registerAddress - - - // Unbounded fields - // Skip if data is not present (null pointer). - if (finn_read_buffer(bp, 1)) - { - - // Allocate memory and set pointer when deserializing down. - // (Calling cods is expected to do so when deserializing up.) - if (!deser_up) - { - dst->pMessage = FINN_MALLOC((dst->messageLength)); - if (!dst->pMessage) - { - status = NV_ERR_NO_MEMORY; - FINN_ERROR(NV_ERR_NO_MEMORY); - goto exit; - } - - FINN_MEMZERO(dst->pMessage, (dst->messageLength)); - } - - // Otherwise the pointer must be provided. - else if (!dst->pMessage) - { - status = NV_ERR_INVALID_POINTER; - FINN_ERROR(NV_ERR_INVALID_POINTER); - goto exit; - } - - // Deserialize each 1-byte NvU8 element. - for (NvU64 j = 0; j < (dst->messageLength); ++j) - { - ((NvU8 *) NvP64_VALUE(dst->pMessage))[j] = (NvU8) finn_read_buffer(bp, 1 * 8); - } - } - else - { - if (!deser_up) - dst->pMessage = NULL; - } - -exit: - return status; -} - - -static NV_STATUS Nv402cCtrlI2cTransactionDataSerialize(const NV402C_CTRL_I2C_TRANSACTION_DATA *src, finn_bit_pump_for_write *bp, NvBool seri_up, NV402C_CTRL_I2C_TRANSACTION_TYPE transType) -{ - // Local variables - NV_STATUS status = NV_OK; - uint64_t field_presence_mask; - - // Field bitmasks - field_presence_mask = 0x7ff; - - // Write field-presence indicators. - if (finn_write_buffer(bp, field_presence_mask, 64)) - { - status = NV_ERR_BUFFER_TOO_SMALL; - FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); - goto exit; - } - - // Field copying based on union selector - switch (transType) - { - case NV402C_CTRL_I2C_TRANSACTION_TYPE_SMBUS_QUICK_RW: - { - status = Nv402cCtrlI2cTransactionDataSmbusQuickRwSerialize(&src->smbusQuickData, bp, seri_up); - if (status != NV_OK) - goto exit; - - break; - } - case NV402C_CTRL_I2C_TRANSACTION_TYPE_I2C_BYTE_RW: - { - status = Nv402cCtrlI2cTransactionDataI2cByteRwSerialize(&src->i2cByteData, bp, seri_up); - if (status != NV_OK) - goto exit; - - break; - } - case NV402C_CTRL_I2C_TRANSACTION_TYPE_SMBUS_BYTE_RW: - { - status = Nv402cCtrlI2cTransactionDataSmbusByteRwSerialize(&src->smbusByteData, bp, seri_up); - if (status != NV_OK) - goto exit; - - break; - } - case NV402C_CTRL_I2C_TRANSACTION_TYPE_SMBUS_WORD_RW: - { - status = Nv402cCtrlI2cTransactionDataSmbusWordRwSerialize(&src->smbusWordData, bp, seri_up); - if (status != NV_OK) - goto exit; - - break; - } - case NV402C_CTRL_I2C_TRANSACTION_TYPE_SMBUS_PROCESS_CALL: - { - status = Nv402cCtrlI2cTransactionDataSmbusProcessCallSerialize(&src->smbusProcessData, bp, seri_up); - if (status != NV_OK) - goto exit; - - break; - } - case NV402C_CTRL_I2C_TRANSACTION_TYPE_SMBUS_BLOCK_PROCESS_CALL: - { - status = Nv402cCtrlI2cTransactionDataSmbusBlockProcessCallSerialize(&src->smbusBlockProcessData, bp, seri_up); - if (status != NV_OK) - goto exit; - - break; - } - case NV402C_CTRL_I2C_TRANSACTION_TYPE_I2C_BLOCK_RW: - { - status = Nv402cCtrlI2cTransactionDataI2cBlockRwSerialize(&src->i2cBlockData, bp, seri_up); - if (status != NV_OK) - goto exit; - - break; - } - case NV402C_CTRL_I2C_TRANSACTION_TYPE_I2C_BUFFER_RW: - { - status = Nv402cCtrlI2cTransactionDataI2cBufferRwSerialize(&src->i2cBufferData, bp, seri_up); - if (status != NV_OK) - goto exit; - - break; - } - case NV402C_CTRL_I2C_TRANSACTION_TYPE_SMBUS_BLOCK_RW: - { - status = Nv402cCtrlI2cTransactionDataSmbusBlockRwSerialize(&src->smbusBlockData, bp, seri_up); - if (status != NV_OK) - goto exit; - - break; - } - case NV402C_CTRL_I2C_TRANSACTION_TYPE_SMBUS_MULTIBYTE_REGISTER_BLOCK_RW: - { - status = Nv402cCtrlI2cTransactionDataSmbusMultibyteRegisterBlockRwSerialize(&src->smbusMultibyteRegisterData, bp, seri_up); - if (status != NV_OK) - goto exit; - - break; - } - case NV402C_CTRL_I2C_TRANSACTION_TYPE_READ_EDID_DDC: - { - status = Nv402cCtrlI2cTransactionDataReadEdidDdcSerialize(&src->edidData, bp, seri_up); - if (status != NV_OK) - goto exit; - - break; - } - default: - { - status = NV_ERR_INVALID_ARGUMENT; - FINN_ERROR(NV_ERR_INVALID_ARGUMENT); - goto exit; - } - } - - goto exit; // Suppress potential not-used warning -exit: - return status; -} - - -static NV_STATUS Nv402cCtrlI2cTransactionDataDeserialize(finn_bit_pump_for_read *bp, NV402C_CTRL_I2C_TRANSACTION_DATA *dst, NvLength dst_size, NvBool deser_up, NV402C_CTRL_I2C_TRANSACTION_TYPE transType) -{ - // Local variables - NV_STATUS status = NV_OK; - - // Check that the destination struct fits within the destination buffer - if (sizeof(NV402C_CTRL_I2C_TRANSACTION_DATA) > dst_size) - { - status = NV_ERR_BUFFER_TOO_SMALL; - FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); - goto exit; - } - - // Validate the field bitmasks, which must match the expected values for now. - if (finn_read_buffer(bp, 64) != 0x7ff) - { - status = NV_ERR_LIB_RM_VERSION_MISMATCH; - FINN_ERROR(NV_ERR_LIB_RM_VERSION_MISMATCH); - goto exit; - } - - // Field copying based on union selector - switch (transType) - { - case NV402C_CTRL_I2C_TRANSACTION_TYPE_SMBUS_QUICK_RW: - { - status = Nv402cCtrlI2cTransactionDataSmbusQuickRwDeserialize(bp, &dst->smbusQuickData, dst_size, deser_up); - if (status != NV_OK) - goto exit; - - break; - } - case NV402C_CTRL_I2C_TRANSACTION_TYPE_I2C_BYTE_RW: - { - status = Nv402cCtrlI2cTransactionDataI2cByteRwDeserialize(bp, &dst->i2cByteData, dst_size, deser_up); - if (status != NV_OK) - goto exit; - - break; - } - case NV402C_CTRL_I2C_TRANSACTION_TYPE_SMBUS_BYTE_RW: - { - status = Nv402cCtrlI2cTransactionDataSmbusByteRwDeserialize(bp, &dst->smbusByteData, dst_size, deser_up); - if (status != NV_OK) - goto exit; - - break; - } - case NV402C_CTRL_I2C_TRANSACTION_TYPE_SMBUS_WORD_RW: - { - status = Nv402cCtrlI2cTransactionDataSmbusWordRwDeserialize(bp, &dst->smbusWordData, dst_size, deser_up); - if (status != NV_OK) - goto exit; - - break; - } - case NV402C_CTRL_I2C_TRANSACTION_TYPE_SMBUS_PROCESS_CALL: - { - status = Nv402cCtrlI2cTransactionDataSmbusProcessCallDeserialize(bp, &dst->smbusProcessData, dst_size, deser_up); - if (status != NV_OK) - goto exit; - - break; - } - case NV402C_CTRL_I2C_TRANSACTION_TYPE_SMBUS_BLOCK_PROCESS_CALL: - { - status = Nv402cCtrlI2cTransactionDataSmbusBlockProcessCallDeserialize(bp, &dst->smbusBlockProcessData, dst_size, deser_up); - if (status != NV_OK) - goto exit; - - break; - } - case NV402C_CTRL_I2C_TRANSACTION_TYPE_I2C_BLOCK_RW: - { - status = Nv402cCtrlI2cTransactionDataI2cBlockRwDeserialize(bp, &dst->i2cBlockData, dst_size, deser_up); - if (status != NV_OK) - goto exit; - - break; - } - case NV402C_CTRL_I2C_TRANSACTION_TYPE_I2C_BUFFER_RW: - { - status = Nv402cCtrlI2cTransactionDataI2cBufferRwDeserialize(bp, &dst->i2cBufferData, dst_size, deser_up); - if (status != NV_OK) - goto exit; - - break; - } - case NV402C_CTRL_I2C_TRANSACTION_TYPE_SMBUS_BLOCK_RW: - { - status = Nv402cCtrlI2cTransactionDataSmbusBlockRwDeserialize(bp, &dst->smbusBlockData, dst_size, deser_up); - if (status != NV_OK) - goto exit; - - break; - } - case NV402C_CTRL_I2C_TRANSACTION_TYPE_SMBUS_MULTIBYTE_REGISTER_BLOCK_RW: - { - status = Nv402cCtrlI2cTransactionDataSmbusMultibyteRegisterBlockRwDeserialize(bp, &dst->smbusMultibyteRegisterData, dst_size, deser_up); - if (status != NV_OK) - goto exit; - - break; - } - case NV402C_CTRL_I2C_TRANSACTION_TYPE_READ_EDID_DDC: - { - status = Nv402cCtrlI2cTransactionDataReadEdidDdcDeserialize(bp, &dst->edidData, dst_size, deser_up); - if (status != NV_OK) - goto exit; - - break; - } - default: - { - status = NV_ERR_INVALID_ARGUMENT; - FINN_ERROR(NV_ERR_INVALID_ARGUMENT); - goto exit; - } - } - -exit: - return status; -} - - -static NV_STATUS Nv402cCtrlI2cTransactionParamsSerialize(const NV402C_CTRL_I2C_TRANSACTION_PARAMS *src, finn_bit_pump_for_write *bp, NvBool seri_up) -{ - // Local variables - NV_STATUS status = NV_OK; - uint64_t field_presence_mask; - - // Field bitmasks - field_presence_mask = 0x1f; - - // Write field-presence indicators. - if (finn_write_buffer(bp, field_presence_mask, 64)) - { - status = NV_ERR_BUFFER_TOO_SMALL; - FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); - goto exit; - } - - // Statically sized fields - // No range check for src->flags - // Deserialize 4-byte NvU32 object. - if (finn_write_buffer(bp, src->flags, 4 * 8)) - { - status = NV_ERR_BUFFER_TOO_SMALL; - FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); - goto exit; - } - - - // No range check for src->transType - status = Nv402cCtrlI2cTransactionTypeCheckEnum(src->transType); - if (status != NV_OK) - goto exit; - - // Deserialize 4-byte NV402C_CTRL_I2C_TRANSACTION_TYPE object. - if (finn_write_buffer(bp, src->transType, 4 * 8)) - { - status = NV_ERR_BUFFER_TOO_SMALL; - FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); - goto exit; - } - - - // No range check for src->deviceAddress - // Deserialize 2-byte NvU16 object. - if (finn_write_buffer(bp, src->deviceAddress, 2 * 8)) - { - status = NV_ERR_BUFFER_TOO_SMALL; - FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); - goto exit; - } - - - // No range check for src->portId - // Deserialize 1-byte NvU8 object. - if (finn_write_buffer(bp, src->portId, 1 * 8)) - { - status = NV_ERR_BUFFER_TOO_SMALL; - FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); - goto exit; - } - - - // Unbounded fields - status = Nv402cCtrlI2cTransactionDataSerialize(&src->transData, bp, seri_up, src->transType); - if (status != NV_OK) - goto exit; - - goto exit; // Suppress potential not-used warning -exit: - return status; -} - - -static NV_STATUS Nv402cCtrlI2cTransactionParamsDeserialize(finn_bit_pump_for_read *bp, NV402C_CTRL_I2C_TRANSACTION_PARAMS *dst, NvLength dst_size, NvBool deser_up) -{ - // Local variables - NV_STATUS status = NV_OK; - - // Check that the destination struct fits within the destination buffer - if (sizeof(NV402C_CTRL_I2C_TRANSACTION_PARAMS) > dst_size) - { - status = NV_ERR_BUFFER_TOO_SMALL; - FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); - goto exit; - } - - // Validate the field bitmasks, which must match the expected values for now. - if (finn_read_buffer(bp, 64) != 0x1f) - { - status = NV_ERR_LIB_RM_VERSION_MISMATCH; - FINN_ERROR(NV_ERR_LIB_RM_VERSION_MISMATCH); - goto exit; - } - - // Statically sized fields - // Deserialize 4-byte NvU32 object. - dst->flags = (NvU32) finn_read_buffer(bp, 4 * 8); - // No range check for dst->flags - - - // Deserialize 4-byte NV402C_CTRL_I2C_TRANSACTION_TYPE object. - dst->transType = (NV402C_CTRL_I2C_TRANSACTION_TYPE) finn_read_buffer(bp, 4 * 8); - // No range check for dst->transType - status = Nv402cCtrlI2cTransactionTypeCheckEnum(dst->transType); - if (status != NV_OK) - goto exit; - - - - // Deserialize 2-byte NvU16 object. - dst->deviceAddress = (NvU16) finn_read_buffer(bp, 2 * 8); - // No range check for dst->deviceAddress - - - // Deserialize 1-byte NvU8 object. - dst->portId = (NvU8) finn_read_buffer(bp, 1 * 8); - // No range check for dst->portId - - - // Unbounded fields - status = Nv402cCtrlI2cTransactionDataDeserialize(bp, &dst->transData, dst_size, deser_up, dst->transType); - if (status != NV_OK) - goto exit; - -exit: - return status; -} - - -static NV_STATUS Nv83deCtrlDebugReadMemoryParamsSerialize(const NV83DE_CTRL_DEBUG_READ_MEMORY_PARAMS *src, finn_bit_pump_for_write *bp, NvBool seri_up) -{ - // Local variables - NV_STATUS status = NV_OK; - uint64_t field_presence_mask; - - // Field bitmasks - field_presence_mask = 0xf; - - // Write field-presence indicators. - if (finn_write_buffer(bp, field_presence_mask, 64)) - { - status = NV_ERR_BUFFER_TOO_SMALL; - FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); - goto exit; - } - - // Statically sized fields - // No range check for src->offset - // Deserialize 8-byte NvU64 object. - if (finn_write_buffer(bp, src->offset, 8 * 8)) - { - status = NV_ERR_BUFFER_TOO_SMALL; - FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); - goto exit; - } - - - // No range check for src->hMemory - // Deserialize 4-byte NvU32 object. - if (finn_write_buffer(bp, src->hMemory, 4 * 8)) - { - status = NV_ERR_BUFFER_TOO_SMALL; - FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); - goto exit; - } - - - // No range check for src->length - // Deserialize 4-byte NvU32 object. - if (finn_write_buffer(bp, src->length, 4 * 8)) - { - status = NV_ERR_BUFFER_TOO_SMALL; - FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); - goto exit; - } - - - // Unbounded fields - // Set data-presence indicator. - if (finn_write_buffer(bp, !!(src->buffer), 1)) - { - status = NV_ERR_BUFFER_TOO_SMALL; - FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); - goto exit; - } - - // Skip if pointer is null. - if (src->buffer) - { - - // Serialize each 1-byte NvU8 element. - for (NvU64 j = 0; j < (src->length); ++j) - { - if (finn_write_buffer(bp, ((NvU8 *) NvP64_VALUE(src->buffer))[j], 1 * 8)) - { - status = NV_ERR_BUFFER_TOO_SMALL; - FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); - goto exit; - } - } - - // Free memory that was allocated during downward deserialization. - if (seri_up && src->buffer) - FINN_FREE(NvP64_VALUE(src->buffer)); - } - - goto exit; // Suppress potential not-used warning -exit: - return status; -} - - -static NV_STATUS Nv83deCtrlDebugReadMemoryParamsDeserialize(finn_bit_pump_for_read *bp, NV83DE_CTRL_DEBUG_READ_MEMORY_PARAMS *dst, NvLength dst_size, NvBool deser_up) -{ - // Local variables - NV_STATUS status = NV_OK; - - // Check that the destination struct fits within the destination buffer - if (sizeof(NV83DE_CTRL_DEBUG_READ_MEMORY_PARAMS) > dst_size) - { - status = NV_ERR_BUFFER_TOO_SMALL; - FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); - goto exit; - } - - // Validate the field bitmasks, which must match the expected values for now. - if (finn_read_buffer(bp, 64) != 0xf) - { - status = NV_ERR_LIB_RM_VERSION_MISMATCH; - FINN_ERROR(NV_ERR_LIB_RM_VERSION_MISMATCH); - goto exit; - } - - // Statically sized fields - // Deserialize 8-byte NvU64 object. - dst->offset = (NvU64) finn_read_buffer(bp, 8 * 8); - // No range check for dst->offset - - - // Deserialize 4-byte NvU32 object. - dst->hMemory = (NvU32) finn_read_buffer(bp, 4 * 8); - // No range check for dst->hMemory - - - // Deserialize 4-byte NvU32 object. - dst->length = (NvU32) finn_read_buffer(bp, 4 * 8); - // No range check for dst->length - - - // Unbounded fields - // Skip if data is not present (null pointer). - if (finn_read_buffer(bp, 1)) - { - - // Allocate memory and set pointer when deserializing down. - // (Calling cods is expected to do so when deserializing up.) - if (!deser_up) - { - dst->buffer = FINN_MALLOC((dst->length)); - if (!dst->buffer) - { - status = NV_ERR_NO_MEMORY; - FINN_ERROR(NV_ERR_NO_MEMORY); - goto exit; - } - - FINN_MEMZERO(dst->buffer, (dst->length)); - } - - // Otherwise the pointer must be provided. - else if (!dst->buffer) - { - status = NV_ERR_INVALID_POINTER; - FINN_ERROR(NV_ERR_INVALID_POINTER); - goto exit; - } - - // Deserialize each 1-byte NvU8 element. - for (NvU64 j = 0; j < (dst->length); ++j) - { - ((NvU8 *) NvP64_VALUE(dst->buffer))[j] = (NvU8) finn_read_buffer(bp, 1 * 8); - } - } - else - { - if (!deser_up) - dst->buffer = NULL; - } - -exit: - return status; -} - - -static NV_STATUS Nv83deCtrlDebugWriteMemoryParamsSerialize(const NV83DE_CTRL_DEBUG_WRITE_MEMORY_PARAMS *src, finn_bit_pump_for_write *bp, NvBool seri_up) -{ - // Local variables - NV_STATUS status = NV_OK; - uint64_t field_presence_mask; - - // Field bitmasks - field_presence_mask = 0xf; - - // Write field-presence indicators. - if (finn_write_buffer(bp, field_presence_mask, 64)) - { - status = NV_ERR_BUFFER_TOO_SMALL; - FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); - goto exit; - } - - // Statically sized fields - // No range check for src->offset - // Deserialize 8-byte NvU64 object. - if (finn_write_buffer(bp, src->offset, 8 * 8)) - { - status = NV_ERR_BUFFER_TOO_SMALL; - FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); - goto exit; - } - - - // No range check for src->hMemory - // Deserialize 4-byte NvU32 object. - if (finn_write_buffer(bp, src->hMemory, 4 * 8)) - { - status = NV_ERR_BUFFER_TOO_SMALL; - FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); - goto exit; - } - - - // No range check for src->length - // Deserialize 4-byte NvU32 object. - if (finn_write_buffer(bp, src->length, 4 * 8)) - { - status = NV_ERR_BUFFER_TOO_SMALL; - FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); - goto exit; - } - - - // Unbounded fields - // Set data-presence indicator. - if (finn_write_buffer(bp, !!(src->buffer), 1)) - { - status = NV_ERR_BUFFER_TOO_SMALL; - FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); - goto exit; - } - - // Skip if pointer is null. - if (src->buffer) - { - - // Serialize each 1-byte NvU8 element. - for (NvU64 j = 0; j < (src->length); ++j) - { - if (finn_write_buffer(bp, ((NvU8 *) NvP64_VALUE(src->buffer))[j], 1 * 8)) - { - status = NV_ERR_BUFFER_TOO_SMALL; - FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); - goto exit; - } - } - - // Free memory that was allocated during downward deserialization. - if (seri_up && src->buffer) - FINN_FREE(NvP64_VALUE(src->buffer)); - } - - goto exit; // Suppress potential not-used warning -exit: - return status; -} - - -static NV_STATUS Nv83deCtrlDebugWriteMemoryParamsDeserialize(finn_bit_pump_for_read *bp, NV83DE_CTRL_DEBUG_WRITE_MEMORY_PARAMS *dst, NvLength dst_size, NvBool deser_up) -{ - // Local variables - NV_STATUS status = NV_OK; - - // Check that the destination struct fits within the destination buffer - if (sizeof(NV83DE_CTRL_DEBUG_WRITE_MEMORY_PARAMS) > dst_size) - { - status = NV_ERR_BUFFER_TOO_SMALL; - FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); - goto exit; - } - - // Validate the field bitmasks, which must match the expected values for now. - if (finn_read_buffer(bp, 64) != 0xf) - { - status = NV_ERR_LIB_RM_VERSION_MISMATCH; - FINN_ERROR(NV_ERR_LIB_RM_VERSION_MISMATCH); - goto exit; - } - - // Statically sized fields - // Deserialize 8-byte NvU64 object. - dst->offset = (NvU64) finn_read_buffer(bp, 8 * 8); - // No range check for dst->offset - - - // Deserialize 4-byte NvU32 object. - dst->hMemory = (NvU32) finn_read_buffer(bp, 4 * 8); - // No range check for dst->hMemory - - - // Deserialize 4-byte NvU32 object. - dst->length = (NvU32) finn_read_buffer(bp, 4 * 8); - // No range check for dst->length - - - // Unbounded fields - // Skip if data is not present (null pointer). - if (finn_read_buffer(bp, 1)) - { - - // Allocate memory and set pointer when deserializing down. - // (Calling cods is expected to do so when deserializing up.) - if (!deser_up) - { - dst->buffer = FINN_MALLOC((dst->length)); - if (!dst->buffer) - { - status = NV_ERR_NO_MEMORY; - FINN_ERROR(NV_ERR_NO_MEMORY); - goto exit; - } - - FINN_MEMZERO(dst->buffer, (dst->length)); - } - - // Otherwise the pointer must be provided. - else if (!dst->buffer) - { - status = NV_ERR_INVALID_POINTER; - FINN_ERROR(NV_ERR_INVALID_POINTER); - goto exit; - } - - // Deserialize each 1-byte NvU8 element. - for (NvU64 j = 0; j < (dst->length); ++j) - { - ((NvU8 *) NvP64_VALUE(dst->buffer))[j] = (NvU8) finn_read_buffer(bp, 1 * 8); - } - } - else - { - if (!deser_up) - dst->buffer = NULL; - } - -exit: - return status; -} - - -static NV_STATUS Nvb06fCtrlGetEngineCtxDataParamsSerialize(const NVB06F_CTRL_GET_ENGINE_CTX_DATA_PARAMS *src, finn_bit_pump_for_write *bp, NvBool seri_up) -{ - // Local variables - NV_STATUS status = NV_OK; - uint64_t field_presence_mask; - - // Field bitmasks - field_presence_mask = 0x7; - - // Write field-presence indicators. - if (finn_write_buffer(bp, field_presence_mask, 64)) - { - status = NV_ERR_BUFFER_TOO_SMALL; - FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); - goto exit; - } - - // Statically sized fields - // No range check for src->engineID - // Deserialize 4-byte NvU32 object. - if (finn_write_buffer(bp, src->engineID, 4 * 8)) - { - status = NV_ERR_BUFFER_TOO_SMALL; - FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); - goto exit; - } - - - // No range check for src->size - // Deserialize 4-byte NvU32 object. - if (finn_write_buffer(bp, src->size, 4 * 8)) - { - status = NV_ERR_BUFFER_TOO_SMALL; - FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); - goto exit; - } - - - // Unbounded fields - // Set data-presence indicator. - if (finn_write_buffer(bp, !!(src->pEngineCtxBuff), 1)) - { - status = NV_ERR_BUFFER_TOO_SMALL; - FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); - goto exit; - } - - // Skip if pointer is null. - if (src->pEngineCtxBuff) - { - - // Serialize each 1-byte NvU8 element. - for (NvU64 j = 0; j < (src->size); ++j) - { - if (finn_write_buffer(bp, ((NvU8 *) NvP64_VALUE(src->pEngineCtxBuff))[j], 1 * 8)) - { - status = NV_ERR_BUFFER_TOO_SMALL; - FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); - goto exit; - } - } - - // Free memory that was allocated during downward deserialization. - if (seri_up && src->pEngineCtxBuff) - FINN_FREE(NvP64_VALUE(src->pEngineCtxBuff)); - } - - goto exit; // Suppress potential not-used warning -exit: - return status; -} - - -static NV_STATUS Nvb06fCtrlGetEngineCtxDataParamsDeserialize(finn_bit_pump_for_read *bp, NVB06F_CTRL_GET_ENGINE_CTX_DATA_PARAMS *dst, NvLength dst_size, NvBool deser_up) -{ - // Local variables - NV_STATUS status = NV_OK; - - // Check that the destination struct fits within the destination buffer - if (sizeof(NVB06F_CTRL_GET_ENGINE_CTX_DATA_PARAMS) > dst_size) - { - status = NV_ERR_BUFFER_TOO_SMALL; - FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); - goto exit; - } - - // Validate the field bitmasks, which must match the expected values for now. - if (finn_read_buffer(bp, 64) != 0x7) - { - status = NV_ERR_LIB_RM_VERSION_MISMATCH; - FINN_ERROR(NV_ERR_LIB_RM_VERSION_MISMATCH); - goto exit; - } - - // Statically sized fields - // Deserialize 4-byte NvU32 object. - dst->engineID = (NvU32) finn_read_buffer(bp, 4 * 8); - // No range check for dst->engineID - - - // Deserialize 4-byte NvU32 object. - dst->size = (NvU32) finn_read_buffer(bp, 4 * 8); - // No range check for dst->size - - - // Unbounded fields - // Skip if data is not present (null pointer). - if (finn_read_buffer(bp, 1)) - { - - // Allocate memory and set pointer when deserializing down. - // (Calling cods is expected to do so when deserializing up.) - if (!deser_up) - { - dst->pEngineCtxBuff = FINN_MALLOC((dst->size)); - if (!dst->pEngineCtxBuff) - { - status = NV_ERR_NO_MEMORY; - FINN_ERROR(NV_ERR_NO_MEMORY); - goto exit; - } - - FINN_MEMZERO(dst->pEngineCtxBuff, (dst->size)); - } - - // Otherwise the pointer must be provided. - else if (!dst->pEngineCtxBuff) - { - status = NV_ERR_INVALID_POINTER; - FINN_ERROR(NV_ERR_INVALID_POINTER); - goto exit; - } - - // Deserialize each 1-byte NvU8 element. - for (NvU64 j = 0; j < (dst->size); ++j) - { - ((NvU8 *) NvP64_VALUE(dst->pEngineCtxBuff))[j] = (NvU8) finn_read_buffer(bp, 1 * 8); - } - } - else - { - if (!deser_up) - dst->pEngineCtxBuff = NULL; - } - -exit: - return status; -} - - -static NV_STATUS Nvb06fCtrlCmdMigrateEngineCtxDataFinnParamsSerialize(const NVB06F_CTRL_CMD_MIGRATE_ENGINE_CTX_DATA_FINN_PARAMS *src, finn_bit_pump_for_write *bp, NvBool seri_up) -{ - // Local variables - NV_STATUS status = NV_OK; - uint64_t field_presence_mask; - - // Field bitmasks - field_presence_mask = 0x1; - - // Write field-presence indicators. - if (finn_write_buffer(bp, field_presence_mask, 64)) - { - status = NV_ERR_BUFFER_TOO_SMALL; - FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); - goto exit; - } - - // Unbounded fields - status = Nvb06fCtrlGetEngineCtxDataParamsSerialize(&src->params, bp, seri_up); - if (status != NV_OK) - goto exit; - - goto exit; // Suppress potential not-used warning -exit: - return status; -} - - -static NV_STATUS Nvb06fCtrlCmdMigrateEngineCtxDataFinnParamsDeserialize(finn_bit_pump_for_read *bp, NVB06F_CTRL_CMD_MIGRATE_ENGINE_CTX_DATA_FINN_PARAMS *dst, NvLength dst_size, NvBool deser_up) -{ - // Local variables - NV_STATUS status = NV_OK; - - // Check that the destination struct fits within the destination buffer - if (sizeof(NVB06F_CTRL_CMD_MIGRATE_ENGINE_CTX_DATA_FINN_PARAMS) > dst_size) - { - status = NV_ERR_BUFFER_TOO_SMALL; - FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); - goto exit; - } - - // Validate the field bitmasks, which must match the expected values for now. - if (finn_read_buffer(bp, 64) != 0x1) - { - status = NV_ERR_LIB_RM_VERSION_MISMATCH; - FINN_ERROR(NV_ERR_LIB_RM_VERSION_MISMATCH); - goto exit; - } - - // Unbounded fields - status = Nvb06fCtrlGetEngineCtxDataParamsDeserialize(bp, &dst->params, dst_size, deser_up); - if (status != NV_OK) - goto exit; - -exit: - return status; -} - - -static NV_STATUS Nvb06fCtrlSaveEngineCtxDataParamsSerialize(const NVB06F_CTRL_SAVE_ENGINE_CTX_DATA_PARAMS *src, finn_bit_pump_for_write *bp, NvBool seri_up) -{ - // Local variables - NV_STATUS status = NV_OK; - uint64_t field_presence_mask; - - // Field bitmasks - field_presence_mask = 0x7; - - // Write field-presence indicators. - if (finn_write_buffer(bp, field_presence_mask, 64)) - { - status = NV_ERR_BUFFER_TOO_SMALL; - FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); - goto exit; - } - - // Statically sized fields - // No range check for src->engineID - // Deserialize 4-byte NvU32 object. - if (finn_write_buffer(bp, src->engineID, 4 * 8)) - { - status = NV_ERR_BUFFER_TOO_SMALL; - FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); - goto exit; - } - - - // No range check for src->size - // Deserialize 4-byte NvU32 object. - if (finn_write_buffer(bp, src->size, 4 * 8)) - { - status = NV_ERR_BUFFER_TOO_SMALL; - FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); - goto exit; - } - - - for (NvU64 i = 0; i < (NVB06F_CTRL_ENGINE_CTX_BUFFER_SIZE_MAX); ++i) - { - // No range check for src->engineCtxBuff[i] - // Deserialize 1-byte NvU8 object. - if (finn_write_buffer(bp, src->engineCtxBuff[i], 1 * 8)) - { - status = NV_ERR_BUFFER_TOO_SMALL; - FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); - goto exit; - } - } - - - goto exit; // Suppress potential not-used warning -exit: - return status; -} - - -static NV_STATUS Nvb06fCtrlSaveEngineCtxDataParamsDeserialize(finn_bit_pump_for_read *bp, NVB06F_CTRL_SAVE_ENGINE_CTX_DATA_PARAMS *dst, NvLength dst_size, NvBool deser_up) -{ - // Local variables - NV_STATUS status = NV_OK; - - // Check that the destination struct fits within the destination buffer - if (sizeof(NVB06F_CTRL_SAVE_ENGINE_CTX_DATA_PARAMS) > dst_size) - { - status = NV_ERR_BUFFER_TOO_SMALL; - FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); - goto exit; - } - - // Validate the field bitmasks, which must match the expected values for now. - if (finn_read_buffer(bp, 64) != 0x7) - { - status = NV_ERR_LIB_RM_VERSION_MISMATCH; - FINN_ERROR(NV_ERR_LIB_RM_VERSION_MISMATCH); - goto exit; - } - - // Statically sized fields - // Deserialize 4-byte NvU32 object. - dst->engineID = (NvU32) finn_read_buffer(bp, 4 * 8); - // No range check for dst->engineID - - - // Deserialize 4-byte NvU32 object. - dst->size = (NvU32) finn_read_buffer(bp, 4 * 8); - // No range check for dst->size - - - for (NvU64 i = 0; i < (NVB06F_CTRL_ENGINE_CTX_BUFFER_SIZE_MAX); ++i) - { - // Deserialize 1-byte NvU8 object. - dst->engineCtxBuff[i] = (NvU8) finn_read_buffer(bp, 1 * 8); - // No range check for dst->engineCtxBuff[i] - } - - -exit: - return status; -} - - -static NV_STATUS Nvb06fCtrlCmdRestoreEngineCtxDataFinnParamsSerialize(const NVB06F_CTRL_CMD_RESTORE_ENGINE_CTX_DATA_FINN_PARAMS *src, finn_bit_pump_for_write *bp, NvBool seri_up) -{ - // Local variables - NV_STATUS status = NV_OK; - uint64_t field_presence_mask; - - // Field bitmasks - field_presence_mask = 0x1; - - // Write field-presence indicators. - if (finn_write_buffer(bp, field_presence_mask, 64)) - { - status = NV_ERR_BUFFER_TOO_SMALL; - FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); - goto exit; - } - - // Bounded nested fields - status = Nvb06fCtrlSaveEngineCtxDataParamsSerialize(&src->params, bp, seri_up); - if (status != NV_OK) - goto exit; - - goto exit; // Suppress potential not-used warning -exit: - return status; -} - - -static NV_STATUS Nvb06fCtrlCmdRestoreEngineCtxDataFinnParamsDeserialize(finn_bit_pump_for_read *bp, NVB06F_CTRL_CMD_RESTORE_ENGINE_CTX_DATA_FINN_PARAMS *dst, NvLength dst_size, NvBool deser_up) -{ - // Local variables - NV_STATUS status = NV_OK; - - // Check that the destination struct fits within the destination buffer - if (sizeof(NVB06F_CTRL_CMD_RESTORE_ENGINE_CTX_DATA_FINN_PARAMS) > dst_size) - { - status = NV_ERR_BUFFER_TOO_SMALL; - FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); - goto exit; - } - - // Validate the field bitmasks, which must match the expected values for now. - if (finn_read_buffer(bp, 64) != 0x1) - { - status = NV_ERR_LIB_RM_VERSION_MISMATCH; - FINN_ERROR(NV_ERR_LIB_RM_VERSION_MISMATCH); - goto exit; - } - - // Bounded nested fields - status = Nvb06fCtrlSaveEngineCtxDataParamsDeserialize(bp, &dst->params, dst_size, deser_up); - if (status != NV_OK) - goto exit; - -exit: - return status; -} - - diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/interface/rmapi/src/g_finn_rm_api.c nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/interface/rmapi/src/g_finn_rm_api.c --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/interface/rmapi/src/g_finn_rm_api.c 1970-01-01 00:00:00.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/interface/rmapi/src/g_finn_rm_api.c 2024-03-05 22:13:10.000000000 +0000 @@ -0,0 +1,9079 @@ +#include "g_finn_rm_api.h" +#include "ctrl/ctrl0000/ctrl0000nvd.h" +#include "ctrl/ctrl0080/ctrl0080dma.h" +#include "ctrl/ctrl0080/ctrl0080fb.h" +#include "ctrl/ctrl0080/ctrl0080fifo.h" +#include "ctrl/ctrl0080/ctrl0080gpu.h" +#include "ctrl/ctrl0080/ctrl0080gr.h" +#include "ctrl/ctrl0080/ctrl0080host.h" +#include "ctrl/ctrl0080/ctrl0080msenc.h" +#include "ctrl/ctrl2080/ctrl2080bios.h" +#include "ctrl/ctrl2080/ctrl2080ce.h" +#include "ctrl/ctrl2080/ctrl2080gpu.h" +#include "ctrl/ctrl2080/ctrl2080i2c.h" +#include "ctrl/ctrl2080/ctrl2080nvd.h" +#include "ctrl/ctrl2080/ctrl2080perf.h" +#include "ctrl/ctrl2080/ctrl2080rc.h" +#include "ctrl/ctrl2080/ctrl2080ucodefuzzer.h" +#include "ctrl/ctrl208f/ctrl208fgpu.h" +#include "ctrl/ctrl402c.h" +#include "ctrl/ctrl83de/ctrl83dedebug.h" +#include "ctrl/ctrlb06f.h" + +#if defined(NVRM) /* Kernel Mode */ +#include +#include +#include "nvport/nvport.h" +#elif defined(NV_LIBOS) /* LIBOS */ +#include +#include "nvport/nvport.h" +#elif defined(USE_CUSTOM_MALLOC) /* OpenGL */ +#include +#include +#include +extern void *rmapi_import_malloc(size_t size); +extern void rmapi_import_free(void *ptr); +#else /* Default */ +#include +#include +#include +#include +#endif + + +// +// This file was generated with FINN, an NVIDIA coding tool. +// + +/* + * Serialization helper macros. These make field copying code more readable. + * Size is provided explicitly for cross-platform compatibility. + */ + +// Allocate memory. +#if defined(FINN_MALLOC) /* Use override from Makefile */ +#elif defined(NVRM) /* Kernel Mode */ +#define FINN_MALLOC(size) portMemAllocNonPaged(size) + +#elif defined(NV_LIBOS) /* LIBOS */ +#define FINN_MALLOC(size) portMemAllocNonPaged(size) + +#elif defined(USE_CUSTOM_MALLOC) /* OpenGL */ +#define FINN_MALLOC(size) rmapi_import_malloc(size) + +#else /* Default */ +#define FINN_MALLOC(size) malloc(size) +#endif + +// Free allocated memory. +#if defined(FINN_FREE) /* Use override from Makefile */ +#elif defined(NVRM) /* Kernel Mode */ +#define FINN_FREE(buf) portMemFree(buf) + +#elif defined(NV_LIBOS) /* LIBOS */ +#define FINN_FREE(buf) portMemFree(buf) + +#elif defined(USE_CUSTOM_MALLOC) /* OpenGL */ +#define FINN_FREE(buf) rmapi_import_free(buf) + +#else /* Default */ +#define FINN_FREE(buf) free(buf) +#endif + +// Set memory region to all zeroes. +#if defined(FINN_MEMZERO) /* Use override from Makefile */ +#elif defined(NVRM) /* Kernel Mode */ +#define FINN_MEMZERO(buf, size) portMemSet(buf, 0, size) + +#elif defined(NV_LIBOS) /* LIBOS */ +#define FINN_MEMZERO(buf, size) portMemSet(buf, 0, size) + +#elif defined(USE_CUSTOM_MALLOC) /* OpenGL */ +#define FINN_MEMZERO(buf, size) memset(buf, 0, size) + +#else /* Default */ +#define FINN_MEMZERO(buf, size) memset(buf, 0, size) +#endif + +// Copy nonoverlapping memory region. +#if defined(FINN_MEMCPY) /* Use override from Makefile */ +#elif defined(NVRM) /* Kernel Mode */ +#define FINN_MEMCPY(dst, src, size) portMemCopy(dst, size, src, size) + +#elif defined(NV_LIBOS) /* LIBOS */ +#define FINN_MEMCPY(dst, src, size) portMemCopy(dst, size, src, size) + +#elif defined(USE_CUSTOM_MALLOC) /* OpenGL */ +#define FINN_MEMCPY(dst, src, size) memcpy(dst, src, size) + +#else /* Default */ +#define FINN_MEMCPY(dst, src, size) memcpy(dst, src, size) +#endif + +// Report an error. +#if defined(FINN_ERROR) /* Use override from Makefile */ +#else /* Default */ +#define FINN_ERROR(err) /* No-op */ +#endif + + + +// +// The purpose of the bit pump is to ensure 64-bit aligned access to the +// buffer while enabling arbitrary bits to be read/written. +// +typedef struct finn_bit_pump_for_read finn_bit_pump_for_read; + +struct finn_bit_pump_for_read +{ + uint64_t accumulator; // Bits not yet read from the data buffer + const uint64_t *buffer_position; // Next word within data buffer to be read + const uint64_t *end_of_data; // End of data within buffer + uint8_t remaining_bit_count; // Number of bits remaining in the accumulator +}; + + +// +// Initialize bit pump for reading from the buffer. +// +// WARNING: The buffer start is assumed to be 64-bit aligned for optimal performance. +// `sod` (start of data) and `eod` (end of data) must be multiples of 64 bits +// since this logic is optimized for a 64-bit word size. Caller must check both +// `sod` and `eod`. +// +// `eod` points to the 64-bit word after the data (like most C++ `std` iterators). +// +static inline void finn_open_buffer_for_read(finn_bit_pump_for_read *bp, const uint64_t *sod, const uint64_t *eod) +{ + bp->accumulator = 0U; + bp->buffer_position = sod; + bp->end_of_data = eod; + bp->remaining_bit_count = 0U; +} + + +// +// Read the next several bits. +// +// `bit_size` must be in range of 0 to 64 inclusive; no check is made. +// When `bit_size` is zero, an unsupported use-case, it works as expected by +// returning zero without advancing the pointer. +// +static uint64_t finn_read_buffer(finn_bit_pump_for_read *bp, uint8_t bit_size) +{ + // Value to be deserialized and returned + uint64_t value; + + // Boundary crossing + // Accumulator does not have enough to satisfy the request. + if (bit_size > bp->remaining_bit_count) + { + // Number of bits not yet satisfied + bit_size -= bp->remaining_bit_count; + + // Shift the bits we have into place. + value = bp->accumulator; + + // Return zeroes for unsatisfied bits (if any) at end of data. + if (bp->buffer_position >= bp->end_of_data) + bp->accumulator = 0U; + + // Read the next word from the buffer. + else + bp->accumulator = *(bp->buffer_position++); + + // + // This is the special case where we are reading an entire 64-bit word + // without crossing a boundary (when the accumulator is empty). The + // accumulator remains empty on exit. + // + // The bitwise operations in the normal flow do not work in this case. + // Shifts are not well-defined in C when the right operand exceeds the + // size of the left operand. Also, the right operand of the bitwise-and + // would exceed the 64-bit capacity. However, the needed logic is simple. + // + // 64 is the largest legal value for `bit_size`, so `>=` is equivalent to `==`. + // Furthermore, if `bit_size == 64`, then `bp->remaining_bit_count` must + // have been zero when subtracted above. That's how we know that there is + // no boundary crossing. + // + if (bit_size >= 64) + { + // The value is the entire word. + value = bp->accumulator; + + // Discard the consumed data from the accumulator. + bp->accumulator = 0U; + + // Under the assumption that `bit_size` is never larger than 64, + // `bit_size == 64` implies `bp->remaining_bit_count == 0` because + // of the above `bit_size -= bp->remaining_bit_count`. As such, there + // is no need to do `bp->remaining_bit_count = 64U - bit_size`. + + // Done + return value; + } + + // OR in the bits since this was a boundary crossing. + // Shift it over by the number of bits we get from the prior word. + value |= (bp->accumulator + & (((uint64_t) 1U << bit_size) - 1U)) + << bp->remaining_bit_count; + + // Logic below subtracts off the bits consumed in the accumulator. + bp->remaining_bit_count = 64U; + } + + else + { + // The accumulator has enough to satisfy the request. + value = bp->accumulator & (((uint64_t) 1U << bit_size) - 1U); + } + + // Discard the consumed bits from the accumulator. + bp->accumulator >>= bit_size; + + // Keep track of the remaining available bits in the accumulator. + bp->remaining_bit_count -= bit_size; + + // Done + return value; +} + + +typedef struct finn_bit_pump_for_write finn_bit_pump_for_write; +struct finn_bit_pump_for_write +{ + uint64_t accumulator; // Bits not yet written to the data buffer + uint64_t checksum; // Checksum of data + uint64_t *buffer_position; // Next word within the data buffer to be written + const uint64_t *end_of_buffer; // End of buffer (which may be after end of data) + uint8_t empty_bit_count; // Number of available bits in the accumulator +}; + + +// +// Initialize bit pump for writing to the buffer. +// +// In the general case for writing to the bit pump: +// +// WARNING: The buffer start is assumed to be 64-bit aligned for optimal performance. +// `sod` (start of data) and `eob` (end of buffer) must be multiples of 64 bits +// since this logic is optimized for a 64-bit word size. Caller must check both +// `sod` and `eod`. +// +// `eob` points to the 64-bit word after the buffer, an illegal access. +// +// +// Special case to get the serialized size without writing to the buffer: +// Both `sod` and `eob` are null. +// When closed, `bp->buffer_position` contains the byte count. +// +static inline void finn_open_buffer_for_write(finn_bit_pump_for_write *bp, uint64_t *sod, const uint64_t *eob) +{ + bp->accumulator = 0U; + bp->buffer_position = sod; + bp->end_of_buffer = eob; + bp->checksum = 0U; + bp->empty_bit_count = 64U; +} + +// +// Write several bits to the buffer. +// +// `bit_size` must be in range of 1 to 64 inclusive; no check is made. +// `value` must not have more 1 bits than specified by `bit_size`. +// In other words, bits that are left of `bit_size` must be 0s; no check is made. +// +// Return value is nonzero if the end of buffer is reached, an error. +// +// `bp->end_of_buffer` is null to disable writing to the buffer. +// +static int finn_write_buffer(finn_bit_pump_for_write *bp, uint64_t value, uint8_t bit_size) +{ + // Boundary crossing: Accumulator does not have enough to satisfy the request, + if (bit_size >= bp->empty_bit_count) + { + // Number of bits not yet satisfied + bit_size -= bp->empty_bit_count; + + // OR as many bits as will fit into the accumulator. + bp->accumulator |= value << (64U - bp->empty_bit_count); + + // Discard these bits by setting them to 0s. + // CAUTION: `value` may be unchanged when `bp->empty_bit_count` is 64 + // depending on the processor/ISA. + value >>= bp->empty_bit_count; + + // Write the word to the buffer unless writes are disabled. + if (bp->end_of_buffer) + { + *bp->buffer_position = bp->accumulator; + } + + // Advance to the next word in the buffer. + bp->buffer_position++; + + // Update the checksum. + bp->checksum = ((bp->checksum << 1) ^ (bp->checksum & 1U)) ^ bp->accumulator; + + // Re-initialize the accumulator and the bits filled. + bp->accumulator = 0U; + bp->empty_bit_count = 64U; + } + + // OR the data into the accumulator. + // When `bit_size` and `bp->empty_bit_count` are both 64 above, `bit_size` + // is assigned zero, but `value` may be unchanged. Check `bit_size` here so + // that stale `value` is not ORed into the accumulator again. + if (bit_size) + { + bp->accumulator |= (value << (64U - bp->empty_bit_count)); + } + + // Advance the bit count + bp->empty_bit_count -= bit_size; + + // Return nonzero on buffer overrun. + return bp->end_of_buffer && bp->buffer_position >= bp->end_of_buffer && bit_size; +} + + +// +// Close the write buffer and compute the checksum. +// +// Do NOT call this function if `finn_write_buffer` returned nonzero; no check is made. +// +// In the general case for writing to the bit pump: +// +// Postcondition: `bp->buffer_position` points to the word after the end of the data, +// which can be used to calculate the data size in 64-bit words by subtracting from +// `bp->end_of_buffer`. Buffer data at and after this point is set to zeroes. +// +// Special case to get the serialized size without writing to the buffer: +// Postcondition: ``bp->buffer_position` contains the byte count. +// +// All cases: +// Postcondition: `bp->checksum` contains the checksum of words written to the buffer. +// +static inline void finn_close_buffer_for_write(finn_bit_pump_for_write *bp) +{ + uint64_t *p; + + // The accumulator is not empty. + if (bp->empty_bit_count < 64U) + { + // Update the buffer with the last word. + if (bp->end_of_buffer) + { + *bp->buffer_position = bp->accumulator; + } + + // Advance to the next word to get an accurate word count. + bp->buffer_position++; + + // Update the checksum. + bp->checksum = ((bp->checksum << 1U) ^ (bp->checksum & 1U)) ^ bp->accumulator; + } + + // Zero out the rest of the buffer. + for (p = bp->buffer_position; p < bp->end_of_buffer; ++p) + { + *p = 0u; + } +} + + + + + +static NV_STATUS finnSerializeRoot_FINN_RM_API(NvU64 interface, NvU64 message, const char *api, finn_bit_pump_for_write *bp, NvBool seri_up); +static NV_STATUS finnDeserializeRoot_FINN_RM_API(NvU64 interface, NvU64 message, finn_bit_pump_for_read *bp, char *api, NvLength dst_size, NvBool deser_up); +#if (defined(NVRM)) +NvBool finnBadEnum_NV402C_CTRL_I2C_TRANSACTION_TYPE(NV402C_CTRL_I2C_TRANSACTION_TYPE value); +#endif // (defined(NVRM)) + +static NV_STATUS finnSerializeInterface_FINN_GT200_DEBUGGER_DEBUG(NvU64 message, const char *api_intf, finn_bit_pump_for_write *bp, NvBool seri_up); +static NV_STATUS finnDeserializeInterface_FINN_GT200_DEBUGGER_DEBUG(NvU64 message, finn_bit_pump_for_read *bp, FINN_GT200_DEBUGGER_DEBUG *api_intf, NvLength api_size, NvBool deser_up); +static NvU64 finnUnserializedInterfaceSize_FINN_GT200_DEBUGGER_DEBUG(NvU64 message); +static NV_STATUS finnSerializeInterface_FINN_MAXWELL_CHANNEL_GPFIFO_A_GPFIFO(NvU64 message, const char *api_intf, finn_bit_pump_for_write *bp, NvBool seri_up); +static NV_STATUS finnDeserializeInterface_FINN_MAXWELL_CHANNEL_GPFIFO_A_GPFIFO(NvU64 message, finn_bit_pump_for_read *bp, FINN_MAXWELL_CHANNEL_GPFIFO_A_GPFIFO *api_intf, NvLength api_size, NvBool deser_up); +static NvU64 finnUnserializedInterfaceSize_FINN_MAXWELL_CHANNEL_GPFIFO_A_GPFIFO(NvU64 message); +static NV_STATUS finnSerializeInterface_FINN_NV01_DEVICE_0_DMA(NvU64 message, const char *api_intf, finn_bit_pump_for_write *bp, NvBool seri_up); +static NV_STATUS finnDeserializeInterface_FINN_NV01_DEVICE_0_DMA(NvU64 message, finn_bit_pump_for_read *bp, FINN_NV01_DEVICE_0_DMA *api_intf, NvLength api_size, NvBool deser_up); +static NvU64 finnUnserializedInterfaceSize_FINN_NV01_DEVICE_0_DMA(NvU64 message); +static NV_STATUS finnSerializeInterface_FINN_NV01_DEVICE_0_FB(NvU64 message, const char *api_intf, finn_bit_pump_for_write *bp, NvBool seri_up); +static NV_STATUS finnDeserializeInterface_FINN_NV01_DEVICE_0_FB(NvU64 message, finn_bit_pump_for_read *bp, FINN_NV01_DEVICE_0_FB *api_intf, NvLength api_size, NvBool deser_up); +static NvU64 finnUnserializedInterfaceSize_FINN_NV01_DEVICE_0_FB(NvU64 message); +static NV_STATUS finnSerializeInterface_FINN_NV01_DEVICE_0_FIFO(NvU64 message, const char *api_intf, finn_bit_pump_for_write *bp, NvBool seri_up); +static NV_STATUS finnDeserializeInterface_FINN_NV01_DEVICE_0_FIFO(NvU64 message, finn_bit_pump_for_read *bp, FINN_NV01_DEVICE_0_FIFO *api_intf, NvLength api_size, NvBool deser_up); +static NvU64 finnUnserializedInterfaceSize_FINN_NV01_DEVICE_0_FIFO(NvU64 message); +static NV_STATUS finnSerializeInterface_FINN_NV01_DEVICE_0_GPU(NvU64 message, const char *api_intf, finn_bit_pump_for_write *bp, NvBool seri_up); +static NV_STATUS finnDeserializeInterface_FINN_NV01_DEVICE_0_GPU(NvU64 message, finn_bit_pump_for_read *bp, FINN_NV01_DEVICE_0_GPU *api_intf, NvLength api_size, NvBool deser_up); +static NvU64 finnUnserializedInterfaceSize_FINN_NV01_DEVICE_0_GPU(NvU64 message); +static NV_STATUS finnSerializeInterface_FINN_NV01_DEVICE_0_GR(NvU64 message, const char *api_intf, finn_bit_pump_for_write *bp, NvBool seri_up); +static NV_STATUS finnDeserializeInterface_FINN_NV01_DEVICE_0_GR(NvU64 message, finn_bit_pump_for_read *bp, FINN_NV01_DEVICE_0_GR *api_intf, NvLength api_size, NvBool deser_up); +static NvU64 finnUnserializedInterfaceSize_FINN_NV01_DEVICE_0_GR(NvU64 message); +static NV_STATUS finnSerializeInterface_FINN_NV01_DEVICE_0_HOST(NvU64 message, const char *api_intf, finn_bit_pump_for_write *bp, NvBool seri_up); +static NV_STATUS finnDeserializeInterface_FINN_NV01_DEVICE_0_HOST(NvU64 message, finn_bit_pump_for_read *bp, FINN_NV01_DEVICE_0_HOST *api_intf, NvLength api_size, NvBool deser_up); +static NvU64 finnUnserializedInterfaceSize_FINN_NV01_DEVICE_0_HOST(NvU64 message); +static NV_STATUS finnSerializeInterface_FINN_NV01_DEVICE_0_MSENC(NvU64 message, const char *api_intf, finn_bit_pump_for_write *bp, NvBool seri_up); +static NV_STATUS finnDeserializeInterface_FINN_NV01_DEVICE_0_MSENC(NvU64 message, finn_bit_pump_for_read *bp, FINN_NV01_DEVICE_0_MSENC *api_intf, NvLength api_size, NvBool deser_up); +static NvU64 finnUnserializedInterfaceSize_FINN_NV01_DEVICE_0_MSENC(NvU64 message); +static NV_STATUS finnSerializeInterface_FINN_NV01_ROOT_NVD(NvU64 message, const char *api_intf, finn_bit_pump_for_write *bp, NvBool seri_up); +static NV_STATUS finnDeserializeInterface_FINN_NV01_ROOT_NVD(NvU64 message, finn_bit_pump_for_read *bp, FINN_NV01_ROOT_NVD *api_intf, NvLength api_size, NvBool deser_up); +static NvU64 finnUnserializedInterfaceSize_FINN_NV01_ROOT_NVD(NvU64 message); +static NV_STATUS finnSerializeInterface_FINN_NV20_SUBDEVICE_0_BIOS(NvU64 message, const char *api_intf, finn_bit_pump_for_write *bp, NvBool seri_up); +static NV_STATUS finnDeserializeInterface_FINN_NV20_SUBDEVICE_0_BIOS(NvU64 message, finn_bit_pump_for_read *bp, FINN_NV20_SUBDEVICE_0_BIOS *api_intf, NvLength api_size, NvBool deser_up); +static NvU64 finnUnserializedInterfaceSize_FINN_NV20_SUBDEVICE_0_BIOS(NvU64 message); +static NV_STATUS finnSerializeInterface_FINN_NV20_SUBDEVICE_0_CE(NvU64 message, const char *api_intf, finn_bit_pump_for_write *bp, NvBool seri_up); +static NV_STATUS finnDeserializeInterface_FINN_NV20_SUBDEVICE_0_CE(NvU64 message, finn_bit_pump_for_read *bp, FINN_NV20_SUBDEVICE_0_CE *api_intf, NvLength api_size, NvBool deser_up); +static NvU64 finnUnserializedInterfaceSize_FINN_NV20_SUBDEVICE_0_CE(NvU64 message); +static NV_STATUS finnSerializeInterface_FINN_NV20_SUBDEVICE_0_GPU(NvU64 message, const char *api_intf, finn_bit_pump_for_write *bp, NvBool seri_up); +static NV_STATUS finnDeserializeInterface_FINN_NV20_SUBDEVICE_0_GPU(NvU64 message, finn_bit_pump_for_read *bp, FINN_NV20_SUBDEVICE_0_GPU *api_intf, NvLength api_size, NvBool deser_up); +static NvU64 finnUnserializedInterfaceSize_FINN_NV20_SUBDEVICE_0_GPU(NvU64 message); +static NV_STATUS finnSerializeInterface_FINN_NV20_SUBDEVICE_0_I2C(NvU64 message, const char *api_intf, finn_bit_pump_for_write *bp, NvBool seri_up); +static NV_STATUS finnDeserializeInterface_FINN_NV20_SUBDEVICE_0_I2C(NvU64 message, finn_bit_pump_for_read *bp, FINN_NV20_SUBDEVICE_0_I2C *api_intf, NvLength api_size, NvBool deser_up); +static NvU64 finnUnserializedInterfaceSize_FINN_NV20_SUBDEVICE_0_I2C(NvU64 message); +static NV_STATUS finnSerializeInterface_FINN_NV20_SUBDEVICE_0_NVD(NvU64 message, const char *api_intf, finn_bit_pump_for_write *bp, NvBool seri_up); +static NV_STATUS finnDeserializeInterface_FINN_NV20_SUBDEVICE_0_NVD(NvU64 message, finn_bit_pump_for_read *bp, FINN_NV20_SUBDEVICE_0_NVD *api_intf, NvLength api_size, NvBool deser_up); +static NvU64 finnUnserializedInterfaceSize_FINN_NV20_SUBDEVICE_0_NVD(NvU64 message); +static NV_STATUS finnSerializeInterface_FINN_NV20_SUBDEVICE_0_PERF(NvU64 message, const char *api_intf, finn_bit_pump_for_write *bp, NvBool seri_up); +static NV_STATUS finnDeserializeInterface_FINN_NV20_SUBDEVICE_0_PERF(NvU64 message, finn_bit_pump_for_read *bp, FINN_NV20_SUBDEVICE_0_PERF *api_intf, NvLength api_size, NvBool deser_up); +static NvU64 finnUnserializedInterfaceSize_FINN_NV20_SUBDEVICE_0_PERF(NvU64 message); +static NV_STATUS finnSerializeInterface_FINN_NV20_SUBDEVICE_0_RC(NvU64 message, const char *api_intf, finn_bit_pump_for_write *bp, NvBool seri_up); +static NV_STATUS finnDeserializeInterface_FINN_NV20_SUBDEVICE_0_RC(NvU64 message, finn_bit_pump_for_read *bp, FINN_NV20_SUBDEVICE_0_RC *api_intf, NvLength api_size, NvBool deser_up); +static NvU64 finnUnserializedInterfaceSize_FINN_NV20_SUBDEVICE_0_RC(NvU64 message); + +static NV_STATUS finnSerializeInterface_FINN_NV20_SUBDEVICE_DIAG_GPU(NvU64 message, const char *api_intf, finn_bit_pump_for_write *bp, NvBool seri_up); +static NV_STATUS finnDeserializeInterface_FINN_NV20_SUBDEVICE_DIAG_GPU(NvU64 message, finn_bit_pump_for_read *bp, FINN_NV20_SUBDEVICE_DIAG_GPU *api_intf, NvLength api_size, NvBool deser_up); +static NvU64 finnUnserializedInterfaceSize_FINN_NV20_SUBDEVICE_DIAG_GPU(NvU64 message); +static NV_STATUS finnSerializeInterface_FINN_NV40_I2C_I2C(NvU64 message, const char *api_intf, finn_bit_pump_for_write *bp, NvBool seri_up); +static NV_STATUS finnDeserializeInterface_FINN_NV40_I2C_I2C(NvU64 message, finn_bit_pump_for_read *bp, FINN_NV40_I2C_I2C *api_intf, NvLength api_size, NvBool deser_up); +static NvU64 finnUnserializedInterfaceSize_FINN_NV40_I2C_I2C(NvU64 message); +#if (defined(NVRM)) +static NV_STATUS finnSerializeMessage_NV0000_CTRL_NVD_GET_DUMP_PARAMS(const NV0000_CTRL_NVD_GET_DUMP_PARAMS *api, finn_bit_pump_for_write *bp, NvBool seri_up); +static NV_STATUS finnDeserializeMessage_NV0000_CTRL_NVD_GET_DUMP_PARAMS(finn_bit_pump_for_read *bp, NV0000_CTRL_NVD_GET_DUMP_PARAMS *api, NvLength api_size, NvBool deser_up); +static NV_STATUS finnSerializeMessage_NV0080_CTRL_DMA_UPDATE_PDE_2_PARAMS(const NV0080_CTRL_DMA_UPDATE_PDE_2_PARAMS *api, finn_bit_pump_for_write *bp, NvBool seri_up); +static NV_STATUS finnDeserializeMessage_NV0080_CTRL_DMA_UPDATE_PDE_2_PARAMS(finn_bit_pump_for_read *bp, NV0080_CTRL_DMA_UPDATE_PDE_2_PARAMS *api, NvLength api_size, NvBool deser_up); +static NV_STATUS finnSerializeMessage_NV0080_CTRL_FB_GET_CAPS_PARAMS(const NV0080_CTRL_FB_GET_CAPS_PARAMS *api, finn_bit_pump_for_write *bp, NvBool seri_up); +static NV_STATUS finnDeserializeMessage_NV0080_CTRL_FB_GET_CAPS_PARAMS(finn_bit_pump_for_read *bp, NV0080_CTRL_FB_GET_CAPS_PARAMS *api, NvLength api_size, NvBool deser_up); +static NV_STATUS finnSerializeMessage_NV0080_CTRL_FIFO_GET_CAPS_PARAMS(const NV0080_CTRL_FIFO_GET_CAPS_PARAMS *api, finn_bit_pump_for_write *bp, NvBool seri_up); +static NV_STATUS finnDeserializeMessage_NV0080_CTRL_FIFO_GET_CAPS_PARAMS(finn_bit_pump_for_read *bp, NV0080_CTRL_FIFO_GET_CAPS_PARAMS *api, NvLength api_size, NvBool deser_up); +static NV_STATUS finnSerializeMessage_NV0080_CTRL_FIFO_GET_CHANNELLIST_PARAMS(const NV0080_CTRL_FIFO_GET_CHANNELLIST_PARAMS *api, finn_bit_pump_for_write *bp, NvBool seri_up); +static NV_STATUS finnDeserializeMessage_NV0080_CTRL_FIFO_GET_CHANNELLIST_PARAMS(finn_bit_pump_for_read *bp, NV0080_CTRL_FIFO_GET_CHANNELLIST_PARAMS *api, NvLength api_size, NvBool deser_up); +#endif // (defined(NVRM)) + +static NV_STATUS finnSerializeMessage_NV0080_CTRL_FIFO_START_SELECTED_CHANNELS_PARAMS(const NV0080_CTRL_FIFO_START_SELECTED_CHANNELS_PARAMS *api, finn_bit_pump_for_write *bp, NvBool seri_up); +static NV_STATUS finnDeserializeMessage_NV0080_CTRL_FIFO_START_SELECTED_CHANNELS_PARAMS(finn_bit_pump_for_read *bp, NV0080_CTRL_FIFO_START_SELECTED_CHANNELS_PARAMS *api, NvLength api_size, NvBool deser_up); +#if (defined(NVRM)) +static NV_STATUS finnSerializeMessage_NV0080_CTRL_GPU_GET_CLASSLIST_PARAMS(const NV0080_CTRL_GPU_GET_CLASSLIST_PARAMS *api, finn_bit_pump_for_write *bp, NvBool seri_up); +static NV_STATUS finnDeserializeMessage_NV0080_CTRL_GPU_GET_CLASSLIST_PARAMS(finn_bit_pump_for_read *bp, NV0080_CTRL_GPU_GET_CLASSLIST_PARAMS *api, NvLength api_size, NvBool deser_up); +static NV_STATUS finnSerializeMessage_NV0080_CTRL_GR_GET_CAPS_PARAMS(const NV0080_CTRL_GR_GET_CAPS_PARAMS *api, finn_bit_pump_for_write *bp, NvBool seri_up); +static NV_STATUS finnDeserializeMessage_NV0080_CTRL_GR_GET_CAPS_PARAMS(finn_bit_pump_for_read *bp, NV0080_CTRL_GR_GET_CAPS_PARAMS *api, NvLength api_size, NvBool deser_up); +static NV_STATUS finnSerializeMessage_NV0080_CTRL_HOST_GET_CAPS_PARAMS(const NV0080_CTRL_HOST_GET_CAPS_PARAMS *api, finn_bit_pump_for_write *bp, NvBool seri_up); +static NV_STATUS finnDeserializeMessage_NV0080_CTRL_HOST_GET_CAPS_PARAMS(finn_bit_pump_for_read *bp, NV0080_CTRL_HOST_GET_CAPS_PARAMS *api, NvLength api_size, NvBool deser_up); +static NV_STATUS finnSerializeMessage_NV0080_CTRL_MSENC_GET_CAPS_PARAMS(const NV0080_CTRL_MSENC_GET_CAPS_PARAMS *api, finn_bit_pump_for_write *bp, NvBool seri_up); +static NV_STATUS finnDeserializeMessage_NV0080_CTRL_MSENC_GET_CAPS_PARAMS(finn_bit_pump_for_read *bp, NV0080_CTRL_MSENC_GET_CAPS_PARAMS *api, NvLength api_size, NvBool deser_up); +static NV_STATUS finnSerializeMessage_NV2080_CTRL_BIOS_GET_NBSI_OBJ_PARAMS(const NV2080_CTRL_BIOS_GET_NBSI_OBJ_PARAMS *api, finn_bit_pump_for_write *bp, NvBool seri_up); +static NV_STATUS finnDeserializeMessage_NV2080_CTRL_BIOS_GET_NBSI_OBJ_PARAMS(finn_bit_pump_for_read *bp, NV2080_CTRL_BIOS_GET_NBSI_OBJ_PARAMS *api, NvLength api_size, NvBool deser_up); +static NV_STATUS finnSerializeMessage_NV2080_CTRL_CE_GET_CAPS_PARAMS(const NV2080_CTRL_CE_GET_CAPS_PARAMS *api, finn_bit_pump_for_write *bp, NvBool seri_up); +static NV_STATUS finnDeserializeMessage_NV2080_CTRL_CE_GET_CAPS_PARAMS(finn_bit_pump_for_read *bp, NV2080_CTRL_CE_GET_CAPS_PARAMS *api, NvLength api_size, NvBool deser_up); +static NV_STATUS finnSerializeMessage_NV2080_CTRL_GPU_GET_ENGINES_PARAMS(const NV2080_CTRL_GPU_GET_ENGINES_PARAMS *api, finn_bit_pump_for_write *bp, NvBool seri_up); +static NV_STATUS finnDeserializeMessage_NV2080_CTRL_GPU_GET_ENGINES_PARAMS(finn_bit_pump_for_read *bp, NV2080_CTRL_GPU_GET_ENGINES_PARAMS *api, NvLength api_size, NvBool deser_up); +static NV_STATUS finnSerializeMessage_NV2080_CTRL_GPU_GET_ENGINE_CLASSLIST_PARAMS(const NV2080_CTRL_GPU_GET_ENGINE_CLASSLIST_PARAMS *api, finn_bit_pump_for_write *bp, NvBool seri_up); +static NV_STATUS finnDeserializeMessage_NV2080_CTRL_GPU_GET_ENGINE_CLASSLIST_PARAMS(finn_bit_pump_for_read *bp, NV2080_CTRL_GPU_GET_ENGINE_CLASSLIST_PARAMS *api, NvLength api_size, NvBool deser_up); +static NV_STATUS finnSerializeMessage_NV2080_CTRL_I2C_ACCESS_PARAMS(const NV2080_CTRL_I2C_ACCESS_PARAMS *api, finn_bit_pump_for_write *bp, NvBool seri_up); +static NV_STATUS finnDeserializeMessage_NV2080_CTRL_I2C_ACCESS_PARAMS(finn_bit_pump_for_read *bp, NV2080_CTRL_I2C_ACCESS_PARAMS *api, NvLength api_size, NvBool deser_up); +static NV_STATUS finnSerializeMessage_NV2080_CTRL_NVD_GET_DUMP_PARAMS(const NV2080_CTRL_NVD_GET_DUMP_PARAMS *api, finn_bit_pump_for_write *bp, NvBool seri_up); +static NV_STATUS finnDeserializeMessage_NV2080_CTRL_NVD_GET_DUMP_PARAMS(finn_bit_pump_for_read *bp, NV2080_CTRL_NVD_GET_DUMP_PARAMS *api, NvLength api_size, NvBool deser_up); +static NV_STATUS finnSerializeMessage_NV2080_CTRL_RC_READ_VIRTUAL_MEM_PARAMS(const NV2080_CTRL_RC_READ_VIRTUAL_MEM_PARAMS *api, finn_bit_pump_for_write *bp, NvBool seri_up); +static NV_STATUS finnDeserializeMessage_NV2080_CTRL_RC_READ_VIRTUAL_MEM_PARAMS(finn_bit_pump_for_read *bp, NV2080_CTRL_RC_READ_VIRTUAL_MEM_PARAMS *api, NvLength api_size, NvBool deser_up); +#endif // (defined(NVRM)) + +#if (defined(NVRM)) +static NV_STATUS finnSerializeMessage_NV402C_CTRL_I2C_INDEXED_PARAMS(const NV402C_CTRL_I2C_INDEXED_PARAMS *api, finn_bit_pump_for_write *bp, NvBool seri_up); +static NV_STATUS finnDeserializeMessage_NV402C_CTRL_I2C_INDEXED_PARAMS(finn_bit_pump_for_read *bp, NV402C_CTRL_I2C_INDEXED_PARAMS *api, NvLength api_size, NvBool deser_up); +static NV_STATUS finnSerializeMessage_NV402C_CTRL_I2C_TRANSACTION_PARAMS(const NV402C_CTRL_I2C_TRANSACTION_PARAMS *api, finn_bit_pump_for_write *bp, NvBool seri_up); +static NV_STATUS finnDeserializeMessage_NV402C_CTRL_I2C_TRANSACTION_PARAMS(finn_bit_pump_for_read *bp, NV402C_CTRL_I2C_TRANSACTION_PARAMS *api, NvLength api_size, NvBool deser_up); +static NV_STATUS finnSerializeMessage_NV83DE_CTRL_DEBUG_READ_MEMORY_PARAMS(const NV83DE_CTRL_DEBUG_READ_MEMORY_PARAMS *api, finn_bit_pump_for_write *bp, NvBool seri_up); +static NV_STATUS finnDeserializeMessage_NV83DE_CTRL_DEBUG_READ_MEMORY_PARAMS(finn_bit_pump_for_read *bp, NV83DE_CTRL_DEBUG_READ_MEMORY_PARAMS *api, NvLength api_size, NvBool deser_up); +static NV_STATUS finnSerializeMessage_NV83DE_CTRL_DEBUG_WRITE_MEMORY_PARAMS(const NV83DE_CTRL_DEBUG_WRITE_MEMORY_PARAMS *api, finn_bit_pump_for_write *bp, NvBool seri_up); +static NV_STATUS finnDeserializeMessage_NV83DE_CTRL_DEBUG_WRITE_MEMORY_PARAMS(finn_bit_pump_for_read *bp, NV83DE_CTRL_DEBUG_WRITE_MEMORY_PARAMS *api, NvLength api_size, NvBool deser_up); +static NV_STATUS finnSerializeMessage_NVB06F_CTRL_CMD_RESTORE_ENGINE_CTX_DATA_FINN_PARAMS(const NVB06F_CTRL_CMD_RESTORE_ENGINE_CTX_DATA_FINN_PARAMS *api, finn_bit_pump_for_write *bp, NvBool seri_up); +static NV_STATUS finnDeserializeMessage_NVB06F_CTRL_CMD_RESTORE_ENGINE_CTX_DATA_FINN_PARAMS(finn_bit_pump_for_read *bp, NVB06F_CTRL_CMD_RESTORE_ENGINE_CTX_DATA_FINN_PARAMS *api, NvLength api_size, NvBool deser_up); +static NV_STATUS finnSerializeMessage_NVB06F_CTRL_GET_ENGINE_CTX_DATA_PARAMS(const NVB06F_CTRL_GET_ENGINE_CTX_DATA_PARAMS *api, finn_bit_pump_for_write *bp, NvBool seri_up); +static NV_STATUS finnDeserializeMessage_NVB06F_CTRL_GET_ENGINE_CTX_DATA_PARAMS(finn_bit_pump_for_read *bp, NVB06F_CTRL_GET_ENGINE_CTX_DATA_PARAMS *api, NvLength api_size, NvBool deser_up); +static NV_STATUS finnSerializeMessage_NVB06F_CTRL_SAVE_ENGINE_CTX_DATA_PARAMS(const NVB06F_CTRL_SAVE_ENGINE_CTX_DATA_PARAMS *api, finn_bit_pump_for_write *bp, NvBool seri_up); +static NV_STATUS finnDeserializeMessage_NVB06F_CTRL_SAVE_ENGINE_CTX_DATA_PARAMS(finn_bit_pump_for_read *bp, NVB06F_CTRL_SAVE_ENGINE_CTX_DATA_PARAMS *api, NvLength api_size, NvBool deser_up); +static NV_STATUS finnSerializeRecord_NV0080_CTRL_DMA_UPDATE_PDE_2_PAGE_TABLE_PARAMS(const NV0080_CTRL_DMA_UPDATE_PDE_2_PAGE_TABLE_PARAMS *api, finn_bit_pump_for_write *bp, NvBool seri_up); +static NV_STATUS finnDeserializeRecord_NV0080_CTRL_DMA_UPDATE_PDE_2_PAGE_TABLE_PARAMS(finn_bit_pump_for_read *bp, NV0080_CTRL_DMA_UPDATE_PDE_2_PAGE_TABLE_PARAMS *api, NvLength api_size, NvBool deser_up); +#endif // (defined(NVRM)) + +static NV_STATUS finnSerializeRecord_NV0080_CTRL_FIFO_CHANNEL(const NV0080_CTRL_FIFO_CHANNEL *api, finn_bit_pump_for_write *bp, NvBool seri_up); +static NV_STATUS finnDeserializeRecord_NV0080_CTRL_FIFO_CHANNEL(finn_bit_pump_for_read *bp, NV0080_CTRL_FIFO_CHANNEL *api, NvLength api_size, NvBool deser_up); +#if (defined(NVRM)) +static NV_STATUS finnSerializeRecord_NV2080_CTRL_GPUMON_SAMPLES(const NV2080_CTRL_GPUMON_SAMPLES *api, finn_bit_pump_for_write *bp, NvBool seri_up); +static NV_STATUS finnDeserializeRecord_NV2080_CTRL_GPUMON_SAMPLES(finn_bit_pump_for_read *bp, NV2080_CTRL_GPUMON_SAMPLES *api, NvLength api_size, NvBool deser_up); +#endif // (defined(NVRM)) + +#if (defined(NVRM)) +static NV_STATUS finnSerializeRecord_NV402C_CTRL_I2C_TRANSACTION_DATA_I2C_BLOCK_RW(const NV402C_CTRL_I2C_TRANSACTION_DATA_I2C_BLOCK_RW *api, finn_bit_pump_for_write *bp, NvBool seri_up); +static NV_STATUS finnDeserializeRecord_NV402C_CTRL_I2C_TRANSACTION_DATA_I2C_BLOCK_RW(finn_bit_pump_for_read *bp, NV402C_CTRL_I2C_TRANSACTION_DATA_I2C_BLOCK_RW *api, NvLength api_size, NvBool deser_up); +static NV_STATUS finnSerializeRecord_NV402C_CTRL_I2C_TRANSACTION_DATA_I2C_BUFFER_RW(const NV402C_CTRL_I2C_TRANSACTION_DATA_I2C_BUFFER_RW *api, finn_bit_pump_for_write *bp, NvBool seri_up); +static NV_STATUS finnDeserializeRecord_NV402C_CTRL_I2C_TRANSACTION_DATA_I2C_BUFFER_RW(finn_bit_pump_for_read *bp, NV402C_CTRL_I2C_TRANSACTION_DATA_I2C_BUFFER_RW *api, NvLength api_size, NvBool deser_up); +static NV_STATUS finnSerializeRecord_NV402C_CTRL_I2C_TRANSACTION_DATA_I2C_BYTE_RW(const NV402C_CTRL_I2C_TRANSACTION_DATA_I2C_BYTE_RW *api, finn_bit_pump_for_write *bp, NvBool seri_up); +static NV_STATUS finnDeserializeRecord_NV402C_CTRL_I2C_TRANSACTION_DATA_I2C_BYTE_RW(finn_bit_pump_for_read *bp, NV402C_CTRL_I2C_TRANSACTION_DATA_I2C_BYTE_RW *api, NvLength api_size, NvBool deser_up); +static NV_STATUS finnSerializeRecord_NV402C_CTRL_I2C_TRANSACTION_DATA_READ_EDID_DDC(const NV402C_CTRL_I2C_TRANSACTION_DATA_READ_EDID_DDC *api, finn_bit_pump_for_write *bp, NvBool seri_up); +static NV_STATUS finnDeserializeRecord_NV402C_CTRL_I2C_TRANSACTION_DATA_READ_EDID_DDC(finn_bit_pump_for_read *bp, NV402C_CTRL_I2C_TRANSACTION_DATA_READ_EDID_DDC *api, NvLength api_size, NvBool deser_up); +static NV_STATUS finnSerializeRecord_NV402C_CTRL_I2C_TRANSACTION_DATA_SMBUS_BLOCK_PROCESS_CALL(const NV402C_CTRL_I2C_TRANSACTION_DATA_SMBUS_BLOCK_PROCESS_CALL *api, finn_bit_pump_for_write *bp, NvBool seri_up); +static NV_STATUS finnDeserializeRecord_NV402C_CTRL_I2C_TRANSACTION_DATA_SMBUS_BLOCK_PROCESS_CALL(finn_bit_pump_for_read *bp, NV402C_CTRL_I2C_TRANSACTION_DATA_SMBUS_BLOCK_PROCESS_CALL *api, NvLength api_size, NvBool deser_up); +static NV_STATUS finnSerializeRecord_NV402C_CTRL_I2C_TRANSACTION_DATA_SMBUS_BLOCK_RW(const NV402C_CTRL_I2C_TRANSACTION_DATA_SMBUS_BLOCK_RW *api, finn_bit_pump_for_write *bp, NvBool seri_up); +static NV_STATUS finnDeserializeRecord_NV402C_CTRL_I2C_TRANSACTION_DATA_SMBUS_BLOCK_RW(finn_bit_pump_for_read *bp, NV402C_CTRL_I2C_TRANSACTION_DATA_SMBUS_BLOCK_RW *api, NvLength api_size, NvBool deser_up); +static NV_STATUS finnSerializeRecord_NV402C_CTRL_I2C_TRANSACTION_DATA_SMBUS_BYTE_RW(const NV402C_CTRL_I2C_TRANSACTION_DATA_SMBUS_BYTE_RW *api, finn_bit_pump_for_write *bp, NvBool seri_up); +static NV_STATUS finnDeserializeRecord_NV402C_CTRL_I2C_TRANSACTION_DATA_SMBUS_BYTE_RW(finn_bit_pump_for_read *bp, NV402C_CTRL_I2C_TRANSACTION_DATA_SMBUS_BYTE_RW *api, NvLength api_size, NvBool deser_up); +static NV_STATUS finnSerializeRecord_NV402C_CTRL_I2C_TRANSACTION_DATA_SMBUS_MULTIBYTE_REGISTER_BLOCK_RW(const NV402C_CTRL_I2C_TRANSACTION_DATA_SMBUS_MULTIBYTE_REGISTER_BLOCK_RW *api, finn_bit_pump_for_write *bp, NvBool seri_up); +static NV_STATUS finnDeserializeRecord_NV402C_CTRL_I2C_TRANSACTION_DATA_SMBUS_MULTIBYTE_REGISTER_BLOCK_RW(finn_bit_pump_for_read *bp, NV402C_CTRL_I2C_TRANSACTION_DATA_SMBUS_MULTIBYTE_REGISTER_BLOCK_RW *api, NvLength api_size, NvBool deser_up); +static NV_STATUS finnSerializeRecord_NV402C_CTRL_I2C_TRANSACTION_DATA_SMBUS_PROCESS_CALL(const NV402C_CTRL_I2C_TRANSACTION_DATA_SMBUS_PROCESS_CALL *api, finn_bit_pump_for_write *bp, NvBool seri_up); +static NV_STATUS finnDeserializeRecord_NV402C_CTRL_I2C_TRANSACTION_DATA_SMBUS_PROCESS_CALL(finn_bit_pump_for_read *bp, NV402C_CTRL_I2C_TRANSACTION_DATA_SMBUS_PROCESS_CALL *api, NvLength api_size, NvBool deser_up); +static NV_STATUS finnSerializeRecord_NV402C_CTRL_I2C_TRANSACTION_DATA_SMBUS_QUICK_RW(const NV402C_CTRL_I2C_TRANSACTION_DATA_SMBUS_QUICK_RW *api, finn_bit_pump_for_write *bp, NvBool seri_up); +static NV_STATUS finnDeserializeRecord_NV402C_CTRL_I2C_TRANSACTION_DATA_SMBUS_QUICK_RW(finn_bit_pump_for_read *bp, NV402C_CTRL_I2C_TRANSACTION_DATA_SMBUS_QUICK_RW *api, NvLength api_size, NvBool deser_up); +static NV_STATUS finnSerializeRecord_NV402C_CTRL_I2C_TRANSACTION_DATA_SMBUS_WORD_RW(const NV402C_CTRL_I2C_TRANSACTION_DATA_SMBUS_WORD_RW *api, finn_bit_pump_for_write *bp, NvBool seri_up); +static NV_STATUS finnDeserializeRecord_NV402C_CTRL_I2C_TRANSACTION_DATA_SMBUS_WORD_RW(finn_bit_pump_for_read *bp, NV402C_CTRL_I2C_TRANSACTION_DATA_SMBUS_WORD_RW *api, NvLength api_size, NvBool deser_up); +#endif // (defined(NVRM)) + +#if (defined(NVRM)) +static NV_STATUS finnSerializeUnion_NV402C_CTRL_I2C_TRANSACTION_DATA(const NV402C_CTRL_I2C_TRANSACTION_DATA *api, finn_bit_pump_for_write *bp, NvBool seri_up, NV402C_CTRL_I2C_TRANSACTION_TYPE transType); +static NV_STATUS finnDeserializeUnion_NV402C_CTRL_I2C_TRANSACTION_DATA(finn_bit_pump_for_read *bp, NV402C_CTRL_I2C_TRANSACTION_DATA *api, NvLength dst_size, NvBool deser_up, NV402C_CTRL_I2C_TRANSACTION_TYPE transType); + +#endif // (defined(NVRM)) + +// Serialize this API. +NV_STATUS finnSerializeInternal_FINN_RM_API(NvU64 interface, NvU64 message, const char *api, char *dst, NvLength dst_size, NvBool seri_up) +{ + // Header + FINN_RM_API *header; + + // Buffer end + // `char` is the C-standrd unit of measure for `sizeof`. + const char *dst_end; + + // Bit pump is used to fill the buffer with serialized data. + finn_bit_pump_for_write bp; + + // Error code returned from serialization + NV_STATUS error_code; + + // Input validation + // Null pointers are not permitted. + // Buffer must begin on an 8-byte boundary. + if (!api || !dst || !dst_size || (uintptr_t) dst & 0x7u) + { + FINN_ERROR(NV_ERR_INVALID_ARGUMENT); + return NV_ERR_INVALID_ARGUMENT; + } + + // Header is at the start of the buffer. + header = (FINN_RM_API *) dst; + + // Buffer must end on an 8-byte boundary, so round down. + dst_end = (const char *) ((uintptr_t) (dst + dst_size) & ~ (uintptr_t) 0x7); + + // Set header data. + header->version = FINN_SERIALIZATION_VERSION; + header->payloadSize = 0; // Zero until completed successfully + header->interface = interface; + header->message = message; + + // Advance past header. + dst += sizeof(FINN_RM_API); + + // Open the bit pump. + finn_open_buffer_for_write(&bp, (uint64_t *) dst, (const uint64_t *) dst_end); + + // Call the serializer. + error_code = finnSerializeRoot_FINN_RM_API(interface, message, api, &bp, seri_up); + + // Close the bit pump. + finn_close_buffer_for_write(&bp); + + // Payload size in bytes + if (error_code == NV_OK) + header->payloadSize = (NvU64) (((const char *) bp.buffer_position) - ((const char *) header)); + + // Done + return error_code; +} + +// Serialize this API to the bit pump. +static NV_STATUS finnSerializeRoot_FINN_RM_API(NvU64 interface, NvU64 message, const char *api, finn_bit_pump_for_write *bp, NvBool seri_up) +{ + // Serialize the specified interface. + switch (interface) + { + case FINN_INTERFACE_ID(FINN_NV01_ROOT_NVD): + return finnSerializeInterface_FINN_NV01_ROOT_NVD(message, api, bp, seri_up); + case FINN_INTERFACE_ID(FINN_NV01_DEVICE_0_DMA): + return finnSerializeInterface_FINN_NV01_DEVICE_0_DMA(message, api, bp, seri_up); + case FINN_INTERFACE_ID(FINN_NV01_DEVICE_0_FB): + return finnSerializeInterface_FINN_NV01_DEVICE_0_FB(message, api, bp, seri_up); + case FINN_INTERFACE_ID(FINN_NV01_DEVICE_0_FIFO): + return finnSerializeInterface_FINN_NV01_DEVICE_0_FIFO(message, api, bp, seri_up); + case FINN_INTERFACE_ID(FINN_NV01_DEVICE_0_GPU): + return finnSerializeInterface_FINN_NV01_DEVICE_0_GPU(message, api, bp, seri_up); + case FINN_INTERFACE_ID(FINN_NV01_DEVICE_0_GR): + return finnSerializeInterface_FINN_NV01_DEVICE_0_GR(message, api, bp, seri_up); + case FINN_INTERFACE_ID(FINN_NV01_DEVICE_0_HOST): + return finnSerializeInterface_FINN_NV01_DEVICE_0_HOST(message, api, bp, seri_up); + case FINN_INTERFACE_ID(FINN_NV01_DEVICE_0_MSENC): + return finnSerializeInterface_FINN_NV01_DEVICE_0_MSENC(message, api, bp, seri_up); + case FINN_INTERFACE_ID(FINN_NV20_SUBDEVICE_0_BIOS): + return finnSerializeInterface_FINN_NV20_SUBDEVICE_0_BIOS(message, api, bp, seri_up); + case FINN_INTERFACE_ID(FINN_NV20_SUBDEVICE_0_CE): + return finnSerializeInterface_FINN_NV20_SUBDEVICE_0_CE(message, api, bp, seri_up); + case FINN_INTERFACE_ID(FINN_NV20_SUBDEVICE_0_GPU): + return finnSerializeInterface_FINN_NV20_SUBDEVICE_0_GPU(message, api, bp, seri_up); + case FINN_INTERFACE_ID(FINN_NV20_SUBDEVICE_0_I2C): + return finnSerializeInterface_FINN_NV20_SUBDEVICE_0_I2C(message, api, bp, seri_up); + case FINN_INTERFACE_ID(FINN_NV20_SUBDEVICE_0_NVD): + return finnSerializeInterface_FINN_NV20_SUBDEVICE_0_NVD(message, api, bp, seri_up); + case FINN_INTERFACE_ID(FINN_NV20_SUBDEVICE_0_PERF): + return finnSerializeInterface_FINN_NV20_SUBDEVICE_0_PERF(message, api, bp, seri_up); + case FINN_INTERFACE_ID(FINN_NV20_SUBDEVICE_0_RC): + return finnSerializeInterface_FINN_NV20_SUBDEVICE_0_RC(message, api, bp, seri_up); + + case FINN_INTERFACE_ID(FINN_NV20_SUBDEVICE_DIAG_GPU): + return finnSerializeInterface_FINN_NV20_SUBDEVICE_DIAG_GPU(message, api, bp, seri_up); + case FINN_INTERFACE_ID(FINN_NV40_I2C_I2C): + return finnSerializeInterface_FINN_NV40_I2C_I2C(message, api, bp, seri_up); + case FINN_INTERFACE_ID(FINN_GT200_DEBUGGER_DEBUG): + return finnSerializeInterface_FINN_GT200_DEBUGGER_DEBUG(message, api, bp, seri_up); + case FINN_INTERFACE_ID(FINN_MAXWELL_CHANNEL_GPFIFO_A_GPFIFO): + return finnSerializeInterface_FINN_MAXWELL_CHANNEL_GPFIFO_A_GPFIFO(message, api, bp, seri_up); + + // Everything else is unsupported. + default: + { + FINN_ERROR(NV_ERR_NOT_SUPPORTED); + return NV_ERR_NOT_SUPPORTED; + } + } +} // end finnSerializeRoot_FINN_RM_API + + +// Deserialize this API. +NV_STATUS finnDeserializeInternal_FINN_RM_API(const char *src, NvLength src_size, char *api, NvLength api_size, NvBool deser_up) +{ + // Header + const FINN_RM_API *header; + + // End of data + const char *src_max; + + // Bit pump is used to read the serialized data. + finn_bit_pump_for_read bp; + + // Error code + NV_STATUS status; + + // Input validation + // Null pointers are not permitted. + // Buffer must begin on an 8-byte boundary. + if (!src || !src_size || !api || !api_size || (uintptr_t) src & 0x7u) + { + FINN_ERROR(NV_ERR_INVALID_ARGUMENT); + return NV_ERR_INVALID_ARGUMENT; + } + + // Header data comes first. + header = (const FINN_RM_API *) src; + + // Check the version. + if (header->version != FINN_SERIALIZATION_VERSION) + { + FINN_ERROR(NV_ERR_LIB_RM_VERSION_MISMATCH); + return NV_ERR_LIB_RM_VERSION_MISMATCH; + } + + // Set src_max for buffer bounds checking. + src_max = src + src_size; + + // Check that source buffer is large enough. + if (sizeof(FINN_RM_API) > src_size || + header->payloadSize > src_size || + header->payloadSize < sizeof(FINN_RM_API)) + { + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + return NV_ERR_BUFFER_TOO_SMALL; + } + + // Open the bit punp, skipping past the header. + finn_open_buffer_for_read(&bp, (const uint64_t *) (src + sizeof(FINN_RM_API)), (const uint64_t *) (src_max)); + + // Dispatch to interface-specific routine + status = finnDeserializeRoot_FINN_RM_API(header->interface, header->message, &bp, api, api_size, deser_up); + + // Nothing more to do if there was an error. + if (status != NV_OK) + return status; + + // Check that the declared size matches the serialization outcome. + if (header->payloadSize != (NvU64) (((const char *) bp.buffer_position) - ((const char *) header))) + { + FINN_ERROR(NV_ERR_INVALID_ARGUMENT); + return NV_ERR_INVALID_ARGUMENT; + } + + // All good + return NV_OK; +} + + +// Deserialize this API from the bit pump. +static NV_STATUS finnDeserializeRoot_FINN_RM_API(NvU64 interface, NvU64 message, finn_bit_pump_for_read *bp, char *api, NvLength api_size, NvBool deser_up) +{ + // Deserialize the specified interface. + switch (interface) + { + case FINN_INTERFACE_ID(FINN_NV01_ROOT_NVD): + return finnDeserializeInterface_FINN_NV01_ROOT_NVD(message, bp, (FINN_NV01_ROOT_NVD *) api, api_size, deser_up); + case FINN_INTERFACE_ID(FINN_NV01_DEVICE_0_DMA): + return finnDeserializeInterface_FINN_NV01_DEVICE_0_DMA(message, bp, (FINN_NV01_DEVICE_0_DMA *) api, api_size, deser_up); + case FINN_INTERFACE_ID(FINN_NV01_DEVICE_0_FB): + return finnDeserializeInterface_FINN_NV01_DEVICE_0_FB(message, bp, (FINN_NV01_DEVICE_0_FB *) api, api_size, deser_up); + case FINN_INTERFACE_ID(FINN_NV01_DEVICE_0_FIFO): + return finnDeserializeInterface_FINN_NV01_DEVICE_0_FIFO(message, bp, (FINN_NV01_DEVICE_0_FIFO *) api, api_size, deser_up); + case FINN_INTERFACE_ID(FINN_NV01_DEVICE_0_GPU): + return finnDeserializeInterface_FINN_NV01_DEVICE_0_GPU(message, bp, (FINN_NV01_DEVICE_0_GPU *) api, api_size, deser_up); + case FINN_INTERFACE_ID(FINN_NV01_DEVICE_0_GR): + return finnDeserializeInterface_FINN_NV01_DEVICE_0_GR(message, bp, (FINN_NV01_DEVICE_0_GR *) api, api_size, deser_up); + case FINN_INTERFACE_ID(FINN_NV01_DEVICE_0_HOST): + return finnDeserializeInterface_FINN_NV01_DEVICE_0_HOST(message, bp, (FINN_NV01_DEVICE_0_HOST *) api, api_size, deser_up); + case FINN_INTERFACE_ID(FINN_NV01_DEVICE_0_MSENC): + return finnDeserializeInterface_FINN_NV01_DEVICE_0_MSENC(message, bp, (FINN_NV01_DEVICE_0_MSENC *) api, api_size, deser_up); + case FINN_INTERFACE_ID(FINN_NV20_SUBDEVICE_0_BIOS): + return finnDeserializeInterface_FINN_NV20_SUBDEVICE_0_BIOS(message, bp, (FINN_NV20_SUBDEVICE_0_BIOS *) api, api_size, deser_up); + case FINN_INTERFACE_ID(FINN_NV20_SUBDEVICE_0_CE): + return finnDeserializeInterface_FINN_NV20_SUBDEVICE_0_CE(message, bp, (FINN_NV20_SUBDEVICE_0_CE *) api, api_size, deser_up); + case FINN_INTERFACE_ID(FINN_NV20_SUBDEVICE_0_GPU): + return finnDeserializeInterface_FINN_NV20_SUBDEVICE_0_GPU(message, bp, (FINN_NV20_SUBDEVICE_0_GPU *) api, api_size, deser_up); + case FINN_INTERFACE_ID(FINN_NV20_SUBDEVICE_0_I2C): + return finnDeserializeInterface_FINN_NV20_SUBDEVICE_0_I2C(message, bp, (FINN_NV20_SUBDEVICE_0_I2C *) api, api_size, deser_up); + case FINN_INTERFACE_ID(FINN_NV20_SUBDEVICE_0_NVD): + return finnDeserializeInterface_FINN_NV20_SUBDEVICE_0_NVD(message, bp, (FINN_NV20_SUBDEVICE_0_NVD *) api, api_size, deser_up); + case FINN_INTERFACE_ID(FINN_NV20_SUBDEVICE_0_PERF): + return finnDeserializeInterface_FINN_NV20_SUBDEVICE_0_PERF(message, bp, (FINN_NV20_SUBDEVICE_0_PERF *) api, api_size, deser_up); + case FINN_INTERFACE_ID(FINN_NV20_SUBDEVICE_0_RC): + return finnDeserializeInterface_FINN_NV20_SUBDEVICE_0_RC(message, bp, (FINN_NV20_SUBDEVICE_0_RC *) api, api_size, deser_up); + + case FINN_INTERFACE_ID(FINN_NV20_SUBDEVICE_DIAG_GPU): + return finnDeserializeInterface_FINN_NV20_SUBDEVICE_DIAG_GPU(message, bp, (FINN_NV20_SUBDEVICE_DIAG_GPU *) api, api_size, deser_up); + case FINN_INTERFACE_ID(FINN_NV40_I2C_I2C): + return finnDeserializeInterface_FINN_NV40_I2C_I2C(message, bp, (FINN_NV40_I2C_I2C *) api, api_size, deser_up); + case FINN_INTERFACE_ID(FINN_GT200_DEBUGGER_DEBUG): + return finnDeserializeInterface_FINN_GT200_DEBUGGER_DEBUG(message, bp, (FINN_GT200_DEBUGGER_DEBUG *) api, api_size, deser_up); + case FINN_INTERFACE_ID(FINN_MAXWELL_CHANNEL_GPFIFO_A_GPFIFO): + return finnDeserializeInterface_FINN_MAXWELL_CHANNEL_GPFIFO_A_GPFIFO(message, bp, (FINN_MAXWELL_CHANNEL_GPFIFO_A_GPFIFO *) api, api_size, deser_up); + + // Everything else is unsupported. + default: + { + FINN_ERROR(NV_ERR_NOT_SUPPORTED); + return NV_ERR_NOT_SUPPORTED; + } + } +} // end finnDeserializeRoot_FINN_RM_API + + +// Size of the serialized format for this interface/message +NvU64 FinnRmApiGetSerializedSize(NvU64 interface, NvU64 message, const NvP64 src) +{ + // Bit pump with writing disabled. + finn_bit_pump_for_write bp; + finn_open_buffer_for_write(&bp, (uint64_t *) 0, (const uint64_t *) 0); + + // Call the serializer with write-suppressed bit pump. + // The size is the same in bith directions (up/down). + // Eeturn zero on error to indicate that this API is not serialized by FINN. + if (finnSerializeRoot_FINN_RM_API(interface, message, (const char *) NvP64_VALUE(src), &bp, 0) != NV_OK) + return 0; + + // Close the bit pump. + finn_close_buffer_for_write(&bp); + + // Add the header size in bytes to the amount of data serialzied. + // `buffer_position` is the payload size (not really the buffer position). + return (NvU64) NV_PTR_TO_NvP64(bp.buffer_position) + sizeof(FINN_RM_API); +} + + +// Size of the unserialized format for this interface/message +NvU64 FinnRmApiGetUnserializedSize(NvU64 interface, NvU64 message) +{ + // Forward to message-specific routine. + switch (interface) + { + case FINN_INTERFACE_ID(FINN_NV01_ROOT_NVD): + return finnUnserializedInterfaceSize_FINN_NV01_ROOT_NVD(message); + case FINN_INTERFACE_ID(FINN_NV01_DEVICE_0_DMA): + return finnUnserializedInterfaceSize_FINN_NV01_DEVICE_0_DMA(message); + case FINN_INTERFACE_ID(FINN_NV01_DEVICE_0_FB): + return finnUnserializedInterfaceSize_FINN_NV01_DEVICE_0_FB(message); + case FINN_INTERFACE_ID(FINN_NV01_DEVICE_0_FIFO): + return finnUnserializedInterfaceSize_FINN_NV01_DEVICE_0_FIFO(message); + case FINN_INTERFACE_ID(FINN_NV01_DEVICE_0_GPU): + return finnUnserializedInterfaceSize_FINN_NV01_DEVICE_0_GPU(message); + case FINN_INTERFACE_ID(FINN_NV01_DEVICE_0_GR): + return finnUnserializedInterfaceSize_FINN_NV01_DEVICE_0_GR(message); + case FINN_INTERFACE_ID(FINN_NV01_DEVICE_0_HOST): + return finnUnserializedInterfaceSize_FINN_NV01_DEVICE_0_HOST(message); + case FINN_INTERFACE_ID(FINN_NV01_DEVICE_0_MSENC): + return finnUnserializedInterfaceSize_FINN_NV01_DEVICE_0_MSENC(message); + case FINN_INTERFACE_ID(FINN_NV20_SUBDEVICE_0_BIOS): + return finnUnserializedInterfaceSize_FINN_NV20_SUBDEVICE_0_BIOS(message); + case FINN_INTERFACE_ID(FINN_NV20_SUBDEVICE_0_CE): + return finnUnserializedInterfaceSize_FINN_NV20_SUBDEVICE_0_CE(message); + case FINN_INTERFACE_ID(FINN_NV20_SUBDEVICE_0_GPU): + return finnUnserializedInterfaceSize_FINN_NV20_SUBDEVICE_0_GPU(message); + case FINN_INTERFACE_ID(FINN_NV20_SUBDEVICE_0_I2C): + return finnUnserializedInterfaceSize_FINN_NV20_SUBDEVICE_0_I2C(message); + case FINN_INTERFACE_ID(FINN_NV20_SUBDEVICE_0_NVD): + return finnUnserializedInterfaceSize_FINN_NV20_SUBDEVICE_0_NVD(message); + case FINN_INTERFACE_ID(FINN_NV20_SUBDEVICE_0_PERF): + return finnUnserializedInterfaceSize_FINN_NV20_SUBDEVICE_0_PERF(message); + case FINN_INTERFACE_ID(FINN_NV20_SUBDEVICE_0_RC): + return finnUnserializedInterfaceSize_FINN_NV20_SUBDEVICE_0_RC(message); + + case FINN_INTERFACE_ID(FINN_NV20_SUBDEVICE_DIAG_GPU): + return finnUnserializedInterfaceSize_FINN_NV20_SUBDEVICE_DIAG_GPU(message); + case FINN_INTERFACE_ID(FINN_NV40_I2C_I2C): + return finnUnserializedInterfaceSize_FINN_NV40_I2C_I2C(message); + case FINN_INTERFACE_ID(FINN_GT200_DEBUGGER_DEBUG): + return finnUnserializedInterfaceSize_FINN_GT200_DEBUGGER_DEBUG(message); + case FINN_INTERFACE_ID(FINN_MAXWELL_CHANNEL_GPFIFO_A_GPFIFO): + return finnUnserializedInterfaceSize_FINN_MAXWELL_CHANNEL_GPFIFO_A_GPFIFO(message); + + // Zero indicates an unsupported interface (or message). + default: + return 0; + } +} // end FINN_RM_APIGetUnserializedSize +#if (defined(NVRM)) +// Validate the enum value. +NvBool finnBadEnum_NV402C_CTRL_I2C_TRANSACTION_TYPE(NV402C_CTRL_I2C_TRANSACTION_TYPE value) +{ switch(value) + { + case NV402C_CTRL_I2C_TRANSACTION_TYPE_SMBUS_QUICK_RW: + case NV402C_CTRL_I2C_TRANSACTION_TYPE_I2C_BYTE_RW: + case NV402C_CTRL_I2C_TRANSACTION_TYPE_I2C_BLOCK_RW: + case NV402C_CTRL_I2C_TRANSACTION_TYPE_I2C_BUFFER_RW: + case NV402C_CTRL_I2C_TRANSACTION_TYPE_SMBUS_BYTE_RW: + case NV402C_CTRL_I2C_TRANSACTION_TYPE_SMBUS_WORD_RW: + case NV402C_CTRL_I2C_TRANSACTION_TYPE_SMBUS_BLOCK_RW: + case NV402C_CTRL_I2C_TRANSACTION_TYPE_SMBUS_PROCESS_CALL: + case NV402C_CTRL_I2C_TRANSACTION_TYPE_SMBUS_BLOCK_PROCESS_CALL: + case NV402C_CTRL_I2C_TRANSACTION_TYPE_SMBUS_MULTIBYTE_REGISTER_BLOCK_RW: + case NV402C_CTRL_I2C_TRANSACTION_TYPE_READ_EDID_DDC: + return NV_FALSE; + + default: + return NV_TRUE; + } +} + +#endif // (defined(NVRM)) + +// Serialize this interface. +static NV_STATUS finnSerializeInterface_FINN_GT200_DEBUGGER_DEBUG(NvU64 message, const char *api_intf, finn_bit_pump_for_write *bp, NvBool seri_up) +{ + // Serialize one of 2 messages in this interface. + switch (message) + { +#if (defined(NVRM)) + case FINN_MESSAGE_ID(NV83DE_CTRL_DEBUG_READ_MEMORY_PARAMS): + return finnSerializeMessage_NV83DE_CTRL_DEBUG_READ_MEMORY_PARAMS((const NV83DE_CTRL_DEBUG_READ_MEMORY_PARAMS *) api_intf, bp, seri_up); + case FINN_MESSAGE_ID(NV83DE_CTRL_DEBUG_WRITE_MEMORY_PARAMS): + return finnSerializeMessage_NV83DE_CTRL_DEBUG_WRITE_MEMORY_PARAMS((const NV83DE_CTRL_DEBUG_WRITE_MEMORY_PARAMS *) api_intf, bp, seri_up); +#endif // (defined(NVRM)) + + + // Everything else is unsupported. + default: + { + FINN_ERROR(NV_ERR_NOT_SUPPORTED); + return NV_ERR_NOT_SUPPORTED; + } + } +} + + +// Deerialize this interface. +static NV_STATUS finnDeserializeInterface_FINN_GT200_DEBUGGER_DEBUG(NvU64 message, finn_bit_pump_for_read *bp, FINN_GT200_DEBUGGER_DEBUG *api_intf, NvLength api_size, NvBool deser_up) +{ + // Deerialize one of 2 messages in this interface. + switch (message) + { +#if (defined(NVRM)) + case FINN_MESSAGE_ID(NV83DE_CTRL_DEBUG_READ_MEMORY_PARAMS): + return finnDeserializeMessage_NV83DE_CTRL_DEBUG_READ_MEMORY_PARAMS(bp, (NV83DE_CTRL_DEBUG_READ_MEMORY_PARAMS *) api_intf, api_size, deser_up); + case FINN_MESSAGE_ID(NV83DE_CTRL_DEBUG_WRITE_MEMORY_PARAMS): + return finnDeserializeMessage_NV83DE_CTRL_DEBUG_WRITE_MEMORY_PARAMS(bp, (NV83DE_CTRL_DEBUG_WRITE_MEMORY_PARAMS *) api_intf, api_size, deser_up); +#endif // (defined(NVRM)) + + + // Everything else is unsupported. + default: + { + FINN_ERROR(NV_ERR_NOT_SUPPORTED); + return NV_ERR_NOT_SUPPORTED; + } + } +} + + +// Size of the unserialized format for this interface/message +static NvU64 finnUnserializedInterfaceSize_FINN_GT200_DEBUGGER_DEBUG(NvU64 message) +{ + // Forward to message-specific routine. + switch (message) + { +#if (defined(NVRM)) + case FINN_MESSAGE_ID(NV83DE_CTRL_DEBUG_READ_MEMORY_PARAMS): + return sizeof(NV83DE_CTRL_DEBUG_READ_MEMORY_PARAMS); + case FINN_MESSAGE_ID(NV83DE_CTRL_DEBUG_WRITE_MEMORY_PARAMS): + return sizeof(NV83DE_CTRL_DEBUG_WRITE_MEMORY_PARAMS); +#endif // (defined(NVRM)) + + + // Zero indicates an unsupported message (or interface). + default: + return 0; + } +} + +// Serialize this interface. +static NV_STATUS finnSerializeInterface_FINN_MAXWELL_CHANNEL_GPFIFO_A_GPFIFO(NvU64 message, const char *api_intf, finn_bit_pump_for_write *bp, NvBool seri_up) +{ + // Serialize one of 3 messages in this interface. + switch (message) + { +#if (defined(NVRM)) + case FINN_MESSAGE_ID(NVB06F_CTRL_GET_ENGINE_CTX_DATA_PARAMS): + return finnSerializeMessage_NVB06F_CTRL_GET_ENGINE_CTX_DATA_PARAMS((const NVB06F_CTRL_GET_ENGINE_CTX_DATA_PARAMS *) api_intf, bp, seri_up); + case FINN_MESSAGE_ID(NVB06F_CTRL_SAVE_ENGINE_CTX_DATA_PARAMS): + return finnSerializeMessage_NVB06F_CTRL_SAVE_ENGINE_CTX_DATA_PARAMS((const NVB06F_CTRL_SAVE_ENGINE_CTX_DATA_PARAMS *) api_intf, bp, seri_up); + case FINN_MESSAGE_ID(NVB06F_CTRL_CMD_RESTORE_ENGINE_CTX_DATA_FINN_PARAMS): + return finnSerializeMessage_NVB06F_CTRL_CMD_RESTORE_ENGINE_CTX_DATA_FINN_PARAMS((const NVB06F_CTRL_CMD_RESTORE_ENGINE_CTX_DATA_FINN_PARAMS *) api_intf, bp, seri_up); +#endif // (defined(NVRM)) + + + // Everything else is unsupported. + default: + { + FINN_ERROR(NV_ERR_NOT_SUPPORTED); + return NV_ERR_NOT_SUPPORTED; + } + } +} + + +// Deerialize this interface. +static NV_STATUS finnDeserializeInterface_FINN_MAXWELL_CHANNEL_GPFIFO_A_GPFIFO(NvU64 message, finn_bit_pump_for_read *bp, FINN_MAXWELL_CHANNEL_GPFIFO_A_GPFIFO *api_intf, NvLength api_size, NvBool deser_up) +{ + // Deerialize one of 3 messages in this interface. + switch (message) + { +#if (defined(NVRM)) + case FINN_MESSAGE_ID(NVB06F_CTRL_GET_ENGINE_CTX_DATA_PARAMS): + return finnDeserializeMessage_NVB06F_CTRL_GET_ENGINE_CTX_DATA_PARAMS(bp, (NVB06F_CTRL_GET_ENGINE_CTX_DATA_PARAMS *) api_intf, api_size, deser_up); + case FINN_MESSAGE_ID(NVB06F_CTRL_SAVE_ENGINE_CTX_DATA_PARAMS): + return finnDeserializeMessage_NVB06F_CTRL_SAVE_ENGINE_CTX_DATA_PARAMS(bp, (NVB06F_CTRL_SAVE_ENGINE_CTX_DATA_PARAMS *) api_intf, api_size, deser_up); + case FINN_MESSAGE_ID(NVB06F_CTRL_CMD_RESTORE_ENGINE_CTX_DATA_FINN_PARAMS): + return finnDeserializeMessage_NVB06F_CTRL_CMD_RESTORE_ENGINE_CTX_DATA_FINN_PARAMS(bp, (NVB06F_CTRL_CMD_RESTORE_ENGINE_CTX_DATA_FINN_PARAMS *) api_intf, api_size, deser_up); +#endif // (defined(NVRM)) + + + // Everything else is unsupported. + default: + { + FINN_ERROR(NV_ERR_NOT_SUPPORTED); + return NV_ERR_NOT_SUPPORTED; + } + } +} + + +// Size of the unserialized format for this interface/message +static NvU64 finnUnserializedInterfaceSize_FINN_MAXWELL_CHANNEL_GPFIFO_A_GPFIFO(NvU64 message) +{ + // Forward to message-specific routine. + switch (message) + { +#if (defined(NVRM)) + case FINN_MESSAGE_ID(NVB06F_CTRL_GET_ENGINE_CTX_DATA_PARAMS): + return sizeof(NVB06F_CTRL_GET_ENGINE_CTX_DATA_PARAMS); + case FINN_MESSAGE_ID(NVB06F_CTRL_SAVE_ENGINE_CTX_DATA_PARAMS): + return sizeof(NVB06F_CTRL_SAVE_ENGINE_CTX_DATA_PARAMS); + case FINN_MESSAGE_ID(NVB06F_CTRL_CMD_RESTORE_ENGINE_CTX_DATA_FINN_PARAMS): + return sizeof(NVB06F_CTRL_CMD_RESTORE_ENGINE_CTX_DATA_FINN_PARAMS); +#endif // (defined(NVRM)) + + + // Zero indicates an unsupported message (or interface). + default: + return 0; + } +} + +// Serialize this interface. +static NV_STATUS finnSerializeInterface_FINN_NV01_DEVICE_0_DMA(NvU64 message, const char *api_intf, finn_bit_pump_for_write *bp, NvBool seri_up) +{ + // Serialize one of 1 messages in this interface. + switch (message) + { +#if (defined(NVRM)) + case FINN_MESSAGE_ID(NV0080_CTRL_DMA_UPDATE_PDE_2_PARAMS): + return finnSerializeMessage_NV0080_CTRL_DMA_UPDATE_PDE_2_PARAMS((const NV0080_CTRL_DMA_UPDATE_PDE_2_PARAMS *) api_intf, bp, seri_up); +#endif // (defined(NVRM)) + + + // Everything else is unsupported. + default: + { + FINN_ERROR(NV_ERR_NOT_SUPPORTED); + return NV_ERR_NOT_SUPPORTED; + } + } +} + + +// Deerialize this interface. +static NV_STATUS finnDeserializeInterface_FINN_NV01_DEVICE_0_DMA(NvU64 message, finn_bit_pump_for_read *bp, FINN_NV01_DEVICE_0_DMA *api_intf, NvLength api_size, NvBool deser_up) +{ + // Deerialize one of 1 messages in this interface. + switch (message) + { +#if (defined(NVRM)) + case FINN_MESSAGE_ID(NV0080_CTRL_DMA_UPDATE_PDE_2_PARAMS): + return finnDeserializeMessage_NV0080_CTRL_DMA_UPDATE_PDE_2_PARAMS(bp, (NV0080_CTRL_DMA_UPDATE_PDE_2_PARAMS *) api_intf, api_size, deser_up); +#endif // (defined(NVRM)) + + + // Everything else is unsupported. + default: + { + FINN_ERROR(NV_ERR_NOT_SUPPORTED); + return NV_ERR_NOT_SUPPORTED; + } + } +} + + +// Size of the unserialized format for this interface/message +static NvU64 finnUnserializedInterfaceSize_FINN_NV01_DEVICE_0_DMA(NvU64 message) +{ + // Forward to message-specific routine. + switch (message) + { +#if (defined(NVRM)) + case FINN_MESSAGE_ID(NV0080_CTRL_DMA_UPDATE_PDE_2_PARAMS): + return sizeof(NV0080_CTRL_DMA_UPDATE_PDE_2_PARAMS); +#endif // (defined(NVRM)) + + + // Zero indicates an unsupported message (or interface). + default: + return 0; + } +} + +// Serialize this interface. +static NV_STATUS finnSerializeInterface_FINN_NV01_DEVICE_0_FB(NvU64 message, const char *api_intf, finn_bit_pump_for_write *bp, NvBool seri_up) +{ + // Serialize one of 1 messages in this interface. + switch (message) + { +#if (defined(NVRM)) + case FINN_MESSAGE_ID(NV0080_CTRL_FB_GET_CAPS_PARAMS): + return finnSerializeMessage_NV0080_CTRL_FB_GET_CAPS_PARAMS((const NV0080_CTRL_FB_GET_CAPS_PARAMS *) api_intf, bp, seri_up); +#endif // (defined(NVRM)) + + + // Everything else is unsupported. + default: + { + FINN_ERROR(NV_ERR_NOT_SUPPORTED); + return NV_ERR_NOT_SUPPORTED; + } + } +} + + +// Deerialize this interface. +static NV_STATUS finnDeserializeInterface_FINN_NV01_DEVICE_0_FB(NvU64 message, finn_bit_pump_for_read *bp, FINN_NV01_DEVICE_0_FB *api_intf, NvLength api_size, NvBool deser_up) +{ + // Deerialize one of 1 messages in this interface. + switch (message) + { +#if (defined(NVRM)) + case FINN_MESSAGE_ID(NV0080_CTRL_FB_GET_CAPS_PARAMS): + return finnDeserializeMessage_NV0080_CTRL_FB_GET_CAPS_PARAMS(bp, (NV0080_CTRL_FB_GET_CAPS_PARAMS *) api_intf, api_size, deser_up); +#endif // (defined(NVRM)) + + + // Everything else is unsupported. + default: + { + FINN_ERROR(NV_ERR_NOT_SUPPORTED); + return NV_ERR_NOT_SUPPORTED; + } + } +} + + +// Size of the unserialized format for this interface/message +static NvU64 finnUnserializedInterfaceSize_FINN_NV01_DEVICE_0_FB(NvU64 message) +{ + // Forward to message-specific routine. + switch (message) + { +#if (defined(NVRM)) + case FINN_MESSAGE_ID(NV0080_CTRL_FB_GET_CAPS_PARAMS): + return sizeof(NV0080_CTRL_FB_GET_CAPS_PARAMS); +#endif // (defined(NVRM)) + + + // Zero indicates an unsupported message (or interface). + default: + return 0; + } +} + +// Serialize this interface. +static NV_STATUS finnSerializeInterface_FINN_NV01_DEVICE_0_FIFO(NvU64 message, const char *api_intf, finn_bit_pump_for_write *bp, NvBool seri_up) +{ + // Serialize one of 3 messages in this interface. + switch (message) + { +#if (defined(NVRM)) + case FINN_MESSAGE_ID(NV0080_CTRL_FIFO_GET_CAPS_PARAMS): + return finnSerializeMessage_NV0080_CTRL_FIFO_GET_CAPS_PARAMS((const NV0080_CTRL_FIFO_GET_CAPS_PARAMS *) api_intf, bp, seri_up); +#endif // (defined(NVRM)) + + case FINN_MESSAGE_ID(NV0080_CTRL_FIFO_START_SELECTED_CHANNELS_PARAMS): + return finnSerializeMessage_NV0080_CTRL_FIFO_START_SELECTED_CHANNELS_PARAMS((const NV0080_CTRL_FIFO_START_SELECTED_CHANNELS_PARAMS *) api_intf, bp, seri_up); +#if (defined(NVRM)) + case FINN_MESSAGE_ID(NV0080_CTRL_FIFO_GET_CHANNELLIST_PARAMS): + return finnSerializeMessage_NV0080_CTRL_FIFO_GET_CHANNELLIST_PARAMS((const NV0080_CTRL_FIFO_GET_CHANNELLIST_PARAMS *) api_intf, bp, seri_up); +#endif // (defined(NVRM)) + + + // Everything else is unsupported. + default: + { + FINN_ERROR(NV_ERR_NOT_SUPPORTED); + return NV_ERR_NOT_SUPPORTED; + } + } +} + + +// Deerialize this interface. +static NV_STATUS finnDeserializeInterface_FINN_NV01_DEVICE_0_FIFO(NvU64 message, finn_bit_pump_for_read *bp, FINN_NV01_DEVICE_0_FIFO *api_intf, NvLength api_size, NvBool deser_up) +{ + // Deerialize one of 3 messages in this interface. + switch (message) + { +#if (defined(NVRM)) + case FINN_MESSAGE_ID(NV0080_CTRL_FIFO_GET_CAPS_PARAMS): + return finnDeserializeMessage_NV0080_CTRL_FIFO_GET_CAPS_PARAMS(bp, (NV0080_CTRL_FIFO_GET_CAPS_PARAMS *) api_intf, api_size, deser_up); +#endif // (defined(NVRM)) + + case FINN_MESSAGE_ID(NV0080_CTRL_FIFO_START_SELECTED_CHANNELS_PARAMS): + return finnDeserializeMessage_NV0080_CTRL_FIFO_START_SELECTED_CHANNELS_PARAMS(bp, (NV0080_CTRL_FIFO_START_SELECTED_CHANNELS_PARAMS *) api_intf, api_size, deser_up); +#if (defined(NVRM)) + case FINN_MESSAGE_ID(NV0080_CTRL_FIFO_GET_CHANNELLIST_PARAMS): + return finnDeserializeMessage_NV0080_CTRL_FIFO_GET_CHANNELLIST_PARAMS(bp, (NV0080_CTRL_FIFO_GET_CHANNELLIST_PARAMS *) api_intf, api_size, deser_up); +#endif // (defined(NVRM)) + + + // Everything else is unsupported. + default: + { + FINN_ERROR(NV_ERR_NOT_SUPPORTED); + return NV_ERR_NOT_SUPPORTED; + } + } +} + + +// Size of the unserialized format for this interface/message +static NvU64 finnUnserializedInterfaceSize_FINN_NV01_DEVICE_0_FIFO(NvU64 message) +{ + // Forward to message-specific routine. + switch (message) + { +#if (defined(NVRM)) + case FINN_MESSAGE_ID(NV0080_CTRL_FIFO_GET_CAPS_PARAMS): + return sizeof(NV0080_CTRL_FIFO_GET_CAPS_PARAMS); +#endif // (defined(NVRM)) + + case FINN_MESSAGE_ID(NV0080_CTRL_FIFO_START_SELECTED_CHANNELS_PARAMS): + return sizeof(NV0080_CTRL_FIFO_START_SELECTED_CHANNELS_PARAMS); +#if (defined(NVRM)) + case FINN_MESSAGE_ID(NV0080_CTRL_FIFO_GET_CHANNELLIST_PARAMS): + return sizeof(NV0080_CTRL_FIFO_GET_CHANNELLIST_PARAMS); +#endif // (defined(NVRM)) + + + // Zero indicates an unsupported message (or interface). + default: + return 0; + } +} + +// Serialize this interface. +static NV_STATUS finnSerializeInterface_FINN_NV01_DEVICE_0_GPU(NvU64 message, const char *api_intf, finn_bit_pump_for_write *bp, NvBool seri_up) +{ + // Serialize one of 1 messages in this interface. + switch (message) + { +#if (defined(NVRM)) + case FINN_MESSAGE_ID(NV0080_CTRL_GPU_GET_CLASSLIST_PARAMS): + return finnSerializeMessage_NV0080_CTRL_GPU_GET_CLASSLIST_PARAMS((const NV0080_CTRL_GPU_GET_CLASSLIST_PARAMS *) api_intf, bp, seri_up); +#endif // (defined(NVRM)) + + + // Everything else is unsupported. + default: + { + FINN_ERROR(NV_ERR_NOT_SUPPORTED); + return NV_ERR_NOT_SUPPORTED; + } + } +} + + +// Deerialize this interface. +static NV_STATUS finnDeserializeInterface_FINN_NV01_DEVICE_0_GPU(NvU64 message, finn_bit_pump_for_read *bp, FINN_NV01_DEVICE_0_GPU *api_intf, NvLength api_size, NvBool deser_up) +{ + // Deerialize one of 1 messages in this interface. + switch (message) + { +#if (defined(NVRM)) + case FINN_MESSAGE_ID(NV0080_CTRL_GPU_GET_CLASSLIST_PARAMS): + return finnDeserializeMessage_NV0080_CTRL_GPU_GET_CLASSLIST_PARAMS(bp, (NV0080_CTRL_GPU_GET_CLASSLIST_PARAMS *) api_intf, api_size, deser_up); +#endif // (defined(NVRM)) + + + // Everything else is unsupported. + default: + { + FINN_ERROR(NV_ERR_NOT_SUPPORTED); + return NV_ERR_NOT_SUPPORTED; + } + } +} + + +// Size of the unserialized format for this interface/message +static NvU64 finnUnserializedInterfaceSize_FINN_NV01_DEVICE_0_GPU(NvU64 message) +{ + // Forward to message-specific routine. + switch (message) + { +#if (defined(NVRM)) + case FINN_MESSAGE_ID(NV0080_CTRL_GPU_GET_CLASSLIST_PARAMS): + return sizeof(NV0080_CTRL_GPU_GET_CLASSLIST_PARAMS); +#endif // (defined(NVRM)) + + + // Zero indicates an unsupported message (or interface). + default: + return 0; + } +} + +// Serialize this interface. +static NV_STATUS finnSerializeInterface_FINN_NV01_DEVICE_0_GR(NvU64 message, const char *api_intf, finn_bit_pump_for_write *bp, NvBool seri_up) +{ + // Serialize one of 1 messages in this interface. + switch (message) + { +#if (defined(NVRM)) + case FINN_MESSAGE_ID(NV0080_CTRL_GR_GET_CAPS_PARAMS): + return finnSerializeMessage_NV0080_CTRL_GR_GET_CAPS_PARAMS((const NV0080_CTRL_GR_GET_CAPS_PARAMS *) api_intf, bp, seri_up); +#endif // (defined(NVRM)) + + + // Everything else is unsupported. + default: + { + FINN_ERROR(NV_ERR_NOT_SUPPORTED); + return NV_ERR_NOT_SUPPORTED; + } + } +} + + +// Deerialize this interface. +static NV_STATUS finnDeserializeInterface_FINN_NV01_DEVICE_0_GR(NvU64 message, finn_bit_pump_for_read *bp, FINN_NV01_DEVICE_0_GR *api_intf, NvLength api_size, NvBool deser_up) +{ + // Deerialize one of 1 messages in this interface. + switch (message) + { +#if (defined(NVRM)) + case FINN_MESSAGE_ID(NV0080_CTRL_GR_GET_CAPS_PARAMS): + return finnDeserializeMessage_NV0080_CTRL_GR_GET_CAPS_PARAMS(bp, (NV0080_CTRL_GR_GET_CAPS_PARAMS *) api_intf, api_size, deser_up); +#endif // (defined(NVRM)) + + + // Everything else is unsupported. + default: + { + FINN_ERROR(NV_ERR_NOT_SUPPORTED); + return NV_ERR_NOT_SUPPORTED; + } + } +} + + +// Size of the unserialized format for this interface/message +static NvU64 finnUnserializedInterfaceSize_FINN_NV01_DEVICE_0_GR(NvU64 message) +{ + // Forward to message-specific routine. + switch (message) + { +#if (defined(NVRM)) + case FINN_MESSAGE_ID(NV0080_CTRL_GR_GET_CAPS_PARAMS): + return sizeof(NV0080_CTRL_GR_GET_CAPS_PARAMS); +#endif // (defined(NVRM)) + + + // Zero indicates an unsupported message (or interface). + default: + return 0; + } +} + +// Serialize this interface. +static NV_STATUS finnSerializeInterface_FINN_NV01_DEVICE_0_HOST(NvU64 message, const char *api_intf, finn_bit_pump_for_write *bp, NvBool seri_up) +{ + // Serialize one of 1 messages in this interface. + switch (message) + { +#if (defined(NVRM)) + case FINN_MESSAGE_ID(NV0080_CTRL_HOST_GET_CAPS_PARAMS): + return finnSerializeMessage_NV0080_CTRL_HOST_GET_CAPS_PARAMS((const NV0080_CTRL_HOST_GET_CAPS_PARAMS *) api_intf, bp, seri_up); +#endif // (defined(NVRM)) + + + // Everything else is unsupported. + default: + { + FINN_ERROR(NV_ERR_NOT_SUPPORTED); + return NV_ERR_NOT_SUPPORTED; + } + } +} + + +// Deerialize this interface. +static NV_STATUS finnDeserializeInterface_FINN_NV01_DEVICE_0_HOST(NvU64 message, finn_bit_pump_for_read *bp, FINN_NV01_DEVICE_0_HOST *api_intf, NvLength api_size, NvBool deser_up) +{ + // Deerialize one of 1 messages in this interface. + switch (message) + { +#if (defined(NVRM)) + case FINN_MESSAGE_ID(NV0080_CTRL_HOST_GET_CAPS_PARAMS): + return finnDeserializeMessage_NV0080_CTRL_HOST_GET_CAPS_PARAMS(bp, (NV0080_CTRL_HOST_GET_CAPS_PARAMS *) api_intf, api_size, deser_up); +#endif // (defined(NVRM)) + + + // Everything else is unsupported. + default: + { + FINN_ERROR(NV_ERR_NOT_SUPPORTED); + return NV_ERR_NOT_SUPPORTED; + } + } +} + + +// Size of the unserialized format for this interface/message +static NvU64 finnUnserializedInterfaceSize_FINN_NV01_DEVICE_0_HOST(NvU64 message) +{ + // Forward to message-specific routine. + switch (message) + { +#if (defined(NVRM)) + case FINN_MESSAGE_ID(NV0080_CTRL_HOST_GET_CAPS_PARAMS): + return sizeof(NV0080_CTRL_HOST_GET_CAPS_PARAMS); +#endif // (defined(NVRM)) + + + // Zero indicates an unsupported message (or interface). + default: + return 0; + } +} + +// Serialize this interface. +static NV_STATUS finnSerializeInterface_FINN_NV01_DEVICE_0_MSENC(NvU64 message, const char *api_intf, finn_bit_pump_for_write *bp, NvBool seri_up) +{ + // Serialize one of 1 messages in this interface. + switch (message) + { +#if (defined(NVRM)) + case FINN_MESSAGE_ID(NV0080_CTRL_MSENC_GET_CAPS_PARAMS): + return finnSerializeMessage_NV0080_CTRL_MSENC_GET_CAPS_PARAMS((const NV0080_CTRL_MSENC_GET_CAPS_PARAMS *) api_intf, bp, seri_up); +#endif // (defined(NVRM)) + + + // Everything else is unsupported. + default: + { + FINN_ERROR(NV_ERR_NOT_SUPPORTED); + return NV_ERR_NOT_SUPPORTED; + } + } +} + + +// Deerialize this interface. +static NV_STATUS finnDeserializeInterface_FINN_NV01_DEVICE_0_MSENC(NvU64 message, finn_bit_pump_for_read *bp, FINN_NV01_DEVICE_0_MSENC *api_intf, NvLength api_size, NvBool deser_up) +{ + // Deerialize one of 1 messages in this interface. + switch (message) + { +#if (defined(NVRM)) + case FINN_MESSAGE_ID(NV0080_CTRL_MSENC_GET_CAPS_PARAMS): + return finnDeserializeMessage_NV0080_CTRL_MSENC_GET_CAPS_PARAMS(bp, (NV0080_CTRL_MSENC_GET_CAPS_PARAMS *) api_intf, api_size, deser_up); +#endif // (defined(NVRM)) + + + // Everything else is unsupported. + default: + { + FINN_ERROR(NV_ERR_NOT_SUPPORTED); + return NV_ERR_NOT_SUPPORTED; + } + } +} + + +// Size of the unserialized format for this interface/message +static NvU64 finnUnserializedInterfaceSize_FINN_NV01_DEVICE_0_MSENC(NvU64 message) +{ + // Forward to message-specific routine. + switch (message) + { +#if (defined(NVRM)) + case FINN_MESSAGE_ID(NV0080_CTRL_MSENC_GET_CAPS_PARAMS): + return sizeof(NV0080_CTRL_MSENC_GET_CAPS_PARAMS); +#endif // (defined(NVRM)) + + + // Zero indicates an unsupported message (or interface). + default: + return 0; + } +} + +// Serialize this interface. +static NV_STATUS finnSerializeInterface_FINN_NV01_ROOT_NVD(NvU64 message, const char *api_intf, finn_bit_pump_for_write *bp, NvBool seri_up) +{ + // Serialize one of 1 messages in this interface. + switch (message) + { +#if (defined(NVRM)) + case FINN_MESSAGE_ID(NV0000_CTRL_NVD_GET_DUMP_PARAMS): + return finnSerializeMessage_NV0000_CTRL_NVD_GET_DUMP_PARAMS((const NV0000_CTRL_NVD_GET_DUMP_PARAMS *) api_intf, bp, seri_up); +#endif // (defined(NVRM)) + + + // Everything else is unsupported. + default: + { + FINN_ERROR(NV_ERR_NOT_SUPPORTED); + return NV_ERR_NOT_SUPPORTED; + } + } +} + + +// Deerialize this interface. +static NV_STATUS finnDeserializeInterface_FINN_NV01_ROOT_NVD(NvU64 message, finn_bit_pump_for_read *bp, FINN_NV01_ROOT_NVD *api_intf, NvLength api_size, NvBool deser_up) +{ + // Deerialize one of 1 messages in this interface. + switch (message) + { +#if (defined(NVRM)) + case FINN_MESSAGE_ID(NV0000_CTRL_NVD_GET_DUMP_PARAMS): + return finnDeserializeMessage_NV0000_CTRL_NVD_GET_DUMP_PARAMS(bp, (NV0000_CTRL_NVD_GET_DUMP_PARAMS *) api_intf, api_size, deser_up); +#endif // (defined(NVRM)) + + + // Everything else is unsupported. + default: + { + FINN_ERROR(NV_ERR_NOT_SUPPORTED); + return NV_ERR_NOT_SUPPORTED; + } + } +} + + +// Size of the unserialized format for this interface/message +static NvU64 finnUnserializedInterfaceSize_FINN_NV01_ROOT_NVD(NvU64 message) +{ + // Forward to message-specific routine. + switch (message) + { +#if (defined(NVRM)) + case FINN_MESSAGE_ID(NV0000_CTRL_NVD_GET_DUMP_PARAMS): + return sizeof(NV0000_CTRL_NVD_GET_DUMP_PARAMS); +#endif // (defined(NVRM)) + + + // Zero indicates an unsupported message (or interface). + default: + return 0; + } +} + +// Serialize this interface. +static NV_STATUS finnSerializeInterface_FINN_NV20_SUBDEVICE_0_BIOS(NvU64 message, const char *api_intf, finn_bit_pump_for_write *bp, NvBool seri_up) +{ + // Serialize one of 1 messages in this interface. + switch (message) + { +#if (defined(NVRM)) + case FINN_MESSAGE_ID(NV2080_CTRL_BIOS_GET_NBSI_OBJ_PARAMS): + return finnSerializeMessage_NV2080_CTRL_BIOS_GET_NBSI_OBJ_PARAMS((const NV2080_CTRL_BIOS_GET_NBSI_OBJ_PARAMS *) api_intf, bp, seri_up); +#endif // (defined(NVRM)) + + + // Everything else is unsupported. + default: + { + FINN_ERROR(NV_ERR_NOT_SUPPORTED); + return NV_ERR_NOT_SUPPORTED; + } + } +} + + +// Deerialize this interface. +static NV_STATUS finnDeserializeInterface_FINN_NV20_SUBDEVICE_0_BIOS(NvU64 message, finn_bit_pump_for_read *bp, FINN_NV20_SUBDEVICE_0_BIOS *api_intf, NvLength api_size, NvBool deser_up) +{ + // Deerialize one of 1 messages in this interface. + switch (message) + { +#if (defined(NVRM)) + case FINN_MESSAGE_ID(NV2080_CTRL_BIOS_GET_NBSI_OBJ_PARAMS): + return finnDeserializeMessage_NV2080_CTRL_BIOS_GET_NBSI_OBJ_PARAMS(bp, (NV2080_CTRL_BIOS_GET_NBSI_OBJ_PARAMS *) api_intf, api_size, deser_up); +#endif // (defined(NVRM)) + + + // Everything else is unsupported. + default: + { + FINN_ERROR(NV_ERR_NOT_SUPPORTED); + return NV_ERR_NOT_SUPPORTED; + } + } +} + + +// Size of the unserialized format for this interface/message +static NvU64 finnUnserializedInterfaceSize_FINN_NV20_SUBDEVICE_0_BIOS(NvU64 message) +{ + // Forward to message-specific routine. + switch (message) + { +#if (defined(NVRM)) + case FINN_MESSAGE_ID(NV2080_CTRL_BIOS_GET_NBSI_OBJ_PARAMS): + return sizeof(NV2080_CTRL_BIOS_GET_NBSI_OBJ_PARAMS); +#endif // (defined(NVRM)) + + + // Zero indicates an unsupported message (or interface). + default: + return 0; + } +} + +// Serialize this interface. +static NV_STATUS finnSerializeInterface_FINN_NV20_SUBDEVICE_0_CE(NvU64 message, const char *api_intf, finn_bit_pump_for_write *bp, NvBool seri_up) +{ + // Serialize one of 1 messages in this interface. + switch (message) + { +#if (defined(NVRM)) + case FINN_MESSAGE_ID(NV2080_CTRL_CE_GET_CAPS_PARAMS): + return finnSerializeMessage_NV2080_CTRL_CE_GET_CAPS_PARAMS((const NV2080_CTRL_CE_GET_CAPS_PARAMS *) api_intf, bp, seri_up); +#endif // (defined(NVRM)) + + + // Everything else is unsupported. + default: + { + FINN_ERROR(NV_ERR_NOT_SUPPORTED); + return NV_ERR_NOT_SUPPORTED; + } + } +} + + +// Deerialize this interface. +static NV_STATUS finnDeserializeInterface_FINN_NV20_SUBDEVICE_0_CE(NvU64 message, finn_bit_pump_for_read *bp, FINN_NV20_SUBDEVICE_0_CE *api_intf, NvLength api_size, NvBool deser_up) +{ + // Deerialize one of 1 messages in this interface. + switch (message) + { +#if (defined(NVRM)) + case FINN_MESSAGE_ID(NV2080_CTRL_CE_GET_CAPS_PARAMS): + return finnDeserializeMessage_NV2080_CTRL_CE_GET_CAPS_PARAMS(bp, (NV2080_CTRL_CE_GET_CAPS_PARAMS *) api_intf, api_size, deser_up); +#endif // (defined(NVRM)) + + + // Everything else is unsupported. + default: + { + FINN_ERROR(NV_ERR_NOT_SUPPORTED); + return NV_ERR_NOT_SUPPORTED; + } + } +} + + +// Size of the unserialized format for this interface/message +static NvU64 finnUnserializedInterfaceSize_FINN_NV20_SUBDEVICE_0_CE(NvU64 message) +{ + // Forward to message-specific routine. + switch (message) + { +#if (defined(NVRM)) + case FINN_MESSAGE_ID(NV2080_CTRL_CE_GET_CAPS_PARAMS): + return sizeof(NV2080_CTRL_CE_GET_CAPS_PARAMS); +#endif // (defined(NVRM)) + + + // Zero indicates an unsupported message (or interface). + default: + return 0; + } +} + +// Serialize this interface. +static NV_STATUS finnSerializeInterface_FINN_NV20_SUBDEVICE_0_GPU(NvU64 message, const char *api_intf, finn_bit_pump_for_write *bp, NvBool seri_up) +{ + // Serialize one of 2 messages in this interface. + switch (message) + { +#if (defined(NVRM)) + case FINN_MESSAGE_ID(NV2080_CTRL_GPU_GET_ENGINES_PARAMS): + return finnSerializeMessage_NV2080_CTRL_GPU_GET_ENGINES_PARAMS((const NV2080_CTRL_GPU_GET_ENGINES_PARAMS *) api_intf, bp, seri_up); + case FINN_MESSAGE_ID(NV2080_CTRL_GPU_GET_ENGINE_CLASSLIST_PARAMS): + return finnSerializeMessage_NV2080_CTRL_GPU_GET_ENGINE_CLASSLIST_PARAMS((const NV2080_CTRL_GPU_GET_ENGINE_CLASSLIST_PARAMS *) api_intf, bp, seri_up); +#endif // (defined(NVRM)) + + + // Everything else is unsupported. + default: + { + FINN_ERROR(NV_ERR_NOT_SUPPORTED); + return NV_ERR_NOT_SUPPORTED; + } + } +} + + +// Deerialize this interface. +static NV_STATUS finnDeserializeInterface_FINN_NV20_SUBDEVICE_0_GPU(NvU64 message, finn_bit_pump_for_read *bp, FINN_NV20_SUBDEVICE_0_GPU *api_intf, NvLength api_size, NvBool deser_up) +{ + // Deerialize one of 2 messages in this interface. + switch (message) + { +#if (defined(NVRM)) + case FINN_MESSAGE_ID(NV2080_CTRL_GPU_GET_ENGINES_PARAMS): + return finnDeserializeMessage_NV2080_CTRL_GPU_GET_ENGINES_PARAMS(bp, (NV2080_CTRL_GPU_GET_ENGINES_PARAMS *) api_intf, api_size, deser_up); + case FINN_MESSAGE_ID(NV2080_CTRL_GPU_GET_ENGINE_CLASSLIST_PARAMS): + return finnDeserializeMessage_NV2080_CTRL_GPU_GET_ENGINE_CLASSLIST_PARAMS(bp, (NV2080_CTRL_GPU_GET_ENGINE_CLASSLIST_PARAMS *) api_intf, api_size, deser_up); +#endif // (defined(NVRM)) + + + // Everything else is unsupported. + default: + { + FINN_ERROR(NV_ERR_NOT_SUPPORTED); + return NV_ERR_NOT_SUPPORTED; + } + } +} + + +// Size of the unserialized format for this interface/message +static NvU64 finnUnserializedInterfaceSize_FINN_NV20_SUBDEVICE_0_GPU(NvU64 message) +{ + // Forward to message-specific routine. + switch (message) + { +#if (defined(NVRM)) + case FINN_MESSAGE_ID(NV2080_CTRL_GPU_GET_ENGINES_PARAMS): + return sizeof(NV2080_CTRL_GPU_GET_ENGINES_PARAMS); + case FINN_MESSAGE_ID(NV2080_CTRL_GPU_GET_ENGINE_CLASSLIST_PARAMS): + return sizeof(NV2080_CTRL_GPU_GET_ENGINE_CLASSLIST_PARAMS); +#endif // (defined(NVRM)) + + + // Zero indicates an unsupported message (or interface). + default: + return 0; + } +} + +// Serialize this interface. +static NV_STATUS finnSerializeInterface_FINN_NV20_SUBDEVICE_0_I2C(NvU64 message, const char *api_intf, finn_bit_pump_for_write *bp, NvBool seri_up) +{ + // Serialize one of 1 messages in this interface. + switch (message) + { +#if (defined(NVRM)) + case FINN_MESSAGE_ID(NV2080_CTRL_I2C_ACCESS_PARAMS): + return finnSerializeMessage_NV2080_CTRL_I2C_ACCESS_PARAMS((const NV2080_CTRL_I2C_ACCESS_PARAMS *) api_intf, bp, seri_up); +#endif // (defined(NVRM)) + + + // Everything else is unsupported. + default: + { + FINN_ERROR(NV_ERR_NOT_SUPPORTED); + return NV_ERR_NOT_SUPPORTED; + } + } +} + + +// Deerialize this interface. +static NV_STATUS finnDeserializeInterface_FINN_NV20_SUBDEVICE_0_I2C(NvU64 message, finn_bit_pump_for_read *bp, FINN_NV20_SUBDEVICE_0_I2C *api_intf, NvLength api_size, NvBool deser_up) +{ + // Deerialize one of 1 messages in this interface. + switch (message) + { +#if (defined(NVRM)) + case FINN_MESSAGE_ID(NV2080_CTRL_I2C_ACCESS_PARAMS): + return finnDeserializeMessage_NV2080_CTRL_I2C_ACCESS_PARAMS(bp, (NV2080_CTRL_I2C_ACCESS_PARAMS *) api_intf, api_size, deser_up); +#endif // (defined(NVRM)) + + + // Everything else is unsupported. + default: + { + FINN_ERROR(NV_ERR_NOT_SUPPORTED); + return NV_ERR_NOT_SUPPORTED; + } + } +} + + +// Size of the unserialized format for this interface/message +static NvU64 finnUnserializedInterfaceSize_FINN_NV20_SUBDEVICE_0_I2C(NvU64 message) +{ + // Forward to message-specific routine. + switch (message) + { +#if (defined(NVRM)) + case FINN_MESSAGE_ID(NV2080_CTRL_I2C_ACCESS_PARAMS): + return sizeof(NV2080_CTRL_I2C_ACCESS_PARAMS); +#endif // (defined(NVRM)) + + + // Zero indicates an unsupported message (or interface). + default: + return 0; + } +} + +// Serialize this interface. +static NV_STATUS finnSerializeInterface_FINN_NV20_SUBDEVICE_0_NVD(NvU64 message, const char *api_intf, finn_bit_pump_for_write *bp, NvBool seri_up) +{ + // Serialize one of 1 messages in this interface. + switch (message) + { +#if (defined(NVRM)) + case FINN_MESSAGE_ID(NV2080_CTRL_NVD_GET_DUMP_PARAMS): + return finnSerializeMessage_NV2080_CTRL_NVD_GET_DUMP_PARAMS((const NV2080_CTRL_NVD_GET_DUMP_PARAMS *) api_intf, bp, seri_up); +#endif // (defined(NVRM)) + + + // Everything else is unsupported. + default: + { + FINN_ERROR(NV_ERR_NOT_SUPPORTED); + return NV_ERR_NOT_SUPPORTED; + } + } +} + + +// Deerialize this interface. +static NV_STATUS finnDeserializeInterface_FINN_NV20_SUBDEVICE_0_NVD(NvU64 message, finn_bit_pump_for_read *bp, FINN_NV20_SUBDEVICE_0_NVD *api_intf, NvLength api_size, NvBool deser_up) +{ + // Deerialize one of 1 messages in this interface. + switch (message) + { +#if (defined(NVRM)) + case FINN_MESSAGE_ID(NV2080_CTRL_NVD_GET_DUMP_PARAMS): + return finnDeserializeMessage_NV2080_CTRL_NVD_GET_DUMP_PARAMS(bp, (NV2080_CTRL_NVD_GET_DUMP_PARAMS *) api_intf, api_size, deser_up); +#endif // (defined(NVRM)) + + + // Everything else is unsupported. + default: + { + FINN_ERROR(NV_ERR_NOT_SUPPORTED); + return NV_ERR_NOT_SUPPORTED; + } + } +} + + +// Size of the unserialized format for this interface/message +static NvU64 finnUnserializedInterfaceSize_FINN_NV20_SUBDEVICE_0_NVD(NvU64 message) +{ + // Forward to message-specific routine. + switch (message) + { +#if (defined(NVRM)) + case FINN_MESSAGE_ID(NV2080_CTRL_NVD_GET_DUMP_PARAMS): + return sizeof(NV2080_CTRL_NVD_GET_DUMP_PARAMS); +#endif // (defined(NVRM)) + + + // Zero indicates an unsupported message (or interface). + default: + return 0; + } +} + +// Serialize this interface. +static NV_STATUS finnSerializeInterface_FINN_NV20_SUBDEVICE_0_PERF(NvU64 message, const char *api_intf, finn_bit_pump_for_write *bp, NvBool seri_up) +{ + // Serialize one of 1 messages in this interface. + switch (message) + { +#if (defined(NVRM)) + case FINN_MESSAGE_ID(NV2080_CTRL_PERF_GET_GPUMON_PERFMON_UTIL_SAMPLES_PARAM): /* alias */ + return finnSerializeRecord_NV2080_CTRL_GPUMON_SAMPLES((const NV2080_CTRL_GPUMON_SAMPLES *) api_intf, bp, seri_up); +#endif // (defined(NVRM)) + + + // Everything else is unsupported. + default: + { + FINN_ERROR(NV_ERR_NOT_SUPPORTED); + return NV_ERR_NOT_SUPPORTED; + } + } +} + + +// Deerialize this interface. +static NV_STATUS finnDeserializeInterface_FINN_NV20_SUBDEVICE_0_PERF(NvU64 message, finn_bit_pump_for_read *bp, FINN_NV20_SUBDEVICE_0_PERF *api_intf, NvLength api_size, NvBool deser_up) +{ + // Deerialize one of 1 messages in this interface. + switch (message) + { +#if (defined(NVRM)) + case FINN_MESSAGE_ID(NV2080_CTRL_PERF_GET_GPUMON_PERFMON_UTIL_SAMPLES_PARAM): /* alias */ + return finnDeserializeRecord_NV2080_CTRL_GPUMON_SAMPLES(bp, (NV2080_CTRL_GPUMON_SAMPLES *) api_intf, api_size, deser_up); +#endif // (defined(NVRM)) + + + // Everything else is unsupported. + default: + { + FINN_ERROR(NV_ERR_NOT_SUPPORTED); + return NV_ERR_NOT_SUPPORTED; + } + } +} + + +// Size of the unserialized format for this interface/message +static NvU64 finnUnserializedInterfaceSize_FINN_NV20_SUBDEVICE_0_PERF(NvU64 message) +{ + // Forward to message-specific routine. + switch (message) + { +#if (defined(NVRM)) + case FINN_MESSAGE_ID(NV2080_CTRL_PERF_GET_GPUMON_PERFMON_UTIL_SAMPLES_PARAM): /* alias */ + return sizeof(NV2080_CTRL_GPUMON_SAMPLES); +#endif // (defined(NVRM)) + + + // Zero indicates an unsupported message (or interface). + default: + return 0; + } +} + +// Serialize this interface. +static NV_STATUS finnSerializeInterface_FINN_NV20_SUBDEVICE_0_RC(NvU64 message, const char *api_intf, finn_bit_pump_for_write *bp, NvBool seri_up) +{ + // Serialize one of 1 messages in this interface. + switch (message) + { +#if (defined(NVRM)) + case FINN_MESSAGE_ID(NV2080_CTRL_RC_READ_VIRTUAL_MEM_PARAMS): + return finnSerializeMessage_NV2080_CTRL_RC_READ_VIRTUAL_MEM_PARAMS((const NV2080_CTRL_RC_READ_VIRTUAL_MEM_PARAMS *) api_intf, bp, seri_up); +#endif // (defined(NVRM)) + + + // Everything else is unsupported. + default: + { + FINN_ERROR(NV_ERR_NOT_SUPPORTED); + return NV_ERR_NOT_SUPPORTED; + } + } +} + + +// Deerialize this interface. +static NV_STATUS finnDeserializeInterface_FINN_NV20_SUBDEVICE_0_RC(NvU64 message, finn_bit_pump_for_read *bp, FINN_NV20_SUBDEVICE_0_RC *api_intf, NvLength api_size, NvBool deser_up) +{ + // Deerialize one of 1 messages in this interface. + switch (message) + { +#if (defined(NVRM)) + case FINN_MESSAGE_ID(NV2080_CTRL_RC_READ_VIRTUAL_MEM_PARAMS): + return finnDeserializeMessage_NV2080_CTRL_RC_READ_VIRTUAL_MEM_PARAMS(bp, (NV2080_CTRL_RC_READ_VIRTUAL_MEM_PARAMS *) api_intf, api_size, deser_up); +#endif // (defined(NVRM)) + + + // Everything else is unsupported. + default: + { + FINN_ERROR(NV_ERR_NOT_SUPPORTED); + return NV_ERR_NOT_SUPPORTED; + } + } +} + + +// Size of the unserialized format for this interface/message +static NvU64 finnUnserializedInterfaceSize_FINN_NV20_SUBDEVICE_0_RC(NvU64 message) +{ + // Forward to message-specific routine. + switch (message) + { +#if (defined(NVRM)) + case FINN_MESSAGE_ID(NV2080_CTRL_RC_READ_VIRTUAL_MEM_PARAMS): + return sizeof(NV2080_CTRL_RC_READ_VIRTUAL_MEM_PARAMS); +#endif // (defined(NVRM)) + + + // Zero indicates an unsupported message (or interface). + default: + return 0; + } +} + +// Serialize this interface. +static NV_STATUS finnSerializeInterface_FINN_NV20_SUBDEVICE_DIAG_GPU(NvU64 message, const char *api_intf, finn_bit_pump_for_write *bp, NvBool seri_up) +{ + // Serialize one of 2 messages in this interface. + switch (message) + { + + + // Everything else is unsupported. + default: + { + FINN_ERROR(NV_ERR_NOT_SUPPORTED); + return NV_ERR_NOT_SUPPORTED; + } + } +} + + +// Deerialize this interface. +static NV_STATUS finnDeserializeInterface_FINN_NV20_SUBDEVICE_DIAG_GPU(NvU64 message, finn_bit_pump_for_read *bp, FINN_NV20_SUBDEVICE_DIAG_GPU *api_intf, NvLength api_size, NvBool deser_up) +{ + // Deerialize one of 2 messages in this interface. + switch (message) + { + + + // Everything else is unsupported. + default: + { + FINN_ERROR(NV_ERR_NOT_SUPPORTED); + return NV_ERR_NOT_SUPPORTED; + } + } +} + + +// Size of the unserialized format for this interface/message +static NvU64 finnUnserializedInterfaceSize_FINN_NV20_SUBDEVICE_DIAG_GPU(NvU64 message) +{ + // Forward to message-specific routine. + switch (message) + { + + + // Zero indicates an unsupported message (or interface). + default: + return 0; + } +} + +// Serialize this interface. +static NV_STATUS finnSerializeInterface_FINN_NV40_I2C_I2C(NvU64 message, const char *api_intf, finn_bit_pump_for_write *bp, NvBool seri_up) +{ + // Serialize one of 2 messages in this interface. + switch (message) + { +#if (defined(NVRM)) + case FINN_MESSAGE_ID(NV402C_CTRL_I2C_INDEXED_PARAMS): + return finnSerializeMessage_NV402C_CTRL_I2C_INDEXED_PARAMS((const NV402C_CTRL_I2C_INDEXED_PARAMS *) api_intf, bp, seri_up); + case FINN_MESSAGE_ID(NV402C_CTRL_I2C_TRANSACTION_PARAMS): + return finnSerializeMessage_NV402C_CTRL_I2C_TRANSACTION_PARAMS((const NV402C_CTRL_I2C_TRANSACTION_PARAMS *) api_intf, bp, seri_up); +#endif // (defined(NVRM)) + + + // Everything else is unsupported. + default: + { + FINN_ERROR(NV_ERR_NOT_SUPPORTED); + return NV_ERR_NOT_SUPPORTED; + } + } +} + + +// Deerialize this interface. +static NV_STATUS finnDeserializeInterface_FINN_NV40_I2C_I2C(NvU64 message, finn_bit_pump_for_read *bp, FINN_NV40_I2C_I2C *api_intf, NvLength api_size, NvBool deser_up) +{ + // Deerialize one of 2 messages in this interface. + switch (message) + { +#if (defined(NVRM)) + case FINN_MESSAGE_ID(NV402C_CTRL_I2C_INDEXED_PARAMS): + return finnDeserializeMessage_NV402C_CTRL_I2C_INDEXED_PARAMS(bp, (NV402C_CTRL_I2C_INDEXED_PARAMS *) api_intf, api_size, deser_up); + case FINN_MESSAGE_ID(NV402C_CTRL_I2C_TRANSACTION_PARAMS): + return finnDeserializeMessage_NV402C_CTRL_I2C_TRANSACTION_PARAMS(bp, (NV402C_CTRL_I2C_TRANSACTION_PARAMS *) api_intf, api_size, deser_up); +#endif // (defined(NVRM)) + + + // Everything else is unsupported. + default: + { + FINN_ERROR(NV_ERR_NOT_SUPPORTED); + return NV_ERR_NOT_SUPPORTED; + } + } +} + + +// Size of the unserialized format for this interface/message +static NvU64 finnUnserializedInterfaceSize_FINN_NV40_I2C_I2C(NvU64 message) +{ + // Forward to message-specific routine. + switch (message) + { +#if (defined(NVRM)) + case FINN_MESSAGE_ID(NV402C_CTRL_I2C_INDEXED_PARAMS): + return sizeof(NV402C_CTRL_I2C_INDEXED_PARAMS); + case FINN_MESSAGE_ID(NV402C_CTRL_I2C_TRANSACTION_PARAMS): + return sizeof(NV402C_CTRL_I2C_TRANSACTION_PARAMS); +#endif // (defined(NVRM)) + + + // Zero indicates an unsupported message (or interface). + default: + return 0; + } +} + +#if (defined(NVRM)) + +// Serialize each of the 3 field(s). +// 2 out of 2 independent field(s) are reordered to be before 1 dependent field(s). +static NV_STATUS finnSerializeMessage_NV0000_CTRL_NVD_GET_DUMP_PARAMS(const NV0000_CTRL_NVD_GET_DUMP_PARAMS *api, finn_bit_pump_for_write *bp, NvBool seri_up) +{ + // Serialize field-presence indicator for `component`. + if (finn_write_buffer(bp, 1, 1)) + { + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + return NV_ERR_BUFFER_TOO_SMALL; + } + + // Serialize 32-bit NvU32 primitive. + if (finn_write_buffer(bp, api->component, 32)) + { + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + return NV_ERR_BUFFER_TOO_SMALL; + } + + // Serialize field-presence indicator for `size`. + if (finn_write_buffer(bp, 1, 1)) + { + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + return NV_ERR_BUFFER_TOO_SMALL; + } + + // Reject source data if it is out of range. + if (api->size > NV0000_CTRL_NVD_MAX_DUMP_SIZE) + { + FINN_ERROR(NV_ERR_OUT_OF_RANGE); + return NV_ERR_OUT_OF_RANGE; + } + + // Serialize 32-bit NvU32 primitive. + if (finn_write_buffer(bp, api->size, 32)) + { + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + return NV_ERR_BUFFER_TOO_SMALL; + } + + // Serialize data-presence (nonnull pointer) indicator. + if (finn_write_buffer(bp, !!(api->pBuffer), 1)) + { + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + return NV_ERR_BUFFER_TOO_SMALL; + } + + // Skip if pointer is null. + if (api->pBuffer) + { + // Serialize each element in `pBuffer`. + { + NvLength i; + for (i = 0; i < (api->size); ++i) + { + // Serialize field-presence indicator for `pBuffer[i]`. + if (finn_write_buffer(bp, 1, 1)) + { + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + return NV_ERR_BUFFER_TOO_SMALL; + } + + // Serialize 8-bit NvU8 primitive. + if (finn_write_buffer(bp, ((NvU8 *)(NvP64_VALUE(api->pBuffer)))[i], 8)) + { + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + return NV_ERR_BUFFER_TOO_SMALL; + } + + } + } + + // Free memory that was allocated during downward deserialization. + if (seri_up && api->pBuffer) + FINN_FREE(NvP64_VALUE(api->pBuffer)); + } + + + // Done + return NV_OK; +} + + +// Deserialize each of the 3 field(s). +// 2 out of 2 independent field(s) are reordered to be before 1 dependent field(s). +static NV_STATUS finnDeserializeMessage_NV0000_CTRL_NVD_GET_DUMP_PARAMS(finn_bit_pump_for_read *bp, NV0000_CTRL_NVD_GET_DUMP_PARAMS *api, NvLength api_size, NvBool deser_up) +{ + // Check that the destination struct fits within the destination buffer. + if (sizeof(NV0000_CTRL_NVD_GET_DUMP_PARAMS) > api_size) + { + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + return NV_ERR_BUFFER_TOO_SMALL; + } + + // Check field-presence indicator for `component`. + if (!finn_read_buffer(bp, 1)) + { + FINN_ERROR(NV_ERR_LIB_RM_VERSION_MISMATCH); + return NV_ERR_LIB_RM_VERSION_MISMATCH; + } + + // Deserialize 32-bit NvU32 primitive. + api->component = (NvU32) finn_read_buffer(bp, 32); + + // Check field-presence indicator for `size`. + if (!finn_read_buffer(bp, 1)) + { + FINN_ERROR(NV_ERR_LIB_RM_VERSION_MISMATCH); + return NV_ERR_LIB_RM_VERSION_MISMATCH; + } + + // Deserialize 32-bit NvU32 primitive. + api->size = (NvU32) finn_read_buffer(bp, 32); + + // Reject deserialized data if it is out of range. + if (api->size > NV0000_CTRL_NVD_MAX_DUMP_SIZE) + { + FINN_ERROR(NV_ERR_OUT_OF_RANGE); + return NV_ERR_OUT_OF_RANGE; + } + + // Check data-presence (nonnull pointer) indicator for `pBuffer`. + if (finn_read_buffer(bp, 1)) + { + // Allocate memory and set pointer when deserializing down. + // (Calling code is expected to do so when deserializing up.) + if (!deser_up) + { + // The data-presence indicator would have been false + // if there were no data to deserialize. + if ((api->size) * (sizeof(NvU8) /*pBuffer[i]*/) /*pBuffer*/ < 1) + { + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + return NV_ERR_BUFFER_TOO_SMALL; + } + + api->pBuffer = NV_PTR_TO_NvP64(FINN_MALLOC((api->size) * (sizeof(NvU8) /*pBuffer[i]*/) /*pBuffer*/)); + if (!api->pBuffer) + { + FINN_ERROR(NV_ERR_NO_MEMORY); + return NV_ERR_NO_MEMORY; + } + + FINN_MEMZERO(NvP64_VALUE(api->pBuffer), (api->size) * (sizeof(NvU8) /*pBuffer[i]*/) /*pBuffer*/); + } + + // Otherwise the pointer must be provided by caller. + else if (!api->pBuffer) + { + FINN_ERROR(NV_ERR_INVALID_POINTER); + return NV_ERR_INVALID_POINTER; + } + + // Deserialize each element in `pBuffer`. + { + NvLength i; + for (i = 0; i < (api->size); ++i) + { + // Check field-presence indicator for `pBuffer[i]`. + if (!finn_read_buffer(bp, 1)) + { + FINN_ERROR(NV_ERR_LIB_RM_VERSION_MISMATCH); + return NV_ERR_LIB_RM_VERSION_MISMATCH; + } + + // Deserialize 8-bit NvU8 primitive. + ((NvU8 *)(NvP64_VALUE(api->pBuffer)))[i] = (NvU8) finn_read_buffer(bp, 8); + + } + } + + } + + // Nullify pointer only if FINN manages memory allocation. + else + { + if (!deser_up) + api->pBuffer = NV_PTR_TO_NvP64(NULL); + } + + // Done + return NV_OK; +} + + +// Serialize each of the 6 field(s). +// 2 out of 4 independent field(s) are reordered to be before 2 dependent field(s). +static NV_STATUS finnSerializeMessage_NV0080_CTRL_DMA_UPDATE_PDE_2_PARAMS(const NV0080_CTRL_DMA_UPDATE_PDE_2_PARAMS *api, finn_bit_pump_for_write *bp, NvBool seri_up) +{ + // Serialize field-presence indicator for `pdeIndex`. + if (finn_write_buffer(bp, 1, 1)) + { + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + return NV_ERR_BUFFER_TOO_SMALL; + } + + // Serialize 32-bit NvU32 primitive. + if (finn_write_buffer(bp, api->pdeIndex, 32)) + { + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + return NV_ERR_BUFFER_TOO_SMALL; + } + + // Serialize field-presence indicator for `flags`. + if (finn_write_buffer(bp, 1, 1)) + { + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + return NV_ERR_BUFFER_TOO_SMALL; + } + + // Serialize 32-bit NvU32 primitive. + if (finn_write_buffer(bp, api->flags, 32)) + { + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + return NV_ERR_BUFFER_TOO_SMALL; + } + + // Serialize field-presence indicator for `hVASpace`. + if (finn_write_buffer(bp, 1, 1)) + { + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + return NV_ERR_BUFFER_TOO_SMALL; + } + + // Serialize 32-bit NvU32 primitive. + if (finn_write_buffer(bp, api->hVASpace, 32)) + { + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + return NV_ERR_BUFFER_TOO_SMALL; + } + + // Serialize field-presence indicator for `subDeviceId`. + if (finn_write_buffer(bp, 1, 1)) + { + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + return NV_ERR_BUFFER_TOO_SMALL; + } + + // Serialize 32-bit NvU32 primitive. + if (finn_write_buffer(bp, api->subDeviceId, 32)) + { + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + return NV_ERR_BUFFER_TOO_SMALL; + } + + // Serialize each element in `ptParams`. + { + NvLength i; + for (i = 0; i < NV0080_CTRL_DMA_UPDATE_PDE_2_PT_IDX__SIZE; ++i) + { + // Serialize field-presence indicator for `ptParams[i]`. + if (finn_write_buffer(bp, 1, 1)) + { + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + return NV_ERR_BUFFER_TOO_SMALL; + } + + // Record has 3 field(s) to be serialized. + { + NV_STATUS status = finnSerializeRecord_NV0080_CTRL_DMA_UPDATE_PDE_2_PAGE_TABLE_PARAMS((api->ptParams+(i)), bp, seri_up); + if (status != NV_OK) + return status; + } + + } + } + + // Serialize data-presence (nonnull pointer) indicator. + if (finn_write_buffer(bp, !!(api->pPdeBuffer), 1)) + { + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + return NV_ERR_BUFFER_TOO_SMALL; + } + + // Skip if pointer is null. + if (api->pPdeBuffer) + { + // Serialize each element in `pPdeBuffer`. + { + NvLength i; + for (i = 0; i < 1; ++i) + { + // Serialize field-presence indicator for `pPdeBuffer[i]`. + if (finn_write_buffer(bp, 1, 1)) + { + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + return NV_ERR_BUFFER_TOO_SMALL; + } + + // Serialize 64-bit NvU64 primitive. + if (finn_write_buffer(bp, ((*(NvU64 (*) [1])(NvP64_VALUE(api->pPdeBuffer))))[i], 64)) + { + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + return NV_ERR_BUFFER_TOO_SMALL; + } + + } + } + + // Free memory that was allocated during downward deserialization. + if (seri_up && api->pPdeBuffer) + FINN_FREE(NvP64_VALUE(api->pPdeBuffer)); + } + + + // Done + return NV_OK; +} + + +// Deserialize each of the 6 field(s). +// 2 out of 4 independent field(s) are reordered to be before 2 dependent field(s). +static NV_STATUS finnDeserializeMessage_NV0080_CTRL_DMA_UPDATE_PDE_2_PARAMS(finn_bit_pump_for_read *bp, NV0080_CTRL_DMA_UPDATE_PDE_2_PARAMS *api, NvLength api_size, NvBool deser_up) +{ + // Check that the destination struct fits within the destination buffer. + if (sizeof(NV0080_CTRL_DMA_UPDATE_PDE_2_PARAMS) > api_size) + { + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + return NV_ERR_BUFFER_TOO_SMALL; + } + + // Check field-presence indicator for `pdeIndex`. + if (!finn_read_buffer(bp, 1)) + { + FINN_ERROR(NV_ERR_LIB_RM_VERSION_MISMATCH); + return NV_ERR_LIB_RM_VERSION_MISMATCH; + } + + // Deserialize 32-bit NvU32 primitive. + api->pdeIndex = (NvU32) finn_read_buffer(bp, 32); + + // Check field-presence indicator for `flags`. + if (!finn_read_buffer(bp, 1)) + { + FINN_ERROR(NV_ERR_LIB_RM_VERSION_MISMATCH); + return NV_ERR_LIB_RM_VERSION_MISMATCH; + } + + // Deserialize 32-bit NvU32 primitive. + api->flags = (NvU32) finn_read_buffer(bp, 32); + + // Check field-presence indicator for `hVASpace`. + if (!finn_read_buffer(bp, 1)) + { + FINN_ERROR(NV_ERR_LIB_RM_VERSION_MISMATCH); + return NV_ERR_LIB_RM_VERSION_MISMATCH; + } + + // Deserialize 32-bit NvU32 primitive. + api->hVASpace = (NvU32) finn_read_buffer(bp, 32); + + // Check field-presence indicator for `subDeviceId`. + if (!finn_read_buffer(bp, 1)) + { + FINN_ERROR(NV_ERR_LIB_RM_VERSION_MISMATCH); + return NV_ERR_LIB_RM_VERSION_MISMATCH; + } + + // Deserialize 32-bit NvU32 primitive. + api->subDeviceId = (NvU32) finn_read_buffer(bp, 32); + + // Deserialize each element in `ptParams`. + { + NvLength i; + for (i = 0; i < NV0080_CTRL_DMA_UPDATE_PDE_2_PT_IDX__SIZE; ++i) + { + // Check field-presence indicator for `ptParams[i]`. + if (!finn_read_buffer(bp, 1)) + { + FINN_ERROR(NV_ERR_LIB_RM_VERSION_MISMATCH); + return NV_ERR_LIB_RM_VERSION_MISMATCH; + } + + // Record has 3 field(s) to be deserialized. + { + NV_STATUS status = finnDeserializeRecord_NV0080_CTRL_DMA_UPDATE_PDE_2_PAGE_TABLE_PARAMS(bp, (api->ptParams+(i)), sizeof(NV0080_CTRL_DMA_UPDATE_PDE_2_PAGE_TABLE_PARAMS), deser_up); + if (status != NV_OK) + return status; + } + + } + } + + // Check data-presence (nonnull pointer) indicator for `pPdeBuffer`. + if (finn_read_buffer(bp, 1)) + { + // Allocate memory and set pointer when deserializing down. + // (Calling code is expected to do so when deserializing up.) + if (!deser_up) + { + // The data-presence indicator would have been false + // if there were no data to deserialize. + if (1 * (sizeof(NvU64) /*pPdeBuffer[i]*/) /*pPdeBuffer*/ < 1) + { + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + return NV_ERR_BUFFER_TOO_SMALL; + } + + api->pPdeBuffer = NV_PTR_TO_NvP64(FINN_MALLOC(1 * (sizeof(NvU64) /*pPdeBuffer[i]*/) /*pPdeBuffer*/)); + if (!api->pPdeBuffer) + { + FINN_ERROR(NV_ERR_NO_MEMORY); + return NV_ERR_NO_MEMORY; + } + + FINN_MEMZERO(NvP64_VALUE(api->pPdeBuffer), 1 * (sizeof(NvU64) /*pPdeBuffer[i]*/) /*pPdeBuffer*/); + } + + // Otherwise the pointer must be provided by caller. + else if (!api->pPdeBuffer) + { + FINN_ERROR(NV_ERR_INVALID_POINTER); + return NV_ERR_INVALID_POINTER; + } + + // Deserialize each element in `pPdeBuffer`. + { + NvLength i; + for (i = 0; i < 1; ++i) + { + // Check field-presence indicator for `pPdeBuffer[i]`. + if (!finn_read_buffer(bp, 1)) + { + FINN_ERROR(NV_ERR_LIB_RM_VERSION_MISMATCH); + return NV_ERR_LIB_RM_VERSION_MISMATCH; + } + + // Deserialize 64-bit NvU64 primitive. + ((*(NvU64 (*) [1])(NvP64_VALUE(api->pPdeBuffer))))[i] = (NvU64) finn_read_buffer(bp, 64); + + } + } + + } + + // Nullify pointer only if FINN manages memory allocation. + else + { + if (!deser_up) + api->pPdeBuffer = NV_PTR_TO_NvP64(NULL); + } + + // Done + return NV_OK; +} + + +// Serialize each of the 2 field(s). +static NV_STATUS finnSerializeMessage_NV0080_CTRL_FB_GET_CAPS_PARAMS(const NV0080_CTRL_FB_GET_CAPS_PARAMS *api, finn_bit_pump_for_write *bp, NvBool seri_up) +{ + // Serialize field-presence indicator for `capsTblSize`. + if (finn_write_buffer(bp, 1, 1)) + { + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + return NV_ERR_BUFFER_TOO_SMALL; + } + + // Reject source data if it is out of range. + if (api->capsTblSize > NV0080_CTRL_FB_CAPS_TBL_SIZE) + { + FINN_ERROR(NV_ERR_OUT_OF_RANGE); + return NV_ERR_OUT_OF_RANGE; + } + + // Serialize 32-bit NvU32 primitive. + if (finn_write_buffer(bp, api->capsTblSize, 32)) + { + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + return NV_ERR_BUFFER_TOO_SMALL; + } + + // Serialize data-presence (nonnull pointer) indicator. + if (finn_write_buffer(bp, !!(api->capsTbl), 1)) + { + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + return NV_ERR_BUFFER_TOO_SMALL; + } + + // Skip if pointer is null. + if (api->capsTbl) + { + // Serialize each element in `capsTbl`. + { + NvLength i; + for (i = 0; i < (api->capsTblSize); ++i) + { + // Serialize field-presence indicator for `capsTbl[i]`. + if (finn_write_buffer(bp, 1, 1)) + { + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + return NV_ERR_BUFFER_TOO_SMALL; + } + + // Serialize 8-bit NvU8 primitive. + if (finn_write_buffer(bp, ((NvU8 *)(NvP64_VALUE(api->capsTbl)))[i], 8)) + { + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + return NV_ERR_BUFFER_TOO_SMALL; + } + + } + } + + // Free memory that was allocated during downward deserialization. + if (seri_up && api->capsTbl) + FINN_FREE(NvP64_VALUE(api->capsTbl)); + } + + + // Done + return NV_OK; +} + + +// Deserialize each of the 2 field(s). +static NV_STATUS finnDeserializeMessage_NV0080_CTRL_FB_GET_CAPS_PARAMS(finn_bit_pump_for_read *bp, NV0080_CTRL_FB_GET_CAPS_PARAMS *api, NvLength api_size, NvBool deser_up) +{ + // Check that the destination struct fits within the destination buffer. + if (sizeof(NV0080_CTRL_FB_GET_CAPS_PARAMS) > api_size) + { + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + return NV_ERR_BUFFER_TOO_SMALL; + } + + // Check field-presence indicator for `capsTblSize`. + if (!finn_read_buffer(bp, 1)) + { + FINN_ERROR(NV_ERR_LIB_RM_VERSION_MISMATCH); + return NV_ERR_LIB_RM_VERSION_MISMATCH; + } + + // Deserialize 32-bit NvU32 primitive. + api->capsTblSize = (NvU32) finn_read_buffer(bp, 32); + + // Reject deserialized data if it is out of range. + if (api->capsTblSize > NV0080_CTRL_FB_CAPS_TBL_SIZE) + { + FINN_ERROR(NV_ERR_OUT_OF_RANGE); + return NV_ERR_OUT_OF_RANGE; + } + + // Check data-presence (nonnull pointer) indicator for `capsTbl`. + if (finn_read_buffer(bp, 1)) + { + // Allocate memory and set pointer when deserializing down. + // (Calling code is expected to do so when deserializing up.) + if (!deser_up) + { + // The data-presence indicator would have been false + // if there were no data to deserialize. + if ((api->capsTblSize) * (sizeof(NvU8) /*capsTbl[i]*/) /*capsTbl*/ < 1) + { + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + return NV_ERR_BUFFER_TOO_SMALL; + } + + api->capsTbl = NV_PTR_TO_NvP64(FINN_MALLOC((api->capsTblSize) * (sizeof(NvU8) /*capsTbl[i]*/) /*capsTbl*/)); + if (!api->capsTbl) + { + FINN_ERROR(NV_ERR_NO_MEMORY); + return NV_ERR_NO_MEMORY; + } + + FINN_MEMZERO(NvP64_VALUE(api->capsTbl), (api->capsTblSize) * (sizeof(NvU8) /*capsTbl[i]*/) /*capsTbl*/); + } + + // Otherwise the pointer must be provided by caller. + else if (!api->capsTbl) + { + FINN_ERROR(NV_ERR_INVALID_POINTER); + return NV_ERR_INVALID_POINTER; + } + + // Deserialize each element in `capsTbl`. + { + NvLength i; + for (i = 0; i < (api->capsTblSize); ++i) + { + // Check field-presence indicator for `capsTbl[i]`. + if (!finn_read_buffer(bp, 1)) + { + FINN_ERROR(NV_ERR_LIB_RM_VERSION_MISMATCH); + return NV_ERR_LIB_RM_VERSION_MISMATCH; + } + + // Deserialize 8-bit NvU8 primitive. + ((NvU8 *)(NvP64_VALUE(api->capsTbl)))[i] = (NvU8) finn_read_buffer(bp, 8); + + } + } + + } + + // Nullify pointer only if FINN manages memory allocation. + else + { + if (!deser_up) + api->capsTbl = NV_PTR_TO_NvP64(NULL); + } + + // Done + return NV_OK; +} + + +// Serialize each of the 2 field(s). +static NV_STATUS finnSerializeMessage_NV0080_CTRL_FIFO_GET_CAPS_PARAMS(const NV0080_CTRL_FIFO_GET_CAPS_PARAMS *api, finn_bit_pump_for_write *bp, NvBool seri_up) +{ + // Serialize field-presence indicator for `capsTblSize`. + if (finn_write_buffer(bp, 1, 1)) + { + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + return NV_ERR_BUFFER_TOO_SMALL; + } + + // Reject source data if it is out of range. + if (api->capsTblSize > NV0080_CTRL_FIFO_CAPS_TBL_SIZE) + { + FINN_ERROR(NV_ERR_OUT_OF_RANGE); + return NV_ERR_OUT_OF_RANGE; + } + + // Serialize 32-bit NvU32 primitive. + if (finn_write_buffer(bp, api->capsTblSize, 32)) + { + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + return NV_ERR_BUFFER_TOO_SMALL; + } + + // Serialize data-presence (nonnull pointer) indicator. + if (finn_write_buffer(bp, !!(api->capsTbl), 1)) + { + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + return NV_ERR_BUFFER_TOO_SMALL; + } + + // Skip if pointer is null. + if (api->capsTbl) + { + // Serialize each element in `capsTbl`. + { + NvLength i; + for (i = 0; i < (api->capsTblSize); ++i) + { + // Serialize field-presence indicator for `capsTbl[i]`. + if (finn_write_buffer(bp, 1, 1)) + { + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + return NV_ERR_BUFFER_TOO_SMALL; + } + + // Serialize 8-bit NvU8 primitive. + if (finn_write_buffer(bp, ((NvU8 *)(NvP64_VALUE(api->capsTbl)))[i], 8)) + { + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + return NV_ERR_BUFFER_TOO_SMALL; + } + + } + } + + // Free memory that was allocated during downward deserialization. + if (seri_up && api->capsTbl) + FINN_FREE(NvP64_VALUE(api->capsTbl)); + } + + + // Done + return NV_OK; +} + + +// Deserialize each of the 2 field(s). +static NV_STATUS finnDeserializeMessage_NV0080_CTRL_FIFO_GET_CAPS_PARAMS(finn_bit_pump_for_read *bp, NV0080_CTRL_FIFO_GET_CAPS_PARAMS *api, NvLength api_size, NvBool deser_up) +{ + // Check that the destination struct fits within the destination buffer. + if (sizeof(NV0080_CTRL_FIFO_GET_CAPS_PARAMS) > api_size) + { + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + return NV_ERR_BUFFER_TOO_SMALL; + } + + // Check field-presence indicator for `capsTblSize`. + if (!finn_read_buffer(bp, 1)) + { + FINN_ERROR(NV_ERR_LIB_RM_VERSION_MISMATCH); + return NV_ERR_LIB_RM_VERSION_MISMATCH; + } + + // Deserialize 32-bit NvU32 primitive. + api->capsTblSize = (NvU32) finn_read_buffer(bp, 32); + + // Reject deserialized data if it is out of range. + if (api->capsTblSize > NV0080_CTRL_FIFO_CAPS_TBL_SIZE) + { + FINN_ERROR(NV_ERR_OUT_OF_RANGE); + return NV_ERR_OUT_OF_RANGE; + } + + // Check data-presence (nonnull pointer) indicator for `capsTbl`. + if (finn_read_buffer(bp, 1)) + { + // Allocate memory and set pointer when deserializing down. + // (Calling code is expected to do so when deserializing up.) + if (!deser_up) + { + // The data-presence indicator would have been false + // if there were no data to deserialize. + if ((api->capsTblSize) * (sizeof(NvU8) /*capsTbl[i]*/) /*capsTbl*/ < 1) + { + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + return NV_ERR_BUFFER_TOO_SMALL; + } + + api->capsTbl = NV_PTR_TO_NvP64(FINN_MALLOC((api->capsTblSize) * (sizeof(NvU8) /*capsTbl[i]*/) /*capsTbl*/)); + if (!api->capsTbl) + { + FINN_ERROR(NV_ERR_NO_MEMORY); + return NV_ERR_NO_MEMORY; + } + + FINN_MEMZERO(NvP64_VALUE(api->capsTbl), (api->capsTblSize) * (sizeof(NvU8) /*capsTbl[i]*/) /*capsTbl*/); + } + + // Otherwise the pointer must be provided by caller. + else if (!api->capsTbl) + { + FINN_ERROR(NV_ERR_INVALID_POINTER); + return NV_ERR_INVALID_POINTER; + } + + // Deserialize each element in `capsTbl`. + { + NvLength i; + for (i = 0; i < (api->capsTblSize); ++i) + { + // Check field-presence indicator for `capsTbl[i]`. + if (!finn_read_buffer(bp, 1)) + { + FINN_ERROR(NV_ERR_LIB_RM_VERSION_MISMATCH); + return NV_ERR_LIB_RM_VERSION_MISMATCH; + } + + // Deserialize 8-bit NvU8 primitive. + ((NvU8 *)(NvP64_VALUE(api->capsTbl)))[i] = (NvU8) finn_read_buffer(bp, 8); + + } + } + + } + + // Nullify pointer only if FINN manages memory allocation. + else + { + if (!deser_up) + api->capsTbl = NV_PTR_TO_NvP64(NULL); + } + + // Done + return NV_OK; +} + + +// Serialize each of the 3 field(s). +static NV_STATUS finnSerializeMessage_NV0080_CTRL_FIFO_GET_CHANNELLIST_PARAMS(const NV0080_CTRL_FIFO_GET_CHANNELLIST_PARAMS *api, finn_bit_pump_for_write *bp, NvBool seri_up) +{ + // Serialize field-presence indicator for `numChannels`. + if (finn_write_buffer(bp, 1, 1)) + { + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + return NV_ERR_BUFFER_TOO_SMALL; + } + + // Serialize 32-bit NvU32 primitive. + if (finn_write_buffer(bp, api->numChannels, 32)) + { + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + return NV_ERR_BUFFER_TOO_SMALL; + } + + // Serialize data-presence (nonnull pointer) indicator. + if (finn_write_buffer(bp, !!(api->pChannelHandleList), 1)) + { + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + return NV_ERR_BUFFER_TOO_SMALL; + } + + // Skip if pointer is null. + if (api->pChannelHandleList) + { + // Serialize each element in `pChannelHandleList`. + { + NvLength i; + for (i = 0; i < (api->numChannels); ++i) + { + // Serialize field-presence indicator for `pChannelHandleList[i]`. + if (finn_write_buffer(bp, 1, 1)) + { + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + return NV_ERR_BUFFER_TOO_SMALL; + } + + // Serialize 32-bit NvU32 primitive. + if (finn_write_buffer(bp, ((NvU32 *)(NvP64_VALUE(api->pChannelHandleList)))[i], 32)) + { + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + return NV_ERR_BUFFER_TOO_SMALL; + } + + } + } + + // Free memory that was allocated during downward deserialization. + if (seri_up && api->pChannelHandleList) + FINN_FREE(NvP64_VALUE(api->pChannelHandleList)); + } + + // Serialize data-presence (nonnull pointer) indicator. + if (finn_write_buffer(bp, !!(api->pChannelList), 1)) + { + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + return NV_ERR_BUFFER_TOO_SMALL; + } + + // Skip if pointer is null. + if (api->pChannelList) + { + // Serialize each element in `pChannelList`. + { + NvLength i; + for (i = 0; i < (api->numChannels); ++i) + { + // Serialize field-presence indicator for `pChannelList[i]`. + if (finn_write_buffer(bp, 1, 1)) + { + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + return NV_ERR_BUFFER_TOO_SMALL; + } + + // Serialize 32-bit NvU32 primitive. + if (finn_write_buffer(bp, ((NvU32 *)(NvP64_VALUE(api->pChannelList)))[i], 32)) + { + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + return NV_ERR_BUFFER_TOO_SMALL; + } + + } + } + + // Free memory that was allocated during downward deserialization. + if (seri_up && api->pChannelList) + FINN_FREE(NvP64_VALUE(api->pChannelList)); + } + + + // Done + return NV_OK; +} + + +// Deserialize each of the 3 field(s). +static NV_STATUS finnDeserializeMessage_NV0080_CTRL_FIFO_GET_CHANNELLIST_PARAMS(finn_bit_pump_for_read *bp, NV0080_CTRL_FIFO_GET_CHANNELLIST_PARAMS *api, NvLength api_size, NvBool deser_up) +{ + // Check that the destination struct fits within the destination buffer. + if (sizeof(NV0080_CTRL_FIFO_GET_CHANNELLIST_PARAMS) > api_size) + { + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + return NV_ERR_BUFFER_TOO_SMALL; + } + + // Check field-presence indicator for `numChannels`. + if (!finn_read_buffer(bp, 1)) + { + FINN_ERROR(NV_ERR_LIB_RM_VERSION_MISMATCH); + return NV_ERR_LIB_RM_VERSION_MISMATCH; + } + + // Deserialize 32-bit NvU32 primitive. + api->numChannels = (NvU32) finn_read_buffer(bp, 32); + + // Check data-presence (nonnull pointer) indicator for `pChannelHandleList`. + if (finn_read_buffer(bp, 1)) + { + // Allocate memory and set pointer when deserializing down. + // (Calling code is expected to do so when deserializing up.) + if (!deser_up) + { + // The data-presence indicator would have been false + // if there were no data to deserialize. + if ((api->numChannels) * (sizeof(NvU32) /*pChannelHandleList[i]*/) /*pChannelHandleList*/ < 1) + { + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + return NV_ERR_BUFFER_TOO_SMALL; + } + + api->pChannelHandleList = NV_PTR_TO_NvP64(FINN_MALLOC((api->numChannels) * (sizeof(NvU32) /*pChannelHandleList[i]*/) /*pChannelHandleList*/)); + if (!api->pChannelHandleList) + { + FINN_ERROR(NV_ERR_NO_MEMORY); + return NV_ERR_NO_MEMORY; + } + + FINN_MEMZERO(NvP64_VALUE(api->pChannelHandleList), (api->numChannels) * (sizeof(NvU32) /*pChannelHandleList[i]*/) /*pChannelHandleList*/); + } + + // Otherwise the pointer must be provided by caller. + else if (!api->pChannelHandleList) + { + FINN_ERROR(NV_ERR_INVALID_POINTER); + return NV_ERR_INVALID_POINTER; + } + + // Deserialize each element in `pChannelHandleList`. + { + NvLength i; + for (i = 0; i < (api->numChannels); ++i) + { + // Check field-presence indicator for `pChannelHandleList[i]`. + if (!finn_read_buffer(bp, 1)) + { + FINN_ERROR(NV_ERR_LIB_RM_VERSION_MISMATCH); + return NV_ERR_LIB_RM_VERSION_MISMATCH; + } + + // Deserialize 32-bit NvU32 primitive. + ((NvU32 *)(NvP64_VALUE(api->pChannelHandleList)))[i] = (NvU32) finn_read_buffer(bp, 32); + + } + } + + } + + // Nullify pointer only if FINN manages memory allocation. + else + { + if (!deser_up) + api->pChannelHandleList = NV_PTR_TO_NvP64(NULL); + } + + // Check data-presence (nonnull pointer) indicator for `pChannelList`. + if (finn_read_buffer(bp, 1)) + { + // Allocate memory and set pointer when deserializing down. + // (Calling code is expected to do so when deserializing up.) + if (!deser_up) + { + // The data-presence indicator would have been false + // if there were no data to deserialize. + if ((api->numChannels) * (sizeof(NvU32) /*pChannelList[i]*/) /*pChannelList*/ < 1) + { + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + return NV_ERR_BUFFER_TOO_SMALL; + } + + api->pChannelList = NV_PTR_TO_NvP64(FINN_MALLOC((api->numChannels) * (sizeof(NvU32) /*pChannelList[i]*/) /*pChannelList*/)); + if (!api->pChannelList) + { + FINN_ERROR(NV_ERR_NO_MEMORY); + return NV_ERR_NO_MEMORY; + } + + FINN_MEMZERO(NvP64_VALUE(api->pChannelList), (api->numChannels) * (sizeof(NvU32) /*pChannelList[i]*/) /*pChannelList*/); + } + + // Otherwise the pointer must be provided by caller. + else if (!api->pChannelList) + { + FINN_ERROR(NV_ERR_INVALID_POINTER); + return NV_ERR_INVALID_POINTER; + } + + // Deserialize each element in `pChannelList`. + { + NvLength i; + for (i = 0; i < (api->numChannels); ++i) + { + // Check field-presence indicator for `pChannelList[i]`. + if (!finn_read_buffer(bp, 1)) + { + FINN_ERROR(NV_ERR_LIB_RM_VERSION_MISMATCH); + return NV_ERR_LIB_RM_VERSION_MISMATCH; + } + + // Deserialize 32-bit NvU32 primitive. + ((NvU32 *)(NvP64_VALUE(api->pChannelList)))[i] = (NvU32) finn_read_buffer(bp, 32); + + } + } + + } + + // Nullify pointer only if FINN manages memory allocation. + else + { + if (!deser_up) + api->pChannelList = NV_PTR_TO_NvP64(NULL); + } + + // Done + return NV_OK; +} + +#endif // (defined(NVRM)) + + +// Serialize each of the 3 field(s). +static NV_STATUS finnSerializeMessage_NV0080_CTRL_FIFO_START_SELECTED_CHANNELS_PARAMS(const NV0080_CTRL_FIFO_START_SELECTED_CHANNELS_PARAMS *api, finn_bit_pump_for_write *bp, NvBool seri_up) +{ + // Serialize field-presence indicator for `fifoStartChannelListCount`. + if (finn_write_buffer(bp, 1, 1)) + { + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + return NV_ERR_BUFFER_TOO_SMALL; + } + + // Serialize 32-bit NvU32 primitive. + if (finn_write_buffer(bp, api->fifoStartChannelListCount, 32)) + { + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + return NV_ERR_BUFFER_TOO_SMALL; + } + + // Serialize each element in `channelHandle`. + { + NvLength i; + for (i = 0; i < 8; ++i) + { + // Serialize field-presence indicator for `channelHandle[i]`. + if (finn_write_buffer(bp, 1, 1)) + { + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + return NV_ERR_BUFFER_TOO_SMALL; + } + + // Serialize 32-bit NvU32 primitive. + if (finn_write_buffer(bp, (api->channelHandle)[i], 32)) + { + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + return NV_ERR_BUFFER_TOO_SMALL; + } + + } + } + + // Serialize data-presence (nonnull pointer) indicator. + if (finn_write_buffer(bp, !!(api->fifoStartChannelList), 1)) + { + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + return NV_ERR_BUFFER_TOO_SMALL; + } + + // Skip if pointer is null. + if (api->fifoStartChannelList) + { + // Serialize each element in `fifoStartChannelList`. + { + NvLength i; + for (i = 0; i < (api->fifoStartChannelListCount); ++i) + { + // Serialize field-presence indicator for `fifoStartChannelList[i]`. + if (finn_write_buffer(bp, 1, 1)) + { + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + return NV_ERR_BUFFER_TOO_SMALL; + } + + // Record has 1 field(s) to be serialized. + { + NV_STATUS status = finnSerializeRecord_NV0080_CTRL_FIFO_CHANNEL(((NV0080_CTRL_FIFO_CHANNEL *)(NvP64_VALUE(api->fifoStartChannelList))+(i)), bp, seri_up); + if (status != NV_OK) + return status; + } + + } + } + + // Free memory that was allocated during downward deserialization. + if (seri_up && api->fifoStartChannelList) + FINN_FREE(NvP64_VALUE(api->fifoStartChannelList)); + } + + + // Done + return NV_OK; +} + + +// Deserialize each of the 3 field(s). +static NV_STATUS finnDeserializeMessage_NV0080_CTRL_FIFO_START_SELECTED_CHANNELS_PARAMS(finn_bit_pump_for_read *bp, NV0080_CTRL_FIFO_START_SELECTED_CHANNELS_PARAMS *api, NvLength api_size, NvBool deser_up) +{ + // Check that the destination struct fits within the destination buffer. + if (sizeof(NV0080_CTRL_FIFO_START_SELECTED_CHANNELS_PARAMS) > api_size) + { + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + return NV_ERR_BUFFER_TOO_SMALL; + } + + // Check field-presence indicator for `fifoStartChannelListCount`. + if (!finn_read_buffer(bp, 1)) + { + FINN_ERROR(NV_ERR_LIB_RM_VERSION_MISMATCH); + return NV_ERR_LIB_RM_VERSION_MISMATCH; + } + + // Deserialize 32-bit NvU32 primitive. + api->fifoStartChannelListCount = (NvU32) finn_read_buffer(bp, 32); + + // Deserialize each element in `channelHandle`. + { + NvLength i; + for (i = 0; i < 8; ++i) + { + // Check field-presence indicator for `channelHandle[i]`. + if (!finn_read_buffer(bp, 1)) + { + FINN_ERROR(NV_ERR_LIB_RM_VERSION_MISMATCH); + return NV_ERR_LIB_RM_VERSION_MISMATCH; + } + + // Deserialize 32-bit NvU32 primitive. + (api->channelHandle)[i] = (NvU32) finn_read_buffer(bp, 32); + + } + } + + // Check data-presence (nonnull pointer) indicator for `fifoStartChannelList`. + if (finn_read_buffer(bp, 1)) + { + // Allocate memory and set pointer when deserializing down. + // (Calling code is expected to do so when deserializing up.) + if (!deser_up) + { + // The data-presence indicator would have been false + // if there were no data to deserialize. + if ((api->fifoStartChannelListCount) * (sizeof(NV0080_CTRL_FIFO_CHANNEL) /*fifoStartChannelList[i]*/) /*fifoStartChannelList*/ < 1) + { + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + return NV_ERR_BUFFER_TOO_SMALL; + } + + api->fifoStartChannelList = NV_PTR_TO_NvP64(FINN_MALLOC((api->fifoStartChannelListCount) * (sizeof(NV0080_CTRL_FIFO_CHANNEL) /*fifoStartChannelList[i]*/) /*fifoStartChannelList*/)); + if (!api->fifoStartChannelList) + { + FINN_ERROR(NV_ERR_NO_MEMORY); + return NV_ERR_NO_MEMORY; + } + + FINN_MEMZERO(NvP64_VALUE(api->fifoStartChannelList), (api->fifoStartChannelListCount) * (sizeof(NV0080_CTRL_FIFO_CHANNEL) /*fifoStartChannelList[i]*/) /*fifoStartChannelList*/); + } + + // Otherwise the pointer must be provided by caller. + else if (!api->fifoStartChannelList) + { + FINN_ERROR(NV_ERR_INVALID_POINTER); + return NV_ERR_INVALID_POINTER; + } + + // Deserialize each element in `fifoStartChannelList`. + { + NvLength i; + for (i = 0; i < (api->fifoStartChannelListCount); ++i) + { + // Check field-presence indicator for `fifoStartChannelList[i]`. + if (!finn_read_buffer(bp, 1)) + { + FINN_ERROR(NV_ERR_LIB_RM_VERSION_MISMATCH); + return NV_ERR_LIB_RM_VERSION_MISMATCH; + } + + // Record has 1 field(s) to be deserialized. + { + NV_STATUS status = finnDeserializeRecord_NV0080_CTRL_FIFO_CHANNEL(bp, ((NV0080_CTRL_FIFO_CHANNEL *)(NvP64_VALUE(api->fifoStartChannelList))+(i)), sizeof(NV0080_CTRL_FIFO_CHANNEL), deser_up); + if (status != NV_OK) + return status; + } + + } + } + + } + + // Nullify pointer only if FINN manages memory allocation. + else + { + if (!deser_up) + api->fifoStartChannelList = NV_PTR_TO_NvP64(NULL); + } + + // Done + return NV_OK; +} + +#if (defined(NVRM)) + +// Serialize each of the 2 field(s). +static NV_STATUS finnSerializeMessage_NV0080_CTRL_GPU_GET_CLASSLIST_PARAMS(const NV0080_CTRL_GPU_GET_CLASSLIST_PARAMS *api, finn_bit_pump_for_write *bp, NvBool seri_up) +{ + // Serialize field-presence indicator for `numClasses`. + if (finn_write_buffer(bp, 1, 1)) + { + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + return NV_ERR_BUFFER_TOO_SMALL; + } + + // Serialize 32-bit NvU32 primitive. + if (finn_write_buffer(bp, api->numClasses, 32)) + { + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + return NV_ERR_BUFFER_TOO_SMALL; + } + + // Serialize data-presence (nonnull pointer) indicator. + if (finn_write_buffer(bp, !!(api->classList), 1)) + { + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + return NV_ERR_BUFFER_TOO_SMALL; + } + + // Skip if pointer is null. + if (api->classList) + { + // Serialize each element in `classList`. + { + NvLength i; + for (i = 0; i < (api->numClasses); ++i) + { + // Serialize field-presence indicator for `classList[i]`. + if (finn_write_buffer(bp, 1, 1)) + { + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + return NV_ERR_BUFFER_TOO_SMALL; + } + + // Serialize 32-bit NvU32 primitive. + if (finn_write_buffer(bp, ((NvU32 *)(NvP64_VALUE(api->classList)))[i], 32)) + { + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + return NV_ERR_BUFFER_TOO_SMALL; + } + + } + } + + // Free memory that was allocated during downward deserialization. + if (seri_up && api->classList) + FINN_FREE(NvP64_VALUE(api->classList)); + } + + + // Done + return NV_OK; +} + + +// Deserialize each of the 2 field(s). +static NV_STATUS finnDeserializeMessage_NV0080_CTRL_GPU_GET_CLASSLIST_PARAMS(finn_bit_pump_for_read *bp, NV0080_CTRL_GPU_GET_CLASSLIST_PARAMS *api, NvLength api_size, NvBool deser_up) +{ + // Check that the destination struct fits within the destination buffer. + if (sizeof(NV0080_CTRL_GPU_GET_CLASSLIST_PARAMS) > api_size) + { + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + return NV_ERR_BUFFER_TOO_SMALL; + } + + // Check field-presence indicator for `numClasses`. + if (!finn_read_buffer(bp, 1)) + { + FINN_ERROR(NV_ERR_LIB_RM_VERSION_MISMATCH); + return NV_ERR_LIB_RM_VERSION_MISMATCH; + } + + // Deserialize 32-bit NvU32 primitive. + api->numClasses = (NvU32) finn_read_buffer(bp, 32); + + // Check data-presence (nonnull pointer) indicator for `classList`. + if (finn_read_buffer(bp, 1)) + { + // Allocate memory and set pointer when deserializing down. + // (Calling code is expected to do so when deserializing up.) + if (!deser_up) + { + // The data-presence indicator would have been false + // if there were no data to deserialize. + if ((api->numClasses) * (sizeof(NvU32) /*classList[i]*/) /*classList*/ < 1) + { + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + return NV_ERR_BUFFER_TOO_SMALL; + } + + api->classList = NV_PTR_TO_NvP64(FINN_MALLOC((api->numClasses) * (sizeof(NvU32) /*classList[i]*/) /*classList*/)); + if (!api->classList) + { + FINN_ERROR(NV_ERR_NO_MEMORY); + return NV_ERR_NO_MEMORY; + } + + FINN_MEMZERO(NvP64_VALUE(api->classList), (api->numClasses) * (sizeof(NvU32) /*classList[i]*/) /*classList*/); + } + + // Otherwise the pointer must be provided by caller. + else if (!api->classList) + { + FINN_ERROR(NV_ERR_INVALID_POINTER); + return NV_ERR_INVALID_POINTER; + } + + // Deserialize each element in `classList`. + { + NvLength i; + for (i = 0; i < (api->numClasses); ++i) + { + // Check field-presence indicator for `classList[i]`. + if (!finn_read_buffer(bp, 1)) + { + FINN_ERROR(NV_ERR_LIB_RM_VERSION_MISMATCH); + return NV_ERR_LIB_RM_VERSION_MISMATCH; + } + + // Deserialize 32-bit NvU32 primitive. + ((NvU32 *)(NvP64_VALUE(api->classList)))[i] = (NvU32) finn_read_buffer(bp, 32); + + } + } + + } + + // Nullify pointer only if FINN manages memory allocation. + else + { + if (!deser_up) + api->classList = NV_PTR_TO_NvP64(NULL); + } + + // Done + return NV_OK; +} + + +// Serialize each of the 2 field(s). +static NV_STATUS finnSerializeMessage_NV0080_CTRL_GR_GET_CAPS_PARAMS(const NV0080_CTRL_GR_GET_CAPS_PARAMS *api, finn_bit_pump_for_write *bp, NvBool seri_up) +{ + // Serialize field-presence indicator for `capsTblSize`. + if (finn_write_buffer(bp, 1, 1)) + { + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + return NV_ERR_BUFFER_TOO_SMALL; + } + + // Serialize 32-bit NvU32 primitive. + if (finn_write_buffer(bp, api->capsTblSize, 32)) + { + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + return NV_ERR_BUFFER_TOO_SMALL; + } + + // Serialize data-presence (nonnull pointer) indicator. + if (finn_write_buffer(bp, !!(api->capsTbl), 1)) + { + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + return NV_ERR_BUFFER_TOO_SMALL; + } + + // Skip if pointer is null. + if (api->capsTbl) + { + // Serialize each element in `capsTbl`. + { + NvLength i; + for (i = 0; i < (api->capsTblSize); ++i) + { + // Serialize field-presence indicator for `capsTbl[i]`. + if (finn_write_buffer(bp, 1, 1)) + { + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + return NV_ERR_BUFFER_TOO_SMALL; + } + + // Serialize 8-bit NvU8 primitive. + if (finn_write_buffer(bp, ((NvU8 *)(NvP64_VALUE(api->capsTbl)))[i], 8)) + { + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + return NV_ERR_BUFFER_TOO_SMALL; + } + + } + } + + // Free memory that was allocated during downward deserialization. + if (seri_up && api->capsTbl) + FINN_FREE(NvP64_VALUE(api->capsTbl)); + } + + + // Done + return NV_OK; +} + + +// Deserialize each of the 2 field(s). +static NV_STATUS finnDeserializeMessage_NV0080_CTRL_GR_GET_CAPS_PARAMS(finn_bit_pump_for_read *bp, NV0080_CTRL_GR_GET_CAPS_PARAMS *api, NvLength api_size, NvBool deser_up) +{ + // Check that the destination struct fits within the destination buffer. + if (sizeof(NV0080_CTRL_GR_GET_CAPS_PARAMS) > api_size) + { + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + return NV_ERR_BUFFER_TOO_SMALL; + } + + // Check field-presence indicator for `capsTblSize`. + if (!finn_read_buffer(bp, 1)) + { + FINN_ERROR(NV_ERR_LIB_RM_VERSION_MISMATCH); + return NV_ERR_LIB_RM_VERSION_MISMATCH; + } + + // Deserialize 32-bit NvU32 primitive. + api->capsTblSize = (NvU32) finn_read_buffer(bp, 32); + + // Check data-presence (nonnull pointer) indicator for `capsTbl`. + if (finn_read_buffer(bp, 1)) + { + // Allocate memory and set pointer when deserializing down. + // (Calling code is expected to do so when deserializing up.) + if (!deser_up) + { + // The data-presence indicator would have been false + // if there were no data to deserialize. + if ((api->capsTblSize) * (sizeof(NvU8) /*capsTbl[i]*/) /*capsTbl*/ < 1) + { + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + return NV_ERR_BUFFER_TOO_SMALL; + } + + api->capsTbl = NV_PTR_TO_NvP64(FINN_MALLOC((api->capsTblSize) * (sizeof(NvU8) /*capsTbl[i]*/) /*capsTbl*/)); + if (!api->capsTbl) + { + FINN_ERROR(NV_ERR_NO_MEMORY); + return NV_ERR_NO_MEMORY; + } + + FINN_MEMZERO(NvP64_VALUE(api->capsTbl), (api->capsTblSize) * (sizeof(NvU8) /*capsTbl[i]*/) /*capsTbl*/); + } + + // Otherwise the pointer must be provided by caller. + else if (!api->capsTbl) + { + FINN_ERROR(NV_ERR_INVALID_POINTER); + return NV_ERR_INVALID_POINTER; + } + + // Deserialize each element in `capsTbl`. + { + NvLength i; + for (i = 0; i < (api->capsTblSize); ++i) + { + // Check field-presence indicator for `capsTbl[i]`. + if (!finn_read_buffer(bp, 1)) + { + FINN_ERROR(NV_ERR_LIB_RM_VERSION_MISMATCH); + return NV_ERR_LIB_RM_VERSION_MISMATCH; + } + + // Deserialize 8-bit NvU8 primitive. + ((NvU8 *)(NvP64_VALUE(api->capsTbl)))[i] = (NvU8) finn_read_buffer(bp, 8); + + } + } + + } + + // Nullify pointer only if FINN manages memory allocation. + else + { + if (!deser_up) + api->capsTbl = NV_PTR_TO_NvP64(NULL); + } + + // Done + return NV_OK; +} + + +// Serialize each of the 2 field(s). +static NV_STATUS finnSerializeMessage_NV0080_CTRL_HOST_GET_CAPS_PARAMS(const NV0080_CTRL_HOST_GET_CAPS_PARAMS *api, finn_bit_pump_for_write *bp, NvBool seri_up) +{ + // Serialize field-presence indicator for `capsTblSize`. + if (finn_write_buffer(bp, 1, 1)) + { + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + return NV_ERR_BUFFER_TOO_SMALL; + } + + // Reject source data if it is out of range. + if (api->capsTblSize > NV0080_CTRL_HOST_CAPS_TBL_SIZE) + { + FINN_ERROR(NV_ERR_OUT_OF_RANGE); + return NV_ERR_OUT_OF_RANGE; + } + + // Serialize 32-bit NvU32 primitive. + if (finn_write_buffer(bp, api->capsTblSize, 32)) + { + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + return NV_ERR_BUFFER_TOO_SMALL; + } + + // Serialize data-presence (nonnull pointer) indicator. + if (finn_write_buffer(bp, !!(api->capsTbl), 1)) + { + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + return NV_ERR_BUFFER_TOO_SMALL; + } + + // Skip if pointer is null. + if (api->capsTbl) + { + // Serialize each element in `capsTbl`. + { + NvLength i; + for (i = 0; i < (api->capsTblSize); ++i) + { + // Serialize field-presence indicator for `capsTbl[i]`. + if (finn_write_buffer(bp, 1, 1)) + { + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + return NV_ERR_BUFFER_TOO_SMALL; + } + + // Serialize 8-bit NvU8 primitive. + if (finn_write_buffer(bp, ((NvU8 *)(NvP64_VALUE(api->capsTbl)))[i], 8)) + { + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + return NV_ERR_BUFFER_TOO_SMALL; + } + + } + } + + // Free memory that was allocated during downward deserialization. + if (seri_up && api->capsTbl) + FINN_FREE(NvP64_VALUE(api->capsTbl)); + } + + + // Done + return NV_OK; +} + + +// Deserialize each of the 2 field(s). +static NV_STATUS finnDeserializeMessage_NV0080_CTRL_HOST_GET_CAPS_PARAMS(finn_bit_pump_for_read *bp, NV0080_CTRL_HOST_GET_CAPS_PARAMS *api, NvLength api_size, NvBool deser_up) +{ + // Check that the destination struct fits within the destination buffer. + if (sizeof(NV0080_CTRL_HOST_GET_CAPS_PARAMS) > api_size) + { + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + return NV_ERR_BUFFER_TOO_SMALL; + } + + // Check field-presence indicator for `capsTblSize`. + if (!finn_read_buffer(bp, 1)) + { + FINN_ERROR(NV_ERR_LIB_RM_VERSION_MISMATCH); + return NV_ERR_LIB_RM_VERSION_MISMATCH; + } + + // Deserialize 32-bit NvU32 primitive. + api->capsTblSize = (NvU32) finn_read_buffer(bp, 32); + + // Reject deserialized data if it is out of range. + if (api->capsTblSize > NV0080_CTRL_HOST_CAPS_TBL_SIZE) + { + FINN_ERROR(NV_ERR_OUT_OF_RANGE); + return NV_ERR_OUT_OF_RANGE; + } + + // Check data-presence (nonnull pointer) indicator for `capsTbl`. + if (finn_read_buffer(bp, 1)) + { + // Allocate memory and set pointer when deserializing down. + // (Calling code is expected to do so when deserializing up.) + if (!deser_up) + { + // The data-presence indicator would have been false + // if there were no data to deserialize. + if ((api->capsTblSize) * (sizeof(NvU8) /*capsTbl[i]*/) /*capsTbl*/ < 1) + { + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + return NV_ERR_BUFFER_TOO_SMALL; + } + + api->capsTbl = NV_PTR_TO_NvP64(FINN_MALLOC((api->capsTblSize) * (sizeof(NvU8) /*capsTbl[i]*/) /*capsTbl*/)); + if (!api->capsTbl) + { + FINN_ERROR(NV_ERR_NO_MEMORY); + return NV_ERR_NO_MEMORY; + } + + FINN_MEMZERO(NvP64_VALUE(api->capsTbl), (api->capsTblSize) * (sizeof(NvU8) /*capsTbl[i]*/) /*capsTbl*/); + } + + // Otherwise the pointer must be provided by caller. + else if (!api->capsTbl) + { + FINN_ERROR(NV_ERR_INVALID_POINTER); + return NV_ERR_INVALID_POINTER; + } + + // Deserialize each element in `capsTbl`. + { + NvLength i; + for (i = 0; i < (api->capsTblSize); ++i) + { + // Check field-presence indicator for `capsTbl[i]`. + if (!finn_read_buffer(bp, 1)) + { + FINN_ERROR(NV_ERR_LIB_RM_VERSION_MISMATCH); + return NV_ERR_LIB_RM_VERSION_MISMATCH; + } + + // Deserialize 8-bit NvU8 primitive. + ((NvU8 *)(NvP64_VALUE(api->capsTbl)))[i] = (NvU8) finn_read_buffer(bp, 8); + + } + } + + } + + // Nullify pointer only if FINN manages memory allocation. + else + { + if (!deser_up) + api->capsTbl = NV_PTR_TO_NvP64(NULL); + } + + // Done + return NV_OK; +} + + +// Serialize each of the 2 field(s). +static NV_STATUS finnSerializeMessage_NV0080_CTRL_MSENC_GET_CAPS_PARAMS(const NV0080_CTRL_MSENC_GET_CAPS_PARAMS *api, finn_bit_pump_for_write *bp, NvBool seri_up) +{ + // Serialize field-presence indicator for `capsTblSize`. + if (finn_write_buffer(bp, 1, 1)) + { + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + return NV_ERR_BUFFER_TOO_SMALL; + } + + // Reject source data if it is out of range. + if (api->capsTblSize > NV0080_CTRL_MSENC_CAPS_TBL_SIZE) + { + FINN_ERROR(NV_ERR_OUT_OF_RANGE); + return NV_ERR_OUT_OF_RANGE; + } + + // Serialize 32-bit NvU32 primitive. + if (finn_write_buffer(bp, api->capsTblSize, 32)) + { + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + return NV_ERR_BUFFER_TOO_SMALL; + } + + // Serialize data-presence (nonnull pointer) indicator. + if (finn_write_buffer(bp, !!(api->capsTbl), 1)) + { + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + return NV_ERR_BUFFER_TOO_SMALL; + } + + // Skip if pointer is null. + if (api->capsTbl) + { + // Serialize each element in `capsTbl`. + { + NvLength i; + for (i = 0; i < (api->capsTblSize); ++i) + { + // Serialize field-presence indicator for `capsTbl[i]`. + if (finn_write_buffer(bp, 1, 1)) + { + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + return NV_ERR_BUFFER_TOO_SMALL; + } + + // Serialize 8-bit NvU8 primitive. + if (finn_write_buffer(bp, ((NvU8 *)(NvP64_VALUE(api->capsTbl)))[i], 8)) + { + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + return NV_ERR_BUFFER_TOO_SMALL; + } + + } + } + + // Free memory that was allocated during downward deserialization. + if (seri_up && api->capsTbl) + FINN_FREE(NvP64_VALUE(api->capsTbl)); + } + + + // Done + return NV_OK; +} + + +// Deserialize each of the 2 field(s). +static NV_STATUS finnDeserializeMessage_NV0080_CTRL_MSENC_GET_CAPS_PARAMS(finn_bit_pump_for_read *bp, NV0080_CTRL_MSENC_GET_CAPS_PARAMS *api, NvLength api_size, NvBool deser_up) +{ + // Check that the destination struct fits within the destination buffer. + if (sizeof(NV0080_CTRL_MSENC_GET_CAPS_PARAMS) > api_size) + { + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + return NV_ERR_BUFFER_TOO_SMALL; + } + + // Check field-presence indicator for `capsTblSize`. + if (!finn_read_buffer(bp, 1)) + { + FINN_ERROR(NV_ERR_LIB_RM_VERSION_MISMATCH); + return NV_ERR_LIB_RM_VERSION_MISMATCH; + } + + // Deserialize 32-bit NvU32 primitive. + api->capsTblSize = (NvU32) finn_read_buffer(bp, 32); + + // Reject deserialized data if it is out of range. + if (api->capsTblSize > NV0080_CTRL_MSENC_CAPS_TBL_SIZE) + { + FINN_ERROR(NV_ERR_OUT_OF_RANGE); + return NV_ERR_OUT_OF_RANGE; + } + + // Check data-presence (nonnull pointer) indicator for `capsTbl`. + if (finn_read_buffer(bp, 1)) + { + // Allocate memory and set pointer when deserializing down. + // (Calling code is expected to do so when deserializing up.) + if (!deser_up) + { + // The data-presence indicator would have been false + // if there were no data to deserialize. + if ((api->capsTblSize) * (sizeof(NvU8) /*capsTbl[i]*/) /*capsTbl*/ < 1) + { + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + return NV_ERR_BUFFER_TOO_SMALL; + } + + api->capsTbl = NV_PTR_TO_NvP64(FINN_MALLOC((api->capsTblSize) * (sizeof(NvU8) /*capsTbl[i]*/) /*capsTbl*/)); + if (!api->capsTbl) + { + FINN_ERROR(NV_ERR_NO_MEMORY); + return NV_ERR_NO_MEMORY; + } + + FINN_MEMZERO(NvP64_VALUE(api->capsTbl), (api->capsTblSize) * (sizeof(NvU8) /*capsTbl[i]*/) /*capsTbl*/); + } + + // Otherwise the pointer must be provided by caller. + else if (!api->capsTbl) + { + FINN_ERROR(NV_ERR_INVALID_POINTER); + return NV_ERR_INVALID_POINTER; + } + + // Deserialize each element in `capsTbl`. + { + NvLength i; + for (i = 0; i < (api->capsTblSize); ++i) + { + // Check field-presence indicator for `capsTbl[i]`. + if (!finn_read_buffer(bp, 1)) + { + FINN_ERROR(NV_ERR_LIB_RM_VERSION_MISMATCH); + return NV_ERR_LIB_RM_VERSION_MISMATCH; + } + + // Deserialize 8-bit NvU8 primitive. + ((NvU8 *)(NvP64_VALUE(api->capsTbl)))[i] = (NvU8) finn_read_buffer(bp, 8); + + } + } + + } + + // Nullify pointer only if FINN manages memory allocation. + else + { + if (!deser_up) + api->capsTbl = NV_PTR_TO_NvP64(NULL); + } + + // Done + return NV_OK; +} + + +// Serialize each of the 8 field(s). +// 3 out of 7 independent field(s) are reordered to be before 1 dependent field(s). +static NV_STATUS finnSerializeMessage_NV2080_CTRL_BIOS_GET_NBSI_OBJ_PARAMS(const NV2080_CTRL_BIOS_GET_NBSI_OBJ_PARAMS *api, finn_bit_pump_for_write *bp, NvBool seri_up) +{ + // Serialize field-presence indicator for `globType`. + if (finn_write_buffer(bp, 1, 1)) + { + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + return NV_ERR_BUFFER_TOO_SMALL; + } + + // Serialize 16-bit NvU16 primitive. + if (finn_write_buffer(bp, api->globType, 16)) + { + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + return NV_ERR_BUFFER_TOO_SMALL; + } + + // Serialize field-presence indicator for `globIndex`. + if (finn_write_buffer(bp, 1, 1)) + { + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + return NV_ERR_BUFFER_TOO_SMALL; + } + + // Serialize 8-bit NvU8 primitive. + if (finn_write_buffer(bp, api->globIndex, 8)) + { + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + return NV_ERR_BUFFER_TOO_SMALL; + } + + // Serialize field-presence indicator for `globSource`. + if (finn_write_buffer(bp, 1, 1)) + { + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + return NV_ERR_BUFFER_TOO_SMALL; + } + + // Serialize 16-bit NvU16 primitive. + if (finn_write_buffer(bp, api->globSource, 16)) + { + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + return NV_ERR_BUFFER_TOO_SMALL; + } + + // Serialize field-presence indicator for `retBufOffset`. + if (finn_write_buffer(bp, 1, 1)) + { + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + return NV_ERR_BUFFER_TOO_SMALL; + } + + // Serialize 32-bit NvU32 primitive. + if (finn_write_buffer(bp, api->retBufOffset, 32)) + { + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + return NV_ERR_BUFFER_TOO_SMALL; + } + + // Serialize field-presence indicator for `retSize`. + if (finn_write_buffer(bp, 1, 1)) + { + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + return NV_ERR_BUFFER_TOO_SMALL; + } + + // Serialize 32-bit NvU32 primitive. + if (finn_write_buffer(bp, api->retSize, 32)) + { + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + return NV_ERR_BUFFER_TOO_SMALL; + } + + // Serialize field-presence indicator for `totalObjSize`. + if (finn_write_buffer(bp, 1, 1)) + { + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + return NV_ERR_BUFFER_TOO_SMALL; + } + + // Serialize 32-bit NvU32 primitive. + if (finn_write_buffer(bp, api->totalObjSize, 32)) + { + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + return NV_ERR_BUFFER_TOO_SMALL; + } + + // Serialize field-presence indicator for `errorCode`. + if (finn_write_buffer(bp, 1, 1)) + { + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + return NV_ERR_BUFFER_TOO_SMALL; + } + + // Serialize 32-bit NvU32 primitive. + if (finn_write_buffer(bp, api->errorCode, 32)) + { + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + return NV_ERR_BUFFER_TOO_SMALL; + } + + // Serialize data-presence (nonnull pointer) indicator. + if (finn_write_buffer(bp, !!(api->retBuf), 1)) + { + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + return NV_ERR_BUFFER_TOO_SMALL; + } + + // Skip if pointer is null. + if (api->retBuf) + { + // Serialize each element in `retBuf`. + { + NvLength i; + for (i = 0; i < (api->retSize); ++i) + { + // Serialize field-presence indicator for `retBuf[i]`. + if (finn_write_buffer(bp, 1, 1)) + { + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + return NV_ERR_BUFFER_TOO_SMALL; + } + + // Serialize 8-bit NvU8 primitive. + if (finn_write_buffer(bp, ((NvU8 *)(NvP64_VALUE(api->retBuf)))[i], 8)) + { + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + return NV_ERR_BUFFER_TOO_SMALL; + } + + } + } + + // Free memory that was allocated during downward deserialization. + if (seri_up && api->retBuf) + FINN_FREE(NvP64_VALUE(api->retBuf)); + } + + + // Done + return NV_OK; +} + + +// Deserialize each of the 8 field(s). +// 3 out of 7 independent field(s) are reordered to be before 1 dependent field(s). +static NV_STATUS finnDeserializeMessage_NV2080_CTRL_BIOS_GET_NBSI_OBJ_PARAMS(finn_bit_pump_for_read *bp, NV2080_CTRL_BIOS_GET_NBSI_OBJ_PARAMS *api, NvLength api_size, NvBool deser_up) +{ + // Check that the destination struct fits within the destination buffer. + if (sizeof(NV2080_CTRL_BIOS_GET_NBSI_OBJ_PARAMS) > api_size) + { + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + return NV_ERR_BUFFER_TOO_SMALL; + } + + // Check field-presence indicator for `globType`. + if (!finn_read_buffer(bp, 1)) + { + FINN_ERROR(NV_ERR_LIB_RM_VERSION_MISMATCH); + return NV_ERR_LIB_RM_VERSION_MISMATCH; + } + + // Deserialize 16-bit NvU16 primitive. + api->globType = (NvU16) finn_read_buffer(bp, 16); + + // Check field-presence indicator for `globIndex`. + if (!finn_read_buffer(bp, 1)) + { + FINN_ERROR(NV_ERR_LIB_RM_VERSION_MISMATCH); + return NV_ERR_LIB_RM_VERSION_MISMATCH; + } + + // Deserialize 8-bit NvU8 primitive. + api->globIndex = (NvU8) finn_read_buffer(bp, 8); + + // Check field-presence indicator for `globSource`. + if (!finn_read_buffer(bp, 1)) + { + FINN_ERROR(NV_ERR_LIB_RM_VERSION_MISMATCH); + return NV_ERR_LIB_RM_VERSION_MISMATCH; + } + + // Deserialize 16-bit NvU16 primitive. + api->globSource = (NvU16) finn_read_buffer(bp, 16); + + // Check field-presence indicator for `retBufOffset`. + if (!finn_read_buffer(bp, 1)) + { + FINN_ERROR(NV_ERR_LIB_RM_VERSION_MISMATCH); + return NV_ERR_LIB_RM_VERSION_MISMATCH; + } + + // Deserialize 32-bit NvU32 primitive. + api->retBufOffset = (NvU32) finn_read_buffer(bp, 32); + + // Check field-presence indicator for `retSize`. + if (!finn_read_buffer(bp, 1)) + { + FINN_ERROR(NV_ERR_LIB_RM_VERSION_MISMATCH); + return NV_ERR_LIB_RM_VERSION_MISMATCH; + } + + // Deserialize 32-bit NvU32 primitive. + api->retSize = (NvU32) finn_read_buffer(bp, 32); + + // Check field-presence indicator for `totalObjSize`. + if (!finn_read_buffer(bp, 1)) + { + FINN_ERROR(NV_ERR_LIB_RM_VERSION_MISMATCH); + return NV_ERR_LIB_RM_VERSION_MISMATCH; + } + + // Deserialize 32-bit NvU32 primitive. + api->totalObjSize = (NvU32) finn_read_buffer(bp, 32); + + // Check field-presence indicator for `errorCode`. + if (!finn_read_buffer(bp, 1)) + { + FINN_ERROR(NV_ERR_LIB_RM_VERSION_MISMATCH); + return NV_ERR_LIB_RM_VERSION_MISMATCH; + } + + // Deserialize 32-bit NvU32 primitive. + api->errorCode = (NvU32) finn_read_buffer(bp, 32); + + // Check data-presence (nonnull pointer) indicator for `retBuf`. + if (finn_read_buffer(bp, 1)) + { + // Allocate memory and set pointer when deserializing down. + // (Calling code is expected to do so when deserializing up.) + if (!deser_up) + { + // The data-presence indicator would have been false + // if there were no data to deserialize. + if ((api->retSize) * (sizeof(NvU8) /*retBuf[i]*/) /*retBuf*/ < 1) + { + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + return NV_ERR_BUFFER_TOO_SMALL; + } + + api->retBuf = NV_PTR_TO_NvP64(FINN_MALLOC((api->retSize) * (sizeof(NvU8) /*retBuf[i]*/) /*retBuf*/)); + if (!api->retBuf) + { + FINN_ERROR(NV_ERR_NO_MEMORY); + return NV_ERR_NO_MEMORY; + } + + FINN_MEMZERO(NvP64_VALUE(api->retBuf), (api->retSize) * (sizeof(NvU8) /*retBuf[i]*/) /*retBuf*/); + } + + // Otherwise the pointer must be provided by caller. + else if (!api->retBuf) + { + FINN_ERROR(NV_ERR_INVALID_POINTER); + return NV_ERR_INVALID_POINTER; + } + + // Deserialize each element in `retBuf`. + { + NvLength i; + for (i = 0; i < (api->retSize); ++i) + { + // Check field-presence indicator for `retBuf[i]`. + if (!finn_read_buffer(bp, 1)) + { + FINN_ERROR(NV_ERR_LIB_RM_VERSION_MISMATCH); + return NV_ERR_LIB_RM_VERSION_MISMATCH; + } + + // Deserialize 8-bit NvU8 primitive. + ((NvU8 *)(NvP64_VALUE(api->retBuf)))[i] = (NvU8) finn_read_buffer(bp, 8); + + } + } + + } + + // Nullify pointer only if FINN manages memory allocation. + else + { + if (!deser_up) + api->retBuf = NV_PTR_TO_NvP64(NULL); + } + + // Done + return NV_OK; +} + + +// Serialize each of the 3 field(s). +static NV_STATUS finnSerializeMessage_NV2080_CTRL_CE_GET_CAPS_PARAMS(const NV2080_CTRL_CE_GET_CAPS_PARAMS *api, finn_bit_pump_for_write *bp, NvBool seri_up) +{ + // Serialize field-presence indicator for `ceEngineType`. + if (finn_write_buffer(bp, 1, 1)) + { + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + return NV_ERR_BUFFER_TOO_SMALL; + } + + // Serialize 32-bit NvU32 primitive. + if (finn_write_buffer(bp, api->ceEngineType, 32)) + { + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + return NV_ERR_BUFFER_TOO_SMALL; + } + + // Serialize field-presence indicator for `capsTblSize`. + if (finn_write_buffer(bp, 1, 1)) + { + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + return NV_ERR_BUFFER_TOO_SMALL; + } + + // Reject source data if it is out of range. + if (api->capsTblSize > NV2080_CTRL_CE_CAPS_TBL_SIZE) + { + FINN_ERROR(NV_ERR_OUT_OF_RANGE); + return NV_ERR_OUT_OF_RANGE; + } + + // Serialize 32-bit NvU32 primitive. + if (finn_write_buffer(bp, api->capsTblSize, 32)) + { + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + return NV_ERR_BUFFER_TOO_SMALL; + } + + // Serialize data-presence (nonnull pointer) indicator. + if (finn_write_buffer(bp, !!(api->capsTbl), 1)) + { + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + return NV_ERR_BUFFER_TOO_SMALL; + } + + // Skip if pointer is null. + if (api->capsTbl) + { + // Serialize each element in `capsTbl`. + { + NvLength i; + for (i = 0; i < (api->capsTblSize); ++i) + { + // Serialize field-presence indicator for `capsTbl[i]`. + if (finn_write_buffer(bp, 1, 1)) + { + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + return NV_ERR_BUFFER_TOO_SMALL; + } + + // Serialize 8-bit NvU8 primitive. + if (finn_write_buffer(bp, ((NvU8 *)(NvP64_VALUE(api->capsTbl)))[i], 8)) + { + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + return NV_ERR_BUFFER_TOO_SMALL; + } + + } + } + + // Free memory that was allocated during downward deserialization. + if (seri_up && api->capsTbl) + FINN_FREE(NvP64_VALUE(api->capsTbl)); + } + + + // Done + return NV_OK; +} + + +// Deserialize each of the 3 field(s). +static NV_STATUS finnDeserializeMessage_NV2080_CTRL_CE_GET_CAPS_PARAMS(finn_bit_pump_for_read *bp, NV2080_CTRL_CE_GET_CAPS_PARAMS *api, NvLength api_size, NvBool deser_up) +{ + // Check that the destination struct fits within the destination buffer. + if (sizeof(NV2080_CTRL_CE_GET_CAPS_PARAMS) > api_size) + { + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + return NV_ERR_BUFFER_TOO_SMALL; + } + + // Check field-presence indicator for `ceEngineType`. + if (!finn_read_buffer(bp, 1)) + { + FINN_ERROR(NV_ERR_LIB_RM_VERSION_MISMATCH); + return NV_ERR_LIB_RM_VERSION_MISMATCH; + } + + // Deserialize 32-bit NvU32 primitive. + api->ceEngineType = (NvU32) finn_read_buffer(bp, 32); + + // Check field-presence indicator for `capsTblSize`. + if (!finn_read_buffer(bp, 1)) + { + FINN_ERROR(NV_ERR_LIB_RM_VERSION_MISMATCH); + return NV_ERR_LIB_RM_VERSION_MISMATCH; + } + + // Deserialize 32-bit NvU32 primitive. + api->capsTblSize = (NvU32) finn_read_buffer(bp, 32); + + // Reject deserialized data if it is out of range. + if (api->capsTblSize > NV2080_CTRL_CE_CAPS_TBL_SIZE) + { + FINN_ERROR(NV_ERR_OUT_OF_RANGE); + return NV_ERR_OUT_OF_RANGE; + } + + // Check data-presence (nonnull pointer) indicator for `capsTbl`. + if (finn_read_buffer(bp, 1)) + { + // Allocate memory and set pointer when deserializing down. + // (Calling code is expected to do so when deserializing up.) + if (!deser_up) + { + // The data-presence indicator would have been false + // if there were no data to deserialize. + if ((api->capsTblSize) * (sizeof(NvU8) /*capsTbl[i]*/) /*capsTbl*/ < 1) + { + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + return NV_ERR_BUFFER_TOO_SMALL; + } + + api->capsTbl = NV_PTR_TO_NvP64(FINN_MALLOC((api->capsTblSize) * (sizeof(NvU8) /*capsTbl[i]*/) /*capsTbl*/)); + if (!api->capsTbl) + { + FINN_ERROR(NV_ERR_NO_MEMORY); + return NV_ERR_NO_MEMORY; + } + + FINN_MEMZERO(NvP64_VALUE(api->capsTbl), (api->capsTblSize) * (sizeof(NvU8) /*capsTbl[i]*/) /*capsTbl*/); + } + + // Otherwise the pointer must be provided by caller. + else if (!api->capsTbl) + { + FINN_ERROR(NV_ERR_INVALID_POINTER); + return NV_ERR_INVALID_POINTER; + } + + // Deserialize each element in `capsTbl`. + { + NvLength i; + for (i = 0; i < (api->capsTblSize); ++i) + { + // Check field-presence indicator for `capsTbl[i]`. + if (!finn_read_buffer(bp, 1)) + { + FINN_ERROR(NV_ERR_LIB_RM_VERSION_MISMATCH); + return NV_ERR_LIB_RM_VERSION_MISMATCH; + } + + // Deserialize 8-bit NvU8 primitive. + ((NvU8 *)(NvP64_VALUE(api->capsTbl)))[i] = (NvU8) finn_read_buffer(bp, 8); + + } + } + + } + + // Nullify pointer only if FINN manages memory allocation. + else + { + if (!deser_up) + api->capsTbl = NV_PTR_TO_NvP64(NULL); + } + + // Done + return NV_OK; +} + + +// Serialize each of the 2 field(s). +static NV_STATUS finnSerializeMessage_NV2080_CTRL_GPU_GET_ENGINES_PARAMS(const NV2080_CTRL_GPU_GET_ENGINES_PARAMS *api, finn_bit_pump_for_write *bp, NvBool seri_up) +{ + // Serialize field-presence indicator for `engineCount`. + if (finn_write_buffer(bp, 1, 1)) + { + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + return NV_ERR_BUFFER_TOO_SMALL; + } + + // Serialize 32-bit NvU32 primitive. + if (finn_write_buffer(bp, api->engineCount, 32)) + { + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + return NV_ERR_BUFFER_TOO_SMALL; + } + + // Serialize data-presence (nonnull pointer) indicator. + if (finn_write_buffer(bp, !!(api->engineList), 1)) + { + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + return NV_ERR_BUFFER_TOO_SMALL; + } + + // Skip if pointer is null. + if (api->engineList) + { + // Serialize each element in `engineList`. + { + NvLength i; + for (i = 0; i < (api->engineCount); ++i) + { + // Serialize field-presence indicator for `engineList[i]`. + if (finn_write_buffer(bp, 1, 1)) + { + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + return NV_ERR_BUFFER_TOO_SMALL; + } + + // Serialize 32-bit NvU32 primitive. + if (finn_write_buffer(bp, ((NvU32 *)(NvP64_VALUE(api->engineList)))[i], 32)) + { + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + return NV_ERR_BUFFER_TOO_SMALL; + } + + } + } + + // Free memory that was allocated during downward deserialization. + if (seri_up && api->engineList) + FINN_FREE(NvP64_VALUE(api->engineList)); + } + + + // Done + return NV_OK; +} + + +// Deserialize each of the 2 field(s). +static NV_STATUS finnDeserializeMessage_NV2080_CTRL_GPU_GET_ENGINES_PARAMS(finn_bit_pump_for_read *bp, NV2080_CTRL_GPU_GET_ENGINES_PARAMS *api, NvLength api_size, NvBool deser_up) +{ + // Check that the destination struct fits within the destination buffer. + if (sizeof(NV2080_CTRL_GPU_GET_ENGINES_PARAMS) > api_size) + { + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + return NV_ERR_BUFFER_TOO_SMALL; + } + + // Check field-presence indicator for `engineCount`. + if (!finn_read_buffer(bp, 1)) + { + FINN_ERROR(NV_ERR_LIB_RM_VERSION_MISMATCH); + return NV_ERR_LIB_RM_VERSION_MISMATCH; + } + + // Deserialize 32-bit NvU32 primitive. + api->engineCount = (NvU32) finn_read_buffer(bp, 32); + + // Check data-presence (nonnull pointer) indicator for `engineList`. + if (finn_read_buffer(bp, 1)) + { + // Allocate memory and set pointer when deserializing down. + // (Calling code is expected to do so when deserializing up.) + if (!deser_up) + { + // The data-presence indicator would have been false + // if there were no data to deserialize. + if ((api->engineCount) * (sizeof(NvU32) /*engineList[i]*/) /*engineList*/ < 1) + { + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + return NV_ERR_BUFFER_TOO_SMALL; + } + + api->engineList = NV_PTR_TO_NvP64(FINN_MALLOC((api->engineCount) * (sizeof(NvU32) /*engineList[i]*/) /*engineList*/)); + if (!api->engineList) + { + FINN_ERROR(NV_ERR_NO_MEMORY); + return NV_ERR_NO_MEMORY; + } + + FINN_MEMZERO(NvP64_VALUE(api->engineList), (api->engineCount) * (sizeof(NvU32) /*engineList[i]*/) /*engineList*/); + } + + // Otherwise the pointer must be provided by caller. + else if (!api->engineList) + { + FINN_ERROR(NV_ERR_INVALID_POINTER); + return NV_ERR_INVALID_POINTER; + } + + // Deserialize each element in `engineList`. + { + NvLength i; + for (i = 0; i < (api->engineCount); ++i) + { + // Check field-presence indicator for `engineList[i]`. + if (!finn_read_buffer(bp, 1)) + { + FINN_ERROR(NV_ERR_LIB_RM_VERSION_MISMATCH); + return NV_ERR_LIB_RM_VERSION_MISMATCH; + } + + // Deserialize 32-bit NvU32 primitive. + ((NvU32 *)(NvP64_VALUE(api->engineList)))[i] = (NvU32) finn_read_buffer(bp, 32); + + } + } + + } + + // Nullify pointer only if FINN manages memory allocation. + else + { + if (!deser_up) + api->engineList = NV_PTR_TO_NvP64(NULL); + } + + // Done + return NV_OK; +} + + +// Serialize each of the 3 field(s). +static NV_STATUS finnSerializeMessage_NV2080_CTRL_GPU_GET_ENGINE_CLASSLIST_PARAMS(const NV2080_CTRL_GPU_GET_ENGINE_CLASSLIST_PARAMS *api, finn_bit_pump_for_write *bp, NvBool seri_up) +{ + // Serialize field-presence indicator for `engineType`. + if (finn_write_buffer(bp, 1, 1)) + { + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + return NV_ERR_BUFFER_TOO_SMALL; + } + + // Serialize 32-bit NvU32 primitive. + if (finn_write_buffer(bp, api->engineType, 32)) + { + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + return NV_ERR_BUFFER_TOO_SMALL; + } + + // Serialize field-presence indicator for `numClasses`. + if (finn_write_buffer(bp, 1, 1)) + { + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + return NV_ERR_BUFFER_TOO_SMALL; + } + + // Serialize 32-bit NvU32 primitive. + if (finn_write_buffer(bp, api->numClasses, 32)) + { + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + return NV_ERR_BUFFER_TOO_SMALL; + } + + // Serialize data-presence (nonnull pointer) indicator. + if (finn_write_buffer(bp, !!(api->classList), 1)) + { + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + return NV_ERR_BUFFER_TOO_SMALL; + } + + // Skip if pointer is null. + if (api->classList) + { + // Serialize each element in `classList`. + { + NvLength i; + for (i = 0; i < (api->numClasses); ++i) + { + // Serialize field-presence indicator for `classList[i]`. + if (finn_write_buffer(bp, 1, 1)) + { + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + return NV_ERR_BUFFER_TOO_SMALL; + } + + // Serialize 32-bit NvU32 primitive. + if (finn_write_buffer(bp, ((NvU32 *)(NvP64_VALUE(api->classList)))[i], 32)) + { + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + return NV_ERR_BUFFER_TOO_SMALL; + } + + } + } + + // Free memory that was allocated during downward deserialization. + if (seri_up && api->classList) + FINN_FREE(NvP64_VALUE(api->classList)); + } + + + // Done + return NV_OK; +} + + +// Deserialize each of the 3 field(s). +static NV_STATUS finnDeserializeMessage_NV2080_CTRL_GPU_GET_ENGINE_CLASSLIST_PARAMS(finn_bit_pump_for_read *bp, NV2080_CTRL_GPU_GET_ENGINE_CLASSLIST_PARAMS *api, NvLength api_size, NvBool deser_up) +{ + // Check that the destination struct fits within the destination buffer. + if (sizeof(NV2080_CTRL_GPU_GET_ENGINE_CLASSLIST_PARAMS) > api_size) + { + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + return NV_ERR_BUFFER_TOO_SMALL; + } + + // Check field-presence indicator for `engineType`. + if (!finn_read_buffer(bp, 1)) + { + FINN_ERROR(NV_ERR_LIB_RM_VERSION_MISMATCH); + return NV_ERR_LIB_RM_VERSION_MISMATCH; + } + + // Deserialize 32-bit NvU32 primitive. + api->engineType = (NvU32) finn_read_buffer(bp, 32); + + // Check field-presence indicator for `numClasses`. + if (!finn_read_buffer(bp, 1)) + { + FINN_ERROR(NV_ERR_LIB_RM_VERSION_MISMATCH); + return NV_ERR_LIB_RM_VERSION_MISMATCH; + } + + // Deserialize 32-bit NvU32 primitive. + api->numClasses = (NvU32) finn_read_buffer(bp, 32); + + // Check data-presence (nonnull pointer) indicator for `classList`. + if (finn_read_buffer(bp, 1)) + { + // Allocate memory and set pointer when deserializing down. + // (Calling code is expected to do so when deserializing up.) + if (!deser_up) + { + // The data-presence indicator would have been false + // if there were no data to deserialize. + if ((api->numClasses) * (sizeof(NvU32) /*classList[i]*/) /*classList*/ < 1) + { + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + return NV_ERR_BUFFER_TOO_SMALL; + } + + api->classList = NV_PTR_TO_NvP64(FINN_MALLOC((api->numClasses) * (sizeof(NvU32) /*classList[i]*/) /*classList*/)); + if (!api->classList) + { + FINN_ERROR(NV_ERR_NO_MEMORY); + return NV_ERR_NO_MEMORY; + } + + FINN_MEMZERO(NvP64_VALUE(api->classList), (api->numClasses) * (sizeof(NvU32) /*classList[i]*/) /*classList*/); + } + + // Otherwise the pointer must be provided by caller. + else if (!api->classList) + { + FINN_ERROR(NV_ERR_INVALID_POINTER); + return NV_ERR_INVALID_POINTER; + } + + // Deserialize each element in `classList`. + { + NvLength i; + for (i = 0; i < (api->numClasses); ++i) + { + // Check field-presence indicator for `classList[i]`. + if (!finn_read_buffer(bp, 1)) + { + FINN_ERROR(NV_ERR_LIB_RM_VERSION_MISMATCH); + return NV_ERR_LIB_RM_VERSION_MISMATCH; + } + + // Deserialize 32-bit NvU32 primitive. + ((NvU32 *)(NvP64_VALUE(api->classList)))[i] = (NvU32) finn_read_buffer(bp, 32); + + } + } + + } + + // Nullify pointer only if FINN manages memory allocation. + else + { + if (!deser_up) + api->classList = NV_PTR_TO_NvP64(NULL); + } + + // Done + return NV_OK; +} + + +// Serialize each of the 9 field(s). +// 4 out of 8 independent field(s) are reordered to be before 1 dependent field(s). +static NV_STATUS finnSerializeMessage_NV2080_CTRL_I2C_ACCESS_PARAMS(const NV2080_CTRL_I2C_ACCESS_PARAMS *api, finn_bit_pump_for_write *bp, NvBool seri_up) +{ + // Serialize field-presence indicator for `token`. + if (finn_write_buffer(bp, 1, 1)) + { + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + return NV_ERR_BUFFER_TOO_SMALL; + } + + // Serialize 32-bit NvU32 primitive. + if (finn_write_buffer(bp, api->token, 32)) + { + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + return NV_ERR_BUFFER_TOO_SMALL; + } + + // Serialize field-presence indicator for `cmd`. + if (finn_write_buffer(bp, 1, 1)) + { + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + return NV_ERR_BUFFER_TOO_SMALL; + } + + // Serialize 32-bit NvU32 primitive. + if (finn_write_buffer(bp, api->cmd, 32)) + { + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + return NV_ERR_BUFFER_TOO_SMALL; + } + + // Serialize field-presence indicator for `port`. + if (finn_write_buffer(bp, 1, 1)) + { + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + return NV_ERR_BUFFER_TOO_SMALL; + } + + // Serialize 32-bit NvU32 primitive. + if (finn_write_buffer(bp, api->port, 32)) + { + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + return NV_ERR_BUFFER_TOO_SMALL; + } + + // Serialize field-presence indicator for `flags`. + if (finn_write_buffer(bp, 1, 1)) + { + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + return NV_ERR_BUFFER_TOO_SMALL; + } + + // Serialize 32-bit NvU32 primitive. + if (finn_write_buffer(bp, api->flags, 32)) + { + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + return NV_ERR_BUFFER_TOO_SMALL; + } + + // Serialize field-presence indicator for `status`. + if (finn_write_buffer(bp, 1, 1)) + { + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + return NV_ERR_BUFFER_TOO_SMALL; + } + + // Serialize 32-bit NvU32 primitive. + if (finn_write_buffer(bp, api->status, 32)) + { + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + return NV_ERR_BUFFER_TOO_SMALL; + } + + // Serialize field-presence indicator for `dataBuffSize`. + if (finn_write_buffer(bp, 1, 1)) + { + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + return NV_ERR_BUFFER_TOO_SMALL; + } + + // Reject source data if it is out of range. + if (api->dataBuffSize > NV2080_CTRL_I2C_MAX_ENTRIES) + { + FINN_ERROR(NV_ERR_OUT_OF_RANGE); + return NV_ERR_OUT_OF_RANGE; + } + + // Serialize 32-bit NvU32 primitive. + if (finn_write_buffer(bp, api->dataBuffSize, 32)) + { + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + return NV_ERR_BUFFER_TOO_SMALL; + } + + // Serialize field-presence indicator for `speed`. + if (finn_write_buffer(bp, 1, 1)) + { + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + return NV_ERR_BUFFER_TOO_SMALL; + } + + // Serialize 32-bit NvU32 primitive. + if (finn_write_buffer(bp, api->speed, 32)) + { + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + return NV_ERR_BUFFER_TOO_SMALL; + } + + // Serialize field-presence indicator for `encrClientID`. + if (finn_write_buffer(bp, 1, 1)) + { + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + return NV_ERR_BUFFER_TOO_SMALL; + } + + // Serialize 32-bit NvU32 primitive. + if (finn_write_buffer(bp, api->encrClientID, 32)) + { + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + return NV_ERR_BUFFER_TOO_SMALL; + } + + // Serialize data-presence (nonnull pointer) indicator. + if (finn_write_buffer(bp, !!(api->data), 1)) + { + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + return NV_ERR_BUFFER_TOO_SMALL; + } + + // Skip if pointer is null. + if (api->data) + { + // Serialize each element in `data`. + { + NvLength i; + for (i = 0; i < (api->dataBuffSize); ++i) + { + // Serialize field-presence indicator for `data[i]`. + if (finn_write_buffer(bp, 1, 1)) + { + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + return NV_ERR_BUFFER_TOO_SMALL; + } + + // Serialize 8-bit NvU8 primitive. + if (finn_write_buffer(bp, ((NvU8 *)(NvP64_VALUE(api->data)))[i], 8)) + { + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + return NV_ERR_BUFFER_TOO_SMALL; + } + + } + } + + // Free memory that was allocated during downward deserialization. + if (seri_up && api->data) + FINN_FREE(NvP64_VALUE(api->data)); + } + + + // Done + return NV_OK; +} + + +// Deserialize each of the 9 field(s). +// 4 out of 8 independent field(s) are reordered to be before 1 dependent field(s). +static NV_STATUS finnDeserializeMessage_NV2080_CTRL_I2C_ACCESS_PARAMS(finn_bit_pump_for_read *bp, NV2080_CTRL_I2C_ACCESS_PARAMS *api, NvLength api_size, NvBool deser_up) +{ + // Check that the destination struct fits within the destination buffer. + if (sizeof(NV2080_CTRL_I2C_ACCESS_PARAMS) > api_size) + { + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + return NV_ERR_BUFFER_TOO_SMALL; + } + + // Check field-presence indicator for `token`. + if (!finn_read_buffer(bp, 1)) + { + FINN_ERROR(NV_ERR_LIB_RM_VERSION_MISMATCH); + return NV_ERR_LIB_RM_VERSION_MISMATCH; + } + + // Deserialize 32-bit NvU32 primitive. + api->token = (NvU32) finn_read_buffer(bp, 32); + + // Check field-presence indicator for `cmd`. + if (!finn_read_buffer(bp, 1)) + { + FINN_ERROR(NV_ERR_LIB_RM_VERSION_MISMATCH); + return NV_ERR_LIB_RM_VERSION_MISMATCH; + } + + // Deserialize 32-bit NvU32 primitive. + api->cmd = (NvU32) finn_read_buffer(bp, 32); + + // Check field-presence indicator for `port`. + if (!finn_read_buffer(bp, 1)) + { + FINN_ERROR(NV_ERR_LIB_RM_VERSION_MISMATCH); + return NV_ERR_LIB_RM_VERSION_MISMATCH; + } + + // Deserialize 32-bit NvU32 primitive. + api->port = (NvU32) finn_read_buffer(bp, 32); + + // Check field-presence indicator for `flags`. + if (!finn_read_buffer(bp, 1)) + { + FINN_ERROR(NV_ERR_LIB_RM_VERSION_MISMATCH); + return NV_ERR_LIB_RM_VERSION_MISMATCH; + } + + // Deserialize 32-bit NvU32 primitive. + api->flags = (NvU32) finn_read_buffer(bp, 32); + + // Check field-presence indicator for `status`. + if (!finn_read_buffer(bp, 1)) + { + FINN_ERROR(NV_ERR_LIB_RM_VERSION_MISMATCH); + return NV_ERR_LIB_RM_VERSION_MISMATCH; + } + + // Deserialize 32-bit NvU32 primitive. + api->status = (NvU32) finn_read_buffer(bp, 32); + + // Check field-presence indicator for `dataBuffSize`. + if (!finn_read_buffer(bp, 1)) + { + FINN_ERROR(NV_ERR_LIB_RM_VERSION_MISMATCH); + return NV_ERR_LIB_RM_VERSION_MISMATCH; + } + + // Deserialize 32-bit NvU32 primitive. + api->dataBuffSize = (NvU32) finn_read_buffer(bp, 32); + + // Reject deserialized data if it is out of range. + if (api->dataBuffSize > NV2080_CTRL_I2C_MAX_ENTRIES) + { + FINN_ERROR(NV_ERR_OUT_OF_RANGE); + return NV_ERR_OUT_OF_RANGE; + } + + // Check field-presence indicator for `speed`. + if (!finn_read_buffer(bp, 1)) + { + FINN_ERROR(NV_ERR_LIB_RM_VERSION_MISMATCH); + return NV_ERR_LIB_RM_VERSION_MISMATCH; + } + + // Deserialize 32-bit NvU32 primitive. + api->speed = (NvU32) finn_read_buffer(bp, 32); + + // Check field-presence indicator for `encrClientID`. + if (!finn_read_buffer(bp, 1)) + { + FINN_ERROR(NV_ERR_LIB_RM_VERSION_MISMATCH); + return NV_ERR_LIB_RM_VERSION_MISMATCH; + } + + // Deserialize 32-bit NvU32 primitive. + api->encrClientID = (NvU32) finn_read_buffer(bp, 32); + + // Check data-presence (nonnull pointer) indicator for `data`. + if (finn_read_buffer(bp, 1)) + { + // Allocate memory and set pointer when deserializing down. + // (Calling code is expected to do so when deserializing up.) + if (!deser_up) + { + // The data-presence indicator would have been false + // if there were no data to deserialize. + if ((api->dataBuffSize) * (sizeof(NvU8) /*data[i]*/) /*data*/ < 1) + { + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + return NV_ERR_BUFFER_TOO_SMALL; + } + + api->data = NV_PTR_TO_NvP64(FINN_MALLOC((api->dataBuffSize) * (sizeof(NvU8) /*data[i]*/) /*data*/)); + if (!api->data) + { + FINN_ERROR(NV_ERR_NO_MEMORY); + return NV_ERR_NO_MEMORY; + } + + FINN_MEMZERO(NvP64_VALUE(api->data), (api->dataBuffSize) * (sizeof(NvU8) /*data[i]*/) /*data*/); + } + + // Otherwise the pointer must be provided by caller. + else if (!api->data) + { + FINN_ERROR(NV_ERR_INVALID_POINTER); + return NV_ERR_INVALID_POINTER; + } + + // Deserialize each element in `data`. + { + NvLength i; + for (i = 0; i < (api->dataBuffSize); ++i) + { + // Check field-presence indicator for `data[i]`. + if (!finn_read_buffer(bp, 1)) + { + FINN_ERROR(NV_ERR_LIB_RM_VERSION_MISMATCH); + return NV_ERR_LIB_RM_VERSION_MISMATCH; + } + + // Deserialize 8-bit NvU8 primitive. + ((NvU8 *)(NvP64_VALUE(api->data)))[i] = (NvU8) finn_read_buffer(bp, 8); + + } + } + + } + + // Nullify pointer only if FINN manages memory allocation. + else + { + if (!deser_up) + api->data = NV_PTR_TO_NvP64(NULL); + } + + // Done + return NV_OK; +} + + +// Serialize each of the 3 field(s). +// 2 out of 2 independent field(s) are reordered to be before 1 dependent field(s). +static NV_STATUS finnSerializeMessage_NV2080_CTRL_NVD_GET_DUMP_PARAMS(const NV2080_CTRL_NVD_GET_DUMP_PARAMS *api, finn_bit_pump_for_write *bp, NvBool seri_up) +{ + // Serialize field-presence indicator for `component`. + if (finn_write_buffer(bp, 1, 1)) + { + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + return NV_ERR_BUFFER_TOO_SMALL; + } + + // Serialize 32-bit NvU32 primitive. + if (finn_write_buffer(bp, api->component, 32)) + { + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + return NV_ERR_BUFFER_TOO_SMALL; + } + + // Serialize field-presence indicator for `size`. + if (finn_write_buffer(bp, 1, 1)) + { + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + return NV_ERR_BUFFER_TOO_SMALL; + } + + // Serialize 32-bit NvU32 primitive. + if (finn_write_buffer(bp, api->size, 32)) + { + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + return NV_ERR_BUFFER_TOO_SMALL; + } + + // Serialize data-presence (nonnull pointer) indicator. + if (finn_write_buffer(bp, !!(api->pBuffer), 1)) + { + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + return NV_ERR_BUFFER_TOO_SMALL; + } + + // Skip if pointer is null. + if (api->pBuffer) + { + // Serialize each element in `pBuffer`. + { + NvLength i; + for (i = 0; i < (api->size); ++i) + { + // Serialize field-presence indicator for `pBuffer[i]`. + if (finn_write_buffer(bp, 1, 1)) + { + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + return NV_ERR_BUFFER_TOO_SMALL; + } + + // Serialize 8-bit NvU8 primitive. + if (finn_write_buffer(bp, ((NvU8 *)(NvP64_VALUE(api->pBuffer)))[i], 8)) + { + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + return NV_ERR_BUFFER_TOO_SMALL; + } + + } + } + + // Free memory that was allocated during downward deserialization. + if (seri_up && api->pBuffer) + FINN_FREE(NvP64_VALUE(api->pBuffer)); + } + + + // Done + return NV_OK; +} + + +// Deserialize each of the 3 field(s). +// 2 out of 2 independent field(s) are reordered to be before 1 dependent field(s). +static NV_STATUS finnDeserializeMessage_NV2080_CTRL_NVD_GET_DUMP_PARAMS(finn_bit_pump_for_read *bp, NV2080_CTRL_NVD_GET_DUMP_PARAMS *api, NvLength api_size, NvBool deser_up) +{ + // Check that the destination struct fits within the destination buffer. + if (sizeof(NV2080_CTRL_NVD_GET_DUMP_PARAMS) > api_size) + { + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + return NV_ERR_BUFFER_TOO_SMALL; + } + + // Check field-presence indicator for `component`. + if (!finn_read_buffer(bp, 1)) + { + FINN_ERROR(NV_ERR_LIB_RM_VERSION_MISMATCH); + return NV_ERR_LIB_RM_VERSION_MISMATCH; + } + + // Deserialize 32-bit NvU32 primitive. + api->component = (NvU32) finn_read_buffer(bp, 32); + + // Check field-presence indicator for `size`. + if (!finn_read_buffer(bp, 1)) + { + FINN_ERROR(NV_ERR_LIB_RM_VERSION_MISMATCH); + return NV_ERR_LIB_RM_VERSION_MISMATCH; + } + + // Deserialize 32-bit NvU32 primitive. + api->size = (NvU32) finn_read_buffer(bp, 32); + + // Check data-presence (nonnull pointer) indicator for `pBuffer`. + if (finn_read_buffer(bp, 1)) + { + // Allocate memory and set pointer when deserializing down. + // (Calling code is expected to do so when deserializing up.) + if (!deser_up) + { + // The data-presence indicator would have been false + // if there were no data to deserialize. + if ((api->size) * (sizeof(NvU8) /*pBuffer[i]*/) /*pBuffer*/ < 1) + { + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + return NV_ERR_BUFFER_TOO_SMALL; + } + + api->pBuffer = NV_PTR_TO_NvP64(FINN_MALLOC((api->size) * (sizeof(NvU8) /*pBuffer[i]*/) /*pBuffer*/)); + if (!api->pBuffer) + { + FINN_ERROR(NV_ERR_NO_MEMORY); + return NV_ERR_NO_MEMORY; + } + + FINN_MEMZERO(NvP64_VALUE(api->pBuffer), (api->size) * (sizeof(NvU8) /*pBuffer[i]*/) /*pBuffer*/); + } + + // Otherwise the pointer must be provided by caller. + else if (!api->pBuffer) + { + FINN_ERROR(NV_ERR_INVALID_POINTER); + return NV_ERR_INVALID_POINTER; + } + + // Deserialize each element in `pBuffer`. + { + NvLength i; + for (i = 0; i < (api->size); ++i) + { + // Check field-presence indicator for `pBuffer[i]`. + if (!finn_read_buffer(bp, 1)) + { + FINN_ERROR(NV_ERR_LIB_RM_VERSION_MISMATCH); + return NV_ERR_LIB_RM_VERSION_MISMATCH; + } + + // Deserialize 8-bit NvU8 primitive. + ((NvU8 *)(NvP64_VALUE(api->pBuffer)))[i] = (NvU8) finn_read_buffer(bp, 8); + + } + } + + } + + // Nullify pointer only if FINN manages memory allocation. + else + { + if (!deser_up) + api->pBuffer = NV_PTR_TO_NvP64(NULL); + } + + // Done + return NV_OK; +} + + +// Serialize each of the 4 field(s). +// 1 out of 3 independent field(s) are reordered to be before 1 dependent field(s). +static NV_STATUS finnSerializeMessage_NV2080_CTRL_RC_READ_VIRTUAL_MEM_PARAMS(const NV2080_CTRL_RC_READ_VIRTUAL_MEM_PARAMS *api, finn_bit_pump_for_write *bp, NvBool seri_up) +{ + // Serialize field-presence indicator for `hChannel`. + if (finn_write_buffer(bp, 1, 1)) + { + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + return NV_ERR_BUFFER_TOO_SMALL; + } + + // Serialize 32-bit NvU32 primitive. + if (finn_write_buffer(bp, api->hChannel, 32)) + { + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + return NV_ERR_BUFFER_TOO_SMALL; + } + + // Serialize field-presence indicator for `virtAddress`. + if (finn_write_buffer(bp, 1, 1)) + { + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + return NV_ERR_BUFFER_TOO_SMALL; + } + + // Serialize 64-bit NvU64 primitive. + if (finn_write_buffer(bp, api->virtAddress, 64)) + { + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + return NV_ERR_BUFFER_TOO_SMALL; + } + + // Serialize field-presence indicator for `bufferSize`. + if (finn_write_buffer(bp, 1, 1)) + { + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + return NV_ERR_BUFFER_TOO_SMALL; + } + + // Serialize 32-bit NvU32 primitive. + if (finn_write_buffer(bp, api->bufferSize, 32)) + { + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + return NV_ERR_BUFFER_TOO_SMALL; + } + + // Serialize data-presence (nonnull pointer) indicator. + if (finn_write_buffer(bp, !!(api->bufferPtr), 1)) + { + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + return NV_ERR_BUFFER_TOO_SMALL; + } + + // Skip if pointer is null. + if (api->bufferPtr) + { + // Serialize each element in `bufferPtr`. + { + NvLength i; + for (i = 0; i < (api->bufferSize); ++i) + { + // Serialize field-presence indicator for `bufferPtr[i]`. + if (finn_write_buffer(bp, 1, 1)) + { + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + return NV_ERR_BUFFER_TOO_SMALL; + } + + // Serialize 8-bit NvU8 primitive. + if (finn_write_buffer(bp, ((NvU8 *)(NvP64_VALUE(api->bufferPtr)))[i], 8)) + { + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + return NV_ERR_BUFFER_TOO_SMALL; + } + + } + } + + // Free memory that was allocated during downward deserialization. + if (seri_up && api->bufferPtr) + FINN_FREE(NvP64_VALUE(api->bufferPtr)); + } + + + // Done + return NV_OK; +} + + +// Deserialize each of the 4 field(s). +// 1 out of 3 independent field(s) are reordered to be before 1 dependent field(s). +static NV_STATUS finnDeserializeMessage_NV2080_CTRL_RC_READ_VIRTUAL_MEM_PARAMS(finn_bit_pump_for_read *bp, NV2080_CTRL_RC_READ_VIRTUAL_MEM_PARAMS *api, NvLength api_size, NvBool deser_up) +{ + // Check that the destination struct fits within the destination buffer. + if (sizeof(NV2080_CTRL_RC_READ_VIRTUAL_MEM_PARAMS) > api_size) + { + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + return NV_ERR_BUFFER_TOO_SMALL; + } + + // Check field-presence indicator for `hChannel`. + if (!finn_read_buffer(bp, 1)) + { + FINN_ERROR(NV_ERR_LIB_RM_VERSION_MISMATCH); + return NV_ERR_LIB_RM_VERSION_MISMATCH; + } + + // Deserialize 32-bit NvU32 primitive. + api->hChannel = (NvU32) finn_read_buffer(bp, 32); + + // Check field-presence indicator for `virtAddress`. + if (!finn_read_buffer(bp, 1)) + { + FINN_ERROR(NV_ERR_LIB_RM_VERSION_MISMATCH); + return NV_ERR_LIB_RM_VERSION_MISMATCH; + } + + // Deserialize 64-bit NvU64 primitive. + api->virtAddress = (NvU64) finn_read_buffer(bp, 64); + + // Check field-presence indicator for `bufferSize`. + if (!finn_read_buffer(bp, 1)) + { + FINN_ERROR(NV_ERR_LIB_RM_VERSION_MISMATCH); + return NV_ERR_LIB_RM_VERSION_MISMATCH; + } + + // Deserialize 32-bit NvU32 primitive. + api->bufferSize = (NvU32) finn_read_buffer(bp, 32); + + // Check data-presence (nonnull pointer) indicator for `bufferPtr`. + if (finn_read_buffer(bp, 1)) + { + // Allocate memory and set pointer when deserializing down. + // (Calling code is expected to do so when deserializing up.) + if (!deser_up) + { + // The data-presence indicator would have been false + // if there were no data to deserialize. + if ((api->bufferSize) * (sizeof(NvU8) /*bufferPtr[i]*/) /*bufferPtr*/ < 1) + { + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + return NV_ERR_BUFFER_TOO_SMALL; + } + + api->bufferPtr = NV_PTR_TO_NvP64(FINN_MALLOC((api->bufferSize) * (sizeof(NvU8) /*bufferPtr[i]*/) /*bufferPtr*/)); + if (!api->bufferPtr) + { + FINN_ERROR(NV_ERR_NO_MEMORY); + return NV_ERR_NO_MEMORY; + } + + FINN_MEMZERO(NvP64_VALUE(api->bufferPtr), (api->bufferSize) * (sizeof(NvU8) /*bufferPtr[i]*/) /*bufferPtr*/); + } + + // Otherwise the pointer must be provided by caller. + else if (!api->bufferPtr) + { + FINN_ERROR(NV_ERR_INVALID_POINTER); + return NV_ERR_INVALID_POINTER; + } + + // Deserialize each element in `bufferPtr`. + { + NvLength i; + for (i = 0; i < (api->bufferSize); ++i) + { + // Check field-presence indicator for `bufferPtr[i]`. + if (!finn_read_buffer(bp, 1)) + { + FINN_ERROR(NV_ERR_LIB_RM_VERSION_MISMATCH); + return NV_ERR_LIB_RM_VERSION_MISMATCH; + } + + // Deserialize 8-bit NvU8 primitive. + ((NvU8 *)(NvP64_VALUE(api->bufferPtr)))[i] = (NvU8) finn_read_buffer(bp, 8); + + } + } + + } + + // Nullify pointer only if FINN manages memory allocation. + else + { + if (!deser_up) + api->bufferPtr = NV_PTR_TO_NvP64(NULL); + } + + // Done + return NV_OK; +} + +#endif // (defined(NVRM)) + +#if (defined(NVRM)) + +// Serialize each of the 8 field(s). +// 1 out of 6 independent field(s) are reordered to be before 2 dependent field(s). +static NV_STATUS finnSerializeMessage_NV402C_CTRL_I2C_INDEXED_PARAMS(const NV402C_CTRL_I2C_INDEXED_PARAMS *api, finn_bit_pump_for_write *bp, NvBool seri_up) +{ + // Serialize field-presence indicator for `portId`. + if (finn_write_buffer(bp, 1, 1)) + { + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + return NV_ERR_BUFFER_TOO_SMALL; + } + + // Serialize 8-bit NvU8 primitive. + if (finn_write_buffer(bp, api->portId, 8)) + { + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + return NV_ERR_BUFFER_TOO_SMALL; + } + + // Serialize field-presence indicator for `bIsWrite`. + if (finn_write_buffer(bp, 1, 1)) + { + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + return NV_ERR_BUFFER_TOO_SMALL; + } + + // Serialize 8-bit NvU8 primitive. + if (finn_write_buffer(bp, api->bIsWrite, 8)) + { + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + return NV_ERR_BUFFER_TOO_SMALL; + } + + // Serialize field-presence indicator for `address`. + if (finn_write_buffer(bp, 1, 1)) + { + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + return NV_ERR_BUFFER_TOO_SMALL; + } + + // Serialize 16-bit NvU16 primitive. + if (finn_write_buffer(bp, api->address, 16)) + { + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + return NV_ERR_BUFFER_TOO_SMALL; + } + + // Serialize field-presence indicator for `flags`. + if (finn_write_buffer(bp, 1, 1)) + { + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + return NV_ERR_BUFFER_TOO_SMALL; + } + + // Serialize 32-bit NvU32 primitive. + if (finn_write_buffer(bp, api->flags, 32)) + { + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + return NV_ERR_BUFFER_TOO_SMALL; + } + + // Serialize field-presence indicator for `indexLength`. + if (finn_write_buffer(bp, 1, 1)) + { + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + return NV_ERR_BUFFER_TOO_SMALL; + } + + // Reject source data if it is out of range. + if (api->indexLength > NV402C_CTRL_I2C_INDEX_LENGTH_MAX) + { + FINN_ERROR(NV_ERR_OUT_OF_RANGE); + return NV_ERR_OUT_OF_RANGE; + } + + // Serialize 32-bit NvU32 primitive. + if (finn_write_buffer(bp, api->indexLength, 32)) + { + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + return NV_ERR_BUFFER_TOO_SMALL; + } + + // Serialize field-presence indicator for `messageLength`. + if (finn_write_buffer(bp, 1, 1)) + { + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + return NV_ERR_BUFFER_TOO_SMALL; + } + + // Serialize 32-bit NvU32 primitive. + if (finn_write_buffer(bp, api->messageLength, 32)) + { + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + return NV_ERR_BUFFER_TOO_SMALL; + } + + // Serialize each element in `index`. + { + NvLength i; + for (i = 0; i < NV402C_CTRL_I2C_INDEX_LENGTH_MAX; ++i) + { + // Serialize field-presence indicator for `index[i]`. + if (finn_write_buffer(bp, 1, 1)) + { + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + return NV_ERR_BUFFER_TOO_SMALL; + } + + // Serialize 8-bit NvU8 primitive. + if (finn_write_buffer(bp, (api->index)[i], 8)) + { + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + return NV_ERR_BUFFER_TOO_SMALL; + } + + } + } + + // Serialize data-presence (nonnull pointer) indicator. + if (finn_write_buffer(bp, !!(api->pMessage), 1)) + { + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + return NV_ERR_BUFFER_TOO_SMALL; + } + + // Skip if pointer is null. + if (api->pMessage) + { + // Serialize each element in `pMessage`. + { + NvLength i; + for (i = 0; i < (api->messageLength); ++i) + { + // Serialize field-presence indicator for `pMessage[i]`. + if (finn_write_buffer(bp, 1, 1)) + { + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + return NV_ERR_BUFFER_TOO_SMALL; + } + + // Serialize 8-bit NvU8 primitive. + if (finn_write_buffer(bp, ((NvU8 *)(NvP64_VALUE(api->pMessage)))[i], 8)) + { + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + return NV_ERR_BUFFER_TOO_SMALL; + } + + } + } + + // Free memory that was allocated during downward deserialization. + if (seri_up && api->pMessage) + FINN_FREE(NvP64_VALUE(api->pMessage)); + } + + + // Done + return NV_OK; +} + + +// Deserialize each of the 8 field(s). +// 1 out of 6 independent field(s) are reordered to be before 2 dependent field(s). +static NV_STATUS finnDeserializeMessage_NV402C_CTRL_I2C_INDEXED_PARAMS(finn_bit_pump_for_read *bp, NV402C_CTRL_I2C_INDEXED_PARAMS *api, NvLength api_size, NvBool deser_up) +{ + // Check that the destination struct fits within the destination buffer. + if (sizeof(NV402C_CTRL_I2C_INDEXED_PARAMS) > api_size) + { + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + return NV_ERR_BUFFER_TOO_SMALL; + } + + // Check field-presence indicator for `portId`. + if (!finn_read_buffer(bp, 1)) + { + FINN_ERROR(NV_ERR_LIB_RM_VERSION_MISMATCH); + return NV_ERR_LIB_RM_VERSION_MISMATCH; + } + + // Deserialize 8-bit NvU8 primitive. + api->portId = (NvU8) finn_read_buffer(bp, 8); + + // Check field-presence indicator for `bIsWrite`. + if (!finn_read_buffer(bp, 1)) + { + FINN_ERROR(NV_ERR_LIB_RM_VERSION_MISMATCH); + return NV_ERR_LIB_RM_VERSION_MISMATCH; + } + + // Deserialize 8-bit NvU8 primitive. + api->bIsWrite = (NvU8) finn_read_buffer(bp, 8); + + // Check field-presence indicator for `address`. + if (!finn_read_buffer(bp, 1)) + { + FINN_ERROR(NV_ERR_LIB_RM_VERSION_MISMATCH); + return NV_ERR_LIB_RM_VERSION_MISMATCH; + } + + // Deserialize 16-bit NvU16 primitive. + api->address = (NvU16) finn_read_buffer(bp, 16); + + // Check field-presence indicator for `flags`. + if (!finn_read_buffer(bp, 1)) + { + FINN_ERROR(NV_ERR_LIB_RM_VERSION_MISMATCH); + return NV_ERR_LIB_RM_VERSION_MISMATCH; + } + + // Deserialize 32-bit NvU32 primitive. + api->flags = (NvU32) finn_read_buffer(bp, 32); + + // Check field-presence indicator for `indexLength`. + if (!finn_read_buffer(bp, 1)) + { + FINN_ERROR(NV_ERR_LIB_RM_VERSION_MISMATCH); + return NV_ERR_LIB_RM_VERSION_MISMATCH; + } + + // Deserialize 32-bit NvU32 primitive. + api->indexLength = (NvU32) finn_read_buffer(bp, 32); + + // Reject deserialized data if it is out of range. + if (api->indexLength > NV402C_CTRL_I2C_INDEX_LENGTH_MAX) + { + FINN_ERROR(NV_ERR_OUT_OF_RANGE); + return NV_ERR_OUT_OF_RANGE; + } + + // Check field-presence indicator for `messageLength`. + if (!finn_read_buffer(bp, 1)) + { + FINN_ERROR(NV_ERR_LIB_RM_VERSION_MISMATCH); + return NV_ERR_LIB_RM_VERSION_MISMATCH; + } + + // Deserialize 32-bit NvU32 primitive. + api->messageLength = (NvU32) finn_read_buffer(bp, 32); + + // Deserialize each element in `index`. + { + NvLength i; + for (i = 0; i < NV402C_CTRL_I2C_INDEX_LENGTH_MAX; ++i) + { + // Check field-presence indicator for `index[i]`. + if (!finn_read_buffer(bp, 1)) + { + FINN_ERROR(NV_ERR_LIB_RM_VERSION_MISMATCH); + return NV_ERR_LIB_RM_VERSION_MISMATCH; + } + + // Deserialize 8-bit NvU8 primitive. + (api->index)[i] = (NvU8) finn_read_buffer(bp, 8); + + } + } + + // Check data-presence (nonnull pointer) indicator for `pMessage`. + if (finn_read_buffer(bp, 1)) + { + // Allocate memory and set pointer when deserializing down. + // (Calling code is expected to do so when deserializing up.) + if (!deser_up) + { + // The data-presence indicator would have been false + // if there were no data to deserialize. + if ((api->messageLength) * (sizeof(NvU8) /*pMessage[i]*/) /*pMessage*/ < 1) + { + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + return NV_ERR_BUFFER_TOO_SMALL; + } + + api->pMessage = NV_PTR_TO_NvP64(FINN_MALLOC((api->messageLength) * (sizeof(NvU8) /*pMessage[i]*/) /*pMessage*/)); + if (!api->pMessage) + { + FINN_ERROR(NV_ERR_NO_MEMORY); + return NV_ERR_NO_MEMORY; + } + + FINN_MEMZERO(NvP64_VALUE(api->pMessage), (api->messageLength) * (sizeof(NvU8) /*pMessage[i]*/) /*pMessage*/); + } + + // Otherwise the pointer must be provided by caller. + else if (!api->pMessage) + { + FINN_ERROR(NV_ERR_INVALID_POINTER); + return NV_ERR_INVALID_POINTER; + } + + // Deserialize each element in `pMessage`. + { + NvLength i; + for (i = 0; i < (api->messageLength); ++i) + { + // Check field-presence indicator for `pMessage[i]`. + if (!finn_read_buffer(bp, 1)) + { + FINN_ERROR(NV_ERR_LIB_RM_VERSION_MISMATCH); + return NV_ERR_LIB_RM_VERSION_MISMATCH; + } + + // Deserialize 8-bit NvU8 primitive. + ((NvU8 *)(NvP64_VALUE(api->pMessage)))[i] = (NvU8) finn_read_buffer(bp, 8); + + } + } + + } + + // Nullify pointer only if FINN manages memory allocation. + else + { + if (!deser_up) + api->pMessage = NV_PTR_TO_NvP64(NULL); + } + + // Done + return NV_OK; +} + + +// Serialize each of the 5 field(s). +static NV_STATUS finnSerializeMessage_NV402C_CTRL_I2C_TRANSACTION_PARAMS(const NV402C_CTRL_I2C_TRANSACTION_PARAMS *api, finn_bit_pump_for_write *bp, NvBool seri_up) +{ + // Serialize field-presence indicator for `portId`. + if (finn_write_buffer(bp, 1, 1)) + { + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + return NV_ERR_BUFFER_TOO_SMALL; + } + + // Serialize 8-bit NvU8 primitive. + if (finn_write_buffer(bp, api->portId, 8)) + { + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + return NV_ERR_BUFFER_TOO_SMALL; + } + + // Serialize field-presence indicator for `flags`. + if (finn_write_buffer(bp, 1, 1)) + { + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + return NV_ERR_BUFFER_TOO_SMALL; + } + + // Serialize 32-bit NvU32 primitive. + if (finn_write_buffer(bp, api->flags, 32)) + { + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + return NV_ERR_BUFFER_TOO_SMALL; + } + + // Serialize field-presence indicator for `deviceAddress`. + if (finn_write_buffer(bp, 1, 1)) + { + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + return NV_ERR_BUFFER_TOO_SMALL; + } + + // Serialize 16-bit NvU16 primitive. + if (finn_write_buffer(bp, api->deviceAddress, 16)) + { + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + return NV_ERR_BUFFER_TOO_SMALL; + } + + // Serialize field-presence indicator for `transType`. + if (finn_write_buffer(bp, 1, 1)) + { + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + return NV_ERR_BUFFER_TOO_SMALL; + } + + // Validate the enum value. + if (finnBadEnum_NV402C_CTRL_I2C_TRANSACTION_TYPE(api->transType)) + { + FINN_ERROR(NV_ERR_INVALID_ARGUMENT); + return NV_ERR_INVALID_ARGUMENT; + } + + // Serialize NV402C_CTRL_I2C_TRANSACTION_TYPE enum. + if (finn_write_buffer(bp, api->transType, 32)) + { + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + return NV_ERR_BUFFER_TOO_SMALL; + } + + // Serialize field-presence indicator for `transData`. + if (finn_write_buffer(bp, 1, 1)) + { + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + return NV_ERR_BUFFER_TOO_SMALL; + } + + // `transData` has 11 cases to serialize. + { + NV_STATUS status = finnSerializeUnion_NV402C_CTRL_I2C_TRANSACTION_DATA(&api->transData, bp, seri_up, api->transType); + if (status != NV_OK) + return status; + } + + + // Done + return NV_OK; +} + + +// Deserialize each of the 5 field(s). +static NV_STATUS finnDeserializeMessage_NV402C_CTRL_I2C_TRANSACTION_PARAMS(finn_bit_pump_for_read *bp, NV402C_CTRL_I2C_TRANSACTION_PARAMS *api, NvLength api_size, NvBool deser_up) +{ + // Check that the destination struct fits within the destination buffer. + if (sizeof(NV402C_CTRL_I2C_TRANSACTION_PARAMS) > api_size) + { + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + return NV_ERR_BUFFER_TOO_SMALL; + } + + // Check field-presence indicator for `portId`. + if (!finn_read_buffer(bp, 1)) + { + FINN_ERROR(NV_ERR_LIB_RM_VERSION_MISMATCH); + return NV_ERR_LIB_RM_VERSION_MISMATCH; + } + + // Deserialize 8-bit NvU8 primitive. + api->portId = (NvU8) finn_read_buffer(bp, 8); + + // Check field-presence indicator for `flags`. + if (!finn_read_buffer(bp, 1)) + { + FINN_ERROR(NV_ERR_LIB_RM_VERSION_MISMATCH); + return NV_ERR_LIB_RM_VERSION_MISMATCH; + } + + // Deserialize 32-bit NvU32 primitive. + api->flags = (NvU32) finn_read_buffer(bp, 32); + + // Check field-presence indicator for `deviceAddress`. + if (!finn_read_buffer(bp, 1)) + { + FINN_ERROR(NV_ERR_LIB_RM_VERSION_MISMATCH); + return NV_ERR_LIB_RM_VERSION_MISMATCH; + } + + // Deserialize 16-bit NvU16 primitive. + api->deviceAddress = (NvU16) finn_read_buffer(bp, 16); + + // Check field-presence indicator for `transType`. + if (!finn_read_buffer(bp, 1)) + { + FINN_ERROR(NV_ERR_LIB_RM_VERSION_MISMATCH); + return NV_ERR_LIB_RM_VERSION_MISMATCH; + } + + // Deserialize NV402C_CTRL_I2C_TRANSACTION_TYPE enum. + api->transType = (NV402C_CTRL_I2C_TRANSACTION_TYPE) finn_read_buffer(bp, 32); + + // Validate the enum value. + if (finnBadEnum_NV402C_CTRL_I2C_TRANSACTION_TYPE(api->transType)) + { + FINN_ERROR(NV_ERR_INVALID_ARGUMENT); + return NV_ERR_INVALID_ARGUMENT; + } + + // Check field-presence indicator for `transData`. + if (!finn_read_buffer(bp, 1)) + { + FINN_ERROR(NV_ERR_LIB_RM_VERSION_MISMATCH); + return NV_ERR_LIB_RM_VERSION_MISMATCH; + } + + // `transData` has 11 cases to deserialize. + { + NV_STATUS status = finnDeserializeUnion_NV402C_CTRL_I2C_TRANSACTION_DATA(bp, &api->transData, api_size, deser_up, api->transType); + if (status != NV_OK) + return status; + } + + // Done + return NV_OK; +} + + +// Serialize each of the 4 field(s). +static NV_STATUS finnSerializeMessage_NV83DE_CTRL_DEBUG_READ_MEMORY_PARAMS(const NV83DE_CTRL_DEBUG_READ_MEMORY_PARAMS *api, finn_bit_pump_for_write *bp, NvBool seri_up) +{ + // Serialize field-presence indicator for `hMemory`. + if (finn_write_buffer(bp, 1, 1)) + { + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + return NV_ERR_BUFFER_TOO_SMALL; + } + + // Serialize 32-bit NvU32 primitive. + if (finn_write_buffer(bp, api->hMemory, 32)) + { + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + return NV_ERR_BUFFER_TOO_SMALL; + } + + // Serialize field-presence indicator for `length`. + if (finn_write_buffer(bp, 1, 1)) + { + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + return NV_ERR_BUFFER_TOO_SMALL; + } + + // Serialize 32-bit NvU32 primitive. + if (finn_write_buffer(bp, api->length, 32)) + { + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + return NV_ERR_BUFFER_TOO_SMALL; + } + + // Serialize field-presence indicator for `offset`. + if (finn_write_buffer(bp, 1, 1)) + { + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + return NV_ERR_BUFFER_TOO_SMALL; + } + + // Serialize 64-bit NvU64 primitive. + if (finn_write_buffer(bp, api->offset, 64)) + { + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + return NV_ERR_BUFFER_TOO_SMALL; + } + + // Serialize data-presence (nonnull pointer) indicator. + if (finn_write_buffer(bp, !!(api->buffer), 1)) + { + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + return NV_ERR_BUFFER_TOO_SMALL; + } + + // Skip if pointer is null. + if (api->buffer) + { + // Serialize each element in `buffer`. + { + NvLength i; + for (i = 0; i < (api->length); ++i) + { + // Serialize field-presence indicator for `buffer[i]`. + if (finn_write_buffer(bp, 1, 1)) + { + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + return NV_ERR_BUFFER_TOO_SMALL; + } + + // Serialize 8-bit NvU8 primitive. + if (finn_write_buffer(bp, ((NvU8 *)(NvP64_VALUE(api->buffer)))[i], 8)) + { + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + return NV_ERR_BUFFER_TOO_SMALL; + } + + } + } + + // Free memory that was allocated during downward deserialization. + if (seri_up && api->buffer) + FINN_FREE(NvP64_VALUE(api->buffer)); + } + + + // Done + return NV_OK; +} + + +// Deserialize each of the 4 field(s). +static NV_STATUS finnDeserializeMessage_NV83DE_CTRL_DEBUG_READ_MEMORY_PARAMS(finn_bit_pump_for_read *bp, NV83DE_CTRL_DEBUG_READ_MEMORY_PARAMS *api, NvLength api_size, NvBool deser_up) +{ + // Check that the destination struct fits within the destination buffer. + if (sizeof(NV83DE_CTRL_DEBUG_READ_MEMORY_PARAMS) > api_size) + { + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + return NV_ERR_BUFFER_TOO_SMALL; + } + + // Check field-presence indicator for `hMemory`. + if (!finn_read_buffer(bp, 1)) + { + FINN_ERROR(NV_ERR_LIB_RM_VERSION_MISMATCH); + return NV_ERR_LIB_RM_VERSION_MISMATCH; + } + + // Deserialize 32-bit NvU32 primitive. + api->hMemory = (NvU32) finn_read_buffer(bp, 32); + + // Check field-presence indicator for `length`. + if (!finn_read_buffer(bp, 1)) + { + FINN_ERROR(NV_ERR_LIB_RM_VERSION_MISMATCH); + return NV_ERR_LIB_RM_VERSION_MISMATCH; + } + + // Deserialize 32-bit NvU32 primitive. + api->length = (NvU32) finn_read_buffer(bp, 32); + + // Check field-presence indicator for `offset`. + if (!finn_read_buffer(bp, 1)) + { + FINN_ERROR(NV_ERR_LIB_RM_VERSION_MISMATCH); + return NV_ERR_LIB_RM_VERSION_MISMATCH; + } + + // Deserialize 64-bit NvU64 primitive. + api->offset = (NvU64) finn_read_buffer(bp, 64); + + // Check data-presence (nonnull pointer) indicator for `buffer`. + if (finn_read_buffer(bp, 1)) + { + // Allocate memory and set pointer when deserializing down. + // (Calling code is expected to do so when deserializing up.) + if (!deser_up) + { + // The data-presence indicator would have been false + // if there were no data to deserialize. + if ((api->length) * (sizeof(NvU8) /*buffer[i]*/) /*buffer*/ < 1) + { + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + return NV_ERR_BUFFER_TOO_SMALL; + } + + api->buffer = NV_PTR_TO_NvP64(FINN_MALLOC((api->length) * (sizeof(NvU8) /*buffer[i]*/) /*buffer*/)); + if (!api->buffer) + { + FINN_ERROR(NV_ERR_NO_MEMORY); + return NV_ERR_NO_MEMORY; + } + + FINN_MEMZERO(NvP64_VALUE(api->buffer), (api->length) * (sizeof(NvU8) /*buffer[i]*/) /*buffer*/); + } + + // Otherwise the pointer must be provided by caller. + else if (!api->buffer) + { + FINN_ERROR(NV_ERR_INVALID_POINTER); + return NV_ERR_INVALID_POINTER; + } + + // Deserialize each element in `buffer`. + { + NvLength i; + for (i = 0; i < (api->length); ++i) + { + // Check field-presence indicator for `buffer[i]`. + if (!finn_read_buffer(bp, 1)) + { + FINN_ERROR(NV_ERR_LIB_RM_VERSION_MISMATCH); + return NV_ERR_LIB_RM_VERSION_MISMATCH; + } + + // Deserialize 8-bit NvU8 primitive. + ((NvU8 *)(NvP64_VALUE(api->buffer)))[i] = (NvU8) finn_read_buffer(bp, 8); + + } + } + + } + + // Nullify pointer only if FINN manages memory allocation. + else + { + if (!deser_up) + api->buffer = NV_PTR_TO_NvP64(NULL); + } + + // Done + return NV_OK; +} + + +// Serialize each of the 4 field(s). +static NV_STATUS finnSerializeMessage_NV83DE_CTRL_DEBUG_WRITE_MEMORY_PARAMS(const NV83DE_CTRL_DEBUG_WRITE_MEMORY_PARAMS *api, finn_bit_pump_for_write *bp, NvBool seri_up) +{ + // Serialize field-presence indicator for `hMemory`. + if (finn_write_buffer(bp, 1, 1)) + { + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + return NV_ERR_BUFFER_TOO_SMALL; + } + + // Serialize 32-bit NvU32 primitive. + if (finn_write_buffer(bp, api->hMemory, 32)) + { + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + return NV_ERR_BUFFER_TOO_SMALL; + } + + // Serialize field-presence indicator for `length`. + if (finn_write_buffer(bp, 1, 1)) + { + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + return NV_ERR_BUFFER_TOO_SMALL; + } + + // Serialize 32-bit NvU32 primitive. + if (finn_write_buffer(bp, api->length, 32)) + { + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + return NV_ERR_BUFFER_TOO_SMALL; + } + + // Serialize field-presence indicator for `offset`. + if (finn_write_buffer(bp, 1, 1)) + { + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + return NV_ERR_BUFFER_TOO_SMALL; + } + + // Serialize 64-bit NvU64 primitive. + if (finn_write_buffer(bp, api->offset, 64)) + { + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + return NV_ERR_BUFFER_TOO_SMALL; + } + + // Serialize data-presence (nonnull pointer) indicator. + if (finn_write_buffer(bp, !!(api->buffer), 1)) + { + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + return NV_ERR_BUFFER_TOO_SMALL; + } + + // Skip if pointer is null. + if (api->buffer) + { + // Serialize each element in `buffer`. + { + NvLength i; + for (i = 0; i < (api->length); ++i) + { + // Serialize field-presence indicator for `buffer[i]`. + if (finn_write_buffer(bp, 1, 1)) + { + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + return NV_ERR_BUFFER_TOO_SMALL; + } + + // Serialize 8-bit NvU8 primitive. + if (finn_write_buffer(bp, ((NvU8 *)(NvP64_VALUE(api->buffer)))[i], 8)) + { + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + return NV_ERR_BUFFER_TOO_SMALL; + } + + } + } + + // Free memory that was allocated during downward deserialization. + if (seri_up && api->buffer) + FINN_FREE(NvP64_VALUE(api->buffer)); + } + + + // Done + return NV_OK; +} + + +// Deserialize each of the 4 field(s). +static NV_STATUS finnDeserializeMessage_NV83DE_CTRL_DEBUG_WRITE_MEMORY_PARAMS(finn_bit_pump_for_read *bp, NV83DE_CTRL_DEBUG_WRITE_MEMORY_PARAMS *api, NvLength api_size, NvBool deser_up) +{ + // Check that the destination struct fits within the destination buffer. + if (sizeof(NV83DE_CTRL_DEBUG_WRITE_MEMORY_PARAMS) > api_size) + { + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + return NV_ERR_BUFFER_TOO_SMALL; + } + + // Check field-presence indicator for `hMemory`. + if (!finn_read_buffer(bp, 1)) + { + FINN_ERROR(NV_ERR_LIB_RM_VERSION_MISMATCH); + return NV_ERR_LIB_RM_VERSION_MISMATCH; + } + + // Deserialize 32-bit NvU32 primitive. + api->hMemory = (NvU32) finn_read_buffer(bp, 32); + + // Check field-presence indicator for `length`. + if (!finn_read_buffer(bp, 1)) + { + FINN_ERROR(NV_ERR_LIB_RM_VERSION_MISMATCH); + return NV_ERR_LIB_RM_VERSION_MISMATCH; + } + + // Deserialize 32-bit NvU32 primitive. + api->length = (NvU32) finn_read_buffer(bp, 32); + + // Check field-presence indicator for `offset`. + if (!finn_read_buffer(bp, 1)) + { + FINN_ERROR(NV_ERR_LIB_RM_VERSION_MISMATCH); + return NV_ERR_LIB_RM_VERSION_MISMATCH; + } + + // Deserialize 64-bit NvU64 primitive. + api->offset = (NvU64) finn_read_buffer(bp, 64); + + // Check data-presence (nonnull pointer) indicator for `buffer`. + if (finn_read_buffer(bp, 1)) + { + // Allocate memory and set pointer when deserializing down. + // (Calling code is expected to do so when deserializing up.) + if (!deser_up) + { + // The data-presence indicator would have been false + // if there were no data to deserialize. + if ((api->length) * (sizeof(NvU8) /*buffer[i]*/) /*buffer*/ < 1) + { + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + return NV_ERR_BUFFER_TOO_SMALL; + } + + api->buffer = NV_PTR_TO_NvP64(FINN_MALLOC((api->length) * (sizeof(NvU8) /*buffer[i]*/) /*buffer*/)); + if (!api->buffer) + { + FINN_ERROR(NV_ERR_NO_MEMORY); + return NV_ERR_NO_MEMORY; + } + + FINN_MEMZERO(NvP64_VALUE(api->buffer), (api->length) * (sizeof(NvU8) /*buffer[i]*/) /*buffer*/); + } + + // Otherwise the pointer must be provided by caller. + else if (!api->buffer) + { + FINN_ERROR(NV_ERR_INVALID_POINTER); + return NV_ERR_INVALID_POINTER; + } + + // Deserialize each element in `buffer`. + { + NvLength i; + for (i = 0; i < (api->length); ++i) + { + // Check field-presence indicator for `buffer[i]`. + if (!finn_read_buffer(bp, 1)) + { + FINN_ERROR(NV_ERR_LIB_RM_VERSION_MISMATCH); + return NV_ERR_LIB_RM_VERSION_MISMATCH; + } + + // Deserialize 8-bit NvU8 primitive. + ((NvU8 *)(NvP64_VALUE(api->buffer)))[i] = (NvU8) finn_read_buffer(bp, 8); + + } + } + + } + + // Nullify pointer only if FINN manages memory allocation. + else + { + if (!deser_up) + api->buffer = NV_PTR_TO_NvP64(NULL); + } + + // Done + return NV_OK; +} + + +// Serialize each of the 1 field(s). +static NV_STATUS finnSerializeMessage_NVB06F_CTRL_CMD_RESTORE_ENGINE_CTX_DATA_FINN_PARAMS(const NVB06F_CTRL_CMD_RESTORE_ENGINE_CTX_DATA_FINN_PARAMS *api, finn_bit_pump_for_write *bp, NvBool seri_up) +{ + // Serialize field-presence indicator for `params`. + if (finn_write_buffer(bp, 1, 1)) + { + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + return NV_ERR_BUFFER_TOO_SMALL; + } + + // Message has 3 field(s) to be serialized. + { + NV_STATUS status = finnSerializeMessage_NVB06F_CTRL_SAVE_ENGINE_CTX_DATA_PARAMS(&api->params, bp, seri_up); + if (status != NV_OK) + return status; + } + + + // Done + return NV_OK; +} + + +// Deserialize each of the 1 field(s). +static NV_STATUS finnDeserializeMessage_NVB06F_CTRL_CMD_RESTORE_ENGINE_CTX_DATA_FINN_PARAMS(finn_bit_pump_for_read *bp, NVB06F_CTRL_CMD_RESTORE_ENGINE_CTX_DATA_FINN_PARAMS *api, NvLength api_size, NvBool deser_up) +{ + // Check that the destination struct fits within the destination buffer. + if (sizeof(NVB06F_CTRL_CMD_RESTORE_ENGINE_CTX_DATA_FINN_PARAMS) > api_size) + { + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + return NV_ERR_BUFFER_TOO_SMALL; + } + + // Check field-presence indicator for `params`. + if (!finn_read_buffer(bp, 1)) + { + FINN_ERROR(NV_ERR_LIB_RM_VERSION_MISMATCH); + return NV_ERR_LIB_RM_VERSION_MISMATCH; + } + + // Message has 3 field(s) to be deserialized. + { + NV_STATUS status = finnDeserializeMessage_NVB06F_CTRL_SAVE_ENGINE_CTX_DATA_PARAMS(bp, &api->params, sizeof(NVB06F_CTRL_SAVE_ENGINE_CTX_DATA_PARAMS), deser_up); + if (status != NV_OK) + return status; + } + + // Done + return NV_OK; +} + + +// Serialize each of the 3 field(s). +static NV_STATUS finnSerializeMessage_NVB06F_CTRL_GET_ENGINE_CTX_DATA_PARAMS(const NVB06F_CTRL_GET_ENGINE_CTX_DATA_PARAMS *api, finn_bit_pump_for_write *bp, NvBool seri_up) +{ + // Serialize field-presence indicator for `engineID`. + if (finn_write_buffer(bp, 1, 1)) + { + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + return NV_ERR_BUFFER_TOO_SMALL; + } + + // Serialize 32-bit NvU32 primitive. + if (finn_write_buffer(bp, api->engineID, 32)) + { + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + return NV_ERR_BUFFER_TOO_SMALL; + } + + // Serialize field-presence indicator for `size`. + if (finn_write_buffer(bp, 1, 1)) + { + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + return NV_ERR_BUFFER_TOO_SMALL; + } + + // Serialize 32-bit NvU32 primitive. + if (finn_write_buffer(bp, api->size, 32)) + { + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + return NV_ERR_BUFFER_TOO_SMALL; + } + + // Serialize data-presence (nonnull pointer) indicator. + if (finn_write_buffer(bp, !!(api->pEngineCtxBuff), 1)) + { + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + return NV_ERR_BUFFER_TOO_SMALL; + } + + // Skip if pointer is null. + if (api->pEngineCtxBuff) + { + // Serialize each element in `pEngineCtxBuff`. + { + NvLength i; + for (i = 0; i < (api->size); ++i) + { + // Serialize field-presence indicator for `pEngineCtxBuff[i]`. + if (finn_write_buffer(bp, 1, 1)) + { + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + return NV_ERR_BUFFER_TOO_SMALL; + } + + // Serialize 8-bit NvU8 primitive. + if (finn_write_buffer(bp, ((NvU8 *)(NvP64_VALUE(api->pEngineCtxBuff)))[i], 8)) + { + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + return NV_ERR_BUFFER_TOO_SMALL; + } + + } + } + + // Free memory that was allocated during downward deserialization. + if (seri_up && api->pEngineCtxBuff) + FINN_FREE(NvP64_VALUE(api->pEngineCtxBuff)); + } + + + // Done + return NV_OK; +} + + +// Deserialize each of the 3 field(s). +static NV_STATUS finnDeserializeMessage_NVB06F_CTRL_GET_ENGINE_CTX_DATA_PARAMS(finn_bit_pump_for_read *bp, NVB06F_CTRL_GET_ENGINE_CTX_DATA_PARAMS *api, NvLength api_size, NvBool deser_up) +{ + // Check that the destination struct fits within the destination buffer. + if (sizeof(NVB06F_CTRL_GET_ENGINE_CTX_DATA_PARAMS) > api_size) + { + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + return NV_ERR_BUFFER_TOO_SMALL; + } + + // Check field-presence indicator for `engineID`. + if (!finn_read_buffer(bp, 1)) + { + FINN_ERROR(NV_ERR_LIB_RM_VERSION_MISMATCH); + return NV_ERR_LIB_RM_VERSION_MISMATCH; + } + + // Deserialize 32-bit NvU32 primitive. + api->engineID = (NvU32) finn_read_buffer(bp, 32); + + // Check field-presence indicator for `size`. + if (!finn_read_buffer(bp, 1)) + { + FINN_ERROR(NV_ERR_LIB_RM_VERSION_MISMATCH); + return NV_ERR_LIB_RM_VERSION_MISMATCH; + } + + // Deserialize 32-bit NvU32 primitive. + api->size = (NvU32) finn_read_buffer(bp, 32); + + // Check data-presence (nonnull pointer) indicator for `pEngineCtxBuff`. + if (finn_read_buffer(bp, 1)) + { + // Allocate memory and set pointer when deserializing down. + // (Calling code is expected to do so when deserializing up.) + if (!deser_up) + { + // The data-presence indicator would have been false + // if there were no data to deserialize. + if ((api->size) * (sizeof(NvU8) /*pEngineCtxBuff[i]*/) /*pEngineCtxBuff*/ < 1) + { + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + return NV_ERR_BUFFER_TOO_SMALL; + } + + api->pEngineCtxBuff = NV_PTR_TO_NvP64(FINN_MALLOC((api->size) * (sizeof(NvU8) /*pEngineCtxBuff[i]*/) /*pEngineCtxBuff*/)); + if (!api->pEngineCtxBuff) + { + FINN_ERROR(NV_ERR_NO_MEMORY); + return NV_ERR_NO_MEMORY; + } + + FINN_MEMZERO(NvP64_VALUE(api->pEngineCtxBuff), (api->size) * (sizeof(NvU8) /*pEngineCtxBuff[i]*/) /*pEngineCtxBuff*/); + } + + // Otherwise the pointer must be provided by caller. + else if (!api->pEngineCtxBuff) + { + FINN_ERROR(NV_ERR_INVALID_POINTER); + return NV_ERR_INVALID_POINTER; + } + + // Deserialize each element in `pEngineCtxBuff`. + { + NvLength i; + for (i = 0; i < (api->size); ++i) + { + // Check field-presence indicator for `pEngineCtxBuff[i]`. + if (!finn_read_buffer(bp, 1)) + { + FINN_ERROR(NV_ERR_LIB_RM_VERSION_MISMATCH); + return NV_ERR_LIB_RM_VERSION_MISMATCH; + } + + // Deserialize 8-bit NvU8 primitive. + ((NvU8 *)(NvP64_VALUE(api->pEngineCtxBuff)))[i] = (NvU8) finn_read_buffer(bp, 8); + + } + } + + } + + // Nullify pointer only if FINN manages memory allocation. + else + { + if (!deser_up) + api->pEngineCtxBuff = NV_PTR_TO_NvP64(NULL); + } + + // Done + return NV_OK; +} + + +// Serialize each of the 3 field(s). +static NV_STATUS finnSerializeMessage_NVB06F_CTRL_SAVE_ENGINE_CTX_DATA_PARAMS(const NVB06F_CTRL_SAVE_ENGINE_CTX_DATA_PARAMS *api, finn_bit_pump_for_write *bp, NvBool seri_up) +{ + // Serialize field-presence indicator for `engineID`. + if (finn_write_buffer(bp, 1, 1)) + { + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + return NV_ERR_BUFFER_TOO_SMALL; + } + + // Serialize 32-bit NvU32 primitive. + if (finn_write_buffer(bp, api->engineID, 32)) + { + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + return NV_ERR_BUFFER_TOO_SMALL; + } + + // Serialize field-presence indicator for `size`. + if (finn_write_buffer(bp, 1, 1)) + { + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + return NV_ERR_BUFFER_TOO_SMALL; + } + + // Serialize 32-bit NvU32 primitive. + if (finn_write_buffer(bp, api->size, 32)) + { + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + return NV_ERR_BUFFER_TOO_SMALL; + } + + // Serialize each element in `engineCtxBuff`. + { + NvLength i; + for (i = 0; i < NVB06F_CTRL_ENGINE_CTX_BUFFER_SIZE_MAX; ++i) + { + // Serialize field-presence indicator for `engineCtxBuff[i]`. + if (finn_write_buffer(bp, 1, 1)) + { + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + return NV_ERR_BUFFER_TOO_SMALL; + } + + // Serialize 8-bit NvU8 primitive. + if (finn_write_buffer(bp, (api->engineCtxBuff)[i], 8)) + { + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + return NV_ERR_BUFFER_TOO_SMALL; + } + + } + } + + + // Done + return NV_OK; +} + + +// Deserialize each of the 3 field(s). +static NV_STATUS finnDeserializeMessage_NVB06F_CTRL_SAVE_ENGINE_CTX_DATA_PARAMS(finn_bit_pump_for_read *bp, NVB06F_CTRL_SAVE_ENGINE_CTX_DATA_PARAMS *api, NvLength api_size, NvBool deser_up) +{ + // Check that the destination struct fits within the destination buffer. + if (sizeof(NVB06F_CTRL_SAVE_ENGINE_CTX_DATA_PARAMS) > api_size) + { + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + return NV_ERR_BUFFER_TOO_SMALL; + } + + // Check field-presence indicator for `engineID`. + if (!finn_read_buffer(bp, 1)) + { + FINN_ERROR(NV_ERR_LIB_RM_VERSION_MISMATCH); + return NV_ERR_LIB_RM_VERSION_MISMATCH; + } + + // Deserialize 32-bit NvU32 primitive. + api->engineID = (NvU32) finn_read_buffer(bp, 32); + + // Check field-presence indicator for `size`. + if (!finn_read_buffer(bp, 1)) + { + FINN_ERROR(NV_ERR_LIB_RM_VERSION_MISMATCH); + return NV_ERR_LIB_RM_VERSION_MISMATCH; + } + + // Deserialize 32-bit NvU32 primitive. + api->size = (NvU32) finn_read_buffer(bp, 32); + + // Deserialize each element in `engineCtxBuff`. + { + NvLength i; + for (i = 0; i < NVB06F_CTRL_ENGINE_CTX_BUFFER_SIZE_MAX; ++i) + { + // Check field-presence indicator for `engineCtxBuff[i]`. + if (!finn_read_buffer(bp, 1)) + { + FINN_ERROR(NV_ERR_LIB_RM_VERSION_MISMATCH); + return NV_ERR_LIB_RM_VERSION_MISMATCH; + } + + // Deserialize 8-bit NvU8 primitive. + (api->engineCtxBuff)[i] = (NvU8) finn_read_buffer(bp, 8); + + } + } + + // Done + return NV_OK; +} + + +// Serialize each of the 3 field(s). +static NV_STATUS finnSerializeRecord_NV0080_CTRL_DMA_UPDATE_PDE_2_PAGE_TABLE_PARAMS(const NV0080_CTRL_DMA_UPDATE_PDE_2_PAGE_TABLE_PARAMS *api, finn_bit_pump_for_write *bp, NvBool seri_up) +{ + // Serialize field-presence indicator for `physAddr`. + if (finn_write_buffer(bp, 1, 1)) + { + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + return NV_ERR_BUFFER_TOO_SMALL; + } + + // Serialize 64-bit NvU64 primitive. + if (finn_write_buffer(bp, api->physAddr, 64)) + { + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + return NV_ERR_BUFFER_TOO_SMALL; + } + + // Serialize field-presence indicator for `numEntries`. + if (finn_write_buffer(bp, 1, 1)) + { + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + return NV_ERR_BUFFER_TOO_SMALL; + } + + // Serialize 32-bit NvU32 primitive. + if (finn_write_buffer(bp, api->numEntries, 32)) + { + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + return NV_ERR_BUFFER_TOO_SMALL; + } + + // Serialize field-presence indicator for `aperture`. + if (finn_write_buffer(bp, 1, 1)) + { + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + return NV_ERR_BUFFER_TOO_SMALL; + } + + // Serialize 32-bit NvU32 primitive. + if (finn_write_buffer(bp, api->aperture, 32)) + { + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + return NV_ERR_BUFFER_TOO_SMALL; + } + + + // Done + return NV_OK; +} + + +// Deserialize each of the 3 field(s). +static NV_STATUS finnDeserializeRecord_NV0080_CTRL_DMA_UPDATE_PDE_2_PAGE_TABLE_PARAMS(finn_bit_pump_for_read *bp, NV0080_CTRL_DMA_UPDATE_PDE_2_PAGE_TABLE_PARAMS *api, NvLength api_size, NvBool deser_up) +{ + // Check that the destination struct fits within the destination buffer. + if (sizeof(NV0080_CTRL_DMA_UPDATE_PDE_2_PAGE_TABLE_PARAMS) > api_size) + { + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + return NV_ERR_BUFFER_TOO_SMALL; + } + + // Check field-presence indicator for `physAddr`. + if (!finn_read_buffer(bp, 1)) + { + FINN_ERROR(NV_ERR_LIB_RM_VERSION_MISMATCH); + return NV_ERR_LIB_RM_VERSION_MISMATCH; + } + + // Deserialize 64-bit NvU64 primitive. + api->physAddr = (NvU64) finn_read_buffer(bp, 64); + + // Check field-presence indicator for `numEntries`. + if (!finn_read_buffer(bp, 1)) + { + FINN_ERROR(NV_ERR_LIB_RM_VERSION_MISMATCH); + return NV_ERR_LIB_RM_VERSION_MISMATCH; + } + + // Deserialize 32-bit NvU32 primitive. + api->numEntries = (NvU32) finn_read_buffer(bp, 32); + + // Check field-presence indicator for `aperture`. + if (!finn_read_buffer(bp, 1)) + { + FINN_ERROR(NV_ERR_LIB_RM_VERSION_MISMATCH); + return NV_ERR_LIB_RM_VERSION_MISMATCH; + } + + // Deserialize 32-bit NvU32 primitive. + api->aperture = (NvU32) finn_read_buffer(bp, 32); + + // Done + return NV_OK; +} + +#endif // (defined(NVRM)) + + +// Serialize each of the 1 field(s). +static NV_STATUS finnSerializeRecord_NV0080_CTRL_FIFO_CHANNEL(const NV0080_CTRL_FIFO_CHANNEL *api, finn_bit_pump_for_write *bp, NvBool seri_up) +{ + // Serialize field-presence indicator for `hChannel`. + if (finn_write_buffer(bp, 1, 1)) + { + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + return NV_ERR_BUFFER_TOO_SMALL; + } + + // Serialize 32-bit NvU32 primitive. + if (finn_write_buffer(bp, api->hChannel, 32)) + { + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + return NV_ERR_BUFFER_TOO_SMALL; + } + + + // Done + return NV_OK; +} + + +// Deserialize each of the 1 field(s). +static NV_STATUS finnDeserializeRecord_NV0080_CTRL_FIFO_CHANNEL(finn_bit_pump_for_read *bp, NV0080_CTRL_FIFO_CHANNEL *api, NvLength api_size, NvBool deser_up) +{ + // Check that the destination struct fits within the destination buffer. + if (sizeof(NV0080_CTRL_FIFO_CHANNEL) > api_size) + { + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + return NV_ERR_BUFFER_TOO_SMALL; + } + + // Check field-presence indicator for `hChannel`. + if (!finn_read_buffer(bp, 1)) + { + FINN_ERROR(NV_ERR_LIB_RM_VERSION_MISMATCH); + return NV_ERR_LIB_RM_VERSION_MISMATCH; + } + + // Deserialize 32-bit NvU32 primitive. + api->hChannel = (NvU32) finn_read_buffer(bp, 32); + + // Done + return NV_OK; +} + +#if (defined(NVRM)) + +// Serialize each of the 5 field(s). +static NV_STATUS finnSerializeRecord_NV2080_CTRL_GPUMON_SAMPLES(const NV2080_CTRL_GPUMON_SAMPLES *api, finn_bit_pump_for_write *bp, NvBool seri_up) +{ + // Serialize field-presence indicator for `type`. + if (finn_write_buffer(bp, 1, 1)) + { + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + return NV_ERR_BUFFER_TOO_SMALL; + } + + // Serialize 8-bit NvU8 primitive. + if (finn_write_buffer(bp, api->type, 8)) + { + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + return NV_ERR_BUFFER_TOO_SMALL; + } + + // Serialize field-presence indicator for `bufSize`. + if (finn_write_buffer(bp, 1, 1)) + { + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + return NV_ERR_BUFFER_TOO_SMALL; + } + + // Serialize 32-bit NvU32 primitive. + if (finn_write_buffer(bp, api->bufSize, 32)) + { + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + return NV_ERR_BUFFER_TOO_SMALL; + } + + // Serialize field-presence indicator for `count`. + if (finn_write_buffer(bp, 1, 1)) + { + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + return NV_ERR_BUFFER_TOO_SMALL; + } + + // Serialize 32-bit NvU32 primitive. + if (finn_write_buffer(bp, api->count, 32)) + { + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + return NV_ERR_BUFFER_TOO_SMALL; + } + + // Serialize field-presence indicator for `tracker`. + if (finn_write_buffer(bp, 1, 1)) + { + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + return NV_ERR_BUFFER_TOO_SMALL; + } + + // Serialize 32-bit NvU32 primitive. + if (finn_write_buffer(bp, api->tracker, 32)) + { + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + return NV_ERR_BUFFER_TOO_SMALL; + } + + // Serialize data-presence (nonnull pointer) indicator. + if (finn_write_buffer(bp, !!(api->pSamples), 1)) + { + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + return NV_ERR_BUFFER_TOO_SMALL; + } + + // Skip if pointer is null. + if (api->pSamples) + { + // Serialize each element in `pSamples`. + { + NvLength i; + for (i = 0; i < (api->bufSize); ++i) + { + // Serialize field-presence indicator for `pSamples[i]`. + if (finn_write_buffer(bp, 1, 1)) + { + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + return NV_ERR_BUFFER_TOO_SMALL; + } + + // Serialize 8-bit NvU8 primitive. + if (finn_write_buffer(bp, ((NvU8 *)(NvP64_VALUE(api->pSamples)))[i], 8)) + { + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + return NV_ERR_BUFFER_TOO_SMALL; + } + + } + } + + // Free memory that was allocated during downward deserialization. + if (seri_up && api->pSamples) + FINN_FREE(NvP64_VALUE(api->pSamples)); + } + + + // Done + return NV_OK; +} + + +// Deserialize each of the 5 field(s). +static NV_STATUS finnDeserializeRecord_NV2080_CTRL_GPUMON_SAMPLES(finn_bit_pump_for_read *bp, NV2080_CTRL_GPUMON_SAMPLES *api, NvLength api_size, NvBool deser_up) +{ + // Check that the destination struct fits within the destination buffer. + if (sizeof(NV2080_CTRL_GPUMON_SAMPLES) > api_size) + { + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + return NV_ERR_BUFFER_TOO_SMALL; + } + + // Check field-presence indicator for `type`. + if (!finn_read_buffer(bp, 1)) + { + FINN_ERROR(NV_ERR_LIB_RM_VERSION_MISMATCH); + return NV_ERR_LIB_RM_VERSION_MISMATCH; + } + + // Deserialize 8-bit NvU8 primitive. + api->type = (NvU8) finn_read_buffer(bp, 8); + + // Check field-presence indicator for `bufSize`. + if (!finn_read_buffer(bp, 1)) + { + FINN_ERROR(NV_ERR_LIB_RM_VERSION_MISMATCH); + return NV_ERR_LIB_RM_VERSION_MISMATCH; + } + + // Deserialize 32-bit NvU32 primitive. + api->bufSize = (NvU32) finn_read_buffer(bp, 32); + + // Check field-presence indicator for `count`. + if (!finn_read_buffer(bp, 1)) + { + FINN_ERROR(NV_ERR_LIB_RM_VERSION_MISMATCH); + return NV_ERR_LIB_RM_VERSION_MISMATCH; + } + + // Deserialize 32-bit NvU32 primitive. + api->count = (NvU32) finn_read_buffer(bp, 32); + + // Check field-presence indicator for `tracker`. + if (!finn_read_buffer(bp, 1)) + { + FINN_ERROR(NV_ERR_LIB_RM_VERSION_MISMATCH); + return NV_ERR_LIB_RM_VERSION_MISMATCH; + } + + // Deserialize 32-bit NvU32 primitive. + api->tracker = (NvU32) finn_read_buffer(bp, 32); + + // Check data-presence (nonnull pointer) indicator for `pSamples`. + if (finn_read_buffer(bp, 1)) + { + // Allocate memory and set pointer when deserializing down. + // (Calling code is expected to do so when deserializing up.) + if (!deser_up) + { + // The data-presence indicator would have been false + // if there were no data to deserialize. + if ((api->bufSize) * (sizeof(NvU8) /*pSamples[i]*/) /*pSamples*/ < 1) + { + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + return NV_ERR_BUFFER_TOO_SMALL; + } + + api->pSamples = NV_PTR_TO_NvP64(FINN_MALLOC((api->bufSize) * (sizeof(NvU8) /*pSamples[i]*/) /*pSamples*/)); + if (!api->pSamples) + { + FINN_ERROR(NV_ERR_NO_MEMORY); + return NV_ERR_NO_MEMORY; + } + + FINN_MEMZERO(NvP64_VALUE(api->pSamples), (api->bufSize) * (sizeof(NvU8) /*pSamples[i]*/) /*pSamples*/); + } + + // Otherwise the pointer must be provided by caller. + else if (!api->pSamples) + { + FINN_ERROR(NV_ERR_INVALID_POINTER); + return NV_ERR_INVALID_POINTER; + } + + // Deserialize each element in `pSamples`. + { + NvLength i; + for (i = 0; i < (api->bufSize); ++i) + { + // Check field-presence indicator for `pSamples[i]`. + if (!finn_read_buffer(bp, 1)) + { + FINN_ERROR(NV_ERR_LIB_RM_VERSION_MISMATCH); + return NV_ERR_LIB_RM_VERSION_MISMATCH; + } + + // Deserialize 8-bit NvU8 primitive. + ((NvU8 *)(NvP64_VALUE(api->pSamples)))[i] = (NvU8) finn_read_buffer(bp, 8); + + } + } + + } + + // Nullify pointer only if FINN manages memory allocation. + else + { + if (!deser_up) + api->pSamples = NV_PTR_TO_NvP64(NULL); + } + + // Done + return NV_OK; +} + +#endif // (defined(NVRM)) + +#if (defined(NVRM)) + +// Serialize each of the 3 field(s). +static NV_STATUS finnSerializeRecord_NV402C_CTRL_I2C_TRANSACTION_DATA_I2C_BLOCK_RW(const NV402C_CTRL_I2C_TRANSACTION_DATA_I2C_BLOCK_RW *api, finn_bit_pump_for_write *bp, NvBool seri_up) +{ + // Serialize field-presence indicator for `bWrite`. + if (finn_write_buffer(bp, 1, 1)) + { + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + return NV_ERR_BUFFER_TOO_SMALL; + } + + // Serialize 1-bit NvBool primitive. + if (finn_write_buffer(bp, api->bWrite, 1)) + { + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + return NV_ERR_BUFFER_TOO_SMALL; + } + + // Serialize field-presence indicator for `messageLength`. + if (finn_write_buffer(bp, 1, 1)) + { + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + return NV_ERR_BUFFER_TOO_SMALL; + } + + // Serialize 32-bit NvU32 primitive. + if (finn_write_buffer(bp, api->messageLength, 32)) + { + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + return NV_ERR_BUFFER_TOO_SMALL; + } + + // Serialize data-presence (nonnull pointer) indicator. + if (finn_write_buffer(bp, !!(api->pMessage), 1)) + { + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + return NV_ERR_BUFFER_TOO_SMALL; + } + + // Skip if pointer is null. + if (api->pMessage) + { + // Serialize each element in `pMessage`. + { + NvLength i; + for (i = 0; i < (api->messageLength); ++i) + { + // Serialize field-presence indicator for `pMessage[i]`. + if (finn_write_buffer(bp, 1, 1)) + { + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + return NV_ERR_BUFFER_TOO_SMALL; + } + + // Serialize 8-bit NvU8 primitive. + if (finn_write_buffer(bp, ((NvU8 *)(NvP64_VALUE(api->pMessage)))[i], 8)) + { + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + return NV_ERR_BUFFER_TOO_SMALL; + } + + } + } + + // Free memory that was allocated during downward deserialization. + if (seri_up && api->pMessage) + FINN_FREE(NvP64_VALUE(api->pMessage)); + } + + + // Done + return NV_OK; +} + + +// Deserialize each of the 3 field(s). +static NV_STATUS finnDeserializeRecord_NV402C_CTRL_I2C_TRANSACTION_DATA_I2C_BLOCK_RW(finn_bit_pump_for_read *bp, NV402C_CTRL_I2C_TRANSACTION_DATA_I2C_BLOCK_RW *api, NvLength api_size, NvBool deser_up) +{ + // Check that the destination struct fits within the destination buffer. + if (sizeof(NV402C_CTRL_I2C_TRANSACTION_DATA_I2C_BLOCK_RW) > api_size) + { + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + return NV_ERR_BUFFER_TOO_SMALL; + } + + // Check field-presence indicator for `bWrite`. + if (!finn_read_buffer(bp, 1)) + { + FINN_ERROR(NV_ERR_LIB_RM_VERSION_MISMATCH); + return NV_ERR_LIB_RM_VERSION_MISMATCH; + } + + // Deserialize 1-bit NvBool primitive. + api->bWrite = (NvBool) finn_read_buffer(bp, 1); + + // Check field-presence indicator for `messageLength`. + if (!finn_read_buffer(bp, 1)) + { + FINN_ERROR(NV_ERR_LIB_RM_VERSION_MISMATCH); + return NV_ERR_LIB_RM_VERSION_MISMATCH; + } + + // Deserialize 32-bit NvU32 primitive. + api->messageLength = (NvU32) finn_read_buffer(bp, 32); + + // Check data-presence (nonnull pointer) indicator for `pMessage`. + if (finn_read_buffer(bp, 1)) + { + // Allocate memory and set pointer when deserializing down. + // (Calling code is expected to do so when deserializing up.) + if (!deser_up) + { + // The data-presence indicator would have been false + // if there were no data to deserialize. + if ((api->messageLength) * (sizeof(NvU8) /*pMessage[i]*/) /*pMessage*/ < 1) + { + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + return NV_ERR_BUFFER_TOO_SMALL; + } + + api->pMessage = NV_PTR_TO_NvP64(FINN_MALLOC((api->messageLength) * (sizeof(NvU8) /*pMessage[i]*/) /*pMessage*/)); + if (!api->pMessage) + { + FINN_ERROR(NV_ERR_NO_MEMORY); + return NV_ERR_NO_MEMORY; + } + + FINN_MEMZERO(NvP64_VALUE(api->pMessage), (api->messageLength) * (sizeof(NvU8) /*pMessage[i]*/) /*pMessage*/); + } + + // Otherwise the pointer must be provided by caller. + else if (!api->pMessage) + { + FINN_ERROR(NV_ERR_INVALID_POINTER); + return NV_ERR_INVALID_POINTER; + } + + // Deserialize each element in `pMessage`. + { + NvLength i; + for (i = 0; i < (api->messageLength); ++i) + { + // Check field-presence indicator for `pMessage[i]`. + if (!finn_read_buffer(bp, 1)) + { + FINN_ERROR(NV_ERR_LIB_RM_VERSION_MISMATCH); + return NV_ERR_LIB_RM_VERSION_MISMATCH; + } + + // Deserialize 8-bit NvU8 primitive. + ((NvU8 *)(NvP64_VALUE(api->pMessage)))[i] = (NvU8) finn_read_buffer(bp, 8); + + } + } + + } + + // Nullify pointer only if FINN manages memory allocation. + else + { + if (!deser_up) + api->pMessage = NV_PTR_TO_NvP64(NULL); + } + + // Done + return NV_OK; +} + + +// Serialize each of the 5 field(s). +static NV_STATUS finnSerializeRecord_NV402C_CTRL_I2C_TRANSACTION_DATA_I2C_BUFFER_RW(const NV402C_CTRL_I2C_TRANSACTION_DATA_I2C_BUFFER_RW *api, finn_bit_pump_for_write *bp, NvBool seri_up) +{ + // Serialize field-presence indicator for `bWrite`. + if (finn_write_buffer(bp, 1, 1)) + { + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + return NV_ERR_BUFFER_TOO_SMALL; + } + + // Serialize 1-bit NvBool primitive. + if (finn_write_buffer(bp, api->bWrite, 1)) + { + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + return NV_ERR_BUFFER_TOO_SMALL; + } + + // Serialize field-presence indicator for `warFlags`. + if (finn_write_buffer(bp, 1, 1)) + { + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + return NV_ERR_BUFFER_TOO_SMALL; + } + + // Serialize 32-bit NvU32 primitive. + if (finn_write_buffer(bp, api->warFlags, 32)) + { + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + return NV_ERR_BUFFER_TOO_SMALL; + } + + // Serialize field-presence indicator for `registerAddress`. + if (finn_write_buffer(bp, 1, 1)) + { + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + return NV_ERR_BUFFER_TOO_SMALL; + } + + // Serialize 8-bit NvU8 primitive. + if (finn_write_buffer(bp, api->registerAddress, 8)) + { + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + return NV_ERR_BUFFER_TOO_SMALL; + } + + // Serialize field-presence indicator for `messageLength`. + if (finn_write_buffer(bp, 1, 1)) + { + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + return NV_ERR_BUFFER_TOO_SMALL; + } + + // Serialize 32-bit NvU32 primitive. + if (finn_write_buffer(bp, api->messageLength, 32)) + { + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + return NV_ERR_BUFFER_TOO_SMALL; + } + + // Serialize data-presence (nonnull pointer) indicator. + if (finn_write_buffer(bp, !!(api->pMessage), 1)) + { + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + return NV_ERR_BUFFER_TOO_SMALL; + } + + // Skip if pointer is null. + if (api->pMessage) + { + // Serialize each element in `pMessage`. + { + NvLength i; + for (i = 0; i < (api->messageLength); ++i) + { + // Serialize field-presence indicator for `pMessage[i]`. + if (finn_write_buffer(bp, 1, 1)) + { + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + return NV_ERR_BUFFER_TOO_SMALL; + } + + // Serialize 8-bit NvU8 primitive. + if (finn_write_buffer(bp, ((NvU8 *)(NvP64_VALUE(api->pMessage)))[i], 8)) + { + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + return NV_ERR_BUFFER_TOO_SMALL; + } + + } + } + + // Free memory that was allocated during downward deserialization. + if (seri_up && api->pMessage) + FINN_FREE(NvP64_VALUE(api->pMessage)); + } + + + // Done + return NV_OK; +} + + +// Deserialize each of the 5 field(s). +static NV_STATUS finnDeserializeRecord_NV402C_CTRL_I2C_TRANSACTION_DATA_I2C_BUFFER_RW(finn_bit_pump_for_read *bp, NV402C_CTRL_I2C_TRANSACTION_DATA_I2C_BUFFER_RW *api, NvLength api_size, NvBool deser_up) +{ + // Check that the destination struct fits within the destination buffer. + if (sizeof(NV402C_CTRL_I2C_TRANSACTION_DATA_I2C_BUFFER_RW) > api_size) + { + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + return NV_ERR_BUFFER_TOO_SMALL; + } + + // Check field-presence indicator for `bWrite`. + if (!finn_read_buffer(bp, 1)) + { + FINN_ERROR(NV_ERR_LIB_RM_VERSION_MISMATCH); + return NV_ERR_LIB_RM_VERSION_MISMATCH; + } + + // Deserialize 1-bit NvBool primitive. + api->bWrite = (NvBool) finn_read_buffer(bp, 1); + + // Check field-presence indicator for `warFlags`. + if (!finn_read_buffer(bp, 1)) + { + FINN_ERROR(NV_ERR_LIB_RM_VERSION_MISMATCH); + return NV_ERR_LIB_RM_VERSION_MISMATCH; + } + + // Deserialize 32-bit NvU32 primitive. + api->warFlags = (NvU32) finn_read_buffer(bp, 32); + + // Check field-presence indicator for `registerAddress`. + if (!finn_read_buffer(bp, 1)) + { + FINN_ERROR(NV_ERR_LIB_RM_VERSION_MISMATCH); + return NV_ERR_LIB_RM_VERSION_MISMATCH; + } + + // Deserialize 8-bit NvU8 primitive. + api->registerAddress = (NvU8) finn_read_buffer(bp, 8); + + // Check field-presence indicator for `messageLength`. + if (!finn_read_buffer(bp, 1)) + { + FINN_ERROR(NV_ERR_LIB_RM_VERSION_MISMATCH); + return NV_ERR_LIB_RM_VERSION_MISMATCH; + } + + // Deserialize 32-bit NvU32 primitive. + api->messageLength = (NvU32) finn_read_buffer(bp, 32); + + // Check data-presence (nonnull pointer) indicator for `pMessage`. + if (finn_read_buffer(bp, 1)) + { + // Allocate memory and set pointer when deserializing down. + // (Calling code is expected to do so when deserializing up.) + if (!deser_up) + { + // The data-presence indicator would have been false + // if there were no data to deserialize. + if ((api->messageLength) * (sizeof(NvU8) /*pMessage[i]*/) /*pMessage*/ < 1) + { + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + return NV_ERR_BUFFER_TOO_SMALL; + } + + api->pMessage = NV_PTR_TO_NvP64(FINN_MALLOC((api->messageLength) * (sizeof(NvU8) /*pMessage[i]*/) /*pMessage*/)); + if (!api->pMessage) + { + FINN_ERROR(NV_ERR_NO_MEMORY); + return NV_ERR_NO_MEMORY; + } + + FINN_MEMZERO(NvP64_VALUE(api->pMessage), (api->messageLength) * (sizeof(NvU8) /*pMessage[i]*/) /*pMessage*/); + } + + // Otherwise the pointer must be provided by caller. + else if (!api->pMessage) + { + FINN_ERROR(NV_ERR_INVALID_POINTER); + return NV_ERR_INVALID_POINTER; + } + + // Deserialize each element in `pMessage`. + { + NvLength i; + for (i = 0; i < (api->messageLength); ++i) + { + // Check field-presence indicator for `pMessage[i]`. + if (!finn_read_buffer(bp, 1)) + { + FINN_ERROR(NV_ERR_LIB_RM_VERSION_MISMATCH); + return NV_ERR_LIB_RM_VERSION_MISMATCH; + } + + // Deserialize 8-bit NvU8 primitive. + ((NvU8 *)(NvP64_VALUE(api->pMessage)))[i] = (NvU8) finn_read_buffer(bp, 8); + + } + } + + } + + // Nullify pointer only if FINN manages memory allocation. + else + { + if (!deser_up) + api->pMessage = NV_PTR_TO_NvP64(NULL); + } + + // Done + return NV_OK; +} + + +// Serialize each of the 2 field(s). +static NV_STATUS finnSerializeRecord_NV402C_CTRL_I2C_TRANSACTION_DATA_I2C_BYTE_RW(const NV402C_CTRL_I2C_TRANSACTION_DATA_I2C_BYTE_RW *api, finn_bit_pump_for_write *bp, NvBool seri_up) +{ + // Serialize field-presence indicator for `bWrite`. + if (finn_write_buffer(bp, 1, 1)) + { + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + return NV_ERR_BUFFER_TOO_SMALL; + } + + // Serialize 1-bit NvBool primitive. + if (finn_write_buffer(bp, api->bWrite, 1)) + { + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + return NV_ERR_BUFFER_TOO_SMALL; + } + + // Serialize field-presence indicator for `message`. + if (finn_write_buffer(bp, 1, 1)) + { + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + return NV_ERR_BUFFER_TOO_SMALL; + } + + // Serialize 8-bit NvU8 primitive. + if (finn_write_buffer(bp, api->message, 8)) + { + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + return NV_ERR_BUFFER_TOO_SMALL; + } + + + // Done + return NV_OK; +} + + +// Deserialize each of the 2 field(s). +static NV_STATUS finnDeserializeRecord_NV402C_CTRL_I2C_TRANSACTION_DATA_I2C_BYTE_RW(finn_bit_pump_for_read *bp, NV402C_CTRL_I2C_TRANSACTION_DATA_I2C_BYTE_RW *api, NvLength api_size, NvBool deser_up) +{ + // Check that the destination struct fits within the destination buffer. + if (sizeof(NV402C_CTRL_I2C_TRANSACTION_DATA_I2C_BYTE_RW) > api_size) + { + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + return NV_ERR_BUFFER_TOO_SMALL; + } + + // Check field-presence indicator for `bWrite`. + if (!finn_read_buffer(bp, 1)) + { + FINN_ERROR(NV_ERR_LIB_RM_VERSION_MISMATCH); + return NV_ERR_LIB_RM_VERSION_MISMATCH; + } + + // Deserialize 1-bit NvBool primitive. + api->bWrite = (NvBool) finn_read_buffer(bp, 1); + + // Check field-presence indicator for `message`. + if (!finn_read_buffer(bp, 1)) + { + FINN_ERROR(NV_ERR_LIB_RM_VERSION_MISMATCH); + return NV_ERR_LIB_RM_VERSION_MISMATCH; + } + + // Deserialize 8-bit NvU8 primitive. + api->message = (NvU8) finn_read_buffer(bp, 8); + + // Done + return NV_OK; +} + + +// Serialize each of the 4 field(s). +static NV_STATUS finnSerializeRecord_NV402C_CTRL_I2C_TRANSACTION_DATA_READ_EDID_DDC(const NV402C_CTRL_I2C_TRANSACTION_DATA_READ_EDID_DDC *api, finn_bit_pump_for_write *bp, NvBool seri_up) +{ + // Serialize field-presence indicator for `segmentNumber`. + if (finn_write_buffer(bp, 1, 1)) + { + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + return NV_ERR_BUFFER_TOO_SMALL; + } + + // Serialize 8-bit NvU8 primitive. + if (finn_write_buffer(bp, api->segmentNumber, 8)) + { + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + return NV_ERR_BUFFER_TOO_SMALL; + } + + // Serialize field-presence indicator for `registerAddress`. + if (finn_write_buffer(bp, 1, 1)) + { + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + return NV_ERR_BUFFER_TOO_SMALL; + } + + // Serialize 8-bit NvU8 primitive. + if (finn_write_buffer(bp, api->registerAddress, 8)) + { + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + return NV_ERR_BUFFER_TOO_SMALL; + } + + // Serialize field-presence indicator for `messageLength`. + if (finn_write_buffer(bp, 1, 1)) + { + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + return NV_ERR_BUFFER_TOO_SMALL; + } + + // Serialize 32-bit NvU32 primitive. + if (finn_write_buffer(bp, api->messageLength, 32)) + { + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + return NV_ERR_BUFFER_TOO_SMALL; + } + + // Serialize data-presence (nonnull pointer) indicator. + if (finn_write_buffer(bp, !!(api->pMessage), 1)) + { + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + return NV_ERR_BUFFER_TOO_SMALL; + } + + // Skip if pointer is null. + if (api->pMessage) + { + // Serialize each element in `pMessage`. + { + NvLength i; + for (i = 0; i < (api->messageLength); ++i) + { + // Serialize field-presence indicator for `pMessage[i]`. + if (finn_write_buffer(bp, 1, 1)) + { + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + return NV_ERR_BUFFER_TOO_SMALL; + } + + // Serialize 8-bit NvU8 primitive. + if (finn_write_buffer(bp, ((NvU8 *)(NvP64_VALUE(api->pMessage)))[i], 8)) + { + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + return NV_ERR_BUFFER_TOO_SMALL; + } + + } + } + + // Free memory that was allocated during downward deserialization. + if (seri_up && api->pMessage) + FINN_FREE(NvP64_VALUE(api->pMessage)); + } + + + // Done + return NV_OK; +} + + +// Deserialize each of the 4 field(s). +static NV_STATUS finnDeserializeRecord_NV402C_CTRL_I2C_TRANSACTION_DATA_READ_EDID_DDC(finn_bit_pump_for_read *bp, NV402C_CTRL_I2C_TRANSACTION_DATA_READ_EDID_DDC *api, NvLength api_size, NvBool deser_up) +{ + // Check that the destination struct fits within the destination buffer. + if (sizeof(NV402C_CTRL_I2C_TRANSACTION_DATA_READ_EDID_DDC) > api_size) + { + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + return NV_ERR_BUFFER_TOO_SMALL; + } + + // Check field-presence indicator for `segmentNumber`. + if (!finn_read_buffer(bp, 1)) + { + FINN_ERROR(NV_ERR_LIB_RM_VERSION_MISMATCH); + return NV_ERR_LIB_RM_VERSION_MISMATCH; + } + + // Deserialize 8-bit NvU8 primitive. + api->segmentNumber = (NvU8) finn_read_buffer(bp, 8); + + // Check field-presence indicator for `registerAddress`. + if (!finn_read_buffer(bp, 1)) + { + FINN_ERROR(NV_ERR_LIB_RM_VERSION_MISMATCH); + return NV_ERR_LIB_RM_VERSION_MISMATCH; + } + + // Deserialize 8-bit NvU8 primitive. + api->registerAddress = (NvU8) finn_read_buffer(bp, 8); + + // Check field-presence indicator for `messageLength`. + if (!finn_read_buffer(bp, 1)) + { + FINN_ERROR(NV_ERR_LIB_RM_VERSION_MISMATCH); + return NV_ERR_LIB_RM_VERSION_MISMATCH; + } + + // Deserialize 32-bit NvU32 primitive. + api->messageLength = (NvU32) finn_read_buffer(bp, 32); + + // Check data-presence (nonnull pointer) indicator for `pMessage`. + if (finn_read_buffer(bp, 1)) + { + // Allocate memory and set pointer when deserializing down. + // (Calling code is expected to do so when deserializing up.) + if (!deser_up) + { + // The data-presence indicator would have been false + // if there were no data to deserialize. + if ((api->messageLength) * (sizeof(NvU8) /*pMessage[i]*/) /*pMessage*/ < 1) + { + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + return NV_ERR_BUFFER_TOO_SMALL; + } + + api->pMessage = NV_PTR_TO_NvP64(FINN_MALLOC((api->messageLength) * (sizeof(NvU8) /*pMessage[i]*/) /*pMessage*/)); + if (!api->pMessage) + { + FINN_ERROR(NV_ERR_NO_MEMORY); + return NV_ERR_NO_MEMORY; + } + + FINN_MEMZERO(NvP64_VALUE(api->pMessage), (api->messageLength) * (sizeof(NvU8) /*pMessage[i]*/) /*pMessage*/); + } + + // Otherwise the pointer must be provided by caller. + else if (!api->pMessage) + { + FINN_ERROR(NV_ERR_INVALID_POINTER); + return NV_ERR_INVALID_POINTER; + } + + // Deserialize each element in `pMessage`. + { + NvLength i; + for (i = 0; i < (api->messageLength); ++i) + { + // Check field-presence indicator for `pMessage[i]`. + if (!finn_read_buffer(bp, 1)) + { + FINN_ERROR(NV_ERR_LIB_RM_VERSION_MISMATCH); + return NV_ERR_LIB_RM_VERSION_MISMATCH; + } + + // Deserialize 8-bit NvU8 primitive. + ((NvU8 *)(NvP64_VALUE(api->pMessage)))[i] = (NvU8) finn_read_buffer(bp, 8); + + } + } + + } + + // Nullify pointer only if FINN manages memory allocation. + else + { + if (!deser_up) + api->pMessage = NV_PTR_TO_NvP64(NULL); + } + + // Done + return NV_OK; +} + + +// Serialize each of the 5 field(s). +// 1 out of 3 independent field(s) are reordered to be before 2 dependent field(s). +static NV_STATUS finnSerializeRecord_NV402C_CTRL_I2C_TRANSACTION_DATA_SMBUS_BLOCK_PROCESS_CALL(const NV402C_CTRL_I2C_TRANSACTION_DATA_SMBUS_BLOCK_PROCESS_CALL *api, finn_bit_pump_for_write *bp, NvBool seri_up) +{ + // Serialize field-presence indicator for `registerAddress`. + if (finn_write_buffer(bp, 1, 1)) + { + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + return NV_ERR_BUFFER_TOO_SMALL; + } + + // Serialize 8-bit NvU8 primitive. + if (finn_write_buffer(bp, api->registerAddress, 8)) + { + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + return NV_ERR_BUFFER_TOO_SMALL; + } + + // Serialize field-presence indicator for `writeMessageLength`. + if (finn_write_buffer(bp, 1, 1)) + { + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + return NV_ERR_BUFFER_TOO_SMALL; + } + + // Reject source data if it is out of range. + if (api->writeMessageLength > NV402C_CTRL_I2C_BLOCK_PROCESS_PROTOCOL_MAX) + { + FINN_ERROR(NV_ERR_OUT_OF_RANGE); + return NV_ERR_OUT_OF_RANGE; + } + + // Serialize 32-bit NvU32 primitive. + if (finn_write_buffer(bp, api->writeMessageLength, 32)) + { + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + return NV_ERR_BUFFER_TOO_SMALL; + } + + // Serialize field-presence indicator for `readMessageLength`. + if (finn_write_buffer(bp, 1, 1)) + { + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + return NV_ERR_BUFFER_TOO_SMALL; + } + + // Reject source data if it is out of range. + if (api->readMessageLength > NV402C_CTRL_I2C_BLOCK_PROCESS_PROTOCOL_MAX) + { + FINN_ERROR(NV_ERR_OUT_OF_RANGE); + return NV_ERR_OUT_OF_RANGE; + } + + // Serialize 32-bit NvU32 primitive. + if (finn_write_buffer(bp, api->readMessageLength, 32)) + { + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + return NV_ERR_BUFFER_TOO_SMALL; + } + + // Serialize each element in `writeMessage`. + { + NvLength i; + for (i = 0; i < NV402C_CTRL_I2C_BLOCK_PROCESS_PROTOCOL_MAX; ++i) + { + // Serialize field-presence indicator for `writeMessage[i]`. + if (finn_write_buffer(bp, 1, 1)) + { + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + return NV_ERR_BUFFER_TOO_SMALL; + } + + // Serialize 8-bit NvU8 primitive. + if (finn_write_buffer(bp, (api->writeMessage)[i], 8)) + { + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + return NV_ERR_BUFFER_TOO_SMALL; + } + + } + } + + // Serialize each element in `readMessage`. + { + NvLength i; + for (i = 0; i < NV402C_CTRL_I2C_BLOCK_PROCESS_PROTOCOL_MAX; ++i) + { + // Serialize field-presence indicator for `readMessage[i]`. + if (finn_write_buffer(bp, 1, 1)) + { + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + return NV_ERR_BUFFER_TOO_SMALL; + } + + // Serialize 8-bit NvU8 primitive. + if (finn_write_buffer(bp, (api->readMessage)[i], 8)) + { + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + return NV_ERR_BUFFER_TOO_SMALL; + } + + } + } + + + // Done + return NV_OK; +} + + +// Deserialize each of the 5 field(s). +// 1 out of 3 independent field(s) are reordered to be before 2 dependent field(s). +static NV_STATUS finnDeserializeRecord_NV402C_CTRL_I2C_TRANSACTION_DATA_SMBUS_BLOCK_PROCESS_CALL(finn_bit_pump_for_read *bp, NV402C_CTRL_I2C_TRANSACTION_DATA_SMBUS_BLOCK_PROCESS_CALL *api, NvLength api_size, NvBool deser_up) +{ + // Check that the destination struct fits within the destination buffer. + if (sizeof(NV402C_CTRL_I2C_TRANSACTION_DATA_SMBUS_BLOCK_PROCESS_CALL) > api_size) + { + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + return NV_ERR_BUFFER_TOO_SMALL; + } + + // Check field-presence indicator for `registerAddress`. + if (!finn_read_buffer(bp, 1)) + { + FINN_ERROR(NV_ERR_LIB_RM_VERSION_MISMATCH); + return NV_ERR_LIB_RM_VERSION_MISMATCH; + } + + // Deserialize 8-bit NvU8 primitive. + api->registerAddress = (NvU8) finn_read_buffer(bp, 8); + + // Check field-presence indicator for `writeMessageLength`. + if (!finn_read_buffer(bp, 1)) + { + FINN_ERROR(NV_ERR_LIB_RM_VERSION_MISMATCH); + return NV_ERR_LIB_RM_VERSION_MISMATCH; + } + + // Deserialize 32-bit NvU32 primitive. + api->writeMessageLength = (NvU32) finn_read_buffer(bp, 32); + + // Reject deserialized data if it is out of range. + if (api->writeMessageLength > NV402C_CTRL_I2C_BLOCK_PROCESS_PROTOCOL_MAX) + { + FINN_ERROR(NV_ERR_OUT_OF_RANGE); + return NV_ERR_OUT_OF_RANGE; + } + + // Check field-presence indicator for `readMessageLength`. + if (!finn_read_buffer(bp, 1)) + { + FINN_ERROR(NV_ERR_LIB_RM_VERSION_MISMATCH); + return NV_ERR_LIB_RM_VERSION_MISMATCH; + } + + // Deserialize 32-bit NvU32 primitive. + api->readMessageLength = (NvU32) finn_read_buffer(bp, 32); + + // Reject deserialized data if it is out of range. + if (api->readMessageLength > NV402C_CTRL_I2C_BLOCK_PROCESS_PROTOCOL_MAX) + { + FINN_ERROR(NV_ERR_OUT_OF_RANGE); + return NV_ERR_OUT_OF_RANGE; + } + + // Deserialize each element in `writeMessage`. + { + NvLength i; + for (i = 0; i < NV402C_CTRL_I2C_BLOCK_PROCESS_PROTOCOL_MAX; ++i) + { + // Check field-presence indicator for `writeMessage[i]`. + if (!finn_read_buffer(bp, 1)) + { + FINN_ERROR(NV_ERR_LIB_RM_VERSION_MISMATCH); + return NV_ERR_LIB_RM_VERSION_MISMATCH; + } + + // Deserialize 8-bit NvU8 primitive. + (api->writeMessage)[i] = (NvU8) finn_read_buffer(bp, 8); + + } + } + + // Deserialize each element in `readMessage`. + { + NvLength i; + for (i = 0; i < NV402C_CTRL_I2C_BLOCK_PROCESS_PROTOCOL_MAX; ++i) + { + // Check field-presence indicator for `readMessage[i]`. + if (!finn_read_buffer(bp, 1)) + { + FINN_ERROR(NV_ERR_LIB_RM_VERSION_MISMATCH); + return NV_ERR_LIB_RM_VERSION_MISMATCH; + } + + // Deserialize 8-bit NvU8 primitive. + (api->readMessage)[i] = (NvU8) finn_read_buffer(bp, 8); + + } + } + + // Done + return NV_OK; +} + + +// Serialize each of the 4 field(s). +static NV_STATUS finnSerializeRecord_NV402C_CTRL_I2C_TRANSACTION_DATA_SMBUS_BLOCK_RW(const NV402C_CTRL_I2C_TRANSACTION_DATA_SMBUS_BLOCK_RW *api, finn_bit_pump_for_write *bp, NvBool seri_up) +{ + // Serialize field-presence indicator for `bWrite`. + if (finn_write_buffer(bp, 1, 1)) + { + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + return NV_ERR_BUFFER_TOO_SMALL; + } + + // Serialize 1-bit NvBool primitive. + if (finn_write_buffer(bp, api->bWrite, 1)) + { + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + return NV_ERR_BUFFER_TOO_SMALL; + } + + // Serialize field-presence indicator for `registerAddress`. + if (finn_write_buffer(bp, 1, 1)) + { + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + return NV_ERR_BUFFER_TOO_SMALL; + } + + // Serialize 8-bit NvU8 primitive. + if (finn_write_buffer(bp, api->registerAddress, 8)) + { + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + return NV_ERR_BUFFER_TOO_SMALL; + } + + // Serialize field-presence indicator for `messageLength`. + if (finn_write_buffer(bp, 1, 1)) + { + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + return NV_ERR_BUFFER_TOO_SMALL; + } + + // Serialize 32-bit NvU32 primitive. + if (finn_write_buffer(bp, api->messageLength, 32)) + { + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + return NV_ERR_BUFFER_TOO_SMALL; + } + + // Serialize data-presence (nonnull pointer) indicator. + if (finn_write_buffer(bp, !!(api->pMessage), 1)) + { + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + return NV_ERR_BUFFER_TOO_SMALL; + } + + // Skip if pointer is null. + if (api->pMessage) + { + // Serialize each element in `pMessage`. + { + NvLength i; + for (i = 0; i < (api->messageLength); ++i) + { + // Serialize field-presence indicator for `pMessage[i]`. + if (finn_write_buffer(bp, 1, 1)) + { + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + return NV_ERR_BUFFER_TOO_SMALL; + } + + // Serialize 8-bit NvU8 primitive. + if (finn_write_buffer(bp, ((NvU8 *)(NvP64_VALUE(api->pMessage)))[i], 8)) + { + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + return NV_ERR_BUFFER_TOO_SMALL; + } + + } + } + + // Free memory that was allocated during downward deserialization. + if (seri_up && api->pMessage) + FINN_FREE(NvP64_VALUE(api->pMessage)); + } + + + // Done + return NV_OK; +} + + +// Deserialize each of the 4 field(s). +static NV_STATUS finnDeserializeRecord_NV402C_CTRL_I2C_TRANSACTION_DATA_SMBUS_BLOCK_RW(finn_bit_pump_for_read *bp, NV402C_CTRL_I2C_TRANSACTION_DATA_SMBUS_BLOCK_RW *api, NvLength api_size, NvBool deser_up) +{ + // Check that the destination struct fits within the destination buffer. + if (sizeof(NV402C_CTRL_I2C_TRANSACTION_DATA_SMBUS_BLOCK_RW) > api_size) + { + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + return NV_ERR_BUFFER_TOO_SMALL; + } + + // Check field-presence indicator for `bWrite`. + if (!finn_read_buffer(bp, 1)) + { + FINN_ERROR(NV_ERR_LIB_RM_VERSION_MISMATCH); + return NV_ERR_LIB_RM_VERSION_MISMATCH; + } + + // Deserialize 1-bit NvBool primitive. + api->bWrite = (NvBool) finn_read_buffer(bp, 1); + + // Check field-presence indicator for `registerAddress`. + if (!finn_read_buffer(bp, 1)) + { + FINN_ERROR(NV_ERR_LIB_RM_VERSION_MISMATCH); + return NV_ERR_LIB_RM_VERSION_MISMATCH; + } + + // Deserialize 8-bit NvU8 primitive. + api->registerAddress = (NvU8) finn_read_buffer(bp, 8); + + // Check field-presence indicator for `messageLength`. + if (!finn_read_buffer(bp, 1)) + { + FINN_ERROR(NV_ERR_LIB_RM_VERSION_MISMATCH); + return NV_ERR_LIB_RM_VERSION_MISMATCH; + } + + // Deserialize 32-bit NvU32 primitive. + api->messageLength = (NvU32) finn_read_buffer(bp, 32); + + // Check data-presence (nonnull pointer) indicator for `pMessage`. + if (finn_read_buffer(bp, 1)) + { + // Allocate memory and set pointer when deserializing down. + // (Calling code is expected to do so when deserializing up.) + if (!deser_up) + { + // The data-presence indicator would have been false + // if there were no data to deserialize. + if ((api->messageLength) * (sizeof(NvU8) /*pMessage[i]*/) /*pMessage*/ < 1) + { + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + return NV_ERR_BUFFER_TOO_SMALL; + } + + api->pMessage = NV_PTR_TO_NvP64(FINN_MALLOC((api->messageLength) * (sizeof(NvU8) /*pMessage[i]*/) /*pMessage*/)); + if (!api->pMessage) + { + FINN_ERROR(NV_ERR_NO_MEMORY); + return NV_ERR_NO_MEMORY; + } + + FINN_MEMZERO(NvP64_VALUE(api->pMessage), (api->messageLength) * (sizeof(NvU8) /*pMessage[i]*/) /*pMessage*/); + } + + // Otherwise the pointer must be provided by caller. + else if (!api->pMessage) + { + FINN_ERROR(NV_ERR_INVALID_POINTER); + return NV_ERR_INVALID_POINTER; + } + + // Deserialize each element in `pMessage`. + { + NvLength i; + for (i = 0; i < (api->messageLength); ++i) + { + // Check field-presence indicator for `pMessage[i]`. + if (!finn_read_buffer(bp, 1)) + { + FINN_ERROR(NV_ERR_LIB_RM_VERSION_MISMATCH); + return NV_ERR_LIB_RM_VERSION_MISMATCH; + } + + // Deserialize 8-bit NvU8 primitive. + ((NvU8 *)(NvP64_VALUE(api->pMessage)))[i] = (NvU8) finn_read_buffer(bp, 8); + + } + } + + } + + // Nullify pointer only if FINN manages memory allocation. + else + { + if (!deser_up) + api->pMessage = NV_PTR_TO_NvP64(NULL); + } + + // Done + return NV_OK; +} + + +// Serialize each of the 3 field(s). +static NV_STATUS finnSerializeRecord_NV402C_CTRL_I2C_TRANSACTION_DATA_SMBUS_BYTE_RW(const NV402C_CTRL_I2C_TRANSACTION_DATA_SMBUS_BYTE_RW *api, finn_bit_pump_for_write *bp, NvBool seri_up) +{ + // Serialize field-presence indicator for `bWrite`. + if (finn_write_buffer(bp, 1, 1)) + { + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + return NV_ERR_BUFFER_TOO_SMALL; + } + + // Serialize 1-bit NvBool primitive. + if (finn_write_buffer(bp, api->bWrite, 1)) + { + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + return NV_ERR_BUFFER_TOO_SMALL; + } + + // Serialize field-presence indicator for `registerAddress`. + if (finn_write_buffer(bp, 1, 1)) + { + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + return NV_ERR_BUFFER_TOO_SMALL; + } + + // Serialize 8-bit NvU8 primitive. + if (finn_write_buffer(bp, api->registerAddress, 8)) + { + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + return NV_ERR_BUFFER_TOO_SMALL; + } + + // Serialize field-presence indicator for `message`. + if (finn_write_buffer(bp, 1, 1)) + { + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + return NV_ERR_BUFFER_TOO_SMALL; + } + + // Serialize 8-bit NvU8 primitive. + if (finn_write_buffer(bp, api->message, 8)) + { + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + return NV_ERR_BUFFER_TOO_SMALL; + } + + + // Done + return NV_OK; +} + + +// Deserialize each of the 3 field(s). +static NV_STATUS finnDeserializeRecord_NV402C_CTRL_I2C_TRANSACTION_DATA_SMBUS_BYTE_RW(finn_bit_pump_for_read *bp, NV402C_CTRL_I2C_TRANSACTION_DATA_SMBUS_BYTE_RW *api, NvLength api_size, NvBool deser_up) +{ + // Check that the destination struct fits within the destination buffer. + if (sizeof(NV402C_CTRL_I2C_TRANSACTION_DATA_SMBUS_BYTE_RW) > api_size) + { + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + return NV_ERR_BUFFER_TOO_SMALL; + } + + // Check field-presence indicator for `bWrite`. + if (!finn_read_buffer(bp, 1)) + { + FINN_ERROR(NV_ERR_LIB_RM_VERSION_MISMATCH); + return NV_ERR_LIB_RM_VERSION_MISMATCH; + } + + // Deserialize 1-bit NvBool primitive. + api->bWrite = (NvBool) finn_read_buffer(bp, 1); + + // Check field-presence indicator for `registerAddress`. + if (!finn_read_buffer(bp, 1)) + { + FINN_ERROR(NV_ERR_LIB_RM_VERSION_MISMATCH); + return NV_ERR_LIB_RM_VERSION_MISMATCH; + } + + // Deserialize 8-bit NvU8 primitive. + api->registerAddress = (NvU8) finn_read_buffer(bp, 8); + + // Check field-presence indicator for `message`. + if (!finn_read_buffer(bp, 1)) + { + FINN_ERROR(NV_ERR_LIB_RM_VERSION_MISMATCH); + return NV_ERR_LIB_RM_VERSION_MISMATCH; + } + + // Deserialize 8-bit NvU8 primitive. + api->message = (NvU8) finn_read_buffer(bp, 8); + + // Done + return NV_OK; +} + + +// Serialize each of the 6 field(s). +// 1 out of 4 independent field(s) are reordered to be before 2 dependent field(s). +static NV_STATUS finnSerializeRecord_NV402C_CTRL_I2C_TRANSACTION_DATA_SMBUS_MULTIBYTE_REGISTER_BLOCK_RW(const NV402C_CTRL_I2C_TRANSACTION_DATA_SMBUS_MULTIBYTE_REGISTER_BLOCK_RW *api, finn_bit_pump_for_write *bp, NvBool seri_up) +{ + // Serialize field-presence indicator for `bWrite`. + if (finn_write_buffer(bp, 1, 1)) + { + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + return NV_ERR_BUFFER_TOO_SMALL; + } + + // Serialize 1-bit NvBool primitive. + if (finn_write_buffer(bp, api->bWrite, 1)) + { + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + return NV_ERR_BUFFER_TOO_SMALL; + } + + // Serialize field-presence indicator for `warFlags`. + if (finn_write_buffer(bp, 1, 1)) + { + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + return NV_ERR_BUFFER_TOO_SMALL; + } + + // Serialize 32-bit NvU32 primitive. + if (finn_write_buffer(bp, api->warFlags, 32)) + { + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + return NV_ERR_BUFFER_TOO_SMALL; + } + + // Serialize field-presence indicator for `indexLength`. + if (finn_write_buffer(bp, 1, 1)) + { + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + return NV_ERR_BUFFER_TOO_SMALL; + } + + // Reject source data if it is out of range. + if (api->indexLength > NV402C_CTRL_I2C_INDEX_LENGTH_MAX) + { + FINN_ERROR(NV_ERR_OUT_OF_RANGE); + return NV_ERR_OUT_OF_RANGE; + } + + // Serialize 32-bit NvU32 primitive. + if (finn_write_buffer(bp, api->indexLength, 32)) + { + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + return NV_ERR_BUFFER_TOO_SMALL; + } + + // Serialize field-presence indicator for `messageLength`. + if (finn_write_buffer(bp, 1, 1)) + { + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + return NV_ERR_BUFFER_TOO_SMALL; + } + + // Serialize 32-bit NvU32 primitive. + if (finn_write_buffer(bp, api->messageLength, 32)) + { + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + return NV_ERR_BUFFER_TOO_SMALL; + } + + // Serialize each element in `index`. + { + NvLength i; + for (i = 0; i < NV402C_CTRL_I2C_INDEX_LENGTH_MAX; ++i) + { + // Serialize field-presence indicator for `index[i]`. + if (finn_write_buffer(bp, 1, 1)) + { + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + return NV_ERR_BUFFER_TOO_SMALL; + } + + // Serialize 8-bit NvU8 primitive. + if (finn_write_buffer(bp, (api->index)[i], 8)) + { + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + return NV_ERR_BUFFER_TOO_SMALL; + } + + } + } + + // Serialize data-presence (nonnull pointer) indicator. + if (finn_write_buffer(bp, !!(api->pMessage), 1)) + { + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + return NV_ERR_BUFFER_TOO_SMALL; + } + + // Skip if pointer is null. + if (api->pMessage) + { + // Serialize each element in `pMessage`. + { + NvLength i; + for (i = 0; i < (api->messageLength); ++i) + { + // Serialize field-presence indicator for `pMessage[i]`. + if (finn_write_buffer(bp, 1, 1)) + { + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + return NV_ERR_BUFFER_TOO_SMALL; + } + + // Serialize 8-bit NvU8 primitive. + if (finn_write_buffer(bp, ((NvU8 *)(NvP64_VALUE(api->pMessage)))[i], 8)) + { + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + return NV_ERR_BUFFER_TOO_SMALL; + } + + } + } + + // Free memory that was allocated during downward deserialization. + if (seri_up && api->pMessage) + FINN_FREE(NvP64_VALUE(api->pMessage)); + } + + + // Done + return NV_OK; +} + + +// Deserialize each of the 6 field(s). +// 1 out of 4 independent field(s) are reordered to be before 2 dependent field(s). +static NV_STATUS finnDeserializeRecord_NV402C_CTRL_I2C_TRANSACTION_DATA_SMBUS_MULTIBYTE_REGISTER_BLOCK_RW(finn_bit_pump_for_read *bp, NV402C_CTRL_I2C_TRANSACTION_DATA_SMBUS_MULTIBYTE_REGISTER_BLOCK_RW *api, NvLength api_size, NvBool deser_up) +{ + // Check that the destination struct fits within the destination buffer. + if (sizeof(NV402C_CTRL_I2C_TRANSACTION_DATA_SMBUS_MULTIBYTE_REGISTER_BLOCK_RW) > api_size) + { + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + return NV_ERR_BUFFER_TOO_SMALL; + } + + // Check field-presence indicator for `bWrite`. + if (!finn_read_buffer(bp, 1)) + { + FINN_ERROR(NV_ERR_LIB_RM_VERSION_MISMATCH); + return NV_ERR_LIB_RM_VERSION_MISMATCH; + } + + // Deserialize 1-bit NvBool primitive. + api->bWrite = (NvBool) finn_read_buffer(bp, 1); + + // Check field-presence indicator for `warFlags`. + if (!finn_read_buffer(bp, 1)) + { + FINN_ERROR(NV_ERR_LIB_RM_VERSION_MISMATCH); + return NV_ERR_LIB_RM_VERSION_MISMATCH; + } + + // Deserialize 32-bit NvU32 primitive. + api->warFlags = (NvU32) finn_read_buffer(bp, 32); + + // Check field-presence indicator for `indexLength`. + if (!finn_read_buffer(bp, 1)) + { + FINN_ERROR(NV_ERR_LIB_RM_VERSION_MISMATCH); + return NV_ERR_LIB_RM_VERSION_MISMATCH; + } + + // Deserialize 32-bit NvU32 primitive. + api->indexLength = (NvU32) finn_read_buffer(bp, 32); + + // Reject deserialized data if it is out of range. + if (api->indexLength > NV402C_CTRL_I2C_INDEX_LENGTH_MAX) + { + FINN_ERROR(NV_ERR_OUT_OF_RANGE); + return NV_ERR_OUT_OF_RANGE; + } + + // Check field-presence indicator for `messageLength`. + if (!finn_read_buffer(bp, 1)) + { + FINN_ERROR(NV_ERR_LIB_RM_VERSION_MISMATCH); + return NV_ERR_LIB_RM_VERSION_MISMATCH; + } + + // Deserialize 32-bit NvU32 primitive. + api->messageLength = (NvU32) finn_read_buffer(bp, 32); + + // Deserialize each element in `index`. + { + NvLength i; + for (i = 0; i < NV402C_CTRL_I2C_INDEX_LENGTH_MAX; ++i) + { + // Check field-presence indicator for `index[i]`. + if (!finn_read_buffer(bp, 1)) + { + FINN_ERROR(NV_ERR_LIB_RM_VERSION_MISMATCH); + return NV_ERR_LIB_RM_VERSION_MISMATCH; + } + + // Deserialize 8-bit NvU8 primitive. + (api->index)[i] = (NvU8) finn_read_buffer(bp, 8); + + } + } + + // Check data-presence (nonnull pointer) indicator for `pMessage`. + if (finn_read_buffer(bp, 1)) + { + // Allocate memory and set pointer when deserializing down. + // (Calling code is expected to do so when deserializing up.) + if (!deser_up) + { + // The data-presence indicator would have been false + // if there were no data to deserialize. + if ((api->messageLength) * (sizeof(NvU8) /*pMessage[i]*/) /*pMessage*/ < 1) + { + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + return NV_ERR_BUFFER_TOO_SMALL; + } + + api->pMessage = NV_PTR_TO_NvP64(FINN_MALLOC((api->messageLength) * (sizeof(NvU8) /*pMessage[i]*/) /*pMessage*/)); + if (!api->pMessage) + { + FINN_ERROR(NV_ERR_NO_MEMORY); + return NV_ERR_NO_MEMORY; + } + + FINN_MEMZERO(NvP64_VALUE(api->pMessage), (api->messageLength) * (sizeof(NvU8) /*pMessage[i]*/) /*pMessage*/); + } + + // Otherwise the pointer must be provided by caller. + else if (!api->pMessage) + { + FINN_ERROR(NV_ERR_INVALID_POINTER); + return NV_ERR_INVALID_POINTER; + } + + // Deserialize each element in `pMessage`. + { + NvLength i; + for (i = 0; i < (api->messageLength); ++i) + { + // Check field-presence indicator for `pMessage[i]`. + if (!finn_read_buffer(bp, 1)) + { + FINN_ERROR(NV_ERR_LIB_RM_VERSION_MISMATCH); + return NV_ERR_LIB_RM_VERSION_MISMATCH; + } + + // Deserialize 8-bit NvU8 primitive. + ((NvU8 *)(NvP64_VALUE(api->pMessage)))[i] = (NvU8) finn_read_buffer(bp, 8); + + } + } + + } + + // Nullify pointer only if FINN manages memory allocation. + else + { + if (!deser_up) + api->pMessage = NV_PTR_TO_NvP64(NULL); + } + + // Done + return NV_OK; +} + + +// Serialize each of the 3 field(s). +static NV_STATUS finnSerializeRecord_NV402C_CTRL_I2C_TRANSACTION_DATA_SMBUS_PROCESS_CALL(const NV402C_CTRL_I2C_TRANSACTION_DATA_SMBUS_PROCESS_CALL *api, finn_bit_pump_for_write *bp, NvBool seri_up) +{ + // Serialize field-presence indicator for `registerAddress`. + if (finn_write_buffer(bp, 1, 1)) + { + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + return NV_ERR_BUFFER_TOO_SMALL; + } + + // Serialize 8-bit NvU8 primitive. + if (finn_write_buffer(bp, api->registerAddress, 8)) + { + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + return NV_ERR_BUFFER_TOO_SMALL; + } + + // Serialize field-presence indicator for `writeMessage`. + if (finn_write_buffer(bp, 1, 1)) + { + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + return NV_ERR_BUFFER_TOO_SMALL; + } + + // Serialize 16-bit NvU16 primitive. + if (finn_write_buffer(bp, api->writeMessage, 16)) + { + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + return NV_ERR_BUFFER_TOO_SMALL; + } + + // Serialize field-presence indicator for `readMessage`. + if (finn_write_buffer(bp, 1, 1)) + { + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + return NV_ERR_BUFFER_TOO_SMALL; + } + + // Serialize 16-bit NvU16 primitive. + if (finn_write_buffer(bp, api->readMessage, 16)) + { + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + return NV_ERR_BUFFER_TOO_SMALL; + } + + + // Done + return NV_OK; +} + + +// Deserialize each of the 3 field(s). +static NV_STATUS finnDeserializeRecord_NV402C_CTRL_I2C_TRANSACTION_DATA_SMBUS_PROCESS_CALL(finn_bit_pump_for_read *bp, NV402C_CTRL_I2C_TRANSACTION_DATA_SMBUS_PROCESS_CALL *api, NvLength api_size, NvBool deser_up) +{ + // Check that the destination struct fits within the destination buffer. + if (sizeof(NV402C_CTRL_I2C_TRANSACTION_DATA_SMBUS_PROCESS_CALL) > api_size) + { + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + return NV_ERR_BUFFER_TOO_SMALL; + } + + // Check field-presence indicator for `registerAddress`. + if (!finn_read_buffer(bp, 1)) + { + FINN_ERROR(NV_ERR_LIB_RM_VERSION_MISMATCH); + return NV_ERR_LIB_RM_VERSION_MISMATCH; + } + + // Deserialize 8-bit NvU8 primitive. + api->registerAddress = (NvU8) finn_read_buffer(bp, 8); + + // Check field-presence indicator for `writeMessage`. + if (!finn_read_buffer(bp, 1)) + { + FINN_ERROR(NV_ERR_LIB_RM_VERSION_MISMATCH); + return NV_ERR_LIB_RM_VERSION_MISMATCH; + } + + // Deserialize 16-bit NvU16 primitive. + api->writeMessage = (NvU16) finn_read_buffer(bp, 16); + + // Check field-presence indicator for `readMessage`. + if (!finn_read_buffer(bp, 1)) + { + FINN_ERROR(NV_ERR_LIB_RM_VERSION_MISMATCH); + return NV_ERR_LIB_RM_VERSION_MISMATCH; + } + + // Deserialize 16-bit NvU16 primitive. + api->readMessage = (NvU16) finn_read_buffer(bp, 16); + + // Done + return NV_OK; +} + + +// Serialize each of the 2 field(s). +static NV_STATUS finnSerializeRecord_NV402C_CTRL_I2C_TRANSACTION_DATA_SMBUS_QUICK_RW(const NV402C_CTRL_I2C_TRANSACTION_DATA_SMBUS_QUICK_RW *api, finn_bit_pump_for_write *bp, NvBool seri_up) +{ + // Serialize field-presence indicator for `bWrite`. + if (finn_write_buffer(bp, 1, 1)) + { + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + return NV_ERR_BUFFER_TOO_SMALL; + } + + // Serialize 1-bit NvBool primitive. + if (finn_write_buffer(bp, api->bWrite, 1)) + { + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + return NV_ERR_BUFFER_TOO_SMALL; + } + + // Serialize field-presence indicator for `warFlags`. + if (finn_write_buffer(bp, 1, 1)) + { + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + return NV_ERR_BUFFER_TOO_SMALL; + } + + // Serialize 32-bit NvU32 primitive. + if (finn_write_buffer(bp, api->warFlags, 32)) + { + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + return NV_ERR_BUFFER_TOO_SMALL; + } + + + // Done + return NV_OK; +} + + +// Deserialize each of the 2 field(s). +static NV_STATUS finnDeserializeRecord_NV402C_CTRL_I2C_TRANSACTION_DATA_SMBUS_QUICK_RW(finn_bit_pump_for_read *bp, NV402C_CTRL_I2C_TRANSACTION_DATA_SMBUS_QUICK_RW *api, NvLength api_size, NvBool deser_up) +{ + // Check that the destination struct fits within the destination buffer. + if (sizeof(NV402C_CTRL_I2C_TRANSACTION_DATA_SMBUS_QUICK_RW) > api_size) + { + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + return NV_ERR_BUFFER_TOO_SMALL; + } + + // Check field-presence indicator for `bWrite`. + if (!finn_read_buffer(bp, 1)) + { + FINN_ERROR(NV_ERR_LIB_RM_VERSION_MISMATCH); + return NV_ERR_LIB_RM_VERSION_MISMATCH; + } + + // Deserialize 1-bit NvBool primitive. + api->bWrite = (NvBool) finn_read_buffer(bp, 1); + + // Check field-presence indicator for `warFlags`. + if (!finn_read_buffer(bp, 1)) + { + FINN_ERROR(NV_ERR_LIB_RM_VERSION_MISMATCH); + return NV_ERR_LIB_RM_VERSION_MISMATCH; + } + + // Deserialize 32-bit NvU32 primitive. + api->warFlags = (NvU32) finn_read_buffer(bp, 32); + + // Done + return NV_OK; +} + + +// Serialize each of the 3 field(s). +static NV_STATUS finnSerializeRecord_NV402C_CTRL_I2C_TRANSACTION_DATA_SMBUS_WORD_RW(const NV402C_CTRL_I2C_TRANSACTION_DATA_SMBUS_WORD_RW *api, finn_bit_pump_for_write *bp, NvBool seri_up) +{ + // Serialize field-presence indicator for `bWrite`. + if (finn_write_buffer(bp, 1, 1)) + { + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + return NV_ERR_BUFFER_TOO_SMALL; + } + + // Serialize 1-bit NvBool primitive. + if (finn_write_buffer(bp, api->bWrite, 1)) + { + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + return NV_ERR_BUFFER_TOO_SMALL; + } + + // Serialize field-presence indicator for `registerAddress`. + if (finn_write_buffer(bp, 1, 1)) + { + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + return NV_ERR_BUFFER_TOO_SMALL; + } + + // Serialize 8-bit NvU8 primitive. + if (finn_write_buffer(bp, api->registerAddress, 8)) + { + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + return NV_ERR_BUFFER_TOO_SMALL; + } + + // Serialize field-presence indicator for `message`. + if (finn_write_buffer(bp, 1, 1)) + { + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + return NV_ERR_BUFFER_TOO_SMALL; + } + + // Serialize 16-bit NvU16 primitive. + if (finn_write_buffer(bp, api->message, 16)) + { + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + return NV_ERR_BUFFER_TOO_SMALL; + } + + + // Done + return NV_OK; +} + + +// Deserialize each of the 3 field(s). +static NV_STATUS finnDeserializeRecord_NV402C_CTRL_I2C_TRANSACTION_DATA_SMBUS_WORD_RW(finn_bit_pump_for_read *bp, NV402C_CTRL_I2C_TRANSACTION_DATA_SMBUS_WORD_RW *api, NvLength api_size, NvBool deser_up) +{ + // Check that the destination struct fits within the destination buffer. + if (sizeof(NV402C_CTRL_I2C_TRANSACTION_DATA_SMBUS_WORD_RW) > api_size) + { + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + return NV_ERR_BUFFER_TOO_SMALL; + } + + // Check field-presence indicator for `bWrite`. + if (!finn_read_buffer(bp, 1)) + { + FINN_ERROR(NV_ERR_LIB_RM_VERSION_MISMATCH); + return NV_ERR_LIB_RM_VERSION_MISMATCH; + } + + // Deserialize 1-bit NvBool primitive. + api->bWrite = (NvBool) finn_read_buffer(bp, 1); + + // Check field-presence indicator for `registerAddress`. + if (!finn_read_buffer(bp, 1)) + { + FINN_ERROR(NV_ERR_LIB_RM_VERSION_MISMATCH); + return NV_ERR_LIB_RM_VERSION_MISMATCH; + } + + // Deserialize 8-bit NvU8 primitive. + api->registerAddress = (NvU8) finn_read_buffer(bp, 8); + + // Check field-presence indicator for `message`. + if (!finn_read_buffer(bp, 1)) + { + FINN_ERROR(NV_ERR_LIB_RM_VERSION_MISMATCH); + return NV_ERR_LIB_RM_VERSION_MISMATCH; + } + + // Deserialize 16-bit NvU16 primitive. + api->message = (NvU16) finn_read_buffer(bp, 16); + + // Done + return NV_OK; +} + +#endif // (defined(NVRM)) + +#if (defined(NVRM)) + +// Serialize selected field from 11 possible values. +static NV_STATUS finnSerializeUnion_NV402C_CTRL_I2C_TRANSACTION_DATA(const NV402C_CTRL_I2C_TRANSACTION_DATA *api, finn_bit_pump_for_write *bp, NvBool seri_up, NV402C_CTRL_I2C_TRANSACTION_TYPE transType) +{ + switch(transType) + { + case NV402C_CTRL_I2C_TRANSACTION_TYPE_SMBUS_QUICK_RW: + { + // Serialize field-presence indicator for `api->smbusQuickData`. + if (finn_write_buffer(bp, 1, 1)) + { + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + return NV_ERR_BUFFER_TOO_SMALL; + } + + // Record has 2 field(s) to be serialized. + { + NV_STATUS status = finnSerializeRecord_NV402C_CTRL_I2C_TRANSACTION_DATA_SMBUS_QUICK_RW(&api->smbusQuickData, bp, seri_up); + if (status != NV_OK) + return status; + } + + return NV_OK; // Success + } + + case NV402C_CTRL_I2C_TRANSACTION_TYPE_I2C_BYTE_RW: + { + // Serialize field-presence indicator for `api->i2cByteData`. + if (finn_write_buffer(bp, 1, 1)) + { + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + return NV_ERR_BUFFER_TOO_SMALL; + } + + // Record has 2 field(s) to be serialized. + { + NV_STATUS status = finnSerializeRecord_NV402C_CTRL_I2C_TRANSACTION_DATA_I2C_BYTE_RW(&api->i2cByteData, bp, seri_up); + if (status != NV_OK) + return status; + } + + return NV_OK; // Success + } + + case NV402C_CTRL_I2C_TRANSACTION_TYPE_I2C_BLOCK_RW: + { + // Serialize field-presence indicator for `api->i2cBlockData`. + if (finn_write_buffer(bp, 1, 1)) + { + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + return NV_ERR_BUFFER_TOO_SMALL; + } + + // Record has 3 field(s) to be serialized. + { + NV_STATUS status = finnSerializeRecord_NV402C_CTRL_I2C_TRANSACTION_DATA_I2C_BLOCK_RW(&api->i2cBlockData, bp, seri_up); + if (status != NV_OK) + return status; + } + + return NV_OK; // Success + } + + case NV402C_CTRL_I2C_TRANSACTION_TYPE_I2C_BUFFER_RW: + { + // Serialize field-presence indicator for `api->i2cBufferData`. + if (finn_write_buffer(bp, 1, 1)) + { + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + return NV_ERR_BUFFER_TOO_SMALL; + } + + // Record has 5 field(s) to be serialized. + { + NV_STATUS status = finnSerializeRecord_NV402C_CTRL_I2C_TRANSACTION_DATA_I2C_BUFFER_RW(&api->i2cBufferData, bp, seri_up); + if (status != NV_OK) + return status; + } + + return NV_OK; // Success + } + + case NV402C_CTRL_I2C_TRANSACTION_TYPE_SMBUS_BYTE_RW: + { + // Serialize field-presence indicator for `api->smbusByteData`. + if (finn_write_buffer(bp, 1, 1)) + { + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + return NV_ERR_BUFFER_TOO_SMALL; + } + + // Record has 3 field(s) to be serialized. + { + NV_STATUS status = finnSerializeRecord_NV402C_CTRL_I2C_TRANSACTION_DATA_SMBUS_BYTE_RW(&api->smbusByteData, bp, seri_up); + if (status != NV_OK) + return status; + } + + return NV_OK; // Success + } + + case NV402C_CTRL_I2C_TRANSACTION_TYPE_SMBUS_WORD_RW: + { + // Serialize field-presence indicator for `api->smbusWordData`. + if (finn_write_buffer(bp, 1, 1)) + { + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + return NV_ERR_BUFFER_TOO_SMALL; + } + + // Record has 3 field(s) to be serialized. + { + NV_STATUS status = finnSerializeRecord_NV402C_CTRL_I2C_TRANSACTION_DATA_SMBUS_WORD_RW(&api->smbusWordData, bp, seri_up); + if (status != NV_OK) + return status; + } + + return NV_OK; // Success + } + + case NV402C_CTRL_I2C_TRANSACTION_TYPE_SMBUS_BLOCK_RW: + { + // Serialize field-presence indicator for `api->smbusBlockData`. + if (finn_write_buffer(bp, 1, 1)) + { + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + return NV_ERR_BUFFER_TOO_SMALL; + } + + // Record has 4 field(s) to be serialized. + { + NV_STATUS status = finnSerializeRecord_NV402C_CTRL_I2C_TRANSACTION_DATA_SMBUS_BLOCK_RW(&api->smbusBlockData, bp, seri_up); + if (status != NV_OK) + return status; + } + + return NV_OK; // Success + } + + case NV402C_CTRL_I2C_TRANSACTION_TYPE_SMBUS_PROCESS_CALL: + { + // Serialize field-presence indicator for `api->smbusProcessData`. + if (finn_write_buffer(bp, 1, 1)) + { + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + return NV_ERR_BUFFER_TOO_SMALL; + } + + // Record has 3 field(s) to be serialized. + { + NV_STATUS status = finnSerializeRecord_NV402C_CTRL_I2C_TRANSACTION_DATA_SMBUS_PROCESS_CALL(&api->smbusProcessData, bp, seri_up); + if (status != NV_OK) + return status; + } + + return NV_OK; // Success + } + + case NV402C_CTRL_I2C_TRANSACTION_TYPE_SMBUS_BLOCK_PROCESS_CALL: + { + // Serialize field-presence indicator for `api->smbusBlockProcessData`. + if (finn_write_buffer(bp, 1, 1)) + { + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + return NV_ERR_BUFFER_TOO_SMALL; + } + + // Record has 5 field(s) to be serialized. + { + NV_STATUS status = finnSerializeRecord_NV402C_CTRL_I2C_TRANSACTION_DATA_SMBUS_BLOCK_PROCESS_CALL(&api->smbusBlockProcessData, bp, seri_up); + if (status != NV_OK) + return status; + } + + return NV_OK; // Success + } + + case NV402C_CTRL_I2C_TRANSACTION_TYPE_SMBUS_MULTIBYTE_REGISTER_BLOCK_RW: + { + // Serialize field-presence indicator for `api->smbusMultibyteRegisterData`. + if (finn_write_buffer(bp, 1, 1)) + { + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + return NV_ERR_BUFFER_TOO_SMALL; + } + + // Record has 6 field(s) to be serialized. + { + NV_STATUS status = finnSerializeRecord_NV402C_CTRL_I2C_TRANSACTION_DATA_SMBUS_MULTIBYTE_REGISTER_BLOCK_RW(&api->smbusMultibyteRegisterData, bp, seri_up); + if (status != NV_OK) + return status; + } + + return NV_OK; // Success + } + + case NV402C_CTRL_I2C_TRANSACTION_TYPE_READ_EDID_DDC: + { + // Serialize field-presence indicator for `api->edidData`. + if (finn_write_buffer(bp, 1, 1)) + { + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + return NV_ERR_BUFFER_TOO_SMALL; + } + + // Record has 4 field(s) to be serialized. + { + NV_STATUS status = finnSerializeRecord_NV402C_CTRL_I2C_TRANSACTION_DATA_READ_EDID_DDC(&api->edidData, bp, seri_up); + if (status != NV_OK) + return status; + } + + return NV_OK; // Success + } + + default: + { + FINN_ERROR(NV_ERR_INVALID_ARGUMENT); + return NV_ERR_INVALID_ARGUMENT; + } + } +} + + +// Deserialize selected field from 11 possible values. +static NV_STATUS finnDeserializeUnion_NV402C_CTRL_I2C_TRANSACTION_DATA(finn_bit_pump_for_read *bp, NV402C_CTRL_I2C_TRANSACTION_DATA *api, NvLength api_size, NvBool deser_up, NV402C_CTRL_I2C_TRANSACTION_TYPE transType) +{ + // Check that the destination struct fits within the destination buffer. + if (sizeof(NV402C_CTRL_I2C_TRANSACTION_DATA) > api_size) + { + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + return NV_ERR_BUFFER_TOO_SMALL; + } + + switch(transType) + { + case NV402C_CTRL_I2C_TRANSACTION_TYPE_SMBUS_QUICK_RW: + { + // Check field-presence indicator for `api->smbusQuickData`. + if (!finn_read_buffer(bp, 1)) + { + FINN_ERROR(NV_ERR_LIB_RM_VERSION_MISMATCH); + return NV_ERR_LIB_RM_VERSION_MISMATCH; + } + + // Record has 2 field(s) to be deserialized. + { + NV_STATUS status = finnDeserializeRecord_NV402C_CTRL_I2C_TRANSACTION_DATA_SMBUS_QUICK_RW(bp, &api->smbusQuickData, sizeof(NV402C_CTRL_I2C_TRANSACTION_DATA_SMBUS_QUICK_RW), deser_up); + if (status != NV_OK) + return status; + } + + return NV_OK; // Success + } + + case NV402C_CTRL_I2C_TRANSACTION_TYPE_I2C_BYTE_RW: + { + // Check field-presence indicator for `api->i2cByteData`. + if (!finn_read_buffer(bp, 1)) + { + FINN_ERROR(NV_ERR_LIB_RM_VERSION_MISMATCH); + return NV_ERR_LIB_RM_VERSION_MISMATCH; + } + + // Record has 2 field(s) to be deserialized. + { + NV_STATUS status = finnDeserializeRecord_NV402C_CTRL_I2C_TRANSACTION_DATA_I2C_BYTE_RW(bp, &api->i2cByteData, sizeof(NV402C_CTRL_I2C_TRANSACTION_DATA_I2C_BYTE_RW), deser_up); + if (status != NV_OK) + return status; + } + + return NV_OK; // Success + } + + case NV402C_CTRL_I2C_TRANSACTION_TYPE_I2C_BLOCK_RW: + { + // Check field-presence indicator for `api->i2cBlockData`. + if (!finn_read_buffer(bp, 1)) + { + FINN_ERROR(NV_ERR_LIB_RM_VERSION_MISMATCH); + return NV_ERR_LIB_RM_VERSION_MISMATCH; + } + + // Record has 3 field(s) to be deserialized. + { + NV_STATUS status = finnDeserializeRecord_NV402C_CTRL_I2C_TRANSACTION_DATA_I2C_BLOCK_RW(bp, &api->i2cBlockData, sizeof(NV402C_CTRL_I2C_TRANSACTION_DATA_I2C_BLOCK_RW), deser_up); + if (status != NV_OK) + return status; + } + + return NV_OK; // Success + } + + case NV402C_CTRL_I2C_TRANSACTION_TYPE_I2C_BUFFER_RW: + { + // Check field-presence indicator for `api->i2cBufferData`. + if (!finn_read_buffer(bp, 1)) + { + FINN_ERROR(NV_ERR_LIB_RM_VERSION_MISMATCH); + return NV_ERR_LIB_RM_VERSION_MISMATCH; + } + + // Record has 5 field(s) to be deserialized. + { + NV_STATUS status = finnDeserializeRecord_NV402C_CTRL_I2C_TRANSACTION_DATA_I2C_BUFFER_RW(bp, &api->i2cBufferData, sizeof(NV402C_CTRL_I2C_TRANSACTION_DATA_I2C_BUFFER_RW), deser_up); + if (status != NV_OK) + return status; + } + + return NV_OK; // Success + } + + case NV402C_CTRL_I2C_TRANSACTION_TYPE_SMBUS_BYTE_RW: + { + // Check field-presence indicator for `api->smbusByteData`. + if (!finn_read_buffer(bp, 1)) + { + FINN_ERROR(NV_ERR_LIB_RM_VERSION_MISMATCH); + return NV_ERR_LIB_RM_VERSION_MISMATCH; + } + + // Record has 3 field(s) to be deserialized. + { + NV_STATUS status = finnDeserializeRecord_NV402C_CTRL_I2C_TRANSACTION_DATA_SMBUS_BYTE_RW(bp, &api->smbusByteData, sizeof(NV402C_CTRL_I2C_TRANSACTION_DATA_SMBUS_BYTE_RW), deser_up); + if (status != NV_OK) + return status; + } + + return NV_OK; // Success + } + + case NV402C_CTRL_I2C_TRANSACTION_TYPE_SMBUS_WORD_RW: + { + // Check field-presence indicator for `api->smbusWordData`. + if (!finn_read_buffer(bp, 1)) + { + FINN_ERROR(NV_ERR_LIB_RM_VERSION_MISMATCH); + return NV_ERR_LIB_RM_VERSION_MISMATCH; + } + + // Record has 3 field(s) to be deserialized. + { + NV_STATUS status = finnDeserializeRecord_NV402C_CTRL_I2C_TRANSACTION_DATA_SMBUS_WORD_RW(bp, &api->smbusWordData, sizeof(NV402C_CTRL_I2C_TRANSACTION_DATA_SMBUS_WORD_RW), deser_up); + if (status != NV_OK) + return status; + } + + return NV_OK; // Success + } + + case NV402C_CTRL_I2C_TRANSACTION_TYPE_SMBUS_BLOCK_RW: + { + // Check field-presence indicator for `api->smbusBlockData`. + if (!finn_read_buffer(bp, 1)) + { + FINN_ERROR(NV_ERR_LIB_RM_VERSION_MISMATCH); + return NV_ERR_LIB_RM_VERSION_MISMATCH; + } + + // Record has 4 field(s) to be deserialized. + { + NV_STATUS status = finnDeserializeRecord_NV402C_CTRL_I2C_TRANSACTION_DATA_SMBUS_BLOCK_RW(bp, &api->smbusBlockData, sizeof(NV402C_CTRL_I2C_TRANSACTION_DATA_SMBUS_BLOCK_RW), deser_up); + if (status != NV_OK) + return status; + } + + return NV_OK; // Success + } + + case NV402C_CTRL_I2C_TRANSACTION_TYPE_SMBUS_PROCESS_CALL: + { + // Check field-presence indicator for `api->smbusProcessData`. + if (!finn_read_buffer(bp, 1)) + { + FINN_ERROR(NV_ERR_LIB_RM_VERSION_MISMATCH); + return NV_ERR_LIB_RM_VERSION_MISMATCH; + } + + // Record has 3 field(s) to be deserialized. + { + NV_STATUS status = finnDeserializeRecord_NV402C_CTRL_I2C_TRANSACTION_DATA_SMBUS_PROCESS_CALL(bp, &api->smbusProcessData, sizeof(NV402C_CTRL_I2C_TRANSACTION_DATA_SMBUS_PROCESS_CALL), deser_up); + if (status != NV_OK) + return status; + } + + return NV_OK; // Success + } + + case NV402C_CTRL_I2C_TRANSACTION_TYPE_SMBUS_BLOCK_PROCESS_CALL: + { + // Check field-presence indicator for `api->smbusBlockProcessData`. + if (!finn_read_buffer(bp, 1)) + { + FINN_ERROR(NV_ERR_LIB_RM_VERSION_MISMATCH); + return NV_ERR_LIB_RM_VERSION_MISMATCH; + } + + // Record has 5 field(s) to be deserialized. + { + NV_STATUS status = finnDeserializeRecord_NV402C_CTRL_I2C_TRANSACTION_DATA_SMBUS_BLOCK_PROCESS_CALL(bp, &api->smbusBlockProcessData, sizeof(NV402C_CTRL_I2C_TRANSACTION_DATA_SMBUS_BLOCK_PROCESS_CALL), deser_up); + if (status != NV_OK) + return status; + } + + return NV_OK; // Success + } + + case NV402C_CTRL_I2C_TRANSACTION_TYPE_SMBUS_MULTIBYTE_REGISTER_BLOCK_RW: + { + // Check field-presence indicator for `api->smbusMultibyteRegisterData`. + if (!finn_read_buffer(bp, 1)) + { + FINN_ERROR(NV_ERR_LIB_RM_VERSION_MISMATCH); + return NV_ERR_LIB_RM_VERSION_MISMATCH; + } + + // Record has 6 field(s) to be deserialized. + { + NV_STATUS status = finnDeserializeRecord_NV402C_CTRL_I2C_TRANSACTION_DATA_SMBUS_MULTIBYTE_REGISTER_BLOCK_RW(bp, &api->smbusMultibyteRegisterData, sizeof(NV402C_CTRL_I2C_TRANSACTION_DATA_SMBUS_MULTIBYTE_REGISTER_BLOCK_RW), deser_up); + if (status != NV_OK) + return status; + } + + return NV_OK; // Success + } + + case NV402C_CTRL_I2C_TRANSACTION_TYPE_READ_EDID_DDC: + { + // Check field-presence indicator for `api->edidData`. + if (!finn_read_buffer(bp, 1)) + { + FINN_ERROR(NV_ERR_LIB_RM_VERSION_MISMATCH); + return NV_ERR_LIB_RM_VERSION_MISMATCH; + } + + // Record has 4 field(s) to be deserialized. + { + NV_STATUS status = finnDeserializeRecord_NV402C_CTRL_I2C_TRANSACTION_DATA_READ_EDID_DDC(bp, &api->edidData, sizeof(NV402C_CTRL_I2C_TRANSACTION_DATA_READ_EDID_DDC), deser_up); + if (status != NV_OK) + return status; + } + + return NV_OK; // Success + } + + default: + { + FINN_ERROR(NV_ERR_INVALID_ARGUMENT); + return NV_ERR_INVALID_ARGUMENT; + } + } +} + + +#endif // (defined(NVRM)) diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/kernel/inc/dev_p2060.h nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/kernel/inc/dev_p2060.h --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/kernel/inc/dev_p2060.h 2023-10-25 20:20:48.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/kernel/inc/dev_p2060.h 2024-03-05 22:13:10.000000000 +0000 @@ -303,4 +303,12 @@ #define NV_P2060_MOSAIC_MODE_ENABLE_TRUE 0x01 /* RW--V */ #define NV_P2060_MOSAIC_MODE_RESERVED 7:4 /* RWIVF */ +#define NV_P2060_MULTIPLIER_DIVIDER 0x2F /* RW-1R */ +#define NV_P2060_MULTIPLIER_DIVIDER_VALUE_MINUS_ONE 2:0 /* RWIVF */ +#define NV_P2060_MULTIPLIER_DIVIDER_VALUE_MINUS_ONE_MAX 0x7 +#define NV_P2060_MULTIPLIER_DIVIDER_MODE 7:7 /* RWIVF */ +#define NV_P2060_MULTIPLIER_DIVIDER_MODE_MULTIPLY 0x0 /* RWIVF */ +#define NV_P2060_MULTIPLIER_DIVIDER_MODE_DIVIDE 0x1 /* RWIVF */ + #endif //DEV_P2060_H + diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/kernel/inc/objrpc.h nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/kernel/inc/objrpc.h --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/kernel/inc/objrpc.h 2023-10-25 20:20:48.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/kernel/inc/objrpc.h 2024-03-05 22:13:10.000000000 +0000 @@ -53,7 +53,9 @@ typedef struct RpcHistoryEntry { NvU32 function; - NvU32 data[3]; + NvU64 data[2]; + NvU64 ts_start; + NvU64 ts_end; } RpcHistoryEntry; struct OBJRPC{ @@ -74,16 +76,13 @@ NvU32 *message_buffer_priv_uvm; MEMORY_DESCRIPTOR *pMemDesc_mesg_uvm; - // Buffer for initial GSP message. - void *init_msg_buf; - RmPhysAddr init_msg_buf_pa; - /* Message Queue */ struct _message_queue_info *pMessageQueueInfo; - RmPhysAddr messageQueuePhysMem; RpcHistoryEntry rpcHistory[RPC_HISTORY_DEPTH]; NvU32 rpcHistoryCurrent; + RpcHistoryEntry rpcEventHistory[RPC_HISTORY_DEPTH]; + NvU32 rpcEventHistoryCurrent; NvU32 timeoutCount; NvBool bQuietPrints; @@ -110,7 +109,6 @@ OBJRPC *initRpcObject(OBJGPU *pGpu); void rpcSetIpVersion(OBJGPU *pGpu, OBJRPC *pRpc, NvU32 ipVersion); void rpcObjIfacesSetup(OBJRPC *pRpc); -void rpcRmApiSetup(OBJGPU *pGpu); NV_STATUS rpcWriteCommonHeader(OBJGPU *pGpu, OBJRPC *pRpc, NvU32 func, NvU32 paramLength); NV_STATUS rpcWriteCommonHeaderSim(OBJGPU *pGpu); NV_STATUS _allocRpcMemDesc(OBJGPU *pGpu, NvU64 size, NvBool bContig, NV_ADDRESS_SPACE addrSpace, MEMORY_DESCRIPTOR **ppMemDesc, void **ppMemBuffer, void **ppMemBufferPriv); diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/kernel/inc/vgpu/rpc.h nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/kernel/inc/vgpu/rpc.h --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/kernel/inc/vgpu/rpc.h 2023-10-25 20:20:48.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/kernel/inc/vgpu/rpc.h 2024-03-05 22:13:10.000000000 +0000 @@ -62,7 +62,6 @@ static inline void NV_RM_RPC_CONTROL(OBJGPU *pGpu, ...) { return; } static inline void NV_RM_RPC_MANAGE_HW_RESOURCE_ALLOC(OBJGPU *pGpu, ...) { return; } static inline void NV_RM_RPC_MANAGE_HW_RESOURCE_FREE(OBJGPU *pGpu, ...) { return; } -static inline void NV_RM_RPC_MANAGE_HW_RESOURCE_BIND(OBJGPU *pGpu, ...) { return; } static inline void NV_RM_RPC_SET_GUEST_SYSTEM_INFO(OBJGPU *pGpu, ...) { return; } static inline void NV_RM_RPC_PERF_GET_PSTATE_INFO(OBJGPU *pGpu, ...) { return; } static inline void NV_RM_RPC_PERF_GET_VIRTUAL_PSTATE_INFO(OBJGPU *pGpu, ...) { return; } @@ -84,6 +83,7 @@ static inline void NV_RM_RPC_VGPU_PF_REG_READ32(OBJGPU *pGpu, ...) { return; } static inline void NV_RM_RPC_PMA_SCRUBBER_SHARED_BUFFER_GUEST_PAGES_OPERATION(OBJGPU *pGpu, ...) { return; } +static inline void NV_RM_RPC_INVALIDATE_TLB(OBJGPU *pGpu, ...) { return; } // RPC free stubs static inline void NV_RM_RPC_SIM_FREE_INFRA(OBJGPU *pGpu, ...) { return; } @@ -92,7 +92,6 @@ // Simulation stubs static inline void NV_RM_RPC_SIM_LOAD_ESCAPE_FUNCTIONS(OBJOS *pOS, ...) { return; } -static inline void NV_RM_RPC_SIM_ADD_DISP_CONTEXT_DMA(OBJGPU *pGpu, ...) { return; } static inline void NV_RM_RPC_SIM_UPDATE_DISP_CONTEXT_DMA(OBJGPU *pGpu, ...) { return; } static inline void NV_RM_RPC_SIM_DELETE_DISP_CONTEXT_DMA(OBJGPU *pGpu, ...) { return; } static inline void NV_RM_RPC_SIM_UPDATE_DISP_CHANNEL_INFO(OBJGPU *pGpu, ...) { return; } @@ -110,10 +109,10 @@ \ if (!IsT234DorBetter(pGpu)) \ { \ - RmClient *pClient = NULL; \ + RmClient *pClient = serverutilGetClientUnderLock(hclient); \ \ /* Get process ID from the client database */ \ - if (NV_OK == serverutilGetClientUnderLock(hclient, &pClient)) \ + if (pClient != NULL) \ { \ CALL_CONTEXT *pCallContext = resservGetTlsCallContext(); \ NV_ASSERT_OR_RETURN(pCallContext != NULL, NV_ERR_INVALID_STATE); \ @@ -134,7 +133,7 @@ \ status = pRmApi->AllocWithHandle(pRmApi, hclient, NV01_NULL_OBJECT, \ NV01_NULL_OBJECT, NV01_ROOT, \ - &root_alloc_params); \ + &root_alloc_params, sizeof(root_alloc_params)); \ \ if (status == NV_OK) \ { \ @@ -147,7 +146,8 @@ device_alloc_params.vaSpaceSize = vasize; \ \ status = pRmApi->AllocWithHandle(pRmApi, hclient, hclient, hdevice, \ - hclass, &device_alloc_params); \ + hclass, &device_alloc_params, \ + sizeof(device_alloc_params)); \ } \ else \ NV_ASSERT(0); \ @@ -182,7 +182,8 @@ DRF_DEF(OS02,_FLAGS,_PHYSICALITY,_NONCONTIGUOUS) | \ (flags & DRF_SHIFTMASK(NVOS02_FLAGS_COHERENCY))); \ status = pRmApi->AllocWithHandle(pRmApi, hclient, hdevice, \ - hmemory, NV01_MEMORY_LIST_SYSTEM, &listAllocParams); \ + hmemory, NV01_MEMORY_LIST_SYSTEM, &listAllocParams, \ + sizeof(listAllocParams)); \ } \ else \ { \ @@ -281,13 +282,14 @@ NV_ASSERT(IS_GSP_CLIENT(pGpu)); \ RM_API *pRmApi = GPU_GET_PHYSICAL_RMAPI(pGpu); \ status = pRmApi->AllocWithHandle(pRmApi, hclient, hparent, hchannel, \ - hclass, pGpfifoAllocParams); \ + hclass, pGpfifoAllocParams, \ + sizeof(*pGpfifoAllocParams)); \ } else if (pRpc == NULL) \ status = NV_ERR_INSUFFICIENT_RESOURCES; \ } \ while (0) -#define NV_RM_RPC_ALLOC_OBJECT(pGpu, hclient, hchannel, hobject, hclass, params, status)\ +#define NV_RM_RPC_ALLOC_OBJECT(pGpu, hclient, hchannel, hobject, hclass, params, paramsSize, status) \ do \ { \ OBJRPC *pRpc = GPU_GET_RPC(pGpu); \ @@ -297,7 +299,7 @@ NV_ASSERT(IS_GSP_CLIENT(pGpu)); \ RM_API *pRmApi = GPU_GET_PHYSICAL_RMAPI(pGpu); \ status = pRmApi->AllocWithHandle(pRmApi, hclient, hchannel, hobject, \ - hclass, params); \ + hclass, params, paramsSize); \ } \ } while (0) @@ -350,7 +352,8 @@ allocParams.data = 0; \ status = pRmApi->AllocWithHandle(pRmApi, hclient, \ hobject, hevent, \ - hclass, &allocParams); \ + hclass, &allocParams, \ + sizeof(allocParams)); \ } else if (pRpc == NULL) \ status = NV_ERR_INSUFFICIENT_RESOURCES; \ } while(0) @@ -370,7 +373,8 @@ alloc_params.subDeviceId = subDeviceInst; \ \ status = pRmApi->AllocWithHandle(pRmApi, hclient, hdevice, hsubdevice, \ - hclass, &alloc_params); \ + hclass, &alloc_params, \ + sizeof(alloc_params)); \ } else if (pRpc == NULL) \ status = NV_ERR_INSUFFICIENT_RESOURCES; \ } while (0) @@ -440,19 +444,6 @@ status = NV_ERR_INSUFFICIENT_RESOURCES; \ } while(0) -#define NV_RM_RPC_MANAGE_HW_RESOURCE_BIND(pGpu, hclient, hdevice, hresource, \ - virtaddr, physaddr, status) \ - do \ - { \ - OBJRPC *pRpc = GPU_GET_RPC(pGpu); \ - NV_ASSERT(pRpc != NULL); \ - if ((status == NV_OK) && (pRpc != NULL)) \ - status = RmRpcHwResourceBind(pGpu, pRpc, hclient, hdevice, \ - hresource, virtaddr, physaddr); \ - if (pRpc == NULL) \ - status = NV_ERR_INSUFFICIENT_RESOURCES; \ - } while(0) - #define NV_RM_RPC_SIM_LOAD_ESCAPE_FUNCTIONS(pos) \ do \ { \ @@ -464,17 +455,6 @@ while(0) /* outgoing updates to the plugin */ -#define NV_RM_RPC_SIM_ADD_DISP_CONTEXT_DMA(pGpu, hclient, pcontextdma, channelnum) \ - do \ - { \ - NV_STATUS status; \ - SLI_LOOP_START(SLI_LOOP_FLAGS_BC_ONLY) \ - status = RmRpcSimAddDisplayContextDma(pGpu, hclient, pcontextdma, channelnum); \ - NV_ASSERT(status == NV_OK); \ - SLI_LOOP_END \ - } \ - while(0) - #define NV_RM_RPC_SIM_UPDATE_DISP_CONTEXT_DMA(pGpu, hclient, pcontextdma, physaddrnew, \ physlimitnew, pagesize, ptekind) \ do \ @@ -545,13 +525,13 @@ status = NV_ERR_INSUFFICIENT_RESOURCES; \ } while(0) -#define NV_RM_RPC_UNLOADING_GUEST_DRIVER(pGpu, status, bSuspend, bGc6Entering, newPMLevel) \ +#define NV_RM_RPC_UNLOADING_GUEST_DRIVER(pGpu, status, bInPMTransition, bGc6Entering, newPMLevel) \ do \ { \ OBJRPC *pRpc = GPU_GET_RPC(pGpu); \ NV_ASSERT(pRpc != NULL); \ if ((status == NV_OK) && (pRpc != NULL)) \ - status = rpcUnloadingGuestDriver_HAL(pGpu, pRpc, bSuspend, bGc6Entering, newPMLevel); \ + status = rpcUnloadingGuestDriver_HAL(pGpu, pRpc, bInPMTransition, bGc6Entering, newPMLevel); \ else if (pRpc == NULL) \ status = NV_ERR_INSUFFICIENT_RESOURCES; \ } \ @@ -693,6 +673,17 @@ status = NV_ERR_INSUFFICIENT_RESOURCES; \ } while (0) +#define NV_RM_RPC_ECC_NOTIFIER_WRITE_ACK(pGpu, status) \ + do \ + { \ + OBJRPC *pRpc = GPU_GET_RPC(pGpu); \ + NV_ASSERT(pRpc != NULL); \ + if ((status == NV_OK) && (pRpc != NULL)) \ + status = rpcEccNotifierWriteAck_HAL(pGpu, pRpc); \ + else if (pRpc == NULL) \ + status = NV_ERR_INSUFFICIENT_RESOURCES; \ + } while (0) + #define NV_RM_RPC_RMFS_INIT(pGpu, statusQueueMemDesc, status) do {} while(0) #define NV_RM_RPC_RMFS_CLOSE_QUEUE(pGpu, status) do {} while(0) @@ -703,13 +694,11 @@ testData3, status) do {} while(0) static inline NV_STATUS RmRpcSimFreeInfra(OBJGPU *pGpu, ...) { return NV_OK; } -static inline NV_STATUS RmRpcSimAddDisplayContextDma(OBJGPU *pGpu, ...) { return NV_ERR_NOT_SUPPORTED; } static inline NV_STATUS RmRpcSimUpdateDisplayContextDma(OBJGPU *pGpu, ...) { return NV_ERR_NOT_SUPPORTED; } static inline NV_STATUS RmRpcSimDeleteDisplayContextDma(OBJGPU *pGpu, ...) { return NV_ERR_NOT_SUPPORTED; } static inline NV_STATUS RmRpcSimUpdateDispChannelInfo(OBJGPU *pGpu, ...) { return NV_ERR_NOT_SUPPORTED; } static inline NV_STATUS RmRpcHwResourceAlloc(OBJGPU *pGpu, ...) { return NV_ERR_NOT_SUPPORTED; } static inline NV_STATUS RmRpcHwResourceFree(OBJGPU *pGpu, ...) { return NV_ERR_NOT_SUPPORTED; } -static inline NV_STATUS RmRpcHwResourceBind(OBJGPU *pGpu, ...) { return NV_ERR_NOT_SUPPORTED; } static inline NV_STATUS RmRpcPerfGetPstateInfo(OBJGPU *pGpu, ...) { return NV_ERR_NOT_SUPPORTED; } static inline NV_STATUS RmRpcPerfGetCurrentPstate(OBJGPU *pGpu, ...) { return NV_ERR_NOT_SUPPORTED; } static inline NV_STATUS RmRpcPerfGetVirtualPstateInfo(OBJGPU *pGpu, ...) { return NV_ERR_NOT_SUPPORTED; } diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/kernel/inc/vgpu/rpc_global_enums.h nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/kernel/inc/vgpu/rpc_global_enums.h --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/kernel/inc/vgpu/rpc_global_enums.h 2023-10-25 20:20:48.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/kernel/inc/vgpu/rpc_global_enums.h 2024-03-05 22:13:10.000000000 +0000 @@ -205,7 +205,10 @@ X(RM, CTRL_GET_TOTAL_HS_CREDITS) // 196 X(RM, CTRL_GET_HS_CREDITS) // 197 X(RM, CTRL_SET_HS_CREDITS) // 198 - X(RM, CTRL_PM_AREA_PC_SAMPLER) // 199 + X(RM, CTRL_PM_AREA_PC_SAMPLER) // 199 + X(RM, INVALIDATE_TLB) // 200 + X(RM, RESERVED_201) // 201 + X(RM, ECC_NOTIFIER_WRITE_ACK) // 202 X(RM, NUM_FUNCTIONS) //END #ifdef DEFINING_X_IN_RPC_GLOBAL_ENUMS_H }; @@ -246,8 +249,10 @@ E(TIMED_SEMAPHORE_RELEASE) // 0x1018 E(NVLINK_IS_GPU_DEGRADED) // 0x1019 E(PFM_REQ_HNDLR_STATE_SYNC_CALLBACK) // 0x101a + E(GSP_SEND_USER_SHARED_DATA) // 0x101b E(NVLINK_FAULT_UP) // 0x101c E(GSP_LOCKDOWN_NOTICE) // 0x101d + E(MIG_CI_CONFIG_UPDATE) // 0x101e E(NUM_EVENTS) // END #ifdef DEFINING_E_IN_RPC_GLOBAL_ENUMS_H }; diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/kernel/inc/vgpu/sdk-structures.h nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/kernel/inc/vgpu/sdk-structures.h --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/kernel/inc/vgpu/sdk-structures.h 2023-10-25 20:20:48.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/kernel/inc/vgpu/sdk-structures.h 2024-03-05 22:13:10.000000000 +0000 @@ -106,6 +106,7 @@ #define NV2080_CTRL_NVLINK_MAX_LINKS_v15_02 6 #define NV2080_CTRL_NVLINK_MAX_LINKS_v1A_18 12 +#define NV2080_CTRL_NVLINK_MAX_LINKS_v23_04 24 #define NV0000_CTRL_P2P_CAPS_INDEX_TABLE_SIZE_v15_02 8 #define NV0000_CTRL_P2P_CAPS_INDEX_TABLE_SIZE_v1F_0D 9 @@ -122,6 +123,8 @@ #define NV0080_CTRL_GR_INFO_MAX_SIZE_1C_01 (0x00000030) #define NV0080_CTRL_GR_INFO_MAX_SIZE_1E_02 (0x00000032) #define NV0080_CTRL_GR_INFO_MAX_SIZE_21_01 (0x00000033) +#define NV0080_CTRL_GR_INFO_MAX_SIZE_22_02 (0x00000034) +#define NV0080_CTRL_GR_INFO_MAX_SIZE_23_00 (0x00000035) #define NV2080_CTRL_INTERNAL_GR_MAX_ENGINES_1B_04 8 #define NV2080_CTRL_INTERNAL_GR_MAX_SM_v1B_05 256 #define NV2080_CTRL_INTERNAL_GR_MAX_SM_v1E_03 240 @@ -132,11 +135,10 @@ #define NV2080_CTRL_MC_GET_STATIC_INTR_TABLE_MAX_v1E_09 32 #define NV2080_CTRL_PERF_GPUMON_SAMPLE_COUNT_PERFMON_UTIL_v1F_0E 72 #define NV2080_CTRL_GPU_PARTITION_FLAG_COMPUTE_SIZE__SIZE_v20_04 6 -#define NV2080_CTRL_MIGRATABLE_OPS_ARRAY_MAX_v21_07 50 #define NVB0CC_MAX_CREDIT_INFO_ENTRIES_v21_08 63 +#define NV2080_CTRL_MIGRATABLE_OPS_ARRAY_MAX_v21_07 50 #define NV2080_CTRL_MAX_PCES_v21_0A 32 #define NV2080_CTRL_CE_CAPS_TBL_SIZE_v21_0A 2 -#define NV2080_ENGINE_TYPE_COPY_SIZE_v21_0A 10 // Defined this intermediate RM-RPC structure for making RPC call from Guest as // we have the restriction of passing max 4kb of data to plugin and the @@ -181,8 +183,7 @@ */ #define VGPU_CACHED_RMCTRL_LIST \ - VGPU_CACHED_RMCTRL_ENTRY(NV2080_CTRL_CMD_PERF_VPSTATES_GET_INFO, NV2080_CTRL_PERF_VPSTATES_INFO) \ - VGPU_CACHED_RMCTRL_ENTRY(NV2080_CTRL_CMD_GPU_GET_MAX_SUPPORTED_PAGE_SIZE, NV2080_CTRL_GPU_GET_MAX_SUPPORTED_PAGE_SIZE_PARAMS) + VGPU_CACHED_RMCTRL_ENTRY(NV2080_CTRL_CMD_PERF_VPSTATES_GET_INFO, NV2080_CTRL_PERF_VPSTATES_INFO) enum VGPU_CACHED_RMCTRL_INDICES { @@ -213,29 +214,6 @@ NvU8 capsTbl[NV0080_CTRL_BSP_CAPS_TBL_SIZE]; } VGPU_BSP_CAPS; -#define VGPU_PAGE_SIZE 4096 -#define NUM_MFN_PAGES 16 - -typedef struct HYPERV_SHARED_MEMORY_DESCRIPTOR -{ - union - { - struct - { - NvU32 shm_lock; - NvU64 vmbus_packet_id NV_ALIGN_BYTES(8); - }; - - char control_page[VGPU_PAGE_SIZE]; - }; - - NvU32 mfn_data[NUM_MFN_PAGES * VGPU_PAGE_SIZE / sizeof(NvU32)]; - -} HYPERV_SHARED_MEMORY_DESCRIPTOR; - -#define HYPERV_SHM_MFN_WRITE_WAIT 0 -#define HYPERV_SHM_MFN_WRITE_COMPLETE 1 - #define NV2080_CTRL_GPU_ECC_UNIT_COUNT_v15_01 (0x00000014) #define NV2080_CTRL_GPU_ECC_UNIT_COUNT_v1A_04 (0x00000014) #define NV2080_CTRL_GPU_ECC_UNIT_COUNT_v1C_09 (0x00000016) @@ -244,6 +222,11 @@ #define NV2080_ENGINE_TYPE_LAST_v18_01 (0x0000002a) #define NV2080_ENGINE_TYPE_LAST_v1C_09 (0x00000034) +#define NV2080_ENGINE_TYPE_LAST_v1A_00 (0x2a) + +#define NV2080_ENGINE_TYPE_COPY_SIZE_v1A_0D (10) +#define NV2080_ENGINE_TYPE_COPY_SIZE_v22_00 (10) + #define NV2080_CTRL_BUS_INFO_MAX_LIST_SIZE_v1A_0F (0x00000033) #define NV2080_CTRL_BUS_INFO_MAX_LIST_SIZE_v1C_09 (0x00000034) diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/kernel/inc/vgpu/vgpu_guest_pma_scrubber.h nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/kernel/inc/vgpu/vgpu_guest_pma_scrubber.h --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/kernel/inc/vgpu/vgpu_guest_pma_scrubber.h 2023-10-25 20:20:48.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/kernel/inc/vgpu/vgpu_guest_pma_scrubber.h 2024-03-05 22:13:11.000000000 +0000 @@ -34,7 +34,7 @@ #ifndef __vgpu_pma_guest_scrubber_h__ #define __vgpu_pma_guest_scrubber_h__ -#include "gpu/mem_mgr/virt_mem_allocator_common.h" +#include "gpu/mem_mgr/rm_page_size.h" #define VGPU_GUEST_PMA_MAX_SCRUB_ITEMS 4096 #define VGPU_GUEST_PMA_SCRUBBER_SHARED_BUFFER_SIZE ((sizeof(VGPU_SCRUB_NODE) * VGPU_GUEST_PMA_MAX_SCRUB_ITEMS) + RM_PAGE_SIZE) diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/kernel/inc/vgpu/vgpu_version.h nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/kernel/inc/vgpu/vgpu_version.h --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/kernel/inc/vgpu/vgpu_version.h 2023-10-25 20:20:48.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/kernel/inc/vgpu/vgpu_version.h 2024-03-05 22:13:11.000000000 +0000 @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 2008-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2008-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -30,9 +30,8 @@ #define RPC_VERSION_FROM_VGX_VERSION(major, minor) ( DRF_NUM(_RPC, _VERSION_NUMBER, _MAJOR, major) | \ DRF_NUM(_RPC, _VERSION_NUMBER, _MINOR, minor)) -#define VGX_MAJOR_VERSION_NUMBER 0x21 -#define VGX_MINOR_VERSION_NUMBER 0x0C - +#define VGX_MAJOR_VERSION_NUMBER 0x23 +#define VGX_MINOR_VERSION_NUMBER 0x05 #define VGX_MAJOR_VERSION_NUMBER_VGPU_12_0 0x1A #define VGX_MINOR_VERSION_NUMBER_VGPU_12_0 0x18 @@ -50,6 +49,8 @@ * 2. This is the first break in migration compatibility after a release. */ #define NV_VGPU_GRIDSW_INTERNAL_TO_EXTERNAL_VERSION_MAPPING \ + {{0x23, 0x0}, {0x23, 0x05}, {0x12, 0x1}}, \ + {{0x22, 0x0}, {0x22, 0x02}, {0x11, 0x1}}, \ {{0x21, 0x0}, {0x21, 0x0C}, {0x10, 0x1}}, \ {{0x20, 0x0}, {0x20, 0x04}, {0xF, 0x1}}, \ {{0x1F, 0x0}, {0x1F, 0xF}, {0xE, 0x1}}, \ @@ -94,7 +95,7 @@ /* WARNING: Should be updated with each vGPU release, if there is a break in * migration compatibility during the development of that release. */ -#define NV_VGPU_MAX_SUPPORTED_GRIDSW_VERSION_EXTERNAL_MAJOR 0x10 +#define NV_VGPU_MAX_SUPPORTED_GRIDSW_VERSION_EXTERNAL_MAJOR 0x12 #define NV_VGPU_MAX_SUPPORTED_GRIDSW_VERSION_EXTERNAL_MINOR 0x1 /* WARNING: Should be updated with each vGPU release, if minimum supported diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/kernel/nvd/nv/nvdctrl.c nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/kernel/nvd/nv/nvdctrl.c --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/kernel/nvd/nv/nvdctrl.c 2023-10-25 20:20:49.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/kernel/nvd/nv/nvdctrl.c 2024-03-05 22:13:11.000000000 +0000 @@ -213,9 +213,9 @@ pReportParams->nocatOutstandingRecordCount = rcdbGetNocatOutstandingCount(pRcdb); // add in the activity counters. - portMemCopy(pReportParams->activityCounters, NV_SIZEOF32(pReportParams->activityCounters), + portMemCopy(pReportParams->activityCounters, sizeof(pReportParams->activityCounters), pRcdb->nocatJournalDescriptor.nocatEventCounters, - NV_SIZEOF32(pRcdb->nocatJournalDescriptor.nocatEventCounters)); + sizeof(pRcdb->nocatJournalDescriptor.nocatEventCounters)); } return status; } diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/kernel/vgpu/nv/objvgpu.c nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/kernel/vgpu/nv/objvgpu.c --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/kernel/vgpu/nv/objvgpu.c 2023-10-25 20:20:49.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/kernel/vgpu/nv/objvgpu.c 2024-03-05 22:13:11.000000000 +0000 @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 2017-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2017-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -22,6 +22,7 @@ */ #include "core/core.h" +#include "core/locks.h" #include "os/os.h" #include "gpu/gpu.h" #include "vgpu/vgpu_version.h" @@ -39,7 +40,7 @@ OBJGPU *pGpu ) { - NV_STATUS rmStatus = NV_OK; + NV_STATUS rmStatus = NV_OK; return rmStatus; } diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/kernel/vgpu/nv/rpc.c nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/kernel/vgpu/nv/rpc.c --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/kernel/vgpu/nv/rpc.c 2023-10-25 20:20:49.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/kernel/vgpu/nv/rpc.c 2024-03-05 22:13:11.000000000 +0000 @@ -28,11 +28,15 @@ // //****************************************************************************** +// FIXME XXX +#define NVOC_KERNEL_GRAPHICS_CONTEXT_H_PRIVATE_ACCESS_ALLOWED + #include "os/os.h" #include "core/system.h" #include "core/locks.h" #include "gpu/gpu.h" #include "gpu/bif/kernel_bif.h" +#include "gpu/subdevice/subdevice.h" #include "gpu/mem_mgr/mem_desc.h" #include "nvVer.h" #include "nvBldVer.h" @@ -50,9 +54,11 @@ #include "vgpu/rpc.h" #include "vgpu/vgpu_events.h" #include "virtualization/hypervisor/hypervisor.h" -#include "finn_rm_api.h" #include "os/os.h" #include "objtmr.h" +#include "lib/base_utils.h" + +#include "gpu/conf_compute/conf_compute.h" #define SDK_ALL_CLASSES_INCLUDE_FULL_HEADER #include "g_allclasses.h" @@ -74,6 +80,7 @@ #include "g_rpc_private.h" +#include "g_finn_rm_api.h" #include "gpu/gsp/message_queue_priv.h" @@ -176,6 +183,9 @@ osGetPerformanceCounter(&pNewEntry->rpcData.startTimeInNs); } + // For HCC, cache expectedFunc value before encrypting. + NvU32 expectedFunc = vgpu_rpc_message_header_v->function; + status = rpcSendMessage(pGpu, pRpc); if (status != NV_OK) { @@ -191,7 +201,8 @@ return (status == NV_ERR_BUSY_RETRY) ? NV_ERR_GENERIC : status; } - status = rpcRecvPoll(pGpu, pRpc, vgpu_rpc_message_header_v->function); + // Use cached expectedFunc here because vgpu_rpc_message_header_v is encrypted for HCC. + status = rpcRecvPoll(pGpu, pRpc, expectedFunc); if (status != NV_OK) { if (status == NV_ERR_TIMEOUT) @@ -273,11 +284,8 @@ // should not be called in broadcast mode NV_ASSERT_OR_RETURN(!gpumgrGetBcEnabledStatus(pGpu), NV_ERR_INVALID_STATE); - // // Copy the initial buffer - // Temporary black magic WAR for bug 3594082: reducing the size by 2 - // - entryLength = NV_MIN(bufSize, pRpc->maxRpcSize - 2); + entryLength = NV_MIN(bufSize, pRpc->maxRpcSize); if ((NvU8 *)vgpu_rpc_message_header_v != pBuf8) portMemCopy(vgpu_rpc_message_header_v, entryLength, pBuf8, entryLength); @@ -302,16 +310,20 @@ remainingSize -= entryLength; pBuf8 += entryLength; - // // Copy the remaining buffers - // Temporary black magic WAR for bug 3594082: reducing the size by 2 - // - entryLength = pRpc->maxRpcSize - sizeof(rpc_message_header_v) - 2; + entryLength = pRpc->maxRpcSize - sizeof(rpc_message_header_v); while (remainingSize != 0) { if (entryLength > remainingSize) entryLength = remainingSize; + ConfidentialCompute *pCC = GPU_GET_CONF_COMPUTE(pGpu); + if (pCC != NULL && pCC->getProperty(pCC, PDB_PROP_CONFCOMPUTE_ENCRYPT_ENABLED)) + { + // Zero out the entire RPC message header to clear the state of previous chunk. + portMemSet(vgpu_rpc_message_header_v, 0, sizeof(rpc_message_header_v)); + } + portMemCopy(rpc_message, entryLength, pBuf8, entryLength); // Set the correct length for this queue entry. @@ -679,17 +691,17 @@ { if (rpcVgxVersion.majorNum != 0) { - if (pGpu->getProperty(pGpu, PDB_PROP_GPU_IN_PM_RESUME_CODEPATH) && !bSkipRpcVersionHandshake) - { - bSkipRpcVersionHandshake = NV_TRUE; - } - else - { - NV_PRINTF(LEVEL_INFO, - "NVRM_RPC: Skipping RPC version handshake for instance 0x%x\n", - gpuGetInstance(pGpu)); - goto skip_ver_handshake; - } + if (pGpu->getProperty(pGpu, PDB_PROP_GPU_IN_PM_RESUME_CODEPATH) && !bSkipRpcVersionHandshake) + { + bSkipRpcVersionHandshake = NV_TRUE; + } + else + { + NV_PRINTF(LEVEL_INFO, + "NVRM_RPC: Skipping RPC version handshake for instance 0x%x\n", + gpuGetInstance(pGpu)); + goto skip_ver_handshake; + } } else { @@ -835,7 +847,7 @@ return status; } -NV_STATUS rpcUnloadingGuestDriver_v03_00(OBJGPU *pGpu, OBJRPC *pRpc, NvBool bSuspend, NvBool bGc6Entering, NvU32 newPMLevel) +NV_STATUS rpcUnloadingGuestDriver_v03_00(OBJGPU *pGpu, OBJRPC *pRpc, NvBool bInPMTransition, NvBool bGc6Entering, NvU32 newPMLevel) { NV_STATUS status = NV_OK; @@ -849,7 +861,7 @@ } -NV_STATUS rpcUnloadingGuestDriver_v1F_07(OBJGPU *pGpu, OBJRPC *pRpc, NvBool bSuspend, NvBool bGc6Entering, NvU32 newPMLevel) +NV_STATUS rpcUnloadingGuestDriver_v1F_07(OBJGPU *pGpu, OBJRPC *pRpc, NvBool bInPMTransition, NvBool bGc6Entering, NvU32 newPMLevel) { NV_STATUS status = NV_OK; NvU32 headerLength = sizeof(rpc_message_header_v) + sizeof(rpc_unloading_guest_driver_v1F_07); @@ -866,7 +878,7 @@ status = rpcWriteCommonHeader(pGpu, pRpc, NV_VGPU_MSG_FUNCTION_UNLOADING_GUEST_DRIVER, sizeof(rpc_unloading_guest_driver_v1F_07)); if (status != NV_OK) return status; - rpc_message->unloading_guest_driver_v1F_07.bSuspend = bSuspend; + rpc_message->unloading_guest_driver_v1F_07.bInPMTransition = bInPMTransition; rpc_message->unloading_guest_driver_v1F_07.bGc6Entering = bGc6Entering; rpc_message->unloading_guest_driver_v1F_07.newLevel = newPMLevel; @@ -1255,6 +1267,8 @@ if (IS_GSP_CLIENT(pGpu)) { + OBJSYS *pSys = SYS_GET_INSTANCE(); + OBJHYPERVISOR *pHypervisor = SYS_GET_HYPERVISOR(pSys); GspSystemInfo *rpcInfo = (GspSystemInfo *)&rpc_message->gsp_set_system_info_v17_00.data; const NvU32 messageLength = sizeof(rpc_message_header_v) + sizeof(*rpcInfo); @@ -1286,6 +1300,9 @@ NV_ASSERT_OK(kbifGetPciConfigSpacePriMirror_HAL(pGpu, pKernelBif, &rpcInfo->pciConfigMirrorBase, &rpcInfo->pciConfigMirrorSize)); + + // Cache MNOC interface support + rpcInfo->bMnocAvailable = pKernelBif->bMnocAvailable; } if (IS_SIMULATION(pGpu)) @@ -1319,6 +1336,9 @@ rpcInfo->bUpstreamL1PorMobileOnly = pGpu->getProperty(pGpu, PDB_PROP_GPU_UPSTREAM_PORT_L1_POR_MOBILE_ONLY); rpcInfo->upstreamAddressValid = pGpu->gpuClData.upstreamPort.addr.valid; + rpcInfo->hypervisorType = hypervisorGetHypervisorType(pHypervisor); + rpcInfo->bIsPassthru = pGpu->bIsPassthru; + // Fill in VF related GPU flags rpcInfo->gspVFInfo.totalVFs = pGpu->sriovState.totalVFs; rpcInfo->gspVFInfo.firstVFOffset = pGpu->sriovState.firstVFOffset; @@ -1354,7 +1374,7 @@ if (IS_GSP_CLIENT(pGpu)) { - NvU32 regTableSize; + NvU32 regTableSize = 0; NvU32 totalSize; NvU32 remainingMessageSize; PACKED_REGISTRY_TABLE *pRegTable; @@ -1400,18 +1420,20 @@ status = osPackageRegistry(pGpu, pRegTable, ®TableSize); if (status != NV_OK) - return status; + goto fail; if (largeRpcBuffer != NULL) { status = _issueRpcAsyncLarge(pGpu, pRpc, totalSize, largeRpcBuffer); - portMemFree(largeRpcBuffer); } else { vgpu_rpc_message_header_v->length = totalSize; status = _issueRpcAsync(pGpu, pRpc); } + + fail: + portMemFree(largeRpcBuffer); } return status; @@ -1544,17 +1566,17 @@ NvU32 rpc_params_size; NvU32 total_size; - const NvU32 interface_id = (DRF_VAL(XXXX, _CTRL_CMD, _CLASS, cmd) << 8) | - DRF_VAL(XXXX, _CTRL_CMD, _CATEGORY, cmd); - const NvU32 message_id = DRF_VAL(XXXX, _CTRL_CMD, _INDEX, cmd); - NvU8 *pSerBuffer = NULL; - NvU32 serializedSize = 0; - NvU32 origParamsSize = paramsSize; NvU32 gpuMaskRelease = 0; NvU32 ctrlFlags = 0; NvU32 ctrlAccessRight = 0; NvBool bCacheable; + CALL_CONTEXT *pCallContext; + CALL_CONTEXT newContext; + NvU32 resCtrlFlags = NVOS54_FLAGS_NONE; + NvBool bPreSerialized = NV_FALSE; + void *pOriginalParams = pParamStructPtr; + if (!rmDeviceGpuLockIsOwner(pGpu->gpuInstance)) { NV_PRINTF(LEVEL_WARNING, "Calling RPC RmControl 0x%08x without adequate locks!\n", cmd); @@ -1565,18 +1587,39 @@ GPU_LOCK_FLAGS_SAFE_LOCK_UPGRADE, RM_LOCK_MODULES_RPC, &gpuMaskRelease)); } - rmapiutilGetControlInfo(cmd, &ctrlFlags, &ctrlAccessRight); + rmapiutilGetControlInfo(cmd, &ctrlFlags, &ctrlAccessRight, NULL); bCacheable = rmapiControlIsCacheable(ctrlFlags, ctrlAccessRight, NV_TRUE); - // Attempt to calculate the serialized size of the param struct using FINN. - serializedSize = FinnRmApiGetSerializedSize(interface_id, message_id, pParamStructPtr); + pCallContext = resservGetTlsCallContext(); + if (pCallContext == NULL || pCallContext->bReserialize) + { + // This should only happen when using the internal physical RMAPI + NV_ASSERT_OR_RETURN(pRmApi == GPU_GET_PHYSICAL_RMAPI(pGpu), NV_ERR_INVALID_STATE); + + portMemSet(&newContext, 0, sizeof(newContext)); + pCallContext = &newContext; + } + + if (pCallContext->pControlParams != NULL) + { + resCtrlFlags = pCallContext->pControlParams->flags; + } + + if (resCtrlFlags & NVOS54_FLAGS_FINN_SERIALIZED) + { + bPreSerialized = NV_TRUE; + } + else + { + status = serverSerializeCtrlDown(pCallContext, cmd, &pParamStructPtr, ¶msSize, &resCtrlFlags); + if (status != NV_OK) + goto done; + } - // If successful, this is a serializable API and rpc_params->params is a serialized buffer. + // If this is a serializable API, rpc_params->params is a serialized buffer. // otherwise this is a flat API and paramsSize is the param struct size - if (serializedSize != 0) + if (resCtrlFlags & NVOS54_FLAGS_FINN_SERIALIZED) { - // Allocate twice the amount to account for the return buffer - paramsSize = 2 * serializedSize; NV_ASSERT_OR_RETURN(!bCacheable, NV_ERR_INVALID_STATE); } @@ -1601,7 +1644,13 @@ rpc_params->hObject = hObject; rpc_params->cmd = cmd; rpc_params->paramsSize = paramsSize; - rpc_params->copyOutOnError = !!(ctrlFlags & RMCTRL_FLAGS_COPYOUT_ON_ERROR); + rpc_params->flags = RMAPI_RPC_FLAGS_NONE; + + if (ctrlFlags & RMCTRL_FLAGS_COPYOUT_ON_ERROR) + rpc_params->flags |= RMAPI_RPC_FLAGS_COPYOUT_ON_ERROR; + + if (resCtrlFlags & NVOS54_FLAGS_FINN_SERIALIZED) + rpc_params->flags |= RMAPI_RPC_FLAGS_SERIALIZED; // If we have a big payload control, we need to make a local copy... if (message_buffer_remaining < paramsSize) @@ -1613,65 +1662,40 @@ message_buffer_remaining = total_size - fixed_param_size; } - // If this is a serializable API, attempt to serialize the param struct using FINN, - // otherwise do a flat memcpy - if (serializedSize != 0) - { - rpc_params->serialized = NV_TRUE; - pSerBuffer = (NvU8 *)rpc_params->params; - - // Serialize into the first half of the RPC buffer. - status = FinnRmApiSerializeDown(interface_id, message_id, pParamStructPtr, - &pSerBuffer, message_buffer_remaining); - if (status != NV_OK) - { - NV_PRINTF(LEVEL_ERROR, - "GspRmControl: Serialization failed for cmd 0x%x with status %s (0x%x) at index 0x%llx\n", - cmd, nvAssertStatusToString(status), status, - (NvUPtr)(pSerBuffer - (NvU8 *)rpc_params->params)); - goto done; - } - } - else + if (paramsSize != 0) { - rpc_params->serialized = NV_FALSE; - - if (paramsSize != 0) - { - if (pParamStructPtr == NULL) - { - status = NV_ERR_INVALID_ARGUMENT; - goto done; - } - else - { - // Serialize RM control - for now a simple memcpy, could be more when FINN comes - if (portMemCopy(rpc_params->params, message_buffer_remaining, pParamStructPtr, paramsSize) == NULL) - { - status = NV_ERR_BUFFER_TOO_SMALL; - goto done; - } - } - } - else if (pParamStructPtr != NULL) + if (pParamStructPtr == NULL) { - NV_PRINTF(LEVEL_ERROR, "Bad params: ptr " NvP64_fmt " size: 0x%x\n", - pParamStructPtr, paramsSize); status = NV_ERR_INVALID_ARGUMENT; goto done; } else { - // - // paramsSize = 0 and pParamStructPtr == NULL - // rpc_params->params is static, cannot be set to NULL. - // We will allow rpc_params->paramsSize = 0 and - // rpc_params->params != NULL from here, but in - // _rpcGspRmControl() have the logic that - // pc_params->paramsSize = 0 means no params. - // + if (portMemCopy(rpc_params->params, message_buffer_remaining, pParamStructPtr, paramsSize) == NULL) + { + status = NV_ERR_BUFFER_TOO_SMALL; + goto done; + } } } + else if (pParamStructPtr != NULL) + { + NV_PRINTF(LEVEL_ERROR, "Bad params: ptr " NvP64_fmt " size: 0x%x\n", + pParamStructPtr, paramsSize); + status = NV_ERR_INVALID_ARGUMENT; + goto done; + } + else + { + // + // paramsSize = 0 and pParamStructPtr == NULL + // rpc_params->params is static, cannot be set to NULL. + // We will allow rpc_params->paramsSize = 0 and + // rpc_params->params != NULL from here, but in + // _rpcGspRmControl() have the logic that + // pc_params->paramsSize = 0 means no params. + // + } // Issue RPC if (large_message_copy) @@ -1691,28 +1715,27 @@ if (status == NV_OK) { // Skip copyout if we got an error from the GSP control handler - if (rpc_params->status != NV_OK && !rpc_params->copyOutOnError) + if (rpc_params->status != NV_OK && !(rpc_params->flags & RMAPI_RPC_FLAGS_COPYOUT_ON_ERROR)) { status = rpc_params->status; goto done; } - // If FINN was used to serialize the params, they must be deserialized on the way back, - // otherwise do a flat memcpy - if (serializedSize != 0) - { - NvU8 *pRetBuffer = pSerBuffer; - - // Deserialize from the second half of the RPC buffer. - status = FinnRmApiDeserializeUp(&pSerBuffer, paramsSize / 2, - pParamStructPtr, origParamsSize); - if (status != NV_OK) + if (resCtrlFlags & NVOS54_FLAGS_FINN_SERIALIZED) + { + // + // If it was preserialized, copy it to call context for deserialization by caller + // Otherwise deserialize it because it was serialized here + // + if (bPreSerialized) { - NV_PRINTF(LEVEL_ERROR, - "GspRmControl: Deserialization failed for cmd 0x%x with status %s (0x%x) at index 0x%llx\n", - cmd, nvAssertStatusToString(status), status, - (NvUPtr)(pSerBuffer - pRetBuffer)); - goto done; + portMemCopy(pCallContext->pSerializedParams, pCallContext->serializedSize, rpc_params->params, rpc_params->paramsSize); + } + else + { + status = serverDeserializeCtrlUp(pCallContext, cmd, &pParamStructPtr, ¶msSize, &resCtrlFlags); + if (status != NV_OK) + goto done; } } else @@ -1752,6 +1775,15 @@ // Free the local copy we might have allocated above portMemFree(large_message_copy); + // + // Free data structures if we serialized/deserialized here + // Also check for serialized flag here as we may be called directly from within another control call + // + if ((resCtrlFlags & NVOS54_FLAGS_FINN_SERIALIZED) && !bPreSerialized) + { + serverFreeSerializeStructures(pCallContext, pOriginalParams); + } + return status; } @@ -1762,7 +1794,8 @@ NvHandle hParent, NvHandle hObject, NvU32 hClass, - void *pAllocParams + void *pAllocParams, + NvU32 allocParamsSize ) { NV_STATUS status = NV_ERR_NOT_SUPPORTED; @@ -1771,7 +1804,10 @@ OBJRPC *pRpc = GPU_GET_RPC(pGpu); rpc_gsp_rm_alloc_v03_00 *rpc_params = &rpc_message->gsp_rm_alloc_v03_00; + CALL_CONTEXT callContext = {0}; + NvU32 flags = RMAPI_ALLOC_FLAGS_NONE; NvU32 paramsSize; + void *pOriginalParams = pAllocParams; NvBool bNullAllowed; const NvU32 fixed_param_size = sizeof(rpc_message_header_v) + sizeof(*rpc_params); @@ -1816,24 +1852,40 @@ rpc_params->hParent = hParent; rpc_params->hObject = hObject; rpc_params->hClass = hClass; - rpc_params->paramsSize = pAllocParams ? paramsSize : 0; + rpc_params->flags = RMAPI_RPC_FLAGS_NONE; - // Serialize RM alloc - for now a simple memcpy, could be more when FINN comes + // Serialize RM alloc if (paramsSize > 0) { - if (portMemCopy(rpc_params->params, message_buffer_remaining, pAllocParams, paramsSize) == NULL) + void *memCopyResult; + + NV_CHECK_OK_OR_GOTO(status, LEVEL_INFO, serverSerializeAllocDown(&callContext, hClass, &pAllocParams, ¶msSize, &flags), done); + if (flags & RMAPI_ALLOC_FLAGS_SERIALIZED) + { + rpc_params->flags |= RMAPI_RPC_FLAGS_SERIALIZED; + } + + memCopyResult = portMemCopy(rpc_params->params, message_buffer_remaining, pAllocParams, paramsSize); + rpc_params->paramsSize = paramsSize; + + if (memCopyResult == NULL) { status = NV_ERR_BUFFER_TOO_SMALL; goto done; } } + else + { + rpc_params->paramsSize = 0; + } status = _issueRpcAndWait(pGpu, pRpc); if (status == NV_OK) { - // Deserialize - if (paramsSize > 0) + // Deserialize. pAllocParams will be populated correctly if deserialized + NV_CHECK_OK_OR_GOTO(status, LEVEL_INFO, serverDeserializeAllocUp(&callContext, hClass, &pAllocParams, ¶msSize, &flags), done); + if (!(flags & RMAPI_ALLOC_FLAGS_SERIALIZED) && (paramsSize > 0)) { portMemCopy(pAllocParams, paramsSize, rpc_params->params, paramsSize); } @@ -1851,6 +1903,8 @@ { rmGpuGroupLockRelease(gpuMaskRelease, GPUS_LOCK_FLAGS_NONE); } + serverFreeSerializeStructures(&callContext, pOriginalParams); + return status; } @@ -1950,3 +2004,27 @@ } return status; } + +/* + * Sends ack from CPU-RM to GSP-RM that ECC error + * notifier write has completed. + */ +NV_STATUS rpcEccNotifierWriteAck_v23_05 +( + OBJGPU *pGpu, + OBJRPC *pRpc +) +{ + NV_STATUS status = NV_ERR_NOT_SUPPORTED; + + if (IS_GSP_CLIENT(pGpu)) + { + status = rpcWriteCommonHeader(pGpu, pRpc, NV_VGPU_MSG_FUNCTION_ECC_NOTIFIER_WRITE_ACK, 0); + if (status != NV_OK) + return status; + + status = _issueRpcAsync(pGpu, pRpc); + } + + return status; +} diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/kernel/compute/fabric.c nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/kernel/compute/fabric.c --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/kernel/compute/fabric.c 2023-10-25 20:20:49.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/kernel/compute/fabric.c 2024-03-05 22:13:11.000000000 +0000 @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 2019-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2019-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -97,7 +97,8 @@ FabricCacheEntry *pEntry; pEntry = multimapFindItem(pCache, key1, key2); - NV_ASSERT_OR_RETURN_VOID(pEntry != NULL); + if (pEntry == NULL) + return; mapRemoveByKey(&pEntry->map, key3); if (mapCount(&pEntry->map) > 0) diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/kernel/core/hal/hal.c nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/kernel/core/hal/hal.c --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/kernel/core/hal/hal.c 2023-10-25 20:20:50.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/kernel/core/hal/hal.c 2024-03-05 22:13:12.000000000 +0000 @@ -68,54 +68,3 @@ return NV_OK; } - -// Helper to install IP_VERSIONS function pointers into pObj->hal fn ptr table -// based on IP_VER register value. -// Uses tables and code in g_FOO_private.h (generated by rmconfig) - -NV_STATUS ipVersionsSetupHal -( - OBJGPU *pGpu, - void * pDynamic_v, // eg: pDisp - IGrp_ipVersions_getInfo getInfoFn // eg: disp_iGrp_ipVersions_getInfo() -) -{ - IGRP_IP_VERSIONS_TABLE_INFO info; - const IGRP_IP_VERSIONS_ENTRY *pVer; - const IGRP_IP_VERSION_RANGE *pRange; - NV_STATUS rmStatus; - Dynamic *pDynamic = (Dynamic*)pDynamic_v; - Object *pObj = dynamicCast(pDynamic, Object); - - // nothing to do if IP_VERSION is invalid - if ( ! IsIPVersionValid(pObj)) - return NV_OK; - - info.pGpu = pGpu; - info.pDynamic = pDynamic; - - // call into the hal to finish filling in the table - rmStatus = getInfoFn(&info); - if (rmStatus != NV_OK) - return rmStatus; - - // perform setup for *all* matching variants - for (pVer = info.pTable; pVer < info.pTable + info.numEntries; pVer++) - { - // Each version has 1 or more "version ranges". - // Invoke this version's setup fn if any of it's ranges match. - for (pRange = pVer->pRanges; pRange < (pVer->pRanges + pVer->numRanges); pRange++) - { - if ((IPVersion(pObj) >= pRange->v0) && (IPVersion(pObj) <= pRange->v1)) - { - pVer->ifacesInstallFn(&info); - break; - } - } - } - - // invoke rmconfig-generated wrapup function to handle any overrides & verification - rmStatus = info.ifacesWrapupFn(&info); - - return rmStatus; -} diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/kernel/core/hal_mgr.c nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/kernel/core/hal_mgr.c --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/kernel/core/hal_mgr.c 2023-10-25 20:20:50.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/kernel/core/hal_mgr.c 2024-03-05 22:13:12.000000000 +0000 @@ -214,7 +214,7 @@ } halImplNames[] = { HAL_IMPL_NAME_LIST }; // generated by rmconfig into g_hal.h NvU32 i; - for (i = 0; i < NV_ARRAY_ELEMENTS32(halImplNames); i++) + for (i = 0; i < NV_ARRAY_ELEMENTS(halImplNames); i++) { if (halImplNames[i].halImpl == halImpl) { diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/kernel/core/locks.c nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/kernel/core/locks.c --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/kernel/core/locks.c 2023-10-25 20:20:50.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/kernel/core/locks.c 2024-03-05 22:13:12.000000000 +0000 @@ -39,6 +39,7 @@ #include #include "kernel/gpu/intr/intr.h" #include +#include "gpu/disp/kern_disp.h" // // GPU lock @@ -1486,6 +1487,9 @@ OBJSYS *pSys = SYS_GET_INSTANCE(); OBJGPU *pDpcGpu = NULL; + if (gpuMask == 0) + return NV_SEMA_RELEASE_SUCCEED; + // // QuadroSync (previously known as GSync) is a cross GPU feature that // synchronizes display across multiple GPUs. See changelist 16809243. If diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/kernel/core/system.c nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/kernel/core/system.c --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/kernel/core/system.c 2023-10-25 20:20:50.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/kernel/core/system.c 2024-03-05 22:13:12.000000000 +0000 @@ -47,6 +47,7 @@ #include "platform/cpu.h" #include "platform/platform.h" #include "diagnostics/gpu_acct.h" +#include "platform/platform_request_handler.h" #include "gpu/external_device/gsync.h" #include "virtualization/kernel_vgpu_mgr.h" #include "mem_mgr/virt_mem_mgr.h" @@ -83,6 +84,7 @@ { NV_OFFSETOF(OBJSYS, pGpuMgr), classInfo(OBJGPUMGR), NV_TRUE }, { NV_OFFSETOF(OBJSYS, pGsyncMgr), classInfo(OBJGSYNCMGR), NV_TRUE }, { NV_OFFSETOF(OBJSYS, pGpuAcct), classInfo(GpuAccounting), NV_TRUE }, + { NV_OFFSETOF(OBJSYS, pPlatformRequestHandler), classInfo(PlatformRequestHandler), NV_TRUE }, { NV_OFFSETOF(OBJSYS, pRcDB), classInfo(OBJRCDB), NV_TRUE }, { NV_OFFSETOF(OBJSYS, pVmm), classInfo(OBJVMM), NV_TRUE }, { NV_OFFSETOF(OBJSYS, pKernelVgpuMgr), classInfo(KernelVgpuMgr), NV_TRUE }, @@ -200,7 +202,7 @@ NV_STATUS status = NV_OK; NvU32 i, n; - n = NV_ARRAY_ELEMENTS32(sysChildObjects); + n = NV_ARRAY_ELEMENTS(sysChildObjects); for (i = 0; i < n; i++) { @@ -252,7 +254,7 @@ osRmCapUnregister(&pSys->pOsRmCaps); - for (i = NV_ARRAY_ELEMENTS32(sysChildObjects) - 1; i >= 0; i--) + for (i = NV_ARRAY_ELEMENTS(sysChildObjects) - 1; i >= 0; i--) { NvLength offset = sysChildObjects[i].childOffset; Dynamic **ppChild = reinterpretCast(reinterpretCast(pSys, NvU8*) + offset, Dynamic**); @@ -325,6 +327,18 @@ { pSys->setProperty(pSys, PDB_PROP_SYS_CLIENT_HANDLE_LOOKUP, !!data32); } + + if (osReadRegistryDword(pGpu, NV_REG_STR_RM_CLIENT_LIST_DEFERRED_FREE, + &data32) == NV_OK) + { + pSys->bUseDeferredClientListFree = !!data32; + } + + if (osReadRegistryDword(pGpu, NV_REG_STR_RM_CLIENT_LIST_DEFERRED_FREE_LIMIT, + &data32) == NV_OK) + { + pSys->clientListDeferredFreeLimit = data32; + } } static void @@ -656,15 +670,6 @@ pSys->setProperty(pSys, PDB_PROP_SYS_PRIORITY_THROTTLE_DELAY_US, data32); } - if (osReadRegistryDword(pGpu, NV_REG_STR_RM_MULTICAST_FLA, - &data32) == NV_OK) - { - if (data32 == NV_REG_STR_RM_MULTICAST_FLA_ENABLED) - { - pSys->bMulticastFlaEnabled = NV_TRUE; - } - } - _sysRegistryOverrideExternalFabricMgmt(pSys, pGpu); _sysRegistryOverrideResourceServer(pSys, pGpu); @@ -678,6 +683,8 @@ { pSys->setProperty(pSys, PDB_PROP_SYS_ROUTE_TO_PHYSICAL_LOCK_BYPASS, !!data32); } + + gpumgrSetGpuNvlinkBwModeFromRegistry(pGpu); } void diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/kernel/core/thread_state.c nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/kernel/core/thread_state.c --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/kernel/core/thread_state.c 2023-10-25 20:20:50.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/kernel/core/thread_state.c 2024-03-05 22:13:13.000000000 +0000 @@ -1135,7 +1135,7 @@ // Log the Timeout in the RM Journal RmRC2GpuTimeout3_RECORD* pRec = NULL; - rcdbAddAssertJournalRecWithLine(pGpu, lineNum, (void**)&pRec, + rcdbAddAssertJournalRecWithLine(pGpu, lineNum, (void**)&pRec, RmGroup, RmRC2GpuTimeout_V3, sizeof(RmRC2GpuTimeout3_RECORD), DRF_DEF(_RM, _ASSERT, _TYPE, _INFO), diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/kernel/diagnostics/gpu_acct.c nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/kernel/diagnostics/gpu_acct.c --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/kernel/diagnostics/gpu_acct.c 2023-10-25 20:20:51.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/kernel/diagnostics/gpu_acct.c 2024-03-05 22:13:13.000000000 +0000 @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 2013-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2013-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -156,8 +156,9 @@ { NV_ASSERT_OR_RETURN(pDS != NULL, NV_ERR_INVALID_ARGUMENT); - GPU_ACCT_PROC_LISTIter iter = listIterAll(&pDS->procList); - while (listIterNext(&iter)) + for (GPU_ACCT_PROC_LISTIter iter = listIterAll(&pDS->procList); + listIterNext(&iter); + iter = listIterAll(&pDS->procList)) { GPUACCT_PROC_ENTRY *pEntry = iter.pValue; if (pEntry) diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/kernel/diagnostics/journal.c nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/kernel/diagnostics/journal.c --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/kernel/diagnostics/journal.c 2023-10-25 20:20:51.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/kernel/diagnostics/journal.c 2024-03-05 22:13:13.000000000 +0000 @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 1993-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 1993-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -45,6 +45,7 @@ #include "gpu/mem_mgr/mem_mgr.h" #include "nvdevid.h" #include "nvop.h" +#include "jt.h" @@ -87,7 +88,7 @@ static volatile NvS32 probeGpuRecursion = 0; #endif #endif -static NvU32 _rcdbGetOcaRecordSizeWithHeader(Journal *pRcDB, RMCD_RECORD_TYPE type); +static NvU32 _rcdbGetOcaRecordSize(Journal *pRcDB, RMCD_RECORD_TYPE type); static volatile NvS32 concurrentRingBufferAccess = 0; static volatile NvS32 assertListRecursion = 0; static void rcdbFindRingBufferForType(Journal *pRcDB, RMCD_RECORD_TYPE recType, RING_BUFFER_LOG **ppRingBuffer); @@ -254,8 +255,8 @@ pRcDB->rcErrorCounterArray[RC_ERROR_COUNTER_OTHER_INDEX].rcErrorType = RC_ERROR_COUNTER_OTHER_TYPE; // clear the Nocat Queue descriptors & counters - portMemSet(&pRcDB->nocatJournalDescriptor, 0x00, NV_SIZEOF32(pRcDB->nocatJournalDescriptor)); - portMemSet(pRcDB->nocatJournalDescriptor.lastRecordId, 0xff, NV_SIZEOF32(pRcDB->nocatJournalDescriptor.lastRecordId)); + portMemSet(&pRcDB->nocatJournalDescriptor, 0x00, sizeof(pRcDB->nocatJournalDescriptor)); + portMemSet(pRcDB->nocatJournalDescriptor.lastRecordId, 0xff, sizeof(pRcDB->nocatJournalDescriptor.lastRecordId)); pRcDB->nocatJournalDescriptor.nocatLastRecordType = NV2080_NOCAT_JOURNAL_REC_TYPE_UNKNOWN; pRcDB->nocatJournalDescriptor.cacheFreshnessPeriodticks = NOCAT_CACHE_FRESHNESS_PERIOD_MS; pRcDB->nocatJournalDescriptor.cacheFreshnessPeriodticks *= osGetTimestampFreq(); @@ -529,7 +530,40 @@ // Populate stateMask with flags that represent the power state and other useful things. static NvU64 _getCommonJournalStateMask(OBJGPU *pGpu) { - return 0; + NvU64 stateMask = REF_NUM(NV_RM_JOURNAL_STATE_MASK_GC6_STATE, + pGpu->gc6State.currentState); + + if (!gpuIsGpuFullPower(pGpu)) + stateMask |= NV_RM_JOURNAL_STATE_MASK_IS_NOT_FULL_POWER; + + if (!pGpu->getProperty(pGpu, PDB_PROP_GPU_IS_CONNECTED)) + stateMask |= NV_RM_JOURNAL_STATE_MASK_IS_NOT_CONNECTED; + + if (pGpu->getProperty(pGpu, PDB_PROP_GPU_IN_STANDBY)) + stateMask |= NV_RM_JOURNAL_STATE_MASK_IS_IN_STANDBY; + + if (pGpu->getProperty(pGpu, PDB_PROP_GPU_IN_HIBERNATE)) + stateMask |= NV_RM_JOURNAL_STATE_MASK_IS_IN_HIBERNATE; + + if (pGpu->getProperty(pGpu, PDB_PROP_GPU_IN_PM_CODEPATH)) + stateMask |= NV_RM_JOURNAL_STATE_MASK_IS_IN_PM_CODEPATH; + + if (pGpu->getProperty(pGpu, PDB_PROP_GPU_IN_GC6_RESET)) + stateMask |= NV_RM_JOURNAL_STATE_MASK_IS_IN_GC6_RESET; + + if (pGpu->getProperty(pGpu, PDB_PROP_GPU_IN_FULLCHIP_RESET)) + stateMask |= NV_RM_JOURNAL_STATE_MASK_IS_IN_FULLCHIP_RESET; + + if (pGpu->getProperty(pGpu, PDB_PROP_GPU_IN_SECONDARY_BUS_RESET)) + stateMask |= NV_RM_JOURNAL_STATE_MASK_IS_IN_SEC_BUS_RESET; + + if (pGpu->getProperty(pGpu, PDB_PROP_GPU_IN_TIMEOUT_RECOVERY)) + stateMask |= NV_RM_JOURNAL_STATE_MASK_IS_IN_TIMEOUT_RECOVERY; + + if (pGpu->getProperty(pGpu, PDB_PROP_GPU_IS_LOST)) + stateMask |= NV_RM_JOURNAL_STATE_MASK_IS_LOST; + + return stateMask; } // Fill in the common portion of the journal structure. @@ -644,7 +678,7 @@ for (i = 0; i < pRingBuffer->numEntries; ++i) { // get a pointer to the record from the buffer. - pCommon = (RmRCCommonJournal_RECORD *)(((NvU8 *)pRingBuffer->pBuffer) + (_rcdbGetOcaRecordSizeWithHeader(pRcDB, RmRcDiagReport) * ((logicalStartIdx + i) % pRingBuffer->maxEntries))); + pCommon = (RmRCCommonJournal_RECORD *)(((NvU8 *)pRingBuffer->pBuffer) + (rcdbGetOcaRecordSizeWithHeader(pRcDB, RmRcDiagReport) * ((logicalStartIdx + i) % pRingBuffer->maxEntries))); pRecord = (RmRcDiag_RECORD*) &(pCommon[1]); // check to see if the record qualifies @@ -711,7 +745,7 @@ return status; } -NV_STATUS +RmRCCommonJournal_RECORD * rcdbAddRcDiagRec_IMPL ( OBJGPU *pGpu, @@ -719,6 +753,7 @@ RmRcDiag_RECORD *pRmDiagWrapBuffRec ) { + RmRCCommonJournal_RECORD *pCommon; NvU32 usec; // Create Records, then write it. @@ -733,11 +768,32 @@ } osGetCurrentTime(&(pRmDiagWrapBuffRec->timeStamp), &usec); - rcdbAddRecToRingBuffer(pGpu, pRcDB, RmRcDiagReport, - sizeof(RmRcDiag_RECORD), (NvU8 *) pRmDiagWrapBuffRec); + pCommon = rcdbAddRecToRingBuffer(pGpu, pRcDB, RmRcDiagReport, + sizeof(RmRcDiag_RECORD), (NvU8 *)pRmDiagWrapBuffRec); pRcDB->RcErrRptRecordsDropped |= pRcDB->RcErrRptNextIdx >= MAX_RCDB_RCDIAG_WRAP_BUFF; - return NV_OK; + return pCommon; +} + +RmRCCommonJournal_RECORD * +rcdbAddRcDiagRecFromGsp_IMPL +( + OBJGPU *pGpu, + Journal *pRcDB, + RmRCCommonJournal_RECORD *pCommonGsp, + RmRcDiag_RECORD *pRmDiagGsp +) +{ + RmRCCommonJournal_RECORD *pCommonCpu; + + pCommonCpu = rcdbAddRcDiagRec(pGpu, pRcDB, pRmDiagGsp); + if (pCommonCpu) + { + NV_ASSERT(pCommonCpu->GPUTag == pCommonGsp->GPUTag); + pCommonCpu->stateMask |= pCommonGsp->stateMask; + } + + return pCommonCpu; } NV_STATUS @@ -777,7 +833,7 @@ i %= pRingBuffer->maxEntries; // get a pointer to the record from the buffer. - pCommon = (RmRCCommonJournal_RECORD *)(((NvU8 *)pRingBuffer->pBuffer) + (_rcdbGetOcaRecordSizeWithHeader(pRcDB, RmRcDiagReport) * i)); + pCommon = (RmRCCommonJournal_RECORD *)(((NvU8 *)pRingBuffer->pBuffer) + (rcdbGetOcaRecordSizeWithHeader(pRcDB, RmRcDiagReport) * i)); pRecord = (RmRcDiag_RECORD*) &(pCommon[1]); // verify we have the record that was requested. @@ -807,6 +863,7 @@ exit: return status; } + NV_STATUS rcdbGetRcDiagRec_IMPL ( @@ -817,19 +874,23 @@ NvU32 processId ) { - NV_STATUS status = NV_ERR_INVALID_INDEX; + NV_STATUS status; if (ppRmDiagWrapBuffRec == NULL) { return NV_ERR_INVALID_ARGUMENT; } - // assume we will fail. + *ppRmDiagWrapBuffRec = NULL; if (portAtomicIncrementS32(&concurrentRingBufferAccess) == 1) { status = _rcdbInternalGetRcDiagRec(pRcDB, reqIdx, ppRmDiagWrapBuffRec, owner, processId); } + else + { + status = NV_ERR_BUSY_RETRY; + } portAtomicDecrementS32(&concurrentRingBufferAccess); return status; } @@ -1655,7 +1716,7 @@ if (pRec->count != 1) prbEncAddUInt32(pPrbEnc, JOURNAL_ASSERT_COUNT, pRec->count); - for (i = 0; i < NV_ARRAY_ELEMENTS32(pRec->callStack); i++) + for (i = 0; i < NV_ARRAY_ELEMENTS(pRec->callStack); i++) { if (pRec->callStack[i] == 0) break; @@ -1823,7 +1884,7 @@ NvU32 recordSize; NvU32 i; - recordSize = _rcdbGetOcaRecordSizeWithHeader(pRcDB, pRingBuffer->entryType); + recordSize = rcdbGetOcaRecordSizeWithHeader(pRcDB, pRingBuffer->entryType); // // Order does not matter here because the record will be inserted into the @@ -1855,7 +1916,7 @@ NvU32 recSize = pCurrentBuffer->bufferSize; NV_ASSERT(pCurrentBuffer->maxEntries * - _rcdbGetOcaRecordSizeWithHeader(pRcDB, pCurrentBuffer->entryType) == + rcdbGetOcaRecordSizeWithHeader(pRcDB, pCurrentBuffer->entryType) == pCurrentBuffer->bufferSize); if (recSize > 0) @@ -2301,7 +2362,7 @@ // Add assert to NvLog. But skip when nvLog asserts to avoid stack overflow. if (portAtomicIncrementS32(&nvLogRecursion) == 1) { - NV_PRINTF(LEVEL_ERROR, "Breakpoint at 0x%llx.\n", ip); + NV_PRINTF(LEVEL_NOTICE, "Breakpoint at 0x%llx.\n", ip); } portAtomicDecrementS32(&nvLogRecursion); @@ -2439,7 +2500,7 @@ rcdbFindRingBufferForType(pRcDB, type, &pRingBuffer); - entrySize = _rcdbGetOcaRecordSizeWithHeader(pRcDB, type); + entrySize = rcdbGetOcaRecordSizeWithHeader(pRcDB, type); if (entrySize == 0) { NV_ASSERT(entrySize != 0); @@ -2612,7 +2673,7 @@ ** it is assumed the caller has successfully acquired the concurrentRingBufferAccess lock. ** failure to do so can result in concurrency issues. */ -RmRCCommonJournal_RECORD* +RmRCCommonJournal_RECORD * _rcdbAllocRecFromRingBuffer ( OBJGPU *pGpu, @@ -2641,10 +2702,10 @@ newItemIndex = (pRingBuffer->numEntries + pRingBuffer->headIndex) % pRingBuffer->maxEntries; // prepend the rmJournalCommon record to record. - pCommon = (RmRCCommonJournal_RECORD*)(pRingBuffer->pBuffer + (_rcdbGetOcaRecordSizeWithHeader(pRcDB, type) * newItemIndex)); + pCommon = (RmRCCommonJournal_RECORD*)(pRingBuffer->pBuffer + (rcdbGetOcaRecordSizeWithHeader(pRcDB, type) * newItemIndex)); pCommon->Header.cRecordGroup = RmGroup; pCommon->Header.cRecordType = type; - pCommon->Header.wRecordSize = (NvU16)_rcdbGetOcaRecordSizeWithHeader(pRcDB, type); + pCommon->Header.wRecordSize = (NvU16)rcdbGetOcaRecordSizeWithHeader(pRcDB, type); rcdbSetCommonJournalRecord(pGpu, pCommon); // Increment the number of entries or advance the head index. @@ -2676,7 +2737,7 @@ ** ** notes: */ -void +RmRCCommonJournal_RECORD * rcdbAddRecToRingBuffer_IMPL ( OBJGPU *pGpu, @@ -2686,10 +2747,9 @@ NvU8 *pRecord ) { - RmRCCommonJournal_RECORD - *pCommon; + RmRCCommonJournal_RECORD *pCommon = NULL; - NV_ASSERT(recordSize == rcdbGetOcaRecordSize(pRcDB, type)); + NV_ASSERT(recordSize == _rcdbGetOcaRecordSize(pRcDB, type)); if (portAtomicIncrementS32(&concurrentRingBufferAccess) == 1) { @@ -2701,10 +2761,11 @@ } } portAtomicDecrementS32(&concurrentRingBufferAccess); + + return pCommon; } -// Non-hal function to return the sizes of records that are not chip dependent. -NvU32 rcdbGetOcaRecordSize_IMPL(Journal *pRcDB, RMCD_RECORD_TYPE type) +static NvU32 _rcdbGetOcaRecordSize(Journal *pRcDB, RMCD_RECORD_TYPE type) { switch(type) { @@ -2718,11 +2779,12 @@ return 0; } } -static NvU32 _rcdbGetOcaRecordSizeWithHeader(Journal *pRcDB, RMCD_RECORD_TYPE type) + +NvU32 rcdbGetOcaRecordSizeWithHeader_IMPL(Journal *pRcDB, RMCD_RECORD_TYPE type) { NvU32 recSz; - recSz = rcdbGetOcaRecordSize(pRcDB, type); + recSz = _rcdbGetOcaRecordSize(pRcDB, type); if (0 < recSz) { recSz += sizeof(RmRCCommonJournal_RECORD); @@ -2737,7 +2799,6 @@ return NV_ALIGN_UP(recSz, 8); } - NV_STATUS rcdbAddRmGpuDump ( @@ -3075,6 +3136,8 @@ pContextCache->subsystemId = (NvU16)(DRF_VAL(_PCI, _SUBID, _DEVICE, pGpu->idInfo.PCISubDeviceID)); pContextCache->revision = pGpu->idInfo.PCIRevisionID; pContextCache->type = pGpu->getProperty(pGpu, PDB_PROP_GPU_IS_MOBILE); + pContextCache->bMsHybrid = FLD_TEST_DRF(_JT_FUNC, _CAPS, _MSHYB_ENABLED, _TRUE, + pGpu->acpiMethodData.jtMethodData.jtCaps); portStringCopy((char *)pContextCache->vbiosProject, NV2080_NOCAT_JOURNAL_MAX_STR_LEN, NOCAT_UNKNOWN_STR, portStringLength(NOCAT_UNKNOWN_STR) + 1); @@ -3215,10 +3278,10 @@ if (pCommon != NULL) { // advance the pointer past the common header. - pNocatEntry = (RM_NOCAT_JOURNAL_ENTRY*)(((NvU8*)pCommon) + NV_SIZEOF32(RmRCCommonJournal_RECORD)); + pNocatEntry = (RM_NOCAT_JOURNAL_ENTRY*)(((NvU8*)pCommon) + sizeof(RmRCCommonJournal_RECORD)); // clear the record & assign an id. - portMemSet(pNocatEntry, 0, NV_SIZEOF32(*pNocatEntry)); + portMemSet(pNocatEntry, 0, sizeof(*pNocatEntry)); pNocatEntry->id = pDesc->nextRecordId++; pRcdb->nocatJournalDescriptor.nocatEventCounters[NV2080_NOCAT_JOURNAL_REPORT_ACTIVITY_ALLOCATED_IDX]++; } @@ -3341,10 +3404,10 @@ idx %= pRingBuffer->numEntries; // get a pointer to the common record & the record from the buffer. - pCommon = (RmRCCommonJournal_RECORD*)(((NvU8*)pRingBuffer->pBuffer) + (_rcdbGetOcaRecordSizeWithHeader(pRcdb, RmNocatReport) * idx)); + pCommon = (RmRCCommonJournal_RECORD*)(((NvU8*)pRingBuffer->pBuffer) + (rcdbGetOcaRecordSizeWithHeader(pRcdb, RmNocatReport) * idx)); // get a pointer to the data that follows the common header, that is the record data. - pNocatEntry = (RM_NOCAT_JOURNAL_ENTRY*)(((NvU8*)pCommon) + NV_SIZEOF32(RmRCCommonJournal_RECORD)); + pNocatEntry = (RM_NOCAT_JOURNAL_ENTRY*)(((NvU8*)pCommon) + sizeof(RmRCCommonJournal_RECORD)); // pass the record along if (ppReturnedCommon != NULL) @@ -3455,7 +3518,7 @@ pRcdb->nocatJournalDescriptor.nocatEventCounters[NV2080_NOCAT_JOURNAL_REPORT_ACTIVITY_BAD_PARAM_IDX]++; return NV_ERR_INVALID_ARGUMENT; } - portMemSet(pReturnedNocatEntry, 0, NV_SIZEOF32(*pReturnedNocatEntry)); + portMemSet(pReturnedNocatEntry, 0, sizeof(*pReturnedNocatEntry)); if (portAtomicIncrementS32(&concurrentRingBufferAccess) == 1) { @@ -3835,7 +3898,7 @@ diagBufferLen = NV_ARRAY_ELEMENTS(pNocatEntry->nocatJournalEntry.diagBuffer); } portMemCopy(pNocatEntry->nocatJournalEntry.diagBuffer, - NV_SIZEOF32(pNocatEntry->nocatJournalEntry.diagBuffer), + sizeof(pNocatEntry->nocatJournalEntry.diagBuffer), pNewEntry->pDiagBuffer, diagBufferLen); } pNocatEntry->nocatJournalEntry.diagBufferLen = diagBufferLen; @@ -3849,7 +3912,7 @@ _rcdbSetTdrReason(pRcdb, pNewEntry->tdrReason, (char*)pNocatEntry->nocatJournalEntry.tdrReason, - NV_SIZEOF32(pNocatEntry->nocatJournalEntry.tdrReason)); + sizeof(pNocatEntry->nocatJournalEntry.tdrReason)); } else { @@ -4093,7 +4156,7 @@ // put the line number in the upper 32 bits. newEntry.errorCode |= ((NvU64)pAssertRec->lineNum) << 32; - for (idx = 0; idx < NV_ARRAY_ELEMENTS32(pAssertRec->callStack); idx++) + for (idx = 0; idx < NV_ARRAY_ELEMENTS(pAssertRec->callStack); idx++) { diagBuffer.callStack[idx] = (NvU32)((pAssertRec->callStack[idx] - pRcdb->nocatJournalDescriptor.loadAddress) @@ -4105,14 +4168,14 @@ // setup the pointer to our diag buffer & its length newEntry.pDiagBuffer = (NvU8 *)&diagBuffer; - newEntry.diagBufferLen = NV_SIZEOF32(diagBuffer); + newEntry.diagBufferLen = sizeof(diagBuffer); // is the last thing we logged an assert, & is this the same assert? if ((pRcdb->nocatJournalDescriptor.lastRecordId[NV2080_NOCAT_JOURNAL_REC_TYPE_ASSERT] == pRcdb->nocatJournalDescriptor.lastRecordId[NV2080_NOCAT_JOURNAL_REC_TYPE_ANY]) && (0 == portMemCmp(&pRcdb->nocatJournalDescriptor.lastAssertData, diagBuffer.callStack, // same stack - NV_SIZEOF32(diagBuffer.callStack)))) + sizeof(diagBuffer.callStack)))) { // it is the same as the last assert we logged. so don't log it again. // but see if we can increment the counter in an unreported assert. @@ -4145,8 +4208,8 @@ // we are logging this assert, save off the stack so we can use it to // compare against future asserts. portMemCopy(&pRcdb->nocatJournalDescriptor.lastAssertData, - NV_SIZEOF32(pRcdb->nocatJournalDescriptor.lastAssertData), - &diagBuffer, NV_SIZEOF32(diagBuffer)); + sizeof(pRcdb->nocatJournalDescriptor.lastAssertData), + &diagBuffer, sizeof(diagBuffer)); rcdbNocatInsertNocatError(pGpu, &newEntry); } @@ -4220,7 +4283,7 @@ // there is, set the reason. _rcdbSetTdrReason(pRcdb, pReasonData->reasonCode, (char *)pNocatEntry->nocatJournalEntry.tdrReason, - NV_SIZEOF32(pNocatEntry->nocatJournalEntry.tdrReason)); + sizeof(pNocatEntry->nocatJournalEntry.tdrReason)); pRcdb->nocatJournalDescriptor.nocatEventCounters[NV2080_NOCAT_JOURNAL_REPORT_ACTIVITY_UPDATED_IDX]++; } } diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/kernel/diagnostics/nvlog_printf.c nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/kernel/diagnostics/nvlog_printf.c --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/kernel/diagnostics/nvlog_printf.c 2023-10-25 20:20:51.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/kernel/diagnostics/nvlog_printf.c 2024-03-05 22:13:13.000000000 +0000 @@ -1283,7 +1283,7 @@ // RmMsgPrefix - Add the RmMsg prefix to the passed in string, returning // the length of the formatted string. // -// Format: "NVRM file linenum function timestamp: " +// Format: "NVRM: file linenum function timestamp: " // NvU32 RmMsgPrefix @@ -1306,7 +1306,8 @@ { portStringCopy(str + len, totalLen - len, NV_PRINTF_PREFIX, sizeof(NV_PRINTF_PREFIX)); len += sizeof(NV_PRINTF_PREFIX) - 1; - space = " "; + portStringCopy(str + len, totalLen - len, NV_PRINTF_PREFIX_SEPARATOR, sizeof(NV_PRINTF_PREFIX_SEPARATOR)); + len += sizeof(NV_PRINTF_PREFIX_SEPARATOR) - 1; } if (prefix & NVRM_MSG_PREFIX_FILE) diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/kernel/disp/disp_sw.c nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/kernel/disp/disp_sw.c --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/kernel/disp/disp_sw.c 2023-10-25 20:20:51.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/kernel/disp/disp_sw.c 2024-03-05 22:13:13.000000000 +0000 @@ -66,7 +66,7 @@ if (!pKernelDisplay) { - NV_PRINTF(LEVEL_ERROR, "Display is not enabled, can't create class\n"); + NV_PRINTF(LEVEL_INFO, "Display is not enabled, can't create class\n"); return (NV_ERR_INVALID_ARGUMENT); } @@ -128,13 +128,13 @@ NV_STATUS dispswReleaseSemaphoreAndNotifierFill ( - OBJGPU *pGpu, + OBJGPU *pGpu, NvU64 gpuVA, NvU32 vaSpace, NvU32 releasevalue, NvU32 flags, NvU32 completionStatus, - NvHandle hClient, + RsClient *pClient, NvHandle hEvent ) { @@ -144,7 +144,7 @@ if (flags & F_SEMAPHORE_ADDR_VALID) { - bFound = CliGetDmaMappingInfo(hClient, + bFound = CliGetDmaMappingInfo(pClient, hEvent, vaSpace, gpuVA, @@ -153,10 +153,10 @@ if (!bFound) return NV_ERR_INVALID_ADDRESS; } - else if (flags & F_SEMAPHORE_RELEASE) + else if (flags & F_SEMAPHORE_RELEASE) { status = semaphoreFillGPUVA(pGpu, - hClient, + pClient, vaSpace, gpuVA, releasevalue, @@ -164,10 +164,10 @@ NV_TRUE); return status; } - else if (flags & F_NOTIFIER_FILL) + else if (flags & F_NOTIFIER_FILL) { status = notifyFillNotifierGPUVA(pGpu, - hClient, + pClient, vaSpace, gpuVA, releasevalue, /* Info32 */ diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/kernel/gpu/arch/ada/kern_gpu_ad102.c nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/kernel/gpu/arch/ada/kern_gpu_ad102.c --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/kernel/gpu/arch/ada/kern_gpu_ad102.c 2023-10-25 20:20:51.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/kernel/gpu/arch/ada/kern_gpu_ad102.c 2024-03-05 22:13:14.000000000 +0000 @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 2021-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2021-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -29,6 +29,7 @@ #include "core/core.h" #include "gpu/gpu.h" +#include "gpu/gpu_child_class_defs.h" #include "gpu/eng_desc.h" // @@ -46,79 +47,39 @@ static const GPUCHILDPRESENT gpuChildrenPresent_AD102[] = { - {classId(OBJSWENG), 1}, - {classId(OBJUVM), 1}, - {classId(OBJACR), 1}, - {classId(OBJBIF), 1}, - {classId(KernelBif), 1}, - {classId(OBJNNE), 1}, - {classId(OBJBSP), 4}, - {classId(OBJBUS), 1}, - {classId(KernelBus), 1}, - {classId(OBJCE), 5}, - {classId(KernelCE), 5}, - {classId(OBJCIPHER), 1}, - {classId(ClockManager), 1}, - {classId(OBJDISP), 1}, - {classId(KernelDisplay), 1}, - {classId(VirtMemAllocator), 1}, - {classId(OBJDPAUX), 1}, - {classId(Fan), 1}, - {classId(OBJHSHUBMANAGER), 1}, - {classId(Hshub), 2 }, - {classId(MemorySystem), 1}, - {classId(KernelMemorySystem), 1}, - {classId(MemoryManager), 1}, - {classId(OBJFBFLCN), 1}, - {classId(KernelFifo), 1 }, - {classId(OBJFIFO), 1}, - {classId(OBJGMMU), 1}, - {classId(KernelGmmu), 1}, - {classId(OBJGPULOG), 1}, - {classId(OBJGPUMON), 1}, - {classId(GraphicsManager), 1}, - {classId(MIGManager), 1}, - {classId(KernelMIGManager), 1}, - {classId(KernelGraphicsManager), 1}, - {classId(Graphics), 1}, - {classId(KernelGraphics), 1}, - {classId(OBJHDACODEC), 1}, - {classId(OBJHWPM), 1}, - {classId(OBJINFOROM), 1}, - {classId(Intr), 1}, - {classId(Lpwr ), 1}, - {classId(OBJLSFM), 1}, - {classId(OBJMC), 1}, - {classId(KernelMc), 1}, - {classId(PrivRing), 1}, - {classId(SwIntr), 1}, - {classId(OBJNVJPG), 4}, - {classId(OBJMSENC), 3}, - {classId(NvDebugDump), 1}, - {classId(KernelNvlink), 1}, - {classId(Nvlink), 1}, - {classId(Perf), 1}, - {classId(KernelPerf), 1}, - {classId(Pmgr), 1}, - {classId(Pmu), 1}, - {classId(KernelPmu), 1}, - {classId(OBJSEC2), 1}, - {classId(Gsp), 1}, - {classId(Therm), 1}, - {classId(OBJTMR), 1}, - {classId(OBJVOLT), 1}, - {classId(OBJGRIDDISPLAYLESS), 1}, - {classId(OBJFAS), 1}, - {classId(OBJVMMU), 1}, - {classId(OBJOFA), 1 }, - {classId(KernelSec2), 1}, - {classId(KernelGsp), 1}, + GPU_CHILD_PRESENT(OBJTMR, 1), + GPU_CHILD_PRESENT(KernelMIGManager, 1), + GPU_CHILD_PRESENT(KernelGraphicsManager, 1), + GPU_CHILD_PRESENT(KernelRc, 1), + GPU_CHILD_PRESENT(Intr, 1), + GPU_CHILD_PRESENT(NvDebugDump, 1), + GPU_CHILD_PRESENT(OBJGPUMON, 1), + GPU_CHILD_PRESENT(OBJSWENG, 1), + GPU_CHILD_PRESENT(OBJUVM, 1), + GPU_CHILD_PRESENT(KernelBif, 1), + GPU_CHILD_PRESENT(KernelBus, 1), + GPU_CHILD_PRESENT(KernelCE, 5), + GPU_CHILD_PRESENT(KernelDisplay, 1), + GPU_CHILD_PRESENT(VirtMemAllocator, 1), + GPU_CHILD_PRESENT(KernelMemorySystem, 1), + GPU_CHILD_PRESENT(MemoryManager, 1), + GPU_CHILD_PRESENT(KernelFifo, 1), + GPU_CHILD_PRESENT(KernelGmmu, 1), + GPU_CHILD_PRESENT(KernelGraphics, 1), + GPU_CHILD_PRESENT(KernelMc, 1), + GPU_CHILD_PRESENT(SwIntr, 1), + GPU_CHILD_PRESENT(KernelNvlink, 1), + GPU_CHILD_PRESENT(KernelPerf, 1), + GPU_CHILD_PRESENT(KernelPmu, 1), + GPU_CHILD_PRESENT(KernelSec2, 1), + GPU_CHILD_PRESENT(KernelGsp, 1), + GPU_CHILD_PRESENT(ConfidentialCompute, 1), }; const GPUCHILDPRESENT * gpuGetChildrenPresent_AD102(OBJGPU *pGpu, NvU32 *pNumEntries) { - *pNumEntries = NV_ARRAY_ELEMENTS32(gpuChildrenPresent_AD102); + *pNumEntries = NV_ARRAY_ELEMENTS(gpuChildrenPresent_AD102); return gpuChildrenPresent_AD102; } diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/kernel/gpu/arch/ampere/kern_gpu_ga100.c nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/kernel/gpu/arch/ampere/kern_gpu_ga100.c --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/kernel/gpu/arch/ampere/kern_gpu_ga100.c 2023-10-25 20:20:51.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/kernel/gpu/arch/ampere/kern_gpu_ga100.c 2024-03-05 22:13:14.000000000 +0000 @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 2021-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2021-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -22,11 +22,13 @@ */ #include "gpu/gpu.h" +#include "gpu/gpu_child_class_defs.h" #include "kernel/gpu/intr/intr.h" #include "gpu/mem_mgr/mem_mgr.h" #include "published/ampere/ga100/dev_fb.h" #include "published/ampere/ga100/dev_vm.h" #include "published/ampere/ga100/dev_fuse.h" +#include "virtualization/hypervisor/hypervisor.h" /*! * @brief Read fuse for display supported status. @@ -98,7 +100,7 @@ NvU64 gpuGetFlaVasSize_GA100 ( - POBJGPU pGpu, + OBJGPU *pGpu, NvBool bNvswitchVirtualization ) { @@ -115,6 +117,25 @@ } } +/*! + * @brief Is ctx buffer allocation in PMA supported + */ +NvBool +gpuIsCtxBufAllocInPmaSupported_GA100 +( + OBJGPU *pGpu +) +{ + // + // This is supported by default on baremetal RM. + // This has no impact in guest-RM since ctxBufPools are disabled on guest. + // We leave this disabled on host-RM. TODO: Bug 4066846 + // + if (!hypervisorIsVgxHyper()) + return NV_TRUE; + return NV_FALSE; +} + // // List of GPU children that present for the chip. List entries contain$ // {CLASS-ID, # of instances} pairs, e.g.: {CE, 2} is 2 instance of OBJCE. This$ @@ -130,77 +151,39 @@ static const GPUCHILDPRESENT gpuChildrenPresent_GA100[] = { - { classId(OBJSWENG), 1 }, - { classId(OBJUVM), 1 }, - { classId(OBJACR), 1 }, - { classId(OBJBIF), 1 }, - { classId(KernelBif), 1 }, - { classId(OBJBSP), 5 }, - { classId(OBJBUS), 1 }, - { classId(KernelBus), 1 }, - { classId(OBJCE), 10 }, - { classId(KernelCE), 10 }, - { classId(OBJCIPHER), 1 }, - { classId(ClockManager), 1 }, - { classId(OBJDISP), 1 }, - { classId(KernelDisplay), 1 }, - { classId(VirtMemAllocator), 1 }, - { classId(OBJDPAUX), 1 }, - { classId(Fan), 1 }, - { classId(OBJHSHUBMANAGER), 1 }, - { classId(Hshub), 2 }, - { classId(MemorySystem), 1 }, - { classId(KernelMemorySystem), 1 }, - { classId(MemoryManager), 1 }, - { classId(OBJFBFLCN), 1 }, - { classId(KernelFifo), 1 }, - { classId(OBJFIFO), 1 }, - { classId(OBJGMMU), 1 }, - { classId(KernelGmmu), 1}, - { classId(OBJGPULOG), 1 }, - { classId(OBJGPUMON), 1 }, - { classId(GraphicsManager), 1 }, - { classId(MIGManager), 1}, - { classId(KernelMIGManager), 1 }, - { classId(KernelGraphicsManager), 1 }, - { classId(Graphics), 8 }, - { classId(KernelGraphics), 8 }, - { classId(OBJHDACODEC), 1 }, - { classId(OBJHWPM), 1 }, - { classId(OBJINFOROM), 1 }, - { classId(Intr), 1 }, - { classId(Lpwr ), 1 }, - { classId(OBJLSFM), 1 }, - { classId(OBJMC), 1 }, - { classId(KernelMc), 1 }, - { classId(PrivRing), 1 }, - { classId(SwIntr), 1 }, - { classId(OBJNVJPG), 1 }, - { classId(NvDebugDump), 1 }, - { classId(KernelNvlink), 1 }, - { classId(Nvlink), 1 }, - { classId(Perf), 1 }, - { classId(KernelPerf), 1 }, - { classId(Pmgr), 1 }, - { classId(Pmu), 1 }, - { classId(KernelPmu), 1 }, - { classId(OBJSEC2), 1 }, - { classId(Gsp), 1 }, - { classId(Therm), 1 }, - { classId(OBJTMR), 1 }, - { classId(OBJVOLT), 1 }, - { classId(OBJGRIDDISPLAYLESS), 1 }, - { classId(OBJFAS), 1 }, - { classId(OBJVMMU), 1 }, - { classId(OBJOFA), 1 }, - { classId(KernelSec2), 1 }, - { classId(KernelGsp), 1 }, + GPU_CHILD_PRESENT(OBJTMR, 1), + GPU_CHILD_PRESENT(KernelMIGManager, 1), + GPU_CHILD_PRESENT(KernelGraphicsManager, 1), + GPU_CHILD_PRESENT(KernelRc, 1), + GPU_CHILD_PRESENT(Intr, 1), + GPU_CHILD_PRESENT(NvDebugDump, 1), + GPU_CHILD_PRESENT(OBJGPUMON, 1), + GPU_CHILD_PRESENT(OBJSWENG, 1), + GPU_CHILD_PRESENT(OBJUVM, 1), + GPU_CHILD_PRESENT(KernelBif, 1), + GPU_CHILD_PRESENT(KernelBus, 1), + GPU_CHILD_PRESENT(KernelCE, 10), + GPU_CHILD_PRESENT(KernelDisplay, 1), + GPU_CHILD_PRESENT(VirtMemAllocator, 1), + GPU_CHILD_PRESENT(KernelMemorySystem, 1), + GPU_CHILD_PRESENT(MemoryManager, 1), + GPU_CHILD_PRESENT(KernelFifo, 1), + GPU_CHILD_PRESENT(KernelGmmu, 1), + GPU_CHILD_PRESENT(KernelGraphics, 8), + GPU_CHILD_PRESENT(KernelMc, 1), + GPU_CHILD_PRESENT(SwIntr, 1), + GPU_CHILD_PRESENT(KernelNvlink, 1), + GPU_CHILD_PRESENT(KernelPerf, 1), + GPU_CHILD_PRESENT(KernelPmu, 1), + GPU_CHILD_PRESENT(KernelSec2, 1), + GPU_CHILD_PRESENT(KernelGsp, 1), + GPU_CHILD_PRESENT(ConfidentialCompute, 1), }; const GPUCHILDPRESENT * gpuGetChildrenPresent_GA100(OBJGPU *pGpu, NvU32 *pNumEntries) { - *pNumEntries = NV_ARRAY_ELEMENTS32(gpuChildrenPresent_GA100); + *pNumEntries = NV_ARRAY_ELEMENTS(gpuChildrenPresent_GA100); return gpuChildrenPresent_GA100; } @@ -218,78 +201,47 @@ // static const GPUCHILDPRESENT gpuChildrenPresent_GA102[] = { - {classId(OBJSWENG), 1}, - {classId(OBJUVM), 1}, - {classId(OBJACR), 1}, - {classId(OBJBIF), 1}, - {classId(KernelBif), 1}, - {classId(OBJNNE), 1}, - {classId(OBJBSP), 2}, - {classId(OBJBUS), 1}, - {classId(KernelBus), 1}, - {classId(OBJCE), 5}, - {classId(KernelCE), 5}, - {classId(OBJCIPHER), 1}, - {classId(ClockManager), 1}, - {classId(OBJDISP), 1}, - {classId(KernelDisplay), 1}, - {classId(VirtMemAllocator), 1}, - {classId(OBJDPAUX), 1}, - {classId(Fan), 1}, - {classId(OBJHSHUBMANAGER), 1 }, - {classId(Hshub), 2 }, - {classId(MemorySystem), 1}, - {classId(KernelMemorySystem), 1}, - {classId(MemoryManager), 1}, - {classId(OBJFBFLCN), 1}, - {classId(KernelFifo), 1 }, - {classId(OBJFIFO), 1}, - {classId(OBJGMMU), 1}, - {classId(KernelGmmu), 1}, - {classId(OBJGPULOG), 1}, - {classId(OBJGPUMON), 1}, - {classId(GraphicsManager), 1 }, - {classId(MIGManager), 1}, - {classId(KernelMIGManager), 1}, - {classId(KernelGraphicsManager), 1}, - {classId(Graphics), 1}, - {classId(KernelGraphics), 1}, - {classId(OBJHDACODEC), 1}, - {classId(OBJHWPM), 1}, - {classId(OBJINFOROM), 1}, - {classId(Intr), 1}, - {classId(Lpwr ), 1}, - {classId(OBJLSFM), 1}, - {classId(OBJMC), 1}, - {classId(KernelMc), 1}, - {classId(PrivRing), 1}, - {classId(SwIntr), 1}, - {classId(OBJMSENC), 1}, - {classId(NvDebugDump), 1}, - {classId(KernelNvlink), 1}, - {classId(Nvlink), 1}, - {classId(Perf), 1}, - {classId(KernelPerf), 1 }, - {classId(Pmgr), 1}, - {classId(Pmu), 1}, - {classId(KernelPmu), 1}, - {classId(OBJSEC2), 1}, - {classId(Gsp), 1}, - {classId(Therm), 1}, - {classId(OBJTMR), 1}, - {classId(OBJVOLT), 1}, - {classId(OBJGRIDDISPLAYLESS), 1}, - {classId(OBJFAS), 1}, - {classId(OBJVMMU), 1}, - {classId(OBJOFA), 1 }, - {classId(KernelSec2), 1}, - {classId(KernelGsp), 1}, + GPU_CHILD_PRESENT(OBJTMR, 1), + GPU_CHILD_PRESENT(KernelMIGManager, 1), + GPU_CHILD_PRESENT(KernelGraphicsManager, 1), + GPU_CHILD_PRESENT(KernelRc, 1), + GPU_CHILD_PRESENT(Intr, 1), + GPU_CHILD_PRESENT(NvDebugDump, 1), + GPU_CHILD_PRESENT(OBJGPUMON, 1), + GPU_CHILD_PRESENT(OBJSWENG, 1), + GPU_CHILD_PRESENT(OBJUVM, 1), + GPU_CHILD_PRESENT(KernelBif, 1), + GPU_CHILD_PRESENT(KernelBus, 1), + GPU_CHILD_PRESENT(KernelCE, 5), + GPU_CHILD_PRESENT(KernelDisplay, 1), + GPU_CHILD_PRESENT(VirtMemAllocator, 1), + GPU_CHILD_PRESENT(KernelMemorySystem, 1), + GPU_CHILD_PRESENT(MemoryManager, 1), + GPU_CHILD_PRESENT(KernelFifo, 1), + GPU_CHILD_PRESENT(KernelGmmu, 1), + GPU_CHILD_PRESENT(KernelGraphics, 1), + GPU_CHILD_PRESENT(KernelMc, 1), + GPU_CHILD_PRESENT(SwIntr, 1), + GPU_CHILD_PRESENT(KernelNvlink, 1), + GPU_CHILD_PRESENT(KernelPerf, 1), + GPU_CHILD_PRESENT(KernelPmu, 1), + GPU_CHILD_PRESENT(KernelSec2, 1), + GPU_CHILD_PRESENT(KernelGsp, 1), + GPU_CHILD_PRESENT(ConfidentialCompute, 1), }; const GPUCHILDPRESENT * gpuGetChildrenPresent_GA102(OBJGPU *pGpu, NvU32 *pNumEntries) { - *pNumEntries = NV_ARRAY_ELEMENTS32(gpuChildrenPresent_GA102); + *pNumEntries = NV_ARRAY_ELEMENTS(gpuChildrenPresent_GA102); return gpuChildrenPresent_GA102; } +NvBool +gpuCheckIfFbhubPoisonIntrPending_GA100 +( + OBJGPU *pGpu +) +{ + return intrIsVectorPending_HAL(pGpu, GPU_GET_INTR(pGpu), NV_PFB_FBHUB_POISON_INTR_VECTOR_HW_INIT, NULL); +} diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/kernel/gpu/arch/hopper/kern_gpu_gh100.c nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/kernel/gpu/arch/hopper/kern_gpu_gh100.c --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/kernel/gpu/arch/hopper/kern_gpu_gh100.c 2023-10-25 20:20:52.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/kernel/gpu/arch/hopper/kern_gpu_gh100.c 2024-03-05 22:13:14.000000000 +0000 @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 2021-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2021-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -22,16 +22,20 @@ */ #include "gpu/gpu.h" +#include "gpu/gpu_child_class_defs.h" #include "os/os.h" #include "nverror.h" #include "published/hopper/gh100/hwproject.h" #include "published/hopper/gh100/dev_gc6_island.h" +#include "published/hopper/gh100/dev_gc6_island_addendum.h" #include "published/hopper/gh100/dev_pmc.h" #include "published/hopper/gh100/dev_xtl_ep_pcfg_gpu.h" #include "published/hopper/gh100/pri_nv_xal_ep.h" #include "published/hopper/gh100/dev_xtl_ep_pri.h" +#include "ctrl/ctrl2080/ctrl2080mc.h" + #include "gpu/gsp/gsp_static_config.h" /*! @@ -169,6 +173,15 @@ */ NvBool gpuIsAtsSupportedWithSmcMemPartitioning_GH100(OBJGPU *pGpu) { + // + // ATS is supported only on self-hosted Hopper. + // Also enable it for simulation platforms for fmodel/RTL verification + // with CPU model. + // + if (gpuIsSelfHosted(pGpu)) + { + return NV_TRUE; + } if (IS_SIMULATION(pGpu)) { @@ -380,79 +393,121 @@ static const GPUCHILDPRESENT gpuChildrenPresent_GH100[] = { - { classId(OBJSWENG), 1 }, - { classId(OBJUVM), 1 }, - { classId(OBJACR), 1 }, - { classId(OBJBIF), 1 }, - { classId(KernelBif), 1 }, - { classId(OBJBSP), 8 }, - { classId(OBJBUS), 1 }, - { classId(KernelBus), 1 }, - { classId(OBJCE), 10 }, - { classId(KernelCE), 10 }, - { classId(OBJCIPHER), 1 }, - { classId(ClockManager), 1 }, - { classId(OBJDISP), 1 }, - { classId(KernelDisplay), 1 }, - { classId(VirtMemAllocator), 1 }, - { classId(OBJDPAUX), 1 }, - { classId(Fan), 1 }, - { classId(OBJHSHUBMANAGER), 1 }, - { classId(Hshub), 5 }, - { classId(MemorySystem), 1 }, - { classId(KernelMemorySystem), 1 }, - { classId(MemoryManager), 1 }, - { classId(OBJFBFLCN), 1 }, - {classId(KernelFifo), 1}, - { classId(OBJFIFO), 1 }, - { classId(OBJGMMU), 1 }, - { classId(KernelGmmu), 1}, - { classId(OBJGPULOG), 1 }, - { classId(OBJGPUMON), 1 }, - { classId(GraphicsManager), 1 }, - { classId(MIGManager), 1 }, - { classId(KernelMIGManager), 1 }, - { classId(KernelGraphicsManager), 1 }, - { classId(Graphics), 8 }, - { classId(KernelGraphics), 8 }, - { classId(OBJHDACODEC), 1 }, - { classId(OBJHWPM), 1 }, - { classId(OBJINFOROM), 1 }, - { classId(Intr), 1 }, - { classId(Lpwr ), 1 }, - { classId(OBJLSFM), 1 }, - { classId(OBJMC), 1 }, - { classId(KernelMc), 1 }, - { classId(PrivRing), 1 }, - { classId(SwIntr), 1 }, - { classId(OBJNVJPG), 8 }, - { classId(NvDebugDump), 1 }, - { classId(KernelNvlink), 1 }, - { classId(Nvlink), 1 }, - { classId(Perf), 1 }, - { classId(KernelPerf), 1 }, - { classId(Pmgr), 1 }, - { classId(Pmu), 1 }, - { classId(KernelPmu), 1 }, - { classId(OBJSEC2), 1 }, - { classId(Gsp), 1 }, - { classId(OBJFSP), 1 }, - { classId(KernelFsp), 1 }, - { classId(Therm), 1 }, - { classId(OBJTMR), 1 }, - { classId(OBJVOLT), 1 }, - { classId(OBJGRIDDISPLAYLESS), 1 }, - { classId(OBJFAS), 1 }, - { classId(OBJVMMU), 1 }, - { classId(OBJOFA), 1 }, - { classId(KernelGsp), 1}, - { classId(KernelCcu), 1 }, + GPU_CHILD_PRESENT(OBJTMR, 1), + GPU_CHILD_PRESENT(KernelMIGManager, 1), + GPU_CHILD_PRESENT(KernelGraphicsManager, 1), + GPU_CHILD_PRESENT(KernelRc, 1), + GPU_CHILD_PRESENT(Intr, 1), + GPU_CHILD_PRESENT(NvDebugDump, 1), + GPU_CHILD_PRESENT(OBJGPUMON, 1), + GPU_CHILD_PRESENT(OBJSWENG, 1), + GPU_CHILD_PRESENT(OBJUVM, 1), + GPU_CHILD_PRESENT(KernelBif, 1), + GPU_CHILD_PRESENT(KernelBus, 1), + GPU_CHILD_PRESENT(KernelCE, 10), + GPU_CHILD_PRESENT(KernelDisplay, 1), + GPU_CHILD_PRESENT(VirtMemAllocator, 1), + GPU_CHILD_PRESENT(KernelMemorySystem, 1), + GPU_CHILD_PRESENT(MemoryManager, 1), + GPU_CHILD_PRESENT(KernelFifo, 1), + GPU_CHILD_PRESENT(KernelGmmu, 1), + GPU_CHILD_PRESENT(KernelGraphics, 8), + GPU_CHILD_PRESENT(KernelMc, 1), + GPU_CHILD_PRESENT(SwIntr, 1), + GPU_CHILD_PRESENT(KernelNvlink, 1), + GPU_CHILD_PRESENT(KernelPerf, 1), + GPU_CHILD_PRESENT(KernelPmu, 1), + GPU_CHILD_PRESENT(KernelFsp, 1), + GPU_CHILD_PRESENT(KernelGsp, 1), + GPU_CHILD_PRESENT(KernelSec2, 1), + GPU_CHILD_PRESENT(ConfidentialCompute, 1), + GPU_CHILD_PRESENT(KernelCcu, 1), }; const GPUCHILDPRESENT * gpuGetChildrenPresent_GH100(OBJGPU *pGpu, NvU32 *pNumEntries) { - *pNumEntries = NV_ARRAY_ELEMENTS32(gpuChildrenPresent_GH100); + *pNumEntries = NV_ARRAY_ELEMENTS(gpuChildrenPresent_GH100); return gpuChildrenPresent_GH100; } +/*! + * @brief Determine if GPU is configured in Self Hosted mode. + * In Hopper+, GPU can be configured to work in Self Hosted, + * Externally Hosted and Endpoint mode. + * + * @param[in] pGpu OBJGPU pointer + * + * @return void + */ +void +gpuDetermineSelfHostedMode_KERNEL_GH100 +( + OBJGPU *pGpu +) +{ + if (IS_GSP_CLIENT(pGpu)) + { + GspStaticConfigInfo *pGSCI = GPU_GET_GSP_STATIC_INFO(pGpu); + if (pGSCI->bSelfHostedMode) + { + pGpu->bIsSelfHosted = NV_TRUE; + NV_PRINTF(LEVEL_INFO, "SELF HOSTED mode detected after reading GSP static info.\n"); + } + } +} + +/*! + * @brief Determine if MIG can be supported. + * In self hosted hopper, MIG can be supported only from specific + * GH100 revisions. + * + * @param[in] pGpu OBJGPU pointer + * + * @return void + */ +void +gpuDetermineMIGSupport_GH100 +( + OBJGPU *pGpu +) +{ + if (gpuIsSelfHosted(pGpu) && + (gpuGetChipSubRev_HAL(pGpu) < NV2080_CTRL_MC_ARCH_INFO_SUBREVISION_R)) + { + NV_PRINTF(LEVEL_ERROR, "Disabling MIG Support. MIG can be supported on self hosted hopper " + "only from revision R onwards\n"); + pGpu->setProperty(pGpu, PDB_PROP_GPU_MIG_SUPPORTED, NV_FALSE); + } +} + +/*! + * Check if CC bit has been set in the scratch register + * + * @param[in] pGpu GPU object pointer + */ +NvBool +gpuIsCCEnabledInHw_GH100 +( + OBJGPU *pGpu +) +{ + NvU32 val = GPU_REG_RD32(pGpu, NV_PGC6_AON_SECURE_SCRATCH_GROUP_20_CC); + return FLD_TEST_DRF(_PGC6, _AON_SECURE_SCRATCH_GROUP_20_CC, _MODE_ENABLED, _TRUE, val); +} + +/*! + * Check if dev mode bit has been set in the scratch register + * + * @param[in] pGpu GPU object pointer + */ +NvBool +gpuIsDevModeEnabledInHw_GH100 +( + OBJGPU *pGpu +) +{ + NvU32 val = GPU_REG_RD32(pGpu, NV_PGC6_AON_SECURE_SCRATCH_GROUP_20_CC); + return FLD_TEST_DRF(_PGC6, _AON_SECURE_SCRATCH_GROUP_20_CC, _DEV_ENABLED, _TRUE, val); +} + diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/kernel/gpu/arch/maxwell/kern_gpu_gm107.c nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/kernel/gpu/arch/maxwell/kern_gpu_gm107.c --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/kernel/gpu/arch/maxwell/kern_gpu_gm107.c 2023-10-25 20:20:52.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/kernel/gpu/arch/maxwell/kern_gpu_gm107.c 2024-03-05 22:13:14.000000000 +0000 @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 2021-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2021-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -22,8 +22,10 @@ */ #include "gpu/gpu.h" +#include "gpu/gpu_child_class_defs.h" +#include "gpu_mgr/gpu_mgr_sli.h" #include "gpu/bif/kernel_bif.h" - +#include "jt.h" #include "published/maxwell/gm107/dev_bus.h" #include "published/maxwell/gm107/dev_nv_xve.h" #include "published/maxwell/gm107/dev_nv_xve1.h" @@ -375,9 +377,11 @@ static const GPUCHILDORDER gpuChildOrderList_GM200[] = { + {classId(ConfidentialCompute), GCO_ALL}, + {classId(Pxuc), GCO_ALL}, {classId(OBJBIF), GCO_ALL}, {classId(KernelBif), GCO_ALL}, - {classId(OBJNNE), GCO_ALL}, + {classId(Nne), GCO_ALL}, {classId(NvDebugDump), GCO_ALL}, {classId(ClockManager), GCO_ALL}, {classId(Pmgr), GCO_ALL}, @@ -469,7 +473,7 @@ const GPUCHILDORDER * gpuGetChildrenOrder_GM200(OBJGPU *pGpu, NvU32 *pNumEntries) { - *pNumEntries = NV_ARRAY_ELEMENTS32(gpuChildOrderList_GM200); + *pNumEntries = NV_ARRAY_ELEMENTS(gpuChildOrderList_GM200); return gpuChildOrderList_GM200; } @@ -487,68 +491,146 @@ // static const GPUCHILDPRESENT gpuChildrenPresent_GM200[] = { - {classId(OBJSWENG), 1}, - {classId(OBJACR), 1}, - {classId(OBJBIF), 1}, - {classId(KernelBif), 1}, - {classId(OBJBSP), 1}, - {classId(OBJBUS), 1}, - {classId(KernelBus), 1}, - {classId(OBJCE), 3}, - {classId(KernelCE), 3}, - {classId(OBJCIPHER), 1}, - {classId(ClockManager), 1}, - {classId(OBJDISP), 1}, - {classId(KernelDisplay), 1}, - {classId(VirtMemAllocator), 1}, - {classId(OBJDPAUX), 1}, - {classId(Fan), 1}, - {classId(OBJHSHUBMANAGER), 1}, - {classId(Hshub), 1}, - {classId(MemorySystem), 1}, - {classId(KernelMemorySystem), 1}, - {classId(MemoryManager), 1}, - {classId(KernelFifo), 1}, - {classId(OBJFIFO), 1}, - {classId(OBJGMMU), 1}, - {classId(KernelGmmu), 1}, - {classId(OBJGPULOG), 1}, - {classId(OBJGPUMON), 1}, - {classId(GraphicsManager), 1}, - {classId(MIGManager), 1}, - {classId(KernelMIGManager), 1}, - {classId(KernelGraphicsManager), 1}, - {classId(Graphics), 1}, - {classId(KernelGraphics), 1}, - {classId(OBJHDA), 1}, - {classId(OBJHDACODEC), 1}, - {classId(OBJHWPM), 1}, - {classId(OBJINFOROM), 1}, - {classId(Intr), 1}, - {classId(Lpwr ), 1}, - {classId(OBJLSFM), 1}, - {classId(OBJMC), 1}, - {classId(KernelMc), 1}, - {classId(PrivRing), 1}, - {classId(SwIntr), 1}, - {classId(OBJMSENC), 2}, - {classId(NvDebugDump), 1}, - {classId(Perf), 1}, - {classId(KernelPerf), 1}, - {classId(Pmgr), 1}, - {classId(Pmu), 1}, - {classId(KernelPmu), 1}, - {classId(OBJSEC2), 1}, - {classId(Therm), 1}, - {classId(OBJTMR), 1}, - {classId(OBJVOLT), 1}, - {classId(OBJGRIDDISPLAYLESS), 1}, + GPU_CHILD_PRESENT(OBJTMR, 1), + GPU_CHILD_PRESENT(KernelMIGManager, 1), + GPU_CHILD_PRESENT(KernelGraphicsManager, 1), + GPU_CHILD_PRESENT(KernelRc, 1), + GPU_CHILD_PRESENT(Intr, 1), + GPU_CHILD_PRESENT(NvDebugDump, 1), + GPU_CHILD_PRESENT(OBJGPUMON, 1), + GPU_CHILD_PRESENT(OBJSWENG, 1), + GPU_CHILD_PRESENT(KernelBif, 1), + GPU_CHILD_PRESENT(KernelBus, 1), + GPU_CHILD_PRESENT(KernelCE, 3), + GPU_CHILD_PRESENT(KernelDisplay, 1), + GPU_CHILD_PRESENT(VirtMemAllocator, 1), + GPU_CHILD_PRESENT(KernelMemorySystem, 1), + GPU_CHILD_PRESENT(MemoryManager, 1), + GPU_CHILD_PRESENT(KernelFifo, 1), + GPU_CHILD_PRESENT(KernelGmmu, 1), + GPU_CHILD_PRESENT(KernelGraphics, 1), + GPU_CHILD_PRESENT(KernelMc, 1), + GPU_CHILD_PRESENT(SwIntr, 1), + GPU_CHILD_PRESENT(KernelPerf, 1), + GPU_CHILD_PRESENT(KernelPmu, 1), }; const GPUCHILDPRESENT * gpuGetChildrenPresent_GM200(OBJGPU *pGpu, NvU32 *pNumEntries) { - *pNumEntries = NV_ARRAY_ELEMENTS32(gpuChildrenPresent_GM200); + *pNumEntries = NV_ARRAY_ELEMENTS(gpuChildrenPresent_GM200); return gpuChildrenPresent_GM200; } +/*! + * @brief checks for each type of bridge to deterimne what is available, + * then selects the SLI bridge to use. + * + * @param[In] gpuCount The number of GPUs to be checked for SLI links. + * @param[In] gpuMaskArg A mask of the GPUs that are to be tested for SLI links. + * @param[Out] pSliLinkOutputMask a mask of the GPUs that are attached to the type of + * SLI link that is being used. + * @param[Out] pSliLinkCircular a boolean indicating if teh SLI link is circular. + * @param[Out] pSliLinkEndsMask a mask indicating the endpoints of the SLI link, + * if there are any. +.*/ +void +gpuDetectSliLinkFromGpus_GK104 +( + OBJGPU *pGpu, + NvU32 gpuCount, + NvU32 gpuMaskArg, + NvU32 *pSliLinkOutputMask, + NvBool *pSliLinkCircular, + NvU32 *pSliLinkEndsMask, + NvU32 *pVidLinkCount +) +{ + NvU32 i; + NvU32 sliLinkOutputMask[SLI_MAX_BRIDGE_TYPES] = {0, 0}; + NvBool bSliLinkCircular[SLI_MAX_BRIDGE_TYPES] = {NV_FALSE, NV_FALSE}; + NvU32 sliLinkEndsMask[SLI_MAX_BRIDGE_TYPES] = {0, 0}; + NvU32 vidLinkCount[SLI_MAX_BRIDGE_TYPES] = {0, 0}; + OBJSYS *pSys = SYS_GET_INSTANCE(); + OBJGPUMGR *pGpuMgr = SYS_GET_GPUMGR(pSys); + OBJGPU *pGpuLoop; + OBJGPU *pGpuSaved; + NvU32 gpuMask; + // Array to store the link detection HAL flag of GpuDetectVidLinkFromGpus_HAL and GpuDetectNvlinkLinkFromGpus_HAL. + NvU32 linkHalImpl[SLI_MAX_BRIDGE_TYPES]; + NvBool bFoundBridge = NV_FALSE; + + // set the return values assuming we will not find an SLI link. + *pSliLinkOutputMask = 0; + *pSliLinkCircular = NV_FALSE; + *pSliLinkEndsMask = 0; + + pGpuMgr->gpuBridgeType = SLI_BT_VIDLINK; + + // + // Link detection HAL should have same HAL implementation as HAL flag. + // This checks for mismatched HAL implementation flag. + // + NV_ASSERT_OR_RETURN_VOID(gpuGetSliLinkDetectionHalFlag_HAL(pGpu) == GPU_LINK_DETECTION_HAL_GK104); + + i = 0; + gpuMask = gpuMaskArg; + pGpuLoop = gpumgrGetNextGpu(gpuMask, &i); + if (pGpuLoop != NULL) + { + pGpuSaved = pGpuLoop; + linkHalImpl[SLI_BT_NVLINK] = gpuGetNvlinkLinkDetectionHalFlag_HAL(pGpuLoop); + + } + else + { + return; + } + + // run thru the GPUs and see if they are all using the same HAL functions. + // if they are different, we can't use the function to check for a bridge + pGpuLoop = gpumgrGetNextGpu(gpuMask, &i); + while (NULL != pGpuLoop) + { + if (linkHalImpl[SLI_BT_NVLINK] != gpuGetNvlinkLinkDetectionHalFlag_HAL(pGpuLoop)) + { + linkHalImpl[SLI_BT_NVLINK] = GPU_LINK_DETECTION_HAL_STUB; + } + pGpuLoop = gpumgrGetNextGpu(gpuMask, &i); + } + + if (linkHalImpl[SLI_BT_NVLINK] != GPU_LINK_DETECTION_HAL_STUB) + { + gpuDetectNvlinkLinkFromGpus_HAL(pGpuSaved, gpuCount, gpuMaskArg, + &sliLinkOutputMask[SLI_BT_NVLINK], + &bSliLinkCircular[SLI_BT_NVLINK], + &sliLinkEndsMask[SLI_BT_NVLINK], + &vidLinkCount[SLI_BT_NVLINK]); + } + + // + // Determine which type of bridge we are going to support. + // Currently we only support a single type of SLI bridge in the system. + // + for (i = 0; i < SLI_MAX_BRIDGE_TYPES; ++i) + { + if (sliLinkOutputMask[i] != 0) + { + if (bFoundBridge) + { + NV_PRINTF(LEVEL_ERROR, "More than one type of SLI bridge detected!\n"); + NV_ASSERT(0); + break; + } + else + { + pGpuMgr->gpuBridgeType = (NvU8)i; + *pSliLinkOutputMask = sliLinkOutputMask[i]; + *pSliLinkCircular = bSliLinkCircular[i]; + *pSliLinkEndsMask = sliLinkEndsMask[i]; + *pVidLinkCount = vidLinkCount[i]; + bFoundBridge = NV_TRUE; + } + } + } +} diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/kernel/gpu/arch/pascal/kern_gpu_gp100.c nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/kernel/gpu/arch/pascal/kern_gpu_gp100.c --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/kernel/gpu/arch/pascal/kern_gpu_gp100.c 1970-01-01 00:00:00.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/kernel/gpu/arch/pascal/kern_gpu_gp100.c 2024-03-05 22:13:14.000000000 +0000 @@ -0,0 +1,135 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2014-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#include "core/core.h" +#include "gpu/gpu.h" +#include "gpu/eng_desc.h" +#include "gpu/gpu_child_class_defs.h" +#include "gpu/nvlink/kernel_nvlink.h" +#include "gpu_mgr/gpu_mgr_sli.h" + +/*! + * @brief checks for NvLink connections between the GPUs specified in the gpuMaskArg, + * and updates the routing information as appropriate. + * + * @param[In] gpuCount The number of GPUs to be checked for NvLink links. + * @param[In] gpuMaskArg A mask of the GPUs that are to be tested for NvLink links. + * @param[Out] pSliLinkOutputMask a mask of the GPUs that are attached to the NvLink link. + * @param[Out] pSliLinkCircular a boolean indicating if the NvLink link is circular + * (always FALSE). + * @param[Out] pSliLinkEndsMask a mask indicating the endpoints of the NvLink link. + * (always 0). + */ +void +gpuDetectNvlinkLinkFromGpus_GP100 +( + OBJGPU *pGpu, + NvU32 gpuCount, + NvU32 gpuMaskArg, + NvU32 *pSliLinkOutputMask, + NvBool *pSliLinkCircular, + NvU32 *pSliLinkEndsMask, + NvU32 *pVidLinkCount +) +{ + OBJGPU *pGpuLoop = NULL; + KernelNvlink *pKernelNvlink = NULL; + KernelNvlink *pKernelNvlinkChild = NULL; + OBJGPU *pGpuChild = NULL; + NvU32 gpuIndex = 0; + NvU32 gpuIndexChild = 0; + NvU32 parentPinsetIndex; + NvU32 childPinsetIndex; + NvU32 gpuMask = gpuMaskArg; + + *pSliLinkOutputMask = 0; + *pSliLinkCircular = NV_FALSE; + *pSliLinkEndsMask = 0; + *pVidLinkCount = 0; + + // + // Link detection HAL should have same HAL implementation as HAL flag. + // This checks for mismatched HAL implementation flag. + // + NV_ASSERT_OR_RETURN_VOID(gpuGetNvlinkLinkDetectionHalFlag_HAL(pGpu) == GPU_LINK_DETECTION_HAL_GP100); + + // Loop through GPU unique pairs + gpuIndex = 0; + pGpuLoop = gpumgrGetNextGpu(gpuMask, &gpuIndex); + while (pGpuLoop != NULL) + { + // determine if there is a connected NvLink on the GPU. + pKernelNvlink = GPU_GET_KERNEL_NVLINK(pGpuLoop); + if (NULL == pKernelNvlink) + { + pGpuLoop = gpumgrGetNextGpu(gpuMask, &gpuIndex); + continue; + } + + gpuIndexChild = gpuIndex; + pGpuChild = gpumgrGetNextGpu(gpuMask, &gpuIndexChild); + while (pGpuChild != NULL) + { + // determine if there is a connected NvLink on the GPU. + pKernelNvlinkChild = GPU_GET_KERNEL_NVLINK(pGpuChild); + if (NULL != pKernelNvlinkChild) + { + if (knvlinkIsNvlinkP2pSupported(pGpuLoop, pKernelNvlink, pGpuChild) == NV_FALSE) + { + pGpuChild = gpumgrGetNextGpu(gpuMask, &gpuIndexChild); + continue; + } + if (0 == knvlinkGetConnectedLinksMask_HAL(pGpuChild, pKernelNvlinkChild)) + { + pGpuChild = gpumgrGetNextGpu(gpuMask, &gpuIndexChild); + continue; + } + } + else + { + pGpuChild = gpumgrGetNextGpu(gpuMask, &gpuIndexChild); + continue; + } + // Loop through the parent pinsets + for (parentPinsetIndex = 0; parentPinsetIndex < DR_PINSET_COUNT; parentPinsetIndex++) + { + // Loop through the child pinsets + for (childPinsetIndex = 0; childPinsetIndex < DR_PINSET_COUNT; childPinsetIndex++) + { + if (gpumgrUpdateSliLinkRouting(pGpuLoop, pGpuChild, SLI_BT_NVLINK, + parentPinsetIndex, childPinsetIndex, NV_FALSE)) + { + // update link Output Mask + *pSliLinkOutputMask |= (NVBIT(pGpuLoop->gpuInstance) | NVBIT(pGpuChild->gpuInstance)); + + // Since we found the connection, don't even test any + // other ChildPinset for this connected ParentPinset. + break; + } + } // for (ChildPinset + } // for (ParentPinset + pGpuChild = gpumgrGetNextGpu(gpuMask, &gpuIndexChild); + } // while (pGpuChild) + pGpuLoop = gpumgrGetNextGpu(gpuMask, &gpuIndex); + } // while (pGpu) +} diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/kernel/gpu/arch/turing/kern_gpu_tu102.c nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/kernel/gpu/arch/turing/kern_gpu_tu102.c --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/kernel/gpu/arch/turing/kern_gpu_tu102.c 2023-10-25 20:20:52.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/kernel/gpu/arch/turing/kern_gpu_tu102.c 2024-03-05 22:13:14.000000000 +0000 @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 2021-2022 NVIDIA CORPORATION & AFFILIATES + * SPDX-FileCopyrightText: Copyright (c) 2021-2024 NVIDIA CORPORATION & AFFILIATES * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -21,8 +21,22 @@ * DEALINGS IN THE SOFTWARE. */ #include "gpu/gpu.h" +#include "gpu/gpu_child_class_defs.h" #include "published/turing/tu102/dev_vm.h" #include "published/turing/tu102/hwproject.h" +#include "gpu/mem_sys/kern_mem_sys.h" +#include "gpu/bus/kern_bus.h" +#include "gpu/bif/kernel_bif.h" +#include "gpu/mem_mgr/rm_page_size.h" +#include "nverror.h" +#include "jt.h" +#include "gpu/falcon/kernel_falcon.h" +#include "gpu/gsp/kernel_gsp.h" + +#include "published/turing/tu102/dev_nv_xve.h" +#include "published/turing/tu102/dev_gc6_island.h" +#include "published/turing/tu102/dev_gc6_island_addendum.h" +#include "published/turing/tu102/dev_falcon_v4.h" /*! * @brief Returns SR-IOV capabilities @@ -111,224 +125,379 @@ // static const GPUCHILDPRESENT gpuChildrenPresent_TU102[] = { - {classId(OBJSWENG), 1}, - {classId(OBJUVM), 1}, - {classId(OBJACR), 1}, - {classId(OBJBIF), 1}, - {classId(KernelBif), 1}, - {classId(OBJBSP), 1}, - {classId(OBJBUS), 1}, - {classId(KernelBus), 1}, - {classId(OBJCE), 9}, - {classId(KernelCE), 9}, - {classId(OBJCIPHER), 1}, - {classId(ClockManager), 1}, - {classId(OBJDISP), 1}, - {classId(KernelDisplay), 1}, - {classId(VirtMemAllocator), 1}, - {classId(OBJDPAUX), 1}, - {classId(Fan), 1}, - {classId(OBJHSHUBMANAGER), 1}, - {classId(Hshub), 1}, - {classId(MemorySystem), 1}, - {classId(KernelMemorySystem), 1}, - {classId(MemoryManager), 1}, - {classId(OBJFBFLCN), 1}, - {classId(KernelFifo), 1}, - {classId(OBJFIFO), 1}, - {classId(OBJGMMU), 1}, - {classId(KernelGmmu), 1}, - {classId(OBJGPULOG), 1}, - {classId(OBJGPUMON), 1}, - {classId(GraphicsManager), 1}, - {classId(MIGManager), 1}, - {classId(KernelMIGManager), 1}, - {classId(KernelGraphicsManager), 1}, - {classId(Graphics), 1}, - {classId(KernelGraphics), 1}, - {classId(OBJHDACODEC), 1}, - {classId(OBJHWPM), 1}, - {classId(OBJINFOROM), 1}, - {classId(Intr), 1}, - {classId(Lpwr ), 1}, - {classId(OBJLSFM), 1}, - {classId(OBJMC), 1}, - {classId(KernelMc), 1}, - {classId(PrivRing), 1}, - {classId(SwIntr), 1}, - {classId(OBJMSENC), 1}, - {classId(NvDebugDump), 1}, - {classId(KernelNvlink), 1}, - {classId(Nvlink), 1}, - {classId(Perf), 1}, - {classId(KernelPerf), 1}, - {classId(Pmgr), 1}, - {classId(Pmu), 1}, - {classId(KernelPmu), 1}, - {classId(OBJSEC2), 1}, - {classId(Gsp), 1}, - {classId(Therm), 1}, - {classId(OBJTMR), 1}, - {classId(OBJVOLT), 1}, - {classId(OBJGRIDDISPLAYLESS), 1}, - {classId(OBJFAS), 1}, - {classId(OBJVMMU), 1}, - {classId(KernelSec2), 1}, - {classId(KernelGsp), 1}, + GPU_CHILD_PRESENT(OBJTMR, 1), + GPU_CHILD_PRESENT(KernelMIGManager, 1), + GPU_CHILD_PRESENT(KernelGraphicsManager, 1), + GPU_CHILD_PRESENT(KernelRc, 1), + GPU_CHILD_PRESENT(Intr, 1), + GPU_CHILD_PRESENT(NvDebugDump, 1), + GPU_CHILD_PRESENT(OBJGPUMON, 1), + GPU_CHILD_PRESENT(OBJSWENG, 1), + GPU_CHILD_PRESENT(OBJUVM, 1), + GPU_CHILD_PRESENT(KernelBif, 1), + GPU_CHILD_PRESENT(KernelBus, 1), + GPU_CHILD_PRESENT(KernelCE, 9), + GPU_CHILD_PRESENT(KernelDisplay, 1), + GPU_CHILD_PRESENT(VirtMemAllocator, 1), + GPU_CHILD_PRESENT(KernelMemorySystem, 1), + GPU_CHILD_PRESENT(MemoryManager, 1), + GPU_CHILD_PRESENT(KernelFifo, 1), + GPU_CHILD_PRESENT(KernelGmmu, 1), + GPU_CHILD_PRESENT(KernelGraphics, 1), + GPU_CHILD_PRESENT(KernelMc, 1), + GPU_CHILD_PRESENT(SwIntr, 1), + GPU_CHILD_PRESENT(KernelNvlink, 1), + GPU_CHILD_PRESENT(KernelPerf, 1), + GPU_CHILD_PRESENT(KernelPmu, 1), + GPU_CHILD_PRESENT(KernelSec2, 1), + GPU_CHILD_PRESENT(KernelGsp, 1), }; static const GPUCHILDPRESENT gpuChildrenPresent_TU104[] = { - {classId(OBJSWENG), 1}, - {classId(OBJUVM), 1}, - {classId(OBJACR), 1}, - {classId(OBJBIF), 1}, - {classId(KernelBif), 1}, - {classId(OBJBSP), 2}, - {classId(OBJBUS), 1}, - {classId(KernelBus), 1}, - {classId(OBJCE), 9}, - {classId(KernelCE), 9}, - {classId(OBJCIPHER), 1}, - {classId(ClockManager), 1}, - {classId(OBJDISP), 1}, - {classId(KernelDisplay), 1}, - {classId(VirtMemAllocator), 1}, - {classId(OBJDPAUX), 1}, - {classId(Fan), 1}, - {classId(OBJHSHUBMANAGER), 1}, - {classId(Hshub), 1}, - {classId(MemorySystem), 1}, - {classId(KernelMemorySystem), 1}, - {classId(MemoryManager), 1}, - {classId(OBJFBFLCN), 1}, - {classId(KernelFifo), 1}, - {classId(OBJFIFO), 1}, - {classId(OBJGMMU), 1}, - {classId(KernelGmmu), 1}, - {classId(OBJGPULOG), 1}, - {classId(OBJGPUMON), 1}, - {classId(GraphicsManager), 1}, - {classId(MIGManager), 1}, - {classId(KernelMIGManager), 1}, - {classId(KernelGraphicsManager), 1}, - {classId(Graphics), 1}, - {classId(KernelGraphics), 1}, - {classId(OBJHDACODEC), 1}, - {classId(OBJHWPM), 1}, - {classId(OBJINFOROM), 1}, - {classId(Intr), 1}, - {classId(Lpwr ), 1}, - {classId(OBJLSFM), 1}, - {classId(OBJMC), 1}, - {classId(KernelMc), 1}, - {classId(PrivRing), 1}, - {classId(SwIntr), 1}, - {classId(OBJMSENC), 1}, - {classId(NvDebugDump), 1}, - {classId(KernelNvlink), 1}, - {classId(Nvlink), 1}, - {classId(Perf), 1}, - {classId(KernelPerf), 1}, - {classId(Pmgr), 1}, - {classId(Pmu), 1}, - {classId(KernelPmu), 1}, - {classId(OBJSEC2), 1}, - {classId(Gsp), 1}, - {classId(Therm), 1}, - {classId(OBJTMR), 1}, - {classId(OBJVOLT), 1}, - {classId(OBJGRIDDISPLAYLESS), 1}, - {classId(OBJFAS), 1}, - {classId(OBJVMMU), 1}, - {classId(KernelSec2), 1}, - {classId(KernelGsp), 1}, + GPU_CHILD_PRESENT(OBJTMR, 1), + GPU_CHILD_PRESENT(KernelMIGManager, 1), + GPU_CHILD_PRESENT(KernelGraphicsManager, 1), + GPU_CHILD_PRESENT(KernelRc, 1), + GPU_CHILD_PRESENT(Intr, 1), + GPU_CHILD_PRESENT(NvDebugDump, 1), + GPU_CHILD_PRESENT(OBJGPUMON, 1), + GPU_CHILD_PRESENT(OBJSWENG, 1), + GPU_CHILD_PRESENT(OBJUVM, 1), + GPU_CHILD_PRESENT(KernelBif, 1), + GPU_CHILD_PRESENT(KernelBus, 1), + GPU_CHILD_PRESENT(KernelCE, 9), + GPU_CHILD_PRESENT(KernelDisplay, 1), + GPU_CHILD_PRESENT(VirtMemAllocator, 1), + GPU_CHILD_PRESENT(KernelMemorySystem, 1), + GPU_CHILD_PRESENT(MemoryManager, 1), + GPU_CHILD_PRESENT(KernelFifo, 1), + GPU_CHILD_PRESENT(KernelGmmu, 1), + GPU_CHILD_PRESENT(KernelGraphics, 1), + GPU_CHILD_PRESENT(KernelMc, 1), + GPU_CHILD_PRESENT(SwIntr, 1), + GPU_CHILD_PRESENT(KernelNvlink, 1), + GPU_CHILD_PRESENT(KernelPerf, 1), + GPU_CHILD_PRESENT(KernelPmu, 1), + GPU_CHILD_PRESENT(KernelSec2, 1), + GPU_CHILD_PRESENT(KernelGsp, 1), }; static const GPUCHILDPRESENT gpuChildrenPresent_TU106[] = { - {classId(OBJSWENG), 1}, - {classId(OBJUVM), 1}, - {classId(OBJACR), 1}, - {classId(OBJBIF), 1}, - {classId(KernelBif), 1}, - {classId(OBJBSP), 3}, - {classId(OBJBUS), 1}, - {classId(KernelBus), 1}, - {classId(OBJCE), 9}, - {classId(KernelCE), 9}, - {classId(OBJCIPHER), 1}, - {classId(ClockManager), 1}, - {classId(OBJDISP), 1}, - {classId(KernelDisplay), 1}, - {classId(VirtMemAllocator), 1}, - {classId(OBJDPAUX), 1}, - {classId(Fan), 1}, - {classId(MemorySystem), 1}, - {classId(KernelMemorySystem), 1}, - {classId(MemoryManager), 1}, - {classId(OBJFBFLCN), 1}, - {classId(KernelFifo), 1}, - {classId(OBJFIFO), 1}, - {classId(OBJGMMU), 1}, - {classId(KernelGmmu), 1}, - {classId(OBJGPULOG), 1}, - {classId(OBJGPUMON), 1}, - {classId(GraphicsManager), 1}, - {classId(MIGManager), 1}, - {classId(KernelMIGManager), 1}, - {classId(KernelGraphicsManager), 1}, - {classId(Graphics), 1}, - {classId(KernelGraphics), 1}, - {classId(OBJHDACODEC), 1}, - {classId(OBJHWPM), 1}, - {classId(OBJINFOROM), 1}, - {classId(Intr), 1}, - {classId(Lpwr ), 1}, - {classId(OBJLSFM), 1}, - {classId(OBJMC), 1}, - {classId(KernelMc), 1}, - {classId(PrivRing), 1}, - {classId(SwIntr), 1}, - {classId(OBJMSENC), 1}, - {classId(NvDebugDump), 1}, - {classId(KernelNvlink), 1}, - {classId(Nvlink), 1}, - {classId(Perf), 1}, - {classId(KernelPerf), 1}, - {classId(Pmgr), 1}, - {classId(Pmu), 1}, - {classId(KernelPmu), 1}, - {classId(OBJSEC2), 1}, - {classId(Gsp), 1}, - {classId(Therm), 1}, - {classId(OBJTMR), 1}, - {classId(OBJVOLT), 1}, - {classId(OBJGRIDDISPLAYLESS), 1}, - {classId(OBJFAS), 1}, - {classId(OBJVMMU), 1}, - {classId(KernelSec2), 1}, - {classId(KernelGsp), 1}, + GPU_CHILD_PRESENT(OBJTMR, 1), + GPU_CHILD_PRESENT(KernelMIGManager, 1), + GPU_CHILD_PRESENT(KernelGraphicsManager, 1), + GPU_CHILD_PRESENT(KernelRc, 1), + GPU_CHILD_PRESENT(Intr, 1), + GPU_CHILD_PRESENT(NvDebugDump, 1), + GPU_CHILD_PRESENT(OBJGPUMON, 1), + GPU_CHILD_PRESENT(OBJSWENG, 1), + GPU_CHILD_PRESENT(OBJUVM, 1), + GPU_CHILD_PRESENT(KernelBif, 1), + GPU_CHILD_PRESENT(KernelBus, 1), + GPU_CHILD_PRESENT(KernelCE, 9), + GPU_CHILD_PRESENT(KernelDisplay, 1), + GPU_CHILD_PRESENT(VirtMemAllocator, 1), + GPU_CHILD_PRESENT(KernelMemorySystem, 1), + GPU_CHILD_PRESENT(MemoryManager, 1), + GPU_CHILD_PRESENT(KernelFifo, 1), + GPU_CHILD_PRESENT(KernelGmmu, 1), + GPU_CHILD_PRESENT(KernelGraphics, 1), + GPU_CHILD_PRESENT(KernelMc, 1), + GPU_CHILD_PRESENT(SwIntr, 1), + GPU_CHILD_PRESENT(KernelNvlink, 1), + GPU_CHILD_PRESENT(KernelPerf, 1), + GPU_CHILD_PRESENT(KernelPmu, 1), + GPU_CHILD_PRESENT(KernelSec2, 1), + GPU_CHILD_PRESENT(KernelGsp, 1), }; const GPUCHILDPRESENT * gpuGetChildrenPresent_TU102(OBJGPU *pGpu, NvU32 *pNumEntries) { - *pNumEntries = NV_ARRAY_ELEMENTS32(gpuChildrenPresent_TU102); + *pNumEntries = NV_ARRAY_ELEMENTS(gpuChildrenPresent_TU102); return gpuChildrenPresent_TU102; } const GPUCHILDPRESENT * gpuGetChildrenPresent_TU104(OBJGPU *pGpu, NvU32 *pNumEntries) { - *pNumEntries = NV_ARRAY_ELEMENTS32(gpuChildrenPresent_TU104); + *pNumEntries = NV_ARRAY_ELEMENTS(gpuChildrenPresent_TU104); return gpuChildrenPresent_TU104; } const GPUCHILDPRESENT * gpuGetChildrenPresent_TU106(OBJGPU *pGpu, NvU32 *pNumEntries) { - *pNumEntries = NV_ARRAY_ELEMENTS32(gpuChildrenPresent_TU106); + *pNumEntries = NV_ARRAY_ELEMENTS(gpuChildrenPresent_TU106); return gpuChildrenPresent_TU106; } +/*! + * @brief Check if the DSM JT version is correct + * + * @param pGpu OBJGPU pointer + * + * @return NV_OK if DSM version matches otherwise NV_ERR_INVALID_PARAMETER + */ +NV_STATUS +gpuJtVersionSanityCheck_TU102 +( + OBJGPU *pGpu +) +{ + NV_STATUS status = NV_OK; + + if (!IS_SILICON(pGpu) || NV_IS_MODS) + { + goto gpuJtVersionSanityCheck_TU102_EXIT; + } + + if (FLD_TEST_DRF(_JT_FUNC, _CAPS, _JT_ENABLED, _TRUE, pGpu->acpiMethodData.jtMethodData.jtCaps)) + { + if (!(pGpu->acpiMethodData.jtMethodData.jtRevId == NV_JT_FUNC_CAPS_REVISION_ID_2_00)) + { + NV_PRINTF(LEVEL_ERROR, + "JT Version mismatch 0x%x\n", pGpu->acpiMethodData.jtMethodData.jtRevId); + DBG_BREAKPOINT(); + status = NV_ERR_INVALID_PARAMETER; + goto gpuJtVersionSanityCheck_TU102_EXIT; + } + } + +gpuJtVersionSanityCheck_TU102_EXIT: + return status; +} + +/* + * @brief Function that checks if ECC error occurred by reading various count + * registers/interrupt registers. This function is not floorsweeping-aware so + * PRI errors are ignored + */ +NvBool +gpuCheckEccCounts_TU102 +( + OBJGPU *pGpu +) +{ + NvU32 dramCount = 0; + NvU32 ltcCount = 0; + NvU32 mmuCount = 0; + NvU32 pcieCount = 0; + + kmemsysGetEccCounts_HAL(pGpu, GPU_GET_KERNEL_MEMORY_SYSTEM(pGpu), &dramCount, <cCount); + mmuCount += kgmmuGetEccCounts_HAL(pGpu, GPU_GET_KERNEL_GMMU(pGpu)); + pcieCount += kbifGetEccCounts_HAL(pGpu, GPU_GET_KERNEL_BIF(pGpu)); + pcieCount += kbusGetEccCounts_HAL(pGpu, GPU_GET_KERNEL_BUS(pGpu)); + + // If counts > 0 or if poison interrupt pending, ECC error has occurred. + if (((dramCount + ltcCount + mmuCount + pcieCount) != 0) || gpuCheckIfFbhubPoisonIntrPending_HAL(pGpu)) + { + NV_ERROR_LOG(pGpu, UNRECOVERABLE_ECC_ERROR_ESCAPE, + "An uncorrectable ECC error detected " + "(possible firmware handling failure) " + "DRAM:%d, LTC:%d, MMU:%d, PCIE:%d", dramCount, ltcCount, mmuCount, pcieCount); + return NV_TRUE; + } + + return NV_FALSE; +} + +// +// This function checks for GFW boot completion status by reading +// NV_AON_SECURE_SCRATCH_GROUP_05_0_GFW_BOOT_PROGRESS_COMPLETED bits and +// return true if GFW boot has completed. +// +// Either pGpu or pgc6VirtAddr should be not null. +// This function needs to be called in early init code-path where OBJGPU +// has not created. For that case, the NV_PGC6 base address will be mapped +// and pgc6VirtAddr will contain the virtual address for NV_PGC6. +// If pgc6VirtAddr is not null, then read the register with MEM_RD32, +// otherwise use the GPU_REG_RD32. +// +// The current GFW boot progress value will be returned in gfwBootProgressVal. +// +static NvBool +_gpuIsGfwBootCompleted_TU102 +( + OBJGPU *pGpu, + NvU8 *pgc6VirtAddr, + NvU32 *gfwBootProgressVal +) +{ + NvU32 regVal; + + if (pgc6VirtAddr != NULL) + { + regVal = MEM_RD32(pgc6VirtAddr + + (NV_PGC6_AON_SECURE_SCRATCH_GROUP_05_PRIV_LEVEL_MASK - + DEVICE_BASE(NV_PGC6))); + } + else + { + regVal = GPU_REG_RD32(pGpu, NV_PGC6_AON_SECURE_SCRATCH_GROUP_05_PRIV_LEVEL_MASK); + } + + // + // Before reading the actual GFW_BOOT status register, + // we want to check that FWSEC has lowered its PLM first. + // If not then obviously it has not completed. + // + if (!FLD_TEST_DRF(_PGC6, _AON_SECURE_SCRATCH_GROUP_05_PRIV_LEVEL_MASK, + _READ_PROTECTION_LEVEL0, _ENABLE, regVal)) + { + *gfwBootProgressVal = 0x0; + return NV_FALSE; + } + + if (pgc6VirtAddr != NULL) + { + regVal = MEM_RD32(pgc6VirtAddr + + (NV_PGC6_AON_SECURE_SCRATCH_GROUP_05_0_GFW_BOOT - + DEVICE_BASE(NV_PGC6))); + } + else + { + regVal = GPU_REG_RD32(pGpu, NV_PGC6_AON_SECURE_SCRATCH_GROUP_05_0_GFW_BOOT); + } + + *gfwBootProgressVal = DRF_VAL(_PGC6, _AON_SECURE_SCRATCH_GROUP_05_0_GFW_BOOT, + _PROGRESS, regVal); + + return FLD_TEST_DRF(_PGC6, _AON_SECURE_SCRATCH_GROUP_05_0_GFW_BOOT, + _PROGRESS, _COMPLETED, regVal); +} + +#define FWSECLIC_PROG_START_TIMEOUT 50000 // 50ms +#define FWSECLIC_PROG_COMPLETE_TIMEOUT 2000000 // 2s +#define GPU_GFW_BOOT_COMPLETION_TIMEOUT_US (FWSECLIC_PROG_START_TIMEOUT + \ + FWSECLIC_PROG_COMPLETE_TIMEOUT) +NV_STATUS +gpuWaitForGfwBootComplete_TU102 +( + OBJGPU *pGpu +) +{ + NvU32 timeoutUs = GPU_GFW_BOOT_COMPLETION_TIMEOUT_US; + NvU32 gfwBootProgressVal = 0; + RMTIMEOUT timeout; + NV_STATUS status = NV_OK; + KernelGsp *pKernelGsp = GPU_GET_KERNEL_GSP(pGpu); + KernelFalcon *pKernelFalcon = staticCast(pKernelGsp, KernelFalcon); + + // Use the OS timer since the GPU timer is not ready yet + gpuSetTimeout(pGpu, gpuScaleTimeout(pGpu, timeoutUs), &timeout, + GPU_TIMEOUT_FLAGS_OSTIMER); + + while (status == NV_OK) + { + if (_gpuIsGfwBootCompleted_TU102(pGpu, NULL, &gfwBootProgressVal)) + { + status = NV_OK; + break; + } + + status = gpuCheckTimeout(pGpu, &timeout); + } + + if (status != NV_OK) + { + NV_PRINTF(LEVEL_ERROR, "failed to wait for GFW_BOOT: (progress 0x%x)\n", + gfwBootProgressVal); + return status; + } + + // + // GFW runs on GSP, so wait for GSP to halt as well + // OS timer need to be used here, hence not using wrapper kflcnWaitForHalt_HAL + // + while (status == NV_OK) + { + if (FLD_TEST_DRF(_PFALCON, _FALCON, _CPUCTL_HALTED, _TRUE, + kflcnRegRead_HAL(pGpu, pKernelFalcon, NV_PFALCON_FALCON_CPUCTL))) + { + return NV_OK; + } + + status = gpuCheckTimeout(pGpu, &timeout); + } + + NV_PRINTF(LEVEL_ERROR, "GSP failed to halt after GFW completion\n"); + + return status; +} + +// +// Workaround for Bug 3809777. +// +// This function is not created through HAL infrastructure. It needs to be +// called when OBJGPU is not created. HAL infrastructure can’t be used for +// this case, so it has been added manually. It will be invoked directly by +// gpumgrIsDeviceMsixAllowed() after checking the GPU architecture. +// +// When driver is running inside guest in pass-through mode, check if MSI-X +// is enabled by reading NV_XVE_PRIV_MISC_1_CYA_HIDE_MSIX_CAP. The devinit +// can disable MSI-X capability, if configured. The hypervisor issues reset +// before launching VM. After reset, the MSI-X capability will be visible +// for some duration and then devinit hides the MSI-X capability. This +// devinit will run in the background. During this time, the hypervisor can +// assume that MSI-X capability is present in the GPU and configure the guest +// GPU PCIe device instance with MSI-X capability. When GPU tries to use the +// MSI-X interrupts later, then interrupt won’t be triggered. To identify +// this case, wait for GPU devinit completion and check if MSI-X capability +// is not hidden. +// +NvBool gpuIsMsixAllowed_TU102 +( + RmPhysAddr bar0BaseAddr +) +{ + NvU8 *vAddr; + NvU32 regVal; + NvU32 timeUs = 0; + NvU32 gfwBootProgressVal = 0; + NvBool bGfwBootCompleted = NV_FALSE; + + ct_assert(DRF_SIZE(NV_PGC6) <= RM_PAGE_SIZE); + vAddr = osMapKernelSpace(bar0BaseAddr + DEVICE_BASE(NV_PGC6), + RM_PAGE_SIZE, NV_MEMORY_UNCACHED, + NV_PROTECT_READABLE); + if (vAddr == NULL) + { + return NV_FALSE; + } + + while (timeUs < GPU_GFW_BOOT_COMPLETION_TIMEOUT_US) + { + bGfwBootCompleted = _gpuIsGfwBootCompleted_TU102(NULL, vAddr, &gfwBootProgressVal); + if (bGfwBootCompleted) + { + break; + } + + osDelayUs(1000); + timeUs += 1000; + } + + osUnmapKernelSpace(vAddr, RM_PAGE_SIZE); + if (!bGfwBootCompleted) + { + NV_PRINTF(LEVEL_ERROR, "failed to wait for GFW_BOOT: (progress 0x%x)\n", + gfwBootProgressVal); + return NV_FALSE; + } + + vAddr = osMapKernelSpace(bar0BaseAddr + DEVICE_BASE(NV_PCFG) + + NV_XVE_PRIV_MISC_1, 4, NV_MEMORY_UNCACHED, + NV_PROTECT_READABLE); + if (vAddr == NULL) + { + return NV_FALSE; + } + + regVal = MEM_RD32(vAddr); + osUnmapKernelSpace(vAddr, 4); + + return FLD_TEST_DRF(_XVE, _PRIV_MISC_1, _CYA_HIDE_MSIX_CAP, _FALSE, regVal); +} diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/kernel/gpu/bif/arch/ada/kernel_bif_ad102.c nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/kernel/gpu/bif/arch/ada/kernel_bif_ad102.c --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/kernel/gpu/bif/arch/ada/kernel_bif_ad102.c 1970-01-01 00:00:00.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/kernel/gpu/bif/arch/ada/kernel_bif_ad102.c 2024-03-05 22:13:14.000000000 +0000 @@ -0,0 +1,88 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2022-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +/* ------------------------ Includes ---------------------------------------- */ +#include "os/os.h" +#include "gpu/bif/kernel_bif.h" + +#include "published/ada/ad102/dev_bus.h" +#include "published/ada/ad102/dev_bus_addendum.h" + +static NvBool _kbifPreOsCheckErotGrantAllowed_AD102(OBJGPU *pGpu, void *pVoid); + +/*! + * Signals preOs to have eRoT hand over control of EEPROM to RM + * + * @param[in] pGpu OBJGPU pointer + * @param[in] pKernelBif KernelBif pointer + * + * @returns NV_OK if RM has control of the EEPROM + * @returns NV_ERR_TIMEOUT if preOs fails to hand over control of the EEPROM + * + */ +NV_STATUS +kbifPreOsGlobalErotGrantRequest_AD102 +( + OBJGPU *pGpu, + KernelBif *pKernelBif +) +{ + NV_STATUS status = NV_OK; + NvU32 reg = GPU_REG_RD32(pGpu, NV_PBUS_SW_GLOBAL_EROT_GRANT); + + // Invalid value suggests that there is no ERoT + if (FLD_TEST_DRF(_PBUS, _SW_GLOBAL_EROT_GRANT, _VALID, _NO, reg)) + { + return status; + } + + // Check if grant has already been allowed + if (_kbifPreOsCheckErotGrantAllowed_AD102(pGpu, NULL)) + { + return status; + } + + reg = FLD_SET_DRF(_PBUS, _SW_GLOBAL_EROT_GRANT, _REQUEST, _SET, reg); + GPU_REG_WR32(pGpu, NV_PBUS_SW_GLOBAL_EROT_GRANT, reg); + + status = gpuTimeoutCondWait(pGpu, _kbifPreOsCheckErotGrantAllowed_AD102, NULL, NULL); + if (status != NV_OK) + { + NV_PRINTF(LEVEL_ERROR, "Timed out waiting for preOs to grant access to EEPROM\n"); + } + + return status; +} + +static NvBool +_kbifPreOsCheckErotGrantAllowed_AD102 +( + OBJGPU *pGpu, + void *pVoid +) +{ + NvU32 reg = GPU_REG_RD32(pGpu, NV_PBUS_SW_GLOBAL_EROT_GRANT); + + return FLD_TEST_DRF(_PBUS, _SW_GLOBAL_EROT_GRANT, _ALLOW, _YES, reg); +} + diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/kernel/gpu/bif/arch/hopper/kernel_bif_gh100.c nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/kernel/gpu/bif/arch/hopper/kernel_bif_gh100.c --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/kernel/gpu/bif/arch/hopper/kernel_bif_gh100.c 2023-10-25 20:20:52.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/kernel/gpu/bif/arch/hopper/kernel_bif_gh100.c 2024-03-05 22:13:15.000000000 +0000 @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 2021-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2021-2024 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -26,18 +26,19 @@ #include "nverror.h" #include "gpu/bif/kernel_bif.h" +#include "gpu/fsp/kern_fsp.h" #include "platform/chipset/chipset.h" #include "ctrl/ctrl2080/ctrl2080bus.h" #include "published/hopper/gh100/dev_fb.h" +#include "published/hopper/gh100/hwproject.h" #include "published/hopper/gh100/dev_xtl_ep_pri.h" +#include "published/hopper/gh100/dev_nv_xpl.h" #include "published/hopper/gh100/dev_xtl_ep_pcfg_gpu.h" #include "published/hopper/gh100/hwproject.h" #include "os/os.h" -static void _kbifEnablePcieAtomics_GH100(OBJGPU *); - /*! * @brief Check if MSI is enabled in HW * @@ -272,7 +273,6 @@ KernelBif *pKernelBif ) { - NvU32 xveDevCtrlStatus; if (GPU_BUS_CFG_CYCLE_RD32(pGpu, @@ -339,7 +339,6 @@ NvU32 *pStatus ) { - // control/status reg 0x68 NvU32 xtlDevCtrlStatus; @@ -419,7 +418,6 @@ NvU32 *pStatus ) { - NvU32 xtlDevCtrlStatus; if (pStatus) @@ -462,7 +460,6 @@ NvU32 *pBits ) { - NvU32 xtlAerUncorr; NvU32 xtlAerCorr; @@ -538,7 +535,6 @@ NvU32 bits ) { - NvU32 xtlAerUncorr = 0; NvU32 xtlAerCorr = 0; @@ -611,7 +607,6 @@ NvU32 *pSize ) { - *pBase = DEVICE_BASE(NV_EP_PCFGM); *pSize = DEVICE_EXTENT(NV_EP_PCFGM) - DEVICE_BASE(NV_EP_PCFGM) + 1; return NV_OK; @@ -658,7 +653,7 @@ pKernelBif->osPcieAtomicsOpMask = osAtomicsMask; // Program PCIe atomics register settings - _kbifEnablePcieAtomics_GH100(pGpu); + kbifEnablePcieAtomics_HAL(pGpu, pKernelBif); return; } @@ -666,12 +661,15 @@ /*! * @brief Enable PCIe atomics if PCIe hierarchy supports it * - * @param[in] pGpu GPU object pointer + * @param[in] pGpu GPU object pointer + * @param[in] pKernelBif Kernel BIF object pointer + * */ -static void -_kbifEnablePcieAtomics_GH100 +void +kbifEnablePcieAtomics_GH100 ( - OBJGPU *pGpu + OBJGPU *pGpu, + KernelBif *pKernelBif ) { NvU32 regVal; @@ -736,7 +734,6 @@ return status; } - /*! * @brief: Get BAR information from PCIe config space * @@ -874,3 +871,39 @@ pGpu->sriovState.firstVFBarAddress[2] = barAddr; pGpu->sriovState.b64bitVFBar2 = barIs64Bit; } + +NvU32 +kbifGetEccCounts_GH100 +( + OBJGPU *pGpu, + KernelBif *pKernelBif +) +{ + NvU32 regVal; + NvU32 count = 0; + + // PCIE RBUF + regVal = GPU_REG_RD32(pGpu, NV_XPL_BASE_ADDRESS + NV_XPL_DL_ERR_COUNT_RBUF); + count += DRF_VAL(_XPL_DL, _ERR_COUNT_RBUF, _UNCORR_ERR, regVal); + + // PCIE SEQ_LUT + regVal = GPU_REG_RD32(pGpu, NV_XPL_BASE_ADDRESS + NV_XPL_DL_ERR_COUNT_SEQ_LUT); + count += DRF_VAL(_XPL_DL, _ERR_COUNT_SEQ_LUT, _UNCORR_ERR, regVal); + + // PCIE XTL + regVal = GPU_REG_RD32(pGpu, NV_XTL_BASE_ADDRESS + NV_XTL_EP_PRI_DED_ERROR_STATUS); + if (regVal != 0) + { + count += 1; + } + + // PCIE XTL + regVal = GPU_REG_RD32(pGpu, NV_XTL_BASE_ADDRESS + NV_XTL_EP_PRI_RAM_ERROR_INTR_STATUS); + if (regVal != 0) + { + count += 1; + } + + return count; +} + diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/kernel/gpu/bif/arch/maxwell/kernel_bif_gm107.c nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/kernel/gpu/bif/arch/maxwell/kernel_bif_gm107.c --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/kernel/gpu/bif/arch/maxwell/kernel_bif_gm107.c 2023-10-25 20:20:52.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/kernel/gpu/bif/arch/maxwell/kernel_bif_gm107.c 2024-03-05 22:13:15.000000000 +0000 @@ -631,3 +631,36 @@ } return status; } + +NV_STATUS +kbifDisableSysmemAccess_GM107 +( + OBJGPU *pGpu, + KernelBif *pKernelBif, + NvBool bDisable +) +{ + NV_STATUS status = NV_OK; + RM_API *pRmApi = GPU_GET_PHYSICAL_RMAPI(pGpu); + NV2080_CTRL_INTERNAL_BIF_DISABLE_SYSTEM_MEMORY_ACCESS_PARAMS params = {0}; + + // Only support on Windows + NV_ASSERT_OR_RETURN(RMCFG_FEATURE_PLATFORM_WINDOWS_LDDM, NV_ERR_NOT_SUPPORTED); + + params.bDisable = bDisable; + status = pRmApi->Control(pRmApi, + pGpu->hInternalClient, + pGpu->hInternalSubdevice, + NV2080_CTRL_CMD_INTERNAL_BIF_DISABLE_SYSTEM_MEMORY_ACCESS, + ¶ms, + sizeof(NV2080_CTRL_INTERNAL_BIF_DISABLE_SYSTEM_MEMORY_ACCESS_PARAMS)); + + // Only set the PDB in kernel if it was set in physical successfully + if (status == NV_OK) + { + pKernelBif->setProperty(pKernelBif, PDB_PROP_KBIF_SYSTEM_ACCESS_DISABLED, bDisable); + } + + return status; +} + diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/kernel/gpu/bif/arch/turing/kernel_bif_tu102.c nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/kernel/gpu/bif/arch/turing/kernel_bif_tu102.c --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/kernel/gpu/bif/arch/turing/kernel_bif_tu102.c 2023-10-25 20:20:52.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/kernel/gpu/bif/arch/turing/kernel_bif_tu102.c 2024-03-05 22:13:15.000000000 +0000 @@ -32,8 +32,6 @@ #include "virtualization/kernel_vgpu_mgr.h" #include "virtualization/hypervisor/hypervisor.h" -#define NUM_VF_SPARSE_MMAP_REGIONS 2 - #include "published/turing/tu102/dev_nv_xve.h" #include "published/turing/tu102/dev_vm.h" @@ -93,137 +91,113 @@ } } -/*! - * @brief Get the number of sparse mmap regions - * - * @param[in] pGpu GPU object pointer - * @param[in] pKernelBif BIF object pointer - * @param[out] numAreas Number of sparse mmap regions - * - * @returns NV_OK If all args are proper - * NV_ERR_INVALID_ARGUMENT In case of erroneous args - */ - NV_STATUS -kbifGetNumVFSparseMmapRegions_TU102 +kbifGetVFSparseMmapRegions_TU102 ( OBJGPU *pGpu, KernelBif *pKernelBif, KERNEL_HOST_VGPU_DEVICE *pKernelHostVgpuDevice, - NvU32 *numAreas + NvU64 osPageSize, + NvU32 *pNumAreas, + NvU64 *pOffsets, + NvU64 *pSizes ) { - if (numAreas && pKernelHostVgpuDevice != NULL) - { - NvU32 maxInstance = 0; - NV_STATUS status; + NvU64 offsetStart = 0; + NvU64 offsetEnd = 0; + NvU32 idx = 0; + NvU32 maxInstance; + NvU32 i; + NvBool bDryRun; - status = kvgpumgrGetMaxInstanceOfVgpu(pKernelHostVgpuDevice->vgpuType, &maxInstance); - if (status != NV_OK) - goto exit; + NV_CHECK_OR_RETURN(LEVEL_ERROR, pKernelHostVgpuDevice != NULL, NV_ERR_INVALID_ARGUMENT); + NV_CHECK_OR_RETURN(LEVEL_ERROR, pNumAreas != NULL, NV_ERR_INVALID_ARGUMENT); - if (maxInstance != 1 && pGpu->getProperty(pGpu, PDB_PROP_GPU_BUG_3007008_EMULATE_VF_MMU_TLB_INVALIDATE)) - *numAreas = NUM_VF_SPARSE_MMAP_REGIONS + 1; // +1 for TLB invalidation - else - *numAreas = NUM_VF_SPARSE_MMAP_REGIONS; + NV_CHECK_OK_OR_RETURN(LEVEL_ERROR, + kvgpumgrGetMaxInstanceOfVgpu(pKernelHostVgpuDevice->vgpuType, + &maxInstance)); - return NV_OK; + // Dry run to calculate the total number of areas + bDryRun = ((pOffsets == NULL) || (pSizes == NULL)); + if (bDryRun) + { + pOffsets = portMemAllocStackOrHeap(NVA084_CTRL_KERNEL_HOST_VGPU_DEVICE_MAX_BAR_MAPPING_RANGES * sizeof(pOffsets[0])); + pSizes = portMemAllocStackOrHeap(NVA084_CTRL_KERNEL_HOST_VGPU_DEVICE_MAX_BAR_MAPPING_RANGES * sizeof(pSizes[0])); } -exit: - return NV_ERR_INVALID_ARGUMENT; -} - -NV_STATUS -kbifGetVFSparseMmapRegions_TU102 -( - OBJGPU *pGpu, - KernelBif *pKernelBif, - KERNEL_HOST_VGPU_DEVICE *pKernelHostVgpuDevice, - NvU64 os_page_size, - NvU64 *offsets, - NvU64 *sizes) -{ - NvBool bEmulateVfTlbInvalidation = pGpu->getProperty(pGpu, PDB_PROP_GPU_BUG_3007008_EMULATE_VF_MMU_TLB_INVALIDATE); - NvU64 offsetStart = 0; - NvU64 offsetEnd = 0; - int idx = 0; + // For SRIOV heavy, trap BOOT_0 page + if (gpuIsWarBug200577889SriovHeavyEnabled(pGpu)) + { + offsetStart = osPageSize; + } - if (offsets && sizes && pKernelHostVgpuDevice != NULL) + // For VF TLB emulation, trap MMU FAULT BUFFER page + if ((maxInstance > 1) && pGpu->getProperty(pGpu, PDB_PROP_GPU_BUG_3007008_EMULATE_VF_MMU_TLB_INVALIDATE)) { - NvU32 maxInstance = 0; - NV_STATUS status; + offsetEnd = NV_VIRTUAL_FUNCTION_PRIV_MMU_FAULT_BUFFER_LO(0); + pOffsets[idx] = offsetStart; + pSizes[idx] = offsetEnd - offsetStart; + idx++; - status = kvgpumgrGetMaxInstanceOfVgpu(pKernelHostVgpuDevice->vgpuType, &maxInstance); - if (status != NV_OK) - return NV_ERR_INVALID_ARGUMENT; + offsetStart = NV_VIRTUAL_FUNCTION_PRIV_MMU_FAULT_BUFFER_LO(0) + osPageSize; + } - // For SRIOV heavy, trap BOOT_0 page - if (gpuIsWarBug200577889SriovHeavyEnabled(pGpu)) - { - offsetStart = os_page_size; - } + // For non-GSP, trap VGPU_EMU page + if (!IS_VGPU_GSP_PLUGIN_OFFLOAD_ENABLED(pGpu)) + { + offsetEnd = DRF_BASE(NV_VGPU_EMU); + pOffsets[idx] = offsetStart; + pSizes[idx] = offsetEnd - offsetStart; + idx++; - // For VF TLB emulation, trap MMU FAULT BUFFER page - if ((maxInstance > 1) && bEmulateVfTlbInvalidation) - { - offsetEnd = NV_VIRTUAL_FUNCTION_PRIV_MMU_FAULT_BUFFER_LO(0); - offsets[idx] = offsetStart; - sizes[idx] = offsetEnd - offsetStart; - idx++; + offsetStart = DRF_BASE(NV_VGPU_EMU) + osPageSize; + } - offsetStart = NV_VIRTUAL_FUNCTION_PRIV_MMU_FAULT_BUFFER_LO(0) + os_page_size; - } + // For non-HyperV, trap MSI-X table page + if (!hypervisorIsType(OS_HYPERVISOR_HYPERV)) + { + // Assert whenever the MSI-X table page is not immediately after + // the NV_VGPU_EMU page, as it will break the current assumption. + ct_assert((DRF_BASE(NV_VGPU_EMU) + DRF_SIZE(NV_VGPU_EMU)) == NV_VIRTUAL_FUNCTION_PRIV_MSIX_TABLE_ADDR_LO(0)); + + offsetEnd = NV_VIRTUAL_FUNCTION_PRIV_MSIX_TABLE_ADDR_LO(0); - // For non-GSP, trap VGPU_EMU page - if (!IS_VGPU_GSP_PLUGIN_OFFLOAD_ENABLED(pGpu)) + // Since MSI-X page is immediately after VGPU_EMU, if both are + // trapped, skip creating a 0 size region in between + if (offsetEnd > offsetStart) { - offsetEnd = DRF_BASE(NV_VGPU_EMU); - offsets[idx] = offsetStart; - sizes[idx] = offsetEnd - offsetStart; + pOffsets[idx] = offsetStart; + pSizes[idx] = offsetEnd - offsetStart; idx++; - - offsetStart = DRF_BASE(NV_VGPU_EMU) + os_page_size; } - // For non-HyperV, trap MSI-X table page - if (!hypervisorIsType(OS_HYPERVISOR_HYPERV)) - { - // Assert whenever the MSI-X table page is not immediately after - // the NV_VGPU_EMU page, as it will break the current assumption. - NV_ASSERT((DRF_BASE(NV_VGPU_EMU) + DRF_SIZE(NV_VGPU_EMU)) == - NV_VIRTUAL_FUNCTION_PRIV_MSIX_TABLE_ADDR_LO(0)); - - offsetEnd = NV_VIRTUAL_FUNCTION_PRIV_MSIX_TABLE_ADDR_LO(0); - - // Since MSI-X page is immediately after VGPU_EMU, if both are - // trapped, skip creating a 0 size region in between - if (offsetEnd > offsetStart) - { - offsets[idx] = offsetStart; - sizes[idx] = offsetEnd - offsetStart; - idx++; - } + offsetStart = NV_VIRTUAL_FUNCTION_PRIV_MSIX_TABLE_ADDR_LO(0) + osPageSize; + } - offsetStart = NV_VIRTUAL_FUNCTION_PRIV_MSIX_TABLE_ADDR_LO(0) + os_page_size; - } + offsetEnd = pGpu->sriovState.vfBarSize[0]; + pOffsets[idx] = offsetStart; + pSizes[idx] = offsetEnd - offsetStart; + idx++; - offsetEnd = pGpu->sriovState.vfBarSize[0]; - offsets[idx] = offsetStart; - sizes[idx] = offsetEnd - offsetStart; - idx++; + if (bDryRun) + { + portMemFreeStackOrHeap(pOffsets); + portMemFreeStackOrHeap(pSizes); } else { - return NV_ERR_INVALID_ARGUMENT; - } + // It might be too late to check if the passed arrays are big enough, + // but better late than never + NV_ASSERT_OR_RETURN(idx <= *pNumAreas, NV_ERR_FATAL_ERROR); - for (int i = 0; i < idx; i++) - { - NV_PRINTF(LEVEL_INFO, "VF Sparse Mmap Region[%u] range 0x%llx - 0x%llx, size 0x%llx\n", - i, offsets[i], offsets[i] + sizes[i], sizes[i]); + for (i = 0; i < idx; i++) + { + NV_PRINTF(LEVEL_INFO, "VF Sparse Mmap Region[%u] range 0x%llx - 0x%llx, size 0x%llx\n", + i, pOffsets[i], pOffsets[i] + pSizes[i], pSizes[i]); + } } + *pNumAreas = idx; return NV_OK; } diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/kernel/gpu/bif/kernel_bif.c nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/kernel/gpu/bif/kernel_bif.c --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/kernel/gpu/bif/kernel_bif.c 2023-10-25 20:20:52.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/kernel/gpu/bif/kernel_bif.c 2024-03-05 22:13:15.000000000 +0000 @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 2013-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2013-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -73,6 +73,9 @@ // Disables P2P on VF kbifDisableP2PTransactions_HAL(pGpu, pKernelBif); + // Cache MNOC interface support + kbifIsMnocSupported_HAL(pGpu, pKernelBif); + // Cache VF info kbifCacheVFInfo_HAL(pGpu, pKernelBif); @@ -248,6 +251,7 @@ NvU32 flags ) { + return NV_OK; } @@ -375,7 +379,7 @@ kbifPcieConfigDisableRelaxedOrdering_HAL(pGpu, pKernelBif); } - // + // // WAR for bug 3661529. All GH100 SKUs will need the NoSnoop WAR. // But currently GSP-RM does not detect this correctly, // @@ -518,7 +522,7 @@ } /*! - * @brief Clear PCIe HW PCIe config space error counters. + * @brief Clear PCIe HW PCIe config space error counters. * All of these should be cleared using config cycles. * * @param[in] pGpu GPU object pointer @@ -732,8 +736,8 @@ } } -static NvU32 -kbifGetGpuLinkCapabilities +NvU32 +kbifGetGpuLinkCapabilities_IMPL ( OBJGPU *pGpu, KernelBif *pKernelBif @@ -756,8 +760,8 @@ return data; } -static NvU32 -kbifGetGpuLinkControlStatus +NvU32 +kbifGetGpuLinkControlStatus_IMPL ( OBJGPU *pGpu, KernelBif *pKernelBif @@ -783,7 +787,7 @@ static NvBool _doesBoardHaveMultipleGpusAndSwitch(OBJGPU *pGpu) { - if (((gpuIsMultiGpuBoard(pGpu, NULL)) || + if (((gpuIsMultiGpuBoard(pGpu)) || (pGpu->getProperty(pGpu, PDB_PROP_GPU_IS_GEMINI)))&& ((pGpu->getProperty(pGpu, PDB_PROP_GPU_IS_PLX_PRESENT)) || (pGpu->getProperty(pGpu, PDB_PROP_GPU_IS_BR03_PRESENT)) || @@ -812,8 +816,8 @@ if (kbifGetBusIntfType_HAL(pKernelBif) != NV2080_CTRL_BUS_INFO_TYPE_PCI_EXPRESS) { - // KMD cannot handle error codes for this ctrl call, hence returning - // NV_OK, once KMD fixes the bug:3545197, RM can return NV_ERR_NOT_SUPPORTED + // KMD cannot handle error codes for this ctrl call, hence returning + // NV_OK, once KMD fixes the bug:3545197, RM can return NV_ERR_NOT_SUPPORTED return NV_OK; } @@ -939,7 +943,7 @@ { NV2080_CTRL_BUS_INFO busInfo = {0}; NV_STATUS rmStatus = NV_OK; - + busInfo.index = NV2080_CTRL_BUS_INFO_INDEX_PCIE_GEN_INFO; if ((rmStatus = kbusSendBusInfo(pGpu, GPU_GET_KERNEL_BUS(pGpu), &busInfo)) != NV_OK) @@ -1117,3 +1121,40 @@ pBusInfo->data = data; return NV_OK; } + +/*! + * @brief To ensure GPU is back on bus and accessible by polling device ID + * + * @param[in] pGpu GPU object pointer + * @param[in] pKernelBif Kernel BIF object pointer + * + * @returns NV_OK + * @returns NV_ERR_TIMEOUT + */ +NV_STATUS +kbifPollDeviceOnBus_IMPL +( + OBJGPU *pGpu, + KernelBif *pKernelBif +) +{ + RMTIMEOUT timeout; + + gpuSetTimeout(pGpu, GPU_TIMEOUT_DEFAULT, &timeout, 0); + + while (osPciInitHandle(gpuGetDomain(pGpu), + gpuGetBus(pGpu), + gpuGetDevice(pGpu), 0, NULL, NULL) == NULL) + { + if (gpuCheckTimeout(pGpu, &timeout) == NV_ERR_TIMEOUT) + { + NV_PRINTF(LEVEL_ERROR, "Timeout polling GPU back on bus\n"); + DBG_BREAKPOINT(); + return NV_ERR_TIMEOUT; + } + osDelayUs(100); + } + + return NV_OK; +} + diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/kernel/gpu/bus/arch/ampere/kern_bus_ga100.c nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/kernel/gpu/bus/arch/ampere/kern_bus_ga100.c --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/kernel/gpu/bus/arch/ampere/kern_bus_ga100.c 2023-10-25 20:20:53.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/kernel/gpu/bus/arch/ampere/kern_bus_ga100.c 2024-03-05 22:13:15.000000000 +0000 @@ -21,6 +21,9 @@ * DEALINGS IN THE SOFTWARE. */ +// FIXME XXX +#define NVOC_KERNEL_NVLINK_H_PRIVATE_ACCESS_ALLOWED + #include "core/core.h" #include "gpu/gpu.h" @@ -30,6 +33,7 @@ #include "gpu/mmu/kern_gmmu.h" #include "gpu/device/device.h" #include "gpu/mem_mgr/mem_mgr.h" +#include "gpu/bus/p2p_api.h" #include "kernel/gpu/mig_mgr/kernel_mig_manager.h" #include "kernel/gpu/nvlink/kernel_nvlink.h" #include "rmapi/rmapi.h" @@ -74,7 +78,7 @@ //Allocate the client in RM which owns the FLAVASpace status = pRmApi->AllocWithHandle(pRmApi, NV01_NULL_OBJECT, NV01_NULL_OBJECT, NV01_NULL_OBJECT, - NV01_ROOT, &pKernelBus->flaInfo.hClient); + NV01_ROOT, &pKernelBus->flaInfo.hClient, sizeof(pKernelBus->flaInfo.hClient)); NV_ASSERT_OR_RETURN(status == NV_OK, status); status = serverGetClientUnderLock(&g_resServ, pKernelBus->flaInfo.hClient, &pClient); @@ -87,7 +91,7 @@ nv0080AllocParams.deviceId = gpuGetDeviceInstance(pGpu); status = pRmApi->AllocWithHandle(pRmApi, pKernelBus->flaInfo.hClient, pKernelBus->flaInfo.hClient, pKernelBus->flaInfo.hDevice, NV01_DEVICE_0, - &nv0080AllocParams); + &nv0080AllocParams, sizeof(nv0080AllocParams)); if (status != NV_OK) { @@ -104,7 +108,7 @@ status = pRmApi->AllocWithHandle(pRmApi, pKernelBus->flaInfo.hClient, pKernelBus->flaInfo.hDevice, pKernelBus->flaInfo.hSubDevice, NV20_SUBDEVICE_0, - &nv2080AllocParams); + &nv2080AllocParams, sizeof(nv2080AllocParams)); if (status != NV_OK) { @@ -138,7 +142,7 @@ // Allocate a FERMI_VASPACE_A object and associate it with hFlaVASpace status = pRmApi->AllocWithHandle(pRmApi, pKernelBus->flaInfo.hClient, pKernelBus->flaInfo.hDevice, pKernelBus->flaInfo.hFlaVASpace, FERMI_VASPACE_A, - &vaParams); + &vaParams, sizeof(vaParams)); if (bAcquireLock) { NV_ASSERT_OK_OR_CAPTURE_FIRST_ERROR(status, @@ -325,7 +329,7 @@ if (pGpu->pFabricVAS != NULL) { NV_ASSERT_OK_OR_GOTO(status, fabricvaspaceInitUCRange( - dynamicCast(pGpu->pFabricVAS, FABRIC_VASPACE), pGpu, + dynamicCast(pGpu->pFabricVAS, FABRIC_VASPACE), pGpu, base, size), free_instblk); } @@ -516,7 +520,7 @@ if (pGpu->pFabricVAS != NULL) { NV_ASSERT_OK_OR_GOTO(status, fabricvaspaceInitUCRange( - dynamicCast(pGpu->pFabricVAS, FABRIC_VASPACE), pGpu, + dynamicCast(pGpu->pFabricVAS, FABRIC_VASPACE), pGpu, base, size), free_instblk); } @@ -548,8 +552,8 @@ return status; } -/*! - * Top level function to check if the platform supports FLA, and initialize if +/*! + * Top level function to check if the platform supports FLA, and initialize if * supported. This function gets called in all the platforms where Nvlink is enabled. * * @param[in] base VASpace base @@ -604,7 +608,7 @@ } /*! - * @brief Determine FLA Base and Size for NvSwitch Virtualization systems + * @brief Determine FLA Base and Size for NvSwitch Virtualization systems * from reading the scratch registers. This determines FLA base and size * GA100 direct connected systems as well as skip allocation of FLA Vaspace * for vgpu host. @@ -1012,11 +1016,13 @@ KernelBus *pKernelBus0, OBJGPU *pGpu1, KernelBus *pKernelBus1, - NvU32 *nvlinkPeer + NvU32 *nvlinkPeer, + NvU32 attributes ) { KernelNvlink *pKernelNvlink0 = GPU_GET_KERNEL_NVLINK(pGpu0); NV_STATUS status = NV_OK; + NvBool bEgmPeer = FLD_TEST_DRF(_P2PAPI, _ATTRIBUTES, _REMOTE_EGM, _YES, attributes); if (nvlinkPeer == NULL) { @@ -1035,8 +1041,8 @@ // If NVLINK topology is forced and the forced configuration has peer links, // get the peer ID from the table // - if (knvlinkIsForcedConfig(pGpu0, pKernelNvlink0) || - pKernelNvlink0->bRegistryLinkOverride) + if ((knvlinkIsForcedConfig(pGpu0, pKernelNvlink0) || + pKernelNvlink0->bRegistryLinkOverride) && !bEgmPeer) { if (knvlinkGetPeersNvlinkMaskFromHshub(pGpu0, pKernelNvlink0) != 0) { @@ -1064,7 +1070,15 @@ } // Return if a peer ID is already allocated for P2P from pGpu0 to pGpu1 - *nvlinkPeer = kbusGetPeerId_HAL(pGpu0, pKernelBus0, pGpu1); + if (bEgmPeer) + { + *nvlinkPeer = kbusGetEgmPeerId_HAL(pGpu0, pKernelBus0, pGpu1); + } + else + { + *nvlinkPeer = kbusGetPeerId_HAL(pGpu0, pKernelBus0, pGpu1); + } + if (*nvlinkPeer != BUS_INVALID_PEER) { return NV_OK; @@ -1080,8 +1094,7 @@ // 2. Mix of direct NVLink and NVSwitch connections is supported // None of the above hold true currently // - if ((pGpu0 == pGpu1) || - knvlinkIsGpuConnectedToNvswitch(pGpu0, pKernelNvlink0)) + if (((pGpu0 == pGpu1) && !bEgmPeer) || knvlinkIsGpuConnectedToNvswitch(pGpu0, pKernelNvlink0)) { *nvlinkPeer = 0; @@ -1110,6 +1123,12 @@ // Reserve the peer ID for NVLink use status = kbusReserveP2PPeerIds_HAL(pGpu0, pKernelBus0, NVBIT(*nvlinkPeer)); + if ((status == NV_OK) && + !knvlinkIsGpuConnectedToNvswitch(pGpu0, pKernelNvlink0)) + { + pKernelBus0->p2p.bEgmPeer[*nvlinkPeer] = bEgmPeer; + } + return status; } diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/kernel/gpu/bus/arch/hopper/kern_bus_gh100.c nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/kernel/gpu/bus/arch/hopper/kern_bus_gh100.c --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/kernel/gpu/bus/arch/hopper/kern_bus_gh100.c 2023-10-25 20:20:53.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/kernel/gpu/bus/arch/hopper/kern_bus_gh100.c 2024-03-05 22:13:15.000000000 +0000 @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 2021-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2021-2024 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -32,6 +32,7 @@ #include "gpu/mem_mgr/mem_mgr.h" #include "gpu/mem_sys/kern_mem_sys.h" #include "kernel/gpu/nvlink/kernel_nvlink.h" +#include "kernel/gpu/mem_mgr/virt_mem_allocator_common.h" #include "mem_mgr/fabric_vaspace.h" #include "mem_mgr/virt_mem_mgr.h" #include "vgpu/rpc.h" @@ -56,6 +57,9 @@ ((HOPPER_WRITE_MAILBOX_SIZE << kbusGetP2PWriteMailboxAddressSize_HAL(pGpu)) - \ HOPPER_WRITE_MAILBOX_SIZE) +// RM reserved memory region is mapped separately as it is not added to the kernel +#define COHERENT_CPU_MAPPING_RM_RESV_REGION COHERENT_CPU_MAPPING_REGION_1 + /*! * @brief Gets the P2P write mailbox address size (NV_XAL_EP_P2P_WMBOX_ADDR_ADDR) * @@ -118,7 +122,7 @@ NvBool kbusValidateBAR0WindowBase_GH100 ( - OBJGPU *pGpu, + OBJGPU *pGpu, KernelBus *pKernelBus, NvU32 base ) @@ -134,6 +138,11 @@ NvU64 vidOffset ) { + if (KBUS_BAR0_PRAMIN_DISABLED(pGpu)) + { + NV_ASSERT_FAILED("kbusSetBAR0WindowVidOffset_HAL call in coherent path\n"); + return NV_ERR_INVALID_STATE; + } NV_ASSERT((vidOffset & 0xffff)==0); NV_ASSERT(kbusValidateBAR0WindowBase_HAL(pGpu, pKernelBus, vidOffset >> NV_XAL_EP_BAR0_WINDOW_BASE_SHIFT)); @@ -231,7 +240,7 @@ NvU32 flagsClean = 0; NvU64 bar2VirtualAddr = 0; - NV_ASSERT_OR_RETURN(pGpu->getProperty(pGPU, PDB_PROP_GPU_COHERENT_CPU_MAPPING) == NV_FALSE, NV_ERR_INVALID_STATE); + NV_ASSERT_OR_RETURN(pGpu->getProperty(pGpu, PDB_PROP_GPU_COHERENT_CPU_MAPPING) == NV_FALSE, NV_ERR_INVALID_STATE); // // kbusVerifyBar2 will test BAR0 against sysmem on Tegra; otherwise skip @@ -572,7 +581,8 @@ } else { - if (pKernelBus->virtualBar2[gfid].pPageLevels) + if (pKernelBus->virtualBar2[gfid].pPageLevels != NULL && + pKernelBus->virtualBar2[gfid].pPageLevelsMemDesc != NULL) { memmgrMemDescEndTransfer(GPU_GET_MEMORY_MANAGER(pGpu), pKernelBus->virtualBar2[gfid].pPageLevelsMemDesc, @@ -858,6 +868,508 @@ } /*! + * @brief Create C2C mappings for FB memory + * When this is called, we should not have any BAR1/BAR2 mappings + * + * @param[in] pGpu OBJGPU pointer + * @param[in] pKernelBus Kernel bus pointer + * @param[in] numaOnlineMemorySize Size of FB memory to online in + * kernel as a NUMA node + * @param[in] bFlush Flush CPU cache or not + * + * @return 'NV_OK' if successful, an RM error code otherwise. + */ +NV_STATUS +kbusCreateCoherentCpuMapping_GH100 +( + OBJGPU *pGpu, + KernelBus *pKernelBus, + NvU64 numaOnlineMemorySize, + NvBool bFlush +) +{ + MemoryManager *pMemoryManager = GPU_GET_MEMORY_MANAGER(pGpu); + KernelMemorySystem *pKernelMemorySystem = GPU_GET_KERNEL_MEMORY_SYSTEM(pGpu); + NV_STATUS status = NV_OK; + KernelBif *pKernelBif = GPU_GET_KERNEL_BIF(pGpu); + NvP64 pCpuMapping = NvP64_NULL; + NvU64 fbSize; + NvU64 busAddrStart; + NvU64 busAddrSize; + NvU32 i; + NvU64 memblockSize; + NvU32 cachingMode[COHERENT_CPU_MAPPING_TOTAL_REGIONS]; + + NV_ASSERT_OR_RETURN(gpuIsSelfHosted(pGpu) && pKernelBif->getProperty(pKernelBif, PDB_PROP_KBIF_IS_C2C_LINK_UP), NV_ERR_INVALID_STATE); + + // Assert no BAR1/BAR2 mappings + NV_ASSERT_OR_RETURN(kbusGetBar1VASpace_HAL(pGpu, pKernelBus) == NULL, + NV_ERR_INVALID_STATE); + NV_ASSERT_OR_RETURN(listCount(&pKernelBus->virtualBar2[GPU_GFID_PF].usedMapList) == 0, + NV_ERR_INVALID_STATE); + + fbSize = (pMemoryManager->Ram.fbTotalMemSizeMb << 20); + + NV_ASSERT_OK_OR_RETURN(osNumaMemblockSize(&memblockSize)); + + pKernelBus->coherentCpuMapping.nrMapping = 2; + + pKernelBus->coherentCpuMapping.physAddr[COHERENT_CPU_MAPPING_REGION_0] = pMemoryManager->Ram.fbRegion[0].base; + pKernelBus->coherentCpuMapping.size[COHERENT_CPU_MAPPING_REGION_0] = numaOnlineMemorySize; + cachingMode[COHERENT_CPU_MAPPING_REGION_0] = NV_MEMORY_CACHED; + + pKernelBus->coherentCpuMapping.physAddr[COHERENT_CPU_MAPPING_RM_RESV_REGION] = + pKernelBus->coherentCpuMapping.physAddr[COHERENT_CPU_MAPPING_REGION_0] + + pKernelBus->coherentCpuMapping.size[COHERENT_CPU_MAPPING_REGION_0]; + pKernelBus->coherentCpuMapping.size[COHERENT_CPU_MAPPING_RM_RESV_REGION] = + fbSize - pKernelBus->coherentCpuMapping.size[COHERENT_CPU_MAPPING_REGION_0]; + + if (pKernelMemorySystem->bBug3656943WAR) + { + // + // RM reserved region should be mapped as Normal Non-cacheable as a SW WAR + // for the bug 3656943. NV_MEMORY_WRITECOMBINED translates to linux + // kernel ioremap_wc which actually uses the normal non-cacheable type + // PROT_NORMAL_NC + // + cachingMode[COHERENT_CPU_MAPPING_RM_RESV_REGION] = NV_MEMORY_WRITECOMBINED; + } + else + { + cachingMode[COHERENT_CPU_MAPPING_RM_RESV_REGION] = NV_MEMORY_CACHED; + } + + for (i = COHERENT_CPU_MAPPING_REGION_0; i < pKernelBus->coherentCpuMapping.nrMapping; ++i) + { + busAddrStart = pKernelMemorySystem->coherentCpuFbBase + pKernelBus->coherentCpuMapping.physAddr[i]; + busAddrSize = pKernelBus->coherentCpuMapping.size[i]; + + // In SHH, CPU uses coherent C2C link to access GPU memory and hence it can be accessed cached. + status = osMapPciMemoryKernel64(pGpu, + (NvUPtr)busAddrStart, + (NvU64)busAddrSize, + NV_PROTECT_READ_WRITE, + &(pCpuMapping), + cachingMode[i]); + + NV_ASSERT_OR_RETURN(status == NV_OK, NV_ERR_GENERIC); + + pKernelBus->coherentCpuMapping.pCpuMapping[i] = (NvP64)pCpuMapping; + pKernelBus->coherentCpuMapping.size[i] = busAddrSize; + + NV_ASSERT_OR_RETURN(bFlush == NV_FALSE, NV_ERR_NOT_SUPPORTED); + + // Counts the number of outstanding mappings in FB. + pKernelBus->coherentCpuMapping.refcnt[i] = 0; + } + + pKernelBus->coherentCpuMapping.bCoherentCpuMapping = NV_TRUE; + + NV_PRINTF(LEVEL_INFO, "Enabling CPU->C2C->FBMEM path\n"); + + return status; +} + +/*! + * @brief Sanity test coherent link between CPU and GPU. + * + * @param[in] pGpu OBJGPU pointer + * @param[in] pKernelBus Kernel bus pointer + * + * @returns NV_OK on success. + */ +NV_STATUS +kbusVerifyCoherentLink_GH100 +( + OBJGPU *pGpu, + KernelBus *pKernelBus +) +{ + NvU64 size = BUS_COHERENT_LINK_TEST_BUFFER_SIZE; + MEMORY_DESCRIPTOR *pMemDesc = NULL; + NvU8 *pOffset = NULL; + const NvU32 sampleData = 0x12345678; + NV_STATUS status = NV_OK; + KernelMemorySystem *pKernelMemorySystem = GPU_GET_KERNEL_MEMORY_SYSTEM(pGpu); + NvU32 index = 0; + NvU32 flagsClean = 0; + MEMORY_DESCRIPTOR memDesc; + + // Skip the test if 0FB configuration is used. + if (pGpu->getProperty(pGpu, PDB_PROP_GPU_IS_ALL_INST_IN_SYSMEM)) + { + NV_PRINTF(IS_EMULATION(pGpu) ? LEVEL_ERROR : LEVEL_INFO, + "Skipping Coherent link test\n"); + return NV_OK; + } + + NV_ASSERT_OR_RETURN(pKernelBus->coherentLinkTestBufferBase != 0, NV_ERR_INVALID_STATE); + memdescCreateExisting(&memDesc, pGpu, size, ADDR_FBMEM, NV_MEMORY_CACHED, MEMDESC_FLAGS_NONE); + memdescDescribe(&memDesc, ADDR_FBMEM, pKernelBus->coherentLinkTestBufferBase, size); + + pOffset = kbusMapRmAperture_HAL(pGpu, &memDesc); + if (pOffset == NULL) + { + status = NV_ERR_INSUFFICIENT_RESOURCES; + goto busVerifyCoherentLink_failed; + } + pMemDesc = &memDesc; + + for(index = 0; index < size; index += 4) + { + MEM_WR32(pOffset + index, sampleData); + } + + // Ensure the writes are flushed out of the CPU caches. + osFlushGpuCoherentCpuCacheRange(pGpu->pOsGpuInfo, (NvUPtr)pOffset, size); + + flagsClean = NV2080_CTRL_INTERNAL_MEMSYS_L2_INVALIDATE_EVICT_FLAGS_ALL | + NV2080_CTRL_INTERNAL_MEMSYS_L2_INVALIDATE_EVICT_FLAGS_CLEAN; + if (kmemsysIsL2CleanFbPull(pKernelMemorySystem)) + { + flagsClean |= NV2080_CTRL_INTERNAL_MEMSYS_L2_INVALIDATE_EVICT_FLAGS_WAIT_FB_PULL; + } + status = kmemsysSendL2InvalidateEvict(pGpu, pKernelMemorySystem, flagsClean); + if (NV_OK != status) + { + NV_PRINTF(LEVEL_ERROR, "L2 evict failed\n"); + goto busVerifyCoherentLink_failed; + } + + for(index = 0; index < size; index += 4) + { + NvU32 readbackData = MEM_RD32(pOffset + index); + + if (readbackData != sampleData) + { + NV_PRINTF(LEVEL_ERROR, + "Coherent Link test readback VA = 0x%llx returned garbage 0x%x\n", + (NvUPtr)(pOffset + index), readbackData); + + DBG_BREAKPOINT_REASON(NV_ERR_MEMORY_ERROR); + status = NV_ERR_GENERIC; + } + } + +busVerifyCoherentLink_failed: + if (pOffset != NULL) + { + kbusUnmapRmAperture_HAL(pGpu, pMemDesc, &pOffset, NV_TRUE); + } + memdescDestroy(pMemDesc); + + if (status == NV_OK) + { + NV_PRINTF(IS_EMULATION(pGpu) ? LEVEL_ERROR : LEVEL_INFO, + "Coherent link test passes\n"); + } + + return status; + +} + +/** + * @brief Setup BAR1 P2P capability property. + * All Hopper+ are BAR1 P2P capable. + * + * @param pGpu + * @param pBus + * + * @return void + */ +void kbusSetupBar1P2PCapability_GH100 +( + OBJGPU *pGpu, + KernelBus *pKernelBus +) +{ + NvU64 bar1Size = kbusGetPciBarSize(pKernelBus, 1); + MemoryManager *pMemoryManager = GPU_GET_MEMORY_MANAGER(pGpu); + NvU64 fbSize = pMemoryManager->Ram.fbUsableMemSize; + + // Make sure the BAR1 size is big enough to cover all FB + if((bar1Size >= fbSize) && (fbSize != 0)) + { + NV_PRINTF(LEVEL_INFO, "The gpu %d is BAR1 P2P capable.\n", pGpu->gpuInstance); + kbusSetBar1P2pCapable(pKernelBus, NV_TRUE); + } + else + { + NV_PRINTF(LEVEL_INFO, "The gpu %d is not BAR1 P2P capable.\n", pGpu->gpuInstance); + kbusSetBar1P2pCapable(pKernelBus, NV_FALSE); + } +} + +/*! + * @brief check if it can support BAR1 P2P between the GPUs + * At the point this function is called, the system do not support C2C and + * NVLINK P2P and the BAR1 P2P is the preferred option. + * + * @param[in] pGpu0 (local GPU) + * @param[in] pKernelBus0 (local GPU) + * @param[in] pGpu1 (remote GPU) + * @param[in] pKernelBus1 (remote GPU) + * + * return NV_TRUE if the GPU support BAR1 P2P + */ +NvBool +kbusIsPcieBar1P2PMappingSupported_GH100 +( + OBJGPU *pGpu0, + KernelBus *pKernelBus0, + OBJGPU *pGpu1, + KernelBus *pKernelBus1 +) +{ + NvU32 gpuInst0 = gpuGetInstance(pGpu0); + NvU32 gpuInst1 = gpuGetInstance(pGpu1); + KernelBif *pKernelBif0 = GPU_GET_KERNEL_BIF(pGpu0); + NvU32 gpu0Gfid; + NvU32 gpu1Gfid; + NV_STATUS status = NV_OK; + + // Check if BAR1 P2P is disabled by a regkey + if ((pKernelBif0->forceP2PType != NV_REG_STR_RM_FORCE_P2P_TYPE_DEFAULT) && + (pKernelBif0->forceP2PType != NV_REG_STR_RM_FORCE_P2P_TYPE_BAR1P2P)) + { + return NV_FALSE; + } + + // Not loopback support + if (pGpu0 == pGpu1) + { + return NV_FALSE; + } + + // Both of GPUs need to support BAR1P2P + if (!kbusIsBar1P2PCapable(pKernelBus0) || + !kbusIsBar1P2PCapable(pKernelBus1)) + { + return NV_FALSE; + } + + // + // TODO: To move this check to kbusSetupBar1P2PCapability. It should check bStaticBar1Enabled + // to determine if the GPU is Bar1P2P Capable. + // + NV_ASSERT_OK_OR_ELSE(status, vgpuGetCallingContextGfid(pGpu0, &gpu0Gfid), return NV_FALSE); + NV_ASSERT_OK_OR_ELSE(status, vgpuGetCallingContextGfid(pGpu1, &gpu1Gfid), return NV_FALSE); + if (!pKernelBus0->bar1[gpu0Gfid].bStaticBar1Enabled || + !pKernelBus1->bar1[gpu1Gfid].bStaticBar1Enabled) + { + return NV_FALSE; + } + + // + // RM only supports one type of PCIE P2P protocol, either BAR1 P2P or mailbox P2P, between + // two GPUs at a time. For more info on this topic, please check bug 3274549 comment 10 + // + // Check if there is p2p mailbox connection between the GPUs. + // + if ((pKernelBus0->p2pPcie.peerNumberMask[gpuInst1] != 0) || + (pKernelBus1->p2pPcie.peerNumberMask[gpuInst0] != 0)) + { + return NV_FALSE; + } + + return NV_TRUE; +} + +/*! + * @brief Remove source GPU IOMMU mapping for the peer GPU + * + * @param[in] pSrcGpu The source GPU + * @param[in] pSrcKernelBus The source Kernel Bus + * @param[in] pPeerGpu The peer GPU + * + * @returns void + */ +static void +_kbusRemoveStaticBar1IOMMUMapping +( + OBJGPU *pSrcGpu, + KernelBus *pSrcKernelBus, + OBJGPU *pPeerGpu, + KernelBus *pPeerKernelBus +) +{ + NvU32 peerGfid; + + NV_CHECK_OR_RETURN_VOID(LEVEL_ERROR, + vgpuGetCallingContextGfid(pPeerGpu, &peerGfid) == NV_OK); + + NV_ASSERT_OR_RETURN_VOID(pPeerKernelBus->bar1[peerGfid].staticBar1.pDmaMemDesc != NULL); + + memdescUnmapIommu(pPeerKernelBus->bar1[peerGfid].staticBar1.pDmaMemDesc, + pSrcGpu->busInfo.iovaspaceId); +} + +/*! + * @brief Remove GPU IOMMU mapping between the pair of GPUs + * + * @param[in] pGpu0 + * @param[in] pKernelBus0 + * @param[in] pGpu1 + * @param[in] pKernelBus0 + * + * @returns void + */ +static void +_kbusRemoveStaticBar1IOMMUMappingForGpuPair +( + OBJGPU *pGpu0, + KernelBus *pKernelBus0, + OBJGPU *pGpu1, + KernelBus *pKernelBus1 +) +{ + _kbusRemoveStaticBar1IOMMUMapping(pGpu0, pKernelBus0, pGpu1, pKernelBus1); + _kbusRemoveStaticBar1IOMMUMapping(pGpu1, pKernelBus1, pGpu0, pKernelBus0); +} + +/*! + * @brief Create source GPU IOMMU mapping for the peer GPU + * + * @param[in] pSrcGpu The source GPU + * @param[in] pSrcKernelBus The source Kernel Bus + * @param[in] pPeerGpu The peer GPU + * @param[in] pPeerKernelBus The peer Kernel Bus + * + * @returns NV_OK on success + */ +static NV_STATUS +_kbusCreateStaticBar1IOMMUMapping +( + OBJGPU *pSrcGpu, + KernelBus *pSrcKernelBus, + OBJGPU *pPeerGpu, + KernelBus *pPeerKernelBus +) +{ + NvU32 peerGpuGfid; + MEMORY_DESCRIPTOR *pPeerDmaMemDesc = NULL; + RmPhysAddr peerDmaAddr; + + NV_ASSERT_OK_OR_RETURN(vgpuGetCallingContextGfid(pPeerGpu, &peerGpuGfid)); + + pPeerDmaMemDesc = pPeerKernelBus->bar1[peerGpuGfid].staticBar1.pDmaMemDesc; + + NV_ASSERT_OR_RETURN(pPeerDmaMemDesc != NULL, NV_ERR_INVALID_STATE); + + // Create the source GPU IOMMU mapping on the peer static bar1 + NV_ASSERT_OK_OR_RETURN(memdescMapIommu(pPeerDmaMemDesc, + pSrcGpu->busInfo.iovaspaceId)); + + // To get the peer DMA address of the memory for the GPU was mapped to + memdescGetPhysAddrsForGpu(pPeerDmaMemDesc, pSrcGpu, + AT_GPU, 0, 0, 1, &peerDmaAddr); + + // Check the if it is aligned to max RM_PAGE_SIZE 512M. + if (!NV_IS_ALIGNED64(peerDmaAddr, RM_PAGE_SIZE_512M)) + { + NV_PRINTF(LEVEL_ERROR, "The peer DMA address 0x%llx is not aligned at 0x%llx\n", + peerDmaAddr, RM_PAGE_SIZE_512M); + + memdescUnmapIommu(pPeerDmaMemDesc, pSrcGpu->busInfo.iovaspaceId); + + return NV_ERR_INVALID_ADDRESS; + } + + return NV_OK; +} + +/*! + * @brief To create IOMMU mapping between the pair of GPUs + * + * @param[in] pGpu0 + * @param[in] pKernelBus0 + * @param[in] pGpu1 + * @param[in] pKernelBus0 + * + * @returns NV_OK on success + */ +static NV_STATUS +_kbusCreateStaticBar1IOMMUMappingForGpuPair +( + OBJGPU *pGpu0, + KernelBus *pKernelBus0, + OBJGPU *pGpu1, + KernelBus *pKernelBus1 +) +{ + NvU32 gpuInst0 = gpuGetInstance(pGpu0); + NvU32 gpuInst1 = gpuGetInstance(pGpu1); + NV_STATUS status; + + // Create GPU0 IOMMU mapping to GPU1 BAR1 + status = _kbusCreateStaticBar1IOMMUMapping(pGpu0, pKernelBus0, pGpu1, pKernelBus1); + if (status != NV_OK) + { + NV_PRINTF(LEVEL_ERROR, "IOMMU mapping failed from GPU%u to GPU%u\n", + gpuInst0, gpuInst1); + return status; + } + + // Create GPU1 IOMMU mapping to GPU0 BAR1 + status = _kbusCreateStaticBar1IOMMUMapping(pGpu1, pKernelBus1, pGpu0, pKernelBus0); + if (status != NV_OK) + { + NV_PRINTF(LEVEL_ERROR, "IOMMU mapping failed from GPU%u to GPU%u\n", + gpuInst1, gpuInst0); + + // Remove the previous created IOMMU mapping + _kbusRemoveStaticBar1IOMMUMapping(pGpu0, pKernelBus0, pGpu1, pKernelBus1); + } + + return status; +} + +/*! + * @brief To get the DMA information from the source GPU to the peer GPU + * + * @param[in] pSrcGpu The source GPU + * @param[in] pPeerGpu The peer GPU + * @param[in] pPeerKernelBus The peer Kernel Bus + * @param[out] pDmaAddress The start DMA address for the source GPU + * to access the peer GPU + * @param[out] pDmaSize The size of the DMA transfer range + * + * @returns NV_OK on success + */ +NV_STATUS kbusGetBar1P2PDmaInfo_GH100 +( + OBJGPU *pSrcGpu, + OBJGPU *pPeerGpu, + KernelBus *pPeerKernelBus, + NvU64 *pDmaAddress, + NvU64 *pDmaSize +) +{ + NvU32 peerGfid; + MEMORY_DESCRIPTOR *pPeerDmaMemDesc; + + NV_ASSERT_OR_RETURN((pDmaAddress != NULL) && (pDmaSize != NULL), + NV_ERR_INVALID_ARGUMENT); + + // Set the default value + *pDmaAddress = NV_U64_MAX; + *pDmaSize = 0; + + NV_ASSERT_OK_OR_RETURN(vgpuGetCallingContextGfid(pPeerGpu, &peerGfid)); + + pPeerDmaMemDesc = pPeerKernelBus->bar1[peerGfid].staticBar1.pDmaMemDesc; + NV_ASSERT_OR_RETURN(pPeerDmaMemDesc != NULL, NV_ERR_NOT_SUPPORTED); + + // Get the peer GPU DMA address for the source GPU + memdescGetPhysAddrsForGpu(pPeerDmaMemDesc, pSrcGpu, + AT_GPU, 0, 0, 1, pDmaAddress); + + *pDmaSize = memdescGetSize(pPeerDmaMemDesc); + + return NV_OK; +} + +/*! * @brief check if there is BAR1 P2P mapping between given GPUs * * @param[in] pGpu0 (local GPU) @@ -876,8 +1388,8 @@ KernelBus *pKernelBus1 ) { - return (pKernelBus0->p2pPcieBar1.busBar1PeerRefcount[gpuGetInstance(pGpu1)] != 0 && - pKernelBus1->p2pPcieBar1.busBar1PeerRefcount[gpuGetInstance(pGpu0)] != 0); + return ((pKernelBus0->p2pPcieBar1.busBar1PeerRefcount[gpuGetInstance(pGpu1)] != 0) && + (pKernelBus1->p2pPcieBar1.busBar1PeerRefcount[gpuGetInstance(pGpu0)] != 0)); } /*! @@ -904,6 +1416,7 @@ { NvU32 gpuInst0 = gpuGetInstance(pGpu0); NvU32 gpuInst1 = gpuGetInstance(pGpu1); + NV_STATUS status = NV_OK; if (IS_VIRTUAL(pGpu0) || IS_VIRTUAL(pGpu1)) { @@ -915,13 +1428,21 @@ return NV_ERR_NOT_SUPPORTED; } + // Only create IOMMU mapping between the pair of GPUs at the first time. + if ((pKernelBus0->p2pPcieBar1.busBar1PeerRefcount[gpuInst1] == 0) && + (pKernelBus1->p2pPcieBar1.busBar1PeerRefcount[gpuInst0] == 0)) + { + NV_ASSERT_OK_OR_RETURN(_kbusCreateStaticBar1IOMMUMappingForGpuPair(pGpu0, pKernelBus0, + pGpu1, pKernelBus1)); + } + pKernelBus0->p2pPcieBar1.busBar1PeerRefcount[gpuInst1]++; pKernelBus1->p2pPcieBar1.busBar1PeerRefcount[gpuInst0]++; NV_PRINTF(LEVEL_INFO, "added PCIe BAR1 P2P mapping between GPU%u and GPU%u\n", gpuInst0, gpuInst1); - return NV_OK; + return status; } /*! @@ -955,8 +1476,8 @@ gpuInst0 = gpuGetInstance(pGpu0); gpuInst1 = gpuGetInstance(pGpu1); - if ( (pKernelBus0->p2pPcieBar1.busBar1PeerRefcount[gpuInst1] == 0) || - (pKernelBus1->p2pPcieBar1.busBar1PeerRefcount[gpuInst0] == 0) ) + if ((pKernelBus0->p2pPcieBar1.busBar1PeerRefcount[gpuInst1] == 0) || + (pKernelBus1->p2pPcieBar1.busBar1PeerRefcount[gpuInst0] == 0)) { return NV_ERR_INVALID_STATE; } @@ -964,9 +1485,15 @@ pKernelBus0->p2pPcieBar1.busBar1PeerRefcount[gpuInst1]--; pKernelBus1->p2pPcieBar1.busBar1PeerRefcount[gpuInst0]--; - NV_PRINTF(LEVEL_INFO, - "removed PCIe BAR1 P2P mapping between GPU%u and GPU%u\n", - gpuInst0, gpuInst1); + // Only remove the IOMMU mapping between the pair of GPUs when it is the last mapping. + if ((pKernelBus0->p2pPcieBar1.busBar1PeerRefcount[gpuInst1] == 0) && + (pKernelBus1->p2pPcieBar1.busBar1PeerRefcount[gpuInst0] == 0)) + { + _kbusRemoveStaticBar1IOMMUMappingForGpuPair(pGpu0, pKernelBus0, pGpu1, pKernelBus1); + } + + NV_PRINTF(LEVEL_INFO, "removed PCIe BAR1 P2P mapping between GPU%u and GPU%u\n", + gpuInst0, gpuInst1); return NV_OK; } @@ -1232,6 +1759,419 @@ return status; } +NvBool +kbusNeedStaticBar1Mapping_GH100(OBJGPU *pGpu, KernelBus *pKernelBus) +{ + KernelBif *pKernelBif = GPU_GET_KERNEL_BIF(pGpu); + + // Check if BAR1 P2P is enabled by a regkey + if (pKernelBif->forceP2PType != NV_REG_STR_RM_FORCE_P2P_TYPE_BAR1P2P) + { + return NV_FALSE; + } + + // We need static Bar1 only when the GPU is BAR1 P2P capable. + return kbusIsBar1P2PCapable(pKernelBus); +} + +/*! + * @brief Setup static Bar1 mapping. + * + * @param[in] pGpu GPU pointer + * @param[in] pKernelBus Kernel bus pointer + * @param[in] reservedFbSize The size to reserve in FB from the address 0 + * @param[in] gfid The GFID + * + * @returns NV_OK on success, or rm_status from called functions on failure. + */ +NV_STATUS +kbusEnableStaticBar1Mapping_GH100 +( + OBJGPU *pGpu, + KernelBus *pKernelBus, + NvU64 reservedFbSize, + NvU32 gfid +) +{ + MemoryManager *pMemoryManager = GPU_GET_MEMORY_MANAGER(pGpu); + MEMORY_DESCRIPTOR *pMemDesc = NULL; + MEMORY_DESCRIPTOR *pDmaMemDesc = NULL; + NvU64 bar1Size = kbusGetPciBarSize(pKernelBus, 1); + NV_STATUS status = NV_OK; + OBJEHEAP *pVASpaceHeap = vaspaceGetHeap(pKernelBus->bar1[gfid].pVAS); + NvU64 bar1Offset = RM_ALIGN_UP(reservedFbSize, RM_PAGE_SIZE_2M); + NvU64 bar1MapSize; + NvU64 staticBar1PhyAddr; + + if (!kbusNeedStaticBar1Mapping_HAL(pGpu, pKernelBus)) + { + return NV_ERR_INVALID_STATE; + } + + NV_PRINTF(LEVEL_INFO, "Static bar1 size 0x%llx fb size 0x%llx\n", + bar1Size, pMemoryManager->Ram.fbUsableMemSize); + + // BAR1 VA size can be smaller than BAR1 size + bar1MapSize = NV_MIN(bar1Size, pVASpaceHeap->rangeHi); + bar1MapSize = NV_MIN(bar1MapSize, pMemoryManager->Ram.fbUsableMemSize); + + NV_ASSERT_OR_RETURN(bar1MapSize > bar1Offset, NV_ERR_INVALID_STATE); + + // Adjust the offset + bar1MapSize -= bar1Offset; + + // + // GPU BAR1 VA also supports the SYSMEM mapping, we need to reserve some + // spaces for such cases, like doorbell mapping which is not backed by + // FBMEM. + // + if ((bar1Size - (bar1MapSize + bar1Offset)) < (4 * RM_PAGE_SIZE_2M)) + { + // + // When BAR1 size much bigger than FB, then there are plenty of + // VA space left for other type of mapping. + // When BAR1 size is slightly bigger or equal FB, the available + // BAR1 VA is very limited. + // Here reserves 4 * 2MB blocks. + // !!! NOTE: Not sure how big Rm need to reserve + // TODO: Need to find a better solution, bug 3869651 + // + bar1MapSize -= 4 * RM_PAGE_SIZE_2M; + + NV_PRINTF(LEVEL_INFO, "Static bar1 reserved 8 MB from the top of FB\n"); + } + + // align to 2MB page size + bar1MapSize = RM_ALIGN_UP(bar1MapSize, RM_PAGE_SIZE_2M); + + // + // The static mapping is not backed by an allocated physical FB. + // Here RM describes the memory for the static mapping. + // + NV_ASSERT_OK_OR_RETURN(memdescCreate(&pMemDesc, pGpu, bar1MapSize, 0, + NV_MEMORY_CONTIGUOUS, ADDR_FBMEM, + NV_MEMORY_UNCACHED, MEMDESC_FLAGS_NONE)); + + memdescDescribe(pMemDesc, ADDR_FBMEM, bar1Offset, bar1MapSize); + + // Set to use RM_PAGE_SIZE_HUGE, 2MB + memdescSetPageSize(pMemDesc, AT_GPU, RM_PAGE_SIZE_HUGE); + + // Setup GMK PTE type for this memory + memdescSetPteKind(pMemDesc, NV_MMU_PTE_KIND_GENERIC_MEMORY); + + // Deploy the static mapping. + NV_ASSERT_OK_OR_GOTO(status, + kbusMapFbAperture_HAL(pGpu, pKernelBus, pMemDesc, 0, + &bar1Offset, &bar1MapSize, + BUS_MAP_FB_FLAGS_MAP_UNICAST | BUS_MAP_FB_FLAGS_MAP_OFFSET_FIXED, + NV01_NULL_OBJECT), + cleanup_mem); + + // Get the system physical address the base address of staticBar1 + staticBar1PhyAddr = gpumgrGetGpuPhysFbAddr(pGpu) + bar1Offset; + + // + // Create a memory descriptor to describe a SYSMEM target of the GPU + // BAR1 region. This memDesc will be used for P2P DMA related mapping. + // + NV_ASSERT_OK_OR_GOTO(status, + memdescCreate(&pDmaMemDesc, + pGpu, + bar1MapSize, + 0, + NV_MEMORY_CONTIGUOUS, + ADDR_SYSMEM, + NV_MEMORY_UNCACHED, + MEMDESC_FLAGS_NONE), + cleanup_bus_map); + + memdescDescribe(pDmaMemDesc, ADDR_SYSMEM, staticBar1PhyAddr, bar1MapSize); + + pKernelBus->bar1[gfid].bStaticBar1Enabled = NV_TRUE; + pKernelBus->bar1[gfid].staticBar1.pVidMemDesc = pMemDesc; + pKernelBus->bar1[gfid].staticBar1.pDmaMemDesc = pDmaMemDesc; + pKernelBus->bar1[gfid].staticBar1.base = bar1Offset; + pKernelBus->bar1[gfid].staticBar1.size = bar1MapSize; + + NV_PRINTF(LEVEL_INFO, "Static bar1 mapped offset 0x%llx size 0x%llx\n", + bar1Offset, bar1MapSize); + + return NV_OK; + +cleanup_bus_map: + NV_ASSERT_OK(kbusUnmapFbAperture_HAL(pGpu, pKernelBus, + pMemDesc, bar1Offset, bar1MapSize, + BUS_MAP_FB_FLAGS_MAP_UNICAST | + BUS_MAP_FB_FLAGS_MAP_OFFSET_FIXED)); + +cleanup_mem: + NV_PRINTF(LEVEL_ERROR, "Failed to create the static bar1 mapping offset" + "0x%llx size 0x%llx\n", bar1Offset, bar1MapSize); + + pKernelBus->bar1[gfid].bStaticBar1Enabled = NV_FALSE; + pKernelBus->bar1[gfid].staticBar1.pVidMemDesc = NULL; + pKernelBus->bar1[gfid].staticBar1.pDmaMemDesc = NULL; + + memdescDestroy(pDmaMemDesc); + memdescDestroy(pMemDesc); + + return status; +} + +/*! + * @brief tear down static Bar1 mapping. + * + * @param[in] pGpu GPU pointer + * @param[in] pKernelBus Kernel bus pointer + * @param[in] gfid The GFID + * + * @returns NV_OK on success, or rm_status from called functions on failure. + */ +NV_STATUS +kbusDisableStaticBar1Mapping_GH100(OBJGPU *pGpu, KernelBus *pKernelBus, NvU32 gfid) +{ + if (pKernelBus->bar1[gfid].bStaticBar1Enabled) + { + if (pKernelBus->bar1[gfid].staticBar1.pVidMemDesc != NULL) + { + NV_CHECK_OK_OR_RETURN(LEVEL_ERROR, + kbusUnmapFbAperture_HAL(pGpu, pKernelBus, + pKernelBus->bar1[gfid].staticBar1.pVidMemDesc, + pKernelBus->bar1[gfid].staticBar1.base, + pKernelBus->bar1[gfid].staticBar1.size, + BUS_MAP_FB_FLAGS_MAP_UNICAST | BUS_MAP_FB_FLAGS_MAP_OFFSET_FIXED)); + + memdescDestroy(pKernelBus->bar1[gfid].staticBar1.pVidMemDesc); + + pKernelBus->bar1[gfid].staticBar1.pVidMemDesc = NULL; + } + + memdescDestroy(pKernelBus->bar1[gfid].staticBar1.pDmaMemDesc); + pKernelBus->bar1[gfid].staticBar1.pDmaMemDesc = NULL; + + pKernelBus->bar1[gfid].bStaticBar1Enabled = NV_FALSE; + } + + return NV_OK; +} + +/*! + * @brief To update the StaticBar1 PTE kind for the specified memory. + * + * The staticbar1 only support GMK (generic memory kind) and other compressed kind. + * By default, the bar1 is statically mapped with GMK at boot when the static bar1 is enabled. + * + * When to map a uncompressed kind memory, RM just return the static bar1 address which is mapped + * to the specified memory. + * + * When to map a compressed kind memory, RM must call this function to change the static mapped + * bar1 range to the specified memory from GMK to the compressed kind. And RM needs to + * call this function to change it back to GMK from the compressed kind after this mapping is released. + * + * @param[in] pGpu GPU pointer + * @param[in] pKernelBus Kernel bus pointer + * @param[in] pMemDesc The memory to update + * @param[in] offset The offset of the memory to update + * @param[in] length The length of the memory to update + * @param[in] bRelease Call to release the mapping + * @param[in] gfid The GFID + * + * return NV_OK on success + */ +NV_STATUS +_kbusUpdateStaticBAR1VAMapping_GH100 +( + OBJGPU *pGpu, + KernelBus *pKernelBus, + MEMORY_DESCRIPTOR *pMemDesc, + NvU64 offset, + NvU64 length, + NvBool bRelease, + NvU32 gfid +) +{ + NV_STATUS status = NV_OK; + VirtMemAllocator *pDma = GPU_GET_DMA(pGpu); + MemoryManager *pMemoryManager = GPU_GET_MEMORY_MANAGER(pGpu); + OBJVASPACE *pVAS = pKernelBus->bar1[gfid].pVAS; + NvU32 kind; + MEMORY_DESCRIPTOR *pTempMemDesc; + NvU64 vAddr; + NvU64 vaLo; + NvU64 vaHi; + NvU64 physAddr; + NvU64 pageOffset; + NvU64 mapLength; + NvU64 pageSize; + DMA_PAGE_ARRAY pageArray = {0}; + COMPR_INFO comprInfo; + NvBool bCompressed; + + NV_ASSERT_OR_RETURN(pMemDesc != NULL, NV_ERR_INVALID_ARGUMENT); + + NV_ASSERT_OR_RETURN(memdescGetAddressSpace(pMemDesc) == ADDR_FBMEM, NV_ERR_INVALID_ARGUMENT); + + // It only support contiguous memory + NV_ASSERT_OR_RETURN(memdescGetPteArraySize(pMemDesc, AT_GPU) == 1, NV_ERR_INVALID_ARGUMENT); + + pTempMemDesc = memdescGetMemDescFromGpu(pMemDesc, pGpu); + + pageSize = memdescGetPageSize(pTempMemDesc, VAS_ADDRESS_TRANSLATION(pVAS)); + + NV_ASSERT_OK_OR_RETURN(memmgrGetKindComprFromMemDesc(pMemoryManager, pTempMemDesc, 0, &kind, &comprInfo)); + bCompressed = memmgrIsKind_HAL(pMemoryManager, FB_IS_KIND_COMPRESSIBLE, kind); + + // Static BAR1 mapping only support >=2MB page size for compressed memory + NV_CHECK_OR_RETURN(LEVEL_WARNING, bCompressed && (pageSize >= RM_PAGE_SIZE_HUGE), NV_ERR_INVALID_STATE); + + if (bRelease) + { + // update the PTE kind to be the uncompressed kind + comprInfo.kind = memmgrGetUncompressedKind_HAL(pGpu, pMemoryManager, kind, NV_FALSE); + } + + // Under static BAR1 mapping, BAR1 VA equal to physAddr + physAddr = memdescGetPhysAddr(pTempMemDesc, VAS_ADDRESS_TRANSLATION(pVAS), offset); + vAddr = RM_ALIGN_DOWN(physAddr, pageSize); + + pageOffset = physAddr & (pageSize - 1); + mapLength = RM_ALIGN_UP(pageOffset + length, pageSize); + + vaLo = vAddr; + vaHi = vaLo + mapLength - 1; + + pageArray.count = 1; + pageArray.pData = &physAddr; + + status = dmaUpdateVASpace_HAL(pGpu, pDma, pVAS, + pTempMemDesc, NULL, + vaLo, vaHi, + DMA_UPDATE_VASPACE_FLAGS_UPDATE_KIND, // only change KIND + &pageArray, 0, + &comprInfo, 0, + NV_MMU_VER3_PTE_VALID_TRUE, + NV_MMU_VER3_PTE_APERTURE_VIDEO_MEMORY, + BUS_INVALID_PEER, + NVLINK_INVALID_FABRIC_ADDR, + DMA_TLB_INVALIDATE, + NV_FALSE, + pageSize); + + if (status != NV_OK) + { + NV_PRINTF(LEVEL_ERROR, "error updating static bar1 VA space.\n"); + } + + return status; +} + +/*! + * @brief To unmap FB aperture for the specified memory under the static mapping. + * + * @param[in] pGpu GPU pointer + * @param[in] pKernelBus Kernel bus pointer + * @param[in] pMemDesc The memory to update + * @param[in] gfid The GFID + * + * return NV_OK on success + */ +NV_STATUS +kbusStaticUnmapFbAperture_GH100 +( + OBJGPU *pGpu, + KernelBus *pKernelBus, + MEMORY_DESCRIPTOR *pMemDesc, + NvU32 gfid +) +{ + MemoryManager *pMemoryManager = GPU_GET_MEMORY_MANAGER(pGpu); + NvBool bCompressedkind = memmgrIsKind_HAL(pMemoryManager, FB_IS_KIND_COMPRESSIBLE, + memdescGetPteKind(pMemDesc)); + + // + // For uncompressed type, nothing to do + // For compressed type, restore PTE kind to GMK + // + if (bCompressedkind) + { + NV_ASSERT_OK_OR_RETURN(_kbusUpdateStaticBAR1VAMapping_GH100(pGpu, pKernelBus, + pMemDesc, 0, memdescGetSize(pMemDesc), NV_TRUE, gfid)); + } + + // Nothing else to do on static mapping mode + NV_PRINTF(LEVEL_INFO, + "StaticBar1 unmapped at 0x%llx size 0x%llx%s\n", + memdescGetPhysAddr(pMemDesc, AT_GPU, 0), + memdescGetSize(pMemDesc), + bCompressedkind ? " [compressed]" : ""); + + return NV_OK; +} + +/*! + * @brief To map FB aperture for the specified memory under the static mapping. + * + * @param[in] pGpu GPU pointer + * @param[in] pKernelBus Kernel bus pointer + * @param[in] pMemDesc The memory to update + * @param[in] offset The offset of the memory to map + * @param[out] pAperOffset The Fb Aperture(BAR1) offset of the mapped vidmem + * @param[in] pLength The size of vidmem to map + * @param[in] gfid The GFID + * + * return NV_OK on success + */ +NV_STATUS +kbusStaticMapFbAperture_GH100 +( + OBJGPU *pGpu, + KernelBus *pKernelBus, + MEMORY_DESCRIPTOR *pMemDesc, + NvU64 offset, + NvU64 *pAperOffset, + NvU64 *pLength, + NvU32 gfid +) +{ + MemoryManager *pMemoryManager = GPU_GET_MEMORY_MANAGER(pGpu); + NvU64 physAddr; + NvU32 status = NV_OK; + NvBool bCompressedkind = memmgrIsKind_HAL(pMemoryManager, FB_IS_KIND_COMPRESSIBLE, memdescGetPteKind(pMemDesc)); + + // It only support contiguous memory + NV_ASSERT_OR_RETURN(memdescGetPteArraySize(pMemDesc, AT_GPU) == 1, NV_ERR_INVALID_ARGUMENT); + + physAddr = memdescGetPhysAddr(pMemDesc, AT_GPU, offset); + + if (physAddr < pKernelBus->bar1[gfid].staticBar1.base || + physAddr + *pLength >= pKernelBus->bar1[gfid].staticBar1.size) + { + NV_PRINTF(LEVEL_ERROR, + "0x%llx + 0x%llx is out of the range of the StaticBar1 map [0x%llx, 0x%llx]\n", + physAddr, *pLength, pKernelBus->bar1[gfid].staticBar1.base, + pKernelBus->bar1[gfid].staticBar1.base + pKernelBus->bar1[gfid].staticBar1.size); + + return NV_ERR_INVALID_ARGUMENT; + } + + if (bCompressedkind) + { + // Update PTE to be the compressed kind + NV_ASSERT_OK_OR_RETURN(_kbusUpdateStaticBAR1VAMapping_GH100(pGpu, pKernelBus, pMemDesc, + offset, *pLength, NV_FALSE, gfid)); + } + + // When the static bar1 enabled, the Fb aperture offset is the physical address. + *pAperOffset = physAddr; + + NV_PRINTF(LEVEL_INFO, "StaticBar1 mapped at 0x%llx size 0x%llx%s\n", + physAddr, *pLength, + bCompressedkind ? " [compressed]" : ""); + + return status; +} + void kbusWriteP2PWmbTag_GH100 ( @@ -1399,15 +2339,11 @@ if (GPU_GET_KERNEL_NVLINK(pGpu) != NULL) { NVLINK_INBAND_MSG_CALLBACK inbandMsgCbParams; - + inbandMsgCbParams.messageType = NVLINK_INBAND_MSG_TYPE_MC_TEAM_SETUP_RSP; inbandMsgCbParams.pCallback = &memorymulticastfabricTeamSetupResponseCallback; - - // - // Update this such that it indicates that Gpu lock shouldn't be taken - // when the callback is invoked - // - inbandMsgCbParams.wqItemFlags = 0; + inbandMsgCbParams.wqItemFlags = OS_QUEUE_WORKITEM_FLAGS_LOCK_SEMA | + OS_QUEUE_WORKITEM_FLAGS_LOCK_GPUS_RW; status = knvlinkRegisterInbandCallback(pGpu, GPU_GET_KERNEL_NVLINK(pGpu), @@ -1425,10 +2361,10 @@ if (!GPU_IS_NVSWITCH_DETECTED(pGpu)) { size = gpuGetFlaVasSize_HAL(pGpu, NV_FALSE); - base = pGpu->gpuInstance * size; + base = pGpu->gpuInstance * size; NV_ASSERT_OK_OR_GOTO(status, fabricvaspaceInitUCRange( - dynamicCast(pGpu->pFabricVAS, FABRIC_VASPACE), pGpu, + dynamicCast(pGpu->pFabricVAS, FABRIC_VASPACE), pGpu, base, size), free_instblk); } @@ -1491,7 +2427,7 @@ vmmDestroyVaspace(pVmm, pGpu->pFabricVAS); pGpu->pFabricVAS = NULL; - // TODO: Remove this once legacy FLA VAS support is deprecated + // TODO: Remove this once legacy FLA VAS support is deprecated pRmApi->Free(pRmApi, pKernelBus->flaInfo.hClient, pKernelBus->flaInfo.hClient); portMemSet(&pKernelBus->flaInfo, 0, sizeof(pKernelBus->flaInfo)); if (GPU_GET_KERNEL_NVLINK(pGpu) != NULL) @@ -1628,3 +2564,68 @@ return NV_OK; } + +/*! + * @brief Returns the EGM peer ID of pRemoteGpu if it was + * reserved already. + * + * @param[in] pLocalGpu local OBJGPU pointer + * @param[in] pLocalBus local OBJBUS pointer + * @param[in] pRemoteGpu remote OBJGPU pointer + * + * return NV_OK on success + * BUS_INVALID_PEER otherwise + * + */ +NvU32 +kbusGetEgmPeerId_GH100 +( + OBJGPU *pLocalGpu, + KernelBus *pLocalKernelBus, + OBJGPU *pRemoteGpu +) +{ + NvU32 gpuPeerInst = gpuGetInstance(pRemoteGpu); + NvU32 peerMask = pLocalKernelBus->p2p.busNvlinkPeerNumberMask[gpuPeerInst]; + NvU32 peerId; + + if (peerMask == 0) + { + NV_PRINTF(LEVEL_INFO, + "NVLINK P2P not set up between GPU%u and GPU%u\n", + gpuGetInstance(pLocalGpu), gpuPeerInst); + return BUS_INVALID_PEER; + } + + FOR_EACH_INDEX_IN_MASK(32, peerId, peerMask) + { + if (pLocalKernelBus->p2p.bEgmPeer[peerId]) + { + return peerId; + } + } + FOR_EACH_INDEX_IN_MASK_END; + + return BUS_INVALID_PEER; +} + +NvU32 +kbusGetEccCounts_GH100 +( + OBJGPU *pGpu, + KernelBus *pKernelBus +) +{ + NvU32 regVal; + NvU32 count = 0; + + // PCIE RE ORDER + regVal = GPU_REG_RD32(pGpu, NV_XAL_EP_REORDER_ECC_UNCORRECTED_ERR_COUNT); + count += DRF_VAL(_XAL_EP, _REORDER_ECC, _UNCORRECTED_ERR_COUNT_UNIQUE, regVal); + + // PCIE P2PREQ + regVal = GPU_REG_RD32(pGpu, NV_XAL_EP_P2PREQ_ECC_UNCORRECTED_ERR_COUNT); + count += DRF_VAL(_XAL_EP, _P2PREQ_ECC, _UNCORRECTED_ERR_COUNT_UNIQUE, regVal); + + return count; +} diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/kernel/gpu/bus/arch/maxwell/kern_bus_gm107.c nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/kernel/gpu/bus/arch/maxwell/kern_bus_gm107.c --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/kernel/gpu/bus/arch/maxwell/kern_bus_gm107.c 2023-10-25 20:20:53.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/kernel/gpu/bus/arch/maxwell/kern_bus_gm107.c 2024-03-05 22:13:15.000000000 +0000 @@ -22,6 +22,7 @@ */ #include "core/core.h" +#include "gpu/conf_compute/conf_compute.h" #include "gpu/gpu.h" #include "gpu/mmu/kern_gmmu.h" #include "gpu/bus/kern_bus.h" @@ -57,10 +58,11 @@ static NvU32 _kbusGetSizeOfBar2PageDir_GM107(NvU64 vaBase, NvU64 vaLimit, NvU64 vaPerEntry, NvU32 entrySize); static NV_STATUS _kbusBar0TunnelCb_GM107(void *pPrivData, NvU64 addr, void *pData, NvU64 size, NvBool bRead); +static NV_STATUS _kbusUpdateDebugStatistics(OBJGPU *pGpu); -NV_STATUS _kbusMapAperture_GM107(OBJGPU *, PMEMORY_DESCRIPTOR, OBJVASPACE *, NvU64, NvU64 *, - NvU64 *, NvU32 mapFlags, NvHandle hClient); -NV_STATUS _kbusUnmapAperture_GM107(OBJGPU *, OBJVASPACE *, PMEMORY_DESCRIPTOR, NvU64); +NV_STATUS _kbusMapAperture_GM107(OBJGPU *, KernelBus *, PMEMORY_DESCRIPTOR, OBJVASPACE *, NvU64, NvU64 *, + NvU64 *, NvU32 mapFlags, Device *pDevice); +NV_STATUS _kbusUnmapAperture_GM107(OBJGPU *, KernelBus *, OBJVASPACE *, PMEMORY_DESCRIPTOR, NvU64); MEMORY_DESCRIPTOR* kbusCreateStagingMemdesc(OBJGPU *pGpu); // This is the peer number assignment for SLI with @@ -189,6 +191,7 @@ kmemsysGetStaticConfig(pGpu, GPU_GET_KERNEL_MEMORY_SYSTEM(pGpu)); NvU64 offsetBar0; + NV_ASSERT_OR_RETURN_VOID(!KBUS_BAR0_PRAMIN_DISABLED(pGpu)); // // Initialize BAR0 window to the last 1MB of FB. Since this is where it // should already be positioned by the vbios, this should not be an issue. @@ -282,14 +285,24 @@ } } - kbusSetupDefaultBar0Window(pGpu, pKernelBus); + if (!KBUS_BAR0_PRAMIN_DISABLED(pGpu)) + { + kbusSetupDefaultBar0Window(pGpu, pKernelBus); + } // // Initialize BAR2 before initializing BAR1. That way, we can use BAR2 // rather than BAR0 to set up the BAR1 page table. This is faster because // BAR2 can be write-combined // - NV_ASSERT_OK_OR_RETURN(kbusInitBar2_HAL(pGpu, pKernelBus, GPU_GFID_PF)); + if (IS_GSP_CLIENT(pGpu) && KBUS_CPU_VISIBLE_BAR12_DISABLED(pGpu)) + { + NV_PRINTF(LEVEL_INFO, "For GSP client with C2C enabled, skip BAR2 init\n"); + } + else + { + NV_ASSERT_OK_OR_RETURN(kbusInitBar2_HAL(pGpu, pKernelBus, GPU_GFID_PF)); + } if (IS_VGPU_GSP_PLUGIN_OFFLOAD_ENABLED(pGpu) && IS_VIRTUAL_WITH_SRIOV(pGpu)) { @@ -324,6 +337,61 @@ return NV_OK; } + ConfidentialCompute *pConfCompute = GPU_GET_CONF_COMPUTE(pGpu); + + if (IS_GSP_CLIENT(pGpu) && (pConfCompute != NULL) && + !(pConfCompute->ccStaticInfo.bIsBar1Trusted && pConfCompute->ccStaticInfo.bIsPcieTrusted)) + { + pKernelBus->bBarAccessBlocked = NV_TRUE; + pKernelBus->bBar2TestSkipped = NV_TRUE; + NV_PRINTF(LEVEL_INFO, "BARs will be blocked for CC\n"); + } + else + { + pKernelBus->bBarAccessBlocked = NV_FALSE; + } + + // Verify GSP-DMA functionality before it is used for bootstrapping BAR2 + NV_ASSERT_OK_OR_RETURN( + memmgrVerifyGspDmaOps(pGpu, GPU_GET_MEMORY_MANAGER(pGpu))); + + if (KBUS_CPU_VISIBLE_BAR12_DISABLED(pGpu)) + { + NV_PRINTF(LEVEL_INFO, "C2C is being used, so disable CPU visible BAR1/2 now before they are setup\n"); + + pKernelBus->pciBarSizes[BUS_BAR_1] = 0; + pKernelBus->pciBarSizes[BUS_BAR_2] = 0; + + pKernelBus->bar1[GPU_GFID_PF].physAddr = 0; + pKernelBus->bar2[GPU_GFID_PF].physAddr = 0; + + pKernelBus->bar1[GPU_GFID_PF].apertureLength = 0; + pKernelBus->bar2[GPU_GFID_PF].rmApertureLimit = 0; + + // + // For C2C case, there is no CPU visible BAR2. So CPU visible BAR2 + // window is removed. In MONOLITHIC RM, where CPU visible and invisible + // BAR2 windows are contiguous, just shift CPU invisible BAR2 down to + // CPU invisible BAR2 base (0). + // Only need to handle PF, since VF BAR1/2 is disabled for C2C case. + // + if (!RMCFG_FEATURE_PLATFORM_GSP) // contiguous BAR2 + { + NV_PRINTF(LEVEL_INFO, "C2C is being used (contiguous/MONOLITHIC), update BAR2 cpuInvisibleBase: 0x%llX to 0, and cpuInvisibleLimit: 0x%llX to 0x%llX. Setting cpuVisibleLimit: 0x%llX to 0\n", + pKernelBus->bar2[GPU_GFID_PF].cpuInvisibleBase, + pKernelBus->bar2[GPU_GFID_PF].cpuInvisibleLimit, + pKernelBus->bar2[GPU_GFID_PF].cpuInvisibleLimit - pKernelBus->bar2[GPU_GFID_PF].cpuInvisibleBase, + pKernelBus->bar2[GPU_GFID_PF].cpuVisibleLimit); + + NV_ASSERT(pKernelBus->bar2[GPU_GFID_PF].cpuVisibleBase == 0); + NV_ASSERT(pKernelBus->bar2[GPU_GFID_PF].cpuInvisibleLimit >= pKernelBus->bar2[GPU_GFID_PF].cpuInvisibleBase); + pKernelBus->bar2[GPU_GFID_PF].cpuInvisibleLimit -= pKernelBus->bar2[GPU_GFID_PF].cpuInvisibleBase; + pKernelBus->bar2[GPU_GFID_PF].cpuInvisibleBase = pKernelBus->bar2[GPU_GFID_PF].cpuVisibleBase; + } + pKernelBus->bar2[GPU_GFID_PF].cpuVisibleLimit = 0; + pKernelBus->bUsePhysicalBar2InitPagetable = NV_FALSE; + } + if (RMCFG_FEATURE_PLATFORM_GSP) { NV_ASSERT_OK_OR_RETURN(kbusInitBar2_HAL(pGpu, pKernelBus, GPU_GFID_PF)); @@ -352,11 +420,14 @@ // FB address space may not be available on Tegra (see fbInitFbRegions) if (pMemoryManager->Ram.fbAddrSpaceSizeMb != 0) { - // Bind the BAR0 window to its default location - // note: we can't move the window for all intents and purposes since VBIOS - // will also use the window at arbitrary locations (eg during an SMI event - NvU64 offsetBar0 = (pMemoryManager->Ram.fbAddrSpaceSizeMb << 20) - DRF_SIZE(NV_PRAMIN); - kbusSetBAR0WindowVidOffset_HAL(pGpu, pKernelBus, offsetBar0); + if (!KBUS_BAR0_PRAMIN_DISABLED(pGpu)) + { + // Bind the BAR0 window to its default location + // note: we can't move the window for all intents and purposes since VBIOS + // will also use the window at arbitrary locations (eg during an SMI event + NvU64 offsetBar0 = (pMemoryManager->Ram.fbAddrSpaceSizeMb << 20) - DRF_SIZE(NV_PRAMIN); + kbusSetBAR0WindowVidOffset_HAL(pGpu, pKernelBus, offsetBar0); + } } else { @@ -365,7 +436,8 @@ if (!(flags & GPU_STATE_FLAGS_GC6_TRANSITION)) { - if (NULL == pKernelBus->virtualBar2[GPU_GFID_PF].pCpuMapping) + if (NULL == pKernelBus->virtualBar2[GPU_GFID_PF].pCpuMapping && + !KBUS_CPU_VISIBLE_BAR12_DISABLED(pGpu)) { NV_ASSERT_OK_OR_RETURN(kbusSetupBar2CpuAperture_HAL(pGpu, pKernelBus, GPU_GFID_PF)); } @@ -378,7 +450,7 @@ // a hit on the GC6 exit times, so this verif only feature does not // come for free. // - if (!pGpu->getProperty(pGpu, PDB_PROP_GPU_COHERENT_CPU_MAPPING) && + if (!pGpu->getProperty(pGpu, PDB_PROP_GPU_COHERENT_CPU_MAPPING) && !(IS_GPU_GC6_STATE_EXITING(pGpu) && pKernelBus->bSkipBar2TestOnGc6Exit)) { // Verify that BAR2 and the MMU actually works @@ -402,7 +474,8 @@ NV_STATUS status = NV_OK; KernelBif *pKernelBif = GPU_GET_KERNEL_BIF(pGpu); - if ( ! IS_GPU_GC6_STATE_EXITING(pGpu)) + if ( ! IS_GPU_GC6_STATE_EXITING(pGpu) && + !KBUS_CPU_VISIBLE_BAR12_DISABLED(pGpu)) { // Bar1 is created once per Gpu on each Gpu call to kbusStatePostLoad_GM107 if ((status = kbusInitBar1_HAL(pGpu, pKernelBus, GPU_GFID_PF)) != NV_OK) @@ -411,6 +484,7 @@ } } + // Call _kbusLinkP2P_GM107 only in case of Linked SLI and Unlinked SLI. Bug 4182245 if ((pKernelBif != NULL) && // RM managed P2P or restoring the HW state for OS resume @@ -418,11 +492,15 @@ (flags & GPU_STATE_FLAGS_PM_TRANSITION)) && (!pKernelBif->getProperty(pKernelBif, PDB_PROP_KBIF_P2P_READS_DISABLED) || - !pKernelBif->getProperty(pKernelBif, PDB_PROP_KBIF_P2P_WRITES_DISABLED))) + !pKernelBif->getProperty(pKernelBif, PDB_PROP_KBIF_P2P_WRITES_DISABLED)) + && + !gpuIsSelfHosted(pGpu)) { _kbusLinkP2P_GM107(pGpu, pKernelBus); } + _kbusUpdateDebugStatistics(pGpu); + return status; } @@ -463,6 +541,7 @@ if (IS_VIRTUAL(pGpu) && !(flags & GPU_STATE_FLAGS_PRESERVING)) return NV_OK; + // Call kbusUnlinkP2P_HAL only in case of Linked SLI and Unliked SLI. Bug 4182245 if ((pKernelBif != NULL) && (!pKernelBif->getProperty(pKernelBif, PDB_PROP_KBIF_P2P_READS_DISABLED) || @@ -470,17 +549,22 @@ && // RM managed P2P or unconfiguring HW P2P for OS suspend/hibernate (!kbusIsP2pMailboxClientAllocated(pKernelBus) || - (flags & GPU_STATE_FLAGS_PM_TRANSITION))) + (flags & GPU_STATE_FLAGS_PM_TRANSITION)) + && !gpuIsSelfHosted(pGpu)) { kbusUnlinkP2P_HAL(pGpu, pKernelBus); } - if ((flags & GPU_STATE_FLAGS_PRESERVING) && !IS_VIRTUAL_WITH_SRIOV(pGpu)) + if (flags & GPU_STATE_FLAGS_PRESERVING) { if (!IS_GPU_GC6_STATE_ENTERING(pGpu)) { status = kbusTeardownBar2CpuAperture_HAL(pGpu, pKernelBus, GPU_GFID_PF); - pKernelBus->bUsePhysicalBar2InitPagetable = NV_FALSE; + if (!IS_VIRTUAL_WITH_SRIOV(pGpu)) + { + // Do not use BAR2 physical mode for bootstrapping BAR2 across S/R. + pKernelBus->bUsePhysicalBar2InitPagetable = NV_FALSE; + } } } else @@ -517,12 +601,13 @@ NvU64 vaRangeMax; NvU32 vaflags; KernelBif *pKernelBif = GPU_GET_KERNEL_BIF(pGpu); - NvU32 vaSpaceBigPageSize = 0; + NvU64 vaSpaceBigPageSize = 0; OBJSYS *pSys = SYS_GET_INSTANCE(); OBJVMM *pVmm = SYS_GET_VMM(pSys); NvU32 gpuMask = 0; NvBool bSmoothTransitionEnabled = ((pGpu->uefiScanoutSurfaceSizeInMB != 0) && RMCFG_FEATURE_PLATFORM_WINDOWS_LDDM); + NvU32 bar1ReservedSize = 0; vaRangeMax = pKernelBus->bar1[gfid].apertureLength - 1; @@ -535,6 +620,9 @@ return rmStatus; } + if (IsT234(pGpu) && pGpu->getProperty(pGpu, PDB_PROP_GPU_ZERO_FB)) + return NV_OK; + // // For BAR address spaces, leave a valid PTE pointed to page 0. // According to page 196 of revision 2.1 of the PCI spec, prefetchable @@ -574,10 +662,10 @@ } else { - NV_PRINTF(LEVEL_ERROR, - "Arch doesnt support BAR1 Big page Override- Using defaults\n"); - NV_ASSERT(0); - vaSpaceBigPageSize = 0; + NV_PRINTF(LEVEL_ERROR, + "Arch doesnt support BAR1 Big page Override- Using defaults\n"); + NV_ASSERT(0); + vaSpaceBigPageSize = 0; } } } @@ -666,7 +754,6 @@ // Restrict normal BAR1 alloc to be within the aperture pVASpaceHeap = vaspaceGetHeap(pKernelBus->bar1[gfid].pVAS); - // // Reduce BAR1 VA space by FERMI_SMALL_PAGESIZE for host overfetch bug // WAR (Bug 529932/525381). (FERMI_SMALL_PAGESIZE is sufficient to @@ -732,7 +819,7 @@ rmStatus = kbusMapFbAperture_HAL(pGpu, pKernelBus, pConsoleMemDesc, fbPhysOffset, &bar1VAOffset, &consoleSize, BUS_MAP_FB_FLAGS_MAP_UNICAST | BUS_MAP_FB_FLAGS_MAP_OFFSET_FIXED, - NV01_NULL_OBJECT); + NULL); if (rmStatus != NV_OK) { NV_PRINTF(LEVEL_ERROR, @@ -760,6 +847,7 @@ } pKernelBus->bBar1ConsolePreserved = NV_TRUE; + bar1ReservedSize += consoleSize; } else { @@ -770,19 +858,29 @@ } } - // Reserve space for max number of peers regardless of SLI config - if ((!pKernelBif->getProperty(pKernelBif, PDB_PROP_KBIF_P2P_READS_DISABLED) || - !pKernelBif->getProperty(pKernelBif, PDB_PROP_KBIF_P2P_WRITES_DISABLED)) - && - IS_GFID_PF(gfid) - && - !kbusIsP2pMailboxClientAllocated(pKernelBus)) + if (kbusNeedStaticBar1Mapping_HAL(pGpu, pKernelBus)) { - rmStatus = kbusAllocP2PMailboxBar1_HAL(pGpu, pKernelBus, gfid, vaRangeMax); - - if (NV_OK != rmStatus) + // Enable the static BAR1 mapping for the BAR1 P2P + NV_ASSERT_OK_OR_GOTO(rmStatus, + kbusEnableStaticBar1Mapping_HAL(pGpu, pKernelBus, bar1ReservedSize, gfid), + kbusInitBar1_failed); + } + else + { + // Reserve space for max number of peers for the mailbox p2p regardless of SLI config + if ((!pKernelBif->getProperty(pKernelBif, PDB_PROP_KBIF_P2P_READS_DISABLED) || + !pKernelBif->getProperty(pKernelBif, PDB_PROP_KBIF_P2P_WRITES_DISABLED)) + && + IS_GFID_PF(gfid) + && + !kbusIsP2pMailboxClientAllocated(pKernelBus)) { - goto kbusInitBar1_failed; + rmStatus = kbusAllocP2PMailboxBar1_HAL(pGpu, pKernelBus, gfid, vaRangeMax); + + if (NV_OK != rmStatus) + { + goto kbusInitBar1_failed; + } } } @@ -908,6 +1006,11 @@ pKernelBus->bBar1ConsolePreserved = NV_FALSE; } + if (pKernelBus->bar1[gfid].bStaticBar1Enabled) + { + status = kbusDisableStaticBar1Mapping_HAL(pGpu, pKernelBus, gfid); + } + vmmDestroyVaspace(pVmm, pKernelBus->bar1[gfid].pVAS); pKernelBus->bar1[gfid].pVAS = NULL; @@ -956,15 +1059,15 @@ return NV_OK; } - status = kbusSetupBar2CpuAperture_HAL(pGpu, pKernelBus, gfid); - NV_ASSERT_OR_GOTO(status == NV_OK, cleanup); - - if (KBUS_BAR2_ENABLED(pKernelBus)) + if (!KBUS_CPU_VISIBLE_BAR12_DISABLED(pGpu)) { - status = kbusSetupBar2GpuVaSpace_HAL(pGpu, pKernelBus, gfid); + status = kbusSetupBar2CpuAperture_HAL(pGpu, pKernelBus, gfid); NV_ASSERT_OR_GOTO(status == NV_OK, cleanup); } + status = kbusSetupBar2GpuVaSpace_HAL(pGpu, pKernelBus, gfid); + NV_ASSERT_OR_GOTO(status == NV_OK, cleanup); + status = kbusCommitBar2_HAL(pGpu, pKernelBus, GPU_STATE_DEFAULT); NV_ASSERT_OR_GOTO(status == NV_OK, cleanup); @@ -1040,8 +1143,11 @@ if (gpuIsCacheOnlyModeEnabled(pGpu) && !pGpu->getProperty(pGpu, PDB_PROP_GPU_BROKEN_FB)) { - kbusFlush_HAL(pGpu, pKernelBus, BUS_FLUSH_VIDEO_MEMORY); - kbusFlush_HAL(pGpu, pKernelBus, BUS_FLUSH_VIDEO_MEMORY); + // + // Send 2 explicit sysmembars. Bug 557124 + // + kbusSendSysmembar(pGpu, pKernelBus); + kbusSendSysmembar(pGpu, pKernelBus); } return status; @@ -1275,6 +1381,7 @@ OBJEHEAP *pVASpaceHeap; MEMORY_DESCRIPTOR *pPageLevelsMemDesc = NULL; NvU32 allocSize; + NvBool bUseStagingBuffer = NV_FALSE; // // Nothing to be done in guest in the paravirtualization case or if @@ -1322,7 +1429,8 @@ pKernelBus->bar2[gfid].pteBase += memmgrGetRsvdMemoryBase(pMemoryManager); } - if (IS_GFID_PF(gfid)) + if (IS_GFID_PF(gfid) && + !KBUS_BAR0_PRAMIN_DISABLED(pGpu)) { // Setup BAR0 window for page directory/table updates during BAR2 bootstrap status = kbusSetupBar0WindowBeforeBar2Bootstrap_HAL(pGpu, pKernelBus, &origVidOffset); @@ -1391,6 +1499,44 @@ } } + // + // Setup a memdesc that covers all of BAR2's page levels. + // + // The following is based on _bar2WalkCBLevelAlloc(). + // + if (IS_GFID_PF(gfid)) + { + switch (pKernelBus->PDEBAR2Aperture) + { + default: + case ADDR_FBMEM: + if (pPageLevelsMemDesc != NULL) + { + memdescDescribe(pPageLevelsMemDesc, + pKernelBus->PDEBAR2Aperture, + pKernelBus->bar2[gfid].pdeBase, + allocSize); + } + break; + + case ADDR_SYSMEM: + // + // In SYSMEM, page level instances are allocated one at a time. It is + // not guaranteed that they are contiguous. Thus, SYSMEM page level + // instances are dynamically mapped-in via memmap as needed instead of + // having one static mapping. + // + pPageLevelsMemDesc = NULL; + break; + } + pKernelBus->virtualBar2[gfid].pPageLevelsMemDesc = pPageLevelsMemDesc; + + if (KBUS_BAR0_PRAMIN_DISABLED(pGpu)) + { + NV_ASSERT_OK_OR_GOTO(status, kbusInitVirtualBar2_HAL(pGpu, pKernelBus), cleanup); + } + } + // Get the MMU format for BAR2. pKernelBus->bar2[gfid].pFmt = kgmmuFmtGet(pKernelGmmu, GMMU_FMT_VERSION_DEFAULT, 0); NV_ASSERT_OR_GOTO(NULL != pKernelBus->bar2[gfid].pFmt, cleanup); @@ -1402,8 +1548,10 @@ // if (pKernelBus->bar2[gfid].pWalkStagingBuffer == NULL && pKernelBus->PTEBAR2Aperture == ADDR_FBMEM && - pKernelBus->bar2[gfid].bBootstrap) + pKernelBus->bar2[gfid].bBootstrap && + !RMCFG_FEATURE_PLATFORM_GSP) { + bUseStagingBuffer = NV_TRUE; pKernelBus->bar2[gfid].pWalkStagingBuffer = kbusCreateStagingMemdesc(pGpu); } @@ -1435,10 +1583,10 @@ status = mmuWalkReserveEntries(pWalk, pLevelFmt, pKernelBus->bar2[gfid].cpuVisibleBase, pKernelBus->bar2[gfid].cpuVisibleLimit, NV_FALSE); NV_ASSERT_OR_GOTO(NV_OK == status, cleanup); - - pKernelBus->bar2[gfid].cpuVisiblePgTblSize = pKernelBus->bar2[gfid].pageTblInit * pKernelBus->bar2[gfid].pageTblSize; - - status = mmuWalkSparsify(pWalk, pKernelBus->bar2[gfid].cpuVisibleBase, pKernelBus->bar2[gfid].cpuVisibleLimit, NV_TRUE); + status = mmuWalkSparsify(pWalk, + pKernelBus->bar2[gfid].cpuVisibleBase, + pKernelBus->bar2[gfid].cpuVisibleLimit, + bUseStagingBuffer); NV_ASSERT_OR_GOTO(NV_OK == status, cleanup); } @@ -1447,7 +1595,10 @@ status = mmuWalkReserveEntries(pWalk, pLevelFmt, pKernelBus->bar2[gfid].cpuInvisibleBase, pKernelBus->bar2[gfid].cpuInvisibleLimit, NV_FALSE); NV_ASSERT_OR_GOTO(NV_OK == status, cleanup); - status = mmuWalkSparsify(pWalk, pKernelBus->bar2[gfid].cpuInvisibleBase, pKernelBus->bar2[gfid].cpuInvisibleLimit, NV_TRUE); + status = mmuWalkSparsify(pWalk, + pKernelBus->bar2[gfid].cpuInvisibleBase, + pKernelBus->bar2[gfid].cpuInvisibleLimit, + bUseStagingBuffer); NV_ASSERT_OR_GOTO(NV_OK == status, cleanup); } @@ -1468,44 +1619,13 @@ pKernelBus->virtualBar2[gfid].pPDB = pKernelBus->bar2[gfid].pPDEMemDesc; } - // - // Setup a memdesc that covers all of BAR2's page levels. - // - // The following is based on _bar2WalkCBLevelAlloc(). - // - if (IS_GFID_PF(gfid)) - { - switch (pKernelBus->PDEBAR2Aperture) - { - default: - case ADDR_FBMEM: - if (pPageLevelsMemDesc != NULL) - { - memdescDescribe(pPageLevelsMemDesc, - pKernelBus->PDEBAR2Aperture, - pKernelBus->bar2[gfid].pdeBase, - allocSize); - } - break; - - case ADDR_SYSMEM: - // - // In SYSMEM, page level instances are allocated one at a time. It is - // not guaranteed that they are contiguous. Thus, SYSMEM page level - // instances are dynamically mapped-in via memmap as needed instead of - // having one static mapping. - // - pPageLevelsMemDesc = NULL; - break; - } - pKernelBus->virtualBar2[gfid].pPageLevelsMemDesc = pPageLevelsMemDesc; - } - kbusPatchBar2Pdb_HAL(pGpu, pKernelBus); cleanup: - if (IS_GFID_VF(gfid) && (pKernelBus->virtualBar2[gfid].pPageLevels != NULL)) + if (IS_GFID_VF(gfid) && + (pKernelBus->virtualBar2[gfid].pPageLevels != NULL) && + (pKernelBus->virtualBar2[gfid].pPageLevelsMemDesc != NULL)) { kbusUnmapRmAperture_HAL(pGpu, pKernelBus->virtualBar2[gfid].pPageLevelsMemDesc, @@ -1518,7 +1638,8 @@ mmuWalkSetUserCtx(pWalk, NULL); } - if (!kbusIsPhysicalBar2InitPagetableEnabled(pKernelBus) && IS_GFID_PF(gfid)) + if (!kbusIsPhysicalBar2InitPagetableEnabled(pKernelBus) && IS_GFID_PF(gfid) && + !KBUS_BAR0_PRAMIN_DISABLED(pGpu)) { // Restore BAR0 window after BAR2 bootstrap kbusRestoreBar0WindowAfterBar2Bootstrap_HAL(pGpu, pKernelBus, origVidOffset); @@ -1582,7 +1703,9 @@ NV_ASSERT_OK_OR_RETURN(mmuWalkSetUserCtx(pKernelBus->bar2[gfid].pWalk, &userCtx)); - if (kbusIsPhysicalBar2InitPagetableEnabled(pKernelBus) || IS_GFID_VF(gfid)) + if (kbusIsPhysicalBar2InitPagetableEnabled(pKernelBus) || + IS_GFID_VF(gfid) || + KBUS_BAR0_PRAMIN_DISABLED(pGpu)) { mmuWalkLevelInstancesForceFree(pKernelBus->bar2[gfid].pWalk); } @@ -1695,6 +1818,11 @@ { NV_STATUS status = NV_OK; + if (kbusIsBarAccessBlocked(pKernelBus)) + return NV_OK; + + NV_ASSERT_OR_RETURN(!KBUS_BAR0_PRAMIN_DISABLED(pGpu), + NV_ERR_INVALID_STATE); // Check that Bar2 Page Dir starts at or after bar0 window vid offset if (ADDR_FBMEM == pKernelBus->PDEBAR2Aperture || ADDR_FBMEM == pKernelBus->PTEBAR2Aperture) @@ -1740,6 +1868,11 @@ NvU64 origVidOffset ) { + if (kbusIsBarAccessBlocked(pKernelBus)) + return; + + NV_ASSERT_OR_RETURN_VOID(!KBUS_BAR0_PRAMIN_DISABLED(pGpu)); + NV_ASSERT(pKernelBus->bar2[GPU_GFID_PF].bBootstrap); pKernelBus->bar2[GPU_GFID_PF].bBootstrap = NV_FALSE; @@ -1880,7 +2013,40 @@ if (memdescGetAddressSpace(pMemDesc) == ADDR_FBMEM) { - if (pKernelBus->virtualBar2[gfid].pPageLevels != NULL) + if (kbusIsBarAccessBlocked(pKernelBus)) + { + MemoryManager *pMemoryManager = GPU_GET_MEMORY_MANAGER(pGpu); + TRANSFER_SURFACE surf = {0}; + NvU32 sizeOfEntries; + NvU32 index; + + NV_ASSERT_OR_RETURN_VOID(pKernelBus->virtualBar2[gfid].pPageLevels == NULL); + + surf.pMemDesc = pMemDesc; + surf.offset = entryIndexLo * pLevelFmt->entrySize; + + sizeOfEntries = (entryIndexHi - entryIndexLo + 1) * pLevelFmt->entrySize; + + pMap = memmgrMemBeginTransfer(pMemoryManager, &surf, sizeOfEntries, + TRANSFER_FLAGS_SHADOW_ALLOC); + + for (entryIndex = entryIndexLo; entryIndex <= entryIndexHi; entryIndex++) + { + // Update the PTE with the physical address. + _busWalkCBMapNextEntries_UpdatePhysAddr(pGpu, + &entryValue, + pIter, + pageSize); + + index = (entryIndex - entryIndexLo) * pLevelFmt->entrySize; + portMemCopy(&pMap[index], pLevelFmt->entrySize, + entryValue.v8, pLevelFmt->entrySize); + } + + memmgrMemEndTransfer(pMemoryManager, &surf, sizeOfEntries, + TRANSFER_FLAGS_SHADOW_ALLOC); + } + else if (pKernelBus->virtualBar2[gfid].pPageLevels != NULL) { // // Determine the start of the desired page level offset from @@ -1940,25 +2106,22 @@ else { // Use BAR0 or nvlink if available - sizeInDWord = (NvU32)NV_CEIL(pLevelFmt->entrySize, sizeof(NvU32)); NvU64 entryStart = memdescGetPhysAddr(pMemDesc, FORCE_VMMU_TRANSLATION(pMemDesc, AT_GPU), entryOffset); - NvU32 i; NvU8 *pMapping = NULL; - if (pKernelBus->coherentCpuMapping.bCoherentCpuMapping) + if (KBUS_BAR0_PRAMIN_DISABLED(pGpu)) { - NV_ASSERT_OR_RETURN_VOID(pGpu->getProperty(pGpu, PDB_PROP_GPU_COHERENT_CPU_MAPPING)); pMapping = kbusMapCoherentCpuMapping_HAL(pGpu, pKernelBus, pMemDesc); NV_ASSERT_OR_RETURN_VOID(pMapping != NULL); - for (i = 0; i < sizeInDWord; i++) - { - MEM_WR32(pMapping + entryOffset + sizeof(NvU32)*i, - entryValue.v32[i]); - } + portMemCopy(pMapping + entryStart, + pLevelFmt->entrySize, entryValue.v8, + pLevelFmt->entrySize); kbusUnmapCoherentCpuMapping_HAL(pGpu, pKernelBus, pMemDesc); } else { + sizeInDWord = (NvU32)NV_CEIL(pLevelFmt->entrySize, sizeof(NvU32)); + NvU32 i; for (i = 0; i < sizeInDWord; i++) { // BAR0 write. @@ -2095,7 +2258,7 @@ NvU64 vaLo; NvU64 vaHi; NvU32 gfid; - const NvU32 pageSize = FERMI_SMALL_PAGESIZE; + const NvU64 pageSize = FERMI_SMALL_PAGESIZE; const GMMU_FMT *pFmt; ADDRESS_TRANSLATION addressTranslation; NvBool bCallingContextPlugin; @@ -2175,7 +2338,7 @@ // MMU_MAP_CTX mapTarget.pLevelFmt = mmuFmtFindLevelWithPageShift(pFmt->pRoot, - BIT_IDX_32(pageSize)); + BIT_IDX_64(pageSize)); mapTarget.pIter = &mapIter; mapTarget.MapNextEntries = _kbusWalkCBMapNextEntries_RmAperture; @@ -2322,23 +2485,34 @@ _kbusUpdateDebugStatistics(OBJGPU *pGpu) { KernelBus *pKernelBus = GPU_GET_KERNEL_BUS(pGpu); - OBJVASPACE *pBar1VAS = kbusGetBar1VASpace_HAL(pGpu, pKernelBus); + OBJVASPACE *pBar1VAS; OBJEHEAP *pVASHeap; NV00DE_SHARED_DATA *pSharedData = gpushareddataWriteStart(pGpu); NV_RANGE bar1VARange = NV_RANGE_EMPTY; - pVASHeap = vaspaceGetHeap(pBar1VAS); - bar1VARange = rangeMake(vaspaceGetVaStart(pBar1VAS), vaspaceGetVaLimit(pBar1VAS)); + if (!KBUS_CPU_VISIBLE_BAR12_DISABLED(pGpu)) + { + pBar1VAS = kbusGetBar1VASpace_HAL(pGpu, pKernelBus); + NV_ASSERT_OR_RETURN(pBar1VAS != NULL, NV_ERR_INVALID_STATE); + pVASHeap = vaspaceGetHeap(pBar1VAS); + bar1VARange = rangeMake(vaspaceGetVaStart(pBar1VAS), vaspaceGetVaLimit(pBar1VAS)); - pSharedData->bar1Size = (NvU32)(rangeLength(bar1VARange) / 1024); - pSharedData->bar1AvailSize = 0; + pSharedData->bar1Size = (NvU32)(rangeLength(bar1VARange) / 1024); + pSharedData->bar1AvailSize = 0; - if (pVASHeap != NULL) - { - NvU64 freeSize = 0; + if (pVASHeap != NULL) + { + NvU64 freeSize = 0; - pVASHeap->eheapInfoForRange(pVASHeap, bar1VARange, NULL, NULL, NULL, &freeSize); - pSharedData->bar1AvailSize = (NvU32)(freeSize / 1024); + pVASHeap->eheapInfoForRange(pVASHeap, bar1VARange, NULL, NULL, NULL, &freeSize); + pSharedData->bar1AvailSize = (NvU32)(freeSize / 1024); + } + } + else + { + // When coherent C2C path is enabled, BAR1 is disabled + pSharedData->bar1Size = 0; + pSharedData->bar1AvailSize = 0; } gpushareddataWriteFinish(pGpu); @@ -2356,7 +2530,7 @@ NvU64 *pAperOffset, NvU64 *pLength, NvU32 flags, - NvHandle hClient + Device *pDevice ) { NvBool bBcState = gpumgrGetBcEnabledStatus(pGpu); @@ -2370,8 +2544,6 @@ NV_ASSERT((flags & BUS_MAP_FB_FLAGS_FERMI_INVALID) == 0); - pVAS = kbusGetBar1VASpace_HAL(pGpu, pKernelBus); - // Set BC to enabled in UC flag not passed if ((IsSLIEnabled(pGpu) && ((flags & BUS_MAP_FB_FLAGS_MAP_UNICAST) == 0)) && ((flags & BUS_MAP_FB_FLAGS_PRE_INIT) == 0)) @@ -2391,9 +2563,14 @@ pLoopGpu = pGpu; pVAS = kbusGetBar1VASpace_HAL(pGpu, pKernelBus); - rmStatus = _kbusMapAperture_GM107(pGpu, pMemDesc, + if (pVAS == NULL) + { + rmStatus = NV_ERR_GENERIC; + SLI_LOOP_BREAK; + } + rmStatus = _kbusMapAperture_GM107(pGpu, pKernelBus, pMemDesc, pVAS, offset, pAperOffset, - pLength, flags, hClient); + pLength, flags, pDevice); // // Ensure that all returned VA offsets are the same on each GPU @@ -2505,7 +2682,7 @@ SLI_LOOP_BREAK; } memdescFlushCpuCaches(pGpu, pMemDesc); - rmStatus = _kbusUnmapAperture_GM107(pGpu, pVAS, pMemDesc, aperOffset); + rmStatus = _kbusUnmapAperture_GM107(pGpu, pKernelBus, pVAS, pMemDesc, aperOffset); if (rmStatus != NV_OK) { @@ -2589,6 +2766,12 @@ return NV_OK; } + if (kbusIsBarAccessBlocked(pKernelBus)) + { + // If BAR has been blocked, there's nothing to flush for vidmem + return NV_OK; + } + if (flags & BUS_FLUSH_VIDEO_MEMORY) { // @@ -2696,13 +2879,14 @@ _kbusMapAperture_GM107 ( OBJGPU *pGpu, + KernelBus *pKernelBus, MEMORY_DESCRIPTOR *pMemDesc, OBJVASPACE *pVAS, NvU64 offset, NvU64 *pAperOffset, NvU64 *pLength, NvU32 mapFlags, - NvHandle hClient + Device *pDevice ) { NV_STATUS rmStatus = NV_ERR_GENERIC; @@ -2711,6 +2895,9 @@ NvU32 flags = DRF_DEF(OS46, _FLAGS, _DMA_UNICAST_REUSE_ALLOC, _FALSE); MEMORY_DESCRIPTOR *pTempMemDesc; NvU32 swizzId = KMIGMGR_SWIZZID_INVALID; + NvU32 gfid; + + NV_ASSERT_OK_OR_RETURN(vgpuGetCallingContextGfid(pGpu, &gfid)); // Ensure that the BAR1 VA space is the same across all subdevices if (IsSLIEnabled(pGpu) && ((mapFlags & BUS_MAP_FB_FLAGS_MAP_UNICAST) == 0)) @@ -2719,6 +2906,14 @@ gpumgrSetBcEnabledStatus(pGpu, NV_TRUE); } + if (pKernelBus->bar1[gfid].bStaticBar1Enabled && + (memdescGetAddressSpace(pMemDesc) == ADDR_FBMEM)) + { + return kbusStaticMapFbAperture_HAL(pGpu, pKernelBus, pMemDesc, + offset, pAperOffset, + pLength, gfid); + } + if (mapFlags & BUS_MAP_FB_FLAGS_MAP_OFFSET_FIXED) { flags = FLD_SET_DRF(OS46, _FLAGS, _DMA_OFFSET_FIXED, _TRUE, flags); @@ -2726,23 +2921,37 @@ pDma = GPU_GET_DMA(pGpu); - // - // Valid client handle should be associated with a BAR1 mapping request if SMC memory - // partitioning is enabled. That's because BAR1 VA space is split among SMC partitions. - // - // Internal allocations like RM allocated USERD which require BAR1 mapping are done during RM init - // before SMC is enabled and BAR1 VA space is split. So they should work despite not having - // an associated hClient and also such BAR VA space allocations should happen before BAR1 is split. - // if (IS_MIG_IN_USE(pGpu)) { - MIG_INSTANCE_REF ref; - KernelMIGManager *pKernelMIGManager = GPU_GET_KERNEL_MIG_MANAGER(pGpu); + if (pDevice != NULL) + { + MIG_INSTANCE_REF ref; + KernelMIGManager *pKernelMIGManager = GPU_GET_KERNEL_MIG_MANAGER(pGpu); + + NV_ASSERT_OR_RETURN(pDevice != NULL, NV_ERR_INVALID_ARGUMENT); + NV_ASSERT_OK_OR_RETURN(kmigmgrGetInstanceRefFromDevice(pGpu, pKernelMIGManager, + pDevice, &ref)); + swizzId = ref.pKernelMIGGpuInstance->swizzId; + } + else if (pMemDesc->pHeap != NULL) + { + KernelMIGManager *pKernelMIGManager = GPU_GET_KERNEL_MIG_MANAGER(pGpu); + KERNEL_MIG_GPU_INSTANCE *pCurrKernelMIGGPUInstance = NULL; + KERNEL_MIG_GPU_INSTANCE *pKernelMIGGPUInstance = NULL; + + FOR_EACH_VALID_GPU_INSTANCE(pGpu, pKernelMIGManager, pCurrKernelMIGGPUInstance) + { + if (pCurrKernelMIGGPUInstance->pMemoryPartitionHeap == pMemDesc->pHeap) + { + pKernelMIGGPUInstance = pCurrKernelMIGGPUInstance; + break; + } + } + FOR_EACH_VALID_GPU_INSTANCE_END(); - NV_ASSERT_OR_RETURN(hClient != NV01_NULL_OBJECT, NV_ERR_INVALID_ARGUMENT); - NV_ASSERT_OK_OR_RETURN(kmigmgrGetInstanceRefFromClient(pGpu, pKernelMIGManager, - hClient, &ref)); - swizzId = ref.pKernelMIGGpuInstance->swizzId; + NV_ASSERT_OR_RETURN(pKernelMIGGPUInstance != NULL, NV_ERR_INVALID_STATE); + swizzId = pKernelMIGGPUInstance->swizzId; + } } if (memdescGetCpuCacheAttrib(pMemDesc) == NV_MEMORY_CACHED) @@ -2802,6 +3011,7 @@ _kbusUnmapAperture_GM107 ( OBJGPU *pGpu, + KernelBus *pKernelBus, OBJVASPACE *pVAS, MEMORY_DESCRIPTOR *pMemDesc, NvU64 aperOffset @@ -2809,6 +3019,15 @@ { NV_STATUS rmStatus = NV_OK; VirtMemAllocator *pDma = GPU_GET_DMA(pGpu); + NvU32 gfid; + + NV_ASSERT_OK_OR_RETURN(vgpuGetCallingContextGfid(pGpu, &gfid)); + + if (pKernelBus->bar1[gfid].bStaticBar1Enabled && + (memdescGetAddressSpace(pMemDesc) == ADDR_FBMEM)) + { + return kbusStaticUnmapFbAperture_HAL(pGpu, pKernelBus, pMemDesc, gfid); + } rmStatus = dmaFreeMapping_HAL(pGpu, pDma, pVAS, aperOffset, pMemDesc, 0, NULL); @@ -3286,8 +3505,11 @@ // will also use the window at arbitrary locations (eg during an SMI event if (pMemoryManager->Ram.fbAddrSpaceSizeMb) { - offsetBar0 = (pMemoryManager->Ram.fbAddrSpaceSizeMb << 20) - DRF_SIZE(NV_PRAMIN); - (void)kbusSetBAR0WindowVidOffset_HAL(pGpu, pKernelBus, offsetBar0); + if (!KBUS_BAR0_PRAMIN_DISABLED(pGpu)) + { + offsetBar0 = (pMemoryManager->Ram.fbAddrSpaceSizeMb << 20) - DRF_SIZE(NV_PRAMIN); + (void)kbusSetBAR0WindowVidOffset_HAL(pGpu, pKernelBus, offsetBar0); + } } // Unmap BAR0 Writecombined Window @@ -3311,9 +3533,12 @@ // clean up private info block // + + // Call _kbusDestroyP2P_GM107 only in case of Linked SLI and Unlinked SLI. Bug 4182245 if ((pKernelBif != NULL) && ((!pKernelBif->getProperty(pKernelBif, PDB_PROP_KBIF_P2P_READS_DISABLED) || !pKernelBif->getProperty(pKernelBif, PDB_PROP_KBIF_P2P_WRITES_DISABLED)) && - (kbusIsP2pInitialized(pKernelBus)))) + (kbusIsP2pInitialized(pKernelBus))) && + !gpuIsSelfHosted(pGpu)) { (void)_kbusDestroyP2P_GM107(pGpu, pKernelBus); } @@ -3658,7 +3883,9 @@ NvU32 gfid ) { - NvU32 data32; + NvU32 data32; + NvU32 maxRmAddressibleBar2SizeMb = pKernelBus->bIsEntireBar2RegionVirtuallyAddressible ? + BUS_BAR2_APERTURE_MB : BUS_BAR2_RM_APERTURE_MB; // // Setup BAR1 aperture size only for GFID_VF @@ -3674,7 +3901,7 @@ // Check to see if a BAR2 aperture size override has been specified. // if (((NV_OK == osReadRegistryDword(pGpu, NV_REG_STR_RM_BAR2_APERTURE_SIZE_MB, - &data32))) && data32 && data32 <= BUS_BAR2_RM_APERTURE_MB) + &data32))) && data32 && data32 <= maxRmAddressibleBar2SizeMb) { // Set the BAR2 aperture size based on the override pKernelBus->bar2[gfid].rmApertureLimit = (data32 << 20) - 1; @@ -3695,13 +3922,17 @@ // if ((IS_SIM_MODS(GPU_GET_OS(pGpu)) && IS_SILICON(pGpu) == 0) || (!RMCFG_FEATURE_MODS_FEATURES && IS_SIMULATION(pGpu))) { + // Temporarily increasing the RM aperture size to 16MB - Bug 3317956 + if (gpuIsCCFeatureEnabled(pGpu)) + pKernelBus->bar2[gfid].rmApertureLimit = (BUS_BAR2_RM_APERTURE_MB << 20) - 1; // 16MB + else pKernelBus->bar2[gfid].rmApertureLimit = ((BUS_BAR2_RM_APERTURE_MB >> 1) << 20) - 1; // 8MB pKernelBus->bar2[gfid].cpuVisibleLimit = pKernelBus->bar2[gfid].rmApertureLimit; // No VESA space } else { pKernelBus->bar2[gfid].cpuVisibleLimit = (BUS_BAR2_APERTURE_MB << 20) - 1; - pKernelBus->bar2[gfid].rmApertureLimit = (BUS_BAR2_RM_APERTURE_MB << 20) - 1; + pKernelBus->bar2[gfid].rmApertureLimit = (maxRmAddressibleBar2SizeMb << 20) - 1; } } @@ -4227,6 +4458,12 @@ // The following code assumes aperture to be VID_MEM (or that vidmem/sysmem are same). NV_ASSERT(gpuIsUnifiedMemorySpaceEnabled(pGpu) || (addrSpace == ADDR_FBMEM)); + if (KBUS_BAR0_PRAMIN_DISABLED(pGpu)) + { + NV_ASSERT_FAILED("kbusMemAccessBar0Window_HAL call in coherent path\n"); + return NV_ERR_INVALID_STATE; + } + bar0WindowOrig = kbusGetBAR0WindowVidOffset_HAL(pGpu, pKernelBus); bar0WindowOffset = physAddr - bar0WindowOrig; @@ -4327,7 +4564,6 @@ NvBool bRead ) { - NV_STATUS ret = NV_ERR_NOT_SUPPORTED; NvLength copied = 0; NvU8 *pSysmemBuf = pSysmem; NvU64 fbCopyOffset = physAddr; @@ -4344,8 +4580,7 @@ NvU8 *pSource = bRead ? pPramin : pSysmemBuf; NvU8 *pDest = bRead ? pSysmemBuf : pPramin; - ret = kbusSetBAR0WindowVidOffset_HAL(pGpu, pKernelBus, praminFbBase); - NV_ASSERT_OK(ret); + NV_ASSERT_OK_OR_RETURN(kbusSetBAR0WindowVidOffset_HAL(pGpu, pKernelBus, praminFbBase)); // TODO: use MMIO-safe memcopy abstraction if provided portMemCopy(pDest, copySize, pSource, copySize); @@ -4357,7 +4592,7 @@ } while (copied < size); - return ret; + return NV_OK; } /*! @@ -4539,7 +4774,8 @@ // (Re-)bind instance block so host fetches the new VAS state. // Flush to ensure host sees the latest. // - kbusFlush_HAL(pGpu, pKernelBus, BUS_FLUSH_VIDEO_MEMORY); + kbusFlush_HAL(pGpu, pKernelBus, BUS_FLUSH_VIDEO_MEMORY | BUS_FLUSH_USE_PCIE_READ); + kbusSendSysmembar(pGpu, pKernelBus); return NV_OK; } diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/kernel/gpu/bus/arch/maxwell/kern_bus_gm200.c nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/kernel/gpu/bus/arch/maxwell/kern_bus_gm200.c --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/kernel/gpu/bus/arch/maxwell/kern_bus_gm200.c 2023-10-25 20:20:53.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/kernel/gpu/bus/arch/maxwell/kern_bus_gm200.c 2024-03-05 22:13:15.000000000 +0000 @@ -882,7 +882,7 @@ OBJGPU *pParentGpu; NvU64 vaAllocMax; NV_STATUS status = NV_OK; - + VAS_ALLOC_FLAGS flags = {0}; pParentGpu = gpumgrGetParentGPU(pGpu); diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/kernel/gpu/bus/arch/pascal/kern_bus_gp100.c nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/kernel/gpu/bus/arch/pascal/kern_bus_gp100.c --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/kernel/gpu/bus/arch/pascal/kern_bus_gp100.c 2023-10-25 20:20:53.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/kernel/gpu/bus/arch/pascal/kern_bus_gp100.c 2024-03-05 22:13:16.000000000 +0000 @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 2014-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2014-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -21,11 +21,15 @@ * DEALINGS IN THE SOFTWARE. */ +// FIXME XXX +#define NVOC_KERNEL_NVLINK_H_PRIVATE_ACCESS_ALLOWED + #include "core/core.h" #include "gpu/gpu.h" #include "mem_mgr/vaspace.h" #include "gpu/bus/kern_bus.h" #include "gpu/bus/p2p_api.h" +#include "gpu/mem_mgr/mem_mgr.h" #include "kernel/gpu/nvlink/kernel_nvlink.h" /*! @@ -155,6 +159,7 @@ portMemSet(¶ms, 0, sizeof(params)); params.connectionType = NV2080_CTRL_CMD_BUS_SET_P2P_MAPPING_CONNECTION_TYPE_NVLINK; params.peerId = peerId; + params.bEgmPeer = FLD_TEST_DRF(_P2PAPI, _ATTRIBUTES, _REMOTE_EGM, _YES, attributes); params.bUseUuid = NV_FALSE; params.remoteGpuId = pGpu1->gpuId; params.bSpaAccessOnly = FLD_TEST_DRF(_P2PAPI, _ATTRIBUTES, _LINK_TYPE, _SPA, attributes); @@ -184,7 +189,7 @@ * @param[out] peer0 Peer ID (local to remote) * @param[out] peer1 Peer ID (remote to local) * @param[in] attributes Sepcial attributes for the mapping - * + * * return NV_OK on success */ NV_STATUS @@ -203,6 +208,7 @@ NvU32 gpu1Instance = gpuGetInstance(pGpu1); NvBool bLoopback = (pGpu0 == pGpu1); NV_STATUS status = NV_OK; + NvBool bEgmPeer = FLD_TEST_DRF(_P2PAPI, _ATTRIBUTES, _REMOTE_EGM, _YES, attributes); if (peer0 == NULL || peer1 == NULL) { @@ -212,7 +218,7 @@ // Set the default RM mapping if peer id's are not explicitly provided if (*peer0 == BUS_INVALID_PEER || *peer1 == BUS_INVALID_PEER) { - if (bLoopback) + if (bLoopback && !bEgmPeer) { if (pKernelBus0->p2pMapSpecifyId) { @@ -222,22 +228,33 @@ { // If no static mapping is found, set peer id as 0 for loopback *peer0 = *peer1 = 0; + NV_CHECK_OK_OR_RETURN(LEVEL_ERROR, + kbusReserveP2PPeerIds_HAL(pGpu0, pKernelBus0, NVBIT(0))); } + } else { // Get the peer ID pGpu0 should use for P2P over NVLINK to pGpu1 if ((status = kbusGetNvlinkP2PPeerId_HAL(pGpu0, pKernelBus0, pGpu1, pKernelBus1, - peer0)) != NV_OK) + peer0, attributes)) != NV_OK) { return status; } + // EGM loopback + if (bLoopback) + { + // The loopback check here becomes true only in the EGM case + NV_ASSERT_OR_RETURN(bEgmPeer, NV_ERR_INVALID_STATE); + *peer1 = *peer0; + } + else // Get the peer ID pGpu1 should use for P2P over NVLINK to pGpu0 if ((status = kbusGetNvlinkP2PPeerId_HAL(pGpu1, pKernelBus1, pGpu0, pKernelBus0, - peer1)) != NV_OK) + peer1, attributes)) != NV_OK) { return status; } @@ -251,6 +268,11 @@ NV_PRINTF(LEVEL_INFO, "- P2P: Using Default RM mapping for P2P.\n"); } + + if (bEgmPeer) + { + NV_PRINTF(LEVEL_INFO, "EGM peer\n"); + } // // Does the mapping already exist between the given pair of GPUs using the peerIDs // *peer0 and *peer1 respectively ? @@ -295,7 +317,7 @@ // // If we're in loopback mode check for specified peer ID arg from RM or MODS - if (bLoopback && pKernelBus0->p2pMapSpecifyId) + if (!bEgmPeer && bLoopback && pKernelBus0->p2pMapSpecifyId) { if ((pKernelBus0->p2p.busNvlinkMappingRefcountPerPeerId[pKernelBus0->p2pMapPeerId] == 0) && (pKernelBus1->p2p.busNvlinkMappingRefcountPerPeerId[pKernelBus1->p2pMapPeerId] == 0)) @@ -452,7 +474,20 @@ // If mapping refcount to remote GPU1 is 0, this implies the peerID is no // longer used for P2P from GPU0 to GPU1. Update busNvlinkPeerNumberMask // - if (pKernelBus0->p2p.busNvlinkMappingRefcountPerGpu[peerGpuInst] == 0) + // Special case: + // Peers connected through NvSwitch in which case all the peers use + // peer id 0 and the refcount for peer id 0 wouldn't reach 0 until + // P2P between all the peers is destroyed. + // busNvlinkMappingRefcountPerGpu == 0 check is done in this case to remove + // the peer id from busNvlinkPeerNumberMask[peerGpuInst] + // Two peer ids are used to reach the same GPU, one for HBM and one for + // EGM. In that case busNvlinkMappingRefcountPerGpu isn't going to + // reach 0 until both the peer ids are removed. In this case, + // busNvlinkMappingRefcountPerPeerId[peerId] == 0 check is required to + // remove the peer id from busNvlinkPeerNumberMask[peerGpuInst]. + // + if (pKernelBus0->p2p.busNvlinkMappingRefcountPerGpu[peerGpuInst] == 0 || + pKernelBus0->p2p.busNvlinkMappingRefcountPerPeerId[peerId] == 0) { NV_PRINTF(LEVEL_INFO, "Removing mapping for GPU%u peer %u (GPU%u)\n", @@ -547,7 +582,7 @@ status = knvlinkSyncLinkMasksAndVbiosInfo(pGpu0, pKernelNvlink0); if (status != NV_OK) { - NV_ASSERT(status == NV_OK); + NV_ASSERT(status != NV_OK); return status; } @@ -754,7 +789,8 @@ KernelBus *pKernelBus0, OBJGPU *pGpu1, KernelBus *pKernelBus1, - NvU32 *nvlinkPeer + NvU32 *nvlinkPeer, + NvU32 attributes ) { KernelNvlink *pKernelNvlink0 = GPU_GET_KERNEL_NVLINK(pGpu0); @@ -870,6 +906,7 @@ return NV_ERR_IN_USE; } + pKernelBus->p2p.bEgmPeer[peerId] = NV_FALSE; pKernelBus->p2pPcie.busPeer[peerId].bReserved = NV_FALSE; } FOR_EACH_INDEX_IN_MASK_END; diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/kernel/gpu/bus/arch/turing/kern_bus_tu102.c nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/kernel/gpu/bus/arch/turing/kern_bus_tu102.c --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/kernel/gpu/bus/arch/turing/kern_bus_tu102.c 2023-10-25 20:20:53.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/kernel/gpu/bus/arch/turing/kern_bus_tu102.c 2024-03-05 22:13:16.000000000 +0000 @@ -50,12 +50,12 @@ PDB_PROP_KNVLINK_WAR_BUG_3471679_PEERID_FILTERING))) { // - // Get the mask of NvLink peerIds, to exclude them from the + // Get the mask of NvLink peerIds, to exclude them from the // peerIds PCIE P2P is using. // Pre-Ampere GPUs use a static peerId assignment reserved in - // busGetNvlinkP2PPeerId_GP100() and we need to make sure the - // PCIE and nvLink P2P assignments do not collide. - // Make this Windows + Turing only until bug 3471679 is fixed. + // busGetNvlinkP2PPeerId_GP100() and we need to make sure the + // PCIE and nvLink P2P assignments do not collide. + // Make this Windows + Turing only until bug 3471679 is fixed. // nvlinkIdMask = knvlinkGetUniquePeerIdMask_HAL(pGpu, pKernelNvlink); } @@ -63,7 +63,7 @@ for (peerId = 0; peerId < pKernelBus->numPeers; peerId++) { if ((pKernelBus->p2pPcie.busPeer[peerId].refCount == 0) && - (!pKernelBus->p2pPcie.busPeer[peerId].bReserved) && + (!pKernelBus->p2pPcie.busPeer[peerId].bReserved) && ((BIT(peerId) & nvlinkIdMask) == 0)) { return peerId; diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/kernel/gpu/bus/arch/volta/kern_bus_gv100.c nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/kernel/gpu/bus/arch/volta/kern_bus_gv100.c --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/kernel/gpu/bus/arch/volta/kern_bus_gv100.c 2023-10-25 20:20:53.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/kernel/gpu/bus/arch/volta/kern_bus_gv100.c 2024-03-05 22:13:16.000000000 +0000 @@ -50,13 +50,15 @@ { NV_STATUS status = NV_OK; - // Nothing to be done in paravirtualized guest or if we don't want to do CPU reads for flushing. + // Nothing to be done in paravirtualized guest (or CC) or if we don't want to do CPU reads for flushing. if (IS_VIRTUAL_WITHOUT_SRIOV(pGpu) || !kbusIsReadCpuPointerToFlushEnabled(pKernelBus)) { return NV_OK; } + NV_ASSERT_OR_RETURN(!kbusIsBarAccessBlocked(pKernelBus), NV_ERR_INVALID_STATE); + status = memdescCreate(&pKernelBus->pFlushMemDesc, pGpu, RM_PAGE_SIZE, RM_PAGE_SIZE, @@ -136,7 +138,7 @@ PMEMORY_DESCRIPTOR pMemDesc ) { - RmPhysAddr startAddr = memdescGetPhysAddr(pMemDesc, AT_GPU, 0); + RmPhysAddr startAddr = memdescGetPhysAddr(pMemDesc, FORCE_VMMU_TRANSLATION(pMemDesc, AT_GPU), 0); NvU64 size = memdescGetSize(pMemDesc); RmPhysAddr endAddr = startAddr + size - 1; RmPhysAddr rangeStart = 0; @@ -186,7 +188,7 @@ PMEMORY_DESCRIPTOR pMemDesc ) { - RmPhysAddr startAddr = pMemDesc->_pteArray[0] + pMemDesc->PteAdjust; + RmPhysAddr startAddr = memdescGetPhysAddr(pMemDesc, FORCE_VMMU_TRANSLATION(pMemDesc, AT_GPU), 0); NvU64 size = memdescGetSize(pMemDesc); RmPhysAddr endAddr = startAddr + size - 1; NvU32 i = 0; @@ -212,7 +214,7 @@ } // Flush the memory since caller writes to the FB - kbusFlush_HAL(pGpu, GPU_GET_KERNEL_BUS(pGpu), BUS_FLUSH_VIDEO_MEMORY); + kbusFlush_HAL(pGpu, GPU_GET_KERNEL_BUS(pGpu), BUS_FLUSH_VIDEO_MEMORY | BUS_FLUSH_USE_PCIE_READ); return; } diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/kernel/gpu/bus/kern_bus.c nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/kernel/gpu/bus/kern_bus.c --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/kernel/gpu/bus/kern_bus.c 2023-10-25 20:20:53.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/kernel/gpu/bus/kern_bus.c 2024-03-05 22:13:16.000000000 +0000 @@ -393,10 +393,14 @@ NvU32 flags ) { - // we will initialize bar2 to the default big page size of the system - NV_ASSERT_OK_OR_RETURN(kbusInitVirtualBar2_HAL(pGpu, pKernelBus)); - NV_ASSERT_OK_OR_RETURN(kbusSetupCpuPointerForBusFlush_HAL(pGpu, pKernelBus)); - + if (!KBUS_BAR0_PRAMIN_DISABLED(pGpu) && + !kbusIsBarAccessBlocked(pKernelBus) && + !(flags & GPU_STATE_FLAGS_GC6_TRANSITION)) + { + // we will initialize bar2 to the default big page size of the system + NV_ASSERT_OK_OR_RETURN(kbusInitVirtualBar2_HAL(pGpu, pKernelBus)); + NV_ASSERT_OK_OR_RETURN(kbusSetupCpuPointerForBusFlush_HAL(pGpu, pKernelBus)); + } return NV_OK; } @@ -715,10 +719,14 @@ KernelBus *pKernelBus ) { - NV_STATUS status = NV_OK; + NV_STATUS status = NV_OK; PMEMORY_DESCRIPTOR pMemDesc; - GspStaticConfigInfo *pGSCI = GPU_GET_GSP_STATIC_INFO(pGpu); + GspStaticConfigInfo *pGSCI = GPU_GET_GSP_STATIC_INFO(pGpu); + const MMU_FMT_LEVEL *pRootFmt = pKernelBus->bar2[GPU_GFID_PF].pFmt->pRoot; NvU64 entryValue; + MEMORY_DESCRIPTOR *pOldPdb; + + pOldPdb = pKernelBus->virtualBar2[GPU_GFID_PF].pPDB; NV_CHECK_OK_OR_RETURN(LEVEL_ERROR, memdescCreate(&pMemDesc, pGpu, pKernelBus->bar2[GPU_GFID_PF].pageDirSize, RM_PAGE_SIZE, NV_TRUE, @@ -731,16 +739,32 @@ // // BAR2 page table is not yet working at this point, so retrieving the - // PDE3[0] of BAR2 page table via BAR0_WINDOW + // PDE3[0] of BAR2 page table via BAR0_WINDOW or GSP-DMA (in case BARs + // are blocked) // - entryValue = GPU_REG_RD32(pGpu, (NvU32)pKernelBus->bar2[GPU_GFID_PF].bar2OffsetInBar0Window) | + if (kbusIsBarAccessBlocked(pKernelBus)) + { + MemoryManager *pMemoryManager = GPU_GET_MEMORY_MANAGER(pGpu); + TRANSFER_SURFACE surf = {0}; + + surf.pMemDesc = pOldPdb; + surf.offset = 0; + + NV_ASSERT_OK_OR_RETURN( + memmgrMemRead(pMemoryManager, &surf, &entryValue, + pRootFmt->entrySize, TRANSFER_FLAGS_NONE)); + } + else + { + entryValue = GPU_REG_RD32(pGpu, (NvU32)pKernelBus->bar2[GPU_GFID_PF].bar2OffsetInBar0Window) | ((NvU64)GPU_REG_RD32(pGpu, (NvU32)pKernelBus->bar2[GPU_GFID_PF].bar2OffsetInBar0Window + 4) << 32); + } // // Provide the PDE3[0] value to GSP-RM so that GSP-RM can merge CPU-RM's // page table to GSP-RM's page table // - NV_RM_RPC_UPDATE_BAR_PDE(pGpu, NV_RPC_UPDATE_PDE_BAR_2, entryValue, pKernelBus->bar2[GPU_GFID_PF].pFmt->pRoot->virtAddrBitLo, status); + NV_RM_RPC_UPDATE_BAR_PDE(pGpu, NV_RPC_UPDATE_PDE_BAR_2, entryValue, pRootFmt->virtAddrBitLo, status); return NV_OK; } @@ -768,9 +792,9 @@ NvBool kbusCheckEngine_KERNEL ( - OBJGPU *pGpu, - KernelBus *pKernelBus, - ENGDESCRIPTOR engDesc + OBJGPU *pGpu, + KernelBus *pKernelBus, + ENGDESCRIPTOR engDesc ) { NvU32 rmEngineCaps[NVGPU_ENGINE_CAPS_MASK_ARRAY_MAX] = {0}; @@ -786,15 +810,17 @@ return NV_FALSE; } - for (i=0; iengineCaps[i]; } } NV_CHECK_OK_OR_ELSE(status, LEVEL_ERROR, - gpuGetRmEngineTypeCapMask(nv2080EngineCaps, NVGPU_ENGINE_CAPS_MASK_ARRAY_MAX, rmEngineCaps), - return NV_FALSE); + gpuGetRmEngineTypeCapMask(nv2080EngineCaps, + NVGPU_ENGINE_CAPS_MASK_ARRAY_MAX, + rmEngineCaps), + return NV_FALSE); switch (engDesc) { @@ -810,10 +836,7 @@ // (b) RM offload (Kernel RM) where display is supported. // case ENG_KERNEL_DISPLAY: - if (IS_GSP_CLIENT(pGpu)) - return NV_TRUE; - else - return NV_FALSE; + return IS_GSP_CLIENT(pGpu); case ENG_BIF: case ENG_KERNEL_BIF: @@ -833,67 +856,51 @@ return NV_TRUE; case ENG_CE(0): - return (NVGPU_GET_ENGINE_CAPS_MASK(rmEngineCaps, RM_ENGINE_TYPE_COPY0) ? NV_TRUE: NV_FALSE); case ENG_CE(1): - return (NVGPU_GET_ENGINE_CAPS_MASK(rmEngineCaps, RM_ENGINE_TYPE_COPY1) ? NV_TRUE: NV_FALSE); case ENG_CE(2): - return (NVGPU_GET_ENGINE_CAPS_MASK(rmEngineCaps, RM_ENGINE_TYPE_COPY2) ? NV_TRUE: NV_FALSE); case ENG_CE(3): - return (NVGPU_GET_ENGINE_CAPS_MASK(rmEngineCaps, RM_ENGINE_TYPE_COPY3) ? NV_TRUE: NV_FALSE); case ENG_CE(4): - return (NVGPU_GET_ENGINE_CAPS_MASK(rmEngineCaps, RM_ENGINE_TYPE_COPY4) ? NV_TRUE: NV_FALSE); case ENG_CE(5): - return (NVGPU_GET_ENGINE_CAPS_MASK(rmEngineCaps, RM_ENGINE_TYPE_COPY5) ? NV_TRUE: NV_FALSE); case ENG_CE(6): - return (NVGPU_GET_ENGINE_CAPS_MASK(rmEngineCaps, RM_ENGINE_TYPE_COPY6) ? NV_TRUE: NV_FALSE); case ENG_CE(7): - return (NVGPU_GET_ENGINE_CAPS_MASK(rmEngineCaps, RM_ENGINE_TYPE_COPY7) ? NV_TRUE: NV_FALSE); case ENG_CE(8): - return (NVGPU_GET_ENGINE_CAPS_MASK(rmEngineCaps, RM_ENGINE_TYPE_COPY8) ? NV_TRUE: NV_FALSE); case ENG_CE(9): - return (NVGPU_GET_ENGINE_CAPS_MASK(rmEngineCaps, RM_ENGINE_TYPE_COPY9) ? NV_TRUE: NV_FALSE); + return !!NVGPU_GET_ENGINE_CAPS_MASK(rmEngineCaps, + RM_ENGINE_TYPE_COPY(GET_CE_IDX(engDesc))); + case ENG_MSENC(0): - return (NVGPU_GET_ENGINE_CAPS_MASK(rmEngineCaps, RM_ENGINE_TYPE_NVENC0) ? NV_TRUE: NV_FALSE); case ENG_MSENC(1): - return (NVGPU_GET_ENGINE_CAPS_MASK(rmEngineCaps, RM_ENGINE_TYPE_NVENC1) ? NV_TRUE: NV_FALSE); case ENG_MSENC(2): - return (NVGPU_GET_ENGINE_CAPS_MASK(rmEngineCaps, RM_ENGINE_TYPE_NVENC2) ? NV_TRUE: NV_FALSE); + return !!NVGPU_GET_ENGINE_CAPS_MASK(rmEngineCaps, + RM_ENGINE_TYPE_NVENC(GET_MSENC_IDX(engDesc))); case ENG_SEC2: - return (NVGPU_GET_ENGINE_CAPS_MASK(rmEngineCaps, RM_ENGINE_TYPE_SEC2) ? NV_TRUE: NV_FALSE); + return !!NVGPU_GET_ENGINE_CAPS_MASK(rmEngineCaps, + RM_ENGINE_TYPE_SEC2); case ENG_NVDEC(0): - return (NVGPU_GET_ENGINE_CAPS_MASK(rmEngineCaps, RM_ENGINE_TYPE_NVDEC0) ? NV_TRUE: NV_FALSE); case ENG_NVDEC(1): - return (NVGPU_GET_ENGINE_CAPS_MASK(rmEngineCaps, RM_ENGINE_TYPE_NVDEC1) ? NV_TRUE: NV_FALSE); case ENG_NVDEC(2): - return (NVGPU_GET_ENGINE_CAPS_MASK(rmEngineCaps, RM_ENGINE_TYPE_NVDEC2) ? NV_TRUE: NV_FALSE); - case ENG_OFA: - return (NVGPU_GET_ENGINE_CAPS_MASK(rmEngineCaps, RM_ENGINE_TYPE_OFA) ? NV_TRUE: NV_FALSE); case ENG_NVDEC(3): - return (NVGPU_GET_ENGINE_CAPS_MASK(rmEngineCaps, RM_ENGINE_TYPE_NVDEC3) ? NV_TRUE: NV_FALSE); case ENG_NVDEC(4): - return (NVGPU_GET_ENGINE_CAPS_MASK(rmEngineCaps, RM_ENGINE_TYPE_NVDEC4) ? NV_TRUE: NV_FALSE); case ENG_NVDEC(5): - return (NVGPU_GET_ENGINE_CAPS_MASK(rmEngineCaps, RM_ENGINE_TYPE_NVDEC5) ? NV_TRUE: NV_FALSE); case ENG_NVDEC(6): - return (NVGPU_GET_ENGINE_CAPS_MASK(rmEngineCaps, RM_ENGINE_TYPE_NVDEC6) ? NV_TRUE: NV_FALSE); case ENG_NVDEC(7): - return (NVGPU_GET_ENGINE_CAPS_MASK(rmEngineCaps, RM_ENGINE_TYPE_NVDEC7) ? NV_TRUE: NV_FALSE); + return !!NVGPU_GET_ENGINE_CAPS_MASK(rmEngineCaps, + RM_ENGINE_TYPE_NVDEC(GET_NVDEC_IDX(engDesc))); + + case ENG_OFA: + return !!NVGPU_GET_ENGINE_CAPS_MASK(rmEngineCaps, + RM_ENGINE_TYPE_OFA); case ENG_NVJPEG(0): - return (NVGPU_GET_ENGINE_CAPS_MASK(rmEngineCaps, RM_ENGINE_TYPE_NVJPEG0) ? NV_TRUE: NV_FALSE); case ENG_NVJPEG(1): - return (NVGPU_GET_ENGINE_CAPS_MASK(rmEngineCaps, RM_ENGINE_TYPE_NVJPEG1) ? NV_TRUE: NV_FALSE); case ENG_NVJPEG(2): - return (NVGPU_GET_ENGINE_CAPS_MASK(rmEngineCaps, RM_ENGINE_TYPE_NVJPEG2) ? NV_TRUE: NV_FALSE); case ENG_NVJPEG(3): - return (NVGPU_GET_ENGINE_CAPS_MASK(rmEngineCaps, RM_ENGINE_TYPE_NVJPEG3) ? NV_TRUE: NV_FALSE); case ENG_NVJPEG(4): - return (NVGPU_GET_ENGINE_CAPS_MASK(rmEngineCaps, RM_ENGINE_TYPE_NVJPEG4) ? NV_TRUE: NV_FALSE); case ENG_NVJPEG(5): - return (NVGPU_GET_ENGINE_CAPS_MASK(rmEngineCaps, RM_ENGINE_TYPE_NVJPEG5) ? NV_TRUE: NV_FALSE); case ENG_NVJPEG(6): - return (NVGPU_GET_ENGINE_CAPS_MASK(rmEngineCaps, RM_ENGINE_TYPE_NVJPEG6) ? NV_TRUE: NV_FALSE); case ENG_NVJPEG(7): - return (NVGPU_GET_ENGINE_CAPS_MASK(rmEngineCaps, RM_ENGINE_TYPE_NVJPEG7) ? NV_TRUE: NV_FALSE); + return !!NVGPU_GET_ENGINE_CAPS_MASK(rmEngineCaps, + RM_ENGINE_TYPE_NVJPEG(GET_NVJPEG_IDX(engDesc))); + case ENG_GR(1): case ENG_GR(2): case ENG_GR(3): @@ -906,10 +913,10 @@ NV_ASSERT_OR_RETURN(pKernelFifo != NULL, NV_FALSE); - if (kfifoCheckEngine_HAL(pGpu, pKernelFifo, engDesc, &bSupported) == NV_OK) - return bSupported; - else - return NV_FALSE; + return (kfifoCheckEngine_HAL(pGpu, pKernelFifo, + engDesc, + &bSupported) == NV_OK && + bSupported); } case ENG_INVALID: @@ -956,24 +963,17 @@ OBJSYS *pSys = SYS_GET_INSTANCE(); OBJCL *pCl = SYS_GET_CL(pSys); NvU8 tempCaps[NV0080_CTRL_HOST_CAPS_TBL_SIZE], temp; - NvBool bVirtualP2P; NvBool bExplicitCacheFlushRequired; NV_ASSERT(!gpumgrGetBcEnabledStatus(pGpu)); portMemSet(tempCaps, 0, NV0080_CTRL_HOST_CAPS_TBL_SIZE); - /*! On KEPLER+, mailbox protocol based P2P transactions goes through virtual to - * physical translation (on request side) */ - bVirtualP2P = IsdMAXWELLorBetter(pGpu); - if (bVirtualP2P) - RMCTRL_SET_CAP(tempCaps, NV0080_CTRL_HOST_CAPS, _VIRTUAL_P2P); - /*! DMAs to/from cached memory need to have the cache flushed explicitly */ - bExplicitCacheFlushRequired = NVCPU_IS_ARM && + bExplicitCacheFlushRequired = NVCPU_IS_ARM && (RMCFG_FEATURE_PLATFORM_UNIX || RMCFG_FEATURE_PLATFORM_MODS_UNIX); if (bExplicitCacheFlushRequired || - (!pCl->getProperty(pCL, PDB_PROP_CL_IS_CHIPSET_IO_COHERENT))) + (!pCl->getProperty(pCl, PDB_PROP_CL_IS_CHIPSET_IO_COHERENT))) RMCTRL_SET_CAP(tempCaps, NV0080_CTRL_HOST_CAPS, _EXPLICIT_CACHE_FLUSH_REQD); if ((pCl->FHBBusInfo.vendorID == PCI_VENDOR_ID_NVIDIA) && @@ -1000,8 +1000,6 @@ RMCTRL_AND_CAP(pHostCaps, tempCaps, temp, NV0080_CTRL_HOST_CAPS, _P2P_8_WAY); RMCTRL_AND_CAP(pHostCaps, tempCaps, temp, - NV0080_CTRL_HOST_CAPS, _VIRTUAL_P2P); - RMCTRL_AND_CAP(pHostCaps, tempCaps, temp, NV0080_CTRL_HOST_CAPS, _GPU_COHERENT_MAPPING_SUPPORTED); RMCTRL_OR_CAP(pHostCaps, tempCaps, temp, @@ -1043,7 +1041,8 @@ NvHandle hMemory, NvU64 offset, NvU64 size, - NvU64 *pBar1Va + NvU64 *pBar1Va, + Device *pDevice ) { NV_STATUS status; @@ -1077,7 +1076,7 @@ status = kbusMapFbAperture_HAL(pGpu, pKernelBus, pMemDesc, offset, &fbApertureOffset, &fbApertureLength, - BUS_MAP_FB_FLAGS_MAP_UNICAST, hClient); + BUS_MAP_FB_FLAGS_MAP_UNICAST, pDevice); if (status != NV_OK) { return status; @@ -1209,9 +1208,16 @@ KernelBus *pKernelBus0, OBJGPU *pGpu1, KernelBus *pKernelBus1, - NvU32 *nvlinkPeer + NvU32 *nvlinkPeer, + NvU32 flags ) { + *nvlinkPeer = kbusGetPeerId_HAL(pGpu0, pKernelBus0, pGpu1); + if (*nvlinkPeer != BUS_INVALID_PEER) + { + return NV_OK; + } + *nvlinkPeer = kbusGetUnusedPeerId_HAL(pGpu0, pKernelBus0); // If could not find a free peer ID, return error @@ -1243,3 +1249,11 @@ return (pKernelBus->totalP2pObjectsAliveRefCount > 0); } +/** + * @brief Setup VF BAR2 during hibernate resume + * + * @param[in] pGpu + * @param[in] pKernelBus + * @param[in] flags + */ + diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/kernel/gpu/bus/kern_bus_ctrl.c nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/kernel/gpu/bus/kern_bus_ctrl.c --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/kernel/gpu/bus/kern_bus_ctrl.c 2023-10-25 20:20:53.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/kernel/gpu/bus/kern_bus_ctrl.c 2024-03-05 22:13:16.000000000 +0000 @@ -83,8 +83,8 @@ static NV_STATUS _getAspmL1FlagsSendRpc ( - OBJGPU *pGpu, - NvBool *bCyaMaskL1, + OBJGPU *pGpu, + NvBool *bCyaMaskL1, NvBool *bEnableAspmDtL1 ) { @@ -656,3 +656,15 @@ return NV_OK; } +NV_STATUS +subdeviceCtrlCmdBusSysmemAccess_IMPL +( + Subdevice* pSubdevice, + NV2080_CTRL_BUS_SYSMEM_ACCESS_PARAMS* pParams +) +{ + OBJGPU *pGpu = GPU_RES_GET_GPU(pSubdevice); + KernelBif *pKernelBif = GPU_GET_KERNEL_BIF(pGpu); + + return kbifDisableSysmemAccess_HAL(pGpu, pKernelBif, pParams->bDisable); +} diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/kernel/gpu/bus/kern_bus_vbar2.c nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/kernel/gpu/bus/kern_bus_vbar2.c --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/kernel/gpu/bus/kern_bus_vbar2.c 2023-10-25 20:20:53.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/kernel/gpu/bus/kern_bus_vbar2.c 2024-03-05 22:13:16.000000000 +0000 @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 2004-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2004-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -384,7 +384,7 @@ pMemDesc = pKernelBus->virtualBar2[gfid].pPageLevelsMemDesc; - if (KBUS_BAR2_TUNNELLED(pKernelBus)) + if (KBUS_BAR2_TUNNELLED(pKernelBus) || kbusIsBarAccessBlocked(pKernelBus)) { return NV_OK; } @@ -441,7 +441,7 @@ pMemDesc = pKernelBus->virtualBar2[gfid].pPageLevelsMemDescForBootstrap; - if (KBUS_BAR2_TUNNELLED(pKernelBus)) + if (KBUS_BAR2_TUNNELLED(pKernelBus) || kbusIsBarAccessBlocked(pKernelBus)) { return NV_OK; } @@ -870,7 +870,7 @@ return NULL; } - return portMemAllocNonPaged((NvU32)pMemDesc->Size); + return portMemAllocNonPaged(pMemDesc->Size); } /*! @@ -897,6 +897,18 @@ NvU32 flags ) { + // + // Fail the mapping when BAR2 access to CPR vidmem is blocked (for HCC) + // It is however legal to allow non-CPR vidmem to be mapped to BAR2 + // + if (kbusIsBarAccessBlocked(pKernelBus) && + !memdescGetFlag(pMemDesc, MEMDESC_FLAGS_ALLOC_IN_UNPROTECTED_MEMORY)) + { + os_dump_stack(); + NV_PRINTF(LEVEL_ERROR, "Cannot map/unmap CPR vidmem into/from BAR2\n"); + return NULL; + } + if (API_GPU_IN_RESET_SANITY_CHECK(pGpu)) { // @@ -976,7 +988,7 @@ ) { portMemFree(*pCpuPtr); - kbusFlush_HAL(pGpu, pKernelBus, kbusGetFlushAperture(pKernelBus, memdescGetAddressSpace(pMemDesc))); + kbusFlush_HAL(pGpu, pKernelBus, kbusGetFlushAperture(pKernelBus, memdescGetAddressSpace(pMemDesc)) | BUS_FLUSH_USE_PCIE_READ); } /*! @@ -1007,6 +1019,18 @@ ) { // + // Fail the mapping when BAR2 access to CPR vidmem is blocked (for HCC) + // It is however legal to allow non-CPR vidmem to be mapped to BAR2 + // + if (kbusIsBarAccessBlocked(pKernelBus) && + !memdescGetFlag(pMemDesc, MEMDESC_FLAGS_ALLOC_IN_UNPROTECTED_MEMORY)) + { + NV_ASSERT(0); + NV_PRINTF(LEVEL_ERROR, "Cannot map/unmap CPR vidmem into/from BAR2\n"); + return; + } + + // // Free the dummy data we allocated for handling a reset GPU. // Let a map created before the reset go through the normal path // to clear out the memory. diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/kernel/gpu/bus/p2p.c nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/kernel/gpu/bus/p2p.c --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/kernel/gpu/bus/p2p.c 2023-10-25 20:20:54.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/kernel/gpu/bus/p2p.c 2024-03-05 22:13:16.000000000 +0000 @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 2011-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2011-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -32,13 +32,14 @@ #include "mem_mgr/vaspace.h" #include "gpu/bus/third_party_p2p.h" #include "gpu/device/device.h" +#include "rmapi/rs_utils.h" #include "vgpu/rpc.h" #include "vgpu/vgpu_events.h" #include "gpu/bus/kern_bus.h" #include "class/cl503c.h" -static NvBool _isSpaceAvailableForBar1P2PMapping(OBJGPU *, Subdevice *, NvHandle, NvU64); +static NvBool _isSpaceAvailableForBar1P2PMapping(OBJGPU *, Subdevice *, RsClient *, NvU64); static NV_STATUS RmP2PValidateSubDevice @@ -139,7 +140,7 @@ NvU64 address, NvU64 length, NvU64 offset, - NvHandle hClient, + RsClient *pClient, PCLI_THIRD_PARTY_P2P_VIDMEM_INFO pVidmemInfo, CLI_THIRD_PARTY_P2P_MAPPING_EXTENT_INFO_LIST *pList, MEMORY_DESCRIPTOR *pMemDesc, @@ -155,14 +156,10 @@ NV_STATUS status; KernelBus *pKernelBus; PCLI_THIRD_PARTY_P2P_MAPPING_EXTENT_INFO pExtentInfoTmp; - RsClient *pClient; Device *pDevice; NvBool bGpuLockTaken = (rmDeviceGpuLockIsOwner(gpuGetInstance(pGpu)) || rmGpuLockIsOwner()); - status = serverGetClientUnderLock(&g_resServ, hClient, &pClient); - NV_ASSERT_OR_RETURN(status == NV_OK, NV_ERR_INVALID_ARGUMENT); - status = deviceGetByGpu(pClient, pGpu, NV_TRUE, &pDevice); NV_ASSERT_OR_RETURN(status == NV_OK, NV_ERR_INVALID_STATE); @@ -194,7 +191,7 @@ if (IS_VIRTUAL(pGpu) && gpuIsWarBug200577889SriovHeavyEnabled(pGpu)) { - NV_RM_RPC_MAP_MEMORY(pGpu, hClient, + NV_RM_RPC_MAP_MEMORY(pGpu, pClient->hClient, RES_GET_HANDLE(pDevice), pVidmemInfo->hMemory, offset, @@ -216,7 +213,7 @@ &fbApertureOffset, &fbApertureMapLength, BUS_MAP_FB_FLAGS_MAP_UNICAST, - hClient); + pDevice); if (!bGpuLockTaken) { @@ -256,7 +253,7 @@ { if (IS_VIRTUAL(pGpu) && gpuIsWarBug200577889SriovHeavyEnabled(pGpu)) { - NV_RM_RPC_UNMAP_MEMORY(pGpu, hClient, + NV_RM_RPC_UNMAP_MEMORY(pGpu, pClient->hClient, RES_GET_HANDLE(pDevice), pVidmemInfo->hMemory, 0, @@ -307,7 +304,6 @@ ( NvU64 address, NvU64 length, - NvHandle hClient, CLI_THIRD_PARTY_P2P_MAPPING_EXTENT_INFO_LIST *pList, MEMORY_DESCRIPTOR *pMemDesc, OBJGPU *pGpu, @@ -353,7 +349,7 @@ static NV_STATUS RmThirdPartyP2PMappingFree ( - NvHandle hClient, + RsClient *pClient, OBJGPU *pGpu, PCLI_THIRD_PARTY_P2P_VIDMEM_INFO pVidmemInfo, PCLI_THIRD_PARTY_P2P_INFO pThirdPartyP2PInfo, @@ -369,7 +365,6 @@ NvU64 startOffset; PCLI_THIRD_PARTY_P2P_MAPPING_EXTENT_INFO pExtentInfo = NULL; PCLI_THIRD_PARTY_P2P_MAPPING_EXTENT_INFO pExtentInfoNext = NULL; - RsClient *pClient; Device *pDevice; NvBool bGpuLockTaken; NvBool bVgpuRpc; @@ -382,9 +377,6 @@ NV_ASSERT_OR_RETURN((pSubDevice != NULL), NV_ERR_INVALID_ARGUMENT); NV_ASSERT_OR_RETURN((pThirdPartyP2PInfo != NULL), NV_ERR_INVALID_ARGUMENT); - status = serverGetClientUnderLock(&g_resServ, hClient, &pClient); - NV_ASSERT_OR_RETURN(status == NV_OK, NV_ERR_INVALID_ARGUMENT); - status = deviceGetByGpu(pClient, pGpu, NV_TRUE, &pDevice); NV_ASSERT_OR_RETURN(status == NV_OK, NV_ERR_INVALID_STATE); @@ -418,7 +410,7 @@ { if (bVgpuRpc) { - NV_RM_RPC_UNMAP_MEMORY(pGpu, hClient, + NV_RM_RPC_UNMAP_MEMORY(pGpu, pClient->hClient, RES_GET_HANDLE(pDevice), pVidmemInfo->hMemory, 0, @@ -469,7 +461,7 @@ NvU64 address, NvU64 length, NvU64 offset, - NvHandle hClient, + RsClient *pClient, PCLI_THIRD_PARTY_P2P_VIDMEM_INFO pVidmemInfo, NvU64 **ppPhysicalAddresses, NvU32 **ppWreqMbH, @@ -543,7 +535,7 @@ if (!bFound) { // Check if there is still space in BAR1 to map this length - if (!_isSpaceAvailableForBar1P2PMapping(pGpu, pSubDevice, hClient, lengthReq)) + if (!_isSpaceAvailableForBar1P2PMapping(pGpu, pSubDevice, pClient, lengthReq)) { NV_PRINTF(LEVEL_ERROR, "no space for BAR1 mappings, length: 0x%llx \n", lengthReq); @@ -554,7 +546,7 @@ pMemDesc = pVidmemInfo->pMemDesc; status = _createThirdPartyP2PMappingExtent( - address, lengthReq, offset, hClient, + address, lengthReq, offset, pClient, pVidmemInfo, &pVidmemInfo->mappingExtentList, pMemDesc, pGpu, pSubDevice, &pExtentInfo, @@ -568,10 +560,8 @@ { pMemDesc = pExtentInfo->pMemDesc; status = _reuseThirdPartyP2PMappingExtent( - address, lengthReq, hClient, - &pVidmemInfo->mappingExtentList, pMemDesc, pGpu, - pSubDevice, &pExtentInfo, - &mappingOffset, &mappingLength); + address, lengthReq, &pVidmemInfo->mappingExtentList, pMemDesc, + pGpu, pSubDevice, &pExtentInfo, &mappingOffset, &mappingLength); if (NV_OK != status) { goto out; @@ -611,7 +601,7 @@ out: if (status != NV_OK) { - RmThirdPartyP2PMappingFree(hClient, pGpu, pVidmemInfo, pThirdPartyP2PInfo, + RmThirdPartyP2PMappingFree(pClient, pGpu, pVidmemInfo, pThirdPartyP2PInfo, pSubDevice, pMappingInfo); } return status; @@ -624,7 +614,6 @@ NV_STATUS RmThirdPartyP2PNVLinkGetPages ( OBJGPU *pGpu, - OBJVASPACE *pVAS, NvU64 address, NvU64 length, NvU64 offset, @@ -647,10 +636,13 @@ lastAddress = (address + length - 1); while (address < lastAddress) { - physAddr = memdescGetPhysAddr(pMemDesc, VAS_ADDRESS_TRANSLATION(pVAS), offset); + physAddr = memdescGetPhysAddr(pMemDesc, AT_CPU, offset); - (*ppWreqMbH)[entries] = 0; - (*ppRreqMbH)[entries] = 0; + if ((ppWreqMbH != NULL) && (ppRreqMbH != NULL)) + { + (*ppWreqMbH)[entries] = 0; + (*ppRreqMbH)[entries] = 0; + } (*ppPhysicalAddresses)[entries] = pKernelMemorySystem->coherentCpuFbBase + physAddr; @@ -673,8 +665,7 @@ NvU64 address, NvU64 length, NvU64 offset, - NvHandle hClient, - NvHandle hThirdPartyP2P, + ThirdPartyP2P *pThirdPartyP2P, NvU64 **ppPhysicalAddresses, NvU32 **ppWreqMbH, NvU32 **ppRreqMbH, @@ -691,33 +682,17 @@ { NV_STATUS status; MEMORY_DESCRIPTOR *pMemDesc; - Device *pDevice; - RsClient *pClient; - OBJVASPACE *pVAS; + RsClient *pClient = RES_GET_CLIENT(pThirdPartyP2P); CLI_THIRD_PARTY_P2P_MAPPING_INFO *pMappingInfo = NULL; - status = serverGetClientUnderLock(&g_resServ, hClient, &pClient); - NV_ASSERT_OR_RETURN(status == NV_OK, NV_ERR_INVALID_ARGUMENT); - - status = deviceGetByGpu(pClient, pGpu, NV_TRUE, &pDevice); - NV_ASSERT_OR_RETURN(status == NV_OK, NV_ERR_INVALID_STATE); - - if (pVASpaceInfo != NULL) - { - NV_ASSERT_OK_OR_RETURN( - vaspaceGetByHandleOrDeviceDefault(pClient, RES_GET_HANDLE(pDevice), - pVASpaceInfo->hVASpace, &pVAS)); - } - pMemDesc = pVidmemInfo->pMemDesc; - status = CliGetThirdPartyP2PMappingInfoFromKey(hClient, - hThirdPartyP2P, pVidmemInfo->hMemory, - pPlatformData, &pMappingInfo); + status = CliGetThirdPartyP2PMappingInfoFromKey(pThirdPartyP2P, + pVidmemInfo->hMemory, pPlatformData, &pMappingInfo); if (status == NV_ERR_OBJECT_NOT_FOUND) { - status = CliAddThirdPartyP2PMappingInfo(hClient, hThirdPartyP2P, - pVidmemInfo->hMemory, pPlatformData, pFreeCallback, pData, &pMappingInfo); + status = CliAddThirdPartyP2PMappingInfo(pThirdPartyP2P, pVidmemInfo->hMemory, + pPlatformData, pFreeCallback, pData, &pMappingInfo); } if (status != NV_OK) { @@ -727,14 +702,14 @@ switch(pThirdPartyP2PInfo->type) { case CLI_THIRD_PARTY_P2P_TYPE_BAR1: - status = RmThirdPartyP2PBAR1GetPages(address, length, offset, hClient, + status = RmThirdPartyP2PBAR1GetPages(address, length, offset, pClient, pVidmemInfo, ppPhysicalAddresses, ppWreqMbH, ppRreqMbH, pEntries, pGpu, pSubDevice, pMappingInfo, pThirdPartyP2PInfo); break; case CLI_THIRD_PARTY_P2P_TYPE_NVLINK: - status = RmThirdPartyP2PNVLinkGetPages(pGpu, pVAS, address, length, + status = RmThirdPartyP2PNVLinkGetPages(pGpu, address, length, offset, pMemDesc, ppWreqMbH, ppRreqMbH, ppPhysicalAddresses, pEntries); @@ -756,19 +731,18 @@ static NV_STATUS RmP2PValidateAddressRangeOrGetPages ( - NvU64 address, - NvU64 length, - NvHandle hClient, - NvHandle hThirdPartyP2P, - NvU64 **ppPhysicalAddresses, - NvU32 **ppWreqMbH, - NvU32 **ppRreqMbH, - NvU32 *pEntries, - void *pPlatformData, - void (*pFreeCallback)(void *pData), - void *pData, - OBJGPU *pGpu, - Subdevice *pSubDevice, + NvU64 address, + NvU64 length, + ThirdPartyP2P *pThirdPartyP2P, + NvU64 **ppPhysicalAddresses, + NvU32 **ppWreqMbH, + NvU32 **ppRreqMbH, + NvU32 *pEntries, + void *pPlatformData, + void (*pFreeCallback)(void *pData), + void *pData, + OBJGPU *pGpu, + Subdevice *pSubDevice, PCLI_THIRD_PARTY_P2P_VASPACE_INFO pVASpaceInfo, PCLI_THIRD_PARTY_P2P_INFO pThirdPartyP2PInfo ) @@ -777,9 +751,8 @@ NV_STATUS status; NvU64 offset; - status = CliGetThirdPartyP2PVidmemInfoFromAddress(hClient, - hThirdPartyP2P, address, length, &offset, - &pVidmemInfo); + status = CliGetThirdPartyP2PVidmemInfoFromAddress(pThirdPartyP2P, + address, length, &offset, &pVidmemInfo); if (status != NV_OK) { return status; @@ -791,10 +764,9 @@ return NV_OK; } - status = RmP2PGetPagesUsingVidmemInfo(address, length, offset, hClient, - hThirdPartyP2P, ppPhysicalAddresses, - ppWreqMbH, ppRreqMbH, pEntries, - pPlatformData, pFreeCallback, + status = RmP2PGetPagesUsingVidmemInfo(address, length, offset, pThirdPartyP2P, + ppPhysicalAddresses, ppWreqMbH, ppRreqMbH, + pEntries, pPlatformData, pFreeCallback, pData, pGpu, pSubDevice, pVASpaceInfo, pThirdPartyP2PInfo, pVidmemInfo); if (status != NV_OK) @@ -820,12 +792,9 @@ NV_STATUS status; PCLI_THIRD_PARTY_P2P_VASPACE_INFO pVASpaceInfo = NULL; NvBool bFound = NV_FALSE; - NvHandle hClient, hThirdPartyP2P; Subdevice *pSubdevice; OBJGPU *pGpu; - hClient = pThirdPartyP2P->hClient; - hThirdPartyP2P = pThirdPartyP2P->hThirdPartyP2P; pSubdevice = pThirdPartyP2P->pSubdevice; status = RmP2PValidateSubDevice(pThirdPartyP2P, &pGpu); @@ -856,12 +825,11 @@ // Passing NULL for arguments to prevent looking up or // updating mapping info in range validation. // - status = RmP2PValidateAddressRangeOrGetPages(address, length, hClient, - hThirdPartyP2P, NULL, NULL, - NULL, NULL, pPlatformData, - pFreeCallback, pData, pGpu, - pSubdevice, pVASpaceInfo, - pThirdPartyP2P); + status = RmP2PValidateAddressRangeOrGetPages(address, length, pThirdPartyP2P, + NULL, NULL, NULL, NULL, + pPlatformData, pFreeCallback, + pData, pGpu, pSubdevice, + pVASpaceInfo, pThirdPartyP2P); if ((NV_OK == status) && bFound) { return NV_ERR_GENERIC; @@ -967,7 +935,7 @@ static NvBool _isSpaceAvailableForBar1P2PMapping( OBJGPU *pGpu, Subdevice *pSubDevice, - NvHandle hClient, + RsClient *pClient, NvU64 length ) { @@ -977,7 +945,9 @@ NV_STATUS status; MemoryManager *pMemoryManager = GPU_GET_MEMORY_MANAGER(pGpu); - status = memmgrGetBAR1InfoForClient_HAL(pGpu, pMemoryManager, hClient, &bar1Info); + status = memmgrGetBAR1InfoForDevice(pGpu, pMemoryManager, + GPU_RES_GET_DEVICE(pSubDevice), + &bar1Info); if (status != NV_OK) return NV_FALSE; @@ -1010,7 +980,6 @@ ) { NV_STATUS status; - NvHandle hClient, hThirdPartyP2P; OBJGPU *pGpu; ThirdPartyP2P *pThirdPartyP2P; Subdevice *pSubdevice; @@ -1038,12 +1007,12 @@ &pVASpaceInfo, NULL); } + if (status != NV_OK) { return status; } - hClient = pThirdPartyP2P->hClient; - hThirdPartyP2P = pThirdPartyP2P->hThirdPartyP2P; + pSubdevice = pThirdPartyP2P->pSubdevice; if ((pThirdPartyP2P->type == CLI_THIRD_PARTY_P2P_TYPE_PROPRIETARY) && @@ -1074,11 +1043,10 @@ goto failed; } - status = RmP2PValidateAddressRangeOrGetPages(address, length, hClient, - hThirdPartyP2P, &pPhysicalAddresses, - &pWreqMbH, &pRreqMbH, pEntries, - pPlatformData, pFreeCallback, - pData, pGpu, pSubdevice, + status = RmP2PValidateAddressRangeOrGetPages(address, length, pThirdPartyP2P, + &pPhysicalAddresses, &pWreqMbH, + &pRreqMbH, pEntries, pPlatformData, + pFreeCallback, pData, pGpu, pSubdevice, pVASpaceInfo, pThirdPartyP2P); if (status != NV_OK) { @@ -1132,8 +1100,7 @@ // Get user client's ThirdPartyP2P's VidmemInfo // Needed to get user's offset and hMemory // - status = CliGetThirdPartyP2PVidmemInfoFromAddress(pThirdPartyP2P->hClient, - pThirdPartyP2P->hThirdPartyP2P, + status = CliGetThirdPartyP2PVidmemInfoFromAddress(pThirdPartyP2P, address, length, &offset, @@ -1152,8 +1119,7 @@ // of the VA. This is because the VA could have been reassigned to another // phys allocation. // - status = CliGetThirdPartyP2PVidmemInfoFromId(pThirdPartyP2PInternal->hClient, - pThirdPartyP2PInternal->hThirdPartyP2P, + status = CliGetThirdPartyP2PVidmemInfoFromId(pThirdPartyP2PInternal, pVidmemInfo->id, &pVidmemInfoInternal); if (status == NV_OK) @@ -1202,8 +1168,7 @@ // and length = 1. This is because keyStart and keyEnd for internal // AddressRangeTree should be the user's VidmemInfo ID. // - status = CliAddThirdPartyP2PVidmemInfo(pMemoryManager->hClient, - pThirdPartyP2PInternal->hThirdPartyP2P, + status = CliAddThirdPartyP2PVidmemInfo(pThirdPartyP2PInternal, hMemoryDuped, pVidmemInfo->id, 1, @@ -1215,8 +1180,7 @@ } // Fetch the newly added VidmemInfo to return. - status = CliGetThirdPartyP2PVidmemInfoFromId(pThirdPartyP2PInternal->hClient, - pThirdPartyP2PInternal->hThirdPartyP2P, + status = CliGetThirdPartyP2PVidmemInfoFromId(pThirdPartyP2PInternal, pVidmemInfo->id, &pVidmemInfoInternal); if (status != NV_OK) @@ -1245,6 +1209,7 @@ void *pGpuInfo ) { + RsResourceRef *pResourceRef; OBJGPU *pGpu = (OBJGPU *) pGpuInfo; ThirdPartyP2P *pThirdPartyP2P = NULL; ThirdPartyP2P *pThirdPartyP2PInternal = NULL; @@ -1261,14 +1226,21 @@ return status; } - status = CliGetThirdPartyP2PInfo(pMemoryManager->hClient, - pMemoryManager->hThirdPartyP2P, - &pThirdPartyP2PInternal); + status = serverutilGetResourceRef(pMemoryManager->hClient, + pMemoryManager->hThirdPartyP2P, + &pResourceRef); if (status != NV_OK) { return status; } + pThirdPartyP2PInternal = dynamicCast(pResourceRef->pResource, ThirdPartyP2P); + + if (status != NV_OK) + { + return NV_ERR_INVALID_OBJECT_HANDLE; + } + pVidmemInfo = _createOrReuseVidmemInfoPersistent(pGpu, address, length, &offset, pThirdPartyP2P, pThirdPartyP2PInternal); @@ -1278,8 +1250,7 @@ } status = RmP2PGetPagesUsingVidmemInfo(address, length, offset, - pMemoryManager->hClient, - pThirdPartyP2PInternal->hThirdPartyP2P, + pThirdPartyP2PInternal, &pPhysicalAddresses, NULL, NULL, pEntries, pPlatformData, NULL, NULL, pGpu, pThirdPartyP2PInternal->pSubdevice, @@ -1387,6 +1358,7 @@ // Unsupported configs/platforms for persistent mappings if (IS_MIG_ENABLED(pGpu) || + gpuIsApmFeatureEnabled(pGpu) || IS_VIRTUAL(pGpu) || NVCPU_IS_PPC64LE || pMemoryManager->hThirdPartyP2P == 0) @@ -1409,7 +1381,6 @@ ) { NV_STATUS status; - NvHandle hClient, hThirdPartyP2P; ThirdPartyP2P *pThirdPartyP2P; PCLI_THIRD_PARTY_P2P_VASPACE_INFO pVASpaceInfo = NULL; PCLI_THIRD_PARTY_P2P_VIDMEM_INFO pVidmemInfo; @@ -1434,21 +1405,14 @@ return status; } - hClient = pThirdPartyP2P->hClient; - hThirdPartyP2P = pThirdPartyP2P->hThirdPartyP2P; - - status = CliGetThirdPartyP2PVidmemInfoFromAddress(hClient, hThirdPartyP2P, - address, length, &offset, - &pVidmemInfo); + status = CliGetThirdPartyP2PVidmemInfoFromAddress(pThirdPartyP2P, address, + length, &offset, &pVidmemInfo); if (status != NV_OK) { return status; } - hClient = pThirdPartyP2P->hClient; - hThirdPartyP2P = pThirdPartyP2P->hThirdPartyP2P; - - return CliRegisterThirdPartyP2PMappingCallback(hClient, hThirdPartyP2P, + return CliRegisterThirdPartyP2PMappingCallback(pThirdPartyP2P, pVidmemInfo->hMemory, pPlatformData, pFreeCallback, pData); diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/kernel/gpu/bus/p2p_api.c nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/kernel/gpu/bus/p2p_api.c --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/kernel/gpu/bus/p2p_api.c 2023-10-25 20:20:54.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/kernel/gpu/bus/p2p_api.c 2024-03-05 22:13:16.000000000 +0000 @@ -26,6 +26,7 @@ #include "gpu/bus/kern_bus.h" #include "gpu/bus/p2p_api.h" #include "gpu/bus/third_party_p2p.h" +#include "gpu/mem_mgr/mem_mgr.h" #include "platform/p2p/p2p_caps.h" #include "kernel/gpu/nvlink/kernel_nvlink.h" #include "nvRmReg.h" @@ -36,6 +37,208 @@ #include "class/cl503b.h" #include //FERMI_VASPACE_A +/*! + * @brief Helper function to reserve peer ids in non-GSP offload vGPU case. + */ +static +NV_STATUS +_p2papiReservePeerID +( + OBJGPU *pLocalGpu, + KernelBus *pLocalKernelBus, + OBJGPU *pRemoteGpu, + KernelBus *pRemoteKernelBus, + NV503B_ALLOC_PARAMETERS *pNv503bAllocParams, + P2PApi *pP2PApi, + NvU32 *peer1, + NvU32 *peer2, + NvBool bEgmPeer, + NvBool bSpaAccessOnly +) +{ + NvU32 gpu0Instance = gpuGetInstance(pLocalGpu); + NvU32 gpu1Instance = gpuGetInstance(pRemoteGpu); + + // loopback request + if ( + !bEgmPeer && + (pNv503bAllocParams->hSubDevice == pNv503bAllocParams->hPeerSubDevice)) + { + *peer1 = *peer2 = 0; + + // Reserve the peer1 ID for NVLink use + NV_CHECK_OK_OR_RETURN(LEVEL_ERROR, + kbusReserveP2PPeerIds_HAL(pLocalGpu, pLocalKernelBus, NVBIT(*peer1))); + } + else + { + if (bEgmPeer) + { + // Check if a peer ID is already allocated for P2P from pLocalGpu to pRemoteGpu + *peer1 = kbusGetEgmPeerId_HAL(pLocalGpu, pLocalKernelBus, pRemoteGpu); + + // Check if a peer ID is already allocated for P2P from pRemoteGpu to pLocalGpu + *peer2 = kbusGetEgmPeerId_HAL(pRemoteGpu, pRemoteKernelBus, pLocalGpu); + } + else + { + // Check if a peer ID is already allocated for P2P from pLocalGpu to pRemoteGpu + *peer1 = kbusGetPeerId_HAL(pLocalGpu, pLocalKernelBus, pRemoteGpu); + + // Check if a peer ID is already allocated for P2P from pRemoteGpu to pLocalGpu + *peer2 = kbusGetPeerId_HAL(pRemoteGpu, pRemoteKernelBus, pLocalGpu); + } + } + + if (*peer1 != BUS_INVALID_PEER && *peer2 != BUS_INVALID_PEER) + { + goto update_mask; + } + else if (*peer1 == BUS_INVALID_PEER && *peer2 == BUS_INVALID_PEER) + { + // Get the peer ID pGpu0 should use for P2P over NVLINK to pGpu1i + *peer1 = kbusGetUnusedPeerId_HAL(pLocalGpu, pLocalKernelBus); + // If could not find a free peer ID, return error + if (*peer1 == BUS_INVALID_PEER) + { + NV_PRINTF(LEVEL_ERROR, + "GPU%d: peerID not available for NVLink P2P\n", + gpu0Instance); + return NV_ERR_GENERIC; + } + + // Reserve the peer ID for NVLink use + NV_CHECK_OK_OR_RETURN(LEVEL_ERROR, + kbusReserveP2PPeerIds_HAL(pLocalGpu, pLocalKernelBus, NVBIT(*peer1))); + + if (pNv503bAllocParams->hSubDevice == pNv503bAllocParams->hPeerSubDevice) + { + // The loopback check here becomes true only in the EGM case + NV_ASSERT_OR_RETURN(bEgmPeer, NV_ERR_INVALID_STATE); + *peer2 = *peer1; + } + else + { + // Get the peer ID pGpu1 should use for P2P over NVLINK to pGpu0 + *peer2 = kbusGetUnusedPeerId_HAL(pRemoteGpu, pRemoteKernelBus); + // If could not find a free peer ID, return error + if (*peer2 == BUS_INVALID_PEER) + { + NV_PRINTF(LEVEL_ERROR, + "GPU%d: peerID not available for NVLink P2P\n", + gpu1Instance); + return NV_ERR_GENERIC; + } + + // Reserve the peer ID for NVLink use + NV_CHECK_OK_OR_RETURN(LEVEL_ERROR, + kbusReserveP2PPeerIds_HAL(pRemoteGpu, pRemoteKernelBus, NVBIT(*peer2))); + } + } + else + { + NV_PRINTF(LEVEL_ERROR, + "Unexpected state, either of the peer ID is invalid \n"); + return NV_ERR_GENERIC; + } + +update_mask: + if (bEgmPeer) + { + NV_PRINTF(LEVEL_INFO, "EGM peer\n"); + } + // + // Does the mapping already exist between the given pair of GPUs using the peerIDs + // peer1 and peer2 respectively ? + // + if ((pLocalKernelBus->p2p.busNvlinkPeerNumberMask[gpu1Instance] & NVBIT(*peer1)) && + (pRemoteKernelBus->p2p.busNvlinkPeerNumberMask[gpu0Instance] & NVBIT(*peer2))) + { + // + // Increment the mapping refcount per peerID - since there is another usage + // of a mapping that is using this peerID + // + pLocalKernelBus->p2p.busNvlinkMappingRefcountPerPeerId[*peer1]++; + pRemoteKernelBus->p2p.busNvlinkMappingRefcountPerPeerId[*peer2]++; + + // + // Increment the mapping refcount per GPU - since there is another usage of + // the mapping to the given remote GPU + // + pLocalKernelBus->p2p.busNvlinkMappingRefcountPerGpu[gpu1Instance]++; + pRemoteKernelBus->p2p.busNvlinkMappingRefcountPerGpu[gpu0Instance]++; + + if (bSpaAccessOnly) + { + pLocalKernelBus->p2p.busNvlinkMappingRefcountPerPeerIdSpa[*peer1]++; + pRemoteKernelBus->p2p.busNvlinkMappingRefcountPerPeerId[*peer2]++; + } + + NV_PRINTF(LEVEL_INFO, + "- P2P: Peer mapping is already in use for gpu instances %x and %x " + "with peer id's %d and %d. Increasing the mapping refcounts for the" + " peer IDs to %d and %d respectively.\n", + gpu0Instance, gpu1Instance, *peer1, *peer2, + pLocalKernelBus->p2p.busNvlinkMappingRefcountPerPeerId[*peer1], + pRemoteKernelBus->p2p.busNvlinkMappingRefcountPerPeerId[*peer2]); + goto update_params; + } + + // + // Reached here implies the mapping between the given pair of GPUs using the peerIDs + // peer1 and peer2 does not exist. Create the mapping + // + + // Set the peer IDs in the corresponding peer number masks + pLocalKernelBus->p2p.busNvlinkPeerNumberMask[gpu1Instance] |= NVBIT(*peer1); + pRemoteKernelBus->p2p.busNvlinkPeerNumberMask[gpu0Instance] |= NVBIT(*peer2); + + pLocalKernelBus->p2p.bEgmPeer[*peer1] = bEgmPeer; + pRemoteKernelBus->p2p.bEgmPeer[*peer2] = bEgmPeer; + + // + // Increment the mapping refcount per peerID - since there is a new mapping that + // will use this peerID + // + pLocalKernelBus->p2p.busNvlinkMappingRefcountPerPeerId[*peer1]++; + pRemoteKernelBus->p2p.busNvlinkMappingRefcountPerPeerId[*peer2]++; + + if (bSpaAccessOnly) + { + pLocalKernelBus->p2p.busNvlinkMappingRefcountPerPeerIdSpa[*peer1]++; + pRemoteKernelBus->p2p.busNvlinkMappingRefcountPerPeerId[*peer2]++; + } + + // + // Increment the mapping refcount per GPU - since there a new mapping now to the + // given remote GPU + // + pLocalKernelBus->p2p.busNvlinkMappingRefcountPerGpu[gpu1Instance]++; + pRemoteKernelBus->p2p.busNvlinkMappingRefcountPerGpu[gpu0Instance]++; + + NV_PRINTF(LEVEL_INFO, + "added NVLink P2P mapping between GPU%u (peer %u) and GPU%u (peer %u)\n", + gpu0Instance, *peer1, gpu1Instance, *peer2); + +update_params: + if (bEgmPeer) + { + pNv503bAllocParams->subDeviceEgmPeerIdMask = NVBIT(*peer1); + pNv503bAllocParams->peerSubDeviceEgmPeerIdMask = NVBIT(*peer2); + } + else + { + pNv503bAllocParams->subDevicePeerIdMask = NVBIT(*peer1); + pNv503bAllocParams->peerSubDevicePeerIdMask = NVBIT(*peer2); + } + + // Update connection type for SRIOV. + pP2PApi->attributes = FLD_SET_DRF(_P2PAPI, _ATTRIBUTES, _CONNECTION_TYPE, _NVLINK, pP2PApi->attributes); + + return NV_OK; +} + + NV_STATUS p2papiConstruct_IMPL ( @@ -44,12 +247,12 @@ RS_RES_ALLOC_PARAMS_INTERNAL *pParams ) { - NvHandle hClient; Subdevice *pSubDevice; Subdevice *pPeerSubDevice; NvU32 subDevicePeerIdMask; NvU32 peerSubDevicePeerIdMask; RsClient *pClient; + RmClient *pRmClient; NvU32 peer1; NvU32 peer2; NvHandle hDevice; @@ -74,14 +277,23 @@ NV0000_CTRL_SYSTEM_GET_P2P_CAPS_V2_PARAMS *pP2pCapsParams; NvU32 p2pCaps; - hClient = pParams->hClient; subDevicePeerIdMask = pNv503bAllocParams->subDevicePeerIdMask; peerSubDevicePeerIdMask = pNv503bAllocParams->peerSubDevicePeerIdMask; + NvU32 egmPeer1; + NvU32 egmPeer2; + NvU32 subDeviceEgmPeerIdMask; + NvU32 peerSubDeviceEgmPeerIdMask; + NvBool bEgmPeer; - status = serverGetClientUnderLock(&g_resServ, hClient, &pClient); - if (status != NV_OK) + subDeviceEgmPeerIdMask = pNv503bAllocParams->subDeviceEgmPeerIdMask; + peerSubDeviceEgmPeerIdMask = pNv503bAllocParams->peerSubDeviceEgmPeerIdMask; + + pRmClient = dynamicCast(pCallContext->pClient, RmClient); + if (pRmClient == NULL) return NV_ERR_INVALID_ARGUMENT; + pClient = staticCast(pRmClient, RsClient); + status = subdeviceGetByHandle(pClient, pNv503bAllocParams->hSubDevice, &pSubDevice); if (status != NV_OK) return NV_ERR_INVALID_ARGUMENT; @@ -106,6 +318,22 @@ } } + if (pNv503bAllocParams->subDeviceEgmPeerIdMask) + { + if (!ONEBITSET(pNv503bAllocParams->subDeviceEgmPeerIdMask)) + { + return NV_ERR_INVALID_ARGUMENT; + } + } + + if (pNv503bAllocParams->peerSubDeviceEgmPeerIdMask) + { + if (!ONEBITSET(pNv503bAllocParams->peerSubDeviceEgmPeerIdMask)) + { + return NV_ERR_INVALID_ARGUMENT; + } + } + // Ensure any loopback requests match if (pNv503bAllocParams->hSubDevice == pNv503bAllocParams->hPeerSubDevice) { @@ -113,31 +341,22 @@ { return NV_ERR_INVALID_ARGUMENT; } + if (pNv503bAllocParams->subDeviceEgmPeerIdMask != pNv503bAllocParams->peerSubDeviceEgmPeerIdMask) + { + return NV_ERR_INVALID_ARGUMENT; + } } - // validate client - if (dynamicCast(pClient, RmClient) == NULL) - return NV_ERR_INVALID_CLIENT; - hSubDevice = RES_GET_HANDLE(pSubDevice); hPeerSubDevice = RES_GET_HANDLE(pPeerSubDevice); // Find the gpu for the subdevices passed to us - if (CliSetSubDeviceContext(hClient, hSubDevice, &hDevice, &pLocalGpu) != NV_OK || - NULL == pLocalGpu) - { - NV_PRINTF(LEVEL_ERROR, "Failed to find GPU for hSubDevice (0x%08x)\n", - hSubDevice); - return NV_ERR_INVALID_ARGUMENT; - } + pLocalGpu = GPU_RES_GET_GPU(pSubDevice); + pRemoteGpu = GPU_RES_GET_GPU(pPeerSubDevice); - if (CliSetSubDeviceContext(hClient, hPeerSubDevice, &hPeerDevice, &pRemoteGpu) != NV_OK || - NULL == pRemoteGpu) - { - NV_PRINTF(LEVEL_ERROR, "Failed to find GPU for hSubDevice (0x%08x)\n", - hPeerSubDevice); - return NV_ERR_INVALID_ARGUMENT; - } + // Get device handles + hDevice = RES_GET_HANDLE(pSubDevice->pDevice); + hPeerDevice = RES_GET_HANDLE(pPeerSubDevice->pDevice); API_GPU_FULL_POWER_SANITY_CHECK(pLocalGpu, NV_TRUE, NV_FALSE); API_GPU_FULL_POWER_SANITY_CHECK(pRemoteGpu, NV_TRUE, NV_FALSE); @@ -169,7 +388,7 @@ pP2pCapsParams->gpuIds[1] = pRemoteGpu->gpuId; NV_CHECK_OK_OR_ELSE(status, LEVEL_ERROR, - pRmApi->Control(pRmApi, hClient, hClient, + pRmApi->Control(pRmApi, pClient->hClient, pClient->hClient, NV0000_CTRL_CMD_SYSTEM_GET_P2P_CAPS_V2, pP2pCapsParams, sizeof(*pP2pCapsParams)), portMemFreeStackOrHeap(pP2pCapsParams); @@ -202,7 +421,7 @@ // // Allocate P2P PCIE Mailbox areas if all of the following conditions occur: // - P2P reads or/and writes are supported - // - The P2P connection is PCIE Mailbox based + // - The P2P connection is PCIE Mailbox based // if ((bP2PWriteCapable || bP2PReadCapable) && @@ -212,7 +431,7 @@ pNv503bAllocParams->mailboxBar1Addr, pNv503bAllocParams->mailboxTotalSize); NV_ASSERT_OK_OR_RETURN(status); - + status = kbusSetP2PMailboxBar1Area_HAL(pRemoteGpu, pRemoteKernelBus, pNv503bAllocParams->mailboxBar1Addr, pNv503bAllocParams->mailboxTotalSize); @@ -239,6 +458,26 @@ peer2 = BUS_INVALID_PEER; } + // Process any specific peer id requests for EGM peer 1 + if (subDeviceEgmPeerIdMask) + { + egmPeer1 = BIT_IDX_32(subDeviceEgmPeerIdMask); + } + else + { + egmPeer1 = BUS_INVALID_PEER; + } + + // Process any specific peer id requests for EGM peer 2 + if (peerSubDeviceEgmPeerIdMask) + { + egmPeer2 = BIT_IDX_32(peerSubDeviceEgmPeerIdMask); + } + else + { + egmPeer2 = BUS_INVALID_PEER; + } + if (!IS_VIRTUAL(pLocalGpu)) { if (!(bP2PWriteCapable || bP2PReadCapable)) @@ -306,164 +545,85 @@ pP2PApi->attributes = DRF_NUM(_P2PAPI, _ATTRIBUTES, _CONNECTION_TYPE, p2pConnectionType); pP2PApi->attributes |= bSpaAccessOnly ? DRF_DEF(_P2PAPI, _ATTRIBUTES, _LINK_TYPE, _SPA) : DRF_DEF(_P2PAPI, _ATTRIBUTES, _LINK_TYPE, _GPA); + bEgmPeer = (!bSpaAccessOnly && + memmgrIsLocalEgmEnabled(GPU_GET_MEMORY_MANAGER(pLocalGpu)) && + memmgrIsLocalEgmEnabled(GPU_GET_MEMORY_MANAGER(pRemoteGpu))); + if (bSpaAccessOnly && + memmgrIsLocalEgmEnabled(GPU_GET_MEMORY_MANAGER(pLocalGpu)) && + memmgrIsLocalEgmEnabled(GPU_GET_MEMORY_MANAGER(pRemoteGpu))) + { + NV_PRINTF(LEVEL_INFO, "EGM P2P not setup because of SPA only P2P flag!\n"); + } + + // Set the default Bar1 P2P DMA Info + pNv503bAllocParams->l2pBar1P2PDmaInfo.dma_address = \ + pNv503bAllocParams->p2lBar1P2PDmaInfo.dma_address = NV_U64_MAX; + pNv503bAllocParams->l2pBar1P2PDmaInfo.dma_size = \ + pNv503bAllocParams->p2lBar1P2PDmaInfo.dma_size = 0; if (IS_VGPU_GSP_PLUGIN_OFFLOAD_ENABLED(pLocalGpu) || !IS_VIRTUAL(pLocalGpu)) { + // + // TODO: This function need to have a cleanup path when this function + // fails after kbusCreateP2PMaping(), busBindLocalGfidForP2P() + // and busBindRemoteGfidForP2P(). The current state, the + // function just returns an error. Bug 4016670 filed to track + // the effort. + // + // setup the p2p resources NV_CHECK_OK_OR_RETURN(LEVEL_ERROR, kbusCreateP2PMapping_HAL(pLocalGpu, pLocalKernelBus, pRemoteGpu, pRemoteKernelBus, &peer1, &peer2, pP2PApi->attributes)); - } - - pGpu = pLocalGpu; - - if (!IS_VGPU_GSP_PLUGIN_OFFLOAD_ENABLED(pGpu) && - IS_VIRTUAL_WITH_SRIOV(pGpu) && - gpuIsSplitVasManagementServerClientRmEnabled(pGpu)) - { - NvU32 gpu0Instance = gpuGetInstance(pLocalGpu); - NvU32 gpu1Instance = gpuGetInstance(pRemoteGpu); - - // loopback request - if (pNv503bAllocParams->hSubDevice == pNv503bAllocParams->hPeerSubDevice) + if (bEgmPeer) { - peer1 = peer2 = 0; - } - else - { - // Check if a peer ID is already allocated for P2P from pLocalGpu to pRemoteGpu - peer1 = kbusGetPeerId_HAL(pLocalGpu, pLocalKernelBus, pRemoteGpu); - - // Check if a peer ID is already allocated for P2P from pRemoteGpu to pLocalGpu - peer2 = kbusGetPeerId_HAL(pRemoteGpu, pRemoteKernelBus, pLocalGpu); + NV_CHECK_OK_OR_RETURN(LEVEL_ERROR, + kbusCreateP2PMapping_HAL(pLocalGpu, pLocalKernelBus, pRemoteGpu, + pRemoteKernelBus, &egmPeer1, &egmPeer2, + pP2PApi->attributes | + DRF_DEF(_P2PAPI, _ATTRIBUTES, _REMOTE_EGM, _YES))); } - if (peer1 != BUS_INVALID_PEER && peer2 != BUS_INVALID_PEER) - { - goto update_mask; - } - else if (peer1 == BUS_INVALID_PEER && peer2 == BUS_INVALID_PEER) + if (p2pConnectionType == P2P_CONNECTIVITY_PCIE_BAR1) { - // Get the peer ID pGpu0 should use for P2P over NVLINK to pGpu1i - peer1 = kbusGetUnusedPeerId_HAL(pLocalGpu, pLocalKernelBus); - // If could not find a free peer ID, return error - if (peer1 == BUS_INVALID_PEER) - { - NV_PRINTF(LEVEL_ERROR, - "GPU%d: peerID not available for NVLink P2P\n", - gpu0Instance); - return NV_ERR_GENERIC; - } - - // Reserve the peer ID for NVLink use NV_CHECK_OK_OR_RETURN(LEVEL_ERROR, - kbusReserveP2PPeerIds_HAL(pLocalGpu, pLocalKernelBus, NVBIT(peer1))); - - // Get the peer ID pGpu1 should use for P2P over NVLINK to pGpu0 - peer2 = kbusGetUnusedPeerId_HAL(pRemoteGpu, pRemoteKernelBus); - // If could not find a free peer ID, return error - if (peer2 == BUS_INVALID_PEER) - { - NV_PRINTF(LEVEL_ERROR, - "GPU%d: peerID not available for NVLink P2P\n", - gpu1Instance); - return NV_ERR_GENERIC; - } + kbusGetBar1P2PDmaInfo_HAL(pLocalGpu, pRemoteGpu, + pRemoteKernelBus, + &pNv503bAllocParams->l2pBar1P2PDmaInfo.dma_address, + &pNv503bAllocParams->l2pBar1P2PDmaInfo.dma_size)); - // Reserve the peer ID for NVLink use NV_CHECK_OK_OR_RETURN(LEVEL_ERROR, - kbusReserveP2PPeerIds_HAL(pRemoteGpu, pRemoteKernelBus, NVBIT(peer2))); - } - else - { - NV_PRINTF(LEVEL_ERROR, - "Unexpected state, either of the peer ID is invalid \n"); - return NV_ERR_GENERIC; - } - -update_mask: - // - // Does the mapping already exist between the given pair of GPUs using the peerIDs - // peer1 and peer2 respectively ? - // - if ((pLocalKernelBus->p2p.busNvlinkPeerNumberMask[gpu1Instance] & NVBIT(peer1)) && - (pRemoteKernelBus->p2p.busNvlinkPeerNumberMask[gpu0Instance] & NVBIT(peer2))) - { - // - // Increment the mapping refcount per peerID - since there is another usage - // of a mapping that is using this peerID - // - pLocalKernelBus->p2p.busNvlinkMappingRefcountPerPeerId[peer1]++; - pRemoteKernelBus->p2p.busNvlinkMappingRefcountPerPeerId[peer2]++; - - // - // Increment the mapping refcount per GPU - since there is another usage of - // the mapping to the given remote GPU - // - pLocalKernelBus->p2p.busNvlinkMappingRefcountPerGpu[gpu1Instance]++; - pRemoteKernelBus->p2p.busNvlinkMappingRefcountPerGpu[gpu0Instance]++; - - if (bSpaAccessOnly) - { - pLocalKernelBus->p2p.busNvlinkMappingRefcountPerPeerIdSpa[peer1]++; - pRemoteKernelBus->p2p.busNvlinkMappingRefcountPerPeerId[peer2]++; - } - - NV_PRINTF(LEVEL_INFO, - "- P2P: Peer mapping is already in use for gpu instances %x and %x " - "with peer id's %d and %d. Increasing the mapping refcounts for the" - " peer IDs to %d and %d respectively.\n", - gpu0Instance, gpu1Instance, peer1, peer2, - pLocalKernelBus->p2p.busNvlinkMappingRefcountPerPeerId[peer1], - pRemoteKernelBus->p2p.busNvlinkMappingRefcountPerPeerId[peer2]); - - goto update_params; + kbusGetBar1P2PDmaInfo_HAL(pRemoteGpu, pLocalGpu, + pLocalKernelBus, + &pNv503bAllocParams->p2lBar1P2PDmaInfo.dma_address, + &pNv503bAllocParams->p2lBar1P2PDmaInfo.dma_size)); } + } - // - // Reached here implies the mapping between the given pair of GPUs using the peerIDs - // peer1 and peer2 does not exist. Create the mapping - // - - // Set the peer IDs in the corresponding peer number masks - pLocalKernelBus->p2p.busNvlinkPeerNumberMask[gpu1Instance] |= NVBIT(peer1); - pRemoteKernelBus->p2p.busNvlinkPeerNumberMask[gpu0Instance] |= NVBIT(peer2); + pGpu = pLocalGpu; - // - // Increment the mapping refcount per peerID - since there is a new mapping that - // will use this peerID - // - pLocalKernelBus->p2p.busNvlinkMappingRefcountPerPeerId[peer1]++; - pRemoteKernelBus->p2p.busNvlinkMappingRefcountPerPeerId[peer2]++; - - if (bSpaAccessOnly) + if (!IS_VGPU_GSP_PLUGIN_OFFLOAD_ENABLED(pGpu) && + IS_VIRTUAL_WITH_SRIOV(pGpu) && + gpuIsSplitVasManagementServerClientRmEnabled(pGpu)) + { + NV_CHECK_OK_OR_RETURN(LEVEL_ERROR, + _p2papiReservePeerID(pLocalGpu, pLocalKernelBus, pRemoteGpu, + pRemoteKernelBus, pNv503bAllocParams, pP2PApi, + &peer1, &peer2, NV_FALSE, bSpaAccessOnly)); + if (bEgmPeer) { - pLocalKernelBus->p2p.busNvlinkMappingRefcountPerPeerIdSpa[peer1]++; - pRemoteKernelBus->p2p.busNvlinkMappingRefcountPerPeerId[peer2]++; + NV_CHECK_OK_OR_RETURN(LEVEL_ERROR, + _p2papiReservePeerID(pLocalGpu, pLocalKernelBus, pRemoteGpu, + pRemoteKernelBus, pNv503bAllocParams, pP2PApi, + &egmPeer1, &egmPeer2, NV_TRUE, bSpaAccessOnly)); } - - // - // Increment the mapping refcount per GPU - since there a new mapping now to the - // given remote GPU - // - pLocalKernelBus->p2p.busNvlinkMappingRefcountPerGpu[gpu1Instance]++; - pRemoteKernelBus->p2p.busNvlinkMappingRefcountPerGpu[gpu0Instance]++; - - NV_PRINTF(LEVEL_INFO, - "added NVLink P2P mapping between GPU%u (peer %u) and GPU%u (peer %u)\n", - gpu0Instance, peer1, gpu1Instance, peer2); - -update_params: - pNv503bAllocParams->subDevicePeerIdMask = NVBIT(peer1); - pNv503bAllocParams->peerSubDevicePeerIdMask = NVBIT(peer2); - - // Update connection type for SRIOV. - pP2PApi->attributes = FLD_SET_DRF(_P2PAPI, _ATTRIBUTES, _CONNECTION_TYPE, _NVLINK, pP2PApi->attributes); } pP2PApi->peerId1 = peer1; pP2PApi->peerId2 = peer2; + pP2PApi->egmPeerId1 = egmPeer1; + pP2PApi->egmPeerId2 = egmPeer2; pP2PApi->localGfid = GPU_GFID_PF; pP2PApi->remoteGfid = GPU_GFID_PF; @@ -475,6 +635,7 @@ pParams->hResource, pParams->externalClassId, pNv503bAllocParams, + sizeof(*pNv503bAllocParams), status); if (status != NV_OK) return status; @@ -515,7 +676,7 @@ { NV_ASSERT_OK_OR_RETURN(refAddDependant(RES_GET_REF(pPeerSubDevice), pCallContext->pResourceRef)); } - + if (status == NV_OK) { NV_CHECK_OR_RETURN(LEVEL_ERROR, pLocalKernelBus->totalP2pObjectsAliveRefCount < NV_U32_MAX, NV_ERR_INSUFFICIENT_RESOURCES); @@ -568,10 +729,21 @@ if (IS_VGPU_GSP_PLUGIN_OFFLOAD_ENABLED(pLocalGpu) || !IS_VIRTUAL(pLocalGpu)) { // remove any resources associated with this mapping - status = kbusRemoveP2PMapping_HAL(pLocalGpu, pLocalKernelBus, - pRemoteGpu, pRemoteKernelBus, - pP2PApi->peerId1, pP2PApi->peerId2, - pP2PApi->attributes); + NV_CHECK_OK_OR_GOTO(status, LEVEL_ERROR, + kbusRemoveP2PMapping_HAL(pLocalGpu, pLocalKernelBus, + pRemoteGpu, pRemoteKernelBus, + pP2PApi->peerId1, pP2PApi->peerId2, + pP2PApi->attributes), end); + if (!FLD_TEST_DRF(_P2PAPI, _ATTRIBUTES, _LINK_TYPE, _SPA, pP2PApi->attributes) && + memmgrIsLocalEgmEnabled(GPU_GET_MEMORY_MANAGER(pLocalGpu)) && + memmgrIsLocalEgmEnabled(GPU_GET_MEMORY_MANAGER(pRemoteGpu))) + { + status = kbusRemoveP2PMapping_HAL(pLocalGpu, pLocalKernelBus, + pRemoteGpu, pRemoteKernelBus, + pP2PApi->egmPeerId1, pP2PApi->egmPeerId2, + pP2PApi->attributes | + DRF_DEF(_P2PAPI, _ATTRIBUTES, _REMOTE_EGM, _YES)); + } } pP2PApi->peer1 = NULL; diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/kernel/gpu/bus/third_party_p2p.c nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/kernel/gpu/bus/third_party_p2p.c --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/kernel/gpu/bus/third_party_p2p.c 2023-10-25 20:20:54.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/kernel/gpu/bus/third_party_p2p.c 2024-03-05 22:13:17.000000000 +0000 @@ -223,29 +223,6 @@ pParams->status = status; } -NV_STATUS CliGetThirdPartyP2PInfo -( - NvHandle hClient, - NvHandle hThirdPartyP2P, - ThirdPartyP2P **ppThirdPartyP2P -) -{ - RsResourceRef *pThirdPartyP2PRef; - RsClient *pRsClient; - NV_ASSERT_OR_RETURN((ppThirdPartyP2P != NULL), NV_ERR_INVALID_ARGUMENT); - - NV_ASSERT_OK_OR_RETURN(serverGetClientUnderLock(&g_resServ, hClient, &pRsClient)); - NV_ASSERT_OK_OR_RETURN(clientGetResourceRef(pRsClient, hThirdPartyP2P, &pThirdPartyP2PRef)); - *ppThirdPartyP2P = dynamicCast(pThirdPartyP2PRef->pResource, ThirdPartyP2P); - - if (*ppThirdPartyP2P == NULL) - { - return NV_ERR_INVALID_OBJECT_HANDLE; - } - - return NV_OK; -} - NV_STATUS CliGetThirdPartyP2PInfoFromToken ( NvU64 p2pToken, @@ -359,28 +336,18 @@ NV_STATUS CliAddThirdPartyP2PVASpace ( - NvHandle hClient, - NvHandle hThirdPartyP2P, - NvHandle hVASpace, - NvU32 *pVASpaceToken + ThirdPartyP2P *pThirdPartyP2P, + NvHandle hVASpace, + NvU32 *pVASpaceToken ) { - RsClient *pRsClient; - ThirdPartyP2P *pThirdPartyP2P; + NvHandle hThirdPartyP2P = RES_GET_HANDLE(pThirdPartyP2P); + RsClient *pClient = RES_GET_CLIENT(pThirdPartyP2P); CLI_THIRD_PARTY_P2P_VASPACE_INFO vaSpaceInfo; NvU32 vaSpaceToken; - NV_STATUS status; - NV_ASSERT_OK_OR_RETURN(serverGetClientUnderLock(&g_resServ, hClient, &pRsClient)); NV_ASSERT_OR_RETURN((pVASpaceToken != NULL), NV_ERR_INVALID_ARGUMENT); - status = CliGetThirdPartyP2PInfo(hClient, hThirdPartyP2P, - &pThirdPartyP2P); - if (status != NV_OK || pThirdPartyP2P == NULL) - { - return NV_ERR_INVALID_OBJECT; - } - portMemSet(&vaSpaceInfo, 0, sizeof(CLI_THIRD_PARTY_P2P_VASPACE_INFO)); for (vaSpaceToken = 0xfe00; vaSpaceToken < 0xff00; vaSpaceToken++) @@ -393,7 +360,7 @@ return NV_ERR_INSUFFICIENT_RESOURCES; } - vaSpaceInfo.hClient = hClient; + vaSpaceInfo.hClient = pClient->hClient; vaSpaceInfo.hThirdPartyP2P = hThirdPartyP2P; vaSpaceInfo.hVASpace = hVASpace; vaSpaceInfo.vaSpaceToken = vaSpaceToken; @@ -414,8 +381,8 @@ { RsResourceRef *pP2PRef; RsResourceRef *pVASpaceRef; - if ((clientGetResourceRef(pRsClient, hThirdPartyP2P, &pP2PRef) == NV_OK) && - (clientGetResourceRef(pRsClient, hVASpace, &pVASpaceRef) == NV_OK)) + if ((clientGetResourceRef(pClient, hThirdPartyP2P, &pP2PRef) == NV_OK) && + (clientGetResourceRef(pClient, hVASpace, &pVASpaceRef) == NV_OK)) { refAddDependant(pVASpaceRef, pP2PRef); } @@ -499,27 +466,19 @@ NV_STATUS CliAddThirdPartyP2PVidmemInfo ( - NvHandle hClient, - NvHandle hThirdPartyP2P, - NvHandle hMemory, - NvU64 address, - NvU64 size, - NvU64 offset, - Memory *pMemory + ThirdPartyP2P *pThirdPartyP2P, + NvHandle hMemory, + NvU64 address, + NvU64 size, + NvU64 offset, + Memory *pMemory ) { NV_STATUS status; - ThirdPartyP2P *pThirdPartyP2P; PCLI_THIRD_PARTY_P2P_VIDMEM_INFO pVidmemInfo; NV_ASSERT_OR_RETURN((pMemory != NULL), NV_ERR_INVALID_ARGUMENT); - status = CliGetThirdPartyP2PInfo(hClient, hThirdPartyP2P, &pThirdPartyP2P); - if (status != NV_OK) - { - return status; - } - pVidmemInfo = portMemAllocNonPaged(sizeof(CLI_THIRD_PARTY_P2P_VIDMEM_INFO)); if (pVidmemInfo == NULL) { @@ -559,8 +518,8 @@ return status; } - pVidmemInfo->hClient = hClient; - pVidmemInfo->hThirdPartyP2P = hThirdPartyP2P; + pVidmemInfo->hClient = RES_GET_CLIENT_HANDLE(pThirdPartyP2P); + pVidmemInfo->hThirdPartyP2P = RES_GET_HANDLE(pThirdPartyP2P); pVidmemInfo->hMemory = hMemory; pVidmemInfo->pMemDesc = pMemory->pMemDesc; pVidmemInfo->id = portAtomicExIncrementU64(&vidmemInfoId); @@ -644,8 +603,7 @@ NV_STATUS CliGetThirdPartyP2PVidmemInfoFromAddress ( - NvHandle hClient, - NvHandle hThirdPartyP2P, + ThirdPartyP2P *pThirdPartyP2P, NvU64 address, NvU64 length, NvU64 *pOffset, @@ -654,19 +612,11 @@ { NV_STATUS status; PNODE pNode; - ThirdPartyP2P *pThirdPartyP2P; PCLI_THIRD_PARTY_P2P_VIDMEM_INFO pVidmemInfo; NV_ASSERT_OR_RETURN((pOffset != NULL), NV_ERR_INVALID_ARGUMENT); NV_ASSERT_OR_RETURN((ppVidmemInfo != NULL), NV_ERR_INVALID_ARGUMENT); - status = CliGetThirdPartyP2PInfo(hClient, hThirdPartyP2P, - &pThirdPartyP2P); - if (status != NV_OK) - { - return status; - } - status = btreeSearch(address, &pNode, pThirdPartyP2P->pAddressRangeTree); if (status != NV_OK) @@ -693,25 +643,16 @@ NV_STATUS CliGetThirdPartyP2PVidmemInfoFromId ( - NvHandle hClient, - NvHandle hThirdPartyP2P, + ThirdPartyP2P *pThirdPartyP2P, NvU64 id, CLI_THIRD_PARTY_P2P_VIDMEM_INFO **ppVidmemInfo ) { NV_STATUS status; PNODE pNode; - ThirdPartyP2P *pThirdPartyP2P; NV_ASSERT_OR_RETURN((ppVidmemInfo != NULL), NV_ERR_INVALID_ARGUMENT); - status = CliGetThirdPartyP2PInfo(hClient, hThirdPartyP2P, - &pThirdPartyP2P); - if (status != NV_OK) - { - return status; - } - status = btreeSearch(id, &pNode, pThirdPartyP2P->pAddressRangeTree); if (status != NV_OK) { @@ -725,8 +666,7 @@ NV_STATUS CliRegisterThirdPartyP2PMappingCallback ( - NvHandle hClient, - NvHandle hThirdPartyP2P, + ThirdPartyP2P *pThirdPartyP2P, NvHandle hMemory, void *pKey, THIRD_PARTY_P2P_VIDMEM_FREE_CALLBACK *pFreeCallback, @@ -738,8 +678,8 @@ NV_ASSERT_OR_RETURN((pFreeCallback != NULL), NV_ERR_INVALID_ARGUMENT); - status = CliGetThirdPartyP2PMappingInfoFromKey(hClient, hThirdPartyP2P, - hMemory, pKey, &pMappingInfo); + status = CliGetThirdPartyP2PMappingInfoFromKey(pThirdPartyP2P, hMemory, pKey, + &pMappingInfo); if (status != NV_OK) { return status; @@ -755,8 +695,7 @@ NV_STATUS CliAddThirdPartyP2PMappingInfo ( - NvHandle hClient, - NvHandle hThirdPartyP2P, + ThirdPartyP2P *pThirdPartyP2P, NvHandle hMemory, void *pKey, THIRD_PARTY_P2P_VIDMEM_FREE_CALLBACK *pFreeCallback, @@ -765,20 +704,12 @@ ) { NV_STATUS status; - ThirdPartyP2P *pThirdPartyP2P; PCLI_THIRD_PARTY_P2P_VIDMEM_INFO pVidmemInfo; PCLI_THIRD_PARTY_P2P_MAPPING_INFO pMappingInfo; NV_ASSERT_OR_RETURN((pKey != NULL), NV_ERR_INVALID_ARGUMENT); NV_ASSERT_OR_RETURN((ppMappingInfo != NULL), NV_ERR_INVALID_ARGUMENT); - status = CliGetThirdPartyP2PInfo(hClient, hThirdPartyP2P, - &pThirdPartyP2P); - if (status != NV_OK) - { - return status; - } - pVidmemInfo = mapFind(&pThirdPartyP2P->vidmemInfoMap, hMemory); if (pVidmemInfo == NULL) { @@ -814,28 +745,19 @@ NV_STATUS CliGetThirdPartyP2PMappingInfoFromKey ( - NvHandle hClient, - NvHandle hThirdPartyP2P, + ThirdPartyP2P *pThirdPartyP2P, NvHandle hMemory, void *pKey, PCLI_THIRD_PARTY_P2P_MAPPING_INFO *ppMappingInfo ) { NV_STATUS status; - ThirdPartyP2P *pThirdPartyP2P; PNODE pNode; PCLI_THIRD_PARTY_P2P_VIDMEM_INFO pVidmemInfo; NV_ASSERT_OR_RETURN((pKey != NULL), NV_ERR_INVALID_ARGUMENT); NV_ASSERT_OR_RETURN((ppMappingInfo != NULL), NV_ERR_INVALID_ARGUMENT); - status = CliGetThirdPartyP2PInfo(hClient, hThirdPartyP2P, - &pThirdPartyP2P); - if (status != NV_OK) - { - return status; - } - pVidmemInfo = mapFind(&pThirdPartyP2P->vidmemInfoMap, hMemory); if (pVidmemInfo == NULL) { @@ -1156,7 +1078,7 @@ return status; } -NV_STATUS +NV_STATUS shrp2pConstruct_IMPL(P2PTokenShare *pP2PTokenShare) { return NV_OK; diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/kernel/gpu/bus/third_party_p2p_ctrl.c nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/kernel/gpu/bus/third_party_p2p_ctrl.c --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/kernel/gpu/bus/third_party_p2p_ctrl.c 2023-10-25 20:20:54.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/kernel/gpu/bus/third_party_p2p_ctrl.c 2024-03-05 22:13:17.000000000 +0000 @@ -37,8 +37,6 @@ NV503C_CTRL_REGISTER_VA_SPACE_PARAMS *pRegisterVaSpaceParams ) { - NvHandle hClient = RES_GET_CLIENT_HANDLE(pThirdPartyP2P); - NvHandle hObject = RES_GET_HANDLE(pThirdPartyP2P); NvU32 vaSpaceToken; NV_STATUS status; OBJGPU *pGpu; @@ -48,8 +46,7 @@ return NV_ERR_INVALID_OBJECT_PARENT; - status = CliAddThirdPartyP2PVASpace(hClient, - hObject, + status = CliAddThirdPartyP2PVASpace(pThirdPartyP2P, pRegisterVaSpaceParams->hVASpace, &vaSpaceToken); if (status == NV_OK) @@ -91,7 +88,6 @@ { Memory *pMemory; RsClient *pClient = RES_GET_CLIENT(pThirdPartyP2P); - NvHandle hObject = RES_GET_HANDLE(pThirdPartyP2P); NvHandle hDevice; NvU64 address = pRegisterVidmemParams->address; NvU64 size = pRegisterVidmemParams->size; @@ -138,8 +134,7 @@ if (memdescGetSize(pMemory->pMemDesc) < offset + size) return NV_ERR_INVALID_ARGUMENT; - status = CliAddThirdPartyP2PVidmemInfo(pClient->hClient, - hObject, + status = CliAddThirdPartyP2PVidmemInfo(pThirdPartyP2P, pRegisterVidmemParams->hMemory, address, size, @@ -185,7 +180,9 @@ NvU32 pid; NV_STATUS status; - NV_ASSERT_OK_OR_RETURN(serverutilGetClientUnderLock(pRegisterPidParams->hClient, &pClient)); + pClient = serverutilGetClientUnderLock(pRegisterPidParams->hClient); + NV_ASSERT_OR_RETURN(pClient != NULL, NV_ERR_INVALID_CLIENT); + pid = pClient->ProcID; status = CliAddThirdPartyP2PClientPid(hClient, diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/kernel/gpu/ccu/kernel_ccu.c nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/kernel/gpu/ccu/kernel_ccu.c --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/kernel/gpu/ccu/kernel_ccu.c 2023-10-25 20:20:54.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/kernel/gpu/ccu/kernel_ccu.c 2024-03-05 22:13:17.000000000 +0000 @@ -230,7 +230,7 @@ NvU32 i = 0; NV_STATUS status = NV_OK; NV2080_CTRL_INTERNAL_CCU_UNMAP_INFO_PARAMS params = { 0 }; - + NV_PRINTF(LEVEL_INFO, "KernelCcu: Unmap and free shared buffer\n"); // Internal RM api ctrl call to physical RM to unmap dev & mig shared buffer memdesc @@ -556,7 +556,7 @@ ( OBJGPU *pGpu, KernelCcu *pKernelCcu, - NvBool bDevCounter + NvBool bDevCounter ) { NV_PRINTF(LEVEL_INFO, "KernelCcu: Get counter block size \n"); @@ -583,7 +583,7 @@ ( OBJGPU *pGpu, KernelCcu *pKernelCcu, - NV_COUNTER_COLLECTION_UNIT_STREAM_STATE_PARAMS *pParams + NV_COUNTER_COLLECTION_UNIT_STREAM_STATE_PARAMS *pParams ) { NV_STATUS status = NV_OK; diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/kernel/gpu/ccu/kernel_ccu_api.c nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/kernel/gpu/ccu/kernel_ccu_api.c --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/kernel/gpu/ccu/kernel_ccu_api.c 2023-10-25 20:20:54.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/kernel/gpu/ccu/kernel_ccu_api.c 2024-03-05 22:13:17.000000000 +0000 @@ -82,7 +82,7 @@ { return kccuMemDescGetForShrBufId(pGpu, pKernelCcu, CCU_DEV_SHRBUF_ID, pMemDesc); } - + // In case of MIG status = kmigmgrGetInstanceRefFromClient(pGpu, pKernelMIGManager, hClient, &ref); if (status != NV_OK) @@ -175,7 +175,7 @@ MEMORY_DESCRIPTOR *pMemDesc = NULL; NV_PRINTF(LEVEL_INFO, "Kernel Ccu Api: memdesc unmap\n"); - + status = rmapiValidateKernelMapping(rmclientGetCachedPrivilege(pClient), pCpuMapping->flags, &bKernel); diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/kernel/gpu/ce/arch/ampere/kernel_ce_ga100.c nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/kernel/gpu/ce/arch/ampere/kernel_ce_ga100.c --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/kernel/gpu/ce/arch/ampere/kernel_ce_ga100.c 2023-10-25 20:20:54.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/kernel/gpu/ce/arch/ampere/kernel_ce_ga100.c 2024-03-05 22:13:17.000000000 +0000 @@ -596,7 +596,7 @@ NV_STATUS status = NV_OK; KernelNvlink *pKernelNvlink = GPU_GET_KERNEL_NVLINK(pGpu); - + NV2080_CTRL_NVLINK_HSHUB_GET_SYSMEM_NVLINK_MASK_PARAMS paramsNvlinkMask; NV2080_CTRL_INTERNAL_HSHUB_GET_HSHUB_ID_FOR_LINKS_PARAMS *pParamsHshubId = NULL; @@ -1021,7 +1021,7 @@ * * @param[in] pGpu OBJGPU pointer * @param[in] pKCe KernelCE pointer - * @param[in] checkGen genX for query + * @param[in] checkGen genX for query */ NvBool kceIsGenXorHigherSupported_GA100 diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/kernel/gpu/ce/arch/hopper/kernel_ce_gh100.c nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/kernel/gpu/ce/arch/hopper/kernel_ce_gh100.c --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/kernel/gpu/ce/arch/hopper/kernel_ce_gh100.c 2023-10-25 20:20:54.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/kernel/gpu/ce/arch/hopper/kernel_ce_gh100.c 2024-03-05 22:13:17.000000000 +0000 @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 2021-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2021-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -31,6 +31,8 @@ #include "published/hopper/gh100/dev_ce.h" #include "published/hopper/gh100/dev_xtl_ep_pcfg_gpu.h" +#define NV_CE_INVALID_TOPO_IDX 0xFFFF + // Defines for PCE-LCE mapping algorithm #define NV_CE_MAX_HSHUBS 5 #define NV_CE_LCE_MASK_INIT 0xFFFFFFFF @@ -43,8 +45,105 @@ #define NV_CE_NUM_FBPCE 4 #define NV_CE_NUM_PCES_NO_LINK_CASE 12 #define NV_CE_MAX_PCE_PER_GRCE 2 +#define NV_CE_HSHUBNVL_ID_0 2 - +/* + * Table for setting the PCE2LCE mapping for WAR configs that cannot be implemented + * using the algorithm because the config does not conform to the algorithm's set + * of requirements/assumptions + */ +static NVLINK_CE_AUTO_CONFIG_TABLE nvLinkCeAutoConfigTable_GH100[] = +{ + // + // #systmem #max #peers Symmetric Switch PCE-LCE GRCE exposeCe + // links (links/peer) Config? Config Map Config Mask + + // Default minimal configuration - NOTE: do not add entrys before this + // Default is for CG1 + {0x0, 0x0, 0x0, NV_FALSE, NV_FALSE, {0x4,0x6,0x4,0x6,0x4,0x6,0x4,0x6, + 0x4,0x4,0x4,0x6,0x4,0x6,0x4,0x6}, {0x4,0x6}, 0x53}, + {0x0, 0x0, 0x0, NV_TRUE, NV_FALSE, {0x4,0x6,0x4,0x6,0x4,0x6,0x4,0x6, + 0x4,0x4,0x4,0x6,0x4,0x6,0x4,0x6}, {0x4,0x6}, 0x53}, + + // Switch cases - Ranger mapping + {0x0, 0x12, 0x1, NV_TRUE, NV_TRUE, {0x4,0x6,0x4,0x6,0x4,0x6,0x4,0x6, + 0x4,0x4,0x4,0x6,0x4,0x6,0x4,0x6}, {0x4,0x6}, 0x53}, + {0x0, 0x6, 0x1, NV_TRUE, NV_TRUE, {0x4,0x6,0x4,0x6,0x4,0x6,0x4,0x6, + 0x4,0x4,0x4,0x6,0x4,0x6,0x4,0x6}, {0x4,0x6}, 0x53}, + // CG4 mapping + {0x0, 0x6, 0x3, NV_TRUE, NV_FALSE, {0x4,0x4,0x4,0x4,0x8,0x8,0x8,0x4, + 0x4,0x6,0x4,0x6,0x4,0x6,0x4,0x6}, {0x4,0x6}, 0x153}, + {0x0, 0x6, 0x3, NV_FALSE, NV_FALSE, {0x4,0x4,0x4,0x4,0x8,0x8,0x8,0x4, + 0x4,0x6,0x4,0x6,0x4,0x6,0x4,0x6}, {0x4,0x6}, 0x153}, + {0x0, 0x6, 0x2, NV_TRUE, NV_FALSE, {0x4,0x4,0x4,0x4,0xF,0xF,0xF,0x4, + 0x4,0x6,0x4,0x6,0x4,0x6,0x4,0x6}, {0x4,0x6}, 0x53}, + {0x0, 0x6, 0x2, NV_FALSE, NV_FALSE, {0x4,0x4,0x4,0x4,0xF,0xF,0xF,0x4, + 0x4,0x6,0x4,0x6,0x4,0x6,0x4,0x6}, {0x4,0x6}, 0x53}, + {0x0, 0x6, 0x1, NV_TRUE, NV_FALSE, {0x4,0x4,0x4,0x4,0xF,0xF,0xF,0x4, + 0x4,0xF,0x4,0xF,0x4,0xF,0x4,0xF}, {0x4,0xF}, 0x13}, + {0x0, 0x6, 0x1, NV_FALSE, NV_FALSE, {0x4,0x4,0x4,0x4,0xF,0xF,0xF,0x4, + 0x4,0xF,0x4,0xF,0x4,0xF,0x4,0xF}, {0x4,0xF}, 0x13}, + {0x0, 0x5, 0x3, NV_TRUE, NV_FALSE, {0x4,0x4,0x4,0x4,0x8,0x8,0x8,0x4, + 0x4,0x6,0x4,0x6,0x4,0x6,0x4,0x6}, {0x4,0x6}, 0x153}, + {0x0, 0x5, 0x3, NV_FALSE, NV_FALSE, {0x4,0x4,0x4,0x4,0x8,0x8,0x8,0x4, + 0x4,0x6,0x4,0x6,0x4,0x6,0x4,0x6}, {0x4,0x6}, 0x153}, + {0x0, 0x5, 0x2, NV_TRUE, NV_FALSE, {0x4,0x4,0x4,0x4,0xF,0xF,0xF,0x4, + 0x4,0x6,0x4,0x6,0x4,0x6,0x4,0x6}, {0x4,0x6}, 0x53}, + {0x0, 0x5, 0x2, NV_FALSE, NV_FALSE, {0x4,0x4,0x4,0x4,0xF,0xF,0xF,0x4, + 0x4,0x6,0x4,0x6,0x4,0x6,0x4,0x6}, {0x4,0x6}, 0x53}, + {0x0, 0x5, 0x1, NV_TRUE, NV_FALSE, {0x4,0x4,0x4,0x4,0xF,0xF,0xF,0x4, + 0x4,0xF,0x4,0xF,0x4,0xF,0x4,0xF}, {0x4,0xF}, 0x13}, + {0x0, 0x5, 0x1, NV_FALSE, NV_FALSE, {0x4,0x4,0x4,0x4,0xF,0xF,0xF,0x4, + 0x4,0xF,0x4,0xF,0x4,0xF,0x4,0xF}, {0x4,0xF}, 0x13}, + {0x0, 0x4, 0x3, NV_TRUE, NV_FALSE, {0x4,0x4,0x4,0x4,0x8,0x8,0x8,0x4, + 0x4,0x6,0x4,0x6,0x4,0x6,0x4,0x6}, {0x4,0x6}, 0x153}, + {0x0, 0x4, 0x3, NV_FALSE, NV_FALSE, {0x4,0x4,0x4,0x4,0x8,0x8,0x8,0x4, + 0x4,0x6,0x4,0x6,0x4,0x6,0x4,0x6}, {0x4,0x6}, 0x153}, + {0x0, 0x4, 0x2, NV_TRUE, NV_FALSE, {0x4,0x4,0x4,0x4,0xF,0xF,0xF,0x4, + 0x4,0x6,0x4,0x6,0x4,0x6,0x4,0x6}, {0x4,0x6}, 0x53}, + {0x0, 0x4, 0x2, NV_FALSE, NV_FALSE, {0x4,0x4,0x4,0x4,0xF,0xF,0xF,0x4, + 0x4,0x6,0x4,0x6,0x4,0x6,0x4,0x6}, {0x4,0x6}, 0x53}, + {0x0, 0x4, 0x1, NV_TRUE, NV_FALSE, {0x4,0x4,0x4,0x4,0xF,0xF,0xF,0x4, + 0x4,0xF,0x4,0xF,0x4,0xF,0x4,0xF}, {0x4,0xF}, 0x13}, + {0x0, 0x4, 0x1, NV_FALSE, NV_FALSE, {0x4,0x4,0x4,0x4,0xF,0xF,0xF,0x4, + 0x4,0xF,0x4,0xF,0x4,0xF,0x4,0xF}, {0x4,0xF}, 0x13}, + {0x0, 0x3, 0x3, NV_TRUE, NV_FALSE, {0x4,0x4,0x4,0x4,0x8,0x8,0x8,0x4, + 0x4,0x6,0x4,0x6,0x4,0x6,0x4,0x6}, {0x4,0x6}, 0x153}, + {0x0, 0x3, 0x3, NV_FALSE, NV_FALSE, {0x4,0x4,0x4,0x4,0x8,0x8,0x8,0x4, + 0x4,0x6,0x4,0x6,0x4,0x6,0x4,0x6}, {0x4,0x6}, 0x153}, + {0x0, 0x3, 0x2, NV_TRUE, NV_FALSE, {0x4,0x4,0x4,0x4,0xF,0xF,0xF,0x4, + 0x4,0x6,0x4,0x6,0x4,0x6,0x4,0x6}, {0x4,0x6}, 0x53}, + {0x0, 0x3, 0x2, NV_FALSE, NV_FALSE, {0x4,0x4,0x4,0x4,0xF,0xF,0xF,0x4, + 0x4,0x6,0x4,0x6,0x4,0x6,0x4,0x6}, {0x4,0x6}, 0x53}, + {0x0, 0x3, 0x1, NV_TRUE, NV_FALSE, {0x4,0x4,0x4,0x4,0xF,0xF,0xF,0x4, + 0x4,0xF,0x4,0xF,0x4,0xF,0x4,0xF}, {0x4,0xF}, 0x13}, + {0x0, 0x3, 0x1, NV_FALSE, NV_FALSE, {0x4,0x4,0x4,0x4,0xF,0xF,0xF,0x4, + 0x4,0xF,0x4,0xF,0x4,0xF,0x4,0xF}, {0x4,0xF}, 0x13}, + {0x0, 0x2, 0x3, NV_TRUE, NV_FALSE, {0x4,0x4,0x4,0x4,0x8,0x8,0x8,0x4, + 0x4,0x6,0x4,0x6,0x4,0x6,0x4,0x6}, {0x4,0x6}, 0x153}, + {0x0, 0x2, 0x3, NV_FALSE, NV_FALSE, {0x4,0x4,0x4,0x4,0x8,0x8,0x8,0x4, + 0x4,0x6,0x4,0x6,0x4,0x6,0x4,0x6}, {0x4,0x6}, 0x153}, + {0x0, 0x2, 0x2, NV_TRUE, NV_FALSE, {0x4,0x4,0x4,0x4,0xF,0xF,0xF,0x4, + 0x4,0x6,0x4,0x6,0x4,0x6,0x4,0x6}, {0x4,0x6}, 0x53}, + {0x0, 0x2, 0x2, NV_FALSE, NV_FALSE, {0x4,0x4,0x4,0x4,0xF,0xF,0xF,0x4, + 0x4,0x6,0x4,0x6,0x4,0x6,0x4,0x6}, {0x4,0x6}, 0x53}, + {0x0, 0x2, 0x1, NV_TRUE, NV_FALSE, {0x4,0x4,0x4,0x4,0xF,0xF,0xF,0x4, + 0x4,0xF,0x4,0xF,0x4,0xF,0x4,0xF}, {0x4,0xF}, 0x13}, + {0x0, 0x2, 0x1, NV_FALSE, NV_FALSE, {0x4,0x4,0x4,0x4,0xF,0xF,0xF,0x4, + 0x4,0xF,0x4,0xF,0x4,0xF,0x4,0xF}, {0x4,0xF}, 0x13}, + {0x0, 0x1, 0x3, NV_TRUE, NV_FALSE, {0x4,0x4,0x4,0x4,0x8,0x8,0x8,0x4, + 0x4,0x6,0x4,0x6,0x4,0x6,0x4,0x6}, {0x4,0x6}, 0x153}, + {0x0, 0x1, 0x3, NV_FALSE, NV_FALSE, {0x4,0x4,0x4,0x4,0x8,0x8,0x8,0x4, + 0x4,0x6,0x4,0x6,0x4,0x6,0x4,0x6}, {0x4,0x6}, 0x153}, + {0x0, 0x1, 0x2, NV_TRUE, NV_FALSE, {0x4,0x4,0x4,0x4,0xF,0xF,0xF,0x4, + 0x4,0x6,0x4,0x6,0x4,0x6,0x4,0x6}, {0x4,0x6}, 0x53}, + {0x0, 0x1, 0x2, NV_FALSE, NV_FALSE, {0x4,0x4,0x4,0x4,0xF,0xF,0xF,0x4, + 0x4,0x6,0x4,0x6,0x4,0x6,0x4,0x6}, {0x4,0x6}, 0x53}, + {0x0, 0x1, 0x1, NV_TRUE, NV_FALSE, {0x4,0x4,0x4,0x4,0xF,0xF,0xF,0x4, + 0x4,0xF,0x4,0xF,0x4,0xF,0x4,0xF}, {0x4,0xF}, 0x13}, + {0x0, 0x1, 0x1, NV_FALSE, NV_FALSE, {0x4,0x4,0x4,0x4,0xF,0xF,0xF,0x4, + 0x4,0xF,0x4,0xF,0x4,0xF,0x4,0xF}, {0x4,0xF}, 0x13} +}; /*! * @brief Returns the size of the PCE2LCE register array @@ -92,6 +191,63 @@ } } +/* + * Look up entry in NVLINK_CE_AUTO_CONFIG_TABLE + * + * @param[in] pGpu OBJGPU pointer + * @param[in] pCe OBJCE pointer + * @param[in] pCurrentTopo NVLINK_TOPOLOGY_INFO pointer + * @param[in] pAutoConfigTable NVLINK_CE_AUTO_CONFIG_TABLE pointer + * @param[in] autoConfigNumEntries NvU32 num entries within pAutoConfigTable + * @param[out] pIdx NvU32 pointer + * @param[out] pExposeCeMask NvU32 pointer + * + * Returns: NV_TRUE if entry is found + * NV_FALSE otheriwse +*/ +NvBool +kceGetAutoConfigTableEntry_GH100 +( + OBJGPU *pGpu, + KernelCE *pKCe, + NVLINK_TOPOLOGY_PARAMS *pCurrentTopo, + NVLINK_CE_AUTO_CONFIG_TABLE *pTable, + NvU32 autoConfigNumEntries, + NvU32 *pIdx, + NvU32 *pExposeCeMask +) +{ + NvU32 i; + + // + // The auto config table entries will only be applicable + // from this function in SHH cases. Rather than + // introduced a new entry in the table to note SHH, + // in order to preserve backwards compatibility this + // function will only attempt to map if we are confirmed + // to be in SHH path. + // + if (!gpuIsSelfHosted(pGpu)) + { + return NV_FALSE; + } + + for (i = 0; i < autoConfigNumEntries; i++) + { + if ((pTable[i].sysmemLinks == pCurrentTopo->sysmemLinks ) && + (pTable[i].maxLinksPerPeer == pCurrentTopo->maxLinksPerPeer) && + (pTable[i].bSymmetric == pCurrentTopo->bSymmetric ) && + (pTable[i].bSwitchConfig == pCurrentTopo->bSwitchConfig ) && + (pTable[i].numPeers == pCurrentTopo->numPeers )) + { + *pIdx = i; + *pExposeCeMask = pTable[i].exposeCeMask; + return NV_TRUE; + } + } + return NV_FALSE; +} + /** * @brief This function returns the pceIndex for a particular link ID * Must always be called with the hshub ID for the calling link ID @@ -115,6 +271,12 @@ NvU8 pHshubIdRequested; NvU32 i; + if ((pceIndex != NULL) && *pceIndex >= kceGetPce2lceConfigSize1_HAL(pKCe)) + { + NV_PRINTF(LEVEL_ERROR, "Invalid PCE request. pceIndex = %d pceCnt = %d\n", *pceIndex, kceGetPce2lceConfigSize1_HAL(pKCe)); + return; + } + if (!(NVBIT32(*pceIndex) & pceAvailableMaskPerHshub[*pHshubId])) { // @@ -201,8 +363,11 @@ for (i = 0; i < selectPcePerHshub; i++) { pceIndex = CE_GET_LOWEST_AVAILABLE_IDX(pceAvailableMaskPerHshub[hshubId]); - pceAvailableMaskPerHshub[hshubId] &= (~(NVBIT32(pceIndex))); - pLocalPceLceMap[pceIndex] = lceIndex; + if (pceIndex < kceGetPce2lceConfigSize1_HAL(pKCe)) + { + pceAvailableMaskPerHshub[hshubId] &= (~(NVBIT32(pceIndex))); + pLocalPceLceMap[pceIndex] = lceIndex; + } } } @@ -215,8 +380,11 @@ for (i = 0; i < selectPcePerHshub; i++) { pceIndex = CE_GET_LOWEST_AVAILABLE_IDX(pceAvailableMaskPerHshub[hshubId]); - pceAvailableMaskPerHshub[hshubId] &= (~(NVBIT32(pceIndex))); - pLocalPceLceMap[pceIndex] = lceIndex; + if (pceIndex < kceGetPce2lceConfigSize1_HAL(pKCe)) + { + pceAvailableMaskPerHshub[hshubId] &= (~(NVBIT32(pceIndex))); + pLocalPceLceMap[pceIndex] = lceIndex; + } } } } @@ -472,6 +640,8 @@ { NvU32 numLinksToPeer = knvlinkGetNumLinksToPeer(pGpu, pKernelNvlink, pRemoteGpu); + NvU32 maxLceCnt = NV_CE_MAX_LCE_MASK; + if (numLinksToPeer == 0) { continue; @@ -494,13 +664,16 @@ // Each peer gets 1 LCE lceIndex = CE_GET_LOWEST_AVAILABLE_IDX(peerAvailableLceMask); - lceMask |= NVBIT32(lceIndex); + HIGHESTBITIDX_32(maxLceCnt); + if (lceIndex < maxLceCnt) + { + lceMask |= NVBIT32(lceIndex); + // Clear out the chosen LCE + peerAvailableLceMask &= (~(NVBIT32(lceIndex))); + } pKCe->nvlinkNumPeers++; - // Clear out the chosen LCE - peerAvailableLceMask &= (~(NVBIT32(lceIndex))); - peerLinkMask = knvlinkGetLinkMaskToPeer(pGpu, pKernelNvlink, pRemoteGpu); if (peerLinkMask == 0) { @@ -615,6 +788,7 @@ NvU32 lceMask = 0; NvU32 pceMask = 0; NvU32 lceIndex, pceIndex, hshubId, i; + NvU32 maxLceCnt = NV_CE_MAX_LCE_MASK; peerAvailableLceMask = kceGetNvlinkPeerSupportedLceMask_HAL(pGpu, pKCe, peerAvailableLceMask); hshubId = 1; @@ -626,9 +800,13 @@ // Reference bug 3042556 // lceIndex = CE_GET_LOWEST_AVAILABLE_IDX(peerAvailableLceMask); - lceMask |= NVBIT32(lceIndex); - // Clear out the chosen LCE - peerAvailableLceMask &= (~(NVBIT32(lceIndex))); + HIGHESTBITIDX_32(maxLceCnt); + if (lceIndex < maxLceCnt) + { + lceMask |= NVBIT32(lceIndex); + // Clear out the chosen LCE + peerAvailableLceMask &= (~(NVBIT32(lceIndex))); + } // Assign PCEs to this LCE based on input request for (i = 0; i < numDefaultPces; i++) @@ -637,8 +815,11 @@ hshubId++; pceIndex = CE_GET_LOWEST_AVAILABLE_IDX(pceAvailableMaskPerHshub[hshubId]); - pceMask |= NVBIT32(pceIndex); - pceAvailableMaskPerHshub[hshubId] &= (~(NVBIT32(pceIndex))); + if (pceIndex < kceGetPce2lceConfigSize1_HAL(pKCe)) + { + pceMask |= NVBIT32(pceIndex); + pceAvailableMaskPerHshub[hshubId] &= (~(NVBIT32(pceIndex))); + } } FOR_EACH_INDEX_IN_MASK(32, pceIndex, pceMask) @@ -670,6 +851,46 @@ NV_STATUS status = NV_OK; NV_STATUS statusC2C = NV_OK; KernelNvlink *pKernelNvlink = GPU_GET_KERNEL_NVLINK(pGpu); + NvU32 topoIdx = NV_CE_INVALID_TOPO_IDX; + NvBool bEntryExists = NV_FALSE; + NvU32 pce2lceConfigSize1 = kceGetPce2lceConfigSize1_HAL(pKCe); + NvU32 grceConfigSize1 = kceGetGrceConfigSize1_HAL(pKCe); + NvU32 pceIdx, grceIdx; + + // + // In the self hosted case, utilize table entries + // with pre defined mappings. Calling from the parent would result in + // using the incorrect autoconfig table so instead set the necessary + // values here if config is found in the table. + // + if (gpuIsSelfHosted(pGpu) && !(pGpu->getProperty(pGpu, PDB_PROP_GPU_SKIP_TABLE_CE_MAP))) + { + bEntryExists = kceGetAutoConfigTableEntry_HAL(pGpu, pKCe, pTopoParams, nvLinkCeAutoConfigTable_GH100, + NV_ARRAY_ELEMENTS(nvLinkCeAutoConfigTable_GH100), + &topoIdx, pExposeCeMask); + if (bEntryExists) + { + // Since entry exists, fill local variables with the associated table entry + for (pceIdx = 0; pceIdx < pce2lceConfigSize1; pceIdx++) + { + pLocalPceLceMap[pceIdx] = nvLinkCeAutoConfigTable_GH100[topoIdx].pceLceMap[pceIdx]; + } + for (grceIdx = 0; grceIdx < grceConfigSize1; grceIdx++) + { + pLocalGrceMap[grceIdx] = nvLinkCeAutoConfigTable_GH100[topoIdx].grceConfig[grceIdx]; + } + + pTopoParams->maxTopoIdx = topoIdx; + pTopoParams->sysmemLinks = nvLinkCeAutoConfigTable_GH100[topoIdx].sysmemLinks; + pTopoParams->maxLinksPerPeer = nvLinkCeAutoConfigTable_GH100[topoIdx].maxLinksPerPeer; + pTopoParams->numPeers = nvLinkCeAutoConfigTable_GH100[topoIdx].numPeers; + pTopoParams->bSymmetric = nvLinkCeAutoConfigTable_GH100[topoIdx].bSymmetric; + pTopoParams->bSwitchConfig = nvLinkCeAutoConfigTable_GH100[topoIdx].bSwitchConfig; + + return NV_OK; + } + + } //Prepare the per-HSHUB/FBHUB available PCE mask kceGetAvailableHubPceMask(pGpu, pTopoParams); @@ -711,3 +932,204 @@ NV_PRINTF(LEVEL_INFO, "status = %d, statusC2C = %d\n", status, statusC2C); return NV_OK; } + +NV_STATUS kceGetP2PCes_GH100(KernelCE *pKCe, OBJGPU *pGpu, NvU32 gpuMask, NvU32 *nvlinkP2PCeMask) +{ + // + // Currently Bug 4103154 requires an updated algorithm described below + // to assign the proper LCE. Cases without MODS enabled can default back + // to the previous version. + // + return kceGetP2PCes_GV100(pKCe, pGpu, gpuMask, nvlinkP2PCeMask); + + NvU32 gpuCount = gpumgrGetSubDeviceCount(gpuMask); + NvU32 minP2PLce = (NV_CE_EVEN_ASYNC_LCE_MASK | NV_CE_ODD_ASYNC_LCE_MASK) & NV_CE_MAX_LCE_MASK; + NvU32 i; + KernelNvlink *pKernelNvlink = GPU_GET_KERNEL_NVLINK(pGpu); + + if (pKernelNvlink == NULL) + { + return NV_WARN_NOTHING_TO_DO; + } + + if (knvlinkIsGpuConnectedToNvswitch(pGpu, pKernelNvlink)) + { + return kceGetP2PCes_GV100(pKCe, pGpu, gpuMask, nvlinkP2PCeMask); + } + + LOWESTBITIDX_32(minP2PLce); + *nvlinkP2PCeMask = 0; + + if (gpuCount == 1) + { + *nvlinkP2PCeMask |= NVBIT(minP2PLce); + for (i = minP2PLce; i < gpuGetNumCEs(pGpu); i++) + { + *nvlinkP2PCeMask |= NVBIT(i); + + } + } + else if (gpuCount > 2) + { + // if gpuCount > 2, this is an invalid request. Print warning and return NV_OK + NV_PRINTF(LEVEL_INFO, "GPU %d invalid request for gpuCount %d\n", gpuGetInstance(pGpu), gpuCount); + return NV_ERR_INVALID_STATE; + } + else + { + OBJGPU *pRemoteGpu = NULL; + KernelCE *pKCeLoop = NULL; + NvU32 peerLinkMask = 0; + NvU32 gpuInstance = 0; + NvU32 phyLinkId, status, targetPceMask, numPces; + + // + // The LCE returned should be the LCE which has the most PCEs mapped + // on the given HSHUB. This HSHUB should be determined by + // tracking where the majority of links are connected. + // + NvU32 linksPerHshub[NV_CE_MAX_HSHUBS] = {0}; + NvU32 maxLinksConnectedHshub = 0; + NvU32 maxConnectedHshubId = NV_CE_MAX_HSHUBS; + NvU32 lceAssignedMask = 0; + KernelCE *maxLcePerHshub[NV_CE_MAX_HSHUBS] = {0}; + + NV2080_CTRL_INTERNAL_HSHUB_GET_HSHUB_ID_FOR_LINKS_PARAMS params; + + if (pKernelNvlink != NULL) + { + // Get the remote GPU + while ((pRemoteGpu = gpumgrGetNextGpu(gpuMask, &gpuInstance)) != NULL) + { + if (pRemoteGpu != pGpu) + break; + } + + NV_ASSERT_OR_RETURN(pRemoteGpu != NULL, NV_ERR_INVALID_STATE); + gpuInstance = gpuGetInstance(pRemoteGpu); + + peerLinkMask = knvlinkGetLinkMaskToPeer(pGpu, pKernelNvlink, pRemoteGpu); + } + + portMemSet(¶ms, 0, sizeof(params)); + params.linkMask = peerLinkMask; + + status = knvlinkExecGspRmRpc(pGpu, pKernelNvlink, + NV2080_CTRL_CMD_INTERNAL_HSHUB_GET_HSHUB_ID_FOR_LINKS, + (void *)¶ms, sizeof(params)); + NV_ASSERT_OK_OR_RETURN(status); + + + FOR_EACH_INDEX_IN_MASK(32, phyLinkId, peerLinkMask) + { + NvU32 hshubId = params.hshubIds[phyLinkId]; + linksPerHshub[hshubId]++; + + if (linksPerHshub[hshubId] > maxLinksConnectedHshub) + { + maxLinksConnectedHshub = linksPerHshub[hshubId]; + maxConnectedHshubId = hshubId; + } + } + FOR_EACH_INDEX_IN_MASK_END; + + // + // Iterate through all Async LCEs to track which HSHUB should + // be using which LCE. This is decided based on the majority. If + // there is a tie, then LCE with the lower index is preferred. + // + KCE_ITER_ALL_BEGIN(pGpu, pKCeLoop, minP2PLce) + NvU32 localMaxPcePerHshub = 0; + KernelCE *localMaxLcePerHshub; + NvU32 localMaxHshub = NV_CE_MAX_HSHUBS; + + // if LCE is stubbed or LCE is already assigned to another peer + if (pKCeLoop->bStubbed) + { + continue; + } + + // LCE is already assigned to this peer + if ((pKCeLoop->nvlinkPeerMask & NVBIT(gpuInstance)) != 0) + { + maxLcePerHshub[maxConnectedHshubId] = pKCeLoop; + break; + } + // LCE is already assigned to another peer + else if (pKCeLoop->nvlinkPeerMask != 0) + { + continue; + } + + NV2080_CTRL_CE_GET_CE_PCE_MASK_PARAMS params = {0}; + + params.ceEngineType = NV2080_ENGINE_TYPE_COPY(pKCeLoop->publicID); + status = knvlinkExecGspRmRpc(pGpu, pKernelNvlink, + NV2080_CTRL_CMD_CE_GET_CE_PCE_MASK, + (void *)¶ms, sizeof(params)); + NV_ASSERT_OK_OR_RETURN(status); + + // + // An LCE may be utilized across several HSHUBs. Loop through all HSHUBs + // in order to decide which HSHUB holds the majority of this specific LCE. + // To help with this, create a mask of PCEs only on the HSHUB which the peer + // is most connected to by shifting the HSHUB PCE mask + // + + for (i = NV_CE_HSHUBNVL_ID_0; i < NV_CE_MAX_HSHUBS; i++) + { + targetPceMask = params.pceMask & ((NVBIT(NV_CE_PCE_PER_HSHUB) - 1) << ((i - NV_CE_HSHUBNVL_ID_0) * NV_CE_PCE_PER_HSHUB)); + numPces = nvPopCount32(targetPceMask); + if (numPces > localMaxPcePerHshub && !(lceAssignedMask & NVBIT(pKCeLoop->publicID))) + { + localMaxPcePerHshub = numPces; + localMaxLcePerHshub = pKCeLoop; + localMaxHshub = i; + } + } + + if (localMaxHshub < NV_CE_MAX_HSHUBS) + { + maxLcePerHshub[localMaxHshub] = localMaxLcePerHshub; + lceAssignedMask |= NVBIT(localMaxLcePerHshub->publicID); + } + + KCE_ITER_END + + if (maxLcePerHshub[maxConnectedHshubId] != NULL) + { + NV_PRINTF(LEVEL_INFO, + "GPU %d Assigning Peer %d to preferred LCE %d\n", + gpuGetInstance(pGpu), gpuInstance, + maxLcePerHshub[maxConnectedHshubId]->publicID); + } + else + { + // + // In the event that the preferred HSHUB's primary LCE is not available, + // choose the first available LCE which was found and set that index as + // the new preferred hshub. + // + for (i = 0; i < NV_CE_MAX_HSHUBS; i++) + { + if (maxLcePerHshub[i] != NULL) + { + NV_PRINTF(LEVEL_INFO, + "GPU %d Assigning Peer %d to first available LCE %d\n", + gpuGetInstance(pGpu), gpuInstance, + maxLcePerHshub[i]->publicID); + maxConnectedHshubId = i; + break; + } + } + } + + if (maxConnectedHshubId < NV_CE_MAX_HSHUBS) + { + maxLcePerHshub[maxConnectedHshubId]->nvlinkPeerMask = NVBIT(gpuInstance); + *nvlinkP2PCeMask = NVBIT(maxLcePerHshub[maxConnectedHshubId]->publicID); + } + } + + return NV_OK; +} diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/kernel/gpu/ce/arch/pascal/kernel_ce_gp100.c nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/kernel/gpu/ce/arch/pascal/kernel_ce_gp100.c --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/kernel/gpu/ce/arch/pascal/kernel_ce_gp100.c 2023-10-25 20:20:54.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/kernel/gpu/ce/arch/pascal/kernel_ce_gp100.c 2024-03-05 22:13:17.000000000 +0000 @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 1993-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 1993-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -27,6 +27,7 @@ #include "gpu/ce/kernel_ce_private.h" #include "gpu/gpu.h" #include "kernel/gpu/nvlink/kernel_nvlink.h" +#include "kernel/gpu/conf_compute/conf_compute.h" NV_STATUS kceStateLoad_GP100(OBJGPU *pGpu, KernelCE *pKCe, NvU32 flags) { @@ -40,7 +41,40 @@ { NV_ASSERT_OK_OR_RETURN(kceTopLevelPceLceMappingsUpdate(pGpu, pKCe)); } + if (gpuIsCCFeatureEnabled(pGpu)) + { + ConfidentialCompute *pCC = GPU_GET_CONF_COMPUTE(pGpu); + switch (pKCe->publicID) + { + case 2: + NV_ASSERT_OK_OR_RETURN(confComputeDeriveSecrets(pCC, MC_ENGINE_IDX_CE2)); + break; + case 3: + NV_ASSERT_OK_OR_RETURN(confComputeDeriveSecrets(pCC, MC_ENGINE_IDX_CE3)); + break; + case 4: + NV_ASSERT_OK_OR_RETURN(confComputeDeriveSecrets(pCC, MC_ENGINE_IDX_CE4)); + break; + case 5: + NV_ASSERT_OK_OR_RETURN(confComputeDeriveSecrets(pCC, MC_ENGINE_IDX_CE5)); + break; + case 6: + NV_ASSERT_OK_OR_RETURN(confComputeDeriveSecrets(pCC, MC_ENGINE_IDX_CE6)); + break; + case 7: + NV_ASSERT_OK_OR_RETURN(confComputeDeriveSecrets(pCC, MC_ENGINE_IDX_CE7)); + break; + case 8: + NV_ASSERT_OK_OR_RETURN(confComputeDeriveSecrets(pCC, MC_ENGINE_IDX_CE8)); + break; + case 9: + NV_ASSERT_OK_OR_RETURN(confComputeDeriveSecrets(pCC, MC_ENGINE_IDX_CE9)); + break; + default: + break; + } + } return NV_OK; } diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/kernel/gpu/ce/kernel_ce.c nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/kernel/gpu/ce/kernel_ce.c --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/kernel/gpu/ce/kernel_ce.c 2023-10-25 20:20:55.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/kernel/gpu/ce/kernel_ce.c 2024-03-05 22:13:18.000000000 +0000 @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 1993-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 1993-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -104,6 +104,7 @@ PRINT_CAP(_CE_SUPPORTS_NONPIPELINED_BL); PRINT_CAP(_CE_SUPPORTS_PIPELINED_BL); + PRINT_CAP(_CE_CC_SECURE); } void kceGetNvlinkCaps(OBJGPU *pGpu, KernelCE *pKCe, NvU8 *pKCeCaps) @@ -220,7 +221,7 @@ { RM_API *pRmApi = GPU_GET_PHYSICAL_RMAPI(pGpu); - NV2080_CTRL_CE_UPDATE_CLASS_DB_PARAMS params; + NV2080_CTRL_CE_UPDATE_CLASS_DB_PARAMS params = {0}; NV_STATUS status = pRmApi->Control(pRmApi, pGpu->hInternalClient, @@ -335,7 +336,7 @@ // Set bUpdateNvlinkPceLce to auto-config status bUpdateNvlinkPceLce = pKCe->bIsAutoConfigEnabled; - if (bUpdateNvlinkPceLce) + if (bUpdateNvlinkPceLce || IS_SILICON(pGpu)) { status = kceGetNvlinkAutoConfigCeValues_HAL(pGpu, pKCe, pceLceMap, grceConfig, &exposeCeMask); @@ -372,7 +373,7 @@ // exposeCeMask will be 0x0 when bUpdateNvlinkPceLce is NV_FALSE. // RM_API *pRmApi = GPU_GET_PHYSICAL_RMAPI(pGpu); - NV2080_CTRL_CE_UPDATE_PCE_LCE_MAPPINGS_PARAMS params; + NV2080_CTRL_CE_UPDATE_PCE_LCE_MAPPINGS_PARAMS params = {0}; if (bUpdateNvlinkPceLce) { @@ -418,7 +419,7 @@ NV_STATUS kceGetFaultMethodBufferSize_IMPL(OBJGPU *pGpu, NvU32 *size) { RM_API *pRmApi = GPU_GET_PHYSICAL_RMAPI(pGpu); - NV2080_CTRL_CE_GET_FAULT_METHOD_BUFFER_SIZE_PARAMS params; + NV2080_CTRL_CE_GET_FAULT_METHOD_BUFFER_SIZE_PARAMS params = {0}; NV_ASSERT_OK_OR_RETURN(pRmApi->Control(pRmApi, pGpu->hInternalClient, pGpu->hInternalSubdevice, NV2080_CTRL_CMD_CE_GET_FAULT_METHOD_BUFFER_SIZE, ¶ms, sizeof(params))); @@ -444,7 +445,7 @@ ) { RM_API *pRmApi = GPU_GET_PHYSICAL_RMAPI(pGpu); - NV2080_CTRL_CE_GET_HUB_PCE_MASK_PARAMS params; + NV2080_CTRL_CE_GET_HUB_PCE_MASK_PARAMS params = {0}; NV_ASSERT_OR_RETURN(pTopoParams != NULL, NV_ERR_INVALID_ARGUMENT); ct_assert(NV_ARRAY_ELEMENTS(pTopoParams->pceAvailableMaskPerHshub) == NV_ARRAY_ELEMENTS(params.hshubPceMasks)); diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/kernel/gpu/ce/kernel_ce_context.c nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/kernel/gpu/ce/kernel_ce_context.c --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/kernel/gpu/ce/kernel_ce_context.c 2023-10-25 20:20:55.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/kernel/gpu/ce/kernel_ce_context.c 2024-03-05 22:13:18.000000000 +0000 @@ -24,6 +24,7 @@ #include "gpu/ce/kernel_ce_context.h" #include "gpu/ce/kernel_ce_private.h" #include "kernel/gpu/mig_mgr/kernel_mig_manager.h" +#include "kernel/gpu/device/device.h" #include "os/os.h" #include "resserv/rs_client.h" @@ -58,6 +59,16 @@ { CALL_CONTEXT *pCallContext = resservGetTlsCallContext(); NvU32 engineIndex = 0; + RsResourceRef *pDeviceRef; + NV_STATUS status = NV_OK; + Device *pDevice; + + NV_ASSERT_OK_OR_ELSE(status, + refFindAncestorOfType(pCallContext->pResourceRef, + classId(Device), &pDeviceRef), + return ENG_INVALID; ); + + pDevice = dynamicCast(pDeviceRef->pResource, Device); NV_ASSERT(pAllocParams); @@ -72,9 +83,8 @@ MIG_INSTANCE_REF ref; NV_ASSERT_OK( - kmigmgrGetInstanceRefFromClient(pGpu, pKernelMIGManager, - pCallContext->pClient->hClient, - &ref)); + kmigmgrGetInstanceRefFromDevice(pGpu, pKernelMIGManager, + pDevice, &ref)); NV_ASSERT_OK( kmigmgrGetLocalToGlobalEngineType(pGpu, pKernelMIGManager, ref, @@ -158,11 +168,13 @@ } } - NV_STATUS status = ceIndexFromType(pGpu, pCallContext->pClient->hClient, - RM_ENGINE_TYPE_COPY(engineIndex), &engineIndex); + status = ceIndexFromType(pGpu, pDevice, + RM_ENGINE_TYPE_COPY(engineIndex), &engineIndex); if (status == NV_OK) { NV_PRINTF(LEVEL_INFO, "Class %d, CE%d\n", externalClassId, engineIndex); + // confirm that engine is valid + NV_ASSERT_OR_RETURN(GPU_GET_KCE(pGpu, engineIndex), ENG_INVALID); return ENG_CE(engineIndex); } else @@ -179,20 +191,7 @@ RS_RES_ALLOC_PARAMS_INTERNAL *pParams ) { - ChannelDescendant *pChannelDescendant = staticCast(pKCeContext, ChannelDescendant); - OBJGPU *pGpu = GPU_RES_GET_GPU(pChannelDescendant); - NvU32 ceIdx = GET_CE_IDX(pChannelDescendant->resourceDesc.engDesc); - - // - // Don't do anything for AMODEL - // - if (IsAMODEL(pGpu)) - { - return NV_OK; - } - - NV_ASSERT_OR_RETURN(GPU_GET_KCE(pGpu, ceIdx), NV_ERR_INVALID_PARAMETER); - + // stub, initialization done in chandesConstruct return NV_OK; } diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/kernel/gpu/ce/kernel_ce_ctrl.c nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/kernel/gpu/ce/kernel_ce_ctrl.c --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/kernel/gpu/ce/kernel_ce_ctrl.c 2023-10-25 20:20:55.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/kernel/gpu/ce/kernel_ce_ctrl.c 2024-03-05 22:13:18.000000000 +0000 @@ -52,7 +52,7 @@ KernelCE *pKCe; NvU32 ceNumber; NV_STATUS status = NV_OK; - RM_ENGINE_TYPE rmEngineType; + RM_ENGINE_TYPE rmEngineType; LOCK_ASSERT_AND_RETURN(rmapiLockIsOwner()); @@ -66,6 +66,11 @@ rmEngineType = gpuGetRmEngineType(pCeCapsParams->ceEngineType); + if (!RM_ENGINE_TYPE_IS_COPY(rmEngineType)) + { + return NV_ERR_NOT_SUPPORTED; + } + // // vGPU: // @@ -98,7 +103,8 @@ return status; } - NV_ASSERT_OK_OR_RETURN(ceIndexFromType(pGpu, RES_GET_CLIENT_HANDLE(pSubdevice), rmEngineType, &ceNumber)); + NV_ASSERT_OK_OR_RETURN(ceIndexFromType(pGpu, GPU_RES_GET_DEVICE(pSubdevice), + rmEngineType, &ceNumber)); pKCe = GPU_GET_KCE(pGpu, ceNumber); @@ -111,4 +117,4 @@ // now fill in caps for this CE return kceGetDeviceCaps(pGpu, pKCe, rmEngineType, NvP64_VALUE(pCeCapsParams->capsTbl)); -} \ No newline at end of file +} diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/kernel/gpu/ce/kernel_ce_shared.c nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/kernel/gpu/ce/kernel_ce_shared.c --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/kernel/gpu/ce/kernel_ce_shared.c 2023-10-25 20:20:55.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/kernel/gpu/ce/kernel_ce_shared.c 2024-03-05 22:13:18.000000000 +0000 @@ -139,13 +139,20 @@ { OBJGPU *pGpu = GPU_RES_GET_GPU(pSubdevice); NvU32 ceNumber; - RM_ENGINE_TYPE rmEngineType = gpuGetRmEngineType(pCeCapsParams->ceEngineType); + RM_ENGINE_TYPE rmEngineType = gpuGetRmEngineType(pCeCapsParams->ceEngineType); LOCK_ASSERT_AND_RETURN(rmapiLockIsOwner()); NV_PRINTF(LEVEL_INFO, "NV2080_CTRL_CE_GET_CAPS_V2 ceEngineType = %d\n", pCeCapsParams->ceEngineType); - NV_ASSERT_OK_OR_RETURN(ceIndexFromType(pGpu, RES_GET_CLIENT_HANDLE(pSubdevice), rmEngineType, &ceNumber)); + if (!RM_ENGINE_TYPE_IS_COPY(rmEngineType)) + { + return NV_ERR_NOT_SUPPORTED; + } + + NV_ASSERT_OK_OR_RETURN(ceIndexFromType(pGpu, + GPU_RES_GET_DEVICE(pSubdevice), + rmEngineType, &ceNumber)); { KernelCE *pKCe = GPU_GET_KCE(pGpu, ceNumber); @@ -172,7 +179,7 @@ { RM_API *pRmApi; OBJGPU *pGpu = GPU_RES_GET_GPU(pSubdevice); - NvHandle hClient = RES_GET_CLIENT_HANDLE(pSubdevice); + Device *pDevice = GPU_RES_GET_DEVICE(pSubdevice); ct_assert(ENG_CE__SIZE_1 <= sizeof(pCeCapsParams->capsTbl) / sizeof(pCeCapsParams->capsTbl[0])); @@ -205,7 +212,7 @@ KernelCE *pKCe; KernelNvlink *pKernelNvlink = GPU_GET_KERNEL_NVLINK(pGpu); - KCE_ITER_CLIENT_BEGIN(pGpu, pKCe, hClient) + KCE_ITER_DEVICE_BEGIN(pGpu, pKCe, pDevice) if (pKCe->bStubbed) continue; diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/kernel/gpu/conf_compute/arch/hopper/conf_compute_gh100.c nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/kernel/gpu/conf_compute/arch/hopper/conf_compute_gh100.c --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/kernel/gpu/conf_compute/arch/hopper/conf_compute_gh100.c 1970-01-01 00:00:00.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/kernel/gpu/conf_compute/arch/hopper/conf_compute_gh100.c 2024-03-05 22:13:18.000000000 +0000 @@ -0,0 +1,452 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2021-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +/***************************************************************************\ + * * + * Confidential Compute HALs * + * * + \**************************************************************************/ + +#define NVOC_CONF_COMPUTE_H_PRIVATE_ACCESS_ALLOWED + +#include "gpu/conf_compute/conf_compute.h" +#include "published/hopper/gh100/dev_fuse.h" +#include "rmapi/rmapi.h" +#include "conf_compute/cc_keystore.h" + +/*! + * check if debug mode is enabled. + * + * @param[in] pGpu GPU object pointer + * @param[in] pConfCompute ConfidentialCompute pointer + */ +NvBool +confComputeIsDebugModeEnabled_GH100 +( + OBJGPU *pGpu, + ConfidentialCompute *pConfCompute +) +{ + NvU32 fuseStat = GPU_REG_RD32(pGpu, NV_FUSE_OPT_SECURE_GSP_DEBUG_DIS); + + return !FLD_TEST_DRF(_FUSE_OPT, _SECURE_GSP_DEBUG_DIS, _DATA, _YES, fuseStat); +} + +/*! + * @brief confComputeIsGpuCcCapable + * Checks if Gpu can handle ConfCompute workloads. + * + * @param[in] pGpu : OBJGPU Pointer + * @param[in] pConfCompute : ConfidentialCompute pointer + */ +NvBool +confComputeIsGpuCcCapable_GH100 +( + OBJGPU *pGpu, + ConfidentialCompute *pConfCompute +) +{ + NvU32 reg; + + if (confComputeIsDebugModeEnabled_HAL(pGpu, pConfCompute)) + { + NV_PRINTF(LEVEL_ERROR, "Not checking if GPU is capable of accepting conf compute workloads\n"); + return NV_TRUE; + } + + reg = GPU_REG_RD32(pGpu, NV_FUSE_SPARE_BIT_0); + if (FLD_TEST_DRF(_FUSE, _SPARE_BIT_0, _DATA, _ENABLE, reg)) + { + if (FLD_TEST_DRF(_FUSE, _SPARE_BIT_1, _DATA, _ENABLE, GPU_REG_RD32(pGpu, NV_FUSE_SPARE_BIT_1)) + && FLD_TEST_DRF(_FUSE, _SPARE_BIT_2, _DATA, _DISABLE, GPU_REG_RD32(pGpu, NV_FUSE_SPARE_BIT_2))) + { + return NV_TRUE; + } + } + return NV_FALSE; +} + +NV_STATUS +confComputeDeriveSecrets_GH100(ConfidentialCompute *pConfCompute, + NvU32 engine) +{ + OBJGPU *pGpu = ENG_GET_GPU(pConfCompute); + RM_API *pRmApi = GPU_GET_PHYSICAL_RMAPI(pGpu); + + switch (engine) + { + case MC_ENGINE_IDX_GSP: + // GSP automatically derives these keys so no need for CPU-RM to trigger it. + NV_ASSERT_OK_OR_RETURN(confComputeKeyStoreDeriveKey_HAL(pConfCompute, + CC_GKEYID_GEN(CC_KEYSPACE_GSP, CC_LKEYID_GSP_CPU_LOCKED_RPC))); + NV_ASSERT_OK_OR_RETURN(confComputeKeyStoreDeriveKey_HAL(pConfCompute, + CC_GKEYID_GEN(CC_KEYSPACE_GSP, CC_LKEYID_CPU_GSP_LOCKED_RPC))); + NV_ASSERT_OK_OR_RETURN(confComputeKeyStoreDeriveKey_HAL(pConfCompute, + CC_GKEYID_GEN(CC_KEYSPACE_GSP, CC_LKEYID_GSP_CPU_DMA))); + NV_ASSERT_OK_OR_RETURN(confComputeKeyStoreDeriveKey_HAL(pConfCompute, + CC_GKEYID_GEN(CC_KEYSPACE_GSP, CC_LKEYID_CPU_GSP_DMA))); + NV_ASSERT_OK_OR_RETURN(confComputeKeyStoreDeriveKey_HAL(pConfCompute, + CC_GKEYID_GEN(CC_KEYSPACE_GSP, CC_LKEYID_GSP_CPU_REPLAYABLE_FAULT))); + NV_ASSERT_OK_OR_RETURN(confComputeKeyStoreDeriveKey_HAL(pConfCompute, + CC_GKEYID_GEN(CC_KEYSPACE_GSP, CC_LKEYID_GSP_CPU_NON_REPLAYABLE_FAULT))); + break; + case MC_ENGINE_IDX_SEC2: + { + NV2080_CTRL_INTERNAL_CONF_COMPUTE_DERIVE_SWL_KEYS_PARAMS params = {0}; + + params.engineId = NV2080_ENGINE_TYPE_SEC2; + NV_ASSERT_OK_OR_RETURN(pRmApi->Control(pRmApi, + pGpu->hInternalClient, + pGpu->hInternalSubdevice, + NV2080_CTRL_CMD_INTERNAL_CONF_COMPUTE_DERIVE_SWL_KEYS, + ¶ms, + sizeof(params))); + + confComputeKeyStoreDepositIvMask_HAL(pConfCompute, + CC_GKEYID_GEN(CC_KEYSPACE_SEC2, CC_LKEYID_CPU_SEC2_DATA_USER), + (void*)¶ms.ivMaskSet[NV2080_CTRL_INTERNAL_CONF_COMPUTE_IVMASK_SWL_USER].ivMask[0]); + + confComputeKeyStoreDepositIvMask_HAL(pConfCompute, + CC_GKEYID_GEN(CC_KEYSPACE_SEC2, CC_LKEYID_CPU_SEC2_DATA_KERN), + (void*)¶ms.ivMaskSet[NV2080_CTRL_INTERNAL_CONF_COMPUTE_IVMASK_SWL_KERNEL].ivMask[0]); + + NV_ASSERT_OK_OR_RETURN(confComputeKeyStoreDeriveKey_HAL(pConfCompute, + CC_GKEYID_GEN(CC_KEYSPACE_SEC2, CC_LKEYID_CPU_SEC2_DATA_USER))); + NV_ASSERT_OK_OR_RETURN(confComputeKeyStoreDeriveKey_HAL(pConfCompute, + CC_GKEYID_GEN(CC_KEYSPACE_SEC2, CC_LKEYID_CPU_SEC2_HMAC_USER))); + NV_ASSERT_OK_OR_RETURN(confComputeKeyStoreDeriveKey_HAL(pConfCompute, + CC_GKEYID_GEN(CC_KEYSPACE_SEC2, CC_LKEYID_CPU_SEC2_DATA_KERN))); + NV_ASSERT_OK_OR_RETURN(confComputeKeyStoreDeriveKey_HAL(pConfCompute, + CC_GKEYID_GEN(CC_KEYSPACE_SEC2, CC_LKEYID_CPU_SEC2_HMAC_KERN))); + } + break; + case MC_ENGINE_IDX_CE2: + { + NV2080_CTRL_INTERNAL_CONF_COMPUTE_DERIVE_LCE_KEYS_PARAMS params = {0}; + + params.engineId = NV2080_ENGINE_TYPE_COPY0; + NV_ASSERT_OK_OR_RETURN(pRmApi->Control(pRmApi, + pGpu->hInternalClient, + pGpu->hInternalSubdevice, + NV2080_CTRL_CMD_INTERNAL_CONF_COMPUTE_DERIVE_LCE_KEYS, + ¶ms, + sizeof(params))); + + NV_ASSERT_OK_OR_RETURN(confComputeKeyStoreDeriveKey_HAL(pConfCompute, + CC_GKEYID_GEN(CC_KEYSPACE_LCE0, CC_LKEYID_LCE_H2D_USER))); + NV_ASSERT_OK_OR_RETURN(confComputeKeyStoreDeriveKey_HAL(pConfCompute, + CC_GKEYID_GEN(CC_KEYSPACE_LCE0, CC_LKEYID_LCE_D2H_USER))); + NV_ASSERT_OK_OR_RETURN(confComputeKeyStoreDeriveKey_HAL(pConfCompute, + CC_GKEYID_GEN(CC_KEYSPACE_LCE0, CC_LKEYID_LCE_H2D_KERN))); + NV_ASSERT_OK_OR_RETURN(confComputeKeyStoreDeriveKey_HAL(pConfCompute, + CC_GKEYID_GEN(CC_KEYSPACE_LCE0, CC_LKEYID_LCE_D2H_KERN))); + + confComputeKeyStoreDepositIvMask_HAL(pConfCompute, + CC_GKEYID_GEN(CC_KEYSPACE_LCE0, CC_LKEYID_LCE_H2D_USER), + (void*)¶ms.ivMaskSet[0].ivMask); + + confComputeKeyStoreDepositIvMask_HAL(pConfCompute, + CC_GKEYID_GEN(CC_KEYSPACE_LCE0, CC_LKEYID_LCE_D2H_USER), + (void*)¶ms.ivMaskSet[1].ivMask); + + confComputeKeyStoreDepositIvMask_HAL(pConfCompute, + CC_GKEYID_GEN(CC_KEYSPACE_LCE0, CC_LKEYID_LCE_H2D_KERN), + (void*)¶ms.ivMaskSet[2].ivMask); + + confComputeKeyStoreDepositIvMask_HAL(pConfCompute, + CC_GKEYID_GEN(CC_KEYSPACE_LCE0, CC_LKEYID_LCE_D2H_KERN), + (void*)¶ms.ivMaskSet[3].ivMask); + break; + } + case MC_ENGINE_IDX_CE3: + { + NV2080_CTRL_INTERNAL_CONF_COMPUTE_DERIVE_LCE_KEYS_PARAMS params = {0}; + + params.engineId = NV2080_ENGINE_TYPE_COPY1; + NV_ASSERT_OK_OR_RETURN(pRmApi->Control(pRmApi, + pGpu->hInternalClient, + pGpu->hInternalSubdevice, + NV2080_CTRL_CMD_INTERNAL_CONF_COMPUTE_DERIVE_LCE_KEYS, + ¶ms, + sizeof(params))); + + NV_ASSERT_OK_OR_RETURN(confComputeKeyStoreDeriveKey_HAL(pConfCompute, + CC_GKEYID_GEN(CC_KEYSPACE_LCE1, CC_LKEYID_LCE_H2D_USER))); + NV_ASSERT_OK_OR_RETURN(confComputeKeyStoreDeriveKey_HAL(pConfCompute, + CC_GKEYID_GEN(CC_KEYSPACE_LCE1, CC_LKEYID_LCE_D2H_USER))); + NV_ASSERT_OK_OR_RETURN(confComputeKeyStoreDeriveKey_HAL(pConfCompute, + CC_GKEYID_GEN(CC_KEYSPACE_LCE1, CC_LKEYID_LCE_H2D_KERN))); + NV_ASSERT_OK_OR_RETURN(confComputeKeyStoreDeriveKey_HAL(pConfCompute, + CC_GKEYID_GEN(CC_KEYSPACE_LCE1, CC_LKEYID_LCE_D2H_KERN))); + + confComputeKeyStoreDepositIvMask_HAL(pConfCompute, + CC_GKEYID_GEN(CC_KEYSPACE_LCE1, CC_LKEYID_LCE_H2D_USER), + (void*)¶ms.ivMaskSet[0].ivMask); + + confComputeKeyStoreDepositIvMask_HAL(pConfCompute, + CC_GKEYID_GEN(CC_KEYSPACE_LCE1, CC_LKEYID_LCE_D2H_USER), + (void*)¶ms.ivMaskSet[1].ivMask); + + confComputeKeyStoreDepositIvMask_HAL(pConfCompute, + CC_GKEYID_GEN(CC_KEYSPACE_LCE1, CC_LKEYID_LCE_H2D_KERN), + (void*)¶ms.ivMaskSet[2].ivMask); + + confComputeKeyStoreDepositIvMask_HAL(pConfCompute, + CC_GKEYID_GEN(CC_KEYSPACE_LCE1, CC_LKEYID_LCE_D2H_KERN), + (void*)¶ms.ivMaskSet[3].ivMask); + break; + } + case MC_ENGINE_IDX_CE4: + { + NV2080_CTRL_INTERNAL_CONF_COMPUTE_DERIVE_LCE_KEYS_PARAMS params = {0}; + + params.engineId = NV2080_ENGINE_TYPE_COPY2; + NV_ASSERT_OK_OR_RETURN(pRmApi->Control(pRmApi, + pGpu->hInternalClient, + pGpu->hInternalSubdevice, + NV2080_CTRL_CMD_INTERNAL_CONF_COMPUTE_DERIVE_LCE_KEYS, + ¶ms, + sizeof(params))); + + NV_ASSERT_OK_OR_RETURN(confComputeKeyStoreDeriveKey_HAL(pConfCompute, + CC_GKEYID_GEN(CC_KEYSPACE_LCE2, CC_LKEYID_LCE_H2D_USER))); + NV_ASSERT_OK_OR_RETURN(confComputeKeyStoreDeriveKey_HAL(pConfCompute, + CC_GKEYID_GEN(CC_KEYSPACE_LCE2, CC_LKEYID_LCE_D2H_USER))); + NV_ASSERT_OK_OR_RETURN(confComputeKeyStoreDeriveKey_HAL(pConfCompute, + CC_GKEYID_GEN(CC_KEYSPACE_LCE2, CC_LKEYID_LCE_H2D_KERN))); + NV_ASSERT_OK_OR_RETURN(confComputeKeyStoreDeriveKey_HAL(pConfCompute, + CC_GKEYID_GEN(CC_KEYSPACE_LCE2, CC_LKEYID_LCE_D2H_KERN))); + + confComputeKeyStoreDepositIvMask_HAL(pConfCompute, + CC_GKEYID_GEN(CC_KEYSPACE_LCE2, CC_LKEYID_LCE_H2D_USER), + (void*)¶ms.ivMaskSet[0].ivMask); + + confComputeKeyStoreDepositIvMask_HAL(pConfCompute, + CC_GKEYID_GEN(CC_KEYSPACE_LCE2, CC_LKEYID_LCE_D2H_USER), + (void*)¶ms.ivMaskSet[1].ivMask); + + confComputeKeyStoreDepositIvMask_HAL(pConfCompute, + CC_GKEYID_GEN(CC_KEYSPACE_LCE2, CC_LKEYID_LCE_H2D_KERN), + (void*)¶ms.ivMaskSet[2].ivMask); + + confComputeKeyStoreDepositIvMask_HAL(pConfCompute, + CC_GKEYID_GEN(CC_KEYSPACE_LCE2, CC_LKEYID_LCE_D2H_KERN), + (void*)¶ms.ivMaskSet[3].ivMask); + break; + } + case MC_ENGINE_IDX_CE5: + { + NV2080_CTRL_INTERNAL_CONF_COMPUTE_DERIVE_LCE_KEYS_PARAMS params = {0}; + + params.engineId = NV2080_ENGINE_TYPE_COPY3; + NV_ASSERT_OK_OR_RETURN(pRmApi->Control(pRmApi, + pGpu->hInternalClient, + pGpu->hInternalSubdevice, + NV2080_CTRL_CMD_INTERNAL_CONF_COMPUTE_DERIVE_LCE_KEYS, + ¶ms, + sizeof(params))); + + NV_ASSERT_OK_OR_RETURN(confComputeKeyStoreDeriveKey_HAL(pConfCompute, + CC_GKEYID_GEN(CC_KEYSPACE_LCE3, CC_LKEYID_LCE_H2D_USER))); + NV_ASSERT_OK_OR_RETURN(confComputeKeyStoreDeriveKey_HAL(pConfCompute, + CC_GKEYID_GEN(CC_KEYSPACE_LCE3, CC_LKEYID_LCE_D2H_USER))); + NV_ASSERT_OK_OR_RETURN(confComputeKeyStoreDeriveKey_HAL(pConfCompute, + CC_GKEYID_GEN(CC_KEYSPACE_LCE3, CC_LKEYID_LCE_H2D_KERN))); + NV_ASSERT_OK_OR_RETURN(confComputeKeyStoreDeriveKey_HAL(pConfCompute, + CC_GKEYID_GEN(CC_KEYSPACE_LCE3, CC_LKEYID_LCE_D2H_KERN))); + + confComputeKeyStoreDepositIvMask_HAL(pConfCompute, + CC_GKEYID_GEN(CC_KEYSPACE_LCE3, CC_LKEYID_LCE_H2D_USER), + (void*)¶ms.ivMaskSet[0].ivMask); + + confComputeKeyStoreDepositIvMask_HAL(pConfCompute, + CC_GKEYID_GEN(CC_KEYSPACE_LCE3, CC_LKEYID_LCE_D2H_USER), + (void*)¶ms.ivMaskSet[1].ivMask); + + confComputeKeyStoreDepositIvMask_HAL(pConfCompute, + CC_GKEYID_GEN(CC_KEYSPACE_LCE3, CC_LKEYID_LCE_H2D_KERN), + (void*)¶ms.ivMaskSet[2].ivMask); + + confComputeKeyStoreDepositIvMask_HAL(pConfCompute, + CC_GKEYID_GEN(CC_KEYSPACE_LCE3, CC_LKEYID_LCE_D2H_KERN), + (void*)¶ms.ivMaskSet[3].ivMask); + break; + } + case MC_ENGINE_IDX_CE6: + { + NV2080_CTRL_INTERNAL_CONF_COMPUTE_DERIVE_LCE_KEYS_PARAMS params = {0}; + + params.engineId = NV2080_ENGINE_TYPE_COPY4; + NV_ASSERT_OK_OR_RETURN(pRmApi->Control(pRmApi, + pGpu->hInternalClient, + pGpu->hInternalSubdevice, + NV2080_CTRL_CMD_INTERNAL_CONF_COMPUTE_DERIVE_LCE_KEYS, + ¶ms, + sizeof(params))); + + NV_ASSERT_OK_OR_RETURN(confComputeKeyStoreDeriveKey_HAL(pConfCompute, + CC_GKEYID_GEN(CC_KEYSPACE_LCE4, CC_LKEYID_LCE_H2D_USER))); + NV_ASSERT_OK_OR_RETURN(confComputeKeyStoreDeriveKey_HAL(pConfCompute, + CC_GKEYID_GEN(CC_KEYSPACE_LCE4, CC_LKEYID_LCE_D2H_USER))); + NV_ASSERT_OK_OR_RETURN(confComputeKeyStoreDeriveKey_HAL(pConfCompute, + CC_GKEYID_GEN(CC_KEYSPACE_LCE4, CC_LKEYID_LCE_H2D_KERN))); + NV_ASSERT_OK_OR_RETURN(confComputeKeyStoreDeriveKey_HAL(pConfCompute, + CC_GKEYID_GEN(CC_KEYSPACE_LCE4, CC_LKEYID_LCE_D2H_KERN))); + + confComputeKeyStoreDepositIvMask_HAL(pConfCompute, + CC_GKEYID_GEN(CC_KEYSPACE_LCE4, CC_LKEYID_LCE_H2D_USER), + (void*)¶ms.ivMaskSet[0].ivMask); + + confComputeKeyStoreDepositIvMask_HAL(pConfCompute, + CC_GKEYID_GEN(CC_KEYSPACE_LCE4, CC_LKEYID_LCE_D2H_USER), + (void*)¶ms.ivMaskSet[1].ivMask); + + confComputeKeyStoreDepositIvMask_HAL(pConfCompute, + CC_GKEYID_GEN(CC_KEYSPACE_LCE4, CC_LKEYID_LCE_H2D_KERN), + (void*)¶ms.ivMaskSet[2].ivMask); + + confComputeKeyStoreDepositIvMask_HAL(pConfCompute, + CC_GKEYID_GEN(CC_KEYSPACE_LCE4, CC_LKEYID_LCE_D2H_KERN), + (void*)¶ms.ivMaskSet[3].ivMask); + break; + } + case MC_ENGINE_IDX_CE7: + { + NV2080_CTRL_INTERNAL_CONF_COMPUTE_DERIVE_LCE_KEYS_PARAMS params = {0}; + + params.engineId = NV2080_ENGINE_TYPE_COPY5; + NV_ASSERT_OK_OR_RETURN(pRmApi->Control(pRmApi, + pGpu->hInternalClient, + pGpu->hInternalSubdevice, + NV2080_CTRL_CMD_INTERNAL_CONF_COMPUTE_DERIVE_LCE_KEYS, + ¶ms, + sizeof(params))); + + NV_ASSERT_OK_OR_RETURN(confComputeKeyStoreDeriveKey_HAL(pConfCompute, + CC_GKEYID_GEN(CC_KEYSPACE_LCE5, CC_LKEYID_LCE_H2D_USER))); + NV_ASSERT_OK_OR_RETURN(confComputeKeyStoreDeriveKey_HAL(pConfCompute, + CC_GKEYID_GEN(CC_KEYSPACE_LCE5, CC_LKEYID_LCE_D2H_USER))); + NV_ASSERT_OK_OR_RETURN(confComputeKeyStoreDeriveKey_HAL(pConfCompute, + CC_GKEYID_GEN(CC_KEYSPACE_LCE5, CC_LKEYID_LCE_H2D_KERN))); + NV_ASSERT_OK_OR_RETURN(confComputeKeyStoreDeriveKey_HAL(pConfCompute, + CC_GKEYID_GEN(CC_KEYSPACE_LCE5, CC_LKEYID_LCE_D2H_KERN))); + + confComputeKeyStoreDepositIvMask_HAL(pConfCompute, + CC_GKEYID_GEN(CC_KEYSPACE_LCE5, CC_LKEYID_LCE_H2D_USER), + (void*)¶ms.ivMaskSet[0].ivMask); + + confComputeKeyStoreDepositIvMask_HAL(pConfCompute, + CC_GKEYID_GEN(CC_KEYSPACE_LCE5, CC_LKEYID_LCE_D2H_USER), + (void*)¶ms.ivMaskSet[1].ivMask); + + confComputeKeyStoreDepositIvMask_HAL(pConfCompute, + CC_GKEYID_GEN(CC_KEYSPACE_LCE5, CC_LKEYID_LCE_H2D_KERN), + (void*)¶ms.ivMaskSet[2].ivMask); + + confComputeKeyStoreDepositIvMask_HAL(pConfCompute, + CC_GKEYID_GEN(CC_KEYSPACE_LCE5, CC_LKEYID_LCE_D2H_KERN), + (void*)¶ms.ivMaskSet[3].ivMask); + break; + } + case MC_ENGINE_IDX_CE8: + { + NV2080_CTRL_INTERNAL_CONF_COMPUTE_DERIVE_LCE_KEYS_PARAMS params = {0}; + + params.engineId = NV2080_ENGINE_TYPE_COPY6; + NV_ASSERT_OK_OR_RETURN(pRmApi->Control(pRmApi, + pGpu->hInternalClient, + pGpu->hInternalSubdevice, + NV2080_CTRL_CMD_INTERNAL_CONF_COMPUTE_DERIVE_LCE_KEYS, + ¶ms, + sizeof(params))); + + NV_ASSERT_OK_OR_RETURN(confComputeKeyStoreDeriveKey_HAL(pConfCompute, + CC_GKEYID_GEN(CC_KEYSPACE_LCE6, CC_LKEYID_LCE_H2D_USER))); + NV_ASSERT_OK_OR_RETURN(confComputeKeyStoreDeriveKey_HAL(pConfCompute, + CC_GKEYID_GEN(CC_KEYSPACE_LCE6, CC_LKEYID_LCE_D2H_USER))); + NV_ASSERT_OK_OR_RETURN(confComputeKeyStoreDeriveKey_HAL(pConfCompute, + CC_GKEYID_GEN(CC_KEYSPACE_LCE6, CC_LKEYID_LCE_H2D_KERN))); + NV_ASSERT_OK_OR_RETURN(confComputeKeyStoreDeriveKey_HAL(pConfCompute, + CC_GKEYID_GEN(CC_KEYSPACE_LCE6, CC_LKEYID_LCE_D2H_KERN))); + + confComputeKeyStoreDepositIvMask_HAL(pConfCompute, + CC_GKEYID_GEN(CC_KEYSPACE_LCE6, CC_LKEYID_LCE_H2D_USER), + (void*)¶ms.ivMaskSet[0].ivMask); + + confComputeKeyStoreDepositIvMask_HAL(pConfCompute, + CC_GKEYID_GEN(CC_KEYSPACE_LCE6, CC_LKEYID_LCE_D2H_USER), + (void*)¶ms.ivMaskSet[1].ivMask); + + confComputeKeyStoreDepositIvMask_HAL(pConfCompute, + CC_GKEYID_GEN(CC_KEYSPACE_LCE6, CC_LKEYID_LCE_H2D_KERN), + (void*)¶ms.ivMaskSet[2].ivMask); + + confComputeKeyStoreDepositIvMask_HAL(pConfCompute, + CC_GKEYID_GEN(CC_KEYSPACE_LCE6, CC_LKEYID_LCE_D2H_KERN), + (void*)¶ms.ivMaskSet[3].ivMask); + break; + } + case MC_ENGINE_IDX_CE9: + { + NV2080_CTRL_INTERNAL_CONF_COMPUTE_DERIVE_LCE_KEYS_PARAMS params = {0}; + + params.engineId = NV2080_ENGINE_TYPE_COPY7; + NV_ASSERT_OK_OR_RETURN(pRmApi->Control(pRmApi, + pGpu->hInternalClient, + pGpu->hInternalSubdevice, + NV2080_CTRL_CMD_INTERNAL_CONF_COMPUTE_DERIVE_LCE_KEYS, + ¶ms, + sizeof(params))); + + NV_ASSERT_OK_OR_RETURN(confComputeKeyStoreDeriveKey_HAL(pConfCompute, + CC_GKEYID_GEN(CC_KEYSPACE_LCE7, CC_LKEYID_LCE_H2D_USER))); + NV_ASSERT_OK_OR_RETURN(confComputeKeyStoreDeriveKey_HAL(pConfCompute, + CC_GKEYID_GEN(CC_KEYSPACE_LCE7, CC_LKEYID_LCE_D2H_USER))); + NV_ASSERT_OK_OR_RETURN(confComputeKeyStoreDeriveKey_HAL(pConfCompute, + CC_GKEYID_GEN(CC_KEYSPACE_LCE7, CC_LKEYID_LCE_H2D_KERN))); + NV_ASSERT_OK_OR_RETURN(confComputeKeyStoreDeriveKey_HAL(pConfCompute, + CC_GKEYID_GEN(CC_KEYSPACE_LCE7, CC_LKEYID_LCE_D2H_KERN))); + + confComputeKeyStoreDepositIvMask_HAL(pConfCompute, + CC_GKEYID_GEN(CC_KEYSPACE_LCE7, CC_LKEYID_LCE_H2D_USER), + (void*)¶ms.ivMaskSet[0].ivMask); + + confComputeKeyStoreDepositIvMask_HAL(pConfCompute, + CC_GKEYID_GEN(CC_KEYSPACE_LCE7, CC_LKEYID_LCE_D2H_USER), + (void*)¶ms.ivMaskSet[1].ivMask); + + confComputeKeyStoreDepositIvMask_HAL(pConfCompute, + CC_GKEYID_GEN(CC_KEYSPACE_LCE7, CC_LKEYID_LCE_H2D_KERN), + (void*)¶ms.ivMaskSet[2].ivMask); + + confComputeKeyStoreDepositIvMask_HAL(pConfCompute, + CC_GKEYID_GEN(CC_KEYSPACE_LCE7, CC_LKEYID_LCE_D2H_KERN), + (void*)¶ms.ivMaskSet[3].ivMask); + break; + } + default: + return NV_ERR_INVALID_ARGUMENT; + } + + return NV_OK; +} diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/kernel/gpu/conf_compute/arch/hopper/conf_compute_keystore_gh100.c nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/kernel/gpu/conf_compute/arch/hopper/conf_compute_keystore_gh100.c --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/kernel/gpu/conf_compute/arch/hopper/conf_compute_keystore_gh100.c 1970-01-01 00:00:00.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/kernel/gpu/conf_compute/arch/hopper/conf_compute_keystore_gh100.c 2024-03-05 22:13:18.000000000 +0000 @@ -0,0 +1,629 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#define NVOC_CONF_COMPUTE_H_PRIVATE_ACCESS_ALLOWED + +#include "kernel/gpu/conf_compute/conf_compute.h" +#include "class/cl2080.h" +#include "libraries/nvport/nvport.h" +#include "kernel/gpu/spdm/libspdm_includes.h" +#include "hal/library/cryptlib.h" + +// +// The keystore holds keys, IV masks, and IVs for the LCE, SEC2, and GSP channels. It owns the channel +// counter for each key and helps prevent IV reuse. The keystore is comprised of key slots. A key +// slot holds either AES (key, IV mask, IV) or HMAC (key, nonce) secrets. Key slots are paired +// so that the even-numbered key slot typically holds the host-to-device secrets and the subsequent +// odd-numbered key slot typically holds the device-to-host secrets. The flow for accessing +// the keystore is: +// +// 1. confComputeKeyStoreInit() +// 2. confComputeKeyStoreGetExportMasterKey() +// a. Caller copies the Export Master Key into the keystore. +// 4. confComputeKeyStoreDeriveKey() as needed. +// a. Caller retrieves IV masks from GSP and calls confComputeKeyStoreDepositIvMask() as needed. +// 5. confComputeKeyStoreClearExportMasterKey() once all keys have been derived. +// 6. confComputeKeyStoreRetrieveVia*() as needed. +// 7. confComputeKeyStoreUpdateKey() as needed. +// 8. confComputeKeyStoreDeinit() at the end of the confidential compute session. +// + +#define CONCAT64(hi, low) ((((NvU64)(hi) << 32)) | ((NvU64)(low))) + +typedef struct cryptoBundle_t +{ + union + { + CC_AES_CRYPTOBUNDLE cryptBundle; + CC_HMAC_CRYPTOBUNDLE hmacBundle; + }; + enum {NO_CHAN_COUNTER, CRYPT_COUNTER, HMAC_COUNTER} type; +} cryptoBundle_t; + +typedef cryptoBundle_t keySlot_t[CC_KEYSPACE_TOTAL_SIZE]; + +static NV_STATUS checkSlot(ConfidentialCompute *pConfCompute, NvU32 slotNumber); +static void incrementChannelCounter(ConfidentialCompute *pConfCompute, NvU32 slotNumber); +static NvU64 getChannelCounter(ConfidentialCompute *pConfCompute, NvU32 slotNumber); +static NV_STATUS getKeyIdLce(KernelChannel *pKernelChannel, ROTATE_IV_TYPE rotateOperation, + NvU16 *keyId); +static NV_STATUS getKeyIdSec2(KernelChannel *pKernelChannel, ROTATE_IV_TYPE rotateOperation, + NvU16 *keyId); +static NV_STATUS getKeyspaceLce(KernelChannel *pKernelChannel, NvU16 *keyspace); +static NvU32 getKeySlotFromGlobalKeyId (NvU32 globalKeyId); +static NvU32 getKeyspaceSize(NvU16 keyspace); + +NV_STATUS +confComputeKeyStoreInit_GH100(ConfidentialCompute *pConfCompute) +{ + NvU32 index; + cryptoBundle_t (*pKeyStore)[]; + + NV_PRINTF(LEVEL_INFO, "Initializing keystore.\n"); + + pConfCompute->m_keySlot = portMemAllocNonPaged((NvLength) sizeof(keySlot_t)); + + if (pConfCompute->m_keySlot == NULL) + { + return NV_ERR_NO_MEMORY; + } + + portMemSet(pConfCompute->m_keySlot, 0, (NvLength) sizeof(keySlot_t)); + + pKeyStore = pConfCompute->m_keySlot; + + // GSP key slots don't have a channel counter. + for (index = 0; index < CC_KEYSPACE_GSP_SIZE; index++) + { + (*pKeyStore)[index].type = NO_CHAN_COUNTER; + } + + // SEC2 key slots are a mix of encryption / decryption with channel counter and HMAC. + ct_assert(CC_KEYSPACE_SEC2_SIZE == 4); + + (*pKeyStore)[index++].type = CRYPT_COUNTER; + (*pKeyStore)[index++].type = HMAC_COUNTER; + (*pKeyStore)[index++].type = CRYPT_COUNTER; + (*pKeyStore)[index++].type = HMAC_COUNTER; + + // The remaining LCE key slots are all encryption / decryption with channel counter. + for (; index < CC_KEYSPACE_TOTAL_SIZE; index++) + { + (*pKeyStore)[index].type = CRYPT_COUNTER; + } + + return NV_OK; +} + +void +confComputeKeyStoreDeinit_GH100(ConfidentialCompute *pConfCompute) +{ + NV_PRINTF(LEVEL_INFO, "Deinitializing keystore.\n"); + + if (pConfCompute->m_keySlot != NULL) + { + portMemSet(pConfCompute->m_keySlot, 0, (NvLength) sizeof(keySlot_t)); + confComputeKeyStoreClearExportMasterKey_HAL(pConfCompute); + portMemFree(pConfCompute->m_keySlot); + } +} + +void +*confComputeKeyStoreGetExportMasterKey_GH100 +( + ConfidentialCompute *pConfCompute +) +{ + return pConfCompute->m_exportMasterKey; +} + +NV_STATUS +confComputeKeyStoreDeriveKey_GH100(ConfidentialCompute *pConfCompute, NvU32 globalKeyId) +{ + const NvU32 slotIndex = getKeySlotFromGlobalKeyId(globalKeyId); + cryptoBundle_t (*pKeyStore)[]; + + pKeyStore = pConfCompute->m_keySlot; + + NV_PRINTF(LEVEL_INFO, "Deriving key for global key ID %x.\n", globalKeyId); + + // SEC2 HMAC keys are not generated from the EMK but from the encryption/decryption key. + if ((globalKeyId == CC_GKEYID_GEN(CC_KEYSPACE_SEC2, CC_LKEYID_CPU_SEC2_HMAC_USER)) || + (globalKeyId == CC_GKEYID_GEN(CC_KEYSPACE_SEC2, CC_LKEYID_CPU_SEC2_HMAC_KERN))) + { + NvU32 sourceSlotIndex = 0; + + switch (CC_GKEYID_GET_LKEYID(globalKeyId)) + { + case CC_LKEYID_CPU_SEC2_HMAC_USER: + sourceSlotIndex = getKeySlotFromGlobalKeyId( + CC_GKEYID_GEN(CC_KEYSPACE_SEC2, CC_LKEYID_CPU_SEC2_DATA_USER)); + break; + case CC_LKEYID_CPU_SEC2_HMAC_KERN: + sourceSlotIndex = getKeySlotFromGlobalKeyId( + CC_GKEYID_GEN(CC_KEYSPACE_SEC2, CC_LKEYID_CPU_SEC2_DATA_KERN)); + break; + } + + if (!libspdm_sha256_hash_all((const void *)(*pKeyStore)[sourceSlotIndex].cryptBundle.key, + sizeof((*pKeyStore)[sourceSlotIndex].cryptBundle.key), + (uint8_t *)(*pKeyStore)[slotIndex].hmacBundle.key)) + { + return NV_ERR_FATAL_ERROR; + } + } + else + { + if (!libspdm_hkdf_sha256_expand(pConfCompute->m_exportMasterKey, + sizeof(pConfCompute->m_exportMasterKey), + (const uint8_t *)(CC_GKEYID_GET_STR(globalKeyId)), + (size_t)portStringLength(CC_GKEYID_GET_STR(globalKeyId)), + (uint8_t *)(*pKeyStore)[slotIndex].cryptBundle.key, + sizeof((*pKeyStore)[slotIndex].cryptBundle.key))) + { + return NV_ERR_FATAL_ERROR; + } + } + + // LCEs will return an error / interrupt if the key is all 0s. + if ((CC_GKEYID_GET_KEYSPACE(globalKeyId) >= CC_KEYSPACE_LCE0) && + (CC_GKEYID_GET_KEYSPACE(globalKeyId) <= CC_KEYSPACE_LCE7)) + { + for (NvU32 index = 0; index < CC_AES_256_GCM_KEY_SIZE_DWORD; index++) + { + if ((*pKeyStore)[slotIndex].cryptBundle.key[index] != 0) + { + return NV_OK; + } + } + + return NV_ERR_FATAL_ERROR; + } + return NV_OK; + return NV_ERR_NOT_SUPPORTED; +} + +void +confComputeKeyStoreDepositIvMask_GH100 +( + ConfidentialCompute *pConfCompute, + NvU32 globalKeyId, + void *ivMask +) +{ + NvU32 slotNumber = getKeySlotFromGlobalKeyId(globalKeyId); + cryptoBundle_t (*pKeyStore)[]; + + pKeyStore = pConfCompute->m_keySlot; + + NV_PRINTF(LEVEL_INFO, "Depositing IV mask for global key ID %x.\n", globalKeyId); + + portMemCopy((*pKeyStore)[slotNumber].cryptBundle.ivMask, + sizeof((*pKeyStore)[slotNumber].cryptBundle.ivMask), + ivMask, CC_AES_256_GCM_IV_SIZE_BYTES); +} + +void +confComputeKeyStoreClearExportMasterKey_GH100(ConfidentialCompute *pConfCompute) +{ + NV_PRINTF(LEVEL_INFO, "Clearing the Export Master Key.\n"); + + portMemSet(pConfCompute->m_exportMasterKey, 0, (NvLength) sizeof(pConfCompute->m_exportMasterKey)); +} + +NV_STATUS +confComputeKeyStoreRetrieveViaChannel_GH100 +( + ConfidentialCompute *pConfCompute, + KernelChannel *pKernelChannel, + ROTATE_IV_TYPE rotateOperation, + NvBool includeSecrets, + CC_KMB *keyMaterialBundle +) +{ + NvU32 globalKeyId; + NvU16 keyId; + + if (RM_ENGINE_TYPE_IS_COPY(kchannelGetEngineType(pKernelChannel))) + { + NvU16 keyspace; + + if (getKeyspaceLce(pKernelChannel, &keyspace) != NV_OK) + { + return NV_ERR_INVALID_PARAMETER; + } + + if (getKeyIdLce(pKernelChannel, rotateOperation, &keyId) != NV_OK) + { + return NV_ERR_INVALID_PARAMETER; + } + + globalKeyId = CC_GKEYID_GEN(keyspace, keyId); + } + else if (kchannelGetEngineType(pKernelChannel) == RM_ENGINE_TYPE_SEC2) + { + if (getKeyIdSec2(pKernelChannel, rotateOperation, &keyId) != NV_OK) + { + return NV_ERR_INVALID_PARAMETER; + } + + globalKeyId = CC_GKEYID_GEN(CC_KEYSPACE_SEC2, keyId); + } + else + { + return NV_ERR_INVALID_PARAMETER; + } + + return confComputeKeyStoreRetrieveViaKeyId_GH100(pConfCompute, globalKeyId, rotateOperation, + includeSecrets, keyMaterialBundle); +} + +NV_STATUS +confComputeKeyStoreRetrieveViaKeyId_GH100 +( + ConfidentialCompute *pConfCompute, + NvU32 globalKeyId, + ROTATE_IV_TYPE rotateOperation, + NvBool includeSecrets, + CC_KMB *keyMaterialBundle +) +{ + NvU32 slotNumber = getKeySlotFromGlobalKeyId(globalKeyId); + cryptoBundle_t (*pKeyStore)[]; + + pKeyStore = pConfCompute->m_keySlot; + + NV_PRINTF(LEVEL_INFO, "Retrieving KMB from slot number = %d and type is %d.\n", + slotNumber, (*pKeyStore)[slotNumber].type); + + if ((slotNumber % 2) == 1) + { + slotNumber--; + } + + if ((rotateOperation == ROTATE_IV_ENCRYPT) || (rotateOperation == ROTATE_IV_ALL_VALID)) + { + if (checkSlot(pConfCompute, slotNumber) != NV_OK) + { + // Right now returns error to caller. Depending on how the re-keying flow is designed + // this may initiate re-keying. + return NV_ERR_INSUFFICIENT_RESOURCES; + } + } + + if ((rotateOperation == ROTATE_IV_DECRYPT) || (rotateOperation == ROTATE_IV_ALL_VALID) || + (rotateOperation == ROTATE_IV_HMAC)) + { + if (checkSlot(pConfCompute, slotNumber + 1) != NV_OK) + { + // Right now returns error to caller. Depending on how the re-keying flow is designed + // this may initiate re-keying. + return NV_ERR_INSUFFICIENT_RESOURCES; + } + } + + if ((rotateOperation == ROTATE_IV_ENCRYPT) || (rotateOperation == ROTATE_IV_ALL_VALID)) + { + incrementChannelCounter(pConfCompute, slotNumber); + + if (includeSecrets) + { + keyMaterialBundle->encryptBundle = (*pKeyStore)[slotNumber].cryptBundle; + } + else + { + portMemCopy(keyMaterialBundle->encryptBundle.iv, sizeof(keyMaterialBundle->encryptBundle.iv), + (*pKeyStore)[slotNumber].cryptBundle.iv, CC_AES_256_GCM_IV_SIZE_BYTES); + } + } + + if ((rotateOperation == ROTATE_IV_DECRYPT) || (rotateOperation == ROTATE_IV_ALL_VALID) || + (rotateOperation == ROTATE_IV_HMAC)) + { + incrementChannelCounter(pConfCompute, slotNumber + 1); + + switch ((*pKeyStore)[slotNumber + 1].type) + { + case NO_CHAN_COUNTER: + case CRYPT_COUNTER: + if (includeSecrets) + { + keyMaterialBundle->decryptBundle = (*pKeyStore)[slotNumber + 1].cryptBundle; + } + else + { + portMemCopy(keyMaterialBundle->decryptBundle.iv, sizeof(keyMaterialBundle->decryptBundle.iv), + (*pKeyStore)[slotNumber].cryptBundle.iv, CC_AES_256_GCM_IV_SIZE_BYTES); + } + keyMaterialBundle->bIsWorkLaunch = NV_FALSE; + break; + case HMAC_COUNTER: + if (includeSecrets) + { + keyMaterialBundle->hmacBundle = (*pKeyStore)[slotNumber + 1].hmacBundle; + } + else + { + portMemCopy(keyMaterialBundle->hmacBundle.nonce, sizeof(keyMaterialBundle->hmacBundle.nonce), + (*pKeyStore)[slotNumber].hmacBundle.nonce, CC_HMAC_NONCE_SIZE_BYTES); + } + keyMaterialBundle->bIsWorkLaunch = NV_TRUE; + break; + } + } + + return NV_OK; +} + +NV_STATUS +confComputeKeyStoreUpdateKey_GH100(ConfidentialCompute *pConfCompute, NvU32 globalKeyId) +{ + return NV_ERR_NOT_SUPPORTED; +} + +// +// Return the key ID for a given LCE channel and rotation operation. +// If rotateOperation is ROTATE_IV_ALL_VALID then it will return the least +// key ID of the key pair; ie the one that corresponds to an even numbered slot. +// +static NV_STATUS +getKeyIdLce +( + KernelChannel *pKernelChannel, + ROTATE_IV_TYPE rotateOperation, + NvU16 *keyId +) +{ + if (kchannelCheckIsUserMode(pKernelChannel)) + { + if ((rotateOperation == ROTATE_IV_ENCRYPT) || (rotateOperation == ROTATE_IV_ALL_VALID)) + { + *keyId = CC_LKEYID_LCE_H2D_USER; + } + else + { + *keyId = CC_LKEYID_LCE_D2H_USER; + } + + return NV_OK; + } + else if (kchannelCheckIsKernel(pKernelChannel)) + { + if ((rotateOperation == ROTATE_IV_ENCRYPT) || (rotateOperation == ROTATE_IV_ALL_VALID)) + { + *keyId = CC_LKEYID_LCE_H2D_KERN; + } + else + { + *keyId = CC_LKEYID_LCE_D2H_KERN; + } + + return NV_OK; + } + + return NV_ERR_GENERIC; +} + +// +// Return the key ID for a given SEC2 channel and rotation operation. +// If rotateOperation is ROTATE_IV_ALL_VALID then it will return the least +// key ID of the key pair; ie the one that corresponds to an even numbered slot. +// +static NV_STATUS +getKeyIdSec2 +( + KernelChannel *pKernelChannel, + ROTATE_IV_TYPE rotateOperation, + NvU16 *keyId +) +{ + if (kchannelCheckIsUserMode(pKernelChannel)) + { + if ((rotateOperation == ROTATE_IV_ENCRYPT) || (rotateOperation == ROTATE_IV_ALL_VALID)) + { + *keyId = CC_LKEYID_CPU_SEC2_DATA_USER; + } + else + { + *keyId = CC_LKEYID_CPU_SEC2_HMAC_USER; + } + + return NV_OK; + } + else if (kchannelCheckIsKernel(pKernelChannel)) + { + if ((rotateOperation == ROTATE_IV_ENCRYPT) || (rotateOperation == ROTATE_IV_ALL_VALID)) + { + *keyId = CC_LKEYID_CPU_SEC2_DATA_KERN; + } + else + { + *keyId = CC_LKEYID_CPU_SEC2_HMAC_KERN; + } + + return NV_OK; + } + + return NV_ERR_GENERIC; +} + +static NV_STATUS +getKeyspaceLce +( + KernelChannel *pKernelChannel, + NvU16 *keyspace +) +{ + // The actual copy engine (2 through 9) is normalized to start at 0. + switch (kchannelGetEngineType(pKernelChannel)) + { + case RM_ENGINE_TYPE_COPY2: + *keyspace = CC_KEYSPACE_LCE0; + break; + case RM_ENGINE_TYPE_COPY3: + *keyspace = CC_KEYSPACE_LCE1; + break; + case RM_ENGINE_TYPE_COPY4: + *keyspace = CC_KEYSPACE_LCE2; + break; + case RM_ENGINE_TYPE_COPY5: + *keyspace = CC_KEYSPACE_LCE3; + break; + case RM_ENGINE_TYPE_COPY6: + *keyspace = CC_KEYSPACE_LCE4; + break; + case RM_ENGINE_TYPE_COPY7: + *keyspace = CC_KEYSPACE_LCE5; + break; + case RM_ENGINE_TYPE_COPY8: + *keyspace = CC_KEYSPACE_LCE6; + break; + case RM_ENGINE_TYPE_COPY9: + *keyspace = CC_KEYSPACE_LCE7; + break; + default: + return NV_ERR_GENERIC; + } + + return NV_OK; +} + +static NvU32 +getKeySlotFromGlobalKeyId +( + NvU32 globalKeyId +) +{ + NvU16 keyspace = CC_GKEYID_GET_KEYSPACE(globalKeyId); + NvU32 keySlotIndex = 0; + + for (NvU16 index = 0; index < CC_KEYSPACE_SIZE; index++) + { + if (index == keyspace) + { + break; + } + else + { + keySlotIndex += getKeyspaceSize(index); + } + } + + return keySlotIndex + CC_GKEYID_GET_LKEYID(globalKeyId); +} + +static NV_STATUS +checkSlot +( + ConfidentialCompute *pConfCompute, + NvU32 slotNumber +) +{ + if (getChannelCounter(pConfCompute, slotNumber) == NV_U64_MAX) + { + return NV_ERR_GENERIC; + } + + return NV_OK; +} + +static void +incrementChannelCounter +( + ConfidentialCompute *pConfCompute, + NvU32 slotNumber +) +{ + NvU64 channelCounter = getChannelCounter(pConfCompute, slotNumber); + cryptoBundle_t (*pKeyStore)[]; + + pKeyStore = pConfCompute->m_keySlot; + + channelCounter++; + + switch ((*pKeyStore)[slotNumber].type) + { + case NO_CHAN_COUNTER: + break; + case CRYPT_COUNTER: + (*pKeyStore)[slotNumber].cryptBundle.iv[2] = NvU64_HI32(channelCounter); + (*pKeyStore)[slotNumber].cryptBundle.iv[1] = NvU64_LO32(channelCounter); + break; + case HMAC_COUNTER: + (*pKeyStore)[slotNumber].hmacBundle.nonce[7] = NvU64_HI32(channelCounter); + (*pKeyStore)[slotNumber].hmacBundle.nonce[6] = NvU64_LO32(channelCounter); + break; + } +} + +static NvU32 +getKeyspaceSize +( + NvU16 keyspace +) +{ + switch (keyspace) + { + case CC_KEYSPACE_GSP: + return CC_KEYSPACE_GSP_SIZE; + case CC_KEYSPACE_SEC2: + return CC_KEYSPACE_SEC2_SIZE; + case CC_KEYSPACE_LCE0: + case CC_KEYSPACE_LCE1: + case CC_KEYSPACE_LCE2: + case CC_KEYSPACE_LCE3: + case CC_KEYSPACE_LCE4: + case CC_KEYSPACE_LCE5: + case CC_KEYSPACE_LCE6: + case CC_KEYSPACE_LCE7: + return CC_KEYSPACE_LCE_SIZE; + default: + NV_ASSERT_OR_RETURN(NV_FALSE, 0); + } +} + +static NvU64 +getChannelCounter +( + ConfidentialCompute *pConfCompute, + NvU32 slotNumber +) +{ + cryptoBundle_t (*pKeyStore)[]; + + pKeyStore = pConfCompute->m_keySlot; + + switch ((*pKeyStore)[slotNumber].type) + { + case NO_CHAN_COUNTER: + return 0; + case CRYPT_COUNTER: + return CONCAT64((*pKeyStore)[slotNumber].cryptBundle.iv[2], + (*pKeyStore)[slotNumber].cryptBundle.iv[1]); + case HMAC_COUNTER: + return CONCAT64((*pKeyStore)[slotNumber].hmacBundle.nonce[7], + (*pKeyStore)[slotNumber].hmacBundle.nonce[6]); + default: + NV_ASSERT_OR_RETURN(NV_FALSE, 0); + } +} diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/kernel/gpu/conf_compute/ccsl.c nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/kernel/gpu/conf_compute/ccsl.c --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/kernel/gpu/conf_compute/ccsl.c 1970-01-01 00:00:00.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/kernel/gpu/conf_compute/ccsl.c 2024-03-05 22:13:18.000000000 +0000 @@ -0,0 +1,711 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2021-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#define NVOC_CCSL_H_PRIVATE_ACCESS_ALLOWED + +#include "core/prelude.h" +#include "core/locks.h" +#include "rmconfig.h" +#include "kernel/gpu/conf_compute/ccsl.h" +#include "kernel/gpu/fifo/kernel_channel.h" +#include "nvport/nvport.h" +#include "rmapi/rmapi.h" +#include "ctrl/ctrlc56f.h" +#include +// This guard is here until we fix CONF_COMPUTE and SPDM guards across whole RM +#include "kernel/gpu/spdm/libspdm_includes.h" +#include +#include + +#include "cc_drv.h" + +static void +ccslSplit32(NvU8 *dst, NvU32 num) +{ + dst[3] = (NvU8) (num >> 24); + dst[2] = (NvU8) (num >> 16); + dst[1] = (NvU8) (num >> 8); + dst[0] = (NvU8) (num); +} + +static void +ccslSplit64(NvU8 *dst, NvU64 num) +{ + dst[7] = (NvU8) (num >> 56); + dst[6] = (NvU8) (num >> 48); + dst[5] = (NvU8) (num >> 40); + dst[4] = (NvU8) (num >> 32); + dst[3] = (NvU8) (num >> 24); + dst[2] = (NvU8) (num >> 16); + dst[1] = (NvU8) (num >> 8); + dst[0] = (NvU8) (num); +} + +static void +writeKmbToContext +( + pCcslContext pCtx, + CC_KMB *kmb +) +{ + for (NvU32 index = 0; index < CC_AES_256_GCM_KEY_SIZE_DWORD; index++) + { + ccslSplit32(pCtx->keyOut + 4 * index, kmb->encryptBundle.key[index]); + } + + for (NvU32 index = 0; index < CC_AES_256_GCM_IV_SIZE_DWORD; index++) + { + ccslSplit32(pCtx->ivOut + 4 * index, kmb->encryptBundle.iv[index]); + ccslSplit32(pCtx->ivMaskOut + 4 * index, kmb->encryptBundle.ivMask[index]); + } + + if (kmb->bIsWorkLaunch) + { + for (NvU32 index = 0; index < CC_AES_256_GCM_KEY_SIZE_DWORD; index++) + { + ccslSplit32(pCtx->keyIn + 4 * index, kmb->hmacBundle.key[index]); + } + + for (NvU32 index = 0; index < CC_HMAC_NONCE_SIZE_DWORD; index++) + { + ccslSplit32(pCtx->nonce + 4 * index, kmb->hmacBundle.nonce[index]); + } + } + else + { + for (NvU32 index = 0; index < CC_AES_256_GCM_KEY_SIZE_DWORD; index++) + { + ccslSplit32(pCtx->keyIn + 4 * index, kmb->decryptBundle.key[index]); + } + + for (NvU32 index = 0; index < CC_AES_256_GCM_IV_SIZE_DWORD; index++) + { + ccslSplit32(pCtx->ivMaskIn + 4 * index, kmb->decryptBundle.ivMask[index]); + ccslSplit32(pCtx->ivIn + 4 * index, kmb->decryptBundle.iv[index]); + } + } +} + +NV_STATUS +ccslIncrementCounter_IMPL +( + pCcslContext pCtx, + NvU8 *ctr, + NvU64 increment +) +{ + NvU32 msgCounterLo = NvU32_BUILD(ctr[3], ctr[2], ctr[1], ctr[0]); + + switch (pCtx->msgCounterSize) + { + case CSL_MSG_CTR_32: + if (increment > NV_U32_MAX) + { + return NV_ERR_INVALID_ARGUMENT; + } + + if (msgCounterLo > (NV_U32_MAX - increment)) + { + return NV_ERR_INSUFFICIENT_RESOURCES; + } + + msgCounterLo += increment; + ccslSplit32(ctr, msgCounterLo); + break; + case CSL_MSG_CTR_64: + { + NvU32 msgCounterHi = NvU32_BUILD(ctr[7], ctr[6], ctr[5], ctr[4]); + NvU64 msgCounter = ((NvU64) msgCounterHi << 32) | msgCounterLo; + + if (msgCounterLo > (NV_U64_MAX - increment)) + { + return NV_ERR_INSUFFICIENT_RESOURCES; + } + + msgCounter += increment; + ccslSplit64(ctr, msgCounter); + break; + } + } + + return NV_OK; +} + +NV_STATUS +ccslContextInitViaChannel_IMPL +( + pCcslContext *ppCtx, + NvHandle hClient, + NvHandle hChannel +) +{ + CC_KMB *kmb; + + OBJSYS *pSys = SYS_GET_INSTANCE(); + OBJGPUMGR *pGpuMgr = SYS_GET_GPUMGR(pSys); + OBJGPU *pGpu; + NvU32 gpuMask; + NvU32 gpuInstance = 0; + RM_API *pRmApi = NULL; + NV_STATUS status; + + NVC56F_CTRL_CMD_GET_KMB_PARAMS getKmbParams; + + NV_PRINTF(LEVEL_INFO, "Initializing CCSL context via channel.\n"); + + // This function must be redesigned for multi-gpu + if(!pGpuMgr->ccCaps.bHccFeatureCapable) + { + return NV_ERR_NOT_SUPPORTED; + } + + if (ppCtx == NULL) + { + return NV_ERR_INVALID_PARAMETER; + } + + pCcslContext pCtx = portMemAllocNonPaged(sizeof(*pCtx)); + if (pCtx == NULL) + { + return NV_ERR_NO_MEMORY; + } + *ppCtx = pCtx; + + if (!libspdm_aead_gcm_prealloc(&pCtx->openrmCtx)) + { + portMemFree(pCtx); + return NV_ERR_NO_MEMORY; + } + + pCtx->hClient = hClient; + pCtx->hChannel = hChannel; + + (void)gpumgrGetGpuAttachInfo(NULL, &gpuMask); + + while ((pGpu = gpumgrGetNextGpu(gpuMask, &gpuInstance)) != NULL) + { + if (IS_GSP_CLIENT(pGpu)) + { + if (rmGpuLockIsOwner()) + { + pRmApi = rmapiGetInterface(RMAPI_GPU_LOCK_INTERNAL); + } + else + { + pRmApi = rmapiGetInterface(RMAPI_EXTERNAL_KERNEL); + } + } + else + { + pRmApi = GPU_GET_PHYSICAL_RMAPI(pGpu); + } + portMemSet(&getKmbParams, 0, sizeof(getKmbParams)); + + status = pRmApi->Control(pRmApi, hClient, hChannel, + NVC56F_CTRL_CMD_GET_KMB, &getKmbParams, + sizeof(getKmbParams)); + if (status != NV_OK) + { + libspdm_aead_free(pCtx->openrmCtx); + portMemFree(pCtx); + return status; + } + + pCtx->msgCounterSize = CSL_MSG_CTR_32; + + kmb = &getKmbParams.kmb; + + writeKmbToContext(pCtx, kmb); + } + + return NV_OK; +} + +NV_STATUS +ccslContextInitViaKeyId_KERNEL +( + ConfidentialCompute *pConfCompute, + pCcslContext *ppCtx, + NvU32 globalKeyId +) +{ + NV_STATUS status; + CC_KMB kmb; + OBJSYS *pSys = SYS_GET_INSTANCE(); + OBJGPUMGR *pGpuMgr = SYS_GET_GPUMGR(pSys); + + NV_PRINTF(LEVEL_INFO, "Initializing CCSL context via globak key ID.\n"); + + // This function must be redesigned for multi-gpu + if(!pGpuMgr->ccCaps.bHccFeatureCapable) + { + return NV_ERR_NOT_SUPPORTED; + } + + if (ppCtx == NULL) + { + return NV_ERR_INVALID_PARAMETER; + } + + pCcslContext pCtx = portMemAllocNonPaged(sizeof(*pCtx)); + if (pCtx == NULL) + { + return NV_ERR_NO_MEMORY; + } + *ppCtx = pCtx; + if (!libspdm_aead_gcm_prealloc(&pCtx->openrmCtx)) + { + portMemFree(pCtx); + return NV_ERR_NO_MEMORY; + } + + status = confComputeKeyStoreRetrieveViaKeyId_HAL(pConfCompute, + globalKeyId, + ROTATE_IV_ALL_VALID, + NV_TRUE, + &kmb); + if (status != NV_OK) + { + libspdm_aead_free(pCtx->openrmCtx); + portMemFree(pCtx); + return status; + } + + // For now assume any call to this function uses a 64-bit message counter. + pCtx->msgCounterSize = CSL_MSG_CTR_64; + writeKmbToContext(pCtx, &kmb); + + return NV_OK; +} + +void +ccslContextClear_IMPL +( + pCcslContext pCtx +) +{ + NV_PRINTF(LEVEL_INFO, "Clearing the CCSL context.\n"); + + if (pCtx == NULL) + { + return; + } + + libspdm_aead_free(pCtx->openrmCtx); + portMemFree(pCtx); +} + +NV_STATUS +ccslRotateIv_IMPL +( + pCcslContext pCtx, + NvU8 direction +) +{ + OBJGPU *pGpu; + NvU32 gpuMask; + NvU32 gpuInstance = 0; + RM_API *pRmApi = NULL; + + NVC56F_CTRL_ROTATE_SECURE_CHANNEL_IV_PARAMS rotateIvParams; + + if ((direction != CCSL_DIR_HOST_TO_DEVICE) && (direction != CCSL_DIR_DEVICE_TO_HOST)) + { + return NV_ERR_INVALID_ARGUMENT; + } + + portMemSet(&rotateIvParams, 0, sizeof(rotateIvParams)); + + if (direction == CCSL_DIR_HOST_TO_DEVICE) + { + rotateIvParams.rotateIvType = ROTATE_IV_ENCRYPT; + } + else + { + rotateIvParams.rotateIvType = ROTATE_IV_DECRYPT; + } + + (void)gpumgrGetGpuAttachInfo(NULL, &gpuMask); + while ((pGpu = gpumgrGetNextGpu(gpuMask, &gpuInstance)) != NULL) + { + if (IS_GSP_CLIENT(pGpu)) + { + pRmApi = rmapiGetInterface(RMAPI_EXTERNAL_KERNEL); + } + else + { + pRmApi = GPU_GET_PHYSICAL_RMAPI(pGpu); + } + NV_ASSERT_OK_OR_RETURN(pRmApi->Control(pRmApi, + pCtx->hClient, + pCtx->hChannel, + NVC56F_CTRL_ROTATE_SECURE_CHANNEL_IV, + &rotateIvParams, + sizeof(rotateIvParams))); + } + + switch (direction) + { + case CCSL_DIR_HOST_TO_DEVICE: + portMemCopy(pCtx->keyOut, sizeof(pCtx->keyOut), + &rotateIvParams.updatedKmb.encryptBundle.key, + sizeof(rotateIvParams.updatedKmb.encryptBundle.key)); + portMemCopy(pCtx->ivMaskOut, sizeof(pCtx->ivMaskOut), + &rotateIvParams.updatedKmb.encryptBundle.ivMask, + sizeof(rotateIvParams.updatedKmb.encryptBundle.ivMask)); + portMemCopy(pCtx->ivOut, sizeof(pCtx->ivOut), + &rotateIvParams.updatedKmb.encryptBundle.iv, + sizeof(rotateIvParams.updatedKmb.encryptBundle.iv)); + break; + + case CCSL_DIR_DEVICE_TO_HOST: + portMemCopy(pCtx->keyIn, sizeof(pCtx->keyIn), + &rotateIvParams.updatedKmb.decryptBundle.key, + sizeof(rotateIvParams.updatedKmb.decryptBundle.key)); + portMemCopy(pCtx->ivMaskIn, sizeof(pCtx->ivMaskIn), + &rotateIvParams.updatedKmb.decryptBundle.ivMask, + sizeof(rotateIvParams.updatedKmb.decryptBundle.ivMask)); + portMemCopy(pCtx->ivIn, sizeof(pCtx->ivIn), + &rotateIvParams.updatedKmb.decryptBundle.iv, + sizeof(rotateIvParams.updatedKmb.decryptBundle.iv)); + break; + } + + return NV_OK; +} + +NV_STATUS +ccslEncryptWithIv_IMPL +( + pCcslContext pCtx, + NvU32 bufferSize, + NvU8 const *inputBuffer, + NvU8 *encryptIv, + NvU8 const *aadBuffer, + NvU32 aadSize, + NvU8 *outputBuffer, + NvU8 *authTagBuffer +) +{ + NvU8 iv[CC_AES_256_GCM_IV_SIZE_BYTES] = {0}; + size_t outputBufferSize = bufferSize; + + // The "freshness" bit is right after the IV + if (encryptIv[CC_AES_256_GCM_IV_SIZE_BYTES] != 1) + { + return NV_ERR_INVALID_ARGUMENT; + } + + encryptIv[CC_AES_256_GCM_IV_SIZE_BYTES] = 0; + + for (NvU64 i = 0; i < CC_AES_256_GCM_IV_SIZE_BYTES; i++) + { + iv[i] = encryptIv[i] ^ pCtx->ivMaskOut[i]; + } + + if(!libspdm_aead_aes_gcm_encrypt_prealloc(pCtx->openrmCtx, + (NvU8 *)pCtx->keyOut, CC_AES_256_GCM_KEY_SIZE_BYTES, + iv, CC_AES_256_GCM_IV_SIZE_BYTES, aadBuffer, aadSize, + inputBuffer, bufferSize, authTagBuffer, 16, + outputBuffer, &outputBufferSize)) + { + return NV_ERR_GENERIC; + } + + return NV_OK; +} + +NV_STATUS +ccslEncrypt_KERNEL +( + pCcslContext pCtx, + NvU32 bufferSize, + NvU8 const *inputBuffer, + NvU8 const *aadBuffer, + NvU32 aadSize, + NvU8 *outputBuffer, + NvU8 *authTagBuffer +) +{ + NvU8 iv[CC_AES_256_GCM_IV_SIZE_BYTES] = {0}; + size_t outputBufferSize = bufferSize; + + if (ccslIncrementCounter(pCtx, pCtx->ivOut, 1) != NV_OK) + { + return NV_ERR_INSUFFICIENT_RESOURCES; + } + + for (NvU64 i = 0; i < CC_AES_256_GCM_IV_SIZE_BYTES; i++) + { + iv[i] = pCtx->ivOut[i] ^ pCtx->ivMaskOut[i]; + } + + if(!libspdm_aead_aes_gcm_encrypt_prealloc(pCtx->openrmCtx, + (NvU8 *)pCtx->keyOut, CC_AES_256_GCM_KEY_SIZE_BYTES, + iv, CC_AES_256_GCM_IV_SIZE_BYTES, aadBuffer, aadSize, + inputBuffer, bufferSize, authTagBuffer, 16, + outputBuffer, &outputBufferSize)) + { + return NV_ERR_GENERIC; + } + + return NV_OK; +} + +NV_STATUS +ccslDecrypt_KERNEL +( + pCcslContext pCtx, + NvU32 bufferSize, + NvU8 const *inputBuffer, + NvU8 const *decryptIv, + NvU8 const *aadBuffer, + NvU32 aadSize, + NvU8 *outputBuffer, + NvU8 const *authTagBuffer +) +{ + NvU8 iv[CC_AES_256_GCM_IV_SIZE_BYTES] = {0}; + size_t outputBufferSize = bufferSize; + + if ((bufferSize == 0) || ((aadBuffer != NULL) && (aadSize == 0))) + { + return NV_ERR_INVALID_ARGUMENT; + } + + if (decryptIv == NULL) + { + if (ccslIncrementCounter(pCtx, pCtx->ivIn, 1) != NV_OK) + { + return NV_ERR_INSUFFICIENT_RESOURCES; + } + + for (NvU64 i = 0; i < CC_AES_256_GCM_IV_SIZE_BYTES; i++) + { + iv[i] = pCtx->ivIn[i] ^ pCtx->ivMaskIn[i]; + } + } + else + { + for (NvU64 i = 0; i < CC_AES_256_GCM_IV_SIZE_BYTES; i++) + { + iv[i] = decryptIv[i] ^ pCtx->ivMaskIn[i]; + } + } + + if(!libspdm_aead_aes_gcm_decrypt_prealloc(pCtx->openrmCtx, + (NvU8 *)pCtx->keyIn, CC_AES_256_GCM_KEY_SIZE_BYTES, + iv, CC_AES_256_GCM_IV_SIZE_BYTES, aadBuffer, aadSize, + inputBuffer, bufferSize, (NvU8 *) authTagBuffer, 16, + outputBuffer, &outputBufferSize)) + { + return NV_ERR_INVALID_DATA; + } + + return NV_OK; +} + +static NV_STATUS ccslIncrementCounter192(NvU8 *ctr) +{ + NvU8 carry = 1; + NvU64 i; + NvBool overflow = NV_TRUE; + + for (i = 0; i < 192 / 8; ++i) + { + if (ctr[i] != 0xFF) + { + overflow = NV_FALSE; + break; + } + } + if (overflow) + { + return NV_ERR_INSUFFICIENT_RESOURCES; + } + + for (i = 0; i < 192 / 8; ++i) + { + ctr[i] += carry; + carry = (ctr[i] == 0) && (carry == 1); + } + + return NV_OK; +} + +NV_STATUS +ccslSign_IMPL +( + pCcslContext pCtx, + NvU32 bufferSize, + NvU8 const *inputBuffer, + NvU8 *authTagBuffer +) +{ + void *hmac_ctx; + + if (bufferSize == 0) + { + return NV_ERR_INVALID_PARAMETER; + } + + if (ccslIncrementCounter192(pCtx->nonce) != NV_OK) + { + return NV_ERR_INSUFFICIENT_RESOURCES; + } + + hmac_ctx = libspdm_hmac_sha256_new(); + if (hmac_ctx == NULL) + { + return NV_ERR_GENERIC; + } + + if (!libspdm_hmac_sha256_set_key(hmac_ctx, pCtx->keyIn, CC_AES_256_GCM_KEY_SIZE_BYTES)) + { + libspdm_hmac_sha256_free(hmac_ctx); + return NV_ERR_GENERIC; + } + + if (!libspdm_hmac_sha256_update(hmac_ctx, inputBuffer, bufferSize)) + { + libspdm_hmac_sha256_free(hmac_ctx); + return NV_ERR_GENERIC; + } + + if (!libspdm_hmac_sha256_update(hmac_ctx, pCtx->nonce, CC_HMAC_NONCE_SIZE_BYTES)) + { + libspdm_hmac_sha256_free(hmac_ctx); + return NV_ERR_GENERIC; + } + + if (!libspdm_hmac_sha256_final(hmac_ctx, authTagBuffer)) + { + libspdm_hmac_sha256_free(hmac_ctx); + return NV_ERR_GENERIC; + } + + libspdm_hmac_sha256_free(hmac_ctx); + + return NV_OK; +} + +static NvU64 +getMessageCounterAndLimit +( + pCcslContext pCtx, + NvU8 *iv, + NvU64 *limit +) +{ + NvU32 msgCounterLo = NvU32_BUILD(iv[3], iv[2], iv[1], iv[0]); + NvU32 msgCounterHi = NvU32_BUILD(iv[7], iv[6], iv[5], iv[4]); + + switch (pCtx->msgCounterSize) + { + case CSL_MSG_CTR_32: + *limit = NV_U32_MAX; + return msgCounterLo; + case CSL_MSG_CTR_64: + *limit = NV_U64_MAX; + return ((((NvU64) msgCounterHi) << 32) | msgCounterLo); + default: + return 0; + } +} + +NV_STATUS +ccslQueryMessagePool_IMPL +( + pCcslContext pCtx, + NvU8 direction, + NvU64 *messageNum +) +{ + NvU64 limit; + NvU64 messageCounter; + + switch (direction) + { + case CCSL_DIR_HOST_TO_DEVICE: + messageCounter = getMessageCounterAndLimit(pCtx, pCtx->ivOut, &limit); + break; + case CCSL_DIR_DEVICE_TO_HOST: + messageCounter = getMessageCounterAndLimit(pCtx, pCtx->ivIn, &limit); + break; + default: + return NV_ERR_INVALID_ARGUMENT; + } + + *messageNum = limit - messageCounter; + + return NV_OK; +} + +NV_STATUS +ccslIncrementIv_IMPL +( + pCcslContext pCtx, + NvU8 direction, + NvU64 increment, + NvU8 *iv +) +{ + NV_STATUS status; + void *ivPtr; + + switch (direction) + { + case CCSL_DIR_HOST_TO_DEVICE: + ivPtr = pCtx->ivOut; + break; + case CCSL_DIR_DEVICE_TO_HOST: + ivPtr = pCtx->ivIn; + break; + default: + return NV_ERR_INVALID_ARGUMENT; + } + + status = ccslIncrementCounter(pCtx, ivPtr, increment); + + if (status != NV_OK) + { + return status; + } + + if (iv != NULL) { + portMemCopy(iv, CC_AES_256_GCM_IV_SIZE_BYTES, ivPtr, CC_AES_256_GCM_IV_SIZE_BYTES); + + if (direction == CCSL_DIR_HOST_TO_DEVICE) + { + // The "freshness" bit is right after the IV. + iv[CC_AES_256_GCM_IV_SIZE_BYTES] = 1; + } + else + { + // Decrypt IV cannot be used for encryption. + iv[CC_AES_256_GCM_IV_SIZE_BYTES] = 0; + } + } + + return NV_OK; +} diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/kernel/gpu/conf_compute/conf_compute.c nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/kernel/gpu/conf_compute/conf_compute.c --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/kernel/gpu/conf_compute/conf_compute.c 1970-01-01 00:00:00.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/kernel/gpu/conf_compute/conf_compute.c 2024-03-05 22:13:18.000000000 +0000 @@ -0,0 +1,614 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2021-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +/***************************************************************************\ + * * + * Confidential Compute Object Module * + * * + \**************************************************************************/ + +#define NVOC_CONF_COMPUTE_H_PRIVATE_ACCESS_ALLOWED + +#include "nvrm_registry.h" +#include "gpu/conf_compute/conf_compute.h" +#include "gpu/conf_compute/conf_compute_keystore.h" +#include "spdm/rmspdmvendordef.h" +#include "gsp/gsp_proxy_reg.h" +#include "gpu_mgr/gpu_mgr.h" +#include "gpu/gpu.h" +#include "ctrl/ctrl2080/ctrl2080internal.h" +#include "ctrl/ctrl2080/ctrl2080spdm.h" +#include "kernel/gpu/conf_compute/ccsl.h" + +/*! + * Local object related functions + */ +static void _confComputeInitRegistryOverrides(OBJGPU *, ConfidentialCompute*); + + +NV_STATUS +confComputeConstructEngine_IMPL(OBJGPU *pGpu, + ConfidentialCompute *pConfCompute, + ENGDESCRIPTOR engDesc) +{ + OBJSYS *pSys = SYS_GET_INSTANCE(); + NvU32 data = 0; + NvBool bForceEnableCC = 0; + pConfCompute->pSpdm = NULL; + portMemSet(&pConfCompute->ccStaticInfo, 0, sizeof(pConfCompute->ccStaticInfo)); + pConfCompute->gspProxyRegkeys = 0; + + pConfCompute->pRpcCcslCtx = NULL; + pConfCompute->pDmaCcslCtx = NULL; + pConfCompute->pReplayableFaultCcslCtx = NULL; + pConfCompute->pNonReplayableFaultCcslCtx = NULL; + + if (gpuIsCCEnabledInHw_HAL(pGpu)) + { + pConfCompute->setProperty(pConfCompute, PDB_PROP_CONFCOMPUTE_ENABLED, NV_TRUE); + } + + if (gpuIsDevModeEnabledInHw_HAL(pGpu)) + { + pConfCompute->setProperty(pConfCompute, PDB_PROP_CONFCOMPUTE_DEVTOOLS_MODE_ENABLED, NV_TRUE); + } + + _confComputeInitRegistryOverrides(pGpu, pConfCompute); + + if (pConfCompute->getProperty(pConfCompute, PDB_PROP_CONFCOMPUTE_ENABLED)) + { + bForceEnableCC = (osReadRegistryDword(pGpu, NV_REG_STR_RM_CONFIDENTIAL_COMPUTE, &data) == NV_OK) && + FLD_TEST_DRF(_REG_STR, _RM_CONFIDENTIAL_COMPUTE, _ENABLED, _YES, data); + + if (!RMCFG_FEATURE_PLATFORM_GSP && !RMCFG_FEATURE_PLATFORM_MODS && !bForceEnableCC) + { + if (!(sysGetStaticConfig(pSys)->bOsCCEnabled)) + { + NV_PRINTF(LEVEL_ERROR, "CPU does not support confidential compute.\n"); + NV_ASSERT(0); + pConfCompute->setProperty(pConfCompute, PDB_PROP_CONFCOMPUTE_ENABLED, NV_FALSE); + return NV_ERR_INVALID_OPERATION; + } + } + + NV_CHECK_OR_RETURN(LEVEL_ERROR, confComputeIsGpuCcCapable_HAL(pGpu, pConfCompute), NV_ERR_INVALID_OPERATION); + + if (pGpu->getProperty(pGpu, PDB_PROP_GPU_APM_FEATURE_CAPABLE)) + { + pConfCompute->setProperty(pConfCompute, PDB_PROP_CONFCOMPUTE_APM_FEATURE_ENABLED, NV_TRUE); + + // Forcing DEV_MODE to False for APM + NV_PRINTF(LEVEL_INFO, "Confidential Compute devtools mode DISABLED in APM.\n"); + pConfCompute->setProperty(pConfCompute, PDB_PROP_CONFCOMPUTE_DEVTOOLS_MODE_ENABLED, NV_FALSE); + pConfCompute->gspProxyRegkeys |= DRF_DEF(GSP, _PROXY_REG, _CONF_COMPUTE_DEV_MODE, _DISABLE); + } + else if (pGpu->getProperty(pGpu, PDB_PROP_GPU_CC_FEATURE_CAPABLE)) + { + pConfCompute->setProperty(pConfCompute, PDB_PROP_CONFCOMPUTE_CC_FEATURE_ENABLED, NV_TRUE); + pGpu->setProperty(pGpu, PDB_PROP_GPU_FASTPATH_SEQ_ENABLED, NV_TRUE); + } + else + { + NV_PRINTF(LEVEL_ERROR, "GPU does not support confidential compute.\n"); + NV_ASSERT(0); + return NV_ERR_INVALID_OPERATION; + } + } + + return NV_OK; +} + +/*! + * Initialize all registry overrides for this object + * + * @param[in] pGpu GPU object pointer + * @param[in] pConfCompute ConfidentialCompute pointer + */ +static void +_confComputeInitRegistryOverrides +( + OBJGPU *pGpu, + ConfidentialCompute *pConfCompute +) +{ + NvU32 data = 0; + + if ((osReadRegistryDword(pGpu, NV_REG_STR_RM_CONFIDENTIAL_COMPUTE, &data) == NV_OK) && + FLD_TEST_DRF(_REG_STR, _RM_CONFIDENTIAL_COMPUTE, _ENABLED, _YES, data)) + { + NV_PRINTF(LEVEL_INFO, "Confidential Compute enabled via regkey override.\n"); + pConfCompute->setProperty(pConfCompute, PDB_PROP_CONFCOMPUTE_ENABLED, NV_TRUE); + pConfCompute->gspProxyRegkeys |= DRF_DEF(GSP, _PROXY_REG, _CONFIDENTIAL_COMPUTE, _ENABLE); + + if (FLD_TEST_DRF(_REG_STR, _RM_CONFIDENTIAL_COMPUTE, _GPUS_READY_CHECK, _DISABLED, data)) + { + pConfCompute->setProperty(pConfCompute, PDB_PROP_CONFCOMPUTE_GPUS_READY_CHECK_ENABLED, NV_FALSE); + } + + if ((osReadRegistryDword(pGpu, NV_REG_STR_RM_CONF_COMPUTE_EARLY_INIT, &data) + == NV_OK) && (data == NV_REG_STR_RM_CONF_COMPUTE_EARLY_INIT_ENABLED)) + { + NV_PRINTF(LEVEL_INFO, "Confidential Compute early init enabled via regkey override.\n"); + pConfCompute->setProperty(pConfCompute, PDB_PROP_CONFCOMPUTE_ENABLE_EARLY_INIT, NV_TRUE); + pConfCompute->gspProxyRegkeys |= DRF_DEF(GSP, _PROXY_REG, _CONF_COMPUTE_EARLY_INIT, _ENABLE); + } + + if (FLD_TEST_DRF(_REG_STR, _RM_CONFIDENTIAL_COMPUTE, _DEV_MODE_ENABLED, _YES, data)) + { + NV_PRINTF(LEVEL_INFO, "Confidential Compute dev mode enabled via regkey override.\n"); + pConfCompute->setProperty(pConfCompute, PDB_PROP_CONFCOMPUTE_DEVTOOLS_MODE_ENABLED, NV_TRUE); + pConfCompute->gspProxyRegkeys |= DRF_DEF(GSP, _PROXY_REG, _CONF_COMPUTE_DEV_MODE, _ENABLE); + } + } + + if (pConfCompute->getProperty(pConfCompute, PDB_PROP_CONFCOMPUTE_ENABLED)) + { + if (confComputeIsSpdmEnabled(pGpu, pConfCompute)) + { + NV_PRINTF(LEVEL_INFO, "SPDM is enabled by default.\n"); + pConfCompute->setProperty(pConfCompute, PDB_PROP_CONFCOMPUTE_SPDM_ENABLED, NV_TRUE); + } + + // Allow override of whatever default settings are. + if (osReadRegistryDword(pGpu, NV_REG_STR_RM_CONF_COMPUTE_SPDM_POLICY, &data) == NV_OK) + { + if (FLD_TEST_DRF(_REG_STR, _RM_CONF_COMPUTE_SPDM_POLICY, _ENABLED, _YES, data)) + { + NV_PRINTF(LEVEL_INFO, "Confidential Compute SPDM enabled via regkey override.\n"); + pConfCompute->setProperty(pConfCompute, PDB_PROP_CONFCOMPUTE_SPDM_ENABLED, NV_TRUE); + } + else if (FLD_TEST_DRF(_REG_STR, _RM_CONF_COMPUTE_SPDM_POLICY, _ENABLED, _NO, data)) + { + // OPENRM-TODO: Always enable SPDM for debug. + NV_PRINTF(LEVEL_INFO, "Confidential Compute SPDM disabled via regkey override.\n"); + pConfCompute->setProperty(pConfCompute, PDB_PROP_CONFCOMPUTE_SPDM_ENABLED, NV_FALSE); + } + } + } + + if (pConfCompute->getProperty(pConfCompute, PDB_PROP_CONFCOMPUTE_ENABLED)) + { + if (osReadRegistryDword(pGpu, NV_REG_STR_RM_GSP_OWNED_FAULT_BUFFERS_ENABLE, &data) == NV_OK) + { + pGpu->bIsGspOwnedFaultBuffersEnabled = data; + } + else + { + if (IS_GSP_CLIENT(pGpu) || RMCFG_FEATURE_PLATFORM_GSP) + { + pGpu->bIsGspOwnedFaultBuffersEnabled = NV_REG_STR_RM_GSP_OWNED_FAULT_BUFFERS_ENABLE_YES; + } + else + { + pGpu->bIsGspOwnedFaultBuffersEnabled = NV_REG_STR_RM_GSP_OWNED_FAULT_BUFFERS_ENABLE_NO; + } + } + } +} + +/*! + * Establish the SPDM session with the GPU Responder. + * After establishing the session, initialize all keys required + * for the Confidential Compute session. + * + * Note: This assumes that Confidential Compute is the first object + * to be initialized in the GPU child order list, and therefore + * SPDM session establishment is the first thing to happen. If another + * object precedes Confidential Compute - it will be initialized before + * SPDM session establishment. + * + * @param[in] pGpu GPU object pointer + * @param[in] pConfCompute ConfidentialCompute pointer + */ +NV_STATUS +confComputeEstablishSpdmSessionAndKeys_KERNEL +( + OBJGPU *pGpu, + ConfidentialCompute *pConfCompute +) +{ + NV_STATUS status = NV_OK; + + if (IS_FMODEL(pGpu)) + { + // Skip SPDM support on fmodel due to bugs 3553627 and 3556621. + return NV_OK; + } + + // + // Initialize SPDM session between Guest RM and SPDM Responder on GPU. + // The session lifetime will track Confidential Compute object state lifetime. + // + if (pConfCompute->getProperty(pConfCompute, PDB_PROP_CONFCOMPUTE_SPDM_ENABLED)) + { + status = objCreate(&pConfCompute->pSpdm, pConfCompute, Spdm); + if (status != NV_OK) + { + return status; + } + + NV_ASSERT(pConfCompute->pSpdm); + + // Initialize SPDM context & begin session. + NV_CHECK_OK_OR_GOTO(status, LEVEL_ERROR, + spdmContextInit(pGpu, pConfCompute->pSpdm), + ErrorExit); + NV_CHECK_OK_OR_GOTO(status, LEVEL_ERROR, + spdmStart(pGpu, pConfCompute->pSpdm), + ErrorExit); + + // + // Now that SPDM session is established, we must initialize + // keystore for any session-derived keys. + // + NV_CHECK_OK_OR_GOTO(status, LEVEL_ERROR, + confComputeKeyStoreInit_HAL(pConfCompute), + ErrorExit); + + // Store the export master secret in the keystore. + NV_CHECK_OK_OR_GOTO(status, LEVEL_ERROR, + spdmRetrieveExportSecret(pGpu, pConfCompute->pSpdm, + CC_EXPORT_MASTER_KEY_SIZE_BYTES, + confComputeKeyStoreGetExportMasterKey(pConfCompute)), + ErrorExit); + + // Derive secrets for encrypted communication + NV_CHECK_OK_OR_GOTO(status, LEVEL_ERROR, + confComputeDeriveSecrets_HAL(pConfCompute, MC_ENGINE_IDX_GSP), + ErrorExit); + + // Enable encryption for all traffic between CPU and GPU + status = confComputeStartEncryption_HAL(pGpu, pConfCompute); + if (status != NV_OK) + { + NV_PRINTF(LEVEL_ERROR, "ConfCompute : Failed enabling encryption!"); + return status; + } + } +ErrorExit: + + return status; +} + +/*! + * Deinitialize the SPDM context with the GPU Responder. + * + * Note: This assumes that Confidential Compute is the first object + * to be initialized in the GPU child order list, and therefore + * SPDM deinitialization is the last thing to happen. If another + * object precedes Confidential Compute - it will be deinitialized + * before SPDM. + * + * @param[in] pGpu GPU object pointer + * @param[in] pConfCompute ConfidentialCompute pointer + */ +static NV_STATUS +_confComputeDeinitSpdmSession +( + OBJGPU *pGpu, + ConfidentialCompute *pConfCompute +) +{ + NV_STATUS status = NV_OK; + + if (IS_FMODEL(pGpu)) + { + // Skip SPDM support on fmodel due to bugs 3553627 and 3556621. + return NV_OK; + } + + // + // Tear down SPDM session between Guest RM and SPDM Responder on GPU. + // We must do in pre-unload, before Responder is torn down entirely. + // + if (pConfCompute->getProperty(pConfCompute, PDB_PROP_CONFCOMPUTE_SPDM_ENABLED)) + { + if (pConfCompute->pSpdm == NULL) + { + // + // If SPDM object doesn't exist, we must have failed earlier. + // Alert in logs and move on. + // + NV_PRINTF(LEVEL_ERROR, "SPDM teardown did not occur, as SPDM object is null!\n"); + return NV_OK; + } + + status = spdmContextDeinit(pGpu, pConfCompute->pSpdm, NV_TRUE); + + objDelete(pConfCompute->pSpdm); + pConfCompute->pSpdm = NULL; + } + + return status; +} + + +/*! + * Perform any work that must be done before GPU initialization. + * + * @param[in] pGpu GPU object pointer + * @param[in] pConfCompute ConfidentialCompute pointer + */ +NV_STATUS +confComputeStatePreInitLocked_IMPL +( + OBJGPU *pGpu, + ConfidentialCompute *pConfCompute +) +{ + return confComputeEstablishSpdmSessionAndKeys_HAL(pGpu, pConfCompute); +} + +/*! + * Perform any init that must occur after GPU state load. + * + * @param[in] pGpu GPU object pointer + * @param[in] pConfCompute ConfidentialCompute pointer + * @param[in] flags Optional flags describing state load conditions + */ +NV_STATUS +confComputeStatePostLoad_IMPL +( + OBJGPU *pGpu, + ConfidentialCompute *pConfCompute, + NvU32 flags +) +{ + NV_STATUS status = NV_OK; + RM_API *pRmApi = GPU_GET_PHYSICAL_RMAPI(pGpu); + + NV_ASSERT_OK_OR_RETURN(pRmApi->Control(pRmApi, + pGpu->hInternalClient, + pGpu->hInternalSubdevice, + NV2080_CTRL_CMD_INTERNAL_CONF_COMPUTE_GET_STATIC_INFO, + &pConfCompute->ccStaticInfo, + sizeof(pConfCompute->ccStaticInfo))); + + if (!IS_GSP_CLIENT(pGpu) && !RMCFG_FEATURE_PLATFORM_GSP) + { + NV_PRINTF(LEVEL_INFO, "Performing late SPDM initialization!\n"); + status = confComputeEstablishSpdmSessionAndKeys_HAL(pGpu, pConfCompute); + } + + return status; +} + +/*! + * Perform any deinit that must occur before GPU state unload. + * + * @param[in] pGpu GPU object pointer + * @param[in] pConfCompute ConfidentialCompute pointer + * @param[in] flags Optional flags describing state unload conditions + */ +NV_STATUS +confComputeStatePreUnload_IMPL +( + OBJGPU *pGpu, + ConfidentialCompute *pConfCompute, + NvU32 flags +) +{ + NV_PRINTF(LEVEL_INFO, "Performing SPDM deinitialization in Pre Unload!\n"); + return _confComputeDeinitSpdmSession(pGpu, pConfCompute); +} + +NvBool +confComputeAcceptClientRequest_IMPL +( + OBJGPU *pGpu, + ConfidentialCompute *pConfCompute +) +{ + OBJSYS *pSys = SYS_GET_INSTANCE(); + OBJGPUMGR *pGpuMgr = SYS_GET_GPUMGR(pSys); + + if (pConfCompute->getProperty(pConfCompute, PDB_PROP_CONFCOMPUTE_GPUS_READY_CHECK_ENABLED)) + { + return pGpuMgr->ccCaps.bAcceptClientRequest; + } + else + { + return NV_TRUE; + } +} + +NV_STATUS +confComputeStateInitLocked_IMPL +( + OBJGPU *pGpu, + ConfidentialCompute *pConfCompute +) +{ + RM_API *pRmApi = IS_GSP_CLIENT(pGpu) ? GPU_GET_PHYSICAL_RMAPI(pGpu) : + rmapiGetInterface(RMAPI_GPU_LOCK_INTERNAL); + + NV_ASSERT_OK_OR_RETURN(pRmApi->Control(pRmApi, + pGpu->hInternalClient, + pGpu->hInternalSubdevice, + NV2080_CTRL_CMD_INTERNAL_CONF_COMPUTE_GET_STATIC_INFO, + &pConfCompute->ccStaticInfo, + sizeof(pConfCompute->ccStaticInfo))); + + NV_PRINTF(LEVEL_INFO, "BAR1 Trusted: 0x%x PCIE Trusted: 0x%x\n", + pConfCompute->ccStaticInfo.bIsBar1Trusted, pConfCompute->ccStaticInfo.bIsPcieTrusted); + + return NV_OK; +} + +NV_STATUS +confComputeStartEncryption_KERNEL +( + OBJGPU *pGpu, + ConfidentialCompute *pConfCompute +) +{ + NV_STATUS status = NV_OK; + RM_API *pRmApi = GPU_GET_PHYSICAL_RMAPI(pGpu); + NV2080_CTRL_CMD_INTERNAL_CONF_COMPUTE_ENCRYPTION_CONTROL_PARAMS params; + + if (!IS_GSP_CLIENT(pGpu)) + { + return NV_ERR_INVALID_STATE; + } + + if ((pConfCompute->getProperty(pConfCompute, PDB_PROP_CONFCOMPUTE_ENCRYPT_READY) == NV_FALSE) && + (pConfCompute->getProperty(pConfCompute, PDB_PROP_CONFCOMPUTE_ENCRYPT_ENABLED) == NV_FALSE)) + { + NV_PRINTF(LEVEL_INFO, "ConfCompute: Enabling encryption on Kernel-RM!\n"); + + pConfCompute->setProperty(pConfCompute, PDB_PROP_CONFCOMPUTE_ENCRYPT_READY, NV_TRUE); + pConfCompute->setProperty(pConfCompute, PDB_PROP_CONFCOMPUTE_ENCRYPT_ENABLED, NV_TRUE); + + // + // GSP-RM has already initialized all its secrets successfully. + // We must initialize our own before we attempt to start encryption. + // + NV_ASSERT_OK_OR_RETURN(ccslContextInitViaKeyId(pConfCompute, + &pConfCompute->pRpcCcslCtx, + CC_GKEYID_GEN(CC_KEYSPACE_GSP, CC_LKEYID_CPU_GSP_LOCKED_RPC))); + NV_ASSERT_OK_OR_RETURN(ccslContextInitViaKeyId(pConfCompute, + &pConfCompute->pDmaCcslCtx, + CC_GKEYID_GEN(CC_KEYSPACE_GSP, CC_LKEYID_CPU_GSP_DMA))); + NV_ASSERT_OK_OR_RETURN(ccslContextInitViaKeyId(pConfCompute, + &pConfCompute->pReplayableFaultCcslCtx, + CC_GKEYID_GEN(CC_KEYSPACE_GSP, CC_LKEYID_GSP_CPU_REPLAYABLE_FAULT))); + NV_ASSERT_OK_OR_RETURN(ccslContextInitViaKeyId(pConfCompute, + &pConfCompute->pNonReplayableFaultCcslCtx, + CC_GKEYID_GEN(CC_KEYSPACE_GSP, CC_LKEYID_GSP_CPU_NON_REPLAYABLE_FAULT))); + + portMemSet(¶ms, 0, sizeof(params)); + params.bEncryptionControl = NV_TRUE; + + // Tell GSP-RM to start encrypting its responses. + NV_ASSERT_OK_OR_RETURN(status = pRmApi->Control(pRmApi, + pGpu->hInternalClient, + pGpu->hInternalSubdevice, + NV2080_CTRL_CMD_INTERNAL_CONF_COMPUTE_ENCRYPTION_CONTROL, + ¶ms, + sizeof(params))); + } + else + { + return NV_ERR_INVALID_STATE; + } + + return NV_OK; +} + +NV_STATUS +confComputeStopEncryption_KERNEL +( + OBJGPU *pGpu, + ConfidentialCompute *pConfCompute +) +{ + RM_API *pRmApi = GPU_GET_PHYSICAL_RMAPI(pGpu); + NV2080_CTRL_CMD_INTERNAL_CONF_COMPUTE_ENCRYPTION_CONTROL_PARAMS params; + NV_STATUS status = NV_OK; + + if (pConfCompute->getProperty(pConfCompute, PDB_PROP_CONFCOMPUTE_SPDM_ENABLED)) + { + if (!IS_GSP_CLIENT(pGpu)) + { + return NV_ERR_INVALID_STATE; + } + + if (pConfCompute->getProperty(pConfCompute, PDB_PROP_CONFCOMPUTE_ENCRYPT_READY)) + { + NV_PRINTF(LEVEL_INFO, "ConfCompute: Turning off receive encryption on Kernel-RM!\n"); + pConfCompute->setProperty(pConfCompute, PDB_PROP_CONFCOMPUTE_ENCRYPT_READY, NV_FALSE); + } + + portMemSet(¶ms, 0, sizeof(params)); + params.bEncryptionControl = NV_FALSE; + + // + // Tell GSP-RM to stop encrypting its data. + // Always have GPU delete secrets, regardless of CPU-RM state. + // + status = pRmApi->Control(pRmApi, + pGpu->hInternalClient, + pGpu->hInternalSubdevice, + NV2080_CTRL_CMD_INTERNAL_CONF_COMPUTE_ENCRYPTION_CONTROL, + ¶ms, + sizeof(params)); + + // Regardless of response, be sure to disable and clear all encryption secrets from kernel side. + if (pConfCompute->getProperty(pConfCompute, PDB_PROP_CONFCOMPUTE_ENCRYPT_ENABLED)) + { + NV_PRINTF(LEVEL_INFO, "ConfCompute: Turning off send encryption on Kernel-RM!\n"); + pConfCompute->setProperty(pConfCompute, PDB_PROP_CONFCOMPUTE_ENCRYPT_ENABLED, NV_FALSE); + } + + // Deinitialize CCSL contexts. + ccslContextClear(pConfCompute->pRpcCcslCtx); + ccslContextClear(pConfCompute->pDmaCcslCtx); + ccslContextClear(pConfCompute->pReplayableFaultCcslCtx); + ccslContextClear(pConfCompute->pNonReplayableFaultCcslCtx); + + pConfCompute->pRpcCcslCtx = NULL; + pConfCompute->pDmaCcslCtx = NULL; + pConfCompute->pReplayableFaultCcslCtx = NULL; + pConfCompute->pNonReplayableFaultCcslCtx = NULL; + } + + return status; +} + +/*! + * Deinitialize all keys required for the Confidential Compute session. + * + * Note: This assumes that Confidential Compute is the first object + * to be initialized in the GPU child order list, and therefore + * SPDM deinitialization is the last thing to happen. If another + * object precedes Confidential Compute - it will be deinitialized + * before SPDM. + * + * @param[in] pGpu GPU object pointer + * @param[in] pConfCompute ConfidentialCompute pointer + */ +void +confComputeStateDestroy_IMPL +( + OBJGPU *pGpu, + ConfidentialCompute *pConfCompute +) +{ + NV_STATUS status = NV_OK; + + status = _confComputeDeinitSpdmSession(pGpu, pConfCompute); + if (status != NV_OK) + { + NV_PRINTF(LEVEL_ERROR, "ConfCompute: Failed deinitializing SPDM: 0x%x!\n", status); + } + + status = confComputeStopEncryption_HAL(pGpu, pConfCompute); + if (status != NV_OK) + { + NV_PRINTF(LEVEL_ERROR, "ConfCompute: Failed disabling encryption: 0x%x!\n", status); + } + + confComputeKeyStoreDeinit_HAL(pConfCompute); + + return; +} diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/kernel/gpu/conf_compute/conf_compute_api.c nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/kernel/gpu/conf_compute/conf_compute_api.c --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/kernel/gpu/conf_compute/conf_compute_api.c 1970-01-01 00:00:00.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/kernel/gpu/conf_compute/conf_compute_api.c 2024-03-05 22:13:19.000000000 +0000 @@ -0,0 +1,319 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2021-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +/***************************************************************************\ + * * + * Confidential Compute API Object Module * + * * + \**************************************************************************/ + +#include "core/locks.h" +#include "rmapi/rs_utils.h" +#include "core/system.h" +#include "gpu/gpu.h" +#include "gpu/mem_mgr/mem_mgr.h" +#include "gpu/mem_mgr/heap.h" +#include "kernel/gpu/mig_mgr/kernel_mig_manager.h" +#include "kernel/gpu/fifo/kernel_fifo.h" +#include "gpu/conf_compute/conf_compute_api.h" +#include "gpu/subdevice/subdevice.h" +#include "class/clcb33.h" // NV_CONFIDENTIAL_COMPUTE + +NV_STATUS +confComputeApiConstruct_IMPL +( + ConfidentialComputeApi *pConfComputeApi, + CALL_CONTEXT *pCallContext, + RS_RES_ALLOC_PARAMS_INTERNAL *pParams +) +{ + OBJSYS *pSys = SYS_GET_INSTANCE(); + OBJGPUMGR *pGpuMgr = SYS_GET_GPUMGR(pSys); + + pConfComputeApi->pCcCaps = &pGpuMgr->ccCaps; + + return NV_OK; +} + +void +confComputeApiDestruct_IMPL +( + ConfidentialComputeApi *pConfComputeApi +) +{ +} + +NV_STATUS +confComputeApiCtrlCmdSystemGetCapabilities_IMPL +( + ConfidentialComputeApi *pConfComputeApi, + NV_CONF_COMPUTE_CTRL_CMD_SYSTEM_GET_CAPABILITIES_PARAMS *pParams +) +{ + OBJSYS *pSys = SYS_GET_INSTANCE(); + CONF_COMPUTE_CAPS *pCcCaps = pConfComputeApi->pCcCaps; + + LOCK_ASSERT_AND_RETURN(rmapiLockIsOwner() && rmGpuLockIsOwner()); + + pParams->cpuCapability = NV_CONF_COMPUTE_SYSTEM_CPU_CAPABILITY_NONE; + if ((sysGetStaticConfig(pSys))->bOsCCEnabled) + { + pParams->cpuCapability = NV_CONF_COMPUTE_SYSTEM_CPU_CAPABILITY_AMD_SEV; + if ((sysGetStaticConfig(pSys))->bOsCCTdxEnabled) + { + pParams->cpuCapability = NV_CONF_COMPUTE_SYSTEM_CPU_CAPABILITY_INTEL_TDX; + } + } + + pParams->gpusCapability = NV_CONF_COMPUTE_SYSTEM_GPUS_CAPABILITY_NONE; + pParams->environment = NV_CONF_COMPUTE_SYSTEM_ENVIRONMENT_UNAVAILABLE; + pParams->ccFeature = NV_CONF_COMPUTE_SYSTEM_FEATURE_DISABLED; + pParams->devToolsMode = NV_CONF_COMPUTE_SYSTEM_DEVTOOLS_MODE_DISABLED; + + if (pCcCaps->bApmFeatureCapable) + { + pParams->gpusCapability = NV_CONF_COMPUTE_SYSTEM_GPUS_CAPABILITY_APM; + } + else if (pCcCaps->bHccFeatureCapable) + { + pParams->gpusCapability = NV_CONF_COMPUTE_SYSTEM_GPUS_CAPABILITY_HCC; + } + + if (pCcCaps->bCCFeatureEnabled) + { + if (pCcCaps->bApmFeatureCapable) + { + pParams->ccFeature = NV_CONF_COMPUTE_SYSTEM_FEATURE_APM_ENABLED; + } + else if (pCcCaps->bHccFeatureCapable) + { + pParams->ccFeature = NV_CONF_COMPUTE_SYSTEM_FEATURE_HCC_ENABLED; + } + } + + if (pCcCaps->bDevToolsModeEnabled) + { + pParams->devToolsMode = NV_CONF_COMPUTE_SYSTEM_DEVTOOLS_MODE_ENABLED; + } + + if (pParams->ccFeature != NV_CONF_COMPUTE_SYSTEM_FEATURE_DISABLED) + { + pParams->environment = NV_CONF_COMPUTE_SYSTEM_ENVIRONMENT_SIM; + } + + return NV_OK; +} + +NV_STATUS +confComputeApiCtrlCmdSystemGetGpusState_IMPL +( + ConfidentialComputeApi *pConfComputeApi, + NV_CONF_COMPUTE_CTRL_CMD_SYSTEM_GET_GPUS_STATE_PARAMS *pParams +) +{ + LOCK_ASSERT_AND_RETURN(rmapiLockIsOwner() && rmGpuLockIsOwner()); + + pParams->bAcceptClientRequest = pConfComputeApi->pCcCaps->bAcceptClientRequest; + + return NV_OK; +} + +NV_STATUS +confComputeApiCtrlCmdSystemSetGpusState_IMPL +( + ConfidentialComputeApi *pConfComputeApi, + NV_CONF_COMPUTE_CTRL_CMD_SYSTEM_SET_GPUS_STATE_PARAMS *pParams +) +{ + LOCK_ASSERT_AND_RETURN(rmapiLockIsOwner() && rmGpuLockIsOwner()); + + pConfComputeApi->pCcCaps->bAcceptClientRequest = pParams->bAcceptClientRequest; + + return NV_OK; +} + +NV_STATUS +confComputeApiCtrlCmdGpuGetVidmemSize_IMPL +( + ConfidentialComputeApi *pConfComputeApi, + NV_CONF_COMPUTE_CTRL_CMD_GPU_GET_VIDMEM_SIZE_PARAMS *pParams +) +{ + Subdevice *pSubdevice = NULL; + OBJGPU *pGpu = NULL; + Heap *pHeap = NULL; + Heap *pMemoryPartitionHeap = NULL; + KernelMIGManager *pKernelMIGManager = NULL; + NvU64 totalProtectedBytes = 0; + NvU64 totalUnprotectedBytes = 0; + + LOCK_ASSERT_AND_RETURN(rmapiLockIsOwner() && rmGpuLockIsOwner()); + + NV_CHECK_OK_OR_RETURN(LEVEL_INFO, + subdeviceGetByHandle(RES_GET_CLIENT(pConfComputeApi), + pParams->hSubDevice, &pSubdevice)); + + pGpu = GPU_RES_GET_GPU(pSubdevice); + pHeap = GPU_GET_HEAP(pGpu); + pKernelMIGManager = GPU_GET_KERNEL_MIG_MANAGER(pGpu); + + // + // If MIG-GPU-Instancing is enabled, we check for GPU instance subscription + // and provide GPU instance local info + // + if (IS_MIG_IN_USE(pGpu)) + { + NV_CHECK_OK_OR_RETURN(LEVEL_INFO, + kmigmgrGetMemoryPartitionHeapFromDevice(pGpu, pKernelMIGManager, + GPU_RES_GET_DEVICE(pSubdevice), + &pMemoryPartitionHeap)); + // + // If client is associated with a GPU instance then point pHeap + // to client's memory partition heap + // + if (pMemoryPartitionHeap != NULL) + pHeap = pMemoryPartitionHeap; + } + + pmaGetTotalProtectedMemory(&pHeap->pmaObject, &totalProtectedBytes); + pmaGetTotalUnprotectedMemory(&pHeap->pmaObject, &totalUnprotectedBytes); + + pParams->protectedMemSizeInKb = totalProtectedBytes >> 10; + pParams->unprotectedMemSizeInKb = totalUnprotectedBytes >> 10; + + return NV_OK; +} + +NV_STATUS +confComputeApiCtrlCmdGpuSetVidmemSize_IMPL +( + ConfidentialComputeApi *pConfComputeApi, + NV_CONF_COMPUTE_CTRL_CMD_GPU_SET_VIDMEM_SIZE_PARAMS *pParams +) +{ + LOCK_ASSERT_AND_RETURN(rmapiLockIsOwner() && rmGpuLockIsOwner()); + + return NV_OK; +} + +NV_STATUS +confComputeApiCtrlCmdGetGpuCertificate_IMPL +( + ConfidentialComputeApi *pConfComputeApi, + NV_CONF_COMPUTE_CTRL_CMD_GET_GPU_CERTIFICATE_PARAMS *pParams +) +{ + Subdevice *pSubdevice = NULL; + OBJGPU *pGpu = NULL; + ConfidentialCompute *pConfCompute = NULL; + + LOCK_ASSERT_AND_RETURN(rmapiLockIsOwner() && rmGpuLockIsOwner()); + + NV_CHECK_OK_OR_RETURN(LEVEL_INFO, + subdeviceGetByHandle(RES_GET_CLIENT(pConfComputeApi), + pParams->hSubDevice, &pSubdevice)); + pGpu = GPU_RES_GET_GPU(pSubdevice); + pConfCompute = GPU_GET_CONF_COMPUTE(pGpu); + + if (pConfCompute != NULL && pConfCompute->pSpdm != NULL && + pConfCompute->getProperty(pConfCompute, PDB_PROP_CONFCOMPUTE_SPDM_ENABLED)) + { + // Set max size of certificate buffers before calling SPDM. + pParams->certChainSize = NV_CONF_COMPUTE_CERT_CHAIN_MAX_SIZE; + pParams->attestationCertChainSize = NV_CONF_COMPUTE_ATTESTATION_CERT_CHAIN_MAX_SIZE; + + return spdmGetCertChains_HAL(pGpu, + pConfCompute->pSpdm, + pParams->certChain, + &pParams->certChainSize, + pParams->attestationCertChain, + &pParams->attestationCertChainSize); + } + + return NV_ERR_OBJECT_NOT_FOUND; +} + +NV_STATUS +confComputeApiCtrlCmdGetGpuAttestationReport_IMPL +( + ConfidentialComputeApi *pConfComputeApi, + NV_CONF_COMPUTE_CTRL_CMD_GET_GPU_ATTESTATION_REPORT_PARAMS *pParams +) +{ + Subdevice *pSubdevice = NULL; + OBJGPU *pGpu = NULL; + ConfidentialCompute *pConfCompute = NULL; + + LOCK_ASSERT_AND_RETURN(rmapiLockIsOwner() && rmGpuLockIsOwner()); + + NV_CHECK_OK_OR_RETURN(LEVEL_INFO, + subdeviceGetByHandle(RES_GET_CLIENT(pConfComputeApi), + pParams->hSubDevice, &pSubdevice)); + pGpu = GPU_RES_GET_GPU(pSubdevice); + pConfCompute = GPU_GET_CONF_COMPUTE(pGpu); + + if (pConfCompute != NULL && pConfCompute->pSpdm != NULL && + pConfCompute->getProperty(pConfCompute, PDB_PROP_CONFCOMPUTE_SPDM_ENABLED)) + { + // Set max size of report buffers before calling SPDM. + pParams->attestationReportSize = NV_CONF_COMPUTE_GPU_ATTESTATION_REPORT_MAX_SIZE; + pParams->cecAttestationReportSize = NV_CONF_COMPUTE_GPU_CEC_ATTESTATION_REPORT_MAX_SIZE; + + return spdmGetAttestationReport(pGpu, + pConfCompute->pSpdm, + pParams->nonce, + pParams->attestationReport, + &pParams->attestationReportSize, + &pParams->isCecAttestationReportPresent, + pParams->cecAttestationReport, + &pParams->cecAttestationReportSize); + } + + return NV_ERR_OBJECT_NOT_FOUND; +} + +NV_STATUS +confComputeApiCtrlCmdGpuGetNumSecureChannels_IMPL +( + ConfidentialComputeApi *pConfComputeApi, + NV_CONF_COMPUTE_CTRL_CMD_GPU_GET_NUM_SECURE_CHANNELS_PARAMS *pParams +) +{ + Subdevice *pSubdevice; + OBJGPU *pGpu; + KernelFifo *pKernelFifo; + + LOCK_ASSERT_AND_RETURN(rmapiLockIsOwner() && rmGpuLockIsOwner()); + + NV_CHECK_OK_OR_RETURN(LEVEL_INFO, + subdeviceGetByHandle(RES_GET_CLIENT(pConfComputeApi), + pParams->hSubDevice, &pSubdevice)); + + pGpu = GPU_RES_GET_GPU(pSubdevice); + pKernelFifo = GPU_GET_KERNEL_FIFO(pGpu); + + pParams->maxSec2Channels = pKernelFifo->maxSec2SecureChannels; + pParams->maxCeChannels = pKernelFifo->maxCeSecureChannels; + + return NV_OK; +} diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/kernel/gpu/conf_compute/conf_compute_keystore.c nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/kernel/gpu/conf_compute/conf_compute_keystore.c --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/kernel/gpu/conf_compute/conf_compute_keystore.c 1970-01-01 00:00:00.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/kernel/gpu/conf_compute/conf_compute_keystore.c 2024-03-05 22:13:19.000000000 +0000 @@ -0,0 +1,350 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2021-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#include "kernel/gpu/conf_compute/conf_compute_keystore.h" +#include "class/cl2080.h" +#include "libraries/nvport/nvport.h" + +#define NUM_SLOTS (KEYSTORE_SLOT_LCE_MGPU(7) + 1) + +#define CONCAT64(hi, low) ((((NvU64)(hi) << 32)) | ((NvU64)(low))) + +// TODO: Remove once key slots are populated by SPDM module. +#define lceBundle \ +{\ + .encryptBundle =\ + {\ + .key = {0x38782F41, 0x3F442847, 0x2B4B6250, 0x65536756, 0x6B597033, 0x73367639, 0x79244226, 0x45294840},\ + .iv = {0x00000000, 0x00000000, 0x00000000},\ + .ivMask = {0x00000000, 0x00000000, 0x00000000}\ + },\ + .decryptBundle =\ + {\ + .key = {0x566B5970, 0x33733676, 0x39792442, 0x26452948, 0x404D6251, 0x65546857, 0x6D5A7134, 0x74377721},\ + .iv = {0x00000000, 0x00000000, 0x00000000},\ + .ivMask = {0x00000000, 0x00000000, 0x00000000}\ + },\ + .bIsWorkLaunch = NV_FALSE\ +} + +static enum {HCC, APM} ccMode; + +// TODO: Remove initialization once key slots are populated by SPDM module. +// Currently the APM Requester will populate the SEC2 slots. +// HCC still relies on hardcoded keys. +static CC_KMB keySlot[NUM_SLOTS] = +{ + lceBundle, lceBundle, + lceBundle, lceBundle, lceBundle, + lceBundle, lceBundle, lceBundle, + lceBundle, lceBundle, lceBundle, + lceBundle, lceBundle, lceBundle, + lceBundle, lceBundle, lceBundle, + lceBundle, lceBundle, lceBundle, + lceBundle, lceBundle, lceBundle, + lceBundle, lceBundle, lceBundle +}; + +static NV_STATUS checkSlot (NvU32 slotNumber, ROTATE_IV_TYPE rotateOperation); +static void incrementChannelCounter (NvU32 slotNumber, ROTATE_IV_TYPE rotateOperation); +static NvU64 getChannelCounter (NvU32 slotNumber, ROTATE_IV_TYPE rotateOperation); +static NV_STATUS checkAndIncrementSlot (NvU32 slotNumber, ROTATE_IV_TYPE rotateOperation); +static NV_STATUS getSlotNumberLce (KernelChannel *pKernelChannel, NvU32 *slotNumber); +static NvU64 getChannelMaxValue (void); + +NV_STATUS +ccKeyStoreInit (OBJGPU *pGpu) +{ + if (gpuIsApmFeatureEnabled(pGpu)) + { + ccMode = APM; + } + else if (gpuIsCCFeatureEnabled(pGpu)) + { + ccMode = HCC; + } + else + { + return NV_ERR_INVALID_STATE; + } + + return NV_OK; +} + +NV_STATUS +ccKeyStoreDeposit +( + NvU32 slotNumber, + CC_KMB keyMaterialBundle +) +{ + if (slotNumber >= NUM_SLOTS) + { + return NV_ERR_INVALID_INDEX; + } + + keySlot[slotNumber] = keyMaterialBundle; + + for (NvU32 index = 0; index < CC_AES_256_GCM_IV_SIZE_DWORD; index++) + { + keySlot[slotNumber].encryptBundle.iv[index] = 0; + keySlot[slotNumber].decryptBundle.iv[index] = 0; + } + + return NV_OK; +} + +NV_STATUS +ccKeyStoreRetrieveViaChannel +( + KernelChannel *pKernelChannel, + ROTATE_IV_TYPE rotateOperation, + PCC_KMB keyMaterialBundle +) +{ + NvU32 slotNumber; + + if (RM_ENGINE_TYPE_IS_COPY(kchannelGetEngineType(pKernelChannel))) + { + if (getSlotNumberLce (pKernelChannel, &slotNumber) != NV_OK) + { + return NV_ERR_INVALID_PARAMETER; + } + } + else if (kchannelGetEngineType(pKernelChannel) == RM_ENGINE_TYPE_SEC2) + { + slotNumber = KEYSTORE_SLOT_SEC2; + } + else + { + return NV_ERR_INVALID_PARAMETER; + } + + if ((rotateOperation == ROTATE_IV_ENCRYPT) || (rotateOperation == ROTATE_IV_ALL_VALID)) + { + if (checkAndIncrementSlot (slotNumber, ROTATE_IV_ENCRYPT) != NV_OK) + { + // Right now returns error to caller. Depending on how the re-keying flow is designed + // this may initiate re-keying. + + return NV_ERR_INSUFFICIENT_RESOURCES; + } + } + + if ((rotateOperation == ROTATE_IV_DECRYPT) || (rotateOperation == ROTATE_IV_ALL_VALID)) + { + if (checkAndIncrementSlot (slotNumber, ROTATE_IV_DECRYPT) != NV_OK) + { + // Right now returns error to caller. Depending on how the re-keying flow is designed + // this may initiate re-keying. + + return NV_ERR_INSUFFICIENT_RESOURCES; + } + } + + *keyMaterialBundle = keySlot[slotNumber]; + + return NV_OK; +} + +void +cckeyStoreClear (void) +{ + portMemSet (keySlot, 0, sizeof(keySlot)); +} + +static NV_STATUS +getSlotNumberLce +( + KernelChannel *pKernelChannel, + NvU32 *slotNumber +) +{ + NvU8 index; + + // TODO: Get actual privilege level of channel. For now assume + // all channels have user mode privilege. + switch (kchannelGetEngineType(pKernelChannel)) + { + case RM_ENGINE_TYPE_COPY0: + index = 0; + break; + case RM_ENGINE_TYPE_COPY1: + index = 1; + break; + case RM_ENGINE_TYPE_COPY2: + index = 2; + break; + case RM_ENGINE_TYPE_COPY3: + index = 3; + break; + case RM_ENGINE_TYPE_COPY4: + index = 4; + break; + case RM_ENGINE_TYPE_COPY5: + index = 5; + break; + case RM_ENGINE_TYPE_COPY6: + index = 6; + break; + case RM_ENGINE_TYPE_COPY7: + index = 7; + break; + default: + return NV_ERR_GENERIC; + } + + *slotNumber = KEYSTORE_SLOT_LCE_UMD(index); + + return NV_OK; +} + +static NV_STATUS +checkAndIncrementSlot +( + NvU32 slotNumber, + ROTATE_IV_TYPE rotateOperation // Will only be ROTATE_IV_ENCRYPT or ROTATE_IV_DECRYPT. +) +{ + if (checkSlot (slotNumber, rotateOperation) != NV_OK) + { + return NV_ERR_GENERIC; + } + + // TODO: Unconditionally increment channel counter once HCC supports it. + if (ccMode == APM) + { + incrementChannelCounter (slotNumber, rotateOperation); + } + + return NV_OK; +} + +static NV_STATUS +checkSlot +( + NvU32 slotNumber, + ROTATE_IV_TYPE rotateOperation // Will only be ROTATE_IV_ENCRYPT or ROTATE_IV_DECRYPT. +) +{ + if (getChannelCounter (slotNumber, rotateOperation) == getChannelMaxValue()) + { + return NV_ERR_GENERIC; + } + + return NV_OK; +} + +static void +incrementChannelCounter +( + NvU32 slotNumber, + ROTATE_IV_TYPE rotateOperation // Will only be ROTATE_IV_ENCRYPT or ROTATE_IV_DECRYPT. +) +{ + NvU64 channelCounter = getChannelCounter (slotNumber, rotateOperation); + + channelCounter++; + + switch (rotateOperation) + { + case ROTATE_IV_ENCRYPT: + if (ccMode == HCC) + { + keySlot[slotNumber].encryptBundle.iv[2] = (NvU32) (channelCounter >> 32); + keySlot[slotNumber].encryptBundle.iv[1] = (NvU32) (channelCounter); + } + else if (ccMode == APM) + { + keySlot[slotNumber].encryptBundle.iv[2] = (NvU32) (channelCounter); + } + break; + case ROTATE_IV_DECRYPT: + if (ccMode == HCC) + { + keySlot[slotNumber].decryptBundle.iv[2] = (NvU32) (channelCounter >> 32); + keySlot[slotNumber].decryptBundle.iv[1] = (NvU32) (channelCounter); + } + else if (ccMode == APM) + { + keySlot[slotNumber].decryptBundle.iv[2] = (NvU32) (channelCounter); + } + break; + default: + break; + } +} + +static NvU64 +getChannelCounter +( + NvU32 slotNumber, + ROTATE_IV_TYPE rotateOperation // Will only be ROTATE_IV_ENCRYPT or ROTATE_IV_DECRYPT. +) +{ + NvU64 channelCounter = 0; + + switch (rotateOperation) + { + case ROTATE_IV_ENCRYPT: + if (ccMode == HCC) + { + channelCounter = CONCAT64(keySlot[slotNumber].encryptBundle.iv[2], + keySlot[slotNumber].encryptBundle.iv[1]); + } + else if (ccMode == APM) + { + channelCounter = keySlot[slotNumber].encryptBundle.iv[2]; + } + break; + case ROTATE_IV_DECRYPT: + if (ccMode == HCC) + { + channelCounter = CONCAT64(keySlot[slotNumber].decryptBundle.iv[2], + keySlot[slotNumber].decryptBundle.iv[1]); + } + else if (ccMode == APM) + { + channelCounter = keySlot[slotNumber].decryptBundle.iv[2]; + } + break; + default: + break; + } + + return channelCounter; +} + +static NvU64 +getChannelMaxValue (void) +{ + switch (ccMode) + { + case HCC: + return NV_U64_MAX; + case APM: + return NV_U32_MAX; + default: + return 0; + } +} diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/kernel/gpu/deferred_api.c nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/kernel/gpu/deferred_api.c --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/kernel/gpu/deferred_api.c 2023-10-25 20:20:55.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/kernel/gpu/deferred_api.c 2024-03-05 22:13:19.000000000 +0000 @@ -45,7 +45,6 @@ static NV_STATUS _class5080DeferredApiV2(OBJGPU *pGpu, ChannelDescendant *Object, - METHOD *pMethod, NvU32 Offset, NvU32 Data); @@ -469,7 +468,6 @@ ( OBJGPU *pGpu, ChannelDescendant *Object, - METHOD *pMethod, NvU32 Offset, NvU32 Data ) @@ -479,7 +477,6 @@ NV5080_CTRL_DEFERRED_API_PARAMS *pDeferredApi; NV_STATUS rmStatus = NV_OK; NvU32 paramSize = 0; - NvHandle hDevice; NvBool bIsCtrlCall = NV_TRUE; rmStatus = _Class5080GetDeferredApiInfo(pDeferredApiObject, @@ -510,28 +507,36 @@ { OBJGPU *pTgtGpu; RsClient *pClientVA; + Subdevice *pSubdevice; bIsCtrlCall = NV_FALSE; - rmStatus = serverGetClientUnderLock(&g_resServ, pDeferredApi->hClientVA, &pClientVA); + rmStatus = serverGetClientUnderLock(&g_resServ, pDeferredApi->hClientVA, + &pClientVA); if (rmStatus != NV_OK) break; - if (CliSetSubDeviceContext( - pDeferredApi->hClientVA, - pDeferredApi->hDeviceVA, - &hDevice, - &pTgtGpu) != NV_OK) + rmStatus = subdeviceGetByHandle(pClientVA, pDeferredApi->hDeviceVA, + &pSubdevice); + + if (rmStatus != NV_OK) { NV_PRINTF(LEVEL_ERROR, "Unable to find target gpu from hClient(%x), hDevice(%x)\n", pDeferredApi->hClientVA, pDeferredApi->hDeviceVA); - - rmStatus = NV_ERR_INVALID_ARGUMENT; } else { + NvHandle hDevice; OBJVASPACE *pVAS = NULL; + + // Fetch target GPU and set threadstate + pTgtGpu = GPU_RES_GET_GPU(pSubdevice); + + hDevice = RES_GET_HANDLE(pSubdevice->pDevice); + + GPU_RES_SET_THREAD_BC_STATE(pSubdevice); + rmStatus = vaspaceGetByHandleOrDeviceDefault(pClientVA, hDevice, pDeferredApi->api_bundle.InvalidateTlb.hVASpace, @@ -655,7 +660,8 @@ callContext.secInfo.pProcessToken = (void *)(NvU64) gfid; } - resservSwapTlsCallContext(&pOldContext, &callContext); + NV_ASSERT_OK_OR_GOTO(rmStatus, + resservSwapTlsCallContext(&pOldContext, &callContext), cleanup); rmStatus = serverControl_Prologue(&g_resServ, &rmCtrlParams, &access, &releaseFlags); @@ -675,7 +681,7 @@ } } - resservRestoreTlsCallContext(pOldContext); + NV_ASSERT_OK(resservRestoreTlsCallContext(pOldContext)); rmStatus = serverControl_Epilogue(&g_resServ, &rmCtrlParams, access, &releaseFlags, rmStatus); } @@ -702,7 +708,7 @@ return rmStatus; } -static METHOD Nv50DeferredApi[] = +static const METHOD Nv50DeferredApi[] = { { mthdNoOperation, 0x0100, 0x0103 }, { _class5080DeferredApiV2, 0x0200, 0x0203 }, @@ -711,12 +717,12 @@ NV_STATUS defapiGetSwMethods_IMPL ( DeferredApiObject *pDeferredApi, - METHOD **ppMethods, + const METHOD **ppMethods, NvU32 *pNumMethods ) { *ppMethods = Nv50DeferredApi; - *pNumMethods = NV_ARRAY_ELEMENTS32(Nv50DeferredApi); + *pNumMethods = NV_ARRAY_ELEMENTS(Nv50DeferredApi); return NV_OK; } diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/kernel/gpu/device.c nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/kernel/gpu/device.c --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/kernel/gpu/device.c 2023-10-25 20:20:55.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/kernel/gpu/device.c 2024-03-05 22:13:19.000000000 +0000 @@ -195,8 +195,6 @@ NV_STATUS rmStatus = NV_OK; NV_STATUS tmpStatus; NvHandle hClient; - NODE *pNode; - RM_API *pRmApi = rmapiGetInterface(RMAPI_GPU_LOCK_INTERNAL); resGetFreeParams(staticCast(pDevice, RsResource), &pCallContext, &pParams); @@ -206,18 +204,6 @@ LOCK_METER_DATA(FREE_DEVICE, 0, 0, 0); - // Free all device memory - btreeEnumStart(0, &pNode, pDevice->DevMemoryTable); - while (pNode != NULL) - { - Memory *pMemory = pNode->Data; - btreeEnumNext(&pNode, pDevice->DevMemoryTable); - - tmpStatus = pRmApi->Free(pRmApi, hClient, RES_GET_HANDLE(pMemory)); - if ((tmpStatus != NV_OK) && (rmStatus == NV_OK)) - rmStatus = tmpStatus; - } - // free the device if (_deviceTeardownRef(pDevice, pCallContext) != NV_OK || _deviceTeardown(pDevice, pCallContext) != NV_OK) @@ -531,29 +517,6 @@ // **************************************************************************** /** - * WARNING: This function is deprecated! Please use deviceGetByHandle. - */ -Device * -CliGetDeviceInfo -( - NvHandle hClient, - NvHandle hDevice -) -{ - RsClient *pClient; - NV_STATUS status; - Device *pDevice; - - status = serverGetClientUnderLock(&g_resServ, hClient, &pClient); - if (status != NV_OK) - return NULL; - - status = deviceGetByHandle(pClient, hDevice, &pDevice); - - return (status == NV_OK) ? pDevice : NULL; -} - -/** * WARNING: This function is deprecated and use is *strongly* discouraged * (especially for new code!) * diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/kernel/gpu/device_ctrl.c nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/kernel/gpu/device_ctrl.c --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/kernel/gpu/device_ctrl.c 2023-10-25 20:20:55.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/kernel/gpu/device_ctrl.c 2024-03-05 22:13:19.000000000 +0000 @@ -35,6 +35,7 @@ #include "gpu/gpu.h" #include "gpu_mgr/gpu_mgr.h" #include "kernel/gpu/rc/kernel_rc.h" +#include "virtualization/hypervisor/hypervisor.h" @@ -210,6 +211,29 @@ pParams->virtualizationMode = NV0080_CTRL_GPU_VIRTUALIZATION_MODE_NMOS; } + else if (hypervisorIsVgxHyper() && (gpuIsSriovEnabled(pGpu) + )) + { + if (pGpu->getProperty(pGpu, PDB_PROP_GPU_IS_VIRTUALIZATION_MODE_HOST_VGPU)) + { + pParams->virtualizationMode = + NV0080_CTRL_GPU_VIRTUALIZATION_MODE_HOST_VGPU; + } + else if (pGpu->getProperty(pGpu, PDB_PROP_GPU_IS_VIRTUALIZATION_MODE_HOST_VSGA)) + { + pParams->virtualizationMode = + NV0080_CTRL_GPU_VIRTUALIZATION_MODE_HOST_VSGA; + } + else + { + NV_PRINTF(LEVEL_ERROR, + "invalid virtualization Mode: %x. Returning NONE!\n", + pParams->virtualizationMode); + + pParams->virtualizationMode = + NV0080_CTRL_GPU_VIRTUALIZATION_MODE_NONE; + } + } else { pParams->virtualizationMode = diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/kernel/gpu/disp/arch/v02/kern_disp_0207.c nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/kernel/gpu/disp/arch/v02/kern_disp_0207.c --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/kernel/gpu/disp/arch/v02/kern_disp_0207.c 2023-10-25 20:20:55.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/kernel/gpu/disp/arch/v02/kern_disp_0207.c 2024-03-05 22:13:19.000000000 +0000 @@ -53,3 +53,59 @@ *computedLsrMinTime = swapRdyHiLsrMinTime * 1000; return NV_OK; } + +NV_STATUS +kdispGetRgScanLock_v02_01 +( + POBJGPU pGpu, + KernelDisplay *pKernelDisplay, + NvU32 head0, + POBJGPU pPeerGpu, + NvU32 head1, + NvBool *pMasterScanLock, + NvU32 *pMasterScanLockPin, + NvBool *pSlaveScanLock, + NvU32 *pSlaveScanLockPin +) +{ + NvU32 pinSetOut, pinSetIn; + NV_STATUS rmStatus = NV_OK; + + if (!pMasterScanLock || !pMasterScanLockPin || + !pSlaveScanLock || !pSlaveScanLockPin || head0 >= pKernelDisplay->numHeads || + ((pPeerGpu != NULL) && (head1 >= pKernelDisplay->numHeads))) + { + return NV_ERR_INVALID_ARGUMENT; + } + + // + // The head parameters are not currently needed for G8X, but for more + // complicated setups or GT200 SLI, we may need to take them into + // consideration in the future. + // + rmStatus = gpumgrGetGpuLockAndDrPorts(pGpu, pPeerGpu, &pinSetOut, &pinSetIn); + if (rmStatus != NV_OK) + { + return rmStatus; + } + + NV2080_CTRL_INTERNAL_DISP_PINSETS_TO_LOCKPINS_PARAMS params = {0}; + params.pinSetIn = pinSetIn; + params.pinSetOut = pinSetOut; + + RM_API *pRmApi = GPU_GET_PHYSICAL_RMAPI(pGpu); + NV_ASSERT_OK_OR_RETURN(pRmApi->Control(pRmApi, + pGpu->hInternalClient, + pGpu->hInternalSubdevice, + NV2080_CTRL_CMD_INTERNAL_DISP_PINSETS_TO_LOCKPINS, + ¶ms, + sizeof(params))); + + *pMasterScanLock = params.bMasterScanLock; + *pMasterScanLockPin = params.masterScanLockPin; + + *pSlaveScanLock = params.bSlaveScanLock; + *pSlaveScanLockPin = params.slaveScanLockPin; + + return rmStatus; +} diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/kernel/gpu/disp/arch/v03/kern_disp_0300.c nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/kernel/gpu/disp/arch/v03/kern_disp_0300.c --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/kernel/gpu/disp/arch/v03/kern_disp_0300.c 2023-10-25 20:20:56.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/kernel/gpu/disp/arch/v03/kern_disp_0300.c 2024-03-05 22:13:19.000000000 +0000 @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 2020-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2020-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/kernel/gpu/disp/arch/v04/kern_disp_0400.c nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/kernel/gpu/disp/arch/v04/kern_disp_0400.c --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/kernel/gpu/disp/arch/v04/kern_disp_0400.c 2023-10-25 20:20:55.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/kernel/gpu/disp/arch/v04/kern_disp_0400.c 2024-03-05 22:13:19.000000000 +0000 @@ -33,7 +33,10 @@ #include "gpu/gpu.h" #include "gpu/disp/kern_disp.h" -#include "published/disp/v04_00/dev_disp.h" +#include "disp/v04_00/dev_disp.h" + +#include "ctrl/ctrl2080/ctrl2080gpio.h" +#include "core/locks.h" /*! * @brief Get the VGA workspace base address, if valid. @@ -57,3 +60,209 @@ return NV_FALSE; } + +static NV_STATUS setSliLinkGpioSwControl(OBJGPU *pGpu, + NvU32 pinSet, NvU32 *pGpioFunction, NvU32 *pGpioPin, NvBool *pGpioDirection) +{ + NV_STATUS status = NV_OK; + RM_API *pRmApi = GPU_GET_PHYSICAL_RMAPI(pGpu); + + NV2080_CTRL_INTERNAL_DISP_SET_SLI_LINK_GPIO_SW_CONTROL_PARAMS params = {0}; + params.pinSet = pinSet; + + status = pRmApi->Control(pRmApi, + pGpu->hInternalClient, + pGpu->hInternalSubdevice, + NV2080_CTRL_CMD_INTERNAL_DISP_SET_SLI_LINK_GPIO_SW_CONTROL, + ¶ms, + sizeof(params)); + + if (status == NV_OK) + { + *pGpioFunction = params.gpioFunction; + *pGpioPin = params.gpioPin; + *pGpioDirection = params.gpioDirection; + } + + return status; +} + +static NV_STATUS programGpioDirection(OBJGPU *pGpu, NvU32 gpioPin, NvBool bInput) +{ + NV_STATUS status = NV_OK; + RM_API *pRmApi = GPU_GET_PHYSICAL_RMAPI(pGpu); + + NV2080_CTRL_INTERNAL_GPIO_PROGRAM_DIRECTION_PARAMS params = {0}; + params.gpioPin = gpioPin; + params.bInput = bInput; + + status = pRmApi->Control(pRmApi, + pGpu->hInternalClient, + pGpu->hInternalSubdevice, + NV2080_CTRL_CMD_INTERNAL_GPIO_PROGRAM_DIRECTION, + ¶ms, + sizeof(params)); + return status; +} + +static NV_STATUS programGpioOutput(OBJGPU *pGpu, NvU32 gpioPin, NvU32 value) +{ + NV_STATUS status = NV_OK; + RM_API *pRmApi = GPU_GET_PHYSICAL_RMAPI(pGpu); + + NV2080_CTRL_INTERNAL_GPIO_PROGRAM_OUTPUT_PARAMS params = {0}; + params.gpioPin = gpioPin; + params.value = value; + + status = pRmApi->Control(pRmApi, + pGpu->hInternalClient, + pGpu->hInternalSubdevice, + NV2080_CTRL_CMD_INTERNAL_GPIO_PROGRAM_OUTPUT, + ¶ms, + sizeof(params)); + return status; +} + +static NV_STATUS readGpioInput(OBJGPU *pGpu, NvU32 gpioPin, NvU32 *value) +{ + NV_STATUS status = NV_OK; + RM_API *pRmApi = GPU_GET_PHYSICAL_RMAPI(pGpu); + + NV2080_CTRL_INTERNAL_GPIO_READ_INPUT_PARAMS params = {0}; + params.gpioPin = gpioPin; + + status = pRmApi->Control(pRmApi, + pGpu->hInternalClient, + pGpu->hInternalSubdevice, + NV2080_CTRL_CMD_INTERNAL_GPIO_READ_INPUT, + ¶ms, + sizeof(params)); + + if (status == NV_OK) + *value = params.value; + + return status; +} + +static NV_STATUS activateHwFunction(OBJGPU *pGpu, NvU32 gpioPin, NvU32 function) +{ + NV_STATUS status = NV_OK; + RM_API *pRmApi = GPU_GET_PHYSICAL_RMAPI(pGpu); + + NV2080_CTRL_INTERNAL_GPIO_ACTIVATE_HW_FUNCTION_PARAMS params = {0}; + params.pin = gpioPin; + params.function = function; + + status = pRmApi->Control(pRmApi, + pGpu->hInternalClient, + pGpu->hInternalSubdevice, + NV2080_CTRL_CMD_INTERNAL_GPIO_ACTIVATE_HW_FUNCTION, + ¶ms, + sizeof(params)); + + return status; +} + +#define GPIO_INVALID_PIN 0xff + +NV_STATUS kdispDetectSliLink_v04_00(KernelDisplay *pKernelDisplay, OBJGPU *pParentGpu, OBJGPU *pChildGpu, NvU32 parentPinSet, NvU32 childPinSet) +{ + // Sanity check, this function should be called with pDisp of Parent GPU + NV_ASSERT(pKernelDisplay == GPU_GET_KERNEL_DISPLAY(pParentGpu)); + + NvU32 parentGpioFunction = 0; + NvU32 childGpioFunction = 0; + NvBool parentGpioDirection = NV_FALSE; + NvBool childGpioDirection = NV_FALSE; + + NvU32 parentGpioPin = GPIO_INVALID_PIN; + NvU32 childGpioPin = GPIO_INVALID_PIN; + NvU32 value = 0; + + NV_STATUS rmStatus; + + // Check the pinset info, needs to have only one bit set + if (!ONEBITSET(parentPinSet) || !ONEBITSET(childPinSet)) + { + return NV_ERR_INVALID_ARGUMENT; + } + + NvU32 parentGpuLockMask = 0, childGpuLockMask = 0; + if (IS_GSP_CLIENT(pParentGpu) && !rmDeviceGpuLockIsOwner(pParentGpu->gpuInstance)) + NV_ASSERT_OK_OR_GOTO(rmStatus, rmGpuGroupLockAcquire(pParentGpu->gpuInstance, + GPU_LOCK_GRP_SUBDEVICE, + GPUS_LOCK_FLAGS_NONE, + RM_LOCK_MODULES_RPC, + &parentGpuLockMask), done); + + if (IS_GSP_CLIENT(pChildGpu) && !rmDeviceGpuLockIsOwner(pChildGpu->gpuInstance)) + NV_ASSERT_OK_OR_GOTO(rmStatus, rmGpuGroupLockAcquire(pChildGpu->gpuInstance, + GPU_LOCK_GRP_SUBDEVICE, + GPUS_LOCK_FLAGS_NONE, + RM_LOCK_MODULES_RPC, + &childGpuLockMask), done); + + // Set the gpio on parent gpu to sw control mode(aka normal) for twiddling + NV_CHECK_OK_OR_GOTO(rmStatus, LEVEL_INFO, + setSliLinkGpioSwControl(pParentGpu, parentPinSet, + &parentGpioFunction, &parentGpioPin, &parentGpioDirection), done); + + NV_CHECK_OK_OR_GOTO(rmStatus, LEVEL_INFO, + setSliLinkGpioSwControl(pChildGpu, childPinSet, + &childGpioFunction, &childGpioPin, &childGpioDirection), done); + + rmStatus = NV_ERR_NO_VALID_PATH; + + // Program the GPIO direction on parent and child + NV_ASSERT_OK_OR_GOTO(rmStatus, programGpioDirection(pParentGpu, parentGpioPin, NV_FALSE), done); + NV_ASSERT_OK_OR_GOTO(rmStatus, programGpioDirection(pChildGpu, childGpioPin, NV_TRUE), done); + + // Toggle GPIO on parent, and read from child + NV_ASSERT_OK_OR_GOTO(rmStatus, programGpioOutput(pParentGpu, parentGpioPin, 1), done); + NV_ASSERT_OK_OR_GOTO(rmStatus, readGpioInput(pChildGpu, childGpioPin, &value), done); + NV_ASSERT_OR_GOTO(value == 1, done); + + NV_ASSERT_OK_OR_GOTO(rmStatus, programGpioOutput(pParentGpu, parentGpioPin, 0), done); + NV_ASSERT_OK_OR_GOTO(rmStatus, readGpioInput(pChildGpu, childGpioPin, &value), done); + NV_ASSERT_OR_GOTO(value == 0, done); + + // Program the GPIO direction on parent and child + NV_ASSERT_OK_OR_GOTO(rmStatus, programGpioDirection(pParentGpu, parentGpioPin, NV_TRUE), done); + NV_ASSERT_OK_OR_GOTO(rmStatus, programGpioDirection(pChildGpu, childGpioPin, NV_FALSE), done); + + // Toggle GPIO on child, and read from parent + NV_ASSERT_OK_OR_GOTO(rmStatus, programGpioOutput(pChildGpu, childGpioPin, 1), done); + NV_ASSERT_OK_OR_GOTO(rmStatus, readGpioInput(pParentGpu, parentGpioPin, &value), done); + NV_ASSERT_OR_GOTO(value == 1, done); + + NV_ASSERT_OK_OR_GOTO(rmStatus, programGpioOutput(pChildGpu, childGpioPin, 0), done); + NV_ASSERT_OK_OR_GOTO(rmStatus, readGpioInput(pParentGpu, parentGpioPin, &value), done); + NV_ASSERT_OR_GOTO(value == 0, done); + + // Link in both direction is verified + rmStatus = NV_OK; + +done: + // Set the GPIOs on both GPUs to original direction and hw function state + if (parentGpioPin != GPIO_INVALID_PIN) + { + NV_ASSERT_OK(programGpioDirection(pParentGpu, parentGpioPin, parentGpioDirection)); + // restore the gpio to hw control mode. (aka non-normal mode) + NV_ASSERT_OK(activateHwFunction(pParentGpu, parentGpioPin, parentGpioFunction)); + } + + if (childGpioPin != GPIO_INVALID_PIN) + { + NV_ASSERT_OK(programGpioDirection(pChildGpu, childGpioPin, childGpioDirection)); + // restore the gpio to hw control mode. (aka non-normal mode) + NV_ASSERT_OK(activateHwFunction(pChildGpu, childGpioPin, childGpioFunction)); + } + + if (parentGpuLockMask != 0) + rmGpuGroupLockRelease(parentGpuLockMask, GPUS_LOCK_FLAGS_NONE); + + if (childGpuLockMask != 0) + rmGpuGroupLockRelease(childGpuLockMask, GPUS_LOCK_FLAGS_NONE); + + return rmStatus; +} diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/kernel/gpu/disp/disp_capabilities.c nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/kernel/gpu/disp/disp_capabilities.c --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/kernel/gpu/disp/disp_capabilities.c 2023-10-25 20:20:56.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/kernel/gpu/disp/disp_capabilities.c 2024-03-05 22:13:20.000000000 +0000 @@ -47,14 +47,6 @@ OBJGPU *pGpu = GPU_RES_GET_GPU(pDispCapabilities); KernelDisplay *pKernelDisplay = GPU_GET_KERNEL_DISPLAY(pGpu); - if (pParams->pSecInfo->privLevel < RS_PRIV_LEVEL_USER_ROOT) - { - NV_PRINTF(LEVEL_ERROR, - "Failure allocating display class 0x%08x: Only root(admin)/kernel clients are allowed\n", - pParams->externalClassId); - - return NV_ERR_INSUFFICIENT_PERMISSIONS; - } // Set display caps RegBase offsets kdispGetDisplayCapsBaseAndSize_HAL(pGpu, pKernelDisplay, &pDispCapabilities->ControlOffset, diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/kernel/gpu/disp/disp_channel.c nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/kernel/gpu/disp/disp_channel.c --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/kernel/gpu/disp/disp_channel.c 2023-10-25 20:20:56.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/kernel/gpu/disp/disp_channel.c 2024-03-05 22:13:20.000000000 +0000 @@ -126,9 +126,16 @@ if (pParams->pSecInfo->privLevel < RS_PRIV_LEVEL_USER_ROOT) { NV_PRINTF(LEVEL_ERROR, - "Failure allocating display class 0x%08x: Only root(admin)/kernel clients are allowed\n", + "Failure allocating display class 0x%08x: Only root(admin)/kernel clients are allowed\n", pParams->externalClassId); + // + // GPUSWSEC-1560 introduced a central object privilege check in RS. Please mark derived external classes + // of DispChannel privileged in their RS_ENTRY. Since DispChannel doesn't have an external class of its own + // and is used as a base class, leaving this check inline to catch future derivations. + // + osAssertFailed(); + return NV_ERR_INSUFFICIENT_PERMISSIONS; } @@ -175,7 +182,7 @@ { rmStatus = kdispSetPushBufferParamsToPhysical_HAL(pGpu, pKernelDisplay, - pDispChannel, + pDispChannel, hObjectBuffer, pBufferContextDma, hClass, @@ -294,7 +301,7 @@ { rmStatus = kdispSetPushBufferParamsToPhysical_HAL(pGpu, pKernelDisplay, - pDispChannel, + pDispChannel, hObjectBuffer, pBufferContextDma, hClass, diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/kernel/gpu/disp/disp_common_ctrl_acpi.c nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/kernel/gpu/disp/disp_common_ctrl_acpi.c --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/kernel/gpu/disp/disp_common_ctrl_acpi.c 2023-10-25 20:20:56.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/kernel/gpu/disp/disp_common_ctrl_acpi.c 2024-03-05 22:13:20.000000000 +0000 @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 2020-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2020-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -62,6 +62,7 @@ staticCast(pDispCommon, DisplayApi), DISPAPI_GET_GPUGRP(pDispCommon), &pGpu, + NULL, pParams->mapTable[acpiIdx].subDeviceInstance); if (status != NV_OK) return status; @@ -97,6 +98,48 @@ return status; } +NV_STATUS +dispcmnCtrlCmdSystemAcpiSubsystemActivated_IMPL +( + DispCommon *pDispCommon, + NV0073_CTRL_SYSTEM_ACPI_SUBSYSTEM_ACTIVATED_PARAMS *pParams +) +{ + OBJGPU *pGpu = DISPAPI_GET_GPU(pDispCommon); + RM_API *pRmApi = GPU_GET_PHYSICAL_RMAPI(pGpu); + OBJOS *pOs = NULL; + NV_STATUS status = NV_OK; + + // client gave us a subdevice #: get right pGpu/pDisp for it + status = dispapiSetUnicastAndSynchronize_HAL( + staticCast(pDispCommon, DisplayApi), + DISPAPI_GET_GPUGRP(pDispCommon), + &pGpu, + NULL, + pParams->subDeviceInstance); + if (status != NV_OK) + { + return status; + } + + pOs = GPU_GET_OS(pGpu); + + pOs->setProperty(pOs, PDB_PROP_OS_WAIT_FOR_ACPI_SUBSYSTEM, NV_FALSE); + + status = pRmApi->Control(pRmApi, pGpu->hInternalClient, pGpu->hInternalSubdevice, + NV2080_CTRL_CMD_INTERNAL_DISPLAY_ACPI_SUBSYSTEM_ACTIVATED, + NULL, 0); + + if (status != NV_OK) + { + NV_PRINTF(LEVEL_INFO, + "ERROR: NV0073_CTRL_SYSTEM_ACPI_SUBSYSTEM_ACTIVATED control call failed. " + "Should be rmapi ctrl call which is failed"); + } + + return status; +} + // // This rmctrl MUST NOT touch hw since it's tagged as NO_GPUS_ACCESS in ctrl0073.def // RM allow this type of rmctrl to go through when GPU is not available. @@ -187,7 +230,7 @@ acpiId = pfmFindAcpiId(pPfm, pGpu, displayMask); outDataSize = sizeof(NvU32); - outStatus = pOS->osCallACPI_MXMX(pGpu, acpiId, pInOutData); + outStatus = osCallACPI_MXMX(pGpu, acpiId, pInOutData); break; } @@ -200,7 +243,7 @@ } outDataSize = sizeof(NvU32); - outStatus = pOS->osCallACPI_NVHG_GPUON(pGpu, (NvU32*) pInOutData); + outStatus = osCallACPI_NVHG_GPUON(pGpu, (NvU32*) pInOutData); break; } case NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_GPUOFF: @@ -212,7 +255,7 @@ } outDataSize = sizeof(NvU32); - outStatus = pOS->osCallACPI_NVHG_GPUOFF(pGpu, (NvU32*) pInOutData); + outStatus = osCallACPI_NVHG_GPUOFF(pGpu, (NvU32*) pInOutData); break; } case NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_GPUSTA: @@ -270,7 +313,7 @@ sizeof(NvU32)); outDataSize = sizeof(NvU32); - outStatus = pOS->osCallACPI_MXDS(pGpu, acpiId, (NvU32*) pInOutData); + outStatus = osCallACPI_MXDS(pGpu, acpiId, (NvU32*) pInOutData); break; } case NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_NBCI_MXDM: @@ -292,8 +335,8 @@ ((NvU8*) pInOutData) + NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_NBCI_MXDM_DISP_MASK_OFFSET, sizeof(NvU32)); + outStatus = osCallACPI_MXDM(pGpu, acpiId, (NvU32*) pInOutData); outDataSize = sizeof(NvU32); - outStatus = pOS->osCallACPI_MXDM(pGpu, acpiId, (NvU32*) pInOutData); break; } case NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_NBCI_MXID: @@ -311,7 +354,7 @@ sizeof(NvU32)); outDataSize = sizeof(NvU32); - outStatus = pOS->osCallACPI_MXID(pGpu, acpiId, (NvU32*) pInOutData); + outStatus = osCallACPI_MXID(pGpu, acpiId, (NvU32*) pInOutData); break; } case NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_NBCI_LRST: @@ -327,8 +370,8 @@ ((NvU8*) pInOutData) + NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_NBCI_LRST_DISP_MASK_OFFSET, sizeof(NvU32)); + outStatus = osCallACPI_LRST(pGpu, acpiId, (NvU32*) pInOutData); outDataSize = sizeof(NvU32); - outStatus = pOS->osCallACPI_LRST(pGpu, acpiId, (NvU32*) pInOutData); break; } case NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_DDC_EDID: @@ -345,8 +388,8 @@ sizeof(NvU32)); NvU32 outSize = outDataSize; - outStatus = pOS->osCallACPI_DDC(pGpu, acpiId, (NvU8*) pInOutData, - &outSize, NV_TRUE /*bReadMultiBlock*/); + outStatus = osCallACPI_DDC(pGpu, acpiId, (NvU8*) pInOutData, + &outSize, NV_TRUE /*bReadMultiBlock*/); outDataSize = (NvU16) outSize; break; } @@ -411,7 +454,7 @@ } outDataSize = pBuffer[1]; - outStatus = pGpu->pOS->osCallACPI_NVHG_ROM(pGpu, (NvU32*) pInOutData, (NvU32*) pInOutData); + outStatus = osCallACPI_NVHG_ROM(pGpu, (NvU32*) pInOutData, (NvU32*) pInOutData); break; } case NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_DCS: @@ -432,116 +475,116 @@ case NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_DOD: { NvU32 size32 = inOutDataSize; - outStatus = pOS->osCallACPI_DOD(pGpu, (NvU32*) pInOutData, &size32); + outStatus = osCallACPI_DOD(pGpu, (NvU32*) pInOutData, &size32); outDataSize = (NvU16) size32; break; } case NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_DSM_SUPPORT: { - outStatus = pOS->osCallACPI_DSM(pGpu, ACPI_DSM_FUNCTION_NVHG, NVHG_FUNC_SUPPORT, (NvU32*) pInOutData, &outDataSize); + outStatus = osCallACPI_DSM(pGpu, ACPI_DSM_FUNCTION_NVHG, NVHG_FUNC_SUPPORT, (NvU32*) pInOutData, &outDataSize); break; } case NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_DSM_HYBRIDCAPS: { - outStatus = pOS->osCallACPI_DSM(pGpu, ACPI_DSM_FUNCTION_NVHG, NVHG_FUNC_HYBRIDCAPS, (NvU32*) pInOutData, &outDataSize); + outStatus = osCallACPI_DSM(pGpu, ACPI_DSM_FUNCTION_NVHG, NVHG_FUNC_HYBRIDCAPS, (NvU32*) pInOutData, &outDataSize); break; } case NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_DSM_POLICYSELECT: { - outStatus = pOS->osCallACPI_DSM(pGpu, ACPI_DSM_FUNCTION_NVHG, NVHG_FUNC_POLICYSELECT, (NvU32*) pInOutData, &outDataSize); + outStatus = osCallACPI_DSM(pGpu, ACPI_DSM_FUNCTION_NVHG, NVHG_FUNC_POLICYSELECT, (NvU32*) pInOutData, &outDataSize); break; } case NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_DSM_POWERCONTROL: { - outStatus = pOS->osCallACPI_DSM(pGpu, ACPI_DSM_FUNCTION_NVHG, NVHG_FUNC_POWERCONTROL, (NvU32*) pInOutData, &outDataSize); + outStatus = osCallACPI_DSM(pGpu, ACPI_DSM_FUNCTION_NVHG, NVHG_FUNC_POWERCONTROL, (NvU32*) pInOutData, &outDataSize); break; } case NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_DSM_PLATPOLICY: { - outStatus = pOS->osCallACPI_DSM(pGpu, ACPI_DSM_FUNCTION_NVHG, NVHG_FUNC_PLATPOLICY, (NvU32*) pInOutData, &outDataSize); + outStatus = osCallACPI_DSM(pGpu, ACPI_DSM_FUNCTION_NVHG, NVHG_FUNC_PLATPOLICY, (NvU32*) pInOutData, &outDataSize); break; } case NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_DSM_DISPLAYSTATUS: { if (pGpu->getProperty(pGpu, PDB_PROP_GPU_IS_MXM_3X)) - outStatus = pGpu->pOS->osCallACPI_DSM(pGpu, ACPI_DSM_FUNCTION_MXM, NV_ACPI_DSM_MXM_FUNC_MXDP, (NvU32*)pInOutData, &outDataSize); + outStatus = osCallACPI_DSM(pGpu, ACPI_DSM_FUNCTION_MXM, NV_ACPI_DSM_MXM_FUNC_MXDP, (NvU32*)pInOutData, &outDataSize); else - outStatus = pGpu->pOS->osCallACPI_DSM(pGpu, ACPI_DSM_FUNCTION_NVHG, NVHG_FUNC_DISPLAYSTATUS, (NvU32*)pInOutData, &outDataSize); + outStatus = osCallACPI_DSM(pGpu, ACPI_DSM_FUNCTION_NVHG, NVHG_FUNC_DISPLAYSTATUS, (NvU32*)pInOutData, &outDataSize); break; } case NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_DSM_MDTL: { if (pGpu->getProperty(pGpu, PDB_PROP_GPU_IS_MXM_3X)) - outStatus = pGpu->pOS->osCallACPI_DSM(pGpu, ACPI_DSM_FUNCTION_MXM, NV_ACPI_DSM_MXM_FUNC_MDTL, (NvU32*)pInOutData, &outDataSize); + outStatus = osCallACPI_DSM(pGpu, ACPI_DSM_FUNCTION_MXM, NV_ACPI_DSM_MXM_FUNC_MDTL, (NvU32*)pInOutData, &outDataSize); else - outStatus = pGpu->pOS->osCallACPI_DSM(pGpu, ACPI_DSM_FUNCTION_NVHG, NVHG_FUNC_MDTL, (NvU32*)pInOutData, &outDataSize); + outStatus = osCallACPI_DSM(pGpu, ACPI_DSM_FUNCTION_NVHG, NVHG_FUNC_MDTL, (NvU32*)pInOutData, &outDataSize); break; } case NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_DSM_HCSMBLIST: { - outStatus = pOS->osCallACPI_DSM(pGpu, ACPI_DSM_FUNCTION_NVHG, NVHG_FUNC_HCSMBLIST, (NvU32*) pInOutData, &outDataSize); + outStatus = osCallACPI_DSM(pGpu, ACPI_DSM_FUNCTION_NVHG, NVHG_FUNC_HCSMBLIST, (NvU32*) pInOutData, &outDataSize); break; } case NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_DSM_HCSMBADDR: { - outStatus = pOS->osCallACPI_DSM(pGpu, ACPI_DSM_FUNCTION_NVHG, NVHG_FUNC_HCSMBADDR, (NvU32*) pInOutData, &outDataSize); + outStatus = osCallACPI_DSM(pGpu, ACPI_DSM_FUNCTION_NVHG, NVHG_FUNC_HCSMBADDR, (NvU32*) pInOutData, &outDataSize); break; } case NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_DSM_HCREADBYTE: { - outStatus = pOS->osCallACPI_DSM(pGpu, ACPI_DSM_FUNCTION_NVHG, NVHG_FUNC_HCREADBYTE, (NvU32*) pInOutData, &outDataSize); + outStatus = osCallACPI_DSM(pGpu, ACPI_DSM_FUNCTION_NVHG, NVHG_FUNC_HCREADBYTE, (NvU32*) pInOutData, &outDataSize); break; } case NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_DSM_HCSENDBYTE: { - outStatus = pOS->osCallACPI_DSM(pGpu, ACPI_DSM_FUNCTION_NVHG, NVHG_FUNC_HCSENDBYTE, (NvU32*) pInOutData, &outDataSize); + outStatus = osCallACPI_DSM(pGpu, ACPI_DSM_FUNCTION_NVHG, NVHG_FUNC_HCSENDBYTE, (NvU32*) pInOutData, &outDataSize); break; } case NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_DSM_HCGETSTATUS: { - outStatus = pOS->osCallACPI_DSM(pGpu, ACPI_DSM_FUNCTION_NVHG, NVHG_FUNC_HCGETSTATUS, (NvU32*) pInOutData, &outDataSize); + outStatus = osCallACPI_DSM(pGpu, ACPI_DSM_FUNCTION_NVHG, NVHG_FUNC_HCGETSTATUS, (NvU32*) pInOutData, &outDataSize); break; } case NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_DSM_HCTRIGDDC: { - outStatus = pOS->osCallACPI_DSM(pGpu, ACPI_DSM_FUNCTION_NVHG, NVHG_FUNC_HCTRIGDDC, (NvU32*) pInOutData, &outDataSize); + outStatus = osCallACPI_DSM(pGpu, ACPI_DSM_FUNCTION_NVHG, NVHG_FUNC_HCTRIGDDC, (NvU32*) pInOutData, &outDataSize); break; } case NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_DSM_HCGETDDC: { - outStatus = pOS->osCallACPI_DSM(pGpu, ACPI_DSM_FUNCTION_NVHG, NVHG_FUNC_HCGETDDC, (NvU32*) pInOutData, &outDataSize); + outStatus = osCallACPI_DSM(pGpu, ACPI_DSM_FUNCTION_NVHG, NVHG_FUNC_HCGETDDC, (NvU32*) pInOutData, &outDataSize); break; } case NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_DSM_MXM_MXSS: { - outStatus = pOS->osCallACPI_DSM(pGpu, ACPI_DSM_FUNCTION_MXM, NV_ACPI_DSM_MXM_FUNC_MXSS, (NvU32*) pInOutData, &outDataSize); + outStatus = osCallACPI_DSM(pGpu, ACPI_DSM_FUNCTION_MXM, NV_ACPI_DSM_MXM_FUNC_MXSS, (NvU32*) pInOutData, &outDataSize); break; } case NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_DSM_MXM_MXMI: { - outStatus = pOS->osCallACPI_DSM(pGpu, ACPI_DSM_FUNCTION_MXM, NV_ACPI_DSM_MXM_FUNC_MXMI, (NvU32*) pInOutData, &outDataSize); + outStatus = osCallACPI_DSM(pGpu, ACPI_DSM_FUNCTION_MXM, NV_ACPI_DSM_MXM_FUNC_MXMI, (NvU32*) pInOutData, &outDataSize); break; } case NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_DSM_MXM_MXMS: { - outStatus = pOS->osCallACPI_DSM(pGpu, ACPI_DSM_FUNCTION_MXM, NV_ACPI_DSM_MXM_FUNC_MXMS, (NvU32*) pInOutData, &outDataSize); + outStatus = osCallACPI_DSM(pGpu, ACPI_DSM_FUNCTION_MXM, NV_ACPI_DSM_MXM_FUNC_MXMS, (NvU32*) pInOutData, &outDataSize); break; } case NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_DSM_MXM_MXPP: { - outStatus = pOS->osCallACPI_DSM(pGpu, ACPI_DSM_FUNCTION_MXM, NV_ACPI_DSM_MXM_FUNC_MXPP, (NvU32*) pInOutData, &outDataSize); + outStatus = osCallACPI_DSM(pGpu, ACPI_DSM_FUNCTION_MXM, NV_ACPI_DSM_MXM_FUNC_MXPP, (NvU32*) pInOutData, &outDataSize); break; } case NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_DSM_MXM_MXDP: { - outStatus = pOS->osCallACPI_DSM(pGpu, ACPI_DSM_FUNCTION_MXM, NV_ACPI_DSM_MXM_FUNC_MXDP, (NvU32*) pInOutData, &outDataSize); + outStatus = osCallACPI_DSM(pGpu, ACPI_DSM_FUNCTION_MXM, NV_ACPI_DSM_MXM_FUNC_MXDP, (NvU32*) pInOutData, &outDataSize); break; } case NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_DSM_MXM_MDTL: { - outStatus = pOS->osCallACPI_DSM(pGpu, ACPI_DSM_FUNCTION_MXM, NV_ACPI_DSM_MXM_FUNC_MDTL, (NvU32*) pInOutData, &outDataSize); + outStatus = osCallACPI_DSM(pGpu, ACPI_DSM_FUNCTION_MXM, NV_ACPI_DSM_MXM_FUNC_MDTL, (NvU32*) pInOutData, &outDataSize); break; } case NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_DSM_MXM_MXCB: @@ -551,27 +594,27 @@ } case NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_DSM_MXM_GETEVENTLIST: { - outStatus = pOS->osCallACPI_DSM(pGpu, ACPI_DSM_FUNCTION_MXM, NV_ACPI_DSM_MXM_FUNC_GETEVENTLIST, (NvU32*) pInOutData, &outDataSize); + outStatus = osCallACPI_DSM(pGpu, ACPI_DSM_FUNCTION_MXM, NV_ACPI_DSM_MXM_FUNC_GETEVENTLIST, (NvU32*) pInOutData, &outDataSize); break; } case NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_DSM_GETMEMTABLE: { - outStatus = pOS->osCallACPI_DSM(pGpu, ACPI_DSM_FUNCTION_NVHG, NVHG_FUNC_GETMEMTABLE, (NvU32*) pInOutData, &outDataSize); + outStatus = osCallACPI_DSM(pGpu, ACPI_DSM_FUNCTION_NVHG, NVHG_FUNC_GETMEMTABLE, (NvU32*) pInOutData, &outDataSize); break; } case NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_DSM_GETMEMCFG: { - outStatus = pOS->osCallACPI_DSM(pGpu, ACPI_DSM_FUNCTION_NVHG, NVHG_FUNC_GETMEMCFG, (NvU32*) pInOutData, &outDataSize); + outStatus = osCallACPI_DSM(pGpu, ACPI_DSM_FUNCTION_NVHG, NVHG_FUNC_GETMEMCFG, (NvU32*) pInOutData, &outDataSize); break; } case NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_DSM_GETOBJBYTYPE: { - outStatus = pOS->osCallACPI_DSM(pGpu, ACPI_DSM_FUNCTION_NVHG, NVHG_FUNC_GETOBJBYTYPE, (NvU32*) pInOutData, &outDataSize); + outStatus = osCallACPI_DSM(pGpu, ACPI_DSM_FUNCTION_NVHG, NVHG_FUNC_GETOBJBYTYPE, (NvU32*) pInOutData, &outDataSize); break; } case NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_DSM_GETALLOBJS: { - outStatus = pOS->osCallACPI_DSM(pGpu, ACPI_DSM_FUNCTION_NVHG, NVHG_FUNC_GETALLOBJS, (NvU32*) pInOutData, &outDataSize); + outStatus = osCallACPI_DSM(pGpu, ACPI_DSM_FUNCTION_NVHG, NVHG_FUNC_GETALLOBJS, (NvU32*) pInOutData, &outDataSize); break; } case NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_DSM_GENERIC_CTL_GETSUPPORTEDFUNC: @@ -586,106 +629,106 @@ } case NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_DSM_GENERIC_DISPLAYSTATUS: { - outStatus = pOS->osCallACPI_DSM(pGpu, - pGpu->acpi.dsmCurrentFunc[NV_ACPI_GENERIC_FUNC_DISPLAYSTATUS-NV_ACPI_GENERIC_FUNC_START], - pGpu->acpi.dsmCurrentSubFunc[NV_ACPI_GENERIC_FUNC_DISPLAYSTATUS-NV_ACPI_GENERIC_FUNC_START], - (NvU32*) pInOutData, - &outDataSize); + outStatus = osCallACPI_DSM(pGpu, + pGpu->acpi.dsmCurrentFunc[NV_ACPI_GENERIC_FUNC_DISPLAYSTATUS-NV_ACPI_GENERIC_FUNC_START], + pGpu->acpi.dsmCurrentSubFunc[NV_ACPI_GENERIC_FUNC_DISPLAYSTATUS-NV_ACPI_GENERIC_FUNC_START], + (NvU32*) pInOutData, + &outDataSize); break; } case NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_DSM_GENERIC_MDTL: { - outStatus = pOS->osCallACPI_DSM(pGpu, - pGpu->acpi.dsmCurrentFunc[NV_ACPI_GENERIC_FUNC_MDTL-NV_ACPI_GENERIC_FUNC_START], - pGpu->acpi.dsmCurrentSubFunc[NV_ACPI_GENERIC_FUNC_MDTL-NV_ACPI_GENERIC_FUNC_START], - (NvU32*) pInOutData, - &outDataSize); + outStatus = osCallACPI_DSM(pGpu, + pGpu->acpi.dsmCurrentFunc[NV_ACPI_GENERIC_FUNC_MDTL-NV_ACPI_GENERIC_FUNC_START], + pGpu->acpi.dsmCurrentSubFunc[NV_ACPI_GENERIC_FUNC_MDTL-NV_ACPI_GENERIC_FUNC_START], + (NvU32*) pInOutData, + &outDataSize); break; } case NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_DSM_GENERIC_MSTL: { - outStatus = pOS->osCallACPI_DSM(pGpu, - pGpu->acpi.dsmCurrentFunc[NV_ACPI_GENERIC_FUNC_MSTL-NV_ACPI_GENERIC_FUNC_START], - pGpu->acpi.dsmCurrentSubFunc[NV_ACPI_GENERIC_FUNC_MSTL-NV_ACPI_GENERIC_FUNC_START], - (NvU32*) pInOutData, - &outDataSize); + outStatus = osCallACPI_DSM(pGpu, + pGpu->acpi.dsmCurrentFunc[NV_ACPI_GENERIC_FUNC_MSTL-NV_ACPI_GENERIC_FUNC_START], + pGpu->acpi.dsmCurrentSubFunc[NV_ACPI_GENERIC_FUNC_MSTL-NV_ACPI_GENERIC_FUNC_START], + (NvU32*) pInOutData, + &outDataSize); break; } case NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_DSM_GENERIC_GETOBJBYTYPE: { - outStatus = pOS->osCallACPI_DSM(pGpu, - pGpu->acpi.dsmCurrentFunc[NV_ACPI_GENERIC_FUNC_GETOBJBYTYPE-NV_ACPI_GENERIC_FUNC_START], - pGpu->acpi.dsmCurrentSubFunc[NV_ACPI_GENERIC_FUNC_GETOBJBYTYPE-NV_ACPI_GENERIC_FUNC_START], - (NvU32*) pInOutData, - &outDataSize); + outStatus = osCallACPI_DSM(pGpu, + pGpu->acpi.dsmCurrentFunc[NV_ACPI_GENERIC_FUNC_GETOBJBYTYPE-NV_ACPI_GENERIC_FUNC_START], + pGpu->acpi.dsmCurrentSubFunc[NV_ACPI_GENERIC_FUNC_GETOBJBYTYPE-NV_ACPI_GENERIC_FUNC_START], + (NvU32*) pInOutData, + &outDataSize); break; } case NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_DSM_GENERIC_GETALLOBJS: { - outStatus = pOS->osCallACPI_DSM(pGpu, - pGpu->acpi.dsmCurrentFunc[NV_ACPI_GENERIC_FUNC_GETALLOBJS-NV_ACPI_GENERIC_FUNC_START], - pGpu->acpi.dsmCurrentSubFunc[NV_ACPI_GENERIC_FUNC_GETALLOBJS-NV_ACPI_GENERIC_FUNC_START], - (NvU32*) pInOutData, - &outDataSize); + outStatus = osCallACPI_DSM(pGpu, + pGpu->acpi.dsmCurrentFunc[NV_ACPI_GENERIC_FUNC_GETALLOBJS-NV_ACPI_GENERIC_FUNC_START], + pGpu->acpi.dsmCurrentSubFunc[NV_ACPI_GENERIC_FUNC_GETALLOBJS-NV_ACPI_GENERIC_FUNC_START], + (NvU32*) pInOutData, + &outDataSize); break; } case NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_DSM_GENERIC_GETEVENTLIST: { - outStatus = pOS->osCallACPI_DSM(pGpu, - pGpu->acpi.dsmCurrentFunc[NV_ACPI_GENERIC_FUNC_GETEVENTLIST-NV_ACPI_GENERIC_FUNC_START], - pGpu->acpi.dsmCurrentSubFunc[NV_ACPI_GENERIC_FUNC_GETEVENTLIST-NV_ACPI_GENERIC_FUNC_START], - (NvU32*) pInOutData, - &outDataSize); + outStatus = osCallACPI_DSM(pGpu, + pGpu->acpi.dsmCurrentFunc[NV_ACPI_GENERIC_FUNC_GETEVENTLIST-NV_ACPI_GENERIC_FUNC_START], + pGpu->acpi.dsmCurrentSubFunc[NV_ACPI_GENERIC_FUNC_GETEVENTLIST-NV_ACPI_GENERIC_FUNC_START], + (NvU32*) pInOutData, + &outDataSize); break; } case NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_DSM_GENERIC_GETBACKLIGHT: { - outStatus = pOS->osCallACPI_DSM(pGpu, - pGpu->acpi.dsmCurrentFunc[NV_ACPI_GENERIC_FUNC_GETBACKLIGHT-NV_ACPI_GENERIC_FUNC_START], - pGpu->acpi.dsmCurrentSubFunc[NV_ACPI_GENERIC_FUNC_GETBACKLIGHT-NV_ACPI_GENERIC_FUNC_START], - (NvU32*) pInOutData, - &outDataSize); + outStatus = osCallACPI_DSM(pGpu, + pGpu->acpi.dsmCurrentFunc[NV_ACPI_GENERIC_FUNC_GETBACKLIGHT-NV_ACPI_GENERIC_FUNC_START], + pGpu->acpi.dsmCurrentSubFunc[NV_ACPI_GENERIC_FUNC_GETBACKLIGHT-NV_ACPI_GENERIC_FUNC_START], + (NvU32*) pInOutData, + &outDataSize); break; } case NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_DSM_GENERIC_GETCALLBACKS: { - outStatus = pOS->osCallACPI_DSM(pGpu, - pGpu->acpi.dsmCurrentFunc[NV_ACPI_GENERIC_FUNC_CALLBACKS-NV_ACPI_GENERIC_FUNC_START], - pGpu->acpi.dsmCurrentSubFunc[NV_ACPI_GENERIC_FUNC_CALLBACKS-NV_ACPI_GENERIC_FUNC_START], - (NvU32*) pInOutData, - &outDataSize); + outStatus = osCallACPI_DSM(pGpu, + pGpu->acpi.dsmCurrentFunc[NV_ACPI_GENERIC_FUNC_CALLBACKS-NV_ACPI_GENERIC_FUNC_START], + pGpu->acpi.dsmCurrentSubFunc[NV_ACPI_GENERIC_FUNC_CALLBACKS-NV_ACPI_GENERIC_FUNC_START], + (NvU32*) pInOutData, + &outDataSize); break; } case NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_DSM_NBCI_SUPPORTFUNCS: { - outStatus = pOS->osCallACPI_DSM(pGpu, - ACPI_DSM_FUNCTION_NBCI, - NV_NBCI_FUNC_SUPPORT, - (NvU32*) pInOutData, - &outDataSize); + outStatus = osCallACPI_DSM(pGpu, + ACPI_DSM_FUNCTION_NBCI, + NV_NBCI_FUNC_SUPPORT, + (NvU32*) pInOutData, + &outDataSize); break; } case NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_DSM_NBCI_PLATCAPS: { - outStatus = pOS->osCallACPI_DSM(pGpu, - ACPI_DSM_FUNCTION_NBCI, - NV_NBCI_FUNC_PLATCAPS, - (NvU32*) pInOutData, - &outDataSize); + outStatus = osCallACPI_DSM(pGpu, + ACPI_DSM_FUNCTION_NBCI, + NV_NBCI_FUNC_PLATCAPS, + (NvU32*) pInOutData, + &outDataSize); break; } case NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_DSM_NBCI_PLATPOLICY: { - outStatus = pOS->osCallACPI_DSM(pGpu, - ACPI_DSM_FUNCTION_NBCI, - NV_NBCI_FUNC_PLATPOLICY, - (NvU32*) pInOutData, - &outDataSize); + outStatus = osCallACPI_DSM(pGpu, + ACPI_DSM_FUNCTION_NBCI, + NV_NBCI_FUNC_PLATPOLICY, + (NvU32*) pInOutData, + &outDataSize); break; } case NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_WMMX_NVOP_GPUON: { - outStatus = pOS->osCallACPI_OPTM_GPUON(pGpu); + outStatus = osCallACPI_OPTM_GPUON(pGpu); break; } default: diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/kernel/gpu/disp/disp_common_kern_ctrl_minimal.c nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/kernel/gpu/disp/disp_common_kern_ctrl_minimal.c --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/kernel/gpu/disp/disp_common_kern_ctrl_minimal.c 2023-10-25 20:20:56.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/kernel/gpu/disp/disp_common_kern_ctrl_minimal.c 2024-03-05 22:13:20.000000000 +0000 @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 2020-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2020-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -116,6 +116,7 @@ staticCast(pDispCommon, DisplayApi), DISPAPI_GET_GPUGRP(pDispCommon), &pGpu, + NULL, pParams->subDeviceInstance); if (status != NV_OK) { @@ -147,6 +148,7 @@ staticCast(pDispCommon, DisplayApi), DISPAPI_GET_GPUGRP(pDispCommon), &pGpu, + NULL, pParams->subDeviceInstance); if (status != NV_OK) { @@ -208,3 +210,57 @@ return NV_OK; } + +NV_STATUS dispcmnCtrlCmdVRRSetRgLineActive_IMPL +( + DispCommon *pDispCommon, + NV0073_CTRL_CMD_SYSTEM_VRR_SET_RGLINE_ACTIVE_PARAMS *pParams +) +{ + POBJGPU pGpu = DISPAPI_GET_GPU(pDispCommon); + NvHandle hClient = RES_GET_CLIENT_HANDLE(pDispCommon); + NvHandle hParent = RES_GET_PARENT_HANDLE(pDispCommon); + RM_API *pRmApi = GPU_GET_PHYSICAL_RMAPI(DISPAPI_GET_GPU(pDispCommon)); + NV_STATUS status = NV_OK; + + // Get the right pGpu from subdevice instance given by client + status = dispapiSetUnicastAndSynchronize_HAL( + staticCast(pDispCommon, DisplayApi), + DISPAPI_GET_GPUGRP(pDispCommon), + &pGpu, + NULL, + pParams->subDeviceInstance); + + if (status != NV_OK) + { + return status; + } + + if (pParams->bEnable) + { + status = memdescRegisterToGSP(pGpu, hClient, hParent, pParams->hMemory); + if (status != NV_OK) + { + NV_PRINTF(LEVEL_ERROR, "memdescRegisterToGSP failed %d\n", status); + return status; + } + } + + status = pRmApi->Control(pRmApi, + hClient, + RES_GET_HANDLE(pDispCommon), + NV0073_CTRL_CMD_INTERNAL_VRR_SET_RGLINE_ACTIVE, + pParams, + sizeof(*pParams)); + + if (!pParams->bEnable) + { + status = memdescDeregisterFromGSP(pGpu, hClient, hParent, pParams->hMemory); + if (status != NV_OK) + { + NV_PRINTF(LEVEL_ERROR, "memdescDeRegisterFromGSP failed %d\n", status); + } + } + + return status; +} diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/kernel/gpu/disp/disp_object_kern_ctrl_minimal.c nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/kernel/gpu/disp/disp_object_kern_ctrl_minimal.c --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/kernel/gpu/disp/disp_object_kern_ctrl_minimal.c 2023-10-25 20:20:56.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/kernel/gpu/disp/disp_object_kern_ctrl_minimal.c 2024-03-05 22:13:20.000000000 +0000 @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 2021 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2021-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -23,12 +23,17 @@ #define RM_STRICT_CONFIG_EMIT_DISP_ENGINE_DEFINITIONS 0 -#include "gpu/disp/kern_disp.h" -#include "gpu/disp/disp_objs.h" #include "class/cl5070.h" -#include "mem_mgr/mem.h" +#include "gpu/device/device.h" +#include "gpu/disp/disp_objs.h" +#include "gpu/disp/kern_disp.h" #include "gpu/gpu.h" +#include "gpu/subdevice/subdevice.h" #include "gpu_mgr/gpu_mgr.h" +#include "mem_mgr/mem.h" +#include "rmapi/client_resource.h" +#include "rmapi/rmapi.h" +#include "rmapi/rs_utils.h" NV_STATUS dispobjCtrlCmdEventSetTrigger_IMPL @@ -96,3 +101,100 @@ return NV_OK; } + +static NV_STATUS getRgConnectedLockpin(OBJGPU *pGpu, + KernelDisplay *pKernelDisplay, NvU32 head, + OBJGPU *pPeerGpu, NvU32 peerHead, + NvU32 *pMasterScanLock, NvU32 *pSlaveScanLock) +{ + NvBool bMasterScanLock, bSlaveScanLock; + NvU32 masterScanLockPin, slaveScanLockPin; + + *pMasterScanLock = 0; + *pSlaveScanLock = 0; + + NV_STATUS status = kdispGetRgScanLock_HAL(pGpu, pKernelDisplay, + head, + pPeerGpu, + peerHead, + &bMasterScanLock, + &masterScanLockPin, + &bSlaveScanLock, + &slaveScanLockPin); + NV_ASSERT_OK_OR_RETURN(status); + + if (bMasterScanLock) + { + *pMasterScanLock = + FLD_SET_DRF(5070, _CTRL_CMD_GET_RG_CONNECTED_LOCKPIN_STATELESS, + _MASTER_SCAN_LOCK_CONNECTED, _YES, *pMasterScanLock); + + *pMasterScanLock = + FLD_SET_DRF_NUM(5070, _CTRL_CMD_GET_RG_CONNECTED_LOCKPIN_STATELESS, + _MASTER_SCAN_LOCK_PIN, masterScanLockPin, + *pMasterScanLock); + } + else + { + *pMasterScanLock = + FLD_SET_DRF(5070, _CTRL_CMD_GET_RG_CONNECTED_LOCKPIN_STATELESS, + _MASTER_SCAN_LOCK_CONNECTED, _NO, *pMasterScanLock); + } + + if (bSlaveScanLock) + { + *pSlaveScanLock = + FLD_SET_DRF(5070, _CTRL_CMD_GET_RG_CONNECTED_LOCKPIN_STATELESS, + _SLAVE_SCAN_LOCK_CONNECTED, _YES, *pSlaveScanLock); + + *pSlaveScanLock = + FLD_SET_DRF_NUM(5070, _CTRL_CMD_GET_RG_CONNECTED_LOCKPIN_STATELESS, + _SLAVE_SCAN_LOCK_PIN, slaveScanLockPin, + *pSlaveScanLock); + } + else + { + *pSlaveScanLock = + FLD_SET_DRF(5070, _CTRL_CMD_GET_RG_CONNECTED_LOCKPIN_STATELESS, + _SLAVE_SCAN_LOCK_CONNECTED, _NO, *pSlaveScanLock); + } + + return NV_OK; +} + +NV_STATUS +dispobjCtrlCmdGetRgConnectedLockpinStateless_IMPL +( + DispObject *pDispObject, + NV5070_CTRL_GET_RG_CONNECTED_LOCKPIN_STATELESS_PARAMS *pParams +) +{ + OBJGPU *pGpu = DISPAPI_GET_GPU(pDispObject); + KernelDisplay *pKernelDisplay = GPU_GET_KERNEL_DISPLAY(pGpu); + NvHandle hClient = RES_GET_CLIENT_HANDLE(pDispObject); + DisplayApi *pDisplayApi; + OBJGPU *pPeerGpu; + + NV_ASSERT_OR_RETURN(pParams->head < pKernelDisplay->numHeads, NV_ERR_INVALID_ARGUMENT); + + if (!CliGetDispInfo(hClient, pParams->peer.hDisplay, &pDisplayApi) && + !CliGetDispCommonInfo(hClient, pParams->peer.hDisplay, &pDisplayApi)) + { + return NV_ERR_INVALID_OBJECT_HANDLE; + } + + RsResourceRef *pPeerDisplayRef; + NV_ASSERT_OK_OR_RETURN(serverutilGetResourceRef(hClient, pParams->peer.hDisplay, &pPeerDisplayRef)); + NV_ASSERT_OR_RETURN(pPeerDisplayRef->pParentRef != NULL, NV_ERR_INVALID_STATE); + + Subdevice *pPeerSubdevice; + NV_ASSERT_OK_OR_RETURN(subdeviceGetByInstance(RES_GET_CLIENT(pDispObject), pPeerDisplayRef->pParentRef->hResource, + pParams->peer.subdeviceIndex, &pPeerSubdevice)); + pPeerGpu = GPU_RES_GET_GPU(pPeerSubdevice); + + NV_ASSERT_OR_RETURN(pPeerGpu != NULL, NV_ERR_INVALID_ARGUMENT); + NV_ASSERT_OR_RETURN(pParams->peer.head < GPU_GET_KERNEL_DISPLAY(pPeerGpu)->numHeads, NV_ERR_INVALID_ARGUMENT); + + return getRgConnectedLockpin(pGpu, pKernelDisplay, pParams->head, pPeerGpu, pParams->peer.head, + &pParams->masterScanLock, &pParams->slaveScanLock); +} diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/kernel/gpu/disp/disp_objs.c nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/kernel/gpu/disp/disp_objs.c --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/kernel/gpu/disp/disp_objs.c 2023-10-25 20:20:56.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/kernel/gpu/disp/disp_objs.c 2024-03-05 22:13:20.000000000 +0000 @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 1993-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 1993-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -225,6 +225,13 @@ "Failure allocating display class 0x%08x: Only root(admin)/kernel clients are allowed\n", pParams->externalClassId); + // + // GPUSWSEC-1560 introduced a central object privilege check in RS. Please mark derived external classes + // of DispObject privileged in their RS_ENTRY. Since DispObject doesn't have an external class of its own + // and is used as a base class, leaving this check inline to catch future derivations. + // + osAssertFailed(); + return NV_ERR_INSUFFICIENT_PERMISSIONS; } @@ -282,6 +289,7 @@ DisplayApi *pDisplayApi, OBJGPUGRP *pGpuGroup, OBJGPU **ppGpu, + OBJDISP **ppDisp, NvU32 subDeviceInstance ) { @@ -293,6 +301,19 @@ gpumgrSetBcEnabledStatus(*ppGpu, NV_FALSE); + // + // The _KERNEL version of this function is only called from Kernel RM, but + // in Kernel RM, OBJDISP is not available, so ppDisp must be NULL. If the + // caller needs to access OBJDISP, either the caller code must remove the + // OBJDISP dependency, or the caller code must be changed so that + // dispapiSetUnicastAndSynchronize is called only from physical or + // monolithic RM, never Kernel RM. + // + if (ppDisp != NULL) + { + return NV_ERR_INVALID_STATE; + } + return nvStatus; } @@ -368,6 +389,7 @@ status = dispapiSetUnicastAndSynchronize_HAL(pDisplayApi, pRmCtrlParams->pGpuGrp, &pRmCtrlParams->pGpu, + NULL, subdeviceIndex); if (status == NV_OK) @@ -450,14 +472,6 @@ RS_RES_ALLOC_PARAMS_INTERNAL *pParams ) { - if (pParams->pSecInfo->privLevel < RS_PRIV_LEVEL_USER_ROOT) - { - NV_PRINTF(LEVEL_ERROR, - "Failure allocating display class 0x%08x: Only root(admin)/kernel clients are allowed\n", - pParams->externalClassId); - - return NV_ERR_INSUFFICIENT_PERMISSIONS; - } return NV_OK; } @@ -470,7 +484,7 @@ ) { DisplayApi *pDisplayApi = staticCast(pDispCommon, DisplayApi); - + // // Not adding the priv-level check for this class // as it is being used by OpenGL from userspace.Once the Cleanup is done from the OpenGL diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/kernel/gpu/disp/disp_sf_user.c nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/kernel/gpu/disp/disp_sf_user.c --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/kernel/gpu/disp/disp_sf_user.c 2023-10-25 20:20:56.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/kernel/gpu/disp/disp_sf_user.c 2024-03-05 22:13:20.000000000 +0000 @@ -47,15 +47,6 @@ OBJGPU *pGpu = GPU_RES_GET_GPU(pDispSfUser); KernelDisplay *pKernelDisplay = GPU_GET_KERNEL_DISPLAY(pGpu); - if (pParams->pSecInfo->privLevel < RS_PRIV_LEVEL_USER_ROOT) - { - NV_PRINTF(LEVEL_ERROR, - "Failure allocating display class 0x%08x: Only root(admin)/kernel clients are allowed\n", - pParams->externalClassId); - - return NV_ERR_INSUFFICIENT_PERMISSIONS; - } - NV_CHECK_OR_RETURN(LEVEL_ERROR, pKernelDisplay != NULL, NV_ERR_NOT_SUPPORTED); // Set sf user RegBase offset diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/kernel/gpu/disp/head/arch/v04/kernel_head_0400.c nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/kernel/gpu/disp/head/arch/v04/kernel_head_0400.c --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/kernel/gpu/disp/head/arch/v04/kernel_head_0400.c 1970-01-01 00:00:00.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/kernel/gpu/disp/head/arch/v04/kernel_head_0400.c 2024-03-05 22:13:20.000000000 +0000 @@ -0,0 +1,107 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#include "gpu/disp/head/kernel_head.h" +#include "published/disp/v04_00/dev_disp.h" + +void kheadResetPendingVblank_KERNEL(OBJGPU *pGpu, KernelHead *pKernelHead, THREAD_STATE_NODE *pThreadState) +{ + NvU32 writeIntr = GPU_REG_RD32(pGpu, NV_PDISP_FE_EVT_STAT_HEAD_TIMING(pKernelHead->PublicId)); + + writeIntr = DRF_DEF(_PDISP, _FE_EVT_STAT_HEAD_TIMING, _LAST_DATA, _RESET); + + GPU_REG_WR32(pGpu, NV_PDISP_FE_EVT_STAT_HEAD_TIMING(pKernelHead->PublicId), writeIntr); +} + +NvBool kheadReadPendingVblank_KERNEL(OBJGPU *pGpu, KernelHead *pKernelHead, NvU32 *pCachedIntr, THREAD_STATE_NODE *pThreadState) +{ + NvU32 intr = GPU_REG_RD32(pGpu, NV_PDISP_FE_RM_INTR_DISPATCH); + + if (!FLD_IDX_TEST_DRF(_PDISP, _FE_RM_INTR_DISPATCH, _HEAD_TIMING, pKernelHead->PublicId, _PENDING, intr)) + { + return NV_FALSE; + } + + intr = GPU_REG_RD32(pGpu, NV_PDISP_FE_RM_INTR_STAT_HEAD_TIMING(pKernelHead->PublicId)); + + if (FLD_TEST_DRF(_PDISP, _FE_EVT_STAT_HEAD_TIMING, _LAST_DATA, _PENDING, intr)) + { + return NV_TRUE; + } + + return NV_FALSE; +} + +NvBool kheadGetDisplayInitialized_KERNEL +( + OBJGPU *pGpu, + KernelHead *pKernelHead +) +{ + NvU32 intr = GPU_REG_RD32(pGpu, NV_PDISP_FE_CORE_HEAD_STATE(pKernelHead->PublicId)); + + if (DRF_VAL(_PDISP, _FE_CORE_HEAD_STATE, _OPERATING_MODE, intr)) + { + return NV_TRUE; + } + + return NV_FALSE; +} + +NvBool kheadReadVblankIntrEnable_KERNEL +( + OBJGPU *pGpu, + KernelHead *pKernelHead +) +{ + NvU32 intr = GPU_REG_RD32(pGpu, NV_PDISP_FE_RM_INTR_EN_HEAD_TIMING(pKernelHead->PublicId)); + if (FLD_TEST_DRF(_PDISP, _FE_RM_INTR_EN_HEAD_TIMING, _LAST_DATA, _ENABLE, intr)) + { + return NV_TRUE; + } + + return NV_FALSE; +} + +void kheadWriteVblankIntrEnable_KERNEL +( + OBJGPU *pGpu, + KernelHead *pKernelHead, + NvBool bEnable +) +{ + NvU32 intrEn = GPU_REG_RD32(pGpu, NV_PDISP_FE_RM_INTR_EN_HEAD_TIMING(pKernelHead->PublicId)); + + kheadResetPendingVblank_HAL(pGpu, pKernelHead, NULL); + + if (bEnable) + { + intrEn = FLD_SET_DRF(_PDISP, _FE_RM_INTR_EN_HEAD_TIMING, _LAST_DATA, _ENABLE, intrEn); + } + else + { + intrEn = FLD_SET_DRF(_PDISP, _FE_RM_INTR_EN_HEAD_TIMING, _LAST_DATA, _DISABLE, intrEn); + } + + GPU_REG_WR32(pGpu, NV_PDISP_FE_RM_INTR_EN_HEAD_TIMING(pKernelHead->PublicId), intrEn); +} diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/kernel/gpu/disp/head/arch/v04/kernel_head_gpu_0400.c nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/kernel/gpu/disp/head/arch/v04/kernel_head_gpu_0400.c --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/kernel/gpu/disp/head/arch/v04/kernel_head_gpu_0400.c 2023-10-25 20:20:56.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/kernel/gpu/disp/head/arch/v04/kernel_head_gpu_0400.c 1970-01-01 00:00:00.000000000 +0000 @@ -1,59 +0,0 @@ -/* - * SPDX-FileCopyrightText: Copyright (c) 2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. - * SPDX-License-Identifier: MIT - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER - * DEALINGS IN THE SOFTWARE. - */ - -#include "gpu/disp/head/kernel_head.h" -#include "published/disp/v04_00/dev_disp.h" - -void kheadResetPendingVblank_v04_00_KERNEL(OBJGPU *pGpu, KernelHead *pKernelHead, THREAD_STATE_NODE *pThreadState) -{ - NvU32 writeIntr = 0; - - writeIntr = DRF_DEF(_PDISP, _FE_EVT_STAT_HEAD_TIMING, _LAST_DATA, _RESET); - - GPU_REG_WR32(pGpu, NV_PDISP_FE_EVT_STAT_HEAD_TIMING(pKernelHead->PublicId), writeIntr); -} - -NvU32 kheadReadPendingVblank_v04_00_KERNEL(OBJGPU *pGpu, KernelHead *pKernelHead, NvU32 headIntrMask) -{ - - NvU32 intr = GPU_REG_RD32(pGpu, NV_PDISP_FE_RM_INTR_DISPATCH); - - if (!FLD_IDX_TEST_DRF(_PDISP, _FE_RM_INTR_DISPATCH, _HEAD_TIMING, pKernelHead->PublicId, _PENDING, intr)) - { - return headIntrMask; - } - - intr = GPU_REG_RD32(pGpu, NV_PDISP_FE_RM_INTR_STAT_HEAD_TIMING(pKernelHead->PublicId)); - - if (FLD_TEST_DRF(_PDISP, _FE_EVT_STAT_HEAD_TIMING, _LAST_DATA, _PENDING, intr)) - { - headIntrMask |= headIntr_vblank; - } - if (headIntrMask & headIntr_vblank) - { - return NVBIT(pKernelHead->PublicId); - } - - return headIntr_none; -} - diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/kernel/gpu/disp/head/kernel_head.c nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/kernel/gpu/disp/head/kernel_head.c --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/kernel/gpu/disp/head/kernel_head.c 2023-10-25 20:20:56.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/kernel/gpu/disp/head/kernel_head.c 2024-03-05 22:13:21.000000000 +0000 @@ -25,9 +25,10 @@ #include "gpu/disp/head/kernel_head.h" #include "objtmr.h" -NV_STATUS +NV_STATUS kheadConstruct_IMPL(KernelHead *pKernelHead) { + pKernelHead->Vblank.IntrState = NV_HEAD_VBLANK_INTR_UNAVAILABLE; return NV_OK; } @@ -215,7 +216,7 @@ { if (kheadIsVblankCallbackDue(pCallback, state, time, vblankCount)) { - *expiring |= VBLANK_STATE_PROCESS_NORMAL_LATENCY; + *expiring |= VBLANK_STATE_PROCESS_NORMAL_LATENCY; } pCallback = pCallback->Next; @@ -239,10 +240,6 @@ // HW is enabled, check if SW state is not enabled if (pKernelHead->Vblank.IntrState != NV_HEAD_VBLANK_INTR_ENABLED) { - NV_PRINTF(LEVEL_ERROR, - "Head %d: HW: %d != SW: %d! Fixing SW State...\n", - pKernelHead->PublicId, NV_HEAD_VBLANK_INTR_ENABLED, - pKernelHead->Vblank.IntrState); pKernelHead->Vblank.IntrState = NV_HEAD_VBLANK_INTR_ENABLED; } } @@ -272,9 +269,6 @@ if (state != pKernelHead->Vblank.IntrState) { - NV_PRINTF(LEVEL_ERROR, - "Head %d: HW: %d != SW: %d! Fixing SW State...\n", - pKernelHead->PublicId, state, pKernelHead->Vblank.IntrState); pKernelHead->Vblank.IntrState = state; } } @@ -286,9 +280,6 @@ // if (!kheadGetDisplayInitialized_HAL(pGpu, pKernelHead)) { - NV_PRINTF(LEVEL_ERROR, - "Head %d: HW: %d != SW: %d! Fixing SW State...\n", - pKernelHead->PublicId, NV_HEAD_VBLANK_INTR_UNAVAILABLE, pKernelHead->Vblank.IntrState); pKernelHead->Vblank.IntrState = NV_HEAD_VBLANK_INTR_UNAVAILABLE; } } diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/kernel/gpu/disp/kern_disp.c nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/kernel/gpu/disp/kern_disp.c --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/kernel/gpu/disp/kern_disp.c 2023-10-25 20:20:57.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/kernel/gpu/disp/kern_disp.c 2024-03-05 22:13:21.000000000 +0000 @@ -46,19 +46,19 @@ #include "core/locks.h" #include "ctrl/ctrl402c.h" #include "platform/acpi_common.h" +#include "nvrm_registry.h" #include "kernel/gpu/intr/engine_idx.h" +#include "gpu/external_device/external_device.h" + #include "ctrl/ctrl2080.h" #include "class/cl5070.h" #include "class/cl917a.h" #include "class/cl917b.h" -#include "class/cl917c.h" -#include "class/cl917d.h" #include "class/cl917e.h" #include "class/cl927c.h" -#include "class/cl927d.h" #include "class/cl947d.h" #include "class/cl957d.h" #include "class/cl977d.h" @@ -81,6 +81,9 @@ #include "gpu/disp/rg_line_callback/rg_line_callback.h" +#include "rmapi/rmapi_utils.h" +#include "class/cl0073.h" + NV_STATUS kdispConstructEngine_IMPL(OBJGPU *pGpu, KernelDisplay *pKernelDisplay, @@ -208,6 +211,61 @@ } NV_STATUS +kdispAllocateCommonHandle_IMPL +( + OBJGPU *pGpu, + KernelDisplay *pKernelDisplay +) +{ + NV_STATUS rmStatus; + NvHandle hClient; + NvHandle hDevice; + NvHandle hSubdevice; + NvHandle hSubscription = NV01_NULL_OBJECT; + RM_API *pRmApi = rmapiGetInterface(RMAPI_GPU_LOCK_INTERNAL); + + rmStatus = rmapiutilAllocClientAndDeviceHandles(pRmApi, pGpu, &hClient, + &hDevice, &hSubdevice); + NV_ASSERT_OR_RETURN(rmStatus == NV_OK, NV_FALSE); + + rmStatus = pRmApi->AllocWithSecInfo(pRmApi, hClient, hDevice, &hSubscription, + NV04_DISPLAY_COMMON, NULL, 0, RMAPI_ALLOC_FLAGS_NONE, + NULL, &pRmApi->defaultSecInfo); + NV_ASSERT_OR_RETURN(rmStatus == NV_OK, NV_FALSE); + + pKernelDisplay->hInternalClient = hClient; + pKernelDisplay->hInternalDevice = hDevice; + pKernelDisplay->hInternalSubdevice = hSubdevice; + pKernelDisplay->hDispCommonHandle = hSubscription; + + return NV_OK; +} + +void +kdispDestroyCommonHandle_IMPL +( + KernelDisplay *pKernelDisplay +) +{ + NV_STATUS rmStatus; + RM_API *pRmApi = rmapiGetInterface(RMAPI_GPU_LOCK_INTERNAL); + + rmStatus = pRmApi->FreeWithSecInfo(pRmApi, pKernelDisplay->hInternalClient, + pKernelDisplay->hDispCommonHandle, + RMAPI_ALLOC_FLAGS_NONE, &pRmApi->defaultSecInfo); + NV_ASSERT(rmStatus == NV_OK); + + rmapiutilFreeClientAndDeviceHandles(pRmApi, &pKernelDisplay->hInternalClient, + &pKernelDisplay->hInternalDevice, + &pKernelDisplay->hInternalSubdevice); + + pKernelDisplay->hInternalClient = 0; + pKernelDisplay->hInternalDevice = 0; + pKernelDisplay->hInternalSubdevice = 0; + pKernelDisplay->hDispCommonHandle = 0; +} + +NV_STATUS kdispStatePreInitLocked_IMPL(OBJGPU *pGpu, KernelDisplay *pKernelDisplay) { @@ -219,7 +277,7 @@ if (!gpuFuseSupportsDisplay_HAL(pGpu)) return NV_ERR_NOT_SUPPORTED; - + status = pRmApi->Control(pRmApi, hClient, hSubdevice, NV2080_CTRL_CMD_INTERNAL_DISPLAY_GET_IP_VERSION, &ctrlParams, sizeof(ctrlParams)); @@ -234,6 +292,10 @@ // NOTE: KernelDisplay IpVersion _HAL functions can only be called after this point. status = gpuInitDispIpHal(pGpu, ctrlParams.ipVersion); + kdispInitRegistryOverrides_HAL(pGpu, pKernelDisplay); + + kdispAllocateCommonHandle(pGpu, pKernelDisplay); + return status; } @@ -258,9 +320,9 @@ { // Fill in the Backlight Method Data. pBrightcInfo->backLightDataSize = sizeof(pBrightcInfo->backLightData); - status = pGpu->pOS->osCallACPI_DSM(pGpu, ACPI_DSM_FUNCTION_CURRENT, NV_ACPI_GENERIC_FUNC_GETBACKLIGHT, - (NvU32 *)(pBrightcInfo->backLightData), - &pBrightcInfo->backLightDataSize); + status = osCallACPI_DSM(pGpu, ACPI_DSM_FUNCTION_CURRENT, NV_ACPI_GENERIC_FUNC_GETBACKLIGHT, + (NvU32 *)(pBrightcInfo->backLightData), + &pBrightcInfo->backLightDataSize); pBrightcInfo->status = status; } @@ -274,6 +336,78 @@ } NV_STATUS +kdispSetupAcpiEdid_IMPL +( + OBJGPU *pGpu, + KernelDisplay *pKernelDisplay +) +{ + NV2080_CTRL_CMD_INTERNAL_SET_STATIC_EDID_DATA_PARAMS *pEdidParams = NULL; + RM_API *pRmApi = GPU_GET_PHYSICAL_RMAPI(pGpu); + NvU32 status = NV_ERR_GENERIC; + NvU32 index; + + pEdidParams = portMemAllocNonPaged(sizeof(NV2080_CTRL_CMD_INTERNAL_SET_STATIC_EDID_DATA_PARAMS)); + if (pEdidParams == NULL) + { + NV_PRINTF(LEVEL_ERROR, "Could not allocate memory for pEdidParams\n"); + return NV_ERR_NO_MEMORY; + } + portMemSet(pEdidParams, 0, sizeof(*pEdidParams)); + + pEdidParams->tableLen = pGpu->acpiMethodData.dodMethodData.acpiIdListLen / sizeof(NvU32); + + for (index = 0; index < pEdidParams->tableLen; index++) + { + pEdidParams->edidTable[index].bufferSize = MAX_EDID_SIZE_FROM_SBIOS; + status = osCallACPI_DDC(pGpu, pGpu->acpiMethodData.dodMethodData.acpiIdList[index], + pEdidParams->edidTable[index].edidBuffer, + &pEdidParams->edidTable[index].bufferSize, NV_TRUE); + pEdidParams->edidTable[index].acpiId = pGpu->acpiMethodData.dodMethodData.acpiIdList[index]; + pEdidParams->edidTable[index].status = status; + } + + status = pRmApi->Control(pRmApi, pGpu->hInternalClient, pGpu->hInternalSubdevice, + NV2080_CTRL_CMD_INTERNAL_SET_STATIC_EDID_DATA, + pEdidParams, sizeof(*pEdidParams)); + + portMemFree(pEdidParams); + + return status; +} + +void +kdispInitRegistryOverrides_IMPL(OBJGPU *pGpu, + KernelDisplay *pKernelDisplay) +{ + NvU32 data32 = 0; + + if (pKernelDisplay == NULL) + { + return; + } + + if (NV_OK == osReadRegistryDword(pGpu, NV_REG_STR_RM_BUG_2089053_WAR, &data32)) + { + if (data32 == NV_REG_STR_RM_BUG_2089053_WAR_DISABLE) + { + pKernelDisplay->setProperty(pKernelDisplay, PDB_PROP_KDISP_BUG_2089053_SERIALIZE_AGGRESSIVE_VBLANK_ALWAYS, NV_FALSE); + pKernelDisplay->setProperty(pKernelDisplay, PDB_PROP_KDISP_BUG_2089053_SERIALIZE_AGGRESSIVE_VBLANKS_ONLY_ON_HMD_ACTIVE, NV_FALSE); + } + else if (data32 == NV_REG_STR_RM_BUG_2089053_WAR_ENABLE_ALWAYS) + { + pKernelDisplay->setProperty(pKernelDisplay, PDB_PROP_KDISP_BUG_2089053_SERIALIZE_AGGRESSIVE_VBLANK_ALWAYS, NV_TRUE); + pKernelDisplay->setProperty(pKernelDisplay, PDB_PROP_KDISP_BUG_2089053_SERIALIZE_AGGRESSIVE_VBLANKS_ONLY_ON_HMD_ACTIVE, NV_FALSE); + } + else if (data32 == NV_REG_STR_RM_BUG_2089053_WAR_ENABLE_ON_HMD_ACTIVE_ONLY) + { + pKernelDisplay->setProperty(pKernelDisplay, PDB_PROP_KDISP_BUG_2089053_SERIALIZE_AGGRESSIVE_VBLANKS_ONLY_ON_HMD_ACTIVE, NV_TRUE); + pKernelDisplay->setProperty(pKernelDisplay, PDB_PROP_KDISP_BUG_2089053_SERIALIZE_AGGRESSIVE_VBLANK_ALWAYS, NV_FALSE); + } + } +} + +NV_STATUS kdispStateInitLocked_IMPL(OBJGPU *pGpu, KernelDisplay *pKernelDisplay) { @@ -308,6 +442,14 @@ goto exit; } + // Set up ACPI DDC data in Physical RM for future usage + status = kdispSetupAcpiEdid_HAL(pGpu, pKernelDisplay); + if (status != NV_OK) + { + NV_PRINTF(LEVEL_WARNING, "rmapi control call for acpi child device init failed\n"); + goto exit; + } + if (pKernelDisplay->pInst != NULL) { NV_CHECK_OK_OR_GOTO(status, LEVEL_ERROR, @@ -350,6 +492,8 @@ kdispStateDestroy_IMPL(OBJGPU *pGpu, KernelDisplay *pKernelDisplay) { + extdevDestroy(pGpu); + if (pKernelDisplay->pInst != NULL) { instmemStateDestroy(pGpu, pKernelDisplay->pInst); @@ -357,6 +501,8 @@ portMemFree((void*) pKernelDisplay->pStaticInfo); pKernelDisplay->pStaticInfo = NULL; + + kdispDestroyCommonHandle(pKernelDisplay); } NV_STATUS @@ -410,7 +556,7 @@ simulationMode = osGetSimulationMode(); if (simulationMode == NV_SIM_MODE_TEGRA_FPGA) { - pKernelDisplay->setProperty(pDisp, PDB_PROP_KDISP_IMP_ENABLE, NV_FALSE); + pKernelDisplay->setProperty(pKernelDisplay, PDB_PROP_KDISP_IMP_ENABLE, NV_FALSE); return NV_OK; } @@ -449,13 +595,10 @@ *pDispChnClass = dispChnClass_Ovim; break; - case NV917C_BASE_CHANNEL_DMA: case NV927C_BASE_CHANNEL_DMA: *pDispChnClass = dispChnClass_Base; break; - case NV917D_CORE_CHANNEL_DMA: - case NV927D_CORE_CHANNEL_DMA: case NV947D_CORE_CHANNEL_DMA: case NV957D_CORE_CHANNEL_DMA: case NV977D_CORE_CHANNEL_DMA: @@ -906,7 +1049,10 @@ if (!unionNonEmptyQueues) { // all queues (belonging to heads with pending vblank ints) are empty. - kheadResetPendingVblankForKernel_HAL(pGpu, pKernelHead, pThreadState); + if (IS_GSP_CLIENT(pGpu)) + { + kheadResetPendingVblank_HAL(pGpu, pKernelHead, pThreadState); + } return; } @@ -945,7 +1091,10 @@ for(i=0; i< OBJ_MAX_HEADS; i++) { pKernelHead = KDISP_GET_HEAD(pKernelDisplay, i); - kheadResetPendingVblankForKernel_HAL(pGpu, pKernelHead, pThreadState); + if (IS_GSP_CLIENT(pGpu)) + { + kheadResetPendingVblank_HAL(pGpu, pKernelHead, pThreadState); + } } } else @@ -964,19 +1113,21 @@ return; } -NvU32 kdispReadPendingVblank_KERNEL(OBJGPU *pGpu, KernelDisplay *pKernelDisplay, THREAD_STATE_NODE *pThreadState) +NvU32 kdispReadPendingVblank_IMPL(OBJGPU *pGpu, KernelDisplay *pKernelDisplay, THREAD_STATE_NODE *pThreadState) { - KernelHead *pKernelHead; - NvU32 headIntrMask; - NvU32 pending = 0; - NvU8 headIdx; + KernelHead *pKernelHead; + NvU32 headIdx, pending = 0; - for(headIdx = 0; headIdx < OBJ_MAX_HEADS; headIdx++) + for (headIdx = 0; headIdx < kdispGetNumHeads(pKernelDisplay); headIdx++) { pKernelHead = KDISP_GET_HEAD(pKernelDisplay, headIdx); - headIntrMask = headIntr_none; - pending |= kheadReadPendingVblank_HAL(pGpu, pKernelHead, headIntrMask); + + if (kheadReadPendingVblank_HAL(pGpu, pKernelHead, NULL, pThreadState)) + { + pending |= NVBIT(headIdx); + } } + return pending; } diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/kernel/gpu/disp/rg_line_callback/rg_line_callback.c nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/kernel/gpu/disp/rg_line_callback/rg_line_callback.c --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/kernel/gpu/disp/rg_line_callback/rg_line_callback.c 2023-10-25 20:20:57.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/kernel/gpu/disp/rg_line_callback/rg_line_callback.c 2024-03-05 22:13:21.000000000 +0000 @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -55,6 +55,7 @@ status = dispapiSetUnicastAndSynchronize_HAL(staticCast(pRgLineCallback->pDispCommon, DisplayApi), DISPAPI_GET_GPUGRP(pRgLineCallback->pDispCommon), &pGpu, + NULL, pRgLineCallback->subDeviceInstance); if (status != NV_OK) return status; @@ -97,11 +98,6 @@ { NV0092_RG_LINE_CALLBACK_ALLOCATION_PARAMETERS *pAllocParams = pParams->pAllocParams; - if (pCallContext->secInfo.privLevel < RS_PRIV_LEVEL_KERNEL) - { - return NV_ERR_INSUFFICIENT_PERMISSIONS; - } - pRgLineCallback->subDeviceInstance = pAllocParams->subDeviceInstance; pRgLineCallback->head = pAllocParams->head; pRgLineCallback->rgLineNum = pAllocParams->rgLineNum; diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/kernel/gpu/disp/vblank_callback/vblank.c nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/kernel/gpu/disp/vblank_callback/vblank.c --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/kernel/gpu/disp/vblank_callback/vblank.c 2023-10-25 20:20:57.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/kernel/gpu/disp/vblank_callback/vblank.c 2024-03-05 22:13:21.000000000 +0000 @@ -286,7 +286,7 @@ } // Disable VBlank (if it is even on) while we scan/process the callback list - enabled = kheadReadVblankIntrEnable(pGpu, pKernelHead); + enabled = kheadReadVblankIntrEnable_HAL(pGpu, pKernelHead); if (enabled) { diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/kernel/gpu/disp/vblank_callback/vblank_callback.c nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/kernel/gpu/disp/vblank_callback/vblank_callback.c --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/kernel/gpu/disp/vblank_callback/vblank_callback.c 2023-10-25 20:20:57.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/kernel/gpu/disp/vblank_callback/vblank_callback.c 2024-03-05 22:13:21.000000000 +0000 @@ -67,11 +67,6 @@ NV_STATUS status = NV_OK; NV_VBLANK_CALLBACK_ALLOCATION_PARAMETERS *pAllocParams = pParams->pAllocParams; - if (pCallContext->secInfo.privLevel < RS_PRIV_LEVEL_KERNEL) - { - return NV_ERR_INSUFFICIENT_PERMISSIONS; - } - if (pKernelDisplay == NULL) { return NV_ERR_NOT_SUPPORTED; diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/kernel/gpu/eng_state.c nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/kernel/gpu/eng_state.c --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/kernel/gpu/eng_state.c 2023-10-25 20:20:57.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/kernel/gpu/eng_state.c 2024-03-05 22:13:21.000000000 +0000 @@ -177,8 +177,6 @@ OBJENGSTATE *pEngstate ) { - portMemFree(pEngstate->pOriginalTunableState); - pEngstate->pOriginalTunableState = NULL; } /*! @@ -385,117 +383,6 @@ } /*! - * @brief allocates a tunable state structure - * - * @param[in] pGpu - * @param[in] pEngstate - * @param[out] ppTunableState - */ -NV_STATUS -engstateAllocTunableState_IMPL -( - OBJGPU *pGpu, - OBJENGSTATE *pEngstate, - void **ppTunableState -) -{ - *ppTunableState = NULL; - return NV_OK; -} - -/*! - * @brief frees a tunable state structure - * - * @param[in] pGpu - * @param[in] pEngstate - * @param[in] pTunableState - */ -void -engstateFreeTunableState_IMPL -( - OBJGPU *pGpu, - OBJENGSTATE *pEngstate, - void *pTunableState -) -{ - portMemFree(pTunableState); -} - -/*! - * @brief fills pTunableState with the current state - * - * @param[in] pGpu - * @param[in] pEngstate - * @param[out] pTunableState - */ -NV_STATUS -engstateGetTunableState_IMPL -( - OBJGPU *pGpu, - OBJENGSTATE *pEngstate, - void *pTunableState -) -{ - return NV_OK; -} - -/*! - * @brief sets the current state to values in pTunableState - * - * @param[in] pGpu - * @param[in,out] pEngstate - * @param[in] pTunableState - */ -NV_STATUS -engstateSetTunableState_IMPL -( - OBJGPU *pGpu, - OBJENGSTATE *pEngstate, - void *pTunableState -) -{ - return NV_OK; -} - -/*! - * @brief modifies pTunableState to be compatible with pEngstate->pOriginalTunableState - * - * @param[in] pGpu - * @param[in] pEngstate - * @param[in,out] pTunableState - */ -NV_STATUS -engstateReconcileTunableState_IMPL -( - OBJGPU *pGpu, - OBJENGSTATE *pEngstate, - void *pTunableState -) -{ - return NV_OK; -} - -/*! - * @brief returns NV_ERR_GENERIC if two tunable states are incompatible - * - * @param[in] pGpu - * @param[in] pEngstate - * @param[in] pTunables1 - * @param[in] pTunables2 - */ -NV_STATUS -engstateCompareTunableState_IMPL -( - OBJGPU *pGpu, - OBJENGSTATE *pEngstate, - void *pTunables1, - void *pTunables2 -) -{ - return NV_OK; -} - -/*! * @brief returns the ENGDESCRIPTOR associated with this ENGSTATE * * @param[in] pEngstate diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/kernel/gpu/external_device/arch/kepler/kern_gsync_p2060.c nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/kernel/gpu/external_device/arch/kepler/kern_gsync_p2060.c --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/kernel/gpu/external_device/arch/kepler/kern_gsync_p2060.c 2023-10-25 20:20:57.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/kernel/gpu/external_device/arch/kepler/kern_gsync_p2060.c 2024-03-05 22:13:21.000000000 +0000 @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 1993-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 1993-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -79,10 +79,11 @@ static NV_STATUS gsyncResetFrameCountData_P2060(OBJGPU *, PDACP2060EXTERNALDEVICE); static NV_STATUS gsyncGpuStereoHeadSync(OBJGPU *, NvU32, PDACEXTERNALDEVICE, NvU32); +static NvBool supportsMulDiv(DACEXTERNALDEVICE *); static NvBool needsMasterBarrierWar(PDACEXTERNALDEVICE); static NvBool isFirmwareRevMismatch(OBJGPU *, DAC_EXTERNAL_DEVICE_REVS); -static NvBool isBoardWithNvlinkQsyncContention(POBJGPU); +static NvBool isBoardWithNvlinkQsyncContention(OBJGPU *); static void _extdevService(NvU32 , void *); NvBool @@ -348,7 +349,7 @@ NV_ASSERT_OR_RETURN(rmStatus == NV_OK, NV_FALSE); rmStatus = pRmApi->Alloc(pRmApi, hClient, hSubdevice, - &hSubscription, NV40_I2C, NULL); + &hSubscription, NV40_I2C, NULL, 0); NV_ASSERT_OR_RETURN(rmStatus == NV_OK, NV_FALSE); @@ -682,12 +683,12 @@ connector = iface + 1; // - // If adding a check before the gsyncAttachGpu call and returning before + // If adding a check before the gsyncAttachGpu call and returning before // that please add the following code: // pThis->gpuAttachMask &= ~NVBIT(pGpu->gpuInstance); // (*ppExtdevs)->ReferenceCount--; - // before returning NV_FALSE so that the caller can destroy the - // ext device structure. The destroy funciton only decrements the ref count + // before returning NV_FALSE so that the caller can destroy the + // ext device structure. The destroy funciton only decrements the ref count // if the gpu has already been attached. // (*ppExtdevs)->ReferenceCount++; @@ -1113,7 +1114,7 @@ static NV_STATUS gsyncApplyStereoPinAlwaysHiWar ( - POBJGPU pGpu, + OBJGPU *pGpu, PDACEXTERNALDEVICE pExtDev ) { @@ -1125,7 +1126,7 @@ static NV_STATUS gsyncUnApplyStereoPinAlwaysHiWar ( - POBJGPU pGpu + OBJGPU *pGpu ) { @@ -2072,15 +2073,11 @@ /* * This function returns whether there is a sync source present. * - * SYNC_LOSS bit in STATUS register is true by default, i.e when there - * is no incoming sync source. This bit is unset when a stable sync - * source is detected. - * - * Whenever framelock is enabled, NV_TRUE is returned only when the incoming - * sync source is stable. Therefore it is sent based on the software state. + * If framelock is not enabled, the only sync source possible is an external signal. * - * When framelock is not enabled, return value totally depends on the value - * of the gsync STATUS register. + * If framelock is enabled, a local master may be providing the sync signal, or + * housesync may be providing a signal via a local master, or we may need to + * poll for an external signal. */ static NV_STATUS gsyncReadIsSyncDetected_P2060 @@ -2091,8 +2088,11 @@ ) { PDACP2060EXTERNALDEVICE pThis = (PDACP2060EXTERNALDEVICE)pExtDev; - NV_STATUS rmStatus = NV_OK; - NvU32 iface; + KernelDisplay *pKernelDisplay = GPU_GET_KERNEL_DISPLAY(pGpu); + NvU32 numHeads = kdispGetNumHeads(pKernelDisplay); + + // Assume we are not synced, unless we match one of the cases below + *pVal = NV_FALSE; NV_ASSERT_OR_RETURN(pGpu, NV_ERR_GENERIC); @@ -2100,30 +2100,90 @@ { NvU8 regStatus; - // framelock is not enabled, read the NV_P2060_STATUS register to get the SYNC status - rmStatus = readregu008_extdeviceTargeted(pGpu, (PDACEXTERNALDEVICE)pThis, (NvU8)NV_P2060_STATUS, ®Status); - - if (rmStatus == NV_OK) - { - *pVal = (NV_P2060_STATUS_SYNC_LOSS_TRUE != DRF_VAL(_P2060, _STATUS, _SYNC_LOSS, regStatus)); - } + // + // Framelock is not enabled; read the NV_P2060_STATUS register to get + // the external sync status + // + NV_ASSERT_OK_OR_RETURN( + readregu008_extdeviceTargeted(pGpu, pExtDev, (NvU8)NV_P2060_STATUS, ®Status)); + *pVal = FLD_TEST_DRF(_P2060, _STATUS, _SYNC_LOSS, _FALSE, regStatus); } else { - rmStatus = GetP2060GpuLocation(pGpu, pThis, &iface); - if (NV_OK != rmStatus) + NvU32 iface, head, tempIface, tempHead; + + NV_ASSERT_OK_OR_RETURN(GetP2060GpuLocation(pGpu, pThis, &iface)); + + + for (head = 0; head < numHeads; head++) { - return rmStatus; - } + // Check if we're slaved to another master head in the same system + if (pThis->Iface[iface].Sync.LocalSlave[head]) + { + for (tempIface = 0; tempIface < NV_P2060_MAX_IFACES_PER_GSYNC; tempIface++) + { + for (tempHead = 0; tempHead < numHeads; tempHead++) + { + if (pThis->Iface[tempIface].Sync.Master[tempHead]) + { + // + // If we're slaved to another local head, we are + // receiving a sync signal from it. (But if it uses + // housesync, then it must also be receiving housesync.) + // + if (!pThis->Iface[tempIface].Sync.Slaved[tempHead]) + { + *pVal = NV_TRUE; + } + else + { + NV_ASSERT_OK_OR_RETURN( + gsyncReadHouseSignalPresent_P2060(pGpu, pExtDev, + NV_TRUE, pVal)); + } + } + } + } + break; + } - // - // Sync gain should only be derived from our internal tracking variable. - // The gsync status variables are reporting more transient data than desired. - // - *pVal = pThis->Iface[iface].gainedSync; + if (pThis->Iface[iface].Sync.Master[head]) + { + // + // A master head with no house signal has its own sync signal. + // A master head with house signal has a sync signal if the + // house signal is present. + // + if (pThis->Iface[iface].Sync.Slaved[head]) + { + NV_ASSERT_OK_OR_RETURN( + gsyncReadHouseSignalPresent_P2060(pGpu, pExtDev, NV_TRUE, pVal)); + break; + } + else + { + *pVal = NV_TRUE; + break; + } + } + + if (pThis->Iface[iface].Sync.Slaved[head]) + { + NvU8 regStatus; + + // + // A slaved head with external master signal must poll + // NV_P2060_STATUS_SYNC_LOSS for sync status. + // + NV_ASSERT_OK_OR_RETURN( + readregu008_extdeviceTargeted(pGpu, pExtDev, (NvU8)NV_P2060_STATUS, ®Status)); + *pVal = FLD_TEST_DRF(_P2060, _STATUS, _SYNC_LOSS, _FALSE, regStatus); + break; + } + } } - return rmStatus; + return NV_OK; } /* @@ -2190,41 +2250,12 @@ return rmStatus; } -/* - * Check if VCXO is locked or not. - */ -static NV_STATUS -gsyncReadVCXOLocked_P2060 -( - OBJGPU *pGpu, - PDACEXTERNALDEVICE pExtDev, - NvU32 *pVal -) -{ - PDACP2060EXTERNALDEVICE pThis = (PDACP2060EXTERNALDEVICE)pExtDev; - NV_STATUS rmStatus = NV_OK; - NvU32 regStatus = GetP2060GpuSnapshot(pGpu,pThis); - - // Status1 only needs to be read if the shapshot shows recent error or no vcxo lock - if (!FLD_TEST_DRF(_P2060, _STATUS, _VCXO, _LOCK, regStatus)) - { - rmStatus = gsyncUpdateGsyncStatusSnapshot_P2060(pGpu, pExtDev); - if ( NV_OK == rmStatus ) - { - *pVal = FLD_TEST_DRF(_P2060, _STATUS, _VCXO, _LOCK, GetP2060GpuSnapshot(pGpu,pThis)); - } - } - else - { - *pVal = 1; //VCXO is locked. - } - - return rmStatus; -} - -/* - * Check if timing is present or not. - */ +// +// Check if we are in sync, i.e. we supply the master sync signal or are servoed +// to the master sync signal. The servo should be stable for about 5 seconds if +// the signal is external (i.e. use the gainedSync value which already maintains +// this.) +// static NV_STATUS gsyncReadIsTiming_P2060 ( @@ -2234,73 +2265,15 @@ ) { PDACP2060EXTERNALDEVICE pThis = (PDACP2060EXTERNALDEVICE)pExtDev; - NV_STATUS rmStatus = NV_OK; - KernelDisplay *pKernelDisplay = GPU_GET_KERNEL_DISPLAY(pGpu); - NvU32 numHeads = kdispGetNumHeads(pKernelDisplay); - NvU32 bHouse, bLock = 0, bSync; - NvU32 iface, head, tempIface, tempHead; - - rmStatus = GetP2060GpuLocation(pGpu, pThis, &iface); - if (NV_OK != rmStatus) - { - return rmStatus; - } + NvU32 iface; - // assume no, unless we find something below - *pVal = (NvU32)NV_FALSE; + *pVal = NV_FALSE; - for (head = 0; head < numHeads; head++) - { - // check if we're slaved to another master head in the same system - if (pThis->Iface[iface].Sync.LocalSlave[head]) - { - for (tempIface = 0; tempIface < NV_P2060_MAX_IFACES_PER_GSYNC; tempIface++) - { - for (tempHead = 0; tempHead < numHeads; tempHead++) - { - if (pThis->Iface[tempIface].Sync.Master[tempHead]) - { - // assume that if we're slaved to another local head - // that we're in sync. there's no easy way to verify - // this, short of trying to compare raster scanlines - *pVal = (NvU32)NV_TRUE; - } - } - } - break; - } - - // check if we have a master, connected to a house sync - if (pThis->Iface[iface].Sync.Master[head] && pThis->Iface[iface].Sync.Slaved[head]) - { - rmStatus |= gsyncReadHouseSignalPresent_P2060(pGpu, pExtDev, NV_TRUE, &bHouse); - if ( NV_OK == rmStatus ) - { - *pVal = (NvU32)(bHouse); - } - break; - } + NV_ASSERT_OK_OR_RETURN(GetP2060GpuLocation(pGpu, pThis, &iface)); - // check if we have a master head, not connected to house sync - if (pThis->Iface[iface].Sync.Master[head]) - { - // a master is by definition always in sync - *pVal = (NvU32)NV_TRUE; - break; - } + *pVal = pThis->Iface[iface].gainedSync; - if (pThis->Iface[iface].Sync.Slaved[head]) - { - rmStatus |= gsyncReadIsSyncDetected_P2060(pGpu, pExtDev, &bSync); - rmStatus |= gsyncReadVCXOLocked_P2060(pGpu, pExtDev, &bLock); - if ( NV_OK == rmStatus ) - { - *pVal = (NvU32)(bSync && bLock); - } - break; - } - } - return rmStatus; + return NV_OK; } @@ -4094,6 +4067,8 @@ return NV_ERR_GENERIC; // something more descriptive, perhaps? } + portMemSet(pParams, 0, sizeof(*pParams)); + pParams->revId = (NvU32)pExtDev->revId; pParams->boardId = (NvU32)deviceId; pParams->revision = (NvU32)deviceRev; @@ -4140,6 +4115,12 @@ { pParams->capFlags |= NV30F1_CTRL_GSYNC_GET_CAPS_CAP_FLAGS_NEED_MASTER_BARRIER_WAR; } + + if (supportsMulDiv(pExtDev)) + { + pParams->capFlags |= NV30F1_CTRL_GSYNC_GET_CAPS_CAP_FLAGS_MULTIPLY_DIVIDE_SYNC; + pParams->maxMulDivValue = (NV_P2060_MULTIPLIER_DIVIDER_VALUE_MINUS_ONE_MAX + 1); + } } else { @@ -5422,7 +5403,7 @@ /* * Nvlink and QSync can both transmit inter-GPU Display sync signals. - * Contention in these signals is observed on some boards, if both Nvlink and + * Contention in these signals is observed on some boards, if both Nvlink and * QSync are present between the boards. * * Returns TRUE if contention in transmission of sync signals possible on the @@ -5432,7 +5413,7 @@ static NvBool isBoardWithNvlinkQsyncContention ( - POBJGPU pGpu + OBJGPU *pGpu ) { NvU16 devIds[] = { @@ -5454,3 +5435,105 @@ return NV_FALSE; } + +// Return NV_TRUE if the current Qsync revision supports sync multiply/divide +static NvBool +supportsMulDiv +( + DACEXTERNALDEVICE *pExtDev +) +{ + // Supported only for 2061 boards with >= 2.4 + if (pExtDev->deviceId == DAC_EXTERNAL_DEVICE_P2061) + { + if ((pExtDev->deviceRev >= DAC_EXTERNAL_DEVICE_REV_3) || + ((pExtDev->deviceRev == DAC_EXTERNAL_DEVICE_REV_2) && + (pExtDev->deviceExRev >= 4))) + { + return NV_TRUE; + } + } + return NV_FALSE; +} + +NV_STATUS +gsyncGetMulDiv_P2060 +( + OBJGPU *pGpu, + DACEXTERNALDEVICE *pExtDev, + NV30F1_CTRL_GSYNC_MULTIPLY_DIVIDE_SETTINGS *pMulDivSettings +) +{ + DACP2060EXTERNALDEVICE *pThis = (DACP2060EXTERNALDEVICE *)pExtDev; + NvU8 reg; + + NV_ASSERT_OR_RETURN(pMulDivSettings != NULL, NV_ERR_INVALID_ARGUMENT); + NV_CHECK_OR_RETURN(LEVEL_INFO, supportsMulDiv(pExtDev), NV_ERR_NOT_SUPPORTED); + + NV_CHECK_OK_OR_RETURN(LEVEL_INFO, + readregu008_extdeviceTargeted(pGpu, pExtDev, NV_P2060_MULTIPLIER_DIVIDER, ®)); + + pMulDivSettings->multiplyDivideValue = + DRF_VAL(_P2060, _MULTIPLIER_DIVIDER, _VALUE_MINUS_ONE, reg) + 1; + pMulDivSettings->multiplyDivideMode = + FLD_TEST_DRF(_P2060, _MULTIPLIER_DIVIDER, _MODE, _DIVIDE, reg) ? + NV30F1_CTRL_GSYNC_SET_CONTROL_MULTIPLY_DIVIDE_MODE_DIVIDE : + NV30F1_CTRL_GSYNC_SET_CONTROL_MULTIPLY_DIVIDE_MODE_MULTIPLY; + + // Cache this for debugging + portMemCopy(&pThis->mulDivSettings, sizeof(pThis->mulDivSettings), + pMulDivSettings, sizeof(*pMulDivSettings)); + + return NV_OK; +} + +NV_STATUS +gsyncSetMulDiv_P2060 +( + OBJGPU *pGpu, + DACEXTERNALDEVICE *pExtDev, + NV30F1_CTRL_GSYNC_MULTIPLY_DIVIDE_SETTINGS *pMulDivSettings +) +{ + DACP2060EXTERNALDEVICE *pThis = (DACP2060EXTERNALDEVICE *)pExtDev; + NvU8 reg; + + NV_ASSERT_OR_RETURN(pMulDivSettings != NULL, NV_ERR_INVALID_ARGUMENT); + NV_CHECK_OR_RETURN(LEVEL_INFO, supportsMulDiv(pExtDev), NV_ERR_NOT_SUPPORTED); + pGpu = GetP2060MasterableGpu(pGpu, (DACP2060EXTERNALDEVICE *)pExtDev); + NV_ASSERT_OR_RETURN(pGpu != NULL, NV_ERR_GENERIC); + + // + // Assume that there are no other fields inside NV_P2060_MULTIPLIER_DIVIDER + // to necessitate a read-modify-write + // + reg = 0; + + switch (pMulDivSettings->multiplyDivideMode) + { + case NV30F1_CTRL_GSYNC_SET_CONTROL_MULTIPLY_DIVIDE_MODE_MULTIPLY: + reg = FLD_SET_DRF(_P2060, _MULTIPLIER_DIVIDER, _MODE, _MULTIPLY, reg); + break; + case NV30F1_CTRL_GSYNC_SET_CONTROL_MULTIPLY_DIVIDE_MODE_DIVIDE: + reg = FLD_SET_DRF(_P2060, _MULTIPLIER_DIVIDER, _MODE, _DIVIDE, reg); + break; + default: + return NV_ERR_INVALID_PARAMETER; + } + + // The register is a 3-bit value ranging from 0-7 representing the integers from 1-8, so check the input param + if ((pMulDivSettings->multiplyDivideValue < 1) || + (pMulDivSettings->multiplyDivideValue > (NV_P2060_MULTIPLIER_DIVIDER_VALUE_MINUS_ONE_MAX + 1))) + return NV_ERR_INVALID_PARAMETER; + // Subtract 1 while packing the register + reg = FLD_SET_DRF_NUM(_P2060, _MULTIPLIER_DIVIDER, _VALUE_MINUS_ONE, + pMulDivSettings->multiplyDivideValue - 1, reg); + + NV_CHECK_OK_OR_RETURN(LEVEL_INFO, writeregu008_extdeviceTargeted(pGpu, pExtDev, NV_P2060_MULTIPLIER_DIVIDER, reg)); + + // Cache this for debugging + portMemCopy(&pThis->mulDivSettings, sizeof(pThis->mulDivSettings), + pMulDivSettings, sizeof(*pMulDivSettings)); + + return NV_OK; +} diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/kernel/gpu/external_device/gsync.c nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/kernel/gpu/external_device/gsync.c --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/kernel/gpu/external_device/gsync.c 2023-10-25 20:20:57.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/kernel/gpu/external_device/gsync.c 2024-03-05 22:13:22.000000000 +0000 @@ -232,6 +232,8 @@ pGsync->gsyncHal.gsyncSetInterlaceMode = gsyncSetInterlaceMode_P2060; pGsync->gsyncHal.gsyncGetStereoLockMode = gsyncGetStereoLockMode_P2060; pGsync->gsyncHal.gsyncSetStereoLockMode = gsyncSetStereoLockMode_P2060; + pGsync->gsyncHal.gsyncGetMulDiv = gsyncGetMulDiv_P2060; + pGsync->gsyncHal.gsyncSetMulDiv = gsyncSetMulDiv_P2060; pGsync->gsyncHal.gsyncRefSwapBarrier = gsyncRefSwapBarrier_P2060; pGsync->gsyncHal.gsyncSetMosaic = gsyncSetMosaic_P2060; @@ -239,7 +241,7 @@ // Constants to be returned in NV30F1_CTRL_GSYNC_GET_CAPS p2060->syncSkewResolutionInNs = NV_P2060_SYNC_SKEW_RESOLUTION; - p2060->syncSkewMax = gsyncSupportsLargeSyncSkew_P2060(pExtDev) ? + p2060->syncSkewMax = gsyncSupportsLargeSyncSkew_P2060(pExtDev) ? NV_P2060_SYNC_SKEW_MAX_UNITS_FULL_SUPPORT : NV_P2060_SYNC_SKEW_MAX_UNITS_LIMITED_SUPPORT; @@ -1230,34 +1232,39 @@ if ( pParams->which & NV30F1_CTRL_GSYNC_GET_CONTROL_SYNC_POLARITY ) { - status |= pGsync->gsyncHal.gsyncGetSyncPolarity(pGpu, pGsync->pExtDev, &SyncPolarity); + NV_CHECK_OK_OR_CAPTURE_FIRST_ERROR(status, LEVEL_INFO, pGsync->gsyncHal.gsyncGetSyncPolarity(pGpu, pGsync->pExtDev, &SyncPolarity)); pParams->syncPolarity = (NvU32)SyncPolarity; } if ( pParams->which & NV30F1_CTRL_GSYNC_GET_CONTROL_VIDEO_MODE ) { - status |= pGsync->gsyncHal.gsyncGetVideoMode(pGpu, pGsync->pExtDev, &VideoMode); + NV_CHECK_OK_OR_CAPTURE_FIRST_ERROR(status, LEVEL_INFO, pGsync->gsyncHal.gsyncGetVideoMode(pGpu, pGsync->pExtDev, &VideoMode)); pParams->syncVideoMode = (NvU32)VideoMode; } if ( pParams->which & NV30F1_CTRL_GSYNC_GET_CONTROL_NSYNC ) { - status |= pGsync->gsyncHal.gsyncGetNSync(pGpu, pGsync->pExtDev, &pParams->nSync); + NV_CHECK_OK_OR_CAPTURE_FIRST_ERROR(status, LEVEL_INFO, pGsync->gsyncHal.gsyncGetNSync(pGpu, pGsync->pExtDev, &pParams->nSync)); } if ( pParams->which & NV30F1_CTRL_GSYNC_GET_CONTROL_SYNC_SKEW ) { - status |= pGsync->gsyncHal.gsyncGetSyncSkew(pGpu, pGsync->pExtDev, &pParams->syncSkew); + NV_CHECK_OK_OR_CAPTURE_FIRST_ERROR(status, LEVEL_INFO, pGsync->gsyncHal.gsyncGetSyncSkew(pGpu, pGsync->pExtDev, &pParams->syncSkew)); } if ( pParams->which & NV30F1_CTRL_GSYNC_GET_CONTROL_SYNC_START_DELAY ) { - status |= pGsync->gsyncHal.gsyncGetSyncStartDelay(pGpu, pGsync->pExtDev, &pParams->syncStartDelay); + NV_CHECK_OK_OR_CAPTURE_FIRST_ERROR(status, LEVEL_INFO, pGsync->gsyncHal.gsyncGetSyncStartDelay(pGpu, pGsync->pExtDev, &pParams->syncStartDelay)); } if ( pParams->which & NV30F1_CTRL_GSYNC_GET_CONTROL_SYNC_USE_HOUSE ) { - status |= pGsync->gsyncHal.gsyncGetUseHouse(pGpu, pGsync->pExtDev, &pParams->useHouseSync); + NV_CHECK_OK_OR_CAPTURE_FIRST_ERROR(status, LEVEL_INFO, pGsync->gsyncHal.gsyncGetUseHouse(pGpu, pGsync->pExtDev, &pParams->useHouseSync)); + } + + if ( pParams->which & NV30F1_CTRL_GSYNC_GET_CONTROL_SYNC_MULTIPLY_DIVIDE ) + { + NV_CHECK_OK_OR_CAPTURE_FIRST_ERROR(status, LEVEL_INFO, pGsync->gsyncHal.gsyncGetMulDiv(pGpu, pGsync->pExtDev, &pParams->syncMulDiv)); } return status; @@ -1308,6 +1315,11 @@ status |= pGsync->gsyncHal.gsyncSetUseHouse(pGpu, pGsync->pExtDev, pParams->useHouseSync); } + if ( pParams->which & NV30F1_CTRL_GSYNC_SET_CONTROL_SYNC_MULTIPLY_DIVIDE ) + { + status |= pGsync->gsyncHal.gsyncSetMulDiv(pGpu, pGsync->pExtDev, &pParams->syncMulDiv); + } + return status; } @@ -2453,6 +2465,28 @@ } static NV_STATUS +gsyncNullGetMulDiv +( + OBJGPU *pGpu, + DACEXTERNALDEVICE *pExtDev, + NV30F1_CTRL_GSYNC_MULTIPLY_DIVIDE_SETTINGS *pMulDivSettings +) +{ + return NV_ERR_NOT_SUPPORTED; +} + +static NV_STATUS +gsyncNullSetMulDiv +( + OBJGPU *pGpu, + DACEXTERNALDEVICE *pExtDev, + NV30F1_CTRL_GSYNC_MULTIPLY_DIVIDE_SETTINGS *pMulDivSettings +) +{ + return NV_ERR_NOT_SUPPORTED; +} + +static NV_STATUS gsyncSetupNullProvider(OBJGSYNCMGR *pGsyncMgr, NvU32 gsyncInst) { OBJGSYNC *pGsync; @@ -2496,6 +2530,8 @@ pGsync->gsyncHal.gsyncConfigFlashGsync = gsyncNullConfigFlashGsync; pGsync->gsyncHal.gsyncGetHouseSyncMode = gsyncNullGetHouseSyncMode; pGsync->gsyncHal.gsyncSetHouseSyncMode = gsyncNullSetHouseSyncMode; + pGsync->gsyncHal.gsyncGetMulDiv = gsyncNullGetMulDiv; + pGsync->gsyncHal.gsyncSetMulDiv = gsyncNullSetMulDiv; return status; } diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/kernel/gpu/external_device/gsync_api.c nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/kernel/gpu/external_device/gsync_api.c --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/kernel/gpu/external_device/gsync_api.c 2023-10-25 20:20:58.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/kernel/gpu/external_device/gsync_api.c 2024-03-05 22:13:22.000000000 +0000 @@ -159,7 +159,7 @@ // Syncloss could also be a notifcation to reset the // event notification tracking when enabling framelock. // - if ((NV30F1_CTRL_GSYNC_SET_EVENT_NOTIFICATION_ACTION_SMART_SYNC_LOSS == oldEventFlags) && + if ((NV30F1_CTRL_GSYNC_SET_EVENT_NOTIFICATION_ACTION_SMART_SYNC_LOSS == oldEventFlags) && (pEventNotification == NULL)) { // update smart event notification tracking when diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/kernel/gpu/external_device/kern_external_device.c nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/kernel/gpu/external_device/kern_external_device.c --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/kernel/gpu/external_device/kern_external_device.c 2023-10-25 20:20:58.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/kernel/gpu/external_device/kern_external_device.c 2024-03-05 22:13:22.000000000 +0000 @@ -227,7 +227,7 @@ NvU8 Data ) { - + NV_STATUS status = NV_ERR_GENERIC; NvU32 i2cPort = (pGpu->i2cPortForExtdev < NV402C_CTRL_NUM_I2C_PORTS) ? pGpu->i2cPortForExtdev : pThis->I2CPort; @@ -282,7 +282,7 @@ NvU8 *pData ) { - + NV_STATUS status = NV_ERR_GENERIC; NvU32 i2cPort = (pGpu->i2cPortForExtdev < NV402C_CTRL_NUM_I2C_PORTS) ? pGpu->i2cPortForExtdev : pThis->I2CPort; diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/kernel/gpu/falcon/arch/turing/kernel_crashcat_engine_tu102.c nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/kernel/gpu/falcon/arch/turing/kernel_crashcat_engine_tu102.c --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/kernel/gpu/falcon/arch/turing/kernel_crashcat_engine_tu102.c 1970-01-01 00:00:00.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/kernel/gpu/falcon/arch/turing/kernel_crashcat_engine_tu102.c 2024-03-05 22:13:22.000000000 +0000 @@ -0,0 +1,74 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#define NVOC_KERNEL_CRASHCAT_ENGINE_H_PRIVATE_ACCESS_ALLOWED +#include "gpu/falcon/kernel_crashcat_engine.h" +#include "gpu/gpu.h" +#include "utils/nvprintf.h" + +#include "published/turing/tu102/dev_falcon_v4.h" + +void kcrashcatEngineReadDmem_TU102 +( + KernelCrashCatEngine *pKernelCrashCatEng, + NvU32 offset, + NvU32 size, + void *pBuf +) +{ + // This implementation only supports 32-bit-aligned accesses + NV_CHECK_OR_RETURN_VOID(LEVEL_ERROR, (offset & (sizeof(NvU32) - 1)) == 0); + NV_CHECK_OR_RETURN_VOID(LEVEL_ERROR, (size & (sizeof(NvU32) - 1)) == 0); + + NvU8 port = pKernelCrashCatEng->dmemPort; + NvU32 dmemc = kcrashcatEngineMaskDmemAddr(pKernelCrashCatEng->pGpu, pKernelCrashCatEng, offset); + dmemc = FLD_SET_DRF(_PFALCON, _FALCON_DMEMC, _AINCR, _TRUE, dmemc); + kcrashcatEngineRegWrite(pKernelCrashCatEng->pGpu, pKernelCrashCatEng, + NV_PFALCON_FALCON_DMEMC(port), dmemc); + + NvU32 *pWordBuf = (NvU32 *)pBuf; + for (NvU32 i = 0; i < (size >> 2); i++) + pWordBuf[i] = kcrashcatEngineRegRead(pKernelCrashCatEng->pGpu, pKernelCrashCatEng, + NV_PFALCON_FALCON_DMEMD(port)); +} + +NvU32 kcrashcatEngineGetWFL0Offset_TU102(KernelCrashCatEngine *pKernelCrashCatEng) +{ + return NV_PFALCON_FALCON_DEBUGINFO; +} + +const NvU32 *kcrashcatEngineGetScratchOffsets_TU102 +( + KernelCrashCatEngine *pKernelCrashCatEng, + NV_CRASHCAT_SCRATCH_GROUP_ID scratchId +) +{ + NV_CRASHCAT_DEF_SCRATCH_GROUP_V1_REGMAP_TABLE(scratchOffsetTable); + + if (scratchId <= NV_CRASHCAT_SCRATCH_GROUP_ID_LAST) + return scratchOffsetTable[scratchId]; + + NV_PRINTF(LEVEL_ERROR, "unknown CrashCat scratch ID %u\n", scratchId); + + return NULL; +} diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/kernel/gpu/falcon/kernel_crashcat_engine.c nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/kernel/gpu/falcon/kernel_crashcat_engine.c --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/kernel/gpu/falcon/kernel_crashcat_engine.c 1970-01-01 00:00:00.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/kernel/gpu/falcon/kernel_crashcat_engine.c 2024-03-05 22:13:23.000000000 +0000 @@ -0,0 +1,328 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#define NVOC_KERNEL_CRASHCAT_ENGINE_H_PRIVATE_ACCESS_ALLOWED +#include "gpu/falcon/kernel_crashcat_engine.h" +#include "gpu/gpu.h" +#include "core/printf.h" +#include "os/nv_memory_type.h" + +NV_STATUS kcrashcatEngineConfigure_IMPL +( + KernelCrashCatEngine *pKernelCrashCatEng, + KernelCrashCatEngineConfig *pEngConfig +) +{ + if (!pEngConfig->bEnable) + return NV_OK; + + NV_CHECK_OR_RETURN(LEVEL_ERROR, pEngConfig->pName != NULL, NV_ERR_INVALID_ARGUMENT); + NV_CHECK_OR_RETURN(LEVEL_ERROR, pEngConfig->errorId != 0, NV_ERR_INVALID_ARGUMENT); + + pKernelCrashCatEng->bConfigured = NV_TRUE; + pKernelCrashCatEng->pName = pEngConfig->pName; + pKernelCrashCatEng->errorId = pEngConfig->errorId; + pKernelCrashCatEng->pGpu = ENG_GET_GPU(pKernelCrashCatEng); + pKernelCrashCatEng->dmemPort = pEngConfig->dmemPort; + + if (pEngConfig->allocQueueSize > 0) + { + const NvU32 CRASHCAT_QUEUE_ALIGNMENT = 1u << 10; + pEngConfig->allocQueueSize = NV_ALIGN_UP(pEngConfig->allocQueueSize, + CRASHCAT_QUEUE_ALIGNMENT); + NV_STATUS status; + + // + // The queue must be contiguous and 1KB aligned in both size and offset. + // Typically the queue will be a single page to satisfy these requirements. + // + NV_CHECK_OK_OR_RETURN(LEVEL_ERROR, + memdescCreate(&pKernelCrashCatEng->pQueueMemDesc, pKernelCrashCatEng->pGpu, + pEngConfig->allocQueueSize, CRASHCAT_QUEUE_ALIGNMENT, NV_TRUE, + ADDR_SYSMEM, NV_MEMORY_CACHED, MEMDESC_FLAGS_NONE)); + + NV_CHECK_OK_OR_GOTO(status, LEVEL_ERROR, + memdescAlloc(pKernelCrashCatEng->pQueueMemDesc), + memdescCleanup); + + // + // After kcrashcatEngineRegisterCrashBuffer(), the CrashCat library should be able to map + // and access the queue buffer when it shows up in a wayfinder. + // + NV_CHECK_OK_OR_GOTO(status, LEVEL_ERROR, + kcrashcatEngineRegisterCrashBuffer(pKernelCrashCatEng, + pKernelCrashCatEng->pQueueMemDesc), + memdescCleanup); + +memdescCleanup: + if (status != NV_OK) + { + kcrashcatEngineUnload(pKernelCrashCatEng); + return status; + } + } + + return NV_OK; +} + +NvBool kcrashcatEngineConfigured_IMPL(KernelCrashCatEngine *pKernelCrashCatEng) +{ + return pKernelCrashCatEng->bConfigured; +} + +MEMORY_DESCRIPTOR *kcrashcatEngineGetQueueMemDesc_IMPL(KernelCrashCatEngine *pKernelCrashCatEng) +{ + return pKernelCrashCatEng->pQueueMemDesc; +} + +void kcrashcatEngineUnload_IMPL(KernelCrashCatEngine *pKernelCrashCatEng) +{ + if (pKernelCrashCatEng->pQueueMemDesc != NULL) + { + kcrashcatEngineUnregisterCrashBuffer(pKernelCrashCatEng, pKernelCrashCatEng->pQueueMemDesc); + memdescFree(pKernelCrashCatEng->pQueueMemDesc); + memdescDestroy(pKernelCrashCatEng->pQueueMemDesc); + pKernelCrashCatEng->pQueueMemDesc = NULL; + } + + crashcatEngineUnload_IMPL(staticCast(pKernelCrashCatEng, CrashCatEngine)); +} + +NvU32 kcrashcatEnginePriRead_IMPL +( + KernelCrashCatEngine *pKernelCrashCatEng, + NvU32 offset +) +{ + return kcrashcatEngineRegRead(pKernelCrashCatEng->pGpu, pKernelCrashCatEng, offset); +} + +void kcrashcatEnginePriWrite_IMPL +( + KernelCrashCatEngine *pKernelCrashCatEng, + NvU32 offset, + NvU32 data +) +{ + kcrashcatEngineRegWrite(pKernelCrashCatEng->pGpu, pKernelCrashCatEng, offset, data); +} + +void kcrashcatEngineVprintf_IMPL +( + KernelCrashCatEngine *pKernelCrashCatEng, + NvBool bReportStart, + const char *fmt, + va_list args +) +{ + // + // The first line logs an Xid - subsequent crash report lines are printed via + // portDbgPrintString() so that they are in dmesg, but don't cause additional Xid "events". + // + if (bReportStart) + { + va_list argsCopy; + + // + // Prefix the engine name to the format string. + // nvErrorLog() appends a newline, so we don't add one here. + // + nvDbgSnprintf(pKernelCrashCatEng->fmtBuffer, MAX_ERROR_STRING, "%s %s", + pKernelCrashCatEng->pName, fmt); + + va_copy(argsCopy, args); + nvErrorLog(pKernelCrashCatEng->pGpu, pKernelCrashCatEng->errorId, + pKernelCrashCatEng->fmtBuffer, argsCopy); + va_end(argsCopy); + } + + // portDbgPrintString/NVLOG_PRINTF don't add a newline, so add one here + const char *newline = "\n"; + const NvLength fmtSize = portStringLength(fmt) + 1; + const NvLength newlineSize = 3; // Two chars plus terminating null + const NvLength newFmtSize = fmtSize + newlineSize - 1; // terminating null is shared + + portMemCopy(pKernelCrashCatEng->fmtBuffer, MAX_ERROR_STRING, fmt, fmtSize); + portStringCat(pKernelCrashCatEng->fmtBuffer, newFmtSize, newline, newlineSize); + nvDbgVsnprintf(pKernelCrashCatEng->printBuffer, MAX_ERROR_STRING, + pKernelCrashCatEng->fmtBuffer, args); + + // The report-starting line was already printed by nvErrorLog above + if (!bReportStart) + portDbgPrintString(pKernelCrashCatEng->printBuffer, MAX_ERROR_STRING); + + // + // Also print the formatted string to NvLog - avoid direct NV_PRINTF calls so as not to + // duplicate output in dmesg. + // + NVLOG_PRINTF(NV_PRINTF_MODULE, NVLOG_ROUTE_RM, LEVEL_ERROR, pKernelCrashCatEng->printBuffer); +} + +static NV_INLINE +NV_CRASHCAT_MEM_APERTURE _addressSpaceToCrashcatAperture(NV_ADDRESS_SPACE addrSpace) +{ + switch (addrSpace) + { + case ADDR_SYSMEM: return NV_CRASHCAT_MEM_APERTURE_SYSGPA; + case ADDR_FBMEM: return NV_CRASHCAT_MEM_APERTURE_FBGPA; + default: NV_ASSERT_OR_RETURN(0, NV_CRASHCAT_MEM_APERTURE_UNKNOWN); + } +} + +NV_STATUS kcrashcatEngineRegisterCrashBuffer_IMPL +( + KernelCrashCatEngine *pKernelCrashCatEng, + MEMORY_DESCRIPTOR *pMemDesc +) +{ + return crashcatEngineRegisterCrashBuffer(staticCast(pKernelCrashCatEng, CrashCatEngine), + _addressSpaceToCrashcatAperture(memdescGetAddressSpace(pMemDesc)), + memdescGetPhysAddr(pMemDesc, AT_GPU, 0), memdescGetSize(pMemDesc), + pMemDesc); +} + +void kcrashcatEngineUnregisterCrashBuffer_IMPL +( + KernelCrashCatEngine *pKernelCrashCatEng, + MEMORY_DESCRIPTOR *pMemDesc +) +{ + crashcatEngineUnregisterCrashBuffer(staticCast(pKernelCrashCatEng, CrashCatEngine), + _addressSpaceToCrashcatAperture(memdescGetAddressSpace(pMemDesc)), + memdescGetPhysAddr(pMemDesc, AT_GPU, 0), memdescGetSize(pMemDesc)); +} + +static NV_INLINE NV_ADDRESS_SPACE _crashcatApertureToAddressSpace(NV_CRASHCAT_MEM_APERTURE aper) +{ + switch (aper) + { + case NV_CRASHCAT_MEM_APERTURE_FBGPA: return ADDR_FBMEM; + case NV_CRASHCAT_MEM_APERTURE_SYSGPA: return ADDR_SYSMEM; + default: return ADDR_UNKNOWN; + } +} + +static MEMORY_DESCRIPTOR *_kcrashcatEngineCreateBufferMemDesc +( + KernelCrashCatEngine *pKernelCrashCatEng, + CrashCatBufferDescriptor *pBufDesc +) +{ + // Convert the buffer descriptor to a set of memdesc parameters + MEMORY_DESCRIPTOR *pMemDesc; + NV_STATUS status; + NV_ADDRESS_SPACE bufAddrSpace = _crashcatApertureToAddressSpace(pBufDesc->aperture); + NV_CHECK_OK_OR_ELSE(status, LEVEL_ERROR, + memdescCreate(&pMemDesc, pKernelCrashCatEng->pGpu, pBufDesc->size, 0, + NV_TRUE, bufAddrSpace, NV_MEMORY_CACHED, MEMDESC_FLAGS_NONE), + return NULL;); + + memdescDescribe(pMemDesc, bufAddrSpace, pBufDesc->physOffset, pBufDesc->size); + return pMemDesc; +} + +void *kcrashcatEngineMapBufferDescriptor_IMPL +( + KernelCrashCatEngine *pKernelCrashCatEng, + CrashCatBufferDescriptor *pBufDesc +) +{ + MEMORY_DESCRIPTOR *pMemDesc; + + if (pBufDesc->bRegistered) + pMemDesc = pBufDesc->pEngPriv; + else + pMemDesc = _kcrashcatEngineCreateBufferMemDesc(pKernelCrashCatEng, pBufDesc); + + NV_CHECK_OR_RETURN(LEVEL_ERROR, pMemDesc != NULL, NULL); + + NvP64 pBuf, pPriv; + NV_STATUS status; + + // CrashCat buffers are read-only + NV_CHECK_OK_OR_ELSE(status, LEVEL_ERROR, + memdescMap(pMemDesc, 0, memdescGetSize(pMemDesc), NV_TRUE, + NV_PROTECT_READABLE, &pBuf, &pPriv), + { + if (!pBufDesc->bRegistered) + memdescDestroy(pMemDesc); + return NULL; + }); + + memdescSetKernelMapping(pMemDesc, pBuf); + memdescSetKernelMappingPriv(pMemDesc, pPriv); + pBufDesc->pEngPriv = pMemDesc; + return NvP64_VALUE(pBuf); +} + +void kcrashcatEngineUnmapBufferDescriptor_IMPL +( + KernelCrashCatEngine *pKernelCrashCatEng, + CrashCatBufferDescriptor *pBufDesc +) +{ + MEMORY_DESCRIPTOR *pMemDesc = pBufDesc->pEngPriv; + NvP64 pBuf = memdescGetKernelMapping(pMemDesc); + NvP64 pPriv = memdescGetKernelMappingPriv(pMemDesc); + + memdescUnmap(pMemDesc, NV_TRUE, 0, pBuf, pPriv); + memdescSetKernelMapping(pMemDesc, NULL); + memdescSetKernelMappingPriv(pMemDesc, NULL); + + if (!pBufDesc->bRegistered) + memdescDestroy(pMemDesc); +} + +void kcrashcatEngineSyncBufferDescriptor_IMPL +( + KernelCrashCatEngine *pKernelCrashCatEng, + CrashCatBufferDescriptor *pBufDesc, + NvU32 offset, + NvU32 size +) +{ + // + // The buffers which support the "sync" operation don't have a memdesc - they are accessed + // through ports, so we copy the data out into a local buffer instead of direct map. + // + NV_ASSERT_CHECKED(NvU64_HI32(pBufDesc->physOffset) == 0); + NV_ASSERT_CHECKED(NvU64_HI32(pBufDesc->size) == 0); + + switch (pBufDesc->aperture) + { + case NV_CRASHCAT_MEM_APERTURE_DMEM: + kcrashcatEngineReadDmem_HAL(pKernelCrashCatEng, + NvU64_LO32(pBufDesc->physOffset) + offset, + size, + (void *)((NvUPtr)pBufDesc->pMapping + offset)); + return; + case NV_CRASHCAT_MEM_APERTURE_EMEM: + kcrashcatEngineReadEmem_HAL(pKernelCrashCatEng, + NvU64_LO32(pBufDesc->physOffset) + offset, + size, + (void *)((NvUPtr)pBufDesc->pMapping + offset)); + return; + default: + NV_ASSERT_CHECKED(0); + } +} diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/kernel/gpu/falcon/kernel_falcon.c nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/kernel/gpu/falcon/kernel_falcon.c --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/kernel/gpu/falcon/kernel_falcon.c 2023-10-25 20:20:58.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/kernel/gpu/falcon/kernel_falcon.c 2024-03-05 22:13:23.000000000 +0000 @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 2021-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2021-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -30,12 +30,12 @@ #include "gpu/fifo/kernel_channel_group_api.h" #include "gpu/intr/intr.h" #include "gpu/subdevice/subdevice.h" +#include "gpu/mem_mgr/mem_mgr.h" #include "gpu/mem_mgr/mem_desc.h" #include "mem_mgr/gpu_vaspace.h" #include "mem_mgr/ctx_buf_pool.h" #include "rmapi/rmapi.h" - void kflcnConfigureEngine_IMPL(OBJGPU *pGpu, KernelFalcon *pKernelFalcon, KernelFalconEngineConfig *pFalconConfig) { pKernelFalcon->registerBase = pFalconConfig->registerBase; @@ -49,6 +49,10 @@ pKernelFalcon->ctxBufferSize = pFalconConfig->ctxBufferSize; pKernelFalcon->addrSpaceList = pFalconConfig->addrSpaceList; + // Configure CrashCat with caller arguments (disabled by default) + kcrashcatEngineConfigure(staticCast(pKernelFalcon, KernelCrashCatEngine), + &pFalconConfig->crashcatEngConfig); + NV_PRINTF(LEVEL_INFO, "for physEngDesc 0x%x\n", pKernelFalcon->physEngDesc); } @@ -96,7 +100,6 @@ CTX_BUF_POOL_INFO *pCtxBufPool = NULL; KernelChannelGroup *pKernelChannelGroup = pKernelChannel->pKernelChannelGroupApi->pKernelChannelGroup; OBJGVASPACE *pGVAS = dynamicCast(pKernelChannel->pVAS, OBJGVASPACE); - NvU8 *pInstMem; NV_STATUS status = NV_OK; NvU64 flags = MEMDESC_FLAGS_OWNED_BY_CURRENT_DEVICE; @@ -135,22 +138,10 @@ memdescAllocList(pCtxMemDesc, memdescU32ToAddrSpaceList(pKernelFalcon->addrSpaceList)), done); - pInstMem = memdescMapInternal(pGpu, pCtxMemDesc, 0); - if (pInstMem != NULL) - { - // Clear the engine context buffer - NvU32 i; - for (i = 0; i < pKernelFalcon->ctxBufferSize; i += 4) - { - MEM_WR32(pInstMem + i, 0); - } - memdescUnmapInternal(pGpu, pCtxMemDesc, 0); - } - else - { - status = NV_ERR_INSUFFICIENT_RESOURCES; - goto done; - } + NV_ASSERT_OK_OR_GOTO(status, + memmgrMemDescMemSet(GPU_GET_MEMORY_MANAGER(pGpu), pCtxMemDesc, 0, + TRANSFER_FLAGS_NONE), + done); NV_ASSERT_OK_OR_GOTO(status, kchannelSetEngineContextMemDesc(pGpu, pKernelChannel, pKernelFalcon->physEngDesc, pCtxMemDesc), @@ -183,17 +174,16 @@ RM_API *pRmApi = GPU_GET_PHYSICAL_RMAPI(pGpu); RsClient *pClient = RES_GET_CLIENT(pKernelChannel); Subdevice *pSubdevice; - NvU64 addr; RM_ENGINE_TYPE rmEngineType; ENGINE_CTX_DESCRIPTOR *pEngCtx; NV2080_CTRL_GPU_PROMOTE_CTX_PARAMS rmCtrlParams = {0}; + OBJGVASPACE *pGVAS = dynamicCast(pKernelChannel->pVAS, OBJGVASPACE); NV_ASSERT_OK_OR_RETURN(subdeviceGetByGpu(pClient, pGpu, &pSubdevice)); NV_ASSERT_OR_RETURN(gpumgrGetSubDeviceInstanceFromGpu(pGpu) == 0, NV_ERR_INVALID_STATE); pEngCtx = pKernelChannel->pKernelChannelGroupApi->pKernelChannelGroup->ppEngCtxDesc[0]; NV_ASSERT_OR_RETURN(pEngCtx != NULL, NV_ERR_INVALID_ARGUMENT); - NV_ASSERT_OK_OR_RETURN(vaListFindVa(&pEngCtx->vaList, pKernelChannel->pVAS, &addr)); NV_ASSERT_OK_OR_RETURN(kfifoEngineInfoXlate_HAL(pGpu, GPU_GET_KERNEL_FIFO(pGpu), ENGINE_INFO_TYPE_ENG_DESC, pKernelFalcon->physEngDesc, @@ -202,11 +192,65 @@ rmCtrlParams.hClient = pClient->hClient; rmCtrlParams.hObject = RES_GET_HANDLE(pKernelChannel); rmCtrlParams.hChanClient = pClient->hClient; - rmCtrlParams.virtAddress = addr; rmCtrlParams.size = pKernelFalcon->ctxBufferSize; rmCtrlParams.engineType = gpuGetNv2080EngineType(rmEngineType); rmCtrlParams.ChID = pKernelChannel->ChID; + // Promote physical address only. VA will be promoted later as part of nvgpuBindChannelResources + if (gvaspaceIsExternallyOwned(pGVAS)) + { + MEMORY_DESCRIPTOR *pMemDesc = NULL; + NvU32 physAttr = 0x0; + + NV_ASSERT_OK_OR_RETURN(kchangrpGetEngineContextMemDesc(pGpu, + pKernelChannel->pKernelChannelGroupApi->pKernelChannelGroup, &pMemDesc)); + NV_ASSERT_OR_RETURN(memdescGetContiguity(pMemDesc, AT_GPU), NV_ERR_INVALID_STATE); + + switch (memdescGetAddressSpace(pMemDesc)) + { + case ADDR_FBMEM: + physAttr = FLD_SET_DRF(2080, _CTRL_GPU_INITIALIZE_CTX, + _APERTURE, _VIDMEM, physAttr); + break; + + case ADDR_SYSMEM: + if (memdescGetCpuCacheAttrib(pMemDesc) == NV_MEMORY_CACHED) + { + physAttr = FLD_SET_DRF(2080, _CTRL_GPU_INITIALIZE_CTX, + _APERTURE, _COH_SYS, physAttr); + } + else if (memdescGetCpuCacheAttrib(pMemDesc) == NV_MEMORY_UNCACHED) + { + physAttr = FLD_SET_DRF(2080, _CTRL_GPU_INITIALIZE_CTX, + _APERTURE, _NCOH_SYS, physAttr); + } + else + { + return NV_ERR_INVALID_STATE; + } + break; + + default: + return NV_ERR_INVALID_STATE; + } + + physAttr = FLD_SET_DRF(2080, _CTRL_GPU_INITIALIZE_CTX, _GPU_CACHEABLE, _NO, physAttr); + + rmCtrlParams.entryCount = 1; + rmCtrlParams.promoteEntry[0].gpuPhysAddr = memdescGetPhysAddr(pMemDesc, AT_GPU, 0); + rmCtrlParams.promoteEntry[0].size = pMemDesc->Size; + rmCtrlParams.promoteEntry[0].physAttr = physAttr; + rmCtrlParams.promoteEntry[0].bufferId = 0; // unused for flcn + rmCtrlParams.promoteEntry[0].bInitialize = NV_TRUE; + rmCtrlParams.promoteEntry[0].bNonmapped = NV_TRUE; + } + else + { + NvU64 addr; + NV_ASSERT_OK_OR_RETURN(vaListFindVa(&pEngCtx->vaList, pKernelChannel->pVAS, &addr)); + rmCtrlParams.virtAddress = addr; + } + NV_ASSERT_OK_OR_RETURN(pRmApi->Control(pRmApi, pClient->hClient, RES_GET_HANDLE(pSubdevice), NV2080_CTRL_CMD_GPU_PROMOTE_CTX, &rmCtrlParams, sizeof(rmCtrlParams))); @@ -291,11 +335,6 @@ NV_ASSERT_FAILED("This should only be called on full KernelFalcon implementations"); return NV_ERR_NOT_SUPPORTED; } -NvBool gkflcnIsEngineInReset_IMPL(OBJGPU *pGpu, GenericKernelFalcon *pGenKernFlcn) -{ - NV_ASSERT_FAILED("This should only be called on full KernelFalcon implementations"); - return NV_FALSE; -} void gkflcnRegisterIntrService_IMPL(OBJGPU *pGpu, GenericKernelFalcon *pGenericKernelFalcon, IntrServiceRecord pRecords[MC_ENGINE_IDX_MAX]) { diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/kernel/gpu/falcon/kernel_falcon_ctrl.c nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/kernel/gpu/falcon/kernel_falcon_ctrl.c --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/kernel/gpu/falcon/kernel_falcon_ctrl.c 1970-01-01 00:00:00.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/kernel/gpu/falcon/kernel_falcon_ctrl.c 2024-03-05 22:13:23.000000000 +0000 @@ -0,0 +1,243 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2021-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ +#include "gpu/falcon/kernel_falcon.h" +#include "gpu/nvlink/kernel_nvlink.h" +#include "gpu/fifo/kernel_fifo.h" +#include "gpu/fifo/kernel_channel.h" +#include "gpu/fifo/kernel_channel_group.h" +#include "gpu/fifo/kernel_channel_group_api.h" +#include "gpu/subdevice/subdevice.h" +#include "gpu/mem_mgr/mem_mgr.h" +#include "vgpu/rpc.h" +#include "ctrl/ctrl2080/ctrl2080flcn.h" + +NV_STATUS subdeviceCtrlCmdFlcnGetCtxBufferInfo_IMPL +( Subdevice *pSubdevice, + NV2080_CTRL_FLCN_GET_CTX_BUFFER_INFO_PARAMS *pParams +) +{ + POBJGPU pGpu = GPU_RES_GET_GPU(pSubdevice); + PMEMORY_DESCRIPTOR pMemDesc, pRootMemDesc; + RsClient *pUserClient; + KernelChannel *pKernelChannel = NULL; + NV_STATUS status = NV_OK; + NvU64 pageSize; + NvU8 *pUuid = NULL; + + // + // vGPU: + // + // Since vGPU does all real hardware management in the + // host, if we are in guest OS (where IS_VIRTUAL(pGpu) is true), + // do an RPC to the host to get context buffers information. + // + if (IS_VIRTUAL_WITHOUT_SRIOV(pGpu) || + (IS_VIRTUAL_WITH_SRIOV(pGpu) && gpuIsWarBug200577889SriovHeavyEnabled(pGpu))) + { + CALL_CONTEXT *pCallContext = resservGetTlsCallContext(); + RmCtrlParams *pRmCtrlParams = pCallContext->pControlParams; + + NV_RM_RPC_CONTROL(pGpu, + pRmCtrlParams->hClient, + pRmCtrlParams->hObject, + pRmCtrlParams->cmd, + pRmCtrlParams->pParams, + pRmCtrlParams->paramsSize, + status); + return status; + } + + NV_CHECK_OK_OR_RETURN(LEVEL_INFO, + serverGetClientUnderLock(&g_resServ, pParams->hUserClient, &pUserClient)); + + NV_CHECK_OK_OR_RETURN(LEVEL_INFO, + CliGetKernelChannel(pUserClient, pParams->hChannel, &pKernelChannel)); + NV_ASSERT_OR_RETURN(pKernelChannel != NULL, NV_ERR_INVALID_CHANNEL); + + switch (kchannelGetEngineType(pKernelChannel)) + { + case RM_ENGINE_TYPE_SEC2: + { + break; + } + default: + { + return NV_ERR_NOT_SUPPORTED; + } + } + + NV_ASSERT_OK_OR_RETURN(kchangrpGetEngineContextMemDesc(pGpu, pKernelChannel->pKernelChannelGroupApi->pKernelChannelGroup, &pMemDesc)); + pRootMemDesc = memdescGetRootMemDesc(pMemDesc, NULL); + + pParams->bufferHandle = NV_PTR_TO_NvP64(pMemDesc); + pParams->bIsContigous = memdescGetContiguity(pMemDesc, AT_GPU); + pParams->aperture = memdescGetAddressSpace(pMemDesc); + pParams->pageCount = pMemDesc->PageCount; + pParams->kind = memdescGetPteKindForGpu(pMemDesc, pMemDesc->pGpu); + + { + NvU64 physAddr; + GMMU_APERTURE aperture = kgmmuGetExternalAllocAperture(pParams->aperture); + + memdescGetPhysAddrsForGpu(pMemDesc, pMemDesc->pGpu, + AT_GPU, 0, 0, 1, + &physAddr); + + pParams->physAddr = + kgmmuEncodePhysAddr(GPU_GET_KERNEL_GMMU(pMemDesc->pGpu), aperture, physAddr, NVLINK_INVALID_FABRIC_ADDR); + } + + pageSize = memdescGetPageSize(pMemDesc, AT_GPU); + if (pageSize == 0) + { + status = memmgrSetMemDescPageSize_HAL(pMemDesc->pGpu, + GPU_GET_MEMORY_MANAGER(pMemDesc->pGpu), + pMemDesc, + AT_GPU, + RM_ATTR_PAGE_SIZE_DEFAULT); + if (status != NV_OK) + return status; + + pageSize = memdescGetPageSize(pMemDesc, AT_GPU); + NV_ASSERT(pageSize != 0); + } + + // + // Alignment is used to adjust the mapping VA. Hence, we need to make sure + // that it is at least pageSize to make mapping calculation work correctly. + // + pParams->alignment = (pMemDesc->Alignment != 0) ? + NV_ALIGN_UP(pMemDesc->Alignment, pageSize) : pageSize; + + pParams->size = pMemDesc->ActualSize; + + NV_ASSERT_OR_RETURN(pageSize <= NV_U32_MAX, NV_ERR_INVALID_STATE); + pParams->pageSize = (NvU32)pageSize; + + pParams->bDeviceDescendant = pRootMemDesc->pGpu != NULL; + + if (pParams->bDeviceDescendant) + { + NvU32 flags = DRF_DEF(2080_GPU_CMD, _GPU_GET_GID_FLAGS, _TYPE, _SHA1) | + DRF_DEF(2080_GPU_CMD, _GPU_GET_GID_FLAGS, _FORMAT, _BINARY); + NvU32 uuidLength; + // allocates memory for pUuid on success + NV_ASSERT_OK_OR_RETURN(gpuGetGidInfo(pGpu, &pUuid, &uuidLength, flags)); + if (uuidLength == sizeof(pParams->uuid)) + portMemCopy(pParams->uuid, uuidLength, pUuid, uuidLength); + else + { + status = NV_ERR_INVALID_ARGUMENT; + goto done; + } + } + +done: + portMemFree(pUuid); + return status; +} + +NV_STATUS +subdeviceCtrlCmdFlcnGetCtxBufferSize_IMPL +( + Subdevice *pSubdevice, + NV2080_CTRL_FLCN_GET_CTX_BUFFER_SIZE_PARAMS *pParams +) +{ + POBJGPU pGpu = GPU_RES_GET_GPU(pSubdevice); + PMEMORY_DESCRIPTOR pMemDesc; + KernelChannel *pKernelChannel = NULL; + NV_STATUS status = NV_OK; + NvU64 alignment; + NvU64 pageSize; + NvU64 totalBufferSize; + + // + // vGPU: + // + // Since vGPU does all real hardware management in the + // host, if we are in guest OS (where IS_VIRTUAL(pGpu) is true), + // do an RPC to the host to fetch the engine context buffer size. + // + if (IS_VIRTUAL_WITHOUT_SRIOV(pGpu) || + (IS_VIRTUAL_WITH_SRIOV(pGpu) && gpuIsWarBug200577889SriovHeavyEnabled(pGpu))) + { + CALL_CONTEXT *pCallContext = resservGetTlsCallContext(); + RmCtrlParams *pRmCtrlParams = pCallContext->pControlParams; + + NV_RM_RPC_CONTROL(pGpu, + pRmCtrlParams->hClient, + pRmCtrlParams->hObject, + pRmCtrlParams->cmd, + pRmCtrlParams->pParams, + pRmCtrlParams->paramsSize, + status); + return status; + } + + NV_CHECK_OK_OR_RETURN(LEVEL_INFO, + CliGetKernelChannel(RES_GET_CLIENT(pSubdevice), pParams->hChannel, + &pKernelChannel)); + NV_ASSERT_OR_RETURN(pKernelChannel != NULL, NV_ERR_INVALID_CHANNEL); + + switch (kchannelGetEngineType(pKernelChannel)) + { + case RM_ENGINE_TYPE_SEC2: + { + break; + } + default: + { + return NV_ERR_NOT_SUPPORTED; + } + } + + NV_ASSERT_OK_OR_RETURN(kchangrpGetEngineContextMemDesc(pGpu, pKernelChannel->pKernelChannelGroupApi->pKernelChannelGroup, &pMemDesc)); + + pageSize = memdescGetPageSize(pMemDesc, AT_GPU); + if (pageSize == 0) + { + status = memmgrSetMemDescPageSize_HAL(pMemDesc->pGpu, + GPU_GET_MEMORY_MANAGER(pMemDesc->pGpu), + pMemDesc, + AT_GPU, + RM_ATTR_PAGE_SIZE_DEFAULT); + if (status != NV_OK) + return status; + + pageSize = memdescGetPageSize(pMemDesc, AT_GPU); + NV_ASSERT(pageSize != 0); + } + + // + // Adjust the total size by adding the alignment so that the mapping VA can + // be adjusted. + // + alignment = (pMemDesc->Alignment != 0) ? NV_ALIGN_UP(pMemDesc->Alignment, pageSize) : pageSize; + totalBufferSize = 0; + totalBufferSize += alignment; + totalBufferSize += (alignment != 0) ? NV_ALIGN_UP(pMemDesc->ActualSize, alignment) : pMemDesc->ActualSize; + pParams->totalBufferSize = totalBufferSize; + + return status; +} diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/kernel/gpu/fifo/arch/ampere/kernel_fifo_ga100.c nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/kernel/gpu/fifo/arch/ampere/kernel_fifo_ga100.c --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/kernel/gpu/fifo/arch/ampere/kernel_fifo_ga100.c 2023-10-25 20:20:58.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/kernel/gpu/fifo/arch/ampere/kernel_fifo_ga100.c 2024-03-05 22:13:23.000000000 +0000 @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 2021-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2021-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -21,6 +21,9 @@ * DEALINGS IN THE SOFTWARE. */ +// FIXME XXX +#define NVOC_KERNEL_GRAPHICS_MANAGER_H_PRIVATE_ACCESS_ALLOWED + #include "kernel/gpu/fifo/kernel_fifo.h" #include "kernel/gpu/fifo/kernel_channel_group_api.h" #include "kernel/gpu/fifo/kernel_channel_group.h" @@ -33,19 +36,7 @@ #include "published/ampere/ga100/dev_ram.h" #include "published/ampere/ga100/dev_ctrl.h" -/** - * @brief Translates between 2 engine values - * - * To iterate through a value for all engines call with inType of - * ENGINE_INFO_TYPE_INVALID for 0 through fifoGetNumEngines(). - * - * @param pGpu - * @param pKernelFifo - * @param[in] inType ENGINE_INFO_TYPE_* - * @param[in] inVal - * @param[in] outType ENGINE_INFO_TYPE_* - * @param[out] pOutVal - */ + NV_STATUS kfifoEngineInfoXlate_GA100 ( @@ -94,10 +85,13 @@ if (outType == ENGINE_INFO_TYPE_MMU_FAULT_ID) { NvU32 grIdx, startSubctxId; + NV_STATUS status; RM_ENGINE_TYPE rmEngineType; - NV_ASSERT_OK_OR_RETURN(kfifoEngineInfoXlate_GV100(pGpu, pKernelFifo, inType, inVal, - ENGINE_INFO_TYPE_RM_ENGINE_TYPE, (NvU32 *)&rmEngineType)); + status = kfifoEngineInfoXlate_GV100(pGpu, pKernelFifo, inType, inVal, + ENGINE_INFO_TYPE_RM_ENGINE_TYPE, (NvU32 *)&rmEngineType); + if (status != NV_OK) + return status; // check if rmEngineType corresponding to input is GR if (RM_ENGINE_TYPE_IS_GR(rmEngineType)) @@ -149,29 +143,6 @@ } /*! - * @brief Clear USERD memory - */ -void -kfifoSetupUserD_GA100 -( - KernelFifo *pKernelFifo, - NvU8 *pUserD -) -{ - NV_ASSERT_OR_RETURN_VOID(pUserD != NULL); - - MEM_WR32( pUserD + SF_OFFSET( NV_RAMUSERD_PUT ), 0 ); - MEM_WR32( pUserD + SF_OFFSET( NV_RAMUSERD_GET ), 0 ); - MEM_WR32( pUserD + SF_OFFSET( NV_RAMUSERD_REF ), 0 ); - MEM_WR32( pUserD + SF_OFFSET( NV_RAMUSERD_PUT_HI ), 0 ); - MEM_WR32( pUserD + SF_OFFSET( NV_RAMUSERD_TOP_LEVEL_GET ), 0 ); - MEM_WR32( pUserD + SF_OFFSET( NV_RAMUSERD_TOP_LEVEL_GET_HI ), 0 ); - MEM_WR32( pUserD + SF_OFFSET( NV_RAMUSERD_GET_HI ), 0 ); - MEM_WR32( pUserD + SF_OFFSET( NV_RAMUSERD_GP_GET ), 0 ); - MEM_WR32( pUserD + SF_OFFSET( NV_RAMUSERD_GP_PUT ), 0 ); -} - -/*! * @brief Update the usermode doorbell register with work submit token to notify * host that work is available on this channel. * diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/kernel/gpu/fifo/arch/hopper/kernel_fifo_gh100.c nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/kernel/gpu/fifo/arch/hopper/kernel_fifo_gh100.c --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/kernel/gpu/fifo/arch/hopper/kernel_fifo_gh100.c 2023-10-25 20:20:59.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/kernel/gpu/fifo/arch/hopper/kernel_fifo_gh100.c 2024-03-05 22:13:23.000000000 +0000 @@ -24,6 +24,7 @@ #include "kernel/gpu/fifo/kernel_fifo.h" #include "published/hopper/gh100/dev_vm.h" #include "kernel/gpu/mem_mgr/virt_mem_allocator.h" +#include "gpu/mem_mgr/mem_mgr.h" /*! * Checks the USERD and GPFIFO/PushBuffer location attributes @@ -77,38 +78,49 @@ return; } -/*! - * @brief Get offset to create GMMU internal MMIO mapping with for access to VF Pages. +/* + * Allocate Memory Descriptors for BAR1 VF pages * - * @param[in] pGpu OBJGPU pointer - * @param[in] pKernelFifo KernelFifo pointer - * @param[in] bPriv Whether PRIV offset or regular VF offset is desired + * @param[in] pGpu OBJGPU pointer + * @param[in] pKernelFifo KernelFifo pointer */ -NvU64 -kfifoGetMmioUsermodeOffset_GH100 +NV_STATUS +kfifoConstructUsermodeMemdescs_GH100 ( OBJGPU *pGpu, - KernelFifo *pKernelFifo, - NvBool bPriv + KernelFifo *pKernelFifo ) { - return bPriv ? DRF_BASE(NV_VIRTUAL_FUNCTION_PRIV) : DRF_BASE(NV_VIRTUAL_FUNCTION); -} + MemoryManager *pMemoryManager = GPU_GET_MEMORY_MANAGER(pGpu); + NvU32 attr = 0; + NvU32 attr2 = 0; + NvU32 i = 0; + NV_STATUS status = NV_OK; -/*! - * @brief Get size of either one of the VF pages, for use with GMMU internal MMIO mapping. - * - * @param[in] pGpu OBJGPU pointer - * @param[in] pKernelFifo KernelFifo pointer - * @param[in] bPriv Whether PRIV size or regular VF size is desired - */ -NvU64 -kfifoGetMmioUsermodeSize_GH100 -( - OBJGPU *pGpu, - KernelFifo *pKernelFifo, - NvBool bPriv -) -{ - return bPriv ? DRF_SIZE(NV_VIRTUAL_FUNCTION_PRIV) : DRF_SIZE(NV_VIRTUAL_FUNCTION); + attr = FLD_SET_DRF(OS32, _ATTR, _PHYSICALITY, _CONTIGUOUS, attr); + attr = FLD_SET_DRF(OS32, _ATTR, _COHERENCY, _CACHED, attr); + + attr2 = FLD_SET_DRF(OS32, _ATTR2, _GPU_CACHEABLE, _NO, attr2 ); + + for(i = 0; i < 2; i++) + { + NvBool bPriv = (i==0); + NvU64 offset = bPriv ? DRF_BASE(NV_VIRTUAL_FUNCTION_PRIV) : DRF_BASE(NV_VIRTUAL_FUNCTION); + NvU64 size = bPriv ? DRF_SIZE(NV_VIRTUAL_FUNCTION_PRIV) : DRF_SIZE(NV_VIRTUAL_FUNCTION); + MEMORY_DESCRIPTOR **ppMemDesc = bPriv ? &(pKernelFifo->pBar1PrivVF) : &(pKernelFifo->pBar1VF); + NV_ASSERT_OK_OR_GOTO(status, + memCreateMemDesc(pGpu, ppMemDesc, ADDR_SYSMEM, offset, size, attr, attr2), + err); + memdescSetPteKind(*ppMemDesc, memmgrGetMessageKind_HAL(pGpu, pMemoryManager)); + memdescSetFlag(*ppMemDesc, MEMDESC_FLAGS_MAP_SYSCOH_OVER_BAR1, NV_TRUE); + } + + NV_ASSERT_OK_OR_GOTO(status, + kfifoConstructUsermodeMemdescs_GV100(pGpu, pKernelFifo), + err); + return NV_OK; +err: + memdescDestroy(pKernelFifo->pBar1VF); + memdescDestroy(pKernelFifo->pBar1PrivVF); + return status; } diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/kernel/gpu/fifo/arch/hopper/usermode_api_gh100.c nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/kernel/gpu/fifo/arch/hopper/usermode_api_gh100.c --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/kernel/gpu/fifo/arch/hopper/usermode_api_gh100.c 2023-10-25 20:20:59.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/kernel/gpu/fifo/arch/hopper/usermode_api_gh100.c 1970-01-01 00:00:00.000000000 +0000 @@ -1,121 +0,0 @@ -/* - * SPDX-FileCopyrightText: Copyright (c) 2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. - * SPDX-License-Identifier: MIT - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER - * DEALINGS IN THE SOFTWARE. - */ - -#include "gpu/mem_mgr/mem_mgr.h" -#include "kernel/gpu/fifo/usermode_api.h" -#include "kernel/gpu/fifo/kernel_fifo.h" -#include "kernel/gpu/bus/kern_bus.h" - -#include "class/clc661.h" // HOPPER_USERMODE_A -#include "class/cl003e.h" // NV01_MEMORY_SYSTEM -#include "class/cl003f.h" // NV01_MEMORY_LOCAL_PRIVILEGED - -NV_STATUS -usrmodeConstructHal_GH100 -( - UserModeApi *pUserModeApi, - CALL_CONTEXT *pCallContext, - RS_RES_ALLOC_PARAMS_INTERNAL *pParams -) -{ - Memory *pMemory = staticCast(pUserModeApi, Memory); - NvU32 hClass = pCallContext->pResourceRef->externalClassId; - NvBool bBar1Mapping = NV_FALSE; - NvBool bPriv = NV_FALSE; - NV_HOPPER_USERMODE_A_PARAMS *pAllocParams = (NV_HOPPER_USERMODE_A_PARAMS*)pParams->pAllocParams; - NV_STATUS status = NV_OK; - MEMORY_DESCRIPTOR *pMemDesc = NULL; - OBJGPU *pGpu = pMemory->pGpu; - KernelFifo *pKernelFifo = GPU_GET_KERNEL_FIFO(pGpu); - KernelBus *pKernelBus = GPU_GET_KERNEL_BUS(pGpu); - MemoryManager *pMemoryManager = GPU_GET_MEMORY_MANAGER(pGpu); - NvU64 offset = 0; - NvU32 size = 0; - NvU32 attr = 0; - NvU32 attr2 = 0; - - attr = FLD_SET_DRF(OS32, _ATTR, _PHYSICALITY, _CONTIGUOUS, attr); - attr = FLD_SET_DRF(OS32, _ATTR, _COHERENCY, _CACHED, attr); - - attr2 = FLD_SET_DRF(OS32, _ATTR2, _GPU_CACHEABLE, _NO, attr2 ); - - if (hClass >= HOPPER_USERMODE_A && pAllocParams != NULL) - { - bBar1Mapping = pAllocParams->bBar1Mapping; - bPriv = pAllocParams->bPriv; - } - - // BAR1/2 is not used on coherent platforms like SHH, so use BAR0 path instead - if (pGpu->getProperty(pGpu, PDB_PROP_GPU_COHERENT_CPU_MAPPING)) - { - bBar1Mapping = NV_FALSE; - } - - // - // If we are in inst_in_sys mode, BAR1 page tables are not used so we cannot - // support internal MMIO for work submission. - // It is safe to return BAR0 mapping here because USERD cannot be in vidmem - // anyway so UMDs can use this mapping transparently. - // TODO: we should rename bBar1Mapping to accommodate cases where RM - // transparently gives out BAR0 mappings instead. - // - if (bBar1Mapping && pGpu->getProperty(pGpu, PDB_PROP_GPU_IS_ALL_INST_IN_SYSMEM)) - { - NV_ASSERT_OR_RETURN(kbusIsBar1PhysicalModeEnabled(pKernelBus), - NV_ERR_INVALID_STATE); - bBar1Mapping = NV_FALSE; - } - - if (bPriv && pCallContext->secInfo.privLevel < RS_PRIV_LEVEL_KERNEL) - { - return NV_ERR_INSUFFICIENT_PERMISSIONS; - } - - NV_ASSERT_OK_OR_RETURN(kfifoGetUsermodeMapInfo_HAL(pGpu, pKernelFifo, &offset, &size)); - - if (bBar1Mapping) - { - offset = kfifoGetMmioUsermodeOffset_HAL(pGpu, pKernelFifo, bPriv); - size = kfifoGetMmioUsermodeSize_HAL(pGpu, pKernelFifo, bPriv); - } - - status = memCreateMemDesc(pGpu, &pMemDesc, bBar1Mapping ? ADDR_SYSMEM : ADDR_REGMEM, - offset, size, attr, attr2); - - NV_CHECK_OK_OR_RETURN(LEVEL_ERROR, status); - - if (bBar1Mapping) - { - memdescSetPteKind(pMemDesc, memmgrGetMessageKind_HAL(pGpu, pMemoryManager)); - memdescSetFlag(pMemDesc, MEMDESC_FLAGS_MAP_SYSCOH_OVER_BAR1, NV_TRUE); - } - else - { - memdescSetFlag(pMemDesc, MEMDESC_FLAGS_SKIP_REGMEM_PRIV_CHECK, NV_TRUE); - } - - status = memConstructCommon(pMemory, bBar1Mapping? NV01_MEMORY_SYSTEM : NV01_MEMORY_LOCAL_PRIVILEGED, - 0, pMemDesc, 0, NULL, 0, 0, 0, 0, NVOS32_MEM_TAG_NONE, NULL); - - return status; -} diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/kernel/gpu/fifo/arch/maxwell/kernel_channel_gm107.c nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/kernel/gpu/fifo/arch/maxwell/kernel_channel_gm107.c --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/kernel/gpu/fifo/arch/maxwell/kernel_channel_gm107.c 2023-10-25 20:20:59.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/kernel/gpu/fifo/arch/maxwell/kernel_channel_gm107.c 2024-03-05 22:13:24.000000000 +0000 @@ -48,43 +48,31 @@ NV_STATUS kchannelGetClassEngineID_GM107 ( - OBJGPU *pGpu, - KernelChannel *pKernelChannel, - NvHandle handle, - NvU32 *pClassEngineID, - NvU32 *pClassID, + OBJGPU *pGpu, + KernelChannel *pKernelChannel, + NvHandle handle, + NvU32 *pClassEngineID, + NvU32 *pClassID, RM_ENGINE_TYPE *pRmEngineID ) { - NV_STATUS status = NV_OK; - NvU32 halEngineTag = 0; - NvU32 hwEngineID = 0; - NvU32 classID; - KernelFifo *pKernelFifo = GPU_GET_KERNEL_FIFO(pGpu); - ChannelDescendant *pObject = NULL; + NV_STATUS status = NV_OK; + NvU32 halEngineTag; + NvU32 classID; + ChannelDescendant *pObject = NULL; - NV_CHECK_OK_OR_RETURN(LEVEL_INFO, kchannelFindChildByHandle(pKernelChannel, handle, &pObject)); + NV_CHECK_OK_OR_RETURN(LEVEL_INFO, + kchannelFindChildByHandle(pKernelChannel, handle, &pObject)); NV_ASSERT_OR_RETURN(pObject != NULL, NV_ERR_OBJECT_NOT_FOUND); *pClassID = classID = RES_GET_EXT_CLASS_ID(pObject); halEngineTag = pObject->resourceDesc.engDesc; - status = kfifoEngineInfoXlate_HAL(pGpu, pKernelFifo, ENGINE_INFO_TYPE_ENG_DESC, - halEngineTag, ENGINE_INFO_TYPE_FIFO_TAG, &hwEngineID); - if (halEngineTag == ENG_SW) { classID = pObject->classID; } - if (status != NV_OK) - { - NV_PRINTF(LEVEL_ERROR, - ": Invalid Engine Tag %x associated with object handle = %x\n", - halEngineTag, handle); - return NV_ERR_OBJECT_NOT_FOUND; - } - status = gpuXlateEngDescToClientEngineId(pGpu, halEngineTag, pRmEngineID); if (status == NV_OK) @@ -93,8 +81,8 @@ } NV_PRINTF(LEVEL_INFO, - "class ID: 0x%08x engine id 0x%08x classEngine ID: 0x%08x\n", - classID, hwEngineID, *pClassEngineID); + "class ID: 0x%08x classEngine ID: 0x%08x\n", + classID, *pClassEngineID); return status; } diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/kernel/gpu/fifo/arch/maxwell/kernel_channel_group_gm107.c nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/kernel/gpu/fifo/arch/maxwell/kernel_channel_group_gm107.c --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/kernel/gpu/fifo/arch/maxwell/kernel_channel_group_gm107.c 2023-10-25 20:20:59.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/kernel/gpu/fifo/arch/maxwell/kernel_channel_group_gm107.c 1970-01-01 00:00:00.000000000 +0000 @@ -1,62 +0,0 @@ -/* - * SPDX-FileCopyrightText: Copyright (c) 1993-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. - * SPDX-License-Identifier: MIT - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER - * DEALINGS IN THE SOFTWARE. - */ - -#include "core/core.h" - -#include "kernel/gpu/fifo/kernel_channel_group.h" - -/** - * @brief Gets the default runlist id to use for TSGs allocated with no engines on them. - * - * @param[in] pGpu - * @param[in] pKernelChannelGroup - TSG to retrieve default runlist id for - */ -NvU32 -kchangrpGetDefaultRunlist_GM107 -( - OBJGPU *pGpu, - KernelChannelGroup *pKernelChannelGroup -) -{ - KernelFifo *pKernelFifo = GPU_GET_KERNEL_FIFO(pGpu); - NvU32 runlistId = INVALID_RUNLIST_ID; - ENGDESCRIPTOR engDesc = ENG_GR(0); - - if (RM_ENGINE_TYPE_IS_VALID(pKernelChannelGroup->engineType)) - { - // if translation fails, default is GR0 - NV_ASSERT_OK(kfifoEngineInfoXlate_HAL(pGpu, pKernelFifo, - ENGINE_INFO_TYPE_RM_ENGINE_TYPE, - (NvU32)pKernelChannelGroup->engineType, - ENGINE_INFO_TYPE_ENG_DESC, - &engDesc)); - } - - // if translation fails, defualt is INVALID_RUNLIST_ID - NV_ASSERT_OK( - kfifoEngineInfoXlate_HAL(pGpu, pKernelFifo, - ENGINE_INFO_TYPE_ENG_DESC, engDesc, - ENGINE_INFO_TYPE_RUNLIST, &runlistId)); - - return runlistId; -} diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/kernel/gpu/fifo/arch/maxwell/kernel_fifo_gm107.c nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/kernel/gpu/fifo/arch/maxwell/kernel_fifo_gm107.c --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/kernel/gpu/fifo/arch/maxwell/kernel_fifo_gm107.c 2023-10-25 20:20:59.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/kernel/gpu/fifo/arch/maxwell/kernel_fifo_gm107.c 2024-03-05 22:13:24.000000000 +0000 @@ -37,11 +37,16 @@ #include "published/maxwell/gm107/dev_ram.h" #include "published/maxwell/gm107/dev_mmu.h" + +static inline NvBool +_isEngineInfoTypeValidForOnlyHostDriven(ENGINE_INFO_TYPE type); + + /*! Construct kfifo object */ NV_STATUS kfifoConstructHal_GM107 ( - OBJGPU *pGpu, + OBJGPU *pGpu, KernelFifo *pKernelFifo ) { @@ -380,15 +385,19 @@ // if translation fails, defualt is ENG_GR(0) NV_ASSERT_OK( kfifoEngineInfoXlate_HAL(pGpu, pKernelFifo, - ENGINE_INFO_TYPE_RM_ENGINE_TYPE, (NvU32)rmEngineType, - ENGINE_INFO_TYPE_ENG_DESC, &engDesc)); + ENGINE_INFO_TYPE_RM_ENGINE_TYPE, (NvU32)rmEngineType, + ENGINE_INFO_TYPE_ENG_DESC, &engDesc)); } - // if translation fails, defualt is INVALID_RUNLIST_ID - NV_ASSERT_OK( - kfifoEngineInfoXlate_HAL(pGpu, pKernelFifo, - ENGINE_INFO_TYPE_ENG_DESC, engDesc, - ENGINE_INFO_TYPE_RUNLIST, &runlistId)); + // if translation fails, default is INVALID_RUNLIST_ID + if (kfifoEngineInfoXlate_HAL(pGpu, pKernelFifo, + ENGINE_INFO_TYPE_ENG_DESC, + engDesc, + ENGINE_INFO_TYPE_RUNLIST, + &runlistId) != NV_OK) + { + runlistId = INVALID_RUNLIST_ID; + } return runlistId; } @@ -661,34 +670,54 @@ return NV_ERR_INVALID_CHANNEL; } -/** - * @brief Translates between 2 engine values - * - * To iterate through a value for all engines call with inType of - * ENGINE_INFO_TYPE_INVALID for 0 through fifoGetNumEngines(). - * - * @param pGpu - * @param pKernelFifo - * @param[in] inType ENGINE_INFO_TYPE_* - * @param[in] inVal - * @param[in] outType ENGINE_INFO_TYPE_* - * @param[out] pOutVal - */ +static inline NvBool +_isEngineInfoTypeValidForOnlyHostDriven(ENGINE_INFO_TYPE type) +{ + switch (type) + { + case ENGINE_INFO_TYPE_RUNLIST: + case ENGINE_INFO_TYPE_RUNLIST_PRI_BASE: + case ENGINE_INFO_TYPE_RUNLIST_ENGINE_ID: + case ENGINE_INFO_TYPE_PBDMA_ID: + case ENGINE_INFO_TYPE_CHRAM_PRI_BASE: + case ENGINE_INFO_TYPE_FIFO_TAG: + return NV_TRUE; + case ENGINE_INFO_TYPE_ENG_DESC: + case ENGINE_INFO_TYPE_RM_ENGINE_TYPE: + case ENGINE_INFO_TYPE_MMU_FAULT_ID: + case ENGINE_INFO_TYPE_RC_MASK: + case ENGINE_INFO_TYPE_RESET: + case ENGINE_INFO_TYPE_INTR: + case ENGINE_INFO_TYPE_MC: + case ENGINE_INFO_TYPE_DEV_TYPE_ENUM: + case ENGINE_INFO_TYPE_INSTANCE_ID: + case ENGINE_INFO_TYPE_IS_HOST_DRIVEN_ENGINE: + // The bool itself is valid for non-host-driven engines too. + case ENGINE_INFO_TYPE_INVALID: + return NV_FALSE; + default: + // Ensure that this function covers every value in ENGINE_INFO_TYPE + NV_ASSERT(0 && "check all ENGINE_INFO_TYPE are classified as host-driven or not"); + return NV_FALSE; + } +} + + NV_STATUS kfifoEngineInfoXlate_GM107 ( - OBJGPU *pGpu, - KernelFifo *pKernelFifo, - ENGINE_INFO_TYPE inType, - NvU32 inVal, - ENGINE_INFO_TYPE outType, - NvU32 *pOutVal + OBJGPU *pGpu, + KernelFifo *pKernelFifo, + ENGINE_INFO_TYPE inType, + NvU32 inVal, + ENGINE_INFO_TYPE outType, + NvU32 *pOutVal ) { - const ENGINE_INFO *pEngineInfo = kfifoGetEngineInfo(pKernelFifo); - NvU32 i; + const ENGINE_INFO *pEngineInfo = kfifoGetEngineInfo(pKernelFifo); + FIFO_ENGINE_LIST *pFoundInputEngine = NULL; - NV_ASSERT_OR_RETURN(pOutVal, NV_ERR_INVALID_ARGUMENT); + NV_ASSERT_OR_RETURN(pOutVal != NULL, NV_ERR_INVALID_ARGUMENT); // PBDMA_ID can only be inType NV_ASSERT_OR_RETURN(outType != ENGINE_INFO_TYPE_PBDMA_ID, @@ -697,49 +726,70 @@ if (pEngineInfo == NULL) { NV_ASSERT_OK_OR_RETURN(kfifoConstructEngineList_HAL(pGpu, pKernelFifo)); - pEngineInfo = kfifoGetEngineInfo(pKernelFifo); - NV_ASSERT_OR_RETURN(pEngineInfo != NULL, NV_ERR_INVALID_STATE); } + NV_ASSERT_OR_RETURN(pEngineInfo != NULL, NV_ERR_INVALID_STATE); if (inType == ENGINE_INFO_TYPE_INVALID) { NV_ASSERT_OR_RETURN(inVal < pEngineInfo->engineInfoListSize, NV_ERR_INVALID_ARGUMENT); - *pOutVal = pEngineInfo->engineInfoList[inVal].engineData[outType]; - return NV_OK; + pFoundInputEngine = &pEngineInfo->engineInfoList[inVal]; } - - for (i = 0; i < pEngineInfo->engineInfoListSize; ++i) + else { - FIFO_ENGINE_LIST *pFifoEngineList = &pEngineInfo->engineInfoList[i]; - NvBool bFound = NV_FALSE; - - if (inType == ENGINE_INFO_TYPE_PBDMA_ID) + NvU32 i; + for (i = 0; + (i < pEngineInfo->engineInfoListSize) && + (pFoundInputEngine == NULL); + ++i) { - NvU32 j; - for (j = 0; j < pFifoEngineList->numPbdmas; ++j) + FIFO_ENGINE_LIST *pThisEngine = &pEngineInfo->engineInfoList[i]; + + if (inType == ENGINE_INFO_TYPE_PBDMA_ID) { - if (pFifoEngineList->pbdmaIds[j] == inVal) + NvU32 j; + for (j = 0; j < pThisEngine->numPbdmas; ++j) { - bFound = NV_TRUE; - break; + if (pThisEngine->pbdmaIds[j] == inVal) + { + pFoundInputEngine = pThisEngine; + break; + } } } + else if (pThisEngine->engineData[inType] == inVal) + { + pFoundInputEngine = pThisEngine; + } } - else if (pFifoEngineList->engineData[inType] == inVal) - { - bFound = NV_TRUE; - } + } - if (bFound) - { - *pOutVal = pFifoEngineList->engineData[outType]; - return NV_OK; - } + if (pFoundInputEngine == NULL) + { + return NV_ERR_OBJECT_NOT_FOUND; } - return NV_ERR_INVALID_ARGUMENT; + if (_isEngineInfoTypeValidForOnlyHostDriven(outType) && + !pFoundInputEngine->engineData[ENGINE_INFO_TYPE_IS_HOST_DRIVEN_ENGINE]) + { + // + // Bug 3748452 TODO + // Bug 3772199 TODO + // + // We can't easily just return an error here because hundreds of + // callsites would fail their asserts. The above two bugs track fixing + // all callsites after which, we can uncomment this. + // + // return NV_ERR_OBJECT_NOT_FOUND; + // + NV_PRINTF(LEVEL_ERROR, + "Asked for host-specific type(0x%x) for non-host engine type(0x%x),val(0x%08x)\n", + outType, inType, inVal); + } + + *pOutVal = pFoundInputEngine->engineData[outType]; + return NV_OK; } /** @@ -761,22 +811,15 @@ void kfifoSetupUserD_GM107 ( + OBJGPU *pGpu, KernelFifo *pKernelFifo, - NvU8 *pUserD + MEMORY_DESCRIPTOR *pMemDesc ) { - NV_ASSERT_OR_RETURN_VOID(pUserD != NULL); + TRANSFER_SURFACE tSurf = {.pMemDesc = pMemDesc, .offset = 0}; - MEM_WR32( pUserD + SF_OFFSET( NV_RAMUSERD_PUT ), 0 ); - MEM_WR32( pUserD + SF_OFFSET( NV_RAMUSERD_GET ), 0 ); - MEM_WR32( pUserD + SF_OFFSET( NV_RAMUSERD_REF ), 0 ); - MEM_WR32( pUserD + SF_OFFSET( NV_RAMUSERD_PUT_HI ), 0 ); - MEM_WR32( pUserD + SF_OFFSET( NV_RAMUSERD_REF_THRESHOLD ), 0 ); - MEM_WR32( pUserD + SF_OFFSET( NV_RAMUSERD_GP_TOP_LEVEL_GET ), 0 ); - MEM_WR32( pUserD + SF_OFFSET( NV_RAMUSERD_GP_TOP_LEVEL_GET_HI ), 0 ); - MEM_WR32( pUserD + SF_OFFSET( NV_RAMUSERD_GET_HI ), 0 ); - MEM_WR32( pUserD + SF_OFFSET( NV_RAMUSERD_GP_GET ), 0 ); - MEM_WR32( pUserD + SF_OFFSET( NV_RAMUSERD_GP_PUT ), 0 ); + NV_ASSERT_OK(memmgrMemSet(GPU_GET_MEMORY_MANAGER(pGpu), &tSurf, 0, + NV_RAMUSERD_CHAN_SIZE, TRANSFER_FLAGS_NONE)); } /** * @brief return number of HW engines @@ -1247,7 +1290,7 @@ // Now BAR1 map it status = kbusMapFbAperture_HAL(pGpu, pKernelBus, pUserdInfo->userdPhysDesc[currentGpuInst], 0, &pUserdInfo->userdBar1MapStartOffset, - &temp, mapFlags | BUS_MAP_FB_FLAGS_PRE_INIT, NV01_NULL_OBJECT); + &temp, mapFlags | BUS_MAP_FB_FLAGS_PRE_INIT, NULL); } if (status != NV_OK) @@ -1492,14 +1535,14 @@ NvBool *pPresent ) { - NvU32 tmp; + NvU32 bEschedDriven = NV_FALSE; NV_STATUS status; status = kfifoEngineInfoXlate_HAL(pGpu, pKernelFifo, - ENGINE_INFO_TYPE_ENG_DESC, engDesc, - ENGINE_INFO_TYPE_FIFO_TAG, &tmp); + ENGINE_INFO_TYPE_ENG_DESC, engDesc, + ENGINE_INFO_TYPE_IS_HOST_DRIVEN_ENGINE, &bEschedDriven); - *pPresent = (status == NV_OK); + *pPresent = (status == NV_OK) && bEschedDriven; return NV_OK; } diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/kernel/gpu/fifo/arch/volta/kernel_channel_group_gv100.c nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/kernel/gpu/fifo/arch/volta/kernel_channel_group_gv100.c --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/kernel/gpu/fifo/arch/volta/kernel_channel_group_gv100.c 2023-10-25 20:20:59.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/kernel/gpu/fifo/arch/volta/kernel_channel_group_gv100.c 2024-03-05 22:13:24.000000000 +0000 @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 2021 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2021-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -43,14 +43,15 @@ NV_STATUS status = NV_OK; NvU32 bufSizeInBytes = 0; KernelFifo *pKernelFifo = GPU_GET_KERNEL_FIFO(pGpu); + MemoryManager *pMemoryManager = GPU_GET_MEMORY_MANAGER(pGpu); NvU32 runQueues = kfifoGetNumRunqueues_HAL(pGpu, pKernelFifo); NvU32 index = 0; NvU32 faultBufApert = ADDR_SYSMEM; NvU32 faultBufAttr = NV_MEMORY_CACHED; - NvU8 *pRmMapAddr = NULL; NvU64 memDescFlags = MEMDESC_FLAGS_LOST_ON_SUSPEND; HW_ENG_FAULT_METHOD_BUFFER *pFaultMthdBuf = NULL; NvU32 gfid = pKernelChannelGroup->gfid; + TRANSFER_SURFACE surf = {0}; // // Allocate method buffer if applicable @@ -122,21 +123,12 @@ memdescSetName(pGpu, pFaultMthdBuf->pMemDesc, NV_RM_SURF_NAME_CE_FAULT_METHOD_BUFFER, NULL); - // Map the buffer to RM - pRmMapAddr = kbusMapRmAperture_HAL(pGpu, pFaultMthdBuf->pMemDesc); - if (!pRmMapAddr) - { - status = NV_ERR_INVALID_ADDRESS; - goto fail; - } - - // Memset to 0 - portMemSet(pRmMapAddr, 0, bufSizeInBytes); + surf.pMemDesc = pFaultMthdBuf->pMemDesc; + surf.offset = 0; - // Unmap the buffer from RM - kbusUnmapRmAperture_HAL(pGpu, pFaultMthdBuf->pMemDesc, &(pRmMapAddr), - NV_TRUE); - pRmMapAddr = NULL; + NV_ASSERT_OK_OR_RETURN( + memmgrMemSet(pMemoryManager, &surf, 0, bufSizeInBytes, + TRANSFER_FLAGS_NONE)); pFaultMthdBuf->bar2Addr = 0; } diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/kernel/gpu/fifo/arch/volta/kernel_channel_gv100.c nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/kernel/gpu/fifo/arch/volta/kernel_channel_gv100.c --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/kernel/gpu/fifo/arch/volta/kernel_channel_gv100.c 2023-10-25 20:21:00.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/kernel/gpu/fifo/arch/volta/kernel_channel_gv100.c 2024-03-05 22:13:24.000000000 +0000 @@ -170,7 +170,7 @@ NvU32 userdAddrLo; NvU32 userdAddrHi; NvU32 userdAlignment; - NvU32 pageSize; + NvU64 pageSize; NV_ASSERT_OR_RETURN(!gpumgrGetBcEnabledStatus(pGpu), NV_ERR_INVALID_STATE); pKernelChannel->pUserdSubDeviceMemDesc[gpumgrGetSubDeviceInstanceFromGpu(pGpu)] = NULL; @@ -203,6 +203,15 @@ AT_GPU, userdOffset); + // Adjust for the DMA window start address, if any + if (memdescGetAddressSpace(pUserdMemDescForSubDev) == ADDR_SYSMEM) + { + RmPhysAddr dmaWindowStart = gpuGetDmaStartAddress(pGpu); + NV_ASSERT_OR_RETURN(userdAddr > dmaWindowStart, NV_ERR_INVALID_ADDRESS); + + userdAddr -= dmaWindowStart; + } + userdAddrLo = NvU64_LO32(userdAddr) >> userdShift; userdAddrHi = NvU64_HI32(userdAddr); diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/kernel/gpu/fifo/arch/volta/kernel_fifo_gv100.c nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/kernel/gpu/fifo/arch/volta/kernel_fifo_gv100.c --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/kernel/gpu/fifo/arch/volta/kernel_fifo_gv100.c 2023-10-25 20:21:00.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/kernel/gpu/fifo/arch/volta/kernel_fifo_gv100.c 2024-03-05 22:13:24.000000000 +0000 @@ -28,6 +28,7 @@ #include "kernel/gpu/fifo/kernel_channel.h" #include "kernel/rmapi/rmapi.h" #include "kernel/gpu/gpu.h" +#include "kernel/mem_mgr/mem.h" #include "nvRmReg.h" @@ -92,19 +93,6 @@ return NV_OK; } -/** - * @brief Translates between 2 engine values - * - * To iterate through a value for all engines call with inType of - * ENGINE_INFO_TYPE_INVALID for 0 through fifoGetNumEngines(). - * - * @param pGpu - * @param pKernelFifo - * @param[in] inType ENGINE_INFO_TYPE_* - * @param[in] inVal - * @param[in] outType ENGINE_INFO_TYPE_* - * @param[out] pOutVal - */ NV_STATUS kfifoEngineInfoXlate_GV100 ( @@ -349,3 +337,36 @@ return numChannels; } + +/* + * Allocate Memory Descriptors for Regmem VF page + * + * @param[in] pGpu OBJGPU pointer + * @param[in] pKernelFifo KernelFifo pointer + */ +NV_STATUS +kfifoConstructUsermodeMemdescs_GV100 +( + OBJGPU *pGpu, + KernelFifo *pKernelFifo +) +{ + NvU32 attr = 0; + NvU32 attr2 = 0; + NvU64 offset = 0; + NvU32 size = 0; + + attr = FLD_SET_DRF(OS32, _ATTR, _PHYSICALITY, _CONTIGUOUS, attr); + attr = FLD_SET_DRF(OS32, _ATTR, _COHERENCY, _CACHED, attr); + + attr2 = FLD_SET_DRF(OS32, _ATTR2, _GPU_CACHEABLE, _NO, attr2); + + NV_ASSERT_OK_OR_RETURN(kfifoGetUsermodeMapInfo_HAL(pGpu, pKernelFifo, &offset, &size)); + + NV_ASSERT_OK_OR_RETURN(memCreateMemDesc(pGpu, &(pKernelFifo->pRegVF), ADDR_REGMEM, + offset, size, attr, attr2)); + + memdescSetFlag(pKernelFifo->pRegVF, MEMDESC_FLAGS_SKIP_REGMEM_PRIV_CHECK, NV_TRUE); + + return NV_OK; +} diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/kernel/gpu/fifo/arch/volta/usermode_api_gv100.c nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/kernel/gpu/fifo/arch/volta/usermode_api_gv100.c --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/kernel/gpu/fifo/arch/volta/usermode_api_gv100.c 2023-10-25 20:21:00.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/kernel/gpu/fifo/arch/volta/usermode_api_gv100.c 1970-01-01 00:00:00.000000000 +0000 @@ -1,66 +0,0 @@ -/* - * SPDX-FileCopyrightText: Copyright (c) 2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. - * SPDX-License-Identifier: MIT - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER - * DEALINGS IN THE SOFTWARE. - */ - -#include "kernel/gpu/fifo/usermode_api.h" -#include "kernel/gpu/fifo/kernel_fifo.h" - -#include "class/cl003e.h" // NV01_MEMORY_SYSTEM -#include "class/cl003f.h" // NV01_MEMORY_LOCAL_PRIVILEGED - -NV_STATUS -usrmodeConstructHal_GV100 -( - UserModeApi *pUserModeApi, - CALL_CONTEXT *pCallContext, - RS_RES_ALLOC_PARAMS_INTERNAL *pParams -) -{ - Memory *pMemory = staticCast(pUserModeApi, Memory); - NV_STATUS status = NV_OK; - MEMORY_DESCRIPTOR *pMemDesc = NULL; - OBJGPU *pGpu = pMemory->pGpu; - KernelFifo *pKernelFifo = GPU_GET_KERNEL_FIFO(pGpu); - NvU64 offset = 0; - NvU32 size = 0; - NvU32 attr = 0; - NvU32 attr2 = 0; - - attr = FLD_SET_DRF(OS32, _ATTR, _PHYSICALITY, _CONTIGUOUS, attr); - attr = FLD_SET_DRF(OS32, _ATTR, _COHERENCY, _CACHED, attr); - - attr2 = FLD_SET_DRF(OS32, _ATTR2, _GPU_CACHEABLE, _NO, attr2 ); - - NV_ASSERT_OK_OR_RETURN(kfifoGetUsermodeMapInfo_HAL(pGpu, pKernelFifo, &offset, &size)); - - status = memCreateMemDesc(pGpu, &pMemDesc, ADDR_REGMEM, - offset, size, attr, attr2); - - NV_CHECK_OK_OR_RETURN(LEVEL_ERROR, status); - - memdescSetFlag(pMemDesc, MEMDESC_FLAGS_SKIP_REGMEM_PRIV_CHECK, NV_TRUE); - - status = memConstructCommon(pMemory, NV01_MEMORY_LOCAL_PRIVILEGED, - 0, pMemDesc, 0, NULL, 0, 0, 0, 0, NVOS32_MEM_TAG_NONE, NULL); - - return status; -} diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/kernel/gpu/fifo/channel_descendant.c nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/kernel/gpu/fifo/channel_descendant.c --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/kernel/gpu/fifo/channel_descendant.c 2023-10-25 20:21:00.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/kernel/gpu/fifo/channel_descendant.c 2024-03-05 22:13:24.000000000 +0000 @@ -141,7 +141,7 @@ partnerParams.runqueue = kchannelGetRunqueue(pKernelChannel); NV_ASSERT_OK_OR_RETURN(kfifoGetEnginePartnerList_HAL(pGpu, pKernelFifo, &partnerParams)); NV_ASSERT_OR_RETURN(partnerParams.numPartners == 1, NV_ERR_INVALID_STATE); - rmEngineType = gpuGetRmEngineType(partnerParams.partnerList[0]); + rmEngineType = gpuGetRmEngineType(partnerParams.partnerList[0]); } // Get the engDesc from engineType @@ -164,7 +164,7 @@ // ENGDESCRIPTOR engDesc = pParamToEngDescFn(pGpu, pParams->externalClassId, pParams->pAllocParams); - + if (rmapiutilIsExternalClassIdInternalOnly(pParams->externalClassId)) { // @@ -213,25 +213,25 @@ // engDesc = MKENGDESC(classId(KernelGraphics), GET_GR_IDX(engDesc)); } - else if (IS_CE(engDesc) && gpuGetEngstate(pGpu, engDesc) == NULL) - { - // If CE is missing, check for KCE instead - engDesc = MKENGDESC(classId(KernelCE), GET_CE_IDX(engDesc)); - } - - void *pEngObject = gpuGetEngstate(pGpu, engDesc); // - // In a kernel-only config, falcons are represented by KernelFalcons and do not have an - // engstate. + // skip checking engstate for CE, engine guaranteed to exist if pParamToEngDescFn is succesful // - if (pEngObject == NULL) - pEngObject = kflcnGetKernelFalconForEngine(pGpu, engDesc); - - if (pEngObject == NULL) + if (!IS_CE(engDesc)) { - NV_PRINTF(LEVEL_ERROR, "engine is missing for class 0x%x\n", - pParams->externalClassId); - return NV_ERR_INVALID_CLASS; + void *pEngObject = gpuGetEngstate(pGpu, engDesc); + // + // In a kernel-only config, falcons are represented by KernelFalcons and do not have an + // engstate. + // + if (pEngObject == NULL) + pEngObject = kflcnGetKernelFalconForEngine(pGpu, engDesc); + + if (pEngObject == NULL) + { + NV_PRINTF(LEVEL_ERROR, "engine is missing for class 0x%x\n", + pParams->externalClassId); + return NV_ERR_INVALID_CLASS; + } } pChannelDescendant->pKernelChannel = pKernelChannel; @@ -282,7 +282,7 @@ chandesGetSwMethods_IMPL ( ChannelDescendant *pChannelDescendant, - METHOD **ppMethods, + const METHOD **ppMethods, NvU32 *pNumMethods ) { @@ -301,7 +301,6 @@ ( OBJGPU *pGpu, ChannelDescendant *Object, - PMETHOD Method, NvU32 Offset, NvU32 Data ) diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/kernel/gpu/fifo/kernel_channel.c nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/kernel/gpu/fifo/kernel_channel.c --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/kernel/gpu/fifo/kernel_channel.c 2023-10-25 20:21:00.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/kernel/gpu/fifo/kernel_channel.c 2024-03-05 22:13:25.000000000 +0000 @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 2020-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2020-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -21,10 +21,15 @@ * DEALINGS IN THE SOFTWARE. */ +// FIXME XXX +#define NVOC_KERNEL_GRAPHICS_CONTEXT_H_PRIVATE_ACCESS_ALLOWED +#define NVOC_KERNEL_CHANNEL_H_PRIVATE_ACCESS_ALLOWED + #include "kernel/gpu/fifo/kernel_channel.h" #include "kernel/core/locks.h" #include "kernel/diagnostics/gpu_acct.h" +#include "kernel/gpu/conf_compute/conf_compute.h" #include "kernel/gpu/device/device.h" #include "kernel/gpu/fifo/kernel_ctxshare.h" #include "kernel/gpu/fifo/kernel_channel_group.h" @@ -42,6 +47,7 @@ #include "kernel/virtualization/hypervisor/hypervisor.h" #include "gpu/bus/kern_bus.h" #include "gpu/mem_mgr/virt_mem_allocator.h" +#include "objtmr.h" #include "class/cl0090.h" // KERNEL_GRAPHICS_CONTEXT #include "class/cl906fsw.h" // GF100_GPFIFO @@ -162,6 +168,7 @@ NvBool bFullSriov = IS_VIRTUAL_WITH_SRIOV(pGpu) && !gpuIsWarBug200577889SriovHeavyEnabled(pGpu); NvBool bAddedToGroup = NV_FALSE; NvU32 callingContextGfid; + Device *pDevice; // We only support physical channels. NV_ASSERT_OR_RETURN(FLD_TEST_DRF(OS04, _FLAGS, _CHANNEL_TYPE, _PHYSICAL, flags), @@ -180,6 +187,8 @@ NV_ASSERT_OK_OR_GOTO(status, refFindAncestorOfType(pResourceRef, classId(Device), &pDeviceRef), cleanup); NV_ASSERT_OK_OR_RETURN(vgpuGetCallingContextGfid(pGpu, &callingContextGfid)); + pDevice = dynamicCast(pDeviceRef->pResource, Device); + // Internal fields must be cleared when RMAPI call is from client if (!hypervisorIsVgxHyper() || IS_GSP_CLIENT(pGpu)) pChannelGpfifoParams->hPhysChannelGroup = NV01_NULL_OBJECT; @@ -190,6 +199,9 @@ sizeof pChannelGpfifoParams->eccErrorNotifierMem); pChannelGpfifoParams->ProcessID = 0; pChannelGpfifoParams->SubProcessID = 0; + portMemSet(pChannelGpfifoParams->encryptIv, 0, sizeof(pChannelGpfifoParams->encryptIv)); + portMemSet(pChannelGpfifoParams->decryptIv, 0, sizeof(pChannelGpfifoParams->decryptIv)); + portMemSet(pChannelGpfifoParams->hmacNonce, 0, sizeof(pChannelGpfifoParams->hmacNonce)); pRmClient = dynamicCast(pRsClient, RmClient); if (pRmClient == NULL) @@ -299,8 +311,6 @@ } } - - // Find the TSG, or create the TSG if we need to wrap it status = clientGetResourceRefByType(pRsClient, hParent, classId(KernelChannelGroupApi), @@ -336,6 +346,7 @@ &pChannelGpfifoParams->hPhysChannelGroup, KEPLER_CHANNEL_GROUP_A, NV_PTR_TO_NvP64(&tsgParams), + sizeof(tsgParams), RMAPI_ALLOC_FLAGS_SKIP_RPC, NvP64_NULL, &pRmApi->defaultSecInfo); @@ -647,7 +658,8 @@ NV_CHECK_OK_OR_GOTO( status, LEVEL_ERROR, - kmigmgrGetInstanceRefFromClient(pGpu, pKernelMIGManager, hClient, &ref), + kmigmgrGetInstanceRefFromDevice(pGpu, pKernelMIGManager, + pDevice, &ref), cleanup); NV_CHECK_OK_OR_GOTO( @@ -681,11 +693,44 @@ // Determine initial runlist ID (based on engine type if provided or inherited from TSG) pKernelChannel->runlistId = kfifoGetDefaultRunlist_HAL(pGpu, pKernelFifo, pKernelChannel->engineType); + pKernelChannel->bCCSecureChannel = FLD_TEST_DRF(OS04, _FLAGS, _CC_SECURE, _TRUE, flags); + if (pKernelChannel->bCCSecureChannel) + { + ConfidentialCompute* pConfCompute = GPU_GET_CONF_COMPUTE(pGpu); + + // return early if gpu is not ready to accept work + if (pConfCompute && kchannelCheckIsUserMode(pKernelChannel) + && !confComputeAcceptClientRequest(pGpu, pConfCompute)) + { + return NV_ERR_NOT_READY; + } + + status = kchannelRetrieveKmb_HAL(pGpu, pKernelChannel, ROTATE_IV_ALL_VALID, + NV_TRUE, &pKernelChannel->clientKmb); + NV_ASSERT_OR_GOTO(status == NV_OK, cleanup); + + portMemCopy(pChannelGpfifoParams->encryptIv, + sizeof(pChannelGpfifoParams->encryptIv), + pKernelChannel->clientKmb.encryptBundle.iv, + sizeof(pKernelChannel->clientKmb.encryptBundle.iv)); + + portMemCopy(pChannelGpfifoParams->decryptIv, + sizeof(pChannelGpfifoParams->decryptIv), + pKernelChannel->clientKmb.decryptBundle.iv, + sizeof(pKernelChannel->clientKmb.decryptBundle.iv)); + + portMemCopy(pChannelGpfifoParams->hmacNonce, + sizeof(pChannelGpfifoParams->hmacNonce), + pKernelChannel->clientKmb.hmacBundle.nonce, + sizeof(pKernelChannel->clientKmb.hmacBundle.nonce)); + + } + // Set TLS state and BAR0 window if we are working with Gr if (bMIGInUse && RM_ENGINE_TYPE_IS_GR(pKernelChannel->engineType)) { - NV_ASSERT_OK(kmigmgrGetInstanceRefFromClient(pGpu, pKernelMIGManager, pRsClient->hClient, - &pKernelChannel->partitionRef)); + NV_ASSERT_OK(kmigmgrGetInstanceRefFromDevice(pGpu, pKernelMIGManager, + pDevice, &pKernelChannel->partitionRef)); } // Allocate the ChId (except legacy VGPU which allocates ChID on the host) @@ -899,7 +944,6 @@ if (bLockAcquired) rmGpuLocksRelease(GPUS_LOCK_FLAGS_NONE, NULL); - // These fields are only needed internally; clear them here pChannelGpfifoParams->hPhysChannelGroup = 0; pChannelGpfifoParams->internalFlags = 0; @@ -909,6 +953,9 @@ sizeof pChannelGpfifoParams->eccErrorNotifierMem); pChannelGpfifoParams->ProcessID = 0; pChannelGpfifoParams->SubProcessID = 0; + portMemSet(pChannelGpfifoParams->encryptIv, 0, sizeof(pChannelGpfifoParams->encryptIv)); + portMemSet(pChannelGpfifoParams->decryptIv, 0, sizeof(pChannelGpfifoParams->decryptIv)); + portMemSet(pChannelGpfifoParams->hmacNonce, 0, sizeof(pChannelGpfifoParams->hmacNonce)); // Free the allocated resources if there was an error if (status != NV_OK) @@ -1030,8 +1077,11 @@ KernelGraphicsContext *pKernelGraphicsContext; // Perform GR ctx cleanup tasks on channel destruction - if (kgrctxFromKernelChannel(pKernelChannel, &pKernelGraphicsContext) == NV_OK) + if ((kgrctxFromKernelChannel(pKernelChannel, &pKernelGraphicsContext) == NV_OK) && + kgrctxIsValid(pGpu, pKernelGraphicsContext, pKernelChannel)) + { shrkgrctxDetach(pGpu, pKernelGraphicsContext->pShared, pKernelGraphicsContext, pKernelChannel); + } } _kchannelCleanupNotifyActions(pKernelChannel); @@ -1277,13 +1327,12 @@ NV_STATUS CliGetKernelChannelWithDevice ( - NvHandle hClient, + RsClient *pClient, NvHandle hParent, NvHandle hKernelChannel, KernelChannel **ppKernelChannel ) { - RsClient *pRsClient; RsResourceRef *pParentRef; RsResourceRef *pResourceRef; KernelChannel *pKernelChannel; @@ -1293,8 +1342,7 @@ *ppKernelChannel = NULL; - NV_ASSERT_OK_OR_RETURN(serverGetClientUnderLock(&g_resServ, hClient, &pRsClient)); - NV_ASSERT_OK_OR_RETURN(clientGetResourceRef(pRsClient, hKernelChannel, &pResourceRef)); + NV_ASSERT_OK_OR_RETURN(clientGetResourceRef(pClient, hKernelChannel, &pResourceRef)); pKernelChannel = dynamicCast(pResourceRef->pResource, KernelChannel); NV_CHECK_OR_RETURN(LEVEL_INFO, pKernelChannel != NULL, NV_ERR_OBJECT_NOT_FOUND); @@ -1513,12 +1561,12 @@ } /** - * @brief Finds the corresponding KernelChannel given client and channel handle + * @brief Finds the corresponding KernelChannel given client object and channel handle * * Looks in client object store for the channel handle. Scales with total * number of registered objects in the client, not just the number of channels. * - * @param[in] hClient + * @param[in] pClient * @param[in] hKernelChannel a KernelChannel Channel handle * @param[out] ppKernelChannel * @@ -1527,21 +1575,17 @@ NV_STATUS CliGetKernelChannel ( - NvHandle hClient, + RsClient *pClient, NvHandle hKernelChannel, KernelChannel **ppKernelChannel ) { NV_STATUS status; - RsClient *pRsClient; RsResourceRef *pResourceRef; *ppKernelChannel = NULL; - NV_CHECK_OK_OR_RETURN(LEVEL_INFO, - serverGetClientUnderLock(&g_resServ, hClient, &pRsClient)); - - status = clientGetResourceRef(pRsClient, hKernelChannel, &pResourceRef); + status = clientGetResourceRef(pClient, hKernelChannel, &pResourceRef); if (status != NV_OK) { return status; @@ -1763,7 +1807,7 @@ NvBool bFound; bFound = CliGetDmaMappingInfo( - pRsClient->hClient, + pRsClient, RES_GET_HANDLE(pDevice), RES_GET_HANDLE(pMemory), notifyGpuVA, @@ -1825,6 +1869,27 @@ } /*! + * @brief Check if the client that owns this channel is in user mode. + * + * This replaces using call context for privilege checking, + * and is callable from both CPU and GSP. + * + * @param[in] pGpu + * @param[in] pKernelChannel + * + * @returns NV_TRUE if owned by user mode or NV_FALSE. + */ +NvBool +kchannelCheckIsUserMode_IMPL +( + KernelChannel *pKernelChannel +) +{ + return (pKernelChannel->privilegeLevel == NV_KERNELCHANNEL_ALLOC_INTERNALFLAGS_PRIVILEGE_USER) || + (pKernelChannel->privilegeLevel == NV_KERNELCHANNEL_ALLOC_INTERNALFLAGS_PRIVILEGE_ADMIN); +} + +/*! * @brief Check if the client that owns this channel is kernel. * * This replaces using call context for privilege checking, @@ -2057,40 +2122,12 @@ NvBool bFullSriov = IS_VIRTUAL_WITH_SRIOV(pGpu) && !gpuIsWarBug200577889SriovHeavyEnabled(pGpu); - if (pUserdSubDeviceMemDesc && - (memdescGetAddressSpace(pUserdSubDeviceMemDesc) == ADDR_SYSMEM)) + // Clear Userd if it is in FB for SRIOV environment without BUG 200577889 or if in SYSMEM + if (pUserdSubDeviceMemDesc != NULL && + ((memdescGetAddressSpace(pUserdSubDeviceMemDesc) == ADDR_SYSMEM) + || ((memdescGetAddressSpace(pUserdSubDeviceMemDesc) == ADDR_FBMEM) && bFullSriov))) { - NvP64 pUserDMem = NvP64_NULL; - NvP64 pPriv = NvP64_NULL; - - NV_ASSERT_OK_OR_GOTO(status, - memdescMap(pUserdSubDeviceMemDesc, 0, - memdescGetSize(pUserdSubDeviceMemDesc), NV_TRUE, - NV_PROTECT_READ_WRITE, &pUserDMem, &pPriv), - failed); - - kfifoSetupUserD_HAL(pKernelFifo, KERNEL_POINTER_FROM_NvP64(NvU8 *, pUserDMem)); - - memdescUnmap(pUserdSubDeviceMemDesc, - NV_TRUE, - osGetCurrentProcess(), - pUserDMem, - pPriv); - } // Clear Userd if it is in FB for SRIOV environment without BUG 200577889 - else if (pUserdSubDeviceMemDesc && (memdescGetAddressSpace(pUserdSubDeviceMemDesc) == ADDR_FBMEM) - && bFullSriov) - { - NvU8 *pUserDMem; - - pUserDMem = kbusMapRmAperture_HAL(pGpu, - pKernelChannel->pUserdSubDeviceMemDesc[gpumgrGetSubDeviceInstanceFromGpu(pGpu)]); - - NV_ASSERT_OR_ELSE(pUserDMem != NULL, status = NV_ERR_INSUFFICIENT_RESOURCES; goto failed); - - kfifoSetupUserD_HAL(pKernelFifo, pUserDMem); - - kbusUnmapRmAperture_HAL(pGpu, pUserdSubDeviceMemDesc, &pUserDMem, - NV_TRUE); + kfifoSetupUserD_HAL(pGpu, pKernelFifo, pUserdSubDeviceMemDesc); } } return NV_OK; @@ -2272,9 +2309,11 @@ NV_STATUS status = NV_OK; FIFO_INSTANCE_BLOCK *pInstanceBlock = NULL; NvU32 subDevInst; + Subdevice *pSubDevice; NvHandle hSubDevice = 0; NvU32 apert = ADDR_UNKNOWN; NV2080_CTRL_CMD_FIFO_GET_CHANNEL_MEM_INFO_PARAMS memInfoParams; + Device *pDevice = GPU_RES_GET_DEVICE(pKernelChannel); NV_ASSERT_OR_RETURN(IS_VIRTUAL_WITH_SRIOV(pGpu) && gpuIsWarBug200577889SriovHeavyEnabled(pGpu), NV_ERR_INVALID_STATE); @@ -2296,15 +2335,21 @@ portMemSet(&memInfoParams, 0, sizeof(NV2080_CTRL_CMD_FIFO_GET_CHANNEL_MEM_INFO_PARAMS)); memInfoParams.hChannel = RES_GET_HANDLE(pKernelChannel); - - if ((status = CliGetSubDeviceHandleFromGpu(RES_GET_CLIENT_HANDLE(pKernelChannel), - pGpu, &hSubDevice)) != NV_OK) + status = subdeviceGetByInstance(RES_GET_CLIENT(pKernelChannel), + RES_GET_HANDLE(pDevice), + subDevInst, + &pSubDevice); + if (status != NV_OK) { - NV_PRINTF(LEVEL_ERROR, "Unable to get subdevice handle.\n"); + NV_PRINTF(LEVEL_ERROR, "Unable to get subdevice object.\n"); DBG_BREAKPOINT(); SLI_LOOP_RETURN(status); } + GPU_RES_SET_THREAD_BC_STATE(pSubDevice); + + hSubDevice = RES_GET_HANDLE(pSubDevice); + NV_RM_RPC_CONTROL(pGpu, RES_GET_CLIENT_HANDLE(pKernelChannel), hSubDevice, @@ -2412,6 +2457,24 @@ (const void*)pChannelGpfifoParams->userdOffset, sizeof(NvU64) * NV2080_MAX_SUBDEVICES); + if (pKernelChannel->bCCSecureChannel) + { + portMemCopy((void*)pRpcParams->encryptIv, + sizeof(pRpcParams->encryptIv), + (const void*)pChannelGpfifoParams->encryptIv, + sizeof(pChannelGpfifoParams->encryptIv)); + + portMemCopy((void*)pRpcParams->decryptIv, + sizeof(pRpcParams->decryptIv), + (const void*)pChannelGpfifoParams->decryptIv, + sizeof(pChannelGpfifoParams->decryptIv)); + + portMemCopy((void*)pRpcParams->hmacNonce, + sizeof(pRpcParams->hmacNonce), + (const void*)pChannelGpfifoParams->hmacNonce, + sizeof(pChannelGpfifoParams->hmacNonce)); + } + // // These fields are only filled out for GSP client or full SRIOV // i.e. the guest independently allocs ChID and instmem @@ -2721,8 +2784,8 @@ RM_ENGINE_TYPE localRmEngineType; NV_ASSERT_OK_OR_RETURN( - kmigmgrGetInstanceRefFromClient(pGpu, pKernelMIGManager, - RES_GET_CLIENT_HANDLE(pKernelChannel), + kmigmgrGetInstanceRefFromDevice(pGpu, pKernelMIGManager, + GPU_RES_GET_DEVICE(pKernelChannel), &ref)); NV_ASSERT_OK_OR_RETURN( @@ -2884,19 +2947,9 @@ ) { OBJGPU *pGpu = GPU_RES_GET_GPU(pKernelChannel); - Device *pDevice; - RsClient *pClient = RES_GET_CLIENT(pKernelChannel); RC_NOTIFIER_SCOPE scope; NV_STATUS rmStatus = NV_OK; - rmStatus = deviceGetByGpu(pClient, pGpu, NV_TRUE, &pDevice); - if (rmStatus != NV_OK) - { - NV_PRINTF(LEVEL_ERROR, "Cannot find device for client 0x%x\n", - pClient->hClient); - return NV_ERR_INVALID_DEVICE; - } - NV_PRINTF(LEVEL_INFO, "calling setErrorNotifier on channel: 0x%x, broadcast to TSG: %s\n", kchannelGetDebugTag(pKernelChannel), @@ -2924,7 +2977,6 @@ RM_ENGINE_TYPE globalRmEngineType; RM_ENGINE_TYPE localRmEngineType; OBJGPU *pGpu = GPU_RES_GET_GPU(pKernelChannel); - NvHandle hClient = RES_GET_CLIENT_HANDLE(pKernelChannel); NvBool bMIGInUse = IS_MIG_IN_USE(pGpu); NV_STATUS rmStatus = NV_OK; ENGDESCRIPTOR engineDesc; @@ -2953,7 +3005,9 @@ MIG_INSTANCE_REF ref; NV_CHECK_OK_OR_RETURN(LEVEL_ERROR, - kmigmgrGetInstanceRefFromClient(pGpu, pKernelMIGManager, hClient, &ref)); + kmigmgrGetInstanceRefFromDevice(pGpu, pKernelMIGManager, + GPU_RES_GET_DEVICE(pKernelChannel), + &ref)); NV_CHECK_OK_OR_RETURN(LEVEL_ERROR, kmigmgrGetLocalToGlobalEngineType(pGpu, pKernelMIGManager, ref, localRmEngineType, @@ -3160,13 +3214,11 @@ if (pObject->resourceDesc.engDesc == ENG_SW) { RS_ORDERED_ITERATOR it; - RsClient *pClient; + RsClient *pClient = RES_GET_CLIENT(pKernelChannel); ChannelDescendant *pMatchingObject = NULL; firstObjectClassID = pKernelChannel->nextObjectClassID; - NV_ASSERT_OK_OR_RETURN(serverGetClientUnderLock(&g_resServ, RES_GET_CLIENT_HANDLE(pKernelChannel), &pClient)); - do { if (++pKernelChannel->nextObjectClassID == firstObjectClassID) @@ -3479,25 +3531,6 @@ } // - // If the VAList is not managed by RM, remove all VAs here. - // If the VAList is managed by RM, unmap and remove all VAs in kchannelUnmapEngineCtxBuf() - // - if (!vaListGetManaged(&pEngCtxDesc->vaList)) - { - status = _kchannelClearVAList(pGpu, &pEngCtxDesc->vaList, NV_FALSE); - NV_ASSERT_OR_ELSE(status == NV_OK, SLI_LOOP_GOTO(fail)); - } - - // - // Free all subcontext headers in TSG. This usually happens while last channel in TSG is being freed. - // we make sure all GR objects have already been freed before this point(see kgrctxUnmapAssociatedCtxBuffers). - // Other cases where this is exercised are special cases like golden image init where ctx buffers are swapped, - // control calls which force ctx buffer unmap, re-initializing of virtual ctxs, evicting a ctx, fifoStateDestroy etc. - // - if(IS_GR(engDesc)) - { - status = kchangrpFreeGrSubcontextHdrs_HAL(pGpu, pKernelChannelGroup); - } } else { @@ -3580,15 +3613,8 @@ SLI_LOOP_CONTINUE; } - // Only unmaps if RM manages this VAList - if (!vaListGetManaged(&pEngCtxDesc->vaList)) - { - SLI_LOOP_CONTINUE; - } - - // Clear VA list, including unmap - NV_ASSERT(memdescGetAddressSpace(memdescGetMemDescFromGpu(pEngCtxDesc->pMemDesc, pGpu)) != ADDR_VIRTUAL); - status = _kchannelClearVAList(pGpu, &pEngCtxDesc->vaList, NV_TRUE); + // Clear VA list, including unmap if managed + status = _kchannelClearVAList(pGpu, &pEngCtxDesc->vaList, vaListGetManaged(&pEngCtxDesc->vaList)); NV_ASSERT_OR_ELSE(status == NV_OK, SLI_LOOP_GOTO(fail)); SLI_LOOP_END @@ -3747,12 +3773,11 @@ { NvHandle hNotifier; RsClient *pClient = RES_GET_CLIENT(pKernelChannel); - Device *pDevice; Memory *pMemory; ContextDma *pContextDma; NvU32 addressSpace; NvU64 notificationBufferSize; - NV_STATUS status; + Device *pDevice; hNotifier = pKernelChannel->hErrorContext; @@ -3767,9 +3792,7 @@ return NV_ERR_OUT_OF_RANGE; } - status = deviceGetByInstance(pClient, gpuGetDeviceInstance(pGpu), &pDevice); - if (status != NV_OK) - return NV_ERR_INVALID_DEVICE; + pDevice = GPU_RES_GET_DEVICE(pKernelChannel); if (NV_OK == memGetByHandleAndDevice(pClient, hNotifier, RES_GET_HANDLE(pDevice), &pMemory)) { @@ -3785,7 +3808,7 @@ PCLI_DMA_MAPPING_INFO pDmaMappingInfo; NV_CHECK_OR_RETURN(LEVEL_INFO, - CliGetDmaMappingInfo(pClient->hClient, + CliGetDmaMappingInfo(pClient, RES_GET_HANDLE(pDevice), RES_GET_HANDLE(pMemory), physAddr, @@ -3842,87 +3865,75 @@ NvU32 token ) { - NV_STATUS status = NV_OK; - NvHandle hNotifier; - RsClient *pClient = RES_GET_CLIENT(pKernelChannel); - Device *pDevice; - Memory *pMemory; - ContextDma *pContextDma; - NvU32 addressSpace; + MEMORY_DESCRIPTOR *pNotifierMemDesc = pKernelChannel->pErrContextMemDesc; + NV_ADDRESS_SPACE addressSpace; NvU16 notifyStatus = 0x0; NvU32 index; + OBJTMR *pTmr = GPU_GET_TIMER(pGpu); + NvU64 time; + MemoryManager *pMemoryManager = GPU_GET_MEMORY_MANAGER(pGpu); + KernelBus *pKernelBus = GPU_GET_KERNEL_BUS(pGpu); + TRANSFER_SURFACE surf = {0}; + NvNotification *pNotifier = NULL; + NvBool bMemEndTransfer = NV_FALSE; - hNotifier = pKernelChannel->hErrorContext; - index = pKernelChannel->notifyIndex[NV_CHANNELGPFIFO_NOTIFICATION_TYPE_WORK_SUBMIT_TOKEN]; + if (pNotifierMemDesc == NULL) + return NV_OK; - status = deviceGetByInstance(pClient, gpuGetDeviceInstance(pGpu), &pDevice); - if (status != NV_OK) - return NV_ERR_INVALID_DEVICE; + index = pKernelChannel->notifyIndex[NV_CHANNELGPFIFO_NOTIFICATION_TYPE_WORK_SUBMIT_TOKEN]; notifyStatus = FLD_SET_DRF(_CHANNELGPFIFO, _NOTIFICATION_STATUS, _IN_PROGRESS, _TRUE, notifyStatus); notifyStatus = FLD_SET_DRF_NUM(_CHANNELGPFIFO, _NOTIFICATION_STATUS, _VALUE, 0xFFFF, notifyStatus); - if (NV_OK == memGetByHandleAndDevice(pClient, hNotifier, RES_GET_HANDLE(pDevice), &pMemory)) - { - addressSpace = memdescGetAddressSpace(pMemory->pMemDesc); - - // - // If clients did not allocate enough memory for the doorbell - // notifier, return NV_OK so as not to regress older clients - // - NV_CHECK_OR_RETURN(LEVEL_INFO, pMemory->Length >= ((index + 1) * sizeof(NvNotification)), NV_OK); - switch (addressSpace) - { - case ADDR_VIRTUAL: - { - NvU64 physAddr = memdescGetPhysAddr(pMemory->pMemDesc, AT_GPU_VA, 0); - PCLI_DMA_MAPPING_INFO pDmaMappingInfo; + addressSpace = memdescGetAddressSpace(pNotifierMemDesc); + if (RMCFG_FEATURE_PLATFORM_GSP) + NV_ASSERT_OR_RETURN(addressSpace == ADDR_FBMEM, NV_ERR_INVALID_STATE); - NV_CHECK_OR_RETURN(LEVEL_INFO, - CliGetDmaMappingInfo(pClient->hClient, - RES_GET_HANDLE(pDevice), - RES_GET_HANDLE(pMemory), - physAddr, - gpumgrGetDeviceGpuMask(pGpu->deviceInstance), - &pDmaMappingInfo), - NV_OK); + // + // If clients did not allocate enough memory for the doorbell + // notifier, return NV_OK so as not to regress older clients + // + NV_CHECK_OR_RETURN(LEVEL_INFO, memdescGetSize(pNotifierMemDesc) >= (index + 1) * sizeof(NvNotification), NV_OK); - // - // If clients did not map enough memory for the doorbell - // notifier, return NV_OK so as not to regress older clients - // - NV_CHECK_OR_RETURN(LEVEL_INFO, pDmaMappingInfo->pMemDesc->Size >= ((index + 1) * sizeof(NvNotification)), NV_OK); + pNotifier = (NvNotification *)memdescGetKernelMapping(pNotifierMemDesc); + if (pNotifier == NULL) + { + surf.pMemDesc = pNotifierMemDesc; + surf.offset = index * sizeof(NvNotification); - status = notifyFillNotifierGPUVA(pGpu, pClient->hClient, RES_GET_HANDLE(pMemory), physAddr, - token, 0x0U, notifyStatus, index); - break; - } - case ADDR_FBMEM: - // fall through - case ADDR_SYSMEM: - status = notifyFillNotifierMemory(pGpu, pMemory, token, 0x0U, notifyStatus, index); - break; - default: - status = NV_ERR_NOT_SUPPORTED; - break; - } + pNotifier = + (NvNotification *) memmgrMemBeginTransfer(pMemoryManager, &surf, + sizeof(NvNotification), + TRANSFER_FLAGS_SHADOW_ALLOC); + NV_ASSERT_OR_RETURN(pNotifier != NULL, NV_ERR_INVALID_STATE); + bMemEndTransfer = NV_TRUE; } - else if (NV_OK == ctxdmaGetByHandle(pClient, hNotifier, &pContextDma)) + else { // - // If clients did not allocate enough memory for the doorbell - // notifier, return NV_OK so as not to regress older clients + // If a CPU pointer has been passed by caller ensure that the notifier + // is in sysmem or in case it in vidmem, BAR access to the same is not + // blocked (for HCC) // - NV_CHECK_OR_RETURN(LEVEL_INFO, pContextDma->Limit >= (((index + 1) * sizeof(NvNotification)) - 1), NV_OK); + NV_ASSERT_OR_RETURN( + memdescGetAddressSpace(pNotifierMemDesc) == ADDR_SYSMEM || + !kbusIsBarAccessBlocked(pKernelBus), NV_ERR_INVALID_ARGUMENT); + pNotifier = &pNotifier[index]; + } + + tmrGetCurrentTime(pTmr, &time); - status = notifyFillNotifierOffset(pGpu, pContextDma, token, 0x0U, notifyStatus, - (sizeof(NvNotification) * index)); + notifyFillNvNotification(pGpu, pNotifier, token, 0, + notifyStatus, NV_TRUE, time); + if (bMemEndTransfer) + { + memmgrMemEndTransfer(pMemoryManager, &surf, sizeof(NvNotification), 0); } - return status; + return NV_OK; } /** @@ -4247,14 +4258,14 @@ * @brief Retrieve a KernelChannel from either a KernelChannel or TSG handle. KernelChannel is * checked first. If TSG is provided, the head of the TSG is returned. * - * @param[in] hClient Client + * @param[in] pClient Client object * @param[in] hDual NvHandle either to TSG or to KernelChannel * @param[out] ppKernelChannel Referenced KernelChannel */ NV_STATUS kchannelGetFromDualHandle_IMPL ( - NvHandle hClient, + RsClient *pClient, NvHandle hDual, KernelChannel **ppKernelChannel ) @@ -4266,13 +4277,13 @@ *ppKernelChannel = NULL; - if (CliGetKernelChannel(hClient, hDual, &pKernelChannel) == NV_OK) + if (CliGetKernelChannel(pClient, hDual, &pKernelChannel) == NV_OK) { *ppKernelChannel = pKernelChannel; return NV_OK; } - if (CliGetChannelGroup(hClient, hDual, &pChanGrpRef, NULL) == NV_OK) + if (CliGetChannelGroup(pClient->hClient, hDual, &pChanGrpRef, NULL) == NV_OK) { KernelChannelGroupApi *pKernelChannelGroupApi = dynamicCast( pChanGrpRef->pResource, @@ -4301,20 +4312,20 @@ * checked first. If TSG is provided, the head of the TSG is returned. If * KernelChannel handle is provided, it must not be part of a client-allocated TSG. * - * @param[in] hClient Client + * @param[in] pClient Client object * @param[in] hDual NvHandle either to TSG or to bare Channel * @param[out] ppKernelChannel Referenced KernelChannel */ NV_STATUS kchannelGetFromDualHandleRestricted_IMPL ( - NvHandle hClient, + RsClient *pClient, NvHandle hDual, KernelChannel **ppKernelChannel ) { NV_CHECK_OK_OR_RETURN(LEVEL_ERROR, - kchannelGetFromDualHandle(hClient, hDual, ppKernelChannel)); + kchannelGetFromDualHandle(pClient, hDual, ppKernelChannel)); if ((RES_GET_HANDLE(*ppKernelChannel) == hDual) && (((*ppKernelChannel)->pKernelChannelGroupApi->pKernelChannelGroup != NULL) && !(*ppKernelChannel)->pKernelChannelGroupApi->pKernelChannelGroup->bAllocatedByRm)) @@ -4349,3 +4360,154 @@ pMapping->flags = flags; pMapping->pContext = (void*)(NvUPtr)pKernelChannel->ChID; } + +NV_STATUS kchannelRetrieveKmb_KERNEL +( + OBJGPU *pGpu, + KernelChannel *pKernelChannel, + ROTATE_IV_TYPE rotateOperation, + NvBool includeSecrets, + CC_KMB *keyMaterialBundle +) +{ + ConfidentialCompute *pCC = GPU_GET_CONF_COMPUTE(pGpu); + + NV_ASSERT(pCC != NULL); + + return (confComputeKeyStoreRetrieveViaChannel_HAL(pCC, pKernelChannel, rotateOperation, + includeSecrets, keyMaterialBundle)); +} + +/*! + * @brief Get KMB for secure channel + * + * @param[in] pKernelChannnel + * @param[out] pGetKmbParams + */ +NV_STATUS +kchannelCtrlCmdGetKmb_KERNEL +( + KernelChannel *pKernelChannel, + NVC56F_CTRL_CMD_GET_KMB_PARAMS *pGetKmbParams +) +{ + if (!pKernelChannel->bCCSecureChannel) + { + return NV_ERR_NOT_SUPPORTED; + } + + portMemCopy((void*)(&pGetKmbParams->kmb), sizeof(CC_KMB), + (const void*)(&pKernelChannel->clientKmb), sizeof(CC_KMB)); + + return NV_OK; + return NV_ERR_NOT_SUPPORTED; +} + +/*! + * @brief Rotate the IVs for the given secure channel + * + * @param[in] pKernelChannel + * @param[out] pRotateIvParams + * + * @return NV_OK on success + * @return NV_ERR_NOT_SUPPORTED if channel is not a secure channel. + */ +NV_STATUS +kchannelCtrlRotateSecureChannelIv_KERNEL +( + KernelChannel *pKernelChannel, + NVC56F_CTRL_ROTATE_SECURE_CHANNEL_IV_PARAMS *pRotateIvParams +) +{ + NV_STATUS status = NV_OK; + OBJGPU *pGpu = GPU_RES_GET_GPU(pKernelChannel); + ConfidentialCompute *pCC = GPU_GET_CONF_COMPUTE(pGpu); + ROTATE_IV_TYPE rotateIvOperation = pRotateIvParams->rotateIvType; + + if (!pKernelChannel->bCCSecureChannel) + { + return NV_ERR_NOT_SUPPORTED; + } + + NV_PRINTF(LEVEL_INFO, "Rotating IV in CPU-RM.\n"); + + status = confComputeKeyStoreRetrieveViaChannel_HAL( + pCC, pKernelChannel, rotateIvOperation, NV_TRUE, &pKernelChannel->clientKmb); + + if (status != NV_OK) + { + return status; + } + + portMemSet(pRotateIvParams, 0, sizeof(*pRotateIvParams)); + + portMemCopy(pRotateIvParams->updatedKmb.encryptBundle.iv, + sizeof(pRotateIvParams->updatedKmb.encryptBundle.iv), + pKernelChannel->clientKmb.encryptBundle.iv, + sizeof(pKernelChannel->clientKmb.encryptBundle.iv)); + + portMemCopy(pRotateIvParams->updatedKmb.decryptBundle.iv, + sizeof(pRotateIvParams->updatedKmb.decryptBundle.iv), + pKernelChannel->clientKmb.decryptBundle.iv, + sizeof(pKernelChannel->clientKmb.decryptBundle.iv)); + + pRotateIvParams->rotateIvType = rotateIvOperation; + + NV_RM_RPC_CONTROL(pGpu, + RES_GET_CLIENT_HANDLE(pKernelChannel), + RES_GET_HANDLE(pKernelChannel), + NVC56F_CTRL_ROTATE_SECURE_CHANNEL_IV, + pRotateIvParams, + sizeof(*pRotateIvParams), + status); + + if (status != NV_OK) + { + return status; + } + + if ((rotateIvOperation == ROTATE_IV_ALL_VALID) || (rotateIvOperation == ROTATE_IV_ENCRYPT)) + { + portMemCopy(&pRotateIvParams->updatedKmb.encryptBundle, + sizeof(pRotateIvParams->updatedKmb.encryptBundle), + &pKernelChannel->clientKmb.encryptBundle, + sizeof(pKernelChannel->clientKmb.encryptBundle)); + } + + if ((rotateIvOperation == ROTATE_IV_ALL_VALID) || (rotateIvOperation == ROTATE_IV_DECRYPT)) + { + portMemCopy(&pRotateIvParams->updatedKmb.decryptBundle, + sizeof(pRotateIvParams->updatedKmb.decryptBundle), + &pKernelChannel->clientKmb.decryptBundle, + sizeof(pKernelChannel->clientKmb.decryptBundle)); + } + + return NV_OK; + return NV_ERR_NOT_SUPPORTED; +} + +NV_STATUS +kchannelCtrlRotateSecureChannelIv_PHYSICAL +( + KernelChannel *pKernelChannel, + NVC56F_CTRL_ROTATE_SECURE_CHANNEL_IV_PARAMS *pRotateIvParams +) +{ + NV_STATUS status; + + NV_PRINTF(LEVEL_INFO, "Rotating IV in GSP-RM.\n"); + + // CPU-side encrypt IV corresponds to GPU-side decrypt IV. + // CPU-side decrypt IV corresponds to GPU-side encrypt IV. + status = + kchannelRotateSecureChannelIv_HAL(pKernelChannel, + pRotateIvParams->rotateIvType, + pRotateIvParams->updatedKmb.decryptBundle.iv, + pRotateIvParams->updatedKmb.encryptBundle.iv); + if (status != NV_OK) + { + return status; + } + + return NV_OK; +} diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/kernel/gpu/fifo/kernel_channel_group.c nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/kernel/gpu/fifo/kernel_channel_group.c --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/kernel/gpu/fifo/kernel_channel_group.c 2023-10-25 20:21:00.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/kernel/gpu/fifo/kernel_channel_group.c 2024-03-05 22:13:25.000000000 +0000 @@ -147,7 +147,9 @@ } // Determine initial runlist for this TSG, using engine type if provided - pKernelChannelGroup->runlistId = kchangrpGetDefaultRunlist_HAL(pGpu, pKernelChannelGroup); + pKernelChannelGroup->runlistId = kfifoGetDefaultRunlist_HAL(pGpu, + pKernelFifo, + pKernelChannelGroup->engineType); if (kfifoIsPerRunlistChramEnabled(pKernelFifo)) { @@ -417,18 +419,21 @@ kfifoChannelListDestroy(pGpu, pKernelFifo, pKernelChannelGroup->pChanList); pKernelChannelGroup->pChanList= NULL; - // Remove this from the that we maintain in OBJFIFO - pKernelChannelGroupTemp = mapFind(pChidMgr->pChanGrpTree, pKernelChannelGroup->grpID); - if (pKernelChannelGroupTemp == NULL) - { - NV_PRINTF(LEVEL_ERROR, "Could not find channel group %d\n", - pKernelChannelGroup->grpID); - return NV_ERR_OBJECT_NOT_FOUND; - } - mapRemove(pChidMgr->pChanGrpTree, pKernelChannelGroupTemp); + if (pChidMgr != NULL) + { + // Remove this from the that we maintain in OBJFIFO + pKernelChannelGroupTemp = mapFind(pChidMgr->pChanGrpTree, pKernelChannelGroup->grpID); + if (pKernelChannelGroupTemp == NULL) + { + NV_PRINTF(LEVEL_ERROR, "Could not find channel group %d\n", + pKernelChannelGroup->grpID); + return NV_ERR_OBJECT_NOT_FOUND; + } + mapRemove(pChidMgr->pChanGrpTree, pKernelChannelGroupTemp); - // Release the free grpID - kfifoChidMgrFreeChannelGroupHwID(pGpu, pKernelFifo, pChidMgr, pKernelChannelGroup->grpID); + // Release the free grpID + kfifoChidMgrFreeChannelGroupHwID(pGpu, pKernelFifo, pChidMgr, pKernelChannelGroup->grpID); + } // // Free the method buffer if applicable diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/kernel/gpu/fifo/kernel_channel_group_api.c nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/kernel/gpu/fifo/kernel_channel_group_api.c --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/kernel/gpu/fifo/kernel_channel_group_api.c 2023-10-25 20:21:00.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/kernel/gpu/fifo/kernel_channel_group_api.c 2024-03-05 22:13:25.000000000 +0000 @@ -28,6 +28,9 @@ #include "kernel/gpu/mem_mgr/mem_mgr.h" #include "kernel/gpu/gr/kernel_graphics.h" #include "kernel/gpu/falcon/kernel_falcon.h" +#include "kernel/gpu/rc/kernel_rc.h" + +#include "kernel/gpu/conf_compute/conf_compute.h" #include "class/cl0090.h" // KERNEL_GRAPHICS_CONTEXT #include "class/cl9067.h" // FERMI_CONTEXT_SHARE_A @@ -47,29 +50,30 @@ RS_RES_ALLOC_PARAMS_INTERNAL *pParams ) { - NvBool bTsgAllocated = NV_FALSE; - RsResourceRef *pResourceRef = pCallContext->pResourceRef; - NV_STATUS rmStatus; - OBJVASPACE *pVAS = NULL; - OBJGPU *pGpu = GPU_RES_GET_GPU(pKernelChannelGroupApi); - KernelMIGManager *pKernelMIGManager = NULL; - KernelFifo *pKernelFifo = GPU_GET_KERNEL_FIFO(pGpu); - NvHandle hVASpace = NV01_NULL_OBJECT; - Device *pDevice = NULL; - NvU32 gfid = GPU_GFID_PF; - RsShared *pShared = NULL; - RsClient *pClient; - NvBool bLockAcquired = NV_FALSE; - Heap *pHeap = GPU_GET_HEAP(pGpu); - NvBool bMIGInUse = NV_FALSE; - CTX_BUF_INFO *bufInfoList = NULL; - NvU32 bufCount = 0; - NvBool bReserveMem = NV_FALSE; - MIG_INSTANCE_REF ref; - RM_API *pRmApi = rmapiGetInterface(RMAPI_GPU_LOCK_INTERNAL); - KernelChannelGroup *pKernelChannelGroup = NULL; - NV_CHANNEL_GROUP_ALLOCATION_PARAMETERS *pAllocParams = NULL; - RM_ENGINE_TYPE rmEngineType; + NvBool bTsgAllocated = NV_FALSE; + RsResourceRef *pResourceRef = pCallContext->pResourceRef; + NV_STATUS rmStatus; + OBJVASPACE *pVAS = NULL; + OBJGPU *pGpu = GPU_RES_GET_GPU(pKernelChannelGroupApi); + KernelMIGManager *pKernelMIGManager = NULL; + KernelFifo *pKernelFifo = GPU_GET_KERNEL_FIFO(pGpu); + NvHandle hVASpace = NV01_NULL_OBJECT; + Device *pDevice = NULL; + NvU32 gfid = GPU_GFID_PF; + RsShared *pShared = NULL; + RsClient *pClient; + NvBool bLockAcquired = NV_FALSE; + Heap *pHeap = GPU_GET_HEAP(pGpu); + NvBool bMIGInUse = NV_FALSE; + CTX_BUF_INFO *bufInfoList = NULL; + NvU32 bufCount = 0; + NvBool bReserveMem = NV_FALSE; + MIG_INSTANCE_REF ref; + RM_API *pRmApi = rmapiGetInterface(RMAPI_GPU_LOCK_INTERNAL); + KernelChannelGroup *pKernelChannelGroup = NULL; + NV_CHANNEL_GROUP_ALLOCATION_PARAMETERS *pAllocParams = NULL; + RM_ENGINE_TYPE rmEngineType; + NV_PRINTF(LEVEL_INFO, "hClient: 0x%x, hParent: 0x%x, hObject:0x%x, hClass: 0x%x\n", @@ -167,8 +171,7 @@ // to determine runlistId from engineId passed by client. This // runlistId is used to associate all future channels in this TSG to // that runlist. Setting the engineType will cause the runlist - // corresponding to that engine to be chosen in - // kchangrpGetDefaultRunlist_HAL. + // corresponding to that engine to be chosen. // pKernelChannelGroup->engineType = rmEngineType; } @@ -187,7 +190,8 @@ NV_CHECK_OK_OR_GOTO( rmStatus, LEVEL_ERROR, - kmigmgrGetInstanceRefFromClient(pGpu, pKernelMIGManager, pParams->hClient, &ref), + kmigmgrGetInstanceRefFromDevice(pGpu, pKernelMIGManager, + pDevice, &ref), failed); NV_CHECK_OK_OR_GOTO( @@ -202,6 +206,15 @@ pKernelChannelGroup->engineType = rmEngineType; pHeap = ref.pKernelMIGGpuInstance->pMemoryPartitionHeap; } + else + { + // Only GR0 is allowed without MIG + if ((RM_ENGINE_TYPE_IS_GR(rmEngineType)) && (rmEngineType != RM_ENGINE_TYPE_GR0)) + { + rmStatus = NV_ERR_INVALID_ARGUMENT; + goto failed; + } + } if((pDevice->vaMode != NV_DEVICE_ALLOCATION_VAMODE_MULTIPLE_VASPACES) || (hVASpace != 0)) { @@ -230,13 +243,28 @@ if (!RMCFG_FEATURE_PLATFORM_GSP) { - NV_ASSERT_OK_OR_GOTO(rmStatus, - ctxBufPoolInit(pGpu, pHeap, &pKernelChannelGroup->pCtxBufPool), - failed); + NvHandle hRcWatchdog; - NV_ASSERT_OK_OR_GOTO(rmStatus, - ctxBufPoolInit(pGpu, pHeap, &pKernelChannelGroup->pChannelBufPool), - failed); + // + // WAR for 4217716 - Force allocations made on behalf of watchdog client to + // RM reserved heap. This avoids a constant memory allocation from appearing + // due to the ctxBufPool reservation out of PMA. + // + rmStatus = krcWatchdogGetClientHandle(GPU_GET_KERNEL_RC(pGpu), &hRcWatchdog); + if ((rmStatus != NV_OK) || (pParams->hClient != hRcWatchdog)) + { + NV_ASSERT_OK_OR_GOTO(rmStatus, + ctxBufPoolInit(pGpu, pHeap, &pKernelChannelGroup->pCtxBufPool), + failed); + + NV_ASSERT_OK_OR_GOTO(rmStatus, + ctxBufPoolInit(pGpu, pHeap, &pKernelChannelGroup->pChannelBufPool), + failed); + } + else + { + NV_PRINTF(LEVEL_INFO, "Skipping ctxBufPoolInit for RC watchdog\n"); + } } NV_ASSERT_OK_OR_GOTO(rmStatus, @@ -266,6 +294,28 @@ NVA06C_CTRL_INTERLEAVE_LEVEL_MEDIUM), failed); + ConfidentialCompute *pConfCompute = GPU_GET_CONF_COMPUTE(pGpu); + MemoryManager *pMemoryManager = GPU_GET_MEMORY_MANAGER(pGpu); + if ((pConfCompute != NULL) && + (pConfCompute->getProperty(pCC, PDB_PROP_CONFCOMPUTE_CC_FEATURE_ENABLED))) + { + // TODO: jira CONFCOMP-1621: replace this with actual flag for TSG alloc that skips scrub + if ((pMemoryManager->bScrubChannelSetupInProgress) && + (pKernelChannelGroup->pChannelBufPool != NULL) && + (pKernelChannelGroup->pCtxBufPool != NULL)) + { + if (pCallContext->secInfo.privLevel < RS_PRIV_LEVEL_KERNEL) + { + rmStatus = NV_ERR_INVALID_ARGUMENT; + NV_PRINTF(LEVEL_ERROR, "Only kernel priv clients can skip scrubber\n"); + goto failed; + } + ctxBufPoolSetScrubSkip(pKernelChannelGroup->pChannelBufPool, NV_TRUE); + ctxBufPoolSetScrubSkip(pKernelChannelGroup->pCtxBufPool, NV_TRUE); + NV_PRINTF(LEVEL_INFO, "Skipping scrubber for all allocations on this context\n"); + } + } + // // If ctx buf pools are enabled, filter out partitionable engines // that aren't part of our instance. @@ -273,20 +323,28 @@ // Memory needs to be reserved in the pool only for buffers for // engines in instance. // + + // + // Size of memory that will be calculated for ctxBufPool reservation if ctxBufPool is enabled and MIG is disabled + // or current engine belongs to this MIG instance and MIG is enabled + // if (pKernelChannelGroup->pCtxBufPool != NULL && - kmigmgrIsEngineInInstance(pGpu, pKernelMIGManager, pKernelChannelGroup->engineType, ref)) + (!bMIGInUse || kmigmgrIsEngineInInstance(pGpu, pKernelMIGManager, pKernelChannelGroup->engineType, ref))) { // GR Buffers if (RM_ENGINE_TYPE_IS_GR(pKernelChannelGroup->engineType)) { KernelGraphics *pKernelGraphics = GPU_GET_KERNEL_GRAPHICS(pGpu, RM_ENGINE_TYPE_GR_IDX(pKernelChannelGroup->engineType)); - NvU32 bufId; + NvU32 bufId = 0; portMemSet(&bufInfoList[0], 0, sizeof(CTX_BUF_INFO) * NV_ENUM_SIZE(GR_CTX_BUFFER)); bufCount = 0; + + kgraphicsDiscoverMaxLocalCtxBufferSize(pGpu, pKernelGraphics); + FOR_EACH_IN_ENUM(GR_CTX_BUFFER, bufId) { // TODO expose engine class capabilities to kernel RM - if (kgrmgrIsCtxBufSupported(bufId, !IS_MIG_ENABLED(pGpu))) + if (kgrmgrIsCtxBufSupported(bufId, NV_FALSE)) { const CTX_BUF_INFO *pBufInfo = kgraphicsGetCtxBufferInfo(pGpu, pKernelGraphics, bufId); bufInfoList[bufCount] = *pBufInfo; @@ -351,6 +409,7 @@ &pKernelChannelGroupApi->hKernelGraphicsContext, KERNEL_GRAPHICS_CONTEXT, NvP64_NULL, + 0, RMAPI_ALLOC_FLAGS_SKIP_RPC, NvP64_NULL, &pRmApi->defaultSecInfo), @@ -369,6 +428,7 @@ pParams->hResource, pParams->externalClassId, pAllocParams, + sizeof(*pAllocParams), rmStatus); // // Make sure that corresponding RPC occurs when freeing @@ -872,6 +932,7 @@ &hkCtxShare, FERMI_CONTEXT_SHARE_A, NV_PTR_TO_NvP64(&kctxshareParams), + sizeof(kctxshareParams), RMAPI_ALLOC_FLAGS_SKIP_RPC, NvP64_NULL, &pRmApi->defaultSecInfo), @@ -896,6 +957,7 @@ &hkCtxShare, FERMI_CONTEXT_SHARE_A, NV_PTR_TO_NvP64(&kctxshareParams), + sizeof(kctxshareParams), RMAPI_ALLOC_FLAGS_SKIP_RPC, NvP64_NULL, &pRmApi->defaultSecInfo), @@ -1073,7 +1135,8 @@ // If no channels have a runlist set, get the default and use it. if (runlistId == INVALID_RUNLIST_ID) { - runlistId = kchangrpGetDefaultRunlist_HAL(pGpu, pKernelChannelGroup); + runlistId = kfifoGetDefaultRunlist_HAL(pGpu, pKernelFifo, + pKernelChannelGroup->engineType); } // We can rewrite TSG runlist id just as we will do that for all TSG channels below @@ -1137,7 +1200,7 @@ { NV_STATUS rmStatus = NV_OK; OBJGPU *pGpu = GPU_RES_GET_GPU(pKernelChannelGroupApi); - NvHandle hClient = RES_GET_CLIENT_HANDLE(pKernelChannelGroupApi); + Device *pDevice = GPU_RES_GET_DEVICE(pKernelChannelGroupApi); CHANNEL_NODE *pChanNode; RM_ENGINE_TYPE localEngineType; RM_ENGINE_TYPE globalEngineType; @@ -1154,7 +1217,7 @@ MIG_INSTANCE_REF ref; NV_CHECK_OK_OR_RETURN(LEVEL_ERROR, - kmigmgrGetInstanceRefFromClient(pGpu, pKernelMIGManager, hClient, &ref)); + kmigmgrGetInstanceRefFromDevice(pGpu, pKernelMIGManager, pDevice, &ref)); NV_CHECK_OK_OR_RETURN(LEVEL_ERROR, kmigmgrGetLocalToGlobalEngineType(pGpu, pKernelMIGManager, ref, diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/kernel/gpu/fifo/kernel_ctxshare.c nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/kernel/gpu/fifo/kernel_ctxshare.c --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/kernel/gpu/fifo/kernel_ctxshare.c 2023-10-25 20:21:00.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/kernel/gpu/fifo/kernel_ctxshare.c 2024-03-05 22:13:25.000000000 +0000 @@ -292,7 +292,7 @@ if (pKernelChannelGroupApi->hKernelGraphicsContext != NV01_NULL_OBJECT) { RsResourceRef *pKernelGraphicsContextRef; - NV_ASSERT_OK_OR_ELSE(rmStatus, + NV_ASSERT_OK_OR_ELSE(rmStatus, clientGetResourceRef(pCallContext->pClient, pKernelChannelGroupApi->hKernelGraphicsContext, &pKernelGraphicsContextRef), goto done); @@ -300,7 +300,7 @@ } // - // For legacy internal kctxshares, RPC is handled by the channelgroup object's copy ctor, + // For legacy internal kctxshares, RPC is handled by the channelgroup object's copy ctor, // so we skip the automatic RPC here // if ((IS_VIRTUAL(pGpu) || IS_GSP_CLIENT(pGpu)) && !pKernelCtxShareApi->pShareData->pKernelChannelGroup->bLegacyMode) @@ -311,7 +311,7 @@ pDstRef, rmStatus); } -done: +done: if (rmStatus != NV_OK) { serverFreeShare(&g_resServ, pShared); @@ -505,13 +505,11 @@ ) { NV_STATUS status = NV_OK; - NvU32 subctxId, i; + NvU32 subctxId; + NvU32 i; KernelChannelGroup *pKernelChannelGroup; - NvU32 subDevInst; - ENGINE_CTX_DESCRIPTOR *pEngCtxDesc = NULL; NvU64 numMax = 0; NvBool bRelease = NV_TRUE; - NvU64 vaddr = 0; RsShared *pShared = NULL; NvS32 refcnt = 0; @@ -560,54 +558,6 @@ } } - SLI_LOOP_START(SLI_LOOP_FLAGS_BC_ONLY | SLI_LOOP_FLAGS_IGNORE_REENTRANCY) - RsResourceRef *pParentRef = RES_GET_REF(pKernelCtxShareApi)->pParentRef; - KernelChannelGroupApi *pKernelChannelGroupApi = dynamicCast(pParentRef->pResource, KernelChannelGroupApi); - KernelGraphicsContext *pKernelGraphicsContext; - - subDevInst = gpumgrGetSubDeviceInstanceFromGpu(pGpu); - if ((pKernelChannelGroup->ppEngCtxDesc != NULL) && - kgrctxFromKernelChannelGroupApi(pKernelChannelGroupApi, &pKernelGraphicsContext) == NV_OK) - { - if (bRelease) - { - KernelGraphicsManager *pKernelGraphicsManager = GPU_GET_KERNEL_GRAPHICS_MANAGER(pGpu); - NvHandle hClient = RES_GET_CLIENT_HANDLE(pKernelGraphicsContext); - NvHandle hParent = RES_GET_PARENT_HANDLE(pKernelGraphicsContext); - NV2080_CTRL_GR_ROUTE_INFO grRouteInfo; - KernelGraphics *pKernelGraphics; - - portMemSet(&grRouteInfo, 0, sizeof(grRouteInfo)); - kgrmgrCtrlSetChannelHandle(hParent, &grRouteInfo); - - kgrmgrCtrlRouteKGR(pGpu, pKernelGraphicsManager, hClient, &grRouteInfo, &pKernelGraphics); - - pEngCtxDesc = pKernelChannelGroup->ppEngCtxDesc[subDevInst]; - if (pEngCtxDesc != NULL) - { - vaddr = 0; - if (vaListFindVa(&pEngCtxDesc->vaList, pKernelCtxShare->pVAS, &vaddr) == NV_OK) - { - NvU64 tmpVaddr = 0; - while (vaListFindVa(&pEngCtxDesc->vaList, pKernelCtxShare->pVAS, &tmpVaddr) == NV_OK) - { - status = vaListRemoveVa(&pEngCtxDesc->vaList, pKernelCtxShare->pVAS); - NV_ASSERT(status == NV_OK); - } - - if (vaListGetManaged(&pEngCtxDesc->vaList)) - { - dmaUnmapBuffer_HAL(pGpu, GPU_GET_DMA(pGpu), pKernelCtxShare->pVAS, vaddr); - } - } - } - } - } - SLI_LOOP_END - - - subDevInst = gpumgrGetSubDeviceInstanceFromGpu(pGpu); - status = kctxshareDestroy_HAL(pKernelCtxShare, pKernelCtxShareApi, pGpu, pKernelChannelGroupApi, bRelease); if (status != NV_OK) { diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/kernel/gpu/fifo/kernel_fifo.c nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/kernel/gpu/fifo/kernel_fifo.c --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/kernel/gpu/fifo/kernel_fifo.c 2023-10-25 20:21:01.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/kernel/gpu/fifo/kernel_fifo.c 2024-03-05 22:13:25.000000000 +0000 @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 2021-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2021-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -21,6 +21,9 @@ * DEALINGS IN THE SOFTWARE. */ +// FIXME XXX +#define NVOC_KERNEL_GRAPHICS_MANAGER_H_PRIVATE_ACCESS_ALLOWED + #include "kernel/gpu/fifo/kernel_fifo.h" #include "kernel/gpu/fifo/kernel_channel.h" #include "kernel/gpu/fifo/kernel_channel_group.h" @@ -64,6 +67,20 @@ static NV_STATUS _kfifoChidMgrFreeIsolationId(CHID_MGR *pChidMgr, NvU32 ChID); + +NvU32 kfifoGetNumEschedDrivenEngines_IMPL +( + KernelFifo *pKernelFifo +) +{ + const ENGINE_INFO *pEngineInfo; + NV_ASSERT(kfifoGetNumEngines_HAL(ENG_GET_GPU(pKernelFifo), pKernelFifo) > + 0); + pEngineInfo = kfifoGetEngineInfo(pKernelFifo); + return pEngineInfo->numRunlists; +} + + NV_STATUS kfifoChidMgrConstruct_IMPL ( @@ -586,7 +603,8 @@ chSize = 1; // Create unique isolation ID for each process - if (serverutilGetClientUnderLock(hClient, &pClient) != NV_OK) + pClient = serverutilGetClientUnderLock(hClient); + if (pClient == NULL) { NV_PRINTF(LEVEL_ERROR, "Invalid client handle %ux\n", hClient); DBG_BREAKPOINT(); @@ -953,6 +971,7 @@ pChidMgr->pFifoDataHeap, ChID, NV_FALSE); + NV_ASSERT_OR_RETURN(pFifoDataBlock != NULL, NV_ERR_OBJECT_NOT_FOUND); NV_ASSERT(pFifoDataBlock->refCount > 0); pFifoDataBlock->pData = NULL; @@ -999,6 +1018,7 @@ NvU32 flags, NvU32 gfid, NvU32 *pChidOffset, + NvU32 *pChannelCount, NvHandle hMigClient, NvU32 engineFifoListNumEntries, FIFO_ENGINE_LIST *pEngineFifoList @@ -1063,8 +1083,8 @@ pIsolationIdBlock->pData = pIsolationID; status = kfifoSetChidOffset(pGpu, pKernelFifo, pChidMgr, (NvU32)offset, - numChannels, gfid, pChidOffset, hMigClient, - engineFifoListNumEntries, pEngineFifoList); + numChannels, gfid, pChidOffset, pChannelCount, + hMigClient, engineFifoListNumEntries, pEngineFifoList); if (status != NV_OK) { @@ -1081,6 +1101,7 @@ "channel ID heap\n"); goto cleanup; } + portMemSet(pChidMgr->ppVirtualChIDHeap[gfid], 0, sizeof(OBJEHEAP)); // // Construct heap using low as offset and size of numChannels. This heap @@ -1102,7 +1123,7 @@ cleanup: portMemFree(pChidMgr->ppVirtualChIDHeap[gfid]); NV_ASSERT(kfifoSetChidOffset(pGpu, pKernelFifo, pChidMgr, 0, 0, - gfid, pChidOffset, hMigClient, + gfid, pChidOffset, pChannelCount, hMigClient, engineFifoListNumEntries, pEngineFifoList) == NV_OK); NV_ASSERT(pChidMgr->pGlobalChIDHeap->eheapFree(pChidMgr->pGlobalChIDHeap, offset) == NV_OK); portMemFree(pIsolationID); @@ -1118,6 +1139,7 @@ CHID_MGR *pChidMgr, NvU32 gfid, NvU32 *pChidOffset, + NvU32 *pChannelCount, NvHandle hMigClient, NvU32 engineFifoListNumEntries, FIFO_ENGINE_LIST *pEngineFifoList @@ -1162,7 +1184,7 @@ } tmpStatus = kfifoSetChidOffset(pGpu, pKernelFifo, pChidMgr, 0, 0, - gfid, pChidOffset, hMigClient, + gfid, pChidOffset, pChannelCount, hMigClient, engineFifoListNumEntries, pEngineFifoList); if (tmpStatus != NV_OK) { @@ -1858,14 +1880,13 @@ NvHandle hClient = NV01_NULL_OBJECT; NvHandle hObject = NV01_NULL_OBJECT; NV2080_CTRL_FIFO_GET_DEVICE_INFO_TABLE_PARAMS *pParams; - NV2080_CTRL_FIFO_DEVICE_ENTRY *pHostEntries; + NV2080_CTRL_FIFO_DEVICE_ENTRY *pFetchedTable; NvU32 numEntries; NvU32 device; NvU32 entry; NvU32 numRunlists; NvU32 maxRunlistId; NvU32 maxPbdmaId; - NvU32 minPbdmaFaultId; NvU32 i; struct { NV2080_CTRL_FIFO_GET_DEVICE_INFO_TABLE_PARAMS params; @@ -1886,21 +1907,28 @@ } else { + RsClient *pClient; + Subdevice *pSubdevice; + hClient = hMigClient; - if ((status = CliGetSubDeviceHandleFromGpu(hClient, pGpu, &hObject)) != NV_OK) - { - NV_PRINTF(LEVEL_ERROR, "Unable to get subdevice handle.\n"); - return NV_ERR_INVALID_STATE; - } + + NV_ASSERT_OK_OR_RETURN( + serverGetClientUnderLock(&g_resServ, hClient, &pClient)); + + NV_ASSERT_OK_OR_RETURN(subdeviceGetByGpu(pClient, pGpu, &pSubdevice)); + + GPU_RES_SET_THREAD_BC_STATE(pSubdevice); + + hObject = RES_GET_HANDLE(pSubdevice); } } - // Allocate pHostEntries and params on the heap to avoid stack overflow + // Allocate pFetchedTable and params on the heap to avoid stack overflow pLocals = portMemAllocNonPaged(sizeof(*pLocals)); NV_ASSERT_OR_RETURN((pLocals != NULL), NV_ERR_NO_MEMORY); pParams = &pLocals->params; - pHostEntries = pLocals->entries; + pFetchedTable = pLocals->entries; // // Read device info table entries from Host RM until Host indicates that @@ -1934,9 +1962,10 @@ goto cleanup; } - portMemCopy(&pHostEntries[device], pParams->numEntries * - sizeof(NV2080_CTRL_FIFO_DEVICE_ENTRY), pParams->entries, pParams->numEntries * - sizeof(NV2080_CTRL_FIFO_DEVICE_ENTRY)); + portMemCopy(&pFetchedTable[device], + pParams->numEntries * (sizeof *pFetchedTable), + pParams->entries, + pParams->numEntries * (sizeof *pParams->entries)); numEntries += pParams->numEntries; @@ -1960,70 +1989,79 @@ numRunlists = 0; maxRunlistId = 0; maxPbdmaId = 0; - minPbdmaFaultId = NV_U32_MAX; for (entry = 0; entry < numEntries; ++entry) { - portMemCopy(pEngineInfo->engineInfoList[entry].engineData, - ENGINE_INFO_TYPE_INVALID * sizeof(*(pEngineInfo->engineInfoList[entry].engineData)), - pHostEntries[entry].engineData, - ENGINE_INFO_TYPE_INVALID * sizeof(*(pEngineInfo->engineInfoList[entry].engineData))); - - pEngineInfo->engineInfoList[entry].numPbdmas = pHostEntries[entry].numPbdmas; - portMemCopy(pEngineInfo->engineInfoList[entry].pbdmaIds, - FIFO_ENGINE_MAX_NUM_PBDMA * sizeof(*(pEngineInfo->engineInfoList[entry].pbdmaIds)), - pHostEntries[entry].pbdmaIds, - FIFO_ENGINE_MAX_NUM_PBDMA * sizeof(*(pEngineInfo->engineInfoList[entry].pbdmaIds))); - - portMemCopy(pEngineInfo->engineInfoList[entry].pbdmaFaultIds, - FIFO_ENGINE_MAX_NUM_PBDMA * sizeof(*(pEngineInfo->engineInfoList[entry].pbdmaFaultIds)), - pHostEntries[entry].pbdmaFaultIds, - FIFO_ENGINE_MAX_NUM_PBDMA * sizeof(*(pEngineInfo->engineInfoList[entry].pbdmaFaultIds))); - - portStringCopy((char *)pEngineInfo->engineInfoList[entry].engineName, - sizeof(pEngineInfo->engineInfoList[entry].engineName), - (char *)pHostEntries[entry].engineName, - FIFO_ENGINE_NAME_MAX_SIZE); + FIFO_ENGINE_LIST *pLocalEntry = &pEngineInfo->engineInfoList[entry]; + NV2080_CTRL_FIFO_DEVICE_ENTRY *pFetchedEntry = &pFetchedTable[entry]; - if (0 != pEngineInfo->engineInfoList[entry].engineData[ENGINE_INFO_TYPE_IS_ENGINE]) + ct_assert(sizeof pLocalEntry->engineData <= + sizeof pFetchedEntry->engineData); + portMemCopy(pLocalEntry->engineData, + sizeof pLocalEntry->engineData, + pFetchedEntry->engineData, + NV_ARRAY_ELEMENTS(pLocalEntry->engineData) * + (sizeof *pFetchedEntry->engineData)); + + pLocalEntry->numPbdmas = pFetchedEntry->numPbdmas; + NV_ASSERT_TRUE_OR_GOTO(status, + pLocalEntry->numPbdmas <= + NV_ARRAY_ELEMENTS(pLocalEntry->pbdmaIds) && + pLocalEntry->numPbdmas <= + NV_ARRAY_ELEMENTS(pLocalEntry->pbdmaFaultIds), + NV_ERR_INVALID_STATE, + cleanup); + portMemCopy( + pLocalEntry->pbdmaIds, + pLocalEntry->numPbdmas * (sizeof *(pLocalEntry->pbdmaIds)), + pFetchedEntry->pbdmaIds, + pLocalEntry->numPbdmas * (sizeof *(pFetchedEntry->pbdmaIds))); + portMemCopy( + pLocalEntry->pbdmaFaultIds, + pLocalEntry->numPbdmas * (sizeof *(pLocalEntry->pbdmaFaultIds)), + pFetchedEntry->pbdmaFaultIds, + pLocalEntry->numPbdmas * (sizeof *(pFetchedEntry->pbdmaFaultIds))); + + portStringCopy(pLocalEntry->engineName, + sizeof pLocalEntry->engineName, + pFetchedEntry->engineName, + sizeof pFetchedEntry->engineName); + + if (pLocalEntry->engineData[ENGINE_INFO_TYPE_IS_HOST_DRIVEN_ENGINE] != 0) { numRunlists++; } maxRunlistId = NV_MAX(maxRunlistId, - pHostEntries[entry].engineData[ENGINE_INFO_TYPE_RUNLIST]); + pFetchedEntry->engineData[ENGINE_INFO_TYPE_RUNLIST]); - for (i = 0; i < pEngineInfo->engineInfoList[entry].numPbdmas; i++) + for (i = 0; i < pLocalEntry->numPbdmas; i++) { - maxPbdmaId = NV_MAX(maxPbdmaId, pEngineInfo->engineInfoList[entry].pbdmaIds[i]); + maxPbdmaId = NV_MAX(maxPbdmaId, pLocalEntry->pbdmaIds[i]); // // SW engine while being constructed does not populate any PBDMA Fault IDs. // Hence, skipping it. // - if (pEngineInfo->engineInfoList[entry].engineData[ENGINE_INFO_TYPE_ENG_DESC] != ENG_SW) + if (pLocalEntry->engineData[ENGINE_INFO_TYPE_ENG_DESC] != ENG_SW) { - minPbdmaFaultId = NV_MIN(minPbdmaFaultId, pEngineInfo->engineInfoList[entry].pbdmaFaultIds[i]); + bitVectorSet(&pEngineInfo->validEngineIdsForPbdmas, pLocalEntry->pbdmaFaultIds[i]); } } } + NV_ASSERT_OK_OR_GOTO(status, + kfifoReservePbdmaFaultIds_HAL(pGpu, pKernelFifo, + pEngineInfo->engineInfoList, + pEngineInfo->engineInfoListSize), + cleanup); + if (IS_VIRTUAL(pGpu)) { _kfifoLocalizeGuestEngineData(pGpu, pKernelFifo, pEngineInfo); } - // - // Host RM sends back a copy of their devinfo table, which includes the SW - // engine. This engine has no runlist, so decrement the runlist count. - // - if (numRunlists > 0) - { - --numRunlists; - } - pEngineInfo->numRunlists = numRunlists; pEngineInfo->maxNumRunlists = maxRunlistId + 1; pEngineInfo->maxNumPbdmas = maxPbdmaId + 1; - pEngineInfo->basePbdmaFaultId = minPbdmaFaultId; cleanup: portMemFree(pLocals); @@ -3071,6 +3109,7 @@ NvU32 numChannels, NvU32 gfid, NvU32 *pChidOffset, + NvU32 *pChannelCount, NvU32 hMigClient, NvU32 engineFifoListNumEntries, FIFO_ENGINE_LIST *pEngineFifoList @@ -3094,6 +3133,7 @@ { NV_ASSERT_OR_ELSE(NV2080_ENGINE_TYPE_IS_VALID(pEngineIds[i]), status = NV_ERR_INVALID_STATE; goto cleanup); pChidOffset[pEngineIds[i]] = offset; + pChannelCount[pEngineIds[i]] = numChannels; } NV_ASSERT_OK_OR_GOTO(status, kfifoProgramChIdTable_HAL(pGpu, pKernelFifo, pChidMgr, offset, numChannels, gfid, @@ -3369,3 +3409,31 @@ return guestEngineLookupTable; }; +/** + * @brief Fetch the maximum number of secure channels supported by SEC2 + * and secure CEs when confidential compute is enabled + * + */ +NV_STATUS +kfifoGetMaxSecureChannels_KERNEL +( + OBJGPU *pGpu, + KernelFifo *pKernelFifo +) +{ + RM_API *pRmApi = GPU_GET_PHYSICAL_RMAPI(pGpu); + NV2080_CTRL_INTERNAL_FIFO_GET_NUM_SECURE_CHANNELS_PARAMS numSecureChannelsParams = {0}; + + NV_ASSERT_OK_OR_RETURN( + pRmApi->Control(pRmApi, + pGpu->hInternalClient, + pGpu->hInternalSubdevice, + NV2080_CTRL_CMD_INTERNAL_FIFO_GET_NUM_SECURE_CHANNELS, + &numSecureChannelsParams, + sizeof(numSecureChannelsParams))); + + pKernelFifo->maxSec2SecureChannels = numSecureChannelsParams.maxSec2SecureChannels; + pKernelFifo->maxCeSecureChannels = numSecureChannelsParams.maxCeSecureChannels; + + return NV_OK; +} diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/kernel/gpu/fifo/kernel_fifo_ctrl.c nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/kernel/gpu/fifo/kernel_fifo_ctrl.c --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/kernel/gpu/fifo/kernel_fifo_ctrl.c 2023-10-25 20:21:01.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/kernel/gpu/fifo/kernel_fifo_ctrl.c 2024-03-05 22:13:25.000000000 +0000 @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 2021-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2021-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -44,11 +44,7 @@ static NV_STATUS _kfifoGetCaps(OBJGPU *pGpu, NvU8 *pKfifoCaps); /*! - * * @brief deviceCtrlCmdFifoGetChannelList - * - * Lock Requirements: - * Assert that API lock and GPUs lock held on entry */ NV_STATUS deviceCtrlCmdFifoGetChannelList_IMPL @@ -62,8 +58,6 @@ NvU32 *pChannelList = NvP64_VALUE(pChannelParams->pChannelList); NvU32 counter; - LOCK_ASSERT_AND_RETURN(rmapiLockIsOwner() && rmGpuLockIsOwner()); - // Validate input / Size / Args / Copy args if (pChannelParams->numChannels == 0) { @@ -79,7 +73,8 @@ NV_STATUS status; // Searching through the rm client db. - status = CliGetKernelChannel(RES_GET_CLIENT_HANDLE(pDevice), pChannelHandleList[counter], &pKernelChannel); + status = CliGetKernelChannel(RES_GET_CLIENT(pDevice), + pChannelHandleList[counter], &pKernelChannel); if (status == NV_OK) { @@ -370,8 +365,6 @@ NV2080_CTRL_CMD_FIFO_GET_USERD_LOCATION_PARAMS *pUserdLocationParams ) { - RsClient *pClient = RES_GET_CLIENT(pSubdevice); - Device *pDevice; NvU32 userdAperture; NvU32 userdAttribute; NV_STATUS rmStatus = NV_OK; @@ -380,10 +373,6 @@ LOCK_ASSERT_AND_RETURN(rmapiLockIsOwner() && rmGpuLockIsOwner()); - rmStatus = deviceGetByGpu(pClient, pGpu, NV_TRUE, &pDevice); - if (rmStatus != NV_OK) - return NV_ERR_INVALID_DEVICE; - rmStatus = kfifoGetUserdLocation_HAL(pKernelFifo, &userdAperture, &userdAttribute); @@ -444,7 +433,7 @@ ) { OBJGPU *pGpu = GPU_RES_GET_GPU(pSubdevice); - Device *pDevice; + NvHandle hDevice = RES_GET_PARENT_HANDLE(pSubdevice); RsClient *pClient = RES_GET_CLIENT(pSubdevice); NV_STATUS rmStatus = NV_OK; NvU32 index; @@ -456,12 +445,8 @@ LOCK_ASSERT_AND_RETURN(rmapiLockIsOwner() && rmGpuLockIsOwner()); - rmStatus = deviceGetByGpu(pClient, pGpu, NV_TRUE, &pDevice); - if (rmStatus != NV_OK) - return NV_ERR_INVALID_DEVICE; - - rmStatus = CliGetKernelChannelWithDevice(pClient->hClient, - RES_GET_HANDLE(pDevice), + rmStatus = CliGetKernelChannelWithDevice(pClient, + hDevice, pChannelMemParams->hChannel, &pKernelChannel); if (rmStatus != NV_OK) @@ -484,11 +469,15 @@ // Get RAMFC mem Info pMemDesc = NULL; - kfifoChannelGetFifoContextMemDesc_HAL(pGpu, + rmStatus = kfifoChannelGetFifoContextMemDesc_HAL(pGpu, pKernelFifo, pKernelChannel, FIFO_CTX_RAMFC, &pMemDesc); + + if (rmStatus != NV_OK) + return rmStatus; + kfifoFillMemInfo(pKernelFifo, pMemDesc, &chMemInfo.ramfc); // Get Method buffer mem info @@ -521,18 +510,13 @@ NV208F_CTRL_FIFO_ENABLE_VIRTUAL_CONTEXT_PARAMS *pEnableVCParams ) { - OBJGPU *pGpu = GPU_RES_GET_GPU(pDiagApi); - Device *pDevice; NV_STATUS rmStatus = NV_OK; KernelChannel *pKernelChannel = NULL; RsClient *pClient = RES_GET_CLIENT(pDiagApi); - - rmStatus = deviceGetByGpu(pClient, pGpu, NV_TRUE, &pDevice); - if (rmStatus != NV_OK) - return NV_ERR_INVALID_DEVICE; + Device *pDevice = GPU_RES_GET_DEVICE(pDiagApi); NV_CHECK_OK_OR_RETURN(LEVEL_INFO, - CliGetKernelChannelWithDevice(pClient->hClient, + CliGetKernelChannelWithDevice(pClient, RES_GET_HANDLE(pDevice), pEnableVCParams->hChannel, &pKernelChannel)); @@ -561,6 +545,7 @@ CALL_CONTEXT *pCallContext = resservGetTlsCallContext(); RmCtrlParams *pRmCtrlParams = pCallContext->pControlParams; OBJGPU *pGpu = GPU_RES_GET_GPU(pSubdevice); + RsClient *pChannelClient; NvHandle hClient = RES_GET_CLIENT_HANDLE(pSubdevice); KernelChannel *pKernelChannel = NULL; NV_STATUS status = NV_OK; @@ -571,7 +556,12 @@ LOCK_ASSERT_AND_RETURN(pRmCtrlParams->bDeferredApi || rmGpuLockIsOwner()); NV_CHECK_OK_OR_RETURN(LEVEL_INFO, - CliGetKernelChannel(pChannelInfo->hClient, + serverGetClientUnderLock(&g_resServ, + pChannelInfo->hClient, + &pChannelClient)); + + NV_CHECK_OK_OR_RETURN(LEVEL_INFO, + CliGetKernelChannel(pChannelClient, pChannelInfo->hChannel, &pKernelChannel)); NV_ASSERT_OR_RETURN(pKernelChannel != NULL, NV_ERR_INVALID_CHANNEL); @@ -631,10 +621,15 @@ ) { OBJGPU *pGpu = GPU_RES_GET_GPU(pDiagApi); + RsClient *pChannelClient; KernelChannel *pKernelChannel; NV_CHECK_OK_OR_RETURN(LEVEL_INFO, - CliGetKernelChannel(pChannelStateParams->hClient, pChannelStateParams->hChannel, &pKernelChannel)); + serverGetClientUnderLock(&g_resServ, pChannelStateParams->hClient, + &pChannelClient)); + + NV_CHECK_OK_OR_RETURN(LEVEL_INFO, + CliGetKernelChannel(pChannelClient, pChannelStateParams->hChannel, &pKernelChannel)); NV_CHECK_OK_OR_RETURN(LEVEL_INFO, kchannelGetChannelPhysicalState(pGpu, pKernelChannel, pChannelStateParams)); diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/kernel/gpu/fifo/kernel_fifo_init.c nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/kernel/gpu/fifo/kernel_fifo_init.c --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/kernel/gpu/fifo/kernel_fifo_init.c 2023-10-25 20:21:01.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/kernel/gpu/fifo/kernel_fifo_init.c 2024-03-05 22:13:25.000000000 +0000 @@ -34,7 +34,7 @@ static void _kfifoPreConstructRegistryOverrides(OBJGPU *pGpu, KernelFifo *pKernelFifo); -NV_STATUS +NV_STATUS kfifoConstructEngine_IMPL ( OBJGPU *pGpu, @@ -144,6 +144,8 @@ } } + NV_ASSERT_OK_OR_RETURN(kfifoConstructUsermodeMemdescs_HAL(pGpu, pKernelFifo)); + NV_ASSERT_OK_OR_RETURN(kfifoChidMgrConstruct(pGpu, pKernelFifo)); if (pKernelRc != NULL) @@ -151,6 +153,9 @@ krcInitRegistryOverridesDelayed(pGpu, pKernelRc); } + // Get maximum number of secure channels when APM/HCC is enabled + NV_ASSERT_OK_OR_RETURN(kfifoGetMaxSecureChannels(pGpu, pKernelFifo)); + return NV_OK; } @@ -209,5 +214,10 @@ // kfifoChidMgrDestruct(pKernelFifo); + // Destroy regardless of NULL, if pointers are null, is just a NOP + memdescDestroy(pKernelFifo->pRegVF); + memdescDestroy(pKernelFifo->pBar1VF); + memdescDestroy(pKernelFifo->pBar1PrivVF); + return; } diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/kernel/gpu/fifo/kernel_idle_channels.c nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/kernel/gpu/fifo/kernel_idle_channels.c --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/kernel/gpu/fifo/kernel_idle_channels.c 2023-10-25 20:21:01.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/kernel/gpu/fifo/kernel_idle_channels.c 2024-03-05 22:13:25.000000000 +0000 @@ -141,7 +141,7 @@ GpuResource *pGpuResource; // - // Don't allow other clients' resources to be accessed/modified by this + // Don't allow other clients' resources to be accessed/modified by this // control call. // if (hClient != phClients[chanIdx]) diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/kernel/gpu/fifo/kernel_sched_mgr.c nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/kernel/gpu/fifo/kernel_sched_mgr.c --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/kernel/gpu/fifo/kernel_sched_mgr.c 2023-10-25 20:21:01.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/kernel/gpu/fifo/kernel_sched_mgr.c 2024-03-05 22:13:25.000000000 +0000 @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 2021 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2021-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -59,14 +59,25 @@ switch (schedPolicy) { + case SCHED_POLICY_DEFAULT: default: - if (hypervisorIsVgxHyper()) - return "BEST_EFFORT"; - else // For baremetal and PT - return "NONE"; + // For baremetal and PT + return "NONE"; } } +void kschedmgrSetConfigPolicyFromUser_IMPL +( + KernelSchedMgr *pKernelSchedMgr, + OBJGPU *pGpu, + NvU32 schedSwPolicy +) +{ + NvU32 schedSwPolicyLocal = SCHED_POLICY_DEFAULT; + pKernelSchedMgr->configSchedPolicy = schedSwPolicyLocal; + pKernelSchedMgr->bIsSchedSwEnabled = (schedSwPolicyLocal != SCHED_POLICY_DEFAULT); +} + /*! * Configure PDBs related to scheduler policy per RM configuration. */ diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/kernel/gpu/fifo/usermode_api.c nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/kernel/gpu/fifo/usermode_api.c --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/kernel/gpu/fifo/usermode_api.c 2023-10-25 20:21:01.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/kernel/gpu/fifo/usermode_api.c 2024-03-05 22:13:26.000000000 +0000 @@ -22,6 +22,11 @@ */ #include "kernel/gpu/fifo/usermode_api.h" +#include "kernel/gpu/fifo/kernel_fifo.h" + +#include "class/clc661.h" // HOPPER_USERMODE_A +#include "class/cl003e.h" // NV01_MEMORY_SYSTEM +#include "class/cl003f.h" // NV01_MEMORY_LOCAL_PRIVILEGED NV_STATUS usrmodeConstruct_IMPL @@ -31,7 +36,56 @@ RS_RES_ALLOC_PARAMS_INTERNAL *pParams ) { - return usrmodeConstructHal_HAL(pUserModeApi, pCallContext, pParams); + Memory *pMemory = staticCast(pUserModeApi, Memory); + OBJGPU *pGpu = pMemory->pGpu; + KernelFifo *pKernelFifo = GPU_GET_KERNEL_FIFO(pGpu); + NV_HOPPER_USERMODE_A_PARAMS *pAllocParams = (NV_HOPPER_USERMODE_A_PARAMS*) pParams->pAllocParams; + NvU32 hClass = pCallContext->pResourceRef->externalClassId; + NvBool bBar1Mapping = NV_FALSE; + NvBool bPrivMapping = NV_FALSE; + MEMORY_DESCRIPTOR *pMemDesc = pKernelFifo->pRegVF; + + // Copy-construction has already been done by the base Memory class + if (RS_IS_COPY_CTOR(pParams)) + { + return NV_OK; + } + + // + // We check pKernelFifo->pBar1VF because for some reason RM allows HOPPER_USERMODE_A on ADA. + // This is a WAR until we root cause. + // + if (hClass >= HOPPER_USERMODE_A && pAllocParams != NULL && pKernelFifo->pBar1VF != NULL) + { + bBar1Mapping = pAllocParams->bBar1Mapping; + bPrivMapping = pAllocParams->bPriv; + } + + if (pGpu->getProperty(pGpu, PDB_PROP_GPU_COHERENT_CPU_MAPPING) || + pGpu->getProperty(pGpu, PDB_PROP_GPU_IS_ALL_INST_IN_SYSMEM)) + { + bBar1Mapping = NV_FALSE; + } + + NV_CHECK_OR_RETURN(LEVEL_ERROR, + !bPrivMapping || bBar1Mapping, + NV_ERR_INVALID_PARAMETER); + + NV_CHECK_OR_RETURN(LEVEL_ERROR, + !bPrivMapping || pCallContext->secInfo.privLevel >= RS_PRIV_LEVEL_KERNEL, + NV_ERR_INSUFFICIENT_PERMISSIONS); + + if (bBar1Mapping) + { + pMemDesc = bPrivMapping ? pKernelFifo->pBar1PrivVF : pKernelFifo->pBar1VF; + } + + NV_CHECK_OK_OR_RETURN(LEVEL_ERROR, + memConstructCommon(pMemory, + bBar1Mapping? NV01_MEMORY_SYSTEM : NV01_MEMORY_LOCAL_PRIVILEGED, + 0, pMemDesc, 0, NULL, 0, 0, 0, 0, NVOS32_MEM_TAG_NONE, NULL)); + memdescAddRef(pMemDesc); + return NV_OK; } NvBool diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/kernel/gpu/fifo/uvm_channel_retainer.c nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/kernel/gpu/fifo/uvm_channel_retainer.c --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/kernel/gpu/fifo/uvm_channel_retainer.c 2023-10-25 20:21:01.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/kernel/gpu/fifo/uvm_channel_retainer.c 2024-03-05 22:13:26.000000000 +0000 @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 2016-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2016-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -38,7 +38,7 @@ * * @returns NV_OK on success, specific error code on failure. */ -NV_STATUS +NV_STATUS uvmchanrtnrConstruct_IMPL ( UvmChannelRetainer *pUvmChannelRetainer, @@ -49,11 +49,15 @@ OBJGPU *pGpu = GPU_RES_GET_GPU(pUvmChannelRetainer); KernelFifo *pKernelFifo = GPU_GET_KERNEL_FIFO(pGpu); NV_STATUS rmStatus = NV_OK; + RsClient *pChannelClient; KernelChannel *pKernelChannel = NULL; NV_UVM_CHANNEL_RETAINER_ALLOC_PARAMS *pUvmChannelRetainerParams = pParams->pAllocParams; CHID_MGR *pChidMgr = NULL; - NV_ASSERT_OK_OR_RETURN(CliGetKernelChannel(pUvmChannelRetainerParams->hClient, pUvmChannelRetainerParams->hChannel, &pKernelChannel)); + NV_ASSERT_OK_OR_RETURN(serverGetClientUnderLock(&g_resServ, + pUvmChannelRetainerParams->hClient, &pChannelClient)); + + NV_ASSERT_OK_OR_RETURN(CliGetKernelChannel(pChannelClient, pUvmChannelRetainerParams->hChannel, &pKernelChannel)); if (!uvmchanrtnrIsAllocationAllowed(pUvmChannelRetainer, pCallContext, pKernelChannel)) { @@ -91,7 +95,7 @@ return rmStatus; } -void +void uvmchanrtnrDestruct_IMPL ( UvmChannelRetainer *pUvmChannelRetainer diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/kernel/gpu/fsp/arch/hopper/kern_fsp_gh100.c nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/kernel/gpu/fsp/arch/hopper/kern_fsp_gh100.c --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/kernel/gpu/fsp/arch/hopper/kern_fsp_gh100.c 2023-10-25 20:21:01.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/kernel/gpu/fsp/arch/hopper/kern_fsp_gh100.c 2024-03-05 22:13:26.000000000 +0000 @@ -33,20 +33,17 @@ #include "published/hopper/gh100/dev_fsp_pri.h" #include "published/hopper/gh100/dev_fsp_addendum.h" +#include "fsp/fsp_nvdm_format.h" #include "published/hopper/gh100/dev_gc6_island_addendum.h" +#include "published/hopper/gh100/dev_falcon_v4.h" +#include "published/hopper/gh100/dev_gsp.h" #include "published/hopper/gh100/dev_therm.h" #include "published/hopper/gh100/dev_therm_addendum.h" #include "os/os.h" #include "nvRmReg.h" #include "nverror.h" -#if RMCFG_MODULE_ENABLED (FSP) -#include "hopper/gh100/dev_gsp.h" -#include "gpu/gsp/gsp.h" -#include "gsp/memmap.h" -#include "objfsp.h" -#include "objflcnable.h" -#endif +#include "gpu/conf_compute/conf_compute.h" /*! * @brief Update command queue head and tail pointers @@ -171,7 +168,7 @@ NvU8 kfspNvdmToSeid_GH100 ( - POBJGPU pGpu, + OBJGPU *pGpu, KernelFsp *pKernelFsp, NvU8 nvdmType ) @@ -626,13 +623,13 @@ status = gpuCheckTimeout(pGpu, &timeout); if (status == NV_ERR_TIMEOUT) { - nvErrorLog_va((void*) pGpu, GPU_INIT_ERROR, "Timeout while polling for FSP boot complete, " - "0x%x, 0x%x, 0x%x, 0x%x, 0x%x", - GPU_REG_RD32(pGpu, NV_THERM_I2CS_SCRATCH_FSP_BOOT_COMPLETE), - GPU_REG_RD32(pGpu, NV_PFSP_FALCON_COMMON_SCRATCH_GROUP_2(0)), - GPU_REG_RD32(pGpu, NV_PFSP_FALCON_COMMON_SCRATCH_GROUP_2(1)), - GPU_REG_RD32(pGpu, NV_PFSP_FALCON_COMMON_SCRATCH_GROUP_2(2)), - GPU_REG_RD32(pGpu, NV_PFSP_FALCON_COMMON_SCRATCH_GROUP_2(3))); + NV_ERROR_LOG((void*) pGpu, GPU_INIT_ERROR, "Timeout while polling for FSP boot complete, " + "0x%x, 0x%x, 0x%x, 0x%x, 0x%x", + GPU_REG_RD32(pGpu, NV_THERM_I2CS_SCRATCH_FSP_BOOT_COMPLETE), + GPU_REG_RD32(pGpu, NV_PFSP_FALCON_COMMON_SCRATCH_GROUP_2(0)), + GPU_REG_RD32(pGpu, NV_PFSP_FALCON_COMMON_SCRATCH_GROUP_2(1)), + GPU_REG_RD32(pGpu, NV_PFSP_FALCON_COMMON_SCRATCH_GROUP_2(2)), + GPU_REG_RD32(pGpu, NV_PFSP_FALCON_COMMON_SCRATCH_GROUP_2(3))); break; } } @@ -662,25 +659,40 @@ static const BINDATA_ARCHIVE * kfspGetGspUcodeArchive ( - POBJGPU pGpu, + OBJGPU *pGpu, KernelFsp *pKernelFsp ) { KernelGsp *pKernelGsp = GPU_GET_KERNEL_GSP(pGpu); + ConfidentialCompute *pCC = GPU_GET_CONF_COMPUTE(pGpu); + NV_ASSERT(pCC != NULL); if (pKernelFsp->getProperty(pKernelFsp, PDB_PROP_KFSP_GSP_MODE_GSPRM)) { - NV_PRINTF(LEVEL_ERROR, "Loading GSP-RM image using FSP.\n"); + NV_PRINTF(LEVEL_NOTICE, "Loading GSP-RM image using FSP.\n"); if (kgspIsDebugModeEnabled_HAL(pGpu, pKernelGsp)) { + if (pCC != NULL && pCC->getProperty(pCC, PDB_PROP_CONFCOMPUTE_CC_FEATURE_ENABLED)) + { + NV_PRINTF(LEVEL_ERROR, "GSP-RM image for CC not found\n"); + return NULL; + } + else { return kgspGetBinArchiveGspRmFmcGfwDebugSigned_HAL(pKernelGsp); } } else { - return kgspGetBinArchiveGspRmFmcGfwProdSigned_HAL(pKernelGsp); + if (pCC != NULL && pCC->getProperty(pCC, PDB_PROP_CONFCOMPUTE_CC_FEATURE_ENABLED)) + { + return kgspGetBinArchiveGspRmCcFmcGfwProdSigned_HAL(pKernelGsp); + } + else + { + return kgspGetBinArchiveGspRmFmcGfwProdSigned_HAL(pKernelGsp); + } } } #if RMCFG_MODULE_ENABLED (GSP) @@ -706,6 +718,15 @@ // NV_ASSERT_OR_RETURN(gspSetupRMProxyImage(pGpu, pGsp) == NV_OK, NULL); + // For debug board if CC is enabled pick spdm profile of gspcc ucode + if (pCC->getProperty(pCC, PDB_PROP_CONFCOMPUTE_ENABLED) == NV_TRUE) + { + + { + return gspGetBinArchiveGspFmcSpdmGfwDebugSigned_HAL(pGsp); + } + } + else { return gspGetBinArchiveGspFmcGfwDebugSigned_HAL(pGsp); } @@ -720,6 +741,11 @@ else { NV_ASSERT_OR_RETURN(gspSetupRMProxyImage(pGpu, pGsp) == NV_OK, NULL); + if (pCC->getProperty(pCC, PDB_PROP_CONFCOMPUTE_ENABLED) == NV_TRUE) + { + return gspGetBinArchiveGspCcFmcGfwProdSigned_HAL(pGsp); + } + else { return gspGetBinArchiveGspFmcGfwProdSigned_HAL(pGsp); } @@ -738,13 +764,16 @@ static NV_STATUS kfspGetGspBootArgs ( - POBJGPU pGpu, + OBJGPU *pGpu, KernelFsp *pKernelFsp, RmPhysAddr *pBootArgsGspSysmemOffset ) { NV_STATUS status = NV_OK; + ConfidentialCompute *pCC = GPU_GET_CONF_COMPUTE(pGpu); + NV_ASSERT(pCC != NULL); + if (pKernelFsp->getProperty(pKernelFsp, PDB_PROP_KFSP_GSP_MODE_GSPRM)) { KernelGsp *pKernelGsp = GPU_GET_KERNEL_GSP(pGpu); @@ -770,7 +799,7 @@ static NV_STATUS kfspSetupGspImages ( - POBJGPU pGpu, + OBJGPU *pGpu, KernelFsp *pKernelFsp, NVDM_PAYLOAD_COT *pCotPayload ) @@ -786,6 +815,13 @@ NvU32 pGspImageMapSize; NvP64 pVaKernel = NULL; NvP64 pPrivKernel = NULL; + NvU64 flags = MEMDESC_FLAGS_NONE; + + // + // On systems with SEV enabled, the GSP-FMC image has to be accessible + // to FSP (an unit inside GPU) and hence placed in unprotected sysmem + // + flags = MEMDESC_FLAGS_ALLOC_IN_UNPROTECTED_MEMORY; // Detect the mode of operation for GSP and fetch the right image to boot pBinArchive = kfspGetGspUcodeArchive(pGpu, pKernelFsp); @@ -813,8 +849,7 @@ pGspImageMapSize = NV_ALIGN_UP(pGspImageSize, 0x1000); status = memdescCreate(&pKernelFsp->pGspFmcMemdesc, pGpu, pGspImageMapSize, - 0, NV_TRUE, ADDR_SYSMEM, NV_MEMORY_CACHED, - MEMDESC_FLAGS_NONE); + 0, NV_TRUE, ADDR_SYSMEM, NV_MEMORY_CACHED, flags); NV_ASSERT_OR_GOTO(status == NV_OK, failed); status = memdescAlloc(pKernelFsp->pGspFmcMemdesc); @@ -856,91 +891,63 @@ return status; } -static NV_STATUS -_kfspCheckGspBootStatus +/*! + * Determine if PRIV target mask is unlocked for GSP and BAR0 Decoupler allows GSP access. + * + * This is temporary WAR for the PRIV target mask bug 3640831 until we have notification + * protocol in place (there is no HW mechanism for CPU to check if GSP is open other than + * reading 0xBADF41YY code). + * + * Until the programmed BAR0 decoupler settings are cleared, GSP access is blocked from + * the CPU so all reads will return 0. + */ +static NvBool +_kfspIsGspTargetMaskReleased ( - POBJGPU pGpu, - KernelFsp *pKernelFsp + OBJGPU *pGpu, + void *pVoid ) { -#if RMCFG_MODULE_ENABLED (FSP) - NV_STATUS status = NV_OK; - RMTIMEOUT timeout; - Gsp *pGsp = GPU_GET_GSP(pGpu); - Falcon *pFlcn = ENG_GET_FLCN(pGsp); - - pFlcn->bBootstrapped = NV_TRUE; - - // In Inst_in_sys mode GSP-FMC will write status to NV_PGSP_MAILBOX(0). - if (kfspCheckGspSecureScratch_HAL(pGpu, pKernelFsp)) - { - gpuSetTimeout(pGpu, GPU_TIMEOUT_DEFAULT, &timeout, GPU_TIMEOUT_FLAGS_OSTIMER | GPU_TIMEOUT_FLAGS_BYPASS_THREAD_STATE); - while(FLD_TEST_DRF_NUM(_PGSP, _MAILBOX, _DATA, GSP_INST_IN_SYS_COMPLETION_STATUS_IN_PROGRESS , GPU_REG_RD32(pGpu, NV_PGSP_MAILBOX(0)))) - { - status = gpuCheckTimeout(pGpu, &timeout); - if (status == NV_ERR_TIMEOUT) - { - NV_PRINTF(LEVEL_ERROR, "Timed out waiting for GSP Inst_in_sys ucode to boot\n"); - DBG_BREAKPOINT(); - break; - } - osSpinLoop(); - } - // Read GSP mailbox to check if it is booted successfully. - if (GPU_REG_RD32(pGpu, NV_PGSP_MAILBOX(0)) != GSP_INST_IN_SYS_COMPLETION_STATUS_OK) - { - NV_PRINTF(LEVEL_ERROR, "GSP Inst_in_sys ucode boot failed with GSP status 0x%x\n", GPU_REG_RD32(pGpu, NV_PGSP_MAILBOX(0))); - DBG_BREAKPOINT(); - } - return status; - } - - // Ensure priv lockdown is released before polling interrupts - gpuSetTimeout(pGpu, GPU_TIMEOUT_DEFAULT, &timeout, GPU_TIMEOUT_FLAGS_OSTIMER | GPU_TIMEOUT_FLAGS_BYPASS_THREAD_STATE); - do - { - if (flcnIsRiscvLockdownReleased_HAL(pGpu, pFlcn)) - { - status = NV_OK; - break; - } + const NvU32 privErrTargetLocked = 0xBADF4100U; + const NvU32 privErrTargetLockedMask = 0xFFFFFF00U; // Ignore LSB - it has extra error information + NvU32 reg; - status = gpuCheckTimeout(pGpu, &timeout); - if (status == NV_ERR_TIMEOUT) - { - NV_PRINTF(LEVEL_ERROR, "Timed out waiting for priv lockdown release.\n"); - DBG_BREAKPOINT(); - break; - } - osSpinLoop(); - } while (1); + // + // This register is read with the raw OS read to avoid the 0xbadf sanity checking + // done by the usual register read utilities. + // + reg = osDevReadReg032(pGpu, gpuGetDeviceMapping(pGpu, DEVICE_INDEX_GPU, 0), + DRF_BASE(NV_PGSP) + NV_PFALCON_FALCON_HWCFG2); - // Ensure GSP can send back init ack interrupt to CPU - do - { - gspServiceEarlyInterrupt_HAL(pGpu, pGsp); + return ((reg != 0) && ((reg & privErrTargetLockedMask) != privErrTargetLocked)); +} - if (pFlcn->bOSReady) - { - status = NV_OK; - break; - } +/*! + * Determine if GSP's target mask is released. + */ +NV_STATUS +kfspWaitForGspTargetMaskReleased_GH100 +( + OBJGPU *pGpu, + KernelFsp *pKernelFsp +) +{ + NV_STATUS status = NV_OK; - status = gpuCheckTimeout(pGpu, &timeout); - if (status == NV_ERR_TIMEOUT) - { - NV_PRINTF(LEVEL_ERROR, "Timed out waiting for GSP ucode to boot.\n"); - DBG_BREAKPOINT(); - break; - } - osSpinLoop(); - } while (1); + status = gpuTimeoutCondWait(pGpu, _kfspIsGspTargetMaskReleased, NULL, NULL); return status; -#else +} + +static NV_STATUS +_kfspCheckGspBootStatus +( + OBJGPU *pGpu, + KernelFsp *pKernelFsp +) +{ // On GSP-RM, the kgsp code path will check for GSP boot status return NV_OK; -#endif } /*! @@ -1041,12 +1048,6 @@ return NV_OK; } - if (pKernelFsp->getProperty(pKernelFsp, PDB_PROP_KFSP_BOOT_COMMAND_OK)) - { - NV_PRINTF(LEVEL_ERROR, "Cannot send FSP boot commands multiple times.\n"); - return NV_ERR_NOT_SUPPORTED; - } - // Confirm FSP secure boot partition is done statusBoot = kfspWaitForSecureBoot_HAL(pGpu, pKernelFsp); @@ -1087,9 +1088,15 @@ // Set up sysmem for FRTS copy if (!pKernelFsp->getProperty(pKernelFsp, PDB_PROP_KFSP_DISABLE_FRTS_SYSMEM)) { + NvU64 flags = MEMDESC_FLAGS_NONE; + + // + // On systems with SEV enabled, the FRTS has to be accessible to + // FSP (an unit inside GPU) and hence placed in unprotected sysmem + // + flags = MEMDESC_FLAGS_ALLOC_IN_UNPROTECTED_MEMORY; status = memdescCreate(&pKernelFsp->pSysmemFrtsMemdesc, pGpu, frtsSize, - 0, NV_TRUE, ADDR_SYSMEM, NV_MEMORY_CACHED, - MEMDESC_FLAGS_NONE); + 0, NV_TRUE, ADDR_SYSMEM, NV_MEMORY_CACHED, flags); NV_ASSERT_OR_GOTO(status == NV_OK, failed); status = memdescAlloc(pKernelFsp->pSysmemFrtsMemdesc); @@ -1122,9 +1129,24 @@ // Bug 200711957 has more info and tracks longer term improvements. // const NvU32 ESTIMATED_RESERVE_FB = 0x200000; + NvU64 frtsOffsetFromEnd = ESTIMATED_RESERVE_FB; + + KernelGsp *pKernelGsp = GPU_GET_KERNEL_GSP(pGpu); + + // + // In the boot retry path, we may need to apply an extra margin the end of memory. + // This is done to avoid memory with an ECC error that caused the first boot + // attempt failure. This value will be 0 during normal boot. + // + // Align the margin size to 2MB, as there's potentially an undocumented alignment + // requirement (the previous value should already be 2MB-aligned) and the extra + // padding won't hurt. + // + if (pKernelGsp != NULL) + frtsOffsetFromEnd += NV_ALIGN_UP64(kgspGetWprEndMargin(pGpu, pKernelGsp), 0x200000U); // Offset from end of FB to be used by FSP - pCotPayload->frtsVidmemOffset = ESTIMATED_RESERVE_FB; + pCotPayload->frtsVidmemOffset = frtsOffsetFromEnd; pCotPayload->frtsVidmemSize = frtsSize; } @@ -1144,7 +1166,7 @@ } status = kfspSendAndReadMessage(pGpu, pKernelFsp, (NvU8 *)pCotPayload, - sizeof(NVDM_PAYLOAD_COT), NVDM_TYPE_COT, NULL, 0); + sizeof(NVDM_PAYLOAD_COT), NVDM_TYPE_COT, NULL, 0); if (status != NV_OK) { NV_PRINTF(LEVEL_ERROR, "Sent following content to FSP: \n"); diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/kernel/gpu/fsp/kern_fsp.c nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/kernel/gpu/fsp/kern_fsp.c --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/kernel/gpu/fsp/kern_fsp.c 2023-10-25 20:21:01.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/kernel/gpu/fsp/kern_fsp.c 2024-03-05 22:13:26.000000000 +0000 @@ -103,10 +103,8 @@ } } - // Inst-in-sys must only set up FRTS in SYSMEM. This includes FB broken and cache only. - if (pGpu->getProperty(pGpu, PDB_PROP_GPU_IS_ALL_INST_IN_SYSMEM) || - pGpu->getProperty(pGpu, PDB_PROP_GPU_BROKEN_FB) || - gpuIsCacheOnlyModeEnabled(pGpu)) + // Inst-in-sys must only set up FRTS in SYSMEM. This includes FB broken. + if (pGpu->getProperty(pGpu, PDB_PROP_GPU_IS_ALL_INST_IN_SYSMEM)) { pKernelFsp->setProperty(pKernelFsp, PDB_PROP_KFSP_DISABLE_FRTS_VIDMEM, NV_TRUE); } diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/kernel/gpu/gpu.c nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/kernel/gpu/gpu.c --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/kernel/gpu/gpu.c 2023-10-25 20:21:02.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/kernel/gpu/gpu.c 2024-03-05 22:13:26.000000000 +0000 @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 1993-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 1993-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -46,6 +46,8 @@ #include "rmapi/rmapi_utils.h" #include "core/hal_mgr.h" #include "vgpu/rpc.h" +#include "jt.h" + #include "gpu/gpu_fabric_probe.h" #include "vgpu/vgpu_events.h" @@ -57,7 +59,9 @@ #include "platform/platform.h" #include "platform/chipset/chipset.h" #include "kernel/gpu/host_eng/host_eng.h" +#include "gpu/bif/kernel_bif.h" #include "gpu/ce/kernel_ce.h" +#include "gpu/conf_compute/conf_compute.h" #include "gpu/fifo/kernel_fifo.h" #include "kernel/gpu/intr/intr.h" @@ -104,7 +108,7 @@ static void gpuXlateHalImplToArchImpl(OBJGPU *, HAL_IMPLEMENTATION, NvU32 *, NvU32 *); static NvBool gpuSatisfiesTemporalOrder(OBJGPU *, HAL_IMPLEMENTATION); static NvBool gpuSatisfiesTemporalOrderMaskRev(OBJGPU *, HAL_IMPLEMENTATION, NvU32, NvU32, NvU32); -static NvBool gpuShouldCreateObject(PGPUCHILDINFO, PENGDESCRIPTOR, NvU32); +static NvBool gpuShouldCreateObject(OBJGPU *pGpu, GPUCHILDINFO *pChildInfo); static void gpuDestroyMissingEngine(OBJGPU *, OBJENGSTATE *); static void gpuRemoveMissingEngineClasses(OBJGPU *, NvU32); @@ -135,30 +139,22 @@ pPfm->setProperty(pPfm, PDB_PROP_PFM_NO_HOSTBRIDGE_DETECT, bValue); } -// Forward declare all the class definitions so that we don't need to pull in all the headers -#define GPU_CHILD(className, accessorName, numInstances, bConstructEarly, bAlwaysCreate, gpuField) \ - extern const struct NVOC_CLASS_DEF NV_CONCATENATE(__nvoc_class_def_, className); - -#include "gpu/gpu_child_list.h" - - // Describes a child type (e.g.: classId(OBJCE)) struct GPUCHILDTYPE { NvBool bConstructEarly; // bConstructEarly objects are created in a separate step. FUSE must be created // before BIF since we need to know the OPSB fuse value for enabling/disabling // certain features in bifInitRegistryOverrides - NvBool bAlwaysCreate; NvU32 instances; NvU32 gpuChildPtrOffset; - const NVOC_CLASS_INFO *pClassInfo; // NULL if engine is disabled by chip-config + NVOC_CLASS_ID classId; }; // List of all possible GPU offspring static GPUCHILDTYPE gpuChildTypeList[] = { - #define GPU_CHILD(className, accessorName, numInstances, bConstructEarly, bAlwaysCreate, gpuField) \ - { bConstructEarly, bAlwaysCreate, numInstances, NV_OFFSETOF(OBJGPU, gpuField), classInfo(className) }, + #define GPU_CHILD(className, accessorName, numInstances, bConstructEarly, gpuField) \ + { bConstructEarly, numInstances, NV_OFFSETOF(OBJGPU, gpuField), classId(className) }, #include "gpu/gpu_child_list.h" }; @@ -166,27 +162,28 @@ // Describes a child instance (e.g.: classId(OBJCE) instanceID #1) struct GPUCHILDINFO { - NvBool bAlwaysCreate; NvBool bConstructEarly; ENGDESCRIPTOR engDesc; NvU32 gpuChildPtrOffset; - const NVOC_CLASS_INFO *pClassInfo; GPUCHILDTYPE *pChildType; }; static PGPUCHILDTYPE gpuGetChildType(NVOC_CLASS_ID classId); static NV_STATUS gpuGetChildInfo(NVOC_CLASS_ID classId, NvU32 instanceID, PGPUCHILDINFO pChildInfoOut); +static NV_STATUS _gpuChildNvocClassInfoGet(OBJGPU *pGpu, NVOC_CLASS_ID classId, const NVOC_CLASS_INFO **ppClassInfo); static Dynamic **gpuGetChildPtr(OBJGPU *pGpu, NvU32 gpuChildPtrOffset); #define GPU_NUM_CHILD_TYPES \ ((sizeof(gpuChildTypeList) / sizeof(GPUCHILDTYPE))) -static void +void _gpuDetectNvswitchSupport ( OBJGPU *pGpu ) { + NvU32 val = pGpu->fabricProbeRegKeyOverride; + // // Slowdown Threshold 0 leads to driver crash with DIVIDE ERROR // Hence setting it to 1 @@ -220,16 +217,21 @@ } } - if (pGpu->fabricProbeRegKeyOverride) + if (val != 0) { - pGpu->fabricProbeSlowdownThreshold = - NV_MAX(DRF_VAL(_REG_STR, _RM_GPU_FABRIC_PROBE, _SLOWDOWN_THRESHOLD, pGpu->fabricProbeRegKeyOverride), 1); - pGpu->fabricProbeRetryDelay = - DRF_VAL(_REG_STR, _RM_GPU_FABRIC_PROBE, _DELAY, pGpu->fabricProbeRegKeyOverride); + pGpu->fabricProbeSlowdownThreshold = \ + DRF_VAL(_REG_STR, _RM_GPU_FABRIC_PROBE, _SLOWDOWN_THRESHOLD, val); + + pGpu->fabricProbeSlowdownThreshold = \ + NV_MAX(pGpu->fabricProbeSlowdownThreshold , 1); - if (pGpu->fabricProbeRetryDelay) + pGpu->fabricProbeRetryDelay = \ + DRF_VAL(_REG_STR, _RM_GPU_FABRIC_PROBE, _DELAY, val); + + if (pGpu->fabricProbeRetryDelay != 0) { - pGpu->nvswitchSupport = NV2080_CTRL_PMGR_MODULE_INFO_NVSWITCH_SUPPORTED; + pGpu->nvswitchSupport = \ + NV2080_CTRL_PMGR_MODULE_INFO_NVSWITCH_SUPPORTED; } } } @@ -357,6 +359,8 @@ if (rmStatus != NV_OK) return rmStatus; + pGpu->setProperty(pGpu, PDB_PROP_GPU_MOVE_CTX_BUFFERS_TO_PMA, + gpuIsCtxBufAllocInPmaSupported_HAL(pGpu)); // // gpuDetermineVirtualMode inits hPci but only for virtualization case. So if // it does not init it, do here for using it for non-virtualization as well @@ -453,6 +457,19 @@ if (rmStatus != NV_OK) return rmStatus; + if (IS_SIMULATION(pGpu) && !IS_VIRTUAL(pGpu)) + { + // + // gpuDetermineSelfHostedMode must be called after gpuDetermineVirtualMode + // and vgpuCreateObject(for VGPU static info) as the self hosted detection mechanism + // in VF depends on them. But in SCSIM(SIM_BUILD) it is required to be called + // before vgpuCreateObject(from where initRpcInfrastructure_VGPU is called) in PF + // so that the correct setting NV_VGPU_SEND_RING_GP_IN_RING_NO is done + // for the SIM escapes. + // + gpuDetermineSelfHostedMode_HAL(pGpu); + } + gpuGetHwDefaults(pGpu); // Handle per-device core logic registry settings @@ -485,14 +502,11 @@ { pGpu->gpuInstance = gpuInstance; + pGpu->gspRmInitialized = NV_FALSE; // allocate OS-specific GPU extension area osInitOSHwInfo(pGpu); - // Initialize NvFBC session count and list. - - // Initialize NvENC session count and list. - return gpuConstructPhysical(pGpu); } @@ -502,7 +516,8 @@ ( OBJGPU *pGpu, NvU32 chipId0, - NvU32 chipId1 + NvU32 chipId1, + NvU32 socChipId0 ) { OBJSYS *pSys = SYS_GET_INSTANCE(); @@ -518,7 +533,7 @@ // The system object will pass PMC_BOOT_0 and PMC_BOOT_42 to all the HAL's and return the // one that claims it supports this chip arch/implementation // - status = halmgrGetHalForGpu(pHalMgr, pGpu->chipId0, pGpu->chipId1, &pGpu->halImpl); + status = halmgrGetHalForGpu(pHalMgr, socChipId0 ? socChipId0 : pGpu->chipId0, pGpu->chipId1, &pGpu->halImpl); if (status != NV_OK) return status; @@ -603,7 +618,7 @@ callCtx.pControlParams = &rmCtrlParams; callCtx.pLockInfo = rmCtrlParams.pLockInfo; - resservSwapTlsCallContext(&oldCtx, &callCtx); + NV_ASSERT_OK_OR_RETURN(resservSwapTlsCallContext(&oldCtx, &callCtx)); if (pEntry->paramSize == 0) { @@ -614,7 +629,7 @@ status = ((NV_STATUS(*)(void*,void*))pEntry->pFunc)(pGpu->pCachedSubdevice, pParams); } - resservRestoreTlsCallContext(oldCtx); + NV_ASSERT_OK(resservRestoreTlsCallContext(oldCtx)); } else { @@ -634,12 +649,13 @@ NvHandle hParent, NvHandle hObject, NvU32 hClass, - void *pAllocParams + void *pAllocParams, + NvU32 paramsSize ) { // Simple forwarder for now RM_API *pInternalRmApi = rmapiGetInterface(RMAPI_GPU_LOCK_INTERNAL); - return pInternalRmApi->AllocWithHandle(pInternalRmApi, hClient, hParent, hObject, hClass, pAllocParams); + return pInternalRmApi->AllocWithHandle(pInternalRmApi, hClient, hParent, hObject, hClass, pAllocParams, paramsSize); } static NV_STATUS _gpuRmApiFree ( @@ -841,9 +857,9 @@ ENGLIST_ITER it; ENGDESCRIPTOR engDesc; - ct_assert(NV_ARRAY_ELEMENTS32(ppEngDescriptors) == NV_ARRAY_ELEMENTS32(listTypes)); + ct_assert(NV_ARRAY_ELEMENTS(ppEngDescriptors) == NV_ARRAY_ELEMENTS(listTypes)); -#define GPU_CHILD(a, b, numInstances, c, d, e) +numInstances +#define GPU_CHILD(a, b, numInstances, c, d) +numInstances struct ChildList { char children[ 0 + @@ -858,7 +874,7 @@ ct_assert(NV2080_CTRL_GPU_MAX_ENGINE_OBJECTS >= sizeof(((struct ChildList*)(NULL))->children) /* sizeof(ChildList::children) */); - numLists = NV_ARRAY_ELEMENTS32(listTypes); + numLists = NV_ARRAY_ELEMENTS(listTypes); ppEngDescriptors[0] = &pEngineOrder->pEngineInitDescriptors; ppEngDescriptors[1] = &pEngineOrder->pEngineLoadDescriptors; @@ -996,9 +1012,7 @@ NV_ASSERT_OR_RETURN(pChildType && (instanceID < pChildType->instances), NV_ERR_INVALID_OBJECT); pChildInfoOut->engDesc = MKENGDESC(classId, instanceID); - pChildInfoOut->bAlwaysCreate = pChildType->bAlwaysCreate; pChildInfoOut->bConstructEarly = pChildType->bConstructEarly; - pChildInfoOut->pClassInfo = pChildType->pClassInfo; pChildInfoOut->pChildType = pChildType; pChildInfoOut->gpuChildPtrOffset = pChildType->gpuChildPtrOffset + sizeof(void *) * instanceID; @@ -1007,6 +1021,58 @@ } /*! + * @brief For a given @ref OBJGPU, given the @ref NVOC_CLASS_ID for an object + * that is a @ref OBJGPU child, this function will return the + * @ref NVOC_CLASS_INFO for the concrete class type that should be + * instantiated for the field with that @ref NVOC_CLASS_ID + * + * @details This function helps support polymorphism of @ref OBJGPU children. + * The provided @ref NVOC_CLASS_ID is the class ID for the base class + * of the pointer field in @ref OBJGPU (e.g., @ref OBJGPU::pPmu), which + * can be made to point at different sub-classes at runtime. This + * function, given that @ref NVOC_CLASS_ID, provides the information + * about which concrete sub-class should actually be constructed. + * + * @param[in] pGpu + * @param[in] classId + * @ref NVOC_CLASS_ID for the class type of the base class pointer in + * @ref OBJGPU + * @param[out] ppClassInfo + * Pointer to location into which to store pointer to the class info for the + * concrete class to be constructed + * + * @return @ref NV_OK + * Success + * @return @ref NV_ERR_INVALID_STATE + * No match for classId found within this @ref OBJGPU's children + */ +static NV_STATUS +_gpuChildNvocClassInfoGet +( + OBJGPU *pGpu, + NVOC_CLASS_ID classId, + const NVOC_CLASS_INFO **ppClassInfo +) +{ + NvU32 numChildPresent; + const GPUCHILDPRESENT *const pChildrenPresent = + gpuGetChildrenPresent_HAL(pGpu, &numChildPresent); + NvU32 i; + + for (i = 0U; i < numChildPresent; i++) + { + if (classId == pChildrenPresent[i].classId) + { + *ppClassInfo = pChildrenPresent[i].pClassInfo; + return NV_OK; + } + } + + DBG_BREAKPOINT(); + return NV_ERR_INVALID_STATE; +} + +/*! * @brief Looks up for a class in the table based on class id * * All classes are uniquely identified by their classId. @@ -1020,7 +1086,7 @@ for (i = 0; i < GPU_NUM_CHILD_TYPES; i++) { - if (gpuChildTypeList[i].pClassInfo && gpuChildTypeList[i].pClassInfo->classId == classId) + if (gpuChildTypeList[i].classId == classId) { return &gpuChildTypeList[i]; } @@ -1062,9 +1128,9 @@ pChildType = &gpuChildTypeList[pIt->childTypeIdx]; // Advance instance # - if (pIt->childInst < pChildType->instances && pChildType->pClassInfo) + if (pIt->childInst < pChildType->instances) { - NV_STATUS status = gpuGetChildInfo(pChildType->pClassInfo->classId, pIt->childInst, &childInfo); + NV_STATUS status = gpuGetChildInfo(pChildType->classId, pIt->childInst, &childInfo); NV_ASSERT(status == NV_OK); @@ -1223,11 +1289,13 @@ NvU32 instanceID ) { - NV_STATUS status; - OBJENGSTATE *pEngstate; - GPUCHILDINFO childInfo; - Dynamic **ppChildPtr; - ENGSTATE_TRANSITION_DATA engTransitionData; + NV_STATUS status; + OBJENGSTATE *pEngstate; + GPUCHILDINFO childInfo; + Dynamic **ppChildPtr; + const NVOC_CLASS_INFO *pClassInfo; + Dynamic *pConcreteChild = NULL; + ENGSTATE_TRANSITION_DATA engTransitionData; status = gpuGetChildInfo(classId, instanceID, &childInfo); @@ -1235,14 +1303,27 @@ ppChildPtr = gpuGetChildPtr(pGpu, childInfo.gpuChildPtrOffset); + NV_ASSERT_OK_OR_RETURN( + _gpuChildNvocClassInfoGet(pGpu, classId, &pClassInfo)); + // Ask the object database utility to create a child object. - status = objCreateDynamic(ppChildPtr, pGpu, childInfo.pClassInfo); + status = objCreateDynamic(&pConcreteChild, pGpu, pClassInfo); if (status != NV_OK) { return status; } - NV_ASSERT_OR_RETURN(*ppChildPtr, NV_ERR_INVALID_STATE); + NV_ASSERT_OR_RETURN(pConcreteChild != NULL, NV_ERR_INVALID_STATE); + + // + // Cast back to a pointer to the base class and assign it into the pointer + // in OBJGPU + // + *ppChildPtr = objDynamicCastById(pConcreteChild, classId); + NV_ASSERT_TRUE_OR_GOTO(status, + (*ppChildPtr != NULL), + NV_ERR_INVALID_STATE, + gpuCreateObject_exit); pEngstate = dynamicCast(*ppChildPtr, OBJENGSTATE); @@ -1268,7 +1349,7 @@ gpuCreateObject_exit: if (status != NV_OK) { - objDelete(*ppChildPtr); + objDelete(pConcreteChild); *ppChildPtr = NULL; } @@ -1324,21 +1405,31 @@ } } + // Free GPU shared data + memdescUnmap(pGpu->userSharedData.pMemDesc, NV_TRUE, 0, + pGpu->userSharedData.pMapBuffer, pGpu->userSharedData.pMapBufferPriv); + memdescFree(pGpu->userSharedData.pMemDesc); + memdescDestroy(pGpu->userSharedData.pMemDesc); + + // + // If device instance is unassigned, we haven't initialized far enough to + // do any accounting with it + // + if (gpuGetDeviceInstance(pGpu) != NV_MAX_DEVICES) + { + rmapiReportLeakedDevices(gpuGetGpuMask(pGpu)); + } + // Free children in reverse order from construction for (typeNum = GPU_NUM_CHILD_TYPES - 1; typeNum >= 0; typeNum--) { pChildTypeCur = &gpuChildTypeList[typeNum]; - if (!pChildTypeCur->pClassInfo) - { - continue; - } - for (instNum = pChildTypeCur->instances - 1; instNum >= 0; instNum--) { NV_STATUS status; - status = gpuGetChildInfo(pChildTypeCur->pClassInfo->classId, instNum, &childInfoCur); + status = gpuGetChildInfo(pChildTypeCur->classId, instNum, &childInfoCur); NV_ASSERT(status == NV_OK); @@ -1349,15 +1440,6 @@ } } - // - // If device instance is unassigned, we haven't initialized far enough to - // do any accounting with it - // - if (gpuGetDeviceInstance(pGpu) != NV_MAX_DEVICES) - { - rmapiReportLeakedDevices(gpuGetGpuMask(pGpu)); - } - _gpuFreeEngineOrderList(pGpu); portMemFree(pGpu->pUserRegisterAccessMap); @@ -1416,37 +1498,27 @@ NvBool bConstructEarly ) { - PENGDESCRIPTOR pEngDescriptors; - NvU32 numEngDescriptors; PGPUCHILDTYPE pChildTypeCur; GPUCHILDINFO childInfoCur; NvU32 t, i; NV_STATUS rmStatus = NV_OK; - pEngDescriptors = gpuGetInitEngineDescriptors(pGpu); - numEngDescriptors = gpuGetNumEngDescriptors(pGpu); for (t = 0; t < GPU_NUM_CHILD_TYPES; t++) { pChildTypeCur = &gpuChildTypeList[t]; - if (!pChildTypeCur->pClassInfo) - { - continue; - } - for (i = 0; i < pChildTypeCur->instances; i++) { - NVOC_CLASS_ID classId = pChildTypeCur->pClassInfo->classId; + NVOC_CLASS_ID classId = pChildTypeCur->classId; rmStatus = gpuGetChildInfo(classId, i, &childInfoCur); NV_ASSERT(rmStatus == NV_OK); if ((bConstructEarly == childInfoCur.bConstructEarly) && - gpuShouldCreateObject(&childInfoCur, - pEngDescriptors, - numEngDescriptors)) + gpuShouldCreateObject(pGpu, + &childInfoCur)) { rmStatus = gpuCreateObject(pGpu, classId, i); @@ -1476,29 +1548,25 @@ static NvBool gpuShouldCreateObject ( - PGPUCHILDINFO pChildInfo, - PENGDESCRIPTOR pEngDescriptors, - NvU32 numEngDescriptors + OBJGPU *pGpu, + GPUCHILDINFO *pChildInfo ) { NvBool retVal = NV_FALSE; - NvU32 curEngDescIdx; + NvU32 numChildPresent; + const GPUCHILDPRESENT *const pChildPresentList = + gpuGetChildrenPresent_HAL(pGpu, &numChildPresent); + NvU32 childIdx; - if (pChildInfo->bAlwaysCreate) - { - // For now all SW engines get created - retVal = NV_TRUE; - } - else + // Let the HAL confirm that we should create an object for this engine. + for (childIdx = 0; childIdx < numChildPresent; childIdx++) { - // Let the HAL confirm that we should create an object for this engine. - for (curEngDescIdx = 0; curEngDescIdx < numEngDescriptors; curEngDescIdx++) + if ((ENGDESC_FIELD(pChildInfo->engDesc, _CLASS) == + pChildPresentList[childIdx].classId)) { - if (pChildInfo->engDesc == pEngDescriptors[curEngDescIdx]) - { - retVal = NV_TRUE; - break; - } + retVal = (ENGDESC_FIELD(pChildInfo->engDesc, _INST) < + pChildPresentList[childIdx].instances); + break; } } @@ -1569,7 +1637,7 @@ return NV_OK; } -/* +/*! * The engine removal protocol is as follows: * - engines returning an error code from ConstructEngine will be immediately * removed (this happens in gpuCreateObject) @@ -1581,6 +1649,11 @@ * gpuRemoveMissingEngines takes place before the main loop in gpuStatePreInit * and is responsible for removing engines satisfying the last two bullets * above. + * + * Additionally, note that this function handles engines that were never + * present according to gpuChildrenPresent_HAL; these engines' associated + * classes must be removed from the class DB, and that is handled via this + * function. */ static NV_STATUS gpuRemoveMissingEngines @@ -1592,6 +1665,7 @@ PENGDESCRIPTOR engDescriptorList = gpuGetInitEngineDescriptors(pGpu); NvU32 numEngDescriptors = gpuGetNumEngDescriptors(pGpu); NV_STATUS rmStatus = NV_OK; + NvU32 curClassDescIdx; // Order is determined by gpuGetChildrenOrder_HAL pulling gpuChildOrderList array for (curEngDescIdx = 0; curEngDescIdx < numEngDescriptors; curEngDescIdx++) @@ -1632,6 +1706,61 @@ NV_ASSERT(rmStatus == NV_OK || !"Error while trying to remove missing engine"); } + // + // Check the rest of the class descriptors for engines that are not part of + // the present list, and therefore not part of the init list, and ensure + // that those get removed from the class DB. + // + for (curClassDescIdx = 0U; + curClassDescIdx < pGpu->engineOrder.numClassDescriptors; + curClassDescIdx++) + { + const GPU_RESOURCE_DESC *const pCurDesc = + &pGpu->engineOrder.pClassDescriptors[curClassDescIdx]; + NvBool bGspSupportsEngine; + + // + // Skip any classes which: + // 1.) Do not have an engine class ID + // 2.) Have an engine of GPU. ENG_GPU does not correspond to an + // OBJENGSTATE, and it can never be missing. + // 3.) Have an OBJENGSTATE that is present + // + if ((ENGDESC_FIELD(pCurDesc->engDesc, _CLASS) == classId(OBJINVALID)) || + (pCurDesc->engDesc == ENG_GPU) || + gpuGetEngstate(pGpu, pCurDesc->engDesc) != NULL) + { + continue; + } + + // + // If the engstate is NULL, the engine may still be supported on GSP. If + // it is, we can skip removing it. + // + // Note that if the function returns NV_WARN_NOTHING_TO_DO, this means + // GSP-RM is not running and thus the engine cannot be supported within + // GSP. + // + rmStatus = gspSupportsEngine(pGpu, pCurDesc->engDesc, &bGspSupportsEngine); + if (rmStatus == NV_WARN_NOTHING_TO_DO) + { + rmStatus = NV_OK; + bGspSupportsEngine = NV_FALSE; + } + NV_ASSERT_OK_OR_RETURN(rmStatus); + if (bGspSupportsEngine) + { + continue; + } + + NV_ASSERT_OK_OR_RETURN( + gpuDeleteClassFromClassDBByEngTag(pGpu, pCurDesc->engDesc)); + } + + // Update the engine table after deleting any classes from the class DB + NV_ASSERT_OK_OR_RETURN( + gpuUpdateEngineTable(pGpu)); + return rmStatus; } @@ -1910,6 +2039,18 @@ // Set PDB properties as per data from GSP. gpuInitProperties(pGpu); + // + // gpuDetermineSelfHostedMode must be called after gpuDetermineVirtualMode/kgspInitRm + // where VGPU/GSP static info is populated as the self hosted detection mechanism + // in VF and Kernel-RM depends on them respectively. + // + // For Kernel-RM, gpuDetermineSelfHostedMode_HAL should be called in + // gpuStatePreInit because GSP static config gets populated only by + // PreInit and also all the gpuIsSelfHosted callers are from PreInit and + // onwards. + // + gpuDetermineSelfHostedMode_HAL(pGpu); + LOCK_ASSERT_AND_RETURN(rmGpuLockIsOwner()); NV_ASSERT_OK_OR_RETURN(_gpuAllocateInternalObjects(pGpu)); @@ -1917,6 +2058,12 @@ NV_ASSERT_OK_OR_RETURN(gpuConstructUserRegisterAccessMap(pGpu)); NV_ASSERT_OK_OR_RETURN(gpuBuildGenericKernelFalconList(pGpu)); + // + // Must be called after _gpuInitChipInfo since gpuDetermineMIGSupport_HAL + // reads chip revision and that is available only after _gpuInitChipInfo. + // + gpuDetermineMIGSupport_HAL(pGpu); + rmStatus = gpuRemoveMissingEngines(pGpu); NV_ASSERT(rmStatus == NV_OK); @@ -2278,11 +2425,30 @@ if (rmStatus != NV_OK) goto gpuStateLoad_exit; + if (pGpu->getProperty(pGpu, PDB_PROP_GPU_IN_PM_RESUME_CODEPATH) && + pGpu->bRecheckSliSupportAtResume) + { + NvU32 gpuAttachCnt, gpuAttachMask; + NvU32 gpuInstance = 0; + OBJGPU *gpuLoop; + NvU32 numPoweredOn = 1; // Include the current pGpu + gpumgrGetGpuAttachInfo(&gpuAttachCnt, &gpuAttachMask); + + while ((gpuLoop = gpumgrGetNextGpu(gpuAttachMask, &gpuInstance))) + { + if (gpuIsGpuFullPower(gpuLoop)) + numPoweredOn++; + } + if (numPoweredOn == gpuAttachCnt) + { + RmInitScalability(pGpu); + } + } } { NvBool bVgpuOnGspEnabled = IS_VGPU_GSP_PLUGIN_OFFLOAD_ENABLED(pGpu) && RMCFG_FEATURE_PLATFORM_GSP; - if ((hypervisorIsVgxHyper() || bVgpuOnGspEnabled) && + if ((hypervisorIsVgxHyper() || bVgpuOnGspEnabled) && !pGpu->getProperty(pGpu, PDB_PROP_GPU_ACCOUNTING_ON)) { OBJSYS *pSys = SYS_GET_INSTANCE(); @@ -2332,7 +2498,7 @@ NvU32 gpuCount; NvU32 gpuIndex; - NV_CHECK_OK_OR_RETURN(LEVEL_ERROR, + NV_CHECK_OK_OR_RETURN(LEVEL_ERROR, gpumgrGetGpuAttachInfo(&gpuCount, &attachMask)); gpuIndex = 0; while ((pPeerGpu = gpumgrGetNextGpu(attachMask, &gpuIndex)) != NULL) @@ -2379,18 +2545,18 @@ NV_ERR_NO_MEMORY); peerGpuIds = portMemAllocNonPaged(sizeof(*peerGpuIds) * - NV_ARRAY_ELEMENTS32(pSetP2PCapsParams->peerGpuInfos)); + NV_ARRAY_ELEMENTS(pSetP2PCapsParams->peerGpuInfos)); NV_CHECK_OR_ELSE(LEVEL_ERROR, peerGpuIds != NULL, status = NV_ERR_NO_MEMORY; goto exit); peerGpuInstances = portMemAllocNonPaged(sizeof(*peerGpuInstances) * - NV_ARRAY_ELEMENTS32(pSetP2PCapsParams->peerGpuInfos)); + NV_ARRAY_ELEMENTS(pSetP2PCapsParams->peerGpuInfos)); NV_CHECK_OR_ELSE(LEVEL_ERROR, peerGpuInstances != NULL, status = NV_ERR_NO_MEMORY; goto exit); - NV_CHECK_OK_OR_GOTO(status, LEVEL_ERROR, + NV_CHECK_OK_OR_GOTO(status, LEVEL_ERROR, gpumgrGetGpuAttachInfo(&gpuCount, &attachMask), exit); @@ -2488,7 +2654,7 @@ NV2080_CTRL_CMD_INTERNAL_REMOVE_P2P_CAPS, &removeP2PCapsParams, sizeof(removeP2PCapsParams))); } - + exit: portMemFree(pSetP2PCapsParams); pSetP2PCapsParams = NULL; @@ -2551,6 +2717,16 @@ NvU32 numEngDescriptors; NvU32 curEngDescIdx; NV_STATUS rmStatus = NV_OK; +#if RMCFG_FEATURE_SLINEXT && defined(DEBUG) + NvU32 numPoweredOn = 0; + + SLI_LOOP_START(SLI_LOOP_FLAGS_IGNORE_REENTRANCY) + numPoweredOn++; + SLI_LOOP_END + + // Ensure all GPUs are available + NV_ASSERT(gpumgrGetSubDeviceCountFromGpu(pGpu) == numPoweredOn); +#endif engDescriptorList = gpuGetLoadEngineDescriptors(pGpu); numEngDescriptors = gpuGetNumEngDescriptors(pGpu); @@ -2592,6 +2768,9 @@ goto gpuStatePostLoad_exit; } + // Caching GID data, the GID is generated by PMU and passed to RM during PMU INIT message. + //NV_ASSERT_OK(gpuGetGidInfo(pGpu, NULL, NULL, DRF_DEF(2080_GPU_CMD, _GPU_GET_GID_FLAGS, _TYPE, _SHA1))); + NV_CHECK_OK_OR_GOTO(rmStatus, LEVEL_ERROR, _gpuSetVgpuMgrConfig(pGpu), @@ -2629,7 +2808,7 @@ pGpu->boardInfo = NULL; } } - NV_ASSERT_OR_GOTO(gpuFabricProbeStart(pGpu, &pGpu->pGpuFabricProbeInfo) == NV_OK, + NV_ASSERT_OR_GOTO(gpuFabricProbeStart(pGpu, &pGpu->pGpuFabricProbeInfoKernel) == NV_OK, gpuStatePostLoad_exit); gpuStatePostLoad_exit: @@ -2669,7 +2848,7 @@ rmapiControlCacheFreeAllCacheForGpu(pGpu->gpuInstance); - gpuFabricProbeStop(pGpu->pGpuFabricProbeInfo); + gpuFabricProbeStop(pGpu->pGpuFabricProbeInfoKernel); portMemFree(pGpu->boardInfo); pGpu->boardInfo = NULL; @@ -3057,12 +3236,16 @@ NV_STATUS gpuInitOptimusSettings_IMPL(OBJGPU *pGpu) { - OBJOS *pOS = GPU_GET_OS(pGpu); NV_STATUS status; NvU32 inOut; NvU32 data32; NvU16 rtnSize; + if (!pGpu->getProperty(pGpu, PDB_PROP_GPU_IS_MOBILE)) + { + return NV_OK; + } + // Check regkey settings if (osReadRegistryDword(pGpu, NV_REG_STR_RM_D3_FEATURE, &data32) == NV_OK) @@ -3114,15 +3297,15 @@ // It doesn't matter if this was not successful as we will enable the driver side // save restore anyway. This call is to save some work for the SBIOS if possible. // - status = pOS->osCallACPI_DSM(pGpu, - ACPI_DSM_FUNCTION_NVOP, - NVOP_FUNC_OPTIMUSCAPS, - &inOut, - &rtnSize); + status = osCallACPI_DSM(pGpu, + ACPI_DSM_FUNCTION_NVOP, + NVOP_FUNC_OPTIMUSCAPS, + &inOut, + &rtnSize); if (status != NV_OK) { - NV_PRINTF(LEVEL_ERROR, + NV_PRINTF(LEVEL_NOTICE, "SBIOS did not acknowledge cfg space owner change\n"); } @@ -3141,11 +3324,15 @@ NV_STATUS gpuDeinitOptimusSettings_IMPL(OBJGPU *pGpu) { - OBJOS *pOS = GPU_GET_OS(pGpu); NV_STATUS status; NvU32 inOut; NvU16 rtnSize; + if (!pGpu->getProperty(pGpu, PDB_PROP_GPU_IS_MOBILE)) + { + return NV_OK; + } + if (pGpu->getProperty(pGpu, PDB_PROP_GPU_OPTIMUS_GOLD_CFG_SPACE_RESTORE)) { rtnSize = (NvU16)sizeof(inOut); @@ -3153,11 +3340,11 @@ inOut = FLD_SET_DRF(OP_FUNC, _OPTIMUSCAPS, _CFG_SPACE_OWNER_WR_EN, _TRUE, inOut); inOut = FLD_SET_DRF(OP_FUNC, _OPTIMUSCAPS, _CFG_SPACE_OWNER_TARGET, _SBIOS, inOut); - status = pOS->osCallACPI_DSM(pGpu, - ACPI_DSM_FUNCTION_NVOP, - NVOP_FUNC_OPTIMUSCAPS, - &inOut, - &rtnSize); + status = osCallACPI_DSM(pGpu, + ACPI_DSM_FUNCTION_NVOP, + NVOP_FUNC_OPTIMUSCAPS, + &inOut, + &rtnSize); // NV_ASSERT_OR_RETURN(status == NV_OK, status); // NV_ASSERT_OR_RETURN(FLD_TEST_DRF(OP_FUNC, _OPTIMUSCAPS, _CFG_SPACE_OWNER_ACTUAL, // _SBIOS, inOut), @@ -3587,7 +3774,7 @@ // // default Logic: If halImpl is equal or greater than requested --> NV_TRUE // -// Arch and impl IDs are not guaranteed to be ordered. +// Arch and impl IDs are not guaranteed to be ordered. // "halImpl" is used here to match the ordering in chip-config/NVOC // // NOTE: only defined for gpus within same gpu series @@ -4023,6 +4210,7 @@ pGpu->setProperty(pGpu, PDB_PROP_GPU_IN_STANDBY, NV_FALSE); pGpu->bInD3Cold = NV_FALSE; pGpu->setProperty(pGpu, PDB_PROP_GPU_IN_HIBERNATE, NV_FALSE); + SET_GPU_GC6_STATE(pGpu, GPU_GC6_STATE_POWERED_ON); } @@ -4490,17 +4678,6 @@ return NV_FALSE; } -/** - * Set SLI broadcast state in threadstate if SLI is enabled for the GPU - */ -void -gpuSetThreadBcState_IMPL(OBJGPU *pGpu, NvBool bcState) -{ - { - gpumgrSetBcEnabledStatus(pGpu, bcState); - } -} - NV_STATUS gpuInitDispIpHal_IMPL @@ -4567,10 +4744,73 @@ __nvoc_init_funcTable_DisplayInstanceMemory(KERNEL_DISPLAY_GET_INST_MEM(pKernelDisplay), pRmHalspecOwner); + void __nvoc_init_funcTable_KernelHead(KernelHead *, RmHalspecOwner *); + NvU32 headIdx; + + for (headIdx = 0; headIdx < OBJ_MAX_HEADS; headIdx++) + { + __nvoc_init_funcTable_KernelHead(KDISP_GET_HEAD(pKernelDisplay, headIdx), + pRmHalspecOwner); + } + return NV_OK; } /*! + *@brief Check if CC feature is enabled + */ +NvBool +gpuIsCCFeatureEnabled_IMPL(OBJGPU *pGpu) +{ + ConfidentialCompute *pCC = GPU_GET_CONF_COMPUTE(pGpu); + + if (pCC != NULL) + { + return pCC->getProperty(pCC, PDB_PROP_CONFCOMPUTE_CC_FEATURE_ENABLED); + } + return NV_FALSE; +} + +/*! + *@brief Check if APM feature is enabled + */ +NvBool +gpuIsApmFeatureEnabled_IMPL(OBJGPU *pGpu) +{ + ConfidentialCompute *pCC = GPU_GET_CONF_COMPUTE(pGpu); + + if (pCC != NULL) + { + return pCC->getProperty(pCC, PDB_PROP_CONFCOMPUTE_APM_FEATURE_ENABLED); + } + return NV_FALSE; +} + +/*! + *@brief Check if either CC or APM feature is enabled + */ +NvBool +gpuIsCCorApmFeatureEnabled_IMPL(OBJGPU *pGpu) +{ + return gpuIsCCFeatureEnabled(pGpu) || gpuIsApmFeatureEnabled(pGpu); +} + +/*! + *@brief Check if CC devtools mode is enabled + */ +NvBool +gpuIsCCDevToolsModeEnabled_IMPL(OBJGPU *pGpu) +{ + ConfidentialCompute *pCC = GPU_GET_CONF_COMPUTE(pGpu); + + if ((pCC != NULL) && gpuIsCCFeatureEnabled(pGpu)) + { + return pCC->getProperty(pCC, PDB_PROP_CONFCOMPUTE_DEVTOOLS_MODE_ENABLED); + } + return NV_FALSE; +} + +/*! * @brief: Initialize chip related info * This function fills up the chip info structure of OBJGPU. * @@ -4702,6 +4942,8 @@ NvU8 function = 0; NvBool bIsCCFeatureEnabled = NV_FALSE; + bIsCCFeatureEnabled = gpuIsCCFeatureEnabled(pGpu); + if (IS_PASSTHRU(pGpu) && !bIsCCFeatureEnabled) { gpuReadVgpuConfigReg_HAL(pGpu, index, pData); @@ -4778,3 +5020,100 @@ intrServiceStallListAllGpusCond(pGpu, pIntr, &engines, NV_TRUE); } } + + +NV_STATUS +gpuGetDeviceEntryByType_IMPL +( + OBJGPU *pGpu, + NvU32 deviceTypeEnum, + NvS32 groupId, + NvU32 instanceId, + const DEVICE_INFO2_ENTRY **ppDeviceEntry +) +{ + NvU32 i; + NV_ASSERT_OR_RETURN(ppDeviceEntry != NULL, NV_ERR_INVALID_ARGUMENT); + NV_ASSERT_OR_RETURN(groupId == DEVICE_INFO2_ENTRY_GROUP_ID_ANY || + groupId >= 0, + NV_ERR_INVALID_ARGUMENT); + NV_ASSERT_OK_OR_RETURN(gpuConstructDeviceInfoTable_HAL(pGpu)); + + *ppDeviceEntry = NULL; + + for (i = 0; i < pGpu->numDeviceInfoEntries; ++i) + { + const DEVICE_INFO2_ENTRY *pEntry = &pGpu->pDeviceInfoTable[i]; + if (pEntry->typeEnum == deviceTypeEnum && + (groupId == DEVICE_INFO2_ENTRY_GROUP_ID_ANY || + pEntry->groupId == (NvU32)groupId) && + pEntry->instanceId == instanceId) + { + *ppDeviceEntry = pEntry; + return NV_OK; + } + } + return NV_ERR_OBJECT_NOT_FOUND; +} + +/*! + * @brief Sets the GC6/JT SBIOS capability + * + * The capabilities are retrieved from the SBIOS through JT_FUNC_CAPS subfunction + * + * @param[in] pGpu GPU object pointer + * + * @return status bubble up the return status from osCallACPI_DSM + */ +NV_STATUS +gpuSetGC6SBIOSCapabilities_IMPL(OBJGPU *pGpu) +{ + NV_STATUS status; + + pGpu->acpiMethodData.jtMethodData.bSBIOSCaps = NV_FALSE; + + if ((!pGpu->acpiMethodData.bValid) || + (pGpu->acpiMethodData.jtMethodData.status != NV_OK)) + { + RMTRACE_SBIOS (_ACPI_DSM_ERROR, pGpu->gpuId, ACPI_DSM_FUNCTION_JT, JT_FUNC_CAPS, 0, 0, 0, 0, 0); + return NV_ERR_NOT_SUPPORTED; + } + + status = gpuJtVersionSanityCheck_HAL(pGpu); + if (status != NV_OK) + { + NV_PRINTF(LEVEL_ERROR, + "Unsupported JT revision ID. GC6 is being disabled.\n"); + RMTRACE_SBIOS (_ACPI_DSM_ERROR, pGpu->gpuId, ACPI_DSM_FUNCTION_JT, JT_FUNC_CAPS, 0, 0, 0, 0, 0); + return status; + } + + if (FLD_TEST_DRF(_JT_FUNC, _CAPS, _JT_ENABLED, _TRUE, pGpu->acpiMethodData.jtMethodData.jtCaps)) + { + pGpu->acpiMethodData.jtMethodData.bSBIOSCaps = NV_TRUE; + + switch (pGpu->acpiMethodData.jtMethodData.jtRevId) + { + case NV_JT_FUNC_CAPS_REVISION_ID_1_03: + // GC6 2.0 production + break; + case NV_JT_FUNC_CAPS_REVISION_ID_2_00: + // GC6 3.0 and FGC6 production + break; + default: + NV_PRINTF(LEVEL_ERROR, + "Unsupported JT revision ID. GC6 is being disabled. Update the " + "board EC PIC FW. On Windows, update the SBIOS GC6 AML as well.\n"); + DBG_BREAKPOINT(); + pGpu->acpiMethodData.jtMethodData.bSBIOSCaps = NV_FALSE; + break; + } + + } + + RMTRACE_GPU(_GC6_SBIOS_CAP, pGpu->gpuId, pGpu->acpiMethodData.jtMethodData.jtCaps, pGpu->acpiMethodData.jtMethodData.jtRevId, pGpu->acpiMethodData.jtMethodData.bSBIOSCaps, 0, 0, 0, 0); + RMTRACE_SBIOS (_ACPI_DSM_METHOD, pGpu->gpuId, ACPI_DSM_FUNCTION_JT, JT_FUNC_CAPS, pGpu->acpiMethodData.jtMethodData.jtCaps, 0, 0, 0, 0); + + return NV_OK; +} + diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/kernel/gpu/gpu_access.c nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/kernel/gpu/gpu_access.c --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/kernel/gpu/gpu_access.c 2023-10-25 20:21:02.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/kernel/gpu/gpu_access.c 2024-03-05 22:13:26.000000000 +0000 @@ -37,25 +37,15 @@ BAD_READ_UNKNOWN, } RMCD_BAD_READ_REASON; -static NV_STATUS _allocGpuIODevice(GPU_IO_DEVICE **ppIODevice); static void _gpuCleanRegisterFilterList(DEVICE_REGFILTER_INFO *); static NvU32 _gpuHandleReadRegisterFilter(OBJGPU *, DEVICE_INDEX devIndex, NvU32 devInstance, NvU32 addr, NvU32 accessSize, NvU32 *pFlags, THREAD_STATE_NODE *pThreadState); static void _gpuHandleWriteRegisterFilter(OBJGPU *, DEVICE_INDEX devIndex, NvU32 devInstance, NvU32 addr, NvU32 val, NvU32 accessSize, NvU32 *pFlags, THREAD_STATE_NODE *pThreadState); -static void _gpuApertureWriteRegUnicast(OBJGPU *, IO_APERTURE *pAperture, NvU32 addr, NvV32 val, NvU32 size); -static NvU32 _gpuApertureReadReg(IO_APERTURE *pAperture, NvU32 addr, NvU32 size); - -static NvU8 _gpuApertureReadReg008(IO_APERTURE *a, NvU32 addr); -static NvU16 _gpuApertureReadReg016(IO_APERTURE *a, NvU32 addr); -static NvU32 _gpuApertureReadReg032(IO_APERTURE *a, NvU32 addr); -static void _gpuApertureWriteReg008(IO_APERTURE *a, NvU32 addr, NvV8 value); -static void _gpuApertureWriteReg016(IO_APERTURE *a, NvU32 addr, NvV16 value); -static void _gpuApertureWriteReg032(IO_APERTURE *a, NvU32 addr, NvV32 value); -static void _gpuApertureWriteReg032Unicast(IO_APERTURE *a, NvU32 addr, NvV32 value); -static NvBool _gpuApertureValidReg(IO_APERTURE *a, NvU32 addr); +static void ioaprtWriteRegUnicast(OBJGPU *, IoAperture *pAperture, NvU32 addr, NvV32 val, NvU32 size); +static NvU32 ioaprtReadReg(IoAperture *pAperture, NvU32 addr, NvU32 size); static REGISTER_FILTER * _findGpuRegisterFilter(DEVICE_INDEX devIndex, NvU32 devInstance, NvU32 addr, REGISTER_FILTER *); -static NV_STATUS _gpuInitIODeviceAndAperture(OBJGPU *, NvU32, NvU32, RmPhysAddr, NvU32); +static NV_STATUS _gpuInitIOAperture(OBJGPU *pGpu, NvU32 deviceIndex, DEVICE_MAPPING *pMapping); NV_STATUS regAccessConstruct @@ -89,10 +79,7 @@ DEVICE_MAPPING *pMapping = gpuGetDeviceMapping(pGpu, deviceIndex, 0); if (pMapping != NULL) { - rmStatus = _gpuInitIODeviceAndAperture(pGpu, deviceIndex, - pMapping->gpuDeviceEnum, - pMapping->gpuNvPAddr, - pMapping->gpuNvLength); + rmStatus = _gpuInitIOAperture(pGpu, deviceIndex, pMapping); if (rmStatus != NV_OK) { NV_PRINTF(LEVEL_ERROR, @@ -114,7 +101,7 @@ OBJGPU *pGpu = pRegisterAccess->pGpu; DEVICE_INDEX deviceIndex; NvU32 mappingNum; - IO_APERTURE *pIOAperture; + IoAperture *pIOAperture; REGISTER_FILTER *pNode; // Ignore attempt to destruct a not-fully-constructed RegisterAccess @@ -128,8 +115,7 @@ pIOAperture = pGpu->pIOApertures[deviceIndex]; if (pIOAperture != NULL) { - portMemFree(pIOAperture->pDevice); - ioaccessDestroyIOAperture(pIOAperture); + objDelete(pIOAperture); } } @@ -153,36 +139,6 @@ } } -/*! - * @brief Allocates GPU_IO_DEVICE object - * - * @param[in] ppIODevice Pointer to uninitialized GPU_IO_DEVICE - */ -static NV_STATUS -_allocGpuIODevice -( - GPU_IO_DEVICE **ppIODevice -) -{ - GPU_IO_DEVICE *pDevice; - - pDevice = portMemAllocNonPaged(sizeof(GPU_IO_DEVICE)); - if (pDevice == NULL) - { - NV_PRINTF(LEVEL_ERROR, - "memory allocation failed for GPU IO Device\n"); - DBG_BREAKPOINT(); - return NV_ERR_NO_MEMORY; - } - - portMemSet(pDevice, 0, sizeof(GPU_IO_DEVICE)); - - *ppIODevice = pDevice; - - return NV_OK; -} - - // // The following register I/O functions are organized into two groups; // a multi-chip unaware group and a multi-chip aware group. @@ -254,145 +210,195 @@ } } +/*! + * @brief: Initialize an IoAperture instance in-place. + * + * @param[out] pAperture pointer to the IoAperture. + * @param[in] pParentAperture pointer to the parent of the new IoAperture. + * @param[in] offset offset from the parent APERTURE's baseAddress. + * @param[in] length length of the APERTURE. + * + * @return NV_OK upon success + * NV_ERR* otherwise. + */ +NV_STATUS +ioaprtInit +( + IoAperture *pAperture, + IoAperture *pParentAperture, + NvU32 offset, + NvU32 length +) +{ + return objCreateWithFlags(&pAperture, NVOC_NULL_OBJECT, IoAperture, NVOC_OBJ_CREATE_FLAGS_IN_PLACE_CONSTRUCT, pParentAperture, NULL, 0, 0, NULL, 0, offset, length); +} + +/*! + * Initialize an IoAperture instance. + * + * @param[in,out] pAperture pointer to IoAperture instance to be initialized. + * @param[in] pParentAperture pointer to parent of the new IoAperture. + * @param[in] deviceIndex device index + * @param[in] deviceInstance device instance + * @param[in] pMapping device register mapping + * @param[in] mappingStartAddr register address corresponding to the start of the mapping + * @param[in] offset offset from the parent APERTURE's baseAddress. + * @param[in] length length of the APERTURE. + * + * @return NV_OK when inputs are valid. + */ +NV_STATUS +ioaprtConstruct_IMPL +( + IoAperture *pAperture, + IoAperture *pParentAperture, + OBJGPU *pGpu, + NvU32 deviceIndex, + NvU32 deviceInstance, + DEVICE_MAPPING *pMapping, + NvU32 mappingStartAddr, + NvU32 offset, + NvU32 length +) +{ + if (pParentAperture != NULL) + { + NV_ASSERT_OR_RETURN(pMapping == NULL, NV_ERR_INVALID_ARGUMENT); + NV_ASSERT_OR_RETURN(pGpu == NULL || pGpu == pParentAperture->pGpu, NV_ERR_INVALID_ARGUMENT); + + pAperture->pGpu = pParentAperture->pGpu; + pAperture->deviceIndex = pParentAperture->deviceIndex; + pAperture->deviceInstance = pParentAperture->deviceInstance; + pAperture->pMapping = pParentAperture->pMapping; + pAperture->baseAddress = pParentAperture->baseAddress; + pAperture->mappingStartAddr = pParentAperture->mappingStartAddr; + + // Check if the child Aperture strides beyond the parent's boundary. + if ((length + offset) > pParentAperture->length) + { + NV_PRINTF(LEVEL_WARNING, + "Child aperture crosses parent's boundary, length %u offset %u, Parent's length %u\n", + length, offset, pParentAperture->length); + } + + } + else + { + NV_ASSERT_OR_RETURN(pMapping != NULL, NV_ERR_INVALID_ARGUMENT); + NV_ASSERT_OR_RETURN(pGpu != NULL, NV_ERR_INVALID_ARGUMENT); + + pAperture->pGpu = pGpu; + pAperture->deviceIndex = deviceIndex; + pAperture->deviceInstance = deviceInstance; + pAperture->pMapping = pMapping; + pAperture->baseAddress = 0; + pAperture->mappingStartAddr = mappingStartAddr; + } + + pAperture->baseAddress += offset; + pAperture->length = length; + + return NV_OK; +} + static void -_gpuApertureWriteRegUnicast +ioaprtWriteRegUnicast ( OBJGPU *pGpu, - IO_APERTURE *pAperture, + IoAperture *pAperture, NvU32 addr, NvV32 val, NvU32 size ) { - NV_ASSERT_OR_RETURN_VOID(pAperture); - NV_ASSERT_OR_RETURN_VOID(pAperture->pDevice); - - GPU_IO_DEVICE *pDevice = (GPU_IO_DEVICE*) pAperture->pDevice; - NvU32 deviceIndex = pDevice->deviceIndex; - NvU32 instance = pDevice->instance; + NvU32 deviceIndex = pAperture->deviceIndex; + NvU32 instance = pAperture->deviceInstance; NvU32 regAddr = pAperture->baseAddress + addr; + NvU32 mappingRegAddr = regAddr - pAperture->mappingStartAddr; + DEVICE_MAPPING *pMapping = pAperture->pMapping; NvU32 flags = 0; NV_STATUS status; THREAD_STATE_NODE *pThreadState; - DEVICE_MAPPING *pMapping; - - pMapping = gpuGetDeviceMapping(pGpu, deviceIndex, instance); - if (pMapping == NULL) + if (!pGpu->getProperty(pGpu, PDB_PROP_GPU_TEGRA_SOC_NVDISPLAY)) { - NV_PRINTF(LEVEL_ERROR, - "Could not find mapping for reg %x, deviceIndex=0x%x instance=%d\n", - regAddr, deviceIndex, instance); - NV_ASSERT(0); - return; - } - - status = gpuSanityCheckRegisterAccess(pGpu, regAddr, NULL); - if (status != NV_OK) - { - return; - } + status = gpuSanityCheckRegisterAccess(pGpu, regAddr, NULL); + if (status != NV_OK) + { + return; + } - threadStateGetCurrentUnchecked(&pThreadState, pGpu); + threadStateGetCurrentUnchecked(&pThreadState, pGpu); - _gpuHandleWriteRegisterFilter(pGpu, deviceIndex, instance, regAddr, - val, size, &flags, pThreadState); + _gpuHandleWriteRegisterFilter(pGpu, deviceIndex, instance, regAddr, + val, size, &flags, pThreadState); + } if (!(flags & REGISTER_FILTER_FLAGS_WRITE)) { switch (size) { case 8: - osDevWriteReg008(pGpu, pMapping, regAddr, 0xFFU & (val)); + osDevWriteReg008(pGpu, pMapping, mappingRegAddr, 0xFFU & (val)); break; case 16: - osDevWriteReg016(pGpu, pMapping, regAddr, 0xFFFFU & (val)); + osDevWriteReg016(pGpu, pMapping, mappingRegAddr, 0xFFFFU & (val)); break; case 32: - osDevWriteReg032(pGpu, pMapping, regAddr, val); + osDevWriteReg032(pGpu, pMapping, mappingRegAddr, val); break; } } } void -_gpuApertureWriteReg008 +ioaprtWriteReg08_IMPL ( - IO_APERTURE *pAperture, + IoAperture *pAperture, NvU32 addr, NvV8 val ) { - GPU_IO_DEVICE *pDevice = (GPU_IO_DEVICE*)pAperture->pDevice; - OBJGPU *pGpu = pDevice->pGpu; + NV_ASSERT(!gpumgrGetBcEnabledStatus(pAperture->pGpu)); - // - // NOTE: The SLI loop below reuses pAperture's values across all iterations - // OBJGPU's apertures are initialized to have the same baseAddress and length - // on all GPU device instances, so reusing the aperture here is fine. - // Device-specific instances are obtained via gpuGetDeviceMapping in the SLI loop. - // - SLI_LOOP_START(SLI_LOOP_FLAGS_BC_ONLY); - _gpuApertureWriteRegUnicast(pGpu, pAperture, addr, val, 8 /* size */); - SLI_LOOP_END; + ioaprtWriteRegUnicast(pAperture->pGpu, pAperture, addr, val, 8 /* size */); } void -_gpuApertureWriteReg016 +ioaprtWriteReg16_IMPL ( - IO_APERTURE *pAperture, + IoAperture *pAperture, NvU32 addr, NvV16 val ) { - GPU_IO_DEVICE *pDevice = (GPU_IO_DEVICE*)pAperture->pDevice; - OBJGPU *pGpu = pDevice->pGpu; + NV_ASSERT(!gpumgrGetBcEnabledStatus(pAperture->pGpu)); - // - // NOTE: The SLI loop below reuses pAperture's values across all iterations - // OBJGPU's apertures are initialized to have the same baseAddress and length - // on all GPU device instances, so reusing the aperture here is fine. - // Device-specific instances are obtained via gpuGetDeviceMapping in the SLI loop. - // - SLI_LOOP_START(SLI_LOOP_FLAGS_BC_ONLY); - _gpuApertureWriteRegUnicast(pGpu, pAperture, addr, val, 16 /* size */); - SLI_LOOP_END; + ioaprtWriteRegUnicast(pAperture->pGpu, pAperture, addr, val, 16 /* size */); } void -_gpuApertureWriteReg032 +ioaprtWriteReg32_IMPL ( - IO_APERTURE *pAperture, + IoAperture *pAperture, NvU32 addr, NvV32 val ) { - GPU_IO_DEVICE *pDevice = (GPU_IO_DEVICE*)pAperture->pDevice; - OBJGPU *pGpu = pDevice->pGpu; + NV_ASSERT(!gpumgrGetBcEnabledStatus(pAperture->pGpu)); - // - // NOTE: The SLI loop below reuses pAperture's values across all iterations - // OBJGPU's apertures are initialized to have the same baseAddress and length - // on all GPU device instances, so reusing the aperture here is fine. - // Device-specific instances are obtained via gpuGetDeviceMapping in the SLI loop. - // - SLI_LOOP_START(SLI_LOOP_FLAGS_BC_ONLY); - _gpuApertureWriteRegUnicast(pGpu, pAperture, addr, val, 32 /* size */); - SLI_LOOP_END; + ioaprtWriteRegUnicast(pAperture->pGpu, pAperture, addr, val, 32 /* size */); } void -_gpuApertureWriteReg032Unicast +ioaprtWriteReg32Uc_IMPL ( - IO_APERTURE *pAperture, + IoAperture *pAperture, NvU32 addr, NvV32 val ) { - GPU_IO_DEVICE *pDevice = (GPU_IO_DEVICE*)pAperture->pDevice; - OBJGPU *pGpu = pDevice->pGpu; - - _gpuApertureWriteRegUnicast(pGpu, pAperture, addr, val, 32 /* size */); + ioaprtWriteRegUnicast(pAperture->pGpu, pAperture, addr, val, 32 /* size */); } void @@ -462,114 +468,108 @@ } static NvU32 -_gpuApertureReadReg +ioaprtReadReg ( - IO_APERTURE *pAperture, + IoAperture *pAperture, NvU32 addr, NvU32 size ) { - NV_ASSERT_OR_RETURN(pAperture, NV_ERR_INVALID_ARGUMENT); - NV_ASSERT_OR_RETURN(pAperture->pDevice, NV_ERR_INVALID_ARGUMENT); - NvU32 flags = 0; NvU32 returnValue = 0; - GPU_IO_DEVICE *pDevice = (GPU_IO_DEVICE*) pAperture->pDevice; - OBJGPU *pGpu = pDevice->pGpu; + OBJGPU *pGpu = pAperture->pGpu; NV_STATUS status = NV_OK; NvU32 regAddr = pAperture->baseAddress + addr; - NvU32 deviceIndex = pDevice->deviceIndex; - NvU32 instance = pDevice->instance; + NvU32 mappingRegAddr = regAddr - pAperture->mappingStartAddr; + NvU32 deviceIndex = pAperture->deviceIndex; + NvU32 instance = pAperture->deviceInstance; + DEVICE_MAPPING *pMapping = pAperture->pMapping; THREAD_STATE_NODE *pThreadState; pGpu->registerAccess.regReadCount++; - DEVICE_MAPPING *pMapping = gpuGetDeviceMapping(pGpu, deviceIndex, instance); - if (!pMapping) + if (!pGpu->getProperty(pGpu, PDB_PROP_GPU_TEGRA_SOC_NVDISPLAY)) { - NV_PRINTF(LEVEL_ERROR, - "Could not find mapping for reg %x, deviceIndex=0x%x instance=%d\n", - regAddr, deviceIndex, instance); - NV_ASSERT(0); - return 0xd0d0d0d0U; - } - - status = gpuSanityCheckRegisterAccess(pGpu, regAddr, NULL); - if (status != NV_OK) - { - return (~0); - } + status = gpuSanityCheckRegisterAccess(pGpu, regAddr, NULL); + if (status != NV_OK) + { + return (~0); + } - threadStateGetCurrentUnchecked(&pThreadState, pGpu); + threadStateGetCurrentUnchecked(&pThreadState, pGpu); - returnValue = _gpuHandleReadRegisterFilter(pGpu, deviceIndex, instance, - regAddr, size, &flags, pThreadState); + returnValue = _gpuHandleReadRegisterFilter(pGpu, deviceIndex, instance, + regAddr, size, &flags, pThreadState); + } if (!(flags & REGISTER_FILTER_FLAGS_READ)) { switch (size) { case 8: - returnValue = osDevReadReg008(pGpu, pMapping, regAddr); + returnValue = osDevReadReg008(pGpu, pMapping, mappingRegAddr); break; case 16: - returnValue = osDevReadReg016(pGpu, pMapping, regAddr); + returnValue = osDevReadReg016(pGpu, pMapping, mappingRegAddr); break; case 32: - returnValue = osDevReadReg032(pGpu, pMapping, regAddr); + returnValue = osDevReadReg032(pGpu, pMapping, mappingRegAddr); break; } } - // Make sure the value read is sane before we party on it. - gpuSanityCheckRegRead(pGpu, regAddr, size, &returnValue); + if (!pGpu->getProperty(pGpu, PDB_PROP_GPU_TEGRA_SOC_NVDISPLAY)) + { + // Make sure the value read is sane before we party on it. + gpuSanityCheckRegRead(pGpu, regAddr, size, &returnValue); + } return returnValue; } NvU8 -_gpuApertureReadReg008 +ioaprtReadReg08_IMPL ( - IO_APERTURE *pAperture, + IoAperture *pAperture, NvU32 addr ) { - return (NvU8) _gpuApertureReadReg(pAperture, addr, 8 /* size */); + return (NvU8) ioaprtReadReg(pAperture, addr, 8 /* size */); } -static NvU16 -_gpuApertureReadReg016 +NvU16 +ioaprtReadReg16_IMPL ( - IO_APERTURE *pAperture, + IoAperture *pAperture, NvU32 addr ) { - return (NvU16) _gpuApertureReadReg(pAperture, addr, 16 /* size */); + return (NvU16) ioaprtReadReg(pAperture, addr, 16 /* size */); } -static NvU32 -_gpuApertureReadReg032 +NvU32 +ioaprtReadReg32_IMPL ( - IO_APERTURE *pAperture, + IoAperture *pAperture, NvU32 addr ) { - return _gpuApertureReadReg(pAperture, addr, 32 /* size */); + return ioaprtReadReg(pAperture, addr, 32 /* size */); } /*! * Checks if the register address is valid for a particular aperture * - * @param[in] pAperture IO_APERTURE pointer + * @param[in] pAperture IoAperture pointer * @param[in] addr register address * * @returns NV_TRUE Register offset is valid */ -static NvBool -_gpuApertureValidReg +NvBool +ioaprtIsRegValid_IMPL ( - IO_APERTURE *pAperture, + IoAperture *pAperture, NvU32 addr ) { @@ -748,57 +748,24 @@ * @return NV_OK if IO Aperture is successfully initialized, error otherwise. */ static NV_STATUS -_gpuInitIODeviceAndAperture +_gpuInitIOAperture ( - OBJGPU *pGpu, - NvU32 deviceIndex, - NvU32 gpuDeviceEnum, - RmPhysAddr gpuNvPAddr, - NvU32 gpuNvLength + OBJGPU *pGpu, + NvU32 deviceIndex, + DEVICE_MAPPING *pMapping ) { NV_STATUS rmStatus; - GPU_IO_DEVICE *pIODevice = NULL; - - // Initialize GPU IO Device - rmStatus = _allocGpuIODevice(&pIODevice); - if (rmStatus != NV_OK) - { - NV_PRINTF(LEVEL_ERROR, - "Failed to initialize pGpu IO device for devIdx %d.\n", - deviceIndex); - - return rmStatus; - } - pIODevice->pGpu = pGpu; - pIODevice->deviceIndex = deviceIndex; - pIODevice->gpuDeviceEnum = gpuDeviceEnum; - pIODevice->gpuNvPAddr = gpuNvPAddr; - pIODevice->gpuNvLength = gpuNvLength; - pIODevice->refCount = 0; - - // GPU register operations are always on instance 0 - pIODevice->instance = 0; - - // Initialize register functions in IO_DEVICE - pIODevice->parent.pReadReg008Fn = (ReadReg008Fn*) &_gpuApertureReadReg008; - pIODevice->parent.pReadReg016Fn = (ReadReg016Fn*) &_gpuApertureReadReg016; - pIODevice->parent.pReadReg032Fn = (ReadReg032Fn*) &_gpuApertureReadReg032; - pIODevice->parent.pWriteReg008Fn = (WriteReg008Fn*) &_gpuApertureWriteReg008; - pIODevice->parent.pWriteReg016Fn = (WriteReg016Fn*) &_gpuApertureWriteReg016; - pIODevice->parent.pWriteReg032Fn = (WriteReg032Fn*) &_gpuApertureWriteReg032; - pIODevice->parent.pWriteReg032UcFn = (WriteReg032Fn*) &_gpuApertureWriteReg032Unicast; - pIODevice->parent.pValidRegFn = (ValidRegFn*) &_gpuApertureValidReg; - - rmStatus = ioaccessCreateIOAperture(&pGpu->pIOApertures[deviceIndex], - NULL, // no parent aperture - (IO_DEVICE*) pIODevice, - 0, gpuNvLength); // offset, length + rmStatus = objCreate(&pGpu->pIOApertures[deviceIndex], NVOC_NULL_OBJECT, IoAperture, + NULL, // no parent aperture + pGpu, + deviceIndex, + 0, // GPU register operations are always on instance 0 + pMapping, 0, // mapping, mappingStartAddr + 0, pMapping->gpuNvLength); // offset, length if (rmStatus != NV_OK) { - portMemFree(pIODevice); - NV_PRINTF(LEVEL_ERROR, "Failed to initialize pGpu IO aperture for devIdx %d.\n", deviceIndex); @@ -1634,7 +1601,7 @@ { NvU64 maxBar0Size = pGpu->deviceMappings[0].gpuNvLength; - // The register offset should be 4 bytes smaller than the max bar size + // The register offset should be 4 bytes smaller than the max bar size if (offset > (maxBar0Size - 4)) { return NV_ERR_INVALID_ARGUMENT; @@ -1777,3 +1744,148 @@ return NV_OK; } + + +NV_STATUS swbcaprtConstruct_IMPL +( + SwBcAperture *pAperture, + IoAperture *pApertures, + NvU32 numApertures +) +{ + NV_ASSERT_OR_RETURN(numApertures != 0, NV_ERR_INVALID_ARGUMENT); + + pAperture->pApertures = pApertures; + pAperture->numApertures = numApertures; + + return NV_OK; +} + +NvU8 +swbcaprtReadReg08_IMPL +( + SwBcAperture *pAperture, + NvU32 addr +) +{ + NvU8 val = REG_RD08(&pAperture->pApertures[0], addr); + +#if defined(DEBUG) + NvU32 i; + for (i = 1; i < pAperture->numApertures; i++) + NV_ASSERT(REG_RD08(&pAperture->pApertures[i], addr) == val); +#endif // defined(DEBUG) + + return val; +} + +NvU16 +swbcaprtReadReg16_IMPL +( + SwBcAperture *pAperture, + NvU32 addr +) +{ + NvU16 val = REG_RD16(&pAperture->pApertures[0], addr); + +#if defined(DEBUG) + NvU32 i; + for (i = 1; i < pAperture->numApertures; i++) + NV_ASSERT(REG_RD16(&pAperture->pApertures[i], addr) == val); +#endif // defined(DEBUG) + + return val; +} + +NvU32 +swbcaprtReadReg32_IMPL +( + SwBcAperture *pAperture, + NvU32 addr +) +{ + NvU32 val = REG_RD32(&pAperture->pApertures[0], addr); + +#if defined(DEBUG) + NvU32 i; + for (i = 1; i < pAperture->numApertures; i++) + NV_ASSERT(REG_RD32(&pAperture->pApertures[i], addr) == val); +#endif // defined(DEBUG) + + return val; +} + +void +swbcaprtWriteReg08_IMPL +( + SwBcAperture *pAperture, + NvU32 addr, + NvV8 value +) +{ + NvU32 i; + + for (i = 0; i < pAperture->numApertures; i++) + REG_WR08(&pAperture->pApertures[i], addr, value); +} + +void +swbcaprtWriteReg16_IMPL +( + SwBcAperture *pAperture, + NvU32 addr, + NvV16 value +) +{ + NvU32 i; + + for (i = 0; i < pAperture->numApertures; i++) + REG_WR16(&pAperture->pApertures[i], addr, value); +} + +void +swbcaprtWriteReg32_IMPL +( + SwBcAperture *pAperture, + NvU32 addr, + NvV32 value +) +{ + NvU32 i; + + for (i = 0; i < pAperture->numApertures; i++) + REG_WR32(&pAperture->pApertures[i], addr, value); +} + +void +swbcaprtWriteReg32Uc_IMPL +( + SwBcAperture *pAperture, + NvU32 addr, + NvV32 value +) +{ + NvU32 i; + + for (i = 0; i < pAperture->numApertures; i++) + REG_WR32_UC(&pAperture->pApertures[i], addr, value); +} + +NvBool +swbcaprtIsRegValid_IMPL +( + SwBcAperture *pAperture, + NvU32 addr +) +{ + + NvU32 i; + + for (i = 0; i < pAperture->numApertures; i++) + { + if (!REG_VALID(&pAperture->pApertures[i], addr)) + return NV_FALSE; + } + + return NV_TRUE; +} diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/kernel/gpu/gpu_fabric_probe.c nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/kernel/gpu/gpu_fabric_probe.c --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/kernel/gpu/gpu_fabric_probe.c 2023-10-25 20:21:02.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/kernel/gpu/gpu_fabric_probe.c 2024-03-05 22:13:27.000000000 +0000 @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 1993-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 1993-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -29,54 +29,47 @@ #include "gpu/gpu.h" #include "os/os.h" -#include "objtmr.h" #include "utils/nvprintf.h" #include "kernel/gpu/nvlink/kernel_nvlink.h" -#include "ctrl/ctrl2080/ctrl2080pmgr.h" #include "gpu/gpu_fabric_probe.h" -#include "compute/fabric.h" #include "nvlink_inband_msg.h" #include "kernel/mem_mgr/fabric_vaspace.h" +#include "ctrl/ctrl2080/ctrl2080internal.h" // Structure to hold gpu probe information -typedef struct GPU_FABRIC_PROBE_INFO +typedef struct GPU_FABRIC_PROBE_INFO_KERNEL { - NvU64 probeRetryDelay; NvBool bProbeRespRcvd; - NvU64 numProbes; + NvU8 bwMode; OBJGPU *pGpu; - TMR_EVENT *pTmrEvent; - - NV2080_CTRL_NVLINK_INBAND_SEND_DATA_PARAMS sendDataParams; nvlink_inband_gpu_probe_rsp_msg_t probeResponseMsg; -} GPU_FABRIC_PROBE_INFO; - +} GPU_FABRIC_PROBE_INFO_KERNEL; static NV_STATUS _gpuFabricProbeFullSanityCheck ( - GPU_FABRIC_PROBE_INFO *pGpuFabricProbeInfo + GPU_FABRIC_PROBE_INFO_KERNEL *pGpuFabricProbeInfoKernel ) { - if (pGpuFabricProbeInfo == NULL) + if (pGpuFabricProbeInfoKernel == NULL) { return NV_ERR_NOT_SUPPORTED; } LOCK_ASSERT_AND_RETURN(rmDeviceGpuLockIsOwner( - gpuGetInstance(pGpuFabricProbeInfo->pGpu))); + gpuGetInstance(pGpuFabricProbeInfoKernel->pGpu))); - if (!gpuFabricProbeIsReceived(pGpuFabricProbeInfo)) + if (!gpuFabricProbeIsReceived(pGpuFabricProbeInfoKernel)) { return NV_ERR_NOT_READY; } - if (!gpuFabricProbeIsSuccess(pGpuFabricProbeInfo)) + if (!gpuFabricProbeIsSuccess(pGpuFabricProbeInfoKernel)) { - return pGpuFabricProbeInfo->probeResponseMsg.msgHdr.status; + return pGpuFabricProbeInfoKernel->probeResponseMsg.msgHdr.status; } return NV_OK; @@ -85,17 +78,17 @@ NV_STATUS gpuFabricProbeGetGpuFabricHandle ( - GPU_FABRIC_PROBE_INFO *pGpuFabricProbeInfo, + GPU_FABRIC_PROBE_INFO_KERNEL *pGpuFabricProbeInfoKernel, NvU64 *pHandle ) { NV_STATUS status; - status = _gpuFabricProbeFullSanityCheck(pGpuFabricProbeInfo); + status = _gpuFabricProbeFullSanityCheck(pGpuFabricProbeInfoKernel); NV_CHECK_OR_RETURN(LEVEL_ERROR, status == NV_OK, status); - *pHandle = pGpuFabricProbeInfo->probeResponseMsg.probeRsp.gpuHandle; + *pHandle = pGpuFabricProbeInfoKernel->probeResponseMsg.probeRsp.gpuHandle; return status; } @@ -103,17 +96,17 @@ NV_STATUS gpuFabricProbeGetGfId ( - GPU_FABRIC_PROBE_INFO *pGpuFabricProbeInfo, + GPU_FABRIC_PROBE_INFO_KERNEL *pGpuFabricProbeInfoKernel, NvU32 *pGfId ) { NV_STATUS status; - status = _gpuFabricProbeFullSanityCheck(pGpuFabricProbeInfo); + status = _gpuFabricProbeFullSanityCheck(pGpuFabricProbeInfoKernel); NV_CHECK_OR_RETURN(LEVEL_ERROR, status == NV_OK, status); - *pGfId = pGpuFabricProbeInfo->probeResponseMsg.probeRsp.gfId; + *pGfId = pGpuFabricProbeInfoKernel->probeResponseMsg.probeRsp.gfId; return status; } @@ -121,17 +114,17 @@ NV_STATUS gpuFabricProbeGetfmCaps ( - GPU_FABRIC_PROBE_INFO *pGpuFabricProbeInfo, + GPU_FABRIC_PROBE_INFO_KERNEL *pGpuFabricProbeInfoKernel, NvU64 *pFmCaps ) { NV_STATUS status; - status = _gpuFabricProbeFullSanityCheck(pGpuFabricProbeInfo); + status = _gpuFabricProbeFullSanityCheck(pGpuFabricProbeInfoKernel); NV_CHECK_OR_RETURN(LEVEL_ERROR, status == NV_OK, status); - *pFmCaps = pGpuFabricProbeInfo->probeResponseMsg.probeRsp.fmCaps; + *pFmCaps = pGpuFabricProbeInfoKernel->probeResponseMsg.probeRsp.fmCaps; return status; } @@ -139,20 +132,20 @@ NV_STATUS gpuFabricProbeGetClusterUuid ( - GPU_FABRIC_PROBE_INFO *pGpuFabricProbeInfo, + GPU_FABRIC_PROBE_INFO_KERNEL *pGpuFabricProbeInfoKernel, NvUuid *pClusterUuid ) { NV_STATUS status; - status = _gpuFabricProbeFullSanityCheck(pGpuFabricProbeInfo); + status = _gpuFabricProbeFullSanityCheck(pGpuFabricProbeInfoKernel); NV_CHECK_OR_RETURN(LEVEL_ERROR, status == NV_OK, status); portMemCopy(&pClusterUuid->uuid[0], sizeof(pClusterUuid->uuid), - &pGpuFabricProbeInfo->probeResponseMsg.probeRsp.clusterUuid.uuid[0], - sizeof(pGpuFabricProbeInfo->probeResponseMsg.probeRsp.clusterUuid.uuid)); + &pGpuFabricProbeInfoKernel->probeResponseMsg.probeRsp.clusterUuid.uuid[0], + sizeof(pGpuFabricProbeInfoKernel->probeResponseMsg.probeRsp.clusterUuid.uuid)); return status; } @@ -160,17 +153,17 @@ NV_STATUS gpuFabricProbeGetFabricPartitionId ( - GPU_FABRIC_PROBE_INFO *pGpuFabricProbeInfo, + GPU_FABRIC_PROBE_INFO_KERNEL *pGpuFabricProbeInfoKernel, NvU16 *pFabricPartitionId ) { NV_STATUS status; - status = _gpuFabricProbeFullSanityCheck(pGpuFabricProbeInfo); + status = _gpuFabricProbeFullSanityCheck(pGpuFabricProbeInfoKernel); NV_CHECK_OR_RETURN(LEVEL_ERROR, status == NV_OK, status); - *pFabricPartitionId = pGpuFabricProbeInfo->probeResponseMsg.probeRsp.fabricPartitionId; + *pFabricPartitionId = pGpuFabricProbeInfoKernel->probeResponseMsg.probeRsp.fabricPartitionId; return status; } @@ -178,17 +171,17 @@ NV_STATUS gpuFabricProbeGetGpaAddress ( - GPU_FABRIC_PROBE_INFO *pGpuFabricProbeInfo, + GPU_FABRIC_PROBE_INFO_KERNEL *pGpuFabricProbeInfoKernel, NvU64 *pGpaAddress ) { NV_STATUS status; - status = _gpuFabricProbeFullSanityCheck(pGpuFabricProbeInfo); + status = _gpuFabricProbeFullSanityCheck(pGpuFabricProbeInfoKernel); NV_CHECK_OR_RETURN(LEVEL_ERROR, status == NV_OK, status); - *pGpaAddress = pGpuFabricProbeInfo->probeResponseMsg.probeRsp.gpaAddress; + *pGpaAddress = pGpuFabricProbeInfoKernel->probeResponseMsg.probeRsp.gpaAddress; return status; } @@ -196,17 +189,17 @@ NV_STATUS gpuFabricProbeGetGpaAddressRange ( - GPU_FABRIC_PROBE_INFO *pGpuFabricProbeInfo, + GPU_FABRIC_PROBE_INFO_KERNEL *pGpuFabricProbeInfoKernel, NvU64 *pGpaAddressRange ) { NV_STATUS status; - status = _gpuFabricProbeFullSanityCheck(pGpuFabricProbeInfo); + status = _gpuFabricProbeFullSanityCheck(pGpuFabricProbeInfoKernel); NV_CHECK_OR_RETURN(LEVEL_ERROR, status == NV_OK, status); - *pGpaAddressRange = pGpuFabricProbeInfo->probeResponseMsg.probeRsp.gpaAddressRange; + *pGpaAddressRange = pGpuFabricProbeInfoKernel->probeResponseMsg.probeRsp.gpaAddressRange; return status; } @@ -214,17 +207,17 @@ NV_STATUS gpuFabricProbeGetFlaAddress ( - GPU_FABRIC_PROBE_INFO *pGpuFabricProbeInfo, + GPU_FABRIC_PROBE_INFO_KERNEL *pGpuFabricProbeInfoKernel, NvU64 *pFlaAddress ) { NV_STATUS status; - status = _gpuFabricProbeFullSanityCheck(pGpuFabricProbeInfo); + status = _gpuFabricProbeFullSanityCheck(pGpuFabricProbeInfoKernel); NV_CHECK_OR_RETURN(LEVEL_ERROR, status == NV_OK, status); - *pFlaAddress = pGpuFabricProbeInfo->probeResponseMsg.probeRsp.flaAddress; + *pFlaAddress = pGpuFabricProbeInfoKernel->probeResponseMsg.probeRsp.flaAddress; return status; } @@ -232,17 +225,17 @@ NV_STATUS gpuFabricProbeGetFlaAddressRange ( - GPU_FABRIC_PROBE_INFO *pGpuFabricProbeInfo, + GPU_FABRIC_PROBE_INFO_KERNEL *pGpuFabricProbeInfoKernel, NvU64 *pFlaAddressRange ) { NV_STATUS status; - status = _gpuFabricProbeFullSanityCheck(pGpuFabricProbeInfo); + status = _gpuFabricProbeFullSanityCheck(pGpuFabricProbeInfoKernel); NV_CHECK_OR_RETURN(LEVEL_ERROR, status == NV_OK, status); - *pFlaAddressRange = pGpuFabricProbeInfo->probeResponseMsg.probeRsp.flaAddressRange; + *pFlaAddressRange = pGpuFabricProbeInfoKernel->probeResponseMsg.probeRsp.flaAddressRange; return status; } @@ -250,19 +243,34 @@ NV_STATUS gpuFabricProbeGetNumProbeReqs ( - GPU_FABRIC_PROBE_INFO *pGpuFabricProbeInfo, + GPU_FABRIC_PROBE_INFO_KERNEL *pGpuFabricProbeInfoKernel, NvU64 *numProbes ) { - if (pGpuFabricProbeInfo == NULL) + NV2080_CTRL_CMD_INTERNAL_GET_GPU_FABRIC_PROBE_INFO_PARAMS params = { 0 }; + RM_API *pRmApi; + OBJGPU *pGpu; + + if (pGpuFabricProbeInfoKernel == NULL) { return NV_ERR_NOT_SUPPORTED; } + pGpu = pGpuFabricProbeInfoKernel->pGpu; + pRmApi = GPU_GET_PHYSICAL_RMAPI(pGpu); + LOCK_ASSERT_AND_RETURN(rmDeviceGpuLockIsOwner( - gpuGetInstance(pGpuFabricProbeInfo->pGpu))); + gpuGetInstance(pGpuFabricProbeInfoKernel->pGpu))); + + NV_CHECK_OK_OR_RETURN(LEVEL_ERROR, + pRmApi->Control(pRmApi, + pGpu->hInternalClient, + pGpu->hInternalSubdevice, + NV2080_CTRL_CMD_INTERNAL_GPU_GET_FABRIC_PROBE_INFO, + ¶ms, + sizeof(params))); - *numProbes = pGpuFabricProbeInfo->numProbes; + *numProbes = params.numProbes; return NV_OK; } @@ -270,40 +278,40 @@ NvBool gpuFabricProbeIsReceived ( - GPU_FABRIC_PROBE_INFO *pGpuFabricProbeInfo + GPU_FABRIC_PROBE_INFO_KERNEL *pGpuFabricProbeInfoKernel ) { - if (pGpuFabricProbeInfo == NULL) + if (pGpuFabricProbeInfoKernel == NULL) { return NV_FALSE; } LOCK_ASSERT_AND_RETURN_BOOL(rmDeviceGpuLockIsOwner( - gpuGetInstance(pGpuFabricProbeInfo->pGpu)), + gpuGetInstance(pGpuFabricProbeInfoKernel->pGpu)), NV_FALSE); - return pGpuFabricProbeInfo->bProbeRespRcvd; + return pGpuFabricProbeInfoKernel->bProbeRespRcvd; } NvBool gpuFabricProbeIsSuccess ( - GPU_FABRIC_PROBE_INFO *pGpuFabricProbeInfo + GPU_FABRIC_PROBE_INFO_KERNEL *pGpuFabricProbeInfoKernel ) { nvlink_inband_gpu_probe_rsp_msg_t *pProbeResponseMsg; nvlink_inband_msg_header_t *pProbeRespMsgHdr; - if (pGpuFabricProbeInfo == NULL) + if (pGpuFabricProbeInfoKernel == NULL) { return NV_FALSE; } LOCK_ASSERT_AND_RETURN_BOOL(rmDeviceGpuLockIsOwner(gpuGetInstance( - pGpuFabricProbeInfo->pGpu)), + pGpuFabricProbeInfoKernel->pGpu)), NV_FALSE); - pProbeResponseMsg = &pGpuFabricProbeInfo->probeResponseMsg; + pProbeResponseMsg = &pGpuFabricProbeInfoKernel->probeResponseMsg; pProbeRespMsgHdr = &pProbeResponseMsg->msgHdr; return pProbeRespMsgHdr->status == NV_OK; @@ -312,196 +320,25 @@ NV_STATUS gpuFabricProbeGetFmStatus ( - GPU_FABRIC_PROBE_INFO *pGpuFabricProbeInfo + GPU_FABRIC_PROBE_INFO_KERNEL *pGpuFabricProbeInfoKernel ) { - if (pGpuFabricProbeInfo == NULL) + if (pGpuFabricProbeInfoKernel == NULL) { return NV_ERR_NOT_SUPPORTED; } LOCK_ASSERT_AND_RETURN(rmDeviceGpuLockIsOwner( - gpuGetInstance(pGpuFabricProbeInfo->pGpu))); - - return pGpuFabricProbeInfo->probeResponseMsg.msgHdr.status; -} - -static void -_gpuFabricProbeForceCompletionError -( - GPU_FABRIC_PROBE_INFO *pGpuFabricProbeInfo, - NV_STATUS status -) -{ - NV_ASSERT(!pGpuFabricProbeInfo->bProbeRespRcvd); - pGpuFabricProbeInfo->bProbeRespRcvd = NV_TRUE; - pGpuFabricProbeInfo->probeResponseMsg.msgHdr.status = status; -} - -static NV_STATUS -_gpuFabricProbeSchedule -( - GPU_FABRIC_PROBE_INFO *pGpuFabricProbeInfo -) -{ - NV_STATUS status; - OBJGPU *pGpu = pGpuFabricProbeInfo->pGpu; - OBJTMR *pTmr = GPU_GET_TIMER(pGpu); - - NV_ASSERT(pGpuFabricProbeInfo->pTmrEvent != NULL); - - status = tmrEventScheduleRel(pTmr, pGpuFabricProbeInfo->pTmrEvent, - pGpuFabricProbeInfo->probeRetryDelay); - if (status != NV_OK) - { - NV_PRINTF(LEVEL_ERROR, "GPU%u tmrEventScheduleRel failed\n", - gpuGetInstance(pGpu)); - return status; - } - - pGpuFabricProbeInfo->numProbes++; - - if ((pGpuFabricProbeInfo->numProbes % - pGpu->fabricProbeSlowdownThreshold) == 0) - { - pGpuFabricProbeInfo->probeRetryDelay += pGpuFabricProbeInfo->probeRetryDelay; - } - - NV_PRINTF(LEVEL_INFO, "GPU%u Num retried probes %lld \n", - gpuGetInstance(pGpu), pGpuFabricProbeInfo->numProbes); - - return NV_OK; -} - -static NV_STATUS -_gpuFabricProbeConstructReq -( - nvlink_inband_gpu_probe_req_t *pProbeReq, - OBJGPU *pGpu -) -{ - NV_STATUS status; - KernelNvlink *pKernelNvlink = GPU_GET_KERNEL_NVLINK(pGpu); - NvU8 *pUuid; - NvU32 uuidLength, flags = 0; - - portMemSet(pProbeReq, 0, sizeof(*pProbeReq)); - - flags = FLD_SET_DRF_NUM(2080_GPU_CMD, _GPU_GET_GID_FLAGS, _TYPE, - NV2080_GPU_CMD_GPU_GET_GID_FLAGS_TYPE_SHA1, flags); - flags = FLD_SET_DRF_NUM(2080_GPU_CMD, _GPU_GET_GID_FLAGS, _FORMAT, - NV2080_GPU_CMD_GPU_GET_GID_FLAGS_FORMAT_BINARY, flags); - status = gpuGetGidInfo(pGpu, &pUuid, &uuidLength, flags); - if (status != NV_OK) - { - NV_PRINTF(LEVEL_ERROR, "GPU%u Failed to update GPU UUID\n", - gpuGetInstance(pGpu)); - return status; - } - portMemCopy(&pProbeReq->gpuUuid.uuid[0], uuidLength, pUuid, uuidLength); - portMemFree(pUuid); + gpuGetInstance(pGpuFabricProbeInfoKernel->pGpu))); - pProbeReq->pciInfo = gpuGetDBDF(pGpu); - pProbeReq->moduleId = pGpu->moduleId; - pProbeReq->discoveredLinkMask = pKernelNvlink->discoveredLinks; - pProbeReq->enabledLinkMask = pKernelNvlink->enabledLinks; - pProbeReq->gpuCapMask = (IS_VIRTUAL_WITH_SRIOV(pGpu)) ? - NVLINK_INBAND_GPU_PROBE_CAPS_SRIOV_ENABLED : 0; - return status; + return pGpuFabricProbeInfoKernel->probeResponseMsg.msgHdr.status; } static void -_gpuFabricProbeSend_WORKITEM -( - NvU32 gpuInstance, - void *pArgs -) -{ - OBJGPU *pGpu = gpumgrGetGpu(gpuInstance); - KernelNvlink *pKernelNvlink = GPU_GET_KERNEL_NVLINK(pGpu); - GPU_FABRIC_PROBE_INFO *pGpuFabricProbeInfo = pGpu->pGpuFabricProbeInfo; - NV_STATUS status; - - if (pGpuFabricProbeInfo == NULL) - { - NV_PRINTF(LEVEL_INFO, - "GPU%u Invalid Probe info\n", - gpuGetInstance(pGpu)); - return; - } - - if (pKernelNvlink->bIsGpuDegraded || - (pKernelNvlink->discoveredLinks == 0)) - { - NV_PRINTF(LEVEL_INFO, - "GPU%u Degraded. Not sending probe\n", - gpuGetInstance(pGpu)); - _gpuFabricProbeForceCompletionError(pGpuFabricProbeInfo, NV_ERR_NOT_SUPPORTED); - return; - } - - if (pGpuFabricProbeInfo->bProbeRespRcvd) - { - NV_PRINTF(LEVEL_INFO, - "GPU%u Probe Resp rcvd. Not sending probe\n", - gpuGetInstance(pGpu)); - return; - } - - status = knvlinkSendInbandData(pGpu, - pKernelNvlink, - &pGpuFabricProbeInfo->sendDataParams); - if (status != NV_OK) - { - NV_PRINTF(LEVEL_ERROR, "GPU%u Send Inband data failed\n", - gpuGetInstance(pGpu)); - // - // Deliberately ignoring return value as we want probes to be - // retried until success - // - } - - status = _gpuFabricProbeSchedule(pGpuFabricProbeInfo); - if (status != NV_OK) - { - NV_PRINTF(LEVEL_ERROR, "GPU%u Schedule Probe failed\n", - gpuGetInstance(pGpu)); - _gpuFabricProbeForceCompletionError(pGpuFabricProbeInfo, NV_ERR_OPERATING_SYSTEM); - return; - } -} - -static NV_STATUS -_gpuFabricProbeScheduleWq -( - OBJGPU *pGpu, - OBJTMR *pTmr, - TMR_EVENT *pEvent -) -{ - OBJOS *pOS = GPU_GET_OS(pGpu); - NV_STATUS status = NV_OK; - - NV_ASSERT_OR_RETURN(rmDeviceGpuLockIsOwner(gpuGetInstance(pGpu)), NV_ERR_INVALID_STATE); - - status = pOS->osQueueWorkItemWithFlags(pGpu, _gpuFabricProbeSend_WORKITEM, NULL, - OS_QUEUE_WORKITEM_FLAGS_LOCK_GPU_GROUP_SUBDEVICE_RW); - if (status != NV_OK) - { - NV_PRINTF(LEVEL_ERROR, "GPU%u OS Schedule Probe failed\n", - gpuGetInstance(pGpu)); - _gpuFabricProbeForceCompletionError(pGpu->pGpuFabricProbeInfo, NV_ERR_OPERATING_SYSTEM); - } - - return status; -} - - -static void _gpuFabricProbeSetupGpaRange ( OBJGPU *pGpu, - GPU_FABRIC_PROBE_INFO *pGpuFabricProbeInfo + GPU_FABRIC_PROBE_INFO_KERNEL *pGpuFabricProbeInfoKernel ) { KernelNvlink *pKernelNvlink = GPU_GET_KERNEL_NVLINK(pGpu); @@ -511,19 +348,17 @@ NvU64 gpaAddress; NvU64 gpaAddressSize; - NV_CHECK_OR_RETURN_VOID(LEVEL_ERROR, - gpuFabricProbeGetGpaAddress(pGpuFabricProbeInfo, - &gpaAddress) == NV_OK); + NV_CHECK_OR_RETURN_VOID(LEVEL_ERROR, + gpuFabricProbeGetGpaAddress(pGpuFabricProbeInfoKernel, + &gpaAddress) == NV_OK); NV_CHECK_OR_RETURN_VOID(LEVEL_ERROR, - gpuFabricProbeGetGpaAddressRange(pGpuFabricProbeInfo, - &gpaAddressSize) == NV_OK); + gpuFabricProbeGetGpaAddressRange(pGpuFabricProbeInfoKernel, + &gpaAddressSize) == NV_OK); - //pKernelNvlink->fabricBaseAddr = gpaAddress; - NV_CHECK_OR_RETURN_VOID(LEVEL_ERROR, - knvlinkSetUniqueFabricBaseAddress_HAL(pGpu, - pKernelNvlink, - gpaAddress) == NV_OK); + NV_CHECK_OR_RETURN_VOID(LEVEL_ERROR, + knvlinkSetUniqueFabricBaseAddress_HAL(pGpu, pKernelNvlink, + gpaAddress) == NV_OK); } } @@ -531,7 +366,7 @@ _gpuFabricProbeSetupFlaRange ( OBJGPU *pGpu, - GPU_FABRIC_PROBE_INFO *pGpuFabricProbeInfo + GPU_FABRIC_PROBE_INFO_KERNEL *pGpuFabricProbeInfoKernel ) { if (pGpu->pFabricVAS != NULL) @@ -540,57 +375,61 @@ NvU64 flaSize; NV_CHECK_OR_RETURN_VOID(LEVEL_ERROR, - gpuFabricProbeGetFlaAddress(pGpuFabricProbeInfo, &flaBaseAddress) == NV_OK); + gpuFabricProbeGetFlaAddress(pGpuFabricProbeInfoKernel, + &flaBaseAddress) == NV_OK); NV_CHECK_OR_RETURN_VOID(LEVEL_ERROR, - gpuFabricProbeGetFlaAddressRange(pGpuFabricProbeInfo, &flaSize) == NV_OK); + gpuFabricProbeGetFlaAddressRange(pGpuFabricProbeInfoKernel, + &flaSize) == NV_OK); NV_CHECK_OR_RETURN_VOID(LEVEL_ERROR, - fabricvaspaceInitUCRange(dynamicCast(pGpu->pFabricVAS, FABRIC_VASPACE), - pGpu, flaBaseAddress, flaSize) == NV_OK); + fabricvaspaceInitUCRange(dynamicCast(pGpu->pFabricVAS, FABRIC_VASPACE), + pGpu, flaBaseAddress, flaSize) == NV_OK); } } -void -_gpuFabricProbeReceive +static NV_STATUS +_gpuFabricProbeReceiveKernel ( - OBJGPU *pGpu, + NvU32 gpuInstance, NV2080_CTRL_NVLINK_INBAND_RECEIVED_DATA_PARAMS *pInbandRcvParams ) { + OBJGPU *pGpu; + NvU32 gpuMaskUnused; nvlink_inband_gpu_probe_rsp_msg_t *pProbeRespMsg; - GPU_FABRIC_PROBE_INFO *pGpuFabricProbeInfo; - nvlink_inband_gpu_probe_req_msg_t *pProbeReqMsg = NULL; - NvU8 *pRsvd = NULL; - OBJSYS *pSys = SYS_GET_INSTANCE(); + GPU_FABRIC_PROBE_INFO_KERNEL *pGpuFabricProbeInfoKernel; + NV_STATUS status; - NV_ASSERT(rmDeviceGpuLockIsOwner(gpuGetInstance(pGpu))); + if ((pGpu = gpumgrGetGpu(gpuInstance)) == NULL) + { + NV_ASSERT_FAILED("Invalid GPU instance"); + return NV_ERR_INVALID_ARGUMENT; + } - NV_ASSERT(pInbandRcvParams != NULL); + // + // There is a scenario where _gpuFabricProbeStart fails in the GSP + // and returns failure to kernel ctrl call to start probe. + // This will set the pGpuFabricProbeInfoKernel to NULL. + // GSP also sends a probe response with failure error code. + // Handling this response causes kernel driver to crash since + // pGpuFabricProbeInfoKernel is already cleared in the kernel. + // This check is added to handle this scenario. + // + NV_CHECK_OR_RETURN(LEVEL_ERROR, pGpu->pGpuFabricProbeInfoKernel != NULL, NV_OK); - pGpuFabricProbeInfo = pGpu->pGpuFabricProbeInfo; + NV_ASSERT(rmGpuGroupLockIsOwner(gpuInstance, GPU_LOCK_GRP_SUBDEVICE, + &gpuMaskUnused)); - pProbeReqMsg = (nvlink_inband_gpu_probe_req_msg_t *)&pGpuFabricProbeInfo-> - sendDataParams.buffer[0]; - pProbeRespMsg = (nvlink_inband_gpu_probe_rsp_msg_t *)&pInbandRcvParams->data[0]; - - if (pProbeRespMsg->msgHdr.requestId != pProbeReqMsg->msgHdr.requestId) - { - NV_PRINTF(LEVEL_INFO, - "GPU%u Probe resp invalid reqId %lld respId %lld\n", - gpuGetInstance(pGpu), - pProbeReqMsg->msgHdr.requestId, - pProbeRespMsg->msgHdr.requestId); - return; - } + NV_ASSERT(pInbandRcvParams != NULL); + + pGpuFabricProbeInfoKernel = pGpu->pGpuFabricProbeInfoKernel; - // Assert reserved in probeResponse are zero - pRsvd = &pProbeRespMsg->probeRsp.reserved[0]; - NV_ASSERT((pRsvd[0] == 0) && portMemCmp(pRsvd, pRsvd + 1, - sizeof(pProbeRespMsg->probeRsp.reserved) - 1) == 0); + pProbeRespMsg = \ + (nvlink_inband_gpu_probe_rsp_msg_t *)&pInbandRcvParams->data[0]; - portMemCopy(&pGpuFabricProbeInfo->probeResponseMsg, - sizeof(pGpuFabricProbeInfo->probeResponseMsg), + portMemCopy(&pGpuFabricProbeInfoKernel->probeResponseMsg, + sizeof(pGpuFabricProbeInfoKernel->probeResponseMsg), pProbeRespMsg, sizeof(*pProbeRespMsg)); @@ -598,166 +437,113 @@ // TODO - Add additional check with versioning to continue with the // timer and send lower version requests // - pGpuFabricProbeInfo->bProbeRespRcvd = NV_TRUE; + pGpuFabricProbeInfoKernel->bProbeRespRcvd = NV_TRUE; - NV_CHECK_OR_RETURN_VOID(LEVEL_ERROR, - _gpuFabricProbeFullSanityCheck(pGpuFabricProbeInfo) == NV_OK); - _gpuFabricProbeSetupGpaRange(pGpu, pGpuFabricProbeInfo); - _gpuFabricProbeSetupFlaRange(pGpu, pGpuFabricProbeInfo); - - // if MC FLA is disabled, reset the fmCaps - if (!pSys->bMulticastFlaEnabled) - { - pGpuFabricProbeInfo->probeResponseMsg.probeRsp.fmCaps &= - ~NVLINK_INBAND_FM_CAPS_MC_TEAM_SETUP_V1; - pGpuFabricProbeInfo->probeResponseMsg.probeRsp.fmCaps &= - ~NVLINK_INBAND_FM_CAPS_MC_TEAM_RELEASE_V1; - } + status = _gpuFabricProbeFullSanityCheck(pGpuFabricProbeInfoKernel); + NV_CHECK_OR_RETURN(LEVEL_ERROR, status == NV_OK, status); + + _gpuFabricProbeSetupGpaRange(pGpu, pGpuFabricProbeInfoKernel); + _gpuFabricProbeSetupFlaRange(pGpu, pGpuFabricProbeInfoKernel); + + return NV_OK; } void gpuFabricProbeSuspend ( - GPU_FABRIC_PROBE_INFO *pGpuFabricProbeInfo + GPU_FABRIC_PROBE_INFO_KERNEL *pGpuFabricProbeInfoKernel ) { OBJGPU *pGpu; - OBJTMR *pTmr; + RM_API *pRmApi; + NV_STATUS status; - if (pGpuFabricProbeInfo == NULL) + if (pGpuFabricProbeInfoKernel == NULL) { return; } - pGpu = pGpuFabricProbeInfo->pGpu; + pGpu = pGpuFabricProbeInfoKernel->pGpu; + pRmApi = GPU_GET_PHYSICAL_RMAPI(pGpu); NV_ASSERT(rmDeviceGpuLockIsOwner(gpuGetInstance(pGpu))); - pTmr = GPU_GET_TIMER(pGpu); - - NV_ASSERT(pGpuFabricProbeInfo->pTmrEvent != NULL); - - if (!gpuFabricProbeIsReceived(pGpuFabricProbeInfo)) - { - tmrEventCancel(pTmr, pGpuFabricProbeInfo->pTmrEvent); - } + NV_CHECK_OK(status, LEVEL_ERROR, + pRmApi->Control(pRmApi, + pGpu->hInternalClient, + pGpu->hInternalSubdevice, + NV2080_CTRL_CMD_INTERNAL_GPU_SUSPEND_FABRIC_PROBE, + NULL, 0)); } NV_STATUS gpuFabricProbeResume ( - GPU_FABRIC_PROBE_INFO *pGpuFabricProbeInfo + GPU_FABRIC_PROBE_INFO_KERNEL *pGpuFabricProbeInfoKernel ) { OBJGPU *pGpu; - NV_STATUS status = NV_OK; + RM_API *pRmApi; + NV2080_CTRL_CMD_INTERNAL_RESUME_GPU_FABRIC_PROBE_INFO_PARAMS params = { 0 }; - if (pGpuFabricProbeInfo == NULL) + if (pGpuFabricProbeInfoKernel == NULL) { return NV_ERR_NOT_SUPPORTED; } - pGpu = pGpuFabricProbeInfo->pGpu; + pGpu = pGpuFabricProbeInfoKernel->pGpu; + pRmApi = GPU_GET_PHYSICAL_RMAPI(pGpu); NV_ASSERT(rmDeviceGpuLockIsOwner(gpuGetInstance(pGpu))); - NV_ASSERT(pGpuFabricProbeInfo->pTmrEvent != NULL); + params.bwMode = pGpuFabricProbeInfoKernel->bwMode; - if (!gpuFabricProbeIsReceived(pGpuFabricProbeInfo)) - { - status = _gpuFabricProbeSchedule(pGpuFabricProbeInfo); - if (status != NV_OK) - { - NV_PRINTF(LEVEL_ERROR, "GPU%u Resume and Sending probe request failed\n", - gpuGetInstance(pGpu)); - } - } + NV_CHECK_OK_OR_RETURN(LEVEL_ERROR, + pRmApi->Control(pRmApi, + pGpu->hInternalClient, + pGpu->hInternalSubdevice, + NV2080_CTRL_CMD_INTERNAL_GPU_RESUME_FABRIC_PROBE, + ¶ms, sizeof(params))); - return status; + return NV_OK; } NV_STATUS gpuFabricProbeStart ( OBJGPU *pGpu, - GPU_FABRIC_PROBE_INFO **ppGpuFabricProbeInfo + GPU_FABRIC_PROBE_INFO_KERNEL **ppGpuFabricProbeInfoKernel ) { NV_STATUS status; - OBJTMR *pTmr = GPU_GET_TIMER(pGpu); - nvlink_inband_gpu_probe_req_msg_t *pProbeReqMsg = NULL; - GPU_FABRIC_PROBE_INFO *pGpuFabricProbeInfo; + GPU_FABRIC_PROBE_INFO_KERNEL *pGpuFabricProbeInfoKernel; NVLINK_INBAND_MSG_CALLBACK inbandMsgCbParams; KernelNvlink *pKernelNvlink = GPU_GET_KERNEL_NVLINK(pGpu); + RM_API *pRmApi = GPU_GET_PHYSICAL_RMAPI(pGpu); + NV2080_CTRL_CMD_INTERNAL_START_GPU_FABRIC_PROBE_INFO_PARAMS params = { 0 }; LOCK_ASSERT_AND_RETURN(rmDeviceGpuLockIsOwner(gpuGetInstance(pGpu))); - // - // TODO - probe versioning - // After retrying the latest version probe for a few times, if GPU - // doesn't receive any response, GPU fallsback to the previous - // version of probe request. This process continues until it - // reaches the lowest possible probe request version - // - // Check if NVSwitch based system. If not return without doing anything if (!gpuFabricProbeIsSupported(pGpu)) { return NV_OK; } - *ppGpuFabricProbeInfo = portMemAllocNonPaged(sizeof(*pGpuFabricProbeInfo)); - NV_ASSERT_OR_RETURN(*ppGpuFabricProbeInfo != NULL, NV_ERR_NO_MEMORY); - - pGpuFabricProbeInfo = *ppGpuFabricProbeInfo; - - portMemSet(pGpuFabricProbeInfo, 0, sizeof(*pGpuFabricProbeInfo)); - - pGpuFabricProbeInfo->pGpu = pGpu; - - status = tmrEventCreate(pTmr, &pGpuFabricProbeInfo->pTmrEvent, - _gpuFabricProbeScheduleWq, NULL, TMR_FLAGS_NONE); - if (status != NV_OK) - { - NV_PRINTF(LEVEL_ERROR, "GPU%u Timer create failure\n", - gpuGetInstance(pGpu)); - goto fail; - } - - pGpuFabricProbeInfo->probeRetryDelay = - pGpu->fabricProbeRetryDelay * GPU_FABRIC_PROBE_SEC_TO_NS; - - ct_assert(sizeof(nvlink_inband_gpu_probe_req_msg_t) <= - sizeof(pGpuFabricProbeInfo->sendDataParams.buffer)); + *ppGpuFabricProbeInfoKernel = portMemAllocNonPaged(sizeof(*pGpuFabricProbeInfoKernel)); + NV_ASSERT_OR_RETURN(*ppGpuFabricProbeInfoKernel != NULL, NV_ERR_NO_MEMORY); - pProbeReqMsg = (nvlink_inband_gpu_probe_req_msg_t *)&pGpuFabricProbeInfo-> - sendDataParams.buffer[0]; + pGpuFabricProbeInfoKernel = *ppGpuFabricProbeInfoKernel; - status = _gpuFabricProbeConstructReq(&pProbeReqMsg->probeReq, pGpu); - if (status != NV_OK) - { - NV_PRINTF(LEVEL_ERROR, "GPU%u Init Probe request failed\n", - gpuGetInstance(pGpu)); - goto fail; - } + portMemSet(pGpuFabricProbeInfoKernel, 0, sizeof(*pGpuFabricProbeInfoKernel)); - status = fabricInitInbandMsgHdr(&pProbeReqMsg->msgHdr, - NVLINK_INBAND_MSG_TYPE_GPU_PROBE_REQ, - sizeof(pProbeReqMsg->probeReq)); - if (status != NV_OK) - { - NV_PRINTF(LEVEL_ERROR, "GPU%u Init of Inband msg hdr failed\n", - gpuGetInstance(pGpu)); - goto fail; - } - - pGpuFabricProbeInfo->sendDataParams.dataSize = sizeof(*pProbeReqMsg); + pGpuFabricProbeInfoKernel->pGpu = pGpu; // Register the receive callback inbandMsgCbParams.messageType = NVLINK_INBAND_MSG_TYPE_GPU_PROBE_RSP; - inbandMsgCbParams.pCallback = _gpuFabricProbeReceive; + inbandMsgCbParams.pCallback = _gpuFabricProbeReceiveKernel; inbandMsgCbParams.wqItemFlags = (OS_QUEUE_WORKITEM_FLAGS_LOCK_SEMA | - OS_QUEUE_WORKITEM_FLAGS_LOCK_GPU_GROUP_SUBDEVICE_RW); + OS_QUEUE_WORKITEM_FLAGS_LOCK_GPU_GROUP_SUBDEVICE_RW); status = knvlinkRegisterInbandCallback(pGpu, pKernelNvlink, &inbandMsgCbParams); @@ -768,30 +554,23 @@ goto fail; } - // - // Queue the probe work item directly (without timer delay). - // A small timer delay is likely to fire and be unable to acquire the lock - // (because we'll still be holding it). The timer event will be used if the - // probe work item needs to be rescheduled with a delay. - // - status = _gpuFabricProbeScheduleWq(pGpu, pTmr, pGpuFabricProbeInfo->pTmrEvent); - if (status != NV_OK) - { - NV_PRINTF(LEVEL_ERROR, "GPU%u failed to schedule probe work item (status = 0x%x)\n", - gpuGetInstance(pGpu), status); - goto fail; - } + pGpuFabricProbeInfoKernel->bwMode = gpumgrGetGpuNvlinkBwMode(); + params.bwMode = pGpuFabricProbeInfoKernel->bwMode; + + // Send IOCTL to start probe + NV_CHECK_OK_OR_GOTO(status, LEVEL_ERROR, + pRmApi->Control(pRmApi, + pGpu->hInternalClient, + pGpu->hInternalSubdevice, + NV2080_CTRL_CMD_INTERNAL_GPU_START_FABRIC_PROBE, + ¶ms, sizeof(params)), + fail); return NV_OK; fail: - if (pGpuFabricProbeInfo->pTmrEvent != NULL) - { - tmrEventDestroy(pTmr, pGpuFabricProbeInfo->pTmrEvent); - } - - portMemFree(pGpuFabricProbeInfo); - pGpu->pGpuFabricProbeInfo = NULL; + portMemFree(pGpuFabricProbeInfoKernel); + pGpu->pGpuFabricProbeInfoKernel = NULL; return status; } @@ -799,39 +578,39 @@ void gpuFabricProbeStop ( - GPU_FABRIC_PROBE_INFO *pGpuFabricProbeInfo + GPU_FABRIC_PROBE_INFO_KERNEL *pGpuFabricProbeInfoKernel ) { OBJGPU *pGpu; - OBJTMR *pTmr; KernelNvlink *pKernelNvlink; + RM_API *pRmApi; - if (pGpuFabricProbeInfo == NULL) + if (pGpuFabricProbeInfoKernel == NULL) { return; } - pGpu = pGpuFabricProbeInfo->pGpu; + pGpu = pGpuFabricProbeInfoKernel->pGpu; NV_ASSERT_OR_RETURN_VOID(rmDeviceGpuLockIsOwner(gpuGetInstance(pGpu))); - pTmr = GPU_GET_TIMER(pGpu); pKernelNvlink = GPU_GET_KERNEL_NVLINK(pGpu); - NV_ASSERT(pKernelNvlink != NULL); // Unregister the receive callback NV_ASSERT_OK(knvlinkUnregisterInbandCallback(pGpu, pKernelNvlink, NVLINK_INBAND_MSG_TYPE_GPU_PROBE_RSP)); - if (pGpuFabricProbeInfo->pTmrEvent != NULL) - { - tmrEventDestroy(pTmr, pGpuFabricProbeInfo->pTmrEvent); - } + pRmApi = GPU_GET_PHYSICAL_RMAPI(pGpu); - portMemFree(pGpuFabricProbeInfo); + NV_ASSERT_OK(pRmApi->Control(pRmApi, + pGpu->hInternalClient, + pGpu->hInternalSubdevice, + NV2080_CTRL_CMD_INTERNAL_GPU_STOP_FABRIC_PROBE, + NULL, 0)); - pGpu->pGpuFabricProbeInfo = NULL; + portMemFree(pGpuFabricProbeInfoKernel); + pGpu->pGpuFabricProbeInfoKernel = NULL; } NvBool @@ -854,3 +633,173 @@ return NV_TRUE; } + +static void +_gpuFabricProbeInvalidate +( + OBJGPU *pGpu +) +{ + GPU_FABRIC_PROBE_INFO_KERNEL *pGpuFabricProbeInfoKernel = + pGpu->pGpuFabricProbeInfoKernel; + KernelNvlink *pKernelNvlink = GPU_GET_KERNEL_NVLINK(pGpu); + FABRIC_VASPACE *pFabricVAS = dynamicCast(pGpu->pFabricVAS, FABRIC_VASPACE); + + pGpuFabricProbeInfoKernel->bProbeRespRcvd = NV_FALSE; + + if (pKernelNvlink != NULL) + knvlinkClearUniqueFabricBaseAddress_HAL(pGpu, pKernelNvlink); + + if (pFabricVAS != NULL) + fabricvaspaceClearUCRange(pFabricVAS); +} + +#define GPU_FABRIC_CHECK_BW_MODE(fmCaps, mode) \ + do \ + { \ + if ((fmCaps & NVLINK_INBAND_FM_CAPS_BW_MODE_##mode) == 0) \ + return NV_ERR_NOT_SUPPORTED; \ + } while (0) + +static NV_STATUS +_gpuFabricProbeUpdateBwMode +( + OBJGPU *pGpu, + NvU8 mode +) +{ + GPU_FABRIC_PROBE_INFO_KERNEL *pGpuFabricProbeInfoKernel = + pGpu->pGpuFabricProbeInfoKernel; + RM_API *pRmApi = GPU_GET_PHYSICAL_RMAPI(pGpu); + + pGpuFabricProbeInfoKernel->bwMode = mode; + + gpuFabricProbeSuspend(pGpuFabricProbeInfoKernel); + + NV_CHECK_OK_OR_RETURN(LEVEL_ERROR, + pRmApi->Control(pRmApi, + pGpu->hInternalClient, + pGpu->hInternalSubdevice, + NV2080_CTRL_CMD_INTERNAL_GPU_INVALIDATE_FABRIC_PROBE, + NULL, 0)); + + _gpuFabricProbeInvalidate(pGpu); + + NV_CHECK_OK_OR_RETURN(LEVEL_ERROR, gpuFabricProbeResume(pGpuFabricProbeInfoKernel)); + + return NV_OK; +} + +NV_STATUS +gpuFabricProbeSetBwMode +( + NvU8 mode +) +{ + NvU32 attachedGpuCount; + NvU32 attachedGpuMask; + NV_STATUS status; + NvU32 gpuIndex; + OBJGPU *pGpu; + + status = gpumgrGetGpuAttachInfo(&attachedGpuCount, &attachedGpuMask); + if (status != NV_OK) + { + return NV_ERR_INVALID_STATE; + } + + // Check if all GPUs belong to NvSwitch + gpuIndex = 0; + for(pGpu = gpumgrGetNextGpu(attachedGpuMask, &gpuIndex); + pGpu != NULL; + pGpu = gpumgrGetNextGpu(attachedGpuMask, &gpuIndex)) + { + if (!gpuFabricProbeIsSupported(pGpu)) + { + // For directed connected system + return NV_OK; + } + } + + // + // Check if all GPUs received fabric probe and + // if the mode is supported on all GPUs. + // + gpuIndex = 0; + for(pGpu = gpumgrGetNextGpu(attachedGpuMask, &gpuIndex); + pGpu != NULL; + pGpu = gpumgrGetNextGpu(attachedGpuMask, &gpuIndex)) + { + if (!gpuFabricProbeIsReceived(pGpu->pGpuFabricProbeInfoKernel) || + !gpuFabricProbeIsSuccess(pGpu->pGpuFabricProbeInfoKernel)) + { + return NV_ERR_NOT_READY; + } + + NvU64 fmCaps = pGpu->pGpuFabricProbeInfoKernel->probeResponseMsg.probeRsp.fmCaps; + switch(mode) + { + case GPU_NVLINK_BW_MODE_MIN: + GPU_FABRIC_CHECK_BW_MODE(fmCaps, MIN); + break; + case GPU_NVLINK_BW_MODE_HALF: + GPU_FABRIC_CHECK_BW_MODE(fmCaps, HALF); + break; + case GPU_NVLINK_BW_MODE_3QUARTER: + GPU_FABRIC_CHECK_BW_MODE(fmCaps, 3QUARTER); + break; + case GPU_NVLINK_BW_MODE_OFF: + return NV_OK; // Don't need to ask FM + default: + break; + } + } + + gpuIndex = 0; + for(pGpu = gpumgrGetNextGpu(attachedGpuMask, &gpuIndex); + pGpu != NULL; + pGpu = gpumgrGetNextGpu(attachedGpuMask, &gpuIndex)) + { + FABRIC_VASPACE *pFabricVAS = dynamicCast(pGpu->pFabricVAS, + FABRIC_VASPACE); + if (pFabricVAS == NULL) + { + continue; + } + + if (fabricvaspaceIsInUse(pFabricVAS)) + { + return NV_ERR_STATE_IN_USE; + } + } + + gpuIndex = 0; + for(pGpu = gpumgrGetNextGpu(attachedGpuMask, &gpuIndex); + pGpu != NULL; + pGpu = gpumgrGetNextGpu(attachedGpuMask, &gpuIndex)) + { + status = _gpuFabricProbeUpdateBwMode(pGpu, mode); + if (status != NV_OK) + { + return status; + } + } + + return NV_OK; +} + +NV_STATUS +gpuFabricProbeGetlinkMaskToBeReduced +( + GPU_FABRIC_PROBE_INFO_KERNEL *pGpuFabricProbeInfoKernel, + NvU32 *linkMaskToBeReduced +) +{ + NV_STATUS status; + + status = _gpuFabricProbeFullSanityCheck(pGpuFabricProbeInfoKernel); + NV_CHECK_OR_RETURN(LEVEL_ERROR, status == NV_OK, status); + + *linkMaskToBeReduced = pGpuFabricProbeInfoKernel->probeResponseMsg.probeRsp.linkMaskToBeReduced; + return NV_OK; +} diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/kernel/gpu/gpu_gspclient.c nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/kernel/gpu/gpu_gspclient.c --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/kernel/gpu/gpu_gspclient.c 2023-10-25 20:21:02.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/kernel/gpu/gpu_gspclient.c 2024-03-05 22:13:27.000000000 +0000 @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 2020-2021 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2020-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -26,6 +26,9 @@ * @brief GSP Client (CPU RM) specific GPU routines reside in this file. */ +// FIXME XXX +#define NVOC_KERNEL_GRAPHICS_MANAGER_H_PRIVATE_ACCESS_ALLOWED + #include "core/core.h" #include "gpu/gpu.h" #include "ctrl/ctrl2080.h" @@ -65,7 +68,7 @@ pGpu->sriovState.vfBarSize[0] = pGSCI->sriovCaps.bar0Size; pGpu->sriovState.vfBarSize[1] = pGSCI->sriovCaps.bar1Size; pGpu->sriovState.vfBarSize[2] = pGSCI->sriovCaps.bar2Size; - + pGpu->sriovState.maxGfid = pGSCI->sriovMaxGfid; // note: pGpu->sriovState.virtualRegPhysOffset is initialized separately @@ -178,6 +181,14 @@ if (FLD_TEST_DRF(2080_GPU_CMD, _GPU_GET_GID_FLAGS, _TYPE, _SHA1, gidFlags)) { GspStaticConfigInfo *pGSCI = GPU_GET_GSP_STATIC_INFO(pGpu); + NvU8 zeroGid[RM_SHA1_GID_SIZE] = { 0 }; + + if (portMemCmp(pGSCI->gidInfo.data, zeroGid, RM_SHA1_GID_SIZE) == 0) + { + NV_PRINTF(LEVEL_ERROR, "GSP Static Info has not been initialized yet for UUID\n"); + return NV_ERR_INVALID_STATE; + } + portMemCopy(pGidData, RM_SHA1_GID_SIZE, pGSCI->gidInfo.data, RM_SHA1_GID_SIZE); return NV_OK; } @@ -199,7 +210,12 @@ void gpuInitProperties_FWCLIENT(OBJGPU *pGpu) { GspStaticConfigInfo *pGSCI = GPU_GET_GSP_STATIC_INFO(pGpu); + pGpu->setProperty(pGpu, PDB_PROP_GPU_IS_MOBILE, pGSCI->bIsMobile); + pGpu->setProperty(pGpu, PDB_PROP_GPU_RTD3_GC6_SUPPORTED, pGSCI->bIsGc6Rtd3Allowed); + pGpu->setProperty(pGpu, PDB_PROP_GPU_RTD3_GCOFF_SUPPORTED, pGSCI->bIsGcOffRtd3Allowed); + pGpu->setProperty(pGpu, PDB_PROP_GPU_IS_UEFI, pGSCI->bIsGpuUefi); + pGpu->setProperty(pGpu, PDB_PROP_GPU_LEGACY_GCOFF_SUPPORTED, pGSCI->bIsGcoffLegacyAllowed); } /*! @@ -246,28 +262,37 @@ RM_API *pRmApi = GPU_GET_PHYSICAL_RMAPI(pGpu); NV2080_CTRL_INTERNAL_GET_DEVICE_INFO_TABLE_PARAMS *pParams; - const NvU32 cmd = NV2080_CTRL_CMD_INTERNAL_GET_DEVICE_INFO_TABLE; if (pGpu->pDeviceInfoTable) // already initialized return NV_OK; - pParams = portMemAllocNonPaged(sizeof(*pParams)); + pParams = portMemAllocNonPaged(sizeof *pParams); NV_ASSERT_OR_RETURN(pParams != NULL, NV_ERR_NO_MEMORY); - status = pRmApi->Control(pRmApi, pGpu->hInternalClient, pGpu->hInternalSubdevice, - cmd, pParams, sizeof(*pParams)); + status = pRmApi->Control(pRmApi, + pGpu->hInternalClient, + pGpu->hInternalSubdevice, + NV2080_CTRL_CMD_INTERNAL_GET_DEVICE_INFO_TABLE, + pParams, + sizeof *pParams); if (status != NV_OK) goto done; if (pParams->numEntries == 0) goto done; - pGpu->pDeviceInfoTable = portMemAllocNonPaged(pParams->numEntries * sizeof(DEVICE_INFO2_TABLE)); - NV_ASSERT_TRUE_OR_GOTO(status, pGpu->pDeviceInfoTable != NULL, NV_ERR_NO_MEMORY, done); + pGpu->pDeviceInfoTable = portMemAllocNonPaged( + pParams->numEntries * (sizeof *pGpu->pDeviceInfoTable)); + NV_ASSERT_TRUE_OR_GOTO(status, + pGpu->pDeviceInfoTable != NULL, + NV_ERR_NO_MEMORY, + done); pGpu->numDeviceInfoEntries = pParams->numEntries; - portMemCopy(pGpu->pDeviceInfoTable, pGpu->numDeviceInfoEntries * sizeof(DEVICE_INFO2_TABLE), - pParams->deviceInfoTable, pParams->numEntries * sizeof(DEVICE_INFO2_TABLE)); + portMemCopy(pGpu->pDeviceInfoTable, + pGpu->numDeviceInfoEntries * (sizeof *pGpu->pDeviceInfoTable), + pParams->deviceInfoTable, + pParams->numEntries * (sizeof pParams->deviceInfoTable[0])); done: portMemFree(pParams); @@ -289,7 +314,7 @@ pGrInfo = pKernelGraphicsManager->legacyKgraphicsStaticInfo.pGrInfo; NV_ASSERT_OR_RETURN(pGrInfo != NULL, 0); - for (i = 0; i < NV_ARRAY_ELEMENTS32(pGrInfo->infoList); i++) + for (i = 0; i < NV_ARRAY_ELEMENTS(pGrInfo->infoList); i++) { if (pGrInfo->infoList[i].index == index) return pGrInfo->infoList[i].data; diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/kernel/gpu/gpu_name_kernel.c nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/kernel/gpu/gpu_name_kernel.c --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/kernel/gpu/gpu_name_kernel.c 2023-10-25 20:21:02.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/kernel/gpu/gpu_name_kernel.c 2024-03-05 22:13:27.000000000 +0000 @@ -39,7 +39,7 @@ NV_ASSERT_OK_OR_RETURN(pRmApi->Control(pRmApi, pGpu->hInternalClient, pGpu->hInternalSubdevice, NV2080_CTRL_CMD_GPU_GET_NAME_STRING, ¶ms, sizeof(params))); - + if (type == NV2080_CTRL_GPU_GET_NAME_STRING_FLAGS_TYPE_ASCII) { portMemCopy(nameStringBuffer, sizeof(params.gpuNameString.ascii), diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/kernel/gpu/gpu_registry.c nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/kernel/gpu/gpu_registry.c --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/kernel/gpu/gpu_registry.c 2023-10-25 20:21:03.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/kernel/gpu/gpu_registry.c 2024-03-05 22:13:27.000000000 +0000 @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 1993-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 1993-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -127,11 +127,14 @@ } } } + } if (pGpu->bSriovEnabled && (IS_GSP_CLIENT(pGpu) || RMCFG_FEATURE_PLATFORM_GSP)) { - pGpu->bVgpuGspPluginOffloadEnabled = NV_TRUE; + { + pGpu->bVgpuGspPluginOffloadEnabled = NV_TRUE; + } } if (osReadRegistryDword(pGpu, NV_REG_STR_RM_CLIENT_RM_ALLOCATED_CTX_BUFFER, &data32) == NV_OK) @@ -168,11 +171,19 @@ pGpu->bSplitVasManagementServerClientRm); } - if (osReadRegistryDword(pGpu, NV_REG_STR_RM_GPU_FABRIC_PROBE, &pGpu->fabricProbeRegKeyOverride) == NV_OK) + if (osReadRegistryDword(pGpu, NV_REG_STR_RM_GPU_FABRIC_PROBE, + &pGpu->fabricProbeRegKeyOverride) == NV_OK) { - pGpu->fabricProbeRegKeyOverride |= DRF_NUM(_REG_STR, _RM_GPU_FABRIC_PROBE, _OVERRIDE, 1); + pGpu->fabricProbeRegKeyOverride |= \ + DRF_NUM(_REG_STR, _RM_GPU_FABRIC_PROBE, _OVERRIDE, 1); } + pGpu->bBf3WarBug4040336Enabled = NV_FALSE; + if (osReadRegistryDword(pGpu, NV_REG_STR_RM_DMA_ADJUST_PEER_MMIO_BF3, + &data32) == NV_OK) + { + pGpu->bBf3WarBug4040336Enabled = (data32 == NV_REG_STR_RM_DMA_ADJUST_PEER_MMIO_BF3_ENABLE); + } return NV_OK; } @@ -186,6 +197,25 @@ OBJGPU *pGpu ) { + NvU32 data32 = 0; + // + // If Hopper CC mode is enabled, move all except few buffers to FB + // + if (((osReadRegistryDword(pGpu, NV_REG_STR_RM_CONFIDENTIAL_COMPUTE, &data32) == NV_OK) && + FLD_TEST_DRF(_REG_STR, _RM_CONFIDENTIAL_COMPUTE, _ENABLED, _YES, data32) && + pGpu->getProperty(pGpu, PDB_PROP_GPU_CC_FEATURE_CAPABLE)) || gpuIsCCEnabledInHw_HAL(pGpu)) + { + + pGpu->instLocOverrides = NV_REG_STR_RM_INST_LOC_ALL_VID; + pGpu->instLocOverrides2 = NV_REG_STR_RM_INST_LOC_ALL_VID; + pGpu->instLocOverrides3 = NV_REG_STR_RM_INST_LOC_ALL_VID; + pGpu->instLocOverrides4 = NV_REG_STR_RM_INST_LOC_ALL_VID; + + // Only FW_SEC_LIC & FLCN UCODE buffers are required to be in NCOH now. These will be moved to VIDMEM eventually. + pGpu->instLocOverrides4 = FLD_SET_DRF(_REG_STR, _RM_INST_LOC_4, _FW_SEC_LIC_COMMAND, _NCOH, pGpu->instLocOverrides4); + pGpu->instLocOverrides4 = FLD_SET_DRF(_REG_STR, _RM_INST_LOC_4, _FLCN_UCODE_BUFFERS, _NCOH, pGpu->instLocOverrides4); + } + else { // // The pGpu fields are initialized to zero. Try to fill them from the diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/kernel/gpu/gpu_resource.c nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/kernel/gpu/gpu_resource.c --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/kernel/gpu/gpu_resource.c 2023-10-25 20:21:03.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/kernel/gpu/gpu_resource.c 2024-03-05 22:13:27.000000000 +0000 @@ -381,6 +381,7 @@ RS_RES_CONTROL_PARAMS_INTERNAL *pParams ) { + NV_ASSERT_OR_RETURN(pGpuResource->pGpu != NULL, NV_ERR_INVALID_STATE); gpuresControlSetup(pParams, pGpuResource); return resControl_IMPL(staticCast(pGpuResource, RsResource), @@ -457,7 +458,7 @@ return status; // Must be device or subdevice - if (!dynamicCast(*ppGpuResource, Device) && + if (!dynamicCast(*ppGpuResource, Device) && !dynamicCast(*ppGpuResource, Subdevice)) { return NV_ERR_INVALID_OBJECT_HANDLE; diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/kernel/gpu/gpu_rmapi.c nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/kernel/gpu/gpu_rmapi.c --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/kernel/gpu/gpu_rmapi.c 2023-10-25 20:21:03.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/kernel/gpu/gpu_rmapi.c 2024-03-05 22:13:27.000000000 +0000 @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 1993-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 1993-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -503,9 +503,19 @@ for (i = 0; i < pGpu->numSubdeviceBackReferences; i++) { Subdevice *pSubdevice = pGpu->pSubdeviceBackReferences[i]; + + // + // We've seen cases where pSubdevice is NULL implying that the + // pSubdeviceBackReferences[] array is being modified during this loop. + // Adding a NULL pointer check here is only a stopgap. See bug 3892382. + // NV_ASSERT_OR_RETURN_VOID(pSubdevice != NULL); + INotifier *pNotifier = staticCast(pSubdevice, INotifier); + if (inotifyGetNotificationShare(pNotifier) == NULL) + continue; + GPU_RES_SET_THREAD_BC_STATE(pSubdevice); // @@ -637,6 +647,20 @@ return NV_FALSE; } +static NV_STATUS +_gpuConvertPid +( + RmClient *pClient, + NvU32 *pNsPid +) +{ + if (pClient->pOsPidInfo != NULL) + return osFindNsPid(pClient->pOsPidInfo, pNsPid); + + *pNsPid = pClient->ProcID; + return NV_OK; +} + // // Searches through clients to find processes with clients that have // allocated an ElementType of class, defined by elementID. The return values @@ -663,6 +687,7 @@ RmClient *pClient; RsClient *pRsClient; RsResourceRef *pResourceRef; + NV_STATUS status; NV_ASSERT_OR_RETURN((pPidArray != NULL), NV_ERR_INVALID_ARGUMENT); NV_ASSERT_OR_RETURN((pPidArrayCount != NULL), NV_ERR_INVALID_ARGUMENT); @@ -772,8 +797,15 @@ } if (elementInClient) { - pPidArray[pidcount] = pClient->ProcID; - pidcount++; + status = _gpuConvertPid(pClient, &pPidArray[pidcount]); + if (status == NV_OK) + { + pidcount++; + } + else if (status != NV_ERR_OBJECT_NOT_FOUND) + { + return status; + } if (pidcount == NV2080_CTRL_GPU_GET_PIDS_MAX_COUNT) { @@ -852,18 +884,39 @@ && !(hypervisorIsVgxHyper() && (pResourceRef->externalClassId == NV01_MEMORY_HW_RESOURCES))) || (bIsGuestProcess && (memdescGetFlag(pMemory->pMemDesc, MEMDESC_FLAGS_GUEST_ALLOCATED)) && (pMemory->Type != NVOS32_TYPE_UNUSED)))) { + NvBool bIsMemProtected = NV_FALSE; + + bIsMemProtected = gpuIsCCorApmFeatureEnabled(pMemory->pMemDesc->pGpu) && + (pMemory->Flags & NVOS32_ALLOC_FLAGS_PROTECTED); + if (bIsMemProtected) + { + NV_ASSERT(!memdescGetFlag(pMemory->pMemDesc, + MEMDESC_FLAGS_ALLOC_IN_UNPROTECTED_MEMORY)); + } if (pMemory->pMemDesc->DupCount == 1) { pData->memPrivate += pMemory->Length; + if (bIsMemProtected) + { + pData->protectedMemPrivate += pMemory->Length; + } } else if (pMemory->isMemDescOwner) { pData->memSharedOwned += pMemory->Length; + if (bIsMemProtected) + { + pData->protectedMemSharedOwned += pMemory->Length; + } } else { pData->memSharedDuped += pMemory->Length; + if (bIsMemProtected) + { + pData->protectedMemSharedDuped += pMemory->Length; + } } } } diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/kernel/gpu/gpu_suspend.c nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/kernel/gpu/gpu_suspend.c --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/kernel/gpu/gpu_suspend.c 2023-10-25 20:21:03.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/kernel/gpu/gpu_suspend.c 2024-03-05 22:13:27.000000000 +0000 @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 2000-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2000-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -40,6 +40,7 @@ #include "core/thread_state.h" #include "vgpu/rpc.h" #include "gpu/mem_sys/kern_mem_sys.h" +#include // // Helper functions @@ -71,18 +72,57 @@ if (IS_GSP_CLIENT(pGpu)) { - NV_ASSERT_OK_OR_GOTO(status, memmgrSavePowerMgmtState(pGpu, pMemoryManager), done); + // FB remains alive for GC6 cycle + if (!IS_GPU_GC6_STATE_ENTERING(pGpu)) + { + NV_ASSERT_OK_OR_GOTO(status, memmgrSavePowerMgmtState(pGpu, pMemoryManager), done); + } + + KernelGsp *pKernelGsp = GPU_GET_KERNEL_GSP(pGpu); + NV_RM_RPC_UNLOADING_GUEST_DRIVER(pGpu, status, NV_TRUE, IS_GPU_GC6_STATE_ENTERING(pGpu), newLevel); if (status != NV_OK) goto done; - kpmuFreeLibosLoggingStructures(pGpu, GPU_GET_KERNEL_PMU(pGpu)); + // Wait for GSP-RM to suspend + kgspWaitForProcessorSuspend_HAL(pGpu, pKernelGsp); + // Dump GSP-RM logs before resetting and invoking FWSEC-SB + kgspDumpGspLogs(pKernelGsp, NV_FALSE); + + if (!IS_GPU_GC6_STATE_ENTERING(pGpu)) + { + // Because of COT, RM cannot reset GSP-RISCV. + if (!(pGpu->getProperty(pGpu, PDB_PROP_GPU_IS_COT_ENABLED))) + { + kflcnReset_HAL(pGpu, staticCast(pKernelGsp, KernelFalcon)); + } + + // Invoke FWSEC-SB to load back PreOsApps. + status = kgspExecuteFwsecSb_HAL(pGpu, pKernelGsp, pKernelGsp->pFwsecUcode); + if (status != NV_OK) + { + NV_PRINTF(LEVEL_ERROR, "failed to execute FWSEC-SB for PreOsApps\n"); + goto done; + } + + kpmuFreeLibosLoggingStructures(pGpu, GPU_GET_KERNEL_PMU(pGpu)); + + { + NV_CHECK_OK_OR_GOTO(status, LEVEL_ERROR, + kgspSavePowerMgmtState_HAL(pGpu, pKernelGsp), done); + } + } + else + { + NV_CHECK_OK_OR_GOTO(status, LEVEL_ERROR, + kgspExecuteBooterUnloadIfNeeded_HAL(pGpu, pKernelGsp, 0), done); + } } done: - if (status != NV_OK) + if ((status != NV_OK) && !IS_GPU_GC6_STATE_ENTERING(pGpu)) { memmgrFreeFbsrMemory(pGpu, pMemoryManager); } @@ -133,14 +173,7 @@ // kmemsysProgramSysmemFlushBuffer_HAL(pGpu, GPU_GET_KERNEL_MEMORY_SYSTEM(pGpu)); - KernelGsp *pKernelGsp = GPU_GET_KERNEL_GSP(pGpu); - - status = kpmuInitLibosLoggingStructures(pGpu, GPU_GET_KERNEL_PMU(pGpu)); - if (status != NV_OK) - { - NV_PRINTF(LEVEL_ERROR, "cannot init libOS PMU logging structures: 0x%x\n", status); - goto done; - } + KernelGsp *pKernelGsp = GPU_GET_KERNEL_GSP(pGpu); GSP_SR_INIT_ARGUMENTS gspSrInitArgs; @@ -150,21 +183,38 @@ kgspPopulateGspRmInitArgs(pGpu, pKernelGsp, &gspSrInitArgs); - // - // GSP-TODO - Remove following line after the following is implemented - // JIRA CORERM-4274 - Open RM - Suspend & Resume - GSP Heap and FW save/restore - // - // Reset timeout due to long memmgrRestorePowerMgmtState() through BAR0 Window - // - threadStateResetTimeout(pGpu); - - status = kgspExecuteSequencerCommand_HAL(pGpu, pKernelGsp, GSP_SEQ_BUF_OPCODE_CORE_RESUME, NULL, 0); + // Wait for GFW_BOOT status + status = kgspWaitForGfwBootOk_HAL(pGpu, pKernelGsp); if (status != NV_OK) { - NV_PRINTF(LEVEL_ERROR, "cannot resume riscv/gsp: 0x%x\n", status); goto done; } + if (!IS_GPU_GC6_STATE_EXITING(pGpu)) + { + // Not called when kgspShouldBootWithBooter_HAL() is called and returns NV_FALSE + { + NV_CHECK_OK_OR_GOTO(status, LEVEL_ERROR, + kgspRestorePowerMgmtState_HAL(pGpu, pKernelGsp), done); + } + + status = kpmuInitLibosLoggingStructures(pGpu, GPU_GET_KERNEL_PMU(pGpu)); + if (status != NV_OK) + { + NV_PRINTF(LEVEL_ERROR, "cannot init libOS PMU logging structures: 0x%x\n", status); + goto done; + } + } + else + { + status = kgspExecuteBooterLoad_HAL(pGpu, pKernelGsp, 0); + if (status != NV_OK) + { + NV_PRINTF(LEVEL_ERROR, "cannot resume riscv/gsp from GC6: 0x%x\n", status); + goto done; + } + } + status = kgspWaitForRmInitDone(pGpu, pKernelGsp); if (status != NV_OK) { @@ -172,6 +222,22 @@ goto done; } } + else + { + // Boot GSP-FMC for monolithic RM + KernelFsp *pKernelFsp = GPU_GET_KERNEL_FSP(pGpu); + if ((pKernelFsp != NULL) && !IS_VIRTUAL(pGpu)) + { + pKernelFsp->setProperty(pKernelFsp, PDB_PROP_KFSP_BOOT_COMMAND_OK, NV_FALSE); + + status = kfspSendBootCommands_HAL(pGpu, pKernelFsp); + if (status != NV_OK) + { + NV_PRINTF(LEVEL_ERROR, "FSP boot command failed during resume.\n"); + goto done; + } + } + } // This is a no-op in CPU-RM NV_ASSERT_OK_OR_GOTO(status, gpuPowerManagementResumePreLoadPhysical(pGpu, oldLevel, flags), done); @@ -189,7 +255,10 @@ NV_PRINTF(LEVEL_NOTICE, "Adapter now in D0 state\n"); done: - memmgrFreeFbsrMemory(pGpu, pMemoryManager); + if (!IS_GPU_GC6_STATE_EXITING(pGpu)) + { + memmgrFreeFbsrMemory(pGpu, pMemoryManager); + } return status; } @@ -198,7 +267,7 @@ gpuEnterStandby_IMPL(OBJGPU *pGpu) { OBJSYS *pSys = SYS_GET_INSTANCE(); - POBJPFM pPfm = SYS_GET_PFM(pSys); + OBJPFM *pPfm = SYS_GET_PFM(pSys); NV_STATUS suspendStatus; if ((pPfm != NULL) && pPfm->getProperty(pPfm, PDB_PROP_PFM_SUPPORTS_ACPI)) @@ -241,7 +310,7 @@ gpuResumeFromStandby_IMPL(OBJGPU *pGpu) { OBJSYS *pSys = SYS_GET_INSTANCE(); - POBJPFM pPfm = SYS_GET_PFM(pSys); + OBJPFM *pPfm = SYS_GET_PFM(pSys); NV_STATUS resumeStatus; NvU32 state = 0; @@ -288,7 +357,7 @@ NV_STATUS gpuEnterHibernate_IMPL(OBJGPU *pGpu) { OBJSYS *pSys = SYS_GET_INSTANCE(); - POBJPFM pPfm = SYS_GET_PFM(pSys); + OBJPFM *pPfm = SYS_GET_PFM(pSys); NV_STATUS suspendStatus; if ((pPfm != NULL) && pPfm->getProperty(pPfm, PDB_PROP_PFM_SUPPORTS_ACPI)) @@ -321,7 +390,7 @@ NV_STATUS gpuResumeFromHibernate_IMPL(OBJGPU *pGpu) { OBJSYS *pSys = SYS_GET_INSTANCE(); - POBJPFM pPfm = SYS_GET_PFM(pSys); + OBJPFM *pPfm = SYS_GET_PFM(pSys); NV_STATUS resumeStatus; NV_PRINTF(LEVEL_INFO, diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/kernel/gpu/gpu_timeout.c nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/kernel/gpu/gpu_timeout.c --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/kernel/gpu/gpu_timeout.c 2023-10-25 20:21:03.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/kernel/gpu/gpu_timeout.c 2024-03-05 22:13:28.000000000 +0000 @@ -314,8 +314,11 @@ osGetCurrentTick(&timeInNs); if (timeInNs >= pTimeout->timeout) { - NV_PRINTF(LEVEL_INFO, "OS elapsed %llx >= %llx\n", - timeInNs, pTimeout->timeout); + if (!(pTimeout->flags & GPU_TIMEOUT_FLAGS_BYPASS_JOURNAL_LOG)) + { + NV_PRINTF(LEVEL_INFO, "OS elapsed %llx >= %llx\n", + timeInNs, pTimeout->timeout); + } status = NV_ERR_TIMEOUT; } } @@ -345,7 +348,10 @@ if (pTimeout->timeout == 0) { - NV_PRINTF(LEVEL_INFO, "OS timeout == 0\n"); + if (!(pTimeout->flags & GPU_TIMEOUT_FLAGS_BYPASS_JOURNAL_LOG)) + { + NV_PRINTF(LEVEL_INFO, "OS timeout == 0\n"); + } status = NV_ERR_TIMEOUT; } } diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/kernel/gpu/gpu_user_shared_data.c nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/kernel/gpu/gpu_user_shared_data.c --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/kernel/gpu/gpu_user_shared_data.c 2023-10-25 20:21:03.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/kernel/gpu/gpu_user_shared_data.c 2024-03-05 22:13:28.000000000 +0000 @@ -28,6 +28,7 @@ #include "rmapi/client.h" #include "rmapi/rmapi.h" #include "class/cl00de.h" +#include "class/cl003e.h" // NV01_MEMORY_SYSTEM NV_STATUS gpushareddataConstruct_IMPL @@ -38,187 +39,56 @@ ) { NV_STATUS status = NV_OK; - OBJGPU *pGpu = GPU_RES_GET_GPU(pData); - MEMORY_DESCRIPTOR *pMemDesc = NULL; - NV00DE_SHARED_DATA *pSharedData; + Memory *pMemory = staticCast(pData, Memory); - if (pGpu->userSharedData.pMemDesc == NULL) + // pGpu is initialied in the Memory class constructor + OBJGPU *pGpu = pMemory->pGpu; + MEMORY_DESCRIPTOR **ppMemDesc = &(pGpu->userSharedData.pMemDesc); + + if (RS_IS_COPY_CTOR(pParams)) + { + return NV_OK; + } + + if (*ppMemDesc == NULL) { // Create a kernel-side mapping for writing the data if one is not already present - status = memdescCreate(&pMemDesc, pGpu, sizeof(NV00DE_SHARED_DATA), 0, NV_TRUE, ADDR_SYSMEM, - NV_MEMORY_WRITECOMBINED, MEMDESC_FLAGS_USER_READ_ONLY); - if (status != NV_OK) - { - NV_PRINTF(LEVEL_ERROR, "memdescCreate failed - status=0x%08x\n", status); - return NV_ERR_INSUFFICIENT_RESOURCES; - } - - status = memdescAlloc(pMemDesc); - if (status != NV_OK) - { - memdescDestroy(pMemDesc); - NV_PRINTF(LEVEL_ERROR, "memdescAlloc failed - status=0x%08x\n", status); - return status; - } - - status = memdescMap(pMemDesc, 0, pMemDesc->Size, - NV_TRUE, NV_PROTECT_READABLE, - &pGpu->userSharedData.pMapBuffer, - &pGpu->userSharedData.pMapBufferPriv); - if (status != NV_OK) - { - memdescFree(pMemDesc); - memdescDestroy(pMemDesc); - NV_PRINTF(LEVEL_ERROR, "memdescMap failed - status=0x%08x\n", status); - return status; - } + NV_ASSERT_OK_OR_RETURN(memdescCreate(ppMemDesc, pGpu, sizeof(NV00DE_SHARED_DATA), 0, NV_TRUE, + ADDR_SYSMEM, NV_MEMORY_CACHED, MEMDESC_FLAGS_USER_READ_ONLY)); - pGpu->userSharedData.pMemDesc = pMemDesc; + NV_ASSERT_OK_OR_GOTO(status, memdescAlloc(*ppMemDesc), err); - pSharedData = (NV00DE_SHARED_DATA*)(pGpu->userSharedData.pMapBuffer); - portMemSet(pSharedData, 0, sizeof(*pSharedData)); + + NV_ASSERT_OK_OR_GOTO(status, + memdescMap(*ppMemDesc, 0, (*ppMemDesc)->Size, + NV_TRUE, NV_PROTECT_READ_WRITE, + &pGpu->userSharedData.pMapBuffer, + &pGpu->userSharedData.pMapBufferPriv), + err); + + portMemSet(pGpu->userSharedData.pMapBuffer, 0, sizeof(NV00DE_SHARED_DATA)); // Initial write from cached data - gpushareddataWriteFinish(pGpu); + gpuUpdateUserSharedData_KERNEL(pGpu); } + NV_ASSERT_OK_OR_RETURN(memConstructCommon(pMemory, + NV01_MEMORY_SYSTEM, 0, *ppMemDesc, 0, NULL, 0, 0, 0, 0, + NVOS32_MEM_TAG_NONE, NULL)); memdescAddRef(pGpu->userSharedData.pMemDesc); - return NV_OK; -} - -void -gpushareddataDestruct_IMPL -( - GpuUserSharedData *pData -) -{ - OBJGPU *pGpu = GPU_RES_GET_GPU(pData); - MEMORY_DESCRIPTOR *pMemDesc = pGpu->userSharedData.pMemDesc; - - memdescRemoveRef(pMemDesc); - - if (pMemDesc->RefCount == 1) - { - // Clean up kernel-side mapping if this is the last mapping for this GPU - memdescUnmap(pMemDesc, - NV_TRUE, - pGpu->userSharedData.processId, - pGpu->userSharedData.pMapBuffer, - pGpu->userSharedData.pMapBufferPriv); - - memdescFree(pMemDesc); - memdescDestroy(pMemDesc); - pGpu->userSharedData.pMemDesc = NULL; - pGpu->userSharedData.pMapBuffer = NULL; - pGpu->userSharedData.pMapBufferPriv = NULL; - } -} - -NV_STATUS -gpushareddataMap_IMPL -( - GpuUserSharedData *pData, - CALL_CONTEXT *pCallContext, - RS_CPU_MAP_PARAMS *pParams, - RsCpuMapping *pCpuMapping -) -{ - NV_STATUS status; - NvBool bKernel; - RmClient *pClient = dynamicCast(pCallContext->pClient, RmClient); - OBJGPU *pGpu = GPU_RES_GET_GPU(pData); - - status = rmapiValidateKernelMapping(rmclientGetCachedPrivilege(pClient), - pCpuMapping->flags, - &bKernel); - if (status != NV_OK) - return status; - - // Only support read-only, fail early if writeable - if (pCpuMapping->pPrivate->protect & NV_PROTECT_WRITEABLE) - return NV_ERR_INVALID_PARAMETER; - - pCpuMapping->processId = osGetCurrentProcess(); - - // Map entire buffer (no offsets supported) - status = memdescMap(pGpu->userSharedData.pMemDesc, - 0, - pGpu->userSharedData.pMemDesc->Size, - NV_FALSE, - pCpuMapping->pPrivate->protect, - &pCpuMapping->pLinearAddress, - &pCpuMapping->pPrivate->pPriv); +err: + memdescFree(*ppMemDesc); + memdescDestroy(*ppMemDesc); + *ppMemDesc = NULL; return status; } -NV_STATUS -gpushareddataUnmap_IMPL -( - GpuUserSharedData *pData, - CALL_CONTEXT *pCallContext, - RsCpuMapping *pCpuMapping -) +NvBool +gpushareddataCanCopy_IMPL(GpuUserSharedData *pData) { - NV_STATUS status; - NvBool bKernel; - RmClient *pClient = dynamicCast(pCallContext->pClient, RmClient); - OBJGPU *pGpu = GPU_RES_GET_GPU(pData); - - if (pGpu->userSharedData.pMemDesc == NULL) - return NV_ERR_INVALID_OBJECT; - - status = rmapiValidateKernelMapping(rmclientGetCachedPrivilege(pClient), - pCpuMapping->flags, - &bKernel); - if (status != NV_OK) - return status; - - memdescUnmap(pGpu->userSharedData.pMemDesc, - bKernel, - pCpuMapping->processId, - pCpuMapping->pLinearAddress, - pCpuMapping->pPrivate->pPriv); - - return NV_OK; -} - -NV_STATUS -gpushareddataGetMapAddrSpace_IMPL -( - GpuUserSharedData *pData, - CALL_CONTEXT *pCallContext, - NvU32 mapFlags, - NV_ADDRESS_SPACE *pAddrSpace -) -{ - OBJGPU *pGpu = GPU_RES_GET_GPU(pData); - NV_ADDRESS_SPACE addrSpace; - - if (pGpu->userSharedData.pMemDesc == NULL) - return NV_ERR_INVALID_OBJECT; - - NV_ASSERT_OK_OR_RETURN(rmapiGetEffectiveAddrSpace(pGpu, pGpu->userSharedData.pMemDesc, mapFlags, &addrSpace)); - - if (pAddrSpace != NULL) - *pAddrSpace = addrSpace; - - return NV_OK; -} - -NV_STATUS -gpushareddataGetMemoryMappingDescriptor_IMPL -( - GpuUserSharedData *pData, - MEMORY_DESCRIPTOR **ppMemDesc -) -{ - OBJGPU *pGpu = GPU_RES_GET_GPU(pData); - - *ppMemDesc = pGpu->userSharedData.pMemDesc; - - return NV_OK; + return NV_TRUE; } NV00DE_SHARED_DATA * gpushareddataWriteStart(OBJGPU *pGpu) @@ -228,6 +98,11 @@ void gpushareddataWriteFinish(OBJGPU *pGpu) { + gpuUpdateUserSharedData_HAL(pGpu); +} + +void gpuUpdateUserSharedData_KERNEL(OBJGPU *pGpu) +{ NV00DE_SHARED_DATA *pSharedData = (NV00DE_SHARED_DATA*)(pGpu->userSharedData.pMapBuffer); const NvU32 data_offset = sizeof(pSharedData->seq); const NvU32 data_size = sizeof(NV00DE_SHARED_DATA) - data_offset; diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/kernel/gpu/gr/arch/maxwell/kgraphics_gm200.c nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/kernel/gpu/gr/arch/maxwell/kgraphics_gm200.c --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/kernel/gpu/gr/arch/maxwell/kgraphics_gm200.c 2023-10-25 20:21:03.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/kernel/gpu/gr/arch/maxwell/kgraphics_gm200.c 2024-03-05 22:13:28.000000000 +0000 @@ -21,6 +21,8 @@ * DEALINGS IN THE SOFTWARE. */ +#define NVOC_KERNEL_GRAPHICS_H_PRIVATE_ACCESS_ALLOWED + #include "kernel/gpu/gr/kernel_graphics.h" #include "kernel/gpu/mem_mgr/mem_mgr.h" @@ -165,6 +167,11 @@ cbAllocFlags | MEMDESC_FLAGS_GPU_PRIVILEGED | MEMDESC_FLAGS_HIGH_PRIORITY)); memdescSetGpuCacheAttrib(*ppMemDesc, NV_MEMORY_CACHED); + if ((cbAllocFlags & MEMDESC_FLAGS_OWNED_BY_CTX_BUF_POOL) != 0) + { + memmgrSetMemDescPageSize_HAL(pGpu, pMemoryManager, *ppMemDesc, AT_GPU, RM_ATTR_PAGE_SIZE_4KB); + NV_ASSERT_OK_OR_RETURN(memdescSetCtxBufPool(*ppMemDesc, pCtxBufPool)); + } NV_CHECK_OK_OR_RETURN(LEVEL_ERROR, memdescAllocList(*ppMemDesc, pCtxAttr[GR_GLOBALCTX_BUFFER_BUNDLE_CB].pAllocList)); } @@ -185,6 +192,11 @@ cbAllocFlags | MEMDESC_FLAGS_GPU_PRIVILEGED)); memdescSetGpuCacheAttrib(*ppMemDesc, NV_MEMORY_CACHED); + if ((cbAllocFlags & MEMDESC_FLAGS_OWNED_BY_CTX_BUF_POOL) != 0) + { + memmgrSetMemDescPageSize_HAL(pGpu, pMemoryManager, *ppMemDesc, AT_GPU, RM_ATTR_PAGE_SIZE_4KB); + NV_ASSERT_OK_OR_RETURN(memdescSetCtxBufPool(*ppMemDesc, pCtxBufPool)); + } NV_CHECK_OK_OR_RETURN(LEVEL_ERROR, memdescAllocList(*ppMemDesc, pCtxAttr[GR_GLOBALCTX_BUFFER_PAGEPOOL].pAllocList)); } @@ -205,6 +217,11 @@ cbAllocFlags | MEMDESC_FLAGS_HIGH_PRIORITY)); memdescSetGpuCacheAttrib(*ppMemDesc, NV_MEMORY_CACHED); + if ((cbAllocFlags & MEMDESC_FLAGS_OWNED_BY_CTX_BUF_POOL) != 0) + { + memmgrSetMemDescPageSize_HAL(pGpu, pMemoryManager, *ppMemDesc, AT_GPU, RM_ATTR_PAGE_SIZE_4KB); + NV_ASSERT_OK_OR_RETURN(memdescSetCtxBufPool(*ppMemDesc, pCtxBufPool)); + } NV_CHECK_OK_OR_RETURN(LEVEL_ERROR, memdescAllocList(*ppMemDesc, pCtxAttr[GR_GLOBALCTX_BUFFER_ATTRIBUTE_CB].pAllocList)); memdescSetName(pGpu, *ppMemDesc, NV_RM_SURF_NAME_GR_CIRCULAR_BUFFER, NULL); @@ -231,12 +248,15 @@ pCtxAttr[GR_GLOBALCTX_BUFFER_PRIV_ACCESS_MAP].cpuAttr, flags)); - // - // Force page size to 4KB, we can change this later when RM - // access method support 64k pages - // - memmgrSetMemDescPageSize_HAL(pGpu, pMemoryManager, *ppMemDesc, AT_GPU, RM_ATTR_PAGE_SIZE_4KB); - NV_ASSERT_OK_OR_RETURN(memdescSetCtxBufPool(*ppMemDesc, pCtxBufPool)); + if ((flags & MEMDESC_FLAGS_OWNED_BY_CTX_BUF_POOL) != 0) + { + // + // Force page size to 4KB, we can change this later when RM + // access method support 64k pages + // + memmgrSetMemDescPageSize_HAL(pGpu, pMemoryManager, *ppMemDesc, AT_GPU, RM_ATTR_PAGE_SIZE_4KB); + NV_ASSERT_OK_OR_RETURN(memdescSetCtxBufPool(*ppMemDesc, pCtxBufPool)); + } NV_CHECK_OK_OR_RETURN(LEVEL_ERROR, memdescAllocList(*ppMemDesc, pCtxAttr[GR_GLOBALCTX_BUFFER_PRIV_ACCESS_MAP].pAllocList)); } @@ -259,12 +279,15 @@ pCtxAttr[GR_GLOBALCTX_BUFFER_UNRESTRICTED_PRIV_ACCESS_MAP].cpuAttr, flags)); - // - // Force page size to 4KB, we can change this later when RM - // access method support 64k pages - // - memmgrSetMemDescPageSize_HAL(pGpu, pMemoryManager, *ppMemDesc, AT_GPU, RM_ATTR_PAGE_SIZE_4KB); - NV_ASSERT_OK_OR_RETURN(memdescSetCtxBufPool(*ppMemDesc, pCtxBufPool)); + if ((flags & MEMDESC_FLAGS_OWNED_BY_CTX_BUF_POOL) != 0) + { + // + // Force page size to 4KB, we can change this later when RM + // access method support 64k pages + // + memmgrSetMemDescPageSize_HAL(pGpu, pMemoryManager, *ppMemDesc, AT_GPU, RM_ATTR_PAGE_SIZE_4KB); + NV_ASSERT_OK_OR_RETURN(memdescSetCtxBufPool(*ppMemDesc, pCtxBufPool)); + } NV_CHECK_OK_OR_RETURN(LEVEL_ERROR, memdescAllocList(*ppMemDesc, diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/kernel/gpu/gr/arch/pascal/kgraphics_gp100.c nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/kernel/gpu/gr/arch/pascal/kgraphics_gp100.c --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/kernel/gpu/gr/arch/pascal/kgraphics_gp100.c 2023-10-25 20:21:03.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/kernel/gpu/gr/arch/pascal/kgraphics_gp100.c 2024-03-05 22:13:28.000000000 +0000 @@ -21,7 +21,10 @@ * DEALINGS IN THE SOFTWARE. */ +#define NVOC_KERNEL_GRAPHICS_H_PRIVATE_ACCESS_ALLOWED + #include "kernel/gpu/gr/kernel_graphics.h" +#include "kernel/gpu/mem_mgr/mem_mgr.h" #include "kernel/gpu/mig_mgr/kernel_mig_manager.h" #include "kernel/gpu/intr/engine_idx.h" #include "nvRmReg.h" @@ -64,6 +67,15 @@ kgraphicsSetCtxswLoggingSupported(pGpu, pKernelGraphics, bLog); } + // + // CTXSW logging is not supported when HCC prod settings are enabled. + // However, the same is supported when HCC is enabled in devtools mode + // + if (gpuIsCCFeatureEnabled(pGpu)) + { + kgraphicsSetCtxswLoggingSupported(pGpu, pKernelGraphics, NV_FALSE); + } + fecsSetRecordsPerIntr(pGpu, pKernelGraphics, NV_REG_STR_RM_CTXSW_LOG_RECORDS_PER_INTR_DEFAULT); if (osReadRegistryDword(pGpu, NV_REG_STR_RM_CTXSW_LOG_RECORDS_PER_INTR, &data) == NV_OK) { @@ -90,7 +102,6 @@ { extern NV_STATUS kgraphicsAllocGrGlobalCtxBuffers_GM200(OBJGPU *pGpu, KernelGraphics *pKernelGraphics, NvU32 gfid, KernelGraphicsContext *pKernelGraphicsContext); GR_GLOBALCTX_BUFFERS *pCtxBuffers; - NvU64 allocFlags = MEMDESC_FLAGS_NONE; NV_STATUS status; CTX_BUF_POOL_INFO *pCtxBufPool; const KGRAPHICS_STATIC_INFO *pKernelGraphicsStaticInfo; @@ -113,13 +124,6 @@ if (pCtxBuffers->bAllocated) return NV_OK; - // check for allocating local buffers in VPR memory (don't want for global memory) - if ( - pKernelGraphicsContextUnicast->bVprChannel) - allocFlags |= MEMDESC_ALLOC_FLAGS_PROTECTED; - - // If allocated per channel, ensure allocations goes into Suballocator if available - allocFlags |= MEMDESC_FLAGS_OWNED_BY_CURRENT_DEVICE; } else { @@ -128,12 +132,6 @@ RM_ENGINE_TYPE_GR(pKernelGraphics->instance), &pCtxBufPool)); } - // Don't use context buffer pool for VF allocations managed by host RM. - if (ctxBufPoolIsSupported(pGpu) && (pCtxBufPool != NULL)) - { - allocFlags |= MEMDESC_FLAGS_OWNED_BY_CTX_BUF_POOL; - } - pKernelGraphicsStaticInfo = kgraphicsGetStaticInfo(pGpu, pKernelGraphics); NV_ASSERT_OR_RETURN(pKernelGraphicsStaticInfo != NULL, NV_ERR_INVALID_STATE); NV_ASSERT_OR_RETURN(pKernelGraphicsStaticInfo->pContextBuffersInfo != NULL, NV_ERR_INVALID_STATE); @@ -218,7 +216,13 @@ if ((*ppMemDesc)->_addressSpace == ADDR_FBMEM) memdescSetGpuCacheAttrib(*ppMemDesc, NV_MEMORY_CACHED); - NV_ASSERT_OK_OR_RETURN(memdescSetCtxBufPool(*ppMemDesc, pCtxBufPool)); + if ((allocFlags & MEMDESC_FLAGS_OWNED_BY_CTX_BUF_POOL) != 0) + { + MemoryManager *pMemoryManager = GPU_GET_MEMORY_MANAGER(pGpu); + + memmgrSetMemDescPageSize_HAL(pGpu, pMemoryManager, *ppMemDesc, AT_GPU, RM_ATTR_PAGE_SIZE_4KB); + NV_ASSERT_OK_OR_RETURN(memdescSetCtxBufPool(*ppMemDesc, pCtxBufPool)); + } NV_CHECK_OK_OR_RETURN(LEVEL_ERROR, memdescAllocList(*ppMemDesc, pCtxAttr[GR_GLOBALCTX_BUFFER_FECS_EVENT].pAllocList)); diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/kernel/gpu/gr/arch/turing/kgraphics_tu102.c nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/kernel/gpu/gr/arch/turing/kgraphics_tu102.c --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/kernel/gpu/gr/arch/turing/kgraphics_tu102.c 2023-10-25 20:21:04.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/kernel/gpu/gr/arch/turing/kgraphics_tu102.c 2024-03-05 22:13:28.000000000 +0000 @@ -21,7 +21,10 @@ * DEALINGS IN THE SOFTWARE. */ +#define NVOC_KERNEL_GRAPHICS_H_PRIVATE_ACCESS_ALLOWED + #include "kernel/gpu/gr/kernel_graphics.h" +#include "kernel/gpu/mem_mgr/mem_mgr.h" #include "ctrl/ctrl0080/ctrl0080fifo.h" @@ -52,6 +55,7 @@ NvU32 rtvcbBufferAlign; NV_STATUS status; const KGRAPHICS_STATIC_INFO *pKernelGraphicsStaticInfo; + CTX_BUF_POOL_INFO *pCtxBufPool = NULL; NV_ASSERT_OR_RETURN(!gpumgrGetBcEnabledStatus(pGpu), NV_ERR_INVALID_STATE); @@ -97,6 +101,14 @@ { pCtxBuffers = &pKernelGraphics->globalCtxBuffersInfo.pGlobalCtxBuffers[gfid]; pCtxAttr = pKernelGraphics->globalCtxBuffersInfo.globalCtxAttr; + NV_ASSERT_OK_OR_RETURN(ctxBufPoolGetGlobalPool(pGpu, CTX_BUF_ID_GR_GLOBAL, + RM_ENGINE_TYPE_GR(pKernelGraphics->instance), &pCtxBufPool)); + } + + // Don't use context buffer pool for VF allocations managed by host RM. + if (ctxBufPoolIsSupported(pGpu) && (pCtxBufPool != NULL)) + { + allocFlags |= MEMDESC_FLAGS_OWNED_BY_CTX_BUF_POOL; } if (IS_GFID_VF(gfid)) @@ -127,6 +139,13 @@ allocFlags)); memdescSetGpuCacheAttrib(*ppMemDesc, NV_MEMORY_CACHED); + if ((allocFlags & MEMDESC_FLAGS_OWNED_BY_CTX_BUF_POOL) != 0) + { + MemoryManager *pMemoryManager = GPU_GET_MEMORY_MANAGER(pGpu); + + memmgrSetMemDescPageSize_HAL(pGpu, pMemoryManager, *ppMemDesc, AT_GPU, RM_ATTR_PAGE_SIZE_4KB); + NV_ASSERT_OK_OR_RETURN(memdescSetCtxBufPool(*ppMemDesc, pCtxBufPool)); + } NV_CHECK_OK_OR_RETURN(LEVEL_ERROR, memdescAllocList(*ppMemDesc, pCtxAttr[GR_GLOBALCTX_BUFFER_RTV_CB].pAllocList)); } diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/kernel/gpu/gr/fecs_event_list.c nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/kernel/gpu/gr/fecs_event_list.c --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/kernel/gpu/gr/fecs_event_list.c 2023-10-25 20:21:04.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/kernel/gpu/gr/fecs_event_list.c 2024-03-05 22:13:28.000000000 +0000 @@ -30,6 +30,9 @@ * * \***************************************************************************/ +// FIXME XXX +#define NVOC_GPU_INSTANCE_SUBSCRIPTION_H_PRIVATE_ACCESS_ALLOWED + #include "kernel/gpu/gr/kernel_graphics.h" #include "kernel/rmapi/event.h" #include "kernel/rmapi/event_buffer.h" @@ -48,6 +51,9 @@ #include "class/cl90cdtypes.h" #include "ctrl/ctrl90cd.h" +#define NV_FECS_TRACE_MAX_TIMESTAMPS 5 +#define NV_FECS_TRACE_MAGIC_INVALIDATED 0xdededede // magic number for entries that have been read + typedef struct { NvU32 magic_lo; @@ -56,12 +62,11 @@ NvU32 context_ptr; NvU32 new_context_id; NvU32 new_context_ptr; - NvU64 ts[]; + NvU64 ts[NV_FECS_TRACE_MAX_TIMESTAMPS]; + NvU32 reserved[13]; + NvU32 seqno; } FECS_EVENT_RECORD; -#define NV_FECS_TRACE_MAX_TIMESTAMPS 5 -#define NV_FECS_TRACE_MAGIC_INVALIDATED 0xdededede // magic number for entries that have been read - /*! Opaque pointer to private data */ typedef struct VGPU_FECS_TRACE_STAGING_BUFFER VGPU_FECS_TRACE_STAGING_BUFFER; @@ -73,6 +78,7 @@ NvU16 fecsTraceRdOffset; NvU16 fecsTraceCounter; NvU32 fecsCtxswLogIntrPending; + NvU32 fecsLastSeqno; #if PORT_IS_MODULE_SUPPORTED(crypto) PORT_CRYPTO_PRNG *pFecsLogPrng; @@ -224,6 +230,19 @@ pChannelRef = (pKernelChannel != NULL) ? kchannelGetMIGReference(pKernelChannel) : NULL; pNewChannelRef = (pKernelChannelNew != NULL) ? kchannelGetMIGReference(pKernelChannelNew) : NULL; + if (kgraphicsIsFecsRecordUcodeSeqnoSupported(pGpu, pKernelGraphics)) + { + KGRAPHICS_FECS_TRACE_INFO *pFecsTraceInfo = kgraphicsGetFecsTraceInfo(pGpu, pKernelGraphics); + + // Dropped at least 1 event + if ((pFecsTraceInfo->fecsLastSeqno + 1) != pRecord->seqno) + { + notifRecord.dropCount = pRecord->seqno - pFecsTraceInfo->fecsLastSeqno - 1; + } + + pFecsTraceInfo->fecsLastSeqno = pRecord->seqno; + } + for (timestampId = 0; timestampId < NV_FECS_TRACE_MAX_TIMESTAMPS; timestampId++) { NV_ASSERT_OK_OR_ELSE(status, @@ -345,6 +364,8 @@ pSubmap = multimapFindSubmap(&pGpu->fecsEventBufferBindingsUid, 0); notifyEventBuffers(pGpu, pSubmap, ¬ifRecord); + // Clear so we don't report drops for every event in this record + notifRecord.dropCount = 0; } } } @@ -862,7 +883,7 @@ fecsAddBindpoint ( OBJGPU *pGpu, - RsClient *pClient, + RmClient *pClient, RsResourceRef *pEventBufferRef, NvHandle hNotifier, NvBool bAllUsers, @@ -873,8 +894,7 @@ ) { NV_STATUS status; - NvHandle hClient = pClient->hClient; - RmClient *pRmClient = dynamicCast(pClient, RmClient); + NvHandle hClient = staticCast(pClient, RsClient)->hClient; NvHandle hEventBuffer = pEventBufferRef->hResource; EventBuffer *pEventBuffer; NvBool bAdmin = osIsAdministrator(); @@ -959,7 +979,7 @@ } else { - targetUser = (NvU64)(NvUPtr)pRmClient->pUserInfo; + targetUser = (NvU64)(NvUPtr)pClient->pUserInfo; // Filtering UIDs is not yet implemented in legacy vGPU if (IS_VIRTUAL_WITHOUT_SRIOV(pGpu)) @@ -997,14 +1017,14 @@ pBind->hNotifier = hNotifier; pBind->hEventBuffer = hEventBuffer; pBind->pEventBuffer = pEventBuffer; - pBind->pUserInfo = (NvU64)(NvUPtr)pRmClient->pUserInfo; + pBind->pUserInfo = (NvU64)(NvUPtr)pClient->pUserInfo; pBind->bAdmin = bAdmin; pBind->eventMask = eventMask; pBind->bKernel = bKernel; pBind->version = version; status = registerEventNotification(&pEventBuffer->pListeners, - hClient, + staticCast(pClient, RsClient), hNotifier, hEventBuffer, (version == 2 ? @@ -1025,7 +1045,8 @@ else { GPUInstanceSubscription *pGPUInstanceSubscription; - status = gisubscriptionGetGPUInstanceSubscription(pClient, hNotifier, &pGPUInstanceSubscription); + status = gisubscriptionGetGPUInstanceSubscription( + staticCast(pClient, RsClient), hNotifier, &pGPUInstanceSubscription); if (status != NV_OK) goto done; @@ -1234,6 +1255,8 @@ (NvU8)(NV_FECS_TRACE_MAGIC_INVALIDATED & 0xff), memdescGetSize(pFecsMemDesc)); + pFecsTraceInfo->fecsLastSeqno = 0; + // Routing info is the same for all future calls in this series traceWrOffsetParams.grRouteInfo = getHwEnableParams.grRouteInfo; traceRdOffsetParams.grRouteInfo = getHwEnableParams.grRouteInfo; diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/kernel/gpu/gr/kernel_graphics.c nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/kernel/gpu/gr/kernel_graphics.c --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/kernel/gpu/gr/kernel_graphics.c 2023-10-25 20:21:04.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/kernel/gpu/gr/kernel_graphics.c 2024-03-05 22:13:28.000000000 +0000 @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 2020-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2020-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -21,6 +21,8 @@ * DEALINGS IN THE SOFTWARE. */ +#define NVOC_KERNEL_GRAPHICS_H_PRIVATE_ACCESS_ALLOWED + #include "kernel/gpu/gr/kernel_graphics_manager.h" @@ -544,7 +546,7 @@ portMemSet(¶ms, 0, sizeof(params)); params.swizzId = swizzId; NV_ASSERT_OK( - pRmApi->AllocWithHandle(pRmApi, *phClient, *phSubdevice, hSubscription, AMPERE_SMC_PARTITION_REF, ¶ms)); + pRmApi->AllocWithHandle(pRmApi, *phClient, *phSubdevice, hSubscription, AMPERE_SMC_PARTITION_REF, ¶ms, sizeof(params))); } } @@ -645,12 +647,28 @@ { MIG_INSTANCE_REF ref; RM_ENGINE_TYPE localRmEngineType; + Subdevice *pSubdevice; + RsClient *pClient; + + NV_CHECK_OK_OR_GOTO( + status, + LEVEL_ERROR, + serverGetClientUnderLock(&g_resServ, hClient, &pClient), + cleanup); + + NV_CHECK_OK_OR_GOTO( + status, + LEVEL_ERROR, + subdeviceGetByHandle(pClient, hSubdevice, &pSubdevice), + cleanup); // Physical RM will fill with local indices, so localize the index NV_CHECK_OK_OR_GOTO( status, LEVEL_ERROR, - kmigmgrGetInstanceRefFromClient(pGpu, pKernelMIGManager, hClient, &ref), + kmigmgrGetInstanceRefFromDevice(pGpu, pKernelMIGManager, + GPU_RES_GET_DEVICE(pSubdevice), + &ref), cleanup); NV_CHECK_OK_OR_GOTO( status, @@ -785,12 +803,26 @@ KernelMIGManager *pKernelMIGManager = GPU_GET_KERNEL_MIG_MANAGER(pGpu); MIG_INSTANCE_REF ref; RM_ENGINE_TYPE localRmEngineType; + RsClient *pClient; + Device *pDevice; + + NV_CHECK_OK_OR_GOTO( + status, + LEVEL_ERROR, + serverGetClientUnderLock(&g_resServ, hClient, &pClient), + cleanup); + + NV_CHECK_OK_OR_GOTO( + status, + LEVEL_ERROR, + deviceGetByHandle(pClient, hDevice, &pDevice), + cleanup); // Physical RM will fill with local indices, so localize the index NV_CHECK_OK_OR_GOTO( status, LEVEL_ERROR, - kmigmgrGetInstanceRefFromClient(pGpu, pKernelMIGManager, hClient, &ref), + kmigmgrGetInstanceRefFromDevice(pGpu, pKernelMIGManager, pDevice, &ref), cleanup); NV_CHECK_OK_OR_GOTO( status, @@ -1123,6 +1155,27 @@ return status; } +/*! Return if GFX is supported for the given kernel graphics engine */ +NvBool +kgraphicsIsGFXSupported_IMPL +( + OBJGPU *pGpu, + KernelGraphics *pKernelGraphics +) +{ + const KGRAPHICS_STATIC_INFO *pKernelGraphicsStaticInfo = kgraphicsGetStaticInfo(pGpu, pKernelGraphics); + NvU32 gfxCapabilites; + + NV_ASSERT_OR_RETURN(pKernelGraphicsStaticInfo != NULL, NV_FALSE); + NV_ASSERT_OR_RETURN(pKernelGraphicsStaticInfo->pGrInfo != NULL, NV_FALSE); + + gfxCapabilites = pKernelGraphicsStaticInfo->pGrInfo->infoList[NV2080_CTRL_GR_INFO_INDEX_GFX_CAPABILITIES].data; + + return (FLD_TEST_DRF(2080_CTRL_GR, _INFO_GFX_CAPABILITIES, _2D, _TRUE, gfxCapabilites) && + FLD_TEST_DRF(2080_CTRL_GR, _INFO_GFX_CAPABILITIES, _3D, _TRUE, gfxCapabilites) && + FLD_TEST_DRF(2080_CTRL_GR, _INFO_GFX_CAPABILITIES, _I2M, _TRUE, gfxCapabilites)); +} + /*! Retrieve ctxbufpool parameters for given local ctx buffer */ const CTX_BUF_INFO * kgraphicsGetCtxBufferInfo_IMPL @@ -1325,7 +1378,6 @@ } if (kgraphicsIsCtxswLoggingSupported(pGpu, pKernelGraphics) && - !pKernelGraphics->globalCtxBuffersInfo.pGlobalCtxBuffers[gfid].bFecsTraceUnsupportedInGuest && (kgraphicsGetGlobalCtxBuffers(pGpu, pKernelGraphics, gfid)->memDesc[GR_GLOBALCTX_BUFFER_FECS_EVENT] != NULL)) { if (!gvaspaceIsExternallyOwned(pGVAS) && !IS_VIRTUAL_WITHOUT_SRIOV(pGpu)) @@ -1456,6 +1508,11 @@ NvU32 updateFlags = bIsReadOnly ? (DMA_UPDATE_VASPACE_FLAGS_READ_ONLY | DMA_UPDATE_VASPACE_FLAGS_SHADER_READ_ONLY) : DMA_UPDATE_VASPACE_FLAGS_NONE; + if (pGVAS->flags & VASPACE_FLAGS_RESTRICTED_RM_INTERNAL_VALIMITS) + { + allocFlags |= DMA_ALLOC_VASPACE_USE_RM_INTERNAL_VALIMITS; + } + if (kgraphicsIsPerSubcontextContextHeaderSupported(pGpu, pKernelGraphics)) { status = dmaMapBuffer_HAL(pGpu, GPU_GET_DMA(pGpu), pVAS, pMemDesc, &vaddr, @@ -1662,6 +1719,7 @@ NvU64 gpFifoSize = NVA06F_GP_ENTRY__SIZE * gpFifoEntries; NvU64 chSize = gpFifoSize; RM_API *pRmApi = rmapiGetInterface(RMAPI_GPU_LOCK_INTERNAL); + RsClient *pClientId; KernelMIGManager *pKernelMIGManager = GPU_GET_KERNEL_MIG_MANAGER(pGpu); NvBool bNeedMIGWar; NvBool bBcStatus; @@ -1672,8 +1730,11 @@ NV_MEMORY_ALLOCATION_PARAMS memAllocParams; NV_CHANNEL_ALLOC_PARAMS channelGPFIFOAllocParams; NvU32 classNum; + MIG_INSTANCE_REF ref; + NvU32 objectType; + NvU32 primarySliSubDeviceInstance; - // XXX This should be removed when braodcast SLI support is deprecated + // XXX This should be removed when broadcast SLI support is deprecated if (!gpumgrIsParentGPU(pGpu)) { return NV_OK; @@ -1684,6 +1745,10 @@ // FIXME these allocations corrupt BC state NV_ASSERT_OK_OR_RETURN( rmapiutilAllocClientAndDeviceHandles(pRmApi, pGpu, &hClientId, &hDeviceId, &hSubdeviceId)); + // rmapiutilAllocClientAndDeviceHandles allocates a subdevice object for this subDeviceInstance + primarySliSubDeviceInstance = gpumgrGetSubDeviceInstanceFromGpu(pGpu); + + NV_ASSERT_OK_OR_RETURN(serverGetClientUnderLock(&g_resServ, hClientId, &pClientId)); gpumgrSetBcEnabledStatus(pGpu, NV_TRUE); @@ -1697,14 +1762,19 @@ { NvHandle hSecondary; NV2080_ALLOC_PARAMETERS nv2080AllocParams; + NvU32 thisSubDeviceInstance = gpumgrGetSubDeviceInstanceFromGpu(pGpu); + + // Skip if already allocated by rmapiutilAllocClientAndDeviceHandles() + if (thisSubDeviceInstance == primarySliSubDeviceInstance) + SLI_LOOP_CONTINUE; // Allocate a subDevice NV_CHECK_OK_OR_GOTO(status, LEVEL_ERROR, - serverutilGenResourceHandle(hClientId, &hSecondary), + clientGenResourceHandle(pClientId, &hSecondary), cleanup); portMemSet(&nv2080AllocParams, 0, sizeof(nv2080AllocParams)); - nv2080AllocParams.subDeviceId = gpumgrGetSubDeviceInstanceFromGpu(pGpu); + nv2080AllocParams.subDeviceId = thisSubDeviceInstance; NV_CHECK_OK(status, LEVEL_WARNING, pRmApi->AllocWithHandle(pRmApi, @@ -1712,17 +1782,16 @@ hDeviceId, hSecondary, NV20_SUBDEVICE_0, - &nv2080AllocParams)); + &nv2080AllocParams, + sizeof(nv2080AllocParams))); } SLI_LOOP_END; if (bNeedMIGWar) { - KernelMIGManager *pKernelMIGManager = GPU_GET_KERNEL_MIG_MANAGER(pGpu); NvHandle hPartitionRef = 0xbaba0048; NvHandle hExecPartitionRef = 0xbaba004a; NVC637_ALLOCATION_PARAMETERS nvC637AllocParams = {0}; - MIG_INSTANCE_REF ref; // Get swizzId for this GR NV_ASSERT_OK_OR_GOTO(status, @@ -1740,7 +1809,8 @@ hSubdeviceId, hPartitionRef, AMPERE_SMC_PARTITION_REF, - &nvC637AllocParams), + &nvC637AllocParams, + sizeof(nvC637AllocParams)), cleanup); if (ref.pMIGComputeInstance != NULL) @@ -1753,7 +1823,8 @@ hPartitionRef, hExecPartitionRef, AMPERE_SMC_EXEC_PARTITION_REF, - &nvC638AllocParams), + &nvC638AllocParams, + sizeof(nvC638AllocParams)), cleanup); } } @@ -1771,7 +1842,7 @@ // Create a new VAspace for channel portMemSet(&vaParams, 0, sizeof(NV_VASPACE_ALLOCATION_PARAMETERS)); NV_ASSERT_OK_OR_GOTO(status, - pRmApi->AllocWithHandle(pRmApi, hClientId, hDeviceId, hVASpace, FERMI_VASPACE_A, &vaParams), + pRmApi->AllocWithHandle(pRmApi, hClientId, hDeviceId, hVASpace, FERMI_VASPACE_A, &vaParams, sizeof(vaParams)), cleanup); // Allocate gpfifo entries @@ -1782,8 +1853,18 @@ memAllocParams.attr = DRF_DEF(OS32, _ATTR, _LOCATION, _PCI); memAllocParams.hVASpace = 0; // Physical allocations don't expect vaSpace handles + // + // When APM feature is enabled all RM internal sysmem allocations must + // be in unprotected memory + // When Hopper CC is enabled all RM internal sysmem allocations that + // are required to be accessed from GPU should be in unprotected memory + // Other sysmem allocations that are not required to be accessed from GPU + // must be in protected memory + // + memAllocParams.attr2 |= DRF_DEF(OS32, _ATTR2, _MEMORY_PROTECTION, _UNPROTECTED); + NV_ASSERT_OK_OR_GOTO(status, - pRmApi->AllocWithHandle(pRmApi, hClientId, hDeviceId, hPBPhysMemId, NV01_MEMORY_SYSTEM, &memAllocParams), + pRmApi->AllocWithHandle(pRmApi, hClientId, hDeviceId, hPBPhysMemId, NV01_MEMORY_SYSTEM, &memAllocParams, sizeof(memAllocParams)), cleanup); portMemSet(&memAllocParams, 0, sizeof(NV_MEMORY_ALLOCATION_PARAMS)); @@ -1796,7 +1877,7 @@ // 0 handle = allocations on gpu default vaSpace NV_ASSERT_OK_OR_GOTO(status, - pRmApi->AllocWithHandle(pRmApi, hClientId, hDeviceId, hPBVirtMemId, NV50_MEMORY_VIRTUAL, &memAllocParams), + pRmApi->AllocWithHandle(pRmApi, hClientId, hDeviceId, hPBVirtMemId, NV50_MEMORY_VIRTUAL, &memAllocParams, sizeof(memAllocParams)), cleanup); // Allocate Userd @@ -1847,9 +1928,23 @@ break; } + // + // When APM is enabled all RM internal allocations must to go to + // unprotected memory irrespective of vidmem or sysmem + // When Hopper CC is enabled all RM internal sysmem allocations that + // are required to be accessed from GPU should be in unprotected memory + // and all vidmem allocations must go to protected memory + // + if (gpuIsApmFeatureEnabled(pGpu) || + FLD_TEST_DRF(OS32, _ATTR, _LOCATION, _PCI, memAllocParams.attr)) + { + memAllocParams.attr2 |= DRF_DEF(OS32, _ATTR2, _MEMORY_PROTECTION, + _UNPROTECTED); + } + NV_ASSERT_OK_OR_GOTO(status, pRmApi->AllocWithHandle(pRmApi, hClientId, hDeviceId, hUserdId, - userdMemClass, &memAllocParams), + userdMemClass, &memAllocParams, sizeof(memAllocParams)), cleanup); } @@ -1875,11 +1970,15 @@ if (bNeedMIGWar) { - MIG_INSTANCE_REF ref; RM_ENGINE_TYPE localRmEngineType; + Device *pDevice; NV_ASSERT_OK_OR_GOTO(status, - kmigmgrGetInstanceRefFromClient(pGpu, pKernelMIGManager, hClientId, &ref), + deviceGetByHandle(pClientId, hDeviceId, &pDevice), + cleanup); + + NV_ASSERT_OK_OR_GOTO(status, + kmigmgrGetInstanceRefFromDevice(pGpu, pKernelMIGManager, pDevice, &ref), cleanup); NV_ASSERT_OK_OR_GOTO(status, @@ -1895,7 +1994,7 @@ NV_ASSERT_OK_OR_GOTO(status, pRmApi->AllocWithHandle(pRmApi, hClientId, hDeviceId, hChannelId, - classNum, &channelGPFIFOAllocParams), + classNum, &channelGPFIFOAllocParams, sizeof(channelGPFIFOAllocParams)), cleanup); // @@ -1912,7 +2011,7 @@ const KGRAPHICS_STATIC_INFO *pKernelGraphicsStaticInfo = kgraphicsGetStaticInfo(pGpu, pKernelGraphics); NvU32 i; - NV_ASSERT_OK(CliGetKernelChannel(hClientId, hChannelId, &pKernelChannel)); + NV_ASSERT_OK(CliGetKernelChannel(pClientId, hChannelId, &pKernelChannel)); NV_ASSERT_OR_ELSE(pKernelGraphicsStaticInfo != NULL, status = NV_ERR_INVALID_STATE; @@ -1941,24 +2040,25 @@ bAcquireLock = NV_FALSE; pRmApi = rmapiGetInterface(RMAPI_GPU_LOCK_INTERNAL); - // Get KernelGraphicsObject class Id if (!bNeedMIGWar) { - NV_ASSERT_OK_OR_GOTO(status, - kgraphicsGetClassByType(pGpu, pKernelGraphics, GR_OBJECT_TYPE_3D, &classNum), - cleanup); + objectType = GR_OBJECT_TYPE_3D; } else { - NV_ASSERT_OK_OR_GOTO(status, - kgraphicsGetClassByType(pGpu, pKernelGraphics, GR_OBJECT_TYPE_COMPUTE, &classNum), - cleanup); + objectType = GR_OBJECT_TYPE_COMPUTE; + } + + // Get KernelGraphicsObject class Id + NV_ASSERT_OK_OR_GOTO(status, + kgraphicsGetClassByType(pGpu, pKernelGraphics, objectType, &classNum), + cleanup); NV_ASSERT_OR_GOTO(classNum != 0, cleanup); // Allocate a GR object on the channel NV_ASSERT_OK_OR_GOTO(status, - pRmApi->AllocWithHandle(pRmApi, hClientId, hChannelId, hObj3D, classNum, NULL), + pRmApi->AllocWithHandle(pRmApi, hClientId, hChannelId, hObj3D, classNum, NULL, 0), cleanup); cleanup: @@ -2145,7 +2245,7 @@ portMemSet(&grRouteInfo, 0, sizeof(grRouteInfo)); kgrmgrCtrlSetEngineID(0, &grRouteInfo); NV_CHECK_OK_OR_ELSE(status, LEVEL_ERROR, - kgrmgrCtrlRouteKGR(pGpu, pKernelGraphicsManager, RES_GET_CLIENT_HANDLE(pDevice), &grRouteInfo, &pKernelGraphics), + kgrmgrCtrlRouteKGRWithDevice(pGpu, pKernelGraphicsManager, pDevice, &grRouteInfo, &pKernelGraphics), SLI_LOOP_RETURN(status);); if (!bCapsPopulated) @@ -2193,7 +2293,7 @@ kgrmgrCtrlSetEngineID(0, &grRouteInfo); NV_CHECK_OK_OR_ELSE(status, LEVEL_ERROR, - kgrmgrCtrlRouteKGR(pGpu, pKernelGraphicsManager, RES_GET_CLIENT_HANDLE(pDevice), &grRouteInfo, &pKernelGraphics), + kgrmgrCtrlRouteKGRWithDevice(pGpu, pKernelGraphicsManager, pDevice, &grRouteInfo, &pKernelGraphics), SLI_LOOP_RETURN(status);); if (!pParams->bCapsPopulated) @@ -2214,7 +2314,7 @@ _kgraphicsCtrlCmdGrGetInfoV2 ( OBJGPU *pGpu, - NvHandle hClient, + Device *pDevice, NV2080_CTRL_GR_GET_INFO_V2_PARAMS *pParams ) { @@ -2238,7 +2338,7 @@ return NV_ERR_INVALID_ARGUMENT; } - if (kmigmgrIsClientUsingDeviceProfiling(pGpu, pKernelMIGManager, hClient)) + if (kmigmgrIsClientUsingDeviceProfiling(pGpu, pKernelMIGManager, RES_GET_CLIENT_HANDLE(pDevice))) { NvU32 grIdx; for (grIdx = 0; grIdx < GPU_MAX_GRS; grIdx++) @@ -2253,7 +2353,7 @@ else { NV_CHECK_OK_OR_RETURN(LEVEL_ERROR, - kgrmgrCtrlRouteKGR(pGpu, pKernelGraphicsManager, hClient, &pParams->grRouteInfo, &pKernelGraphics)); + kgrmgrCtrlRouteKGRWithDevice(pGpu, pKernelGraphicsManager, pDevice, &pParams->grRouteInfo, &pKernelGraphics)); } pKernelGraphicsStaticInfo = kgraphicsGetStaticInfo(pGpu, pKernelGraphics); @@ -2288,7 +2388,6 @@ OBJGPU *pGpu = GPU_RES_GET_GPU(pDevice); NV0080_CTRL_GR_GET_INFO_V2_PARAMS grInfoParamsV2; NV0080_CTRL_GR_INFO *pGrInfos = NvP64_VALUE(pParams->grInfoList); - NvHandle hClient = RES_GET_CLIENT_HANDLE(pDevice); NvU32 grInfoListSize = NV_MIN(pParams->grInfoListSize, NV0080_CTRL_GR_INFO_MAX_SIZE); @@ -2302,7 +2401,7 @@ grInfoParamsV2.grInfoListSize = grInfoListSize; NV_CHECK_OK_OR_RETURN(LEVEL_ERROR, - _kgraphicsCtrlCmdGrGetInfoV2(pGpu, hClient, &grInfoParamsV2)); + _kgraphicsCtrlCmdGrGetInfoV2(pGpu, pDevice, &grInfoParamsV2)); portMemCopy(pGrInfos, grInfoListSize * sizeof(*pGrInfos), grInfoParamsV2.grInfoList, grInfoListSize * sizeof(*pGrInfos)); @@ -2323,16 +2422,64 @@ ) { OBJGPU *pGpu = GPU_RES_GET_GPU(pDevice); - NvHandle hClient = RES_GET_CLIENT_HANDLE(pDevice); LOCK_ASSERT_AND_RETURN(rmapiLockIsOwner() && rmGpuLockIsOwner()); NV_CHECK_OK_OR_RETURN(LEVEL_ERROR, - _kgraphicsCtrlCmdGrGetInfoV2(pGpu, hClient, pParams)); + _kgraphicsCtrlCmdGrGetInfoV2(pGpu, pDevice, pParams)); return NV_OK; } +NV_STATUS +kgraphicsDiscoverMaxLocalCtxBufferSize_IMPL +( + OBJGPU *pGpu, + KernelGraphics *pKernelGraphics +) +{ + NvU32 bufId = 0; + const KGRAPHICS_STATIC_INFO *pKernelGraphicsStaticInfo = kgraphicsGetStaticInfo(pGpu, pKernelGraphics); + + if (IS_MODS_AMODEL(pGpu)) + return NV_OK; + + NV_ASSERT_OK_OR_RETURN( + kgraphicsInitializeDeferredStaticData(pGpu, pKernelGraphics, NV01_NULL_OBJECT, NV01_NULL_OBJECT)); + + NV_ASSERT_OR_RETURN(pKernelGraphicsStaticInfo->pContextBuffersInfo != NULL, NV_ERR_INVALID_STATE); + + FOR_EACH_IN_ENUM(GR_CTX_BUFFER, bufId) + { + if (bufId == GR_CTX_BUFFER_MAIN) + { + NvU32 size; + + NV_ASSERT_OK_OR_RETURN(kgraphicsGetMainCtxBufferSize(pGpu, pKernelGraphics, NV_TRUE, &size)); + kgraphicsSetCtxBufferInfo(pGpu, pKernelGraphics, bufId, + size, + RM_PAGE_SIZE, + RM_ATTR_PAGE_SIZE_4KB, + kgraphicsShouldForceMainCtxContiguity_HAL(pGpu, pKernelGraphics)); + } + else + { + NvU32 fifoEngineId; + + NV_ASSERT_OK_OR_RETURN( + kgrctxCtxBufferToFifoEngineId(bufId, &fifoEngineId)); + + kgraphicsSetCtxBufferInfo(pGpu, pKernelGraphics, bufId, + pKernelGraphicsStaticInfo->pContextBuffersInfo->engine[fifoEngineId].size, + RM_PAGE_SIZE, + RM_ATTR_PAGE_SIZE_4KB, + ((bufId == GR_CTX_BUFFER_PATCH) || (bufId == GR_CTX_BUFFER_PM))); + } + } + FOR_EACH_IN_ENUM_END; + return NV_OK; +} + /*! * KernelGraphics RM SubDevice Controls */ @@ -2354,10 +2501,11 @@ KernelGraphicsManager *pKernelGraphicsManager = GPU_GET_KERNEL_GRAPHICS_MANAGER(pGpu); KernelGraphics *pKernelGraphics; NV2080_CTRL_GR_ROUTE_INFO grRouteInfo = pParams->grRouteInfo; + Device *pDevice = GPU_RES_GET_DEVICE(pSubdevice); kgrmgrCtrlSetEngineID(0, &grRouteInfo); NV_CHECK_OK_OR_RETURN(LEVEL_ERROR, - kgrmgrCtrlRouteKGR(pGpu, pKernelGraphicsManager, RES_GET_CLIENT_HANDLE(pSubdevice), &grRouteInfo, &pKernelGraphics)); + kgrmgrCtrlRouteKGRWithDevice(pGpu, pKernelGraphicsManager, pDevice, &grRouteInfo, &pKernelGraphics)); LOCK_ASSERT_AND_RETURN(rmapiLockIsOwner()); @@ -2397,7 +2545,7 @@ NV2080_CTRL_GR_INFO *pGrInfos = NvP64_VALUE(pParams->grInfoList); NV2080_CTRL_GR_ROUTE_INFO grRouteInfo = pParams->grRouteInfo; OBJGPU *pGpu = GPU_RES_GET_GPU(pSubdevice); - NvHandle hClient = RES_GET_CLIENT_HANDLE(pSubdevice); + Device *pDevice = GPU_RES_GET_DEVICE(pSubdevice); NvU32 grInfoListSize = NV_MIN(pParams->grInfoListSize, NV2080_CTRL_GR_INFO_MAX_SIZE); @@ -2418,7 +2566,7 @@ grInfoParamsV2.grRouteInfo = grRouteInfo; NV_CHECK_OK_OR_RETURN(LEVEL_ERROR, - _kgraphicsCtrlCmdGrGetInfoV2(pGpu, hClient, &grInfoParamsV2)); + _kgraphicsCtrlCmdGrGetInfoV2(pGpu, pDevice, &grInfoParamsV2)); portMemCopy(pGrInfos, grInfoListSize * sizeof(*pGrInfos), grInfoParamsV2.grInfoList, grInfoListSize * sizeof(*pGrInfos)); @@ -2439,12 +2587,12 @@ ) { OBJGPU *pGpu = GPU_RES_GET_GPU(pSubdevice); - NvHandle hClient = RES_GET_CLIENT_HANDLE(pSubdevice); + Device *pDevice = GPU_RES_GET_DEVICE(pSubdevice); LOCK_ASSERT_AND_RETURN(rmapiLockIsOwner() && rmDeviceGpuLockIsOwner(pGpu->gpuInstance)); NV_CHECK_OK_OR_RETURN(LEVEL_ERROR, - _kgraphicsCtrlCmdGrGetInfoV2(pGpu, hClient, pParams)); + _kgraphicsCtrlCmdGrGetInfoV2(pGpu, pDevice, pParams)); return NV_OK; } @@ -2465,6 +2613,7 @@ OBJGPU *pGpu = GPU_RES_GET_GPU(pSubdevice); KernelGraphics *pKernelGraphics; NvHandle hClient = RES_GET_CLIENT_HANDLE(pSubdevice); + Device *pDevice = GPU_RES_GET_DEVICE(pSubdevice); KernelGraphicsManager *pKernelGraphicsManager = GPU_GET_KERNEL_GRAPHICS_MANAGER(pGpu); KernelMIGManager *pKernelMIGManager = GPU_GET_KERNEL_MIG_MANAGER(pGpu); const KGRAPHICS_STATIC_INFO *pStaticInfo; @@ -2479,7 +2628,7 @@ else { NV_CHECK_OK_OR_RETURN(LEVEL_ERROR, - kgrmgrCtrlRouteKGR(pGpu, pKernelGraphicsManager, hClient, &pParams->grRouteInfo, &pKernelGraphics)); + kgrmgrCtrlRouteKGRWithDevice(pGpu, pKernelGraphicsManager, pDevice, &pParams->grRouteInfo, &pKernelGraphics)); } // Verify static info is available @@ -2512,6 +2661,7 @@ OBJGPU *pGpu = GPU_RES_GET_GPU(pSubdevice); KernelGraphics *pKernelGraphics; NvHandle hClient = RES_GET_CLIENT_HANDLE(pSubdevice); + Device *pDevice = GPU_RES_GET_DEVICE(pSubdevice); KernelGraphicsManager *pKernelGraphicsManager = GPU_GET_KERNEL_GRAPHICS_MANAGER(pGpu); KernelMIGManager *pKernelMIGManager = GPU_GET_KERNEL_MIG_MANAGER(pGpu); const KGRAPHICS_STATIC_INFO *pStaticInfo; @@ -2526,7 +2676,7 @@ else { NV_CHECK_OK_OR_RETURN(LEVEL_ERROR, - kgrmgrCtrlRouteKGR(pGpu, pKernelGraphicsManager, hClient, &pParams->grRouteInfo, &pKernelGraphics)); + kgrmgrCtrlRouteKGRWithDevice(pGpu, pKernelGraphicsManager, pDevice, &pParams->grRouteInfo, &pKernelGraphics)); } // Verify static info is available @@ -2569,6 +2719,7 @@ OBJGPU *pGpu = GPU_RES_GET_GPU(pSubdevice); KernelGraphics *pKernelGraphics; NvHandle hClient = RES_GET_CLIENT_HANDLE(pSubdevice); + Device *pDevice = GPU_RES_GET_DEVICE(pSubdevice); KernelGraphicsManager *pKernelGraphicsManager = GPU_GET_KERNEL_GRAPHICS_MANAGER(pGpu); const KGRAPHICS_STATIC_INFO *pStaticInfo; KernelMIGManager *pKernelMIGManager = GPU_GET_KERNEL_MIG_MANAGER(pGpu); @@ -2590,7 +2741,7 @@ else { NV_CHECK_OK_OR_RETURN(LEVEL_ERROR, - kgrmgrCtrlRouteKGR(pGpu, pKernelGraphicsManager, hClient, &pParams->grRouteInfo, &pKernelGraphics)); + kgrmgrCtrlRouteKGRWithDevice(pGpu, pKernelGraphicsManager, pDevice, &pParams->grRouteInfo, &pKernelGraphics)); } // Verify static info is available @@ -2627,6 +2778,7 @@ NV_STATUS status = NV_OK; OBJGPU *pGpu = GPU_RES_GET_GPU(pSubdevice); NvHandle hClient = RES_GET_CLIENT_HANDLE(pSubdevice); + Device *pDevice = GPU_RES_GET_DEVICE(pSubdevice); KernelGraphicsManager *pKernelGraphicsManager = GPU_GET_KERNEL_GRAPHICS_MANAGER(pGpu); KernelGraphics *pKernelGraphics; const KGRAPHICS_STATIC_INFO *pKernelGraphicsStaticInfo; @@ -2642,7 +2794,7 @@ else { NV_CHECK_OK_OR_RETURN(LEVEL_ERROR, - kgrmgrCtrlRouteKGR(pGpu, pKernelGraphicsManager, hClient, &pParams->grRouteInfo, &pKernelGraphics)); + kgrmgrCtrlRouteKGRWithDevice(pGpu, pKernelGraphicsManager, pDevice, &pParams->grRouteInfo, &pKernelGraphics)); pKernelGraphicsStaticInfo = kgraphicsGetStaticInfo(pGpu, pKernelGraphics); NV_ASSERT_OR_RETURN(pKernelGraphicsStaticInfo != NULL, NV_ERR_INVALID_STATE); @@ -2673,6 +2825,7 @@ NV_STATUS status = NV_OK; OBJGPU *pGpu = GPU_RES_GET_GPU(pSubdevice); NvHandle hClient = RES_GET_CLIENT_HANDLE(pSubdevice); + Device *pDevice = GPU_RES_GET_DEVICE(pSubdevice); KernelGraphicsManager *pKernelGraphicsManager = GPU_GET_KERNEL_GRAPHICS_MANAGER(pGpu); KernelGraphics *pKernelGraphics; const KGRAPHICS_STATIC_INFO *pKernelGraphicsStaticInfo; @@ -2689,7 +2842,7 @@ else { NV_CHECK_OK_OR_RETURN(LEVEL_ERROR, - kgrmgrCtrlRouteKGR(pGpu, pKernelGraphicsManager, hClient, &pParams->grRouteInfo, &pKernelGraphics)); + kgrmgrCtrlRouteKGRWithDevice(pGpu, pKernelGraphicsManager, pDevice, &pParams->grRouteInfo, &pKernelGraphics)); pKernelGraphicsStaticInfo = kgraphicsGetStaticInfo(pGpu, pKernelGraphics); NV_ASSERT_OR_RETURN(pKernelGraphicsStaticInfo != NULL, NV_ERR_INVALID_STATE); @@ -2715,7 +2868,7 @@ ) { OBJGPU *pGpu = GPU_RES_GET_GPU(pSubdevice); - NvHandle hClient = RES_GET_CLIENT_HANDLE(pSubdevice); + Device *pDevice = GPU_RES_GET_DEVICE(pSubdevice); KernelGraphicsManager *pKernelGraphicsManager = GPU_GET_KERNEL_GRAPHICS_MANAGER(pGpu); KernelGraphics *pKernelGraphics; const KGRAPHICS_STATIC_INFO *pKernelGraphicsStaticInfo; @@ -2724,7 +2877,7 @@ portMemSet(&grRouteInfo, 0, sizeof(grRouteInfo)); NV_CHECK_OK_OR_RETURN(LEVEL_ERROR, - kgrmgrCtrlRouteKGR(pGpu, pKernelGraphicsManager, hClient, &grRouteInfo, &pKernelGraphics)); + kgrmgrCtrlRouteKGRWithDevice(pGpu, pKernelGraphicsManager, pDevice, &grRouteInfo, &pKernelGraphics)); pKernelGraphicsStaticInfo = kgraphicsGetStaticInfo(pGpu, pKernelGraphics); NV_ASSERT_OR_RETURN(pKernelGraphicsStaticInfo != NULL, NV_ERR_INVALID_STATE); @@ -2756,6 +2909,7 @@ { OBJGPU *pGpu = GPU_RES_GET_GPU(pSubdevice); NvHandle hClient = RES_GET_CLIENT_HANDLE(pSubdevice); + Device *pDevice = GPU_RES_GET_DEVICE(pSubdevice); KernelGraphicsManager *pKernelGraphicsManager = GPU_GET_KERNEL_GRAPHICS_MANAGER(pGpu); KernelGraphics *pKernelGraphics; const KGRAPHICS_STATIC_INFO *pKernelGraphicsStaticInfo; @@ -2770,7 +2924,7 @@ else { NV_CHECK_OK_OR_RETURN(LEVEL_ERROR, - kgrmgrCtrlRouteKGR(pGpu, pKernelGraphicsManager, hClient, &pParams->grRouteInfo, &pKernelGraphics)); + kgrmgrCtrlRouteKGRWithDevice(pGpu, pKernelGraphicsManager, pDevice, &pParams->grRouteInfo, &pKernelGraphics)); pKernelGraphicsStaticInfo = kgraphicsGetStaticInfo(pGpu, pKernelGraphics); NV_ASSERT_OR_RETURN(pKernelGraphicsStaticInfo != NULL, NV_ERR_INVALID_STATE); @@ -2816,13 +2970,14 @@ NV_ASSERT_OK_OR_RETURN( serverutilGetResourceRefWithType(hClient, pParams->hEventBuffer, classId(EventBuffer), &pEventBufferRef)); - NV_ASSERT_OK_OR_RETURN(serverutilGetClientUnderLock(hClient, &pClient)); + pClient = serverutilGetClientUnderLock(hClient); + NV_ASSERT_OR_RETURN(pClient != NULL, NV_ERR_INVALID_CLIENT); if (bMIGInUse) return NV_ERR_NOT_SUPPORTED; status = fecsAddBindpoint(pGpu, - staticCast(pClient, RsClient), + pClient, pEventBufferRef, hNotifier, pParams->bAllUsers, @@ -2860,10 +3015,11 @@ NV_ASSERT_OK_OR_RETURN( serverutilGetResourceRefWithType(hClient, pParams->hEventBuffer, classId(EventBuffer), &pEventBufferRef)); - NV_ASSERT_OK_OR_RETURN(serverutilGetClientUnderLock(hClient, &pClient)); + pClient = serverutilGetClientUnderLock(hClient); + NV_ASSERT_OR_RETURN(pClient != NULL, NV_ERR_INVALID_CLIENT); status = fecsAddBindpoint(pGpu, - staticCast(pClient, RsClient), + pClient, pEventBufferRef, hNotifier, pParams->bAllUsers, @@ -2891,6 +3047,7 @@ KernelGraphics *pKernelGraphics; const KGRAPHICS_STATIC_INFO *pKernelGraphicsStaticInfo; NvHandle hClient = RES_GET_CLIENT_HANDLE(pSubdevice); + Device *pDevice = GPU_RES_GET_DEVICE(pSubdevice); KernelMIGManager *pKernelMIGManager = GPU_GET_KERNEL_MIG_MANAGER(pGpu); NvU32 grIdx = 0; @@ -2922,9 +3079,8 @@ // valid in defined GPU instance // NV_CHECK_OK_OR_RETURN(LEVEL_ERROR, - kmigmgrGetInstanceRefFromClient(pGpu, pKernelMIGManager, - hClient, - &ref)); + kmigmgrGetInstanceRefFromDevice(pGpu, pKernelMIGManager, + pDevice, &ref)); NV_CHECK_OK_OR_RETURN(LEVEL_ERROR, kmigmgrGetGlobalToLocalEngineType(pGpu, pKernelMIGManager, ref, @@ -2959,6 +3115,7 @@ { OBJGPU *pGpu = GPU_RES_GET_GPU(pSubdevice); NvHandle hClient = RES_GET_CLIENT_HANDLE(pSubdevice); + Device *pDevice = GPU_RES_GET_DEVICE(pSubdevice); KernelGraphicsManager *pKernelGraphicsManager = GPU_GET_KERNEL_GRAPHICS_MANAGER(pGpu); NV2080_CTRL_GR_ROUTE_INFO grRouteInfo; KernelGraphics *pKernelGraphics; @@ -2975,7 +3132,7 @@ { portMemSet(&grRouteInfo, 0, sizeof(grRouteInfo)); NV_CHECK_OK_OR_RETURN(LEVEL_ERROR, - kgrmgrCtrlRouteKGR(pGpu, pKernelGraphicsManager, hClient, &grRouteInfo, &pKernelGraphics)); + kgrmgrCtrlRouteKGRWithDevice(pGpu, pKernelGraphicsManager, pDevice, &grRouteInfo, &pKernelGraphics)); pKernelGraphicsStaticInfo = kgraphicsGetStaticInfo(pGpu, pKernelGraphics); NV_ASSERT_OR_RETURN(pKernelGraphicsStaticInfo != NULL, NV_ERR_INVALID_STATE); @@ -3015,7 +3172,7 @@ { OBJGPU *pGpu = GPU_RES_GET_GPU(pSubdevice); KernelGraphicsManager *pKernelGraphicsManager = GPU_GET_KERNEL_GRAPHICS_MANAGER(pGpu); - NvHandle hClient = RES_GET_CLIENT_HANDLE(pSubdevice); + Device *pDevice = GPU_RES_GET_DEVICE(pSubdevice); NV2080_CTRL_GR_ROUTE_INFO grRouteInfo; KernelGraphics *pKernelGraphics; const KGRAPHICS_STATIC_INFO *pKernelGraphicsStaticInfo; @@ -3029,7 +3186,7 @@ portMemSet(&grRouteInfo, 0, sizeof(grRouteInfo)); NV_CHECK_OK_OR_RETURN(LEVEL_ERROR, - kgrmgrCtrlRouteKGR(pGpu, pKernelGraphicsManager, hClient, &grRouteInfo, &pKernelGraphics)); + kgrmgrCtrlRouteKGRWithDevice(pGpu, pKernelGraphicsManager, pDevice, &grRouteInfo, &pKernelGraphics)); pKernelGraphicsStaticInfo = kgraphicsGetStaticInfo(pGpu, pKernelGraphics); NV_ASSERT_OR_RETURN(pKernelGraphicsStaticInfo != NULL, NV_ERR_INVALID_STATE); @@ -3068,14 +3225,15 @@ { kgrmgrCtrlSetChannelHandle(pParams->hChannel, &grRouteInfo); NV_CHECK_OK_OR_RETURN(LEVEL_ERROR, - kgrmgrCtrlRouteKGR(pGpu, pKernelGraphicsManager, - RES_GET_CLIENT_HANDLE(pSubdevice), - &grRouteInfo, - &pKernelGraphics)); + kgrmgrCtrlRouteKGRWithDevice(pGpu, pKernelGraphicsManager, + GPU_RES_GET_DEVICE(pSubdevice), + &grRouteInfo, + &pKernelGraphics)); // Retrieve channel from either bare channel or TSG handle NV_CHECK_OK_OR_RETURN(LEVEL_ERROR, - kchannelGetFromDualHandleRestricted(RES_GET_CLIENT_HANDLE(pSubdevice), pParams->hChannel, &pKernelChannel)); + kchannelGetFromDualHandleRestricted(RES_GET_CLIENT(pSubdevice), + pParams->hChannel, &pKernelChannel)); NV_ASSERT_OK_OR_RETURN( kgrctxFromKernelChannel(pKernelChannel, &pKernelGraphicsContext)); @@ -3113,7 +3271,7 @@ { OBJGPU *pGpu = GPU_RES_GET_GPU(pSubdevice); KernelGraphicsManager *pKernelGraphicsManager = GPU_GET_KERNEL_GRAPHICS_MANAGER(pGpu); - NvHandle hClient = RES_GET_CLIENT_HANDLE(pSubdevice); + Device *pDevice = GPU_RES_GET_DEVICE(pSubdevice); NV2080_CTRL_GR_ROUTE_INFO grRouteInfo; KernelGraphics *pKernelGraphics; const KGRAPHICS_STATIC_INFO *pKernelGraphicsStaticInfo; @@ -3122,7 +3280,7 @@ portMemSet(&grRouteInfo, 0, sizeof(grRouteInfo)); NV_CHECK_OK_OR_RETURN(LEVEL_ERROR, - kgrmgrCtrlRouteKGR(pGpu, pKernelGraphicsManager, hClient, &grRouteInfo, &pKernelGraphics)); + kgrmgrCtrlRouteKGRWithDevice(pGpu, pKernelGraphicsManager, pDevice, &grRouteInfo, &pKernelGraphics)); pKernelGraphicsStaticInfo = kgraphicsGetStaticInfo(pGpu, pKernelGraphics); NV_ASSERT_OR_RETURN(pKernelGraphicsStaticInfo != NULL, NV_ERR_INVALID_STATE); @@ -3156,14 +3314,14 @@ NV2080_CTRL_GR_ROUTE_INFO grRouteInfo; KernelGraphics *pKernelGraphics; const KGRAPHICS_STATIC_INFO *pKernelGraphicsStaticInfo; - NvHandle hClient = RES_GET_CLIENT_HANDLE(pSubdevice); + Device *pDevice = GPU_RES_GET_DEVICE(pSubdevice); NvU32 engineId; LOCK_ASSERT_AND_RETURN(rmapiLockIsOwner() && rmGpuLockIsOwner()); portMemSet(&grRouteInfo, 0, sizeof(grRouteInfo)); NV_CHECK_OK_OR_RETURN(LEVEL_ERROR, - kgrmgrCtrlRouteKGR(pGpu, pKernelGraphicsManager, hClient, &grRouteInfo, &pKernelGraphics)); + kgrmgrCtrlRouteKGRWithDevice(pGpu, pKernelGraphicsManager, pDevice, &grRouteInfo, &pKernelGraphics)); // Verify static info is available pKernelGraphicsStaticInfo = kgraphicsGetStaticInfo(pGpu, pKernelGraphics); @@ -3200,7 +3358,7 @@ KernelGraphicsManager *pKernelGraphicsManager = GPU_GET_KERNEL_GRAPHICS_MANAGER(pGpu); KernelGraphics *pKernelGraphics; const KGRAPHICS_STATIC_INFO *pKernelGraphicsStaticInfo; - NvHandle hClient = RES_GET_CLIENT_HANDLE(pSubdevice); + Device *pDevice = GPU_RES_GET_DEVICE(pSubdevice); NvU32 size = 0; NvU32 alignment = RM_PAGE_SIZE; NvU32 engineId; @@ -3215,7 +3373,8 @@ } NV_CHECK_OK_OR_RETURN(LEVEL_ERROR, - kgrmgrCtrlRouteKGR(pGpu, pKernelGraphicsManager, hClient, &pParams->grRouteInfo, &pKernelGraphics)); + kgrmgrCtrlRouteKGRWithDevice(pGpu, pKernelGraphicsManager, pDevice, + &pParams->grRouteInfo, &pKernelGraphics)); // Verify static info is available pKernelGraphicsStaticInfo = kgraphicsGetStaticInfo(pGpu, pKernelGraphics); @@ -3266,7 +3425,8 @@ NV_STATUS status = NV_OK; OBJGPU *pGpu = GPU_RES_GET_GPU(pSubdevice); KernelGraphics *pKernelGraphics; - NvHandle hClient = RES_GET_CLIENT_HANDLE(pSubdevice); + RsClient *pClient = RES_GET_CLIENT(pSubdevice); + Device *pDevice = GPU_RES_GET_DEVICE(pSubdevice); KernelGraphicsManager *pKernelGraphicsManager = GPU_GET_KERNEL_GRAPHICS_MANAGER(pGpu); NV2080_CTRL_GR_CTX_BUFFER_INFO *pCtxBufferInfo; NV2080_CTRL_GR_ROUTE_INFO grRouteInfo; @@ -3305,11 +3465,12 @@ portMemSet(&grRouteInfo, 0, sizeof(grRouteInfo)); kgrmgrCtrlSetChannelHandle(pParams->hChannel, &grRouteInfo); NV_CHECK_OK_OR_RETURN(LEVEL_ERROR, - kgrmgrCtrlRouteKGR(pGpu, pKernelGraphicsManager, hClient, &grRouteInfo, &pKernelGraphics)); + kgrmgrCtrlRouteKGRWithDevice(pGpu, pKernelGraphicsManager, pDevice, + &grRouteInfo, &pKernelGraphics)); // Get channel from provided handle and owner client NV_CHECK_OK_OR_RETURN(LEVEL_INFO, - CliGetKernelChannel(hClient, pParams->hChannel, &pKernelChannel)); + CliGetKernelChannel(pClient, pParams->hChannel, &pKernelChannel)); NV_CHECK_OK_OR_RETURN(LEVEL_ERROR, kgrctxFromKernelChannel(pKernelChannel, &pKernelGraphicsContext)); @@ -3378,6 +3539,7 @@ OBJGPU *pGpu = GPU_RES_GET_GPU(pSubdevice); KernelGraphicsManager *pKernelGraphicsManager = GPU_GET_KERNEL_GRAPHICS_MANAGER(pGpu); NV2080_CTRL_GR_ROUTE_INFO grRouteInfo; + RsClient *pUserClient; KernelGraphics *pKernelGraphics; KernelChannel *pKernelChannel; KernelGraphicsContext *pKernelGraphicsContext; @@ -3407,14 +3569,19 @@ return status; } - portMemSet(&grRouteInfo, 0, sizeof(grRouteInfo)); - kgrmgrCtrlSetChannelHandle(pParams->hChannel, &grRouteInfo); - NV_CHECK_OK_OR_RETURN(LEVEL_ERROR, - kgrmgrCtrlRouteKGR(pGpu, pKernelGraphicsManager, pParams->hUserClient, &grRouteInfo, &pKernelGraphics)); + NV_CHECK_OK_OR_RETURN(LEVEL_INFO, + serverGetClientUnderLock(&g_resServ, pParams->hUserClient, &pUserClient)); // Get channel from provided handle and owner client NV_CHECK_OK_OR_RETURN(LEVEL_INFO, - CliGetKernelChannel(pParams->hUserClient, pParams->hChannel, &pKernelChannel)); + CliGetKernelChannel(pUserClient, pParams->hChannel, &pKernelChannel)); + + portMemSet(&grRouteInfo, 0, sizeof(grRouteInfo)); + kgrmgrCtrlSetChannelHandle(pParams->hChannel, &grRouteInfo); + NV_CHECK_OK_OR_RETURN(LEVEL_ERROR, + kgrmgrCtrlRouteKGRWithDevice(pGpu, pKernelGraphicsManager, + GPU_RES_GET_DEVICE(pKernelChannel), + &grRouteInfo, &pKernelGraphics)); NV_CHECK_OK_OR_RETURN(LEVEL_ERROR, kgrctxFromKernelChannel(pKernelChannel, &pKernelGraphicsContext)); @@ -3448,6 +3615,7 @@ OBJGPU *pGpu = GPU_RES_GET_GPU(pSubdevice); KernelGraphicsManager *pKernelGraphicsManager = GPU_GET_KERNEL_GRAPHICS_MANAGER(pGpu); NV2080_CTRL_GR_ROUTE_INFO grRouteInfo; + RsClient *pUserClient; KernelGraphics *pKernelGraphics; KernelChannel *pKernelChannel; KernelGraphicsContext *pKernelGraphicsContext; @@ -3483,15 +3651,19 @@ return status; } - portMemSet(&grRouteInfo, 0, sizeof(grRouteInfo)); - - kgrmgrCtrlSetChannelHandle(pParams->hChannel, &grRouteInfo); NV_CHECK_OK_OR_RETURN(LEVEL_INFO, - kgrmgrCtrlRouteKGR(pGpu, pKernelGraphicsManager, pParams->hUserClient, &grRouteInfo, &pKernelGraphics)); + serverGetClientUnderLock(&g_resServ, pParams->hUserClient, &pUserClient)); // Get channel from provided handle and owner client NV_CHECK_OK_OR_RETURN(LEVEL_INFO, - CliGetKernelChannel(pParams->hUserClient, pParams->hChannel, &pKernelChannel)); + CliGetKernelChannel(pUserClient, pParams->hChannel, &pKernelChannel)); + + portMemSet(&grRouteInfo, 0, sizeof(grRouteInfo)); + kgrmgrCtrlSetChannelHandle(pParams->hChannel, &grRouteInfo); + NV_CHECK_OK_OR_RETURN(LEVEL_INFO, + kgrmgrCtrlRouteKGRWithDevice(pGpu, pKernelGraphicsManager, + GPU_RES_GET_DEVICE(pKernelChannel), + &grRouteInfo, &pKernelGraphics)); NV_CHECK_OK_OR_RETURN(LEVEL_ERROR, kgrctxFromKernelChannel(pKernelChannel, &pKernelGraphicsContext)); @@ -3528,12 +3700,13 @@ KernelGraphicsManager *pKernelGraphicsManager = GPU_GET_KERNEL_GRAPHICS_MANAGER(pGpu); KernelGraphics *pKernelGraphics; const KGRAPHICS_STATIC_INFO *pKernelGraphicsStaticInfo; - NvHandle hClient = RES_GET_CLIENT_HANDLE(pSubdevice); + Device *pDevice = GPU_RES_GET_DEVICE(pSubdevice); LOCK_ASSERT_AND_RETURN(rmapiLockIsOwner() && rmGpuLockIsOwner()); NV_CHECK_OK_OR_RETURN(LEVEL_ERROR, - kgrmgrCtrlRouteKGR(pGpu, pKernelGraphicsManager, hClient, &pParams->grRouteInfo, &pKernelGraphics)); + kgrmgrCtrlRouteKGRWithDevice(pGpu, pKernelGraphicsManager, pDevice, + &pParams->grRouteInfo, &pKernelGraphics)); // Verify static info is available pKernelGraphicsStaticInfo = kgraphicsGetStaticInfo(pGpu, pKernelGraphics); diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/kernel/gpu/gr/kernel_graphics_context.c nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/kernel/gpu/gr/kernel_graphics_context.c --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/kernel/gpu/gr/kernel_graphics_context.c 2023-10-25 20:21:04.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/kernel/gpu/gr/kernel_graphics_context.c 2024-03-05 22:13:29.000000000 +0000 @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 2020-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2020-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -21,6 +21,11 @@ * DEALINGS IN THE SOFTWARE. */ +// FIXME XXX +#define NVOC_KERNEL_GRAPHICS_OBJECT_H_PRIVATE_ACCESS_ALLOWED + +#define NVOC_KERNEL_GRAPHICS_CONTEXT_H_PRIVATE_ACCESS_ALLOWED + #include "kernel/gpu/gr/kernel_graphics_context.h" #include "kernel/gpu/gr/kernel_graphics_manager.h" #include "kernel/gpu/gr/kernel_graphics.h" @@ -385,7 +390,7 @@ NV2080_CTRL_GR_CTX_BUFFER_INFO *pCtxBufferInfo ) { - NvU32 pageSize; + NvU64 pageSize; NV_STATUS status; MEMORY_DESCRIPTOR *pRootMemDesc = memdescGetRootMemDesc(pMemDesc, NULL); @@ -547,14 +552,9 @@ KernelGraphicsContextUnicast **ppKernelGraphicsContextUnicast ) { - NvU32 subdevInst = gpumgrGetSubDeviceInstanceFromGpu(pGpu); - + *ppKernelGraphicsContextUnicast = NULL; NV_ASSERT_OR_RETURN(pKernelGraphicsContext->pShared != NULL, NV_ERR_INVALID_STATE); - NV_ASSERT_OR_RETURN(pKernelGraphicsContext->pShared->pKernelGraphicsContextUnicast != NULL, - NV_ERR_INVALID_STATE); - - *ppKernelGraphicsContextUnicast = - &pKernelGraphicsContext->pShared->pKernelGraphicsContextUnicast[subdevInst]; + *ppKernelGraphicsContextUnicast = &pKernelGraphicsContext->pShared->kernelGraphicsContextUnicast; return NV_OK; } @@ -671,6 +671,43 @@ } /*! + * @brief Determine whether channels in this context are associated with GR engine + * + * @returns NV_TRUE if passed channel is allocated on GR, and is on GR runlist + */ +NvBool +kgrctxIsValid_IMPL +( + OBJGPU *pGpu, + KernelGraphicsContext *pKernelGraphicsContext, + KernelChannel *pKernelChannel +) +{ + NvU32 runlistId; + RM_ENGINE_TYPE engineType; + + // TODO remove pKernelChannel from params + + if (RM_ENGINE_TYPE_IS_VALID(kchannelGetEngineType(pKernelChannel)) && + !RM_ENGINE_TYPE_IS_GR(kchannelGetEngineType(pKernelChannel))) + { + return NV_FALSE; + } + + NV_CHECK_OR_RETURN(LEVEL_INFO, kchannelIsRunlistSet(pGpu, pKernelChannel), NV_FALSE); + + runlistId = kchannelGetRunlistId(pKernelChannel); + NV_ASSERT_OK( + kfifoEngineInfoXlate_HAL(pGpu, GPU_GET_KERNEL_FIFO(pGpu), + ENGINE_INFO_TYPE_RUNLIST, runlistId, + ENGINE_INFO_TYPE_RM_ENGINE_TYPE, (NvU32 *) &engineType)); + + NV_CHECK_OR_RETURN(LEVEL_INFO, RM_ENGINE_TYPE_IS_GR(engineType), NV_FALSE); + + return NV_TRUE; +} + +/*! * @brief returns if the main context buffer has been allocated * * @return NV_TRUE if allocated, NV_FALSE otherwise @@ -1332,7 +1369,7 @@ // Allocate Ctx Buffers that are local to this channel if required // and they have yet to be allocated. // - if ((pKernelGraphicsContextUnicast->bVprChannel + if ((pKernelGraphicsContextUnicast->bVprChannel ) && !pKernelGraphicsContextUnicast->localCtxBuffer.bAllocated) { NV_CHECK_OK_OR_RETURN(LEVEL_ERROR, @@ -1965,8 +2002,10 @@ NV_STATUS status = NV_OK; Subdevice *pSubdevice; - pSubdevice = CliGetSubDeviceInfoFromGpu(RES_GET_CLIENT_HANDLE(pKernelChannel), pGpu); - NV_ASSERT_OR_RETURN(pSubdevice != NULL, NV_ERR_INVALID_STATE); + NV_ASSERT_OK_OR_RETURN( + subdeviceGetByGpu(RES_GET_CLIENT(pKernelChannel), pGpu, &pSubdevice)); + + GPU_RES_SET_THREAD_BC_STATE(pSubdevice); NV_ASSERT_OK_OR_RETURN( kgrctxGetUnicast(pGpu, pKernelGraphicsContext, &pKernelGraphicsContextUnicast)); @@ -2244,72 +2283,6 @@ kgraphicsUnmapCtxBuffer(pGpu, pKernelGraphics, pVAS, &pKernelGraphicsContextUnicast->rtvCbCtxswBuffer.vAddrList); } -/*! - * @brief This funciton operates as a last step check before proceeding with unmapping - * various global ctx buffers. - * - * @param[in] pGpu - * @param[in] pKernelGraphicsContext - * @param[in] pKernelChannel KernelChannel attempting to be unmapped - * @param[in] bufId GR_GLOBALCTX_BUFFER checking for un-accounted references - * - * @return NV_FALSE unmapping on bufId can proceed for pKernelChannel's VAS - * @return NV_TRUE References which use the mapping are still alive - */ -NvBool -kgrctxIsFinalGlobalBufMapRefDuped_IMPL -( - OBJGPU *pGpu, - KernelGraphicsContext *pKernelGraphicsContext, - KernelChannel *pKernelChannel, - GR_GLOBALCTX_BUFFER bufId -) -{ - CHANNEL_NODE *pChanNode; - CHANNEL_LIST *pChanList; - KernelGraphicsContextUnicast *pKernelGraphicsContextUnicast; - NV_STATUS status = NV_OK; - NvU64 refCount; - - NV_CHECK_OR_RETURN(LEVEL_ERROR, pKernelChannel != NULL, NV_FALSE); - NV_CHECK_OR_RETURN(LEVEL_ERROR, pKernelChannel->pKernelChannelGroupApi != NULL, NV_FALSE); - NV_CHECK_OR_RETURN(LEVEL_ERROR, pKernelChannel->pKernelChannelGroupApi->pKernelChannelGroup != NULL, NV_FALSE); - - NV_ASSERT_OK_OR_ELSE(status, - kgrctxGetUnicast(pGpu, - pKernelGraphicsContext, - &pKernelGraphicsContextUnicast), - return NV_FALSE;); - - // - // Return NV_FALSE if the VA is not found or the refCount for the channels pVAS is not exactly 1. - // Both cases we want to handle in the unmapping call itself. - // - status = vaListGetRefCount(&pKernelGraphicsContextUnicast->globalCtxBufferVaList[bufId], pKernelChannel->pVAS, &refCount); - if (status != NV_OK || refCount != 1) - { - return NV_FALSE; - } - - pChanList = pKernelChannel->pKernelChannelGroupApi->pKernelChannelGroup->pChanList; - NV_CHECK_OR_RETURN(LEVEL_ERROR, pChanList != NULL, NV_FALSE); - - for (pChanNode = pChanList->pHead; pChanNode; pChanNode = pChanNode->pNext) - { - // Skip the channel we are looking to unmap - if (kchannelGetDebugTag(pKernelChannel) == kchannelGetDebugTag(pChanNode->pKernelChannel)) - continue; - - if (pKernelChannel->pVAS == pChanNode->pKernelChannel->pVAS) - { - NV_PRINTF(LEVEL_INFO, "Channel %d shares a pVAS with channel %d\n", - kchannelGetDebugTag(pKernelChannel), - kchannelGetDebugTag(pChanNode->pKernelChannel)); - return NV_TRUE; - } - } - return NV_FALSE; -} /** * @brief Unmap associated ctx buffers (main, patch, global buffers etc). * @@ -2332,7 +2305,7 @@ NvBool bRelease3d = NV_FALSE; NvU32 gfid = kchannelGetGfid(pKernelChannel); NvU32 status; - NvU64 refCount; + GR_GLOBALCTX_BUFFER registerMapBufferId = kgrctxGetRegisterAccessMapId_HAL(pGpu, pKernelGraphicsContext, pKernelChannel); NV_ASSERT(!gpumgrGetBcEnabledStatus(pGpu)); @@ -2365,28 +2338,54 @@ kgrctxUnmapGlobalCtxBuffers(pGpu, pKernelGraphicsContext, pKernelGraphics, pKernelChannel->pVAS, gfid); } + // + // If multiple channels sharing the same VAS exist, it is possible both + // channels could be using these mappings, and we must wait for both + // channels to be detached before we remove them. + // + if (pKernelChannel->pKernelChannelGroupApi->pKernelChannelGroup->pChanList != NULL) + { + CHANNEL_NODE *pChanNode; + CHANNEL_LIST *pChanList; + + pChanList = pKernelChannel->pKernelChannelGroupApi->pKernelChannelGroup->pChanList; + + for (pChanNode = pChanList->pHead; pChanNode; pChanNode = pChanNode->pNext) + { + // Skip the channel we are looking to unmap + if (kchannelGetDebugTag(pKernelChannel) == kchannelGetDebugTag(pChanNode->pKernelChannel)) + continue; + + if (pKernelChannel->pVAS == pChanNode->pKernelChannel->pVAS) + { + NV_PRINTF(LEVEL_INFO, "TSG %d Channel %d shares a pVAS with channel %d\n", + pKernelChannel->pKernelChannelGroupApi->pKernelChannelGroup->grpID, + kchannelGetDebugTag(pKernelChannel), + kchannelGetDebugTag(pChanNode->pKernelChannel)); + return; + } + } + } + // Only unmap once the last channel using this VAS has gone - if ((kgraphicsGetGlobalCtxBuffers(pGpu, pKernelGraphics, gfid)->memDesc[GR_GLOBALCTX_BUFFER_FECS_EVENT] != NULL) && - (vaListGetRefCount(&pKernelGraphicsContextUnicast->globalCtxBufferVaList[GR_GLOBALCTX_BUFFER_FECS_EVENT], pKernelChannel->pVAS, &refCount) == NV_OK) && - (refCount == 1)) + if (kgraphicsGetGlobalCtxBuffers(pGpu, pKernelGraphics, gfid)->memDesc[GR_GLOBALCTX_BUFFER_FECS_EVENT] != NULL) { - if (!(kgrctxIsFinalGlobalBufMapRefDuped(pGpu, pKernelGraphicsContext, pKernelChannel, GR_GLOBALCTX_BUFFER_FECS_EVENT))) - kgrctxUnmapGlobalCtxBuffer(pGpu, pKernelGraphicsContext, pKernelGraphics, pKernelChannel->pVAS, GR_GLOBALCTX_BUFFER_FECS_EVENT); + kgrctxUnmapGlobalCtxBuffer(pGpu, pKernelGraphicsContext, pKernelGraphics, pKernelChannel->pVAS, GR_GLOBALCTX_BUFFER_FECS_EVENT); } - if ((pKernelGraphicsContextUnicast->pmCtxswBuffer.pMemDesc != NULL) && - (vaListGetRefCount(&pKernelGraphicsContextUnicast->pmCtxswBuffer.vAddrList, pKernelChannel->pVAS, &refCount) == NV_OK) && - (refCount == 1)) + if (pKernelGraphicsContextUnicast->pmCtxswBuffer.pMemDesc != NULL) { kgrctxUnmapCtxPmBuffer(pGpu, pKernelGraphicsContext, pKernelGraphics, pKernelChannel->pVAS); } - // - // When sharing contexts across channels we need to defer this until all - // objects have been freed. - // - NV_CHECK_OR_RETURN_VOID(LEVEL_SILENT, - pKernelGraphicsContextUnicast->channelObjects == 0); + if (kgraphicsDoesUcodeSupportPrivAccessMap(pGpu, pKernelGraphics)) + { + kgrctxUnmapGlobalCtxBuffer(pGpu, + pKernelGraphicsContext, + pKernelGraphics, + pKernelChannel->pVAS, + registerMapBufferId); + } if (pKernelGraphicsContextUnicast->ctxPatchBuffer.pMemDesc != NULL) { @@ -2402,6 +2401,29 @@ // Release all preemption buffers if they were allocated kgrctxUnmapCtxPreemptionBuffers(pGpu, pKernelGraphicsContext, pKernelGraphics, pKernelChannel->pVAS); + // + // Cleanup lingering main ctx buffer mappings for this VAS + // TODO fix main ctx buffer refcounting + // TODO move setEngineContextMemDesc to FreeMainCtxBuffer, move this loop + // inside UnmapMainCtxBuffer + // + if (pKernelChannel->pKernelChannelGroupApi->pKernelChannelGroup->ppEngCtxDesc[gpumgrGetSubDeviceInstanceFromGpu(pGpu)] != NULL) + { + NvU32 subdevInst = gpumgrGetSubDeviceInstanceFromGpu(pGpu); + VA_LIST *pVAddrList = &pKernelChannel->pKernelChannelGroupApi->pKernelChannelGroup->ppEngCtxDesc[subdevInst]->vaList; + NvU64 vaddr; + + while (vaListFindVa(pVAddrList, pKernelChannel->pVAS, &vaddr) == NV_OK) + kgraphicsUnmapCtxBuffer(pGpu, pKernelGraphics, pKernelChannel->pVAS, pVAddrList); + } + + // + // When sharing contexts across channels we need to defer this until all + // objects have been freed. + // + NV_CHECK_OR_RETURN_VOID(LEVEL_SILENT, + pKernelGraphicsContextUnicast->channelObjects == 0); + kgrctxUnmapMainCtxBuffer(pGpu, pKernelGraphicsContext, pKernelGraphics, pKernelChannel); } @@ -2953,6 +2975,7 @@ NvU32 objType; NvU32 gfid; NvU64 refCount; + GR_GLOBALCTX_BUFFER registerMapBufferId = kgrctxGetRegisterAccessMapId_HAL(pGpu, pKernelGraphicsContext, pChannelDescendant->pKernelChannel); NV_PRINTF(LEVEL_INFO, "gpu:%d isBC=%d\n", pGpu->gpuInstance, gpumgrGetBcEnabledStatus(pGpu)); @@ -2999,13 +3022,16 @@ kgrctxUnmapCtxPmBuffer(pGpu, pKernelGraphicsContext, pKernelGraphics, pKernelChannel->pVAS); } - if (kgraphicsDoesUcodeSupportPrivAccessMap(pGpu, pKernelGraphics)) + // Defer releasing mapping if this would cause the buffer to be unmapped + if (kgraphicsDoesUcodeSupportPrivAccessMap(pGpu, pKernelGraphics) && + (vaListGetRefCount(&pKernelGraphicsContextUnicast->globalCtxBufferVaList[registerMapBufferId], pKernelChannel->pVAS, &refCount) == NV_OK) && + (refCount > 1)) { kgrctxUnmapGlobalCtxBuffer(pGpu, pKernelGraphicsContext, pKernelGraphics, pKernelChannel->pVAS, - kgrctxGetRegisterAccessMapId_HAL(pGpu, pKernelGraphicsContext, pChannelDescendant->pKernelChannel)); + registerMapBufferId); } // Defer releasing mapping if this would cause the buffer to be unmapped @@ -3070,6 +3096,7 @@ NV_ASSERT_OK_OR_ELSE(status, kgrctxGetUnicast(pGpu, pKernelGraphicsContext, &pKernelGraphicsContextUnicast), return;); + switch (objType) { case GR_OBJECT_TYPE_COMPUTE: @@ -3355,21 +3382,13 @@ ) { NV_STATUS status = NV_OK; - NvU32 subdevCount = gpumgrGetSubDeviceMaxValuePlus1(pGpu); - - pKernelGraphicsContextShared->pKernelGraphicsContextUnicast = - portMemAllocNonPaged(subdevCount * sizeof(*pKernelGraphicsContextShared->pKernelGraphicsContextUnicast)); - if (pKernelGraphicsContextShared->pKernelGraphicsContextUnicast == NULL) - return NV_ERR_NO_MEMORY; - portMemSet(pKernelGraphicsContextShared->pKernelGraphicsContextUnicast, 0, - subdevCount * sizeof(*pKernelGraphicsContextShared->pKernelGraphicsContextUnicast)); SLI_LOOP_START(SLI_LOOP_FLAGS_BC_ONLY) { + KernelGraphicsContextUnicast *pKernelGraphicsContextUnicast; KernelGraphicsManager *pKernelGraphicsManager = GPU_GET_KERNEL_GRAPHICS_MANAGER(pGpu); KernelGraphics *pKernelGraphics; NV2080_CTRL_GR_ROUTE_INFO grRouteInfo; - NvU32 subdevInst = gpumgrGetSubDeviceInstanceFromGpu(pGpu); NvHandle hClient = RES_GET_CLIENT_HANDLE(pKernelGraphicsContext); NvHandle hParent = RES_GET_PARENT_HANDLE(pKernelGraphicsContext); @@ -3382,14 +3401,14 @@ if (status != NV_OK) SLI_LOOP_BREAK; - NV_CHECK_OK_OR_CAPTURE_FIRST_ERROR(status, LEVEL_ERROR, - shrkgrctxConstructUnicast(pGpu, pKernelGraphicsContextShared, - pKernelGraphicsContext, - pKernelGraphics, - &pKernelGraphicsContextShared->pKernelGraphicsContextUnicast[subdevInst])); + if (kgrctxGetUnicast(pGpu, pKernelGraphicsContext, &pKernelGraphicsContextUnicast) == NV_OK) + { + NV_CHECK_OK_OR_CAPTURE_FIRST_ERROR(status, LEVEL_ERROR, + shrkgrctxConstructUnicast(pGpu, pKernelGraphicsContextShared, pKernelGraphicsContext, pKernelGraphics, pKernelGraphicsContextUnicast)); - if (status != NV_OK) - SLI_LOOP_BREAK; + if (status != NV_OK) + SLI_LOOP_BREAK; + } } SLI_LOOP_END; @@ -3459,20 +3478,17 @@ KernelGraphicsContext *pKernelGraphicsContext ) { - if (pKernelGraphicsContextShared->pKernelGraphicsContextUnicast != NULL) + + SLI_LOOP_START(SLI_LOOP_FLAGS_BC_ONLY) { - SLI_LOOP_START(SLI_LOOP_FLAGS_BC_ONLY) - { - NvU32 subdevInst = gpumgrGetSubDeviceInstanceFromGpu(pGpu); - shrkgrctxDestructUnicast(pGpu, pKernelGraphicsContextShared, - pKernelGraphicsContext, - &pKernelGraphicsContextShared->pKernelGraphicsContextUnicast[subdevInst]); - } - SLI_LOOP_END; + KernelGraphicsContextUnicast *pKernelGraphicsContextUnicast; + + if (kgrctxGetUnicast(pGpu, pKernelGraphicsContext, &pKernelGraphicsContextUnicast) == NV_OK) + shrkgrctxDestructUnicast(pGpu, pKernelGraphicsContextShared, pKernelGraphicsContext, pKernelGraphicsContextUnicast); } + SLI_LOOP_END; - portMemFree(pKernelGraphicsContextShared->pKernelGraphicsContextUnicast); - pKernelGraphicsContextShared->pKernelGraphicsContextUnicast = NULL; + portMemSet(&pKernelGraphicsContext->pShared->kernelGraphicsContextUnicast, 0x0, sizeof(pKernelGraphicsContext->pShared->kernelGraphicsContextUnicast)); } /*! @@ -3569,16 +3585,13 @@ if (!kgrctxShouldCleanup(pGpu, pKernelGraphicsContext)) return; - - if (pKernelGraphicsContextShared->pKernelGraphicsContextUnicast != NULL) + SLI_LOOP_START(SLI_LOOP_FLAGS_BC_ONLY) { - SLI_LOOP_START(SLI_LOOP_FLAGS_BC_ONLY) - { - NvU32 subdevInst = gpumgrGetSubDeviceInstanceFromGpu(pGpu); - kgrctxUnmapBuffers_HAL(pGpu, pKernelGraphicsContext, - &pKernelGraphicsContextShared->pKernelGraphicsContextUnicast[subdevInst], - pKernelChannel); - } - SLI_LOOP_END; + KernelGraphicsContextUnicast *pKernelGraphicsContextUnicast; + + if (kgrctxGetUnicast(pGpu, pKernelGraphicsContext, &pKernelGraphicsContextUnicast) == NV_OK) + kgrctxUnmapBuffers_HAL(pGpu, pKernelGraphicsContext, pKernelGraphicsContextUnicast, pKernelChannel); } + SLI_LOOP_END; } + diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/kernel/gpu/gr/kernel_graphics_manager.c nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/kernel/gpu/gr/kernel_graphics_manager.c --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/kernel/gpu/gr/kernel_graphics_manager.c 2023-10-25 20:21:04.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/kernel/gpu/gr/kernel_graphics_manager.c 2024-03-05 22:13:29.000000000 +0000 @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 2021-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2021-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -21,9 +21,12 @@ * DEALINGS IN THE SOFTWARE. */ +#define NVOC_KERNEL_GRAPHICS_MANAGER_H_PRIVATE_ACCESS_ALLOWED + #include "kernel/gpu/gr/kernel_graphics_manager.h" #include "kernel/gpu/gr/kernel_graphics.h" +#include "kernel/gpu/device/device.h" #include "kernel/gpu/fifo/kernel_channel_group_api.h" #include "kernel/gpu/fifo/kernel_channel_group.h" @@ -380,6 +383,50 @@ KernelGraphics **ppKernelGraphics ) { + RsClient *pClient; + Device *pDevice; + + if (!IS_MIG_IN_USE(pGpu)) + { + KernelGraphics *pKernelGraphics = GPU_GET_KERNEL_GRAPHICS(pGpu, 0); + + NV_ASSERT_OR_RETURN(pKernelGraphics != NULL, NV_ERR_INVALID_STATE); + + if (ppKernelGraphics != NULL) + *ppKernelGraphics = pKernelGraphics; + + return NV_OK; + } + + NV_ASSERT_OK_OR_RETURN( + serverGetClientUnderLock(&g_resServ, hClient, &pClient)); + + NV_ASSERT_OK_OR_RETURN( + deviceGetByGpu(pClient, pGpu, NV_TRUE, &pDevice)); + + return kgrmgrCtrlRouteKGRWithDevice(pGpu, pKernelGraphicsManager, pDevice, + pGrRouteInfo, ppKernelGraphics); +} + +/*! + * @brief Retrieves associated KernelGraphics engine for given device / route info + * + * @param[in] pGpu + * @param[in] pKernelGraphicsManager + * @param[in] pDevice + * @param[in] grRouteInfo Client-provided info to direct GR accesses + * @param[out] ppKernelGraphics (Optional) Ptr to store appropriate KernelGraphics *, if desired. + */ +NV_STATUS +kgrmgrCtrlRouteKGRWithDevice_IMPL +( + OBJGPU *pGpu, + KernelGraphicsManager *pKernelGraphicsManager, + Device *pDevice, + const NV2080_CTRL_GR_ROUTE_INFO *pGrRouteInfo, + KernelGraphics **ppKernelGraphics +) +{ MIG_INSTANCE_REF ref; KernelGraphics *pKernelGraphics; NvU32 type; @@ -387,6 +434,7 @@ NvU32 grIdx; NV2080_CTRL_GR_ROUTE_INFO grRouteInfo = *pGrRouteInfo; KernelMIGManager *pKernelMIGManager = GPU_GET_KERNEL_MIG_MANAGER(pGpu); + RsClient *pClient; if (!IS_MIG_IN_USE(pGpu)) { @@ -394,8 +442,10 @@ goto done; } + pClient = RES_GET_CLIENT(pDevice); + NV_CHECK_OK_OR_RETURN(LEVEL_ERROR, - kmigmgrGetInstanceRefFromClient(pGpu, pKernelMIGManager, hClient, &ref)); + kmigmgrGetInstanceRefFromDevice(pGpu, pKernelMIGManager, pDevice, &ref)); // // Compute instances always have 1 GR engine, so automatically fill in @@ -408,8 +458,13 @@ } else { - RS_PRIV_LEVEL privLevel = rmclientGetCachedPrivilegeByHandle(hClient); - if (!rmclientIsAdminByHandle(hClient, privLevel) && + RmClient *pRmClient = dynamicCast(pClient, RmClient); + + if (pRmClient == NULL) + return NV_ERR_INVALID_OBJECT_HANDLE; + + RS_PRIV_LEVEL privLevel = rmclientGetCachedPrivilege(pRmClient); + if (!rmclientIsAdmin(pRmClient, privLevel) && _kgrmgrGPUInstanceHasComputeInstances(pGpu, pKernelGraphicsManager, ref.pKernelMIGGpuInstance)) { return NV_ERR_INSUFFICIENT_PERMISSIONS; @@ -448,7 +503,7 @@ NvHandle hChannel = DRF_VAL64(2080_CTRL_GR, _ROUTE_INFO_DATA, _CHANNEL_HANDLE, grRouteInfo.route); - status = CliGetKernelChannel(hClient, hChannel, &pKernelChannel); + status = CliGetKernelChannel(pClient, hChannel, &pKernelChannel); if (status != NV_OK) { RsResourceRef *pChanGrpRef; @@ -459,12 +514,13 @@ // If retrieving a channel with the given hChannel doesn't work, // try interpreting it as a handle to a channel group instead. // - status = CliGetChannelGroup(hClient, hChannel, &pChanGrpRef, NULL); + status = CliGetChannelGroup(pClient->hClient, hChannel, + &pChanGrpRef, NULL); if (NV_OK != status) { NV_PRINTF(LEVEL_ERROR, "Failed to find a channel or TSG with given handle 0x%08x associated with hClient=0x%08x\n", - hChannel, hClient); + hChannel, pClient->hClient); return NV_ERR_INVALID_ARGUMENT; } @@ -533,6 +589,21 @@ } /*! + * @return legacy physical GFX GPC mask enumerated by this chip + */ +NvU32 +kgrmgrGetLegacyPhysGfxGpcMask_IMPL +( + OBJGPU *pGpu, + KernelGraphicsManager *pKernelGraphicsManager +) +{ + NV_ASSERT_OR_RETURN(pKernelGraphicsManager->legacyKgraphicsStaticInfo.bInitialized, 0); + + return pKernelGraphicsManager->legacyKgraphicsStaticInfo.floorsweepingMasks.physGfxGpcMask; +} + +/*! * @return legacy TPC mask for certain GPC * * @param[in] pGpu @@ -652,7 +723,7 @@ veidStart = (veidSpanOffset * maxVeidsPerGpc) + pKernelMIGGPUInstance->resourceAllocation.veidOffset; veidEnd = veidStart + veidCount - 1; - + NV_ASSERT_OR_RETURN(veidStart < veidEnd, NV_ERR_INVALID_STATE); NV_ASSERT_OR_RETURN(veidStart < 64, NV_ERR_INVALID_ARGUMENT); NV_ASSERT_OR_RETURN(veidEnd < 64, NV_ERR_INVALID_ARGUMENT); @@ -796,8 +867,6 @@ ) { KernelMIGManager *pKernelMIGManager = GPU_GET_KERNEL_MIG_MANAGER(pGpu); - const KGRAPHICS_STATIC_INFO *pKernelGraphicsStaticInfo = kgraphicsGetStaticInfo(pGpu, pKernelGraphics); - NvU32 bufId; // // Most of GR is stub'd so context related things are not needed in AMODEL. @@ -810,43 +879,7 @@ NV_CHECK_OR_RETURN(LEVEL_SILENT, kmigmgrIsMemoryPartitioningNeeded_HAL(pGpu, pKernelMIGManager, swizzId), NV_OK); - // Make sure sizes of all buffers are setup - NV_ASSERT_OK_OR_RETURN( - kgraphicsInitializeDeferredStaticData(pGpu, pKernelGraphics, NV01_NULL_OBJECT, NV01_NULL_OBJECT)); - - NV_ASSERT_OR_RETURN(pKernelGraphicsStaticInfo->pContextBuffersInfo != NULL, NV_ERR_INVALID_STATE); - - // Get sizes of local ctx buffers - FOR_EACH_IN_ENUM(GR_CTX_BUFFER, bufId) - { - if (bufId == GR_CTX_BUFFER_MAIN) - { - NvU32 size; - - // Get size of main buffer including subctx headers - NV_ASSERT_OK_OR_RETURN(kgraphicsGetMainCtxBufferSize(pGpu, pKernelGraphics, NV_TRUE, &size)); - kgraphicsSetCtxBufferInfo(pGpu, pKernelGraphics, bufId, - size, - RM_PAGE_SIZE, - RM_ATTR_PAGE_SIZE_4KB, - kgraphicsShouldForceMainCtxContiguity_HAL(pGpu, pKernelGraphics)); - } - else - { - NvU32 fifoEngineId; - - NV_ASSERT_OK_OR_RETURN( - kgrctxCtxBufferToFifoEngineId(bufId, &fifoEngineId)); - - kgraphicsSetCtxBufferInfo(pGpu, pKernelGraphics, bufId, - pKernelGraphicsStaticInfo->pContextBuffersInfo->engine[fifoEngineId].size, - RM_PAGE_SIZE, - RM_ATTR_PAGE_SIZE_4KB, - ((bufId == GR_CTX_BUFFER_PATCH) || (bufId == GR_CTX_BUFFER_PM))); - } - } - FOR_EACH_IN_ENUM_END; - return NV_OK; + return kgraphicsDiscoverMaxLocalCtxBufferSize(pGpu, pKernelGraphics); } /*! @@ -1026,7 +1059,7 @@ NV_PRINTF(LEVEL_ERROR, "veidCount %d is not aligned to maxVeidsPerGpc=%d\n", veidCount, maxVeidsPerGpc); return NV_ERR_INVALID_ARGUMENT; } - + // Create a mask for VEIDs associated with this GPU instance GPUInstanceVeidEnd = pKernelMIGGPUInstance->resourceAllocation.veidOffset + pKernelMIGGPUInstance->resourceAllocation.veidCount - 1; GPUInstanceVeidMask = DRF_SHIFTMASK64(GPUInstanceVeidEnd:pKernelMIGGPUInstance->resourceAllocation.veidOffset); @@ -1045,7 +1078,7 @@ NV_ASSERT_OR_RETURN(veidEnd < 64, NV_ERR_INVALID_ARGUMENT); } else - { + { NvU64 reqVeidMask = DRF_SHIFTMASK64(veidCount - 1:0); NvU32 i; diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/kernel/gpu/gr/kernel_graphics_object.c nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/kernel/gpu/gr/kernel_graphics_object.c --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/kernel/gpu/gr/kernel_graphics_object.c 2023-10-25 20:21:04.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/kernel/gpu/gr/kernel_graphics_object.c 2024-03-05 22:13:29.000000000 +0000 @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 1993-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 1993-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -21,6 +21,8 @@ * DEALINGS IN THE SOFTWARE. */ +#define NVOC_KERNEL_GRAPHICS_OBJECT_H_PRIVATE_ACCESS_ALLOWED + #include "kernel/gpu/gr/kernel_graphics_manager.h" #include "kernel/gpu/gr/kernel_graphics.h" #include "kernel/core/locks.h" @@ -65,8 +67,10 @@ if (IS_MODS_AMODEL(pGpu)) return NV_OK; - pSubdevice = CliGetSubDeviceInfoFromGpu(RES_GET_CLIENT_HANDLE(pKernelGraphicsObject), pGpu); - NV_ASSERT_OR_RETURN(pSubdevice != NULL, NV_ERR_INVALID_STATE); + NV_ASSERT_OK_OR_RETURN( + subdeviceGetByGpu(RES_GET_CLIENT(pKernelGraphicsObject), pGpu, &pSubdevice)); + + GPU_RES_SET_THREAD_BC_STATE(pSubdevice); kgrobjGetPromoteIds_HAL(pGpu, pKernelGraphicsObject, NV_ARRAY_ELEMENTS(promoteIds), @@ -194,8 +198,6 @@ kgraphicsInitializeDeferredStaticData(pGpu, pKernelGraphics, NV01_NULL_OBJECT, NV01_NULL_OBJECT)); } - pKernelGraphics->globalCtxBuffersInfo.pGlobalCtxBuffers[gfid].bFecsTraceUnsupportedInGuest = NV_FALSE; - // Allocate FECS buffer in Guest for SRIOV configs. if (kgrctxShouldManageCtxBuffers_HAL(pGpu, pKernelGraphicsObject->pKernelGraphicsContext, gfid) || IS_VIRTUAL_WITH_SRIOV(pGpu)) { @@ -245,7 +247,6 @@ NvHandle hClient = RES_GET_CLIENT_HANDLE(pChannelDescendant); NvHandle hParent = RES_GET_PARENT_HANDLE(pChannelDescendant); NvU32 classNum = pChannelDescendant->resourceDesc.externalClassId; - NvU32 gfid = kchannelGetGfid(pChannelDescendant->pKernelChannel); // If MIG is enabled, perform GR instance routing based upon parent channel handle kgrmgrCtrlSetChannelHandle(hParent, &grRouteInfo); @@ -255,8 +256,6 @@ if (status != NV_OK) SLI_LOOP_CONTINUE; - pKernelGraphics->globalCtxBuffersInfo.pGlobalCtxBuffers[gfid].bFecsTraceUnsupportedInGuest = NV_FALSE; - // Free Compute Mmio mapping kgrobjFreeComputeMmio_HAL(pGpu, pKernelGraphicsObject); diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/kernel/gpu/gr/kernel_sm_debugger_session.c nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/kernel/gpu/gr/kernel_sm_debugger_session.c --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/kernel/gpu/gr/kernel_sm_debugger_session.c 2023-10-25 20:21:04.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/kernel/gpu/gr/kernel_sm_debugger_session.c 2024-03-05 22:13:29.000000000 +0000 @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 1993-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 1993-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -21,6 +21,11 @@ * DEALINGS IN THE SOFTWARE. */ +#define NVOC_KERNEL_SM_DEBUGGER_SESSION_H_PRIVATE_ACCESS_ALLOWED + +// FIXME XXX +#define NVOC_KERNEL_GRAPHICS_OBJECT_H_PRIVATE_ACCESS_ALLOWED + #include "kernel/os/os.h" #include "kernel/core/locks.h" #include "kernel/gpu/gr/kernel_sm_debugger_session.h" @@ -126,7 +131,8 @@ NV01_NULL_OBJECT, NV01_NULL_OBJECT, NV01_ROOT, - &pKernelSMDebuggerSession->hInternalClient), + &pKernelSMDebuggerSession->hInternalClient, + sizeof(pKernelSMDebuggerSession->hInternalClient)), failed); // Allocate a device. @@ -143,7 +149,8 @@ pKernelSMDebuggerSession->hInternalClient, pKernelSMDebuggerSession->hInternalDevice, NV01_DEVICE_0, - &nv0080AllocParams), + &nv0080AllocParams, + sizeof(nv0080AllocParams)), failed); // Allocate a subdevice. @@ -159,7 +166,8 @@ pKernelSMDebuggerSession->hInternalDevice, pKernelSMDebuggerSession->hInternalSubdevice, NV20_SUBDEVICE_0, - &nv2080AllocParams), + &nv2080AllocParams, + sizeof(nv2080AllocParams)), failed); if (bMIGInUse) @@ -183,7 +191,8 @@ pKernelSMDebuggerSession->hInternalSubdevice, pKernelSMDebuggerSession->hInternalSubscription, AMPERE_SMC_PARTITION_REF, - &nvC637AllocParams), + &nvC637AllocParams, + sizeof(nvC637AllocParams)), failed); } @@ -219,6 +228,7 @@ NvHandle hSubdevice; NV_STATUS status = NV_OK; RsClient *pAppClient; + Subdevice *pSubdevice; RsResourceRef *pGrResourceRef; RsResourceRef *pParentRef; @@ -306,8 +316,11 @@ NV_CHECK_OR_RETURN(LEVEL_ERROR, pGpu == GPU_RES_GET_GPU(pKernelSMDebuggerSession->pObject), NV_ERR_INVALID_ARGUMENT); - NV_CHECK_OK_OR_RETURN(LEVEL_ERROR, - CliGetSubDeviceHandleFromGpu(pAppClient->hClient, pGpu, &hSubdevice)); + NV_CHECK_OK_OR_RETURN(LEVEL_ERROR, subdeviceGetByGpu(pAppClient, pGpu, &pSubdevice)); + + GPU_RES_SET_THREAD_BC_STATE(pSubdevice); + + hSubdevice = RES_GET_HANDLE(pSubdevice); // Initialize the object info pKernelSMDebuggerSession->hChannelClient = pAppClient->hClient; diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/kernel/gpu/gr/kernel_sm_debugger_session_ctrl.c nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/kernel/gpu/gr/kernel_sm_debugger_session_ctrl.c --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/kernel/gpu/gr/kernel_sm_debugger_session_ctrl.c 2023-10-25 20:21:05.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/kernel/gpu/gr/kernel_sm_debugger_session_ctrl.c 2024-03-05 22:13:29.000000000 +0000 @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 1993-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 1993-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -30,6 +30,11 @@ * * \***************************************************************************/ +#define NVOC_KERNEL_SM_DEBUGGER_SESSION_H_PRIVATE_ACCESS_ALLOWED + +// FIXME XXX +#define NVOC_KERNEL_GRAPHICS_OBJECT_H_PRIVATE_ACCESS_ALLOWED + #include "kernel/rmapi/control.h" #include "kernel/rmapi/rmapi.h" #include "kernel/os/os.h" @@ -58,14 +63,14 @@ // for the caller to explicitly pass in the handle corresponding to the VaSpaceApi: // static NV_STATUS -_nv83deCtrlCmdFetchVAS(NvU32 hClient, NvU32 hChannel, OBJVASPACE **ppVASpace) +_nv83deCtrlCmdFetchVAS(RsClient *pClient, NvU32 hChannel, OBJVASPACE **ppVASpace) { KernelChannel *pKernelChannel = NULL; NV_ASSERT_OR_RETURN(ppVASpace != NULL, NV_ERR_INVALID_ARGUMENT); // Fetch the corresponding Channel object from our handle - NV_ASSERT_OK_OR_RETURN(CliGetKernelChannel(hClient, hChannel, &pKernelChannel)); + NV_ASSERT_OK_OR_RETURN(CliGetKernelChannel(pClient, hChannel, &pKernelChannel)); NV_ASSERT_OR_RETURN(pKernelChannel != NULL, NV_ERR_INVALID_ARGUMENT); *ppVASpace = pKernelChannel->pVAS; @@ -148,7 +153,7 @@ ) { OBJGPU *pGpu = GPU_RES_GET_GPU(pKernelSMDebuggerSession); - NvHandle hClient = RES_GET_CLIENT_HANDLE(pKernelSMDebuggerSession); + RsClient *pClient = RES_GET_CLIENT(pKernelSMDebuggerSession); OBJVASPACE *pVASpace = NULL; NvU32 count = pParams->count; NvU32 i; @@ -161,7 +166,7 @@ // Attempt to retrieve the VAS pointer NV_ASSERT_OK_OR_RETURN( - _nv83deCtrlCmdFetchVAS(hClient, pKernelSMDebuggerSession->hChannel, &pVASpace)); + _nv83deCtrlCmdFetchVAS(pClient, pKernelSMDebuggerSession->hChannel, &pVASpace)); // Validate VA range and fail if invalid NV_ASSERT_OK_OR_RETURN( @@ -169,7 +174,6 @@ for (i = 0; i < count; i++) { - NvU8 *pBase; MEMORY_DESCRIPTOR *pMemDesc = NULL; NvU64 virtAddr = pParams->opsBuffer[i].gpuVA; NvP64 bufPtr = pParams->opsBuffer[i].pCpuVA; @@ -191,8 +195,11 @@ for (cur4kPage = start4kPage; cur4kPage <= end4kPage; ++cur4kPage) { - MMU_TRACE_PARAM mmuParams = {0}; - MMU_TRACE_ARG traceArg = {0}; + MMU_TRACE_PARAM mmuParams = {0}; + MMU_TRACE_ARG traceArg = {0}; + TRANSFER_SURFACE surf = {0}; + MemoryManager *pMemoryManager = GPU_GET_MEMORY_MANAGER(pGpu); + NvU8 *pKernBuffer = NULL; mmuParams.mode = MMU_TRACE_MODE_TRANSLATE; mmuParams.va = virtAddr; @@ -207,6 +214,12 @@ curSize = bufSize; } + pKernBuffer = portMemAllocNonPaged(curSize); + if (pKernBuffer == NULL) + { + return NV_ERR_INSUFFICIENT_RESOURCES; + } + if (traceArg.aperture == ADDR_SYSMEM) { NvP64 physAddr = NV_PTR_TO_NvP64(traceArg.pa); @@ -217,7 +230,7 @@ DRF_DEF(OS02, _FLAGS, _PHYSICALITY, _CONTIGUOUS) | DRF_DEF(OS02, _FLAGS, _COHERENCY, _CACHED); - NV_CHECK_OK_OR_RETURN(LEVEL_ERROR, + NV_ASSERT_OK_OR_ELSE(status, osCreateMemFromOsDescriptor(pGpu, physAddr, pKernelSMDebuggerSession->hInternalClient, @@ -225,39 +238,55 @@ &limit, &pMemDesc, NVOS32_DESCRIPTOR_TYPE_OS_PHYS_ADDR, - RS_PRIV_LEVEL_KERNEL)); + RS_PRIV_LEVEL_KERNEL), + portMemFree(pKernBuffer); return status; ); } else if (traceArg.aperture == ADDR_FBMEM) { - NV_ASSERT_OK_OR_RETURN(memdescCreate(&pMemDesc, pGpu, curSize, 0, NV_TRUE, - traceArg.aperture, NV_MEMORY_UNCACHED, MEMDESC_FLAGS_NONE)); + NV_ASSERT_OK_OR_ELSE(status, + memdescCreate(&pMemDesc, pGpu, curSize, 0, NV_TRUE, + traceArg.aperture, NV_MEMORY_UNCACHED, + MEMDESC_FLAGS_NONE), + portMemFree(pKernBuffer); return status; ); memdescDescribe(pMemDesc, traceArg.aperture, traceArg.pa, curSize); } - pBase = kbusMapRmAperture_HAL(pGpu, pMemDesc); - NV_ASSERT_OR_ELSE( - pBase != NULL, - memdescDestroy(pMemDesc); - return NV_ERR_INVALID_ARGUMENT; ); + surf.pMemDesc = pMemDesc; + surf.offset = pageStartOffset; if (bWrite) { NV_ASSERT_OK_OR_CAPTURE_FIRST_ERROR(status, - portMemExCopyFromUser(bufPtr, pBase + pageStartOffset, curSize)); + portMemExCopyFromUser(bufPtr, pKernBuffer, curSize)); + + // Write out the buffer to memory + if (status == NV_OK) + { + NV_ASSERT_OK_OR_CAPTURE_FIRST_ERROR(status, + memmgrMemWrite(pMemoryManager, &surf, pKernBuffer, curSize, + TRANSFER_FLAGS_DEFER_FLUSH)); + } } else { + // Read from memory NV_ASSERT_OK_OR_CAPTURE_FIRST_ERROR(status, - portMemExCopyToUser(pBase + pageStartOffset, bufPtr, curSize)); + memmgrMemRead(pMemoryManager, &surf, pKernBuffer, curSize, + TRANSFER_FLAGS_DEFER_FLUSH)); + + if (status == NV_OK) + { + NV_ASSERT_OK_OR_CAPTURE_FIRST_ERROR(status, + portMemExCopyToUser(pKernBuffer, bufPtr, curSize)); + } } - kbusUnmapRmAperture_HAL(pGpu, pMemDesc, &pBase, NV_FALSE); + portMemFree(pKernBuffer); memdescDestroy(pMemDesc); if (status != NV_OK) return status; - pBase = NULL; pageStartOffset = 0; bufPtr = NvP64_PLUS_OFFSET(bufPtr,curSize); bufSize -= curSize; @@ -297,7 +326,7 @@ ) { OBJGPU *pGpu = GPU_RES_GET_GPU(pKernelSMDebuggerSession); - NvHandle hClient = RES_GET_CLIENT_HANDLE(pKernelSMDebuggerSession); + RsClient *pClient = RES_GET_CLIENT(pKernelSMDebuggerSession); OBJVASPACE *pVASpace = NULL; MMU_TRACE_ARG traceArg = {0}; MMU_TRACE_PARAM mmuParams = {0}; @@ -306,7 +335,7 @@ // Attempt to retrieve the VAS pointer NV_ASSERT_OK_OR_RETURN( - _nv83deCtrlCmdFetchVAS(hClient, pKernelSMDebuggerSession->hChannel, &pVASpace)); + _nv83deCtrlCmdFetchVAS(pClient, pKernelSMDebuggerSession->hChannel, &pVASpace)); traceArg.pMapParams = pParams; diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/kernel/gpu/gsp/arch/ada/kernel_gsp_ad102.c nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/kernel/gpu/gsp/arch/ada/kernel_gsp_ad102.c --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/kernel/gpu/gsp/arch/ada/kernel_gsp_ad102.c 2023-10-25 20:21:05.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/kernel/gpu/gsp/arch/ada/kernel_gsp_ad102.c 2024-03-05 22:13:29.000000000 +0000 @@ -85,28 +85,3 @@ return status; } -NvU64 -kgspGetWprHeapSize_AD102 -( - OBJGPU *pGpu, - KernelGsp *pKernelGsp -) -{ - if (pGpu->bVgpuGspPluginOffloadEnabled) - { - // - // Memory calculations which we used to size the WPR heap: - // Memory needed for libOS kernel - 10MB(RM) + 32MB(VF partitions) + 8MB(global page) = 50MB - // Memory needed from FW's Heap - 17MB for RM + 15MB * 32(VF) = 497MB - // Total Memory needed = 497MB + 50MB = 547MB - // (Added extra 2 Mb due to alignment) - // @TODO: Change total Heap size to 546MB once fix for making global page to 4MB submitted. - // - return 550 * 1024 * 1024; - } - else - { - // GSP-RM WPR heap (96MB) + libos3 (16MB) - return 112 * 1024 * 1024; - } -} \ No newline at end of file diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/kernel/gpu/gsp/arch/ampere/kernel_gsp_ga102.c nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/kernel/gpu/gsp/arch/ampere/kernel_gsp_ga102.c --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/kernel/gpu/gsp/arch/ampere/kernel_gsp_ga102.c 2023-10-25 20:21:05.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/kernel/gpu/gsp/arch/ampere/kernel_gsp_ga102.c 2024-03-05 22:13:29.000000000 +0000 @@ -28,6 +28,8 @@ #include "gpu/gsp/kernel_gsp.h" #include "gpu/bus/kern_bus.h" +#include "gpu/conf_compute/conf_compute.h" +#include "nverror.h" #include "rmgspseq.h" #include "vgpu/rpc.h" @@ -61,6 +63,21 @@ falconConfig.bIsPmcDeviceEngine = NV_FALSE; falconConfig.physEngDesc = ENG_GSP; + + ConfidentialCompute *pCC = GPU_GET_CONF_COMPUTE(pGpu); + + // + // No CrashCat queue when CC is enabled, as it's not encrypted. + // Don't bother enabling the host-side decoding either. + // + if (pCC == NULL || !pCC->getProperty(pCC, PDB_PROP_CONFCOMPUTE_CC_FEATURE_ENABLED)) + { + // Enable CrashCat monitoring + falconConfig.crashcatEngConfig.bEnable = NV_TRUE; + falconConfig.crashcatEngConfig.pName = MAKE_NV_PRINTF_STR("GSP"); + falconConfig.crashcatEngConfig.errorId = GSP_ERROR; + } + kflcnConfigureEngine(pGpu, staticCast(pKernelGsp, KernelFalcon), &falconConfig); } @@ -310,32 +327,6 @@ switch (opCode) { - case GSP_SEQ_BUF_OPCODE_CORE_RESET: - { - NV_ASSERT_OR_RETURN(payloadSize == 0, NV_ERR_INVALID_ARGUMENT); - - // Reset falcon - kflcnEnable_HAL(pGpu, pKernelFalcon, NV_FALSE); - kflcnEnable_HAL(pGpu, pKernelFalcon, NV_TRUE); - - kflcnDisableCtxReq_HAL(pGpu, pKernelFalcon); - break; - } - case GSP_SEQ_BUF_OPCODE_CORE_START: - { - NV_ASSERT_OR_RETURN(payloadSize == 0, NV_ERR_INVALID_ARGUMENT); - - kflcnStartCpu_HAL(pGpu, pKernelFalcon); - break; - } - case GSP_SEQ_BUF_OPCODE_CORE_WAIT_FOR_HALT: - { - NV_ASSERT_OR_RETURN(payloadSize == 0, NV_ERR_INVALID_ARGUMENT); - - // Wait for the bootloader to complete execution. - status = kflcnWaitForHalt_HAL(pGpu, pKernelFalcon, GPU_TIMEOUT_DEFAULT, 0); - break; - } case GSP_SEQ_BUF_OPCODE_CORE_RESUME: { RM_RISCV_UCODE_DESC *pRiscvDesc = pKernelGsp->pGspRmBootUcodeDesc; @@ -357,7 +348,7 @@ // Wait for reload to be completed. status = gpuTimeoutCondWait(pGpu, _kgspIsReloadCompleted, NULL, NULL); - // Check SEC mailbox. + // Check SEC mailbox. secMailbox0 = kflcnRegRead_HAL(pGpu, pKernelSec2Falcon, NV_PFALCON_FALCON_MAILBOX0); if ((status != NV_OK) || (secMailbox0 != NV_OK)) diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/kernel/gpu/gsp/arch/hopper/kernel_gsp_gh100.c nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/kernel/gpu/gsp/arch/hopper/kernel_gsp_gh100.c --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/kernel/gpu/gsp/arch/hopper/kernel_gsp_gh100.c 2023-10-25 20:21:05.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/kernel/gpu/gsp/arch/hopper/kernel_gsp_gh100.c 2024-03-05 22:13:29.000000000 +0000 @@ -26,6 +26,7 @@ */ #include "rmconfig.h" +#include "gpu/conf_compute/conf_compute.h" #include "gpu/fsp/kern_fsp.h" #include "gpu/gsp/kernel_gsp.h" #include "gpu/mem_sys/kern_mem_sys.h" @@ -45,6 +46,9 @@ KernelGsp *pKernelGsp ) { + ConfidentialCompute *pCC = GPU_GET_CONF_COMPUTE(pGpu); + if (pCC != NULL && pCC->getProperty(pCC, PDB_PROP_CONFCOMPUTE_CC_FEATURE_ENABLED)) + return GSP_CC_SIGNATURE_SECTION_NAME_PREFIX; return GSP_SIGNATURE_SECTION_NAME_PREFIX; } @@ -143,13 +147,16 @@ NvP64 pVa = NvP64_NULL; NvP64 pPriv = NvP64_NULL; NV_STATUS nvStatus = NV_OK; + NvU64 flags = MEMDESC_FLAGS_NONE; + + flags |= MEMDESC_FLAGS_ALLOC_IN_UNPROTECTED_MEMORY; // Allocate GSP-FMC arguments NV_ASSERT_OK_OR_GOTO(nvStatus, memdescCreate(&pKernelGsp->pGspFmcArgumentsDescriptor, pGpu, sizeof(GSP_FMC_BOOT_PARAMS), 0x1000, NV_TRUE, ADDR_SYSMEM, NV_MEMORY_CACHED, - MEMDESC_FLAGS_NONE), + flags), _kgspAllocBootArgs_exit_cleanup); NV_ASSERT_OK_OR_GOTO(nvStatus, @@ -207,6 +214,15 @@ KernelGsp *pKernelGsp ) { + ConfidentialCompute *pCC = GPU_GET_CONF_COMPUTE(pGpu); + if (pCC != NULL && pCC->getProperty(pCC, PDB_PROP_CONFCOMPUTE_CC_FEATURE_ENABLED)) + { + // + // Due to BAR0 decoupler, we may not be able to read WPR2 MMU regs. + // Assume WPR2 is down. + // + return NV_FALSE; + } return kgspIsWpr2Up_TU102(pGpu, pKernelGsp); } @@ -219,7 +235,13 @@ ) { KernelFsp *pKernelFsp = GPU_GET_KERNEL_FSP(pGpu); - return kfspWaitForSecureBoot_HAL(pGpu, pKernelFsp); + + if (pKernelFsp != NULL) + { + return kfspWaitForSecureBoot_HAL(pGpu, pKernelFsp); + } + + return NV_OK; } /*! @@ -237,7 +259,7 @@ * ---------------------------- <- vbiosReservedOffset (64K? aligned) * | (potential align. gap) | * ---------------------------- <- gspFwWprEnd (128K aligned) - * | FRTS data | (frtsSize is 0 on GA100) + * | FRTS data | * | ------------------------ | <- frtsOffset * | BOOT BIN (e.g. GSP-FMC) | * ---------------------------- <- bootBinOffset @@ -250,7 +272,6 @@ * ---------------------------- <- gspFwWprStart (128K aligned) * | GSP FW (non-WPR) HEAP | * ---------------------------- <- nonWprHeapOffset, gspFwRsvdStart - * (GSP_CARVEOUT_SIZE bytes from end of FB) * * @param pGpu GPU object pointer * @param pKernelGsp KernelGsp object pointer @@ -276,8 +297,6 @@ NV_ASSERT_OR_RETURN(pKernelGsp->gspRmBootUcodeSize != 0, NV_ERR_INVALID_STATE); NV_ASSERT_OR_RETURN(pRiscvDesc != NULL, NV_ERR_INVALID_STATE); - portMemSet(pWprMeta, 0, sizeof *pWprMeta); - // // We send this to FSP as the size to reserve above FRTS. // The actual offset gets filled in by ACR ucode when it sets up WPR2. @@ -310,9 +329,30 @@ // // The WPR heap size (gspFwHeapSize) is variable to also get any padding needed - // in the carveout to align the WPR start. We specify a minimum size here. + // in the carveout to align the WPR start. This is a minimum size request to + // the GSP-FMC. // - pWprMeta->gspFwHeapSize = kgspGetWprHeapSize(pGpu, pKernelGsp); + // We won't know the exact size of everything that comes after the heap until + // after the GSP-FMC lays it all out during boot. At any rate, this value isn't + // needed on Hopper+, since the GSP-FMC can scrub/unlock anything we would need + // before GSP-RM boots, so we pass 0 to allow the heap to extend outside the + // pre-scrubbed area at the end of FB, if needed. + // + pWprMeta->gspFwHeapSize = kgspGetFwHeapSize(pGpu, pKernelGsp, 0); + + // Number of VF partitions allocating sub-heaps from the WPR heap + pWprMeta->gspFwHeapVfPartitionCount = + pGpu->bVgpuGspPluginOffloadEnabled ? MAX_PARTITIONS_WITH_GFID : 0; + + // CrashCat queue (if allocated in sysmem) + KernelCrashCatEngine *pKernelCrashCatEng = staticCast(pKernelGsp, KernelCrashCatEngine); + MEMORY_DESCRIPTOR *pCrashCatQueueMemDesc = kcrashcatEngineGetQueueMemDesc(pKernelCrashCatEng); + if (pCrashCatQueueMemDesc != NULL) + { + NV_ASSERT_CHECKED(memdescGetAddressSpace(pCrashCatQueueMemDesc) == ADDR_SYSMEM); + pWprMeta->sysmemAddrOfCrashReportQueue = memdescGetPhysAddr(pCrashCatQueueMemDesc, AT_GPU, 0); + pWprMeta->sizeOfCrashReportQueue = (NvU32)memdescGetSize(pCrashCatQueueMemDesc); + } // Fill in the meta-metadata pWprMeta->revision = GSP_FW_WPR_META_REVISION; @@ -354,6 +394,12 @@ GSP_FMC_BOOT_PARAMS *pGspFmcBootParams = pKernelGsp->pGspFmcArgumentsCached; + ConfidentialCompute *pCC = GPU_GET_CONF_COMPUTE(pGpu); + if (pCC != NULL) + { + pGspFmcBootParams->initParams.regkeys = pCC->gspProxyRegkeys; + } + pGspFmcBootParams->bootGspRmParams.gspRmDescOffset = memdescGetPhysAddr(pKernelGsp->pWprMetaDescriptor, AT_GPU, 0); pGspFmcBootParams->bootGspRmParams.gspRmDescSize = sizeof(*pKernelGsp->pWprMeta); pGspFmcBootParams->bootGspRmParams.target = _kgspMemdescToDmaTarget(pKernelGsp->pWprMetaDescriptor); @@ -366,55 +412,29 @@ } /*! - * Determine if lockdown is released. + * Determine if PRIV lockdown is released or the FMC has encountered an error. */ static NvBool -_kgspIsLockdownReleased +_kgspLockdownReleasedOrFmcError ( OBJGPU *pGpu, void *pVoid ) { KernelGsp *pKernelGsp = reinterpretCast(pVoid, KernelGsp *); - NvU32 reg; - - reg = kflcnRegRead_HAL(pGpu, staticCast(pKernelGsp, KernelFalcon), NV_PFALCON_FALCON_HWCFG2); - - return FLD_TEST_DRF(_PFALCON, _FALCON_HWCFG2, _RISCV_BR_PRIV_LOCKDOWN, - _UNLOCK, reg); -} - -/*! - * Determine if PRIV target mask is unlocked for GSP and BAR0 Decoupler allows GSP access. - * - * This is temporary WAR for the PRIV target mask bug 3640831 until we have notification - * protocol in place (there is no HW mechanism for CPU to check if GSP is open other than - * reading 0xBADF41YY code). - * - * Until the programmed BAR0 decoupler settings are cleared, GSP access is blocked from - * the CPU so all reads will return 0. - */ -static NvBool -_kgspIsTargetMaskReleased -( - OBJGPU *pGpu, - void *pVoid -) -{ - KernelGsp *pKernelGsp = reinterpretCast(pVoid, KernelGsp *); - KernelFalcon *pKernelFalcon = staticCast(pKernelGsp, KernelFalcon); - const NvU32 privErrTargetLocked = 0xBADF4100U; - const NvU32 privErrTargetLockedMask = 0xFFFFFF00U; // Ignore LSB - it has extra error information - NvU32 reg; + KernelFalcon *pKernelFalcon = staticCast(pKernelGsp, KernelFalcon); + NvU32 hwcfg2, mailbox0; // - // This register is read with the raw OS read to avoid the 0xbadf sanity checking - // done by the usual register read utilities. + // If lockdown has not been released, check NV_PGSP_FALCON_MAILBOX0, where the GSP-FMC + // (namely ACR) logs error codes during boot. GSP-FMC reported errors are always fatal, + // so there's no reason to continue polling for lockdown release. // - reg = osDevReadReg032(pGpu, gpuGetDeviceMapping(pGpu, DEVICE_INDEX_GPU, 0), - pKernelFalcon->registerBase + NV_PFALCON_FALCON_HWCFG2); + mailbox0 = kflcnRegRead_HAL(pGpu, pKernelFalcon, NV_PFALCON_FALCON_MAILBOX0); + hwcfg2 = kflcnRegRead_HAL(pGpu, pKernelFalcon, NV_PFALCON_FALCON_HWCFG2); - return ((reg != 0) && ((reg & privErrTargetLockedMask) != privErrTargetLocked)); + return (FLD_TEST_DRF(_PFALCON, _FALCON_HWCFG2, _RISCV_BR_PRIV_LOCKDOWN, _UNLOCK, hwcfg2) || + (mailbox0 != 0)); } @@ -436,6 +456,10 @@ kflcnRegWrite_HAL(pGpu, pKernelFalcon, NV_PFALCON_FALCON_MAILBOX0, NvU64_LO32(physAddr)); kflcnRegWrite_HAL(pGpu, pKernelFalcon, NV_PFALCON_FALCON_MAILBOX1, NvU64_HI32(physAddr)); + // CC needs additional "regkeys" stuffed in a separate mailbox for the init partition + ConfidentialCompute *pConfCompute = GPU_GET_CONF_COMPUTE(pGpu); + GPU_REG_WR32(pGpu, NV_PGSP_MAILBOX(0), pConfCompute->gspProxyRegkeys); + // Bootstrap the GSP-FMC by pointing the GSP's BootROM at it RM_RISCV_UCODE_DESC *pRiscvDesc = pKernelGsp->pGspRmBootUcodeDesc; RmPhysAddr fmcPhysAddr = memdescGetPhysAddr(pKernelGsp->pGspRmBootUcodeMemdesc, AT_GPU, 0); @@ -503,8 +527,8 @@ { KernelFalcon *pKernelFalcon = staticCast(pKernelGsp, KernelFalcon); KernelFsp *pKernelFsp = GPU_GET_KERNEL_FSP(pGpu); - KernelMemorySystem *pKernelMemorySystem = GPU_GET_KERNEL_MEMORY_SYSTEM(pGpu); NV_STATUS status = NV_OK; + NvU32 mailbox0; // Only for GSP client builds if (!IS_GSP_CLIENT(pGpu)) @@ -513,16 +537,8 @@ return NV_ERR_NOT_SUPPORTED; } - // Clear ECC errors before attempting to load GSP - status = kmemsysClearEccCounts_HAL(pGpu, pKernelMemorySystem); - if (status != NV_OK) - { - NV_PRINTF(LEVEL_ERROR, "Issue clearing ECC counts! Status:0x%x\n", status); - } - // Setup the descriptors that GSP-FMC needs to boot GSP-RM - NV_CHECK_OK_OR_GOTO(status, LEVEL_ERROR, - kgspSetupGspFmcArgs_HAL(pGpu, pKernelGsp, pGspFw), exit); + NV_CHECK_OK_OR_RETURN(LEVEL_ERROR, kgspSetupGspFmcArgs_HAL(pGpu, pKernelGsp, pGspFw)); kgspSetupLibosInitArgs(pGpu, pKernelGsp); @@ -537,22 +553,21 @@ if (status != NV_OK) { NV_ASSERT_OK_FAILED("NV_RM_RPC_GSP_SET_SYSTEM_INFO", status); - goto exit; + return status; } NV_RM_RPC_SET_REGISTRY(pGpu, status); if (status != NV_OK) { NV_ASSERT_OK_FAILED("NV_RM_RPC_SET_REGISTRY", status); - goto exit; + return status; } if (pKernelFsp != NULL && !pKernelFsp->getProperty(pKernelFsp, PDB_PROP_KFSP_DISABLE_GSPFMC)) { - NV_PRINTF(LEVEL_ERROR, "Starting to boot GSP via FSP.\n"); + NV_PRINTF(LEVEL_NOTICE, "Starting to boot GSP via FSP.\n"); pKernelFsp->setProperty(pKernelFsp, PDB_PROP_KFSP_GSP_MODE_GSPRM, NV_TRUE); - NV_CHECK_OK_OR_GOTO(status, LEVEL_ERROR, - kfspSendBootCommands_HAL(pGpu, pKernelFsp), exit); + NV_CHECK_OK_OR_RETURN(LEVEL_ERROR, kfspSendBootCommands_HAL(pGpu, pKernelFsp)); } else { @@ -560,24 +575,27 @@ } // Wait for target mask to be released. - status = gpuTimeoutCondWait(pGpu, _kgspIsTargetMaskReleased, pKernelGsp, NULL); - if (status != NV_OK) + if (pKernelFsp != NULL) { - NV_PRINTF(LEVEL_ERROR, "Timeout waiting for GSP target mask release. " - "This error may be caused by several reasons: Bootrom may have failed, " - "GSP init code may have failed or ACR failed to release target mask. " - "RM does not have access to information on which of those conditions happened.\n"); - - if (pKernelFsp != NULL && pKernelFsp->getProperty(pKernelFsp, PDB_PROP_KFSP_GSP_MODE_GSPRM)) + status = kfspWaitForGspTargetMaskReleased_HAL(pGpu, pKernelFsp); + if (status != NV_OK) { - kfspDumpDebugState_HAL(pGpu, pKernelFsp); - } + NV_PRINTF(LEVEL_ERROR, "Timeout waiting for GSP target mask release. " + "This error may be caused by several reasons: Bootrom may have failed, " + "GSP init code may have failed or ACR failed to release target mask. " + "RM does not have access to information on which of those conditions happened.\n"); + + if (pKernelFsp->getProperty(pKernelFsp, PDB_PROP_KFSP_GSP_MODE_GSPRM)) + { + kfspDumpDebugState_HAL(pGpu, pKernelFsp); + } - goto exit; + return status; + } } - // Wait for lockdown to be released. - status = gpuTimeoutCondWait(pGpu, _kgspIsLockdownReleased, pKernelGsp, NULL); + // Wait for lockdown to be released or the FMC to report an error + status = gpuTimeoutCondWait(pGpu, _kgspLockdownReleasedOrFmcError, pKernelGsp, NULL); if (status != NV_OK) { NV_PRINTF(LEVEL_ERROR, "Timeout waiting for lockdown release. It's also " @@ -593,7 +611,13 @@ kflcnRegRead_HAL(pGpu, pKernelFalcon, NV_PFALCON_FALCON_MAILBOX0)); NV_PRINTF(LEVEL_ERROR, "NV_PGSP_FALCON_MAILBOX1 = 0x%x\n", kflcnRegRead_HAL(pGpu, pKernelFalcon, NV_PFALCON_FALCON_MAILBOX1)); - goto exit; + return status; + } + else if ((mailbox0 = kflcnRegRead_HAL(pGpu, pKernelFalcon, NV_PFALCON_FALCON_MAILBOX0)) != 0) + { + NV_PRINTF(LEVEL_ERROR, "GSP-FMC reported an error while attempting to boot GSP: 0x%x\n", + mailbox0); + return NV_ERR_NOT_READY; } // Start polling for libos logs now that lockdown is released @@ -611,30 +635,19 @@ else { NV_ASSERT_FAILED("Failed to boot GSP"); - status = NV_ERR_NOT_READY; - goto exit; + return NV_ERR_NOT_READY; } NV_PRINTF(LEVEL_INFO, "Waiting for GSP fw RM to be ready...\n"); // Link the status queue. - NV_ASSERT_OK_OR_GOTO(status, GspStatusQueueInit(pGpu, &pKernelGsp->pRpc->pMessageQueueInfo), - exit); + NV_ASSERT_OK_OR_RETURN(GspStatusQueueInit(pGpu, &pKernelGsp->pRpc->pMessageQueueInfo)); - NV_ASSERT_OK_OR_GOTO(status, kgspWaitForRmInitDone(pGpu, pKernelGsp), - exit); + NV_ASSERT_OK_OR_RETURN(kgspWaitForRmInitDone(pGpu, pKernelGsp)); NV_PRINTF(LEVEL_INFO, "GSP FW RM ready.\n"); -exit: - // If GSP fails to boot, check if there's any DED error. - if (status != NV_OK) - { - kmemsysCheckEccCounts_HAL(pGpu, pKernelMemorySystem); - } - NV_ASSERT(status == NV_OK); - - return status; + return NV_OK; } void @@ -646,5 +659,24 @@ BINDATA_STORAGE **ppBinStorageDesc ) { + ConfidentialCompute *pCC = GPU_GET_CONF_COMPUTE(pGpu); + if (pCC != NULL && pCC->getProperty(pCC, PDB_PROP_CONFCOMPUTE_CC_FEATURE_ENABLED)) + { + const BINDATA_ARCHIVE *pBinArchiveConcatenatedFMCDesc = kgspGetBinArchiveConcatenatedFMCDesc_HAL(pKernelGsp); + const BINDATA_ARCHIVE *pBinArchiveConcatenatedFMC = kgspGetBinArchiveConcatenatedFMC_HAL(pKernelGsp); + + if (kgspIsDebugModeEnabled(pGpu, pKernelGsp)) + { + *ppBinStorageImage = (BINDATA_STORAGE *)bindataArchiveGetStorage(pBinArchiveConcatenatedFMC, "ucode_image_dbg"); + *ppBinStorageDesc = (BINDATA_STORAGE *)bindataArchiveGetStorage(pBinArchiveConcatenatedFMCDesc, "ucode_desc_dbg"); + } + else + { + *ppBinStorageImage = (BINDATA_STORAGE *)bindataArchiveGetStorage(pBinArchiveConcatenatedFMC, "ucode_image_prod"); + *ppBinStorageDesc = (BINDATA_STORAGE *)bindataArchiveGetStorage(pBinArchiveConcatenatedFMCDesc, "ucode_desc_prod"); + } + + return; + } kgspGetGspRmBootUcodeStorage_GA102(pGpu, pKernelGsp, ppBinStorageImage, ppBinStorageDesc); } diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/kernel/gpu/gsp/arch/turing/kernel_gsp_booter_tu102.c nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/kernel/gpu/gsp/arch/turing/kernel_gsp_booter_tu102.c --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/kernel/gpu/gsp/arch/turing/kernel_gsp_booter_tu102.c 2023-10-25 20:21:05.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/kernel/gpu/gsp/arch/turing/kernel_gsp_booter_tu102.c 2024-03-05 22:13:30.000000000 +0000 @@ -87,22 +87,28 @@ ( OBJGPU *pGpu, KernelGsp *pKernelGsp, - const NvU64 gspFwWprMetaOffset + const NvU64 sysmemAddrOfData ) { NV_STATUS status; - NvU32 mailbox0, mailbox1; + NvU32 mailbox0 = 0, mailbox1 = 0; KernelSec2 *pKernelSec2 = GPU_GET_KERNEL_SEC2(pGpu); NV_ASSERT_OR_RETURN(pKernelGsp->pBooterLoadUcode != NULL, NV_ERR_INVALID_STATE); - // Provide gspFwWprMetaOffset in falcon SEC mailboxes 0 (low 32 bits) and 1 (high 32 bits) - mailbox0 = NvU64_LO32(gspFwWprMetaOffset); - mailbox1 = NvU64_HI32(gspFwWprMetaOffset); + if (sysmemAddrOfData != 0) + { + // + // sysmemAddrOfData either represents the FW WPR MetaData or the FW SR Data as a physical address in SYSTEM + // Provide that data in falcon SEC mailboxes 0 (low 32 bits) and 1 (high 32 bits) + // + mailbox0 = NvU64_LO32(sysmemAddrOfData); + mailbox1 = NvU64_HI32(sysmemAddrOfData); + } - NV_PRINTF(LEVEL_INFO, "executing Booter Load, gspFwWprMetaOffset 0x%llx\n", - gspFwWprMetaOffset); + NV_PRINTF(LEVEL_INFO, "executing Booter Load, sysmemAddrOfData 0x%llx\n", + sysmemAddrOfData); kflcnReset_HAL(pGpu, staticCast(pKernelSec2, KernelFalcon)); @@ -123,11 +129,18 @@ kgspExecuteBooterUnloadIfNeeded_TU102 ( OBJGPU *pGpu, - KernelGsp *pKernelGsp + KernelGsp *pKernelGsp, + const NvU64 sysmemAddrOfSuspendResumeData ) { NV_STATUS status; KernelSec2 *pKernelSec2 = GPU_GET_KERNEL_SEC2(pGpu); + NvU32 mailbox0 = 0xFF, mailbox1 = 0xFF; + + if (IS_GPU_GC6_STATE_ENTERING(pGpu)) + { + mailbox0 = mailbox1 = 0xdeaddead; + } // skip actually executing Booter Unload if WPR2 is not up if (!kgspIsWpr2Up_HAL(pGpu, pKernelGsp)) @@ -140,20 +153,40 @@ NV_ASSERT_OR_RETURN(pKernelGsp->pBooterUnloadUcode != NULL, NV_ERR_INVALID_STATE); kflcnReset_HAL(pGpu, staticCast(pKernelSec2, KernelFalcon)); + + // SR code + if (sysmemAddrOfSuspendResumeData != 0) + { + mailbox0 = NvU64_LO32(sysmemAddrOfSuspendResumeData); + mailbox1 = NvU64_HI32(sysmemAddrOfSuspendResumeData); + } status = s_executeBooterUcode_TU102(pGpu, pKernelGsp, pKernelGsp->pBooterUnloadUcode, staticCast(pKernelSec2, KernelFalcon), - 0xFF, 0xFF); + mailbox0, mailbox1); if (status != NV_OK) { NV_PRINTF(LEVEL_ERROR, "failed to execute Booter Unload: 0x%x\n", status); return status; } - if (kgspIsWpr2Up_HAL(pGpu, pKernelGsp)) + if (IS_GPU_GC6_STATE_ENTERING(pGpu)) + { + // For GC6 path, WPR2 should still be up (not torn down) + if (!kgspIsWpr2Up_HAL(pGpu, pKernelGsp)) + { + NV_PRINTF(LEVEL_ERROR, "failed to execute Booter Unload: WPR2 is cleared despite GC6\n"); + return NV_ERR_GENERIC; + } + } + else { - NV_PRINTF(LEVEL_ERROR, "failed to execute Booter Unload: WPR2 is still up\n"); - return NV_ERR_GENERIC; + // For all other unloads (non-GC6), WPR2 should be torn down + if (kgspIsWpr2Up_HAL(pGpu, pKernelGsp)) + { + NV_PRINTF(LEVEL_ERROR, "failed to execute Booter Unload: WPR2 is still up\n"); + return NV_ERR_GENERIC; + } } return status; diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/kernel/gpu/gsp/arch/turing/kernel_gsp_frts_tu102.c nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/kernel/gpu/gsp/arch/turing/kernel_gsp_frts_tu102.c --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/kernel/gpu/gsp/arch/turing/kernel_gsp_frts_tu102.c 2023-10-25 20:21:05.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/kernel/gpu/gsp/arch/turing/kernel_gsp_frts_tu102.c 2024-03-05 22:13:30.000000000 +0000 @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 2021-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2021-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -398,7 +398,7 @@ { NV_PRINTF(LEVEL_ERROR, "failed to prepare interface data for FWSEC cmd 0x%x: 0x%x\n", cmd, status); - return status; + goto out; } } else if (pFwsecUcode->bootType == KGSP_FLCN_UCODE_BOOT_WITH_LOADER) @@ -426,7 +426,7 @@ { NV_PRINTF(LEVEL_ERROR, "failed to prepare interface data for FWSEC cmd 0x%x: 0x%x\n", cmd, status); - return status; + goto out; } } else @@ -440,7 +440,7 @@ if (status != NV_OK) { NV_PRINTF(LEVEL_ERROR, "failed to execute FWSEC cmd 0x%x: status 0x%x\n", cmd, status); - return status; + goto out; } if (cmd == FALCON_APPLICATION_INTERFACE_DMEM_MAPPER_V3_CMD_FRTS) @@ -456,7 +456,8 @@ if (frtsErrCode != NV_VBIOS_FWSECLIC_FRTS_ERR_CODE_NONE) { NV_PRINTF(LEVEL_ERROR, "failed to execute FWSEC for FRTS: FRTS error code 0x%x\n", frtsErrCode); - return NV_ERR_GENERIC; + status = NV_ERR_GENERIC; + goto out; } data = GPU_REG_RD32(pGpu, NV_PFB_PRI_MMU_WPR2_ADDR_HI); @@ -464,7 +465,8 @@ if (wpr2HiVal == 0) { NV_PRINTF(LEVEL_ERROR, "failed to execute FWSEC for FRTS: no initialized WPR2 found\n"); - return NV_ERR_GENERIC; + status = NV_ERR_GENERIC; + goto out; } data = GPU_REG_RD32(pGpu, NV_PFB_PRI_MMU_WPR2_ADDR_LO); @@ -475,7 +477,8 @@ NV_PRINTF(LEVEL_ERROR, "failed to execute FWSEC for FRTS: WPR2 initialized at an unexpected location: 0x%08x (expected 0x%08x)\n", wpr2LoVal, expectedLoVal); - return NV_ERR_GENERIC; + status = NV_ERR_GENERIC; + goto out; } } else // i.e. FALCON_APPLICATION_INTERFACE_DMEM_MAPPER_V3_CMD_SB @@ -487,14 +490,16 @@ _READ_PROTECTION_LEVEL0, _ENABLE)) { NV_PRINTF(LEVEL_ERROR, "failed to execute FWSEC for SB: GFW PLM not lowered\n"); - return NV_ERR_GENERIC; + status = NV_ERR_GENERIC; + goto out; } if (!GPU_FLD_TEST_DRF_DEF(pGpu, _PGC6, _AON_SECURE_SCRATCH_GROUP_05_0_GFW_BOOT, _PROGRESS, _COMPLETED)) { NV_PRINTF(LEVEL_ERROR, "failed to execute FWSEC for SB: GFW progress not completed\n"); - return NV_ERR_GENERIC; + status = NV_ERR_GENERIC; + goto out; } data = GPU_REG_RD32(pGpu, NV_PBUS_VBIOS_SCRATCH(NV_VBIOS_FWSECLIC_SCRATCH_INDEX_15)); @@ -502,10 +507,17 @@ if (sbErrCode != NV_VBIOS_FWSECLIC_SB_ERR_CODE_NONE) { NV_PRINTF(LEVEL_ERROR, "failed to execute FWSEC for SB: SB error code 0x%x\n", sbErrCode); - return NV_ERR_GENERIC; + status = NV_ERR_GENERIC; + goto out; } } +out: + if (status != NV_OK) + { + NV_PRINTF(LEVEL_ERROR, "(note: VBIOS version %s)\n", pKernelGsp->vbiosVersionStr); + } + return status; } diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/kernel/gpu/gsp/arch/turing/kernel_gsp_tu102.c nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/kernel/gpu/gsp/arch/turing/kernel_gsp_tu102.c --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/kernel/gpu/gsp/arch/turing/kernel_gsp_tu102.c 2023-10-25 20:21:06.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/kernel/gpu/gsp/arch/turing/kernel_gsp_tu102.c 2024-03-05 22:13:30.000000000 +0000 @@ -37,6 +37,7 @@ #include "os/os.h" #include "nverror.h" #include "gsp/gsp_error.h" +#include "crashcat/crashcat_report.h" #include "published/turing/tu102/dev_gsp.h" #include "published/turing/tu102/dev_gsp_addendum.h" @@ -57,7 +58,6 @@ #undef RPC_STRUCTURES #undef RPC_GENERIC_UNION - void kgspConfigureFalcon_TU102 ( @@ -77,6 +77,11 @@ falconConfig.bIsPmcDeviceEngine = NV_FALSE; falconConfig.physEngDesc = ENG_GSP; + // Enable CrashCat monitoring + falconConfig.crashcatEngConfig.bEnable = NV_TRUE; + falconConfig.crashcatEngConfig.pName = MAKE_NV_PRINTF_STR("GSP"); + falconConfig.crashcatEngConfig.errorId = GSP_ERROR; + kflcnConfigureEngine(pGpu, staticCast(pKernelGsp, KernelFalcon), &falconConfig); } @@ -109,79 +114,88 @@ NvP64 pVa = NvP64_NULL; NvP64 pPriv = NvP64_NULL; NV_STATUS nvStatus = NV_OK; + NvU64 flags = MEMDESC_FLAGS_NONE; + + flags |= MEMDESC_FLAGS_ALLOC_IN_UNPROTECTED_MEMORY; // Allocate WPR meta data NV_ASSERT_OK_OR_GOTO(nvStatus, - memdescCreate(&pKernelGsp->pWprMetaDescriptor, - pGpu, 0x1000, 0x1000, - NV_TRUE, ADDR_SYSMEM, NV_MEMORY_CACHED, - MEMDESC_FLAGS_NONE), - _kgspAllocBootArgs_exit_cleanup); + memdescCreate(&pKernelGsp->pWprMetaDescriptor, + pGpu, 0x1000, 0x1000, + NV_TRUE, ADDR_SYSMEM, NV_MEMORY_CACHED, + flags), + _kgspAllocBootArgs_exit_cleanup); NV_ASSERT_OK_OR_GOTO(nvStatus, - memdescAlloc(pKernelGsp->pWprMetaDescriptor), - _kgspAllocBootArgs_exit_cleanup); + memdescAlloc(pKernelGsp->pWprMetaDescriptor), + _kgspAllocBootArgs_exit_cleanup); NV_ASSERT_OK_OR_GOTO(nvStatus, - memdescMap(pKernelGsp->pWprMetaDescriptor, 0, - memdescGetSize(pKernelGsp->pWprMetaDescriptor), - NV_TRUE, NV_PROTECT_READ_WRITE, - &pVa, &pPriv), - _kgspAllocBootArgs_exit_cleanup); + memdescMap(pKernelGsp->pWprMetaDescriptor, 0, + memdescGetSize(pKernelGsp->pWprMetaDescriptor), + NV_TRUE, NV_PROTECT_READ_WRITE, + &pVa, &pPriv), + _kgspAllocBootArgs_exit_cleanup); pKernelGsp->pWprMeta = (GspFwWprMeta *)NvP64_VALUE(pVa); pKernelGsp->pWprMetaMappingPriv = pPriv; + portMemSet(pKernelGsp->pWprMeta, 0, sizeof(*pKernelGsp->pWprMeta)); + // // Setup libos arguments memory // NV_ASSERT_OK_OR_GOTO(nvStatus, - memdescCreate(&pKernelGsp->pLibosInitArgumentsDescriptor, - pGpu, - LIBOS_INIT_ARGUMENTS_SIZE, - LIBOS_INIT_ARGUMENTS_SIZE, - NV_TRUE, ADDR_SYSMEM, NV_MEMORY_UNCACHED, - MEMDESC_FLAGS_NONE), - _kgspAllocBootArgs_exit_cleanup); - - NV_ASSERT_OK_OR_GOTO(nvStatus, - memdescAlloc(pKernelGsp->pLibosInitArgumentsDescriptor), - _kgspAllocBootArgs_exit_cleanup); - - NV_ASSERT_OK_OR_GOTO(nvStatus, - memdescMap(pKernelGsp->pLibosInitArgumentsDescriptor, 0, - memdescGetSize(pKernelGsp->pLibosInitArgumentsDescriptor), - NV_TRUE, NV_PROTECT_READ_WRITE, + memdescCreate(&pKernelGsp->pLibosInitArgumentsDescriptor, + pGpu, + LIBOS_INIT_ARGUMENTS_SIZE, + LIBOS_INIT_ARGUMENTS_SIZE, + NV_TRUE, ADDR_SYSMEM, NV_MEMORY_UNCACHED, + flags), + _kgspAllocBootArgs_exit_cleanup); + + NV_ASSERT_OK_OR_GOTO(nvStatus, + memdescAlloc(pKernelGsp->pLibosInitArgumentsDescriptor), + _kgspAllocBootArgs_exit_cleanup); + + NV_ASSERT_OK_OR_GOTO(nvStatus, + memdescMap(pKernelGsp->pLibosInitArgumentsDescriptor, 0, + memdescGetSize(pKernelGsp->pLibosInitArgumentsDescriptor), + NV_TRUE, NV_PROTECT_READ_WRITE, &pVa, &pPriv), - _kgspAllocBootArgs_exit_cleanup); + _kgspAllocBootArgs_exit_cleanup); pKernelGsp->pLibosInitArgumentsCached = (LibosMemoryRegionInitArgument *)NvP64_VALUE(pVa); pKernelGsp->pLibosInitArgumentsMappingPriv = pPriv; + portMemSet(pKernelGsp->pLibosInitArgumentsCached, 0, LIBOS_INIT_ARGUMENTS_SIZE); + // Setup bootloader arguments memory. NV_ASSERT(sizeof(GSP_ARGUMENTS_CACHED) <= 0x1000); NV_ASSERT_OK_OR_GOTO(nvStatus, - memdescCreate(&pKernelGsp->pGspArgumentsDescriptor, - pGpu, 0x1000, 0x1000, - NV_TRUE, ADDR_SYSMEM, NV_MEMORY_CACHED, - MEMDESC_FLAGS_NONE), - _kgspAllocBootArgs_exit_cleanup); + memdescCreate(&pKernelGsp->pGspArgumentsDescriptor, + pGpu, 0x1000, 0x1000, + NV_TRUE, ADDR_SYSMEM, NV_MEMORY_CACHED, + flags), + _kgspAllocBootArgs_exit_cleanup); NV_ASSERT_OK_OR_GOTO(nvStatus, - memdescAlloc(pKernelGsp->pGspArgumentsDescriptor), - _kgspAllocBootArgs_exit_cleanup); + memdescAlloc(pKernelGsp->pGspArgumentsDescriptor), + _kgspAllocBootArgs_exit_cleanup); NV_ASSERT_OK_OR_GOTO(nvStatus, - memdescMap(pKernelGsp->pGspArgumentsDescriptor, 0, - memdescGetSize(pKernelGsp->pGspArgumentsDescriptor), - NV_TRUE, NV_PROTECT_READ_WRITE, - &pVa, &pPriv), - _kgspAllocBootArgs_exit_cleanup); + memdescMap(pKernelGsp->pGspArgumentsDescriptor, 0, + memdescGetSize(pKernelGsp->pGspArgumentsDescriptor), + NV_TRUE, NV_PROTECT_READ_WRITE, + &pVa, &pPriv), + _kgspAllocBootArgs_exit_cleanup); pKernelGsp->pGspArgumentsCached = (GSP_ARGUMENTS_CACHED *)NvP64_VALUE(pVa); pKernelGsp->pGspArgumentsMappingPriv = pPriv; + portMemSet(pKernelGsp->pGspArgumentsCached, 0, sizeof(*pKernelGsp->pGspArgumentsCached)); + return nvStatus; _kgspAllocBootArgs_exit_cleanup: @@ -362,8 +376,11 @@ kflcnReset_HAL(pGpu, pKernelFalcon); NV_ASSERT_OK_OR_GOTO(status, - kgspExecuteFwsecFrts_HAL(pGpu, pKernelGsp, pKernelGsp->pFwsecUcode, - pKernelGsp->pWprMeta->frtsOffset), exit); + kgspExecuteFwsecFrts_HAL(pGpu, + pKernelGsp, + pKernelGsp->pFwsecUcode, + pKernelGsp->pWprMeta->frtsOffset), + exit); } } @@ -427,11 +444,13 @@ NV_PRINTF(LEVEL_INFO, "Waiting for GSP fw RM to be ready...\n"); // Link the status queue. - NV_ASSERT_OK_OR_GOTO(status, GspStatusQueueInit(pGpu, &pKernelGsp->pRpc->pMessageQueueInfo), - exit); - - NV_ASSERT_OK_OR_GOTO(status, kgspWaitForRmInitDone(pGpu, pKernelGsp), - exit); + NV_ASSERT_OK_OR_GOTO(status, + GspStatusQueueInit(pGpu, &pKernelGsp->pRpc->pMessageQueueInfo), + exit); + + NV_ASSERT_OK_OR_GOTO(status, + kgspWaitForRmInitDone(pGpu, pKernelGsp), + exit); NV_PRINTF(LEVEL_INFO, "GSP FW RM ready.\n"); @@ -479,8 +498,9 @@ * | GSP FW (non-WPR) HEAP | * ---------------------------- <- nonWprHeapOffset, gspFwRsvdStart * - * gspFwHeapOffset** contains the RM/Libos Heap. First 16 Mb are for Libos heap - * rest is for GSP-RM + * gspFwHeapOffset** contains the entire WPR heap region, which can be subdivided + * for various GSP FW components. + * * @param pGpu GPU object pointer * @param pKernelGsp KernelGsp object pointer * @param pGspFw Pointer to GSP-RM fw image. @@ -510,8 +530,6 @@ NV_ASSERT_OR_RETURN(pKernelGsp->gspRmBootUcodeSize != 0, NV_ERR_INVALID_STATE); NV_ASSERT_OR_RETURN(pRiscvDesc != NULL, NV_ERR_INVALID_STATE); - portMemSet(pWprMeta, 0, sizeof *pWprMeta); - NV_ASSERT_OK_OR_RETURN(kmemsysGetUsableFbSize_HAL(pGpu, pKernelMemorySystem, &pWprMeta->fbSize)); // @@ -545,8 +563,11 @@ else vbiosReservedOffset = pWprMeta->vgaWorkspaceOffset; - // End of WPR region (128KB aligned) - pWprMeta->gspFwWprEnd = NV_ALIGN_DOWN64(vbiosReservedOffset, 0x20000); + // Set the size of the GSP FW ahead of kgspGetWprEndMargin() + pWprMeta->sizeOfRadix3Elf = pGspFw->imageSize; + + // End of WPR region (128KB aligned), shifted for any WPR end margin + pWprMeta->gspFwWprEnd = NV_ALIGN_DOWN64(vbiosReservedOffset - kgspGetWprEndMargin(pGpu, pKernelGsp), 0x20000); pWprMeta->frtsSize = kgspGetFrtsSize(pGpu, pKernelGsp); pWprMeta->frtsOffset = pWprMeta->gspFwWprEnd - pWprMeta->frtsSize; @@ -555,29 +576,31 @@ pWprMeta->sizeOfBootloader = pKernelGsp->gspRmBootUcodeSize; pWprMeta->bootBinOffset = NV_ALIGN_DOWN64(pWprMeta->frtsOffset - pWprMeta->sizeOfBootloader, 0x1000); - // Compute GSP firmware image size - pWprMeta->sizeOfRadix3Elf = pGspFw->imageSize; - // // Compute the start of the ELF. Align to 64K to avoid issues with - // inherent alignment constraints (e.g. GC6 buffers which are allocated - // just below this offset). + // inherent alignment constraints. // pWprMeta->gspFwOffset = NV_ALIGN_DOWN64(pWprMeta->bootBinOffset - pWprMeta->sizeOfRadix3Elf, 0x10000); - NvU64 wprHeapSize = kgspGetWprHeapSize(pGpu, pKernelGsp); - - // Start of WPR region (1Mb aligned) - pWprMeta->gspFwWprStart = - NV_ALIGN_DOWN64(pWprMeta->gspFwOffset - wprHeapSize, 0x100000); + const NvU64 wprHeapSize = kgspGetFwHeapSize(pGpu, pKernelGsp, pWprMeta->fbSize - pWprMeta->gspFwOffset); - // GSP-RM heap in WPR, align to 1Mb - pWprMeta->gspFwHeapOffset = NV_ALIGN_UP64(pWprMeta->gspFwWprStart + sizeof *pWprMeta, 0x100000); + // GSP-RM heap in WPR, align to 1MB + pWprMeta->gspFwHeapOffset = NV_ALIGN_DOWN64(pWprMeta->gspFwOffset - wprHeapSize, 0x100000); pWprMeta->gspFwHeapSize = NV_ALIGN_DOWN64(pWprMeta->gspFwOffset - pWprMeta->gspFwHeapOffset, 0x100000); - // Non WPR heap + // Number of VF partitions allocating sub-heaps from the WPR heap + pWprMeta->gspFwHeapVfPartitionCount = pGpu->bVgpuGspPluginOffloadEnabled ? MAX_PARTITIONS_WITH_GFID : 0; + + // + // Start of WPR region (128K alignment requirement, but 1MB aligned so that + // the extra padding sits in WPR instead of in between the end of the + // non-WPR heap and the start of WPR). + // + pWprMeta->gspFwWprStart = NV_ALIGN_DOWN64(pWprMeta->gspFwHeapOffset - sizeof *pWprMeta, 0x100000); + + // Non WPR heap (1MB aligned) pWprMeta->nonWprHeapSize = kgspGetNonWprHeapSize(pGpu, pKernelGsp); - pWprMeta->nonWprHeapOffset = pWprMeta->gspFwWprStart - pWprMeta->nonWprHeapSize; + pWprMeta->nonWprHeapOffset = NV_ALIGN_DOWN64(pWprMeta->gspFwWprStart - pWprMeta->nonWprHeapSize, 0x100000); pWprMeta->gspFwRsvdStart = pWprMeta->nonWprHeapOffset; @@ -600,20 +623,21 @@ pWprMeta->sizeOfSignature = memdescGetSize(pKernelGsp->pSignatureMemdesc); } + // CrashCat queue (if allocated in sysmem) + KernelCrashCatEngine *pKernelCrashCatEng = staticCast(pKernelGsp, KernelCrashCatEngine); + MEMORY_DESCRIPTOR *pCrashCatQueueMemDesc = kcrashcatEngineGetQueueMemDesc(pKernelCrashCatEng); + if (pCrashCatQueueMemDesc != NULL) + { + NV_ASSERT_CHECKED(memdescGetAddressSpace(pCrashCatQueueMemDesc) == ADDR_SYSMEM); + pWprMeta->sysmemAddrOfCrashReportQueue = memdescGetPhysAddr(pCrashCatQueueMemDesc, AT_GPU, 0); + pWprMeta->sizeOfCrashReportQueue = (NvU32)memdescGetSize(pCrashCatQueueMemDesc); + } + pWprMeta->bootCount = 0; pWprMeta->verified = 0; pWprMeta->revision = GSP_FW_WPR_META_REVISION; pWprMeta->magic = GSP_FW_WPR_META_MAGIC; - if (pGpu->bVgpuGspPluginOffloadEnabled) - { - pKernelGsp->pWprMeta->driverModel = 1; - } - else - { - pKernelGsp->pWprMeta->driverModel = 0; - } - #if 0 NV_PRINTF(LEVEL_ERROR, "WPR meta data offset: 0x%016llx\n", pWprMeta->gspFwWprStart); NV_PRINTF(LEVEL_ERROR, " magic: 0x%016llx\n", pWprMeta->magic); @@ -749,28 +773,36 @@ return NV_OK; } -/*! - * Return NV_OK along with the Engine Reset state. - */ NvBool -kgspIsEngineInReset_TU102 +kgspHealthCheck_TU102 ( OBJGPU *pGpu, KernelGsp *pKernelGsp ) { - NvU32 val = GPU_REG_RD32(pGpu, NV_PGSP_FALCON_ENGINE); + NvBool bHealthy = NV_TRUE; - return FLD_TEST_DRF(_PGSP_FALCON, _ENGINE, _RESET, _TRUE, val); -} + // If enabled, CrashCat is the primary reporting interface for GSP issues + KernelCrashCatEngine *pKernelCrashCatEng = staticCast(pKernelGsp, KernelCrashCatEngine); + if (kcrashcatEngineConfigured(pKernelCrashCatEng)) + { + CrashCatEngine *pCrashCatEng = staticCast(pKernelCrashCatEng, CrashCatEngine); + CrashCatReport *pReport; + + while ((pReport = crashcatEngineGetNextCrashReport(pCrashCatEng)) != NULL) + { + bHealthy = NV_FALSE; + + NV_PRINTF(LEVEL_ERROR, + "****************************** GSP-CrashCat Report *******************************\n"); + crashcatReportLog(pReport); + + objDelete(pReport); + } + + goto exit_health_check; + } -void -kgspHealthCheck_TU102 -( - OBJGPU *pGpu, - KernelGsp *pKernelGsp -) -{ NvU32 mb0 = GPU_REG_RD32(pGpu, NV_PGSP_MAILBOX(0)); // @@ -782,7 +814,7 @@ NvU32 mb1 = GPU_REG_RD32(pGpu, NV_PGSP_MAILBOX(1)); NvU32 skipped = DRF_VAL(_GSP, _ERROR, _SKIPPED, mb0); - pKernelGsp->bFatalError = NV_TRUE; + bHealthy = NV_FALSE; // Clear the mailbox GPU_REG_WR32(pGpu, NV_PGSP_MAILBOX(0), 0); @@ -790,14 +822,8 @@ NV_PRINTF(LEVEL_ERROR, "********************************* GSP Failure **********************************\n"); - nvErrorLog_va((void*)pGpu, GSP_ERROR, - "GSP Error: Task %d raised error code 0x%x for reason 0x%x at 0x%x. The GPU likely needs to be reset.", - DRF_VAL(_GSP, _ERROR, _TASK, mb0), - DRF_VAL(_GSP, _ERROR, _CODE, mb0), - DRF_VAL(_GSP, _ERROR, _REASON, mb0), - mb1); - NVLOG_PRINTF(NV_PRINTF_MODULE, NVLOG_ROUTE_RM, LEVEL_ERROR, NV_PRINTF_ADD_PREFIX - ("GSP Error: Task %d raised error code 0x%x for reason 0x%x at 0x%x"), + NV_ERROR_LOG(pGpu, GSP_ERROR, + "GSP Error: Task %d raised error code 0x%x for reason 0x%x at 0x%x. The GPU likely needs to be reset.", DRF_VAL(_GSP, _ERROR, _TASK, mb0), DRF_VAL(_GSP, _ERROR, _CODE, mb0), DRF_VAL(_GSP, _ERROR, _REASON, mb0), @@ -808,13 +834,22 @@ { NV_PRINTF(LEVEL_ERROR, "%d more errors skipped\n", skipped); } + } - NV_PRINTF(LEVEL_ERROR, - "********************************************************************************\n"); +exit_health_check: + if (!bHealthy) + { + pKernelGsp->bFatalError = NV_TRUE; - KernelMemorySystem *pKernelMemorySystem = GPU_GET_KERNEL_MEMORY_SYSTEM(pGpu); - kmemsysCheckEccCounts_HAL(pGpu, pKernelMemorySystem); + if (pKernelGsp->pRpc) + kgspLogRpcDebugInfo(pGpu, pKernelGsp->pRpc, GSP_ERROR, pKernelGsp->bPollingForRpcResponse); + + gpuCheckEccCounts_HAL(pGpu); + + NV_PRINTF(LEVEL_ERROR, + "**********************************************************************************\n"); } + return bHealthy; } /*! @@ -830,7 +865,6 @@ KernelGsp *pKernelGsp ) { - NvU32 clearBits = 0; NvU32 intrStatus; KernelFalcon *pKernelFalcon = staticCast(pKernelGsp, KernelFalcon); @@ -840,6 +874,7 @@ // Exit immediately if there is nothing to do if (intrStatus == 0) { + NV_ASSERT_FAILED("KGSP service called when no KGSP interrupt pending\n"); return 0; } @@ -851,16 +886,17 @@ if (intrStatus & DRF_DEF(_PFALCON, _FALCON_IRQSTAT, _HALT, _TRUE)) { - clearBits |= DRF_DEF(_PFALCON, _FALCON_IRQSCLR, _HALT, _SET); - // - // Currently, GSP-RISCV triggers _HALT interrupt to RM when it finds - // itself running into a bad state. Triggering _HALT interrupt to RM - // provides RM a chance to handle it so we have better debugability - // into GSP-RISCV issues. + // The _HALT is triggered by ucode as part of the CrashCat protocol to + // signal the host that some handling is required. Clear the interrupt + // before handling, so that once the GSP code continues, we won't miss + // a second _HALT interrupt for the next step. // + kflcnRegWrite_HAL(pGpu, pKernelFalcon, NV_PFALCON_FALCON_IRQSCLR, + DRF_DEF(_PFALCON, _FALCON_IRQSCLR, _HALT, _SET)); + kgspDumpGspLogs(pKernelGsp, NV_FALSE); - kgspHealthCheck_HAL(pGpu, pKernelGsp); + (void)kgspHealthCheck_HAL(pGpu, pKernelGsp); } if (intrStatus & DRF_DEF(_PFALCON, _FALCON_IRQSTAT, _SWGEN0, _TRUE)) { @@ -880,9 +916,6 @@ NV_CHECK_OR_RETURN(LEVEL_SILENT, !pKernelGsp->bInLockdown, 0); } - // Clear any sources that were serviced and get the new status - kflcnRegWrite_HAL(pGpu, pKernelFalcon, NV_PFALCON_FALCON_IRQSCLR, clearBits); - kflcnIntrRetrigger_HAL(pGpu, pKernelFalcon); intrStatus = kflcnReadIntrStatus_HAL(pGpu, pKernelFalcon); @@ -903,7 +936,7 @@ // Check for LIBOS_INTERRUPT_PROCESSOR_SUSPENDED in mailbox mailbox = kflcnRegRead_HAL(pGpu, staticCast(pKernelGsp, KernelFalcon), NV_PFALCON_FALCON_MAILBOX0); - return (mailbox & 0x80000000) == 0x80000000; + return (mailbox == 0x80000000); } NV_STATUS @@ -928,9 +961,6 @@ return (wpr2HiVal != 0); } -#define FWSECLIC_PROG_START_TIMEOUT 50000 // 50ms -#define FWSECLIC_PROG_COMPLETE_TIMEOUT 2000000 // 2s - NV_STATUS kgspWaitForGfwBootOk_TU102 ( @@ -938,49 +968,170 @@ KernelGsp *pKernelGsp ) { - NvU32 timeoutUs = FWSECLIC_PROG_START_TIMEOUT + FWSECLIC_PROG_COMPLETE_TIMEOUT; - RMTIMEOUT timeout; NV_STATUS status = NV_OK; - // Use the OS timer since the GPU timer is not ready yet - gpuSetTimeout(pGpu, gpuScaleTimeout(pGpu, timeoutUs), &timeout, - GPU_TIMEOUT_FLAGS_OSTIMER); + status = gpuWaitForGfwBootComplete_HAL(pGpu); + if (status != NV_OK) + { + NV_PRINTF(LEVEL_ERROR, "failed to wait for GFW boot complete: 0x%x VBIOS version %s\n", + status, pKernelGsp->vbiosVersionStr); + NV_PRINTF(LEVEL_ERROR, "(the GPU may be in a bad state and may need to be reset)\n"); + } - while (status == NV_OK) + return status; +} + +void +kgspFreeSuspendResumeData_TU102 +( + OBJGPU *pGpu, + KernelGsp *pKernelGsp +) +{ + // release sr meta data resources + if (pKernelGsp->pSRMetaDescriptor != NULL) { - // - // Before reading the actual GFW_BOOT status register, - // we want to check that FWSEC has lowered its PLM first. - // If not then obviously it has not completed. - // - if (GPU_FLD_TEST_DRF_DEF(pGpu, - _PGC6, - _AON_SECURE_SCRATCH_GROUP_05_PRIV_LEVEL_MASK, - _READ_PROTECTION_LEVEL0, - _ENABLE) - ) - { - if (GPU_FLD_TEST_DRF_DEF(pGpu, - _PGC6, - _AON_SECURE_SCRATCH_GROUP_05_0_GFW_BOOT, - _PROGRESS, - _COMPLETED) - ) - { - return NV_OK; - } - } + memdescFree(pKernelGsp->pSRMetaDescriptor); + memdescDestroy(pKernelGsp->pSRMetaDescriptor); + pKernelGsp->pSRMetaDescriptor = NULL; + } - status = gpuCheckTimeout(pGpu, &timeout); + // release sr meta data resources + if (pKernelGsp->pSRRadix3Descriptor != NULL) + { + memdescFree(pKernelGsp->pSRRadix3Descriptor); + memdescDestroy(pKernelGsp->pSRRadix3Descriptor); + pKernelGsp->pSRRadix3Descriptor = NULL; } +} - // The wait failed if we reach here (as above loop returns upon success). - NV_PRINTF(LEVEL_ERROR, "failed to wait for GFW_BOOT: 0x%x (progress 0x%x)\n", - status, GPU_REG_RD_DRF(pGpu, - _PGC6, - _AON_SECURE_SCRATCH_GROUP_05_0_GFW_BOOT, - _PROGRESS)); - NV_PRINTF(LEVEL_ERROR, "(the GPU may be in a bad state and may need to be reset)\n"); +NV_STATUS +kgspSavePowerMgmtState_TU102 +( + OBJGPU *pGpu, + KernelGsp *pKernelGsp +) +{ + GspFwSRMeta gspfwSRMeta; + NvP64 pVa = NvP64_NULL; + NvP64 pPriv = NvP64_NULL; + NV_STATUS nvStatus = NV_OK; - return status; + // Fill in GspFwSRMeta structure + portMemSet(&gspfwSRMeta, 0, sizeof(gspfwSRMeta)); + gspfwSRMeta.magic = GSP_FW_SR_META_MAGIC; + gspfwSRMeta.revision = GSP_FW_SR_META_REVISION; + gspfwSRMeta.sizeOfSuspendResumeData = pKernelGsp->pWprMeta->gspFwWprEnd - pKernelGsp->pWprMeta->gspFwWprStart; + + + NV_ASSERT_OK_OR_GOTO(nvStatus, + kgspCreateRadix3(pGpu, + pKernelGsp, + &pKernelGsp->pSRRadix3Descriptor, + NULL, + NULL, + gspfwSRMeta.sizeOfSuspendResumeData), + exit_fail_cleanup); + + gspfwSRMeta.sysmemAddrOfSuspendResumeData = memdescGetPhysAddr(pKernelGsp->pSRRadix3Descriptor, AT_GPU, 0); + + // Create SR Metadata Area + NV_ASSERT_OK_OR_GOTO(nvStatus, + memdescCreate(&pKernelGsp->pSRMetaDescriptor, + pGpu, + sizeof(GspFwSRMeta), + 256, + NV_TRUE, + ADDR_SYSMEM, + NV_MEMORY_UNCACHED, + MEMDESC_FLAGS_NONE), + exit_fail_cleanup); + + NV_ASSERT_OK_OR_GOTO(nvStatus, + memdescAlloc(pKernelGsp->pSRMetaDescriptor), + exit_fail_cleanup); + + // Copy SR Metadata Structure + NV_ASSERT_OK_OR_GOTO(nvStatus, + memdescMap(pKernelGsp->pSRMetaDescriptor, + 0, + memdescGetSize(pKernelGsp->pSRMetaDescriptor), + NV_TRUE, + NV_PROTECT_WRITEABLE, + &pVa, + &pPriv), + exit_fail_cleanup); + + portMemCopy(pVa, sizeof(gspfwSRMeta), &gspfwSRMeta, sizeof(gspfwSRMeta)); + + memdescUnmap(pKernelGsp->pSRMetaDescriptor, + NV_TRUE, osGetCurrentProcess(), + pVa, pPriv); + + NV_ASSERT_OK_OR_GOTO(nvStatus, + kgspExecuteBooterUnloadIfNeeded_HAL(pGpu, + pKernelGsp, + memdescGetPhysAddr(pKernelGsp->pSRMetaDescriptor,AT_GPU, 0)), + exit_fail_cleanup); + + return nvStatus; + +exit_fail_cleanup: + kgspFreeSuspendResumeData_HAL(pGpu, pKernelGsp); + return nvStatus; +} + +NV_STATUS +kgspRestorePowerMgmtState_TU102 +( + OBJGPU *pGpu, + KernelGsp *pKernelGsp +) +{ + NV_STATUS nvStatus = NV_OK; + + NV_ASSERT_TRUE_OR_GOTO(nvStatus, pKernelGsp->pSRMetaDescriptor != NULL, NV_ERR_INVALID_STATE, exit_cleanup); + + NV_ASSERT_OK_OR_GOTO(nvStatus, + kgspExecuteBooterLoad_HAL(pGpu, + pKernelGsp, + memdescGetPhysAddr(pKernelGsp->pSRMetaDescriptor, AT_GPU,0)), + exit_cleanup); + +exit_cleanup: + kgspFreeSuspendResumeData_HAL(pGpu, pKernelGsp); + return nvStatus; +} + +void +kgspReadEmem_TU102 +( + KernelGsp *pKernelGsp, + NvU64 offset, + NvU64 size, + void *pBuf +) +{ + NvU32 ememMask = DRF_SHIFTMASK(NV_PGSP_EMEMC_OFFS) | DRF_SHIFTMASK(NV_PGSP_EMEMC_BLK); + OBJGPU *pGpu = ENG_GET_GPU(pKernelGsp); + NvU32 limit = size - NVBIT(DRF_SHIFT(NV_PGSP_EMEMC_OFFS)); + NvU32 *pBuffer = pBuf; + + portMemSet(pBuf, 0, size); + +#if defined(DEBUG) || defined(DEVELOP) + NV_ASSERT_OR_RETURN_VOID((offset & ~ememMask) == 0); + NV_ASSERT_OR_RETURN_VOID(limit <= ememMask); + NV_ASSERT_OR_RETURN_VOID(offset + limit <= ememMask); +#else + NV_CHECK_OR_RETURN_VOID(LEVEL_SILENT, (offset & ~ememMask) == 0); + NV_CHECK_OR_RETURN_VOID(LEVEL_SILENT, limit <= ememMask); + NV_CHECK_OR_RETURN_VOID(LEVEL_SILENT, offset + limit <= ememMask); +#endif + + GPU_REG_WR32(pGpu, NV_PGSP_EMEMC(pKernelGsp->ememPort), + offset | DRF_DEF(_PGSP, _EMEMC, _AINCR, _TRUE)); + + for (NvU32 idx = 0; idx < size / sizeof(NvU32); idx++) + pBuffer[idx] = GPU_REG_RD32(pGpu, NV_PGSP_EMEMD(pKernelGsp->ememPort)); } diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/kernel/gpu/gsp/arch/turing/kernel_gsp_vbios_tu102.c nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/kernel/gpu/gsp/arch/turing/kernel_gsp_vbios_tu102.c --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/kernel/gpu/gsp/arch/turing/kernel_gsp_vbios_tu102.c 2023-10-25 20:21:06.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/kernel/gpu/gsp/arch/turing/kernel_gsp_vbios_tu102.c 2024-03-05 22:13:30.000000000 +0000 @@ -33,7 +33,7 @@ */ #include "gpu/gsp/kernel_gsp.h" -#include "gpu/pmu/kern_pmu.h" +#include "gpu/bif/kernel_bif.h" #include "platform/pci_exp_table.h" // PCI_EXP_ROM_* #include "gpu/gpu.h" @@ -452,7 +452,7 @@ NV_STATUS status = NV_OK; KernelGspVbiosImg *pVbiosImg = NULL; - KernelPmu *pKernelPmu = GPU_GET_KERNEL_PMU(pGpu); + KernelBif *pKernelBif = GPU_GET_KERNEL_BIF(pGpu); RomImgSrc src; NvU32 romSig; @@ -479,9 +479,9 @@ src.maxOffset = biosSize; src.pGpu = pGpu; - if (pKernelPmu != NULL) + if (pKernelBif != NULL) { - status = kpmuPreOsGlobalErotGrantRequest_HAL(pGpu, pKernelPmu); + status = kbifPreOsGlobalErotGrantRequest_HAL(pGpu, pKernelBif); if (status != NV_OK) { NV_PRINTF(LEVEL_ERROR, "ERoT Req/Grant for EEPROM access failed, status=%u\n", diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/kernel/gpu/gsp/kernel_gsp.c nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/kernel/gpu/gsp/kernel_gsp.c --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/kernel/gpu/gsp/kernel_gsp.c 2023-10-25 20:21:06.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/kernel/gpu/gsp/kernel_gsp.c 2024-03-05 22:13:30.000000000 +0000 @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 2019-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2019-2024 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -21,24 +21,32 @@ * DEALINGS IN THE SOFTWARE. */ +#include "resserv/rs_server.h" + #include "gpu/gsp/kernel_gsp.h" #include "kernel/core/thread_state.h" #include "kernel/core/locks.h" #include "kernel/diagnostics/gpu_acct.h" +#include "kernel/diagnostics/journal.h" #include "kernel/gpu/fifo/kernel_channel.h" #include "kernel/gpu/intr/engine_idx.h" #include "kernel/gpu/mem_mgr/heap.h" #include "kernel/gpu/mem_mgr/mem_mgr.h" +#include "kernel/gpu/mem_sys/kern_mem_sys.h" #include "kernel/gpu/rc/kernel_rc.h" #include "kernel/gpu/nvlink/kernel_nvlink.h" +#include "virtualization/hypervisor/hypervisor.h" #include "virtualization/vgpuconfigapi.h" #include "kernel/gpu/disp/kern_disp.h" +#include "kernel/gpu/mig_mgr/kernel_mig_manager.h" #include "gpu/external_device/external_device.h" +#include "kernel/platform/platform_request_handler.h" #include "class/cl2080.h" // NV20_SUBDEVICE_0 #include "liblogdecode.h" #include "libelf.h" #include "nverror.h" +#include "nvrm_registry.h" #include "nv-firmware.h" #include "nv-firmware-chip-family-select.h" #include "nvtypes.h" @@ -53,6 +61,7 @@ #include "kernel/gpu/pmu/kern_pmu.h" #include "gpu/perf/kern_perf.h" #include "core/locks.h" +#include "kernel/gpu/intr/intr.h" #define RPC_STRUCTURES #define RPC_GENERIC_UNION @@ -68,8 +77,18 @@ #include "gpu/gsp/message_queue_priv.h" +#include "gpu/conf_compute/conf_compute.h" + #define RPC_HDR ((rpc_message_header_v*)(pRpc->message_buffer)) +struct MIG_CI_UPDATE_CALLBACK_PARAMS +{ + NvU32 execPartCount; + NvU32 execPartId[NVC637_CTRL_MAX_EXEC_PARTITIONS]; + NvU32 gfid; + NvBool bDelete; +}; + // // RPC_PARAMS defines the rpc_params pointer and initializes it to the correct // sub-structure. @@ -88,6 +107,8 @@ static NV_STATUS _kgspInitRpcInfrastructure(OBJGPU *, KernelGsp *); static void _kgspFreeRpcInfrastructure(OBJGPU *, KernelGsp *); +static NV_STATUS _kgspConstructRpcObject(OBJGPU *, KernelGsp *, MESSAGE_QUEUE_INFO *, OBJRPC **); + static NV_STATUS _kgspRpcSendMessage(OBJGPU *, OBJRPC *); static NV_STATUS _kgspRpcRecvPoll(OBJGPU *, OBJRPC *, NvU32); static NV_STATUS _kgspRpcDrainEvents(OBJGPU *, KernelGsp *, NvU32); @@ -102,9 +123,6 @@ static NV_STATUS _kgspPrepareGspRmBinaryImage(OBJGPU *pGpu, KernelGsp *pKernelGsp, GSP_FIRMWARE *pGspFw); -static NV_STATUS _kgspCreateRadix3(OBJGPU *pGpu, MEMORY_DESCRIPTOR **ppMemdescRadix3, - MEMORY_DESCRIPTOR *pMemdescData, const void *pData, NvU64 size); - static NV_STATUS _kgspCreateSignatureMemdesc(OBJGPU *pGpu, KernelGsp *pKernelGsp, GSP_FIRMWARE *pGspFw); @@ -126,33 +144,72 @@ ( OBJRPC *pRpc, NvU32 function, - NvU32 *data0, - NvU32 *data1 + NvU64 *data0, + NvU64 *data1 ) { switch (function) { + // Functions (CPU -> GSP) case NV_VGPU_MSG_FUNCTION_GSP_RM_CONTROL: { - rpc_gsp_rm_control_v03_00 *rpc_params = &rpc_message->gsp_rm_control_v03_00; + RPC_PARAMS(gsp_rm_control, _v03_00); *data0 = rpc_params->cmd; *data1 = rpc_params->paramsSize; break; } case NV_VGPU_MSG_FUNCTION_GSP_RM_ALLOC: { - rpc_gsp_rm_alloc_v03_00 *rpc_params = &rpc_message->gsp_rm_alloc_v03_00; + RPC_PARAMS(gsp_rm_alloc, _v03_00); *data0 = rpc_params->hClass; *data1 = rpc_params->paramsSize; break; } case NV_VGPU_MSG_FUNCTION_FREE: { - rpc_free_v03_00 *rpc_params = &rpc_message->free_v03_00; + RPC_PARAMS(free, _v03_00); *data0 = rpc_params->params.hObjectOld; *data1 = rpc_params->params.hObjectParent; break; } + + // Events (CPU <- GSP) + case NV_VGPU_MSG_EVENT_GSP_RUN_CPU_SEQUENCER: + { + RPC_PARAMS(run_cpu_sequencer, _v17_00); + *data0 = rpc_params->cmdIndex; + *data1 = rpc_params->bufferSizeDWord; + break; + } + case NV_VGPU_MSG_EVENT_POST_EVENT: + { + RPC_PARAMS(post_event, _v17_00); + *data0 = rpc_params->notifyIndex; + *data1 = rpc_params->data; + break; + } + case NV_VGPU_MSG_EVENT_RC_TRIGGERED: + { + RPC_PARAMS(rc_triggered, _v17_02); + *data0 = rpc_params->nv2080EngineType; + *data1 = rpc_params->exceptType; + break; + } + case NV_VGPU_MSG_EVENT_VGPU_GSP_PLUGIN_TRIGGERED: + { + RPC_PARAMS(vgpu_gsp_plugin_triggered, _v17_00); + *data0 = rpc_params->gfid; + *data1 = rpc_params->notifyIndex; + break; + } + case NV_VGPU_MSG_EVENT_GSP_LOCKDOWN_NOTICE: + { + RPC_PARAMS(gsp_lockdown_notice, _v17_00); + *data0 = rpc_params->bLockdownEngaging; + *data1 = 0; + break; + } + default: { *data0 = 0; @@ -163,42 +220,98 @@ } static NV_STATUS -_kgspRpcSanityCheck(OBJGPU *pGpu) +_kgspRpcSanityCheck(OBJGPU *pGpu, KernelGsp *pKernelGsp, OBJRPC *pRpc) { + if (pKernelGsp->bFatalError) + { + NV_PRINTF(LEVEL_INFO, "GSP crashed, skipping RPC\n"); + // + // In case of a fatal GSP error, if there was an outstanding RPC at the + // time, we should have already printed the error for that, so this is a + // new RPC call...from now on don't bother printing RPC errors anymore, + // as it can be too noisy and overrun logs. + // + pRpc->bQuietPrints = NV_TRUE; + return NV_ERR_RESET_REQUIRED; + } if (API_GPU_IN_RESET_SANITY_CHECK(pGpu)) { - NV_PRINTF(LEVEL_INFO, - "GPU in reset, skipping RPC\n"); + NV_PRINTF(LEVEL_INFO, "GPU in reset, skipping RPC\n"); return NV_ERR_GPU_IN_FULLCHIP_RESET; } if (!API_GPU_ATTACHED_SANITY_CHECK(pGpu) || pGpu->getProperty(pGpu, PDB_PROP_GPU_IS_LOST)) { - NV_PRINTF(LEVEL_INFO, - "GPU lost, skipping RPC\n"); + NV_PRINTF(LEVEL_INFO, "GPU lost, skipping RPC\n"); return NV_ERR_GPU_IS_LOST; } if (osIsGpuShutdown(pGpu)) { - NV_PRINTF(LEVEL_INFO, - "GPU shutdown, skipping RPC\n"); + NV_PRINTF(LEVEL_INFO, "GPU shutdown, skipping RPC\n"); return NV_ERR_GPU_IS_LOST; } if (!gpuIsGpuFullPowerForPmResume(pGpu)) { - NV_PRINTF(LEVEL_INFO, - "GPU not full power, skipping RPC\n"); + NV_PRINTF(LEVEL_INFO, "GPU not full power, skipping RPC\n"); return NV_ERR_GPU_NOT_FULL_POWER; } if (!gpuCheckSysmemAccess(pGpu)) { - NV_PRINTF(LEVEL_INFO, - "GPU has no sysmem access, skipping RPC\n"); + NV_PRINTF(LEVEL_INFO, "GPU has no sysmem access, skipping RPC\n"); return NV_ERR_INVALID_ACCESS_TYPE; } return NV_OK; } +static void +_kgspAddRpcHistoryEntry +( + OBJRPC *pRpc, + RpcHistoryEntry *pHistory, + NvU32 *pCurrent +) +{ + NvU32 func = RPC_HDR->function; + NvU32 entry; + + entry = *pCurrent = (*pCurrent + 1) % RPC_HISTORY_DEPTH; + + portMemSet(&pHistory[entry], 0, sizeof(pHistory[0])); + pHistory[entry].function = func; + pHistory[entry].ts_start = osGetTimestamp(); + + _kgspGetActiveRpcDebugData(pRpc, func, + &pHistory[entry].data[0], + &pHistory[entry].data[1]); +} + +static void +_kgspCompleteRpcHistoryEntry +( + RpcHistoryEntry *pHistory, + NvU32 current +) +{ + NvU32 historyIndex; + NvU32 historyEntry; + + pHistory[current].ts_end = osGetTimestamp(); + + // + // Complete any previous entries that aren't marked complete yet, using the same timestamp + // (we may not have explicitly waited for them) + // + for (historyIndex = 0; historyIndex < RPC_HISTORY_DEPTH; historyIndex++) + { + historyEntry = (current + RPC_HISTORY_DEPTH - historyIndex) % RPC_HISTORY_DEPTH; + if (pHistory[historyEntry].ts_start != 0 && + pHistory[historyEntry].ts_end == 0) + { + pHistory[historyEntry].ts_end = pHistory[current].ts_end; + } + } +} + /*! * GSP client RM RPC send routine */ @@ -214,7 +327,7 @@ NV_ASSERT(rmDeviceGpuLockIsOwner(pGpu->gpuInstance)); - NV_CHECK_OK_OR_RETURN(LEVEL_SILENT, _kgspRpcSanityCheck(pGpu)); + NV_CHECK_OK_OR_RETURN(LEVEL_SILENT, _kgspRpcSanityCheck(pGpu, pKernelGsp, pRpc)); nvStatus = GspMsgQueueSendCommand(pRpc->pMessageQueueInfo, pGpu); if (nvStatus != NV_OK) @@ -230,23 +343,9 @@ return nvStatus; } - // GSPRM TODO: Use this call to pass the actual index. - kgspSetCmdQueueHead_HAL(pGpu, pKernelGsp, 0, 0); + kgspSetCmdQueueHead_HAL(pGpu, pKernelGsp, pRpc->pMessageQueueInfo->queueIdx, 0); - // Add RPC history entry - { - NvU32 func = vgpu_rpc_message_header_v->function; - NvU32 entry; - - entry = pRpc->rpcHistoryCurrent = (pRpc->rpcHistoryCurrent + 1) % RPC_HISTORY_DEPTH; - - portMemSet(&pRpc->rpcHistory[entry], 0, sizeof(pRpc->rpcHistory[0])); - pRpc->rpcHistory[entry].function = func; - - _kgspGetActiveRpcDebugData(pRpc, func, - &pRpc->rpcHistory[entry].data[0], - &pRpc->rpcHistory[entry].data[1]); - } + _kgspAddRpcHistoryEntry(pRpc, pRpc->rpcHistory, &pRpc->rpcHistoryCurrent); return NV_OK; } @@ -336,8 +435,8 @@ if (rpc_params->bNotifyList) { // Send notification to all matching events on the list. - nvStatus = osEventNotification(pGpu, pNotifyList, rpc_params->notifyIndex, - rpc_params->eventData, rpc_params->eventDataSize); + nvStatus = osEventNotificationWithInfo(pGpu, pNotifyList, rpc_params->notifyIndex, + rpc_params->data, rpc_params->info16, rpc_params->eventData, rpc_params->eventDataSize); } else { @@ -382,6 +481,18 @@ // check if there's a PCI-E error pending either in device status or in AER krcCheckBusError_HAL(pGpu, pKernelRc); + // + // If we have received a special msg from GSP then ack back immediately + // that we are done writing notifiers since we would have already processed the + // other RC msgs that trigger notifier writes before this one. + // + if (rpc_params->exceptType == ROBUST_CHANNEL_FAST_PATH_ERROR) + { + NV_RM_RPC_ECC_NOTIFIER_WRITE_ACK(pGpu, status); + NV_ASSERT_OK(status); + return status; + } + status = kfifoGetChidMgrFromType(pGpu, pKernelFifo, ENGINE_INFO_TYPE_RM_ENGINE_TYPE, (NvU32)rmEngineType, @@ -396,6 +507,74 @@ pKernelChannel != NULL, NV_ERR_INVALID_CHANNEL); + // Add the RcDiag records we received from GSP-RM to our system wide journal + { + OBJSYS *pSys = SYS_GET_INSTANCE(); + Journal *pRcDB = SYS_GET_RCDB(pSys); + RmClient *pClient; + + NvU32 recordSize = rcdbGetOcaRecordSizeWithHeader(pRcDB, RmRcDiagReport); + NvU32 rcDiagRecStart = pRcDB->RcErrRptNextIdx; + NvU32 rcDiagRecEnd; + NvU32 processId = 0; + NvU32 owner = RCDB_RCDIAG_DEFAULT_OWNER; + + pClient = dynamicCast(RES_GET_CLIENT(pKernelChannel), RmClient); + NV_ASSERT(pClient != NULL); + if (pClient != NULL) + processId = pClient->ProcID; + + for (NvU32 i = 0; i < rpc_params->rcJournalBufferSize / recordSize; i++) + { + RmRCCommonJournal_RECORD *pCommonRecord = + (RmRCCommonJournal_RECORD *)((NvU8*)&rpc_params->rcJournalBuffer + i * recordSize); + RmRcDiag_RECORD *pRcDiagRecord = + (RmRcDiag_RECORD *)&pCommonRecord[1]; + +#if defined(DEBUG) + NV_PRINTF(LEVEL_INFO, "%d: GPUTag=0x%x CPUTag=0x%llx timestamp=0x%llx stateMask=0x%llx\n", + i, pCommonRecord->GPUTag, pCommonRecord->CPUTag, pCommonRecord->timeStamp, + pCommonRecord->stateMask); + NV_PRINTF(LEVEL_INFO, " idx=%d timeStamp=0x%x type=0x%x flags=0x%x count=%d owner=0x%x processId=0x%x\n", + pRcDiagRecord->idx, pRcDiagRecord->timeStamp, pRcDiagRecord->type, pRcDiagRecord->flags, + pRcDiagRecord->count, pRcDiagRecord->owner, processId); + for (NvU32 j = 0; j < pRcDiagRecord->count; j++) + { + NV_PRINTF(LEVEL_INFO, " %d: offset=0x08%x tag=0x08%x value=0x08%x attribute=0x08%x\n", + j, pRcDiagRecord->data[j].offset, pRcDiagRecord->data[j].tag, + pRcDiagRecord->data[j].value, pRcDiagRecord->data[j].attribute); + } +#endif + if (rcdbAddRcDiagRecFromGsp(pGpu, pRcDB, pCommonRecord, pRcDiagRecord) == NULL) + { + NV_PRINTF(LEVEL_WARNING, "Lost RC diagnostic record coming from GPU%d GSP: type=0x%x stateMask=0x%llx\n", + gpuGetInstance(pGpu), pRcDiagRecord->type, pCommonRecord->stateMask); + } + } + + rcDiagRecEnd = pRcDB->RcErrRptNextIdx - 1; + + // Update records to have the correct PID associated with the channel + if (rcDiagRecStart != rcDiagRecEnd) + { + rcdbUpdateRcDiagRecContext(pRcDB, + rcDiagRecStart, + rcDiagRecEnd, + processId, + owner); + } + } + + // With CC enabled, CPU-RM needs to write error notifiers + if (gpuIsCCFeatureEnabled(pGpu)) + { + NV_ASSERT_OK_OR_RETURN(krcErrorSetNotifier(pGpu, pKernelRc, + pKernelChannel, + rpc_params->exceptType, + rmEngineType, + rpc_params->scope)); + } + return krcErrorSendEventNotifications_HAL(pGpu, pKernelRc, pKernelChannel, rmEngineType, // unused on kernel side @@ -550,6 +729,20 @@ } static void +_kgspRpcNvlinkFaultUpCallback +( + OBJGPU *pGpu, + OBJRPC *pRpc +) +{ + RPC_PARAMS(nvlink_fault_up, _v17_00); + + KernelNvlink *pKernelNvlink = GPU_GET_KERNEL_NVLINK(pGpu); + + knvlinkHandleFaultUpInterrupt_HAL(pGpu, pKernelNvlink, rpc_params->linkId); +} + +static void _kgspRpcNvlinkInbandReceivedData256Callback ( OBJGPU *pGpu, @@ -717,6 +910,12 @@ ) { RPC_PARAMS(semaphore_schedule_callback, _v17_00); + NV_STATUS status; + RsClient *pClient; + + status = serverGetClientUnderLock(&g_resServ, rpc_params->hClient, &pClient); + if (status != NV_OK) + return status; return dispswReleaseSemaphoreAndNotifierFill(pGpu, rpc_params->GPUVA, @@ -724,8 +923,7 @@ rpc_params->ReleaseValue, rpc_params->Flags, rpc_params->completionStatus, - rpc_params->hClient, - rpc_params->hEvent); + pClient, rpc_params->hEvent); } static NV_STATUS @@ -735,6 +933,12 @@ ) { RPC_PARAMS(timed_semaphore_release, _v01_00); + NV_STATUS status; + RsClient *pClient; + + status = serverGetClientUnderLock(&g_resServ, rpc_params->hClient, &pClient); + if (status != NV_OK) + return status; return tsemaRelease_HAL(pGpu, rpc_params->semaphoreVA, @@ -742,7 +946,7 @@ rpc_params->hVASpace, rpc_params->releaseValue, rpc_params->completionStatus, - rpc_params->hClient); + pClient); } @@ -821,6 +1025,79 @@ return NV_OK; } +static void +_kgspRpcGspSendUserSharedData +( + OBJGPU *pGpu, + OBJRPC *pRpc +) +{ + RPC_PARAMS(gsp_send_user_shared_data, _v17_00); + NV00DE_SHARED_DATA *pSharedData = gpushareddataWriteStart(pGpu); + GspUserSharedData *pRpcData = (GspUserSharedData*)(&rpc_params->data); + + // Copy over all GSP-owned data + pSharedData->gspAssertCount = pRpcData->gspAssertCount; + + gpushareddataWriteFinish(pGpu); +} + +static void _kgspRpcMigCiConfigUpdateCallback +( + NvU32 gpuInstance, + void *pArgs +) +{ + OBJGPU *pGpu = gpumgrGetGpu(gpuInstance); + KernelMIGManager *pKernelMIGManager = GPU_GET_KERNEL_MIG_MANAGER(pGpu); + struct MIG_CI_UPDATE_CALLBACK_PARAMS * pParams = (struct MIG_CI_UPDATE_CALLBACK_PARAMS *)pArgs; + + kmigmgrUpdateCiConfigForVgpu(pGpu, pKernelMIGManager, + pParams->execPartCount, pParams->execPartId, + pParams->gfid, pParams->bDelete); + + return; +} + +static NV_STATUS +_kgspRpcMigCiConfigUpdate +( + OBJGPU *pGpu, + OBJRPC *pRpc +) +{ + NV_STATUS status; + OBJOS *pOS = GPU_GET_OS(pGpu); + struct MIG_CI_UPDATE_CALLBACK_PARAMS *pParams; + + RPC_PARAMS(vgpu_gsp_mig_ci_config, _v21_03); + + NV_ASSERT_OR_RETURN(rpc_params->execPartCount <= NVC637_CTRL_MAX_EXEC_PARTITIONS, + NV_ERR_INVALID_ARGUMENT); + + pParams = portMemAllocNonPaged(sizeof(struct MIG_CI_UPDATE_CALLBACK_PARAMS)); + if (pParams == NULL) + { + return NV_ERR_NO_MEMORY; + } + + pParams->execPartCount = rpc_params->execPartCount; + portMemCopy(pParams->execPartId, (sizeof(NvU32) * rpc_params->execPartCount), + rpc_params->execPartId, (sizeof(NvU32) * rpc_params->execPartCount)); + pParams->gfid = rpc_params->gfid; + pParams->bDelete = rpc_params->bDelete; + status = pOS->osQueueWorkItemWithFlags(pGpu, + _kgspRpcMigCiConfigUpdateCallback, + (void *)pParams, + OS_QUEUE_WORKITEM_FLAGS_LOCK_API_RW | OS_QUEUE_WORKITEM_FLAGS_LOCK_GPUS_RW); + if (status != NV_OK) + { + portMemFree(pParams); + } + + return status; +} + static NV_STATUS _kgspRpcRgLineIntr ( @@ -845,6 +1122,37 @@ OBJRPC* pRpc ) { + OBJSYS *pSys = SYS_GET_INSTANCE(); + PlatformRequestHandler* pPlatformRequestHandler + = SYS_GET_PFM_REQ_HNDLR(pSys); + + RPC_PARAMS(pfm_req_hndlr_state_sync_callback, _v21_04); + + NV2080_CTRL_INTERNAL_PFM_REQ_HNDLR_STATE_SYNC_PARAMS_v21_04 *src = &rpc_params->params; + NV2080_CTRL_INTERNAL_PFM_REQ_HNDLR_STATE_SYNC_PARAMS dst = { 0 }; + + dst.flags = src->flags; + dst.syncData.type = src->syncData.type; + + // Copy in the rpc data + switch (src->syncData.type) + { + case NV2080_CTRL_INTERNAL_PFM_REQ_HNDLR_STATE_SYNC_DATA_TYPE_SMBPBI: + { + dst.syncData.data.smbpbi.sensorId = + src->syncData.data.smbpbi.sensorId; + dst.syncData.data.smbpbi.limit = + src->syncData.data.smbpbi.limit; + break; + } + default: + { + // Nothing for now + break; + } + } + + pfmreqhndlrStateSync(pPlatformRequestHandler, pGpu, &dst); return NV_OK; } @@ -901,7 +1209,7 @@ /*! * GSP client process RPC events */ -static NV_STATUS +static void _kgspProcessRpcEvent ( OBJGPU *pGpu, @@ -910,11 +1218,14 @@ { rpc_message_header_v *pMsgHdr = RPC_HDR; NV_STATUS nvStatus = NV_OK; + NvU32 event = pMsgHdr->function; - NV_PRINTF(LEVEL_INFO, "received event: 0x%x (%s) status: 0x%x size: %d\n", - pMsgHdr->function, _getRpcName(pMsgHdr->function), pMsgHdr->rpc_result, pMsgHdr->length); + NV_PRINTF(LEVEL_INFO, "received event from GPU%d: 0x%x (%s) status: 0x%x size: %d\n", + gpuGetInstance(pGpu), event, _getRpcName(event), pMsgHdr->rpc_result, pMsgHdr->length); - switch(pMsgHdr->function) + _kgspAddRpcHistoryEntry(pRpc, pRpc->rpcEventHistory, &pRpc->rpcEventHistoryCurrent); + + switch(event) { case NV_VGPU_MSG_EVENT_GSP_RUN_CPU_SEQUENCER: nvStatus = _kgspRpcRunCpuSequencer(pGpu, pRpc); @@ -964,6 +1275,10 @@ _kgspRpcTimedSemaphoreRelease(pGpu, pRpc); break; + case NV_VGPU_MSG_EVENT_NVLINK_FAULT_UP: + _kgspRpcNvlinkFaultUpCallback(pGpu, pRpc); + break; + case NV_VGPU_MSG_EVENT_NVLINK_INBAND_RECEIVED_DATA_256: _kgspRpcNvlinkInbandReceivedData256Callback(pGpu, pRpc); break; @@ -1012,6 +1327,14 @@ nvStatus = _kgspRpcEventPlatformRequestHandlerStateSyncCallback(pGpu, pRpc); break; + case NV_VGPU_MSG_EVENT_MIG_CI_CONFIG_UPDATE: + nvStatus = _kgspRpcMigCiConfigUpdate(pGpu, pRpc); + break; + + case NV_VGPU_MSG_EVENT_GSP_SEND_USER_SHARED_DATA: + _kgspRpcGspSendUserSharedData(pGpu, pRpc); + break; + case NV_VGPU_MSG_EVENT_GSP_LOCKDOWN_NOTICE: _kgspRpcGspLockdownNotice(pGpu, pRpc); break; @@ -1019,17 +1342,29 @@ case NV_VGPU_MSG_EVENT_GSP_INIT_DONE: // Handled by _kgspRpcRecvPoll. default: // + // Log, but otherwise ignore unexpected events. + // // We will get here if the previous RPC timed out. The response // eventually comes in as an unexpected event. The error handling - // for the timeout has already happened, and returning an error here - // causes subsequent messages to fail. So return NV_OK. + // for the timeout should have already happened. // - NV_PRINTF(LEVEL_ERROR, "Unexpected RPC event 0x%x (%s)\n", - pMsgHdr->function, _getRpcName(pMsgHdr->function)); + NV_PRINTF(LEVEL_ERROR, "Unexpected RPC event from GPU%d: 0x%x (%s)\n", + gpuGetInstance(pGpu), event, _getRpcName(event)); break; } - return nvStatus; + if (nvStatus != NV_OK) + { + // + // Failing to properly handle a specific event does not mean we should stop + // processing events/RPCs, so print the error and soldier on. + // + NV_PRINTF(LEVEL_ERROR, + "Failed to process received event 0x%x (%s) from GPU%d: status=0x%x\n", + event, _getRpcName(event), gpuGetInstance(pGpu), nvStatus); + } + + _kgspCompleteRpcHistoryEntry(pRpc->rpcEventHistory, pRpc->rpcEventHistoryCurrent); } /*! @@ -1040,7 +1375,7 @@ * NV_OK if the event is successfully handled. * NV_WARN_NOTHING_TO_DO if there are no events available. * NV_WARN_MORE_PROCESSING_REQUIRED if the event is expectedFunc: it is unhandled and in the staging area. - * (Another status) if event reading or processing fails. + * (Another status) if event reading fails. */ static NV_STATUS _kgspRpcDrainOneEvent @@ -1057,25 +1392,20 @@ // waiting for a message that has already arrived. portAtomicMemoryFenceFull(); - nvStatus = GspMsgQueueReceiveStatus(pRpc->pMessageQueueInfo); + nvStatus = GspMsgQueueReceiveStatus(pRpc->pMessageQueueInfo, pGpu); if (nvStatus == NV_OK) { rpc_message_header_v *pMsgHdr = RPC_HDR; + if (pMsgHdr->function == expectedFunc) return NV_WARN_MORE_PROCESSING_REQUIRED; - nvStatus = _kgspProcessRpcEvent(pGpu, pRpc); - if (nvStatus != NV_OK) - { - NV_PRINTF(LEVEL_ERROR, - "Failed to process received event 0x%x (%s): status=0x%x\n", - pMsgHdr->function, _getRpcName(pMsgHdr->function), nvStatus); - } + _kgspProcessRpcEvent(pGpu, pRpc); } // - // We don't expect the NV_WARN_MORE_PROCESSING_REQUIRED from either called function. + // We don't expect NV_WARN_MORE_PROCESSING_REQUIRED here. // If we get it we need to suppress it to avoid confusing our caller, for whom it has special meaning. // NV_ASSERT_OR_ELSE(nvStatus != NV_WARN_MORE_PROCESSING_REQUIRED, @@ -1113,7 +1443,9 @@ kgspDumpGspLogs(pKernelGsp, NV_FALSE); } - kgspHealthCheck_HAL(pGpu, pKernelGsp); + // If GSP-RM has died, the GPU will need to be reset + if (!kgspHealthCheck_HAL(pGpu, pKernelGsp)) + return NV_ERR_RESET_REQUIRED; if (nvStatus == NV_WARN_NOTHING_TO_DO) nvStatus = NV_OK; @@ -1121,6 +1453,165 @@ return nvStatus; } +static NvU64 +_tsDiffToDuration +( + NvU64 duration, + char *pDurationUnitsChar +) +{ + const NvU64 tsFreqUs = osGetTimestampFreq() / 1000000; + + *pDurationUnitsChar = 'u'; + + NV_ASSERT_OR_RETURN(tsFreqUs > 0, 0); + + duration /= tsFreqUs; + + // 999999us then 1000ms + if (duration >= 1000000) + { + duration /= 1000; + *pDurationUnitsChar = 'm'; + } + + // 9999ms then 10s + if (duration >= 10000) + { + duration /= 1000; + *pDurationUnitsChar = ' '; // so caller can always just append 's' + } + + return duration; +} + +static NvBool +_kgspIsTimestampDuringRecentRpc +( + OBJRPC *pRpc, + NvU64 timestamp, + NvBool bCheckIncompleteRpcsOnly +) +{ + NvU32 historyIndex; + NvU32 historyEntry; + + for (historyIndex = 0; historyIndex < RPC_HISTORY_DEPTH; historyIndex++) + { + historyEntry = (pRpc->rpcHistoryCurrent + RPC_HISTORY_DEPTH - historyIndex) % RPC_HISTORY_DEPTH; + if (pRpc->rpcHistory[historyEntry].function != 0) + { + if ((timestamp >= pRpc->rpcHistory[historyEntry].ts_start) && + ((pRpc->rpcHistory[historyEntry].ts_end == 0) || + (!bCheckIncompleteRpcsOnly && (timestamp <= pRpc->rpcHistory[historyEntry].ts_end)))) + { + return NV_TRUE; + } + } + } + + return NV_FALSE; +} + +static void +_kgspLogRpcHistoryEntry +( + OBJGPU *pGpu, + NvU32 errorNum, + NvU32 historyIndex, + RpcHistoryEntry *pEntry, + NvBool lastColumnCondition +) +{ + NvU64 duration; + char durationUnitsChar; + + if (pEntry->function != 0) + { + duration = (pEntry->ts_end > pEntry->ts_start) ? (pEntry->ts_end - pEntry->ts_start) : 0; + if (duration) + { + duration = _tsDiffToDuration(duration, &durationUnitsChar); + + NV_ERROR_LOG_DATA(pGpu, errorNum, + " %c%-4d %-4d %-21.21s 0x%016llx 0x%016llx 0x%016llx 0x%016llx %6llu%cs %c\n", + ((historyIndex == 0) ? ' ' : '-'), + historyIndex, + pEntry->function, + _getRpcName(pEntry->function), + pEntry->data[0], + pEntry->data[1], + pEntry->ts_start, + pEntry->ts_end, + duration, durationUnitsChar, + (lastColumnCondition ? 'y' : ' ')); + } + else + { + NV_ERROR_LOG_DATA(pGpu, errorNum, + " %c%-4d %-4d %-21.21s 0x%016llx 0x%016llx 0x%016llx 0x%016llx %c\n", + ((historyIndex == 0) ? ' ' : '-'), + historyIndex, + pEntry->function, + _getRpcName(pEntry->function), + pEntry->data[0], + pEntry->data[1], + pEntry->ts_start, + pEntry->ts_end, + (lastColumnCondition ? 'y' : ' ')); + } + } +} + +void +kgspLogRpcDebugInfo +( + OBJGPU *pGpu, + OBJRPC *pRpc, + NvU32 errorNum, + NvBool bPollingForRpcResponse +) +{ + const rpc_message_header_v *pMsgHdr = RPC_HDR; + NvU32 historyIndex; + NvU32 historyEntry; + NvU64 activeData[2]; + + _kgspGetActiveRpcDebugData(pRpc, pMsgHdr->function, + &activeData[0], &activeData[1]); + NV_ERROR_LOG_DATA(pGpu, errorNum, + "GPU%d GSP RPC buffer contains function %d (%s) and data 0x%016llx 0x%016llx.\n", + gpuGetInstance(pGpu), + pMsgHdr->function, _getRpcName(pMsgHdr->function), + activeData[0], activeData[1]); + + NV_ERROR_LOG_DATA(pGpu, errorNum, + "GPU%d RPC history (CPU -> GSP):\n", + gpuGetInstance(pGpu)); + NV_ERROR_LOG_DATA(pGpu, errorNum, + " entry function data0 data1 ts_start ts_end duration actively_polling\n"); + for (historyIndex = 0; historyIndex < RPC_HISTORY_DEPTH; historyIndex++) + { + historyEntry = (pRpc->rpcHistoryCurrent + RPC_HISTORY_DEPTH - historyIndex) % RPC_HISTORY_DEPTH; + _kgspLogRpcHistoryEntry(pGpu, errorNum, historyIndex, &pRpc->rpcHistory[historyEntry], + ((historyIndex == 0) && bPollingForRpcResponse)); + } + + NV_ERROR_LOG_DATA(pGpu, errorNum, + "GPU%d RPC event history (CPU <- GSP):\n", + gpuGetInstance(pGpu)); + NV_ERROR_LOG_DATA(pGpu, errorNum, + " entry function data0 data1 ts_start ts_end duration during_incomplete_rpc\n"); + for (historyIndex = 0; historyIndex < RPC_HISTORY_DEPTH; historyIndex++) + { + historyEntry = (pRpc->rpcEventHistoryCurrent + RPC_HISTORY_DEPTH - historyIndex) % RPC_HISTORY_DEPTH; + _kgspLogRpcHistoryEntry(pGpu, errorNum, historyIndex, &pRpc->rpcEventHistory[historyEntry], + _kgspIsTimestampDuringRecentRpc(pRpc, + pRpc->rpcEventHistory[historyEntry].ts_start, + NV_TRUE/*bCheckIncompleteRpcsOnly*/)); + } +} + /*! * Log Xid 119 - GSP RPC Timeout */ @@ -1132,65 +1623,37 @@ NvU32 expectedFunc ) { - NvU32 historyEntry = pRpc->rpcHistoryCurrent; - NvU32 activeData[2]; + RpcHistoryEntry *pHistoryEntry = &pRpc->rpcHistory[pRpc->rpcHistoryCurrent]; + NvU64 ts_end = osGetTimestamp(); + NvU64 duration; + char durationUnitsChar; if (pRpc->timeoutCount == 1) { NV_PRINTF(LEVEL_ERROR, - "********************************* GSP Failure **********************************\n"); + "********************************* GSP Timeout **********************************\n"); + NV_PRINTF(LEVEL_ERROR, + "Note: Please also check logs above.\n"); } - NV_ASSERT(expectedFunc == pRpc->rpcHistory[historyEntry].function); + NV_ASSERT(expectedFunc == pHistoryEntry->function); - _kgspGetActiveRpcDebugData(pRpc, expectedFunc, - &activeData[0], &activeData[1]); + NV_ASSERT(ts_end > pHistoryEntry->ts_start); + duration = _tsDiffToDuration(ts_end - pHistoryEntry->ts_start, &durationUnitsChar); - nvErrorLog_va((void*)pGpu, GSP_RPC_TIMEOUT, - "Timeout waiting for RPC from GSP! Expected function %d (%s) (0x%x 0x%x).", - expectedFunc, - _getRpcName(expectedFunc), - pRpc->rpcHistory[historyEntry].data[0], - pRpc->rpcHistory[historyEntry].data[1]); - NVLOG_PRINTF(NV_PRINTF_MODULE, NVLOG_ROUTE_RM, LEVEL_ERROR, NV_PRINTF_ADD_PREFIX - ("Timeout waiting for RPC from GSP%d! Expected function %d (0x%x 0x%x)"), + NV_ERROR_LOG(pGpu, GSP_RPC_TIMEOUT, + "Timeout after %llus of waiting for RPC response from GPU%d GSP! Expected function %d (%s) (0x%x 0x%x).", + (durationUnitsChar == 'm' ? duration / 1000 : duration), gpuGetInstance(pGpu), expectedFunc, - pRpc->rpcHistory[historyEntry].data[0], - pRpc->rpcHistory[historyEntry].data[1]); + _getRpcName(expectedFunc), + pHistoryEntry->data[0], + pHistoryEntry->data[1]); if (pRpc->timeoutCount == 1) { - NvU32 historyIndex; - - if ((expectedFunc != vgpu_rpc_message_header_v->function) || - (pRpc->rpcHistory[historyEntry].data[0] != activeData[0]) || - (pRpc->rpcHistory[historyEntry].data[1] != activeData[1])) - { - NV_PRINTF(LEVEL_ERROR, - "Current RPC function %d (%s) or data (0x%x 0x%x) does not match expected function %d (%s) or data (0x%x 0x%x).\n", - vgpu_rpc_message_header_v->function, _getRpcName(vgpu_rpc_message_header_v->function), - activeData[0], activeData[1], - expectedFunc, _getRpcName(expectedFunc), - pRpc->rpcHistory[historyEntry].data[0], - pRpc->rpcHistory[historyEntry].data[1]); - } - - NV_PRINTF(LEVEL_ERROR, "RPC history (CPU -> GSP):\n"); - NV_PRINTF(LEVEL_ERROR, "\tentry\tfunc\t\t\t\tdata\n"); - for (historyIndex = 0; historyIndex < RPC_HISTORY_DEPTH; historyIndex++) - { - historyEntry = (pRpc->rpcHistoryCurrent + RPC_HISTORY_DEPTH - historyIndex) % RPC_HISTORY_DEPTH; - NV_PRINTF(LEVEL_ERROR, "\t%c%-2d\t%2d %-22s\t0x%08x 0x%08x\n", - ((historyIndex == 0) ? ' ' : '-'), - historyIndex, - pRpc->rpcHistory[historyEntry].function, - _getRpcName(pRpc->rpcHistory[historyEntry].function), - pRpc->rpcHistory[historyEntry].data[0], - pRpc->rpcHistory[historyEntry].data[1]); - } + kgspLogRpcDebugInfo(pGpu, pRpc, GSP_RPC_TIMEOUT, NV_TRUE/*bPollingForRpcResponse*/); - NV_PRINTF(LEVEL_ERROR, "Dumping stack:\n"); osAssertFailed(); NV_PRINTF(LEVEL_ERROR, @@ -1205,17 +1668,8 @@ OBJRPC *pRpc ) { - KernelGsp *pKernelGsp = GPU_GET_KERNEL_GSP(pGpu); - pRpc->timeoutCount++; - if (pKernelGsp->bFatalError) - { - // in case of a fatal GSP error, don't bother printing RPC errors at all - pRpc->bQuietPrints = NV_TRUE; - return; - } - if ((pRpc->timeoutCount == (RPC_TIMEOUT_LIMIT_PRINT_RATE_THRESH + 1)) && (RPC_TIMEOUT_LIMIT_PRINT_RATE_SKIP > 0)) { @@ -1271,6 +1725,7 @@ NV_ASSERT_OR_RETURN(!pKernelGsp->bPollingForRpcResponse, NV_ERR_INVALID_STATE); pKernelGsp->bPollingForRpcResponse = NV_TRUE; + // // GSP-RM init in emulation/simulation environment is extremely slow, // so need to increment timeout. // Apply the timeout extension to other RPCs as well, mostly so that @@ -1296,9 +1751,11 @@ } else { + // // We should only ever timeout this when GSP is in really bad state, so if it just // happens to timeout on default timeout it should be OK for us to give it a little // more time - make this timeout 1.5 of the default to allow some leeway. + // timeoutUs = defaultus + defaultus / 2; } } @@ -1323,6 +1780,8 @@ switch (rpcStatus) { case NV_WARN_MORE_PROCESSING_REQUIRED: + // The synchronous RPC response we were waiting for is here + _kgspCompleteRpcHistoryEntry(pRpc->rpcHistory, pRpc->rpcHistoryCurrent); rpcStatus = NV_OK; goto done; case NV_OK: @@ -1332,7 +1791,7 @@ goto done; } - NV_CHECK_OK_OR_GOTO(rpcStatus, LEVEL_SILENT, _kgspRpcSanityCheck(pGpu), done); + NV_CHECK_OK_OR_GOTO(rpcStatus, LEVEL_SILENT, _kgspRpcSanityCheck(pGpu, pKernelGsp, pRpc), done); if (timeoutStatus == NV_ERR_TIMEOUT) { @@ -1373,50 +1832,97 @@ } /*! - * Initialize stripped down version of RPC infra init for GSP clients. + * Initialize RPC objects required for interfacing with GSP. */ static NV_STATUS _kgspInitRpcInfrastructure ( - OBJGPU *pGpu, + OBJGPU *pGpu, KernelGsp *pKernelGsp ) { NV_STATUS nvStatus = NV_OK; + MESSAGE_QUEUE_COLLECTION *pMQCollection = NULL; - pKernelGsp->pRpc = initRpcObject(pGpu); - if (pKernelGsp->pRpc == NULL) + nvStatus = GspMsgQueuesInit(pGpu, &pMQCollection); + if (nvStatus != NV_OK) { - NV_PRINTF(LEVEL_ERROR, "initRpcObject failed\n"); - return NV_ERR_INSUFFICIENT_RESOURCES; + NV_PRINTF(LEVEL_ERROR, "GspMsgQueueInit failed\n"); + goto done; } - OBJRPC *pRpc = pKernelGsp->pRpc; + pKernelGsp->pMQCollection = pMQCollection; - portMemSet(&pRpc->rpcHistory, 0, sizeof(pRpc->rpcHistory)); - pRpc->rpcHistoryCurrent = RPC_HISTORY_DEPTH - 1; + // Init RM RPC object + nvStatus = _kgspConstructRpcObject(pGpu, pKernelGsp, + &pMQCollection->rpcQueues[RPC_TASK_RM_QUEUE_IDX], + &pKernelGsp->pRpc); + if (nvStatus != NV_OK) + { + NV_PRINTF(LEVEL_ERROR, "init task RM RPC infrastructure failed\n"); + goto done; + } - pRpc->pMessageQueueInfo = NULL; + // Init task_isr RPC object + if (pKernelGsp->bIsTaskIsrQueueRequired) + { + nvStatus = _kgspConstructRpcObject(pGpu, pKernelGsp, + &pMQCollection->rpcQueues[RPC_TASK_ISR_QUEUE_IDX], + &pKernelGsp->pLocklessRpc); + if (nvStatus != NV_OK) + { + NV_PRINTF(LEVEL_ERROR, "init task ISR RPC infrastructure failed\n"); + goto done; + } + } - nvStatus = GspMsgQueueInit(pGpu, &pRpc->pMessageQueueInfo); +done: if (nvStatus != NV_OK) { - NV_PRINTF(LEVEL_ERROR, "GspMsgQueueInit failed\n"); _kgspFreeRpcInfrastructure(pGpu, pKernelGsp); - return nvStatus; } - pRpc->messageQueuePhysMem = pRpc->pMessageQueueInfo->sharedMemPA; - pRpc->message_buffer = (NvU32 *)pRpc->pMessageQueueInfo->pRpcMsgBuf; - pRpc->maxRpcSize = GSP_MSG_QUEUE_RPC_SIZE_MAX; - pRpc->init_msg_buf = (NvU32 *)pRpc->pMessageQueueInfo->pInitMsgBuf; - pRpc->init_msg_buf_pa = pRpc->pMessageQueueInfo->initMsgBufPA; + return nvStatus; +} - portMemSet(&pKernelGsp->gspStaticInfo, 0, - sizeof(pKernelGsp->gspStaticInfo)); - rpcSendMessage_FNPTR(pKernelGsp->pRpc) = _kgspRpcSendMessage; - rpcRecvPoll_FNPTR(pKernelGsp->pRpc) = _kgspRpcRecvPoll; +/*! + * Initialize stripped down version of RPC infra init for GSP clients. + */ +static NV_STATUS +_kgspConstructRpcObject +( + OBJGPU *pGpu, + KernelGsp *pKernelGsp, + MESSAGE_QUEUE_INFO *pMQI, + OBJRPC **ppRpc +) +{ + OBJRPC *pRpc; + + NV_ASSERT_OR_RETURN(pMQI != NULL, NV_ERR_INVALID_ARGUMENT); + + pRpc = initRpcObject(pGpu); + if (pRpc == NULL) + { + NV_PRINTF(LEVEL_ERROR, "initRpcObject failed\n"); + return NV_ERR_INSUFFICIENT_RESOURCES; + } + + pRpc->pMessageQueueInfo = pMQI; + + portMemSet(&pRpc->rpcHistory, 0, sizeof(pRpc->rpcHistory)); + pRpc->rpcHistoryCurrent = RPC_HISTORY_DEPTH - 1; + portMemSet(&pRpc->rpcEventHistory, 0, sizeof(pRpc->rpcEventHistory)); + pRpc->rpcEventHistoryCurrent = RPC_HISTORY_DEPTH - 1; + + pRpc->message_buffer = (NvU32 *)pRpc->pMessageQueueInfo->pRpcMsgBuf; + pRpc->maxRpcSize = GSP_MSG_QUEUE_RPC_SIZE_MAX; + + rpcSendMessage_FNPTR(pRpc) = _kgspRpcSendMessage; + rpcRecvPoll_FNPTR(pRpc) = _kgspRpcRecvPoll; + + *ppRpc = pRpc; return NV_OK; } @@ -1430,11 +1936,17 @@ { if (pKernelGsp->pRpc != NULL) { - GspMsgQueueCleanup(&pKernelGsp->pRpc->pMessageQueueInfo); rpcDestroy(pGpu, pKernelGsp->pRpc); portMemFree(pKernelGsp->pRpc); pKernelGsp->pRpc = NULL; } + if (pKernelGsp->pLocklessRpc != NULL) + { + rpcDestroy(pGpu, pKernelGsp->pLocklessRpc); + portMemFree(pKernelGsp->pLocklessRpc); + pKernelGsp->pLocklessRpc = NULL; + } + GspMsgQueuesCleanup(&pKernelGsp->pMQCollection); } /*! @@ -1745,8 +2257,7 @@ _kgspInitLibosLoggingStructures ( OBJGPU *pGpu, - KernelGsp *pKernelGsp, - GSP_FIRMWARE *pGspFw + KernelGsp *pKernelGsp ) { static const struct @@ -1773,6 +2284,7 @@ NV_STATUS nvStatus = NV_OK; NvU8 idx; + NvU64 flags = MEMDESC_FLAGS_NONE; pKernelGsp->pNvlogFlushMtx = portSyncMutexCreate(portMemAllocatorGetGlobalNonPaged()); if (pKernelGsp->pNvlogFlushMtx == NULL) @@ -1783,23 +2295,22 @@ libosLogCreate(&pKernelGsp->logDecode); + flags |= MEMDESC_FLAGS_ALLOC_IN_UNPROTECTED_MEMORY; + for (idx = 0; idx < LOGIDX_SIZE; idx++) { RM_LIBOS_LOG_MEM *pLog = &pKernelGsp->rmLibosLogMem[idx]; NvP64 pVa = NvP64_NULL; NvP64 pPriv = NvP64_NULL; - // // Setup logging memory for each task. - // Use MEMDESC_FLAGS_CPU_ONLY -- too early to call memdescMapIommu. - // NV_ASSERT_OK_OR_GOTO(nvStatus, memdescCreate(&pLog->pTaskLogDescriptor, pGpu, logInitValues[idx].size, RM_PAGE_SIZE, NV_TRUE, ADDR_SYSMEM, NV_MEMORY_CACHED, - MEMDESC_FLAGS_NONE), + flags), error_cleanup); NV_ASSERT_OK_OR_GOTO(nvStatus, @@ -1837,52 +2348,52 @@ logInitValues[idx].elfSectionName); } - // Setup symbol decoder - if (pGspFw->pLogElf) - { - const void *pLogData = NULL; - NvU64 logSize = 0; +error_cleanup: + if (nvStatus != NV_OK) + _kgspFreeLibosLoggingStructures(pGpu, pKernelGsp); - NV_ASSERT_OK_OR_GOTO( - nvStatus, - _kgspFwContainerVerifyVersion(pGpu, pKernelGsp, - pGspFw->pLogElf, - pGspFw->logElfSize, - "GSP firmware log"), - error_cleanup); + return nvStatus; +} - NV_ASSERT_OK_OR_GOTO( - nvStatus, - _kgspFwContainerGetSection(pGpu, pKernelGsp, - pGspFw->pLogElf, - pGspFw->logElfSize, - GSP_LOGGING_SECTION_NAME, - &pLogData, - &logSize), - error_cleanup); +static NV_STATUS +_kgspInitLibosLogDecoder +( + OBJGPU *pGpu, + KernelGsp *pKernelGsp, + GSP_FIRMWARE *pGspFw +) +{ + // If there's no log ELF or it's already been wired, skip wiring it now + if ((pGspFw->pLogElf == NULL) || (pKernelGsp->pLogElf != NULL)) + return NV_OK; - pKernelGsp->pLogElf = portMemAllocNonPaged(logSize); - pKernelGsp->logElfDataSize = logSize; + // Setup symbol decoder + const void *pLogData = NULL; + NvU64 logSize = 0; - if (pKernelGsp->pLogElf == NULL) - { - NV_PRINTF(LEVEL_ERROR, "Failed to allocate memory for log elf"); - nvStatus = NV_ERR_NO_MEMORY; - goto error_cleanup; - } - portMemCopy(pKernelGsp->pLogElf, logSize, pLogData, logSize); + NV_ASSERT_OK_OR_RETURN( + _kgspFwContainerVerifyVersion(pGpu, pKernelGsp, + pGspFw->pLogElf, + pGspFw->logElfSize, + "GSP firmware log")); - if (pKernelGsp->pLogElf) - { - libosLogInit(&pKernelGsp->logDecode, pKernelGsp->pLogElf, logSize); - } - } + NV_ASSERT_OK_OR_RETURN( + _kgspFwContainerGetSection(pGpu, pKernelGsp, + pGspFw->pLogElf, + pGspFw->logElfSize, + GSP_LOGGING_SECTION_NAME, + &pLogData, + &logSize)); -error_cleanup: - if (nvStatus != NV_OK) - _kgspFreeLibosLoggingStructures(pGpu, pKernelGsp); + pKernelGsp->pLogElf = portMemAllocNonPaged(logSize); + pKernelGsp->logElfDataSize = logSize; - return nvStatus; + NV_ASSERT_OR_RETURN(pKernelGsp->pLogElf != NULL, NV_ERR_NO_MEMORY); + + portMemCopy(pKernelGsp->pLogElf, logSize, pLogData, logSize); + libosLogInit(&pKernelGsp->logDecode, pKernelGsp->pLogElf, logSize); + + return NV_OK; } static NV_STATUS @@ -1969,19 +2480,31 @@ kgspConfigureFalcon_HAL(pGpu, pKernelGsp); + // Init RPC objects used to communicate with GSP. nvStatus = _kgspInitRpcInfrastructure(pGpu, pKernelGsp); if (nvStatus != NV_OK) { NV_PRINTF(LEVEL_ERROR, "init RPC infrastructure failed\n"); - return nvStatus; + goto done; } + // Init logging memory used by GSP + nvStatus = _kgspInitLibosLoggingStructures(pGpu, pKernelGsp); + if (nvStatus != NV_OK) + { + NV_PRINTF(LEVEL_ERROR, "init libos logging structures failed: 0x%x\n", nvStatus); + goto done; + } + + // Clear out the gspStaticInfo. We will populate this once GSP-RM is up. + portMemSet(&pKernelGsp->gspStaticInfo, 0, + sizeof(pKernelGsp->gspStaticInfo)); + nvStatus = kgspAllocBootArgs_HAL(pGpu, pKernelGsp); if (nvStatus != NV_OK) { NV_PRINTF(LEVEL_ERROR, "boot arg alloc failed: 0x%x\n", nvStatus); - _kgspFreeRpcInfrastructure(pGpu, pKernelGsp); - return nvStatus; + goto done; } if (IS_SIMULATION(pGpu)) @@ -1990,15 +2513,86 @@ if (nvStatus != NV_OK) { NV_PRINTF(LEVEL_ERROR, "sim access buffer alloc failed: 0x%x\n", nvStatus); - kgspFreeBootArgs_HAL(pGpu, pKernelGsp); - _kgspFreeRpcInfrastructure(pGpu, pKernelGsp); - return nvStatus; + goto done; } } +done: + if (nvStatus != NV_OK) + { + kgspFreeBootArgs_HAL(pGpu, pKernelGsp); + _kgspFreeLibosLoggingStructures(pGpu, pKernelGsp); + _kgspFreeRpcInfrastructure(pGpu, pKernelGsp); + } + + return nvStatus; +} + +/*! + * Convert VBIOS version containing Version and OemVersion packed together to + * a string representation. + * + * Example: + * for Version 0x05400001, OemVersion 0x12 + * input argument vbiosVersionCombined 0x0540000112 + * output str "5.40.00.01.12" + */ +static void +_kgspVbiosVersionToStr(NvU64 vbiosVersionCombined, char *pVbiosVersionStr, NvU32 size) +{ + nvDbgSnprintf(pVbiosVersionStr, size, "%2X.%02X.%02X.%02X.%02X", + (vbiosVersionCombined >> 32) & 0xff, + (vbiosVersionCombined >> 24) & 0xff, + (vbiosVersionCombined >> 16) & 0xff, + (vbiosVersionCombined >> 8) & 0xff, + (vbiosVersionCombined) & 0xff); +} + +static NV_STATUS +_kgspPrepareScrubberImageIfNeeded(OBJGPU *pGpu, KernelGsp *pKernelGsp) +{ + // Prepare Scrubber ucode image if pre-scrubbed memory is insufficient + NvU64 neededSize = pKernelGsp->pWprMeta->fbSize - pKernelGsp->pWprMeta->gspFwRsvdStart; + NvU64 prescrubbedSize = kgspGetPrescrubbedTopFbSize(pGpu, pKernelGsp); + NV_PRINTF(LEVEL_INFO, "pre-scrubbed memory: 0x%llx bytes, needed: 0x%llx bytes\n", + prescrubbedSize, neededSize); + + if (neededSize > prescrubbedSize) + NV_CHECK_OK_OR_RETURN(LEVEL_ERROR, + kgspAllocateScrubberUcodeImage(pGpu, pKernelGsp, &pKernelGsp->pScrubberUcode)); + return NV_OK; } +static NV_STATUS +_kgspBootGspRm(OBJGPU *pGpu, KernelGsp *pKernelGsp, GSP_FIRMWARE *pGspFw) +{ + NV_STATUS status; + + // Fail early if WPR2 is up + if (kgspIsWpr2Up_HAL(pGpu, pKernelGsp)) + { + NV_PRINTF(LEVEL_ERROR, "unexpected WPR2 already up, cannot proceed with booting GSP\n"); + NV_PRINTF(LEVEL_ERROR, "(the GPU is likely in a bad state and may need to be reset)\n"); + return NV_ERR_INVALID_STATE; + } + + // Calculate FB layout (requires knowing FB size which depends on GFW_BOOT) + NV_CHECK_OK_OR_RETURN(LEVEL_ERROR, kgspCalculateFbLayout_HAL(pGpu, pKernelGsp, pGspFw)); + + // If the new FB layout requires a scrubber ucode to scrub additional space, prepare it now + NV_CHECK_OK_OR_RETURN(LEVEL_ERROR, _kgspPrepareScrubberImageIfNeeded(pGpu, pKernelGsp)); + + // Proceed with GSP boot - if it fails, check for ECC errors + status = kgspBootstrapRiscvOSEarly_HAL(pGpu, pKernelGsp, pGspFw); + if ((status != NV_OK) && gpuCheckEccCounts_HAL(pGpu)) + status = NV_ERR_ECC_ERROR; + + pKernelGsp->bootAttempts++; + + return status; +} + /*! * Initialize GSP-RM * @@ -2038,9 +2632,6 @@ GPUS_LOCK_FLAGS_NONE, RM_LOCK_MODULES_INIT, &gpusLockedMask), done); - // Set the GPU time to the wall-clock time before loading GSP ucode. - tmrSetCurrentTime_HAL(pGpu, pTmr); - /* * For GSP-RM boot, we must trigger FRTS (if it exists for the chip) * before loading GSP-RM so that FRTS data and GSP-RM code/data/heap can coexist @@ -2052,29 +2643,38 @@ { KernelGspVbiosImg *pVbiosImg = NULL; + // Start VBIOS version string as "unknown" + portStringCopy(pKernelGsp->vbiosVersionStr, sizeof(pKernelGsp->vbiosVersionStr), "unknown", sizeof("unknown")); + // Try and extract a VBIOS image. status = kgspExtractVbiosFromRom_HAL(pGpu, pKernelGsp, &pVbiosImg); if (status == NV_OK) { + NvU64 vbiosVersionCombined = 0; + // Got a VBIOS image, now parse it for FWSEC. status = kgspParseFwsecUcodeFromVbiosImg(pGpu, pKernelGsp, pVbiosImg, - &pKernelGsp->pFwsecUcode); + &pKernelGsp->pFwsecUcode, &vbiosVersionCombined); kgspFreeVbiosImg(pVbiosImg); + + if (vbiosVersionCombined > 0) + { + _kgspVbiosVersionToStr(vbiosVersionCombined, pKernelGsp->vbiosVersionStr, sizeof(pKernelGsp->vbiosVersionStr)); + } + if (status != NV_OK) { - NV_PRINTF(LEVEL_ERROR, "failed to parse FWSEC ucode from VBIOS image: 0x%x\n", - status); + NV_PRINTF(LEVEL_ERROR, "failed to parse FWSEC ucode from VBIOS image (VBIOS version %s): 0x%x\n", + pKernelGsp->vbiosVersionStr, status); goto done; } + + NV_PRINTF(LEVEL_INFO, "parsed VBIOS version %s\n", pKernelGsp->vbiosVersionStr); } else if (status == NV_ERR_NOT_SUPPORTED) { - // // Extracting VBIOS image from ROM is not supported. - // Sanity check we don't depend on it for FRTS, and proceed without FWSEC. - // - NV_ASSERT_OR_GOTO(kgspGetFrtsSize(pGpu, pKernelGsp) == 0, done); status = NV_OK; } else @@ -2143,66 +2743,53 @@ goto done; } - NV_CHECK_OK_OR_GOTO(status, LEVEL_ERROR, kgspInitLogging(pGpu, pKernelGsp, pGspFw), done); + NV_CHECK_OK_OR_GOTO(status, LEVEL_ERROR, _kgspInitLibosLogDecoder(pGpu, pKernelGsp, pGspFw), done); // If live decoding is enabled, do not register flush callback to avoid racing with ioctl if (pKernelGsp->pLogElf == NULL) NV_CHECK_OK_OR_GOTO(status, LEVEL_ERROR, nvlogRegisterFlushCb(kgspNvlogFlushCb, pKernelGsp), done); - // Wait for GFW_BOOT OK status + // Reset thread state timeout and wait for GFW_BOOT OK status + threadStateResetTimeout(pGpu); NV_CHECK_OK_OR_GOTO(status, LEVEL_ERROR, kgspWaitForGfwBootOk_HAL(pGpu, pKernelGsp), done); - // Fail early if WPR2 is up - if (kgspIsWpr2Up_HAL(pGpu, pKernelGsp)) - { - NV_PRINTF(LEVEL_ERROR, "unexpected WPR2 already up, cannot proceed with booting gsp\n"); - NV_PRINTF(LEVEL_ERROR, "(the GPU is likely in a bad state and may need to be reset)\n"); - status = NV_ERR_INVALID_STATE; - goto done; - } - - // Calculate FB layout (requires knowing FB size which depends on GFW_BOOT) - status = kgspCalculateFbLayout_HAL(pGpu, pKernelGsp, pGspFw); - if (status != NV_OK) - { - NV_PRINTF(LEVEL_ERROR, "Error calculating FB layout\n"); - goto done; - } + // + // Set the GPU time to the wall-clock time after GFW boot is complete + // (to avoid PLM collisions) but before loading GSP-RM ucode (which + // consumes the updated GPU time). + // + tmrSetCurrentTime_HAL(pGpu, pTmr); - // Prepare Scrubber ucode image if pre-scrubbed memory is insufficient - if (pKernelGsp->pScrubberUcode == NULL) + // + // Bring up ucode with RM offload task. + // If an ECC error occurs which results in the failure of the bootstrap, try again. + // Subsequent attempts will shift the GSP region of FB in an attempt to avoid the + // unstable memory. + // + const NvU8 MAX_GSP_BOOT_ATTEMPTS = 4; + do { - NvU64 neededSize = pKernelGsp->pWprMeta->fbSize - pKernelGsp->pWprMeta->gspFwRsvdStart; - NvU64 prescrubbedSize = kgspGetPrescrubbedTopFbSize(pGpu, pKernelGsp); + // Reset the thread state timeout after failed attempts to prevent premature timeouts. + if (status != NV_OK) + threadStateResetTimeout(pGpu); - if (neededSize > prescrubbedSize) - { - NV_PRINTF(LEVEL_INFO, - "allocating Scrubber ucode as pre-scrubbed memory (0x%llx bytes) is insufficient (0x%llx bytes needed)\n", - prescrubbedSize, neededSize); - - status = kgspAllocateScrubberUcodeImage(pGpu, pKernelGsp, - &pKernelGsp->pScrubberUcode); - if (status != NV_OK) - { - NV_PRINTF(LEVEL_ERROR, "failed to allocate Scrubber ucode: 0x%x\n", status); - goto done; - } - } - else - { - NV_PRINTF(LEVEL_INFO, - "skipping allocating Scrubber ucode as pre-scrubbed memory (0x%llx bytes) is sufficient (0x%llx bytes needed)\n", - prescrubbedSize, neededSize); - } - } + // + // _kgspBootGspRm() will return NV_ERR_ECC_ERROR if any unhandled ECC errors are + // detected during a failed GSP boot attempt. Depending on where and when the + // error occurred, we may not be able to try again, in which case a different + // error code will be returned. + // + status = _kgspBootGspRm(pGpu, pKernelGsp, pGspFw); + } while ((status == NV_ERR_ECC_ERROR) && (pKernelGsp->bootAttempts < MAX_GSP_BOOT_ATTEMPTS)); - // bring up ucode with RM offload task - status = kgspBootstrapRiscvOSEarly_HAL(pGpu, pKernelGsp, pGspFw); if (status != NV_OK) { - NV_PRINTF(LEVEL_ERROR, "cannot bootstrap riscv/gsp: 0x%x\n", status); - kgspHealthCheck_HAL(pGpu, pKernelGsp); + // + // Ignore return value - a crash report may have already been consumed, + // this is just here as a last attempt to report boot issues that might + // have escaped prior checks. + // + (void)kgspHealthCheck_HAL(pGpu, pKernelGsp); goto done; } @@ -2248,26 +2835,6 @@ return status; } -NV_STATUS -kgspInitLogging_IMPL -( - OBJGPU *pGpu, - KernelGsp *pKernelGsp, - GSP_FIRMWARE *pGspFw -) -{ - NV_STATUS nvStatus; - - nvStatus = _kgspInitLibosLoggingStructures(pGpu, pKernelGsp, pGspFw); - if (nvStatus != NV_OK) - { - NV_PRINTF(LEVEL_ERROR, "init LIBOS logging structures failed: 0x%x\n", nvStatus); - return nvStatus; - } - - return nvStatus; -} - /*! * Unload GSP-RM */ @@ -2321,7 +2888,20 @@ else { // After instructing GSP-RM to unload itself, run Booter Unload to teardown WPR2 - status = kgspExecuteBooterUnloadIfNeeded_HAL(pGpu, pKernelGsp); + status = kgspExecuteBooterUnloadIfNeeded_HAL(pGpu, pKernelGsp, 0); + } + + // + // To fix boot issue after GPU reset on ESXi config: + // We still do not have root cause but looks like some sanity is failing during boot after reset is done. + // As temp WAR, add delay of 250 ms after gsp rm unload is done. + // Limit this to [VGPU-GSP] supported configs only and when we are in GPU RESET path. + // + if (API_GPU_IN_RESET_SANITY_CHECK(pGpu) && + gpuIsSriovEnabled(pGpu) && + IS_VGPU_GSP_PLUGIN_OFFLOAD_ENABLED(pGpu)) + { + osDelay(250); } if (rpcStatus != NV_OK) @@ -2346,6 +2926,9 @@ if (!IS_GSP_CLIENT(pGpu)) return; + // set VBIOS version string back to "unknown" + portStringCopy(pKernelGsp->vbiosVersionStr, sizeof(pKernelGsp->vbiosVersionStr), "unknown", sizeof("unknown")); + kgspFreeFlcnUcode(pKernelGsp->pFwsecUcode); pKernelGsp->pFwsecUcode = NULL; @@ -2355,12 +2938,17 @@ kgspFreeFlcnUcode(pKernelGsp->pBooterUnloadUcode); pKernelGsp->pBooterUnloadUcode = NULL; + kgspFreeFlcnUcode(pKernelGsp->pScrubberUcode); + pKernelGsp->pScrubberUcode = NULL; + kgspFreeBootArgs_HAL(pGpu, pKernelGsp); _kgspFreeLibosLoggingStructures(pGpu, pKernelGsp); _kgspFreeRpcInfrastructure(pGpu, pKernelGsp); _kgspFreeBootBinaryImage(pGpu, pKernelGsp); _kgspFreeSimAccessBuffer(pGpu, pKernelGsp); + + kgspFreeSuspendResumeData_HAL(pGpu, pKernelGsp); } void @@ -2425,14 +3013,24 @@ { GSP_ARGUMENTS_CACHED *pGspArgs = pKernelGsp->pGspArgumentsCached; MESSAGE_QUEUE_INIT_ARGUMENTS *pMQInitArgs = &pGspArgs->messageQueueInitArguments; - MESSAGE_QUEUE_INFO *pMQI = pKernelGsp->pRpc->pMessageQueueInfo; + MESSAGE_QUEUE_COLLECTION *pMQCollection = pKernelGsp->pMQCollection; GSP_SR_INIT_ARGUMENTS *pSrInitArgs = &pGspArgs->srInitArguments; // Setup the message queue arguments - pMQInitArgs->sharedMemPhysAddr = pKernelGsp->pRpc->messageQueuePhysMem; - pMQInitArgs->pageTableEntryCount = pMQI->pageTableEntryCount; - pMQInitArgs->cmdQueueOffset = pMQI->pageTableSize; - pMQInitArgs->statQueueOffset = pMQInitArgs->cmdQueueOffset + pMQI->commandQueueSize; + pMQInitArgs->sharedMemPhysAddr = pMQCollection->sharedMemPA; + pMQInitArgs->pageTableEntryCount = pMQCollection->pageTableEntryCount; + pMQInitArgs->cmdQueueOffset = pMQCollection->pageTableSize; + pMQInitArgs->statQueueOffset = pMQInitArgs->cmdQueueOffset + pMQCollection->rpcQueues[RPC_TASK_RM_QUEUE_IDX].commandQueueSize; + if (pKernelGsp->bIsTaskIsrQueueRequired) + { + pMQInitArgs->locklessCmdQueueOffset = pMQInitArgs->statQueueOffset + pMQCollection->rpcQueues[RPC_TASK_RM_QUEUE_IDX].statusQueueSize; + pMQInitArgs->locklessStatQueueOffset = pMQInitArgs->locklessCmdQueueOffset + pMQCollection->rpcQueues[RPC_TASK_ISR_QUEUE_IDX].commandQueueSize; + } + else + { + pMQInitArgs->locklessCmdQueueOffset = 0; + pMQInitArgs->locklessStatQueueOffset = 0; + } if (pGspInitArgs == NULL) { @@ -2448,6 +3046,15 @@ } pGspArgs->gpuInstance = pGpu->gpuInstance; + + portMemSet(&pGspArgs->profilerArgs, 0, sizeof(pGspArgs->profilerArgs)); + + if (pKernelGsp->pProfilerSamples != NULL && + pKernelGsp->pProfilerSamplesMD != NULL) + { + pGspArgs->profilerArgs.pa = memdescGetPhysAddr(pKernelGsp->pProfilerSamplesMD, AT_GPU, 0); + pGspArgs->profilerArgs.size = memdescGetSize(pKernelGsp->pProfilerSamplesMD); + } } /*! @@ -2471,6 +3078,7 @@ NvU8 *pDesc = NULL; NvP64 pVa = NvP64_NULL; NvP64 pPriv = NvP64_NULL; + NvU64 flags = MEMDESC_FLAGS_NONE; NV_ASSERT_OR_RETURN(pKernelGsp->pGspRmBootUcodeImage == NULL, NV_ERR_INVALID_STATE); NV_ASSERT_OR_RETURN(pKernelGsp->pGspRmBootUcodeDesc == NULL, NV_ERR_INVALID_STATE); @@ -2482,13 +3090,15 @@ bufSize = bindataGetBufferSize(pBinStorageImage); bufSizeAligned = NV_ALIGN_UP(bufSize, 0x1000); + flags |= MEMDESC_FLAGS_ALLOC_IN_UNPROTECTED_MEMORY; + NV_ASSERT_OK_OR_GOTO(status, memdescCreate(&pKernelGsp->pGspRmBootUcodeMemdesc, pGpu, bufSizeAligned, RM_PAGE_SIZE, NV_TRUE, ADDR_SYSMEM, NV_MEMORY_CACHED, - MEMDESC_FLAGS_NONE), + flags), fail); NV_ASSERT_OK_OR_GOTO(status, @@ -2574,12 +3184,15 @@ { NV_STATUS status = NV_OK; NvU8 *pSignatureVa = NULL; + NvU64 flags = MEMDESC_FLAGS_NONE; + + flags |= MEMDESC_FLAGS_ALLOC_IN_UNPROTECTED_MEMORY; // NOTE: align to 256 because that's the alignment needed for Booter DMA NV_CHECK_OK_OR_RETURN(LEVEL_ERROR, memdescCreate(&pKernelGsp->pSignatureMemdesc, pGpu, NV_ALIGN_UP(pGspFw->signatureSize, 256), 256, - NV_TRUE, ADDR_SYSMEM, NV_MEMORY_CACHED, MEMDESC_FLAGS_NONE)); + NV_TRUE, ADDR_SYSMEM, NV_MEMORY_CACHED, flags)); NV_CHECK_OK_OR_GOTO(status, LEVEL_ERROR, memdescAlloc(pKernelGsp->pSignatureMemdesc), fail_create); @@ -2755,16 +3368,17 @@ pGspFw)); NV_CHECK_OK_OR_RETURN(LEVEL_ERROR, - _kgspCreateRadix3(pGpu, &pKernelGsp->pGspUCodeRadix3Descriptor, + kgspCreateRadix3(pGpu, pKernelGsp, &pKernelGsp->pGspUCodeRadix3Descriptor, NULL, pGspFw->pImageData, pGspFw->imageSize)); return NV_OK; } -static NV_STATUS -_kgspCreateRadix3 +NV_STATUS +kgspCreateRadix3_IMPL ( OBJGPU *pGpu, + KernelGsp *pKernelGsp, MEMORY_DESCRIPTOR **ppMemdescRadix3, MEMORY_DESCRIPTOR *pMemdescData, const void *pData, @@ -2781,6 +3395,7 @@ NvU64 dataOffset = 0; NvU32 i; NV_STATUS status = NV_OK; + NvU64 flags = MEMDESC_FLAGS_KERNEL_MODE; // radix3 working array. struct @@ -2790,8 +3405,8 @@ } radix3[4]; NV_ASSERT_OR_RETURN(ppMemdescRadix3 != NULL, NV_ERR_INVALID_PARAMETER); - NV_ASSERT_OR_ELSE_STR((pMemdescData != NULL) != (pData != NULL), - "Specify pMemdescData or pData, but not both", + NV_ASSERT_OR_ELSE_STR(!((pMemdescData != NULL) && (pData != NULL)), + "Specify pMemdescData or pData, or none, but not both", return NV_ERR_INVALID_PARAMETER); // If the size is not specified, get it from the memory descriptor. @@ -2822,20 +3437,22 @@ ptSize = nPages << LIBOS_MEMORY_REGION_RADIX_PAGE_LOG2; allocSize = ptSize; - if (pData != NULL) + if (pMemdescData == NULL) { // We don't have a separate descriptor for the data. We need PTEs, // so include space for data in the new descriptor. allocSize += radix3[3].nPages << LIBOS_MEMORY_REGION_RADIX_PAGE_LOG2; } + flags |= MEMDESC_FLAGS_ALLOC_IN_UNPROTECTED_MEMORY; + NV_ASSERT_OK_OR_GOTO(status, memdescCreate(ppMemdescRadix3, pGpu, allocSize, LIBOS_MEMORY_REGION_RADIX_PAGE_SIZE, NV_MEMORY_NONCONTIGUOUS, ADDR_SYSMEM, NV_MEMORY_CACHED, - MEMDESC_FLAGS_KERNEL_MODE), + flags), done); NV_ASSERT_OK_OR_GOTO(status, memdescAlloc(*ppMemdescRadix3), error_ret); @@ -2869,10 +3486,10 @@ (RmPhysAddr *)(pRadix3Buf + radix3[i].offset)); // physical address table } + dataOffset = radix3[3].offset; + if (pData != NULL) { - dataOffset = radix3[3].offset; - // Optionally copy data into the radix3 buffer. portMemCopy(pRadix3Buf + dataOffset, size, pData, size); @@ -3082,7 +3699,7 @@ KernelGsp *pKernelGsp ) { - NV_STATUS nvStatus = NV_OK; + OBJRPC *pRpc = pKernelGsp->pRpc; // // Kernel RM can timeout when GSP-RM has an error condition. Give GSP-RM @@ -3091,16 +3708,22 @@ threadStateResetTimeout(pGpu); NV_CHECK_OK_OR_RETURN(LEVEL_ERROR, - rpcRecvPoll(pGpu, pKernelGsp->pRpc, NV_VGPU_MSG_EVENT_GSP_INIT_DONE)); + rpcRecvPoll(pGpu, pRpc, NV_VGPU_MSG_EVENT_GSP_INIT_DONE)); + + // + // Now check if RPC really succeeded (NV_VGPU_MSG_RESULT_* are defined to + // equivalent NV_STATUS codes in RM). + // + NV_ASSERT_OK_OR_RETURN(RPC_HDR->rpc_result); - // Now check if RPC really succeeded - NV_ASSERT_OK_OR_RETURN(((rpc_message_header_v *)pKernelGsp->pRpc->message_buffer)->rpc_result); - if (nvStatus != NV_VGPU_MSG_RESULT_SUCCESS) + pGpu->gspRmInitialized = NV_TRUE; + if (hypervisorIsVgxHyper() && pGpu->getProperty(pGpu, PDB_PROP_GPU_EXTENDED_GSP_RM_INITIALIZATION_TIMEOUT_FOR_VGX)) { - NV_ASSERT_OK_FAILED("nvStatus", nvStatus); + // Decrease timeout values for VGX driver + timeoutInitializeGpuDefault(&pGpu->timeoutData, pGpu); } - return nvStatus; + return NV_OK; } /*! @@ -3221,6 +3844,31 @@ break; } + case GSP_SEQ_BUF_OPCODE_CORE_RESET: + { + NV_ASSERT_OR_RETURN(payloadSize == 0, NV_ERR_INVALID_ARGUMENT); + + kflcnReset_HAL(pGpu, staticCast(pKernelGsp, KernelFalcon)); + kflcnDisableCtxReq_HAL(pGpu, staticCast(pKernelGsp, KernelFalcon)); + break; + } + + case GSP_SEQ_BUF_OPCODE_CORE_START: + { + NV_ASSERT_OR_RETURN(payloadSize == 0, NV_ERR_INVALID_ARGUMENT); + + kflcnStartCpu_HAL(pGpu, staticCast(pKernelGsp, KernelFalcon)); + break; + } + + case GSP_SEQ_BUF_OPCODE_CORE_WAIT_FOR_HALT: + { + NV_ASSERT_OR_RETURN(payloadSize == 0, NV_ERR_INVALID_ARGUMENT); + + NV_ASSERT_OK_OR_RETURN(kflcnWaitForHalt_HAL(pGpu, staticCast(pKernelGsp, KernelFalcon), GPU_TIMEOUT_DEFAULT, 0)); + break; + } + default: // // Route this command to the arch-specific handler. @@ -3341,3 +3989,177 @@ return kgspService_HAL(pGpu, pKernelGsp); } + +/*! + * Calculates the GSP FW heap size based on the GPU's resources. + */ +static NvU64 +_kgspCalculateFwHeapSize +( + OBJGPU *pGpu, + KernelGsp *pKernelGsp, + NvU32 maxGspFwHeapSizeMB +) +{ + // For VGPU, use the static pre-calculated size + if (pGpu->bVgpuGspPluginOffloadEnabled) + return GSP_FW_HEAP_SIZE_VGPU_DEFAULT; + + // + // The baremetal heap calculation is a function of the architecture, FB + // size, and a chunk for backing client allocations (pre-calibrated for the + // architecture through rough profiling). + // + KernelMemorySystem *pKernelMemorySystem = GPU_GET_KERNEL_MEMORY_SYSTEM(pGpu); + NvU64 fbSize = 0; + + NV_ASSERT_OK(kmemsysGetUsableFbSize_HAL(pGpu, pKernelMemorySystem, &fbSize)); + const NvU32 fbSizeGB = (NvU32)(NV_ALIGN_UP64(fbSize, 1 << 30) >> 30); + + // + // Reclaimable binary data will end up padding the heap (in some cases, + // significantly), but due to memory fragmentation we can't rely on it to + // linearly reduce the amount needed in the primary heap, so it is not a + // factor here. Instead, it's just extra margin to keep us from exhausting + // the heap at runtime. + // + NvU64 heapSize = pKernelGsp->fwHeapParamOsCarveoutSize + + pKernelGsp->fwHeapParamBaseSize + + NV_ALIGN_UP(GSP_FW_HEAP_PARAM_SIZE_PER_GB_FB * fbSizeGB, 1 << 20) + + NV_ALIGN_UP(GSP_FW_HEAP_PARAM_CLIENT_ALLOC_SIZE, 1 << 20); + + // Clamp to the minimum, even if the calculations say we can do with less + const NvU32 minGspFwHeapSizeMB = kgspGetMinWprHeapSizeMB_HAL(pGpu, pKernelGsp); + heapSize = NV_MAX(heapSize, (NvU64)minGspFwHeapSizeMB << 20); + + // Clamp to the maximum heap size, if necessary + heapSize = NV_MIN(heapSize, (NvU64)maxGspFwHeapSizeMB << 20); + + NV_PRINTF(LEVEL_INFO, "GSP FW heap %lluMB of %uGB\n", + heapSize >> 20, fbSizeGB); + + return heapSize; +} + +/*! + * Returns the size in bytes of the GSP FW heap: + * - the registry override, if present + * - otherwise, calculate the FW heap size for this GPU, limiting it to stay + * within the pre-scrubbed area at the end of FB, if needed + * + * @param[in] posteriorFbSize - size in bytes of the memory reserved between the + * end of the GSP FW heap and the end of FB, or 0 + * to disable limiting of the heap range to within + * the pre-scrubbed area at the end of FB + */ +NvU64 +kgspGetFwHeapSize_IMPL +( + OBJGPU *pGpu, + KernelGsp *pKernelGsp, + NvU64 posteriorFbSize +) +{ + NvU32 maxScrubbedHeapSizeMB = NV_U32_MAX; + NvU32 heapSizeMB = 0; + + // + // The pre-scrubbed region at the end of FB may limit the heap size, if no + // scrubber ucode is supported to unlock the rest of memory prior to booting + // GSP-RM. + // + if (!pKernelGsp->bScrubberUcodeSupported && (posteriorFbSize != 0)) + { + const NvU64 prescrubbedSize = kgspGetPrescrubbedTopFbSize(pGpu, pKernelGsp); + if (prescrubbedSize < NV_U64_MAX) + maxScrubbedHeapSizeMB = (NvU32)((prescrubbedSize - posteriorFbSize) >> 20); + } + + // Get the heap size override from the registry, if any + if ((osReadRegistryDword(pGpu, NV_REG_STR_GSP_FIRMWARE_HEAP_SIZE_MB, &heapSizeMB) == NV_OK) && + (heapSizeMB != NV_REG_STR_GSP_FIRMWARE_HEAP_SIZE_MB_DEFAULT)) + { + const NvU32 minGspFwHeapSizeMB = kgspGetMinWprHeapSizeMB_HAL(pGpu, pKernelGsp); + const NvU32 maxGspFwHeapSizeMB = NV_MIN(kgspGetMaxWprHeapSizeMB_HAL(pGpu, pKernelGsp), + maxScrubbedHeapSizeMB); + + NV_ASSERT(minGspFwHeapSizeMB < maxGspFwHeapSizeMB); + + if (heapSizeMB > maxGspFwHeapSizeMB) + { + NV_PRINTF(LEVEL_WARNING, "Firmware heap size clamped to maximum (%uMB)\n", + maxGspFwHeapSizeMB); + heapSizeMB = maxGspFwHeapSizeMB; + } + else if (heapSizeMB < minGspFwHeapSizeMB) + { + NV_PRINTF(LEVEL_WARNING, "Firmware heap size clamped to minimum (%uMB)\n", + minGspFwHeapSizeMB); + heapSizeMB = minGspFwHeapSizeMB; + } + else + { + NV_PRINTF(LEVEL_WARNING, "Firmware heap size overridden (%uMB)\n", + heapSizeMB); + } + + return ((NvU64)heapSizeMB) << 20; + } + + return _kgspCalculateFwHeapSize(pGpu, pKernelGsp, maxScrubbedHeapSizeMB); +} + +NvU64 kgspGetWprEndMargin_IMPL(OBJGPU *pGpu, KernelGsp *pKernelGsp) +{ + NvU64 wprEndMargin; + NvU32 marginOverride = 0; + GspFwWprMeta *pWprMeta = pKernelGsp->pWprMeta; + + (void)osReadRegistryDword(pGpu, NV_REG_STR_RM_GSP_WPR_END_MARGIN, &marginOverride); + + wprEndMargin = ((NvU64)DRF_VAL(_REG, _RM_GSP_WPR_END_MARGIN, _MB, marginOverride)) << 20; + if (wprEndMargin == 0) + { + // Calculate the default margin size based on the WPR size + const GspFwWprMeta *pWprMeta = pKernelGsp->pWprMeta; + + // + // This needs to be called after pWprMeta->sizeOfRadix3Elf has been initialized, + // in order to estimate the default WPR size. + // + NV_ASSERT(pWprMeta->sizeOfRadix3Elf > 0); + + // + // If the bounds are encoded in GspFwWprMeta from a prior attempt, use them. + // Otherwise, estimate the WPR size by the sizes of the elements in the layout + // + if (pWprMeta->gspFwWprEnd > pWprMeta->nonWprHeapOffset) + { + wprEndMargin = pWprMeta->gspFwWprEnd - pWprMeta->nonWprHeapOffset; + } + else + { + wprEndMargin += kgspGetFrtsSize_HAL(pGpu, pKernelGsp); + wprEndMargin += pKernelGsp->gspRmBootUcodeSize; + wprEndMargin += pWprMeta->sizeOfRadix3Elf; + wprEndMargin += kgspGetFwHeapSize(pGpu, pKernelGsp, 0); + wprEndMargin += kgspGetNonWprHeapSize(pGpu, pKernelGsp); + } + + if (pKernelGsp->bootAttempts > 0) + wprEndMargin *= pKernelGsp->bootAttempts; + } + + if (FLD_TEST_DRF(_REG, _RM_GSP_WPR_END_MARGIN, _APPLY, _ALWAYS, marginOverride) || + (pKernelGsp->bootAttempts > 0)) + { + NV_PRINTF(LEVEL_WARNING, "Adding margin of 0x%llx bytes after the end of WPR2\n", + wprEndMargin); + pWprMeta->flags |= GSP_FW_FLAGS_RECOVERY_MARGIN_PRESENT; + return wprEndMargin; + } + + // Normal boot path + pWprMeta->flags &= ~GSP_FW_FLAGS_RECOVERY_MARGIN_PRESENT; + return 0; +} diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/kernel/gpu/gsp/kernel_gsp_fwsec.c nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/kernel/gpu/gsp/kernel_gsp_fwsec.c --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/kernel/gpu/gsp/kernel_gsp_fwsec.c 2023-10-25 20:21:06.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/kernel/gpu/gsp/kernel_gsp_fwsec.c 2024-03-05 22:13:30.000000000 +0000 @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 2021-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2021-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -67,6 +67,18 @@ #define BIT_TOKEN_V1_00_FMT "2b2w" typedef struct BIT_TOKEN_V1_00 BIT_TOKEN_V1_00; +#define BIT_TOKEN_BIOSDATA 0x42 + +// structure for only version info from BIT_DATA_BIOSDATA_V1 and BIT_DATA_BIOSDATA_V2 +typedef struct +{ + bios_U032 Version; // BIOS Binary Version Ex. 5.40.00.01.12 = 0x05400001 + bios_U008 OemVersion; // OEM Version Number Ex. 5.40.00.01.12 = 0x12 +} BIT_DATA_BIOSDATA_BINVER; + +#define BIT_DATA_BIOSDATA_BINVER_FMT "1d1b" +#define BIT_DATA_BIOSDATA_BINVER_SIZE_5 5 + #define BIT_TOKEN_FALCON_DATA 0x70 typedef struct @@ -441,6 +453,7 @@ * @param[in] bitAddr Offset of BIT header within VBIOS image * @param[in] bUseDebugFwsec Whether to look for debug or prod FWSEC * @param[out] pFwsecUcodeDescFromBit Resulting ucode desc + * @param[out] pVbiosVersionCombined (optional) output VBIOS version */ static NV_STATUS s_vbiosParseFwsecUcodeDescFromBit @@ -448,7 +461,8 @@ const KernelGspVbiosImg * const pVbiosImg, const NvU32 bitAddr, const NvBool bUseDebugFwsec, - FlcnUcodeDescFromBit *pFwsecUcodeDescFromBit // out + FlcnUcodeDescFromBit *pFwsecUcodeDescFromBit, // out + NvU64 *pVbiosVersionCombined // out ) { @@ -491,6 +505,26 @@ continue; } + // catch BIOSDATA token (for capturing VBIOS version) + if (pVbiosVersionCombined != NULL && + bitToken.TokenId == BIT_TOKEN_BIOSDATA && + ((bitToken.DataVersion == 1) || (bitToken.DataVersion == 2)) && + bitToken.DataSize > BIT_DATA_BIOSDATA_BINVER_SIZE_5) + { + BIT_DATA_BIOSDATA_BINVER binver; + status = s_vbiosReadStructure(pVbiosImg, &binver, + bitToken.DataPtr, BIT_DATA_BIOSDATA_BINVER_FMT); + if (status != NV_OK) + { + NV_PRINTF(LEVEL_ERROR, + "failed to read BIOSDATA (BIT token %u), skipping: 0x%x\n", + tokIdx, status); + continue; + } + + *pVbiosVersionCombined = (((NvU64) binver.Version) << 8) | ((NvU32) binver.OemVersion); + } + // skip tokens that are not for falcon ucode data v2 if (bitToken.TokenId != BIT_TOKEN_FALCON_DATA || bitToken.DataVersion != 2 || @@ -1037,10 +1071,11 @@ * The resulting KernelGspFlcnUcode should be freed with kgspFlcnUcodeFree * after use. * - * @param[in] pGpu OBJGPU pointer - * @param[in] pKernelGsp KernelGsp pointer - * @param[in] pVbiosImg VBIOS image - * @param[out] ppFwsecUcode Pointer to resulting KernelGspFlcnUcode + * @param[in] pGpu OBJGPU pointer + * @param[in] pKernelGsp KernelGsp pointer + * @param[in] pVbiosImg VBIOS image + * @param[out] ppFwsecUcode Pointer to resulting KernelGspFlcnUcode + * @param[out] pVbiosVersionCombined (optional) pointer to output VBIOS version */ NV_STATUS kgspParseFwsecUcodeFromVbiosImg_IMPL @@ -1048,7 +1083,8 @@ OBJGPU *pGpu, KernelGsp *pKernelGsp, const KernelGspVbiosImg * const pVbiosImg, - KernelGspFlcnUcode **ppFwsecUcode // out + KernelGspFlcnUcode **ppFwsecUcode, // out + NvU64 *pVbiosVersionCombined // out ) { NV_STATUS status; @@ -1072,7 +1108,8 @@ } bUseDebugFwsec = kgspIsDebugModeEnabled_HAL(pGpu, pKernelGsp); - status = s_vbiosParseFwsecUcodeDescFromBit(pVbiosImg, bitAddr, bUseDebugFwsec, &fwsecUcodeDescFromBit); + status = s_vbiosParseFwsecUcodeDescFromBit(pVbiosImg, bitAddr, bUseDebugFwsec, + &fwsecUcodeDescFromBit, pVbiosVersionCombined); if (status != NV_OK) { NV_PRINTF(LEVEL_ERROR, "failed to parse FWSEC ucode desc from VBIOS image: 0x%x\n", status); diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/kernel/gpu/gsp/message_queue_cpu.c nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/kernel/gpu/gsp/message_queue_cpu.c --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/kernel/gpu/gsp/message_queue_cpu.c 2023-10-25 20:21:06.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/kernel/gpu/gsp/message_queue_cpu.c 2024-03-05 22:13:31.000000000 +0000 @@ -51,25 +51,33 @@ #include "msgq/msgq_priv.h" #include "gpu/gsp/kernel_gsp.h" #include "nvrm_registry.h" +#include "gpu/conf_compute/ccsl.h" +#include "gpu/conf_compute/conf_compute.h" ct_assert(GSP_MSG_QUEUE_HEADER_SIZE > sizeof(msgqTxHeader) + sizeof(msgqRxHeader)); +static void _gspMsgQueueCleanup(MESSAGE_QUEUE_INFO *pMQI); + static void _getMsgQueueParams ( OBJGPU *pGpu, - MESSAGE_QUEUE_INFO *pMQI + MESSAGE_QUEUE_COLLECTION *pMQCollection ) { + KernelGsp *pKernelGsp = GPU_GET_KERNEL_GSP(pGpu); NvLength queueSize; + MESSAGE_QUEUE_INFO *pRmQueueInfo = &pMQCollection->rpcQueues[RPC_TASK_RM_QUEUE_IDX]; + MESSAGE_QUEUE_INFO *pTaskIsrQueueInfo = &pMQCollection->rpcQueues[RPC_TASK_ISR_QUEUE_IDX]; NvU32 numPtes; const NvLength defaultCommandQueueSize = 0x40000; // 256 KB const NvLength defaultStatusQueueSize = 0x40000; // 256 KB NvU32 regStatusQueueSize; + // RmQueue sizes if (IS_SILICON(pGpu)) { - pMQI->commandQueueSize = defaultCommandQueueSize; + pRmQueueInfo->commandQueueSize = defaultCommandQueueSize; } else { @@ -77,7 +85,7 @@ // Pre-silicon platforms need a large command queue in order to send // the VBIOS image via RPC. // - pMQI->commandQueueSize = defaultCommandQueueSize * 6; + pRmQueueInfo->commandQueueSize = defaultCommandQueueSize * 6; } // Check for status queue size overried @@ -86,18 +94,31 @@ regStatusQueueSize *= 1024; // to bytes regStatusQueueSize = NV_MAX(GSP_MSG_QUEUE_ELEMENT_SIZE_MAX, regStatusQueueSize); regStatusQueueSize = NV_ALIGN_UP(regStatusQueueSize, 1 << GSP_MSG_QUEUE_ALIGN); - pMQI->statusQueueSize = regStatusQueueSize; + pRmQueueInfo->statusQueueSize = regStatusQueueSize; } else { - pMQI->statusQueueSize = defaultStatusQueueSize; + pRmQueueInfo->statusQueueSize = defaultStatusQueueSize; + } + + // TaskIsrQueue sizes + if (pKernelGsp->bIsTaskIsrQueueRequired) + { + pTaskIsrQueueInfo->commandQueueSize = defaultCommandQueueSize; + pTaskIsrQueueInfo->statusQueueSize = defaultStatusQueueSize; + } + else + { + pTaskIsrQueueInfo->commandQueueSize = 0; + pTaskIsrQueueInfo->statusQueueSize = 0; } // // Calculate the number of entries required to map both queues in addition // to the page table itself. // - queueSize = pMQI->commandQueueSize + pMQI->statusQueueSize; + queueSize = pRmQueueInfo->commandQueueSize + pRmQueueInfo->statusQueueSize + + pTaskIsrQueueInfo->commandQueueSize + pTaskIsrQueueInfo->statusQueueSize; NV_ASSERT((queueSize & RM_PAGE_MASK) == 0); numPtes = (queueSize >> RM_PAGE_SHIFT); @@ -108,78 +129,146 @@ // Align the page table size to RM_PAGE_SIZE, so that the command queue is // aligned. // - pMQI->pageTableSize = RM_PAGE_ALIGN_UP(numPtes * sizeof(RmPhysAddr)); - pMQI->pageTableEntryCount = numPtes; + pMQCollection->pageTableSize = RM_PAGE_ALIGN_UP(numPtes * sizeof(RmPhysAddr)); + pMQCollection->pageTableEntryCount = numPtes; +} + +static NV_STATUS +_gspMsgQueueInit +( + MESSAGE_QUEUE_INFO *pMQI +) +{ + NvU32 workAreaSize; + NV_STATUS nvStatus = NV_OK; + int nRet; + + // Allocate work area. + workAreaSize = (1 << GSP_MSG_QUEUE_ELEMENT_ALIGN) + + GSP_MSG_QUEUE_ELEMENT_SIZE_MAX + msgqGetMetaSize(); + pMQI->pWorkArea = portMemAllocNonPaged(workAreaSize); + if (pMQI->pWorkArea == NULL) + { + NV_PRINTF(LEVEL_ERROR, "Error allocating pWorkArea.\n"); + return NV_ERR_NO_MEMORY; + } + + portMemSet(pMQI->pWorkArea, 0, workAreaSize); + + pMQI->pCmdQueueElement = (GSP_MSG_QUEUE_ELEMENT *) + NV_ALIGN_UP((NvUPtr)pMQI->pWorkArea, 1 << GSP_MSG_QUEUE_ELEMENT_ALIGN); + pMQI->pMetaData = (void *)((NvUPtr)pMQI->pCmdQueueElement + GSP_MSG_QUEUE_ELEMENT_SIZE_MAX); + + nRet = msgqInit(&pMQI->hQueue, pMQI->pMetaData); + if (nRet < 0) + { + NV_PRINTF(LEVEL_ERROR, "msgqInit failed: %d\n", nRet); + nvStatus = NV_ERR_GENERIC; + goto error_ret; + } + + nRet = msgqTxCreate(pMQI->hQueue, + pMQI->pCommandQueue, + pMQI->commandQueueSize, + GSP_MSG_QUEUE_ELEMENT_SIZE_MIN, + GSP_MSG_QUEUE_HEADER_ALIGN, + GSP_MSG_QUEUE_ELEMENT_ALIGN, + MSGQ_FLAGS_SWAP_RX); + if (nRet < 0) + { + NV_PRINTF(LEVEL_ERROR, "msgqTxCreate failed: %d\n", nRet); + nvStatus = NV_ERR_GENERIC; + goto error_ret; + } + + pMQI->pRpcMsgBuf = &pMQI->pCmdQueueElement->rpc; + + NV_PRINTF(LEVEL_INFO, "Created command queue.\n"); + return nvStatus; + +error_ret: + _gspMsgQueueCleanup(pMQI); + return nvStatus; } /*! * GspMsgQueueInit * - * Initialize the command queue for CPU side. + * Initialize the command queues for CPU side. * Must not be called before portInitialize. */ NV_STATUS -GspMsgQueueInit +GspMsgQueuesInit ( - OBJGPU *pGpu, - MESSAGE_QUEUE_INFO **ppMQI + OBJGPU *pGpu, + MESSAGE_QUEUE_COLLECTION **ppMQCollection ) { - MESSAGE_QUEUE_INFO *pMQI = NULL; + KernelGsp *pKernelGsp = GPU_GET_KERNEL_GSP(pGpu); + MESSAGE_QUEUE_COLLECTION *pMQCollection = NULL; + MESSAGE_QUEUE_INFO *pRmQueueInfo = NULL; + MESSAGE_QUEUE_INFO *pTaskIsrQueueInfo = NULL; RmPhysAddr *pPageTbl; - int nRet; NvP64 pVaKernel; NvP64 pPrivKernel; NV_STATUS nvStatus = NV_OK; NvLength sharedBufSize; - NvLength firstCmdOffset; - NvU32 workAreaSize; + NvP64 lastQueueVa; + NvLength lastQueueSize; + NvU64 flags = MEMDESC_FLAGS_NONE; - if (*ppMQI != NULL) + if (*ppMQCollection != NULL) { NV_PRINTF(LEVEL_ERROR, "GSP message queue was already initialized.\n"); return NV_ERR_INVALID_STATE; } - pMQI = portMemAllocNonPaged(sizeof *pMQI); - if (pMQI == NULL) + pMQCollection = portMemAllocNonPaged(sizeof *pMQCollection); + if (pMQCollection == NULL) { NV_PRINTF(LEVEL_ERROR, "Error allocating queue info area.\n"); nvStatus = NV_ERR_NO_MEMORY; goto done; } - portMemSet(pMQI, 0, sizeof *pMQI); + portMemSet(pMQCollection, 0, sizeof *pMQCollection); + + _getMsgQueueParams(pGpu, pMQCollection); + + pRmQueueInfo = &pMQCollection->rpcQueues[RPC_TASK_RM_QUEUE_IDX]; + pTaskIsrQueueInfo = &pMQCollection->rpcQueues[RPC_TASK_ISR_QUEUE_IDX]; - _getMsgQueueParams(pGpu, pMQI); + sharedBufSize = pMQCollection->pageTableSize + + pRmQueueInfo->commandQueueSize + + pRmQueueInfo->statusQueueSize + + pTaskIsrQueueInfo->commandQueueSize + + pTaskIsrQueueInfo->statusQueueSize; - sharedBufSize = pMQI->pageTableSize + - pMQI->commandQueueSize + - pMQI->statusQueueSize; + flags |= MEMDESC_FLAGS_ALLOC_IN_UNPROTECTED_MEMORY; // // For now, put all shared queue memory in one block. // NV_ASSERT_OK_OR_GOTO(nvStatus, - memdescCreate(&pMQI->pSharedMemDesc, pGpu, sharedBufSize, + memdescCreate(&pMQCollection->pSharedMemDesc, pGpu, sharedBufSize, RM_PAGE_SIZE, NV_MEMORY_NONCONTIGUOUS, ADDR_SYSMEM, NV_MEMORY_CACHED, - MEMDESC_FLAGS_NONE), + flags), done); - memdescSetFlag(pMQI->pSharedMemDesc, MEMDESC_FLAGS_KERNEL_MODE, NV_TRUE); + memdescSetFlag(pMQCollection->pSharedMemDesc, MEMDESC_FLAGS_KERNEL_MODE, NV_TRUE); NV_ASSERT_OK_OR_GOTO(nvStatus, - memdescAlloc(pMQI->pSharedMemDesc), + memdescAlloc(pMQCollection->pSharedMemDesc), error_ret); // Create kernel mapping for command queue. NV_ASSERT_OK_OR_GOTO(nvStatus, - memdescMap(pMQI->pSharedMemDesc, 0, sharedBufSize, + memdescMap(pMQCollection->pSharedMemDesc, 0, sharedBufSize, NV_TRUE, NV_PROTECT_WRITEABLE, &pVaKernel, &pPrivKernel), error_ret); - memdescSetKernelMapping(pMQI->pSharedMemDesc, pVaKernel); - memdescSetKernelMappingPriv(pMQI->pSharedMemDesc, pPrivKernel); + memdescSetKernelMapping(pMQCollection->pSharedMemDesc, pVaKernel); + memdescSetKernelMappingPriv(pMQCollection->pSharedMemDesc, pPrivKernel); if (pVaKernel == NvP64_NULL) { @@ -196,81 +285,63 @@ // // Each of the following are page aligned: // Shared memory layout header (includes page table) - // Command queue header - // Command queue entries - // Status queue header - // Status queue entries - memdescGetPhysAddrs(pMQI->pSharedMemDesc, + // RM Command queue header + // RM Command queue entries + // RM Status queue header + // RM Status queue entries + // TASKISR Command queue header + // TASKISR Command queue entries + // TASKISR Status queue header + // TASKISR Status queue entries + memdescGetPhysAddrs(pMQCollection->pSharedMemDesc, AT_GPU, // addressTranslation 0, // offset RM_PAGE_SIZE, // stride - pMQI->pageTableEntryCount, // count + pMQCollection->pageTableEntryCount, // count pPageTbl); // physical address table - pMQI->pCommandQueue = NvP64_VALUE( - NvP64_PLUS_OFFSET(pVaKernel, pMQI->pageTableSize)); + pRmQueueInfo->pCommandQueue = NvP64_VALUE( + NvP64_PLUS_OFFSET(pVaKernel, pMQCollection->pageTableSize)); - pMQI->pStatusQueue = NvP64_VALUE( - NvP64_PLUS_OFFSET(NV_PTR_TO_NvP64(pMQI->pCommandQueue), pMQI->commandQueueSize)); - - NV_ASSERT(NvP64_PLUS_OFFSET(pVaKernel, sharedBufSize) == - NvP64_PLUS_OFFSET(NV_PTR_TO_NvP64(pMQI->pStatusQueue), pMQI->statusQueueSize)); + pRmQueueInfo->pStatusQueue = NvP64_VALUE( + NvP64_PLUS_OFFSET(NV_PTR_TO_NvP64(pRmQueueInfo->pCommandQueue), pRmQueueInfo->commandQueueSize)); - // Allocate work area. - workAreaSize = (1 << GSP_MSG_QUEUE_ELEMENT_ALIGN) + - GSP_MSG_QUEUE_ELEMENT_SIZE_MAX + msgqGetMetaSize(); - pMQI->pWorkArea = portMemAllocNonPaged(workAreaSize); + lastQueueVa = NV_PTR_TO_NvP64(pRmQueueInfo->pStatusQueue); + lastQueueSize = pRmQueueInfo->statusQueueSize; - if (pMQI->pWorkArea == NULL) + if (pKernelGsp->bIsTaskIsrQueueRequired) { - NV_PRINTF(LEVEL_ERROR, "Error allocating pWorkArea.\n"); - nvStatus = NV_ERR_NO_MEMORY; - goto error_ret; - } - - portMemSet(pMQI->pWorkArea, 0, workAreaSize); + pTaskIsrQueueInfo->pCommandQueue = NvP64_VALUE( + NvP64_PLUS_OFFSET(NV_PTR_TO_NvP64(pRmQueueInfo->pStatusQueue), pRmQueueInfo->statusQueueSize)); - pMQI->pCmdQueueElement = (GSP_MSG_QUEUE_ELEMENT *) - NV_ALIGN_UP((NvUPtr)pMQI->pWorkArea, 1 << GSP_MSG_QUEUE_ELEMENT_ALIGN); - pMQI->pMetaData = (void *)((NvUPtr)pMQI->pCmdQueueElement + GSP_MSG_QUEUE_ELEMENT_SIZE_MAX); + pTaskIsrQueueInfo->pStatusQueue = NvP64_VALUE( + NvP64_PLUS_OFFSET(NV_PTR_TO_NvP64(pTaskIsrQueueInfo->pCommandQueue), pTaskIsrQueueInfo->commandQueueSize)); - nRet = msgqInit(&pMQI->hQueue, pMQI->pMetaData); - if (nRet < 0) - { - NV_PRINTF(LEVEL_ERROR, "msgqInit failed: %d\n", nRet); - nvStatus = NV_ERR_GENERIC; - goto error_ret; + lastQueueVa = NV_PTR_TO_NvP64(pTaskIsrQueueInfo->pStatusQueue); + lastQueueSize = pTaskIsrQueueInfo->statusQueueSize; } - nRet = msgqTxCreate(pMQI->hQueue, - pMQI->pCommandQueue, - pMQI->commandQueueSize, - GSP_MSG_QUEUE_ELEMENT_SIZE_MIN, - GSP_MSG_QUEUE_HEADER_ALIGN, - GSP_MSG_QUEUE_ELEMENT_ALIGN, - MSGQ_FLAGS_SWAP_RX); - if (nRet < 0) + // Assert that the last queue offset + size fits into the shared memory. + NV_ASSERT(NvP64_PLUS_OFFSET(pVaKernel, sharedBufSize) == + NvP64_PLUS_OFFSET(lastQueueVa, lastQueueSize)); + + NV_ASSERT_OK_OR_GOTO(nvStatus, _gspMsgQueueInit(pRmQueueInfo), error_ret); + pRmQueueInfo->queueIdx = RPC_TASK_RM_QUEUE_IDX; + + if (pKernelGsp->bIsTaskIsrQueueRequired) { - NV_PRINTF(LEVEL_ERROR, "msgqTxCreate failed: %d\n", nRet); - nvStatus = NV_ERR_GENERIC; - goto error_ret; + NV_ASSERT_OK_OR_GOTO(nvStatus, _gspMsgQueueInit(pTaskIsrQueueInfo), error_ret); + pTaskIsrQueueInfo->queueIdx = RPC_TASK_ISR_QUEUE_IDX; } - NV_PRINTF(LEVEL_INFO, "Created command queue.\n"); - - *ppMQI = pMQI; - pMQI->sharedMemPA = pPageTbl[0]; - pMQI->pRpcMsgBuf = &pMQI->pCmdQueueElement->rpc; + *ppMQCollection = pMQCollection; + pMQCollection->sharedMemPA = pPageTbl[0]; - firstCmdOffset = pMQI->pageTableSize + GSP_MSG_QUEUE_HEADER_SIZE; - pMQI->pInitMsgBuf = NvP64_PLUS_OFFSET(pVaKernel, firstCmdOffset); - pMQI->initMsgBufPA = pPageTbl[firstCmdOffset >> RM_PAGE_SHIFT] + - (firstCmdOffset & RM_PAGE_MASK); done: return nvStatus; error_ret: - GspMsgQueueCleanup(&pMQI); + GspMsgQueuesCleanup(&pMQCollection); return nvStatus; } @@ -334,6 +405,11 @@ break; kgspDumpGspLogs(pKernelGsp, NV_FALSE); + if (!kgspHealthCheck_HAL(pGpu, pKernelGsp)) + { + nvStatus = NV_ERR_RESET_REQUIRED; + break; + } } if (nRet < 0) @@ -341,50 +417,63 @@ NV_PRINTF(LEVEL_ERROR, "msgqRxLink failed: %d, nvStatus 0x%08x, retries: %d\n", nRet, nvStatus, nRetries); - GspMsgQueueCleanup(ppMQI); + _gspMsgQueueCleanup(*ppMQI); } return nvStatus; } -void GspMsgQueueCleanup(MESSAGE_QUEUE_INFO **ppMQI) +static void +_gspMsgQueueCleanup(MESSAGE_QUEUE_INFO *pMQI) +{ + if (pMQI == NULL) + { + return; + } + + portMemFree(pMQI->pWorkArea); + + pMQI->pWorkArea = NULL; + pMQI->pCmdQueueElement = NULL; + pMQI->pMetaData = NULL; +} + +void GspMsgQueuesCleanup(MESSAGE_QUEUE_COLLECTION **ppMQCollection) { - MESSAGE_QUEUE_INFO *pMQI = NULL; + MESSAGE_QUEUE_COLLECTION *pMQCollection = NULL; + MESSAGE_QUEUE_INFO *pRmQueueInfo = NULL; + MESSAGE_QUEUE_INFO *pTaskIsrQueueInfo = NULL; - if ((ppMQI == NULL) || (*ppMQI == NULL)) + if ((ppMQCollection == NULL) || (*ppMQCollection == NULL)) return; - pMQI = *ppMQI; - pMQI->hQueue = NULL; + pMQCollection = *ppMQCollection; + pRmQueueInfo = &pMQCollection->rpcQueues[RPC_TASK_RM_QUEUE_IDX]; + pTaskIsrQueueInfo = &pMQCollection->rpcQueues[RPC_TASK_ISR_QUEUE_IDX]; - if (pMQI->pWorkArea != NULL) - { - portMemFree(pMQI->pWorkArea); - pMQI->pWorkArea = NULL; - pMQI->pCmdQueueElement = NULL; - pMQI->pMetaData = NULL; - } + _gspMsgQueueCleanup(pRmQueueInfo); + _gspMsgQueueCleanup(pTaskIsrQueueInfo); - if (pMQI->pSharedMemDesc != NULL) + if (pMQCollection->pSharedMemDesc != NULL) { - NvP64 pVaKernel = memdescGetKernelMapping(pMQI->pSharedMemDesc); - NvP64 pPrivKernel = memdescGetKernelMappingPriv(pMQI->pSharedMemDesc); + NvP64 pVaKernel = memdescGetKernelMapping(pMQCollection->pSharedMemDesc); + NvP64 pPrivKernel = memdescGetKernelMappingPriv(pMQCollection->pSharedMemDesc); // Destroy kernel mapping for command queue. if (pVaKernel != 0) { - memdescUnmap(pMQI->pSharedMemDesc, NV_TRUE, osGetCurrentProcess(), + memdescUnmap(pMQCollection->pSharedMemDesc, NV_TRUE, osGetCurrentProcess(), pVaKernel, pPrivKernel); } // Free command queue memory. - memdescFree(pMQI->pSharedMemDesc); - memdescDestroy(pMQI->pSharedMemDesc); - pMQI->pSharedMemDesc = NULL; + memdescFree(pMQCollection->pSharedMemDesc); + memdescDestroy(pMQCollection->pSharedMemDesc); + pMQCollection->pSharedMemDesc = NULL; } - portMemFree(pMQI); - *ppMQI = NULL; + portMemFree(pMQCollection); + *ppMQCollection = NULL; } /*! @@ -422,9 +511,8 @@ NvU8 *pSrc = (NvU8 *)pCQE; NvU8 *pNextElement = NULL; int nRet; - int i; - int nRetries; - int nElements; + NvU32 i; + NvU32 nRetries; RMTIMEOUT timeout; NV_STATUS nvStatus = NV_OK; NvU32 uElementSize = GSP_MSG_QUEUE_ELEMENT_HDR_SIZE + @@ -443,13 +531,41 @@ if ((uElementSize & 7) != 0) portMemSet(pSrc + uElementSize, 0, 8 - (uElementSize & 7)); - pCQE->seqNum = pMQI->txSeqNum; - pCQE->checkSum = 0; - pCQE->checkSum = _checkSum32(pSrc, uElementSize); + pCQE->seqNum = pMQI->txSeqNum; + pCQE->elemCount = GSP_MSG_QUEUE_BYTES_TO_ELEMENTS(uElementSize); + pCQE->checkSum = 0; + + ConfidentialCompute *pCC = GPU_GET_CONF_COMPUTE(pGpu); + if (pCC != NULL && pCC->getProperty(pCC, PDB_PROP_CONFCOMPUTE_ENCRYPT_ENABLED)) + { + // Use sequence number as AAD. + portMemCopy((NvU8*)pCQE->aadBuffer, sizeof(pCQE->aadBuffer), (NvU8 *)&pCQE->seqNum, sizeof(pCQE->seqNum)); + + // We need to encrypt the full queue elements to obscure the data. + nvStatus = ccslEncrypt(pCC->pRpcCcslCtx, + (pCQE->elemCount * GSP_MSG_QUEUE_ELEMENT_SIZE_MIN) - GSP_MSG_QUEUE_ELEMENT_HDR_SIZE, + pSrc + GSP_MSG_QUEUE_ELEMENT_HDR_SIZE, + (NvU8*)pCQE->aadBuffer, + sizeof(pCQE->aadBuffer), + pSrc + GSP_MSG_QUEUE_ELEMENT_HDR_SIZE, + pCQE->authTagBuffer); + + if(nvStatus != NV_OK) + { + NV_PRINTF(LEVEL_ERROR, "Encryption failed with status = 0x%x.\n", nvStatus); + // Do not re-try if decryption failed. + return nvStatus; + } - nElements = GSP_MSG_QUEUE_BYTES_TO_ELEMENTS(uElementSize); + // Now that encryption covers elements completely, include them in checksum. + pCQE->checkSum = _checkSum32(pSrc, pCQE->elemCount * GSP_MSG_QUEUE_ELEMENT_SIZE_MIN); + } + else + { + pCQE->checkSum = _checkSum32(pSrc, uElementSize); + } - for (i = 0; i < nElements; i++) + for (i = 0; i < pCQE->elemCount; i++) { NvU32 timeoutFlags = 0; @@ -479,7 +595,9 @@ if (pNextElement == NULL) { pMQI->txBufferFull++; - NV_PRINTF_COND(pMQI->txBufferFull == 1, LEVEL_ERROR, LEVEL_INFO, "buffer is full\n"); + NV_PRINTF_COND(pMQI->txBufferFull == 1, LEVEL_ERROR, LEVEL_INFO, + "buffer is full (waiting for %d free elements, got %d)\n", + pCQE->elemCount, i); nvStatus = NV_ERR_BUSY_RETRY; goto done; } @@ -503,7 +621,7 @@ // portAtomicMemoryFenceStore(); - nRet = msgqTxSubmitBuffers(pMQI->hQueue, nElements); + nRet = msgqTxSubmitBuffers(pMQI->hQueue, pCQE->elemCount); if (nRet != 0) { @@ -533,24 +651,25 @@ * NV_ERR_NOT_READY - Partial read. * NV_ERR_INVALID_STATE - Something really bad happenned. */ -NV_STATUS GspMsgQueueReceiveStatus(MESSAGE_QUEUE_INFO *pMQI) +NV_STATUS GspMsgQueueReceiveStatus(MESSAGE_QUEUE_INFO *pMQI, OBJGPU *pGpu) { const NvU8 *pNextElement = NULL; NvU8 *pTgt = (NvU8 *)pMQI->pCmdQueueElement; int nRet; - int i; - int nRetries; - int nMaxRetries = 3; - int nElements = 1; // Assume record fits in one 256-byte queue element for now. + NvU32 i; + NvU32 nRetries; + NvU32 nMaxRetries = 3; + NvU32 nElements = 1; // Assume record fits in one queue element for now. NvU32 uElementSize = 0; NvU32 seqMismatchDiff = NV_U32_MAX; NV_STATUS nvStatus = NV_OK; + ConfidentialCompute *pCC = NULL; for (nRetries = 0; nRetries < nMaxRetries; nRetries++) { pTgt = (NvU8 *)pMQI->pCmdQueueElement; nvStatus = NV_OK; - nElements = 1; // Assume record fits in one 256-byte queue element for now. + nElements = 1; // Assume record fits in one queue element for now. for (i = 0; i < nElements; i++) { @@ -576,29 +695,14 @@ pNextElement, GSP_MSG_QUEUE_ELEMENT_SIZE_MIN); pTgt += GSP_MSG_QUEUE_ELEMENT_SIZE_MIN; - if (i != 0) - continue; - - // - // Special processing for first element of the record. - // Pull out the length and make sure it is valid. - // - uElementSize = GSP_MSG_QUEUE_ELEMENT_HDR_SIZE + - pMQI->pCmdQueueElement->rpc.length; - - if ((uElementSize < sizeof(GSP_MSG_QUEUE_ELEMENT)) || - (uElementSize > GSP_MSG_QUEUE_ELEMENT_SIZE_MAX)) + if (i == 0) { - // The length is not valid. If we are running without a fence, - // this could mean that the data is still in flight from the CPU. - NV_PRINTF(LEVEL_ERROR, "Incorrect length %u\n", - pMQI->pCmdQueueElement->rpc.length); - nvStatus = NV_ERR_INVALID_PARAM_STRUCT; - break; + // + // Special processing for first element of the record. + // Pull out the element count. This adjusts the loop condition. + // + nElements = pMQI->pCmdQueueElement->elemCount; } - - // This adjusts the loop condition. - nElements = GSP_MSG_QUEUE_BYTES_TO_ELEMENTS(uElementSize); } // Retry if there was an error. @@ -606,6 +710,17 @@ continue; // Retry if checksum fails. + pCC = GPU_GET_CONF_COMPUTE(pGpu); + if (pCC != NULL && pCC->getProperty(pCC, PDB_PROP_CONFCOMPUTE_ENCRYPT_READY)) + { + // In Confidential Compute scenario, checksum includes complete element range. + if (_checkSum32(pMQI->pCmdQueueElement, (nElements * GSP_MSG_QUEUE_ELEMENT_SIZE_MIN)) != 0) + { + NV_PRINTF(LEVEL_ERROR, "Bad checksum.\n"); + nvStatus = NV_ERR_INVALID_DATA; + continue; + } + } else if (_checkSum32(pMQI->pCmdQueueElement, uElementSize) != 0) { NV_PRINTF(LEVEL_ERROR, "Bad checksum.\n"); @@ -646,18 +761,6 @@ break; } - if (nvStatus == NV_OK) - { - pMQI->rxSeqNum++; - - nRet = msgqRxMarkConsumed(pMQI->hQueue, nElements); - if (nRet < 0) - { - NV_PRINTF(LEVEL_ERROR, "msgqRxMarkConsumed failed: %d\n", nRet); - nvStatus = NV_ERR_GENERIC; - } - } - if (nRetries > 0) { if (nvStatus == NV_OK) @@ -667,6 +770,52 @@ else { NV_PRINTF(LEVEL_ERROR, "Read failed after %d retries.\n", nRetries); + return nvStatus; + } + } + + pCC = GPU_GET_CONF_COMPUTE(pGpu); + if (pCC != NULL && pCC->getProperty(pCC, PDB_PROP_CONFCOMPUTE_ENCRYPT_READY)) + { + nvStatus = ccslDecrypt(pCC->pRpcCcslCtx, + (nElements * GSP_MSG_QUEUE_ELEMENT_SIZE_MIN) - GSP_MSG_QUEUE_ELEMENT_HDR_SIZE, + ((NvU8*)pMQI->pCmdQueueElement) + GSP_MSG_QUEUE_ELEMENT_HDR_SIZE, + NULL, + (NvU8*)pMQI->pCmdQueueElement->aadBuffer, + sizeof(pMQI->pCmdQueueElement->aadBuffer), + ((NvU8*)pMQI->pCmdQueueElement) + GSP_MSG_QUEUE_ELEMENT_HDR_SIZE, + ((NvU8*)pMQI->pCmdQueueElement->authTagBuffer)); + + if(nvStatus != NV_OK) + { + NV_PRINTF(LEVEL_ERROR, "Decryption failed with status = 0x%x.\n", nvStatus); + // Do not re-try if decryption failed. + return nvStatus; + } + } + + // Sanity check for the given RPC length + uElementSize = GSP_MSG_QUEUE_ELEMENT_HDR_SIZE + pMQI->pCmdQueueElement->rpc.length; + + if ((uElementSize < sizeof(GSP_MSG_QUEUE_ELEMENT)) || + (uElementSize > GSP_MSG_QUEUE_ELEMENT_SIZE_MAX)) + { + // The length is not valid. If we are running without a fence, + // this could mean that the data is still in flight from the CPU. + NV_PRINTF(LEVEL_ERROR, "Incorrect length %u\n", + pMQI->pCmdQueueElement->rpc.length); + nvStatus = NV_ERR_INVALID_PARAM_STRUCT; + } + + if (nvStatus == NV_OK) + { + pMQI->rxSeqNum++; + + nRet = msgqRxMarkConsumed(pMQI->hQueue, nElements); + if (nRet < 0) + { + NV_PRINTF(LEVEL_ERROR, "msgqRxMarkConsumed failed: %d\n", nRet); + nvStatus = NV_ERR_GENERIC; } } diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/kernel/gpu/hwpm/profiler_v2/kern_profiler_v2.c nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/kernel/gpu/hwpm/profiler_v2/kern_profiler_v2.c --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/kernel/gpu/hwpm/profiler_v2/kern_profiler_v2.c 2023-10-25 20:21:06.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/kernel/gpu/hwpm/profiler_v2/kern_profiler_v2.c 2024-03-05 22:13:31.000000000 +0000 @@ -177,7 +177,7 @@ NV_STATUS status = NV_OK; NV_RM_RPC_ALLOC_OBJECT(pGpu, hClient, hParent, hObject, class, - pAllocParams->pAllocParams, status); + pAllocParams->pAllocParams, pAllocParams->paramsSize, status); return status; } diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/kernel/gpu/hwpm/profiler_v2/kern_profiler_v2_ctrl.c nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/kernel/gpu/hwpm/profiler_v2/kern_profiler_v2_ctrl.c --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/kernel/gpu/hwpm/profiler_v2/kern_profiler_v2_ctrl.c 2023-10-25 20:21:07.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/kernel/gpu/hwpm/profiler_v2/kern_profiler_v2_ctrl.c 2024-03-05 22:13:31.000000000 +0000 @@ -27,6 +27,7 @@ #include "rmapi/rs_utils.h" #include "gpu/hwpm/profiler_v2.h" #include "ctrl/ctrlb0cc/ctrlb0ccinternal.h" +#include "ctrl/ctrlb0cc/ctrlb0ccprofiler.h" #include "mem_mgr/mem.h" #include "vgpu/rpc.h" @@ -88,7 +89,7 @@ pProfiler->pBoundPmaBuf = NULL; pCntMem->pMemDesc->bRmExclusiveUse = NV_FALSE; pBufMem->pMemDesc->bRmExclusiveUse = NV_FALSE; - + } if (pCountRef != NULL) { @@ -158,7 +159,7 @@ pBufMem->pMemDesc->bRmExclusiveUse = NV_FALSE; return NV_ERR_INVALID_ARGUMENT; } - + pProfiler->pBoundCntBuf = pCntRef; pProfiler->pBoundPmaBuf = pBufRef; } @@ -262,30 +263,41 @@ NvHandle hObject = RES_GET_HANDLE(pProfiler); NvBool bMemPmaBufferRegistered = NV_FALSE; NvBool bMemPmaBytesAvailableRegistered = NV_FALSE; + NVB0CC_CTRL_INTERNAL_ALLOC_PMA_STREAM_PARAMS internalParams; RsResourceRef *pMemoryRef = NULL; // // REGISTER MEMDESCs TO GSP // These are no-op with BareMetal/No GSP // - NV_CHECK_OK_OR_GOTO(status, LEVEL_ERROR, + NV_CHECK_OK_OR_GOTO(status, LEVEL_ERROR, memdescRegisterToGSP(pGpu, hClient, hParent, pParams->hMemPmaBuffer), fail); bMemPmaBufferRegistered = NV_TRUE; - NV_CHECK_OK_OR_GOTO(status, LEVEL_ERROR, + NV_CHECK_OK_OR_GOTO(status, LEVEL_ERROR, memdescRegisterToGSP(pGpu, hClient, hParent, pParams->hMemPmaBytesAvailable), fail); bMemPmaBytesAvailableRegistered = NV_TRUE; - + portMemSet(&internalParams, 0, sizeof(NVB0CC_CTRL_INTERNAL_ALLOC_PMA_STREAM_PARAMS)); + internalParams.hMemPmaBuffer = pParams->hMemPmaBuffer; + internalParams.pmaBufferOffset = pParams->pmaBufferOffset; + internalParams.pmaBufferSize = pParams->pmaBufferSize; + internalParams.hMemPmaBytesAvailable = pParams->hMemPmaBytesAvailable; + internalParams.pmaBytesAvailableOffset = pParams->pmaBytesAvailableOffset; + internalParams.ctxsw = pParams->ctxsw; + internalParams.pmaChannelIdx = pParams->pmaChannelIdx; + internalParams.pmaBufferVA = pParams->pmaBufferVA; + internalParams.bInputPmaChIdx = NV_FALSE; NV_CHECK_OK_OR_GOTO(status, LEVEL_ERROR, pRmApi->Control(pRmApi, hClient, hObject, NVB0CC_CTRL_CMD_INTERNAL_ALLOC_PMA_STREAM, - pParams, sizeof(*pParams)), fail); + &internalParams, sizeof(internalParams)), fail); + pParams->pmaChannelIdx = internalParams.pmaChannelIdx; if (serverutilGetResourceRef(hClient, pParams->hMemPmaBytesAvailable, &pMemoryRef) == NV_OK && serverutilGetResourceRef(hClient, pParams->hMemPmaBuffer, &pMemoryRef) == NV_OK) { @@ -302,12 +314,13 @@ pProfiler->ppBytesAvailable = (RsResourceRef**)portMemAllocNonPaged(maxPmaParams.maxPmaChannels * sizeof(RsResourceRef*)); pProfiler->ppStreamBuffers = (RsResourceRef**)portMemAllocNonPaged(maxPmaParams.maxPmaChannels * sizeof(RsResourceRef*)); } + NV_CHECK_OK_OR_GOTO(status, LEVEL_ERROR, serverutilGetResourceRef(hClient, pParams->hMemPmaBytesAvailable, &pMemoryRef), fail); pProfiler->ppBytesAvailable[pParams->pmaChannelIdx] = pMemoryRef; refAddDependant(pMemoryRef, RES_GET_REF(pProfiler)); - NV_CHECK_OK_OR_GOTO(status, LEVEL_ERROR, + NV_CHECK_OK_OR_GOTO(status, LEVEL_ERROR, serverutilGetResourceRef(hClient, pParams->hMemPmaBuffer, &pMemoryRef), fail); pProfiler->ppStreamBuffers[pParams->pmaChannelIdx] = pMemoryRef; refAddDependant(pMemoryRef, RES_GET_REF(pProfiler)); @@ -316,7 +329,10 @@ pProfiler->pmaVchIdx = pParams->pmaChannelIdx; pProfiler->bLegacyHwpm = NV_FALSE; } - + + // Copy output params to external struct. + pParams->pmaBufferVA = internalParams.pmaBufferVA; + return status; fail: @@ -334,3 +350,4 @@ return status; } + diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/kernel/gpu/intr/arch/ampere/intr_cpu_ga102.c nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/kernel/gpu/intr/arch/ampere/intr_cpu_ga102.c --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/kernel/gpu/intr/arch/ampere/intr_cpu_ga102.c 2023-10-25 20:21:07.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/kernel/gpu/intr/arch/ampere/intr_cpu_ga102.c 2024-03-05 22:13:31.000000000 +0000 @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 2020-2021 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2020-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -42,6 +42,12 @@ THREAD_STATE_NODE *pThreadState ) { + // SW assumptions that there are two top-levels. + ct_assert(NV_VIRTUAL_FUNCTION_PRIV_CPU_INTR_TOP_EN_SET__SIZE_1 <= 2); + if (regIndex >= NV_VIRTUAL_FUNCTION_PRIV_CPU_INTR_TOP_EN_SET__SIZE_1) + { + return 0x0; + } return GPU_VREG_RD32_EX(pGpu, NV_VIRTUAL_FUNCTION_PRIV_CPU_INTR_TOP_EN_SET(regIndex), pThreadState); @@ -57,6 +63,12 @@ THREAD_STATE_NODE *pThreadState ) { + // SW assumptions that there are two top-levels. + ct_assert(NV_VIRTUAL_FUNCTION_PRIV_CPU_INTR_TOP_EN_SET__SIZE_1 <= 2); + if (regIndex >= NV_VIRTUAL_FUNCTION_PRIV_CPU_INTR_TOP_EN_SET__SIZE_1) + { + return; + } GPU_VREG_WR32_EX(pGpu, NV_VIRTUAL_FUNCTION_PRIV_CPU_INTR_TOP_EN_SET(regIndex), value, @@ -73,6 +85,12 @@ THREAD_STATE_NODE *pThreadState ) { + // SW assumptions that there are two top-levels. + ct_assert(NV_VIRTUAL_FUNCTION_PRIV_CPU_INTR_TOP_EN_CLEAR__SIZE_1 <= 2); + if (regIndex >= NV_VIRTUAL_FUNCTION_PRIV_CPU_INTR_TOP_EN_CLEAR__SIZE_1) + { + return; + } GPU_VREG_WR32_EX(pGpu, NV_VIRTUAL_FUNCTION_PRIV_CPU_INTR_TOP_EN_CLEAR(regIndex), value, diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/kernel/gpu/intr/arch/ampere/intr_ga100.c nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/kernel/gpu/intr/arch/ampere/intr_ga100.c --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/kernel/gpu/intr/arch/ampere/intr_ga100.c 2023-10-25 20:21:07.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/kernel/gpu/intr/arch/ampere/intr_ga100.c 2024-03-05 22:13:31.000000000 +0000 @@ -59,6 +59,7 @@ NvU32 intrVectorNonReplayableFault; NvU32 intrVectorTimerSwrl = NV_INTR_VECTOR_INVALID; NvU64 mask = 0; + NV2080_INTR_CATEGORY_SUBTREE_MAP uvmShared; // GSP RM services both MMU non-replayable fault and FIFO interrupts with // vgpu plugin offload enabled. Otherwise, GSP RM only services FIFO interrupts @@ -83,25 +84,30 @@ NV_CTRL_INTR_GPU_VECTOR_TO_LEAF_REG(intrVectorTimerSwrl)); } + NV_ASSERT_OK(intrGetSubtreeRange(pIntr, + NV2080_INTR_CATEGORY_UVM_SHARED, + &uvmShared)); // - // Compile-time ascertain that we only have 1 client subtree (we assume - // this since we cache only 64 bits). + // Ascertain that we only have 1 client subtree (we assume this since we + // cache only 64 bits). // - ct_assert(NV_CPU_INTR_UVM_SHARED_SUBTREE_START == NV_CPU_INTR_UVM_SHARED_SUBTREE_LAST); + NV_ASSERT(uvmShared.subtreeStart == uvmShared.subtreeEnd); // - // Compile-time ascertain that we only have 2 subtrees as this is what we currently support - // by only caching 64 bits + // Ascertain that we only have 2 subtrees as this is what we currently + // support by only caching 64 bits // - ct_assert((NV_CTRL_INTR_SUBTREE_TO_LEAF_IDX_END(NV_CPU_INTR_UVM_SHARED_SUBTREE_LAST) - 1) == - NV_CTRL_INTR_SUBTREE_TO_LEAF_IDX_START(NV_CPU_INTR_UVM_SHARED_SUBTREE_START)); + NV_ASSERT( + (NV_CTRL_INTR_SUBTREE_TO_LEAF_IDX_END(uvmShared.subtreeEnd) - 1) == + NV_CTRL_INTR_SUBTREE_TO_LEAF_IDX_START(uvmShared.subtreeStart)); // On GSP we service non replayable faults in the bottom half, so we shouldn't mask them if (intrVectorNonReplayableFault != NV_INTR_VECTOR_INVALID) { // Ascertain that it's in the first leaf - NV_ASSERT(NV_CTRL_INTR_GPU_VECTOR_TO_LEAF_REG(intrVectorNonReplayableFault) == - NV_CTRL_INTR_SUBTREE_TO_LEAF_IDX_START(NV_CPU_INTR_UVM_SHARED_SUBTREE_START)); + NV_ASSERT( + NV_CTRL_INTR_GPU_VECTOR_TO_LEAF_REG(intrVectorNonReplayableFault) == + NV_CTRL_INTR_SUBTREE_TO_LEAF_IDX_START(uvmShared.subtreeStart)); mask |= NVBIT32(NV_CTRL_INTR_GPU_VECTOR_TO_LEAF_BIT(intrVectorNonReplayableFault)); } @@ -109,8 +115,9 @@ if (intrVectorTimerSwrl != NV_INTR_VECTOR_INVALID) { // Ascertain that it's in the first leaf - NV_ASSERT(NV_CTRL_INTR_GPU_VECTOR_TO_LEAF_REG(intrVectorTimerSwrl) == - NV_CTRL_INTR_SUBTREE_TO_LEAF_IDX_START(NV_CPU_INTR_UVM_SHARED_SUBTREE_START)); + NV_ASSERT( + NV_CTRL_INTR_GPU_VECTOR_TO_LEAF_REG(intrVectorTimerSwrl) == + NV_CTRL_INTR_SUBTREE_TO_LEAF_IDX_START(uvmShared.subtreeStart)); mask |= NVBIT32(NV_CTRL_INTR_GPU_VECTOR_TO_LEAF_BIT(intrVectorTimerSwrl)); } diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/kernel/gpu/intr/arch/hopper/intr_gh100.c nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/kernel/gpu/intr/arch/hopper/intr_gh100.c --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/kernel/gpu/intr/arch/hopper/intr_gh100.c 2023-10-25 20:21:07.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/kernel/gpu/intr/arch/hopper/intr_gh100.c 2024-03-05 22:13:31.000000000 +0000 @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 2020-2021 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2020-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -31,32 +31,51 @@ // Compile time asserts to make sure we don't write beyond the leaf register array -ct_assert(NV_CPU_INTR_STALL_SUBTREE_START < NV_VIRTUAL_FUNCTION_PRIV_CPU_INTR_LEAF__SIZE_1); -ct_assert(NV_CPU_INTR_STALL_SUBTREE_LAST < NV_VIRTUAL_FUNCTION_PRIV_CPU_INTR_LEAF__SIZE_1); -ct_assert(NV_CPU_INTR_STALL_SUBTREE_START < NV_VIRTUAL_FUNCTION_PRIV_CPU_INTR_LEAF_EN_SET__SIZE_1); -ct_assert(NV_CPU_INTR_STALL_SUBTREE_LAST < NV_VIRTUAL_FUNCTION_PRIV_CPU_INTR_LEAF_EN_SET__SIZE_1); -ct_assert(NV_CPU_INTR_STALL_SUBTREE_START < NV_VIRTUAL_FUNCTION_PRIV_CPU_INTR_LEAF_EN_CLEAR__SIZE_1); -ct_assert(NV_CPU_INTR_STALL_SUBTREE_LAST < NV_VIRTUAL_FUNCTION_PRIV_CPU_INTR_LEAF_EN_CLEAR__SIZE_1); - ct_assert(NV_VIRTUAL_FUNCTION_PRIV_CPU_INTR_LEAF__SIZE_1 == NV_VIRTUAL_FUNCTION_PRIV_CPU_INTR_LEAF_EN_SET__SIZE_1); ct_assert(NV_VIRTUAL_FUNCTION_PRIV_CPU_INTR_LEAF__SIZE_1 == NV_VIRTUAL_FUNCTION_PRIV_CPU_INTR_LEAF_EN_CLEAR__SIZE_1); -/*! - * @brief Gets the stall subtree end index - */ -NvU32 -intrGetStallSubtreeLast_GH100(OBJGPU *pGpu, Intr *pIntr) + +NV_STATUS +intrInitSubtreeMap_GH100 +( + OBJGPU *pGpu, + Intr *pIntr +) { - if (pGpu->getProperty(pGpu, PDB_PROP_GPU_SWRL_GRANULAR_LOCKING)) - { - return NV_CPU_INTR_STALL_SUBTREE_LAST_SWRL; - } - else - { - return NV_CPU_INTR_STALL_SUBTREE_LAST; - } + NV2080_INTR_CATEGORY_SUBTREE_MAP *pCategoryEngine = + &pIntr->subtreeMap[NV2080_INTR_CATEGORY_ESCHED_DRIVEN_ENGINE]; + pCategoryEngine->subtreeStart = NV_CPU_INTR_STALL_SUBTREE_START; + pCategoryEngine->subtreeEnd = NV_CPU_INTR_STALL_SUBTREE_START; + + NV2080_INTR_CATEGORY_SUBTREE_MAP *pCategoryEngineNotification = + &pIntr->subtreeMap[NV2080_INTR_CATEGORY_ESCHED_DRIVEN_ENGINE_NOTIFICATION]; + pCategoryEngineNotification->subtreeStart = NV_VIRTUAL_FUNCTION_PRIV_CPU_INTR_TOP_SUBTREE(0); + pCategoryEngineNotification->subtreeEnd = NV_VIRTUAL_FUNCTION_PRIV_CPU_INTR_TOP_SUBTREE(0); + + NV2080_INTR_CATEGORY_SUBTREE_MAP *pCategoryRunlistLocked = + &pIntr->subtreeMap[NV2080_INTR_CATEGORY_RUNLIST]; + pCategoryRunlistLocked->subtreeStart = NV_CPU_INTR_STALL_SUBTREE_LAST_SWRL; + pCategoryRunlistLocked->subtreeEnd = NV_CPU_INTR_STALL_SUBTREE_LAST_SWRL; + + NV2080_INTR_CATEGORY_SUBTREE_MAP *pCategoryRunlistNotification = + &pIntr->subtreeMap[NV2080_INTR_CATEGORY_RUNLIST_NOTIFICATION]; + pCategoryRunlistNotification->subtreeStart = NV_CPU_INTR_STALL_SUBTREE_LAST; + pCategoryRunlistNotification->subtreeEnd = NV_CPU_INTR_STALL_SUBTREE_LAST; + + NV2080_INTR_CATEGORY_SUBTREE_MAP *pCategoryUvmOwned = + &pIntr->subtreeMap[NV2080_INTR_CATEGORY_UVM_OWNED]; + pCategoryUvmOwned->subtreeStart = NV_CPU_INTR_UVM_SUBTREE_START; + pCategoryUvmOwned->subtreeEnd = NV_CPU_INTR_UVM_SUBTREE_LAST; + + NV2080_INTR_CATEGORY_SUBTREE_MAP *pCategoryUvmShared = + &pIntr->subtreeMap[NV2080_INTR_CATEGORY_UVM_SHARED]; + pCategoryUvmShared->subtreeStart = NV_CPU_INTR_UVM_SHARED_SUBTREE_START; + pCategoryUvmShared->subtreeEnd = NV_CPU_INTR_UVM_SHARED_SUBTREE_LAST; + + return NV_OK; } + /*! * @brief Gets the number of leaf registers used */ @@ -76,14 +95,15 @@ return NV_VIRTUAL_FUNCTION_PRIV_CPU_INTR_LEAF__SIZE_1; } -/*! - * @brief Gets the mask of INTR_TOP that covers nonstall interrupts - */ -NvU32 -intrGetIntrTopNonStallMask_GH100(OBJGPU *pGpu, Intr *pIntr) -{ - NvU32 nonStallMask; +NvU64 +intrGetIntrTopNonStallMask_GH100 +( + OBJGPU *pGpu, + Intr *pIntr +) +{ + // TODO Bug 3823562 Remove all these asserts // Compile-time assert against the highest set bit that will be returned #define NV_CPU_INTR_NOSTALL_SUBTREE_HIGHEST NV_VIRTUAL_FUNCTION_PRIV_CPU_INTR_TOP_SUBTREE(5) @@ -91,16 +111,23 @@ ct_assert(NV_CPU_INTR_NOSTALL_SUBTREE_HIGHEST < NV_VIRTUAL_FUNCTION_PRIV_CPU_INTR_LEAF_EN_SET__SIZE_1); ct_assert(NV_CPU_INTR_NOSTALL_SUBTREE_HIGHEST < NV_VIRTUAL_FUNCTION_PRIV_CPU_INTR_LEAF_EN_CLEAR__SIZE_1); - nonStallMask = NVBIT32(NV_VIRTUAL_FUNCTION_PRIV_CPU_INTR_TOP_SUBTREE(0)); + + NvU64 mask = 0; + mask |= intrGetIntrTopCategoryMask(pIntr, + NV2080_INTR_CATEGORY_ESCHED_DRIVEN_ENGINE_NOTIFICATION); if (pGpu->getProperty(pGpu, PDB_PROP_GPU_SWRL_GRANULAR_LOCKING)) { - nonStallMask |= NVBIT32(NV_VIRTUAL_FUNCTION_PRIV_CPU_INTR_TOP_SUBTREE(5)); + mask |= intrGetIntrTopCategoryMask(pIntr, + NV2080_INTR_CATEGORY_RUNLIST_NOTIFICATION); } - return nonStallMask; + // Sanity check that Intr.subtreeMap is initialized + NV_ASSERT(mask != 0); + return mask; } + /*! * @brief Sanity check that the given stall engine interrupt vector is in the right tree * diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/kernel/gpu/intr/arch/maxwell/intr_gm107.c nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/kernel/gpu/intr/arch/maxwell/intr_gm107.c --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/kernel/gpu/intr/arch/maxwell/intr_gm107.c 2023-10-25 20:21:07.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/kernel/gpu/intr/arch/maxwell/intr_gm107.c 2024-03-05 22:13:31.000000000 +0000 @@ -46,6 +46,7 @@ THREAD_STATE_NODE *pThreadState ) { + KernelDisplay *pKernelDisplay = GPU_GET_KERNEL_DISPLAY(pGpu); NvU8 i; NV_ASSERT_OR_RETURN(pEngines != NULL, NV_ERR_INVALID_ARGUMENT); @@ -77,6 +78,12 @@ if (IS_VIRTUAL(pGpu) && vgpuGetPendingEvent(pGpu, pThreadState)) bitVectorSet(pEngines, MC_ENGINE_IDX_VGPU); + if (pKernelDisplay != NULL && kdispGetDeferredVblankHeadMask(pKernelDisplay)) + { + // Deferred vblank is pending which we need to handle + bitVectorSet(pEngines, MC_ENGINE_IDX_DISP); + } + if (pGpu->fecsCtxswLogConsumerCount > 0) { // diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/kernel/gpu/intr/arch/turing/intr_cpu_tu102.c nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/kernel/gpu/intr/arch/turing/intr_cpu_tu102.c --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/kernel/gpu/intr/arch/turing/intr_cpu_tu102.c 2023-10-25 20:21:07.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/kernel/gpu/intr/arch/turing/intr_cpu_tu102.c 2024-03-05 22:13:32.000000000 +0000 @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 2020-2021 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2020-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -70,6 +70,12 @@ THREAD_STATE_NODE *pThreadState ) { + // SW assumptions that there are two top-levels. + ct_assert(NV_VIRTUAL_FUNCTION_PRIV_CPU_INTR_TOP_EN_SET__SIZE_1 <= 2); + if (regIndex >= NV_VIRTUAL_FUNCTION_PRIV_CPU_INTR_TOP_EN_SET__SIZE_1) + { + return 0x0; + } return GPU_VREG_RD32_EX(pGpu, NV_VIRTUAL_FUNCTION_PRIV_CPU_INTR_TOP_EN_SET(regIndex), pThreadState); @@ -84,6 +90,12 @@ THREAD_STATE_NODE *pThreadState ) { + // SW assumptions that there are two top-levels. + ct_assert(NV_VIRTUAL_FUNCTION_PRIV_CPU_INTR_TOP__SIZE_1 <= 2); + if (regIndex >= NV_VIRTUAL_FUNCTION_PRIV_CPU_INTR_TOP__SIZE_1) + { + return 0x0; + } return GPU_VREG_RD32_EX(pGpu, NV_VIRTUAL_FUNCTION_PRIV_CPU_INTR_TOP(regIndex), pThreadState); @@ -147,6 +159,12 @@ THREAD_STATE_NODE *pThreadState ) { + // SW assumptions that there are two top-levels. + ct_assert(NV_VIRTUAL_FUNCTION_PRIV_CPU_INTR_TOP_EN_SET__SIZE_1 <= 2); + if (regIndex >= NV_VIRTUAL_FUNCTION_PRIV_CPU_INTR_TOP_EN_SET__SIZE_1) + { + return; + } GPU_VREG_WR32_EX(pGpu, NV_VIRTUAL_FUNCTION_PRIV_CPU_INTR_TOP_EN_SET(regIndex), value, @@ -163,6 +181,12 @@ THREAD_STATE_NODE *pThreadState ) { + // SW assumptions that there are two top-levels. + ct_assert(NV_VIRTUAL_FUNCTION_PRIV_CPU_INTR_TOP_EN_CLEAR__SIZE_1 <= 2); + if (regIndex >= NV_VIRTUAL_FUNCTION_PRIV_CPU_INTR_TOP_EN_CLEAR__SIZE_1) + { + return; + } GPU_VREG_WR32_EX(pGpu, NV_VIRTUAL_FUNCTION_PRIV_CPU_INTR_TOP_EN_CLEAR(regIndex), value, diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/kernel/gpu/intr/arch/turing/intr_nonstall_tu102.c nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/kernel/gpu/intr/arch/turing/intr_nonstall_tu102.c --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/kernel/gpu/intr/arch/turing/intr_nonstall_tu102.c 2023-10-25 20:21:07.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/kernel/gpu/intr/arch/turing/intr_nonstall_tu102.c 2024-03-05 22:13:32.000000000 +0000 @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 2017-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2017-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -35,21 +35,19 @@ #include "published/turing/tu102/dev_vm.h" -/*! - * @brief Get the current non-stall interrupt enable status - */ + +/*! Get the current non-stall interrupt enable status. */ NvU32 intrGetNonStallEnable_TU102 ( - OBJGPU *pGpu, - Intr *pIntr, + OBJGPU *pGpu, + Intr *pIntr, THREAD_STATE_NODE *pThreadState ) { - NvU32 i; - NvU32 val; - NvU32 nonStallMask; - + NvU64 nonStallMask; + NvU32 maskLo; + NvU32 maskHi; NvU32 isNonStallEnabled = 0; if (IS_VIRTUAL_WITHOUT_SRIOV(pGpu)) @@ -62,51 +60,40 @@ return INTERRUPT_TYPE_DISABLED; } + nonStallMask = intrGetIntrTopNonStallMask_HAL(pGpu, pIntr); + maskLo = NvU64_LO32(nonStallMask); + maskHi = NvU64_HI32(nonStallMask); + // - // We're doing an optimization below to read the TOP_EN_CLEAR register once - // after the for() loop that loops over the subtrees. It assumes that we - // only have one single top level enable register. HW has support for 2 top - // level registers, but until we get to using the second top level register, - // there's no need for us to write code that uses it (it should be a long - // time away, anyway). Use compile-time asserts to catch that this - // assumption has not changed. + // We rely on boolean operator short-circuiting here to avoid reading a + // TopEnSet register if not strictly necessary. // - ct_assert(sizeof(nonStallMask) == sizeof(NvU32)); - - val = intrReadRegTopEnSet_HAL(pGpu, pIntr, 0, pThreadState); - - nonStallMask = intrGetIntrTopNonStallMask_HAL(pGpu, pIntr); - FOR_EACH_INDEX_IN_MASK(32, i, nonStallMask) - { - if (val & NVBIT(NV_CTRL_INTR_SUBTREE_TO_TOP_BIT(i))) + if ((maskLo != 0 && + (maskLo & intrReadRegTopEnSet_HAL(pGpu, pIntr, 0, pThreadState)) != 0) + || + (maskHi != 0 && + (maskHi & intrReadRegTopEnSet_HAL(pGpu, pIntr, 1, pThreadState)) != 0)) { // - // If any top-level subtree corresponding to non-stall interrupts - // is enabled, return that non-stall interrupts are enabled. We - // only support enabling or disabling all non-stall interrupts at - // once, not a subset. - // Note that INTERRUPT_TYPE_MULTI basically means that all kinds - // of non-stall interrupts are enabled. The legacy pre-Pascal code - // had support to only enable software-triggerable interrupts or - // hardware-triggerable interrupts or both. We're just continuing - // to the same enum, but the naming of MULTI in the new interrupt - // tree warrants some explanation, hence the detailed comment. + // If any top-level subtree corresponding to non-stall interrupts is + // enabled, return that non-stall interrupts are enabled. We only + // support enabling or disabling all non-stall interrupts at once, not a + // subset. + // Note that INTERRUPT_TYPE_MULTI basically means that all kinds of + // non-stall interrupts are enabled. The legacy pre-Pascal code had + // support to only enable software-triggerable interrupts or + // hardware-triggerable interrupts or both. We're just continuing to the + // same enum, but the naming of MULTI in the new interrupt tree warrants + // some explanation, hence the detailed comment. // return INTERRUPT_TYPE_MULTI; } - } - FOR_EACH_INDEX_IN_MASK_END; return INTERRUPT_TYPE_DISABLED; } -/*! - * @brief Enable all nonstall interrupts in dev_ctrl at top level - * - * @param[in] pGpu OBJGPU pointer - * @param[in] pIntr Intr pointer - * @param[in] pThreadState thread state node pointer - */ + +/*! Enable all nonstall interrupts in dev_ctrl at top level. */ void intrEnableTopNonstall_TU102 ( @@ -115,39 +102,27 @@ THREAD_STATE_NODE *pThreadState ) { - NvU32 i; - NvU32 val = 0; - NvU32 nonStallMask; - - // - // We're doing an optimization below to write the TOP_EN_CLEAR register once - // after the for() loop that loops over the subtrees. It assumes that we - // only have one single top level enable register. HW has support for 2 top - // level registers, but until we get to using the second top level register, - // there's no need for us to write code that uses it (it should be a long - // time away, anyway). Use compile-time asserts to catch that this - // assumption has not changed. - // - ct_assert(sizeof(nonStallMask) == sizeof(NvU32)); + NvU64 nonStallMask; nonStallMask = intrGetIntrTopNonStallMask_HAL(pGpu, pIntr); - FOR_EACH_INDEX_IN_MASK(32, i, nonStallMask) + + if (NvU64_LO32(nonStallMask) != 0) { - val |= (NV_VIRTUAL_FUNCTION_PRIV_CPU_INTR_TOP_EN_SET_SUBTREE_ENABLE << (NV_CTRL_INTR_SUBTREE_TO_TOP_BIT(i))); + intrWriteRegTopEnSet_HAL(pGpu, pIntr, + 0, + NvU64_LO32(nonStallMask), + pThreadState); + } + if (NvU64_HI32(nonStallMask) != 0) + { + intrWriteRegTopEnSet_HAL(pGpu, pIntr, + 1, + NvU64_HI32(nonStallMask), + pThreadState); } - FOR_EACH_INDEX_IN_MASK_END; - - // This optimization of one single register write - intrWriteRegTopEnSet_HAL(pGpu, pIntr, NV_CTRL_INTR_SUBTREE_TO_TOP_IDX(0), val, pThreadState); } -/*! - * @brief Disable all nonstall interrupts in dev_ctrl at top level - * - * @param[in] pGpu OBJGPU pointer - * @param[in] pIntr Intr pointer - * @param[in] pThreadState thread state node pointer - */ +/*! Disable all nonstall interrupts in dev_ctrl at top level. */ void intrDisableTopNonstall_TU102 ( @@ -156,29 +131,24 @@ THREAD_STATE_NODE *pThreadState ) { - NvU32 i; - NvU32 val = 0; - NvU32 nonStallMask; - - // - // We're doing an optimization below to write the TOP_EN_CLEAR register once - // after the for() loop that loops over the subtrees. It assumes that we - // only have one single top level enable register. HW has support for 2 top - // level registers, but until we get to using the second top level register, - // there's no need for us to write code that uses it (it should be a long - // time away, anyway). Use compile-time asserts to catch that this - // assumption has not changed. - // - ct_assert(sizeof(nonStallMask) == sizeof(NvU32)); + NvU64 nonStallMask; nonStallMask = intrGetIntrTopNonStallMask_HAL(pGpu, pIntr); - FOR_EACH_INDEX_IN_MASK(32, i, nonStallMask) + + if (NvU64_LO32(nonStallMask) != 0) { - val |= (NV_VIRTUAL_FUNCTION_PRIV_CPU_INTR_TOP_EN_CLEAR_SUBTREE_DISABLE << (NV_CTRL_INTR_SUBTREE_TO_TOP_BIT(i))); + intrWriteRegTopEnClear_HAL(pGpu, pIntr, + 0, + NvU64_LO32(nonStallMask), + pThreadState); + } + if (NvU64_HI32(nonStallMask) != 0) + { + intrWriteRegTopEnClear_HAL(pGpu, pIntr, + 1, + NvU64_HI32(nonStallMask), + pThreadState); } - FOR_EACH_INDEX_IN_MASK_END; - - intrWriteRegTopEnClear_HAL(pGpu, pIntr, NV_CTRL_INTR_SUBTREE_TO_TOP_IDX(0), val, pThreadState); } void @@ -226,12 +196,11 @@ THREAD_STATE_NODE *pThreadState ) { - KernelFifo *pKernelFifo = GPU_GET_KERNEL_FIFO(pGpu); - INTR_TABLE_ENTRY *pIntrTable; - NvU32 intrTableSz; - NvU32 i, j, k; - NvU32 pending; - NvU32 intrVector; + KernelFifo *pKernelFifo = GPU_GET_KERNEL_FIFO(pGpu); + InterruptTable *pIntrTable; + NvU32 i, j; + NvU32 pending; + NvU32 intrVector; NV_ASSERT_OR_RETURN(pEngines != NULL, NV_ERR_INVALID_ARGUMENT); @@ -257,11 +226,12 @@ return vgpuIsNonStallPending(pGpu, pEngines); } - NV_ASSERT_OK_OR_RETURN(intrGetInterruptTable_HAL(pGpu, pIntr, &pIntrTable, &intrTableSz)); + NV_ASSERT_OK_OR_RETURN(intrGetInterruptTable_HAL(pGpu, pIntr, &pIntrTable)); - FOR_EACH_INDEX_IN_MASK(32, i, intrGetIntrTopNonStallMask_HAL(pGpu, pIntr)) + FOR_EACH_INDEX_IN_MASK(64, i, intrGetIntrTopNonStallMask_HAL(pGpu, pIntr)) { j = NV_CTRL_INTR_SUBTREE_TO_TOP_IDX(i); + // TODO Bug 3823562: optimize this and don't read on every loop pending = intrReadRegTop_HAL(pGpu, pIntr, j, pThreadState); if ((pending & (NV_VIRTUAL_FUNCTION_PRIV_CPU_INTR_TOP_SUBTREE_INTR_PENDING << NV_CTRL_INTR_SUBTREE_TO_TOP_BIT(i))) == 0) @@ -271,6 +241,7 @@ for (j = NV_CTRL_INTR_SUBTREE_TO_LEAF_IDX_START(i); j <= NV_CTRL_INTR_SUBTREE_TO_LEAF_IDX_END(i); j++) { + InterruptTableIter iter; NvU32 intr = intrReadRegLeaf_HAL(pGpu, pIntr, j, pThreadState) & intrReadRegLeafEnSet_HAL(pGpu, pIntr, j, pThreadState); if (intr == 0) @@ -278,9 +249,10 @@ continue; } - for (k = 0; k < intrTableSz; k++) + for (iter = vectIterAll(pIntrTable); vectIterNext(&iter);) { - NvU32 intrVector = pIntrTable[k].intrVectorNonStall; + INTR_TABLE_ENTRY *pEntry = iter.pValue; + NvU32 intrVector = pEntry->intrVectorNonStall; if (intrVector == NV_INTR_VECTOR_INVALID) { @@ -296,7 +268,7 @@ } if (intr & NVBIT(NV_CTRL_INTR_GPU_VECTOR_TO_LEAF_BIT(intrVector))) { - bitVectorSet(pEngines, pIntrTable[k].mcEngine); + bitVectorSet(pEngines, pEntry->mcEngine); } } } @@ -347,23 +319,21 @@ THREAD_STATE_NODE *pThreadState ) { - INTR_TABLE_ENTRY *pIntrTable; - NvU32 intrTableSz; - NV_STATUS status = NV_OK; - NV_STATUS tmpStatus; - NvU32 i; - NvU16 mcEngineIdx; + InterruptTable *pIntrTable; + NV_STATUS status = NV_OK; + NV_STATUS tmpStatus; + InterruptTableIter iter; + NvU16 mcEngineIdx; // Don't clear the bitvector pEngines since caller accumulates + NV_ASSERT_OK_OR_RETURN(intrGetInterruptTable_HAL(pGpu, pIntr, &pIntrTable)); - NV_ASSERT_OK_OR_RETURN(intrGetInterruptTable_HAL(pGpu, pIntr, &pIntrTable, &intrTableSz)); - - for (i = 0; i < intrTableSz; i++) + for (iter = vectIterAll(pIntrTable); vectIterNext(&iter);) { - NvU32 intrVector; - NvU32 intrPending; + INTR_TABLE_ENTRY *pEntry = iter.pValue; + NvU32 intrVector = pEntry->intrVectorNonStall; + NvU32 intrPending; - intrVector = pIntrTable[i].intrVectorNonStall; if (intrVector == NV_INTR_VECTOR_INVALID) { // This engine does not have a valid nonstall interrupt vector @@ -383,7 +353,7 @@ continue; } - mcEngineIdx = pIntrTable[i].mcEngine; + mcEngineIdx = pEntry->mcEngine; bitVectorSet(pEngines, mcEngineIdx); // @@ -453,9 +423,10 @@ return vgpuServiceNonStall(pGpu, pEngines); } - FOR_EACH_INDEX_IN_MASK(32, i, intrGetIntrTopNonStallMask_HAL(pGpu, pIntr)) + FOR_EACH_INDEX_IN_MASK(64, i, intrGetIntrTopNonStallMask_HAL(pGpu, pIntr)) { NvU32 j = NV_CTRL_INTR_SUBTREE_TO_TOP_IDX(i); + // TODO Bug 3823562: optimize this and don't read on every loop pending = intrReadRegTop_HAL(pGpu, pIntr, j, pThreadState); if ((pending & (NV_VIRTUAL_FUNCTION_PRIV_CPU_INTR_TOP_SUBTREE_INTR_PENDING << NV_CTRL_INTR_SUBTREE_TO_TOP_BIT(i))) == 0) diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/kernel/gpu/intr/arch/turing/intr_sriov_tu102.c nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/kernel/gpu/intr/arch/turing/intr_sriov_tu102.c --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/kernel/gpu/intr/arch/turing/intr_sriov_tu102.c 2023-10-25 20:21:08.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/kernel/gpu/intr/arch/turing/intr_sriov_tu102.c 2024-03-05 22:13:32.000000000 +0000 @@ -34,47 +34,6 @@ // /*! - * @brief Enables virtual interrupts to be sent from a virtual function with - * the specified GFID. - * - * @param[in] pGpu OBJGPU pointer - * @param[in] pIntr Intr pointer - * @param[in] gfid GFID assigned to the virtual function - */ -NV_STATUS -intrEnableVirtualIntrLeaf_TU102 -( - OBJGPU *pGpu, - Intr *pIntr, - NvU32 gfid -) -{ - GFID_ALLOC_STATUS gfidState; - NvU32 reg = gfid / (DRF_SIZE(NV_CTRL_VIRTUAL_INTR_LEAF_EN_SET_VALUE)); - NvU32 bit = gfid % (DRF_SIZE(NV_CTRL_VIRTUAL_INTR_LEAF_EN_SET_VALUE)); - - NV_ASSERT_OK_OR_RETURN(gpuGetGfidState(pGpu, gfid, &gfidState)); - if (gfidState == GFID_FREE) - { - NV_PRINTF(LEVEL_ERROR, "Invalid GFID 0x%x\n", gfid); - DBG_BREAKPOINT(); - return NV_ERR_INVALID_ARGUMENT; - } - - if (reg >= NV_CTRL_VIRTUAL_INTR_LEAF_EN_SET__SIZE_1) - { - NV_PRINTF(LEVEL_ERROR, "Computed register index exceeds valid available " - "range of NV_CTRL_VIRTUAL_INTR_LEAF_EN_SET. reg idx = 0x%x\n", reg); - DBG_BREAKPOINT(); - return NV_ERR_INVALID_ARGUMENT; - } - - GPU_REG_WR32(pGpu, NV_CTRL_VIRTUAL_INTR_LEAF_EN_SET(reg), - (NV_CTRL_VIRTUAL_INTR_LEAF_EN_SET_VECTOR_ENABLE << bit)); - return NV_OK; -} - -/*! * @brief Services virtual interrupts, i.e. interrupts triggered by PRIV_DOORBELL * writes from virtual functions * diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/kernel/gpu/intr/arch/turing/intr_tu102.c nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/kernel/gpu/intr/arch/turing/intr_tu102.c --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/kernel/gpu/intr/arch/turing/intr_tu102.c 2023-10-25 20:21:08.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/kernel/gpu/intr/arch/turing/intr_tu102.c 2024-03-05 22:13:32.000000000 +0000 @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 2017-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2017-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -32,6 +32,8 @@ #include "vgpu/vgpu_events.h" #include "vgpu/rpc.h" #include "gpu/mmu/kern_gmmu.h" +#include "libraries/nvport/nvport.h" +#include "gpu/disp/kern_disp.h" #include "published/turing/tu102/dev_ctrl.h" #include "published/turing/tu102/dev_vm.h" @@ -113,10 +115,10 @@ ) { NV_STATUS status = NV_OK; - INTR_TABLE_ENTRY *pIntrTable; - NvU32 intrTableSz, i; + InterruptTable *pIntrTable; + InterruptTableIter iter; - NV_ASSERT_OK_OR_RETURN(intrGetInterruptTable_HAL(pGpu, pIntr, &pIntrTable, &intrTableSz)); + NV_ASSERT_OK_OR_RETURN(intrGetInterruptTable_HAL(pGpu, pIntr, &pIntrTable)); // // Make sure all leaf nodes are disabled before we enable them. Older drivers @@ -135,25 +137,26 @@ // and all the VFs // pGpu->pmcRmOwnsIntrMask = INTERRUPT_MASK_DISABLED; - for (i = 0; i < intrTableSz; i++) + for (iter = vectIterAll(pIntrTable); vectIterNext(&iter);) { - if (pIntrTable[i].pmcIntrMask != NV_PMC_INTR_INVALID_MASK) + INTR_TABLE_ENTRY *pEntry = iter.pValue; + if (pEntry->pmcIntrMask != NV_PMC_INTR_INVALID_MASK) { - pGpu->pmcRmOwnsIntrMask |= pIntrTable[i].pmcIntrMask; + pGpu->pmcRmOwnsIntrMask |= pEntry->pmcIntrMask; - if (pIntrTable[i].mcEngine != MC_ENGINE_IDX_TMR) + if (pEntry->mcEngine != MC_ENGINE_IDX_TMR) continue; } - if (pIntrTable[i].intrVector != NV_INTR_VECTOR_INVALID) + if (pEntry->intrVector != NV_INTR_VECTOR_INVALID) { - intrEnableLeaf_HAL(pGpu, pIntr, pIntrTable[i].intrVector); + intrEnableLeaf_HAL(pGpu, pIntr, pEntry->intrVector); } - if ((pIntrTable[i].intrVectorNonStall != NV_INTR_VECTOR_INVALID) && - !pIntrTable[i].bDisableNonStall) + if ((pEntry->intrVectorNonStall != NV_INTR_VECTOR_INVALID) + ) { - intrEnableLeaf_HAL(pGpu, pIntr, pIntrTable[i].intrVectorNonStall); + intrEnableLeaf_HAL(pGpu, pIntr, pEntry->intrVectorNonStall); } } @@ -183,6 +186,7 @@ // Disable all interrupts since we're unloading intrWriteRegTopEnClear_HAL(pGpu, pIntr, 0, 0xFFFFFFFF, NULL); + intrWriteRegTopEnClear_HAL(pGpu, pIntr, 1, 0xFFFFFFFF, NULL); _intrClearLeafEnables_TU102(pGpu, pIntr); @@ -203,45 +207,51 @@ ) { NV_STATUS status = NV_OK; - NvU32 leafEnHi, leafEnLo; - NvU32 uvmSharedLeafIdxStart = NV_CTRL_INTR_SUBTREE_TO_LEAF_IDX_START(NV_CPU_INTR_UVM_SHARED_SUBTREE_START); - NvU32 uvmSharedLeafIdxEnd = NV_CTRL_INTR_SUBTREE_TO_LEAF_IDX_END(NV_CPU_INTR_UVM_SHARED_SUBTREE_LAST); - NvU32 stallSubtreeLast = intrGetStallSubtreeLast_HAL(pGpu, pIntr); - NvU32 i; - // - // Compile time assert to make sure we have only one client shared subtree. - // The below code assumes that. - // - ct_assert(NV_CPU_INTR_UVM_SHARED_SUBTREE_START == NV_CPU_INTR_UVM_SHARED_SUBTREE_LAST); + { + NV2080_INTR_CATEGORY_SUBTREE_MAP uvmShared; + NV_ASSERT_OK_OR_RETURN( + intrGetSubtreeRange(pIntr, + NV2080_INTR_CATEGORY_UVM_SHARED, + &uvmShared)); + // + // Assert to make sure we have only one client shared subtree. + // The below code assumes that. + // + NV_ASSERT_OR_RETURN(uvmShared.subtreeStart == uvmShared.subtreeEnd, + NV_ERR_INVALID_STATE); - // Now cache the leaf enable mask for the subtree shared with the client - leafEnHi = intrReadRegLeafEnSet_HAL(pGpu, pIntr, uvmSharedLeafIdxStart, NULL); - leafEnLo = intrReadRegLeafEnSet_HAL(pGpu, pIntr, uvmSharedLeafIdxEnd, NULL); + // Now cache the leaf enable mask for the subtree shared with the client + NvU32 leafEnHi = intrReadRegLeafEnSet_HAL(pGpu, pIntr, + NV_CTRL_INTR_SUBTREE_TO_LEAF_IDX_START(uvmShared.subtreeStart), + NULL); + NvU32 leafEnLo = intrReadRegLeafEnSet_HAL(pGpu, pIntr, + NV_CTRL_INTR_SUBTREE_TO_LEAF_IDX_END(uvmShared.subtreeStart), + NULL); - pIntr->uvmSharedCpuLeafEn = ((NvU64)(leafEnHi) << 32) | leafEnLo; - pIntr->uvmSharedCpuLeafEnDisableMask = intrGetUvmSharedLeafEnDisableMask_HAL(pGpu, pIntr); + pIntr->uvmSharedCpuLeafEn = ((NvU64)(leafEnHi) << 32) | leafEnLo; + pIntr->uvmSharedCpuLeafEnDisableMask = + intrGetUvmSharedLeafEnDisableMask_HAL(pGpu, pIntr); + } // - // Cache the CPU_INTR_TOP_EN mask to clear when disabling stall interrupts - // (other interrupts are either not disabled or disabled selectively at leaf level) + // Cache the CPU_INTR_TOP_EN mask to clear when disabling stall + // interrupts (other interrupts are either not disabled or disabled + // selectively at leaf level) // - for (i = NV_CPU_INTR_STALL_SUBTREE_START; i <= stallSubtreeLast; i++) - { - pIntr->intrTopEnMask |= NVBIT(i); - } + pIntr->intrTopEnMask |= intrGetIntrTopLockedMask(pGpu, pIntr); OBJDISP *pDisp = GPU_GET_DISP(pGpu); // Cache client owned, shared interrupt, and display vectors for ease of use later pIntr->accessCntrIntrVector = intrGetVectorFromEngineId(pGpu, pIntr, MC_ENGINE_IDX_ACCESS_CNTR, NV_FALSE); - if (!gpuIsCCFeatureEnabled(pGpu)) + if (!gpuIsCCFeatureEnabled(pGpu) || !gpuIsGspOwnedFaultBuffersEnabled(pGpu)) { pIntr->replayableFaultIntrVector = intrGetVectorFromEngineId(pGpu, pIntr, MC_ENGINE_IDX_REPLAYABLE_FAULT, NV_FALSE); } else { - pIntr->replayableFaultIntrVector = NV_INTR_VECTOR_INVALID; + pIntr->replayableFaultIntrVector = intrGetVectorFromEngineId(pGpu, pIntr, MC_ENGINE_IDX_REPLAYABLE_FAULT_CPU, NV_FALSE); } if (pDisp != NULL) { @@ -270,20 +280,30 @@ } } - // - // Now ensure that they're in the expected subtree (check right now so we - // don't have to check later in latency critical paths where this is assumed - // to be true) - // - if (NV_CTRL_INTR_GPU_VECTOR_TO_SUBTREE(pIntr->accessCntrIntrVector) != NV_CPU_INTR_UVM_SUBTREE_START) - { - NV_PRINTF(LEVEL_ERROR, "UVM interrupt vectors for replayable fault and " - "access counter are in an unexpected subtree. Expected = 0x%x, actual = 0x%x\n", - NV_CPU_INTR_UVM_SUBTREE_START, - NV_CTRL_INTR_GPU_VECTOR_TO_SUBTREE(pIntr->accessCntrIntrVector)); - DBG_BREAKPOINT(); - status = NV_ERR_GENERIC; - goto exit; + { + // + // Now ensure that they're in the expected subtree (check right now so + // we don't have to check later in latency critical paths where this is + // assumed to be true) + // + NV2080_INTR_CATEGORY_SUBTREE_MAP uvmOwned; + NvU32 accessCntrSubtree = NV_CTRL_INTR_GPU_VECTOR_TO_SUBTREE( + pIntr->accessCntrIntrVector); + NV_ASSERT_OK_OR_RETURN( + intrGetSubtreeRange(pIntr, + NV2080_INTR_CATEGORY_UVM_OWNED, + &uvmOwned)); + if (!(uvmOwned.subtreeStart <= accessCntrSubtree && + accessCntrSubtree <= uvmOwned.subtreeEnd)) + { + NV_PRINTF(LEVEL_ERROR, + "UVM owned interrupt vector for access counter is in an unexpected subtree\n" + "Expected range = [0x%x, 0x%x], actual = 0x%x\n", + uvmOwned.subtreeStart, uvmOwned.subtreeEnd, accessCntrSubtree); + DBG_BREAKPOINT(); + status = NV_ERR_GENERIC; + goto exit; + } } exit: @@ -439,13 +459,13 @@ THREAD_STATE_NODE *pThreadState ) { - NvU32 val, idx; + NvU32 idx; // // 1. Enable the UVM interrupts that RM currently owns at INTR_LEAF // level. // - val = _intrGetUvmLeafMask_TU102(pGpu, pIntr); + NvU32 val = _intrGetUvmLeafMask_TU102(pGpu, pIntr); idx = NV_CTRL_INTR_GPU_VECTOR_TO_LEAF_REG(pIntr->accessCntrIntrVector); if (val != 0) { @@ -457,12 +477,18 @@ // level, based on the cached value. // - // - // Compile time assert to make sure we have only one client shared subtree. - // The below code assumes that. - // - ct_assert(NV_CPU_INTR_UVM_SHARED_SUBTREE_START == NV_CPU_INTR_UVM_SHARED_SUBTREE_LAST); - idx = NV_CPU_INTR_UVM_SHARED_SUBTREE_START; + { + NV2080_INTR_CATEGORY_SUBTREE_MAP uvmShared; + NV_ASSERT_OK(intrGetSubtreeRange(pIntr, + NV2080_INTR_CATEGORY_UVM_SHARED, + &uvmShared)); + // + // Assert to make sure we have only one client shared subtree. + // The below code assumes that. + // + NV_ASSERT(uvmShared.subtreeStart == uvmShared.subtreeEnd); + idx = uvmShared.subtreeStart; + } if (NvU64_HI32(pIntr->uvmSharedCpuLeafEn) != 0) { @@ -482,15 +508,30 @@ // We use the assumption that 1 == ENABLE below ct_assert(NV_VIRTUAL_FUNCTION_PRIV_CPU_INTR_TOP_EN_SET_SUBTREE_ENABLE == 1); - // - // 3. Enable all interrupt subtrees (except nonstall) at top level. Nonstall - // enablement is handled by a different function. - // - val = 0xFFFFFFFF; + { + // + // 3. Enable all interrupt subtrees (except nonstall) at top level. + // Nonstall enablement is handled by a different function. + // + NvU64 mask = NV_U64_MAX; - val &= ~intrGetIntrTopNonStallMask_HAL(pGpu, pIntr); + mask &= ~intrGetIntrTopNonStallMask_HAL(pGpu, pIntr); - intrWriteRegTopEnSet_HAL(pGpu, pIntr, 0, val, pThreadState); + if (NvU64_LO32(mask) != 0) + { + intrWriteRegTopEnSet_HAL(pGpu, pIntr, + 0, + NvU64_LO32(mask), + pThreadState); + } + if (NvU64_HI32(mask) != 0) + { + intrWriteRegTopEnSet_HAL(pGpu, pIntr, + 1, + NvU64_HI32(mask), + pThreadState); + } + } } /*! @@ -525,12 +566,18 @@ // level, except the ones that can be handled outside the GPU lock. // - // - // Compile time assert to make sure we have only one client shared subtree. - // The below code assumes that. - // - ct_assert(NV_CPU_INTR_UVM_SHARED_SUBTREE_START == NV_CPU_INTR_UVM_SHARED_SUBTREE_LAST); - idx = NV_CPU_INTR_UVM_SHARED_SUBTREE_START; + { + NV2080_INTR_CATEGORY_SUBTREE_MAP uvmShared; + NV_ASSERT_OK(intrGetSubtreeRange(pIntr, + NV2080_INTR_CATEGORY_UVM_SHARED, + &uvmShared)); + // + // Assert to make sure we have only one client shared subtree. + // The below code assumes that. + // + NV_ASSERT(uvmShared.subtreeStart == uvmShared.subtreeEnd); + idx = uvmShared.subtreeStart; + } if (!gpuIsStateLoaded(pGpu)) { @@ -588,7 +635,20 @@ // 3. Disable some interrupt subtrees at top level (information about which // ones to disable is cached in pIntr->intrTopEnMask) // - intrWriteRegTopEnClear_HAL(pGpu, pIntr, 0, pIntr->intrTopEnMask, pThreadState); + if (NvU64_LO32(pIntr->intrTopEnMask) != 0) + { + intrWriteRegTopEnClear_HAL(pGpu, pIntr, + 0, + NvU64_LO32(pIntr->intrTopEnMask), + pThreadState); + } + if (NvU64_HI32(pIntr->intrTopEnMask) != 0) + { + intrWriteRegTopEnClear_HAL(pGpu, pIntr, + 1, + NvU64_HI32(pIntr->intrTopEnMask), + pThreadState); + } } /*! @@ -662,7 +722,7 @@ NvBool bRmOwnsReplayableFault = !!(pKernelGmmu->uvmSharedIntrRmOwnsMask & RM_UVM_SHARED_INTR_MASK_MMU_REPLAYABLE_FAULT_NOTIFY); NvBool bRmOwnsAccessCntr = !!(pKernelGmmu->uvmSharedIntrRmOwnsMask & RM_UVM_SHARED_INTR_MASK_HUB_ACCESS_COUNTER_NOTIFY); - if (bRmOwnsReplayableFault && !gpuIsCCFeatureEnabled(pGpu)) + if (bRmOwnsReplayableFault) { val |= NVBIT(NV_CTRL_INTR_GPU_VECTOR_TO_LEAF_BIT(pIntr->replayableFaultIntrVector)); } @@ -696,6 +756,7 @@ NvU32 intrVectorNonReplayableFault; NvU32 intrVectorFifoNonstall = NV_INTR_VECTOR_INVALID; NvU64 mask = 0; + NV2080_INTR_CATEGORY_SUBTREE_MAP uvmShared; // GSP RM services both MMU non-replayable fault and FIFO interrupts if (IS_GSP_CLIENT(pGpu)) @@ -719,22 +780,28 @@ NV_CTRL_INTR_GPU_VECTOR_TO_LEAF_REG(intrVectorFifoNonstall)); } - // Ascertain that they're in the first leaf - NV_ASSERT(NV_CTRL_INTR_GPU_VECTOR_TO_LEAF_REG(intrVectorNonReplayableFault) == - NV_CTRL_INTR_SUBTREE_TO_LEAF_IDX_START(NV_CPU_INTR_UVM_SHARED_SUBTREE_START)); - + NV_ASSERT_OK(intrGetSubtreeRange(pIntr, + NV2080_INTR_CATEGORY_UVM_SHARED, + &uvmShared)); // - // Compile-time ascertain that we only have 1 client subtree (we assume + // Ascertain that we only have 1 client subtree (we assume // this since we cache only 64 bits). // - ct_assert(NV_CPU_INTR_UVM_SHARED_SUBTREE_START == NV_CPU_INTR_UVM_SHARED_SUBTREE_LAST); + NV_ASSERT(uvmShared.subtreeStart == uvmShared.subtreeEnd); // - // Compile-time ascertain that we only have 2 subtrees as this is what we currently support - // by only caching 64 bits + // Ascertain that we only have 2 subtrees as this is what we currently + // support by only caching 64 bits // - ct_assert((NV_CTRL_INTR_SUBTREE_TO_LEAF_IDX_END(NV_CPU_INTR_UVM_SHARED_SUBTREE_LAST) - 1) == - NV_CTRL_INTR_SUBTREE_TO_LEAF_IDX_START(NV_CPU_INTR_UVM_SHARED_SUBTREE_START)); + NV_ASSERT( + (NV_CTRL_INTR_SUBTREE_TO_LEAF_IDX_END(uvmShared.subtreeEnd) - 1) == + NV_CTRL_INTR_SUBTREE_TO_LEAF_IDX_START(uvmShared.subtreeStart)); + + + // Ascertain that they're in the first leaf + NV_ASSERT( + NV_CTRL_INTR_GPU_VECTOR_TO_LEAF_REG(intrVectorNonReplayableFault) == + NV_CTRL_INTR_SUBTREE_TO_LEAF_IDX_START(uvmShared.subtreeStart)); mask |= NVBIT64(NV_CTRL_INTR_GPU_VECTOR_TO_LEAF_BIT(intrVectorNonReplayableFault)); @@ -767,15 +834,16 @@ THREAD_STATE_NODE *pThreadState ) { - INTR_TABLE_ENTRY *pIntrTable; KernelGmmu *pKernelGmmu = GPU_GET_KERNEL_GMMU(pGpu); - NvU32 intrTableSz, i; - - NvU32 stallSubtreeLast = intrGetStallSubtreeLast_HAL(pGpu, pIntr); + InterruptTable *pIntrTable; + InterruptTableIter iter; + NvU64 sanityCheckSubtreeMask = 0; NvU32 numIntrLeaves = intrGetNumLeaves_HAL(pGpu, pIntr); NV_ASSERT(numIntrLeaves <= NV_MAX_INTR_LEAVES); NvU32 intrLeafValues[NV_MAX_INTR_LEAVES]; + sanityCheckSubtreeMask = intrGetIntrTopLegacyStallMask(pIntr); + portMemSet(intrLeafValues, 0, numIntrLeaves * sizeof(NvU32)); bitVectorClrAll(pEngines); @@ -786,14 +854,15 @@ } NV_ASSERT_OK_OR_RETURN(intrGetLeafStatus_HAL(pGpu, pIntr, intrLeafValues, pThreadState)); - NV_ASSERT_OK_OR_RETURN(intrGetInterruptTable_HAL(pGpu, pIntr, &pIntrTable, &intrTableSz)); + NV_ASSERT_OK_OR_RETURN(intrGetInterruptTable_HAL(pGpu, pIntr, &pIntrTable)); - for (i = 0; i < intrTableSz; i++) + for (iter = vectIterAll(pIntrTable); vectIterNext(&iter);) { - NvU32 intrVector; - NvU32 leaf, leafIndex, leafBit; - - intrVector = pIntrTable[i].intrVector; + INTR_TABLE_ENTRY *pEntry = iter.pValue; + NvU32 intrVector = pEntry->intrVector; + NvU32 leaf; + NvU32 leafIndex; + NvU32 leafBit; // Check if this engine has a valid stalling interrupt vector in the new tree if (intrVector == NV_INTR_VECTOR_INVALID) @@ -810,10 +879,14 @@ // is only to catch issues during code development. Should never happen // in practice // - if ((leafIndex < NV_CTRL_INTR_SUBTREE_TO_LEAF_IDX_START(NV_CPU_INTR_UVM_SUBTREE_START)) || - (leafIndex > NV_CTRL_INTR_SUBTREE_TO_LEAF_IDX_END(stallSubtreeLast))) + + if ((sanityCheckSubtreeMask & + NVBIT64(NV_CTRL_INTR_LEAF_IDX_TO_SUBTREE(leafIndex))) == 0) { - NV_PRINTF(LEVEL_ERROR, "MC_ENGINE_IDX %u has invalid stall intr vector %u\n", pIntrTable[i].mcEngine, intrVector); + NV_PRINTF(LEVEL_ERROR, + "MC_ENGINE_IDX %u has invalid stall intr vector %u\n", + pEntry->mcEngine, + intrVector); DBG_BREAKPOINT(); continue; } @@ -833,7 +906,7 @@ } // Add engine to bitvector - bitVectorSet(pEngines, pIntrTable[i].mcEngine); + bitVectorSet(pEngines, pEntry->mcEngine); } if (pKernelGmmu != NULL) @@ -906,8 +979,7 @@ Intr *pIntr ) { - NvU32 val = 0; - NvU32 i; + NvU64 mask = 0; // We use the assumption that 1 == DISABLE below ct_assert(NV_VIRTUAL_FUNCTION_PRIV_CPU_INTR_TOP_EN_CLEAR_SUBTREE_DISABLE == 1); @@ -923,28 +995,53 @@ // 1. If the alternate tree (nonstall tree) is handled "lockless", it // is not disabled during RM lock acquire, so needs re-arming. // - val |= intrGetIntrTopNonStallMask_HAL(pGpu, pIntr); + mask |= intrGetIntrTopNonStallMask_HAL(pGpu, pIntr); } - // // 2. UVM-owned interrupt tree (never disabled at top level) + mask |= intrGetIntrTopCategoryMask(pIntr, NV2080_INTR_CATEGORY_UVM_OWNED); + // 3. UVM/RM shared interrupt tree (never disabled at top level) - // - for (i = NV_CPU_INTR_UVM_SUBTREE_START; i <= NV_CPU_INTR_UVM_SHARED_SUBTREE_LAST; i++) - { - val |= NVBIT(i); - } + mask |= intrGetIntrTopCategoryMask(pIntr, NV2080_INTR_CATEGORY_UVM_SHARED); // // Bypass GPU_REG_WR32 that requires the GPU lock to be held (for some // register filters) by using the OS interface directly. // - osGpuWriteReg032(pGpu, - GPU_GET_VREG_OFFSET(pGpu, NV_VIRTUAL_FUNCTION_PRIV_CPU_INTR_TOP_EN_CLEAR(0)), - val); - osGpuWriteReg032(pGpu, - GPU_GET_VREG_OFFSET(pGpu, NV_VIRTUAL_FUNCTION_PRIV_CPU_INTR_TOP_EN_SET(0)), - val); + // Clear all first, then set + // + if (NvU64_LO32(mask) != 0 && + 0 < NV_VIRTUAL_FUNCTION_PRIV_CPU_INTR_TOP_EN_CLEAR__SIZE_1) + { + osGpuWriteReg032(pGpu, + GPU_GET_VREG_OFFSET(pGpu, + NV_VIRTUAL_FUNCTION_PRIV_CPU_INTR_TOP_EN_CLEAR(0)), + NvU64_LO32(mask)); + } + if (NvU64_HI32(mask) != 0 && + 1 < NV_VIRTUAL_FUNCTION_PRIV_CPU_INTR_TOP_EN_CLEAR__SIZE_1) + { + osGpuWriteReg032(pGpu, + GPU_GET_VREG_OFFSET(pGpu, + NV_VIRTUAL_FUNCTION_PRIV_CPU_INTR_TOP_EN_CLEAR(1)), + NvU64_HI32(mask)); + } + if (NvU64_LO32(mask) != 0 && + 0 < NV_VIRTUAL_FUNCTION_PRIV_CPU_INTR_TOP_EN_SET__SIZE_1) + { + osGpuWriteReg032(pGpu, + GPU_GET_VREG_OFFSET(pGpu, + NV_VIRTUAL_FUNCTION_PRIV_CPU_INTR_TOP_EN_SET(0)), + NvU64_LO32(mask)); + } + if (NvU64_HI32(mask) != 0 && + 1 < NV_VIRTUAL_FUNCTION_PRIV_CPU_INTR_TOP_EN_SET__SIZE_1) + { + osGpuWriteReg032(pGpu, + GPU_GET_VREG_OFFSET(pGpu, + NV_VIRTUAL_FUNCTION_PRIV_CPU_INTR_TOP_EN_SET(1)), + NvU64_HI32(mask)); + } } /*! @@ -967,11 +1064,8 @@ NvU32 subtreeIndex; NvU32 leafIndex; - // Read all the stalling interrupt leaf status - NvU32 stallSubtreeLast = intrGetStallSubtreeLast_HAL(pGpu, pIntr); - NV_ASSERT_OR_RETURN(NV_CPU_INTR_UVM_SUBTREE_START <= stallSubtreeLast, NV_ERR_INVALID_STATE); - subtreeIndex = NV_CPU_INTR_UVM_SUBTREE_START; - for (; subtreeIndex <= stallSubtreeLast; subtreeIndex++) + FOR_EACH_INDEX_IN_MASK(64, subtreeIndex, + intrGetIntrTopLegacyStallMask(pIntr)) { leafIndex = NV_CTRL_INTR_SUBTREE_TO_LEAF_IDX_START(subtreeIndex); if (pIntr->getProperty(pIntr, PDB_PROP_INTR_READ_ONLY_EVEN_NUMBERED_INTR_LEAF_REGS)) @@ -989,7 +1083,7 @@ pLeafVals[leafIndex] = intrReadRegLeaf_HAL(pGpu, pIntr, leafIndex, pThreadState); } } - } + } FOR_EACH_INDEX_IN_MASK_END return NV_OK; } @@ -1016,6 +1110,8 @@ THREAD_STATE_NODE *pThreadState ) { + KernelDisplay *pKernelDisplay = GPU_GET_KERNEL_DISPLAY(pGpu); + bitVectorClrAll(pEngines); if (IS_GPU_GC6_STATE_ENTERED(pGpu)) @@ -1028,6 +1124,14 @@ return NV_ERR_GPU_IS_LOST; } + if (pKernelDisplay != NULL && kdispGetDeferredVblankHeadMask(pKernelDisplay)) + { + // Deferred vblank is pending which we need to handle + bitVectorSet(pEngines, MC_ENGINE_IDX_DISP); + // Nothing else to set here, return early + return NV_OK; + } + if (pIntr->displayIntrVector == NV_INTR_VECTOR_INVALID) { return NV_OK; @@ -1099,10 +1203,10 @@ Intr *pIntr ) { - INTR_TABLE_ENTRY *pIntrTable; - NvU32 intrTableSz = 0; - NvU32 i; - NvU32 intrLeafSize = intrGetLeafSize_HAL(pGpu, pIntr); + InterruptTable *pIntrTable; + InterruptTableIter iter; + NvU32 i; + NvU32 intrLeafSize = intrGetLeafSize_HAL(pGpu, pIntr); NV_PRINTF(LEVEL_INFO, "Interrupt registers:\n"); for (i = 0; i < NV_VIRTUAL_FUNCTION_PRIV_CPU_INTR_TOP__SIZE_1; i++) @@ -1118,28 +1222,54 @@ } NV_PRINTF(LEVEL_INFO, "MC Interrupt table:\n"); - intrGetInterruptTable_HAL(pGpu, pIntr, &pIntrTable, &intrTableSz); + intrGetInterruptTable_HAL(pGpu, pIntr, &pIntrTable); - for (i = 0; i < intrTableSz; i++) + for (i = 0, iter = vectIterAll(pIntrTable); vectIterNext(&iter); i++) { + INTR_TABLE_ENTRY *pEntry = iter.pValue; + PORT_UNREFERENCED_VARIABLE(pEntry); + NV_PRINTF(LEVEL_INFO, - "%2u: mcEngineIdx=%-4u intrVector=%-10u intrVectorNonStall=%-10u bDisableNonStall=%u\n", i, - pIntrTable[i].mcEngine, - pIntrTable[i].intrVector, - pIntrTable[i].intrVectorNonStall, - pIntrTable[i].bDisableNonStall); + "%2u: mcEngineIdx=%-4u intrVector=%-10u intrVectorNonStall=%-10u\n", + i, + pEntry->mcEngine, + pEntry->intrVector, + pEntry->intrVectorNonStall); } } -/*! - * @brief Gets the stall subtree end index - */ -NvU32 -intrGetStallSubtreeLast_TU102(OBJGPU *pGpu, Intr *pIntr) + +NV_STATUS +intrInitSubtreeMap_TU102 +( + OBJGPU *pGpu, + Intr *pIntr +) { - return NV_CPU_INTR_STALL_SUBTREE_LAST; + NV2080_INTR_CATEGORY_SUBTREE_MAP *pCategoryEngine = + &pIntr->subtreeMap[NV2080_INTR_CATEGORY_ESCHED_DRIVEN_ENGINE]; + pCategoryEngine->subtreeStart = NV_CPU_INTR_STALL_SUBTREE_START; + pCategoryEngine->subtreeEnd = NV_CPU_INTR_STALL_SUBTREE_LAST; + + NV2080_INTR_CATEGORY_SUBTREE_MAP *pCategoryEngineNotification = + &pIntr->subtreeMap[NV2080_INTR_CATEGORY_ESCHED_DRIVEN_ENGINE_NOTIFICATION]; + pCategoryEngineNotification->subtreeStart = NV_VIRTUAL_FUNCTION_PRIV_CPU_INTR_TOP_SUBTREE(0); + pCategoryEngineNotification->subtreeEnd = NV_VIRTUAL_FUNCTION_PRIV_CPU_INTR_TOP_SUBTREE(0); + + NV2080_INTR_CATEGORY_SUBTREE_MAP *pCategoryUvmOwned = + &pIntr->subtreeMap[NV2080_INTR_CATEGORY_UVM_OWNED]; + pCategoryUvmOwned->subtreeStart = NV_CPU_INTR_UVM_SUBTREE_START; + pCategoryUvmOwned->subtreeEnd = NV_CPU_INTR_UVM_SUBTREE_LAST; + + NV2080_INTR_CATEGORY_SUBTREE_MAP *pCategoryUvmShared = + &pIntr->subtreeMap[NV2080_INTR_CATEGORY_UVM_SHARED]; + pCategoryUvmShared->subtreeStart = NV_CPU_INTR_UVM_SHARED_SUBTREE_START; + pCategoryUvmShared->subtreeEnd = NV_CPU_INTR_UVM_SHARED_SUBTREE_LAST; + + return NV_OK; } + /*! * @brief Gets the number of leaf registers used */ @@ -1159,12 +1289,15 @@ return NV_VIRTUAL_FUNCTION_PRIV_CPU_INTR_LEAF__SIZE_1; } -/*! - * @brief Gets the mask of INTR_TOP that covers nonstall interrupts - */ -NvU32 -intrGetIntrTopNonStallMask_TU102(OBJGPU *pGpu, Intr *pIntr) + +NvU64 +intrGetIntrTopNonStallMask_TU102 +( + OBJGPU *pGpu, + Intr *pIntr +) { + // TODO Bug 3823562 Remove these asserts // Compile-time assert against the highest set bit that will be returned #define NV_CPU_INTR_NOSTALL_SUBTREE_HIGHEST NV_VIRTUAL_FUNCTION_PRIV_CPU_INTR_TOP_SUBTREE(0) @@ -1172,9 +1305,20 @@ ct_assert(NV_CPU_INTR_NOSTALL_SUBTREE_HIGHEST < NV_VIRTUAL_FUNCTION_PRIV_CPU_INTR_LEAF_EN_SET__SIZE_1); ct_assert(NV_CPU_INTR_NOSTALL_SUBTREE_HIGHEST < NV_VIRTUAL_FUNCTION_PRIV_CPU_INTR_LEAF_EN_CLEAR__SIZE_1); - return NVBIT32(NV_VIRTUAL_FUNCTION_PRIV_CPU_INTR_TOP_SUBTREE(0)); + NvU64 mask = intrGetIntrTopCategoryMask(pIntr, + NV2080_INTR_CATEGORY_ESCHED_DRIVEN_ENGINE_NOTIFICATION); + + // + // On all Ampere+ that use this TU102 HAL, Esched notification interrupts + // are also included in this if PDB_PROP_GPU_SWRL_GRANULAR_LOCKING is set. + // + + // Sanity check that Intr.subtreeMap is initialized + NV_ASSERT(mask != 0); + return mask; } + /*! * @brief Decode the interrupt mode for SW to use * diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/kernel/gpu/intr/intr.c nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/kernel/gpu/intr/intr.c --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/kernel/gpu/intr/intr.c 2023-10-25 20:21:08.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/kernel/gpu/intr/intr.c 2024-03-05 22:13:32.000000000 +0000 @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 1993-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 1993-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -41,6 +41,7 @@ #include "nv_ref.h" #include "nvRmReg.h" +#include "nvmisc.h" // @@ -56,6 +57,23 @@ static NvBool _intrServiceStallExactList(OBJGPU *pGpu, Intr *pIntr, MC_ENGINE_BITVECTOR *pEngines); static void _intrInitServiceTable(OBJGPU *pGpu, Intr *pIntr); + +NV_STATUS +intrGetSubtreeRange_IMPL +( + Intr *pIntr, + NV2080_INTR_CATEGORY category, + NV2080_INTR_CATEGORY_SUBTREE_MAP *pRange +) +{ + NV_ASSERT_OR_RETURN(pRange != NULL, NV_ERR_INVALID_ARGUMENT); + NV_ASSERT_OR_RETURN(category < NV2080_INTR_CATEGORY_ENUM_COUNT, + NV_ERR_INVALID_ARGUMENT); + *pRange = pIntr->subtreeMap[category]; + return NV_OK; +} + + void intrServiceStall_IMPL(OBJGPU *pGpu, Intr *pIntr) { @@ -138,7 +156,7 @@ Intr *pIntr = GPU_GET_INTR(pGpu); MC_ENGINE_BITVECTOR engines; NvBool bMIGInUse = IS_MIG_IN_USE(pGpu); - NvHandle hClient = RES_GET_CLIENT_HANDLE(pSubdevice); + Device *pDevice = GPU_RES_GET_DEVICE(pSubdevice); bitVectorClrAll(&engines); @@ -148,6 +166,16 @@ RmCtrlParams *pRmCtrlParams = pCallContext->pControlParams; NV_STATUS status = NV_OK; + // + // Force kernel-RM to service interrupts from GSP-RM. This will allow + // kernel-RM to write notifiers and send an ack back to GSP. + // GSP waits for this ack before clearing fast path POSSIBLE_ERR interrupt. + // + if (pGpu->getProperty(pGpu, PDB_PROP_GPU_FASTPATH_SEQ_ENABLED)) + { + intrServiceStallSingle_HAL(pGpu, pIntr, MC_ENGINE_IDX_GSP, NV_TRUE); + } + NV_RM_RPC_CONTROL(pGpu, pRmCtrlParams->hClient, pRmCtrlParams->hObject, pRmCtrlParams->cmd, pRmCtrlParams->pParams, pRmCtrlParams->paramsSize, status); if (status != NV_OK) @@ -177,7 +205,7 @@ NvU32 i; NV_ASSERT_OK_OR_RETURN( - kmigmgrGetInstanceRefFromClient(pGpu, pKernelMIGManager, hClient, &ref)); + kmigmgrGetInstanceRefFromDevice(pGpu, pKernelMIGManager, pDevice, &ref)); // Compute instances always contain 1 GR grCount = 1; @@ -525,30 +553,23 @@ NvBool bNonStall ) { - INTR_TABLE_ENTRY *pIntrTable; - NvU32 intrTableSz; - NvU32 i; - NV_STATUS status; + InterruptTable *pIntrTable; + InterruptTableIter iter; + NV_STATUS status; - status = intrGetInterruptTable_HAL(pGpu, pIntr, &pIntrTable, &intrTableSz); + status = intrGetInterruptTable_HAL(pGpu, pIntr, &pIntrTable); if (status != NV_OK) { NV_ASSERT_OK_FAILED("Failed to get interrupt table", status); return NV_INTR_VECTOR_INVALID; } - for (i = 0; i < intrTableSz; i++) + for (iter = vectIterAll(pIntrTable); vectIterNext(&iter);) { - if (pIntrTable[i].mcEngine == mcEngineId) + INTR_TABLE_ENTRY *pEntry = iter.pValue; + if (pEntry->mcEngine == mcEngineId) { - if (bNonStall) - { - return pIntrTable[i].intrVectorNonStall; - } - else - { - return pIntrTable[i].intrVector; - } + return bNonStall ? pEntry->intrVectorNonStall : pEntry->intrVector; } } @@ -574,22 +595,22 @@ PMC_ENGINE_BITVECTOR engineMask ) { - INTR_TABLE_ENTRY *pIntrTable; - NvU32 intrTableSz; - NvU32 i; - NvU32 pmcIntrMask = 0; + InterruptTable *pIntrTable; + InterruptTableIter iter; + NvU32 pmcIntrMask = 0; - if (NV_OK != intrGetInterruptTable_HAL(pGpu, pIntr, &pIntrTable, &intrTableSz)) + if (NV_OK != intrGetInterruptTable_HAL(pGpu, pIntr, &pIntrTable)) { NV_ASSERT(pmcIntrMask); return pmcIntrMask; } - for (i = 0; i < intrTableSz; i++) + for (iter = vectIterAll(pIntrTable); vectIterNext(&iter);) { - if (bitVectorTest(engineMask, pIntrTable[i].mcEngine)) + INTR_TABLE_ENTRY *pEntry = iter.pValue; + if (bitVectorTest(engineMask, pEntry->mcEngine)) { - pmcIntrMask |= pIntrTable[i].pmcIntrMask; + pmcIntrMask |= pEntry->pmcIntrMask; } } @@ -613,24 +634,25 @@ PMC_ENGINE_BITVECTOR pEngines ) { - INTR_TABLE_ENTRY *pIntrTable; - NvU32 intrTableSz; - NvU32 i; + InterruptTable *pIntrTable; + InterruptTableIter iter; NV_ASSERT_OR_RETURN_VOID(pEngines != NULL); - NV_ASSERT_OR_RETURN_VOID(intrGetInterruptTable_HAL(pGpu, pIntr, &pIntrTable, &intrTableSz) == NV_OK); + NV_ASSERT_OR_RETURN_VOID( + intrGetInterruptTable_HAL(pGpu, pIntr, &pIntrTable) == NV_OK); bitVectorClrAll(pEngines); - for (i = 0; i < intrTableSz; i++) + for (iter = vectIterAll(pIntrTable); vectIterNext(&iter);) { - if (pIntrTable[i].pmcIntrMask == NV_PMC_INTR_INVALID_MASK) + INTR_TABLE_ENTRY *pEntry = iter.pValue; + if (pEntry->pmcIntrMask == NV_PMC_INTR_INVALID_MASK) { continue; } - if (pIntrTable[i].pmcIntrMask & pmcIntrMask) + if (pEntry->pmcIntrMask & pmcIntrMask) { - bitVectorSet(pEngines, pIntrTable[i].mcEngine); + bitVectorSet(pEngines, pEntry->mcEngine); } } } @@ -643,28 +665,24 @@ NV_STATUS intrGetSmallestNotificationVector_IMPL ( - OBJGPU *pGpu, - Intr *pIntr, - NvU32 *pSmallestVector + OBJGPU *pGpu, + Intr *pIntr, + NvU32 *pSmallestVector ) { - INTR_TABLE_ENTRY *pIntrTable; - NvU32 intrTableSz; - NvU32 i, leafIdx; - NvU32 val = NV_INTR_VECTOR_INVALID; + InterruptTable *pIntrTable; + InterruptTableIter iter; + NvU32 val = NV_INTR_VECTOR_INVALID; + NV_ASSERT_OR_RETURN(pSmallestVector != NULL, NV_ERR_INVALID_ARGUMENT); *pSmallestVector = val; - NV_ASSERT_OR_RETURN(pSmallestVector != NULL, NV_ERR_INVALID_ARGUMENT); - NV_ASSERT_OK_OR_RETURN(intrGetInterruptTable_HAL(pGpu, pIntr, &pIntrTable, &intrTableSz)); + NV_ASSERT_OK_OR_RETURN(intrGetInterruptTable_HAL(pGpu, pIntr, &pIntrTable)); - for (i = 0; i < intrTableSz; i++) + for (iter = vectIterAll(pIntrTable); vectIterNext(&iter);) { - NvU32 curVector = pIntrTable[i].intrVectorNonStall; - if (curVector < val) - { - val = curVector; - } + val = NV_MIN(val, + ((INTR_TABLE_ENTRY *)iter.pValue)->intrVectorNonStall); } // @@ -672,8 +690,9 @@ // This should be consistent across all chips even if they have different // floorsweeping configs // - leafIdx = NV_CTRL_INTR_SUBTREE_TO_LEAF_IDX_START(NV_CTRL_INTR_GPU_VECTOR_TO_SUBTREE(val)); - *pSmallestVector = NV_CTRL_INTR_LEAF_IDX_TO_GPU_VECTOR_START(leafIdx); + *pSmallestVector = NV_CTRL_INTR_LEAF_IDX_TO_GPU_VECTOR_START( + NV_CTRL_INTR_SUBTREE_TO_LEAF_IDX_START( + NV_CTRL_INTR_GPU_VECTOR_TO_SUBTREE(val))); return NV_OK; } @@ -720,6 +739,7 @@ return NV_OK; } + void intrDestruct_IMPL ( @@ -735,31 +755,43 @@ pNode = intrDequeueDpc(pGpu, pIntr, pDPCQueue); portMemFree(pNode); } + } NV_STATUS intrStateInitUnlocked_IMPL ( - OBJGPU *pGpu, - Intr *pIntr) + OBJGPU *pGpu, + Intr *pIntr +) { NvU32 data = 0; + NvU32 i; if (osReadRegistryDword(pGpu, NV_REG_STR_RM_INTR_DETAILED_LOGS, &data) == NV_OK) { if (data == NV_REG_STR_RM_INTR_DETAILED_LOGS_ENABLE) { - pIntr->setProperty(pIntr, PDB_PROP_INTR_ENABLE_DETAILED_LOGS, NV_TRUE); + pIntr->setProperty(pIntr, + PDB_PROP_INTR_ENABLE_DETAILED_LOGS, + NV_TRUE); } } _intrInitRegistryOverrides(pGpu, pIntr); + for (i = 0; i < NV_ARRAY_ELEMENTS(pIntr->subtreeMap); ++i) + { + pIntr->subtreeMap[i].subtreeStart = NV2080_INTR_INVALID_SUBTREE; + pIntr->subtreeMap[i].subtreeEnd = NV2080_INTR_INVALID_SUBTREE; + } + return NV_OK; } + NV_STATUS intrStateInitLocked_IMPL ( @@ -767,6 +799,7 @@ Intr *pIntr ) { + NV_STATUS status = NV_OK; // Enable interrupts in the HAL pIntr->halIntrEnabled = NV_TRUE; @@ -784,7 +817,7 @@ pKernelGmmu->uvmSharedIntrRmOwnsMask = RM_UVM_SHARED_INTR_MASK_ALL; } - NV_ASSERT_OK_OR_RETURN(intrInitInterruptTable_HAL(pGpu, pIntr)); + NV_ASSERT_OK_OR_GOTO(status, intrInitInterruptTable_HAL(pGpu, pIntr), exit); _intrInitServiceTable(pGpu, pIntr); if (pIntr->getProperty(pIntr, PDB_PROP_INTR_USE_INTR_MASK_FOR_LOCKING)) @@ -803,7 +836,9 @@ // Hypervisor will set the intr unblocked mask later at the time of SWRL init. } - return NV_OK; +exit: + + return status; } void @@ -943,61 +978,57 @@ intrInitInterruptTable_KERNEL ( OBJGPU *pGpu, - Intr *pIntr + Intr *pIntr ) { - RM_API *pRmApi = GPU_GET_PHYSICAL_RMAPI(pGpu); + RM_API *pRmApi = GPU_GET_PHYSICAL_RMAPI(pGpu); NV_STATUS status = NV_OK; - NvU32 i = 0; - INTR_TABLE_ENTRY *pIntrTable = NULL; + NvU32 i; NV2080_CTRL_INTERNAL_INTR_GET_KERNEL_TABLE_PARAMS *pParams; - NV_ASSERT_OR_RETURN(pIntr->pIntrTable == NULL, NV_ERR_INVALID_STATE); + NV_ASSERT_OR_RETURN(vectIsEmpty(&pIntr->intrTable), NV_ERR_INVALID_STATE); pParams = portMemAllocNonPaged(sizeof(*pParams)); - if (pParams == NULL) - { - NV_PRINTF(LEVEL_ERROR, "Could not allocate params for kernel intr table control"); - status = NV_ERR_NO_MEMORY; - goto exit; - } + NV_ASSERT_TRUE_OR_GOTO(status, pParams != NULL, NV_ERR_NO_MEMORY, exit); NV_ASSERT_OK_OR_GOTO(status, - pRmApi->Control(pRmApi, pGpu->hInternalClient, pGpu->hInternalSubdevice, + pRmApi->Control(pRmApi, + pGpu->hInternalClient, + pGpu->hInternalSubdevice, NV2080_CTRL_CMD_INTERNAL_INTR_GET_KERNEL_TABLE, - pParams, sizeof(*pParams)), + pParams, + sizeof *pParams), exit); + NV_ASSERT_TRUE_OR_GOTO(status, + pParams->tableLen <= + NV2080_CTRL_INTERNAL_INTR_MAX_TABLE_SIZE, + NV_ERR_OUT_OF_RANGE, + exit); - status = NV_ERR_INVALID_PARAMETER; - NV_ASSERT_OR_GOTO(pParams->tableLen <= NV2080_CTRL_INTERNAL_INTR_MAX_TABLE_SIZE, exit); - - pIntrTable = portMemAllocNonPaged(sizeof(INTR_TABLE_ENTRY) * pParams->tableLen); - if (pIntrTable == NULL) - { - NV_PRINTF(LEVEL_ERROR, "Could not allocate kernel interrupt table"); - status = NV_ERR_NO_MEMORY; - goto exit; - } - portMemSet(pIntrTable, 0, sizeof(INTR_TABLE_ENTRY) * pParams->tableLen); - + NV_ASSERT_OK_OR_GOTO(status, + vectInit(&pIntr->intrTable, + portMemAllocatorGetGlobalNonPaged(), + pParams->tableLen), + exit); for (i = 0; i < pParams->tableLen; ++i) { - pIntrTable[i].mcEngine = pParams->table[i].engineIdx; - pIntrTable[i].pmcIntrMask = pParams->table[i].pmcIntrMask; - pIntrTable[i].intrVector = pParams->table[i].vectorStall; - pIntrTable[i].intrVectorNonStall = pParams->table[i].vectorNonStall; + INTR_TABLE_ENTRY entry = {0}; + entry.mcEngine = pParams->table[i].engineIdx; + entry.pmcIntrMask = pParams->table[i].pmcIntrMask; + entry.intrVector = pParams->table[i].vectorStall; + entry.intrVectorNonStall = pParams->table[i].vectorNonStall; + NV_ASSERT_TRUE_OR_GOTO(status, + vectAppend(&pIntr->intrTable, &entry) != NULL, + NV_ERR_NO_MEMORY, + exit); } + NV_ASSERT_OK_OR_GOTO(status, vectTrim(&pIntr->intrTable, 0), exit); - // Transfer ownership of allocated table to pIntr and clear local to avoid MemFree - pIntr->pIntrTable = pIntrTable; - pIntr->intrTableSz = pParams->tableLen; - pIntrTable = NULL; - status = NV_OK; + portMemCopy(pIntr->subtreeMap, sizeof pIntr->subtreeMap, + pParams->subtreeMap, sizeof pParams->subtreeMap); exit: portMemFree(pParams); - portMemFree(pIntrTable); - return status; } @@ -1188,43 +1219,26 @@ NV_STATUS intrGetInterruptTable_IMPL ( - OBJGPU *pGpu, - Intr *pIntr, - INTR_TABLE_ENTRY **ppTable, - NvU32 *pTableSz + OBJGPU *pGpu, + Intr *pIntr, + InterruptTable **ppTable ) { NV_ASSERT_OR_RETURN(ppTable != NULL, NV_ERR_INVALID_ARGUMENT); - NV_ASSERT_OR_RETURN(pTableSz != NULL, NV_ERR_INVALID_ARGUMENT); - - NV_ASSERT_OR_RETURN(pIntr->pIntrTable != NULL, NV_ERR_INVALID_STATE); - - *ppTable = pIntr->pIntrTable; - *pTableSz = pIntr->intrTableSz; - + NV_ASSERT_OR_RETURN(!vectIsEmpty(&pIntr->intrTable), NV_ERR_INVALID_STATE); + *ppTable = &pIntr->intrTable; return NV_OK; } -/** - * @brief Frees memory associated with interrupt table - * - * @param pGpu - * @param pMc - */ + NV_STATUS intrDestroyInterruptTable_IMPL ( - OBJGPU *pGpu, - Intr *pIntr + OBJGPU *pGpu, + Intr *pIntr ) { - if (pIntr->pIntrTable != NULL) - { - portMemFree(pIntr->pIntrTable); - pIntr->pIntrTable = NULL; - pIntr->intrTableSz = 0; - } - + vectDestroy(&pIntr->intrTable); return NV_OK; } @@ -1399,39 +1413,41 @@ NvU32 engineIdx; NvU32 intr; - NvU32 i; NvBool bHandled; NvBool bIntrStuck = NV_FALSE; NvBool bPending = NV_FALSE; NvBool bRequiresPossibleErrorNotifier; - INTR_TABLE_ENTRY *pIntrTable; - NvU32 intrTableSz; + InterruptTable *pIntrTable; + InterruptTableIter iter; if (bitVectorTestAllCleared(pEngines)) { return NV_FALSE; } - NV_ASSERT_OK_OR_ELSE(status, intrGetInterruptTable_HAL(pGpu, pIntr, &pIntrTable, &intrTableSz), - return NV_FALSE); + NV_ASSERT_OK_OR_ELSE(status, + intrGetInterruptTable_HAL(pGpu, pIntr, &pIntrTable), + return NV_FALSE); bRequiresPossibleErrorNotifier = intrRequiresPossibleErrorNotifier_HAL(pGpu, pIntr, pEngines); if (bRequiresPossibleErrorNotifier) { - // - // Notify CUDA there may be an error in ERR_CONT that they may miss because we're - // about to clear it out of the NV_CTRL tree backing ERR_CONT before the interrupt - // is serviced. - // - // info32 contains shadowed value of ERR_CONT - // - gpuNotifySubDeviceEvent(pGpu, NV2080_NOTIFIERS_POSSIBLE_ERROR, NULL, 0, intrReadErrCont_HAL(pGpu, pIntr), 0); + if (pGpu->getProperty(pGpu, PDB_PROP_GPU_FASTPATH_SEQ_ENABLED)) + { + } + else + { + // info32 contains shadowed value of ERR_CONT + gpuNotifySubDeviceEvent(pGpu, NV2080_NOTIFIERS_POSSIBLE_ERROR, NULL, 0, intrReadErrCont_HAL(pGpu, pIntr), 0); + } } - for (i = 0; i < intrTableSz; i++) + for (iter = vectIterAll(pIntrTable); vectIterNext(&iter);) { + INTR_TABLE_ENTRY *pEntry = iter.pValue; + // Skip servicing interrupts when GPU is off the bus if (!API_GPU_ATTACHED_SANITY_CHECK(pGpu)) { @@ -1444,7 +1460,7 @@ return NV_FALSE; } - engineIdx = pIntrTable[i].mcEngine; + engineIdx = pEntry->mcEngine; if (bitVectorTest(pEngines, engineIdx)) { @@ -1480,14 +1496,10 @@ if (bRequiresPossibleErrorNotifier) { - // - // Notify CUDA there may be an error in ERR_CONT that they may miss because we're - // about to clear it out of the NV_CTRL tree backing ERR_CONT before the interrupt - // is serviced. - // - // info32 contains shadowed value of ERR_CONT - // - gpuNotifySubDeviceEvent(pGpu, NV2080_NOTIFIERS_POSSIBLE_ERROR, NULL, 0, intrReadErrCont_HAL(pGpu, pIntr), 0); + { + // info32 contains shadowed value of ERR_CONT + gpuNotifySubDeviceEvent(pGpu, NV2080_NOTIFIERS_POSSIBLE_ERROR, NULL, 0, intrReadErrCont_HAL(pGpu, pIntr), 0); + } } if (bIntrStuck) @@ -1567,7 +1579,7 @@ } } - resservSwapTlsCallContext(&pOldContext, NULL); + NV_ASSERT_OK_OR_ELSE(status, resservSwapTlsCallContext(&pOldContext, NULL), return); // prevent the isr from coming in _intrEnterCriticalSection(pGpu, pIntr, &intrMaskCtx); @@ -1596,7 +1608,7 @@ // allow the isr to come in. _intrExitCriticalSection(pGpu, pIntr, &intrMaskCtx); - resservRestoreTlsCallContext(pOldContext); + NV_ASSERT_OK(resservRestoreTlsCallContext(pOldContext)); } @@ -1644,3 +1656,78 @@ return NV_TRUE; } + + +NvU64 +intrGetIntrTopCategoryMask_IMPL +( + Intr *pIntr, + NV2080_INTR_CATEGORY category +) +{ + NvU32 subtreeStart = pIntr->subtreeMap[category].subtreeStart; + NvU32 subtreeEnd = pIntr->subtreeMap[category].subtreeStart; + NvU64 ret = 0x0; + NvU32 i; + + if (subtreeStart == NV2080_INTR_INVALID_SUBTREE || + subtreeEnd == NV2080_INTR_INVALID_SUBTREE) + { + return 0x0; + } + + for (i = subtreeStart; i <= subtreeEnd; ++i) + { + ret |= NVBIT64(i); + } + + return ret; +} + + +NvU64 +intrGetIntrTopLegacyStallMask_IMPL +( + Intr *pIntr +) +{ + OBJGPU *pGpu = ENG_GET_GPU(pIntr); + NvU64 ret = + intrGetIntrTopCategoryMask(pIntr, NV2080_INTR_CATEGORY_ESCHED_DRIVEN_ENGINE) | + intrGetIntrTopCategoryMask(pIntr, NV2080_INTR_CATEGORY_RUNLIST) | + intrGetIntrTopCategoryMask(pIntr, NV2080_INTR_CATEGORY_UVM_OWNED) | + intrGetIntrTopCategoryMask(pIntr, NV2080_INTR_CATEGORY_UVM_SHARED); + + if (!pGpu->getProperty(pGpu, PDB_PROP_GPU_SWRL_GRANULAR_LOCKING)) + { + ret |= intrGetIntrTopCategoryMask(pIntr, + NV2080_INTR_CATEGORY_RUNLIST_NOTIFICATION); + } + + // Sanity check that Intr.subtreeMap is initialized + NV_ASSERT(ret != 0); + return ret; +} + + +NvU64 +intrGetIntrTopLockedMask_IMPL +( + OBJGPU *pGpu, + Intr *pIntr +) +{ + NvU64 ret = + intrGetIntrTopCategoryMask(pIntr, NV2080_INTR_CATEGORY_ESCHED_DRIVEN_ENGINE) | + intrGetIntrTopCategoryMask(pIntr, NV2080_INTR_CATEGORY_RUNLIST); + + if (!pGpu->getProperty(pGpu, PDB_PROP_GPU_SWRL_GRANULAR_LOCKING)) + { + ret |= intrGetIntrTopCategoryMask(pIntr, + NV2080_INTR_CATEGORY_RUNLIST_NOTIFICATION); + } + + // Sanity check that Intr.subtreeMap is initialized + NV_ASSERT(ret != 0); + return ret; +} diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/kernel/gpu/intr/swintr.c nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/kernel/gpu/intr/swintr.c --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/kernel/gpu/intr/swintr.c 2023-10-25 20:21:08.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/kernel/gpu/intr/swintr.c 2024-03-05 22:13:32.000000000 +0000 @@ -62,7 +62,7 @@ ) { NV_ASSERT_OR_RETURN(pParams != NULL, 0); - + switch (pParams->engineIdx) { case MC_ENGINE_IDX_CPU_DOORBELL: diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/kernel/gpu/kern_gpu_power.c nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/kernel/gpu/kern_gpu_power.c --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/kernel/gpu/kern_gpu_power.c 1970-01-01 00:00:00.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/kernel/gpu/kern_gpu_power.c 2024-03-05 22:13:32.000000000 +0000 @@ -0,0 +1,666 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2012-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#include "gpu/gpu.h" +#include "gpu/bif/kernel_bif.h" +#include "gpu/kern_gpu_power.h" +#include "os/os.h" +#include "nvRmReg.h" +#include "diagnostics/journal.h" +#include "diagnostics/tracer.h" +#include "jt.h" +#include "ctrl/ctrl2080/ctrl2080power.h" + +#include "g_journal_pb.h" + + +// Polling loop delays +#define GC6_PWR_CHECK_DELAY_MS 5 +#define GC6_BUS_CHECK_DELAY_MS 1 + +// +// Static functions +// +static NV_STATUS _gpuGc6EntrySanityCheck(OBJGPU *, NV2080_CTRL_GC6_ENTRY_PARAMS *); +static void _gpuGc6EntrySwStateUpdate(OBJGPU *, NV2080_CTRL_GC6_ENTRY_PARAMS *); +static void _gpuGc6EntryFailed(OBJGPU *); +static NV_STATUS _gpuGc6EntryStateUnload(OBJGPU *); +static NV_STATUS _gpuGc6ExitSanityCheck(OBJGPU *); +static NV_STATUS _gpuGc6ExitGpuPowerOn(OBJGPU *, NV2080_CTRL_GC6_EXIT_PARAMS *); +static NV_STATUS _gpuGc6ExitStateLoad(OBJGPU *, NV2080_CTRL_GC6_EXIT_PARAMS *); +static void _gpuGc6ExitSwStateRestore(OBJGPU *); +static void _gpuForceGc6inD3Hot(OBJGPU *, NV2080_CTRL_GC6_EXIT_PARAMS *); + +/*! + * @brief: This HAL function executes the steps of GC6 exit sequence + * + * @param[in] pGpu GPU object pointer + * @param[in,out] pParams Parameter struct + * + * @return + * NV_OK Success + * NV_ERR_GENERIC Generic error (bad state or stuck) + */ +NV_STATUS +gpuGc6Exit_IMPL( + OBJGPU *pGpu, + NV2080_CTRL_GC6_EXIT_PARAMS *pParams +) +{ + NV_STATUS status = NV_OK; + + // Check if we need to execute GPU_ON step + if (GPU_IS_GC6_STEP_ID_SET(GPU_OFF, pGpu->gc6State.executedStepMask)) + { + // Sanity error checking + status = _gpuGc6ExitSanityCheck(pGpu); + if (status != NV_OK) + { + goto gpuGc6Exit_IMPL_exit; + } + + // GPU power on + status = _gpuGc6ExitGpuPowerOn(pGpu, pParams); + if (status != NV_OK) + { + goto gpuGc6Exit_IMPL_exit; + } + + // Set the GPU state as GC6_STATE_EXITING + SET_GPU_GC6_STATE_AND_LOG(pGpu, GPU_GC6_STATE_EXITING); + + // GPU power on + status = _gpuGc6ExitStateLoad(pGpu, pParams); + if (status != NV_OK) + { + goto gpuGc6Exit_IMPL_exit; + } + + // Set the GPU state as GC6_STATE_EXITED + SET_GPU_GC6_STATE_AND_LOG(pGpu, GPU_GC6_STATE_EXITED); + NV_PRINTF(LEVEL_INFO, "GPU is now in D0 state.\n"); + + // Restore SW state + _gpuGc6ExitSwStateRestore(pGpu); + + } + + // Check if we need to execute SR_EXIT step + if (GPU_IS_GC6_STEP_ID_SET(SR_ENTRY, pGpu->gc6State.executedStepMask)) + { + + } + +gpuGc6Exit_IMPL_exit: + // Reset the executed step mask + pGpu->gc6State.executedStepMask = 0; + + return status; +} + +/*! + * @brief: This HAL function executes the steps of GC6 entry sequence + * + * @param[in] pGpu GPU object pointer + * @param[in,out] pParams Parameter struct + * + * @return + * NV_OK Success + * NV_ERR_INVALID_ARGUMENT Invalid action + * NV_ERR_NOT_SUPPORTED Chip doesn't support the feature + * NV_ERR_NOT_READY Chip not ready to execute operation + * NV_ERR_INVALID_STATE Chip unable to execute command at current state + * NV_ERR_TIMEOUT RM timed out when trying to complete call + * NV_ERR_GENERIC Generic error (bad state or stuck) + */ +NV_STATUS +gpuGc6Entry_IMPL( + OBJGPU *pGpu, + NV2080_CTRL_GC6_ENTRY_PARAMS *pParams +) +{ + NV_STATUS status = NV_OK; + + // Check if we need to execute GPU_OFF step + if (GPU_IS_GC6_STEP_ID_SET(GPU_OFF, pParams->stepMask)) + { + // Sanity error checking + status = _gpuGc6EntrySanityCheck(pGpu, pParams); + if (status != NV_OK) + { + goto gpuGc6Entry_IMPL_exit; + } + + // SW state update + _gpuGc6EntrySwStateUpdate(pGpu, pParams); + + // Set the GPU state as GC6_STATE_ENTERING + SET_GPU_GC6_STATE_AND_LOG(pGpu, GPU_GC6_STATE_ENTERING); + + // RM state unload + status = _gpuGc6EntryStateUnload(pGpu); + if (status != NV_OK) + { + goto gpuGc6Entry_IMPL_exit; + } + + // Sanity check p-state is in P8 + status = gpuGc6EntryPstateCheck(pGpu); + if (status != NV_OK) + { + _gpuGc6EntryFailed(pGpu); + goto gpuGc6Entry_IMPL_exit; + } + + // GPU power off + status = gpuGc6EntryGpuPowerOff(pGpu); + if (status != NV_OK) + { + goto gpuGc6Entry_IMPL_exit; + } + + // Set the GPU state as GC6_STATE_ENTERED + SET_GPU_GC6_STATE_AND_LOG(pGpu, GPU_GC6_STATE_ENTERED); + NV_PRINTF(LEVEL_INFO, "GPU is now in GC6 state.\n"); + + // Add this step in executed step mask + pGpu->gc6State.executedStepMask |= NVBIT(NV2080_CTRL_GC6_STEP_ID_GPU_OFF); + } + +gpuGc6Entry_IMPL_exit: + return status; +} + +/*! + * @brief: Helper function for doing powering down GPU during GC6 entry + * + * @param[in] pGpu OBJGPU pointer + * + * @return + * NV_OK Success + * NV_ERR Otherwise + */ +NV_STATUS +gpuGc6EntryGpuPowerOff(OBJGPU *pGpu) +{ + NV_STATUS status = NV_OK; + + // SW pre-settings before calling power off. + NV_ASSERT_OK_OR_RETURN(gpuPrePowerOff_HAL(pGpu)); + + if ((pGpu->getProperty(pGpu, PDB_PROP_GPU_RTD3_GC6_ACTIVE) && + !pGpu->acpiMethodData.jtMethodData.bSBIOSCaps)) + { + status = NV_OK; + NV_PRINTF(LEVEL_INFO, + "Skip call to power off GPU in OSPM RTD3\n"); + goto _gpuGc6EntryGpuPowerOff_EXIT; + } + + // call on all GC6 systems that contain SBIOS JT caps + status = gpuPowerOff(pGpu); + +_gpuGc6EntryGpuPowerOff_EXIT: + if (status != NV_OK) + { + _gpuGc6EntryFailed(pGpu); + NV_PRINTF(LEVEL_ERROR, "Call to power off GPU failed.\n"); + DBG_BREAKPOINT(); + } + + return status; +} + +/*! + * @brief Power off GPU and enter GC6 state. + * + * This function implements last phase of GC6 entry sequence as defined in + * JT Architecture Specification. + * + * @param[in] pGpu GPU object pointer + * + * @return NV_OK + * If GPU has entered (or is entering) GC6 state. + * + * @return other Bubbles up errors from + * @ref osGC6PowerControl on failure. + */ +NV_STATUS +gpuPowerOff_KERNEL(OBJGPU *pGpu) +{ + + NvU32 deferCmd = 0x134c02; + + if (!pGpu->acpiMethodData.jtMethodData.bSBIOSCaps && + pGpu->getProperty(pGpu, PDB_PROP_GPU_RTD3_GC6_ACTIVE)) + { + return NV_OK; + } + + NV_ASSERT_OK_OR_RETURN( + osGC6PowerControl(pGpu, deferCmd, NULL)); + + return NV_OK; +} + +/*! + * @brief Power on GPU + * + * This function implements first phase of GC6 exit sequence as defined in + * JT Architecture Specification. + * + * @param[in] pGpu GPU object pointer + * + * @return NV_OK + * If GPU showed up on the bus. + * + * @return NV_ERR_TIMEOUT + * If timeout occurred while waiting for GPU to show up on the bus. + * + * @return other Bubbles up errors from @ref osGC6PowerControl on failure. + */ +NV_STATUS +gpuPowerOn_KERNEL(OBJGPU *pGpu) +{ + NV_STATUS status; + NvU32 powerStatus; + RMTIMEOUT timeout; + + // We do not make any _DSM calls for OSPM + RTD3 + if (!pGpu->acpiMethodData.jtMethodData.bSBIOSCaps && + pGpu->getProperty(pGpu, PDB_PROP_GPU_RTD3_GC6_ACTIVE)) + { + return NV_OK; + } + + // + // Pick the correct command to send to the _DSM + // If we are on MsHybrid, the OS has already made the call to power on GPU + // + if (pGpu->getProperty(pGpu, PDB_PROP_GPU_MSHYBRID_GC6_ACTIVE)) + { + // clear the deferred entry/exit state in the SBIOS + NV_ASSERT_OK_OR_RETURN( + osGC6PowerControl(pGpu, 0x8000, &powerStatus)); + } + + // + // wait for SBIOS to report that GPU is powered on. When the GPU is reported + // as "powered on" both the below conditions are true + // 1. The Pex Link is Powered Up + // 2. EC reports PWR_OK to be asserted. + // + gpuSetTimeout(pGpu, GPU_TIMEOUT_DEFAULT, &timeout, 0); + while (NV_TRUE) + { + NV_ASSERT_OK_OR_RETURN( + osGC6PowerControl(pGpu, 0x0, &powerStatus)); + + if (FLD_TEST_DRF(_JT_FUNC, _POWERCONTROL, _GPU_POWER_STATE, _PWOK, powerStatus)) + { + break; + } + + status = gpuCheckTimeout(pGpu, &timeout); + if (status == NV_ERR_TIMEOUT) + { + RMTRACE_GPU(_GC6_POWERON_ERR_TO, pGpu->gpuId, 0, 0, 0, 0, 0, 0, 0); + NV_PRINTF(LEVEL_ERROR, + "Timeout waiting for GPU to enter PWOK/ON state.Current State %x\n", + powerStatus); + DBG_BREAKPOINT(); + return status; + } + + // For same reasons as above, loosen the polling loop. + osDelay(GC6_PWR_CHECK_DELAY_MS); + } + + // + // There is a possibility that GPU hasn't yet appeared on the bus even + // though the link is up. Wait here for the GPU to appear on the bus before + // proceeding. Note, it's not recommended to poll on the device config + // space till the pex link in the root port is restored, but since link + // should be up by the time OS_GC6_GET_GPU_POWER_STATE returns STATUS_ON + // it is safe to do so here. We want to be absolutely sure that the GPU + // is on the bus before we proceed and restore the GPU config space. + // + if (!gpuIsOnTheBus(pGpu)) + { + NV_PRINTF(LEVEL_WARNING, + "GPU is not yet on the bus after GC6 power-up.\n"); + + gpuSetTimeout(pGpu, GPU_TIMEOUT_DEFAULT, &timeout, 0); + while (!gpuIsOnTheBus(pGpu)) + { + status = gpuCheckTimeout(pGpu, &timeout); + if (status == NV_ERR_TIMEOUT) + { + RMTRACE_GPU(_GC6_POWERON_ERR_BUS_TO, pGpu->gpuId, 0, 0, 0, 0, 0, 0, 0); + NV_PRINTF(LEVEL_ERROR, + "Timeout waiting for GPU to appear on the bus.\n"); + DBG_BREAKPOINT(); + return status; + } + + // For same reasons as above, loosen the polling loop. + osDelay(GC6_BUS_CHECK_DELAY_MS); + } + } + + return NV_OK; +} + +/*! + * @brief Check if GPU is on the bus. + * + * @param[in] pGpu GPU object pointer + * + * @return 'NV_TRUE' if GPU is on the bus; 'NV_FALSE' otherwise. + */ +NvBool +gpuIsOnTheBus_IMPL(OBJGPU *pGpu) +{ + NvU32 domain = gpuGetDomain(pGpu); + NvU8 bus = gpuGetBus(pGpu); + NvU8 device = gpuGetDevice(pGpu); + NvU16 vendorId, deviceId; + void *handle; + + handle = osPciInitHandle(domain, bus, device, 0, &vendorId, &deviceId); + return (handle != NULL); +} + +/*! + * @brief: Helper function for sanity error checking during GC6 entry + * + * @param[in] pGpu OBJGPU pointer + * @param[in] pParams Pointer to RmCtrl parameters + * + * @return + * NV_OK Success + * NV_ERR Otherwise + */ +static NV_STATUS +_gpuGc6EntrySanityCheck(OBJGPU *pGpu, NV2080_CTRL_GC6_ENTRY_PARAMS *pParams) +{ + NV_STATUS status = NV_OK; + + // + // Sanity check RTD3 enablement + // TODO: replace with PDB that indicates system support of RTD3, not just the chip + // + if (pParams->params.bIsRTD3Transition && + !pGpu->getProperty(pGpu, PDB_PROP_GPU_CHIP_SUPPORTS_RTD3_DEF)) + { + NV_PRINTF(LEVEL_ERROR, + "Cannot perform RTD3 as chip does not support.\n"); + DBG_BREAKPOINT(); + return NV_ERR_NOT_SUPPORTED; + } + + if (IS_GPU_GC6_STATE_ENTERED(pGpu)) + { + NV_PRINTF(LEVEL_ERROR, + "GPU is already in GC6 state or stuck in transition.\n"); + DBG_BREAKPOINT(); + return NV_ERR_INVALID_STATE; + } + + // Wait for GPU to be ready for GC6 + status = gpuWaitGC6Ready_HAL(pGpu); + if (status != NV_OK) + { + NV_PRINTF(LEVEL_ERROR, + "GPU is not ready to transition from D0 to GC6 state.\n"); + DBG_BREAKPOINT(); + } + + return status; +} + +/*! + * @brief: Helper function for updating SW state during GC6 entry + * + * @param[in] pGpu OBJGPU pointer + * @param[in] pParams Pointer to RmCtrl parameters + */ +static void +_gpuGc6EntrySwStateUpdate(OBJGPU *pGpu, NV2080_CTRL_GC6_ENTRY_PARAMS *pParams) +{ + + // set state if we are doing an MsHybrid GC6 cycle OR Fast GC6 cycle + if (pParams->flavorId == NV2080_CTRL_GC6_FLAVOR_ID_MSHYBRID) + { + pGpu->setProperty(pGpu, PDB_PROP_GPU_MSHYBRID_GC6_ACTIVE, NV_TRUE); + } + + // set state if we are doing a RTD3 GC6 cycle + if (pParams->params.bIsRTD3Transition) + { + pGpu->setProperty(pGpu, PDB_PROP_GPU_RTD3_GC6_ACTIVE, NV_TRUE); + + } +} + +/*! + * @brief: Helper function for restoring SW state during failed GC6 entry + * + * @param[in] pGpu OBJGPU pointer + */ +static void +_gpuGc6EntryFailed(OBJGPU *pGpu) +{ + SET_GPU_GC6_STATE_AND_LOG(pGpu, GPU_GC6_STATE_ENTERING_FAILED); + + pGpu->setProperty(pGpu, PDB_PROP_GPU_MSHYBRID_GC6_ACTIVE, NV_FALSE); + pGpu->setProperty(pGpu, PDB_PROP_GPU_FAST_GC6_ACTIVE, NV_FALSE); + pGpu->setProperty(pGpu, PDB_PROP_GPU_RTD3_GC6_ACTIVE, NV_FALSE); +} + +/*! + * @brief: Helper function for doing RM state unload during GC6 entry + * + * @param[in] pGpu OBJGPU pointer + * + * @return + * NV_OK Success + * NV_ERR Otherwise + */ +static NV_STATUS +_gpuGc6EntryStateUnload(OBJGPU *pGpu) +{ + NV_STATUS status; + + pGpu->setProperty(pGpu, PDB_PROP_GPU_FORCE_PERF_BIOS_LEVEL, NV_TRUE); + status = gpuEnterStandby(pGpu); + pGpu->setProperty(pGpu, PDB_PROP_GPU_FORCE_PERF_BIOS_LEVEL, NV_FALSE); + + if (status != NV_OK) + { + _gpuGc6EntryFailed(pGpu); + NV_PRINTF(LEVEL_ERROR, + "GPU is unable to transition from D0 to GC6 state.\n"); + DBG_BREAKPOINT(); + } + + return status; +} + +/*! + * @brief: Helper function for sanity error checking during GC6 exit + * + * @param[in] pGpu OBJGPU pointer + * + * @return + * NV_OK Success + * NV_ERR Otherwise + */ +static NV_STATUS +_gpuGc6ExitSanityCheck(OBJGPU *pGpu) +{ + NV_STATUS status = NV_OK; + + + // Make sure that the current GC6 state is GPU_STATE_ENTERED_GC6 + if (!IS_GPU_GC6_STATE_ENTERED(pGpu)) + { + NV_PRINTF(LEVEL_ERROR, "GPU is not in GC6 state.\n"); + DBG_BREAKPOINT(); + return NV_ERR_INVALID_STATE; + } + + return status; +} + +/*! + * @brief: Helper function for doing powering up GPU during GC6 exit + * + * @param[in] pGpu OBJGPU pointer + * @param[in] pParams Pointer to RmCtrl parameters + * + * @return + * NV_OK Success + * NV_ERR Otherwise + */ +static NV_STATUS +_gpuGc6ExitGpuPowerOn(OBJGPU *pGpu, NV2080_CTRL_GC6_EXIT_PARAMS *pParams) +{ + NV_STATUS status = NV_OK; + + return status; +} + +/*! + * @brief: Helper function for restoring SW state during GC6 exit + * + * @param[in] pGpu OBJGPU pointer + */ +static void +_gpuGc6ExitSwStateRestore(OBJGPU *pGpu) +{ + pGpu->setProperty(pGpu, PDB_PROP_GPU_MSHYBRID_GC6_ACTIVE, NV_FALSE); + pGpu->setProperty(pGpu, PDB_PROP_GPU_FAST_GC6_ACTIVE, NV_FALSE); + pGpu->setProperty(pGpu, PDB_PROP_GPU_RTD3_GC6_ACTIVE, NV_FALSE); +} + +/*! + * @brief: Helper function to force GC6 cycle in this D3 hot exit + * + * @param[in] pGpu OBJGPU pointer + */ +static void +_gpuForceGc6inD3Hot(OBJGPU *pGpu, NV2080_CTRL_GC6_EXIT_PARAMS *pParams) +{ + + pParams->params.bIsRTD3HotTransition = NV_FALSE; + // + // If this was a D3Hot cycle (no power down), force a GC6 cycle + // This is due to instability of some memory types with D3Hot cycles + // Skip this on RTD3 cycles since we won't have the _DSMs to force cycles + // Summarize the scenario that needs to do _DSM reset + // 1. It's OSPM but not RTD3. + // 2. GPU power was not cut. + // 3. The D3Hot WAR is enabled + // Note _FORCE_D3HOT works only on NVPM + // + + // + // Enable BAR0 accesses here for RTLSIM, EMU, and silicon MFG MODS. + // FMODEL will not be reset, so no need to enable. + // Windows will be pci bus driver to restore, but below function will check before enabling. + // Only enable BAR0 accesses here, + // and leave whole restore steps in gpuPowerManagementResumePreLoadPhysical(). + // + if (!IS_FMODEL(pGpu) && IS_GPU_GC6_STATE_EXITING(pGpu)) + { + NV_STATUS tempStatus = kbifPollDeviceOnBus(pGpu, GPU_GET_KERNEL_BIF(pGpu)); + + if (tempStatus != NV_OK) + { + NV_PRINTF(LEVEL_ERROR, "Enable BAR0 accesses failed.\n"); + } + } + + // The power remains is necessary for d3hot + if (!gpuCompletedGC6PowerOff_HAL(pGpu)) + { + pParams->params.bIsRTD3HotTransition = NV_TRUE; + + NV_PRINTF(LEVEL_ERROR, + "D3Hot detected. Going to recover from D3Hot\n"); + + if (pGpu->getProperty(pGpu, PDB_PROP_GPU_CHIP_SUPPORTS_RTD3_DEF) + ) + { + if (!pGpu->getProperty(pGpu, PDB_PROP_GPU_RTD3_GC6_ACTIVE)) + { + NV_PRINTF(LEVEL_ERROR, + "D3Hot case for Turing and later but legacy GC6/FGC6 flavor.\n"); + } + } + // none RTD3 D3Hot and none legacy D3Hot WAR + else + { + NV_PRINTF(LEVEL_ERROR, + "D3Hot case for none RTD3 and no WAR enabled.\n"); + } + + } // End of if (!gpuCompletedGC6PowerOff_HAL(pGpu)) +} + +/*! + * @brief: Helper function for doing RM state load during GC6 exit + * + * @param[in] pGpu OBJGPU pointer + * @param[in] pParams Pointer to RmCtrl parameters + * + * @return + * NV_OK Success + * NV_ERR Otherwise + */ +static NV_STATUS +_gpuGc6ExitStateLoad(OBJGPU *pGpu, NV2080_CTRL_GC6_EXIT_PARAMS *pParams) +{ + NV_STATUS status = NV_OK; + + pGpu->setProperty(pGpu, PDB_PROP_GPU_FORCE_PERF_BIOS_LEVEL, NV_TRUE); + + // Force GC6 cycle if this D3 hot + _gpuForceGc6inD3Hot(pGpu, pParams); + + status = gpuResumeFromStandby(pGpu); + + pGpu->setProperty(pGpu, PDB_PROP_GPU_FORCE_PERF_BIOS_LEVEL, NV_FALSE); + + if (status != NV_OK) + { + SET_GPU_GC6_STATE_AND_LOG(pGpu, GPU_GC6_STATE_EXITING_FAILED); + NV_PRINTF(LEVEL_ERROR, + "GPU is unable to transition from GC6 to D0 state.\n"); + DBG_BREAKPOINT(); + } + + return status; +} + diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/kernel/gpu/mc/kernel_mc.c nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/kernel/gpu/mc/kernel_mc.c --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/kernel/gpu/mc/kernel_mc.c 2023-10-25 20:21:09.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/kernel/gpu/mc/kernel_mc.c 2024-03-05 22:13:33.000000000 +0000 @@ -53,7 +53,7 @@ { OBJGPU *pGpu = GPU_RES_GET_GPU(pSubdevice); - if (IsTEGRA(pGpu)) + if (IsTEGRA_NVDISP_GPUS(pGpu)) { pArchInfoParams->architecture = pGpu->chipInfo.platformId; pArchInfoParams->implementation = pGpu->chipInfo.implementationId; @@ -61,16 +61,8 @@ } else { - if (pGpu->idInfo.ArchitectureExternal && pGpu->idInfo.ImplementationExternal) - { - pArchInfoParams->architecture = pGpu->idInfo.ArchitectureExternal; - pArchInfoParams->implementation = pGpu->idInfo.ImplementationExternal; - } - else - { - pArchInfoParams->architecture = pGpu->chipInfo.pmcBoot0.arch; - pArchInfoParams->implementation = pGpu->chipInfo.pmcBoot0.impl; - } + pArchInfoParams->architecture = pGpu->chipInfo.pmcBoot0.arch; + pArchInfoParams->implementation = pGpu->chipInfo.pmcBoot0.impl; pArchInfoParams->revision = (pGpu->chipInfo.pmcBoot0.majorRev << 4) | pGpu->chipInfo.pmcBoot0.minorRev; pArchInfoParams->subRevision = pGpu->chipInfo.subRevision; } @@ -124,11 +116,6 @@ OBJGPU *pGpu = GPU_RES_GET_GPU(pSubdevice); KernelGmmu *pKernelGmmu = GPU_GET_KERNEL_GMMU(pGpu); - if (gpuIsCCFeatureEnabled(pGpu)) - { - return NV_ERR_NOT_SUPPORTED; - } - if (pKernelGmmu != NULL) { kgmmuChangeReplayableFaultOwnership_HAL(pGpu, pKernelGmmu, pReplayableFaultOwnrshpParams->bOwnedByRm); @@ -243,7 +230,7 @@ // Adjust the pci latency timer if needed _kmcSetPciLatencyTimer(pGpu, pKernelMc); } - + return NV_OK; } diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/kernel/gpu/mem_mgr/arch/ampere/fbsr_ga100.c nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/kernel/gpu/mem_mgr/arch/ampere/fbsr_ga100.c --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/kernel/gpu/mem_mgr/arch/ampere/fbsr_ga100.c 2023-10-25 20:21:09.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/kernel/gpu/mem_mgr/arch/ampere/fbsr_ga100.c 2024-03-05 22:13:33.000000000 +0000 @@ -26,11 +26,12 @@ #include "gpu/mem_sys/kern_mem_sys.h" #include "gpu/mem_mgr/fbsr.h" -static NV_STATUS -fbsrSendMemsysProgramRawCompressionMode +NV_STATUS +fbsrSendMemsysProgramRawCompressionMode_GA100 ( - OBJGPU *pGpu, - NvBool bRawMode + OBJGPU *pGpu, + OBJFBSR *pFbsr, + NvBool bRawMode ) { RM_API *pRmApi = GPU_GET_PHYSICAL_RMAPI(pGpu); @@ -69,7 +70,7 @@ if (pMemorySystemConfig->bUseRawModeComptaglineAllocation) { - NV_ASSERT_OK(fbsrSendMemsysProgramRawCompressionMode(pGpu, NV_FALSE)); + NV_ASSERT_OK(fbsrSendMemsysProgramRawCompressionMode_HAL(pGpu, pFbsr, NV_FALSE)); pFbsr->bRawModeWasEnabled = NV_TRUE; } } @@ -90,13 +91,13 @@ { NV_STATUS status = fbsrEnd_GM107(pGpu, pFbsr); - if (pFbsr->op == FBSR_OP_RESTORE && - pFbsr->bRawModeWasEnabled) + if (pFbsr->op == FBSR_OP_RESTORE && pFbsr->bRawModeWasEnabled) { /* * Reenable raw mode if it was disabled by fbsrBegin_GA100. */ - NV_ASSERT_OK(fbsrSendMemsysProgramRawCompressionMode(pGpu, NV_TRUE)); + NV_ASSERT_OK(fbsrSendMemsysProgramRawCompressionMode_HAL(pGpu, pFbsr, NV_TRUE)); + pFbsr->bRawModeWasEnabled = NV_FALSE; } return status; diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/kernel/gpu/mem_mgr/arch/ampere/mem_mgr_ga100.c nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/kernel/gpu/mem_mgr/arch/ampere/mem_mgr_ga100.c --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/kernel/gpu/mem_mgr/arch/ampere/mem_mgr_ga100.c 2023-10-25 20:21:09.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/kernel/gpu/mem_mgr/arch/ampere/mem_mgr_ga100.c 2024-03-05 22:13:33.000000000 +0000 @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 2018-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2018-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -110,18 +110,13 @@ // Disabling for GSP-RM ucode, since scrubbing is done from CPU-side kernel RM. // Enabling virtual scrubbing mode for SRIOV-HEAVY mode. // - // Temporary: Disabling scrub on free if CC is enabled. Once the - // support for secure work launch is in, this temporary change can be - // reverted. Bug: 3334708 - // if ((RMCFG_FEATURE_PLATFORM_WINDOWS && !pGpu->getProperty(pGpu, PDB_PROP_GPU_IN_TCC_MODE)) || IS_SIMULATION(pGpu) || IsDFPGA(pGpu) || pGpu->getProperty(pGpu, PDB_PROP_GPU_IS_VIRTUALIZATION_MODE_HOST_VGPU) || IS_VIRTUAL_WITHOUT_SRIOV(pGpu) || RMCFG_FEATURE_PLATFORM_GSP || - pGpu->getProperty(pGpu, PDB_PROP_GPU_BROKEN_FB) || - gpuIsCCFeatureEnabled(pGpu) || + (pGpu->getProperty(pGpu, PDB_PROP_GPU_BROKEN_FB) && !gpuIsCacheOnlyModeEnabled(pGpu)) || IsSLIEnabled(pGpu)) { pMemoryManager->bScrubOnFreeEnabled = NV_FALSE; @@ -364,20 +359,27 @@ return NV_ERR_NOT_SUPPORTED; } + NV2080_CTRL_FB_GET_DYNAMIC_OFFLINED_PAGES_PARAMS *pBlParams = + portMemAllocNonPaged(sizeof(*pBlParams)); + if (pBlParams == NULL) + { + return NV_ERR_NO_MEMORY; + } + while (baseIndex < NV2080_CTRL_FB_DYNAMIC_BLACKLIST_MAX_PAGES) { RM_API *pRmApi = IS_GSP_CLIENT(pGpu) ? GPU_GET_PHYSICAL_RMAPI(pGpu) : rmapiGetInterface(RMAPI_GPU_LOCK_INTERNAL); - NV2080_CTRL_FB_GET_DYNAMIC_OFFLINED_PAGES_PARAMS blParams = {0}; + portMemSet(pBlParams, 0, sizeof(*pBlParams)); - blParams.baseIndex = baseIndex; + pBlParams->baseIndex = baseIndex; status = pRmApi->Control(pRmApi, pGpu->hInternalClient, pGpu->hInternalSubdevice, NV2080_CTRL_CMD_FB_GET_DYNAMIC_OFFLINED_PAGES, - &blParams, - sizeof(blParams)); + pBlParams, + sizeof(*pBlParams)); if(NV_OK != status) { if (NV_ERR_NOT_SUPPORTED == status || @@ -395,7 +397,7 @@ break; } - for (idx = 0; idx < blParams.validEntries; idx++) + for (idx = 0; idx < pBlParams->validEntries; idx++) { if (entryIdx >= *pCount) @@ -403,12 +405,12 @@ status = NV_ERR_BUFFER_TOO_SMALL; goto done; } - pBlAddrs[entryIdx].address = blParams.offlined[idx].pageNumber << RM_PAGE_SHIFT; - pBlAddrs[entryIdx].type = blParams.offlined[idx].source; + pBlAddrs[entryIdx].address = pBlParams->offlined[idx].pageNumber << RM_PAGE_SHIFT; + pBlAddrs[entryIdx].type = pBlParams->offlined[idx].source; entryIdx++; } - if (!blParams.bMore) { + if (!pBlParams->bMore) { break; } @@ -416,6 +418,7 @@ } done: + portMemFree(pBlParams); *pCount = entryIdx; return status; @@ -488,3 +491,18 @@ return NV_OK; } + +NvBool +memmgrIsApertureSupportedByFla_GA100 +( + OBJGPU *pGpu, + MemoryManager *pMemoryManager, + NV_ADDRESS_SPACE aperture +) +{ + if (aperture == ADDR_FBMEM) + { + return NV_TRUE; + } + return NV_FALSE; +} diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/kernel/gpu/mem_mgr/arch/hopper/mem_utils_gh100.c nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/kernel/gpu/mem_mgr/arch/hopper/mem_utils_gh100.c --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/kernel/gpu/mem_mgr/arch/hopper/mem_utils_gh100.c 2023-10-25 20:21:09.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/kernel/gpu/mem_mgr/arch/hopper/mem_utils_gh100.c 2024-03-05 22:13:33.000000000 +0000 @@ -28,7 +28,7 @@ /*! - * Function to verify which memory scubber (fast/slow) has to use in Hopper+ for scrubbering + * Function to verify which memory scubber (fast/slow) has to use in Hopper+ for scrubbering * * @param[in] copyClass DMA ccopy class * @param[in] bIsVirtualMemory Memory type @@ -36,7 +36,7 @@ * @param[in] size Size of the region to scrub * @param[in] dstAddressSpace DST address space * - * @returns NV_TRUE - Use memory fast scrbber for scrubbing + * @returns NV_TRUE - Use memory fast scrbber for scrubbing * NV_FALSE - Use slow scrubber */ NvBool @@ -64,10 +64,53 @@ // Address is 4KB aligned // LineLength is 4KB aligned // - return ((copyClass == HOPPER_DMA_COPY_A + return ((copyClass == HOPPER_DMA_COPY_A ) && (!bIsVirtualMemory) && (dstAddressSpace == ADDR_FBMEM) && (NV_IS_ALIGNED64(addr, MEMUTIL_SCRUB_OFFSET_ALIGNMENT)) && (NV_IS_ALIGNED(size, MEMUTIL_SCRUB_LINE_LENGTH_ALIGNMENT))); } + +/*! + * Create an engine object and setup SEC2 channel scheduling + * + * @param[in] OBJCHANNEL - channel object + * + * @returns NV_OK + */ +NV_STATUS +memmgrMemUtilsSec2CtxInit_GH100 +( + OBJGPU *pGpu, + MemoryManager *pMemoryManager, + OBJCHANNEL *pChannel +) +{ + NV_STATUS rmStatus = NV_OK; + RM_API *pRmApi = rmapiGetInterface(RMAPI_GPU_LOCK_INTERNAL); + + // Alloc sec2 context + NV_CHECK_OK_OR_GOTO( + rmStatus, + LEVEL_ERROR, + pRmApi->AllocWithHandle(pRmApi, + pChannel->hClient, + pChannel->channelId, + pChannel->engineObjectId, + pChannel->sec2Class, + NULL, 0), + exit_free); + + NV_CHECK_OK_OR_GOTO( + rmStatus, + LEVEL_ERROR, + memmgrMemUtilsChannelSchedulingSetup(pGpu, pMemoryManager, pChannel), exit_free); + + return NV_OK; + + exit_free: + pRmApi->Free(pRmApi, pChannel->hClient, pChannel->hClient); + NV_PRINTF(LEVEL_INFO, "end NV_STATUS=0x%08x\n", rmStatus); + return rmStatus; +} \ No newline at end of file diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/kernel/gpu/mem_mgr/arch/hopper/virt_mem_allocator_gh100.c nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/kernel/gpu/mem_mgr/arch/hopper/virt_mem_allocator_gh100.c --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/kernel/gpu/mem_mgr/arch/hopper/virt_mem_allocator_gh100.c 2023-10-25 20:21:09.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/kernel/gpu/mem_mgr/arch/hopper/virt_mem_allocator_gh100.c 2024-03-05 22:13:34.000000000 +0000 @@ -54,7 +54,6 @@ NvU64 bar1ApertureLen = 0; // BAR1 aperture mapped lengths OBJGPU *pPeerGpu = NULL; KernelBus *pPeerKernelBus = NULL; - NvHandle hClient = NV01_NULL_OBJECT; NV_STATUS status = NV_OK; if (params == NULL || @@ -89,7 +88,7 @@ &phyAddr, &bar1ApertureLen, BUS_MAP_FB_FLAGS_MAP_UNICAST, - hClient); + NULL); if (status != NV_OK) goto cleanup; diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/kernel/gpu/mem_mgr/arch/maxwell/fbsr_gm107.c nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/kernel/gpu/mem_mgr/arch/maxwell/fbsr_gm107.c --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/kernel/gpu/mem_mgr/arch/maxwell/fbsr_gm107.c 2023-10-25 20:21:09.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/kernel/gpu/mem_mgr/arch/maxwell/fbsr_gm107.c 2024-03-05 22:13:34.000000000 +0000 @@ -114,9 +114,10 @@ params.fbsrType = pFbsr->type; params.numRegions = pFbsr->numRegions; - params.hClient = pMemoryManager->hClient; + params.hClient = pMemoryManager->hClient; params.hSysMem = hSysMem; params.gspFbAllocsSysOffset = pFbsr->gspFbAllocsSysOffset; + params.bEnteringGcoffState = pGpu->getProperty(pGpu, PDB_PROP_GPU_GCOFF_STATE_ENTERING); // Send S/R init information to GSP NV_ASSERT_OK_OR_RETURN(pRmApi->Control(pRmApi, @@ -160,7 +161,7 @@ portMemSet(¶ms, 0, sizeof(params)); params.fbsrType = pFbsr->type; - params.hClient = pMemoryManager->hClient; + params.hClient = pMemoryManager->hClient; params.hVidMem = hVidMem; params.vidOffset = srcOffset; params.sysOffset = dstOffset; @@ -453,7 +454,7 @@ if(bIommuEnabled) { - status = osSrPinSysmem(pGpu->pOsGpuInfo, + status = osSrPinSysmem(pGpu->pOsGpuInfo, pFbsr->length, &pFbsr->pagedBufferInfo.pMdl); diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/kernel/gpu/mem_mgr/arch/maxwell/mem_mgr_gm107.c nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/kernel/gpu/mem_mgr/arch/maxwell/mem_mgr_gm107.c --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/kernel/gpu/mem_mgr/arch/maxwell/mem_mgr_gm107.c 2023-10-25 20:21:09.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/kernel/gpu/mem_mgr/arch/maxwell/mem_mgr_gm107.c 2024-03-05 22:13:34.000000000 +0000 @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 2006-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2006-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -197,7 +197,7 @@ // No offset alignment requirement for 4KB compression. // The size should be aligned to compression pagesize. // - NvU32 comprPageSize = pMemorySystemConfig->comprPageSize; + NvU64 comprPageSize = pMemorySystemConfig->comprPageSize; *pMemSize = ((*pMemSize + alignPad + comprPageSize - 1) / comprPageSize) * comprPageSize; } else @@ -467,9 +467,10 @@ // if (FLD_TEST_DRF(OS32, _ATTR2, _ZBC_SKIP_ZBCREFCOUNT, _NO, pFbAllocInfo->pageFormat->attr2)) { - if (memmgrIsKind_HAL(pMemoryManager, FB_IS_KIND_ZBC, pFbAllocInfo->pageFormat->kind) && - !(pFbAllocInfo->pageFormat->flags & NVOS32_ALLOC_FLAGS_VIRTUAL) && - !IS_MIG_ENABLED(pGpu)) + if ( + !IS_MIG_ENABLED(pGpu) && + memmgrIsKind_HAL(pMemoryManager, FB_IS_KIND_ZBC, pFbAllocInfo->pageFormat->kind) && + !(pFbAllocInfo->pageFormat->flags & NVOS32_ALLOC_FLAGS_VIRTUAL)) { retAttr2 = FLD_SET_DRF(OS32, _ATTR2, _ZBC, _PREFER_ZBC, retAttr2); if (!bAlignPhase) @@ -524,7 +525,7 @@ PRMTIMEOUT pTimeout ) { - NvU32 commitResId = pFbAllocInfo->hwResId; + NvU32 commitResId = pFbAllocInfo->hwResId; if (pFbAllocInfo->pageFormat->flags & NVOS32_ALLOC_FLAGS_SKIP_RESOURCE_ALLOC) { @@ -643,11 +644,11 @@ } NV_STATUS -memmgrGetBAR1InfoForClient_GM107 +memmgrGetBAR1InfoForDevice_GM107 ( OBJGPU *pGpu, MemoryManager *pMemoryManager, - NvHandle hClient, + Device *pDevice, PGETBAR1INFO bar1Info ) { @@ -657,6 +658,7 @@ OBJVASPACE *pBar1VAS; OBJEHEAP *pVASHeap; NV_RANGE bar1VARange = NV_RANGE_EMPTY; + RsClient *pClient = RES_GET_CLIENT(pDevice); /* * For legacy vGPU and SRIOV heavy, get BAR1 information from vGPU plugin. @@ -666,11 +668,9 @@ { NV_STATUS status = NV_OK; NV2080_CTRL_FB_GET_INFO_V2_PARAMS fbInfoParams = {0}; - RsClient *pRsClient; Subdevice *pSubdevice; - NV_ASSERT_OK_OR_RETURN(serverGetClientUnderLock(&g_resServ, hClient, &pRsClient)); - NV_ASSERT_OK_OR_RETURN(subdeviceGetByGpu(pRsClient, pGpu, &pSubdevice)); + NV_ASSERT_OK_OR_RETURN(subdeviceGetByGpu(pClient, pGpu, &pSubdevice)); fbInfoParams.fbInfoList[0].index = NV2080_CTRL_FB_INFO_INDEX_BAR1_SIZE; fbInfoParams.fbInfoList[1].index = NV2080_CTRL_FB_INFO_INDEX_BAR1_AVAIL_SIZE; @@ -679,7 +679,7 @@ fbInfoParams.fbInfoListSize = 4; - NV_RM_RPC_CONTROL(pGpu, hClient, RES_GET_HANDLE(pSubdevice), + NV_RM_RPC_CONTROL(pGpu, pClient->hClient, RES_GET_HANDLE(pSubdevice), NV2080_CTRL_CMD_FB_GET_INFO_V2, &fbInfoParams, sizeof(fbInfoParams), status); @@ -692,20 +692,32 @@ return status; } - pBar1VAS = kbusGetBar1VASpace_HAL(pGpu, pKernelBus); - pVASHeap = vaspaceGetHeap(pBar1VAS); + if (!KBUS_CPU_VISIBLE_BAR12_DISABLED(pGpu)) + { + pBar1VAS = kbusGetBar1VASpace_HAL(pGpu, pKernelBus); + NV_ASSERT_OR_RETURN(pBar1VAS != NULL, NV_ERR_INVALID_STATE); + pVASHeap = vaspaceGetHeap(pBar1VAS); - NV_ASSERT_OK_OR_RETURN(kbusGetBar1VARangeForClient(pGpu, pKernelBus, hClient, &bar1VARange)); - bar1Info->bar1Size = (NvU32)(rangeLength(bar1VARange) / 1024); - bar1Info->bankSwizzleAlignment = vaspaceGetBigPageSize(pBar1VAS); + NV_ASSERT_OK_OR_RETURN(kbusGetBar1VARangeForClient(pGpu, pKernelBus, pClient->hClient, &bar1VARange)); + bar1Info->bar1Size = (NvU32)(rangeLength(bar1VARange) / 1024); + bar1Info->bankSwizzleAlignment = vaspaceGetBigPageSize(pBar1VAS); - bar1Info->bar1AvailSize = 0; + bar1Info->bar1AvailSize = 0; - if (pVASHeap != NULL) + if (pVASHeap != NULL) + { + pVASHeap->eheapInfoForRange(pVASHeap, bar1VARange, NULL, &largestFreeSize, NULL, &freeSize); + bar1Info->bar1AvailSize = (NvU32)(freeSize / 1024); + bar1Info->bar1MaxContigAvailSize = (NvU32)(largestFreeSize / 1024); + } + } + else { - pVASHeap->eheapInfoForRange(pVASHeap, bar1VARange, NULL, &largestFreeSize, NULL, &freeSize); - bar1Info->bar1AvailSize = (NvU32)(freeSize / 1024); - bar1Info->bar1MaxContigAvailSize = (NvU32)(largestFreeSize / 1024); + // When coherent C2C path is enabled, BAR1 is disabled + bar1Info->bar1Size = 0; + bar1Info->bar1AvailSize = 0; + bar1Info->bar1MaxContigAvailSize = 0; + bar1Info->bankSwizzleAlignment = 0; } return NV_OK; } @@ -819,6 +831,8 @@ } } + bMemoryProtectionEnabled = gpuIsCCFeatureEnabled(pGpu); + memmgrStateInitReservedMemory(pGpu, pMemoryManager); // Align reserved memory to 64K granularity @@ -848,6 +862,10 @@ // Find the last region in memory which is not already reserved or // protected. RM's reserved memory will then be carved out of it below // (once the final size and address are determined). + // RM internal data like BAR2 page tables, BAR1/2 instance blocks, etc should + // always be in protected memory whenever memory protection is enabled using Hopper + // Confidential Compute. For uses outside Hopper Confidential Compute, RM internal + // data should always be in unprotected video memory. // for (i = 0; i < pMemoryManager->Ram.numFBRegions; i++) { @@ -1069,7 +1087,7 @@ ( RmPhysAddr physAddr, MEMORY_DESCRIPTOR *pMemDesc, - NvU32 bigPageSize, + NvU64 bigPageSize, NvU64 sysmemPageSize ) { @@ -1131,10 +1149,10 @@ RM_ATTR_PAGE_SIZE pageSizeAttr ) { - NvU32 newPageSize = RM_PAGE_SIZE; + NvU64 newPageSize = RM_PAGE_SIZE; KernelGmmu *pKernelGmmu = GPU_GET_KERNEL_GMMU(pGpu); NV_ADDRESS_SPACE addrSpace = memdescGetAddressSpace(pMemDesc); - NvU32 oldPageSize; + NvU64 oldPageSize; // This policy is meaningless for virtual memdescs, so abort early. if (ADDR_VIRTUAL == addrSpace) diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/kernel/gpu/mem_mgr/arch/maxwell/mem_mgr_gm200.c nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/kernel/gpu/mem_mgr/arch/maxwell/mem_mgr_gm200.c --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/kernel/gpu/mem_mgr/arch/maxwell/mem_mgr_gm200.c 2023-10-25 20:21:09.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/kernel/gpu/mem_mgr/arch/maxwell/mem_mgr_gm200.c 2024-03-05 22:13:34.000000000 +0000 @@ -38,7 +38,7 @@ MemoryManager *pMemoryManager ) { - NvU64 size; + NvU64 size = 0; // // This function's original purpose was to estimate how much heap memory RM @@ -89,7 +89,8 @@ } else { - if (memmgrIsPmaInitialized(pMemoryManager)) + if (memmgrIsPmaEnabled(pMemoryManager) && + memmgrIsPmaSupportedOnPlatform(pMemoryManager)) { // // We need to estimate the reserved memory needs before PMA is initialized diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/kernel/gpu/mem_mgr/arch/maxwell/mem_utils_gm107.c nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/kernel/gpu/mem_mgr/arch/maxwell/mem_utils_gm107.c --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/kernel/gpu/mem_mgr/arch/maxwell/mem_utils_gm107.c 2023-10-25 20:21:09.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/kernel/gpu/mem_mgr/arch/maxwell/mem_utils_gm107.c 2024-03-05 22:13:34.000000000 +0000 @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 2012-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2012-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -40,6 +40,7 @@ #include "gpu/subdevice/subdevice.h" #include "vgpu/rpc.h" #include "kernel/gpu/fifo/kernel_channel.h" +#include "platform/chipset/chipset.h" #include "class/clc0b5sw.h" #include "class/cla06fsubch.h" // NVA06F_SUBCHANNEL_COPY_ENGINE @@ -51,7 +52,6 @@ #include "class/cl00c2.h" // NV01_MEMORY_LOCAL_PHYSICAL #include "class/clb0b5.h" // MAXWELL_DMA_COPY_A #include "class/clc8b5.h" // HOPPER_DMA_COPY_A -#include "class/cl0005.h" // NV01_EVENT #include "class/cl90f1.h" // FERMI_VASPACE_A #define NONSTALL_METHOD_SIZE 8 @@ -64,12 +64,12 @@ NvHandle hDeviceId, NvHandle hChannelId, NvHandle hObjectError, NvHandle hObjectBuffer, OBJCHANNEL *pChannel); static NV_STATUS _memUtilsAllocCe_GM107(OBJGPU *pGpu, MemoryManager *pMemoryManager, OBJCHANNEL *pChannel, - NvHandle hClientId, NvHandle hChannelId, NvHandle hCopyObjectId); + NvHandle hClientId, NvHandle hDeviceId, NvHandle hChannelId, NvHandle hCopyObjectId); static NV_STATUS _memUtilsAllocateUserD(OBJGPU *pGpu, MemoryManager *pMemoryManager, NvHandle hClientId, NvHandle hDeviceId, OBJCHANNEL *pChannel); static NV_STATUS _memUtilsMapUserd_GM107(OBJGPU *pGpu, MemoryManager *pMemoryManager, OBJCHANNEL *pChannel, NvHandle hClientId, NvHandle hDeviceId, - NvHandle hChannelId); + NvHandle hChannelId, NvBool bUseRmApiForBar1); static NV_STATUS _memUtilsAllocateReductionSema(OBJGPU *pGpu, MemoryManager *pMemoryManager, OBJCHANNEL *pChannel); static NvU32 _ceChannelScheduleBatchWork_GM107(OBJGPU *pGpu, MemoryManager *pMemoryManager, OBJCHANNEL *pChannel, RmPhysAddr src, NV_ADDRESS_SPACE srcAddressSpace, NvU32 srcCpuCacheAttrib, @@ -117,13 +117,23 @@ memAllocParams.attr2 = NVOS32_ATTR2_NONE; memAllocParams.flags = 0; + // + // When APM feature is enabled all RM internal sysmem allocations must + // be in unprotected memory + // When Hopper CC is enabled all RM internal sysmem allocations that + // are required to be accessed from GPU should be in unprotected memory + // but those sysmem allocations that are not required to be accessed from + // GPU should be in protected memory. + // + NV_ASSERT_OK_OR_RETURN( pRmApi->AllocWithHandle(pRmApi, pChannel->hClient, pChannel->deviceId, pChannel->bitMapSemPhysId, NV01_MEMORY_SYSTEM, - &memAllocParams)); + &memAllocParams, + sizeof(memAllocParams))); // allocate virtual memory for a bit map semaphore portMemSet(&memAllocParams, 0, sizeof(memAllocParams)); @@ -141,7 +151,8 @@ pChannel->deviceId, pChannel->bitMapSemVirtId, NV50_MEMORY_VIRTUAL, - &memAllocParams)); + &memAllocParams, + sizeof(memAllocParams))); lockStatus = rmGpuLocksAcquire(GPUS_LOCK_FLAGS_NONE, RM_LOCK_MODULES_MEM); if(lockStatus != NV_OK) @@ -269,6 +280,20 @@ memAllocParams.flags = 0; memAllocParams.internalflags = NVOS32_ALLOC_INTERNAL_FLAGS_SKIP_SCRUB; + // + // When APM is enabled all RM internal allocations must to go to + // unprotected memory irrespective of vidmem or sysmem + // When Hopper CC is enabled all RM internal sysmem allocations that + // are required to be accessed from GPU should be in unprotected memory + // but all vidmem allocations must go to protected memory + // + if (gpuIsApmFeatureEnabled(pGpu) || + FLD_TEST_DRF(OS32, _ATTR, _LOCATION, _PCI, memAllocParams.attr)) + { + memAllocParams.attr2 |= DRF_DEF(OS32, _ATTR2, _MEMORY_PROTECTION, + _UNPROTECTED); + } + NV_CHECK_OK_OR_RETURN( LEVEL_ERROR, pRmApi->AllocWithHandle(pRmApi, @@ -276,7 +301,8 @@ hDevice, hPhysMem, hClass, - &memAllocParams)); + &memAllocParams, + sizeof(memAllocParams))); // allocate the Virtual memory portMemSet(&memAllocParams, 0, sizeof(memAllocParams)); @@ -295,7 +321,8 @@ hDevice, hVirtMem, NV50_MEMORY_VIRTUAL, - &memAllocParams)); + &memAllocParams, + sizeof(memAllocParams))); // allocate the physmem for the notifier portMemSet(&memAllocParams, 0, sizeof(memAllocParams)); @@ -307,6 +334,20 @@ memAllocParams.flags = 0; memAllocParams.internalflags = NVOS32_ALLOC_INTERNAL_FLAGS_SKIP_SCRUB; + // + // When APM is enabled all RM internal allocations must to go to + // unprotected memory irrespective of vidmem or sysmem + // When Hopper CC is enabled all RM internal sysmem allocations that + // are required to be accessed from GPU should be in unprotected memory + // but all vidmem allocations must go to protected memory + // + if (gpuIsApmFeatureEnabled(pGpu) || + FLD_TEST_DRF(OS32, _ATTR, _LOCATION, _PCI, memAllocParams.attr)) + { + memAllocParams.attr2 |= DRF_DEF(OS32, _ATTR2, _MEMORY_PROTECTION, + _UNPROTECTED); + } + NV_CHECK_OK_OR_RETURN( LEVEL_ERROR, pRmApi->AllocWithHandle(pRmApi, @@ -314,7 +355,8 @@ hDevice, pChannel->errNotifierIdPhys, hClass, - &memAllocParams)); + &memAllocParams, + sizeof(memAllocParams))); // allocate Virtual Memory for the notifier portMemSet(&memAllocParams, 0, sizeof(memAllocParams)); @@ -333,7 +375,8 @@ hDevice, pChannel->errNotifierIdVirt, NV50_MEMORY_VIRTUAL, - &memAllocParams)); + &memAllocParams, + sizeof(memAllocParams))); return rmStatus; } @@ -346,24 +389,28 @@ OBJCHANNEL *pChannel ) { - NV_STATUS rmStatus; - NV_STATUS lockStatus; - NvHandle hDevice; // device handle - NvHandle hPhysMem; // memory handle - NvU64 size; - NvHandle hChannel; // channel handle - NvHandle hErrNotifierVirt; - NvHandle hErrNotifierPhys; - NvHandle hPushBuffer; - NvHandle hClient; - RM_API *pRmApi = rmapiGetInterface(RMAPI_GPU_LOCK_INTERNAL); - RmClient *pClient; - Heap *pHeap = GPU_GET_HEAP(pGpu); - NvBool bMIGInUse = IS_MIG_IN_USE(pGpu); - NvU8 *pErrNotifierCpuVA = NULL; - NV_ADDRESS_SPACE userdAddrSpace; - NV_ADDRESS_SPACE pushBuffAddrSpace; - NV_ADDRESS_SPACE gpFifoAddrSpace; + NV_STATUS rmStatus; + NV_STATUS lockStatus; + RsClient *pRsClient; + NvHandle hClient; + NvHandle hDevice; + NvHandle hPhysMem; + NvU64 size; + NvHandle hChannel; + NvHandle hErrNotifierVirt; + NvHandle hErrNotifierPhys; + NvHandle hPushBuffer; + RM_API *pRmApi = rmapiGetInterface(RMAPI_GPU_LOCK_INTERNAL); + Heap *pHeap = GPU_GET_HEAP(pGpu); + NvBool bMIGInUse = IS_MIG_IN_USE(pGpu); + NvU8 *pErrNotifierCpuVA = NULL; + NV_ADDRESS_SPACE userdAddrSpace; + NV_ADDRESS_SPACE pushBuffAddrSpace; + NV_ADDRESS_SPACE gpFifoAddrSpace; + OBJSYS *pSys = SYS_GET_INSTANCE(); + OBJCL *pCl = SYS_GET_CL(pSys); + NvU32 cacheSnoopFlag = 0 ; + NvBool bUseRmApiForBar1 = NV_FALSE; // // Heap alloc one chunk of memory to hold all of our alloc parameters to @@ -385,27 +432,25 @@ hErrNotifierPhys = pChannel->errNotifierIdPhys; hPushBuffer = pChannel->pushBufferId; - if (!pChannel->bClientAllocated) + if (pCl->getProperty(pCl, PDB_PROP_CL_IS_CHIPSET_IO_COHERENT)) { - RsClient *pRsClient; + cacheSnoopFlag = DRF_DEF(OS46, _FLAGS, _CACHE_SNOOP, _ENABLE); + } + if (!pChannel->bClientAllocated) + { NV_CHECK_OK_OR_RETURN( LEVEL_ERROR, pRmApi->AllocWithHandle(pRmApi, NV01_NULL_OBJECT, NV01_NULL_OBJECT, NV01_NULL_OBJECT, NV01_ROOT, - &pChannel->hClient)); - - NV_ASSERT_OK_OR_GOTO( - rmStatus, - serverutilGetClientUnderLock(pChannel->hClient, &pClient), - exit_free_client); + &pChannel->hClient, sizeof(pChannel->hClient))); NV_ASSERT_OK_OR_GOTO( rmStatus, - serverGetClientUnderLock(&g_resServ, pChannel->hClient, &pChannel->pRsClient), + serverGetClientUnderLock(&g_resServ, pChannel->hClient, &pRsClient), exit_free_client); - pRsClient = staticCast(pClient, RsClient); + pChannel->pRsClient = pRsClient; if (IS_VIRTUAL(pGpu)) { @@ -423,8 +468,10 @@ exit_free_client); } } + else + pRsClient = pChannel->pRsClient; - hClient = pChannel->hClient; + hClient = pRsClient->hClient; pParams = portMemAllocNonPaged(sizeof(*pParams)); if (pParams == NULL) @@ -433,14 +480,13 @@ goto exit_free_client; } - NV_ASSERT_OK_OR_GOTO( - rmStatus, - serverutilGenResourceHandle(hClient, &pChannel->deviceId), - exit_free_client); - - hDevice = pChannel->deviceId; - + if (pChannel->deviceId == NV01_NULL_OBJECT) { + NV_ASSERT_OK_OR_GOTO( + rmStatus, + clientGenResourceHandle(pRsClient, &pChannel->deviceId), + exit_free_client); + NV0080_ALLOC_PARAMETERS *pNv0080 = &pParams->nv0080; portMemSet(pNv0080, 0, sizeof(*pNv0080)); @@ -451,18 +497,20 @@ NV_CHECK_OK_OR_GOTO( rmStatus, LEVEL_ERROR, - pRmApi->AllocWithHandle(pRmApi, hClient, hClient, hDevice, - NV01_DEVICE_0, pNv0080), + pRmApi->AllocWithHandle(pRmApi, hClient, hClient, pChannel->deviceId, + NV01_DEVICE_0, pNv0080, sizeof(*pNv0080)), exit_free_client); } - - NV_ASSERT_OK_OR_GOTO( - rmStatus, - serverutilGenResourceHandle(hClient, &pChannel->subdeviceId), - exit_free_client); + hDevice = pChannel->deviceId; // allocate a subdevice + if (pChannel->subdeviceId == NV01_NULL_OBJECT) { + NV_ASSERT_OK_OR_GOTO( + rmStatus, + clientGenResourceHandle(pRsClient, &pChannel->subdeviceId), + exit_free_client); + NV2080_ALLOC_PARAMETERS *pNv2080 = &pParams->nv2080; portMemSet(pNv2080, 0, sizeof(*pNv2080)); pNv2080->subDeviceId = gpumgrGetSubDeviceInstanceFromGpu(pGpu); @@ -470,10 +518,10 @@ NV_CHECK_OK_OR_GOTO( rmStatus, LEVEL_ERROR, - pRmApi->AllocWithHandle(pRmApi, hClient, hDevice, - pChannel->subdeviceId, + pRmApi->AllocWithHandle(pRmApi, hClient, hDevice, pChannel->subdeviceId, NV20_SUBDEVICE_0, - pNv2080), + pNv2080, + sizeof(*pNv2080)), exit_free_client); } @@ -484,8 +532,7 @@ NV_ASSERT_OK_OR_GOTO( rmStatus, - serverutilGenResourceHandle(hClient, - &pChannel->hPartitionRef), + clientGenResourceHandle(pRsClient, &pChannel->hPartitionRef), exit_free_client); portMemSet(pNvC637, 0, sizeof(*pNvC637)); @@ -497,7 +544,8 @@ pChannel->subdeviceId, pChannel->hPartitionRef, AMPERE_SMC_PARTITION_REF, - pNvC637), + pNvC637, + sizeof(*pNvC637)), exit_free_client); pHeap = pChannel->pKernelMIGGpuInstance->pMemoryPartitionHeap; @@ -553,7 +601,7 @@ if (pChannel->bUseVasForCeCopy) { NV_ASSERT_OK_OR_GOTO(rmStatus, - serverutilGenResourceHandle(pChannel->hClient, &pChannel->hFbAlias), + clientGenResourceHandle(pRsClient, &pChannel->hFbAlias), exit_free_client); rmStatus = memmgrMemUtilsCreateMemoryAlias_HAL(pGpu, pMemoryManager, pChannel); @@ -601,7 +649,7 @@ rmStatus = pRmApi->AllocWithHandle(pRmApi, hClient, pChannel->deviceId, pChannel->hVASpaceId, FERMI_VASPACE_A, - pVa); + pVa, sizeof(*pVa)); } if (bAcquireLock) { @@ -617,10 +665,10 @@ goto exit_free_client; } - rmStatus = vaspaceGetByHandleOrDeviceDefault(pChannel->pRsClient, - pChannel->deviceId, - pChannel->hVASpaceId, - &pChannel->pVAS); + rmStatus = vaspaceGetByHandleOrDeviceDefault(pRsClient, + pChannel->deviceId, + pChannel->hVASpaceId, + &pChannel->pVAS); if (rmStatus != NV_OK) { NV_PRINTF(LEVEL_ERROR, @@ -643,7 +691,7 @@ } NV_ASSERT_OK_OR_GOTO(rmStatus, - serverutilGenResourceHandle(pChannel->hClient, &pChannel->hFbAliasVA), exit_free_client); + clientGenResourceHandle(pRsClient, &pChannel->hFbAliasVA), exit_free_client); } if (gpuIsSplitVasManagementServerClientRmEnabled(pGpu)) @@ -679,11 +727,12 @@ pMem->hVASpace = pChannel->hVASpaceId; rmStatus = pRmApi->AllocWithHandle(pRmApi, - pChannel->hClient, - pChannel->deviceId, - pChannel->hFbAliasVA, - NV50_MEMORY_VIRTUAL, - pMem); + hClient, + pChannel->deviceId, + pChannel->hFbAliasVA, + NV50_MEMORY_VIRTUAL, + pMem, + sizeof(*pMem)); } if (bAcquireLock) @@ -707,7 +756,7 @@ rmStatus, LEVEL_ERROR, pRmApi->Map(pRmApi, - pChannel->hClient, + hClient, pChannel->deviceId, pChannel->hFbAliasVA, pChannel->hFbAlias, @@ -792,7 +841,7 @@ hPhysMem, //hMemory, 0, size, - NV04_MAP_MEMORY_FLAGS_NONE, + cacheSnoopFlag, &pChannel->pbGpuVA); // map the error notifier rmStatus = pRmApi->Map(pRmApi, hClient, hDevice, @@ -800,7 +849,7 @@ hErrNotifierPhys, //hMemory, 0, pChannel->channelNotifierSize, - DRF_DEF(OS46, _FLAGS, _KERNEL_MAPPING, _ENABLE), + DRF_DEF(OS46, _FLAGS, _KERNEL_MAPPING, _ENABLE) | cacheSnoopFlag, &pChannel->pbGpuNotifierVA); NV_CHECK_OK_OR_GOTO( @@ -821,46 +870,64 @@ rmStatus, LEVEL_ERROR, _memUtilsMapUserd_GM107(pGpu, pMemoryManager, pChannel, - hClient, hDevice, hChannel), + hClient, hDevice, hChannel, bUseRmApiForBar1), exit_free_client); - // - // map cpu pointer - // Map the pushbuffer memory to CPU viewable region - // - NV_CHECK_OK_OR_GOTO( - rmStatus, - LEVEL_ERROR, - pRmApi->MapToCpu(pRmApi, - hClient, - hDevice, - hPhysMem, - 0, - size, - (void **)&pChannel->pbCpuVA, - 0), - exit_free_client); + // Set up pushbuffer and semaphore memdesc and memset the buffer + pChannel->pChannelBufferMemdesc = + memmgrMemUtilsGetMemDescFromHandle(pMemoryManager, pChannel->hClient, hPhysMem); + NV_ASSERT_OR_GOTO(pChannel->pChannelBufferMemdesc != NULL, exit_free_client); + + // Set up notifier memory + pChannel->pErrNotifierMemdesc = + memmgrMemUtilsGetMemDescFromHandle(pMemoryManager, pChannel->hClient, hErrNotifierPhys); + NV_ASSERT_OR_GOTO(pChannel->pErrNotifierMemdesc != NULL, exit_free_client); + + if (kbusIsBarAccessBlocked(GPU_GET_KERNEL_BUS(pGpu))) + { + rmStatus = memmgrMemDescMemSet(pMemoryManager, pChannel->pChannelBufferMemdesc, 0, + (TRANSFER_FLAGS_SHADOW_ALLOC | TRANSFER_FLAGS_SHADOW_INIT_MEM)); + NV_ASSERT_OR_GOTO(rmStatus == NV_OK, exit_free_client); - portMemSet(pChannel->pbCpuVA, 0, (NvLength)size); + pChannel->pbCpuVA = NULL; + pChannel->pTokenFromNotifier = NULL; + } + else + { + if (bUseRmApiForBar1) + { + NV_CHECK_OK_OR_GOTO(rmStatus, LEVEL_ERROR, + pRmApi->MapToCpu(pRmApi, hClient, hDevice, hPhysMem, 0, size, + (void **)&pChannel->pbCpuVA, 0), + exit_free_client); - // Map the notifier memory to CPU viewable region - NV_CHECK_OK_OR_GOTO( - rmStatus, - LEVEL_ERROR, - pRmApi->MapToCpu(pRmApi, - hClient, - hDevice, - hErrNotifierPhys, - 0, - pChannel->channelNotifierSize, - (void **)&pErrNotifierCpuVA, - 0), - exit_free_client); + NV_CHECK_OK_OR_GOTO(rmStatus, LEVEL_ERROR, + pRmApi->MapToCpu(pRmApi, hClient, hDevice, hErrNotifierPhys, 0, + pChannel->channelNotifierSize, (void **)&pErrNotifierCpuVA, 0), + exit_free_client); + } + else + { + // + // Most use cases can migrate to the internal memdescMap path for BAR1 + // And it is preferred because external path will not work with CC + // + pChannel->pbCpuVA = memmgrMemDescBeginTransfer(pMemoryManager, + pChannel->pChannelBufferMemdesc, TRANSFER_FLAGS_USE_BAR1); + NV_ASSERT_OR_GOTO(pChannel->pbCpuVA != NULL, exit_free_client); + + pErrNotifierCpuVA = memmgrMemDescBeginTransfer(pMemoryManager, + pChannel->pErrNotifierMemdesc, TRANSFER_FLAGS_USE_BAR1); + NV_ASSERT_OR_GOTO(pErrNotifierCpuVA != NULL, exit_free_client); + } - pChannel->pTokenFromNotifier = - (NvNotification *)(pErrNotifierCpuVA + - (NV_CHANNELGPFIFO_NOTIFICATION_TYPE_WORK_SUBMIT_TOKEN * - sizeof(NvNotification))); + portMemSet(pChannel->pbCpuVA, 0, (NvLength)size); + + pChannel->pTokenFromNotifier = + (NvNotification *)(pErrNotifierCpuVA + + (NV_CHANNELGPFIFO_NOTIFICATION_TYPE_WORK_SUBMIT_TOKEN * + sizeof(NvNotification))); + } // // Allocate and map the doorbell region to use in scrub on free @@ -916,7 +983,8 @@ pChannel->deviceId, pChannel->hFbAlias, NV01_MEMORY_LOCAL_PHYSICAL, - &physMemParams); + &physMemParams, + sizeof(physMemParams)); if (status != NV_OK) { NV_CHECK_OK_FAILED(LEVEL_WARNING, "Aliasing FbListMem", status); @@ -930,141 +998,6 @@ return NV_OK; } -/*! - * Registers the callback specified in clientHeap.callback for the channel - * driven scrub. The callback is triggered by NV906F_NON_STALL_INTERRUPT. - */ -static NV_STATUS -memmgrMemUtilsScrubInitRegisterCallback -( - OBJGPU *pGpu, - OBJCHANNEL *pChannel -) -{ - NV0005_ALLOC_PARAMETERS nv0005AllocParams; - NV2080_CTRL_EVENT_SET_NOTIFICATION_PARAMS nv2080EventNotificationParams; - NV_STATUS rmStatus; - NvHandle subDeviceHandle = 0; - RM_API *pRmApi = rmapiGetInterface(RMAPI_GPU_LOCK_INTERNAL); - - if (NV_OK != CliGetSubDeviceHandleFromGpu(pChannel->hClient, - pGpu, - &subDeviceHandle)) - { - NV_PRINTF(LEVEL_WARNING, "Unable to get subdevice handle.\n"); - //Allocate a sub device if we dont have it created before hand - NV2080_ALLOC_PARAMETERS nv2080AllocParams; - - portMemSet(&nv2080AllocParams, 0, sizeof(NV2080_ALLOC_PARAMETERS)); - nv2080AllocParams.subDeviceId = gpumgrGetSubDeviceInstanceFromGpu(pGpu); - - rmStatus = pRmApi->AllocWithHandle(pRmApi, - pChannel->hClient, - pChannel->deviceId, - pChannel->subdeviceId, - NV20_SUBDEVICE_0, - &nv2080AllocParams); - if (rmStatus != NV_OK) - { - NV_PRINTF(LEVEL_ERROR, "Unable to allocate a subdevice.\n"); - return NV_ERR_GENERIC; - } - } - - // Register callback - portMemSet(&nv0005AllocParams, 0, sizeof(NV0005_ALLOC_PARAMETERS)); - nv0005AllocParams.hParentClient = pChannel->hClient; - nv0005AllocParams.hClass = NV01_EVENT_KERNEL_CALLBACK_EX; - nv0005AllocParams.notifyIndex = NV2080_NOTIFIERS_FIFO_EVENT_MTHD | NV01_EVENT_NONSTALL_INTR ; - nv0005AllocParams.data = NV_PTR_TO_NvP64(&pChannel->callback); - - rmStatus = pRmApi->AllocWithHandle(pRmApi, - pChannel->hClient, - subDeviceHandle, - pChannel->eventId, - NV01_EVENT_KERNEL_CALLBACK_EX, - &nv0005AllocParams); - - if (rmStatus != NV_OK) - { - NV_PRINTF(LEVEL_ERROR, "event allocation failed\n"); - return NV_ERR_GENERIC; - } - - // Setup periodic event notification - portMemSet(&nv2080EventNotificationParams, 0, sizeof(NV2080_CTRL_EVENT_SET_NOTIFICATION_PARAMS)); - nv2080EventNotificationParams.event = NV2080_NOTIFIERS_FIFO_EVENT_MTHD; - nv2080EventNotificationParams.action = NV2080_CTRL_EVENT_SET_NOTIFICATION_ACTION_REPEAT; - - rmStatus = pRmApi->Control(pRmApi, - pChannel->hClient, - subDeviceHandle, - NV2080_CTRL_CMD_EVENT_SET_NOTIFICATION, - &nv2080EventNotificationParams, - sizeof(NV2080_CTRL_EVENT_SET_NOTIFICATION_PARAMS)); - - if (rmStatus != NV_OK) - { - NV_PRINTF(LEVEL_ERROR, "event notification control failed\n"); - return NV_ERR_GENERIC; - } - - return NV_OK; -} - -/*! - * Schedules the scrubber channel for execution. - */ -static NV_STATUS -memmgrMemUtilsScrubInitScheduleChannel -( - OBJGPU *pGpu, - OBJCHANNEL *pChannel -) -{ - NV_STATUS rmStatus; - NVA06F_CTRL_GPFIFO_SCHEDULE_PARAMS nvA06fScheduleParams; - RM_API *pRmApi = rmapiGetInterface(RMAPI_GPU_LOCK_INTERNAL); - - if (pChannel->bUseVasForCeCopy) - { - NVA06F_CTRL_BIND_PARAMS bindParams; - portMemSet(&bindParams, 0, sizeof(bindParams)); - - bindParams.engineType = gpuGetNv2080EngineType(pChannel->engineType); - - rmStatus = pRmApi->Control(pRmApi, - pChannel->hClient, - pChannel->channelId, - NVA06F_CTRL_CMD_BIND, - &bindParams, - sizeof(bindParams)); - if (rmStatus != NV_OK) - { - NV_PRINTF(LEVEL_ERROR, "Unable to bind Channel, status: %x\n", rmStatus); - return rmStatus; - } - } - - portMemSet(&nvA06fScheduleParams, 0, sizeof(NVA06F_CTRL_GPFIFO_SCHEDULE_PARAMS)); - nvA06fScheduleParams.bEnable = NV_TRUE; - - rmStatus = pRmApi->Control(pRmApi, - pChannel->hClient, - pChannel->channelId, - NVA06F_CTRL_CMD_GPFIFO_SCHEDULE, - &nvA06fScheduleParams, - sizeof(NVA06F_CTRL_GPFIFO_SCHEDULE_PARAMS)); - - if (rmStatus != NV_OK) - { - NV_PRINTF(LEVEL_ERROR, "Unable to schedule channel, status: %x\n", rmStatus); - return NV_ERR_GENERIC; - } - - return NV_OK; -} - NV_STATUS memmgrMemUtilsCopyEngineInitialize_GM107 ( @@ -1073,12 +1006,8 @@ OBJCHANNEL *pChannel ) { - NvU32 classID; - RM_ENGINE_TYPE engineID; - NV_STATUS rmStatus; - KernelFifo *pKernelFifo = GPU_GET_KERNEL_FIFO(pGpu); - KernelChannel *pFifoKernelChannel = NULL; - RM_API *pRmApi = rmapiGetInterface(RMAPI_GPU_LOCK_INTERNAL); + NV_STATUS rmStatus = NV_OK; + RM_API *pRmApi = rmapiGetInterface(RMAPI_GPU_LOCK_INTERNAL); //allocce NV_CHECK_OK_OR_GOTO( @@ -1088,57 +1017,16 @@ pMemoryManager, pChannel, pChannel->hClient, + pChannel->deviceId, pChannel->channelId, - pChannel->copyObjectId), - exit_free); - - // schedulechannel - NV_CHECK_OK_OR_GOTO( - rmStatus, - LEVEL_WARNING, - memmgrMemUtilsScrubInitScheduleChannel(pGpu, pChannel), - exit_free); - - // Determine classEngineID for SetObject usage - NV_CHECK_OK_OR_GOTO( - rmStatus, - LEVEL_ERROR, - CliGetKernelChannelWithDevice(pChannel->hClient, - pChannel->deviceId, - pChannel->channelId, - &pFifoKernelChannel), - exit_free); - - - NV_CHECK_OK_OR_GOTO( - rmStatus, - LEVEL_ERROR, - kchannelGetClassEngineID_HAL(pGpu, - pFifoKernelChannel, - pChannel->copyObjectId, - &pChannel->classEngineID, - &classID, - &engineID), - exit_free); - - NV_CHECK_OK_OR_GOTO( - rmStatus, - LEVEL_ERROR, - memmgrMemUtilsScrubInitRegisterCallback(pGpu, pChannel), + pChannel->engineObjectId), exit_free); NV_CHECK_OK_OR_GOTO( rmStatus, LEVEL_ERROR, - kfifoRmctrlGetWorkSubmitToken_HAL(pKernelFifo, - pChannel->hClient, - pChannel->channelId, - &pChannel->workSubmitToken), - exit_free); + memmgrMemUtilsChannelSchedulingSetup(pGpu, pMemoryManager, pChannel), exit_free); - // initialize the channel parameters (should be done by the parent object) - pChannel->channelPutOffset = 0; - MEM_WR32(pChannel->pbCpuVA + pChannel->semaOffset, 0); return NV_OK; exit_free: @@ -1151,6 +1039,7 @@ ( OBJGPU *pGpu, NvHandle hClient, + NvHandle hDevice, KernelCE **ppKCe ) { @@ -1163,7 +1052,16 @@ if (IS_MIG_IN_USE(pGpu)) { - status = kmigmgrGetGPUInstanceScrubberCe(pGpu, GPU_GET_KERNEL_MIG_MANAGER(pGpu), hClient, &ceInst); + RsClient *pClient; + Device *pDevice; + + NV_ASSERT_OK_OR_RETURN( + serverGetClientUnderLock(&g_resServ, hClient, &pClient)); + + NV_ASSERT_OK_OR_RETURN( + deviceGetByHandle(pClient, hDevice, &pDevice)); + + status = kmigmgrGetGPUInstanceScrubberCe(pGpu, GPU_GET_KERNEL_MIG_MANAGER(pGpu), pDevice, &ceInst); } else { @@ -1193,6 +1091,7 @@ MemoryManager *pMemoryManager, OBJCHANNEL *pChannel, NvHandle hClientId, + NvHandle hDeviceId, NvHandle hChannelId, NvHandle hCopyObjectId @@ -1204,7 +1103,7 @@ createParams.version = NVC0B5_ALLOCATION_PARAMETERS_VERSION_1; - NV_ASSERT_OK_OR_RETURN(_memUtilsGetCe_GM107(pGpu, hClientId, &pKCe)); + NV_ASSERT_OK_OR_RETURN(_memUtilsGetCe_GM107(pGpu, hClientId, hDeviceId, &pKCe)); NV_ASSERT_OR_RETURN((pKCe != NULL), NV_ERR_INVALID_STATE); createParams.engineType = NV2080_ENGINE_TYPE_COPY(pKCe->publicID); @@ -1224,9 +1123,10 @@ hChannelId, hCopyObjectId, pChannel->hTdCopyClass, - &createParams)); + &createParams, + sizeof(createParams))); - pChannel->pKCe = pKCe; + pChannel->ceId = pKCe->publicID; return NV_OK; } @@ -1238,25 +1138,48 @@ OBJCHANNEL *pChannel, NvHandle hClientId, NvHandle hDeviceId, - NvHandle hChannelId + NvHandle hChannelId, + NvBool bUseRmApiForBar1 ) { - NvU32 userdSize; - RM_API *pRmApi = rmapiGetInterface(RMAPI_GPU_LOCK_INTERNAL); - - kfifoGetUserdSizeAlign_HAL(GPU_GET_KERNEL_FIFO(pGpu), &userdSize, NULL); - - NV_CHECK_OK_OR_RETURN( - LEVEL_ERROR, - pRmApi->MapToCpu(pRmApi, - hClientId, - hDeviceId, - pChannel->bClientUserd ? pChannel->hUserD : hChannelId, - 0, - userdSize, - (void **)&pChannel->pControlGPFifo, - 0)); + // + // The memTransfer API only works for client-allocated USERD + // because otherwise we are calling MapToCpu using the channel + // handle instead. + // + if (pChannel->bClientUserd && !bUseRmApiForBar1) + { + pChannel->pUserdMemdesc = + memmgrMemUtilsGetMemDescFromHandle(pMemoryManager, hClientId, pChannel->hUserD); + NV_ASSERT_OR_RETURN(pChannel->pUserdMemdesc != NULL, NV_ERR_GENERIC); + if (kbusIsBarAccessBlocked(GPU_GET_KERNEL_BUS(pGpu))) + { + // + // GPFIFO aceess will not be set up in order to facilitate memTransfer APIs + // which will use GSP-DMA/CE with shadow buffers + // + pChannel->pControlGPFifo = NULL; + } + else + { + pChannel->pControlGPFifo = + (void *)memmgrMemDescBeginTransfer(pMemoryManager, pChannel->pUserdMemdesc, + TRANSFER_FLAGS_USE_BAR1); + NV_ASSERT_OR_RETURN(pChannel->pControlGPFifo != NULL, NV_ERR_GENERIC); + } + } + else + { + NvU32 userdSize = 0; + RM_API *pRmApi = rmapiGetInterface(RMAPI_GPU_LOCK_INTERNAL); + kfifoGetUserdSizeAlign_HAL(GPU_GET_KERNEL_FIFO(pGpu), &userdSize, NULL); + + NV_CHECK_OK_OR_RETURN(LEVEL_ERROR, + pRmApi->MapToCpu(pRmApi, hClientId, hDeviceId, + pChannel->bClientUserd ? pChannel->hUserD : hChannelId, 0, + userdSize, (void **)&pChannel->pControlGPFifo, 0)); + } return NV_OK; } @@ -1303,10 +1226,25 @@ break; } + // + // When APM is enabled all RM internal allocations must to go to + // unprotected memory irrespective of vidmem or sysmem + // When Hopper CC is enabled all RM internal sysmem allocations that + // are required to be accessed from GPU should be in unprotected memory + // but all vidmem allocations must go to protected memory + // + if (gpuIsApmFeatureEnabled(pGpu) || + FLD_TEST_DRF(OS32, _ATTR, _LOCATION, _PCI, memAllocParams.attr)) + { + memAllocParams.attr2 |= DRF_DEF(OS32, _ATTR2, _MEMORY_PROTECTION, + _UNPROTECTED); + } + NV_ASSERT_OK_OR_RETURN(pRmApi->AllocWithHandle(pRmApi, hClientId, hDeviceId, pChannel->hUserD, userdMemClass, - &memAllocParams)); + &memAllocParams, + sizeof(memAllocParams))); return rmStatus; } @@ -1325,22 +1263,32 @@ ) { NV_CHANNEL_ALLOC_PARAMS channelGPFIFOAllocParams; - NV_STATUS rmStatus = NV_OK; - NvU32 hClass; - RM_API *pRmApi = rmapiGetInterface(RMAPI_GPU_LOCK_INTERNAL); - KernelCE *pKCe; - NvBool bMIGInUse = IS_MIG_IN_USE(pGpu); - - NV_ASSERT_OK_OR_RETURN(_memUtilsGetCe_GM107(pGpu, hClientId, &pKCe)); - NV_ASSERT_OR_RETURN((pKCe != NULL), NV_ERR_INVALID_STATE); + NV_STATUS rmStatus = NV_OK; + NvU32 hClass; + RM_API *pRmApi = rmapiGetInterface(RMAPI_GPU_LOCK_INTERNAL); + NvBool bMIGInUse = IS_MIG_IN_USE(pGpu); + RM_ENGINE_TYPE engineType; + NvU32 flags = DRF_DEF(OS04, _FLAGS, _CHANNEL_SKIP_SCRUBBER, _TRUE); + if (pChannel->type == SWL_SCRUBBER_CHANNEL) + { + engineType = RM_ENGINE_TYPE_SEC2; + flags |= DRF_DEF(OS04, _FLAGS, _CC_SECURE, _TRUE); + } + else + { + KernelCE *pKCe = NULL; + NV_ASSERT_OK_OR_RETURN(_memUtilsGetCe_GM107(pGpu, hClientId, hDeviceId, &pKCe)); + NV_ASSERT_OR_RETURN((pKCe != NULL), NV_ERR_INVALID_STATE); + engineType = RM_ENGINE_TYPE_COPY(pKCe->publicID); + } portMemSet(&channelGPFIFOAllocParams, 0, sizeof(NV_CHANNEL_ALLOC_PARAMS)); channelGPFIFOAllocParams.hObjectError = hObjectError; channelGPFIFOAllocParams.hObjectBuffer = hObjectBuffer; channelGPFIFOAllocParams.gpFifoOffset = pChannel->pbGpuVA + pChannel->channelPbSize; channelGPFIFOAllocParams.gpFifoEntries = pChannel->channelNumGpFifioEntries; channelGPFIFOAllocParams.hContextShare = NV01_NULL_OBJECT; - channelGPFIFOAllocParams.flags = DRF_DEF(OS04, _FLAGS, _CHANNEL_SKIP_SCRUBBER, _TRUE); + channelGPFIFOAllocParams.flags = flags; channelGPFIFOAllocParams.hVASpace = pChannel->hVASpaceId; // @@ -1352,19 +1300,28 @@ KernelMIGManager *pKernelMIGManager = GPU_GET_KERNEL_MIG_MANAGER(pGpu); MIG_INSTANCE_REF ref; RM_ENGINE_TYPE localCe; + RsClient *pClient; + Device *pDevice; + + NV_ASSERT_OK_OR_RETURN( + serverGetClientUnderLock(&g_resServ, hClientId, &pClient)); + + NV_ASSERT_OK_OR_RETURN( + deviceGetByHandle(pClient, hDeviceId, &pDevice)); + NV_ASSERT_OK_OR_RETURN( - kmigmgrGetInstanceRefFromClient(pGpu, pKernelMIGManager, hClientId, &ref)); + kmigmgrGetInstanceRefFromDevice(pGpu, pKernelMIGManager, pDevice, &ref)); // Clear the Compute instance portion, if present ref = kmigmgrMakeGIReference(ref.pKernelMIGGpuInstance); NV_ASSERT_OK_OR_RETURN( kmigmgrGetGlobalToLocalEngineType(pGpu, pKernelMIGManager, ref, - RM_ENGINE_TYPE_COPY(pKCe->publicID), + engineType, &localCe)); channelGPFIFOAllocParams.engineType = gpuGetNv2080EngineType(localCe); } else { - channelGPFIFOAllocParams.engineType = NV2080_ENGINE_TYPE_COPY(pKCe->publicID); + channelGPFIFOAllocParams.engineType = gpuGetNv2080EngineType(engineType); } hClass = kfifoGetChannelClassId(pGpu, GPU_GET_KERNEL_FIFO(pGpu)); @@ -1401,7 +1358,8 @@ hDeviceId, hChannelId, hClass, - &channelGPFIFOAllocParams)); + &channelGPFIFOAllocParams, + sizeof(channelGPFIFOAllocParams))); cleanup: NV_ASSERT_OK_OR_CAPTURE_FIRST_ERROR(rmStatus, @@ -1441,29 +1399,32 @@ return NV_ERR_GENERIC; } + + NV_ASSERT_OR_RETURN(pChannel->pbCpuVA != NULL, NV_ERR_GENERIC); + NV_ASSERT_OR_RETURN(pChannel->pControlGPFifo != NULL, NV_ERR_GENERIC); + if (pChannel->isProgressChecked) { // if progress is checked insert the semaphore with freeToken as payload pChannel->finishPayload = freeToken; _ceChannelScheduleWork_GM107(pGpu, pMemoryManager, pChannel, - 0, 0, 0, /*src parameters*/ - base, ADDR_FBMEM, 0, /*dst parameters*/ + 0, 0, 0, // src parameters + base, ADDR_FBMEM, 0, // dst parameters size, - NV_FALSE, - NV_TRUE, - NV_FALSE /*scrubbing*/); - + NV_FALSE, // blocking + NV_TRUE, // insertFinishPayload + NV_FALSE); // memcopy } else { // issue a standard async scrub blocksPushed = _ceChannelScheduleWork_GM107(pGpu, pMemoryManager, pChannel, - 0, 0, 0, /*src parameters*/ - base, ADDR_FBMEM, 0, /*dst parameters*/ + 0, 0, 0, // src parameters + base, ADDR_FBMEM, 0, // dst parameters size, - NV_FALSE, - NV_FALSE, - NV_FALSE /*scrubbing*/); + NV_FALSE, // blocking + NV_FALSE, // insertFinishPayload + NV_FALSE); // memcopy } *pNumBlocks = blocksPushed; return NV_OK; @@ -1499,13 +1460,16 @@ } + NV_ASSERT_OR_RETURN(pChannel->pControlGPFifo != NULL, NV_ERR_GENERIC); + NV_ASSERT_OR_RETURN(pChannel->pbCpuVA != NULL, NV_ERR_GENERIC); + blocksPushed = _ceChannelScheduleWork_GM107(pGpu, pMemoryManager, pChannel, - 0, 0, 0, /*src parameters*/ - base, ADDR_FBMEM, 0, /*dst parameters*/ + 0, 0, 0, // src parameters + base, ADDR_FBMEM, 0, // dst parameters size, - NV_TRUE, - NV_FALSE, - NV_FALSE /*scrubbing*/); + NV_TRUE, // blocking + NV_FALSE, // insertFinishPayload + NV_FALSE); // memcopy if (blocksPushed > 0) { @@ -1523,10 +1487,10 @@ if (timeoutStatus == NV_ERR_TIMEOUT) { NV_PRINTF(LEVEL_ERROR, - "Timed Out wating for CE semaphore in blocking scrub!\n"); + "Timed Out waiting for CE semaphore\n"); NV_PRINTF(LEVEL_ERROR, - "GET=0x%x, PUT=0x%x, GPGET=0x%x, GPPET=0x%x\n", + "GET=0x%x, PUT=0x%x, GPGET=0x%x, GPPUT=0x%x\n", pChannel->pControlGPFifo->Get, pChannel->pControlGPFifo->Put, pChannel->pControlGPFifo->GPGet, @@ -1564,11 +1528,14 @@ { NvU32 blocksPushed = 0; + NV_ASSERT_OR_RETURN(pChannel->pbCpuVA != NULL, NV_ERR_GENERIC); + NV_ASSERT_OR_RETURN(pChannel->pControlGPFifo != NULL, NV_ERR_GENERIC); + blocksPushed = _ceChannelScheduleBatchWork_GM107(pGpu, pMemoryManager, pChannel, - 0, 0, 0, /*src parameters*/ - base, ADDR_FBMEM, 0, /*dst parameters*/ + 0, 0, 0, // src parameters + base, ADDR_FBMEM, 0, // dst parameters size, - NV_FALSE); /*scrubbing*/ + NV_FALSE); // memcopy if (blocksPushed > 0) { @@ -1586,10 +1553,10 @@ if (timeoutStatus == NV_ERR_TIMEOUT) { NV_PRINTF(LEVEL_ERROR, - "Timed Out wating for CE semaphore in blocking scrub!\n"); + "Timed Out waiting for CE semaphore!\n"); NV_PRINTF(LEVEL_ERROR, - "GET=0x%x, PUT=0x%x, GPGET=0x%x, GPPET=0x%x\n", + "GET=0x%x, PUT=0x%x, GPGET=0x%x, GPPUT=0x%x\n", MEM_RD32(&pChannel->pControlGPFifo->Get), MEM_RD32(&pChannel->pControlGPFifo->Put), MEM_RD32(&pChannel->pControlGPFifo->GPGet), @@ -1640,10 +1607,14 @@ NvU64 size ) { + NV_ASSERT_OR_RETURN(pChannel->pbCpuVA != NULL, NV_ERR_GENERIC); + NV_ASSERT_OR_RETURN(pChannel->pControlGPFifo != NULL, NV_ERR_GENERIC); + NvU32 blocksPushed = _ceChannelScheduleBatchWork_GM107(pGpu, pMemoryManager, pChannel, - src, srcAddressSpace, srcCpuCacheAttrib, /*src parameters*/ - dst, dstAddressSpace, dstCpuCacheAttrib, /*dst parameters*/ - size, NV_TRUE /*memcpy*/); + src, srcAddressSpace, srcCpuCacheAttrib, // src parameters + dst, dstAddressSpace, dstCpuCacheAttrib, // dst parameters + size, + NV_TRUE); // memcopy; if (blocksPushed > 0) { @@ -1663,7 +1634,7 @@ MEM_RD32(semAddr), pChannel->finishPayload); NV_PRINTF(LEVEL_INFO, - "GET=0x%x, PUT=0x%x, GPGET=0x%x, GPPET=0x%x\n", + "GET=0x%x, PUT=0x%x, GPGET=0x%x, GPPUT=0x%x\n", MEM_RD32(&pChannel->pControlGPFifo->Get), MEM_RD32(&pChannel->pControlGPFifo->Put), MEM_RD32(&pChannel->pControlGPFifo->GPGet), @@ -1672,10 +1643,10 @@ if (timeoutStatus == NV_ERR_TIMEOUT) { NV_PRINTF(LEVEL_ERROR, - "Timed Out wating for CE semaphore in blocking scrub!\n"); + "Timed Out waiting for CE semaphore\n"); NV_PRINTF(LEVEL_ERROR, - "GET=0x%x, PUT=0x%x, GPGET=0x%x, GPPET=0x%x\n", + "GET=0x%x, PUT=0x%x, GPGET=0x%x, GPPUT=0x%x\n", MEM_RD32(&pChannel->pControlGPFifo->Get), MEM_RD32(&pChannel->pControlGPFifo->Put), MEM_RD32(&pChannel->pControlGPFifo->GPGet), @@ -1774,7 +1745,8 @@ pEccSyncChannel->deviceId, pEccSyncChannel->bitMapSemVirtId, NV50_MEMORY_VIRTUAL, - &memAllocParams)); + &memAllocParams, + sizeof(memAllocParams))); lockStatus = rmGpuLocksAcquire(GPUS_LOCK_FLAGS_NONE, RM_LOCK_MODULES_MEM); @@ -1815,6 +1787,8 @@ NvU32 filledSpace; NvU32 avlblSpace; + NV_ASSERT_OR_RETURN(pChannel->pbCpuVA != NULL, 0); + if (pChannel->channelPutOffset >= MEM_RD32((NvU8*)pChannel->pbCpuVA + pChannel->semaOffset)) { filledSpace = (pChannel->channelPutOffset - MEM_RD32((NvU8*)pChannel->pbCpuVA + pChannel->semaOffset)); @@ -1870,6 +1844,8 @@ spaceInPb = pChannel->channelPbSize - pChannel->channelPutOffset; NV_ASSERT_OR_RETURN(spaceInPb >= pChannel->methodSizePerBlock, 0); + NV_ASSERT_OR_RETURN(pChannel->pbCpuVA != NULL, 0); + NV_ASSERT_OR_RETURN(pChannel->pControlGPFifo != NULL, 0); // Support for sending semaphore release only work. if (size > 0) @@ -1880,8 +1856,8 @@ ptr = (NvU32 *)(pChannel->pbCpuVA + pChannel->channelPutOffset); bytesPushed = _ceChannelPushMethodsBlock_GM107(pGpu, pMemoryManager, pChannel, - src, srcAddressSpace, srcCpuCacheAttrib, /*src parameters*/ - dst, dstAddressSpace, dstCpuCacheAttrib, /*dst parameters*/ + src, srcAddressSpace, srcCpuCacheAttrib, // src parameters + dst, dstAddressSpace, dstCpuCacheAttrib, // dst parameters size, &ptr, NV_FALSE, NV_FALSE, NV_FALSE, bMemcopy); pChannel->finishPayload += NvU64_LO32(size); NV_ASSERT(NvU64_HI32(size) == 0); @@ -1901,8 +1877,8 @@ ptr = (NvU32 *)(pChannel->pbCpuVA + pChannel->channelPutOffset); bytesPushed = _ceChannelPushMethodsBlock_GM107(pGpu, pMemoryManager, pChannel, - 0, 0, 0, /*src parameters*/ - 0, 0, 0, /*dst parameters*/ + 0, 0, 0, // src parameters + 0, 0, 0, // dst parameters 0, &ptr, NV_FALSE, NV_FALSE, NV_TRUE, bMemcopy); NV_ASSERT(bytesPushed != 0); @@ -1964,6 +1940,9 @@ NvBool addFinishPayload; NvU32 blockSize = 0; + NV_ASSERT_OR_RETURN(pChannel->pbCpuVA != NULL, 0); + NV_ASSERT_OR_RETURN(pChannel->pControlGPFifo != NULL, 0); + gpuSetTimeout(pGpu, GPU_TIMEOUT_DEFAULT, &timeout, 0); spaceInPb = _getSpaceInPb(pChannel); @@ -2025,8 +2004,8 @@ if(_checkSynchronization(pGpu, pMemoryManager, pChannel, BLOCK_INDEX_FROM_ADDR(dst, pChannel->blockShift))) { bytesPushed = _ceChannelPushMethodsBlock_GM107(pGpu, pMemoryManager, pChannel, - src, srcAddressSpace, srcCpuCacheAttrib, /*src parameters*/ - dst, dstAddressSpace, dstCpuCacheAttrib, /*dst parameters*/ + src, srcAddressSpace, srcCpuCacheAttrib, // src parameters + dst, dstAddressSpace, dstCpuCacheAttrib, // dst parameters blockSize, &ptr, NV_TRUE, (addNonStallIntr && !blocking), addFinishPayload, bMemcopy); spaceInPb = spaceInPb - bytesPushed; @@ -2142,6 +2121,9 @@ KernelChannel *pFifoKernelChannel; KernelFifo *pKernelFifo = GPU_GET_KERNEL_FIFO(pGpu); + NV_ASSERT_OR_RETURN_VOID(pChannel->pbCpuVA != NULL); + NV_ASSERT_OR_RETURN_VOID(pChannel->pControlGPFifo != NULL); + gpuSetTimeout(pGpu, GPU_TIMEOUT_DEFAULT, &timeout, 0); GPPut = MEM_RD32(&pChannel->pControlGPFifo->GPPut); GPGet = MEM_RD32(&pChannel->pControlGPFifo->GPGet); @@ -2218,7 +2200,7 @@ else { workSubmitToken = pChannel->workSubmitToken; - NV_ASSERT_OR_RETURN_VOID(CliGetKernelChannelWithDevice(pChannel->hClient, + NV_ASSERT_OR_RETURN_VOID(CliGetKernelChannelWithDevice(pChannel->pRsClient, pChannel->deviceId, pChannel->channelId, &pFifoKernelChannel) == NV_OK); } diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/kernel/gpu/mem_mgr/arch/maxwell/virt_mem_allocator_gm107.c nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/kernel/gpu/mem_mgr/arch/maxwell/virt_mem_allocator_gm107.c --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/kernel/gpu/mem_mgr/arch/maxwell/virt_mem_allocator_gm107.c 2023-10-25 20:21:10.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/kernel/gpu/mem_mgr/arch/maxwell/virt_mem_allocator_gm107.c 2024-03-05 22:13:34.000000000 +0000 @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 2005-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2005-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -265,6 +265,7 @@ Memory *pMemory; NvU32 pageArrayGranularity; NvU8 pageShift; + NvU64 physPageSize; } *pLocals = portMemAllocNonPaged(sizeof(*pLocals)); // Heap Allocate to avoid stack overflow @@ -321,7 +322,7 @@ addressTranslation = VAS_ADDRESS_TRANSLATION(pVAS); // In SRIOV-heavy plugin may map subheap allocations for itself using BAR1 - NV_ASSERT_OK_OR_RETURN(vgpuIsCallingContextPlugin(pGpu, &bCallingContextPlugin)); + NV_ASSERT_OK_OR_GOTO(status, vgpuIsCallingContextPlugin(pGpu, &bCallingContextPlugin), cleanup); if (bCallingContextPlugin) addressTranslation = FORCE_VMMU_TRANSLATION(pMemDesc, addressTranslation); @@ -337,39 +338,49 @@ // Get pageSize pLocals->pTempMemDesc = memdescGetMemDescFromGpu(pAdjustedMemDesc, pGpu); - pLocals->pageSize = memdescGetPageSize(pLocals->pTempMemDesc, addressTranslation); - // Get pte granularity + // Get physical allocation granularity and page size. pLocals->pageArrayGranularity = pLocals->pTempMemDesc->pageArrayGranularity; + pLocals->physPageSize = memdescGetPageSize(pLocals->pTempMemDesc, addressTranslation); - if (memdescGetFlag(pLocals->pTempMemDesc, MEMDESC_FLAGS_DEVICE_READ_ONLY)) + // retrieve mapping page size from flags + switch(DRF_VAL(OS46, _FLAGS, _PAGE_SIZE, flags)) { - NV_ASSERT_OR_ELSE((pLocals->readOnly == DMA_UPDATE_VASPACE_FLAGS_READ_ONLY), - status = NV_ERR_INVALID_ARGUMENT; goto cleanup); + case NVOS46_FLAGS_PAGE_SIZE_DEFAULT: + case NVOS46_FLAGS_PAGE_SIZE_BOTH: + pLocals->pageSize = memdescGetPageSize(pLocals->pTempMemDesc, addressTranslation); + break; + case NVOS46_FLAGS_PAGE_SIZE_4KB: + pLocals->pageSize = RM_PAGE_SIZE; + break; + case NVOS46_FLAGS_PAGE_SIZE_BIG: + // case for arch specific 128K + pLocals->pageSize = pLocals->vaspaceBigPageSize; + break; + case NVOS46_FLAGS_PAGE_SIZE_HUGE: + pLocals->pageSize = RM_PAGE_SIZE_HUGE; + break; + default: + NV_PRINTF(LEVEL_ERROR, "Unknown page size flag encountered during mapping\n"); + status = NV_ERR_INVALID_ARGUMENT; + goto cleanup; } - // For verify purposes we should allow small page override for mapping. - // This will be used for testing VASpace interop. - if (RMCFG_FEATURE_PLATFORM_MODS && - FLD_TEST_DRF(OS46, _FLAGS, _PAGE_SIZE, _4KB, flags) && - kgmmuIsVaspaceInteropSupported(pKernelGmmu)) + NV_PRINTF(LEVEL_INFO, "Picked Page size based on flags: 0x%llx flagVal: 0x%x\n", + pLocals->pageSize, DRF_VAL(OS46, _FLAGS, _PAGE_SIZE, flags)); + + if (pLocals->physPageSize < pLocals->pageSize) { - pLocals->pageSize = RM_PAGE_SIZE; - SLI_LOOP_START(SLI_LOOP_FLAGS_BC_ONLY | SLI_LOOP_FLAGS_IGNORE_REENTRANCY) - memdescSetPageSize(memdescGetMemDescFromGpu(pAdjustedMemDesc, pGpu), addressTranslation, (NvU32)pLocals->pageSize); - SLI_LOOP_END + NV_PRINTF(LEVEL_WARNING, "Requested mapping at larger page size than the physical granularity " + "PhysPageSize = 0x%llx MapPageSize = 0x%llx. Overriding to physical page granularity...\n", + pLocals->physPageSize, pLocals->pageSize); + pLocals->pageSize = pLocals->physPageSize; } - else if (kgmmuIsPerVaspaceBigPageEn(pKernelGmmu) && - (pLocals->pageSize >= RM_PAGE_SIZE_64K)) - { - NV_ASSERT(pLocals->pageSize != RM_PAGE_SIZE_HUGE); - // - // This is a temp WAR till the memdesc->_pageSize is cleaned up - // If the memdesc page size is >= the smallest big page size then - // we will correct it to the Big page size of the VASpace - // - pLocals->pageSize = pLocals->vaspaceBigPageSize; + if (memdescGetFlag(pLocals->pTempMemDesc, MEMDESC_FLAGS_DEVICE_READ_ONLY)) + { + NV_ASSERT_OR_ELSE((pLocals->readOnly == DMA_UPDATE_VASPACE_FLAGS_READ_ONLY), + status = NV_ERR_INVALID_ARGUMENT; goto cleanup); } // @@ -381,7 +392,7 @@ if (kgmmuIsVaspaceInteropSupported(pKernelGmmu) && pLocals->bIsBar1) { - if ((pLocals->pageSize > pLocals->vaspaceBigPageSize) && + if ((pLocals->pageSize > pLocals->vaspaceBigPageSize) && kbusIsBar1Force64KBMappingEnabled(pKernelBus)) { pLocals->pageSize = pLocals->vaspaceBigPageSize; @@ -412,6 +423,18 @@ if (NV_OK != status) goto cleanup; + // + // When compression is enabled mapping at 4K is not supported due to + // RM allocating one comptagline per 64KB allocation (From Pascal to Turing). + // See bug 3909010 + // + if ((pLocals->pageSize == RM_PAGE_SIZE) && + memmgrIsKind_HAL(pMemoryManager, FB_IS_KIND_COMPRESSIBLE, pLocals->kind)) + { + NV_PRINTF(LEVEL_WARNING, "Requested 4K mapping on compressible sufrace. Overriding to physical page granularity..."); + pLocals->pageSize = pLocals->physPageSize; + } + #ifdef DEBUG // Check for subdevices consistency if broadcast memdesc is passed in if (memdescHasSubDeviceMemDescs(pAdjustedMemDesc)) @@ -458,7 +481,9 @@ { // FIXME: This is broken for page size > 4KB and page offset // that crosses a page boundary (can overrun pPteArray). - pLocals->pteCount = pLocals->pageCount; + // -- + // page count is one more than integral division in case of presence of offset hence being rounded up + pLocals->pteCount = RM_ALIGN_UP((pLocals->pTempMemDesc->Size + pLocals->pageOffset), pLocals->pageArrayGranularity) >> BIT_IDX_32(pLocals->pageArrayGranularity); } // Disable PLC Compression for FLA->PA Mapping because of the HW Bug: 3046774 @@ -496,7 +521,7 @@ if (pLocals->bIsMemContiguous) { - pLocals->overMap = pLocals->pageCount + NvU64_LO32((pLocals->pageOffset + (pLocals->pageArrayGranularity - 1)) / pLocals->pageArrayGranularity); + pLocals->overMap = pLocals->pageCount + NvU64_LO32((pLocals->pageOffset + (pLocals->pageSize - 1)) / pLocals->pageSize); } else { @@ -605,13 +630,13 @@ NvU64 vaAlign = NV_MAX(pLocals->pageSize, compAlign); NvU64 vaSize = RM_ALIGN_UP(pLocals->mapLength, vaAlign); NvU64 pageSizeLockMask = 0; + pGVAS = dynamicCast(pVAS, OBJGVASPACE); if (FLD_TEST_DRF(OS46, _FLAGS, _PAGE_SIZE, _BOTH, flags)) { vaAlign = NV_MAX(vaAlign, pLocals->vaspaceBigPageSize); vaSize = RM_ALIGN_UP(pLocals->mapLength, vaAlign); } - // // Third party code path, nvidia_p2p_get_pages, expects on BAR1 VA to be // always aligned at 64K. @@ -641,6 +666,15 @@ goto cleanup; } } + if (pGVAS != NULL && gvaspaceIsInternalVaRestricted(pGVAS)) + { + if ((pLocals->vaRangeLo >= pGVAS->vaStartInternal && pLocals->vaRangeLo <= pGVAS->vaLimitInternal) || + (pLocals->vaRangeHi <= pGVAS->vaLimitInternal && pLocals->vaRangeHi >= pGVAS->vaStartInternal)) + { + status = NV_ERR_INVALID_PARAMETER; + goto cleanup; + } + } } else if (pDma->getProperty(pDma, PDB_PROP_DMA_RESTRICT_VA_RANGE)) { @@ -666,7 +700,6 @@ // Clients can pass an allocation flag to the device or VA space constructor // so that mappings and allocations will fail without an explicit address. // - pGVAS = dynamicCast(pVAS, OBJGVASPACE); if (pGVAS != NULL) { if ((pGVAS->flags & VASPACE_FLAGS_REQUIRE_FIXED_OFFSET) && @@ -676,6 +709,18 @@ NV_PRINTF(LEVEL_ERROR, "The VA space requires all allocations to specify a fixed address\n"); goto cleanup; } + + // + // Bug 3610538 clients can allocate GPU VA, during mapping for ctx dma. + // But if clients enable RM to map internal buffers in a reserved + // range of VA for unlinked SLI in Linux, we want to tag these + // allocations as "client allocated", so that it comes outside of + // RM internal region. + // + if (gvaspaceIsInternalVaRestricted(pGVAS)) + { + allocFlags.bClientAllocation = NV_TRUE; + } } status = vaspaceAlloc(pVAS, vaSize, vaAlign, pLocals->vaRangeLo, pLocals->vaRangeHi, @@ -926,6 +971,32 @@ SLI_LOOP_BREAK; } } + else if ((memdescGetAddressSpace(pLocals->pTempMemDesc) == ADDR_EGM)) + { + NV_ASSERT(memdescGetFlag(pLocals->pTempMemDesc, MEMDESC_FLAGS_ALLOC_FROM_EGM)); + + pLocals->aperture = NV_MMU_PTE_APERTURE_PEER_MEMORY; + + if (pLocals->p2p) + { + OBJGPU *pMappingGpu = pGpu; + OBJGPU *pPeerGpu; + + NV_ASSERT_OR_ELSE(pLocals->pMemory != NULL, status = NV_ERR_INVALID_STATE; goto cleanup); + + pPeerGpu = pLocals->pMemory->pGpu; + pLocals->peerNumber = kbusGetEgmPeerId_HAL(pMappingGpu, GPU_GET_KERNEL_BUS(pMappingGpu), pPeerGpu); + } + else + { + // + // Make sure that we receive a mapping request for EGM memory + // only if local EGM is enabled. + // + NV_ASSERT_OR_ELSE(pMemoryManager->bLocalEgmEnabled, status = NV_ERR_INVALID_STATE; goto cleanup); + pLocals->peerNumber = pMemoryManager->localEgmPeerId; + } + } else { // No P2P for system memory @@ -1027,9 +1098,15 @@ // *pVaddr = pLocals->vaLo + pLocals->pageOffset; + // Fill in the final mapping page size for client mappings. + if (pCliMapInfo != NULL) + { + pCliMapInfo->pDmaMappingInfo->mapPageSize = pLocals->pageSize; + } + SLI_LOOP_START(SLI_LOOP_FLAGS_BC_ONLY | SLI_LOOP_FLAGS_IGNORE_REENTRANCY) // This is needed for cliDB tracking of the map. - memdescSetPageSize(memdescGetMemDescFromGpu(pAdjustedMemDesc, pGpu), addressTranslation, NvU64_LO32(pLocals->pageSize)); + memdescSetPageSize(memdescGetMemDescFromGpu(pAdjustedMemDesc, pGpu), addressTranslation, pLocals->pageSize); SLI_LOOP_END } else @@ -1138,7 +1215,11 @@ } pTempMemDesc = memdescGetMemDescFromGpu(pMemDesc, pGpu); - pageSize = memdescGetPageSize(pTempMemDesc, VAS_ADDRESS_TRANSLATION(pVAS)); + + NV_ASSERT_OR_RETURN(pCliMapInfo != NULL, NV_ERR_INVALID_STATE); + NV_ASSERT_OR_RETURN(pCliMapInfo->pDmaMappingInfo->mapPageSize != 0, NV_ERR_INVALID_STATE); + + pageSize = pCliMapInfo->pDmaMappingInfo->mapPageSize; pageOffset = memdescGetPhysAddr(pTempMemDesc, VAS_ADDRESS_TRANSLATION(pVAS), 0) & (pageSize - 1); mapLength = RM_ALIGN_UP(pageOffset + pTempMemDesc->Size, pageSize); vaLo = RM_ALIGN_DOWN(vAddr, pageSize); @@ -1165,7 +1246,7 @@ NVLINK_INVALID_FABRIC_ADDR, deferInvalidate, NV_FALSE, - pageSize); + pageSize); if (status != NV_OK) { NV_PRINTF(LEVEL_ERROR, "error updating VA space.\n"); @@ -1319,39 +1400,37 @@ MMU_MAP_ITERATOR *pIter = pTarget->pIter; NvU8 *pMap = pIter->pMap; const NvU64 pageSize = mmuFmtLevelPageSize(pLevelFmt); - NvU32 bufferAdjust = 0; GMMU_ENTRY_VALUE entry; - NV_ASSERT_OR_RETURN_VOID(NULL != pMap); + NV_ASSERT_OR_RETURN_VOID(pMap != NULL); - if (NULL == pLevelMem) - { - // - // Calculate buffer adjustment to account for entryIndexLo in - // buffered mode. - // RM writes the user-supplied buffer starting at offset 0 - // even if the it is in middle of the page table. - // - bufferAdjust = entryIndexLo * pLevelFmt->entrySize; - } + // + // This function will always write the caller supplied buffer + // at offset 0. The onus of writing the buffer out to the target + // location in memory at the appropriate offset is on the caller. + // for (i = entryIndexLo; i <= entryIndexHi; ++i) { + NvU32 entryOffset = (i - entryIndexLo) * pLevelFmt->entrySize; + // Copy out current PTE if we are overwriting (Read-Modify-Write) if (pIter->bReadPtes) { - portMemCopy(entry.v8, pLevelFmt->entrySize, pMap + (i * pLevelFmt->entrySize), pLevelFmt->entrySize); + portMemCopy(entry.v8, pLevelFmt->entrySize, + &pMap[entryOffset], pLevelFmt->entrySize); } else { // Copy the static fields passed in, if we aren't overwriting a subset of fields. - portMemCopy(entry.v8, pLevelFmt->entrySize, pIter->pteTemplate, pLevelFmt->entrySize); + portMemCopy(entry.v8, pLevelFmt->entrySize, + pIter->pteTemplate, pLevelFmt->entrySize); } if (pIter->bApplyWarForBug2720120) { // Commit to memory. - portMemCopy(pMap + (i * pLevelFmt->entrySize) - bufferAdjust, pLevelFmt->entrySize, + portMemCopy(&pMap[entryOffset], pLevelFmt->entrySize, entry.v8, pLevelFmt->entrySize); continue; } @@ -1493,7 +1572,7 @@ } // Commit to memory. - portMemCopy(pMap + (i * pLevelFmt->entrySize) - bufferAdjust, pLevelFmt->entrySize, + portMemCopy(&pMap[entryOffset], pLevelFmt->entrySize, entry.v8, pLevelFmt->entrySize); // @@ -1519,22 +1598,35 @@ NvU32 *pProgress ) { - OBJGPU *pGpu = pUserCtx->pGpu; - MMU_MAP_ITERATOR *pIter = pTarget->pIter; - MEMORY_DESCRIPTOR *pMemDesc = (MEMORY_DESCRIPTOR*)pLevelMem; + OBJGPU *pGpu = pUserCtx->pGpu; + MemoryManager *pMemoryManager = GPU_GET_MEMORY_MANAGER(pGpu); + MMU_MAP_ITERATOR *pIter = pTarget->pIter; + MEMORY_DESCRIPTOR *pMemDesc = (MEMORY_DESCRIPTOR*)pLevelMem; + const MMU_FMT_LEVEL *pLevelFmt = pTarget->pLevelFmt; + TRANSFER_SURFACE surf = {0}; + NvU32 sizeOfEntries; NV_PRINTF(LEVEL_INFO, "[GPU%u]: PA 0x%llX, Entries 0x%X-0x%X\n", pUserCtx->pGpu->gpuInstance, memdescGetPhysAddr(pMemDesc, AT_GPU, 0), entryIndexLo, entryIndexHi); - pIter->pMap = kbusMapRmAperture_HAL(pGpu, pMemDesc); + surf.pMemDesc = pMemDesc; + surf.offset = entryIndexLo * pLevelFmt->entrySize; + + sizeOfEntries = (entryIndexHi - entryIndexLo + 1 ) * pLevelFmt->entrySize; + + pIter->pMap = memmgrMemBeginTransfer(pMemoryManager, &surf, sizeOfEntries, + TRANSFER_FLAGS_SHADOW_ALLOC | + TRANSFER_FLAGS_SHADOW_INIT_MEM); NV_ASSERT_OR_RETURN_VOID(NULL != pIter->pMap); _gmmuWalkCBMapNextEntries_Direct(pUserCtx, pTarget, pLevelMem, entryIndexLo, entryIndexHi, pProgress); - kbusUnmapRmAperture_HAL(pGpu, pMemDesc, &pIter->pMap, NV_TRUE); + memmgrMemEndTransfer(pMemoryManager, &surf, sizeOfEntries, + TRANSFER_FLAGS_SHADOW_ALLOC | + TRANSFER_FLAGS_SHADOW_INIT_MEM); } static NV_STATUS _dmaGetFabricAddress @@ -1602,7 +1694,7 @@ NvU64 fabricAddr, NvU32 deferInvalidate, NvBool bSparse, - NvU32 pageSize + NvU64 pageSize ) { KernelBus *pKernelBus = GPU_GET_KERNEL_BUS(pGpu); @@ -1616,15 +1708,16 @@ NvU32 priv; NvU32 writeDisable; NvU32 readDisable; - NvU32 vaSpaceBigPageSize = 0; + NvU64 vaSpaceBigPageSize = 0; + KernelMemorySystem *pKernelMemorySystem = GPU_GET_KERNEL_MEMORY_SYSTEM(pGpu); const MEMORY_SYSTEM_STATIC_CONFIG *pMemorySystemConfig = - kmemsysGetStaticConfig(pGpu, GPU_GET_KERNEL_MEMORY_SYSTEM(pGpu)); + kmemsysGetStaticConfig(pGpu, pKernelMemorySystem); NvU32 alignSize = pMemorySystemConfig->comprPageSize; KernelGmmu *pKernelGmmu = GPU_GET_KERNEL_GMMU(pGpu); NvBool bFillPteMem = !!(flags & DMA_UPDATE_VASPACE_FLAGS_FILL_PTE_MEM); NvBool bUnmap = !bFillPteMem && - (flags & DMA_UPDATE_VASPACE_FLAGS_UPDATE_VALID) && - (SF_VAL(_MMU, _PTE_VALID, valid) == NV_MMU_PTE_VALID_FALSE); + (flags & DMA_UPDATE_VASPACE_FLAGS_UPDATE_VALID) && + (SF_VAL(_MMU, _PTE_VALID, valid) == NV_MMU_PTE_VALID_FALSE); NvBool bIsIndirectPeer; VAS_PTE_UPDATE_TYPE update_type; @@ -1635,7 +1728,15 @@ readDisable = !!(flags & DMA_UPDATE_VASPACE_FLAGS_SHADER_WRITE_ONLY); bIsIndirectPeer = !!(flags & DMA_UPDATE_VASPACE_FLAGS_INDIRECT_PEER); - if (pGpu->bEnableBar1SparseForFillPteMemUnmap) + NV_ASSERT_OR_RETURN(pageSize, NV_ERR_INVALID_ARGUMENT); + + vaSpaceBigPageSize = vaspaceGetBigPageSize(pVAS); + if ((pageSize == RM_PAGE_SIZE_64K) || (pageSize == RM_PAGE_SIZE_128K)) + { + NV_ASSERT_OR_RETURN(pageSize == vaSpaceBigPageSize, NV_ERR_INVALID_STATE); + } + + if (pGpu->bEnableBar1SparseForFillPteMemUnmap) { OBJGVASPACE *pGVAS = dynamicCast(pVAS, OBJGVASPACE); if (bFillPteMem && @@ -1684,27 +1785,6 @@ encrypted = (flags & DMA_UPDATE_VASPACE_FLAGS_DISABLE_ENCRYPTION) ? 0 : memdescGetFlag(pMemDesc, MEMDESC_FLAGS_ENCRYPTED); - vaSpaceBigPageSize = vaspaceGetBigPageSize(pVAS); - pageSize = memdescGetPageSize(pMemDesc, VAS_ADDRESS_TRANSLATION(pVAS)); - NV_ASSERT_OR_RETURN(pageSize, NV_ERR_INVALID_ARGUMENT); - - if (kgmmuIsPerVaspaceBigPageEn(pKernelGmmu) && - (pageSize >= RM_PAGE_SIZE_64K)) - { - NV_ASSERT(pageSize != RM_PAGE_SIZE_HUGE); - NV_ASSERT(vaSpaceBigPageSize); - - // - // This is a temp WAR till the memdesc->_pageSize is cleaned up - // If the memdesc page size is >= the smallest big page size then - // we will correct it to the Big page size of the VASpace - // This will also set it to the correct size for the memDesc - // - pageSize = vaSpaceBigPageSize; - } - - NV_ASSERT_OR_RETURN(pageSize, NV_ERR_INVALID_ARGUMENT); - // Check this here so we don't have to in the loop(s) below as necessary. if ((flags & DMA_UPDATE_VASPACE_FLAGS_UPDATE_PADDR) && (pPageArray == NULL)) { @@ -1734,43 +1814,51 @@ } // - // VMM-TODO: Merge into PL1 traveral. + // If we have dynamic granularity page arrays enabled we will never + // encounter a case where a larger page granularity physical surface gets + // represented by a smaller granularity pageArray. // - // If the pageSize of the mapping != 4K then be sure that the 4k pages - // making up the big physical page are contiguous. This is currently - // necessary since pMemDesc->PteArray is always in terms of 4KB pages. - // Different large pages do not have to be contiguous with each other. - // This check isn't needed for contig allocations. - // - if (pPageArray && (pageSize != RM_PAGE_SIZE) && (pPageArray->count > 1) && - !(flags & DMA_UPDATE_VASPACE_FLAGS_SKIP_4K_PTE_CHECK)) + if (!pMemoryManager->bEnableDynamicGranularityPageArrays) { - NvU32 i, j; - RmPhysAddr pageAddr, pagePrevAddr; - - for (i = 0; i < pPageArray->count; i += j) + // + // VMM-TODO: Merge into PL1 traveral. + // + // If the pageSize of the mapping != 4K then be sure that the 4k pages + // making up the big physical page are contiguous. This is currently + // necessary since pMemDesc->PteArray is always in terms of 4KB pages. + // Different large pages do not have to be contiguous with each other. + // This check isn't needed for contig allocations. + // + if (pPageArray && (pageSize != RM_PAGE_SIZE) && (pPageArray->count > 1) && + !(flags & DMA_UPDATE_VASPACE_FLAGS_SKIP_4K_PTE_CHECK)) { - for (j = i + 1; j < pPageArray->count; j++) - { - pagePrevAddr = dmaPageArrayGetPhysAddr(pPageArray, j - 1); - pageAddr = dmaPageArrayGetPhysAddr(pPageArray, j); + NvU32 i, j; + RmPhysAddr pageAddr, pagePrevAddr; - if ((1 + (pagePrevAddr/(RM_PAGE_SIZE))) != - (pageAddr/(RM_PAGE_SIZE))) + for (i = 0; i < pPageArray->count; i += j) + { + for (j = i + 1; j < pPageArray->count; j++) { - NV_PRINTF(LEVEL_ERROR, - "MMU: given non-contig 4KB pages for %dkB mapping\n", - pageSize / 1024); - DBG_BREAKPOINT(); - return NV_ERR_GENERIC; - } + pagePrevAddr = dmaPageArrayGetPhysAddr(pPageArray, j - 1); + pageAddr = dmaPageArrayGetPhysAddr(pPageArray, j); - // Are we at the pageSize boundary yet? - if ((pageAddr + RM_PAGE_SIZE) - % pageSize == 0) - { - j++; - break; + if ((1 + (pagePrevAddr/(RM_PAGE_SIZE))) != + (pageAddr/(RM_PAGE_SIZE))) + { + NV_PRINTF(LEVEL_ERROR, + "MMU: given non-contig 4KB pages for %lldkB mapping\n", + pageSize / 1024); + DBG_BREAKPOINT(); + return NV_ERR_GENERIC; + } + + // Are we at the pageSize boundary yet? + if ((pageAddr + RM_PAGE_SIZE) + % pageSize == 0) + { + j++; + break; + } } } } @@ -1825,7 +1913,7 @@ // MMU_MAP_CTX mapTarget.pLevelFmt = mmuFmtFindLevelWithPageShift(pFmt->pRoot, - BIT_IDX_32(pageSize)); + BIT_IDX_64(pageSize)); mapTarget.pIter = &mapIter; mapTarget.MapNextEntries = _gmmuWalkCBMapNextEntries_RmAperture; mapTarget.pageArrayGranularity = pMemDesc->pageArrayGranularity; @@ -1849,6 +1937,13 @@ vaLo, vaHi)); } + if (kmemsysNeedInvalidateGpuCacheOnMap_HAL(pGpu, pKernelMemorySystem, isVolatile, aperture)) + { + kmemsysCacheOp_HAL(pGpu, pKernelMemorySystem, pMemDesc, + (aperture == NV_MMU_PTE_APERTURE_PEER_MEMORY) ? FB_CACHE_PEER_MEMORY : FB_CACHE_SYSTEM_MEMORY, + FB_CACHE_EVICT); + } + // Build PTE template if (pFmt->version == GMMU_FMT_VERSION_3) { @@ -2203,9 +2298,20 @@ vaAlign = NV_MAX(vaAlign, temp); } + // Set this first in case we ignore DMA_ALLOC_VASPACE_USE_RM_INTERNAL_VALIMITS next rangeLo = vaspaceGetVaStart(pVAS); rangeHi = vaspaceGetVaLimit(pVAS); + if (flagsForAlloc & DMA_ALLOC_VASPACE_USE_RM_INTERNAL_VALIMITS) + { + OBJGVASPACE *pGVAS = dynamicCast(pVAS, OBJGVASPACE); + if (pGVAS) + { + rangeLo = pGVAS->vaStartInternal; + rangeHi = pGVAS->vaLimitInternal; + } + } + // If trying to conserve 32bit address space, map RM buffers at 4GB+ if (pDma->getProperty(pDma, PDB_PROP_DMA_ENFORCE_32BIT_POINTER) && (pVASpaceHeap->free > NVBIT64(32))) diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/kernel/gpu/mem_mgr/arch/turing/mem_mgr_tu102.c nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/kernel/gpu/mem_mgr/arch/turing/mem_mgr_tu102.c --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/kernel/gpu/mem_mgr/arch/turing/mem_mgr_tu102.c 2023-10-25 20:21:10.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/kernel/gpu/mem_mgr/arch/turing/mem_mgr_tu102.c 2024-03-05 22:13:35.000000000 +0000 @@ -585,3 +585,64 @@ return size; } + + +/*! + * Calculates heap offset based on presence and size of console and CBC regions + * + * When GSP is in use, CBC is placed at the beginning of memory instead of the + * end, which means it must be taken into account when calculating where the + * heap starts. If the offset is successfully calculated, it is placed in the + * offset variable and NV_OK is returned + * + * @returns NV_STATUS + */ +NV_STATUS +memmgrCalculateHeapOffsetWithGSP_TU102 +( + OBJGPU *pGpu, + MemoryManager *pMemoryManager, + NvU32 *offset +) +{ + // The heap will be located after the Console and CBC regions if they are + // present. Zero, one, or both of them may be present. If Console and + // CBC regions are present, they are guaranteed to be in Regions 0 and 1. + // If only one is present, then it is guaranteed to be in Region 0. As an + // extra check, it should be validated that these regions are indeed + // reserved + KernelMemorySystem *pKernelMemorySystem = GPU_GET_KERNEL_MEMORY_SYSTEM(pGpu); + FB_REGION_DESCRIPTOR *pFbRegion0 = &pMemoryManager->Ram.fbRegion[0]; + FB_REGION_DESCRIPTOR *pFbRegion1 = &pMemoryManager->Ram.fbRegion[1]; + + NvBool isConsoleRegionPresent = pMemoryManager->Ram.ReservedConsoleDispMemSize != 0; + NvBool isCbcRegionPresent = !pKernelMemorySystem->pStaticConfig->bDisableCompbitBacking; + + // Both regions in use + if (isCbcRegionPresent && isConsoleRegionPresent && + pFbRegion0->bRsvdRegion && pFbRegion1->bRsvdRegion) + { + // Use Region 1 limit and safely convert to KB + *offset = NvU64_LO32((pFbRegion1->limit + 1) >> 10); + NV_ASSERT_OR_RETURN(((NvU64) *offset << 10ULL) == (pFbRegion1->limit + 1), + NV_ERR_INVALID_DATA); + } + + // One region in use + else if ((isCbcRegionPresent || isConsoleRegionPresent) && + pFbRegion0->bRsvdRegion) + { + // Use Region 0 limit and safely convert to KB + *offset = NvU64_LO32((pFbRegion0->limit + 1) >> 10); + NV_ASSERT_OR_RETURN(((NvU64) *offset << 10ULL) == (pFbRegion0->limit + 1), + NV_ERR_INVALID_DATA); + } + + // Neither region in use, return NOT_SUPPORTED to fall back to default calculation + else + { + return NV_ERR_NOT_SUPPORTED; + } + + return NV_OK; +} \ No newline at end of file diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/kernel/gpu/mem_mgr/arch/volta/mem_mgr_gv100.c nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/kernel/gpu/mem_mgr/arch/volta/mem_mgr_gv100.c --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/kernel/gpu/mem_mgr/arch/volta/mem_mgr_gv100.c 2023-10-25 20:21:10.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/kernel/gpu/mem_mgr/arch/volta/mem_mgr_gv100.c 2024-03-05 22:13:35.000000000 +0000 @@ -50,7 +50,8 @@ pChannel->subdeviceId, pChannel->doorbellRegionHandle, VOLTA_USERMODE_A, - NULL); + NULL, + 0); if (status != NV_OK) goto exit; @@ -115,8 +116,8 @@ } else { - // TODO: Remove the PMA check after enabling on all chips. - if (memmgrIsPmaInitialized(pMemoryManager)) + if (memmgrIsPmaEnabled(pMemoryManager) && + memmgrIsPmaSupportedOnPlatform(pMemoryManager)) { // // Increase the context size by 120 MB. diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/kernel/gpu/mem_mgr/ce_utils.c nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/kernel/gpu/mem_mgr/ce_utils.c --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/kernel/gpu/mem_mgr/ce_utils.c 1970-01-01 00:00:00.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/kernel/gpu/mem_mgr/ce_utils.c 2024-03-05 22:13:35.000000000 +0000 @@ -0,0 +1,802 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + + +#include "core/core.h" +#include "gpu/ce/kernel_ce.h" +#include "gpu/bus/kern_bus.h" +#include "kernel/gpu/intr/intr.h" +#include "kernel/gpu/fifo/kernel_fifo.h" +#include "kernel/gpu/mig_mgr/kernel_mig_manager.h" +#include "kernel/gpu/mem_mgr/channel_utils.h" +#include "rmapi/rs_utils.h" +#include "utils/nvassert.h" +#include "core/prelude.h" +#include "core/locks.h" +#include "gpu/mem_mgr/ce_utils.h" +#include "gpu/subdevice/subdevice.h" +#include "kernel/gpu/mem_mgr/ce_utils_sizes.h" +#include "vgpu/rpc_headers.h" + +#include "class/clb0b5.h" // MAXWELL_DMA_COPY_A +#include "class/clc0b5.h" // PASCAL_DMA_COPY_A +#include "class/clc1b5.h" // PASCAL_DMA_COPY_B +#include "class/clc3b5.h" // VOLTA_DMA_COPY_A +#include "class/clc5b5.h" // TURING_DMA_COPY_A +#include "class/clc8b5.h" // HOPPER_DMA_COPY_A +#include "class/clc86f.h" // HOPPER_CHANNEL_GPFIFO_A + +#include "class/cl0080.h" + +NV_STATUS +ceutilsConstruct_IMPL +( + CeUtils *pCeUtils, + OBJGPU *pGpu, + KERNEL_MIG_GPU_INSTANCE *pKernelMIGGPUInstance, + NV0050_ALLOCATION_PARAMETERS *pAllocParams +) +{ + NV_STATUS status = NV_OK; + NvU64 allocFlags = pAllocParams->flags; + NV_ASSERT_OR_RETURN(pGpu, NV_ERR_INVALID_STATE); + + NvBool bMIGInUse = IS_MIG_IN_USE(pGpu); + MemoryManager *pMemoryManager = GPU_GET_MEMORY_MANAGER(pGpu); + + // Allocate channel with RM internal client + RM_API *pRmApi = rmapiGetInterface(RMAPI_GPU_LOCK_INTERNAL); + RmClient *pClient; + + OBJCHANNEL *pChannel = (OBJCHANNEL *) portMemAllocNonPaged(sizeof(OBJCHANNEL)); + if (pChannel == NULL) + { + return NV_ERR_INSUFFICIENT_RESOURCES; + } + + portMemSet(pChannel, 0, sizeof(OBJCHANNEL)); + + if (pCeUtils->hClient == NV01_NULL_OBJECT) + { + // Allocate client + status = pRmApi->AllocWithHandle(pRmApi, NV01_NULL_OBJECT, NV01_NULL_OBJECT, + NV01_NULL_OBJECT, NV01_ROOT, &pCeUtils->hClient, + sizeof(pCeUtils->hClient)); + NV_ASSERT_OR_GOTO(status == NV_OK, cleanup); + } + + pChannel->hClient = pCeUtils->hClient; + pClient = serverutilGetClientUnderLock(pChannel->hClient); + NV_ASSERT_OR_GOTO(pClient != NULL, free_client); + + status = serverGetClientUnderLock(&g_resServ, pChannel->hClient, &pChannel->pRsClient); + NV_ASSERT_OR_GOTO(status == NV_OK, free_client); + + if (IS_VIRTUAL(pGpu)) + { + NV_ASSERT_OK_OR_GOTO( + status, + clientSetHandleGenerator(staticCast(pClient, RsClient), RS_UNIQUE_HANDLE_BASE, + RS_UNIQUE_HANDLE_RANGE/2 - VGPU_RESERVED_HANDLE_RANGE), + free_client); + } + else + { + NV_ASSERT_OK_OR_GOTO( + status, + clientSetHandleGenerator(staticCast(pClient, RsClient), 1U, ~0U - 1U), + free_client); + } + + pChannel->bClientAllocated = NV_TRUE; + pChannel->pGpu = pGpu; + + pChannel->deviceId = pCeUtils->hDevice; + pChannel->subdeviceId = pCeUtils->hSubdevice; + + pChannel->pKernelMIGGpuInstance = pKernelMIGGPUInstance; + + // We'll allocate new VAS for now. Sharing client VAS will be added later + pChannel->hVASpaceId = NV01_NULL_OBJECT; + pChannel->bUseVasForCeCopy = FLD_TEST_DRF(0050_CEUTILS, _FLAGS, _VIRTUAL_MODE, _TRUE, allocFlags); + + // Detect if we can enable fast scrub on this channel + status = memmgrMemUtilsGetCopyEngineClass_HAL(pGpu, pMemoryManager, &pCeUtils->hTdCopyClass); + NV_ASSERT_OR_GOTO(status == NV_OK, free_channel); + + if (((pCeUtils->hTdCopyClass == HOPPER_DMA_COPY_A) + ) && !pChannel->bUseVasForCeCopy) + { + pChannel->type = FAST_SCRUBBER_CHANNEL; + NV_PRINTF(LEVEL_INFO, "Enabled fast scrubber in construct.\n"); + } + else + { + pChannel->type = CE_SCRUBBER_CHANNEL; + } + + // Set up various channel resources + status = channelSetupIDs(pChannel, pGpu, pChannel->bUseVasForCeCopy, bMIGInUse); + NV_ASSERT_OR_GOTO(status == NV_OK, free_client); + + channelSetupChannelBufferSizes(pChannel); + + status = memmgrMemUtilsChannelInitialize_HAL(pGpu, pMemoryManager, pChannel); + NV_ASSERT_OR_GOTO(status == NV_OK, free_channel); + + NV_PRINTF(LEVEL_INFO, "Channel alloc successful for ceUtils\n"); + pCeUtils->pChannel = pChannel; + + // Allocate CE states + status = memmgrMemUtilsCopyEngineInitialize_HAL(pGpu, pMemoryManager, pChannel); + NV_ASSERT_OR_GOTO(status == NV_OK, free_channel); + + pCeUtils->pGpu = pGpu; + + return status; + +free_channel: + pRmApi->Free(pRmApi, pChannel->hClient, pChannel->channelId); + + if (pAllocParams->hVaspace != NV01_NULL_OBJECT) + { + pRmApi->Free(pRmApi, pChannel->hClient, pChannel->hVASpaceId); + } +free_client: + if (FLD_TEST_DRF(0050_CEUTILS, _FLAGS, _EXTERNAL, _FALSE, allocFlags)) + { + // If client allocated client, we should not free it in RM + pRmApi->Free(pRmApi, pChannel->hClient, pChannel->hClient); + } + +cleanup: + portMemFree(pChannel); + return status; +} + +void +ceutilsDestruct_IMPL +( + CeUtils *pCeUtils +) +{ + OBJCHANNEL *pChannel = pCeUtils->pChannel; + OBJGPU *pGpu = pCeUtils->pGpu; + MemoryManager *pMemoryManager = GPU_GET_MEMORY_MANAGER(pGpu); + RM_API *pRmApi = rmapiGetInterface(RMAPI_GPU_LOCK_INTERNAL); + + // Sanity checks + if ((pGpu == NULL) || (pChannel == NULL)) + { + NV_PRINTF(LEVEL_WARNING, "Possible double-free of CeUtils!\n"); + return; + } + else if (pGpu != pChannel->pGpu) + { + NV_PRINTF(LEVEL_ERROR, "Bad state during ceUtils teardown!\n"); + return; + } + + if ((pChannel->bClientUserd) && (pChannel->pControlGPFifo != NULL)) + { + if (kbusIsBarAccessBlocked(GPU_GET_KERNEL_BUS(pGpu))) + { + // + // When PCIE is blocked, mappings should be created, used and torn + // down when they are used + // + NV_PRINTF(LEVEL_ERROR, "Leaked USERD mapping from ceUtils!\n"); + } + else + { + memmgrMemDescEndTransfer(pMemoryManager, pChannel->pUserdMemdesc, TRANSFER_FLAGS_USE_BAR1); + pChannel->pControlGPFifo = NULL; + } + } + + if (pChannel->pbCpuVA != NULL) + { + if (kbusIsBarAccessBlocked(GPU_GET_KERNEL_BUS(pGpu))) + { + NV_PRINTF(LEVEL_ERROR, "Leaked pushbuffer mapping!\n"); + } + else + { + memmgrMemDescEndTransfer(pMemoryManager, pChannel->pChannelBufferMemdesc, TRANSFER_FLAGS_USE_BAR1); + pChannel->pbCpuVA = NULL; + } + } + + if (pChannel->pTokenFromNotifier != NULL) + { + if (kbusIsBarAccessBlocked(GPU_GET_KERNEL_BUS(pGpu))) + { + NV_PRINTF(LEVEL_ERROR, "Leaked notifier mapping!\n"); + } + else + { + memmgrMemDescEndTransfer(pMemoryManager, pChannel->pErrNotifierMemdesc, TRANSFER_FLAGS_USE_BAR1); + pChannel->pTokenFromNotifier = NULL; + } + } + + // Resource server makes sure no leak can occur + pRmApi->Free(pRmApi, pChannel->hClient, pChannel->hClient); + portMemFree(pChannel); +} + +void +ceutilsServiceInterrupts_IMPL(CeUtils *pCeUtils) +{ + OBJCHANNEL *pChannel = pCeUtils->pChannel; + + // + // FIXME: Bug 2463959: objmemscrub is called with the rmDeviceGpuLock in the + // heapFree_IMPL->_stdmemPmaFree->pmaFreePages->scrubSubmitPages path. + // Yielding while holding the rmDeviceGpuLock can lead to deadlock. Instead, + // if the lock is held, service any interrupts on the owned CE to make progress. + // Bug 2527660 is filed to remove this change. + // + // pChannel is null when PMA scrub requests are handled in vGPU plugin. + // In this case vGpu plugin allocates scrubber channel in PF domain so + // above mention deadlock is not present here. + // + if ((pChannel != NULL) && (rmDeviceGpuLockIsOwner(pChannel->pGpu->gpuInstance))) + { + channelServiceScrubberInterrupts(pChannel); + } + else + { + osSchedule(); + } +} + + +static NvBool +_ceUtilsFastScrubEnabled +( + POBJCHANNEL pChannel, + CHANNEL_PB_INFO *pChannelPbInfo +) +{ + OBJGPU *pGpu = pChannel->pGpu; + MemoryManager *pMemoryManager = GPU_GET_MEMORY_MANAGER(pGpu); + + if (!memmgrIsFastScrubberEnabled(pMemoryManager)) + { + return NV_FALSE; + } + + // + // Enable the memory fast scrubbing only when + // Channel was allocated as fastScrub channel + // We are doing a memset operation + // Memset pattern is 0 + // DstPhysMode.target == LOCAL_FB + // Address is 4KB aligned + // LineLength is 4KB aligned + // + + return ((pChannel->type == FAST_SCRUBBER_CHANNEL) && + (!pChannelPbInfo->bCeMemcopy) && + (pChannelPbInfo->pattern == 0) && + (pChannelPbInfo->dstAddressSpace == ADDR_FBMEM) && + (NV_IS_ALIGNED64(pChannelPbInfo->dstAddr, MEMUTIL_SCRUB_OFFSET_ALIGNMENT)) && + (NV_IS_ALIGNED(pChannelPbInfo->size, MEMUTIL_SCRUB_LINE_LENGTH_ALIGNMENT))); +} + + +// +// Helper to deal with CE_MAX_BYTES_PER_LINE +// This function may modify some fileds in pChannelPbInfo +// +static NV_STATUS +_ceutilsSubmitPushBuffer +( + POBJCHANNEL pChannel, + NvBool bPipelined, + NvBool bInsertFinishPayload, + CHANNEL_PB_INFO * pChannelPbInfo +) +{ + NV_STATUS status = NV_OK; + NvU32 methodsLength, putIndex = 0; + + NV_ASSERT_OR_RETURN(pChannelPbInfo != NULL, NV_ERR_INVALID_ARGUMENT); + NV_ASSERT_OR_RETURN(pChannel != NULL, NV_ERR_INVALID_ARGUMENT); + + MemoryManager *pMemoryManager = GPU_GET_MEMORY_MANAGER(pChannel->pGpu); + NvBool bReleaseMapping = NV_FALSE; + + // + // Use BAR1 if CPU access is allowed, otherwise allocate and init shadow + // buffer for DMA access + // + NvU32 transferFlags = (TRANSFER_FLAGS_USE_BAR1 | + TRANSFER_FLAGS_SHADOW_ALLOC | + TRANSFER_FLAGS_SHADOW_INIT_MEM); + NV_PRINTF(LEVEL_INFO, "Actual size of copying to be pushed: %x\n", pChannelPbInfo->size); + + status = channelWaitForFreeEntry(pChannel, &putIndex); + if (status != NV_OK) + { + NV_PRINTF(LEVEL_ERROR, "Cannot get putIndex.\n"); + return status; + } + + if (pChannel->pbCpuVA == NULL) + { + pChannel->pbCpuVA = memmgrMemDescBeginTransfer(pMemoryManager, pChannel->pChannelBufferMemdesc, + transferFlags); + bReleaseMapping = NV_TRUE; + } + NV_ASSERT_OR_RETURN(pChannel->pbCpuVA != NULL, NV_ERR_GENERIC); + + if (_ceUtilsFastScrubEnabled(pChannel, pChannelPbInfo)) + { + methodsLength = channelFillPbFastScrub(pChannel, putIndex, bPipelined, bInsertFinishPayload, pChannelPbInfo); + } + else + { + methodsLength = channelFillCePb(pChannel, putIndex, bPipelined, bInsertFinishPayload, pChannelPbInfo); + } + + if (bReleaseMapping) + { + memmgrMemDescEndTransfer(pMemoryManager, pChannel->pChannelBufferMemdesc, transferFlags); + pChannel->pbCpuVA = NULL; + } + + if (methodsLength == 0) + { + NV_PRINTF(LEVEL_ERROR, "Cannot push methods to channel.\n"); + return NV_ERR_NO_FREE_FIFOS; + } + + // + // Pushbuffer can be written in a batch, but GPFIFO and doorbell require + // careful ordering so we do each write one-by-one + // + status = channelFillGpFifo(pChannel, putIndex, methodsLength); + if (status != NV_OK) + { + NV_PRINTF(LEVEL_ERROR, "Channel operation failures during memcopy\n"); + return status; + } + + pChannel->lastSubmittedEntry = putIndex; + + return status; +} + + +NV_STATUS +ceutilsMemset_IMPL +( + CeUtils *pCeUtils, + CEUTILS_MEMSET_PARAMS *pParams +) +{ + OBJCHANNEL *pChannel = pCeUtils->pChannel; + NV_STATUS status = NV_OK; + + NvU32 pteArraySize; + NvU64 offset, memsetLength, size, pageGranularity; + NvBool bContiguous; + + MEMORY_DESCRIPTOR *pMemDesc = pParams->pMemDesc; + CHANNEL_PB_INFO channelPbInfo = {0}; + + NvBool bPipelined = pParams->flags & NV0050_CTRL_MEMSET_FLAGS_PIPELINED; + + if (pMemDesc == NULL) + { + NV_PRINTF(LEVEL_ERROR, "Invalid memdesc for CeUtils memset.\n"); + return NV_ERR_INVALID_ARGUMENT; + } + + if ((memdescGetAddressSpace(pMemDesc) != ADDR_FBMEM) || + (pMemDesc->pGpu != pCeUtils->pChannel->pGpu)) + { + NV_PRINTF(LEVEL_ERROR, "Invalid memory descriptor passed.\n"); + return NV_ERR_INVALID_ARGUMENT; + } + + size = memdescGetSize(pMemDesc); + pteArraySize = memdescGetPteArraySize(pMemDesc, AT_GPU); + bContiguous = (pMemDesc->_flags & MEMDESC_FLAGS_PHYSICALLY_CONTIGUOUS) || (pteArraySize == 1); + + if (pParams->offset >= size) + { + NV_PRINTF(LEVEL_ERROR, "Invalid offset passed for the memdesc.\n"); + return NV_ERR_INVALID_ARGUMENT; + } + + NV_PRINTF(LEVEL_INFO, "CeUtils Args to memset - offset: %llx, size: %llx \n", + pParams->offset, pParams->length); + + if ((pParams->length == 0) || (pParams->length > (size - pParams->offset))) + { + NV_PRINTF(LEVEL_ERROR, "Invalid memset length passed.\n"); + return NV_ERR_INVALID_ARGUMENT; + } + + channelPbInfo.bCeMemcopy = NV_FALSE; + channelPbInfo.payload = pCeUtils->lastSubmittedPayload + 1; + pCeUtils->lastSubmittedPayload = channelPbInfo.payload; + + channelPbInfo.pattern = pParams->pattern; + channelPbInfo.dstAddressSpace = memdescGetAddressSpace(pMemDesc); + channelPbInfo.dstCpuCacheAttrib = pMemDesc->_cpuCacheAttrib; + + pageGranularity = pMemDesc->pageArrayGranularity; + memsetLength = pParams->length; + offset = pParams->offset; + + do + { + NvU64 maxContigSize = bContiguous ? memsetLength : (pageGranularity - offset % pageGranularity); + NvU32 memsetSizeContig = (NvU32)NV_MIN(NV_MIN(memsetLength, maxContigSize), CE_MAX_BYTES_PER_LINE); + + channelPbInfo.dstAddr = memdescGetPhysAddr(pMemDesc, AT_GPU, offset); + + NV_PRINTF(LEVEL_INFO, "CeUtils Memset dstAddr: %llx, size: %x\n", + channelPbInfo.dstAddr, memsetSizeContig); + + channelPbInfo.size = memsetSizeContig; + status = _ceutilsSubmitPushBuffer(pChannel, bPipelined, memsetSizeContig == memsetLength, &channelPbInfo); + if (status != NV_OK) + { + NV_PRINTF(LEVEL_ERROR, "Cannot submit push buffer for memset.\n"); + return status; + } + + // Allow _LAUNCH_DMA methods that belong to the same memset operation to be pipelined after each other, as there are no dependencies + bPipelined = NV_TRUE; + + memsetLength -= memsetSizeContig; + offset += memsetSizeContig; + } while (memsetLength != 0); + + if (pParams->flags & NV0050_CTRL_MEMSET_FLAGS_ASYNC) + { + NV_PRINTF(LEVEL_INFO, "Async memset payload returned: 0x%x\n", channelPbInfo.payload); + pParams->submittedWorkId = channelPbInfo.payload; + } + else + { + // Check semaProgress and then timeout + status = channelWaitForFinishPayload(pChannel, channelPbInfo.payload); + if (status == NV_OK) + { + NV_PRINTF(LEVEL_INFO, "Work was done from RM PoV lastSubmitted = 0x%x\n", channelPbInfo.payload); + } + } + + return status; +} + +NV_STATUS +ceutilsMemcopy_IMPL +( + CeUtils *pCeUtils, + CEUTILS_MEMCOPY_PARAMS *pParams +) +{ + OBJCHANNEL *pChannel = pCeUtils->pChannel; + NV_STATUS status = NV_OK; + + NvU64 srcSize, dstSize, copyLength, srcPageGranularity, dstPageGranularity; + NvBool bSrcContig, bDstContig; + + CHANNEL_PB_INFO channelPbInfo = {0}; + MEMORY_DESCRIPTOR *pDstMemDesc = pParams->pDstMemDesc; + MEMORY_DESCRIPTOR *pSrcMemDesc = pParams->pSrcMemDesc; + + NvU64 length = pParams->length; + NvU64 srcOffset = pParams->srcOffset; + NvU64 dstOffset = pParams->dstOffset; + + NvBool bPipelined = pParams->flags & NV0050_CTRL_MEMCOPY_FLAGS_PIPELINED; + + // Validate params + if ((pSrcMemDesc == NULL) || (pDstMemDesc == NULL)) + { + NV_PRINTF(LEVEL_ERROR, "Src/Dst Memory descriptor should be valid.\n"); + return NV_ERR_INVALID_ARGUMENT; + } + + if ((memdescGetAddressSpace(pSrcMemDesc) != ADDR_FBMEM) && + (memdescGetAddressSpace(pDstMemDesc) != ADDR_FBMEM)) + { + NV_PRINTF(LEVEL_ERROR, "Either Dst or Src memory should be in vidmem.\n"); + return NV_ERR_INVALID_ARGUMENT; + } + + if ((pSrcMemDesc->pGpu != pCeUtils->pChannel->pGpu) || + (pDstMemDesc->pGpu != pCeUtils->pChannel->pGpu)) + { + NV_PRINTF(LEVEL_ERROR, "CeUtils does not support p2p copies right now. \n"); + return NV_ERR_INVALID_ARGUMENT; + } + + srcSize = memdescGetSize(pSrcMemDesc); + dstSize = memdescGetSize(pDstMemDesc); + + if ((srcOffset >= srcSize) || (dstOffset >= dstSize)) + { + NV_PRINTF(LEVEL_ERROR, "Invalid offset passed for the src/dst memdesc.\n"); + return NV_ERR_INVALID_ARGUMENT; + } + + if ((length == 0) || + (srcOffset + length > srcSize) || (dstOffset + length > dstSize)) + { + NV_PRINTF(LEVEL_ERROR, "Invalid memcopy length.\n"); + return NV_ERR_INVALID_ARGUMENT; + } + + channelPbInfo.bCeMemcopy = NV_TRUE; + channelPbInfo.payload = pCeUtils->lastSubmittedPayload + 1; + pCeUtils->lastSubmittedPayload = channelPbInfo.payload; + + channelPbInfo.srcAddressSpace = memdescGetAddressSpace(pSrcMemDesc); + channelPbInfo.dstAddressSpace = memdescGetAddressSpace(pDstMemDesc); + + channelPbInfo.srcCpuCacheAttrib = pSrcMemDesc->_cpuCacheAttrib; + channelPbInfo.dstCpuCacheAttrib = pDstMemDesc->_cpuCacheAttrib; + + srcPageGranularity = pSrcMemDesc->pageArrayGranularity; + dstPageGranularity = pDstMemDesc->pageArrayGranularity; + bSrcContig = memdescGetContiguity(pSrcMemDesc, AT_GPU); + bDstContig = memdescGetContiguity(pDstMemDesc, AT_GPU); + + copyLength = length; + + do + { + // + // This algorithm finds the maximum contig region from both src and dst + // for each copy and iterate until we submitted the whole range to CE + // + NvU64 maxContigSizeSrc = bSrcContig ? copyLength : (srcPageGranularity - srcOffset % srcPageGranularity); + NvU64 maxContigSizeDst = bDstContig ? copyLength : (dstPageGranularity - dstOffset % dstPageGranularity); + NvU32 copySizeContig = (NvU32)NV_MIN(NV_MIN(copyLength, NV_MIN(maxContigSizeSrc, maxContigSizeDst)), CE_MAX_BYTES_PER_LINE); + + channelPbInfo.srcAddr = memdescGetPhysAddr(pSrcMemDesc, AT_GPU, srcOffset); + channelPbInfo.dstAddr = memdescGetPhysAddr(pDstMemDesc, AT_GPU, dstOffset); + + NV_PRINTF(LEVEL_INFO, "CeUtils Memcopy dstAddr: %llx, srcAddr: %llx, size: %x\n", + channelPbInfo.dstAddr, channelPbInfo.srcAddr, copySizeContig); + + channelPbInfo.size = copySizeContig; + status = _ceutilsSubmitPushBuffer(pChannel, bPipelined, copySizeContig == copyLength, &channelPbInfo); + if (status != NV_OK) + { + NV_PRINTF(LEVEL_ERROR, "Cannot submit push buffer for memcopy.\n"); + return status; + } + + // Allow _LAUNCH_DMA methods that belong to the same copy operation to be pipelined after each other, as there are no dependencies + bPipelined = NV_TRUE; + + copyLength -= copySizeContig; + srcOffset += copySizeContig; + dstOffset += copySizeContig; + } while (copyLength != 0); + + if (pParams->flags & NV0050_CTRL_MEMSET_FLAGS_ASYNC) + { + NV_PRINTF(LEVEL_INFO, "Async memset payload returned: 0x%x\n", channelPbInfo.payload); + pParams->submittedWorkId = channelPbInfo.payload; + } + else + { + // Check semaProgress and then timeout + status = channelWaitForFinishPayload(pChannel, channelPbInfo.payload); + if (status == NV_OK) + { + NV_PRINTF(LEVEL_INFO, "Work was done from RM PoV lastSubmitted = 0x%x\n", channelPbInfo.payload); + } + } + + return status; +} + + +// This function updates pCeUtils->lastCompletedPayload and handles wrap-around +NvU64 +ceutilsUpdateProgress_IMPL +( + CeUtils *pCeUtils +) +{ + NV_ASSERT((pCeUtils != NULL) && (pCeUtils->pChannel != NULL)); + + NvU32 hwCurrentCompletedPayload = 0; + NvU64 swLastCompletedPayload = pCeUtils->lastCompletedPayload; + + // + // CeUtils uses 64 bit index to track the work submitted. But HW supports + // only 32 bit semaphore. The current completed Id is calculated here, based + // on the lastSubmittedPayload and current HW semaphore value. + // + hwCurrentCompletedPayload = READ_CHANNEL_PAYLOAD_SEMA(pCeUtils->pChannel); + + // No work has been completed since we checked last time + if (hwCurrentCompletedPayload == (NvU32)swLastCompletedPayload) + { + return swLastCompletedPayload; + } + + // Check for wrap around case. Increment the upper 32 bits + if (hwCurrentCompletedPayload < (NvU32)swLastCompletedPayload) + { + swLastCompletedPayload += 0x100000000ULL; + } + + // Update lower 32 bits regardless if wrap-around happened + swLastCompletedPayload &= 0xFFFFFFFF00000000ULL; + swLastCompletedPayload |= (NvU64)hwCurrentCompletedPayload; + + pCeUtils->lastCompletedPayload = swLastCompletedPayload; + return swLastCompletedPayload; +} + +#if defined(DEBUG) || defined (DEVELOP) +NV_STATUS +ceutilsapiCtrlCmdCheckProgress_IMPL +( + CeUtilsApi *pCeUtilsApi, + NV0050_CTRL_CHECK_PROGRESS_PARAMS *pParams +) +{ + if (pParams->submittedWorkId <= ceutilsUpdateProgress(pCeUtilsApi->pCeUtils)) + { + pParams->result = NV0050_CTRL_CHECK_PROGRESS_RESULT_FINISHED; + } + + return NV_OK; +} + +NV_STATUS +ceutilsapiConstruct_IMPL +( + CeUtilsApi *pCeUtilsApi, + CALL_CONTEXT *pCallContext, + RS_RES_ALLOC_PARAMS_INTERNAL *pParams +) +{ + NV0050_ALLOCATION_PARAMETERS *pAllocParams = pParams->pAllocParams; + + if (FLD_TEST_DRF(0050_CEUTILS, _FLAGS, _EXTERNAL, _TRUE, pAllocParams->flags)) + { + NV_PRINTF(LEVEL_ERROR, "CeUtils: unsupported flags = 0x%llx\n", pAllocParams->flags); + return NV_ERR_NOT_SUPPORTED; + } + + return objCreate(&pCeUtilsApi->pCeUtils, pCeUtilsApi, CeUtils, GPU_RES_GET_GPU(pCeUtilsApi), NULL, pAllocParams); +} + +void +ceutilsapiDestruct_IMPL +( + CeUtilsApi *pCeUtilsApi +) +{ + objDelete(pCeUtilsApi->pCeUtils); +} + +NV_STATUS +ceutilsapiCtrlCmdMemset_IMPL +( + CeUtilsApi *pCeUtilsApi, + NV0050_CTRL_MEMSET_PARAMS *pParams +) +{ + NV_STATUS status = NV_OK; + NvHandle hClient = RES_GET_CLIENT_HANDLE(pCeUtilsApi); + RsResourceRef *pPhysmemRef; + MEMORY_DESCRIPTOR *pMemDesc = NULL; + CEUTILS_MEMSET_PARAMS internalParams = {0}; + + if (pParams->hMemory == 0) + { + return NV_ERR_INVALID_ARGUMENT; + } + + status = serverutilGetResourceRef(hClient, pParams->hMemory, &pPhysmemRef); + if (status != NV_OK) + { + NV_PRINTF(LEVEL_ERROR, "Failed to get resource in resource server for physical memory handle.\n"); + return status; + } + pMemDesc = (dynamicCast(pPhysmemRef->pResource, Memory))->pMemDesc; + + internalParams.pMemDesc = pMemDesc; + internalParams.offset = pParams->offset; + internalParams.length = pParams->length; + internalParams.pattern = pParams->pattern; + internalParams.flags = pParams->flags; + + status = ceutilsMemset(pCeUtilsApi->pCeUtils, &internalParams); + if (status == NV_OK) + { + pParams->submittedWorkId = internalParams.submittedWorkId; + } + + return status; +} + +NV_STATUS +ceutilsapiCtrlCmdMemcopy_IMPL +( + CeUtilsApi *pCeUtilsApi, + NV0050_CTRL_MEMCOPY_PARAMS *pParams +) +{ + NV_STATUS status = NV_OK; + NvHandle hClient = RES_GET_CLIENT_HANDLE(pCeUtilsApi); + RsResourceRef *pSrcPhysmemRef; + RsResourceRef *pDstPhysmemRef; + MEMORY_DESCRIPTOR *pSrcMemDesc = NULL; + MEMORY_DESCRIPTOR *pDstMemDesc = NULL; + CEUTILS_MEMCOPY_PARAMS internalParams = {0}; + + if ((pParams->hSrcMemory == 0) || (pParams->hDstMemory == 0)) + { + return NV_ERR_INVALID_ARGUMENT; + } + + status = serverutilGetResourceRef(hClient, pParams->hDstMemory, &pDstPhysmemRef); + if (status != NV_OK) + { + NV_PRINTF(LEVEL_ERROR, "Failed to get resource in resource server for physical memory handle.\n"); + return status; + } + pDstMemDesc = (dynamicCast(pDstPhysmemRef->pResource, Memory))->pMemDesc; + + status = serverutilGetResourceRef(hClient, pParams->hSrcMemory, &pSrcPhysmemRef); + if (status != NV_OK) + { + NV_PRINTF(LEVEL_ERROR, "Failed to get resource in resource server for physical memory handle.\n"); + return status; + } + pSrcMemDesc = (dynamicCast(pSrcPhysmemRef->pResource, Memory))->pMemDesc; + + internalParams.pSrcMemDesc = pSrcMemDesc; + internalParams.pDstMemDesc = pDstMemDesc; + internalParams.srcOffset = pParams->srcOffset; + internalParams.dstOffset = pParams->dstOffset; + internalParams.length = pParams->length; + internalParams.flags = pParams->flags; + + status = ceutilsMemcopy(pCeUtilsApi->pCeUtils, &internalParams); + if (status == NV_OK) + { + pParams->submittedWorkId = internalParams.submittedWorkId; + } + + return status; +} +#endif // defined(DEBUG) || defined (DEVELOP) diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/kernel/gpu/mem_mgr/channel_utils.c nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/kernel/gpu/mem_mgr/channel_utils.c --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/kernel/gpu/mem_mgr/channel_utils.c 1970-01-01 00:00:00.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/kernel/gpu/mem_mgr/channel_utils.c 2024-03-05 22:13:35.000000000 +0000 @@ -0,0 +1,989 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#include "kernel/gpu/intr/intr.h" +#include "kernel/gpu/fifo/kernel_fifo.h" +#include "kernel/gpu/mig_mgr/kernel_mig_manager.h" +#include "utils/nvassert.h" +#include "core/locks.h" +#include "gpu/mem_mgr/mem_mgr.h" + +#include "kernel/gpu/mem_mgr/ce_utils_sizes.h" +#include "kernel/gpu/mem_mgr/channel_utils.h" +#include "class/clcba2.h" + + +#define SEC2_WL_METHOD_ARRAY_SIZE 16 +#define SHA_256_HASH_SIZE_BYTE 32 + +/* Static helper functions */ +static void channelPushAddress(OBJCHANNEL *pChannel, CHANNEL_PB_INFO *pChannelPbInfo, NvU32 **ppPtr); +static NvU32 channelPushMemoryProperties(OBJCHANNEL *pChannel, CHANNEL_PB_INFO *pChannelPbInfo, NvU32 **ppPtr); +static void channelPushMethod(OBJCHANNEL *pChannel, CHANNEL_PB_INFO *pChannelPbInfo, + NvBool bPipelined, NvBool bInsertFinishPayload, + NvU32 launchType, NvU32 semaValue, NvU32 **ppPtr); + +/* Public APIs */ +NV_STATUS +channelSetupIDs +( + OBJCHANNEL *pChannel, + OBJGPU *pGpu, + NvBool bUseVasForCeCopy, + NvBool bMIGInUse +) +{ + NV_CHECK_OK_OR_RETURN(LEVEL_ERROR, + serverutilGenResourceHandle(pChannel->hClient, &pChannel->physMemId)); + + NV_CHECK_OK_OR_RETURN(LEVEL_ERROR, + serverutilGenResourceHandle(pChannel->hClient, &pChannel->channelId)); + + NV_CHECK_OK_OR_RETURN(LEVEL_ERROR, + serverutilGenResourceHandle(pChannel->hClient, &pChannel->errNotifierIdVirt)); + + NV_CHECK_OK_OR_RETURN(LEVEL_ERROR, + serverutilGenResourceHandle(pChannel->hClient, &pChannel->errNotifierIdPhys)); + + NV_CHECK_OK_OR_RETURN(LEVEL_ERROR, + serverutilGenResourceHandle(pChannel->hClient, &pChannel->engineObjectId)); + + NV_CHECK_OK_OR_RETURN(LEVEL_ERROR, + serverutilGenResourceHandle(pChannel->hClient, &pChannel->eventId)); + + NV_CHECK_OK_OR_RETURN(LEVEL_ERROR, + serverutilGenResourceHandle(pChannel->hClient, &pChannel->pushBufferId)); + + NV_CHECK_OK_OR_RETURN(LEVEL_ERROR, + serverutilGenResourceHandle(pChannel->hClient, &pChannel->doorbellRegionHandle)); + + NV_CHECK_OK_OR_RETURN(LEVEL_ERROR, + serverutilGenResourceHandle(pChannel->hClient, &pChannel->hUserD)); + + // For physical CE channels, we will use RM internal VAS to map channel buffers + NV_ASSERT(pChannel->hVASpaceId == NV01_NULL_OBJECT); + + if (bUseVasForCeCopy || (IS_GSP_CLIENT(pGpu) && bMIGInUse)) + { + NV_CHECK_OK_OR_RETURN(LEVEL_ERROR, + serverutilGenResourceHandle(pChannel->hClient, &pChannel->hVASpaceId)); + } + + return NV_OK; +} + +void +channelSetupChannelBufferSizes +( + OBJCHANNEL *pChannel +) +{ + NV_ASSERT_OR_RETURN_VOID(pChannel != NULL); + NV_ASSERT_OR_RETURN_VOID(pChannel->type < MAX_CHANNEL_TYPE); + + if (pChannel->type == SWL_SCRUBBER_CHANNEL) + { + pChannel->methodSizePerBlock = SEC2_METHOD_SIZE_PER_BLOCK; + } + else + { + pChannel->methodSizePerBlock = CE_METHOD_SIZE_PER_BLOCK; + if (pChannel->type == FAST_SCRUBBER_CHANNEL) + { + pChannel->methodSizePerBlock = FAST_SCRUBBER_METHOD_SIZE_PER_BLOCK; + } + } + pChannel->channelNotifierSize = CHANNEL_NOTIFIER_SIZE; + pChannel->channelNumGpFifioEntries = NUM_COPY_BLOCKS; + + // These sizes depend on size of each block of pushbuffer methods + pChannel->channelPbSize = pChannel->methodSizePerBlock * NUM_COPY_BLOCKS; + pChannel->channelSize = pChannel->channelPbSize + GPFIFO_SIZE + + CHANNEL_HOST_SEMAPHORE_SIZE + CHANNEL_ENGINE_SEMAPHORE_SIZE; + if (pChannel->type == SWL_SCRUBBER_CHANNEL) + { + pChannel->channelSize = pChannel->channelSize + SEC2_AUTH_TAG_BUF_SEMAPHORE_SIZE; + } + pChannel->semaOffset = pChannel->channelPbSize + GPFIFO_SIZE; + pChannel->finishPayloadOffset = pChannel->semaOffset + CHANNEL_HOST_SEMAPHORE_SIZE; + pChannel->authTagBufSemaOffset = pChannel->finishPayloadOffset + CHANNEL_ENGINE_SEMAPHORE_SIZE; +} + +NvU32 +channelReadChannelMemdesc +( + OBJCHANNEL *pChannel, + NvU32 offset +) +{ + NV_ASSERT_OR_RETURN(pChannel != NULL, 0); + NV_ASSERT_OR_RETURN(pChannel->pGpu != NULL, 0); + + MemoryManager *pMemoryManager = GPU_GET_MEMORY_MANAGER(pChannel->pGpu); + NvBool bReleaseMapping = NV_FALSE; + NvU32 result = 0; + + // + // Use BAR1 if CPU access is allowed, otherwise allocate and init shadow + // buffer for DMA access + // + NvU32 transferFlags = (TRANSFER_FLAGS_USE_BAR1 | + TRANSFER_FLAGS_SHADOW_ALLOC | + TRANSFER_FLAGS_SHADOW_INIT_MEM); + + if (pChannel->pbCpuVA == NULL) + { + pChannel->pbCpuVA = memmgrMemDescBeginTransfer(pMemoryManager, pChannel->pChannelBufferMemdesc, + transferFlags); + bReleaseMapping = NV_TRUE; + } + + NV_ASSERT_OR_RETURN(pChannel->pbCpuVA != NULL, 0); + + result = MEM_RD32((NvU8*)pChannel->pbCpuVA + offset); + + if (bReleaseMapping) + { + memmgrMemDescEndTransfer(pMemoryManager, pChannel->pChannelBufferMemdesc, transferFlags); + pChannel->pbCpuVA = NULL; + } + + return result; +} + +/*! + * Service any interrupts which may block the CE or SEC2 scrubber associated + * with this channel from making forward progress. That includes interrupts + * from the CE/SEC2 engine as well as host/esched that is processing the + * pushbuffer. + */ +void +channelServiceScrubberInterrupts( + OBJCHANNEL *pChannel +) +{ + OBJGPU *pGpu = pChannel->pGpu; + Intr *pIntr = GPU_GET_INTR(pGpu); + KernelFifo *pKernelFifo = GPU_GET_KERNEL_FIFO(pGpu); + const NvU32 ceId = pChannel->ceId; + MC_ENGINE_BITVECTOR engines; + NvU32 mcIndex; + NvU32 engineType; + + if (pChannel->type == SWL_SCRUBBER_CHANNEL) + { + mcIndex = MC_ENGINE_IDX_SEC2; + engineType = RM_ENGINE_TYPE_SEC2; + } + else + { + mcIndex = MC_ENGINE_IDX_CE(pChannel->ceId); + engineType = RM_ENGINE_TYPE_COPY(ceId); + } + + bitVectorClrAll(&engines); + bitVectorSet(&engines, mcIndex); + if (kfifoIsHostEngineExpansionSupported(pKernelFifo)) + { + NvU32 runlistId; + NV_ASSERT_OK(kfifoEngineInfoXlate_HAL(pGpu, pKernelFifo, + ENGINE_INFO_TYPE_RM_ENGINE_TYPE, engineType, + ENGINE_INFO_TYPE_RUNLIST, &runlistId)); + bitVectorSet(&engines, MC_ENGINE_IDX_ESCHEDn(runlistId)); + } + else + { + bitVectorSet(&engines, MC_ENGINE_IDX_FIFO); + } + intrServiceStallList_HAL(pGpu, pIntr, &engines, NV_FALSE); +} + +NV_STATUS +channelWaitForFinishPayload +( + OBJCHANNEL *pChannel, + NvU64 targetPayload +) +{ + NV_ASSERT_OR_RETURN(pChannel != NULL, NV_ERR_INVALID_STATE); + + OBJGPU *pGpu = pChannel->pGpu; + RMTIMEOUT timeout; + NV_STATUS status = NV_OK; + + gpuSetTimeout(pGpu, GPU_TIMEOUT_DEFAULT, &timeout, GPU_TIMEOUT_FLAGS_BYPASS_THREAD_STATE); + while (1) + { + if (READ_CHANNEL_PAYLOAD_SEMA(pChannel) >= targetPayload) + { + break; + } + + status = gpuCheckTimeout(pGpu, &timeout); + if (status == NV_ERR_TIMEOUT) + { + break; + } + + if (rmDeviceGpuLockIsOwner(pGpu->gpuInstance)) + { + channelServiceScrubberInterrupts(pChannel); + } + else + { + osSchedule(); + } + } + + return status; +} + + +/** helper function which waits for a PB & GPFIO entry to be read by HOST. + * After the HOST reads GPFIFO and PB entry, the semaphore will be released. + */ +NV_STATUS +channelWaitForFreeEntry +( + OBJCHANNEL *pChannel, + NvU32 *pPutIndex +) +{ + NV_ASSERT_OR_RETURN(pChannel != NULL, NV_ERR_INVALID_STATE); + + OBJGPU *pGpu = pChannel->pGpu; + RMTIMEOUT timeout; + NV_STATUS status = NV_OK; + + NvU32 putIndex = 0; + NvU32 getIndex = 0; + + putIndex = (pChannel->lastSubmittedEntry + 1) % pChannel->channelNumGpFifioEntries; + + gpuSetTimeout(pGpu, GPU_TIMEOUT_DEFAULT, &timeout, GPU_TIMEOUT_FLAGS_BYPASS_THREAD_STATE); + do + { + getIndex = READ_CHANNEL_PB_SEMA(pChannel); + + NV_PRINTF(LEVEL_INFO, "Get Index: %x, PayloadIndex: %x\n", getIndex, + READ_CHANNEL_PAYLOAD_SEMA(pChannel)); + + if (getIndex != putIndex) + { + break; + } + + status = gpuCheckTimeout(pGpu, &timeout); + if (status == NV_ERR_TIMEOUT) + { + break; + } + + if (rmDeviceGpuLockIsOwner(pGpu->gpuInstance)) + { + channelServiceScrubberInterrupts(pChannel); + } + else + { + osSchedule(); + } + } while(1); + + if (status == NV_OK) + { + NV_ASSERT_OR_RETURN(pPutIndex != NULL, NV_ERR_INVALID_STATE); + *pPutIndex = putIndex; + } + + return status; +} + + +/** helper function to fill GPFIFO entry with a pushbuffer segment. and kick + * off the executiion by HOST. + */ +NV_STATUS +channelFillGpFifo +( + OBJCHANNEL *pChannel, + NvU32 putIndex, + NvU32 methodsLength +) +{ + NvU32 *pGpEntry; + NvU32 GpEntry0; + NvU32 GpEntry1; + NvU64 pbPutOffset; + OBJGPU *pGpu; + KernelBus *pKernelBus; + MemoryManager *pMemoryManager; + NvBool bReleaseMapping = NV_FALSE; + + // + // Use BAR1 if CPU access is allowed, otherwise allocate and init shadow + // buffer for DMA access + // + NvU32 transferFlags = (TRANSFER_FLAGS_USE_BAR1 | + TRANSFER_FLAGS_SHADOW_ALLOC | + TRANSFER_FLAGS_SHADOW_INIT_MEM); + + NV_ASSERT_OR_RETURN(putIndex < pChannel->channelNumGpFifioEntries, NV_ERR_INVALID_STATE); + NV_ASSERT_OR_RETURN(pChannel != NULL, NV_ERR_INVALID_STATE); + + pGpu = pChannel->pGpu; + NV_ASSERT_OR_RETURN(pGpu != NULL, NV_ERR_INVALID_STATE); + + pKernelBus = GPU_GET_KERNEL_BUS(pGpu); + pMemoryManager = GPU_GET_MEMORY_MANAGER(pGpu); + + if (pChannel->pbCpuVA == NULL) + { + pChannel->pbCpuVA = memmgrMemDescBeginTransfer(pMemoryManager, pChannel->pChannelBufferMemdesc, + transferFlags); + bReleaseMapping = NV_TRUE; + } + + NV_ASSERT_OR_RETURN(pChannel->pbCpuVA != NULL, NV_ERR_GENERIC); + + pbPutOffset = (pChannel->pbGpuVA + (putIndex * pChannel->methodSizePerBlock)); + + GpEntry0 = DRF_DEF(906F, _GP_ENTRY0, _NO_CONTEXT_SWITCH, _FALSE) | + DRF_NUM(906F, _GP_ENTRY0, _GET, NvU64_LO32(pbPutOffset) >> 2); + + GpEntry1 = DRF_NUM(906F, _GP_ENTRY1, _GET_HI, NvU64_HI32(pbPutOffset)) | + DRF_NUM(906F, _GP_ENTRY1, _LENGTH, methodsLength >> 2) | + DRF_DEF(906F, _GP_ENTRY1, _LEVEL, _MAIN); + + pGpEntry = (NvU32 *)(((NvU8 *)pChannel->pbCpuVA) + pChannel->channelPbSize + + (pChannel->lastSubmittedEntry * NV906F_GP_ENTRY__SIZE)); + + MEM_WR32(&pGpEntry[0], GpEntry0); + MEM_WR32(&pGpEntry[1], GpEntry1); + + if (bReleaseMapping) + { + memmgrMemDescEndTransfer(pMemoryManager, pChannel->pChannelBufferMemdesc, + transferFlags); + pChannel->pbCpuVA = NULL; + } + + // need to flush WRC buffer + osFlushCpuWriteCombineBuffer(); + + // write GP put + if (pChannel->pControlGPFifo == NULL) + { + pChannel->pControlGPFifo = + (void *)memmgrMemDescBeginTransfer(pMemoryManager, pChannel->pUserdMemdesc, + transferFlags); + NV_ASSERT_OR_RETURN(pChannel->pControlGPFifo != NULL, NV_ERR_INVALID_STATE); + bReleaseMapping = NV_TRUE; + } + + MEM_WR32(&pChannel->pControlGPFifo->GPPut, putIndex); + + if (bReleaseMapping) + { + memmgrMemDescEndTransfer(pMemoryManager, pChannel->pUserdMemdesc, transferFlags); + pChannel->pControlGPFifo = NULL; + } + + osFlushCpuWriteCombineBuffer(); + + // + // On some architectures, if doorbell is mapped via bar0, we need to send + // an extra flush + // + if (kbusFlushPcieForBar0Doorbell_HAL(pGpu, pKernelBus) != NV_OK) + { + NV_PRINTF(LEVEL_ERROR, "Busflush failed in _scrubFillGpFifo\n"); + return NV_ERR_GENERIC; + } + + // + // removing the FIFO Lite Mode handling + // Refer older _ceChannelUpdateGpFifo_GF100 code for implementation + // + + // Update doorbell with work submission token + if (pChannel->bUseDoorbellRegister) + { + if (pChannel->pTokenFromNotifier == NULL) + { + NvU8 *pErrNotifierCpuVA = + (void *)memmgrMemDescBeginTransfer(pMemoryManager, + pChannel->pErrNotifierMemdesc, transferFlags); + + NV_ASSERT_OR_RETURN(pErrNotifierCpuVA != NULL, NV_ERR_INVALID_STATE); + + pChannel->pTokenFromNotifier = + (NvNotification *)(pErrNotifierCpuVA + + (NV_CHANNELGPFIFO_NOTIFICATION_TYPE_WORK_SUBMIT_TOKEN * + sizeof(NvNotification))); + bReleaseMapping = NV_TRUE; + } + + // Use the token from notifier memory for VM migration support. + MEM_WR32(pChannel->pDoorbellRegisterOffset, + MEM_RD32(&(pChannel->pTokenFromNotifier->info32))); + + if (bReleaseMapping) + { + memmgrMemDescEndTransfer(pMemoryManager, pChannel->pErrNotifierMemdesc, transferFlags); + pChannel->pTokenFromNotifier = NULL; + } + } + + return NV_OK; +} + +NvU32 +channelFillPbFastScrub +( + OBJCHANNEL *pChannel, + NvU32 putIndex, + NvBool bPipelined, + NvBool bInsertFinishPayload, + CHANNEL_PB_INFO *pChannelPbInfo +) +{ + NvU32 pipelinedValue = 0; + NvU32 flushValue = 0; + NvU32 *pPtr = (NvU32 *)((NvU8*)pChannel->pbCpuVA + (putIndex * pChannel->methodSizePerBlock)); + NvU32 *pStartPtr = pPtr; + NvU32 semaValue = 0; + NvU32 data = 0; + NvU64 pSemaAddr = 0; + + NV_PRINTF(LEVEL_INFO, "PutIndex: %x, PbOffset: %x\n", putIndex, + putIndex * pChannel->methodSizePerBlock); + // SET OBJECT + NV_PUSH_INC_1U(RM_SUBCHANNEL, NVC86F_SET_OBJECT, pChannel->classEngineID); + + // Set Pattern for Memset + NV_PUSH_INC_1U(RM_SUBCHANNEL, NVC8B5_SET_REMAP_CONST_A, pChannelPbInfo->pattern); + NV_PUSH_INC_1U(RM_SUBCHANNEL, NVC8B5_SET_REMAP_CONST_B, pChannelPbInfo->pattern); + + // Set Component Size to 1 + NV_PUSH_INC_1U(RM_SUBCHANNEL, NVC8B5_SET_REMAP_COMPONENTS, + DRF_DEF(C8B5, _SET_REMAP_COMPONENTS, _DST_X, _CONST_A) | + DRF_DEF(C8B5, _SET_REMAP_COMPONENTS, _DST_X, _CONST_B) | + DRF_DEF(C8B5, _SET_REMAP_COMPONENTS, _COMPONENT_SIZE, _ONE) | + DRF_DEF(C8B5, _SET_REMAP_COMPONENTS, _NUM_DST_COMPONENTS, _ONE)); + + NV_PUSH_INC_1U(RM_SUBCHANNEL, NVC8B5_SET_DST_PHYS_MODE, + DRF_DEF(C8B5, _SET_DST_PHYS_MODE, _TARGET, _LOCAL_FB)); + + semaValue = (bInsertFinishPayload) ? + DRF_DEF(C8B5, _LAUNCH_DMA, _SEMAPHORE_TYPE, _RELEASE_ONE_WORD_SEMAPHORE) : 0; + + if (bPipelined) + pipelinedValue = DRF_DEF(C8B5, _LAUNCH_DMA, _DATA_TRANSFER_TYPE, _PIPELINED); + else + pipelinedValue = DRF_DEF(C8B5, _LAUNCH_DMA, _DATA_TRANSFER_TYPE, _NON_PIPELINED); + + if (bInsertFinishPayload) + flushValue = DRF_DEF(B0B5, _LAUNCH_DMA, _FLUSH_ENABLE, _TRUE); + else + flushValue = DRF_DEF(B0B5, _LAUNCH_DMA, _FLUSH_ENABLE, _FALSE); + + NV_PUSH_INC_2U(RM_SUBCHANNEL, NVC8B5_OFFSET_OUT_UPPER, + DRF_NUM(C8B5, _OFFSET_OUT_UPPER, _UPPER, NvU64_HI32(pChannelPbInfo->dstAddr)), + NVC8B5_OFFSET_OUT_LOWER, + DRF_NUM(C8B5, _OFFSET_OUT_LOWER, _VALUE,NvU64_LO32(pChannelPbInfo->dstAddr))); + + NV_PUSH_INC_1U(RM_SUBCHANNEL, NVC8B5_LINE_LENGTH_IN, pChannelPbInfo->size); + + if (semaValue) + { + NV_PUSH_INC_3U(RM_SUBCHANNEL, NVC8B5_SET_SEMAPHORE_A, + DRF_NUM(C8B5, _SET_SEMAPHORE_A, _UPPER, NvU64_HI32(pChannel->pbGpuVA + pChannel->finishPayloadOffset)), + NVC8B5_SET_SEMAPHORE_B, + DRF_NUM(C8B5, _SET_SEMAPHORE_B, _LOWER, NvU64_LO32(pChannel->pbGpuVA + pChannel->finishPayloadOffset)), + NVC8B5_SET_SEMAPHORE_PAYLOAD, + pChannelPbInfo->payload); + } + + NV_PUSH_INC_1U(RM_SUBCHANNEL, NVC8B5_SET_MEMORY_SCRUB_PARAMETERS, + DRF_DEF(C8B5, _SET_MEMORY_SCRUB_PARAMETERS, _DISCARDABLE, _FALSE)); + + NV_PUSH_INC_1U(RM_SUBCHANNEL, NVC8B5_LAUNCH_DMA, + DRF_DEF(C8B5, _LAUNCH_DMA, _SRC_MEMORY_LAYOUT, _PITCH) | + DRF_DEF(C8B5, _LAUNCH_DMA, _DST_MEMORY_LAYOUT, _PITCH) | + DRF_DEF(C8B5, _LAUNCH_DMA, _REMAP_ENABLE, _FALSE) | + DRF_DEF(C8B5, _LAUNCH_DMA, _MULTI_LINE_ENABLE, _FALSE) | + DRF_DEF(C8B5, _LAUNCH_DMA, _MEMORY_SCRUB_ENABLE, _TRUE) | + DRF_DEF(C8B5, _LAUNCH_DMA, _DISABLE_PLC, _TRUE) | + DRF_DEF(C8B5, _LAUNCH_DMA, _DST_TYPE, _PHYSICAL) | + DRF_DEF(C8B5, _LAUNCH_DMA, _SRC_TYPE, _PHYSICAL) | + pipelinedValue | + flushValue | + semaValue); + + // + // This should always be at the bottom the push buffer segment, since this + // denotes that HOST has read all the methods needed for this memory operation + // and safely assume that this GPFIFO and PB entry can be reused. + // + data = DRF_DEF(C86F, _SEM_EXECUTE, _OPERATION, _RELEASE) | + DRF_DEF(C86F, _SEM_EXECUTE, _PAYLOAD_SIZE, _32BIT) | + DRF_DEF(C86F, _SEM_EXECUTE, _RELEASE_WFI, _DIS); + + pSemaAddr = (pChannel->pbGpuVA+pChannel->semaOffset); + + NV_PUSH_INC_4U(RM_SUBCHANNEL, NVC86F_SEM_ADDR_LO, + DRF_NUM(C86F, _SEM_ADDR_LO, _OFFSET, NvU64_LO32(pSemaAddr) >> 2), + NVC86F_SEM_ADDR_HI, + DRF_NUM(C86F, _SEM_ADDR_HI, _OFFSET, NvU64_HI32(pSemaAddr)), + NVC86F_SEM_PAYLOAD_LO, putIndex, + NVC86F_SEM_PAYLOAD_HI, 0); + + NV_PUSH_INC_1U(RM_SUBCHANNEL, NVC86F_SEM_EXECUTE, data); + + NvU32 methodSize = (NvU32)((NvU8*)pPtr - (NvU8*)pStartPtr); + NV_ASSERT_OR_RETURN(methodSize <= pChannel->methodSizePerBlock, 0); + return methodSize; +} + +static void +channelAddHostSema +( + OBJCHANNEL *pChannel, + NvU32 putIndex, + NvU32 **ppPtr +) +{ + NvU32 *pPtr = *ppPtr; + NvU32 data = 0; + NvU64 pSemaAddr = 0; + + // Release HOST semaphore after after gpfifo/pb segments are processed by esched + data = DRF_DEF(906F, _SEMAPHORED, _OPERATION, _RELEASE) | + DRF_DEF(906F, _SEMAPHORED, _RELEASE_SIZE, _4BYTE) | + DRF_DEF(906F, _SEMAPHORED, _RELEASE_WFI, _DIS); + + pSemaAddr = (pChannel->pbGpuVA + pChannel->semaOffset); + + // + // This should always be at the bottom the push buffer segment, since this + // denotes that HOST has read all the methods needed for this memory operation + // and safely assume that this GPFIFO and PB entry can be reused. + // + NV_PUSH_INC_4U(RM_SUBCHANNEL, NV906F_SEMAPHOREA, + DRF_NUM(906F, _SEMAPHOREA_OFFSET, _UPPER, NvU64_HI32(pSemaAddr)), + NV906F_SEMAPHOREB, + DRF_NUM(906F, _SEMAPHOREB_OFFSET, _LOWER, NvU64_LO32(pSemaAddr) >> 2), + NV906F_SEMAPHOREC, + putIndex, + NV906F_SEMAPHORED, + data); + *ppPtr = pPtr; +} + +/** single helper function to fill the push buffer with the methods needed for + * memsetting using CE. This function is much more efficient in the sense it + * decouples the mem(set/copy) operation from managing channel resources. + **/ + +NvU32 +channelFillCePb +( + OBJCHANNEL *pChannel, + NvU32 putIndex, + NvBool bPipelined, + NvBool bInsertFinishPayload, + CHANNEL_PB_INFO *pChannelPbInfo +) +{ + NvU32 launchType = 0; + NvU32 *pPtr = (NvU32 *)((NvU8 *)pChannel->pbCpuVA + (putIndex * pChannel->methodSizePerBlock)); + NvU32 *pStartPtr = pPtr; + NvU32 semaValue = 0; + + NV_PRINTF(LEVEL_INFO, "PutIndex: %x, PbOffset: %x\n", putIndex, putIndex * pChannel->methodSizePerBlock); + + NV_PUSH_INC_1U(RM_SUBCHANNEL, NV906F_SET_OBJECT, pChannel->classEngineID); + + // Side effect - pushed target aperture and REMAP method for memset + launchType = channelPushMemoryProperties(pChannel, pChannelPbInfo, &pPtr); + + // Side effect - pushed addresses + channelPushAddress(pChannel, pChannelPbInfo, &pPtr); + NV_PUSH_INC_1U(RM_SUBCHANNEL, NVB0B5_LINE_LENGTH_IN, pChannelPbInfo->size); + + if (bInsertFinishPayload) + { + semaValue = DRF_DEF(B0B5, _LAUNCH_DMA, _SEMAPHORE_TYPE, _RELEASE_ONE_WORD_SEMAPHORE); + + // Do not support client semaphore for now + NV_ASSERT(pChannelPbInfo->clientSemaAddr == 0); + + NV_PUSH_INC_3U(RM_SUBCHANNEL, NVB0B5_SET_SEMAPHORE_A, + DRF_NUM(B0B5, _SET_SEMAPHORE_A, _UPPER, NvU64_HI32(pChannel->pbGpuVA + pChannel->finishPayloadOffset)), + NVB0B5_SET_SEMAPHORE_B, + DRF_NUM(B0B5, _SET_SEMAPHORE_B, _LOWER, NvU64_LO32(pChannel->pbGpuVA + pChannel->finishPayloadOffset)), + NVB0B5_SET_SEMAPHORE_PAYLOAD, + pChannelPbInfo->payload); + } + + // Side effect - pushed LAUNCH_DMA methods + channelPushMethod(pChannel, pChannelPbInfo, bPipelined, bInsertFinishPayload, launchType, semaValue, &pPtr); + + channelAddHostSema(pChannel, putIndex, &pPtr); + + NvU32 methodSize = (NvU32)((NvU8*)pPtr - (NvU8*)pStartPtr); + NV_ASSERT_OR_RETURN(methodSize <= pChannel->methodSizePerBlock, 0); + return methodSize; +} + +static NV_STATUS +addMethodsToMethodBuf +( + NvU32 command, + NvU32 data, + NvU32 *pMethodBuf, + NvU32 index +) +{ + + NV_ASSERT_OR_RETURN((index < SEC2_WL_METHOD_ARRAY_SIZE), NV_ERR_INVALID_ARGUMENT); + pMethodBuf[index*2 + 0] = command; + pMethodBuf[index*2 + 1] = data; + return NV_OK; +} + +/** single helper function to fill the push buffer with the methods needed for + * memsetting using SEC2. This function is much more efficient in the sense it + * decouples the mem(set/copy) operation from managing channel resources. + **/ +NV_STATUS +channelFillSec2Pb +( + OBJCHANNEL *pChannel, + NvU32 putIndex, + NvBool bInsertFinishPayload, + CHANNEL_PB_INFO *pChannelPbInfo, + CCSL_CONTEXT *pCcslCtx, + MEMORY_DESCRIPTOR *pAuthTagBufMemDesc, + MEMORY_DESCRIPTOR *pSemaMemDesc, + NvU64 scrubMthdAuthTagBufGpuVA, + NvU32 scrubAuthTagBufIndex, + NvU64 semaMthdAuthTagBufGpuVA, + NvU32 semaAuthTagBufIndex, + NvU32 *pMethodLength +) +{ + NvU32 *pPtr = NULL; + NvU32 *pStartPtr = NULL; + NvU32 execute = 0; + NvU32 methodIdx = 0; + NvU32 *pMethods = NULL; + NV_STATUS status = NV_OK; + MemoryManager *pMemoryManager = NULL; + NvU32 scrubAuthTagBufoffset = scrubAuthTagBufIndex * SHA_256_HASH_SIZE_BYTE; + NvU32 semaAuthTagBufoffset = semaAuthTagBufIndex * SHA_256_HASH_SIZE_BYTE; + + NV_ASSERT_OR_RETURN((pChannel != NULL), NV_ERR_INVALID_ARGUMENT); + NV_ASSERT_OR_RETURN((pChannelPbInfo != NULL), NV_ERR_INVALID_ARGUMENT); + NV_ASSERT_OR_RETURN((pCcslCtx != NULL), NV_ERR_INVALID_ARGUMENT); + NV_ASSERT_OR_RETURN((pAuthTagBufMemDesc != NULL), NV_ERR_INVALID_ARGUMENT); + NV_ASSERT_OR_RETURN((pSemaMemDesc != NULL), NV_ERR_INVALID_ARGUMENT); + NV_ASSERT_OR_RETURN((pMethodLength != NULL), NV_ERR_INVALID_ARGUMENT); + + pPtr = (NvU32 *)((NvU8 *)pChannel->pbCpuVA + (putIndex * pChannel->methodSizePerBlock)); + pStartPtr = pPtr; + pMemoryManager = GPU_GET_MEMORY_MANAGER(pChannel->pGpu); + + NV_PRINTF(LEVEL_INFO, "PutIndex: %x, PbOffset: %x\n", putIndex, putIndex * pChannel->methodSizePerBlock); + NvU32 transferFlags = (TRANSFER_FLAGS_USE_BAR1 | + TRANSFER_FLAGS_SHADOW_ALLOC | + TRANSFER_FLAGS_SHADOW_INIT_MEM); + NvU8* pScrubMethdAuthTagBuf = (NvU8 *)memmgrMemDescBeginTransfer(pMemoryManager, pAuthTagBufMemDesc, transferFlags); + NV_ASSERT_OR_RETURN((pScrubMethdAuthTagBuf != NULL), NV_ERR_INVALID_STATE); + + NvU8* pSemaAuthTagBuf = (NvU8 *)memmgrMemDescBeginTransfer(pMemoryManager, pSemaMemDesc, transferFlags); + NV_ASSERT_OR_RETURN((pSemaAuthTagBuf != NULL), NV_ERR_INVALID_STATE); + + pMethods = (NvU32*)portMemAllocNonPaged(sizeof(NvU32) * SEC2_WL_METHOD_ARRAY_SIZE * 2); + NV_ASSERT_OR_RETURN(pMethods != NULL, NV_ERR_NO_MEMORY); + portMemSet(pMethods, 0, (sizeof(NvU32) * SEC2_WL_METHOD_ARRAY_SIZE * 2)); + + NV_ASSERT_OK_OR_GOTO(status, addMethodsToMethodBuf(NV906F_SET_OBJECT, pChannel->classEngineID, pMethods, methodIdx++), cleanup); + NV_ASSERT_OK_OR_GOTO(status, addMethodsToMethodBuf(NVCBA2_DECRYPT_COPY_DST_ADDR_HI, NvU64_HI32(pChannelPbInfo->dstAddr), pMethods, methodIdx++), cleanup); + NV_ASSERT_OK_OR_GOTO(status, addMethodsToMethodBuf(NVCBA2_DECRYPT_COPY_DST_ADDR_LO, NvU64_LO32(pChannelPbInfo->dstAddr), pMethods, methodIdx++), cleanup); + NV_ASSERT_OK_OR_GOTO(status, addMethodsToMethodBuf(NVCBA2_DECRYPT_COPY_SIZE, pChannelPbInfo->size, pMethods, methodIdx++), cleanup); + NV_ASSERT_OK_OR_GOTO(status, addMethodsToMethodBuf(NVCBA2_METHOD_STREAM_AUTH_TAG_ADDR_HI, NvU64_HI32(scrubMthdAuthTagBufGpuVA + scrubAuthTagBufoffset), pMethods, methodIdx++), cleanup); + NV_ASSERT_OK_OR_GOTO(status, addMethodsToMethodBuf(NVCBA2_METHOD_STREAM_AUTH_TAG_ADDR_LO, NvU64_LO32(scrubMthdAuthTagBufGpuVA + scrubAuthTagBufoffset), pMethods, methodIdx++), cleanup); + + // Use this semaphore release to track the current method stream auth tag buffer being used + execute |= FLD_SET_DRF(CBA2, _EXECUTE, _NOTIFY, _ENABLE, execute); + execute |= FLD_SET_DRF(CBA2, _EXECUTE, _NOTIFY_ON, _END, execute); + NV_ASSERT_OK_OR_GOTO(status, addMethodsToMethodBuf(NVCBA2_SEMAPHORE_A, NvU64_HI32(pChannel->pbGpuVA + pChannel->authTagBufSemaOffset), pMethods, methodIdx++), cleanup); + NV_ASSERT_OK_OR_GOTO(status, addMethodsToMethodBuf(NVCBA2_SEMAPHORE_B, NvU64_LO32(pChannel->pbGpuVA + pChannel->authTagBufSemaOffset), pMethods, methodIdx++), cleanup); + NV_ASSERT_OK_OR_GOTO(status, addMethodsToMethodBuf(NVCBA2_SET_SEMAPHORE_PAYLOAD_LOWER, scrubAuthTagBufIndex, pMethods, methodIdx++), cleanup); + + execute |= FLD_SET_DRF(CBA2, _EXECUTE, _PHYSICAL_SCRUBBER, _ENABLE, execute); + NV_ASSERT_OK_OR_GOTO(status, addMethodsToMethodBuf(NVCBA2_EXECUTE, execute, pMethods, methodIdx++), cleanup); + + NvU32 hmacBufferSizeBytes = 2 * methodIdx * sizeof(NvU32); + NvU8 hmacDigest[SHA_256_HASH_SIZE_BYTE] = {0}; + NvU8* pBufScrub = &pScrubMethdAuthTagBuf[scrubAuthTagBufoffset]; + + ccslSign(pCcslCtx, hmacBufferSizeBytes, (NvU8 *)pMethods, hmacDigest); + + portMemCopy((void*)pBufScrub, SHA_256_HASH_SIZE_BYTE, (const void*)&hmacDigest[0], SHA_256_HASH_SIZE_BYTE); + + for (NvU32 i = 0; i < methodIdx; i++) + { + NV_PUSH_INC_1U(RM_SUBCHANNEL, pMethods[i*2 + 0], pMethods[i*2 + 1]); + } + + // insert standalone semaphore to track sub operation completion + if (bInsertFinishPayload) + { + NvU32 semaD = 0; + methodIdx = 0; + portMemSet(pMethods, 0, (sizeof(NvU32) * SEC2_WL_METHOD_ARRAY_SIZE * 2)); + semaD |= FLD_SET_DRF(CBA2, _SEMAPHORE_D, _FLUSH_DISABLE, _FALSE, execute); + NV_ASSERT_OK_OR_GOTO(status, addMethodsToMethodBuf(NVCBA2_METHOD_STREAM_AUTH_TAG_ADDR_HI, NvU64_HI32(semaMthdAuthTagBufGpuVA + semaAuthTagBufoffset), pMethods, methodIdx++), cleanup); + NV_ASSERT_OK_OR_GOTO(status, addMethodsToMethodBuf(NVCBA2_METHOD_STREAM_AUTH_TAG_ADDR_LO, NvU64_LO32(semaMthdAuthTagBufGpuVA + semaAuthTagBufoffset), pMethods, methodIdx++), cleanup); + NV_ASSERT_OK_OR_GOTO(status, addMethodsToMethodBuf(NVCBA2_SEMAPHORE_A, NvU64_HI32(pChannel->pbGpuVA + pChannel->finishPayloadOffset), pMethods, methodIdx++), cleanup); + NV_ASSERT_OK_OR_GOTO(status, addMethodsToMethodBuf(NVCBA2_SEMAPHORE_B, NvU64_LO32(pChannel->pbGpuVA + pChannel->finishPayloadOffset), pMethods, methodIdx++), cleanup); + NV_ASSERT_OK_OR_GOTO(status, addMethodsToMethodBuf(NVCBA2_SET_SEMAPHORE_PAYLOAD_LOWER, pChannelPbInfo->payload, pMethods, methodIdx++), cleanup); + NV_ASSERT_OK_OR_GOTO(status, addMethodsToMethodBuf(NVCBA2_SEMAPHORE_D, semaD, pMethods, methodIdx++), cleanup); + + hmacBufferSizeBytes = 2 * methodIdx * sizeof(NvU32); + portMemSet(&hmacDigest[0], 0, SHA_256_HASH_SIZE_BYTE); + NvU8* pBufSema = &pSemaAuthTagBuf[semaAuthTagBufoffset]; + + ccslSign(pCcslCtx, hmacBufferSizeBytes, (NvU8 *)pMethods, hmacDigest); + + portMemCopy((void*)pBufSema, SHA_256_HASH_SIZE_BYTE, (const void*)&hmacDigest[0], SHA_256_HASH_SIZE_BYTE); + + for (NvU32 i = 0; i < methodIdx; i++) + { + NV_PUSH_INC_1U(RM_SUBCHANNEL, pMethods[i*2 + 0], pMethods[i*2 + 1]); + } + } + + channelAddHostSema(pChannel, putIndex, &pPtr); + + *pMethodLength = 0; + NvU32 methodSize = (NvU32)((NvU8*)pPtr - (NvU8*)pStartPtr); + NV_ASSERT_OR_RETURN(methodSize <= pChannel->methodSizePerBlock, NV_ERR_INVALID_STATE); + *pMethodLength = methodSize; + +cleanup: + if (pSemaAuthTagBuf != NULL) + { + memmgrMemDescEndTransfer(pMemoryManager, pSemaMemDesc, transferFlags); + } + if (pScrubMethdAuthTagBuf != NULL) + { + memmgrMemDescEndTransfer(pMemoryManager, pAuthTagBufMemDesc, transferFlags); + } + portMemFree(pMethods); + return status; +} + +/*** Implementation for static methods ***/ +static NvU32 +channelPushMemoryProperties +( + OBJCHANNEL *pChannel, + CHANNEL_PB_INFO *pChannelPbInfo, + NvU32 **ppPtr +) +{ + NV_ADDRESS_SPACE dstAddressSpace = pChannelPbInfo->dstAddressSpace; + NV_ADDRESS_SPACE srcAddressSpace = pChannelPbInfo->srcAddressSpace; + NvU32 dstCpuCacheAttrib = pChannelPbInfo->dstCpuCacheAttrib; + NvU32 srcCpuCacheAttrib = pChannelPbInfo->srcCpuCacheAttrib; + + NvU32 data = 0; + NvU32 retVal = 0; + NvU32 *pPtr = *ppPtr; + + if (!pChannelPbInfo->bCeMemcopy) + { + // If memset, push remap components + NV_PUSH_INC_1U(RM_SUBCHANNEL, NVB0B5_SET_REMAP_CONST_A, pChannelPbInfo->pattern); + NV_PUSH_INC_1U(RM_SUBCHANNEL, NVB0B5_SET_REMAP_COMPONENTS, + DRF_DEF(B0B5, _SET_REMAP_COMPONENTS, _DST_X, _CONST_A) | + DRF_DEF(B0B5, _SET_REMAP_COMPONENTS, _COMPONENT_SIZE, _ONE) | + DRF_DEF(B0B5, _SET_REMAP_COMPONENTS, _NUM_DST_COMPONENTS, _ONE)); + } + else + { + // If memcopy, push src addr properties + if (srcAddressSpace == ADDR_FBMEM) + { + data = DRF_DEF(B0B5, _SET_SRC_PHYS_MODE, _TARGET, _LOCAL_FB); + } + else if (srcCpuCacheAttrib == NV_MEMORY_CACHED) + { + data = DRF_DEF(B0B5, _SET_SRC_PHYS_MODE, _TARGET, _COHERENT_SYSMEM); + } + else + { + data = DRF_DEF(B0B5, _SET_SRC_PHYS_MODE, _TARGET, _NONCOHERENT_SYSMEM); + } + + NV_PUSH_INC_1U(RM_SUBCHANNEL, NVB0B5_SET_SRC_PHYS_MODE, data); + } + + // Push dst addr properties + if (dstAddressSpace == ADDR_FBMEM) + { + data = DRF_DEF(B0B5, _SET_DST_PHYS_MODE, _TARGET, _LOCAL_FB); + } + else if (dstCpuCacheAttrib == NV_MEMORY_CACHED) + { + data = DRF_DEF(B0B5, _SET_DST_PHYS_MODE, _TARGET, _COHERENT_SYSMEM); + } + else + { + data = DRF_DEF(B0B5, _SET_DST_PHYS_MODE, _TARGET, _NONCOHERENT_SYSMEM); + } + + NV_PUSH_INC_1U(RM_SUBCHANNEL, NVB0B5_SET_DST_PHYS_MODE, data); + + if (pChannel->bUseVasForCeCopy) + { + retVal = DRF_DEF(B0B5, _LAUNCH_DMA, _DST_TYPE, _VIRTUAL) | + DRF_DEF(B0B5, _LAUNCH_DMA, _SRC_TYPE, _VIRTUAL); + } + else + { + retVal = DRF_DEF(B0B5, _LAUNCH_DMA, _DST_TYPE, _PHYSICAL) | + DRF_DEF(B0B5, _LAUNCH_DMA, _SRC_TYPE, _PHYSICAL); + } + + *ppPtr = pPtr; + return retVal; +} + + +static void +channelPushAddress +( + OBJCHANNEL *pChannel, + CHANNEL_PB_INFO *pChannelPbInfo, + NvU32 **ppPtr +) +{ + NvU64 dstAddr = pChannelPbInfo->dstAddr; + NvU64 srcAddr = pChannelPbInfo->srcAddr; + NvU32 *pPtr = *ppPtr; + + // Linear translation to map the PA to VA + if (pChannel->bUseVasForCeCopy) + { + dstAddr = dstAddr + pChannel->fbAliasVA - pChannel->startFbOffset; + srcAddr = srcAddr + pChannel->fbAliasVA - pChannel->startFbOffset; + } + + // Set dst addr + NV_PUSH_INC_2U(RM_SUBCHANNEL, NVB0B5_OFFSET_OUT_UPPER, + DRF_NUM(B0B5, _OFFSET_OUT_UPPER, _UPPER, NvU64_HI32(dstAddr)), + NVB0B5_OFFSET_OUT_LOWER, + DRF_NUM(B0B5, _OFFSET_OUT_LOWER, _VALUE, NvU64_LO32(dstAddr))); + + // Set src addr if memcopy + if (pChannelPbInfo->bCeMemcopy) + { + NV_PUSH_INC_2U(RM_SUBCHANNEL, NVB0B5_OFFSET_IN_UPPER, + DRF_NUM(B0B5, _OFFSET_IN_UPPER, _UPPER, NvU64_HI32(srcAddr)), + NVB0B5_OFFSET_IN_LOWER, + DRF_NUM(B0B5, _OFFSET_IN_LOWER, _VALUE, NvU64_LO32(srcAddr))); + } + + *ppPtr = pPtr; +} + + +static void +channelPushMethod +( + OBJCHANNEL *pChannel, + CHANNEL_PB_INFO *pChannelPbInfo, + NvBool bPipelined, + NvBool bInsertFinishPayload, + NvU32 launchType, + NvU32 semaValue, + NvU32 **ppPtr +) +{ + NvU32 pipelinedValue = 0; + NvU32 flushValue = 0; + NvU32 disablePlcKind = 0; + NvU32 launchParams = 0; + NvU32 *pPtr = *ppPtr; + + if (bPipelined) + { + pipelinedValue = DRF_DEF(B0B5, _LAUNCH_DMA, _DATA_TRANSFER_TYPE, _PIPELINED); + } + else + { + pipelinedValue = DRF_DEF(B0B5, _LAUNCH_DMA, _DATA_TRANSFER_TYPE, _NON_PIPELINED); + } + + if (bInsertFinishPayload) + { + flushValue = DRF_DEF(B0B5, _LAUNCH_DMA, _FLUSH_ENABLE, _TRUE); + } + else + { + flushValue = DRF_DEF(B0B5, _LAUNCH_DMA, _FLUSH_ENABLE, _FALSE); + } + + if (!pChannelPbInfo->bCeMemcopy) + { + switch (pChannel->hTdCopyClass) + { + case MAXWELL_DMA_COPY_A: + case PASCAL_DMA_COPY_A: + case PASCAL_DMA_COPY_B: + case VOLTA_DMA_COPY_A: + disablePlcKind = 0; + break; + default: // For anything after Turing, set the kind + disablePlcKind = DRF_DEF(C5B5, _LAUNCH_DMA, _DISABLE_PLC, _TRUE); + break; + } + + launchParams = DRF_DEF(B0B5, _LAUNCH_DMA, _REMAP_ENABLE, _TRUE) | disablePlcKind; + } + + NV_PUSH_INC_1U(RM_SUBCHANNEL, NVB0B5_LAUNCH_DMA, + launchParams | + DRF_DEF(B0B5, _LAUNCH_DMA, _SRC_MEMORY_LAYOUT, _PITCH) | + DRF_DEF(B0B5, _LAUNCH_DMA, _DST_MEMORY_LAYOUT, _PITCH) | + DRF_DEF(B0B5, _LAUNCH_DMA, _MULTI_LINE_ENABLE, _FALSE) | + launchType | + pipelinedValue | + flushValue | + semaValue); + *ppPtr = pPtr; +} diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/kernel/gpu/mem_mgr/context_dma.c nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/kernel/gpu/mem_mgr/context_dma.c --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/kernel/gpu/mem_mgr/context_dma.c 2023-10-25 20:21:10.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/kernel/gpu/mem_mgr/context_dma.c 2024-03-05 22:13:35.000000000 +0000 @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 1993-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 1993-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -83,7 +83,16 @@ // if (pCpuMapping) { - osUnmapPciMemoryKernelOld(pGpu, pContextDma->KernelVAddr[gpuSubDevInst]); + KernelBus *pKernelBus = GPU_GET_KERNEL_BUS(pGpu); + + if(pGpu->getProperty(pGpu, PDB_PROP_GPU_COHERENT_CPU_MAPPING)) + { + kbusUnmapCoherentCpuMapping_HAL(pGpu, pKernelBus, pContextDma->pMemDesc); + } + else + { + osUnmapPciMemoryKernelOld(pGpu, pContextDma->KernelVAddr[gpuSubDevInst]); + } refRemoveMapping(pMemoryRef, pCpuMapping); /// @@ -96,7 +105,6 @@ if (!IS_VIRTUAL(pGpu) && !IS_GSP_CLIENT(pGpu) && (pContextDma->FbApertureLen[gpuSubDevInst] != 0)) { - KernelBus *pKernelBus = GPU_GET_KERNEL_BUS(pGpu); kbusUnmapFbAperture_HAL(pGpu, pKernelBus, pContextDma->pMemDesc, pContextDma->FbAperture[gpuSubDevInst], pContextDma->FbApertureLen[gpuSubDevInst], @@ -194,18 +202,18 @@ pContextDma->Type = type; pContextDma->Limit = limit; - for (i = 0; i < NV_ARRAY_ELEMENTS32(pContextDma->KernelVAddr); i++) + for (i = 0; i < NV_ARRAY_ELEMENTS(pContextDma->KernelVAddr); i++) pContextDma->KernelVAddr[i] = NULL; pContextDma->KernelPriv = NULL; - for (i = 0; i < NV_ARRAY_ELEMENTS32(pContextDma->FbAperture); i++) + for (i = 0; i < NV_ARRAY_ELEMENTS(pContextDma->FbAperture); i++) { pContextDma->FbAperture[i] = (NvU64)-1; pContextDma->FbApertureLen[i] = 0; } - for (i = 0; i < NV_ARRAY_ELEMENTS32(pContextDma->Instance); i++) + for (i = 0; i < NV_ARRAY_ELEMENTS(pContextDma->Instance); i++) { pContextDma->Instance[i] = 0; pContextDma->InstRefCount[i] = 0; @@ -577,13 +585,27 @@ pContextDma->FbAperture[gpuSubDevInst] - pGpu->busInfo.gpuPhysFbAddr; } } + else if (pGpu->getProperty(pGpu, PDB_PROP_GPU_COHERENT_CPU_MAPPING)) + { + NvP64 pMap = kbusMapCoherentCpuMapping_HAL(pGpu, pKernelBus, pMemDesc); + if (pMap == NULL) + { + rmStatus = NV_ERR_GENERIC; + } + else + { + rmStatus = NV_OK; + pMap = NvP64_PLUS_OFFSET(pMap, offset); + } + pContextDma->KernelVAddr[gpuSubDevInst] = pMap; + } else { rmStatus = kbusMapFbAperture_HAL(pGpu, pKernelBus, pMemDesc, offset, &pContextDma->FbAperture[gpuSubDevInst], &pContextDma->FbApertureLen[gpuSubDevInst], - BUS_MAP_FB_FLAGS_MAP_UNICAST, hClient); + BUS_MAP_FB_FLAGS_MAP_UNICAST, pDevice); } if (rmStatus != NV_OK) { @@ -644,7 +666,7 @@ // host, if we are in guest OS (where IS_VIRTUAL(pGpu) is true), // do an RPC to the host to do the hardware update. // - NV_RM_RPC_ALLOC_CONTEXT_DMA(pGpu, hClient, hDevice, RES_GET_HANDLE(pContextDma), hClass, + NV_RM_RPC_ALLOC_CONTEXT_DMA(pGpu, hClient, hDevice, RES_GET_HANDLE(pContextDma), hClass, flags, RES_GET_HANDLE(pMemory), offset, limit, rmStatus); } } @@ -751,33 +773,6 @@ return NV_OK; } -// **************************************************************************** -// Deprecated Functions -// **************************************************************************** - -/** - * @warning This function is deprecated! Please use ctxdmaGetByHandle. - */ -NV_STATUS -CliGetContextDma -( - NvHandle hClient, - NvHandle hContextDma, - ContextDma **ppContextDma -) -{ - RsClient *pClient; - NV_STATUS status; - - *ppContextDma = NULL; - - status = serverGetClientUnderLock(&g_resServ, hClient, &pClient); - if (status != NV_OK) - return NV_ERR_INVALID_CLIENT; - - return ctxdmaGetByHandle(pClient, hContextDma, ppContextDma); -} - NV_STATUS ctxdmaMapTo_IMPL ( @@ -791,7 +786,7 @@ // // For video memory, provide a way to look up the offset of an FB allocation within - // the given context target context dma. still useful for dFPGA. + // the given context target context dma. still useful for dFPGA. // It is used by mods. // if ((memdescGetAddressSpace(memdescGetMemDescFromGpu(pSrcMemDesc, pGpu)) == ADDR_FBMEM) && diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/kernel/gpu/mem_mgr/dma.c nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/kernel/gpu/mem_mgr/dma.c --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/kernel/gpu/mem_mgr/dma.c 2023-10-25 20:21:10.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/kernel/gpu/mem_mgr/dma.c 2024-03-05 22:13:35.000000000 +0000 @@ -690,7 +690,7 @@ if (FLD_TEST_DRF(0080, _CTRL_DMA_FLUSH_TARGET_UNIT, _FB, _ENABLE, flushParams->targetUnit)) { - status = kbusFlush_HAL(pGpu, pKernelBus, BUS_FLUSH_VIDEO_MEMORY); + status = kbusSendSysmembar(pGpu, pKernelBus); } return status; diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/kernel/gpu/mem_mgr/heap.c nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/kernel/gpu/mem_mgr/heap.c --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/kernel/gpu/mem_mgr/heap.c 2023-10-25 20:21:11.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/kernel/gpu/mem_mgr/heap.c 2024-03-05 22:13:35.000000000 +0000 @@ -557,12 +557,12 @@ } } - // + // // Define PMA-managed regions // This will be moved to memmgr once we refactor SMC partitions // - if (memmgrIsPmaEnabled(pMemoryManager) && - memmgrIsPmaSupportedOnPlatform(pMemoryManager) && + if (memmgrIsPmaEnabled(pMemoryManager) && + memmgrIsPmaSupportedOnPlatform(pMemoryManager) && (heapType != HEAP_TYPE_PARTITION_LOCAL)) { memmgrSetPmaInitialized(pMemoryManager, NV_TRUE); @@ -657,6 +657,7 @@ MEMORY_DESCRIPTOR *pMemDesc = NULL; NvBool bProtected = NV_FALSE; + bProtected = gpuIsCCFeatureEnabled(pGpu); status = heapReserveRegion( pMemoryManager, pHeap, @@ -2751,7 +2752,7 @@ NvU8 currentBankInfo = 0; FB_ALLOC_INFO *pFbAllocInfo = NULL; FB_ALLOC_PAGE_FORMAT *pFbAllocPageFormat = NULL; - NvU32 pageSize = 0; + NvU64 pageSize = 0; NvU32 flags; NvU32 owner; NvU32 tiledAttr; @@ -2898,7 +2899,7 @@ if (pAllocHint->flags & NVOS32_ALLOC_FLAGS_FORCE_ALIGN_HOST_PAGE) { OBJSYS *pSys = SYS_GET_INSTANCE(); - NvU32 hostPageSize = pSys->cpuInfo.hostPageSize; + NvU64 hostPageSize = pSys->cpuInfo.hostPageSize; // hostPageSize *should* always be set, but.... if (hostPageSize == 0) @@ -2984,7 +2985,7 @@ FB_ALLOC_INFO *pFbAllocInfo = NULL; FB_ALLOC_PAGE_FORMAT *pFbAllocPageFormat = NULL; NvU32 tiledAttr; - NvU32 pageSize = 0; + NvU64 pageSize = 0; NV_MEMORY_HW_RESOURCES_ALLOCATION_PARAMS *pUserParams = pHwAlloc->pUserParams; // Ensure a valid allocation type was passed in @@ -3064,7 +3065,7 @@ // host, if we are in guest OS (where IS_VIRTUAL(pGpu) is true), // do an RPC to the host to do the hardware update. // - if ((status == NV_OK) && (IS_VIRTUAL(pGpu) || IS_GSP_CLIENT(pGpu))) + if ((status == NV_OK) && IS_VIRTUAL(pGpu)) { { NV_RM_RPC_MANAGE_HW_RESOURCE_ALLOC(pGpu, @@ -3212,7 +3213,7 @@ // do an RPC to the host to do the hardware update. // - if (IS_VIRTUAL(pGpu) || IS_GSP_CLIENT(pGpu)) + if (IS_VIRTUAL(pGpu)) { { NV_STATUS rmStatus = NV_OK; @@ -3225,8 +3226,7 @@ rmStatus); } } - - if (!IS_VIRTUAL(pGpu) && !IS_GSP_CLIENT(pGpu)) + else { memmgrFreeHwResources(pGpu, pMemoryManager, pFbAllocInfo); } @@ -3790,7 +3790,7 @@ NvU32 pteIndexOffset = 0, i = 0; NvU32 blockId = 0; NV_STATUS status = NV_OK; - NvU32 pageSize = 0; + NvU64 pageSize = 0; NvS64 numPagesLeft; MEM_BLOCK *pCurrBlock; MEM_BLOCK *pNextBlock; @@ -3838,7 +3838,7 @@ // numPagesLeft = RM_ALIGN_UP(pAllocData->allocSize, pageSize) / pageSize; NV_PRINTF(LEVEL_INFO, - "pageSize: 0x%x, numPagesLeft: 0x%llx, allocSize: 0x%llx\n", + "pageSize: 0x%llx, numPagesLeft: 0x%llx, allocSize: 0x%llx\n", pageSize / 1024, numPagesLeft, pAllocData->allocSize); for (pCurrBlock = pHeap->pNoncontigFreeBlockList; diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/kernel/gpu/mem_mgr/mem_ctrl.c nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/kernel/gpu/mem_mgr/mem_ctrl.c --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/kernel/gpu/mem_mgr/mem_ctrl.c 2023-10-25 20:21:11.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/kernel/gpu/mem_mgr/mem_ctrl.c 2024-03-05 22:13:36.000000000 +0000 @@ -71,12 +71,18 @@ if (pParams->hSubDevice) { + Subdevice *pSubDevice; + // Alloc operation in unicast mode - NvHandle hDevice; - if ((status = CliSetSubDeviceContext(pRmCtrlParams->hClient, pParams->hSubDevice, &hDevice, &pGpu)) != NV_OK) - { + status = subdeviceGetByHandle(pCallContext->pClient, + pParams->hSubDevice, &pSubDevice); + + if (status != NV_OK) return status; - } + + pGpu = GPU_RES_GET_GPU(pSubDevice); + + GPU_RES_SET_THREAD_BC_STATE(pSubDevice); } status = memmgrGetSurfacePhysAttr_HAL(pGpu, GPU_GET_MEMORY_MANAGER(pGpu), pMemory, @@ -134,7 +140,7 @@ // gets allocated only when ATTR is set to COMPR_REQUIRED // if ((pMemory->pHwResource != NULL) && - pMemory->pHwResource->attr & + pMemory->pHwResource->attr & DRF_DEF(OS32, _ATTR, _COMPR, _REQUIRED)) { zero = 0; @@ -326,7 +332,7 @@ { OBJGPU *pGpu = pMemory->pGpu; PMEMORY_DESCRIPTOR pTempMemDesc = NULL; - NvU32 tempPageSize = 0; + NvU64 tempPageSize = 0; SLI_LOOP_START(SLI_LOOP_FLAGS_BC_ONLY) { @@ -396,6 +402,6 @@ ) { pParams->tag = pMemory->tag; - + return NV_OK; } diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/kernel/gpu/mem_mgr/mem_desc.c nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/kernel/gpu/mem_mgr/mem_desc.c --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/kernel/gpu/mem_mgr/mem_desc.c 2023-10-25 20:21:11.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/kernel/gpu/mem_mgr/mem_desc.c 2024-03-05 22:13:36.000000000 +0000 @@ -261,7 +261,7 @@ } } - if (RMCFG_FEATURE_PLATFORM_MODS || IsT194(pGpu)) + if (RMCFG_FEATURE_PLATFORM_MODS || IsT194(pGpu) || IsT234(pGpu)) { if ( (AddressSpace == ADDR_FBMEM) && !(Flags & MEMDESC_ALLOC_FLAGS_PROTECTED) && @@ -789,6 +789,67 @@ } break; + case ADDR_EGM: + { + MemoryManager *pMemoryManager = GPU_GET_MEMORY_MANAGER(pGpu); + NvU64 i; + + + NV_ASSERT_OK_OR_GOTO(status, osAllocPages(pMemDesc), done); + + pMemDesc->Allocated = NV_TRUE; + + // + // EGM address in the GMMU PTE should be zero base address and so + // the EGM base address is subtracted from the allocated EGM + // address. HSHUB later adds the socket local EGM base system physical address(SPA) + // before sending the transaction to TH500. zero-base address is + // required in passthrough virtualization where guest physical address + // is programmed in the GMMU PTE and the SPA is available only in + // the HSHUB registers. + // + // zero-base address is possible only when the EGM base address is + // available. There are platforms(like off-DUT MODS and dGPU MODS) + // where this is not available and full address is populated in + // the GMMU PTE itself and HSHUB is not programmed to add the SPA. + // + if (pMemoryManager->localEgmBasePhysAddr != 0) + { + for (i = 0; i < memdescGetPteArraySize(pMemDesc, AT_GPU); i++) + { + RmPhysAddr addr = memdescGetPhysAddr(pMemDesc, AT_GPU, i * pMemDesc->pageArrayGranularity); + NV_ASSERT_TRUE_OR_GOTO(status, addr > pMemoryManager->localEgmBasePhysAddr, + NV_ERR_INVALID_STATE, done); + memdescSetPte(pMemDesc, AT_GPU, i, addr - pMemoryManager->localEgmBasePhysAddr); + NV_PRINTF(LEVEL_INFO, "EGM allocation. pte index: %lld addr: 0x%llx zero-base addr: 0x%llx\n", + i, addr, addr - pMemoryManager->localEgmBasePhysAddr); + } + } + + if ((pMemDesc->_flags & MEMDESC_FLAGS_PHYSICALLY_CONTIGUOUS) && + RMCFG_FEATURE_PLATFORM_MODS) + { + if (pMemDesc->Alignment > RM_PAGE_SIZE) + { + RmPhysAddr addr = memdescGetPhysAddr(pMemDesc, AT_CPU, 0); + NvU64 offset; + + NV_ASSERT((addr & (RM_PAGE_SIZE - 1)) == 0); + + NV_ASSERT((pMemDesc->Alignment & (pMemDesc->Alignment - 1)) == 0); + offset = addr & (pMemDesc->Alignment - 1); + + if (offset) + { + NV_ASSERT((pMemDesc->PageCount * pMemDesc->pageArrayGranularity - pMemDesc->Size) >= offset); + NV_ASSERT(pMemDesc->PteAdjust == 0); + pMemDesc->PteAdjust += NvU64_LO32(pMemDesc->Alignment - offset); + } + } + } + + break; + } case ADDR_FBMEM: { Heap *pHeap = pMemDesc->pHeap; @@ -885,6 +946,28 @@ allocData.flags |= NVOS32_ALLOC_FLAGS_PROTECTED; } + // + // Assume all RM internal allocations to go into protected (CPR) + // video memory unless specified otherwise explicitly + // + if (gpuIsCCFeatureEnabled(pGpu)) + { + if (pMemDesc->_flags & MEMDESC_FLAGS_ALLOC_IN_UNPROTECTED_MEMORY) + { + // + // CC-TODO: Remove this check after non-CPR region is + // created. Not sure if RM will ever need to use non-CPR + // region for itself + // + NV_PRINTF(LEVEL_ERROR, "Non-CPR region still not created\n"); + NV_ASSERT_OR_RETURN(0, NV_ERR_INVALID_ARGUMENT); + } + else + { + allocData.flags |= NVOS32_ALLOC_FLAGS_PROTECTED; + } + } + allocData.attr |= DRF_DEF(OS32, _ATTR, _PHYSICALITY, _CONTIGUOUS); pFbAllocInfo = portMemAllocNonPaged(sizeof(FB_ALLOC_INFO)); @@ -924,7 +1007,7 @@ // depend on this. In the future we will have the PageCount be accurate. // pMemDesc->Size = requestedSize; - pMemDesc->PageCount = ((pMemDesc->Size + pMemDesc->PteAdjust + pMemDesc->pageArrayGranularity - 1) >> + pMemDesc->PageCount = ((pMemDesc->Size + pMemDesc->PteAdjust + pMemDesc->pageArrayGranularity - 1) >> BIT_IDX_32(pMemDesc->pageArrayGranularity)); } // We now have the memory @@ -982,6 +1065,7 @@ switch (pMemDesc->_addressSpace) { case ADDR_SYSMEM: + case ADDR_EGM: // Can't alloc sysmem on GSP firmware. if (RMCFG_FEATURE_PLATFORM_GSP && !memdescGetFlag(pMemDesc, MEMDESC_FLAGS_GUEST_ALLOCATED)) { @@ -994,10 +1078,51 @@ pMemDesc->_addressSpace = ADDR_FBMEM; pMemDesc->pHeap = GPU_GET_HEAP(pGpu); } + // + // If AMD SEV is enabled but CC or APM is not enabled on the GPU, + // all RM and client allocations must to to unprotected sysmem. + // So, we override any unprotected/protected flag set by either RM + // or client. + // If APM is enabled and RM is allocating sysmem for its internal use + // use such memory has to be unprotected as protected sysmem is not + // accessible to GPU + // + if ((sysGetStaticConfig(pSys))->bOsCCEnabled) + { + if (!gpuIsCCorApmFeatureEnabled(pGpu) || + (gpuIsApmFeatureEnabled(pGpu) && + !memdescGetFlag(pMemDesc, MEMDESC_FLAGS_SYSMEM_OWNED_BY_CLIENT))) + { + memdescSetFlag(pMemDesc, + MEMDESC_FLAGS_ALLOC_IN_UNPROTECTED_MEMORY, NV_TRUE); + } + } + else + { + // + // This flag has no meaning on non-SEV systems. So, unset it. The + // OS layer currently honours this flag irrespective of whether + // SEV is enabled or not + // + memdescSetFlag(pMemDesc, + MEMDESC_FLAGS_ALLOC_IN_UNPROTECTED_MEMORY, NV_FALSE); + } break; case ADDR_FBMEM: { + // + // When APM is enabled, all RM internal vidmem allocations go to + // unprotected memory. There is an underlying assumption that + // memdescAlloc won't be directly called in the client vidmem alloc + // codepath. Note that memdescAlloc still gets called in the client + // sysmem alloc codepath. See CONFCOMP-529 + // + if (gpuIsApmFeatureEnabled(pGpu)) + { + memdescSetFlag(pMemDesc, + MEMDESC_FLAGS_ALLOC_IN_UNPROTECTED_MEMORY, NV_TRUE); + } // If FB is broken then don't allow the allocation, unless running in L2 cache only mode if (pGpu->getProperty(pGpu, PDB_PROP_GPU_BROKEN_FB) && !gpuIsCacheOnlyModeEnabled(pGpu)) @@ -1335,6 +1460,7 @@ switch (pMemDesc->_addressSpace) { case ADDR_SYSMEM: + case ADDR_EGM: // invalidate if memory is cached in FB L2 cache. if (pMemDesc->_gpuCacheAttrib == NV_MEMORY_CACHED) { @@ -1513,6 +1639,7 @@ } if (pMemDesc->_addressSpace != ADDR_FBMEM && + pMemDesc->_addressSpace != ADDR_EGM && pMemDesc->_addressSpace != ADDR_SYSMEM) { return; @@ -1670,22 +1797,12 @@ Offset += pMemDesc->PteAdjust; } - // - // Sanity check, the top-level descriptor should be allocated or else - // memDesc must be marked as user allocate memory. This allows mapping of - // memDesc keeping track of PA's for user allocated memory, wherein RM - // marks the corresponding memDesc as not allocated. - // - NV_ASSERT_OR_RETURN(pMemDesc->Allocated || - memdescGetFlag(pMemDesc, MEMDESC_FLAGS_EXT_PAGE_ARRAY_MEM) || - memdescGetFlag(pMemDesc, MEMDESC_FLAGS_PEER_IO_MEM), - NV_ERR_INVALID_OBJECT_BUFFER); - NV_ASSERT_OR_RETURN(!memdescHasSubDeviceMemDescs(pMemDesc), NV_ERR_INVALID_OBJECT_BUFFER); switch (pMemDesc->_addressSpace) { case ADDR_SYSMEM: + case ADDR_EGM: { status = osMapSystemMemory(pMemDesc, Offset, Size, Kernel, Protect, pAddress, pPriv); @@ -1764,15 +1881,6 @@ break; } - // Mapping via PCIe BAR - - NvHandle hClient = NV01_NULL_OBJECT; - CALL_CONTEXT *pCallContext = resservGetTlsCallContext(); - if ((pCallContext != NULL) && (pCallContext->pClient != NULL)) - { - hClient = pCallContext->pClient->hClient; - } - // Determine where in BAR1 the mapping will go pMapping->FbApertureLen = Size; status = kbusMapFbAperture_HAL(pGpu, pKernelBus, @@ -1780,7 +1888,7 @@ &pMapping->FbAperture, &pMapping->FbApertureLen, BUS_MAP_FB_FLAGS_MAP_UNICAST, - hClient); + NULL); if (status != NV_OK) { portMemFree(pMapping); @@ -2249,6 +2357,47 @@ } /*! + * Static helper called from memdescFillPages. + * When dynamic granularity memdescs are enabled. We only need to copy over the pages + * without worrying about converting them to 4K. + * + * @param[in] pMemDesc Memory descriptor to fill + * @param[in] pageIndex Index into memory descriptor to fill from + * @param[in] pPages Array of physical addresses + * @param[in] pageCount Number of entries in pPages + * @param[in] pageSize Size of each page in pPages + * + * @returns None + */ +static void +_memdescFillPagesAtNativeGranularity +( + MEMORY_DESCRIPTOR *pMemDesc, + NvU32 pageIndex, + NvU64 *pPages, + NvU32 pageCount, + NvU64 pageSize +) +{ + NV_STATUS status; + + NV_ASSERT(pageIndex + pageCount < pMemDesc->PageCount); + + status = memdescSetPageArrayGranularity(pMemDesc, pageSize); + if (status != NV_OK) + { + return; + } + + for (NvU32 i = 0; i < pageCount; i++) + { + pMemDesc->_pteArray[pageIndex + i] = pPages[i]; + } + + pMemDesc->ActualSize = pageCount * pageSize; +} + +/*! * Fill the PTE array of a memory descriptor with an array of addresses * returned by pmaAllocatePages(). * @@ -2274,9 +2423,10 @@ NvU32 pageIndex, NvU64 *pPages, NvU32 pageCount, - NvU32 pageSize + NvU64 pageSize ) { + OBJGPU *pGpu = gpumgrGetSomeGpu(); NvU32 i, j, k; NvU32 numChunks4k = pageSize / RM_PAGE_SIZE; NvU32 offset4k = numChunks4k * pageIndex; @@ -2286,6 +2436,12 @@ NV_ASSERT(pMemDesc != NULL); + if (GPU_GET_MEMORY_MANAGER(pGpu)->bEnableDynamicGranularityPageArrays) + { + _memdescFillPagesAtNativeGranularity(pMemDesc, pageIndex, pPages, pageCount, pageSize); + return; + } + NV_ASSERT(offset4k < pMemDesc->PageCount); NV_ASSERT(portSafeAddU32(offset4k, pageCount4k, &result4k)); @@ -2423,7 +2579,20 @@ pageOffset = memdescGetPhysAddr(pTempMemDesc, AT_CPU, Offset) & (pTempMemDesc->_pageSize - 1); + + // Check for integer overflow + if (!portSafeAddU64(pageOffset, Size, &tmpSize)) + { + return NV_ERR_INVALID_ARGUMENT; + } + tmpSize = RM_ALIGN_UP(pageOffset + Size, pTempMemDesc->_pageSize); + + // Check for integer overflow + if (tmpSize < pageOffset + Size) + { + return NV_ERR_INVALID_ARGUMENT; + } } // Allocate the new MEMORY_DESCRIPTOR @@ -3411,7 +3580,7 @@ NvU64 memdescGetPageOffset ( MEMORY_DESCRIPTOR *pMemDesc, - NvU32 pageSize + NvU64 pageSize ) { NV_ASSERT(!memdescHasSubDeviceMemDescs(pMemDesc)); @@ -3900,7 +4069,7 @@ * * @returns Current page size. */ -NvU32 memdescGetPageSize +NvU64 memdescGetPageSize ( PMEMORY_DESCRIPTOR pMemDesc, ADDRESS_TRANSLATION addressTranslation @@ -3923,7 +4092,7 @@ ( PMEMORY_DESCRIPTOR pMemDesc, ADDRESS_TRANSLATION addressTranslation, - NvU32 pageSize + NvU64 pageSize ) { NV_ASSERT(!memdescHasSubDeviceMemDescs(pMemDesc)); @@ -4567,6 +4736,12 @@ RM_API *pRmApi = rmapiGetInterface(RMAPI_GPU_LOCK_INTERNAL); NV_MEMORY_LIST_ALLOCATION_PARAMS listAllocParams = {0}; + // Nothing to do without GSP + if (!IS_GSP_CLIENT(pGpu)) + { + return NV_OK; + } + switch (memdescGetAddressSpace(pMemDesc)) { @@ -4618,7 +4793,8 @@ pMemoryManager->hSubdevice, pHandle, hClass, - &listAllocParams), + &listAllocParams, + sizeof(listAllocParams)), end); // Register MemoryList object to GSP @@ -4638,3 +4814,27 @@ return status; } + +NV_STATUS +memdescSetPageArrayGranularity +( + MEMORY_DESCRIPTOR *pMemDesc, + NvU64 pageArrayGranularity +) +{ + // Make sure pageArrayGranularity is a power of 2 value. + NV_ASSERT_OR_RETURN((pageArrayGranularity & (pageArrayGranularity - 1)) == 0, NV_ERR_INVALID_ARGUMENT); + + // Allow setting the same granularity. + if (pMemDesc->pageArrayGranularity == pageArrayGranularity) + { + return NV_OK; + } + + // Make sure setting the page array happens before the pteArray is populated. + NV_ASSERT_OR_RETURN(pMemDesc->_pteArray[0] == 0, NV_ERR_INVALID_STATE); + + pMemDesc->pageArrayGranularity = pageArrayGranularity; + + return NV_OK; +} diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/kernel/gpu/mem_mgr/mem_mgr.c nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/kernel/gpu/mem_mgr/mem_mgr.c --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/kernel/gpu/mem_mgr/mem_mgr.c 2023-10-25 20:21:11.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/kernel/gpu/mem_mgr/mem_mgr.c 2024-03-05 22:13:36.000000000 +0000 @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 1993-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 1993-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -25,10 +25,12 @@ #include "gpu/mem_mgr/heap.h" #include "gpu/mem_sys/kern_mem_sys.h" #include "gpu/mem_mgr/mem_utils.h" +#include "gpu/mem_mgr/ce_utils.h" #include "mem_mgr/video_mem.h" #include "gpu/mem_mgr/fbsr.h" #include "gpu/mmu/kern_gmmu.h" #include "gpu/bus/kern_bus.h" +#include "gpu/bif/kernel_bif.h" #include "core/locks.h" #include "virtualization/kernel_vgpu_mgr.h" #include "vgpu/rpc.h" @@ -43,6 +45,11 @@ #include "class/cl0040.h" // NV01_MEMORY_LOCAL_USER #include "class/cl503c.h" #include "class/cl906f.h" // GF100_CHANNEL_GPFIFO +#include "os/os.h" +#include "gpu/gsp/kernel_gsp.h" +#include "gpu/conf_compute/conf_compute.h" + +#include "class/cl0050.h" static NV_STATUS _memmgrCreateFBSR(MemoryManager *pMemoryManager, NvU32); static NV_STATUS _memmgrCreateChildObjects(MemoryManager *pMemoryManager); @@ -108,7 +115,7 @@ NvU32 data32; // Check for ram size override. - pMemoryManager->Ram.fbOverrideSizeMb = ~0; + pMemoryManager->Ram.fbOverrideSizeMb = (NvU64)~0; if ((osReadRegistryDword(pGpu, NV_REG_STR_OVERRIDE_FB_SIZE, &data32) == NV_OK) && (data32 != 0)) { @@ -244,19 +251,6 @@ } } - if (osReadRegistryDword(pGpu, NV_REG_STR_RM_ENABLE_ADDRTREE, &data32) == NV_OK) - { - if (data32 == NV_REG_STR_RM_ENABLE_ADDRTREE_YES) - { - pMemoryManager->bPmaAddrTree = NV_TRUE; - NV_PRINTF(LEVEL_ERROR, "Enabled address tree for PMA via regkey.\n"); - } - } - else if (RMCFG_FEATURE_PLATFORM_MODS) - { - pMemoryManager->bPmaAddrTree = NV_TRUE; - NV_PRINTF(LEVEL_ERROR, "Enabled address tree for PMA for MODS.\n"); - } } NV_STATUS @@ -266,6 +260,16 @@ MemoryManager *pMemoryManager ) { + if (IS_GSP_CLIENT(pGpu)) + { + // + // Temporary hack to get OpenRM working without breaking SLI + // After fixing CORERM-4078, memmgrInitFbRegions() call should be removed from memsysStateInitLocked() + // and only left here + // + NV_ASSERT_OK_OR_RETURN(memmgrInitFbRegions(pGpu, pMemoryManager)); + } + // Determine the size of reserved memory NV_ASSERT_OK_OR_RETURN(memmgrPreInitReservedMemory_HAL(pGpu, pMemoryManager)); @@ -283,19 +287,10 @@ NvU32 i; NvBool bDynamicPageOffliningDisable = NV_FALSE; - if (IS_GSP_CLIENT(pGpu)) - { - // - // Temporary hack to get OpenRM working without breaking SLI - // After fixing CORERM-4078, memmgrInitFbRegions() call should be removed from memsysStateInitLocked() - // and only left here - // - NV_ASSERT_OK_OR_RETURN(memmgrInitFbRegions(pGpu, pMemoryManager)); - } - NV_ASSERT_OK_OR_RETURN(memmgrInitReservedMemory_HAL(pGpu, pMemoryManager, pMemoryManager->Ram.fbAddrSpaceSizeMb << 20)); _memmgrInitRegistryOverrides(pGpu, pMemoryManager); + // // Enable dynamic page blacklisting at this point before we call CreateHeap // since it internally calls heapGetBlacklistPages which depends on this property @@ -396,6 +391,76 @@ } NV_STATUS +memmgrVerifyGspDmaOps_IMPL +( + OBJGPU *pGpu, + MemoryManager *pMemoryManager +) +{ + KernelBus *pKernelBus = GPU_GET_KERNEL_BUS(pGpu); + NV_STATUS status = NV_OK; + MEMORY_DESCRIPTOR *pMemDesc; + NvU8 *pTestBuffer; + NvU32 testData = 0xdeadbeef; + TRANSFER_SURFACE surf = {0}; + + // + // Return early if CPU access to CPR vidmem is allowed as GSP DMA + // is not needed in this case + // + if (!kbusIsBarAccessBlocked(pKernelBus)) + return NV_OK; + + pTestBuffer = portMemAllocNonPaged(4096); + NV_ASSERT_OR_RETURN(pTestBuffer != NULL, NV_ERR_INSUFFICIENT_RESOURCES); + + portMemSet(pTestBuffer, 0, 4096); + + status = memdescCreate(&pMemDesc, pGpu, RM_PAGE_SIZE, RM_PAGE_SIZE, + NV_TRUE, ADDR_FBMEM, NV_MEMORY_UNCACHED, 0); + NV_ASSERT_OR_RETURN(status == NV_OK, status); + + status = memdescAlloc(pMemDesc); + NV_ASSERT_OR_GOTO(status == NV_OK, failed); + + surf.pMemDesc = pMemDesc; + surf.offset = sizeof(NvU32); // Choosing a random offset + + // Write test data to FB using GSP + status = memmgrMemWrite(pMemoryManager, &surf, &testData, sizeof(NvU32), + TRANSFER_FLAGS_NONE); + NV_ASSERT_OR_GOTO(status == NV_OK, failed); + + // Read the same location using GSP and confirm that GSP read is also working fine + status = memmgrMemRead(pMemoryManager, &surf, pTestBuffer, sizeof(NvU32), + TRANSFER_FLAGS_NONE); + NV_ASSERT_OR_GOTO(status == NV_OK, failed); + + if (((NvU32*)pTestBuffer)[0] != testData) + { + NV_PRINTF(LEVEL_ERROR, "####################################################\n"); + NV_PRINTF(LEVEL_ERROR, " Read back of data using GSP shows mismatch\n"); + NV_PRINTF(LEVEL_ERROR, " Test data: 0x%x Read Data: 0x%x\n", testData, ((NvU32*)pTestBuffer)[0]); + NV_PRINTF(LEVEL_ERROR, "####################################################\n"); + status = NV_ERR_INVALID_STATE; + NV_ASSERT_OR_GOTO(status == NV_OK, failed); + } + else + { + NV_PRINTF(LEVEL_INFO, "####################################################\n"); + NV_PRINTF(LEVEL_INFO, " Read back of data using GSP confirms write\n"); + NV_PRINTF(LEVEL_INFO, "####################################################\n"); + } + +failed: + memdescFree(pMemDesc); + memdescDestroy(pMemDesc); + portMemFree(pTestBuffer); + + return status; +} + +NV_STATUS memmgrStateLoad_IMPL ( OBJGPU *pGpu, @@ -430,8 +495,18 @@ NvU32 flags ) { + KernelMemorySystem *pKernelMemorySystem = GPU_GET_KERNEL_MEMORY_SYSTEM(pGpu); + NV_ASSERT((flags & GPU_STATE_FLAGS_PRESERVING) || pMemoryManager->zbcSurfaces == 0); + if (memmgrIsPmaEnabled(pMemoryManager) && + memmgrIsPmaSupportedOnPlatform(pMemoryManager) && + osNumaOnliningEnabled(pGpu->pOsGpuInfo) && + pKernelMemorySystem->memPartitionNumaInfo[0].bInUse) + { + pmaNumaOfflined(&pMemoryManager->pHeap->pmaObject); + } + return NV_OK; } @@ -515,6 +590,15 @@ fbsrDestroy_HAL(pGpu, pMemoryManager->pFbsr[i]); } } + if (memmgrIsLocalEgmEnabled(pMemoryManager)) + { + if (!IS_VIRTUAL_WITH_SRIOV(pGpu)) + { + kbusUnreserveP2PPeerIds_HAL(pGpu, GPU_GET_KERNEL_BUS(pGpu), NVBIT(pMemoryManager->localEgmPeerId)); + } + pMemoryManager->localEgmPeerId = BUS_INVALID_PEER; + pMemoryManager->bLocalEgmEnabled = NV_FALSE; + } memmgrScrubDestroy_HAL(pGpu, pMemoryManager); } @@ -749,12 +833,21 @@ failed); portMemSet(¶ms, 0, sizeof(params)); - params.flags = NV503C_ALLOC_PARAMETERS_FLAGS_TYPE_BAR1; + if (pGpu->getProperty(pGpu, PDB_PROP_GPU_COHERENT_CPU_MAPPING)) + { + params.flags = NV503C_ALLOC_PARAMETERS_FLAGS_TYPE_NVLINK; + } + else + { + params.flags = NV503C_ALLOC_PARAMETERS_FLAGS_TYPE_BAR1; + } status = pRmApi->AllocWithHandle(pRmApi, pMemoryManager->hClient, pMemoryManager->hSubdevice, hThirdPartyP2P, - NV50_THIRD_PARTY_P2P, ¶ms); + NV50_THIRD_PARTY_P2P, + ¶ms, + sizeof(params)); if (status != NV_OK) { NV_PRINTF(LEVEL_WARNING, "Error creating internal ThirdPartyP2P object: %x\n", @@ -812,6 +905,19 @@ *pFbUsedSize = heapTotalSpace - heapFreeSpace; } + // + // GSP's WPR region has its own save/restore mechanism and does not need + // to be accounted for in total FB size used - which is needed to find out + // how much SYSMEM needs to be allocated to save all FB memory + // + if (IS_GSP_CLIENT(pGpu)) + { + KernelGsp *pKernelGsp = GPU_GET_KERNEL_GSP(pGpu); + NvU64 gspWprRegionSize = pKernelGsp->pWprMeta->gspFwWprEnd - pKernelGsp->pWprMeta->gspFwWprStart; + + *pFbUsedSize = *pFbUsedSize - gspWprRegionSize; + } + return NV_OK; } @@ -1035,6 +1141,8 @@ *pMemAperture = NV0041_CTRL_CMD_GET_SURFACE_PHYS_ATTR_APERTURE_VIDMEM; else if (memdescGetAddressSpace(pMemDesc) == ADDR_SYSMEM) *pMemAperture = NV0041_CTRL_CMD_GET_SURFACE_PHYS_ATTR_APERTURE_SYSMEM; + else if (memdescGetAddressSpace(pMemDesc) == ADDR_EGM) + *pMemAperture = NV0041_CTRL_CMD_GET_SURFACE_PHYS_ATTR_APERTURE_SYSMEM; else if (memdescGetAddressSpace(pMemDesc) == ADDR_VIRTUAL ) { // @@ -1090,7 +1198,7 @@ return NV_OK; } -NvU32 +NvU64 memmgrDeterminePageSize_IMPL ( MemoryManager *pMemoryManager, @@ -1107,7 +1215,7 @@ NV_ADDRESS_SPACE addrSpace; NvBool bIsBigPageSupported; RM_ATTR_PAGE_SIZE pageSizeAttr; - NvU32 pageSize = 0; + NvU64 pageSize = 0; if (pGpu->getProperty(pGpu, PDB_PROP_GPU_TEGRA_SOC_NVDISPLAY) || (pKernelGmmu == NULL)) { @@ -1158,6 +1266,7 @@ { NV_PRINTF(LEVEL_ERROR, "Big/Huge/512MB page size not supported in sysmem.\n"); + NV_ASSERT_OR_RETURN(0, 0); } else @@ -1447,6 +1556,8 @@ NvU32 idxSlowRegion = 0; NvBool bAllocProtected = NV_FALSE; + bAllocProtected = gpuIsCCFeatureEnabled(pGpu); + // // This is a hack solely for Vista (on Vista the OS controls the majority of heap). // Linux and Mac don't have reserved memory and doesn't use this function. @@ -1522,6 +1633,11 @@ NV_ASSERT(!pMemoryManager->Ram.fbRegion[idxFastRegion].bRsvdRegion); NV_ASSERT(!pMemoryManager->Ram.fbRegion[idxSlowRegion].bRsvdRegion); + // + // Whenever Hopper CC is enabled, it is mandatory to put allocations + // like page tables, CBC and fault buffers in CPR region. Cannot put + // reserved memory in protected region in non CC cases + // if (!bAllocProtected) { NV_ASSERT(!pMemoryManager->Ram.fbRegion[idxISORegion].bProtected); @@ -1670,6 +1786,7 @@ portMemSet(pFbAllocInfo, 0, sizeof(FB_ALLOC_INFO)); portMemSet(pFbAllocPageFormat, 0, sizeof(FB_ALLOC_PAGE_FORMAT)); + pFbAllocInfo->hClient = hClient; pFbAllocInfo->pageFormat = pFbAllocPageFormat; // @@ -1835,6 +1952,7 @@ { PMA_REGION_DESCRIPTOR *pFirstPmaRegionDesc = NULL; NvU32 numPmaRegions; + NvU32 pmaConfig = PMA_QUERY_NUMA_ONLINED; NV_ASSERT_OK_OR_RETURN(pmaGetRegionInfo(&pHeap->pmaObject, &numPmaRegions, &pFirstPmaRegionDesc)); @@ -1843,16 +1961,23 @@ pmaGetFreeMemory(&pHeap->pmaObject, &freeMem); pmaGetTotalMemory(&pHeap->pmaObject, &size); + NV_ASSERT_OK(pmaQueryConfigs(&pHeap->pmaObject, &pmaConfig)); + // // MIG won't be used alongside APM and hence the check below is of no use // Even if we enable the check for APM the check will fail given that after // enabling "scrub on free" using virtual CE writes, memory gets consumed by // page tables backing the scrubber channel virtual mappings and hence the // calculation below no longer holds good + // In case of HCC, structures like PB, GPFIFO and USERD for scrubber and golden + // channels are required to be in CPR vidmem. This changes the calculation below + // We can ignore this for the non-MIG case. // - if (!gpuIsApmFeatureEnabled(pGpu) || - !memmgrUseVasForCeMemoryOps(pMemoryManager) || - IS_MIG_ENABLED(pGpu)) + // When FB memory is onlined as NUMA node, kernel can directly alloc FB memory + // and hence free memory can not be expected to be same as total memory. + // + if ((!gpuIsCCorApmFeatureEnabled(pGpu) || IS_MIG_ENABLED(pGpu)) && + !(pmaConfig & PMA_QUERY_NUMA_ONLINED)) { // // PMA should be completely free at this point, otherwise we risk @@ -1860,18 +1985,18 @@ // offset argument is not implemented as of this writing, so we // only get the base address of the region that contains it). There // is a known allocation from the top-level scrubber channel that - // is expected to be no larger than 64K. Issue a warning for any + // is expected to be no larger than 128K. Issue a warning for any // other uses. // - if ((size > RM_PAGE_SIZE_64K) && - (freeMem < (size - RM_PAGE_SIZE_64K))) + if ((size > RM_PAGE_SIZE_128K) && + (freeMem < (size - RM_PAGE_SIZE_128K))) { NV_PRINTF(LEVEL_ERROR, "Assumption that PMA is empty (after accounting for the top-level scrubber) is not met!\n"); NV_PRINTF(LEVEL_ERROR, " free space = 0x%llx bytes, total space = 0x%llx bytes\n", freeMem, size); - NV_ASSERT_OR_RETURN(freeMem >= (size - RM_PAGE_SIZE_64K), + NV_ASSERT_OR_RETURN(freeMem >= (size - RM_PAGE_SIZE_128K), NV_ERR_INVALID_STATE); } } @@ -1916,7 +2041,10 @@ NV_ASSERT_OR_RETURN(!rangeIsEmpty(pMemoryManager->MIGMemoryPartitioningInfo.partitionableMemoryRange), NV_ERR_INVALID_STATE); - NV_ASSERT_OK_OR_RETURN(memmgrSetMIGPartitionableBAR1Range(pGpu, pMemoryManager)); + if (!KBUS_CPU_VISIBLE_BAR12_DISABLED(pGpu)) + { + NV_ASSERT_OK_OR_RETURN(memmgrSetMIGPartitionableBAR1Range(pGpu, pMemoryManager)); + } if (IS_GSP_CLIENT(pGpu)) { @@ -1938,7 +2066,7 @@ ( OBJGPU *pGpu, MemoryManager *pMemoryManager, - NvU32 pageSize, + NvU64 pageSize, NvU32 pageCount, NvU32 kind, NvU64 surfOffset, @@ -1956,12 +2084,13 @@ if (!memmgrIsKind_HAL(pMemoryManager, FB_IS_KIND_COMPRESSIBLE, kind)) return NV_OK; + // TODO: We will have to support compression on vGPU HOST for AC NV_ASSERT(compTagStartOffset != ~(NvU32)0); pComprInfo->compPageShift = pMemorySystemConfig->comprPageShift; pComprInfo->compTagLineMin = compTagStartOffset; pComprInfo->compPageIndexLo = (NvU32)(surfOffset >> pComprInfo->compPageShift); - pComprInfo->compPageIndexHi = (NvU32)((surfOffset + (NvU64)pageSize * (NvU64)pageCount - 1) >> pComprInfo->compPageShift); + pComprInfo->compPageIndexHi = (NvU32)((surfOffset + pageSize * pageCount - 1) >> pComprInfo->compPageShift); pComprInfo->compTagLineMultiplier = 1; return NV_OK; @@ -2027,23 +2156,6 @@ offset, kind, pComprInfo); } -NvBool -memmgrIsCompressible_IMPL -( - MemoryManager *pMemoryManager, - MEMORY_DESCRIPTOR *pMemDesc -) -{ - COMPR_INFO comprInfo; - NvU32 kind; - - NV_CHECK_OR_RETURN(LEVEL_ERROR, - memmgrGetKindComprFromMemDesc(pMemoryManager, pMemDesc, 0, &kind, &comprInfo) == NV_OK, - NV_FALSE); - - return memmgrIsKind_HAL(pMemoryManager, FB_IS_KIND_COMPRESSIBLE, comprInfo.kind); -} - void memmgrSetMIGPartitionableMemoryRange_IMPL ( @@ -2077,12 +2189,18 @@ { KernelBus *pKernelBus = GPU_GET_KERNEL_BUS(pGpu); OBJVASPACE *pBar1VAS = kbusGetBar1VASpace_HAL(pGpu, pKernelBus); - OBJEHEAP *pVASHeap = vaspaceGetHeap(pBar1VAS); + OBJEHEAP *pVASHeap; NvU64 largestFreeOffset = 0; NvU64 largestFreeSize = 0; NvU64 partitionableBar1Start; NvU64 partitionableBar1End; + if (pGpu->getProperty(pGpu, PDB_PROP_GPU_ZERO_FB)) + return NV_OK; + + NV_ASSERT_OR_RETURN(pBar1VAS != NULL, NV_ERR_INVALID_STATE); + pVASHeap = vaspaceGetHeap(pBar1VAS); + // Get partitionable BAR1 range pVASHeap->eheapInfo(pVASHeap, NULL, NULL, &largestFreeOffset, &largestFreeSize, NULL, NULL); @@ -2145,64 +2263,96 @@ NV_STATUS rmStatus = NV_OK; NvHandle hMemory = 0; RM_API *pRmApi = rmapiGetInterface(RMAPI_GPU_LOCK_INTERNAL); + NvBool bNumaEnabled = osNumaOnliningEnabled(pGpu->pOsGpuInfo); NV_ASSERT_OR_RETURN(pKernelMIGManager != NULL, NV_ERR_INVALID_STATE); NV_ASSERT_OK_OR_RETURN(kmemsysGetMIGGPUInstanceMemInfo(pGpu, pKernelMemorySystem, swizzId, pAddrRange)); // // Only allocate memory for non swizzID-0 GPU instances as swizzID-0 owns full - // gpu and there is no need to pre-reserve memory for that + // gpu and there is no need to pre-reserve memory for that and non + // coherent systems. In coherent NUMA systems, NVOS32_ALLOC_FLAGS_FIXED_ADDRESS_ALLOCATE + // is not supported and the memory comes from the MIG partition memory + // NUMA node. // if (kmigmgrIsMemoryPartitioningNeeded_HAL(pGpu, pKernelMIGManager, swizzId)) { - // - // Allocate memory using vidHeapControl - // - // vidHeapControl calls should happen outside GPU locks - // This is a PMA requirement as memory allocation calls may invoke eviction - // which UVM could get stuck behind GPU lock - // See Bug 1735851-#24 - // - rmGpuLocksRelease(GPUS_LOCK_FLAGS_NONE, NULL); - - // Allocate gpfifo entries - NV_MEMORY_ALLOCATION_PARAMS memAllocParams; - portMemSet(&memAllocParams, 0, sizeof(NV_MEMORY_ALLOCATION_PARAMS)); - memAllocParams.owner = HEAP_OWNER_RM_CLIENT_GENERIC; - memAllocParams.type = NVOS32_TYPE_IMAGE; - memAllocParams.size = rangeLength(*pAddrRange); - memAllocParams.attr = DRF_DEF(OS32, _ATTR, _LOCATION, _VIDMEM); - memAllocParams.attr |= DRF_DEF(OS32, _ATTR, _PHYSICALITY, _CONTIGUOUS); - memAllocParams.attr |= DRF_DEF(OS32, _ATTR, _PAGE_SIZE, _DEFAULT); - memAllocParams.attr2 = DRF_DEF(OS32, _ATTR2, _PAGE_OFFLINING, _OFF); // free the offlined pages - memAllocParams.flags |= NVOS32_ALLOC_FLAGS_FIXED_ADDRESS_ALLOCATE; - memAllocParams.rangeLo = 0; - memAllocParams.rangeHi = 0; - memAllocParams.offset = pAddrRange->lo; // Offset needed if fixed address allocation - memAllocParams.hVASpace = 0; // Physical allocation - memAllocParams.internalflags = NVOS32_ALLOC_INTERNAL_FLAGS_SKIP_SCRUB; - - rmStatus = pRmApi->Alloc(pRmApi, - pMemoryManager->MIGMemoryPartitioningInfo.hClient, - pMemoryManager->MIGMemoryPartitioningInfo.hSubdevice, - &hMemory, - NV01_MEMORY_LOCAL_USER, - &memAllocParams); - - // Reaquire the GPU locks - if (rmGpuLocksAcquire(GPUS_LOCK_FLAGS_NONE, RM_LOCK_MODULES_MEM) != NV_OK) + if(bNumaEnabled) { - NV_PRINTF(LEVEL_ERROR, "failed to grab RM-Lock\n"); - DBG_BREAKPOINT(); - rmStatus = NV_ERR_GENERIC; - goto cleanup; - } + NvS32 numaNodeId; + NvU64 partitionBaseAddr = pAddrRange->lo; + NvU64 partitionSize = rangeLength(*pAddrRange); + + if (kmigmgrGetSwizzIdInUseMask(pGpu, pKernelMIGManager) == 0x0) + { + // Remove swizz Id 0 / baremetal GPU memory NUMA node + pmaNumaOfflined(&GPU_GET_HEAP(pGpu)->pmaObject); + kmemsysNumaRemoveMemory_HAL(pGpu, pKernelMemorySystem, 0); + } - if (rmStatus != NV_OK) + // + // The memory gets removed in memmgrFreeMIGGPUInstanceMemory if + // there is any failure after adding the memory. + // + NV_ASSERT_OK_OR_RETURN(kmemsysNumaAddMemory_HAL(pGpu, + pKernelMemorySystem, + swizzId, + partitionBaseAddr, + partitionSize, + &numaNodeId)); + } + else { - NV_PRINTF(LEVEL_ERROR, - "Unable to allocate physical memory for GPU instance.\n"); - return rmStatus; + // + // Allocate memory using vidHeapControl + // + // vidHeapControl calls should happen outside GPU locks + // This is a PMA requirement as memory allocation calls may invoke eviction + // which UVM could get stuck behind GPU lock + // See Bug 1735851-#24 + // + rmGpuLocksRelease(GPUS_LOCK_FLAGS_NONE, NULL); + + // Allocate gpfifo entries + NV_MEMORY_ALLOCATION_PARAMS memAllocParams; + portMemSet(&memAllocParams, 0, sizeof(NV_MEMORY_ALLOCATION_PARAMS)); + memAllocParams.owner = HEAP_OWNER_RM_CLIENT_GENERIC; + memAllocParams.type = NVOS32_TYPE_IMAGE; + memAllocParams.size = rangeLength(*pAddrRange); + memAllocParams.attr = DRF_DEF(OS32, _ATTR, _LOCATION, _VIDMEM); + memAllocParams.attr |= DRF_DEF(OS32, _ATTR, _PHYSICALITY, _CONTIGUOUS); + memAllocParams.attr |= DRF_DEF(OS32, _ATTR, _PAGE_SIZE, _DEFAULT); + memAllocParams.attr2 = DRF_DEF(OS32, _ATTR2, _PAGE_OFFLINING, _OFF); // free the offlined pages + memAllocParams.flags |= NVOS32_ALLOC_FLAGS_FIXED_ADDRESS_ALLOCATE; + memAllocParams.rangeLo = 0; + memAllocParams.rangeHi = 0; + memAllocParams.offset = pAddrRange->lo; // Offset needed if fixed address allocation + memAllocParams.hVASpace = 0; // Physical allocation + memAllocParams.internalflags = NVOS32_ALLOC_INTERNAL_FLAGS_SKIP_SCRUB; + + rmStatus = pRmApi->Alloc(pRmApi, + pMemoryManager->MIGMemoryPartitioningInfo.hClient, + pMemoryManager->MIGMemoryPartitioningInfo.hSubdevice, + &hMemory, + NV01_MEMORY_LOCAL_USER, + &memAllocParams, + sizeof(memAllocParams)); + + // Reaquire the GPU locks + if (rmGpuLocksAcquire(GPUS_LOCK_FLAGS_NONE, RM_LOCK_MODULES_MEM) != NV_OK) + { + NV_PRINTF(LEVEL_ERROR, "failed to grab RM-Lock\n"); + DBG_BREAKPOINT(); + rmStatus = NV_ERR_GENERIC; + goto cleanup; + } + + if (rmStatus != NV_OK) + { + NV_PRINTF(LEVEL_ERROR, + "Unable to allocate physical memory for GPU instance.\n"); + return rmStatus; + } } } rmStatus = _memmgrInitMIGMemoryPartitionHeap(pGpu, pMemoryManager, swizzId, pAddrRange, ppMemoryPartitionHeap); @@ -2239,6 +2389,10 @@ NV_STATUS status = NV_OK; KernelMIGManager *pKernelMIGManager = GPU_GET_KERNEL_MIG_MANAGER(pGpu); Heap *pMemoryPartitionHeap = NULL; + NvBool bNumaEnabled = osNumaOnliningEnabled(pGpu->pOsGpuInfo); + KernelMemorySystem *pKernelMemorySystem = GPU_GET_KERNEL_MEMORY_SYSTEM(pGpu); + NvU64 partitionBaseAddr = pAddrRange->lo; + NvU64 partitionSize = rangeLength(*pAddrRange); // Use default heap for swizzID-0 as we don't prereserve memory for swizzID-0 NV_ASSERT_OR_RETURN(pKernelMIGManager != NULL, NV_ERR_INVALID_STATE); @@ -2267,12 +2421,34 @@ status, memmgrPmaInitialize(pGpu, pMemoryManager, &pMemoryPartitionHeap->pmaObject), fail); + + if (bNumaEnabled) + { + NV_ASSERT_OR_GOTO(pKernelMemorySystem->memPartitionNumaInfo[swizzId].bInUse, fail); + partitionBaseAddr = pKernelMemorySystem->memPartitionNumaInfo[swizzId].offset; + partitionSize = pKernelMemorySystem->memPartitionNumaInfo[swizzId].size; + + // + // The base and size passed here is the FB base and size and + // not the partition's. pmaNumaOnlined requires the FB base and + // size to convert between FB local address and SPA. + // memmgrPmaRegisterRegions is where the partition's base and size + // is reported to PMA. + // + NV_ASSERT_OK_OR_GOTO( + status, + pmaNumaOnlined(&pMemoryPartitionHeap->pmaObject, + pKernelMemorySystem->memPartitionNumaInfo[swizzId].numaNodeId, + pKernelMemorySystem->coherentCpuFbBase, + pKernelMemorySystem->numaOnlineSize), + fail); + } } NV_ASSERT_OK_OR_GOTO( status, - heapInit(pGpu, pMemoryPartitionHeap, pAddrRange->lo, - rangeLength(*pAddrRange), + heapInit(pGpu, pMemoryPartitionHeap, partitionBaseAddr, + partitionSize, HEAP_TYPE_PARTITION_LOCAL, GPU_GFID_PF, NULL), @@ -2330,9 +2506,10 @@ { RM_API *pRmApi = rmapiGetInterface(RMAPI_GPU_LOCK_INTERNAL); KernelMIGManager *pKernelMIGManager = GPU_GET_KERNEL_MIG_MANAGER(pGpu); + KernelMemorySystem *pKernelMemorySystem = GPU_GET_KERNEL_MEMORY_SYSTEM(pGpu); + NvBool bNumaEnabled = osNumaOnliningEnabled(pGpu->pOsGpuInfo); NV_ASSERT_OR_RETURN(pKernelMIGManager != NULL, NV_ERR_INVALID_STATE); - NV_CHECK_OR_RETURN(LEVEL_SILENT, hMemory != NV01_NULL_OBJECT, NV_OK); // Nothing to do for swizzId 0 as we neither allocate memory nor allocate new heap object if (!kmigmgrIsMemoryPartitioningNeeded_HAL(pGpu, pKernelMIGManager, swizzId)) @@ -2341,8 +2518,35 @@ objDelete(*ppMemoryPartitionHeap); *ppMemoryPartitionHeap = NULL; + if (bNumaEnabled) + { + kmemsysNumaRemoveMemory_HAL(pGpu, pKernelMemorySystem, swizzId); + + if (kmigmgrGetSwizzIdInUseMask(pGpu, pKernelMIGManager) == 0x0) + { + NvS32 numaNodeId; + + // Add back the baremetal GPU memory NUMA node. + NV_ASSERT_OK_OR_RETURN(kmemsysNumaAddMemory_HAL(pGpu, + pKernelMemorySystem, + 0, + pKernelMemorySystem->numaOnlineBase, + pKernelMemorySystem->numaOnlineSize, + &numaNodeId)); + // Baremetal NUMA node id should be same as pGpu->numaNodeId + NV_ASSERT_OR_RETURN(numaNodeId == pGpu->numaNodeId, NV_ERR_INVALID_STATE); + NV_ASSERT_OK_OR_RETURN(pmaNumaOnlined(&GPU_GET_HEAP(pGpu)->pmaObject, + pGpu->numaNodeId, + pKernelMemorySystem->coherentCpuFbBase, + pKernelMemorySystem->numaOnlineSize)); + } + } + // Free allocated memory - pRmApi->Free(pRmApi, pMemoryManager->MIGMemoryPartitioningInfo.hClient, hMemory); + if (!bNumaEnabled && (hMemory != NV01_NULL_OBJECT)) + { + pRmApi->Free(pRmApi, pMemoryManager->MIGMemoryPartitioningInfo.hClient, hMemory); + } return NV_OK; } @@ -2403,6 +2607,15 @@ NV_ASSERT(NV_OK == status); + // + // Allocate the pool in CPR in case of Confidential Compute + // When Hopper Confidential Compute is enabled, page tables + // cannot be in non-CPR region + // + if (gpuIsCCFeatureEnabled(pGpu) && (status == NV_OK)) + { + rmMemPoolAllocateProtectedMemory(pMemoryManager->pPageLevelReserve, NV_TRUE); + } } return status; } @@ -2527,9 +2740,10 @@ pmaInitFlags |= PMA_INIT_NUMA; } - if (memmgrIsPmaAddrTree(pMemoryManager)) + if (gpuIsSelfHosted(pGpu)) { - pmaInitFlags |= PMA_INIT_ADDRTREE; + NV_PRINTF(LEVEL_INFO, "Initializing PMA with NUMA_AUTO_ONLINE flag.\n"); + pmaInitFlags |= PMA_INIT_NUMA_AUTO_ONLINE; } status = pmaInitialize(pPma, pmaInitFlags); @@ -2541,6 +2755,8 @@ if (bNumaEnabled) { + KernelMemorySystem *pKernelMemorySystem = GPU_GET_KERNEL_MEMORY_SYSTEM(pGpu); + NvU32 numaSkipReclaimVal = NV_REG_STR_RM_NUMA_ALLOC_SKIP_RECLAIM_PERCENTAGE_DEFAULT; if (osReadRegistryDword(pGpu, NV_REG_STR_RM_NUMA_ALLOC_SKIP_RECLAIM_PERCENTAGE, &numaSkipReclaimVal) == NV_OK) @@ -2551,6 +2767,15 @@ } } pmaNumaSetReclaimSkipThreshold(pPma, numaSkipReclaimVal); + + // Full FB memory is added and onlined already + if (pKernelMemorySystem->memPartitionNumaInfo[0].bInUse) + { + NV_ASSERT_OK_OR_RETURN(pmaNumaOnlined(pPma, pGpu->numaNodeId, + pKernelMemorySystem->coherentCpuFbBase, + pKernelMemorySystem->numaOnlineSize)); + } + } return NV_OK; @@ -2630,7 +2855,10 @@ NvU32 blPageIndex; NvU32 blackListCount; NvU64 base, size; + NvU64 pmaTotalMemorySize = 0; NV_STATUS status = NV_OK; + const MEMORY_SYSTEM_STATIC_CONFIG *pMemsysConfig = + kmemsysGetStaticConfig(pGpu, GPU_GET_KERNEL_MEMORY_SYSTEM(pGpu)); blackListCount = pHeap->blackListAddresses.count; base = pHeap->base; @@ -2720,6 +2948,7 @@ } } + pmaTotalMemorySize += (pmaRegion.limit - pmaRegion.base + 1); NV_PRINTF(LEVEL_INFO, "Register FB region %llx..%llx of size %llx with PMA\n", pmaRegion.base, pmaRegion.limit, @@ -2745,6 +2974,18 @@ pmaRegionIdx++; } + if (gpuIsSelfHosted(pGpu) && osNumaOnliningEnabled(pGpu->pOsGpuInfo)) + { + // + // NUMA onlined memory size should not exceed memory size assigned to PMA. + // TODO : Currently in selfhosted and P9+GV100 systems numaOnlined size is less + // than PMA Memory Size. Ideally both of them should be identical. Bug 4051320. + // + NvU64 numaTotalSize = 0; + NvU64 numaFreeSize = 0; + osGetNumaMemoryUsage(pPma->numaNodeId, &numaFreeSize, &numaTotalSize); + NV_ASSERT_OR_RETURN(pmaTotalMemorySize >= numaTotalSize, NV_ERR_INVALID_STATE); + } // // bug #200354346, make sure the RM reserved region(s) are // scrubbed during the region creation itself. Top Down scrubber, @@ -2757,9 +2998,9 @@ _pmaInitFailed: portMemFree(pBlacklistPages); - if ((status == NV_OK) && (pMemoryManager->fbOverrideStartKb != 0)) + if ((status == NV_OK) && (pMemsysConfig->fbOverrideStartKb != 0)) { - NvU64 allocSize = NV_ALIGN_UP(((NvU64)pMemoryManager->fbOverrideStartKb << 10), PMA_GRANULARITY); + NvU64 allocSize = NV_ALIGN_UP(((NvU64)pMemsysConfig->fbOverrideStartKb << 10), PMA_GRANULARITY); NvU32 numPages = (NvU32)(allocSize >> PMA_PAGE_SHIFT); PMA_ALLOCATION_OPTIONS allocOptions = {0}; @@ -2778,7 +3019,6 @@ portMemFree(pPages); } } - if (status != NV_OK) { if (memmgrIsPmaInitialized(pMemoryManager)) @@ -2867,6 +3107,44 @@ FOR_EACH_VALID_GPU_INSTANCE_END(); } +/*! + * @brief Gets total memory for all valid GPU instances + * + * @param pGpu + * @param pMemoryManager + * @param[out] pBytes pointer to the total memory + * + */ +void +memmgrGetTotalMemoryForAllMIGGPUInstances_IMPL +( + OBJGPU *pGpu, + MemoryManager *pMemoryManager, + NvU64 *pBytes +) +{ + NvU64 val = 0; + Heap *pHeap = NULL; + KernelMIGManager *pKernelMIGManager = GPU_GET_KERNEL_MIG_MANAGER(pGpu); + KERNEL_MIG_GPU_INSTANCE *pKernelMIGGPUInstance; + + *pBytes = 0; + + FOR_EACH_VALID_GPU_INSTANCE(pGpu, pKernelMIGManager, pKernelMIGGPUInstance) + { + NV_ASSERT(pKernelMIGGPUInstance->pMemoryPartitionHeap != NULL); + pHeap = pKernelMIGGPUInstance->pMemoryPartitionHeap; + + if (memmgrIsPmaInitialized(pMemoryManager)) + pmaGetTotalMemory(&pHeap->pmaObject, &val); + else + heapGetSize(pHeap, &val); + + *pBytes += val; + } + FOR_EACH_VALID_GPU_INSTANCE_END(); +} + void memmgrGetTopLevelScrubberStatus_IMPL ( @@ -3077,4 +3355,134 @@ ¶ms, sizeof(params))); return params.hostReservedFb; -} \ No newline at end of file +} + +/*! + * @brief Memory Manager State post load + * + * @param[in] pGpu GPU pointer + * @param[in/out] pMemoryManager MemoryManager pointer + * @param[in] flags State transition flags + * + * @returns On success, returns NV_OK. + * On failure, returns error code. + */ +NV_STATUS +memmgrStatePostLoad_IMPL +( + OBJGPU *pGpu, + MemoryManager *pMemoryManager, + NvU32 flags +) +{ + if (memmgrIsLocalEgmSupported(pMemoryManager)) + { + NvU64 egmPhysAddr, egmSize; + NvS32 egmNodeId; + NvU32 data32; + KernelBif *pKernelBif = GPU_GET_KERNEL_BIF(pGpu); + + pMemoryManager->localEgmNodeId = -1; + if (gpuIsSelfHosted(pGpu) && + pKernelBif->getProperty(pKernelBif, PDB_PROP_KBIF_IS_C2C_LINK_UP) && // EGM can be enabled only in C2C path. + (osGetEgmInfo(pGpu, &egmPhysAddr, &egmSize, &egmNodeId) == NV_OK) && + (egmSize != 0)) + { + pMemoryManager->localEgmBasePhysAddr = egmPhysAddr; + pMemoryManager->localEgmSize = egmSize; + pMemoryManager->localEgmNodeId = egmNodeId; + // + // Using fixed Peer ID 7 for local EGM so that vGPU + // migration doesn't fail because of peer id conflict in + // the new host system. + // + pMemoryManager->localEgmPeerId = 7; + pMemoryManager->bLocalEgmEnabled = NV_TRUE; + } + + // + // regkey can override the production flow values. + // Note that this could cause an issue with vGPU migration + // if one host system uses regkey to override the EGM peer id + // and other host system doesn't. + // + if (osReadRegistryDword(pGpu, NV_REG_STR_RM_ENABLE_LOCAL_EGM_PEER_ID, &data32) == NV_OK) + { + pMemoryManager->bLocalEgmEnabled = NV_TRUE; + pMemoryManager->localEgmPeerId = data32; + } + } + + // + // Reserve the peerID used for local EGM so that the peerID isn't + // resused for other peer Gpus. + // + if (memmgrIsLocalEgmEnabled(pMemoryManager)) + { + if (kbusReserveP2PPeerIds_HAL(pGpu, GPU_GET_KERNEL_BUS(pGpu), NVBIT(pMemoryManager->localEgmPeerId)) == NV_OK) + { + { + NV2080_CTRL_INTERNAL_HSHUB_EGM_CONFIG_PARAMS params = { 0 }; + RM_API *pRmApi = GPU_GET_PHYSICAL_RMAPI(pGpu); + NV_STATUS status; + + params.egmPeerId = pMemoryManager->localEgmPeerId; + + // Call physical HSHUB to program the EGM PeerId settings. + + status = pRmApi->Control(pRmApi, + pGpu->hInternalClient, + pGpu->hInternalSubdevice, + NV2080_CTRL_CMD_INTERNAL_HSHUB_EGM_CONFIG, + ¶ms, + sizeof(params)); + if (status != NV_OK) + { + NV_PRINTF(LEVEL_ERROR, "HSHUB programming failed for EGM Peer ID: %u\n", + pMemoryManager->localEgmPeerId); + pMemoryManager->bLocalEgmEnabled = NV_FALSE; + pMemoryManager->localEgmPeerId = BUS_INVALID_PEER; + return status; + } + } + } + else + { + NV_PRINTF(LEVEL_ERROR, + "Peer ID specified for local EGM already in use!\n"); + pMemoryManager->bLocalEgmEnabled = NV_FALSE; + pMemoryManager->localEgmPeerId = BUS_INVALID_PEER; + return NV_ERR_INVALID_ARGUMENT; + } + } + else + { + pMemoryManager->localEgmPeerId = BUS_INVALID_PEER; + } + return NV_OK; +} + +NV_STATUS +memmgrInitCeUtils_IMPL +( + MemoryManager *pMemoryManager, + NvBool bFifoLite +) +{ + NV0050_ALLOCATION_PARAMETERS ceUtilsParams = {0}; + + NV_ASSERT_OR_RETURN(pMemoryManager->pCeUtils == NULL, NV_ERR_INVALID_STATE); + + ceUtilsParams.flags = bFifoLite ? DRF_DEF(0050_CEUTILS, _FLAGS, _FIFO_LITE, _TRUE) : 0; + return objCreate(&pMemoryManager->pCeUtils, pMemoryManager, CeUtils, ENG_GET_GPU(pMemoryManager), NULL, &ceUtilsParams); +} + +void +memmgrDestroyCeUtils_IMPL +( + MemoryManager *pMemoryManager +) +{ + objDelete(pMemoryManager->pCeUtils); + pMemoryManager->pCeUtils = NULL; +} diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/kernel/gpu/mem_mgr/mem_mgr_ctrl.c nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/kernel/gpu/mem_mgr/mem_mgr_ctrl.c --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/kernel/gpu/mem_mgr/mem_mgr_ctrl.c 2023-10-25 20:21:11.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/kernel/gpu/mem_mgr/mem_mgr_ctrl.c 2024-03-05 22:13:36.000000000 +0000 @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 1993-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 1993-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -250,6 +250,44 @@ } // +// deviceCtrlCmdSetDefaultVidmemPhysicality +// +// Lock Requirements: +// Assert that API lock held on entry +// +NV_STATUS +deviceCtrlCmdSetDefaultVidmemPhysicality_IMPL +( + Device *pDevice, + NV0080_CTRL_FB_SET_DEFAULT_VIDMEM_PHYSICALITY_PARAMS *pParams +) +{ + LOCK_ASSERT_AND_RETURN(rmapiLockIsOwner()); + NvU32 override; + + switch (pParams->value) + { + case NV0080_CTRL_FB_DEFAULT_VIDMEM_PHYSICALITY_DEFAULT: + override = NVOS32_ATTR_PHYSICALITY_DEFAULT; + break; + case NV0080_CTRL_FB_DEFAULT_VIDMEM_PHYSICALITY_CONTIGUOUS: + override = NVOS32_ATTR_PHYSICALITY_CONTIGUOUS; + break; + case NV0080_CTRL_FB_DEFAULT_VIDMEM_PHYSICALITY_NONCONTIGUOUS: + override = NVOS32_ATTR_PHYSICALITY_NONCONTIGUOUS; + break; + case NV0080_CTRL_FB_DEFAULT_VIDMEM_PHYSICALITY_ALLOW_NONCONTIGUOUS: + override = NVOS32_ATTR_PHYSICALITY_ALLOW_NONCONTIGUOUS; + break; + default: + return NV_ERR_INVALID_ARGUMENT; + } + pDevice->defaultVidmemPhysicalityOverride = override; + + return NV_OK; +} + +// // subdeviceCtrlCmdFbGetBar1Offset // // Lock Requirements: @@ -262,23 +300,14 @@ NV2080_CTRL_FB_GET_BAR1_OFFSET_PARAMS *pFbMemParams ) { - OBJGPU *pGpu = GPU_RES_GET_GPU(pSubdevice); NvHandle hClient = RES_GET_CLIENT_HANDLE(pSubdevice); - Device *pDevice; + NvHandle hDevice = RES_GET_PARENT_HANDLE(pSubdevice); NvU64 offset; RsCpuMapping *pCpuMapping = NULL; - NV_STATUS status; LOCK_ASSERT_AND_RETURN(rmapiLockIsOwner() && rmGpuLockIsOwner()); - // Get the device handle - status = deviceGetByInstance(RES_GET_CLIENT(pSubdevice), - gpuGetDeviceInstance(pGpu), - &pDevice); - if (status != NV_OK) - return NV_ERR_INVALID_ARGUMENT; - - pCpuMapping = CliFindMappingInClient(hClient, RES_GET_HANDLE(pDevice), pFbMemParams->cpuVirtAddress); + pCpuMapping = CliFindMappingInClient(hClient, hDevice, pFbMemParams->cpuVirtAddress); if (pCpuMapping == NULL) return NV_ERR_INVALID_ARGUMENT; @@ -360,8 +389,9 @@ { OBJGPU *pGpu = GPU_RES_GET_GPU(pSubdevice); NvHandle hClient = RES_GET_CLIENT_HANDLE(pSubdevice); + Device *pDevice = GPU_RES_GET_DEVICE(pSubdevice); NvHandle hObject = RES_GET_HANDLE(pSubdevice); - Heap *pHeap = vidmemGetHeap(pGpu, hClient, NV_FALSE); + Heap *pHeap = vidmemGetHeap(pGpu, pDevice, NV_FALSE); HEAP_ALLOC_HINT_PARAMS AllocHint = {0}; NvU32 i; NvU64 _size, _alignment; @@ -803,3 +833,32 @@ return NV_OK; } + +NV_STATUS +subdeviceCtrlCmdGbGetSemaphoreSurfaceLayout_IMPL +( + Subdevice *pSubdevice, + NV2080_CTRL_FB_GET_SEMAPHORE_SURFACE_LAYOUT_PARAMS *pParams +) +{ + MemoryManager *pMemoryManager = GPU_GET_MEMORY_MANAGER(GPU_RES_GET_GPU(pSubdevice)); + + pParams->caps = 0; + + if (pMemoryManager->bMonitoredFenceSupported) + pParams->caps |= NV2080_CTRL_FB_GET_SEMAPHORE_SURFACE_LAYOUT_CAPS_MONITORED_FENCE_SUPPORTED; + + if (pMemoryManager->b64BitSemaphoresSupported) + pParams->caps |= NV2080_CTRL_FB_GET_SEMAPHORE_SURFACE_LAYOUT_CAPS_64BIT_SEMAPHORES_SUPPORTED; + + // + // Assume semaphore values to always be 64-bit for simplicity + // It is not possible to pack the surface better due to alignment requirements, + // so use the static layout here. But keep the offsets interface for flexibility in the future. + // + pParams->monitoredFenceThresholdOffset = 16; // payload + timestamp + pParams->maxSubmittedSemaphoreValueOffset = 24; + pParams->size = 32; + + return NV_OK; +} diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/kernel/gpu/mem_mgr/mem_mgr_gsp_client.c nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/kernel/gpu/mem_mgr/mem_mgr_gsp_client.c --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/kernel/gpu/mem_mgr/mem_mgr_gsp_client.c 2023-10-25 20:21:11.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/kernel/gpu/mem_mgr/mem_mgr_gsp_client.c 2024-03-05 22:13:36.000000000 +0000 @@ -152,6 +152,19 @@ tmpAddr += 0x10000; } + if (gpuIsSelfHosted(pGpu)) + { + // + // Reserve space for the test buffer used in coherent link test + // that is run early when memory allocation is not ready yet. + // + // if Self-Hosted is running in PCIe mode then this space will + // will not be used, this should not cause any issue + // + pKernelBus->coherentLinkTestBufferBase = tmpAddr; + tmpAddr += BUS_COHERENT_LINK_TEST_BUFFER_SIZE; + } + if (KBUS_BAR2_ENABLED(pKernelBus)) { // diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/kernel/gpu/mem_mgr/mem_mgr_pwr_mgmt.c nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/kernel/gpu/mem_mgr/mem_mgr_pwr_mgmt.c --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/kernel/gpu/mem_mgr/mem_mgr_pwr_mgmt.c 2023-10-25 20:21:11.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/kernel/gpu/mem_mgr/mem_mgr_pwr_mgmt.c 2024-03-05 22:13:36.000000000 +0000 @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 1993-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 1993-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -28,6 +28,7 @@ #include "vgpu/rpc.h" #include "os/nv_memory_type.h" #include "gpu/gsp/kernel_gsp.h" +#include "gpu/gsp/gsp_static_config.h" static NV_STATUS _memmgrWalkHeap(OBJGPU *pGpu, MemoryManager *pMemoryManager, OBJFBSR *pFbsr); static NV_STATUS _memmgrAllocFbsrReservedRanges(OBJGPU *pGpu, MemoryManager *pMemoryManager); @@ -43,7 +44,6 @@ ) { NvU32 fbsrStartMode = pMemoryManager->fbsrStartMode; - NvBool bGcOffState = NV_FALSE; NvU32 i; OBJFBSR *pFbsr; NV_STATUS rmStatus = NV_OK; @@ -63,12 +63,14 @@ // might fail is not enough non-paged memory available. // pMemoryManager->pActiveFbsr = NULL; + // // Iterate the heap at top level to avoid inconsistent between // several pFbsr instance. // - rmStatus = memmgrAddMemNodes(pGpu, pMemoryManager, bGcOffState); + rmStatus = memmgrAddMemNodes(pGpu, pMemoryManager, + pGpu->getProperty(pGpu, PDB_PROP_GPU_GCOFF_STATE_ENTERING)); if ((rmStatus == NV_OK) && memmgrIsPmaInitialized(pMemoryManager)) @@ -77,7 +79,7 @@ RANGELISTTYPE *pSaveList = NULL; RANGELISTTYPE *pSaveCurr; - if (bGcOffState) + if (pGpu->getProperty(pGpu, PDB_PROP_GPU_GCOFF_STATE_ENTERING)) { rmStatus = pmaBuildAllocatedBlocksList(&pHeap->pmaObject, &pSaveList); } @@ -112,7 +114,7 @@ } } - if (bGcOffState) + if (pGpu->getProperty(pGpu, PDB_PROP_GPU_GCOFF_STATE_ENTERING)) { pmaFreeAllocatedBlocksList(&pHeap->pmaObject, &pSaveList); } @@ -292,43 +294,28 @@ // Alloc the Memory descriptors for Fbsr Reserved regions, if not allocated. if (pMemoryManager->fbsrReservedRanges[FBSR_RESERVED_INST_MEMORY_BEFORE_BAR2PTE] == NULL) { - if(IS_VIRTUAL_WITH_SRIOV(pGpu)) - { - // Allocate Vid Mem descriptor for RM INSTANCE memory from start to BAR2 PDE base. - size = memdescGetPhysAddr(pKernelBus->virtualBar2[GPU_GFID_PF].pPageLevelsMemDesc, AT_GPU, 0) - pMemoryManager->rsvdMemoryBase; - } - else - { - // Allocate Vid Mem descriptor for RM INSTANCE memory from start to BAR2PTE - size = memdescGetPhysAddr(pKernelBus->virtualBar2[GPU_GFID_PF].pPTEMemDesc, AT_GPU, 0) - pMemoryManager->rsvdMemoryBase; - } - + // Allocate Vid Mem descriptor for RM INSTANCE memory from start to BAR2PTE + size = memdescGetPhysAddr(pKernelBus->virtualBar2[GPU_GFID_PF].pPTEMemDesc, AT_GPU, 0) - pMemoryManager->rsvdMemoryBase; NV_ASSERT_OK_OR_GOTO(status, memdescCreate(&pMemoryManager->fbsrReservedRanges[FBSR_RESERVED_INST_MEMORY_BEFORE_BAR2PTE], pGpu, size, 0, NV_TRUE, ADDR_FBMEM, NV_MEMORY_UNCACHED, MEMDESC_FLAGS_NONE), fail); - // Describe the MemDescriptor for RM Instance Memory from start to BAR2 PDE base. + // Describe the MemDescriptor for RM Instance Memory from start to BAR2PTE memdescDescribe(pMemoryManager->fbsrReservedRanges[FBSR_RESERVED_INST_MEMORY_BEFORE_BAR2PTE], ADDR_FBMEM, pMemoryManager->rsvdMemoryBase, size); } if (pMemoryManager->fbsrReservedRanges[FBSR_RESERVED_INST_MEMORY_AFTER_BAR2PTE] == NULL) { - RmPhysAddr afterBar2PteRegionStart = 0; - NvU64 afterBar2PteRegionSize = 0; - - /* - * Allocate Mem descriptors for AFTER_BAR2PTE, GSP HEAP, WPR, NON WPR and VGA Workspace regions. - */ + // Allocate Mem descriptors for AFTER_BAR2PTE, GSP HEAP, WPR, NON WPR and VGA Workspace regions if (IS_GSP_CLIENT(pGpu)) { KernelGsp *pKernelGsp = GPU_GET_KERNEL_GSP(pGpu); - NvU64 afterBar2PteRegionEnd = 0; - afterBar2PteRegionStart = memdescGetPhysAddr(pKernelBus->virtualBar2[GPU_GFID_PF].pPTEMemDesc, AT_GPU, 0) + + RmPhysAddr afterBar2PteRegionStart = memdescGetPhysAddr(pKernelBus->virtualBar2[GPU_GFID_PF].pPTEMemDesc, AT_GPU, 0) + pKernelBus->virtualBar2[GPU_GFID_PF].pPTEMemDesc->Size; - afterBar2PteRegionEnd = pMemoryManager->rsvdMemoryBase + pMemoryManager->rsvdMemorySize; - afterBar2PteRegionSize = afterBar2PteRegionEnd - afterBar2PteRegionStart; + NvU64 afterBar2PteRegionEnd = pMemoryManager->rsvdMemoryBase + pMemoryManager->rsvdMemorySize; + NvU64 afterBar2PteRegionSize = afterBar2PteRegionEnd - afterBar2PteRegionStart; NvU64 gspHeapRegionStart = afterBar2PteRegionEnd; NvU64 gspHeapRegionSize = pKernelGsp->pWprMeta->gspFwRsvdStart - gspHeapRegionStart; NvU64 gspNonWprRegionSize = pKernelGsp->pWprMeta->gspFwWprStart - pKernelGsp->pWprMeta->gspFwRsvdStart; @@ -377,34 +364,17 @@ // Allocate Vid Mem descriptor for RM INSTANCE memory, specific to VGA i.e. after BAR2PTE to end. else { - NvU64 fbAddrSpaceSize = _memmgrGetFbEndExcludingLostOnSuspendRegions(pGpu, pMemoryManager); - - if (IS_VIRTUAL_WITH_SRIOV(pGpu)) - { - /* - * From BAR2 region we skip BAR2 PDEs and CPU visible region PTEs as we rebuild them on restore. - * But we need to save CPU invisible region PTEs across S/R, hence AFTER_BAR2PTE range starts - * after CPU visible region PTEs ends. - */ - afterBar2PteRegionStart = pKernelBus->bar2[GPU_GFID_PF].pteBase + - pKernelBus->bar2[GPU_GFID_PF].cpuVisiblePgTblSize; - } - else - { - afterBar2PteRegionStart = memdescGetPhysAddr(pKernelBus->virtualBar2[GPU_GFID_PF].pPTEMemDesc, AT_GPU, 0) + - pKernelBus->virtualBar2[GPU_GFID_PF].pPTEMemDesc->Size; - } - - afterBar2PteRegionSize = fbAddrSpaceSize - afterBar2PteRegionStart; + NvU64 fbAddrSpaceSize = _memmgrGetFbEndExcludingLostOnSuspendRegions(pGpu, pMemoryManager); + size = (fbAddrSpaceSize) - memdescGetPhysAddr(pKernelBus->virtualBar2[GPU_GFID_PF].pPTEMemDesc, AT_GPU, 0) - pKernelBus->virtualBar2[GPU_GFID_PF].pPTEMemDesc->Size; NV_ASSERT_OK_OR_GOTO(status, memdescCreate(&pMemoryManager->fbsrReservedRanges[FBSR_RESERVED_INST_MEMORY_AFTER_BAR2PTE], - pGpu, afterBar2PteRegionSize, 0, NV_TRUE, ADDR_FBMEM, + pGpu, size, 0, NV_TRUE, ADDR_FBMEM, NV_MEMORY_UNCACHED, MEMDESC_FLAGS_NONE), fail); memdescDescribe(pMemoryManager->fbsrReservedRanges[FBSR_RESERVED_INST_MEMORY_AFTER_BAR2PTE], ADDR_FBMEM, - afterBar2PteRegionStart, afterBar2PteRegionSize); + memdescGetPhysAddr(pKernelBus->virtualBar2[GPU_GFID_PF].pPTEMemDesc, AT_GPU, 0) + pKernelBus->virtualBar2[GPU_GFID_PF].pPTEMemDesc->Size, size); } } @@ -602,18 +572,59 @@ return rmStatus; } +NvBool +memmgrIsGspOwnedMemory_KERNEL +( + OBJGPU *pGpu, + MemoryManager *pMemoryManager, + MEMORY_DESCRIPTOR *pMemDesc +) +{ + + GspStaticConfigInfo *pGSCI = GPU_GET_GSP_STATIC_INFO(pGpu); + RmPhysAddr physAddr = memdescGetPhysAddr(pMemDesc, AT_GPU, 0); + NvU64 fbRegionSize = 0; + + NV2080_CTRL_CMD_FB_GET_FB_REGION_INFO_PARAMS *pFbRegionInfoParams = &pGSCI->fbRegionInfoParams; + NV2080_CTRL_CMD_FB_GET_FB_REGION_FB_REGION_INFO *pFbRegionInfo = NULL; + + // Return NV_TRUE if input MEMORY_DESCRIPTOR corresponds to any GSP managed regions + for (NvU32 i = 0; i < pFbRegionInfoParams->numFBRegions; i++) + { + pFbRegionInfo = &pFbRegionInfoParams->fbRegion[i]; + fbRegionSize = pFbRegionInfo->limit - pFbRegionInfo->base + 1; + + if ((pFbRegionInfo->base == physAddr) && (fbRegionSize == pMemDesc->Size)) + { + NV_PRINTF(LEVEL_INFO, + "Skipping GSP FB Region with addr 0x%llx and size 0x%llx\n", + physAddr, pMemDesc->Size); + return NV_TRUE; + } + } + + return NV_FALSE; +} + NV_STATUS -memmgrAddMemNodes_IMPL(OBJGPU *pGpu, MemoryManager *pMemoryManager, NvBool bSaveAllRmAllocations) +memmgrAddMemNodes_IMPL +( + OBJGPU *pGpu, + MemoryManager *pMemoryManager, + NvBool bSaveAllRmAllocations +) { NV_STATUS status = NV_OK; - Heap *pHeap = GPU_GET_HEAP(pGpu); + Heap *pHeap = GPU_GET_HEAP(pGpu); MEMORY_DESCRIPTOR *pAllocMemDesc; MEM_BLOCK *block; + NvBool bSaveNode = NV_FALSE; block = pHeap->pBlockList; do { pAllocMemDesc = block->pMemDesc; + bSaveNode = NV_FALSE; // // TODO: Bug 1778161: Let memory descriptor lost on suspend be default, @@ -621,17 +632,34 @@ // content of memory descriptor, remove MEMDESC_FLAGS_LOST_ON_SUSPEND // flag. // - if ((pAllocMemDesc != NULL) && - (((block->owner == HEAP_OWNER_RM_RESERVED_REGION) && - (bSaveAllRmAllocations || - memdescGetFlag(pAllocMemDesc, MEMDESC_FLAGS_PRESERVE_CONTENT_ON_SUSPEND))) || - (((block->owner == HEAP_OWNER_RM_CHANNEL_CTX_BUFFER) || - (block->owner == HEAP_OWNER_RM_KERNEL_CLIENT)) && - (bSaveAllRmAllocations || - (!memdescGetFlag(pAllocMemDesc, MEMDESC_FLAGS_LOST_ON_SUSPEND)))))) + if (pAllocMemDesc != NULL) { - if ((memdescGetAddressSpace(pAllocMemDesc) == ADDR_FBMEM) || - (memdescGetAddressSpace(pAllocMemDesc) == ADDR_SYSMEM)) + // + // Save RM_RESERVED_REGION if it is not GSP managed FB region and + // - bSaveRmAllocations true or + // - MEMDESC_FLAGS_PRESERVE_CONTENT_ON_SUSPEND is set + // TODO: Use LOST_ON_SUSPEND flag to skip GSP managed FB regions + // + if ((block->owner == HEAP_OWNER_RM_RESERVED_REGION) && + !memmgrIsGspOwnedMemory_HAL(pGpu, pMemoryManager, pAllocMemDesc)) + { + if (bSaveAllRmAllocations || memdescGetFlag(pAllocMemDesc, MEMDESC_FLAGS_PRESERVE_CONTENT_ON_SUSPEND)) + bSaveNode = NV_TRUE; + } + // + // Save RM_CHANNEL_CTX_BUFFER or RM_KERNEL_CLIENT regions if + // - bSaveRmAllocations true or + // - MEMDESC_FLAGS_PRESERVE_LOST_ON_SUSPEND is not set + // + else if ((block->owner == HEAP_OWNER_RM_CHANNEL_CTX_BUFFER) || (block->owner == HEAP_OWNER_RM_KERNEL_CLIENT)) + { + if (bSaveAllRmAllocations || (!memdescGetFlag(pAllocMemDesc, MEMDESC_FLAGS_LOST_ON_SUSPEND))) + bSaveNode = NV_TRUE; + } + + if (bSaveNode && + ((memdescGetAddressSpace(pAllocMemDesc) == ADDR_FBMEM) || + (memdescGetAddressSpace(pAllocMemDesc) == ADDR_SYSMEM))) { NV_CHECK_OK_OR_GOTO(status, LEVEL_ERROR, diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/kernel/gpu/mem_mgr/mem_scrub.c nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/kernel/gpu/mem_mgr/mem_scrub.c --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/kernel/gpu/mem_mgr/mem_scrub.c 2023-10-25 20:21:12.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/kernel/gpu/mem_mgr/mem_scrub.c 2024-03-05 22:13:37.000000000 +0000 @@ -33,6 +33,7 @@ #include "gpu/mem_mgr/mem_desc.h" #include "kernel/gpu/intr/intr.h" +#include "gpu/mem_mgr/channel_utils.h" #include "gpu/mem_mgr/mem_scrub.h" #include "os/os.h" #include "gpu/mem_mgr/phys_mem_allocator/phys_mem_allocator.h" @@ -44,6 +45,10 @@ #include "nvstatus.h" #include "rmapi/rs_utils.h" #include "core/locks.h" + +#include "gpu/conf_compute/conf_compute.h" + +#include "class/cl0050.h" #include "class/clb0b5.h" // MAXWELL_DMA_COPY_A #include "class/clc0b5.h" // PASCAL_DMA_COPY_A #include "class/clc1b5.h" // PASCAL_DMA_COPY_B @@ -57,20 +62,20 @@ #include "class/clc86f.h" // HOPPER_CHANNEL_GPFIFO_A static NvU64 _scrubCheckProgress(OBJMEMSCRUB *pScrubber); -static void _scrubSetupChannelBufferSizes(OBJCHANNEL *pChannel, NvU32 numCopyBlocks); static NvU64 _searchScrubList(OBJMEMSCRUB *pScrubber, RmPhysAddr base, NvU64 size); static void _waitForPayload(OBJMEMSCRUB *pScrubber, RmPhysAddr base, RmPhysAddr end); static void _scrubAddWorkToList(OBJMEMSCRUB *pScrubber, RmPhysAddr base, NvU64 size, NvU64 newId); -static NvU32 _scrubMemory(OBJCHANNEL *pChannel, RmPhysAddr base, NvU64 size, NV_ADDRESS_SPACE dstAddrSpace, +static NvU32 _scrubMemory(OBJMEMSCRUB *pScrubber, RmPhysAddr base, NvU64 size, NvU32 dstCpuCacheAttrib, NvU32 freeToken); static void _scrubWaitAndSave(OBJMEMSCRUB *pScrubber, PSCRUB_NODE pList, NvLength itemsToSave); static NvU64 _scrubGetFreeEntries(OBJMEMSCRUB *pScrubber); -static NvU64 _scrubCheckAndSubmit(OBJMEMSCRUB *pScrubber, NvU64 chunkSize, NvU64 *pPages, - NvU64 pageCount, PSCRUB_NODE pList, NvLength pagesToScrubCheck); -static void _scrubOsSchedule(OBJCHANNEL *pChannel); +static NvU64 _scrubCheckAndSubmit(OBJMEMSCRUB *pScrubber, NvU64 pageCount, PSCRUB_NODE pList, + PSCRUB_NODE pScrubListCopy, NvLength pagesToScrubCheck); static void _scrubCopyListItems(OBJMEMSCRUB *pScrubber, PSCRUB_NODE pList, NvLength itemsToSave); static NV_STATUS _scrubCheckLocked(OBJMEMSCRUB *pScrubber, PSCRUB_NODE *ppList, NvU64 *pSize); +static NV_STATUS _scrubCombinePages(NvU64 *pPages, NvU64 pageSize, NvU64 pageCount, + PSCRUB_NODE *ppScrubList, NvU64 *pSize); /** * Constructs the memory scrubber object and signals @@ -90,14 +95,12 @@ ) { OBJMEMSCRUB *pScrubber; - OBJCHANNEL *pChannel; - KernelMIGManager *pKernelMIGManager = GPU_GET_KERNEL_MIG_MANAGER(pGpu); - MemoryManager *pMemoryManager = GPU_GET_MEMORY_MANAGER(pGpu); - NV_STATUS status = NV_OK; - PMA *pPma = NULL; - RM_API *pRmApi = rmapiGetInterface(RMAPI_GPU_LOCK_INTERNAL); - NvBool bMIGInUse = IS_MIG_IN_USE(pGpu); - RmClient *pClient; + MemoryManager *pMemoryManager = GPU_GET_MEMORY_MANAGER(pGpu); + KernelMIGManager *pKernelMIGManager = GPU_GET_KERNEL_MIG_MANAGER(pGpu); + NV_STATUS status = NV_OK; + NvBool bMIGInUse = IS_MIG_IN_USE(pGpu); + PMA *pPma = NULL; + KERNEL_MIG_GPU_INSTANCE *pKernelMIGGPUInstance = NULL; if (pHeap == NULL) { @@ -135,129 +138,50 @@ } portMemSet(pScrubber->pScrubList, 0, sizeof(SCRUB_NODE) * MAX_SCRUB_ITEMS); + pScrubber->pGpu = pGpu; + { - pChannel = (OBJCHANNEL *) portMemAllocNonPaged(sizeof(OBJCHANNEL)); - if (pChannel == NULL) - { - status = NV_ERR_INSUFFICIENT_RESOURCES; - goto destroyscrublist; - } - portMemSet(pChannel, 0, sizeof(OBJCHANNEL)); - pScrubber->pChannel = pChannel; - pChannel->type = SCRUBBER_CHANNEL; - pChannel->pGpu = pGpu; - pChannel->bUseVasForCeCopy = memmgrUseVasForCeMemoryOps(pMemoryManager); - memmgrMemUtilsGetCopyEngineClass_HAL(pGpu, pMemoryManager, &pChannel->hTdCopyClass); + NV_PRINTF(LEVEL_INFO, "Starting to init CeUtils for scrubber.\n"); + NV0050_ALLOCATION_PARAMETERS ceUtilsAllocParams = {0}; - if (((pChannel->hTdCopyClass == HOPPER_DMA_COPY_A) - ) && !pChannel->bUseVasForCeCopy) + if (memmgrUseVasForCeMemoryOps(pMemoryManager)) { - pChannel->type = FAST_SCRUBBER_CHANNEL; + ceUtilsAllocParams.flags = DRF_DEF(0050, _CEUTILS_FLAGS, _VIRTUAL_MODE, _TRUE); } - NV_ASSERT_OK_OR_GOTO(status, - pRmApi->AllocWithHandle(pRmApi, NV01_NULL_OBJECT, NV01_NULL_OBJECT, - NV01_NULL_OBJECT, NV01_ROOT, &pChannel->hClient), freeChannelObject); - - pChannel->bClientAllocated = NV_TRUE; - if (bMIGInUse) { - KERNEL_MIG_GPU_INSTANCE *pKernelMIGGPUInstance; - FOR_EACH_VALID_GPU_INSTANCE(pGpu, pKernelMIGManager, pKernelMIGGPUInstance) + KERNEL_MIG_GPU_INSTANCE *pCurrKernelMIGGPUInstance; + + FOR_EACH_VALID_GPU_INSTANCE(pGpu, pKernelMIGManager, pCurrKernelMIGGPUInstance) { - if (pKernelMIGGPUInstance->pMemoryPartitionHeap == pHeap) + if (pCurrKernelMIGGPUInstance->pMemoryPartitionHeap == pHeap) { - pChannel->pKernelMIGGpuInstance = pKernelMIGGPUInstance; + pKernelMIGGPUInstance = pCurrKernelMIGGPUInstance; break; } } FOR_EACH_VALID_GPU_INSTANCE_END(); } - - // set all the unique ID's for the scrubber channel - NV_ASSERT_OK_OR_GOTO(status, - serverutilGetClientUnderLock(pChannel->hClient, &pClient), freechannel); - - NV_ASSERT_OK_OR_GOTO(status, - serverGetClientUnderLock(&g_resServ, pChannel->hClient, &pChannel->pRsClient), freechannel); - - NV_ASSERT_OK_OR_GOTO(status, - clientSetHandleGenerator(staticCast(pClient, RsClient), 1U, ~0U - 1U), freechannel); - - // set all the unique ID's for the scrubber channel - NV_ASSERT_OK_OR_GOTO(status, - serverutilGenResourceHandle(pChannel->hClient, &pChannel->physMemId), freechannel); - - NV_ASSERT_OK_OR_GOTO(status, - serverutilGenResourceHandle(pChannel->hClient, &pChannel->channelId), freechannel); - - NV_ASSERT_OK_OR_GOTO(status, - serverutilGenResourceHandle(pChannel->hClient, &pChannel->errNotifierIdVirt), freechannel); - - NV_ASSERT_OK_OR_GOTO(status, - serverutilGenResourceHandle(pChannel->hClient, &pChannel->errNotifierIdPhys), freechannel); - - NV_ASSERT_OK_OR_GOTO(status, - serverutilGenResourceHandle(pChannel->hClient, &pChannel->copyObjectId), freechannel); - - NV_ASSERT_OK_OR_GOTO(status, - serverutilGenResourceHandle(pChannel->hClient, &pChannel->eventId), freechannel); - - NV_ASSERT_OK_OR_GOTO(status, - serverutilGenResourceHandle(pChannel->hClient, &pChannel->pushBufferId), freechannel); - - NV_ASSERT_OK_OR_GOTO(status, - serverutilGenResourceHandle(pChannel->hClient, &pChannel->doorbellRegionHandle), freechannel); - - NV_ASSERT_OK_OR_GOTO(status, - serverutilGenResourceHandle(pChannel->hClient, &pChannel->hUserD), freechannel); - - // - // RM scrubber channel is always created as privileged channels (physical address access) by default - // For MMU Bug: 2739505, we need to switch to use channels in non-privileged mode. - // We also need a (split) VAS for GSP-RM + MIG, to ensure we don't fall back to the device default - // VAS during channel allocation. - // - // TODO: This is temporary, and should be replaced shortly by enabling VAS allocation unilaterally. - // - if (pChannel->bUseVasForCeCopy || - (IS_GSP_CLIENT(pGpu) && bMIGInUse)) + ConfidentialCompute *pConfCompute = GPU_GET_CONF_COMPUTE(pGpu); + if ((pConfCompute != NULL) && + (pConfCompute->getProperty(pCC, PDB_PROP_CONFCOMPUTE_CC_FEATURE_ENABLED))) + { + NV_ASSERT_OK_OR_GOTO(status, objCreate(&pScrubber->pSec2Utils, pHeap, Sec2Utils, pGpu, pKernelMIGGPUInstance), + destroyscrublist); + pScrubber->engineType = NV2080_ENGINE_TYPE_SEC2; + } + else { - NV_ASSERT_OK_OR_GOTO(status, - serverutilGenResourceHandle(pChannel->hClient, &pChannel->hVASpaceId), freechannel); + NV_ASSERT_OK_OR_GOTO(status, objCreate(&pScrubber->pCeUtils, pHeap, CeUtils, pGpu, pKernelMIGGPUInstance, &ceUtilsAllocParams), + destroyscrublist); + pScrubber->engineType = NV2080_ENGINE_TYPE_COPY2; } - - // set sizes for CE Channel - _scrubSetupChannelBufferSizes(pChannel, MAX_SCRUB_ITEMS); - - // Allocate Scrubber Channel related objects - NV_ASSERT_OK_OR_GOTO(status, - memmgrMemUtilsChannelInitialize_HAL(pGpu, pMemoryManager, pChannel), freechannel); - - NV_ASSERT_OK_OR_GOTO(status, - memmgrMemUtilsCopyEngineInitialize_HAL(pGpu, pMemoryManager, pChannel), freepartitionref); - - // Initialize semaphore location to 0 - WRITE_SCRUBBER_PB_SEMA(pChannel, 0); - WRITE_SCRUBBER_PAYLOAD_SEMA(pChannel, 0); - NV_ASSERT_OK_OR_GOTO(status, pmaRegMemScrub(pPma, pScrubber), freepartitionref); + NV_ASSERT_OK_OR_GOTO(status, pmaRegMemScrub(pPma, pScrubber), destroyscrublist); } return status; -freepartitionref: - if(bMIGInUse) - pRmApi->Free(pRmApi, pChannel->hClient, pChannel->hPartitionRef); - -freechannel: - pRmApi->Free(pRmApi, pChannel->hClient, pChannel->channelId); - pRmApi->Free(pRmApi, pChannel->hClient, pChannel->hClient); - -freeChannelObject: - pRmApi->Free(pRmApi, pChannel->hClient, pChannel->hClient); - portMemFree(pScrubber->pChannel); - destroyscrublist: portMemFree(pScrubber->pScrubList); @@ -287,7 +211,17 @@ } else { - if (pScrubber->pChannel->lastSubmittedEntry != READ_SCRUBBER_PB_SEMA(pScrubber->pChannel)) + NvU64 lastCompleted; + if (pScrubber->engineType == NV2080_ENGINE_TYPE_SEC2) + { + lastCompleted = sec2utilsUpdateProgress(pScrubber->pSec2Utils); + } + else + { + lastCompleted = ceutilsUpdateProgress(pScrubber->pCeUtils); + } + + if (pScrubber->lastSubmittedWorkId != lastCompleted) workPending = NV_TRUE; } return workPending; @@ -311,9 +245,7 @@ OBJMEMSCRUB *pScrubber ) { - OBJCHANNEL *pChannel = NULL; PMA *pPma = NULL; - RM_API *pRmApi = rmapiGetInterface(RMAPI_GPU_LOCK_INTERNAL); PSCRUB_NODE pPmaScrubList = NULL; NvU64 count = 0; NV_STATUS status = NV_OK; @@ -330,8 +262,6 @@ pmaUnregMemScrub(pPma); portSyncMutexAcquire(pScrubber->pScrubberMutex); - pChannel = pScrubber->pChannel; - if (!API_GPU_IN_RESET_SANITY_CHECK(pGpu)) { RMTIMEOUT timeout; @@ -365,45 +295,14 @@ portMemFree(pScrubber->pScrubList); { - // Freeing channel first as in MODS case we don't wait for work to complete. Freeing VAS first causes MMU faults - pRmApi->Free(pRmApi, pChannel->hClient, pChannel->channelId); - - if (pChannel->bClientUserd) + if (pScrubber->engineType == NV2080_ENGINE_TYPE_SEC2) { - // scrub userd memory of scrubber channel as it may be allocated from PMA - NvU32 userdSize = 0; - - kfifoGetUserdSizeAlign_HAL(GPU_GET_KERNEL_FIFO(pGpu), &userdSize, NULL); - portMemSet((void*)pChannel->pControlGPFifo, 0, userdSize); - pRmApi->Free(pRmApi, pChannel->hClient, pChannel->hUserD); + objDelete(pScrubber->pSec2Utils); } - - if (pChannel->bUseVasForCeCopy) + else { - // unmap the Identity mapping - status = pRmApi->Unmap(pRmApi, pChannel->hClient, pChannel->deviceId, - pChannel->hFbAliasVA, pChannel->hFbAlias, 0, pChannel->fbAliasVA); - - if (status != NV_OK) - { - NV_PRINTF(LEVEL_ERROR, "Unmapping scrubber 1:1 Mapping, status: %x\n", status); - } - - // free the Alias memory in host - // this will not trigger scrubber - pRmApi->Free(pRmApi, pChannel->hClient, pChannel->hFbAliasVA); - pRmApi->Free(pRmApi, pChannel->hClient, pChannel->hFbAlias); + objDelete(pScrubber->pCeUtils); } - - pRmApi->Free(pRmApi, pChannel->hClient, pChannel->errNotifierIdPhys); - pRmApi->Free(pRmApi, pChannel->hClient, pChannel->pushBufferId); - pRmApi->Free(pRmApi, pChannel->hClient, pChannel->errNotifierIdVirt); - if (pChannel->hVASpaceId) - pRmApi->Free(pRmApi, pChannel->hClient, pChannel->hVASpaceId); - - - pRmApi->Free(pRmApi, pChannel->hClient, pChannel->hClient); - portMemFree(pScrubber->pChannel); } portSyncMutexRelease(pScrubber->pScrubberMutex); @@ -506,63 +405,78 @@ { NvU64 curPagesSaved = 0; PSCRUB_NODE pScrubList = NULL; + PSCRUB_NODE pScrubListCopy = NULL; + NvU64 scrubListSize = 0; NvLength pagesToScrubCheck = 0; NvU64 totalSubmitted = 0; NvU64 numFinished = 0; NvU64 freeEntriesInList = 0; NvU64 scrubCount = 0; - NvU64 numPagesToScrub = pageCount; + NvU64 numPagesToScrub = 0; NV_STATUS status = NV_OK; portSyncMutexAcquire(pScrubber->pScrubberMutex); *pSize = 0; *ppList = pScrubList; - NV_PRINTF(LEVEL_INFO, "submitting pages, pageCount:%llx\n", pageCount); + NV_CHECK_OR_GOTO(LEVEL_INFO, pageCount > 0, cleanup); + + NV_PRINTF(LEVEL_INFO, "submitting pages, pageCount = 0x%llx chunkSize = 0x%llx\n", pageCount, chunkSize); freeEntriesInList = _scrubGetFreeEntries(pScrubber); - if (freeEntriesInList < pageCount) + + NV_ASSERT_OK_OR_GOTO(status, + _scrubCombinePages(pPages, + chunkSize, + pageCount, + &pScrubList, + &scrubListSize), + cleanup); + + numPagesToScrub = scrubListSize; + + if (freeEntriesInList < scrubListSize) { - pScrubList = (PSCRUB_NODE) - portMemAllocNonPaged((NvLength)(sizeof(SCRUB_NODE) * (pageCount - freeEntriesInList))); - - if (pScrubList == NULL) + pScrubListCopy = (PSCRUB_NODE) + portMemAllocNonPaged((NvLength)(sizeof(SCRUB_NODE) * (scrubListSize - freeEntriesInList))); + + if (pScrubListCopy == NULL) { status = NV_ERR_NO_MEMORY; goto cleanup; } - - while (freeEntriesInList < pageCount) + + while (freeEntriesInList < scrubListSize) { - if (pageCount > MAX_SCRUB_ITEMS) + if (scrubListSize > MAX_SCRUB_ITEMS) { pagesToScrubCheck = (NvLength)(MAX_SCRUB_ITEMS - freeEntriesInList); scrubCount = MAX_SCRUB_ITEMS; } else { - pagesToScrubCheck = (NvLength)(pageCount - freeEntriesInList); - scrubCount = pageCount; + pagesToScrubCheck = (NvLength)(scrubListSize - freeEntriesInList); + scrubCount = scrubListSize; } - numFinished = _scrubCheckAndSubmit(pScrubber, chunkSize, &pPages[totalSubmitted], - scrubCount, &pScrubList[curPagesSaved], + numFinished = _scrubCheckAndSubmit(pScrubber, scrubCount, + &pScrubList[totalSubmitted], + &pScrubListCopy[curPagesSaved], pagesToScrubCheck); - pageCount -= numFinished; + scrubListSize -= numFinished; curPagesSaved += pagesToScrubCheck; totalSubmitted += numFinished; freeEntriesInList = _scrubGetFreeEntries(pScrubber); } - *ppList = pScrubList; + *ppList = pScrubListCopy; *pSize = curPagesSaved; } else { - totalSubmitted = _scrubCheckAndSubmit(pScrubber, chunkSize, pPages, - pageCount, NULL, - 0); + totalSubmitted = _scrubCheckAndSubmit(pScrubber, scrubListSize, + pScrubList, NULL, 0); *ppList = NULL; *pSize = 0; } @@ -570,6 +484,12 @@ cleanup: portSyncMutexRelease(pScrubber->pScrubberMutex); + if (pScrubList != NULL) + { + portMemFree(pScrubList); + pScrubList = NULL; + } + NV_CHECK_OK_OR_RETURN(LEVEL_INFO, status); if (totalSubmitted == numPagesToScrub) @@ -610,15 +530,33 @@ ) { - NvU32 iter = 0; - NV_STATUS status = NV_OK; + NvU32 iter = 0; + NV_STATUS status = NV_OK; + PSCRUB_NODE pScrubList = NULL; + NvU64 scrubListSize = 0; + + NV_ASSERT_OK_OR_RETURN(_scrubCombinePages(pPages, + chunkSize, + pageCount, + &pScrubList, + &scrubListSize)); portSyncMutexAcquire(pScrubber->pScrubberMutex); - for (iter = 0; iter < pageCount; iter++) + + for (iter = 0; iter < scrubListSize; iter++) { - _waitForPayload(pScrubber, pPages[iter], (pPages[iter] + chunkSize - 1)); + _waitForPayload(pScrubber, + pScrubList[iter].base, + (pScrubList[iter].base + pScrubList[iter].size - 1)); } portSyncMutexRelease(pScrubber->pScrubberMutex); + + if (pScrubList != NULL) + { + portMemFree(pScrubList); + pScrubList = NULL; + } + return status; } @@ -747,58 +685,55 @@ /* This function is used to check and submit work items always within the * available / maximum scrub list size. * - * @param[in] pScrubber OBJMEMSCRUB pointer - * @param[in] chunkSize size of each page - * @param[in] pPages Array of base address - * @param[in] pageCount number of pages in the array - * @param[in] pList pointer will store the return check array + * @param[in] pScrubber OBJMEMSCRUB pointer + * @param[in] pageCount number of pages in the array + * @param[in] pList pointer will store the return check array + * @param[in] pScrubListCopy List where pages are saved + * @param[in] pagesToScrubCheck How many pages will need to be saved * @returns the number of work successfully submitted, else 0 */ static NvU64 _scrubCheckAndSubmit ( OBJMEMSCRUB *pScrubber, - NvU64 chunkSize, - NvU64 *pPages, NvU64 pageCount, PSCRUB_NODE pList, + PSCRUB_NODE pScrubListCopy, NvLength pagesToScrubCheck ) { - NvU64 iter = 0; - NvU64 newId; - OBJCHANNEL *pChannel; - NV_STATUS status; + NvU64 iter = 0; + NvU64 newId; + NV_STATUS status; - if (pList == NULL && pagesToScrubCheck != 0) + if (pScrubListCopy == NULL && pagesToScrubCheck != 0) { NV_PRINTF(LEVEL_ERROR, "pages need to be saved off, but stash list is invalid\n"); goto exit; } - _scrubWaitAndSave(pScrubber, pList, pagesToScrubCheck); + _scrubWaitAndSave(pScrubber, pScrubListCopy, pagesToScrubCheck); for (iter = 0; iter < pageCount; iter++) { - pChannel = pScrubber->pChannel; newId = pScrubber->lastSubmittedWorkId + 1; NV_PRINTF(LEVEL_INFO, "Submitting work, Id: %llx, base: %llx, size: %llx\n", - newId, pPages[iter], chunkSize); + newId, pList[iter].base, pList[iter].size); { - status = _scrubMemory(pChannel, pPages[iter], chunkSize, ADDR_FBMEM, NV_MEMORY_DEFAULT, + status =_scrubMemory(pScrubber, pList[iter].base, pList[iter].size, NV_MEMORY_DEFAULT, (NvU32)newId); } if(status != NV_OK) { - NV_PRINTF(LEVEL_ERROR, "Failing because the work dint submit.\n"); + NV_PRINTF(LEVEL_ERROR, "Failing because the work didn't submit.\n"); goto exit; } - _scrubAddWorkToList(pScrubber, pPages[iter], chunkSize, newId); + _scrubAddWorkToList(pScrubber, pList[iter].base, pList[iter].size, newId); _scrubCheckProgress(pScrubber); } @@ -886,41 +821,18 @@ while (currentCompletedId < (pScrubber->lastSeenIdByClient + itemsToSave)) { - _scrubOsSchedule(pScrubber->pChannel); + { + if (pScrubber->engineType == NV2080_ENGINE_TYPE_SEC2) + sec2utilsServiceInterrupts(pScrubber->pSec2Utils); + else + ceutilsServiceInterrupts(pScrubber->pCeUtils); + } currentCompletedId = _scrubCheckProgress(pScrubber); } _scrubCopyListItems(pScrubber, pList, itemsToSave); } -/** - * helper function to yield when we wait for the scrubber to complete a work - */ -static void -_scrubOsSchedule(OBJCHANNEL *pChannel) -{ - // - // FIXME: Bug 2463959: objmemscrub is called with the rmDeviceGpuLock in the - // heapFree_IMPL->_stdmemPmaFree->pmaFreePages->scrubSubmitPages path. - // Yielding while holding the rmDeviceGpuLock can lead to deadlock. Instead, - // if the lock is held, service any interrupts on the owned CE to make progress. - // Bug 2527660 is filed to remove this change. - // - // pChannel is null when PMA scrub requests are handled in vGPU plugin. - // In this case vGpu plugin allocates scrubber channel in PF domain so - // above mention deadlock is not present here. - // - if ((pChannel != NULL) && (rmDeviceGpuLockIsOwner(pChannel->pGpu->gpuInstance))) - { - Intr *pIntr = GPU_GET_INTR(pChannel->pGpu); - intrServiceStallSingle_HAL(pChannel->pGpu, pIntr, MC_ENGINE_IDX_CE(pChannel->pKCe->publicID), NV_FALSE); - } - else - { - osSchedule(); - } - -} /** * helper function to find and wait for a specific work to complete @@ -979,76 +891,7 @@ NV_ASSERT(_scrubGetFreeEntries(pScrubber) <= MAX_SCRUB_ITEMS); } -/** helper function to return methods size needed for a single operation in a - channel. currently only scrubber channel is supported. - */ -static NvU32 -_getOptimalMethodSizePerBlock -( - OBJCHANNEL *pChannel -) -{ - NvU32 methodSizePerBlock = 0; - switch(pChannel->type) - { - case SCRUBBER_CHANNEL: - { - // - // 6 1U methods -- 6 * 8 bytes = 48 bytes - // 1 2U methods -- 1 * 12 bytes = 12 bytes - // 1 3U methods -- 1 * 16 bytes = 16 bytes - // 1 4U methods -- 1 * 20 bytes = 20 bytes - // - methodSizePerBlock = SIZE_OF_ONE_MEMSET_BLOCK; // 0x60 - break; - } - case FAST_SCRUBBER_CHANNEL: - { - // - // 9 1U methods -- 9 * 8 bytes = 72 bytes - // 1 2U methods -- 1 * 12 bytes = 12 bytes - // 1 3U methods -- 1 * 16 bytes = 16 bytes - // 1 4U methods -- 1 * 20 bytes = 20 bytes - // - methodSizePerBlock = SIZE_OF_ONE_MEMSET_BLOCK + 24; // 0x78 - break; - } - // TODO: add the case for COPY CHANNEL. - default: - NV_ASSERT(NV_TRUE); - } - return methodSizePerBlock; -} - -/** - * helper function to set sizes for CE channel used by memory scrubber. - * Channel PB, GPFIFO and channel offsets are set for the numCopyBlock size - */ - -static void -_scrubSetupChannelBufferSizes -( - OBJCHANNEL *pChannel, - NvU32 numCopyBlocks -) -{ - NV_ASSERT(numCopyBlocks != 0); - NvU32 gpFifoSize = NV906F_GP_ENTRY__SIZE * numCopyBlocks; - - // set channel specific sizes - pChannel->methodSizePerBlock = _getOptimalMethodSizePerBlock(pChannel); - NV_ASSERT(pChannel->methodSizePerBlock != 0); - pChannel->channelPbSize = numCopyBlocks * (pChannel->methodSizePerBlock); - NV_ASSERT(pChannel->channelPbSize <= NV_U32_MAX); - pChannel->channelNotifierSize = SCRUBBER_CHANNEL_NOTIFIER_SIZE; - pChannel->channelNumGpFifioEntries = numCopyBlocks; - pChannel->channelSize = pChannel->channelPbSize + gpFifoSize + SCRUBBER_CHANNEL_SEMAPHORE_SIZE; - // Semaphore used to track PB and GPFIFO offset - pChannel->semaOffset = pChannel->channelPbSize + gpFifoSize; - // Semaphore used in work tracking for clients. - pChannel->finishPayloadOffset = pChannel->semaOffset + 4; -} /** * Scrubber uses 64 bit index to track the work submitted. But HW supports @@ -1063,480 +906,125 @@ OBJMEMSCRUB *pScrubber ) { - NvU32 hwCurrentCompletedId; - NvU64 lastSWSemaphoreDone; - OBJCHANNEL *pChannel; + NvU32 hwCurrentCompletedId; + NvU64 lastSWSemaphoreDone; NV_ASSERT(pScrubber != NULL); if (pScrubber->bVgpuScrubberEnabled) { hwCurrentCompletedId = pScrubber->vgpuScrubBuffRing.pScrubBuffRingHeader->lastSWSemaphoreDone; - } else - { - NV_ASSERT(pScrubber->pChannel != NULL); - pChannel = pScrubber->pChannel; - hwCurrentCompletedId = READ_SCRUBBER_PAYLOAD_SEMA(pChannel); - } - lastSWSemaphoreDone = pScrubber->lastSWSemaphoreDone; - - if (hwCurrentCompletedId == (NvU32)lastSWSemaphoreDone) - return lastSWSemaphoreDone; - - // check for wrap around case. Increment the upper 32 bits - if (hwCurrentCompletedId < (NvU32)lastSWSemaphoreDone) - { - lastSWSemaphoreDone += 0x100000000ULL; - } - - // update lower 32 bits - lastSWSemaphoreDone &= 0xFFFFFFFF00000000ULL; - lastSWSemaphoreDone |= (NvU64)hwCurrentCompletedId; + lastSWSemaphoreDone = pScrubber->lastSWSemaphoreDone; - pScrubber->lastSWSemaphoreDone = lastSWSemaphoreDone; + if (hwCurrentCompletedId == (NvU32)lastSWSemaphoreDone) + return lastSWSemaphoreDone; - return lastSWSemaphoreDone; -} - -/** helper function to push destination memory methods - */ -static NvU32 -_memsetPushDstProperties -( - OBJCHANNEL *pChannel, - NV_ADDRESS_SPACE dstAddressSpace, - NvU32 dstCpuCacheAttrib, - NvU32 **ppPtr -) -{ - NvU32 data = 0; - NvU32 *pPtr = *ppPtr; - NvU32 retVal = 0; - - if (dstAddressSpace == ADDR_FBMEM) - data = DRF_DEF(B0B5, _SET_DST_PHYS_MODE, _TARGET, _LOCAL_FB); - else if (dstCpuCacheAttrib == NV_MEMORY_CACHED) - data = DRF_DEF(B0B5, _SET_DST_PHYS_MODE, _TARGET, _COHERENT_SYSMEM); - else if (dstCpuCacheAttrib == NV_MEMORY_UNCACHED) - data = DRF_DEF(B0B5, _SET_DST_PHYS_MODE, _TARGET, _NONCOHERENT_SYSMEM); + // check for wrap around case. Increment the upper 32 bits + if (hwCurrentCompletedId < (NvU32)lastSWSemaphoreDone) + { + lastSWSemaphoreDone += 0x100000000ULL; + } - NV_PUSH_INC_1U(RM_SUBCHANNEL, NVB0B5_SET_DST_PHYS_MODE, data); + // update lower 32 bits + lastSWSemaphoreDone &= 0xFFFFFFFF00000000ULL; + lastSWSemaphoreDone |= (NvU64)hwCurrentCompletedId; - if (pChannel->bUseVasForCeCopy) - { - retVal = DRF_DEF(B0B5, _LAUNCH_DMA, _DST_TYPE, _VIRTUAL) | - DRF_DEF(B0B5, _LAUNCH_DMA, _SRC_TYPE, _VIRTUAL); } else { - retVal = DRF_DEF(B0B5, _LAUNCH_DMA, _DST_TYPE, _PHYSICAL) | - DRF_DEF(B0B5, _LAUNCH_DMA, _SRC_TYPE, _PHYSICAL); + if (pScrubber->engineType == NV2080_ENGINE_TYPE_SEC2) + lastSWSemaphoreDone = sec2utilsUpdateProgress(pScrubber->pSec2Utils); + else + lastSWSemaphoreDone = ceutilsUpdateProgress(pScrubber->pCeUtils); } - *ppPtr = pPtr; - return retVal; + pScrubber->lastSWSemaphoreDone = lastSWSemaphoreDone; + + return lastSWSemaphoreDone; } -/** single helper function to fill the push buffer with the methods needed for - memsetting using CE. This function is much more efficient in the sense it - decouples the mem(set/copy) operation from managing channel resources. - TODO: Add support for memcopy here based on channel type. +/** Single function to memset a surface mapped by GPU. This interface supports + both sysmem and vidmem surface, since it uses CE to memset a surface. + The user is notified by releasing semaphore with value "payload" */ -static NvU32 -_scrubFillPb +static NV_STATUS +_scrubMemory ( - OBJCHANNEL *pChannel, - RmPhysAddr base, - NvU32 size, - NvU32 payload, - NvBool bPipelined, - NV_ADDRESS_SPACE dstAddressSpace, - NvU32 dstCpuCacheAttrib, - NvBool bInsertFinishpayload, - NvBool bNonStallInterrupt, - NvU32 putIndex + OBJMEMSCRUB *pScrubber, + RmPhysAddr base, + NvU64 size, + NvU32 dstCpuCacheAttrib, + NvU32 payload ) { - NvU32 launchDestType = 0; - NvU32 semaValue = 0; - NvU32 pipelinedValue = 0; - NvU32 *pPtr =(NvU32 *)((NvU8*)pChannel->pbCpuVA + (putIndex * pChannel->methodSizePerBlock)); - NvU32 *pStartPtr = pPtr; - NvU32 data = 0; - NvU64 pSemaAddr = 0; - NvU32 disablePlcKind = 0; - - NV_PRINTF(LEVEL_INFO, "PutIndex: %x, PbOffset: %x\n", putIndex, - putIndex * pChannel->methodSizePerBlock); - - // SET OBJECT - NV_PUSH_INC_1U(RM_SUBCHANNEL, NV906F_SET_OBJECT, pChannel->classEngineID); - // Set Pattern for Memset - NV_PUSH_INC_1U(RM_SUBCHANNEL, NVB0B5_SET_REMAP_CONST_A, MEMSET_PATTERN); - // Set Component Size to 1 - NV_PUSH_INC_1U(RM_SUBCHANNEL, NVB0B5_SET_REMAP_COMPONENTS, - DRF_DEF(B0B5, _SET_REMAP_COMPONENTS, _DST_X, _CONST_A) | - DRF_DEF(B0B5, _SET_REMAP_COMPONENTS, _COMPONENT_SIZE, _ONE) | - DRF_DEF(B0B5, _SET_REMAP_COMPONENTS, _NUM_DST_COMPONENTS, _ONE)); - - launchDestType = _memsetPushDstProperties - (pChannel, dstAddressSpace, dstCpuCacheAttrib, &pPtr); - - semaValue = (bInsertFinishpayload) ? - DRF_DEF(B0B5, _LAUNCH_DMA, _SEMAPHORE_TYPE, _RELEASE_ONE_WORD_SEMAPHORE) : 0; - - if (bPipelined) - pipelinedValue = DRF_DEF(B0B5, _LAUNCH_DMA, _DATA_TRANSFER_TYPE, _PIPELINED); - else - pipelinedValue = DRF_DEF(B0B5, _LAUNCH_DMA, _DATA_TRANSFER_TYPE, _NON_PIPELINED); - - if (pChannel->bUseVasForCeCopy) - { - base = base + pChannel->fbAliasVA - pChannel->startFbOffset; - } - - NV_PUSH_INC_2U(RM_SUBCHANNEL, NVB0B5_OFFSET_OUT_UPPER, - DRF_NUM(B0B5, _OFFSET_OUT_UPPER, _UPPER, NvU64_HI32(base)), - NVB0B5_OFFSET_OUT_LOWER, - DRF_NUM(B0B5, _OFFSET_OUT_LOWER, _VALUE,NvU64_LO32(base))); + NV_STATUS status = NV_OK; + MEMORY_DESCRIPTOR *pMemDesc = NULL; + NV_ASSERT_OK_OR_RETURN(memdescCreate(&pMemDesc, pScrubber->pGpu, size, 0, NV_TRUE, + ADDR_FBMEM, dstCpuCacheAttrib, MEMDESC_FLAGS_NONE)); - NV_PUSH_INC_1U(RM_SUBCHANNEL, NVB0B5_LINE_LENGTH_IN, size); + memdescDescribe(pMemDesc, ADDR_FBMEM, base, size); - if (semaValue) + if (pScrubber->engineType == NV2080_ENGINE_TYPE_SEC2) { - NV_PUSH_INC_3U(RM_SUBCHANNEL, NVB0B5_SET_SEMAPHORE_A, - DRF_NUM(B0B5, _SET_SEMAPHORE_A, _UPPER, NvU64_HI32(pChannel->pbGpuVA+pChannel->finishPayloadOffset)), - NVB0B5_SET_SEMAPHORE_B, - DRF_NUM(B0B5, _SET_SEMAPHORE_B, _LOWER, NvU64_LO32(pChannel->pbGpuVA+pChannel->finishPayloadOffset)), - NVB0B5_SET_SEMAPHORE_PAYLOAD, - payload); - } + SEC2UTILS_MEMSET_PARAMS memsetParams = {0}; + memsetParams.pMemDesc = pMemDesc; + memsetParams.length = size; - switch (pChannel->hTdCopyClass) - { - case MAXWELL_DMA_COPY_A: - case PASCAL_DMA_COPY_A: - case PASCAL_DMA_COPY_B: - case VOLTA_DMA_COPY_A: - disablePlcKind = 0; - break; - default: // For anything after Turing, set the kind - disablePlcKind = DRF_DEF(C5B5, _LAUNCH_DMA, _DISABLE_PLC, _TRUE); - break; + NV_ASSERT_OK_OR_GOTO(status, sec2utilsMemset(pScrubber->pSec2Utils, &memsetParams), cleanup); + pScrubber->lastSubmittedWorkId = memsetParams.submittedWorkId; } - - NV_PUSH_INC_1U(RM_SUBCHANNEL, NVB0B5_LAUNCH_DMA, - DRF_DEF(B0B5, _LAUNCH_DMA, _SRC_MEMORY_LAYOUT, _PITCH) | - DRF_DEF(B0B5, _LAUNCH_DMA, _DST_MEMORY_LAYOUT, _PITCH) | - DRF_DEF(B0B5, _LAUNCH_DMA, _MULTI_LINE_ENABLE, _FALSE) | - DRF_DEF(B0B5, _LAUNCH_DMA, _REMAP_ENABLE, _TRUE) | - DRF_DEF(B0B5, _LAUNCH_DMA, _FLUSH_ENABLE, _TRUE) | - disablePlcKind | - launchDestType | - pipelinedValue | - semaValue); - - data = DRF_DEF(906F, _SEMAPHORED, _OPERATION, _RELEASE) | - DRF_DEF(906F, _SEMAPHORED, _RELEASE_SIZE, _4BYTE) | - DRF_DEF(906F, _SEMAPHORED, _RELEASE_WFI, _DIS); - - pSemaAddr = (pChannel->pbGpuVA+pChannel->semaOffset); - // - // This should always be at the bottom the push buffer segment, since this - // denotes that HOST has read all the methods needed for this memory operation - // and safely assume that this GPFIFO and PB entry can be reused. - // - NV_PUSH_INC_4U(RM_SUBCHANNEL, NV906F_SEMAPHOREA, - DRF_NUM(906F, _SEMAPHOREA_OFFSET, _UPPER, NvU64_HI32(pSemaAddr)), - NV906F_SEMAPHOREB, - DRF_NUM(906F, _SEMAPHOREB_OFFSET, _LOWER, NvU64_LO32(pSemaAddr) >> 2), - NV906F_SEMAPHOREC, - putIndex, - NV906F_SEMAPHORED, data - ); - // typecasting to calculate the bytes consumed by this iteration. - return (NvU32)((NvU8*)pPtr - (NvU8*)pStartPtr); -} - -/** single helper function to fill the push buffer with the methods needed for - memsetting using fast memory scrubber in CE. This function is much more efficient than - normal CE scrubber operation - TODO: Add support for memcopy here based on channel type. - */ -static NvU32 -_fastscrubFillPb -( - OBJCHANNEL *pChannel, - RmPhysAddr base, - NvU32 size, - NvU32 payload, - NvBool bPipelined, - NV_ADDRESS_SPACE dstAddressSpace, - NvU32 dstCpuCacheAttrib, - NvBool bInsertFinishpayload, - NvBool bNonStallInterrupt, - NvU32 putIndex -) -{ - NvU32 semaValue = 0; - NvU32 pipelinedValue = 0; - NvU32 *pPtr = (NvU32 *)((NvU8*)pChannel->pbCpuVA + (putIndex * pChannel->methodSizePerBlock)); - NvU32 *pStartPtr = pPtr; - NvU32 data = 0; - NvU64 pSemaAddr = 0; - - NV_PRINTF(LEVEL_INFO, "PutIndex: %x, PbOffset: %x\n", putIndex, - putIndex * pChannel->methodSizePerBlock); - - // SET OBJECT - NV_PUSH_INC_1U(RM_SUBCHANNEL, NVC86F_SET_OBJECT, pChannel->classEngineID); - - // Set Pattern for Memset - NV_PUSH_INC_1U(RM_SUBCHANNEL, NVC8B5_SET_REMAP_CONST_A, MEMSET_PATTERN); - NV_PUSH_INC_1U(RM_SUBCHANNEL, NVC8B5_SET_REMAP_CONST_B, MEMSET_PATTERN); - - // Set Component Size to 1 - NV_PUSH_INC_1U(RM_SUBCHANNEL, NVC8B5_SET_REMAP_COMPONENTS, - DRF_DEF(C8B5, _SET_REMAP_COMPONENTS, _DST_X, _CONST_A) | - DRF_DEF(C8B5, _SET_REMAP_COMPONENTS, _DST_X, _CONST_B) | - DRF_DEF(C8B5, _SET_REMAP_COMPONENTS, _COMPONENT_SIZE, _ONE) | - DRF_DEF(C8B5, _SET_REMAP_COMPONENTS, _NUM_DST_COMPONENTS, _ONE)); - - NV_PUSH_INC_1U(RM_SUBCHANNEL, NVC8B5_SET_DST_PHYS_MODE, - DRF_DEF(C8B5, _SET_DST_PHYS_MODE, _TARGET, _LOCAL_FB)); - - semaValue = (bInsertFinishpayload) ? - DRF_DEF(C8B5, _LAUNCH_DMA, _SEMAPHORE_TYPE, _RELEASE_ONE_WORD_SEMAPHORE) : 0; - - if (bPipelined) - pipelinedValue = DRF_DEF(C8B5, _LAUNCH_DMA, _DATA_TRANSFER_TYPE, _PIPELINED); else - pipelinedValue = DRF_DEF(C8B5, _LAUNCH_DMA, _DATA_TRANSFER_TYPE, _NON_PIPELINED); - - NV_PUSH_INC_2U(RM_SUBCHANNEL, NVC8B5_OFFSET_OUT_UPPER, - DRF_NUM(C8B5, _OFFSET_OUT_UPPER, _UPPER, NvU64_HI32(base)), - NVC8B5_OFFSET_OUT_LOWER, - DRF_NUM(C8B5, _OFFSET_OUT_LOWER, _VALUE,NvU64_LO32(base))); - - NV_PUSH_INC_1U(RM_SUBCHANNEL, NVC8B5_LINE_LENGTH_IN, size); - - if (semaValue) - { - NV_PUSH_INC_3U(RM_SUBCHANNEL, NVC8B5_SET_SEMAPHORE_A, - DRF_NUM(C8B5, _SET_SEMAPHORE_A, _UPPER, NvU64_HI32(pChannel->pbGpuVA+pChannel->finishPayloadOffset)), - NVC8B5_SET_SEMAPHORE_B, - DRF_NUM(C8B5, _SET_SEMAPHORE_B, _LOWER, NvU64_LO32(pChannel->pbGpuVA+pChannel->finishPayloadOffset)), - NVC8B5_SET_SEMAPHORE_PAYLOAD, - payload); - } - - NV_PUSH_INC_1U(RM_SUBCHANNEL, NVC8B5_SET_MEMORY_SCRUB_PARAMETERS, - DRF_DEF(C8B5, _SET_MEMORY_SCRUB_PARAMETERS, _DISCARDABLE, _FALSE)); - - NV_PUSH_INC_1U(RM_SUBCHANNEL, NVC8B5_LAUNCH_DMA, - DRF_DEF(C8B5, _LAUNCH_DMA, _SRC_MEMORY_LAYOUT, _PITCH) | - DRF_DEF(C8B5, _LAUNCH_DMA, _DST_MEMORY_LAYOUT, _PITCH) | - DRF_DEF(C8B5, _LAUNCH_DMA, _REMAP_ENABLE, _FALSE) | - DRF_DEF(C8B5, _LAUNCH_DMA, _MULTI_LINE_ENABLE, _FALSE) | - DRF_DEF(C8B5, _LAUNCH_DMA, _FLUSH_ENABLE, _TRUE) | - DRF_DEF(C8B5, _LAUNCH_DMA, _MEMORY_SCRUB_ENABLE, _TRUE) | - DRF_DEF(C8B5, _LAUNCH_DMA, _DISABLE_PLC, _TRUE) | - DRF_DEF(C8B5, _LAUNCH_DMA, _DST_TYPE, _PHYSICAL) | - DRF_DEF(C8B5, _LAUNCH_DMA, _SRC_TYPE, _PHYSICAL) | - pipelinedValue | - semaValue); - - // - // This should always be at the bottom the push buffer segment, since this - // denotes that HOST has read all the methods needed for this memory operation - // and safely assume that this GPFIFO and PB entry can be reused. - // - data = DRF_DEF(C86F, _SEM_EXECUTE, _OPERATION, _RELEASE) | - DRF_DEF(C86F, _SEM_EXECUTE, _PAYLOAD_SIZE, _32BIT) | - DRF_DEF(C86F, _SEM_EXECUTE, _RELEASE_WFI, _DIS); - - pSemaAddr = (pChannel->pbGpuVA+pChannel->semaOffset); - - NV_PUSH_INC_4U(RM_SUBCHANNEL, NVC86F_SEM_ADDR_LO, - DRF_NUM(C86F, _SEM_ADDR_LO, _OFFSET, NvU64_LO32(pSemaAddr) >> 2), - NVC86F_SEM_ADDR_HI, - DRF_NUM(C86F, _SEM_ADDR_HI, _OFFSET, NvU64_HI32(pSemaAddr)), - NVC86F_SEM_PAYLOAD_LO, putIndex, - NVC86F_SEM_PAYLOAD_HI, 0); - - NV_PUSH_INC_1U(RM_SUBCHANNEL, NVC86F_SEM_EXECUTE, data); - - // typecasting to calculate the bytes consumed by this iteration. - return (NvU32)((NvU8*)pPtr - (NvU8*)pStartPtr); -} - -/** helper function which waits for a PB & GPFIO entry to be read by HOST. - * After the HOST reads GPFIFO and PB entry, the semaphore will be released. - */ + { + CEUTILS_MEMSET_PARAMS memsetParams = {0}; + memsetParams.pMemDesc = pMemDesc; + memsetParams.length = size; + memsetParams.flags = NV0050_CTRL_MEMSET_FLAGS_ASYNC | NV0050_CTRL_MEMSET_FLAGS_PIPELINED; -static NvU32 -_scrubWaitForFreeEntry -( - OBJCHANNEL *pChannel -) -{ - NvU32 putIndex = 0; - NvU32 getIndex = 0; + NV_ASSERT_OK_OR_GOTO(status, ceutilsMemset(pScrubber->pCeUtils, &memsetParams), cleanup); + pScrubber->lastSubmittedWorkId = memsetParams.submittedWorkId; + } - putIndex = (pChannel->lastSubmittedEntry + 1) % MAX_SCRUB_ITEMS; - do - { - getIndex = READ_SCRUBBER_PB_SEMA(pChannel); - NV_PRINTF(LEVEL_INFO, "Get Index: %x, PayloadIndex: %x\n", getIndex, - READ_SCRUBBER_PAYLOAD_SEMA(pChannel)); - if (getIndex != putIndex) - { - break; - } - _scrubOsSchedule(pChannel); - } while(1); - return putIndex; +cleanup: + memdescDestroy(pMemDesc); + return status; } -/** helper function to fill GPFIFO entry with a pushbuffer segment. and kick - off the executiion by HOST. - */ - static NV_STATUS -_scrubFillGpFifo +_scrubCombinePages ( - OBJCHANNEL *pChannel, - NvU32 putIndex, - NvU32 methodsLength + NvU64 *pPages, + NvU64 pageSize, + NvU64 pageCount, + PSCRUB_NODE *ppScrubList, + NvU64 *pSize ) { - NvU32 *pGpEntry; - NvU32 GpEntry0; - NvU32 GpEntry1; - NvU64 pbPutOffset; - OBJGPU *pGpu; - KernelBus *pKernelBus; - - NV_ASSERT(putIndex < pChannel->channelNumGpFifioEntries); - - pbPutOffset = (pChannel->pbGpuVA + (putIndex * pChannel->methodSizePerBlock)); - - - GpEntry0 = - DRF_DEF(906F, _GP_ENTRY0, _NO_CONTEXT_SWITCH, _FALSE) | - DRF_NUM(906F, _GP_ENTRY0, _GET, NvU64_LO32(pbPutOffset) >> 2); - GpEntry1 = - DRF_NUM(906F, _GP_ENTRY1, _GET_HI, NvU64_HI32(pbPutOffset)) | - DRF_NUM(906F, _GP_ENTRY1, _LENGTH, methodsLength >> 2) | - DRF_DEF(906F, _GP_ENTRY1, _LEVEL, _MAIN); + NvU64 i, j; - pGpEntry = (NvU32 *)(((NvU8*)pChannel->pbCpuVA) + pChannel->channelPbSize + - (pChannel->lastSubmittedEntry * NV906F_GP_ENTRY__SIZE)); - - MEM_WR32(&pGpEntry[0], GpEntry0); - MEM_WR32(&pGpEntry[1], GpEntry1); - - // - // need to flush WRC buffer - // - osFlushCpuWriteCombineBuffer(); - - // - // write GP put - // - MEM_WR32(&pChannel->pControlGPFifo->GPPut, putIndex); - osFlushCpuWriteCombineBuffer(); + *ppScrubList = (PSCRUB_NODE)portMemAllocNonPaged(sizeof(SCRUB_NODE) * pageCount); + NV_ASSERT_OR_RETURN(*ppScrubList != NULL, NV_ERR_NO_MEMORY); - // - // On some architectures, if doorbell is mapped via bar0, we need to send - // an extra flush - // - pGpu = pChannel->pGpu; - pKernelBus = GPU_GET_KERNEL_BUS(pGpu); - if (kbusFlushPcieForBar0Doorbell_HAL(pGpu, pKernelBus)!= NV_OK) - { - NV_PRINTF(LEVEL_ERROR, "Busflush failed in _scrubFillGpFifo\n"); - return NV_ERR_GENERIC; - } + // Copy first element from original list to new list + (*ppScrubList)[0].base = pPages[0]; + (*ppScrubList)[0].size = pageSize; - // - // removing the FIFO Lite Mode handling - // Refer older _ceChannelUpdateGpFifo_GF100 code for implementation - // - if (pChannel->bUseDoorbellRegister) + for (i = 0, j = 0; i < (pageCount - 1); i++) { - // Use the token from notifier memory for VM migration support. - MEM_WR32(pChannel->pDoorbellRegisterOffset, - MEM_RD32(&(pChannel->pTokenFromNotifier->info32))); - } - return NV_OK; -} - -/** Single function to memset a surface mapped by GPU. This interface supports - both sysmem and vidmem surface, since it uses CE to memset a surface. - The user is notified by releasing semaphore with value "payload" - */ -static NV_STATUS -_scrubMemory -( - OBJCHANNEL *pChannel, - RmPhysAddr base, - NvU64 size, - NV_ADDRESS_SPACE dstAddressSpace, - NvU32 dstCpuCacheAttrib, - NvU32 payload -) -{ - NvBool bFirstIteration = NV_TRUE; - NvBool bNonStallInterrupt = NV_FALSE; - NvU32 tempMemsetSize = 0; // HW supports copy size 32 bits only - NvU32 putIndex = 0; - NV_STATUS status = NV_OK; - NvU32 methodsLength = 0; - NvBool bFastScrubEnable = NV_FALSE; - - do - { - tempMemsetSize = (NvU32)NV_MIN(size, SCRUB_MAX_BYTES_PER_LINE); - - //poll for free entry - putIndex = _scrubWaitForFreeEntry(pChannel); - NV_PRINTF(LEVEL_INFO, "Put Index: %x\n", putIndex); - - // Fill PB with methods - bFastScrubEnable = memmgrMemUtilsCheckMemoryFastScrubEnable_HAL(pChannel->pGpu, - GPU_GET_MEMORY_MANAGER(pChannel->pGpu), pChannel->hTdCopyClass, - pChannel->bUseVasForCeCopy, base, tempMemsetSize, - dstAddressSpace); - - if (bFastScrubEnable) + if ((((*ppScrubList)[j].size + pageSize) > SCRUB_MAX_BYTES_PER_LINE) || + ((pPages[i] + pageSize) != pPages[i+1])) { - NV_PRINTF(LEVEL_INFO, "Fast Scrubber enabled!\n"); - methodsLength = _fastscrubFillPb(pChannel, base, tempMemsetSize, payload, - bFirstIteration, dstAddressSpace, - dstCpuCacheAttrib, (tempMemsetSize == size), - bNonStallInterrupt, putIndex); + j++; + (*ppScrubList)[j].base = pPages[i+1]; + (*ppScrubList)[j].size = pageSize; } else { - NV_PRINTF(LEVEL_INFO, "Fast Scrubber not enabled!\n"); - methodsLength = _scrubFillPb(pChannel, base, tempMemsetSize, payload, - bFirstIteration, dstAddressSpace, - dstCpuCacheAttrib, (tempMemsetSize == size), - bNonStallInterrupt, putIndex); + (*ppScrubList)[j].size += pageSize; } + } - NV_PRINTF(LEVEL_INFO, "MethodLength: %x\n", methodsLength); - // Add the PB entry in GP FIFO - status = _scrubFillGpFifo(pChannel, putIndex, methodsLength); - - pChannel->lastSubmittedEntry = putIndex; - - base += tempMemsetSize; - size -= tempMemsetSize; - bFirstIteration = NV_FALSE; - } while (size > 0); + *pSize = j + 1; - return status; + return NV_OK; } diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/kernel/gpu/mem_mgr/mem_utils.c nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/kernel/gpu/mem_mgr/mem_utils.c --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/kernel/gpu/mem_mgr/mem_utils.c 2023-10-25 20:21:12.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/kernel/gpu/mem_mgr/mem_utils.c 2024-03-05 22:13:37.000000000 +0000 @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 2020-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2020-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -27,9 +27,21 @@ #include "gpu/mem_mgr/virt_mem_allocator_common.h" #include "os/nv_memory_type.h" #include "core/locks.h" +#include "ctrl/ctrl2080.h" +#include "rmapi/rs_utils.h" +#include "gpu/subdevice/subdevice.h" + +#include "kernel/gpu/fifo/kernel_fifo.h" +#include "kernel/gpu/fifo/kernel_channel.h" #include "gpu/bus/kern_bus.h" +#include "kernel/gpu/conf_compute/ccsl.h" + +#include "class/cl0005.h" // NV01_EVENT + +#include "ctrl/ctrla06f/ctrla06fgpfifo.h" + // Memory copy block size for if we need to cut up a mapping #define MEMORY_COPY_BLOCK_SIZE 1024 * 1024 @@ -42,10 +54,395 @@ static TRANSFER_TYPE memmgrGetMemTransferType ( - MemoryManager *pMemoryManager + MemoryManager *pMemoryManager, + TRANSFER_SURFACE *pDst, + TRANSFER_SURFACE *pSrc ) { - return TRANSFER_TYPE_PROCESSOR; + TRANSFER_TYPE transferType = TRANSFER_TYPE_PROCESSOR; + OBJGPU *pGpu = ENG_GET_GPU(pMemoryManager); + KernelBus *pKernelBus = GPU_GET_KERNEL_BUS(pGpu); + + // + // In case of copy, both dest and src will be passed + // In case of memset/memread/memwrite either dest or src will be passed + // + if ((pDst != NULL) && (pSrc != NULL) && + (memdescGetAddressSpace(pDst->pMemDesc) == ADDR_SYSMEM) && + (memdescGetAddressSpace(pSrc->pMemDesc) == ADDR_SYSMEM)) + { + transferType = TRANSFER_TYPE_PROCESSOR; + } + else if (((pDst != NULL) && + (memdescGetAddressSpace(pDst->pMemDesc) == ADDR_SYSMEM)) || + ((pSrc != NULL) && + (memdescGetAddressSpace(pSrc->pMemDesc) == ADDR_SYSMEM))) + { + transferType = TRANSFER_TYPE_PROCESSOR; + } + else if (kbusIsBarAccessBlocked(pKernelBus)) + { + transferType = TRANSFER_TYPE_GSP_DMA; + } + return transferType; +} + +static NV_STATUS +_memmgrAllocAndMapSurface +( + OBJGPU *pGpu, + NvU64 size, + MEMORY_DESCRIPTOR **ppMemDesc, + void **ppMap, + void **ppPriv +) +{ + NV_STATUS status; + NvU64 flags = 0; + + NV_ASSERT_OR_RETURN(ppMemDesc != NULL, NV_ERR_INVALID_ARGUMENT); + NV_ASSERT_OR_RETURN(ppMap != NULL, NV_ERR_INVALID_ARGUMENT); + NV_ASSERT_OR_RETURN(ppPriv != NULL, NV_ERR_INVALID_ARGUMENT); + + flags = MEMDESC_FLAGS_ALLOC_IN_UNPROTECTED_MEMORY; + + NV_ASSERT_OK_OR_RETURN( + memdescCreate(ppMemDesc, pGpu, size, RM_PAGE_SIZE, NV_TRUE, + ADDR_SYSMEM, NV_MEMORY_UNCACHED, flags)); + + NV_ASSERT_OK_OR_GOTO(status, memdescAlloc(*ppMemDesc), failed); + + NV_ASSERT_OK_OR_GOTO(status, + memdescMapOld(*ppMemDesc, 0, size, NV_TRUE, NV_PROTECT_READ_WRITE, + ppMap, ppPriv), + failed); + + // Clear surface before use + portMemSet(*ppMap, 0, size); + + return NV_OK; +failed: + memdescFree(*ppMemDesc); + memdescDestroy(*ppMemDesc); + + *ppMemDesc = NULL; + *ppMap = NULL; + *ppPriv = NULL; + + return status; +} + +static void +_memmgrUnmapAndFreeSurface +( + MEMORY_DESCRIPTOR *pMemDesc, + void *pMap, + void *pPriv +) +{ + memdescUnmapOld(pMemDesc, NV_TRUE, 0, pMap, pPriv); + + memdescFree(pMemDesc); + memdescDestroy(pMemDesc); +} + +/*! + * @brief This function is used for writing/reading data to/from a client + * provided buffer from/to some source region in vidmem + * + * @param[in] pDst TRANSFER_SURFACE info for destination region + * @param[in] pBuf Client provided buffer + * @param[in] size Size in bytes of the memory transfer + * @param[in] bRead TRUE for read and FALSE for write + */ +static NV_STATUS +_memmgrMemReadOrWriteWithGsp +( + OBJGPU *pGpu, + TRANSFER_SURFACE *pDst, + void *pBuf, + NvU64 size, + NvBool bRead +) +{ + NV2080_CTRL_INTERNAL_MEMMGR_MEMORY_TRANSFER_WITH_GSP_PARAMS gspParams; + NV_STATUS status; + MEMORY_DESCRIPTOR *pStagingBuf = NULL; + void *pStagingBufMap = NULL; + void *pStagingBufPriv = NULL; + RM_API *pRmApi = GPU_GET_PHYSICAL_RMAPI(pGpu); + ConfidentialCompute *pConfCompute = GPU_GET_CONF_COMPUTE(pGpu); + if (gpuIsCCFeatureEnabled(pGpu)) + { + NV_ASSERT_OR_RETURN(pConfCompute->getProperty(pCC, + PDB_PROP_CONFCOMPUTE_ENCRYPT_ENABLED), + NV_ERR_INVALID_STATE); + } + + // Do not expect GSP to be used for reading/writing from/to sysmem + if (memdescGetAddressSpace(pDst->pMemDesc) == ADDR_SYSMEM) + return NV_ERR_NOT_SUPPORTED; + + // Allocate and map the staging buffer + NV_ASSERT_OK_OR_RETURN( + _memmgrAllocAndMapSurface(pGpu, size, &pStagingBuf, &pStagingBufMap, + &pStagingBufPriv)); + + // Setup control call params + portMemSet(&gspParams, 0, sizeof(gspParams)); + + // Copy the data to staging buffer before poking GSP for copying + if (!bRead) + { + if (gpuIsCCFeatureEnabled(pGpu)) + { + NV_ASSERT_OK_OR_GOTO(status, + ccslEncrypt_HAL(pConfCompute->pDmaCcslCtx, size, pBuf, NULL, 0, + pStagingBufMap, gspParams.authTag), + failed); + } + else + { + portMemCopy(pStagingBufMap, size, pBuf, size); + } + } + + gspParams.memop = NV2080_CTRL_MEMMGR_MEMORY_OP_MEMCPY; + gspParams.transferSize = size; + + if (bRead) + { + // Source surface in vidmem + gspParams.src.baseAddr = memdescGetPhysAddr(pDst->pMemDesc, AT_GPU, 0); + gspParams.src.size = memdescGetSize(pDst->pMemDesc); + gspParams.src.offset = pDst->offset; + gspParams.src.cpuCacheAttrib = memdescGetCpuCacheAttrib(pDst->pMemDesc); + gspParams.src.aperture = memdescGetAddressSpace(pDst->pMemDesc); + + // Destination surface in unprotected sysmem + gspParams.dst.baseAddr = memdescGetPhysAddr(pStagingBuf, AT_GPU, 0); + gspParams.dst.size = memdescGetSize(pStagingBuf); + gspParams.dst.offset = 0; + gspParams.dst.cpuCacheAttrib = memdescGetCpuCacheAttrib(pStagingBuf); + gspParams.dst.aperture = memdescGetAddressSpace(pStagingBuf); + } + else + { + // Source surface in unprotected sysmem + gspParams.src.baseAddr = memdescGetPhysAddr(pStagingBuf, AT_GPU, 0); + gspParams.src.size = memdescGetSize(pStagingBuf); + gspParams.src.offset = 0; + gspParams.src.cpuCacheAttrib = memdescGetCpuCacheAttrib(pStagingBuf); + gspParams.src.aperture = memdescGetAddressSpace(pStagingBuf); + + // Destination surface in vidmem + gspParams.dst.baseAddr = memdescGetPhysAddr(pDst->pMemDesc, AT_GPU, 0); + gspParams.dst.size = memdescGetSize(pDst->pMemDesc); + gspParams.dst.offset = pDst->offset; + gspParams.dst.cpuCacheAttrib = memdescGetCpuCacheAttrib(pDst->pMemDesc); + gspParams.dst.aperture = memdescGetAddressSpace(pDst->pMemDesc); + } + + // Send the control call + NV_ASSERT_OK_OR_GOTO(status, + pRmApi->Control(pRmApi, + pGpu->hInternalClient, + pGpu->hInternalSubdevice, + NV2080_CTRL_CMD_INTERNAL_MEMMGR_MEMORY_TRANSFER_WITH_GSP, + &gspParams, + sizeof(gspParams)), + failed); + + // Read contents from staging buffer after GSP is done copying + if (bRead) + { + if (gpuIsCCFeatureEnabled(pGpu)) + { + NV_ASSERT_OK_OR_GOTO(status, + ccslDecrypt_HAL(pConfCompute->pDmaCcslCtx, size, pStagingBufMap, + NULL, NULL, 0, pBuf, gspParams.authTag), + failed); + } + else + { + portMemCopy(pBuf, size, pStagingBufMap, size); + } + } + +failed: + _memmgrUnmapAndFreeSurface(pStagingBuf, pStagingBufMap, pStagingBufPriv); + return status; +} + +/*! + * @brief This function is used for copying data b/w two memory regions + * using GSP. + * + * @param[in] pDst TRANSFER_SURFACE info for destination region + * @param[in] pSrc TRANSFER_SURFACE info for source region + * @param[in] size Size in bytes of the memory transfer + */ +static NV_STATUS +_memmgrMemcpyWithGsp +( + OBJGPU *pGpu, + TRANSFER_SURFACE *pDst, + TRANSFER_SURFACE *pSrc, + NvU64 size +) +{ + NV2080_CTRL_INTERNAL_MEMMGR_MEMORY_TRANSFER_WITH_GSP_PARAMS gspParams; + NV_STATUS status; + MEMORY_DESCRIPTOR *pStagingBuf = NULL; + void *pStagingBufMap = NULL; + void *pStagingBufPriv = NULL; + NvU8 *pMap = NULL; + void *pPriv = NULL; + RM_API *pRmApi = GPU_GET_PHYSICAL_RMAPI(pGpu); + + // + // Do not expect GSP to be used for copying data b/w two surfaces + // in sysmem. For SPT, there is no non-CPR vidmem. So, allow vidmem + // to vidmem copies in plain text. For copies b/w CPR and non-CPR + // vidmem, encryption/decryption needs to happen at the endpoints. + // + if (memdescGetAddressSpace(pSrc->pMemDesc) == ADDR_SYSMEM && + memdescGetAddressSpace(pDst->pMemDesc) == ADDR_SYSMEM) + { + return NV_ERR_NOT_SUPPORTED; + } + + // Allocate and map the bounce buffer + NV_ASSERT_OK_OR_RETURN( + _memmgrAllocAndMapSurface(pGpu, size, &pStagingBuf, &pStagingBufMap, + &pStagingBufPriv)); + + // Setup control call params + portMemSet(&gspParams, 0, sizeof(gspParams)); + + gspParams.memop = NV2080_CTRL_MEMMGR_MEMORY_OP_MEMCPY; + gspParams.transferSize = size; + + if (memdescGetAddressSpace(pSrc->pMemDesc) == ADDR_SYSMEM) + { + NV_ASSERT_OK_OR_GOTO(status, + memdescMapOld(pSrc->pMemDesc, 0, size, NV_TRUE, + NV_PROTECT_READ_WRITE, (void**)&pMap, &pPriv), + failed); + + // Copy to staging buffer + portMemCopy(pStagingBufMap, size, pMap + pSrc->offset, size); + + memdescUnmapOld(pSrc->pMemDesc, NV_TRUE, 0, (void*)pMap, pPriv); + + // Source surface in unprotected sysmem + gspParams.src.baseAddr = memdescGetPhysAddr(pStagingBuf, AT_GPU, 0); + gspParams.src.size = memdescGetSize(pStagingBuf); + gspParams.src.offset = 0; + gspParams.src.cpuCacheAttrib = memdescGetCpuCacheAttrib(pStagingBuf); + gspParams.src.aperture = memdescGetAddressSpace(pStagingBuf); + + // Destination surface in vidmem + gspParams.dst.baseAddr = memdescGetPhysAddr(pDst->pMemDesc, AT_GPU, 0); + gspParams.dst.size = memdescGetSize(pDst->pMemDesc); + gspParams.dst.offset = pDst->offset; + gspParams.dst.cpuCacheAttrib = memdescGetCpuCacheAttrib(pDst->pMemDesc); + gspParams.dst.aperture = memdescGetAddressSpace(pDst->pMemDesc); + } + else + { + // Source surface in vidmem + gspParams.src.baseAddr = memdescGetPhysAddr(pSrc->pMemDesc, AT_GPU, 0); + gspParams.src.size = memdescGetSize(pSrc->pMemDesc); + gspParams.src.offset = pSrc->offset; + gspParams.src.cpuCacheAttrib = memdescGetCpuCacheAttrib(pSrc->pMemDesc); + gspParams.src.aperture = memdescGetAddressSpace(pSrc->pMemDesc); + + if (memdescGetAddressSpace(pDst->pMemDesc) == ADDR_FBMEM) + { + // Destination surface in vidmem + gspParams.dst.baseAddr = memdescGetPhysAddr(pDst->pMemDesc, AT_GPU, 0); + gspParams.dst.size = memdescGetSize(pDst->pMemDesc); + gspParams.dst.offset = pDst->offset; + gspParams.dst.cpuCacheAttrib = memdescGetCpuCacheAttrib(pDst->pMemDesc); + gspParams.dst.aperture = memdescGetAddressSpace(pDst->pMemDesc); + } + else + { + // Destination surface in unprotected sysmem + gspParams.dst.baseAddr = memdescGetPhysAddr(pStagingBuf, AT_GPU, 0); + gspParams.dst.size = memdescGetSize(pStagingBuf); + gspParams.dst.offset = 0; + gspParams.dst.cpuCacheAttrib = memdescGetCpuCacheAttrib(pStagingBuf); + gspParams.dst.aperture = memdescGetAddressSpace(pStagingBuf); + } + } + + // Send the control call + NV_ASSERT_OK_OR_GOTO(status, + pRmApi->Control(pRmApi, + pGpu->hInternalClient, + pGpu->hInternalSubdevice, + NV2080_CTRL_CMD_INTERNAL_MEMMGR_MEMORY_TRANSFER_WITH_GSP, + &gspParams, + sizeof(gspParams)), + failed); + + // Copy from staging buffer to destination + if (memdescGetAddressSpace(pDst->pMemDesc) == ADDR_SYSMEM) + { + NV_ASSERT_OK_OR_GOTO(status, + memdescMapOld(pDst->pMemDesc, 0, size, NV_TRUE, + NV_PROTECT_READ_WRITE, (void**)&pMap, &pPriv), + failed); + + portMemCopy(pMap + pDst->offset, size, pStagingBufMap, size); + + memdescUnmapOld(pDst->pMemDesc, NV_TRUE, 0, (void*)pMap, pPriv); + } + +failed: + _memmgrUnmapAndFreeSurface(pStagingBuf, pStagingBufMap, pStagingBufPriv); + return status; +} + +static NV_STATUS +_memmgrMemsetWithGsp +( + OBJGPU *pGpu, + TRANSFER_SURFACE *pDst, + NvU32 value, + NvU64 size +) +{ + NV2080_CTRL_INTERNAL_MEMMGR_MEMORY_TRANSFER_WITH_GSP_PARAMS gspParams; + RM_API *pRmApi = GPU_GET_PHYSICAL_RMAPI(pGpu); + + // Do not expect to use GSP to memset surfaces in sysmem + if (memdescGetAddressSpace(pDst->pMemDesc) == ADDR_SYSMEM) + return NV_ERR_NOT_SUPPORTED; + + portMemSet(&gspParams, 0, sizeof(gspParams)); + + gspParams.memop = NV2080_CTRL_MEMMGR_MEMORY_OP_MEMSET; + gspParams.transferSize = size; + gspParams.value = value; + gspParams.dst.baseAddr = memdescGetPhysAddr(pDst->pMemDesc, AT_GPU, 0); + gspParams.dst.size = memdescGetSize(pDst->pMemDesc); + gspParams.dst.offset = pDst->offset; + gspParams.dst.cpuCacheAttrib = memdescGetCpuCacheAttrib(pDst->pMemDesc); + gspParams.dst.aperture = memdescGetAddressSpace(pDst->pMemDesc); + + // Send the control call + NV_ASSERT_OK_OR_RETURN( + pRmApi->Control(pRmApi, + pGpu->hInternalClient, + pGpu->hInternalSubdevice, + NV2080_CTRL_CMD_INTERNAL_MEMMGR_MEMORY_TRANSFER_WITH_GSP, + &gspParams, + sizeof(gspParams))); + + return NV_OK; } /*! @@ -100,7 +497,15 @@ memdescUnmapInternal(pGpu, pDstInfo->pMemDesc, flags); break; case TRANSFER_TYPE_GSP_DMA: - NV_PRINTF(LEVEL_INFO, "Add call to GSP DMA task\n"); + if (IS_GSP_CLIENT(pGpu)) + { + NV_ASSERT_OK_OR_RETURN( + _memmgrMemcpyWithGsp(pGpu, pDstInfo, pSrcInfo, size)); + } + else + { + NV_ASSERT_OR_RETURN(0, NV_ERR_INVALID_ARGUMENT); + } break; case TRANSFER_TYPE_CE: NV_PRINTF(LEVEL_INFO, "Add call to CE\n"); @@ -151,7 +556,15 @@ memdescUnmapInternal(pGpu, pDstInfo->pMemDesc, flags); break; case TRANSFER_TYPE_GSP_DMA: - NV_PRINTF(LEVEL_INFO, "Add call to GSP DMA task\n"); + if (IS_GSP_CLIENT(pGpu)) + { + NV_ASSERT_OK_OR_RETURN( + _memmgrMemsetWithGsp(pGpu, pDstInfo, value, size)); + } + else + { + NV_ASSERT_OR_RETURN(0, NV_ERR_INVALID_ARGUMENT); + } break; case TRANSFER_TYPE_CE: NV_PRINTF(LEVEL_INFO, "Add call to CE\n"); @@ -179,7 +592,7 @@ void *pBuf, NvU64 offset, NvU64 size, - NvU32 flags + NvU32 flags ) { NvU8 *pDst = NULL; @@ -231,9 +644,9 @@ NV_CHECK_OK_OR_RETURN(LEVEL_SILENT, memdescCreateSubMem(&pSubMemDesc, pMemDesc, pGpu, offset + baseOffset, mapSize)); // Set the offset to 0, as the sub descriptor already starts at the offset - status = memmgrMemWriteMapAndCopy(pMemoryManager, pSubMemDesc, (NvU8 *)pBuf + offset, + status = memmgrMemWriteMapAndCopy(pMemoryManager, pSubMemDesc, (NvU8 *)pBuf + offset, 0, mapSize, flags); - + memdescFree(pSubMemDesc); memdescDestroy(pSubMemDesc); @@ -266,6 +679,7 @@ ) { NvU8 *pMapping = memdescGetKernelMapping(pDstInfo->pMemDesc); + OBJGPU *pGpu = ENG_GET_GPU(pMemoryManager); // Sanitize the input NV_ASSERT_OR_RETURN(pDstInfo != NULL, NV_ERR_INVALID_ARGUMENT); @@ -291,7 +705,17 @@ } break; case TRANSFER_TYPE_GSP_DMA: - NV_PRINTF(LEVEL_INFO, "Add call to GSP DMA task\n"); + if (IS_GSP_CLIENT(pGpu)) + { + NV_PRINTF(LEVEL_INFO, "Calling GSP DMA task\n"); + NV_ASSERT_OK_OR_RETURN( + _memmgrMemReadOrWriteWithGsp(pGpu, pDstInfo, pBuf, size, + NV_FALSE /* bRead */)); + } + else + { + NV_ASSERT_OR_RETURN(0, NV_ERR_INVALID_ARGUMENT); + } break; case TRANSFER_TYPE_CE: NV_PRINTF(LEVEL_INFO, "Add call to CE\n"); @@ -352,7 +776,16 @@ memdescUnmapInternal(pGpu, pSrcInfo->pMemDesc, 0); break; case TRANSFER_TYPE_GSP_DMA: - NV_PRINTF(LEVEL_INFO, "Add call to GSP DMA task\n"); + if (IS_GSP_CLIENT(pGpu)) + { + NV_ASSERT_OK_OR_RETURN( + _memmgrMemReadOrWriteWithGsp(pGpu, pSrcInfo, pBuf, size, + NV_TRUE /* bRead */)); + } + else + { + NV_ASSERT_OR_RETURN(0, NV_ERR_INVALID_ARGUMENT); + } break; case TRANSFER_TYPE_CE: NV_PRINTF(LEVEL_INFO, "Add call to CE\n"); @@ -460,6 +893,31 @@ } } + +MEMORY_DESCRIPTOR * +memmgrMemUtilsGetMemDescFromHandle_IMPL +( + MemoryManager *pMemoryManager, + NvHandle hClient, + NvHandle hMemory +) +{ + RsResourceRef *pMemoryRef; + Memory *pMemory; + + if (serverutilGetResourceRef(hClient, hMemory, &pMemoryRef) != NV_OK) + { + return NULL; + } + + pMemory = dynamicCast(pMemoryRef->pResource, Memory); + if (pMemory == NULL) + { + return NULL; + } + return pMemory->pMemDesc; +} + /*! * @brief This function is used for copying data b/w two memory regions * Both memory regions can be in the same aperture of different apertures @@ -479,7 +937,8 @@ NvU32 flags ) { - TRANSFER_TYPE transferType = memmgrGetMemTransferType(pMemoryManager); + TRANSFER_TYPE transferType = memmgrGetMemTransferType(pMemoryManager, + pDstInfo, pSrcInfo); return memmgrMemCopyWithTransferType(pMemoryManager, pDstInfo, pSrcInfo, size, transferType, flags); @@ -503,7 +962,8 @@ NvU32 flags ) { - TRANSFER_TYPE transferType = memmgrGetMemTransferType(pMemoryManager); + TRANSFER_TYPE transferType = memmgrGetMemTransferType(pMemoryManager, + pDstInfo, NULL); return memmgrMemSetWithTransferType(pMemoryManager, pDstInfo, value, size, transferType, flags); @@ -526,7 +986,8 @@ ) { TRANSFER_SURFACE transferSurface = {.offset = 0, .pMemDesc = pMemDesc}; - TRANSFER_TYPE transferType = memmgrGetMemTransferType(pMemoryManager); + TRANSFER_TYPE transferType = memmgrGetMemTransferType(pMemoryManager, + &transferSurface, NULL); return memmgrMemSetWithTransferType(pMemoryManager, &transferSurface, value, (NvU32)memdescGetSize(pMemDesc), @@ -552,7 +1013,8 @@ NvU32 flags ) { - TRANSFER_TYPE transferType = memmgrGetMemTransferType(pMemoryManager); + TRANSFER_TYPE transferType = memmgrGetMemTransferType(pMemoryManager, + pDstInfo, NULL); return memmgrMemWriteWithTransferType(pMemoryManager, pDstInfo, pBuf, size, transferType, flags); @@ -577,7 +1039,8 @@ NvU32 flags ) { - TRANSFER_TYPE transferType = memmgrGetMemTransferType(pMemoryManager); + TRANSFER_TYPE transferType = memmgrGetMemTransferType(pMemoryManager, + NULL, pSrcInfo); return memmgrMemReadWithTransferType(pMemoryManager, pSrcInfo, pBuf, size, transferType, flags); @@ -599,7 +1062,8 @@ NvU32 flags ) { - TRANSFER_TYPE transferType = memmgrGetMemTransferType(pMemoryManager); + TRANSFER_TYPE transferType = memmgrGetMemTransferType(pMemoryManager, + pTransferInfo, NULL); MEMORY_DESCRIPTOR *pMemDesc = pTransferInfo->pMemDesc; NvU64 offset = pTransferInfo->offset; OBJGPU *pGpu = ENG_GET_GPU(pMemoryManager); @@ -615,8 +1079,28 @@ switch (transferType) { case TRANSFER_TYPE_PROCESSOR: + if (flags & TRANSFER_FLAGS_USE_BAR1) + { + NvP64 pPriv; + NvU32 protect = NV_PROTECT_READ_WRITE; + + if (flags & TRANSFER_FLAGS_MAP_PROTECT_READABLE) + { + protect = NV_PROTECT_READABLE; + } + else if (flags & TRANSFER_FLAGS_MAP_PROTECT_WRITEABLE) + { + protect = NV_PROTECT_WRITEABLE; + } + + NV_ASSERT_OR_RETURN(memdescMap(pMemDesc, offset, memSz, NV_TRUE, protect, + (NvP64*) &pPtr, &pPriv) == NV_OK, NULL); + memdescSetKernelMappingPriv(pMemDesc, pPriv); + break; + } NV_ASSERT_OR_RETURN((pPtr = memdescMapInternal(pGpu, pMemDesc, flags)) != NULL, NULL); pPtr = &pPtr[offset]; + break; case TRANSFER_TYPE_GSP_DMA: case TRANSFER_TYPE_CE: @@ -652,16 +1136,18 @@ NvU32 flags ) { - TRANSFER_TYPE transferType = memmgrGetMemTransferType(pMemoryManager); + TRANSFER_TYPE transferType = memmgrGetMemTransferType(pMemoryManager, + pTransferInfo, NULL); MEMORY_DESCRIPTOR *pMemDesc = pTransferInfo->pMemDesc; NvU64 offset = pTransferInfo->offset; OBJGPU *pGpu = ENG_GET_GPU(pMemoryManager); NvU64 memSz = 0; - NvU8 *pMapping = memdescGetKernelMapping(pMemDesc); + NvU8 *pMapping = NULL; NV_ASSERT_OR_RETURN_VOID(pMemDesc != NULL); - NV_ASSERT_OR_RETURN_VOID((memSz = memdescGetSize(pMemDesc)) >= (shadowBufSize + offset) ); + pMapping = memdescGetKernelMapping(pMemDesc); + NV_ASSERT_OR_RETURN_VOID((memSz = memdescGetSize(pMemDesc)) >= (shadowBufSize + offset) ); memSz = shadowBufSize == 0 ? memSz : shadowBufSize; memdescSetKernelMapping(pMemDesc, NULL); @@ -669,6 +1155,16 @@ switch (transferType) { case TRANSFER_TYPE_PROCESSOR: + if (flags & TRANSFER_FLAGS_USE_BAR1) + { + NvP64 pPriv = memdescGetKernelMappingPriv(pMemDesc); + memdescSetKernelMappingPriv(pMemDesc, NULL); + if (pMapping != NULL) + { + memdescUnmap(pMemDesc, NV_TRUE, 0, pMapping, pPriv); + } + return; + } memdescUnmapInternal(pGpu, pMemDesc, flags); return; case TRANSFER_TYPE_GSP_DMA: @@ -699,6 +1195,11 @@ NvU32 flags ) { + if (pMemDesc == NULL) + { + return; + } + TRANSFER_SURFACE transferSurface = {.offset = 0, .pMemDesc = pMemDesc}; memmgrMemEndTransfer(pMemoryManager, &transferSurface, memdescGetSize(pMemDesc), flags); } @@ -717,6 +1218,7 @@ NvU32 flags ) { + NV_ASSERT_OR_RETURN(pMemDesc != NULL, NULL); TRANSFER_SURFACE transferSurface = {.offset = 0, .pMemDesc = pMemDesc}; return memmgrMemBeginTransfer(pMemoryManager, &transferSurface, memdescGetSize(pMemDesc), flags); } @@ -743,7 +1245,7 @@ NV_ADDRESS_SPACE addrSpace = memmgrAllocGetAddrSpace(pMemoryManager, pVidHeapAlloc->flags, pFbAllocInfo->retAttr); - NvU32 pageSize = 0; + NvU64 pageSize = 0; NvBool bAllocedHwRes = NV_FALSE; // IRQL TEST: must be running at equivalent of passive-level @@ -883,7 +1385,7 @@ (addrSpace == ADDR_FBMEM)) { OBJSYS *pSys = SYS_GET_INSTANCE(); - NvU32 hostPageSize = pSys->cpuInfo.hostPageSize; + NvU64 hostPageSize = pSys->cpuInfo.hostPageSize; // hostPageSize *should* always be set, but.... if (hostPageSize == 0) @@ -1003,6 +1505,15 @@ switch (memdescGetAddressSpace(pMemDesc)) { case ADDR_FBMEM: + if (KBUS_BAR0_PRAMIN_DISABLED(pGpu)) + { + NvU8 *pMap = kbusMapRmAperture_HAL(pGpu, pMemDesc); + NV_ASSERT_OR_RETURN(pMap != NULL, NV_ERR_INSUFFICIENT_RESOURCES); + portMemSet(pMap, value, pMemDesc->Size); + kbusUnmapRmAperture_HAL(pGpu, pMemDesc, &pMap, NV_TRUE); + + break; + } // // Set the BAR0 window to encompass the given surface while // saving off the location to where the BAR0 window was @@ -1061,3 +1572,199 @@ return NV_OK; } + +/*! + * Registers the callback specified in clientHeap.callback for the channel + * driven scrub. The callback is triggered by NV906F_NON_STALL_INTERRUPT. + */ +static NV_STATUS +_memmgrMemUtilsScrubInitRegisterCallback +( + OBJGPU *pGpu, + OBJCHANNEL *pChannel +) +{ + NV0005_ALLOC_PARAMETERS nv0005AllocParams; + NV2080_CTRL_EVENT_SET_NOTIFICATION_PARAMS nv2080EventNotificationParams; + NV_STATUS rmStatus; + NvHandle subDeviceHandle = 0; + Subdevice *pSubDevice; + RM_API *pRmApi = rmapiGetInterface(RMAPI_GPU_LOCK_INTERNAL); + NvU32 subdeviceInstance = gpumgrGetSubDeviceInstanceFromGpu(pGpu); + + rmStatus = subdeviceGetByInstance(pChannel->pRsClient, pChannel->deviceId, + subdeviceInstance, &pSubDevice); + if (rmStatus != NV_OK) + { + NV2080_ALLOC_PARAMETERS nv2080AllocParams; + + NV_PRINTF(LEVEL_WARNING, "Unable to get subdevice handle. Allocating subdevice\n"); + + // Allocate a sub device if we dont have it created before hand + portMemSet(&nv2080AllocParams, 0, sizeof(NV2080_ALLOC_PARAMETERS)); + nv2080AllocParams.subDeviceId = subdeviceInstance; + + rmStatus = pRmApi->AllocWithHandle(pRmApi, + pChannel->hClient, + pChannel->deviceId, + pChannel->subdeviceId, + NV20_SUBDEVICE_0, + &nv2080AllocParams, + sizeof(nv2080AllocParams)); + if (rmStatus != NV_OK) + { + NV_PRINTF(LEVEL_ERROR, "Unable to allocate a subdevice.\n"); + return NV_ERR_GENERIC; + } + + // Set newly created subdevice's handle + subDeviceHandle = pChannel->subdeviceId; + } + else + { + GPU_RES_SET_THREAD_BC_STATE(pSubDevice); + + subDeviceHandle = RES_GET_HANDLE(pSubDevice); + } + + // Register callback + portMemSet(&nv0005AllocParams, 0, sizeof(NV0005_ALLOC_PARAMETERS)); + nv0005AllocParams.hParentClient = pChannel->hClient; + nv0005AllocParams.hClass = NV01_EVENT_KERNEL_CALLBACK_EX; + nv0005AllocParams.notifyIndex = NV2080_NOTIFIERS_FIFO_EVENT_MTHD | NV01_EVENT_NONSTALL_INTR ; + nv0005AllocParams.data = NV_PTR_TO_NvP64(&pChannel->callback); + + rmStatus = pRmApi->AllocWithHandle(pRmApi, + pChannel->hClient, + subDeviceHandle, + pChannel->eventId, + NV01_EVENT_KERNEL_CALLBACK_EX, + &nv0005AllocParams, + sizeof(nv0005AllocParams)); + + if (rmStatus != NV_OK) + { + NV_PRINTF(LEVEL_ERROR, "event allocation failed\n"); + return NV_ERR_GENERIC; + } + + // Setup periodic event notification + portMemSet(&nv2080EventNotificationParams, 0, sizeof(NV2080_CTRL_EVENT_SET_NOTIFICATION_PARAMS)); + nv2080EventNotificationParams.event = NV2080_NOTIFIERS_FIFO_EVENT_MTHD; + nv2080EventNotificationParams.action = NV2080_CTRL_EVENT_SET_NOTIFICATION_ACTION_REPEAT; + + rmStatus = pRmApi->Control(pRmApi, + pChannel->hClient, + subDeviceHandle, + NV2080_CTRL_CMD_EVENT_SET_NOTIFICATION, + &nv2080EventNotificationParams, + sizeof(NV2080_CTRL_EVENT_SET_NOTIFICATION_PARAMS)); + + if (rmStatus != NV_OK) + { + NV_PRINTF(LEVEL_ERROR, "event notification control failed\n"); + return NV_ERR_GENERIC; + } + + return NV_OK; +} + +/*! + * Schedules the scrubber channel for execution. + */ +static NV_STATUS +_memmgrMemUtilsScrubInitScheduleChannel +( + OBJGPU *pGpu, + OBJCHANNEL *pChannel +) +{ + NV_STATUS rmStatus; + NVA06F_CTRL_GPFIFO_SCHEDULE_PARAMS nvA06fScheduleParams; + RM_API *pRmApi = rmapiGetInterface(RMAPI_GPU_LOCK_INTERNAL); + + if (pChannel->bUseVasForCeCopy) + { + NVA06F_CTRL_BIND_PARAMS bindParams; + portMemSet(&bindParams, 0, sizeof(bindParams)); + + bindParams.engineType = gpuGetNv2080EngineType(pChannel->engineType); + + rmStatus = pRmApi->Control(pRmApi, + pChannel->hClient, + pChannel->channelId, + NVA06F_CTRL_CMD_BIND, + &bindParams, + sizeof(bindParams)); + if (rmStatus != NV_OK) + { + NV_PRINTF(LEVEL_ERROR, "Unable to bind Channel, status: %x\n", rmStatus); + return rmStatus; + } + } + + portMemSet(&nvA06fScheduleParams, 0, sizeof(NVA06F_CTRL_GPFIFO_SCHEDULE_PARAMS)); + nvA06fScheduleParams.bEnable = NV_TRUE; + + rmStatus = pRmApi->Control(pRmApi, + pChannel->hClient, + pChannel->channelId, + NVA06F_CTRL_CMD_GPFIFO_SCHEDULE, + &nvA06fScheduleParams, + sizeof(NVA06F_CTRL_GPFIFO_SCHEDULE_PARAMS)); + + if (rmStatus != NV_OK) + { + NV_PRINTF(LEVEL_ERROR, "Unable to schedule channel, status: %x\n", rmStatus); + return NV_ERR_GENERIC; + } + + return NV_OK; +} + +NV_STATUS +memmgrMemUtilsChannelSchedulingSetup_IMPL +( + OBJGPU *pGpu, + MemoryManager *pMemoryManager, + OBJCHANNEL *pChannel +) +{ + NvU32 classID; + RM_ENGINE_TYPE engineID; + KernelFifo *pKernelFifo = GPU_GET_KERNEL_FIFO(pGpu); + KernelChannel *pFifoKernelChannel = NULL; + + // schedulechannel + NV_ASSERT_OK_OR_RETURN(_memmgrMemUtilsScrubInitScheduleChannel(pGpu, pChannel)); + + // Determine classEngineID for SetObject usage + NV_ASSERT_OK_OR_RETURN(CliGetKernelChannelWithDevice(pChannel->pRsClient, + pChannel->deviceId, + pChannel->channelId, + &pFifoKernelChannel)); + + + NV_ASSERT_OK_OR_RETURN(kchannelGetClassEngineID_HAL(pGpu, + pFifoKernelChannel, + pChannel->engineObjectId, + &pChannel->classEngineID, + &classID, + &engineID)); + + NV_ASSERT_OK_OR_RETURN(_memmgrMemUtilsScrubInitRegisterCallback(pGpu, pChannel)); + + NV_ASSERT_OK_OR_RETURN(kfifoRmctrlGetWorkSubmitToken_HAL(pKernelFifo, + pChannel->hClient, + pChannel->channelId, + &pChannel->workSubmitToken)); + + // initialize the channel parameters (should be done by the parent object) + pChannel->channelPutOffset = 0; + + if (pChannel->pbCpuVA != NULL) + { + MEM_WR32(pChannel->pbCpuVA + pChannel->semaOffset, 0); + } + return NV_OK; +} diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/kernel/gpu/mem_mgr/method_notification.c nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/kernel/gpu/mem_mgr/method_notification.c --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/kernel/gpu/mem_mgr/method_notification.c 2023-10-25 20:21:12.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/kernel/gpu/mem_mgr/method_notification.c 2024-03-05 22:13:37.000000000 +0000 @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 1993-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 1993-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -286,7 +286,7 @@ NV_STATUS notifyFillNotifierGPUVATimestamp ( OBJGPU *pGpu, - NvHandle hClient, + RsClient *pClient, NvHandle hMemoryCtx, NvU64 NotifyGPUVABase, NvV32 Info32, @@ -302,14 +302,9 @@ NvU64 offset; NvU32 subdeviceInstance; NOTIFICATION *pNotifier; - RsClient *pClient; Device *pDevice; NV_STATUS status; - status = serverGetClientUnderLock(&g_resServ, hClient, &pClient); - if (status != NV_OK) - return status; - status = deviceGetByGpu(pClient, pGpu, NV_TRUE, &pDevice); if (status != NV_OK) return status; @@ -317,7 +312,7 @@ notifyGPUVA = NotifyGPUVABase + (Index * sizeof(NOTIFICATION)); // Memory context is required for mapping lookup - bFound = CliGetDmaMappingInfo(hClient, + bFound = CliGetDmaMappingInfo(pClient, RES_GET_HANDLE(pDevice), hMemoryCtx, notifyGPUVA, @@ -395,7 +390,7 @@ NV_STATUS notifyFillNotifierGPUVA ( OBJGPU *pGpu, - NvHandle hClient, + RsClient *pClient, NvHandle hMemoryCtx, NvU64 NotifyGPUVABase, NvV32 Info32, @@ -410,7 +405,7 @@ tmrGetCurrentTime(pTmr, &Time); return notifyFillNotifierGPUVATimestamp(pGpu, - hClient, + pClient, hMemoryCtx, NotifyGPUVABase, Info32, @@ -449,6 +444,9 @@ ) { NvNotification * pDebugNotifier = NULL; + MemoryManager *pMemoryManager = GPU_GET_MEMORY_MANAGER(pGpu); + KernelBus *pKernelBus = GPU_GET_KERNEL_BUS(pGpu); + TRANSFER_SURFACE surf = {0}; // // Check if there's already a CPU mapping we can use. If not, attempt to @@ -458,21 +456,34 @@ pDebugNotifier = (NvNotification *)((NvUPtr)pMemory->KernelVAddr); if (pDebugNotifier == NULL) { - pDebugNotifier = (NvNotification *) kbusMapRmAperture_HAL(pGpu, - pMemory->pMemDesc); - if (pDebugNotifier == NULL) - { - return NV_ERR_GENERIC; - } + surf.pMemDesc = pMemory->pMemDesc; + surf.offset = Index * sizeof(NvNotification); + + pDebugNotifier = + (NvNotification *) memmgrMemBeginTransfer(pMemoryManager, &surf, + sizeof(NvNotification), + TRANSFER_FLAGS_SHADOW_ALLOC); + NV_ASSERT_OR_RETURN(pDebugNotifier != NULL, NV_ERR_INVALID_STATE); + } + else + { + // + // If a CPU pointer has been passed by caller ensure that the notifier + // is in sysmem or in case it in vidmem, BAR access to the same is not + // blocked (for HCC) + // + NV_ASSERT_OR_RETURN( + memdescGetAddressSpace(pMemory->pMemDesc) == ADDR_SYSMEM || + !kbusIsBarAccessBlocked(pKernelBus), NV_ERR_INVALID_ARGUMENT); + pDebugNotifier = &pDebugNotifier[Index]; } - notifyFillNvNotification(pGpu, &pDebugNotifier[Index], Info32, Info16, + notifyFillNvNotification(pGpu, pDebugNotifier, Info32, Info16, CompletionStatus, NV_TRUE, Time); if (pMemory->KernelVAddr == NvP64_NULL) { - kbusUnmapRmAperture_HAL(pGpu, pMemory->pMemDesc, - (NvU8 **)&pDebugNotifier, NV_TRUE); + memmgrMemEndTransfer(pMemoryManager, &surf, sizeof(NvNotification), 0); } return NV_OK; @@ -541,7 +552,7 @@ NV_STATUS semaphoreFillGPUVATimestamp ( OBJGPU *pGpu, - NvHandle hClient, + RsClient *pClient, NvHandle hMemCtx, NvU64 SemaphoreGPUVABase, NvV32 ReleaseValue, @@ -551,6 +562,7 @@ ) { NvU64 semaphoreGPUVA; + NvU64 semaphoreGPUVAOffset; CLI_DMA_MAPPING_INFO *pDmaMappingInfo; NvU64 offset; NvU32 timeHi, timeLo; @@ -558,26 +570,24 @@ NvGpuSemaphore *pSemaphore; NvBool bBcState = gpumgrGetBcEnabledStatus(pGpu); NvBool bFound; - RsClient *pClient; Device *pDevice; NV_STATUS status; - status = serverGetClientUnderLock(&g_resServ, hClient, &pClient); - if (status != NV_OK) - return status; - status = deviceGetByGpu(pClient, pGpu, NV_TRUE, &pDevice); if (status != NV_OK) return status; - if (!portSafeAddU64(SemaphoreGPUVABase, - (NvU64) (Index * sizeof(NvGpuSemaphore)), + if (!portSafeMulU64((NvU64) Index, + (NvU64) sizeof(NvGpuSemaphore), + &semaphoreGPUVAOffset) || + !portSafeAddU64(SemaphoreGPUVABase, + semaphoreGPUVAOffset, &semaphoreGPUVA)) { return NV_ERR_INVALID_ARGUMENT; } - bFound = CliGetDmaMappingInfo(hClient, + bFound = CliGetDmaMappingInfo(pClient, RES_GET_HANDLE(pDevice), hMemCtx, semaphoreGPUVA, @@ -660,7 +670,7 @@ NV_STATUS semaphoreFillGPUVA ( OBJGPU *pGpu, - NvHandle hClient, + RsClient *pClient, NvHandle hMemCtx, NvU64 SemaphoreGPUVABase, NvV32 ReleaseValue, @@ -674,7 +684,7 @@ tmrGetCurrentTime(pTmr, &Time); return semaphoreFillGPUVATimestamp(pGpu, - hClient, + pClient, hMemCtx, SemaphoreGPUVABase, ReleaseValue, diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/kernel/gpu/mem_mgr/phys_mem_allocator/addrtree.c nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/kernel/gpu/mem_mgr/phys_mem_allocator/addrtree.c --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/kernel/gpu/mem_mgr/phys_mem_allocator/addrtree.c 2023-10-25 20:21:12.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/kernel/gpu/mem_mgr/phys_mem_allocator/addrtree.c 1970-01-01 00:00:00.000000000 +0000 @@ -1,2161 +0,0 @@ -/* - * SPDX-FileCopyrightText: Copyright (c) 2015-2021 NVIDIA CORPORATION & AFFILIATES. All rights reserved. - * SPDX-License-Identifier: MIT - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER - * DEALINGS IN THE SOFTWARE. - */ - -/*! - * @file addrtree.c - */ - -#include "gpu/mem_mgr/phys_mem_allocator/addrtree.h" -#include "gpu/mem_mgr/phys_mem_allocator/phys_mem_allocator_util.h" -#include "utils/nvprintf.h" -#include "utils/nvassert.h" -#include "nvport/nvport.h" -#include "nvmisc.h" - -// Returns if (x, x+y-1) contains (u, u+v-1) in one dimention -#define RANGE_CONTAINS(x, y, u, v) ((x <= u) && ((x + y - 1) >= (u + v - 1))) - -static PMA_PAGESTATUS pmaAddrtreeReadLevel(void *pMap, NvU32 levelNum, NvU64 frameNum, NvBool bReadAttrib); -static void _addrtreeUpdateAncestors(PMA_ADDRTREE *pTree, ADDRTREE_NODE *pNode, PMA_PAGESTATUS newStateMask); -static void _addrtreeConvertLevelFrameToNodeIndex(PMA_ADDRTREE *pTree, NvU32 levelNum, NvU64 frameNum, - ADDRTREE_NODE **ppNode, NvU32 *pIndex); -PMA_PAGESTATUS _pmaAddrtreeReadLevelAndSkipUnavailable(void *pMap, NvU32 levelNum, NvU64 frameNum, - PMA_PAGESTATUS searchState, NvBool bAllowFree, - NvU64 *pNumFramesToSkip, NvBool bReverse); - -static NvU64 alignUpToMod(NvU64 frame, NvU64 alignment, NvU64 mod) -{ - if ((frame & (alignment - 1)) <= mod) - return NV_ALIGN_DOWN(frame, alignment) + mod; - else - return NV_ALIGN_UP(frame, alignment) + mod; -} - -static NvU32 -addrtreeGetTreeLevel(NvU64 pageSize) -{ - NvU32 level = 0; - switch (pageSize) - { - case _PMA_64KB: level = 5; break; - // 128KB is supported in wrapper routines - case _PMA_2MB: level = 4; break; - case _PMA_512MB: level = 2; break; - default: break; - } - - NV_ASSERT(level != 0); - return level; -} - -static void -pmaAddrtreePrintLevel(ADDRTREE_LEVEL *pLevel) -{ - NvU32 i; - NvU32 mapIndex = MAP_IDX_ALLOC_PIN; - ADDRTREE_NODE *pNode = NULL; - - for (i = 0; i < pLevel->nodeCount; i++) - { - pNode = &pLevel->pNodeList[i]; - NV_PRINTF(LEVEL_INFO, "S[%d]=0x%llx A[%d]=0x%llx\n", i, - pNode->seeChild[mapIndex], i, pNode->state[mapIndex]); - - // In case compiler complains when the above print is compiled out - pNode = pNode; - mapIndex = mapIndex; - } -} - -void pmaAddrtreePrintTree(void *pMap, const char* str) -{ - NvU32 i; - PMA_ADDRTREE *pTree = (PMA_ADDRTREE *)pMap; - NV_PRINTF(LEVEL_INFO, "%s ==== \n", str); - - for (i = 0; i < pTree->levelCount - 1; i++) - { - NV_PRINTF(LEVEL_INFO, "Level [%d]\n", i); - pmaAddrtreePrintLevel(&pTree->levels[i]); - } - NV_PRINTF(LEVEL_INFO, "END printing Tree ==== \n"); -} - -static NvU64 -_makeMaskUpToIndex(NvU32 index) -{ - NV_ASSERT(index <= 64); - if (index == 64) - { - return NV_U64_MAX; - } - else - { - return (1ULL << index) - 1; - } -} - -void * -pmaAddrtreeInit -( - NvU64 numFrames, - NvU64 addrBase, - PMA_STATS *pPmaStats, - NvBool bProtected -) -{ - // - // Hardcoding this for now to get things started - // TODO: use more flexible configs - // - NvU32 levelSizes[] = {_TREE_2TB, _TREE_32GB, _TREE_512MB, _TREE_128MB, _TREE_2MB, _TREE_64KB}; - NvU32 levelCount = sizeof(levelSizes) / sizeof(levelSizes[0]); - //NV_PRINTF(LEVEL_INFO, "numFrames: 0x%llx, addrBase 0x%llx \n", numFrames, addrBase); - - NvU64 totalNodeCount, num2mbPages; - NvU32 i; - PMA_ADDRTREE *newTree; - NvU64 numFramesToAllocate; - - // PMA already ensures this - NV_ASSERT(NV_IS_ALIGNED(addrBase, PMA_GRANULARITY)); - - newTree = (PMA_ADDRTREE*)portMemAllocNonPaged((NvLength)sizeof(struct pma_addrtree)); - if (newTree == NULL) - { - return NULL; - } - portMemSet(newTree, 0, (NvLength)sizeof(*newTree)); - newTree->levels = NULL; - newTree->root = NULL; - - // Allocate the levels - newTree->levels = (ADDRTREE_LEVEL *)portMemAllocNonPaged((NvLength)(levelCount * sizeof(ADDRTREE_LEVEL))); - if (newTree->levels == NULL) - { - goto error; - } - portMemSet(newTree->levels, 0, (NvLength)(levelCount * sizeof(ADDRTREE_LEVEL))); - - newTree->levelCount = levelCount; - newTree->totalFrames = numFrames; - num2mbPages = numFrames / (_PMA_2MB >> PMA_PAGE_SHIFT); - - pPmaStats->numFreeFrames += newTree->totalFrames; - pPmaStats->num2mbPages += num2mbPages; - pPmaStats->numFree2mbPages += num2mbPages; - - newTree->bProtected = bProtected; - newTree->pPmaStats = pPmaStats; - - // - // Now pad the beginning of addrtree, and round down to the largest - // single page allocation supported so that its level will be aligned. - // The biggest single page is 512 MB currently. - // - newTree->numPaddingFrames = (addrBase - NV_ALIGN_DOWN64(addrBase, _PMA_512MB)) >> PMA_PAGE_SHIFT; - numFramesToAllocate = newTree->totalFrames + newTree->numPaddingFrames; - - // Allocate each level and calculate number of nodes needed - totalNodeCount = 0; - for (i = 0; i < levelCount; i++) - { - ADDRTREE_LEVEL *cur = &newTree->levels[i]; - cur->nodeCount = numFramesToAllocate >> (levelSizes[i] - PMA_PAGE_SHIFT); - cur->pageSizeShift = levelSizes[i]; - - // To be a tree, there needs to be one root node - if (i == 0 && cur->nodeCount != 0) - { - NV_PRINTF(LEVEL_ERROR, "Total memory is > 2TB. PMA Address Tree cannot account for this much.\n"); - goto error; - } - - // The 64KB level is a placeholder level which doesn't need to be allocated - if (i == levelCount - 1) - { - break; - } - - // Always allocate at least 1 node for each level and account for non-full nodes - if ((cur->nodeCount == 0) || (numFramesToAllocate % (1ULL << (levelSizes[i] - PMA_PAGE_SHIFT)) != 0)) - cur->nodeCount++; - - totalNodeCount += cur->nodeCount; - - //NV_PRINTF(LEVEL_INFO, "Level %d: nodeCount: %d, totalNodeCount: %d\n", i, cur->nodeCount, totalNodeCount); - } - - // Allocate all the nodes needed in a linear array - newTree->root = (ADDRTREE_NODE *)portMemAllocNonPaged((NvLength)(totalNodeCount * sizeof(ADDRTREE_NODE))); - if (newTree->root == NULL) - { - goto error; - } - portMemSet(newTree->root, 0, (NvLength)(totalNodeCount * sizeof(ADDRTREE_NODE))); - newTree->root->parent = NULL; - - NvU32 curIdx = 0; - - // Skip the last level because we don't really need to allocate 64K level - for (i = 0; i < levelCount - 1; i++) - { - NvU64 nextLevelStart = curIdx + newTree->levels[i].nodeCount; - // - // The maxChildren a node can have is a factor of - // the difference in page sizes between levels - // - NvU32 maxChildren = 1U<<(levelSizes[i] - levelSizes[i + 1]); - newTree->levels[i].maxFramesPerNode = maxChildren; - - //NV_PRINTF(LEVEL_INFO, "Level %d: maxChildren per node: %d\n", i, maxChildren); - - NvU32 j; - for (j = 0; j < newTree->levels[i].nodeCount; j++) - { - ADDRTREE_NODE *curNode = &newTree->root[curIdx]; - - // Register first node in the level structure - if (j == 0) - { - newTree->levels[i].pNodeList = curNode; - } - - // Populate curNode - curNode->level = i; - curNode->frame = maxChildren * j; - - // All nodes before this node must have maxChildren - NvU64 childrenNodeIdx = nextLevelStart + j * maxChildren; - curNode->children = &newTree->root[childrenNodeIdx]; - - // The last node may not have maxChildren, calculate how many it does have - // OK to just cast because we know numChildren must be at most 64 - NvU32 lastNodeNumValidChildren = (NvU32)(newTree->levels[i+1].nodeCount - (j * maxChildren)); - NvU32 numValidChildren = 0; - - // - // If this is not the last node in a level, - // then it must have maxChildren. - // Otherwise calculate how many it does have. - // - if (j != newTree->levels[i].nodeCount - 1) - { - curNode->numChildren = maxChildren; - numValidChildren = maxChildren; - } - else - { - curNode->numChildren = maxChildren; - numValidChildren = lastNodeNumValidChildren; - - // - // Mark invalid children as allocated so that reads of partial nodes - // do not return that they are available - // - NvU64 invalidChildrenMask = _makeMaskUpToIndex(maxChildren) & ~_makeMaskUpToIndex(lastNodeNumValidChildren); - curNode->state[MAP_IDX_ALLOC_PIN] = invalidChildrenMask; - _addrtreeUpdateAncestors(newTree, curNode, STATE_PIN); - } - - // Populate curNode->children[*]->parent, except for the last level - if (i != levelCount - 2) - { - NvU32 k; - - for (k = 0; k < numValidChildren; k++) - { - ADDRTREE_NODE *curChild = &curNode->children[k]; - curChild->parent = curNode; - } - } - - curIdx++; - } - } - - return (void *)newTree; - -error: - pmaAddrtreeDestroy(newTree); - return NULL; -} - -void pmaAddrtreeDestroy(void *pMap) -{ - NvU64 num2mbPages; - PMA_ADDRTREE *pTree = (PMA_ADDRTREE *)pMap; - NV_ASSERT_OR_RETURN_VOID(pTree != NULL); - - num2mbPages = pTree->totalFrames / (_PMA_2MB >> PMA_PAGE_SHIFT); - pTree->pPmaStats->numFreeFrames -= pTree->totalFrames; - pTree->pPmaStats->numFree2mbPages -= num2mbPages; - - portMemFree(pTree->root); - portMemFree(pTree->levels); - - portMemFree(pTree); -} - -static void -_addrtreeConvertFrame(PMA_ADDRTREE *pTree, NvU32 sourceLevel, NvU64 sourceFrame, NvU32 targetLevel, NvU64 *pTargetFrame) -{ - // Converting up the tree, frame number goes down - if (sourceLevel > targetLevel) - { - *pTargetFrame = sourceFrame >> (pTree->levels[targetLevel+1].pageSizeShift - pTree->levels[sourceLevel+1].pageSizeShift); - } - else - { - *pTargetFrame = sourceFrame << (pTree->levels[sourceLevel+1].pageSizeShift - pTree->levels[targetLevel+1].pageSizeShift); - } -} - -// -// Given a node and index into its children array, whether this node is -// on the target level, the current accumulated status, and the current -// valid status mask, read the status of this node index and return -// - The remaining mask of children that will still need to be -// read to determine the state at a lower level of the tree in -// pStatusMask -// - The accumulated status combined with this node index's status -// -// To read the effective value of a node, callers must start with their -// desired status mask, call getNodeIndexStatus, and use the returned -// status mask to know what states still need to be read at the -// next level down in the tree. -// -// If statusMask is 0 upon return, reading children will give no more information -// That is, shouldCheckChildren == (*pStatusMask != 0) -// -// If the caller wants to keep reading status downwards in the tree, it must -// call getNodeIndexStatus with bIsTargetLevel = NV_FALSE. Here is pseudocode -// for reading a node: -// *pCumulativeStatus = 0; -// *pStatusMask = MAP_MASK; -// while (!targetLevel) { -// getNodeIndexStatus(node, index, NV_FALSE, pStatusMask, pCumulativeStatus); -// // increment while condition, typically the following: -// if (!shouldCheckChildren(stateMask)) -// { -// // do logic -// goto exit; -// } -// } -// -// // At target level -// getNodeIndexStatus(node, index, NV_TRUE, pStatusMask, pCumulativeStatus); -// -static void -getNodeIndexStatus -( - ADDRTREE_NODE *node, - NvU32 index, - NvBool bIsTargetLevel, - PMA_PAGESTATUS *pStatusMask, - PMA_PAGESTATUS *pCumulativeStatus -) -{ - PMA_PAGESTATUS curStatusMask = *pStatusMask; - PMA_PAGESTATUS nextStatusMask = 0; - NvU64 state = 0; - NvU32 i; - - NV_ASSERT(index < node->numChildren); - - for (i = 0; i < PMA_BITS_PER_PAGE; i++) - { - if (curStatusMask & (NVBIT(i))) - { - if (node->seeChild[i] & NVBIT64(index)) - { - nextStatusMask |= NVBIT64(i); - } - - // Assert that either state or seeChild is set, not both - NV_ASSERT(((node->seeChild[i] & node->state[i]) & (NVBIT64(index))) == 0); - - // - // But state does need to be accurate and returned as PMA_PAGESTATUS - // seeChild must be checked to get an accurate state - // - if ((node->state[i] | node->seeChild[i]) & (NVBIT64(index))) - { - state |= NVBIT64(i); - } - } - } - - //NV_PRINTF(LEVEL_ERROR, "curStatusMask=0x%llx, nextStatusMask=0x%llx, index=0x%x, state=0x%llx\n", - // (NvU64)curStatusMask, nextStatusMask, index, state); - - *pStatusMask = nextStatusMask; - - if (bIsTargetLevel) - { - *pCumulativeStatus |= state; - } - else - { - *pCumulativeStatus |= state & ~nextStatusMask; - } -} - -static NvBool -shouldCheckChildren(PMA_PAGESTATUS statusMask) -{ - return statusMask != 0; -} - -// This function returns if the current node holds valid information. -// If not, returns the effective state of this node -static NvBool -_addrtreeNodeValid -( - PMA_ADDRTREE *pTree, - ADDRTREE_NODE *node, - PMA_PAGESTATUS *pFoundState -) -{ - ADDRTREE_NODE *n = pTree->root; - NvU64 newFrame = 0; - NvU32 newIndex = 0; - *pFoundState = STATE_FREE; - PMA_PAGESTATUS stateMask = MAP_MASK; // check all states TODO - - //NV_PRINTF(LEVEL_INFO, "Source level=%d frame=0x%llx.\n", - // node->level, node->frame); - - while(n->level != node->level) - { - _addrtreeConvertFrame(pTree, node->level, node->frame, n->level, &newFrame); - newIndex = (NvU32)(newFrame - n->frame); - - getNodeIndexStatus(n, newIndex, NV_FALSE, &stateMask, pFoundState); - - if (!shouldCheckChildren(stateMask)) - { - return NV_FALSE; - } - - // Go to the right children to continue walking down - n = &n->children[newIndex]; - } - - return NV_TRUE; - -} - -static NvU64 -_addrtreeComputeMask(ADDRTREE_NODE *node, NvU64 frameStart, NvU64 numFrames) -{ - NV_ASSERT(node->numChildren <= 64); - - NvU64 mask = _makeMaskUpToIndex(node->numChildren); - - // If node is contained within the range, return a full mask - if (RANGE_CONTAINS(frameStart, numFrames, node->frame, node->numChildren)) - { - //NV_PRINTF(LEVEL_ERRORS, "frameStart=0x%llx, numFrames=0x%llx, node: start=0x%llx, num=0x%x, mask=0x%llx\n", - // frameStart, numFrames, node->frame, node->numChildren, mask); - return mask; - } - else - { - // If the node doesn't cover the start, unset the beginning bits - if (frameStart > node->frame) - { - mask &= (~_makeMaskUpToIndex((NvU32)(frameStart - node->frame))); - } - - // If the node doesn't cover the end, unset the last bits - if (frameStart + numFrames < node->frame + node->numChildren) - { - mask &= (_makeMaskUpToIndex((NvU32)(frameStart + numFrames - node->frame))); - } - } - return mask; -} - -// -// For the given state, for the mask of a node's children, -// the function returns -// -// NV_TRUE if the mask is available -// NV_FALSE if the mask is not available -// and the last child index which does not satisfy the given state -// -static NvBool -_addrtreeNodeMaskAvailable( - ADDRTREE_NODE *node, - NvU64 mask, - PMA_PAGESTATUS state, - NvBool bReverse, - NvU64 *pDiff -) -{ - NvU64 allocated = 0; - NvU32 i; - - for (i = 0; i < PMA_BITS_PER_PAGE; i++) - { - // - // allocated tracks which pages are not available. - // We are looking for pages in free or state status. - // Pages in state status are available, so exclude them. - // - if ((NVBIT(i) & state) == 0) - { - // Note that once we see a seeChild being set, we would - // count that as allocated because some children are allocated - allocated |= node->seeChild[i]; - allocated |= node->state[i]; - } - } - - allocated &= mask; - - if (!bReverse) - { - // - // Skip past all unavailable and return last child index - // which does not satisfy the given state - // This will underflow for allocated == 0, but in that case, - // *pDiff should not be read anyway - // - *pDiff = 64 - portUtilCountLeadingZeros64(allocated) - 1; - } - else - { - // Return the first child index that doesn't satisfy given state - *pDiff = portUtilCountTrailingZeros64(allocated); - } - - return (allocated == 0); -} - -// This function returns the node on a specific level that contains the frame -// The node may or may not contain valid information. That is handled later. -static NvU64 -_addrtreeGetNodeIdx(PMA_ADDRTREE *pTree, NvU32 level, NvU64 frame) -{ - ADDRTREE_LEVEL *treeLevel = &pTree->levels[level]; - - // Current level's frame number should be the same as next level's node number - NV_ASSERT(frame < pTree->levels[level+1].nodeCount); - - return (frame / (treeLevel->maxFramesPerNode)); -} - -// -// Optimization: enable scanning functions to skip over fully allocated -// parent nodes with _pmaAddrtreeReadLevelAndSkipUnavailable -// -// For a given level and startFrame, return the number of frames to skip on the -// given level based on the parent's allocation state. -// Add this number to skip to the startFrame to get the next node which is not -// fully allocated. -// -PMA_PAGESTATUS -_pmaAddrtreeReadLevelAndSkipUnavailable -( - void *pMap, - NvU32 levelNum, - NvU64 frameNum, - PMA_PAGESTATUS searchState, - NvBool bAllowFree, - NvU64 *pNumFramesToSkip, - NvBool bReverse -) -{ - NvU32 index; - ADDRTREE_NODE *pNode; - PMA_ADDRTREE *pTree = (PMA_ADDRTREE *)pMap; - ADDRTREE_NODE *n = pTree->root; - NvU64 newFrame = 0; - NvU32 newIndex; - PMA_PAGESTATUS status = STATE_FREE; - PMA_PAGESTATUS stateMask = MAP_MASK; - - _addrtreeConvertLevelFrameToNodeIndex(pTree, levelNum, frameNum, &pNode, &index); - - while (n->level != pNode->level) - { - _addrtreeConvertFrame(pTree, pNode->level, pNode->frame, n->level, &newFrame); - newIndex = (NvU32)(newFrame - n->frame); - - getNodeIndexStatus(n, newIndex, NV_FALSE, &stateMask, &status); - - if (!shouldCheckChildren(stateMask)) - { - // - // There's no need to scan further down. - // Return the number of frames to skip over on the target level - // in order to skip over this n->level ancestor. - // - - NvBool bWrongState = (status != searchState) && !(bAllowFree && (status == STATE_FREE)); - - if (bWrongState) - { - // - // This node is fully allocated. - // Return the number of frames of the target level we should skip. - // - NvU64 targetFrameStartForThisNode; - NvU64 numTargetFramesPerAncestor; - - _addrtreeConvertFrame(pTree, n->level, newFrame, levelNum, &targetFrameStartForThisNode); - _addrtreeConvertFrame(pTree, n->level, 1ULL, levelNum, &numTargetFramesPerAncestor); - - if (!bReverse) - *pNumFramesToSkip = numTargetFramesPerAncestor - (frameNum - targetFrameStartForThisNode); - else - *pNumFramesToSkip = frameNum - targetFrameStartForThisNode + 1; - } else { - // - // This node is in a state we're searching for. - // The caller will store off one frame of the target level - // - *pNumFramesToSkip = 1; - } - - goto exit; - } - - // Go to the right children to continue walking down - n = &n->children[newIndex]; - } - - *pNumFramesToSkip = 1; - - // Extract the final value from this pNode - getNodeIndexStatus(pNode, index, NV_TRUE, &stateMask, &status); - -exit: - NV_ASSERT(*pNumFramesToSkip > 0); - return status; -} - -// -// For the given state, between frameStart and (frameStart + numFrames - 1) -// for a given level, this function returns -// -// NV_TRUE if the range is available -// NV_FALSE if the range is not available -// and the frame number of the last frame which does not -// satisfy the given state in the variable pDiff -// -// XXX: Caution! This will not properly pick up nodes only in state `state` -// If it were used for discontig scanning, it would be wrong! -// -static NvBool -_pmaAddrtreeAvailable -( - PMA_ADDRTREE *pTree, - NvU32 level, - PMA_PAGESTATUS state, - NvU64 frameStart, - NvU64 numFrames, - NvU64 *pDiff -) -{ - NvU64 i, startIdx, endIdx, childrenMask; - PMA_PAGESTATUS foundState; - NvU64 nodeIndexDiff; - ADDRTREE_NODE *node; - - NV_ASSERT(level != 0); // TODO handle the root node case - //NV_PRINTF(LEVEL_INFO, "level=%d, frameStart=0x%llx, numFrames=%llx\n", - // level, frameStart, numFrames); - - startIdx = _addrtreeGetNodeIdx(pTree, level, frameStart); - endIdx = _addrtreeGetNodeIdx(pTree, level, (frameStart + numFrames - 1)); - - //NV_PRINTF(LEVEL_INFO, "startIdx = %llx, endIdx = 0x%llx\n", startIdx, endIdx); - - // Begin checking from the end so that we can skip the most frames in the overall search - for (i = endIdx; i >= startIdx; i--) - { - // Protect against underflow - if (i == (NvU64)-1) break; - - //NV_PRINTF(LEVEL_INFO, "IN LOOP: i=0x%llx, startIdx=%llx\n", i, startIdx); - node = &(pTree->levels[level].pNodeList[i]); - if (_addrtreeNodeValid(pTree, node, &foundState)) - { - childrenMask = _addrtreeComputeMask(node, frameStart, numFrames); - - if (!_addrtreeNodeMaskAvailable(node, childrenMask, state, NV_FALSE, &nodeIndexDiff)) - { - *pDiff = node->frame + nodeIndexDiff; - return NV_FALSE; - } - } - else - { - //NV_PRINTF(LEVEL_INFO, "IN LOOP: Node is INVALID. allocated?-%d\n", - // (NvU32)state); - if ((foundState != STATE_FREE) && (foundState != state)) - { - // This node is completely allocated. - // Return the frame number of the last frame in this node - *pDiff = node->frame + node->numChildren - 1; - return NV_FALSE; - } - else - { - // - // This node is completely free or in a state we're looking for, - // continue checking - // - continue; - } - } - } - - return NV_TRUE; -} - -// -// For the given state, between frameStart and (frameStart + numFrames - 1) -// for a given level, this function returns -// -// NV_TRUE if the range is available -// NV_FALSE if the range is not available -// and the frame number of the first frame which does not -// satisfy the given state in the variable pDiff -// -// XXX: Caution! This will not properly pick up nodes only in state `state` -// If it were used for discontig scanning, it would be wrong! -// -static NvBool -_pmaAddrtreeAvailableReverse -( - PMA_ADDRTREE *pTree, - NvU32 level, - PMA_PAGESTATUS state, - NvU64 frameStart, - NvU64 numFrames, - NvU64 *pDiff -) -{ - NvU64 i, startIdx, endIdx, childrenMask; - PMA_PAGESTATUS foundState; - NvU64 nodeIndexDiff; - ADDRTREE_NODE *node; - - NV_ASSERT(level != 0); // TODO handle the root node case - - startIdx = _addrtreeGetNodeIdx(pTree, level, frameStart); - endIdx = _addrtreeGetNodeIdx(pTree, level, (frameStart + numFrames - 1)); - - // For reverse alloc, begin checking from the start so that we can skip the most frames in the overall search - for (i = startIdx; i <= endIdx; i++) - { - node = &(pTree->levels[level].pNodeList[i]); - if (_addrtreeNodeValid(pTree, node, &foundState)) - { - childrenMask = _addrtreeComputeMask(node, frameStart, numFrames); - - if (!_addrtreeNodeMaskAvailable(node, childrenMask, state, NV_TRUE, &nodeIndexDiff)) - { - *pDiff = node->frame + nodeIndexDiff; - return NV_FALSE; - } - } - else - { - if ((foundState != STATE_FREE) && (foundState != state)) - { - // This node is completely allocated. - // Return the frame number of the first frame in this node - *pDiff = node->frame; - return NV_FALSE; - } - else - { - // - // This node is completely free or in a state we're looking for, - // continue checking - // - continue; - } - } - } - - return NV_TRUE; -} - -static NvBool -_pmaAddrtreeContigSearchLoop -( - PMA_ADDRTREE *pTree, - NvU32 level, - PMA_PAGESTATUS state, - NvU64 addrBase, - NvU64 localStart, - NvU64 localEnd, - NvU64 numFrames, - NvU64 frameAlignment, - NvU64 *freeList -) -{ - NvBool found = NV_FALSE; - NvU64 freeStart; - NvU64 diff; - PMA_PAGESTATUS startStatus, endStatus; - - if ((state != STATE_FREE) && (state != STATE_UNPIN)) - { - NV_PRINTF(LEVEL_INFO, "Scanning for state %d is not supported\n", state); - return found; - } - - freeStart = localStart; - while (!found) - { - NvU64 endFrame = freeStart + numFrames - 1; - NvU64 framesToSkip = 0; - - if (endFrame > localEnd) - { - // freeStart + numFrames too close to local search end. Re-starting search - break; - } - - // - // Read endStatus first so we don't have to waste time traversing the - // tree again to read startStatus if endStatus is not even usable - // - endStatus = _pmaAddrtreeReadLevelAndSkipUnavailable(pTree, level, endFrame, state, NV_TRUE, &framesToSkip, NV_FALSE); - - if (framesToSkip > 1) { - freeStart = NV_ALIGN_UP(endFrame + framesToSkip, frameAlignment); - NV_ASSERT(freeStart != 0); - continue; - } - - startStatus = _pmaAddrtreeReadLevelAndSkipUnavailable(pTree, level, freeStart, state, NV_TRUE, &framesToSkip, NV_FALSE); - - if (framesToSkip > 1) { - freeStart += NV_ALIGN_UP(framesToSkip, frameAlignment); - NV_ASSERT(freeStart != 0); - continue; - } - - if ((endStatus == STATE_FREE) || (endStatus == state)) - { - if ((startStatus == STATE_FREE) || (startStatus == state)) - { - if (_pmaAddrtreeAvailable(pTree, level, state, freeStart, numFrames, &diff)) - { - found = NV_TRUE; - // Substract off padding when returning - *freeList = addrBase + ((freeStart << pTree->levels[level+1].pageSizeShift) - - (pTree->numPaddingFrames << PMA_PAGE_SHIFT)); - //NV_PRINTF(LEVEL_INFO, "found! 0x%llx\n", freeStart); - } - else - { - //NV_PRINTF(LEVEL_INFO, "Frame number of allocated frame = 0x%llx\n", - // diff); - // - // Find the next aligned free frame and set it as the start - // frame for next iteration's scan. - // - freeStart = NV_ALIGN_UP(diff + 1, frameAlignment); - NV_ASSERT(freeStart != 0); - } - } - else - { - // Start point isn't free, so bump to check the next aligned frame - freeStart += frameAlignment; - } - } - else - { - // - // End point isn't usable, so jump to after the end to check again - // However, align the new start point properly before next iteration. - // - freeStart += NV_ALIGN_UP(numFrames, frameAlignment); - } - } - - return found; -} - -static NvBool -_pmaAddrtreeContigSearchLoopReverse -( - PMA_ADDRTREE *pTree, - NvU32 level, - PMA_PAGESTATUS state, - NvU64 addrBase, - NvU64 localStart, - NvU64 localEnd, - NvU64 numFrames, - NvU64 frameAlignment, - NvU64 *freeList -) -{ - NvBool found = NV_FALSE; - NvU64 freeStart; - NvU64 diff; - PMA_PAGESTATUS startStatus, endStatus; - - if ((state != STATE_FREE) && (state != STATE_UNPIN)) - { - NV_PRINTF(LEVEL_INFO, "Scanning for state %d is not supported\n", state); - return found; - } - - freeStart = localEnd + 1 - numFrames; // First frame from end able to accommodate num_frames allocation. - freeStart = NV_ALIGN_DOWN(freeStart, frameAlignment); - while (!found) - { - NvU64 framesToSkip = 0; - - if (freeStart < localStart || (NvS64)freeStart < 0) // Account for underflow - { - // freeStart too close to local search start. Re-starting search - break; - } - - // - // For reverse allocation, read startStatus first so we don't have to waste time - // traversing the tree again to read endStatus if startStatus is not even usable - // - startStatus = _pmaAddrtreeReadLevelAndSkipUnavailable(pTree, level, freeStart, state, NV_TRUE, &framesToSkip, NV_TRUE); - if (framesToSkip > 1) { - NvU64 newEndFrame = freeStart - framesToSkip; - freeStart = newEndFrame + 1 - numFrames; - freeStart = NV_ALIGN_DOWN(freeStart, frameAlignment); - continue; - } - - endStatus = _pmaAddrtreeReadLevelAndSkipUnavailable(pTree, level, freeStart + numFrames - 1, state, NV_TRUE, &framesToSkip, NV_TRUE); - if (framesToSkip > 1) { - freeStart -= NV_ALIGN_UP(framesToSkip, frameAlignment); - continue; - } - - if ((startStatus == STATE_FREE) || (startStatus == state)) - { - if ((endStatus == STATE_FREE) || (endStatus == state)) - { - if (_pmaAddrtreeAvailableReverse(pTree, level, state, freeStart, numFrames, &diff)) - { - found = NV_TRUE; - // Subtract off padding when returning - *freeList = addrBase + ((freeStart << pTree->levels[level+1].pageSizeShift) - - (pTree->numPaddingFrames << PMA_PAGE_SHIFT)); - //NV_PRINTF(LEVEL_INFO, "found! 0x%llx\n", freeStart); - } - else - { - //NV_PRINTF(LEVEL_INFO, "Frame number of allocated frame = 0x%llx\n", - // diff); - // - // Find the next aligned free frame and set it as the end - // frame for next iteration's scan. - // - freeStart = NV_ALIGN_DOWN(diff - numFrames, frameAlignment); - } - } - else - { - // Start point isn't free, so bump to check the next aligned frame - freeStart -= frameAlignment; - } - } - else - { - // - // End point isn't usable, so jump to after the end to check again - // However, align the new start point properly before next iteration. - // - freeStart -= NV_ALIGN_UP(numFrames, frameAlignment); - } - } - - return found; -} - -static NV_STATUS -_pmaAddrtreeScanContiguous -( - void *pMap, - NvU64 addrBase, - NvU64 rangeStart, - NvU64 rangeEnd, - NvU64 numPages, - NvU64 *freeList, - NvU32 pageSize, - NvU64 alignment, - NvU64 *numPagesAlloc, - NvBool bSkipEvict, - NvBool bReverseAlloc -) -{ - NvU64 localStart, localEnd, frameAlignment; - NvBool found; - NvU32 level; - PMA_ADDRTREE *pTree = (PMA_ADDRTREE *)pMap; - - // This requirement is ensured in PMA - NV_ASSERT(alignment >= pageSize && portUtilIsPowerOfTwo(alignment)); - - *numPagesAlloc = 0; - - // Only focus on the level above the pageSize level. Children are ignored. - level = addrtreeGetTreeLevel(pageSize); - if (level == 0) - { - NV_PRINTF(LEVEL_ERROR, "address tree cannot handle page size 0x%x\n", - pageSize); - return NV_ERR_INVALID_ARGUMENT; - } - - frameAlignment = alignment / pageSize; - - // Handle restricted allocations - if (rangeStart != 0 || rangeEnd != 0) - { - rangeStart += (pTree->numPaddingFrames << PMA_PAGE_SHIFT); - rangeEnd += (pTree->numPaddingFrames << PMA_PAGE_SHIFT); - localStart = NV_ALIGN_UP64(rangeStart, alignment) >> pTree->levels[level].pageSizeShift; - localEnd = NV_MIN(rangeEnd >> pTree->levels[level].pageSizeShift, pTree->levels[level].nodeCount - 1); - } - else - { - localStart = NV_ALIGN_UP64(pTree->numPaddingFrames << PMA_PAGE_SHIFT, alignment) >> pTree->levels[level].pageSizeShift; - localEnd = pTree->levels[level].nodeCount - 1; - } - - //NV_PRINTF(LEVEL_INFO, "Scanning level %d with addrBase 0x%llx in frame range 0x%llx..0x%llx, " - // "pages to allocate 0x%llx (pageSize=0x%x, alignment=0x%x)\n", - // (level - 1), addrBase, localStart, localEnd, numPages, pageSize, alignment); - if (!bReverseAlloc) - { - found = _pmaAddrtreeContigSearchLoop(pTree, level - 1, STATE_FREE, addrBase, localStart, localEnd, - numPages, frameAlignment, freeList); - } - else - { - found = _pmaAddrtreeContigSearchLoopReverse(pTree, level - 1, STATE_FREE, addrBase, localStart, localEnd, - numPages, frameAlignment, freeList); - } - - if (found) - { - *numPagesAlloc = numPages; - return NV_OK; - } - - if (bSkipEvict) - { - return NV_ERR_NO_MEMORY; - } - - // Loop back to the beginning and continue searching for evictable pages - if (!bReverseAlloc) - { - found = _pmaAddrtreeContigSearchLoop(pTree, level - 1, STATE_UNPIN, addrBase, localStart, localEnd, - numPages, frameAlignment, freeList); - } - else - { - found = _pmaAddrtreeContigSearchLoopReverse(pTree, level - 1, STATE_UNPIN, addrBase, localStart, localEnd, - numPages, frameAlignment, freeList); - } - if (found) - return NV_ERR_IN_USE; - else - return NV_ERR_NO_MEMORY; -} - -// -// This function wraps the real _pmaAddrtreeScanContiguous -// to allow addrtree to scan for 128KB page size -// -NV_STATUS -pmaAddrtreeScanContiguous -( - void *pMap, - NvU64 addrBase, - NvU64 rangeStart, - NvU64 rangeEnd, - NvU64 numPages, - NvU64 *freeList, - NvU32 pageSize, - NvU64 alignment, - NvU64 *numPagesAlloc, - NvBool bSkipEvict, - NvBool bReverseAlloc -) -{ - if (NV_UNLIKELY(pageSize == _PMA_128KB)) { - // - // Call the contig function with twice as many 64KB frames, - // and cut in half the number of allocated frames. - // Contig allocations are all or nothing so the number of - // allocated frames cannot be odd. - // - NV_STATUS status; - - status = _pmaAddrtreeScanContiguous( - pMap, - addrBase, - rangeStart, - rangeEnd, - numPages * 2, - freeList, - _PMA_64KB, - alignment, - numPagesAlloc, - bSkipEvict, - bReverseAlloc); - - *numPagesAlloc /= 2; - - return status; - } - else - { - return _pmaAddrtreeScanContiguous( - pMap, - addrBase, - rangeStart, - rangeEnd, - numPages, - freeList, - pageSize, - alignment, - numPagesAlloc, - bSkipEvict, - bReverseAlloc); - } -} - -static NvU64 -_pmaAddrtreeDiscontigSearchLoop -( - PMA_ADDRTREE *pTree, - NvU32 level, - PMA_PAGESTATUS state, - NvU64 addrBase, - NvU64 localStart, - NvU64 localEnd, - NvU64 numFrames, - NvU64 frameAlignment, - NvU64 *freeList, - NvBool bReverseAlloc -) -{ - NvU64 found = 0; - NvU64 freeStart; - PMA_PAGESTATUS startStatus; - - if ((state != STATE_FREE) && (state != STATE_UNPIN)) - { - NV_PRINTF(LEVEL_INFO, "Scanning for state %d is not supported\n", state); - return found; - } - - freeStart = !bReverseAlloc ? localStart : localEnd; - - // - // We only need one frame at a time on this level, - // so we can skip much of the frame logic - // - while (found != numFrames) - { - NvU64 framesToSkip = 0; - - if (freeStart > localEnd || freeStart < localStart || (NvS64)freeStart < 0) break; - - // - // For discontig, we MUST only pick up the exact state. - // Otherwise we give away pages for eviction that we already stored off to be allocated. - // - startStatus = _pmaAddrtreeReadLevelAndSkipUnavailable(pTree, level, freeStart, state, NV_FALSE, &framesToSkip, bReverseAlloc); - - if (startStatus == state) - { - // Substract off padding when returning - freeList[found++] = addrBase + ((freeStart << pTree->levels[level+1].pageSizeShift) - - (pTree->numPaddingFrames << PMA_PAGE_SHIFT)); - } - freeStart = !bReverseAlloc ? (freeStart + framesToSkip) : (freeStart - framesToSkip); - } - - return found; -} - -static NV_STATUS -_pmaAddrtreeScanDiscontiguous -( - void *pMap, - NvU64 addrBase, - NvU64 rangeStart, - NvU64 rangeEnd, - NvU64 numPages, - NvU64 *freeList, - NvU32 pageSize, - NvU64 alignment, - NvU64 *numPagesAlloc, - NvBool bSkipEvict, - NvBool bReverseAlloc -) -{ - NvU64 localStart, localEnd; - NvU64 foundFree; - NvU64 foundEvictable; - NvU32 level; - PMA_ADDRTREE *pTree = (PMA_ADDRTREE *)pMap; - - // This requirement is ensured in PMA - NV_ASSERT(alignment == pageSize); - - // Only focus on the level above the pageSize level. Children are ignored. - level = addrtreeGetTreeLevel(pageSize); - if (level == 0) - { - NV_PRINTF(LEVEL_ERROR, "address tree cannot handle page size 0x%x\n", - pageSize); - return NV_ERR_INVALID_ARGUMENT; - } - - // Handle restricted allocations - if (rangeStart != 0 || rangeEnd != 0) - { - // Embedded % requires special handling. - NV_ASSERT_OR_ELSE_STR(rangeStart % pageSize == 0, - "rangeStart %% pageSize == 0", /*do nothing*/); - NV_ASSERT_OR_ELSE_STR((rangeEnd + 1) % pageSize == 0, - "(rangeEnd + 1) %% pageSize == 0", /*do nothing*/); - - rangeStart += (pTree->numPaddingFrames << PMA_PAGE_SHIFT); - rangeEnd += (pTree->numPaddingFrames << PMA_PAGE_SHIFT); - localStart = NV_ALIGN_UP(rangeStart, alignment) >> pTree->levels[level].pageSizeShift; - localEnd = NV_MIN(rangeEnd >> pTree->levels[level].pageSizeShift, pTree->levels[level].nodeCount - 1); - } - else - { - localStart = NV_ALIGN_UP64(pTree->numPaddingFrames << PMA_PAGE_SHIFT, alignment) >> pTree->levels[level].pageSizeShift; - localEnd = pTree->levels[level].nodeCount - 1; - } - - //NV_PRINTF(LEVEL_INFO, "Scanning level %d with addrBase 0x%llx in frame range 0x%llx..0x%llx, " - // "pages to allocate 0x%llx (pageSize=0x%x, alignment=0x%x)\n", - // (level - 1), addrBase, localStart, localEnd, numPages, pageSize, alignment); - - foundFree = _pmaAddrtreeDiscontigSearchLoop(pTree, level - 1, STATE_FREE, addrBase, localStart, localEnd, - numPages, alignment, freeList, bReverseAlloc); - - - // numPagesAlloc must be set for partial allocations - *numPagesAlloc = foundFree; - - if (foundFree == numPages) - { - return NV_OK; - } - else if (bSkipEvict) - { - return NV_ERR_NO_MEMORY; - } - - // - // Loop back to the beginning and continue searching for evictable pages - // This next search picks up only evictable pages and not free pages - // - foundEvictable = _pmaAddrtreeDiscontigSearchLoop(pTree, level - 1, STATE_UNPIN, addrBase, localStart, localEnd, - (numPages - foundFree), alignment, (freeList + foundFree), bReverseAlloc); - - if ((foundFree + foundEvictable) == numPages) - return NV_ERR_IN_USE; - else - return NV_ERR_NO_MEMORY; -} - -// -// This function wraps the real _pmaAddrtreeScanDiscontiguous -// to allow addrtree to scan for 128KB page size -// -NV_STATUS -pmaAddrtreeScanDiscontiguous -( - void *pMap, - NvU64 addrBase, - NvU64 rangeStart, - NvU64 rangeEnd, - NvU64 numPages, - NvU64 *freeList, - NvU32 pageSize, - NvU64 alignment, - NvU64 *numPagesAlloc, - NvBool bSkipEvict, - NvBool bReverseAlloc -) -{ - if (NV_UNLIKELY(pageSize == _PMA_128KB)) { - NV_STATUS status = NV_OK; - NvU64 i; - NvU64 localNumPagesAlloc; - *numPagesAlloc = 0; - - if (rangeEnd == 0) { - NV_ASSERT(rangeStart == 0); - rangeEnd = ((PMA_ADDRTREE *)pMap)->totalFrames << PMA_PAGE_SHIFT; - } - - for (i = 0; i < numPages; i++) { - // - // Only call the contig function because we need the two frames to be - // contiguous. - // Alignment only needs to be aligned to 64KB and power of 2, - // so it is ok to pass through even if it is 128KB - // - status = _pmaAddrtreeScanContiguous( - pMap, - addrBase, - rangeStart, - rangeEnd, - 2, - freeList + i, - _PMA_64KB, - alignment, - &localNumPagesAlloc, - bSkipEvict, - bReverseAlloc); - - // Give back the first of every two 64KB frames - *numPagesAlloc += localNumPagesAlloc / 2; - - if (status != NV_OK) - { - return status; - } - - if (!bReverseAlloc) - rangeStart = freeList[i] + _PMA_128KB; - else - { - rangeEnd = freeList[i] - 1; - if (rangeEnd < rangeStart || (NvS64)rangeEnd < 0) - { - // Extended the current implementation to reverse alloc here but - // isn't this logic incorrect for tryEvict case? As we are closing - // off the region for tryEvict case after an allocation is made. - // Also we don't check evictable for remaining pages after the - // first NV_ERR_IN_USE is returned. - if (i < numPages - 1) return NV_ERR_NO_MEMORY; - } - } - } - - return status; - } - else - { - return _pmaAddrtreeScanDiscontiguous( - pMap, - addrBase, - rangeStart, - rangeEnd, - numPages, - freeList, - pageSize, - alignment, - numPagesAlloc, - bSkipEvict, - bReverseAlloc); - } -} - -// Either set or clear a specified bit in old and return the result -static NvU64 -replaceBit(NvU64 old, NvU32 bit, NvBool bIsSet) -{ - NV_ASSERT(bit < 64); - NvU64 mask = NVBIT64(bit); - return bIsSet ? (old | mask) : (old & ~mask); -} - -static void -_addrtreeUpdateAncestors -( - PMA_ADDRTREE *pTree, - ADDRTREE_NODE *pNode, - PMA_PAGESTATUS newStateMask -) -{ - ADDRTREE_NODE *pParent; - NvU32 i; - NvU64 newFrame; - NvU32 newIndex; - PMA_PAGESTATUS stateMask; - NvU64 fillPattern; - - pParent = pNode->parent; - - while (pParent != NULL) - { - //NV_PRINTF(LEVEL_INFO, "Current level %d Maybe updating parent at level %d newStateMask=%x\n", - // pNode->level, pNode->level - 1, newStateMask); - - if (newStateMask == 0) - break; - - fillPattern = _makeMaskUpToIndex(pNode->numChildren); - _addrtreeConvertFrame(pTree, pNode->level, pNode->frame, pParent->level, &newFrame); - newIndex = (NvU32)(newFrame - pParent->frame); - - for (i = 0; i < PMA_BITS_PER_PAGE; i++) - { - stateMask = NVBIT(i); - - if (stateMask & newStateMask) - { - NvBool bSeeChild; - NvBool bSetState; - NvU64 newSeeChild; - NvU64 newState; - - // Calculate what this node should look like to the parent - bSetState = NV_FALSE; - bSeeChild = NV_TRUE; - if (pNode->seeChild[i] == 0) - { - if (pNode->state[i] == fillPattern) - { - bSetState = NV_TRUE; - bSeeChild = NV_FALSE; - } - else if (pNode->state[i] == 0) - { - bSeeChild = NV_FALSE; - } - } - - newSeeChild = replaceBit(pParent->seeChild[i], newIndex, bSeeChild); - newState = replaceBit(pParent->state[i], newIndex, bSetState); - - //NV_PRINTF(LEVEL_INFO, "bSetState %d bSeeChild %d newSeeChild=0x%llx newState=0x%llx \n", - // bSetState, bSeeChild, newSeeChild, newState); - - // - // If the parent won't change from this update, do not do any further - // checking on this state: remove it from the mask - // - if (pParent->seeChild[i] == newSeeChild && pParent->state[i] == newState) - { - newStateMask &= ~stateMask; - continue; - } - - //NV_PRINTF(LEVEL_INFO, "update parent\n"); - - pParent->seeChild[i] = newSeeChild; - pParent->state[i] = newState; - - } - } - - pNode = pParent; - pParent = pNode->parent; - } - -} - -// -// This function traverses the tree and changes the state of the frame at `index` -// in `node` to the desired states and change all its ancestors to set seeChild. -// Note that this function also makes `node` a valid node unconditionally. -// -static void -_addrtreeSetState -( - PMA_ADDRTREE *pTree, - ADDRTREE_NODE *pNode, - NvU32 index, - PMA_PAGESTATUS newState, - PMA_PAGESTATUS newStateMask -) -{ - ADDRTREE_NODE *n = pTree->root; - ADDRTREE_NODE *pChildNode; - NvU32 i; - NvU64 newFrame = 0; - NvU32 newIndex; - NvU64 stateMask; - NvU64 childMask = 0; - - //NV_PRINTF(LEVEL_INFO, "Source level=%d frame=0x%llx.\n", - // pNode->level, pNode->frame); - NV_ASSERT(index < pNode->numChildren); - - // Walk down from root and update all its ancestors - while(n->level != pNode->level) - { - _addrtreeConvertFrame(pTree, pNode->level, pNode->frame, n->level, &newFrame); - newIndex = (NvU32)(newFrame - n->frame); - - //NV_PRINTF(LEVEL_INFO, "Going to traverse level=%d newFrame=0x%x newIndex=0x%x \n", - // n->level, newFrame, newIndex); - - childMask = NVBIT64(newIndex); - pChildNode = &n->children[newIndex]; - - for (i = 0; i < PMA_BITS_PER_PAGE; i++) - { - stateMask = NVBIT64(i); - - if (stateMask & newStateMask) - { - // - // If entire node has some state, update children to contain the same state - // Only update child state if this node's seeChild is 0 - // - if ((childMask & n->seeChild[i]) == 0) - { - if ((n->state[i] & childMask) != 0) - { - // - // Note that we may overwrite the pinned state of the edge cases here, - // but they will still be in the correct state since they cannot be the - // ones being freed. - // - pChildNode->state[i] = _makeMaskUpToIndex(pChildNode->numChildren); - } - else - { - // - // There is no risk of overwriting the ALLOC_PIN frames set to - // protect the end-of-region edge case. If seeChild == 0, these nodes - // and all ancestors must be in the set state, not the clear state - // because addrtree will not give out frames that are out of bounds - // - pChildNode->state[i] = 0; - } - - // Set the child's seeChild to 0 so we force update it next iteration - pChildNode->seeChild[i] = 0; - } - n->seeChild[i] |= childMask; - } - } - // Go to the right children to continue walking down - n = pChildNode; - } - - - //NV_PRINTF(LEVEL_INFO, "Setting pNode level=%d frame=0x%llx index=0x%x to state=0x%llx mask=0x%llx\n", - // pNode->level, pNode->frame, index, newState, newStateMask); - - // - // Important loop to actually set the state bits now. - // Do not refactor this unless you know what you are doing! - // Update the node, then go update the ancestors. - // - for (i = 0; i < PMA_BITS_PER_PAGE; i++) - { - stateMask = NVBIT64(i); - - if (stateMask & newStateMask) - { - // Set the current node index as valid since we are changing its states - pNode->seeChild[i] &= ~NVBIT64(index); - - if (stateMask & newStateMask & newState) - { - pNode->state[i] |= NVBIT64(index); - } - else - { - pNode->state[i] &= ~NVBIT64(index); - } - } - } - - _addrtreeUpdateAncestors(pTree, pNode, newStateMask); -} - -static PMA_PAGESTATUS -_addrtreeGetState -( - PMA_ADDRTREE *pTree, - ADDRTREE_NODE *node, - NvU32 index, - NvBool bReadAttrib -) -{ - ADDRTREE_NODE *n = pTree->root; - - NvU64 newFrame = 0; - NvU32 newIndex; - PMA_PAGESTATUS status = STATE_FREE; - PMA_PAGESTATUS stateMask = bReadAttrib ? MAP_MASK : STATE_MASK; - - while(n->level != node->level) - { - _addrtreeConvertFrame(pTree, node->level, node->frame, n->level, &newFrame); - newIndex = (NvU32)(newFrame - n->frame); - - //NV_PRINTF(LEVEL_INFO, "n->level=0x%x, node->level=0x%x\n", n->level, node->level); - - getNodeIndexStatus(n, newIndex, NV_FALSE, &stateMask, &status); - - if (!shouldCheckChildren(stateMask)) - { - return status; - } - - // Go to the right children to continue walking down - n = &n->children[newIndex]; - } - - // Extract the final value from this node - getNodeIndexStatus(node, index, NV_TRUE, &stateMask, &status); - - return status; -} - -// TODO: this is pretty similar to _addrtreeConvertFrame: maybe combine - -static void -_addrtreeConvertLevelFrameToNodeIndex -( - PMA_ADDRTREE *pTree, - NvU32 levelNum, - NvU64 frameNum, - ADDRTREE_NODE **ppNode, - NvU32 *pIndex -) -{ - NvU32 nodeIdx; - ADDRTREE_LEVEL *pLevel; - NvU32 framesPerNode; - - pLevel = &pTree->levels[levelNum]; - framesPerNode = pLevel->maxFramesPerNode; - - nodeIdx = (NvU32)(frameNum / framesPerNode); - *pIndex = (NvU32)(frameNum % framesPerNode); - *ppNode = &pLevel->pNodeList[nodeIdx]; - - NV_ASSERT(*pIndex < (*ppNode)->numChildren); -} - -//frameNum is a levelNum frame -static PMA_PAGESTATUS -pmaAddrtreeReadLevel -( - void *pMap, - NvU32 levelNum, - NvU64 frameNum, - NvBool bReadAttrib -) -{ - NvU32 index; - ADDRTREE_NODE *pNode; - PMA_PAGESTATUS state; - PMA_ADDRTREE *pTree = (PMA_ADDRTREE *)pMap; - - _addrtreeConvertLevelFrameToNodeIndex(pTree, levelNum, - frameNum, &pNode, &index); - - state = _addrtreeGetState(pTree, pNode, index, bReadAttrib); - return state; -} - -// -// This function returns if the node pointed to by pNode index -// has any seeChild bits set for those seeChild bits that are valid for this node. -// It also returns the value of the pNode index in pState -// This is very similar to _addrtreeNodeValid, but requires some tweaked logic -// This is necessary for a very specific check in _pmaAddrtreeChangePageStateAttribEx -// This node must have at least one more level beneath it! -// -static NvBool -_addrtreeNodeIndexHasSeeChildSet -( - PMA_ADDRTREE *pTree, - ADDRTREE_NODE *pNode, - NvU32 index, - PMA_PAGESTATUS *pState -) -{ - ADDRTREE_NODE *n = pTree->root; - NvU64 newFrame = 0; - NvU32 newIndex = 0; - *pState = STATE_FREE; - - // TODO: try this for only STATE_MASK, because stats will only - // get corrupted if the STATE_MASK values differ. - PMA_PAGESTATUS stateMask = MAP_MASK; // check all states TODO - - while(n->level != pNode->level) - { - _addrtreeConvertFrame(pTree, pNode->level, pNode->frame, n->level, &newFrame); - newIndex = (NvU32)(newFrame - n->frame); - - getNodeIndexStatus(n, newIndex, NV_FALSE, &stateMask, pState); - - if (!shouldCheckChildren(stateMask)) - { - // State is fully realized in an ancestor above the parent - return NV_FALSE; - } - - // Go to the right children to continue walking down - n = &n->children[newIndex]; - } - - // Extract the value from this pNode - getNodeIndexStatus(pNode, index, NV_FALSE, &stateMask, pState); - - // Now check if the final child has any seeChild set - if (shouldCheckChildren(stateMask)) - { - // Target child is different from parent - return NV_TRUE; - } - else - { - // State is fully realized in parent - return NV_FALSE; - } -} - -// frameNumStart is the 64k frameNum to start with -static void -__pmaAddrtreeChangePageStateAttribEx -( - void *pMap, - NvU64 frameNumStart, - NvU32 pageSize, - PMA_PAGESTATUS newState, - PMA_PAGESTATUS newStateMask -) -{ - NvU32 index; - ADDRTREE_NODE *pNode; - NvU32 targetLevelNum = addrtreeGetTreeLevel(pageSize) - 1; - NvU64 targetFrameNum; - NvU32 levelNum = addrtreeGetTreeLevel(_PMA_64KB) - 1; - NvU32 levelNum2mb = addrtreeGetTreeLevel(_PMA_2MB) - 1; - PMA_PAGESTATUS oldState, updatedState, oldState2mb, updatedState2mb; - PMA_ADDRTREE *pTree = (PMA_ADDRTREE *)pMap; - PMA_PAGESTATUS targetFoundState; - ADDRTREE_NODE *pTargetNode; - NvU32 targetIndex; - - frameNumStart += pTree->numPaddingFrames; - newStateMask &= MAP_MASK; - - _addrtreeConvertFrame(pTree, levelNum, frameNumStart, targetLevelNum, &targetFrameNum); - - _addrtreeConvertLevelFrameToNodeIndex(pTree, targetLevelNum, targetFrameNum, &pTargetNode, &targetIndex); - - // - // In address tree, if a node is partially allocated, any node above that node is considered fully - // allocated because you cannot allocate a node-aligned block at the higher level. - // Because of address tree structure, we don't get an accurate count of the number of frames - // that were allocated beforehand if we're overwriting some state. - // e.g. if a node is half allocated and then we allocate the rest of it at a higher level, - // then there's no way to know how many frames were allocated before without going downwards and reading them. - // Until something better is implemented, implement a heuristic wherein we only do the optimized case - // when the current node has no seeChild bits are set for thoese seeChild bits that are valid for this node. - // Also, we won't get any optimization out of doing this for 64KB, so skip it and avoid wasting time - // reading state. - // Since stats only care about free/unpin/pin states,.we could perhaps relax this restriction - // - - if ((pageSize >= _PMA_2MB) && - !_addrtreeNodeIndexHasSeeChildSet(pTree, pTargetNode, targetIndex, &targetFoundState)) - { - // Do optimized case - - // Figure out how many 64KB frames and how many 2MB frames we're going to touch - NvU64 numFramesTouched = pageSize >> PMA_PAGE_SHIFT; - NvU64 num2mbFramesTouched = pageSize >> _TREE_2MB; - - updatedState = (targetFoundState & ~newStateMask) | (newState & newStateMask); - - _addrtreeSetState(pTree, pTargetNode, targetIndex, newState, newStateMask); - - // In this case, the states at the 2MB and 64KB levels are the same because we're changing at - // least a 2MB node that had no valid children - pmaStatsUpdateState(&pTree->pPmaStats->numFreeFrames, - numFramesTouched, targetFoundState, updatedState); - pmaStatsUpdateState(&pTree->pPmaStats->numFree2mbPages, - num2mbFramesTouched, targetFoundState, updatedState); - - } - else - { - // Do unoptimized case - NvU32 framesPerPage = pageSize >> PMA_PAGE_SHIFT; - NvU32 j; - - for (j = 0; j < framesPerPage; j++) - { - NvU64 frameNum2mb; - NvU64 frameNum = frameNumStart + j; - - _addrtreeConvertFrame(pTree, levelNum, frameNum, levelNum2mb, &frameNum2mb); - oldState2mb = pmaAddrtreeReadLevel(pTree, levelNum2mb, frameNum2mb, NV_TRUE); - - _addrtreeConvertLevelFrameToNodeIndex(pTree, levelNum, frameNum, &pNode, &index); - - // The read is done only to update the stats tracking - oldState = pmaAddrtreeReadLevel(pTree, levelNum, frameNum, NV_TRUE); - _addrtreeSetState(pTree, pNode, index, newState, newStateMask); - - // Calculate what the new state will be - updatedState = (oldState & ~newStateMask) | (newState & newStateMask); - - pmaStatsUpdateState(&pTree->pPmaStats->numFreeFrames, 1, oldState, updatedState); - - updatedState2mb = pmaAddrtreeReadLevel(pTree, levelNum2mb, frameNum2mb, NV_TRUE); - - if (updatedState2mb != oldState2mb) - { - pmaStatsUpdateState(&pTree->pPmaStats->numFree2mbPages, 1, - oldState2mb, updatedState2mb); - - } - } - - } -} - -// -// This function wraps the real __pmaAddrtreeChangePageStateAttribEx -// to allow addrtree to set 128KB page size -// -static void -_pmaAddrtreeChangePageStateAttribEx -( - void *pMap, - NvU64 frameNumStart, - NvU32 pageSize, - PMA_PAGESTATUS newState, - PMA_PAGESTATUS newStateMask -) -{ - if (NV_UNLIKELY(pageSize == _PMA_128KB)) { - NvU64 i; - for (i = 0; i < 2; i++) { - __pmaAddrtreeChangePageStateAttribEx( - pMap, - frameNumStart + i, - _PMA_64KB, - newState, - newStateMask); - } - } - else - { - __pmaAddrtreeChangePageStateAttribEx( - pMap, - frameNumStart, - pageSize, - newState, - newStateMask); - } -} - -// -// These accessor functions can be made more efficient. TODO improve this. -// We have page size information in the alloc path, but in general, we don't use -// _pmaAddrtreeChangePageStateAttribEx to its fullest extent for all other cases where -// we change the state of the tree. -// If we had the page size information, we won't need to walk the tree for every frame. -// For now, pmaAddrtreeChangeState and pmaAddrtreeRead only operate on 64K level frameNums -// -void -pmaAddrtreeChangeStateAttribEx -( - void *pMap, - NvU64 frameNum, - PMA_PAGESTATUS newState, - PMA_PAGESTATUS newStateMask -) -{ - _pmaAddrtreeChangePageStateAttribEx(pMap, frameNum, _PMA_64KB, newState, newStateMask); -} - -// TODO: merge this on PMA level -void pmaAddrtreeChangeState(void *pTree, NvU64 frameNum, PMA_PAGESTATUS newState) -{ - pmaAddrtreeChangeStateAttribEx(pTree, frameNum, newState, STATE_MASK); -} - -// TODO: merge this on PMA level -void pmaAddrtreeChangeStateAttrib(void *pTree, NvU64 frameNum, PMA_PAGESTATUS newState, NvBool writeAttrib) -{ - PMA_PAGESTATUS mask = writeAttrib ? MAP_MASK : STATE_MASK; - pmaAddrtreeChangeStateAttribEx(pTree, frameNum, newState, mask); -} - -// TODO: merge this on PMA level -void -pmaAddrtreeChangePageStateAttrib -( - void * pTree, - NvU64 frameNumStart, - NvU32 pageSize, - PMA_PAGESTATUS newState, - NvBool writeAttrib -) -{ - PMA_PAGESTATUS mask = writeAttrib ? MAP_MASK : STATE_MASK; - _pmaAddrtreeChangePageStateAttribEx(pTree, frameNumStart, pageSize, newState, mask); -} - -PMA_PAGESTATUS pmaAddrtreeRead -( - void *pMap, - NvU64 frameNum, - NvBool bReadAttrib -) -{ - NvU32 index; - ADDRTREE_NODE *pNode; - NvU32 levelNum = addrtreeGetTreeLevel(_PMA_64KB) - 1; - PMA_PAGESTATUS state; - PMA_ADDRTREE *pTree = (PMA_ADDRTREE *)pMap; - frameNum += pTree->numPaddingFrames; - - _addrtreeConvertLevelFrameToNodeIndex(pTree, levelNum, - frameNum, &pNode, &index); - - state = _addrtreeGetState(pTree, pNode, index, bReadAttrib); - return state; -} - - -void pmaAddrtreeGetSize -( - void *pMap, - NvU64 *pBytesTotal -) -{ - PMA_ADDRTREE *pTree = (PMA_ADDRTREE *)pMap; - *pBytesTotal = (pTree->totalFrames << PMA_PAGE_SHIFT); -} - -// -// The algorithm here is very simplistic. But maybe that's OK because this call -// is not used a whole lot. We can optimize it but might not worth the effort. -// -void pmaAddrtreeGetLargestFree -( - void *pMap, - NvU64 *pLargestFree -) -{ - NvU64 i, length = 0, largestLength = 0; - PMA_ADDRTREE *pTree = (PMA_ADDRTREE *)pMap; - - for (i = 0; i < pTree->totalFrames; i++) - { - if (pmaAddrtreeRead(pTree, i, NV_FALSE) != STATE_FREE) - { - largestLength = NV_MAX(length, largestLength); - length = 0; - } - else - { - length++; - } - } - - largestLength = NV_MAX(length, largestLength); - *pLargestFree = (largestLength << PMA_PAGE_SHIFT); -} - -// -// Check whether the specified frame range is available completely for eviction -// -// Returns: -// - -1 if the whole range is evictable -// -// - Index of the last unevictable frame number -// -// For now, just do a dumb scan frame by frame -static NvS64 -_pmaAddrtreeScanNumaUnevictable -( - PMA_ADDRTREE *pTree, - NvU64 frameBegin, - NvU64 frameEnd -) -{ - NvU64 frame; - PMA_PAGESTATUS frameStatus; - - for(frame = frameEnd; frame >= frameBegin; frame--) - { - frameStatus = pmaAddrtreeRead((void*)pTree, frame, NV_TRUE); - if (frameStatus != STATE_UNPIN) - { - return frame; - } - } - return -1; -} - -// -// Determine a contiguous evictable range of size actualSize -// -// Returns: -// - NV_ERR_NO_MEMORY if eviction is not possible for this size -// -// - NV_OK if there is a valid contiguous evictable range -// starting and ending at address stored at evictStart and evictEnd -// -// - -NV_STATUS pmaAddrtreeScanContiguousNumaEviction -( - void *pMap, - NvU64 addrBase, - NvLength actualSize, - NvU64 pageSize, - NvU64 *evictStart, - NvU64 *evictEnd -) -{ - NV_STATUS status = NV_ERR_NO_MEMORY; - PMA_ADDRTREE *pTree = (PMA_ADDRTREE *)pMap; - - NvU64 alignedAddrBase; - NvU64 frameNum; - NvU64 endFrame, frameStart; - NvU64 alignment = pageSize; - NvU64 frameAlignment, frameAlignmentPadding; - NvU64 numFrames = actualSize >> PMA_PAGE_SHIFT; - NvU64 framesToSkip; - NvU32 level = addrtreeGetTreeLevel(_PMA_64KB) - 1; - PMA_PAGESTATUS startStatus, endStatus; - - endFrame = pTree->totalFrames - 1; - - if (pTree->totalFrames < numFrames) - return status; - - // Copied from _pmaAddrtreeContigSearchLoop, pmaRegmapScanContiguous - // We need to do this one the 64K frame level because addrtree will currently - // qualify a 2MB node that is half unpin and half free as entirely - // unpin, which doesn't work in NUMA mode because PMA cannot ask - // UVM to evict free pages in NUMA mode - - frameAlignment = alignment >> PMA_PAGE_SHIFT; - alignedAddrBase = NV_ALIGN_UP(addrBase, alignment); - // May need to modify to work with internal address tree padding - frameAlignmentPadding = (alignedAddrBase - addrBase) >> PMA_PAGE_SHIFT; - frameStart = alignUpToMod(0, frameAlignment, frameAlignmentPadding); - - for (frameNum = frameStart; frameNum <= endFrame; ) - { - NvS64 firstUnevictableFrame; - NvU64 endFrame = frameNum + numFrames - 1; - - // - // Read endStatus first so we don't have to waste time traversing the - // tree again to read startStatus if endStatus is not even usable - // - endStatus = _pmaAddrtreeReadLevelAndSkipUnavailable(pTree, level, endFrame, STATE_UNPIN, NV_FALSE, &framesToSkip, NV_FALSE); - - if (framesToSkip > 1) { - frameNum = NV_ALIGN_UP(endFrame + framesToSkip, frameAlignment); - NV_ASSERT(frameNum != 0); - continue; - } - - startStatus = _pmaAddrtreeReadLevelAndSkipUnavailable(pTree, level, frameNum, STATE_UNPIN, NV_FALSE, &framesToSkip, NV_FALSE); - - if (framesToSkip > 1) { - frameNum += NV_ALIGN_UP(framesToSkip, frameAlignment); - NV_ASSERT(frameNum != 0); - continue; - } - - // Check against the whole state since we've already ready that in addrtree - if (endStatus != STATE_UNPIN) - { - // end is not available jump from start to after numFrames - frameNum += numFrames; - frameNum = alignUpToMod(frameNum, frameAlignment, frameAlignmentPadding); - continue; - } - - if (startStatus != STATE_UNPIN) - { - // startFrame is unavailable, jump to next aligned frame - frameNum += frameAlignment; - continue; - } - - // First occurrence of 0 in STATE_UNPIN from frameNum to frameNum + numFrames - 1 - firstUnevictableFrame = _pmaAddrtreeScanNumaUnevictable(pMap, frameNum, frameNum + numFrames - 1); - - if (firstUnevictableFrame == -1) - { - NV_PRINTF(LEVEL_INFO, " %s evictable frame = %lld evictstart = %llx evictEnd = %llx\n", - __FUNCTION__, frameNum, addrBase + (frameNum << PMA_PAGE_SHIFT), - (addrBase + (frameNum << PMA_PAGE_SHIFT) + actualSize - 1)); - - // Subtract off padding when returning - *evictStart = addrBase + (frameNum << PMA_PAGE_SHIFT) - (pTree->numPaddingFrames << PMA_PAGE_SHIFT); - *evictEnd = *evictStart + actualSize - 1; - status = NV_OK; - break; - } - else - { - // get the next aligned frame after the unevictable frame. - frameNum = alignUpToMod(firstUnevictableFrame + 1, frameAlignment, frameAlignmentPadding); - } - } - - return status; - -} - -NvU64 pmaAddrtreeGetEvictingFrames(void *pMap) -{ - return ((PMA_ADDRTREE *)pMap)->frameEvictionsInProcess; -} - -void pmaAddrtreeSetEvictingFrames(void *pMap, NvU64 frameEvictionsInProcess) -{ - ((PMA_ADDRTREE *)pMap)->frameEvictionsInProcess = frameEvictionsInProcess; -} diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/kernel/gpu/mem_mgr/phys_mem_allocator/numa.c nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/kernel/gpu/mem_mgr/phys_mem_allocator/numa.c --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/kernel/gpu/mem_mgr/phys_mem_allocator/numa.c 2023-10-25 20:21:12.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/kernel/gpu/mem_mgr/phys_mem_allocator/numa.c 2024-03-05 22:13:37.000000000 +0000 @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 2015-2021 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2015-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -47,7 +47,7 @@ static NV_STATUS _pmaNumaAllocateRange(PMA *pPma, NvU32 numaNodeId, NvLength actualSize, NvU64 pageSize, NvU64 *pPages, NvBool bScrubOnAlloc, NvBool allowEvict, NvS32 *validRegionList, NvU64 *allocatedCount); -static NV_STATUS _pmaNumaAllocatePages (PMA *pPma, NvU32 numaNodeId, NvU32 pageSize, +static NV_STATUS _pmaNumaAllocatePages (PMA *pPma, NvU32 numaNodeId, NvU64 pageSize, NvLength allocationCount, NvU64 *pPages, NvBool bScrubOnAlloc, NvBool allowEvict, NvS32 *validRegionList, NvU64 *allocatedPages); @@ -163,7 +163,7 @@ */ static NvBool _pmaCheckFreeFramesToSkipReclaim(PMA *pPma) { - return (100 * pPma->pmaStats.numFreeFrames < + return (100 * pPma->pmaStats.numFreeFrames < (pPma->pmaStats.num2mbPages * (_PMA_2MB >> PMA_PAGE_SHIFT) * pPma->numaReclaimSkipThreshold)); } @@ -189,6 +189,8 @@ NvU32 flags = OS_ALLOC_PAGES_NODE_NONE; *allocatedCount = 0; + NV_ASSERT_OR_RETURN(actualSize >= osGetPageSize(), NV_ERR_INVALID_ARGUMENT); + // check if numFreeFrames(64KB) are below a certain % of PMA managed memory(indicated by num2mbPages). if (_pmaCheckFreeFramesToSkipReclaim(pPma)) { @@ -202,12 +204,10 @@ if (status == NV_OK) { - NvU32 j; - // j=0 head page is already refcounted at allocation - for (j = 1; j < (actualSize >> PMA_PAGE_SHIFT); j++) - { - osAllocAcquirePage(sysPhysAddr + (j << PMA_PAGE_SHIFT)); - } + NvU8 osPageShift = osGetPageShift(); + + // Skip the first page as it is refcounted at allocation. + osAllocAcquirePage(sysPhysAddr + (1 << osPageShift), (actualSize >> osPageShift) - 1); gpaPhysAddr = sysPhysAddr - pPma->coherentCpuFbBase; NV_ASSERT(gpaPhysAddr < pPma->coherentCpuFbBase); @@ -319,7 +319,7 @@ ( PMA *pPma, NvU32 numaNodeId, - NvU32 pageSize, + NvU64 pageSize, NvLength allocationCount, NvU64 *pPages, NvBool bScrubOnAlloc, @@ -330,10 +330,12 @@ { NV_STATUS status = NV_ERR_NO_MEMORY; NvU64 sysPhysAddr; - NvU64 i = 0, j = 0; - NvU32 flags = OS_ALLOC_PAGES_NODE_NONE; + NvU64 i = 0; + NvU32 flags = OS_ALLOC_PAGES_NODE_NONE; + NvU8 osPageShift = osGetPageShift(); NV_ASSERT(allocationCount); + NV_ASSERT_OR_RETURN(pageSize >= osGetPageSize(), NV_ERR_INVALID_ARGUMENT); // check if numFreeFrames are below certain % of PMA managed memory. if (_pmaCheckFreeFramesToSkipReclaim(pPma)) @@ -357,14 +359,11 @@ NV_ASSERT(sysPhysAddr >= pPma->coherentCpuFbBase); pPages[i] = sysPhysAddr - pPma->coherentCpuFbBase; - // Skip the head page at offset 0 (j=0) as it is refcounted at allocation - for (j = 1; j < (pageSize >> PMA_PAGE_SHIFT); j++) - { - osAllocAcquirePage(sysPhysAddr + (j << PMA_PAGE_SHIFT)); - } + // Skip the first page as it is refcounted at allocation. + osAllocAcquirePage(sysPhysAddr + (1 << osPageShift), (pageSize >> osPageShift) - 1); } - if (bScrubOnAlloc) + if (bScrubOnAlloc && (i > 0)) { PSCRUB_NODE pPmaScrubList = NULL; NvU64 count; @@ -465,23 +464,24 @@ ( PMA *pPma, NvLength allocationCount, - NvU32 pageSize, + NvU64 pageSize, PMA_ALLOCATION_OPTIONS *allocationOptions, NvU64 *pPages ) { NvU32 i; - NV_STATUS status = NV_OK; - NvU32 numaNodeId = pPma->numaNodeId; + NV_STATUS status = NV_OK; + NvU32 numaNodeId = pPma->numaNodeId; NvS32 regionList[PMA_REGION_SIZE]; - NvU32 flags = allocationOptions->flags; - NvLength allocSize = 0; - NvLength allocCount = 0; - NvU32 contigFlag = !!(flags & PMA_ALLOCATE_CONTIGUOUS); + NvU32 flags = allocationOptions->flags; + NvLength allocSize = 0; + NvLength allocCount = 0; + NvU32 contigFlag = !!(flags & PMA_ALLOCATE_CONTIGUOUS); // As per bug #2444368, kernel scrubbing is too slow. Use the GPU scrubber instead - NvBool bScrubOnAlloc = !(flags & PMA_ALLOCATE_NO_ZERO); - NvBool allowEvict = !(flags & PMA_ALLOCATE_DONT_EVICT); - NvBool partialFlag = !!(flags & PMA_ALLOCATE_ALLOW_PARTIAL); + NvBool bScrubOnAlloc = !(flags & PMA_ALLOCATE_NO_ZERO); + NvBool allowEvict = !(flags & PMA_ALLOCATE_DONT_EVICT); + NvBool partialFlag = !!(flags & PMA_ALLOCATE_ALLOW_PARTIAL); + NvBool bSkipScrubFlag = !!(flags & PMA_ALLOCATE_NO_ZERO); NvU64 finalAllocatedCount = 0; @@ -492,9 +492,9 @@ return NV_ERR_INVALID_ARGUMENT; } - if (pageSize > _PMA_2MB) + if (pageSize > _PMA_512MB) { - NV_PRINTF(LEVEL_FATAL, "Cannot allocate with more than 2MB contiguity.\n"); + NV_PRINTF(LEVEL_FATAL, "Cannot allocate with more than 512MB contiguity.\n"); return NV_ERR_INVALID_ARGUMENT; } @@ -517,7 +517,13 @@ // We are not changing the state. Can be outside the lock perhaps NV_CHECK_OK_OR_RETURN(LEVEL_FATAL, pmaSelector(pPma, allocationOptions, regionList)); - if (pPma->bScrubOnFree) + // + // Scrub on free is enabled for this allocation request if the feature is enabled and the + // caller does not want to skip scrubber. + // Caller may want to skip scrubber when it knows the memory is zero'ed or when we are + // initializing RM structures needed by the scrubber itself. + // + if (pPma->bScrubOnFree && !bSkipScrubFlag) { portSyncMutexAcquire(pPma->pAllocLock); portSyncRwLockAcquireRead(pPma->pScrubberValidLock); @@ -602,7 +608,7 @@ status = NV_ERR_NO_MEMORY; break; } - pPma->pMapInfo->pmaMapChangeStateAttrib(pMap, frameOffset, allocOption, NV_TRUE); + pPma->pMapInfo->pmaMapChangeStateAttribEx(pMap, frameOffset, allocOption, MAP_MASK); } if (status != NV_OK) break; @@ -632,7 +638,7 @@ portSyncSpinlockRelease(pPma->pPmaLock); - if (pPma->bScrubOnFree) + if (pPma->bScrubOnFree && !bSkipScrubFlag) { portSyncRwLockReleaseRead(pPma->pScrubberValidLock); portSyncMutexRelease(pPma->pAllocLock); @@ -651,6 +657,9 @@ ) { NvU64 i, j; + NvU8 osPageShift = osGetPageShift(); + + NV_ASSERT_OR_RETURN_VOID(PMA_PAGE_SHIFT >= osPageShift); NV_PRINTF(LEVEL_INFO, "Freeing pPage[0] = %llx pageCount %lld\n", pPages[0], pageCount); @@ -697,7 +706,7 @@ continue; } sysPagePhysAddr = sysPhysAddr + (j << PMA_PAGE_SHIFT); - osAllocReleasePage(sysPagePhysAddr); + osAllocReleasePage(sysPagePhysAddr, 1 << (PMA_PAGE_SHIFT - osPageShift)); pPma->pMapInfo->pmaMapChangeStateAttribEx(pPma->pRegions[regId], (frameNum + j), newStatus, ~ATTRIB_EVICTING); } } diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/kernel/gpu/mem_mgr/phys_mem_allocator/phys_mem_allocator.c nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/kernel/gpu/mem_mgr/phys_mem_allocator/phys_mem_allocator.c --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/kernel/gpu/mem_mgr/phys_mem_allocator/phys_mem_allocator.c 2023-10-25 20:21:12.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/kernel/gpu/mem_mgr/phys_mem_allocator/phys_mem_allocator.c 2024-03-05 22:13:37.000000000 +0000 @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 2015-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2015-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -45,7 +45,7 @@ ( PMA *pPma, NvLength allocationCount, - NvU32 pageSize, + NvU64 pageSize, PMA_ALLOCATION_OPTIONS *allocationOptions, NvU64 *pPages ) @@ -70,7 +70,7 @@ } #endif -typedef NV_STATUS (*scanFunc)(void *, NvU64, NvU64, NvU64, NvU64, NvU64*, NvU32, NvU64, NvU64*, NvBool, NvBool); +typedef NV_STATUS (*scanFunc)(void *, NvU64, NvU64, NvU64, NvU64, NvU64*, NvU64, NvU64, NvU64*, NvBool, NvBool); static void _pmaRollback @@ -79,14 +79,14 @@ NvU64 *pPages, NvU32 failCount, NvU32 failFrame, - NvU32 pageSize, + NvU64 pageSize, PMA_PAGESTATUS oldState ) { NvU32 framesPerPage, regId, i, j; NvU64 frameNum, addrBase; - framesPerPage = pageSize >> PMA_PAGE_SHIFT; + framesPerPage = (NvU32)(pageSize >> PMA_PAGE_SHIFT); if (failCount != 0) { for(i = 0; i < failCount; i++) @@ -97,7 +97,7 @@ for (j = 0; j < framesPerPage; j++) { - pPma->pMapInfo->pmaMapChangeState(pPma->pRegions[regId], (frameNum + j), oldState); + pPma->pMapInfo->pmaMapChangeStateAttribEx(pPma->pRegions[regId], (frameNum + j), oldState, STATE_MASK); } } } @@ -110,7 +110,7 @@ frameNum = PMA_ADDR2FRAME(pPages[failCount], addrBase); for(i = 0; i < failFrame; i++) { - pPma->pMapInfo->pmaMapChangeState(pPma->pRegions[regId], (frameNum + i), oldState); + pPma->pMapInfo->pmaMapChangeStateAttribEx(pPma->pRegions[regId], (frameNum + i), oldState, STATE_MASK); } } } @@ -208,10 +208,9 @@ // pMapInfo->pmaMapInit = pmaRegmapInit; pMapInfo->pmaMapDestroy = pmaRegmapDestroy; - pMapInfo->pmaMapChangeState = pmaRegmapChangeState; - pMapInfo->pmaMapChangeStateAttrib = pmaRegmapChangeStateAttrib; pMapInfo->pmaMapChangeStateAttribEx = pmaRegmapChangeStateAttribEx; - pMapInfo->pmaMapChangePageStateAttrib = pmaRegmapChangePageStateAttrib; + pMapInfo->pmaMapChangePageStateAttribEx = pmaRegmapChangePageStateAttribEx; + pMapInfo->pmaMapChangeBlockStateAttrib = pmaRegmapChangeBlockStateAttrib; pMapInfo->pmaMapRead = pmaRegmapRead; pMapInfo->pmaMapScanContiguous = pmaRegmapScanContiguous; pMapInfo->pmaMapScanDiscontiguous = pmaRegmapScanDiscontiguous; @@ -239,31 +238,16 @@ } pPma->bNuma = !!(initFlags & PMA_INIT_NUMA); - // If we want to run with address tree instead of regmap - if (initFlags & PMA_INIT_ADDRTREE) - { - pMapInfo->pmaMapInit = pmaAddrtreeInit; - pMapInfo->pmaMapDestroy = pmaAddrtreeDestroy; - pMapInfo->pmaMapChangeState = pmaAddrtreeChangeState; - pMapInfo->pmaMapChangeStateAttrib = pmaAddrtreeChangeStateAttrib; - pMapInfo->pmaMapChangeStateAttribEx = pmaAddrtreeChangeStateAttribEx; - pMapInfo->pmaMapChangePageStateAttrib = pmaAddrtreeChangePageStateAttrib; - pMapInfo->pmaMapRead = pmaAddrtreeRead; - pMapInfo->pmaMapScanContiguous = pmaAddrtreeScanContiguous; - pMapInfo->pmaMapScanDiscontiguous = pmaAddrtreeScanDiscontiguous; - pMapInfo->pmaMapGetSize = pmaAddrtreeGetSize; - pMapInfo->pmaMapGetLargestFree = pmaAddrtreeGetLargestFree; - pMapInfo->pmaMapScanContiguousNumaEviction = pmaAddrtreeScanContiguousNumaEviction; - pMapInfo->pmaMapGetEvictingFrames = pmaAddrtreeGetEvictingFrames; - pMapInfo->pmaMapSetEvictingFrames = pmaAddrtreeSetEvictingFrames; - NV_PRINTF(LEVEL_WARNING, "Going to use addrtree for PMA init!!\n"); - } + pPma->bNumaAutoOnline = !!(initFlags & PMA_INIT_NUMA_AUTO_ONLINE); } pPma->pMapInfo = pMapInfo; pPma->pmaStats.numFreeFrames = 0; pPma->pmaStats.num2mbPages = 0; pPma->pmaStats.numFree2mbPages = 0; + pPma->pmaStats.numFreeFramesProtected = 0; + pPma->pmaStats.num2mbPagesProtected = 0; + pPma->pmaStats.numFree2mbPagesProtected = 0; pPma->regSize = 0; portAtomicSetSize(&pPma->initScrubbing, PMA_SCRUB_INITIALIZE); @@ -552,7 +536,7 @@ ( PMA *pPma, NvLength allocationCount, - NvU32 pageSize, + NvU64 pageSize, PMA_ALLOCATION_OPTIONS *allocationOptions, NvU64 *pPages ) @@ -573,7 +557,7 @@ scanFunc useFunc; PMA_PAGESTATUS pinOption; NvU64 alignment = pageSize; - NvU32 framesPerPage = pageSize >> PMA_PAGE_SHIFT; + NvU32 framesPerPage = (NvU32)(pageSize >> PMA_PAGE_SHIFT); // // A boolean indicating if we should try to evict. We at most try eviction once per call @@ -595,7 +579,7 @@ if (allocationCount == 0) NV_PRINTF(LEVEL_ERROR, "count == 0\n"); if (pageSize != _PMA_64KB && pageSize != _PMA_128KB && pageSize != _PMA_2MB && pageSize != _PMA_512MB) - NV_PRINTF(LEVEL_ERROR, "pageSize=0x%x (not 64K, 128K, 2M, or 512M)\n", pageSize); + NV_PRINTF(LEVEL_ERROR, "pageSize=0x%llx (not 64K, 128K, 2M, or 512M)\n", pageSize); if (allocationOptions == NULL) NV_PRINTF(LEVEL_ERROR, "NULL allocationOptions\n"); return NV_ERR_INVALID_ARGUMENT; @@ -655,7 +639,7 @@ || !NV_IS_ALIGNED((allocationOptions->physEnd + 1), pageSize))) { NV_PRINTF(LEVEL_WARNING, - "base [0x%llx] or limit [0x%llx] not aligned to page size 0x%x\n", + "base [0x%llx] or limit [0x%llx] not aligned to page size 0x%llx\n", allocationOptions->physBegin, allocationOptions->physEnd + 1, pageSize); @@ -681,7 +665,7 @@ if (!contigFlag && alignment > pageSize) { NV_PRINTF(LEVEL_WARNING, - "alignment [%llx] larger than the pageSize [%x] not supported for non-contiguous allocs\n", + "alignment [%llx] larger than the pageSize [%llx] not supported for non-contiguous allocs\n", alignment, pageSize); return NV_ERR_INVALID_ARGUMENT; } @@ -722,7 +706,7 @@ // after checking the scrubber so any pages allocated so far are not guaranteed // to be there any more. Restart from scratch. // - NV_PRINTF(LEVEL_INFO, "Attempt %s allocation of 0x%llx pages of size 0x%x " + NV_PRINTF(LEVEL_INFO, "Attempt %s allocation of 0x%llx pages of size 0x%llx " "(0x%x frames per page)\n", contigFlag ? "contiguous" : "discontiguous", (NvU64)allocationCount, pageSize, framesPerPage); @@ -831,15 +815,6 @@ curPages += numPagesAllocatedThisTime; numPagesLeftToAllocate -= numPagesAllocatedThisTime; - // - // PMA must currently catch addrtree shortcomings and fail the request - // Just follow the no memory path for now to properly release locks - // - if (status == NV_ERR_INVALID_ARGUMENT) - { - status = NV_ERR_NO_MEMORY; - } - if (status == NV_ERR_IN_USE && !tryEvict) { // @@ -889,7 +864,7 @@ NvU64 evictStart = *curPages; NvU64 evictEnd = *curPages + (numFramesToAllocateTotal << PMA_PAGE_SHIFT) - 1; - NV_PRINTF(LEVEL_INFO, "Attempt %s eviction of 0x%llx pages of size 0x%x, " + NV_PRINTF(LEVEL_INFO, "Attempt %s eviction of 0x%llx pages of size 0x%llx, " "(0x%x frames per page) in the frame range 0x%llx..0x%llx\n", contigFlag ? "contiguous" : "discontiguous", numPagesLeftToAllocate, @@ -919,7 +894,7 @@ NV_ASSERT(evictPhysBegin <= evictPhysEnd); } - NV_PRINTF(LEVEL_INFO, "Attempt %s eviction of 0x%llx pages of size 0x%x, " + NV_PRINTF(LEVEL_INFO, "Attempt %s eviction of 0x%llx pages of size 0x%llx, " "(0x%x frames per page), in the frame range 0x%llx..0x%llx\n", contigFlag ? "contiguous" : "discontiguous", numPagesLeftToAllocate, @@ -1079,11 +1054,8 @@ frameBase, frameBase + numFramesAllocated - 1); - for (i = 0; i < numPagesAllocatedSoFar; i++) - { - pPma->pMapInfo->pmaMapChangePageStateAttrib(pMap, frameBase + (i * framesPerPage), - pageSize, pinOption, NV_TRUE); - } + pPma->pMapInfo->pmaMapChangeBlockStateAttrib(pMap, frameBase, numPagesAllocatedSoFar * framesPerPage, + pinOption, MAP_MASK); if (blacklistOffFlag && blacklistOffPerRegion[regId]) { @@ -1129,8 +1101,8 @@ } lastFrameRangeEnd = frameBase + framesPerPage - 1; - pPma->pMapInfo->pmaMapChangePageStateAttrib(pMap, PMA_ADDR2FRAME(pPages[i], addrBase), - pageSize, pinOption, NV_TRUE); + pPma->pMapInfo->pmaMapChangePageStateAttribEx(pMap, PMA_ADDR2FRAME(pPages[i], addrBase), + pageSize, pinOption, MAP_MASK); } NV_PRINTF(LEVEL_INFO, "0x%llx through 0x%llx \n", @@ -1182,7 +1154,7 @@ PMA **pPma, NvU32 pmaCount, NvLength allocationCount, - NvU32 pageSize, + NvU64 pageSize, PMA_ALLOCATION_OPTIONS *allocationOptions, NvU64 *pPages ) @@ -1204,14 +1176,14 @@ PMA *pPma, NvU64 *pPages, NvLength pageCount, - NvU32 pageSize + NvU64 pageSize ) { NV_STATUS status = NV_OK; NvU32 framesPerPage, regId, i, j; NvU64 frameNum, addrBase; PMA_PAGESTATUS state; - framesPerPage = pageSize >> PMA_PAGE_SHIFT; + framesPerPage = (NvU32)(pageSize >> PMA_PAGE_SHIFT); if (pPma == NULL || pageCount == 0 || pPages == NULL || (pageSize != _PMA_64KB && pageSize != _PMA_128KB && pageSize != _PMA_2MB && pageSize != _PMA_512MB)) @@ -1262,7 +1234,7 @@ } else { - pPma->pMapInfo->pmaMapChangeState(pPma->pRegions[regId], (frameNum + j), STATE_PIN); + pPma->pMapInfo->pmaMapChangeStateAttribEx(pPma->pRegions[regId], (frameNum + j), STATE_PIN, STATE_MASK); } } } @@ -1280,13 +1252,13 @@ PMA *pPma, NvU64 *pPages, NvLength pageCount, - NvU32 pageSize + NvU64 pageSize ) { NvU32 framesPerPage, regId, i, j; NvU64 frameNum, addrBase; PMA_PAGESTATUS state; - framesPerPage = pageSize >> PMA_PAGE_SHIFT; + framesPerPage = (NvU32)(pageSize >> PMA_PAGE_SHIFT); if (pPma == NULL || pageCount == 0 || pPages == NULL || (pageSize != _PMA_64KB && pageSize != _PMA_128KB && pageSize != _PMA_2MB && pageSize != _PMA_512MB)) @@ -1310,12 +1282,12 @@ NV_PRINTF(LEVEL_ERROR, "Unpin failed at %dth page %dth frame\n", i, j); _pmaRollback(pPma, pPages, i, j, pageSize, STATE_PIN); + portSyncSpinlockRelease(pPma->pPmaLock); return NV_ERR_INVALID_STATE; - } else { - pPma->pMapInfo->pmaMapChangeState(pPma->pRegions[regId], (frameNum + j), STATE_UNPIN); + pPma->pMapInfo->pmaMapChangeStateAttribEx(pPma->pRegions[regId], (frameNum + j), STATE_UNPIN, STATE_MASK); } } } @@ -1350,7 +1322,8 @@ { NV_ASSERT((size == _PMA_64KB) || (size == _PMA_128KB) || - (size == _PMA_2MB)); + (size == _PMA_2MB) || + (size == _PMA_512MB)); } // Fork out new code path for NUMA sub-allocation from OS @@ -1612,6 +1585,24 @@ NvU64 *pBytesFree ) { +#if !defined(SRT_BUILD) + NvU64 val; + + portSyncSpinlockAcquire(pPma->pPmaLock); + NvBool nodeOnlined = pPma->nodeOnlined; + portSyncSpinlockRelease(pPma->pPmaLock); + + if (nodeOnlined) + { + osGetNumaMemoryUsage(pPma->numaNodeId, pBytesFree, &val); + return; + } + // + // what to return when bNUMA == NV_TRUE and nodeOnlined==NV_FALSE? + // TODO : BUG 4199482. + // +#endif + portSyncSpinlockAcquire(pPma->pPmaLock); *pBytesFree = pPma->pmaStats.numFreeFrames << PMA_PAGE_SHIFT; @@ -1632,6 +1623,24 @@ *pBytesTotal = 0; +#if !defined(SRT_BUILD) + NvU64 val; + + portSyncSpinlockAcquire(pPma->pPmaLock); + NvBool nodeOnlined = pPma->nodeOnlined; + portSyncSpinlockRelease(pPma->pPmaLock); + + if (nodeOnlined) + { + osGetNumaMemoryUsage(pPma->numaNodeId, &val, pBytesTotal); + return; + } + // + // what to return when bNUMA == NV_TRUE and nodeOnlined==NV_FALSE? + // TODO : BUG 4199482. + // +#endif + for (i = 0; i < pPma->regSize; i++) { pMap = pPma->pRegions[i]; @@ -1800,7 +1809,7 @@ ( PMA *pPma, NvU64 *pChunks, - NvU32 *pPageSize, + NvU64 *pPageSize, NvU32 *pNumChunks ) { @@ -1977,7 +1986,11 @@ NvU64 *pBytesFree ) { - *pBytesFree = 0; + portSyncSpinlockAcquire(pPma->pPmaLock); + + *pBytesFree = (pPma->pmaStats.numFreeFramesProtected) << PMA_PAGE_SHIFT; + + portSyncSpinlockRelease(pPma->pPmaLock); } void @@ -1987,6 +2000,10 @@ NvU64 *pBytesFree ) { - // When memory protection is not enabled all memory is unprotected - pmaGetFreeMemory(pPma, pBytesFree); + portSyncSpinlockAcquire(pPma->pPmaLock); + + *pBytesFree = (pPma->pmaStats.numFreeFrames - + pPma->pmaStats.numFreeFramesProtected) << PMA_PAGE_SHIFT; + + portSyncSpinlockRelease(pPma->pPmaLock); } diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/kernel/gpu/mem_mgr/phys_mem_allocator/phys_mem_allocator_util.c nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/kernel/gpu/mem_mgr/phys_mem_allocator/phys_mem_allocator_util.c --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/kernel/gpu/mem_mgr/phys_mem_allocator/phys_mem_allocator_util.c 2023-10-25 20:21:12.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/kernel/gpu/mem_mgr/phys_mem_allocator/phys_mem_allocator_util.c 2024-03-05 22:13:37.000000000 +0000 @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 2015-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2015-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -41,11 +41,21 @@ return 0; } -static void osAllocReleasePage(NvU64 sysPagePhysAddr) +static void osAllocReleasePage(NvU64 sysPagePhysAddr, NvU32 pageCount) { return; } +static NV_STATUS osOfflinePageAtAddress(NvU64 address) +{ + return NV_ERR_GENERIC; +} + +static NvU8 osGetPageShift(void) +{ + return 0; +} + NV_STATUS scrubCheck(OBJMEMSCRUB *pScrubber, PSCRUB_NODE *ppList, NvU64 *size) { return NV_ERR_GENERIC; @@ -373,6 +383,10 @@ // Since we set the NUMA_REUSE bit when we decide to reuse the pages, // we know exactly which pages to free both to OS and in PMA bitmap. // + NvU8 osPageShift = osGetPageShift(); + + NV_ASSERT_OR_RETURN(PMA_PAGE_SHIFT >= osPageShift, NV_ERR_INVALID_STATE); + for (i = 0; i < numFrames; i++) { currentStatus = pPma->pMapInfo->pmaMapRead(pPma->pRegions[regId], (frameNum + i), NV_TRUE); @@ -380,7 +394,7 @@ if (currentStatus & ATTRIB_NUMA_REUSE) { - osAllocReleasePage(sysPagePhysAddr); + osAllocReleasePage(sysPagePhysAddr, 1 << (PMA_PAGE_SHIFT - osPageShift)); pPma->pMapInfo->pmaMapChangeStateAttribEx(pPma->pRegions[regId], (frameNum + i), STATE_FREE, (STATE_MASK | ATTRIB_NUMA_REUSE)); } @@ -519,7 +533,7 @@ NvU64 evictPageCount, NvU64 *allocPages, NvU64 allocPageCount, - NvU32 pageSize, + NvU64 pageSize, NvU64 physBegin, NvU64 physEnd, MEMORY_PROTECTION prot @@ -824,7 +838,7 @@ ( PMA *pPma, NvLength allocationCount, - NvU32 pageSize, + NvU64 pageSize, PMA_ALLOCATION_OPTIONS *allocationOptions ) { @@ -839,7 +853,15 @@ if ((alignFlag && (alignment == _PMA_2MB)) || pageSize == _PMA_2MB) { - free2mbPages = pPma->pmaStats.numFree2mbPages; + if (allocationOptions->flags & PMA_ALLOCATE_PROTECTED_REGION) + { + free2mbPages = pPma->pmaStats.numFree2mbPagesProtected; + } + else + { + free2mbPages = pPma->pmaStats.numFree2mbPages - + pPma->pmaStats.numFree2mbPagesProtected; + } // If we have at least one page free, don't fail a partial allocation if (partialFlag && (free2mbPages > 0)) @@ -854,7 +876,15 @@ } // Do a quick check and exit early if we are in OOM case - bytesFree = pPma->pmaStats.numFreeFrames << PMA_PAGE_SHIFT; + if (allocationOptions->flags & PMA_ALLOCATE_PROTECTED_REGION) + { + bytesFree = pPma->pmaStats.numFreeFramesProtected << PMA_PAGE_SHIFT; + } + else + { + bytesFree = (pPma->pmaStats.numFreeFrames - + pPma->pmaStats.numFreeFramesProtected) << PMA_PAGE_SHIFT; + } // If we have at least one page free, don't fail a partial allocation if (partialFlag && (bytesFree >= pageSize)) @@ -1225,6 +1255,32 @@ pmaSetBlockStateAttrib(pPma, alignedBlacklistAddr, PMA_GRANULARITY, ATTRIB_BLACKLIST, ATTRIB_BLACKLIST); pBlacklistChunk->bIsValid = NV_TRUE; + // + // In NUMA systems, memory allocation comes directly from kernel, which + // won't check for ATTRIB_BLACKLIST. So pages need to be blacklisted + // directly through the kernel. + // + // Use physOffset without 64K alignment, because kernel may use a different + // page size. + // + // This is only needed for NUMA systems that auto online NUMA memory. + // Other systems (e.g., P9) already do blacklisting in nvidia-persistenced. + // + if (pPma->bNuma && pPma->bNumaAutoOnline) + { + NV_STATUS status; + + NV_PRINTF(LEVEL_INFO, + "NUMA enabled - blacklisting page through kernel at address 0x%llx (GPA) 0x%llx (SPA)\n", + pBlacklistPageBase[blacklistEntryIn].physOffset, + pBlacklistPageBase[blacklistEntryIn].physOffset + pPma->coherentCpuFbBase); + status = osOfflinePageAtAddress(pBlacklistPageBase[blacklistEntryIn].physOffset + pPma->coherentCpuFbBase); + if (status != NV_OK) + { + NV_PRINTF(LEVEL_ERROR, "osOfflinePageAtAddress() failed with status: %d\n", status); + } + } + blacklistEntryIn++; } diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/kernel/gpu/mem_mgr/phys_mem_allocator/regmap.c nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/kernel/gpu/mem_mgr/phys_mem_allocator/regmap.c --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/kernel/gpu/mem_mgr/phys_mem_allocator/regmap.c 2023-10-25 20:21:12.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/kernel/gpu/mem_mgr/phys_mem_allocator/regmap.c 2024-03-05 22:13:38.000000000 +0000 @@ -35,12 +35,13 @@ #include "nvport/nvport.h" #include "nvmisc.h" -#define _UINT_SIZE 64 -#define _UINT_SHIFT 6 - -#define PAGE_BITIDX(n) ((n) & (_UINT_SIZE - 1)) -#define PAGE_MAPIDX(n) ((n) >> _UINT_SHIFT) -#define MAKE_BITMASK(n) ((NvU64)0x1 << (n)) +#define FRAME_TO_U64_SHIFT 6 +#define FRAME_TO_U64_SIZE (1llu << FRAME_TO_U64_SHIFT) +#define FRAME_TO_U64_MASK (FRAME_TO_U64_SIZE - 1llu) + +#define PAGE_BITIDX(n) ((n) & (FRAME_TO_U64_SIZE - 1llu)) +#define PAGE_MAPIDX(n) ((n) >> FRAME_TO_U64_SHIFT) +#define MAKE_BITMASK(n) (1llu << (n)) #define SETBITS(bits, mask, newVal) ((bits & (~mask)) | (mask & newVal)) @@ -105,12 +106,12 @@ if (bits[mapIdx] != 0) { firstSetBit = portUtilCountTrailingZeros64(bits[mapIdx]); - return ((mapIdx << _UINT_SHIFT) + firstSetBit); + return ((mapIdx << FRAME_TO_U64_SHIFT) + firstSetBit); } } // handle edge case - endMask = (NV_U64_MAX >> (_UINT_SIZE - endBitIdx - 1)); + endMask = (NV_U64_MAX >> (FRAME_TO_U64_SIZE - endBitIdx - 1)); if ((bits[endMapIdx] & endMask) == 0) { @@ -140,7 +141,7 @@ NV_ASSERT(startMapIdx == endMapIdx); startMask = (NV_U64_MAX << startBitIdx); - endMask = (NV_U64_MAX >> (_UINT_SIZE - endBitIdx - 1)); + endMask = (NV_U64_MAX >> (FRAME_TO_U64_SIZE - endBitIdx - 1)); handle = (startMask & endMask); if ((handle & bits[startMapIdx]) == 0) @@ -159,43 +160,11 @@ static NvU64 alignUpToMod(NvU64 frame, NvU64 alignment, NvU64 mod) { - if ((frame & (alignment - 1)) <= mod) - return NV_ALIGN_DOWN(frame, alignment) + mod; - else - return NV_ALIGN_UP(frame, alignment) + mod; + return ((frame - mod + alignment - 1ll) & ~(alignment - 1ll)) + mod; } - -// -// Determine if all frames in the 2MB range is not allocated -// They could be in scrubbing or eviction state. -// -static NvBool _pmaRegmapAllFree2mb(PMA_REGMAP *pRegmap, NvU64 frameNum) +static NvU64 alignDownToMod(NvU64 frame, NvU64 alignment, NvU64 mod) { - NvU64 baseFrame = (NV_ALIGN_DOWN((frameNum << PMA_PAGE_SHIFT), _PMA_2MB)) >> PMA_PAGE_SHIFT; - NvU32 numFrames = _PMA_2MB >> PMA_PAGE_SHIFT; - - // Always return false if the last 2MB range is incomplete - if ((baseFrame + numFrames) >= pRegmap->totalFrames) - { - return NV_FALSE; - } - - // - // We only care about STATE_PIN and STATE_UNPIN because: - // Even if the page is marked as SCRUBBING for example, we should not report OOM and prevent - // the clients from scanning the bitmap. - // - if (_checkOne(pRegmap->map[MAP_IDX_ALLOC_PIN], baseFrame, (baseFrame + numFrames - 1)) != -1) - { - return NV_FALSE; - } - - if (_checkOne(pRegmap->map[MAP_IDX_ALLOC_UNPIN], baseFrame, (baseFrame + numFrames - 1)) != -1) - { - return NV_FALSE; - } - - return NV_TRUE; + return ((frame - mod) & ~(alignment - 1ll)) + mod; } // @@ -235,7 +204,7 @@ if (mapIter == endMapIdx) { - mask = (mask >> (_UINT_SIZE - endBitIdx - 1)); + mask = (mask >> (FRAME_TO_U64_SIZE - endBitIdx - 1)); } if (mapIter == startMapIdx) @@ -246,7 +215,7 @@ #ifdef DEBUG_VERBOSE NV_PRINTF(LEVEL_INFO, "mapIter %llx frame %llx mask %llx unpinbitmap %llx pinbitmap %llx evictbitmap %llx", - mapIter, (mapIter << _UINT_SHIFT), mask, unpinBitmap[mapIter], pinBitmap[mapIter], evictBitmap[mapIter]); + mapIter, (mapIter << FRAME_TO_U64_SHIFT), mask, unpinBitmap[mapIter], pinBitmap[mapIter], evictBitmap[mapIter]); #endif // start from the end if ((unpinBitmap[mapIter] & mask) == mask) @@ -259,15 +228,15 @@ if (mapIter == endMapIdx) unevictableFrameIndex = frameEnd; else - unevictableFrameIndex = (mapIter << _UINT_SHIFT) + (_UINT_SIZE - 1); + unevictableFrameIndex = (mapIter << FRAME_TO_U64_SHIFT) + (FRAME_TO_U64_SIZE - 1); break; } #ifdef DEBUG_VERBOSE NV_PRINTF(LEVEL_INFO, "Check leading zero of %llx", ~(unpinBitmap[mapIter] & mask)); #endif - unevictableIndex = _UINT_SIZE - portUtilCountLeadingZeros64((~unpinBitmap[mapIter]) & mask) - 1; - unevictableFrameIndex = (mapIter << _UINT_SHIFT) + unevictableIndex; + unevictableIndex = FRAME_TO_U64_SIZE - portUtilCountLeadingZeros64((~unpinBitmap[mapIter]) & mask) - 1; + unevictableFrameIndex = (mapIter << FRAME_TO_U64_SHIFT) + unevictableIndex; break; } @@ -317,12 +286,13 @@ NvU64 alignedAddrBase; NvU64 frameNum; - NvU64 endFrame, frameStart; + NvU64 frameLimit, frameStart; NvU64 alignment = pageSize; NvU64 frameAlignment, frameAlignmentPadding; NvU64 numFrames = actualSize >> PMA_PAGE_SHIFT; + NvU64 numFramesLimit = numFrames - 1; - endFrame = pRegmap->totalFrames - 1; + frameLimit = pRegmap->totalFrames - 1; if (pRegmap->totalFrames < numFrames) return status; @@ -334,14 +304,14 @@ frameStart = alignUpToMod(0, frameAlignment, frameAlignmentPadding); - for (frameNum = frameStart; frameNum <= endFrame; ) + for (frameNum = frameStart; frameNum <= (frameLimit - numFramesLimit); ) { PMA_PAGESTATUS startFrameAllocState; PMA_PAGESTATUS endFrameAllocState; NvS64 firstUnevictableFrame; startFrameAllocState = pmaRegmapRead(pRegmap, frameNum, NV_TRUE); - endFrameAllocState = pmaRegmapRead(pRegmap, frameNum + numFrames - 1, NV_TRUE); + endFrameAllocState = pmaRegmapRead(pRegmap, frameNum + numFramesLimit, NV_TRUE); if ((endFrameAllocState & STATE_MASK) != STATE_UNPIN) { @@ -359,8 +329,8 @@ } - // First occurrence of 0 in STATE_UNPIN from frameNum to frameNum + numFrames - 1 - firstUnevictableFrame = _pmaRegmapScanNumaUnevictable(pRegmap, frameNum, frameNum + numFrames - 1); + // First occurrence of 0 in STATE_UNPIN from frameNum to frameNum + numFramesLimit + firstUnevictableFrame = _pmaRegmapScanNumaUnevictable(pRegmap, frameNum, frameNum + numFramesLimit); if (firstUnevictableFrame == -1) { @@ -383,119 +353,6 @@ return status; } -// -// Check whether the specified frame range is available for allocation or -// eviction. -// -// Returns: -// - NV_OK if the whole range is available and leaves frameIndex unset. -// -// - NV_ERR_IN_USE if some frames would need to be evicted, and sets frameIndex -// to the first one. -// -// - NV_ERR_NO_MEMORY if some frames are unavailable, and sets frameIndex to -// the first one. -// -// TODO: Would it be better to return the last frame index instead, given how the -// search skips over right past it? -// -static NV_STATUS -_pmaRegmapStatus(PMA_REGMAP *pRegmap, NvU64 start, NvU64 end, NvU64 *frameIndex) -{ - NvS64 diff; - - if ((diff = _checkOne(pRegmap->map[MAP_IDX_ALLOC_PIN], start, end)) != -1) - { - *frameIndex = diff; - return NV_ERR_NO_MEMORY; - } - - if (pRegmap->frameEvictionsInProcess > 0) - { - // - // Pages that are being evicted may be in the free state so we need to - // check for eviction on all frames as long as any eviction is happening - // in the region. - // - if ((diff = _checkOne(pRegmap->map[MAP_IDX_EVICTING], start, end)) != -1) - { - *frameIndex = diff; - return NV_ERR_NO_MEMORY; - } - } - - // - // Check SCRUBBING - // TODO: Skip this check if scrubbing has been completed for all frames. - // - if ((diff = _checkOne(pRegmap->map[MAP_IDX_SCRUBBING], start, end)) != -1) - { - *frameIndex = diff; - return NV_ERR_NO_MEMORY; - } - - if ((diff = _checkOne(pRegmap->map[MAP_IDX_NUMA_REUSE], start, end)) != -1) - { - *frameIndex = diff; - return NV_ERR_NO_MEMORY; - } - - if ((diff = _checkOne(pRegmap->map[MAP_IDX_ALLOC_UNPIN], start, end)) != -1) - { - *frameIndex = diff; - return NV_ERR_IN_USE; - } - - if ((diff = _checkOne(pRegmap->map[MAP_IDX_BLACKLIST], start, end)) != -1) - { - *frameIndex = diff; - return NV_ERR_NO_MEMORY; - } - - return NV_OK; -} - -// -// Return ALL_FREE if all frames in the [start, end] range are available for -// allocation or the first frame index that isn't. -// -static NvS64 -_pmaRegmapAvailable(PMA_REGMAP *pRegmap, NvU64 start, NvU64 end) -{ - NvU64 unavailableFrameIndex; - NV_STATUS frameStatus = _pmaRegmapStatus(pRegmap, start, end, &unavailableFrameIndex); - - if (frameStatus == NV_OK) - return ALL_FREE; - - NV_ASSERT(unavailableFrameIndex >= start); - NV_ASSERT(unavailableFrameIndex <= end); - - return unavailableFrameIndex; -} - -// -// Return ALL_FREE if all frames in the [start, end] range are available for -// allocation, EVICTABLE if some of them would need to be evicted, or the first -// frame index that isn't free nor evictable. -// -static NvS64 -_pmaRegmapEvictable(PMA_REGMAP *pRegmap, NvU64 start, NvU64 end) -{ - NvU64 unavailableFrameIndex; - NvS64 frameStatus = _pmaRegmapStatus(pRegmap, start, end, &unavailableFrameIndex); - - if (frameStatus == NV_OK) - return ALL_FREE; - - NV_ASSERT(unavailableFrameIndex >= start); - NV_ASSERT(unavailableFrameIndex <= end); - - if (frameStatus == NV_ERR_IN_USE) - return EVICTABLE; - - return unavailableFrameIndex; -} void * pmaRegmapInit @@ -528,6 +385,13 @@ pPmaStats->num2mbPages += num2mbPages; pPmaStats->numFree2mbPages += num2mbPages; + if (bProtected) + { + pPmaStats->numFreeFramesProtected += newMap->totalFrames; + pPmaStats->num2mbPagesProtected += num2mbPages; + pPmaStats->numFree2mbPagesProtected += num2mbPages; + } + newMap->bProtected = bProtected; newMap->pPmaStats = pPmaStats; newMap->mapLength = PAGE_MAPIDX(numFrames-1) + 1; @@ -544,6 +408,16 @@ } portMemSet(newMap->map[i], 0, (NvLength) (newMap->mapLength * sizeof(NvU64))); } + { + // + // Simplify logic for 2M tracking. Set the last few nonaligned bits as pinned + // so that the XOR logic for delta 2M tracking is never true for an incomplete final page + // + NvU64 endOffs = (numFrames - 1llu) >> FRAME_TO_U64_SHIFT; + NvU64 endBit = (numFrames - 1llu) & FRAME_TO_U64_MASK; + NvU64 endMask = endBit == FRAME_TO_U64_MASK ? 0llu : ~(NV_U64_MAX >> (FRAME_TO_U64_MASK - endBit)); + newMap->map[MAP_IDX_ALLOC_PIN][endOffs] |= endMask; + } return (void *)newMap; } @@ -562,9 +436,19 @@ pRegmap->pPmaStats->numFreeFrames -= pRegmap->totalFrames; + if (pRegmap->bProtected) + { + pRegmap->pPmaStats->numFreeFramesProtected -= pRegmap->totalFrames; + } + num2mbPages = pRegmap->totalFrames / (_PMA_2MB >> PMA_PAGE_SHIFT); pRegmap->pPmaStats->numFree2mbPages -= num2mbPages; + if (pRegmap->bProtected) + { + pRegmap->pPmaStats->numFree2mbPagesProtected -= num2mbPages; + } + portMemFree(pRegmap); } @@ -578,7 +462,6 @@ // Masks: // STATE_MASK, ATTRIB_MASK // - void pmaRegmapChangeStateAttribEx ( @@ -588,153 +471,178 @@ PMA_PAGESTATUS newStateMask ) { - NvU64 mapIndex, mapOffset, bits, newVal, mask; - NvU32 i, bitWriteCount; - PMA_PAGESTATUS oldState, updatedState; - NvBool bUpdate2mbTracking = NV_FALSE; - PMA_REGMAP *pRegmap = (PMA_REGMAP *)pMap; - - mapIndex = PAGE_MAPIDX(frameNum); - mapOffset = PAGE_BITIDX(frameNum); - - NV_ASSERT(pRegmap != NULL); // possible error code return - NV_ASSERT(mapIndex < pRegmap->mapLength); - - bitWriteCount = PMA_STATE_BITS_PER_PAGE + PMA_ATTRIB_BITS_PER_PAGE; - - mask = (NvU64)MAKE_BITMASK(mapOffset); - - oldState = pmaRegmapRead(pRegmap, frameNum, NV_TRUE); - - // - // If we are going to allocate the 2MB page, we need bookkeeping - // before the bitmap is changed - // - if (((newState & STATE_MASK) != STATE_FREE) && _pmaRegmapAllFree2mb(pRegmap, frameNum)) - { - bUpdate2mbTracking = NV_TRUE; - } - - for (i = 0; i < bitWriteCount; i++) - { - if (NVBIT(i) & newStateMask) - { - newVal = ((NvU64) (newState & (1 << i)) >> i) << mapOffset; - bits = pRegmap->map[i][mapIndex]; - pRegmap->map[i][mapIndex] = (NvU64) SETBITS(bits, mask, newVal); - } - } - - // Update some stats for optimization - updatedState = pmaRegmapRead(pRegmap, frameNum, NV_TRUE); + pmaRegmapChangeBlockStateAttrib(pMap, frameNum, 1, newState, newStateMask); +} - pmaStatsUpdateState(&pRegmap->pPmaStats->numFreeFrames, 1, - oldState, updatedState); +void +pmaRegmapChangePageStateAttribEx +( + void * pMap, + NvU64 startFrame, + NvU64 pageSize, + PMA_PAGESTATUS newState, + PMA_PAGESTATUS newStateMask +) +{ + pmaRegmapChangeBlockStateAttrib(pMap, startFrame, pageSize / _PMA_64KB, newState, newStateMask); +} - // - // If we are freeing a frame, we should check if we need to update the 2MB - // page tracking - // - if (bUpdate2mbTracking || - (((oldState & STATE_MASK) != STATE_FREE) && _pmaRegmapAllFree2mb(pRegmap, frameNum))) - { - pmaStatsUpdateState(&pRegmap->pPmaStats->numFree2mbPages, 1, - oldState, updatedState); - } +static NV_FORCEINLINE +void +_pmaRegmapDoSingleStateChange +( + PMA_REGMAP *pRegmap, + NvU64 idx, + NvU32 newState, + NvU32 writeMask, + NvU64 bitMask, + NvU64 *delta2m, + NvU64 *delta64k +) +{ + // get bits from map + NvU64 pinIn = pRegmap->map[MAP_IDX_ALLOC_PIN][idx]; + NvU64 unpinIn = pRegmap->map[MAP_IDX_ALLOC_UNPIN][idx]; + // Or of state for delta-tracking purposes + NvU64 initialState = pinIn | unpinIn; + // Mask out bits that are being upda + NvU64 maskedPin = pinIn & ~bitMask; + NvU64 maskedUnpin = unpinIn & ~bitMask; + // Update bits in new with bitMask + NvU64 pinRes = ((newState & (1llu << MAP_IDX_ALLOC_PIN)) ? bitMask : 0llu); + NvU64 unpinRes = ((newState & (1llu << MAP_IDX_ALLOC_UNPIN)) ? bitMask : 0llu); + // Output state based on whether writeMask is set + NvU64 pinOut = (writeMask & (1llu << MAP_IDX_ALLOC_PIN)) ? (maskedPin | pinRes) : pinIn; + NvU64 unpinOut = (writeMask & (1llu << MAP_IDX_ALLOC_UNPIN)) ? (maskedUnpin | unpinRes) : unpinIn; + // Or of final state for delta-tracking purposes + NvU64 finalState = pinOut | unpinOut; + NvU64 xored = initialState ^ finalState; + + // Write out new bits + pRegmap->map[MAP_IDX_ALLOC_PIN][idx] = pinOut; + pRegmap->map[MAP_IDX_ALLOC_UNPIN][idx] = unpinOut; + + // Update deltas + (*delta64k) += nvPopCount64(xored); + // Each 2M page is 32 64K pages, so we check each half of a 64-bit qword and xor them + (*delta2m) += ((((NvU32)finalState) == 0) != (((NvU32)initialState) == 0)) + + ((((NvU32)(finalState >> 32)) == 0) != (((NvU32)(initialState >> 32)) == 0)); } void -pmaRegmapChangeStateAttrib +pmaRegmapChangeBlockStateAttrib ( void *pMap, - NvU64 frameNum, + NvU64 frame, + NvU64 len, PMA_PAGESTATUS newState, - NvBool writeAttrib + PMA_PAGESTATUS writeMask ) { - NvU64 mapIndex, mapOffset, bits, newVal, mask; - NvU32 i; - NvU32 bitWriteCount; - PMA_PAGESTATUS oldState; - NvBool bUpdate2mbTracking = NV_FALSE; + NvU64 initialIdx = PAGE_MAPIDX(frame); + NvU64 finalIdx = PAGE_MAPIDX(frame + len - 1llu); + NvU64 initialOffs = PAGE_BITIDX(frame); + NvU64 finalOffs = PAGE_BITIDX(frame + len - 1llu); + NvU64 initialMask = NV_U64_MAX << initialOffs; + NvU64 finalMask = NV_U64_MAX >> (FRAME_TO_U64_MASK - finalOffs); PMA_REGMAP *pRegmap = (PMA_REGMAP *)pMap; + NvU64 i; + NvU64 delta2m = 0, delta64k = 0; - mapIndex = PAGE_MAPIDX(frameNum); - mapOffset = PAGE_BITIDX(frameNum); - - NV_ASSERT(pRegmap != NULL); // possible error code return - NV_ASSERT(mapIndex < pRegmap->mapLength); - - bitWriteCount = (writeAttrib ? - (PMA_STATE_BITS_PER_PAGE + PMA_ATTRIB_BITS_PER_PAGE) : - PMA_STATE_BITS_PER_PAGE); - - mask = (NvU64)MAKE_BITMASK(mapOffset); - - oldState = pmaRegmapRead(pRegmap, frameNum, NV_TRUE); + NV_ASSERT(pRegmap != NULL); + NV_ASSERT(frame + len <= pRegmap->totalFrames); - // - // If we are going to allocate the 2MB page, we need bookkeeping - // before the bitmap is changed - // - if (((newState & STATE_MASK) != STATE_FREE) && _pmaRegmapAllFree2mb(pRegmap, frameNum)) + // Update non-state attributes first in a tight loop. + for (i = PMA_STATE_BITS_PER_PAGE; i < PMA_BITS_PER_PAGE; i++) { - bUpdate2mbTracking = NV_TRUE; + NvU64 j; + NvU64 toWrite = (newState & (1u << i)) ? NV_U64_MAX : 0llu; + if (!((1u << i) & writeMask)) + { + continue; + } + if (initialIdx == finalIdx) + { + pRegmap->map[i][initialIdx] &= ~(initialMask & finalMask); + pRegmap->map[i][initialIdx] |= toWrite & (initialMask & finalMask); + continue; + } + + pRegmap->map[i][initialIdx] &= ~initialMask; + pRegmap->map[i][initialIdx] |= toWrite & initialMask; + + for (j = initialIdx + 1; j < finalIdx; j++) + { + pRegmap->map[i][j] = toWrite; + + } + pRegmap->map[i][finalIdx] &= ~finalMask; + pRegmap->map[i][finalIdx] |= toWrite & finalMask; + } - for (i = 0; i < bitWriteCount; i++) + if (!(writeMask & STATE_MASK)) { - newVal = ((NvU64) (newState & (1 << i)) >> i) << mapOffset; - bits = pRegmap->map[i][mapIndex]; - pRegmap->map[i][mapIndex] = (NvU64) SETBITS(bits, mask, newVal); + return; } - NV_ASSERT(pmaRegmapRead(pRegmap, frameNum, writeAttrib) == newState); - - // Update some stats for optimization - pmaStatsUpdateState(&pRegmap->pPmaStats->numFreeFrames, 1, - oldState, newState); - - // - // If we are freeing a frame, we should check if we need to update the 2MB - // page tracking - // - if (bUpdate2mbTracking || - (((oldState & STATE_MASK) != STATE_FREE) && _pmaRegmapAllFree2mb(pRegmap, frameNum))) + // Entire state is in one NvU64, so exit immediately after + if (initialIdx == finalIdx) { - pmaStatsUpdateState(&pRegmap->pPmaStats->numFree2mbPages, 1, - oldState, newState); + _pmaRegmapDoSingleStateChange(pRegmap, initialIdx, newState, writeMask, initialMask & finalMask, &delta2m, &delta64k); + goto set_regs; + } + // Checks for 64-aligned start/end so we don't have to deal with partial coverage in the main loop + if (initialOffs != 0) + { + // Do first state update with partial NvU64 coverage + _pmaRegmapDoSingleStateChange(pRegmap, initialIdx, newState, writeMask, initialMask, &delta2m, &delta64k); + initialIdx++; + } + if (finalOffs != FRAME_TO_U64_MASK) + { + // Update last partial NvU64 + _pmaRegmapDoSingleStateChange(pRegmap, finalIdx, newState, writeMask, finalMask, &delta2m, &delta64k); + finalIdx--; } -} -void -pmaRegmapChangeState(void *pMap, NvU64 frameNum, PMA_PAGESTATUS newState) -{ - NV_ASSERT(newState <= STATE_PIN); - // Write state bits, but not attrib bits - pmaRegmapChangeStateAttrib((PMA_REGMAP *)pMap, frameNum, newState, NV_FALSE); -} + // Update all full-size + for (i = initialIdx; i <= finalIdx; i++) + { + _pmaRegmapDoSingleStateChange(pRegmap, i, newState, writeMask, NV_U64_MAX, &delta2m, &delta64k); + } -void -pmaRegmapChangePageStateAttrib -( - void * pMap, - NvU64 startFrame, - NvU32 pageSize, - PMA_PAGESTATUS newState, - NvBool writeAttrib -) -{ - NvU32 framesPerPage = pageSize >> PMA_PAGE_SHIFT; - NvU64 frame; - for (frame = startFrame; frame < startFrame + framesPerPage; frame++) +set_regs: + if ((newState & writeMask & STATE_MASK) != 0) + { + pRegmap->pPmaStats->numFreeFrames -= delta64k; + pRegmap->pPmaStats->numFree2mbPages -= delta2m; + } + else + { + pRegmap->pPmaStats->numFreeFrames += delta64k; + pRegmap->pPmaStats->numFree2mbPages += delta2m; + } + if (!pRegmap->bProtected) { - pmaRegmapChangeStateAttrib((PMA_REGMAP *)pMap, frame, newState, writeAttrib); + return; } + if ((writeMask & newState & STATE_MASK) != 0) + { + pRegmap->pPmaStats->numFreeFramesProtected -= delta64k; + pRegmap->pPmaStats->numFree2mbPagesProtected -= delta2m; + } + else + { + pRegmap->pPmaStats->numFreeFramesProtected += delta64k; + pRegmap->pPmaStats->numFree2mbPagesProtected += delta2m; + } + return; } + PMA_PAGESTATUS pmaRegmapRead(void *pMap, NvU64 frameNum, NvBool readAttrib) { @@ -771,148 +679,504 @@ NvBool bSearchEvictable ) { - NvU64 freeStart; - PMA_PAGESTATUS startStatus, endStatus, state; - NvS64 checkDiff; - NvS64 (*useFunc)(PMA_REGMAP *, NvU64, NvU64); - - if (!bSearchEvictable) - { - // Look for available frames - state = STATE_FREE; - checkDiff = ALL_FREE; - useFunc = _pmaRegmapAvailable; - } - else + NvU64 frameBaseIdx = alignUpToMod(localStart, frameAlignment, frameAlignmentPadding); + // + // latestFree stores the highest '0' seen in the given map array in the current run + // ie we have the needed pages if frameBaseIdx + numPages == latestFree. Initialize to first aligned frame + // + NvU64 latestFree[PMA_BITS_PER_PAGE]; + NvU64 i; + for (i = 0; i < PMA_BITS_PER_PAGE; i++) { - // Look for evictable frames - state = STATE_UNPIN; - checkDiff = EVICTABLE; - useFunc = _pmaRegmapEvictable; + latestFree[i] = frameBaseIdx; } - freeStart = localStart; - while ((freeStart + numFrames - 1) <= localEnd) +loop_begin: + // + // Always start a loop iteration with an updated frameBaseIdx by ensuring that latestFree is always >= frameBaseIdx + // frameBaseIdx == latestFree[i] means that there are no observed 0s so far in the current run + // + for (i = 0; i < PMA_BITS_PER_PAGE; i++) { - startStatus = pmaRegmapRead(pRegmap, freeStart, NV_TRUE); - endStatus = pmaRegmapRead(pRegmap, (freeStart + numFrames - 1), NV_TRUE); - - if (endStatus == STATE_FREE || endStatus == state) + if (latestFree[i] < frameBaseIdx) + { + latestFree[i] = frameBaseIdx; + } + } + // At the end of memory, pages not available + if ((frameBaseIdx + numFrames - 1llu) > localEnd) + { + return -1; + } + for (i = 0; i < PMA_BITS_PER_PAGE; i++) + { + // TODO, merge logic so we don't need multiple calls for unpin + if (i == MAP_IDX_ALLOC_UNPIN && bSearchEvictable) + { + continue; + } + while (latestFree[i] < (frameBaseIdx + numFrames)) { - if (startStatus == STATE_FREE || startStatus == state) + // + // All this logic looks complicated, but essentially all it is doing is getting the NvU64 from + // the correct index in the array and shifting and masking so that the first bit is latestFree[i]. + // endOffs is set then to the length of the run of zeros at the beginning + // + NvU64 curMapIdx = PAGE_MAPIDX(latestFree[i]); + NvU64 beginOffs = PAGE_BITIDX(latestFree[i]); + NvU64 mask = beginOffs == 0 ? 0 : NV_U64_MAX << (FRAME_TO_U64_SIZE - beginOffs); + NvU64 curWithOffs = (pRegmap->map[i][curMapIdx] >> beginOffs) | mask; + NvU64 endOffs = portUtilCountTrailingZeros64(curWithOffs); + // + // If no more are free, we have not hit the needed number of pages. Following loop finds + // the next free page + // + if (endOffs == 0) { - NvS64 diff = (*useFunc)(pRegmap, freeStart, (freeStart + numFrames - 1)); - if (diff == checkDiff) + mask = beginOffs == 0 ? 0 : NV_U64_MAX >> (FRAME_TO_U64_SIZE - beginOffs); + NvU64 curMap = pRegmap->map[i][curMapIdx] | mask; + frameBaseIdx = latestFree[i] - beginOffs; + if (curMap != NV_U64_MAX) { - return (NvS64)freeStart; + goto free_found; } - else + curMapIdx++; + frameBaseIdx += FRAME_TO_U64_SIZE; + while (frameBaseIdx <= localEnd) { - // - // Find the next aligned free frame and set it as the start - // frame for next iteration's scan. - // - NV_ASSERT(diff >= 0); - - freeStart = alignUpToMod(diff + 1, frameAlignment, frameAlignmentPadding); - - NV_ASSERT(freeStart != 0); + curMap = pRegmap->map[i][curMapIdx]; + if(curMap != NV_U64_MAX) + { + goto free_found; + } + frameBaseIdx += FRAME_TO_U64_SIZE; + curMapIdx++; } + // No more free pages, exit + return -1; +free_found: + // Found a free page, set frameBaseIdx and go back to the beginning of the loop + frameBaseIdx += portUtilCountTrailingZeros64(~curMap); + frameBaseIdx = alignUpToMod(frameBaseIdx, frameAlignment, frameAlignmentPadding); + goto loop_begin; } - else - { - // Start point isn't free, so bump to check the next aligned frame - freeStart += frameAlignment; - } + latestFree[i] += endOffs; } - else + } + + return frameBaseIdx; +} + +static NvS64 _scanContiguousSearchLoopReverse +( + PMA_REGMAP *pRegmap, + NvU64 numFrames, + NvU64 localStart, + NvU64 localEnd, + NvU64 frameAlignment, + NvU64 frameAlignmentPadding, + NvBool bSearchEvictable +) +{ + NvU64 realAlign = (frameAlignmentPadding + numFrames) & (frameAlignment - 1ll); + NvU64 frameBaseIdx = alignDownToMod(localEnd + 1llu, frameAlignment, realAlign); + // + // latestFree stores the lowest '0' seen in the given map array in the current run + // ie we have the needed pages if frameBaseIdx - numPages == latestFree. Initialize to last aligned frame + // + NvU64 latestFree[PMA_BITS_PER_PAGE]; + NvU64 i; + for (i = 0; i < PMA_BITS_PER_PAGE; i++) + { + latestFree[i] = frameBaseIdx; + } +loop_begin: + // + // Always start a loop iteration with an updated frameBaseIdx by ensuring that latestFree is always <= frameBaseIdx + // frameBaseIdx == latestFree[i] means that there are no observed 0s so far in the current run + // + for (i = 0; i < PMA_BITS_PER_PAGE; i++) + { + if (latestFree[i] > frameBaseIdx) { + latestFree[i] = frameBaseIdx; + } + } + // At the beginning of memory, pages not available + if ((localStart + numFrames) > frameBaseIdx) + { + return -1; + } + for (i = 0; i < PMA_BITS_PER_PAGE; i++) + { + // TODO, merge logic so we don't need multiple calls for unpin + if (i == MAP_IDX_ALLOC_UNPIN && bSearchEvictable) + { + continue; + } + while (latestFree[i] > (frameBaseIdx - numFrames)) + { + // + // All this logic looks complicated, but essentially all it is doing is getting the NvU64 from + // the correct index in the array and shifting and masking so that the last bit is latestFree[i]. + // endOffs is set then to the length of the run of zeros at the end // - // End point isn't usable, so jump to after the end to check again - // However, align the new start point properly before next iteration. + NvU64 curId = latestFree[i] - 1llu; + NvU64 curMapIdx = PAGE_MAPIDX(curId); + NvU64 beginOffs = PAGE_BITIDX(curId); + NvU64 mask = beginOffs == FRAME_TO_U64_MASK ? 0 : NV_U64_MAX >> (1llu + beginOffs); + NvU64 curWithOffs = (pRegmap->map[i][curMapIdx] << (FRAME_TO_U64_MASK - beginOffs)) | mask; + NvU64 endOffs = portUtilCountLeadingZeros64(curWithOffs); // - freeStart += NV_ALIGN_UP(numFrames, frameAlignment); + // If no more are free, we have not hit the needed number of pages. Following loop finds + // the next free page + // + if (endOffs == 0) + { + mask = beginOffs == FRAME_TO_U64_MASK ? 0 : NV_U64_MAX << (1llu + beginOffs); + NvU64 curMap = (pRegmap->map[i][curMapIdx]) | mask; + frameBaseIdx = latestFree[i] + FRAME_TO_U64_MASK - beginOffs; + if (curMap != NV_U64_MAX) + { + goto free_found; + } + curMapIdx--; + frameBaseIdx -= FRAME_TO_U64_SIZE; + while (frameBaseIdx > localStart) + { + curMap = pRegmap->map[i][curMapIdx]; + if(curMap != NV_U64_MAX) + { + goto free_found; + } + frameBaseIdx -= FRAME_TO_U64_SIZE; + curMapIdx--; + } + // No more free pages, exit + return -1; +free_found: + // Found a free page, set frameBaseIdx and go back to the beginning of the loop + frameBaseIdx -= portUtilCountLeadingZeros64(~curMap); + frameBaseIdx = alignDownToMod(frameBaseIdx, frameAlignment, realAlign); + goto loop_begin; + } + latestFree[i] -= endOffs; } } - return -1; + return frameBaseIdx - numFrames; } -static NvS64 _scanContiguousSearchLoopReverse +static NV_FORCEINLINE +NvU64 +_scanDiscontiguousSearchLoop ( PMA_REGMAP *pRegmap, - NvU64 numFrames, + NvU64 numPages, + NvU64 framesPerPage, NvU64 localStart, NvU64 localEnd, NvU64 frameAlignment, NvU64 frameAlignmentPadding, - NvBool bSearchEvictable + NvU64 *pPages, + NvU64 *pNumEvictablePages ) { - NvU64 freeStart; - PMA_PAGESTATUS startStatus, endStatus, state; - NvS64 checkDiff; - NvS64 (*useFunc)(PMA_REGMAP *, NvU64, NvU64); - - if (!bSearchEvictable) - { - // Look for available frames - state = STATE_FREE; - checkDiff = ALL_FREE; - useFunc = _pmaRegmapAvailable; + NvU64 frameBaseIdx = alignUpToMod(localStart, frameAlignment, frameAlignmentPadding); + + // + // latestFree stores the lowest '0' seen in the given map array in the current run + // ie we have the needed pages if frameBaseIdx - numPages == latestFree. Initialize to last aligned frame + // + NvU64 latestFree[PMA_BITS_PER_PAGE]; + NvU64 totalFound = 0; + + // Evictable pages count down from end of array + NvU64 curEvictPage = numPages; + NvBool bEvictablePage = NV_FALSE; + NvU64 i; + + for (i = 0; i < PMA_BITS_PER_PAGE; i++) + { + latestFree[i] = frameBaseIdx; } - else +loop_begin: + // + // Always start a loop iteration with an updated frameBaseIdx by ensuring that latestFree is always >= frameBaseIdx + // frameBaseIdx == latestFree[i] means that there are no observed 0s so far in the current run + // + for (i = 0; i < PMA_BITS_PER_PAGE; i++) { - // Look for evictable frames - state = STATE_UNPIN; - checkDiff = EVICTABLE; - useFunc = _pmaRegmapEvictable; + if (latestFree[i] < frameBaseIdx) + { + latestFree[i] = frameBaseIdx; + } } - // First frame from end able to accommodate num_frames allocation. - freeStart = localEnd + 1 - numFrames; - freeStart -= (freeStart - localStart) % frameAlignment; + // Initialize to standard free page state + bEvictablePage = NV_FALSE; - while (freeStart >= localStart && (NvS64)freeStart >= 0) + // At the end of memory, pages not available + if ((frameBaseIdx + framesPerPage - 1llu) > localEnd) { - startStatus = pmaRegmapRead(pRegmap, freeStart, NV_TRUE); - endStatus = pmaRegmapRead(pRegmap, (freeStart + numFrames - 1), NV_TRUE); + *pNumEvictablePages = numPages - curEvictPage; + return totalFound; + } - if (startStatus == STATE_FREE || startStatus == state) + for (i = 0; i < PMA_BITS_PER_PAGE; i++) + { + // If array is not already full of evictable and free pages, go to evictable loop + if ((i != MAP_IDX_ALLOC_UNPIN) || (curEvictPage <= totalFound)) { - if (endStatus == STATE_FREE || endStatus == state) + while (latestFree[i] < (frameBaseIdx + framesPerPage)) { - NvS64 diff = (*useFunc)(pRegmap, freeStart, (freeStart + numFrames - 1)); - if (diff == checkDiff) + // + // All this logic looks complicated, but essentially all it is doing is getting the NvU64 from + // the correct index in the array and shifting and masking so that the first bit is latestFree[i]. + // endOffs is set then to the length of the run of zeros at the beginning + // + NvU64 curMapIdx = PAGE_MAPIDX(latestFree[i]); + NvU64 beginOffs = PAGE_BITIDX(latestFree[i]); + NvU64 mask = beginOffs == 0 ? 0 : NV_U64_MAX << (FRAME_TO_U64_SIZE - beginOffs); + NvU64 curWithOffs = (pRegmap->map[i][curMapIdx] >> beginOffs) | mask; + NvU64 endOffs = portUtilCountTrailingZeros64(curWithOffs); + // + // If no more are free, we have not hit the needed number of pages. Following loop finds + // the next free page + // + if (endOffs == 0) { - return (NvS64)freeStart; + mask = beginOffs == 0 ? 0 : NV_U64_MAX >> (FRAME_TO_U64_SIZE - beginOffs); + NvU64 curMap = pRegmap->map[i][curMapIdx] | mask; + frameBaseIdx = latestFree[i] - beginOffs; + if (curMap != NV_U64_MAX) + { + goto free_found; + } + curMapIdx++; + frameBaseIdx += FRAME_TO_U64_SIZE; + while (frameBaseIdx <= localEnd) + { + curMap = pRegmap->map[i][curMapIdx]; + if(curMap != NV_U64_MAX) + { + goto free_found; + } + frameBaseIdx += FRAME_TO_U64_SIZE; + curMapIdx++; + } + // No more free pages, exit + *pNumEvictablePages = numPages - curEvictPage; + return totalFound; +free_found: + // Found a free page, set frameBaseIdx and go back to the beginning of the loop + frameBaseIdx += portUtilCountTrailingZeros64(~curMap); + frameBaseIdx = alignUpToMod(frameBaseIdx, frameAlignment, frameAlignmentPadding); + goto loop_begin; } - else + latestFree[i] += endOffs; + } + } + else + { + // Loop to check if current range has an unpinned page, then it gets stored in the evictable area + while (latestFree[i] < (frameBaseIdx + framesPerPage)) + { + // Basically same as above loop, just not exiting if 0 not found, instead setting bEvictablePage + NvU64 curMapIdx = PAGE_MAPIDX(latestFree[i]); + NvU64 beginOffs = PAGE_BITIDX(latestFree[i]); + NvU64 mask = beginOffs == 0 ? 0 : NV_U64_MAX << (FRAME_TO_U64_SIZE - beginOffs); + NvU64 curWithOffs = (pRegmap->map[i][curMapIdx] >> beginOffs) | mask; + NvU64 endOffs = portUtilCountTrailingZeros64(curWithOffs); + latestFree[i] += endOffs; + if (endOffs == 0) { - NV_ASSERT(diff >= 0); - - // Set end point to one frame before the first unavailable frame found - freeStart = diff - numFrames; - freeStart -= (freeStart - localStart) % frameAlignment; + bEvictablePage = NV_TRUE; + break; } } - else + } + } + + // Store evictable pages at end of array to not interfere with free pages + if (bEvictablePage) + { + curEvictPage--; + pPages[curEvictPage] = frameBaseIdx; + frameBaseIdx += framesPerPage; + goto loop_begin; + } + + pPages[totalFound] = frameBaseIdx; + totalFound++; + frameBaseIdx += framesPerPage; + + // Found all needed pages (all free and not STATE_UNPIN) + if (totalFound == numPages) + { + *pNumEvictablePages = 0; + return numPages; + } + goto loop_begin; +} + +static NV_FORCEINLINE +NvU64 +_scanDiscontiguousSearchLoopReverse +( + PMA_REGMAP *pRegmap, + NvU64 numPages, + NvU64 framesPerPage, + NvU64 localStart, + NvU64 localEnd, + NvU64 frameAlignment, + NvU64 frameAlignmentPadding, + NvU64 *pPages, + NvU64 *pNumEvictablePages +) +{ + NvU64 realAlign = (frameAlignmentPadding + framesPerPage) & (frameAlignment - 1ll); + NvU64 frameBaseIdx = alignDownToMod(localEnd+1llu, frameAlignment, realAlign); + + // + // latestFree stores the lowest '0' seen in the given map array in the current run + // ie we have the needed pages if frameBaseIdx - numPages == latestFree. Initialize to last aligned frame + // + NvU64 latestFree[PMA_BITS_PER_PAGE]; + NvU64 totalFound = 0; + + // Evictable pages count down from end of array + NvU64 curEvictPage = numPages; + NvBool bEvictablePage = NV_FALSE; + NvU64 i; + + for (i = 0; i < PMA_BITS_PER_PAGE; i++) + { + latestFree[i] = frameBaseIdx; + } +loop_begin: + // + // Always start a loop iteration with an updated frameBaseIdx by ensuring that latestFree is always <= frameBaseIdx + // frameBaseIdx == latestFree[i] means that there are no observed 0s so far in the current run + // + for (i = 0; i < PMA_BITS_PER_PAGE; i++) + { + if (latestFree[i] > frameBaseIdx) + { + latestFree[i] = frameBaseIdx; + } + } + + // Initialize to standard free page state + bEvictablePage = NV_FALSE; + + // At the beginning of memory, pages not available + if ((localStart + framesPerPage) > frameBaseIdx) + { + *pNumEvictablePages = numPages - curEvictPage; + return totalFound; + } + + for (i = 0; i < PMA_BITS_PER_PAGE; i++) + { + // If array is not already full of evictable and free pages, go to evictable loop + if ((i != MAP_IDX_ALLOC_UNPIN) || (curEvictPage <= totalFound)) + { + while (latestFree[i] > (frameBaseIdx - framesPerPage)) { - // Start point isn't free, so bump to check the next aligned frame - freeStart -= frameAlignment; + // + // All this logic looks complicated, but essentially all it is doing is getting the NvU64 from + // the correct index in the array and shifting and masking so that the last bit is latestFree[i]. + // endOffs is set then to the length of the run of zeros at the end + // + NvU64 curId = latestFree[i] - 1llu; + NvU64 curMapIdx = PAGE_MAPIDX(curId); + NvU64 beginOffs = PAGE_BITIDX(curId); + NvU64 mask = beginOffs == FRAME_TO_U64_MASK ? 0 : NV_U64_MAX >> (1llu + beginOffs); + NvU64 curWithOffs = (pRegmap->map[i][curMapIdx] << (FRAME_TO_U64_MASK - beginOffs)) | mask; + NvU64 endOffs = portUtilCountLeadingZeros64(curWithOffs); + + // + // If no more are free, we have not hit the needed number of pages. Following loop finds + // the next free page + // + if (endOffs == 0) + { + mask = beginOffs == FRAME_TO_U64_MASK ? 0 : NV_U64_MAX << (1llu + beginOffs); + NvU64 curMap = pRegmap->map[i][curMapIdx] | mask; + frameBaseIdx = latestFree[i] + FRAME_TO_U64_MASK - beginOffs; + if (curMap != NV_U64_MAX) + { + goto free_found; + } + curMapIdx--; + frameBaseIdx -= 64; + while (frameBaseIdx > localStart) + { + curMap = pRegmap->map[i][curMapIdx]; + if(curMap != NV_U64_MAX) + { + goto free_found; + } + frameBaseIdx -= 64; + curMapIdx--; + } + + // No more free pages, exit + *pNumEvictablePages = numPages - curEvictPage; + return totalFound; +free_found: + // Found a free page, set frameBaseIdx and go back to the beginning of the loop + frameBaseIdx -= portUtilCountLeadingZeros64(~curMap); + frameBaseIdx = alignDownToMod(frameBaseIdx, frameAlignment, realAlign); + goto loop_begin; + } + latestFree[i] -= endOffs; } } else { - // - // End point isn't usable, so jump to after the end to check again - // However, align the new start point properly before next iteration. - // - freeStart -= NV_ALIGN_UP(numFrames, frameAlignment); + // Loop to check if current range has an unpinned page, then it gets stored in the evictable area + while (latestFree[i] > (frameBaseIdx - framesPerPage)) + { + // Basically same as above loop, just not exiting if 0 not found, instead setting bEvictablePage + NvU64 curId = latestFree[i] - 1llu; + NvU64 curMapIdx = PAGE_MAPIDX(curId); + NvU64 beginOffs = PAGE_BITIDX(curId); + NvU64 mask = beginOffs == FRAME_TO_U64_MASK ? 0 : NV_U64_MAX >> (1llu + beginOffs); + NvU64 curWithOffs = (pRegmap->map[i][curMapIdx] << (FRAME_TO_U64_MASK - beginOffs)) | mask; + NvU64 endOffs = portUtilCountLeadingZeros64(curWithOffs); + latestFree[i] -= endOffs; + if (endOffs == 0) + { + bEvictablePage = NV_TRUE; + break; + } + } } } - return -1; + frameBaseIdx -= framesPerPage; + + // Store evictable pages at end of array to not interfere with free pages + if (bEvictablePage) + { + curEvictPage--; + pPages[curEvictPage] = frameBaseIdx; + goto loop_begin; + } + + pPages[totalFound] = frameBaseIdx; + totalFound++; + + // Found all needed pages (all free and not STATE_UNPIN) + if (totalFound == numPages) + { + *pNumEvictablePages = 0; + return numPages; + } + + goto loop_begin; } // @@ -928,7 +1192,7 @@ NvU64 rangeEnd, NvU64 numPages, NvU64 *freeList, - NvU32 pageSize, + NvU64 pageSize, NvU64 alignment, NvU64 *numPagesAlloc, NvBool bSkipEvict, @@ -964,10 +1228,6 @@ } localStart = alignUpToMod(localStart, frameAlignment, frameAlignmentPadding); - NV_PRINTF(LEVEL_INFO, - "Scanning with addrBase 0x%llx in frame range 0x%llx..0x%llx, pages to allocate 0x%llx\n", - addrBase, localStart, localEnd, numPages); - if (!bReverseAlloc) { frameFound = _scanContiguousSearchLoop(pRegmap, numFrames, localStart, localEnd, @@ -1022,17 +1282,19 @@ NvU64 rangeEnd, NvU64 numPages, NvU64 *freeList, - NvU32 pageSize, + NvU64 pageSize, NvU64 alignment, NvU64 *numPagesAlloc, NvBool bSkipEvict, NvBool bReverseAlloc ) { - NvU64 freeStart, found, framesPerPage, localStart, localEnd; - NvU64 alignedAddrBase, frameAlignmentPadding; - PMA_PAGESTATUS startStatus, endStatus; - PMA_REGMAP *pRegmap = (PMA_REGMAP *)pMap; + PMA_REGMAP *pRegmap = (PMA_REGMAP*) pMap; + NvU64 localStart, localEnd, framesPerPage, alignedAddrBase, frameAlignmentPadding; + NvU64 freeFound = 0, evictFound = 0; + NvU64 totalFound = 0; + NV_STATUS status = NV_OK; + NvU64 i; NV_ASSERT(alignment == pageSize); @@ -1060,101 +1322,69 @@ else { localStart = 0; - localEnd = pRegmap->totalFrames-1; + localEnd = pRegmap->totalFrames - 1; } - localStart = alignUpToMod(localStart, framesPerPage, frameAlignmentPadding); - found = 0; + // + // Do the actual scanning here. The scanning functions return free pages at the beginning of + // the array, and evictable pages in reverse order at the end of the array + // if (!bReverseAlloc) { - freeStart = localStart; + freeFound = _scanDiscontiguousSearchLoop(pRegmap, numPages, framesPerPage, + localStart, localEnd, alignment >> PMA_PAGE_SHIFT, + frameAlignmentPadding, freeList, &evictFound); } else { - // First frame from end able to accommodate page allocation. - freeStart = localEnd + 1 - framesPerPage; - freeStart -= (freeStart - localStart) % framesPerPage; + freeFound = _scanDiscontiguousSearchLoopReverse(pRegmap, numPages, framesPerPage, + localStart, localEnd, alignment >> PMA_PAGE_SHIFT, + frameAlignmentPadding, freeList, &evictFound); } - NV_PRINTF(LEVEL_INFO, - "Scanning with addrBase 0x%llx in frame range 0x%llx..0x%llx, pages to allocate 0x%llx\n", - addrBase, localStart, localEnd, numPages); - - // scan for allocatable pages - // two-pass algorithm - while (found != numPages) - { - if (!bReverseAlloc) - { - if ((freeStart + framesPerPage - 1) > localEnd) break; - } - else - { - if (freeStart < localStart || (NvS64)freeStart < 0) break; - } + *numPagesAlloc = freeFound; - startStatus = pmaRegmapRead(pRegmap, freeStart, NV_TRUE); - endStatus = pmaRegmapRead(pRegmap, (freeStart + framesPerPage - 1), NV_TRUE); + // Scanning implementations don't actually decrement evictFound, so adjust appropriately here + evictFound = freeFound + evictFound > numPages ? numPages - freeFound : evictFound; - if (startStatus == STATE_FREE) - { - if(endStatus == STATE_FREE) - { - NvS64 diff = _pmaRegmapAvailable(pRegmap, freeStart, (freeStart + framesPerPage - 1)); - if (diff == ALL_FREE) - { - freeList[found++] = addrBase + (freeStart << PMA_PAGE_SHIFT); - } - } - } - freeStart = !bReverseAlloc ? (freeStart + framesPerPage) : (freeStart - framesPerPage); - } - - *numPagesAlloc = found; - if(found == numPages) return NV_OK; - if(bSkipEvict) return NV_ERR_NO_MEMORY; - - if (!bReverseAlloc) + // Not enough pages + if (((freeFound + evictFound) != numPages) || + (bSkipEvict && (freeFound != numPages))) { - freeStart = localStart; + status = NV_ERR_NO_MEMORY; } - else + else if (evictFound != 0) { - // First frame from end able to accommodate page allocation. - freeStart = localEnd + 1 - framesPerPage; - freeStart -= (freeStart - localStart) % framesPerPage; + status = NV_ERR_IN_USE; } - while (found != numPages) - { - if (!bReverseAlloc) - { - if ((freeStart + framesPerPage - 1) > localEnd) return NV_ERR_NO_MEMORY; - } - else - { - if (freeStart < localStart || (NvS64)freeStart < 0) return NV_ERR_NO_MEMORY; - } - startStatus = pmaRegmapRead(pRegmap, freeStart, NV_TRUE); - endStatus = pmaRegmapRead(pRegmap, (freeStart + framesPerPage - 1), NV_TRUE); + // Set totalFound appropriately to shift pages at the end of the function + totalFound = freeFound + evictFound; + if (bSkipEvict) + { + totalFound = freeFound; + goto alignAndReturn; + } - if (startStatus == STATE_FREE || startStatus == STATE_UNPIN) - { - if(endStatus == STATE_FREE || endStatus == STATE_UNPIN) - { - NvS64 diff = _pmaRegmapEvictable(pRegmap, freeStart, (freeStart + framesPerPage - 1)); - if (diff == EVICTABLE) - { - freeList[found++] = addrBase + (freeStart << PMA_PAGE_SHIFT); - } - } - } - freeStart = !bReverseAlloc ? (freeStart + framesPerPage) : (freeStart - framesPerPage); + // End of list contains the evictable pages, swap elements from beginning of range to end + for (i = (numPages - freeFound) >> 1; i != 0; i--) + { + NvU64 temp = freeList[freeFound + i - 1llu]; + freeList[freeFound + i - 1llu] = freeList[numPages - i]; + freeList[numPages - i] = temp; } - return NV_ERR_IN_USE; +alignAndReturn: + while (totalFound != 0) + { + totalFound--; + freeList[totalFound] <<= PMA_PAGE_SHIFT; + freeList[totalFound] += addrBase; + } + return status; } + void pmaRegmapGetSize ( @@ -1192,9 +1422,9 @@ bitmap |= (~0ULL) << PAGE_BITIDX(pRegmap->totalFrames); } - if (maxZerosGet(bitmap) == _UINT_SIZE) + if (maxZerosGet(bitmap) == FRAME_TO_U64_SIZE) { - mapTrailZeros += _UINT_SIZE; + mapTrailZeros += FRAME_TO_U64_SIZE; } else { diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/kernel/gpu/mem_mgr/sec2_utils.c nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/kernel/gpu/mem_mgr/sec2_utils.c --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/kernel/gpu/mem_mgr/sec2_utils.c 1970-01-01 00:00:00.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/kernel/gpu/mem_mgr/sec2_utils.c 2024-03-05 22:13:38.000000000 +0000 @@ -0,0 +1,660 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + + +#include "core/core.h" +#include "kernel/gpu/intr/intr.h" +#include "kernel/gpu/mem_mgr/channel_utils.h" +#include "rmapi/rs_utils.h" +#include "utils/nvassert.h" +#include "core/prelude.h" +#include "core/locks.h" +#include "gpu/mem_mgr/sec2_utils.h" +#include "gpu/subdevice/subdevice.h" +#include "kernel/gpu/mem_mgr/ce_utils_sizes.h" +#include "kernel/gpu/mig_mgr/kernel_mig_manager.h" +#include "nvrm_registry.h" +#include "platform/chipset/chipset.h" +#include "gpu/mem_mgr/heap.h" + + +#include "class/clcba2.h" // HOPPER_SEC2_WORK_LAUNCH_A +#include "class/cl003e.h" // NV01_MEMORY_SYSTEM +#include "class/cl50a0.h" // NV50_MEMORY_VIRTUAL + +#include "class/cl0080.h" + +#include "gpu/conf_compute/conf_compute.h" +#include "gpu/conf_compute/ccsl.h" + +static NV_STATUS +_sec2GetClass(OBJGPU *pGpu, NvU32 *pClass) +{ + NV_STATUS status; + NvU32 numClasses = 0; + NvU32 *pClassList = NULL; + NvU32 class = 0; + + NV_ASSERT_OR_RETURN(pClass != NULL, NV_ERR_INVALID_ARGUMENT); + NV_ASSERT_OK_OR_RETURN(gpuGetClassList(pGpu, &numClasses, NULL, ENG_SEC2)); + NV_ASSERT_OR_RETURN((numClasses != 0), NV_ERR_NOT_SUPPORTED); + + pClassList = portMemAllocNonPaged(sizeof(*pClassList) * numClasses); + NV_ASSERT_OR_RETURN((pClassList != NULL), NV_ERR_INSUFFICIENT_RESOURCES); + + status = gpuGetClassList(pGpu, &numClasses, pClassList, ENG_SEC2); + if (status == NV_OK) + { + for (NvU32 i = 0; i < numClasses; i++) + { + class = NV_MAX(class, pClassList[i]); + } + if (class == 0) + { + status = NV_ERR_INVALID_STATE; + } + *pClass = class; + } + portMemFree(pClassList); + return status; +} + +static NV_STATUS +_sec2AllocAndMapBuffer +( + Sec2Utils *pSec2Utils, + NvU32 size, + SEC2UTILS_BUFFER_INFO *pSec2Buf +) +{ + RM_API *pRmApi = rmapiGetInterface(RMAPI_GPU_LOCK_INTERNAL); + NV_MEMORY_ALLOCATION_PARAMS memAllocParams; + MemoryManager *pMemoryManager = GPU_GET_MEMORY_MANAGER(pSec2Utils->pGpu); + + pSec2Buf->size = size; + + // allocate the physmem + portMemSet(&memAllocParams, 0, sizeof(memAllocParams)); + memAllocParams.owner = HEAP_OWNER_RM_CLIENT_GENERIC; + memAllocParams.type = NVOS32_TYPE_IMAGE; + memAllocParams.size = pSec2Buf->size; + memAllocParams.attr = DRF_DEF(OS32, _ATTR, _LOCATION, _PCI) | + DRF_DEF(OS32, _ATTR, _COHERENCY, _UNCACHED); + memAllocParams.attr2 = DRF_DEF(OS32, _ATTR2, _MEMORY_PROTECTION, _UNPROTECTED); + memAllocParams.flags = 0; + memAllocParams.internalflags = NVOS32_ALLOC_INTERNAL_FLAGS_SKIP_SCRUB; + + NV_CHECK_OK_OR_RETURN( + LEVEL_ERROR, + pRmApi->AllocWithHandle(pRmApi, + pSec2Utils->hClient, + pSec2Utils->hDevice, + pSec2Buf->hPhysMem, + NV01_MEMORY_SYSTEM, + &memAllocParams, + sizeof(memAllocParams))); + + // allocate Virtual Memory + portMemSet(&memAllocParams, 0, sizeof(memAllocParams)); + memAllocParams.owner = HEAP_OWNER_RM_CLIENT_GENERIC; + memAllocParams.type = NVOS32_TYPE_IMAGE; + memAllocParams.size = pSec2Buf->size; + memAllocParams.attr = DRF_DEF(OS32, _ATTR, _LOCATION, _PCI); + memAllocParams.attr2 = NVOS32_ATTR2_NONE; + memAllocParams.flags |= NVOS32_ALLOC_FLAGS_VIRTUAL; + memAllocParams.hVASpace = pSec2Buf->hVASpace; + + NV_CHECK_OK_OR_RETURN( + LEVEL_ERROR, + pRmApi->AllocWithHandle(pRmApi, + pSec2Utils->hClient, + pSec2Utils->hDevice, + pSec2Buf->hVirtMem, + NV50_MEMORY_VIRTUAL, + &memAllocParams, + sizeof(memAllocParams))); + + // map the buffer + OBJSYS *pSys = SYS_GET_INSTANCE(); + OBJCL *pCl = SYS_GET_CL(pSys); + NvU32 cacheSnoopFlag = 0; + if (pCl->getProperty(pCl, PDB_PROP_CL_IS_CHIPSET_IO_COHERENT)) + { + cacheSnoopFlag = DRF_DEF(OS46, _FLAGS, _CACHE_SNOOP, _ENABLE); + } + NV_CHECK_OK_OR_RETURN( + LEVEL_ERROR, + pRmApi->Map(pRmApi, pSec2Utils->hClient, pSec2Utils->hDevice, + pSec2Buf->hVirtMem, pSec2Buf->hPhysMem, 0, pSec2Buf->size, + DRF_DEF(OS46, _FLAGS, _KERNEL_MAPPING, _ENABLE) | cacheSnoopFlag, + &pSec2Buf->gpuVA)); + + pSec2Buf->pMemDesc = memmgrMemUtilsGetMemDescFromHandle(pMemoryManager, pSec2Utils->hClient, pSec2Buf->hPhysMem); + return NV_OK; +} + +static NV_STATUS +_sec2InitBuffers +( + Sec2Utils *pSec2Utils +) +{ + NV_ASSERT_OK_OR_RETURN(serverutilGenResourceHandle(pSec2Utils->hClient, &pSec2Utils->scrubMthdAuthTagBuf.hPhysMem)); + NV_ASSERT_OK_OR_RETURN(serverutilGenResourceHandle(pSec2Utils->hClient, &pSec2Utils->scrubMthdAuthTagBuf.hVirtMem)); + NV_ASSERT_OK_OR_RETURN(_sec2AllocAndMapBuffer(pSec2Utils, RM_PAGE_SIZE_64K, &pSec2Utils->scrubMthdAuthTagBuf)); + + NV_ASSERT_OK_OR_RETURN(serverutilGenResourceHandle(pSec2Utils->hClient, &pSec2Utils->semaMthdAuthTagBuf.hPhysMem)); + NV_ASSERT_OK_OR_RETURN(serverutilGenResourceHandle(pSec2Utils->hClient, &pSec2Utils->semaMthdAuthTagBuf.hVirtMem)); + NV_ASSERT_OK_OR_RETURN(_sec2AllocAndMapBuffer(pSec2Utils, RM_PAGE_SIZE_64K, &pSec2Utils->semaMthdAuthTagBuf)); + return NV_OK; +} + +NV_STATUS +sec2utilsConstruct_IMPL +( + Sec2Utils *pSec2Utils, + OBJGPU *pGpu, + KERNEL_MIG_GPU_INSTANCE *pKernelMIGGPUInstance +) +{ + NV_STATUS status = NV_OK; + NV_ASSERT_OR_RETURN(pGpu, NV_ERR_INVALID_STATE); + MemoryManager *pMemoryManager = GPU_GET_MEMORY_MANAGER(pGpu); + + ConfidentialCompute *pConfCompute = GPU_GET_CONF_COMPUTE(pGpu); + NV_ASSERT_OR_RETURN(((pConfCompute != NULL) && (pConfCompute->getProperty(pCC, PDB_PROP_CONFCOMPUTE_CC_FEATURE_ENABLED))), + NV_ERR_NOT_SUPPORTED); + + pSec2Utils->pGpu = pGpu; + + // Allocate channel with RM internal client + RM_API *pRmApi = rmapiGetInterface(RMAPI_GPU_LOCK_INTERNAL); + RmClient *pClient = NULL; + + OBJCHANNEL *pChannel = (OBJCHANNEL *) portMemAllocNonPaged(sizeof(OBJCHANNEL)); + NV_ASSERT_OR_RETURN(pChannel != NULL, NV_ERR_INSUFFICIENT_RESOURCES); + portMemSet(pChannel, 0, sizeof(OBJCHANNEL)); + + // Allocate client + NV_ASSERT_OK_OR_GOTO(status, pRmApi->AllocWithHandle(pRmApi, NV01_NULL_OBJECT, NV01_NULL_OBJECT, + NV01_NULL_OBJECT, NV01_ROOT, &pSec2Utils->hClient, + sizeof(pSec2Utils->hClient)), cleanup); + + pChannel->hClient = pSec2Utils->hClient; + pClient = serverutilGetClientUnderLock(pChannel->hClient); + NV_ASSERT_OR_GOTO(pClient != NULL, free_client); + + NV_ASSERT_OK_OR_GOTO(status, serverGetClientUnderLock(&g_resServ, pChannel->hClient, &pChannel->pRsClient), free_client); + + NV_ASSERT_OK_OR_GOTO(status, clientSetHandleGenerator(staticCast(pClient, RsClient), 1U, ~0U - 1U), free_client); + + pChannel->bClientAllocated = NV_TRUE; + pChannel->pGpu = pGpu; + + pChannel->deviceId = NV01_NULL_OBJECT; + pChannel->subdeviceId = NV01_NULL_OBJECT; + + pChannel->pKernelMIGGpuInstance = pKernelMIGGPUInstance; + + pChannel->hVASpaceId = NV01_NULL_OBJECT; + pChannel->bUseVasForCeCopy = NV_FALSE; + + pChannel->type = SWL_SCRUBBER_CHANNEL; + pChannel->engineType = RM_ENGINE_TYPE_SEC2; + + // Detect if we can enable fast scrub on this channel + NV_ASSERT_OK_OR_GOTO(status, _sec2GetClass(pGpu, &pSec2Utils->sec2Class), free_client); + pChannel->sec2Class = pSec2Utils->sec2Class; + + // Set up various channel resources + NV_ASSERT_OK_OR_GOTO(status, channelSetupIDs(pChannel, pGpu, NV_FALSE, IS_MIG_IN_USE(pGpu)), free_client); + + channelSetupChannelBufferSizes(pChannel); + + // save original values + NvU32 instLocOverrides4 = pGpu->instLocOverrides4; + NvU32 instLocOverrides = pGpu->instLocOverrides; + + // Force PB, GPFIFO, notifier and userd to sysmem before allocating channel + pGpu->instLocOverrides4 = FLD_SET_DRF(_REG_STR_RM, _INST_LOC_4, _CHANNEL_PUSHBUFFER, _NCOH, pGpu->instLocOverrides4); + pGpu->instLocOverrides = FLD_SET_DRF(_REG_STR_RM, _INST_LOC, _USERD, _NCOH, pGpu->instLocOverrides); + + pChannel->engineType = NV2080_ENGINE_TYPE_SEC2; + + pMemoryManager->bScrubChannelSetupInProgress = NV_TRUE; + NV_ASSERT_OK_OR_GOTO(status, memmgrMemUtilsChannelInitialize_HAL(pGpu, pMemoryManager, pChannel), free_channel); + pMemoryManager->bScrubChannelSetupInProgress = NV_FALSE; + + pSec2Utils->hDevice = pChannel->deviceId; + pSec2Utils->hSubdevice = pChannel->subdeviceId; + + NV_PRINTF(LEVEL_INFO, "Channel alloc successful for Sec2Utils\n"); + pSec2Utils->pChannel = pChannel; + + NV_ASSERT_OK_OR_GOTO(status, memmgrMemUtilsSec2CtxInit_HAL(pGpu, pMemoryManager, pChannel), free_channel); + + // restore original values + pGpu->instLocOverrides4 = instLocOverrides4; + pGpu->instLocOverrides = instLocOverrides; + + pSec2Utils->lastSubmittedPayload = 0; + pSec2Utils->lastCompletedPayload = 0; + pSec2Utils->authTagPutIndex = 0; + pSec2Utils->authTagGetIndex = 0; + + NV_ASSERT_OK_OR_GOTO(status, _sec2InitBuffers(pSec2Utils), free_channel); + + NV_ASSERT_OK_OR_GOTO(status, ccslContextInitViaChannel(&pSec2Utils->pCcslCtx, pSec2Utils->hClient, pChannel->channelId), free_channel); + + return status; + +free_channel: + pRmApi->Free(pRmApi, pChannel->hClient, pChannel->channelId); + +free_client: + pRmApi->Free(pRmApi, pChannel->hClient, pChannel->hClient); + +cleanup: + portMemFree(pChannel); + return status; +} + +void +sec2utilsDestruct_IMPL +( + Sec2Utils *pSec2Utils +) +{ + OBJCHANNEL *pChannel = pSec2Utils->pChannel; + OBJGPU *pGpu = pSec2Utils->pGpu; + MemoryManager *pMemoryManager = NULL; + RM_API *pRmApi = NULL; + + // Sanity checks + if ((pGpu == NULL) || (pChannel == NULL)) + { + NV_PRINTF(LEVEL_WARNING, "Possible double-free of Sec2Utils!\n"); + return; + } + else if (pGpu != pChannel->pGpu) + { + NV_PRINTF(LEVEL_ERROR, "Bad state during sec2Utils teardown!\n"); + return; + } + + pMemoryManager = GPU_GET_MEMORY_MANAGER(pGpu); + pRmApi = rmapiGetInterface(RMAPI_GPU_LOCK_INTERNAL); + + ccslContextClear(pSec2Utils->pCcslCtx); + + if ((pChannel->bClientUserd) && (pChannel->pControlGPFifo != NULL)) + { + if (kbusIsBarAccessBlocked(GPU_GET_KERNEL_BUS(pGpu))) + { + // + // When PCIE is blocked, mappings should be created, used and torn + // down when they are used + // + NV_PRINTF(LEVEL_ERROR, "Leaked USERD mapping from ceUtils!\n"); + } + else + { + memmgrMemDescEndTransfer(pMemoryManager, pChannel->pUserdMemdesc, TRANSFER_FLAGS_USE_BAR1); + pChannel->pControlGPFifo = NULL; + } + } + + if (pChannel->pbCpuVA != NULL) + { + if (kbusIsBarAccessBlocked(GPU_GET_KERNEL_BUS(pGpu))) + { + NV_PRINTF(LEVEL_ERROR, "Leaked pushbuffer mapping!\n"); + } + else + { + memmgrMemDescEndTransfer(pMemoryManager, pChannel->pChannelBufferMemdesc, TRANSFER_FLAGS_USE_BAR1); + pChannel->pbCpuVA = NULL; + } + } + + if (pChannel->pTokenFromNotifier != NULL) + { + if (kbusIsBarAccessBlocked(GPU_GET_KERNEL_BUS(pGpu))) + { + NV_PRINTF(LEVEL_ERROR, "Leaked notifier mapping!\n"); + } + else + { + memmgrMemDescEndTransfer(pMemoryManager, pChannel->pErrNotifierMemdesc, TRANSFER_FLAGS_USE_BAR1); + pChannel->pTokenFromNotifier = NULL; + } + } + + pRmApi->Free(pRmApi, pSec2Utils->hClient, pSec2Utils->scrubMthdAuthTagBuf.hPhysMem); + pRmApi->Free(pRmApi, pSec2Utils->hClient, pSec2Utils->scrubMthdAuthTagBuf.hVirtMem); + + pRmApi->Free(pRmApi, pSec2Utils->hClient, pSec2Utils->semaMthdAuthTagBuf.hPhysMem); + pRmApi->Free(pRmApi, pSec2Utils->hClient, pSec2Utils->semaMthdAuthTagBuf.hVirtMem); + + pRmApi->Free(pRmApi, pChannel->hClient, pChannel->channelId); + pRmApi->Free(pRmApi, pChannel->hClient, pChannel->errNotifierIdPhys); + pRmApi->Free(pRmApi, pChannel->hClient, pChannel->pushBufferId); + pRmApi->Free(pRmApi, pChannel->hClient, pChannel->errNotifierIdVirt); + pRmApi->Free(pRmApi, pChannel->hClient, pChannel->hVASpaceId); + pRmApi->Free(pRmApi, pChannel->hClient, pChannel->deviceId); + + // Resource server makes sure no leak can occur + pRmApi->Free(pRmApi, pChannel->hClient, pChannel->hClient); + portMemFree(pChannel); +} + +void +sec2utilsServiceInterrupts_IMPL(Sec2Utils *pSec2Utils) +{ + OBJCHANNEL *pChannel = pSec2Utils->pChannel; + + // + // FIXME: Bug 2463959: objmemscrub is called with the rmDeviceGpuLock in the + // heapFree_IMPL->_stdmemPmaFree->pmaFreePages->scrubSubmitPages path. + // This can result in RM waiting for scrubbing to complete and yielding while holding the + // rmDeviceGpuLock. This can lead to deadlock. + // Instead, if the lock is held, service any interrupts on SEC2 to help the engine make progress. + // Bug 2527660 is filed to remove this change. + // + // pChannel is null when PMA scrub requests are handled in vGPU plugin. + // In this case vGpu plugin allocates scrubber channel in PF domain so + // above mention deadlock is not present here. + // + if ((pChannel != NULL) && (rmDeviceGpuLockIsOwner(pChannel->pGpu->gpuInstance))) + { + channelServiceScrubberInterrupts(pChannel); + } + else + { + osSchedule(); + } +} + +static NvU32 +_sec2utilsUpdateGetPtr +( + Sec2Utils *pSec2Utils +) +{ + return channelReadChannelMemdesc(pSec2Utils->pChannel, pSec2Utils->pChannel->authTagBufSemaOffset); +} + +static NV_STATUS +_sec2utilsGetNextAuthTagSlot +( + Sec2Utils *pSec2Utils +) +{ + NvU32 totalSlots = pSec2Utils->scrubMthdAuthTagBuf.size / SHA_256_HASH_SIZE_BYTES; + NvU32 nextPut = (pSec2Utils->authTagPutIndex + 1) % totalSlots; + + // check if slots have freed up + NV_STATUS status = NV_OK; + RMTIMEOUT timeout; + gpuSetTimeout(pSec2Utils->pGpu, GPU_TIMEOUT_DEFAULT, &timeout, GPU_TIMEOUT_FLAGS_BYPASS_THREAD_STATE); + while (nextPut == pSec2Utils->authTagGetIndex) + { + status = gpuCheckTimeout(pSec2Utils->pGpu, &timeout); + if (status != NV_OK) + { + NV_PRINTF(LEVEL_ERROR, "Timed out waiting for next auth tag buf slot to free up: nextPut = %d get = %d\n", + nextPut, _sec2utilsUpdateGetPtr(pSec2Utils)); + return status; + } + pSec2Utils->authTagGetIndex = _sec2utilsUpdateGetPtr(pSec2Utils); + osSpinLoop(); + } + + pSec2Utils->authTagPutIndex = nextPut; + return NV_OK; +} + +static NV_STATUS +_sec2utilsSubmitPushBuffer +( + Sec2Utils *pSec2Utils, + OBJCHANNEL *pChannel, + NvBool bInsertFinishPayload, + NvU32 nextIndex, + CHANNEL_PB_INFO *pChannelPbInfo +) +{ + NV_STATUS status = NV_OK; + NvU32 methodsLength = 0; + NvU32 putIndex = 0; + + NV_ASSERT_OR_RETURN(pChannelPbInfo != NULL, NV_ERR_INVALID_ARGUMENT); + NV_ASSERT_OR_RETURN(pChannel != NULL, NV_ERR_INVALID_ARGUMENT); + + MemoryManager *pMemoryManager = GPU_GET_MEMORY_MANAGER(pChannel->pGpu); + NvBool bReleaseMapping = NV_FALSE; + + // + // Use BAR1 if CPU access is allowed, otherwise allocate and init shadow + // buffer for DMA access + // + NvU32 transferFlags = (TRANSFER_FLAGS_USE_BAR1 | + TRANSFER_FLAGS_SHADOW_ALLOC | + TRANSFER_FLAGS_SHADOW_INIT_MEM); + NV_PRINTF(LEVEL_INFO, "Actual size of copying to be pushed: %x\n", pChannelPbInfo->size); + + status = channelWaitForFreeEntry(pChannel, &putIndex); + if (status != NV_OK) + { + NV_PRINTF(LEVEL_ERROR, "Cannot get putIndex.\n"); + return status; + } + + if (pChannel->pbCpuVA == NULL) + { + pChannel->pbCpuVA = memmgrMemDescBeginTransfer(pMemoryManager, pChannel->pChannelBufferMemdesc, + transferFlags); + bReleaseMapping = NV_TRUE; + } + NV_ASSERT_OR_RETURN(pChannel->pbCpuVA != NULL, NV_ERR_GENERIC); + + NV_ASSERT_OK_OR_RETURN(_sec2utilsGetNextAuthTagSlot(pSec2Utils)); + NV_ASSERT_OK_OR_RETURN(channelFillSec2Pb(pChannel, putIndex, bInsertFinishPayload, pChannelPbInfo, pSec2Utils->pCcslCtx, + pSec2Utils->scrubMthdAuthTagBuf.pMemDesc, pSec2Utils->semaMthdAuthTagBuf.pMemDesc, + pSec2Utils->scrubMthdAuthTagBuf.gpuVA, pSec2Utils->authTagPutIndex, + pSec2Utils->semaMthdAuthTagBuf.gpuVA, nextIndex, &methodsLength)); + + if (bReleaseMapping) + { + memmgrMemDescEndTransfer(pMemoryManager, pChannel->pChannelBufferMemdesc, transferFlags); + pChannel->pbCpuVA = NULL; + } + + if (methodsLength == 0) + { + NV_PRINTF(LEVEL_ERROR, "Cannot push methods to channel.\n"); + return NV_ERR_NO_FREE_FIFOS; + } + + // + // Pushbuffer can be written in a batch, but GPFIFO and doorbell require + // careful ordering so we do each write one-by-one + // + status = channelFillGpFifo(pChannel, putIndex, methodsLength); + if (status != NV_OK) + { + NV_PRINTF(LEVEL_ERROR, "Channel operation failures during memcopy\n"); + return status; + } + + pChannel->lastSubmittedEntry = putIndex; + + return status; +} + + +NV_STATUS +sec2utilsMemset_IMPL +( + Sec2Utils *pSec2Utils, + SEC2UTILS_MEMSET_PARAMS *pParams +) +{ + OBJCHANNEL *pChannel = pSec2Utils->pChannel; + NV_STATUS status = NV_OK; + RMTIMEOUT timeout; + + NvU32 pteArraySize; + NvU64 offset, memsetLength, size, pageGranularity; + NvBool bContiguous; + + MEMORY_DESCRIPTOR *pMemDesc = pParams->pMemDesc; + CHANNEL_PB_INFO channelPbInfo = {0}; + + if (pMemDesc == NULL) + { + NV_PRINTF(LEVEL_ERROR, "Invalid memdesc for Sec2Utils memset.\n"); + return NV_ERR_INVALID_ARGUMENT; + } + + if ((memdescGetAddressSpace(pMemDesc) != ADDR_FBMEM) || + (pMemDesc->pGpu != pSec2Utils->pChannel->pGpu)) + { + NV_PRINTF(LEVEL_ERROR, "Invalid memory descriptor passed.\n"); + return NV_ERR_INVALID_ARGUMENT; + } + + size = memdescGetSize(pMemDesc); + pteArraySize = memdescGetPteArraySize(pMemDesc, AT_GPU); + bContiguous = (pMemDesc->_flags & MEMDESC_FLAGS_PHYSICALLY_CONTIGUOUS) || (pteArraySize == 1); + + if (pParams->offset >= size) + { + NV_PRINTF(LEVEL_ERROR, "Invalid offset passed for the memdesc.\n"); + return NV_ERR_INVALID_ARGUMENT; + } + + if ((pParams->length == 0) || (pParams->length > (size - pParams->offset))) + { + NV_PRINTF(LEVEL_ERROR, "Invalid memset length passed.\n"); + return NV_ERR_INVALID_ARGUMENT; + } + + // Make sure free auth tag buffers are available + NvU32 totalSlots = pSec2Utils->semaMthdAuthTagBuf.size / SHA_256_HASH_SIZE_BYTES; + NvU32 nextIndex = (pSec2Utils->lastSubmittedPayload + 1) % totalSlots; + NvU32 lastCompleted = sec2utilsUpdateProgress(pSec2Utils); + NvU32 currentIndex = lastCompleted % totalSlots; + + gpuSetTimeout(pSec2Utils->pGpu, GPU_TIMEOUT_DEFAULT, &timeout, GPU_TIMEOUT_FLAGS_BYPASS_THREAD_STATE); + while (nextIndex == currentIndex) + { + status = gpuCheckTimeout(pSec2Utils->pGpu, &timeout); + if (status != NV_OK) + { + NV_PRINTF(LEVEL_ERROR, "Failed to finish previous scrub op before re-using method stream auth tag buf: lastCompleted = %d lastSubmitted = %lld\n", + lastCompleted, pSec2Utils->lastSubmittedPayload); + return status; + } + lastCompleted = sec2utilsUpdateProgress(pSec2Utils); + currentIndex = lastCompleted % totalSlots; + osSpinLoop(); + } + + channelPbInfo.payload = pSec2Utils->lastSubmittedPayload + 1; + pSec2Utils->lastSubmittedPayload = channelPbInfo.payload; + + channelPbInfo.dstAddressSpace = memdescGetAddressSpace(pMemDesc); + channelPbInfo.dstCpuCacheAttrib = pMemDesc->_cpuCacheAttrib; + + pageGranularity = pMemDesc->pageArrayGranularity; + memsetLength = pParams->length; + offset = pParams->offset; + + do + { + NvU64 maxContigSize = bContiguous ? memsetLength : (pageGranularity - offset % pageGranularity); + NvU32 memsetSizeContig = (NvU32)NV_MIN(NV_MIN(memsetLength, maxContigSize), NVCBA2_DECRYPT_SCRUB_SIZE_MAX_BYTES); + + channelPbInfo.dstAddr = memdescGetPhysAddr(pMemDesc, AT_GPU, offset); + + NV_PRINTF(LEVEL_INFO, "Sec2Utils Memset dstAddr: %llx, size: %x\n", + channelPbInfo.dstAddr, memsetSizeContig); + + channelPbInfo.size = memsetSizeContig; + + status = _sec2utilsSubmitPushBuffer(pSec2Utils, pChannel, memsetSizeContig == memsetLength, nextIndex, &channelPbInfo); + if (status != NV_OK) + { + NV_PRINTF(LEVEL_ERROR, "Cannot submit push buffer for memset.\n"); + return status; + } + + memsetLength -= memsetSizeContig; + offset += memsetSizeContig; + } while (memsetLength != 0); + + NV_PRINTF(LEVEL_INFO, "Async memset payload returned: 0x%x\n", channelPbInfo.payload); + pParams->submittedWorkId = channelPbInfo.payload; + + return status; +} + +// This function updates pSec2Utils->lastCompletedPayload and handles wrap-around +NvU64 +sec2utilsUpdateProgress_IMPL +( + Sec2Utils *pSec2Utils +) +{ + NV_ASSERT((pSec2Utils != NULL) && (pSec2Utils->pChannel != NULL)); + + NvU32 hwCurrentCompletedPayload = 0; + NvU64 swLastCompletedPayload = pSec2Utils->lastCompletedPayload; + + // + // Sec2Utils uses 64 bit index to track the work submitted. But HW supports + // only 32 bit semaphore. The current completed Id is calculated here, based + // on the lastSubmittedPayload and current HW semaphore value. + // + hwCurrentCompletedPayload = READ_CHANNEL_PAYLOAD_SEMA(pSec2Utils->pChannel); + + // No work has been completed since we checked last time + if (hwCurrentCompletedPayload == (NvU32)swLastCompletedPayload) + { + return swLastCompletedPayload; + } + + // Check for wrap around case. Increment the upper 32 bits + if (hwCurrentCompletedPayload < (NvU32)swLastCompletedPayload) + { + swLastCompletedPayload += 0x100000000ULL; + } + + // Update lower 32 bits regardless if wrap-around happened + swLastCompletedPayload &= 0xFFFFFFFF00000000ULL; + swLastCompletedPayload |= (NvU64)hwCurrentCompletedPayload; + + pSec2Utils->lastCompletedPayload = swLastCompletedPayload; + return swLastCompletedPayload; +} diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/kernel/gpu/mem_mgr/sem_surf.c nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/kernel/gpu/mem_mgr/sem_surf.c --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/kernel/gpu/mem_mgr/sem_surf.c 1970-01-01 00:00:00.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/kernel/gpu/mem_mgr/sem_surf.c 2024-03-05 22:13:38.000000000 +0000 @@ -0,0 +1,1639 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#include "gpu/mem_mgr/sem_surf.h" +#include "os/os.h" // NV_MEMORY_NONCONTIGUOUS, osEventNotification +#include "gpu/device/device.h" +#include "gpu/mem_mgr/mem_mgr.h" +#include "gpu/mem_mgr/mem_desc.h" +#include "gpu/gpu.h" +#include "rmapi/client.h" +#include "rmapi/rs_utils.h" + +#include "class/cl0080.h" +#include "class/cl2080.h" +#include "class/cl0005.h" +#include "class/cl003e.h" // NV01_MEMORY_SYSTEM +#include "class/cl0040.h" // NV01_MEMORY_LOCAL_USER + +static void +_semsurfFreeRmClient +( + SEM_SHARED_DATA *pShared +) +{ + RM_API *pRmApi = rmapiGetInterface(RMAPI_GPU_LOCK_INTERNAL); + + if (pShared->hClient != NV01_NULL_OBJECT) + { + pRmApi->Free(pRmApi, + pShared->hClient, + pShared->hClient); + } + + pShared->hClient = NV01_NULL_OBJECT; + pShared->hDevice = NV01_NULL_OBJECT; + pShared->hSubDevice = NV01_NULL_OBJECT; +} + +static void +_semsurfUnregisterCallback +( + SEM_SHARED_DATA *pShared +) +{ + RM_API *pRmApi = rmapiGetInterface(RMAPI_GPU_LOCK_INTERNAL); + + if ((pShared->hClient != NV01_NULL_OBJECT) && + (pShared->hEvent != NV01_NULL_OBJECT)) + { + pRmApi->Free(pRmApi, + pShared->hClient, + pShared->hEvent); + } + + pShared->hEvent = NV01_NULL_OBJECT; +} + +static NvU64 +_semsurfGetValue +( + SEM_SHARED_DATA *pShared, + NvU64 index +) +{ + volatile NvU8 *pSem = pShared->pSem; + volatile NvU8 *pMaxSubmitted = pShared->pMaxSubmitted; + volatile NvU8 *pSemBase = pSem + index * pShared->layout.size; + + portAtomicMemoryFenceFull(); + + if (pShared->bIs64Bit) + { + volatile NvU64 *pSemVal = (volatile NvU64 *)pSemBase; + + NV_PRINTF(LEVEL_INFO, " Read semaphore surface value as 64-bit native\n"); + + return *pSemVal; + } + else + { + const volatile NvU32 *pSemVal = (volatile NvU32 *)pSemBase; + volatile NvU8 *pMaxSubmittedBase = pMaxSubmitted + index * pShared->layout.size; + volatile NvU64 *pMaxSubmitted = (volatile NvU64 *)(pMaxSubmittedBase + pShared->layout.maxSubmittedSemaphoreValueOffset); + + // The ordering below is critical. See NvTimeSemFermiGetPayload() for full comment. + // TODO Share this code? + NvU64 semVal = *pSemVal; + + portAtomicMemoryFenceLoad(); + + NvU64 maxSubmitted = portAtomicExAddU64(pMaxSubmitted, 0); + + NV_PRINTF(LEVEL_INFO, " Read maxSubmitted %" NvU64_fmtu " and 32-bit semVal %" + NvU64_fmtu " from semaphore index %" NvU64_fmtu "\n", + maxSubmitted, semVal, index); + + // The value is monotonically increasing, and the max outstanding + // wait and the value can differ by no more than 2^31-1. Hence... + if ((maxSubmitted & 0xFFFFFFFFull) < semVal) + maxSubmitted -= 0x100000000ull; + + return semVal | (maxSubmitted & 0xffffffff00000000ull); + } +} + +static void +_semsurfSetValue +( + SEM_SHARED_DATA *pShared, + NvU64 index, + NvU64 newValue +) +{ + volatile NvU8 *pSem = pShared->pSem; + volatile NvU8 *pMaxSubmitted = pShared->pMaxSubmitted; + volatile NvU8 *pSemBase = pSem + index * pShared->layout.size; + + if (pShared->bIs64Bit) + { + volatile NvU64 *pSemVal = (volatile NvU64 *)pSemBase; + + portAtomicMemoryFenceFull(); + + *pSemVal = newValue; + + NV_PRINTF(LEVEL_INFO, " Updated semaphore surface value as 64-bit " + "native to %" NvU64_fmtu "\n", newValue); + } + else + { + volatile NvU32 *pSemVal = (volatile NvU32 *)pSemBase; + volatile NvU8 *pMaxSubmittedBase = pMaxSubmitted + index * pShared->layout.size; + volatile NvU64 *pMaxSubmitted = (volatile NvU64 *)(pMaxSubmittedBase + pShared->layout.maxSubmittedSemaphoreValueOffset); + NvU64 oldMax, origMax; + + portAtomicMemoryFenceFull(); + origMax = oldMax = portAtomicExAddU64(pMaxSubmitted, 0); + + // First save the actual value to the max submitted slot using + // an atomic max operation + while (oldMax < newValue) + { + NvBool exchanged; + + // XXX Does CompareAndSwap imply any barriers? The comments in + // nvport/atomic.h imply it does, but that this shouldn't be relied + // upon, so include another barrier here. + portAtomicMemoryFenceFull(); + exchanged = portAtomicExCompareAndSwapU64(pMaxSubmitted, + newValue, + oldMax); + + if (exchanged) + break; // The value was set. Exit. + + // The "current" value changed. Update it. + oldMax = portAtomicExAddU64(pMaxSubmitted, 0); + } + + portAtomicMemoryFenceStore(); + + // Now write the low bits to the GPU-accessible semaphore value. + *pSemVal = NvU64_LO32(newValue); + + NV_PRINTF(LEVEL_INFO, " Updated maxSubmitted from %" NvU64_fmtu " to %" + NvU64_fmtu " and 32-bit semVal %u" + " at semaphore index %" NvU64_fmtu "\n", + origMax, newValue, NvU64_LO32(newValue), index); + (void) origMax; + } +} + +static NvBool +_semsurfNotifyCompleted +( + SEM_SHARED_DATA *pShared, + SEM_PENDING_NOTIFICATIONS *notifications +) +{ + OBJGPU *pGpu = pShared->pSemaphoreMem->pGpu; + SEM_PENDING_NOTIFICATIONSIter pendIter; + SEM_VALUE_LISTENERS_NODE *pVNode; + NV_STATUS rmStatus; + NvBool valuesChanged = NV_FALSE; + EVENTNOTIFICATION **ppListeners; + + for (pendIter = listIterAll(notifications); + listIterNext(&pendIter); + pendIter = listIterAll(notifications)) + { + pVNode = pendIter.pValue; + + rmStatus = osEventNotification(pGpu, + pVNode->pListeners, + NV_SEMAPHORE_SURFACE_WAIT_VALUE, + NULL, + 0); + + NV_PRINTF(LEVEL_INFO, + "SemMem(0x%08x, 0x%08x): Delivered OS events for value %" + NvU64_fmtu " at idx %" NvU64_fmtu ". Status: %s (0x%08x)\n", + pShared->hClient, pShared->hSemaphoreMem, + pVNode->value, pVNode->index, + nvstatusToString(rmStatus), + rmStatus); + (void) rmStatus; + + /* + * Auto-remove the event listeners for this value now that they + * have been notified. It makes little sense to keep notifying + * them after this. + */ + ppListeners = &pendIter.pValue->pListeners; + while (*ppListeners) + { + unregisterEventNotificationWithData(ppListeners, + (*ppListeners)->hEventClient, + NV01_NULL_OBJECT, /* hNotifier/subdevice */ + (*ppListeners)->hEvent, + NV_TRUE, /* match data/notificationHandle */ + (*ppListeners)->Data); + } + + if (pVNode->newValue != 0) { + /* + * It is safe to do this operation outside of the spinlock because + * it is the RM client's responsibility to ensure the semaphore + * surface value is monotonically incrementing by explicitly + * ordering all writes to it, including these. This does imply the + * need to manually fence memory operations touching the semaphore + * value though. + */ + _semsurfSetValue(pShared, pVNode->index, pVNode->newValue); + + NV_PRINTF(LEVEL_INFO, + "SemMem(0x%08x, 0x%08x): Value updated by waiter " + " to %" NvU64_fmtu " at idx %" NvU64_fmtu "\n", + pShared->hClient, pShared->hSemaphoreMem, pVNode->newValue, pVNode->index); + + valuesChanged = NV_TRUE; + } + + listRemove(notifications, pendIter.pValue); + portMemFree(pendIter.pValue); + } + + return valuesChanged; +} + +static void +_semsurfSetMonitoredValue +( + SEM_SHARED_DATA *pShared, + NvU64 index, + NvU64 value +) +{ + if (!pShared->bHasMonitoredFence) + return; + + /* + * This function must be called with the spinlock held to avoid a race + * condition where two threads disagree on the current minimum wait value + * for a given slot. + */ + volatile NvU64 *pMonitoredFence = + (volatile NvU64 *)(pShared->pSem + + pShared->layout.size * index + + pShared->layout.monitoredFenceThresholdOffset); + + NV_PRINTF(LEVEL_NOTICE, + "SemMem(0x%08x, 0x%08x): " + "Setting monitored fence value at index %" NvU64_fmtu + " to %" NvU64_fmtu "\n", + pShared->hClient, pShared->hSemaphoreMem, + index, value); + + // Don't care if this races with loads, but ensure it happens in order + // with prior stores. + portAtomicMemoryFenceStore(); + *pMonitoredFence = value; +} + +static void +_semsurfEventCallback +( + void *pArg, + void *pData, + NvHandle hEvent, + NvU32 data, + NvU32 status +) +{ + SEM_SHARED_DATA *pShared = pArg; + SEM_INDEX_LISTENERSIter ilIter; + SEM_VALUE_LISTENERSIter vlIter; + SEM_PENDING_NOTIFICATIONS notifications; + NvU64 index; + NvU64 semValue; + NvU64 minWaitValue; + NvBool removedIndex = NV_FALSE; + NvBool valuesChanged = NV_TRUE; + + NV_PRINTF(LEVEL_INFO, "SemMem(0x%08x, 0x%08x): Got a callback\n", pShared->hClient, pShared->hSemaphoreMem); + NV_PRINTF(LEVEL_INFO, " hEvent: 0x%08x surf event: 0x%08x, data 0x%08x, status 0x%08x\n", + hEvent, pShared->hEvent, data, status); + + while (valuesChanged) + { + listInitIntrusive(¬ifications); + + NV_PRINTF(LEVEL_INFO, "SemMem(0x%08x, 0x%08x): Entering spinlock\n", + pShared->hClient, + pShared->hSemaphoreMem); + portSyncSpinlockAcquire(pShared->pSpinlock); + + for (ilIter = mapIterAll(&pShared->listenerMap); + mapIterNext(&ilIter); + removedIndex ? ilIter = mapIterAll(&pShared->listenerMap) : + ilIter) + { + removedIndex = NV_FALSE; + minWaitValue = NV_U64_MAX; + + /* + * TODO Only notify if vlIter.pValue->value <= the semaphore current + * value at mapKey(&pShared->listenerMap, ilIter->pValue) + */ + index = mapKey(&pShared->listenerMap, ilIter.pValue); + semValue = _semsurfGetValue(pShared, index); + + for (vlIter = listIterAll(&ilIter.pValue->listeners); + listIterNext(&vlIter); + vlIter = listIterAll(&ilIter.pValue->listeners)) + { + NV_PRINTF(LEVEL_SILENT, + " Checking index %" NvU64_fmtu " value waiter %" + NvU64_fmtu " against semaphore value %" NvU64_fmtu "\n", + index, vlIter.pValue->value, semValue); + + if (semValue >= vlIter.pValue->value) + { + listInsertExisting(¬ifications, NULL, vlIter.pValue); + listRemove(&ilIter.pValue->listeners, vlIter.pValue); + } + else + { + /* No other values at this index should be signaled yet. */ + minWaitValue = vlIter.pValue->value; + break; + } + } + + if (listCount(&ilIter.pValue->listeners) == 0) + { + NV_ASSERT(minWaitValue == NV_U64_MAX); + mapRemove(&pShared->listenerMap, ilIter.pValue); + portMemFree(ilIter.pValue); + removedIndex = NV_TRUE; + } + else + { + removedIndex = NV_FALSE; + } + + _semsurfSetMonitoredValue(pShared, index, minWaitValue); + } + + portSyncSpinlockRelease(pShared->pSpinlock); + NV_PRINTF(LEVEL_INFO, "SemMem(0x%08x, 0x%08x): Exited spinlock\n", + pShared->hClient, + pShared->hSemaphoreMem); + + // Send notifications outside of spinlock. They have already been removed + // from the object-wide lists, so their existance is private to this + // instance of this function now. Hence, no locking is required for this + // step. + valuesChanged = _semsurfNotifyCompleted(pShared, ¬ifications); + } +} + +static NV_STATUS +_semsurfAllocRmClient +( + SemaphoreSurface *pSemSurf +) +{ + SEM_SHARED_DATA *pShared = pSemSurf->pShared; + NV0080_ALLOC_PARAMETERS nv0080AllocParams; + NV2080_ALLOC_PARAMETERS nv2080AllocParams; + RM_API *pRmApi = rmapiGetInterface(RMAPI_GPU_LOCK_INTERNAL); + + // Allocate an internal client, device, and subDevice for the semaphore + // surface. These will be used to allocate the internally-managed memory + // object wrapped by the semaphore surface, and to to register callbacks + // on the GPU for semaphore awaken/notification interrupts. + NV_ASSERT_OK_OR_RETURN( + pRmApi->AllocWithHandle(pRmApi, + NV01_NULL_OBJECT, + NV01_NULL_OBJECT, + NV01_NULL_OBJECT, + NV01_ROOT, + &pShared->hClient, + sizeof(pShared->hClient))); + + portMemSet(&nv0080AllocParams, 0, sizeof(nv0080AllocParams)); + nv0080AllocParams.deviceId = + gpuGetDeviceInstance(GPU_RES_GET_GPU(pSemSurf)); + + NV_ASSERT_OK_OR_RETURN( + pRmApi->Alloc(pRmApi, + pShared->hClient, + pShared->hClient, + &pShared->hDevice, + NV01_DEVICE_0, + &nv0080AllocParams, + sizeof(nv0080AllocParams))); + + // Allocate a subDevice + portMemSet(&nv2080AllocParams, 0, sizeof(nv2080AllocParams)); + nv2080AllocParams.subDeviceId = + gpumgrGetSubDeviceInstanceFromGpu(GPU_RES_GET_GPU(pSemSurf)); + + NV_ASSERT_OK_OR_RETURN( + pRmApi->Alloc(pRmApi, + pShared->hClient, + pShared->hDevice, + &pShared->hSubDevice, + NV20_SUBDEVICE_0, + &nv2080AllocParams, + sizeof(nv2080AllocParams))); + + return NV_OK; +} + +static void +_semsurfFreeMemory +( + SEM_SHARED_DATA *pShared +) +{ + RM_API *pRmApi = rmapiGetInterface(RMAPI_GPU_LOCK_INTERNAL); + + if (pShared->hClient != NV01_NULL_OBJECT) + { + if ((pShared->hMaxSubmittedMem != NV01_NULL_OBJECT) && + (pShared->hMaxSubmittedMem != pShared->hSemaphoreMem)) + pRmApi->Free(pRmApi, + pShared->hClient, + pShared->hMaxSubmittedMem); + + if (pShared->hSemaphoreMem != NV01_NULL_OBJECT) + pRmApi->Free(pRmApi, + pShared->hClient, + pShared->hSemaphoreMem); + } + + pShared->hSemaphoreMem = NV01_NULL_OBJECT; + pShared->hMaxSubmittedMem = NV01_NULL_OBJECT; +} + +static NV_STATUS +_semsurfDupMemory +( + SemaphoreSurface *pSemSurf, + NV_SEMAPHORE_SURFACE_ALLOC_PARAMETERS *pAllocParams +) +{ + SEM_SHARED_DATA *pShared = pSemSurf->pShared; + RM_API *pRmApi = rmapiGetInterface(RMAPI_GPU_LOCK_INTERNAL); + + NV_CHECK_OK_OR_RETURN(LEVEL_ERROR, + pRmApi->DupObject(pRmApi, + pShared->hClient, + pShared->hDevice, + &pShared->hSemaphoreMem, + RES_GET_CLIENT_HANDLE(pSemSurf), + pAllocParams->hSemaphoreMem, + NV04_DUP_HANDLE_FLAGS_NONE)); + + if (pAllocParams->hMaxSubmittedMem != NV01_NULL_OBJECT) + { + NV_CHECK_OR_RETURN(LEVEL_ERROR, + !pSemSurf->pShared->bIs64Bit, + NV_ERR_INVALID_PARAMETER); + + if (pAllocParams->hMaxSubmittedMem != pAllocParams->hSemaphoreMem) + { + NV_CHECK_OK_OR_RETURN(LEVEL_ERROR, + pRmApi->DupObject(pRmApi, + pShared->hClient, + pShared->hDevice, + &pShared->hMaxSubmittedMem, + RES_GET_CLIENT_HANDLE(pSemSurf), + pAllocParams->hMaxSubmittedMem, + NV04_DUP_HANDLE_FLAGS_NONE)); + } + else + { + pSemSurf->pShared->hMaxSubmittedMem = + pSemSurf->pShared->hSemaphoreMem; + } + } + else + { + pSemSurf->pShared->hMaxSubmittedMem = NV01_NULL_OBJECT; + } + + return NV_OK; +} + +static NV_STATUS +_semsurfRegisterCallback +( + SemaphoreSurface *pSemSurf +) +{ + SEM_SHARED_DATA *pShared = pSemSurf->pShared; + NV0005_ALLOC_PARAMETERS nv0005AllocParams; + RM_API *pRmApi = rmapiGetInterface(RMAPI_GPU_LOCK_INTERNAL); + + pShared->callback.func = _semsurfEventCallback; + pShared->callback.arg = pShared; + + portMemSet(&nv0005AllocParams, 0, sizeof(nv0005AllocParams)); + nv0005AllocParams.hParentClient = pShared->hClient; + nv0005AllocParams.hClass = NV01_EVENT_KERNEL_CALLBACK_EX; + nv0005AllocParams.notifyIndex = NV2080_NOTIFIERS_FIFO_EVENT_MTHD | + NV01_EVENT_NONSTALL_INTR | + NV01_EVENT_WITHOUT_EVENT_DATA | + NV01_EVENT_SUBDEVICE_SPECIFIC | + DRF_NUM(0005, _NOTIFY_INDEX, _SUBDEVICE, + gpumgrGetSubDeviceInstanceFromGpu(GPU_RES_GET_GPU(pSemSurf))); + nv0005AllocParams.data = NV_PTR_TO_NvP64(&pShared->callback); + + return pRmApi->Alloc(pRmApi, + pShared->hClient, + pShared->hSubDevice, + &pShared->hEvent, + NV01_EVENT_KERNEL_CALLBACK_EX, + &nv0005AllocParams, + sizeof(nv0005AllocParams)); +} + +static NV_STATUS +semsurfCopyConstruct +( + SemaphoreSurface *pSemSurf, + CALL_CONTEXT *pCallContext, + RS_RES_ALLOC_PARAMS_INTERNAL *pParams +) +{ + RsResourceRef *pSrcRef = pParams->pSrcRef; + SemaphoreSurface *pSrcSemSurf = dynamicCast(pSrcRef->pResource, + SemaphoreSurface); + + pSemSurf->pShared = pSrcSemSurf->pShared; + NV_ASSERT(pSemSurf->pShared->refCount > 0); + pSemSurf->pShared->refCount++; + + NV_PRINTF(LEVEL_NOTICE, + "SemSurf(0x%08x, 0x%08x): Copied with SemMem(0x%08x, 0x%08x)\n", + RES_GET_CLIENT_HANDLE(pSemSurf), RES_GET_HANDLE(pSemSurf), + pSemSurf->pShared->hClient, pSemSurf->pShared->hSemaphoreMem); + + return NV_OK; +} + +static void +_semsurfDestroyShared +( + SEM_SHARED_DATA *pShared +) +{ + RM_API *pRmApi = rmapiGetInterface(RMAPI_GPU_LOCK_INTERNAL); + + if (pShared == NULL) + return; + + _semsurfUnregisterCallback(pShared); + + if (pShared->pMaxSubmittedMem) + { + if (pShared->maxSubmittedKernAddr) + { + pRmApi->UnmapFromCpu(pRmApi, + pShared->hClient, + pShared->hDevice, + pShared->hMaxSubmittedMem, + pShared->maxSubmittedKernAddr, + 0, 0); + + pShared->maxSubmittedKernAddr = 0; + pShared->pMaxSubmitted = NULL; + } + } + + if (pShared->pSemaphoreMem) + { + if (pShared->semKernAddr) + { + pRmApi->UnmapFromCpu(pRmApi, + pShared->hClient, + pShared->hDevice, + pShared->hSemaphoreMem, + pShared->semKernAddr, + 0, 0); + } + + pShared->semKernAddr = 0; + pShared->pSem = NULL; + } + + pShared->pMaxSubmittedMem = NULL; + pShared->pSemaphoreMem = NULL; + + _semsurfFreeMemory(pShared); + _semsurfFreeRmClient(pShared); + + if (pShared->pSpinlock) + portSyncSpinlockDestroy(pShared->pSpinlock); + + portMemFree(pShared); +} + +static NvBool +_semsurfValidateIndex +( + SEM_SHARED_DATA *pShared, + NvU64 index +) +{ + const NvU64 slotSize = pShared->layout.size; + + if (((index * slotSize) + slotSize) <= pShared->pSemaphoreMem->pMemDesc->Size) + return NV_TRUE; + else + return NV_FALSE; +} + +NV_STATUS +semsurfConstruct_IMPL +( + SemaphoreSurface *pSemSurf, + CALL_CONTEXT *pCallContext, + RS_RES_ALLOC_PARAMS_INTERNAL *pParams +) +{ + RM_API *pRmApi = rmapiGetInterface(RMAPI_GPU_LOCK_INTERNAL); + SEM_SHARED_DATA *pShared; + RmClient *pClient; + RsClient *pRsClient; + NV_SEMAPHORE_SURFACE_ALLOC_PARAMETERS *pAllocParams = pParams->pAllocParams; + NvU32 maxSubmittedCoherency; + NV_STATUS status = NV_OK; + NvU64 i; + + if (RS_IS_COPY_CTOR(pParams)) + { + // + // Copy constructor (NvRmDupObject) + // + return semsurfCopyConstruct(pSemSurf, pCallContext, pParams); + } + + NV_CHECK_OR_RETURN(LEVEL_ERROR, + pAllocParams->flags == 0ULL, + NV_ERR_INVALID_ARGUMENT); + + pShared = pSemSurf->pShared = portMemAllocNonPaged(sizeof(*pSemSurf->pShared)); + NV_ASSERT_TRUE_OR_GOTO(status, pShared != NULL, NV_ERR_NO_MEMORY, ctorFailed); + + portMemSet(pShared, 0, sizeof(*pShared)); + pShared->refCount = 1; + mapInitIntrusive(&pShared->listenerMap); + + pShared->pSpinlock = portSyncSpinlockCreate(portMemAllocatorGetGlobalNonPaged()); + NV_ASSERT_TRUE_OR_GOTO(status, pShared->pSpinlock != NULL, NV_ERR_NO_MEMORY, ctorFailed); + + NV_ASSERT_OK_OR_GOTO(status, _semsurfAllocRmClient(pSemSurf), ctorFailed); + + NV_ASSERT_OK_OR_GOTO(status, + pRmApi->Control(pRmApi, + pShared->hClient, + pShared->hSubDevice, + NV2080_CTRL_CMD_FB_GET_SEMAPHORE_SURFACE_LAYOUT, + &pShared->layout, + sizeof pShared->layout), + ctorFailed); + + pShared->bIs64Bit = !!(pShared->layout.caps & NV2080_CTRL_FB_GET_SEMAPHORE_SURFACE_LAYOUT_CAPS_64BIT_SEMAPHORES_SUPPORTED); + pShared->bHasMonitoredFence = !!(pShared->layout.caps & NV2080_CTRL_FB_GET_SEMAPHORE_SURFACE_LAYOUT_CAPS_MONITORED_FENCE_SUPPORTED); + + pClient = serverutilGetClientUnderLock(pShared->hClient); + NV_ASSERT_TRUE_OR_GOTO(status, pClient != NULL, NV_ERR_INVALID_STATE, ctorFailed); + + pRsClient = staticCast(pClient, RsClient); + + NV_CHECK_OK_OR_GOTO(status, LEVEL_ERROR, + _semsurfDupMemory(pSemSurf, pAllocParams), + ctorFailed); + + NV_ASSERT_OK_OR_GOTO(status, memGetByHandle(pRsClient, pShared->hSemaphoreMem, &pShared->pSemaphoreMem), ctorFailed); + + /* + * XXX Limit semaphore surfaces to sysmem for the time being. Vidmem + * access latency may be too high to allow handling semaphore surfaces + * directly in the lockless top-half ISR. + */ + NV_CHECK_OR_ELSE(LEVEL_ERROR, + DRF_VAL(OS32, _ATTR, _LOCATION, + pShared->pSemaphoreMem->Attr) == + NVOS32_ATTR_LOCATION_PCI, + status = NV_ERR_INVALID_PARAMETER; + goto ctorFailed); + + NV_ASSERT_OK_OR_GOTO(status, + pRmApi->MapToCpu(pRmApi, + pShared->hClient, + pShared->hDevice, + pShared->hSemaphoreMem, + 0, + pShared->pSemaphoreMem->pMemDesc->Size, + &pShared->semKernAddr, + 0), + ctorFailed); + + pShared->pSem = KERNEL_POINTER_FROM_NvP64(NvU8 *, pShared->semKernAddr); + + if (!pShared->bIs64Bit) + { + if (pShared->hSemaphoreMem != pShared->hMaxSubmittedMem) + { + + NV_ASSERT_OK_OR_GOTO(status, + memGetByHandle(pRsClient, pShared->hMaxSubmittedMem, &pShared->pMaxSubmittedMem), + ctorFailed); + + NV_CHECK_OR_ELSE(LEVEL_ERROR, + pShared->pMaxSubmittedMem->pMemDesc->Size >= + pShared->pSemaphoreMem->pMemDesc->Size, + status = NV_ERR_BUFFER_TOO_SMALL; + goto ctorFailed); + + NV_ASSERT_OK_OR_GOTO(status, + pRmApi->MapToCpu(pRmApi, + pShared->hClient, + pShared->hDevice, + pShared->hMaxSubmittedMem, + 0, + pShared->pMaxSubmittedMem->pMemDesc->Size, + &pShared->maxSubmittedKernAddr, + 0), + ctorFailed); + + pShared->pMaxSubmitted = + KERNEL_POINTER_FROM_NvP64(NvU8 *, pShared->maxSubmittedKernAddr); + } + else + { + pShared->pMaxSubmitted = pShared->pSem; + pShared->pMaxSubmittedMem = pShared->pSemaphoreMem; + } + + /* + * XXX Limit semaphore surfaces to sysmem for the time being. Vidmem + * access latency may be too high to allow handling semaphore surfaces + * directly in the lockless top-half ISR. + */ + NV_CHECK_OR_ELSE(LEVEL_ERROR, + DRF_VAL(OS32, _ATTR, _LOCATION, + pShared->pMaxSubmittedMem->Attr) == + NVOS32_ATTR_LOCATION_PCI, + status = NV_ERR_INVALID_PARAMETER; + goto ctorFailed); + + /* + * The max submitted value memory must be usable with CPU atomics, + * which at least on ARM architectures requires cached mappings. + */ + maxSubmittedCoherency = DRF_VAL(OS32, _ATTR, _COHERENCY, pShared->pMaxSubmittedMem->Attr); + NV_CHECK_OR_ELSE(LEVEL_ERROR, + (maxSubmittedCoherency != NVOS32_ATTR_COHERENCY_UNCACHED) && + (maxSubmittedCoherency != NVOS32_ATTR_COHERENCY_WRITE_COMBINE), + status = NV_ERR_INVALID_PARAMETER; + goto ctorFailed); + } + + + NV_ASSERT_OK_OR_GOTO(status, _semsurfRegisterCallback(pSemSurf), ctorFailed); + + for (i = 0; _semsurfValidateIndex(pShared, i); i++) + { + _semsurfSetMonitoredValue(pShared, i, NV_U64_MAX); + } + + /* Any failures should have already taken the ctorFailed path */ + NV_ASSERT_OR_GOTO(status == NV_OK, ctorFailed); + + NV_PRINTF(LEVEL_NOTICE, + "SemSurf(0x%08x, 0x%08x): Constructed with SemMem(0x%08x, 0x%08x)\n", + RES_GET_CLIENT_HANDLE(pSemSurf), RES_GET_HANDLE(pSemSurf), + pShared->hClient, pShared->hSemaphoreMem); + + return NV_OK; + +ctorFailed: + _semsurfDestroyShared(pShared); + + return status; +} + +void +semsurfDestruct_IMPL +( + SemaphoreSurface *pSemSurf +) +{ + SEM_SHARED_DATA *pShared = pSemSurf->pShared; + SEM_INDEX_LISTENERS_NODE *pIndexListeners; + SEM_VALUE_LISTENERS_NODE *pValueListeners; + SEM_VALUE_LISTENERS_NODE *pNextValueListeners; + EVENTNOTIFICATION *pListener; + EVENTNOTIFICATION *pNextListener; + NvU64 minWaitValue; + NvU64 curIdx; + NvHandle hSemClient = RES_GET_CLIENT_HANDLE(pSemSurf); + NvHandle hSemSurf = RES_GET_HANDLE(pSemSurf); + NvHandle hSharedClient = pShared->hClient; + NvHandle hSharedMem = pShared->hSemaphoreMem; + + NV_ASSERT_OR_RETURN_VOID(pShared); + NV_ASSERT_OR_GOTO(pShared->pSpinlock, skipRemoveListeners); + + NV_PRINTF(LEVEL_NOTICE, + "SemSurf(0x%08x, 0x%08x): Destructor with SemMem(0x%08x, 0x%08x)\n", + hSemClient, hSemSurf, hSharedClient, hSharedMem); + + /* Remove any pending waiters instantiated via this sibling */ + NV_PRINTF(LEVEL_INFO, "SemMem(0x%08x, 0x%08x): Entering spinlock\n", + hSharedClient, hSharedMem); + + portSyncSpinlockAcquire(pShared->pSpinlock); + + for (pIndexListeners = mapFindGEQ(&pShared->listenerMap, 0); + pIndexListeners; + pIndexListeners = mapFindGEQ(&pShared->listenerMap, curIdx + 1)) + { + minWaitValue = NV_U64_MAX; + curIdx = mapKey(&pShared->listenerMap, pIndexListeners); + + for (pValueListeners = listHead(&pIndexListeners->listeners); + pValueListeners; + pValueListeners = pNextValueListeners) + { + for (pListener = pValueListeners->pListeners; + pListener; + pListener = pNextListener) + { + pNextListener = pListener->Next; + + if ((pListener->hEventClient == hSemClient) && + (pListener->hEvent == hSemSurf)) + { + NV_PRINTF(LEVEL_WARNING, + "SemSurf(0x%08x, 0x%08x): " + "Deleting active waiter at index %" NvU64_fmtu + " value %" NvU64_fmtu "\n", + hSemClient, + hSemSurf, + curIdx, + pValueListeners->value); + + unregisterEventNotificationWithData(&pValueListeners->pListeners, + hSemClient, + NV01_NULL_OBJECT, /* hNotifier/subdevice */ + hSemSurf, + NV_TRUE, /* match data/notificationHandle */ + pListener->Data); + } + } + + pNextValueListeners = listNext(&pIndexListeners->listeners, + pValueListeners); + + if (!pValueListeners->pListeners) + { + listRemove(&pIndexListeners->listeners, pValueListeners); + portMemFree(pValueListeners); + } + else if (pValueListeners->value < minWaitValue) + { + minWaitValue = pValueListeners->value; + } + } + + _semsurfSetMonitoredValue(pShared, + curIdx, + minWaitValue); + + if (listCount(&pIndexListeners->listeners) == 0) + { + NV_ASSERT(minWaitValue == NV_U64_MAX); + mapRemove(&pShared->listenerMap, pIndexListeners); + portMemFree(pIndexListeners); + } + } + + portSyncSpinlockRelease(pShared->pSpinlock); + NV_PRINTF(LEVEL_INFO, "SemMem(0x%08x, 0x%08x): Exited spinlock\n", + hSharedClient, hSharedMem); + +skipRemoveListeners: + NV_ASSERT(pShared->refCount > 0); + --pShared->refCount; + if (pShared->refCount <= 0) + _semsurfDestroyShared(pShared); +} + +NV_STATUS +semsurfCtrlCmdRefMemory_IMPL +( + SemaphoreSurface *pSemSurf, + NV_SEMAPHORE_SURFACE_CTRL_REF_MEMORY_PARAMS *pParams +) +{ + RM_API *pRmApi = rmapiGetInterface(RMAPI_GPU_LOCK_INTERNAL); + SEM_SHARED_DATA *pShared = pSemSurf->pShared; + NV_STATUS status = NV_OK; + NvHandle hSemMemOut = pParams->hSemaphoreMem; + NvHandle hMaxMemOut = pParams->hMaxSubmittedMem; + NvHandle hDeviceDst = RES_GET_HANDLE(GPU_RES_GET_DEVICE(pSemSurf)); + NvBool bSemMemDuped = NV_FALSE; + NvBool bMaxMemDuped = NV_FALSE; + + NV_CHECK_OK_OR_GOTO(status, + LEVEL_ERROR, + pRmApi->DupObject(pRmApi, + RES_GET_CLIENT_HANDLE(pSemSurf), + hDeviceDst, + &hSemMemOut, + pShared->hClient, + pShared->hSemaphoreMem, + 0), + error); + + bSemMemDuped = NV_TRUE; + + if (pShared->pMaxSubmittedMem) + { + if (pShared->pMaxSubmittedMem != pShared->pSemaphoreMem) + { + NV_CHECK_OK_OR_GOTO(status, + LEVEL_ERROR, + pRmApi->DupObject(pRmApi, + RES_GET_CLIENT_HANDLE(pSemSurf), + hDeviceDst, + &hMaxMemOut, + pShared->hClient, + pShared->hMaxSubmittedMem, + 0), + error); + + bMaxMemDuped = NV_TRUE; + } + else + { + if (pParams->hMaxSubmittedMem != pParams->hSemaphoreMem) + { + status = NV_ERR_INVALID_PARAMETER; + goto error; + } + + hMaxMemOut = hSemMemOut; + } + } + else + { + if (pParams->hMaxSubmittedMem != NV01_NULL_OBJECT) + { + return NV_ERR_INVALID_PARAMETER; + } + } + + pParams->hSemaphoreMem = hSemMemOut; + pParams->hMaxSubmittedMem = hMaxMemOut; + + return NV_OK; + +error: + if (bMaxMemDuped) + { + pRmApi->Free(pRmApi, + RES_GET_CLIENT_HANDLE(pSemSurf), + hMaxMemOut); + } + + if (bSemMemDuped) + { + pRmApi->Free(pRmApi, + RES_GET_CLIENT_HANDLE(pSemSurf), + hSemMemOut); + } + + return status; +} + +NV_STATUS +semsurfCtrlCmdBindChannel_IMPL +( + SemaphoreSurface *pSemSurf, + NV_SEMAPHORE_SURFACE_CTRL_BIND_CHANNEL_PARAMS *pParams +) +{ + return NV_ERR_NOT_SUPPORTED; +} + +NV_STATUS +_semsurfSetValueAndNotify +( + SemaphoreSurface *pSemSurf, + NvU64 index, + NvU64 newValue +) +{ + SEM_INDEX_LISTENERS_NODE *valueNode; + SEM_VALUE_LISTENERSIter vlIter; + SEM_PENDING_NOTIFICATIONS notifications; + NvU64 curValue; + NvU64 minWaitValue; + NvBool valueChanged = NV_TRUE; + + _semsurfSetValue(pSemSurf->pShared, index, newValue); + + while (valueChanged) + { + curValue = newValue; + listInitIntrusive(¬ifications); + + NV_PRINTF(LEVEL_INFO, "SemMem(0x%08x, 0x%08x): Entering spinlock\n", + pSemSurf->pShared->hClient, pSemSurf->pShared->hSemaphoreMem); + portSyncSpinlockAcquire(pSemSurf->pShared->pSpinlock); + + valueNode = mapFind(&pSemSurf->pShared->listenerMap, index); + + if (valueNode) + { + minWaitValue = NV_U64_MAX; + + for (vlIter = listIterAll(&valueNode->listeners); + listIterNext(&vlIter); + vlIter = listIterAll(&valueNode->listeners)) + { + NV_PRINTF(LEVEL_SILENT, + " Checking index %" NvU64_fmtu " value waiter %" + NvU64_fmtu " against semaphore value %" NvU64_fmtu + " from CPU write\n", + index, vlIter.pValue->value, curValue); + + if (curValue >= vlIter.pValue->value) + { + listInsertExisting(¬ifications, NULL, vlIter.pValue); + listRemove(&valueNode->listeners, vlIter.pValue); + if (vlIter.pValue->newValue != 0) + { + NV_ASSERT(vlIter.pValue->newValue >= newValue); + newValue = vlIter.pValue->newValue; + } + } + else + { + /* No other values at this index should be signaled yet. */ + minWaitValue = vlIter.pValue->value; + break; + } + } + + if (listCount(&valueNode->listeners) == 0) + { + NV_ASSERT(minWaitValue == NV_U64_MAX); + mapRemove(&pSemSurf->pShared->listenerMap, valueNode); + portMemFree(valueNode); + } + + _semsurfSetMonitoredValue(pSemSurf->pShared, index, minWaitValue); + } + + portSyncSpinlockRelease(pSemSurf->pShared->pSpinlock); + NV_PRINTF(LEVEL_INFO, "SemMem(0x%08x, 0x%08x): Exited spinlock\n", + pSemSurf->pShared->hClient, pSemSurf->pShared->hSemaphoreMem); + + // Send notifications outside of spinlock. They have already been removed + // from the object-wide lists, so their existance is private to this + // instance of this function now. Hence, no locking is required for this + // step. + valueChanged = _semsurfNotifyCompleted(pSemSurf->pShared, + ¬ifications); + + NV_ASSERT(!valueChanged || (newValue > curValue)); + } + + return NV_OK; +} + +static NV_STATUS +_semsurfAddWaiter +( + SemaphoreSurface *pSemSurf, + RsClient *pRsClient, + NvU32 hSemaphoreSurf, + NvU64 index, + NvU64 waitValue, + NvU64 newValue, + NvP64 notificationHandle, + NvBool bKernel +) +{ + SEM_INDEX_LISTENERS_NODE *pIndexListeners; + SEM_VALUE_LISTENERSIter vlIter; + SEM_VALUE_LISTENERS_NODE *pValueListeners; + EVENTNOTIFICATION *pListener; + NvHandle hClient = pRsClient->hClient; + NvBool valid; + NV_STATUS rmStatus = NV_OK; + NvU64 semValue; + NvU64 prevMinWaitValue = NV_U64_MAX; + + // The new value must be greater than the wait value to guarantee + // the monotonically incrementing behavior required of semaphore surface + // values. + if ((newValue != 0) && (newValue <= waitValue)) + { + NV_PRINTF(LEVEL_ERROR, + "SemSurf(0x%08x, 0x%08x): " + "Requested backwards update from %" NvU64_fmtu "->%" + NvU64_fmtu " at idx %" NvU64_fmtu "\n", + hClient, hSemaphoreSurf, waitValue, newValue, index); + return NV_ERR_INVALID_STATE; + } + + portSyncSpinlockAcquire(pSemSurf->pShared->pSpinlock); + + pIndexListeners = mapFind(&pSemSurf->pShared->listenerMap, index); + + if (pIndexListeners && listCount(&pIndexListeners->listeners) > 0) + { + pValueListeners = listHead(&pIndexListeners->listeners); + prevMinWaitValue = pValueListeners->value; + } + + /* Check if semaphore value has already been reached. This must be done + * inside the spinlock to prevent the following race from dropping + * notifications: + * + * -Enter RM control registering waiter for value 1 + * -RM control read current semaphore value 0 + * -GPU semaphore write land semaphore value 1 + * -GPU conditional TRAP non-stall interrupt. + * -RM interrupt handler walks handlers, finds no registered waiters + * -RM control proceeds, adds waiter for value 1. + * -No further interrupts are generated. + * -FAILURE - client's wait stalls indefinitely. + * + * Placing the value read inside the spinlock forces this deterministic + * ordering of the above events: + * + * -Enter RM control registering waiter for value 1 + * *lock* + * -RM control read current semaphore value 0 + * -GPU semaphore write land semaphore value 1 + * -GPU conditional TRAP non-stall interrupt. + * -RM interrupt handler walks handlers + * *lock* -- Blocks, defers rest of handler + * -RM control proceeds, adds waiter for value 1. + * *unlock + * -RM interrupt handler walks handlers + * *lock* -- Unblocks, defers rest of handler + * --finds the registered waiter, signals it + * *unlock* + * -SUCCESS - client's wait was signaled. + * + * Additionally, note there is a race involving checking the semaphore + * value and updating the monitored fence/conditional trap value here. In + * order for the semaphore surface event handler to have a chance to run + * and queue up a waiter list walk, the monitored fence value must be + * updated before the conditional trap methods execute. These execute + * after the methods to update the semaphore value, but the following + * race is possible if the monitored fence value is updated after the + * check for already-signalled semaphores: + * + * -RM control reads current semaphore value 0 + * *Semaphore not yet signaled. Proceed with registering a waiter* + * -GPU semaphore write land semaphore value 1 + * -GPU conditional TRAP executes: Monitored fence value indicates no waiter + * *Interrupt is not generated* + * -RM control updates monitored fence value to 1 + * -RM control finishes registering waiter on value 1 + * -FAILURE - conditional trap method has already executed, + * so waiter won't signal until something else generate san interrupt! + * + * Hence, enough work must be done to update the monitored fence value + * before checking for an already signalled semaphore, and then the + * monitored fence update, if any, must be undone if an already-signalled + * semaphore is indeed found. If the updated monitored fence value has + * already caused an interrupt to be generated, that's OK, the handler will + * just be a no-op. + */ + if (waitValue < prevMinWaitValue) + { + _semsurfSetMonitoredValue(pSemSurf->pShared, index, waitValue); + } + + semValue = _semsurfGetValue(pSemSurf->pShared, index); + + if (semValue >= waitValue) + { + NV_PRINTF(LEVEL_NOTICE, + "SemSurf(0x%08x, 0x%08x): " + "Detected already signalled wait for %" NvU64_fmtu + " at idx %" NvU64_fmtu " current val %" NvU64_fmtu "\n", + hClient, hSemaphoreSurf, waitValue, index, semValue); + rmStatus = NV_ERR_ALREADY_SIGNALLED; + goto failureUnlock; + } + + if (!pIndexListeners) + { + pIndexListeners = portMemAllocNonPaged(sizeof(*pIndexListeners)); + if (!pIndexListeners) + { + NV_PRINTF(LEVEL_ERROR, + "SemSurf(0x%08x, 0x%08x): " + "Failed to allocate a semaphore index listeners node\n", + hClient, hSemaphoreSurf); + rmStatus = NV_ERR_NO_MEMORY; + goto failureUnlock; + } + + listInitIntrusive(&pIndexListeners->listeners); + + if (!mapInsertExisting(&pSemSurf->pShared->listenerMap, + index, + pIndexListeners)) + { + NV_PRINTF(LEVEL_ERROR, + "SemSurf(0x%08x, 0x%08x): " + "Duplicate entry found for new index listener list\n", + hClient, hSemaphoreSurf); + portMemFree(pIndexListeners); + rmStatus = NV_ERR_INVALID_STATE; + goto failureUnlock; + } + } + + /* XXX Would be easier/faster if the value listener list was a priority queue */ + vlIter = listIterAll(&pIndexListeners->listeners); + while ((valid = listIterNext(&vlIter)) && vlIter.pValue->value < waitValue); + + if (valid && vlIter.pValue->value == waitValue) + { + pValueListeners = vlIter.pValue; + } + else + { + pValueListeners = portMemAllocNonPaged(sizeof(*pValueListeners)); + + if (!pValueListeners) + { + NV_PRINTF(LEVEL_ERROR, + "SemSurf(0x%08x, 0x%08x): " + "Failed to allocate a semaphore value listener node\n", + hClient, hSemaphoreSurf); + rmStatus = NV_ERR_NO_MEMORY; + goto cleanupIndexListener; + } + portMemSet(pValueListeners, 0, sizeof(*pValueListeners)); + + pValueListeners->value = waitValue; + pValueListeners->index = index; + + listInsertExisting(&pIndexListeners->listeners, + valid ? vlIter.pValue : NULL, pValueListeners); + } + + if (newValue) + { + // It is a client error if two waiters request to auto-update the value + // of a semaphore after it reaches the same prerequisite value, as the + // order of those signal two operations is indeterminate. This could be + // handled by taking the max here without violating any forward progress + // rules, but it is better to return an error given the likelyhood there + // is an error in the client's logic. + if ((pValueListeners->newValue != 0)) + { + NV_PRINTF(LEVEL_ERROR, + "SemSurf(0x%08x, 0x%08x): " + "Existing value-updating waiter at index %" NvU64_fmtu + " for wait value %" NvU64_fmtu ":\n Existing update " + "value: %" NvU64_fmtu "\n Requested update value: %" + NvU64_fmtu "\n", + hClient, hSemaphoreSurf, index, waitValue, + pValueListeners->newValue, newValue); + rmStatus = NV_ERR_STATE_IN_USE; + goto cleanupValueListener; + + } + pValueListeners->newValue = newValue; + } + + if (notificationHandle) + { + for (pListener = pValueListeners->pListeners; + pListener; + pListener = pListener->Next) + { + if (pListener->Data == notificationHandle) + { + NV_PRINTF(LEVEL_ERROR, + "SemSurf(0x%08x, 0x%08x): " + "Notification handle already registered at index %" + NvU64_fmtu " for wait value %" NvU64_fmtu ".\n", + hClient, hSemaphoreSurf, index, waitValue); + /* Back out the auto-update value applied above, if any */ + pValueListeners->newValue = 0; + rmStatus = NV_ERR_STATE_IN_USE; + goto cleanupValueListener; + } + } + + rmStatus = registerEventNotification(&pValueListeners->pListeners, + pRsClient, + NV01_NULL_OBJECT, /* hNotifier/subdevice */ + hSemaphoreSurf, + NV_SEMAPHORE_SURFACE_WAIT_VALUE | + NV01_EVENT_WITHOUT_EVENT_DATA, + /* + * Allow user to pass this in + * explicitly? Doesn't seem to provide + * any added value value and adds more + * parameter validation work + */ + bKernel ? + NV01_EVENT_KERNEL_CALLBACK_EX : + NV01_EVENT_WIN32_EVENT, + notificationHandle, + !bKernel); + + if (rmStatus != NV_OK) + { + NV_PRINTF(LEVEL_ERROR, + "SemSurf(0x%08x, 0x%08x): " + "Failed to register event notification for semaphore surface " + "listener at index %" NvU64_fmtu ", value %" NvU64_fmtu + ". Status: 0x%08x\n", + hClient, hSemaphoreSurf, index, waitValue, rmStatus); + goto cleanupValueListener; + } + } + + portSyncSpinlockRelease(pSemSurf->pShared->pSpinlock); + + NV_PRINTF(LEVEL_INFO, + "SemSurf(0x%08x, 0x%08x): " + "Registered semaphore surface value listener at index %" + NvU64_fmtu ", value %" NvU64_fmtu " current value %" NvU64_fmtu + " post-wait value %" NvU64_fmtu " notification: %" NvU64_fmtx "\n", + hClient, hSemaphoreSurf, index, waitValue, semValue, newValue, + (NvU64)notificationHandle); + + return rmStatus; + +cleanupValueListener: + if (!pValueListeners->pListeners) + { + listRemove(&pIndexListeners->listeners, pValueListeners); + portMemFree(pValueListeners); + } + +cleanupIndexListener: + if (listCount(&pIndexListeners->listeners) == 0) + { + mapRemove(&pSemSurf->pShared->listenerMap, pIndexListeners); + portMemFree(pIndexListeners); + } + +failureUnlock: + // Must be done with the lock. + if (waitValue < prevMinWaitValue) + { + _semsurfSetMonitoredValue(pSemSurf->pShared, index, prevMinWaitValue); + } + + portSyncSpinlockRelease(pSemSurf->pShared->pSpinlock); + + // There's no point of going through the trouble of notifying the waiter in + // this case, but it is worth immediately running the auto-update code here + // to avoid the need for the caller to call back in through the whole RMAPI + // framework with the set value control to emulate an auto-update itself. + // Just take care of it here. + if ((rmStatus == NV_ERR_ALREADY_SIGNALLED) && (newValue != 0)) + { + // On success, the ALREADY_SIGNALLED value must be preserved if the + // client also asked to register an OS event/callback. If no event/ + // callback was requested, return success, as there is all requested + // operations have been carried out. + // + // On error, the client must always be notified this call did nothing. + NV_STATUS setValStatus = _semsurfSetValueAndNotify(pSemSurf, + index, + newValue); + + if ((setValStatus != NV_OK) || !notificationHandle) + rmStatus = setValStatus; + } + + return rmStatus; +} + +NV_STATUS +semsurfCtrlCmdRegisterWaiter_IMPL +( + SemaphoreSurface *pSemSurf, + NV_SEMAPHORE_SURFACE_CTRL_REGISTER_WAITER_PARAMS *pParams +) +{ + CALL_CONTEXT *pCallContext = resservGetTlsCallContext(); + NvP64 notificationHandle = 0; + const NvBool bKernel = (pCallContext->secInfo.paramLocation == + PARAM_LOCATION_KERNEL); + NV_STATUS rmStatus = NV_OK; + + NV_CHECK_OR_RETURN(LEVEL_ERROR, + _semsurfValidateIndex(pSemSurf->pShared, pParams->index), + NV_ERR_INVALID_INDEX); + + if (pParams->notificationHandle) + { + if (bKernel) + { + notificationHandle = (NvP64)pParams->notificationHandle; + } + else + { + rmStatus = osUserHandleToKernelPtr(pCallContext->pClient->hClient, + (NvP64)pParams->notificationHandle, + ¬ificationHandle); + } + } + + if (rmStatus != NV_OK) + { + NV_PRINTF(LEVEL_ERROR, + "Invalid semaphore surface notification handle: 0x%016" + NvU64_fmtx ", status: %s (0x%08x)\n", + pParams->notificationHandle, nvstatusToString(rmStatus), + rmStatus); + return rmStatus; + } + + rmStatus = _semsurfAddWaiter(pSemSurf, + staticCast(RES_GET_CLIENT(pSemSurf), RsClient), + RES_GET_HANDLE(pSemSurf), + pParams->index, + pParams->waitValue, + pParams->newValue, + notificationHandle, + bKernel); + + return rmStatus; +} + +NV_STATUS +semsurfCtrlCmdSetValue_IMPL +( + SemaphoreSurface *pSemSurf, + NV_SEMAPHORE_SURFACE_CTRL_SET_VALUE_PARAMS *pParams +) +{ + NV_CHECK_OR_RETURN(LEVEL_ERROR, + _semsurfValidateIndex(pSemSurf->pShared, pParams->index), + NV_ERR_INVALID_INDEX); + + return _semsurfSetValueAndNotify(pSemSurf, + pParams->index, + pParams->newValue); +} + +static NV_STATUS +_semsurfDelWaiter +( + SemaphoreSurface *pSemSurf, + NvU64 index, + NvU64 waitValue, + NvP64 notificationHandle, + NvBool bKernel +) +{ + SEM_INDEX_LISTENERS_NODE *pIndexListeners; + SEM_VALUE_LISTENERSIter vlIter; + SEM_VALUE_LISTENERS_NODE *pValueListeners; + NvHandle hClient = RES_GET_CLIENT_HANDLE(pSemSurf); + NvHandle hSemaphoreSurf = RES_GET_HANDLE(pSemSurf); + NvBool valid; + NV_STATUS rmStatus = NV_ERR_GENERIC; + + NV_PRINTF(LEVEL_INFO, "SemMem(0x%08x, 0x%08x): Entering spinlock\n", + pSemSurf->pShared->hClient, + pSemSurf->pShared->hSemaphoreMem); + portSyncSpinlockAcquire(pSemSurf->pShared->pSpinlock); + + pIndexListeners = mapFind(&pSemSurf->pShared->listenerMap, index); + + if (!pIndexListeners) + goto unlockReturn; + + vlIter = listIterAll(&pIndexListeners->listeners); + while ((valid = listIterNext(&vlIter)) && vlIter.pValue->value < waitValue); + + if (!valid || (vlIter.pValue->value != waitValue)) + goto unlockReturn; + + pValueListeners = vlIter.pValue; + + rmStatus = unregisterEventNotificationWithData(&pValueListeners->pListeners, + hClient, + /* hNotifier/subdevice */ + NV01_NULL_OBJECT, + hSemaphoreSurf, + /* match notificationHandle */ + NV_TRUE, + notificationHandle); + + if (rmStatus != NVOS_STATUS_SUCCESS) + goto unlockReturn; + + NV_PRINTF(LEVEL_INFO, "SemSurf(0x%08x, 0x%08x): " + "Unregistered event notification " NvP64_fmt + " from semaphore surface listener at index %" NvU64_fmtu + ", value %" NvU64_fmtu ".\n", + hClient, hSemaphoreSurf, notificationHandle, index, waitValue); + + if (!pValueListeners->pListeners) + { + listRemove(&pIndexListeners->listeners, pValueListeners); + portMemFree(pValueListeners); + + if (listCount(&pIndexListeners->listeners) == 0) + { + mapRemove(&pSemSurf->pShared->listenerMap, pIndexListeners); + portMemFree(pIndexListeners); + _semsurfSetMonitoredValue(pSemSurf->pShared, index, NV_U64_MAX); + } + else + { + pValueListeners = listHead(&pIndexListeners->listeners); + _semsurfSetMonitoredValue(pSemSurf->pShared, index, + pValueListeners->value); + } + } + + rmStatus = NV_OK; + +unlockReturn: + portSyncSpinlockRelease(pSemSurf->pShared->pSpinlock); + NV_PRINTF(LEVEL_INFO, "SemMem(0x%08x, 0x%08x): Exited spinlock\n", + pSemSurf->pShared->hClient, pSemSurf->pShared->hSemaphoreMem); + + return rmStatus; +} + +NV_STATUS +semsurfCtrlCmdUnregisterWaiter_IMPL +( + SemaphoreSurface *pSemSurf, + NV_SEMAPHORE_SURFACE_CTRL_UNREGISTER_WAITER_PARAMS *pParams +) +{ + CALL_CONTEXT *pCallContext = resservGetTlsCallContext(); + NvP64 notificationHandle = 0; + const NvBool bKernel = (pCallContext->secInfo.paramLocation == + PARAM_LOCATION_KERNEL); + NV_STATUS rmStatus = NV_OK; + + NV_CHECK_OR_RETURN(LEVEL_ERROR, + _semsurfValidateIndex(pSemSurf->pShared, pParams->index), + NV_ERR_INVALID_INDEX); + + if (pParams->notificationHandle) + { + if (bKernel) + { + notificationHandle = (NvP64)pParams->notificationHandle; + } + else + { + rmStatus = osUserHandleToKernelPtr(pCallContext->pClient->hClient, + (NvP64)pParams->notificationHandle, + ¬ificationHandle); + } + } + + if (rmStatus != NV_OK) + { + NV_PRINTF(LEVEL_ERROR, + "Invalid semaphore surface notification handle: 0x%016" + NvU64_fmtx ", status: %s (0x%08x)\n", + pParams->notificationHandle, nvstatusToString(rmStatus), + rmStatus); + return rmStatus; + } + + rmStatus = _semsurfDelWaiter(pSemSurf, + pParams->index, + pParams->waitValue, + notificationHandle, + bKernel); + + return rmStatus; +} diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/kernel/gpu/mem_mgr/vaspace_api.c nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/kernel/gpu/mem_mgr/vaspace_api.c --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/kernel/gpu/mem_mgr/vaspace_api.c 2023-10-25 20:21:13.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/kernel/gpu/mem_mgr/vaspace_api.c 2024-03-05 22:13:38.000000000 +0000 @@ -43,7 +43,6 @@ /* ------------------ static and helper functions prototypes------------------*/ static NvU32 translateAllocFlagsToVASpaceFlags(NvU32 allocFlags, NvU32 *translatedFlags); static NvU32 translatePageSizeToVASpaceFlags(NV_VASPACE_ALLOCATION_PARAMETERS *pNvVASpaceAllocParams); -static void destroyMemDesc(Device *pDevice, NvHandle hVASpace); static NV_STATUS _vaspaceapiManagePageLevelsForSplitVaSpace(OBJGPU *pGpu, NvHandle hClient, NvU32 gpuMask, NvU32 flags, VASPACEAPI_MANAGE_PAGE_LEVELS_ACTION action); NvBool @@ -81,6 +80,8 @@ NvBool bLockAcquired = NV_FALSE; MemoryManager *pMemoryManager = GPU_GET_MEMORY_MANAGER(pGpu); KernelMIGManager *pKernelMIGManager = GPU_GET_KERNEL_MIG_MANAGER(pGpu); + NvU64 originalVaBase; + NvU64 originalVaSize; if (RS_IS_COPY_CTOR(pParams)) { @@ -116,6 +117,10 @@ pNvVASpaceAllocParams = pParams->pAllocParams; allocFlags = pNvVASpaceAllocParams->flags; + // These input parameters get overwritten later but original values are needed + originalVaBase = pNvVASpaceAllocParams->vaBase; + originalVaSize = pNvVASpaceAllocParams->vaSize; + // Translate & validate flags NV_CHECK_OK_OR_RETURN(LEVEL_WARNING, translateAllocFlagsToVASpaceFlags(allocFlags, &flags)); @@ -219,7 +224,7 @@ { // In case of SR-IOV, the BAR1 and FLA is managed by the guest. So, no need // to communicate with the host for BAR1 and FLA VA. - if ((pNvVASpaceAllocParams->index == NV_VASPACE_ALLOCATION_INDEX_GPU_HOST)) + if (pNvVASpaceAllocParams->index == NV_VASPACE_ALLOCATION_INDEX_GPU_HOST) bSendRPC = NV_FALSE; } @@ -237,6 +242,7 @@ pParams->hResource, pParams->externalClassId, pNvVASpaceAllocParams, + sizeof(*pNvVASpaceAllocParams), status); if (status != NV_OK) { @@ -328,34 +334,45 @@ // Get flags for the requested big page size flags |= translatePageSizeToVASpaceFlags(pNvVASpaceAllocParams); - if (0 != pNvVASpaceAllocParams->vaSize) + if (0 != originalVaSize) { // FLA VASpace can start from any base (!= 0) if (flags & VASPACE_FLAGS_FLA) { - vasLimit = pNvVASpaceAllocParams->vaBase + - pNvVASpaceAllocParams->vaSize - 1; - if (vasLimit < pNvVASpaceAllocParams->vaBase) + vasLimit = originalVaBase + originalVaSize - 1; + if (vasLimit < originalVaBase) { NV_PRINTF(LEVEL_ERROR, "Integer overflow !!! Invalid parameters for vaBase:%llx, vaSize:%llx\n", - pNvVASpaceAllocParams->vaBase, - pNvVASpaceAllocParams->vaSize); + originalVaBase, + originalVaSize); status = NV_ERR_INVALID_ARGUMENT; NV_ASSERT_OR_GOTO(0, done); } } else { - vasLimit = pNvVASpaceAllocParams->vaSize - 1; + vasLimit = originalVaSize - 1; } } + // + // Bug 3610538 For unlinked SLI, clients want to restrict internal buffers to + // Internal VA range. setting internal va range to match what we use for + // windows. + // + if (allocFlags & NV_VASPACE_ALLOCATION_FLAGS_VA_INTERNAL_LIMIT) + { + vaStartInternal = SPLIT_VAS_SERVER_RM_MANAGED_VA_START; + vaLimitInternal = SPLIT_VAS_SERVER_RM_MANAGED_VA_START + + SPLIT_VAS_SERVER_RM_MANAGED_VA_SIZE - 1; + } + // Finally call the factory status = vmmCreateVaspace(pVmm, pParams->externalClassId, pNvVASpaceAllocParams->index, gpuMask, - pNvVASpaceAllocParams->vaBase, + originalVaBase, vasLimit, vaStartInternal, vaLimitInternal, @@ -522,7 +539,6 @@ VASPACEAPI_MANAGE_PAGE_LEVELS_RELEASE); } - destroyMemDesc(pDevice, hVASpace); if ((vaspaceGetFlags(pVaspaceApi->pVASpace) & VASPACE_FLAGS_FLA)) { if (GPU_GET_KERNEL_BUS(pGpu)->flaInfo.pFlaVAS == NULL) @@ -561,52 +577,6 @@ pCallContext->pResourceRef->pParentRef); } -/*--------------------------static and helper functions ----------------------*/ -// move this to Device -/** - * @brief Destroy associated memory with this vaspace. - * - * @param[in] pDevice Pointer to Device instance - * @param[in] hVASpace VASpace handle of the vaspace that will be deleted - **/ -static void -destroyMemDesc -( - Device *pDevice, - NvHandle hVASpace -) -{ - VirtualMemory *pVirtualMemory = NULL; - RsClient *pClient = RES_GET_CLIENT(pDevice); - NODE *pNode = NULL; - RM_API *pRmApi = rmapiGetInterface(RMAPI_GPU_LOCK_INTERNAL); - - // - // RS-TODO: Convert to resource server dependency tracking system. - // stdmemConstruct calls add refAddDependant() but does it work properly for - // sharing (?) - // - - // Check if any memory linked to this VASpace hasn't been freed. - btreeEnumStart(0, &pNode, pDevice->DevMemoryTable); - while (pNode != NULL) - { - Memory *pMemory = pNode->Data; - pVirtualMemory = dynamicCast(pMemory, VirtualMemory); - btreeEnumNext(&pNode, pDevice->DevMemoryTable); - - if ((pVirtualMemory != NULL) && - virtmemMatchesVASpace(pVirtualMemory, pClient->hClient, hVASpace)) - { - // Free hMemory - pRmApi->Free(pRmApi, pClient->hClient, RES_GET_HANDLE(pVirtualMemory)); - - // Restart iteration as memory will be freed. - btreeEnumStart(0, &pNode, pDevice->DevMemoryTable); - } - } -} - /** * @brief Translate flags to vaspace equivalent flags and perform error check. * @@ -667,6 +637,10 @@ { flags |= VASPACE_FLAGS_REQUIRE_FIXED_OFFSET; } + if (allocFlags & NV_VASPACE_ALLOCATION_FLAGS_VA_INTERNAL_LIMIT) + { + flags |= VASPACE_FLAGS_RESTRICTED_RM_INTERNAL_VALIMITS; + } flags |= VASPACE_FLAGS_ENABLE_VMM; // Validate the flag combinations diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/kernel/gpu/mem_sys/arch/ampere/kern_mem_sys_ga100.c nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/kernel/gpu/mem_sys/arch/ampere/kern_mem_sys_ga100.c --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/kernel/gpu/mem_sys/arch/ampere/kern_mem_sys_ga100.c 2023-10-25 20:21:13.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/kernel/gpu/mem_sys/arch/ampere/kern_mem_sys_ga100.c 2024-03-05 22:13:38.000000000 +0000 @@ -30,6 +30,7 @@ #include "gpu/mem_mgr/mem_desc.h" #include "published/ampere/ga100/dev_fb.h" +#include "published/ampere/ga100/hwproject.h" /*! * @brief Write the sysmemFlushBuffer val into the NV_PFB_NISO_FLUSH_SYSMEM_ADDR register @@ -90,6 +91,9 @@ // if (pKernelMemorySystem->pSysmemFlushBufferMemDesc == NULL) { + NvU64 flags = MEMDESC_FLAGS_NONE; + + flags |= MEMDESC_FLAGS_ALLOC_IN_UNPROTECTED_MEMORY; // // Sysmem flush buffer // The sysmembar flush does a zero byte read of sysmem if there was a @@ -103,7 +107,7 @@ NV_TRUE, ADDR_SYSMEM, NV_MEMORY_UNCACHED, - MEMDESC_FLAGS_NONE); + flags); if (status != NV_OK) return status; @@ -262,14 +266,14 @@ { case 0: { - numBoundaries = 0; + numBoundaries = 0; partitionDivFactor = 1; break; } case 1: case 2: { - numBoundaries = 1; + numBoundaries = 1; partitionDivFactor = 2; break; } @@ -278,7 +282,7 @@ case 5: case 6: { - numBoundaries = 3; + numBoundaries = 3; partitionDivFactor = 4; break; } @@ -437,3 +441,13 @@ return NV_TRUE; } } + +NvU32 +kmemsysGetMaxFbpas_GA100 +( + OBJGPU *pGpu, + KernelMemorySystem *pKernelMemorySystem +) +{ + return NV_SCAL_LITTER_NUM_FBPAS; +} diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/kernel/gpu/mem_sys/arch/hopper/kern_mem_sys_gh100.c nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/kernel/gpu/mem_sys/arch/hopper/kern_mem_sys_gh100.c --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/kernel/gpu/mem_sys/arch/hopper/kern_mem_sys_gh100.c 2023-10-25 20:21:13.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/kernel/gpu/mem_sys/arch/hopper/kern_mem_sys_gh100.c 2024-03-05 22:13:38.000000000 +0000 @@ -32,7 +32,6 @@ #include "nverror.h" #include "published/hopper/gh100/dev_fb.h" -#include "published/hopper/gh100/dev_ltc.h" #include "published/hopper/gh100/dev_fbpa.h" #include "published/hopper/gh100/dev_vm.h" #include "published/hopper/gh100/pri_nv_xal_ep.h" @@ -409,200 +408,190 @@ (GPU_REG_RD_DRF(pGpu, _PFB, _FBHUB_PCIE_FLUSH_SYSMEM_ADDR_HI, _ADR) != 0)); } -/* - * @brief Function to map swizzId to VMMU Segments +/*! + * @brief Add GPU memory as a NUMA node. + * + * Add GPU memory as a NUMA node to the OS kernel in platforms where + * GPU is coherently connected to the CPU. + * + * @param[in] pGPU OBJGPU pointer + * @param[in] pKernelMemorySystem KernelMemorySystem pointer + * @param[in] swizzId swizzId of the MIG GPU instance, 0 for full GPU instance/non-MIG. + * @param[in] offset start offset of the GPU instance within FB + * @param[in] size size of the GPU instance + * @param[out] numaNodeId NUMA node id corresponding to the added @swizzId partition memory + * when NV_OK is returned. + * + * @returns NV_OK if all is okay. Otherwise an error-specific value. + * */ NV_STATUS -kmemsysSwizzIdToVmmuSegmentsRange_GH100 +kmemsysNumaAddMemory_GH100 ( - OBJGPU *pGpu, + OBJGPU *pGpu, KernelMemorySystem *pKernelMemorySystem, - NvU32 swizzId, - NvU32 vmmuSegmentSize, - NvU32 totalVmmuSegments + NvU32 swizzId, + NvU64 offset, + NvU64 size, + NvS32 *numaNodeId ) { - KernelMIGManager *pKernelMIGManager = GPU_GET_KERNEL_MIG_MANAGER(pGpu); - const KERNEL_MIG_MANAGER_STATIC_INFO *pStaticInfo = kmigmgrGetStaticInfo(pGpu, pKernelMIGManager); - NvU64 startingVmmuSegment; - NvU64 memSizeInVmmuSegment; + NV_STATUS status; + NvU64 memblockSize = 0; + NvU32 lNumaNodeId; - NV_ASSERT_OR_RETURN(swizzId < KMIGMGR_MAX_GPU_SWIZZID, NV_ERR_INVALID_ARGUMENT); - NV_ASSERT_OR_RETURN(pStaticInfo != NULL, NV_ERR_INVALID_STATE); - NV_ASSERT_OR_RETURN(pStaticInfo->pSwizzIdFbMemPageRanges != NULL, NV_ERR_INVALID_STATE); + NV_ASSERT_OK_OR_RETURN(osNumaMemblockSize(&memblockSize)); + NV_ASSERT_OR_RETURN(NV_IS_ALIGNED(size, memblockSize), NV_ERR_INVALID_STATE); - startingVmmuSegment = pStaticInfo->pSwizzIdFbMemPageRanges->fbMemPageRanges[swizzId].lo; - memSizeInVmmuSegment = pStaticInfo->pSwizzIdFbMemPageRanges->fbMemPageRanges[swizzId].hi - - pStaticInfo->pSwizzIdFbMemPageRanges->fbMemPageRanges[swizzId].lo; - NV_ASSERT_OR_RETURN((memSizeInVmmuSegment <= totalVmmuSegments), NV_ERR_INVALID_STATE); + if (pKernelMemorySystem->memPartitionNumaInfo[swizzId].bInUse) + { + NV_PRINTF(LEVEL_ERROR, "Memory partition: %u is already in use!\n", swizzId); + return NV_ERR_IN_USE; + } - NV_ASSERT_OK_OR_RETURN( - kmemsysInitMIGGPUInstanceMemConfigForSwizzId(pGpu, pKernelMemorySystem, swizzId, startingVmmuSegment, memSizeInVmmuSegment)); + status = osNumaAddGpuMemory(pGpu->pOsGpuInfo, offset, size, &lNumaNodeId); + if (status == NV_OK) + { + pKernelMemorySystem->memPartitionNumaInfo[swizzId].bInUse = NV_TRUE; + pKernelMemorySystem->memPartitionNumaInfo[swizzId].offset = offset; + pKernelMemorySystem->memPartitionNumaInfo[swizzId].size = size; + pKernelMemorySystem->memPartitionNumaInfo[swizzId].numaNodeId = lNumaNodeId; + *numaNodeId = lNumaNodeId; - return NV_OK; + pKernelMemorySystem->bNumaNodesAdded = NV_TRUE; + + NV_PRINTF(LEVEL_INFO, "Memory partition: %u added successfully!" + " numa id: %u offset: 0x%llx size: 0x%llx\n", + swizzId, lNumaNodeId, offset, size); + } + + return status; } + /*! - * Utility function used to read registers and ignore PRI errors + * @brief Remove a particular MIG GPU instance GPU memory from OS kernel. + * + * Remove GPU memory from the OS kernel that is earlier added as a NUMA node + * to the kernel in platforms where GPU is coherently connected to the CPU. + * + * @param[in] pGPU OBJGPU pointer + * @param[in] pKernelMemorySystem KernelMemorySystem pointer + * @param[in] swizzId swizzId of the MIG GPU instance, 0 for full partition/non-MIG. */ -static NvU32 -_kmemsysReadRegAndMaskPriError +void +kmemsysNumaRemoveMemory_GH100 ( - OBJGPU *pGpu, - NvU32 regAddr + OBJGPU *pGpu, + KernelMemorySystem *pKernelMemorySystem, + NvU32 swizzId ) { - NvU32 regVal; - - regVal = osGpuReadReg032(pGpu, regAddr); - if ((regVal & GPU_READ_PRI_ERROR_MASK) == GPU_READ_PRI_ERROR_CODE) + if (pKernelMemorySystem->memPartitionNumaInfo[swizzId].bInUse == NV_FALSE) { - return 0; + return; } - return regVal; + osNumaRemoveGpuMemory(pGpu->pOsGpuInfo, + pKernelMemorySystem->memPartitionNumaInfo[swizzId].offset, + pKernelMemorySystem->memPartitionNumaInfo[swizzId].size, + pKernelMemorySystem->memPartitionNumaInfo[swizzId].numaNodeId); + pKernelMemorySystem->memPartitionNumaInfo[swizzId].bInUse = NV_FALSE; + pKernelMemorySystem->memPartitionNumaInfo[swizzId].offset = 0; + pKernelMemorySystem->memPartitionNumaInfo[swizzId].size = 0; + pKernelMemorySystem->memPartitionNumaInfo[swizzId].numaNodeId = NV_U32_MAX; + + NV_PRINTF(LEVEL_INFO, "NVRM: memory partition: %u removed successfully!\n", + swizzId); + return; } -/* - * @brief Function that checks if ECC error occurred by reading various count - * registers/interrupt registers. This function is not floorsweeping-aware so - * PRI errors are ignored + +/*! + * @brief Remove all GPU memory from OS kernel. + * + * Remove all MIG GPU instances GPU memory from the OS kernel that is earlier added + * as a NUMA node to the kernel in platforms where GPU is coherently + * connected to the CPU. + * + * @param[in] pGPU OBJGPU pointer + * @param[in] pKernelMemorySystem KernelMemorySystem pointer + * */ void -kmemsysCheckEccCounts_GH100 +kmemsysNumaRemoveAllMemory_GH100 ( - OBJGPU *pGpu, + OBJGPU *pGpu, KernelMemorySystem *pKernelMemorySystem ) { - NvU32 dramCount = 0; - NvU32 mmuCount = 0; - NvU32 ltcCount = 0; - NvU32 pcieCount = 0; - NvU32 regVal; - for (NvU32 i = 0; i < NV_SCAL_LITTER_NUM_FBPAS; i++) - { - for (NvU32 j = 0; j < NV_PFB_FBPA_0_ECC_DED_COUNT__SIZE_1; j++) - { - // DRAM count read - dramCount += _kmemsysReadRegAndMaskPriError(pGpu, NV_PFB_FBPA_0_ECC_DED_COUNT(j) + (i * NV_FBPA_PRI_STRIDE)); - - // LTC count read - regVal = _kmemsysReadRegAndMaskPriError(pGpu, NV_PLTCG_LTC0_LTS0_L2_CACHE_ECC_UNCORRECTED_ERR_COUNT + - (i * NV_LTC_PRI_STRIDE) + (j * NV_LTS_PRI_STRIDE)); - ltcCount += DRF_VAL(_PLTCG_LTC0_LTS0, _L2_CACHE_ECC, _UNCORRECTED_ERR_COUNT_UNIQUE, regVal); - } - } - - // L2TLB - regVal = _kmemsysReadRegAndMaskPriError(pGpu, NV_PFB_PRI_MMU_L2TLB_ECC_UNCORRECTED_ERR_COUNT); - mmuCount += DRF_VAL(_PFB_PRI_MMU, _L2TLB_ECC, _UNCORRECTED_ERR_COUNT_UNIQUE, regVal); - - // HUBTLB - regVal = _kmemsysReadRegAndMaskPriError(pGpu, NV_PFB_PRI_MMU_HUBTLB_ECC_UNCORRECTED_ERR_COUNT); - mmuCount += DRF_VAL(_PFB_PRI_MMU, _HUBTLB_ECC, _UNCORRECTED_ERR_COUNT_UNIQUE, regVal); + NvU32 swizzId; - // FILLUNIT - regVal = _kmemsysReadRegAndMaskPriError(pGpu, NV_PFB_PRI_MMU_FILLUNIT_ECC_UNCORRECTED_ERR_COUNT); - mmuCount += DRF_VAL(_PFB_PRI_MMU, _FILLUNIT_ECC, _UNCORRECTED_ERR_COUNT_UNIQUE, regVal); - - // PCIE RBUF - regVal = _kmemsysReadRegAndMaskPriError(pGpu, NV_XPL_BASE_ADDRESS + NV_XPL_DL_ERR_COUNT_RBUF); - pcieCount += DRF_VAL(_XPL_DL, _ERR_COUNT_RBUF, _UNCORR_ERR, regVal); - - // PCIE SEQ_LUT - regVal = _kmemsysReadRegAndMaskPriError(pGpu, NV_XPL_BASE_ADDRESS + NV_XPL_DL_ERR_COUNT_SEQ_LUT); - pcieCount += DRF_VAL(_XPL_DL, _ERR_COUNT_SEQ_LUT, _UNCORR_ERR, regVal); - - // PCIE RE ORDER - regVal = _kmemsysReadRegAndMaskPriError(pGpu, NV_XAL_EP_REORDER_ECC_UNCORRECTED_ERR_COUNT); - pcieCount += DRF_VAL(_XAL_EP, _REORDER_ECC, _UNCORRECTED_ERR_COUNT_UNIQUE, regVal); - - // PCIE P2PREQ - regVal = _kmemsysReadRegAndMaskPriError(pGpu, NV_XAL_EP_P2PREQ_ECC_UNCORRECTED_ERR_COUNT); - pcieCount += DRF_VAL(_XAL_EP, _P2PREQ_ECC, _UNCORRECTED_ERR_COUNT_UNIQUE, regVal); - - // PCIE XTL - regVal = _kmemsysReadRegAndMaskPriError(pGpu, NV_XTL_BASE_ADDRESS + NV_XTL_EP_PRI_DED_ERROR_STATUS); - if (regVal != 0) - { - pcieCount += 1; - } - - // PCIE XTL - regVal = _kmemsysReadRegAndMaskPriError(pGpu, NV_XTL_BASE_ADDRESS + NV_XTL_EP_PRI_RAM_ERROR_INTR_STATUS); - if (regVal != 0) + for (swizzId = 0; swizzId < KMIGMGR_MAX_GPU_SWIZZID; swizzId++) { - pcieCount += 1; + kmemsysNumaRemoveMemory_HAL(pGpu, pKernelMemorySystem, swizzId); } - // If counts > 0 or if poison interrupt pending, ECC error has occurred. - if (((dramCount + ltcCount + mmuCount + pcieCount) != 0) || - intrIsVectorPending_HAL(pGpu, GPU_GET_INTR(pGpu), NV_PFB_FBHUB_POISON_INTR_VECTOR_HW_INIT, NULL)) - { - nvErrorLog_va((void *)pGpu, UNRECOVERABLE_ECC_ERROR_ESCAPE, - "An uncorrectable ECC error detected " - "(possible firmware handling failure) " - "DRAM:%d, LTC:%d, MMU:%d, PCIE:%d", dramCount, ltcCount, mmuCount, pcieCount); - } + return; } /* - * @brief Function that clears ECC error count registers. + * @brief Function to map swizzId to VMMU Segments */ NV_STATUS -kmemsysClearEccCounts_GH100 +kmemsysSwizzIdToVmmuSegmentsRange_GH100 ( OBJGPU *pGpu, - KernelMemorySystem *pKernelMemorySystem + KernelMemorySystem *pKernelMemorySystem, + NvU32 swizzId, + NvU32 vmmuSegmentSize, + NvU32 totalVmmuSegments ) { - NvU32 regVal = 0; - RMTIMEOUT timeout; - NV_STATUS status = NV_OK; - - gpuClearFbhubPoisonIntrForBug2924523_HAL(pGpu); + KernelMIGManager *pKernelMIGManager = GPU_GET_KERNEL_MIG_MANAGER(pGpu); + const KERNEL_MIG_MANAGER_STATIC_INFO *pStaticInfo = kmigmgrGetStaticInfo(pGpu, pKernelMIGManager); + NvU64 startingVmmuSegment; + NvU64 memSizeInVmmuSegment; - for (NvU32 i = 0; i < NV_SCAL_LITTER_NUM_FBPAS; i++) - { - for (NvU32 j = 0; j < NV_PFB_FBPA_0_ECC_DED_COUNT__SIZE_1; j++) - { - osGpuWriteReg032(pGpu, NV_PFB_FBPA_0_ECC_DED_COUNT(j) + (i * NV_FBPA_PRI_STRIDE), 0); - osGpuWriteReg032(pGpu, NV_PLTCG_LTC0_LTS0_L2_CACHE_ECC_UNCORRECTED_ERR_COUNT + (i * NV_LTC_PRI_STRIDE) + (j * NV_LTS_PRI_STRIDE), 0); - } - } + NV_ASSERT_OR_RETURN(swizzId < KMIGMGR_MAX_GPU_SWIZZID, NV_ERR_INVALID_ARGUMENT); + NV_ASSERT_OR_RETURN(pStaticInfo != NULL, NV_ERR_INVALID_STATE); + NV_ASSERT_OR_RETURN(pStaticInfo->pSwizzIdFbMemPageRanges != NULL, NV_ERR_INVALID_STATE); - // Reset MMU counts - osGpuWriteReg032(pGpu, NV_PFB_PRI_MMU_L2TLB_ECC_UNCORRECTED_ERR_COUNT, 0); - osGpuWriteReg032(pGpu, NV_PFB_PRI_MMU_HUBTLB_ECC_UNCORRECTED_ERR_COUNT, 0); - osGpuWriteReg032(pGpu, NV_PFB_PRI_MMU_FILLUNIT_ECC_UNCORRECTED_ERR_COUNT, 0); - - // Reset XAL-EP counts - osGpuWriteReg032(pGpu, NV_XAL_EP_REORDER_ECC_UNCORRECTED_ERR_COUNT, 0); - osGpuWriteReg032(pGpu, NV_XAL_EP_P2PREQ_ECC_UNCORRECTED_ERR_COUNT, 0); - - // Reset XTL-EP status registers - osGpuWriteReg032(pGpu, NV_XTL_BASE_ADDRESS + NV_XTL_EP_PRI_DED_ERROR_STATUS, ~0); - osGpuWriteReg032(pGpu, NV_XTL_BASE_ADDRESS + NV_XTL_EP_PRI_RAM_ERROR_INTR_STATUS, ~0); - - // Reset XPL-EP error counters - regVal = DRF_DEF(_XPL, _DL_ERR_RESET, _RBUF_UNCORR_ERR_COUNT, _PENDING) | - DRF_DEF(_XPL, _DL_ERR_RESET, _SEQ_LUT_UNCORR_ERR_COUNT, _PENDING); - osGpuWriteReg032(pGpu, NV_XPL_BASE_ADDRESS + NV_XPL_DL_ERR_RESET, regVal); + startingVmmuSegment = pStaticInfo->pSwizzIdFbMemPageRanges->fbMemPageRanges[swizzId].lo; + memSizeInVmmuSegment = (pStaticInfo->pSwizzIdFbMemPageRanges->fbMemPageRanges[swizzId].hi - + pStaticInfo->pSwizzIdFbMemPageRanges->fbMemPageRanges[swizzId].lo + 1); - // Wait for the error counter reset to complete - gpuSetTimeout(pGpu, GPU_TIMEOUT_DEFAULT, &timeout, 0); - for (;;) + if (memSizeInVmmuSegment > totalVmmuSegments) { - status = gpuCheckTimeout(pGpu, &timeout); - - regVal = osGpuReadReg032(pGpu, NV_XPL_BASE_ADDRESS + NV_XPL_DL_ERR_RESET); - - if (FLD_TEST_DRF(_XPL, _DL_ERR_RESET, _RBUF_UNCORR_ERR_COUNT, _DONE, regVal) && - FLD_TEST_DRF(_XPL, _DL_ERR_RESET, _SEQ_LUT_UNCORR_ERR_COUNT, _DONE, regVal)) - break; - - if (status != NV_OK) - return status; + // + // SwizzID-0 should cover only partitionable range, however for AMAP, + // there is no difference between swizzID-0 and no MIG which can result in + // AMAP returning an additional vmmuSegment for swizzID-0 + // + NV_ASSERT_OR_RETURN((swizzId == 0), NV_ERR_INVALID_STATE); } + NV_ASSERT_OK_OR_RETURN( + kmemsysInitMIGGPUInstanceMemConfigForSwizzId(pGpu, pKernelMemorySystem, swizzId, startingVmmuSegment, memSizeInVmmuSegment)); + return NV_OK; } +NvU32 +kmemsysGetEccDedCountSize_GH100 +( + OBJGPU *pGpu, + KernelMemorySystem *pKernelMemorySystem +) +{ + return NV_PFB_FBPA_0_ECC_DED_COUNT__SIZE_1; +} + +NvU32 +kmemsysGetEccDedCountRegAddr_GH100 +( + OBJGPU *pGpu, + KernelMemorySystem *pKernelMemorySystem, + NvU32 fbpa, + NvU32 subp +) +{ + return NV_PFB_FBPA_0_ECC_DED_COUNT(fbpa) + (subp * NV_FBPA_PRI_STRIDE); +} diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/kernel/gpu/mem_sys/arch/turing/kern_mem_sys_tu102.c nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/kernel/gpu/mem_sys/arch/turing/kern_mem_sys_tu102.c --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/kernel/gpu/mem_sys/arch/turing/kern_mem_sys_tu102.c 2023-10-25 20:21:13.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/kernel/gpu/mem_sys/arch/turing/kern_mem_sys_tu102.c 2024-03-05 22:13:39.000000000 +0000 @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 2017-2021 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2017-2024 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -26,6 +26,9 @@ #include "gpu/mem_sys/kern_mem_sys.h" #include "published/turing/tu102/dev_vm.h" +#include "published/turing/tu102/hwproject.h" +#include "published/turing/tu102/dev_fbpa.h" +#include "published/turing/tu102/dev_ltc.h" void kmemsysWriteL2SysmemInvalidateReg_TU102 @@ -68,3 +71,93 @@ { return GPU_VREG_RD32(pGpu, NV_VIRTUAL_FUNCTION_PRIV_L2_PEERMEM_INVALIDATE); } + +NvU32 +kmemsysGetMaxFbpas_TU102 +( + OBJGPU *pGpu, + KernelMemorySystem *pKernelMemorySystem +) +{ + return NV_SCAL_LITTER_NUM_FBPAS; +} + +NvU32 kmemsysGetEccDedCountSize_TU102 +( + OBJGPU *pGpu, + KernelMemorySystem *pKernelMemorySystem +) +{ + return NV_PFB_FBPA_0_ECC_DED_COUNT__SIZE_1; +} + +NvU32 kmemsysGetEccDedCountRegAddr_TU102 +( + OBJGPU *pGpu, + KernelMemorySystem *pKernelMemorySystem, + NvU32 fbpa, + NvU32 subp +) +{ + return NV_PFB_FBPA_0_ECC_DED_COUNT(fbpa) + (subp * NV_FBPA_PRI_STRIDE); +} + +/*! + * Utility function used to read registers and ignore PRI errors + */ +static NvU32 +_kmemsysReadRegAndMaskPriError +( + OBJGPU *pGpu, + NvU32 regAddr +) +{ + NvU32 regVal; + + regVal = osGpuReadReg032(pGpu, regAddr); + if (regVal == GPU_REG_VALUE_INVALID) + return 0; + + if ((regVal & GPU_READ_PRI_ERROR_MASK) == GPU_READ_PRI_ERROR_CODE) + return 0; + + return regVal; +} + +void +kmemsysGetEccCounts_TU102 +( + OBJGPU *pGpu, + KernelMemorySystem *pKernelMemorySystem, + NvU32 *dramCount, + NvU32 *ltcCount +) +{ + NvU32 maxFbpas = kmemsysGetMaxFbpas_HAL(pGpu, pKernelMemorySystem); + NvU32 dedCountSize = kmemsysGetEccDedCountSize_HAL(pGpu, pKernelMemorySystem); + NvU32 fbpaDedCountRegAddr = 0; + NvU32 regVal; + + if (dramCount == NULL || ltcCount == NULL) + { + return; + } + + *dramCount = 0; + *ltcCount = 0; + + for (NvU32 i = 0; i < maxFbpas; i++) + { + for (NvU32 j = 0; j < dedCountSize; j++) + { + // DRAM count read + fbpaDedCountRegAddr = kmemsysGetEccDedCountRegAddr_HAL(pGpu, pKernelMemorySystem, i, j); + *dramCount += _kmemsysReadRegAndMaskPriError(pGpu, fbpaDedCountRegAddr); + + // LTC count read + regVal = _kmemsysReadRegAndMaskPriError(pGpu, NV_PLTCG_LTC0_LTS0_L2_CACHE_ECC_UNCORRECTED_ERR_COUNT + + (i * NV_LTC_PRI_STRIDE) + (j * NV_LTS_PRI_STRIDE)); + *ltcCount += DRF_VAL(_PLTCG_LTC0_LTS0, _L2_CACHE_ECC, _UNCORRECTED_ERR_COUNT_UNIQUE, regVal); + } + } +} diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/kernel/gpu/mem_sys/arch/volta/kern_mem_sys_gv100.c nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/kernel/gpu/mem_sys/arch/volta/kern_mem_sys_gv100.c --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/kernel/gpu/mem_sys/arch/volta/kern_mem_sys_gv100.c 2023-10-25 20:21:14.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/kernel/gpu/mem_sys/arch/volta/kern_mem_sys_gv100.c 2024-03-05 22:13:39.000000000 +0000 @@ -25,6 +25,10 @@ #include "gpu/gpu.h" #include "os/os.h" #include "gpu/mem_sys/kern_mem_sys.h" +#include "gpu/bus/kern_bus.h" +#include "gpu/bus/p2p_api.h" +#include "gpu/nvlink/kernel_nvlink.h" +#include "published/volta/gv100/dev_mmu.h" /*! * @brief Get physical address of the FB memory on systems where GPU memory @@ -32,7 +36,7 @@ * * @param[in] pGpu OBJGPU pointer * @param[in] pKernelMemorySystem pointer to the kernel side KernelMemorySystem instance. - * @param[in] physAddr Physical Address of FB memory + * @param[in] physAddr Physical Address of FB memory * @param[in] numaNodeId NUMA node id where FB memory is added to the * kernel * @@ -58,3 +62,346 @@ return status; } + +/*! + * @brief Determine whether RM needs to invalidate GPU L2 cache during map call + * + * @param[in] pGpu OBJGPU pointer + * @param[in] pKernelMemorySystem pointer to the kernel side KernelMemorySystem instance. + * @param[in] bIsVolatile Whether the map call is to create vol mapping + * @param[in] aperture Aperture of the memory being mapped + * + * @return NV_OK on success + */ +NvBool +kmemsysNeedInvalidateGpuCacheOnMap_GV100 +( + OBJGPU *pGpu, + KernelMemorySystem *pKernelMemorySystem, + NvBool bIsVolatile, + NvU32 aperture +) +{ + // + // Only need to invalidate L2 for cached (vol=0) mapping to sys/peer memory + // because GPU's L2 is not coherent with CPU updates to sysmem + // See bug 3342220 for more info + // + return (!bIsVolatile && (aperture == NV_MMU_PTE_APERTURE_PEER_MEMORY || + aperture == NV_MMU_PTE_APERTURE_SYSTEM_COHERENT_MEMORY || + aperture == NV_MMU_PTE_APERTURE_SYSTEM_NON_COHERENT_MEMORY)); +} + +/*! + * @brief Configure local GPU's peer ATS config using peer GPU's local + * ATS config. + * + * @param[in] pLocalGpu Local GPU OBJGPU pointer + * @param[in] pLocalKernelMemorySystem Local GPU KernelMemorySystem pointer + * @param[in] pRemoteGpu Remote GPU OBJGPU pointer + * @param[in] peerId peer id from local GPU to remote GPU in + * local GPU + * + * @return NV_OK on success + */ +static +NV_STATUS +_kmemsysConfigureAtsPeers +( + OBJGPU *pLocalGpu, + KernelMemorySystem *pLocalKernelMemorySystem, + OBJGPU *pRemoteGpu, + NvU32 peerId +) +{ + RM_API *pLocalRmApi = GPU_GET_PHYSICAL_RMAPI(pLocalGpu); + RM_API *pRemoteRmApi = GPU_GET_PHYSICAL_RMAPI(pRemoteGpu); + NV2080_CTRL_INTERNAL_MEMSYS_GET_LOCAL_ATS_CONFIG_PARAMS getParams = { 0 }; + NV2080_CTRL_INTERNAL_MEMSYS_SET_PEER_ATS_CONFIG_PARAMS setParams = { 0 }; + + NV_ASSERT_OK_OR_RETURN(pRemoteRmApi->Control(pRemoteRmApi, + pRemoteGpu->hInternalClient, + pRemoteGpu->hInternalSubdevice, + NV2080_CTRL_CMD_INTERNAL_MEMSYS_GET_LOCAL_ATS_CONFIG, + &getParams, + sizeof(NV2080_CTRL_INTERNAL_MEMSYS_GET_LOCAL_ATS_CONFIG_PARAMS))); + setParams.peerId = peerId; + setParams.addrSysPhys = getParams.addrSysPhys; + setParams.addrWidth = getParams.addrWidth; + setParams.mask = getParams.mask; + setParams.maskWidth = getParams.maskWidth; + + NV_ASSERT_OK_OR_RETURN(pLocalRmApi->Control(pLocalRmApi, + pLocalGpu->hInternalClient, + pLocalGpu->hInternalSubdevice, + NV2080_CTRL_CMD_INTERNAL_MEMSYS_SET_PEER_ATS_CONFIG, + &setParams, + sizeof(NV2080_CTRL_INTERNAL_MEMSYS_SET_PEER_ATS_CONFIG_PARAMS))); + + return NV_OK; +} + +/*! + * @brief Remove local GPU's peer ATS config + * + * @param[in] pLocalGpu Local GPU OBJGPU pointer + * @param[in] pLocalKernelMemorySystem Local GPU KernelMemorySystem pointer + * @param[in] peerId peer id from local GPU to remote GPU in + * local GPU + * + * @return NV_OK on success + */ +static +NV_STATUS +_kmemsysResetAtsPeerConfiguration +( + OBJGPU *pLocalGpu, + KernelMemorySystem *pLocalKernelMemorySystem, + NvU32 peerId +) +{ + RM_API *pLocalRmApi = GPU_GET_PHYSICAL_RMAPI(pLocalGpu); + NV2080_CTRL_INTERNAL_MEMSYS_GET_LOCAL_ATS_CONFIG_PARAMS getParams = { 0 }; + NV2080_CTRL_INTERNAL_MEMSYS_SET_PEER_ATS_CONFIG_PARAMS setParams = { 0 }; + + NV_ASSERT_OK_OR_RETURN(pLocalRmApi->Control(pLocalRmApi, + pLocalGpu->hInternalClient, + pLocalGpu->hInternalSubdevice, + NV2080_CTRL_CMD_INTERNAL_MEMSYS_GET_LOCAL_ATS_CONFIG, + &getParams, + sizeof(NV2080_CTRL_INTERNAL_MEMSYS_GET_LOCAL_ATS_CONFIG_PARAMS))); + + setParams.peerId = peerId; + setParams.addrSysPhys = 0; + setParams.addrWidth = getParams.addrWidth; + setParams.mask = 0; + setParams.maskWidth = getParams.maskWidth; + + NV_ASSERT_OK_OR_RETURN(pLocalRmApi->Control(pLocalRmApi, + pLocalGpu->hInternalClient, + pLocalGpu->hInternalSubdevice, + NV2080_CTRL_CMD_INTERNAL_MEMSYS_SET_PEER_ATS_CONFIG, + &setParams, + sizeof(NV2080_CTRL_INTERNAL_MEMSYS_SET_PEER_ATS_CONFIG_PARAMS))); + + return NV_OK; +} + +/** + * @brief Setup one pair of ATS peers (non-chiplib configs) + * + * @param[in] pGpu OBJGPU pointer + * @param[in] pKernelMemorySystem Kernel Memory System pointer + * @param[in] pRemoteGpu OBJGPU pointer for the ATS peer + * + * @return NV_OK on success + */ +static +NV_STATUS +_kmemsysSetupAtsPeers +( + OBJGPU *pGpu, + KernelMemorySystem *pKernelMemorySystem, + OBJGPU *pRemoteGpu +) +{ + NvU32 peer1 = BUS_INVALID_PEER; + NvU32 peer2 = BUS_INVALID_PEER; + NV_STATUS status = NV_OK; + KernelNvlink *pKernelNvlink = GPU_GET_KERNEL_NVLINK(pGpu); + KernelMemorySystem *pLocalKernelMs = NULL; + KernelMemorySystem *pRemoteKernelMs = NULL; + NvU32 attributes = DRF_DEF(_P2PAPI, _ATTRIBUTES, _CONNECTION_TYPE, _NVLINK) | + DRF_DEF(_P2PAPI, _ATTRIBUTES, _LINK_TYPE, _SPA); + + // Set up P2P ATS configuration + pLocalKernelMs = pKernelMemorySystem; + pRemoteKernelMs = GPU_GET_KERNEL_MEMORY_SYSTEM(pRemoteGpu); + + if (pKernelNvlink != NULL) + { + // Trigger P2P link training to HS before releasing credits on P9 + knvlinkTrainP2pLinksToActive(pGpu, pRemoteGpu, pKernelNvlink); + } + + status = kbusCreateP2PMapping_HAL(pGpu, GPU_GET_KERNEL_BUS(pGpu), pRemoteGpu, GPU_GET_KERNEL_BUS(pRemoteGpu), + &peer1, &peer2, attributes); + if (status != NV_OK) + { + return status; + } + + if (pLocalKernelMs && pRemoteKernelMs && + pGpu->getProperty(pGpu, PDB_PROP_GPU_ATS_SUPPORTED) && + pRemoteGpu->getProperty(pRemoteGpu, PDB_PROP_GPU_ATS_SUPPORTED)) + { + status = _kmemsysConfigureAtsPeers(pGpu, pLocalKernelMs, pRemoteGpu, peer1); + if (status != NV_OK) + { + NV_PRINTF(LEVEL_ERROR, + "Configuring ATS p2p config between GPU%u and GPU%u " + "failed with status %x\n", pGpu->gpuInstance, + pRemoteGpu->gpuInstance, status); + return status; + } + + status = _kmemsysConfigureAtsPeers(pRemoteGpu, pRemoteKernelMs, pGpu, peer2); + if (status != NV_OK) + { + NV_PRINTF(LEVEL_ERROR, + "Configuring ATS p2p config between GPU%u and GPU%u " + "failed with status %x\n", pRemoteGpu->gpuInstance, + pGpu->gpuInstance, status); + return status; + } + } + + return NV_OK; +} + +/** + * @brief Remove one pair of ATS peers (non-chiplib configs) + * + * @param[in] pGpu OBJGPU pointer + * @param[in] pKernelMemorySystem Kernel Memory System pointer + * @param[in] pRemoteGpu OBJGPU pointer for the ATS peer + * + * @return NV_OK on success + */ +static +NV_STATUS +_kmemsysRemoveAtsPeers +( + OBJGPU *pGpu, + KernelMemorySystem *pKernelMemorySystem, + OBJGPU *pRemoteGpu +) +{ + NvU32 peer1 = BUS_INVALID_PEER; + NvU32 peer2 = BUS_INVALID_PEER; + NV_STATUS status = NV_OK; + KernelMemorySystem *pLocalKernelMs = NULL; + KernelMemorySystem *pRemoteKernelMs = NULL; + NvU32 attributes = DRF_DEF(_P2PAPI, _ATTRIBUTES, _CONNECTION_TYPE, _NVLINK) | + DRF_DEF(_P2PAPI, _ATTRIBUTES, _LINK_TYPE, _SPA); + + pLocalKernelMs = pKernelMemorySystem; + pRemoteKernelMs = GPU_GET_KERNEL_MEMORY_SYSTEM(pRemoteGpu); + + peer1 = kbusGetPeerId_HAL(pGpu, GPU_GET_KERNEL_BUS(pGpu), pRemoteGpu); + peer2 = kbusGetPeerId_HAL(pRemoteGpu, GPU_GET_KERNEL_BUS(pRemoteGpu), pGpu); + + status = kbusRemoveP2PMapping_HAL(pGpu, GPU_GET_KERNEL_BUS(pGpu), pRemoteGpu, GPU_GET_KERNEL_BUS(pRemoteGpu), + peer1, peer2, attributes); + if (status != NV_OK) + { + return status; + } + + if (pLocalKernelMs && pRemoteKernelMs && + pGpu->getProperty(pGpu, PDB_PROP_GPU_ATS_SUPPORTED) && + pRemoteGpu->getProperty(pRemoteGpu, PDB_PROP_GPU_ATS_SUPPORTED)) + { + status = _kmemsysResetAtsPeerConfiguration(pGpu, pLocalKernelMs, peer1); + if (status != NV_OK) + { + NV_PRINTF(LEVEL_ERROR, + "Removing ATS p2p config between GPU%u and GPU%u " + "failed with status %x\n", pGpu->gpuInstance, + pRemoteGpu->gpuInstance, status); + } + + status = _kmemsysResetAtsPeerConfiguration(pRemoteGpu, pRemoteKernelMs, peer2); + if (status != NV_OK) + { + NV_PRINTF(LEVEL_ERROR, + "Removinging ATS p2p config between GPU%u and GPU%u " + "failed with status %x\n", pRemoteGpu->gpuInstance, + pGpu->gpuInstance, status); + } + } + + return NV_OK; +} + +/** + * @brief Setup ATS peer access. On GV100 and GH180, ATS peers use NVLINK. + * + * @param[in] pGpu OBJGPU pointer + * @param[in] pKernelMemorySystem Kernel Memory System pointer + * + * @return NV_OK on success + */ +NV_STATUS +kmemsysSetupAllAtsPeers_GV100 +( + OBJGPU *pGpu, + KernelMemorySystem *pKernelMemorySystem +) +{ + KernelNvlink *pKernelNvlink = GPU_GET_KERNEL_NVLINK(pGpu); + NvU32 gpuAttachCnt, gpuAttachMask, gpuInstance = 0; + + NV_STATUS status = NV_OK; + POBJGPU pRemoteGpu = NULL; + + NV_CHECK_OR_RETURN(LEVEL_WARNING, pKernelNvlink != NULL, status); + + // loop over all possible GPU pairs and setup the ATS config + gpumgrGetGpuAttachInfo(&gpuAttachCnt, &gpuAttachMask); + while ((pRemoteGpu = gpumgrGetNextGpu(gpuAttachMask, &gpuInstance)) != NULL) + { + if (pRemoteGpu == pGpu) + continue; + + if (gpuIsGpuFullPower(pRemoteGpu) == NV_FALSE) + continue; + + if (!knvlinkIsNvlinkP2pSupported(pGpu, pKernelNvlink, pRemoteGpu)) + continue; + + status = _kmemsysSetupAtsPeers(pGpu, pKernelMemorySystem, pRemoteGpu); + if (status != NV_OK) + return status; + } + + return NV_OK; +} + +/** + * @brief Remove ATS peer access. On GV100 and GH180, ATS peers use NVLINK. + * + * @param[in] pGpu OBJGPU pointer + * @param[in] pKernelMemorySystem Kernel Memory System pointer + */ +void +kmemsysRemoveAllAtsPeers_GV100 +( + OBJGPU *pGpu, + KernelMemorySystem *pKernelMemorySystem +) +{ + NvU32 gpuAttachCnt, gpuAttachMask, gpuInstance = 0; + + NV_STATUS status = NV_OK; + POBJGPU pRemoteGpu = NULL; + + // loop over all possible GPU pairs and remove the ATS config + gpumgrGetGpuAttachInfo(&gpuAttachCnt, &gpuAttachMask); + while ((pRemoteGpu = gpumgrGetNextGpu(gpuAttachMask, &gpuInstance)) != NULL) + { + if (pRemoteGpu == pGpu) + continue; + + if (gpuIsGpuFullPower(pRemoteGpu) == NV_FALSE) + continue; + + status = _kmemsysRemoveAtsPeers(pGpu, pKernelMemorySystem, pRemoteGpu); + if (status != NV_OK) + { + NV_PRINTF(LEVEL_ERROR, "Failed to remove ATS peer access between GPU%d and GPU%d\n", + pGpu->gpuInstance, pRemoteGpu->gpuInstance); + } + } +} + diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/kernel/gpu/mem_sys/kern_mem_sys.c nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/kernel/gpu/mem_sys/kern_mem_sys.c --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/kernel/gpu/mem_sys/kern_mem_sys.c 2023-10-25 20:21:14.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/kernel/gpu/mem_sys/kern_mem_sys.c 2024-03-05 22:13:39.000000000 +0000 @@ -78,10 +78,10 @@ /* * Initialize the Kernel Memory System state. - * + * * @param[in] pGpu pointer to the GPU instance. * @param[in] pKernelMemorySystem pointer to the kernel side KernelMemorySystem instance. - * + * * @return NV_OK upon success. */ NV_STATUS kmemsysStateInitLocked_IMPL @@ -105,6 +105,58 @@ pKernelMemorySystem->pStaticConfig = pStaticConfig; + KernelBif *pKernelBif = GPU_GET_KERNEL_BIF(pGpu); + + pKernelMemorySystem->memPartitionNumaInfo = portMemAllocNonPaged(sizeof(MEM_PARTITION_NUMA_INFO) * KMIGMGR_MAX_GPU_SWIZZID); + if (pKernelMemorySystem->memPartitionNumaInfo == NULL) + { + NV_PRINTF(LEVEL_ERROR, "Failed to allocate memory for numa information.\n"); + status = NV_ERR_NO_MEMORY; + NV_ASSERT_OR_GOTO(0, fail); + } + portMemSet(pKernelMemorySystem->memPartitionNumaInfo, 0, sizeof(MEM_PARTITION_NUMA_INFO) * KMIGMGR_MAX_GPU_SWIZZID); + + if (gpuIsSelfHosted(pGpu) && + (pKernelBif != NULL) && pKernelBif->getProperty(pKernelBif, PDB_PROP_KBIF_IS_C2C_LINK_UP)) + { + // + // memsysSetupCoherentCpuLink should be done only for the self hosted + // configuration(SHH) where the coherent C2C link connects host CPU(TH500) and GPU + // and not in the externally hosted(EHH) case where host CPU(say x86) is connected + // to GPU through PCIe and C2C only connects the TH500 (for EGM memory) and GPU. + // The gpuIsSelfHosted(pGpu) check here is to distinguish between the SHH + // and EHH configuration as C2C link is up in both of these cases. + // + + if (IS_GSP_CLIENT(pGpu)) + { + GspStaticConfigInfo *pGSCI = GPU_GET_GSP_STATIC_INFO(pGpu); + + if (pGSCI->bAtsSupported) + { + NV_PRINTF(LEVEL_INFO, "ATS supported\n"); + + pGpu->setProperty(pGpu, PDB_PROP_GPU_ATS_SUPPORTED, NV_TRUE); + } + + // + // PDB_PROP_GPU_C2C_SYSMEM is already set in physical RM but not in + // in Kernel-RM where it is actually consumed. setting PDB_PROP_GPU_C2C_SYSMEM + // in Kernel-RM when the platform is self-hosted and the C2C links are up, which + // indicate the C2C is connected to CPU and Physical-RM would have set up the HSHUB + // to route sysmem through C2C. + // + pGpu->setProperty(pGpu, PDB_PROP_GPU_C2C_SYSMEM, NV_TRUE); + } + + // + // kmemesysSetupCoherentCpuLink should not be called from physical RM as + // it is intended to be called on kernel side to update + // KernelMemorySystem for C2C, NUMA functionality. + // + NV_ASSERT_OK_OR_GOTO(status, kmemsysSetupCoherentCpuLink(pGpu, pKernelMemorySystem, NV_FALSE), fail); + } + fail: if (status != NV_OK) { @@ -130,11 +182,63 @@ kmemsysProgramSysmemFlushBuffer_HAL(pGpu, pKernelMemorySystem); kmemsysAssertSysmemFlushBufferValid_HAL(pGpu, pKernelMemorySystem); + // Self Hosted GPUs should have its memory onlined by now. + if (gpuIsSelfHosted(pGpu) && + pGpu->getProperty(pGpu, PDB_PROP_GPU_COHERENT_CPU_MAPPING) && + osNumaOnliningEnabled(pGpu->pOsGpuInfo) && + !pKernelMemorySystem->bNumaNodesAdded) + { + // + // TODO: Bug 1945658: Deferred error checking from stateInit so that stateDestroy + // gets called. Refer kmemsysNumaAddMemory_HAL call site for further + // details. + // + return NV_ERR_INVALID_STATE; + } + + return NV_OK; +} + +NV_STATUS +kmemsysStatePostLoad_IMPL +( + OBJGPU *pGpu, + KernelMemorySystem *pKernelMemorySystem, + NvU32 flags +) +{ + if (IS_SILICON(pGpu) && + pGpu->getProperty(pGpu, PDB_PROP_GPU_ATS_SUPPORTED)) + { + NV_STATUS status = kmemsysSetupAllAtsPeers_HAL(pGpu, pKernelMemorySystem); + if (status != NV_OK) + { + NV_PRINTF(LEVEL_ERROR, "ATS peer setup failed.\n"); + return status; + } + } + + return NV_OK; +} + +NV_STATUS +kmemsysStatePreUnload_IMPL +( + OBJGPU *pGpu, + KernelMemorySystem *pKernelMemorySystem, + NvU32 flags +) +{ + if (IS_SILICON(pGpu) && + pGpu->getProperty(pGpu, PDB_PROP_GPU_ATS_SUPPORTED)) + { + kmemsysRemoveAllAtsPeers_HAL(pGpu, pKernelMemorySystem); + } return NV_OK; } /* - * Release the state accumulated in StateInit. + * Release the state accumulated in StateInit. * @param[in] pGpu pointer to the GPU instance. * @param[in] pKernelMemorySystem pointer to the kernel side KernelMemorySystem instance. */ @@ -145,6 +249,15 @@ ) { + // Teardown of Coherent Cpu Link is not required on Physical RM + KernelBif *pKernelBif = GPU_GET_KERNEL_BIF(pGpu); + + if (pKernelBif && pKernelBif->getProperty(pKernelBif, PDB_PROP_KBIF_IS_C2C_LINK_UP) && + pGpu->getProperty(pGpu, PDB_PROP_GPU_COHERENT_CPU_MAPPING)) + { + kmemsysTeardownCoherentCpuLink(pGpu, GPU_GET_KERNEL_MEMORY_SYSTEM(pGpu), NV_FALSE); + } + portMemFree((void *)pKernelMemorySystem->pStaticConfig); } @@ -171,6 +284,27 @@ KernelMemorySystem *pKernelMemorySystem ) { + OBJGPU *pGpu = ENG_GET_GPU(pKernelMemorySystem); + + // + // kmemsysNumaRemoveAllMemory_HAL() is called here in Destruct instead of + // Destroy to guarantee that NUMA memory is removed. This goes against + // Init/Destroy symmetry, but it is necessary because kmemsysStateDestroy + // may not be called for all cases when kmemsysStateInit was called + // (e.g., when kmemsys or another engine afterwards fails Init). + // + // If NUMA memory is not removed, then all subsequent attempts to add NUMA + // memory will fail, which will cause failures in future RM init attempts. + // + if (pKernelMemorySystem->memPartitionNumaInfo != NULL) + { + if (pKernelMemorySystem->bNumaNodesAdded == NV_TRUE) + { + kmemsysNumaRemoveAllMemory_HAL(pGpu, pKernelMemorySystem); + } + portMemFree(pKernelMemorySystem->memPartitionNumaInfo); + } + pKernelMemorySystem->sysmemFlushBuffer = 0; memdescFree(pKernelMemorySystem->pSysmemFlushBufferMemDesc); memdescDestroy(pKernelMemorySystem->pSysmemFlushBufferMemDesc); @@ -235,9 +369,9 @@ * @param[in] pGpu pointer to the GPU instance. * @param[in] pKernelMemorySystem pointer to the kernel side KernelMemorySystem instance. * @param[out] pConfig pointer to the static config init on Physical driver. - * + * * @return NV_OK upon success. - * NV_ERR* otherwise. + * NV_ERR* otherwise. */ NV_STATUS kmemsysInitStaticConfig_KERNEL @@ -397,6 +531,7 @@ NvU64 vmmuSegmentSize; NvU64 startAddr; NvU64 endAddr; + NvU64 partitionSize; NV_ASSERT_OR_RETURN(pAddrRange != NULL, NV_ERR_INVALID_ARGUMENT); *pAddrRange = NV_RANGE_EMPTY; @@ -422,12 +557,75 @@ NV_ASSERT_OR_RETURN((vmmuSegmentSize != 0), NV_ERR_INVALID_STATE); startAddr = pKernelMemorySystem->gpuInstanceMemConfig[swizzId].startingVmmuSegment * vmmuSegmentSize; - endAddr = startAddr + (pKernelMemorySystem->gpuInstanceMemConfig[swizzId].memSizeInVmmuSegment * vmmuSegmentSize) - 1; + partitionSize = pKernelMemorySystem->gpuInstanceMemConfig[swizzId].memSizeInVmmuSegment * vmmuSegmentSize; + + if (osNumaOnliningEnabled(pGpu->pOsGpuInfo)) + { + NvU64 memblockSize; + NvU64 alignedStartAddr; + + NV_ASSERT_OK_OR_RETURN(osNumaMemblockSize(&memblockSize)); + + // + // Align the partition start address and size to memblock size + // Some FB memory is wasted here if it is not already aligned. + // + alignedStartAddr = NV_ALIGN_UP64(startAddr, memblockSize); + + if(pKernelMemorySystem->bNumaMigPartitionSizeEnumerated) + { + partitionSize = pKernelMemorySystem->numaMigPartitionSize[swizzId]; + } + else + { + partitionSize -= (alignedStartAddr - startAddr); + } + + partitionSize = NV_ALIGN_DOWN64(partitionSize, memblockSize); + startAddr = alignedStartAddr; + } + + endAddr = startAddr + partitionSize - 1; + *pAddrRange = rangeMake(startAddr, endAddr); return NV_OK; } +/** + * @brief Modifies numaMigPartitionSize array such that memory size of + all the mig partitions with swizzId between startSwizzId and + endSwizzId is assigned the minimum value among all partition's + memory size. + * + * @param[IN] pKernelMemorySystem + * @param[IN] startSwizzId + * @param[IN] endSwizzId + * + */ +static void +_kmemsysSetNumaMigPartitionSizeSubArrayToMinimumValue +( + KernelMemorySystem *pKernelMemorySystem, + NvU64 startSwizzId, + NvU64 endSwizzId +) +{ + NvU64 minPartitionSize = pKernelMemorySystem->numaMigPartitionSize[startSwizzId]; + NvU64 index; + + for (index = startSwizzId; index <= endSwizzId; index++) + { + if(pKernelMemorySystem->numaMigPartitionSize[index] < minPartitionSize) + minPartitionSize = pKernelMemorySystem->numaMigPartitionSize[index]; + } + + for (index = startSwizzId; index <= endSwizzId; index++) + { + pKernelMemorySystem->numaMigPartitionSize[index] = minPartitionSize; + } +} + /*! * @brief Function to populate static GPU instance memory config which will be * utilized for GPU instance memory query and memory allocation @@ -481,6 +679,30 @@ kmemsysSwizzIdToVmmuSegmentsRange_HAL(pGpu, pKernelMemorySystem, swizzId, vmmuSegmentSize, totalVmmuSegments)); } + if (osNumaOnliningEnabled(pGpu->pOsGpuInfo)) + { + NV_RANGE addrRange = NV_RANGE_EMPTY; + NvU32 memSize; + + for(swizzId = 0; swizzId < KMIGMGR_MAX_GPU_SWIZZID; swizzId++) + { + kmemsysGetMIGGPUInstanceMemInfo(pGpu, pKernelMemorySystem, swizzId, &addrRange); + pKernelMemorySystem->numaMigPartitionSize[swizzId] = addrRange.hi - addrRange.lo + 1; + } + + // + // In GH180 for all the swizzId's for a given memory profile (FULL, HALF, QUARTER + // and EIGHTH partitions) might not be same. Modify numaMigPartitionSize array + // for the partition size to be constant for a given profile. BUG 4284299. + // + for (memSize = NV2080_CTRL_GPU_PARTITION_FLAG_MEMORY_SIZE_FULL; memSize < NV2080_CTRL_GPU_PARTITION_FLAG_MEMORY_SIZE__SIZE; memSize++) + { + NV_RANGE swizzRange = kmigmgrMemSizeFlagToSwizzIdRange(pGpu, pKernelMIGManager, + DRF_NUM(2080_CTRL_GPU, _PARTITION_FLAG, _MEMORY_SIZE, memSize)); + _kmemsysSetNumaMigPartitionSizeSubArrayToMinimumValue(pKernelMemorySystem, swizzRange.lo, swizzRange.hi); + } + pKernelMemorySystem->bNumaMigPartitionSizeEnumerated = NV_TRUE; + } return NV_OK; } @@ -579,38 +801,59 @@ { KernelBus *pKernelBus = GPU_GET_KERNEL_BUS(pGpu); MemoryManager *pMemoryManager = GPU_GET_MEMORY_MANAGER(pGpu); - NvU64 memblockSize = 0; - NvU64 numaOnlineBase = 0; NvU64 numaOnlineSize = 0; + NvU64 fbSize = (pMemoryManager->Ram.fbTotalMemSizeMb << 20); NvU32 data32; NvBool bCpuMapping = NV_TRUE; // Default enable + NvS32 numaNodeId = NV0000_CTRL_NO_NUMA_NODE; + NvU64 memblockSize = 0; + NvU64 numaOnlineBase = 0; + NvU64 rsvdFastSize = 0; + NvU64 rsvdSlowSize = 0; + NvU64 rsvdISOSize = 0; + NvU64 totalRsvdBytes = 0; { NV_ASSERT_OK_OR_RETURN(kmemsysGetFbNumaInfo_HAL(pGpu, pKernelMemorySystem, &pKernelMemorySystem->coherentCpuFbBase, - &pGpu->numaNodeId)); + &numaNodeId)); if (pKernelMemorySystem->coherentCpuFbBase != 0) { - RM_API *pRmApi = GPU_GET_PHYSICAL_RMAPI(pGpu); - NV2080_CTRL_INTERNAL_GET_COHERENT_FB_APERTURE_SIZE_PARAMS params = {0}; - - NV_ASSERT_OK_OR_RETURN(pRmApi->Control(pRmApi, - pGpu->hInternalClient, - pGpu->hInternalSubdevice, - NV2080_CTRL_CMD_INTERNAL_GET_COHERENT_FB_APERTURE_SIZE, - ¶ms, - sizeof(NV2080_CTRL_INTERNAL_GET_COHERENT_FB_APERTURE_SIZE_PARAMS))); - pKernelMemorySystem->coherentCpuFbEnd = pKernelMemorySystem->coherentCpuFbBase + - params.coherentFbApertureSize; + if (gpuIsSelfHosted(pGpu)) + { + // + // For self-hosted, coherentCpuFbEnd is only till the FB size + // end and NOT till the FB AMAP end since self-hosted doesn't + // support indirect peer and requires GPU nvlink for peer. + // + pKernelMemorySystem->coherentCpuFbEnd = pKernelMemorySystem->coherentCpuFbBase + fbSize; + } + else + { + RM_API *pRmApi = GPU_GET_PHYSICAL_RMAPI(pGpu); + NV2080_CTRL_INTERNAL_GET_COHERENT_FB_APERTURE_SIZE_PARAMS params = {0}; + + NV_ASSERT_OK_OR_RETURN(pRmApi->Control(pRmApi, + pGpu->hInternalClient, + pGpu->hInternalSubdevice, + NV2080_CTRL_CMD_INTERNAL_GET_COHERENT_FB_APERTURE_SIZE, + ¶ms, + sizeof(NV2080_CTRL_INTERNAL_GET_COHERENT_FB_APERTURE_SIZE_PARAMS))); + // + // Indirect peer(uses P9 to reach other GV100) in P9+GV100 requires coherentCpuFbEnd to + // also include the entire FB AMAP range even when FB size is less than the FB AMAP size. + // + pKernelMemorySystem->coherentCpuFbEnd = pKernelMemorySystem->coherentCpuFbBase + + params.coherentFbApertureSize; + } } } if ((osReadRegistryDword(pGpu, NV_REG_STR_OVERRIDE_GPU_NUMA_NODE_ID, &data32)) == NV_OK) { - pGpu->numaNodeId = (NvS32)data32; - NV_PRINTF(LEVEL_ERROR, "Override GPU NUMA node ID %d!\n", - pGpu->numaNodeId); + numaNodeId = (NvS32)data32; + NV_PRINTF(LEVEL_ERROR, "Override GPU NUMA node ID %d!\n", numaNodeId); } // Parse regkey here @@ -629,40 +872,59 @@ return NV_OK; } - NV_ASSERT_OK_OR_RETURN(kbusCreateCoherentCpuMapping_HAL(pGpu, pKernelBus, bFlush)); + NV_ASSERT_OK_OR_RETURN(osNumaMemblockSize(&memblockSize)); - // Switch the toggle for coherent link mapping only if migration is successful - pGpu->setProperty(pGpu, PDB_PROP_GPU_COHERENT_CPU_MAPPING, NV_TRUE); + memmgrCalcReservedFbSpaceHal_HAL(pGpu, pMemoryManager, &rsvdFastSize, &rsvdSlowSize, &rsvdISOSize); // - // TODO clean up with bug 2020982 - // RM: Encapsulate NUMA-specific kernel code and logic in a new object + // Calculate the size of the memory which can be safely onlined to the + // kernel after accounting for different reserved memory requirements. // - if (osNumaMemblockSize(&memblockSize) == NV_OK) - { - NvU64 rsvdFastSize = 0; - NvU64 rsvdSlowSize = 0; - NvU64 rsvdISOSize = 0; - NvU64 totalResvBytes = 0; - - memmgrCalcReservedFbSpaceHal_HAL(pGpu, pMemoryManager, &rsvdFastSize, &rsvdSlowSize, &rsvdISOSize); - totalResvBytes = (rsvdFastSize + rsvdSlowSize + rsvdISOSize); - totalResvBytes += memmgrGetRsvdMemorySize(pMemoryManager); + // Align rsvd memory to 64K granularity. + // TODO : rsvdMemorySize is not finalized at this point of time in + // GH180, currently rsvdMemorySize is not increasing after this + // point. This needs to be fixed. + // + totalRsvdBytes += NV_ALIGN_UP(pMemoryManager->rsvdMemorySize, 0x10000); + totalRsvdBytes += (rsvdFastSize + rsvdSlowSize + rsvdISOSize); + totalRsvdBytes += pMemoryManager->Ram.reservedMemSize; - // - // Online all of FB memory less reserved memory, aligned to memblock - // - // TODO: make sure the onlineable memory is aligned to memblockSize - // Currently, if we have leftover memory, it'll just be wasted because no - // one can access it - // - numaOnlineSize = NV_ALIGN_DOWN(pMemoryManager->Ram.fbUsableMemSize - totalResvBytes, memblockSize); - NV_PRINTF(LEVEL_INFO, "NUMA reserved memory size: 0x%llx online memory size: 0x%llx\n", - totalResvBytes, numaOnlineSize); + // + // TODO: make sure the onlineable memory is aligned to memblockSize + // Currently, if we have leftover memory, it'll just be wasted because no + // one can access it. If FB size itself is memblock size unaligned(because + // of CBC and row remapper deductions), then the memory wastage is unavoidable. + // + numaOnlineSize = NV_ALIGN_DOWN64(fbSize - totalRsvdBytes, memblockSize); - pKernelMemorySystem->numaOnlineBase = numaOnlineBase; - pKernelMemorySystem->numaOnlineSize = numaOnlineSize; - } + pKernelMemorySystem->numaOnlineBase = numaOnlineBase; + pKernelMemorySystem->numaOnlineSize = numaOnlineSize; + + NV_PRINTF(LEVEL_INFO, "fbSize: 0x%llx NUMA reserved memory size: 0x%llx online memory size: 0x%llx\n", + fbSize, totalRsvdBytes, numaOnlineSize); + // + // TODO: Bug 1945658: Soldier through on GPU memory add + // failure(which is often possible because of missing auto online + // setting) and instead check for failure on stateLoad. + // Any failure in StateInit results in gpuStateDestroy not getting called. + // kgspUnloadRm_IMPL from gpuStateDestroy also doesn't get called leaving + // GSP in unclean state and requiring GPU reset to recover from that. + // + // kmemsysNumaAddMemory_HAL by itself cannot be called from stateLoad + // because the memory mapping that follows this call site comes from linear + // kernel virtual address when memory is added to the kernel vs the + // VMALLOC_START region when memory is not added. + // + NV_ASSERT_OK(kmemsysNumaAddMemory_HAL(pGpu, pKernelMemorySystem, 0, 0, + numaOnlineSize, &numaNodeId)); + pGpu->numaNodeId = numaNodeId; + + NV_ASSERT_OK_OR_RETURN(kbusCreateCoherentCpuMapping_HAL(pGpu, pKernelBus, numaOnlineSize, bFlush)); + + // Switch the toggle for coherent link mapping only if migration is successful + pGpu->setProperty(pGpu, PDB_PROP_GPU_COHERENT_CPU_MAPPING, NV_TRUE); + + NV_ASSERT_OK_OR_RETURN(kbusVerifyCoherentLink_HAL(pGpu, pKernelBus)); return NV_OK; } @@ -728,3 +990,4 @@ { return kmemsysReadUsableFbSize_HAL(pGpu, pKernelMemorySystem, pFbSize); } + diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/kernel/gpu/mem_sys/kern_mem_sys_ctrl.c nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/kernel/gpu/mem_sys/kern_mem_sys_ctrl.c --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/kernel/gpu/mem_sys/kern_mem_sys_ctrl.c 2023-10-25 20:21:14.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/kernel/gpu/mem_sys/kern_mem_sys_ctrl.c 2024-03-05 22:13:39.000000000 +0000 @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 1993-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 1993-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -41,7 +41,7 @@ static NV_STATUS -_fbGetFbInfos(OBJGPU *pGpu, NvHandle hClient, NvHandle hObject, NV2080_CTRL_FB_INFO *pFbInfos, NvU32 fbInfoListSize) +_fbGetFbInfos(OBJGPU *pGpu, RsClient *pClient, Device *pDevice, NvHandle hObject, NV2080_CTRL_FB_INFO *pFbInfos, NvU32 fbInfoListSize) { KernelMemorySystem *pKernelMemorySystem = GPU_GET_KERNEL_MEMORY_SYSTEM(pGpu); MemoryManager *pMemoryManager = GPU_GET_MEMORY_MANAGER(pGpu); @@ -70,8 +70,8 @@ if (bIsMIGInUse) { - bIsClientMIGMonitor = !RMCFG_FEATURE_PLATFORM_GSP && rmclientIsCapableByHandle(hClient, NV_RM_CAP_SYS_SMC_MONITOR); - bIsClientMIGProfiler = kmigmgrIsClientUsingDeviceProfiling(pGpu, pKernelMIGManager, hClient); + bIsClientMIGMonitor = !RMCFG_FEATURE_PLATFORM_GSP && rmclientIsCapableByHandle(pClient->hClient, NV_RM_CAP_SYS_SMC_MONITOR); + bIsClientMIGProfiler = kmigmgrIsClientUsingDeviceProfiling(pGpu, pKernelMIGManager, pClient->hClient); } // @@ -147,8 +147,8 @@ !bIsClientMIGProfiler && !bIsClientMIGMonitor) { MIG_INSTANCE_REF ref; - status = kmigmgrGetInstanceRefFromClient(pGpu, pKernelMIGManager, - hClient, &ref); + status = kmigmgrGetInstanceRefFromDevice(pGpu, pKernelMIGManager, + pDevice, &ref); if ((status != NV_OK) && !kmigmgrIsMIGReferenceValid(&ref)) { @@ -169,8 +169,8 @@ if (bIsMIGInUse && !bIsClientMIGProfiler && !bIsClientMIGMonitor) { - NV_CHECK_OR_RETURN(LEVEL_INFO, (kmigmgrGetMemoryPartitionHeapFromClient(pGpu, - pKernelMIGManager, hClient, &pMemoryPartitionHeap) == NV_OK), + NV_CHECK_OR_RETURN(LEVEL_INFO, (kmigmgrGetMemoryPartitionHeapFromDevice(pGpu, + pKernelMIGManager, pDevice, &pMemoryPartitionHeap) == NV_OK), NV_ERR_INSUFFICIENT_PERMISSIONS); // @@ -203,7 +203,7 @@ pParams->fbInfoListSize = physIdx; NV_CHECK_OK_OR_ELSE(status, LEVEL_ERROR, - pRmApi->Control(pRmApi, hClient, hObject, + pRmApi->Control(pRmApi, pClient->hClient, hObject, NV2080_CTRL_CMD_FB_GET_INFO_V2, pParams, sizeof(*pParams)), portMemFree(pParams); @@ -243,7 +243,7 @@ case NV2080_CTRL_FB_INFO_INDEX_BAR1_SIZE: { GETBAR1INFO bar1Info = {0}; - status = memmgrGetBAR1InfoForClient_HAL(pGpu, pMemoryManager, hClient, &bar1Info); + status = memmgrGetBAR1InfoForDevice(pGpu, pMemoryManager, pDevice, &bar1Info); if (status != NV_OK) data = 0; else @@ -254,7 +254,7 @@ case NV2080_CTRL_FB_INFO_INDEX_BAR1_AVAIL_SIZE: { GETBAR1INFO bar1Info = {0}; - status = memmgrGetBAR1InfoForClient_HAL(pGpu, pMemoryManager, hClient, &bar1Info); + status = memmgrGetBAR1InfoForDevice(pGpu, pMemoryManager, pDevice, &bar1Info); if (status != NV_OK) data = 0; else @@ -265,7 +265,7 @@ case NV2080_CTRL_FB_INFO_INDEX_BAR1_MAX_CONTIGUOUS_AVAIL_SIZE: { GETBAR1INFO bar1Info = {0}; - status = memmgrGetBAR1InfoForClient_HAL(pGpu, pMemoryManager, hClient, &bar1Info); + status = memmgrGetBAR1InfoForDevice(pGpu, pMemoryManager, pDevice, &bar1Info); if (status != NV_OK) data = 0; else @@ -276,7 +276,7 @@ case NV2080_CTRL_FB_INFO_INDEX_BANK_SWIZZLE_ALIGNMENT: { GETBAR1INFO bar1Info = {0}; - status = memmgrGetBAR1InfoForClient_HAL(pGpu, pMemoryManager, hClient, &bar1Info); + status = memmgrGetBAR1InfoForDevice(pGpu, pMemoryManager, pDevice, &bar1Info); if (status != NV_OK) data = 0; else @@ -308,13 +308,19 @@ } else { + const MEMORY_SYSTEM_STATIC_CONFIG *pMemsysConfig = + kmemsysGetStaticConfig(pGpu, pKernelMemorySystem); NV_ASSERT(0 == NvU64_HI32(pMemoryManager->Ram.fbTotalMemSizeMb << 10)); - data = NvU64_LO32(NV_MIN((pMemoryManager->Ram.fbTotalMemSizeMb << 10), (pMemoryManager->Ram.fbOverrideSizeMb << 10))); + data = NvU64_LO32(NV_MIN((pMemoryManager->Ram.fbTotalMemSizeMb << 10), + (pMemoryManager->Ram.fbOverrideSizeMb << 10)) + - pMemsysConfig->fbOverrideStartKb); break; } } case NV2080_CTRL_FB_INFO_INDEX_RAM_SIZE: { + const MEMORY_SYSTEM_STATIC_CONFIG *pMemsysConfig = + kmemsysGetStaticConfig(pGpu, pKernelMemorySystem); if (pMemoryPartitionHeap != NULL) { NvU32 heapSizeKb; @@ -336,11 +342,15 @@ break; } NV_ASSERT(0 == NvU64_HI32(pMemoryManager->Ram.fbTotalMemSizeMb << 10)); - data = NvU64_LO32(NV_MIN((pMemoryManager->Ram.fbTotalMemSizeMb << 10), (pMemoryManager->Ram.fbOverrideSizeMb << 10))); + data = NvU64_LO32(NV_MIN((pMemoryManager->Ram.fbTotalMemSizeMb << 10), + (pMemoryManager->Ram.fbOverrideSizeMb << 10)) + - pMemsysConfig->fbOverrideStartKb); break; } case NV2080_CTRL_FB_INFO_INDEX_USABLE_RAM_SIZE: { + const MEMORY_SYSTEM_STATIC_CONFIG *pMemsysConfig = + kmemsysGetStaticConfig(pGpu, pKernelMemorySystem); if (pMemoryPartitionHeap != NULL) { NvU32 heapSizeKb; @@ -362,11 +372,15 @@ break; } NV_ASSERT(0 == NvU64_HI32(pMemoryManager->Ram.fbUsableMemSize >> 10)); - data = NvU64_LO32(NV_MIN((pMemoryManager->Ram.fbUsableMemSize >> 10), (pMemoryManager->Ram.fbOverrideSizeMb << 10))); + data = NvU64_LO32(NV_MIN((pMemoryManager->Ram.fbUsableMemSize >> 10 ), + (pMemoryManager->Ram.fbOverrideSizeMb << 10)) + - pMemsysConfig->fbOverrideStartKb); break; } case NV2080_CTRL_FB_INFO_INDEX_HEAP_SIZE: { + const MEMORY_SYSTEM_STATIC_CONFIG *pMemsysConfig = + kmemsysGetStaticConfig(pGpu, pKernelMemorySystem); if (bIsPmaEnabled) { pmaGetTotalMemory(&pHeap->pmaObject, &bytesTotal); @@ -381,6 +395,7 @@ NV_ASSERT(NvU64_HI32(size >> 10) == 0); data = NvU64_LO32(size >> 10); } + data -= pMemsysConfig->fbOverrideStartKb; break; } case NV2080_CTRL_FB_INFO_INDEX_HEAP_START: @@ -400,13 +415,33 @@ } else { - // - // Returns start of heap in kbytes. This is zero unless - // VGA display memory is reserved. - // - heapGetBase(pHeap, &heapBase); - data = NvU64_LO32(heapBase >> 10); - NV_ASSERT(((NvU64) data << 10ULL) == heapBase); + status = memmgrCalculateHeapOffsetWithGSP_HAL(pGpu, pMemoryManager, &data); + if (status == NV_ERR_NOT_SUPPORTED) + { + // If GSP is not in use, if neither Console nor CBC + // region are present, or if this calculation is done + // in hardware, then heapGetBase() will give the correct + // value and it just needs to be converted to kbytes. + // It will be zero unless VGA display memory is reserved + const MEMORY_SYSTEM_STATIC_CONFIG *pMemsysConfig = + kmemsysGetStaticConfig(pGpu, pKernelMemorySystem); + if (pMemsysConfig->fbOverrideStartKb != 0) + { + data = NvU64_LO32(pMemsysConfig->fbOverrideStartKb); + NV_ASSERT(((NvU64) data << 10ULL) == pMemsysConfig->fbOverrideStartKb); + } + else + { + // + // Returns start of heap in kbytes. This is zero unless + // VGA display memory is reserved. + // + status = heapGetBase(pHeap, &heapBase); + data = NvU64_LO32(heapBase >> 10); + NV_ASSERT_OR_ELSE(((NvU64) data << 10ULL) == heapBase, + status = NV_ERR_INVALID_DATA); + } + } } break; } @@ -416,6 +451,13 @@ { bytesFree = 0; + if (bIsPmaEnabled) + pmaGetFreeMemory(&pHeap->pmaObject, &val); + else + heapGetFree(pHeap, &val); + + bytesFree = val; + // // Add free memory across the all valid MIG GPU instances and // the global heap. @@ -425,17 +467,34 @@ // if (kmigmgrIsMIGMemPartitioningEnabled(pGpu, pKernelMIGManager)) { - memmgrGetFreeMemoryForAllMIGGPUInstances(pGpu, pMemoryManager, &val); - bytesFree = val; + NvU64 partTotalBytesFree = 0; + NvU64 partTotalBytes = 0; + NvU32 config = PMA_QUERY_NUMA_ENABLED; + + memmgrGetFreeMemoryForAllMIGGPUInstances(pGpu, pMemoryManager, &partTotalBytesFree); + + // + // In the case of MIG+NUMA case(self hosted GPUs), NVOS32_ALLOC_FLAGS_FIXED_ADDRESS_ALLOCATE + // is not supported and hence the partition's memory is not accounted in the global PMA. + // This resulted in more free memory than the total memory resulting in the + // used memory(calculated as total - free) showing very large value. + // Now calculating the global free memory in the NUMA case as: + // partitions' free memory + (global total memory - all created partitions' total memory). + // + if (bIsPmaEnabled && + (pmaQueryConfigs(&pHeap->pmaObject, &config) == NV_OK) && + (config & PMA_QUERY_NUMA_ENABLED)) + { + memmgrGetTotalMemoryForAllMIGGPUInstances(pGpu, pMemoryManager, &partTotalBytes); + pmaGetTotalMemory(&pHeap->pmaObject, &val); + bytesFree = partTotalBytesFree + (val - partTotalBytes); + } + else + { + bytesFree += partTotalBytesFree; + } } - if (bIsPmaEnabled) - pmaGetFreeMemory(&pHeap->pmaObject, &val); - else - heapGetFree(pHeap, &val); - - bytesFree += val; - NV_ASSERT(NvU64_HI32(bytesFree >> 10) == 0); data = NvU64_LO32(bytesFree >> 10); } @@ -487,6 +546,8 @@ case NV2080_CTRL_FB_INFO_INDEX_MAPPABLE_HEAP_SIZE: { + const MEMORY_SYSTEM_STATIC_CONFIG *pMemsysConfig = + kmemsysGetStaticConfig(pGpu, pKernelMemorySystem); if (bIsPmaEnabled) { NvU32 heapSizeKb; @@ -512,6 +573,7 @@ if (data > heapSizeKb) data = heapSizeKb; } + data -= pMemsysConfig->fbOverrideStartKb; break; } case NV2080_CTRL_FB_INFO_INDEX_BANK_COUNT: @@ -669,6 +731,60 @@ kbusGetP2PMailboxAttributes_HAL(pGpu, pKernelBus, NULL, NULL, &data); break; } + case NV2080_CTRL_FB_INFO_INDEX_PROTECTED_MEM_SIZE_TOTAL_KB: + { + if (gpuIsCCorApmFeatureEnabled(pGpu)) + { + if (bIsPmaEnabled) + { + pmaGetTotalProtectedMemory(&pHeap->pmaObject, &bytesTotal); + NV_ASSERT(NvU64_HI32(bytesTotal >> 10) == 0); + data = NvU64_LO32(bytesTotal >> 10); + } + else + { + // + // We should never reach here given that PMA is enabled + // on all platforms where confidential compute is supported + // + NV_ASSERT(0); + data = 0; + status = NV_ERR_INVALID_ARGUMENT; + } + } + else + { + data = 0; + } + break; + } + case NV2080_CTRL_FB_INFO_INDEX_PROTECTED_MEM_SIZE_FREE_KB: + { + if (gpuIsCCorApmFeatureEnabled(pGpu)) + { + if (bIsPmaEnabled) + { + pmaGetFreeProtectedMemory(&pHeap->pmaObject, &bytesFree); + NV_ASSERT(NvU64_HI32(bytesFree >> 10) == 0); + data = NvU64_LO32(bytesFree >> 10); + } + else + { + // + // We should never reach here given that PMA is enabled + // on all platforms where confidential compute is supported + // + NV_ASSERT(0); + data = 0; + status = NV_ERR_INVALID_ARGUMENT; + } + } + else + { + data = 0; + } + break; + } default: { data = 0; @@ -700,8 +816,9 @@ ) { OBJGPU *pGpu = GPU_RES_GET_GPU(pSubdevice); - NvHandle hClient = RES_GET_CLIENT_HANDLE(pSubdevice); + RsClient *pClient = RES_GET_CLIENT(pSubdevice); NvHandle hObject = RES_GET_HANDLE(pSubdevice); + Device *pDevice = GPU_RES_GET_DEVICE(pSubdevice); LOCK_ASSERT_AND_RETURN(rmapiLockIsOwner() && rmDeviceGpuLockIsOwner(pGpu->gpuInstance)); @@ -711,7 +828,7 @@ return NV_ERR_INVALID_ARGUMENT; } - return _fbGetFbInfos(pGpu, hClient, hObject, NvP64_VALUE(pFbInfoParams->fbInfoList), pFbInfoParams->fbInfoListSize); + return _fbGetFbInfos(pGpu, pClient, pDevice, hObject, NvP64_VALUE(pFbInfoParams->fbInfoList), pFbInfoParams->fbInfoListSize); } // @@ -728,8 +845,9 @@ ) { OBJGPU *pGpu = GPU_RES_GET_GPU(pSubdevice); - NvHandle hClient = RES_GET_CLIENT_HANDLE(pSubdevice); + RsClient *pClient = RES_GET_CLIENT(pSubdevice); NvHandle hObject = RES_GET_HANDLE(pSubdevice); + Device *pDevice = GPU_RES_GET_DEVICE(pSubdevice); LOCK_ASSERT_AND_RETURN(rmapiLockIsOwner() && rmDeviceGpuLockIsOwner(pGpu->gpuInstance)); @@ -739,7 +857,7 @@ return NV_ERR_INVALID_ARGUMENT; } - return _fbGetFbInfos(pGpu, hClient, hObject, pFbInfoParams->fbInfoList, pFbInfoParams->fbInfoListSize); + return _fbGetFbInfos(pGpu, pClient, pDevice, hObject, pFbInfoParams->fbInfoList, pFbInfoParams->fbInfoListSize); } // @@ -876,7 +994,7 @@ NvU32 osBlackListCount = 0; NvU32 chunk; NvU64 chunks[NV2080_CTRL_FB_OFFLINED_PAGES_MAX_PAGES]; - NvU32 pageSize; + NvU64 pageSize; NvU32 numChunks = 0; LOCK_ASSERT_AND_RETURN(rmapiLockIsOwner() && rmGpuLockIsOwner()); @@ -894,7 +1012,7 @@ pOsOfflinedParams->offlinedPages[chunk] = (NvU32)(chunks[chunk] >> RM_PAGE_SHIFT); } pOsOfflinedParams->validEntries = numChunks; - pOsOfflinedParams->pageSize = pageSize; + pOsOfflinedParams->pageSize = (NvU32)pageSize; } else { @@ -989,6 +1107,8 @@ NvU32 idx; NV_STATUS status; NvU32 count; + NvU64 numaMemOffset = 0; + NvU64 numaMemSize = 0; const MEMORY_SYSTEM_STATIC_CONFIG *pMemorySystemConfig = kmemsysGetStaticConfig(pGpu, pKernelMemorySystem); @@ -1000,9 +1120,37 @@ return NV_ERR_INVALID_ARGUMENT; } - pParams->numaNodeId = pGpu->numaNodeId; - pParams->numaMemAddr = pKernelMemorySystem->coherentCpuFbBase + pKernelMemorySystem->numaOnlineBase; - pParams->numaMemSize = pKernelMemorySystem->numaOnlineSize; + if (gpuIsSelfHosted(pGpu) && IS_MIG_IN_USE(pGpu)) + { + KernelMIGManager *pKernelMIGManager = GPU_GET_KERNEL_MIG_MANAGER(pGpu); + Device *pDevice = GPU_RES_GET_DEVICE(pSubdevice); + MIG_INSTANCE_REF ref; + NvU32 swizzId; + + pParams->numaNodeId = NV0000_CTRL_NO_NUMA_NODE; + + if (kmigmgrGetInstanceRefFromDevice(pGpu, pKernelMIGManager, pDevice, &ref) == NV_OK) + { + swizzId = ref.pKernelMIGGpuInstance->swizzId; + + if (pKernelMemorySystem->memPartitionNumaInfo[swizzId].bInUse) + { + pParams->numaNodeId = pKernelMemorySystem->memPartitionNumaInfo[swizzId].numaNodeId; + pParams->numaMemAddr = pKernelMemorySystem->coherentCpuFbBase + pKernelMemorySystem->memPartitionNumaInfo[swizzId].offset; + pParams->numaMemSize = pKernelMemorySystem->memPartitionNumaInfo[swizzId].size; + numaMemOffset = pKernelMemorySystem->memPartitionNumaInfo[swizzId].offset; + numaMemSize = pKernelMemorySystem->memPartitionNumaInfo[swizzId].size; + } + } + } + else + { + pParams->numaNodeId = pGpu->numaNodeId; + pParams->numaMemAddr = pKernelMemorySystem->coherentCpuFbBase + pKernelMemorySystem->numaOnlineBase; + pParams->numaMemSize = pKernelMemorySystem->numaOnlineSize; + numaMemOffset = pKernelMemorySystem->numaOnlineBase; + numaMemSize = pKernelMemorySystem->numaOnlineSize; + } if (pParams->numaOfflineAddressesCount == 0) { @@ -1039,9 +1187,9 @@ } // Only tell the caller about Offline pages in the NUMA region. - if (offset < pParams->numaMemSize) + if ((offset >= numaMemOffset) && (offset < (numaMemOffset + numaMemSize))) { - pParams->numaOfflineAddresses[numaOfflineIdx++] = pParams->numaMemAddr + offset; + pParams->numaOfflineAddresses[numaOfflineIdx++] = pKernelMemorySystem->coherentCpuFbBase + offset; } else { @@ -1070,9 +1218,10 @@ NV2080_CTRL_INTERNAL_MEMSYS_SET_ZBC_REFERENCED_PARAMS *pParams ) { - OBJGPU *pGpu = GPU_RES_GET_GPU(pSubdevice); - CALL_CONTEXT *pCallContext = resservGetTlsCallContext(); + OBJGPU *pGpu = GPU_RES_GET_GPU(pSubdevice); + CALL_CONTEXT *pCallContext = resservGetTlsCallContext(); NvU32 gfid; + NV_STATUS status = NV_OK; NV_ASSERT_OK_OR_RETURN(vgpuGetCallingContextGfid(pGpu, &gfid)); @@ -1081,7 +1230,6 @@ if (IS_VIRTUAL(pGpu) || IS_GSP_CLIENT(pGpu)) { RmCtrlParams *pRmCtrlParams = pCallContext->pControlParams; - NV_STATUS status = NV_OK; NV_RM_RPC_CONTROL(pGpu, pRmCtrlParams->hClient, @@ -1094,7 +1242,7 @@ return status; } - return NV_OK; + return status; } /*! @@ -1228,7 +1376,7 @@ _YES, pCacheFlushParams->flags)) { NV_CHECK_OK_OR_CAPTURE_FIRST_ERROR(status, LEVEL_ERROR, - kbusFlush_HAL(pGpu, pKernelBus, BUS_FLUSH_VIDEO_MEMORY)); + kbusSendSysmembar(pGpu, pKernelBus)); } return status; diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/kernel/gpu/mig_mgr/arch/ampere/kmigmgr_ga100.c nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/kernel/gpu/mig_mgr/arch/ampere/kmigmgr_ga100.c --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/kernel/gpu/mig_mgr/arch/ampere/kmigmgr_ga100.c 2023-10-25 20:21:14.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/kernel/gpu/mig_mgr/arch/ampere/kmigmgr_ga100.c 2024-03-05 22:13:39.000000000 +0000 @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 2021-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2021-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -21,6 +21,8 @@ * DEALINGS IN THE SOFTWARE. */ +#define NVOC_KERNEL_MIG_MANAGER_H_PRIVATE_ACCESS_ALLOWED + #include "kernel/gpu/mem_mgr/mem_mgr.h" #include "kernel/gpu/mem_mgr/heap.h" #include "kernel/gpu/mig_mgr/kernel_mig_manager.h" @@ -112,16 +114,16 @@ // Make sure there are no channels alive on any of these engines if (kfifoEngineListHasChannel(pGpu, pKernelFifo, engines, engineCount)) return NV_ERR_STATE_IN_USE; - + // - // Check for any alive P2P references to this GPU. P2P objects must - // be re-created after disabling MIG. If it is allowed for MIG to - // continue enablement without all P2P objects torn down, there is + // Check for any alive P2P references to this GPU. P2P objects must + // be re-created after disabling MIG. If it is allowed for MIG to + // continue enablement without all P2P objects torn down, there is // the possibility that P2P mappings and state will never be updated. // if (bMemoryPartitioningNeeded || !kmigmgrIsMIGNvlinkP2PSupportOverridden(pGpu, pKernelMIGManager)) { - NV_CHECK_OR_RETURN(LEVEL_ERROR, + NV_CHECK_OR_RETURN(LEVEL_ERROR, !kbusIsGpuP2pAlive(pGpu, GPU_GET_KERNEL_BUS(pGpu)), NV_ERR_STATE_IN_USE); } diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/kernel/gpu/mig_mgr/arch/hopper/kmigmgr_gh100.c nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/kernel/gpu/mig_mgr/arch/hopper/kmigmgr_gh100.c --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/kernel/gpu/mig_mgr/arch/hopper/kmigmgr_gh100.c 2023-10-25 20:21:14.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/kernel/gpu/mig_mgr/arch/hopper/kmigmgr_gh100.c 2024-03-05 22:13:39.000000000 +0000 @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2022-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -21,6 +21,8 @@ * DEALINGS IN THE SOFTWARE. */ +#define NVOC_KERNEL_MIG_MANAGER_H_PRIVATE_ACCESS_ALLOWED + #include "kernel/gpu/mem_mgr/mem_mgr.h" #include "kernel/gpu/mem_mgr/heap.h" #include "kernel/gpu/mig_mgr/kernel_mig_manager.h" @@ -106,7 +108,7 @@ return NV_FALSE; } } - + switch (computeSizeFlag) { case NV2080_CTRL_GPU_PARTITION_FLAG_COMPUTE_SIZE_FULL: diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/kernel/gpu/mig_mgr/compute_instance_subscription.c nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/kernel/gpu/mig_mgr/compute_instance_subscription.c --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/kernel/gpu/mig_mgr/compute_instance_subscription.c 2023-10-25 20:21:14.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/kernel/gpu/mig_mgr/compute_instance_subscription.c 2024-03-05 22:13:40.000000000 +0000 @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 2019-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2019-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -28,6 +28,11 @@ * *****************************************************************************/ +#define NVOC_COMPUTE_INSTANCE_SUBSCRIPTION_H_PRIVATE_ACCESS_ALLOWED + +// FIXME XXX +#define NVOC_GPU_INSTANCE_SUBSCRIPTION_H_PRIVATE_ACCESS_ALLOWED + #include "core/core.h" #include "gpu/gpu.h" #include "core/system.h" @@ -124,7 +129,7 @@ ComputeInstanceSubscription *pComputeInstanceSubscriptionSrc = dynamicCast(pSrcRef->pResource, ComputeInstanceSubscription); OBJGPU *pGpu = GPU_RES_GET_GPU(pComputeInstanceSubscription); - // non kernel clients are not allowed to dup MIG instances + // non kernel clients are not allowed to dup MIG instances NV_CHECK_OR_RETURN(LEVEL_SILENT, pCallContext->secInfo.privLevel >= RS_PRIV_LEVEL_KERNEL, NV_ERR_NOT_SUPPORTED); diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/kernel/gpu/mig_mgr/gpu_instance_subscription.c nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/kernel/gpu/mig_mgr/gpu_instance_subscription.c --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/kernel/gpu/mig_mgr/gpu_instance_subscription.c 2023-10-25 20:21:14.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/kernel/gpu/mig_mgr/gpu_instance_subscription.c 2024-03-05 22:13:40.000000000 +0000 @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 2018-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2018-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -28,6 +28,12 @@ * *****************************************************************************/ +// FIXME XXX +#define NVOC_KERNEL_GRAPHICS_MANAGER_H_PRIVATE_ACCESS_ALLOWED +#define NVOC_COMPUTE_INSTANCE_SUBSCRIPTION_H_PRIVATE_ACCESS_ALLOWED + +#define NVOC_GPU_INSTANCE_SUBSCRIPTION_H_PRIVATE_ACCESS_ALLOWED + #include "core/core.h" #include "core/system.h" #include "gpu/gpu.h" @@ -126,6 +132,12 @@ } // + // Disable RMCTRL Cache before subscribe to GPU instance. + // RMCTRL-CACHE-TODO: remove the workaround when CORERM-5016 is done. + // + rmapiControlCacheSetMode(NV0000_CTRL_SYSTEM_RMCTRL_CACHE_MODE_CTRL_MODE_DISABLE); + + // // Root-SwizzID is a special swizzID which doesn't have any GPU instance // associated with it. It can be subscribed to even without GPU instances // @@ -643,6 +655,7 @@ ++pParams->execPartCount; pOutInfo->gpcCount = pMIGComputeInstance->resourceAllocation.gpcCount; + pOutInfo->gfxGpcCount = pMIGComputeInstance->resourceAllocation.gfxGpcCount; pOutInfo->veidCount = pMIGComputeInstance->resourceAllocation.veidCount; pOutInfo->ceCount = kmigmgrCountEnginesOfType(&pMIGComputeInstance->resourceAllocation.engines, RM_ENGINE_TYPE_COPY(0)); @@ -862,7 +875,8 @@ { KernelMIGManager *pKernelMIGManager = GPU_GET_KERNEL_MIG_MANAGER(pGpu); NV_CHECK_OK_OR_GOTO(status, LEVEL_ERROR, - kmigmgrCreateComputeInstances_HAL(pGpu, pKernelMIGManager, pGPUInstance, NV_FALSE, restore, &pParams->id, NV_FALSE), + kmigmgrCreateComputeInstances_HAL(pGpu, pKernelMIGManager, + pGPUInstance, NV_FALSE, restore, &pParams->id, pParams->bCreateCap), cleanup_rpc); } else diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/kernel/gpu/mig_mgr/kernel_mig_manager.c nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/kernel/gpu/mig_mgr/kernel_mig_manager.c --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/kernel/gpu/mig_mgr/kernel_mig_manager.c 2023-10-25 20:21:14.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/kernel/gpu/mig_mgr/kernel_mig_manager.c 2024-03-05 22:13:40.000000000 +0000 @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 2021-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2021-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -21,6 +21,14 @@ * DEALINGS IN THE SOFTWARE. */ +#define NVOC_KERNEL_MIG_MANAGER_H_PRIVATE_ACCESS_ALLOWED + +// FIXME XXX +#define NVOC_KERNEL_GRAPHICS_MANAGER_H_PRIVATE_ACCESS_ALLOWED +#define NVOC_GPU_INSTANCE_SUBSCRIPTION_H_PRIVATE_ACCESS_ALLOWED +#define NVOC_COMPUTE_INSTANCE_SUBSCRIPTION_H_PRIVATE_ACCESS_ALLOWED +#define NVOC_KERNEL_NVLINK_H_PRIVATE_ACCESS_ALLOWED + #include "kernel/gpu/mig_mgr/kernel_mig_manager.h" #include "kernel/gpu/gr/kernel_graphics.h" #include "kernel/gpu/rc/kernel_rc.h" @@ -41,6 +49,7 @@ #include "rmapi/rmapi_utils.h" #include "gpu/mem_mgr/mem_scrub.h" #include "vgpu/rpc.h" +#include "virtualization/kernel_vgpu_mgr.h" #include "kernel/gpu/gr/kernel_graphics_manager.h" #include "kernel/gpu/gr/kernel_graphics.h" #include "kernel/core/locks.h" @@ -332,13 +341,14 @@ * @brief Chooses the engines of the given type to allocate. Supports * shared/exclusive ownership arbitration. * - * @param[IN] pSourceEngines Mask of engines to allocate from - * @param[IN} bShared NV_TRUE if engines should be shared - * @param[IN] engTypeRange NV_RANGE of bit indices for this eng type - * @param[IN] regEngCount Requested number of engines in this exec part - * @param[I/O] pOutEngines Mask of engines already/newly allocated - * @param[I/O] pExclusiveEngines Mask of already exclusively-allocated engines - * @param[I/O] pSharedEngines Mask of engines shared by other instances + * @param[IN] pSourceEngines Mask of engines in an instance + * @param[IN} bShared NV_TRUE if engines should be shared + * @param[IN] engTypeRange NV_RANGE of bit indices for this eng type + * @param[IN] regEngCount Requested number of engines in this CI + * @param[I/O] pOutEngines Mask of engines already/newly allocated + * @param[I/O] pExclusiveEngines Mask of already exclusively-allocated engines + * @param[I/O] pSharedEngines Mask of engines shared by other instances + * @param[IN] pAllocatableEngines Mask of engines that are allocatable */ NV_STATUS kmigmgrAllocateInstanceEngines_IMPL @@ -349,7 +359,8 @@ NvU32 reqEngCount, ENGTYPE_BIT_VECTOR *pOutEngines, ENGTYPE_BIT_VECTOR *pExclusiveEngines, - ENGTYPE_BIT_VECTOR *pSharedEngines + ENGTYPE_BIT_VECTOR *pSharedEngines, + ENGTYPE_BIT_VECTOR *pAllocatableEngines ) { NvU32 allocated = 0; @@ -357,6 +368,11 @@ RM_ENGINE_TYPE rmEngineType; NvU32 localIdx; + // Ensure allocatableEngines is subset of sourceEngines + bitVectorClrAll(&engines); + bitVectorAnd(&engines, pAllocatableEngines, pSourceEngines); + NV_ASSERT_OR_RETURN(bitVectorTestEqual(&engines, pAllocatableEngines), NV_ERR_INVALID_STATE); + // If using shared engines, allocate as many from existing shared engines as possible if (bShared) { @@ -369,8 +385,9 @@ if (allocated == reqEngCount) break; - // Skip engines that aren't in the shared pool already - if (!bitVectorTest(pSharedEngines, rmEngineType)) + // Skip engines that aren't allocatable or aren't in the shared pool already + if (!bitVectorTest(pAllocatableEngines, rmEngineType) || + !bitVectorTest(pSharedEngines, rmEngineType)) { localIdx++; continue; @@ -395,8 +412,9 @@ if (allocated == reqEngCount) break; - // Skip in-use engines - if (bitVectorTest(pSharedEngines, rmEngineType) || + // Skip non-allocatable or in-use engines + if (!bitVectorTest(pAllocatableEngines, rmEngineType) || + bitVectorTest(pSharedEngines, rmEngineType) || bitVectorTest(pExclusiveEngines, rmEngineType)) { localIdx++; @@ -499,7 +517,7 @@ portMemSet(¶ms, 0, sizeof(params)); params.swizzId = swizzId; NV_ASSERT_OK_OR_RETURN( - pRmApi->Alloc(pRmApi, hClient, hSubdevice, &hSubscription, AMPERE_SMC_PARTITION_REF, ¶ms)); + pRmApi->Alloc(pRmApi, hClient, hSubdevice, &hSubscription, AMPERE_SMC_PARTITION_REF, ¶ms, sizeof(params))); pKernelMIGGpuInstance->instanceHandles.hClient = hClient; pKernelMIGGpuInstance->instanceHandles.hDevice = hDevice; @@ -1494,74 +1512,6 @@ } /*! - * @brief Function to allocate N available sys pipes for the given swizzid. - * This function will only retrieve available pipes according to the - * sys pipe free mask in KernelMIGManager, and is not responsible for - * updating that mask. - * - * @param[IN] pGpu - * @param[IN] pKernerlMIGManager - * @param[IN] engineCount Number of engines requested - * @param[IN] engineRange Range of acceptable RM_ENGINE_TYPE to allocate - * @param[IN/OUT] pInstanceEngines Bitmask tracking engines owned by MIG instance - */ -NV_STATUS -kmigmgrGetFreeEngines_IMPL -( - OBJGPU *pGpu, - KernelMIGManager *pKernelMIGManager, - NvU32 engineCount, - NV_RANGE engineRange, - ENGTYPE_BIT_VECTOR *pInstanceEngines -) -{ - const KERNEL_MIG_MANAGER_STATIC_INFO *pStaticInfo = kmigmgrGetStaticInfo(pGpu, pKernelMIGManager); - ENGTYPE_BIT_VECTOR partitionableEngines; - ENGTYPE_BIT_VECTOR availableEngines; - NvU32 numAllocated; - RM_ENGINE_TYPE rmEngineType; - - NV_ASSERT_OR_RETURN(pStaticInfo != NULL, NV_ERR_INVALID_STATE); - NV_ASSERT_OR_RETURN(!rangeIsEmpty(engineRange), NV_ERR_INVALID_ARGUMENT); - NV_ASSERT_OR_RETURN(pInstanceEngines != NULL, NV_ERR_INVALID_ARGUMENT); - - if (engineCount == 0) - { - return NV_OK; - } - - bitVectorFromRaw(&partitionableEngines, - &pStaticInfo->partitionableEngineMask, - sizeof(pStaticInfo->partitionableEngineMask)); - - NV_ASSERT_OR_RETURN(!bitVectorTestAllCleared(&partitionableEngines), - NV_ERR_INVALID_STATE); - - // availableEngines = (ENGINE_MASK & partitionableEngines) & ~enginesInUse - bitVectorClrAll(&availableEngines); - bitVectorSetRange(&availableEngines, engineRange); - bitVectorAnd(&availableEngines, &availableEngines, &partitionableEngines); - { - ENGTYPE_BIT_VECTOR enginesNotInUse; - bitVectorComplement(&enginesNotInUse, &pKernelMIGManager->partitionableEnginesInUse); - bitVectorAnd(&availableEngines, &availableEngines, &enginesNotInUse); - } - - numAllocated = 0; - FOR_EACH_IN_BITVECTOR(&availableEngines, rmEngineType) - { - if (numAllocated == engineCount) - break; - - bitVectorSet(pInstanceEngines, rmEngineType); - numAllocated++; - } - FOR_EACH_IN_BITVECTOR_END(); - - return NV_OK; -} - -/*! * @brief Trim runlist buffer pools */ void @@ -1615,7 +1565,7 @@ RM_ENGINE_TYPE rmEngineType; NvU32 engDesc; NV_STATUS status = NV_OK; - NvU32 numEngines = kfifoGetNumEngines_HAL(pGpu, pKernelFifo); + NvU32 numEngines = kfifoGetNumEschedDrivenEngines(pKernelFifo); NvU32 maxRunlists = kfifoGetMaxNumRunlists_HAL(pGpu, pKernelFifo); NvU64 runlistAlign; NvU64 allocFlags; @@ -1913,6 +1863,7 @@ &hSubscription, AMPERE_SMC_PARTITION_REF, &alloc, + sizeof(alloc), RMAPI_ALLOC_FLAGS_NONE, NULL, &pRmApi->defaultSecInfo), @@ -1920,6 +1871,7 @@ portMemSet(pExecPartImportParams, 0, sizeof(*pExecPartImportParams)); pExecPartImportParams->id = pComputeInstanceSave->id; + pExecPartImportParams->bCreateCap = NV_FALSE; portMemCopy(&pExecPartImportParams->info, sizeof(pExecPartImportParams->info), &pComputeInstanceSave->ciInfo, sizeof(pComputeInstanceSave->ciInfo)); @@ -2032,7 +1984,12 @@ .type = KMIGMGR_CREATE_COMPUTE_INSTANCE_PARAMS_TYPE_RESTORE, .inst.restore.pComputeInstanceSave = pComputeInstanceSave }; - NvU32 id; + // + // This id variable actually doesn't need to be initialized since the callee + // is not referencing to its value. But GCC13 is unhappy with that, thus WAR + // this issue by initializing it. + // + NvU32 id = pComputeInstanceSave->id; if (!pComputeInstanceSave->bValid) continue; @@ -2167,8 +2124,7 @@ ) { RsClient *pRsClient; - GPUInstanceSubscription *pGPUInstanceSubscription; - Subdevice *pSubdevice; + Device *pDevice; NV_STATUS status; NV_CHECK_OR_RETURN(LEVEL_SILENT, IS_MIG_ENABLED(pGpu), NV_FALSE); @@ -2183,9 +2139,40 @@ return NV_FALSE; ); NV_CHECK_OK_OR_ELSE(status, LEVEL_ERROR, - subdeviceGetByGpu(pRsClient, pGpu, &pSubdevice), + deviceGetByGpu(pRsClient, pGpu, NV_TRUE, &pDevice), return NV_FALSE; ); + return kmigmgrIsDeviceUsingDeviceProfiling(pGpu, pKernelMIGManager, pDevice); +} + +/*! + * @brief Function to check if specific device is subscribed to DeviceProfiling + */ +NvBool +kmigmgrIsDeviceUsingDeviceProfiling_IMPL +( + OBJGPU *pGpu, + KernelMIGManager *pKernelMIGManager, + Device *pDevice +) +{ + RsClient *pRsClient; + GPUInstanceSubscription *pGPUInstanceSubscription; + Subdevice *pSubdevice; + NV_STATUS status; + + NV_CHECK_OR_RETURN(LEVEL_SILENT, IS_MIG_ENABLED(pGpu), NV_FALSE); + + if (!kmigmgrIsDeviceProfilingInUse(pGpu, pKernelMIGManager)) + { + return NV_FALSE; + } + + pRsClient = RES_GET_CLIENT(pDevice); + + NV_CHECK_OK_OR_RETURN(LEVEL_ERROR, + subdeviceGetByInstance(pRsClient, RES_GET_HANDLE(pDevice), 0, &pSubdevice)); + NV_CHECK_OK_OR_ELSE(status, LEVEL_ERROR, gisubscriptionGetGPUInstanceSubscription(pRsClient, RES_GET_HANDLE(pSubdevice), &pGPUInstanceSubscription), return NV_FALSE; ); @@ -2223,14 +2210,14 @@ } /*! - * @brief Retrieves instance(s) associated with a client, if applicable + * @brief Retrieves instance(s) associated with a device, if applicable */ NV_STATUS -kmigmgrGetInstanceRefFromClient_IMPL +kmigmgrGetInstanceRefFromDevice_IMPL ( OBJGPU *pGpu, KernelMIGManager *pKernelMIGManager, - NvHandle hClient, + Device *pDevice, MIG_INSTANCE_REF *pRef ) { @@ -2249,12 +2236,12 @@ return NV_ERR_INVALID_STATE; } - NV_ASSERT_OK_OR_RETURN(serverGetClientUnderLock(&g_resServ, hClient, &pRsClient)); + pRsClient = RES_GET_CLIENT(pDevice); NV_CHECK_OK_OR_RETURN(LEVEL_ERROR, - subdeviceGetByGpu(pRsClient, pGpu, &pSubdevice)); + subdeviceGetByInstance(pRsClient, RES_GET_HANDLE(pDevice), 0, &pSubdevice)); - NV_CHECK_OK_OR_RETURN(LEVEL_ERROR, + NV_CHECK_OK_OR_RETURN(LEVEL_NOTICE, gisubscriptionGetGPUInstanceSubscription(pRsClient, RES_GET_HANDLE(pSubdevice), &pGPUInstanceSubscription)); @@ -2281,23 +2268,58 @@ } /*! - * @brief Retrieves GPU instance heap associated with a client, if applicable + * @brief Retrieves instance(s) associated with a client, if applicable */ NV_STATUS -kmigmgrGetMemoryPartitionHeapFromClient_IMPL +kmigmgrGetInstanceRefFromClient_IMPL +( + OBJGPU *pGpu, + KernelMIGManager *pKernelMIGManager, + NvHandle hClient, + MIG_INSTANCE_REF *pRef +) +{ + RsClient *pRsClient; + Device *pDevice; + + NV_ASSERT_OR_RETURN(pRef != NULL, NV_ERR_INVALID_ARGUMENT); + *pRef = kmigmgrMakeNoMIGReference(); + + if (!IS_MIG_IN_USE(pGpu)) + { + return NV_ERR_INVALID_STATE; + } + + NV_ASSERT_OK_OR_RETURN(serverGetClientUnderLock(&g_resServ, hClient, &pRsClient)); + + NV_CHECK_OK_OR_RETURN(LEVEL_ERROR, + deviceGetByGpu(pRsClient, pGpu, NV_TRUE, &pDevice)); + + return kmigmgrGetInstanceRefFromDevice(pGpu, pKernelMIGManager, + pDevice, pRef); +} + +/*! + * @brief Retrieves GPU instance heap associated with a device, if applicable + */ +NV_STATUS +kmigmgrGetMemoryPartitionHeapFromDevice_IMPL ( OBJGPU *pGpu, KernelMIGManager *pKernelMIGManager, - NvHandle hClient, + Device *pDevice, Heap **ppMemoryPartitionHeap ) { MIG_INSTANCE_REF ref; NV_STATUS rmStatus = NV_OK; + NvHandle hClient; NV_ASSERT_OR_RETURN(IS_MIG_IN_USE(pGpu), NV_ERR_INVALID_STATE); - rmStatus = kmigmgrGetInstanceRefFromClient(pGpu, pKernelMIGManager, hClient, &ref); + hClient = RES_GET_CLIENT_HANDLE(pDevice); + + rmStatus = kmigmgrGetInstanceRefFromDevice(pGpu, pKernelMIGManager, pDevice, &ref); if ((rmStatus != NV_OK) || !kmigmgrIsMIGReferenceValid(&ref)) { RS_PRIV_LEVEL privLevel = rmclientGetCachedPrivilegeByHandle(hClient); @@ -2334,17 +2356,17 @@ * @brief Retrieves swizzid associated with a client, if applicable */ NV_STATUS -kmigmgrGetSwizzIdFromClient_IMPL +kmigmgrGetSwizzIdFromDevice_IMPL ( OBJGPU *pGpu, KernelMIGManager *pKernelMIGManager, - NvHandle hClient, + Device *pDevice, NvU32 *pSwizzId ) { MIG_INSTANCE_REF ref; NV_ASSERT_OK_OR_RETURN( - kmigmgrGetInstanceRefFromClient(pGpu, pKernelMIGManager, hClient, &ref)); + kmigmgrGetInstanceRefFromDevice(pGpu, pKernelMIGManager, pDevice, &ref)); *pSwizzId = ref.pKernelMIGGpuInstance->swizzId; return NV_OK; @@ -2520,6 +2542,29 @@ pKernelMIGGpuInstance->pMemoryPartitionHeap = pMemoryPartitionHeap; pKernelMIGGpuInstance->partitionFlag = partitionFlag; + // + // Offloading of VGPU to GSP requires that the memRange in KERNEL_MIG_GPU_INSTANCE + // be populated, as the plugin will query only within GSP for GPU INSTANCE information. + // CPU-RM is the entity which actually calculates and allocates memory, so with + // VGPU offloaded, GSP-RM must be updated with the memRange info. + // + if (IS_GSP_CLIENT(pGpu) && !IS_VIRTUAL(pGpu) && IS_VGPU_GSP_PLUGIN_OFFLOAD_ENABLED(pGpu)) + { + RM_API *pRmApi = GPU_GET_PHYSICAL_RMAPI(pGpu); + NV2080_CTRL_INTERNAL_KMIGMGR_PROMOTE_GPU_INSTANCE_MEM_RANGE_PARAMS memParams; + + memParams.swizzId = pKernelMIGGpuInstance->swizzId; + memParams.memAddrRange.lo = pKernelMIGGpuInstance->memRange.lo; + memParams.memAddrRange.hi = pKernelMIGGpuInstance->memRange.hi; + NV_CHECK_OK_OR_RETURN(LEVEL_ERROR, + pRmApi->Control(pRmApi, + pGpu->hInternalClient, + pGpu->hInternalSubdevice, + NV2080_CTRL_CMD_INTERNAL_KMIGMGR_PROMOTE_GPU_INSTANCE_MEM_RANGE, + &memParams, + sizeof(memParams))); + } + NV_CHECK_OK_OR_RETURN(LEVEL_ERROR, kmigmgrGetProfileByPartitionFlag(pGpu, pKernelMIGManager, partitionFlag, &pKernelMIGGpuInstance->pProfile)); @@ -2533,6 +2578,8 @@ pKernelMIGGpuInstance, &pKernelMIGGpuInstance->resourceAllocation)); + pKernelMIGGpuInstance->resourceAllocation.gfxGpcCount = pKernelMIGGpuInstance->pProfile->gfxGpcCount; + // Set assigned engines as in use NV_ASSERT_OK_OR_RETURN( kmigmgrSetEnginesInUse(pGpu, pKernelMIGManager, &pKernelMIGGpuInstance->resourceAllocation.engines)); @@ -3071,7 +3118,7 @@ * * @param[IN] pGpu * @param[IN] pKernelMIGManager - * @param[IN] hClient Client handle subscribed to GI + * @param[IN] pDevice Device subscribed to GI * @param[OUT] ppCe Scrubber CE */ NV_STATUS @@ -3079,7 +3126,7 @@ ( OBJGPU *pGpu, KernelMIGManager *pKernelMIGManager, - NvHandle hClient, + Device *pDevice, NvU32 *ceInst ) { @@ -3087,7 +3134,7 @@ ENGTYPE_BIT_VECTOR ces; NV_ASSERT_OK_OR_RETURN( - kmigmgrGetInstanceRefFromClient(pGpu, pKernelMIGManager, hClient, &ref)); + kmigmgrGetInstanceRefFromDevice(pGpu, pKernelMIGManager, pDevice, &ref)); bitVectorClrAll(&ces); bitVectorSetRange(&ces, RM_ENGINE_RANGE_COPY()); @@ -3156,7 +3203,9 @@ pParams->partitionDescs[entryCount].partitionFlag = pStaticInfo->pProfiles->table[i].partitionFlag; pParams->partitionDescs[entryCount].grCount = pStaticInfo->pProfiles->table[i].grCount; + pParams->partitionDescs[entryCount].gfxGrCount = pStaticInfo->pProfiles->table[i].gfxGrCount; pParams->partitionDescs[entryCount].gpcCount = pStaticInfo->pProfiles->table[i].gpcCount; + pParams->partitionDescs[entryCount].gfxGpcCount = pStaticInfo->pProfiles->table[i].gfxGpcCount; pParams->partitionDescs[entryCount].virtualGpcCount = pStaticInfo->pProfiles->table[i].virtualGpcCount; pParams->partitionDescs[entryCount].veidCount = pStaticInfo->pProfiles->table[i].veidCount; pParams->partitionDescs[entryCount].smCount = pStaticInfo->pProfiles->table[i].smCount; @@ -3222,6 +3271,8 @@ { pComputeInstanceSave->ciInfo.gpcMask = DRF_MASK(pMIGComputeInstance->resourceAllocation.gpcCount - 1 : 0); } + + pComputeInstanceSave->ciInfo.gfxGpcCount = pMIGComputeInstance->resourceAllocation.gfxGpcCount; pComputeInstanceSave->ciInfo.veidOffset = pMIGComputeInstance->resourceAllocation.veidOffset; pComputeInstanceSave->ciInfo.veidCount = pMIGComputeInstance->resourceAllocation.veidCount; pComputeInstanceSave->ciInfo.smCount = pMIGComputeInstance->resourceAllocation.smCount; @@ -3335,7 +3386,7 @@ portMemSet(¶ms, 0, sizeof(params)); params.swizzId = pKernelMIGGpuInstance->swizzId; NV_ASSERT_OK_OR_GOTO(status, - pRmApi->Alloc(pRmApi, hClient, hSubdevice, &hGPUInstanceSubscription, AMPERE_SMC_PARTITION_REF, ¶ms), + pRmApi->Alloc(pRmApi, hClient, hSubdevice, &hGPUInstanceSubscription, AMPERE_SMC_PARTITION_REF, ¶ms, sizeof(params)), failed); } @@ -3344,7 +3395,7 @@ portMemSet(¶ms, 0, sizeof(params)); params.execPartitionId = pMIGComputeInstance->id; NV_ASSERT_OK_OR_GOTO(status, - pRmApi->Alloc(pRmApi, hClient, hGPUInstanceSubscription, &hComputeInstanceSubscription, AMPERE_SMC_EXEC_PARTITION_REF, ¶ms), + pRmApi->Alloc(pRmApi, hClient, hGPUInstanceSubscription, &hComputeInstanceSubscription, AMPERE_SMC_EXEC_PARTITION_REF, ¶ms, sizeof(params)), failed); } @@ -3500,7 +3551,7 @@ // This is done specifically to accomodate legacy flows which don't have knowledge of the new spanStart field // spanStart = (params.inst.request.pReqComputeInstanceInfo[CIIdx].spanStart != 0) - ? params.inst.request.pReqComputeInstanceInfo[CIIdx].spanStart + ? params.inst.request.pReqComputeInstanceInfo[CIIdx].spanStart : params.inst.request.pReqComputeInstanceInfo[CIIdx].veidStartOffset / maxVeidsPerGpc; } } @@ -3558,7 +3609,7 @@ pCIProfile->gpcCount = gpcCount; pCIProfile->smCount = gpcCount * (pKernelMIGGpuInstance->pProfile->smCount / pKernelMIGGpuInstance->pProfile->gpcCount); pCIProfile->veidCount = maxVeidsPerGpc * gpcCount; - + // Force non-profile requests to go through VEID allocator pConfigRequestPerCi[CIIdx].veidSpanStart = KMIGMGR_SPAN_OFFSET_INVALID; } @@ -3566,8 +3617,8 @@ pConfigRequestPerCi[CIIdx].ctsId = ctsId; // Perform VEID request checks or use the best fit allocator to find a slot - NV_CHECK_OK_OR_GOTO(status, LEVEL_ERROR, - kgrmgrCheckVeidsRequest(pGpu, pKernelGraphicsManager, + NV_CHECK_OK_OR_GOTO(status, LEVEL_ERROR, + kgrmgrCheckVeidsRequest(pGpu, pKernelGraphicsManager, &shadowVeidInUseMask, pCIProfile->veidCount, &pConfigRequestPerCi[CIIdx].veidSpanStart, @@ -3606,7 +3657,7 @@ bitVectorClrAll(&engines); bitVectorAnd(&engines, &pResourceAllocation->engines, &pKernelMIGGpuInstance->resourceAllocation.localEngines); NV_CHECK_OR_ELSE(LEVEL_ERROR, - bitVectorTestEqual(&engines, &pResourceAllocation->engines), + bitVectorTestEqual(&engines, &pResourceAllocation->engines), status = NV_ERR_INVALID_ARGUMENT; goto done;); // Set Shared/Exclusive Engine Masks for GRs restored @@ -3615,7 +3666,7 @@ bitVectorAnd(&engines, &engines, &pResourceAllocation->engines); // Only 1 GR can be requested per compute instance - NV_CHECK_OR_ELSE(LEVEL_ERROR, + NV_CHECK_OR_ELSE(LEVEL_ERROR, (kmigmgrCountEnginesOfType(&engines, RM_ENGINE_TYPE_GR(0)) == 1), status = NV_ERR_INVALID_ARGUMENT; goto done;); @@ -3627,7 +3678,7 @@ // Exclusive engine mask should not intersect with the current exclusive mask bitVectorAnd(&tempVector, &engines, &shadowExclusiveEngMask); - NV_CHECK_OR_ELSE(LEVEL_ERROR, + NV_CHECK_OR_ELSE(LEVEL_ERROR, bitVectorTestAllCleared(&tempVector), status = NV_ERR_STATE_IN_USE; goto done;); bitVectorOr(&shadowExclusiveEngMask, &shadowExclusiveEngMask, &engines); @@ -3645,7 +3696,7 @@ // Exclusive engine mask should not intersect with the current exclusive mask bitVectorAnd(&tempVector, &engines, &shadowExclusiveEngMask); - NV_CHECK_OR_ELSE(LEVEL_ERROR, + NV_CHECK_OR_ELSE(LEVEL_ERROR, bitVectorTestAllCleared(&tempVector), status = NV_ERR_STATE_IN_USE; goto done;); bitVectorOr(&shadowExclusiveEngMask, &shadowExclusiveEngMask, &engines); @@ -3663,7 +3714,7 @@ // Exclusive engine mask should not intersect with the current exclusive mask bitVectorAnd(&tempVector, &engines, &shadowExclusiveEngMask); - NV_CHECK_OR_ELSE(LEVEL_ERROR, + NV_CHECK_OR_ELSE(LEVEL_ERROR, bitVectorTestAllCleared(&tempVector), status = NV_ERR_STATE_IN_USE; goto done;); bitVectorOr(&shadowExclusiveEngMask, &shadowExclusiveEngMask, &engines); @@ -3681,7 +3732,7 @@ // Exclusive engine mask should not intersect with the current exclusive mask bitVectorAnd(&tempVector, &engines, &shadowExclusiveEngMask); - NV_CHECK_OR_ELSE(LEVEL_ERROR, + NV_CHECK_OR_ELSE(LEVEL_ERROR, bitVectorTestAllCleared(&tempVector), status = NV_ERR_STATE_IN_USE; goto done;); bitVectorOr(&shadowExclusiveEngMask, &shadowExclusiveEngMask, &engines); @@ -3699,7 +3750,7 @@ // Exclusive engine mask should not intersect with the current exclusive mask bitVectorAnd(&tempVector, &engines, &shadowExclusiveEngMask); - NV_CHECK_OR_ELSE(LEVEL_ERROR, + NV_CHECK_OR_ELSE(LEVEL_ERROR, bitVectorTestAllCleared(&tempVector), status = NV_ERR_STATE_IN_USE; goto done;); bitVectorOr(&shadowExclusiveEngMask, &shadowExclusiveEngMask, &engines); @@ -3717,7 +3768,7 @@ // Exclusive engine mask should not intersect with the current exclusive mask bitVectorAnd(&tempVector, &engines, &shadowExclusiveEngMask); - NV_CHECK_OR_ELSE(LEVEL_ERROR, + NV_CHECK_OR_ELSE(LEVEL_ERROR, bitVectorTestAllCleared(&tempVector), status = NV_ERR_STATE_IN_USE; goto done;); bitVectorOr(&shadowExclusiveEngMask, &shadowExclusiveEngMask, &engines); @@ -3743,7 +3794,8 @@ grCount, &pResourceAllocation->engines, &shadowExclusiveEngMask, - &shadowSharedEngMask), done); + &shadowSharedEngMask, + &pKernelMIGGpuInstance->resourceAllocation.engines), done); // Allocate the Copy engines for this compute instance NV_CHECK_OK_OR_GOTO(status, LEVEL_ERROR, @@ -3754,7 +3806,8 @@ ceCount, &pResourceAllocation->engines, &shadowExclusiveEngMask, - &shadowSharedEngMask), done); + &shadowSharedEngMask, + &pKernelMIGGpuInstance->resourceAllocation.engines), done); // Allocate the NVDEC engines for this compute instance NV_CHECK_OK_OR_GOTO(status, LEVEL_ERROR, @@ -3765,7 +3818,8 @@ decCount, &pResourceAllocation->engines, &shadowExclusiveEngMask, - &shadowSharedEngMask), done); + &shadowSharedEngMask, + &pKernelMIGGpuInstance->resourceAllocation.engines), done); // Allocate the NVENC engines for this compute instance NV_CHECK_OK_OR_GOTO(status, LEVEL_ERROR, @@ -3776,7 +3830,8 @@ encCount, &pResourceAllocation->engines, &shadowExclusiveEngMask, - &shadowSharedEngMask), done); + &shadowSharedEngMask, + &pKernelMIGGpuInstance->resourceAllocation.engines), done); // Allocate the NVJPG engines for this compute instance NV_CHECK_OK_OR_GOTO(status, LEVEL_ERROR, @@ -3787,7 +3842,8 @@ jpgCount, &pResourceAllocation->engines, &shadowExclusiveEngMask, - &shadowSharedEngMask), done); + &shadowSharedEngMask, + &pKernelMIGGpuInstance->resourceAllocation.engines), done); // Allocate the NVOFA engines for this compute instance NV_CHECK_OK_OR_GOTO(status, LEVEL_ERROR, @@ -3798,7 +3854,8 @@ ofaCount, &pResourceAllocation->engines, &shadowExclusiveEngMask, - &shadowSharedEngMask), done); + &shadowSharedEngMask, + &pKernelMIGGpuInstance->resourceAllocation.engines), done); } // Cache local mask of engine IDs for this compute instance @@ -3810,7 +3867,9 @@ if (!bQuery) { NvU32 swizzId = pKernelMIGGpuInstance->swizzId; + KMIGMGR_CONFIGURE_INSTANCE_REQUEST configRequestsPerCiOrdered[KMIGMGR_MAX_COMPUTE_INSTANCES] = {0}; NvU32 updateEngMask; + NvU32 updateEngMaskShadow; // Populate configure GPU instance parameters with compute instance info updateEngMask = 0x0; @@ -3833,9 +3892,38 @@ updateEngMask |= NVBIT32(RM_ENGINE_TYPE_GR_IDX(localEngineType)); } + // + // Reorder the entries in pConfigRequestPerCi per the GR engine assigned to each CI + // (Sorted from lower GR to higer GR), so kmigmgrConfigureGPUInstance can configure + // each CI with correct GR. + // + updateEngMaskShadow = updateEngMask; + i = 0; + while (updateEngMaskShadow != 0) + { + for (CIIdx = 0; CIIdx < count; ++CIIdx) + { + RM_ENGINE_TYPE localRmEngineType; + MIG_COMPUTE_INSTANCE *pMIGComputeInstance = &pComputeInstanceInfo[CIIdx]; + MIG_RESOURCE_ALLOCATION *pComputeResourceAllocation = &pMIGComputeInstance->resourceAllocation; + NV_ASSERT_OK( + kmigmgrEngineTypeXlate(&pComputeResourceAllocation->localEngines, RM_ENGINE_TYPE_GR(0), + &pComputeResourceAllocation->engines, &localRmEngineType)); + + if (portUtilCountTrailingZeros32(updateEngMaskShadow) == RM_ENGINE_TYPE_GR_IDX(localRmEngineType)) + { + configRequestsPerCiOrdered[i] = pConfigRequestPerCi[CIIdx]; + updateEngMaskShadow &= ~NVBIT32(RM_ENGINE_TYPE_GR_IDX(localRmEngineType)); + i++; + break; + } + } + NV_ASSERT(CIIdx < count); + } + // Configure the GR engines for each compute instance status = kmigmgrConfigureGPUInstance(pGpu, pKernelMIGManager, swizzId, - pConfigRequestPerCi, + configRequestsPerCiOrdered, updateEngMask); // Do our best to deconfigure the engines we configured so far, then bail @@ -4131,7 +4219,7 @@ pComputeResourceAllocation->gpcIds[(pComputeResourceAllocation->gpcCount)++] = gpcIdx; tempGpcMask &= ~(NVBIT32(gpcIdx)); } - + pComputeResourceAllocation->gfxGpcCount = info.gfxGpcCount; pComputeResourceAllocation->veidCount = info.veidCount; pComputeResourceAllocation->veidOffset = info.veidOffset; pComputeResourceAllocation->smCount = info.smCount; @@ -4164,8 +4252,8 @@ pConfigRequestPerCi[0].veidSpanStart = info.spanStart; shadowVeidInUseMask = pKernelGraphicsManager->veidInUseMask; - NV_CHECK_OK_OR_GOTO(status, LEVEL_ERROR, - kgrmgrCheckVeidsRequest(pGpu, pKernelGraphicsManager, + NV_CHECK_OK_OR_GOTO(status, LEVEL_ERROR, + kgrmgrCheckVeidsRequest(pGpu, pKernelGraphicsManager, &shadowVeidInUseMask, pConfigRequestPerCi[0].profile.veidCount, &pConfigRequestPerCi[0].veidSpanStart, @@ -4190,7 +4278,7 @@ } NV_ASSERT(pKernelMIGGpuInstance->MIGComputeInstance[CIIdx].id == KMIGMGR_COMPUTE_INSTANCE_ID_INVALID); - + pMIGComputeInstance->spanStart = pConfigRequestPerCi[0].veidSpanStart; portMemCopy(&pKernelMIGGpuInstance->MIGComputeInstance[CIIdx], @@ -5317,7 +5405,7 @@ cleanup_createPartitionCheck); // On Nvswitch based systems, suspend gpu fabric probe on nvlink inband - gpuFabricProbeSuspend(pGpu->pGpuFabricProbeInfo); + gpuFabricProbeSuspend(pGpu->pGpuFabricProbeInfoKernel); // Ensure NVLINK is shutdown before enabling MIG if (!kmigmgrIsMIGNvlinkP2PSupportOverridden(pGpu, pKernelMIGManager) || @@ -5437,8 +5525,12 @@ NV_ASSERT_OK( gpuDeleteClassFromClassDBByClassId(pGpu, AMPERE_SMC_PARTITION_REF)); + // // Disable ctx buf pool after freeing any resources that uses it. - pGpu->setProperty(pGpu, PDB_PROP_GPU_MOVE_CTX_BUFFERS_TO_PMA, NV_FALSE); + // Leave enabled on platforms that support it outside MIG. + // + pGpu->setProperty(pGpu, PDB_PROP_GPU_MOVE_CTX_BUFFERS_TO_PMA, + gpuIsCtxBufAllocInPmaSupported_HAL(pGpu)); // // HACK: GSP-RM always enables/disables LCEs during MIG enable/disable. @@ -5461,9 +5553,9 @@ // On Nvswitch based systems, resume the gpu fabric probe // request on nvlink inband to register the GPU with the nvswitch fabric // - if (pGpu->pGpuFabricProbeInfo != NULL) + if (pGpu->pGpuFabricProbeInfoKernel != NULL) { - NV_ASSERT_OK(gpuFabricProbeResume(pGpu->pGpuFabricProbeInfo)); + NV_ASSERT_OK(gpuFabricProbeResume(pGpu->pGpuFabricProbeInfoKernel)); } cleanup_createPartitionCheck: @@ -5685,6 +5777,12 @@ rmMemPoolSetup((void*)&pKernelMIGGpuInstance->pMemoryPartitionHeap->pmaObject, &pKernelMIGGpuInstance->pPageTableMemPool, version)); + // Allocate the pool in CPR in case of Confidential Compute + if (gpuIsCCFeatureEnabled(pGpu)) + { + rmMemPoolAllocateProtectedMemory(pKernelMIGGpuInstance->pPageTableMemPool, NV_TRUE); + } + return NV_OK; } @@ -5702,6 +5800,7 @@ { Heap *pHeap; MemoryManager *pMemoryManager = GPU_GET_MEMORY_MANAGER(pGpu); + NvU32 pmaConfig = PMA_QUERY_NUMA_ONLINED; NV_ASSERT_OR_RETURN(pKernelMIGGpuInstance != NULL, NV_ERR_INVALID_ARGUMENT); pHeap = pKernelMIGGpuInstance->pMemoryPartitionHeap; NV_ASSERT_OR_RETURN(pHeap != NULL, NV_ERR_INVALID_STATE); @@ -5717,7 +5816,12 @@ // This is just a sanity check to make sure this assumption is correct and // allocation from PMA cannot trigger UVM evictions. // - if (memmgrIsPmaInitialized(pMemoryManager)) + // When FB memory is onlined as NUMA node, kernel can directly alloc FB memory + // and hence free memory can not be expected to be same as total memory. + // + if (memmgrIsPmaInitialized(pMemoryManager) && + (pmaQueryConfigs(&pHeap->pmaObject, &pmaConfig) == NV_OK) && + !(pmaConfig & PMA_QUERY_NUMA_ONLINED)) { NvU64 freeSpace, totalSpace; pmaGetFreeMemory(&pHeap->pmaObject, &freeSpace); @@ -5965,6 +6069,24 @@ return NV_OK; } +/*! + * @brief Update MIG CI config for CPU-RM if compute instance is created + * by a guest and RPC is directly handled by GSP-RM + */ +NV_STATUS +kmigmgrUpdateCiConfigForVgpu_IMPL +( + OBJGPU *pGpu, + KernelMIGManager *pKernelMIGManager, + NvU32 execPartCount, + NvU32 *pExecPartId, + NvU32 gfid, + NvBool bDelete +) +{ + return NV_ERR_NOT_SUPPORTED; +} + // Control call for getting active gpu instance Ids NV_STATUS subdeviceCtrlCmdGpuGetActivePartitionIds_IMPL @@ -6519,6 +6641,7 @@ pParams->queryPartitionInfo[i].ceCount = kmigmgrCountEnginesOfType(&pResourceAllocation->engines, RM_ENGINE_TYPE_COPY(0)); pParams->queryPartitionInfo[i].gpcCount = pResourceAllocation->gpcCount; + pParams->queryPartitionInfo[i].gfxGpcCount = pResourceAllocation->gfxGpcCount; pParams->queryPartitionInfo[i].virtualGpcCount = pResourceAllocation->virtualGpcCount; pParams->queryPartitionInfo[i].nvDecCount = kmigmgrCountEnginesOfType(&pResourceAllocation->engines, RM_ENGINE_TYPE_NVDEC(0)); @@ -6547,6 +6670,7 @@ continue; pParams->queryPartitionInfo[i].gpcsPerGr[j] = pRpcParams->queryPartitionInfo[i].gpcsPerGr[j]; + pParams->queryPartitionInfo[i].gfxGpcPerGr[j] = pRpcParams->queryPartitionInfo[i].gfxGpcPerGr[j]; pParams->queryPartitionInfo[i].veidsPerGr[j] = pRpcParams->queryPartitionInfo[i].veidsPerGr[j]; pParams->queryPartitionInfo[i].virtualGpcsPerGr[j] = pRpcParams->queryPartitionInfo[i].virtualGpcsPerGr[j]; @@ -6665,20 +6789,26 @@ if (IS_GSP_CLIENT(pGpu)) { - struct GPUMGR_SAVE_GPU_INSTANCE save; + GPUMGR_SAVE_GPU_INSTANCE *pSave = portMemAllocNonPaged(sizeof(*pSave)); + NV_CHECK_OR_ELSE(LEVEL_ERROR, + pSave != NULL, + status = NV_ERR_NO_MEMORY; + goto cleanup_mig_state;); + KMIGMGR_CREATE_GPU_INSTANCE_PARAMS restore = { .type = KMIGMGR_CREATE_GPU_INSTANCE_PARAMS_TYPE_RESTORE, - .inst.restore.pGPUInstanceSave = &save, + .inst.restore.pGPUInstanceSave = pSave, }; - save.bValid = NV_TRUE; - save.swizzId = pParams->swizzId; - save.pOsRmCaps = NULL; - portMemCopy(&save.giInfo, sizeof(save.giInfo), &pParams->info, sizeof(pParams->info)); + pSave->bValid = NV_TRUE; + pSave->swizzId = pParams->swizzId; + pSave->pOsRmCaps = NULL; + portMemCopy(&(pSave->giInfo), sizeof(pSave->giInfo), &pParams->info, sizeof(pParams->info)); - NV_CHECK_OK_OR_GOTO(status, LEVEL_ERROR, - kmigmgrCreateGPUInstance(pGpu, pKernelMIGManager, &pParams->swizzId, restore, NV_TRUE, NV_FALSE), - cleanup_rpc); + status = kmigmgrCreateGPUInstance(pGpu, pKernelMIGManager, &pParams->swizzId, restore, NV_TRUE, NV_FALSE); + + portMemFree(pSave); + NV_CHECK_OR_GOTO(LEVEL_ERROR, status == NV_OK, cleanup_rpc); } return NV_OK; @@ -7491,4 +7621,3 @@ FOR_EACH_INDEX_IN_MASK_END; return !!((ctsIdValidMask & ~invalidMask) & NVBIT64(ctsId)); } - diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/kernel/gpu/mig_mgr/mig_config_session.c nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/kernel/gpu/mig_mgr/mig_config_session.c --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/kernel/gpu/mig_mgr/mig_config_session.c 2023-10-25 20:21:14.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/kernel/gpu/mig_mgr/mig_config_session.c 2024-03-05 22:13:40.000000000 +0000 @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 2019-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2019-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -32,6 +32,8 @@ * *****************************************************************************/ +#define NVOC_MIG_CONFIG_SESSION_H_PRIVATE_ACCESS_ALLOWED + #include "core/core.h" #include "gpu/gpu.h" #include "kernel/gpu/mig_mgr/mig_config_session.h" diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/kernel/gpu/mig_mgr/mig_monitor_session.c nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/kernel/gpu/mig_mgr/mig_monitor_session.c --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/kernel/gpu/mig_mgr/mig_monitor_session.c 2023-10-25 20:21:14.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/kernel/gpu/mig_mgr/mig_monitor_session.c 2024-03-05 22:13:40.000000000 +0000 @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 2020-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2020-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -27,11 +27,13 @@ * * Description: * Upon successful allocation of this class, a client is granted - * permission to query information across the GPU instances + * permission to query information across the GPU instances * irrespective of per-instance MIG subscriptions * *****************************************************************************/ +#define NVOC_MIG_MONITOR_SESSION_H_PRIVATE_ACCESS_ALLOWED + #include "core/core.h" #include "kernel/gpu/mig_mgr/mig_monitor_session.h" #include "class/clc640.h" diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/kernel/gpu/mmu/arch/hopper/kern_gmmu_fmt_gh10x.c nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/kernel/gpu/mmu/arch/hopper/kern_gmmu_fmt_gh10x.c --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/kernel/gpu/mmu/arch/hopper/kern_gmmu_fmt_gh10x.c 2023-10-25 20:21:15.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/kernel/gpu/mmu/arch/hopper/kern_gmmu_fmt_gh10x.c 2024-03-05 22:13:40.000000000 +0000 @@ -58,7 +58,7 @@ { NV_ASSERT_OR_RETURN_VOID(version == GMMU_FMT_VERSION_3); NV_ASSERT_OR_RETURN_VOID(numLevels >= 7); - + // Page directory 4 (root). pLevels[0].virtAddrBitHi = 56; pLevels[0].virtAddrBitLo = 56; diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/kernel/gpu/mmu/arch/hopper/kern_gmmu_gh100.c nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/kernel/gpu/mmu/arch/hopper/kern_gmmu_gh100.c --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/kernel/gpu/mmu/arch/hopper/kern_gmmu_gh100.c 2023-10-25 20:21:15.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/kernel/gpu/mmu/arch/hopper/kern_gmmu_gh100.c 2024-03-05 22:13:40.000000000 +0000 @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 2021-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2021-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -25,10 +25,15 @@ #include "gpu/mmu/kern_gmmu.h" #include "gpu/mem_mgr/mem_mgr.h" +#include "vgpu/vgpu_events.h" +#include "nv_sriov_defines.h" +#include "kernel/gpu/intr/intr.h" #include "mmu/gmmu_fmt.h" #include "published/hopper/gh100/dev_mmu.h" #include "published/hopper/gh100/dev_fault.h" +#include "published/hopper/gh100/dev_vm.h" +#include "published/hopper/gh100/dev_vm_addendum.h" /*! * Check if a specific GMMU format version is supported. @@ -53,10 +58,10 @@ // Initialize the sparse encoding in the PDE PCF field for V3 GMMU_FMT_FAMILY *pFam = pKernelGmmu->pFmtFamilies[GMMU_FMT_VERSION_3 - 1]; - + if (pFam != NULL) { - // 1.Initialize sparsePde + // 1.Initialize sparsePde pdePcfSw |= (1 << SW_MMU_PCF_SPARSE_IDX); pdePcfSw |= (1 << SW_MMU_PCF_ATS_ALLOWED_IDX); NV_ASSERT_OR_RETURN((kgmmuTranslatePdePcfFromSw_HAL(pKernelGmmu, pdePcfSw, &pdePcfHw) == NV_OK), @@ -64,7 +69,7 @@ gmmuFieldSetAperture(&pFam->pde.fldAperture, GMMU_APERTURE_INVALID, pFam->sparsePde.v8); nvFieldSet32(&pFam->pde.fldPdePcf, pdePcfHw, pFam->sparsePde.v8); - + // 2.Initialize sparsePdeMulti for (i = 0; i < MMU_FMT_MAX_SUB_LEVELS; ++i) { @@ -77,7 +82,7 @@ nvFieldSet32(&pPdeFmt->fldPdePcf, pdePcfHw, pFam->sparsePdeMulti.v8); } } - + // 3.Initialize nv4kPte ptePcfSw |= (1 << SW_MMU_PCF_NV4K_IDX); nvFieldSetBool(&pFam->pte.fldValid, NV_FALSE, pFam->nv4kPte.v8); @@ -340,3 +345,289 @@ { return NV_PFAULT_MMU_ENG_ID_GRAPHICS; } + +NV_STATUS +kgmmuGetFaultRegisterMappings_GH100 +( + OBJGPU *pGpu, + KernelGmmu *pKernelGmmu, + NvU32 index, + NvP64 *pFaultBufferGet, + NvP64 *pFaultBufferPut, + NvP64 *pFaultBufferInfo, + NvP64 *pHubIntr, + NvP64 *pHubIntrEnSet, + NvP64 *pHubIntrEnClear, + NvU32 *faultMask, + NvP64 *pPrefetchCtrl +) +{ + DEVICE_MAPPING *pMapping = gpuGetDeviceMapping(pGpu, DEVICE_INDEX_GPU, 0); + NvP64 bar0Mapping = NV_PTR_TO_NvP64(pMapping->gpuNvAddr); + + NV_ASSERT_OR_RETURN((index < NUM_FAULT_BUFFERS), NV_ERR_INVALID_ARGUMENT); + + // + // If Hopper CC is not enabled or GSP doesn't entirely own the HW fault buffers + // use the Turing HAL + // + if (!gpuIsCCFeatureEnabled(pGpu) || !gpuIsGspOwnedFaultBuffersEnabled(pGpu)) + { + return kgmmuGetFaultRegisterMappings_TU102(pGpu, pKernelGmmu, index, + pFaultBufferGet, pFaultBufferPut, + pFaultBufferInfo, pHubIntr, + pHubIntrEnSet, pHubIntrEnClear, + faultMask, pPrefetchCtrl); + } + + *pFaultBufferGet = 0; + *pFaultBufferInfo = 0; + *pHubIntr = 0; + *pHubIntrEnSet = 0; + *pHubIntrEnClear = 0; + *faultMask = 0; + *pPrefetchCtrl = 0; + + // + // When Hopper CC is enabled, we repurpose the access counter registers to + // hold the PUT pointer of the shadow buffers. Only GSP-RM can write the + // PUT pointer to these PRIs. CPU has read-only access to these PRIs + // + if (index == REPLAYABLE_FAULT_BUFFER) + { + Intr *pIntr = GPU_GET_INTR(pGpu); + NvU32 intrVector = intrGetVectorFromEngineId(pGpu, pIntr, MC_ENGINE_IDX_REPLAYABLE_FAULT_CPU, NV_FALSE); + struct GMMU_FAULT_BUFFER *pFaultBuffer; + GMMU_CLIENT_SHADOW_FAULT_BUFFER *pClientShadowFaultBuf; + FAULT_BUFFER_SHARED_MEMORY *pFaultBufSharedMem; + NvU32 leafReg; + NvU32 leafBit; + + leafReg = NV_CTRL_INTR_GPU_VECTOR_TO_LEAF_REG(intrVector); + leafBit = NV_CTRL_INTR_GPU_VECTOR_TO_LEAF_BIT(intrVector); + + pFaultBuffer = &pKernelGmmu->mmuFaultBuffer[GPU_GFID_PF]; + pClientShadowFaultBuf = + KERNEL_POINTER_FROM_NvP64(GMMU_CLIENT_SHADOW_FAULT_BUFFER *, + pFaultBuffer->pClientShadowFaultBuffer[index]); + + pFaultBufSharedMem = + KERNEL_POINTER_FROM_NvP64(FAULT_BUFFER_SHARED_MEMORY *, + pClientShadowFaultBuf->pFaultBufferSharedMemoryAddress); + + *pHubIntr = NvP64_PLUS_OFFSET(bar0Mapping, + GPU_GET_VREG_OFFSET(pGpu, NV_VIRTUAL_FUNCTION_PRIV_CPU_INTR_LEAF(leafReg))); + *pHubIntrEnSet = NvP64_PLUS_OFFSET(bar0Mapping, + GPU_GET_VREG_OFFSET(pGpu, NV_VIRTUAL_FUNCTION_PRIV_CPU_INTR_LEAF_EN_SET(leafReg))); + *pHubIntrEnClear = NvP64_PLUS_OFFSET(bar0Mapping, + GPU_GET_VREG_OFFSET(pGpu, NV_VIRTUAL_FUNCTION_PRIV_CPU_INTR_LEAF_EN_CLEAR(leafReg))); + *faultMask = NVBIT(leafBit); + *pFaultBufferGet = (NvU32*) &(pFaultBufSharedMem->swGetIndex); + *pFaultBufferPut = NvP64_PLUS_OFFSET(bar0Mapping, + GPU_GET_VREG_OFFSET(pGpu, NV_VIRTUAL_FUNCTION_PRIV_ACCESS_COUNTER_NOTIFY_BUFFER_HI)); + *pPrefetchCtrl = NvP64_PLUS_OFFSET(bar0Mapping, + GPU_GET_VREG_OFFSET(pGpu, NV_VIRTUAL_FUNCTION_PRIV_MMU_PAGE_FAULT_CTRL)); + } + else if (index == NON_REPLAYABLE_FAULT_BUFFER) + { + *pFaultBufferPut = NvP64_PLUS_OFFSET(bar0Mapping, + GPU_GET_VREG_OFFSET(pGpu, NV_VIRTUAL_FUNCTION_PRIV_ACCESS_COUNTER_NOTIFY_BUFFER_LO)); + } + else + { + NV_ASSERT_OR_RETURN(0, NV_ERR_INVALID_ARGUMENT); + } + + return NV_OK; +} + +NV_STATUS +kgmmuFaultBufferAllocSharedMemory_GH100 +( + OBJGPU *pGpu, + KernelGmmu *pKernelGmmu, + FAULT_BUFFER_TYPE index +) +{ + NV_STATUS status; + GMMU_CLIENT_SHADOW_FAULT_BUFFER *pClientShadowFaultBuffer; + MEMORY_DESCRIPTOR *pMemDesc; + NvU64 flags = MEMDESC_FLAGS_NONE; + + if (pKernelGmmu->getProperty(pKernelGmmu, PDB_PROP_KGMMU_FAULT_BUFFER_DISABLED)) + { + NV_PRINTF(LEVEL_ERROR, "Fault-Buffer is disabled. Flush Seq memory cannot be created\n"); + NV_ASSERT_OR_RETURN(0, NV_ERR_INVALID_STATE); + } + + if (index != REPLAYABLE_FAULT_BUFFER) + { + return NV_OK; + } + + if (!gpuIsCCFeatureEnabled(pGpu) || !gpuIsGspOwnedFaultBuffersEnabled(pGpu)) + { + return NV_OK; + } + + // + // On systems with SEV enabled, the fault buffer flush sequence memory should be allocated + // in unprotected sysmem as GSP will be writing to this location to let the guest + // know a flush has finished. + // + flags |= MEMDESC_FLAGS_ALLOC_IN_UNPROTECTED_MEMORY; + + pClientShadowFaultBuffer = &pKernelGmmu->mmuFaultBuffer[GPU_GFID_PF].clientShadowFaultBuffer[index]; + status = memdescCreate(&pMemDesc, pGpu, + sizeof(FAULT_BUFFER_SHARED_MEMORY), RM_PAGE_SIZE, + NV_FALSE, ADDR_SYSMEM, NV_MEMORY_UNCACHED, + flags); + if (status != NV_OK) + { + return status; + } + + status = memdescAlloc(pMemDesc); + if (status != NV_OK) + { + goto destroy_memdesc; + } + + status = memdescMap(pMemDesc, 0, + memdescGetSize(pMemDesc), + NV_TRUE, NV_PROTECT_READ_WRITE, + &pClientShadowFaultBuffer->pFaultBufferSharedMemoryAddress, + &pClientShadowFaultBuffer->pFaultBufferSharedMemoryPriv); + if (status != NV_OK) + { + goto free_memory; + } + + pClientShadowFaultBuffer->pFaultBufferSharedMemDesc = pMemDesc; + + return NV_OK; + +free_memory: + memdescFree(pMemDesc); + +destroy_memdesc: + memdescDestroy(pMemDesc); + + return status; +} + +void +kgmmuFaultBufferFreeSharedMemory_GH100 +( + OBJGPU *pGpu, + KernelGmmu *pKernelGmmu, + FAULT_BUFFER_TYPE index +) +{ + MEMORY_DESCRIPTOR *pMemDesc; + GMMU_CLIENT_SHADOW_FAULT_BUFFER *pClientShadowFaultBuffer; + + if (index != REPLAYABLE_FAULT_BUFFER) + { + return; + } + + if (!gpuIsCCFeatureEnabled(pGpu) || !gpuIsGspOwnedFaultBuffersEnabled(pGpu)) + { + return; + } + + pClientShadowFaultBuffer = &pKernelGmmu->mmuFaultBuffer[GPU_GFID_PF].clientShadowFaultBuffer[index]; + pMemDesc = pClientShadowFaultBuffer->pFaultBufferSharedMemDesc; + + memdescUnmap(pMemDesc, + NV_TRUE, osGetCurrentProcess(), + pClientShadowFaultBuffer->pFaultBufferSharedMemoryAddress, + pClientShadowFaultBuffer->pFaultBufferSharedMemoryPriv); + + memdescFree(pMemDesc); + memdescDestroy(pMemDesc); + return; +} + +/* + * @brief GSP client can use this function to initiate a replayable fault buffer flush when the + * HW fault buffer is owned by GSP. + */ +NV_STATUS +kgmmuIssueReplayableFaultBufferFlush_GH100 +( + OBJGPU *pGpu, + KernelGmmu *pKernelGmmu +) +{ + GMMU_CLIENT_SHADOW_FAULT_BUFFER *pClientShadowFaultBuffer; + FAULT_BUFFER_SHARED_MEMORY *pFaultBufSharedMem; + NvU32 gfid; + volatile NvU32 *pFlushSeqAddr; + NvU32 replayableFlushSeqValue; + NV_STATUS status; + RMTIMEOUT timeout; + + if (!gpuIsCCFeatureEnabled(pGpu) || !gpuIsGspOwnedFaultBuffersEnabled(pGpu) || !IS_GSP_CLIENT(pGpu)) + { + return NV_OK; + } + + NV_ASSERT_OK_OR_RETURN(vgpuGetCallingContextGfid(pGpu, &gfid)); + + pClientShadowFaultBuffer = &pKernelGmmu->mmuFaultBuffer[gfid].clientShadowFaultBuffer[REPLAYABLE_FAULT_BUFFER]; + pFaultBufSharedMem = KERNEL_POINTER_FROM_NvP64(FAULT_BUFFER_SHARED_MEMORY *, + pClientShadowFaultBuffer->pFaultBufferSharedMemoryAddress); + pFlushSeqAddr = (NvU32*) &(pFaultBufSharedMem->flushBufferSeqNum); + replayableFlushSeqValue = *pFlushSeqAddr; + + gpuSetTimeout(pGpu, GPU_TIMEOUT_DEFAULT, &timeout, 0); + GPU_VREG_WR32(pGpu, NV_VIRTUAL_FUNCTION_PRIV_DOORBELL, NV_DOORBELL_NOTIFY_LEAF_SERVICE_REPLAYABLE_FAULT_FLUSH_HANDLE); + + while (replayableFlushSeqValue + 1 != *pFlushSeqAddr) + { + status = gpuCheckTimeout(pGpu, &timeout); + + if (status != NV_OK) + { + NV_PRINTF(LEVEL_ERROR, "gpuCheckTimeout failed, status = 0x%x\n", status); + return status; + } + osSpinLoop(); + } + + return NV_OK; +} + +/* + * @brief When Hopper Confidential Compute is enabled, the put index of the + * client replayable/non-replayable shadow buffers gets stored in the + * access counter PRIs. This function is used by Kernel RM to read the put index. + * + * @param[in] pGpu OBJGPU pointer + * @param[in] pKernelGmmu KernelGmmu pointer + * @param[in] type Replayable/Non-replayable fault buffer + * + * @returns NvU32 + */ +NvU32 +kgmmuReadShadowBufPutIndex_GH100 +( + OBJGPU *pGpu, + KernelGmmu *pKernelGmmu, + FAULT_BUFFER_TYPE type +) +{ + NvU32 val; + if (type == REPLAYABLE_FAULT_BUFFER) + { + val = GPU_VREG_RD32(pGpu, NV_VIRTUAL_FUNCTION_PRIV_REPLAYABLE_FAULT_SHADOW_BUFFER_PUT); + } + else + { + val = GPU_VREG_RD32(pGpu, NV_VIRTUAL_FUNCTION_PRIV_NON_REPLAYABLE_FAULT_SHADOW_BUFFER_PUT); + val = DRF_VAL(_VIRTUAL_FUNCTION_PRIV, _NON_REPLAYABLE_FAULT_SHADOW_BUFFER_PUT, _PTR, val); + } + return val; +} diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/kernel/gpu/mmu/arch/maxwell/kern_gmmu_gm107.c nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/kernel/gpu/mmu/arch/maxwell/kern_gmmu_gm107.c --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/kernel/gpu/mmu/arch/maxwell/kern_gmmu_gm107.c 2023-10-25 20:21:15.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/kernel/gpu/mmu/arch/maxwell/kern_gmmu_gm107.c 2024-03-05 22:13:41.000000000 +0000 @@ -25,6 +25,7 @@ #include "gpu/mmu/kern_gmmu.h" #include "gpu/bus/kern_bus.h" +#include "vgpu/rpc.h" #include "published/maxwell/gm107/dev_fb.h" #include "published/maxwell/gm107/dev_mmu.h" @@ -36,7 +37,7 @@ * * @returns NvU32 */ -NvU32 +NvU64 kgmmuGetBigPageSize_GM107(KernelGmmu *pKernelGmmu) { return pKernelGmmu->defaultBigPageSize; @@ -78,6 +79,7 @@ NV_STATUS status = NV_OK; TLB_INVALIDATE_PARAMS params; NvU32 flushCount = 0; + NvBool bDoVgpuRpc = NV_FALSE; // // Bail out early if @@ -105,26 +107,29 @@ return; } - // - // Originally the flag is 0, but to WAR bug 2909388, add flag - // GPU_TIMEOUT_FLAGS_BYPASS_THREAD_STATE to bypass using threadStateCheckTimeout, - // GPU_TIMEOUT_FLAGS_BYPASS_CPU_YIELD to not wait inside timeout with mutex held. - // - gpuSetTimeout(pGpu, GPU_TIMEOUT_DEFAULT, ¶ms.timeout, - GPU_TIMEOUT_FLAGS_BYPASS_THREAD_STATE | - GPU_TIMEOUT_FLAGS_DEFAULT | GPU_TIMEOUT_FLAGS_BYPASS_CPU_YIELD); - - // - // 2. Wait until we can issue an invalidate. On pre-Turing, wait for space - // in the PRI FIFO. On Turing, check if an invalidate is already in progress. - // - // Set the GFID. - params.gfid = gfid; - - status = kgmmuCheckPendingInvalidates_HAL(pGpu, pKernelGmmu, ¶ms.timeout, params.gfid); - if (status != NV_OK) + if (!bDoVgpuRpc) { - return; + // + // Originally the flag is 0, but to WAR bug 2909388, add flag + // GPU_TIMEOUT_FLAGS_BYPASS_THREAD_STATE to bypass using threadStateCheckTimeout, + // GPU_TIMEOUT_FLAGS_BYPASS_CPU_YIELD to not wait inside timeout with mutex held. + // + gpuSetTimeout(pGpu, GPU_TIMEOUT_DEFAULT, ¶ms.timeout, + GPU_TIMEOUT_FLAGS_BYPASS_THREAD_STATE | + GPU_TIMEOUT_FLAGS_DEFAULT | GPU_TIMEOUT_FLAGS_BYPASS_CPU_YIELD); + + // + // 2. Wait until we can issue an invalidate. On pre-Turing, wait for space + // in the PRI FIFO. On Turing, check if an invalidate is already in progress. + // + // Set the GFID. + params.gfid = gfid; + + status = kgmmuCheckPendingInvalidates_HAL(pGpu, pKernelGmmu, ¶ms.timeout, params.gfid); + if (status != NV_OK) + { + return; + } } // Trigger an invalidate. @@ -178,16 +183,22 @@ if (!(status == NV_OK || status == NV_ERR_NOT_SUPPORTED)) return; - // 3 and 4. Commit the invalidate and wait for invalidate to complete. - status = kgmmuCommitTlbInvalidate_HAL(pGpu, pKernelGmmu, ¶ms); - if (status != NV_OK) + if (bDoVgpuRpc) + { + } + else { - return; + // 3 and 4. Commit the invalidate and wait for invalidate to complete. + status = kgmmuCommitTlbInvalidate_HAL(pGpu, pKernelGmmu, ¶ms); + if (status != NV_OK) + { + return; + } } while (flushCount--) { - if (kbusFlush_HAL(pGpu, GPU_GET_KERNEL_BUS(pGpu), BUS_FLUSH_VIDEO_MEMORY) == NV_ERR_TIMEOUT) + if (kbusSendSysmembar(pGpu, GPU_GET_KERNEL_BUS(pGpu)) == NV_ERR_TIMEOUT) { break; } @@ -221,7 +232,7 @@ maxFmtVersionSupported = maxFmtVersionSupported < ver ? ver : maxFmtVersionSupported; } } - + switch (maxFmtVersionSupported) { case GMMU_FMT_VERSION_1: @@ -284,7 +295,7 @@ * * @returns The size of a large page in bytes */ -NvU32 +NvU64 kgmmuGetMaxBigPageSize_GM107(KernelGmmu *pKernelGmmu) { if (!kgmmuIsPerVaspaceBigPageEn(pKernelGmmu)) @@ -317,6 +328,7 @@ break; case ADDR_FABRIC_V2: case ADDR_FABRIC_MC: + case ADDR_EGM: aperture = NV_MMU_PTE_APERTURE_PEER_MEMORY; break; case ADDR_FBMEM: diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/kernel/gpu/mmu/arch/pascal/kern_gmmu_gp100.c nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/kernel/gpu/mmu/arch/pascal/kern_gmmu_gp100.c --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/kernel/gpu/mmu/arch/pascal/kern_gmmu_gp100.c 2023-10-25 20:21:15.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/kernel/gpu/mmu/arch/pascal/kern_gmmu_gp100.c 2024-03-05 22:13:41.000000000 +0000 @@ -144,7 +144,7 @@ RmPhysAddr physAdd; NvU32 aperture; NvU32 addrLo; - NvU32 bigPageSize = vaspaceGetBigPageSize(pVAS); + NvU64 bigPageSize = vaspaceGetBigPageSize(pVAS); pPDB = (pParams->bIsClientAdmin) ? vaspaceGetKernelPageDirBase(pVAS, pGpu) : vaspaceGetPageDirBase(pVAS, pGpu); diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/kernel/gpu/mmu/arch/turing/kern_gmmu_fmt_tu10x.c nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/kernel/gpu/mmu/arch/turing/kern_gmmu_fmt_tu10x.c --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/kernel/gpu/mmu/arch/turing/kern_gmmu_fmt_tu10x.c 2023-10-25 20:21:16.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/kernel/gpu/mmu/arch/turing/kern_gmmu_fmt_tu10x.c 2024-03-05 22:13:41.000000000 +0000 @@ -37,7 +37,7 @@ void kgmmuFmtInitPeerPteFld_TU10X(KernelGmmu *pKernelGmmu, GMMU_FMT_PTE *pPte, const NvU32 version) { NV_ASSERT_OR_RETURN_VOID(version == GMMU_FMT_VERSION_2); - + NV_FIELD_DESC64 *pField = &pPte->fldAddrPeer.desc; pPte->fldAddrPeer.shift = NV_MMU_VER2_PTE_ADDRESS_SHIFT; diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/kernel/gpu/mmu/arch/turing/kern_gmmu_tu102.c nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/kernel/gpu/mmu/arch/turing/kern_gmmu_tu102.c --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/kernel/gpu/mmu/arch/turing/kern_gmmu_tu102.c 2023-10-25 20:21:16.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/kernel/gpu/mmu/arch/turing/kern_gmmu_tu102.c 2024-03-05 22:13:41.000000000 +0000 @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 2021-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2021-2024 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -420,7 +420,7 @@ void kgmmuClearNonReplayableFaultIntr_TU102 ( - POBJGPU pGpu, + OBJGPU *pGpu, KernelGmmu *pKernelGmmu, THREAD_STATE_NODE *pThreadState ) @@ -428,3 +428,47 @@ Intr *pIntr = GPU_GET_INTR(pGpu); intrClearLeafVector_HAL(pGpu, pIntr, NV_PFB_PRI_MMU_INT_VECTOR_FAULT_NOTIFY_NON_REPLAYABLE, pThreadState); } + +/*! + * @brief Clear replayable fault interrupt. + * + * @param[in] pGpu OBJGPU pointer + * @param[in] pKernelGmmu KernelGmmu pointer + * @param[in] pThreadState THREAD_STATE_NODE pointer + */ +void +kgmmuClearReplayableFaultIntr_TU102 +( + OBJGPU *pGpu, + KernelGmmu *pKernelGmmu, + THREAD_STATE_NODE *pThreadState +) +{ + Intr *pIntr = GPU_GET_INTR(pGpu); + intrClearLeafVector_HAL(pGpu, pIntr, NV_PFB_PRI_MMU_INT_VECTOR_FAULT_NOTIFY_REPLAYABLE, pThreadState); +} + +NvU32 +kgmmuGetEccCounts_TU102 +( + OBJGPU *pGpu, + KernelGmmu *pKernelGmmu +) +{ + NvU32 mmuCount = 0; + NvU32 regVal; + + // L2TLB + regVal = GPU_REG_RD32(pGpu, NV_PFB_PRI_MMU_L2TLB_ECC_UNCORRECTED_ERR_COUNT); + mmuCount += DRF_VAL(_PFB_PRI_MMU, _L2TLB_ECC, _UNCORRECTED_ERR_COUNT_UNIQUE, regVal); + + // HUBTLB + regVal = GPU_REG_RD32(pGpu, NV_PFB_PRI_MMU_HUBTLB_ECC_UNCORRECTED_ERR_COUNT); + mmuCount += DRF_VAL(_PFB_PRI_MMU, _HUBTLB_ECC, _UNCORRECTED_ERR_COUNT_UNIQUE, regVal); + + // FILLUNIT + regVal = GPU_REG_RD32(pGpu, NV_PFB_PRI_MMU_FILLUNIT_ECC_UNCORRECTED_ERR_COUNT); + mmuCount += DRF_VAL(_PFB_PRI_MMU, _FILLUNIT_ECC, _UNCORRECTED_ERR_COUNT_UNIQUE, regVal); + + return mmuCount; +} diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/kernel/gpu/mmu/arch/volta/kern_gmmu_gv100.c nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/kernel/gpu/mmu/arch/volta/kern_gmmu_gv100.c --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/kernel/gpu/mmu/arch/volta/kern_gmmu_gv100.c 2023-10-25 20:21:16.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/kernel/gpu/mmu/arch/volta/kern_gmmu_gv100.c 2024-03-05 22:13:42.000000000 +0000 @@ -89,7 +89,7 @@ } /*! - * @brief Creates the shadow fault buffer for client handling of non-replayable faults + * @brief Creates the shadow fault buffer for client handling of replayable/non-replayable faults * * @param[in] pGpu * @param[in] pKernelGmmu @@ -99,8 +99,9 @@ NV_STATUS kgmmuClientShadowFaultBufferAlloc_GV100 ( - OBJGPU *pGpu, - KernelGmmu *pKernelGmmu + OBJGPU *pGpu, + KernelGmmu *pKernelGmmu, + FAULT_BUFFER_TYPE index ) { if (IS_VIRTUAL_WITHOUT_SRIOV(pGpu)) @@ -112,7 +113,7 @@ NV_ASSERT_OR_RETURN(0, NV_ERR_INVALID_STATE); } - return kgmmuClientShadowFaultBufferNonreplayableAllocate(pGpu, pKernelGmmu); + return kgmmuClientShadowFaultBufferAllocate(pGpu, pKernelGmmu, index); } /*! @@ -126,14 +127,15 @@ NV_STATUS kgmmuClientShadowFaultBufferFree_GV100 ( - OBJGPU *pGpu, - KernelGmmu *pKernelGmmu + OBJGPU *pGpu, + KernelGmmu *pKernelGmmu, + FAULT_BUFFER_TYPE index ) { if (IS_VIRTUAL_WITHOUT_SRIOV(pGpu)) return NV_OK; - return kgmmuClientShadowFaultBufferNonreplayableDestroy(pGpu, pKernelGmmu); + return kgmmuClientShadowFaultBufferDestroy(pGpu, pKernelGmmu, index); } /*! @@ -472,8 +474,12 @@ MODS_ARCH_ERROR_PRINTF("MMU Fault Buffer overflow detected\n"); rmStatus = notifyEvents(pGpu, *ppEventNotification, NVC369_NOTIFIER_MMU_FAULT_ERROR, 0, 0, NV_OK, NV_OS_WRITE_THEN_AWAKEN); - if (rmStatus != NV_OK) - return rmStatus; + // + // Mods will check the error and clear error status. As Mods uses Async event + // clearing the error in RM will cause a race with Mods + // + if (RMCFG_FEATURE_MODS_FEATURES) + return rmStatus; } krcBreakpoint(GPU_GET_KERNEL_RC(pGpu)); @@ -482,6 +488,8 @@ faultStatus = FLD_SET_DRF(_PFB_PRI, _MMU_FAULT_STATUS, _NON_REPLAYABLE_OVERFLOW, _RESET, faultStatus); kgmmuWriteMmuFaultStatus_HAL(pGpu, pKernelGmmu, faultStatus); + + gpuMarkDeviceForReset(pGpu); return rmStatus; } diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/kernel/gpu/mmu/bar2_walk.c nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/kernel/gpu/mmu/bar2_walk.c --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/kernel/gpu/mmu/bar2_walk.c 2023-10-25 20:21:16.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/kernel/gpu/mmu/bar2_walk.c 2024-03-05 22:13:42.000000000 +0000 @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 2013-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2013-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -24,6 +24,7 @@ #include "gpu/gpu.h" #include "gpu/mmu/kern_gmmu.h" #include "gpu/mem_sys/kern_mem_sys.h" +#include "gpu/mem_mgr/mem_mgr.h" #include "gpu/nvlink/kernel_nvlink.h" #include "gpu/bus/kern_bus.h" #include "mem_mgr/gpu_vaspace.h" @@ -180,7 +181,33 @@ // Determine how to write the entry value. if (memdescGetAddressSpace(pMemDesc) == ADDR_FBMEM) { - if (pKernelBus->bar2[gfid].bBootstrap) + if (kbusIsBarAccessBlocked(pKernelBus)) + { + MemoryManager *pMemoryManager = GPU_GET_MEMORY_MANAGER(pGpu); + TRANSFER_SURFACE surf = {0}; + NvU32 sizeOfEntries; + + NV_ASSERT_OR_RETURN_VOID(pKernelBus->virtualBar2[gfid].pPageLevels == NULL); + + surf.pMemDesc = pMemDesc; + surf.offset = entryIndexLo * pLevelFmt->entrySize; + + sizeOfEntries = (entryIndexHi - entryIndexLo + 1) * pLevelFmt->entrySize; + + pMap = memmgrMemBeginTransfer(pMemoryManager, &surf, sizeOfEntries, + TRANSFER_FLAGS_SHADOW_ALLOC); + + for (entryIndex = entryIndexLo; entryIndex <= entryIndexHi; entryIndex++) + { + NvU32 index = (entryIndex - entryIndexLo) * pLevelFmt->entrySize; + portMemCopy(&pMap[index], pLevelFmt->entrySize, + entryValue.v8, pLevelFmt->entrySize); + } + + memmgrMemEndTransfer(pMemoryManager, &surf, sizeOfEntries, + TRANSFER_FLAGS_SHADOW_ALLOC); + } + else if (pKernelBus->bar2[gfid].bBootstrap) { if (kbusIsPhysicalBar2InitPagetableEnabled(pKernelBus)) { @@ -357,22 +384,38 @@ entryOffset = entryIndex * pLevelFmt->entrySize; - // If we are setting up BAR2, we need special handling. - if (pKernelBus->bar2[gfid].bBootstrap) + if (pKernelBus->PDEBAR2Aperture == ADDR_FBMEM) { - entryStart = memdescGetPhysAddr(pMemDesc, FORCE_VMMU_TRANSLATION(pMemDesc, AT_GPU), entryOffset); - sizeInDWord = (NvU32)NV_CEIL(pLevelFmt->entrySize, sizeof(NvU32)); + if (kbusIsBarAccessBlocked(pKernelBus)) + { + MemoryManager *pMemoryManager = GPU_GET_MEMORY_MANAGER(pGpu); + TRANSFER_SURFACE surf = {0}; + + NV_ASSERT_OR_RETURN(pKernelBus->virtualBar2[gfid].pPageLevels == NULL, + NV_FALSE); - for (i = 0; i < sizeInDWord; i++) + surf.pMemDesc = pMemDesc; + surf.offset = entryOffset; + + NV_ASSERT_OR_RETURN(memmgrMemWrite(pMemoryManager, &surf, + entry.v8, pLevelFmt->entrySize, + TRANSFER_FLAGS_NONE) == NV_OK, + NV_FALSE); + } + // If we are setting up BAR2, we need special handling. + else if (pKernelBus->bar2[gfid].bBootstrap) { - if (ADDR_FBMEM == pKernelBus->PDEBAR2Aperture) + if (kbusIsPhysicalBar2InitPagetableEnabled(pKernelBus)) { - if (kbusIsPhysicalBar2InitPagetableEnabled(pKernelBus)) - { - pMap = kbusCpuOffsetInBar2WindowGet(pGpu, pKernelBus, pMemDesc); - portMemCopy(pMap + entryOffset, pLevelFmt->entrySize, entry.v8, pLevelFmt->entrySize); - } - else + pMap = kbusCpuOffsetInBar2WindowGet(pGpu, pKernelBus, pMemDesc); + portMemCopy(pMap + entryOffset, pLevelFmt->entrySize, entry.v8, pLevelFmt->entrySize); + } + else + { + entryStart = memdescGetPhysAddr(pMemDesc, AT_PA, entryOffset); + sizeInDWord = (NvU32)NV_CEIL(pLevelFmt->entrySize, sizeof(NvU32)); + + for (i = 0; i < sizeInDWord; i++) { status = kbusMemAccessBar0Window_HAL(pGpu, pKernelBus, (entryStart + (sizeof(NvU32) * i)), @@ -383,24 +426,9 @@ NV_ASSERT_OR_RETURN(NV_OK == status, NV_FALSE); } } - else - { - // Plain old memmap. - status = memdescMapOld(pMemDesc, 0, - pMemDesc->Size, - NV_TRUE, // kernel, - NV_PROTECT_READ_WRITE, - (void **)&pMap, - &pPriv); - NV_ASSERT_OR_RETURN(NV_OK == status, NV_FALSE); - portMemCopy(pMap + entryOffset, pLevelFmt->entrySize, entry.v8, pLevelFmt->entrySize); - memdescUnmapOld(pMemDesc, 1, 0, pMap, pPriv); - } } - } - else if (pKernelBus->bar2[gfid].bMigrating || IS_GFID_VF(gfid)) - { - if (ADDR_FBMEM == pKernelBus->PDEBAR2Aperture) + else if (pKernelBus->bar2[gfid].bMigrating || IS_GFID_VF(gfid) || + KBUS_BAR0_PRAMIN_DISABLED(pGpu)) { NV_ASSERT(NULL != pKernelBus->virtualBar2[gfid].pPageLevels); @@ -412,12 +440,25 @@ } else { - NV_ASSERT(0); // Page level instances in sysmem don't need migration. + NV_ASSERT_OR_RETURN(0, NV_FALSE); // Not yet supported. } } + else if (pKernelBus->PDEBAR2Aperture == ADDR_SYSMEM) + { + // Plain old memmap. + status = memdescMapOld(pMemDesc, 0, + pMemDesc->Size, + NV_TRUE, // kernel, + NV_PROTECT_READ_WRITE, + (void **)&pMap, + &pPriv); + NV_ASSERT_OR_RETURN(NV_OK == status, NV_FALSE); + portMemCopy(pMap + entryOffset, pLevelFmt->entrySize, entry.v8, pLevelFmt->entrySize); + memdescUnmapOld(pMemDesc, 1, 0, pMap, pPriv); + } else { - NV_ASSERT(0); // Not yet supported. + NV_ASSERT_OR_RETURN(0, NV_FALSE); // only SYSMEM and FBMEM are supported. } return NV_TRUE; @@ -487,7 +528,9 @@ } // Specify which Page Level we are initializing. - if (pKernelBus->bar2[gfid].bBootstrap || pKernelBus->bar2[gfid].bMigrating || IS_GFID_VF(gfid)) + if (pKernelBus->bar2[gfid].bBootstrap || pKernelBus->bar2[gfid].bMigrating || + IS_GFID_VF(gfid) || KBUS_BAR0_PRAMIN_DISABLED(pGpu) || + kbusIsBarAccessBlocked(pKernelBus)) { if (pLevelFmt == pKernelBus->bar2[gfid].pFmt->pRoot) { @@ -521,7 +564,9 @@ } else { - NV_ASSERT(pKernelBus->bar2[gfid].bBootstrap || IS_GFID_VF(gfid)); + NV_ASSERT(pKernelBus->bar2[gfid].bBootstrap || IS_GFID_VF(gfid) || + KBUS_BAR0_PRAMIN_DISABLED(pGpu) || + kbusIsBarAccessBlocked(pKernelBus)); pdeBase = pKernelBus->bar2[gfid].pdeBase; pteBase = pKernelBus->bar2[gfid].pteBase; } @@ -600,12 +645,16 @@ } else { - NV_ASSERT(pKernelBus->bar2[gfid].bBootstrap || IS_GFID_VF(gfid)); + NV_ASSERT(pKernelBus->bar2[gfid].bBootstrap || IS_GFID_VF(gfid) || + KBUS_BAR0_PRAMIN_DISABLED(pGpu) || + kbusIsBarAccessBlocked(pKernelBus)); pKernelBus->bar2[gfid].pdeBase = memdescGetPhysAddr(pMemDesc, AT_GPU, 0); pKernelBus->bar2[gfid].pPDEMemDesc = pMemDesc; } } - if (pKernelBus->bar2[gfid].bBootstrap || pKernelBus->bar2[gfid].bMigrating || IS_GFID_VF(gfid)) + if (pKernelBus->bar2[gfid].bBootstrap || pKernelBus->bar2[gfid].bMigrating || + IS_GFID_VF(gfid) || KBUS_BAR0_PRAMIN_DISABLED(pGpu) || + kbusIsBarAccessBlocked(pKernelBus)) { pKernelBus->bar2[gfid].pageDirInit++; } @@ -680,13 +729,17 @@ } else { - NV_ASSERT(pKernelBus->bar2[gfid].bBootstrap || IS_GFID_VF(gfid)); + NV_ASSERT(pKernelBus->bar2[gfid].bBootstrap || IS_GFID_VF(gfid) || + KBUS_BAR0_PRAMIN_DISABLED(pGpu) || + kbusIsBarAccessBlocked(pKernelBus)); pKernelBus->bar2[gfid].pteBase = memdescGetPhysAddr(pMemDesc, AT_GPU, 0); } pKernelBus->virtualBar2[gfid].pPTEMemDesc = pMemDesc; } - if (pKernelBus->bar2[gfid].bBootstrap || pKernelBus->bar2[gfid].bMigrating || IS_GFID_VF(gfid)) + if (pKernelBus->bar2[gfid].bBootstrap || pKernelBus->bar2[gfid].bMigrating || + IS_GFID_VF(gfid) || KBUS_BAR0_PRAMIN_DISABLED(pGpu) || + kbusIsBarAccessBlocked(pKernelBus)) { pKernelBus->bar2[gfid].pageTblInit++; } @@ -750,7 +803,29 @@ pStagingBufferMapping = &pStagingDescMapping[firstEntryOffset % tableSize]; - if (pKernelBus->bar2[gfid].bBootstrap) + if (kbusIsBarAccessBlocked(pKernelBus)) + { + MemoryManager *pMemoryManager = GPU_GET_MEMORY_MANAGER(pGpu); + TRANSFER_SURFACE surf = {0}; + + NV_ASSERT_OR_RETURN_VOID(pKernelBus->virtualBar2[gfid].pPageLevels == NULL); + + surf.pMemDesc = pOutputBufferDesc; + surf.offset = firstEntryOffset; + + pOutputBufferMapping = memmgrMemBeginTransfer(pMemoryManager, &surf, + entryRangeSize, + TRANSFER_FLAGS_SHADOW_ALLOC); + + portMemCopy(pOutputBufferMapping, entryRangeSize, + pStagingBufferMapping, entryRangeSize); + + memmgrMemEndTransfer(pMemoryManager, &surf, entryRangeSize, + TRANSFER_FLAGS_SHADOW_ALLOC); + + goto unmap_and_exit; + } + else if (pKernelBus->bar2[gfid].bBootstrap) { if (kbusIsPhysicalBar2InitPagetableEnabled(pKernelBus)) { @@ -807,6 +882,7 @@ pStagingBufferMapping, entryRangeSize); +unmap_and_exit: memdescUnmapOld(pStagingBufferDesc, NV_TRUE, 0, pStagingDescMapping, pPriv); if (bRestore) diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/kernel/gpu/mmu/fault_buffer_ctrl.c nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/kernel/gpu/mmu/fault_buffer_ctrl.c --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/kernel/gpu/mmu/fault_buffer_ctrl.c 2023-10-25 20:21:16.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/kernel/gpu/mmu/fault_buffer_ctrl.c 2024-03-05 22:13:42.000000000 +0000 @@ -57,7 +57,7 @@ OBJGPU *pGpu = GPU_RES_GET_GPU(pMmuFaultBuffer); KernelGmmu *pKernelGmmu = GPU_GET_KERNEL_GMMU(pGpu); - return kgmmuGetFaultRegisterMappings_HAL(pGpu, pKernelGmmu, REPLAYABLE_FAULT_BUFFER, + return kgmmuGetFaultRegisterMappings_HAL(pGpu, pKernelGmmu, pParams->faultBufferType, &pParams->pFaultBufferGet, &pParams->pFaultBufferPut, &pParams->pFaultBufferInfo, diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/kernel/gpu/mmu/gmmu_walk.c nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/kernel/gpu/mmu/gmmu_walk.c --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/kernel/gpu/mmu/gmmu_walk.c 2023-10-25 20:21:16.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/kernel/gpu/mmu/gmmu_walk.c 2024-03-05 22:13:42.000000000 +0000 @@ -285,7 +285,7 @@ // Add memList end entry. memPoolList[memPoolListCount++] = ADDR_UNKNOWN; - NV_ASSERT(memPoolListCount <= NV_ARRAY_ELEMENTS32(memPoolList)); + NV_ASSERT(memPoolListCount <= NV_ARRAY_ELEMENTS(memPoolList)); // MEMDESC flags memDescFlags = MEMDESC_FLAGS_LOCKLESS_SYSMEM_ALLOC | diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/kernel/gpu/mmu/kern_gmmu.c nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/kernel/gpu/mmu/kern_gmmu.c --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/kernel/gpu/mmu/kern_gmmu.c 2023-10-25 20:21:16.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/kernel/gpu/mmu/kern_gmmu.c 2024-03-05 22:13:42.000000000 +0000 @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 2021-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2021-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -45,6 +45,7 @@ #include "vgpu/rpc.h" #include "kernel/gpu/intr/engine_idx.h" +#include "kernel/gpu/conf_compute/ccsl.h" static void _kgmmuInitRegistryOverrides(OBJGPU *pGpu, KernelGmmu *pKernelGmmu); @@ -184,6 +185,10 @@ } status = _kgmmuInitStaticInfo(pGpu, pKernelGmmu); + if (status != NV_OK) + { + return status; + } return status; } @@ -191,15 +196,15 @@ static NV_STATUS _kgmmuCreateGlobalVASpace ( - POBJGPU pGpu, + OBJGPU *pGpu, KernelGmmu *pKernelGmmu, NvU32 flags ) { NvU32 constructFlags = VASPACE_FLAGS_NONE; - POBJVASPACE pGlobalVAS = NULL; + OBJVASPACE *pGlobalVAS = NULL; NV_STATUS rmStatus; - POBJGPUGRP pGpuGrp = NULL; + OBJGPUGRP *pGpuGrp = NULL; // Bail out early on sleep/suspend cases if (flags & GPU_STATE_FLAGS_PRESERVING) @@ -235,12 +240,12 @@ static NV_STATUS _kgmmuDestroyGlobalVASpace ( - POBJGPU pGpu, + OBJGPU *pGpu, KernelGmmu *pKernelGmmu, NvU32 flags ) { - POBJGPUGRP pGpuGrp = NULL; + OBJGPUGRP *pGpuGrp = NULL; if (flags & GPU_STATE_FLAGS_PRESERVING) return NV_OK; @@ -926,23 +931,37 @@ { NvU32 faultBufferAddrSpace = ADDR_UNKNOWN; NvU32 faultBufferAttr = 0; + NvBool bAllocInVidmem = NV_FALSE; + + bAllocInVidmem = gpuIsCCFeatureEnabled(pGpu); NV_ASSERT_OR_RETURN((index < NUM_FAULT_BUFFERS), NV_ERR_INVALID_ARGUMENT); if (index == NON_REPLAYABLE_FAULT_BUFFER) { - faultBufferAddrSpace = ADDR_SYSMEM; - faultBufferAttr = NV_MEMORY_CACHED; + faultBufferAddrSpace = bAllocInVidmem ? ADDR_FBMEM : ADDR_SYSMEM; + faultBufferAttr = bAllocInVidmem ? NV_MEMORY_UNCACHED : NV_MEMORY_CACHED; memdescOverrideInstLoc(DRF_VAL(_REG_STR_RM, _INST_LOC_3, _UVM_FAULT_BUFFER_NONREPLAYABLE, pGpu->instLocOverrides3), "UVM non-replayable fault", &faultBufferAddrSpace, &faultBufferAttr); } else if (index == REPLAYABLE_FAULT_BUFFER) { - faultBufferAddrSpace = ADDR_SYSMEM; - faultBufferAttr = NV_MEMORY_CACHED; + faultBufferAddrSpace = bAllocInVidmem ? ADDR_FBMEM : ADDR_SYSMEM; + faultBufferAttr = bAllocInVidmem ? NV_MEMORY_UNCACHED : NV_MEMORY_CACHED; memdescOverrideInstLoc(DRF_VAL(_REG_STR_RM, _INST_LOC_4, _UVM_FAULT_BUFFER_REPLAYABLE, pGpu->instLocOverrides4), "UVM replayable fault", &faultBufferAddrSpace, &faultBufferAttr); } + // + // Whenever Hopper CC is enabled, HW requires both replayable and non-replayable + // fault buffers to be in CPR vidmem. It would be illegal to allocate the buffers + // in any other aperture + // + if (bAllocInVidmem && (faultBufferAddrSpace == ADDR_SYSMEM)) + { + NV_PRINTF(LEVEL_ERROR, "Fault buffers must be in CPR vidmem when HCC is enabled\n"); + NV_ASSERT(0); + return NV_ERR_INVALID_ARGUMENT; + } if (pFaultBufferAddrSpace != NULL) { @@ -983,9 +1002,13 @@ return status; } - if (IS_VIRTUAL(pGpu) && gpuIsWarBug200577889SriovHeavyEnabled(pGpu)) + if ((IS_VIRTUAL(pGpu) && gpuIsWarBug200577889SriovHeavyEnabled(pGpu)) + || gpuIsCCFeatureEnabled(pGpu) + ) { // Allocate contiguous fault buffers for SR-IOV Heavy + // Fault buffers get allocated in CPR vidmem when Hopper CC is enabled + // We're almost assured to get contiguous allocations in vidmem isContiguous = NV_TRUE; } @@ -1009,6 +1032,8 @@ memdescSetGpuCacheAttrib(pMemDesc, NV_MEMORY_UNCACHED); } + memdescSetPageSize(pMemDesc, AT_GPU, RM_PAGE_SIZE); + *ppMemDesc = pMemDesc; return NV_OK; @@ -1185,6 +1210,7 @@ pKernelGmmu->mmuFaultBuffer[GPU_GFID_PF].hFaultBufferClient = hClient; pKernelGmmu->mmuFaultBuffer[GPU_GFID_PF].hFaultBufferObject = hObject; + pKernelGmmu->mmuFaultBuffer[GPU_GFID_PF].faultBufferGenerationCounter = 0; return NV_OK; } @@ -1355,20 +1381,37 @@ static NV_STATUS _kgmmuClientShadowFaultBufferQueueAllocate ( - OBJGPU *pGpu, - KernelGmmu *pKernelGmmu + OBJGPU *pGpu, + KernelGmmu *pKernelGmmu, + FAULT_BUFFER_TYPE index ) { NV_STATUS status; GMMU_CLIENT_SHADOW_FAULT_BUFFER *pClientShadowFaultBuffer; MEMORY_DESCRIPTOR *pQueueMemDesc; + NvU64 flags = MEMDESC_FLAGS_NONE; - pClientShadowFaultBuffer = &pKernelGmmu->mmuFaultBuffer[GPU_GFID_PF].clientShadowFaultBuffer; + // + // On systems with SEV enabled, the client shadow buffers should be allocated + // in unprotected sysmem as GSP will be writing the fault packets to these + // buffers. Since GSP will be encrypting the fault packets, we don't risk + // leaking any information + // + flags |= MEMDESC_FLAGS_ALLOC_IN_UNPROTECTED_MEMORY; + + // + // Shadow fault buffers are not implemented using circular queues when + // Hopper CC is enabled + // + if (gpuIsCCFeatureEnabled(pGpu) && gpuIsGspOwnedFaultBuffersEnabled(pGpu)) + return NV_OK; + + pClientShadowFaultBuffer = &pKernelGmmu->mmuFaultBuffer[GPU_GFID_PF].clientShadowFaultBuffer[index]; status = memdescCreate(&pQueueMemDesc, pGpu, sizeof(GMMU_SHADOW_FAULT_BUF), RM_PAGE_SIZE, NV_TRUE, ADDR_SYSMEM, NV_MEMORY_CACHED, - MEMDESC_FLAGS_NONE); + flags); if (status != NV_OK) { return status; @@ -1403,15 +1446,23 @@ void kgmmuClientShadowFaultBufferQueueDestroy_IMPL ( - OBJGPU *pGpu, - KernelGmmu *pKernelGmmu, - NvBool bFreeQueue + OBJGPU *pGpu, + KernelGmmu *pKernelGmmu, + NvBool bFreeQueue, + FAULT_BUFFER_TYPE index ) { GMMU_CLIENT_SHADOW_FAULT_BUFFER *pClientShadowFaultBuffer; MEMORY_DESCRIPTOR *pQueueMemDesc; - pClientShadowFaultBuffer = &pKernelGmmu->mmuFaultBuffer[GPU_GFID_PF].clientShadowFaultBuffer; + // + // Shadow fault buffers are not implemented using circular queues when + // Hopper CC is enabled. So, there is nothing to free here + // + if (gpuIsCCFeatureEnabled(pGpu) && gpuIsGspOwnedFaultBuffersEnabled(pGpu)) + return; + + pClientShadowFaultBuffer = &pKernelGmmu->mmuFaultBuffer[GPU_GFID_PF].clientShadowFaultBuffer[index]; pQueueMemDesc = pClientShadowFaultBuffer->pQueueMemDesc; @@ -1429,23 +1480,35 @@ static NV_STATUS _kgmmuClientShadowFaultBufferPagesAllocate ( - OBJGPU *pGpu, - KernelGmmu *pKernelGmmu, - NvU32 shadowFaultBufferSize + OBJGPU *pGpu, + KernelGmmu *pKernelGmmu, + NvU32 shadowFaultBufferSize, + NvU32 shadowFaultBufferMetadataSize, + FAULT_BUFFER_TYPE index ) { NV_STATUS status; GMMU_CLIENT_SHADOW_FAULT_BUFFER *pClientShadowFaultBuffer; MEMORY_DESCRIPTOR *pMemDesc; + NvU64 flags = MEMDESC_FLAGS_NONE; + NvU32 shadowFaultBufferSizeTotal; - pClientShadowFaultBuffer = &pKernelGmmu->mmuFaultBuffer[GPU_GFID_PF].clientShadowFaultBuffer; + // + // On systems with SEV enabled, the client shadow buffers should be allocated + // in unprotected sysmem as GSP will be writing the fault packets to these + // buffers. Since GSP will be encrypting the fault packets, we don't risk + // leaking any information + // + flags |= MEMDESC_FLAGS_ALLOC_IN_UNPROTECTED_MEMORY; - shadowFaultBufferSize = RM_PAGE_ALIGN_UP(shadowFaultBufferSize); + pClientShadowFaultBuffer = &pKernelGmmu->mmuFaultBuffer[GPU_GFID_PF].clientShadowFaultBuffer[index]; + + shadowFaultBufferSizeTotal = RM_PAGE_ALIGN_UP(shadowFaultBufferSize) + RM_PAGE_ALIGN_UP(shadowFaultBufferMetadataSize); status = memdescCreate(&pMemDesc, pGpu, - shadowFaultBufferSize, RM_PAGE_SIZE, + shadowFaultBufferSizeTotal, RM_PAGE_SIZE, NV_FALSE, ADDR_SYSMEM, NV_MEMORY_CACHED, - MEMDESC_FLAGS_NONE); + flags); if (status != NV_OK) { return status; @@ -1470,6 +1533,9 @@ return status; } + pClientShadowFaultBuffer->pFaultBufferMetadataAddress = + ((NvP64)(((NvU64) pClientShadowFaultBuffer->pBufferAddress) + + RM_PAGE_ALIGN_UP(shadowFaultBufferSize))); pClientShadowFaultBuffer->pBufferMemDesc = pMemDesc; return NV_OK; @@ -1478,9 +1544,10 @@ void kgmmuClientShadowFaultBufferPagesDestroy_IMPL ( - OBJGPU *pGpu, - KernelGmmu *pKernelGmmu, - NvBool bFreePages + OBJGPU *pGpu, + KernelGmmu *pKernelGmmu, + NvBool bFreePages, + FAULT_BUFFER_TYPE index ) { MEMORY_DESCRIPTOR *pMemDesc; @@ -1488,7 +1555,7 @@ GMMU_FAULT_BUFFER_PAGE *pBufferPage; NvU32 i; - pClientShadowFaultBuffer = &pKernelGmmu->mmuFaultBuffer[GPU_GFID_PF].clientShadowFaultBuffer; + pClientShadowFaultBuffer = &pKernelGmmu->mmuFaultBuffer[GPU_GFID_PF].clientShadowFaultBuffer[index]; pMemDesc = pClientShadowFaultBuffer->pBufferMemDesc; if (bFreePages) @@ -1517,11 +1584,12 @@ NV_STATUS kgmmuClientShadowFaultBufferRegister_IMPL ( - OBJGPU *pGpu, - KernelGmmu *pKernelGmmu + OBJGPU *pGpu, + KernelGmmu *pKernelGmmu, + FAULT_BUFFER_TYPE index ) { - NV_STATUS status; + NV_STATUS status = NV_OK; struct GMMU_FAULT_BUFFER *pFaultBuffer; GMMU_CLIENT_SHADOW_FAULT_BUFFER *pClientShadowFaultBuffer; GMMU_SHADOW_FAULT_BUF *pQueue; @@ -1529,29 +1597,53 @@ RmPhysAddr shadowFaultBufferQueuePhysAddr; NvU32 queueCapacity, numBufferPages; NvU32 faultBufferSize; + NvU32 shadowFaultBufferMetadataSize; const NV2080_CTRL_INTERNAL_GMMU_GET_STATIC_INFO_PARAMS *pStaticInfo = kgmmuGetStaticInfo(pGpu, pKernelGmmu); + NvBool bQueueAllocated = NV_FALSE; pFaultBuffer = &pKernelGmmu->mmuFaultBuffer[GPU_GFID_PF]; - pClientShadowFaultBuffer = &pFaultBuffer->clientShadowFaultBuffer; - faultBufferSize = pStaticInfo->nonReplayableFaultBufferSize; + pClientShadowFaultBuffer = &pFaultBuffer->clientShadowFaultBuffer[index]; - pQueue = KERNEL_POINTER_FROM_NvP64(GMMU_SHADOW_FAULT_BUF *, - pClientShadowFaultBuffer->pQueueAddress); - queueCapacity = faultBufferSize / NVC369_BUF_SIZE; + if (index == NON_REPLAYABLE_FAULT_BUFFER) + { + faultBufferSize = pStaticInfo->nonReplayableFaultBufferSize; + shadowFaultBufferMetadataSize = pStaticInfo->nonReplayableShadowFaultBufferMetadataSize; + } + else if (index == REPLAYABLE_FAULT_BUFFER) + { + faultBufferSize = pStaticInfo->replayableFaultBufferSize; + shadowFaultBufferMetadataSize = pStaticInfo->replayableShadowFaultBufferMetadataSize; + } + else + { + NV_ASSERT_OR_RETURN(0, NV_ERR_INVALID_ARGUMENT); + } - status = queueInitNonManaged(pQueue, queueCapacity); - if (status != NV_OK) + // + // We don't use circular queues for shadow fault buffers when Hopper + // CC is enabled + // + if (!gpuIsCCFeatureEnabled(pGpu) || !gpuIsGspOwnedFaultBuffersEnabled(pGpu)) { - return status; + pQueue = KERNEL_POINTER_FROM_NvP64(GMMU_SHADOW_FAULT_BUF *, + pClientShadowFaultBuffer->pQueueAddress); + queueCapacity = faultBufferSize / NVC369_BUF_SIZE; + + status = queueInitNonManaged(pQueue, queueCapacity); + if (status != NV_OK) + { + return status; + } + bQueueAllocated = NV_TRUE; } if (!IS_GSP_CLIENT(pGpu)) { portSyncSpinlockAcquire(pFaultBuffer->pShadowFaultBufLock); - if (pFaultBuffer->pClientShadowFaultBuffer == NULL) + if (pFaultBuffer->pClientShadowFaultBuffer[index] == NULL) { - pFaultBuffer->pClientShadowFaultBuffer = pClientShadowFaultBuffer; + pFaultBuffer->pClientShadowFaultBuffer[index] = pClientShadowFaultBuffer; } else { @@ -1562,7 +1654,8 @@ if (status != NV_OK) { - queueDestroy(pQueue); + if (bQueueAllocated) + queueDestroy(pQueue); return status; } } @@ -1574,7 +1667,8 @@ pParams = portMemAllocNonPaged(sizeof(*pParams)); if (pParams == NULL) { - queueDestroy(pQueue); + if (bQueueAllocated) + queueDestroy(pQueue); return NV_ERR_NO_MEMORY; } portMemSet(pParams, 0, sizeof(*pParams)); @@ -1584,20 +1678,33 @@ if (numBufferPages > NV_ARRAY_ELEMENTS(pParams->shadowFaultBufferPteArray)) { portMemFree(pParams); - queueDestroy(pQueue); + if (bQueueAllocated) + queueDestroy(pQueue); return NV_ERR_BUFFER_TOO_SMALL; } - shadowFaultBufferQueuePhysAddr = memdescGetPhysAddr(pClientShadowFaultBuffer->pQueueMemDesc, - AT_GPU, 0); - memdescGetPhysAddrs(pBufferMemDesc, AT_GPU, 0, RM_PAGE_SIZE, numBufferPages, pParams->shadowFaultBufferPteArray); - pParams->shadowFaultBufferQueuePhysAddr = shadowFaultBufferQueuePhysAddr; - pParams->shadowFaultBufferSize = faultBufferSize; + if (!gpuIsCCFeatureEnabled(pGpu) || !gpuIsGspOwnedFaultBuffersEnabled(pGpu)) + { + shadowFaultBufferQueuePhysAddr = memdescGetPhysAddr(pClientShadowFaultBuffer->pQueueMemDesc, + AT_GPU, 0); + pParams->shadowFaultBufferQueuePhysAddr = shadowFaultBufferQueuePhysAddr; + } + pParams->shadowFaultBufferSize = faultBufferSize; + pParams->shadowFaultBufferMetadataSize = shadowFaultBufferMetadataSize; + pParams->shadowFaultBufferType = (index == NON_REPLAYABLE_FAULT_BUFFER) ? + NV2080_CTRL_FAULT_BUFFER_NON_REPLAYABLE : + NV2080_CTRL_FAULT_BUFFER_REPLAYABLE; + + if (gpuIsCCFeatureEnabled(pGpu) && gpuIsGspOwnedFaultBuffersEnabled(pGpu) && index == REPLAYABLE_FAULT_BUFFER) + { + pParams->faultBufferSharedMemoryPhysAddr = memdescGetPhysAddr(pClientShadowFaultBuffer->pFaultBufferSharedMemDesc, + AT_GPU, 0); + } status = pRmApi->Control(pRmApi, pGpu->hInternalClient, @@ -1608,11 +1715,12 @@ portMemFree(pParams); if (status != NV_OK) { - queueDestroy(pQueue); + if (bQueueAllocated) + queueDestroy(pQueue); return status; } - pFaultBuffer->pClientShadowFaultBuffer = pClientShadowFaultBuffer; + pFaultBuffer->pClientShadowFaultBuffer[index] = pClientShadowFaultBuffer; } return NV_OK; @@ -1621,8 +1729,9 @@ void kgmmuClientShadowFaultBufferUnregister_IMPL ( - OBJGPU *pGpu, - KernelGmmu *pKernelGmmu + OBJGPU *pGpu, + KernelGmmu *pKernelGmmu, + FAULT_BUFFER_TYPE index ) { NV_STATUS status = NV_OK; @@ -1636,52 +1745,67 @@ { portSyncSpinlockAcquire(pFaultBuffer->pShadowFaultBufLock); - pFaultBuffer->pClientShadowFaultBuffer = NULL; + pFaultBuffer->pClientShadowFaultBuffer[index] = NULL; portSyncSpinlockRelease(pFaultBuffer->pShadowFaultBufLock); } else { RM_API *pRmApi = GPU_GET_PHYSICAL_RMAPI(pGpu); + NV2080_CTRL_INTERNAL_GMMU_UNREGISTER_CLIENT_SHADOW_FAULT_BUFFER_PARAMS params; + + portMemSet(¶ms, 0, sizeof(params)); + + params.shadowFaultBufferType = (index == NON_REPLAYABLE_FAULT_BUFFER) ? + NV2080_CTRL_FAULT_BUFFER_NON_REPLAYABLE : + NV2080_CTRL_FAULT_BUFFER_REPLAYABLE; status = pRmApi->Control(pRmApi, pGpu->hInternalClient, pGpu->hInternalSubdevice, NV2080_CTRL_CMD_INTERNAL_GMMU_UNREGISTER_CLIENT_SHADOW_FAULT_BUFFER, - NULL, 0); + ¶ms, sizeof(params)); if (status != NV_OK) { NV_PRINTF(LEVEL_ERROR, - "Unregistering Replayable Fault buffer failed (status=0x%08x), proceeding...\n", + "Unregistering %s fault buffer failed (status=0x%08x), proceeding...\n", + (index == NON_REPLAYABLE_FAULT_BUFFER) ? "non-replayable" : "replayable", status); } - pFaultBuffer->pClientShadowFaultBuffer = NULL; + pFaultBuffer->pClientShadowFaultBuffer[index] = NULL; } - pClientShadowFaultBuffer = &pFaultBuffer->clientShadowFaultBuffer; - pQueue = KERNEL_POINTER_FROM_NvP64(GMMU_SHADOW_FAULT_BUF *, - pClientShadowFaultBuffer->pQueueAddress); - queueDestroy(pQueue); + if (!gpuIsCCFeatureEnabled(pGpu) || !gpuIsGspOwnedFaultBuffersEnabled(pGpu)) + { + pClientShadowFaultBuffer = &pFaultBuffer->clientShadowFaultBuffer[index]; + pQueue = KERNEL_POINTER_FROM_NvP64(GMMU_SHADOW_FAULT_BUF *, + pClientShadowFaultBuffer->pQueueAddress); + queueDestroy(pQueue); + } } /*! - * @brief Creates shadow fault buffer for client handling of non-replayable + * @brief Creates shadow fault buffer for client handling of replayable/non-replayable * faults in the CPU-RM, and registers it in the GSP-RM. * * @param[in] pGpu * @param[in] pKernelGmmu + * @param[in] index Replayable or non-replayable fault buffer * * @returns */ NV_STATUS -kgmmuClientShadowFaultBufferNonreplayableAllocate_IMPL +kgmmuClientShadowFaultBufferAllocate_IMPL ( - OBJGPU *pGpu, - KernelGmmu *pKernelGmmu + OBJGPU *pGpu, + KernelGmmu *pKernelGmmu, + FAULT_BUFFER_TYPE index ) { NV_STATUS status; const NV2080_CTRL_INTERNAL_GMMU_GET_STATIC_INFO_PARAMS *pStaticInfo = kgmmuGetStaticInfo(pGpu, pKernelGmmu); + NvU32 faultBufferSize; + NvU32 shadowFaultBufferMetadataSize; ct_assert((RM_PAGE_SIZE % sizeof(struct GMMU_FAULT_PACKET)) == 0); @@ -1689,31 +1813,59 @@ NV_ASSERT_OR_RETURN(pStaticInfo->nonReplayableFaultBufferSize != 0, NV_ERR_INVALID_STATE); - status = _kgmmuClientShadowFaultBufferQueueAllocate(pGpu, pKernelGmmu); + if (index == NON_REPLAYABLE_FAULT_BUFFER) + { + faultBufferSize = pStaticInfo->nonReplayableFaultBufferSize; + shadowFaultBufferMetadataSize = pStaticInfo->nonReplayableShadowFaultBufferMetadataSize; + } + else if (index == REPLAYABLE_FAULT_BUFFER) + { + faultBufferSize = pStaticInfo->replayableFaultBufferSize; + shadowFaultBufferMetadataSize = pStaticInfo->replayableShadowFaultBufferMetadataSize; + } + else + { + NV_ASSERT_OR_RETURN(0, NV_ERR_INVALID_ARGUMENT); + } + + status = _kgmmuClientShadowFaultBufferQueueAllocate(pGpu, pKernelGmmu, index); if (status != NV_OK) { return status; } status = _kgmmuClientShadowFaultBufferPagesAllocate(pGpu, pKernelGmmu, - pStaticInfo->nonReplayableFaultBufferSize); + faultBufferSize, + shadowFaultBufferMetadataSize, + index); if (status != NV_OK) { goto destroy_queue_and_exit; } - status = kgmmuClientShadowFaultBufferRegister(pGpu, pKernelGmmu); + status = kgmmuFaultBufferAllocSharedMemory_HAL(pGpu, pKernelGmmu, index); if (status != NV_OK) { goto destroy_pages_and_exit; } + status = kgmmuClientShadowFaultBufferRegister(pGpu, pKernelGmmu, + index); + if (status != NV_OK) + { + goto destroy_shared_memory_and_exit; + } + return NV_OK; +destroy_shared_memory_and_exit: + kgmmuFaultBufferFreeSharedMemory_HAL(pGpu, pKernelGmmu, index); destroy_pages_and_exit: - kgmmuClientShadowFaultBufferPagesDestroy(pGpu, pKernelGmmu, NV_TRUE); + kgmmuClientShadowFaultBufferPagesDestroy(pGpu, pKernelGmmu, NV_TRUE, + index); destroy_queue_and_exit: - kgmmuClientShadowFaultBufferQueueDestroy(pGpu, pKernelGmmu, NV_TRUE); + kgmmuClientShadowFaultBufferQueueDestroy(pGpu, pKernelGmmu, NV_TRUE, + index); return status; } @@ -1727,23 +1879,30 @@ * @returns */ NV_STATUS -kgmmuClientShadowFaultBufferNonreplayableDestroy_IMPL +kgmmuClientShadowFaultBufferDestroy_IMPL ( - OBJGPU *pGpu, - KernelGmmu *pKernelGmmu + OBJGPU *pGpu, + KernelGmmu *pKernelGmmu, + FAULT_BUFFER_TYPE index ) { GMMU_CLIENT_SHADOW_FAULT_BUFFER *pClientShadowFaultBuffer; NvBool bFreeMemory = !RMCFG_FEATURE_PLATFORM_GSP; - pClientShadowFaultBuffer = pKernelGmmu->mmuFaultBuffer[GPU_GFID_PF].pClientShadowFaultBuffer; + pClientShadowFaultBuffer = + pKernelGmmu->mmuFaultBuffer[GPU_GFID_PF].pClientShadowFaultBuffer[index]; if (pClientShadowFaultBuffer != NvP64_NULL) { - kgmmuClientShadowFaultBufferUnregister(pGpu, pKernelGmmu); + kgmmuClientShadowFaultBufferUnregister(pGpu, pKernelGmmu, + index); + + kgmmuFaultBufferFreeSharedMemory_HAL(pGpu, pKernelGmmu, index); - kgmmuClientShadowFaultBufferPagesDestroy(pGpu, pKernelGmmu, bFreeMemory); - kgmmuClientShadowFaultBufferQueueDestroy(pGpu, pKernelGmmu, bFreeMemory); + kgmmuClientShadowFaultBufferPagesDestroy(pGpu, pKernelGmmu, bFreeMemory, + index); + kgmmuClientShadowFaultBufferQueueDestroy(pGpu, pKernelGmmu, bFreeMemory, + index); } return NV_OK; @@ -1756,7 +1915,7 @@ * * @return NvU32 */ -NvU32 +NvU64 kgmmuGetMinBigPageSize_IMPL(KernelGmmu *pKernelGmmu) { // @@ -1803,6 +1962,8 @@ NvU32 dirBaseLoData; NvU32 atsOffset; NvU32 atsData; + NvU32 magicValueOffset; + NvU32 magicValueData; NV_STATUS status = NV_OK; NV_ASSERT(!gpumgrGetBcEnabledStatus(pGpu)); @@ -1827,6 +1988,9 @@ atsOffset = 0; atsData = 0; } + + status = kgmmuInstBlkMagicValueGet_HAL(pKernelGmmu, &magicValueOffset, &magicValueData); + // Write the fields out pInstBlk = pInstBlkParams->pInstBlk; @@ -1851,10 +2015,16 @@ if (atsOffset != 0) MEM_WR32(pInstBlk + atsOffset, atsData); + + if (status == NV_OK) + MEM_WR32(pInstBlk + magicValueOffset, magicValueData); } else { - pInstBlk = kbusMapRmAperture_HAL(pGpu, pInstBlkDesc); + MemoryManager *pMemoryManager = GPU_GET_MEMORY_MANAGER(pGpu); + + pInstBlk = memmgrMemDescBeginTransfer(pMemoryManager, pInstBlkDesc, + TRANSFER_FLAGS_SHADOW_ALLOC); if (pInstBlk == NULL) { return NV_ERR_INSUFFICIENT_RESOURCES; @@ -1880,7 +2050,11 @@ if (atsOffset != 0) MEM_WR32(pInstBlk + atsOffset, atsData); - kbusUnmapRmAperture_HAL(pGpu, pInstBlkDesc, &pInstBlk, NV_FALSE); + if (status == NV_OK) + MEM_WR32(pInstBlk + magicValueOffset, magicValueData); + + memmgrMemDescEndTransfer(pMemoryManager, pInstBlkDesc, + TRANSFER_FLAGS_SHADOW_ALLOC); } if (!pInstBlkParams->bDeferFlush) @@ -1889,7 +2063,7 @@ | kbusGetFlushAperture(pKernelBus, memdescGetAddressSpace(pInstBlkDesc))); } - return status; + return NV_OK; } GMMU_APERTURE @@ -1953,15 +2127,33 @@ ) { NvU32 engineIdx; + NvU16 *pEngineIdxList; + NvU32 listSize; static NvU16 engineIdxList[] = { MC_ENGINE_IDX_REPLAYABLE_FAULT, MC_ENGINE_IDX_REPLAYABLE_FAULT_ERROR, }; - for (NvU32 tableIdx = 0; tableIdx < NV_ARRAY_ELEMENTS32(engineIdxList); tableIdx++) + static NvU16 engineIdxListForCC[] = { + MC_ENGINE_IDX_REPLAYABLE_FAULT_CPU, + MC_ENGINE_IDX_NON_REPLAYABLE_FAULT_CPU, + }; + + if (IS_GSP_CLIENT(pGpu) && gpuIsCCFeatureEnabled(pGpu) && gpuIsGspOwnedFaultBuffersEnabled(pGpu)) + { + pEngineIdxList = engineIdxListForCC; + listSize = NV_ARRAY_ELEMENTS(engineIdxListForCC); + } + else + { + pEngineIdxList = engineIdxList; + listSize = NV_ARRAY_ELEMENTS(engineIdxList); + } + + for (NvU32 tableIdx = 0; tableIdx < listSize; tableIdx++) { - engineIdx = engineIdxList[tableIdx]; + engineIdx = (pEngineIdxList)[tableIdx]; NV_ASSERT(pRecords[engineIdx].pInterruptService == NULL); pRecords[engineIdx].pInterruptService = staticCast(pKernelGmmu, IntrService); } @@ -2008,6 +2200,18 @@ } break; } + case MC_ENGINE_IDX_NON_REPLAYABLE_FAULT_CPU: + { + osQueueMMUFaultHandler(pGpu); + status = 0; + break; + } + case MC_ENGINE_IDX_REPLAYABLE_FAULT_CPU: + { + NV_PRINTF(LEVEL_ERROR, "Unexpected replayable interrupt routed to RM. Verify UVM took ownership.\n"); + status = NV_ERR_INVALID_STATE; + break; + } default: { NV_ASSERT_FAILED("Invalid engineIdx"); @@ -2238,3 +2442,46 @@ { return &pKernelGmmu->mmuFaultBuffer[gfid].hwFaultBuffers[faultBufferIndex]; } + +NvU64 +kgmmuGetFaultBufferGenCnt_IMPL +( + OBJGPU *pGpu, + KernelGmmu *pKernelGmmu, + NvU8 gfid +) +{ + return pKernelGmmu->mmuFaultBuffer[gfid].faultBufferGenerationCounter; +} + +void * +kgmmuGetShadowFaultBufferCslContext_IMPL +( + OBJGPU *pGpu, + KernelGmmu *pKernelGmmu, + FAULT_BUFFER_TYPE type +) +{ + ConfidentialCompute *pConfCompute = GPU_GET_CONF_COMPUTE(pGpu); + + if (!gpuIsCCFeatureEnabled(pGpu)) + { + return NULL; + } + + NV_ASSERT_OR_RETURN( + pConfCompute->getProperty(pConfCompute, PDB_PROP_CONFCOMPUTE_ENCRYPT_ENABLED), + NULL); + + switch (type) + { + case NON_REPLAYABLE_FAULT_BUFFER: + return pConfCompute->pNonReplayableFaultCcslCtx; + case REPLAYABLE_FAULT_BUFFER: + return pConfCompute->pReplayableFaultCcslCtx; + default: + break; + } + + return NULL; +} diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/kernel/gpu/mmu/mmu_fault_buffer.c nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/kernel/gpu/mmu/mmu_fault_buffer.c --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/kernel/gpu/mmu/mmu_fault_buffer.c 2023-10-25 20:21:16.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/kernel/gpu/mmu/mmu_fault_buffer.c 2024-03-05 22:13:42.000000000 +0000 @@ -54,12 +54,6 @@ return NV_ERR_INVALID_CLASS; } - if (pCallContext->secInfo.privLevel < RS_PRIV_LEVEL_KERNEL) - { - NV_PRINTF(LEVEL_ERROR, "Client is not privileged\n"); - return NV_ERR_INSUFFICIENT_PERMISSIONS; - } - NV_ASSERT_OR_RETURN(pKernelGmmu != NULL, NV_ERR_NOT_SUPPORTED); status = kgmmuFaultBufferReplayableAllocate(pGpu, pKernelGmmu, diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/kernel/gpu/mmu/mmu_fault_buffer_ctrl.c nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/kernel/gpu/mmu/mmu_fault_buffer_ctrl.c --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/kernel/gpu/mmu/mmu_fault_buffer_ctrl.c 2023-10-25 20:21:16.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/kernel/gpu/mmu/mmu_fault_buffer_ctrl.c 2024-03-05 22:13:43.000000000 +0000 @@ -44,7 +44,8 @@ const NV2080_CTRL_INTERNAL_GMMU_GET_STATIC_INFO_PARAMS *pStaticInfo = kgmmuGetStaticInfo(pGpu, pKernelGmmu); GMMU_CLIENT_SHADOW_FAULT_BUFFER *pClientShadowFaultBuffer; - pClientShadowFaultBuffer = pKernelGmmu->mmuFaultBuffer[GPU_GFID_PF].pClientShadowFaultBuffer; + pClientShadowFaultBuffer = + pKernelGmmu->mmuFaultBuffer[GPU_GFID_PF].pClientShadowFaultBuffer[NON_REPLAYABLE_FAULT_BUFFER]; // This call takes GpuLock, so shadowBuffer pointers can be accessed without grabbing lock protecting them if (pClientShadowFaultBuffer) @@ -56,7 +57,7 @@ return NV_ERR_NOT_SUPPORTED; } - status = kgmmuClientShadowFaultBufferAlloc_HAL(pGpu, pKernelGmmu); + status = kgmmuClientShadowFaultBufferAlloc_HAL(pGpu, pKernelGmmu, NON_REPLAYABLE_FAULT_BUFFER); if (status != NV_OK) { NV_PRINTF(LEVEL_ERROR, @@ -65,10 +66,21 @@ return status; } - pClientShadowFaultBuffer = pKernelGmmu->mmuFaultBuffer[GPU_GFID_PF].pClientShadowFaultBuffer; + pClientShadowFaultBuffer = + pKernelGmmu->mmuFaultBuffer[GPU_GFID_PF].pClientShadowFaultBuffer[NON_REPLAYABLE_FAULT_BUFFER]; - pParams->pShadowBuffer = pClientShadowFaultBuffer->pQueueAddress; - pParams->pShadowBufferContext = (NvP64) &pClientShadowFaultBuffer->queueContext; + if (gpuIsCCFeatureEnabled(pGpu) && gpuIsGspOwnedFaultBuffersEnabled(pGpu)) + { + pParams->pShadowBuffer = pClientShadowFaultBuffer->pBufferAddress; + pParams->pShadowBufferContext = NvP64_NULL; + pParams->pShadowBufferMetadata = pClientShadowFaultBuffer->pFaultBufferMetadataAddress; + } + else + { + pParams->pShadowBuffer = pClientShadowFaultBuffer->pQueueAddress; + pParams->pShadowBufferContext = (NvP64) &pClientShadowFaultBuffer->queueContext; + pParams->pShadowBufferMetadata = NvP64_NULL; + } pParams->bufferSize = pStaticInfo->nonReplayableFaultBufferSize; return NV_OK; @@ -86,26 +98,120 @@ KernelGmmu *pKernelGmmu = GPU_GET_KERNEL_GMMU(pGpu); // This call takes GpuLock, so shadowBuffer pointers can be accessed without grabbing lock protecting them - if (!pKernelGmmu->mmuFaultBuffer[GPU_GFID_PF].pClientShadowFaultBuffer) + if (!pKernelGmmu->mmuFaultBuffer[GPU_GFID_PF].pClientShadowFaultBuffer[NON_REPLAYABLE_FAULT_BUFFER]) { NV_PRINTF(LEVEL_ERROR, "Client shadow fault buffer for non-replayable faults does not exist\n"); return NV_OK; } - if (pParams->pShadowBuffer != - pKernelGmmu->mmuFaultBuffer[GPU_GFID_PF].pClientShadowFaultBuffer->pQueueAddress) + if ((pParams->pShadowBuffer != + pKernelGmmu->mmuFaultBuffer[GPU_GFID_PF].pClientShadowFaultBuffer[NON_REPLAYABLE_FAULT_BUFFER]->pQueueAddress) + && (!gpuIsCCFeatureEnabled(pGpu) || !gpuIsGspOwnedFaultBuffersEnabled(pGpu)) + ) + { + NV_PRINTF(LEVEL_ERROR, + "Given client shadow fault buffer for non-replayable faults does not " + "match with the actual\n"); + } + else if (gpuIsCCFeatureEnabled(pGpu) && gpuIsGspOwnedFaultBuffersEnabled(pGpu) && + (pParams->pShadowBuffer != + pKernelGmmu->mmuFaultBuffer[GPU_GFID_PF].pClientShadowFaultBuffer[NON_REPLAYABLE_FAULT_BUFFER]->pBufferAddress)) { NV_PRINTF(LEVEL_ERROR, "Given client shadow fault buffer for non-replayable faults does not " "match with the actual\n"); } - status = kgmmuClientShadowFaultBufferFree_HAL(pGpu, pKernelGmmu); + status = kgmmuClientShadowFaultBufferFree_HAL(pGpu, pKernelGmmu, NON_REPLAYABLE_FAULT_BUFFER); if (status != NV_OK) { NV_PRINTF(LEVEL_ERROR, "Error freeing client shadow fault buffer for non-replayable faults\n"); } return status; +} + +NV_STATUS +faultbufCtrlCmdMmuFaultBufferRegisterReplayBuf_IMPL +( + MmuFaultBuffer *pMmuFaultBuffer, + NVC369_CTRL_MMU_FAULT_BUFFER_REGISTER_REPLAY_BUF_PARAMS *pParams +) +{ + NV_STATUS status; + OBJGPU *pGpu = GPU_RES_GET_GPU(pMmuFaultBuffer); + KernelGmmu *pKernelGmmu = GPU_GET_KERNEL_GMMU(pGpu); + const NV2080_CTRL_INTERNAL_GMMU_GET_STATIC_INFO_PARAMS *pStaticInfo = kgmmuGetStaticInfo(pGpu, pKernelGmmu); + GMMU_CLIENT_SHADOW_FAULT_BUFFER *pClientShadowFaultBuffer; + + NV_ASSERT_OR_RETURN(gpuIsCCFeatureEnabled(pGpu), NV_ERR_NOT_SUPPORTED); + + pClientShadowFaultBuffer = + pKernelGmmu->mmuFaultBuffer[GPU_GFID_PF].pClientShadowFaultBuffer[REPLAYABLE_FAULT_BUFFER]; + + // This call takes GpuLock, so shadowBuffer pointers can be accessed without grabbing lock protecting them + if (pClientShadowFaultBuffer != NULL) + { + NV_PRINTF(LEVEL_ERROR, + "Client shadow fault buffer for replayable faults already allocated\n"); + NV_ASSERT(0); + + return NV_ERR_NOT_SUPPORTED; + } + + status = kgmmuClientShadowFaultBufferAlloc_HAL(pGpu, pKernelGmmu, REPLAYABLE_FAULT_BUFFER); + if (status != NV_OK) + { + NV_PRINTF(LEVEL_ERROR, + "Error allocating client shadow fault buffer for replayable faults\n"); + return status; + } + + pClientShadowFaultBuffer = + pKernelGmmu->mmuFaultBuffer[GPU_GFID_PF].pClientShadowFaultBuffer[REPLAYABLE_FAULT_BUFFER]; + + pParams->pShadowBuffer = pClientShadowFaultBuffer->pBufferAddress; + pParams->pShadowBufferMetadata = pClientShadowFaultBuffer->pFaultBufferMetadataAddress; + pParams->bufferSize = pStaticInfo->replayableFaultBufferSize; + + return NV_OK; +} + +NV_STATUS +faultbufCtrlCmdMmuFaultBufferUnregisterReplayBuf_IMPL +( + MmuFaultBuffer *pMmuFaultBuffer, + NVC369_CTRL_MMU_FAULT_BUFFER_UNREGISTER_REPLAY_BUF_PARAMS *pParams +) +{ + NV_STATUS status; + OBJGPU *pGpu = GPU_RES_GET_GPU(pMmuFaultBuffer); + KernelGmmu *pKernelGmmu = GPU_GET_KERNEL_GMMU(pGpu); + + NV_ASSERT_OR_RETURN(gpuIsCCFeatureEnabled(pGpu), NV_ERR_NOT_SUPPORTED); + + // This call takes GpuLock, so shadowBuffer pointers can be accessed without grabbing lock protecting them + if (pKernelGmmu->mmuFaultBuffer[GPU_GFID_PF].pClientShadowFaultBuffer[REPLAYABLE_FAULT_BUFFER] == NULL) + { + NV_PRINTF(LEVEL_ERROR, + "Client shadow fault buffer for replayable faults does not exist\n"); + return NV_OK; + } + + if (pParams->pShadowBuffer != + pKernelGmmu->mmuFaultBuffer[GPU_GFID_PF].pClientShadowFaultBuffer[REPLAYABLE_FAULT_BUFFER]->pBufferAddress) + { + NV_PRINTF(LEVEL_ERROR, + "Given client shadow fault buffer for replayable faults does not " + "match with the actual\n"); + } + + status = kgmmuClientShadowFaultBufferFree_HAL(pGpu, pKernelGmmu, REPLAYABLE_FAULT_BUFFER); + if (status != NV_OK) { + NV_PRINTF(LEVEL_ERROR, + "Error freeing client shadow fault buffer for replayable faults\n"); + } + + return status; } diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/kernel/gpu/mmu/mmu_trace.c nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/kernel/gpu/mmu/mmu_trace.c --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/kernel/gpu/mmu/mmu_trace.c 2023-10-25 20:21:16.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/kernel/gpu/mmu/mmu_trace.c 2024-03-05 22:13:43.000000000 +0000 @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 2013-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2013-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -461,23 +461,26 @@ NvBool verbose ) { - const void *pFmt = pLayout->pFmt; - const MMU_TRACE_CALLBACKS *pTraceCb = pLayout->pTraceCb; - NvU32 index = mmuFmtVirtAddrToEntryIndex(pFmtLevel, va); - NvU64 offset = index * pFmtLevel->entrySize; - NV_STATUS status = NV_OK; - MMU_INVALID_RANGE invalidRange = {0}; - NvU64 entryVa = va; - NvBool isPt = NV_FALSE; - NvU8 *pBase = NULL; - MEMORY_DESCRIPTOR *pTempMemDesc = NULL; + const void *pFmt = pLayout->pFmt; + const MMU_TRACE_CALLBACKS *pTraceCb = pLayout->pTraceCb; + NvU32 index = mmuFmtVirtAddrToEntryIndex(pFmtLevel, va); + NvU64 offset = index * pFmtLevel->entrySize; + NV_STATUS status = NV_OK; + MMU_INVALID_RANGE invalidRange = {0}; + NvU64 entryVa = va; + NvBool isPt = NV_FALSE; + NvU8 *pBase = NULL; + MEMORY_DESCRIPTOR *pTempMemDesc = NULL; + MemoryManager *pMemoryManager = GPU_GET_MEMORY_MANAGER(pGpu); if (pMemDesc == NULL) { return NV_OK; } - pBase = kbusMapRmAperture_HAL(pGpu, pMemDesc); + pBase = memmgrMemDescBeginTransfer(pMemoryManager, pMemDesc, + TRANSFER_FLAGS_SHADOW_ALLOC | + TRANSFER_FLAGS_SHADOW_INIT_MEM); if (pBase == NULL) { return NV_ERR_INSUFFICIENT_RESOURCES; @@ -572,9 +575,10 @@ continue; } - NV_ASSERT_OK_OR_RETURN( + NV_ASSERT_OK_OR_GOTO(status, mmuWalkGetPageLevelInfo(pWalk, &pFmtLevel->subLevels[i], entryVa, - (const MMU_WALK_MEMDESC**)&pTempMemDesc, &memSize)); + (const MMU_WALK_MEMDESC**)&pTempMemDesc, &memSize), + unmap_and_exit); // Only print out the PDE the first time we know it's a valid PDE if (!valid) @@ -659,7 +663,7 @@ unmap_and_exit: - kbusUnmapRmAperture_HAL(pGpu, pMemDesc, &pBase, NV_FALSE); + memmgrMemDescEndTransfer(pMemoryManager, pMemDesc, TRANSFER_FLAGS_DEFER_FLUSH); return status; } diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/kernel/gpu/mmu/uvm_sw.c nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/kernel/gpu/mmu/uvm_sw.c --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/kernel/gpu/mmu/uvm_sw.c 2023-10-25 20:21:17.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/kernel/gpu/mmu/uvm_sw.c 2024-03-05 22:13:43.000000000 +0000 @@ -52,7 +52,7 @@ RS_PRIV_LEVEL privLevel = pCallContext->secInfo.privLevel; if (!(rmclientIsAdmin(pRmClient, privLevel) || hypervisorCheckForObjectAccess(hClient))) - return NV_ERR_INVALID_CLIENT; + return NV_ERR_INSUFFICIENT_PERMISSIONS; uvmswInitSwMethodState(pUvmSw); diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/kernel/gpu/mmu/vidmem_access_bit_buffer_v2.c nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/kernel/gpu/mmu/vidmem_access_bit_buffer_v2.c --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/kernel/gpu/mmu/vidmem_access_bit_buffer_v2.c 1970-01-01 00:00:00.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/kernel/gpu/mmu/vidmem_access_bit_buffer_v2.c 2024-03-05 22:13:43.000000000 +0000 @@ -0,0 +1,40 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2021-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#include "core/core.h" +#include "os/os.h" +#include "gpu/mmu/vidmem_access_bit_buffer.h" +#include "gpu/device/device.h" +#include "gpu/gpu.h" + +NV_STATUS +vidmemAccessBitBufConstructHelper_KERNEL +( + VidmemAccessBitBuffer *pVidmemAccessBitBuffer, + CALL_CONTEXT *pCallContext, + RS_RES_ALLOC_PARAMS_INTERNAL *pParams +) +{ + OBJGPU *pGpu = GPU_RES_GET_GPU(pVidmemAccessBitBuffer); + return IS_VGPU_GSP_PLUGIN_OFFLOAD_ENABLED(pGpu) && !IS_VIRTUAL(pGpu)? NV_OK : NV_ERR_NOT_SUPPORTED; +} \ No newline at end of file diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/kernel/gpu/nvdec/kernel_nvdec_engdesc.c nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/kernel/gpu/nvdec/kernel_nvdec_engdesc.c --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/kernel/gpu/nvdec/kernel_nvdec_engdesc.c 2023-10-25 20:21:17.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/kernel/gpu/nvdec/kernel_nvdec_engdesc.c 2024-03-05 22:13:43.000000000 +0000 @@ -25,6 +25,7 @@ #include "kernel/gpu/mig_mgr/kernel_mig_manager.h" #include "kernel/gpu/fifo/kernel_channel.h" #include "kernel/gpu/nvdec/kernel_nvdec_ctx.h" +#include "kernel/gpu/device/device.h" #include "class/cla0b0.h" // NVA0B0_VIDEO_DECODER #include "class/clb0b0.h" // NVB0B0_VIDEO_DECODER @@ -97,10 +98,19 @@ KernelMIGManager *pKernelMIGManager = GPU_GET_KERNEL_MIG_MANAGER(pGpu); MIG_INSTANCE_REF ref; RM_ENGINE_TYPE rmEngineType; + RsResourceRef *pDeviceRef = NULL; NV_ASSERT_OK( - kmigmgrGetInstanceRefFromClient(pGpu, pKernelMIGManager, - pCallContext->pClient->hClient, &ref)); + refFindAncestorOfType(pCallContext->pResourceRef, + classId(Device), &pDeviceRef)); + + if (pDeviceRef == NULL) + return ENG_INVALID; + + NV_ASSERT_OK( + kmigmgrGetInstanceRefFromDevice(pGpu, pKernelMIGManager, + dynamicCast(pDeviceRef->pResource, Device), + &ref)); NV_ASSERT_OK( kmigmgrGetLocalToGlobalEngineType(pGpu, pKernelMIGManager, ref, diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/kernel/gpu/nvenc/kernel_nvenc_engdesc.c nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/kernel/gpu/nvenc/kernel_nvenc_engdesc.c --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/kernel/gpu/nvenc/kernel_nvenc_engdesc.c 2023-10-25 20:21:17.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/kernel/gpu/nvenc/kernel_nvenc_engdesc.c 2024-03-05 22:13:43.000000000 +0000 @@ -24,6 +24,7 @@ #include "os/os.h" #include "kernel/gpu/mig_mgr/kernel_mig_manager.h" #include "kernel/gpu/fifo/kernel_channel.h" +#include "kernel/gpu/device/device.h" #include "class/clc0b7.h" #include "class/cld0b7.h" @@ -75,8 +76,14 @@ case NVC7B7_VIDEO_ENCODER: case NVC9B7_VIDEO_ENCODER: engineInstance = pMsencAllocParms->engineInstance; + NV_PRINTF(LEVEL_INFO, "Supported msenc class Id (classId = 0x%x / engineInstance = 0x%x)\n", + externalClassId, + engineInstance); break; default: + NV_PRINTF(LEVEL_ERROR, "Not supported msenc class Id (classId = 0x%x / engineInstance = 0x%x)\n", + externalClassId, + pMsencAllocParms->engineInstance); return ENG_INVALID; } @@ -85,10 +92,19 @@ KernelMIGManager *pKernelMIGManager = GPU_GET_KERNEL_MIG_MANAGER(pGpu); MIG_INSTANCE_REF ref; RM_ENGINE_TYPE rmEngineType; + RsResourceRef *pDeviceRef = NULL; NV_ASSERT_OK( - kmigmgrGetInstanceRefFromClient(pGpu, pKernelMIGManager, - pCallContext->pClient->hClient, &ref)); + refFindAncestorOfType(pCallContext->pResourceRef, + classId(Device), &pDeviceRef)); + + if (pDeviceRef == NULL) + return ENG_INVALID; + + NV_ASSERT_OK( + kmigmgrGetInstanceRefFromDevice(pGpu, pKernelMIGManager, + dynamicCast(pDeviceRef->pResource, Device), + &ref)); NV_ASSERT_OK( kmigmgrGetLocalToGlobalEngineType(pGpu, pKernelMIGManager, ref, diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/kernel/gpu/nvjpg/kernel_nvjpg_engdesc.c nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/kernel/gpu/nvjpg/kernel_nvjpg_engdesc.c --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/kernel/gpu/nvjpg/kernel_nvjpg_engdesc.c 2023-10-25 20:21:17.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/kernel/gpu/nvjpg/kernel_nvjpg_engdesc.c 2024-03-05 22:13:43.000000000 +0000 @@ -23,6 +23,7 @@ #include "gpu/gpu.h" #include "gpu/mig_mgr/kernel_mig_manager.h" +#include "kernel/gpu/device/device.h" #include "nvos.h" #include "resserv/rs_server.h" @@ -71,9 +72,16 @@ case NVB8D1_VIDEO_NVJPG: case NVC9D1_VIDEO_NVJPG: engineInstance = pNvjpgAllocParms->engineInstance; + NV_PRINTF(LEVEL_INFO, "Supported nvjpg class Id (classId = 0x%x / engineInstance = 0x%x)\n", + externalClassId, + engineInstance); break; + default: DBG_BREAKPOINT(); + NV_PRINTF(LEVEL_ERROR, "Not supported nvjpg class Id (classId = 0x%x / engineInstance = 0x%x)\n", + externalClassId, + pNvjpgAllocParms->engineInstance); return ENG_INVALID; } @@ -82,10 +90,19 @@ KernelMIGManager *pKernelMIGManager = GPU_GET_KERNEL_MIG_MANAGER(pGpu); MIG_INSTANCE_REF ref; RM_ENGINE_TYPE rmEngineType; + RsResourceRef *pDeviceRef = NULL; + + NV_ASSERT_OK( + refFindAncestorOfType(pCallContext->pResourceRef, + classId(Device), &pDeviceRef)); + + if (pDeviceRef == NULL) + return ENG_INVALID; NV_ASSERT_OK( - kmigmgrGetInstanceRefFromClient(pGpu, pKernelMIGManager, - pCallContext->pClient->hClient, &ref)); + kmigmgrGetInstanceRefFromDevice(pGpu, pKernelMIGManager, + dynamicCast(pDeviceRef->pResource, Device), + &ref)); NV_ASSERT_OK( kmigmgrGetLocalToGlobalEngineType(pGpu, pKernelMIGManager, ref, diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/kernel/gpu/nvlink/arch/ampere/kernel_nvlink_ga100.c nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/kernel/gpu/nvlink/arch/ampere/kernel_nvlink_ga100.c --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/kernel/gpu/nvlink/arch/ampere/kernel_nvlink_ga100.c 2023-10-25 20:21:17.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/kernel/gpu/nvlink/arch/ampere/kernel_nvlink_ga100.c 2024-03-05 22:13:44.000000000 +0000 @@ -21,6 +21,8 @@ * DEALINGS IN THE SOFTWARE. */ +#define NVOC_KERNEL_NVLINK_H_PRIVATE_ACCESS_ALLOWED + #include "os/os.h" #include "kernel/gpu/nvlink/kernel_nvlink.h" #include "kernel/gpu/nvlink/kernel_ioctrl.h" @@ -31,7 +33,7 @@ * @brief This routine overrides the nvlink connection topology if chiplib arguments * have been provided. It queries MODS API for the chiplib overrides and based * on that, derives hshub configuration values that are programmed at a later - * stage during nvlink state load. The override values should exist for ALL + * stage during nvlink state load. The override values should exist for ALL * links or NO links. The field encoding can be found in phys_nvlink.h * * @param[in] pGpu OBJGPU pointer @@ -133,7 +135,7 @@ { NV_STATUS status = NV_OK; NvU32 peerId; - NvBool bBufferReady; + NvBool bBufferReady = NV_FALSE; NV2080_CTRL_NVLINK_REMOVE_NVLINK_MAPPING_PARAMS params; portMemSet(¶ms, 0, sizeof(params)); @@ -166,7 +168,7 @@ status = knvlinkSyncLinkMasksAndVbiosInfo(pGpu, pKernelNvlink); if (status != NV_OK) { - NV_ASSERT(status == NV_OK); + NV_ASSERT(status != NV_OK); return status; } @@ -184,6 +186,7 @@ if (!bBufferReady) { status = knvlinkUpdateCurrentConfig(pGpu, pKernelNvlink); + } } else diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/kernel/gpu/nvlink/arch/hopper/kernel_nvlink_gh100.c nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/kernel/gpu/nvlink/arch/hopper/kernel_nvlink_gh100.c --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/kernel/gpu/nvlink/arch/hopper/kernel_nvlink_gh100.c 2023-10-25 20:21:17.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/kernel/gpu/nvlink/arch/hopper/kernel_nvlink_gh100.c 2024-03-05 22:13:44.000000000 +0000 @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2022-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -21,6 +21,8 @@ * DEALINGS IN THE SOFTWARE. */ +#define NVOC_KERNEL_NVLINK_H_PRIVATE_ACCESS_ALLOWED + #include "os/os.h" #include "kernel/gpu/nvlink/kernel_nvlink.h" #include "kernel/gpu/nvlink/kernel_ioctrl.h" @@ -28,6 +30,8 @@ #include "gpu/mem_mgr/mem_mgr.h" #include "nverror.h" #include "objtmr.h" +#include "gpu_mgr/gpu_mgr.h" +#include "gpu/gpu_fabric_probe.h" /*! * @brief Check if ALI is supported for the given device @@ -209,7 +213,7 @@ // // Initialize Mask of links that have made it past RxDet to 0 then // request to get all links from the given GPU that have gotted past RxDet - // + // pKernelNvlink0->postRxDetLinkMask = 0; status = knvlinkUpdatePostRxDetectLinkMask(pGpu0, pKernelNvlink0); if(status != NV_OK) @@ -242,7 +246,8 @@ if(pKernelNvlink0->postRxDetLinkMask == 0 || pKernelNvlink1->postRxDetLinkMask == 0) { - NV_PRINTF(LEVEL_ERROR, "Got 0 post RxDet Links!"); + NV_PRINTF(LEVEL_INFO, "Got 0 post RxDet Links on GPU %d or GPU %d!\n", + gpuGetInstance(pGpu0), gpuGetInstance(pGpu1)); return NV_ERR_NOT_READY; } @@ -371,6 +376,203 @@ return NV_OK; } +/** + * @brief Check if the nvlink bandwidth setting is OFF + * + * @param[in] pKernelNvlink reference of KernelNvlink + */ +NvBool +knvlinkIsBandwidthModeOff_GH100 +( + KernelNvlink *pKernelNvlink +) +{ + return (gpumgrGetGpuNvlinkBwMode() == GPU_NVLINK_BW_MODE_OFF); +} + +/** + * @brief Calculate the number of active nvlinks needs to be reduced + * for direct connect GPU system + * + * @param[in] pKernelNvlink reference of KernelNvlink + */ +NvU32 +knvlinkGetNumLinksToBeReducedPerIoctrl_GH100 +( + KernelNvlink *pKernelNvlink +) +{ + NvU32 numlinks = 0; + NvU8 mode; + +#if defined(INCLUDE_NVLINK_LIB) + numlinks = pKernelNvlink->pNvlinkDev->numActiveLinksPerIoctrl; +#endif + + if (numlinks == 0) + goto out; + + mode = gpumgrGetGpuNvlinkBwMode(); + + switch (mode) + { + case GPU_NVLINK_BW_MODE_OFF: + NV_PRINTF(LEVEL_ERROR, "Cannot reach here %s %d mode=%d\n", + __func__, __LINE__, mode); + NV_ASSERT(0); + break; + case GPU_NVLINK_BW_MODE_MIN: + numlinks = numlinks - 1; // At least one is ative at this point. + break; + case GPU_NVLINK_BW_MODE_HALF: + numlinks = numlinks / 2; + break; + case GPU_NVLINK_BW_MODE_3QUARTER: + numlinks = numlinks / 4; + break; + default: // Treat as GPU_NVLINK_BW_MODE_FULL + numlinks = 0; + break; + } + +out: + return numlinks; +} + +/** + * @brief Calculate the effective peer link mask for HS_HUB configuration + * + * @param[in] pGpu OBJGPU pointer of local GPU + * @param[in] pKernelNvlink reference of KernelNvlink + * @param[in] pRemoteGpu OBJGPU pointer of remote GPU + * @param[in/out] pPeerLinkMask reference of peerLinkMask + */ +void +knvlinkGetEffectivePeerLinkMask_GH100 +( + OBJGPU *pGpu, + KernelNvlink *pKernelNvlink, + OBJGPU *pRemoteGpu, + NvU32 *pPeerLinkMask +) +{ + NvU32 peerLinkMask, remotePeerLinkMask, effectivePeerLinkMask, peerLinkMaskPerIoctrl; + NvU32 gpuInstance, remoteGpuInstance; + NvU32 numLinksPerIoctrl, numIoctrls; + KernelNvlink *pRemoteKernelNvlink; + NvU32 numLinksToBeReduced; + NvU32 linkMaskToBeReduced; + NvU32 linkId, count, i; + + gpuInstance = gpuGetInstance(pGpu); + remoteGpuInstance = gpuGetInstance(pRemoteGpu); + + if (knvlinkIsGpuConnectedToNvswitch(pGpu, pKernelNvlink)) + { + if (gpuFabricProbeGetlinkMaskToBeReduced(pGpu->pGpuFabricProbeInfoKernel, + &linkMaskToBeReduced) == NV_OK) + { + *pPeerLinkMask &= (~linkMaskToBeReduced); + } + + return; + } + + peerLinkMask = pKernelNvlink->peerLinkMasks[remoteGpuInstance]; + if (peerLinkMask == 0) + { + return; + } + + // + // No need to check if remotePeerLinkMask and peerLinkMask are equal because + // RM will not enable P2P otherwise. Given that we have reached here means + // the masks must be equal. + // + pRemoteKernelNvlink = GPU_GET_KERNEL_NVLINK(pRemoteGpu); + remotePeerLinkMask = pRemoteKernelNvlink->peerLinkMasks[gpuInstance]; + NV_ASSERT(nvPopCount32(remotePeerLinkMask) == nvPopCount32(peerLinkMask)); + + // Find out number of active NVLinks between the two GPUs. + numLinksToBeReduced = knvlinkGetNumLinksToBeReducedPerIoctrl_HAL(pKernelNvlink); + effectivePeerLinkMask = peerLinkMask; + + if (numLinksToBeReduced == 0) + { + return; + } + + // Start reducing effectivePeerLinkMask... + + // + // To have deterministic approach, if local GPU ID is less than remote GPU + // ID, always trim peerLinkMask from the perspective of local GPU. + // Otherwise, use remote GPU for the same. + // +#if defined(INCLUDE_NVLINK_LIB) + numIoctrls = pKernelNvlink->pNvlinkDev->numIoctrls; + numLinksPerIoctrl = pKernelNvlink->pNvlinkDev->numLinksPerIoctrl; +#else + numIoctrls = 0; + numLinksPerIoctrl = 0; +#endif + + if (pGpu->gpuId < pRemoteGpu->gpuId) + { + for (i = 0; i < numIoctrls; i++) + { + count = 0; + peerLinkMaskPerIoctrl = peerLinkMask & + (((1 << numLinksPerIoctrl) - 1) << (i * numLinksPerIoctrl)); + + FOR_EACH_INDEX_IN_MASK(32, linkId, peerLinkMaskPerIoctrl) + { + if (count == numLinksToBeReduced) + { + break; + } + + effectivePeerLinkMask &= (~NVBIT(linkId)); + count++; + } + FOR_EACH_INDEX_IN_MASK_END; + } + } + else + { + for (i = 0; i < numIoctrls; i++) + { + count = 0; + peerLinkMaskPerIoctrl = remotePeerLinkMask & + (((1 << numLinksPerIoctrl) - 1) << (i * numLinksPerIoctrl)); + + FOR_EACH_INDEX_IN_MASK(32, linkId, peerLinkMaskPerIoctrl) + { + if (count == numLinksToBeReduced) + { + break; + } + +#if defined(INCLUDE_NVLINK_LIB) + effectivePeerLinkMask &= + (~NVBIT(pRemoteKernelNvlink->nvlinkLinks[linkId].remoteEndInfo.linkNumber)); +#endif + count++; + } + FOR_EACH_INDEX_IN_MASK_END; + } + } + + // + // effectivePeerLinkMask can never be zero, otherwise we create inconsistent + // HW/SW state, where we say that NVLink P2P is supported, but we don't + // program HSHUB. + // + // So, if not enough NVLinks are present, then drop effectivePeerLinkMask. + // + *pPeerLinkMask = (effectivePeerLinkMask > 0) ? effectivePeerLinkMask : peerLinkMask; +} + /*! * @brief Set unique fabric address for NVSwitch enabled systems. * @@ -432,6 +634,48 @@ } /*! + * @brief Clear unique fabric address for NVSwitch enabled systems. + * + * @param[in] pGpu OBJGPU pointer + * @param[in] pKernelNvlink KernelNvlink pointer + */ +void +knvlinkClearUniqueFabricBaseAddress_GH100 +( + OBJGPU *pGpu, + KernelNvlink *pKernelNvlink +) +{ + pKernelNvlink->fabricBaseAddr = NVLINK_INVALID_FABRIC_ADDR; +} + +/*! + * @brief Check if system has enough active NVLinks and + * enough NVLink bridges + * + * @param[in] pGpu OBJGPU pointer + * @param[in] pKernelNvlink KernelNvlink pointer + * + */ +void +knvlinkDirectConnectCheck_GH100 +( + OBJGPU *pGpu, + KernelNvlink *pKernelNvlink +) +{ + NV2080_CTRL_NVLINK_DIRECT_CONNECT_CHECK_PARAMS params = {0}; + + if (knvlinkExecGspRmRpc(pGpu, pKernelNvlink, + NV2080_CTRL_CMD_NVLINK_DIRECT_CONNECT_CHECK, + (void *)¶ms, + sizeof(params)) != NV_OK) + { + NV_PRINTF(LEVEL_ERROR, "Fail to call direct conect check command\n"); + } +} + +/*! * @brief Check if floorsweeping is needed for this particular chip * * @param[in] pGpu OBJGPU pointer @@ -452,19 +696,22 @@ // // Only floorsweep down the given GPU if the following conditions are met: - // 1. The number of active links allowed for the IOCTRL is less then the + // 1. if the number of links for the IP is > 0 + // + // 2. The number of active links allowed for the IOCTRL is less then the // total number of links for the IOCTRL. No reason to spend time in code // if the exectution of it will be a NOP // - // 2. If the GPU has never been floorswept. An optimization to make sure RM + // 3. If the GPU has never been floorswept. An optimization to make sure RM // doesn't burn cycles repeatedly running running code that will be a NOP // - // 3. (temporary) Run only on Silicon chips. Fmodel currently doesn't support + // 4. (temporary) Run only on Silicon chips. Fmodel currently doesn't support // this feature // - if (numActiveLinksPerIoctrl < numLinksPerIoctrl && - !pKernelNvlink->bFloorSwept && + if ((numLinksPerIoctrl > 0 && numActiveLinksPerIoctrl > 0) && + numActiveLinksPerIoctrl < numLinksPerIoctrl && + !pKernelNvlink->bFloorSwept && IS_SILICON(pGpu)) { return NV_TRUE; @@ -473,25 +720,3 @@ return NV_FALSE; } -/*! - * @brief Check if system has enough active NVLinks and - * enough NVLink bridges - * - * @param[in] pGpu OBJGPU pointer - * @param[in] pKernelNvlink KernelNvlink pointer - * - */ -void -knvlinkDirectConnectCheck_GH100 -( - OBJGPU *pGpu, - KernelNvlink *pKernelNvlink -) -{ - NV2080_CTRL_NVLINK_DIRECT_CONNECT_CHECK_PARAMS params = {0}; - - knvlinkExecGspRmRpc(pGpu, pKernelNvlink, - NV2080_CTRL_CMD_NVLINK_DIRECT_CONNECT_CHECK, - (void *)¶ms, - sizeof(params)); -} diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/kernel/gpu/nvlink/arch/pascal/kernel_nvlink_gp100.c nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/kernel/gpu/nvlink/arch/pascal/kernel_nvlink_gp100.c --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/kernel/gpu/nvlink/arch/pascal/kernel_nvlink_gp100.c 2023-10-25 20:21:18.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/kernel/gpu/nvlink/arch/pascal/kernel_nvlink_gp100.c 2024-03-05 22:13:44.000000000 +0000 @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 2021-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2021-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -21,6 +21,8 @@ * DEALINGS IN THE SOFTWARE. */ +#define NVOC_KERNEL_NVLINK_H_PRIVATE_ACCESS_ALLOWED + #include "os/os.h" #include "kernel/gpu/nvlink/kernel_nvlink.h" #include "kernel/gpu/nvlink/kernel_ioctrl.h" @@ -275,12 +277,14 @@ } peerLinkMask = pKernelNvlink->peerLinkMasks[gpuGetInstance(pRemoteGpu)]; + knvlinkGetEffectivePeerLinkMask_HAL(pGpu, pKernelNvlink, pRemoteGpu, &peerLinkMask); if (peerLinkMask != 0) { portMemSet(&preSetupNvlinkPeerParams, 0, sizeof(preSetupNvlinkPeerParams)); preSetupNvlinkPeerParams.peerId = peerId; preSetupNvlinkPeerParams.peerLinkMask = peerLinkMask; + preSetupNvlinkPeerParams.bEgmPeer = GPU_GET_KERNEL_BUS(pGpu)->p2p.bEgmPeer[peerId]; preSetupNvlinkPeerParams.bNvswitchConn = knvlinkIsGpuConnectedToNvswitch(pGpu, pKernelNvlink); status = knvlinkExecGspRmRpc(pGpu, pKernelNvlink, diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/kernel/gpu/nvlink/arch/turing/kernel_nvlink_tu102.c nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/kernel/gpu/nvlink/arch/turing/kernel_nvlink_tu102.c --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/kernel/gpu/nvlink/arch/turing/kernel_nvlink_tu102.c 2023-10-25 20:21:18.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/kernel/gpu/nvlink/arch/turing/kernel_nvlink_tu102.c 2024-03-05 22:13:44.000000000 +0000 @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 2021-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2021-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -21,6 +21,8 @@ * DEALINGS IN THE SOFTWARE. */ +#define NVOC_KERNEL_NVLINK_H_PRIVATE_ACCESS_ALLOWED + #include "os/os.h" #include "kernel/gpu/nvlink/kernel_nvlink.h" #include "kernel/gpu/nvlink/kernel_ioctrl.h" diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/kernel/gpu/nvlink/arch/volta/kernel_minion_gv100.c nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/kernel/gpu/nvlink/arch/volta/kernel_minion_gv100.c --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/kernel/gpu/nvlink/arch/volta/kernel_minion_gv100.c 2023-10-25 20:21:18.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/kernel/gpu/nvlink/arch/volta/kernel_minion_gv100.c 2024-03-05 22:13:44.000000000 +0000 @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2022-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -21,6 +21,11 @@ * DEALINGS IN THE SOFTWARE. */ +#define NVOC_KERNEL_IOCTRL_H_PRIVATE_ACCESS_ALLOWED + +// FIXME XXX +#define NVOC_KERNEL_NVLINK_H_PRIVATE_ACCESS_ALLOWED + #include "os/os.h" #include "nvRmReg.h" #include "kernel/gpu/nvlink/kernel_nvlink.h" diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/kernel/gpu/nvlink/arch/volta/kernel_nvlink_gv100.c nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/kernel/gpu/nvlink/arch/volta/kernel_nvlink_gv100.c --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/kernel/gpu/nvlink/arch/volta/kernel_nvlink_gv100.c 2023-10-25 20:21:18.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/kernel/gpu/nvlink/arch/volta/kernel_nvlink_gv100.c 2024-03-05 22:13:44.000000000 +0000 @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 2021-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2021-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -21,6 +21,8 @@ * DEALINGS IN THE SOFTWARE. */ +#define NVOC_KERNEL_NVLINK_H_PRIVATE_ACCESS_ALLOWED + #include "os/os.h" #include "kernel/gpu/nvlink/kernel_nvlink.h" #include "os/os.h" @@ -330,27 +332,32 @@ NV_ASSERT_OR_RETURN(bLinkDisconnected != NULL, NV_ERR_INVALID_ARGUMENT); - NV2080_CTRL_NVLINK_GET_LINK_AND_CLOCK_INFO_PARAMS params; + NV2080_CTRL_NVLINK_GET_LINK_AND_CLOCK_INFO_PARAMS *pParams = + portMemAllocNonPaged(sizeof(*pParams)); + if (pParams == NULL) + { + return NV_ERR_NO_MEMORY; + } - portMemSet(¶ms, 0, sizeof(params)); - params.linkMask = pKernelNvlink->enabledLinks; + portMemSet(pParams, 0, sizeof(*pParams)); + pParams->linkMask = pKernelNvlink->enabledLinks; status = knvlinkExecGspRmRpc(pGpu, pKernelNvlink, NV2080_CTRL_CMD_NVLINK_GET_LINK_AND_CLOCK_INFO, - (void *)¶ms, sizeof(params)); + (void *)pParams, sizeof(*pParams)); if (status != NV_OK) - return status; + goto cleanup; FOR_EACH_INDEX_IN_MASK(32, linkId, pKernelNvlink->enabledLinks) { - if ((params.linkInfo[linkId].linkState == NVLINK_LINKSTATE_SAFE) && - (params.linkInfo[linkId].txSublinkState == NVLINK_SUBLINK_STATE_TX_OFF) && - (params.linkInfo[linkId].rxSublinkState == NVLINK_SUBLINK_STATE_RX_OFF)) + if ((pParams->linkInfo[linkId].linkState == NVLINK_LINKSTATE_SAFE) && + (pParams->linkInfo[linkId].txSublinkState == NVLINK_SUBLINK_STATE_TX_OFF) && + (pParams->linkInfo[linkId].rxSublinkState == NVLINK_SUBLINK_STATE_RX_OFF)) { // Case 1: Pseudo-clean shutdown bLinkDisconnected[linkId] = NV_TRUE; } - else if (params.linkInfo[linkId].bLinkReset) + else if (pParams->linkInfo[linkId].bLinkReset) { // Case 2: Link reset post shutdown bLinkDisconnected[linkId] = NV_TRUE; @@ -363,6 +370,9 @@ } FOR_EACH_INDEX_IN_MASK_END; +cleanup: + portMemFree(pParams); + return status; } diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/kernel/gpu/nvlink/common_nvlinkapi.c nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/kernel/gpu/nvlink/common_nvlinkapi.c --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/kernel/gpu/nvlink/common_nvlinkapi.c 2023-10-25 20:21:18.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/kernel/gpu/nvlink/common_nvlinkapi.c 2024-03-05 22:13:44.000000000 +0000 @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 1993-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 1993-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -21,6 +21,8 @@ * DEALINGS IN THE SOFTWARE. */ +#define NVOC_KERNEL_NVLINK_H_PRIVATE_ACCESS_ALLOWED + #include "gpu/gpu.h" #include "gpu/subdevice/subdevice.h" #include "vgpu/rpc.h" @@ -589,6 +591,7 @@ NvBool bMIGNvLinkP2PSupported = ((pKernelMIGManager != NULL) && kmigmgrIsMIGNvlinkP2PSupported(pGpu, pKernelMIGManager)); NV_STATUS status = NV_OK; + NvBool bIsNvlinkReady = NV_TRUE; NvU8 i = 0; struct { @@ -621,7 +624,7 @@ FOR_EACH_INDEX_IN_MASK(32, i, pParams->enabledLinkMask) { NV2080_CTRL_NVLINK_DEVICE_INFO *pDeviceInfo = &pParams->linkInfo[i].remoteDeviceInfo; - OBJGPU *pLoopGpu = gpumgrGetGpuFromUuid(pDeviceInfo->deviceUUID, + OBJGPU *pLoopGpu = gpumgrGetGpuFromUuid(pDeviceInfo->deviceUUID, DRF_DEF(2080_GPU_CMD, _GPU_GET_GID_FLAGS, _TYPE, _SHA1) | DRF_DEF(2080_GPU_CMD, _GPU_GET_GID_FLAGS, _FORMAT, _BINARY)); @@ -696,12 +699,16 @@ // as not ready // status = knvlinkCoreGetRemoteDeviceInfo(pGpu, pKernelNvlink); - if (status != NV_OK) + if (status == NV_ERR_NOT_READY) { NV_PRINTF(LEVEL_INFO, "Nvlink is not ready yet!\n"); - status = NV_ERR_NOT_READY; + bIsNvlinkReady = NV_FALSE; + } + else if (status != NV_OK) + { goto done; } + } // @@ -711,7 +718,8 @@ // knvlinkFilterBridgeLinks_HAL(pGpu, pKernelNvlink); - pParams->enabledLinkMask = pKernelNvlink->enabledLinks; + // If nvlink is not ready don't report back any links as being enabled + pParams->enabledLinkMask = (bIsNvlinkReady) ? pKernelNvlink->enabledLinks : 0x0; pTmpData->nvlinkLinkAndClockInfoParams.linkMask = pParams->enabledLinkMask; pTmpData->nvlinkLinkAndClockInfoParams.bSublinkStateInst = pParams->bSublinkStateInst; diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/kernel/gpu/nvlink/kernel_ioctrl.c nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/kernel/gpu/nvlink/kernel_ioctrl.c --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/kernel/gpu/nvlink/kernel_ioctrl.c 2023-10-25 20:21:18.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/kernel/gpu/nvlink/kernel_ioctrl.c 2024-03-05 22:13:44.000000000 +0000 @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 2020-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2020-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -21,6 +21,8 @@ * DEALINGS IN THE SOFTWARE. */ +#define NVOC_KERNEL_IOCTRL_H_PRIVATE_ACCESS_ALLOWED + #include "kernel/gpu/nvlink/kernel_nvlink.h" #include "kernel/gpu/nvlink/kernel_ioctrl.h" diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/kernel/gpu/nvlink/kernel_nvlink.c nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/kernel/gpu/nvlink/kernel_nvlink.c --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/kernel/gpu/nvlink/kernel_nvlink.c 2023-10-25 20:21:18.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/kernel/gpu/nvlink/kernel_nvlink.c 2024-03-05 22:13:45.000000000 +0000 @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 2020-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2020-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -21,6 +21,11 @@ * DEALINGS IN THE SOFTWARE. */ +#define NVOC_KERNEL_NVLINK_H_PRIVATE_ACCESS_ALLOWED + +// FIXME XXX +#define NVOC_KERNEL_IOCTRL_H_PRIVATE_ACCESS_ALLOWED + #include "os/os.h" #include "core/hal.h" #include "core/info_block.h" @@ -204,6 +209,11 @@ return NV_FALSE; } + if (knvlinkIsBandwidthModeOff(pKernelNvlink)) + { + return NV_FALSE; + } + // Get the Nvlink P2P connections from the core library status = knvlinkGetP2pConnectionStatus(pGpu, pKernelNvlink, pPeerGpu); @@ -367,7 +377,11 @@ } // Get the remote ends of the links of local GPU from the nvlink core - knvlinkCoreGetRemoteDeviceInfo(pGpu0, pKernelNvlink0); + status = knvlinkCoreGetRemoteDeviceInfo(pGpu0, pKernelNvlink0); + if (status != NV_OK) + { + return status; + } // Post topology link enable on links of local GPU status = knvlinkEnableLinksPostTopology_HAL(pGpu0, pKernelNvlink0, @@ -404,7 +418,11 @@ if (knvlinkGetNumLinksToPeer(pGpu1, pKernelNvlink1, pGpu0) != numPeerLinks) { // Get the remote ends of the links of remote GPU from the nvlink core - knvlinkCoreGetRemoteDeviceInfo(pGpu1, pKernelNvlink1); + status = knvlinkCoreGetRemoteDeviceInfo(pGpu1, pKernelNvlink1); + if (status != NV_OK) + { + return status; + } // Post topology link enable on links of remote GPU status = knvlinkEnableLinksPostTopology_HAL(pGpu1, pKernelNvlink1, @@ -643,7 +661,7 @@ NV_ASSERT((pRsvd[0] == 0) && portMemCmp(pRsvd, pRsvd + 1, sizeof(pHeader->reserved) - 1) == 0); - pKernelNvlink->inbandCallback[pHeader->type].pCallback(pGpu, pData); + (void)pKernelNvlink->inbandCallback[pHeader->type].pCallback(gpuInstance, pData); } NV_STATUS @@ -1068,7 +1086,7 @@ // If GFW is booted and running through link-training, then no need to tear-down the // links to reset. Exit out early from the function // - if (!bForceShutdown && pKernelNvlink->getProperty(pNvlink, PDB_PROP_KNVLINK_MINION_GFW_BOOT)) + if (!bForceShutdown && pKernelNvlink->getProperty(pKernelNvlink, PDB_PROP_KNVLINK_MINION_GFW_BOOT)) { return NV_OK; } @@ -1180,10 +1198,6 @@ { case NVLINK_VERSION_22: { - // Regkeys finally decide whether or not the power state is supported - pKernelNvlink->setProperty(pKernelNvlink, PDB_PROP_KNVLINK_SINGLE_LANE_POWER_STATE_ENABLED, - (pKernelNvlink->bDisableSingleLaneMode ? NV_FALSE : NV_TRUE)); - // NVLink L2 is supported only on MODS and Windows LDDM if (RMCFG_FEATURE_PLATFORM_WINDOWS_LDDM || RMCFG_FEATURE_MODS_FEATURES) { @@ -1193,15 +1207,6 @@ break; } - case NVLINK_VERSION_31: - case NVLINK_VERSION_30: - case NVLINK_VERSION_20: - { - // Regkeys finally decide whether or not the power state is supported - pKernelNvlink->setProperty(pKernelNvlink, PDB_PROP_KNVLINK_SINGLE_LANE_POWER_STATE_ENABLED, - (pKernelNvlink->bDisableSingleLaneMode ? NV_FALSE : NV_TRUE)); - break; - } default: break; } diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/kernel/gpu/nvlink/kernel_nvlinkapi.c nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/kernel/gpu/nvlink/kernel_nvlinkapi.c --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/kernel/gpu/nvlink/kernel_nvlinkapi.c 2023-10-25 20:21:18.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/kernel/gpu/nvlink/kernel_nvlinkapi.c 2024-03-05 22:13:45.000000000 +0000 @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 2026-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2026-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -21,6 +21,8 @@ * DEALINGS IN THE SOFTWARE. */ +#define NVOC_KERNEL_NVLINK_H_PRIVATE_ACCESS_ALLOWED + #include "os/os.h" #include "core/hal.h" #include "core/info_block.h" diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/kernel/gpu/nvlink/kernel_nvlinkcorelib.c nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/kernel/gpu/nvlink/kernel_nvlinkcorelib.c --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/kernel/gpu/nvlink/kernel_nvlinkcorelib.c 2023-10-25 20:21:18.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/kernel/gpu/nvlink/kernel_nvlinkcorelib.c 2024-03-05 22:13:45.000000000 +0000 @@ -21,6 +21,8 @@ * DEALINGS IN THE SOFTWARE. */ +#define NVOC_KERNEL_NVLINK_H_PRIVATE_ACCESS_ALLOWED + #include "os/os.h" #include "core/hal.h" #include "core/info_block.h" diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/kernel/gpu/nvlink/kernel_nvlinkcorelibcallback.c nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/kernel/gpu/nvlink/kernel_nvlinkcorelibcallback.c --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/kernel/gpu/nvlink/kernel_nvlinkcorelibcallback.c 2023-10-25 20:21:18.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/kernel/gpu/nvlink/kernel_nvlinkcorelibcallback.c 2024-03-05 22:13:45.000000000 +0000 @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 2020-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2020-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -21,6 +21,11 @@ * DEALINGS IN THE SOFTWARE. */ +#define NVOC_KERNEL_NVLINK_H_PRIVATE_ACCESS_ALLOWED + +// FIXME XXX +#define NVOC_KERNEL_IOCTRL_H_PRIVATE_ACCESS_ALLOWED + #include "os/os.h" #include "core/hal.h" #include "core/info_block.h" @@ -493,7 +498,7 @@ OBJGPU *pGpu = NULL; KernelNvlink *pKernelNvlink = NULL; KernelIoctrl *pKernelIoctrl = NULL; - NV_STATUS status = NV_OK; + NV_STATUS status = NV_OK; NvU8 linkIndex; NV2080_CTRL_NVLINK_CORE_CALLBACK_PARAMS params; NV2080_CTRL_NVLINK_CALLBACK_SET_DL_LINK_MODE_PARAMS @@ -514,6 +519,9 @@ linkIndex = pNvlinkLink->linkId; pKernelIoctrl = KNVLINK_LINK_GET_IOCTRL(pKernelNvlink, linkIndex); + if (pKernelIoctrl == NULL) + return 0; + // If link training is disabled through regkey if (pKernelNvlink->bSkipLinkTraining) { @@ -1501,7 +1509,7 @@ ) { KNVLINK_RM_LINK *pNvlinkLink = (KNVLINK_RM_LINK *) link->link_info; - POBJGPU pGpu = pNvlinkLink->pGpu; + OBJGPU *pGpu = pNvlinkLink->pGpu; KernelNvlink * pKernelNvlink = NULL; NV_STATUS status; diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/kernel/gpu/nvlink/kernel_nvlinkcorelibtrain.c nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/kernel/gpu/nvlink/kernel_nvlinkcorelibtrain.c --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/kernel/gpu/nvlink/kernel_nvlinkcorelibtrain.c 2023-10-25 20:21:18.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/kernel/gpu/nvlink/kernel_nvlinkcorelibtrain.c 2024-03-05 22:13:45.000000000 +0000 @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 2020-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2020-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -21,6 +21,8 @@ * DEALINGS IN THE SOFTWARE. */ +#define NVOC_KERNEL_NVLINK_H_PRIVATE_ACCESS_ALLOWED + #include "os/os.h" #include "core/hal.h" #include "core/info_block.h" @@ -80,7 +82,7 @@ NvBool bNvswitchProxyPresent = NV_FALSE; NvBool bUpdateConnStatus = NV_FALSE; NvBool bCheckDegradedMode = NV_FALSE; - nvlink_conn_info conn_info; + nvlink_conn_info conn_info = {0}; NvU32 linkId; NvU32 numActiveLinksPerIoctrl = 0; NvU32 numLinksPerIoctrl = 0; @@ -100,6 +102,9 @@ bNvswitchProxyPresent = knvlinkIsNvswitchProxyPresent(pGpu, pKernelNvlink); } + // + // UpdatePostRxDetect has to happen only if there is a disconnected link + // if (pKernelNvlink->disconnectedLinkMask && pKernelNvlink->bEnableAli) { // Update the post Rx Det link Mask for the GPU @@ -109,18 +114,11 @@ if (pKernelNvlink->ipVerNvlink >= NVLINK_VERSION_40 && !bNvswitchProxyPresent && !pSys->getProperty(pSys, PDB_PROP_SYS_FABRIC_IS_EXTERNALLY_MANAGED) && - pKernelNvlink->pNvlinkDev != NULL) + pKernelNvlink->pNvlinkDev != NULL && + !pKernelNvlink->bFloorSwept) { - // The path here is important not getting the connection info - FOR_EACH_INDEX_IN_MASK(32, linkId, pKernelNvlink->enabledLinks) - { - nvlink_lib_discover_and_get_remote_conn_info( - pKernelNvlink->nvlinkLinks[linkId].core_link, &conn_info, 0); - } - FOR_EACH_INDEX_IN_MASK_END; - numLinksPerIoctrl = knvlinkGetTotalNumLinksPerIoctrl(pGpu, pKernelNvlink); - status = knvlinkFloorSweep_IMPL(pGpu, pKernelNvlink, + status = knvlinkFloorSweep(pGpu, pKernelNvlink, numLinksPerIoctrl, &numActiveLinksPerIoctrl); if (status != NV_OK) @@ -160,7 +158,7 @@ // discover remote information explicitly. // nvlink_lib_discover_and_get_remote_conn_info( - pKernelNvlink->nvlinkLinks[linkId].core_link, &conn_info, 0); + pKernelNvlink->nvlinkLinks[linkId].core_link, &conn_info, flags); } else { @@ -176,7 +174,8 @@ // if (!conn_info.bConnected && (bNvswitchProxyPresent || - GPU_IS_NVSWITCH_DETECTED(pGpu))) + (!pSys->getProperty(pSys, PDB_PROP_SYS_NVSWITCH_IS_PRESENT) && + GPU_IS_NVSWITCH_DETECTED(pGpu)))) { conn_info.bConnected = NV_TRUE; conn_info.deviceType = NVLINK_DEVICE_TYPE_NVSWITCH; @@ -1037,7 +1036,7 @@ NvU32 linkId; // Skip link shutdown where fabric manager is present, for nvlink version bellow 4.0 - if ((pKernelNvlink->ipVerNvlink < NVLINK_VERSION_40 && + if ((pKernelNvlink->ipVerNvlink < NVLINK_VERSION_40 && pSys->getProperty(pSys, PDB_PROP_SYS_FABRIC_IS_EXTERNALLY_MANAGED)) || (pKernelNvlink->pNvlinkDev == NULL)) { @@ -1056,7 +1055,7 @@ return NV_OK; } - if (!bForceShutdown && pKernelNvlink->getProperty(pNvlink, PDB_PROP_KNVLINK_MINION_GFW_BOOT)) + if (!bForceShutdown && pKernelNvlink->getProperty(pKernelNvlink, PDB_PROP_KNVLINK_MINION_GFW_BOOT)) { NV_PRINTF(LEVEL_INFO, "GFW boot is enabled. Link shutdown is not required, skipping\n"); @@ -1075,7 +1074,7 @@ { OBJGPU* pRemoteGpu = gpumgrGetGpuFromBusInfo( pKernelNvlink->nvlinkLinks[linkId].remoteEndInfo.domain, - pKernelNvlink->nvlinkLinks[linkId].remoteEndInfo.bus, + pKernelNvlink->nvlinkLinks[linkId].remoteEndInfo.bus, pKernelNvlink->nvlinkLinks[linkId].remoteEndInfo.device); if (API_GPU_IN_RESET_SANITY_CHECK(pRemoteGpu)) { @@ -1136,7 +1135,7 @@ NvU32 linkId; // Skip link reset where fabric manager is present, for nvlink version bellow 4.0 - if ((pKernelNvlink->ipVerNvlink < NVLINK_VERSION_40 && + if ((pKernelNvlink->ipVerNvlink < NVLINK_VERSION_40 && pSys->getProperty(pSys, PDB_PROP_SYS_FABRIC_IS_EXTERNALLY_MANAGED)) || (pKernelNvlink->pNvlinkDev == NULL)) { @@ -1333,6 +1332,7 @@ NvU32 linkId; NvU32 tmpDisabledLinkMask = 0; NvU32 tmpEnabledLinkMask = 0; + nvlink_conn_info conn_info; *pNumActiveLinksPerIoctrl = knvlinkGetNumActiveLinksPerIoctrl(pGpu, pKernelNvlink); if (!knvlinkIsFloorSweepingNeeded_HAL(pGpu, pKernelNvlink, *pNumActiveLinksPerIoctrl, numLinksPerIoctrl)) @@ -1340,6 +1340,14 @@ return NV_OK; } + // The path here is important not getting the connection info + FOR_EACH_INDEX_IN_MASK(32, linkId, pKernelNvlink->enabledLinks) + { + nvlink_lib_discover_and_get_remote_conn_info( + pKernelNvlink->nvlinkLinks[linkId].core_link, &conn_info, 0); + } + FOR_EACH_INDEX_IN_MASK_END; + // // This call must be before the floorswept to cache the NVLink bridge // information in physical RM. @@ -2438,7 +2446,7 @@ } NV_PRINTF(LEVEL_INFO, "GPU%02u cached topology:\n", gpuGetInstance(pGpu)); - + NV2080_CTRL_NVLINK_HSHUB_GET_SYSMEM_NVLINK_MASK_PARAMS params; portMemSet(¶ms, 0, sizeof(params)); diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/kernel/gpu/nvlink/kernel_nvlinkoverrides.c nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/kernel/gpu/nvlink/kernel_nvlinkoverrides.c --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/kernel/gpu/nvlink/kernel_nvlinkoverrides.c 2023-10-25 20:21:18.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/kernel/gpu/nvlink/kernel_nvlinkoverrides.c 2024-03-05 22:13:45.000000000 +0000 @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 2020-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2020-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -21,6 +21,8 @@ * DEALINGS IN THE SOFTWARE. */ +#define NVOC_KERNEL_NVLINK_H_PRIVATE_ACCESS_ALLOWED + #include "kernel/gpu/nvlink/kernel_nvlink.h" #include "kernel/gpu/nvlink/kernel_ioctrl.h" #include "nvRmReg.h" @@ -59,7 +61,6 @@ pKernelNvlink->nvlinkLinkSpeed = NV_REG_STR_RM_NVLINK_SPEED_CONTROL_SPEED_DEFAULT; // Power management settings - pKernelNvlink->bDisableSingleLaneMode = NV_FALSE; pKernelNvlink->bDisableL2Mode = NV_FALSE; // Debug Settings @@ -225,15 +226,6 @@ { NV_PRINTF(LEVEL_INFO, "RM NVLink Link PM controlled via regkey\n"); - // Whether one-eighth mode has been disabled by regkey - if (FLD_TEST_DRF(_REG_STR_RM, _NVLINK_LINK_PM_CONTROL, _SINGLE_LANE_MODE, - _DISABLE, regdata)) - { - NV_PRINTF(LEVEL_INFO, - "NVLink single-lane power state disabled via regkey\n"); - pKernelNvlink->bDisableSingleLaneMode = NV_TRUE; - } - // Whether L2 power state has been disabled by regkey if (FLD_TEST_DRF(_REG_STR_RM, _NVLINK_LINK_PM_CONTROL, _L2_MODE, _DISABLE, regdata)) diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/kernel/gpu/nvlink/kernel_nvlinkstate.c nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/kernel/gpu/nvlink/kernel_nvlinkstate.c --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/kernel/gpu/nvlink/kernel_nvlinkstate.c 2023-10-25 20:21:19.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/kernel/gpu/nvlink/kernel_nvlinkstate.c 2024-03-05 22:13:45.000000000 +0000 @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 2020-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2020-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -21,6 +21,11 @@ * DEALINGS IN THE SOFTWARE. */ +#define NVOC_KERNEL_NVLINK_H_PRIVATE_ACCESS_ALLOWED + +// FIXME XXX +#define NVOC_KERNEL_IOCTRL_H_PRIVATE_ACCESS_ALLOWED + #include "kernel/gpu/nvlink/kernel_nvlink.h" #include "kernel/gpu/nvlink/kernel_ioctrl.h" #include "kernel/gpu/mem_sys/kern_mem_sys.h" @@ -193,7 +198,7 @@ return status; } - // + // // When GSP inform about link error occurs on this GPU // it will updated to NV_TRUE // @@ -248,6 +253,10 @@ { NV_STATUS status = NV_OK; + // Mark NVLINK as absent when HCC is enabled + if (gpuIsCCFeatureEnabled(pGpu)) + return NV_FALSE; + // On GSP clients, retrieve all device discovery info from GSP through RPC status = knvlinkCopyNvlinkDeviceInfo(pGpu, pKernelNvlink); if (status != NV_OK) @@ -1076,15 +1085,15 @@ if (!pKernelNvlink) { NV_PRINTF(LEVEL_ERROR, - "Failed to get Local Nvlink info for linkId %d to update Degraded GPU%d status\n", + "Failed to get Local Nvlink info for linkId %d to update Degraded GPU%d status\n", linkId, pGpu->gpuInstance); - - return; + + return; } if(pKernelNvlink->bIsGpuDegraded) { - return; + return; } //Find the remote GPU/NVLink attached to this link, if any @@ -1100,27 +1109,27 @@ if (pRemoteGpu == NULL) { NV_PRINTF(LEVEL_ERROR, - "Failed to get Remote GPU info for linkId %d to update Degraded GPU%d status\n", + "Failed to get Remote GPU info for linkId %d to update Degraded GPU%d status\n", linkId, pGpu->gpuInstance); - - return; + + return; } pRemoteKernelNvlink = GPU_GET_KERNEL_NVLINK(pRemoteGpu); if (!pRemoteKernelNvlink) { NV_PRINTF(LEVEL_ERROR, - "Failed to get Remote Nvlink info for linkId %d to update Degraded GPU%d status\n", + "Failed to get Remote Nvlink info for linkId %d to update Degraded GPU%d status\n", linkId, pGpu->gpuInstance); - - return; + + return; } if (pRemoteKernelNvlink->bIsGpuDegraded == NV_FALSE) { pKernelNvlink->bIsGpuDegraded = NV_TRUE; NV_PRINTF(LEVEL_ERROR, - "GPU%d marked Degraded for error on linkId %d \n", + "GPU%d marked Degraded for error on linkId %d \n", pGpu->gpuInstance, linkId); // shutdown all the links on this GPU @@ -1131,7 +1140,7 @@ "failed to shutdown links on degraded GPU%d\n", pGpu->gpuInstance); } } - + return; } @@ -1147,7 +1156,7 @@ // Destroy the RM NVLink state _knvlinkPurgeState(pGpu, pKernelNvlink); - + // Free Ioctrls for (ioctrlIdx = 0; ioctrlIdx < NVLINK_MAX_IOCTRLS_SW; ioctrlIdx++) { diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/kernel/gpu/perf/kern_perf.c nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/kernel/gpu/perf/kern_perf.c --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/kernel/gpu/perf/kern_perf.c 2023-10-25 20:21:19.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/kernel/gpu/perf/kern_perf.c 2024-03-05 22:13:46.000000000 +0000 @@ -54,40 +54,49 @@ NV_STATUS kperfStateInitLocked_IMPL(OBJGPU *pGpu, KernelPerf *pKernelPerf) { - OBJSYS *pSys = SYS_GET_INSTANCE(); - PlatformRequestHandler *pPlatformRequestHandler = SYS_GET_PFM_REQ_HNDLR(pSys); + NV_STATUS status = NV_OK; // Initialize SW state corresponding to SLI GPU Boost synchronization. status = kperfGpuBoostSyncStateInit(pGpu, pKernelPerf); - // Initialize PFM_REQ_HNDLR module which is a child of OBJSYS - if (RMCFG_MODULE_PLATFORM_REQUEST_HANDLER && pPlatformRequestHandler != NULL) { - pfmreqhndlrStateInit(pPlatformRequestHandler); + OBJSYS *pSys = SYS_GET_INSTANCE(); + PlatformRequestHandler *pPlatformRequestHandler = SYS_GET_PFM_REQ_HNDLR(pSys); + + + // Initialize PFM_REQ_HNDLR module which is a child of OBJSYS + if (pPlatformRequestHandler != NULL) + { + pfmreqhndlrStateInit(pPlatformRequestHandler); + } } return status; } - + /*! * @copydoc kperfStateLoad */ NV_STATUS kperfStateLoad_IMPL(OBJGPU *pGpu, KernelPerf *pKernelPerf, NvU32 flags) { - OBJSYS *pSys = SYS_GET_INSTANCE(); - OBJCL *pCl = SYS_GET_CL(pSys); - PlatformRequestHandler *pPlatformRequestHandler = SYS_GET_PFM_REQ_HNDLR(pSys); - // Initialize SW state corresponding to SLI GPU Boost synchronization. kperfGpuBoostSyncStateInit(pGpu, pKernelPerf); - // Load PFM_REQ_HNDLR module which is a child of OBJSYS - // Skip pfmreqhndlrStateLoad on eGPU - if (!(pCl->getProperty(pCl, PDB_PROP_CL_IS_EXTERNAL_GPU)) && RMCFG_MODULE_PLATFORM_REQUEST_HANDLER && (pPlatformRequestHandler != NULL)) { - pfmreqhndlrStateLoad(pPlatformRequestHandler); + OBJSYS *pSys = SYS_GET_INSTANCE(); + OBJCL *pCl = SYS_GET_CL(pSys); + PlatformRequestHandler *pPlatformRequestHandler = SYS_GET_PFM_REQ_HNDLR(pSys); + + + // Load PFM_REQ_HNDLR module which is a child of OBJSYS + // Skip pfmreqhndlrStateLoad on eGPU + if (!(pCl->getProperty(pCl, PDB_PROP_CL_IS_EXTERNAL_GPU)) && + (pPlatformRequestHandler != NULL)) + { + pfmreqhndlrStateLoad(pPlatformRequestHandler); + } } return NV_OK; @@ -104,13 +113,15 @@ NvU32 flags ) { - OBJSYS *pSys = SYS_GET_INSTANCE(); - PlatformRequestHandler *pPlatformRequestHandler = SYS_GET_PFM_REQ_HNDLR(pSys); - - if (RMCFG_MODULE_PLATFORM_REQUEST_HANDLER && (pPlatformRequestHandler != NULL)) { - // Unload PFM_REQ_HNDLR module which is a child of OBJSYS - pfmreqhndlrStateUnload(pPlatformRequestHandler); + OBJSYS *pSys = SYS_GET_INSTANCE(); + PlatformRequestHandler *pPlatformRequestHandler = SYS_GET_PFM_REQ_HNDLR(pSys); + + if ((pPlatformRequestHandler != NULL)) + { + // Unload PFM_REQ_HNDLR module which is a child of OBJSYS + pfmreqhndlrStateUnload(pPlatformRequestHandler); + } } return NV_OK; @@ -126,13 +137,15 @@ KernelPerf *pKernelPerf ) { - OBJSYS *pSys = SYS_GET_INSTANCE(); - PlatformRequestHandler *pPlatformRequestHandler = SYS_GET_PFM_REQ_HNDLR(pSys); - - // destroy PFM_REQ_HNDLR module state - if (RMCFG_MODULE_PLATFORM_REQUEST_HANDLER && (pPlatformRequestHandler != NULL)) { - pfmreqhndlrStateDestroy(pPlatformRequestHandler); + OBJSYS *pSys = SYS_GET_INSTANCE(); + PlatformRequestHandler *pPlatformRequestHandler = SYS_GET_PFM_REQ_HNDLR(pSys); + + // destroy PFM_REQ_HNDLR module state + if (pPlatformRequestHandler != NULL) + { + pfmreqhndlrStateDestroy(pPlatformRequestHandler); + } } } diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/kernel/gpu/perf/kern_perf_boost.c nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/kernel/gpu/perf/kern_perf_boost.c --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/kernel/gpu/perf/kern_perf_boost.c 2023-10-25 20:21:19.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/kernel/gpu/perf/kern_perf_boost.c 2024-03-05 22:13:46.000000000 +0000 @@ -50,6 +50,8 @@ KernelPerf *pKernelPerf = GPU_GET_KERNEL_PERF(pGpu); NV_STATUS status = NV_OK; + NV_CHECK_OR_RETURN(LEVEL_INFO, (pKernelPerf != NULL), NV_ERR_NOT_SUPPORTED); + status = kperfBoostSet_HAL(pKernelPerf, pSubdevice, pBoostParams); return status; } diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/kernel/gpu/perf/kern_perf_gpuboostsync.c nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/kernel/gpu/perf/kern_perf_gpuboostsync.c --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/kernel/gpu/perf/kern_perf_gpuboostsync.c 2023-10-25 20:21:19.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/kernel/gpu/perf/kern_perf_gpuboostsync.c 2024-03-05 22:13:46.000000000 +0000 @@ -378,7 +378,7 @@ } } } - // Intentionaly ignoring the status as we want to rollback the algorithm + // Intentionaly ignoring the status as we want to rollback the algorithm // activation and return previously failing status if (pGpuItr == pGpuItr2) diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/kernel/gpu/perf/kern_perf_pm.c nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/kernel/gpu/perf/kern_perf_pm.c --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/kernel/gpu/perf/kern_perf_pm.c 2023-10-25 20:21:19.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/kernel/gpu/perf/kern_perf_pm.c 2024-03-05 22:13:46.000000000 +0000 @@ -25,7 +25,7 @@ #include "os/os.h" #include "gpu/subdevice/subdevice.h" #include "rmapi/rmapi.h" -#include "rmapi/rs_utils.h" +#include "rmapi/rs_utils.h" #include "gpu/gpu.h" #include "gpu/perf/kern_perf_pm.h" @@ -66,7 +66,8 @@ RS_ITERATOR it; NV_STATUS status = NV_OK; - if (NV_OK != serverutilGetClientUnderLock(hClient, &pClient)) + pClient = serverutilGetClientUnderLock(hClient); + if (pClient == NULL) { return NV_ERR_INVALID_CLIENT; } @@ -97,7 +98,7 @@ NV2080_CTRL_INTERNAL_PERF_PERFMON_CLIENT_RESERVATION_CHECK_PARAMS params = {0}; params.bReservation = bReservation; - status = pRmApi->Control(pRmApi, + status = pRmApi->Control(pRmApi, hClient, it.pResourceRef->hResource, NV2080_CTRL_CMD_INTERNAL_PERF_PERFMON_CLIENT_RESERVATION_CHECK, @@ -220,7 +221,7 @@ NV_CHECK_OK_OR_CAPTURE_FIRST_ERROR(status, LEVEL_ERROR, - pRmApi->Control(pRmApi, + pRmApi->Control(pRmApi, hClient, it.pResourceRef->hResource, NV2080_CTRL_CMD_INTERNAL_PERF_PERFMON_CLIENT_RESERVATION_SET, diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/kernel/gpu/perf/kern_perf_pwr.c nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/kernel/gpu/perf/kern_perf_pwr.c --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/kernel/gpu/perf/kern_perf_pwr.c 2023-10-25 20:21:19.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/kernel/gpu/perf/kern_perf_pwr.c 2024-03-05 22:13:46.000000000 +0000 @@ -111,7 +111,6 @@ { NvU32 inOutData = 0; NvU16 outDataSize = sizeof(inOutData); - OBJOS *pOS = GPU_GET_OS(pGpu); NV_STATUS status = NV_OK; ACPI_DSM_FUNCTION func = gpuGetPerfPostPowerStateFunc(pGpu); RM_API *pRmApi = GPU_GET_PHYSICAL_RMAPI(pGpu); @@ -141,9 +140,9 @@ inOutData = FLD_SET_DRF_NUM(_ACPI, _CALLBACKS_ARG, _CURRENTPOWERSTATE, ctrlParams.powerState, inOutData); - status = pOS->osCallACPI_DSM(pGpu, func, - NV_ACPI_GENERIC_FUNC_CALLBACKS, - &inOutData, &outDataSize); + status = osCallACPI_DSM(pGpu, func, + NV_ACPI_GENERIC_FUNC_CALLBACKS, + &inOutData, &outDataSize); if (status != NV_OK) { NV_PRINTF(LEVEL_ERROR, "PostPState callback error:0x%x\n", status); @@ -192,7 +191,7 @@ NV2080_CTRL_PERF_SET_POWERSTATE_PARAMS *pPowerInfoParams ) { - POBJGPU pGpu = GPU_RES_GET_GPU(pSubdevice); + OBJGPU *pGpu = GPU_RES_GET_GPU(pSubdevice); RM_API *pRmApi = GPU_GET_PHYSICAL_RMAPI(pGpu); KernelPerf *pKernelPerf = GPU_GET_KERNEL_PERF(pGpu); NV_STATUS status = NV_OK; diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/kernel/gpu/perf/kern_perfbuffer.c nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/kernel/gpu/perf/kern_perfbuffer.c --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/kernel/gpu/perf/kern_perfbuffer.c 2023-10-25 20:21:19.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/kernel/gpu/perf/kern_perfbuffer.c 2024-03-05 22:13:46.000000000 +0000 @@ -58,7 +58,7 @@ NV_CHECK_OK_OR_RETURN(LEVEL_NOTICE, perfbufferPrivilegeCheck(pResource)); NV_RM_RPC_ALLOC_OBJECT(pGpu, hClient, hParent, hMemory, class, - pParams->pAllocParams, status); + pParams->pAllocParams, pParams->paramsSize, status); return status; } diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/kernel/gpu/pmu/arch/ada/kern_pmu_ad102.c nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/kernel/gpu/pmu/arch/ada/kern_pmu_ad102.c --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/kernel/gpu/pmu/arch/ada/kern_pmu_ad102.c 2023-10-25 20:21:20.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/kernel/gpu/pmu/arch/ada/kern_pmu_ad102.c 1970-01-01 00:00:00.000000000 +0000 @@ -1,88 +0,0 @@ -/* - * SPDX-FileCopyrightText: Copyright (c) 2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. - * SPDX-License-Identifier: MIT - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER - * DEALINGS IN THE SOFTWARE. - */ - -#include "os/os.h" -#include "gpu/pmu/kern_pmu.h" - -#include "published/ada/ad102/dev_bus.h" -#include "published/ada/ad102/dev_bus_addendum.h" - -static NvBool _kpmuPreOsCheckErotGrantAllowed_AD102(OBJGPU *pGpu, void *pVoid); - -/*! - * Signals preOs to have eRoT hand over control of EEPROM to RM - * - * @param[in] pGpu OBJGPU pointer - * @param[in] pKernelPmu KernelPmu pointer - * - * @returns NV_OK if RM has control of the EEPROM - * @returns NV_ERR_TIMEOUT if preOs fails to hand over control of the EEPROM - * - */ -NV_STATUS -kpmuPreOsGlobalErotGrantRequest_AD102 -( - OBJGPU *pGpu, - KernelPmu *pKernelPmu -) -{ - NV_STATUS status = NV_OK; - RMTIMEOUT timeout; - NvU32 reg = GPU_REG_RD32(pGpu, NV_PBUS_SW_GLOBAL_EROT_GRANT); - - // Invalid value suggests that there is no ERoT - if (FLD_TEST_DRF(_PBUS, _SW_GLOBAL_EROT_GRANT, _VALID, _NO, reg)) - { - return status; - } - - // Check if grant has already been allowed - if (_kpmuPreOsCheckErotGrantAllowed_AD102(pGpu, NULL)) - { - return status; - } - - reg = FLD_SET_DRF(_PBUS, _SW_GLOBAL_EROT_GRANT, _REQUEST, _SET, reg); - GPU_REG_WR32(pGpu, NV_PBUS_SW_GLOBAL_EROT_GRANT, reg); - - gpuSetTimeout(pGpu, GPU_TIMEOUT_DEFAULT, &timeout, 0); - status = gpuTimeoutCondWait(pGpu, _kpmuPreOsCheckErotGrantAllowed_AD102, NULL, &timeout); - if (status != NV_OK) - { - NV_PRINTF(LEVEL_ERROR, "Timed out waiting for preOs to grant access to EEPROM\n"); - } - - return status; -} - -static NvBool -_kpmuPreOsCheckErotGrantAllowed_AD102 -( - OBJGPU *pGpu, - void *pVoid -) -{ - NvU32 reg = GPU_REG_RD32(pGpu, NV_PBUS_SW_GLOBAL_EROT_GRANT); - - return FLD_TEST_DRF(_PBUS, _SW_GLOBAL_EROT_GRANT, _ALLOW, _YES, reg); -} diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/kernel/gpu/pmu/kern_pmu.c nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/kernel/gpu/pmu/kern_pmu.c --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/kernel/gpu/pmu/kern_pmu.c 2023-10-25 20:21:20.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/kernel/gpu/pmu/kern_pmu.c 2024-03-05 22:13:47.000000000 +0000 @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 2021-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2021-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/kernel/gpu/rc/kernel_rc.c nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/kernel/gpu/rc/kernel_rc.c --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/kernel/gpu/rc/kernel_rc.c 2023-10-25 20:21:20.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/kernel/gpu/rc/kernel_rc.c 2024-03-05 22:13:47.000000000 +0000 @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 2021-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2021-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -184,7 +184,10 @@ { pKernelRc->watchdog.flags |= WATCHDOG_FLAGS_DISABLED; } - + else if (gpuIsCCFeatureEnabled(pGpu) && !gpuIsCCDevToolsModeEnabled(pGpu)) + { + pKernelRc->watchdog.flags |= WATCHDOG_FLAGS_DISABLED; + } dword = 0; if (osReadRegistryDword(pGpu, NV_REG_STR_RM_DO_LOG_RC_EVENTS, &dword) == diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/kernel/gpu/rc/kernel_rc_callback.c nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/kernel/gpu/rc/kernel_rc_callback.c --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/kernel/gpu/rc/kernel_rc_callback.c 2023-10-25 20:21:20.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/kernel/gpu/rc/kernel_rc_callback.c 2024-03-05 22:13:47.000000000 +0000 @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 2021 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2021-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -31,6 +31,7 @@ #include "kernel/gpu/mmu/kern_gmmu.h" #include "kernel/os/os.h" #include "rmapi/client.h" +#include "rmapi/rs_utils.h" #include "ctrl/ctrl506f.h" @@ -147,6 +148,7 @@ if (rmGpuLocksAcquire(GPUS_LOCK_FLAGS_NONE, RM_LOCK_MODULES_RC) == NV_OK) { + RsClient *pClient; KernelChannel *pKernelChannel = NULL; threadStateInitISRAndDeferredIntHandler( @@ -156,11 +158,11 @@ NV_ASSERT_OK_OR_GOTO( status, - serverGetClientUnderLock(&g_resServ, hClient, NULL), + serverGetClientUnderLock(&g_resServ, hClient, &pClient), error_cleanup); NV_ASSERT_OK_OR_GOTO( status, - CliGetKernelChannel(hClient, hChannel, &pKernelChannel), + CliGetKernelChannel(pClient, hChannel, &pKernelChannel), error_cleanup); NV_ASSERT_OR_ELSE(pKernelChannel != NULL, @@ -233,7 +235,6 @@ OBJOS *pOS = SYS_GET_OS(pSys); KernelMIGManager *pKernelMigManager = GPU_GET_KERNEL_MIG_MANAGER(pGpu); RmClient *pClient = NULL; - RsClient *pRsClient; RC_CALLBACK_STATUS clientAction; RM_ENGINE_TYPE localRmEngineType = rmEngineType; NvU32 rcDiagRecOwner = RCDB_RCDIAG_DEFAULT_OWNER; @@ -243,13 +244,7 @@ NV_ASSERT_OR_RETURN(!gpumgrGetBcEnabledStatus(pGpu), bReturn); NV_CHECK_OR_RETURN(LEVEL_ERROR, pKernelChannel != NULL, bReturn); - status = serverGetClientUnderLock(&g_resServ, - RES_GET_CLIENT_HANDLE(pKernelChannel), - &pRsClient); - if (status != NV_OK) - return bReturn; - - pClient = dynamicCast(pRsClient, RmClient); + pClient = dynamicCast(RES_GET_CLIENT(pKernelChannel), RmClient); if (pClient == NULL) return bReturn; @@ -263,7 +258,7 @@ MIG_INSTANCE_REF ref; status = kmigmgrGetInstanceRefFromClient(pGpu, pKernelMigManager, - pRsClient->hClient, + RES_GET_CLIENT_HANDLE(pKernelChannel), &ref); if (status != NV_OK) return bReturn; @@ -293,7 +288,7 @@ Device *pDevice; NV_ASSERT_OK_OR_RETURN( - deviceGetByGpu(pRsClient, pGpu, NV_TRUE, &pDevice)); + deviceGetByGpu(RES_GET_CLIENT(pKernelChannel), pGpu, NV_TRUE, &pDevice)); hDevice = RES_GET_HANDLE(pDevice); diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/kernel/gpu/rc/kernel_rc_ctrl.c nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/kernel/gpu/rc/kernel_rc_ctrl.c --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/kernel/gpu/rc/kernel_rc_ctrl.c 2023-10-25 20:21:20.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/kernel/gpu/rc/kernel_rc_ctrl.c 2024-03-05 22:13:47.000000000 +0000 @@ -49,7 +49,7 @@ return NV_ERR_INVALID_ARGUMENT; } - if (CliGetKernelChannelWithDevice(RES_GET_CLIENT_HANDLE(pSubdevice), + if (CliGetKernelChannelWithDevice(RES_GET_CLIENT(pSubdevice), RES_GET_PARENT_HANDLE(pSubdevice), pReadVirtMemParam->hChannel, &pKernelChannel) == NV_OK) diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/kernel/gpu/rc/kernel_rc_misc.c nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/kernel/gpu/rc/kernel_rc_misc.c --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/kernel/gpu/rc/kernel_rc_misc.c 2023-10-25 20:21:20.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/kernel/gpu/rc/kernel_rc_misc.c 2024-03-05 22:13:47.000000000 +0000 @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 2021-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2021-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -43,6 +43,7 @@ ) { VirtMemAllocator *pDma = GPU_GET_DMA(pGpu); + MemoryManager *pMemoryManager = GPU_GET_MEMORY_MANAGER(pGpu); MEMORY_DESCRIPTOR memDesc; NvU32 pageStartOffset; @@ -54,6 +55,7 @@ NvU32 cursize; NvU32 cur4kPage; NV_STATUS status = NV_OK; + TRANSFER_SURFACE surf = {0}; pageStartOffset = NvOffset_LO32(virtAddr) & RM_PAGE_MASK; start4kPage = (NvOffset_LO32(virtAddr) >> 12) & 0x1FFFF; @@ -78,6 +80,10 @@ pMem = (NvU8*) osMapKernelSpace(physaddr, RM_PAGE_SIZE, NV_MEMORY_UNCACHED, NV_PROTECT_READ_WRITE); + if (pMem == NULL) + { + return NV_ERR_INSUFFICIENT_RESOURCES; + } } else if (memtype == ADDR_FBMEM) { @@ -88,11 +94,20 @@ NV_MEMORY_UNCACHED, MEMDESC_FLAGS_NONE); memdescDescribe(&memDesc, ADDR_FBMEM, physaddr, RM_PAGE_SIZE); - pMem = kbusMapRmAperture_HAL(pGpu, &memDesc); - } - if (pMem == NULL) - { - return NV_ERR_INSUFFICIENT_RESOURCES; + + surf.pMemDesc = &memDesc; + surf.offset = 0; + + pMem = portMemAllocNonPaged(RM_PAGE_SIZE); + if (pMem == NULL) + { + return NV_ERR_INSUFFICIENT_RESOURCES; + } + + NV_ASSERT_OK_OR_ELSE(status, + memmgrMemRead(pMemoryManager, &surf, pMem, RM_PAGE_SIZE, + TRANSFER_FLAGS_NONE), + portMemFree(pMem); return status; ); } if (cursize > bufSize) { @@ -110,7 +125,7 @@ } else if (memtype == ADDR_FBMEM) { - kbusUnmapRmAperture_HAL(pGpu, &memDesc, &pMem, NV_TRUE); + portMemFree(pMem); memdescDestroy(&memDesc); } pMem = NULL; diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/kernel/gpu/rc/kernel_rc_notification.c nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/kernel/gpu/rc/kernel_rc_notification.c --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/kernel/gpu/rc/kernel_rc_notification.c 2023-10-25 20:21:20.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/kernel/gpu/rc/kernel_rc_notification.c 2024-03-05 22:13:47.000000000 +0000 @@ -44,7 +44,7 @@ ( OBJGPU *pGpu, Memory *pMemory, - NvHandle hClient, + RsClient *pClient, NvU32 exceptType, RM_ENGINE_TYPE localRmEngineType, NV_STATUS notifierStatus @@ -56,7 +56,7 @@ { case ADDR_VIRTUAL: notifyFillNotifierGPUVA(pGpu, - hClient, + pClient, RES_GET_HANDLE(pMemory), memdescGetPhysAddr(pMemory->pMemDesc, AT_GPU_VA, 0), exceptType, @@ -147,7 +147,7 @@ { status = _krcErrorWriteNotifierCpuMemHelper(pGpu, pMemory, - RES_GET_CLIENT_HANDLE(pKernelChannel), + RES_GET_CLIENT(pKernelChannel), exceptType, localRmEngineType, notifierStatus); @@ -199,7 +199,7 @@ { status = _krcErrorWriteNotifierCpuMemHelper(pGpu, pMemory, - RES_GET_CLIENT_HANDLE(pKernelChannel), + RES_GET_CLIENT(pKernelChannel), exceptType, localRmEngineType, notifierStatus); @@ -335,7 +335,7 @@ } if (flushFlags != 0) { - kbusFlush_HAL(pGpu, GPU_GET_KERNEL_BUS(pGpu), flushFlags); + kbusFlush_HAL(pGpu, GPU_GET_KERNEL_BUS(pGpu), flushFlags | BUS_FLUSH_USE_PCIE_READ); } Error: diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/kernel/gpu/rc/kernel_rc_watchdog.c nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/kernel/gpu/rc/kernel_rc_watchdog.c --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/kernel/gpu/rc/kernel_rc_watchdog.c 2023-10-25 20:21:20.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/kernel/gpu/rc/kernel_rc_watchdog.c 2024-03-05 22:13:48.000000000 +0000 @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 2021 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2021-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -52,7 +52,6 @@ #include "deprecated/rmapi_deprecated.h" #include "nvRmReg.h" - // // Watchdog object ids // @@ -107,7 +106,6 @@ #define SUBDEVICE_MASK_ALL DRF_MASK(NV906F_DMA_SET_SUBDEVICE_MASK_VALUE) - NV_STATUS krcWatchdogChangeState_IMPL ( @@ -402,7 +400,7 @@ // // Make sure to clear any old watchdog data this also clears - // WATCHDOG_FLAGS_INITIALIZED + // WATCHDOG_FLAGS_INITIALIZED, bHandleValid, and hClient // portMemSet(&pKernelRc->watchdog, 0, sizeof pKernelRc->watchdog); portMemSet(&pKernelRc->watchdogChannelInfo, 0, @@ -445,8 +443,8 @@ NvU32 pushBufBytes; NvU32 allocationSize; NvU32 ctrlSize; - NvU32 flags; NV_STATUS status; + RsClient *pClient; KernelChannel *pKernelChannel; NvBool bCacheSnoop; RM_API *pRmApi = rmGpuLockIsOwner() ? @@ -490,6 +488,14 @@ portMemSet(&pKernelRc->watchdogChannelInfo, 0, sizeof pKernelRc->watchdogChannelInfo); + // Bug 4088184 WAR: release GPU lock before allocating NV01_ROOT + if (rmGpuLockIsOwner()) + { + bAcquireLock = NV_TRUE; + rmGpuLocksRelease(GPUS_LOCK_FLAGS_NONE, NULL); + pRmApi = rmapiGetInterface(RMAPI_API_LOCK_INTERNAL); + } + // Allocate a root. { hClient = NV01_NULL_OBJECT; @@ -498,7 +504,8 @@ NV01_NULL_OBJECT /* hParent */, NV01_NULL_OBJECT /* hObject */, NV01_ROOT, - &hClient) != NV_OK) + &hClient, + sizeof(hClient)) != NV_OK) { NV_PRINTF(LEVEL_WARNING, "Unable to allocate a watchdog client\n"); return NV_ERR_GENERIC; @@ -510,6 +517,21 @@ status = NV_ERR_NO_MEMORY; goto error; } + pKernelRc->watchdog.hClient = hClient; + pKernelRc->watchdog.bHandleValid = NV_TRUE; + } + + if (bAcquireLock) + { + status = rmGpuLocksAcquire(GPUS_LOCK_FLAGS_NONE, RM_LOCK_MODULES_RC); + if (status != NV_OK) + { + NV_PRINTF(LEVEL_ERROR, "failed to grab RM-Lock\n"); + DBG_BREAKPOINT(); + goto error; + } + pRmApi = rmapiGetInterface(RMAPI_GPU_LOCK_INTERNAL); + bAcquireLock = NV_FALSE; } // Alloc device @@ -525,7 +547,8 @@ hClient /* hParent */, WATCHDOG_DEVICE_ID /* hObject */, NV01_DEVICE_0, - pNv0080); + pNv0080, + sizeof(*pNv0080)); if (status != NV_OK) { NV_PRINTF(LEVEL_WARNING, "Unable to allocate a watchdog device\n"); @@ -548,7 +571,8 @@ WATCHDOG_DEVICE_ID /* hParent */, (WATCHDOG_SUB_DEVICE_0_ID + subDeviceInstance) /* hObject */, NV20_SUBDEVICE_0, - pNv2080); + pNv2080, + sizeof(*pNv2080)); if (status != NV_OK) { NV_PRINTF(LEVEL_WARNING, @@ -627,7 +651,8 @@ WATCHDOG_DEVICE_ID /* hParent */, WATCHDOG_VIRTUAL_CTX_ID /* hObject */, NV01_MEMORY_VIRTUAL, - pVirtual); + pVirtual, + sizeof(*pVirtual)); if (status != NV_OK) { NV_PRINTF(LEVEL_WARNING, @@ -655,45 +680,108 @@ bCacheSnoop = FLD_TEST_REF(BIF_DMA_CAPS_SNOOP, _CTXDMA, kbifGetDmaCaps(pGpu, pKernelBif)); - // Allocate memory for the notifiers and pushbuffer. - flags = ((bCacheSnoop ? DRF_DEF(OS02, _FLAGS, _COHERENCY, _CACHED) : - DRF_DEF(OS02, _FLAGS, _COHERENCY, _UNCACHED)) | - DRF_DEF(OS02, _FLAGS, _LOCATION, _PCI) | - DRF_DEF(OS02, _FLAGS, _PHYSICALITY, _NONCONTIGUOUS)); - if ((pKernelRc->watchdog.flags & WATCHDOG_FLAGS_ALLOC_UNCACHED_PCI) != 0) - { - flags = FLD_SET_DRF(OS02, _FLAGS, _COHERENCY, _UNCACHED, flags); - } - { NV_MEMORY_ALLOCATION_PARAMS *pMem = &pParams->mem; + NvU32 hClass = NV01_MEMORY_SYSTEM; portMemSet(pMem, 0, sizeof *pMem); pMem->owner = HEAP_OWNER_RM_CLIENT_GENERIC; pMem->size = allocationSize; pMem->type = NVOS32_TYPE_IMAGE; - // TODO - migrate to use newer OS32 flags inline JIRA CORERM-4212 - status = RmDeprecatedConvertOs02ToOs32Flags(flags, - &pMem->attr, - &pMem->attr2, - &pMem->flags); - if (status != NV_OK) + pMem->attr2 = DRF_DEF(OS32, _ATTR2, _GPU_CACHEABLE, _NO); + + // Apply registry overrides to channel pushbuffer. + switch (DRF_VAL(_REG_STR_RM, _INST_LOC_4, _CHANNEL_PUSHBUFFER, pGpu->instLocOverrides4)) { - NV_PRINTF(LEVEL_ERROR, "Invalid flags\n"); - goto error; + case NV_REG_STR_RM_INST_LOC_4_CHANNEL_PUSHBUFFER_VID: + hClass = NV01_MEMORY_LOCAL_USER; + pMem->attr |= DRF_DEF(OS32, _ATTR, _LOCATION, _VIDMEM) | + DRF_DEF(OS32, _ATTR, _COHERENCY, _UNCACHED); + break; + + case NV_REG_STR_RM_INST_LOC_4_CHANNEL_PUSHBUFFER_COH: + hClass = NV01_MEMORY_SYSTEM; + pMem->attr |= DRF_DEF(OS32, _ATTR, _LOCATION, _PCI) | + DRF_DEF(OS32, _ATTR, _COHERENCY, _CACHED) | + DRF_DEF(OS32, _ATTR, _PHYSICALITY, _NONCONTIGUOUS); + break; + + case NV_REG_STR_RM_INST_LOC_4_CHANNEL_PUSHBUFFER_NCOH: + hClass = NV01_MEMORY_SYSTEM; + pMem->attr |= DRF_DEF(OS32, _ATTR, _LOCATION, _PCI) | + DRF_DEF(OS32, _ATTR, _COHERENCY, _UNCACHED) | + DRF_DEF(OS32, _ATTR, _PHYSICALITY, _NONCONTIGUOUS); + break; + + case NV_REG_STR_RM_INST_LOC_4_CHANNEL_PUSHBUFFER_DEFAULT: + default: + hClass = NV01_MEMORY_SYSTEM; + pMem->attr |= DRF_DEF(OS32, _ATTR, _LOCATION, _PCI) | + DRF_DEF(OS32, _ATTR, _COHERENCY, _UNCACHED) | + DRF_DEF(OS32, _ATTR, _PHYSICALITY, _NONCONTIGUOUS); + } + + if (bCacheSnoop && (hClass == NV01_MEMORY_SYSTEM)) + { + pMem->attr = FLD_SET_DRF(OS32, _ATTR, _COHERENCY, _CACHED, + pMem->attr); + } + + if (((pKernelRc->watchdog.flags & WATCHDOG_FLAGS_ALLOC_UNCACHED_PCI) != 0) && + (hClass == NV01_MEMORY_SYSTEM)) + { + pMem->attr = FLD_SET_DRF(OS32, _ATTR, _COHERENCY, _UNCACHED, + pMem->attr); + } + + // + // When Hopper CC is enabled all RM internal sysmem allocations that are + // required to be accessed from GPU should be in unprotected memory + // All video allocations must be in CPR + // + + // + // Allocate memory using vidHeapControl + // + // vidHeapControl calls should happen outside GPU locks. This is a PMA + // requirement as memory allocation calls may invoke eviction which UVM + // could get stuck behind GPU lock + // + if (hClass == NV01_MEMORY_LOCAL_USER && rmGpuLockIsOwner()) + { + bAcquireLock = NV_TRUE; + rmGpuLocksRelease(GPUS_LOCK_FLAGS_NONE, NULL); + pRmApi = rmapiGetInterface(RMAPI_API_LOCK_INTERNAL); } + // Allocate memory for the notifiers and pushbuffer status = pRmApi->AllocWithHandle(pRmApi, hClient /* hClient */, WATCHDOG_DEVICE_ID /* hParent */, WATCHDOG_MEM_ID /* hObject */, - NV01_MEMORY_SYSTEM, - pMem); + hClass, + pMem, + sizeof(*pMem)); + + if (bAcquireLock) + { + // Re-acquire the GPU locks + if (rmGpuLocksAcquire(GPUS_LOCK_FLAGS_NONE, RM_LOCK_MODULES_RC) != NV_OK) + { + NV_PRINTF(LEVEL_ERROR, "failed to grab RM-Lock\n"); + DBG_BREAKPOINT(); + goto error; + } + pRmApi = rmapiGetInterface(RMAPI_GPU_LOCK_INTERNAL); + bAcquireLock = NV_FALSE; + } + if (status != NV_OK) { NV_PRINTF(LEVEL_WARNING, - "Unable to allocate system memory for watchdog\n"); + "Unable to allocate %s memory for watchdog\n", + (hClass == NV01_MEMORY_LOCAL_USER) ? "video" : "system"); goto error; } @@ -708,7 +796,7 @@ if (status != NV_OK) { NV_PRINTF(LEVEL_WARNING, - "Unable to map system memory for watchdog\n"); + "Unable to map memory for watchdog\n"); goto error; } @@ -729,7 +817,7 @@ if (status != NV_OK) { NV_PRINTF(LEVEL_ERROR, - "Unable to map system memory into watchdog's heap\n"); + "Unable to map memory into watchdog's heap\n"); goto error; } } @@ -758,7 +846,8 @@ WATCHDOG_DEVICE_ID /* hParent */ , WATCHDOG_ERROR_DMA_ID /* hObject */, NV01_CONTEXT_DMA, - pCtxDma); + pCtxDma, + sizeof(*pCtxDma)); if (status != NV_OK) { NV_PRINTF(LEVEL_WARNING, @@ -792,7 +881,8 @@ WATCHDOG_DEVICE_ID /* hParent */, WATCHDOG_NOTIFIER_DMA_ID /* hObject */, NV01_CONTEXT_DMA, - pCtxDma); + pCtxDma, + sizeof(*pCtxDma)); if (status != NV_OK) { NV_PRINTF(LEVEL_WARNING, "Unable to set up watchdog's notifier\n"); @@ -826,6 +916,14 @@ } // + // When APM is enabled all RM internal allocations must to go to + // unprotected memory irrespective of vidmem or sysmem + // When Hopper CC is enabled all RM internal sysmem allocations that + // are required to be accessed from GPU should be in unprotected memory + // and all vidmem allocations must go to protected memory + // + + // // Allocate memory using vidHeapControl // // vidHeapControl calls should happen outside GPU locks. This is a PMA @@ -848,7 +946,8 @@ WATCHDOG_DEVICE_ID /* hParent */, WATCHDOG_USERD_PHYS_MEM_ID /* hObject */, userdMemClass, - pMem); + pMem, + sizeof(*pMem)); if (status != NV_OK) { @@ -894,7 +993,8 @@ WATCHDOG_DEVICE_ID /* hParent */, WATCHDOG_PUSHBUFFER_CHANNEL_ID /* hObject */, gpfifoObj, - pChannelGPFifo); + pChannelGPFifo, + sizeof(*pChannelGPFifo)); if (bAcquireLock) { @@ -970,18 +1070,27 @@ WATCHDOG_PUSHBUFFER_CHANNEL_ID /* hParent */, WATCHDOG_GROBJ_ID /* hObject */, grObj, - NULL); + NULL, + 0); if (status != NV_OK) { NV_PRINTF(LEVEL_WARNING, "Unable to allocate class %x\n", grObj); goto error; } + // Fetch the client object + status = serverGetClientUnderLock(&g_resServ, hClient, &pClient); + if (status != NV_OK) + { + NV_PRINTF(LEVEL_ERROR, "Unable to obtain client object\n"); + goto error; + } + // // Determine the (class + engine) handle the hardware will understand, if // necessary // - if (CliGetKernelChannelWithDevice(hClient, + if (CliGetKernelChannelWithDevice(pClient, WATCHDOG_DEVICE_ID, WATCHDOG_PUSHBUFFER_CHANNEL_ID, &pKernelChannel) != NV_OK) @@ -1065,9 +1174,11 @@ error: NV_ASSERT(status == NV_OK); + if (status != NV_OK) { pRmApi->Free(pRmApi, hClient, hClient); + pKernelRc->watchdog.bHandleValid = NV_FALSE; } portMemFree(pParams); @@ -1307,4 +1418,11 @@ SLI_LOOP_END; } +NV_STATUS krcWatchdogGetClientHandle(KernelRc *pKernelRc, NvHandle *phClient) +{ + if (!pKernelRc->watchdog.bHandleValid) + return NV_ERR_INVALID_STATE; + *phClient = pKernelRc->watchdog.hClient; + return NV_OK; +} diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/kernel/gpu/sec2/arch/hopper/kernel_sec2_gh100.c nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/kernel/gpu/sec2/arch/hopper/kernel_sec2_gh100.c --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/kernel/gpu/sec2/arch/hopper/kernel_sec2_gh100.c 1970-01-01 00:00:00.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/kernel/gpu/sec2/arch/hopper/kernel_sec2_gh100.c 2024-03-05 22:13:48.000000000 +0000 @@ -0,0 +1,46 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#include "gpu/sec2/kernel_sec2.h" +#include "gpu/conf_compute/conf_compute.h" +#include "conf_compute/cc_keystore.h" + +#include "core/core.h" + +NV_STATUS +ksec2StateLoad_GH100 +( + OBJGPU *pGpu, + KernelSec2 *pKernelSec2, + NvU32 unused +) +{ + ConfidentialCompute *pConfCompute = GPU_GET_CONF_COMPUTE(pGpu); + + if ((pConfCompute != NULL) && + (pConfCompute->getProperty(pCC, PDB_PROP_CONFCOMPUTE_CC_FEATURE_ENABLED))) + { + NV_ASSERT_OK_OR_RETURN(confComputeDeriveSecrets_HAL(pConfCompute, MC_ENGINE_IDX_SEC2)); + } + return NV_OK; +} diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/kernel/gpu/sec2/arch/turing/kernel_sec2_tu102.c nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/kernel/gpu/sec2/arch/turing/kernel_sec2_tu102.c --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/kernel/gpu/sec2/arch/turing/kernel_sec2_tu102.c 2023-10-25 20:21:21.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/kernel/gpu/sec2/arch/turing/kernel_sec2_tu102.c 2024-03-05 22:13:48.000000000 +0000 @@ -85,18 +85,6 @@ return NV_OK; } -NvBool -ksec2IsEngineInReset_TU102 -( - OBJGPU *pGpu, - KernelSec2 *pKernelSec2 -) -{ - NvU32 val = GPU_REG_RD32(pGpu, NV_PSEC_FALCON_ENGINE); - - return FLD_TEST_DRF(_PSEC_FALCON, _ENGINE, _RESET, _TRUE, val); -} - static NV_STATUS s_allocateGenericBlUcode ( @@ -155,7 +143,7 @@ goto out; } - NV_ASSERT_OK_OR_GOTO(status, + NV_ASSERT_OK_OR_GOTO(status, bindataWriteToBuffer(pBinImg, pGenericBlUcodeImg, imgSizeAligned), out); *ppDesc = pGenericBlUcodeDesc; diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/kernel/gpu/sec2/kernel_sec2.c nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/kernel/gpu/sec2/kernel_sec2.c --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/kernel/gpu/sec2/kernel_sec2.c 2023-10-25 20:21:21.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/kernel/gpu/sec2/kernel_sec2.c 2024-03-05 22:13:49.000000000 +0000 @@ -27,6 +27,8 @@ #include "gpu/eng_desc.h" #include "gpu/falcon/kernel_falcon.h" #include "gpu/gpu.h" +#include "gpu/fifo/kernel_fifo.h" +#include "rmapi/event.h" NV_STATUS ksec2ConstructEngine_IMPL @@ -52,3 +54,42 @@ portMemFree((void * /* const_cast */) pKernelSec2->pGenericBlUcodeImg); pKernelSec2->pGenericBlUcodeImg = NULL; } + +void +ksec2RegisterIntrService_IMPL +( + OBJGPU *pGpu, + KernelSec2 *pKernelSec2, + IntrServiceRecord pRecords[MC_ENGINE_IDX_MAX] +) +{ + KernelFalcon *pKernelFalcon = staticCast(pKernelSec2, KernelFalcon); + NV_ASSERT_OR_RETURN_VOID(pKernelFalcon); + + // Register to handle nonstalling interrupts + NV_ASSERT_OR_RETURN_VOID(pKernelFalcon->physEngDesc != ENG_INVALID); + + NvU32 mcIdx = MC_ENGINE_IDX_SEC2; + + NV_PRINTF(LEVEL_INFO, "Registering 0x%x/0x%x to handle SEC2 nonstall intr\n", pKernelFalcon->physEngDesc, mcIdx); + + NV_ASSERT(pRecords[mcIdx].pNotificationService == NULL); + pRecords[mcIdx].bFifoWaiveNotify = NV_FALSE; + pRecords[mcIdx].pNotificationService = staticCast(pKernelSec2, IntrService); + +} + +NV_STATUS +ksec2ServiceNotificationInterrupt_IMPL +( + OBJGPU *pGpu, + KernelSec2 *pKernelSec2, + IntrServiceServiceNotificationInterruptArguments *pParams +) +{ + NV_PRINTF(LEVEL_INFO, "servicing nonstall intr for SEC2 engine\n"); + + // Wake up channels waiting on this event + engineNonStallIntrNotify(pGpu, RM_ENGINE_TYPE_SEC2); + return NV_OK; +} \ No newline at end of file diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/kernel/gpu/sec2/sec2_context.c nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/kernel/gpu/sec2/sec2_context.c --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/kernel/gpu/sec2/sec2_context.c 1970-01-01 00:00:00.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/kernel/gpu/sec2/sec2_context.c 2024-03-05 22:13:49.000000000 +0000 @@ -0,0 +1,56 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2021-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#include "kernel/gpu/sec2/sec2_context.h" +#include "kernel/gpu/fifo/kernel_channel.h" +#include "gpu/falcon/kernel_falcon.h" + +NV_STATUS +sec2ctxConstructHal_KERNEL +( + Sec2Context *pSec2Context, + CALL_CONTEXT *pCallContext, + RS_RES_ALLOC_PARAMS_INTERNAL *pParams +) +{ + ChannelDescendant *pChannelDescendant = staticCast(pSec2Context, ChannelDescendant); + OBJGPU *pGpu = GPU_RES_GET_GPU(pChannelDescendant); + KernelFalcon *pKernelFalcon = kflcnGetKernelFalconForEngine(pGpu, ENG_SEC2); + KernelChannel *pKernelChannel = pChannelDescendant->pKernelChannel; + + return kflcnAllocContext(pGpu, pKernelFalcon, pKernelChannel, RES_GET_EXT_CLASS_ID(pChannelDescendant)); +} + +void +sec2ctxDestructHal_KERNEL +( + Sec2Context *pSec2Context +) +{ + ChannelDescendant *pChannelDescendant = staticCast(pSec2Context, ChannelDescendant); + OBJGPU *pGpu = GPU_RES_GET_GPU(pChannelDescendant); + KernelFalcon *pKernelFalcon = kflcnGetKernelFalconForEngine(pGpu, ENG_SEC2); + KernelChannel *pKernelChannel = pChannelDescendant->pKernelChannel; + + NV_ASSERT_OK(kflcnFreeContext(pGpu, pKernelFalcon, pKernelChannel, RES_GET_EXT_CLASS_ID(pChannelDescendant))); +} diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/kernel/gpu/spdm/arch/hopper/spdm_certs_gh100.c nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/kernel/gpu/spdm/arch/hopper/spdm_certs_gh100.c --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/kernel/gpu/spdm/arch/hopper/spdm_certs_gh100.c 1970-01-01 00:00:00.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/kernel/gpu/spdm/arch/hopper/spdm_certs_gh100.c 2024-03-05 22:13:49.000000000 +0000 @@ -0,0 +1,829 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +/*! + * Provides the implementation for all GH100 SPDM certificate HAL interfaces. + */ + +/* ------------------------ Includes --------------------------------------- */ +#include "nvRmReg.h" +#include "gpu/spdm/spdm.h" +#include "gpu/spdm/libspdm_includes.h" +#include "spdm/rmspdmvendordef.h" +#include "flcnretval.h" + +/* ------------------------ Macros ----------------------------------------- */ +#define DER_LONG_FORM_LENGTH_FIELD_BIT (0x80) +#define DER_CERT_SIZE_FIELD_LENGTH (0x4) + +#define SPDM_MAX_ENCODED_CERT_CHAIN_SIZE (0x1400) + +#define SPDM_PEM_BEGIN_CERTIFICATE "-----BEGIN CERTIFICATE-----\n" +#define SPDM_PEM_END_CERTIFICATE "-----END CERTIFICATE-----\n" + +#define SPDM_L1_CERTIFICATE_PEM "-----BEGIN CERTIFICATE-----\n"\ + "MIICCzCCAZCgAwIBAgIQLTZwscoQBBHB/sDoKgZbVDAKBggqhkjOPQQDAzA1MSIw\n"\ + "IAYDVQQDDBlOVklESUEgRGV2aWNlIElkZW50aXR5IENBMQ8wDQYDVQQKDAZOVklE\n"\ + "SUEwIBcNMjExMTA1MDAwMDAwWhgPOTk5OTEyMzEyMzU5NTlaMDUxIjAgBgNVBAMM\n"\ + "GU5WSURJQSBEZXZpY2UgSWRlbnRpdHkgQ0ExDzANBgNVBAoMBk5WSURJQTB2MBAG\n"\ + "ByqGSM49AgEGBSuBBAAiA2IABA5MFKM7+KViZljbQSlgfky/RRnEQScW9NDZF8SX\n"\ + "gAW96r6u/Ve8ZggtcYpPi2BS4VFu6KfEIrhN6FcHG7WP05W+oM+hxj7nyA1r1jkB\n"\ + "2Ry70YfThX3Ba1zOryOP+MJ9vaNjMGEwDwYDVR0TAQH/BAUwAwEB/zAOBgNVHQ8B\n"\ + "Af8EBAMCAQYwHQYDVR0OBBYEFFeF/4PyY8xlfWi3Olv0jUrL+0lfMB8GA1UdIwQY\n"\ + "MBaAFFeF/4PyY8xlfWi3Olv0jUrL+0lfMAoGCCqGSM49BAMDA2kAMGYCMQCPeFM3\n"\ + "TASsKQVaT+8S0sO9u97PVGCpE9d/I42IT7k3UUOLSR/qvJynVOD1vQKVXf0CMQC+\n"\ + "EY55WYoDBvs2wPAH1Gw4LbcwUN8QCff8bFmV4ZxjCRr4WXTLFHBKjbfneGSBWwA=\n"\ + "-----END CERTIFICATE-----\n" + +#define SPDM_L2_CERTIFICATE_PEM "-----BEGIN CERTIFICATE-----\n"\ + "MIICijCCAhCgAwIBAgIQTCVe3jvQAb8/SjtgX8qJijAKBggqhkjOPQQDAzA1MSIw\n"\ + "IAYDVQQDDBlOVklESUEgRGV2aWNlIElkZW50aXR5IENBMQ8wDQYDVQQKDAZOVklE\n"\ + "SUEwIBcNMjIwMTEyMDAwMDAwWhgPOTk5OTEyMzEyMzU5NTlaMD0xHjAcBgNVBAMM\n"\ + "FU5WSURJQSBHSDEwMCBJZGVudGl0eTEbMBkGA1UECgwSTlZJRElBIENvcnBvcmF0\n"\ + "aW9uMHYwEAYHKoZIzj0CAQYFK4EEACIDYgAE+pg+tDUuILlZILk5wg22YEJ9Oh6c\n"\ + "yPcsv3IvgRWcV4LeZK1pTCoQDIplZ0E4qsLG3G04pxsbMhxbqkiz9pqlTV2rtuVg\n"\ + "SmIqnSYkU1jWXsPS9oVLCGE8VRLl1JvqyOxUo4HaMIHXMA8GA1UdEwEB/wQFMAMB\n"\ + "Af8wDgYDVR0PAQH/BAQDAgEGMDsGA1UdHwQ0MDIwMKAuoCyGKmh0dHA6Ly9jcmwu\n"\ + "bmRpcy5udmlkaWEuY29tL2NybC9sMS1yb290LmNybDA3BggrBgEFBQcBAQQrMCkw\n"\ + "JwYIKwYBBQUHMAGGG2h0dHA6Ly9vY3NwLm5kaXMubnZpZGlhLmNvbTAdBgNVHQ4E\n"\ + "FgQUB0Kg6wOcgGB7oUFhmU2uJffCmx4wHwYDVR0jBBgwFoAUV4X/g/JjzGV9aLc6\n"\ + "W/SNSsv7SV8wCgYIKoZIzj0EAwMDaAAwZQIxAPIQhnveFxYIrPzBqViT2I34SfS4\n"\ + "JGWFnk/1UcdmgJmp+7l6rH/C4qxwntYSgeYrlQIwdjQuofHnhd1RL09OBO34566J\n"\ + "C9bYAosT/86cCojiGjhLnal9hJOH0nS/lrbaoc5a\n"\ + "-----END CERTIFICATE-----\n" + +#define SPDM_L3_CERTIFICATE_PEM "-----BEGIN CERTIFICATE-----\n"\ + "MIICqjCCAi+gAwIBAgIQav5xhPkiMsjfeyQiYXduVjAKBggqhkjOPQQDAzA9MR4w\n"\ + "HAYDVQQDDBVOVklESUEgR0gxMDAgSWRlbnRpdHkxGzAZBgNVBAoMEk5WSURJQSBD\n"\ + "b3Jwb3JhdGlvbjAgFw0yMjAzMDEwMDAwMDBaGA85OTk5MTIzMTIzNTk1OVowUzEn\n"\ + "MCUGA1UEAwweTlZJRElBIEdIMTAwIFByb3Zpc2lvbmVyIElDQSAxMRswGQYDVQQK\n"\ + "DBJOVklESUEgQ29ycG9yYXRpb24xCzAJBgNVBAYTAlVTMHYwEAYHKoZIzj0CAQYF\n"\ + "K4EEACIDYgAEzUdWqjn1OlXhLfFOKAFTghqG+Q3zF4xgSBbZsUEyWYCC3rKjE9Nn\n"\ + "o88ZpBQx85Oo0PkqP2dwoMVNTQMv5cvy9jLaTvSTXZwN2HQHE9u7x7BIYrWi0sG3\n"\ + "5q1IJNSOGO5Lo4HbMIHYMA8GA1UdEwEB/wQFMAMBAf8wDgYDVR0PAQH/BAQDAgEG\n"\ + "MDwGA1UdHwQ1MDMwMaAvoC2GK2h0dHA6Ly9jcmwubmRpcy5udmlkaWEuY29tL2Ny\n"\ + "bC9sMi1naDEwMC5jcmwwNwYIKwYBBQUHAQEEKzApMCcGCCsGAQUFBzABhhtodHRw\n"\ + "Oi8vb2NzcC5uZGlzLm52aWRpYS5jb20wHQYDVR0OBBYEFCloyxYs0HeVcqJ5EAPm\n"\ + "nroMzAqUMB8GA1UdIwQYMBaAFAdCoOsDnIBge6FBYZlNriX3wpseMAoGCCqGSM49\n"\ + "BAMDA2kAMGYCMQDK0BCr49DNJ48Yh5wu388bZifDFxAsiUS4U1fGmpJZFhCbODH6\n"\ + "mRwcMxp6EOayZuYCMQDYKTyNc2FxWFuhHtdCE3ls4S7SInehdErTZNuhFymc4YOM\n"\ + "6VlLWTY/CM+resjjqxQ=\n"\ + "-----END CERTIFICATE-----\n" + +const static NvU8 SPDM_L1_CERTIFICATE_DER[527] = +{ + 0x30, 0x82, 0x02, 0x0b, 0x30, 0x82, 0x01, 0x90, 0xa0, 0x03, 0x02, 0x01, 0x02, 0x02, 0x10, 0x2d, + 0x36, 0x70, 0xb1, 0xca, 0x10, 0x04, 0x11, 0xc1, 0xfe, 0xc0, 0xe8, 0x2a, 0x06, 0x5b, 0x54, 0x30, + 0x0a, 0x06, 0x08, 0x2a, 0x86, 0x48, 0xce, 0x3d, 0x04, 0x03, 0x03, 0x30, 0x35, 0x31, 0x22, 0x30, + 0x20, 0x06, 0x03, 0x55, 0x04, 0x03, 0x0c, 0x19, 0x4e, 0x56, 0x49, 0x44, 0x49, 0x41, 0x20, 0x44, + 0x65, 0x76, 0x69, 0x63, 0x65, 0x20, 0x49, 0x64, 0x65, 0x6e, 0x74, 0x69, 0x74, 0x79, 0x20, 0x43, + 0x41, 0x31, 0x0f, 0x30, 0x0d, 0x06, 0x03, 0x55, 0x04, 0x0a, 0x0c, 0x06, 0x4e, 0x56, 0x49, 0x44, + 0x49, 0x41, 0x30, 0x20, 0x17, 0x0d, 0x32, 0x31, 0x31, 0x31, 0x30, 0x35, 0x30, 0x30, 0x30, 0x30, + 0x30, 0x30, 0x5a, 0x18, 0x0f, 0x39, 0x39, 0x39, 0x39, 0x31, 0x32, 0x33, 0x31, 0x32, 0x33, 0x35, + 0x39, 0x35, 0x39, 0x5a, 0x30, 0x35, 0x31, 0x22, 0x30, 0x20, 0x06, 0x03, 0x55, 0x04, 0x03, 0x0c, + 0x19, 0x4e, 0x56, 0x49, 0x44, 0x49, 0x41, 0x20, 0x44, 0x65, 0x76, 0x69, 0x63, 0x65, 0x20, 0x49, + 0x64, 0x65, 0x6e, 0x74, 0x69, 0x74, 0x79, 0x20, 0x43, 0x41, 0x31, 0x0f, 0x30, 0x0d, 0x06, 0x03, + 0x55, 0x04, 0x0a, 0x0c, 0x06, 0x4e, 0x56, 0x49, 0x44, 0x49, 0x41, 0x30, 0x76, 0x30, 0x10, 0x06, + 0x07, 0x2a, 0x86, 0x48, 0xce, 0x3d, 0x02, 0x01, 0x06, 0x05, 0x2b, 0x81, 0x04, 0x00, 0x22, 0x03, + 0x62, 0x00, 0x04, 0x0e, 0x4c, 0x14, 0xa3, 0x3b, 0xf8, 0xa5, 0x62, 0x66, 0x58, 0xdb, 0x41, 0x29, + 0x60, 0x7e, 0x4c, 0xbf, 0x45, 0x19, 0xc4, 0x41, 0x27, 0x16, 0xf4, 0xd0, 0xd9, 0x17, 0xc4, 0x97, + 0x80, 0x05, 0xbd, 0xea, 0xbe, 0xae, 0xfd, 0x57, 0xbc, 0x66, 0x08, 0x2d, 0x71, 0x8a, 0x4f, 0x8b, + 0x60, 0x52, 0xe1, 0x51, 0x6e, 0xe8, 0xa7, 0xc4, 0x22, 0xb8, 0x4d, 0xe8, 0x57, 0x07, 0x1b, 0xb5, + 0x8f, 0xd3, 0x95, 0xbe, 0xa0, 0xcf, 0xa1, 0xc6, 0x3e, 0xe7, 0xc8, 0x0d, 0x6b, 0xd6, 0x39, 0x01, + 0xd9, 0x1c, 0xbb, 0xd1, 0x87, 0xd3, 0x85, 0x7d, 0xc1, 0x6b, 0x5c, 0xce, 0xaf, 0x23, 0x8f, 0xf8, + 0xc2, 0x7d, 0xbd, 0xa3, 0x63, 0x30, 0x61, 0x30, 0x0f, 0x06, 0x03, 0x55, 0x1d, 0x13, 0x01, 0x01, + 0xff, 0x04, 0x05, 0x30, 0x03, 0x01, 0x01, 0xff, 0x30, 0x0e, 0x06, 0x03, 0x55, 0x1d, 0x0f, 0x01, + 0x01, 0xff, 0x04, 0x04, 0x03, 0x02, 0x01, 0x06, 0x30, 0x1d, 0x06, 0x03, 0x55, 0x1d, 0x0e, 0x04, + 0x16, 0x04, 0x14, 0x57, 0x85, 0xff, 0x83, 0xf2, 0x63, 0xcc, 0x65, 0x7d, 0x68, 0xb7, 0x3a, 0x5b, + 0xf4, 0x8d, 0x4a, 0xcb, 0xfb, 0x49, 0x5f, 0x30, 0x1f, 0x06, 0x03, 0x55, 0x1d, 0x23, 0x04, 0x18, + 0x30, 0x16, 0x80, 0x14, 0x57, 0x85, 0xff, 0x83, 0xf2, 0x63, 0xcc, 0x65, 0x7d, 0x68, 0xb7, 0x3a, + 0x5b, 0xf4, 0x8d, 0x4a, 0xcb, 0xfb, 0x49, 0x5f, 0x30, 0x0a, 0x06, 0x08, 0x2a, 0x86, 0x48, 0xce, + 0x3d, 0x04, 0x03, 0x03, 0x03, 0x69, 0x00, 0x30, 0x66, 0x02, 0x31, 0x00, 0x8f, 0x78, 0x53, 0x37, + 0x4c, 0x04, 0xac, 0x29, 0x05, 0x5a, 0x4f, 0xef, 0x12, 0xd2, 0xc3, 0xbd, 0xbb, 0xde, 0xcf, 0x54, + 0x60, 0xa9, 0x13, 0xd7, 0x7f, 0x23, 0x8d, 0x88, 0x4f, 0xb9, 0x37, 0x51, 0x43, 0x8b, 0x49, 0x1f, + 0xea, 0xbc, 0x9c, 0xa7, 0x54, 0xe0, 0xf5, 0xbd, 0x02, 0x95, 0x5d, 0xfd, 0x02, 0x31, 0x00, 0xbe, + 0x11, 0x8e, 0x79, 0x59, 0x8a, 0x03, 0x06, 0xfb, 0x36, 0xc0, 0xf0, 0x07, 0xd4, 0x6c, 0x38, 0x2d, + 0xb7, 0x30, 0x50, 0xdf, 0x10, 0x09, 0xf7, 0xfc, 0x6c, 0x59, 0x95, 0xe1, 0x9c, 0x63, 0x09, 0x1a, + 0xf8, 0x59, 0x74, 0xcb, 0x14, 0x70, 0x4a, 0x8d, 0xb7, 0xe7, 0x78, 0x64, 0x81, 0x5b, 0x00 +}; + +const static NvU8 SPDM_L2_CERTIFICATE_DER[654] = +{ + 0x30, 0x82, 0x02, 0x8a, 0x30, 0x82, 0x02, 0x10, 0xa0, 0x03, 0x02, 0x01, 0x02, 0x02, 0x10, 0x4c, + 0x25, 0x5e, 0xde, 0x3b, 0xd0, 0x01, 0xbf, 0x3f, 0x4a, 0x3b, 0x60, 0x5f, 0xca, 0x89, 0x8a, 0x30, + 0x0a, 0x06, 0x08, 0x2a, 0x86, 0x48, 0xce, 0x3d, 0x04, 0x03, 0x03, 0x30, 0x35, 0x31, 0x22, 0x30, + 0x20, 0x06, 0x03, 0x55, 0x04, 0x03, 0x0c, 0x19, 0x4e, 0x56, 0x49, 0x44, 0x49, 0x41, 0x20, 0x44, + 0x65, 0x76, 0x69, 0x63, 0x65, 0x20, 0x49, 0x64, 0x65, 0x6e, 0x74, 0x69, 0x74, 0x79, 0x20, 0x43, + 0x41, 0x31, 0x0f, 0x30, 0x0d, 0x06, 0x03, 0x55, 0x04, 0x0a, 0x0c, 0x06, 0x4e, 0x56, 0x49, 0x44, + 0x49, 0x41, 0x30, 0x20, 0x17, 0x0d, 0x32, 0x32, 0x30, 0x31, 0x31, 0x32, 0x30, 0x30, 0x30, 0x30, + 0x30, 0x30, 0x5a, 0x18, 0x0f, 0x39, 0x39, 0x39, 0x39, 0x31, 0x32, 0x33, 0x31, 0x32, 0x33, 0x35, + 0x39, 0x35, 0x39, 0x5a, 0x30, 0x3d, 0x31, 0x1e, 0x30, 0x1c, 0x06, 0x03, 0x55, 0x04, 0x03, 0x0c, + 0x15, 0x4e, 0x56, 0x49, 0x44, 0x49, 0x41, 0x20, 0x47, 0x48, 0x31, 0x30, 0x30, 0x20, 0x49, 0x64, + 0x65, 0x6e, 0x74, 0x69, 0x74, 0x79, 0x31, 0x1b, 0x30, 0x19, 0x06, 0x03, 0x55, 0x04, 0x0a, 0x0c, + 0x12, 0x4e, 0x56, 0x49, 0x44, 0x49, 0x41, 0x20, 0x43, 0x6f, 0x72, 0x70, 0x6f, 0x72, 0x61, 0x74, + 0x69, 0x6f, 0x6e, 0x30, 0x76, 0x30, 0x10, 0x06, 0x07, 0x2a, 0x86, 0x48, 0xce, 0x3d, 0x02, 0x01, + 0x06, 0x05, 0x2b, 0x81, 0x04, 0x00, 0x22, 0x03, 0x62, 0x00, 0x04, 0xfa, 0x98, 0x3e, 0xb4, 0x35, + 0x2e, 0x20, 0xb9, 0x59, 0x20, 0xb9, 0x39, 0xc2, 0x0d, 0xb6, 0x60, 0x42, 0x7d, 0x3a, 0x1e, 0x9c, + 0xc8, 0xf7, 0x2c, 0xbf, 0x72, 0x2f, 0x81, 0x15, 0x9c, 0x57, 0x82, 0xde, 0x64, 0xad, 0x69, 0x4c, + 0x2a, 0x10, 0x0c, 0x8a, 0x65, 0x67, 0x41, 0x38, 0xaa, 0xc2, 0xc6, 0xdc, 0x6d, 0x38, 0xa7, 0x1b, + 0x1b, 0x32, 0x1c, 0x5b, 0xaa, 0x48, 0xb3, 0xf6, 0x9a, 0xa5, 0x4d, 0x5d, 0xab, 0xb6, 0xe5, 0x60, + 0x4a, 0x62, 0x2a, 0x9d, 0x26, 0x24, 0x53, 0x58, 0xd6, 0x5e, 0xc3, 0xd2, 0xf6, 0x85, 0x4b, 0x08, + 0x61, 0x3c, 0x55, 0x12, 0xe5, 0xd4, 0x9b, 0xea, 0xc8, 0xec, 0x54, 0xa3, 0x81, 0xda, 0x30, 0x81, + 0xd7, 0x30, 0x0f, 0x06, 0x03, 0x55, 0x1d, 0x13, 0x01, 0x01, 0xff, 0x04, 0x05, 0x30, 0x03, 0x01, + 0x01, 0xff, 0x30, 0x0e, 0x06, 0x03, 0x55, 0x1d, 0x0f, 0x01, 0x01, 0xff, 0x04, 0x04, 0x03, 0x02, + 0x01, 0x06, 0x30, 0x3b, 0x06, 0x03, 0x55, 0x1d, 0x1f, 0x04, 0x34, 0x30, 0x32, 0x30, 0x30, 0xa0, + 0x2e, 0xa0, 0x2c, 0x86, 0x2a, 0x68, 0x74, 0x74, 0x70, 0x3a, 0x2f, 0x2f, 0x63, 0x72, 0x6c, 0x2e, + 0x6e, 0x64, 0x69, 0x73, 0x2e, 0x6e, 0x76, 0x69, 0x64, 0x69, 0x61, 0x2e, 0x63, 0x6f, 0x6d, 0x2f, + 0x63, 0x72, 0x6c, 0x2f, 0x6c, 0x31, 0x2d, 0x72, 0x6f, 0x6f, 0x74, 0x2e, 0x63, 0x72, 0x6c, 0x30, + 0x37, 0x06, 0x08, 0x2b, 0x06, 0x01, 0x05, 0x05, 0x07, 0x01, 0x01, 0x04, 0x2b, 0x30, 0x29, 0x30, + 0x27, 0x06, 0x08, 0x2b, 0x06, 0x01, 0x05, 0x05, 0x07, 0x30, 0x01, 0x86, 0x1b, 0x68, 0x74, 0x74, + 0x70, 0x3a, 0x2f, 0x2f, 0x6f, 0x63, 0x73, 0x70, 0x2e, 0x6e, 0x64, 0x69, 0x73, 0x2e, 0x6e, 0x76, + 0x69, 0x64, 0x69, 0x61, 0x2e, 0x63, 0x6f, 0x6d, 0x30, 0x1d, 0x06, 0x03, 0x55, 0x1d, 0x0e, 0x04, + 0x16, 0x04, 0x14, 0x07, 0x42, 0xa0, 0xeb, 0x03, 0x9c, 0x80, 0x60, 0x7b, 0xa1, 0x41, 0x61, 0x99, + 0x4d, 0xae, 0x25, 0xf7, 0xc2, 0x9b, 0x1e, 0x30, 0x1f, 0x06, 0x03, 0x55, 0x1d, 0x23, 0x04, 0x18, + 0x30, 0x16, 0x80, 0x14, 0x57, 0x85, 0xff, 0x83, 0xf2, 0x63, 0xcc, 0x65, 0x7d, 0x68, 0xb7, 0x3a, + 0x5b, 0xf4, 0x8d, 0x4a, 0xcb, 0xfb, 0x49, 0x5f, 0x30, 0x0a, 0x06, 0x08, 0x2a, 0x86, 0x48, 0xce, + 0x3d, 0x04, 0x03, 0x03, 0x03, 0x68, 0x00, 0x30, 0x65, 0x02, 0x31, 0x00, 0xf2, 0x10, 0x86, 0x7b, + 0xde, 0x17, 0x16, 0x08, 0xac, 0xfc, 0xc1, 0xa9, 0x58, 0x93, 0xd8, 0x8d, 0xf8, 0x49, 0xf4, 0xb8, + 0x24, 0x65, 0x85, 0x9e, 0x4f, 0xf5, 0x51, 0xc7, 0x66, 0x80, 0x99, 0xa9, 0xfb, 0xb9, 0x7a, 0xac, + 0x7f, 0xc2, 0xe2, 0xac, 0x70, 0x9e, 0xd6, 0x12, 0x81, 0xe6, 0x2b, 0x95, 0x02, 0x30, 0x76, 0x34, + 0x2e, 0xa1, 0xf1, 0xe7, 0x85, 0xdd, 0x51, 0x2f, 0x4f, 0x4e, 0x04, 0xed, 0xf8, 0xe7, 0xae, 0x89, + 0x0b, 0xd6, 0xd8, 0x02, 0x8b, 0x13, 0xff, 0xce, 0x9c, 0x0a, 0x88, 0xe2, 0x1a, 0x38, 0x4b, 0x9d, + 0xa9, 0x7d, 0x84, 0x93, 0x87, 0xd2, 0x74, 0xbf, 0x96, 0xb6, 0xda, 0xa1, 0xce, 0x5a, +}; + +const static NvU8 SPDM_L3_CERTIFICATE_DER[686] = +{ + 0x30, 0x82, 0x02, 0xaa, 0x30, 0x82, 0x02, 0x2f, 0xa0, 0x03, 0x02, 0x01, 0x02, 0x02, 0x10, 0x6a, + 0xfe, 0x71, 0x84, 0xf9, 0x22, 0x32, 0xc8, 0xdf, 0x7b, 0x24, 0x22, 0x61, 0x77, 0x6e, 0x56, 0x30, + 0x0a, 0x06, 0x08, 0x2a, 0x86, 0x48, 0xce, 0x3d, 0x04, 0x03, 0x03, 0x30, 0x3d, 0x31, 0x1e, 0x30, + 0x1c, 0x06, 0x03, 0x55, 0x04, 0x03, 0x0c, 0x15, 0x4e, 0x56, 0x49, 0x44, 0x49, 0x41, 0x20, 0x47, + 0x48, 0x31, 0x30, 0x30, 0x20, 0x49, 0x64, 0x65, 0x6e, 0x74, 0x69, 0x74, 0x79, 0x31, 0x1b, 0x30, + 0x19, 0x06, 0x03, 0x55, 0x04, 0x0a, 0x0c, 0x12, 0x4e, 0x56, 0x49, 0x44, 0x49, 0x41, 0x20, 0x43, + 0x6f, 0x72, 0x70, 0x6f, 0x72, 0x61, 0x74, 0x69, 0x6f, 0x6e, 0x30, 0x20, 0x17, 0x0d, 0x32, 0x32, + 0x30, 0x33, 0x30, 0x31, 0x30, 0x30, 0x30, 0x30, 0x30, 0x30, 0x5a, 0x18, 0x0f, 0x39, 0x39, 0x39, + 0x39, 0x31, 0x32, 0x33, 0x31, 0x32, 0x33, 0x35, 0x39, 0x35, 0x39, 0x5a, 0x30, 0x53, 0x31, 0x27, + 0x30, 0x25, 0x06, 0x03, 0x55, 0x04, 0x03, 0x0c, 0x1e, 0x4e, 0x56, 0x49, 0x44, 0x49, 0x41, 0x20, + 0x47, 0x48, 0x31, 0x30, 0x30, 0x20, 0x50, 0x72, 0x6f, 0x76, 0x69, 0x73, 0x69, 0x6f, 0x6e, 0x65, + 0x72, 0x20, 0x49, 0x43, 0x41, 0x20, 0x31, 0x31, 0x1b, 0x30, 0x19, 0x06, 0x03, 0x55, 0x04, 0x0a, + 0x0c, 0x12, 0x4e, 0x56, 0x49, 0x44, 0x49, 0x41, 0x20, 0x43, 0x6f, 0x72, 0x70, 0x6f, 0x72, 0x61, + 0x74, 0x69, 0x6f, 0x6e, 0x31, 0x0b, 0x30, 0x09, 0x06, 0x03, 0x55, 0x04, 0x06, 0x13, 0x02, 0x55, + 0x53, 0x30, 0x76, 0x30, 0x10, 0x06, 0x07, 0x2a, 0x86, 0x48, 0xce, 0x3d, 0x02, 0x01, 0x06, 0x05, + 0x2b, 0x81, 0x04, 0x00, 0x22, 0x03, 0x62, 0x00, 0x04, 0xcd, 0x47, 0x56, 0xaa, 0x39, 0xf5, 0x3a, + 0x55, 0xe1, 0x2d, 0xf1, 0x4e, 0x28, 0x01, 0x53, 0x82, 0x1a, 0x86, 0xf9, 0x0d, 0xf3, 0x17, 0x8c, + 0x60, 0x48, 0x16, 0xd9, 0xb1, 0x41, 0x32, 0x59, 0x80, 0x82, 0xde, 0xb2, 0xa3, 0x13, 0xd3, 0x67, + 0xa3, 0xcf, 0x19, 0xa4, 0x14, 0x31, 0xf3, 0x93, 0xa8, 0xd0, 0xf9, 0x2a, 0x3f, 0x67, 0x70, 0xa0, + 0xc5, 0x4d, 0x4d, 0x03, 0x2f, 0xe5, 0xcb, 0xf2, 0xf6, 0x32, 0xda, 0x4e, 0xf4, 0x93, 0x5d, 0x9c, + 0x0d, 0xd8, 0x74, 0x07, 0x13, 0xdb, 0xbb, 0xc7, 0xb0, 0x48, 0x62, 0xb5, 0xa2, 0xd2, 0xc1, 0xb7, + 0xe6, 0xad, 0x48, 0x24, 0xd4, 0x8e, 0x18, 0xee, 0x4b, 0xa3, 0x81, 0xdb, 0x30, 0x81, 0xd8, 0x30, + 0x0f, 0x06, 0x03, 0x55, 0x1d, 0x13, 0x01, 0x01, 0xff, 0x04, 0x05, 0x30, 0x03, 0x01, 0x01, 0xff, + 0x30, 0x0e, 0x06, 0x03, 0x55, 0x1d, 0x0f, 0x01, 0x01, 0xff, 0x04, 0x04, 0x03, 0x02, 0x01, 0x06, + 0x30, 0x3c, 0x06, 0x03, 0x55, 0x1d, 0x1f, 0x04, 0x35, 0x30, 0x33, 0x30, 0x31, 0xa0, 0x2f, 0xa0, + 0x2d, 0x86, 0x2b, 0x68, 0x74, 0x74, 0x70, 0x3a, 0x2f, 0x2f, 0x63, 0x72, 0x6c, 0x2e, 0x6e, 0x64, + 0x69, 0x73, 0x2e, 0x6e, 0x76, 0x69, 0x64, 0x69, 0x61, 0x2e, 0x63, 0x6f, 0x6d, 0x2f, 0x63, 0x72, + 0x6c, 0x2f, 0x6c, 0x32, 0x2d, 0x67, 0x68, 0x31, 0x30, 0x30, 0x2e, 0x63, 0x72, 0x6c, 0x30, 0x37, + 0x06, 0x08, 0x2b, 0x06, 0x01, 0x05, 0x05, 0x07, 0x01, 0x01, 0x04, 0x2b, 0x30, 0x29, 0x30, 0x27, + 0x06, 0x08, 0x2b, 0x06, 0x01, 0x05, 0x05, 0x07, 0x30, 0x01, 0x86, 0x1b, 0x68, 0x74, 0x74, 0x70, + 0x3a, 0x2f, 0x2f, 0x6f, 0x63, 0x73, 0x70, 0x2e, 0x6e, 0x64, 0x69, 0x73, 0x2e, 0x6e, 0x76, 0x69, + 0x64, 0x69, 0x61, 0x2e, 0x63, 0x6f, 0x6d, 0x30, 0x1d, 0x06, 0x03, 0x55, 0x1d, 0x0e, 0x04, 0x16, + 0x04, 0x14, 0x29, 0x68, 0xcb, 0x16, 0x2c, 0xd0, 0x77, 0x95, 0x72, 0xa2, 0x79, 0x10, 0x03, 0xe6, + 0x9e, 0xba, 0x0c, 0xcc, 0x0a, 0x94, 0x30, 0x1f, 0x06, 0x03, 0x55, 0x1d, 0x23, 0x04, 0x18, 0x30, + 0x16, 0x80, 0x14, 0x07, 0x42, 0xa0, 0xeb, 0x03, 0x9c, 0x80, 0x60, 0x7b, 0xa1, 0x41, 0x61, 0x99, + 0x4d, 0xae, 0x25, 0xf7, 0xc2, 0x9b, 0x1e, 0x30, 0x0a, 0x06, 0x08, 0x2a, 0x86, 0x48, 0xce, 0x3d, + 0x04, 0x03, 0x03, 0x03, 0x69, 0x00, 0x30, 0x66, 0x02, 0x31, 0x00, 0xca, 0xd0, 0x10, 0xab, 0xe3, + 0xd0, 0xcd, 0x27, 0x8f, 0x18, 0x87, 0x9c, 0x2e, 0xdf, 0xcf, 0x1b, 0x66, 0x27, 0xc3, 0x17, 0x10, + 0x2c, 0x89, 0x44, 0xb8, 0x53, 0x57, 0xc6, 0x9a, 0x92, 0x59, 0x16, 0x10, 0x9b, 0x38, 0x31, 0xfa, + 0x99, 0x1c, 0x1c, 0x33, 0x1a, 0x7a, 0x10, 0xe6, 0xb2, 0x66, 0xe6, 0x02, 0x31, 0x00, 0xd8, 0x29, + 0x3c, 0x8d, 0x73, 0x61, 0x71, 0x58, 0x5b, 0xa1, 0x1e, 0xd7, 0x42, 0x13, 0x79, 0x6c, 0xe1, 0x2e, + 0xd2, 0x22, 0x77, 0xa1, 0x74, 0x4a, 0xd3, 0x64, 0xdb, 0xa1, 0x17, 0x29, 0x9c, 0xe1, 0x83, 0x8c, + 0xe9, 0x59, 0x4b, 0x59, 0x36, 0x3f, 0x08, 0xcf, 0xab, 0x7a, 0xc8, 0xe3, 0xab, 0x14, +}; + +/* ------------------------ Static Functions ------------------------------- */ +/*! + @param pCert : The pointer to certification chain start + @param bufferEnd : The pointer to certification chain end + @parsm pCertLength : The pointer to store return certification size + + @return Return NV-OK if no error. + +* Static function that calculates the length of the X509 certificate in DER/TLV +* format. It assumes that the certificate is valid. +*/ +static NV_STATUS +_calcX509CertSize +( + NvU8 *pCert, + NvU8 *bufferEnd, + NvU32 *pCertLength +) +{ + // The cert is in TLV format. + NvU32 certSize = pCert[1]; + + // Check to make sure that some data exists after SPDM header, and it is enough to check cert size. + if (pCert + DER_CERT_SIZE_FIELD_LENGTH >= bufferEnd || + pCert + DER_CERT_SIZE_FIELD_LENGTH <= pCert) + { + NV_PRINTF(LEVEL_ERROR, " %s: pCert + DER_CERT_SIZE_FIELD_LENGTH(0x%x) is not valid value !! \n", + __FUNCTION__, DER_CERT_SIZE_FIELD_LENGTH); + + return NV_ERR_BUFFER_TOO_SMALL; + } + + // Check if the length is in DER longform. + // MSB in the length field is set for long form notation. + // fields. + if (certSize & DER_LONG_FORM_LENGTH_FIELD_BIT) + { + // + // The remaining bits in the length field indicate the + // number of following bytes used to represent the length. + // in base 256, most significant digit first. + // + NvU32 numLenBytes = certSize & 0x3f; + NvU8 *pStart = &pCert[2]; + NvU8 *pEnd = pStart + numLenBytes; // NOTE: Don't need to subtract numLenBytes 1 here. + + // Checking for buffer overflow. + if (pEnd > bufferEnd) + { + return NV_ERR_BUFFER_TOO_SMALL; + } + + certSize = *pStart; + while (++pStart < pEnd) + { + certSize = (certSize << 8) + *pStart ; + } + // Total cert length includes the Tag + length + // Adding it here. + certSize += 2 + numLenBytes; + } + + // + // Check to make sure we have not hit end of buffer, and there is space for AK cert. + // Check for underflow as well. This makes sure we haven't missed the calculation to + // go past the end of the buffer + // + if (pCert + (certSize - 1) > bufferEnd || + pCert + (certSize - 1) <= pCert) + { + NV_PRINTF(LEVEL_ERROR, " %s: pCert + (certSize(0x%x) - 1) is not a valid value !! \n", + __FUNCTION__, certSize); + + return NV_ERR_BUFFER_TOO_SMALL; + } + + *pCertLength = certSize; + return NV_OK; +} + +static NV_STATUS +pem_write_buffer +( + NvU8 const *der, + NvU64 derLen, + NvU8 *buffer, + NvU64 bufferLen, + NvU64 *bufferUsed +) +{ + static const NvU8 base64[] = "ABCDEFGHIJKLMNOPQRSTUVWXYZabcdefghijklmnopqrstuvwxyz0123456789+/"; + NvU64 i, tmp, size; + NvU64 printed = 0; + NvU8 *ptr = buffer; + + // Base64 encoded size + size = (derLen + 2) / 3 * 4; + + // Add 1 byte per 64 for newline + size = size + (size + 63) / 64; + + // Add header excluding the terminating null and footer including the null + size += sizeof(SPDM_PEM_BEGIN_CERTIFICATE) - 1 + + sizeof(SPDM_PEM_END_CERTIFICATE); + + if (bufferLen < size) + { + return NV_ERR_BUFFER_TOO_SMALL; + } + + portMemCopy(ptr, bufferLen - (ptr - buffer), SPDM_PEM_BEGIN_CERTIFICATE, + sizeof(SPDM_PEM_BEGIN_CERTIFICATE) - 1); + ptr += sizeof(SPDM_PEM_BEGIN_CERTIFICATE) - 1; + + for (i = 0; (i + 2) < derLen; i += 3) + { + tmp = (der[i] << 16) | (der[i + 1] << 8) | (der[i + 2]); + *ptr++ = base64[(tmp >> 18) & 63]; + *ptr++ = base64[(tmp >> 12) & 63]; + *ptr++ = base64[(tmp >> 6) & 63]; + *ptr++ = base64[(tmp >> 0) & 63]; + + printed += 4; + if (printed == 64) + { + *ptr++ = '\n'; + printed = 0; + } + } + + if ((i == derLen) && (printed != 0)) + { + *ptr++ = '\n'; + } + + // 1 byte extra + if (i == (derLen - 1)) + { + tmp = der[i] << 4; + *ptr++ = base64[(tmp >> 6) & 63]; + *ptr++ = base64[(tmp >> 0) & 63]; + *ptr++ = '='; + *ptr++ = '='; + *ptr++ = '\n'; + } + + // 2 byte extra + if (i == (derLen - 2)) + { + tmp = ((der[i] << 8) | (der[i + 1])) << 2; + *ptr++ = base64[(tmp >> 12) & 63]; + *ptr++ = base64[(tmp >> 6) & 63]; + *ptr++ = base64[(tmp >> 0) & 63]; + *ptr++ = '='; + *ptr++ = '\n'; + } + + portMemCopy(ptr, bufferLen - (ptr - buffer), SPDM_PEM_END_CERTIFICATE, + sizeof(SPDM_PEM_END_CERTIFICATE)); + ptr += sizeof(SPDM_PEM_END_CERTIFICATE); + + *bufferUsed = size; + return NV_OK; +} + +/*! +* Static function builds the cert chain in DER format. It is assumed that +* the all the certificates are valid. Also it is assumed that there is a valid +* spdm session already established. +*/ +static NV_STATUS +_spdmBuildCertChainDer +( + NvU8 *pFirstCert, + NvU32 firstCertSize, + NvU8 *pSecondCert, + NvU32 secondCertSize, + NvU8 *pOutBuffer, + size_t *outBufferSize +) +{ + NvU64 remainingOutBufferSize = 0; + NvU64 totalSize = 0; + void *pPortMemCopyStatus = NULL; + + if (pFirstCert == NULL || pSecondCert == NULL || pOutBuffer == NULL || outBufferSize == NULL) + { + return NV_ERR_INVALID_ARGUMENT; + } + + // Calculate the total size of the certificate chain (in DER). + totalSize = sizeof(SPDM_L1_CERTIFICATE_DER) + + sizeof(SPDM_L2_CERTIFICATE_DER) + + sizeof(SPDM_L3_CERTIFICATE_DER) + + secondCertSize + + firstCertSize; + + remainingOutBufferSize = *outBufferSize; + if (remainingOutBufferSize < totalSize) + { + return NV_ERR_BUFFER_TOO_SMALL; + } + + // + // Write the L1 DER certificate to the output buffer + // + pPortMemCopyStatus = portMemCopy(pOutBuffer, + remainingOutBufferSize, + SPDM_L1_CERTIFICATE_DER, + sizeof(SPDM_L1_CERTIFICATE_DER)); + if (pPortMemCopyStatus == NULL) + { + return NV_ERR_BUFFER_TOO_SMALL; + } + + remainingOutBufferSize -= sizeof(SPDM_L1_CERTIFICATE_DER); + pOutBuffer += sizeof(SPDM_L1_CERTIFICATE_DER); + + // + // Write the L2 DER certificate to the output buffer + // + pPortMemCopyStatus = portMemCopy(pOutBuffer, + remainingOutBufferSize, + SPDM_L2_CERTIFICATE_DER, + sizeof(SPDM_L2_CERTIFICATE_DER)); + if (pPortMemCopyStatus == NULL) + { + return NV_ERR_BUFFER_TOO_SMALL; + } + + remainingOutBufferSize -= sizeof(SPDM_L2_CERTIFICATE_DER); + pOutBuffer += sizeof(SPDM_L2_CERTIFICATE_DER); + + // + // Write the L3 DER certificate to the output buffer + // + pPortMemCopyStatus = portMemCopy(pOutBuffer, + remainingOutBufferSize, + SPDM_L3_CERTIFICATE_DER, + sizeof(SPDM_L3_CERTIFICATE_DER)); + if (pPortMemCopyStatus == NULL) + { + return NV_ERR_BUFFER_TOO_SMALL; + } + + remainingOutBufferSize -= sizeof(SPDM_L3_CERTIFICATE_DER); + pOutBuffer += sizeof(SPDM_L3_CERTIFICATE_DER); + + // + // Write the IK certificate in DER to the output buffer + // + pPortMemCopyStatus = portMemCopy(pOutBuffer, + remainingOutBufferSize, + pSecondCert, + secondCertSize); + if (pPortMemCopyStatus == NULL) + { + return NV_ERR_BUFFER_TOO_SMALL; + } + + remainingOutBufferSize -= secondCertSize; + pOutBuffer += secondCertSize; + + // + // Write the AK certificate in DER to the output buffer + // + pPortMemCopyStatus = portMemCopy(pOutBuffer, + remainingOutBufferSize, + pFirstCert, + firstCertSize); + if (pPortMemCopyStatus == NULL) + { + return NV_ERR_BUFFER_TOO_SMALL; + } + + remainingOutBufferSize -= firstCertSize; + pOutBuffer += firstCertSize; + + // Output the total certificate chain size + *outBufferSize = totalSize; + + return NV_OK; +} + +/*! +* Static function that first converts the IK and AK certificates from DER to +* PEM format. Then it builds the cert chain in PEM format. It is assumed that +* the all the certificates are valid. Also it is assumed that there is a valid +* spdm session already established. +*/ +static NV_STATUS +_spdmBuildCertChainPem +( + NvU8 *pFirstCert, + NvU32 firstCertSize, + NvU8 *pSecondCert, + NvU32 secondCertSize, + NvU8 *pOutBuffer, + size_t *outBufferSize +) +{ + NvU64 firstCertOutputSize = 0; + NvU64 secondCertOutputSize = 0; + NvU64 remainingOutBufferSize = 0; + void *pPortMemCopyStatus = NULL; + NV_STATUS status; + + if (pFirstCert == NULL || pSecondCert == NULL || pOutBuffer == NULL || outBufferSize == NULL) + { + return NV_ERR_INVALID_ARGUMENT; + } + + remainingOutBufferSize = *outBufferSize; + + // + // Write the AK certificate to the output buffer + // + status = pem_write_buffer(pFirstCert, firstCertSize, pOutBuffer, + remainingOutBufferSize, &firstCertOutputSize); + if (status != NV_OK) + { + return status; + } + + // + // Keep track how much space we have left in the output buffer + // and where the next certificate should start. + // Clear the last byte (NULL). + // + remainingOutBufferSize -= firstCertOutputSize - 1; + pOutBuffer += firstCertOutputSize - 1; + + // + // Write the IK certificate to the output buffer + // + status = pem_write_buffer(pSecondCert, secondCertSize, pOutBuffer, + remainingOutBufferSize, &secondCertOutputSize); + if (status != NV_OK) + { + return status; + } + + remainingOutBufferSize -= secondCertOutputSize - 1; + pOutBuffer += secondCertOutputSize - 1; + + // Checking if the available size of buffer is enough to keep the whole + // certificate chain otherwise raise error. + if (remainingOutBufferSize < sizeof(SPDM_L1_CERTIFICATE_PEM) + + sizeof(SPDM_L2_CERTIFICATE_PEM) + + sizeof(SPDM_L3_CERTIFICATE_PEM)) + { + return NV_ERR_BUFFER_TOO_SMALL; + } + + // + // Write the L3 certificate to the output buffer + // + pPortMemCopyStatus = portMemCopy(pOutBuffer, + remainingOutBufferSize, + SPDM_L3_CERTIFICATE_PEM, + sizeof(SPDM_L3_CERTIFICATE_PEM) - 1); + if (pPortMemCopyStatus == NULL) + { + return NV_ERR_BUFFER_TOO_SMALL; + } + + remainingOutBufferSize -= sizeof(SPDM_L3_CERTIFICATE_PEM) - 1; + pOutBuffer += sizeof(SPDM_L3_CERTIFICATE_PEM) - 1; + + // + // Write the L2 certificate to the output buffer + // + pPortMemCopyStatus = portMemCopy(pOutBuffer, + remainingOutBufferSize, + SPDM_L2_CERTIFICATE_PEM, + sizeof(SPDM_L2_CERTIFICATE_PEM) - 1); + if (pPortMemCopyStatus == NULL) + { + return NV_ERR_BUFFER_TOO_SMALL; + } + remainingOutBufferSize -= sizeof(SPDM_L2_CERTIFICATE_PEM) - 1; + pOutBuffer += sizeof(SPDM_L2_CERTIFICATE_PEM) - 1; + + // + // Write the L1 certificate to the output buffer + // + pPortMemCopyStatus = portMemCopy(pOutBuffer, + remainingOutBufferSize, + SPDM_L1_CERTIFICATE_PEM, + sizeof(SPDM_L1_CERTIFICATE_PEM) - 1); + if (pPortMemCopyStatus == NULL) + { + return NV_ERR_BUFFER_TOO_SMALL; + } + + // + // Output the total certificate chain size + // Do not count the NULL bytes. + // + *outBufferSize = firstCertOutputSize - 1 + + secondCertOutputSize - 1 + + sizeof(SPDM_L3_CERTIFICATE_PEM) - 1 + + sizeof(SPDM_L2_CERTIFICATE_PEM) - 1 + + sizeof(SPDM_L1_CERTIFICATE_PEM) - 1; + + return NV_OK; +} + +/* ------------------------ Public Functions ------------------------------- */ +NV_STATUS +spdmGetCertificates_GH100 +( + OBJGPU *pGpu, + Spdm *pSpdm +) +{ + NV_STATUS status = NV_OK; + NvU8 *pIkCertificate = NULL; + NvU32 ikCertificateSize = 0; + NvU8 *pAkCertificate = NULL; + NvU32 akCertificateSize = 0; + NvU8 *pGpuCerts = NULL; + size_t gpuCertsSize = 0; + NvU8 *pDerCertChain = NULL; + size_t derCertChainSize = 0; + NvU8 *pSpdmCertChainBufferEnd = NULL; + libspdm_context_t *pContext = NULL; + uint32_t base_hash_algo = 0; + NvU32 totalSize = 0; + + if (pGpu == NULL || pSpdm == NULL) + { + return NV_ERR_INVALID_ARGUMENT; + } + + if (pSpdm->pLibspdmContext == NULL) + { + return NV_ERR_NOT_READY; + } + + // Allocate buffer for certificates. + gpuCertsSize = LIBSPDM_MAX_CERT_CHAIN_SIZE; + pGpuCerts = portMemAllocNonPaged(gpuCertsSize); + derCertChainSize = SPDM_MAX_ENCODED_CERT_CHAIN_SIZE; + pDerCertChain = portMemAllocNonPaged(derCertChainSize); + pSpdm->attestationCertChainSize = SPDM_MAX_ENCODED_CERT_CHAIN_SIZE; + pSpdm->pAttestationCertChain = portMemAllocNonPaged(pSpdm->attestationCertChainSize); + + // Ensure data was properly allocated. + if (pGpuCerts == NULL || pDerCertChain == NULL || pSpdm->pAttestationCertChain == NULL) + { + status = NV_ERR_NO_MEMORY; + goto ErrorExit; + } + + portMemSet(pGpuCerts, 0, gpuCertsSize); + portMemSet(pDerCertChain, 0, derCertChainSize); + portMemSet(pSpdm->pAttestationCertChain, 0, pSpdm->attestationCertChainSize); + + // We fetch Attestation cert chain only on Hopper. + CHECK_SPDM_STATUS(libspdm_get_certificate(pSpdm->pLibspdmContext, SPDM_CERT_DEFAULT_SLOT_ID, + &gpuCertsSize, pGpuCerts)); + + // Now, append the root certificates to create the entire chain. + pContext = (libspdm_context_t *)pSpdm->pLibspdmContext; + + // + // Skip over the certificate chain size, reserved size and the root hash + // pSpdmCertChainBufferEnd represents last valid byte for cert buffer. + // + pSpdmCertChainBufferEnd = pGpuCerts + gpuCertsSize - 1; + base_hash_algo = pContext->connection_info.algorithm.base_hash_algo; + pIkCertificate = (NvU8 *)pGpuCerts; + pIkCertificate += sizeof(spdm_cert_chain_t) + libspdm_get_hash_size(base_hash_algo); + + // Calculate the size of the IK cert, and skip past it to get the AK cert. + status = _calcX509CertSize(pIkCertificate, pSpdmCertChainBufferEnd, &ikCertificateSize); + + if (status != NV_OK) + { + goto ErrorExit; + } + + pAkCertificate = (NvU8 *)pIkCertificate + ikCertificateSize; + + // Calculate the size of the AK certificate. + status = _calcX509CertSize(pAkCertificate, pSpdmCertChainBufferEnd, &akCertificateSize); + if (status != NV_OK) + { + return status; + } + + // Make sure we have calculated the size correctly. + if ((pAkCertificate + akCertificateSize - 1) != pSpdmCertChainBufferEnd) + { + return NV_ERR_BUFFER_TOO_SMALL; + } + + // Retrieve the entire certificate chain in DER format in order to validate it. + status = _spdmBuildCertChainDer(pAkCertificate, akCertificateSize, + pIkCertificate, ikCertificateSize, + pDerCertChain, + &derCertChainSize); + + if (status != NV_OK) + { + goto ErrorExit; + } + + totalSize = sizeof(SPDM_L1_CERTIFICATE_DER) + + sizeof(SPDM_L2_CERTIFICATE_DER) + + sizeof(SPDM_L3_CERTIFICATE_DER) + + akCertificateSize + + ikCertificateSize; + + if (derCertChainSize != totalSize) + { + NV_PRINTF(LEVEL_ERROR, " %s: derCertChainSize(%lu) != totalSize(0x%x) !! \n", + __FUNCTION__, derCertChainSize, totalSize); + + // Something has gone quite wrong with our calculations. + status = NV_ERR_BUFFER_TOO_SMALL; + goto ErrorExit; + } + + // Now, validate that the certificate chain is correctly signed. + if (!libspdm_x509_verify_cert_chain(pDerCertChain, sizeof(SPDM_L1_CERTIFICATE_DER), + pDerCertChain + sizeof(SPDM_L1_CERTIFICATE_DER), + derCertChainSize - sizeof(SPDM_L1_CERTIFICATE_DER))) + { + status = NV_ERR_INVALID_DATA; + goto ErrorExit; + } + + // + // Now that the cert chain is valid, retrieve the cert chain in PEM format, + // as the Verifier can only parse PEM format. + // + status = _spdmBuildCertChainPem(pAkCertificate, akCertificateSize, + pIkCertificate, ikCertificateSize, + pSpdm->pAttestationCertChain, + &pSpdm->attestationCertChainSize); + if (status != NV_OK) + { + goto ErrorExit; + } + +ErrorExit: + // + // In both success and failure we need to free these allocated buffers. + // portMemFree() will handle if they are NULL. On success, keep + // the local pAttestationCertChain buffer. + // + portMemFree(pGpuCerts); + portMemFree(pDerCertChain); + + if (status != NV_OK) + { + // portMemFree() handles NULL. + portMemFree(pSpdm->pAttestationCertChain); + pSpdm->pAttestationCertChain = NULL; + pSpdm->attestationCertChainSize = 0; + } + + return status; +} + +NV_STATUS +spdmGetCertChains_GH100 +( + OBJGPU *pGpu, + Spdm *pSpdm, + void *pKeyExCertChain, + NvU32 *pKeyExCertChainSize, + void *pAttestationCertChain, + NvU32 *pAttestationCertChainSize +) +{ + if (pGpu == NULL || pSpdm == NULL || pAttestationCertChain == NULL || + pAttestationCertChainSize == NULL) + { + return NV_ERR_INVALID_ARGUMENT; + } + + // Check that we're in a valid state. + if (pSpdm->pLibspdmContext == NULL || pSpdm->pAttestationCertChain == NULL || + pSpdm->attestationCertChainSize == 0) + { + return NV_ERR_NOT_READY; + } + + // We only support Attestation certificates on Hopper. + if (pKeyExCertChainSize != NULL) + { + pKeyExCertChainSize = 0; + } + + if (*pAttestationCertChainSize < pSpdm->attestationCertChainSize) + { + return NV_ERR_BUFFER_TOO_SMALL; + } + + portMemCopy(pAttestationCertChain, *pAttestationCertChainSize, + pSpdm->pAttestationCertChain, pSpdm->attestationCertChainSize); + *pAttestationCertChainSize = pSpdm->attestationCertChainSize; + + return NV_OK; +} diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/kernel/gpu/spdm/arch/hopper/spdm_gh100.c nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/kernel/gpu/spdm/arch/hopper/spdm_gh100.c --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/kernel/gpu/spdm/arch/hopper/spdm_gh100.c 1970-01-01 00:00:00.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/kernel/gpu/spdm/arch/hopper/spdm_gh100.c 2024-03-05 22:13:49.000000000 +0000 @@ -0,0 +1,1334 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2022-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +/*! + * Provides the implementation for all GH100 specific SPDM HALs + * interfaces. + */ + +/* ------------------------ Includes --------------------------------------- */ +#include "nvRmReg.h" +#include "gpu/spdm/spdm.h" +#include "spdm/rmspdmtransport.h" +#include "spdm/rmspdmvendordef.h" +#include "objtmr.h" +#include "gpu/bus/kern_bus.h" +#include "gpu/mem_mgr/mem_mgr.h" +#include "gpu/spdm/libspdm_includes.h" +#include "rmapi/client_resource.h" +#include "ctrl/ctrl2080/ctrl2080spdm.h" +#include "flcnretval.h" +#include "gpu/conf_compute/conf_compute.h" + +/* ------------------------ Macros ----------------------------------------- */ +#define SPDM_MESSAGE_BUFFER_ADDRESS_ALIGNMENT (256) + +#define SPDM_CAPABILITIES_FLAGS_GH100 \ + SPDM_GET_CAPABILITIES_RESPONSE_FLAGS_CERT_CAP | \ + SPDM_GET_CAPABILITIES_RESPONSE_FLAGS_MEAS_CAP_SIG | \ + SPDM_GET_CAPABILITIES_RESPONSE_FLAGS_MEAS_FRESH_CAP | \ + SPDM_GET_CAPABILITIES_RESPONSE_FLAGS_ENCRYPT_CAP | \ + SPDM_GET_CAPABILITIES_RESPONSE_FLAGS_MAC_CAP | \ + SPDM_GET_CAPABILITIES_RESPONSE_FLAGS_KEY_EX_CAP | \ + SPDM_GET_CAPABILITIES_RESPONSE_FLAGS_KEY_UPD_CAP + +/* ------------------------ Types Definitions ------------------------------ */ +/*! + * Define context structure which tracks all state required for IO between + * RM and GSP. They communicate via a shared memory surface in which SPDM + * payloads are stored, and use the RM<->GSP command queue to alert of payloads. + */ +typedef struct _SPDM_GSP_IO_CONTEXT +{ + /*! + * Buffer to store SPDM response read from memory surface. Required since + * libspdm splits send and receive message across two message calls. + */ + NV_DECLARE_ALIGNED(NvU8 *pResponse, 8); + + /*! The memory descriptor that describes the memory surface */ + NV_DECLARE_ALIGNED(MEMORY_DESCRIPTOR *pMemDesc, 8); + + /*! + * The size of the surface. This information is also contained in + * the surfaces's memory descriptor but is still required since + * surface structures will be allocated and populated before the + * underlying surfaces are allocated themselves (time at which the + * memory descriptors will allocated and populated). + */ + NvU32 surfaceSizeInByte; + + /*! + * Represents the amount by which the actual size of the surface will + * aligned when the surface is allocated. + */ + NvU32 alignSize; + + /*! + * Stores the address that the GSP will use when accessing the surface. + */ + NvU64 dmaAddr; + + /*! + * Address space for memory surface (sysmem or FB). + */ + NvU32 addrSpace; + + /*! + * Sequence number for the memory surface. + */ + NvU32 seqNum; + + /*! + * Region ID for the payload (i.e. unprotected, protected). + */ + NvU32 regionId; + + /*! + * Size allocated for the SPDM message decription header, which + * describes the payload contained in the surface. + */ + NvU32 descHdrSizeInByte; + + /*! + * Size of the surface available to RM for storing SPDM messages. + */ + NvU32 rmBufferSizeInByte; + + /*! + * Size of the above response buffer. + */ + NvU32 responseSize; + +} SPDM_GSP_IO_CONTEXT; + +/* ------------------------ Static Variables ------------------------------- */ +// +// For transport functionality, we require access to the GPU and Spdm objects. +// However, libspdm transport layer currently does not support passing any custom +// parameters, meaning we must use static variables to access these objects. +// If we ever require multiple instances of the Spdm object, this will be an issue. +// +static OBJGPU *g_pGpu = NULL; +static Spdm *g_pSpdm = NULL; + +static SPDM_ALGO_CHECK_ENTRY g_SpdmAlgoCheckTable_GH100[] = +{ + { LIBSPDM_DATA_MEASUREMENT_SPEC, SPDM_MEASUREMENT_BLOCK_HEADER_SPECIFICATION_DMTF }, + { LIBSPDM_DATA_MEASUREMENT_HASH_ALGO, SPDM_ALGORITHMS_MEASUREMENT_HASH_ALGO_TPM_ALG_SHA_384 }, + { LIBSPDM_DATA_BASE_ASYM_ALGO, SPDM_ALGORITHMS_BASE_ASYM_ALGO_TPM_ALG_ECDSA_ECC_NIST_P384 }, + { LIBSPDM_DATA_BASE_HASH_ALGO, SPDM_ALGORITHMS_BASE_HASH_ALGO_TPM_ALG_SHA_384 }, + { LIBSPDM_DATA_DHE_NAME_GROUP, SPDM_ALGORITHMS_DHE_NAMED_GROUP_SECP_384_R1 }, + { LIBSPDM_DATA_AEAD_CIPHER_SUITE, SPDM_ALGORITHMS_AEAD_CIPHER_SUITE_AES_256_GCM }, + { LIBSPDM_DATA_KEY_SCHEDULE, SPDM_ALGORITHMS_KEY_SCHEDULE_HMAC_HASH }, + { LIBSPDM_DATA_OTHER_PARAMS_SUPPORT, 0 }, + { LIBSPDM_DATA_REQ_BASE_ASYM_ALG, 0 } +}; + +/* ------------------------ Static Function Prototypes --------------------- */ +static void _spdmReleaseSurfaceGsp(Spdm *pSpdm); + +static NV_STATUS _spdmErrorCheck(RM_GSP_SPDM_MSG *pSpdmMsg, + NvU32 guestIdChk, + NvU32 endpointIdChk, + NvU32 cmdType); + +// +// Static transport layer functions which we pass to libspdm as function pointers. +// The libspdm library will then use these functions to send and receive SPDM messages. +// Function parameters and types must match those expected by libspdm. +// +static uint32_t _spdmGetTransportHeaderSizeGsp(void *spdm_context); + +static libspdm_return_t _spdmEncodeMessageGsp(void *spdm_context, const uint32_t *session_id, + bool is_app_message, bool is_requester, + size_t message_size, void *message, + size_t *transport_message_size, + void **transport_message); + +static libspdm_return_t _spdmDecodeMessageGsp(void *spdm_context, uint32_t **session_id, + bool *is_app_message, bool is_requester, + size_t transport_message_size, void *transport_message, + size_t *message_size, void **message); + +static libspdm_return_t _spdmSendMessageGsp(void *spdm_context, size_t message_size, + const void *message, uint64_t timeout); + +static libspdm_return_t _spdmReceiveMessageGsp(void *spdm_context, size_t *message_size, + void **message, uint64_t timeout); + +static NV_STATUS _spdmSendInitRmDataCommand(OBJGPU *pGpu, Spdm *pSpdm); + +/* ------------------------ Static Functions ------------------------------- */ +/*! + * Frees all memory and state associated with the GSP SPDM-message surface. + */ +void +_spdmReleaseSurfaceGsp +( + Spdm *pSpdm +) +{ + SPDM_GSP_IO_CONTEXT *pIOContext = NULL; + + if (pSpdm == NULL || pSpdm->pDeviceIOContext == NULL) + { + NV_PRINTF(LEVEL_ERROR, "SPDM: Attempting to release NULL MemDesc, this is BUG!\n"); + DBG_BREAKPOINT(); + return; + } + + pIOContext = (SPDM_GSP_IO_CONTEXT *)pSpdm->pDeviceIOContext; + memdescFree(pIOContext->pMemDesc); + memdescDestroy(pIOContext->pMemDesc); + portMemFree(pIOContext->pResponse); + portMemSet(pIOContext, 0, sizeof(SPDM_GSP_IO_CONTEXT)); + portMemFree(pIOContext); + + // Ensure we clear object context pointer. + pSpdm->pDeviceIOContext = NULL; +} + +/*! + * Performs validation of received RPC SPDM message and + * by comparing the message against expected values. Used + * to detect mismatch between attributes of request sent + * and attributes of response received. + * + * @param[in] pSpdmMsg Pointer to SPDM Message structure. + * @param[in] guestIdChk Expected guest ID. + * @param[in] endpointIdChk Expected endpoint ID. + * @param[in] cmdType SPDM command type. + */ +NV_STATUS +_spdmErrorCheck +( + RM_GSP_SPDM_MSG *pSpdmMsg, + NvU32 guestIdChk, + NvU32 endpointIdChk, + NvU32 cmdType +) +{ + // Perform validation of received RPC SPDM message. + if (pSpdmMsg->status != FLCN_OK) + { + NV_PRINTF(LEVEL_ERROR, "SPDM: RPC message error : status = 0x%x.\n", + pSpdmMsg->status); + + DBG_BREAKPOINT(); + return NV_ERR_GENERIC; + } + + // Perform validation of received SPDM message description header only if SPDM RPC message status is FLCN_OK. + if (pSpdmMsg->version != NV_SPDM_DESC_HEADER_VERSION_CURRENT) + { + NV_PRINTF(LEVEL_ERROR, + "SPDM: Version mismatch: [Check] version = 0x%x, [SpdmRet] version = 0x%x\n", + NV_SPDM_DESC_HEADER_VERSION_CURRENT, pSpdmMsg->version); + DBG_BREAKPOINT(); + return NV_ERR_GENERIC; + } + + if (pSpdmMsg->guestId != guestIdChk) + { + NV_PRINTF(LEVEL_ERROR, + "SPDM: Guest ID mismatch: [Check] guestId = 0x%x, [SpdmRet] guestId = 0x%x\n", + guestIdChk, pSpdmMsg->guestId); + DBG_BREAKPOINT(); + return NV_ERR_GENERIC; + } + + if (cmdType != RM_GSP_SPDM_CMD_ID_CC_INIT) + { + if (pSpdmMsg->endpointId != endpointIdChk) + { + NV_PRINTF(LEVEL_ERROR, + "SPDM: Endpoint ID mismatch: [Check] endpointId = 0x%x, [SpdmRet] endpointId = 0x%x\n", + endpointIdChk, pSpdmMsg->endpointId); + DBG_BREAKPOINT(); + return NV_ERR_GENERIC; + } + } + + return NV_OK; +} + +/*! + * Callback to fill out sequence number in expected format. + * The sequence number is for secured message format only and defined in DMTF DSP0277. + * Currently, requester(RM) and responder(GSP-SPDM) doesn't support sequence number. + */ +uint8_t +_spdmGetSequenceNumberGsp +( + uint64_t sequence_number, + uint8_t *sequence_number_buffer +) +{ + // No sequence number included as a part of GSP secured message. + return 0; +} + +/*! + * Callback to fill RNG blob in secured message. + * The random number size is for secured message format only and defined in DMTF DSP0277. + */ +uint32_t +_spdmGetMaxRandomNumberCountGsp +( + void +) +{ + return NV_SPDM_MAX_RANDOM_MSG_BYTES; +} + +/*! + * Callback to get allocated space for transport header that is pre-pended + * to the SPDM message. Return the size of the NV_SPDM_MESSAGE_HEADER we prepend. + */ +uint32_t +_spdmGetTransportHeaderSizeGsp +( + void *spdm_context +) +{ + return sizeof(NV_SPDM_DESC_HEADER); +} + +/*! + * Static function libspdm uses as hook to RM<->GSP transport layer. + * If secured, encodes message into SPDM Secured Message format. + */ +libspdm_return_t +_spdmEncodeMessageGsp +( + void *spdm_context, + const uint32_t *session_id, + bool is_app_message, + bool is_requester, + size_t message_size, + void *message, + size_t *transport_message_size, + void **transport_message +) +{ + libspdm_secured_message_callbacks_t securedMessageInfo; + libspdm_return_t status = LIBSPDM_STATUS_SUCCESS; + size_t securedMessageSize = 0; + void *pSecuredMessageContext = NULL; + NV_SPDM_DESC_HEADER *pNvSpdmDescHdr = NULL; + NvU32 payloadSize = 0; + SPDM_GSP_IO_CONTEXT *pIOContext = NULL; + + pIOContext = (SPDM_GSP_IO_CONTEXT *)g_pSpdm->pDeviceIOContext; + + // Check libspdm parameters. + if (spdm_context == NULL || message == NULL || message_size == 0 || + transport_message == NULL || *transport_message == NULL || + transport_message_size == NULL || pIOContext == NULL) + { + return LIBSPDM_STATUS_INVALID_PARAMETER; + } + + // Only support sending requester SPDM/Secured messages. + if (!is_requester || is_app_message) + { + return LIBSPDM_STATUS_INVALID_PARAMETER; + } + + // The transport buffer must be large enough to fit the transport header and the message. + if (*transport_message_size < (sizeof(NV_SPDM_DESC_HEADER) + message_size)) + { + return LIBSPDM_STATUS_INVALID_MSG_FIELD; + } + + // Initialize descriptor header. + pNvSpdmDescHdr = (NV_SPDM_DESC_HEADER *)*transport_message; + portMemSet(pNvSpdmDescHdr, 0, sizeof(NV_SPDM_DESC_HEADER)); + + // Determine whether message is secured. + if (session_id != NULL) + { + pNvSpdmDescHdr->msgType = NV_SPDM_MESSAGE_TYPE_SECURED; + + pSecuredMessageContext = + libspdm_get_secured_message_context_via_session_id(spdm_context, *session_id); + + if (pSecuredMessageContext == NULL) + { + return LIBSPDM_STATUS_SESSION_MSG_ERROR; + } + + // Calculate max space we have for secured message in transport buffer. + securedMessageSize = *transport_message_size; + securedMessageSize -= sizeof(NV_SPDM_DESC_HEADER); + + // Initialize secured message attributes. + portMemSet(&securedMessageInfo, 0, sizeof(securedMessageInfo)); + securedMessageInfo.version = SPDM_SECURED_MESSAGE_CALLBACKS_VERSION; + securedMessageInfo.get_sequence_number = _spdmGetSequenceNumberGsp; + securedMessageInfo.get_max_random_number_count = _spdmGetMaxRandomNumberCountGsp; + + // Encode secured message into output buffer. + status = libspdm_encode_secured_message(pSecuredMessageContext, *session_id, is_requester, + message_size, message, &securedMessageSize, + (pNvSpdmDescHdr + 1), &securedMessageInfo); + if (status != LIBSPDM_STATUS_SUCCESS) + { + return status; + } + + // Transport message buffer must be large enough to store secured message + NV_SPDM_DESC_HEADER. + NV_ASSERT_OR_RETURN(*transport_message_size > (securedMessageSize + sizeof(NV_SPDM_DESC_HEADER)), + LIBSPDM_STATUS_INVALID_MSG_FIELD); + + pNvSpdmDescHdr->msgSizeByte = (NvU32)securedMessageSize; + *transport_message_size = securedMessageSize + sizeof(NV_SPDM_DESC_HEADER); + } + else + { + // The normal message is not encrypted, it will be sent as NV_SPDM_DESC_HEADER + Message. + payloadSize = sizeof(NV_SPDM_DESC_HEADER) + message_size; + + // + // Check for large enough buffer for payload, as well as for overflow in + // operation above. If no overflow, we know message_size fits in NvU32. + // + if (*transport_message_size < payloadSize || payloadSize < message_size) + { + return LIBSPDM_STATUS_BUFFER_TOO_SMALL; + } + + // + // Fill in SPDM message header. + // The SPDM message is already after the SPDM msg header. + // + pNvSpdmDescHdr->msgType = NV_SPDM_MESSAGE_TYPE_NORMAL; + pNvSpdmDescHdr->msgSizeByte = (NvU32)message_size; + *transport_message_size = payloadSize; + } + + // Check final encrypted message size. + if (*transport_message_size > NV_SPDM_RM_SURFACE_SIZE_IN_BYTE) + { + return LIBSPDM_STATUS_BUFFER_TOO_SMALL; + } + + // Record the message in the last exchange transcript. + if (message_size > SPDM_MAX_EXCHANGE_BUFFER_SIZE) + { + return LIBSPDM_STATUS_INVALID_PARAMETER; + } + + portMemCopy(g_pSpdm->pLastExchange, SPDM_MAX_EXCHANGE_BUFFER_SIZE, + message, message_size); + g_pSpdm->lastExchangeSize = message_size; + + return LIBSPDM_STATUS_SUCCESS; +} + +/*! + * Static function libspdm uses as hook to RM<->GSP transport layer. + * If secured, decodes the message from the SPDM Secured Message format. + */ +libspdm_return_t +_spdmDecodeMessageGsp +( + void *spdm_context, + uint32_t **session_id, + bool *is_app_message, + bool is_requester, + size_t transport_message_size, + void *transport_message, + size_t *message_size, + void **message +) +{ + libspdm_secured_message_callbacks_t securedMessageInfo; + NV_SPDM_DESC_HEADER *pNvSpdmDescHdr = NULL; + NvU32 payloadSize = 0; + void *pSecuredMessageContext = NULL; + libspdm_return_t status = LIBSPDM_STATUS_SUCCESS; + NvU32 lastExchangeSizeLeft = 0; + spdm_secured_message_a_data_header1_t *pSpdmSecuredMsgHdr = NULL; + + // Check libspdm parameters. + if (spdm_context == NULL || session_id == NULL || is_app_message == NULL || + transport_message_size == 0 || transport_message == NULL || + message_size == NULL || message == NULL || *message == NULL) + { + return LIBSPDM_STATUS_INVALID_PARAMETER; + } + + // Only support receiving Responder SPDM/Secured messages. + if (is_requester) + { + return LIBSPDM_STATUS_INVALID_PARAMETER; + } + + // Retrieve NV-header from message, and perform basic validation. + pNvSpdmDescHdr = (NV_SPDM_DESC_HEADER *)transport_message; + if (transport_message_size < sizeof(NV_SPDM_DESC_HEADER) || + transport_message_size > NV_SPDM_RM_SURFACE_SIZE_IN_BYTE) + { + return LIBSPDM_STATUS_INVALID_MSG_FIELD; + } + + payloadSize = NV_SPDM_DESC_HEADER_SIZE_IN_BYTE + pNvSpdmDescHdr->msgSizeByte; + + if (transport_message_size != payloadSize) + { + return LIBSPDM_STATUS_INVALID_MSG_FIELD; + } + + // Decode message, based on type. + switch (pNvSpdmDescHdr->msgType) + { + case NV_SPDM_MESSAGE_TYPE_SECURED: + { + // + // Double-check the payload fits a secured message header. + // Our implementation of a secure message header only includes + // session ID - no sequence number. + // + if (pNvSpdmDescHdr->msgSizeByte < sizeof(spdm_secured_message_a_data_header1_t)) + { + return LIBSPDM_STATUS_INVALID_MSG_FIELD; + } + + // Secured message header begins immediately after general NV header. + pSpdmSecuredMsgHdr = (spdm_secured_message_a_data_header1_t *)(pNvSpdmDescHdr + 1); + *session_id = &pSpdmSecuredMsgHdr->session_id; + + pSecuredMessageContext = + libspdm_get_secured_message_context_via_session_id(spdm_context, **session_id); + + if (pSecuredMessageContext == NULL) + { + return LIBSPDM_STATUS_SESSION_MSG_ERROR; + } + + // Initialize secured message attributes. + portMemSet(&securedMessageInfo, 0, sizeof(securedMessageInfo)); + securedMessageInfo.version = SPDM_SECURED_MESSAGE_CALLBACKS_VERSION; + securedMessageInfo.get_sequence_number = _spdmGetSequenceNumberGsp; + securedMessageInfo.get_max_random_number_count = _spdmGetMaxRandomNumberCountGsp; + + // Decode and retrieve application payload from secured message. + // We must copy the message to the scratch buffer. + status = libspdm_decode_secured_message(pSecuredMessageContext, + **session_id, is_requester, + transport_message_size - NV_SPDM_DESC_HEADER_SIZE_IN_BYTE, + (pNvSpdmDescHdr + 1), message_size, + message, &securedMessageInfo); + if (status != LIBSPDM_STATUS_SUCCESS) + { + return status; + } + } + break; + + case NV_SPDM_MESSAGE_TYPE_NORMAL: + { + // Indicate the message is unsecured. + *session_id = NULL; + + // + // We both check that the buffer is large enough, and that the + // size_t type is large enough to hold the size of the message. + // + if (*message_size < pNvSpdmDescHdr->msgSizeByte) + { + return LIBSPDM_STATUS_BUFFER_TOO_SMALL; + } + + // The message is already present in the receiver buffer. + // Just use that. + *message = (uint8_t *)(pNvSpdmDescHdr + 1); + *message_size = pNvSpdmDescHdr->msgSizeByte; + } + break; + + default: + { + return LIBSPDM_STATUS_INVALID_MSG_FIELD; + } + } + + // We don't expect app message for any scenario. + *is_app_message = NV_FALSE; + + // Record the message in the last exchange transcript. + lastExchangeSizeLeft = SPDM_MAX_EXCHANGE_BUFFER_SIZE - g_pSpdm->lastExchangeSize; + if (*message_size > lastExchangeSizeLeft || SPDM_MAX_EXCHANGE_BUFFER_SIZE < g_pSpdm->lastExchangeSize) + { + return LIBSPDM_STATUS_INVALID_PARAMETER; + } + + portMemCopy((NvU8 *)g_pSpdm->pLastExchange + g_pSpdm->lastExchangeSize, + lastExchangeSizeLeft, *message, *message_size); + g_pSpdm->lastExchangeSize += *message_size; + + return LIBSPDM_STATUS_SUCCESS; +} + +/*! + * Static function libspdm uses as hook to RM<->GSP transport layer. + * Sends SPDM request message to GSP, and stores received response to buffer. + * Response buffer must be freed by corresponding _spdmReceiveMessageGsp(). + */ +libspdm_return_t +_spdmSendMessageGsp +( + void *spdm_context, + size_t message_size, + const void *message, + uint64_t timeout +) +{ + NvU8 *pRequest = NULL; + NvU32 requestSize = 0; + NV_STATUS nvStatus = NV_OK; + libspdm_return_t spdmStatus = LIBSPDM_STATUS_SUCCESS; + SPDM_GSP_IO_CONTEXT *pIOContext = NULL; + + // Check libspdm parameters. + if (message_size == 0 || message == NULL) + { + return LIBSPDM_STATUS_INVALID_PARAMETER; + } + + if (g_pGpu == NULL || g_pSpdm == NULL || g_pSpdm->pDeviceIOContext == NULL) + { + return LIBSPDM_STATUS_INVALID_STATE_LOCAL; + } + + pIOContext = (SPDM_GSP_IO_CONTEXT *)g_pSpdm->pDeviceIOContext; + + // Initialize space for SPDM request and response buffers. + requestSize = message_size; + pRequest = (NvU8 *)portMemAllocNonPaged(requestSize); + pIOContext->responseSize = LIBSPDM_MAX_MESSAGE_BUFFER_SIZE; + pIOContext->pResponse = (NvU8 *)portMemAllocNonPaged(pIOContext->responseSize); + + if (pRequest == NULL || pIOContext->pResponse == NULL) + { + spdmStatus = LIBSPDM_STATUS_BUFFER_FULL; + goto ErrorExit; + } + + portMemSet(pRequest, 0, requestSize); + portMemSet(pIOContext->pResponse, 0, pIOContext->responseSize); + portMemCopy(pRequest, requestSize, message, message_size); + + nvStatus = spdmMessageProcess_HAL(g_pGpu, g_pSpdm, + pRequest, requestSize, + pIOContext->pResponse, + &pIOContext->responseSize); + +ErrorExit: + + portMemFree(pRequest); + if (spdmStatus != LIBSPDM_STATUS_SUCCESS || nvStatus != NV_OK) + { + portMemFree(pIOContext->pResponse); + pIOContext->pResponse = NULL; + pIOContext->responseSize = 0; + spdmStatus = LIBSPDM_STATUS_SEND_FAIL; + } + + return spdmStatus; +} + +/*! + * Static function libspdm uses as hook to RM<->GSP transport layer. + * Copies stored response message back to libspdm buffer. Cannot be retried, + * as must free response message regardless of success or failure. + */ +libspdm_return_t +_spdmReceiveMessageGsp +( + void *spdm_context, + size_t *message_size, + void **message, + uint64_t timeout +) +{ + libspdm_return_t spdmStatus = LIBSPDM_STATUS_SUCCESS; + SPDM_GSP_IO_CONTEXT *pIOContext = NULL; + + // Check libspdm parameters. + if (message_size == NULL || message == NULL || *message == NULL) + { + return LIBSPDM_STATUS_INVALID_PARAMETER; + } + + if (g_pGpu == NULL || g_pSpdm == NULL || g_pSpdm->pDeviceIOContext == NULL) + { + return LIBSPDM_STATUS_INVALID_STATE_LOCAL; + } + + // Basic validation to ensure we have a real response. + pIOContext = (SPDM_GSP_IO_CONTEXT *)g_pSpdm->pDeviceIOContext; + if (pIOContext->pResponse == NULL || pIOContext->responseSize == 0) + { + spdmStatus = LIBSPDM_STATUS_RECEIVE_FAIL; + goto ErrorExit; + } + + if (pIOContext->responseSize > *message_size) + { + spdmStatus = LIBSPDM_STATUS_BUFFER_TOO_SMALL; + goto ErrorExit; + } + + portMemCopy(*message, *message_size, pIOContext->pResponse, pIOContext->responseSize); + *message_size = pIOContext->responseSize; + +ErrorExit: + + // Invalidate response message, regardless of success or failure. + portMemFree(pIOContext->pResponse); + pIOContext->pResponse = NULL; + pIOContext->responseSize = 0; + + return spdmStatus; +} + +/*! +* Static function that sends the opaque data from RM to GSP. +*/ +NV_STATUS +_spdmSendInitRmDataCommand +( + OBJGPU *pGpu, + Spdm *pSpdm +) +{ + NV_STATUS status = NV_OK; + RMTIMEOUT timeout; + NV2080_CTRL_INTERNAL_SPDM_PARTITION_PARAMS params; + + if (pGpu == NULL || pSpdm == NULL) + { + return NV_ERR_INVALID_ARGUMENT; + } + + portMemSet(¶ms, 0, sizeof(params)); + params.cmd.cmdType = RM_GSP_SPDM_CMD_ID_CC_INIT_RM_DATA; + + gpuSetTimeout(pGpu, GPU_TIMEOUT_DEFAULT, &timeout, 0); + + status = spdmCtrlSpdmPartition(pGpu, ¶ms); + if (status != NV_OK) + { + return NV_ERR_FLCN_ERROR; + } + + // Perform basic validation of header returned, ensuring it matches expected values. + status = _spdmErrorCheck(¶ms.msg, pSpdm->guestId, pSpdm->endpointId, RM_GSP_SPDM_CMD_ID_CC_INIT_RM_DATA); + if (status != NV_OK) + { + NV_PRINTF(LEVEL_ERROR, "SPDM: _spdmErrorCheck() failed in INIT_RM_DATA command \n"); + DBG_BREAKPOINT(); + return status; + } + + return NV_OK; +} + +/* ------------------------ Public Functions ------------------------------- */ +/*! + * On Hopper, we use GSP as SPDM Responder. To initialize, we must allocate + * a surface for SPDM communication, send initialization command to GSP-SPDM + * partition, and register all transport-layer functionality with library. + */ +NV_STATUS +spdmDeviceInit_GH100 +( + OBJGPU *pGpu, + Spdm *pSpdm +) +{ + NV_STATUS status = NV_OK; + NV_STATUS descHdrStatus = NV_OK; + SPDM_GSP_IO_CONTEXT *pIOContext = NULL; + RmPhysAddr physAddr = 0; + NvU64 memDescFlags = MEMDESC_FLAGS_NONE; + NV2080_CTRL_INTERNAL_SPDM_PARTITION_PARAMS params; + RMTIMEOUT timeout; + TRANSFER_SURFACE surf = {0}; + MemoryManager *pMemoryManager = NULL; + + if (pGpu == NULL || pSpdm == NULL || pSpdm->pLibspdmContext == NULL) + { + return NV_ERR_INVALID_ARGUMENT; + } + + g_pGpu = pGpu; + g_pSpdm = pSpdm; + + // Register transport layer functionality with library. + libspdm_register_transport_layer_func(pSpdm->pLibspdmContext, + _spdmEncodeMessageGsp, + _spdmDecodeMessageGsp, + _spdmGetTransportHeaderSizeGsp); + + libspdm_register_device_io_func(pSpdm->pLibspdmContext, + _spdmSendMessageGsp, + _spdmReceiveMessageGsp); + + + pSpdm->pDeviceIOContext = portMemAllocNonPaged(sizeof(SPDM_GSP_IO_CONTEXT)); + if (pSpdm->pDeviceIOContext == NULL) + { + return NV_ERR_INSUFFICIENT_RESOURCES; + } + + pIOContext = (SPDM_GSP_IO_CONTEXT *)pSpdm->pDeviceIOContext; + portMemSet(pIOContext, 0, sizeof(SPDM_GSP_IO_CONTEXT)); + + // + // Set default values for IO context. + // TODO CONFCOMP-1463: Generalize command structures. + // + pIOContext->surfaceSizeInByte = NV_SPDM_RM_SURFACE_SIZE_IN_BYTE; + pIOContext->descHdrSizeInByte = NV_SPDM_DESC_HEADER_SIZE_IN_BYTE; + pIOContext->rmBufferSizeInByte = NV_RM_BUFFER_SIZE_IN_BYTE; + pIOContext->alignSize = SPDM_MESSAGE_BUFFER_ADDRESS_ALIGNMENT; + pIOContext->addrSpace = NV_SPDM_DMA_ADDR_SPACE_DEFAULT; + pIOContext->regionId = NV_SPDM_DMA_REGION_ID_DEFAULT; + pIOContext->pResponse = NULL; + pIOContext->responseSize = 0; + + // Be sure to allocate in unprotected memory, so GPU can read. + memDescFlags = MEMDESC_FLAGS_ALLOC_IN_UNPROTECTED_MEMORY; + + // Create memory descriptor. + status = memdescCreate(&pIOContext->pMemDesc, pGpu, + pIOContext->surfaceSizeInByte, + pIOContext->alignSize, + NV_TRUE, pIOContext->addrSpace, + NV_MEMORY_UNCACHED, + memDescFlags); + if (status != NV_OK || pIOContext->pMemDesc == NULL) + { + portMemFree(pIOContext); + pSpdm->pDeviceIOContext = NULL; + return NV_ERR_INSUFFICIENT_RESOURCES; + } + + status = memdescAlloc(pIOContext->pMemDesc); + if (status != NV_OK) + { + NV_PRINTF(LEVEL_ERROR, "SPDM: Cannot allocate SPDM surface!\n"); + memdescDestroy(pIOContext->pMemDesc); + portMemFree(pIOContext); + pSpdm->pDeviceIOContext = NULL; + return status; + } + + // Physical mode with GSP. + if ((pIOContext->addrSpace == ADDR_SYSMEM) || (pIOContext->addrSpace == ADDR_FBMEM)) + { + physAddr = memdescGetPhysAddr(pIOContext->pMemDesc, AT_GPU, 0); + } + else + { + NV_PRINTF(LEVEL_ERROR, "SPDM: Message surface addr space is invalid: (0x%x)\n", + pIOContext->addrSpace); + status = NV_ERR_INSUFFICIENT_RESOURCES; + goto ErrorExit; + } + + SLI_LOOP_START(SLI_LOOP_FLAGS_BC_ONLY) + + pMemoryManager = GPU_GET_MEMORY_MANAGER(pGpu); + + surf.pMemDesc = pIOContext->pMemDesc; + surf.offset = 0; + + // Scrub surface + NV_ASSERT_OK_OR_GOTO(status, + memmgrMemSet(pMemoryManager, &surf, 0, pIOContext->surfaceSizeInByte, + TRANSFER_FLAGS_NONE), + ErrorExit); + + pIOContext->dmaAddr = (NvU64)physAddr; + + // Prepare GSP-CMD and send to GSP-SPDM partition. + portMemSet(¶ms, 0, sizeof(params)); + + params.cmd.cmdType = RM_GSP_SPDM_CMD_ID_CC_INIT; + + RM_GSP_SPDM_CMD_CC_INIT *pCcInit = ¶ms.cmd.ccInit; + RM_GSP_SPDM_CC_INIT_CTX *pCcInitCtx = &pCcInit->ccInitCtx; + + // Ucode is responsible for setting DMA index. + pCcInitCtx->guestId = pSpdm->guestId; + NvU64_ALIGN32_PACK(&pCcInitCtx->dmaAddr, &pIOContext->dmaAddr); + + gpuSetTimeout(pGpu, GPU_TIMEOUT_DEFAULT, &timeout, 0); + + status = spdmCtrlSpdmPartition(pGpu, ¶ms); + + // + // If successful, copy status received from GSP-SPDM. In case of failure, we will + // unmap memory first before breaking to error handling routine. + // + if (status == NV_OK) + { + descHdrStatus = _spdmErrorCheck(¶ms.msg, pSpdm->guestId, pSpdm->endpointId, RM_GSP_SPDM_CMD_ID_CC_INIT); + } + + // Now we check for command success. + if (status != NV_OK || descHdrStatus != NV_OK) + { + NV_PRINTF(LEVEL_ERROR, "SPDM: gspCommandPostBlocking() failed in INIT command, status = 0x%x, descHdrStatus = 0x%x \n", + status, descHdrStatus); + DBG_BREAKPOINT(); + + status = (status == NV_OK ? descHdrStatus : status); + goto ErrorExit; + } + + // If successful, save returned endpoint ID to context. + pSpdm->endpointId = params.msg.endpointId; + + // Sending Rm data for opaque data to GSP. + status = _spdmSendInitRmDataCommand(pGpu, pSpdm); + + SLI_LOOP_END + +ErrorExit: + if (status != NV_OK) + { + NV_PRINTF(LEVEL_ERROR, "SPDM: INIT command failed: status 0x%x\n", status); + _spdmReleaseSurfaceGsp(pSpdm); + } + + return status; +} + + +/*! + * To deinitialize the GSP SPDM Responder, we need to release the surface for + * SPDM communcation, and send deinitialization command to GSP-SPDM. + */ +NV_STATUS +spdmDeviceDeinit_GH100 +( + OBJGPU *pGpu, + Spdm *pSpdm, + NvBool bForceClear +) +{ + NV_STATUS status = NV_OK; + NV_STATUS descHdrStatus = NV_OK; + RM_GSP_SPDM_CMD_CC_DEINIT *pCcDeinit = NULL; + RM_GSP_SPDM_CC_DEINIT_CTX *pCcDeinitCtx = NULL; + NV2080_CTRL_INTERNAL_SPDM_PARTITION_PARAMS params; + RMTIMEOUT timeout; + + if (pGpu == NULL || pSpdm == NULL || pSpdm->pDeviceIOContext == NULL) + { + return NV_ERR_INVALID_ARGUMENT; + } + + SLI_LOOP_START(SLI_LOOP_FLAGS_BC_ONLY) + + // Prepare GSP-CMD and send to GSP-SPDM partition. + portMemSet(¶ms, 0, sizeof(params)); + + params.cmd.cmdType = RM_GSP_SPDM_CMD_ID_CC_DEINIT; + + // TODO CONFCOMP-1463: Generalize command structures. + pCcDeinit = ¶ms.cmd.ccDeinit; + pCcDeinitCtx = &pCcDeinit->ccDeinitCtx; + pCcDeinitCtx->guestId = pSpdm->guestId; + pCcDeinitCtx->endpointId = pSpdm->endpointId; + + if (bForceClear) + { + pCcDeinitCtx->flags |= DEINIT_FLAGS_FORCE_CLEAR; + } + + gpuSetTimeout(pGpu, GPU_TIMEOUT_DEFAULT, &timeout, 0); + + status = spdmCtrlSpdmPartition(pGpu, ¶ms); + + // + // If successful, copy status received from GSP-SPDM. In case of failure, we will + // unmap memory first before breaking to error handling routine. + // + if (status == NV_OK) + { + descHdrStatus = _spdmErrorCheck(¶ms.msg, pSpdm->guestId, pSpdm->endpointId, RM_GSP_SPDM_CMD_ID_CC_DEINIT); + } + + SLI_LOOP_END + + if (status != NV_OK || descHdrStatus != NV_OK) + { + NV_PRINTF(LEVEL_ERROR, "SPDM: DEINIT command failed: status = 0x%x, descHdrStatus = 0x%x\n", + status, descHdrStatus); + DBG_BREAKPOINT(); + + status = (status == NV_OK ? descHdrStatus : status); + goto ErrorExit; + } + + // Only release surface on success, as we may want to retry deinit on failure. + _spdmReleaseSurfaceGsp(pSpdm); + +ErrorExit: + + if (status != NV_OK) + { + NV_PRINTF(LEVEL_ERROR, "SPDM: DEINIT command failed: status 0x%x\n", status); + } + + return status; +} + +NV_STATUS +spdmMessageProcess_GH100 +( + OBJGPU *pGpu, + Spdm *pSpdm, + NvU8 *pRequest, + NvU32 requestSize, + NvU8 *pResponse, + NvU32 *pResponseSize +) +{ + NV_STATUS status = NV_OK; + NV_STATUS descHdrStatus = NV_OK; + NvU8 *pMapMem = NULL; + NvU32 transportResponseSize = 0; + SPDM_GSP_IO_CONTEXT *pIOContext = NULL; + RM_GSP_SPDM_CMD_CC_CTRL *pCcCtrl = NULL; + RM_GSP_SPDM_CC_CTRL_CTX *pCcCtrlCtx = NULL; + NV2080_CTRL_INTERNAL_SPDM_PARTITION_PARAMS params; + RMTIMEOUT timeout; + MemoryManager *pMemoryManager = NULL; + TRANSFER_SURFACE surf = {0}; + NvBool bFreeShadowBuf = NV_FALSE; + + if (pGpu == NULL || pSpdm == NULL || pSpdm->pDeviceIOContext == NULL || + pRequest == NULL || pResponse == NULL || pResponseSize == NULL) + { + return NV_ERR_INVALID_ARGUMENT; + } + + pIOContext = (SPDM_GSP_IO_CONTEXT *)pSpdm->pDeviceIOContext; + if (requestSize > pIOContext->rmBufferSizeInByte) + { + return NV_ERR_INSUFFICIENT_RESOURCES; + } + + // + // Map memory for CPU access to copy SPDM message - ensure we unmap + // before returning for any reason. + // + SLI_LOOP_START(SLI_LOOP_FLAGS_BC_ONLY) + + pMemoryManager = GPU_GET_MEMORY_MANAGER(pGpu); + + pMapMem = memmgrMemDescBeginTransfer(pMemoryManager, pIOContext->pMemDesc, + TRANSFER_FLAGS_SHADOW_ALLOC); + if (pMapMem == NULL) + { + status = NV_ERR_INSUFFICIENT_RESOURCES; + goto ErrorExit; + } + + // Copy entire SPDM message to shared memory. + portMemCopy(pMapMem, requestSize, pRequest, requestSize); + + memmgrMemDescEndTransfer(pMemoryManager, pIOContext->pMemDesc, + TRANSFER_FLAGS_SHADOW_ALLOC); + + // Prepare GSP-CMD and send to GSP-SPDM partition + portMemSet(¶ms, 0, sizeof(params)); + params.cmd.cmdType = RM_GSP_SPDM_CMD_ID_CC_CTRL; + pCcCtrl = ¶ms.cmd.ccCtrl; + pCcCtrlCtx = &pCcCtrl->ccCtrlCtx; + pCcCtrlCtx->version = NV_SPDM_DESC_HEADER_VERSION_CURRENT; + pCcCtrlCtx->guestId = pSpdm->guestId; + pCcCtrlCtx->endpointId = pSpdm->endpointId; + + gpuSetTimeout(pGpu, GPU_TIMEOUT_DEFAULT, &timeout, 0); + + status = spdmCtrlSpdmPartition(pGpu, ¶ms); + + // Retrieve descriptor header and response message, checking header to ensure valid response. + if (status == NV_OK) + { + surf.pMemDesc = pIOContext->pMemDesc; + surf.offset = 0; + + pMapMem = portMemAllocNonPaged(pIOContext->surfaceSizeInByte); + + if (pMapMem == NULL) + { + status = NV_ERR_INSUFFICIENT_RESOURCES; + goto ErrorExit; + } + + bFreeShadowBuf = NV_TRUE; + + NV_ASSERT_OK_OR_GOTO(status, + memmgrMemRead(pMemoryManager, &surf, pMapMem, + pIOContext->surfaceSizeInByte, + TRANSFER_FLAGS_NONE), + ErrorExit); + + descHdrStatus = _spdmErrorCheck(¶ms.msg, pSpdm->guestId, pSpdm->endpointId, RM_GSP_SPDM_CMD_ID_CC_CTRL); + } + + if (status != NV_OK || descHdrStatus != NV_OK) + { + NV_PRINTF(LEVEL_ERROR, "SPDM: Process message failed: status = 0x%x, descHdrStatus = 0x%x\n", + status, descHdrStatus); + DBG_BREAKPOINT(); + + status = (status == NV_OK ? descHdrStatus : status); + goto ErrorExit; + } + + transportResponseSize = (((NV_SPDM_DESC_HEADER *)pMapMem)->msgSizeByte + NV_SPDM_DESC_HEADER_SIZE_IN_BYTE); + + if (transportResponseSize > *pResponseSize) + { + status = NV_ERR_INSUFFICIENT_RESOURCES; + NV_PRINTF(LEVEL_ERROR, "SPDM: Error: transportResponseSize = 0x%x, responseSize = 0x%x\n", + transportResponseSize, *pResponseSize); + DBG_BREAKPOINT(); + goto ErrorExit; + } + + portMemCopy(pResponse, *pResponseSize, pMapMem, transportResponseSize); + *pResponseSize = transportResponseSize; + + SLI_LOOP_END + +ErrorExit: + if (bFreeShadowBuf) + { + portMemFree(pMapMem); + bFreeShadowBuf = NV_FALSE; + } + return status; +} + +NV_STATUS +spdmDeviceSecuredSessionSupported_GH100 +( + OBJGPU *pGpu, + Spdm *pSpdm +) +{ + + return NV_OK; +} + +NV_STATUS +spdmCheckConnection_GH100 +( + OBJGPU *pGpu, + Spdm *pSpdm +) +{ + void *pContext = NULL; + uint32_t expectedFlags = 0; + uint32_t capabilitiesFlags = 0; + libspdm_return_t ret = LIBSPDM_STATUS_SUCCESS; + libspdm_data_parameter_t dataParam; + libspdm_connection_state_t connectionState; + uint8_t ctExponent; + size_t dataSize; + NvU32 i; + NvU32 algoCheckCount; + NvU32 actualAlgo; + PSPDM_ALGO_CHECK_ENTRY pCheckEntry; + + if (pGpu == NULL || pSpdm == NULL) + { + return NV_ERR_INVALID_ARGUMENT; + } + + // Ensure we have at least negotiated the parameters of the SPDM connection. + pContext = (void *)pSpdm->pLibspdmContext; + + if (pContext == NULL) + { + return NV_ERR_NOT_READY; + } + + dataParam.location = LIBSPDM_DATA_LOCATION_CONNECTION; + dataSize = sizeof(connectionState); + ret = libspdm_get_data(pContext, LIBSPDM_DATA_CONNECTION_STATE, + &dataParam, &connectionState, &dataSize); + + if (ret != LIBSPDM_STATUS_SUCCESS || connectionState < LIBSPDM_CONNECTION_STATE_NEGOTIATED) + { + return NV_ERR_NOT_READY; + } + + // Check version matches expected. + if (libspdm_get_connection_version(pContext) != SPDM_MESSAGE_VERSION_11) + { + return NV_ERR_INVALID_STATE; + } + + dataSize = sizeof(ctExponent); + ret = libspdm_get_data(pContext, LIBSPDM_DATA_CAPABILITY_CT_EXPONENT, + &dataParam, &ctExponent, &dataSize); + + if (ret != LIBSPDM_STATUS_SUCCESS || ctExponent != SPDM_CAPABILITIES_CT_EXPONENT_MAX) + { + NV_PRINTF(LEVEL_ERROR, "SPDM: Invalid Responder CT exponent.\n"); + return NV_ERR_INVALID_STATE; + } + + // Check all capabilities match expected. + expectedFlags = SPDM_CAPABILITIES_FLAGS_GH100; + + dataSize = sizeof(capabilitiesFlags); + ret = libspdm_get_data(pContext, LIBSPDM_DATA_CAPABILITY_FLAGS, + &dataParam, &capabilitiesFlags, &dataSize); + + if (ret != LIBSPDM_STATUS_SUCCESS || capabilitiesFlags != expectedFlags) + { + NV_PRINTF(LEVEL_ERROR, "SPDM: Invalid Responder capabilities.\n"); + return NV_ERR_INVALID_STATE; + } + + // Check all crypto algorithms match expected. + algoCheckCount = sizeof(g_SpdmAlgoCheckTable_GH100)/sizeof(SPDM_ALGO_CHECK_ENTRY); + + for (i = 0; i < algoCheckCount; i++) + { + pCheckEntry = &g_SpdmAlgoCheckTable_GH100[i]; + + actualAlgo = 0; + dataSize = sizeof(actualAlgo); + ret = libspdm_get_data(pContext, pCheckEntry->dataType, + &dataParam, &actualAlgo, &dataSize); + + if (ret != LIBSPDM_STATUS_SUCCESS || actualAlgo != pCheckEntry->expectedAlgo) + { + NV_PRINTF(LEVEL_ERROR, "SPDM: Invalid crypto algorithms selected.\n"); + NV_PRINTF(LEVEL_ERROR, "SPDM: AlgoCheckCount 0x%0x, i is 0x%0x, status is 0x%0x.\n", (NvU32)algoCheckCount, (NvU32)i, (NvU32)ret); + NV_PRINTF(LEVEL_ERROR, "SPDM: Expected algo 0x%0x, actual algo 0x%0x\n", (NvU32)pCheckEntry->expectedAlgo, (NvU32)actualAlgo); + return NV_ERR_INVALID_STATE; + } + } + + return NV_OK; +} + +NV_STATUS +spdmGetAttestationReport_GH100 +( + OBJGPU *pGpu, + Spdm *pSpdm, + NvU8 *pNonce, + void *pAttestationReport, + NvU32 *pAttestationReportSize, + NvBool *pbIsCecAttestationReportPresent, + void *pCecAttestationReport, + NvU32 *pCecAttestationReportSize +) +{ + NV_STATUS status = NV_OK; + uint8_t numBlocks = 0; + uint32_t measurementSize = 0; + void *pMeasurementBuffer = NULL; + + if (pGpu == NULL || pSpdm == NULL) + { + return NV_ERR_INVALID_ARGUMENT; + } + + // Ensure we have a valid session, and have retrieved the certificates. + if (pSpdm->pLibspdmContext == NULL || pSpdm->sessionId == INVALID_SESSION_ID) + { + return NV_ERR_NOT_READY; + } + + // Retrieve Attestation Report, if requested. + if (pAttestationReport != NULL && pAttestationReportSize != NULL) + { + // Guarantees the latest transcript will fit inside the Attestation Report buffer. + if (*pAttestationReportSize < SPDM_MAX_EXCHANGE_BUFFER_SIZE) + { + return NV_ERR_BUFFER_TOO_SMALL; + } + + numBlocks = LIBSPDM_MAX_MEASUREMENT_BLOCK_COUNT; + + // + // Use Attestation Report buffer temporarily to store measurements, we will replace + // with the full Attestation Report from message transcripts. + // + pMeasurementBuffer = pAttestationReport; + measurementSize = *pAttestationReportSize; + + // Request the Attestation Report using the provided nonce, signed by the AK cert. + CHECK_SPDM_STATUS(libspdm_get_measurement_ex(pSpdm->pLibspdmContext, &pSpdm->sessionId, + SPDM_GET_MEASUREMENTS_REQUEST_ATTRIBUTES_GENERATE_SIGNATURE, + SPDM_GET_MEASUREMENTS_REQUEST_MEASUREMENT_OPERATION_ALL_MEASUREMENTS, + SPDM_CERT_DEFAULT_SLOT_ID, NULL, &numBlocks, + &measurementSize, pMeasurementBuffer, pNonce, NULL, NULL)); + + if (!nvspdm_check_and_clear_libspdm_assert()) + { + // libspdm detects assert/error in GET_MEASUREMENT process, need to return error. + NV_PRINTF(LEVEL_ERROR, "SPDM: spdmCheckAndClearLibspdmAssert() failed \n"); + DBG_BREAKPOINT(); + + return NV_ERR_INVALID_STATE; + } + + // + // Last exchange buffer will hold Attestation Report, which is comprised of + // the GET_MEASUREMENTS request concatenated with the MEASUREMENTS response. + // By definition, must be larger than the measurements written above. + // + portMemCopy(pAttestationReport, *pAttestationReportSize, + pSpdm->pLastExchange, pSpdm->lastExchangeSize); + *pAttestationReportSize = pSpdm->lastExchangeSize; + } + + // Retrieve CEC Attestation Report, if requested. + if (pbIsCecAttestationReportPresent != NULL) + { + *pbIsCecAttestationReportPresent = NV_FALSE; + } + +ErrorExit: + + return status; +} diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/kernel/gpu/spdm/arch/hopper/spdm_module.c nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/kernel/gpu/spdm/arch/hopper/spdm_module.c --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/kernel/gpu/spdm/arch/hopper/spdm_module.c 1970-01-01 00:00:00.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/kernel/gpu/spdm/arch/hopper/spdm_module.c 2024-03-05 22:13:49.000000000 +0000 @@ -0,0 +1,87 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2022-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +/*! + * Provides the implementation for SPDM module that interacts between RM and SPDM. + */ +/* ------------------------------ Includes ---------------------------------- */ +#include "gpu/spdm/spdm.h" +#include "gpu/conf_compute/conf_compute.h" +#include "core/locks.h" +#include "ctrl/ctrl2080/ctrl2080spdm.h" +#include "rmapi/client_resource.h" +#include "gpu/conf_compute/ccsl.h" +#include "gpu/conf_compute/conf_compute.h" +/* ------------------------- Macros and Defines ----------------------------- */ + +/* ------------------------- Static Functions ------------------------------ */ + +/* ------------------------- Public Functions ------------------------------ */ + +/*! + * @brief spdmCtrlSpdmPartition + * Common function used to call gspCommandPostBlocking based on the platform on which it runs (i.e. vGPU, GSP-RM, Monolithic). + * + * @param[in] pGpu : OBJGPU Pointer + * @param[in] pSpdmPartitionParams : SPDM RPC structure pointer + */ +NV_STATUS spdmCtrlSpdmPartition +( + OBJGPU *pGpu, + NV2080_CTRL_INTERNAL_SPDM_PARTITION_PARAMS *pSpdmPartitionParams +) +{ + NV_STATUS status = NV_OK; + + LOCK_ASSERT_AND_RETURN(rmapiLockIsOwner() && rmGpuLockIsOwner()); + + if (IS_VIRTUAL(pGpu)) + { + // The control call currently doesn't support the vGPU environment, therefore return NV_ERR_NOT_SUPPORTED. + return NV_ERR_NOT_SUPPORTED; + } + else if (IS_GSP_CLIENT(pGpu)) + { + RM_API *pRmApi = GPU_GET_PHYSICAL_RMAPI(pGpu); + + // Calls the subdeviceCtrlCmdSpdmPartition_IMPL control call in Physical RM mode. + status = pRmApi->Control(pRmApi, + pGpu->hInternalClient, + pGpu->hInternalSubdevice, + NV2080_CTRL_INTERNAL_SPDM_PARTITION, + pSpdmPartitionParams, + sizeof(NV2080_CTRL_INTERNAL_SPDM_PARTITION_PARAMS)); + } + else + { + return NV_ERR_NOT_SUPPORTED; + } + + if (status != NV_OK) + { + NV_PRINTF(LEVEL_ERROR, "spdmCtrlSpdmPartition failed with error 0x%0x\n", status); + } + + return status; +} + diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/kernel/gpu/spdm/spdm.c nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/kernel/gpu/spdm/spdm.c --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/kernel/gpu/spdm/spdm.c 1970-01-01 00:00:00.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/kernel/gpu/spdm/spdm.c 2024-03-05 22:13:49.000000000 +0000 @@ -0,0 +1,538 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2022-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +/***************************************************************************\ + * * + * SPDM Object Module * + * * + \**************************************************************************/ + +/* ------------------------ Includes --------------------------------------- */ +#include "gpu/spdm/spdm.h" +#include "spdm/rmspdmtransport.h" +#include "spdm/rmspdmvendordef.h" +#include "gpu/gpu.h" +#include "gpu/gpu_resource.h" + +// +// Libspdm only supported on certain builds, +// take note if you are copying header elsewhere. +// +#include "gpu/spdm/libspdm_includes.h" + +/* ------------------------ Static Function Prototypes --------------------- */ +static void _spdmClearContext(Spdm *pSpdm); +libspdm_return_t _spdmAcquireTransportBuffer(void *context, size_t *max_msg_size, void **msg_buf_ptr); +void _spdmReleaseTransportBuffer(void *context, const void *msg_buf_ptr); +bool _spdmVerifyCertChain(void *spdm_context, uint8_t slot_id, size_t cert_chain_size, + const void *cert_chain, const void **trust_anchor, size_t *trust_anchor_size); + +/* ------------------------ Static Functions ------------------------------- */ +/* + * Helper to clear and free any SPDM object context. + */ +void +_spdmClearContext +( + Spdm *pSpdm +) +{ + NvU32 index = 0; + + if (pSpdm == NULL) + { + return; + } + + // + // If we haven't deinitialized session, not much we can do now. + // Make best effort to free any allocated Requester context, + // ensuring we scrub the libspdm context. + // + if (pSpdm->pLibspdmContext != NULL) + { + + libspdm_reset_message_b(pSpdm->pLibspdmContext); + libspdm_reset_message_c(pSpdm->pLibspdmContext); + libspdm_reset_message_mut_b(pSpdm->pLibspdmContext); + libspdm_reset_message_mut_c(pSpdm->pLibspdmContext); + + libspdm_reset_message_m(pSpdm->pLibspdmContext, NULL); + for (index = 0; index < LIBSPDM_MAX_SESSION_COUNT; index++) + { + libspdm_reset_message_m(pSpdm->pLibspdmContext, &(((libspdm_context_t *)pSpdm->pLibspdmContext)->session_info[index])); + } + + libspdm_deinit_context(pSpdm->pLibspdmContext); + libspdm_reset_context(pSpdm->pLibspdmContext); + portMemSet((NvU8 *)pSpdm->pLibspdmContext, 0, pSpdm->libspdmContextSize); + } + + if (pSpdm->pLibspdmScratch != NULL) + { + portMemSet((NvU8 *)pSpdm->pLibspdmScratch, 0, pSpdm->libspdmScratchSize); + } + + // portMemFree handles NULL pointers gracefully. + portMemFree(pSpdm->pLibspdmContext); + portMemFree(pSpdm->pLibspdmScratch); + portMemFree(pSpdm->pAttestationCertChain); + portMemFree(pSpdm->pDeviceIOContext); + portMemFree(pSpdm->pLastExchange); + + pSpdm->pLibspdmContext = NULL; + pSpdm->pLibspdmScratch = NULL; + pSpdm->pAttestationCertChain = NULL; + pSpdm->pDeviceIOContext = NULL; + pSpdm->pLastExchange = NULL; + + pSpdm->libspdmContextSize = 0; + pSpdm->libspdmScratchSize = 0; + pSpdm->attestationCertChainSize = 0; + pSpdm->lastExchangeSize = 0; + + pSpdm->guestId = 0; + pSpdm->sessionId = INVALID_SESSION_ID; + pSpdm->endpointId = 0; +} + +/* + * Transport layer helpers for send/receive message buffers. + */ +libspdm_return_t +_spdmAcquireTransportBuffer +( + void *context, + size_t *max_msg_size, + void **msg_buf_ptr +) +{ + if (context == NULL || max_msg_size == NULL || msg_buf_ptr == NULL) + { + return LIBSPDM_STATUS_INVALID_PARAMETER; + } + + *msg_buf_ptr = portMemAllocNonPaged(LIBSPDM_MAX_MESSAGE_BUFFER_SIZE); + if (*msg_buf_ptr == NULL) + { + return LIBSPDM_STATUS_BUFFER_FULL; + } + + *max_msg_size = LIBSPDM_MAX_MESSAGE_BUFFER_SIZE; + + return LIBSPDM_STATUS_SUCCESS; +} + +void +_spdmReleaseTransportBuffer +( + void *context, + const void *msg_buf_ptr +) +{ + portMemFree((void *)msg_buf_ptr); +} + +bool +_spdmVerifyCertChain +( + void *spdm_context, + uint8_t slot_id, + size_t cert_chain_size, + const void *cert_chain, + const void **trust_anchor, + size_t *trust_anchor_size +) +{ + return NV_TRUE; +} + +/* ------------------------ Public Functions ------------------------------- */ +/*! + * Constructor + */ +NV_STATUS +spdmConstruct_IMPL +( + Spdm *pSpdm +) +{ + + if (pSpdm == NULL) + { + return NV_ERR_INVALID_ARGUMENT; + } + + pSpdm->pLibspdmContext = NULL; + pSpdm->pLibspdmScratch = NULL; + pSpdm->pAttestationCertChain = NULL; + pSpdm->pDeviceIOContext = NULL; + pSpdm->pLastExchange = NULL; + + pSpdm->libspdmContextSize = 0; + pSpdm->libspdmScratchSize = 0; + pSpdm->attestationCertChainSize = 0; + pSpdm->lastExchangeSize = 0; + + pSpdm->guestId = 0; + pSpdm->sessionId = INVALID_SESSION_ID; + pSpdm->endpointId = 0; + + pSpdm->bExportSecretCleared = NV_FALSE; + + return NV_OK; +} + +/*! + * Destructor + */ +void +spdmDestruct_IMPL +( + Spdm * pSpdm +) +{ + _spdmClearContext(pSpdm); +} + +NV_STATUS +spdmContextInit_IMPL +( + OBJGPU *pGpu, + Spdm *pSpdm +) +{ + NV_STATUS status = NV_OK; + libspdm_data_parameter_t parameter; + uint8_t ctExponent; + uint32_t capFlags; + uint8_t measSpec; + uint32_t baseAsymAlgo; + uint32_t baseHashAlgo; + uint16_t dheGroup; + uint16_t aeadSuite; + uint16_t keySched; + + if (pGpu == NULL || pSpdm == NULL) + { + return NV_ERR_INVALID_ARGUMENT; + } + + // Allocate and initialize all required memory for context and certificates. + pSpdm->libspdmContextSize = libspdm_get_context_size(); + pSpdm->pLibspdmContext = portMemAllocNonPaged(pSpdm->libspdmContextSize); + + if (pSpdm->libspdmContextSize == 0 || pSpdm->pLibspdmContext == NULL) + { + status = NV_ERR_NO_MEMORY; + goto ErrorExit; + } + + portMemSet(pSpdm->pLibspdmContext, 0, pSpdm->libspdmContextSize); + libspdm_init_context(pSpdm->pLibspdmContext); + + // Allocate scratch space required for libspdm processing. + pSpdm->libspdmScratchSize = libspdm_get_sizeof_required_scratch_buffer(pSpdm->pLibspdmContext); + pSpdm->pLibspdmScratch = portMemAllocNonPaged(pSpdm->libspdmScratchSize); + + if (pSpdm->libspdmScratchSize == 0 || pSpdm->pLibspdmScratch == NULL) + { + status = NV_ERR_NO_MEMORY; + goto ErrorExit; + } + + portMemSet(pSpdm->pLibspdmScratch, 0, pSpdm->libspdmScratchSize); + libspdm_set_scratch_buffer(pSpdm->pLibspdmContext, pSpdm->pLibspdmScratch, + pSpdm->libspdmScratchSize); + + // Allocate message transcript recording buffer. + pSpdm->pLastExchange = portMemAllocNonPaged(SPDM_MAX_EXCHANGE_BUFFER_SIZE); + pSpdm->lastExchangeSize = 0; + + if (pSpdm->pLastExchange == NULL) + { + status = NV_ERR_NO_MEMORY; + goto ErrorExit; + } + + // + // Eventually, owner of Spdm object may want to set their own + // specific configuration. For now, hardcode the only supported configuration. + // + portMemSet(¶meter, 0, sizeof(parameter)); + parameter.location = LIBSPDM_DATA_LOCATION_LOCAL; + + // Requester will not check Responder's timing, set to maximum value. + ctExponent = SPDM_CAPABILITIES_CT_EXPONENT_MAX; + CHECK_SPDM_STATUS(libspdm_set_data(pSpdm->pLibspdmContext, LIBSPDM_DATA_CAPABILITY_CT_EXPONENT, + ¶meter, &ctExponent, sizeof(ctExponent))); + + capFlags = SPDM_GET_CAPABILITIES_REQUEST_FLAGS_CERT_CAP | + SPDM_GET_CAPABILITIES_REQUEST_FLAGS_ENCRYPT_CAP | + SPDM_GET_CAPABILITIES_REQUEST_FLAGS_MAC_CAP | + SPDM_GET_CAPABILITIES_REQUEST_FLAGS_KEY_EX_CAP | + SPDM_GET_CAPABILITIES_REQUEST_FLAGS_KEY_UPD_CAP; + CHECK_SPDM_STATUS(libspdm_set_data(pSpdm->pLibspdmContext, + LIBSPDM_DATA_CAPABILITY_FLAGS, ¶meter, + &capFlags, sizeof(capFlags))); + + measSpec = SPDM_MEASUREMENT_BLOCK_HEADER_SPECIFICATION_DMTF; + CHECK_SPDM_STATUS(libspdm_set_data(pSpdm->pLibspdmContext, + LIBSPDM_DATA_MEASUREMENT_SPEC, ¶meter, + &measSpec, sizeof(measSpec))); + + baseAsymAlgo = SPDM_ALGORITHMS_BASE_ASYM_ALGO_TPM_ALG_ECDSA_ECC_NIST_P384; + CHECK_SPDM_STATUS(libspdm_set_data(pSpdm->pLibspdmContext, LIBSPDM_DATA_BASE_ASYM_ALGO, + ¶meter, &baseAsymAlgo, + sizeof(baseAsymAlgo))); + + baseHashAlgo = SPDM_ALGORITHMS_BASE_HASH_ALGO_TPM_ALG_SHA_384; + CHECK_SPDM_STATUS(libspdm_set_data(pSpdm->pLibspdmContext, LIBSPDM_DATA_BASE_HASH_ALGO, + ¶meter, &baseHashAlgo, + sizeof(baseHashAlgo))); + + dheGroup = SPDM_ALGORITHMS_DHE_NAMED_GROUP_SECP_384_R1; + CHECK_SPDM_STATUS(libspdm_set_data(pSpdm->pLibspdmContext, LIBSPDM_DATA_DHE_NAME_GROUP, + ¶meter, &dheGroup, sizeof(dheGroup))); + + aeadSuite = SPDM_ALGORITHMS_AEAD_CIPHER_SUITE_AES_256_GCM; + CHECK_SPDM_STATUS(libspdm_set_data(pSpdm->pLibspdmContext, LIBSPDM_DATA_AEAD_CIPHER_SUITE, + ¶meter, &aeadSuite, sizeof(aeadSuite))); + + keySched = SPDM_ALGORITHMS_KEY_SCHEDULE_HMAC_HASH; + CHECK_SPDM_STATUS(libspdm_set_data(pSpdm->pLibspdmContext, LIBSPDM_DATA_KEY_SCHEDULE, + ¶meter, &keySched, sizeof(keySched))); + + pSpdm->guestId = 0x01; + + // + // Perform any device-specific initialization. spdmDeviceInit is also + // responsible for registering transport layer functions with libspdm. + // + status = spdmDeviceInit_HAL(pGpu, pSpdm); + if (status != NV_OK) + { + goto ErrorExit; + } + + libspdm_register_device_buffer_func(pSpdm->pLibspdmContext, + _spdmAcquireTransportBuffer, _spdmReleaseTransportBuffer, + _spdmAcquireTransportBuffer, _spdmReleaseTransportBuffer); + + // + // Verifier is responsible for verifying the certificate chain. To avoid concerns + // with libspdm compatibility, override certificate validation function with stub. + // + libspdm_register_verify_spdm_cert_chain_func(pSpdm->pLibspdmContext, _spdmVerifyCertChain); + +ErrorExit: + + // Clear all SPDM state on failure. + if (status != NV_OK) + { + _spdmClearContext(pSpdm); + } + + return status; +} + +NV_STATUS +spdmContextDeinit_IMPL +( + OBJGPU *pGpu, + Spdm *pSpdm, + NvBool bForceClear +) +{ + NV_STATUS status = NV_OK; + + if (pGpu == NULL || pSpdm == NULL) + { + return NV_ERR_INVALID_ARGUMENT; + } + + // If no session to end, just wipe state and return. + if (pSpdm->pLibspdmContext == NULL) + { + _spdmClearContext(pSpdm); + return NV_OK; + } + + // + // End the session by deinitializing the Responder. + // We don't send END_SESSION as Responder will handle teardown. + // + NV_PRINTF(LEVEL_INFO, "SPDM: Tearing down session.\n"); + status = spdmDeviceDeinit_HAL(pGpu, pSpdm, NV_TRUE); + + // Regardless of success or failure, clear any context. + _spdmClearContext(pSpdm); + + // We really shouldn't fail on deinitialization - ASSERT if we do. + NV_ASSERT_OK(status); + return status; +} + +NV_STATUS +spdmStart_IMPL +( + OBJGPU *pGpu, + Spdm *pSpdm +) +{ + NV_STATUS status = NV_OK; + + if (pGpu == NULL || pSpdm == NULL) + { + return NV_ERR_INVALID_ARGUMENT; + } + + if (pSpdm->pLibspdmContext == NULL) + { + return NV_ERR_NOT_READY; + } + + // Send GET_VERSION, GET_CAPABILITIES, and NEGOTIATE_ALGORITHMS to Responder. + NV_PRINTF(LEVEL_INFO, "SPDM: Starting new SPDM connection.\n"); + CHECK_SPDM_STATUS(libspdm_init_connection(pSpdm->pLibspdmContext, NV_FALSE)); + + if (!nvspdm_check_and_clear_libspdm_assert()) + { + NV_PRINTF(LEVEL_ERROR, "SPDM: libspdm_init_connection() assert hit !!!.\n"); + status = NV_ERR_GENERIC; + goto ErrorExit; + } + + // Ensure the connection attributes match expected. + status = spdmCheckConnection_HAL(pGpu, pSpdm); + if (status != NV_OK) + { + NV_PRINTF(LEVEL_ERROR, "SPDM: Connection attributes did not match expected!\n"); + goto ErrorExit; + } + + // Fetch the certificates from the responder and validate them + status = spdmGetCertificates_HAL(pGpu, pSpdm); + if (status != NV_OK) + { + NV_PRINTF(LEVEL_ERROR, "SPDM: Certificate retrieval failed!\n"); + goto ErrorExit; + } + + if (!nvspdm_check_and_clear_libspdm_assert()) + { + NV_PRINTF(LEVEL_ERROR, "SPDM: spdmGetCertificates_HAL() assert hit !!!.\n"); + status = NV_ERR_GENERIC; + goto ErrorExit; + } + + // + // Complete the SPDM handshake and start the secured session. + // Ensure we match type of sessionId parameter with what libspdm expects. + // + if (spdmDeviceSecuredSessionSupported_HAL(pGpu, pSpdm) == NV_OK) + { + NV_PRINTF(LEVEL_INFO, "SPDM: Attempting to establish SPDM session.\n"); + CHECK_SPDM_STATUS(libspdm_start_session(pSpdm->pLibspdmContext, NV_FALSE, + SPDM_KEY_EXCHANGE_REQUEST_NO_MEASUREMENT_SUMMARY_HASH, + SPDM_CERT_DEFAULT_SLOT_ID, 0, &pSpdm->sessionId, NULL, NULL)); + + + if (!nvspdm_check_and_clear_libspdm_assert()) + { + NV_PRINTF(LEVEL_ERROR, "SPDM: libspdm_start_session() assert hit !!!.\n"); + status = NV_ERR_GENERIC; + goto ErrorExit; + } + else + { + NV_PRINTF(LEVEL_INFO, "SPDM: Session establishment successful: sessionId 0x%x.\n", + pSpdm->sessionId); + } + } + +ErrorExit: + + // + // On error, set session as invalid. Don't need to reset context, since + // restarting SPDM exchange is valid scenario. Responder may not support. + // + if (status != NV_OK) + { + pSpdm->sessionId = INVALID_SESSION_ID; + NV_PRINTF(LEVEL_ERROR, "SPDM: Session establishment failed!\n"); + DBG_BREAKPOINT(); + } + + return status; +} + +NV_STATUS +spdmRetrieveExportSecret_IMPL +( + OBJGPU *pGpu, + Spdm *pSpdm, + NvU32 keySize, + NvU8 *pKeyOut +) +{ + size_t keySizeSizeT = 0; + libspdm_secured_message_context_t *pSessionContext = NULL; + + // Basic parameter validation. + if (pGpu == NULL || pSpdm == NULL || keySize == 0 || pKeyOut == NULL) + { + return NV_ERR_INVALID_ARGUMENT; + } + + // Ensure we are in valid state. Note that export master secret can only be retrieved once. + if (pSpdm->pLibspdmContext == NULL || pSpdm->sessionId == INVALID_SESSION_ID || + pSpdm->bExportSecretCleared) + { + return NV_ERR_NOT_READY; + } + + pSessionContext = + libspdm_get_secured_message_context_via_session_id(pSpdm->pLibspdmContext, pSpdm->sessionId); + if (pSessionContext == NULL) + { + return NV_ERR_INVALID_STATE; + } + + // + // Fetch the export master secret. + // Use temporary size variable to handle type differences and avoid overflow. + // + keySizeSizeT = keySize; + if (!libspdm_secured_message_export_master_secret(pSessionContext, pKeyOut, &keySizeSizeT)) + { + return NV_ERR_INVALID_STATE; + } + + // Clear the export master secret from SPDM memory. + libspdm_secured_message_clear_export_master_secret(pSessionContext); + pSpdm->bExportSecretCleared = NV_TRUE; + + return NV_OK; +} + diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/kernel/gpu/subdevice/generic_engine.c nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/kernel/gpu/subdevice/generic_engine.c --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/kernel/gpu/subdevice/generic_engine.c 2023-10-25 20:21:21.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/kernel/gpu/subdevice/generic_engine.c 2024-03-05 22:13:49.000000000 +0000 @@ -29,6 +29,7 @@ #include "rmapi/client.h" #include +#include NV_STATUS @@ -82,6 +83,15 @@ RS_RES_CONTROL_PARAMS_INTERNAL *pParams ) { + if (RES_GET_EXT_CLASS_ID(pGenericEngineApi) == GF100_SUBDEVICE_INFOROM) + { + OBJGPU *pGpu = GPU_RES_GET_GPU(pGenericEngineApi); + OBJINFOROM *pInforom = GPU_GET_INFOROM(pGpu); + if (!IS_GSP_CLIENT(pGpu) && pInforom == NULL) + { + return NV_ERR_NOT_SUPPORTED; + } + } return gpuresControl_IMPL(staticCast(pGenericEngineApi, GpuResource), pCallContext, pParams); diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/kernel/gpu/subdevice/subdevice.c nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/kernel/gpu/subdevice/subdevice.c --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/kernel/gpu/subdevice/subdevice.c 2023-10-25 20:21:21.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/kernel/gpu/subdevice/subdevice.c 2024-03-05 22:13:49.000000000 +0000 @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 1993-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 1993-2024 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -195,6 +195,9 @@ subdeviceRestoreLockedClock(pSubdevice, pCallContext); + // Decrement the reference count for VF if previously incremented. + subdeviceRestoreVF(pSubdevice, pCallContext); + // Restore GR tick frequency to default. subdeviceRestoreGrTickFreq(pSubdevice, pCallContext); @@ -422,124 +425,3 @@ krcWatchdogChangeState(pKernelRc, pSubdevice, RM_CLIENT_DESTRUCTION); } -// **************************************************************************** -// Deprecated Functions -// **************************************************************************** - -/** - * WARNING: This function is deprecated! Please use subdeviceGetByGpu and - * GPU_RES_SET_THREAD_BC_STATE (if needed to set thread UC state for SLI) - */ -Subdevice * -CliGetSubDeviceInfoFromGpu -( - NvHandle hClient, - OBJGPU *pGpu -) -{ - RsClient *pClient; - NV_STATUS status; - Subdevice *pSubdevice; - - status = serverGetClientUnderLock(&g_resServ, hClient, &pClient); - if (status != NV_OK) - return NULL; - - status = subdeviceGetByGpu(pClient, pGpu, &pSubdevice); - if (status != NV_OK) - return NULL; - - GPU_RES_SET_THREAD_BC_STATE(pSubdevice); - - return pSubdevice; -} - -/** - * WARNING: This function is deprecated! Please use subdeviceGetByGpu and - * RES_GET_HANDLE - */ -NV_STATUS -CliGetSubDeviceHandleFromGpu -( - NvHandle hClient, - OBJGPU *pGpu, - NvHandle *phSubDevice -) -{ - Subdevice *pSubdevice; - - if (phSubDevice == NULL) - { - return NV_ERR_INVALID_ARGUMENT; - } - - if ((pSubdevice = CliGetSubDeviceInfoFromGpu(hClient, pGpu)) == NULL) - { - return NV_ERR_INVALID_ARGUMENT; - } - - *phSubDevice = RES_GET_HANDLE(pSubdevice); - - return NV_OK; -} - -/** - * WARNING: This function is deprecated and use is *strongly* discouraged - * (especially for new code!) - * - * From the function name (CliSetSubDeviceContext) it appears as a simple - * accessor but violates expectations by modifying the SLI BC threadstate (calls - * to GPU_RES_SET_THREAD_BC_STATE). This can be dangerous if not carefully - * managed by the caller. - * - * Instead of using this routine, please use subdeviceGetByHandle then call - * GPU_RES_GET_GPU, RES_GET_HANDLE, GPU_RES_SET_THREAD_BC_STATE as needed. - * - * Note that GPU_RES_GET_GPU supports returning a pGpu for both pDevice, - * pSubdevice, the base pResource type, and any resource that inherits from - * GpuResource. That is, instead of using CliSetGpuContext or - * CliSetSubDeviceContext, please use following pattern to look up the pGpu: - * - * OBJGPU *pGpu = GPU_RES_GET_GPU(pResource or pResourceRef->pResource) - * - * To set the threadstate, please use: - * - * GPU_RES_SET_THREAD_BC_STATE(pResource or pResourceRef->pResource); - */ -NV_STATUS -CliSetSubDeviceContext -( - NvHandle hClient, - NvHandle hSubdevice, - NvHandle *phDevice, - OBJGPU **ppGpu -) -{ - Subdevice *pSubdevice; - RsClient *pClient; - NV_STATUS status; - - if (phDevice != NULL) - { - *phDevice = 0; - } - *ppGpu = NULL; - - status = serverGetClientUnderLock(&g_resServ, hClient, &pClient); - if (status != NV_OK) - return status; - - status = subdeviceGetByHandle(pClient, hSubdevice, &pSubdevice); - if (status != NV_OK) - return status; - - *ppGpu = GPU_RES_GET_GPU(pSubdevice); - if (phDevice != NULL) - { - *phDevice = RES_GET_HANDLE(pSubdevice->pDevice); - } - - GPU_RES_SET_THREAD_BC_STATE(pSubdevice); - - return NV_OK; -} diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/kernel/gpu/subdevice/subdevice_ctrl_event_kernel.c nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/kernel/gpu/subdevice/subdevice_ctrl_event_kernel.c --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/kernel/gpu/subdevice/subdevice_ctrl_event_kernel.c 2023-10-25 20:21:21.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/kernel/gpu/subdevice/subdevice_ctrl_event_kernel.c 2024-03-05 22:13:49.000000000 +0000 @@ -192,7 +192,7 @@ NV_CHECK_OK_OR_RETURN(LEVEL_SILENT, memGetByHandle(pClient, pSetMemoryNotifiesParams->hMemory, &pMemory)); - if (pMemory->pMemDesc->Size < NV_SIZEOF32(NvNotification) * NV2080_NOTIFIERS_MAXCOUNT) + if (pMemory->pMemDesc->Size < sizeof(NvNotification) * NV2080_NOTIFIERS_MAXCOUNT) { return NV_ERR_INVALID_LIMIT; } diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/kernel/gpu/subdevice/subdevice_ctrl_fla.c nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/kernel/gpu/subdevice/subdevice_ctrl_fla.c --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/kernel/gpu/subdevice/subdevice_ctrl_fla.c 2023-10-25 20:21:21.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/kernel/gpu/subdevice/subdevice_ctrl_fla.c 2024-03-05 22:13:49.000000000 +0000 @@ -174,7 +174,7 @@ ) { NV_STATUS status = NV_OK; - POBJGPU pGpu = GPU_RES_GET_GPU(pSubdevice); + OBJGPU *pGpu = GPU_RES_GET_GPU(pSubdevice); KernelBus *pKernelBus = GPU_GET_KERNEL_BUS(pGpu); KernelMIGManager *pKernelMIGManager; NvHandle hClient = RES_GET_CLIENT_HANDLE(pSubdevice); @@ -293,3 +293,4 @@ return fabricvaspaceGetFreeHeap(pFabricVAS, &pParams->freeSize); } + diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/kernel/gpu/subdevice/subdevice_ctrl_gpu_kernel.c nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/kernel/gpu/subdevice/subdevice_ctrl_gpu_kernel.c --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/kernel/gpu/subdevice/subdevice_ctrl_gpu_kernel.c 2023-10-25 20:21:22.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/kernel/gpu/subdevice/subdevice_ctrl_gpu_kernel.c 2024-03-05 22:13:50.000000000 +0000 @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 2004-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2004-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -29,6 +29,9 @@ * File contains ctrls related to general GPU */ +// FIXME XXX +#define NVOC_KERNEL_GRAPHICS_MANAGER_H_PRIVATE_ACCESS_ALLOWED + #include "core/core.h" #include "core/locks.h" #include "gpu/subdevice/subdevice.h" @@ -318,6 +321,35 @@ } break; } + case NV2080_CTRL_GPU_INFO_INDEX_GPU_LOCAL_EGM_CAPABILITY: + { + MemoryManager *pMemoryManager = GPU_GET_MEMORY_MANAGER(pGpu); + if (memmgrIsLocalEgmEnabled(pMemoryManager)) + { + data = NV2080_CTRL_GPU_INFO_INDEX_GPU_LOCAL_EGM_CAPABILITY_YES; + data = FLD_SET_DRF_NUM(2080_CTRL_GPU_INFO, _INDEX_GPU_LOCAL_EGM, _PEERID, pMemoryManager->localEgmPeerId, data); + } + else + { + data = NV2080_CTRL_GPU_INFO_INDEX_GPU_LOCAL_EGM_CAPABILITY_NO; + } + break; + } + case NV2080_CTRL_GPU_INFO_INDEX_GPU_SELF_HOSTED_CAPABILITY: + { + KernelBif *pKernelBif = GPU_GET_KERNEL_BIF(pGpu); + + if (gpuIsSelfHosted(pGpu) && + pKernelBif->getProperty(pKernelBif, PDB_PROP_KBIF_IS_C2C_LINK_UP)) + { + data = NV2080_CTRL_GPU_INFO_INDEX_GPU_SELF_HOSTED_CAPABILITY_YES; + } + else + { + data = NV2080_CTRL_GPU_INFO_INDEX_GPU_SELF_HOSTED_CAPABILITY_NO; + } + break; + } case NV2080_CTRL_GPU_INFO_INDEX_CMP_SKU: { if (gpuGetChipInfo(pGpu) && gpuGetChipInfo(pGpu)->isCmpSku) @@ -336,12 +368,23 @@ if (osDmabufIsSupported() && (!IS_VIRTUAL(pGpu)) && + (!gpuIsApmFeatureEnabled(pGpu)) && (!NVCPU_IS_PPC64LE)) { data = NV2080_CTRL_GPU_INFO_INDEX_DMABUF_CAPABILITY_YES; } break; } + case NV2080_CTRL_GPU_INFO_INDEX_IS_RESETLESS_MIG_SUPPORTED: + { + data = NV2080_CTRL_GPU_INFO_INDEX_IS_RESETLESS_MIG_SUPPORTED_NO; + + if (pGpu->getProperty(pGpu, PDB_PROP_GPU_RESETLESS_MIG_SUPPORTED)) + { + data = NV2080_CTRL_GPU_INFO_INDEX_IS_RESETLESS_MIG_SUPPORTED_YES; + } + break; + } default: { // Only forward to GSP if we're in the HW-access-enabled control @@ -973,7 +1016,7 @@ if (pKernelMIGManager != NULL) { RM_ENGINE_TYPE rmEngineTypeList[NV2080_GPU_MAX_ENGINES_LIST_SIZE]; - + // Filter engines based on current partitioning scheme status = kmigmgrFilterEngineList(pGpu, pKernelMIGManager, @@ -1010,10 +1053,28 @@ OBJGPU *pGpu = GPU_RES_GET_GPU(pSubdevice); ENGDESCRIPTOR engDesc; NV_STATUS status = NV_OK; + RM_ENGINE_TYPE rmEngineType = gpuGetRmEngineType(pClassParams->engineType); LOCK_ASSERT_AND_RETURN(rmapiLockIsOwner()); - status = gpuXlateClientEngineIdToEngDesc(pGpu, gpuGetRmEngineType(pClassParams->engineType), &engDesc); + { + if (IS_MIG_IN_USE(pGpu)) + { + KernelMIGManager *pKernelMIGManager = GPU_GET_KERNEL_MIG_MANAGER(pGpu); + MIG_INSTANCE_REF ref; + + NV_CHECK_OK_OR_RETURN(LEVEL_ERROR, + kmigmgrGetInstanceRefFromDevice(pGpu, pKernelMIGManager, GPU_RES_GET_DEVICE(pSubdevice), &ref)); + + NV_CHECK_OK_OR_RETURN(LEVEL_ERROR, + kmigmgrGetLocalToGlobalEngineType(pGpu, pKernelMIGManager, ref, + rmEngineType, + &rmEngineType)); + } + } + + status = gpuXlateClientEngineIdToEngDesc(pGpu, rmEngineType, &engDesc); + NV_ASSERT(status == NV_OK); if (status != NV_OK) @@ -1050,7 +1111,6 @@ ) { OBJGPU *pGpu = GPU_RES_GET_GPU(pSubdevice); - NvHandle hClient = RES_GET_CLIENT_HANDLE(pSubdevice); KernelMIGManager *pKernelMIGManager = GPU_GET_KERNEL_MIG_MANAGER(pGpu); ENGDESCRIPTOR engDesc; NvU32 localNv2080EngineType; @@ -1094,11 +1154,12 @@ // Translate the instance-local engine type to the global engine type in MIG mode if (IS_MIG_IN_USE(pGpu)) { + Device *pDevice = GPU_RES_GET_DEVICE(pSubdevice); MIG_INSTANCE_REF ref; NV_CHECK_OK_OR_RETURN( LEVEL_ERROR, - kmigmgrGetInstanceRefFromClient(pGpu, pKernelMIGManager, hClient, &ref)); + kmigmgrGetInstanceRefFromDevice(pGpu, pKernelMIGManager, pDevice, &ref)); NV_CHECK_OK_OR_RETURN( LEVEL_ERROR, @@ -1190,11 +1251,11 @@ if (IS_MIG_IN_USE(pGpu)) { KernelMIGManager *pKernelMIGManager = GPU_GET_KERNEL_MIG_MANAGER(pGpu); - NvHandle hClient = RES_GET_CLIENT_HANDLE(pSubdevice); + Device *pDevice = GPU_RES_GET_DEVICE(pSubdevice); MIG_INSTANCE_REF ref; NV_CHECK_OK_OR_RETURN(LEVEL_ERROR, - kmigmgrGetInstanceRefFromClient(pGpu, pKernelMIGManager, hClient, &ref)); + kmigmgrGetInstanceRefFromDevice(pGpu, pKernelMIGManager, pDevice, &ref)); NV_CHECK_OK_OR_RETURN(LEVEL_ERROR, kmigmgrGetLocalToGlobalEngineType(pGpu, pKernelMIGManager, ref, @@ -1314,7 +1375,7 @@ NvHandle hClient = RES_GET_CLIENT_HANDLE(pSubdevice); NvHandle hSubdevice = RES_GET_HANDLE(pSubdevice); - LOCK_ASSERT_AND_RETURN(rmapiLockIsOwner() && rmGpuLockIsOwner()); + LOCK_ASSERT_AND_RETURN(rmapiLockIsOwner() && rmDeviceGpuLockIsOwner(GPU_RES_GET_GPU(pSubdevice)->gpuInstance)); portMemSet(&zcullMaskParams, 0, sizeof(zcullMaskParams)); zcullMaskParams.gpcId = pParams->gpcId; @@ -1720,13 +1781,14 @@ if (IS_MIG_IN_USE(pGpu) && !rmclientIsCapableByHandle(hClient, NV_RM_CAP_SYS_SMC_MONITOR)) { + Device *pDevice = GPU_RES_GET_DEVICE(pSubdevice); // // Check instanceSubscription to limit the scope of the call // Clients with mig-monitor capability are allowed to get full device // info // - NV_CHECK_OR_RETURN(LEVEL_INFO, (kmigmgrGetInstanceRefFromClient(pGpu, pKernelMIGManager, - hClient, pRef) == NV_OK), + NV_CHECK_OR_RETURN(LEVEL_INFO, (kmigmgrGetInstanceRefFromDevice(pGpu, pKernelMIGManager, + pDevice, pRef) == NV_OK), NV_ERR_INSUFFICIENT_PERMISSIONS); } @@ -1786,13 +1848,14 @@ if (IS_MIG_IN_USE(pGpu) && !rmclientIsCapableByHandle(hClient, NV_RM_CAP_SYS_SMC_MONITOR)) { + Device *pDevice = GPU_RES_GET_DEVICE(pSubdevice); // // Check instanceSubscription to limit the scope of the call // Clients with mig-monitor capability are allowed to get full device // info // - NV_CHECK_OR_RETURN(LEVEL_INFO, (kmigmgrGetInstanceRefFromClient(pGpu, pKernelMIGManager, - hClient, pRef) == NV_OK), + NV_CHECK_OR_RETURN(LEVEL_INFO, (kmigmgrGetInstanceRefFromDevice(pGpu, pKernelMIGManager, + pDevice, pRef) == NV_OK), NV_ERR_INSUFFICIENT_PERMISSIONS); bGlobalInfo = NV_FALSE; } @@ -1875,14 +1938,13 @@ if (IS_MIG_IN_USE(pGpu)) { KernelMIGManager *pKernelMIGManager = GPU_GET_KERNEL_MIG_MANAGER(pGpu); - MIG_INSTANCE_REF ref; - NvHandle hClient = RES_GET_CLIENT_HANDLE(pSubdevice); + Device *pDevice = GPU_RES_GET_DEVICE(pSubdevice); + MIG_INSTANCE_REF ref; NV_CHECK_OK_OR_RETURN( LEVEL_ERROR, - kmigmgrGetInstanceRefFromClient(pGpu, pKernelMIGManager, - hClient, - &ref)); + kmigmgrGetInstanceRefFromDevice(pGpu, pKernelMIGManager, + pDevice, &ref)); NV_CHECK_OK_OR_RETURN( LEVEL_ERROR, @@ -1947,14 +2009,13 @@ if (IS_MIG_IN_USE(pGpu)) { KernelMIGManager *pKernelMIGManager = GPU_GET_KERNEL_MIG_MANAGER(pGpu); - MIG_INSTANCE_REF ref; - NvHandle hClient = RES_GET_CLIENT_HANDLE(pSubdevice); + Device *pDevice = GPU_RES_GET_DEVICE(pSubdevice); + MIG_INSTANCE_REF ref; NV_CHECK_OK_OR_RETURN( LEVEL_ERROR, - kmigmgrGetInstanceRefFromClient(pGpu, pKernelMIGManager, - hClient, - &ref)); + kmigmgrGetInstanceRefFromDevice(pGpu, pKernelMIGManager, + pDevice, &ref)); NV_CHECK_OK_OR_RETURN( LEVEL_ERROR, @@ -1993,6 +2054,7 @@ pParams->maxSupportedPageSize = RM_PAGE_SIZE; KernelGmmu *pKernelGmmu = GPU_GET_KERNEL_GMMU(pGpu); + if (kgmmuIsPageSize512mbSupported(pKernelGmmu)) { pParams->maxSupportedPageSize = RM_PAGE_SIZE_512M; @@ -2003,10 +2065,12 @@ } else { - pParams->maxSupportedPageSize = kgmmuGetMaxBigPageSize_HAL(pKernelGmmu); + pParams->maxSupportedPageSize = (NvU32)kgmmuGetMaxBigPageSize_HAL(pKernelGmmu); } - if (gpuIsSriovEnabled(pGpu)) + if (gpuIsSriovEnabled(pGpu) + || gpuIsCCFeatureEnabled(pGpu) + ) { NvU64 vmmuSegmentSize = gpuGetVmmuSegmentSize(pGpu); if (vmmuSegmentSize > 0 && @@ -2042,8 +2106,9 @@ } NV_CHECK_OK_OR_RETURN(LEVEL_ERROR, - kgrmgrCtrlRouteKGR(pGpu, pKernelGraphicsManager, RES_GET_CLIENT_HANDLE(pSubdevice), - &pParams->grRouteInfo, &pKernelGraphics)); + kgrmgrCtrlRouteKGRWithDevice(pGpu, pKernelGraphicsManager, + GPU_RES_GET_DEVICE(pSubdevice), + &pParams->grRouteInfo, &pKernelGraphics)); pKernelGraphicsStaticInfo = kgraphicsGetStaticInfo(pGpu, pKernelGraphics); NV_ASSERT_OR_RETURN(pKernelGraphicsStaticInfo != NULL, NV_ERR_INVALID_STATE); @@ -2062,9 +2127,6 @@ /* * @brief Update/Set the compute policy config for a GPU * - * Lock Requirements: - * Assert that API and GPUs lock held on entry - * * @param[in] pSubdevice * @param[in] pParams pointer to control parameters * @@ -2086,8 +2148,6 @@ NvU32 gidFlags; NV_STATUS status = NV_OK; - LOCK_ASSERT_AND_RETURN(rmapiLockIsOwner() && rmGpuLockIsOwner()); - switch(pParams->config.type) { case NV2080_CTRL_GPU_COMPUTE_POLICY_TIMESLICE: @@ -2139,9 +2199,6 @@ /* * @brief Get all compute policy configs for a GPU * - * Lock Requirements: - * Assert that API and GPUs lock held on entry - * * @param[in] pSubdevice * @param[in] pParams pointer to control parameters * @@ -2162,8 +2219,6 @@ NvU32 gidFlags; NV_STATUS status = NV_OK; - LOCK_ASSERT_AND_RETURN(rmapiLockIsOwner() && rmGpuLockIsOwner()); - gidFlags = DRF_DEF(2080_GPU_CMD, _GPU_GET_GID_FLAGS, _TYPE, _SHA1) | DRF_DEF(2080_GPU_CMD, _GPU_GET_GID_FLAGS, _FORMAT, _BINARY); status = gpuGetGidInfo(pGpu, NULL, NULL, gidFlags); @@ -2266,7 +2321,7 @@ NvU32 bar0MapSize; NvU64 bar0MapOffset; - LOCK_ASSERT_AND_RETURN(rmapiLockIsOwner() && rmGpuLockIsOwner()); + LOCK_ASSERT_AND_RETURN(rmapiLockIsOwner() && rmDeviceGpuLockIsOwner(GPU_RES_GET_GPU(pSubdevice)->gpuInstance)); pParams->protection = NV_PROTECT_READ_WRITE; @@ -2494,6 +2549,19 @@ return NV_OK; } +/* + * Set the EGM fabric base address + */ +NV_STATUS +subdeviceCtrlCmdGpuSetEgmGpaFabricAddr_IMPL +( + Subdevice *pSubdevice, + NV2080_CTRL_GPU_SET_EGM_GPA_FABRIC_BASE_ADDR_PARAMS *pParams +) +{ + return NV_OK; +} + /*! * @brief: This command returns the load time (latency) of each engine, * implementing NV2080_CTRL_CMD_GPU_GET_ENGINE_LOAD_TIMES control call. @@ -2622,13 +2690,13 @@ LOCK_ASSERT_AND_RETURN(rmapiLockIsOwner() && rmDeviceGpuLockIsOwner(gpuGetInstance(pGpu))); - if (pGpu->pGpuFabricProbeInfo == NULL) + if (pGpu->pGpuFabricProbeInfoKernel == NULL) { pParams->state = NV2080_CTRL_GPU_FABRIC_PROBE_STATE_UNSUPPORTED; return NV_OK; } - status = gpuFabricProbeGetNumProbeReqs(pGpu->pGpuFabricProbeInfo, + status = gpuFabricProbeGetNumProbeReqs(pGpu->pGpuFabricProbeInfoKernel, &numProbeReqs); if (status != NV_OK) { @@ -2640,10 +2708,10 @@ NV2080_CTRL_GPU_FABRIC_PROBE_STATE_NOT_STARTED : NV2080_CTRL_GPU_FABRIC_PROBE_STATE_IN_PROGRESS; - if (gpuFabricProbeIsReceived(pGpu->pGpuFabricProbeInfo)) + if (gpuFabricProbeIsReceived(pGpu->pGpuFabricProbeInfoKernel)) { pParams->state = NV2080_CTRL_GPU_FABRIC_PROBE_STATE_COMPLETE; - pParams->status = gpuFabricProbeGetFmStatus(pGpu->pGpuFabricProbeInfo); + pParams->status = gpuFabricProbeGetFmStatus(pGpu->pGpuFabricProbeInfoKernel); if (pParams->status != NV_OK) { // Nothing needs to be done as probe response status is not success @@ -2652,13 +2720,13 @@ ct_assert(NV2080_GPU_FABRIC_CLUSTER_UUID_LEN == NV_UUID_LEN); - NV_ASSERT_OK(gpuFabricProbeGetClusterUuid(pGpu->pGpuFabricProbeInfo, + NV_ASSERT_OK(gpuFabricProbeGetClusterUuid(pGpu->pGpuFabricProbeInfoKernel, pClusterUuid)); - NV_ASSERT_OK(gpuFabricProbeGetFabricPartitionId(pGpu->pGpuFabricProbeInfo, + NV_ASSERT_OK(gpuFabricProbeGetFabricPartitionId(pGpu->pGpuFabricProbeInfoKernel, &pParams->fabricPartitionId)); - NV_ASSERT_OK(gpuFabricProbeGetfmCaps(pGpu->pGpuFabricProbeInfo, &fmCaps)); + NV_ASSERT_OK(gpuFabricProbeGetfmCaps(pGpu->pGpuFabricProbeInfoKernel, &fmCaps)); pParams->fabricCaps = _convertGpuFabricProbeInfoCaps(fmCaps); } diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/kernel/gpu/subdevice/subdevice_ctrl_gpu_regops.c nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/kernel/gpu/subdevice/subdevice_ctrl_gpu_regops.c --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/kernel/gpu/subdevice/subdevice_ctrl_gpu_regops.c 2023-10-25 20:21:22.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/kernel/gpu/subdevice/subdevice_ctrl_gpu_regops.c 2024-03-05 22:13:50.000000000 +0000 @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 2004-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2004-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -120,7 +120,7 @@ RmCtrlParams *pRmCtrlParams = pCallContext->pControlParams; NvBool bUseMigratableOps; - LOCK_ASSERT_AND_RETURN(rmapiLockIsOwner() && rmGpuLockIsOwner()); + LOCK_ASSERT_AND_RETURN(rmapiLockIsOwner() && rmDeviceGpuLockIsOwner(GPU_RES_GET_GPU(pSubdevice)->gpuInstance)); NV_PRINTF(LEVEL_INFO, "client 0x%x channel 0x%x\n", hClientTarget, hChannelTarget); @@ -183,12 +183,12 @@ } else { - NV_RM_RPC_GPU_EXEC_REG_OPS(pGpu, - pRmCtrlParams->hClient, - pRmCtrlParams->hObject, - pRmCtrlParams->pParams, - pRegOps, - status); + NV_RM_RPC_GPU_EXEC_REG_OPS(pGpu, + pRmCtrlParams->hClient, + pRmCtrlParams->hObject, + pRmCtrlParams->pParams, + pRegOps, + status); } return status; } diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/kernel/gpu/subdevice/subdevice_ctrl_timer_kernel.c nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/kernel/gpu/subdevice/subdevice_ctrl_timer_kernel.c --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/kernel/gpu/subdevice/subdevice_ctrl_timer_kernel.c 2023-10-25 20:21:22.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/kernel/gpu/subdevice/subdevice_ctrl_timer_kernel.c 2024-03-05 22:13:50.000000000 +0000 @@ -292,11 +292,44 @@ LOCK_ASSERT_AND_RETURN(rmapiLockIsOwner() && rmGpuLockIsOwner()); - NV_ASSERT_OR_RETURN((pParams->sampleCount <= - NV2080_CTRL_TIMER_GPU_CPU_TIME_MAX_SAMPLES), - NV_ERR_INVALID_ARGUMENT); + NV_CHECK_OR_RETURN(LEVEL_SILENT, + (pParams->sampleCount <= NV2080_CTRL_TIMER_GPU_CPU_TIME_MAX_SAMPLES), + NV_ERR_INVALID_ARGUMENT); - switch (pParams->cpuClkId) + if (RMCFG_FEATURE_PLATFORM_GSP) + { + NV_ASSERT_OR_RETURN( + FLD_TEST_DRF(2080, _TIMER_GPU_CPU_TIME_CPU_CLK_ID, _PROCESSOR, _GSP, + pParams->cpuClkId), + NV_ERR_INVALID_ARGUMENT); + } + else if (FLD_TEST_DRF(2080, _TIMER_GPU_CPU_TIME_CPU_CLK_ID, _PROCESSOR, _GSP, + pParams->cpuClkId)) + { + // + // If GSP time is requested, forward the whole request to GSP. + // This can only be supported in GSP-RM offload mode. + // + if (!IS_GSP_CLIENT(pGpu)) + return NV_ERR_NOT_SUPPORTED; + + RM_API *pRmApi = GPU_GET_PHYSICAL_RMAPI(pGpu); + + return pRmApi->Control(pRmApi, + pGpu->hInternalClient, + pGpu->hInternalSubdevice, + NV2080_CTRL_CMD_TIMER_GET_GPU_CPU_TIME_CORRELATION_INFO, + pParams, sizeof(*pParams)); + } + else + { + NV_CHECK_OR_RETURN(LEVEL_SILENT, + FLD_TEST_DRF(2080, _TIMER_GPU_CPU_TIME_CPU_CLK_ID, _PROCESSOR, _CPU, + pParams->cpuClkId), + NV_ERR_INVALID_ARGUMENT); + } + + switch (DRF_VAL(2080, _TIMER_GPU_CPU_TIME_CPU_CLK_ID, _SOURCE, pParams->cpuClkId)) { case NV2080_TIMER_GPU_CPU_TIME_CPU_CLK_ID_OSTIME: { diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/kernel/gpu/sw_test.c nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/kernel/gpu/sw_test.c --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/kernel/gpu/sw_test.c 2023-10-25 20:21:22.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/kernel/gpu/sw_test.c 2024-03-05 22:13:51.000000000 +0000 @@ -45,7 +45,7 @@ chandesIsolateOnDestruct(pChannelDescendant); } -static METHOD Nv04SoftwareTestMethods[] = +static const METHOD Nv04SoftwareTestMethods[] = { {mthdNoOperation, 0x0100, 0x0103}, }; @@ -53,12 +53,12 @@ NV_STATUS swtestGetSwMethods_IMPL ( SoftwareMethodTest *pSwTest, - METHOD **ppMethods, + const METHOD **ppMethods, NvU32 *pNumMethods ) { *ppMethods = Nv04SoftwareTestMethods; - *pNumMethods = NV_ARRAY_ELEMENTS32(Nv04SoftwareTestMethods); + *pNumMethods = NV_ARRAY_ELEMENTS(Nv04SoftwareTestMethods); return NV_OK; } diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/kernel/gpu/timed_semaphore.c nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/kernel/gpu/timed_semaphore.c --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/kernel/gpu/timed_semaphore.c 2023-10-25 20:21:22.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/kernel/gpu/timed_semaphore.c 2024-03-05 22:13:51.000000000 +0000 @@ -104,7 +104,7 @@ ( OBJGPU *pGpu, ChannelDescendant *pObject, - NvHandle hClient, + RsClient *pClient, NvU64 notifierGPUVA, NvU64 semaphoreGPUVA, NvU64 time, @@ -122,7 +122,7 @@ pObject->pKernelChannel->hVASpace, releaseValue, notifierStatus, - hClient); + pClient); // timedSemaphoreRelease_HAL will print errors on its own if (status != NV_OK) @@ -183,7 +183,7 @@ { status = _9074TimedSemRelease(pGpu, pObject, - RES_GET_CLIENT_HANDLE(pTimedSemSw), + RES_GET_CLIENT(pTimedSemSw), notifierGPUVA, semaphoreGPUVA, currentTime, @@ -339,7 +339,6 @@ ( OBJGPU *pGpu, ChannelDescendant *pObject, - PMETHOD pMethod, NvU32 Offset, NvU32 Data ) @@ -358,7 +357,6 @@ ( OBJGPU *pGpu, ChannelDescendant *pObject, - PMETHOD pMethod, NvU32 Offset, NvU32 Data ) @@ -394,7 +392,6 @@ ( OBJGPU *pGpu, ChannelDescendant *pObject, - PMETHOD pMethod, NvU32 Offset, NvU32 Data ) @@ -413,7 +410,6 @@ ( OBJGPU *pGpu, ChannelDescendant *pObject, - PMETHOD pMethod, NvU32 Offset, NvU32 Data ) @@ -449,7 +445,6 @@ ( OBJGPU *pGpu, ChannelDescendant *pObject, - PMETHOD pMethod, NvU32 Offset, NvU32 Data ) @@ -468,7 +463,6 @@ ( OBJGPU *pGpu, ChannelDescendant *pObject, - PMETHOD pMethod, NvU32 Offset, NvU32 Data ) @@ -497,7 +491,6 @@ ( OBJGPU *pGpu, ChannelDescendant *pObject, - PMETHOD pMethod, NvU32 Offset, NvU32 Data ) @@ -516,7 +509,6 @@ ( OBJGPU *pGpu, ChannelDescendant *pObject, - PMETHOD pMethod, NvU32 Offset, NvU32 Data ) @@ -576,7 +568,7 @@ status = _9074TimedSemRelease(pGpu, pObject, - RES_GET_CLIENT_HANDLE(pTimedSemSw), + RES_GET_CLIENT(pTimedSemSw), pTimedSemEntry->NotifierGPUVA, pTimedSemEntry->SemaphoreGPUVA, currentTime, @@ -599,7 +591,7 @@ } // end of _class9074TimerCallback // GF100_TIMED_SEMAPHORE_SW -static METHOD GF100TimedSemSwMethods[] = +static const METHOD GF100TimedSemSwMethods[] = { { mthdNoOperation, 0x0100, 0x0103 }, { _class9074SetNotifierHi, 0x0140, 0x0143 }, @@ -615,12 +607,12 @@ NV_STATUS tsemaGetSwMethods_IMPL ( TimedSemaSwObject *pTimedSemSw, - METHOD **ppMethods, + const METHOD **ppMethods, NvU32 *pNumMethods ) { *ppMethods = GF100TimedSemSwMethods; - *pNumMethods = NV_ARRAY_ELEMENTS32(GF100TimedSemSwMethods); + *pNumMethods = NV_ARRAY_ELEMENTS(GF100TimedSemSwMethods); return NV_OK; } @@ -633,7 +625,7 @@ NvU32 hVASpace, NvU32 releaseValue, NvU32 completionStatus, - NvHandle hClient + RsClient *pClient ) { OBJTMR *pTmr = GPU_GET_TIMER(pGpu); @@ -644,7 +636,7 @@ tmrGetCurrentTime(pTmr, ¤tTime); status = semaphoreFillGPUVATimestamp(pGpu, - hClient, + pClient, hVASpace, semaphoreVA, releaseValue, @@ -660,7 +652,7 @@ } status = notifyFillNotifierGPUVATimestamp(pGpu, - hClient, + pClient, hVASpace, notifierVA, 0, /* Info32 */ diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/kernel/gpu/timer/arch/ampere/timer_ga100.c nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/kernel/gpu/timer/arch/ampere/timer_ga100.c --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/kernel/gpu/timer/arch/ampere/timer_ga100.c 2023-10-25 20:21:22.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/kernel/gpu/timer/arch/ampere/timer_ga100.c 2024-03-05 22:13:52.000000000 +0000 @@ -41,8 +41,8 @@ NV_STATUS tmrGetGpuPtimerOffset_GA100 ( - POBJGPU pGpu, - POBJTMR pTmr, + OBJGPU *pGpu, + OBJTMR *pTmr, NvU32 *pGpuTimestampOffsetLo, NvU32 *pGpuTimestampOffsetHi ) diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/kernel/gpu/timer/arch/hopper/timer_gh100.c nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/kernel/gpu/timer/arch/hopper/timer_gh100.c --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/kernel/gpu/timer/arch/hopper/timer_gh100.c 2023-10-25 20:21:22.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/kernel/gpu/timer/arch/hopper/timer_gh100.c 2024-03-05 22:13:52.000000000 +0000 @@ -86,7 +86,7 @@ { // // We can only safely program the timer offset if FSP includes the fix - // for bug 3957833. + // for bug 3957833. // GPU_REG_WR32(pGpu, NV_PGC6_SCI_SYS_TIMER_OFFSET_1, NvU64_HI32(sysTimerOffsetNs)); GPU_REG_WR32(pGpu, NV_PGC6_SCI_SYS_TIMER_OFFSET_0, NvU64_LO32(sysTimerOffsetNs) | @@ -107,8 +107,8 @@ NV_STATUS tmrSetCountdown_GH100 ( - POBJGPU pGpu, - POBJTMR pTmr, + OBJGPU *pGpu, + OBJTMR *pTmr, NvU32 time, NvU32 tmrId, THREAD_STATE_NODE *pThreadState diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/kernel/gpu/timer/arch/maxwell/timer_gm107.c nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/kernel/gpu/timer/arch/maxwell/timer_gm107.c --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/kernel/gpu/timer/arch/maxwell/timer_gm107.c 2023-10-25 20:21:22.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/kernel/gpu/timer/arch/maxwell/timer_gm107.c 2024-03-05 22:13:53.000000000 +0000 @@ -89,8 +89,8 @@ NV_STATUS tmrGetGpuAndCpuTimestampPair_GM107 ( - POBJGPU pGpu, - POBJTMR pTmr, + OBJGPU *pGpu, + OBJTMR *pTmr, NvU64 *pGpuTime, NvU64 *pCpuTime ) @@ -165,8 +165,8 @@ NV_STATUS tmrGetGpuPtimerOffset_GM107 ( - POBJGPU pGpu, - POBJTMR pTmr, + OBJGPU *pGpu, + OBJTMR *pTmr, NvU32 *pGpuTimestampOffsetLo, NvU32 *pGpuTimestampOffsetHi ) diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/kernel/gpu/timer/arch/turing/timer_tu102.c nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/kernel/gpu/timer/arch/turing/timer_tu102.c --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/kernel/gpu/timer/arch/turing/timer_tu102.c 2023-10-25 20:21:23.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/kernel/gpu/timer/arch/turing/timer_tu102.c 2024-03-05 22:13:53.000000000 +0000 @@ -38,8 +38,8 @@ NV_STATUS tmrSetCountdown_TU102 ( - POBJGPU pGpu, - POBJTMR pTmr, + OBJGPU *pGpu, + OBJTMR *pTmr, NvU32 time, NvU32 tmrId, THREAD_STATE_NODE *pThreadState @@ -128,16 +128,14 @@ /* * @brief This function returns the PTIMER_TIME_0 register. This function will * work for both Physical function and virtual function in SR-IOV. - * @param[in] POBJGPU - GPU Object pointer - * @param[in] POBJTMR - Timer Object pointer * * @return NvU32 */ NvU32 tmrReadTimeLoReg_TU102 ( - POBJGPU pGpu, - POBJTMR pTmr, + OBJGPU *pGpu, + OBJTMR *pTmr, THREAD_STATE_NODE *pThreadState ) { @@ -147,16 +145,14 @@ /* * @brief This function returns the PTIMER_TIME_1 register. This function will * work for both Physical function and virtual function in SR-IOV. - * @param[in] POBJGPU - GPU Object pointer - * @param[in] POBJTMR - Timer Object pointer * * @return NvU32 */ NvU32 tmrReadTimeHiReg_TU102 ( - POBJGPU pGpu, - POBJTMR pTmr, + OBJGPU *pGpu, + OBJTMR *pTmr, THREAD_STATE_NODE *pThreadState ) { diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/kernel/gpu/timer/arch/volta/timer_gv100.c nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/kernel/gpu/timer/arch/volta/timer_gv100.c --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/kernel/gpu/timer/arch/volta/timer_gv100.c 2023-10-25 20:21:23.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/kernel/gpu/timer/arch/volta/timer_gv100.c 2024-03-05 22:13:53.000000000 +0000 @@ -91,8 +91,8 @@ NV_STATUS tmrGetGpuPtimerOffset_GV100 ( - POBJGPU pGpu, - POBJTMR pTmr, + OBJGPU *pGpu, + OBJTMR *pTmr, NvU32 *pGpuTimestampOffsetLo, NvU32 *pGpuTimestampOffsetHi ) diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/kernel/gpu/timer/timer.c nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/kernel/gpu/timer/timer.c --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/kernel/gpu/timer/timer.c 2023-10-25 20:21:23.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/kernel/gpu/timer/timer.c 2024-03-05 22:13:53.000000000 +0000 @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 1993-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 1993-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -37,6 +37,7 @@ /* ------------------------ Static Function Prototypes ---------------------- */ static PTMR_EVENT_PVT _tmrPullCallbackFromHead (OBJTMR *); static void _tmrScanCallback(OBJTMR *, void *); +static void _tmrScanCallbackOSTimer(OBJTMR *, PTMR_EVENT_PVT); static PTMR_EVENT_PVT _tmrGetNextFreeCallback(OBJTMR *); static NV_STATUS _tmrInsertCallback(OBJTMR *, PTMR_EVENT_PVT, NvU64); static void _tmrInsertCallbackInList(OBJGPU *pGpu, OBJTMR *pTmr, PTMR_EVENT_PVT pEvent); @@ -205,6 +206,13 @@ return pTmr->pRmActiveEventList != NULL; } +static NV_INLINE NvBool tmrIsOSTimer(OBJTMR *pTmr, PTMR_EVENT pEventPublic) +{ + return ((pEventPublic != NULL) && + (pTmr->getProperty(pTmr, PDB_PROP_TMR_USE_OS_TIMER_FOR_CALLBACKS) || + (pEventPublic->flags & TMR_FLAG_USE_OS_TIMER))); +} + /*! * Allocates the necessary memory for storing a callback in the timer. * @@ -235,8 +243,7 @@ (*ppEventPublic)->pUserData = pUserData; (*ppEventPublic)->flags = flags; - if (pTmr->getProperty(pTmr, PDB_PROP_TMR_USE_OS_TIMER_FOR_CALLBACKS) || - (flags & TMR_FLAG_USE_OS_TIMER)) + if (tmrIsOSTimer(pTmr, *ppEventPublic)) { status = tmrEventCreateOSTimer_HAL(pTmr, *ppEventPublic); if (status != NV_OK) @@ -339,10 +346,10 @@ pEvent->bInUse = NV_FALSE; - if (pTmr->getProperty(pTmr, PDB_PROP_TMR_USE_OS_TIMER_FOR_CALLBACKS) || - (pEventPublic->flags & TMR_FLAG_USE_OS_TIMER)) + if (tmrIsOSTimer(pTmr, pEventPublic)) { NV_STATUS status = NV_OK; + _tmrScanCallbackOSTimer(pTmr, pEvent); status = tmrEventCancelOSTimer_HAL(pTmr, pEventPublic); if (status != NV_OK) { @@ -398,9 +405,10 @@ if (pEvent != NULL) { NV_ASSERT(!pEvent->bLegacy); - if (pTmr->getProperty(pTmr, PDB_PROP_TMR_USE_OS_TIMER_FOR_CALLBACKS) || - (pEventPublic->flags & TMR_FLAG_USE_OS_TIMER)) + if (tmrIsOSTimer(pTmr, pEventPublic)) { + _tmrScanCallbackOSTimer(pTmr, pEvent); + // OS timer destroying will cancel the timer tmrEventDestroyOSTimer_HAL(pTmr, pEventPublic); } @@ -548,21 +556,29 @@ NvU64 AbsTime, currentTime; NV_STATUS rmStatus; + if ((pEvent != NULL) && tmrIsOSTimer(pTmr, pEvent)) + { + TMR_EVENT_PVT *pEventPvt = (TMR_EVENT_PVT *)pEvent; + + NV_CHECK_OK(rmStatus, LEVEL_ERROR, + tmrEventScheduleRelOSTimer_HAL(pTmr, pEvent, RelTime)); + // + // Capture system time here, this will help in scheduling callbacks + // if there is a state unload before receiving the OS timer callback. + // + osGetCurrentTick(&pEventPvt->startTimeNs); + if (!tmrEventOnList(pTmr, pEvent)) + { + _tmrInsertCallback(pTmr, pEventPvt, RelTime); + } + return rmStatus; + } + rmStatus = tmrGetCurrentTime(pTmr, ¤tTime); if (rmStatus != NV_OK) return rmStatus; - if (pTmr->getProperty(pTmr, PDB_PROP_TMR_USE_OS_TIMER_FOR_CALLBACKS) || - (pEvent->flags & TMR_FLAG_USE_OS_TIMER)) - { - /*HR timer scheduled in relative mode*/ - /*TBD : This condition needs to be moved to OS timer handling functions */ - AbsTime = RelTime; - } - else - { - NV_CHECK_OR_RETURN(LEVEL_ERROR, portSafeAddU64(currentTime, RelTime, &AbsTime), NV_ERR_INVALID_ARGUMENT); - } + NV_CHECK_OR_RETURN(LEVEL_ERROR, portSafeAddU64(currentTime, RelTime, &AbsTime), NV_ERR_INVALID_ARGUMENT); return tmrEventScheduleAbs(pTmr, pEvent, AbsTime); } @@ -628,7 +644,9 @@ ) { PTMR_EVENT_PVT pEvent = (PTMR_EVENT_PVT)pEventPublic; - PTMR_EVENT_PVT pScan = pTmr->pRmActiveEventList; + PTMR_EVENT_PVT pScan = tmrIsOSTimer(pTmr, pEventPublic) ? + pTmr->pRmActiveOSTimerEventList : + pTmr->pRmActiveEventList; while (pScan != NULL) { @@ -734,7 +752,9 @@ } /*! - * Insert (time sorted) a specific event into the callback queue. + * Insert (time sorted) a specific event into the callback queue in case + * of GPU Timer. Insert a specific event on the top of callback queue in + * case of OS timer. * * Handles setting the next alarm time as well as enabling alarm if needed * @@ -753,9 +773,15 @@ NvU64 nextAlarmTime; NV_ASSERT(!pEvent->bInUse); - pEvent->bInUse = NV_TRUE; + if (tmrIsOSTimer(pTmr, (PTMR_EVENT)pEvent)) + { + pEvent->pNext = pTmr->pRmActiveOSTimerEventList; + pTmr->pRmActiveOSTimerEventList = pEvent; + return; + } + if (pTmr->pRmActiveEventList == NULL) { // Enable PTIMER interrupt. @@ -832,21 +858,25 @@ ( OBJTMR *pTmr, PTMR_EVENT pEventPublic, - NvU64 Time + NvU64 timeAbsNs ) { NV_STATUS rmStatus = NV_OK; - PTMR_EVENT_PVT pEvent = (PTMR_EVENT_PVT)pEventPublic; + TMR_EVENT_PVT *pEvent = (TMR_EVENT_PVT *)pEventPublic; - if (pTmr->getProperty(pTmr, PDB_PROP_TMR_USE_OS_TIMER_FOR_CALLBACKS) || - (pEventPublic->flags & TMR_FLAG_USE_OS_TIMER)) + if ((pEvent != NULL) && tmrIsOSTimer(pTmr, pEventPublic)) { - NV_CHECK_OK(rmStatus, LEVEL_ERROR, - tmrEventScheduleAbsOSTimer_HAL(pTmr, pEventPublic, Time)); + // + // OS-Timer is supported only in Relative mode. This assert is to trap + // if someone trying to call tmrEventScheduleAbs for OSTimer + // + NV_ASSERT_FAILED("Attempting to schedule OS-Timer callback with Abs time."); + rmStatus = NV_ERR_INVALID_ARGUMENT; return rmStatus; } - if (pEventPublic->pTimeProc == NULL && pEvent->pTimeProc_OBSOLETE == NULL) + if ((pEvent == NULL) || (pEventPublic->pTimeProc == NULL && + pEvent->pTimeProc_OBSOLETE == NULL)) { // // Bug 372159: Not sure exactly how this is happening, but we are seeing @@ -877,7 +907,7 @@ // removed the 250 ns threshold, so that we will always re-read the // current time after setting the alarm to prevent the wrap-around. // - rmStatus = _tmrInsertCallback(pTmr, pEvent, Time); + rmStatus = _tmrInsertCallback(pTmr, pEvent, timeAbsNs); } return rmStatus; @@ -1024,6 +1054,40 @@ } } +/*! + * This function removes the timer callback from the OS timer list + * after it is serviced, cancelled, or destroyed. + */ +static void +_tmrScanCallbackOSTimer +( + OBJTMR *pTmr, + PTMR_EVENT_PVT pEvent +) +{ + PTMR_EVENT_PVT pCurrent = pTmr->pRmActiveOSTimerEventList; + + if (pCurrent == pEvent) + { + pTmr->pRmActiveOSTimerEventList = pCurrent->pNext; + pEvent->pNext = NULL; + pEvent->bInUse = NV_FALSE; + return; + } + + while (pCurrent != NULL) + { + if (pCurrent->pNext == pEvent) + { + pCurrent->pNext = pEvent->pNext; + pEvent->pNext = NULL; + pEvent->bInUse = NV_FALSE; + break; + } + pCurrent = pCurrent->pNext; + } +} + // determine which (if any) callback should determine the next alarm time static NV_STATUS _tmrGetNextAlarmTime @@ -1200,6 +1264,7 @@ ) { NvU64 nextAlarmTime = 0; + PTMR_EVENT_PVT pScan = pTmr->pRmActiveOSTimerEventList; if (tmrEventsExist(pTmr)) { @@ -1224,6 +1289,18 @@ tmrSetAlarmIntrEnable_HAL(pGpu, pTmr); } } + + // Schedule the timer callbacks which were paused during state unload + while (pScan != NULL) + { + // + // Capture system time here, this will help in scheduling callbacks + // if there is a state unload before receiving the OS timer callback. + // + osGetCurrentTick(&pScan->startTimeNs); + tmrEventScheduleRelOSTimer_HAL(pTmr, (PTMR_EVENT)pScan, pScan->timens); + pScan = pScan->pNext; + } } /*! @@ -1344,6 +1421,7 @@ // Initialize the timer callback lists. pTmr->pRmActiveEventList = NULL; + pTmr->pRmActiveOSTimerEventList = NULL; // Everything below this comment will be removed with new API pTmr->pRmCallbackFreeList_OBSOLETE = pTmr->rmCallbackTable_OBSOLETE; @@ -1488,10 +1566,36 @@ NvU32 flags ) { + PTMR_EVENT_PVT pScan = pTmr->pRmActiveOSTimerEventList; + NvU64 currentSysTime, elapsedTime; + // Disable Timer interrupt. tmrSetAlarmIntrDisable_HAL(pGpu, pTmr); tmrSetCountdownIntrDisable_HAL(pGpu, pTmr); + // + // Cancel OS timers, and save the time remaining for callback + // in 'timens', to reschedule after state load. + // + while (pScan != NULL) + { + osGetCurrentTick(¤tSysTime); + // + // If somehow any of the time difference is negative, + // we will use the original time duration. + // + if (currentSysTime >= pScan->startTimeNs) + { + elapsedTime = currentSysTime - pScan->startTimeNs; + if (pScan->timens > elapsedTime) + { + pScan->timens -= elapsedTime; + } + } + + tmrEventCancelOSTimer_HAL(pTmr, (PTMR_EVENT)pScan); + pScan = pScan->pNext; + } return NV_OK; } @@ -1663,6 +1767,7 @@ /*! * Schedules an existing event. Takes in time arguments and a flag to * determine if it should be interpreted as absolute or relative time. + * While using OSTimer, use this api only with relative time. * * @returns NV_STATUS */ @@ -1675,10 +1780,19 @@ { NV_STATUS rc; OBJTMR *pTmr = GPU_GET_TIMER(pGpu); - PTMR_EVENT pEvent = (PTMR_EVENT)NvP64_VALUE(pParams->pEvent); + TMR_EVENT *pEvent = (PTMR_EVENT)NvP64_VALUE(pParams->pEvent); - if(pParams->bUseTimeAbs) + if (pParams->bUseTimeAbs) { + // + // FIXME: This function is called only from dynamic_power.c file, + // using OSTimer. And OSTimer is always scheduled in relative mode + // + if ((pEvent != NULL) && tmrIsOSTimer(pTmr, pEvent)) + { + NV_ASSERT_FAILED("Attempting to schedule OSTimer with Abs time."); + return NV_ERR_INVALID_ARGUMENT; + } rc = tmrEventScheduleAbs(pTmr, pEvent, pParams->timeNs); } else @@ -1732,6 +1846,30 @@ return NV_OK; } +NV_STATUS tmrEventServiceTimer_IMPL +( + OBJGPU *pGpu, + OBJTMR *pTmr, + PTMR_EVENT pPublicEvent +) +{ + PTMR_EVENT_PVT pEvent = (PTMR_EVENT_PVT)pPublicEvent; + NV_STATUS status = NV_ERR_INVALID_REQUEST; + + if ((pEvent == NULL) || !tmrIsOSTimer(pTmr, (PTMR_EVENT)pEvent)) + { + return status; + } + + if (tmrEventOnList(pTmr, (PTMR_EVENT)pEvent)) + { + _tmrScanCallbackOSTimer(pTmr, pEvent); + status = tmrEventServiceOSTimerCallback_HAL(pGpu, pTmr, pPublicEvent); + } + + return status; +} + /** * @brief Provides an opportunity to register some IntrService during intrStateInit. * diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/kernel/gpu/timer/timer_ostimer.c nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/kernel/gpu/timer/timer_ostimer.c --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/kernel/gpu/timer/timer_ostimer.c 2023-10-25 20:21:23.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/kernel/gpu/timer/timer_ostimer.c 2024-03-05 22:13:53.000000000 +0000 @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 1993-2021 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 1993-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -93,15 +93,15 @@ * * @param[in] pTmr Pointer to Timer Object * @param[in] pEvent pointer to timer event information - * @param[in] absolute time in nano seconds + * @param[in] relative time in nano seconds * * @returns NV_ERR_INVALID_REQUEST failed to create timer */ -NV_STATUS tmrEventScheduleAbsOSTimer_OSTIMER +NV_STATUS tmrEventScheduleRelOSTimer_OSTIMER ( OBJTMR *pTmr, PTMR_EVENT pPublicEvent, - NvU64 timeNs + NvU64 timeRelNs ) { NV_STATUS status= NV_OK; @@ -114,7 +114,7 @@ return NV_ERR_INVALID_REQUEST; } - status = osStartNanoTimer(pGpu->pOsGpuInfo, pEvent->super.pOSTmrCBdata, timeNs); + status = osStartNanoTimer(pGpu->pOsGpuInfo, pEvent->super.pOSTmrCBdata, timeRelNs); if (status != NV_OK) { diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/kernel/gpu/uvm/access_cntr_buffer.c nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/kernel/gpu/uvm/access_cntr_buffer.c --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/kernel/gpu/uvm/access_cntr_buffer.c 2023-10-25 20:21:23.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/kernel/gpu/uvm/access_cntr_buffer.c 2024-03-05 22:13:53.000000000 +0000 @@ -30,6 +30,8 @@ #include "gpu/device/device.h" #include "kernel/rmapi/client.h" +#include "alloc/alloc_access_counter_buffer.h" + NV_STATUS accesscntrConstruct_IMPL ( @@ -38,7 +40,7 @@ RS_RES_ALLOC_PARAMS_INTERNAL *pParams ) { - NV_STATUS status; + NV_ACCESS_COUNTER_NOTIFY_BUFFER_ALLOC_PARAMS *pAllocParams = pParams->pAllocParams; OBJGPU *pGpu = GPU_RES_GET_GPU(pAccessCounterBuffer); OBJUVM *pUvm = GPU_GET_UVM(pGpu); @@ -58,17 +60,17 @@ NV_ASSERT_OR_RETURN(pUvm != NULL, NV_ERR_NOT_SUPPORTED); - status = uvmInitializeAccessCntrBuffer(pGpu, pUvm); - if (status != NV_OK) - { - NV_PRINTF(LEVEL_ERROR, - "Failed to initialize UVM Access Counters (status=0x%08x).\n", - status); - return status; - } + pAccessCounterBuffer->accessCounterIndex = (pAllocParams != NULL) ? pAllocParams->accessCounterIndex : 0; + + NV_CHECK_OR_RETURN(LEVEL_ERROR, + pAccessCounterBuffer->accessCounterIndex < pUvm->accessCounterBufferCount, + NV_ERR_INVALID_ARGUMENT); + NV_CHECK_OR_RETURN(LEVEL_ERROR, + pUvm->pAccessCounterBuffers[pAccessCounterBuffer->accessCounterIndex].pAccessCounterBuffer == NULL, + NV_ERR_INVALID_STATE); - pUvm->accessCntrBuffer.hAccessCntrBufferClient = pCallContext->pClient->hClient; - pUvm->accessCntrBuffer.hAccessCntrBufferObject = pCallContext->pResourceRef->hResource; + NV_ASSERT_OK_OR_RETURN(uvmInitializeAccessCntrBuffer(pGpu, pUvm, pAccessCounterBuffer)); + pUvm->pAccessCounterBuffers[pAccessCounterBuffer->accessCounterIndex].pAccessCounterBuffer = pAccessCounterBuffer; return NV_OK; } @@ -82,7 +84,11 @@ OBJGPU *pGpu = GPU_RES_GET_GPU(pAccessCounterBuffer); OBJUVM *pUvm = GPU_GET_UVM(pGpu); - (void) uvmTerminateAccessCntrBuffer(pGpu, pUvm); + NV_ASSERT(pUvm->pAccessCounterBuffers[pAccessCounterBuffer->accessCounterIndex].pAccessCounterBuffer == pAccessCounterBuffer); + + NV_ASSERT_OK(uvmTerminateAccessCntrBuffer(pGpu, pUvm, pAccessCounterBuffer)); + + pUvm->pAccessCounterBuffers[pAccessCounterBuffer->accessCounterIndex].pAccessCounterBuffer = NULL; } NV_STATUS @@ -96,7 +102,6 @@ { RmClient *pClient = dynamicCast(pCallContext->pClient, RmClient); OBJGPU *pGpu; - OBJUVM *pUvm; NV_STATUS rmStatus = NV_OK; NvBool bBroadcast = NV_TRUE; NvBool bKernel; @@ -104,7 +109,6 @@ pGpu = CliGetGpuFromContext(pCpuMapping->pContextRef, &bBroadcast); NV_ASSERT_OR_RETURN(pGpu != NULL, NV_ERR_INVALID_ARGUMENT); gpuSetThreadBcState(pGpu, bBroadcast); - pUvm = GPU_GET_UVM(pGpu); rmStatus = rmapiValidateKernelMapping(rmclientGetCachedPrivilege(pClient), pCpuMapping->flags, @@ -114,14 +118,13 @@ pCpuMapping->processId = osGetCurrentProcess(); - rmStatus = memdescMap(pUvm->accessCntrBuffer.pUvmAccessCntrAllocMemDesc, + rmStatus = memdescMap(pAccessCounterBuffer->pUvmAccessCntrAllocMemDesc, 0, - pUvm->accessCntrBuffer.pUvmAccessCntrAllocMemDesc->Size, + pAccessCounterBuffer->pUvmAccessCntrAllocMemDesc->Size, bKernel, pCpuMapping->pPrivate->protect, &pCpuMapping->pLinearAddress, &pCpuMapping->pPrivate->pPriv); - pUvm->accessCntrBuffer.hAccessCntrBufferCpuMapping = pCpuMapping->pPrivate->pPriv; return rmStatus; } @@ -137,7 +140,6 @@ NV_STATUS rmStatus; RmClient *pClient = dynamicCast(pCallContext->pClient, RmClient); OBJGPU *pGpu; - OBJUVM *pUvm; NvBool bBroadcast = NV_TRUE; NvBool bKernel; @@ -145,19 +147,17 @@ NV_ASSERT_OR_RETURN(pGpu != NULL, NV_ERR_INVALID_ARGUMENT); gpuSetThreadBcState(pGpu, bBroadcast); - pUvm = GPU_GET_UVM(pGpu); - rmStatus = rmapiValidateKernelMapping(rmclientGetCachedPrivilege(pClient), pCpuMapping->flags, &bKernel); if (rmStatus != NV_OK) return rmStatus; - memdescUnmap(pUvm->accessCntrBuffer.pUvmAccessCntrAllocMemDesc, + memdescUnmap(pAccessCounterBuffer->pUvmAccessCntrAllocMemDesc, bKernel, pCpuMapping->processId, pCpuMapping->pLinearAddress, - pUvm->accessCntrBuffer.hAccessCntrBufferCpuMapping); + pCpuMapping->pPrivate->pPriv); return NV_OK; } @@ -173,8 +173,7 @@ { NV_ADDRESS_SPACE addrSpace; OBJGPU *pGpu = GPU_RES_GET_GPU(pAccessCounterBuffer); - OBJUVM *pUvm = GPU_GET_UVM(pGpu); - PMEMORY_DESCRIPTOR pMemDesc = pUvm->accessCntrBuffer.pUvmAccessCntrAllocMemDesc; + PMEMORY_DESCRIPTOR pMemDesc = pAccessCounterBuffer->pUvmAccessCntrAllocMemDesc; if (pMemDesc == NULL) return NV_ERR_INVALID_OBJECT; diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/kernel/gpu/uvm/access_cntr_buffer_ctrl.c nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/kernel/gpu/uvm/access_cntr_buffer_ctrl.c --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/kernel/gpu/uvm/access_cntr_buffer_ctrl.c 2023-10-25 20:21:23.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/kernel/gpu/uvm/access_cntr_buffer_ctrl.c 2024-03-05 22:13:53.000000000 +0000 @@ -40,7 +40,7 @@ OBJGPU *pGpu = GPU_RES_GET_GPU(pAccessCounterBuffer); OBJUVM *pUvm = GPU_GET_UVM(pGpu); - return uvmReadAccessCntrBufferGetPtr_HAL(pGpu, pUvm, &pGetParams->accessCntrBufferGetOffset); + return uvmReadAccessCntrBufferGetPtr_HAL(pGpu, pUvm, pAccessCounterBuffer->accessCounterIndex, &pGetParams->accessCntrBufferGetOffset); } NV_STATUS @@ -53,7 +53,7 @@ OBJGPU *pGpu = GPU_RES_GET_GPU(pAccessCounterBuffer); OBJUVM *pUvm = GPU_GET_UVM(pGpu); - return uvmWriteAccessCntrBufferGetPtr_HAL(pGpu, pUvm, pGetParams->accessCntrBufferGetValue); + return uvmWriteAccessCntrBufferGetPtr_HAL(pGpu, pUvm, pAccessCounterBuffer->accessCounterIndex, pGetParams->accessCntrBufferGetValue); } NV_STATUS @@ -66,7 +66,7 @@ OBJGPU *pGpu = GPU_RES_GET_GPU(pAccessCounterBuffer); OBJUVM *pUvm = GPU_GET_UVM(pGpu); - return uvmReadAccessCntrBufferPutPtr_HAL(pGpu, pUvm, &pGetParams->accessCntrBufferPutOffset); + return uvmReadAccessCntrBufferPutPtr_HAL(pGpu, pUvm, pAccessCounterBuffer->accessCounterIndex, &pGetParams->accessCntrBufferPutOffset); } NV_STATUS @@ -76,10 +76,7 @@ NVC365_CTRL_ACCESS_CNTR_BUFFER_GET_SIZE_PARAMS *pGetParams ) { - OBJGPU *pGpu = GPU_RES_GET_GPU(pAccessCounterBuffer); - OBJUVM *pUvm = GPU_GET_UVM(pGpu); - - pGetParams->accessCntrBufferSize = pUvm->accessCntrBuffer.accessCntrBufferSize; + pGetParams->accessCntrBufferSize = pAccessCounterBuffer->pUvmAccessCntrAllocMemDesc->Size; return NV_OK; } @@ -114,11 +111,11 @@ if (pGetParams->enable) { - return uvmEnableAccessCntr_HAL(pGpu, pUvm, NV_FALSE); + return uvmEnableAccessCntr_HAL(pGpu, pUvm, pAccessCounterBuffer->accessCounterIndex, NV_FALSE); } else { - return uvmDisableAccessCntr_HAL(pGpu, pUvm, NV_FALSE); + return uvmDisableAccessCntr_HAL(pGpu, pUvm, pAccessCounterBuffer->accessCounterIndex, NV_FALSE); } } @@ -155,13 +152,14 @@ OBJUVM *pUvm = GPU_GET_UVM(pGpu); return uvmGetAccessCntrRegisterMappings_HAL(pGpu, pUvm, - &pParams->pAccessCntrBufferGet, - &pParams->pAccessCntrBufferPut, - &pParams->pAccessCntrBufferFull, - &pParams->pHubIntr, - &pParams->pHubIntrEnSet, - &pParams->pHubIntrEnClear, - &pParams->accessCntrMask); + pAccessCounterBuffer->accessCounterIndex, + &pParams->pAccessCntrBufferGet, + &pParams->pAccessCntrBufferPut, + &pParams->pAccessCntrBufferFull, + &pParams->pHubIntr, + &pParams->pHubIntrEnSet, + &pParams->pHubIntrEnClear, + &pParams->accessCntrMask); } NV_STATUS @@ -174,7 +172,7 @@ OBJGPU *pGpu = GPU_RES_GET_GPU(pAccessCounterBuffer); OBJUVM *pUvm = GPU_GET_UVM(pGpu); - return uvmReadAccessCntrBufferFullPtr_HAL(pGpu, pUvm, &pParams->fullFlag); + return uvmReadAccessCntrBufferFullPtr_HAL(pGpu, pUvm, pAccessCounterBuffer->accessCounterIndex, &pParams->fullFlag); } NV_STATUS @@ -187,7 +185,7 @@ OBJGPU *pGpu = GPU_RES_GET_GPU(pAccessCounterBuffer); OBJUVM *pUvm = GPU_GET_UVM(pGpu); - NV_STATUS status = uvmResetAccessCntrBuffer_HAL(pGpu, pUvm, pParams->counterType); + NV_STATUS status = uvmResetAccessCntrBuffer_HAL(pGpu, pUvm, pAccessCounterBuffer->accessCounterIndex, pParams->counterType); if (status == NV_OK) { pParams->resetFlag = NV_TRUE; @@ -212,17 +210,20 @@ NvU32 cmd = pParams->cmd; if (cmd & NVC365_CTRL_ACCESS_COUNTER_SET_MIMC_GRANULARITY) - uvmAccessCntrSetGranularity_HAL(pGpu, pUvm, MIMC, pParams->mimcGranularity); + uvmAccessCntrSetGranularity_HAL(pGpu, pUvm, pAccessCounterBuffer->accessCounterIndex, + MIMC, pParams->mimcGranularity); if (cmd & NVC365_CTRL_ACCESS_COUNTER_SET_MOMC_GRANULARITY) - uvmAccessCntrSetGranularity_HAL(pGpu, pUvm, MOMC, pParams->momcGranularity); + uvmAccessCntrSetGranularity_HAL(pGpu, pUvm, pAccessCounterBuffer->accessCounterIndex, + MOMC, pParams->momcGranularity); if (cmd & NVC365_CTRL_ACCESS_COUNTER_SET_MIMC_LIMIT) - uvmAccessCntrSetCounterLimit_HAL(pGpu, pUvm, + uvmAccessCntrSetCounterLimit_HAL(pGpu, pUvm, pAccessCounterBuffer->accessCounterIndex, NVC365_CTRL_ACCESS_COUNTER_MIMC_LIMIT, pParams->mimcLimit); if (cmd & NVC365_CTRL_ACCESS_COUNTER_SET_MOMC_LIMIT) - uvmAccessCntrSetCounterLimit_HAL(pGpu, pUvm, + uvmAccessCntrSetCounterLimit_HAL(pGpu, pUvm, pAccessCounterBuffer->accessCounterIndex, NVC365_CTRL_ACCESS_COUNTER_MOMC_LIMIT, pParams->momcLimit); if (cmd & NVC365_CTRL_ACCESS_COUNTER_SET_THRESHOLD) - uvmAccessCntrSetThreshold_HAL(pGpu, pUvm, pParams->threshold); + uvmAccessCntrSetThreshold_HAL(pGpu, pUvm, pAccessCounterBuffer->accessCounterIndex, + pParams->threshold); return NV_OK; } @@ -246,6 +247,7 @@ } status = uvmAccessCntrBufferRegister(pGpu, pUvm, + pParams->accessCounterIndex, pParams->bufferSize, pParams->bufferPteArray); return status; @@ -254,41 +256,15 @@ NV_STATUS subdeviceCtrlCmdInternalUvmUnregisterAccessCntrBuffer_IMPL ( - Subdevice *pSubdevice + Subdevice *pSubdevice, + NV2080_CTRL_INTERNAL_UVM_UNREGISTER_ACCESS_CNTR_BUFFER_PARAMS *pParams ) { NV_STATUS status; OBJGPU *pGpu = GPU_RES_GET_GPU(pSubdevice); OBJUVM *pUvm = GPU_GET_UVM(pGpu); - status = uvmAccessCntrBufferUnregister(pGpu, pUvm); + status = uvmAccessCntrBufferUnregister(pGpu, pUvm, pParams->accessCounterIndex); return status; } - -NV_STATUS -subdeviceCtrlCmdInternalUvmServiceAccessCntrBuffer_IMPL -( - Subdevice *pSubdevice -) -{ - OBJGPU *pGpu = GPU_RES_GET_GPU(pSubdevice); - OBJUVM *pUvm = GPU_GET_UVM(pGpu); - - return uvmAccessCntrService_HAL(pGpu, pUvm); -} - -NV_STATUS -subdeviceCtrlCmdInternalUvmGetAccessCntrBufferSize_IMPL -( - Subdevice *pSubdevice, - NV2080_CTRL_INTERNAL_UVM_GET_ACCESS_CNTR_BUFFER_SIZE_PARAMS *pParams -) -{ - OBJGPU *pGpu = GPU_RES_GET_GPU(pSubdevice); - OBJUVM *pUvm = GPU_GET_UVM(pGpu); - - pParams->bufferSize = uvmGetAccessCounterBufferSize_HAL(pGpu, pUvm); - - return NV_OK; -} diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/kernel/gpu/uvm/arch/turing/uvm_tu102.c nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/kernel/gpu/uvm/arch/turing/uvm_tu102.c --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/kernel/gpu/uvm/arch/turing/uvm_tu102.c 2023-10-25 20:21:23.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/kernel/gpu/uvm/arch/turing/uvm_tu102.c 2024-03-05 22:13:54.000000000 +0000 @@ -25,6 +25,7 @@ #include "gpu/gpu.h" #include "gpu/mmu/kern_gmmu.h" #include "gpu/uvm/uvm.h" +#include "gpu/uvm/access_cntr_buffer.h" #include "kernel/gpu/intr/intr.h" #include "class/clc365.h" @@ -32,16 +33,100 @@ #include "published/turing/tu102/dev_access_counter.h" #include "published/turing/tu102/dev_vm.h" +NvU32 +uvmGetRegOffsetAccessCntrBufferPut_TU102 +( + OBJUVM *pUvm, + NvU32 accessCounterIndex +) +{ + NV_ASSERT(accessCounterIndex == 0); + + return NV_VIRTUAL_FUNCTION_PRIV_ACCESS_COUNTER_NOTIFY_BUFFER_PUT; +} + +NvU32 +uvmGetRegOffsetAccessCntrBufferGet_TU102 +( + OBJUVM *pUvm, + NvU32 accessCounterIndex +) +{ + NV_ASSERT(accessCounterIndex == 0); + + return NV_VIRTUAL_FUNCTION_PRIV_ACCESS_COUNTER_NOTIFY_BUFFER_GET; +} + +NvU32 +uvmGetRegOffsetAccessCntrBufferHi_TU102 +( + OBJUVM *pUvm, + NvU32 accessCounterIndex +) +{ + NV_ASSERT(accessCounterIndex == 0); + + return NV_VIRTUAL_FUNCTION_PRIV_ACCESS_COUNTER_NOTIFY_BUFFER_HI; +} + +NvU32 +uvmGetRegOffsetAccessCntrBufferLo_TU102 +( + OBJUVM *pUvm, + NvU32 accessCounterIndex +) +{ + NV_ASSERT(accessCounterIndex == 0); + + return NV_VIRTUAL_FUNCTION_PRIV_ACCESS_COUNTER_NOTIFY_BUFFER_LO; +} + +NvU32 +uvmGetRegOffsetAccessCntrBufferConfig_TU102 +( + OBJUVM *pUvm, + NvU32 accessCounterIndex +) +{ + NV_ASSERT(accessCounterIndex == 0); + + return NV_VIRTUAL_FUNCTION_PRIV_ACCESS_COUNTER_CONFIG; +} + +NvU32 +uvmGetRegOffsetAccessCntrBufferInfo_TU102 +( + OBJUVM *pUvm, + NvU32 accessCounterIndex +) +{ + NV_ASSERT(accessCounterIndex == 0); + + return NV_VIRTUAL_FUNCTION_PRIV_ACCESS_COUNTER_NOTIFY_BUFFER_INFO; +} + +NvU32 +uvmGetRegOffsetAccessCntrBufferSize_TU102 +( + OBJUVM *pUvm, + NvU32 accessCounterIndex +) +{ + NV_ASSERT(accessCounterIndex == 0); + + return NV_VIRTUAL_FUNCTION_PRIV_ACCESS_COUNTER_NOTIFY_BUFFER_SIZE; +} + NV_STATUS uvmReadAccessCntrBufferPutPtr_TU102 ( - POBJGPU pGpu, - POBJUVM pUvm, - NvU32 *putOffset + OBJGPU *pGpu, + OBJUVM *pUvm, + NvU32 accessCounterIndex, + NvU32 *pPutOffset ) { - - *putOffset = GPU_VREG_RD32(pGpu, NV_VIRTUAL_FUNCTION_PRIV_ACCESS_COUNTER_NOTIFY_BUFFER_PUT); + *pPutOffset = GPU_VREG_RD32(pGpu, uvmGetRegOffsetAccessCntrBufferPut_HAL(pUvm, accessCounterIndex)); return NV_OK; } @@ -49,12 +134,13 @@ NV_STATUS uvmReadAccessCntrBufferGetPtr_TU102 ( - POBJGPU pGpu, - POBJUVM pUvm, - NvU32 *getOffset + OBJGPU *pGpu, + OBJUVM *pUvm, + NvU32 accessCounterIndex, + NvU32 *pGetOffset ) { - *getOffset = GPU_VREG_RD32(pGpu, NV_VIRTUAL_FUNCTION_PRIV_ACCESS_COUNTER_NOTIFY_BUFFER_GET); + *pGetOffset = GPU_VREG_RD32(pGpu, uvmGetRegOffsetAccessCntrBufferGet_HAL(pUvm, accessCounterIndex)); return NV_OK; } @@ -62,20 +148,23 @@ NV_STATUS uvmWriteAccessCntrBufferGetPtr_TU102 ( - POBJGPU pGpu, - POBJUVM pUvm, - NvU32 getPtrValue + OBJGPU *pGpu, + OBJUVM *pUvm, + NvU32 accessCounterIndex, + NvU32 getPtrValue ) { - GPU_VREG_WR32(pGpu, NV_VIRTUAL_FUNCTION_PRIV_ACCESS_COUNTER_NOTIFY_BUFFER_GET, getPtrValue); + GPU_VREG_WR32(pGpu, uvmGetRegOffsetAccessCntrBufferGet_HAL(pUvm, accessCounterIndex), getPtrValue); + return NV_OK; } NV_STATUS uvmEnableAccessCntr_TU102 ( - POBJGPU pGpu, - POBJUVM pUvm, + OBJGPU *pGpu, + OBJUVM *pUvm, + NvU32 accessCounterIndex, NvBool bIsErrorRecovery ) { @@ -97,7 +186,7 @@ uvmEnableAccessCntrIntr_HAL(pGpu, pUvm, intr_all); } - GPU_VREG_FLD_WR_DRF_DEF(pGpu, _VIRTUAL_FUNCTION, _PRIV_ACCESS_COUNTER_NOTIFY_BUFFER_LO, _EN, _TRUE); + uvmProgramAccessCntrBufferEnabled_HAL(pGpu, pUvm, accessCounterIndex, NV_TRUE); return NV_OK; } @@ -105,15 +194,16 @@ NV_STATUS uvmGetAccessCntrRegisterMappings_TU102 ( - POBJGPU pGpu, - POBJUVM pUvm, + OBJGPU *pGpu, + OBJUVM *pUvm, + NvU32 accessCounterIndex, NvP64 *pAccessCntrBufferGet, NvP64 *pAccessCntrBufferPut, NvP64 *pAccessCntrBufferFull, NvP64 *pHubIntr, NvP64 *pHubIntrEnSet, NvP64 *pHubIntrEnClear, - NvU32 *accessCntrMask + NvU32 *pAccessCntrMask ) { Intr *pIntr = GPU_GET_INTR(pGpu); @@ -125,73 +215,92 @@ leafReg = NV_CTRL_INTR_GPU_VECTOR_TO_LEAF_REG(intrVector); leafBit = NV_CTRL_INTR_GPU_VECTOR_TO_LEAF_BIT(intrVector); - *pAccessCntrBufferGet = NvP64_PLUS_OFFSET(bar0Mapping, GPU_GET_VREG_OFFSET(pGpu, NV_VIRTUAL_FUNCTION_PRIV_ACCESS_COUNTER_NOTIFY_BUFFER_GET)); - *pAccessCntrBufferPut = NvP64_PLUS_OFFSET(bar0Mapping, GPU_GET_VREG_OFFSET(pGpu, NV_VIRTUAL_FUNCTION_PRIV_ACCESS_COUNTER_NOTIFY_BUFFER_PUT)); - *pAccessCntrBufferFull = NvP64_PLUS_OFFSET(bar0Mapping,GPU_GET_VREG_OFFSET(pGpu, NV_VIRTUAL_FUNCTION_PRIV_ACCESS_COUNTER_NOTIFY_BUFFER_INFO)); + *pAccessCntrBufferGet = NvP64_PLUS_OFFSET(bar0Mapping, GPU_GET_VREG_OFFSET(pGpu, uvmGetRegOffsetAccessCntrBufferGet_HAL(pUvm, accessCounterIndex))); + *pAccessCntrBufferPut = NvP64_PLUS_OFFSET(bar0Mapping, GPU_GET_VREG_OFFSET(pGpu, uvmGetRegOffsetAccessCntrBufferPut_HAL(pUvm, accessCounterIndex))); + *pAccessCntrBufferFull = NvP64_PLUS_OFFSET(bar0Mapping,GPU_GET_VREG_OFFSET(pGpu, uvmGetRegOffsetAccessCntrBufferInfo_HAL(pUvm, accessCounterIndex))); *pHubIntr = NvP64_PLUS_OFFSET(bar0Mapping, GPU_GET_VREG_OFFSET(pGpu, NV_VIRTUAL_FUNCTION_PRIV_CPU_INTR_LEAF(leafReg))); *pHubIntrEnSet = NvP64_PLUS_OFFSET(bar0Mapping, GPU_GET_VREG_OFFSET(pGpu, NV_VIRTUAL_FUNCTION_PRIV_CPU_INTR_LEAF_EN_SET(leafReg))); *pHubIntrEnClear = NvP64_PLUS_OFFSET(bar0Mapping, GPU_GET_VREG_OFFSET(pGpu, NV_VIRTUAL_FUNCTION_PRIV_CPU_INTR_LEAF_EN_CLEAR(leafReg))); - *accessCntrMask = NVBIT(leafBit); + *pAccessCntrMask = NVBIT(leafBit); + return NV_OK; } NV_STATUS uvmReadAccessCntrBufferFullPtr_TU102 ( - POBJGPU pGpu, - POBJUVM pUvm, - NvBool *fullFlag + OBJGPU *pGpu, + OBJUVM *pUvm, + NvU32 accessCounterIndex, + NvBool *pFullFlag ) { - NvU32 fullPtrValue; + NvU32 info = GPU_VREG_RD32(pGpu, uvmGetRegOffsetAccessCntrBufferInfo_HAL(pUvm, accessCounterIndex)); + + *pFullFlag = FLD_TEST_DRF(_VIRTUAL_FUNCTION, _PRIV_ACCESS_COUNTER_NOTIFY_BUFFER_INFO, _FULL, _TRUE, info); - fullPtrValue = GPU_VREG_RD32(pGpu, NV_VIRTUAL_FUNCTION_PRIV_ACCESS_COUNTER_NOTIFY_BUFFER_INFO); - if (fullPtrValue & NV_VIRTUAL_FUNCTION_PRIV_ACCESS_COUNTER_NOTIFY_BUFFER_INFO_FULL_TRUE) - { - *fullFlag = NV_TRUE; - } - else - { - *fullFlag = NV_FALSE; - } return NV_OK; } NV_STATUS -uvmAccessCntrSetThreshold_TU102(POBJGPU pGpu, POBJUVM pUvm, NvU32 threshold) +uvmAccessCntrSetThreshold_TU102 +( + OBJGPU *pGpu, + OBJUVM *pUvm, + NvU32 accessCounterIndex, + NvU32 threshold +) { + NvU32 regOffsetConfig = uvmGetRegOffsetAccessCntrBufferConfig_HAL(pUvm, accessCounterIndex); + NvU32 config = GPU_VREG_RD32(pGpu, regOffsetConfig); + + config = FLD_SET_DRF_NUM(_VIRTUAL_FUNCTION, _PRIV_ACCESS_COUNTER_CONFIG, _THRESHOLD, threshold, config); + GPU_VREG_WR32(pGpu, regOffsetConfig, config); - GPU_VREG_FLD_WR_DRF_NUM(pGpu, _VIRTUAL_FUNCTION_PRIV, _ACCESS_COUNTER_CONFIG, _THRESHOLD, threshold); return NV_OK; } // Note: This function returns zero for chips which do not support the access counter. -NvU32 uvmGetAccessCounterBufferSize_TU102(POBJGPU pGpu, POBJUVM pUvm) +NvU32 +uvmGetAccessCounterBufferSize_TU102 +( + OBJGPU *pGpu, + OBJUVM *pUvm, + NvU32 accessCounterIndex +) { - - return GPU_VREG_RD32(pGpu, NV_VIRTUAL_FUNCTION_PRIV_ACCESS_COUNTER_NOTIFY_BUFFER_SIZE) * + return GPU_VREG_RD32(pGpu, uvmGetRegOffsetAccessCntrBufferSize_HAL(pUvm, accessCounterIndex)) * NV_ACCESS_COUNTER_NOTIFY_BUF_SIZE; } NV_STATUS -uvmAccessCntrSetGranularity_TU102(POBJGPU pGpu, POBJUVM pUvm, ACCESS_CNTR_TYPE accessCntType, NvU32 granularity) +uvmAccessCntrSetGranularity_TU102 +( + OBJGPU *pGpu, + OBJUVM *pUvm, + NvU32 accessCounterIndex, + ACCESS_CNTR_TYPE accessCntType, + NvU32 granularity +) { + NvU32 regOffsetConfig = uvmGetRegOffsetAccessCntrBufferConfig_HAL(pUvm, accessCounterIndex); + NvU32 config = GPU_VREG_RD32(pGpu, regOffsetConfig); if (accessCntType == MIMC) { switch(granularity) { case NVC365_CTRL_ACCESS_COUNTER_GRANULARITY_64K: - GPU_VREG_FLD_WR_DRF_DEF(pGpu, _VIRTUAL_FUNCTION_PRIV, _ACCESS_COUNTER_CONFIG, _MIMC_GRANULARITY, _64K); + config = FLD_SET_DRF(_VIRTUAL_FUNCTION, _PRIV_ACCESS_COUNTER_CONFIG, _MIMC_GRANULARITY, _64K, config); break; case NVC365_CTRL_ACCESS_COUNTER_GRANULARITY_2M: - GPU_VREG_FLD_WR_DRF_DEF(pGpu, _VIRTUAL_FUNCTION_PRIV, _ACCESS_COUNTER_CONFIG, _MIMC_GRANULARITY, _2M); + config = FLD_SET_DRF(_VIRTUAL_FUNCTION, _PRIV_ACCESS_COUNTER_CONFIG, _MIMC_GRANULARITY, _2M, config); break; case NVC365_CTRL_ACCESS_COUNTER_GRANULARITY_16M: - GPU_VREG_FLD_WR_DRF_DEF(pGpu, _VIRTUAL_FUNCTION_PRIV, _ACCESS_COUNTER_CONFIG, _MIMC_GRANULARITY, _16M); + config = FLD_SET_DRF(_VIRTUAL_FUNCTION, _PRIV_ACCESS_COUNTER_CONFIG, _MIMC_GRANULARITY, _16M, config); break; case NVC365_CTRL_ACCESS_COUNTER_GRANULARITY_16G: - GPU_VREG_FLD_WR_DRF_DEF(pGpu, _VIRTUAL_FUNCTION_PRIV, _ACCESS_COUNTER_CONFIG, _MIMC_GRANULARITY, _16G); + config = FLD_SET_DRF(_VIRTUAL_FUNCTION, _PRIV_ACCESS_COUNTER_CONFIG, _MIMC_GRANULARITY, _16G, config); break; default: return NV_ERR_INVALID_ARGUMENT; @@ -202,16 +311,16 @@ switch(granularity) { case NVC365_CTRL_ACCESS_COUNTER_GRANULARITY_64K: - GPU_VREG_FLD_WR_DRF_DEF(pGpu, _VIRTUAL_FUNCTION_PRIV, _ACCESS_COUNTER_CONFIG, _MOMC_GRANULARITY, _64K); + config = FLD_SET_DRF(_VIRTUAL_FUNCTION, _PRIV_ACCESS_COUNTER_CONFIG, _MOMC_GRANULARITY, _64K, config); break; case NVC365_CTRL_ACCESS_COUNTER_GRANULARITY_2M: - GPU_VREG_FLD_WR_DRF_DEF(pGpu, _VIRTUAL_FUNCTION_PRIV, _ACCESS_COUNTER_CONFIG, _MOMC_GRANULARITY, _2M); + config = FLD_SET_DRF(_VIRTUAL_FUNCTION, _PRIV_ACCESS_COUNTER_CONFIG, _MOMC_GRANULARITY, _2M, config); break; case NVC365_CTRL_ACCESS_COUNTER_GRANULARITY_16M: - GPU_VREG_FLD_WR_DRF_DEF(pGpu, _VIRTUAL_FUNCTION_PRIV, _ACCESS_COUNTER_CONFIG, _MOMC_GRANULARITY, _16M); + config = FLD_SET_DRF(_VIRTUAL_FUNCTION, _PRIV_ACCESS_COUNTER_CONFIG, _MOMC_GRANULARITY, _16M, config); break; case NVC365_CTRL_ACCESS_COUNTER_GRANULARITY_16G: - GPU_VREG_FLD_WR_DRF_DEF(pGpu, _VIRTUAL_FUNCTION_PRIV, _ACCESS_COUNTER_CONFIG, _MOMC_GRANULARITY, _16G); + config = FLD_SET_DRF(_VIRTUAL_FUNCTION, _PRIV_ACCESS_COUNTER_CONFIG, _MOMC_GRANULARITY, _16G, config); break; default: return NV_ERR_INVALID_ARGUMENT; @@ -220,6 +329,8 @@ else return NV_ERR_INVALID_ARGUMENT; + GPU_VREG_WR32(pGpu, regOffsetConfig, config); + return NV_OK; } @@ -228,11 +339,12 @@ ( OBJGPU *pGpu, OBJUVM *pUvm, + NvU32 accessCounterIndex, NvU64 addr ) { - GPU_VREG_WR32(pGpu, NV_VIRTUAL_FUNCTION_PRIV_ACCESS_COUNTER_NOTIFY_BUFFER_HI, NvU64_HI32(addr)); - GPU_VREG_WR32(pGpu, NV_VIRTUAL_FUNCTION_PRIV_ACCESS_COUNTER_NOTIFY_BUFFER_LO, NvU64_LO32(addr)); + GPU_VREG_WR32(pGpu, uvmGetRegOffsetAccessCntrBufferHi_HAL(pUvm, accessCounterIndex), NvU64_HI32(addr)); + GPU_VREG_WR32(pGpu, uvmGetRegOffsetAccessCntrBufferLo_HAL(pUvm, accessCounterIndex), NvU64_LO32(addr)); } void @@ -240,37 +352,48 @@ ( OBJGPU *pGpu, OBJUVM *pUvm, + NvU32 accessCounterIndex, NvBool bEn ) { - GPU_VREG_FLD_WR_DRF_NUM(pGpu, _VIRTUAL_FUNCTION, _PRIV_ACCESS_COUNTER_NOTIFY_BUFFER_LO, _EN, bEn); + NvU32 regOffsetLo = uvmGetRegOffsetAccessCntrBufferLo_HAL(pUvm, accessCounterIndex); + NvU32 lo = GPU_VREG_RD32(pGpu, regOffsetLo); + + lo = FLD_SET_DRF_NUM(_VIRTUAL_FUNCTION, _PRIV_ACCESS_COUNTER_NOTIFY_BUFFER_LO, _EN, bEn, lo); + GPU_VREG_WR32(pGpu, regOffsetLo, lo); } NvBool uvmIsAccessCntrBufferEnabled_TU102 ( OBJGPU *pGpu, - OBJUVM *pUvm + OBJUVM *pUvm, + NvU32 accessCounterIndex ) { - return (NvBool) GPU_VREG_RD_DRF(pGpu, _VIRTUAL_FUNCTION, _PRIV_ACCESS_COUNTER_NOTIFY_BUFFER_LO, _EN); + NvU32 lo = GPU_VREG_RD32(pGpu, uvmGetRegOffsetAccessCntrBufferLo_HAL(pUvm, accessCounterIndex)); + + return FLD_TEST_DRF(_VIRTUAL_FUNCTION, _PRIV_ACCESS_COUNTER_NOTIFY_BUFFER_LO, _EN, _TRUE, lo); } NvBool uvmIsAccessCntrBufferPushed_TU102 ( OBJGPU *pGpu, - OBJUVM *pUvm + OBJUVM *pUvm, + NvU32 accessCounterIndex ) { - return GPU_VREG_FLD_TEST_DRF_DEF(pGpu, _VIRTUAL_FUNCTION, _PRIV_ACCESS_COUNTER_NOTIFY_BUFFER_INFO, _PUSHED, _TRUE); + NvU32 info = GPU_VREG_RD32(pGpu, uvmGetRegOffsetAccessCntrBufferInfo_HAL(pUvm, accessCounterIndex)); + + return FLD_TEST_DRF(_VIRTUAL_FUNCTION, _PRIV_ACCESS_COUNTER_NOTIFY_BUFFER_INFO, _PUSHED, _TRUE, info); } NV_STATUS uvmEnableAccessCntrIntr_TU102 ( - POBJGPU pGpu, - POBJUVM pUvm, + OBJGPU *pGpu, + OBJUVM *pUvm, NvU32 intrType ) { @@ -288,8 +411,8 @@ NV_STATUS uvmDisableAccessCntrIntr_TU102 ( - POBJGPU pGpu, - POBJUVM pUvm + OBJGPU *pGpu, + OBJUVM *pUvm ) { Intr *pIntr = GPU_GET_INTR(pGpu); @@ -302,18 +425,48 @@ NV_STATUS uvmAccessCntrService_TU102 ( - POBJGPU pGpu, - POBJUVM pUvm + OBJGPU *pGpu, + OBJUVM *pUvm ) { - NvU64 accessCntrAddress = 0; - PEVENTNOTIFICATION *ppEventNotification = NULL; + NvU32 i; - if (NV_OK == CliGetEventNotificationList(pUvm->accessCntrBuffer.hAccessCntrBufferClient, - pUvm->accessCntrBuffer.hAccessCntrBufferObject, NULL, &ppEventNotification) && ppEventNotification) + for (i = 0; i < pUvm->accessCounterBufferCount; i++) { - NV_ASSERT_OK_OR_RETURN(notifyEvents(pGpu, *ppEventNotification, NVC365_NOTIFIERS_ACCESS_COUNTER, - NvU64_HI32(accessCntrAddress), NvU64_LO32(accessCntrAddress), NV_OK, NV_OS_WRITE_THEN_AWAKEN)); + AccessCounterBuffer *pAccessCounterBuffer = pUvm->pAccessCounterBuffers[i].pAccessCounterBuffer; + EVENTNOTIFICATION **ppEventNotification; + + if (pAccessCounterBuffer == NULL) + continue; + + ppEventNotification = inotifyGetNotificationListPtr(staticCast(pAccessCounterBuffer, INotifier)); + + if (ppEventNotification == NULL) + continue; + + if (pUvm->accessCounterBufferCount > 1) + { + NvU32 get, put; + + NV_ASSERT_OK_OR_RETURN(uvmReadAccessCntrBufferGetPtr(pGpu, pUvm, pAccessCounterBuffer->accessCounterIndex, &get)); + NV_ASSERT_OK_OR_RETURN(uvmReadAccessCntrBufferPutPtr(pGpu, pUvm, pAccessCounterBuffer->accessCounterIndex, &put)); + + // + // We can't know which access counter buffer has the new entries, + // so we send out notifications for each non-empty buffer. + // This can generate extra notifications when interrupts for different counters + // arrive in rapid succession, so client doesn't update get pointer in time. + // + // We could remember the last known put pointer and compare it, but + // theoretically the buffer can wrap around while the interrupt is being handled by client + // + if (get == put) + continue; + } + + NV_ASSERT_OK(notifyEvents(pGpu, *ppEventNotification, NVC365_NOTIFIERS_ACCESS_COUNTER, + 0, 0, NV_OK, NV_OS_WRITE_THEN_AWAKEN)); } + return NV_OK; } diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/kernel/gpu/uvm/arch/volta/uvm_gv100.c nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/kernel/gpu/uvm/arch/volta/uvm_gv100.c --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/kernel/gpu/uvm/arch/volta/uvm_gv100.c 2023-10-25 20:21:23.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/kernel/gpu/uvm/arch/volta/uvm_gv100.c 2024-03-05 22:13:54.000000000 +0000 @@ -31,6 +31,7 @@ #include "gpu/gpu.h" #include "gpu/mmu/kern_gmmu.h" #include "gpu/uvm/uvm.h" +#include "gpu/uvm/access_cntr_buffer.h" #include "os/os.h" #include "gpu/mem_mgr/mem_mgr.h" #include "gpu/mem_mgr/mem_desc.h" @@ -45,7 +46,8 @@ uvmSetupAccessCntrBuffer_GV100 ( OBJGPU *pGpu, - OBJUVM *pUvm + OBJUVM *pUvm, + NvU32 accessCounterIndex ) { KernelBus *pKernelBus = GPU_GET_KERNEL_BUS(pGpu); @@ -59,21 +61,21 @@ return NV_OK; } - if (!pUvm->accessCntrBuffer.pUvmAccessCntrMemDesc) + if (!pUvm->pAccessCounterBuffers[accessCounterIndex].pUvmAccessCntrMemDesc) { return NV_ERR_INVALID_OBJECT_BUFFER; } - status = kbusMapCpuInvisibleBar2Aperture_HAL(pGpu, pKernelBus, pUvm->accessCntrBuffer.pUvmAccessCntrMemDesc, - &vaddr, pUvm->accessCntrBuffer.pUvmAccessCntrMemDesc->Size, 0, GPU_GFID_PF); + status = kbusMapCpuInvisibleBar2Aperture_HAL(pGpu, pKernelBus, pUvm->pAccessCounterBuffers[accessCounterIndex].pUvmAccessCntrMemDesc, + &vaddr, pUvm->pAccessCounterBuffers[accessCounterIndex].pUvmAccessCntrMemDesc->Size, 0, GPU_GFID_PF); if (status != NV_OK) { return status; } - pUvm->accessCntrBuffer.bar2UvmAccessCntrBufferAddr = vaddr; + pUvm->pAccessCounterBuffers[accessCounterIndex].bar2UvmAccessCntrBufferAddr = vaddr; - uvmProgramWriteAccessCntrBufferAddress_HAL(pGpu, pUvm, vaddr); - uvmProgramAccessCntrBufferEnabled_HAL(pGpu, pUvm, NV_FALSE); + uvmProgramWriteAccessCntrBufferAddress_HAL(pGpu, pUvm, accessCounterIndex, vaddr); + uvmProgramAccessCntrBufferEnabled_HAL(pGpu, pUvm, accessCounterIndex, NV_FALSE); return NV_OK; } @@ -83,6 +85,7 @@ ( OBJGPU *pGpu, OBJUVM *pUvm, + NvU32 accessCounterIndex, NvBool bIsErrorRecovery ) { @@ -103,7 +106,7 @@ bIsErrorRecovery = NV_TRUE; } - uvmProgramAccessCntrBufferEnabled_HAL(pGpu, pUvm, NV_FALSE); + uvmProgramAccessCntrBufferEnabled_HAL(pGpu, pUvm, accessCounterIndex, NV_FALSE); // // Check for any pending notifications which might be pending in pipe to ensure @@ -113,9 +116,9 @@ // bit to show up for all packets and then reset the buffer // gpuSetTimeout(pGpu, GPU_TIMEOUT_DEFAULT, &timeout, 0); - if (!uvmIsAccessCntrBufferEnabled_HAL(pGpu, pUvm)) + if (!uvmIsAccessCntrBufferEnabled_HAL(pGpu, pUvm, accessCounterIndex)) { - while (!uvmIsAccessCntrBufferPushed_HAL(pGpu, pUvm)) + while (!uvmIsAccessCntrBufferPushed_HAL(pGpu, pUvm, accessCounterIndex)) { if (gpuCheckTimeout(pGpu, &timeout) == NV_ERR_TIMEOUT) { @@ -134,13 +137,13 @@ goto done; // If PUT pointer is updated, wait for VALID packets to show up and reset the packets - uvmReadAccessCntrBufferPutPtr_HAL(pGpu, pUvm, &putPtr); - uvmReadAccessCntrBufferGetPtr_HAL(pGpu, pUvm, &getPtr); + uvmReadAccessCntrBufferPutPtr_HAL(pGpu, pUvm, accessCounterIndex, &putPtr); + uvmReadAccessCntrBufferGetPtr_HAL(pGpu, pUvm, accessCounterIndex, &getPtr); if (getPtr != putPtr) { MEMORY_DESCRIPTOR *pMemDesc = RMCFG_FEATURE_PLATFORM_GSP ? - pUvm->accessCntrBuffer.pUvmAccessCntrMemDesc : - pUvm->accessCntrBuffer.pUvmAccessCntrAllocMemDesc; + pUvm->pAccessCounterBuffers[accessCounterIndex].pUvmAccessCntrMemDesc : + pUvm->pAccessCounterBuffers[accessCounterIndex].pAccessCounterBuffer->pUvmAccessCntrAllocMemDesc; NvU8 *pAccessCntrBufferPage; NvU32 entriesPerPage = RM_PAGE_SIZE / NVC365_NOTIFY_BUF_SIZE; NvU32 pageSizeModBufSize = RM_PAGE_SIZE % NVC365_NOTIFY_BUF_SIZE; @@ -186,13 +189,13 @@ // Write get progress so far, all entries in [get, put) // are valid or will become valid. - uvmWriteAccessCntrBufferGetPtr_HAL(pGpu, pUvm, getPtr); + uvmWriteAccessCntrBufferGetPtr_HAL(pGpu, pUvm, accessCounterIndex, getPtr); return status; } } } - uvmWriteAccessCntrBufferGetPtr_HAL(pGpu, pUvm, getPtr); + uvmWriteAccessCntrBufferGetPtr_HAL(pGpu, pUvm, accessCounterIndex, getPtr); memdescUnmap(pMemDesc, NV_TRUE, osGetCurrentProcess(), pAddr, pPriv); } @@ -209,7 +212,12 @@ } NV_STATUS -uvmUnloadAccessCntrBuffer_GV100(OBJGPU *pGpu, OBJUVM *pUvm) +uvmUnloadAccessCntrBuffer_GV100 +( + OBJGPU *pGpu, + OBJUVM *pUvm, + NvU32 accessCounterIndex +) { KernelBus *pKernelBus = GPU_GET_KERNEL_BUS(pGpu); @@ -220,16 +228,21 @@ return NV_OK; } - uvmDisableAccessCntr_HAL(pGpu, pUvm, NV_FALSE); - kbusUnmapCpuInvisibleBar2Aperture_HAL(pGpu, pKernelBus, pUvm->accessCntrBuffer.pUvmAccessCntrMemDesc, - pUvm->accessCntrBuffer.bar2UvmAccessCntrBufferAddr, GPU_GFID_PF); - pUvm->accessCntrBuffer.bar2UvmAccessCntrBufferAddr = 0; + uvmDisableAccessCntr_HAL(pGpu, pUvm, accessCounterIndex, NV_FALSE); + kbusUnmapCpuInvisibleBar2Aperture_HAL(pGpu, pKernelBus, pUvm->pAccessCounterBuffers[accessCounterIndex].pUvmAccessCntrMemDesc, + pUvm->pAccessCounterBuffers[accessCounterIndex].bar2UvmAccessCntrBufferAddr, GPU_GFID_PF); + pUvm->pAccessCounterBuffers[accessCounterIndex].bar2UvmAccessCntrBufferAddr = 0; return NV_OK; } NV_STATUS -uvmDestroyAccessCntrBuffer_GV100(OBJGPU *pGpu, OBJUVM *pUvm) +uvmDestroyAccessCntrBuffer_GV100 +( + OBJGPU *pGpu, + OBJUVM *pUvm, + AccessCounterBuffer *pAccessCounterBuffer +) { if(pUvm == NULL) { @@ -243,19 +256,24 @@ return NV_OK; } - memdescFree(pUvm->accessCntrBuffer.pUvmAccessCntrAllocMemDesc); - memdescDestroy(pUvm->accessCntrBuffer.pUvmAccessCntrAllocMemDesc); + memdescFree(pAccessCounterBuffer->pUvmAccessCntrAllocMemDesc); + memdescDestroy(pAccessCounterBuffer->pUvmAccessCntrAllocMemDesc); - pUvm->accessCntrBuffer.pUvmAccessCntrAllocMemDesc = NULL; - pUvm->accessCntrBuffer.accessCntrBufferSize = 0; + pAccessCounterBuffer->pUvmAccessCntrAllocMemDesc = NULL; return NV_OK; } NV_STATUS -uvmInitAccessCntrBuffer_GV100(OBJGPU *pGpu, OBJUVM *pUvm) +uvmInitAccessCntrBuffer_GV100 +( + OBJGPU *pGpu, + OBJUVM *pUvm, + AccessCounterBuffer *pAccessCounterBuffer +) { NV_STATUS status; + NvU32 accessCntrBufferSize; MEMORY_DESCRIPTOR *pUvmAccessCntrBufferDesc; NvP64 pAddr; NvP64 pPriv; @@ -264,7 +282,6 @@ NvU32 accessCntrBufferAperture = 0; NvU32 accessCntrBufferAttr = 0; - NV2080_CTRL_INTERNAL_UVM_GET_ACCESS_CNTR_BUFFER_SIZE_PARAMS getSizeParams = {0}; // Return if guest RM is with no sriov if (IS_VIRTUAL_WITHOUT_SRIOV(pGpu) || @@ -273,26 +290,13 @@ return NV_OK; } - // Issue control to fetch buffer size from physical - status = pUvm->pRmApi->Control(pUvm->pRmApi, - pUvm->hClient, - pUvm->hSubdevice, - NV2080_CTRL_CMD_INTERNAL_UVM_GET_ACCESS_CNTR_BUFFER_SIZE, - &getSizeParams, - sizeof(getSizeParams)); - if (status != NV_OK) - { - return status; - } - - pUvm->accessCntrBuffer.accessCntrBufferSize = getSizeParams.bufferSize; - + accessCntrBufferSize = uvmGetAccessCounterBufferSize_HAL(pGpu, pUvm, pAccessCounterBuffer->accessCounterIndex); accessCntrBufferAperture = ADDR_SYSMEM; accessCntrBufferAttr = NV_MEMORY_CACHED; memdescOverrideInstLoc(DRF_VAL(_REG_STR_RM, _INST_LOC_4, _UVM_FAULT_BUFFER_REPLAYABLE, pGpu->instLocOverrides4), "UVM access counter", &accessCntrBufferAperture, &accessCntrBufferAttr); - status = memdescCreate(&pUvmAccessCntrBufferDesc, pGpu, pUvm->accessCntrBuffer.accessCntrBufferSize, 0, + status = memdescCreate(&pUvmAccessCntrBufferDesc, pGpu, accessCntrBufferSize, 0, NV_FALSE, accessCntrBufferAperture, accessCntrBufferAttr, MEMDESC_FLAGS_LOST_ON_SUSPEND); if (status != NV_OK) { @@ -333,13 +337,19 @@ memdescUnmap(pUvmAccessCntrBufferDesc, NV_TRUE, osGetCurrentProcess(), pAddr, pPriv); - pUvm->accessCntrBuffer.pUvmAccessCntrAllocMemDesc = pUvmAccessCntrBufferDesc; + pAccessCounterBuffer->pUvmAccessCntrAllocMemDesc = pUvmAccessCntrBufferDesc; return status; } NV_STATUS -uvmResetAccessCntrBuffer_GV100(OBJGPU *pGpu, OBJUVM *pUvm, NvU32 counterType) +uvmResetAccessCntrBuffer_GV100 +( + OBJGPU *pGpu, + OBJUVM *pUvm, + NvU32 accessCounterIndex, + NvU32 counterType +) { switch(counterType) { @@ -359,7 +369,14 @@ } NV_STATUS -uvmAccessCntrSetCounterLimit_GV100(OBJGPU *pGpu, OBJUVM *pUvm, NvU32 type, NvU32 limit) +uvmAccessCntrSetCounterLimit_GV100 +( + OBJGPU *pGpu, + OBJUVM *pUvm, + NvU32 accessCounterIndex, + NvU32 type, + NvU32 limit +) { if (type == NVC365_CTRL_ACCESS_COUNTER_MIMC_LIMIT) { diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/kernel/gpu/uvm/uvm.c nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/kernel/gpu/uvm/uvm.c --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/kernel/gpu/uvm/uvm.c 2023-10-25 20:21:23.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/kernel/gpu/uvm/uvm.c 2024-03-05 22:13:54.000000000 +0000 @@ -24,6 +24,8 @@ #include "core/core.h" #include "gpu/gpu.h" #include "gpu/uvm/uvm.h" +#include "gpu/uvm/access_cntr_buffer.h" +#include "gpu/mem_sys/kern_mem_sys.h" #include "nvRmReg.h" #include "rmapi/control.h" #include "rmapi/rmapi_utils.h" @@ -34,12 +36,14 @@ /** * @brief Send the request to set up the buffer to physical RM. - * - * @param pGpu - * @param pUvm */ static NV_STATUS -_uvmSetupAccessCntrBuffer(OBJGPU *pGpu, OBJUVM *pUvm) +_uvmSetupAccessCntrBuffer +( + OBJGPU *pGpu, + OBJUVM *pUvm, + AccessCounterBuffer *pAccessCounterBuffer +) { NvU32 bufferSize; NvU32 numBufferPages; @@ -47,12 +51,12 @@ NV_STATUS status = NV_OK; // Buffer was not allocated, nothing to do - if (pUvm->accessCntrBuffer.pUvmAccessCntrAllocMemDesc == NULL) + if (pAccessCounterBuffer->pUvmAccessCntrAllocMemDesc == NULL) { return NV_OK; } - bufferSize = pUvm->accessCntrBuffer.pUvmAccessCntrAllocMemDesc->Size; + bufferSize = pAccessCounterBuffer->pUvmAccessCntrAllocMemDesc->Size; numBufferPages = NV_ROUNDUP(bufferSize, RM_PAGE_SIZE) / RM_PAGE_SIZE; if (numBufferPages > NV_ARRAY_ELEMENTS(params.bufferPteArray)) @@ -60,11 +64,12 @@ return NV_ERR_BUFFER_TOO_SMALL; } - memdescGetPhysAddrs(pUvm->accessCntrBuffer.pUvmAccessCntrAllocMemDesc, + memdescGetPhysAddrs(pAccessCounterBuffer->pUvmAccessCntrAllocMemDesc, AT_GPU, 0, RM_PAGE_SIZE, numBufferPages, params.bufferPteArray); params.bufferSize = bufferSize; + params.accessCounterIndex = pAccessCounterBuffer->accessCounterIndex; status = pUvm->pRmApi->Control(pUvm->pRmApi, pUvm->hClient, @@ -82,21 +87,29 @@ * @param pUvm */ static NV_STATUS -_uvmUnloadAccessCntrBuffer(OBJGPU *pGpu, OBJUVM *pUvm) +_uvmUnloadAccessCntrBuffer +( + OBJGPU *pGpu, + OBJUVM *pUvm, + AccessCounterBuffer *pAccessCounterBuffer +) { + NV2080_CTRL_INTERNAL_UVM_UNREGISTER_ACCESS_CNTR_BUFFER_PARAMS params = {0}; NV_STATUS status; // Buffer was not allocated, nothing to do - if (pUvm->accessCntrBuffer.pUvmAccessCntrAllocMemDesc == NULL) + if (pAccessCounterBuffer->pUvmAccessCntrAllocMemDesc == NULL) { return NV_OK; } + params.accessCounterIndex = pAccessCounterBuffer->accessCounterIndex; + status = pUvm->pRmApi->Control(pUvm->pRmApi, pUvm->hClient, pUvm->hSubdevice, NV2080_CTRL_CMD_INTERNAL_UVM_UNREGISTER_ACCESS_CNTR_BUFFER, - NULL, 0); + ¶ms, sizeof(params)); return status; } @@ -116,6 +129,12 @@ status = rmapiutilAllocClientAndDeviceHandles(pUvm->pRmApi, pGpu, &pUvm->hClient, NULL, &pUvm->hSubdevice); + pUvm->accessCounterBufferCount = 1; + + pUvm->pAccessCounterBuffers = portMemAllocNonPaged(sizeof (*pUvm->pAccessCounterBuffers) * pUvm->accessCounterBufferCount); + NV_ASSERT_OR_RETURN(pUvm->pAccessCounterBuffers != NULL, NV_ERR_NO_MEMORY); + portMemSet(pUvm->pAccessCounterBuffers, 0, sizeof (*pUvm->pAccessCounterBuffers) * pUvm->accessCounterBufferCount); + return status; } @@ -128,6 +147,7 @@ void uvmStateDestroy_IMPL(OBJGPU *pGpu, OBJUVM *pUvm) { + portMemFree(pUvm->pAccessCounterBuffers); rmapiutilFreeClientAndDeviceHandles(pUvm->pRmApi, &pUvm->hClient, NULL, &pUvm->hSubdevice); } @@ -139,20 +159,25 @@ * @param pUvm */ NV_STATUS -uvmInitializeAccessCntrBuffer_IMPL(OBJGPU *pGpu, OBJUVM *pUvm) +uvmInitializeAccessCntrBuffer_IMPL +( + OBJGPU *pGpu, + OBJUVM *pUvm, + AccessCounterBuffer *pAccessCounterBuffer +) { NV_STATUS status; - status = uvmInitAccessCntrBuffer_HAL(pGpu, pUvm); + status = uvmInitAccessCntrBuffer_HAL(pGpu, pUvm, pAccessCounterBuffer); if (status != NV_OK) { return status; } - status = _uvmSetupAccessCntrBuffer(pGpu, pUvm); + status = _uvmSetupAccessCntrBuffer(pGpu, pUvm, pAccessCounterBuffer); if (status != NV_OK) { - (void) uvmDestroyAccessCntrBuffer_HAL(pGpu, pUvm); + (void) uvmDestroyAccessCntrBuffer_HAL(pGpu, pUvm, pAccessCounterBuffer); } return status; @@ -165,11 +190,16 @@ * @param pUvm */ NV_STATUS -uvmTerminateAccessCntrBuffer_IMPL(OBJGPU *pGpu, OBJUVM *pUvm) +uvmTerminateAccessCntrBuffer_IMPL +( + OBJGPU *pGpu, + OBJUVM *pUvm, + AccessCounterBuffer *pAccessCounterBuffer +) { NV_STATUS status; - status = _uvmUnloadAccessCntrBuffer(pGpu, pUvm); + status = _uvmUnloadAccessCntrBuffer(pGpu, pUvm, pAccessCounterBuffer); if (status != NV_OK) { NV_PRINTF(LEVEL_ERROR, @@ -177,7 +207,7 @@ status); } - status = uvmDestroyAccessCntrBuffer_HAL(pGpu, pUvm); + status = uvmDestroyAccessCntrBuffer_HAL(pGpu, pUvm, pAccessCounterBuffer); if (status != NV_OK) { NV_PRINTF(LEVEL_ERROR, @@ -195,8 +225,14 @@ * @param pUvm */ NV_STATUS -uvmAccessCntrBufferRegister_IMPL(OBJGPU *pGpu, OBJUVM *pUvm, - NvU32 bufferSize, NvU64 *pBufferPages) +uvmAccessCntrBufferRegister_IMPL +( + OBJGPU *pGpu, + OBJUVM *pUvm, + NvU32 accessCounterIndex, + NvU32 bufferSize, + NvU64 *pBufferPages +) { NV_STATUS status; MEMORY_DESCRIPTOR *pMemDesc; @@ -221,9 +257,9 @@ NV_ROUNDUP(bufferSize, RM_PAGE_SIZE) / RM_PAGE_SIZE, RM_PAGE_SIZE); - pUvm->accessCntrBuffer.pUvmAccessCntrMemDesc = pMemDesc; + pUvm->pAccessCounterBuffers[accessCounterIndex].pUvmAccessCntrMemDesc = pMemDesc; - status = uvmSetupAccessCntrBuffer_HAL(pGpu, pUvm); + status = uvmSetupAccessCntrBuffer_HAL(pGpu, pUvm, accessCounterIndex); if (status != NV_OK) { NV_PRINTF(LEVEL_ERROR, @@ -232,7 +268,7 @@ memdescDestroy(pMemDesc); - pUvm->accessCntrBuffer.pUvmAccessCntrMemDesc = NULL; + pUvm->pAccessCounterBuffers[accessCounterIndex].pUvmAccessCntrMemDesc = NULL; } return status; @@ -246,11 +282,16 @@ * @param pUvm */ NV_STATUS -uvmAccessCntrBufferUnregister_IMPL(OBJGPU *pGpu, OBJUVM *pUvm) +uvmAccessCntrBufferUnregister_IMPL +( + OBJGPU *pGpu, + OBJUVM *pUvm, + NvU32 accessCounterIndex +) { NV_STATUS status; - status = uvmUnloadAccessCntrBuffer_HAL(pGpu, pUvm); + status = uvmUnloadAccessCntrBuffer_HAL(pGpu, pUvm, accessCounterIndex); if (status != NV_OK) { NV_PRINTF(LEVEL_ERROR, @@ -258,9 +299,9 @@ status); } - memdescDestroy(pUvm->accessCntrBuffer.pUvmAccessCntrMemDesc); + memdescDestroy(pUvm->pAccessCounterBuffers[accessCounterIndex].pUvmAccessCntrMemDesc); - pUvm->accessCntrBuffer.pUvmAccessCntrMemDesc = NULL; + pUvm->pAccessCounterBuffers[accessCounterIndex].pUvmAccessCntrMemDesc = NULL; return NV_OK; } @@ -298,11 +339,7 @@ NV_ASSERT_OR_RETURN(pParams != NULL, 0); NV_ASSERT_OR_RETURN(pParams->engineIdx == MC_ENGINE_IDX_ACCESS_CNTR, 0); - NV_ASSERT_OK(pUvm->pRmApi->Control(pUvm->pRmApi, - pUvm->hClient, - pUvm->hSubdevice, - NV2080_CTRL_CMD_INTERNAL_UVM_SERVICE_ACCESS_CNTR_BUFFER, - NULL, 0)); + NV_ASSERT_OK(uvmAccessCntrService_HAL(pGpu, pUvm)); return 0; } diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/kernel/gpu_mgr/gpu_db.c nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/kernel/gpu_mgr/gpu_db.c --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/kernel/gpu_mgr/gpu_db.c 2023-10-25 20:21:24.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/kernel/gpu_mgr/gpu_db.c 2024-03-05 22:13:54.000000000 +0000 @@ -127,7 +127,7 @@ pNode->upstreamPciPortInfo.bus = pUpstreamPortPciInfo->bus; pNode->upstreamPciPortInfo.device = pUpstreamPortPciInfo->device; pNode->upstreamPciPortInfo.function = pUpstreamPortPciInfo->func; - pNode->upstreamPciPortInfo.bValid = pUpstreamPortPciInfo->valid; + pNode->upstreamPciPortInfo.bValid = pUpstreamPortPciInfo->valid; pNode->bShutdownState = NV_FALSE; diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/kernel/gpu_mgr/gpu_mgr.c nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/kernel/gpu_mgr/gpu_mgr.c --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/kernel/gpu_mgr/gpu_mgr.c 2023-10-25 20:21:24.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/kernel/gpu_mgr/gpu_mgr.c 2024-03-05 22:13:54.000000000 +0000 @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 1993-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 1993-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -35,6 +35,7 @@ #include "nvrm_registry.h" #include "nv_ref.h" #include "nvlimits.h" +#include "nv-firmware-registry.h" #include "kernel/gpu/intr/intr.h" #include "virtualization/hypervisor/hypervisor.h" @@ -42,10 +43,12 @@ #include "published/pcie_switch/pcie_switch_ref.h" #include "kernel/gpu/nvlink/kernel_nvlink.h" #include "gpu/mem_sys/kern_mem_sys.h" +#include "gpu/conf_compute/conf_compute.h" +#include "gpu/gpu_fabric_probe.h" // local static funcs static void gpumgrSetAttachInfo(OBJGPU *, GPUATTACHARG *); -static void gpumgrGetGpuHalFactor(NvU32 *pChipId0, NvU32 *pChipId1, RM_RUNTIME_VARIANT *pRmVariant, GPUATTACHARG *pAttachArg); +static void gpumgrGetGpuHalFactor(NvU32 *pChipId0, NvU32 *pChipId1, NvU32 *pSocChipId0, RM_RUNTIME_VARIANT *pRmVariant, GPUATTACHARG *pAttachArg); static NvBool _gpumgrGetPcieP2PCapsFromCache(NvU32 gpuMask, NvU8* pP2PWriteCapsStatus, NvU8* pP2PReadCapsStatus); static void @@ -122,6 +125,60 @@ return status; } +static NV_STATUS +_gpumgrDetermineConfComputeCapabilities +( + OBJGPUMGR *pGpuMgr, + OBJGPU *pGpu +) +{ + NvBool bCCFeatureEnabled = NV_FALSE; + ConfidentialCompute *pCC = GPU_GET_CONF_COMPUTE(pGpu); + bCCFeatureEnabled = (pCC != NULL) && + pCC->getProperty(pCC, PDB_PROP_CONFCOMPUTE_ENABLED); + + // First GPU + if (ONEBITSET(pGpuMgr->gpuAttachMask)) + { + pGpuMgr->ccCaps.bApmFeatureCapable = NV_FALSE; + pGpuMgr->ccCaps.bHccFeatureCapable = pGpu->getProperty(pGpu, PDB_PROP_GPU_CC_FEATURE_CAPABLE); + pGpuMgr->ccCaps.bCCFeatureEnabled = bCCFeatureEnabled; + pGpuMgr->ccCaps.bDevToolsModeEnabled = gpuIsCCDevToolsModeEnabled(pGpu); + + if (pGpuMgr->ccCaps.bDevToolsModeEnabled) + { + pGpuMgr->ccCaps.bAcceptClientRequest = NV_TRUE; + } + else + { + pGpuMgr->ccCaps.bAcceptClientRequest = NV_FALSE; + } + } + else + { + NV_ASSERT_OR_RETURN(pGpuMgr->ccCaps.bCCFeatureEnabled == + bCCFeatureEnabled, NV_ERR_INVALID_STATE); + if (pGpuMgr->ccCaps.bCCFeatureEnabled) + { + NV_ASSERT_OR_RETURN(pGpuMgr->ccCaps.bHccFeatureCapable == + pGpu->getProperty(pGpu, PDB_PROP_GPU_CC_FEATURE_CAPABLE), + NV_ERR_INVALID_STATE); + } + // + // If one of the GPUs is not Hopper CC capable, the system as a whole + // is not Hopper CC capable + // + pGpuMgr->ccCaps.bHccFeatureCapable &= + pGpu->getProperty(pGpu, PDB_PROP_GPU_CC_FEATURE_CAPABLE); + + NV_ASSERT_OR_RETURN(pGpuMgr->ccCaps.bDevToolsModeEnabled == + gpuIsCCDevToolsModeEnabled(pGpu), + NV_ERR_INVALID_STATE); + } + + return NV_OK; +} + // // ODB functions // @@ -708,6 +765,53 @@ *pIsVirtual = NV_FALSE; } +NvBool gpumgrGetRmFirmwareLogsEnabled +( + NvU32 enableFirmwareLogsRegVal +) +{ + // Check for logs + if ((enableFirmwareLogsRegVal == NV_REG_ENABLE_GPU_FIRMWARE_LOGS_ENABLE) +#if defined(DEBUG) || defined(DEVELOP) + || (enableFirmwareLogsRegVal == NV_REG_ENABLE_GPU_FIRMWARE_LOGS_ENABLE_ON_DEBUG) +#endif // defined(DEBUG) || defined(DEVELOP) + ) + { + return NV_TRUE; + } + + return NV_FALSE; +} + +void gpumgrGetRmFirmwarePolicy +( + NvU32 chipId, + NvU32 pmcBoot42, + NvBool bIsSoc, + NvU32 enableFirmwareRegVal, + NvBool *pbRequestFirmware, + NvBool *pbAllowFallbackToMonolithicRm +) +{ + NvBool bFirmwareCapable = NV_FALSE; + NvBool bEnableByDefault = NV_FALSE; + NvU32 regkeyFirmwareMode; + + regkeyFirmwareMode = + enableFirmwareRegVal & NV_REG_ENABLE_GPU_FIRMWARE_MODE_MASK; + *pbAllowFallbackToMonolithicRm = + !!(enableFirmwareRegVal & NV_REG_ENABLE_GPU_FIRMWARE_POLICY_ALLOW_FALLBACK); + + bFirmwareCapable = gpumgrIsDeviceRmFirmwareCapable(chipId, pmcBoot42, + bIsSoc, + &bEnableByDefault); + + *pbRequestFirmware = + (bFirmwareCapable && + ((regkeyFirmwareMode == NV_REG_ENABLE_GPU_FIRMWARE_MODE_ENABLED) || + (bEnableByDefault && (regkeyFirmwareMode != NV_REG_ENABLE_GPU_FIRMWARE_MODE_DISABLED)))); +} + static NvBool _gpumgrIsRmFirmwareCapableChip(NvU32 pmcBoot42) { return (DRF_VAL(_PMC, _BOOT_42, _ARCHITECTURE, pmcBoot42) >= NV_PMC_BOOT_42_ARCHITECTURE_TU100); @@ -726,6 +830,9 @@ static NvBool _gpumgrIsVgxRmFirmwareDefaultChip(NvU32 pmcBoot42) { + if (DRF_VAL(_PMC, _BOOT_42, _ARCHITECTURE, pmcBoot42) == NV_PMC_BOOT_42_ARCHITECTURE_GH100) + return NV_TRUE; + if (DRF_VAL(_PMC, _BOOT_42, _ARCHITECTURE, pmcBoot42) == NV_PMC_BOOT_42_ARCHITECTURE_AD100) return NV_TRUE; @@ -736,79 +843,104 @@ ( NvU16 devId, NvU32 pmcBoot42, + NvBool bIsSoc, NvBool *pbEnabledByDefault ) { - static const NvU16 defaultGspRmGpus[] = { - 0x1E37, // GFN - 0x1E38, // TU102 - 0x1EB4, // T4G - 0x1EB8, // T4 - 0x1EB9, // T4 - - 0x20B0, // A100 - 0x20B1, // A100 - 0x20B2, // A100 - 0x20B3, // A200 - 0x20B5, // A100 80GB - 0x20B6, // A100 - 0x20B7, // A30 - 0x20B8, // A100X SKU230/231 Roy-100 - 0x20B9, // A30X SKU205/206 Roy-30 - 0x20F0, // A100 - 0x20F1, // A100 - 0x20F2, // A100 - 0x2235, // A40 - 0x2236, // A10 SKU215 Pris-24 - 0x2237, // A10G SKU215 Pris-24 - 0x25B6, // A16 - 0x20F5, // A800-80 - 0x20F6, // A800-40 - - 0x26B5, // L40 - 0x26B8, // L40G - 0x26F5, // L40-CNX - 0x27B8, // L4 (both SKUs) - }; - NvU32 count = NV_ARRAY_ELEMENTS(defaultGspRmGpus); - NvU32 i; + NvBool bEnabledByDefault = NV_FALSE; + NvBool bFirmwareCapable = NV_TRUE; - *pbEnabledByDefault = NV_FALSE; + // SoC is treated as always firmware capable and not enabled by default + if (bIsSoc) + goto finish; if (!hypervisorIsVgxHyper() && !_gpumgrIsRmFirmwareCapableChip(pmcBoot42)) - return NV_FALSE; - else if (hypervisorIsVgxHyper() && !_gpumgrIsVgxRmFirmwareCapableChip(pmcBoot42)) - return NV_FALSE; - - if (!hypervisorIsVgxHyper() && _gpumgrIsRmFirmwareDefaultChip(pmcBoot42)) { - *pbEnabledByDefault = NV_TRUE; + bFirmwareCapable = NV_FALSE; + goto finish; } - else if (hypervisorIsVgxHyper() && _gpumgrIsVgxRmFirmwareDefaultChip(pmcBoot42)) + else if (hypervisorIsVgxHyper() && !_gpumgrIsVgxRmFirmwareCapableChip(pmcBoot42)) { - *pbEnabledByDefault = NV_TRUE; + bFirmwareCapable = NV_FALSE; + goto finish; } - if (!hypervisorIsVgxHyper() || RMCFG_FEATURE_PLATFORM_GSP) +#if NVCPU_IS_FAMILY_PPC + // Disable default enablement for GSP on PowerPC until it is fully tested + bEnabledByDefault = NV_FALSE; + goto finish; +#else { - for (i = 0; i < count; i++) + static const NvU16 defaultGspRmGpus[] = { + 0x1E37, // GFN + 0x1E38, // TU102 + 0x1EB4, // T4G + 0x1EB8, // T4 + 0x1EB9, // T4 + + 0x20B0, // A100 + 0x20B1, // A100 + 0x20B2, // A100 + 0x20B3, // A200 + 0x20B5, // A100 80GB + 0x20B6, // A100 + 0x20B7, // A30 + 0x20B8, // A100X SKU230/231 Roy-100 + 0x20B9, // A30X SKU205/206 Roy-30 + 0x20F0, // A100 + 0x20F1, // A100 + 0x20F2, // A100 + 0x2235, // A40 + 0x2236, // A10 SKU215 Pris-24 + 0x2237, // A10G SKU215 Pris-24 + 0x25B6, // A16 + 0x20F5, // A800-80 + 0x20F6, // A800-40 + 0x20FD, // A100T RoyB + + 0x26B5, // L40 + 0x26B8, // L40G + 0x26F5, // L40-CNX + 0x27B7, // L16 + 0x27B8, // L4 (both SKUs) + }; + + if (hypervisorIsVgxHyper() && _gpumgrIsVgxRmFirmwareDefaultChip(pmcBoot42)) + { + bEnabledByDefault = NV_TRUE; + } + else if (!hypervisorIsVgxHyper() && _gpumgrIsRmFirmwareDefaultChip(pmcBoot42)) + { + bEnabledByDefault = NV_TRUE; + } + else if (!hypervisorIsVgxHyper() || RMCFG_FEATURE_PLATFORM_GSP) { - if (defaultGspRmGpus[i] == devId) + for (NvU32 i = 0; i < NV_ARRAY_ELEMENTS(defaultGspRmGpus); i++) { - *pbEnabledByDefault = NV_TRUE; - break; + if (defaultGspRmGpus[i] == devId) + { + bEnabledByDefault = NV_TRUE; + break; + } } } } +#endif - if (*pbEnabledByDefault) +finish: + if (pbEnabledByDefault != NULL) { - NV_PRINTF(LEVEL_INFO, - "DevId 0x%x is GSP-RM enabled by default\n", - devId); + *pbEnabledByDefault = bEnabledByDefault; + + if (bEnabledByDefault) + { + NV_PRINTF(LEVEL_INFO, + "DevId 0x%x is GSP-RM enabled by default\n", + devId); + } } - return NV_TRUE; + return bFirmwareCapable; } static NvBool gpumgrCheckRmFirmwarePolicy @@ -822,24 +954,12 @@ if (!bRequestFwClientRm) return NV_FALSE; - NvU32 data; - if (!_gpumgrIsRmFirmwareCapableChip(pmcBoot42)) { NV_PRINTF(LEVEL_ERROR, "Disabling GSP offload -- GPU not supported\n"); return NV_FALSE; } - // Disable if RM registry override set - if (osReadRegistryDword(NULL, NV_REG_STR_RM_DISABLE_GSP_OFFLOAD, &data) == NV_OK) - { - if (data != NV_REG_STR_RM_DISABLE_GSP_OFFLOAD_FALSE) - { - NV_PRINTF(LEVEL_NOTICE, "Disabling GSP offload -- registry entry\n"); - return NV_FALSE; - } - } - return NV_TRUE; } @@ -855,6 +975,7 @@ ( NvU32 *pChipId0, NvU32 *pChipId1, + NvU32 *pSocChipId0, RM_RUNTIME_VARIANT *pRmVariant, GPUATTACHARG *pAttachArg ) @@ -862,17 +983,21 @@ NvBool isVirtual; NvBool isFwClient; - DEVICE_MAPPING gpuDevMapping = {0}; - gpuDevMapping.gpuNvAddr = pAttachArg->regBaseAddr; - gpuDevMapping.gpuNvLength = pAttachArg->regLength; - // get ChipId0 and ChipId1 if (pAttachArg->socDeviceArgs.specified) { - // This path is taken for T234D+ devices. - *pChipId0 = pAttachArg->socDeviceArgs.socChipId0; + + // iGPU has a PMC_BOOT_0, Display does not + if (pAttachArg->socDeviceArgs.bIsIGPU) + { + DEVICE_MAPPING *pGpuDevMapping = NULL; + pGpuDevMapping = &pAttachArg->socDeviceArgs.deviceMapping[DEVICE_INDEX_GPU]; + *pChipId0 = osDevReadReg032(/*pGpu=*/ NULL, pGpuDevMapping, NV_PMC_BOOT_0); + } + *pChipId1 = 0; + *pSocChipId0 = pAttachArg->socDeviceArgs.socChipId0; isVirtual = NV_FALSE; } else if (pAttachArg->bIsSOC) @@ -881,16 +1006,22 @@ *pChipId0 = pAttachArg->socChipId0; *pChipId1 = 0; + *pSocChipId0 = pAttachArg->socChipId0; isVirtual = NV_FALSE; } else { + DEVICE_MAPPING gpuDevMapping = {0}; + gpuDevMapping.gpuNvAddr = pAttachArg->regBaseAddr; + gpuDevMapping.gpuNvLength = pAttachArg->regLength; + // // PMC_BOOT_42 register is added above G94+ chips which is internal to NVIDIA // Earlier we used PMC_BOOT_0 as Internal ID which is now exposed to customers // *pChipId0 = osDevReadReg032(/*pGpu=*/ NULL, &gpuDevMapping, NV_PMC_BOOT_0); *pChipId1 = osDevReadReg032(/*pGpu=*/ NULL, &gpuDevMapping, NV_PMC_BOOT_42); + *pSocChipId0 = 0; gpumgrGetGpuHalFactorOfVirtual(&isVirtual, pAttachArg); } @@ -927,12 +1058,13 @@ RM_RUNTIME_VARIANT rmVariant; NvU32 chipId0; // 32-bit chipId (pmcBoot0 on GPU) NvU32 chipId1; // 32-bit chipId (pmcBoot42 on GPU) + NvU32 socChipId0; // 32-bit SOC chipId NvU32 hidrev, majorRev; - gpumgrGetGpuHalFactor(&chipId0, &chipId1, &rmVariant, pAttachArg); + gpumgrGetGpuHalFactor(&chipId0, &chipId1, &socChipId0, &rmVariant, pAttachArg); - hidrev = DRF_VAL(_PAPB_MISC, _GP_HIDREV, _CHIPID, chipId0); - majorRev = DRF_VAL(_PAPB_MISC, _GP_HIDREV, _MAJORREV, chipId0); + hidrev = DRF_VAL(_PAPB_MISC, _GP_HIDREV, _CHIPID, socChipId0); + majorRev = DRF_VAL(_PAPB_MISC, _GP_HIDREV, _MAJORREV, socChipId0); // WAR: The majorrev of t234 shows 0xa on fmodel instead of 0x4 if ((hidrev == 0x23) && (majorRev == 0xa)) @@ -956,7 +1088,7 @@ } // legacy chip-config Hal registration path - status = gpuBindHalLegacy(pGpu, chipId0, chipId1); + status = gpuBindHalLegacy(pGpu, chipId0, chipId1, socChipId0); if (status != NV_OK) { objDelete(pGpu); @@ -1074,6 +1206,9 @@ // Add entry into system partition topo array gpumgrAddSystemMIGInstanceTopo(pAttachArg->nvDomainBusDeviceFunc); + // Determine conf compute params + NV_ASSERT_OK_OR_RETURN(_gpumgrDetermineConfComputeCapabilities(pGpuMgr, pGpu)); + if (!IS_GSP_CLIENT(pGpu)) pGpuMgr->gpuMonolithicRmMask |= NVBIT(gpuInstance); @@ -1344,7 +1479,7 @@ { NvU32 idx; NvU32 maxIdx; - // This path is taken for T234D+ SOC devices. + // This path is taken for Tegra Display and iGPU // // TODO: This existing field is specifically used to safeguard @@ -1382,7 +1517,7 @@ pGpu->idInfo.PCIDeviceID = pAttachArg->socId; pGpu->idInfo.PCISubDeviceID = pAttachArg->socSubId; pGpu->busInfo.iovaspaceId = pAttachArg->iovaspaceId; - if (RMCFG_FEATURE_PLATFORM_MODS || RMCFG_FEATURE_PLATFORM_WINDOWS_LDDM) + if (RMCFG_FEATURE_PLATFORM_MODS) { NV_ASSERT(sizeof(pGpu->deviceMappings) == sizeof(pAttachArg->socDeviceMappings)); portMemCopy(pGpu->deviceMappings, sizeof(pGpu->deviceMappings), pAttachArg->socDeviceMappings, sizeof(pGpu->deviceMappings)); @@ -1920,7 +2055,7 @@ return NV_ERR_INVALID_ARGUMENT; } - LOCK_ASSERT_AND_RETURN(rmGpuLockIsOwner()); + NV_ASSERT_OR_RETURN(gpumgrIsSafeToReadGpuInfo(), NV_ERR_INVALID_LOCK_STATE); // // We have a valid gpuInstance, so now let's get the corresponding @@ -1950,7 +2085,28 @@ { pGpuInfo->gpuFlags |= DRF_NUM(0000, _CTRL_GPU_ID_INFO, _ATS_ENABLED, NV0000_CTRL_GPU_ID_INFO_ATS_ENABLED_TRUE); - pGpuInfo->numaId = pGpu->numaNodeId; + + if (gpuIsSelfHosted(pGpu) && IS_MIG_IN_USE(pGpu)) + { + CALL_CONTEXT *pCallContext = resservGetTlsCallContext(); + RmCtrlParams *pRmCtrlParams = pCallContext->pControlParams; + KernelMIGManager *pKernelMIGManager = GPU_GET_KERNEL_MIG_MANAGER(pGpu); + MIG_INSTANCE_REF ref; + NvU32 swizzId; + + if (kmigmgrGetInstanceRefFromClient(pGpu, pKernelMIGManager, pRmCtrlParams->hClient, &ref) == NV_OK) + { + swizzId = ref.pKernelMIGGpuInstance->swizzId; + if (GPU_GET_KERNEL_MEMORY_SYSTEM(pGpu)->memPartitionNumaInfo[swizzId].bInUse) + { + pGpuInfo->numaId = GPU_GET_KERNEL_MEMORY_SYSTEM(pGpu)->memPartitionNumaInfo[swizzId].numaNodeId; + } + } + } + else + { + pGpuInfo->numaId = pGpu->numaNodeId; + } } // is this gpu in use? @@ -2008,20 +2164,6 @@ pGpuInfo->gpuInstance = pGpuInfoV2.gpuInstance; pGpuInfo->numaId = pGpuInfoV2.numaId; - // If we get a non-NULL szName parameter, let os-dependent code - // fill it in from information we already have. - if (NvP64_VALUE(pGpuInfo->szName) != NULL) - { - status = osDeviceClassToDeviceName(pGpuInfo->deviceInstance, - NvP64_VALUE(pGpuInfo->szName)); - if (status != NV_OK) - { - NV_PRINTF(LEVEL_ERROR, - "gpumgrGetGpuInfo: deviceInstance to szName translation failed\n"); - return status; - } - } - return status; } @@ -2272,7 +2414,7 @@ // intrStateInit. To avoid calling in too early, check that the // interrupt table is initialized. // - if (pIntr->pIntrTable == NULL) + if (vectIsEmpty(&pIntr->intrTable)) { continue; } @@ -2297,9 +2439,75 @@ NvU32 *pPinsetIn ) { - *pPinsetOut = 0; - *pPinsetIn = 0; - return NV_OK; + + OBJSYS *pSys = SYS_GET_INSTANCE(); + OBJGPUMGR *pGpuMgr = SYS_GET_GPUMGR(pSys); + OBJGPUGRP *pGpuGrp = NULL; + NvU32 pinsetIndex = 0, childPinset = drPinSet_None; + NvU32 i; + NvU32 gpuInstance = pGpu->gpuInstance; + NV_STATUS rmStatus; + + *pPinsetOut = drPinSet_None; + *pPinsetIn = drPinSet_None; + + if (pPeerGpu == NULL) + { + pGpuGrp = gpumgrGetGpuGrpFromGpu(pGpu); + NV_ASSERT_OR_RETURN(pGpuGrp != NULL, NV_ERR_INVALID_DATA); + + for (i = 0; i < NV2080_MAX_SUBDEVICES; i++) + { + if (pGpuGrp->SliLinkOrder[i].gpuInstance == gpuInstance) + { + break; + } + } + + if (i == NV2080_MAX_SUBDEVICES) + { + *pPinsetOut = 0; + *pPinsetIn = 0; + } + else + { + *pPinsetOut = pGpuGrp->SliLinkOrder[i].ChildDrPort; + *pPinsetIn = pGpuGrp->SliLinkOrder[i].ParentDrPort; + } + + return NV_OK; + } + else + { + NvU32 childPinsetIndex; + + for (pinsetIndex = 0; pinsetIndex < DR_PINSET_COUNT; pinsetIndex++) + { + if (!FLD_TEST_DRF(_SLILINK, _ROUTE, _INPUT, _PASSED, + pGpuMgr->gpuSliLinkRoute[pGpuMgr->gpuBridgeType][gpuInstance][pPeerGpu->gpuInstance][pinsetIndex])) + { + continue; + } + + childPinset = DRF_VAL(_SLILINK, _ROUTE, _INPUT_CHILD_PORT, + pGpuMgr->gpuSliLinkRoute[pGpuMgr->gpuBridgeType][gpuInstance][pPeerGpu->gpuInstance][pinsetIndex]); + + rmStatus = gpumgrPinsetToPinsetTableIndex(childPinset, &childPinsetIndex); + if (rmStatus != NV_OK) + { + return rmStatus; + } + if (!FLD_TEST_DRF(_SLILINK, _ROUTE, _OUTPUT, _PASSED, + pGpuMgr->gpuSliLinkRoute[pGpuMgr->gpuBridgeType][pPeerGpu->gpuInstance][gpuInstance][childPinsetIndex])) + { + continue; + } + *pPinsetOut |= childPinset; + *pPinsetIn |= NVBIT(pinsetIndex); + } + return ((*pPinsetOut != drPinSet_None) && (*pPinsetIn != drPinSet_None)) ? NV_OK : NV_ERR_INVALID_ARGUMENT; + } + } // @@ -3016,6 +3224,152 @@ } /*! + * @brief Get nvlink bandwidth mode + * + * @return mode reduced bandwidth mode. + */ +NvU8 +gpumgrGetGpuNvlinkBwMode_IMPL(void) +{ + OBJSYS *pSys = SYS_GET_INSTANCE(); + OBJGPUMGR *pGpuMgr = SYS_GET_GPUMGR(pSys); + + return pGpuMgr->nvlinkBwMode; +} + +/*! + * @brief Set nvlink bandwidth mode from Registry + * + * @param[in] pGpu reference of OBJGPU + * + */ +void +gpumgrSetGpuNvlinkBwModeFromRegistry_IMPL +( + OBJGPU *pGpu +) +{ + OBJSYS *pSys = SYS_GET_INSTANCE(); + OBJGPUMGR *pGpuMgr = SYS_GET_GPUMGR(pSys); + const char *pStrChar; + NvU32 strLength = 32; + NvU8 pStr[32]; + + // + // An RM client can set NVLink BW mode using + // NV0000_CTRL_CMD_GPU_SET_NVLINK_BW_MODE control call. + // If the value is not default i.e. `GPU_NVLINK_BW_MODE_FULL`, then skip. + // + if (pGpuMgr->nvlinkBwMode != GPU_NVLINK_BW_MODE_FULL) + { + return; + } + + // sysInitRegistryOverrides should pass in valid pGpu + NV_ASSERT (pGpu != NULL); + + if (osReadRegistryString(pGpu, NV_REG_STR_RM_NVLINK_BW, pStr, &strLength) != NV_OK) + { + goto out; + } + + pStrChar = (const char *)pStr; + strLength = portStringLength(pStrChar); + if (portStringCompare(pStrChar, "OFF", strLength) == 0) + { + pGpuMgr->nvlinkBwMode = GPU_NVLINK_BW_MODE_OFF; + } + else if (portStringCompare(pStrChar, "MIN", strLength) == 0) + { + pGpuMgr->nvlinkBwMode = GPU_NVLINK_BW_MODE_MIN; + } + else if (portStringCompare(pStrChar, "HALF", strLength) == 0) + { + pGpuMgr->nvlinkBwMode = GPU_NVLINK_BW_MODE_HALF; + } + else if (portStringCompare(pStrChar, "3QUARTER", strLength) == 0) + { + pGpuMgr->nvlinkBwMode = GPU_NVLINK_BW_MODE_3QUARTER; + } + +out: + NV_PRINTF(LEVEL_INFO, "nvlinkBwMode=%d\n", pGpuMgr->nvlinkBwMode); +} + +static NvBool +_gpumgrIsP2PObjectPresent(void) +{ + NvU32 attachedGpuCount; + NvU32 attachedGpuMask; + KernelBus *pKernelBus; + NV_STATUS rmStatus; + NvU32 gpuIndex; + OBJGPU *pGpu; + + rmStatus = gpumgrGetGpuAttachInfo(&attachedGpuCount, &attachedGpuMask); + if (rmStatus != NV_OK) + { + return NV_FALSE; + } + + gpuIndex = 0; + for(pGpu = gpumgrGetNextGpu(attachedGpuMask, &gpuIndex); + pGpu != NULL; + pGpu = gpumgrGetNextGpu(attachedGpuMask, &gpuIndex)) + { + pKernelBus = GPU_GET_KERNEL_BUS(pGpu); + if (pKernelBus->totalP2pObjectsAliveRefCount > 0) + { + return NV_TRUE; + } + } + + return NV_FALSE; +} + +/*! + * @brief Set nvlink bandwidth mode + * + * @param[in] mode nvlink bandwidth mode + * + * @return NV_OK on success, appropriate error on failure. + */ +NV_STATUS +gpumgrSetGpuNvlinkBwMode_IMPL +( + NvU8 mode +) +{ + OBJSYS *pSys = SYS_GET_INSTANCE(); + OBJGPUMGR *pGpuMgr = SYS_GET_GPUMGR(pSys); + NV_STATUS status; + + if (mode == pGpuMgr->nvlinkBwMode) + { + return NV_OK; + } + + if (_gpumgrIsP2PObjectPresent()) + { + return NV_ERR_IN_USE; + } + + if (mode > GPU_NVLINK_BW_MODE_3QUARTER) + { + return NV_ERR_INVALID_ARGUMENT; + } + + status = gpuFabricProbeSetBwMode(mode); + if (status != NV_OK) + { + return status; + } + + pGpuMgr->nvlinkBwMode = mode; + return NV_OK; +} + +/*! * @brief Adds an entry in the system partition topology save for the given GPU * ID. Note that this does not create any saved partition topology. * @@ -3522,3 +3876,58 @@ return pGpuMgr->gpuMonolithicRmMask == 0; } + +NvBool gpumgrIsSafeToReadGpuInfo(void) +{ + // + // A thread that tears down the GPU must own both the API lock for WRITE + // and all GPU locks. + // + // Conversely, if you hold the API lock (either READ or WRITE), or hold + // any GPU locks, you know that no GPUs will be freed from under you. + // + + // + // NOTE: Currently rmapiLockIsOwner() returns TRUE if you own the lock in + // either READ or WRITE modes + // + return rmapiLockIsOwner() || (rmGpuLocksGetOwnedMask() != 0); +} + +// +// Workaround for Bug 3809777. This is a HW bug happening in Ampere and +// Ada GPU's. For these GPU's, after device reset, CRS (Configuration Request +// Retry Status) is being released without waiting for GFW boot completion. +// MSI-X capability in the config space may be inconsistent when GFW boot +// is in progress, so this function checks if MSI-X is allowed. +// For Hopper and above, the CRS will be released after +// GFW boot completion, so the WAR is not needed. +// The bug will be exposed only when GPU is running inside guest in +// pass-through mode. +// +NvBool gpumgrIsDeviceMsixAllowed +( + RmPhysAddr bar0BaseAddr, + NvU32 pmcBoot1, + NvU32 pmcBoot42 +) +{ + OBJSYS *pSys = SYS_GET_INSTANCE(); + OBJHYPERVISOR *pHypervisor = SYS_GET_HYPERVISOR(pSys); + NvU32 chipArch; + + if ((hypervisorGetHypervisorType(pHypervisor) == OS_HYPERVISOR_UNKNOWN) || + !FLD_TEST_DRF(_PMC, _BOOT_1, _VGPU, _REAL, pmcBoot1)) + { + return NV_TRUE; + } + + chipArch = DRF_VAL(_PMC, _BOOT_42, _ARCHITECTURE, pmcBoot42); + if ((chipArch != NV_PMC_BOOT_42_ARCHITECTURE_AD100) && + (chipArch != NV_PMC_BOOT_42_ARCHITECTURE_GA100)) + { + return NV_TRUE; + } + + return gpuIsMsixAllowed_TU102(bar0BaseAddr); +} diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/kernel/gpu_mgr/gpu_mgr_sli.c nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/kernel/gpu_mgr/gpu_mgr_sli.c --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/kernel/gpu_mgr/gpu_mgr_sli.c 1970-01-01 00:00:00.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/kernel/gpu_mgr/gpu_mgr_sli.c 2024-03-05 22:13:54.000000000 +0000 @@ -0,0 +1,598 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2012-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +/***************************** HW State Routines ***************************\ +* * +* SLI specific GPU Manager functions * +* * +\***************************************************************************/ + +#include "core/system.h" +#include "core/thread_state.h" +#include "core/locks.h" +#include "os/os.h" +#include "gpu/mem_mgr/mem_mgr.h" +#include "kernel/gpu/intr/intr.h" +#include "kernel/gpu/rc/kernel_rc.h" +#include "kernel/gpu/mig_mgr/kernel_mig_manager.h" +#include "gpu/disp/kern_disp.h" +#include "gpu/mem_mgr/mem_desc.h" +#include "platform/sli/sli.h" +#include "nvpcie.h" +#include "nvhybridacpi.h" +#include "platform/platform.h" +#include "gpu_mgr/gpu_mgr.h" +#include "gpu_mgr/gpu_mgr_sli.h" +#include "gpu_mgr/gpu_group.h" +#include "kernel/gpu/nvlink/kernel_nvlink.h" +#include "kernel/gpu/rc/kernel_rc.h" + +#include "nvRmReg.h" + +#include "ctrl/ctrl0000/ctrl0000gpu.h" +#include "nvlimits.h" + +static NV_STATUS gpumgrStateInitialized(void); + +void +gpumgrDetectSliLinkFromGpus +( + NvBool bForceDetection, + NvU32 gpuCount, + NvU32 gpuMaskArg, + NvU32 *pSliLinkTestDone, + NvU32 *pSliLinkOutputMask, + NvBool *pSliLinkCircular, + NvU32 *pSliLinkEndsMask, + NvU32 *pVidLinkCount +) +{ + OBJGPU *pGpu; + OBJGPU *pGpuSaved; + NvU32 gpuIndex = 0; + NvU32 EndsMask = 0; + NvU32 gpuMask = gpuMaskArg; + NvU32 linkTestDone = 0, linkOutputMask = 0; + NvBool bSliLinkCircular = NV_FALSE; + NvU32 vidLinkCount = 0; + NvU32 linkHalImpl; + NvBool *pBcState; + NvU32 gpuIndexInBcStateTable; + + *pSliLinkTestDone = *pSliLinkOutputMask = *pSliLinkEndsMask = 0; + + // Bail out early if all GPU'S haven't been loaded. + if (gpumgrStateInitialized() != NV_OK) + { + NV_PRINTF(LEVEL_WARNING, + "All GPUs do not have state initialized\n"); + return; + } + + // If there's only 1 bit set or no bits set here then this call + // is not going to help! + if (gpuCount < 2) + { + // If we've gotten here, then that means the caller is calling + // before more than one GPU is setup + NV_PRINTF(LEVEL_INFO, + "gpumgrDetectSliLinkFromGpus: Need >=2 GPUs to test SliLink.\n gpuMask = 0x%x\n", + gpuMask); + return; + } + + // If we've already done the detection on this set of gpus + // return the output mask. + + if ((linkTestDone == gpuMask) && !bForceDetection) + { + *pSliLinkTestDone = linkTestDone; + *pSliLinkOutputMask = linkOutputMask; + *pSliLinkCircular = bSliLinkCircular; + *pSliLinkEndsMask = EndsMask; + *pVidLinkCount = vidLinkCount; + return; + } + + // Bail early if one of the GPUs does not have a display engine + gpuIndex = 0; + while ((pGpu = gpumgrGetNextGpu(gpuMask, &gpuIndex)) != NULL) + { + KernelDisplay *pKernelDisp = GPU_GET_KERNEL_DISPLAY(pGpu); + if ( + pKernelDisp == NULL) + { + *pSliLinkTestDone = gpuMask; + *pSliLinkOutputMask = 0; + return; + } + } + + // clear out linkTestDone, linkOutputMask, circularVideoBridge + linkTestDone = linkOutputMask = 0; + bSliLinkCircular = NV_FALSE; + + // Check that all GPUs have the same HAL + gpuIndex = 0; + pGpu = gpumgrGetNextGpu(gpuMask, &gpuIndex); + if (pGpu != NULL) + { + pGpuSaved = pGpu; + linkHalImpl = gpuGetSliLinkDetectionHalFlag_HAL(pGpu); + } + else + { + *pSliLinkTestDone = gpuMask; + *pSliLinkOutputMask = 0; + return; + } + + pGpu = gpumgrGetNextGpu(gpuMask, &gpuIndex); + while (pGpu != NULL) + { + if (linkHalImpl != gpuGetSliLinkDetectionHalFlag_HAL(pGpu)) + { + *pSliLinkTestDone = gpuMask; + *pSliLinkOutputMask = 0; + return; + } + pGpu = gpumgrGetNextGpu(gpuMask, &gpuIndex); + } + + // Make sure BC is disabled + pBcState = portMemAllocNonPaged(gpuCount * sizeof(NvBool)); + if (pBcState == NULL) + { + NV_PRINTF(LEVEL_ERROR, + "gpumgrDetectSliLinkFromGpus: Insufficient resources.\n"); + return; + } + + gpuIndex = 0; + gpuIndexInBcStateTable = 0; + pGpu = gpumgrGetNextGpu(gpuMask, &gpuIndex); + while (pGpu != NULL) + { + if (IsSLIEnabled(pGpu)) + { + pBcState[gpuIndexInBcStateTable++] = gpumgrGetBcEnabledStatus(pGpu); + gpumgrSetBcEnabledStatus(pGpu, NV_FALSE); + } + pGpu = gpumgrGetNextGpu(gpuMask, &gpuIndex); + } + + // Call HAL function + gpuDetectSliLinkFromGpus_HAL(pGpuSaved, gpuCount, gpuMaskArg, + &linkOutputMask, + &bSliLinkCircular, + &EndsMask, + &vidLinkCount); + + // Restore BC settings + gpuIndex = 0; + gpuIndexInBcStateTable = 0; + pGpu = gpumgrGetNextGpu(gpuMask, &gpuIndex); + while (pGpu != NULL) + { + if (IsSLIEnabled(pGpu)) + { + gpumgrSetBcEnabledStatus(pGpu, pBcState[gpuIndexInBcStateTable++]); + } + + // Clear high speed bridge property here on all GPUs. + // We set it in gpumgrDetectHighSpeedVideoBridges() for the GPUs in the video link. + pGpu->setProperty(pGpu, PDB_PROP_GPU_HIGH_SPEED_BRIDGE_CONNECTED, NV_FALSE); + + pGpu = gpumgrGetNextGpu(gpuMask, &gpuIndex); + } + + portMemFree(pBcState); + + linkTestDone = gpuMaskArg; + + // See if we want to disable SLI Video Bridge - Bug 174307 + // Only need to read the regkey if we passed the detection code + if (linkOutputMask) + { + gpuMask = linkOutputMask; + + gpuIndex = 0; + for (pGpu = gpumgrGetNextGpu(gpuMask, &gpuIndex); + NULL != pGpu; + pGpu = gpumgrGetNextGpu(gpuMask, &gpuIndex)) + { + if (gpuIsVideoLinkDisabled(pGpu)) + { + // Remove all gpus if this regkey is found on any gpu + linkOutputMask = 0; + } + } + } + + gpumgrDetectHighSpeedVideoBridges(linkOutputMask); + + *pSliLinkOutputMask = linkOutputMask; + *pSliLinkTestDone = linkTestDone; + *pSliLinkCircular = bSliLinkCircular; + *pSliLinkEndsMask = EndsMask; + *pVidLinkCount = vidLinkCount; +} + + +// +// Return a status indicating whether all GPU's have been initialized via StateInit(). +// +static NV_STATUS gpumgrStateInitialized(void) +{ + OBJGPU *pGpu = NULL; + NvU32 gpuMask = 0; + NvU32 gpuCount = 0; + NvU32 gpuIndex = 0; + NV_STATUS status = NV_OK; + + gpumgrGetGpuAttachInfo(&gpuCount, &gpuMask); + + pGpu = gpumgrGetNextGpu(gpuMask, &gpuIndex); + if (pGpu == NULL) + { + return NV_ERR_INVALID_POINTER; + } + + do + { + if (!pGpu->getProperty(pGpu, PDB_PROP_GPU_STATE_INITIALIZED)) + { + status = NV_ERR_INVALID_STATE; + } + + pGpu = gpumgrGetNextGpu(gpuMask, &gpuIndex); + + } while (pGpu); + + return (status); +} + +/*! + * @brief Updates the GPU routing information for the + * 2 specified GPUs using the 2 Pinset Indices specified. + * + * @param[In] pGpuParent The 1st GPU to be tested for a connection. + * pGpuChild The 2nd GPU to be tested for a connection with the 1st GPU. + * bridgeType The type of bridge whose routing information + * should be updated withthe resiults of the testing. + * parentPinsetIndex The pinset index to be used on the GpuParent + * to test for an SLI connection. + * childPinsetIndex The pinset index to be used on the GpuChild + * to test for an SLI connection. + * bForceUpdate Will be NV_TRUE if we want to force update the SLI link even + * with no video link detected. + * + * @retun a boolen indicating if the SLI connection specified + * by the pinset indices is valid between the 2 specified GPUs. +.*/ +NvBool gpumgrUpdateSliLinkRouting +( + OBJGPU *pGpuParent, + OBJGPU *pGpuChild, + NvU32 bridgeType, + NvU32 parentPinsetIndex, + NvU32 childPinsetIndex, + NvBool bForceUpdate +) +{ + + NvBool linkFound = NV_FALSE; + OBJSYS *pSys = SYS_GET_INSTANCE(); + OBJGPUMGR *pGpuMgr = SYS_GET_GPUMGR(pSys); + KernelDisplay *pKernelDisp = GPU_GET_KERNEL_DISPLAY(pGpuParent); + + NV_ASSERT_OR_RETURN(!IS_GSP_CLIENT(pGpuParent) || pKernelDisp != NULL, NV_FALSE); + + // run the test. It is bidirectional + if (!bForceUpdate) + { + if (pKernelDisp != NULL) + linkFound = kdispDetectSliLink_HAL(pKernelDisp, pGpuParent, pGpuChild, NVBIT(parentPinsetIndex), NVBIT(childPinsetIndex)) == NV_OK; + } + + if (linkFound || bForceUpdate) + { + // Store off the input connection between Parent and Child here + pGpuMgr->gpuSliLinkRoute[bridgeType][pGpuParent->gpuInstance][pGpuChild->gpuInstance][parentPinsetIndex] = + FLD_SET_DRF(_SLILINK, _ROUTE, _INPUT, _PASSED, + pGpuMgr->gpuSliLinkRoute[bridgeType][pGpuParent->gpuInstance][pGpuChild->gpuInstance][parentPinsetIndex]); + pGpuMgr->gpuSliLinkRoute[bridgeType][pGpuChild->gpuInstance][pGpuParent->gpuInstance][childPinsetIndex] = + FLD_SET_DRF(_SLILINK, _ROUTE, _INPUT, _PASSED, + pGpuMgr->gpuSliLinkRoute[bridgeType][pGpuChild->gpuInstance][pGpuParent->gpuInstance][childPinsetIndex]); + + // Store off the output connection between Parent and Child here + pGpuMgr->gpuSliLinkRoute[bridgeType][pGpuParent->gpuInstance][pGpuChild->gpuInstance][parentPinsetIndex] = + FLD_SET_DRF(_SLILINK, _ROUTE, _OUTPUT, _PASSED, + pGpuMgr->gpuSliLinkRoute[bridgeType][pGpuParent->gpuInstance][pGpuChild->gpuInstance][parentPinsetIndex]); + pGpuMgr->gpuSliLinkRoute[bridgeType][pGpuChild->gpuInstance][pGpuParent->gpuInstance][childPinsetIndex] = + FLD_SET_DRF(_SLILINK, _ROUTE, _OUTPUT, _PASSED, + pGpuMgr->gpuSliLinkRoute[bridgeType][pGpuChild->gpuInstance][pGpuParent->gpuInstance][childPinsetIndex]); + + // Store off the Child Port used by the Parent + pGpuMgr->gpuSliLinkRoute[bridgeType][pGpuParent->gpuInstance][pGpuChild->gpuInstance][parentPinsetIndex] = + FLD_SET_DRF_NUM(_SLILINK, _ROUTE, _INPUT_CHILD_PORT, (NvU8) NVBIT(childPinsetIndex), + pGpuMgr->gpuSliLinkRoute[bridgeType][pGpuParent->gpuInstance][pGpuChild->gpuInstance][parentPinsetIndex]); + + // Store off the Parent Port used by the Child + pGpuMgr->gpuSliLinkRoute[bridgeType][pGpuChild->gpuInstance][pGpuParent->gpuInstance][childPinsetIndex] = + FLD_SET_DRF_NUM(_SLILINK, _ROUTE, _INPUT_CHILD_PORT, (NvU8) NVBIT(parentPinsetIndex), + pGpuMgr->gpuSliLinkRoute[bridgeType][pGpuChild->gpuInstance][pGpuParent->gpuInstance][childPinsetIndex]); + + // Setup GPUs to reference each other + pGpuParent->peer[parentPinsetIndex].pGpu = pGpuChild; + pGpuParent->peer[parentPinsetIndex].pinset = NVBIT(childPinsetIndex); + pGpuChild->peer[childPinsetIndex].pGpu = pGpuParent; + pGpuChild->peer[childPinsetIndex].pinset = NVBIT(parentPinsetIndex); + } + else + { + // Make sure to not override any passing cases with a failure + // Store off the failed input connection between Parent & Child here + if (!FLD_TEST_DRF(_SLILINK, _ROUTE, _INPUT, _PASSED, + pGpuMgr->gpuSliLinkRoute[bridgeType][pGpuParent->gpuInstance][pGpuChild->gpuInstance][parentPinsetIndex])) + { + pGpuMgr->gpuSliLinkRoute[bridgeType][pGpuParent->gpuInstance][pGpuChild->gpuInstance][parentPinsetIndex] = + FLD_SET_DRF(_SLILINK, _ROUTE, _INPUT, _FAILED, + pGpuMgr->gpuSliLinkRoute[bridgeType][pGpuParent->gpuInstance][pGpuChild->gpuInstance][parentPinsetIndex]); + } + if (!FLD_TEST_DRF(_SLILINK, _ROUTE, _INPUT, _PASSED, + pGpuMgr->gpuSliLinkRoute[bridgeType][pGpuChild->gpuInstance][pGpuParent->gpuInstance][childPinsetIndex])) + { + pGpuMgr->gpuSliLinkRoute[bridgeType][pGpuChild->gpuInstance][pGpuParent->gpuInstance][childPinsetIndex] = + FLD_SET_DRF(_SLILINK, _ROUTE, _INPUT, _FAILED, + pGpuMgr->gpuSliLinkRoute[bridgeType][pGpuChild->gpuInstance][pGpuParent->gpuInstance][childPinsetIndex ]); + } + // Store off the failed output connection between Child & Parent here + if (!FLD_TEST_DRF(_SLILINK, _ROUTE, _OUTPUT, _PASSED, + pGpuMgr->gpuSliLinkRoute[bridgeType][pGpuParent->gpuInstance][pGpuChild->gpuInstance][parentPinsetIndex])) + { + pGpuMgr->gpuSliLinkRoute[bridgeType][pGpuParent->gpuInstance][pGpuChild->gpuInstance][parentPinsetIndex] = + FLD_SET_DRF(_SLILINK, _ROUTE, _OUTPUT, _FAILED, + pGpuMgr->gpuSliLinkRoute[bridgeType][pGpuParent->gpuInstance][pGpuChild->gpuInstance][parentPinsetIndex]); + } + if (!FLD_TEST_DRF(_SLILINK, _ROUTE, _OUTPUT, _PASSED, + pGpuMgr->gpuSliLinkRoute[bridgeType][pGpuChild->gpuInstance][pGpuParent->gpuInstance][childPinsetIndex])) + { + pGpuMgr->gpuSliLinkRoute[bridgeType][pGpuChild->gpuInstance][pGpuParent->gpuInstance][childPinsetIndex] = + FLD_SET_DRF(_SLILINK, _ROUTE, _OUTPUT, _FAILED, + pGpuMgr->gpuSliLinkRoute[bridgeType][pGpuChild->gpuInstance][pGpuParent->gpuInstance][childPinsetIndex ]); + } + } + return linkFound; +} + +NvBool +gpumgrDetectHighSpeedVideoBridges(NvU32 linkOutputMask) +{ + OBJGPU *pGpu; + KernelDisplay *pKernelDisp; + NvU32 gpuIndex; + NvBool bHighSpeedBridgeConnected = NV_FALSE; + + gpuIndex = 0; + while ((pGpu = gpumgrGetNextGpu(linkOutputMask, &gpuIndex))) + { + pKernelDisp = GPU_GET_KERNEL_DISPLAY(pGpu); + + if ( + (pKernelDisp == NULL)) + { + NV_ASSERT(pKernelDisp != NULL); // This should not happen + continue; + } + + // + // Only one GPU in the link is able to detect a high speed bridge. + // 3-way SLI, bridged 4-way SLI are not supported, so it is OK. + // + pGpu->setProperty(pGpu, PDB_PROP_GPU_HIGH_SPEED_BRIDGE_CONNECTED, NV_FALSE); + + NvU32 gpuLockMask = 0; + if (IS_GSP_CLIENT(pGpu) && !rmDeviceGpuLockIsOwner(pGpu->gpuInstance)) + NV_ASSERT_OK_OR_RETURN(rmGpuGroupLockAcquire(pGpu->gpuInstance, + GPU_LOCK_GRP_SUBDEVICE, + GPUS_LOCK_FLAGS_NONE, + RM_LOCK_MODULES_RPC, + &gpuLockMask)); + + RM_API *pRmApi = GPU_GET_PHYSICAL_RMAPI(pGpu); + NV_STATUS status = pRmApi->Control(pRmApi, + pGpu->hInternalClient, + pGpu->hInternalSubdevice, + NV2080_CTRL_CMD_INTERNAL_DETECT_HS_VIDEO_BRIDGE, + NULL, + 0); + + bHighSpeedBridgeConnected |= (status == NV_OK); + + if (gpuLockMask != 0) + rmGpuGroupLockRelease(gpuLockMask, GPUS_LOCK_FLAGS_NONE); + } + + if (bHighSpeedBridgeConnected) + { + // + // Update video bridge max pixelclock to the fast video bridge limit. + // We are here because no slow video bridge ic\s connected to any connectors, + // and a high speed video bridge is connected at least on one of the connectors. + // + gpuIndex = 0; + while ((pGpu = gpumgrGetNextGpu(linkOutputMask, &gpuIndex))) + { + pKernelDisp = GPU_GET_KERNEL_DISPLAY(pGpu); + + if ( + (pKernelDisp == NULL)) + { + NV_ASSERT(pKernelDisp != NULL); // This should not happen + continue; + } + + // Set high speed bridge property on all GPUs. + pGpu->setProperty(pGpu, PDB_PROP_GPU_HIGH_SPEED_BRIDGE_CONNECTED, NV_TRUE); + } + } + return bHighSpeedBridgeConnected; +} + +/*! + * @brief Returns the pinset index to be used in an array from the pinset definition + * + * @param[In] pinset NvU32, Pinset value. Should have only one bit set. + * @param[Out] pPinsetIndex NvU32*, Pinset index value to be used in an array. +.*/ +NV_STATUS +gpumgrPinsetToPinsetTableIndex(NvU32 pinset, NvU32 *pPinsetIndex) +{ + NvU32 pinsetIndex; + if (!ONEBITSET(pinset)) + { + NV_PRINTF(LEVEL_ERROR, "More than one bit set: 0x%x\n", pinset); + DBG_BREAKPOINT(); + return NV_ERR_INVALID_ARGUMENT; + } + + switch (pinset) + { + case drPinSet_A: + case drPinSet_B: + break; + case drPinSet_None: + default: + NV_PRINTF(LEVEL_ERROR, "Unknown pin set value: 0x%x\n", pinset); + DBG_BREAKPOINT(); + return NV_ERR_INVALID_ARGUMENT; + } + pinsetIndex = pinset - 1; + NUMSETBITS_32(pinsetIndex); + + *pPinsetIndex = pinsetIndex; + return NV_OK; +} + +// +// gpumgrGetSliLinks +// +// This routine services the NV0000_CTRL_CMD_GPU_GET_VIDEO_LINKS +// command. The passed in table is filled in with information +// about SLI connections (video bridge or NvLinks) between GPUs identified by their +// GPU IDs. Each row represents the connections, if any, for a +// single GPU. Peer GPUs are listed using their GPU IDs, invalid +// entries are filled with invalid ID values. +// +NV_STATUS +gpumgrGetSliLinks(NV0000_CTRL_GPU_GET_VIDEO_LINKS_PARAMS *pVideoLinksParams) +{ + NvU32 i, j; + NvU32 gpuIndex, peerGpuIndex; + NvU32 pinsetIndex, childDrPort, childDrPortIndex; + NV0000_CTRL_GPU_VIDEO_LINKS *pSliLinks; + OBJGPU *pGpu, *pPeerGpu; + OBJSYS *pSys; + OBJGPUMGR *pGpuMgr; + NvU32 gpuAttachCnt, gpuAttachMask; + NV_STATUS rmStatus = NV_OK; + + for (i = 0; i < NV0000_CTRL_GPU_MAX_ATTACHED_GPUS; i++) + { + pSliLinks = &pVideoLinksParams->links[i]; + + for (j = 0; j < NV0000_CTRL_GPU_MAX_VIDEO_LINKS; j++) + { + pSliLinks->connectedGpuIds[j] = NV0000_CTRL_GPU_INVALID_ID; + } + pSliLinks->gpuId = NV0000_CTRL_GPU_INVALID_ID; + } + + gpumgrGetGpuAttachInfo(&gpuAttachCnt, &gpuAttachMask); + if (gpuAttachCnt < 2) + { + return NV_OK; + } + + pSys = SYS_GET_INSTANCE(); + pGpuMgr = SYS_GET_GPUMGR(pSys); + + i = gpuIndex = 0; + while ((pGpu = gpumgrGetNextGpu(gpuAttachMask, &gpuIndex)) && + (i < NV0000_CTRL_GPU_MAX_ATTACHED_GPUS)) + { + if (pGpu->gpuInstance >= NV2080_MAX_SUBDEVICES) + { + NV_ASSERT(pGpu->gpuInstance < NV2080_MAX_SUBDEVICES); + continue; + } + + pSliLinks = &pVideoLinksParams->links[i++]; + pSliLinks->gpuId = pGpu->gpuId; + + j = peerGpuIndex = 0; + while ((pPeerGpu = gpumgrGetNextGpu(gpuAttachMask, &peerGpuIndex)) && + (j < NV0000_CTRL_GPU_MAX_VIDEO_LINKS)) + { + if ((peerGpuIndex == gpuIndex) || + (pPeerGpu->gpuInstance >= NV2080_MAX_SUBDEVICES)) + { + continue; + } + + for (pinsetIndex = 0; pinsetIndex < DR_PINSET_COUNT; pinsetIndex++) + { + if (!FLD_TEST_DRF(_SLILINK, _ROUTE, _INPUT, _PASSED, + pGpuMgr->gpuSliLinkRoute[pGpuMgr->gpuBridgeType][pGpu->gpuInstance][pPeerGpu->gpuInstance][pinsetIndex])) + { + continue; + } + + childDrPort = DRF_VAL(_SLILINK, _ROUTE, _INPUT_CHILD_PORT, + pGpuMgr->gpuSliLinkRoute[pGpuMgr->gpuBridgeType][pGpu->gpuInstance][pPeerGpu->gpuInstance][pinsetIndex]); + + if (SLI_BT_VIDLINK == pGpuMgr->gpuBridgeType) + { + rmStatus = gpumgrPinsetToPinsetTableIndex(childDrPort, &childDrPortIndex); + if (rmStatus != NV_OK) + { + return rmStatus; + } + + if (!FLD_TEST_DRF(_SLILINK, _ROUTE, _OUTPUT, _PASSED, + pGpuMgr->gpuSliLinkRoute[pGpuMgr->gpuBridgeType][pPeerGpu->gpuInstance][pGpu->gpuInstance][childDrPortIndex])) + { + continue; + } + } + + if (j < NV0000_CTRL_GPU_MAX_VIDEO_LINKS) + { + pSliLinks->connectedGpuIds[j++] = pPeerGpu->gpuId; + } + } + } + } + return NV_OK; +} diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/kernel/mem_mgr/ctx_buf_pool.c nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/kernel/mem_mgr/ctx_buf_pool.c --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/kernel/mem_mgr/ctx_buf_pool.c 2023-10-25 20:21:24.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/kernel/mem_mgr/ctx_buf_pool.c 2024-03-05 22:13:55.000000000 +0000 @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 2016-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2016-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -71,6 +71,13 @@ return NV_FALSE; } + // TODO remove when bug ID 3922001 for ap_sim_compute_uvm test case resolved + if (!IS_SILICON(pGpu)) + { + NV_PRINTF(LEVEL_INFO, "Ctx buffers not supported on simulation/emulation\n"); + return NV_FALSE; + } + if (IS_VIRTUAL(pGpu) || RMCFG_FEATURE_PLATFORM_GSP) { NV_PRINTF(LEVEL_INFO, "Guest RM/GSP don't support ctx buffers in PMA\n"); @@ -155,6 +162,11 @@ poolConfig), cleanup); + // Allocate the pool in CPR in case of Confidential Compute + if (gpuIsCCFeatureEnabled(pGpu)) + { + rmMemPoolAllocateProtectedMemory(pCtxBufPool->pMemPool[i], NV_TRUE); + } } NV_PRINTF(LEVEL_INFO, "Ctx buf pool successfully initialized\n"); @@ -244,7 +256,8 @@ ) { NV_STATUS status = NV_OK; - NvU32 pageSize, i; + NvU64 pageSize; + NvU32 i; NvU64 totalSize[RM_ATTR_PAGE_SIZE_INVALID] = {0}; NvU64 size; @@ -280,10 +293,10 @@ totalSize[RM_ATTR_PAGE_SIZE_512MB] += size; break; default: - NV_PRINTF(LEVEL_ERROR, "Unrecognized/unsupported page size = 0x%x\n", pageSize); + NV_PRINTF(LEVEL_ERROR, "Unrecognized/unsupported page size = 0x%llx\n", pageSize); NV_ASSERT_OR_RETURN(0, NV_ERR_INVALID_ARGUMENT); } - NV_PRINTF(LEVEL_INFO, "Reserving 0x%llx bytes for buf Id = 0x%x in pool with page size = 0x%x\n", size, i, pageSize); + NV_PRINTF(LEVEL_INFO, "Reserving 0x%llx bytes for buf Id = 0x%x in pool with page size = 0x%llx\n", size, i, pageSize); } for (i = 0; i < RM_ATTR_PAGE_SIZE_INVALID; i++) @@ -382,10 +395,10 @@ } // If page size is not set, then set it based on actual size of memdesc and its alignment - NvU32 pageSize = memdescGetPageSize(pMemDesc, AT_GPU); + NvU64 pageSize = memdescGetPageSize(pMemDesc, AT_GPU); if ((pageSize == 0) || (memdescGetContiguity(pMemDesc, AT_GPU))) { - NvU32 newPageSize; + NvU64 newPageSize; NV_ASSERT_OK_OR_RETURN(ctxBufPoolGetSizeAndPageSize(pCtxBufPool, pMemDesc->pGpu, pMemDesc->Alignment, RM_ATTR_PAGE_SIZE_DEFAULT, memdescGetContiguity(pMemDesc, AT_GPU), &pMemDesc->ActualSize, &newPageSize)); @@ -400,7 +413,7 @@ if (pageSize == 0) { memdescSetPageSize(pMemDesc, AT_GPU, newPageSize); - NV_PRINTF(LEVEL_INFO, "Ctx buffer page size set to 0x%x\n", newPageSize); + NV_PRINTF(LEVEL_INFO, "Ctx buffer page size set to 0x%llx\n", newPageSize); } pageSize = newPageSize; } @@ -422,11 +435,11 @@ pPool = pCtxBufPool->pMemPool[RM_ATTR_PAGE_SIZE_512MB]; break; default: - NV_PRINTF(LEVEL_ERROR, "Unsupported page size = 0x%x set for context buffer\n", pageSize); + NV_PRINTF(LEVEL_ERROR, "Unsupported page size = 0x%llx set for context buffer\n", pageSize); NV_ASSERT_OR_RETURN(0, NV_ERR_INVALID_ARGUMENT); } NV_ASSERT_OK_OR_RETURN(rmMemPoolAllocate(pPool, (RM_POOL_ALLOC_MEMDESC*)pMemDesc)); - NV_PRINTF(LEVEL_INFO, "Buffer allocated from ctx buf pool with page size = 0x%x\n", pageSize); + NV_PRINTF(LEVEL_INFO, "Buffer allocated from ctx buf pool with page size = 0x%llx\n", pageSize); return NV_OK; } @@ -449,7 +462,7 @@ NV_ASSERT_OR_RETURN(pCtxBufPool != NULL, NV_ERR_INVALID_ARGUMENT); NV_ASSERT_OR_RETURN(pMemDesc != NULL, NV_ERR_INVALID_ARGUMENT); - NvU32 pageSize = memdescGetPageSize(pMemDesc, AT_GPU); + NvU64 pageSize = memdescGetPageSize(pMemDesc, AT_GPU); // // If buffer is contiguous, then it may or may not be allocated from the same pool @@ -488,21 +501,20 @@ if (rmMemPoolIsScrubSkipped(pPool)) { OBJGPU *pGpu = pMemDesc->pGpu; - NvU8 *pMem = kbusMapRmAperture_HAL(pGpu, pMemDesc); - if (pMem == NULL) - { - NV_PRINTF(LEVEL_ERROR, "Failed to BAR2 map memdesc. memory won't be scrubbed\n"); - NV_ASSERT(pMem != NULL); - } - else - { - portMemSet(pMem, 0, (pMemDesc->PageCount * RM_PAGE_SIZE)); - kbusUnmapRmAperture_HAL(pGpu, pMemDesc, &pMem, NV_TRUE); - } + MemoryManager *pMemoryManager = GPU_GET_MEMORY_MANAGER(pGpu); + TRANSFER_SURFACE surf = {0}; + + surf.pMemDesc = pMemDesc; + surf.offset = 0; + + NV_ASSERT_OK_OR_RETURN( + memmgrMemSet(pMemoryManager, &surf, 0, + pMemDesc->PageCount * RM_PAGE_SIZE, + TRANSFER_FLAGS_NONE)); } rmMemPoolFree(pPool, (RM_POOL_ALLOC_MEMDESC*)pMemDesc, 0); - NV_PRINTF(LEVEL_INFO, "Buffer freed from ctx buf pool with page size = 0x%x\n", pageSize); + NV_PRINTF(LEVEL_INFO, "Buffer freed from ctx buf pool with page size = 0x%llx\n", pageSize); return NV_OK; } @@ -572,12 +584,12 @@ RM_ATTR_PAGE_SIZE attr, NvBool bContig, NvU64 *pSize, - NvU32 *pPageSize + NvU64 *pPageSize ) { MemoryManager *pMemoryManager = GPU_GET_MEMORY_MANAGER(pGpu); NV_STATUS status = NV_OK; - NvU32 pageSize = 0; + NvU64 pageSize = 0; NvU32 allocFlags = 0; NvU32 retAttr = 0; NvU32 retAttr2 = 0; @@ -679,7 +691,7 @@ *pPageSize = pageSize; *pSize = size; - NV_PRINTF(LEVEL_INFO, "Buffer updated size = 0x%llx with page size = 0x%x\n", size, pageSize); + NV_PRINTF(LEVEL_INFO, "Buffer updated size = 0x%llx with page size = 0x%llx\n", size, pageSize); return status; } diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/kernel/mem_mgr/egm_mem.c nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/kernel/mem_mgr/egm_mem.c --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/kernel/mem_mgr/egm_mem.c 1970-01-01 00:00:00.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/kernel/mem_mgr/egm_mem.c 2024-03-05 22:13:55.000000000 +0000 @@ -0,0 +1,364 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2021-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#include "mem_mgr/egm_mem.h" + +#include "gpu/mem_mgr/mem_mgr.h" +#include "gpu/mem_mgr/mem_utils.h" +#include "os/os.h" +#include "deprecated/rmapi_deprecated.h" +#include "vgpu/rpc.h" + +#include "class/cl0042.h" // NV_MEMORY_EXTENDED_USER + +NV_STATUS +egmmemConstruct_IMPL +( + ExtendedGpuMemory *pExtendedGpuMemory, + CALL_CONTEXT *pCallContext, + RS_RES_ALLOC_PARAMS_INTERNAL *pParams +) +{ + Memory *pMemory = staticCast(pExtendedGpuMemory, Memory); + OBJGPU *pGpu = pMemory->pGpu; + MemoryManager *pMemoryManager = GPU_GET_MEMORY_MANAGER(pGpu); + NvHandle hClient = pCallContext->pClient->hClient; + NvHandle hParent = pCallContext->pResourceRef->pParentRef->hResource; + NV_MEMORY_ALLOCATION_PARAMS *pAllocData = pParams->pAllocParams; + MEMORY_ALLOCATION_REQUEST allocRequest = {0}; + MEMORY_ALLOCATION_REQUEST *pAllocRequest = &allocRequest; + RsResourceRef *pResourceRef = pCallContext->pResourceRef; + NV_STATUS rmStatus = NV_OK; + FB_ALLOC_INFO *pFbAllocInfo = NULL; + FB_ALLOC_PAGE_FORMAT *pFbAllocPageFormat = NULL; + MEMORY_DESCRIPTOR *pMemDesc; + HWRESOURCE_INFO hwResource; + NvU64 sizeOut; + NvU64 offsetOut; + NvU32 flags; + NvU32 gpuCacheAttrib; + NvU32 Cache; + + // Copy-construction has already been done by the base Memory class + if (RS_IS_COPY_CTOR(pParams)) + return NV_OK; + + NV_CHECK_OK_OR_RETURN(LEVEL_ERROR, egmmemValidateParams(pGpu, hClient, pAllocData)); + + // + // For non self-hosted case, we mimic vidmem as EGM and is only used for + // ARCH/MODS verification + // + if (!gpuIsSelfHosted(pGpu)) + { + return NV_ERR_NOT_SUPPORTED; + } + + stdmemDumpInputAllocParams(pAllocData, pCallContext); + + NV_PRINTF(LEVEL_ERROR, "EGM Allocation requested\n"); + + pAllocRequest->classNum = NV_MEMORY_EXTENDED_USER; + pAllocRequest->pUserParams = pAllocData; + pAllocRequest->hMemory = pResourceRef->hResource; + pAllocRequest->hClient = hClient; + pAllocRequest->hParent = hParent; + pAllocRequest->pGpu = pGpu; + pAllocRequest->internalflags = NVOS32_ALLOC_INTERNAL_FLAGS_CLIENTALLOC; + pAllocRequest->pHwResource = &hwResource; + + // Unsure if we need to keep separate copies, but keeping old behavior for now. + sizeOut = pAllocData->size; + offsetOut = pAllocData->offset; + + // Allocate and initialize FB_ALLOC_INFO + pFbAllocInfo = portMemAllocNonPaged(sizeof(FB_ALLOC_INFO)); + NV_ASSERT_TRUE_OR_GOTO(rmStatus, pFbAllocInfo != NULL, NV_ERR_NO_MEMORY, free_params_and_return); + + pFbAllocPageFormat = portMemAllocNonPaged(sizeof(FB_ALLOC_PAGE_FORMAT)); + NV_ASSERT_TRUE_OR_GOTO(rmStatus, pFbAllocPageFormat != NULL, NV_ERR_NO_MEMORY, free_params_and_return); + + portMemSet(pFbAllocInfo, 0, sizeof(FB_ALLOC_INFO)); + portMemSet(pFbAllocPageFormat, 0, sizeof(FB_ALLOC_PAGE_FORMAT)); + pFbAllocInfo->pageFormat = pFbAllocPageFormat; + + memUtilsInitFBAllocInfo(pAllocRequest->pUserParams, pFbAllocInfo, + pAllocRequest->hClient, pAllocRequest->hParent); + + NV_ASSERT_OK_OR_GOTO(rmStatus, + memmgrAllocResources(pGpu, pMemoryManager, pAllocRequest, pFbAllocInfo), + free_params_and_return); + + NV_ASSERT_OK_OR_GOTO(rmStatus, + egmmemAllocResources(pGpu, pMemoryManager, pAllocRequest, pFbAllocInfo), + free_params_and_return); + + NV_ASSERT(pAllocRequest->pMemDesc); + pMemDesc = pAllocRequest->pMemDesc; + + offsetOut = memdescGetPhysAddr(pMemDesc, AT_GPU, 0); + sizeOut = pMemDesc->Size; + pAllocData->limit = sizeOut - 1; + + if (FLD_TEST_DRF(OS32, _ATTR2, _GPU_CACHEABLE, _DEFAULT, pAllocData->attr2)) + { + pAllocData->attr2 = FLD_SET_DRF(OS32, _ATTR2, _GPU_CACHEABLE, _NO, + pAllocData->attr2); + } + + if (FLD_TEST_DRF(OS32, _ATTR2, _GPU_CACHEABLE, _YES, pAllocData->attr2)) + { + gpuCacheAttrib = NV_MEMORY_CACHED; + } + else + { + gpuCacheAttrib = NV_MEMORY_UNCACHED; + } + + if (FLD_TEST_DRF(OS32, _ATTR, _COHERENCY, _UNCACHED, pAllocData->attr)) + Cache = NV_MEMORY_UNCACHED; + else if (FLD_TEST_DRF(OS32, _ATTR, _COHERENCY, _CACHED, pAllocData->attr)) + Cache = NV_MEMORY_CACHED; + else if (FLD_TEST_DRF(OS32, _ATTR, _COHERENCY, _WRITE_COMBINE, pAllocData->attr)) + Cache = NV_MEMORY_WRITECOMBINED; + else if (FLD_TEST_DRF(OS32, _ATTR, _COHERENCY, _WRITE_THROUGH, pAllocData->attr)) + Cache = NV_MEMORY_CACHED; + else if (FLD_TEST_DRF(OS32, _ATTR, _COHERENCY, _WRITE_PROTECT, pAllocData->attr)) + Cache = NV_MEMORY_CACHED; + else if (FLD_TEST_DRF(OS32, _ATTR, _COHERENCY, _WRITE_BACK, pAllocData->attr)) + Cache = NV_MEMORY_CACHED; + else + Cache = 0; + + ct_assert(NVOS32_ATTR_COHERENCY_UNCACHED == NVOS02_FLAGS_COHERENCY_UNCACHED); + ct_assert(NVOS32_ATTR_COHERENCY_CACHED == NVOS02_FLAGS_COHERENCY_CACHED); + ct_assert(NVOS32_ATTR_COHERENCY_WRITE_COMBINE == NVOS02_FLAGS_COHERENCY_WRITE_COMBINE); + ct_assert(NVOS32_ATTR_COHERENCY_WRITE_THROUGH == NVOS02_FLAGS_COHERENCY_WRITE_THROUGH); + ct_assert(NVOS32_ATTR_COHERENCY_WRITE_PROTECT == NVOS02_FLAGS_COHERENCY_WRITE_PROTECT); + ct_assert(NVOS32_ATTR_COHERENCY_WRITE_BACK == NVOS02_FLAGS_COHERENCY_WRITE_BACK); + + flags = DRF_DEF(OS02, _FLAGS, _LOCATION, _PCI) | + DRF_DEF(OS02, _FLAGS, _MAPPING, _NO_MAP) | + DRF_NUM(OS02, _FLAGS, _COHERENCY, DRF_VAL(OS32, _ATTR, _COHERENCY, pAllocData->attr)); + + NV_ASSERT(memdescGetAddressSpace(pMemDesc) == ADDR_EGM); + memdescSetCpuCacheAttrib(pMemDesc, Cache); + + if (pCallContext->secInfo.privLevel < RS_PRIV_LEVEL_KERNEL) + memdescSetFlag(pMemDesc, MEMDESC_FLAGS_KERNEL_MODE, NV_FALSE); + + memdescSetFlag(pMemDesc, MEMDESC_FLAGS_SYSMEM_OWNED_BY_CLIENT, NV_TRUE); + + memdescSetGpuCacheAttrib(pMemDesc, gpuCacheAttrib); + + NV_ASSERT_OK_OR_GOTO(rmStatus, memdescAlloc(pMemDesc), mem_construct_failed); + + NV_ASSERT_OK_OR_GOTO(rmStatus, memConstructCommon(pMemory, + pAllocRequest->classNum, + flags, pMemDesc, 0, + NULL, pAllocData->attr, + pAllocData->attr2, 0, 0, + pAllocData->tag, &hwResource), + mem_construct_failed); + if (IS_VIRTUAL(pGpu)) + { + NvU32 os02Flags; + NvU32 os32Flags = pAllocData->flags; + + // + // Calculate os02flags as VGPU plugin allocates sysmem with legacy + // RmAllocMemory API + // + NV_ASSERT_OK_OR_GOTO(rmStatus, RmDeprecatedConvertOs32ToOs02Flags(pAllocData->attr, + pAllocData->attr2, + os32Flags, + &os02Flags), + convert_flags_failed); + + // + // vGPU: + // + // Since vGPU does all real hardware management in the + // host, if we are in guest OS (where IS_VIRTUAL(pGpu) is true), + // do an RPC to the host to do the hardware update. + // + NV_RM_RPC_ALLOC_MEMORY(pGpu, + hClient, + hParent, + pAllocRequest->hMemory, + pAllocRequest->classNum, + os02Flags, + pMemDesc, + rmStatus); + pMemory->bRpcAlloc = NV_TRUE; + } + + pAllocData->size = sizeOut; + pAllocData->offset = offsetOut; + + stdmemDumpOutputAllocParams(pAllocData); + + goto free_params_and_return; + +convert_flags_failed: + memDestructCommon(pMemory); + +mem_construct_failed: + memdescFree(pMemDesc); + memdescDestroy(pMemDesc); + +free_params_and_return: + portMemFree(pFbAllocPageFormat); + portMemFree(pFbAllocInfo); + + return rmStatus; +} + +NV_STATUS +egmmemValidateParams +( + OBJGPU *pGpu, + NvHandle hClient, + NV_MEMORY_ALLOCATION_PARAMS *pAllocData +) +{ + MemoryManager *pMemoryManager = GPU_GET_MEMORY_MANAGER(pGpu); + + NV_CHECK_OK_OR_RETURN(LEVEL_ERROR, stdmemValidateParams(pGpu, hClient, pAllocData)); + + // Make sure EGM memory is not requested if local EGM is not supported + if (!memmgrIsLocalEgmEnabled(pMemoryManager)) + { + NV_PRINTF(LEVEL_ERROR, + "Allocation requested from EGM when local EGM is not supported\n"); + return NV_ERR_INVALID_ARGUMENT; + } + + // For Self-Hosted platforms which support EGM, EGM pool is the same as sysmem pool + // Make sure _USE_EGM attribute is set only for sysmem allocations for SHH + if (gpuIsSelfHosted(pGpu)) + { + if (!FLD_TEST_DRF(OS32, _ATTR, _LOCATION, _PCI, pAllocData->attr)) + { + NV_PRINTF(LEVEL_ERROR, + "NVOS32_ATTR2_USE_EGM can be set to true only when NVOS32_ATTR_LOCATION_PCI is set for SHH\n"); + return NV_ERR_INVALID_ARGUMENT; + } + } + else + { + // Make sure _USE_EGM attribute is set only for NVOS32_ATTR_LOCATION_VIDMEM for non-SHH platforms + if (!FLD_TEST_DRF(OS32, _ATTR, _LOCATION, _VIDMEM, pAllocData->attr)) + { + NV_PRINTF(LEVEL_ERROR, + "NVOS32_ATTR2_USE_EGM can be set to true only when NVOS32_ATTR_LOCATION_VIDMEM is set\n"); + return NV_ERR_INVALID_ARGUMENT; + } + } + + return NV_OK; +} + +NV_STATUS +egmmemAllocResources +( + OBJGPU *pGpu, + MemoryManager *pMemoryManager, + MEMORY_ALLOCATION_REQUEST *pAllocRequest, + FB_ALLOC_INFO *pFbAllocInfo +) +{ + NV_STATUS status = NV_OK; + NV_MEMORY_ALLOCATION_PARAMS *pVidHeapAlloc = pAllocRequest->pUserParams; + MEMORY_DESCRIPTOR *pMemDesc = NULL; + NvBool bAllocedMemDesc = NV_FALSE; + NvBool bContig = FLD_TEST_DRF(OS32, _ATTR, _PHYSICALITY, + _CONTIGUOUS, pVidHeapAlloc->attr); + + // + // Check for virtual-only parameters used on physical allocs. + // + if (pVidHeapAlloc->flags & NVOS32_ALLOC_FLAGS_VIRTUAL_ONLY) + { + NV_PRINTF(LEVEL_ERROR, + "Virtual-only flag used with physical allocation\n"); + status = NV_ERR_INVALID_ARGUMENT; + goto failed; + } + if (FLD_TEST_DRF(OS32, _ATTR2, _32BIT_POINTER, _ENABLE, pVidHeapAlloc->attr2)) + { + NV_PRINTF(LEVEL_ERROR, + "Virtual-only 32-bit pointer attr used with physical allocation\n"); + status = NV_ERR_INVALID_ARGUMENT; + goto failed; + } + if (pVidHeapAlloc->hVASpace != 0) + { + NV_PRINTF(LEVEL_ERROR, + "VA space handle used with physical allocation\n"); + status = NV_ERR_INVALID_ARGUMENT; + goto failed; + } + + NV_ASSERT(!(pVidHeapAlloc->flags & NVOS32_ALLOC_FLAGS_WPR1) && !(pVidHeapAlloc->flags & NVOS32_ALLOC_FLAGS_WPR2)); + + if (pVidHeapAlloc->flags & NVOS32_ALLOC_FLAGS_FIXED_ADDRESS_ALLOCATE) + { + NV_PRINTF(LEVEL_ERROR, + "Expected fixed address allocation\n"); + status = NV_ERR_INVALID_ARGUMENT; + goto failed; + } + + NV_CHECK_OK_OR_GOTO(status, LEVEL_ERROR, memUtilsAllocMemDesc(pGpu, pAllocRequest, pFbAllocInfo, &pMemDesc, NULL, + ADDR_EGM, bContig, &bAllocedMemDesc), failed); + + // get possibly updated surface attributes + pVidHeapAlloc->attr = pFbAllocInfo->retAttr; + pVidHeapAlloc->attr2 = pFbAllocInfo->retAttr2; + + pVidHeapAlloc->offset = pFbAllocInfo->offset; + + if (pAllocRequest->pHwResource != NULL) + { + pAllocRequest->pHwResource->attr = pFbAllocInfo->retAttr; + pAllocRequest->pHwResource->attr2 = pFbAllocInfo->retAttr2; + pAllocRequest->pHwResource->hwResId = pFbAllocInfo->hwResId; + pAllocRequest->pHwResource->comprCovg = pFbAllocInfo->comprCovg; + pAllocRequest->pHwResource->ctagOffset = pFbAllocInfo->ctagOffset; + pAllocRequest->pHwResource->hwResId = pFbAllocInfo->hwResId; + } + + return NV_OK; + +failed: + memmgrFreeHwResources(pGpu, pMemoryManager, pFbAllocInfo); + + if (bAllocedMemDesc) + { + memdescDestroy(pAllocRequest->pMemDesc); + pAllocRequest->pMemDesc = NULL; + } + + return status; +} diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/kernel/mem_mgr/fabric_vaspace.c nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/kernel/mem_mgr/fabric_vaspace.c --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/kernel/mem_mgr/fabric_vaspace.c 2023-10-25 20:21:24.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/kernel/mem_mgr/fabric_vaspace.c 2024-03-05 22:13:55.000000000 +0000 @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 2021-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2021-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -52,6 +52,8 @@ #include "mem_mgr/virt_mem_mgr.h" #include "published/ampere/ga100/dev_mmu.h" +#include "vgpu/rpc.h" +#include "virtualization/hypervisor/hypervisor.h" @@ -146,7 +148,7 @@ } // -// TODO: To be removed when legacy FLA VAS (pKernelBus->flaInfo.pFlaVAS) is removed" +// TODO: To be removed when legacy FLA VAS (pKernelBus->flaInfo.pFlaVAS)is removed" // The instance block is unbind during kbusDestroyFla_HAL(). However, we unbind // it here and bind back the instance block for the legacy FLA VAS after the // last NV_FABRIC_MEMORY allocation is freed. @@ -183,12 +185,15 @@ if (pKernelBus->flaInfo.pFlaVAS != NULL) { // Instantiate the instance block for FLA vaspace. - NV_ASSERT(kgmmuInstBlkInit(pKernelGmmu, pKernelBus->flaInfo.pInstblkMemDesc, - pKernelBus->flaInfo.pFlaVAS, FIFO_PDB_IDX_BASE, - &instblkParams) == NV_OK); + NV_ASSERT(kgmmuInstBlkInit(pKernelGmmu, + pKernelBus->flaInfo.pInstblkMemDesc, + pKernelBus->flaInfo.pFlaVAS, + FIFO_PDB_IDX_BASE, + &instblkParams) == NV_OK); // Bind the instance block for FLA vaspace. - NV_ASSERT(kbusSetupBindFla_HAL(pGpu, pKernelBus, pFabricVAS->gfid) == NV_OK); + NV_ASSERT(kbusSetupBindFla_HAL(pGpu, pKernelBus, + pFabricVAS->gfid) == NV_OK); } } @@ -225,7 +230,7 @@ status = pRmApi->AllocWithHandle(pRmApi, NV01_NULL_OBJECT, NV01_NULL_OBJECT, NV01_NULL_OBJECT, - NV01_ROOT, &hClient); + NV01_ROOT, &hClient, sizeof(hClient)); if (status != NV_OK) { NV_PRINTF(LEVEL_ERROR, "failed creating client, status=0x%x\n", status); @@ -235,14 +240,16 @@ status = serverutilGenResourceHandle(hClient, &hDevice); if (status != NV_OK) { - NV_PRINTF(LEVEL_ERROR, "failed creating device handle, status=0x%x\n", status); + NV_PRINTF(LEVEL_ERROR, + "failed creating device handle, status=0x%x\n", status); goto cleanup; } // Allocate a device handle devAllocParams.deviceId = gpuGetDeviceInstance(pGpu); status = pRmApi->AllocWithHandle(pRmApi, hClient, hClient, hDevice, - NV01_DEVICE_0, &devAllocParams); + NV01_DEVICE_0, + &devAllocParams, sizeof(devAllocParams)); if (status != NV_OK) { NV_PRINTF(LEVEL_ERROR, "failed creating device, status=0x%x\n", status); @@ -261,7 +268,8 @@ pFabricVAS->flags |= VASPACE_FLAGS_ALLOW_PAGES_IN_PHYS_MEM_SUBALLOCATOR; } - pFabricVAS->bRpcAlloc = IS_VIRTUAL(pGpu) && gpuIsWarBug200577889SriovHeavyEnabled(pGpu); + pFabricVAS->bRpcAlloc = IS_VIRTUAL(pGpu) && + gpuIsWarBug200577889SriovHeavyEnabled(pGpu); // Create the GVASPACE object associated with this fabric vaspace. status = vmmCreateVaspace(pVmm, FERMI_VASPACE_A, 0, pVAS->gpuMask, @@ -331,56 +339,11 @@ NvU64 *pAddr ) { - NV_STATUS status = NV_OK; - - // Sanity check the input parameters. - NV_ASSERT_OR_RETURN(pFabricVAS->pGVAS != NULL, NV_ERR_OBJECT_NOT_FOUND); - NV_ASSERT_OR_RETURN(pAddr != NULL, NV_ERR_INVALID_ARGUMENT); - NV_ASSERT_OR_RETURN(pageSize >= RM_PAGE_SIZE_HUGE, NV_ERR_INVALID_ARGUMENT); - NV_ASSERT_OR_RETURN(align != 0, NV_ERR_INVALID_ARGUMENT); - NV_ASSERT_OR_RETURN(size != 0, NV_ERR_INVALID_ARGUMENT); - - // Check the alignment and size are pageSize aligned - NV_ASSERT_OR_RETURN(NV_IS_ALIGNED64(align, pageSize), NV_ERR_INVALID_ARGUMENT); - NV_ASSERT_OR_RETURN(NV_IS_ALIGNED64(size, pageSize), NV_ERR_INVALID_ARGUMENT); - - status = _fabricvaspaceBindInstBlk(pFabricVAS); - if (status != NV_OK) - { - NV_PRINTF(LEVEL_ERROR, "Failed to bind instance block for fabric vaspace." - " Alloc failed\n"); - return status; - } - - // Adjust rangeLo and rangeHi - rangeLo = NV_ALIGN_DOWN(rangeLo, pageSize); - rangeHi = NV_ALIGN_UP(rangeHi, pageSize); - // - // Allocate VA space of the size and alignment requested. - // RM_PAGE_SIZE_HUGE is passed since FLA->PA page size is 2MB or 512MB. + // TODO: If needed, can call into fabricvaspaceAllocNonContiguous_IMPL() + // by forcing contig flag. // - status = vaspaceAlloc(pFabricVAS->pGVAS, size, align, rangeLo, rangeHi, - RM_PAGE_SIZE_HUGE | RM_PAGE_SHIFT_512M, flags, pAddr); - if (status != NV_OK) - { - NV_PRINTF(LEVEL_ERROR, "Failed to allocate vaspace\n"); - goto failed; - } - - // Assert that the address returned is pageSize aligned - NV_ASSERT(NV_IS_ALIGNED64(*pAddr, pageSize)); - - pFabricVAS->ucFabricFreeSize -= size; - pFabricVAS->ucFabricInUseSize += size; - - return NV_OK; - -failed: - - _fabricvaspaceUnbindInstBlk(pFabricVAS); - - return status; + return NV_ERR_NOT_SUPPORTED; } NV_STATUS @@ -460,7 +423,9 @@ // // Attempt to allocate VA space of the size and alignment requested. - // RM_PAGE_SIZE_HUGE is passed since FLA->PA page size is 2MB. + // + // RM_PAGE_SIZE_HUGE is passed since FLA->PA mappings support minimum + // 2MB pagesize. // if (flags.bForceContig || bDefaultAllocMode) { @@ -480,8 +445,10 @@ // // If size could not be allocated in one memblock, break size into - // multiple pageSize chunks. RM_PAGE_SIZE_HUGE is passed since - // FLA->PA page size is 2MB. + // multiple pageSize chunks. + // + // RM_PAGE_SIZE_HUGE is passed since FLA->PA mappings support minimum + // 2MB pagesize. // if (flags.bForceNonContig || (bDefaultAllocMode && (status != NV_OK))) { @@ -541,7 +508,7 @@ NV_ASSERT(vaspaceFreeV2(pFabricVAS->pGVAS, vAddr, &blockSize) == NV_OK); kbusFlush_HAL(pGpu, pKernelBus, (BUS_FLUSH_VIDEO_MEMORY | - BUS_FLUSH_SYSTEM_MEMORY | + BUS_FLUSH_SYSTEM_MEMORY | BUS_FLUSH_USE_PCIE_READ)); fabricvaspaceInvalidateTlb(pFabricVAS, pGpu, PTE_DOWNGRADE); @@ -668,7 +635,8 @@ bUcFla = (pAddr[idx] >= fabricvaspaceGetUCFlaStart(pFabricVAS) && pAddr[idx] < fabricvaspaceGetUCFlaLimit(pFabricVAS)); - NV_ASSERT(vaspaceFreeV2(pFabricVAS->pGVAS, pAddr[idx], &freeSize) == NV_OK); + NV_ASSERT(vaspaceFreeV2(pFabricVAS->pGVAS, + pAddr[idx], &freeSize) == NV_OK); idx += stride; @@ -677,7 +645,7 @@ } kbusFlush_HAL(pGpu, pKernelBus, (BUS_FLUSH_VIDEO_MEMORY | - BUS_FLUSH_SYSTEM_MEMORY | + BUS_FLUSH_SYSTEM_MEMORY | BUS_FLUSH_USE_PCIE_READ)); fabricvaspaceInvalidateTlb(pFabricVAS, pGpu, PTE_DOWNGRADE); @@ -708,17 +676,23 @@ MEMORY_DESCRIPTOR **ppAdjustedMemdesc ) { - KernelNvlink *pKernelNvlink = GPU_GET_KERNEL_NVLINK(pMappingGpu); - MEMORY_DESCRIPTOR *pRootMemDesc = NULL; - NODE *pNode = NULL; - NV_STATUS status = NV_OK; - NvU64 rootOffset = 0; + KernelNvlink *pKernelNvlink = GPU_GET_KERNEL_NVLINK(pMappingGpu); + MEMORY_DESCRIPTOR *pRootMemDesc = NULL; + NODE *pNode = NULL; + NV_STATUS status = NV_OK; + NvU64 rootOffset = 0; + NvBool bLoopbackSupported = NV_FALSE; NV_ASSERT_OR_RETURN(ppAdjustedMemdesc != NULL, NV_ERR_INVALID_ARGUMENT); + { + bLoopbackSupported = pKernelNvlink != NULL && + (knvlinkIsP2pLoopbackSupported(pMappingGpu, pKernelNvlink) || + knvlinkIsForcedConfig(pMappingGpu, pKernelNvlink)); + } + if (memdescGetAddressSpace(pFabricMemdesc) != ADDR_FABRIC_V2 || - (pKernelNvlink != NULL && - knvlinkIsP2pLoopbackSupported(pMappingGpu, pKernelNvlink))) + bLoopbackSupported) { *ppAdjustedMemdesc = pFabricMemdesc; return NV_OK; @@ -737,28 +711,34 @@ } // - // If the address space is of type ADDR_FABRIC_V2 then determine if the FLA import - // is on the mapping GPU. If FLA import is on the mapping GPU and NVLink P2P over - // loopback is not supported, then map GVA->PA directly. For discontiguous fabric - // memory allocation, searching for the first entry in the pteArray should be fine - // to determine if FLA import is on the mapping GPU. + // If the address space is of type ADDR_FABRIC_V2 then determine if the + // FLA import is on the mapping GPU. If FLA import is on the mapping GPU + // and NVLink P2P over loopback is not supported, then map GVA->PA directly. + // For discontiguous fabric memory allocation, searching for the first entry + // in the pteArray should be fine to determine if FLA import is on the + // mapping GPU. // - NV_ASSERT_OK_OR_RETURN(btreeSearch(pteArray[0], &pNode, pFabricVAS->pFabricVaToGpaMap)); + NV_ASSERT_OK_OR_RETURN(btreeSearch(pteArray[0], &pNode, + pFabricVAS->pFabricVaToGpaMap)); - FABRIC_VA_TO_GPA_MAP_NODE *pFabricNode = (FABRIC_VA_TO_GPA_MAP_NODE *)pNode->Data; + FABRIC_VA_TO_GPA_MAP_NODE *pFabricNode = + (FABRIC_VA_TO_GPA_MAP_NODE *)pNode->Data; // - // Create a sub-memdesc for the offset into the vidMemDesc where the GVA would be - // mapped. Note this includes two offsets: + // Create a sub-memdesc for the offset into the vidMemDesc where the GVA + // would be mapped. Note this includes two offsets: // 1. Offset into the fabric memdesc where the GVA is mapped. - // 2. Offset into the physical vidmem memdesc where the fabric memory is mapped. + // 2. Offset into the physical vidmem memdesc where the fabric memory is + // mapped. // - status = memdescCreateSubMem(ppAdjustedMemdesc, pFabricNode->pVidMemDesc, pMappingGpu, + status = memdescCreateSubMem(ppAdjustedMemdesc, pFabricNode->pVidMemDesc, + pMappingGpu, rootOffset + pFabricNode->offset, memdescGetSize(pFabricMemdesc)); if (status != NV_OK) { - NV_PRINTF(LEVEL_ERROR, "Failed to create submMemdesc for the GVA->PA mapping\n"); + NV_PRINTF(LEVEL_ERROR, + "Failed to create submMemdesc for the GVA->PA mapping\n"); return status; } @@ -861,8 +841,12 @@ rangeLo = base; rangeHi = base + size - 1; + // + // RM_PAGE_SIZE_HUGE is passed since MCFLA->PA mappings support minimum + // 2MB pagesize. + // status = vaspaceAlloc(pFabricVAS->pGVAS, size, alignment, rangeLo, - rangeHi, pageSize, flags, &addr); + rangeHi, RM_PAGE_SIZE_HUGE, flags, &addr); NV_ASSERT(addr == base); @@ -874,11 +858,11 @@ ( NvU64 fabricOffset, NvU64 fabricAllocSize, - NvU32 fabricPageSize, + NvU64 fabricPageSize, NvU64 physMapOffset, NvU64 physMapLength, NvU64 physAllocSize, - NvU32 physPageSize + NvU64 physPageSize ) { // Fabric mem offset should be at least phys page size aligned. @@ -1004,7 +988,7 @@ fabricPageSize = memdescGetPageSize(pFabricMemDesc, AT_GPU); - NV_ASSERT_OR_RETURN_VOID(dynamicCast(pGpu->pFabricVAS, FABRIC_VASPACE) == \ + NV_ASSERT_OR_RETURN_VOID(dynamicCast(pGpu->pFabricVAS, FABRIC_VASPACE) == pFabricVAS); _fabricvaspaceGetMappingRegions(fabricOffset, fabricPageSize, physMapLength, @@ -1013,10 +997,13 @@ for (i = 0; i < numRegions; i++) { - fabricPageCount = ((memdescGetPteArraySize(pFabricMemDesc, AT_GPU) == 1) || - (regions.r[i].length < fabricPageSize)) ? \ - 1 : (regions.r[i].length / fabricPageSize); + fabricPageCount = + ((memdescGetPteArraySize(pFabricMemDesc, AT_GPU) == 1) || + (regions.r[i].length < fabricPageSize)) ? + 1 : (regions.r[i].length / fabricPageSize); + mapLength = (fabricPageCount == 1) ? regions.r[i].length : fabricPageSize; + fabricOffset = regions.r[i].offset; for (j = 0; j < fabricPageCount; j++) @@ -1027,10 +1014,11 @@ } else { - fabricAddr = pFabricMemDesc->_pteArray[fabricOffset / pFabricMemDesc->pageArrayGranularity]; + fabricAddr = pFabricMemDesc->_pteArray[fabricOffset / + pFabricMemDesc->pageArrayGranularity]; } - vaspaceUnmap(pFabricVAS->pGVAS, pPhysMemDesc->pGpu, fabricAddr, \ + vaspaceUnmap(pFabricVAS->pGVAS, pPhysMemDesc->pGpu, fabricAddr, fabricAddr + mapLength - 1); fabricOffset = fabricOffset + mapLength; @@ -1063,7 +1051,7 @@ DMA_UPDATE_VASPACE_FLAGS_SKIP_4K_PTE_CHECK; NvU32 fabricPageCount; NvU64 fabricAddr; - NvU32 physPageSize; + NvU64 physPageSize; NvU64 fabricPageSize; NvU64 physAddr; NvU32 i, j; @@ -1072,6 +1060,7 @@ FABRIC_VASPACE_MAPPING_REGIONS regions; NvU32 numRegions; MEMORY_DESCRIPTOR *pTempMemdesc; + NvU32 aperture; NV_ASSERT_OR_RETURN(pFabricMemDesc != NULL, NV_ERR_INVALID_ARGUMENT); NV_ASSERT_OR_RETURN(pPhysMemDesc != NULL, NV_ERR_INVALID_ARGUMENT); @@ -1100,6 +1089,27 @@ physOffset, &kind, &comprInfo); NV_ASSERT_OK_OR_RETURN(status); + if (memdescGetAddressSpace(pPhysMemDesc) == ADDR_FBMEM) + { + aperture = NV_MMU_PTE_APERTURE_VIDEO_MEMORY; + } + else if (memdescGetAddressSpace(pPhysMemDesc) == ADDR_SYSMEM) + { + if (memdescGetCpuCacheAttrib(pPhysMemDesc) == NV_MEMORY_CACHED) + { + aperture = NV_MMU_PTE_APERTURE_SYSTEM_COHERENT_MEMORY; + } + else + { + aperture = NV_MMU_PTE_APERTURE_SYSTEM_NON_COHERENT_MEMORY; + } + } + else + { + NV_PRINTF(LEVEL_ERROR, "Unsupported aperture\n"); + NV_ASSERT_OR_RETURN(0, NV_ERR_INVALID_ARGUMENT); + } + _fabricvaspaceGetMappingRegions(fabricOffset, fabricPageSize, physMapLength, ®ions, &numRegions); NV_ASSERT_OR_RETURN(numRegions != 0, NV_ERR_INVALID_ARGUMENT); @@ -1124,7 +1134,8 @@ } else { - fabricAddr = pFabricMemDesc->_pteArray[fabricOffset / pFabricMemDesc->pageArrayGranularity]; + fabricAddr = pFabricMemDesc->_pteArray[fabricOffset / + pFabricMemDesc->pageArrayGranularity]; } if (pageArray.count == 1) @@ -1134,7 +1145,8 @@ } else { - pageArray.pData = &pPhysMemDesc->_pteArray[physOffset / pPhysMemDesc->pageArrayGranularity]; + pageArray.pData = &pPhysMemDesc->_pteArray[physOffset / + pPhysMemDesc->pageArrayGranularity]; } // @@ -1162,9 +1174,10 @@ NULL, fabricAddr, fabricAddr + mapLength - 1, mapFlags, &pageArray, 0, &comprInfo, 0, NV_MMU_PTE_VALID_TRUE, - NV_MMU_PTE_APERTURE_VIDEO_MEMORY, + aperture, BUS_INVALID_PEER, NVLINK_INVALID_FABRIC_ADDR, - DMA_DEFER_TLB_INVALIDATE, NV_FALSE, fabricPageSize); + DMA_DEFER_TLB_INVALIDATE, NV_FALSE, + memdescGetPageSize(pTempMemdesc, AT_GPU)); if (pTempMemdesc != pPhysMemDesc) memdescDestroy(pTempMemdesc); @@ -1215,3 +1228,37 @@ return NV_OK; } +void +fabricvaspaceClearUCRange_IMPL +( + FABRIC_VASPACE *pFabricVAS +) +{ + pFabricVAS->ucFabricBase = 0; + pFabricVAS->ucFabricLimit = 0; + pFabricVAS->ucFabricInUseSize = 0; + pFabricVAS->ucFabricFreeSize = 0; +} + +NV_STATUS +fabricvaspaceGetPageLevelInfo_IMPL +( + FABRIC_VASPACE *pFabricVAS, + OBJGPU *pGpu, + NV90F1_CTRL_VASPACE_GET_PAGE_LEVEL_INFO_PARAMS *pParams +) +{ + OBJGVASPACE *pGVAS = dynamicCast(pFabricVAS->pGVAS, OBJGVASPACE); + NV_ASSERT_OR_RETURN(pGVAS != NULL, NV_ERR_OBJECT_NOT_FOUND); + + return gvaspaceGetPageLevelInfo(pGVAS, pGpu, pParams); +} + +NvBool +fabricvaspaceIsInUse_IMPL +( + FABRIC_VASPACE *pFabricVAS +) +{ + return gvaspaceIsInUse(dynamicCast(pFabricVAS->pGVAS, OBJGVASPACE)); +} diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/kernel/mem_mgr/fla_mem.c nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/kernel/mem_mgr/fla_mem.c --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/kernel/mem_mgr/fla_mem.c 2023-10-25 20:21:24.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/kernel/mem_mgr/fla_mem.c 2024-03-05 22:13:55.000000000 +0000 @@ -55,7 +55,7 @@ NvBool bContig; NvU32 hwResId = 0; NvU32 format = 0; - NvU32 pageSize = 0; + NvU64 pageSize = 0; NvU64 pageCount = 0; NvU64 newBase = 0; NvU64 flaBaseAddr = 0; @@ -227,7 +227,7 @@ if(!NV_IS_ALIGNED(flaBaseAddr, pageSize)) { NV_PRINTF(LEVEL_ERROR, - "flaBaseAsddr: 0x%llx is not aligned to page size: 0x%x\n", + "flaBaseAsddr: 0x%llx is not aligned to page size: 0x%llx\n", flaBaseAddr, pageSize); return NV_ERR_INVALID_ARGUMENT; } @@ -236,7 +236,7 @@ || (flaSize < pageSize) ) { - NV_PRINTF(LEVEL_ERROR, "flaSize: %llx is either 0 or less than page size: %x, gpu: %x\n", + NV_PRINTF(LEVEL_ERROR, "flaSize: %llx is either 0 or less than page size: %llx, gpu: %x\n", flaSize, pageSize, pGpu->gpuInstance); return NV_ERR_INVALID_ARGUMENT; } @@ -344,12 +344,13 @@ pAllocParams->base = newBase; pAllocParams->limit = flaSize - 1; NV_RM_RPC_ALLOC_OBJECT(pGpu, - pParams->hClient, - pParams->hParent, - pParams->hResource, - pParams->externalClassId, - pAllocParams, - status); + pParams->hClient, + pParams->hParent, + pParams->hResource, + pParams->externalClassId, + pAllocParams, + sizeof(*pAllocParams), + status); if (status != NV_OK) { diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/kernel/mem_mgr/gpu_vaspace.c nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/kernel/mem_mgr/gpu_vaspace.c --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/kernel/mem_mgr/gpu_vaspace.c 2023-10-25 20:21:25.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/kernel/mem_mgr/gpu_vaspace.c 2024-03-05 22:13:55.000000000 +0000 @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 2013-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2013-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -59,13 +59,15 @@ #define GMMU_PD1_VADDR_BIT_LO 29 -static const NvU32 pageSizes[VAS_PAGESIZE_IDX_MAX] = { +static const NvU64 pageSizes[] = { RM_PAGE_SIZE, RM_PAGE_SIZE_64K, RM_PAGE_SIZE_HUGE, RM_PAGE_SIZE_512M }; +static const NvU32 pageSizeCount = sizeof (pageSizes) / sizeof (*pageSizes); + static NV_STATUS _gvaspaceGpuStateConstruct ( @@ -441,8 +443,8 @@ if (pVAS->vasStart > pGVAS->vaStartServerRMOwned) { pGVAS->vaStartServerRMOwned = pVAS->vasStart + SPLIT_VAS_SERVER_RM_MANAGED_VA_START; - } - + } + pGVAS->vaLimitServerRMOwned = pGVAS->vaStartServerRMOwned + SPLIT_VAS_SERVER_RM_MANAGED_VA_SIZE - 1; @@ -482,31 +484,6 @@ return status; } - -static NvU32 -_gvaspacePageSizeToIdx -( - NvU64 pageSize -) -{ - switch (pageSize) - { - case RM_PAGE_SIZE: - return VAS_PAGESIZE_IDX_4K; - case RM_PAGE_SIZE_64K: - case RM_PAGE_SIZE_128K: - return VAS_PAGESIZE_IDX_BIG; - case RM_PAGE_SIZE_HUGE: - return VAS_PAGESIZE_IDX_HUGE; - case RM_PAGE_SIZE_512M: - return VAS_PAGESIZE_IDX_512M; - default: - NV_PRINTF(LEVEL_ERROR, "Invalid pageSize=0x%llx!\n", pageSize); - NV_ASSERT(0); - return 0; - } -} - NV_STATUS gvaspaceConstruct__IMPL ( @@ -558,7 +535,7 @@ { pGVAS->bIsAtsEnabled = NV_TRUE; NV_PRINTF(LEVEL_INFO, "ATS Enabled VaSpace\n"); - // + // // Initialize with invalid PASID value for sanity checking later during // PASID programming in HW. // For non-MODS case, PASID is programmed via control call @@ -665,7 +642,8 @@ // By default allocations will be routed within RM internal va range. pGVAS->bRMInternalRestrictedVaRange = NV_TRUE; - status = _gvaspaceReserveRange(pGVAS, pVAS->vasLimit + 1, pGVAS->vaLimitMax); + if (pVAS->vasLimit != pGVAS->vaLimitMax) + status = _gvaspaceReserveRange(pGVAS, pVAS->vasLimit + 1, pGVAS->vaLimitMax); } else { @@ -895,7 +873,7 @@ static NV_STATUS _gvaspaceFlaVaspaceDestruct ( - POBJGVASPACE pGVAS, + OBJGVASPACE *pGVAS, OBJGPU *pGpu ) { @@ -1102,8 +1080,7 @@ NvU64 pageSizeMask; NvU64 vaStartMin; NvU64 vaLimitMax; - NvU32 bigPageSize; - NvU64 maxPageSizeSupported; + NvU64 bigPageSize; NvU64 compPageSize; NvU64 extManagedAlign; NvU64 vaLimitExt; @@ -1133,14 +1110,8 @@ // Determine GPU's page size settings. pageSizeMask = mmuFmtAllPageSizes(pFmt->pRoot); - bigPageSize = (NvU32)(pageSizeMask & (RM_PAGE_SIZE_64K | RM_PAGE_SIZE_128K)); - // - // Set the max page size supported for the system to determine if we need to look into - // 512Mb page or not. - // - maxPageSizeSupported = (kgmmuIsPageSize512mbSupported(pKernelGmmu)? - RM_PAGE_SIZE_512M: (kgmmuIsHugePageSupported(pKernelGmmu) ? - RM_PAGE_SIZE_HUGE : bigPageSize)); + bigPageSize = pageSizeMask & (RM_PAGE_SIZE_64K | RM_PAGE_SIZE_128K); + compPageSize = pMemorySystemConfig->comprPageSize; // Determine externally managed VA alignment from big page table coverage. @@ -1178,7 +1149,6 @@ if (flags & VASPACE_FLAGS_RESTRICTED_RM_INTERNAL_VALIMITS) { NV_ASSERT_OR_RETURN(vaLimitInternal <= vaLimitMax, NV_ERR_INVALID_ARGUMENT); - NV_ASSERT_OR_RETURN(vaLimitInternal <= vaLimit, NV_ERR_INVALID_ARGUMENT); NV_ASSERT_OR_RETURN(vaStartInternal <= vaLimitInternal, NV_ERR_INVALID_ARGUMENT); NV_ASSERT_OR_RETURN(vaStartInternal >= vaStartMin, NV_ERR_INVALID_ARGUMENT); @@ -1205,7 +1175,6 @@ if (bFirst) { pGVAS->bigPageSize = bigPageSize; - pGVAS->maxPageSizeSupported = maxPageSizeSupported; pGVAS->compPageSize = compPageSize; pGVAS->extManagedAlign = extManagedAlign; @@ -1383,7 +1352,7 @@ status = pRmApi->AllocWithHandle(pRmApi, pKernelBus->flaInfo.hClient, pKernelBus->flaInfo.hSubDevice, pGpuState->flaDummyPage.hMemory, NV01_MEMORY_LOCAL_USER, - &memAllocParams); + &memAllocParams, sizeof(memAllocParams)); if (bAcquireLock) { @@ -2021,7 +1990,7 @@ return pGVAS->pHeap; } -NvU32 +NvU64 gvaspaceGetMapPageSize_IMPL ( OBJGVASPACE *pGVAS, @@ -2034,11 +2003,7 @@ const NvU64 pageSizeMask = mmuFmtAllPageSizes(pRootFmtLvl); NvU32 i; - // - // Though page size mask is 64 bits, we will loop only over 32 bits as the callers - // do not expect a pagsize more than 2^32 bytes - // - for (i = 0; i < 32; ++i) + for (i = 0; i < 64; ++i) { if (pageSizeMask & NVBIT64(i)) { @@ -2051,23 +2016,16 @@ (const MMU_WALK_MEMDESC**)&pMemDesc, &memSize); if (NULL != pMemDesc) { - return NVBIT32(i); + return NVBIT64(i); } } } - if ((pageSizeMask >> 32) != 0) - { - NV_PRINTF(LEVEL_ERROR, - "Time to update width of variables for page size. PageSizeMask: 0x%llx\n", - pageSizeMask); - } - NV_ASSERT(0); return 0; } -NvU32 +NvU64 gvaspaceGetBigPageSize_IMPL(OBJGVASPACE *pGVAS) { return pGVAS->bigPageSize; @@ -2119,7 +2077,7 @@ NV_PRINTF(LEVEL_INFO, "ATS enabled: %u PASID: %u\n", pGVAS->bIsAtsEnabled, pGVAS->processAddrSpaceId); - + NV_ASSERT_OR_RETURN(pGVAS->bIsAtsEnabled, NV_ERR_INVALID_STATE); NV_ASSERT_OR_RETURN(pGVAS->processAddrSpaceId != NV_U32_MAX, NV_ERR_INVALID_STATE); *pPasid = pGVAS->processAddrSpaceId; @@ -2458,10 +2416,13 @@ NV_ASSERT_OR_RETURN(pBigPageTable, NV_ERR_INVALID_EVENT); pParams->bigPageSize = pGVAS->bigPageSize; - pParams->hugePageSize = kgmmuIsHugePageSupported(pKernelGmmu) ? - RM_PAGE_SIZE_HUGE : 0; - pParams->pageSize512MB = kgmmuIsPageSize512mbSupported(pKernelGmmu) ? - RM_PAGE_SIZE_512M : 0; + pParams->supportedPageSizeMask = RM_PAGE_SIZE | pParams->bigPageSize; + + if (kgmmuIsHugePageSupported(pKernelGmmu)) + pParams->supportedPageSizeMask |= RM_PAGE_SIZE_HUGE; + + if (kgmmuIsPageSize512mbSupported(pKernelGmmu)) + pParams->supportedPageSizeMask |= RM_PAGE_SIZE_512M; // Dual Page Table is supported for all Fermi-and-later chips pParams->dualPageTableSupported = (NvU32)NV_TRUE; @@ -2508,7 +2469,6 @@ NvU32 i; NvBool bOrigBcState; NV_STATUS rmStatus; - NvU64 maxPageSizeSupported = pGVAS->maxPageSizeSupported; NV_ASSERT_OR_RETURN(NULL != pParams, NV_ERR_INVALID_PARAM_STRUCT); @@ -2535,7 +2495,7 @@ NV_ASSERT_OR_RETURN((NV_OK == rmStatus), rmStatus); - for (i = 0; i <= (_gvaspacePageSizeToIdx(maxPageSizeSupported)); i++) + for (i = 0; i < pageSizeCount; i++) { PMEMORY_DESCRIPTOR pMemDesc = NULL; NvU32 memSize = 0; @@ -2572,10 +2532,11 @@ pParams->pdeEntrySize = pParentFmt->entrySize; } + NV_ASSERT_OR_RETURN(pteBlockIdx < NV0080_CTRL_DMA_PDE_INFO_PTE_BLOCKS, NV_ERR_INVALID_STATE); pPteBlock = &pParams->pteBlocks[pteBlockIdx++]; // Page size supported by this page table - pPteBlock->pageSize = (NvU32)pageSize; + pPteBlock->pageSize = pageSize; // Phys addr of the Page Table pPteBlock->ptePhysAddr = memdescGetPhysAddr(pMemDesc, VAS_ADDRESS_TRANSLATION(pVAS), 0); @@ -2661,14 +2622,15 @@ ) { KernelGmmu *pKernelGmmu; + MemoryManager *pMemoryManager; GVAS_GPU_STATE *pGpuState; MMU_WALK *pWalk; const GMMU_FMT *pFmt; NV_STATUS status = NV_OK; NvU32 i; NvU32 pteBlockIndex = 0; - NvU64 maxPageSizeSupported = pGVAS->maxPageSizeSupported; const MMU_FMT_LEVEL *pRootFmt; + TRANSFER_SURFACE surf = {0}; NV_ASSERT_OR_RETURN(NULL != pParams, NV_ERR_INVALID_PARAM_STRUCT); @@ -2684,20 +2646,20 @@ pFmt = pGpuState->pFmt; pRootFmt = pFmt->pRoot; pKernelGmmu = GPU_GET_KERNEL_GMMU(pGpu); + pMemoryManager = GPU_GET_MEMORY_MANAGER(pGpu); // // We will try all available page sizes for valid allocation a the give VA. // Will flag error if mutiple valid allocations exist. // - for (i = 0; i <= (_gvaspacePageSizeToIdx(maxPageSizeSupported)); i++) + for (i = 0; i < pageSizeCount; i++) { NV0080_CTRL_DMA_PTE_INFO_PTE_BLOCK *pPteBlock = NULL; const GMMU_FIELD_ADDRESS *pAddrField; const MMU_FMT_LEVEL *pLevelFmt = NULL; PMEMORY_DESCRIPTOR pMemDesc = NULL; NvU32 memSize = 0; - NvU8 *pMap = NULL; NvU32 pteIndex; GMMU_ENTRY_VALUE pte = {{0}}; NvU64 pageSize; @@ -2720,28 +2682,19 @@ pteIndex = mmuFmtVirtAddrToEntryIndex(pLevelFmt, pParams->gpuAddr); - // Map the Page Table to BAR - pMap = kbusMapRmAperture_HAL(pGpu, pMemDesc); - NV_ASSERT_OR_RETURN(NULL != pMap, NV_ERR_INSUFFICIENT_RESOURCES); - portMemCopy(pte.v8, pLevelFmt->entrySize, pMap + (pteIndex * pLevelFmt->entrySize), pLevelFmt->entrySize); - kbusUnmapRmAperture_HAL(pGpu, pMemDesc, &pMap, NV_FALSE); + // Read the PTE + surf.pMemDesc = pMemDesc; + surf.offset = pteIndex * pLevelFmt->entrySize; + + NV_ASSERT_OK_OR_RETURN(memmgrMemRead(pMemoryManager, &surf, pte.v8, + pLevelFmt->entrySize, + TRANSFER_FLAGS_DEFER_FLUSH)); - if (pteBlockIndex <= _gvaspacePageSizeToIdx(maxPageSizeSupported)) - { - pPteBlock = &pParams->pteBlocks[pteBlockIndex++]; - } - else if (nvFieldGetBool(&pFmt->pPte->fldValid, pte.v8)) - { - // Override last block if the PTE is valid. - pPteBlock = &pParams->pteBlocks[pteBlockIndex - 1]; - } - else - { - break; - } + NV_ASSERT_OR_RETURN(pteBlockIndex < NV0080_CTRL_DMA_PDE_INFO_PTE_BLOCKS, NV_ERR_INVALID_STATE); + pPteBlock = &pParams->pteBlocks[pteBlockIndex++]; // Page size supported by this page table - pPteBlock->pageSize = (NvU32)pageSize; + pPteBlock->pageSize = pageSize; // Number of bytes occupied by one PTE pPteBlock->pteEntrySize = pLevelFmt->entrySize; @@ -2814,11 +2767,10 @@ { OBJVASPACE *pVAS = staticCast(pGVAS, OBJVASPACE); MemoryManager *pMemoryManager = GPU_GET_MEMORY_MANAGER(pGpu); - NvU8 *pMap = NULL; NvU8 i; NV_STATUS status = NV_OK; NvBool bDowngrade = NV_FALSE; - NvU64 maxPageSizeSupported = pGVAS->maxPageSizeSupported; + TRANSFER_SURFACE surf = {0}; NV_ASSERT_OR_RETURN(NULL != pParams, NV_ERR_INVALID_PARAM_STRUCT); @@ -2838,7 +2790,7 @@ goto catchGpu; } - for (i = 0; i <= (_gvaspacePageSizeToIdx(maxPageSizeSupported)); i++) + for (i = 0; i < NV0080_CTRL_DMA_SET_PTE_INFO_PTE_BLOCKS; i++) { NV0080_CTRL_DMA_PTE_INFO_PTE_BLOCK *pPteBlock = NULL; const MMU_FMT_LEVEL *pLevelFmt; @@ -2876,7 +2828,7 @@ // Query the Page Tables. pLevelFmt = mmuFmtFindLevelWithPageShift(pRootFmt, - BIT_IDX_32(pParams->pteBlocks[i].pageSize)); + BIT_IDX_64(pParams->pteBlocks[i].pageSize)); if (NULL == pLevelFmt) { status = NV_ERR_INVALID_STATE; @@ -2895,17 +2847,17 @@ pPteBlock = &pParams->pteBlocks[i]; - // Map the Page Table to BAR - pMap = kbusMapRmAperture_HAL(pGpu, pMemDesc); - if (NULL == pMap) - { - status = NV_ERR_INSUFFICIENT_RESOURCES; - NV_ASSERT_OR_GOTO(0, catchGpu); - } - // Read the PTE pteIndex = mmuFmtVirtAddrToEntryIndex(pLevelFmt, pParams->gpuAddr); - portMemCopy(pte.v8, pLevelFmt->entrySize, pMap + (pteIndex * pLevelFmt->entrySize), pLevelFmt->entrySize); + + surf.pMemDesc = pMemDesc; + surf.offset = pteIndex * pLevelFmt->entrySize; + + NV_ASSERT_OK_OR_GOTO(status, + memmgrMemRead(pMemoryManager, &surf, pte.v8, + pLevelFmt->entrySize, + TRANSFER_FLAGS_NONE), + catchGpu); // // If any of these entries are being downgraded, we need to perform @@ -3005,12 +2957,13 @@ } } - - - // Copy back the overwritten values to the actual PTE memory - portMemCopy(pMap + (pteIndex * pLevelFmt->entrySize), pLevelFmt->entrySize, pte.v8, pLevelFmt->entrySize); - kbusUnmapRmAperture_HAL(pGpu, pMemDesc, &pMap, NV_TRUE); + NV_ASSERT_OK_OR_GOTO(status, + memmgrMemWrite(pMemoryManager, &surf, pte.v8, + pLevelFmt->entrySize, + TRANSFER_FLAGS_NONE), + catchGpu); + } // Invalidate TLB @@ -3584,10 +3537,11 @@ NvU32 *pProgress ) { - OBJGPU *pGpu = pUserCtx->pGpu; - MMU_MAP_ITERATOR *pIter = pTarget->pIter; - MEMORY_DESCRIPTOR *pMemDesc = (MEMORY_DESCRIPTOR*)pLevelMem; - NvU8 *pMap = NULL; + OBJGPU *pGpu = pUserCtx->pGpu; + MemoryManager *pMemoryManager = GPU_GET_MEMORY_MANAGER(pGpu); + MMU_MAP_ITERATOR *pIter = pTarget->pIter; + MEMORY_DESCRIPTOR *pMemDesc = (MEMORY_DESCRIPTOR*)pLevelMem; + TRANSFER_SURFACE surf = {0}; NV_PRINTF(LEVEL_INFO, "[GPU%u]: PA 0x%llX, Entries 0x%X-0x%X\n", pUserCtx->pGpu->gpuInstance, @@ -3596,15 +3550,13 @@ NV_ASSERT_OR_RETURN_VOID(entryIndexLo == entryIndexHi); - pMap = kbusMapRmAperture_HAL(pGpu, pMemDesc); - NV_ASSERT_OR_RETURN_VOID(NULL != pMap); - - portMemCopy(pMap + entryIndexLo * pTarget->pLevelFmt->entrySize, - pTarget->pLevelFmt->entrySize, - pIter->entry.v8, - pTarget->pLevelFmt->entrySize); - - kbusUnmapRmAperture_HAL(pGpu, pMemDesc, &pMap, NV_TRUE); + surf.pMemDesc = pMemDesc; + surf.offset = entryIndexLo * pTarget->pLevelFmt->entrySize; + + NV_ASSERT_OR_RETURN_VOID(memmgrMemWrite(pMemoryManager, &surf, + pIter->entry.v8, + pTarget->pLevelFmt->entrySize, + TRANSFER_FLAGS_NONE) == NV_OK); *pProgress = entryIndexHi - entryIndexLo + 1; } @@ -3635,7 +3587,7 @@ // Lookup leaf page table formats. pPTBig = mmuFmtFindLevelWithPageShift(pFmt->pRoot, - BIT_IDX_32(gvaspaceGetBigPageSize(pGVAS))); + BIT_IDX_64(gvaspaceGetBigPageSize(pGVAS))); pPT4KB = mmuFmtFindLevelWithPageShift(pFmt->pRoot, 12); NV_ASSERT_OR_RETURN(NULL != pPTBig, NV_ERR_NOT_SUPPORTED); @@ -3693,6 +3645,7 @@ if (GMMU_APERTURE_INVALID != aperture) { KernelGmmu *pKernelGmmu = GPU_GET_KERNEL_GMMU(pGpu); + MemoryManager *pMemoryManager = GPU_GET_MEMORY_MANAGER(pGpu); gmmuFieldSetAddress(gmmuFmtPdePhysAddrFld(pPdeFmt, aperture), kgmmuEncodePhysAddr(pKernelGmmu, aperture, pPtParams->physAddr, @@ -3705,21 +3658,22 @@ NvU32 pdePcfSw = 0; PMEMORY_DESCRIPTOR pMemDesc = NULL; NvU32 memSize = 0; - NvU8 *pMap = NULL; GMMU_ENTRY_VALUE pde = {{0}}; GMMU_APERTURE currAperture; + TRANSFER_SURFACE surf = {0}; NV_ASSERT_OK_OR_RETURN( mmuWalkGetPageLevelInfo(pGpuState->pWalk, mapTarget.pLevelFmt, (pParams->pdeIndex * mmuFmtLevelPageSize(mapTarget.pLevelFmt)), (const MMU_WALK_MEMDESC**)&pMemDesc, &memSize)); - pMap = kbusMapRmAperture_HAL(pGpu, pMemDesc); - NV_ASSERT_OR_RETURN(pMap != NULL, NV_ERR_INSUFFICIENT_RESOURCES); - portMemCopy(pde.v8, mapTarget.pLevelFmt->entrySize, - pMap + (pParams->pdeIndex * mapTarget.pLevelFmt->entrySize), - mapTarget.pLevelFmt->entrySize); - kbusUnmapRmAperture_HAL(pGpu, pMemDesc, &pMap, NV_FALSE); + surf.pMemDesc = pMemDesc; + surf.offset = pParams->pdeIndex * mapTarget.pLevelFmt->entrySize; + + NV_ASSERT_OK_OR_RETURN(memmgrMemRead(pMemoryManager, &surf, + pde.v8, + mapTarget.pLevelFmt->entrySize, + TRANSFER_FLAGS_DEFER_FLUSH)); pdePcfHw = nvFieldGet32(&pPdeFmt->fldPdePcf, pde.v8); currAperture = gmmuFieldGetAperture(&pPdeFmt->fldAperture, pde.v8); @@ -4100,7 +4054,7 @@ NvBool bFreeNeeded = NV_FALSE; NvHandle hDevice; NvHandle hVASpace; - POBJGPUGRP pGpuGrp = gpumgrGetGpuGrpFromGpu(pGpu); + OBJGPUGRP *pGpuGrp = gpumgrGetGpuGrpFromGpu(pGpu); if (NULL != pContext) { @@ -4154,6 +4108,7 @@ hVASpace, FERMI_VASPACE_A, &vaParams, + sizeof(vaParams), status); NV_ASSERT_OR_RETURN(NV_OK == status, status); @@ -4222,9 +4177,15 @@ if (0 != hSubDevice) { - NvHandle hDevice; - NV_ASSERT_OR_RETURN(CliSetSubDeviceContext(RES_GET_CLIENT_HANDLE(pVaspaceApi), hSubDevice, &hDevice, ppGpu) == NV_OK, - NV_ERR_INVALID_OBJECT); + Subdevice *pSubDevice; + + NV_ASSERT_OK_OR_RETURN( + subdeviceGetByHandle(RES_GET_CLIENT(pVaspaceApi), + hSubDevice, &pSubDevice)); + + *ppGpu = GPU_RES_GET_GPU(pSubDevice); + + GPU_RES_SET_THREAD_BC_STATE(pSubDevice); } else { @@ -5154,7 +5115,7 @@ portMemSet(pPdeCopyParams, 0, sizeof(NV90F1_CTRL_VASPACE_COPY_SERVER_RESERVED_PDES_PARAMS)); // Populate the input params. - pdeInfo.pageSize = NVBIT32(GMMU_PD1_VADDR_BIT_LO); + pdeInfo.pageSize = NVBIT64(GMMU_PD1_VADDR_BIT_LO); pdeInfo.virtAddress = pGVAS->vaStartServerRMOwned; // Fetch the details of the PDEs backing server RM's VA range. @@ -5172,7 +5133,7 @@ pPdeCopyParams->numLevelsToCopy = pdeInfo.numLevels; pPdeCopyParams->subDeviceId = gpumgrGetSubDeviceInstanceFromGpu(pGpu); - pPdeCopyParams->pageSize = NVBIT32(GMMU_PD1_VADDR_BIT_LO); + pPdeCopyParams->pageSize = NVBIT64(GMMU_PD1_VADDR_BIT_LO); pPdeCopyParams->virtAddrLo = pGVAS->vaStartServerRMOwned; pPdeCopyParams->virtAddrHi = pPdeCopyParams->virtAddrLo + SPLIT_VAS_SERVER_RM_MANAGED_VA_SIZE - 1; diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/kernel/mem_mgr/mem.c nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/kernel/mem_mgr/mem.c --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/kernel/mem_mgr/mem.c 2023-10-25 20:21:25.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/kernel/mem_mgr/mem.c 2024-03-05 22:13:55.000000000 +0000 @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 2018-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2018-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -857,7 +857,7 @@ } NV_CHECK_OK_OR_GOTO(status, LEVEL_ERROR, - memCheckCopyPermissions(pMemorySrc, pDstGpu, pDstClient->hClient), done); + memCheckCopyPermissions(pMemorySrc, pDstGpu, pDstDevice), done); // Initialize Memory pMemoryDst->categoryClassId = pMemorySrc->categoryClassId; diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/kernel/mem_mgr/mem_fabric.c nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/kernel/mem_mgr/mem_fabric.c --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/kernel/mem_mgr/mem_fabric.c 2023-10-25 20:21:25.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/kernel/mem_mgr/mem_fabric.c 2024-03-05 22:13:56.000000000 +0000 @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 2021-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2021-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -61,7 +61,7 @@ ) { OBJGPU *pGpu = pMemDesc->pGpu; - NvU32 pageSize = 0; + NvU64 pageSize = 0; // Get the page size from the memory descriptor. pageSize = memdescGetPageSize(pMemDesc, @@ -88,9 +88,10 @@ MEMORY_DESCRIPTOR **ppPhysMemDesc ) { + MemoryManager *pMemoryManager = GPU_GET_MEMORY_MANAGER(pOwnerGpu); RsResourceRef *pPhysmemRef; MEMORY_DESCRIPTOR *pPhysMemDesc; - NvU32 physPageSize; + NvU64 physPageSize; NV_STATUS status; Memory *pMemory; @@ -124,8 +125,9 @@ return NV_ERR_INVALID_OBJECT_HANDLE; } - if ((memdescGetAddressSpace(pPhysMemDesc) != ADDR_FBMEM) || - (pOwnerGpu != pPhysMemDesc->pGpu)) + if ((pOwnerGpu != pPhysMemDesc->pGpu) || + !memmgrIsApertureSupportedByFla_HAL(pOwnerGpu, pMemoryManager, + memdescGetAddressSpace(pPhysMemDesc))) { NV_PRINTF(LEVEL_ERROR, "Invalid physmem handle passed\n"); @@ -133,8 +135,9 @@ } physPageSize = memdescGetPageSize(pPhysMemDesc, AT_GPU); - if ((physPageSize != NV_MEMORY_FABRIC_PAGE_SIZE_2M) && - (physPageSize != NV_MEMORY_FABRIC_PAGE_SIZE_512M)) + if ( + (physPageSize != RM_PAGE_SIZE_HUGE) && + (physPageSize != RM_PAGE_SIZE_512M)) { NV_PRINTF(LEVEL_ERROR, "Physmem page size should be 2MB\n"); @@ -234,6 +237,13 @@ return NV_ERR_NOT_SUPPORTED; } + if (gpuIsCCFeatureEnabled(pGpu)) + { + NV_PRINTF(LEVEL_ERROR, + "Unsupported when Confidential Computing is enabled\n"); + return NV_ERR_NOT_SUPPORTED; + } + status = _memoryfabricValidatePhysMem(RES_GET_CLIENT_HANDLE(pMemory), pAttachInfo->hMemory, pGpu, &pPhysMemDesc); @@ -273,6 +283,7 @@ pNode->node.keyStart = pAttachInfo->offset; pNode->node.keyEnd = pAttachInfo->offset; + pNode->physMapOffset = pAttachInfo->mapOffset; pNode->physMapLength = pAttachInfo->mapLength; pNode->pPhysMemDesc = pPhysMemDesc; pNode->hDupedPhysMem = hDupedPhysMem; @@ -291,7 +302,8 @@ portMemFree(pNode); unmapVas: - fabricvaspaceUnmapPhysMemdesc(pFabricVAS, pFabricMemDesc, pAttachInfo->offset, + fabricvaspaceUnmapPhysMemdesc(pFabricVAS, pFabricMemDesc, + pAttachInfo->offset, pPhysMemDesc, pAttachInfo->mapLength); freeDupedMem: @@ -313,16 +325,18 @@ RmPhysAddr *pteArray; FABRIC_MEMDESC_DATA *pMemdescData; NvU32 numAddr; - NvU32 pageSize; + NvU64 pageSize; NV_ASSERT_OR_RETURN_VOID(pGpu->pFabricVAS != NULL); pFabricVAS = dynamicCast(pGpu->pFabricVAS, FABRIC_VASPACE); pMemdescData = (FABRIC_MEMDESC_DATA *)memdescGetMemData(pMemDesc); - pteArray = memdescGetPteArrayForGpu(pMemDesc, pGpu, VAS_ADDRESS_TRANSLATION(pGpu->pFabricVAS)); + pteArray = memdescGetPteArrayForGpu(pMemDesc, pGpu, + VAS_ADDRESS_TRANSLATION(pGpu->pFabricVAS)); numAddr = _memoryfabricMemDescGetNumAddr(pMemDesc); // Get the page size from the memory descriptor. - pageSize = memdescGetPageSize(pMemDesc, VAS_ADDRESS_TRANSLATION(pGpu->pFabricVAS)); + pageSize = memdescGetPageSize(pMemDesc, + VAS_ADDRESS_TRANSLATION(pGpu->pFabricVAS)); // Remove the fabric memory allocations from the map. fabricvaspaceVaToGpaMapRemove(pFabricVAS, pteArray[0]); @@ -334,10 +348,11 @@ { // // Call fabricvaspaceBatchFree to free the FLA allocations. - // _pteArray in memdesc is RM_PAGE_SIZE whereas page size for memory fabric - // allocations is either 2MB or 512MB. Pass stride accordingly. + // _pteArray in memdesc is RM_PAGE_SIZE whereas page size for memory + // fabric allocations is either 2MB or 512MB. Pass stride accordingly. // - fabricvaspaceBatchFree(pFabricVAS, pteArray, numAddr, (pageSize >> RM_PAGE_SHIFT)); + fabricvaspaceBatchFree(pFabricVAS, pteArray, numAddr, + (pageSize >> RM_PAGE_SHIFT)); } if (pMemdescData != NULL) @@ -409,12 +424,14 @@ pParams->hResource, pParams->externalClassId, pAllocParams, + sizeof(*pAllocParams), status); if (status != NV_OK) { - NV_PRINTF(LEVEL_ERROR, "Alloc NV_MEMORY_FABRIC RPC failed, status: %x\n", - status); + NV_PRINTF(LEVEL_ERROR, + "Alloc NV_MEMORY_FABRIC RPC failed, status: %x\n", + status); return status; } @@ -438,14 +455,16 @@ if (status != NV_OK) { NV_PRINTF(LEVEL_ERROR, "CTRL_CMD_DESCRIBE failed, status: 0x%x, " - "numPfns: 0x%x, totalPfns: 0x%llx, readSoFar: 0x%x \n", - status, pDescribeParams->numPfns, pDescribeParams->totalPfns, idx); + "numPfns: 0x%x, totalPfns: 0x%llx, readSoFar: 0x%x \n", + status, pDescribeParams->numPfns, + pDescribeParams->totalPfns, idx); goto cleanup; } if (pAddr == NULL) { - pAddr = portMemAllocNonPaged(sizeof(NvU64) * pDescribeParams->totalPfns); + pAddr = portMemAllocNonPaged(sizeof(NvU64) * + pDescribeParams->totalPfns); if (pAddr == NULL) { status = NV_ERR_NO_MEMORY; @@ -455,7 +474,8 @@ for (i=0; i < pDescribeParams->numPfns; i++) { - pAddr[idx + i] = (NvU64)((NvU64)pDescribeParams->pfnArray[i] << RM_PAGE_SHIFT_HUGE); + pAddr[idx + i] = + (NvU64)((NvU64)pDescribeParams->pfnArray[i] << RM_PAGE_SHIFT_HUGE); } idx += pDescribeParams->numPfns; @@ -515,25 +535,25 @@ RS_RES_ALLOC_PARAMS_INTERNAL *pParams ) { - Memory *pMemory = staticCast(pMemoryFabric, Memory); - OBJGPU *pGpu = pMemory->pGpu; - FABRIC_VASPACE *pFabricVAS = dynamicCast(pGpu->pFabricVAS, FABRIC_VASPACE); + Memory *pMemory = staticCast(pMemoryFabric, Memory); + OBJGPU *pGpu = pMemory->pGpu; + FABRIC_VASPACE *pFabricVAS = dynamicCast(pGpu->pFabricVAS, FABRIC_VASPACE); NV00F8_ALLOCATION_PARAMETERS *pAllocParams = pParams->pAllocParams; - RM_API *pRmApi = rmapiGetInterface(RMAPI_GPU_LOCK_INTERNAL); - MemoryManager *pMemoryManager = GPU_GET_MEMORY_MANAGER(pGpu); - MEMORY_DESCRIPTOR *pPhysMemDesc = NULL; - NV_STATUS status = NV_OK; - MEMORY_DESCRIPTOR *pMemDesc = NULL; - FABRIC_MEMDESC_DATA *pMemdescData = NULL; - MEM_DESC_DESTROY_CALLBACK *pCallback = NULL; - VAS_ALLOC_FLAGS flags = {0}; - NvU64 *pAddr = NULL; - NvU32 numAddr = 0; - NvU32 pteKind = 0; - NvBool bReadOnly = NV_FALSE; - NvHandle hPhysMem; - NvBool bFlexible = NV_FALSE; - NvU32 mapFlags = 0; + RM_API *pRmApi = rmapiGetInterface(RMAPI_GPU_LOCK_INTERNAL); + MemoryManager *pMemoryManager = GPU_GET_MEMORY_MANAGER(pGpu); + MEMORY_DESCRIPTOR *pPhysMemDesc = NULL; + NV_STATUS status = NV_OK; + MEMORY_DESCRIPTOR *pMemDesc = NULL; + FABRIC_MEMDESC_DATA *pMemdescData = NULL; + MEM_DESC_DESTROY_CALLBACK *pCallback = NULL; + VAS_ALLOC_FLAGS flags = {0}; + NvU64 *pAddr = NULL; + NvU32 numAddr = 0; + NvU32 pteKind = 0; + NvBool bReadOnly = NV_FALSE; + NvHandle hPhysMem; + NvBool bFlexible = NV_FALSE; + NvU32 mapFlags = 0; if (RS_IS_COPY_CTOR(pParams)) { @@ -552,18 +572,19 @@ return NV_ERR_NOT_SUPPORTED; } - // initialize Fabric VAS Unicast range if not already setup + // initialize Fabric VAS Unicast range if not already setup if (fabricvaspaceGetUCFlaLimit(pFabricVAS) == 0) { - NV_PRINTF(LEVEL_ERROR, "UC FLA ranges should be initialized by this time!\n"); + NV_PRINTF(LEVEL_ERROR, + "UC FLA ranges should be initialized by this time!\n"); return NV_ERR_INVALID_STATE; } - // Only page size 512MB and 2MB supported. - if ((pAllocParams->pageSize != NV_MEMORY_FABRIC_PAGE_SIZE_512M) && + if ( + (pAllocParams->pageSize != NV_MEMORY_FABRIC_PAGE_SIZE_512M) && (pAllocParams->pageSize != NV_MEMORY_FABRIC_PAGE_SIZE_2M)) { - NV_PRINTF(LEVEL_ERROR, "Unsupported pageSize: 0x%x\n", + NV_PRINTF(LEVEL_ERROR, "Unsupported pageSize: 0x%llx\n", pAllocParams->pageSize); return NV_ERR_INVALID_ARGUMENT; @@ -589,15 +610,6 @@ bFlexible = !!(pAllocParams->allocFlags & NV00F8_ALLOC_FLAGS_FLEXIBLE_FLA); - // We don't support flexible mappings yet. - if (bFlexible) - { - NV_PRINTF(LEVEL_ERROR, - "Only sticky mappings are supported\n"); - - return NV_ERR_INVALID_ARGUMENT; - } - if (pAllocParams->allocFlags & NV00F8_ALLOC_FLAGS_READ_ONLY) { #if !defined(DEVELOP) && !defined(DEBUG) && !RMCFG_FEATURE_MODS_FEATURES @@ -641,7 +653,7 @@ { NV_PRINTF(LEVEL_ERROR, "VA Space alloc failed! Status Code: 0x%x Size: 0x%llx " - "RangeLo: 0x%llx, RangeHi: 0x%llx, page size: 0x%x\n", + "RangeLo: 0x%llx, RangeHi: 0x%llx, page size: 0x%llx\n", status, pAllocParams->allocSize, fabricvaspaceGetUCFlaStart(pFabricVAS), fabricvaspaceGetUCFlaLimit(pFabricVAS), @@ -720,7 +732,7 @@ // Associate the memdescDestroy callback function. pCallback->pObject = (void *)pCallback; pCallback->destroyCallback = - (MemDescDestroyCallBack*) &_memoryfabricMemDescDestroyCallback; + (MemDescDestroyCallBack*) &_memoryfabricMemDescDestroyCallback; memdescAddDestroyCallback(pMemDesc, pCallback); @@ -733,9 +745,11 @@ if (hPhysMem != 0) { // Dup the physical memory handle and cache it in memfabric memdesc. - status = pRmApi->DupObject(pRmApi, pFabricVAS->hClient, pFabricVAS->hDevice, - &pMemdescData->hDupedPhysMem, pCallContext->pClient->hClient, - hPhysMem, 0); + status = pRmApi->DupObject(pRmApi, pFabricVAS->hClient, + pFabricVAS->hDevice, + &pMemdescData->hDupedPhysMem, + pCallContext->pClient->hClient, + hPhysMem, 0); if (status != NV_OK) { @@ -747,7 +761,7 @@ NV0041_CTRL_GET_SURFACE_INFO_PARAMS surfaceInfoParam = {0}; surfaceInfo[0].index = NV0041_CTRL_SURFACE_INFO_INDEX_ADDR_SPACE_TYPE; - surfaceInfo[1].index = NV0041_CTRL_SURFACE_INFO_INDEX_COMPR_COVERAGE; + surfaceInfo[1].index = NV0041_CTRL_SURFACE_INFO_INDEX_ATTRS; surfaceInfoParam.surfaceInfoListSize = 2; surfaceInfoParam.surfaceInfoList = NvP64_VALUE(&surfaceInfo); @@ -764,7 +778,14 @@ } pMemdescData->physAttrs.addressSpace = surfaceInfo[0].data; - pMemdescData->physAttrs.compressionCoverage = surfaceInfo[1].data; + // + // TODO: Bug 4322867: use NV0041_CTRL_SURFACE_INFO_ATTRS_COMPR + // instead of NV0041_CTRL_SURFACE_INFO_INDEX_COMPR_COVERAGE. + // NV0041_CTRL_SURFACE_INFO_INDEX_COMPR_COVERAGE is buggy and + // will be removed soon. + // + pMemdescData->physAttrs.compressionCoverage = + (surfaceInfo[1].data & NV0041_CTRL_SURFACE_INFO_ATTRS_COMPR) ? 0x1 : 0x0; mapFlags |= bReadOnly ? FABRIC_VASPACE_MAP_FLAGS_READ_ONLY : 0; @@ -789,7 +810,8 @@ // No need to unmap on failure. Unmap happens implicitly when fabric VA // would be freed. // - status = fabricvaspaceVaToGpaMapInsert(pFabricVAS, pAddr[0], pPhysMemDesc, + status = fabricvaspaceVaToGpaMapInsert(pFabricVAS, pAddr[0], + pPhysMemDesc, pAllocParams->map.offset); if (status != NV_OK) goto freeDupedMem; @@ -943,8 +965,8 @@ if (pParams->offset >= pParams->totalPfns) { - NV_PRINTF(LEVEL_ERROR, "offset: %llx is out of range: %llx \n", pParams->offset, - pParams->totalPfns); + NV_PRINTF(LEVEL_ERROR, "offset: %llx is out of range: %llx \n", + pParams->offset, pParams->totalPfns); return NV_ERR_OUT_OF_RANGE; } @@ -957,8 +979,8 @@ return NV_ERR_NO_MEMORY; offset = pParams->offset * pageSize; - memdescGetPhysAddrsForGpu(pMemory->pMemDesc, pMemory->pMemDesc->pGpu, AT_GPU, offset, - pageSize, pParams->numPfns, + memdescGetPhysAddrsForGpu(pMemory->pMemDesc, pMemory->pMemDesc->pGpu, + AT_GPU, offset, pageSize, pParams->numPfns, pFabricArray); for (i = 0; i < pParams->numPfns; i++) @@ -1032,4 +1054,201 @@ } return NV_OK; +} + +NV_STATUS +memoryfabricCtrlGetNumAttachedMem_IMPL +( + MemoryFabric *pMemoryFabric, + NV00F8_CTRL_GET_NUM_ATTACHED_MEM_PARAMS *pParams +) +{ + Memory *pMemory = staticCast(pMemoryFabric, Memory); + MEMORY_DESCRIPTOR *pFabricMemDesc = pMemory->pMemDesc; + FABRIC_MEMDESC_DATA *pMemdescData = \ + (FABRIC_MEMDESC_DATA *)memdescGetMemData(pFabricMemDesc); + NODE *pNode = NULL; + + pParams->numMemInfos = 0; + + btreeEnumStart(pParams->offsetStart, &pNode, + pMemdescData->pAttachMemInfoTree); + + while ((pNode != NULL) && (pNode->keyStart <= pParams->offsetEnd)) + { + pParams->numMemInfos++; + btreeEnumNext(&pNode, pMemdescData->pAttachMemInfoTree); + } + + return NV_OK; +} + +NV_STATUS +memoryfabricCtrlGetAttachedMem_IMPL +( + MemoryFabric *pMemoryFabric, + NV00F8_CTRL_GET_ATTACHED_MEM_PARAMS *pParams +) +{ + NV_STATUS status; + Memory *pMemory = staticCast(pMemoryFabric, Memory); + MEMORY_DESCRIPTOR *pFabricMemDesc = pMemory->pMemDesc; + FABRIC_MEMDESC_DATA *pMemdescData = \ + (FABRIC_MEMDESC_DATA *)memdescGetMemData(pFabricMemDesc); + OBJGPU *pGpu = pMemory->pGpu; + RM_API *pRmApi = rmapiGetInterface(RMAPI_GPU_LOCK_INTERNAL); + FABRIC_VASPACE *pFabricVAS = dynamicCast(pGpu->pFabricVAS, FABRIC_VASPACE); + FABRIC_ATTCH_MEM_INFO_NODE *pAttachMemInfoNode; + NODE *pNode = NULL; + NvU16 i, count = 0; + + if ((pParams->numMemInfos == 0) || + (pParams->numMemInfos > NV00F8_MAX_ATTACHED_MEM_INFOS)) + return NV_ERR_INVALID_ARGUMENT; + + btreeEnumStart(pParams->offsetStart, &pNode, + pMemdescData->pAttachMemInfoTree); + + while (count < pParams->numMemInfos) + { + if (pNode == NULL) + { + status = NV_ERR_INVALID_ARGUMENT; + goto cleanup; + } + + pAttachMemInfoNode = (FABRIC_ATTCH_MEM_INFO_NODE *)pNode->Data; + + status = pRmApi->DupObject(pRmApi, RES_GET_CLIENT_HANDLE(pMemory), + RES_GET_HANDLE(pMemory->pDevice), + &pParams->memInfos[count].hMemory, + pFabricVAS->hClient, + pAttachMemInfoNode->hDupedPhysMem, 0); + if (status != NV_OK) + { + NV_PRINTF(LEVEL_ERROR, "Failed to dup physmem handle\n"); + goto cleanup; + } + + pParams->memInfos[count].offset = pNode->keyStart; + pParams->memInfos[count].mapOffset = pAttachMemInfoNode->physMapOffset; + pParams->memInfos[count].mapLength = pAttachMemInfoNode->physMapLength; + + btreeEnumNext(&pNode, pMemdescData->pAttachMemInfoTree); + count++; + } + + return NV_OK; + +cleanup: + for (i = 0; i < count; i++) + { + NV_ASSERT_OK(pRmApi->Free(pRmApi, RES_GET_CLIENT_HANDLE(pMemory), + pParams->memInfos[i].hMemory)); + pParams->memInfos[i].offset = 0; + pParams->memInfos[i].mapOffset = 0; + pParams->memInfos[i].mapLength = 0; + } + + return status; +} + +static NV_STATUS +_memoryfabricGetPhysAttrsUsingFabricMemdesc +( + OBJGPU *pGpu, + FABRIC_VASPACE *pFabricVAS, + MEMORY_DESCRIPTOR *pFabricMemDesc, + NvU64 offset, + NvU64 *pPhysPageSize +) +{ + NV_STATUS status; + MEMORY_DESCRIPTOR *pPhysMemDesc; + FABRIC_MEMDESC_DATA *pMemdescData; + NODE *pNode = NULL; + FABRIC_ATTCH_MEM_INFO_NODE *pAttachMemInfoNode; + + if ((pFabricMemDesc == NULL) || (pPhysPageSize == NULL)) + { + return NV_ERR_INVALID_ARGUMENT; + } + + status = fabricvaspaceGetGpaMemdesc(pFabricVAS, pFabricMemDesc, pGpu, + &pPhysMemDesc); + if (status == NV_OK) + { + *pPhysPageSize = memdescGetPageSize(pPhysMemDesc, AT_GPU); + memdescDestroy(pPhysMemDesc); + return NV_OK; + } + + if (status != NV_ERR_OBJECT_NOT_FOUND) + return status; + + // If the object is flexible, check the attach mem info tree. + pMemdescData = (FABRIC_MEMDESC_DATA *)memdescGetMemData(pFabricMemDesc); + NV_CHECK_OK_OR_RETURN(LEVEL_ERROR, btreeSearch(offset, &pNode, + pMemdescData->pAttachMemInfoTree)); + pAttachMemInfoNode = (FABRIC_ATTCH_MEM_INFO_NODE*)pNode->Data; + + *pPhysPageSize = memdescGetPageSize(pAttachMemInfoNode->pPhysMemDesc, + AT_GPU); + + return NV_OK; +} + +NV_STATUS +memoryfabricCtrlGetPageLevelInfo_IMPL +( + MemoryFabric *pMemoryFabric, + NV00F8_CTRL_GET_PAGE_LEVEL_INFO_PARAMS *pParams +) +{ + Memory *pMemory = staticCast(pMemoryFabric, Memory); + OBJGPU *pGpu = pMemory->pGpu; + FABRIC_VASPACE *pFabricVAS = dynamicCast(pGpu->pFabricVAS, FABRIC_VASPACE); + NV90F1_CTRL_VASPACE_GET_PAGE_LEVEL_INFO_PARAMS pageLevelInfoParams = {0}; + MEMORY_DESCRIPTOR *pFabricMemDesc = pMemory->pMemDesc; + NvU64 fabricAddr; + NvU64 mappingPageSize; + NvU64 physPageSize; + NvU32 i; + + NV_ASSERT_OR_RETURN(pFabricMemDesc != NULL, NV_ERR_INVALID_ARGUMENT); + + NV_CHECK_OK_OR_RETURN(LEVEL_ERROR, + _memoryfabricGetPhysAttrsUsingFabricMemdesc(pGpu, + pFabricVAS, pFabricMemDesc, pParams->offset, + &physPageSize)); + + mappingPageSize = NV_MIN(physPageSize, + memdescGetPageSize(pFabricMemDesc, AT_GPU)); + + NV_CHECK_OR_RETURN(LEVEL_ERROR, + NV_IS_ALIGNED64(pParams->offset, mappingPageSize), + NV_ERR_INVALID_ARGUMENT); + + NV_CHECK_OR_RETURN(LEVEL_ERROR, + pParams->offset < memdescGetSize(pFabricMemDesc), + NV_ERR_INVALID_ARGUMENT); + + memdescGetPhysAddrsForGpu(pFabricMemDesc, pGpu, AT_GPU, pParams->offset, + mappingPageSize, 1, &fabricAddr); + + pageLevelInfoParams.virtAddress = fabricAddr; + pageLevelInfoParams.pageSize = mappingPageSize; + + NV_ASSERT_OK_OR_RETURN(fabricvaspaceGetPageLevelInfo(pFabricVAS, pGpu, + &pageLevelInfoParams)); + + pParams->numLevels = pageLevelInfoParams.numLevels; + for (i = 0; i < pParams->numLevels; i++) + { + portMemCopy(&pParams->levels[i], sizeof(pParams->levels[i]), + &pageLevelInfoParams.levels[i], + sizeof(pageLevelInfoParams.levels[i])); + } + + return NV_OK; } diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/kernel/mem_mgr/mem_list.c nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/kernel/mem_mgr/mem_list.c --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/kernel/mem_mgr/mem_list.c 2023-10-25 20:21:25.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/kernel/mem_mgr/mem_list.c 2024-03-05 22:13:56.000000000 +0000 @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 2019-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2019-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -419,15 +419,23 @@ NvU64 baseOffset = 0; NvU64 trueLength; NvU32 hwResId = 0; - NvU32 pageSize = 0; + NvU64 pageSize = 0; RM_ATTR_PAGE_SIZE pageSizeAttr; FB_ALLOC_INFO *pFbAllocInfo = NULL; FB_ALLOC_PAGE_FORMAT *pFbAllocPageFormat = NULL; HWRESOURCE_INFO *pHwResource = NULL; MemoryManager *pMemoryManager = GPU_GET_MEMORY_MANAGER(pGpu); KernelGmmu *pKernelGmmu = GPU_GET_KERNEL_GMMU(pGpu); - Heap *pHeap = vidmemGetHeap(pGpu, hClient, NV_FALSE); + Heap *pHeap; NvBool bCallingContextPlugin; + RsResourceRef *pDeviceRef; + + NV_ASSERT_OK_OR_RETURN( + refFindAncestorOfType(pResourceRef, classId(Device), &pDeviceRef)); + + pHeap = vidmemGetHeap(pGpu, + dynamicCast(pDeviceRef->pResource, Device), + NV_FALSE); // // When guest RM client doesn't subscribe to MIG partition and requests for vidmem allocation @@ -580,6 +588,12 @@ // only a kernel client can request for a protected allocation if (pFbAllocInfo->pageFormat->flags & NVOS32_ALLOC_FLAGS_ALLOCATE_KERNEL_PRIVILEGED) { + if (privLevel < RS_PRIV_LEVEL_KERNEL) + { + status = NV_ERR_INSUFFICIENT_PERMISSIONS; + NV_PRINTF(LEVEL_ERROR, "only kernel clients may request for a protected allocation\n"); + goto done_fbmem; + } pFbAllocInfo->bIsKernelAlloc = NV_TRUE; } diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/kernel/mem_mgr/mem_multicast_fabric.c nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/kernel/mem_mgr/mem_multicast_fabric.c --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/kernel/mem_mgr/mem_multicast_fabric.c 2023-10-25 20:21:25.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/kernel/mem_mgr/mem_multicast_fabric.c 2024-03-05 22:13:56.000000000 +0000 @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2022-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -110,21 +110,15 @@ portMemSet(pMulticastFabricDesc, 0, sizeof(MEM_MULTICAST_FABRIC_DESCRIPTOR)); - portAtomicExSetU64(&pMulticastFabricDesc->refCount, 1); - listInit(&pMulticastFabricDesc->waitingClientsList, portMemAllocatorGetGlobalNonPaged()); - listInit(&pMulticastFabricDesc->attachMemInfoList, - portMemAllocatorGetGlobalNonPaged()); - - listInit(&pMulticastFabricDesc->gpuOsInfoList, + listInit(&pMulticastFabricDesc->gpuInfoList, portMemAllocatorGetGlobalNonPaged()); - portAtomicSetU32(&pMulticastFabricDesc->mcTeamStatus, NV_ERR_NOT_READY); - - portAtomicSetU32(&pMulticastFabricDesc->attachedGpusMask, 0); - + pMulticastFabricDesc->refCount = 1; + pMulticastFabricDesc->mcTeamStatus = NV_ERR_NOT_READY; + pMulticastFabricDesc->attachedGpusMask = 0; pMulticastFabricDesc->alignment = pAllocParams->alignment; pMulticastFabricDesc->allocSize = pAllocParams->allocSize; pMulticastFabricDesc->pageSize = pAllocParams->pageSize; @@ -224,167 +218,77 @@ } } -NV_STATUS -_memMulticastFabricGpuOsInfoAddUnderLock +static NV_STATUS +_memMulticastFabricGpuInfoAddUnderLock ( MemoryMulticastFabric *pMemoryMulticastFabric, RS_RES_CONTROL_PARAMS_INTERNAL *pParams ) { - NV00FD_CTRL_ATTACH_MEM_PARAMS *pAttachParams = pParams->pParams; + NV00FD_CTRL_ATTACH_GPU_PARAMS *pAttachParams = pParams->pParams; Subdevice *pSubdevice = NULL; - MEM_MULTICAST_FABRIC_GPU_OS_INFO *pNode; + MEM_MULTICAST_FABRIC_GPU_INFO *pNode; MEM_MULTICAST_FABRIC_DESCRIPTOR *pMulticastFabricDesc = \ pMemoryMulticastFabric->pMulticastFabricDesc; + OBJGPU *pGpu; + MEM_MULTICAST_FABRIC_GPU_INFO *pNodeItr; NV_CHECK_OK_OR_RETURN(LEVEL_ERROR, subdeviceGetByHandle(RES_GET_CLIENT(pMemoryMulticastFabric), pAttachParams->hSubdevice, &pSubdevice)); - if(!osMatchGpuOsInfo(GPU_RES_GET_GPU(pSubdevice), - pParams->secInfo.gpuOsInfo)) - { + pGpu = GPU_RES_GET_GPU(pSubdevice); + + if(!osMatchGpuOsInfo(pGpu, pParams->secInfo.gpuOsInfo)) return NV_ERR_INVALID_DEVICE; + + for (pNodeItr = listHead(&pMulticastFabricDesc->gpuInfoList); + pNodeItr != NULL; + pNodeItr = listNext(&pMulticastFabricDesc->gpuInfoList, pNodeItr)) + { + if (pNodeItr->pGpu == pGpu) + { + NV_PRINTF(LEVEL_ERROR, "GPU %x has already attached\n", + pGpu->gpuInstance); + return NV_ERR_IN_USE; + } } - pNode = listAppendNew(&pMulticastFabricDesc->gpuOsInfoList); + pNode = listAppendNew(&pMulticastFabricDesc->gpuInfoList); if (pNode == NULL) - { return NV_ERR_NO_MEMORY; - } - pNode->gpuOsInfo = pParams->secInfo.gpuOsInfo; + pNode->pGpuOsInfo = pParams->secInfo.gpuOsInfo; + pNode->pGpu = GPU_RES_GET_GPU(pSubdevice); + pNode->pAttachMemInfoTree = NULL; + pNode->bMcflaAlloc = NV_FALSE; return NV_OK; } static void -_memMulticastFabricGpuOsInfoRemoveUnderLock +_memMulticastFabricGpuInfoRemoveUnderLock ( MEM_MULTICAST_FABRIC_DESCRIPTOR *pMulticastFabricDesc ) { - MEM_MULTICAST_FABRIC_GPU_OS_INFO *pNode = NULL; + MEM_MULTICAST_FABRIC_GPU_INFO *pNode = NULL; THREAD_STATE_NODE *pThreadNode = NULL; THREAD_STATE_FREE_CALLBACK freeCallback; NV_ASSERT_OK(threadStateGetCurrent(&pThreadNode, NULL)); - while ((pNode = listHead(&pMulticastFabricDesc->gpuOsInfoList)) != NULL) + while ((pNode = listHead(&pMulticastFabricDesc->gpuInfoList)) != NULL) { freeCallback.pCb = osReleaseGpuOsInfo; - freeCallback.pCbData = (void *)pNode->gpuOsInfo; + freeCallback.pCbData = (void *)pNode->pGpuOsInfo; NV_ASSERT_OK(threadStateEnqueueCallbackOnFree(pThreadNode, &freeCallback)); - listRemove(&pMulticastFabricDesc->gpuOsInfoList, pNode); - } -} - -// -// The caller must have acquired the pMulticastFabricOpsMutex lock. -// GPU lock is acquired as needed. -// -static void -_memMulticastFabricRemoveFabricMapping -( - OBJGPU *pGpu, - MEMORY_DESCRIPTOR *pMemDesc -) -{ - FABRIC_VASPACE *pFabricVAS = dynamicCast(pGpu->pFabricVAS, FABRIC_VASPACE); - NvU64 mcAddressBase = pMemDesc->_pteArray[0]; - - NV_ASSERT_OK(rmDeviceGpuLocksAcquire(pGpu, GPUS_LOCK_FLAGS_NONE, - RM_LOCK_MODULES_MEM_FLA)); - - fabricvaspaceBatchFree(pFabricVAS, &mcAddressBase, 1, 1); - - rmDeviceGpuLocksRelease(pGpu, GPUS_LOCK_FLAGS_NONE, NULL); -} - -static void -_memMulticastFabricBatchRemoveFabricMappingUnderLock -( - MEM_MULTICAST_FABRIC_DESCRIPTOR *pMulticastFabricDesc, - MEMORY_DESCRIPTOR *pMemDesc, - MEM_MULTICAST_FABRIC_ATTACH_MEM_INFO *pEndNode -) -{ - MEM_MULTICAST_FABRIC_ATTACH_MEM_INFO *pNode = NULL; - - for (pNode = listHead(&pMulticastFabricDesc->attachMemInfoList); - pNode != NULL; - pNode = listNext(&pMulticastFabricDesc->attachMemInfoList, pNode)) - { - if (pNode == pEndNode) - return; - - _memMulticastFabricRemoveFabricMapping(pNode->pGpu, pMemDesc); + listRemove(&pMulticastFabricDesc->gpuInfoList, pNode); } -} - -static void -_memMulticastFabricAttachMemInfoRemoveUnderLock -( - MEM_MULTICAST_FABRIC_DESCRIPTOR *pMulticastFabricDesc, - MEM_MULTICAST_FABRIC_ATTACH_MEM_INFO *pNode -) -{ - pMulticastFabricDesc->numAttachedGpus--; - - portAtomicAndU32(&pMulticastFabricDesc->attachedGpusMask, - ~(NVBIT32(pNode->pGpu->gpuInstance))); - - listRemove(&pMulticastFabricDesc->attachMemInfoList, pNode); -} - -static void -_memMulticastFabricDetachMemInfoUnderLock -( - MEM_MULTICAST_FABRIC_DESCRIPTOR *pMulticastFabricDesc, - MEM_MULTICAST_FABRIC_ATTACH_MEM_INFO *pNode -) -{ - RM_API *pRmApi; - OBJGPU *pGpu = pNode->pGpu; - FABRIC_VASPACE *pFabricVAS = \ - dynamicCast(pGpu->pFabricVAS, FABRIC_VASPACE); - NvHandle hDupedPhysMem; - - pRmApi = rmapiGetInterface(RMAPI_GPU_LOCK_INTERNAL); - hDupedPhysMem = pNode->hDupedPhysMem; - - _memMulticastFabricAttachMemInfoRemoveUnderLock(pMulticastFabricDesc, pNode); - - NV_ASSERT_OK(pRmApi->Free(pRmApi, pFabricVAS->hClient, hDupedPhysMem)); -} - -// -// The caller must have acquired the pMulticastFabricOpsMutex lock. -// GPU lock is acquired as needed. -// -static void -_memMulticastFabricBatchDetachMemInfo -( - MEM_MULTICAST_FABRIC_DESCRIPTOR *pMulticastFabricDesc -) -{ - MEM_MULTICAST_FABRIC_ATTACH_MEM_INFO *pNode = NULL; - - NV_ASSERT_OK(rmGpuLocksAcquire(GPUS_LOCK_FLAGS_NONE, - RM_LOCK_MODULES_MEM_FLA)); - - // - // _memMulticastFabricDetachMemInfoUnderLock internally trims down the - // attachMemInfoList where pNode is freed up - // - while ((pNode = listHead(&pMulticastFabricDesc->attachMemInfoList)) != NULL) - { - _memMulticastFabricDetachMemInfoUnderLock(pMulticastFabricDesc, pNode); - } - - rmGpuLocksRelease(GPUS_LOCK_FLAGS_NONE, NULL); + pMulticastFabricDesc->attachedGpusMask = 0; + pMulticastFabricDesc->numAttachedGpus = 0; } NV_STATUS @@ -398,7 +302,7 @@ NV2080_CTRL_NVLINK_INBAND_SEND_DATA_PARAMS *sendDataParams; nvlink_inband_mc_team_setup_req_msg_t *pMcTeamSetupReqMsg = NULL; nvlink_inband_mc_team_setup_req_t *pMcTeamSetupReq = NULL; - MEM_MULTICAST_FABRIC_ATTACH_MEM_INFO *pNode; + MEM_MULTICAST_FABRIC_GPU_INFO *pNode; NvU64 requestId; NvU32 idx = 0; NvU32 payloadSize; @@ -406,7 +310,8 @@ NV_STATUS status = NV_OK; sendDataParams = \ - (NV2080_CTRL_NVLINK_INBAND_SEND_DATA_PARAMS *)portMemAllocNonPaged(sizeof(NV2080_CTRL_NVLINK_INBAND_SEND_DATA_PARAMS)); + (NV2080_CTRL_NVLINK_INBAND_SEND_DATA_PARAMS *) + portMemAllocNonPaged(sizeof(NV2080_CTRL_NVLINK_INBAND_SEND_DATA_PARAMS)); if (sendDataParams == NULL) return NV_ERR_NO_MEMORY; @@ -429,9 +334,9 @@ pMcTeamSetupReq->mcAllocSize = pMulticastFabricDesc->allocSize; pMcTeamSetupReq->numGpuHandles = pMulticastFabricDesc->numMaxGpus; - for (pNode = listHead(&pMulticastFabricDesc->attachMemInfoList); + for (pNode = listHead(&pMulticastFabricDesc->gpuInfoList); pNode != NULL; - pNode = listNext(&pMulticastFabricDesc->attachMemInfoList, pNode)) + pNode = listNext(&pMulticastFabricDesc->gpuInfoList, pNode)) pMcTeamSetupReq->gpuHandles[idx++] = pNode->gpuProbeHandle; NV_ASSERT(idx == pMcTeamSetupReq->numGpuHandles); @@ -519,12 +424,8 @@ return status; } -// -// The caller must have acquired the pMulticastFabricOpsMutex lock. -// GPU lock is acquired as needed. -// NV_STATUS -_memMulticastFabricSendInbandTeamSetupRequest +_memMulticastFabricSendInbandTeamSetupRequestUnderlock ( OBJGPU *pGpu, MEM_MULTICAST_FABRIC_DESCRIPTOR *pMulticastFabricDesc @@ -533,31 +434,19 @@ NvU64 fmCaps; NV_STATUS status = NV_OK; - NV_CHECK_OK_OR_RETURN(LEVEL_ERROR, - rmDeviceGpuLocksAcquire(pGpu, GPUS_LOCK_FLAGS_NONE, - RM_LOCK_MODULES_MEM_FLA)); - - status = gpuFabricProbeGetfmCaps(pGpu->pGpuFabricProbeInfo, &fmCaps); + status = gpuFabricProbeGetfmCaps(pGpu->pGpuFabricProbeInfoKernel, &fmCaps); if (status != NV_OK) - goto done; + return status; if (!(fmCaps & NVLINK_INBAND_FM_CAPS_MC_TEAM_SETUP_V1)) - { - status = NV_ERR_NOT_SUPPORTED; - goto done; - } - - status = _memMulticastFabricSendInbandTeamSetupRequestV1UnderLock(pGpu, - pMulticastFabricDesc); - -done: - rmDeviceGpuLocksRelease(pGpu, GPUS_LOCK_FLAGS_NONE, NULL); + return NV_ERR_NOT_SUPPORTED; - return status; + return _memMulticastFabricSendInbandTeamSetupRequestV1UnderLock(pGpu, + pMulticastFabricDesc); } NV_STATUS -_memMulticastFabricSendInbandTeamReleaseRequest +_memMulticastFabricSendInbandTeamReleaseRequestUnderLock ( OBJGPU *pGpu, NvU64 mcTeamHandle @@ -566,56 +455,40 @@ NvU64 fmCaps; NV_STATUS status = NV_OK; - NV_CHECK_OK_OR_RETURN(LEVEL_ERROR, - rmDeviceGpuLocksAcquire(pGpu, GPUS_LOCK_FLAGS_NONE, - RM_LOCK_MODULES_MEM_FLA)); - - status = gpuFabricProbeGetfmCaps(pGpu->pGpuFabricProbeInfo, &fmCaps); + status = gpuFabricProbeGetfmCaps(pGpu->pGpuFabricProbeInfoKernel, &fmCaps); if (status != NV_OK) - goto done; + return status; if (!(fmCaps & NVLINK_INBAND_FM_CAPS_MC_TEAM_RELEASE_V1)) - { - status = NV_ERR_NOT_SUPPORTED; - goto done; - } - - status = _memMulticastFabricSendInbandTeamReleaseRequestV1UnderLock(pGpu, - mcTeamHandle); - -done: - rmDeviceGpuLocksRelease(pGpu, GPUS_LOCK_FLAGS_NONE, NULL); + return NV_ERR_NOT_SUPPORTED; - return status; + return _memMulticastFabricSendInbandTeamReleaseRequestV1UnderLock(pGpu, + mcTeamHandle); } NV_STATUS _memMulticastFabricSendInbandRequestUnderLock ( + OBJGPU *pGpu, MEM_MULTICAST_FABRIC_DESCRIPTOR *pMulticastFabricDesc, MEM_MULTICAST_FABRIC_REQUEST_TYPE requestType ) { NV_STATUS status = NV_OK; - OBJGPU *pGpu; - // - // TODO: Implement the randomization of pGpu to be used for the inband - // communication. Currently we pick the first pGpu in the attachMemInfoList - // to send the inband request. - // - - pGpu = listHead(&pMulticastFabricDesc->attachMemInfoList)->pGpu; + // If pGpu is NULL, pick the first one attached to the object. + if (pGpu == NULL) + pGpu = listHead(&pMulticastFabricDesc->gpuInfoList)->pGpu; switch (requestType) { case MEM_MULTICAST_FABRIC_TEAM_SETUP_REQUEST: - status = _memMulticastFabricSendInbandTeamSetupRequest(pGpu, - pMulticastFabricDesc); + status = _memMulticastFabricSendInbandTeamSetupRequestUnderlock(pGpu, + pMulticastFabricDesc); break; case MEM_MULTICAST_FABRIC_TEAM_RELEASE_REQUEST: - status = _memMulticastFabricSendInbandTeamReleaseRequest(pGpu, - pMulticastFabricDesc->mcTeamHandle); + status = _memMulticastFabricSendInbandTeamReleaseRequestUnderLock(pGpu, + pMulticastFabricDesc->mcTeamHandle); break; default: status = NV_ERR_NOT_SUPPORTED; @@ -626,6 +499,77 @@ } static void +_memorymulticastfabricDetachMem +( + FABRIC_VASPACE *pFabricVAS, + MEMORY_DESCRIPTOR *pFabricMemDesc, + NODE *pMemNode +) +{ + RM_API *pRmApi = rmapiGetInterface(RMAPI_GPU_LOCK_INTERNAL); + MEMORY_DESCRIPTOR *pPhysMemDesc; + MEM_MULTICAST_FABRIC_ATTACH_MEM_INFO_NODE *pAttachMemInfoNode; + + pAttachMemInfoNode = \ + (MEM_MULTICAST_FABRIC_ATTACH_MEM_INFO_NODE *)pMemNode->Data; + pPhysMemDesc = pAttachMemInfoNode->pPhysMemDesc; + + fabricvaspaceUnmapPhysMemdesc(pFabricVAS, pFabricMemDesc, + pMemNode->keyStart, + pPhysMemDesc, + pAttachMemInfoNode->physMapLength); + + NV_ASSERT_OK(pRmApi->Free(pRmApi, pFabricVAS->hClient, + pAttachMemInfoNode->hDupedPhysMem)); +} + +static void +_memorymulticastfabricBatchDetachMem +( + MEM_MULTICAST_FABRIC_DESCRIPTOR *pMulticastFabricDesc +) +{ + MEMORY_DESCRIPTOR *pFabricMemDesc; + MEM_MULTICAST_FABRIC_GPU_INFO *pGpuNode; + NODE *pMemNode; + FABRIC_VASPACE *pFabricVAS; + + pFabricMemDesc = pMulticastFabricDesc->pMemDesc; + NV_ASSERT_OR_RETURN_VOID(pFabricMemDesc != NULL); + + for (pGpuNode = listHead(&pMulticastFabricDesc->gpuInfoList); + pGpuNode != NULL; + pGpuNode = listNext(&pMulticastFabricDesc->gpuInfoList, pGpuNode)) + { + pFabricVAS = dynamicCast(pGpuNode->pGpu->pFabricVAS, FABRIC_VASPACE); + if (pFabricVAS == NULL) + { + NV_ASSERT(0); + continue; + } + + btreeEnumStart(0, &pMemNode, pGpuNode->pAttachMemInfoTree); + while (pMemNode != NULL) + { + _memorymulticastfabricDetachMem(pFabricVAS, pFabricMemDesc, pMemNode); + + btreeUnlink(pMemNode, &pGpuNode->pAttachMemInfoTree); + portMemFree(pMemNode->Data); + + btreeEnumStart(0, &pMemNode, pGpuNode->pAttachMemInfoTree); + } + + // Everything is detached during object cleanup, free MCFLA now. + if (pGpuNode->bMcflaAlloc) + { + fabricvaspaceBatchFree(pFabricVAS, &pFabricMemDesc->_pteArray[0], + 1, 1); + pGpuNode->bMcflaAlloc = NV_FALSE; + } + } +} + +static void _memMulticastFabricDescriptorFreeUnderLock ( MEM_MULTICAST_FABRIC_DESCRIPTOR *pMulticastFabricDesc @@ -634,16 +578,17 @@ if (pMulticastFabricDesc == NULL) return; - if (portAtomicExDecrementU64(&pMulticastFabricDesc->refCount) == 0) + pMulticastFabricDesc->refCount--; + + if (pMulticastFabricDesc->refCount == 0) { if (pMulticastFabricDesc->pMemDesc != NULL) { NV_ASSERT(pMulticastFabricDesc->bMemdescInstalled); - _memMulticastFabricBatchRemoveFabricMappingUnderLock(pMulticastFabricDesc, - pMulticastFabricDesc->pMemDesc, - NULL); - _memMulticastFabricSendInbandRequestUnderLock(pMulticastFabricDesc, + _memorymulticastfabricBatchDetachMem(pMulticastFabricDesc); + + _memMulticastFabricSendInbandRequestUnderLock(NULL, pMulticastFabricDesc, MEM_MULTICAST_FABRIC_TEAM_RELEASE_REQUEST); } @@ -674,17 +619,13 @@ } } - _memMulticastFabricGpuOsInfoRemoveUnderLock(pMulticastFabricDesc); - - NV_ASSERT(listCount(&pMulticastFabricDesc->gpuOsInfoList) == 0); - listDestroy(&pMulticastFabricDesc->gpuOsInfoList); + _memMulticastFabricGpuInfoRemoveUnderLock(pMulticastFabricDesc); - _memMulticastFabricBatchDetachMemInfo(pMulticastFabricDesc); + NV_ASSERT(listCount(&pMulticastFabricDesc->gpuInfoList) == 0); + listDestroy(&pMulticastFabricDesc->gpuInfoList); NV_ASSERT(pMulticastFabricDesc->numAttachedGpus == 0); - NV_ASSERT(portAtomicOrU32(&pMulticastFabricDesc->attachedGpusMask, 0) == 0); - NV_ASSERT(listCount(&pMulticastFabricDesc->attachMemInfoList) == 0); - listDestroy(&pMulticastFabricDesc->attachMemInfoList); + NV_ASSERT(pMulticastFabricDesc->attachedGpusMask == 0); NV_ASSERT(listCount(&pMulticastFabricDesc->waitingClientsList) == 0); listDestroy(&pMulticastFabricDesc->waitingClientsList); @@ -732,162 +673,6 @@ } NV_STATUS -_memMulticastFabricAttachMemInfoAddUnderLock -( - MEM_MULTICAST_FABRIC_DESCRIPTOR *pMulticastFabricDesc, - OBJGPU *pGpu, - NV00FD_CTRL_ATTACH_MEM_PARAMS *pParams, - MEMORY_DESCRIPTOR *pPhysMemDesc, - NvHandle hDupedPhysMem, - NvU64 gpuProbeHandle, - MEM_MULTICAST_FABRIC_ATTACH_MEM_INFO **pAttachMemNode -) -{ - MEM_MULTICAST_FABRIC_ATTACH_MEM_INFO *pNode; - MEM_MULTICAST_FABRIC_ATTACH_MEM_INFO *pNodeItr; - - for (pNodeItr = listHead(&pMulticastFabricDesc->attachMemInfoList); - pNodeItr != NULL; - pNodeItr = listNext(&pMulticastFabricDesc->attachMemInfoList, pNodeItr)) - { - if (pNodeItr->pGpu == pGpu) - { - NV_PRINTF(LEVEL_ERROR, "GPU %x has already attached to this multicast object\n", - pGpu->gpuInstance); - return NV_ERR_IN_USE; - } - } - - pNode = listAppendNew(&pMulticastFabricDesc->attachMemInfoList); - if (pNode == NULL) - return NV_ERR_NO_MEMORY; - - pNode->offset = pParams->offset; - pNode->mapOffset = pParams->mapOffset; - pNode->mapLength = pParams->mapLength; - pNode->flags = pParams->flags; - pNode->pGpu = pGpu; - pNode->pPhysMemDesc = pPhysMemDesc; - pNode->hDupedPhysMem = hDupedPhysMem; - pNode->gpuProbeHandle = gpuProbeHandle; - - portAtomicOrU32(&pMulticastFabricDesc->attachedGpusMask, - NVBIT32(pGpu->gpuInstance)); - - pMulticastFabricDesc->numAttachedGpus++; - - *pAttachMemNode = pNode; - - return NV_OK; -} - -// -// The caller must have acquired the pMulticastFabricOpsMutex lock. -// GPU lock is acquired as needed. -// -NV_STATUS -_memMulticastFabricSetupFabricMapping -( - OBJGPU *pGpu, - MEM_MULTICAST_FABRIC_DESCRIPTOR *pMulticastFabricDesc, - MEM_MULTICAST_FABRIC_ATTACH_MEM_INFO *pAttachMemInfo, - MEMORY_DESCRIPTOR *pMemDesc -) -{ - FABRIC_VASPACE *pFabricVAS = NULL; - VAS_ALLOC_FLAGS flags = {0}; - NV_STATUS status = NV_OK; - NvU64 physMemPageSize; - NvU64 mcAddressBase = pMemDesc->_pteArray[0]; - - NV_CHECK_OK_OR_RETURN(LEVEL_ERROR, - rmDeviceGpuLocksAcquire(pGpu, GPUS_LOCK_FLAGS_NONE, - RM_LOCK_MODULES_MEM_FLA)); - - pFabricVAS = dynamicCast(pGpu->pFabricVAS, FABRIC_VASPACE); - - physMemPageSize = memdescGetPageSize(pAttachMemInfo->pPhysMemDesc, AT_GPU); - - status = fabricvaspaceAllocMulticast(pFabricVAS, physMemPageSize, - pMulticastFabricDesc->alignment, - flags, - mcAddressBase, - pMulticastFabricDesc->allocSize); - if (status != NV_OK) - { - NV_PRINTF(LEVEL_ERROR, - "Fabric VA space alloc failed! for GPU %x\n", - pGpu->gpuInstance); - goto releaseGpuLock; - } - - // - // For now MCFLA code assumes zero fabric offset. When a non-zero fabric - // offset supported, revisit map/unmap paths. - // - status = fabricvaspaceMapPhysMemdesc(pFabricVAS, - pMemDesc, - 0, - pAttachMemInfo->pPhysMemDesc, - pAttachMemInfo->mapOffset, - pAttachMemInfo->mapLength, - 0); - if (status != NV_OK) - { - NV_PRINTF(LEVEL_ERROR, - "Failed to map MC FLA at the given physical offset for GPU %x\n", - pGpu->gpuInstance); - goto freeFabricVa; - } - - // - // TODO: Handle the case to map remaining MC FLA range - // to dummy pages when physMemSize < mcAllocSize - // - - rmDeviceGpuLocksRelease(pGpu, GPUS_LOCK_FLAGS_NONE, NULL); - - return NV_OK; - -freeFabricVa: - fabricvaspaceBatchFree(pFabricVAS, &mcAddressBase, 1, 1); - -releaseGpuLock: - rmDeviceGpuLocksRelease(pGpu, GPUS_LOCK_FLAGS_NONE, NULL); - - return status; -} - -NV_STATUS -_memMulticastFabricBatchSetupFabricMappingUnderLock -( - MEM_MULTICAST_FABRIC_DESCRIPTOR *pMulticastFabricDesc, - MEMORY_DESCRIPTOR *pMemDesc -) -{ - MEM_MULTICAST_FABRIC_ATTACH_MEM_INFO *pNode = NULL; - NV_STATUS status = NV_OK; - - for (pNode = listHead(&pMulticastFabricDesc->attachMemInfoList); - pNode != NULL; - pNode = listNext(&pMulticastFabricDesc->attachMemInfoList, pNode)) - { - status = _memMulticastFabricSetupFabricMapping(pNode->pGpu, pMulticastFabricDesc, - pNode, pMemDesc); - if (status != NV_OK) - goto batchRemoveMapping; - } - - return NV_OK; - -batchRemoveMapping: - _memMulticastFabricBatchRemoveFabricMappingUnderLock(pMulticastFabricDesc, - pMemDesc, pNode); - - return status; -} - -NV_STATUS _memMulticastFabricCreateMemDescUnderLock ( MEM_MULTICAST_FABRIC_DESCRIPTOR *pMulticastFabricDesc, @@ -937,23 +722,91 @@ pMulticastFabricDesc->pMemDesc = pMemDesc; pMulticastFabricDesc->bMemdescInstalled = NV_TRUE; pMulticastFabricDesc->mcTeamHandle = mcTeamHandle; + pMulticastFabricDesc->mcTeamStatus = status; + + _memMulticastFabricDescriptorFlushClientsUnderLock(pMulticastFabricDesc); +} - portAtomicMemoryFenceStore(); +static NV_STATUS +_memorymulticastFabricAllocVasUnderLock +( + MEM_MULTICAST_FABRIC_DESCRIPTOR *pMulticastFabricDesc, + MEMORY_DESCRIPTOR *pFabricMemDesc +) +{ + NV_STATUS status = NV_OK; + FABRIC_VASPACE *pFabricVAS; + MEM_MULTICAST_FABRIC_GPU_INFO *pGpuInfo; + VAS_ALLOC_FLAGS flags = { 0 }; + NvU64 gpuProbeHandle; + + for (pGpuInfo = listHead(&pMulticastFabricDesc->gpuInfoList); + pGpuInfo != NULL; + pGpuInfo = listNext(&pMulticastFabricDesc->gpuInfoList, pGpuInfo)) + { + OBJGPU *pGpu = pGpuInfo->pGpu; - portAtomicSetU32(&pMulticastFabricDesc->mcTeamStatus, status); + pFabricVAS = dynamicCast(pGpu->pFabricVAS, FABRIC_VASPACE); + if (pFabricVAS == NULL) + { + status = NV_ERR_INVALID_STATE; + goto cleanup; + } - portAtomicMemoryFenceStore(); + // + // The fabric handle might not be available or have changed, if fabric + // state was ever invalidated while MCFLA allocation was in progress. + // + status = gpuFabricProbeGetGpuFabricHandle(pGpu->pGpuFabricProbeInfoKernel, + &gpuProbeHandle); + if ((status != NV_OK) || (pGpuInfo->gpuProbeHandle != gpuProbeHandle)) + { + NV_PRINTF(LEVEL_ERROR, "Attached GPU's probe handle is stale\n"); + status = NV_ERR_INVALID_DEVICE; + goto cleanup; + } - _memMulticastFabricDescriptorFlushClientsUnderLock(pMulticastFabricDesc); + status = fabricvaspaceAllocMulticast(pFabricVAS, + memdescGetPageSize(pFabricMemDesc, AT_GPU), + pMulticastFabricDesc->alignment, + flags, pFabricMemDesc->_pteArray[0], + pMulticastFabricDesc->allocSize); + if (status != NV_OK) + { + NV_PRINTF(LEVEL_ERROR, + "Fabric VA space alloc failed for GPU %d\n", + pGpuInfo->pGpu->gpuInstance); + goto cleanup; + } + + pGpuInfo->bMcflaAlloc = NV_TRUE; + } + + return NV_OK; + +cleanup: + for (pGpuInfo = listHead(&pMulticastFabricDesc->gpuInfoList); + pGpuInfo != NULL; + pGpuInfo = listNext(&pMulticastFabricDesc->gpuInfoList, pGpuInfo)) + { + if (pGpuInfo->bMcflaAlloc) + { + pFabricVAS = dynamicCast(pGpuInfo->pGpu->pFabricVAS, FABRIC_VASPACE); + + fabricvaspaceBatchFree(pFabricVAS, &pFabricMemDesc->_pteArray[0], + 1, 1); + + pGpuInfo->bMcflaAlloc = NV_FALSE; + } + } + + return status; } -// -// TODO: This function will be invoked as part of the FM inband -// response handling once inband integration is complete. -// NV_STATUS -_memMulticastFabricAttachMemPostProcessorUnderLock +_memMulticastFabricAttachGpuPostProcessorUnderLock ( + OBJGPU *pGpu, MEM_MULTICAST_FABRIC_DESCRIPTOR *pMulticastFabricDesc, NV_STATUS mcTeamStatus, NvU64 mcTeamHandle, @@ -992,27 +845,30 @@ status = _memMulticastFabricCreateMemDescUnderLock(pMulticastFabricDesc, mcAddressBase, &pMemDesc); if (status != NV_OK) + { + NV_PRINTF(LEVEL_ERROR, "Failed to allocate fabric memdesc\n"); goto installMemDesc; + } - status = _memMulticastFabricBatchSetupFabricMappingUnderLock(pMulticastFabricDesc, - pMemDesc); + status = _memorymulticastFabricAllocVasUnderLock(pMulticastFabricDesc, + pMemDesc); if (status != NV_OK) - goto cleanupMemdesc; - - goto installMemDesc; - -cleanupMemdesc: - memdescDestroy(pMemDesc); - pMemDesc = NULL; + { + NV_PRINTF(LEVEL_ERROR, "Failed to allocate fabric VAS\n"); + memdescDestroy(pMemDesc); + pMemDesc = NULL; + goto installMemDesc; + } installMemDesc: _memMulticastFabricInstallMemDescUnderLock(pMulticastFabricDesc, pMemDesc, mcTeamHandle, status); + if ((status != NV_OK) && (mcTeamStatus == NV_OK)) - _memMulticastFabricSendInbandRequestUnderLock(pMulticastFabricDesc, - MEM_MULTICAST_FABRIC_TEAM_RELEASE_REQUEST); + _memMulticastFabricSendInbandRequestUnderLock(pGpu, pMulticastFabricDesc, + MEM_MULTICAST_FABRIC_TEAM_RELEASE_REQUEST); return status; } @@ -1035,9 +891,10 @@ _memMulticastFabricDescriptorFreeUnderLock(pMulticastFabricDesc); } -void memorymulticastfabricTeamSetupResponseCallback +NV_STATUS +memorymulticastfabricTeamSetupResponseCallback ( - OBJGPU *pGpu, + NvU32 gpuInstance, NV2080_CTRL_NVLINK_INBAND_RECEIVED_DATA_PARAMS *pInbandRcvParams ) { @@ -1051,8 +908,16 @@ NvU64 mcAddressBase = 0; NvU64 mcAddressSize = 0; NvU8 *pRsvd = NULL; + OBJGPU *pGpu; NV_ASSERT(pInbandRcvParams != NULL); + NV_ASSERT(rmGpuLockIsOwner()); + + if ((pGpu = gpumgrGetGpu(gpuInstance)) == NULL) + { + NV_ASSERT_FAILED("Invalid GPU instance"); + return NV_ERR_INVALID_ARGUMENT; + } pMcTeamSetupRspMsg = \ (nvlink_inband_mc_team_setup_rsp_msg_t *)&pInbandRcvParams->data[0]; @@ -1090,7 +955,8 @@ fabricMulticastSetupCacheDeleteUnderLock_IMPL(pFabric, requestId); - (void)_memMulticastFabricAttachMemPostProcessorUnderLock(pMulticastFabricDesc, + (void)_memMulticastFabricAttachGpuPostProcessorUnderLock(pGpu, + pMulticastFabricDesc, mcTeamStatus, mcTeamHandle, mcAddressBase, @@ -1101,8 +967,8 @@ OS_WAIT_QUEUE *pWq; if (mcTeamStatus == NV_OK) - (void)_memMulticastFabricSendInbandTeamReleaseRequest(pGpu, - mcTeamHandle); + (void)_memMulticastFabricSendInbandTeamReleaseRequestUnderLock(pGpu, + mcTeamHandle); // // Check if there is any thread waiting for team release and @@ -1125,6 +991,8 @@ } fabricMulticastFabricOpsMutexRelease(pFabric); + + return NV_OK; } NV_STATUS @@ -1138,10 +1006,6 @@ Fabric *pFabric = SYS_GET_FABRIC(SYS_GET_INSTANCE()); NV00FD_ALLOCATION_PARAMETERS *pAllocParams = pParams->pAllocParams; NV_STATUS status = NV_OK; - OBJSYS *pSys = SYS_GET_INSTANCE(); - - if (!pSys->bMulticastFlaEnabled) - return NV_ERR_NOT_SUPPORTED; if (RS_IS_COPY_CTOR(pParams)) { @@ -1163,34 +1027,33 @@ return status; } -NV_STATUS -memorymulticastfabricCtrlAttachMem_IMPL +static NV_STATUS +_memorymulticastfabricCtrlAttachGpu ( MemoryMulticastFabric *pMemoryMulticastFabric, - NV00FD_CTRL_ATTACH_MEM_PARAMS *pParams + NV00FD_CTRL_ATTACH_GPU_PARAMS *pParams ) { MEM_MULTICAST_FABRIC_DESCRIPTOR *pMulticastFabricDesc = \ - pMemoryMulticastFabric->pMulticastFabricDesc; + pMemoryMulticastFabric->pMulticastFabricDesc; NV_STATUS status = NV_OK; - NvHandle hClient = RES_GET_CLIENT_HANDLE(pMemoryMulticastFabric); - RsResourceRef *pPhysMemRef = NULL; - MEMORY_DESCRIPTOR *pPhysMemDesc = NULL; - Subdevice *pSubdevice = NULL; - OBJGPU *pGpu = NULL; - FABRIC_VASPACE *pFabricVAS = NULL; - RM_API *pRmApi; - NvHandle hDupedPhysMem = 0; - NvU64 physMemPageSize; - NvU64 physMemSize; - MEM_MULTICAST_FABRIC_ATTACH_MEM_INFO *pAttachMemNode = NULL; - NvU64 gpuProbeHandle = 0; + Subdevice *pSubdevice; + OBJGPU *pGpu; + FABRIC_VASPACE *pFabricVAS; + NvU64 gpuProbeHandle; + MEM_MULTICAST_FABRIC_GPU_INFO *pNode = NULL; + CALL_CONTEXT *pCallContext = resservGetTlsCallContext(); + + if (pParams->flags != 0) + { + NV_PRINTF(LEVEL_ERROR, "flags passed for attach mem must be zero\n"); + return NV_ERR_INVALID_ARGUMENT; + } // Check if the Multicast FLA object has any additional slots for GPUs if (pMulticastFabricDesc->numAttachedGpus == pMulticastFabricDesc->numMaxGpus) { - NV_PRINTF(LEVEL_ERROR, - "Max no. of GPUs for this multicast object have already attached!\n"); + NV_PRINTF(LEVEL_ERROR, "Max no. of GPUs have already attached!\n"); return NV_ERR_INVALID_OPERATION; } @@ -1200,34 +1063,31 @@ pGpu = GPU_RES_GET_GPU(pSubdevice); - NV_CHECK_OK_OR_RETURN(LEVEL_ERROR, - rmDeviceGpuLocksAcquire(pGpu, GPUS_LOCK_FLAGS_NONE, - RM_LOCK_MODULES_MEM_FLA)); - - pRmApi = rmapiGetInterface(RMAPI_GPU_LOCK_INTERNAL); - if (RMCFG_FEATURE_PLATFORM_WINDOWS || + gpuIsCCFeatureEnabled(pGpu) || IS_VIRTUAL(pGpu)) { NV_PRINTF(LEVEL_ERROR, "Multicast attach not supported on Windows/CC/vGPU modes\n"); - status = NV_ERR_NOT_SUPPORTED; - goto fail; + return NV_ERR_NOT_SUPPORTED; } - status = gpuFabricProbeGetGpuFabricHandle(pGpu->pGpuFabricProbeInfo, &gpuProbeHandle); + status = _memMulticastFabricGpuInfoAddUnderLock(pMemoryMulticastFabric, + pCallContext->pControlParams); if (status != NV_OK) { - NV_PRINTF(LEVEL_ERROR, - "Attaching GPU does not have a valid probe handle\n"); - goto fail; + NV_PRINTF(LEVEL_ERROR, "Failed to populate GPU info\n"); + return status; } - status = serverutilGetResourceRef(hClient, pParams->hMemory, &pPhysMemRef); + pNode = listTail(&pMulticastFabricDesc->gpuInfoList); + + status = gpuFabricProbeGetGpuFabricHandle(pGpu->pGpuFabricProbeInfoKernel, + &gpuProbeHandle); if (status != NV_OK) { NV_PRINTF(LEVEL_ERROR, - "Failed to get resource in resserv for physmem handle\n"); + "Attaching GPU does not have a valid probe handle\n"); goto fail; } @@ -1241,112 +1101,324 @@ goto fail; } - pPhysMemDesc = (dynamicCast(pPhysMemRef->pResource, Memory))->pMemDesc; + pNode->gpuProbeHandle = gpuProbeHandle; - if ((memdescGetAddressSpace(pPhysMemDesc) != ADDR_FBMEM) || - (pGpu != pPhysMemDesc->pGpu)) + if ((pMulticastFabricDesc->numAttachedGpus + 1) == pMulticastFabricDesc->numMaxGpus) { - NV_PRINTF(LEVEL_ERROR, "Invalid physical physmem handle passed\n"); - status = NV_ERR_INVALID_ARGUMENT; - goto fail; + status = _memMulticastFabricSendInbandRequestUnderLock(NULL, pMulticastFabricDesc, + MEM_MULTICAST_FABRIC_TEAM_SETUP_REQUEST); + if (status != NV_OK) + { + NV_PRINTF(LEVEL_ERROR, + "Inband request submission to FM for Multicast Team Setup failed!\n"); + goto fail; + } } - physMemPageSize = memdescGetPageSize(pPhysMemDesc, AT_GPU); + pMulticastFabricDesc->numAttachedGpus++; + pMulticastFabricDesc->attachedGpusMask |= NVBIT32(pGpu->gpuInstance); + + return NV_OK; + +fail: + // Remove GPU OS info added in the prologue. + listRemove(&pMulticastFabricDesc->gpuInfoList, pNode); + + return status; +} + +NV_STATUS +memorymulticastfabricCtrlAttachGpu_IMPL +( + MemoryMulticastFabric *pMemoryMulticastFabric, + NV00FD_CTRL_ATTACH_GPU_PARAMS *pParams +) +{ + Fabric *pFabric = SYS_GET_FABRIC(SYS_GET_INSTANCE()); + NV_STATUS status = NV_OK; + + fabricMulticastFabricOpsMutexAcquire(pFabric); + + status = _memorymulticastfabricCtrlAttachGpu(pMemoryMulticastFabric, + pParams); - physMemSize = memdescGetSize(pPhysMemDesc); + fabricMulticastFabricOpsMutexRelease(pFabric); + + return status; +} - if (physMemPageSize != RM_PAGE_SIZE_HUGE) +static MEM_MULTICAST_FABRIC_GPU_INFO* +_memorymulticastfabricGetAttchedGpuInfo +( + MemoryMulticastFabric *pMemoryMulticastFabric, + NvHandle hSubdevice +) +{ + MEM_MULTICAST_FABRIC_DESCRIPTOR *pMulticastFabricDesc = \ + pMemoryMulticastFabric->pMulticastFabricDesc; + MEM_MULTICAST_FABRIC_GPU_INFO *pNodeItr; + Subdevice *pSubdevice = NULL; + NV_STATUS status; + + status = subdeviceGetByHandle(RES_GET_CLIENT(pMemoryMulticastFabric), + hSubdevice, &pSubdevice); + if (status != NV_OK) + return NULL; + + for (pNodeItr = listHead(&pMulticastFabricDesc->gpuInfoList); + pNodeItr != NULL; + pNodeItr = listNext(&pMulticastFabricDesc->gpuInfoList, pNodeItr)) { - NV_PRINTF(LEVEL_ERROR, "Physical physmem page size should be 2MB\n"); - status = NV_ERR_INVALID_ARGUMENT; - goto fail; + if (pNodeItr->pGpu == GPU_RES_GET_GPU(pSubdevice)) + return pNodeItr; } - if ((!NV_IS_ALIGNED64(pParams->mapOffset, physMemPageSize)) || - (!NV_IS_ALIGNED64(pParams->mapLength, physMemPageSize)) || - (pParams->mapOffset >= physMemSize) || - (pParams->mapLength > (physMemSize - pParams->mapOffset))) + return NULL; +} + +static NV_STATUS +_memorymulticastfabricCtrlDetachMem +( + MemoryMulticastFabric *pMemoryMulticastFabric, + NV00FD_CTRL_DETACH_MEM_PARAMS *pParams +) +{ + MEM_MULTICAST_FABRIC_DESCRIPTOR *pMulticastFabricDesc = \ + pMemoryMulticastFabric->pMulticastFabricDesc; + MEM_MULTICAST_FABRIC_GPU_INFO *pGpuInfo; + NODE *pNode; + MEMORY_DESCRIPTOR *pFabricMemDesc; + FABRIC_VASPACE *pFabricVAS; + NV_STATUS status; + + if (pParams->flags != 0) + return NV_ERR_INVALID_ARGUMENT; + + pGpuInfo = _memorymulticastfabricGetAttchedGpuInfo(pMemoryMulticastFabric, + pParams->hSubdevice); + if (pGpuInfo == NULL) + return NV_ERR_INVALID_DEVICE; + + status = btreeSearch(pParams->offset, &pNode, pGpuInfo->pAttachMemInfoTree); + if (status != NV_OK) + return status; + + pFabricMemDesc = pMulticastFabricDesc->pMemDesc; + NV_ASSERT_OR_RETURN(pFabricMemDesc != NULL, NV_ERR_INVALID_STATE); + + pFabricVAS = dynamicCast(pGpuInfo->pGpu->pFabricVAS, FABRIC_VASPACE); + NV_ASSERT_OR_RETURN(pFabricVAS != NULL, NV_ERR_INVALID_STATE); + + _memorymulticastfabricDetachMem(pFabricVAS, pFabricMemDesc, pNode); + + btreeUnlink(pNode, &pGpuInfo->pAttachMemInfoTree); + portMemFree(pNode->Data); + + return NV_OK; +} + +NV_STATUS +memorymulticastfabricCtrlDetachMem_IMPL +( + MemoryMulticastFabric *pMemoryMulticastFabric, + NV00FD_CTRL_DETACH_MEM_PARAMS *pParams +) +{ + Fabric *pFabric = SYS_GET_FABRIC(SYS_GET_INSTANCE()); + NV_STATUS status = NV_OK; + + fabricMulticastFabricOpsMutexAcquire(pFabric); + + status = _memorymulticastfabricCtrlDetachMem(pMemoryMulticastFabric, + pParams); + + fabricMulticastFabricOpsMutexRelease(pFabric); + + return status; +} + +static NV_STATUS +_memorymulticastfabricValidatePhysMem +( + MemoryMulticastFabric *pMemoryMulticastFabric, + NvHandle hPhysMem, + OBJGPU *pAttachedGpu, + MEMORY_DESCRIPTOR **ppPhysMemDesc +) +{ + RsResourceRef *pPhysmemRef; + MEMORY_DESCRIPTOR *pPhysMemDesc; + NvU64 physPageSize; + NV_STATUS status; + Memory *pMemory; + + status = serverutilGetResourceRef(RES_GET_CLIENT_HANDLE(pMemoryMulticastFabric), + hPhysMem, &pPhysmemRef); + if (status != NV_OK) { NV_PRINTF(LEVEL_ERROR, - "Invalid mapOffset passed for the physical physmem handle\n"); - status = NV_ERR_INVALID_OFFSET; - goto fail; + "Failed to get resource in resserv for physmem handle\n"); + + return status; } - if (pParams->offset != 0) + pMemory = dynamicCast(pPhysmemRef->pResource, Memory); + if (pMemory == NULL) { - NV_PRINTF(LEVEL_ERROR, "offset passed for attach mem must be zero\n"); - status = NV_ERR_INVALID_OFFSET; - goto fail; + NV_PRINTF(LEVEL_ERROR, "Invalid memory handle\n"); + return NV_ERR_INVALID_OBJECT_HANDLE; } - if (pParams->mapLength == 0) + pPhysMemDesc = pMemory->pMemDesc; + if (pPhysMemDesc == NULL) { - NV_PRINTF(LEVEL_ERROR, "Invalid mapLength passed\n"); - status = NV_ERR_INVALID_ARGUMENT; - goto fail; + NV_PRINTF(LEVEL_ERROR, "Invalid memory handle\n"); + return NV_ERR_INVALID_OBJECT_HANDLE; } - if ((pParams->offset >= pMulticastFabricDesc->allocSize) || - (pParams->mapLength > (pMulticastFabricDesc->allocSize - pParams->offset))) + if (memdescGetAddressSpace(pPhysMemDesc) != ADDR_FBMEM || + (pAttachedGpu != pPhysMemDesc->pGpu)) { - NV_PRINTF(LEVEL_ERROR, "Invalid multicast offset passed\n"); - status = NV_ERR_INVALID_OFFSET; - goto fail; + NV_PRINTF(LEVEL_ERROR, "Invalid physmem handle passed\n"); + + return NV_ERR_INVALID_ARGUMENT; } - if (pParams->flags != 0) + physPageSize = memdescGetPageSize(pPhysMemDesc, AT_GPU); + if ((physPageSize != RM_PAGE_SIZE_HUGE) && + (physPageSize != RM_PAGE_SIZE_512M)) { - NV_PRINTF(LEVEL_ERROR, "flags passed for attach mem must be zero\n"); - status = NV_ERR_INVALID_ARGUMENT; - goto fail; + NV_PRINTF(LEVEL_ERROR, "Physmem page size should be 2MB\n"); + + return NV_ERR_INVALID_ARGUMENT; } - status = pRmApi->DupObject(pRmApi, pFabricVAS->hClient, pFabricVAS->hDevice, - &hDupedPhysMem, hClient, pParams->hMemory, 0); + *ppPhysMemDesc = pPhysMemDesc; + return NV_OK; +} + +static NV_STATUS +_memorymulticastfabricCtrlAttachMem +( + MemoryMulticastFabric *pMemoryMulticastFabric, + NV00FD_CTRL_ATTACH_MEM_PARAMS *pParams +) +{ + MEM_MULTICAST_FABRIC_DESCRIPTOR *pMulticastFabricDesc = \ + pMemoryMulticastFabric->pMulticastFabricDesc; + MEM_MULTICAST_FABRIC_GPU_INFO *pGpuInfo; + NV_STATUS status; + MEMORY_DESCRIPTOR *pPhysMemDesc; + MEMORY_DESCRIPTOR *pFabricMemDesc; + NvHandle hDupedPhysMem = 0; + RM_API *pRmApi = rmapiGetInterface(RMAPI_GPU_LOCK_INTERNAL); + FABRIC_VASPACE *pFabricVAS; + MEM_MULTICAST_FABRIC_ATTACH_MEM_INFO_NODE *pNode; + + if (pParams->flags != 0) + return NV_ERR_INVALID_ARGUMENT; + + pGpuInfo = _memorymulticastfabricGetAttchedGpuInfo(pMemoryMulticastFabric, + pParams->hSubdevice); + if (pGpuInfo == NULL) + return NV_ERR_INVALID_DEVICE; + + status = _memorymulticastfabricValidatePhysMem(pMemoryMulticastFabric, + pParams->hMemory, + pGpuInfo->pGpu, + &pPhysMemDesc); if (status != NV_OK) { - NV_PRINTF(LEVEL_ERROR, "Failed to dup physical physical memory handle\n"); - goto fail; + NV_PRINTF(LEVEL_ERROR, "Failed to validate physmem handle\n"); + return status; } - status = _memMulticastFabricAttachMemInfoAddUnderLock(pMulticastFabricDesc, - pGpu, pParams, pPhysMemDesc, hDupedPhysMem, gpuProbeHandle, - &pAttachMemNode); + pFabricVAS = dynamicCast(pGpuInfo->pGpu->pFabricVAS, FABRIC_VASPACE); + NV_ASSERT_OR_RETURN(pFabricVAS != NULL, NV_ERR_INVALID_STATE); - rmDeviceGpuLocksRelease(pGpu, GPUS_LOCK_FLAGS_NONE, NULL); + pFabricMemDesc = pMulticastFabricDesc->pMemDesc; + NV_ASSERT_OR_RETURN(pFabricMemDesc != NULL, NV_ERR_INVALID_STATE); + NV_ASSERT_OR_RETURN(pGpuInfo->bMcflaAlloc, NV_ERR_INVALID_STATE); + + status = pRmApi->DupObject(pRmApi, pFabricVAS->hClient, + pFabricVAS->hDevice, &hDupedPhysMem, + RES_GET_CLIENT_HANDLE(pMemoryMulticastFabric), + pParams->hMemory, 0); if (status != NV_OK) - goto addInfoFail; + { + NV_PRINTF(LEVEL_ERROR, "Failed to dup physmem handle\n"); + return status; + } - if (pMulticastFabricDesc->numAttachedGpus == pMulticastFabricDesc->numMaxGpus) + status = fabricvaspaceMapPhysMemdesc(pFabricVAS, + pFabricMemDesc, + pParams->offset, + pPhysMemDesc, + pParams->mapOffset, + pParams->mapLength, + 0); + if (status != NV_OK) { - status = _memMulticastFabricSendInbandRequestUnderLock(pMulticastFabricDesc, - MEM_MULTICAST_FABRIC_TEAM_SETUP_REQUEST); - if (status != NV_OK) - { - NV_PRINTF(LEVEL_ERROR, - "Inband request submission to FM for Multicast Team Setup failed!\n"); - goto inbandFail; - } + NV_PRINTF(LEVEL_ERROR, "Failed to map FLA\n"); + goto freeDupedMem; + } + + pNode = portMemAllocNonPaged(sizeof(*pNode)); + if (pNode == NULL) + { + status = NV_ERR_NO_MEMORY; + goto unmapVas; + } + + portMemSet(pNode, 0, sizeof(*pNode)); + + pNode->node.keyStart = pParams->offset; + pNode->node.keyEnd = pParams->offset; + pNode->physMapLength = pParams->mapLength; + pNode->pPhysMemDesc = pPhysMemDesc; + pNode->hDupedPhysMem = hDupedPhysMem; + pNode->node.Data = pNode; + + status = btreeInsert(&pNode->node, &pGpuInfo->pAttachMemInfoTree); + if (status != NV_OK) + { + NV_PRINTF(LEVEL_ERROR, "Failed to track attach mem info\n"); + goto freeNode; } return NV_OK; -goto inbandFail; -inbandFail: - _memMulticastFabricAttachMemInfoRemoveUnderLock(pMulticastFabricDesc, pAttachMemNode); - -addInfoFail: - // Take all GPU lock. This is enforced by the vidmem class - NV_ASSERT_OK(rmGpuLocksAcquire(GPUS_LOCK_FLAGS_NONE, RM_LOCK_MODULES_MEM_FLA)); - NV_ASSERT(pRmApi->Free(pRmApi, pFabricVAS->hClient, hDupedPhysMem) == NV_OK); - rmGpuLocksRelease(GPUS_LOCK_FLAGS_NONE, NULL); +freeNode: + portMemFree(pNode); -fail: - if (rmDeviceGpuLockIsOwner(pGpu->gpuInstance)) - rmDeviceGpuLocksRelease(pGpu, GPUS_LOCK_FLAGS_NONE, NULL); +unmapVas: + fabricvaspaceUnmapPhysMemdesc(pFabricVAS, pFabricMemDesc, pParams->offset, + pPhysMemDesc, pParams->mapLength); + +freeDupedMem: + NV_ASSERT_OK(pRmApi->Free(pRmApi, pFabricVAS->hClient, hDupedPhysMem)); + + return status; +} + +NV_STATUS +memorymulticastfabricCtrlAttachMem_IMPL +( + MemoryMulticastFabric *pMemoryMulticastFabric, + NV00FD_CTRL_ATTACH_MEM_PARAMS *pParams +) +{ + Fabric *pFabric = SYS_GET_FABRIC(SYS_GET_INSTANCE()); + NV_STATUS status = NV_OK; + + fabricMulticastFabricOpsMutexAcquire(pFabric); + + status = _memorymulticastfabricCtrlAttachMem(pMemoryMulticastFabric, + pParams); + + fabricMulticastFabricOpsMutexRelease(pFabric); return status; } @@ -1375,12 +1447,6 @@ return NV_TRUE; } -// -// memorymulticastfabricCopyConstruct_IMPL does not take -// the multicast fabric mutex lock as it can be invoked -// with the GPU locks held which would result in a lock -// inversion. Hence we resort to portAtomics here. -// NV_STATUS memorymulticastfabricCopyConstruct_IMPL ( @@ -1390,6 +1456,9 @@ ) { MEM_MULTICAST_FABRIC_DESCRIPTOR *pMulticastFabricDesc; + Fabric *pFabric = SYS_GET_FABRIC(SYS_GET_INSTANCE()); + + fabricMulticastFabricOpsMutexAcquire(pFabric); MemoryMulticastFabric *pSourceMemoryMulticastFabric = dynamicCast(pParams->pSrcRef->pResource, MemoryMulticastFabric); @@ -1398,13 +1467,15 @@ pMemoryMulticastFabric->pMulticastFabricDesc = pMulticastFabricDesc; - portAtomicExIncrementU64(&pMulticastFabricDesc->refCount); + pMulticastFabricDesc->refCount++; + + fabricMulticastFabricOpsMutexRelease(pFabric); return NV_OK; } -NV_STATUS -memorymulticastfabricCtrlGetInfo_IMPL +static NV_STATUS +_memorymulticastfabricCtrlGetInfo ( MemoryMulticastFabric *pMemoryMulticastFabric, NV00FD_CTRL_GET_INFO_PARAMS *pParams @@ -1423,12 +1494,26 @@ return NV_OK; } -// -// memorymulticastfabricIsReady_IMPL does not take -// the multicast fabric mutex lock as it can be invoked -// with the GPU locks held which would result in a lock -// inversion. Hence we resort to portAtomics here. -// +NV_STATUS +memorymulticastfabricCtrlGetInfo_IMPL +( + MemoryMulticastFabric *pMemoryMulticastFabric, + NV00FD_CTRL_GET_INFO_PARAMS *pParams +) +{ + Fabric *pFabric = SYS_GET_FABRIC(SYS_GET_INSTANCE()); + NV_STATUS status = NV_OK; + + fabricMulticastFabricOpsMutexAcquire(pFabric); + + status = _memorymulticastfabricCtrlGetInfo(pMemoryMulticastFabric, + pParams); + + fabricMulticastFabricOpsMutexRelease(pFabric); + + return status; +} + NV_STATUS memorymulticastfabricIsReady_IMPL ( @@ -1436,16 +1521,21 @@ NvBool bCopyConstructorContext ) { + Fabric *pFabric = SYS_GET_FABRIC(SYS_GET_INSTANCE()); Memory *pMemory = staticCast(pMemoryMulticastFabric, Memory); MEM_MULTICAST_FABRIC_DESCRIPTOR *pMulticastFabricDesc; NV_STATUS mcTeamStatus; - pMulticastFabricDesc = pMemoryMulticastFabric->pMulticastFabricDesc; + fabricMulticastFabricOpsMutexAcquire(pFabric); - mcTeamStatus = portAtomicOrU32(&pMulticastFabricDesc->mcTeamStatus, 0); + pMulticastFabricDesc = pMemoryMulticastFabric->pMulticastFabricDesc; + mcTeamStatus = pMulticastFabricDesc->mcTeamStatus; if (bCopyConstructorContext && (mcTeamStatus == NV_ERR_NOT_READY)) + { + fabricMulticastFabricOpsMutexRelease(pFabric); return NV_OK; + } if (pMemory->pMemDesc != pMulticastFabricDesc->pMemDesc) { @@ -1457,11 +1547,13 @@ NVOS32_MEM_TAG_NONE, NULL)); } + fabricMulticastFabricOpsMutexRelease(pFabric); + return mcTeamStatus; } -NV_STATUS -memorymulticastfabricCtrlRegisterEvent_IMPL +static NV_STATUS +_memorymulticastfabricCtrlRegisterEvent ( MemoryMulticastFabric *pMemoryMulticastFabric, NV00FD_CTRL_REGISTER_EVENT_PARAMS *pParams @@ -1476,20 +1568,23 @@ } NV_STATUS -memorymulticastfabricControl_Prologue_IMPL +memorymulticastfabricCtrlRegisterEvent_IMPL ( - MemoryMulticastFabric *pMemoryMulticastFabric, - CALL_CONTEXT *pCallContext, - RS_RES_CONTROL_PARAMS_INTERNAL *pParams + MemoryMulticastFabric *pMemoryMulticastFabric, + NV00FD_CTRL_REGISTER_EVENT_PARAMS *pParams ) { - RmResource *pResource = staticCast(pMemoryMulticastFabric, RmResource); + Fabric *pFabric = SYS_GET_FABRIC(SYS_GET_INSTANCE()); + NV_STATUS status = NV_OK; + + fabricMulticastFabricOpsMutexAcquire(pFabric); + + status = _memorymulticastfabricCtrlRegisterEvent(pMemoryMulticastFabric, + pParams); - // Other control calls, nothing to be validated. - if (pParams->cmd != NV00FD_CTRL_CMD_ATTACH_MEM) - return rmresControl_Prologue_IMPL(pResource, pCallContext, pParams); + fabricMulticastFabricOpsMutexRelease(pFabric); - return _memMulticastFabricGpuOsInfoAddUnderLock(pMemoryMulticastFabric, pParams); + return status; } NV_STATUS @@ -1500,13 +1595,10 @@ RS_RES_CONTROL_PARAMS_INTERNAL *pParams ) { - Fabric *pFabric = SYS_GET_FABRIC(SYS_GET_INSTANCE()); NV_STATUS status = NV_OK; - if (pParams->cmd != NV00FD_CTRL_CMD_ATTACH_MEM) - { + if (pParams->cmd != NV00FD_CTRL_CMD_ATTACH_GPU) status = memorymulticastfabricIsReady(pMemoryMulticastFabric, NV_FALSE); - } // // If clients try to register when the multicast object @@ -1514,7 +1606,7 @@ // descriptor is already installed. // // If the status is NV_ERR_NOT_READY then we are yet to - // receive the inband reponse and we register the event. + // receive the inband response and we register the event. // if (pParams->cmd == NV00FD_CTRL_CMD_REGISTER_EVENT) { @@ -1526,25 +1618,22 @@ } else { + // Clients may busy-loop on this error status, don't log error. + if (status == NV_ERR_NOT_READY) + return status; + NV_CHECK_OK_OR_RETURN(LEVEL_ERROR, status); } - fabricMulticastFabricOpsMutexAcquire(pFabric); - - status = resControl_IMPL(staticCast(pMemoryMulticastFabric, RsResource), - pCallContext, pParams); - - fabricMulticastFabricOpsMutexRelease(pFabric); - - return status; + // + // Note: GPU lock(s) is required for some control calls. Thus, it is + // incorrect to take the leaf lock here. resControl_IMPL() attempts to + // acquire the GPU locks before it calls the control call body. + // + return resControl_IMPL(staticCast(pMemoryMulticastFabric, RsResource), + pCallContext, pParams); } -// -// memorymulticastfabricIsGpuMapAllowed_IMPL does not take -// the multicast fabric mutex lock as it can be invoked -// with the GPU locks held which would result in a lock -// inversion. Hence we resort to portAtomics here. -// NvBool memorymulticastfabricIsGpuMapAllowed_IMPL ( @@ -1552,12 +1641,17 @@ OBJGPU *pGpu ) { + Fabric *pFabric = SYS_GET_FABRIC(SYS_GET_INSTANCE()); MEM_MULTICAST_FABRIC_DESCRIPTOR *pMulticastFabricDesc; NvU32 attachedGpusMask; + fabricMulticastFabricOpsMutexAcquire(pFabric); + pMulticastFabricDesc = pMemoryMulticastFabric->pMulticastFabricDesc; - attachedGpusMask = portAtomicOrU32(&pMulticastFabricDesc->attachedGpusMask, 0); + attachedGpusMask = pMulticastFabricDesc->attachedGpusMask; + + fabricMulticastFabricOpsMutexRelease(pFabric); return ((attachedGpusMask & NVBIT32(pGpu->gpuInstance)) != 0U); } diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/kernel/mem_mgr/phys_mem.c nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/kernel/mem_mgr/phys_mem.c --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/kernel/mem_mgr/phys_mem.c 2023-10-25 20:21:26.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/kernel/mem_mgr/phys_mem.c 2024-03-05 22:13:56.000000000 +0000 @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 2018-2021 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2018-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -31,6 +31,7 @@ #include "gpu/mem_mgr/mem_mgr.h" #include "gpu/mem_mgr/heap.h" #include "gpu/mem_sys/kern_mem_sys.h" +#include "gpu/bus/kern_bus.h" #include "gpu/device/device.h" #include "rmapi/client.h" #include "virtualization/hypervisor/hypervisor.h" @@ -67,6 +68,7 @@ NvU32 attr2 = 0; const MEMORY_SYSTEM_STATIC_CONFIG *pMemorySystemConfig = kmemsysGetStaticConfig(pGpu, GPU_GET_KERNEL_MEMORY_SYSTEM(pGpu)); + KernelBus *pKernelBus = GPU_GET_KERNEL_BUS(pGpu); NV_ASSERT_OR_RETURN(RMCFG_FEATURE_KERNEL_RM, NV_ERR_NOT_SUPPORTED); @@ -106,7 +108,17 @@ attr2 |= DRF_DEF(OS32, _ATTR2, _PAGE_SIZE_HUGE, _2MB); break; default: - attr |= DRF_DEF(OS32, _ATTR, _PAGE_SIZE, _BIG); + if (bCompressedKind && + pKernelBus->bar1[GPU_GFID_PF].bStaticBar1Enabled) + { + NV_ASSERT_OR_RETURN(kgmmuIsHugePageSupported(pKernelGmmu), NV_ERR_INVALID_ARGUMENT); + attr |= DRF_DEF(OS32, _ATTR, _PAGE_SIZE, _HUGE); + attr2 |= DRF_DEF(OS32, _ATTR2, _PAGE_SIZE_HUGE, _2MB); + } + else + { + attr |= DRF_DEF(OS32, _ATTR, _PAGE_SIZE, _BIG); + } break; } diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/kernel/mem_mgr/pool_alloc.c nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/kernel/mem_mgr/pool_alloc.c --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/kernel/mem_mgr/pool_alloc.c 2023-10-25 20:21:26.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/kernel/mem_mgr/pool_alloc.c 2024-03-05 22:13:57.000000000 +0000 @@ -1,4 +1,4 @@ -/* + /* * SPDX-FileCopyrightText: Copyright (c) 2016-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * @@ -39,6 +39,7 @@ /* ------------------------------------ Local Defines ------------------------------ */ #define PMA_CHUNK_SIZE_512M (512 * 1024 * 1024) +#define PMA_CHUNK_SIZE_4M (4 * 1024 * 1024) #define PMA_CHUNK_SIZE_2M (2 * 1024 * 1024) #define PMA_CHUNK_SIZE_512K (512 * 1024) #define PMA_CHUNK_SIZE_256K (256 * 1024) @@ -81,31 +82,33 @@ */ typedef enum { - RM_POOL_IDX_512M = 0, - RM_POOL_IDX_2M = 1, - RM_POOL_IDX_256K = 2, - RM_POOL_IDX_128K = 3, - RM_POOL_IDX_64K = 4, - RM_POOL_IDX_8K = 5, - RM_POOL_IDX_4K = 6, - RM_POOL_IDX_256B = 7, + RM_POOL_IDX_512M, + RM_POOL_IDX_2M, + RM_POOL_IDX_256K, + RM_POOL_IDX_128K, + RM_POOL_IDX_64K, + RM_POOL_IDX_8K, + RM_POOL_IDX_4K, + RM_POOL_IDX_256B, NUM_POOLS // This should always be the last entry! }POOL_IDX; /*! * This array contains the alloction sizes (in bytes) of each pool. */ -static const NvU32 poolAllocSizes[] = {0x20000000, 0x200000, 0x40000, 0x20000, 0x10000, 0x2000, 0x1000, 0x100}; +static const NvU64 poolAllocSizes[] = { + 0x20000000, 0x200000, 0x40000, 0x20000, 0x10000, 0x2000, 0x1000, 0x100 +}; #define POOL_CONFIG_POOL_IDX 0 #define POOL_CONFIG_CHUNKSIZE_IDX 1 -static const int poolConfig[POOL_CONFIG_MAX_SUPPORTED][POOL_CONFIG_CHUNKSIZE_IDX + 1] = { +static const NvU64 poolConfig[POOL_CONFIG_MAX_SUPPORTED][POOL_CONFIG_CHUNKSIZE_IDX + 1] = { // page size // chunk size { RM_POOL_IDX_256K, PMA_CHUNK_SIZE_512K}, // pool with pageSize = 256K for GMMU_FMT_VERSION_1 { RM_POOL_IDX_4K, PMA_CHUNK_SIZE_64K }, // pool with pageSize = 4K for GMMU_FMT_VERSION_2 { RM_POOL_IDX_512M, PMA_CHUNK_SIZE_512M }, // pool with pageSize = 512MB for RM allocated buffers (unused as of ampere) - { RM_POOL_IDX_2M, PMA_CHUNK_SIZE_2M }, // pool with pageSize = 2MB for RM allocated buffers + { RM_POOL_IDX_2M, PMA_CHUNK_SIZE_4M }, // pool with pageSize = 2MB for RM allocated buffers { RM_POOL_IDX_64K, PMA_CHUNK_SIZE_256K }, // pool with pageSize = 64K for RM allocated buffers { RM_POOL_IDX_4K, PMA_CHUNK_SIZE_64K } // pool with pageSize = 4K for RM allocated buffers }; @@ -177,7 +180,7 @@ */ NvBool bTrimOnFree; - /*! + /*! * Allocate pool in protected memory */ NvBool bProtected; @@ -190,7 +193,7 @@ * pool. * * @param[in] pCtx Context for upstream allocator. - * @param[in] pageSize Only for debugging. + * @param[in] pageSize Page size to use when allocating from PMA * @param[in] pPage Output page handle from upstream. * * @return NV_STATUS @@ -200,20 +203,20 @@ ( void *pCtx, NvU64 pageSize, + NvU64 numPages, POOLALLOC_HANDLE *pPage ) { PMA_ALLOCATION_OPTIONS allocOptions = {0}; RM_POOL_ALLOC_MEM_RESERVE_INFO *pMemReserveInfo; - NV_STATUS status; + NvU64 i, pageBegin; + NV_STATUS status; NV_ASSERT_OR_RETURN(NULL != pCtx, NV_ERR_INVALID_ARGUMENT); NV_ASSERT_OR_RETURN(NULL != pPage, NV_ERR_INVALID_ARGUMENT); - // TODO: Replace the direct call to PMA with function pointer. pMemReserveInfo = (RM_POOL_ALLOC_MEM_RESERVE_INFO *)pCtx; - allocOptions.flags = PMA_ALLOCATE_PINNED | PMA_ALLOCATE_PERSISTENT | - PMA_ALLOCATE_CONTIGUOUS; + allocOptions.flags = PMA_ALLOCATE_PINNED | PMA_ALLOCATE_PERSISTENT; if (pMemReserveInfo->bSkipScrub) { @@ -225,15 +228,54 @@ allocOptions.flags |= PMA_ALLOCATE_PROTECTED_REGION; } - status = pmaAllocatePages(pMemReserveInfo->pPma, - (NvU32)(pMemReserveInfo->pmaChunkSize/PMA_CHUNK_SIZE_64K), - PMA_CHUNK_SIZE_64K, - &allocOptions, - &pPage->address); - NV_ASSERT_OR_RETURN((NV_OK == status), status); + // + // Some tests fail page table and directory allocation when close to all FB is allocated if we allocate contiguously. + // For now, we're special-casing this supported pageSize and allocating the 64K pages discontigously. + // TODO: Unify the codepaths so that all pages allocated discontiguously (not currently supported by PMA) + // + if (pageSize == PMA_CHUNK_SIZE_64K) + { + NvU64 *pPageStore = portMemAllocNonPaged(sizeof(NvU64) * numPages); + NV_STATUS status = NV_OK; + NV_ASSERT_OK_OR_GOTO(status, + pmaAllocatePages(pMemReserveInfo->pPma, + numPages, + pageSize, + &allocOptions, + pPageStore), + free_mem); + + for (i = 0; i < numPages; i++) + { + pPage[i].address = pPageStore[i]; + pPage[i].pMetadata = NULL; + } +free_mem: + portMemFree(pPageStore); + return status; + } + + allocOptions.flags |= PMA_ALLOCATE_CONTIGUOUS; - pPage->pMetadata = NULL; + for (i = 0; i < numPages; i++) + { + NV_ASSERT_OK_OR_GOTO(status, pmaAllocatePages(pMemReserveInfo->pPma, + pageSize / PMA_CHUNK_SIZE_64K, + PMA_CHUNK_SIZE_64K, + &allocOptions, + &pageBegin), err); + pPage[i].address = pageBegin; + pPage[i].pMetadata = NULL; + } + return NV_OK; +err: + for (;i > 0; i--) + { + NvU32 flags = pMemReserveInfo->bSkipScrub ? PMA_FREE_SKIP_SCRUB : 0; + pmaFreePages(pMemReserveInfo->pPma, &pPage[i - 1].address, 1, + pageSize, flags); + } return status; } @@ -252,17 +294,28 @@ ( void *pCtx, NvU64 pageSize, + NvU64 numPages, POOLALLOC_HANDLE *pPage ) { NV_STATUS status; + NvU64 i; NV_ASSERT_OR_RETURN(NULL != pCtx, NV_ERR_INVALID_ARGUMENT); NV_ASSERT_OR_RETURN(NULL != pPage, NV_ERR_INVALID_ARGUMENT); - status = poolAllocate((POOLALLOC *)pCtx, pPage); - NV_ASSERT_OR_RETURN(status == NV_OK, status); - + for(i = 0; i < numPages; i++) + { + NV_ASSERT_OK_OR_GOTO(status, + poolAllocate((POOLALLOC *)pCtx, &pPage[i]), + cleanup); + } + return NV_OK; +cleanup: + for(;i > 0; i--) + { + poolFree((POOLALLOC *)pCtx, &pPage[i-1]); + } return status; } @@ -444,7 +497,7 @@ flags = FLD_SET_DRF(_RMPOOL, _FLAGS, _AUTO_POPULATE, _DISABLE, flags); } pMemReserveInfo->pPool[pMemReserveInfo->topmostPoolIndex] = poolInitialize( - (NvU32)pMemReserveInfo->pmaChunkSize, + pMemReserveInfo->pmaChunkSize, poolAllocSizes[pMemReserveInfo->topmostPoolIndex], allocUpstreamTopPool, freeUpstreamTopPool, @@ -611,7 +664,7 @@ if (allocSize <= poolAllocSizes[poolIndex]) { NV_PRINTF(LEVEL_INFO, - "Allocating from pool with alloc size = 0x%x Bytes\n", + "Allocating from pool with alloc size = 0x%llx Bytes\n", poolAllocSizes[poolIndex]); break; } @@ -633,7 +686,7 @@ NvU32 index; NV_PRINTF(LEVEL_INFO, - "Allocating from pool with alloc size = 0x%x Bytes\n", + "Allocating from pool with alloc size = 0x%llx Bytes\n", poolAllocSizes[topPool] * numPages); if (memdescGetContiguity(pMemDesc, AT_GPU)) @@ -692,8 +745,7 @@ if (status != NV_OK) { listRemove(pPageHandleList, pPageHandle); - NV_ASSERT_OR_GOTO((NV_OK == status), done); - pPageHandle = NULL; + goto done; } memdescDescribe(pMemDesc, ADDR_FBMEM, pPageHandle->address, pMemDesc->Size); @@ -981,7 +1033,7 @@ ( RM_POOL_ALLOC_MEM_RESERVE_INFO *pMemReserveInfo, NvU64 *pChunkSize, - NvU32 *pPageSize + NvU64 *pPageSize ) { NV_ASSERT_OR_RETURN(pMemReserveInfo != NULL, NV_ERR_INVALID_ARGUMENT); diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/kernel/mem_mgr/standard_mem.c nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/kernel/mem_mgr/standard_mem.c --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/kernel/mem_mgr/standard_mem.c 2023-10-25 20:21:26.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/kernel/mem_mgr/standard_mem.c 2024-03-05 22:13:57.000000000 +0000 @@ -146,7 +146,7 @@ { NV_PRINTF(LEVEL_ERROR, "Encryption requested for video memory on a non-0FB chip;\n"); - return NV_ERR_INVALID_ARGUMENT; + return NV_ERR_INVALID_ARGUMENT; } if (FLD_TEST_DRF(OS32, _ATTR2, _ALLOCATE_FROM_SUBHEAP, _YES, pAllocData->attr2)) @@ -237,7 +237,7 @@ * @returns * The page size in bytes. */ -NvU32 +NvU64 stdmemQueryPageSize ( MemoryManager *pMemoryManager, @@ -256,7 +256,7 @@ // Control calls for system memory objects maintained outside the heap. // -NvU32 stdmemGetSysmemPageSize_IMPL(OBJGPU * pGpu, StandardMemory *pStdMemory) +NvU64 stdmemGetSysmemPageSize_IMPL(OBJGPU * pGpu, StandardMemory *pStdMemory) { return GPU_GET_MEMORY_MANAGER(pGpu)->sysmemPageSize; } diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/kernel/mem_mgr/system_mem.c nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/kernel/mem_mgr/system_mem.c --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/kernel/mem_mgr/system_mem.c 2023-10-25 20:21:26.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/kernel/mem_mgr/system_mem.c 2024-03-05 22:13:58.000000000 +0000 @@ -46,7 +46,6 @@ * @brief * This routine provides common allocation services used by the * following heap allocation functions: - * NVOS32_FUNCTION_ALLOC_DEPTH_WIDTH_HEIGHT * NVOS32_FUNCTION_ALLOC_SIZE * NVOS32_FUNCTION_ALLOC_SIZE_RANGE * NVOS32_FUNCTION_ALLOC_TILED_PITCH_HEIGHT @@ -210,6 +209,15 @@ memdescSetFlag(pMemDesc, MEMDESC_FLAGS_SYSMEM_OWNED_BY_CLIENT, NV_TRUE); + if ((sysGetStaticConfig(SYS_GET_INSTANCE()))->bOsCCEnabled && + gpuIsCCorApmFeatureEnabled(pGpu) && + FLD_TEST_DRF(OS32, _ATTR2, _MEMORY_PROTECTION, _UNPROTECTED, + pAllocData->attr2)) + { + memdescSetFlag(pMemDesc, MEMDESC_FLAGS_ALLOC_IN_UNPROTECTED_MEMORY, + NV_TRUE); + } + memdescSetGpuCacheAttrib(pMemDesc, gpuCacheAttrib); rmStatus = memdescAlloc(pMemDesc); @@ -477,7 +485,7 @@ // While replaying a trace, it is possible for the playback OS to have a smaller page size // than the capture OS so if we're running a replay where the requested page size is larger, // assume this is a contiguous piece of memory, if contiguity is not specified. - // + // if (FLD_TEST_DRF(OS32, _ATTR, _PHYSICALITY, _DEFAULT, pVidHeapAlloc->attr)) { if ((FLD_TEST_DRF(OS32, _ATTR, _PAGE_SIZE, _BIG, pVidHeapAlloc->attr) || diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/kernel/mem_mgr/vaddr_list.c nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/kernel/mem_mgr/vaddr_list.c --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/kernel/mem_mgr/vaddr_list.c 2023-10-25 20:21:26.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/kernel/mem_mgr/vaddr_list.c 2024-03-05 22:13:58.000000000 +0000 @@ -561,7 +561,7 @@ * * @return NV_ERR_OBJECT_NOT_FOUND if VAS not in list */ -NV_STATUS +NV_STATUS vaListGetRefCount(VA_LIST *pVaList, OBJVASPACE *pVAS, NvU64 *pRefCount) { NV_STATUS status = NV_OK; @@ -620,7 +620,7 @@ * * @return NV_ERR_OBJECT_NOT_FOUND if VAS not in list */ -NV_STATUS +NV_STATUS vaListSetRefCount(VA_LIST *pVaList, OBJVASPACE *pVAS, NvU64 refCount) { NV_STATUS status = NV_OK; diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/kernel/mem_mgr/video_mem.c nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/kernel/mem_mgr/video_mem.c --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/kernel/mem_mgr/video_mem.c 2023-10-25 20:21:26.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/kernel/mem_mgr/video_mem.c 2024-03-05 22:13:58.000000000 +0000 @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 2020-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2020-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -34,6 +34,7 @@ #include "diagnostics/gpu_acct.h" #include "Nvcm.h" #include "gpu/bus/third_party_p2p.h" +#include "gpu/bus/kern_bus.h" #include "class/cl0040.h" // NV01_MEMORY_LOCAL_USER @@ -64,7 +65,7 @@ MemoryManager *pMemoryManager = GPU_GET_MEMORY_MANAGER(pGpu); NV_STATUS rmStatus = NV_OK; NvU64 size = pAllocData->size; - NvU32 pageSize = 0; + NvU64 pageSize = 0; NvU64 align = 0; NvU32 retAttr = pAllocData->attr; NvU32 retAttr2 = pAllocData->attr2; @@ -126,20 +127,58 @@ NvU64 size = 0; NvU32 pageCount; NvU32 pmaInfoSize; - NvU32 pageSize; + NvU64 pageSize; NV_STATUS status; NvU64 sizeAlign = 0; PMA_ALLOCATION_OPTIONS allocOptions = {0}; - NvBool bContig = !FLD_TEST_DRF(OS32, _ATTR, - _PHYSICALITY, _NONCONTIGUOUS, - pAllocData->attr); + NvBool bContig; NvU32 subdevInst = gpumgrGetSubDeviceInstanceFromGpu(pGpu); + NvBool bCompressed = !FLD_TEST_DRF(OS32, _ATTR, _COMPR, + _NONE, pAllocData->attr); + KernelBus *pKernelBus = GPU_GET_KERNEL_BUS(pGpu); + NvU32 gfid; + NvU32 pmaConfig = PMA_QUERY_NUMA_ENABLED; + + status = pmaQueryConfigs(pPma, &pmaConfig); + NV_ASSERT(status == NV_OK); + + // + // In NUMA platforms, contig memory is allocated using page order from + // kernel and that could lead to memory wastage when the size is not + // naturally aligned to page order. Prefer non-contig when clients + // are okay with NON_CONTIG. + // + if ((status == NV_OK) && (pmaConfig & PMA_QUERY_NUMA_ENABLED)) + { + bContig = + !FLD_TEST_DRF(OS32, _ATTR, _PHYSICALITY, + _ALLOW_NONCONTIGUOUS, pAllocData->attr) && + !FLD_TEST_DRF(OS32, _ATTR, _PHYSICALITY, + _NONCONTIGUOUS, pAllocData->attr); + } + else + { + bContig = !FLD_TEST_DRF(OS32, _ATTR, + _PHYSICALITY, _NONCONTIGUOUS, + pAllocData->attr); + } // LOCK: acquire device lock status = rmDeviceGpuLocksAcquire(pGpu, GPUS_LOCK_FLAGS_NONE, RM_LOCK_MODULES_MEM_PMA); NV_ASSERT_OR_RETURN(status == NV_OK, status); + if (bCompressed && + (vgpuGetCallingContextGfid(pGpu, &gfid) == NV_OK) && + pKernelBus->bar1[gfid].bStaticBar1Enabled) + { + // Override the attr to use 2MB page size + pAllocData->attr = FLD_SET_DRF(OS32, _ATTR, _PAGE_SIZE, _HUGE, pAllocData->attr); + + NV_PRINTF(LEVEL_INFO, + "Overrode the page size to 2MB on this compressed vidmem for the static bar1\n"); + } + NV_PRINTF(LEVEL_INFO, "PMA input\n"); NV_PRINTF(LEVEL_INFO, " Owner: 0x%x\n", pAllocData->owner); NV_PRINTF(LEVEL_INFO, " hMemory: 0x%x\n", pAllocRequest->hMemory); @@ -278,7 +317,7 @@ pAllocRequest->pPmaAllocInfo[subdevInst]->flags = allocOptions.flags; NV_PRINTF(LEVEL_INFO, "\nNVRM: Size requested: 0x%llx bytes\n", size); - NV_PRINTF(LEVEL_INFO, " PageSize: 0x%x bytes\n", pageSize); + NV_PRINTF(LEVEL_INFO, " PageSize: 0x%llx bytes\n", pageSize); NV_PRINTF(LEVEL_INFO, " PageCount: 0x%x\n", pageCount); NV_PRINTF(LEVEL_INFO, " Actual Size: 0x%llx\n", pAllocRequest->pPmaAllocInfo[subdevInst]->allocSize); @@ -380,7 +419,7 @@ vidmemGetHeap ( OBJGPU *pGpu, - NvHandle hClient, + Device *pDevice, NvBool bSubheap ) { @@ -400,7 +439,8 @@ KernelMIGManager *pKernelMIGManager = GPU_GET_KERNEL_MIG_MANAGER(pGpu); Heap *pMemoryPartitionHeap = NULL; - status = kmigmgrGetMemoryPartitionHeapFromClient(pGpu, pKernelMIGManager, hClient, &pMemoryPartitionHeap); + status = kmigmgrGetMemoryPartitionHeapFromDevice(pGpu, pKernelMIGManager, pDevice, + &pMemoryPartitionHeap); if (status == NV_OK) { if (pMemoryPartitionHeap != NULL) @@ -409,8 +449,8 @@ else { NV_PRINTF(LEVEL_ERROR, - "failed to get memory partition heap for hClient = 0x%x\n", - hClient); + "failed to get memory partition heap for hClient = 0x%x, hDevice = 0x%x\n", + RES_GET_CLIENT_HANDLE(pDevice), RES_GET_HANDLE(pDevice)); return NULL; } } @@ -448,7 +488,6 @@ * @brief * This routine provides common allocation services used by the * following heap allocation functions: - * NVOS32_FUNCTION_ALLOC_DEPTH_WIDTH_HEIGHT * NVOS32_FUNCTION_ALLOC_SIZE * NVOS32_FUNCTION_ALLOC_SIZE_RANGE * NVOS32_FUNCTION_ALLOC_TILED_PITCH_HEIGHT @@ -489,6 +528,8 @@ HWRESOURCE_INFO hwResource; RsClient *pRsClient = pCallContext->pClient; RsResourceRef *pResourceRef = pCallContext->pResourceRef; + RsResourceRef *pDeviceRef; + Device *pDevice; NvU32 gpuCacheAttrib; NvBool bIsPmaAlloc = NV_FALSE; NvU64 sizeOut; @@ -501,6 +542,11 @@ FB_ALLOC_PAGE_FORMAT *pFbAllocPageFormat = NULL; NV_STATUS rmStatus = NV_OK; + NV_ASSERT_OK_OR_RETURN( + refFindAncestorOfType(pResourceRef, classId(Device), &pDeviceRef)); + + pDevice = dynamicCast(pDeviceRef->pResource, Device); + if (RS_IS_COPY_CTOR(pParams)) { if (!rmDeviceGpuLockIsOwner(pGpu->gpuInstance) && !rmGpuLockIsOwner()) @@ -516,6 +562,14 @@ goto done; } + if (FLD_TEST_DRF(OS32, _ATTR, _PHYSICALITY, _DEFAULT, pAllocData->attr)) + { + pAllocData->attr = + FLD_SET_DRF_NUM(OS32, _ATTR, _PHYSICALITY, + pDevice->defaultVidmemPhysicalityOverride, + pAllocData->attr); + } + NV_CHECK_OK_OR_RETURN(LEVEL_WARNING, stdmemValidateParams(pGpu, hClient, pAllocData)); NV_CHECK_OR_RETURN(LEVEL_WARNING, DRF_VAL(OS32, _ATTR, _LOCATION, pAllocData->attr) == NVOS32_ATTR_LOCATION_VIDMEM && @@ -525,9 +579,28 @@ stdmemDumpInputAllocParams(pAllocData, pCallContext); bSubheap = FLD_TEST_DRF(OS32, _ATTR2, _ALLOCATE_FROM_SUBHEAP, _YES, pAllocData->attr2); - pHeap = vidmemGetHeap(pGpu, hClient, bSubheap); + pHeap = vidmemGetHeap(pGpu, pDevice, bSubheap); NV_CHECK_OR_RETURN(LEVEL_INFO, pHeap != NULL, NV_ERR_INVALID_STATE); + if (gpuIsCCorApmFeatureEnabled(pGpu) && + !FLD_TEST_DRF(OS32, _ATTR2, _MEMORY_PROTECTION, _UNPROTECTED, pAllocData->attr2)) + { + pAllocData->flags |= NVOS32_ALLOC_FLAGS_PROTECTED; + } + else if (gpuIsCCFeatureEnabled(pGpu) && + FLD_TEST_DRF(OS32, _ATTR2, _MEMORY_PROTECTION, _UNPROTECTED, pAllocData->attr2)) + { + // CC-TODO: Remove this once non-CPR regions are created + NV_PRINTF(LEVEL_ERROR, "Non-CPR region not yet created\n"); + NV_ASSERT_OR_RETURN(0, NV_ERR_INVALID_ARGUMENT); + } + else if (!gpuIsCCorApmFeatureEnabled(pGpu) && + FLD_TEST_DRF(OS32, _ATTR2, _MEMORY_PROTECTION, _PROTECTED, pAllocData->attr2)) + { + NV_PRINTF(LEVEL_ERROR, "Protected memory not enabled but PROTECTED flag is set by client"); + return NV_ERR_INVALID_ARGUMENT; + } + pAllocRequest->classNum = NV01_MEMORY_LOCAL_USER; pAllocRequest->pUserParams = pAllocData; pAllocRequest->hMemory = pResourceRef->hResource; @@ -558,7 +631,7 @@ { SLI_LOOP_START(SLI_LOOP_FLAGS_BC_ONLY | SLI_LOOP_FLAGS_IGNORE_REENTRANCY) pAllocRequest->pGpu = pGpu; - rmStatus = _vidmemPmaAllocate(vidmemGetHeap(pGpu, hClient, NV_FALSE), pAllocRequest); + rmStatus = _vidmemPmaAllocate(vidmemGetHeap(pGpu, pDevice, NV_FALSE), pAllocRequest); if (NV_OK != rmStatus) SLI_LOOP_GOTO(done); SLI_LOOP_END; @@ -660,7 +733,7 @@ SLI_LOOP_GOTO(done); rmStatus = vidmemAllocResources(pGpu, pMemoryManager, pAllocRequest, pFbAllocInfo, - vidmemGetHeap(pGpu, hClient, NV_FALSE)); + vidmemGetHeap(pGpu, pDevice, NV_FALSE)); if (rmStatus != NV_OK) SLI_LOOP_GOTO(done); @@ -742,6 +815,21 @@ } // + // Set the unprotected flag in memdesc. Some control calls will use + // this flag to determine if this memory lies in the protected or + // unprotected region and use that to gather statistics like total + // protected and unprotected memory usage by different clients, etc + // + if (gpuIsCCorApmFeatureEnabled(pGpu) && + FLD_TEST_DRF(OS32, _ATTR2, _MEMORY_PROTECTION, _UNPROTECTED, pAllocData->attr2)) + { + SLI_LOOP_START(SLI_LOOP_FLAGS_BC_ONLY | SLI_LOOP_FLAGS_IGNORE_REENTRANCY) + memdescSetFlag(memdescGetMemDescFromGpu(pTopLevelMemDesc, pGpu), + MEMDESC_FLAGS_ALLOC_IN_UNPROTECTED_MEMORY, NV_TRUE); + SLI_LOOP_END; + } + + // // Video memory is always locally transparently cached. It does not require // any cache managment. Marked cached unconditionally. Non-coherent peer // caching is handled with an override at mapping time. @@ -872,9 +960,8 @@ if (bSmcGpuPartitioningEnabled) { NV_CHECK_OK_OR_GOTO(rmStatus, LEVEL_ERROR, - kmigmgrGetInstanceRefFromClient(pGpu, pKernelMIGManager, - hClient, - &partitionRef), + kmigmgrGetInstanceRefFromDevice(pGpu, pKernelMIGManager, + pDevice, &partitionRef), done); bGlobalInfo = NV_FALSE; } @@ -920,7 +1007,7 @@ SLI_LOOP_START(SLI_LOOP_FLAGS_BC_ONLY | SLI_LOOP_FLAGS_IGNORE_REENTRANCY) if (pAllocRequest->pPmaAllocInfo[gpumgrGetSubDeviceInstanceFromGpu(pGpu)]) - vidmemPmaFree(pGpu, vidmemGetHeap(pGpu, hClient, NV_FALSE), + vidmemPmaFree(pGpu, vidmemGetHeap(pGpu, pDevice, NV_FALSE), pAllocRequest->pPmaAllocInfo[gpumgrGetSubDeviceInstanceFromGpu(pGpu)], 0); SLI_LOOP_END; } @@ -1061,6 +1148,20 @@ status = NV_ERR_INVALID_ARGUMENT; goto failed; } + // + // In NUMA systems, the memory allocation comes from kernel + // and kernel doesn't support fixed address allocation. + // + if ((pVidHeapAlloc->flags & NVOS32_ALLOC_FLAGS_FIXED_ADDRESS_ALLOCATE) && + bIsPmaOwned && + osNumaOnliningEnabled(pGpu->pOsGpuInfo)) + { + NV_PRINTF(LEVEL_WARNING, + "NVOS32_ALLOC_FLAGS_FIXED_ADDRESS_ALLOCATE for PMA cannot be " + "accommodated for NUMA systems\n"); + status = NV_ERR_INVALID_ARGUMENT; + goto failed; + } if (FLD_TEST_DRF(OS32, _ATTR2, _32BIT_POINTER, _ENABLE, pVidHeapAlloc->attr2)) { NV_PRINTF(LEVEL_WARNING, @@ -1275,12 +1376,13 @@ ( VideoMemory *pVideoMemory, OBJGPU *pDstGpu, - NvHandle hDstClient + Device *pDstDevice ) { Memory *pMemory = staticCast(pVideoMemory, Memory); OBJGPU *pSrcGpu = pMemory->pGpu; NvHandle hSrcClient = RES_GET_CLIENT_HANDLE(pVideoMemory); + NvHandle hDstClient = RES_GET_CLIENT_HANDLE(pDstDevice); KernelMIGManager *pSrcKernelMIGManager = GPU_GET_KERNEL_MIG_MANAGER(pSrcGpu); KernelMIGManager *pDstKernelMIGManager = GPU_GET_KERNEL_MIG_MANAGER(pDstGpu); NvBool bSrcClientKernel = (rmclientGetCachedPrivilegeByHandle(hSrcClient) >= RS_PRIV_LEVEL_KERNEL); @@ -1309,8 +1411,8 @@ // Get memory partition heap from both clients and compare Heap *pDstClientHeap = NULL; NV_CHECK_OK_OR_RETURN(LEVEL_WARNING, - kmigmgrGetMemoryPartitionHeapFromClient(pDstGpu, pDstKernelMIGManager, hDstClient, - &pDstClientHeap)); + kmigmgrGetMemoryPartitionHeapFromDevice(pDstGpu, pDstKernelMIGManager, + pDstDevice, &pDstClientHeap)); // Make sure memory is coming from same heaps if (pDstClientHeap != pMemory->pHeap) @@ -1328,14 +1430,21 @@ // MIG_INSTANCE_REF srcInstRef; MIG_INSTANCE_REF dstInstRef; + RsResourceRef *pSrcDeviceRef; + Device *pSrcDevice; + + NV_ASSERT_OK_OR_RETURN( + refFindAncestorOfType(RES_GET_REF(pMemory), classId(Device), &pSrcDeviceRef)); + + pSrcDevice = dynamicCast(pSrcDeviceRef->pResource, Device); // Check instance subscription of source and destination clients NV_CHECK_OK_OR_RETURN(LEVEL_WARNING, - kmigmgrGetInstanceRefFromClient(pSrcGpu, pSrcKernelMIGManager, hSrcClient, - &srcInstRef)); + kmigmgrGetInstanceRefFromDevice(pSrcGpu, pSrcKernelMIGManager, + pSrcDevice, &srcInstRef)); NV_CHECK_OK_OR_RETURN(LEVEL_WARNING, - kmigmgrGetInstanceRefFromClient(pDstGpu, pDstKernelMIGManager, hDstClient, - &dstInstRef)); + kmigmgrGetInstanceRefFromDevice(pDstGpu, pDstKernelMIGManager, + pDstDevice, &dstInstRef)); // // Memory duping is allowed accross compute instances. so ignore diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/kernel/mem_mgr/virt_mem_range.c nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/kernel/mem_mgr/virt_mem_range.c --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/kernel/mem_mgr/virt_mem_range.c 2023-10-25 20:21:27.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/kernel/mem_mgr/virt_mem_range.c 2024-03-05 22:13:59.000000000 +0000 @@ -126,7 +126,7 @@ if (IS_VIRTUAL(pGpu) || IS_GSP_CLIENT(pGpu)) { NV_RM_RPC_ALLOC_OBJECT(pGpu, hClient, hParent, hMemory, class, - pAllocData, status); + pAllocData, sizeof(*pAllocData), status); if (status != NV_OK) { memdescDestroy(pMemDesc); diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/kernel/mem_mgr/virtual_mem.c nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/kernel/mem_mgr/virtual_mem.c --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/kernel/mem_mgr/virtual_mem.c 2023-10-25 20:21:27.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/kernel/mem_mgr/virtual_mem.c 2024-03-05 22:13:59.000000000 +0000 @@ -270,7 +270,6 @@ * @brief * This routine provides common allocation services used by the * following heap allocation functions: - * NVOS32_FUNCTION_ALLOC_DEPTH_WIDTH_HEIGHT * NVOS32_FUNCTION_ALLOC_SIZE * NVOS32_FUNCTION_ALLOC_SIZE_RANGE * NVOS32_FUNCTION_ALLOC_TILED_PITCH_HEIGHT @@ -947,7 +946,7 @@ OBJGPU *pGpu, NvHandle hDevice, NvU64 size, - NvU32 pageSizeMask + NvU64 pageSizeMask ) { RsClient *pClient = RES_GET_CLIENT(pVirtualMemory); @@ -1089,18 +1088,25 @@ else { KernelBus *pKernelBus = GPU_GET_KERNEL_BUS(pGpu); - NvHandle hClient = NV01_NULL_OBJECT; + Device *pDevice = NULL; CALL_CONTEXT *pCallContext = resservGetTlsCallContext(); if ((pCallContext != NULL) && (pCallContext->pClient != NULL)) { - hClient = pCallContext->pClient->hClient; + RsResourceRef *pDeviceRef = NULL; + + status = refFindAncestorOfType(pCallContext->pResourceRef, + classId(Device), &pDeviceRef); + if (status == NV_OK) + { + pDevice = dynamicCast(pDeviceRef->pResource, Device); + } } status = kbusMapFbAperture_HAL(pGpu, pKernelBus, pMemoryInfo->pMemDesc, offset, &pDmaMappingInfo->FbAperture[gpuSubDevInst], &pDmaMappingInfo->FbApertureLen[gpuSubDevInst], - BUS_MAP_FB_FLAGS_MAP_UNICAST, hClient); + BUS_MAP_FB_FLAGS_MAP_UNICAST, pDevice); if (status != NV_OK) { @@ -1234,7 +1240,6 @@ NvBool bDmaMapNeeded = pParams->bDmaMapNeeded; NvBool bDmaMapped = NV_FALSE; - NvBool bDmaUnmapped = NV_FALSE; NvBool bDmaMappingRegistered = NV_FALSE; NvBool bFlaMapping = pParams->bFlaMapping; NvBool bIsIndirectPeer = NV_FALSE; @@ -1270,7 +1275,7 @@ if (offset + length > pSrcMemDesc->Size) return NV_ERR_INVALID_BASE; - status = intermapCreateDmaMapping(pClient, pMemoryRef, hBroadcastDevice, hVirtualMem, &pDmaMappingInfo, flags); + status = intermapCreateDmaMapping(pClient, pVirtualMemory, &pDmaMappingInfo, flags); if (status != NV_OK) return status; @@ -1323,19 +1328,12 @@ // Different cases for vidmem & system memory/fabric memory. bIsSysmem = (tgtAddressSpace == ADDR_SYSMEM); + bIsSysmem = bIsSysmem || (tgtAddressSpace == ADDR_EGM); if (bIsSysmem || (tgtAddressSpace == ADDR_FABRIC_MC) || (tgtAddressSpace == ADDR_FABRIC_V2)) { - // offset needs to be 0 when reusing a mapping. - if ((DRF_VAL(OS46, _FLAGS, _DMA_UNICAST_REUSE_ALLOC, flags) == NVOS46_FLAGS_DMA_UNICAST_REUSE_ALLOC_TRUE) && - (offset != 0)) - { - status = NV_ERR_INVALID_OFFSET; - goto done; - } - // // Create a MEMORY_DESCRIPTOR describing this region of the memory // alloc in question @@ -1415,7 +1413,7 @@ if (status != NV_OK) goto done; - status = intermapRegisterDmaMapping(pClient, hBroadcastDevice, hVirtualMem, pDmaMappingInfo, pDmaMappingInfo->DmaOffset, gpuMask); + status = intermapRegisterDmaMapping(pClient, pVirtualMemory, pDmaMappingInfo, pDmaMappingInfo->DmaOffset, gpuMask); if (status != NV_OK) { dmaFreeMap(pGpu, pDma, pVas, @@ -1484,7 +1482,7 @@ *pDmaOffset = pDmaMappingInfo->DmaOffset; - status = intermapRegisterDmaMapping(pClient, hBroadcastDevice, hVirtualMem, pDmaMappingInfo, pDmaMappingInfo->DmaOffset, gpuMask); + status = intermapRegisterDmaMapping(pClient, pVirtualMemory, pDmaMappingInfo, pDmaMappingInfo->DmaOffset, gpuMask); if (status != NV_OK) { dmaFreeMap(pGpu, pDma, pVas, @@ -1553,7 +1551,7 @@ pDmaMappingInfo->DmaOffset = *pDmaOffset; - status = intermapRegisterDmaMapping(pClient, hBroadcastDevice, hVirtualMem, pDmaMappingInfo, + status = intermapRegisterDmaMapping(pClient, pVirtualMemory, pDmaMappingInfo, pDmaMappingInfo->DmaOffset, gpuMask); if (status != NV_OK) goto done; @@ -1630,11 +1628,11 @@ if (bDmaMappingRegistered) { - intermapDelDmaMapping(pClient, hBroadcastDevice, hVirtualMem, *pDmaOffset, gpuMask, &bDmaUnmapped); + NV_ASSERT_OK(intermapDelDmaMapping(pClient, pVirtualMemory, *pDmaOffset, gpuMask)); } - if (!bDmaUnmapped) + else { - // Explicitly free the DMA mapping if intermapDelDmaMapping was not able to clean up + // Explicitly free the DMA mapping if mapping was not yet registered intermapFreeDmaMapping(pDmaMappingInfo); } } @@ -1665,7 +1663,6 @@ OBJVASPACE *pVas = NULL; NV_STATUS status = NV_OK; NvBool bIsIndirectPeer = NV_FALSE; - NvBool bReturnStatus; CLI_DMA_MAPPING_INFO *pDmaMappingInfo = NULL; @@ -1702,9 +1699,8 @@ return status; // Get DMA mapping info. - bReturnStatus = CliGetDmaMappingInfo(hClient, hBroadcastDevice, hVirtualMem, dmaOffset, gpuMask, &pDmaMappingInfo); - if (!bReturnStatus) - return NV_ERR_INVALID_OBJECT_HANDLE; + pDmaMappingInfo = intermapGetDmaMapping(pVirtualMemory, dmaOffset, gpuMask); + NV_ASSERT_OR_RETURN(pDmaMappingInfo != NULL, NV_ERR_INVALID_OBJECT_HANDLE); // // if Kernel cookie exists and mapping is in sysmem, free sysmem mapping @@ -1756,19 +1752,13 @@ } } - while (bReturnStatus) - { - // free memory descriptor - memdescFree(pDmaMappingInfo->pMemDesc); - memdescDestroy(pDmaMappingInfo->pMemDesc); - pDmaMappingInfo->pMemDesc = NULL; + // free memory descriptor + memdescFree(pDmaMappingInfo->pMemDesc); + memdescDestroy(pDmaMappingInfo->pMemDesc); + pDmaMappingInfo->pMemDesc = NULL; - // delete client dma mapping - intermapDelDmaMapping(pClient, hBroadcastDevice, hVirtualMem, dmaOffset, gpuMask, NULL); - - // Get the next DMA mapping info for this offset and gpu mask - bReturnStatus = CliGetDmaMappingInfo(hClient, hBroadcastDevice, hVirtualMem, dmaOffset, gpuMask, &pDmaMappingInfo); - } + // delete client dma mapping + intermapDelDmaMapping(pClient, pVirtualMemory, dmaOffset, gpuMask); // // vGPU: diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/kernel/os/os_init.c nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/kernel/os/os_init.c --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/kernel/os/os_init.c 2023-10-25 20:21:27.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/kernel/os/os_init.c 2024-03-05 22:13:59.000000000 +0000 @@ -128,30 +128,13 @@ pOS->osQueueWorkItem = stubOsQueueWorkItem; pOS->osQueueWorkItemWithFlags = stubOsQueueWorkItemWithFlags; pOS->osQueueSystemWorkItem = stubOsQueueSystemWorkItem; - pOS->osCallACPI_MXMX = stubOsCallACPI_MXMX; - pOS->osCallACPI_DDC = stubOsCallACPI_DDC; - pOS->osCallACPI_BCL = stubOsCallACPI_BCL; - pOS->osCallACPI_ON = stubOsCallACPI_ON; - pOS->osCallACPI_OFF = stubOsCallACPI_OFF; - pOS->osCallACPI_NVHG_GPUON = stubOsCallWMI_NVHG_GPUON; - pOS->osCallACPI_NVHG_GPUOFF = stubOsCallWMI_NVHG_GPUOFF; pOS->osCallACPI_NVHG_GPUSTA = stubOsCallWMI_NVHG_GPUSTA; pOS->osCallACPI_NVHG_MXDS = stubOsCallWMI_NVHG_MXDS; pOS->osCallACPI_NVHG_MXMX = stubOsCallWMI_NVHG_MXMX; pOS->osCallACPI_NVHG_DOS = stubOsCallWMI_NVHG_DOS; - pOS->osCallACPI_NVHG_ROM = stubOsCallWMI_NVHG_ROM; pOS->osCallACPI_NVHG_DCS = stubOsCallWMI_NVHG_DCS; - pOS->osCallACPI_DOD = stubOsCallWMI_DOD; pOS->osSetupVBlank = stubOsSetupVBlank; - pOS->osCallACPI_NBPS = stubOsCallACPI_NBPS; - pOS->osCallACPI_NBSL = stubOsCallACPI_NBSL; - pOS->osCallACPI_DSM = stubOsCallACPI_DSM; - pOS->osCallACPI_OPTM_GPUON = stubOsCallWMI_OPTM_GPUON; pOS->osGetUefiVariable = stubOsGetUefiVariable; - pOS->osCallACPI_MXDS = stubOsCallACPI_MXDS; - pOS->osCallACPI_MXDM = stubOsCallACPI_MXDM; - pOS->osCallACPI_MXID = stubOsCallACPI_MXID; - pOS->osCallACPI_LRST = stubOsCallACPI_LRST; } static void @@ -163,9 +146,6 @@ pOS->osNv_rdmsr = stubOsnv_rdmsr; pOS->osNv_wrmsr = stubOsnv_wrmsr; pOS->osRobustChannelsDefaultState = stubOsRobustChannelsDefaultState; - pOS->osCallACPI_MXMX = stubOsCallACPI_MXMX; - pOS->osCallACPI_DDC = stubOsCallACPI_DDC; - pOS->osCallACPI_BCL = stubOsCallACPI_BCL; pOS->osGetUefiVariable = stubOsGetUefiVariable; } @@ -471,7 +451,7 @@ osGetCpuVaAddrShift(void) { NvU64 maxUserVa = osGetMaxUserVa(); - + // // Add 1 to account for kernel VA space, on the assumption // that kernel VA space is the top half of the address space. diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/kernel/os/os_stubs.c nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/kernel/os/os_stubs.c --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/kernel/os/os_stubs.c 2023-10-25 20:21:27.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/kernel/os/os_stubs.c 2024-03-05 22:13:59.000000000 +0000 @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 1993-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 1993-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -140,61 +140,41 @@ return NV_ERR_GENERIC; } -NV_STATUS stubOsCallACPI_MXMX(OBJGPU *pGpu, NvU32 AcpiId, NvU8 *pInOut) +NV_STATUS osCallACPI_MXMX(OBJGPU *pGpu, NvU32 AcpiId, NvU8 *pInOut) { - STUB_CHECK(220); return NV_ERR_NOT_SUPPORTED; } -NV_STATUS stubOsCallACPI_DDC(OBJGPU *pGpu, NvU32 ulAcpiId, NvU8 *pOut, NvU32 *size, NvBool bReadMultiBlock) +NV_STATUS osCallACPI_BCL(OBJGPU *pGpu, NvU32 acpiId, NvU32 *pOut, NvU16 *size) { - STUB_CHECK(221); return NV_ERR_NOT_SUPPORTED; } -NV_STATUS stubOsCallACPI_BCL(OBJGPU *pGpu, NvU32 acpiId, NvU32 *pOut, NvU16 *size) +NV_STATUS osCallACPI_ON(OBJGPU *pGpu, NvU32 uAcpiId) { return NV_ERR_NOT_SUPPORTED; } -NV_STATUS stubOsCallACPI_ON(OBJGPU *pGpu, NvU32 uAcpiId) +NV_STATUS osCallACPI_OFF(OBJGPU *pGpu, NvU32 uAcpiId) { return NV_ERR_NOT_SUPPORTED; } -NV_STATUS stubOsCallACPI_OFF(OBJGPU *pGpu, NvU32 uAcpiId) +NV_STATUS osCallACPI_OPTM_GPUON(OBJGPU *pGpu) { return NV_ERR_NOT_SUPPORTED; } -NV_STATUS stubOsCallACPI_NBPS(OBJGPU *pGpu, NvU8 *pOut, NvU32 *pOutSize) +NV_STATUS osCallACPI_NVHG_GPUON(OBJGPU *pGpu, NvU32 *pInOut) { - *pOutSize = 0; return NV_ERR_NOT_SUPPORTED; } -NV_STATUS stubOsCallACPI_NBSL(OBJGPU *pGpu, NvU32 val) +NV_STATUS osCallACPI_NVHG_GPUOFF(OBJGPU *pGpu, NvU32 *pInOut) { return NV_ERR_NOT_SUPPORTED; } -NV_STATUS stubOsCallWMI_OPTM_GPUON(OBJGPU *pGpu) -{ - return NV_ERR_NOT_SUPPORTED; -} - -NV_STATUS stubOsCallWMI_NVHG_GPUON(OBJGPU *pGpu, NvU32 *pInOut) -{ - //STUB_CHECK(225); - return NV_ERR_NOT_SUPPORTED; -} - -NV_STATUS stubOsCallWMI_NVHG_GPUOFF(OBJGPU *pGpu, NvU32 *pInOut) -{ - //STUB_CHECK(226); - return NV_ERR_NOT_SUPPORTED; -} - NV_STATUS stubOsCallWMI_NVHG_GPUSTA(OBJGPU *pGpu, NvU32 *pInOut) { //STUB_CHECK(227); @@ -219,46 +199,18 @@ return NV_ERR_NOT_SUPPORTED; } -NV_STATUS stubOsCallWMI_NVHG_ROM(OBJGPU *pGpu, NvU32 *pIn, NvU32 *pOut) -{ - //STUB_CHECK(231); - return NV_ERR_NOT_SUPPORTED; -} - NV_STATUS stubOsCallWMI_NVHG_DCS(OBJGPU *pGpu, NvU32 AcpiId, NvU32 *pInOut) { //STUB_CHECK(232); return NV_ERR_NOT_SUPPORTED; } -NV_STATUS stubOsCallWMI_DOD(OBJGPU *pGpu, NvU32 *pInOut, NvU32 *pOutSize) -{ - //STUB_CHECK(233); - return NV_ERR_NOT_SUPPORTED; -} - - -NV_STATUS stubOsCallACPI_DSM(OBJGPU *pGpu, ACPI_DSM_FUNCTION acpiDSMFunction, NvU32 NVHGDSMSubfunction, NvU32 *pInOut, NvU16 *size) -{ - return NV_ERR_NOT_SUPPORTED; -} - -NV_STATUS stubOsCallACPI_MXDS(OBJGPU *pGpu, NvU32 ulAcpiId, NvU32 *pInOut) -{ - return NV_ERR_NOT_SUPPORTED; -} - -NV_STATUS stubOsCallACPI_MXDM(OBJGPU *pGpu, NvU32 ulAcpiId, NvU32 *pInOut) +NV_STATUS osCallACPI_MXID(OBJGPU *pGpu, NvU32 ulAcpiId, NvU32 *pInOut) { return NV_ERR_NOT_SUPPORTED; } -NV_STATUS stubOsCallACPI_MXID(OBJGPU *pGpu, NvU32 ulAcpiId, NvU32 *pInOut) -{ - return NV_ERR_NOT_SUPPORTED; -} - -NV_STATUS stubOsCallACPI_LRST(OBJGPU *pGpu, NvU32 ulAcpiId, NvU32 *pInOut) +NV_STATUS osCallACPI_LRST(OBJGPU *pGpu, NvU32 ulAcpiId, NvU32 *pInOut) { return NV_ERR_NOT_SUPPORTED; } @@ -460,27 +412,34 @@ { return; } -#endif NV_STATUS -osTegraSocParseFixedModeTimings +osTegraSocHspSemaphoreAcquire ( - OS_GPU_INFO *pOsGpuInfo, - NvU32 dcbIndex, - OS_FIXED_MODE_TIMINGS *pFixedModeTimings + NvU32 ownerId, + NvBool bAcquire, + NvU64 timeout ) { - return NV_OK; + return NV_ERR_NOT_SUPPORTED; } - -NV_STATUS osVgpuAllocVmbusEventDpc(void **ppArg1) +NvBool +osTegraSocGetHdcpEnabled(OS_GPU_INFO *pOsGpuInfo) { - return NV_OK; + return NV_TRUE; } +#endif -void osVgpuScheduleVmbusEventDpc(void *pArg1, void *pArg2) +NV_STATUS +osTegraSocParseFixedModeTimings +( + OS_GPU_INFO *pOsGpuInfo, + NvU32 dcbIndex, + OS_FIXED_MODE_TIMINGS *pFixedModeTimings +) { + return NV_OK; } NV_STATUS osLockPageableDataSection(RM_PAGEABLE_SECTION *pSection) @@ -692,26 +651,15 @@ return NV_ERR_NOT_SUPPORTED; } -NvU32 osGetDynamicPowerSupportMask(void) -{ - return 0; -} - -void osUnrefGpuAccessNeeded(OS_GPU_INFO *pOsGpuInfo) -{ - return; -} - -NV_STATUS osRefGpuAccessNeeded(OS_GPU_INFO *pOsGpuInfo) -{ - return NV_OK; -} - -void osClientGcoffDisallowRefcount( - OS_GPU_INFO *pArg1, - NvBool arg2 +NV_STATUS +osGetNvGlobalRegistryDword +( + OBJGPU *pGpu, + const char *pRegParmStr, + NvU32 *pData ) { + return NV_ERR_NOT_SUPPORTED; } #if !RMCFG_FEATURE_PLATFORM_DCE /* dce_core_rm_clk_reset.c */ && \ @@ -829,16 +777,16 @@ { return NV_ERR_NOT_SUPPORTED; } -#endif -#if !(RMCFG_FEATURE_PLATFORM_UNIX) || \ - (RMCFG_FEATURE_PLATFORM_UNIX && !RMCFG_FEATURE_TEGRA_SOC_NVDISPLAY) NvU32 osTegraSocFuseRegRead(NvU32 addr) { return 0; } +#endif +#if !(RMCFG_FEATURE_PLATFORM_UNIX) || \ + (RMCFG_FEATURE_PLATFORM_UNIX && !RMCFG_FEATURE_TEGRA_SOC_NVDISPLAY) NV_STATUS osTegraSocDpUphyPllInit(OS_GPU_INFO *pOsGpuInfo, NvU32 link_rate, NvU32 lanes) { @@ -853,3 +801,4 @@ #endif + diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/kernel/platform/acpi_common.c nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/kernel/platform/acpi_common.c --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/kernel/platform/acpi_common.c 2023-10-25 20:21:27.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/kernel/platform/acpi_common.c 2024-03-05 22:13:59.000000000 +0000 @@ -358,13 +358,13 @@ // Use NV_ASSERT_OR_ELSE_STR for embedded %. // NV_ASSERT_OR_ELSE_STR( - !(NV_ARRAY_ELEMENTS32(genDsmSubFuncRemapTable) % (ACPI_DSM_FUNCTION_COUNT + 1)), - "!(NV_ARRAY_ELEMENTS32(genDsmSubFuncRemapTable) %% (ACPI_DSM_FUNCTION_COUNT + 1))", + !(NV_ARRAY_ELEMENTS(genDsmSubFuncRemapTable) % (ACPI_DSM_FUNCTION_COUNT + 1)), + "!(NV_ARRAY_ELEMENTS(genDsmSubFuncRemapTable) %% (ACPI_DSM_FUNCTION_COUNT + 1))", return NV_ERR_INVALID_ARGUMENT); // find the event in the table i = 0; - while (i <= (NV_ARRAY_ELEMENTS32(genDsmSubFuncRemapTable) - ACPI_DSM_FUNCTION_COUNT - 1)) + while (i <= (NV_ARRAY_ELEMENTS(genDsmSubFuncRemapTable) - ACPI_DSM_FUNCTION_COUNT - 1)) { if (acpiDsmSubFunction == genDsmSubFuncRemapTable[i]) { @@ -823,11 +823,11 @@ // try package type for argument 3. pGpu->acpi.dsm[func].bArg3isInteger = NV_FALSE; rtnSize = sizeof(supportFuncs); - status = pGpu->pOS->osCallACPI_DSM(pGpu, - func, - NV_ACPI_ALL_FUNC_SUPPORT, - (NvU32 *) &supportFuncs, - &rtnSize); + status = osCallACPI_DSM(pGpu, + func, + NV_ACPI_ALL_FUNC_SUPPORT, + (NvU32 *) &supportFuncs, + &rtnSize); if (status != NV_OK) { if (status == NV_ERR_INVALID_ARGUMENT) @@ -835,11 +835,11 @@ // maybe an older SBIOS, try integer type for argument 3. pGpu->acpi.dsm[func].bArg3isInteger = NV_TRUE; rtnSize = sizeof(supportFuncs); - status = pGpu->pOS->osCallACPI_DSM(pGpu, - func, - NV_ACPI_ALL_FUNC_SUPPORT, - (NvU32 *) &supportFuncs, - &rtnSize); + status = osCallACPI_DSM(pGpu, + func, + NV_ACPI_ALL_FUNC_SUPPORT, + (NvU32 *) &supportFuncs, + &rtnSize); } } if (_isDsmError(status, rtnSize, (NvU32 *) &supportFuncs)) @@ -857,7 +857,7 @@ } } -static void +static void _acpiDsmCallbackInit ( OBJGPU *pGpu @@ -908,11 +908,11 @@ if (testIfDsmSubFunctionEnabled(pGpu, func, NV_ACPI_GENERIC_FUNC_CALLBACKS) == NV_OK) { - status = pGpu->pOS->osCallACPI_DSM(pGpu, - func, - NV_ACPI_GENERIC_FUNC_CALLBACKS, - &callbacks, - &rtnSize); + status = osCallACPI_DSM(pGpu, + func, + NV_ACPI_GENERIC_FUNC_CALLBACKS, + &callbacks, + &rtnSize); if (_isDsmError(status, rtnSize, &callbacks)) { @@ -963,7 +963,7 @@ * * @returns */ -static void +static void _acpiDsmCapsInit ( OBJGPU *pGpu @@ -981,11 +981,11 @@ if (testIfDsmSubFunctionEnabled(pGpu, func, asmDsmSubFunction) == NV_OK) { rtnSize = sizeof(platCaps); - status = pGpu->pOS->osCallACPI_DSM(pGpu, - func, - asmDsmSubFunction, - &platCaps, - &rtnSize); + status = osCallACPI_DSM(pGpu, + func, + asmDsmSubFunction, + &platCaps, + &rtnSize); if (_isDsmError(status, rtnSize, &platCaps)) { @@ -1108,7 +1108,6 @@ ) { NV_STATUS status; - OBJOS *pOs = GPU_GET_OS(pGpu); NvU32 inOut = 0; NvU16 rtnSize = sizeof(inOut); NvU32 tableLen = 0, acpiidIndex = 0, mode = 0, muxPartId = 0; @@ -1119,16 +1118,17 @@ // Fill in the DOD Method Data. pGpu->acpiMethodData.dodMethodData.acpiIdListLen = sizeof(pGpu->acpiMethodData.dodMethodData.acpiIdList); - status = pOs->osCallACPI_DOD(pGpu, pGpu->acpiMethodData.dodMethodData.acpiIdList, &pGpu->acpiMethodData.dodMethodData.acpiIdListLen); + status = osCallACPI_DOD(pGpu, pGpu->acpiMethodData.dodMethodData.acpiIdList, &pGpu->acpiMethodData.dodMethodData.acpiIdListLen); pGpu->acpiMethodData.dodMethodData.status = status; // Fill in the JT Method Data. - status = pOs->osCallACPI_DSM(pGpu, ACPI_DSM_FUNCTION_JT, JT_FUNC_CAPS, &inOut, &rtnSize); + status = osCallACPI_DSM(pGpu, ACPI_DSM_FUNCTION_JT, JT_FUNC_CAPS, &inOut, &rtnSize); pGpu->acpiMethodData.jtMethodData.status = status; pGpu->acpiMethodData.jtMethodData.jtCaps = inOut; - pGpu->acpiMethodData.jtMethodData.jtRevId = (NvU16)DRF_VAL(_JT_FUNC, _CAPS, _REVISION_ID, inOut); + pGpu->acpiMethodData.jtMethodData.jtRevId = (NvU16)DRF_VAL(_JT_FUNC, _CAPS, _REVISION_ID, inOut); + gpuSetGC6SBIOSCapabilities(pGpu); // Fill in the MUX Method Data. portMemSet(pGpu->acpiMethodData.muxMethodData.acpiIdMuxModeTable, 0, sizeof(pGpu->acpiMethodData.muxMethodData.acpiIdMuxModeTable)); @@ -1139,12 +1139,12 @@ pGpu->acpiMethodData.muxMethodData.tableLen = tableLen; for (acpiidIndex = 0; acpiidIndex < tableLen; acpiidIndex++) { - status = pOs->osCallACPI_MXDM(pGpu, pGpu->acpiMethodData.dodMethodData.acpiIdList[acpiidIndex], &mode); + status = osCallACPI_MXDM(pGpu, pGpu->acpiMethodData.dodMethodData.acpiIdList[acpiidIndex], &mode); pGpu->acpiMethodData.muxMethodData.acpiIdMuxModeTable[acpiidIndex].acpiId = pGpu->acpiMethodData.dodMethodData.acpiIdList[acpiidIndex]; pGpu->acpiMethodData.muxMethodData.acpiIdMuxModeTable[acpiidIndex].mode = mode; pGpu->acpiMethodData.muxMethodData.acpiIdMuxModeTable[acpiidIndex].status = status; - status = pOs->osCallACPI_MXID(pGpu, pGpu->acpiMethodData.dodMethodData.acpiIdList[acpiidIndex], &muxPartId); + status = osCallACPI_MXID(pGpu, pGpu->acpiMethodData.dodMethodData.acpiIdList[acpiidIndex], &muxPartId); pGpu->acpiMethodData.muxMethodData.acpiIdMuxPartTable[acpiidIndex].acpiId = pGpu->acpiMethodData.dodMethodData.acpiIdList[acpiidIndex]; pGpu->acpiMethodData.muxMethodData.acpiIdMuxPartTable[acpiidIndex].mode = muxPartId; pGpu->acpiMethodData.muxMethodData.acpiIdMuxPartTable[acpiidIndex].status = status; @@ -1153,8 +1153,8 @@ } // Fill in the Optimus caps Method Data. - status = pGpu->pOS->osCallACPI_DSM(pGpu, ACPI_DSM_FUNCTION_NVOP, NVOP_FUNC_OPTIMUSCAPS, - &pGpu->acpiMethodData.capsMethodData.optimusCaps, &rtnSize); + status = osCallACPI_DSM(pGpu, ACPI_DSM_FUNCTION_NVOP, NVOP_FUNC_OPTIMUSCAPS, + &pGpu->acpiMethodData.capsMethodData.optimusCaps, &rtnSize); pGpu->acpiMethodData.capsMethodData.status = status; } diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/kernel/platform/chipset/chipset.c nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/kernel/platform/chipset/chipset.c --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/kernel/platform/chipset/chipset.c 2023-10-25 20:21:27.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/kernel/platform/chipset/chipset.c 2024-03-05 22:13:59.000000000 +0000 @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 1993-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 1993-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -82,6 +82,12 @@ } } + if ((osReadRegistryDword(pGpu, NV_REG_STR_RM_FORCE_DISABLE_IOMAP_WC, &data32) == NV_OK) + && (data32 == NV_REG_STR_RM_FORCE_DISABLE_IOMAP_WC_YES)) + { + pCl->setProperty(pCl, PDB_PROP_CL_DISABLE_IOMAP_WC, NV_TRUE); + } + pOS->osQADbgRegistryInit(pOS); } @@ -133,7 +139,7 @@ NvU16 vendorID, deviceID; NvBool bFoundDevice = NV_FALSE; - if (IsT194(pGpu)) + if (IsT194(pGpu) || IsT234(pGpu)) return NV0000_CTRL_GPU_INVALID_ID; // do we already know our domain/bus/device? @@ -191,7 +197,7 @@ if (gpuGetDBDF(pGpu) == 0) { - if (!(IS_SIMULATION(pGpu)|| IS_SIM_MODS(GPU_GET_OS(pGpu))) + if (!(IS_SIMULATION(pGpu)|| IS_SIM_MODS(GPU_GET_OS(pGpu))) || (bFoundDevice == NV_FALSE)) { NV_PRINTF(LEVEL_ERROR, @@ -210,7 +216,7 @@ static void getSubsystemFromPCIECapabilities ( NvU32 domain, - NvU8 bus, + NvU8 bus, NvU8 device, NvU8 func, NvU16 *subvendorID, @@ -486,7 +492,7 @@ } } - if (vendorID == PCI_INVALID_VENDORID) + if (!PCI_IS_VENDORID_VALID(vendorID)) break; // skip to the next device if ((osPciReadByte(handle, PCI_HEADER_TYPE0_BASECLASS)) != PCI_CLASS_BRIDGE_DEV) @@ -605,41 +611,65 @@ return bEnable; } -// -// return the First Host Bridge's handle, VendorID and DeviceID -// -NV_STATUS -clGetFHBHandle_IMPL( - OBJCL *pCl, - void **Handle, - NvU16 *VendorID, - NvU16 *DeviceID +/*! + * @brief Check if L0s mask is enabled for upstream component + * + * @param[in] pGpu GPU object pointer + * @param[in] pCl CL object pointer + * + * @return NV_TRUE if mask is enabled (implies L0s is disabled) + */ +NvBool +clIsL0sMaskEnabledForUpstreamPort_IMPL +( + OBJGPU *pGpu, + OBJCL *pCl ) { - NV_ASSERT(Handle && DeviceID && VendorID); // Avoid Null Pointer - - if (!pCl->FHBAddr.valid) - return NV_ERR_GENERIC; - - *Handle = pCl->FHBAddr.handle; - *DeviceID = pCl->FHBBusInfo.deviceID; - *VendorID = pCl->FHBBusInfo.vendorID; + NvU32 linkCtrl; + NvBool bEnable = NV_FALSE; - // can this happen, should this be #if 0 out? - if (*Handle == NULL) + if (!pGpu->gpuClData.upstreamPort.addr.valid) { - *Handle = osPciInitHandle(pCl->FHBAddr.domain, - pCl->FHBAddr.bus, - pCl->FHBAddr.device, - pCl->FHBAddr.func, - VendorID, - DeviceID); + if (!pGpu->gpuClData.rootPort.addr.valid) + { + bEnable = NV_TRUE; + } + else + { + if (clPcieReadPortConfigReg(pGpu, pCl, &pGpu->gpuClData.rootPort, + CL_PCIE_LINK_CTRL_STATUS, &linkCtrl) != NV_OK) + { + bEnable = NV_TRUE; + } + else + { + if (!(linkCtrl & CL_PCIE_LINK_CTRL_STATUS_ASPM_L0S_BIT)) + { + bEnable = NV_TRUE; + } + } + } + } + else + { + if (clPcieReadPortConfigReg(pGpu, pCl, &pGpu->gpuClData.upstreamPort, + CL_PCIE_LINK_CTRL_STATUS, &linkCtrl) != NV_OK) + { + bEnable = NV_TRUE; + } + else + { + if (!(linkCtrl & CL_PCIE_LINK_CTRL_STATUS_ASPM_L0S_BIT)) + { + bEnable = NV_TRUE; + } + } } - return (*Handle ? NV_OK : NV_ERR_GENERIC); + return bEnable; } - NV_STATUS clInit_IMPL( OBJGPU *pGpu, @@ -763,6 +793,7 @@ CL_SYNC_PDB(PDB_PROP_CL_ASPM_L1_CHIPSET_DISABLED); CL_SYNC_PDB(PDB_PROP_CL_ASPM_L0S_CHIPSET_ENABLED_MOBILE_ONLY); CL_SYNC_PDB(PDB_PROP_CL_ASPM_L1_CHIPSET_ENABLED_MOBILE_ONLY); + CL_SYNC_PDB(PDB_PROP_CL_ASPM_UPSTREAM_PORT_L1_MASK_ENABLED); CL_SYNC_PDB(PDB_PROP_CL_PCIE_GEN1_GEN2_SWITCH_CHIPSET_DISABLED); CL_SYNC_PDB(PDB_PROP_CL_PCIE_GEN1_GEN2_SWITCH_CHIPSET_DISABLED_GEFORCE); CL_SYNC_PDB(PDB_PROP_CL_EXTENDED_TAG_FIELD_NOT_CAPABLE); diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/kernel/platform/chipset/chipset_info.c nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/kernel/platform/chipset/chipset_info.c --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/kernel/platform/chipset/chipset_info.c 2023-10-25 20:21:27.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/kernel/platform/chipset/chipset_info.c 2024-03-05 22:13:59.000000000 +0000 @@ -948,6 +948,30 @@ } static NV_STATUS +Nvidia_TH500_setupFunc +( + OBJCL *pCl +) +{ + if (!pCl->FHBAddr.valid) + return NV_ERR_GENERIC; + + if (clInsertPcieConfigSpaceBase(pCl, 0, 0, 0, (NvU8)(PCI_MAX_BUSES - 1)) == NV_OK) + pCl->setProperty(pCl, PDB_PROP_CL_PCIE_CONFIG_ACCESSIBLE, NV_TRUE); + + // Enable Gen2 ASLM + pCl->setProperty(pCl, PDB_PROP_CL_ASLM_SUPPORTS_GEN2_LINK_UPGRADE, NV_TRUE); + + pCl->setProperty(pCl, PDB_PROP_CL_IS_CHIPSET_IO_COHERENT, NV_TRUE); + + pCl->setProperty(pCl, PDB_PROP_CL_BUG_3562968_WAR_ALLOW_PCIE_ATOMICS, NV_TRUE); + + _Set_ASPM_L0S_L1(pCl, NV_FALSE, NV_FALSE); + + return NV_OK; +} + +static NV_STATUS SiS_656_setupFunc ( OBJCL *pCl @@ -1210,6 +1234,19 @@ return NV_OK; } +// Mellanox BlueField3 Setup Function +static NV_STATUS +Mellanox_BlueField3_setupFunc +( + OBJCL *pCl +) +{ + // Bug 4151565: BlueField 3 does not support WC mapping + pCl->setProperty(pCl, PDB_PROP_CL_DISABLE_IOMAP_WC, NV_TRUE); + return NV_OK; +} + + // Amazon Gravitron2 Setup Function static NV_STATUS Amazon_Gravitron2_setupFunc @@ -1258,6 +1295,18 @@ ( OBJCL *pCl ) +{ + // TODO Need to check if any more PDB properties should be set + pCl->setProperty(pCl, PDB_PROP_CL_IS_CHIPSET_IO_COHERENT, NV_TRUE); + return NV_OK; +} + +// Ampere AmpereOne Setup Function +static NV_STATUS +Ampere_AmpereOne_setupFunc +( + OBJCL *pCl +) { // TODO Need to check if any more PDB properties should be set pCl->setProperty(pCl, PDB_PROP_CL_IS_CHIPSET_IO_COHERENT, NV_TRUE); diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/kernel/platform/chipset/chipset_pcie.c nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/kernel/platform/chipset/chipset_pcie.c --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/kernel/platform/chipset/chipset_pcie.c 2023-10-25 20:21:28.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/kernel/platform/chipset/chipset_pcie.c 2024-03-05 22:14:00.000000000 +0000 @@ -832,6 +832,93 @@ } } + +#define MAX_MULTI_GPU_BOARD_IDS 4 +typedef struct +{ + NvU16 gpuDevIds[MAX_MULTI_GPU_BOARD_IDS]; + NvU16 gpuSubVenIds[MAX_MULTI_GPU_BOARD_IDS]; + NvU16 gpuSubDevIds[MAX_MULTI_GPU_BOARD_IDS]; +} NV_MULTI_GPU_BOARD_CONFIGS; + +static const NV_MULTI_GPU_BOARD_CONFIGS multiGpuBoards[] = +{ +// gpuDevIds, gpuSubVenIds, gpuSubDevIds + +// A16 GPUs are 4xGPU boards with no nvlink +{{NV_PCI_DEVID_DEVICE_PG171_SKU200_PG179_SKU220, 0}, + {NV_PCI_SUBID_VENDOR_NVIDIA, + 0}, {NV_PCI_SUBID_DEVICE_PG171_SKU200, + 0}}, +}; + +/*! + * Searches through multiGpuBoards[] for the specified DEVID and possibly the + * SSVID and SSDID to determine if the GPU is in a multi GPU board. + * + * @param[in] gpuDevId DEVID of the GPU + * @param[in] gpuSubVenId The subdevice VENID of the GPU + * @param[in] gpuSubDevId The sbudevice DEVID of the GPU + * + * @return NV_TRUE if the GPU is in a multigpu board, NV_FALSE otherwise + */ +static NvBool +gpuDevIdIsMultiGpuBoard +( + NvU16 gpuDevId, + NvU16 gpuSubVenId, + NvU16 gpuSubDevId +) +{ + NvU32 i, j; + NvBool bFound = NV_FALSE, bInvalidSubIds = NV_FALSE; + + for (i = 0; i < sizeof(multiGpuBoards) / sizeof(NV_MULTI_GPU_BOARD_CONFIGS); + i++) + { + bInvalidSubIds = NV_FALSE; + + for (j = 0; j < MAX_MULTI_GPU_BOARD_IDS; j++) + { + // + // As soon as we see a NULL subvenid or subdevid, we stop checking them + // for this entry + // + if ((multiGpuBoards[i].gpuSubVenIds[j] == 0) || + (multiGpuBoards[i].gpuSubDevIds[j] == 0)) + { + bInvalidSubIds = NV_TRUE; + } + + // Arrays are NULL terminated + if (multiGpuBoards[i].gpuDevIds[j] == 0) + { + break; + } + // If the devid matches we might have a match + else if (multiGpuBoards[i].gpuDevIds[j] == gpuDevId) + { + // Do we need to also compare the subdevice ids? + if ((bInvalidSubIds) || + ((multiGpuBoards[i].gpuSubVenIds[j] == gpuSubVenId) && + (multiGpuBoards[i].gpuSubDevIds[j] == gpuSubDevId))) + { + bFound = NV_TRUE; + break; + } + } + } + + if (bFound) + { + break; + } + } + + return bFound; +} + + // // Determine if any updates are needed to the PCI Express // @@ -841,7 +928,6 @@ OBJSYS *pSys = SYS_GET_INSTANCE(); OBJPFM *pPfm = SYS_GET_PFM(pSys); KernelBif *pKernelBif = GPU_GET_KERNEL_BIF(pGpu); - NvBool bIsGemini = NV_FALSE; NvBool bIsMultiGpu; NvU32 busIntfType = kbifGetBusIntfType_HAL(pKernelBif); @@ -886,7 +972,7 @@ // kbifInitPcieDeviceControlStatus(pGpu, pKernelBif); - // + // // Probe root port PCIe atomic capabilities. // kbifProbePcieReqAtomicCaps_HAL should be called from here instead of // kbif construct because of the dependency on the chipset @@ -902,24 +988,28 @@ if (!pPfm->getProperty(pPfm, PDB_PROP_PFM_NO_HOSTBRIDGE_DETECT)) { - // - // MultiGpu board includes all Dagwood and Gemini boards - // A dagwood board would not have bIsGemini flag set but would have - // bIsMultiGpu flag set. - // - bIsMultiGpu = gpuIsMultiGpuBoard(pGpu, &bIsGemini); - if (bIsGemini) - { - pGpu->setProperty(pGpu, PDB_PROP_GPU_IS_GEMINI, NV_TRUE); - } + bIsMultiGpu = gpuIsMultiGpuBoard(pGpu); // Update the board ID only if the Gpu is a multiGpu board if (bIsMultiGpu) { gpumgrUpdateBoardId(pGpu); + + // All multi-GPU boards are Gemini boards. + pGpu->setProperty(pGpu, PDB_PROP_GPU_IS_GEMINI, NV_TRUE); } } + // Initialize ASPM L1 mask state for Upstream port + if (clIsL1MaskEnabledForUpstreamPort(pGpu, pCl)) + { + pCl->setProperty(pCl, PDB_PROP_CL_ASPM_UPSTREAM_PORT_L1_MASK_ENABLED, NV_TRUE); + } + else + { + pCl->setProperty(pCl, PDB_PROP_CL_ASPM_UPSTREAM_PORT_L1_MASK_ENABLED, NV_FALSE); + } + NV_PRINTF(LEVEL_INFO, "Chipset %X Domain %X Bus %X Device %X Func %X PCIE PTR %X\n", pCl->Chipset, @@ -1094,7 +1184,7 @@ if ((kbifGetBusIntfType_HAL(GPU_GET_KERNEL_BIF(pGpu)) != NV2080_CTRL_BUS_INFO_TYPE_FPCI) && (!pHypervisor || !pHypervisor->bDetected) && - !RMCFG_FEATURE_PLATFORM_MODS) + !RMCFG_FEATURE_MODS_FEATURES) { DBG_BREAKPOINT(); return NV_FALSE; @@ -1901,16 +1991,14 @@ // // clCountBR // -// Returns the count of cascaded BR03s and BR04s right under this GPU. +// Returns the count of cascaded BR04s right under this GPU. // void clCountBR_IMPL ( OBJGPU *pGpu, OBJCL *pCl, - NvU8 *pBR03Count, - NvU8 *pBR04Count, - NvU8 *pPLXCount + NvU8 *pBR04Count ) { void *handleUp; @@ -1918,9 +2006,7 @@ NvU8 bus = 0xff, busUp, deviceUp, funcUp; NvU32 domain; NvU8 downstreamPortBus; - NvU8 BR03Count = 0; NvU8 BR04Count = 0; - NvU8 PLXCount = 0; domain = gpuGetDomain(pGpu); handleUp = clFindBrdgUpstreamPort(pGpu, pCl, NV_TRUE, @@ -1930,18 +2016,10 @@ while (handleUp) { - if ((vendorIDUp == PCI_VENDOR_ID_NVIDIA) && (deviceIDUp == NV_BR03_XVU_DEV_ID_DEVICE_ID_BR03)) - { - BR03Count++; - } - else if((vendorIDUp == PCI_VENDOR_ID_NVIDIA) && IS_DEVID_BR04(deviceIDUp)) + if ((vendorIDUp == PCI_VENDOR_ID_NVIDIA) && IS_DEVID_BR04(deviceIDUp)) { BR04Count++; } - else if((vendorIDUp == PCI_VENDOR_ID_PLX) && IS_DEVID_SUPPORTED_PLX(deviceIDUp)) - { - PLXCount++; - } else { break; @@ -1960,9 +2038,7 @@ } } - *pBR03Count = BR03Count; *pBR04Count = BR04Count; - *pPLXCount = PLXCount; return ; } @@ -2032,6 +2108,17 @@ } pBusTopologyInfoBR04GPU = pBusTopologyInfoBR04GPU->next; } + if (pBusTopologyInfoBR04GPU) + { + // There is something + if ((pBusTopologyInfoBR04GPU->busInfo.vendorID == PCI_VENDOR_ID_NVIDIA) && + (gpuDevIdIsMultiGpuBoard(pBusTopologyInfoBR04GPU->busInfo.deviceID, 0, 0))) + { + // This is a BR04 in a Gemini, skip this DS port + pBusTopologyInfoBR04DS = pBusTopologyInfoBR04DS->next; + continue; + } + } BR04DSPorts++; } pBusTopologyInfoBR04DS = pBusTopologyInfoBR04DS->next; @@ -2072,7 +2159,7 @@ // Returns the bus number of a common bridge behind the 2 GPUs. // The returned values are 0xFF when no bridge is found. // This function finds the most upper bridge(s) if bScanAll is set to NV_TRUE. -// This function finds the first recognized bridge (BR04, BR03, PLX) under the GPUs if bScanAll is set to NV_FALSE. +// This function finds the first recognized bridge (BR04) under the GPUs if bScanAll is set to NV_FALSE. // void clFindCommonBR_IMPL @@ -2080,9 +2167,7 @@ OBJGPU *pGpu1, OBJGPU *pGpu2, OBJCL *pCl, - NvU8 *pBR03Bus, NvU8 *pBR04Bus, - NvU8 *pPLXBus, NvBool bScanAll ) { @@ -2091,9 +2176,7 @@ NvU8 bus1 = 0xff, busUp1, deviceUp1, funcUp1, bus2 = 0xff, busUp2, deviceUp2, funcUp2; NvU32 domain1, domain2; NvU8 downstreamPortBus1, downstreamPortBus2; - NvU8 BR03Bus = 0xFF; NvU8 BR04Bus = 0xFF; - NvU8 PLXBus = 0xFF; NV_ASSERT(pGpu1 != pGpu2); @@ -2103,16 +2186,14 @@ if (domain1 != domain2) { // - //1. If two GPUs are from different PCI domains, then there can not be a common BR03/BR04 bridge + //1. If two GPUs are from different PCI domains, then there can not be a common BR04 bridge // that connects to both GPUs. Because a new domain will start form a host bridge. //2. Returning early when two GPUs are from different PCI domains save significant GPU initialization // time when we have more that 6 GPUs in the system connected to different domains. This function // is called multiple times while searching for 2-way 3-way and 4-way sli combination. (Bug 770154) // - *pBR03Bus = BR03Bus; *pBR04Bus = BR04Bus; - *pPLXBus = PLXBus; return; } @@ -2143,21 +2224,6 @@ BR04Bus = busUp2; break; } - - if ((vendorIDUp2 == PCI_VENDOR_ID_NVIDIA) && - (deviceIDUp1 == NV_BR03_XVU_DEV_ID_DEVICE_ID_BR03) && - (deviceIDUp2 == NV_BR03_XVU_DEV_ID_DEVICE_ID_BR03)) - { - BR03Bus = busUp2; - break; - } - if ((vendorIDUp2 == PCI_VENDOR_ID_PLX) && - IS_DEVID_SUPPORTED_PLX(deviceIDUp1) && - IS_DEVID_SUPPORTED_PLX(deviceIDUp2)) - { - PLXBus = busUp2; - break; - } } bus2 = busUp2; @@ -2172,8 +2238,7 @@ // If we requested to not scan all the devices up to the root port, // and we found one, stop right here. // - if (!bScanAll && - ((BR04Bus != 0xFF) || (BR03Bus != 0xFF) || (PLXBus != 0xFF))) + if (!bScanAll && (BR04Bus != 0xFF)) { break; } @@ -2185,9 +2250,7 @@ &funcUp1, &vendorIDUp1, &deviceIDUp1); } - *pBR03Bus = BR03Bus; *pBR04Bus = BR04Bus; - *pPLXBus = PLXBus; return ; } @@ -2303,8 +2366,7 @@ NvU8 *pBR04Bus, NvBool *pBRNot3rdParty, NvBool *pNoUnsupportedBRFound, - NvBool *pNoOnboardBR04, - NvU8 *pPLXBus + NvBool *pNoOnboardBR04 ) { void *handleUp, *br04handle = NULL; @@ -2315,7 +2377,6 @@ NvU32 regValue = 0; NvU32 gpuBrNot3rdPartyCount = 0, gpuBrCount = 0; NvBool bGpuIsMultiGpuBoard = NV_FALSE; - NvBool bIsGemini = NV_FALSE; NvU32 gpuBR04Count = 0; NvU8 BR03Bus = 0xFF; NvU8 BR04Bus = 0xFF; @@ -2332,7 +2393,7 @@ &vendorIDUp, &deviceIDUp, &downstreamPortBus1); - bGpuIsMultiGpuBoard = gpuIsMultiGpuBoard(pGpu, &bIsGemini); + bGpuIsMultiGpuBoard = gpuIsMultiGpuBoard(pGpu); // Traverse the pci tree while (handleUp) @@ -2373,7 +2434,7 @@ PLXBus = busUp; } - // Do not count the BR04A03, PLX, and the bridges behind the dagwoods. + // Do not count the BR04A03, PLX, and the bridges behind the multi-GPU boards. if ((BR04Rev != 0x3) && (PLXBus == 0xFF) && ((gpuBrCount != 1) || (bGpuIsMultiGpuBoard == NV_FALSE))) { gpuBrNot3rdPartyCount++; @@ -2386,7 +2447,7 @@ &funcUp, &vendorIDUp, &deviceIDUp); } - if (bIsGemini && gpuBR04Count) + if (bGpuIsMultiGpuBoard && gpuBR04Count) { // Ignore one BR04 in case of Gemini gpuBR04Count--; @@ -2404,7 +2465,6 @@ *pBRNot3rdParty = brNot3rdParty; *pNoOnboardBR04 = bNoOnboardBR04 ; *pNoUnsupportedBRFound = bNoUnsupportedBRFound; - *pPLXBus = PLXBus; return ; } @@ -2491,7 +2551,7 @@ } } - if (vendorID == PCI_INVALID_VENDORID) + if (!PCI_IS_VENDORID_VALID(vendorID)) { break; // skip to the next device } @@ -3473,76 +3533,25 @@ return NV_OK; } -/** - * Compares two OBJGPUs to see if they are behind the same upstream bridge. - * Used for identifying GPUs behind the same lowest level BR04. - * - * @param[in] pGpu1 First gpu to compare - * @param[in] pGpu2 Second gpu to compare - * - * @return NV_TRUE if the two GPUs are behind the same bridge. - */ -NvBool -clAreGpusBehindSameBridge_IMPL -( - OBJCL *pCl, - OBJGPU *pGpu1, - OBJGPU *pGpu2 -) -{ - NV_ASSERT((pGpu1 != NULL) && - (pGpu2 != NULL)); - - if ((pGpu1->gpuClData.boardUpstreamPort.addr.valid) && - (pGpu2->gpuClData.boardUpstreamPort.addr.valid) && - (pGpu1->gpuClData.boardUpstreamPort.addr.domain - == pGpu2->gpuClData.boardUpstreamPort.addr.domain) && - (pGpu1->gpuClData.boardUpstreamPort.addr.bus - == pGpu2->gpuClData.boardUpstreamPort.addr.bus) && - (pGpu1->gpuClData.boardUpstreamPort.addr.device - == pGpu2->gpuClData.boardUpstreamPort.addr.device) && - (pGpu1->gpuClData.boardUpstreamPort.addr.func - == pGpu2->gpuClData.boardUpstreamPort.addr.func)) - { - return NV_TRUE; - } - - return NV_FALSE; -} - /*! * Pulls the devid info out of the pGpu to pass to gpuDevIdIsMultiGpuBoard(). * * @param[in] pGpu OBJGPU pointer - * @parma[out] pbIsGemini NvBool pointer in which to store whether GPU is a - * Gemini multiboard config. May be NULL if caller does - * not care to receive this information. * * @return NV_TRUE if the GPU is in a multigpu board, NV_FALSE otherwise */ NvBool gpuIsMultiGpuBoard ( - OBJGPU *pGpu, - NvBool *pbIsGemini + OBJGPU *pGpu ) { - if (pbIsGemini != NULL) - *pbIsGemini = NV_FALSE; - - if ((DRF_VAL(_PCI, _DEVID, _DEVICE, pGpu->idInfo.PCIDeviceID) == NV_PCI_DEVID_DEVICE_PG171_SKU200_PG179_SKU220) && - (DRF_VAL(_PCI, _SUBID, _DEVICE, pGpu->idInfo.PCISubDeviceID) == NV_PCI_SUBID_DEVICE_PG171_SKU200) && - (DRF_VAL(_PCI, _SUBID, _VENDOR, pGpu->idInfo.PCISubDeviceID) == NV_PCI_SUBID_VENDOR_NVIDIA)) - { - if (pbIsGemini != NULL) - *pbIsGemini = NV_TRUE; - - return NV_TRUE; - } - - return NV_FALSE; - + return pGpu->getProperty(pGpu, PDB_PROP_GPU_IS_PLX_PRESENT) || + gpuDevIdIsMultiGpuBoard( + (NvU16) DRF_VAL(_PCI, _DEVID, _DEVICE, pGpu->idInfo.PCIDeviceID), + (NvU16) DRF_VAL(_PCI, _SUBID, _VENDOR, pGpu->idInfo.PCISubDeviceID), + (NvU16) DRF_VAL(_PCI, _SUBID, _DEVICE, pGpu->idInfo.PCISubDeviceID)); } /* @@ -4520,6 +4529,37 @@ } /*! + * @brief: Returns the support for CPM of the root node + */ +NvU32 +clGetChipsetL1ClockPMSupport_IMPL +( + OBJGPU *pGpu, + OBJCL *pCl +) +{ + void *handle; + NvU32 PCIECapPtr; + NvU32 linkCaps; + NvU32 clockPmSupport; + + handle = pGpu->gpuClData.rootPort.addr.handle; + if (handle == NULL) + { + return 0; + } + + PCIECapPtr = pGpu->gpuClData.rootPort.PCIECapPtr; + + linkCaps = osPciReadDword(handle, CL_PCIE_LINK_CAP - CL_PCIE_BEGIN + PCIECapPtr); + + // Read field 18:18 to get clock PM support + clockPmSupport = (linkCaps & CL_PCIE_LINK_CAP_CLOCK_PM_BIT); + + return clockPmSupport; +} + +/*! * @brief: Returns the value of link_capabilities_2 of the downstream port * * @param[i] pGpu GPU object pointer @@ -4660,7 +4700,7 @@ { tempDword = osPciReadDword(deviceHandle, capOffset + capSize + PCI_ENHANCED_ALLOCATION_ENTRY_HEADER); tempDword = REF_VAL(PCI_ENHANCED_ALLOCATION_ENTRY_HEADER_ENTRY_SIZE, tempDword); - capSize += (NvU16)((tempDword + 1) * NV_SIZEOF32(NvU32)); + capSize += (NvU16)((tempDword + 1) * sizeof(NvU32)); } } break; @@ -4918,7 +4958,7 @@ return 0; } // clear the capability map. - portMemSet(pCapMap, 0, NV_SIZEOF32(*pCapMap)); + portMemSet(pCapMap, 0, sizeof(*pCapMap)); // if there is not a valid device handle, we are done. if (pDeviceHandle == NULL) @@ -5039,14 +5079,14 @@ } // do all the full dword reads - for (; (blockSz - dataSz) >= sizeof(NvU32); dataSz += NV_SIZEOF32(NvU32)) + for (; (blockSz - dataSz) >= sizeof(NvU32); dataSz += sizeof(NvU32)) { // read a dword of data *((NvU32*)pBuffer) = osPciReadDword(pDeviceHandle, offset); // update the references to the next data to be read/written. - pBuffer += NV_SIZEOF32(NvU32); - offset += NV_SIZEOF32(NvU32); + pBuffer += sizeof(NvU32); + offset += sizeof(NvU32); } // we are at the nearest dword boundary to the end of the block. @@ -5101,8 +5141,8 @@ // do some parameter checks if ((pBuffer == NULL) - || ((blkOffset + NV_SIZEOF32(*pBlkHeader) + blkSize) > PCI_EXTENDED_CONFIG_SPACE_LENGTH) - || ((NV_SIZEOF32(*pBlkHeader) + blkSize) > size)) + || ((blkOffset + sizeof(*pBlkHeader) + blkSize) > PCI_EXTENDED_CONFIG_SPACE_LENGTH) + || ((sizeof(*pBlkHeader) + blkSize) > size)) { return 0; } @@ -5111,7 +5151,7 @@ // copy the block header & update the size pBlkHeader = (CL_PCIE_DC_DIAGNOSTIC_COLLECTION_ENTRY*)pBuffer; *pBlkHeader = *pScriptEntry; - collectedDataSize += NV_SIZEOF32(*pBlkHeader); + collectedDataSize += sizeof(*pBlkHeader); } if((pDeviceHandle != NULL) && (0 < blkSize) @@ -5162,7 +5202,7 @@ { return 0; } - portMemSet(pPCIeHandles, 0, NV_SIZEOF32(pPCIeHandles)); + portMemSet(pPCIeHandles, 0, sizeof(pPCIeHandles)); // get PCIE Handles. pUpstreamPort = &pGpu->gpuClData.upstreamPort.addr; @@ -5185,7 +5225,7 @@ { blkHeader = pScript[idx]; // verify there is space, & we can access the device. - if ((size - collectedDataSize) < (NV_SIZEOF32(blkHeader) + blkHeader.length)) + if ((size - collectedDataSize) < (sizeof(blkHeader) + blkHeader.length)) { // if this block doesn't fit, skip it but continue because another block might. continue; @@ -5343,6 +5383,6 @@ }; return _clPcieGetDiagnosticData(pGpu, - gpuLostCollectionScript, NV_ARRAY_ELEMENTS32(gpuLostCollectionScript), + gpuLostCollectionScript, NV_ARRAY_ELEMENTS(gpuLostCollectionScript), pBuffer, size); } diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/kernel/platform/chipset/pci_pbi.c nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/kernel/platform/chipset/pci_pbi.c --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/kernel/platform/chipset/pci_pbi.c 2023-10-25 20:21:28.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/kernel/platform/chipset/pci_pbi.c 2024-03-05 22:14:00.000000000 +0000 @@ -60,9 +60,9 @@ // Check to see if Post-box interface is found in PCI config space at the // specified base address // -// If the PBI capability was found in the PCI cap list then cap_base is the +// If the PBI capability was found in the PCI cap list then cap_base is the // PCI config offset of the capability. -// If the capability was not found in the PCI cap list then cap_base is zero, but +// If the capability was not found in the PCI cap list then cap_base is zero, but // we still check for PBI at a static location to support certain GPUs in the field. // static NV_STATUS pciPbiCheck(void *handle, NvU32 cap_base) @@ -76,7 +76,7 @@ } // -// Find the base of the PCI PBI capability and return the base. +// Find the base of the PCI PBI capability and return the base. // Returns 0 if PBI is not found in the PCI cap list. // static NvU32 pciPbiFindCapability(void *handle) @@ -87,7 +87,7 @@ // Walk the PCI capability list looking for a match for PBI while (cap_base != 0 && pciPbiCheck(handle, cap_base) != NV_OK) cap_base = osPciReadByte(handle, cap_base + 1); - + return cap_base; } @@ -183,7 +183,7 @@ { poll_limit = PCI_PBI_POLL_STATIC; - // WAR for 2844918, extra delay is needed for early Ampere GA100 devices + // WAR for 2844918, extra delay is needed for early Ampere GA100 devices // which do not have PBI correctly linked in the PCI Capability list devid = osPciReadWord(handle, 0x2); for (i = 0; ampere_devid[i] != 0; i++) diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/kernel/platform/cpu.c nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/kernel/platform/cpu.c --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/kernel/platform/cpu.c 2023-10-25 20:21:28.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/kernel/platform/cpu.c 2024-03-05 22:14:00.000000000 +0000 @@ -172,6 +172,7 @@ case AARCH64_VENDOR_PART(MARVELL, THUNDER_X2): case AARCH64_VENDOR_PART(HUAWEI, KUNPENG_920): case AARCH64_VENDOR_PART(ARM, BLUEFIELD): + case AARCH64_VENDOR_PART(ARM, BLUEFIELD3): // The Neoverse N1 is the same as Gravitron case AARCH64_VENDOR_PART(ARM, GRAVITRON2): case AARCH64_VENDOR_PART(FUJITSU, A64FX): @@ -184,6 +185,8 @@ pSys->cpuInfo.type = NV0000_CTRL_SYSTEM_CPU_TYPE_ARMV8A_GENERIC; break; case AARCH64_VENDOR_PART(ARM, NEOVERSE_N2): + case AARCH64_VENDOR_PART(ARM, NEOVERSE_V2): + case AARCH64_VENDOR_PART(AMPERE_2, AMPEREONE): pSys->cpuInfo.type = NV0000_CTRL_SYSTEM_CPU_TYPE_ARMV9A_GENERIC; break; default: diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/kernel/platform/cpu_arm_def.h nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/kernel/platform/cpu_arm_def.h --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/kernel/platform/cpu_arm_def.h 2023-10-25 20:21:28.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/kernel/platform/cpu_arm_def.h 2024-03-05 22:14:00.000000000 +0000 @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 2000-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2000-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -57,6 +57,7 @@ #define CP_MIDR_IMPLEMENTER_FUJITSU 0x46 #define CP_MIDR_IMPLEMENTER_PHYTIUM 0x70 #define CP_MIDR_IMPLEMENTER_AMPERE 0x81 +#define CP_MIDR_IMPLEMENTER_AMPERE_2 0XC0 #define CP_CSSELR_DATA_CACHE 0 #define CP_CSSELR_INSTRUCTION_CACHE 1 @@ -78,9 +79,11 @@ #define CP_MIDR_PRIMARY_PART_NUM_XGENE 0x0 #define CP_MIDR_PRIMARY_PART_NUM_CORTEX_A57 0xd07 #define CP_MIDR_PRIMARY_PART_NUM_CORTEX_A76 0xd0b +#define CP_MIDR_PRIMARY_PART_NUM_NEOVERSE_V2 0xd4f #define CP_MIDR_PRIMARY_PART_NUM_THUNDER_X2 0x0af #define CP_MIDR_PRIMARY_PART_NUM_KUNPENG_920 0xd01 #define CP_MIDR_PRIMARY_PART_NUM_BLUEFIELD 0xd08 +#define CP_MIDR_PRIMARY_PART_NUM_BLUEFIELD3 0xd42 #define CP_MIDR_PRIMARY_PART_NUM_GRAVITRON2 0xd0c #define CP_MIDR_PRIMARY_PART_NUM_A64FX 0x001 #define CP_MIDR_PRIMARY_PART_NUM_FT2000 0x662 @@ -89,6 +92,7 @@ #define CP_MIDR_PRIMARY_PART_NUM_OCTEON_CN96XX 0x0b2 #define CP_MIDR_PRIMARY_PART_NUM_OCTEON_CN98XX 0x0b1 #define CP_MIDR_PRIMARY_PART_NUM_NEOVERSE_N2 0xd49 +#define CP_MIDR_PRIMARY_PART_NUM_AMPEREONE 0xac3 // Cache Size Identification Register #define CP_CCSIDR "ccsidr_el1" diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/kernel/platform/hwbc.c nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/kernel/platform/hwbc.c --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/kernel/platform/hwbc.c 2023-10-25 20:21:28.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/kernel/platform/hwbc.c 2024-03-05 22:14:00.000000000 +0000 @@ -160,7 +160,7 @@ static RmPhysAddr Plx_Pex8747_GetBar0(OBJCL *pCl, OBJHWBC *pPlx); // -// static functions +// static functions // static OBJHWBC *objClFindUpperHWBC(OBJCL *, NBADDR, OBJHWBC *, RmPhysAddr); @@ -744,7 +744,7 @@ needRes[dev+1] = 1; total++; } else - if (!handle || vendorID == PCI_INVALID_VENDORID) + if (!handle || !PCI_IS_VENDORID_VALID(vendorID)) totalDevices--; } diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/kernel/platform/nbsi/nbsi_init.c nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/kernel/platform/nbsi/nbsi_init.c --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/kernel/platform/nbsi/nbsi_init.c 2023-10-25 20:21:28.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/kernel/platform/nbsi/nbsi_init.c 2024-03-05 22:14:01.000000000 +0000 @@ -728,7 +728,7 @@ } //---------------------------------------------------------------------------- -// NV_STATUS extractNBSIObjFromDir(pGpu, idx, +// NV_STATUS extractNBSIObjFromDir(pGpu, idx, // pNbsiDir, nbsiDirSize, tableLoc, // wantedGlobType, wantedGlobIndex, // * pActualGlobIdx, @@ -1159,7 +1159,7 @@ } //---------------------------------------------------------------------------- -// NV_STATUS getNbsiCacheInfoForGlobType(pGpu, idx, +// NV_STATUS getNbsiCacheInfoForGlobType(pGpu, idx, // globType, // *pWantedGlobSource, *pWantedGlobIndex, // *pNbsiDir, *pNbsiDirSize, *pCurTbl) @@ -1384,7 +1384,7 @@ //---------------------------------------------------------------------------- -// NV_STATUS getNbsiDirFromRegistry(pGpu, idx, +// NV_STATUS getNbsiDirFromRegistry(pGpu, idx, // pNbsiDir, pNbsiDirSize) // // This function determines if an emulated NBSI table exists in the registry @@ -1544,7 +1544,7 @@ } //---------------------------------------------------------------------------- -// NV_STATUS getNbsiDirectory(pGpu, idx, +// NV_STATUS getNbsiDirectory(pGpu, idx, // searchDir, *pNbsiDir, *pNbsiDirSize, // curSource, // *pbFreeDirMemRequired, @@ -1681,11 +1681,11 @@ *(NvU32 *) inOutData = (globTypeWanted & 0xffff) << 16 | (curGlob & 0xf) << 12 | ((*sizeToRead/inOutDataSz) & 0xfff); - status = pGpu->pOS->osCallACPI_DSM(pGpu, - acpiFunction, - NV_ACPI_GENERIC_FUNC_GETOBJBYTYPE, - (NvU32 *)inOutData, - (NvU16 *)&acpiRtnSize); + status = osCallACPI_DSM(pGpu, + acpiFunction, + NV_ACPI_GENERIC_FUNC_GETOBJBYTYPE, + (NvU32 *)inOutData, + (NvU16 *)&acpiRtnSize); if ((acpiRtnSize == 0) || ((status == NV_OK) && @@ -2175,11 +2175,11 @@ { // get page the data is in. *(NvU32 *) inOutData = curOffset / inOutDataSz; - status = pGpu->pOS->osCallACPI_DSM(pGpu, - acpiFunction, - NV_ACPI_GENERIC_FUNC_GETALLOBJS, - (NvU32 *)inOutData, - (NvU16 *)&rtnSize); + status = osCallACPI_DSM(pGpu, + acpiFunction, + NV_ACPI_GENERIC_FUNC_GETALLOBJS, + (NvU32 *)inOutData, + (NvU16 *)&rtnSize); if ((acpiRtnSize == 0) || ((status == NV_OK) && (acpiRtnSize==4) && @@ -2575,7 +2575,7 @@ } //---------------------------------------------------------------------------- -// NV_STATUS _extractNBSIObjFromACPIDir(pGpu, idx, +// NV_STATUS _extractNBSIObjFromACPIDir(pGpu, idx, // curDir, // acpiFunction, validationOption, acpiMethod, // wantedGlobType, wantedGlobIdx, @@ -2853,11 +2853,11 @@ // (IN/OUT) pSizeOfData In = size of inoutdata, Out = size returned // rtnSize = (NvU16) (*pRtnObjSize & 0xffff); - status = pGpu->pOS->osCallACPI_DSM(pGpu, - acpiFunction, - wantedRtnObjOffset, - (NvU32 *)pRtnObj, - (NvU16 *)&rtnSize); + status = osCallACPI_DSM(pGpu, + acpiFunction, + wantedRtnObjOffset, + (NvU32 *)pRtnObj, + (NvU16 *)&rtnSize); *pRtnObjSize = rtnSize; *pWantedGlobSource = (NBSI_SOURCE_LOC) status; diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/kernel/platform/nbsi/nbsi_osrg.c nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/kernel/platform/nbsi/nbsi_osrg.c --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/kernel/platform/nbsi/nbsi_osrg.c 2023-10-25 20:21:29.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/kernel/platform/nbsi/nbsi_osrg.c 2024-03-05 22:14:01.000000000 +0000 @@ -137,7 +137,7 @@ if (errorCode == NV2080_CTRL_BIOS_GET_NBSI_SUCCESS) { *pData = nbsiDword; - } + } else { // diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/kernel/platform/p2p/p2p_caps.c nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/kernel/platform/p2p/p2p_caps.c --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/kernel/platform/p2p/p2p_caps.c 2023-10-25 20:21:29.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/kernel/platform/p2p/p2p_caps.c 2024-03-05 22:14:01.000000000 +0000 @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 1993-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 1993-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -21,6 +21,9 @@ * DEALINGS IN THE SOFTWARE. */ +// FIXME XXX +#define NVOC_KERNEL_NVLINK_H_PRIVATE_ACCESS_ALLOWED + #include "core/system.h" #include "gpu_mgr/gpu_mgr.h" #include "kernel/gpu/mig_mgr/kernel_mig_manager.h" @@ -28,6 +31,7 @@ #include "kernel/gpu/bif/kernel_bif.h" #include "gpu/subdevice/subdevice.h" #include "gpu/gpu.h" +#include "virtualization/hypervisor/hypervisor.h" #include "vgpu/rpc.h" #include "vgpu/vgpu_events.h" #include "platform/chipset/chipset.h" @@ -345,6 +349,7 @@ NvU8 gpuP2PWriteCapsStatus = NV0000_P2P_CAPS_STATUS_OK; NvU32 lockedGpuMask = 0; NV_STATUS status = NV_OK; + OBJHYPERVISOR *pHypervisor = SYS_GET_HYPERVISOR(pSys); // Check if any overrides are enabled. if (_kp2pCapsCheckStatusOverridesForPcie(gpuMask, pP2PWriteCapStatus, @@ -362,6 +367,16 @@ } } + // Check for hypervisor oriented PCIe P2P overrides + if (pHypervisor && + pHypervisor->bDetected && + hypervisorPcieP2pDetection(pHypervisor, gpuMask)) + { + *pP2PReadCapStatus = NV0000_P2P_CAPS_STATUS_OK; + *pP2PWriteCapStatus = NV0000_P2P_CAPS_STATUS_OK; + goto done; + } + // PCI-E topology checks gpuInstance = 0; while ((pGpu = gpumgrGetNextGpu(gpuMask, &gpuInstance)) != NULL) @@ -706,7 +721,7 @@ // If any of the GPU has MIG enabled, return with no P2P support if (!bSmcNvLinkP2PSupported) { - NV_PRINTF(LEVEL_ERROR, + NV_PRINTF(LEVEL_NOTICE, "P2P is marked unsupported with MIG for GPU instance = 0x%x\n", gpuInstance); return NV_OK; @@ -836,7 +851,7 @@ return NV_ERR_NOT_SUPPORTED; NV_CHECK_OR_RETURN(LEVEL_ERROR, - pParams->peerGpuCount <= NV_ARRAY_ELEMENTS32(pGpu->P2PPeerGpuCaps), + pParams->peerGpuCount <= NV_ARRAY_ELEMENTS(pGpu->P2PPeerGpuCaps), NV_ERR_INVALID_ARGUMENT); for (i = 0; i < pParams->peerGpuCount; i++) @@ -851,7 +866,7 @@ if (pLocalPeerCaps == NULL) { NV_CHECK_OR_ELSE(LEVEL_ERROR, - pGpu->P2PPeerGpuCount < NV_ARRAY_ELEMENTS32(pGpu->P2PPeerGpuCaps), + pGpu->P2PPeerGpuCount < NV_ARRAY_ELEMENTS(pGpu->P2PPeerGpuCaps), status = NV_ERR_INSUFFICIENT_RESOURCES; goto fail); pLocalPeerCaps = &pGpu->P2PPeerGpuCaps[pGpu->P2PPeerGpuCount]; @@ -905,7 +920,7 @@ return NV_ERR_NOT_SUPPORTED; NV_CHECK_OR_RETURN(LEVEL_ERROR, - pParams->peerGpuIdCount <= NV_ARRAY_ELEMENTS32(pGpu->P2PPeerGpuCaps), + pParams->peerGpuIdCount <= NV_ARRAY_ELEMENTS(pGpu->P2PPeerGpuCaps), NV_ERR_INVALID_ARGUMENT); for (i = 0; i < pParams->peerGpuIdCount; i++) @@ -943,7 +958,7 @@ for (i = 0; i < pShimParams->peerGpuCount; i++) { NV2080_CTRL_GPU_P2P_PEER_CAPS_PEER_INFO *pParamsPeerInfo = &pShimParams->peerGpuCaps[i]; - POBJGPU pRemoteGpu = gpumgrGetGpuFromId(pParamsPeerInfo->gpuId); + OBJGPU *pRemoteGpu = gpumgrGetGpuFromId(pParamsPeerInfo->gpuId); NV_CHECK_OR_ELSE(LEVEL_INFO, pRemoteGpu != NULL, status = NV_ERR_INVALID_ARGUMENT; goto done); @@ -1028,7 +1043,7 @@ NV_CHECK_OR_RETURN(LEVEL_ERROR, (pParams->bAllCaps || - (pParams->peerGpuCount <= NV_ARRAY_ELEMENTS32(pGpu->P2PPeerGpuCaps))), + (pParams->peerGpuCount <= NV_ARRAY_ELEMENTS(pGpu->P2PPeerGpuCaps))), NV_ERR_INVALID_ARGUMENT); NV_CHECK_OR_RETURN(LEVEL_ERROR, (pParams->bUseUuid == NV_FALSE), NV_ERR_NOT_SUPPORTED); diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/kernel/platform/platform_request_handler.c nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/kernel/platform/platform_request_handler.c --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/kernel/platform/platform_request_handler.c 1970-01-01 00:00:00.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/kernel/platform/platform_request_handler.c 2024-03-05 22:14:01.000000000 +0000 @@ -0,0 +1,1031 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2015-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +/* ------------------------ Includes --------------------------------------- */ +#include "nvRmReg.h" +#include "objtmr.h" +#include "platform/platform_request_handler.h" +#include "core/locks.h" +#include "diagnostics/tracer.h" +#include "gps.h" +#include "platform/platform.h" +#include "rmapi/client_resource.h" + +/* ------------------------ Datatypes -------------------------------------- */ +/* ------------------------ Macros ----------------------------------------- */ +/* ------------------------ Defines ---------------------------------------- */ +/* ---------------------- Static Function Prototypes ----------------------- */ +static NV_STATUS _pfmreqhndlrSupportExists (PlatformRequestHandler *pPlatformRequestHandler, OBJGPU *pGpu); +static NvBool _pfmreqhndlrCheckAndGetPM1ForcedOffState(PlatformRequestHandler *pPlatformRequestHandler, OBJGPU *pGpu); +static GpuPrereqCallback _pfmreqhndlrPmgrPmuPostLoadPrereqCallback; +static GpuPrereqCallback _pfmreqhndlrThermPmuPostInitPrereqCallback; + +/* ---------------------- Extern Function Prototypes ----------------------- */ +extern NV_STATUS pfmreqhndlrCallback(OBJGPU *pGpu, OBJTMR *pTmr, void *pVoid); + +/* ------------------------ Public Functions ------------------------------ */ + +// Constructor +NV_STATUS +pfmreqhndlrConstruct_IMPL +( + PlatformRequestHandler *pPlatformRequestHandler +) +{ + NV_PRINTF(LEVEL_INFO, "\n"); + return NV_OK; +} + +/*! + * @brief Stores the index of first GPU which supports PLATFORM_REQUEST_HANDLER + * + * @param[in] pPlatformRequestHandler *PlatformRequestHandler pointer + * + * @return NV_OK always succeeds + */ +NV_STATUS +pfmreqhndlrInitGpu +( + PlatformRequestHandler *pPlatformRequestHandler +) +{ + pPlatformRequestHandler->dsmVersion = ACPI_DSM_FUNCTION_INVALID; + + OBJGPU *pGpu = NULL; + NvU32 gpuIndex = 0; + NV_STATUS status = NV_ERR_NOT_SUPPORTED; + NvU32 gpuCount; + NvU32 gpuMask; + + // Initialize index to default (invalid) value. + pPlatformRequestHandler->pfmreqhndlrSupportedGpuIdx = PFM_REQ_HNDLR_MAX_GPU_SUPPORTED; + gpumgrGetGpuAttachInfo(&gpuCount, &gpuMask); + + // Invalid GPU configuration + if (gpuCount < 1 || gpuCount > PFM_REQ_HNDLR_MAX_GPU_SUPPORTED) + { + NV_PRINTF(LEVEL_ERROR, "PLATFORM_REQUEST_HANDLER: Cannot support %u GPUs yet\n", gpuCount); + } + else + { + while (((pGpu = gpumgrGetNextGpu(gpuMask, &gpuIndex)) != NULL) && + (pGpu->pPrereqTracker != NULL)) + { + // get pfmreqhndlr support option. + if(testIfDsmSubFunctionEnabled(pGpu, ACPI_DSM_FUNCTION_GPS_2X, GPS_FUNC_SUPPORT) == NV_OK) + { + pPlatformRequestHandler->dsmVersion = ACPI_DSM_FUNCTION_GPS_2X; + status = NV_OK; + } + else if(testIfDsmSubFunctionEnabled(pGpu, ACPI_DSM_FUNCTION_GPS, GPS_FUNC_SUPPORT) == NV_OK) + { + pPlatformRequestHandler->dsmVersion = ACPI_DSM_FUNCTION_GPS; + status = NV_OK; + } + + if (status == NV_OK) + { + // + // Store the GPU index of the current GPU. + // gpumgrGetNextGpu() increments gpuIndex to point to the next + // GPU, so need to subtract 1 to get the current GPU index. + // + pPlatformRequestHandler->pfmreqhndlrSupportedGpuIdx = gpuIndex - 1; + break; + } + } + } + + return NV_OK; +} + +/*! + * @brief Returns the GPU which supports PLATFORM_REQUEST_HANDLER + * + * @param[in] pPlatformRequestHandler *PlatformRequestHandler pointer + * + * @return pGpu if at least one GPU supports ACPI_DSM_FUNCTION_PFM_REQ_HNDLR + * @return NULL if no GPU supports ACPI_DSM_FUNCTION_PFM_REQ_HNDLR + */ +POBJGPU +pfmreqhndlrGetGpu +( + PlatformRequestHandler *pPlatformRequestHandler +) +{ + OBJGPU *pGpu = NULL; + NvU32 gpuIndex; + NvU32 gpuCount; + NvU32 gpuMask; + + gpumgrGetGpuAttachInfo(&gpuCount, &gpuMask); + + // gpumgrGetNextGpu() increments the index, so pass a copy to it. + gpuIndex = pPlatformRequestHandler->pfmreqhndlrSupportedGpuIdx; + + if (gpuIndex < PFM_REQ_HNDLR_MAX_GPU_SUPPORTED) + { + pGpu = gpumgrGetNextGpu(gpuMask, &gpuIndex); + } + + return pGpu; +} + +/*! + * Acquire/release all locks/semaphores before executing passive mode code. + * + * @param[in] bEnter specify if this call was invoked prior (NV_TRUE) or + * after (NV_FALSE) executing passive mode code + * @param[in] APILockFlag flag for the RM API lock + * @param[in] GPULockFlag flag for RM GPU lock + * + * @return NV_ERR_INVALID_OBJECT failed to look-up system object + * @return propagates an error code of other interfaces called within + */ +NV_STATUS +pfmreqhndlrPassiveModeTransition +( + NvBool bEnter, + NvU32 apiLockFlag, + NvU32 gpuLockFlag +) +{ + OBJSYS *pSys = SYS_GET_INSTANCE(); + NvBool bReleaseRmSema = NV_FALSE; + NvBool bReleaseApiLock = NV_FALSE; + NvBool bReleaseGpuLock = NV_FALSE; + NV_STATUS status = NV_OK; + + NV_ASSERT_OR_RETURN(pSys != NULL, NV_ERR_INVALID_OBJECT); + + if (bEnter) + { + if (status == NV_OK) + { + status = osCondAcquireRmSema(pSys->pSema); + + if (status != NV_OK) + { + NV_PRINTF(LEVEL_ERROR, "Error acquiring semaphore!\n"); + DBG_BREAKPOINT(); + } + } + + if (status == NV_OK) + { + status = rmapiLockAcquire(apiLockFlag, RM_LOCK_MODULES_PFM_REQ_HNDLR); + + if (status != NV_OK) + { + bReleaseRmSema = NV_TRUE; + + NV_PRINTF(LEVEL_ERROR, "Error acquiring API lock!\n"); + DBG_BREAKPOINT(); + } + } + + if (status == NV_OK) + { + status = rmGpuLocksAcquire(gpuLockFlag, RM_LOCK_MODULES_PFM_REQ_HNDLR); + + if (status != NV_OK) + { + bReleaseApiLock = NV_TRUE; + bReleaseRmSema = NV_TRUE; + + NV_PRINTF(LEVEL_ERROR, "Error acquiring GPUs lock!\n"); + DBG_BREAKPOINT(); + } + } + } + else + { + bReleaseRmSema = NV_TRUE; + bReleaseApiLock = NV_TRUE; + bReleaseGpuLock = NV_TRUE; + } + + if (bReleaseGpuLock) + { + rmGpuLocksRelease(gpuLockFlag, NULL); + } + + if (bReleaseApiLock) + { + rmapiLockRelease(); + } + + if (bReleaseRmSema) + { + osReleaseRmSema(pSys->pSema, NULL); + } + + return status; +} + +/*! + * @brief Handle PFM_REQ_HNDLR_EVENT_STATUS_CHANGE event. + * + * This function is called for PlatformRequestHandler when SBIOS triggers + * PFM_REQ_HNDLR_EVENT_STATUS_CHANGE event and also when v-Pstate change heppen in RM + * to update it to SBIOS. This control call will send ACK back to SBIOS if + * get a call from SBIOS and do further processing required. + * + * @param[in] pPlatformRequestHandler *PlatformRequestHandler object pointer + * @param[in] input Data used to send in Pcontrol ACPI call + * @param[in] bSbiosCall True if we get a call from SBIOS, false if get + * call to update SBIOS about new v-Pstate + * + * @return 'NV_OK' + * If the command successfully completes. + * @return 'NV_ERR_NOT_SUPPORTED' + * If invalid type of command is requested. + */ +NV_STATUS +pfmreqhndlrPcontrol_IMPL(PlatformRequestHandler *pPlatformRequestHandler, NvU32 input, NvBool bSbiosCall) +{ + OBJGPU *pGpu = NULL; + PFM_REQ_HNDLR_SENSOR_DATA *pPfmreqhndlrData = NULL; + NvU32 indexPstate = 0; // Pstate index received by SBIOS + NvU32 maxVPstate = 0; // Max v-Pstate corresponding to Pstate index + NvU32 inputData = 0; // Input data sent to SBIOS + NvU32 vpStateMapping = 0; // v-Pstate mapping corresponding Pstate index + NvU32 responseData = 0; // Responce data received from SBIOS + NvU32 requestData = 0; // Request data send to SBIOS + NV_STATUS status = NV_OK; + RM_API *pRmApi = NULL; + NvBool bDone = NV_FALSE; + + if (NULL == pPlatformRequestHandler) + { + NV_PRINTF(LEVEL_ERROR, "PlatformRequestHandler pointer is NULL\n"); + DBG_BREAKPOINT(); + return NV_ERR_NOT_SUPPORTED; + } + + pGpu = pfmreqhndlrGetGpu(pPlatformRequestHandler); + if (NULL == pGpu) + { + NV_PRINTF(LEVEL_ERROR, "Gpu pointer is NULL\n"); + DBG_BREAKPOINT(); + return NV_ERR_NOT_SUPPORTED; + } + pPfmreqhndlrData = &(pPlatformRequestHandler->sensorData); + pRmApi = GPU_GET_PHYSICAL_RMAPI(pGpu); + // + // Setup the initial PFM_REQ_HNDLR_FUNC_PCONTROL call + // + + //Updating input data before sending request for Pcontrol call + inputData = FLD_SET_DRF_NUM (_PB, _PFM_REQ_HNDLR_PCTRL, _RES, NV_PB_PFM_REQ_HNDLR_PCTRL_RES_CHANGE_EVENT, inputData); + // Setting reserved bit equal to zero + inputData = FLD_SET_DRF_NUM (_PB, _PFM_REQ_HNDLR_PCTRL, _RESERVED, NV_PB_PFM_REQ_HNDLR_PCTRL_RESERVED_BITS, inputData); + // Last received v-Pstate limit in input data designated by bits [15:8]. + inputData = FLD_SET_DRF_NUM (_PB, _PFM_REQ_HNDLR_PCTRL, _LAST_VPSTATE_LIMIT, pPfmreqhndlrData->PFMREQHNDLRACPIData.prevSbiosVPStateLimit, inputData); + // Send slowest externally available v-Pstate number in [23:16] of input data. + // NOTE: Notion of a "Slow" vpstate is not applicable in PSTATES 3.0+, this usage is broken for non pstates 2.x environments. + inputData = FLD_SET_DRF_NUM (_PB, _PFM_REQ_HNDLR_PCTRL, _SLOW_EXT_VPSTATE, pPlatformRequestHandler->vPstateCache.vPstateIdxHighest, inputData); + // Setting fastest available v-Pstate to 0 + inputData = FLD_SET_DRF_NUM (_PB, _PFM_REQ_HNDLR_PCTRL, _FAST_VPSTATE, 0, inputData); + + NV0000_CTRL_PFM_REQ_HNDLR_CALL_ACPI_PARAMS acpiParams = {0}; + acpiParams.ctrl.cmd = NV0000_CTRL_PFM_REQ_HNDLR_CALL_ACPI_CMD_PCONTROL; + acpiParams.ctrl.input = inputData; + acpiParams.output.pBuffer = (NvU8*)&(requestData); + acpiParams.output.bufferSz = sizeof(requestData); + + bDone = NV_FALSE; + + while (!bDone) + { + // make the previously setup PFM_REQ_HNDLR_FUNC_PCONTROL call + status = pfmreqhndlrCallACPI(pGpu, &acpiParams); + + if (NV_OK != status) + { + NV_PRINTF(LEVEL_ERROR, "ACPI call failed. Error : 0x%x\n", status); + DBG_BREAKPOINT(); + + break; + } + requestData = acpiParams.output.result[0]; + + switch(DRF_VAL(_PB, _PFM_REQ_HNDLR_PCTRL, _REQ, requestData)) + { + case NV_PB_PFM_REQ_HNDLR_PCTRL_REQ_NO_ACTION: + { + // No action is needed, exit the function + NV_PRINTF(LEVEL_INFO, + "No action is required in response to SBIOS event PCONTROL\n"); + bDone = NV_TRUE; + + break; + } + case NV_PB_PFM_REQ_HNDLR_PCTRL_REQ_VPSTATE_INFO: + { + // + // Setup a response PFM_REQ_HNDLR_FUNC_PCONTROL call to return the VP-State range + // + NV2080_CTRL_CMD_INTERNAL_PERF_PFM_REQ_HNDLR_GET_VPSTATE_MAPPING_PARAMS params = {0}; + params.pStateIdx = DRF_VAL(_PB, _PFM_REQ_HNDLR_PCTRL, _INDEX_PSTATE, requestData);; + + status = pRmApi->Control(pRmApi, + pGpu->hInternalClient, + pGpu->hInternalSubdevice, + NV2080_CTRL_CMD_INTERNAL_PERF_PFM_REQ_HNDLR_GET_VPSTATE_MAPPING, + ¶ms, + sizeof(params)); + if (status == NV_OK) + { + vpStateMapping = params.vPstateIdxMapping; + } + + + // Send response for v-Pstate information in response type. + responseData = FLD_SET_DRF_NUM (_PB, _PFM_REQ_HNDLR_PCTRL, _RES, NV_PB_PFM_REQ_HNDLR_PCTRL_RES_VPSTATE_INFO, responseData); + // Setting reserved bit equal to zero + responseData = FLD_SET_DRF_NUM (_PB, _PFM_REQ_HNDLR_PCTRL, _RESERVED, NV_PB_PFM_REQ_HNDLR_PCTRL_RESERVED_BITS, responseData); + // Send Pstate index received from previous return value of Pstate index in [15:8] of input data. + responseData = FLD_SET_DRF_NUM (_PB, _PFM_REQ_HNDLR_PCTRL, _INDEX_PSTATE, indexPstate, responseData); + // Send slowest externally available v-Pstate number in [23:16] of input data. + // NOTE: Notion of a "Slow" vpstate is not applicable in PSTATES 3.0+, this usage is broken for non pstates 2.x environments. + responseData = FLD_SET_DRF_NUM (_PB, _PFM_REQ_HNDLR_PCTRL, _SLOW_EXT_VPSTATE, pPlatformRequestHandler->vPstateCache.vPstateIdxHighest, responseData); + // Send v-Pstate mapping for indexPstate in [31:24] of input data. + responseData = FLD_SET_DRF_NUM (_PB, _PFM_REQ_HNDLR_PCTRL, _MAPPING_VPSTATE, vpStateMapping, responseData); + + acpiParams.ctrl.input = responseData; + requestData = 0; + acpiParams.output.pBuffer = (NvU8*)&(requestData); + acpiParams.output.bufferSz = sizeof(requestData); + + // call will actually be made at the top of the while loop in the next pass. + break; + } + case NV_PB_PFM_REQ_HNDLR_PCTRL_REQ_VPSTATE_SET: + { + maxVPstate = DRF_VAL(_PB, _PFM_REQ_HNDLR_PCTRL, _MAX_VPSTATE_LEVEL, requestData); + + NV2080_CTRL_CMD_INTERNAL_PERF_PFM_REQ_HNDLR_SET_VPSTATE_PARAMS params = {0}; + params.vPstateIdx = maxVPstate; + + pRmApi->Control(pRmApi, + pGpu->hInternalClient, + pGpu->hInternalSubdevice, + NV2080_CTRL_CMD_INTERNAL_PERF_PFM_REQ_HNDLR_SET_VPSTATE, + ¶ms, + sizeof(params)); + + // + // Setup a response PFM_REQ_HNDLR_FUNC_PCONTROL call to indicate we have changed the current VP-State + // + + // Send response for v-Pstate information in response type + responseData = FLD_SET_DRF_NUM (_PB, _PFM_REQ_HNDLR_PCTRL, _RES, NV_PB_PFM_REQ_HNDLR_PCTRL_RES_VPSTATE_SET, responseData); + // Setting reserved bit equal to zero + responseData = FLD_SET_DRF_NUM (_PB, _PFM_REQ_HNDLR_PCTRL, _RESERVED, NV_PB_PFM_REQ_HNDLR_PCTRL_RESERVED_BITS, responseData); + // Last received v-Pstate limit in input data designated by bits [15:8]. + responseData = FLD_SET_DRF_NUM (_PB, _PFM_REQ_HNDLR_PCTRL, _LAST_VPSTATE_LIMIT, pPfmreqhndlrData->PFMREQHNDLRACPIData.prevSbiosVPStateLimit, responseData); + // Return slowest of input data designated by bits [23:16]. + // NOTE: Notion of a "Slow" vpstate is not applicable in PSTATES 3.0+, this usage is broken for non pstates 2.x environments. + responseData = FLD_SET_DRF_NUM (_PB, _PFM_REQ_HNDLR_PCTRL, _SLOW_EXT_VPSTATE, pPlatformRequestHandler->vPstateCache.vPstateIdxHighest, responseData); + // Fastest available v-Pstate of input data designated by bits [31:24] which is 0. + responseData = FLD_SET_DRF_NUM (_PB, _PFM_REQ_HNDLR_PCTRL, _FAST_VPSTATE, 0, responseData); + + pPfmreqhndlrData->PFMREQHNDLRACPIData.prevSbiosVPStateLimit + = maxVPstate; + acpiParams.ctrl.input = responseData; + requestData = 0; + acpiParams.output.pBuffer = (NvU8*)&(requestData); + acpiParams.output.bufferSz = sizeof(requestData); + + // call will actually be made at the top of the while loop in the next pass. + break; + } + default: + { + NV_PRINTF(LEVEL_ERROR, + "Received a wrong request type from SBIOS, which is not supported\n"); + status = NV_ERR_NOT_SUPPORTED; + + bDone = NV_TRUE; + + break; + } + } + } + + return status; +} +/* ---------------------- Static Functions --------------------------------- */ + +NvBool +pfmreqhndlrIsInitialized_IMPL +( + PlatformRequestHandler *pPlatformRequestHandler +) +{ + NV_ASSERT(pPlatformRequestHandler); + + return pPlatformRequestHandler->controlData.bStateInitialized; +} + +/*! + * @brief Initializes the PlatformRequestHandler control SW state. + * + * @param[in] pPlatformRequestHandler *PlatformRequestHandler pointer + * + * @return NV_ERR_INVALID_STATE failed to look-up required object pointers + * @return NV_ERR_NOT_SUPPORTED system doesn't support requested PlatformRequestHandler variant + * @return NV_OK PlatformRequestHandler was successfully initialized + */ +NV_STATUS +pfmreqhndlrStateInit_IMPL +( + PlatformRequestHandler *pPlatformRequestHandler +) +{ + NV_STATUS status = NV_ERR_INVALID_STATE; + OBJGPU *pGpu = NULL; + RM_API *pRmApi = NULL; + + if (pPlatformRequestHandler == NULL) + { + NV_PRINTF(LEVEL_ERROR, "PlatformRequestHandler pointer is NULL\n"); + DBG_BREAKPOINT(); + return NV_ERR_NOT_SUPPORTED; + } + + if (pfmreqhndlrIsInitialized(pPlatformRequestHandler)) + { + // Skip if it has been intialized already + status = NV_OK; + goto pfmreqhndlrStateInit_IMPL_exit; + } + + status = pfmreqhndlrInitGpu(pPlatformRequestHandler); + if (status != NV_OK) + { + goto pfmreqhndlrStateInit_IMPL_exit; + } + + // Validate we have everything. + pGpu = pfmreqhndlrGetGpu(pPlatformRequestHandler); + + if (pGpu == NULL) + { + status = NV_ERR_INVALID_STATE; + goto pfmreqhndlrStateInit_IMPL_exit; + } + pRmApi = GPU_GET_PHYSICAL_RMAPI(pGpu); + + // Init state varibles. + pPlatformRequestHandler->controlData.bTGPUOverrideRequired = NV_TRUE; + pPlatformRequestHandler->controlData.bEDPpeakUpdateEnabled = NV_FALSE; + pPlatformRequestHandler->controlData.bUserConfigTGPmodeEnabled = NV_FALSE; + pPlatformRequestHandler->controlData.bPlatformUserConfigTGPmodeEnabled = NV_FALSE; + + // Initialize FRL reporting data + pPlatformRequestHandler->frmData.nextSampleNumber = 0; + + // Check if PlatformRequestHandler is supported through ACPI + if (_pfmreqhndlrSupportExists(pPlatformRequestHandler, pGpu) == NV_OK) + { + NV2080_CTRL_INTERNAL_SMBPBI_PFM_REQ_HNDLR_CAP_UPDATE_PARAMS ctrlParams = { 0 }; + + pPlatformRequestHandler->setProperty(pPlatformRequestHandler, + PDB_PROP_PFMREQHNDLR_SUPPORTED, NV_TRUE); + + ctrlParams.bIsSysCtrlSupported = NV_TRUE; + + status = pRmApi->Control(pRmApi, + pGpu->hInternalClient, + pGpu->hInternalSubdevice, + NV2080_CTRL_CMD_INTERNAL_SMBPBI_PFM_REQ_HNDLR_CAP_UPDATE, + &ctrlParams, + sizeof(ctrlParams)); + if (status == NV_OK) + { + pPlatformRequestHandler->setProperty(pPlatformRequestHandler, + PDB_PROP_PFMREQHNDLR_SYS_CONTROL_SUPPORTED, NV_TRUE); + + pPlatformRequestHandler->setProperty(pPlatformRequestHandler, + PDB_PROP_PFMREQHNDLR_IS_PLATFORM_LEGACY, ctrlParams.bIsPlatformLegacy); + } + } + else + { + status = NV_ERR_NOT_SUPPORTED; + goto pfmreqhndlrStateInit_IMPL_exit; + } + + // Initialize the sensors based on ACPI + pfmreqhndlrInitSensors(pPlatformRequestHandler); + + pPlatformRequestHandler->controlData.bStateInitialized = NV_TRUE; + + // Check and get PM1ForcedOff state + pPlatformRequestHandler->controlData.bPM1ForcedOff = + _pfmreqhndlrCheckAndGetPM1ForcedOffState(pPlatformRequestHandler, pGpu); + + // Cache VPstate PS 20 Support and Highest VPstate Idx + // Set the load sync with PMGR + NV2080_CTRL_CMD_INTERNAL_PERF_PFM_REQ_HNDLR_GET_VPSTATE_INFO_PARAMS params = { 0 }; + + status = pRmApi->Control(pRmApi, + pGpu->hInternalClient, + pGpu->hInternalSubdevice, + NV2080_CTRL_CMD_INTERNAL_PERF_PFM_REQ_HNDLR_GET_VPSTATE_INFO, + ¶ms, + sizeof(params)); + if (status == NV_OK) + { + pPlatformRequestHandler->vPstateCache.bVpsPs20Supported = params.bVpsPs20Supported; + pPlatformRequestHandler->vPstateCache.vPstateIdxHighest = params.vPstateIdxHighest; + } + else + { + // Set the index to invalid incase of error + pPlatformRequestHandler->vPstateCache.bVpsPs20Supported = NV_FALSE; + pPlatformRequestHandler->vPstateCache.vPstateIdxHighest = PFM_REQ_HNDLR_VPSTATE_INDEX_INVALID; + } + + // Set the load sync with PMGR + NV2080_CTRL_INTERNAL_PFM_REQ_HNDLR_STATE_SYNC_PARAMS ctrlParams = { 0 }; + + ctrlParams.flags = NV2080_CTRL_INTERNAL_PFM_REQ_HNDLR_STATE_SYNC_FLAGS_PMGR_LOAD; + + status = pRmApi->Control(pRmApi, + pGpu->hInternalClient, + pGpu->hInternalSubdevice, + NV2080_CTRL_CMD_INTERNAL_PMGR_PFM_REQ_HNDLR_STATE_LOAD_SYNC, + &ctrlParams, + sizeof(ctrlParams)); + if (status != NV_OK) + { + goto pfmreqhndlrStateInit_IMPL_exit; + } + + // 2X only set the init sync with THERM + if (PFM_REQ_HNDLR_IS_ACPI_VERSION_SW_2X(pPlatformRequestHandler)) + { + ctrlParams.flags = NV2080_CTRL_INTERNAL_PFM_REQ_HNDLR_STATE_SYNC_FLAGS_THERM_INIT; + + status = pRmApi->Control(pRmApi, + pGpu->hInternalClient, + pGpu->hInternalSubdevice, + NV2080_CTRL_CMD_INTERNAL_THERM_PFM_REQ_HNDLR_STATE_INIT_SYNC, + &ctrlParams, + sizeof(ctrlParams)); + if (status != NV_OK) + { + goto pfmreqhndlrStateInit_IMPL_exit; + } + } + +pfmreqhndlrStateInit_IMPL_exit: + return status; +} + +/*! + * @brief deallocates PlatformRequestHandler data. + * + * frees up the memory from PlatformRequestHandler global data + * dynamically allocated during init. + * + * @param[in] pPlatformRequestHandler *PlatformRequestHandler object pointer + */ +void +pfmreqhndlrStateDestroy_IMPL +( + PlatformRequestHandler *pPlatformRequestHandler +) +{ + NV_ASSERT(pPlatformRequestHandler); + + pPlatformRequestHandler->controlData.bStateInitialized = NV_FALSE; +} + +NV_STATUS +pfmreqhndlrStateLoad_IMPL +( + PlatformRequestHandler *pPlatformRequestHandler +) +{ + OBJGPU *pGpu = NULL; + NvBool bPM1Available = NV_FALSE; + NvTemp targetTemp = PFM_REQ_HNDLR_TEMP_0_C; + NvU32 data32 = 0; + RM_API *pRmApi = NULL; + NV_STATUS status = NV_OK; + + NV_ASSERT(pPlatformRequestHandler); + + // Validate we have everything. + pGpu = pfmreqhndlrGetGpu(pPlatformRequestHandler); + if (pGpu == NULL) + { + return NV_ERR_INVALID_STATE; + } + if (!pPlatformRequestHandler->getProperty(pPlatformRequestHandler, PDB_PROP_PFMREQHNDLR_SUPPORTED)) + { + return NV_OK; + } + + if (!PFM_REQ_HNDLR_IS_ACPI_VERSION_SW_2X(pPlatformRequestHandler)) + { + // Find default Temp for Thermal Controller from SBIOS. + if (NV_OK == pfmreqhndlrGetPerfSensorCounterById(pPlatformRequestHandler, + PFM_REQ_HNDLR_LIMIT(PFM_REQ_HNDLR_TGPU_SENSOR), + &data32)) + { + targetTemp = NV_TYPES_CELSIUS_TO_NV_TEMP(data32); + } + + if (targetTemp != PFM_REQ_HNDLR_TEMP_0_C) + { + if (pPlatformRequestHandler->controlData.bTGPUOverrideRequired) + { + NV2080_CTRL_CMD_INTERNAL_THERM_PFM_REQ_HNDLR_UPDATE_TGPU_LIMIT_PARAMS params = { 0 }; + params.targetTemp = targetTemp; + pRmApi = GPU_GET_PHYSICAL_RMAPI(pGpu); + + status = pRmApi->Control(pRmApi, + pGpu->hInternalClient, + pGpu->hInternalSubdevice, + NV2080_CTRL_CMD_INTERNAL_THERM_PFM_REQ_HNDLR_UPDATE_TGPU_LIMIT, + ¶ms, + sizeof(params)); + + if (status == NV_OK) + { + pPlatformRequestHandler->controlData.bTGPUOverrideRequired = NV_FALSE; + } + else + { + NV_ASSERT_FAILED("PRH failed to update thermal limit!"); + + } + } + + if (!pPlatformRequestHandler->controlData.bPM1ForcedOff) + { + if (pfmreqhndlrHandleCheckPM1Available(pPlatformRequestHandler, pGpu, &bPM1Available) == NV_OK) + { + pfmreqhndlrUpdatePerfCounter(pPlatformRequestHandler, PFM_REQ_HNDLR_PM1_STATE_AVAIL, bPM1Available); + } + } + else + { + pfmreqhndlrUpdatePerfCounter(pPlatformRequestHandler, PFM_REQ_HNDLR_PM1_STATE_AVAIL, NV_FALSE); + } + } + } + + return NV_OK; +} + +NV_STATUS +pfmreqhndlrStateUnload_IMPL +( + PlatformRequestHandler *pPlatformRequestHandler +) +{ + return NV_OK; +} + +NV_STATUS +pfmreqhndlrStateSync_IMPL +( + PlatformRequestHandler *pPlatformRequestHandler, + OBJGPU *pGpu, + NV2080_CTRL_INTERNAL_PFM_REQ_HNDLR_STATE_SYNC_PARAMS + *pParams +) +{ + NV_STATUS status = NV_OK; + + switch(pParams->flags) + { + case NV2080_CTRL_INTERNAL_PFM_REQ_HNDLR_STATE_SYNC_FLAGS_PMGR_LOAD: + { + status = _pfmreqhndlrPmgrPmuPostLoadPrereqCallback(pGpu, NV_TRUE); + break; + } + case NV2080_CTRL_INTERNAL_PFM_REQ_HNDLR_STATE_SYNC_FLAGS_THERM_INIT: + { + status = _pfmreqhndlrThermPmuPostInitPrereqCallback(pGpu, NV_TRUE); + break; + } + case NV2080_CTRL_INTERNAL_PFM_REQ_HNDLR_STATE_SYNC_FLAGS_SMBPBI_OP_CLEAR: + { + status = pfmreqhndlrOperatingLimitUpdate(pPlatformRequestHandler, pParams->syncData.data.smbpbi.sensorId, + 0, NV_FALSE); + break; + } + case NV2080_CTRL_INTERNAL_PFM_REQ_HNDLR_STATE_SYNC_FLAGS_SMBPBI_OP_SET: + { + status = pfmreqhndlrOperatingLimitUpdate(pPlatformRequestHandler, pParams->syncData.data.smbpbi.sensorId, + pParams->syncData.data.smbpbi.limit, NV_TRUE); + break; + } + default: + { + return NV_ERR_NOT_SUPPORTED; + } + } + + return status; +} + +/*! + * @brief Checks if ACPI supports calls necessary for the PLATFORM_REQUEST_HANDLER + * + * @param[in] pPlatformRequestHandler *PlatformRequestHandler pointer + * @param[in] pGpu OBJGPU pointer + * + * @return NV_ERR_NOT_SUPPORTED ACPI does not provide support for PLATFORM_REQUEST_HANDLER + * @return NV_OK otherwise + */ +static NV_STATUS +_pfmreqhndlrSupportExists +( + PlatformRequestHandler *pPlatformRequestHandler, + OBJGPU *pGpu +) +{ + NvU64 supportedFunction = 0; + NvU16 outDataSize = 0; + + if (pPlatformRequestHandler->dsmVersion == ACPI_DSM_FUNCTION_INVALID) + { + return NV_ERR_NOT_SUPPORTED; + } + + outDataSize = sizeof(supportedFunction); + + + if (osCallACPI_DSM(pGpu, + pPlatformRequestHandler->dsmVersion, + GPS_FUNC_SUPPORT, + (NvU32 *)&supportedFunction, + &outDataSize) != NV_OK) + { + NV_PRINTF(LEVEL_ERROR, + "GPS FUNC_SUPPORT is not supported on this Platform, Failing ACPI-GPS subfunction 0x%x.\n", + GPS_FUNC_SUPPORT); + return NV_ERR_NOT_SUPPORTED; + } + else + { + if (supportedFunction == 0) + { + NV_PRINTF(LEVEL_INFO, + "PRH : This system doesn't support any ACPI-GPS-subfunctions.\n"); + return NV_ERR_NOT_SUPPORTED; + } + } + + return NV_OK; +} + +/*! + * @brief Check and get PM1ForcedOff state + * + * @param[in] pPlatformRequestHandler *PlatformRequestHandler pointer + * @param[in] pGpu OBJGPU pointer + * + * @return NV_TRUE if PM1ForcedOff state is set + * @return NV_FALSE if PM1ForcedOff state is not set + */ +NvBool +_pfmreqhndlrCheckAndGetPM1ForcedOffState +( + PlatformRequestHandler *pPlatformRequestHandler, + OBJGPU *pGpu +) +{ + RM_API *pRmApi = GPU_GET_PHYSICAL_RMAPI(pGpu); + NvBool bForcedOff = NV_FALSE; // Return NV_FALSE to match Legacy return values + NV_STATUS status = NV_ERR_GENERIC; + + NV2080_CTRL_CMD_INTERNAL_PERF_PFM_REQ_HNDLR_GET_PM1_STATE_PARAMS params = { 0 }; + params.flag = NV2080_CTRL_INTERNAL_PFM_REQ_HNDLR_GET_PM1_FORCED_OFF_STATUS; + + status = pRmApi->Control(pRmApi, + pGpu->hInternalClient, + pGpu->hInternalSubdevice, + NV2080_CTRL_CMD_INTERNAL_PERF_PFM_REQ_HNDLR_GET_PM1_STATE, + ¶ms, + sizeof(params)); + + if (status == NV_OK) + { + bForcedOff = params.bStatus; + } + + return bForcedOff; + +} + +/*! + * @copydoc GpuPrereqCallback + */ +static NV_STATUS +_pfmreqhndlrThermPmuPostInitPrereqCallback +( + OBJGPU *pGpu, + NvBool bSatisfied +) +{ + OBJSYS *pSys = SYS_GET_INSTANCE(); + PlatformRequestHandler *pPlatformRequestHandler = SYS_GET_PFM_REQ_HNDLR(pSys); + NV_STATUS status = NV_OK; + NvU32 data32 = 0; + NvTemp targetTemp; + NvBool bPM1Available = NV_FALSE; + RM_API *pRmApi = GPU_GET_PHYSICAL_RMAPI(pGpu); + // + // bSatisfied handling: + // Only needs to be applied after THERM post pmu init bSatisfied = NV_TRUE + // No need to revert the settings since it is a client applied limit + // so the bSatisfied = NV_FALSE is not required to be handled. + // + // satisfy()/retract () handling: is not supported for this callback since it + // depends on prereq _THERM_PMU_LOADED. + // + if (bSatisfied) + { + // Find default Temp for Thermal Controller from SBIOS. + status = pfmreqhndlrGetPerfSensorCounterById(pPlatformRequestHandler, PFM_REQ_HNDLR_LIMIT(PFM_REQ_HNDLR_TGPU_SENSOR), + &data32); + if (status == NV_OK) + { + // Overrride with system Temp + targetTemp = NV_TYPES_CELSIUS_TO_NV_TEMP(data32); + } + else + { + // Override value is set to 0C + targetTemp = PFM_REQ_HNDLR_TEMP_0_C; + + // Fall back to legacy implementation + status = NV_OK; + } + if (targetTemp != PFM_REQ_HNDLR_TEMP_0_C) + { + if (pPlatformRequestHandler->controlData.bTGPUOverrideRequired) + { + NV2080_CTRL_CMD_INTERNAL_THERM_PFM_REQ_HNDLR_UPDATE_TGPU_LIMIT_PARAMS params = { 0 }; + params.targetTemp = targetTemp; + + status = pRmApi->Control(pRmApi, + pGpu->hInternalClient, + pGpu->hInternalSubdevice, + NV2080_CTRL_CMD_INTERNAL_THERM_PFM_REQ_HNDLR_UPDATE_TGPU_LIMIT, + ¶ms, + sizeof(params)); + + if (status == NV_OK) + { + pPlatformRequestHandler->controlData.bTGPUOverrideRequired = NV_FALSE; + } + else + { + NV_ASSERT_FAILED("PRH failed to update thermal limit!"); + + // Fall back to legacy implementation + status = NV_OK; + } + } + + if (!pPlatformRequestHandler->controlData.bPM1ForcedOff) + { + if (pfmreqhndlrHandleCheckPM1Available(pPlatformRequestHandler, pGpu, &bPM1Available) == NV_OK) + { + pfmreqhndlrUpdatePerfCounter(pPlatformRequestHandler, PFM_REQ_HNDLR_PM1_STATE_AVAIL, bPM1Available); + } + else + { + pfmreqhndlrUpdatePerfCounter(pPlatformRequestHandler, PFM_REQ_HNDLR_PM1_STATE_AVAIL, NV_FALSE); + } + } + else + { + pfmreqhndlrUpdatePerfCounter(pPlatformRequestHandler, PFM_REQ_HNDLR_PM1_STATE_AVAIL, NV_FALSE); + } + } + } + + return status; +} + +/*! + * @copydoc GpuPrereqCallback + */ +NV_STATUS +_pfmreqhndlrPmgrPmuPostLoadPrereqCallback +( + OBJGPU *pGpu, + NvBool bSatisfied +) +{ + OBJSYS *pSys = SYS_GET_INSTANCE(); + PlatformRequestHandler + *pPlatformRequestHandler + = SYS_GET_PFM_REQ_HNDLR(pSys); + NV_STATUS status = NV_OK; + NV_STATUS lcstatus; + + // + // bSatisfied handling: + // Only needs to be applied after PMGR post load bSatisfied = NV_TRUE + // No need to revert the settings since it is a client applied limit + // so the bSatisfied = NV_FALSE is not required to be handled. + // + // satisfy()/retract () handling: is not supported for this callback since it + // depends on prereq _PMGR_PMU_LOADED . + // + if (bSatisfied) + { + // + // EDPpeak event update, at this point SBIOS requested state should match + // with current control state if not trigger an update. + // + if (pPlatformRequestHandler->sensorData.PFMREQHNDLRACPIData.bEDPpeakLimitUpdateRequest != + pPlatformRequestHandler->controlData.bEDPpeakUpdateEnabled) + { + // Update or Reset the EDPp limit if needed + lcstatus = pfmreqhndlrHandleEdppeakLimitUpdate(pPlatformRequestHandler, pGpu, + pPlatformRequestHandler->sensorData.PFMREQHNDLRACPIData.bEDPpeakLimitUpdateRequest); + if ((lcstatus != NV_OK) && (lcstatus != NV_ERR_NOT_SUPPORTED)) + { + NV_ASSERT_OK_FAILED("Failed to apply the EDPpeak limit from system", status); + status = lcstatus; + goto _pfmreqhndlrPmgrPmuPostLoadPrereqCallback_exit; + } + } + + // + // User configurable TGP mode (Turbo) event update, at this point SBIOS requested + // state should match with current control state if not trigger an update. + // + if (pPlatformRequestHandler->sensorData.PFMREQHNDLRACPIData.bUserConfigTGPmodeRequest != + pPlatformRequestHandler->controlData.bUserConfigTGPmodeEnabled) + { + // Enable or Reset the use configurable TGP mode (TGP Turbo mode) if needed. + lcstatus = pfmreqhndlrHandleUserConfigurableTgpMode(pPlatformRequestHandler, pGpu, + pPlatformRequestHandler->sensorData.PFMREQHNDLRACPIData.bUserConfigTGPmodeRequest); + if ((lcstatus != NV_OK) && (lcstatus != NV_ERR_NOT_SUPPORTED)) + { + NV_ASSERT_OK_FAILED("Failed to update user configurable TGP (Turbo) mode from system", + status); + status = lcstatus; + goto _pfmreqhndlrPmgrPmuPostLoadPrereqCallback_exit; + } + } + + // + // Platform EDPp limit if differed apply it after prereq is satisfied + // + if (pPlatformRequestHandler->controlData.edppLimit.bDifferPlatformEdppLimit) + { + lcstatus = pfmreqhndlrHandlePlatformEdppLimitUpdate(pPlatformRequestHandler, pGpu, + pPlatformRequestHandler->sensorData.PFMREQHNDLRACPIData.platformEdppLimit); + if ((NV_OK != lcstatus) && + (NV_ERR_NOT_SUPPORTED != lcstatus)) + { + NV_ASSERT_OK_FAILED("Failed to update platform EDPpeak limit", + status); + status = lcstatus; + goto _pfmreqhndlrPmgrPmuPostLoadPrereqCallback_exit; + } + + // Reset the differ update flag + pPlatformRequestHandler->controlData.edppLimit.bDifferPlatformEdppLimit = NV_FALSE; + } + } + +_pfmreqhndlrPmgrPmuPostLoadPrereqCallback_exit: + return status; +} + diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/kernel/platform/platform_request_handler_ctrl.c nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/kernel/platform/platform_request_handler_ctrl.c --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/kernel/platform/platform_request_handler_ctrl.c 1970-01-01 00:00:00.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/kernel/platform/platform_request_handler_ctrl.c 2024-03-05 22:14:01.000000000 +0000 @@ -0,0 +1,2932 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2015-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +/***************************************************************************\ +* * +* This module contains the Platform Request Handler control interface * +* * +\***************************************************************************/ + +/* ------------------------ Includes --------------------------------------- */ +#include "nvRmReg.h" +#include "platform/platform_request_handler.h" +#include "platform/platform_request_handler_utils.h" +#include "platform/acpi_common.h" +#include "diagnostics/tracer.h" +#include "os/os.h" +#include "objtmr.h" +#include "core/locks.h" +#include "gps.h" +#include "rmapi/client_resource.h" + +/* ------------------------ Datatypes -------------------------------------- */ +// private typedef for this source file. +typedef NV_STATUS PfmreqhndlrControlHandler(PlatformRequestHandler *pPlatformRequestHandler, NvU16 locale, NvU32 *pData); + +// prototypes, to be used inside _PfmreqhndlrControlHandlerTable[] +static PfmreqhndlrControlHandler _handleCmdSystemPfmreqhndlrGetSupportedFunctions; +static PfmreqhndlrControlHandler _handleCmdSystemPfmreqhndlrDataInitUsingSbiosAndAck; + +typedef struct +{ + NvU16 command; + PfmreqhndlrControlHandler *handler; +} PFM_REQ_HNDLR_CONTROL_ENTRY; + +PFM_REQ_HNDLR_CONTROL_ENTRY _PfmreqhndlrControlTable[] = +{ + { NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_SYS_GET_SUPPORTED_FUNCTIONS , _handleCmdSystemPfmreqhndlrGetSupportedFunctions }, + { NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_INIT_USING_SBIOS_AND_ACK, _handleCmdSystemPfmreqhndlrDataInitUsingSbiosAndAck }, + + // always end with a NULL record + { NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_INVALID, NULL } +}; + +NvU16 PerfSensorBlockMap[][32] = { + { + PFM_REQ_HNDLR_RESERVED_COUNTER, PFM_REQ_HNDLR_RESERVED_COUNTER, // 0, 1 + PFM_REQ_HNDLR_RESERVED_COUNTER, PFM_REQ_HNDLR_RESERVED_COUNTER, // 2, 3 + PFM_REQ_HNDLR_RESERVED_COUNTER, PFM_REQ_HNDLR_RESERVED_COUNTER, // 4, 5 + PFM_REQ_HNDLR_RESERVED_COUNTER, PFM_REQ_HNDLR_RESERVED_COUNTER, // 6, 7 + PFM_REQ_HNDLR_RESERVED_COUNTER, PFM_REQ_HNDLR_RESERVED_COUNTER, // 8, 9 + PFM_REQ_HNDLR_RESERVED_COUNTER, PFM_REQ_HNDLR_RESERVED_COUNTER, // 10, 11 + PFM_REQ_HNDLR_RESERVED_COUNTER, PFM_REQ_HNDLR_RESERVED_COUNTER, // 12, 13 + PFM_REQ_HNDLR_TC_ENABLE, PFM_REQ_HNDLR_RESERVED_COUNTER, // 14, 15 + PFM_REQ_HNDLR_RESERVED_COUNTER, PFM_REQ_HNDLR_RESERVED_COUNTER, // 16, 17 + PFM_REQ_HNDLR_PSR_PUB_ENTRY(PFM_REQ_HNDLR_PM1_STATE_AVAIL), PFM_REQ_HNDLR_RESERVED_COUNTER, // 18, 19 + PFM_REQ_HNDLR_RESERVED_COUNTER, PFM_REQ_HNDLR_RESERVED_COUNTER, // 20, 21 + PFM_REQ_HNDLR_RESERVED_COUNTER, PFM_REQ_HNDLR_RESERVED_COUNTER, // 22, 23 + PFM_REQ_HNDLR_RESERVED_COUNTER, PFM_REQ_HNDLR_RESERVED_COUNTER, // 24, 25 + PFM_REQ_HNDLR_CURR_VALUE_PUB_ENTRY(PFM_REQ_HNDLR_TGPU_SENSOR), PFM_REQ_HNDLR_RESERVED_COUNTER, // 26, 27 + PFM_REQ_HNDLR_RESERVED_COUNTER, PFM_REQ_HNDLR_RESERVED_COUNTER, // 28, 29 + PFM_REQ_HNDLR_RESERVED_COUNTER, PFM_REQ_HNDLR_RESERVED_COUNTER // 30, 31 + }, + { + PFM_REQ_HNDLR_RESERVED_COUNTER, PFM_REQ_HNDLR_RESERVED_COUNTER, // 0, 1 + PFM_REQ_HNDLR_RESERVED_COUNTER, PFM_REQ_HNDLR_RESERVED_COUNTER, // 2, 3 + PFM_REQ_HNDLR_RESERVED_COUNTER, PFM_REQ_HNDLR_RESERVED_COUNTER, // 4, 5 + PFM_REQ_HNDLR_RESERVED_COUNTER, PFM_REQ_HNDLR_RESERVED_COUNTER, // 6, 7 + PFM_REQ_HNDLR_RESERVED_COUNTER, PFM_REQ_HNDLR_RESERVED_COUNTER, // 8, 9 + PFM_REQ_HNDLR_RESERVED_COUNTER, PFM_REQ_HNDLR_RESERVED_COUNTER, // 10, 11 + PFM_REQ_HNDLR_RESERVED_COUNTER, PFM_REQ_HNDLR_RESERVED_COUNTER, // 12, 13 + PFM_REQ_HNDLR_RESERVED_COUNTER, PFM_REQ_HNDLR_RESERVED_COUNTER, // 14, 15 + PFM_REQ_HNDLR_RESERVED_COUNTER, PFM_REQ_HNDLR_RESERVED_COUNTER, // 16, 17 + PFM_REQ_HNDLR_RESERVED_COUNTER, PFM_REQ_HNDLR_VPS_PS20_SUPPORT, // 18, 19 + PFM_REQ_HNDLR_RESERVED_COUNTER, PFM_REQ_HNDLR_RESERVED_COUNTER, // 20, 21 + PFM_REQ_HNDLR_RESERVED_COUNTER, PFM_REQ_HNDLR_RESERVED_COUNTER, // 22, 23 + PFM_REQ_HNDLR_RESERVED_COUNTER, PFM_REQ_HNDLR_RESERVED_COUNTER, // 24, 25 + PFM_REQ_HNDLR_RESERVED_COUNTER, PFM_REQ_HNDLR_RESERVED_COUNTER, // 26, 27 + PFM_REQ_HNDLR_RESERVED_COUNTER, PFM_REQ_HNDLR_RESERVED_COUNTER, // 28, 29 + PFM_REQ_HNDLR_RESERVED_COUNTER, PFM_REQ_HNDLR_RESERVED_COUNTER // 30, 31 + }, + { + PFM_REQ_HNDLR_RESERVED_COUNTER, PFM_REQ_HNDLR_RESERVED_COUNTER, // 0, 1 + PFM_REQ_HNDLR_RESERVED_COUNTER, PFM_REQ_HNDLR_RESERVED_COUNTER, // 2, 3 + PFM_REQ_HNDLR_RESERVED_COUNTER, PFM_REQ_HNDLR_RESERVED_COUNTER, // 4, 5 + PFM_REQ_HNDLR_RESERVED_COUNTER, PFM_REQ_HNDLR_RESERVED_COUNTER, // 6, 7 + PFM_REQ_HNDLR_RESERVED_COUNTER, PFM_REQ_HNDLR_RESERVED_COUNTER, // 8, 9 + PFM_REQ_HNDLR_RESERVED_COUNTER, PFM_REQ_HNDLR_RESERVED_COUNTER, // 10, 11 + PFM_REQ_HNDLR_RESERVED_COUNTER, PFM_REQ_HNDLR_RESERVED_COUNTER, // 12, 13 + PFM_REQ_HNDLR_RESERVED_COUNTER, PFM_REQ_HNDLR_RESERVED_COUNTER, // 14, 15 + PFM_REQ_HNDLR_RESERVED_COUNTER, PFM_REQ_HNDLR_RESERVED_COUNTER, // 16, 17 + PFM_REQ_HNDLR_RESERVED_COUNTER, PFM_REQ_HNDLR_RESERVED_COUNTER, // 18, 19 + PFM_REQ_HNDLR_RESERVED_COUNTER, PFM_REQ_HNDLR_RESERVED_COUNTER, // 20, 21 + PFM_REQ_HNDLR_RESERVED_COUNTER, PFM_REQ_HNDLR_RESERVED_COUNTER, // 22, 23 + PFM_REQ_HNDLR_RESERVED_COUNTER, PFM_REQ_HNDLR_RESERVED_COUNTER, // 24, 25 + PFM_REQ_HNDLR_RESERVED_COUNTER, PFM_REQ_HNDLR_RESERVED_COUNTER, // 26, 27 + PFM_REQ_HNDLR_RESERVED_COUNTER, PFM_REQ_HNDLR_RESERVED_COUNTER, // 28, 29 + PFM_REQ_HNDLR_RESERVED_COUNTER, PFM_REQ_HNDLR_RESERVED_COUNTER // 30, 31 + }, + { + PFM_REQ_HNDLR_RESERVED_COUNTER, PFM_REQ_HNDLR_RESERVED_COUNTER, // 0, 1 + PFM_REQ_HNDLR_RESERVED_COUNTER, PFM_REQ_HNDLR_RESERVED_COUNTER, // 2, 3 + PFM_REQ_HNDLR_RESERVED_COUNTER, PFM_REQ_HNDLR_RESERVED_COUNTER, // 4, 5 + PFM_REQ_HNDLR_RESERVED_COUNTER, PFM_REQ_HNDLR_RESERVED_COUNTER, // 6, 7 + PFM_REQ_HNDLR_LIMIT(PFM_REQ_HNDLR_TGPU_SENSOR), PFM_REQ_HNDLR_RESERVED_COUNTER, // 8, 9 + PFM_REQ_HNDLR_RESERVED_COUNTER, PFM_REQ_HNDLR_RESERVED_COUNTER, // 10, 11 + PFM_REQ_HNDLR_RESERVED_COUNTER, PFM_REQ_HNDLR_RESERVED_COUNTER, // 12, 13 + PFM_REQ_HNDLR_RESERVED_COUNTER, PFM_REQ_HNDLR_RESERVED_COUNTER, // 14, 15 + PFM_REQ_HNDLR_RESERVED_COUNTER, PFM_REQ_HNDLR_RESERVED_COUNTER, // 16, 17 + PFM_REQ_HNDLR_RESERVED_COUNTER, PFM_REQ_HNDLR_RESERVED_COUNTER, // 18, 19 + PFM_REQ_HNDLR_RESERVED_COUNTER, PFM_REQ_HNDLR_RESERVED_COUNTER, // 20, 21 + PFM_REQ_HNDLR_RESERVED_COUNTER, PFM_REQ_HNDLR_RESERVED_COUNTER, // 22, 23 + PFM_REQ_HNDLR_AVAIL_SENSOR_MSK, PFM_REQ_HNDLR_RESERVED_COUNTER, // 24, 25 + PFM_REQ_HNDLR_RESERVED_COUNTER, PFM_REQ_HNDLR_RESERVED_COUNTER, // 26, 27 + PFM_REQ_HNDLR_RESERVED_COUNTER, PFM_REQ_HNDLR_RESERVED_COUNTER, // 28, 29 + PFM_REQ_HNDLR_RESERVED_COUNTER, PFM_REQ_HNDLR_RESERVED_COUNTER // 30, 31 + } +}; + +/* ------------------------ Macros ----------------------------------------- */ +/*! + * Macro to detect and request a new update if it is necessary. + * If system has already applied the update or reset to EDPpeak limit + * the subsequent requests to do the same are ignored unless its different request. + */ +#define PFM_REQ_HNDLR_IS_EDPPEAK_UPDATE_REQUIRED(bUpdateAcpiRequest, bEnabled) \ + ((bUpdateAcpiRequest && !bEnabled) || (!bUpdateAcpiRequest && bEnabled)) + +/*! + * Macro to detect and request to enable user configurable TGP mode if it is necessary. + * If system has already applied the update or reset to user configurable TGP mode + * the subsequent requests to do the same are ignored unless its different request. + */ +#define PFM_REQ_HNDLR_IS_USER_CONFIG_TGP_MODE_UPDATE_REQUIRED(bUpdateAcpiRequest, bEnabled) \ + ((bUpdateAcpiRequest && !bEnabled) || (!bUpdateAcpiRequest && bEnabled)) + +/*! + * Macro to detect if a PLATFORM REQUEST HANDLER counter value is valid, the counter is valid if + * the counter is supported and its value updated with a valid bit set. + */ +#define PFM_REQ_HNDLR_IS_COUNTER_VALID(pPlatformRequestHandler, counterId) \ + ((&(pPlatformRequestHandler->sensorData))->PFMREQHNDLRSensorCache[counterId].bSupported && \ + (!(&(pPlatformRequestHandler->sensorData))->PFMREQHNDLRSensorCache[counterId].bInvalid)) + + /* ------------------------ Defines ---------------------------------------- */ +#define PFM_REQ_HNDLR_USE_SBIOS_LIMIT (0U) +#define PFM_REQ_HNDLR_DISABLE_LIMIT (255U) +#define PFM_REQ_HNDLR_AVAILABLE_SENSOR_BLOCKS (4U) +#define NV0000_CTRL_PFM_REQ_HNDLR_THERM_LIMIT_SRC_USER_LIMITED (1) +#define NV0000_CTRL_PFM_REQ_HNDLR_THERM_LIMIT_SRC_SBIOS_LIMITED (2) +#define NV0000_CTRL_PFM_REQ_HNDLR_THERM_LIMIT_SRC_SBIOS_UNLIMITED (3) +#define NV0000_CTRL_PFM_REQ_HNDLR_THERM_LIMIT_SRC_SBIOS_NOT_SUPPORTED (4) +#define NV0000_CTRL_PFM_REQ_HNDLR_THERM_LIMIT_SRC_USER_DISABLED (5) + +/* ---------------------- Static Function Prototypes ----------------------- */ +static NV_STATUS _pfmreqhndlrSampleSensorLimit (PlatformRequestHandler *pPlatformRequestHandler, NvU32 id, NvU32 timeStamp); +static NV_STATUS _pfmreqhndlrSampleSensorLimit_ACPI (PlatformRequestHandler *pPlatformRequestHandler, NvU32 id, NvU32 timeStamp); +static NV_STATUS _pfmreqhndlrUpdateSystemParamLimit (PlatformRequestHandler *pPlatformRequestHandler, NvU32 id); +static void _pfmreqhndlrUpdateSystemParamLimitWorkItem (NvU32 gpuInstance, void *pParams); +static void _pfmreqhndlrResetCounter (PFM_REQ_HNDLR_SENSOR_DATA *pPfmreqhndlrData, NvU32 id, NvU32 timeStamp); +static void _pfmreqhndlrUpdateCounter (PFM_REQ_HNDLR_SENSOR_DATA *pPfmreqhndlrData, NvU32 id, NvBool bValid, NvU32 value, NvU32 timeStamp); +static void _pfmreqhndlrOverrideCounter (PFM_REQ_HNDLR_SENSOR_DATA *pPfmreqhndlrData, NvU32 id, NvU32 value, NvU32 timeStamp); +static void _pfmreqhndlrCancelCounterOverride (PFM_REQ_HNDLR_SENSOR_DATA *pPfmreqhndlrData, NvU32 id, NvU32 timeStamp); +static void _pfmreqhndlrInitSupportedCounter (PFM_REQ_HNDLR_SENSOR_DATA *pPfmreqhndlrData, NvU32 id, NvBool bVolatile, NvU32 timeStamp); +static NvBool _pfmreqhndlrIsCacheEntryStale (PFM_REQ_HNDLR_SENSOR_DATA *pPfmreqhndlrData, NvU32 counterId, NvU32 timeStamp); +static NV_STATUS _pfmreqhndlrCallPshareStatus (PlatformRequestHandler *pPlatformRequestHandler, NvBool bInit); +static NvU32 _pfmreqhndlrGetTimeStamp (PlatformRequestHandler *pPlatformRequestHandler); +static NV_STATUS _pfmreqhndlrEnablePM1 (OBJGPU *pGpu, NvBool bEnable); +static NV_STATUS _pfmreqhndlrSetSupportedStatesFromAcpiParams(OBJGPU *pGpu, PlatformRequestHandler *pPlatformRequestHandler, NvU32 supportedSubfuncs); +static NV_STATUS _pfmreqhndlrHandleUserConfigurableTgpModePlatformCustomization(PlatformRequestHandler *pPlatformRequestHandler, OBJGPU *pGpu); +static void _pfmreqhndlrUpdatePlatformPowerModeWorkItem (NvU32 gpuInstance, void *pParams); +static void _pfmreqhndlrPlatformPowerModeStateReset (PlatformRequestHandler *pPlatformRequestHandler); +static NV_STATUS _pfmreqhndlrUpdatePpmdLimit (PlatformRequestHandler *pPlatformRequestHandler, OBJGPU *pGpu, NvBool bInit); +static NV_STATUS _pfmreqhndlrUpdateTgpuLimit (PlatformRequestHandler *pPlatformRequestHandler, OBJGPU *pGpu); +static void _pfmreqhndlrHandlePlatformSetEdppLimitInfoWorkItem(NvU32 gpuInstance, void *pParams); + +/* ------------------------ Public Functions ------------------------------ */ +NV_STATUS +pfmreqhndlrControl_IMPL +( + PlatformRequestHandler *pPlatformRequestHandler, + NvU16 command, + NvU16 locale, + NvU32 *pData +) +{ + PFM_REQ_HNDLR_CONTROL_ENTRY *pPfmreqhndlrCtrlTableEntry = NULL; + + if (!pPlatformRequestHandler) + { + return NV_ERR_NOT_SUPPORTED; + } + + for (pPfmreqhndlrCtrlTableEntry = _PfmreqhndlrControlTable; + pPfmreqhndlrCtrlTableEntry->handler; + pPfmreqhndlrCtrlTableEntry++) + { + if (command == pPfmreqhndlrCtrlTableEntry->command) + { + return pPfmreqhndlrCtrlTableEntry->handler(pPlatformRequestHandler, locale, pData); + } + } + + return NV_ERR_NOT_SUPPORTED; +} + +/*! + * Set/Remove the operating limit of a specific system-parameter (denoted by + * id) using a deferred workitem. + * + * @param[in] pPlatformRequestHandler *PlatformRequestHandler pointer + * @param[in] id Identifier of parameter (PFM_REQ_HNDLR_*_SENSOR) to update + * @param[in] limit + * New operating-limit to set for the parameter. All limits are accepted as + * unsigned integers, but internally they should be formatted based on the + * type of id/sensor they correspond to. Limits for temperature-sensors for + * instance should be stored in NvTemp format. + * @param[in] bSet Indicates we are setting or removing the limit + * + * @return NV_OK Upon successful update + * @return NV_ERR_INVALID_ARGUMENT Invalid parameter type/id + * @return NV_ERR_INVALID_REQUEST + * Returned if the provided PlatformRequestHandler pointer was NULL or if the corresponding + * OBJGPU object could not be found. + */ +NV_STATUS +pfmreqhndlrOperatingLimitUpdate_IMPL +( + PlatformRequestHandler *pPlatformRequestHandler, + NvU32 id, + NvU32 limit, + NvBool bSet +) +{ + NV_STATUS status = NV_OK; + OBJGPU *pGpu = pfmreqhndlrGetGpu(pPlatformRequestHandler); + OBJOS *pOs = GPU_GET_OS(pGpu); + + if (id >= PFM_REQ_HNDLR_PSHAREPARAMS_COUNT) + { + return NV_ERR_INVALID_ARGUMENT; + } + NV_ASSERT_OR_RETURN(NULL != pPlatformRequestHandler, NV_ERR_INVALID_REQUEST); + + if (bSet) + { + // + // Temperature limits arrive in NvTemp format but are stored in NvU32 + // format. Perform the converstion. The limits will be transformed back to + // NvTemp values before they are used. Once the analogous ACPI code is + // changed to perform an immediate conversion from NvS32 to NvTemp, the + // limits can be stored in NvTemp format directly and double-conversion can + // be removed. + // + switch (id) + { + case PFM_REQ_HNDLR_TGPU_SENSOR: + limit = NV_TYPES_NV_TEMP_TO_CELSIUS_ROUNDED((NvTemp)limit); + break; + } + + status = pfmreqhndlrUpdatePerfCounter(pPlatformRequestHandler, PFM_REQ_HNDLR_LIMIT(id), limit); + if (status != NV_OK) + { + NV_PRINTF(LEVEL_ERROR, "Update perf counter failed.\n"); + DBG_BREAKPOINT(); + return status; + } + } + else + { + _pfmreqhndlrResetCounter(&pPlatformRequestHandler->sensorData, PFM_REQ_HNDLR_LIMIT(id), + _pfmreqhndlrGetTimeStamp(pPlatformRequestHandler)); + } + + // Record which counter needs to be updated + pPlatformRequestHandler->sysControlData.queuedCounterMask |= NVBIT(id); + + // + // Don't submit the workitem again if there is already a pending workitem, + // all the touched counters will be updated once the workitem is executed. + // + if (!pPlatformRequestHandler->sysControlData.bWorkItemPending) + { + status = pOs->osQueueWorkItem(pGpu, + _pfmreqhndlrUpdateSystemParamLimitWorkItem, NULL); + + if (status != NV_OK) + { + // + // It is not a real failure if the OS doesn't support workitem, + // thus setting the status to NV_OK so that we will update the + // limit directly in this situation. But if the error code is + // not NV_ERR_NOT_SUPPORTED, then we treat it as real failure + // and will not do any update. The queued ID will be kept in + // this situation so that we can still handle it if we get any + // chance to queue another workitem later. + // + if (status == NV_ERR_NOT_SUPPORTED) + { + // + // Reset the queued id if the workitem is not supported (we + // will update the limit directly) + // + pPlatformRequestHandler->sysControlData.queuedCounterMask &= ~(NVBIT(id)); + status = NV_OK; + } + } + else + { + pPlatformRequestHandler->sysControlData.bWorkItemPending = NV_TRUE; + } + } + + if (status == NV_OK) + { + if (!pPlatformRequestHandler->sysControlData.bWorkItemPending) + { + // + // Update the limit directly if nothing wrong and no workitem is + // queued + // + return _pfmreqhndlrUpdateSystemParamLimit(pPlatformRequestHandler, id); + } + else + { + // + // Let the client knows that more processing is needed since + // workitem is queued + // + return NV_WARN_MORE_PROCESSING_REQUIRED; + } + } + + return status; +} + +// +// cliresCtrlCmdSystemPfmreqhndlrCtrl +// +// This function process control request for the PLATFORM REQUEST HANDLER object. +// +NV_STATUS +cliresCtrlCmdSystemPfmreqhndlrCtrl_IMPL +( + RmClientResource *pRmCliRes, + NV0000_CTRL_SYSTEM_PFM_REQ_HNDLR_CTRL_PARAMS *pParams +) +{ + OBJSYS *pSys = SYS_GET_INSTANCE(); + PlatformRequestHandler *pPlatformRequestHandler = SYS_GET_PFM_REQ_HNDLR(pSys); + OBJGPU *pGpu = NULL; + PPFM_REQ_HNDLR_SENSOR_DATA pPfmreqhndlrData = NULL; + NV_STATUS status = NV_OK; + NvU32 timeStamp; + NvU32 newLimit; + NvU32 counterVal; + NvU16 counterId; + RM_API *pRmApi = NULL; + + if (NULL == pPlatformRequestHandler) + { + return NV_ERR_NOT_SUPPORTED; + } + pGpu = pfmreqhndlrGetGpu(pPlatformRequestHandler); + pPfmreqhndlrData = &(pPlatformRequestHandler->sensorData); + + if (NULL == pGpu) + { + return NV_ERR_NOT_SUPPORTED; + } + + pRmApi = GPU_GET_PHYSICAL_RMAPI(pGpu); + + timeStamp = _pfmreqhndlrGetTimeStamp(pPlatformRequestHandler); + + switch (pParams->cmd) + { + case NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_GET_THERM_LIMIT: + { + counterId = (NvU16)pParams->input[NV0000_CTRL_PFM_REQ_HNDLR_INPUT_SENSOR_INDEX]; + + if (PFM_REQ_HNDLR_VALID_LIMIT_ID(counterId)) + { + if (NV_OK == pfmreqhndlrGetPerfSensorCounterById(pPlatformRequestHandler, + counterId, + &counterVal)) + { + pParams->result[NV0000_CTRL_PFM_REQ_HNDLR_RESULT_THERMAL_LIMIT] = counterVal; + if (pPfmreqhndlrData->PFMREQHNDLRSensorCache[counterId].bOverridden) + { + // the Thermal limit is from a user specified limit. + pParams->result[NV0000_CTRL_PFM_REQ_HNDLR_RESULT_LIMIT_SOURCE] = + NV0000_CTRL_PFM_REQ_HNDLR_THERM_LIMIT_SRC_USER_LIMITED; + } + else + { + // the thermal limit is from the SBIOS. + pParams->result[NV0000_CTRL_PFM_REQ_HNDLR_RESULT_LIMIT_SOURCE] = + NV0000_CTRL_PFM_REQ_HNDLR_THERM_LIMIT_SRC_SBIOS_LIMITED; + } + } + else + { + pParams->result[NV0000_CTRL_PFM_REQ_HNDLR_RESULT_THERMAL_LIMIT] = 0; + if (pPfmreqhndlrData->PFMREQHNDLRSensorCache[counterId].bSupported) + { + // the SBIOS is not limiting the thermal sensor. + pParams->result[NV0000_CTRL_PFM_REQ_HNDLR_RESULT_LIMIT_SOURCE] = + NV0000_CTRL_PFM_REQ_HNDLR_THERM_LIMIT_SRC_SBIOS_UNLIMITED; + } + else + { + // the SBIOS is not supporting this thermal limit. + pParams->result[NV0000_CTRL_PFM_REQ_HNDLR_RESULT_LIMIT_SOURCE] = + NV0000_CTRL_PFM_REQ_HNDLR_THERM_LIMIT_SRC_SBIOS_NOT_SUPPORTED; + } + } + pParams->result[NV0000_CTRL_PFM_REQ_HNDLR_RESULT_MIN_LIMIT] = 1; + pParams->result[NV0000_CTRL_PFM_REQ_HNDLR_RESULT_MAX_LIMIT] = 100; + + status = NV_OK; + } + else + { + status = NV_ERR_INVALID_ARGUMENT; + } + break; + } + case NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_SET_THERM_LIMIT: + { + newLimit = pParams->input[NV0000_CTRL_PFM_REQ_HNDLR_INPUT_THERMAL_LIMIT]; + counterId = (NvU16)pParams->input[NV0000_CTRL_PFM_REQ_HNDLR_INPUT_SENSOR_INDEX]; + + if (PFM_REQ_HNDLR_VALID_LIMIT_ID(counterId)) + { + if (PFM_REQ_HNDLR_USE_SBIOS_LIMIT == newLimit) + { + // clear any override & invalidate the cached limit. + _pfmreqhndlrCancelCounterOverride(pPfmreqhndlrData, counterId, timeStamp); + } + else + { + // push the new limit into the sensor cache & mark it as overridden. + _pfmreqhndlrOverrideCounter(pPfmreqhndlrData, counterId, pParams->input[NV0000_CTRL_PFM_REQ_HNDLR_INPUT_THERMAL_LIMIT], timeStamp); + } + + if (PFM_REQ_HNDLR_LIMIT(PFM_REQ_HNDLR_TGPU_SENSOR) == counterId) + { + // get & apply the new limit. + if (NV_OK == pfmreqhndlrGetPerfSensorCounterById(pPlatformRequestHandler, + counterId, + &counterVal)) + { + NV2080_CTRL_CMD_INTERNAL_THERM_PFM_REQ_HNDLR_UPDATE_TGPU_LIMIT_PARAMS params = { 0 }; + params.targetTemp = NV_TYPES_CELSIUS_TO_NV_TEMP(newLimit);; + + status = pRmApi->Control(pRmApi, + pGpu->hInternalClient, + pGpu->hInternalSubdevice, + NV2080_CTRL_CMD_INTERNAL_THERM_PFM_REQ_HNDLR_UPDATE_TGPU_LIMIT, + ¶ms, + sizeof(params)); + + if (status != NV_OK) + { + status = NV_ERR_NOT_SUPPORTED; + break; + } + } + } + status = NV_OK; + } + else + { + status = NV_ERR_INVALID_ARGUMENT; + } + break; + } + case NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_GET_TEMP_CTRL_STATUS: + { + // + // No longer able to turn on/off the temperature controller, so + // getting status is no longer needed. + // + status = NV_ERR_NOT_SUPPORTED; + break; + } + case NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_SET_TEMP_CTRL_STATUS: + { + // No longer able to turn on/off the temperature controller + status = NV_ERR_NOT_SUPPORTED; + break; + } + case NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_GET_TEMP_CTRL_DOWN_N_DELTA: + case NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_GET_TEMP_CTRL_HOLD_DELTA: + case NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_GET_TEMP_CTRL_UP_DELTA: + case NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_GET_TEMP_CTRL_ENGAGE_DELTA: + case NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_GET_TEMP_CTRL_DISENGAGE_DELTA: + case NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_SET_TEMP_CTRL_DOWN_N_DELTA: + case NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_SET_TEMP_CTRL_HOLD_DELTA: + case NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_SET_TEMP_CTRL_UP_DELTA: + case NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_SET_TEMP_CTRL_ENGAGE_DELTA: + case NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_SET_TEMP_CTRL_DISENGAGE_DELTA: + { + status = NV_ERR_INVALID_ARGUMENT; + break; + } + case NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_GET_PERF_SENSOR: + { + status = pfmreqhndlrGetPerfSensorCounterById(pPlatformRequestHandler, + (NvU16)pParams->input[NV0000_CTRL_PFM_REQ_HNDLR_INPUT_SENSOR_INDEX], + &counterVal); + if (NV_OK == status) + { + pParams->result[NV0000_CTRL_PFM_REQ_HNDLR_RESULT_PERF_SENSOR_VALUE] = counterVal; + pParams->result[NV0000_CTRL_PFM_REQ_HNDLR_RESULT_PERF_SENSOR_AVAILABLE] = NV_TRUE; + } + else + { + pParams->result[NV0000_CTRL_PFM_REQ_HNDLR_RESULT_PERF_SENSOR_VALUE] = 0; + pParams->result[NV0000_CTRL_PFM_REQ_HNDLR_RESULT_PERF_SENSOR_AVAILABLE] = NV_FALSE; + } + break; + } + case NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_CALL_ACPI: + case NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_SET_IGPU_TURBO: + case NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_SET_TEMP_PERIOD: + case NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_GET_TEMP_PERIOD: + case NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_SET_TEMP_NUDGE_FACTOR: + case NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_GET_TEMP_NUDGE_FACTOR: + case NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_SET_TEMP_THRESHOLD_SAMPLES: + case NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_GET_TEMP_THRESHOLD_SAMPLES: + case NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_SET_TEMP_PERF_LIMITS: + case NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_GET_TEMP_PERF_LIMITS: + { + status = NV_ERR_NOT_SUPPORTED; + break; + } + case NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_SET_PM1_AVAILABLE: + { + if (!pPlatformRequestHandler->controlData.bPM1ForcedOff) + { + status = _pfmreqhndlrEnablePM1(pGpu, + pParams->input[NV0000_CTRL_PFM_REQ_HNDLR_INPUT_PM1_AVAILABLE]); + } + else + { + status = NV_ERR_NOT_SUPPORTED; + } + break; + } + case NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_GET_PM1_AVAILABLE: + { + if (!pPlatformRequestHandler->controlData.bPM1ForcedOff) + { + status = pfmreqhndlrGetPerfSensorCounterById(pPlatformRequestHandler, + PFM_REQ_HNDLR_PM1_STATE_AVAIL, + &counterVal); + if (NV_OK == status) + { + pParams->result[NV0000_CTRL_PFM_REQ_HNDLR_OUTPUT_PM1_AVAILABLE] = counterVal; + } + else + { + pParams->result[NV0000_CTRL_PFM_REQ_HNDLR_OUTPUT_PM1_AVAILABLE] = 0; + } + } + else + { + pParams->result[NV0000_CTRL_PFM_REQ_HNDLR_OUTPUT_PM1_AVAILABLE] = 0; + status = NV_ERR_NOT_SUPPORTED; + } + break; + } + case NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_GET_CPU_PACKAGE_LIMITS: + case NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_SET_CPU_PACKAGE_LIMITS: + { + NV0000_CTRL_PFM_REQ_HNDLR_CALL_ACPI_PARAMS_EX acpiParamsEx = {0}; + + // Use EX type struct -- three NvU32s for both input and output for input + acpiParamsEx.inSize = NV0000_CTRL_PFM_REQ_HNDLR_PPL_ARGS_COUNT * sizeof(NvU32); + acpiParamsEx.input[NV0000_CTRL_PFM_REQ_HNDLR_PPL_ARGS_VERSION_IDX] = + FLD_SET_DRF(0000_CTRL_PFM_REQ_HNDLR, _PPL_ARG0_VERSION, _MAJOR, _V1, + acpiParamsEx.input[NV0000_CTRL_PFM_REQ_HNDLR_PPL_ARGS_VERSION_IDX]); + acpiParamsEx.outSize = NV0000_CTRL_PFM_REQ_HNDLR_PPL_ARGS_COUNT * sizeof(NvU32); + + if (pParams->cmd == NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_SET_CPU_PACKAGE_LIMITS) + { + acpiParamsEx.pfmreqhndlrFunc = GPS_FUNC_SETPPL; + acpiParamsEx.input[NV0000_CTRL_PFM_REQ_HNDLR_PPL_ARGS_LIMIT1_IDX] = + pParams->input[NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_SET_CPU_PACKAGE_LIMITS_PL1]; + acpiParamsEx.input[NV0000_CTRL_PFM_REQ_HNDLR_PPL_ARGS_LIMIT2_IDX] = + pParams->input[NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_SET_CPU_PACKAGE_LIMITS_PL1] * 2; + } + else + { + acpiParamsEx.pfmreqhndlrFunc = GPS_FUNC_GETPPL; + } + + status = pfmreqhndlrCallACPI_EX(pGpu, &acpiParamsEx); + if (NV_OK == status) + { + // Check for major version 1 + if (FLD_TEST_DRF(0000_CTRL_PFM_REQ_HNDLR, _PPL_ARG0_VERSION, _MAJOR, _V1, + acpiParamsEx.output[NV0000_CTRL_PFM_REQ_HNDLR_PPL_ARGS_VERSION_IDX])) + { + pParams->result[NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_GET_CPU_PACKAGE_LIMITS_PL1] = + acpiParamsEx.output[NV0000_CTRL_PFM_REQ_HNDLR_PPL_ARGS_LIMIT1_IDX]; + pParams->result[NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_GET_CPU_PACKAGE_LIMITS_PL2] = + acpiParamsEx.output[NV0000_CTRL_PFM_REQ_HNDLR_PPL_ARGS_LIMIT2_IDX]; + } + else + { + status = NV_ERR_INVALID_DATA; + } + } + break; + } + case NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_GET_CPU_FREQ_LIMIT: + case NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_SET_CPU_FREQ_LIMIT: + { + NV0000_CTRL_PFM_REQ_HNDLR_CALL_ACPI_PARAMS_EX acpiParamsEx = {0}; + + // Use EX type struct -- two NvU32s for both input and output for input + acpiParamsEx.inSize = NV0000_CTRL_PFM_REQ_HNDLR_TRL_ARGS_COUNT * sizeof(NvU32); + acpiParamsEx.input[NV0000_CTRL_PFM_REQ_HNDLR_TRL_ARGS_VERSION_IDX] = + FLD_SET_DRF(0000_CTRL_PFM_REQ_HNDLR, _TRL_ARG0_VERSION, _MAJOR, _V1, + acpiParamsEx.input[NV0000_CTRL_PFM_REQ_HNDLR_TRL_ARGS_VERSION_IDX]); + acpiParamsEx.outSize = NV0000_CTRL_PFM_REQ_HNDLR_TRL_ARGS_COUNT * sizeof(NvU32); + + if (pParams->cmd == NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_SET_CPU_FREQ_LIMIT) + { + acpiParamsEx.pfmreqhndlrFunc = GPS_FUNC_SETTRL; + acpiParamsEx.input[NV0000_CTRL_PFM_REQ_HNDLR_TRL_ARGS_FREQ_MHZ_IDX] = + pParams->input[NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_SET_CPU_FREQ_LIMIT_MHZ]; + } + else + { + acpiParamsEx.pfmreqhndlrFunc = GPS_FUNC_GETTRL; + acpiParamsEx.input[NV0000_CTRL_PFM_REQ_HNDLR_TRL_ARGS_FREQ_MHZ_IDX] = 0; + } + + status = pfmreqhndlrCallACPI_EX(pGpu, &acpiParamsEx); + if (NV_OK == status) + { + // Check for major version 1 + if (FLD_TEST_DRF(0000_CTRL_PFM_REQ_HNDLR, _TRL_ARG0_VERSION, _MAJOR, _V1, + acpiParamsEx.output[NV0000_CTRL_PFM_REQ_HNDLR_TRL_ARGS_VERSION_IDX])) + { + pParams->result[NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_GET_CPU_FREQ_LIMIT_MHZ] = + acpiParamsEx.output[NV0000_CTRL_PFM_REQ_HNDLR_TRL_ARGS_FREQ_MHZ_IDX]; + } + else + { + status = NV_ERR_INVALID_DATA; + } + } + break; + } + case NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_GET_PPM: + { + // + // Mask is cached in pfmreqhndlrStateLoad and when we recieve SBIOS notification on battery transitions in AC. + // Index is cached in pfmreqhndlrStateLoad, SBIOS notification and in the workItem to set the Platform power mode. + // Return the cached values instead of making ACPI calls. + // + pParams->result[NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_GET_PPM_INDEX] = + (NvS32) pPlatformRequestHandler->ppmData.ppmIdxCurrent; + pParams->result[NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_GET_PPM_AVAILABLE_MASK] = + (NvS32) pPlatformRequestHandler->ppmData.ppmMaskCurrent; + + status = NV_OK; + break; + } + case NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_SET_PPM: + { + + // Return error if platform power modes are not supported + if (pPlatformRequestHandler->ppmData.ppmMaskCurrent == NV0000_CTRL_PFM_REQ_HNDLR_PPM_MASK_INVALID) + { + status = NV_ERR_INVALID_DATA; + break; + } + NvU8 clientPpmIdx = (NvU8) pParams->input[NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_SET_PPM_INDEX]; + + // If requested mode is same as current mode, return success + if (pPlatformRequestHandler->ppmData.ppmIdxCurrent == clientPpmIdx) + { + status = NV_OK; + break; + } + + // Return error for invalid mask or if index requested is not present in the mask + if ((clientPpmIdx == NV0000_CTRL_PFM_REQ_HNDLR_PPM_INDEX_INVALID) || + !(pPlatformRequestHandler->ppmData.ppmMaskCurrent & NVBIT(clientPpmIdx))) + { + status = NV_ERR_INVALID_DATA; + break; + } + + status = NV_ERR_BUSY_RETRY; + if (!pPlatformRequestHandler->ppmData.bWorkItemPending) + { + OBJOS *pOS = GPU_GET_OS(pGpu); + pPlatformRequestHandler->ppmData.ppmIdxRequested = clientPpmIdx; + // Create a workItem to change Platform Power Mode + status = pOS->osQueueWorkItem(pGpu, _pfmreqhndlrUpdatePlatformPowerModeWorkItem, NULL); + if (status == NV_OK) + { + // Queing workitem succeeded, mark it as pending. + pPlatformRequestHandler->ppmData.bWorkItemPending = NV_TRUE; + } + } + break; + } + default: + { + NV_PRINTF(LEVEL_ERROR, "Unknown request %x\n", pParams->cmd); + status = NV_ERR_NOT_SUPPORTED; + break; + } + } + return status; +} + +NV_STATUS +cliresCtrlCmdSystemPfmreqhndlrGetFrmData_IMPL +( + RmClientResource *pRmCliRes, + NV0000_CTRL_SYSTEM_PFM_REQ_HNDLR_GET_FRM_DATA_PARAMS *pParams +) +{ + OBJSYS *pSys = SYS_GET_INSTANCE(); + PlatformRequestHandler *pPlatformRequestHandler = SYS_GET_PFM_REQ_HNDLR(pSys); + NvU8 logicalBufferStart; + NvU8 block0Size; + + if (NULL==pPlatformRequestHandler) + { + return NV_ERR_NOT_SUPPORTED; + } + + pParams->nextSampleNumber = pPlatformRequestHandler->frmData.nextSampleNumber; + + // logical buffer starts at the oldest entry + logicalBufferStart = ((pPlatformRequestHandler->frmData.nextSampleNumber) % NV0000_CTRL_SYSTEM_PFM_REQ_HNDLR_FRM_DATA_SAMPLE_SIZE); + + // Block0 goes from the logical start of the buffer to the physical end of the buffer + block0Size = (NV0000_CTRL_SYSTEM_PFM_REQ_HNDLR_FRM_DATA_SAMPLE_SIZE - logicalBufferStart); + + portMemCopy(&(pParams->samples[0]), (sizeof(pPlatformRequestHandler->frmData.samples[0]) * block0Size), &(pPlatformRequestHandler->frmData.samples[logicalBufferStart]), (sizeof(pPlatformRequestHandler->frmData.samples[0]) * block0Size)); + + // + // if the logical buffer is wrapping from the physical end of the buffer back to the beginning, + // copy the logical end block to the end of the output buffer + // + if (0 != logicalBufferStart) + { + portMemCopy(&(pParams->samples[block0Size]), (sizeof(pPlatformRequestHandler->frmData.samples[0]) * (logicalBufferStart)), &(pPlatformRequestHandler->frmData.samples[0]), (sizeof(pPlatformRequestHandler->frmData.samples[0]) * (logicalBufferStart))); + } + + return NV_OK; +} + +NV_STATUS +cliresCtrlCmdSystemPfmreqhndlrSetFrmData_IMPL +( + RmClientResource *pRmCliRes, + NV0000_CTRL_SYSTEM_PFM_REQ_HNDLR_SET_FRM_DATA_PARAMS *pParams +) +{ + OBJSYS *pSys = SYS_GET_INSTANCE(); + PlatformRequestHandler *pPlatformRequestHandler = SYS_GET_PFM_REQ_HNDLR(pSys); + NvU8 sampleNumber = 0; + + if (NULL == pPlatformRequestHandler) + { + return NV_ERR_NOT_SUPPORTED; + } + + sampleNumber = ((pPlatformRequestHandler->frmData.nextSampleNumber) % NV0000_CTRL_SYSTEM_PFM_REQ_HNDLR_FRM_DATA_SAMPLE_SIZE); + pPlatformRequestHandler->frmData.samples[sampleNumber] = pParams->sampleData; + pPlatformRequestHandler->frmData.samples[sampleNumber].sampleNumber = pPlatformRequestHandler->frmData.nextSampleNumber; + pPlatformRequestHandler->frmData.nextSampleNumber++; + + return NV_OK; +} + +NV_STATUS +cliresCtrlCmdSystemPfmreqhndlrCallAcpi_IMPL +( + RmClientResource *pRmCliRes, + NV0000_CTRL_SYSTEM_PFM_REQ_HNDLR_CALL_ACPI_PARAMS *pParams +) +{ + NV_STATUS status; + OBJSYS *pSys = SYS_GET_INSTANCE(); + PlatformRequestHandler *pPlatformRequestHandler = SYS_GET_PFM_REQ_HNDLR(pSys); + OBJGPU *pGpu; + NV0000_CTRL_PFM_REQ_HNDLR_CALL_ACPI_PARAMS acpiParams; + + if (NULL == pPlatformRequestHandler) + { + return NV_ERR_NOT_SUPPORTED; + } + pGpu = pfmreqhndlrGetGpu(pPlatformRequestHandler); + if (NULL == pGpu) + { + return NV_ERR_NOT_SUPPORTED; + } + + portMemSet((void *) &acpiParams, 0, sizeof(NV0000_CTRL_PFM_REQ_HNDLR_CALL_ACPI_PARAMS)); + acpiParams.ctrl.cmd = pParams->cmd; + acpiParams.ctrl.input = pParams->input; + acpiParams.output.pBuffer = (NvU8*)&(pParams->result); + acpiParams.output.bufferSz = sizeof(pParams->result); + + status = pfmreqhndlrCallACPI(pGpu, &acpiParams); + + if (NV_OK != status) + { + return status; + } + if (0 == acpiParams.output.bufferSz) + { + // we used the result field, not the buffer, copy the results to the buffer + // based on the command type. + switch(acpiParams.ctrl.cmd) + { + case NV0000_CTRL_PFM_REQ_HNDLR_CALL_ACPI_CMD_SUPPORT: + { + pParams->result[0] = acpiParams.output.result[0]; + pParams->result[1] = acpiParams.output.result[1]; + pParams->resultSz = sizeof(acpiParams.output.result[0]) * 2; + break; + } + case NV0000_CTRL_PFM_REQ_HNDLR_CALL_ACPI_CMD_PCONTROL: + case NV0000_CTRL_PFM_REQ_HNDLR_CALL_ACPI_CMD_PSHARESTATUS: + { + pParams->result[0] = acpiParams.output.result[0]; + pParams->resultSz = sizeof(acpiParams.output.result[0]); + break; + } + // anything left is either a command that should have used a buffer, or something we don't recognize. + default: + { + pParams->resultSz = 0; + break; + } + } + } + else + { + pParams->resultSz = acpiParams.output.bufferSz; + } + return status; +} + +NV_STATUS +pfmreqhndlrCallACPI +( + OBJGPU *pGpu, + NV0000_CTRL_PFM_REQ_HNDLR_CALL_ACPI_PARAMS *pParams +) +{ + OBJSYS *pSys = SYS_GET_INSTANCE(); + PlatformRequestHandler *pPlatformRequestHandler = SYS_GET_PFM_REQ_HNDLR(pSys); + NV_STATUS status = NV_OK; + NvU32 rc; + NvU16 paramSize; + + switch (pParams->ctrl.cmd) + { + case NV0000_CTRL_PFM_REQ_HNDLR_CALL_ACPI_CMD_SUPPORT: + { + // no input parameters + pParams->output.result[0] = 0; + pParams->output.result[1] = 0; + pParams->output.bufferSz = 0; + paramSize = sizeof(pParams->output.result); + + if ((rc = osCallACPI_DSM(pGpu, + pPlatformRequestHandler->dsmVersion, + GPS_FUNC_SUPPORT, + pParams->output.result, + ¶mSize)) != NV_OK) + { + NV_PRINTF(LEVEL_ERROR, + "Unable to retrieve PFM_REQ_HNDLR_SUPPORT. Possibly not supported/enabled by " + "CPU/ACPI? rc = %x\n", rc); + status = NV_ERR_NOT_SUPPORTED; + RMTRACE_SBIOS (_ACPI_DSM_ERROR, pGpu->gpuId, pPlatformRequestHandler->dsmVersion, GPS_FUNC_SUPPORT, 0, 0, 0, 0, 0); + break; + } + RMTRACE_SBIOS (_ACPI_DSM_METHOD, pGpu->gpuId, pPlatformRequestHandler->dsmVersion, GPS_FUNC_SUPPORT, pParams->output.result[0], pParams->output.result[1], 0, 0, 0); + break; + } + case NV0000_CTRL_PFM_REQ_HNDLR_CALL_ACPI_CMD_PCONTROL: + { + pParams->output.result[0] = pParams->ctrl.input; + paramSize = sizeof(pParams->output.result[0]); + pParams->output.bufferSz = 0; + + if ((rc = osCallACPI_DSM(pGpu, + pPlatformRequestHandler->dsmVersion, + GPS_FUNC_PCONTROL, + (NvU32 *) &pParams->output.result[0], + ¶mSize)) != NV_OK) + { + NV_PRINTF(LEVEL_ERROR, + "Unable to retrieve PFM_REQ_HNDLR_PCONTROL. Possibly not supported/enabled by " + "CPU/ACPI? rc = %x\n", rc); + status = NV_ERR_NOT_SUPPORTED; + RMTRACE_SBIOS (_ACPI_DSM_ERROR, pGpu->gpuId, pPlatformRequestHandler->dsmVersion, GPS_FUNC_PCONTROL, 0, 0, 0, 0, 0); + break; + } + RMTRACE_SBIOS (_ACPI_DSM_METHOD, pGpu->gpuId, pPlatformRequestHandler->dsmVersion, GPS_FUNC_PCONTROL, pParams->ctrl.input, pParams->output.result[0], 0, 0, 0); + break; + } + case NV0000_CTRL_PFM_REQ_HNDLR_CALL_ACPI_CMD_PSHARESTATUS: + { + pParams->output.result[0] = pParams->ctrl.input; + paramSize = sizeof(pParams->output.result[0]); + pParams->output.bufferSz = 0; + + if ((rc = osCallACPI_DSM(pGpu, + pPlatformRequestHandler->dsmVersion, + GPS_FUNC_PSHARESTATUS, + &pParams->output.result[0], + ¶mSize)) != NV_OK) + { + NV_PRINTF(LEVEL_ERROR, + "Unable to retrieve PFM_REQ_HNDLR_PSHARESTATUS. Possibly not supported/enabled by" + " CPU/ACPI? rc = %x\n", rc); + status = NV_ERR_NOT_SUPPORTED; + RMTRACE_SBIOS (_ACPI_DSM_ERROR, pGpu->gpuId, pPlatformRequestHandler->dsmVersion, GPS_FUNC_PSHARESTATUS, 0, 0, 0, 0, 0); + break; + } + RMTRACE_SBIOS (_ACPI_DSM_METHOD, pGpu->gpuId, pPlatformRequestHandler->dsmVersion, GPS_FUNC_PSHARESTATUS, pParams->ctrl.input, pParams->output.result[0], 0, 0, 0); + break; + } + case NV0000_CTRL_PFM_REQ_HNDLR_CALL_ACPI_CMD_PSHAREPARAMS: + { + if (sizeof(PFM_REQ_HNDLR_PSHAREDATA) > pParams->output.bufferSz) + { + NV_PRINTF(LEVEL_ERROR, "buffer to small to hold output.\n"); + status = NV_ERR_NOT_SUPPORTED; + break; + } + *((NvU32*)(pParams->output.pBuffer)) = pParams->ctrl.input; + + if ((rc = osCallACPI_DSM(pGpu, + pPlatformRequestHandler->dsmVersion, + GPS_FUNC_PSHAREPARAMS, + (NvU32 *) pParams->output.pBuffer, + &pParams->output.bufferSz)) != NV_OK) + { + NV_PRINTF(LEVEL_ERROR, + "Unable to retrieve PFM_REQ_HNDLR_PSHAREPARAMS. Possibly not supported/enabled by" + " CPU/ACPI? rc = %x\n", rc); + status = NV_ERR_NOT_SUPPORTED; + RMTRACE_SBIOS (_ACPI_DSM_ERROR, pGpu->gpuId, pPlatformRequestHandler->dsmVersion, GPS_FUNC_PSHAREPARAMS, 0, 0, 0, 0, 0); + break; + } + RMTRACE_SBIOS (_ACPI_DSM_METHOD, pGpu->gpuId, pPlatformRequestHandler->dsmVersion, GPS_FUNC_PSHAREPARAMS, ((NvU32 *) pParams->output.pBuffer)[0], ((NvU32 *) pParams->output.pBuffer)[3], ((NvU32 *) pParams->output.pBuffer)[6], 0, 0); + break; + } + case NV0000_CTRL_PFM_REQ_HNDLR_CALL_ACPI_CMD_GETEDPPLIMIT: + { + pParams->output.result[0] = pParams->ctrl.input; + paramSize = sizeof(pParams->output.result[0]); + + if ((rc = osCallACPI_DSM(pGpu, + pPlatformRequestHandler->dsmVersion, + GPS_FUNC_GETEDPPLIMIT, + &pParams->output.result[0], + ¶mSize)) != NV_OK) + { + NV_PRINTF(LEVEL_ERROR, + "Unable to retrieve PFM_REQ_HNDLR_FUNC_GETEDPPLIMIT. Possibly not supported/enabled by " + "ACPI? rc = %x\n", rc); + status = NV_ERR_NOT_SUPPORTED; + RMTRACE_SBIOS (_ACPI_DSM_ERROR, pGpu->gpuId, pPlatformRequestHandler->dsmVersion, GPS_FUNC_GETEDPPLIMIT, 0, 0, 0, 0, 0); + break; + } + RMTRACE_SBIOS (_ACPI_DSM_METHOD, pGpu->gpuId, pPlatformRequestHandler->dsmVersion, GPS_FUNC_GETEDPPLIMIT, pParams->output.result[0], pParams->output.result[1], 0, 0, 0); + break; + } + case NV0000_CTRL_PFM_REQ_HNDLR_CALL_ACPI_CMD_SETEDPPLIMITINFO: + { + if ((rc = osCallACPI_DSM(pGpu, + pPlatformRequestHandler->dsmVersion, + GPS_FUNC_SETEDPPLIMITINFO, + (NvU32 *) pParams->output.pBuffer, + &pParams->output.bufferSz)) != NV_OK) + { + NV_PRINTF(LEVEL_ERROR, + "Unable to retrieve PFM_REQ_HNDLR_FUNC_SETEDPPLIMITINFO. Possibly not supported/enabled by " + "ACPI? rc = %x\n", rc); + status = NV_ERR_NOT_SUPPORTED; + RMTRACE_SBIOS (_ACPI_DSM_ERROR, pGpu->gpuId, pPlatformRequestHandler->dsmVersion, GPS_FUNC_SETEDPPLIMITINFO, 0, 0, 0, 0, 0); + break; + } + RMTRACE_SBIOS (_ACPI_DSM_METHOD, pGpu->gpuId, pPlatformRequestHandler->dsmVersion, GPS_FUNC_SETEDPPLIMITINFO, pParams->output.result[0], pParams->output.result[1], 0, 0, 0); + break; + } + default: + { + NV_PRINTF(LEVEL_ERROR, "Unknown request %x\n", + DRF_VAL(0000_CTRL_PFM_REQ_HNDLR, _CALL_ACPI, _CMD_TYPE, pParams->ctrl.cmd)); + status = NV_ERR_NOT_SUPPORTED; + break; + } + } + return status; +} + +/*! + * EX version of pfmreqhndlrCallACPI used only for PPL and TRL calls, which require + * a greater number of input args. + * + * @param[in] pGpu GPU object pointer + * @param[in, out] pParams Call parameters + * + * Returns NV_OK if handled successfully; otherwise propogates errors. + */ +NV_STATUS +pfmreqhndlrCallACPI_EX +( + OBJGPU *pGpu, + NV0000_CTRL_PFM_REQ_HNDLR_CALL_ACPI_PARAMS_EX *pParams +) +{ + NvU32 idx; + NvU16 paramSize; + NV_STATUS status; + OBJSYS *pSys = SYS_GET_INSTANCE(); + PlatformRequestHandler *pPlatformRequestHandler = SYS_GET_PFM_REQ_HNDLR(pSys); + + for (idx = 0; idx < NV0000_CTRL_PFM_REQ_HNDLR_CALL_ACPI_PARAMS_EX_MAX_SZ; ++idx) + { + pParams->output[idx] = pParams->input[idx]; + } + paramSize = pParams->outSize; + + if ((status = osCallACPI_DSM(pGpu, + pPlatformRequestHandler->dsmVersion, + pParams->pfmreqhndlrFunc, + pParams->output, + ¶mSize)) != NV_OK) + { + status = NV_ERR_NOT_SUPPORTED; + } + return status; +} + +// +// pfmreqhndlrInitSensors +// +// This function initialises the PLATFORM REQUEST HANDLER sensor data. +// it initializes all the data, and determines which sensors are available for sampling. +// +NV_STATUS +pfmreqhndlrInitSensors +( + PlatformRequestHandler *pPlatformRequestHandler +) +{ + NV_STATUS status = NV_OK; + OBJGPU *pGpu = NULL; + NvU32 timeStamp = 0; + PFM_REQ_HNDLR_PSHAREDATA *pPShareParams = NULL; + PFM_REQ_HNDLR_SENSOR_DATA *pPfmreqhndlrData; + NV0000_CTRL_PFM_REQ_HNDLR_CALL_ACPI_PARAMS + acpiParams; + + NV_ASSERT_OR_RETURN(NULL != pPlatformRequestHandler, NV_ERR_INVALID_REQUEST); + + pGpu = pfmreqhndlrGetGpu(pPlatformRequestHandler); + NV_ASSERT_OR_RETURN(NULL != pGpu, NV_ERR_INVALID_REQUEST); + + pPfmreqhndlrData = &(pPlatformRequestHandler->sensorData); + + // init the PLATFORM REQUEST HANDLER data cache. + portMemSet((void *)pPfmreqhndlrData, 0, sizeof(PFM_REQ_HNDLR_SENSOR_DATA)); + + // + // Initialize a logical sw version based of ACPI dsm version + // + if ((pPlatformRequestHandler->getProperty(pPlatformRequestHandler, PDB_PROP_PFMREQHNDLR_IS_PLATFORM_LEGACY)) || + (pPlatformRequestHandler->dsmVersion == ACPI_DSM_FUNCTION_GPS_2X)) + { + pPfmreqhndlrData->PFMREQHNDLRACPIData.acpiVersionSw = + NV0000_CTRL_PFM_REQ_HNDLR_ACPI_REVISION_SW_2X; + } + + // Cache the current timestamp + timeStamp = _pfmreqhndlrGetTimeStamp(pPlatformRequestHandler); + + pPfmreqhndlrData->counterHoldPeriod = + PFM_REQ_HNDLR_DEFAULT_COUNTER_HOLD_PERIOD_MS; + + // + // init the PSHARESTATUS ACPI cache. + // set up the defaults + // + pPfmreqhndlrData->PFMREQHNDLRACPIData.bPfmReqHndlrSupported = NV_FALSE; + + // + // Check if PLATFORM REQUEST HANDLER is supported on this platform + // determine if we can call the PLATFORM REQUEST HANDLER ACPI call. + // + portMemSet((void *) &acpiParams, 0, sizeof(NV0000_CTRL_PFM_REQ_HNDLR_CALL_ACPI_PARAMS)); + acpiParams.ctrl.cmd = NV0000_CTRL_PFM_REQ_HNDLR_CALL_ACPI_CMD_SUPPORT; + acpiParams.ctrl.input = 0; + acpiParams.output.pBuffer = NULL; + acpiParams.output.bufferSz = 0; + if (NV_OK == pfmreqhndlrCallACPI(pGpu, &acpiParams)) + { + // Set up all the control flags based on all the supported subfunctions + status = _pfmreqhndlrSetSupportedStatesFromAcpiParams(pGpu, + pPlatformRequestHandler, acpiParams.output.result[1]); + if (NV_OK != status) + { + NV_ASSERT_FAILED("Get all the supported PlatformRequestHandler subfunctions"); + return status; + } + } + if (pPfmreqhndlrData->PFMREQHNDLRACPIData.bPfmReqHndlrSupported) + { + // call PSHARESTATUS to get the initial values. + _pfmreqhndlrCallPshareStatus(pPlatformRequestHandler, NV_TRUE); + + // PShare param is available, determine which sensors it is reporting. + pPShareParams = portMemAllocNonPaged(sizeof(PFM_REQ_HNDLR_PSHAREDATA)); + if (NULL != pPShareParams) + { + portMemSet((void *)pPShareParams, 0, sizeof(PFM_REQ_HNDLR_PSHAREDATA)); + portMemSet((void *)&acpiParams, 0, sizeof(NV0000_CTRL_PFM_REQ_HNDLR_CALL_ACPI_PARAMS)); + + acpiParams.ctrl.cmd = NV0000_CTRL_PFM_REQ_HNDLR_CALL_ACPI_CMD_PSHAREPARAMS; + acpiParams.ctrl.input = + DRF_DEF(0000_CTRL_PFM_REQ_HNDLR, _PSHARE_PARAMS, _STATUS_QUERY_TYPE, _SUPPORTED_FIELDS) | + DRF_DEF(0000_CTRL_PFM_REQ_HNDLR, _PSHARE_PARAMS, _STATUS_TGPU, _TRUE) | + DRF_DEF(0000_CTRL_PFM_REQ_HNDLR, _PSHARE_PARAMS, _STATUS_PPMD, _TRUE); + acpiParams.output.pBuffer = (void *) pPShareParams; + acpiParams.output.bufferSz = sizeof(PFM_REQ_HNDLR_PSHAREDATA); + + if (NV_OK == pfmreqhndlrCallACPI(pGpu, &acpiParams)) + { + // Determine the SBP(PFMREQHNDLR) version on this platform + // save the version number + pPfmreqhndlrData->version = pPShareParams->ulVersion; + + // save a mask of available counters + pPfmreqhndlrData->PFMREQHNDLRShareParamsAvailMask = pPShareParams->status & + (DRF_DEF(0000_CTRL_PFM_REQ_HNDLR, _PSHARE_PARAMS, _STATUS_TGPU, _TRUE) | + DRF_DEF(0000_CTRL_PFM_REQ_HNDLR, _PSHARE_PARAMS, _STATUS_PPMD, _TRUE)); + + _pfmreqhndlrInitSupportedCounter(pPfmreqhndlrData, PFM_REQ_HNDLR_AVAIL_SENSOR_MSK, NV_FALSE, timeStamp); + _pfmreqhndlrUpdateCounter(pPfmreqhndlrData, PFM_REQ_HNDLR_AVAIL_SENSOR_MSK, NV_TRUE, pPfmreqhndlrData->PFMREQHNDLRShareParamsAvailMask, timeStamp); + + // check each counter & if available, flag current value, limit, & period as available. + if (0 != (DRF_VAL(0000_CTRL_PFM_REQ_HNDLR, _PSHARE_PARAMS_STATUS, _TGPU, pPShareParams->status))) + { + _pfmreqhndlrInitSupportedCounter(pPfmreqhndlrData, PFM_REQ_HNDLR_LIMIT(PFM_REQ_HNDLR_TGPU_SENSOR), NV_TRUE, timeStamp); + _pfmreqhndlrInitSupportedCounter(pPfmreqhndlrData, PFM_REQ_HNDLR_PERIOD(PFM_REQ_HNDLR_TGPU_SENSOR), NV_FALSE, timeStamp); + _pfmreqhndlrUpdateCounter(pPfmreqhndlrData, PFM_REQ_HNDLR_PERIOD(PFM_REQ_HNDLR_TGPU_SENSOR), NV_TRUE, pPShareParams->tGpu, timeStamp); + } + if (PFM_REQ_HNDLR_IS_ACPI_VERSION_SW_2X(pPlatformRequestHandler) && + (0 != (DRF_VAL(0000_CTRL_PFM_REQ_HNDLR, _PSHARE_PARAMS_STATUS, _PPMD, pPShareParams->status)))) + { + // Invalidate Platform Power Mode cache on boot + _pfmreqhndlrPlatformPowerModeStateReset(pPlatformRequestHandler); + + // Init PPMD sensor if this is enabled + _pfmreqhndlrInitSupportedCounter(pPfmreqhndlrData, PFM_REQ_HNDLR_LIMIT(PFM_REQ_HNDLR_PPMD_SENSOR), NV_TRUE, timeStamp); + + // Sample the PPMD counter from init time + _pfmreqhndlrUpdatePpmdLimit(pPlatformRequestHandler, pGpu, NV_TRUE); + } + } + portMemFree(pPShareParams); + } + + } + + // as long as there is an PlatformRequestHandler object, these counters should always be available. + // The following counters are non-Volatile, they are being updated as the corresponding functions change, + // so they do not need to be sampled on request for a current value. + _pfmreqhndlrInitSupportedCounter(pPfmreqhndlrData, PFM_REQ_HNDLR_VPS_PS20_SUPPORT, NV_TRUE, timeStamp); + + // The following counters are volatile, and need to be sampled on request for a current value. + _pfmreqhndlrInitSupportedCounter(pPfmreqhndlrData, PFM_REQ_HNDLR_PM1_STATE_AVAIL, NV_TRUE, timeStamp); + + // The following counters are dynamically controlled by the Thermal controller. + // they are currently handled as volatile counters, but could be changed to non-volatile counters + // if TC is modified to push the new values to PFMREQHNDLR when they change. + // (note with the current policy of seperating TC & PFMREQHNDLR this is unlikely) + _pfmreqhndlrInitSupportedCounter(pPfmreqhndlrData, PFM_REQ_HNDLR_TC_ENABLE, NV_TRUE, timeStamp); + + return status; +} + +/*! + * Set/update the value of a specific perf-counter (denoted by id). + * + * @param[in] pPlatformRequestHandler *PlatformRequestHandler pointer + * @param[in] id Identifier of counter to update + * @param[in] value New value to set for the counter + * + * @return NV_OK Upon successful update + * @return NV_ERR_INVALID_ARGUMENT Invalid counter id + * @return NV_ERR_INVALID_REQUEST + * Returned if the provided PlatformRequestHandler pointer was NULL or if the corresponding + * OBJGPU object could not be found. + */ +NV_STATUS +pfmreqhndlrUpdatePerfCounter +( + PlatformRequestHandler *pPlatformRequestHandler, + NvU32 id, + NvU32 value +) +{ + OBJGPU *pGpu = NULL; + PFM_REQ_HNDLR_SENSOR_DATA *pPfmreqhndlrData; + NvU32 timeStamp; + + // is the Id within range? + if (id >= PFM_REQ_HNDLR_NUM_COUNTERS) + { + return NV_ERR_INVALID_ARGUMENT; + } + + if (NULL == pPlatformRequestHandler) + { + NV_ASSERT(pPlatformRequestHandler); + return NV_ERR_INVALID_REQUEST; + } + + pGpu = pfmreqhndlrGetGpu(pPlatformRequestHandler); + if (NULL == pGpu) + { + return NV_ERR_INVALID_REQUEST; + } + // determine the current ms timestamp. + timeStamp = _pfmreqhndlrGetTimeStamp(pPlatformRequestHandler); + + pPfmreqhndlrData = &(pPlatformRequestHandler->sensorData); + + _pfmreqhndlrUpdateCounter(pPfmreqhndlrData, id, NV_TRUE, value, timeStamp); + + return NV_OK; +} + +// +// PfmreqhndlrSampleCounter +// +// This function determines if it is appropriate to update the specified counter & does so if it is. +// Note that this function contains all the code specific to the sampling of each counter. +// +NV_STATUS +pfmreqhndlrSampleCounter +( + PlatformRequestHandler *pPlatformRequestHandler, + NvU32 id, + NvU32 timeStamp +) +{ + NV_STATUS status = NV_ERR_NOT_SUPPORTED; + PFM_REQ_HNDLR_SENSOR_DATA *pPfmreqhndlrData = &(pPlatformRequestHandler->sensorData); + PFM_REQ_HNDLR_SENSOR_COUNTER *pCounter = &(pPfmreqhndlrData->PFMREQHNDLRSensorCache[id]); + OBJGPU *pGpu = pfmreqhndlrGetGpu(pPlatformRequestHandler); + NvBool bPM1Available = NV_TRUE; + + NV_ASSERT_OR_RETURN(NULL != pPlatformRequestHandler, NV_ERR_INVALID_REQUEST); + + if (0 == timeStamp) + { + timeStamp = _pfmreqhndlrGetTimeStamp(pPlatformRequestHandler); + } + + // check if we can sample the counter. + // (marked available & can be sampled now.) + if (pCounter->bSupported + && (pCounter->bInvalid || ((timeStamp - pCounter->lastSampled) >= pCounter->minInterval))) + { + // Sample the requested counter. + switch (id) + { + case PFM_REQ_HNDLR_LIMIT(PFM_REQ_HNDLR_TGPU_SENSOR): + case PFM_REQ_HNDLR_LIMIT(PFM_REQ_HNDLR_PPMD_SENSOR): + { + status = _pfmreqhndlrSampleSensorLimit(pPlatformRequestHandler, id, timeStamp); + break; + } + case PFM_REQ_HNDLR_PM1_STATE_AVAIL: + { + if (!pPlatformRequestHandler->controlData.bPM1ForcedOff) + { + if (pfmreqhndlrHandleCheckPM1Available(pPlatformRequestHandler, pGpu, &bPM1Available) == NV_OK) + { + _pfmreqhndlrUpdateCounter(pPfmreqhndlrData, PFM_REQ_HNDLR_PM1_STATE_AVAIL, NV_TRUE, (NvU32)bPM1Available, timeStamp); + status = NV_OK; + } + } + //If PM1 is forced off or Boost Clocks not available + else + { + status = NV_ERR_NOT_SUPPORTED; + } + break; + } + case PFM_REQ_HNDLR_VPS_PS20_SUPPORT: + { + _pfmreqhndlrUpdateCounter(pPfmreqhndlrData, PFM_REQ_HNDLR_VPS_PS20_SUPPORT, NV_TRUE, pPlatformRequestHandler->vPstateCache.bVpsPs20Supported, timeStamp); + } + case PFM_REQ_HNDLR_TC_ENABLE: + { + _pfmreqhndlrUpdateCounter(pPfmreqhndlrData, PFM_REQ_HNDLR_TC_ENABLE, NV_TRUE, NV_TRUE, timeStamp); + break; + } + default: + { + break; + } + } + } + return status; +} + +/*! + * @brief Retrieves the requested counter and returns it if available. + * + * @param[in] pPlatformRequestHandler *PlatformRequestHandler pointer + * @param[in] counterId ID of the requested counter + * @param[out] pCounterVal buffer to hold value of requested counter + * + * @return NV_ERR_INVALID_POINTER NULL pointer passed + * @return NV_ERR_NOT_SUPPORTED various failures (TODO) + * @return NV_ERR_INVALID_DATA counter is not available + * @return NV_OK counter successfully retrieved + */ +NV_STATUS +pfmreqhndlrGetPerfSensorCounterById_IMPL +( + PlatformRequestHandler *pPlatformRequestHandler, + NvU16 counterId, + NvU32 *pCounterVal +) +{ + OBJSYS *pSys = SYS_GET_INSTANCE(); + OBJGPU *pGpu = NULL; + OBJOS *pOs = NULL; + PPFM_REQ_HNDLR_SENSOR_DATA pPfmreqhndlrData = &(pPlatformRequestHandler->sensorData); + NV_STATUS status = NV_ERR_INVALID_DATA; + NvU32 timeStamp; + + NV_ASSERT_OR_RETURN(NULL != pCounterVal, NV_ERR_INVALID_POINTER); + NV_ASSERT_OR_RETURN(NULL != pPlatformRequestHandler, NV_ERR_NOT_SUPPORTED); + + *pCounterVal = 0; + + pGpu = pfmreqhndlrGetGpu(pPlatformRequestHandler); + if(pGpu == NULL){ + return NV_ERR_NOT_SUPPORTED; + } + + pOs = SYS_GET_OS(pSys); + if(pOs == NULL){ + return NV_ERR_NOT_SUPPORTED; + } + + timeStamp = _pfmreqhndlrGetTimeStamp(pPlatformRequestHandler); + + // Is the Id within range? + if (counterId >= PFM_REQ_HNDLR_NUM_COUNTERS) + { + NV_PRINTF(LEVEL_ERROR, + "Invalid counter Id specified = %d.\n", + counterId); + DBG_BREAKPOINT(); + status = NV_ERR_NOT_SUPPORTED; + goto pfmreqhndlrGetPerfSensorCounterById_IMPL_exit; + } + // is the counter available? + if ((!pPfmreqhndlrData->PFMREQHNDLRSensorCache[counterId].bSupported) && + (!pPfmreqhndlrData->PFMREQHNDLRSensorCache[counterId].bVolatile)) + { + goto pfmreqhndlrGetPerfSensorCounterById_IMPL_exit; + } + + // Has the counter gone stale since the last sampling? + if (_pfmreqhndlrIsCacheEntryStale(pPfmreqhndlrData, counterId, timeStamp)) + { + // sample the counter + if (PFM_REQ_HNDLR_IS_ACPI_VERSION_SW_2X(pPlatformRequestHandler)) + { + // 2X path + status = pfmreqhndlrSampleCounter(pPlatformRequestHandler, counterId, timeStamp); + if (status != NV_OK) + { + if (status == NV_ERR_NOT_SUPPORTED) + { + // OK to sample unsupported counters (and fall through). + status = NV_OK; + } + else + { + // Fail for any other error code (and bail) + NV_PRINTF(LEVEL_ERROR, + "Sampling counter failed for counter id = %d.\n", + counterId); + DBG_BREAKPOINT(); + goto pfmreqhndlrGetPerfSensorCounterById_IMPL_exit; + } + } + } + else + { + // 1X path + pfmreqhndlrSampleCounter(pPlatformRequestHandler, counterId, timeStamp); + } + } + // + // NOTE per spec, some counters may be reported as available, + // but may not be available under some conditions. + // I.E. pshare params may report a counter as available when supported fields are queried, + // but the limits are only available if the SBIOS wants that particular sensor limited. + // so these sensors may be intermittently available. + // to check for this case, check to see if the counter is still stale. + // + if (!_pfmreqhndlrIsCacheEntryStale(pPfmreqhndlrData, counterId, timeStamp) && + !pPfmreqhndlrData->PFMREQHNDLRSensorCache[counterId].bInvalid) + { + // the counter is not stale, + // copy it to the output + *pCounterVal = pPfmreqhndlrData->PFMREQHNDLRSensorCache[counterId].value; + status = NV_OK; + goto pfmreqhndlrGetPerfSensorCounterById_IMPL_exit; + } + +pfmreqhndlrGetPerfSensorCounterById_IMPL_exit: + return status; +} + +NV_STATUS +pfmreqhndlrHandleStatusChangeEvent +( + PlatformRequestHandler *pPlatformRequestHandler, + OBJGPU *pGpu +) +{ + NV_STATUS status = NV_OK; + NvU32 data = 0; + NvBool bIsPctrlSupported = NV_TRUE; + + NV_ASSERT_OR_RETURN(NULL != pPlatformRequestHandler, NV_ERR_INVALID_REQUEST); + + // get the latest pshare status + status = _pfmreqhndlrCallPshareStatus(pPlatformRequestHandler, NV_FALSE); + if (status != NV_OK) + { + NV_ASSERT_OK_FAILED("PshareStatus", status); + } + + if (PFM_REQ_HNDLR_IS_ACPI_VERSION_SW_2X(pPlatformRequestHandler)) + { + // Additionally if PCONTROL subfunction is supported call it + NV0000_CTRL_PFM_REQ_HNDLR_CALL_ACPI_PARAMS acpiParams; + + portMemSet((void *) &acpiParams, 0, sizeof(NV0000_CTRL_PFM_REQ_HNDLR_CALL_ACPI_PARAMS)); + acpiParams.ctrl.cmd = NV0000_CTRL_PFM_REQ_HNDLR_CALL_ACPI_CMD_SUPPORT; + acpiParams.ctrl.input = 0; + acpiParams.output.pBuffer = NULL; + acpiParams.output.bufferSz = 0; + status = pfmreqhndlrCallACPI(pGpu, &acpiParams); + if (status != NV_OK) + { + NV_ASSERT_OK_FAILED("supported subfunction", status); + goto pfmreqhndlrHandleStatusChangeEvent_exit; + } + if (0 == (DRF_VAL(0000_CTRL_PFM_REQ_HNDLR, _SUPPORTED, _PCONTROL_AVAIL, acpiParams.output.result[1]))) + { + // PCONTTOL is not supported on 2X, can be hard coded + bIsPctrlSupported = NV_FALSE; + } + } + + if (bIsPctrlSupported) + { + status = pfmreqhndlrPcontrol(pPlatformRequestHandler, data, NV_TRUE); + if (status != NV_OK) + { + NV_ASSERT_FAILED("Pcontrol command"); + goto pfmreqhndlrHandleStatusChangeEvent_exit; + } + } + +pfmreqhndlrHandleStatusChangeEvent_exit: + return status; +} + +/*! + * Helper routine to check PM1 Available Status + * + * @param[in] pPlatformRequestHandler *PlatformRequestHandler object pointer + * @param[in] pGpu GPU object pointer + * @param[out] bIsPm1Available Status of PM1 Availability + * + * @return NV_OK if RMAPI call was succesful. + * @return bubble up errors from called RMAPI + */ + +NV_STATUS +pfmreqhndlrHandleCheckPM1Available_IMPL +( + PlatformRequestHandler *pPlatformRequestHandler, + OBJGPU *pGpu, + NvBool *pbPM1Available +) +{ + NV_STATUS status = NV_ERR_GENERIC; + NV2080_CTRL_CMD_INTERNAL_PERF_PFM_REQ_HNDLR_GET_PM1_STATE_PARAMS params = { 0 }; + RM_API *pRmApi = GPU_GET_PHYSICAL_RMAPI(pGpu); + + params.flag = NV2080_CTRL_INTERNAL_PFM_REQ_HNDLR_GET_PM1_STATUS; + + status = pRmApi->Control(pRmApi, + pGpu->hInternalClient, + pGpu->hInternalSubdevice, + NV2080_CTRL_CMD_INTERNAL_PERF_PFM_REQ_HNDLR_GET_PM1_STATE, + ¶ms, + sizeof(params)); + + if (status == NV_OK) + { + *pbPM1Available = params.bStatus; + } + + return status; +} + +/*! + * Handler routine to Update or Reset EDPpeak limit of GPU + * + * @param[in] pPlatformRequestHandler *PlatformRequestHandler object pointer + * @param[in] pGpu GPU object pointer + * @param[in] bEnable Enable or Reset the settings. + * + * @return NV_OK if the update was successful. + * @return NV_ERR_NOT_SUPPORTED if the POR support is not present + * @return NV_ERR_INVALID_STATE for invalid PMU state + * @return bubble up errors triggered by called code + */ +NV_STATUS +pfmreqhndlrHandleEdppeakLimitUpdate_IMPL +( + PlatformRequestHandler *pPlatformRequestHandler, + OBJGPU *pGpu, + NvBool bEnable +) +{ + RM_API *pRmApi = GPU_GET_PHYSICAL_RMAPI(pGpu); + NV_STATUS status = NV_OK; + + if (gpuIsGpuFullPower(pGpu)) + { + NV2080_CTRL_CMD_INTERNAL_PMGR_PFM_REQ_HNDLR_UPDATE_EDPP_LIMIT_PARAMS params = { 0 }; + + params.bEnable = bEnable; + status = pRmApi->Control(pRmApi, + pGpu->hInternalClient, + pGpu->hInternalSubdevice, + NV2080_CTRL_CMD_INTERNAL_PMGR_PFM_REQ_HNDLR_UPDATE_EDPP_LIMIT, + ¶ms, + sizeof(params)); + + if (status != NV_OK) + { + NV_PRINTF(LEVEL_ERROR, "Error updating EDPpeak Limit State: 0x%08x\n", status); + DBG_BREAKPOINT(); + } + else + { + // Update the cached enable bit, if everything went well + pPlatformRequestHandler->controlData.bEDPpeakUpdateEnabled = bEnable; + } + } + + return status; +} + +/*! + * Handler routine to Update or Reset EDPpeak limit from platform + * + * @param[in] pPlatformRequestHandler PlatformRequestHandler object pointer + * @param[in] pGpu GPU object pointer + * @param[in] platformEdppLimit Platform EDPpeak limit value + * + * @return NV_OK if the update was successful. + * @return NV_ERR_NOT_SUPPORTED if the POR support is not present + * @return NV_ERR_INVALID_STATE for invalid PMU state + * @return bubble up errors triggered by called code + */ +NV_STATUS +pfmreqhndlrHandlePlatformEdppLimitUpdate_IMPL +( + PlatformRequestHandler *pPlatformRequestHandler, + OBJGPU *pGpu, + NvU32 platformEdppLimit +) +{ + RM_API *pRmApi = GPU_GET_PHYSICAL_RMAPI(pGpu); + NV_STATUS status = NV_OK; + + if (gpuIsGpuFullPower(pGpu)) + { + NV2080_CTRL_CMD_INTERNAL_PMGR_PFM_REQ_HNDLR_UPDATE_EDPP_LIMIT_PARAMS params = { 0 }; + + params.clientLimit = platformEdppLimit; + params.bEnable = NV_TRUE; + + // Platform can remove its EDPp and fall back to GPU default by setting a limit of value 0 + if (platformEdppLimit == 0) + { + params.bEnable = NV_FALSE; + } + status = pRmApi->Control(pRmApi, + pGpu->hInternalClient, + pGpu->hInternalSubdevice, + NV2080_CTRL_CMD_INTERNAL_PMGR_PFM_REQ_HNDLR_UPDATE_EDPP_LIMIT, + ¶ms, + sizeof(params)); + if (status != NV_OK) + { + NV_PRINTF(LEVEL_ERROR, "Error updating EDPpeak Limit State: 0x%08x\n", status); + DBG_BREAKPOINT(); + } + } + + return status; +} + +/*! + * Handle EDPpeak new limit query from platform + * + * @param[in] pPlatformRequestHandler PlatformRequestHandler object pointer + * @param[in] pGpu GPU object pointer + * @param[in] pPlatformEdppLimit Pointer to Platform EDPpeak limit value + * + * @return NV_OK if the update was successful. + * @return NV_ERR_NOT_SUPPORTED if the POR support is not present + * @return bubble up errors triggered by called code + */ +NV_STATUS +pfmreqhndlrHandlePlatformGetEdppLimit_IMPL +( + PlatformRequestHandler *pPlatformRequestHandler, + OBJGPU *pGpu, + NvU32 *pPlatformEdppLimit +) +{ + NV0000_CTRL_PFM_REQ_HNDLR_CALL_ACPI_PARAMS acpiParams; + NV_STATUS status = NV_OK; + + portMemSet((void*)&acpiParams, 0, sizeof(NV0000_CTRL_PFM_REQ_HNDLR_CALL_ACPI_PARAMS)); + + acpiParams.ctrl.cmd = NV0000_CTRL_PFM_REQ_HNDLR_CALL_ACPI_CMD_GETEDPPLIMIT; + + // Input is V1 + acpiParams.ctrl.input = NV0000_CTRL_PFM_REQ_HNDLR_EDPP_VERSION_V10; + status = pfmreqhndlrCallACPI(pGpu, &acpiParams); + if (status != NV_OK) + { + NV_PRINTF(LEVEL_ERROR, "Error querying EDPpeak Limit from platform: 0x%08x\n", status); + DBG_BREAKPOINT(); + status = NV_ERR_NOT_SUPPORTED; + goto _pfmreqhndlrHandlePlatformGetEdppLimit_IMPL_IMPL_exit; + } + + *pPlatformEdppLimit = acpiParams.output.result[0]; + +_pfmreqhndlrHandlePlatformGetEdppLimit_IMPL_IMPL_exit: + return status; +} + +/*! + * Handle send GPU EDPpeak limit info to platform + * + * @param[in] pPlatformRequestHandler PlatformRequestHandler object pointer + * @param[in] pGpu GPU object pointer + * + * @return NV_OK if the update was successful. + * @return bubble up errors triggered by called code + */ +NV_STATUS +pfmreqhndlrHandlePlatformSetEdppLimitInfo_IMPL +( + PlatformRequestHandler *pPlatformRequestHandler, + OBJGPU *pGpu +) +{ + + RM_API *pRmApi = GPU_GET_PHYSICAL_RMAPI(pGpu); + NV_STATUS status = NV_OK; + PFM_REQ_HNDLR_EDPP_DATA *pEdppLimit = + &pPlatformRequestHandler->controlData.edppLimit; + + if (gpuIsGpuFullPower(pGpu)) + { + NV2080_CTRL_CMD_INTERNAL_PMGR_PFM_REQ_HNDLR_GET_EDPP_LIMIT_INFO_PARAMS params = { 0 }; + + status = pRmApi->Control(pRmApi, + pGpu->hInternalClient, + pGpu->hInternalSubdevice, + NV2080_CTRL_CMD_INTERNAL_PMGR_PFM_REQ_HNDLR_GET_EDPP_LIMIT_INFO, + ¶ms, + sizeof(params)); + if (status == NV_OK) + { + pEdppLimit->edppLimitInfo.limitMin = params.limitMin; + pEdppLimit->edppLimitInfo.limitRated = params.limitRated; + pEdppLimit->edppLimitInfo.limitMax = params.limitMax; + pEdppLimit->edppLimitInfo.limitCurr = params.limitCurr; + pEdppLimit->edppLimitInfo.limitBattRated = params.limitBattRated; + pEdppLimit->edppLimitInfo.limitBattMax = params.limitBattMax; + pEdppLimit->edppLimitInfo.rsvd = 0; + pEdppLimit->status = NV_OK; + } + else + { + pEdppLimit->status = NV_ERR_INVALID_ARGUMENT; + } + } + else + { + pEdppLimit->status = NV_ERR_GPU_NOT_FULL_POWER; + } + + if (!pEdppLimit->bWorkItemPending) + { + OBJOS *pOS = GPU_GET_OS(pGpu); + + // Queue workitem to send the EDP limit info to platform + status = pOS->osQueueWorkItem(pGpu, + _pfmreqhndlrHandlePlatformSetEdppLimitInfoWorkItem, NULL); + if(status == NV_OK) + { + pEdppLimit->bWorkItemPending = NV_TRUE; + } + } + + return status; +} + +/*! + * Handler routine to enable or Reset GPU User Configurable TGP mode + * + * @param[in] pPlatformRequestHandler *PlatformRequestHandler object pointer + * @param[in] pGpu GPU object pointer + * @param[in] bEnable Enable or Reset the settings. + * + * @return NV_OK if the update was successful. + * @return NV_ERR_NOT_SUPPORTED if the POR support is not present + * @return NV_ERR_INVALID_STATE for invalid PMU state + * @return bubble up errors triggered by called code + */ +NV_STATUS +pfmreqhndlrHandleUserConfigurableTgpMode_IMPL +( + PlatformRequestHandler *pPlatformRequestHandler, + OBJGPU *pGpu, + NvBool bEnable +) +{ + NV_STATUS status = NV_ERR_GENERIC; + NV2080_CTRL_CMD_INTERNAL_PMGR_PFM_REQ_HNDLR_CONFIGURE_TGP_MODE_PARAMS params = { 0 }; + RM_API *pRmApi = GPU_GET_PHYSICAL_RMAPI(pGpu); + + params.bEnable = bEnable; + + status = pRmApi->Control(pRmApi, + pGpu->hInternalClient, + pGpu->hInternalSubdevice, + NV2080_CTRL_CMD_INTERNAL_PMGR_PFM_REQ_HNDLR_CONFIGURE_TGP_MODE, + ¶ms, + sizeof(params)); + if (status == NV_OK) + { + // Update the cached enable bit, if everything went well + pPlatformRequestHandler->controlData.bUserConfigTGPmodeEnabled = bEnable; + } + + return status; +} + +/* ---------------------- Static Functions --------------------------------- */ + +static NV_STATUS +_handleCmdSystemPfmreqhndlrGetSupportedFunctions +( + PlatformRequestHandler + *pPlatformRequestHandler, + NvU16 locale, + NvU32 *pData +) +{ + OBJGPU* pGpu = NULL; + + *pData = 0; + + + if (locale != NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_LOCALE_SYSTEM) + { + return NV_ERR_INVALID_COMMAND; + } + + pGpu = pfmreqhndlrGetGpu(pPlatformRequestHandler); + if (pGpu == NULL) + { + return NV_ERR_INVALID_STATE; + } + + *pData |= (NV_OK == testIfDsmSubFunctionEnabled(pGpu, pPlatformRequestHandler->dsmVersion, + NV_ACPI_ALL_FUNC_SUPPORT)) ? + NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_SYS_DEF_FUNC_SUPPORT : 0; + + return NV_OK; +} + +static NV_STATUS +_handleCmdSystemPfmreqhndlrDataInitUsingSbiosAndAck +( + PlatformRequestHandler + *pPlatformRequestHandler, + NvU16 locale, + NvU32 *pData +) +{ + OBJGPU *pGpu; + NV_STATUS status = NV_OK; + + if (locale != NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_LOCALE_SYSTEM) + { + return NV_ERR_INVALID_COMMAND; + } + + pGpu = pfmreqhndlrGetGpu(pPlatformRequestHandler); + + /* Full GPU check to ensure device is on */ + NV_ASSERT_OR_RETURN(FULL_GPU_SANITY_CHECK(pGpu), NV_ERR_INVALID_STATE); + + if (pPlatformRequestHandler->getProperty(pPlatformRequestHandler, PDB_PROP_PFMREQHNDLR_SUPPORTED)) + { + status = pfmreqhndlrHandleStatusChangeEvent(pPlatformRequestHandler, pGpu); + } + else + { + status = NV_ERR_NOT_SUPPORTED; + } + + return status; +} + +/*! + * Get a current 32 bit timestamp in MS + * + * @param[in] pPlatformRequestHandler *PlatformRequestHandler pointer + * + * @return 32 bit MS timestamp. + */ +static NvU32 +_pfmreqhndlrGetTimeStamp +( + PlatformRequestHandler *pPlatformRequestHandler +) +{ + OBJGPU *pGpu = pfmreqhndlrGetGpu(pPlatformRequestHandler); + OBJTMR *pTmr = GPU_GET_TIMER(pGpu); + NvU32 timeStamp = 0; + + timeStamp = (NvU32)(tmrGetTime_HAL(pGpu, pTmr) / 1000000L); + + return timeStamp; +} + +/*! + * Configure a counter with an override value. + * + * @param[in] pPfmreqhndlrData pointer to the PlatformRequestHandler data structure + * @param[in] id identifier of counter to whose Override should be canceled. + * @param[in] value new value for the specified counter. All values are accepted as + * unsigned integers, but internally they should be formatted based on the + * type of id/sensor they correspond to. + * @param[in] timeStamp current time stamp in MS used to indicate when the counter was last updated + * + */ +static void +_pfmreqhndlrOverrideCounter +( + PFM_REQ_HNDLR_SENSOR_DATA *pPfmreqhndlrData, + NvU32 id, + NvU32 value, + NvU32 timeStamp +) +{ + // update the counter with the new value. + _pfmreqhndlrUpdateCounter(pPfmreqhndlrData, id, NV_TRUE, value, timeStamp); + + // lock it in as an overriden value. + pPfmreqhndlrData->PFMREQHNDLRSensorCache[id].bOverridden = NV_TRUE; +} + +/*! + * Cancel an override of a specified counter. + * + * @param[in] pPfmreqhndlrData pointer to the PlatformRequestHandler data structure + * @param[in] id Identifier of counter to whose Override should be canceled. + * @param[in] timeStamp current time stamp in MSused to indicate when the caounter was last updated + * + * @note if a non-volatile counter has its override canceled, it may not be refreshed as part of a query, + * it is up to the calling function to ensure that the counter is placed in a valid (I.E. updated) state. + */ +static void +_pfmreqhndlrCancelCounterOverride +( + PFM_REQ_HNDLR_SENSOR_DATA *pPfmreqhndlrData, + NvU32 id, + NvU32 timeStamp +) +{ + if (pPfmreqhndlrData->PFMREQHNDLRSensorCache[id].bOverridden) + { + pPfmreqhndlrData->PFMREQHNDLRSensorCache[id].bOverridden = NV_FALSE; + _pfmreqhndlrResetCounter(pPfmreqhndlrData, id, timeStamp); + } +} + +/*! + * place the counter into a reset state where it does not contain a valid value, and the sample is expired. + * it updates the counter so that the value is marked as invalid & the timestamp + * is set so that the counter can be updated + * + * @param[in] pPfmreqhndlrData Pointer to the PlatformRequestHandler data structure + * @param[in] id Identifier of counter to which should be marked invalid. + * + * @note if a non-volatile counter is marked as invalid, it may not be refreshed as part of a query, + * it is up to the calling function to ensure that the counter is placed in a valid (I.E. updated) state. + */ +static void +_pfmreqhndlrResetCounter +( + PFM_REQ_HNDLR_SENSOR_DATA *pPfmreqhndlrData, + NvU32 id, + NvU32 timeStamp +) +{ + if (!pPfmreqhndlrData->PFMREQHNDLRSensorCache[id].bOverridden) + { + pPfmreqhndlrData->PFMREQHNDLRSensorCache[id].bInvalid = NV_TRUE; + + // use a timestamp that marks the value as stale in order to ensure that + // volatile counters are refreshed prior to being reported. + pPfmreqhndlrData->PFMREQHNDLRSensorCache[id].lastSampled = timeStamp - NV_MAX(pPfmreqhndlrData->PFMREQHNDLRSensorCache[id].minInterval, pPfmreqhndlrData->counterHoldPeriod) - 1; + } +} + +/*! + * Update a counter to a specified state (valid/invalid) & value. + * it updates the specified counter based on the result of the sampling + * (as reported in bValid) and the value provided. + * + * @param[in] pPfmreqhndlrData pointer to the PlatformRequestHandler data structure + * @param[in] id identifier of counter to be updated. + * @param[in] bValid a bool indicating a valid value is being provided for the counter. + * @param[in] value new value for the specified counter. All values are accepted as + * unsigned integers, but internally they should be formatted based on the + * type of id/sensor they correspond to. + * @param[in] timeStamp current time stamp in MS used to indicate when the counter was last updated + * + */ +static void +_pfmreqhndlrUpdateCounter +( + PFM_REQ_HNDLR_SENSOR_DATA *pPfmreqhndlrData, + NvU32 id, + NvBool bValid, + NvU32 value, + NvU32 timeStamp +) +{ + if (bValid || pPfmreqhndlrData->PFMREQHNDLRSensorCache[id].bOverridden) + { + // only update the value if the current value is not an override. + if (!pPfmreqhndlrData->PFMREQHNDLRSensorCache[id].bOverridden) + { + pPfmreqhndlrData->PFMREQHNDLRSensorCache[id].value = value; + } + pPfmreqhndlrData->PFMREQHNDLRSensorCache[id].lastSampled = timeStamp; + pPfmreqhndlrData->PFMREQHNDLRSensorCache[id].bInvalid = NV_FALSE; + } + else + { + // The counter is not valid or overridden, mark it as invalid. + pPfmreqhndlrData->PFMREQHNDLRSensorCache[id].bInvalid = NV_TRUE; + } +} + +/*! + * Enables/disables PM1 (boost clocks). + * + * @param[in] pGpu OBJGPU pointer + * @param[in] bEnable Boolean value to turn on/off PM1 (boost clocks) + * + * @return NV_OK PM1 (boost clocks) successfully enabled/disabled + * @return NV_ERR_NOT_SUPPORTED PM1 (boost clocks) not supported + * @return NV_ERR_INVALID_STATE Could not enable/disable PM1 + */ +static NV_STATUS +_pfmreqhndlrEnablePM1 +( + OBJGPU *pGpu, + NvBool bEnable +) +{ + NV2080_CTRL_CMD_INTERNAL_PERF_PFM_REQ_HNDLR_SET_PM1_STATE_PARAMS params = { 0 }; + RM_API *pRmApi = GPU_GET_PHYSICAL_RMAPI(pGpu); + + params.bEnable = bEnable; + + return pRmApi->Control(pRmApi, + pGpu->hInternalClient, + pGpu->hInternalSubdevice, + NV2080_CTRL_CMD_INTERNAL_PERF_PFM_REQ_HNDLR_SET_PM1_STATE, + ¶ms, + sizeof(params)); +} + +/*! + * Sample and update the Platform Power Mode data. + * + * @param[in] pPlatformRequestHandler *PlatformRequestHandler object poiner + * @param[in] pGpu OBJGPU object pointer + * @param[in] If called from PlatformRequestHandler init sequence + * + * @return NV_OK on success + * @return Bubble up error otherwise + */ + +static NV_STATUS +_pfmreqhndlrUpdatePpmdLimit +( + PlatformRequestHandler *pPlatformRequestHandler, + OBJGPU *pGpu, + NvBool bInit +) +{ + NV_STATUS status = NV_OK; + PFM_REQ_HNDLR_PPM_DATA *pPpmData = NULL; + NvU32 counterVal = 0; + NV2080_PLATFORM_POWER_MODE_CHANGE_STATUS params = { 0 }; + NvU32 info32 = 0; + + status = pfmreqhndlrGetPerfSensorCounterById(pPlatformRequestHandler, + PFM_REQ_HNDLR_LIMIT(PFM_REQ_HNDLR_PPMD_SENSOR), + &counterVal); + if (status != NV_OK) + { + NV_ASSERT_OK_FAILED("PlatformRequestHandler failed to get platform power mode from SBIOS", status); + goto _pfmreqhndlrUpdatePpmdLimit_exit; + } + + if (PFM_REQ_HNDLR_IS_COUNTER_VALID(pPlatformRequestHandler, PFM_REQ_HNDLR_LIMIT(PFM_REQ_HNDLR_PPMD_SENSOR))) + { + pPpmData = &(pPlatformRequestHandler->ppmData); + + // Update the power mode mask as received from the platform + pPpmData->ppmMaskCurrent = + DRF_VAL(0000_CTRL_PFM_REQ_HNDLR, _PPM, _MASK, counterVal); + + // + // Cache the platform requested power mode during init time only. + // Runtime, the system request should result in a client notification only. + // + if (bInit) + { + pPpmData->ppmIdxCurrent = + DRF_VAL(0000_CTRL_PFM_REQ_HNDLR, _PPM, _INDEX, counterVal); + } + + // Notify clients with the new limits + params.platformPowerModeIndex = DRF_VAL(0000_CTRL_PFM_REQ_HNDLR, _PPM, _INDEX, counterVal); + params.platformPowerModeMask = pPpmData->ppmMaskCurrent; + params.eventReason = NV2080_PLATFORM_POWER_MODE_CHANGE_ACPI_NOTIFICATION; + + info32 = (params.platformPowerModeIndex << DRF_SHIFT(NV2080_PLATFORM_POWER_MODE_CHANGE_INFO_INDEX)) | + (params.platformPowerModeMask << DRF_SHIFT(NV2080_PLATFORM_POWER_MODE_CHANGE_INFO_MASK)) | + (params.eventReason << DRF_SHIFT(NV2080_PLATFORM_POWER_MODE_CHANGE_INFO_REASON)); + + gpuNotifySubDeviceEvent(pGpu, NV2080_NOTIFIERS_PLATFORM_POWER_MODE_CHANGE, ¶ms, sizeof(params), info32, 0); + } + +_pfmreqhndlrUpdatePpmdLimit_exit: + return status; +} + +static NV_STATUS +_pfmreqhndlrUpdateTgpuLimit +( + PlatformRequestHandler *pPlatformRequestHandler, + OBJGPU *pGpu +) +{ + NvU32 counterVal; + NvTemp targetTemp = PFM_REQ_HNDLR_TEMP_0_C; + NV_STATUS status = NV_ERR_NOT_SUPPORTED; + RM_API *pRmApi = GPU_GET_PHYSICAL_RMAPI(pGpu); + + // note -- we need to go through the call to ensure any override is honored. + status = pfmreqhndlrGetPerfSensorCounterById(pPlatformRequestHandler, + PFM_REQ_HNDLR_LIMIT(PFM_REQ_HNDLR_TGPU_SENSOR), + &counterVal); + + if (status != NV_OK) + { + NV_ASSERT_OK_FAILED("PlatformRequestHandler failed to get target temp from SBIOS", status); + return status; + } + + targetTemp = NV_TYPES_CELSIUS_TO_NV_TEMP(counterVal); + + // 2x operation + if (PFM_REQ_HNDLR_IS_ACPI_VERSION_SW_2X(pPlatformRequestHandler)) + { + // 2X operation Will not allow a 0C default value from SBIOS to SWTC interface + if (targetTemp == PFM_REQ_HNDLR_TEMP_0_C) + { + // The VBIOS default limit takes effect + status = NV_OK; + return status; + } + } + + + NV2080_CTRL_CMD_INTERNAL_THERM_PFM_REQ_HNDLR_UPDATE_TGPU_LIMIT_PARAMS params = { 0 }; + params.targetTemp = targetTemp; + + status = pRmApi->Control(pRmApi, + pGpu->hInternalClient, + pGpu->hInternalSubdevice, + NV2080_CTRL_CMD_INTERNAL_THERM_PFM_REQ_HNDLR_UPDATE_TGPU_LIMIT, + ¶ms, + sizeof(params)); + + return status; +} + +/*! + * @brief helper function to update each system control parameter. + * + * @param[in] pPlatformRequestHandler *PlatformRequestHandler pointer + * @param[in] id Identifier of counter to update + */ +static NV_STATUS +_pfmreqhndlrUpdateSystemParamLimit(PlatformRequestHandler *pPlatformRequestHandler, NvU32 id) +{ + NV_STATUS status; + OBJGPU *pGpu = pfmreqhndlrGetGpu(pPlatformRequestHandler); + + switch (id) + { + case PFM_REQ_HNDLR_TGPU_SENSOR: + { + status = _pfmreqhndlrUpdateTgpuLimit(pPlatformRequestHandler, pGpu); + break; + } + default: + { + status = NV_ERR_NOT_SUPPORTED; + break; + } + } + + return status; +} + +/*! + * @brief passive worker thread to platform power mode. + * + * @param[in] gpuInstance GPU instance ID + * @param[in] newIndex requested Platform Power Mode Index + */ +static void +_pfmreqhndlrUpdatePlatformPowerModeWorkItem +( + NvU32 gpuInstance, + void *pParams +) +{ + OBJSYS *pSys = SYS_GET_INSTANCE(); + PlatformRequestHandler *pPlatformRequestHandler = SYS_GET_PFM_REQ_HNDLR(pSys); + OBJGPU *pGpu = pfmreqhndlrGetGpu(pPlatformRequestHandler); + NvU32 status = NV_OK; + NV0000_CTRL_PFM_REQ_HNDLR_CALL_ACPI_PARAMS_EX acpiParamsEx = {0}; + NvU32 gpuLockFlag = GPUS_LOCK_FLAGS_NONE; + + if (FULL_GPU_SANITY_CHECK(pGpu)) + { + // Attempt to acquire locks/semaphore + if (pfmreqhndlrPassiveModeTransition(NV_TRUE, API_LOCK_FLAGS_NONE, + gpuLockFlag) != NV_OK) + { + NV_PRINTF(LEVEL_ERROR, "Failed to acquire the locks/semaphore!\n"); + goto pfmreqhndlrUpdatePlatformPowerModeWorkItemExit; + } + + // Call ACPI to set the new platform power mode + acpiParamsEx.inSize = NV0000_CTRL_PFM_REQ_HNDLR_PPM_ARGS_COUNT * sizeof(NvU32); + acpiParamsEx.input[NV0000_CTRL_PFM_REQ_HNDLR_PPM_ARGS_VERSION_IDX] = + FLD_SET_DRF(0000_CTRL_PFM_REQ_HNDLR, _PPM_ARG0_VERSION, _MAJOR, _V1, + acpiParamsEx.input[NV0000_CTRL_PFM_REQ_HNDLR_PPM_ARGS_VERSION_IDX]); + acpiParamsEx.outSize = NV0000_CTRL_PFM_REQ_HNDLR_PPM_ARGS_COUNT * sizeof(NvU32); + acpiParamsEx.pfmreqhndlrFunc = GPS_FUNC_SETPPM; + acpiParamsEx.input[NV0000_CTRL_PFM_REQ_HNDLR_PPM_ARGS_IDX] = + FLD_SET_DRF_NUM(0000_CTRL_PFM_REQ_HNDLR, _PPM_ARGS, _INDEX, + pPlatformRequestHandler->ppmData.ppmIdxRequested, acpiParamsEx.input[NV0000_CTRL_PFM_REQ_HNDLR_PPM_ARGS_IDX]); + + status = pfmreqhndlrCallACPI_EX(pGpu, &acpiParamsEx); + + // + // If ACPI call is successful, cache the new Index for future Get PPM calls + // and notify NvCPL + // + if (NV_OK == status) + { + NV2080_PLATFORM_POWER_MODE_CHANGE_STATUS params = {0}; + NvU32 info32 = 0; + pPlatformRequestHandler->ppmData.ppmIdxCurrent = pPlatformRequestHandler->ppmData.ppmIdxRequested; + params.platformPowerModeIndex = pPlatformRequestHandler->ppmData.ppmIdxCurrent; + params.platformPowerModeMask = pPlatformRequestHandler->ppmData.ppmMaskCurrent; + params.eventReason = NV2080_PLATFORM_POWER_MODE_CHANGE_COMPLETION; + + info32 = (params.platformPowerModeIndex << DRF_SHIFT(NV2080_PLATFORM_POWER_MODE_CHANGE_INFO_INDEX)) | + (params.platformPowerModeMask << DRF_SHIFT(NV2080_PLATFORM_POWER_MODE_CHANGE_INFO_MASK)) | + (params.eventReason << DRF_SHIFT(NV2080_PLATFORM_POWER_MODE_CHANGE_INFO_REASON)); + + gpuNotifySubDeviceEvent(pGpu, NV2080_NOTIFIERS_PLATFORM_POWER_MODE_CHANGE, ¶ms, sizeof(params), info32, 0); + } + + // Release locks/semaphore + pfmreqhndlrPassiveModeTransition(NV_FALSE, API_LOCK_FLAGS_NONE, gpuLockFlag); + } + +pfmreqhndlrUpdatePlatformPowerModeWorkItemExit: + // Reset on exit + pPlatformRequestHandler->ppmData.ppmIdxRequested = NV0000_CTRL_PFM_REQ_HNDLR_PPM_INDEX_INVALID; + pPlatformRequestHandler->ppmData.bWorkItemPending = NV_FALSE; +} + +/*! + * @brief passive worker thread to update the system control parameters. + * + * @param[in] gpuInstance GPU instance ID + * @param[in] pParam unused + */ +static void +_pfmreqhndlrUpdateSystemParamLimitWorkItem +( + NvU32 gpuInstance, + void *pParams +) +{ + OBJSYS *pSys = SYS_GET_INSTANCE(); + PlatformRequestHandler *pPlatformRequestHandler = SYS_GET_PFM_REQ_HNDLR(pSys); + NvU32 id; + + // Attempt to acquire locks/semaphore + if (pfmreqhndlrPassiveModeTransition(NV_TRUE, API_LOCK_FLAGS_NONE, GPUS_LOCK_FLAGS_NONE) != NV_OK) + { + NV_PRINTF(LEVEL_ERROR, "Failed to acquire the locks/semaphore!\n"); + + pPlatformRequestHandler->sysControlData.bWorkItemPending = NV_FALSE; + return; + } + + FOR_EACH_INDEX_IN_MASK(32, id, pPlatformRequestHandler->sysControlData.queuedCounterMask) + { + _pfmreqhndlrUpdateSystemParamLimit(pPlatformRequestHandler, id); + } + FOR_EACH_INDEX_IN_MASK_END; + + pPlatformRequestHandler->sysControlData.bWorkItemPending = NV_FALSE; + pPlatformRequestHandler->sysControlData.queuedCounterMask = 0; + + // Release locks/semaphore + pfmreqhndlrPassiveModeTransition(NV_FALSE, API_LOCK_FLAGS_NONE, GPUS_LOCK_FLAGS_NONE); +} + +/*! + * + * _pfmreqhndlrCallPshareStatus + * + * This function makes the PSHARESTATUS ACPI call. It sets up the call based on + * the ACPI cache & updates the cache with the results. + * + * @param[in] pPlatformRequestHandler *PlatformRequestHandler object pointer + * @param[in] bInit If called from PlatformRequestHandler init sequence + * + * @return NV_OK if the update was successful. + * @return NV_ERR_INVALID_STATE for invalid PMU state + * @return bubble up errors triggered by called code + */ +static NV_STATUS +_pfmreqhndlrCallPshareStatus +( + PlatformRequestHandler *pPlatformRequestHandler, + NvBool bInit +) +{ + OBJGPU *pGpu = NULL; + PFM_REQ_HNDLR_SENSOR_DATA *pPfmreqhndlrData = NULL; + NV_STATUS status = NV_OK; + NV_STATUS lclStatus = NV_OK; + NV0000_CTRL_PFM_REQ_HNDLR_CALL_ACPI_PARAMS + acpiParams; + NvU32 timeStamp; + + NV_ASSERT_OR_RETURN(NULL != pPlatformRequestHandler, NV_ERR_INVALID_REQUEST); + + pGpu = pfmreqhndlrGetGpu(pPlatformRequestHandler); + pPfmreqhndlrData = &pPlatformRequestHandler->sensorData; + + acpiParams.ctrl.cmd = NV0000_CTRL_PFM_REQ_HNDLR_CALL_ACPI_CMD_PSHARESTATUS; + acpiParams.ctrl.input = 0; + acpiParams.output.pBuffer = NULL; + acpiParams.output.bufferSz = 0; + + status = pfmreqhndlrCallACPI(pGpu, &acpiParams); + + if (NV_OK == status) + { + NvBool bQueryEdppRequired = NV_FALSE; + NvBool bPlatformEdpUpdate = NV_FALSE; + + // Platform EDPp limit handling check + bQueryEdppRequired = FLD_TEST_DRF(0000_CTRL_PFM_REQ_HNDLR, _PSHARESTATUS, _PLATFORM_GETEDPPEAKLIMIT_SET, _TRUE, acpiParams.output.result[0]); + bPlatformEdpUpdate = FLD_TEST_DRF(0000_CTRL_PFM_REQ_HNDLR, _PSHARESTATUS, _PLATFORM_SETEDPPEAKLIMITINFO_SET, _TRUE, acpiParams.output.result[0]); + + // update the cache values + pPfmreqhndlrData->PFMREQHNDLRACPIData.bSystemParamLimitUpdate = FLD_TEST_DRF(0000_CTRL_PFM_REQ_HNDLR, _PSHARESTATUS, _UPDATE_LIMIT, _PENDING, acpiParams.output.result[0]); + + pPfmreqhndlrData->PFMREQHNDLRACPIData.bEDPpeakLimitUpdateRequest = + FLD_TEST_DRF(0000_CTRL_PFM_REQ_HNDLR, _PSHARESTATUS, _EDPPEAK_LIMIT_UPDATE, _TRUE, acpiParams.output.result[0]); + pPfmreqhndlrData->PFMREQHNDLRACPIData.bUserConfigTGPmodeRequest = + FLD_TEST_DRF(0000_CTRL_PFM_REQ_HNDLR, _PSHARESTATUS, _USER_CONFIG_TGP_MODE, _ENABLE, acpiParams.output.result[0]); + pPfmreqhndlrData->PFMREQHNDLRACPIData.bPlatformUserConfigTGPSupport = + FLD_TEST_DRF(0000_CTRL_PFM_REQ_HNDLR, _PSHARESTATUS, _PLAT_USER_CONFIG_TGP_MODE_SUPPORT, _ENABLE, acpiParams.output.result[0]); + + // + // 1.A. EDPpeak limit update: Handle the legacy way where a VBIOS static limit is applied + // Update only if in reset state and Reset only if is in enabled state + // + if (PFM_REQ_HNDLR_IS_EDPPEAK_UPDATE_REQUIRED(pPfmreqhndlrData->PFMREQHNDLRACPIData.bEDPpeakLimitUpdateRequest, + pPlatformRequestHandler->controlData.bEDPpeakUpdateEnabled) && !bInit) + { + // Update or Reset the EDPp limit if needed + lclStatus = pfmreqhndlrHandleEdppeakLimitUpdate(pPlatformRequestHandler, pGpu, + pPfmreqhndlrData->PFMREQHNDLRACPIData.bEDPpeakLimitUpdateRequest); + if ((NV_OK != lclStatus) && + (NV_ERR_NOT_SUPPORTED != lclStatus)) + { + status = lclStatus; + } + } + + // + // 1.B. EDPpeak limit update : Handle platform supplied limit + // + if (bQueryEdppRequired) + { + NvU32 platformEdppLimit = 0; + + // Query platform for the new EDPp value + lclStatus = pfmreqhndlrHandlePlatformGetEdppLimit(pPlatformRequestHandler, pGpu, &platformEdppLimit); + if ((NV_OK != lclStatus) && + (NV_ERR_NOT_SUPPORTED != lclStatus)) + { + status = lclStatus; + } + else + { + // Cache the EDPp limit from platform request + pPfmreqhndlrData->PFMREQHNDLRACPIData.platformEdppLimit = platformEdppLimit; + } + + if (bInit) + { + // Defer init time EDPp update after prereq is satisfied + pPlatformRequestHandler->controlData.edppLimit.bDifferPlatformEdppLimit = NV_TRUE; + } + else + { + // Followed by apply the platform limit on the GPU + lclStatus = pfmreqhndlrHandlePlatformEdppLimitUpdate(pPlatformRequestHandler, pGpu, + pPfmreqhndlrData->PFMREQHNDLRACPIData.platformEdppLimit); + if ((NV_OK != lclStatus) && + (NV_ERR_NOT_SUPPORTED != lclStatus)) + { + status = lclStatus; + } + } + } + + // + // 2. User configurable TGP mode (Turbo) Update + // Enable only if in reset state and Reset only if in enabled state + // + if (PFM_REQ_HNDLR_IS_USER_CONFIG_TGP_MODE_UPDATE_REQUIRED(pPfmreqhndlrData->PFMREQHNDLRACPIData.bUserConfigTGPmodeRequest, + pPlatformRequestHandler->controlData.bUserConfigTGPmodeEnabled) && !bInit) + { + // Enable or Reset the configurable TGP mode if needed + lclStatus = pfmreqhndlrHandleUserConfigurableTgpMode(pPlatformRequestHandler, pGpu, + pPfmreqhndlrData->PFMREQHNDLRACPIData.bUserConfigTGPmodeRequest); + if ((NV_OK != lclStatus) && + (NV_ERR_NOT_SUPPORTED != lclStatus)) + { + status = lclStatus; + } + } + + // 3. Platform static customization for user config TGP can be handled here one time + if ((pPfmreqhndlrData->PFMREQHNDLRACPIData.bPlatformUserConfigTGPSupport) && + (!pPlatformRequestHandler->controlData.bPlatformUserConfigTGPmodeEnabled) && + (bInit)) + { + lclStatus = _pfmreqhndlrHandleUserConfigurableTgpModePlatformCustomization(pPlatformRequestHandler, pGpu); + if ((NV_OK != lclStatus) && + (NV_ERR_NOT_SUPPORTED != lclStatus)) + { + status = lclStatus; + } + } + + if (pPfmreqhndlrData->PFMREQHNDLRACPIData.bSystemParamLimitUpdate) + { + timeStamp = _pfmreqhndlrGetTimeStamp(pPlatformRequestHandler); + _pfmreqhndlrResetCounter(pPfmreqhndlrData, PFM_REQ_HNDLR_LIMIT(PFM_REQ_HNDLR_TGPU_SENSOR), timeStamp); + _pfmreqhndlrResetCounter(pPfmreqhndlrData, PFM_REQ_HNDLR_LIMIT(PFM_REQ_HNDLR_PPMD_SENSOR), timeStamp); + + lclStatus = _pfmreqhndlrUpdateTgpuLimit(pPlatformRequestHandler, pGpu); + if ((NV_OK == status) && (NV_ERR_NOT_SUPPORTED != lclStatus)) + { + status = lclStatus; + } + + if (PFM_REQ_HNDLR_IS_ACPI_VERSION_SW_2X(pPlatformRequestHandler)) + { + // Run time PPMD update from the system + lclStatus = _pfmreqhndlrUpdatePpmdLimit(pPlatformRequestHandler, pGpu, NV_FALSE); + if ((NV_OK == status) && (NV_ERR_NOT_SUPPORTED != lclStatus)) + { + status = lclStatus; + } + } + + // Reset the system parameter update flag + pPfmreqhndlrData->PFMREQHNDLRACPIData.bSystemParamLimitUpdate = NV_FALSE; + } + + if (bPlatformEdpUpdate) + { + lclStatus = pfmreqhndlrHandlePlatformSetEdppLimitInfo(pPlatformRequestHandler, pGpu); + if ((NV_OK != lclStatus) && (NV_ERR_NOT_SUPPORTED != lclStatus)) + { + status = lclStatus; + } + } + } + + return status; +} + +/*! + * Setup the initial state for the given counter as a supported counter. + * + * @param[in] pPfmreqhndlrData Pointer to the Sensor Data cache. + * @param[in] id Identifier of counter to be updated. + * @param[in] bVolatile bool indicating if the counter is volatile or not. + * Volatile counters can go stale & will be sampled + * on request for a sampling, whereas it is the + * responsability of the code associated with controlling + * the counter value to update a non-volatile counter. + * @param[in] timeStamp current time stamp in MS used to create a stale + * timestamp if needed to ensure that the first time + * the counter is querried we try to sample it. + * + */ +static void +_pfmreqhndlrInitSupportedCounter +( + PFM_REQ_HNDLR_SENSOR_DATA *pPfmreqhndlrData, + NvU32 id, + NvBool bVolatile, + NvU32 timeStamp +) +{ + pPfmreqhndlrData->PFMREQHNDLRSensorCache[id].bSupported = NV_TRUE; + pPfmreqhndlrData->PFMREQHNDLRSensorCache[id].bVolatile = bVolatile; + pPfmreqhndlrData->PFMREQHNDLRSensorCache[id].minInterval = PFM_REQ_HNDLR_DEFAULT_COUNTER_HOLD_PERIOD_MS; + _pfmreqhndlrResetCounter(pPfmreqhndlrData, id, timeStamp); +} + +// +// _pfmreqhndlrGetPerfSensorCounters +// +// This function collects the requested counters and returns those that are actually available. +// +NV_STATUS +pfmreqhndlrGetPerfSensorCounters +( + NV0000_CTRL_SYSTEM_PFM_REQ_HNDLR_GET_PERF_SENSOR_COUNTERS_PARAMS *pParams, + NvU16 mapFlags +) +{ + OBJSYS *pSys = SYS_GET_INSTANCE(); + PlatformRequestHandler *pPlatformRequestHandler = SYS_GET_PFM_REQ_HNDLR(pSys); + NvU32 counterMask; + NvU32 counterVal; + NvU16 idx; + + NV_ASSERT_OR_RETURN(NULL != pPlatformRequestHandler, NV_ERR_NOT_SUPPORTED); + + // is the block Id within range? + if (pParams->blockId >= PFM_REQ_HNDLR_AVAILABLE_SENSOR_BLOCKS) + { + return NV_ERR_NOT_SUPPORTED; + } + + // run thru & get each counter specified in the request mask. + for (idx = 0; idx < PFM_REQ_HNDLR_MAX_SENSORS_IN_BLOCK; ++idx) + { + pParams->counterBlock[idx] = 0; + counterMask = (1 << idx); + + // are we interested in this counter? + if (((pParams->countersReq & counterMask) != 0) && + ((PerfSensorBlockMap[pParams->blockId][idx] & mapFlags) == mapFlags)) + { + if (NV_OK == pfmreqhndlrGetPerfSensorCounterById(pPlatformRequestHandler, + PFM_REQ_HNDLR_PSR_ID(PerfSensorBlockMap[pParams->blockId][idx]), + &counterVal)) + { + pParams->counterBlock[idx] = counterVal; + pParams->countersReturned |= counterMask; + } + } + } + + return NV_OK; +} + +// +// _pfmreqhndlrIsCacheEntryStale +// +// This function returns a bool indicating if the specified cache entry is stale. +// +static NvBool +_pfmreqhndlrIsCacheEntryStale +( + PFM_REQ_HNDLR_SENSOR_DATA *pPfmreqhndlrData, + NvU32 counterId, + NvU32 timeStamp +) +{ + NvU32 age; + NvBool bStale = NV_FALSE; + + // if the counter is Volatile, check to see if it has aged out. + if ((pPfmreqhndlrData->PFMREQHNDLRSensorCache[counterId].bVolatile) && + (!pPfmreqhndlrData->PFMREQHNDLRSensorCache[counterId].bOverridden)) + { + // calculate the age allowing for wrap. + age = timeStamp - pPfmreqhndlrData->PFMREQHNDLRSensorCache[counterId].lastSampled; + + // if the age went negitive, make the age 0. + if ((NvS32)age < 0) + { + age = 0; + } + bStale = ((pPfmreqhndlrData->counterHoldPeriod < age) && (pPfmreqhndlrData->PFMREQHNDLRSensorCache[counterId].minInterval < age)); + } + return bStale; +} + +static NV_STATUS +_pfmreqhndlrSampleSensorLimit +( + PlatformRequestHandler *pPlatformRequestHandler, + NvU32 id, + NvU32 timeStamp +) +{ + NV_STATUS status = NV_ERR_NOT_SUPPORTED; + + if (!PFM_REQ_HNDLR_VALID_LIMIT_ID(id)) + { + return NV_ERR_NOT_SUPPORTED; + } + + // Use ACPI only + status = _pfmreqhndlrSampleSensorLimit_ACPI(pPlatformRequestHandler, id, timeStamp); + + return status; +} + +static NV_STATUS +_pfmreqhndlrSampleSensorLimit_ACPI +( + PlatformRequestHandler *pPlatformRequestHandler, + NvU32 id, + NvU32 timeStamp +) +{ + PFM_REQ_HNDLR_SENSOR_DATA *pPfmreqhndlrData = &pPlatformRequestHandler->sensorData; + OBJGPU *pGpu = pfmreqhndlrGetGpu(pPlatformRequestHandler); + NV0000_CTRL_PFM_REQ_HNDLR_CALL_ACPI_PARAMS acpiParams = {{ 0 }}; + PFM_REQ_HNDLR_PSHAREDATA pshareParams = { 0 }; + NV_STATUS status; + NvU8 i; + + // all the counters for this case are read in a single block + acpiParams.ctrl.cmd = NV0000_CTRL_PFM_REQ_HNDLR_CALL_ACPI_CMD_PSHAREPARAMS; + acpiParams.ctrl.input = pPfmreqhndlrData->PFMREQHNDLRShareParamsAvailMask | + DRF_DEF(0000_CTRL_PFM_REQ_HNDLR, _PSHARE_PARAMS, _STATUS_QUERY_TYPE, _CURRENT_LIMITS); + + // exclude counters that are up-to-date or have forced overrides + for (i = 0; i < PFM_REQ_HNDLR_PSHAREPARAMS_COUNT; i++) + { + if (((timeStamp - pPfmreqhndlrData->PFMREQHNDLRSensorCache[PFM_REQ_HNDLR_LIMIT(i)].lastSampled) < + pPfmreqhndlrData->PFMREQHNDLRSensorCache[PFM_REQ_HNDLR_LIMIT(i)].minInterval) || + pPfmreqhndlrData->PFMREQHNDLRSensorCache[PFM_REQ_HNDLR_LIMIT(i)].bOverridden) + { + acpiParams.ctrl.input &= ~NVBIT(i + DRF_BASE(NV0000_CTRL_PFM_REQ_HNDLR_PSHARE_PARAMS_STATUS_TGPU)); + } + } + + // bail-out if everything is already up-to-date + if (acpiParams.ctrl.input == 0) + { + return NV_OK; + } + + acpiParams.output.pBuffer = (NvU8 *)&pshareParams; + acpiParams.output.bufferSz = sizeof(pshareParams); + status = pfmreqhndlrCallACPI(pGpu, &acpiParams); + if (status == NV_OK) + { + if (FLD_TEST_DRF(0000_CTRL_PFM_REQ_HNDLR, _PSHARE_PARAMS_STATUS, _TGPU, _TRUE, acpiParams.ctrl.input)) + { + _pfmreqhndlrUpdateCounter(pPfmreqhndlrData, PFM_REQ_HNDLR_LIMIT(PFM_REQ_HNDLR_TGPU_SENSOR), FLD_TEST_DRF(0000_CTRL_PFM_REQ_HNDLR, _PSHARE_PARAMS_STATUS, _TGPU, _TRUE, pshareParams.status), pshareParams.tGpu, timeStamp); + } + if (FLD_TEST_DRF(0000_CTRL_PFM_REQ_HNDLR, _PSHARE_PARAMS_STATUS, _PPMD, _TRUE, acpiParams.ctrl.input)) + { + _pfmreqhndlrUpdateCounter(pPfmreqhndlrData, PFM_REQ_HNDLR_LIMIT(PFM_REQ_HNDLR_PPMD_SENSOR), FLD_TEST_DRF(0000_CTRL_PFM_REQ_HNDLR, _PSHARE_PARAMS_STATUS, _PPMD, _TRUE, pshareParams.status), pshareParams.ppmd, timeStamp); + } + } + return status; +} + +/*! + * Set up PlatformRequestHandler control flags based on the ACPI supported subfunction lists. + * + * @param[in] pGpu OBJGPU pointer + * @param[in] pPlatformRequestHandler *PlatformRequestHandler pointer + * @param[in] supportedSubfuncs NvU32 supported subfunctions list from SBIOS + * + * @return NV_OK always succeeds + * + */ +static NV_STATUS +_pfmreqhndlrSetSupportedStatesFromAcpiParams +( + OBJGPU *pGpu, + PlatformRequestHandler + *pPlatformRequestHandler, + NvU32 supportedSubfuncs + +) +{ + PFM_REQ_HNDLR_SENSOR_DATA *pPfmreqhndlrData = &(pPlatformRequestHandler->sensorData); + + pPfmreqhndlrData->PFMREQHNDLRACPIData.bPfmReqHndlrSupported = + ((0 != (DRF_VAL(0000_CTRL_PFM_REQ_HNDLR, _SUPPORTED, _PSHARESTATUS_AVAIL, supportedSubfuncs))) && + (0 != (DRF_VAL(0000_CTRL_PFM_REQ_HNDLR, _SUPPORTED, _PSHAREPARAMS_AVAIL, supportedSubfuncs)))); + + return NV_OK; +} + +/*! + * Handler routine to platform costumization to user mode TGP + * + * @param[in] pPlatformRequestHandler *PlatformRequestHandler object pointer + * + * @return NV_OK if the update was successful. + * @return NV_ERR_NOT_SUPPORTED if the POR support is not present + * @return bubble up errors triggered by called code + */ +static NV_STATUS +_pfmreqhndlrHandleUserConfigurableTgpModePlatformCustomization +( + PlatformRequestHandler *pPlatformRequestHandler, + OBJGPU *pGpu +) +{ + NV_STATUS status = NV_OK; + NV0000_CTRL_PFM_REQ_HNDLR_CALL_ACPI_PARAMS acpiParams; + PFM_REQ_HNDLR_PSHAREDATA pshareParams; + + portMemSet((void *) &acpiParams, 0, sizeof(NV0000_CTRL_PFM_REQ_HNDLR_CALL_ACPI_PARAMS)); + portMemSet((void *) &pshareParams, 0, sizeof(PFM_REQ_HNDLR_PSHAREDATA)); + + acpiParams.ctrl.cmd = NV0000_CTRL_PFM_REQ_HNDLR_CALL_ACPI_CMD_PSHAREPARAMS; + acpiParams.ctrl.input = DRF_DEF(0000_CTRL_PFM_REQ_HNDLR, _PSHARE_PARAMS, _STATUS_CTGP, _TRUE) | + DRF_DEF(0000_CTRL_PFM_REQ_HNDLR, _PSHARE_PARAMS, _STATUS_QUERY_TYPE, _CURRENT_LIMITS); + acpiParams.output.pBuffer = (NvU8*)&pshareParams; + acpiParams.output.bufferSz = sizeof(pshareParams); + status = pfmreqhndlrCallACPI(pGpu, &acpiParams); + if (status != NV_OK) + { + DBG_BREAKPOINT(); + status = NV_ERR_NOT_SUPPORTED; + goto _pfmreqhndlrHandleUserConfigurableTgpModePlatfromCustomization_exit; + } + + //Set the customization config tgp delta + if (FLD_TEST_DRF(0000_CTRL_PFM_REQ_HNDLR, _PSHARE_PARAMS_STATUS, _CTGP, _TRUE, pshareParams.status)) + { + // Cached the platform limit delta in the PlatformRequestHandler ACPI cache + pPlatformRequestHandler->sensorData.PFMREQHNDLRACPIData.platformLimitDeltamW = pshareParams.ctgp; + + // Config TGP from platform is enabled + pPlatformRequestHandler->controlData.bPlatformUserConfigTGPmodeEnabled = NV_TRUE; + + NV2080_CTRL_CMD_INTERNAL_PMGR_PFM_REQ_HNDLR_CONFIGURE_TURBO_V2_PARAMS params = { 0 }; + RM_API *pRmApi = GPU_GET_PHYSICAL_RMAPI(pGpu); + + params.ctgpOffsetmW = pshareParams.ctgp; + + pRmApi->Control(pRmApi, + pGpu->hInternalClient, + pGpu->hInternalSubdevice, + NV2080_CTRL_CMD_INTERNAL_PMGR_PFM_REQ_HNDLR_CONFIGURE_TURBO_V2, + ¶ms, + sizeof(params)); + } + +_pfmreqhndlrHandleUserConfigurableTgpModePlatfromCustomization_exit: + return status; +} + +/*! + * Reset Platform Power Mode cache on PlatformRequestHandler init and PlatformRequestHandler state unload + * + * @param[in] pPlatformRequestHandler *PlatformRequestHandler pointer + * + */ +static void +_pfmreqhndlrPlatformPowerModeStateReset +( + PlatformRequestHandler *pPlatformRequestHandler +) +{ + PFM_REQ_HNDLR_PPM_DATA *pPpmData = NULL; + + pPpmData = &(pPlatformRequestHandler->ppmData); + + // Init the PPM Cache Data + pPpmData->ppmMaskCurrent = NV0000_CTRL_PFM_REQ_HNDLR_PPM_MASK_INVALID; + pPpmData->ppmIdxCurrent = NV0000_CTRL_PFM_REQ_HNDLR_PPM_INDEX_INVALID; + pPpmData->bWorkItemPending = NV_FALSE; + pPpmData->ppmIdxRequested = NV0000_CTRL_PFM_REQ_HNDLR_PPM_INDEX_INVALID; +} + +/*! + * @brief passive worker thread to communcate EDPpeak info to platform. + * + * @param[in] gpuInstance GPU instance ID + * @param[in] pParams unused +*/ +static void +_pfmreqhndlrHandlePlatformSetEdppLimitInfoWorkItem +( + NvU32 gpuInstance, + void *pParams +) +{ + OBJSYS *pSys = SYS_GET_INSTANCE(); + PlatformRequestHandler *pPlatformRequestHandler = SYS_GET_PFM_REQ_HNDLR(pSys); + OBJGPU *pGpu = + pfmreqhndlrGetGpu(pPlatformRequestHandler); + PFM_REQ_HNDLR_EDPP_DATA *pEdppLimit = + &pPlatformRequestHandler->controlData.edppLimit; + NvU32 status = NV_OK; + NvU32 gpuLockFlag = GPUS_LOCK_FLAGS_NONE; + NvBool lockAcquired = NV_FALSE; + NV0000_CTRL_PFM_REQ_HNDLR_CALL_ACPI_PARAMS + acpiParams; + NV0000_CTRL_PFM_REQ_HNDLR_EDPP_LIMIT_INFO_V1 + edppLimitInfo; + + if (FULL_GPU_SANITY_CHECK(pGpu)) + { + // Attempt to acquire locks/semaphore + if (pfmreqhndlrPassiveModeTransition(NV_TRUE, API_LOCK_FLAGS_NONE, + gpuLockFlag) != NV_OK) + { + NV_PRINTF(LEVEL_ERROR, "Failed to acquire the locks/semaphore!\n"); + goto _pfmreqhndlrHandlePlatformSetEdppLimitInfoWorkItem_exit; + } + lockAcquired = NV_TRUE; + + portMemSet((void*)&acpiParams, 0, sizeof(NV0000_CTRL_PFM_REQ_HNDLR_CALL_ACPI_PARAMS)); + portMemSet((void*)&edppLimitInfo, 0, sizeof(NV0000_CTRL_PFM_REQ_HNDLR_EDPP_LIMIT_INFO_V1)); + + edppLimitInfo.ulVersion = NV0000_CTRL_PFM_REQ_HNDLR_EDPP_VERSION_V10; + edppLimitInfo.limitLast = + pPlatformRequestHandler->sensorData.PFMREQHNDLRACPIData.platformEdppLimit; + + // Fill in the other EDPpeak data if we received them from GPU successfully + if (pEdppLimit->status == NV_OK) + { + edppLimitInfo.limitMin = pEdppLimit->edppLimitInfo.limitMin; + edppLimitInfo.limitRated = pEdppLimit->edppLimitInfo.limitRated; + edppLimitInfo.limitMax = pEdppLimit->edppLimitInfo.limitMax; + edppLimitInfo.limitCurr = pEdppLimit->edppLimitInfo.limitCurr; + edppLimitInfo.limitBattRated = pEdppLimit->edppLimitInfo.limitBattRated; + edppLimitInfo.limitBattMax = pEdppLimit->edppLimitInfo.limitBattMax; + } + + // Call the platform and communicate the EDPp info + acpiParams.ctrl.cmd = NV0000_CTRL_PFM_REQ_HNDLR_CALL_ACPI_CMD_SETEDPPLIMITINFO; + + acpiParams.output.pBuffer = (NvU8*)&edppLimitInfo; + acpiParams.output.bufferSz = sizeof(edppLimitInfo); + + status = pfmreqhndlrCallACPI(pGpu, &acpiParams); + if (status != NV_OK) + { + DBG_BREAKPOINT(); + goto _pfmreqhndlrHandlePlatformSetEdppLimitInfoWorkItem_exit; + } + + } + +_pfmreqhndlrHandlePlatformSetEdppLimitInfoWorkItem_exit: + + // Make workitem available + pEdppLimit->bWorkItemPending = NV_FALSE; + if (lockAcquired) + { + // Release locks/semaphore + pfmreqhndlrPassiveModeTransition(NV_FALSE, API_LOCK_FLAGS_NONE, gpuLockFlag); + } + return; +} + +/* + * NOTE. HOSUNGK. These functions are for backwards compatibility with KMD and NvAPI + * These will be removed after promotion from bugfix_main + */ +NV_STATUS +cliresCtrlCmdSystemGpsCtrl_IMPL +( + RmClientResource *pRmCliRes, + NV0000_CTRL_SYSTEM_GPS_CTRL_PARAMS *pParams +) +{ + return NV_OK; +} + +NV_STATUS +cliresCtrlCmdSystemGpsGetFrmData_IMPL +( + RmClientResource *pRmCliRes, + NV0000_CTRL_SYSTEM_GPS_GET_FRM_DATA_PARAMS *pParams +) +{ + return NV_OK; +} + +NV_STATUS +cliresCtrlCmdSystemGpsSetFrmData_IMPL +( + RmClientResource *pRmCliRes, + NV0000_CTRL_SYSTEM_GPS_SET_FRM_DATA_PARAMS *pParams +) +{ + return NV_OK; +} + +NV_STATUS +cliresCtrlCmdSystemGpsCallAcpi_IMPL +( + RmClientResource *pRmCliRes, + NV0000_CTRL_SYSTEM_GPS_CALL_ACPI_PARAMS *pParams +) +{ + return NV_OK; +} diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/kernel/platform/sli/sli.c nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/kernel/platform/sli/sli.c --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/kernel/platform/sli/sli.c 1970-01-01 00:00:00.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/kernel/platform/sli/sli.c 2024-03-05 22:14:01.000000000 +0000 @@ -0,0 +1,287 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 1999-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +/******************* SLI Routines ******************************************\ +* SLI support * +****************************************************************************/ + +#include "core/core.h" +#include "gpu/gpu.h" +#include "gpu_mgr/gpu_mgr.h" +#include "kernel/gpu/nvlink/kernel_nvlink.h" +#include "nvpcie.h" +#include "os/os.h" +#include "platform/chipset/chipset.h" +#include "platform/platform.h" +#include "platform/sli/sli.h" +#include "gpu_mgr/gpu_mgr_sli.h" + +// Return smallest integer greater than mask with the same number of bits set. +static NvU32 rmSliNextMask(NvU32 mask) +{ + NvU32 r, l; + + r = mask & -(NvS32)mask; // lowest set bit + + mask += r; // replace lowest block by a one left to it + + l = mask & -(NvS32)mask;// first zero beyond lowest block + + l -= r; // lowest block + + while ( 0==(l&1) ) { l >>= 1; } // move block to low end of word + + return mask | (l>>1); // need one bit less of low block +} + +// rmSliSearchForSliCombination +// +// This function looks for all the nWay-SLI configurations with this +// GPU. It as all the valid and non-valid SLI configurations with +// their status. It returns the gpu specfic statuses, and the number +// of valid configs found. +// +static NV_INLINE NvU32 +rmSliSearchForSliCombination(OBJGPU *pGpu, NvU32 nWay, NvU32 numFoundValidConfigs, NvU32 *pGpuSliStatus) +{ + NvU32 gpuAttachCnt; + NvU32 gpuAttachMask; + NvU32 gpuMask; + NvU32 numValidConfigs = 0; + NvU32 mask; + NvU32 smallestMask; + NvU32 largestMask; + NvU32 bit; + NvU32 firstBit = ~0; + NvU32 lastBit = ~0; + NvBool bSliLinkCircular = NV_FALSE; + NvU32 sliLinkTestDone = 0; + NvU32 sliLinkOutputMask = 0; + NvU32 sliLinkEndsMask = 0; + NvU32 vidLinkCount = 0; + NvBool bAnyValid = NV_FALSE; + + // get gpu attach info + gpumgrGetGpuAttachInfo(&gpuAttachCnt, &gpuAttachMask); + + // return if we have less gpus than we request for + if (gpuAttachCnt < nWay) + { + numValidConfigs = 0; + goto rmSliSearchForSliCombination_exit; + } + + gpuAttachMask &= ~NVBIT(pGpu->gpuInstance); + + mask = gpuAttachMask; + // Get the first bit and the last bit set in the 32-bit mask. + for (bit = 0; mask; bit++) + { + if ((firstBit == (NvU32)~0) && (mask & 1)) + { + firstBit = lastBit = bit; + } + else if (mask & 1) + { + lastBit = bit; + } + mask >>= 1; + } + + NV_ASSERT(firstBit != (NvU32)~0); + NV_ASSERT(lastBit != (NvU32)~0); + + if ((firstBit == (NvU32)~0) || (lastBit == (NvU32)~0)) + { + numValidConfigs = 0; + goto rmSliSearchForSliCombination_exit; + } + + smallestMask = ((1 << ((nWay - 1) + firstBit)) - 1) & ~((1 << firstBit) - 1); + largestMask = smallestMask << (lastBit - firstBit - (nWay - 1) + 1); + mask = smallestMask; + + // Search for n-way configs with this gpu. + do + { + + // Look for a mask contained in the GPU mask, + if ((mask & gpuAttachMask) != mask) + { + // Last mask. Exit loop. + if (mask == largestMask) + { + break; + } + mask = rmSliNextMask(mask); + NV_ASSERT(mask); + continue; + } + + gpuMask = NVBIT(pGpu->gpuInstance) | mask; + + // Do Sli link detection + gpumgrDetectSliLinkFromGpus(NV_TRUE, nWay, gpuMask, + &sliLinkTestDone, + &sliLinkOutputMask, + &bSliLinkCircular, + &sliLinkEndsMask, + &vidLinkCount); + + // Last mask. Exit loop. + if (mask == largestMask) + { + break; + } + + mask = rmSliNextMask(mask); + NV_ASSERT(mask); + } while (1); + + if ((numValidConfigs == 0) && bAnyValid) + { + *pGpuSliStatus = NV0000_CTRL_SLI_STATUS_OK; + } + +rmSliSearchForSliCombination_exit: + + return numValidConfigs; +} + +// +// +// RmRunSLISupportCheck +// +// This function establishes the SLI possibilities for the specified GPU. +// The GPU is tested with each previously attached GPU to determine the +// set of valid SLI configurations to which it belongs. +// +static NvU32 RmRunSLISupportCheck +( + OBJGPU *pGpu +) +{ + NvU32 gpuSliStatus = NV0000_CTRL_SLI_STATUS_OK; + NvU32 gpuAttachCnt; + NvU32 gpuAttachMask; + NvU32 numValidConfigs = 0; + NvU32 numXWayValidConfigs; + NvU32 nWay = 0; + + // RMCONFIG: is SLI enabled in this build? + + if (IS_VIRTUAL(pGpu) || IS_GSP_CLIENT(pGpu)) + { + gpuSliStatus |= NV0000_CTRL_SLI_STATUS_GPU_NOT_SUPPORTED; + + // Detect SLI link before failing on GSP client RM + if (!IS_GSP_CLIENT(pGpu)) + goto done; + } + + // get gpu attach info + gpumgrGetGpuAttachInfo(&gpuAttachCnt, &gpuAttachMask); + + // Need more than one gpu to continue. + if (gpuAttachCnt <= 1) + { + // Do not cache this status in pGpu->sliStatus as it is dependent on the GPU count + gpuSliStatus |= NV0000_CTRL_SLI_STATUS_INVALID_GPU_COUNT; + goto done; + } + + // For 9 GPUs and above, we do not check the SLI configs + if(gpuAttachCnt <= 8) + { + for(nWay=2; nWay<=gpuAttachCnt; nWay++) + { + numXWayValidConfigs = rmSliSearchForSliCombination(pGpu, nWay, numValidConfigs, &gpuSliStatus); + numValidConfigs += numXWayValidConfigs; + } + + // + // Cache the gpu status in pGpu->sliStatus in case it has been cleared + // + // NOTE: rmSliSearchForSliCombination() clears gpuSliStatus in case of Base Mosaic and + // Base Mosaic also requires gpu specific slistatus to be OK. Hence gpuSlistatus + // is assigned to gpu specific status again. + // + if (gpuSliStatus == NV0000_CTRL_SLI_STATUS_OK) + { + pGpu->sliStatus = gpuSliStatus; + } + } +done: + NV_PRINTF(LEVEL_INFO, "gpuSliStatus 0x%x\n", gpuSliStatus); + + return numValidConfigs; +} + +// +// +// RmInitScalability +// +// This function calls to establish the SLI possibilities for the specified GPU. +// Then it initalizes any additional SLI attributes. +// +void RmInitScalability +( + OBJGPU *pGpu +) +{ + NvU32 numValidConfigs; + NvU32 gpuMask; + NvU32 idx = 0; + NvU32 gpuLockMask = 0; + + if (IS_GSP_CLIENT(pGpu) && !rmDeviceGpuLockIsOwner(pGpu->gpuInstance)) + NV_ASSERT_OR_RETURN_VOID(rmGpuGroupLockAcquire(pGpu->gpuInstance, + GPU_LOCK_GRP_SUBDEVICE, + GPUS_LOCK_FLAGS_NONE, + RM_LOCK_MODULES_RPC, + &gpuLockMask) == NV_OK); + + // determine the supported SLI configurations. + numValidConfigs = RmRunSLISupportCheck(pGpu); + + if (0 < numValidConfigs) + { + gpuMask = gpumgrGetVidLinkOutputMaskFromGpu(pGpu); + while ((pGpu = gpumgrGetNextGpu(gpuMask, &idx)) != NULL) + { + gpuInitSliIllumination(pGpu); + } + } + + if (gpuLockMask != 0) + rmGpuGroupLockRelease(gpuLockMask, GPUS_LOCK_FLAGS_NONE); +} + + +NV_STATUS RmShutdownScalability +( + OBJGPU *pGpu +) +{ + return NV_OK; +} diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/kernel/power/gpu_boost_mgr.c nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/kernel/power/gpu_boost_mgr.c --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/kernel/power/gpu_boost_mgr.c 2023-10-25 20:21:29.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/kernel/power/gpu_boost_mgr.c 2024-03-05 22:14:02.000000000 +0000 @@ -643,6 +643,8 @@ for (i = 1; i < pBoostConfig->gpuCount; i++) { pGpuItr = gpumgrGetGpuFromId(pBoostConfig->gpuIds[i]); + NV_ASSERT_OR_RETURN(NULL != pGpuItr, NV_ERR_OBJECT_NOT_FOUND); + if (pGpuGrp == gpumgrGetGpuGrpFromGpu(pGpuItr)) { continue; diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/kernel/rmapi/alloc_free.c nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/kernel/rmapi/alloc_free.c --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/kernel/rmapi/alloc_free.c 2023-10-25 20:21:29.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/kernel/rmapi/alloc_free.c 2024-03-05 22:14:02.000000000 +0000 @@ -31,6 +31,7 @@ #include "gpu/disp/disp_objs.h" #include "gpu/disp/disp_channel.h" #include "nvsecurityinfo.h" +#include "virtualization/hypervisor/hypervisor.h" #include "kernel/gpu/mig_mgr/kernel_mig_manager.h" @@ -278,6 +279,9 @@ if (access == LOCK_ACCESS_READ) flags |= RMAPI_LOCK_FLAGS_READ; + if (pLockInfo->flags & RS_LOCK_FLAGS_LOW_PRIORITY) + flags |= RMAPI_LOCK_FLAGS_LOW_PRIORITY; + if ((status = rmapiLockAcquire(flags, RM_LOCK_MODULES_CLIENT)) != NV_OK) { return status; @@ -543,6 +547,7 @@ NvHandle *phObject, NvU32 hClass, NvP64 pUserAllocParams, + NvU32 paramsSize, NvU32 allocFlags, NvU32 allocInitStates, RS_LOCK_INFO *pLockInfo, @@ -565,6 +570,7 @@ rmAllocParams.pSecInfo = &secInfo; rmAllocParams.pResourceRef = NULL; rmAllocParams.pAllocParams = NvP64_VALUE(pUserAllocParams); + rmAllocParams.paramsSize = paramsSize; rmAllocParams.pLockInfo = pLockInfo; rmAllocParams.pRightsRequested = NvP64_VALUE(pRightsRequested); rmAllocParams.pRightsRequired = NULL; @@ -616,6 +622,62 @@ return NV_OK; } +static +NV_STATUS +_serverAllocValidatePrivilege +( + RsServer *pServer, + RS_RESOURCE_DESC *pResDesc, + RS_RES_ALLOC_PARAMS *pParams +) +{ + if (hypervisorIsVgxHyper()) + { + // Host CPU-RM context + // Don't check here, allow it to pass to the inline constructor check. + // TODO: GPUSWSEC-1552 Hypervisor + } + else + { + RS_PRIV_LEVEL privLevel = pParams->pSecInfo->privLevel; + + // Reject allocations for objects with no flags. + if (!(pResDesc->flags & RS_FLAGS_ALLOC_NON_PRIVILEGED) && + !(pResDesc->flags & RS_FLAGS_ALLOC_PRIVILEGED) && + !(pResDesc->flags & RS_FLAGS_ALLOC_KERNEL_PRIVILEGED)) + { + // See GPUSWSEC-1560 for more details on privilege flag requirements + NV_PRINTF(LEVEL_WARNING, "external class 0x%08x is missing its privilege flag in RS_ENTRY\n", pParams->externalClassId); + return NV_ERR_INSUFFICIENT_PERMISSIONS; + } + + // Default case, verify admin and kernel privileges + if (pResDesc->flags & RS_FLAGS_ALLOC_PRIVILEGED) + { + if (privLevel < RS_PRIV_LEVEL_USER_ROOT) + { + NV_PRINTF(LEVEL_WARNING, + "hClient: 0x%08x, externalClassId: 0x%08x: non-privileged context tried to allocate privileged object\n", + pParams->hClient, pParams->externalClassId); + return NV_ERR_INSUFFICIENT_PERMISSIONS; + } + } + + if (pResDesc->flags & RS_FLAGS_ALLOC_KERNEL_PRIVILEGED) + { + if (privLevel < RS_PRIV_LEVEL_KERNEL) + { + NV_PRINTF(LEVEL_WARNING, + "hClient: 0x%08x, externalClassId: 0x%08x: non-privileged context tried to allocate kernel privileged object\n", + pParams->hClient, pParams->externalClassId); + return NV_ERR_INSUFFICIENT_PERMISSIONS; + } + } + } + + return NV_OK; +} + NV_STATUS serverAllocResourceUnderLock ( @@ -656,6 +718,10 @@ NV_ASSERT_OK_OR_RETURN(_fixupAllocParams(&pResDesc, pRmAllocParams)); rmapiResourceDescToLegacyFlags(pResDesc, &pLockInfo->flags, NULL); + status = _serverAllocValidatePrivilege(pServer, pResDesc, pRmAllocParams); + if (status != NV_OK) + goto done; + pLockInfo->traceOp = RS_LOCK_TRACE_ALLOC; pLockInfo->traceClassId = pRmAllocParams->externalClassId; hParent = pRmAllocParams->hParent; @@ -847,15 +913,17 @@ callContext.pLockInfo = pRmAllocParams->pLockInfo; callContext.secInfo = *pRmAllocParams->pSecInfo; - resservSwapTlsCallContext(&pOldContext, &callContext); + NV_ASSERT_OK_OR_GOTO(status, + resservSwapTlsCallContext(&pOldContext, &callContext), done); NV_RM_RPC_ALLOC_OBJECT(pGpu, pRmAllocParams->hClient, pRmAllocParams->hParent, pRmAllocParams->hResource, pRmAllocParams->externalClassId, pRmAllocParams->pAllocParams, + pRmAllocParams->paramsSize, status); - resservRestoreTlsCallContext(pOldContext); + NV_ASSERT_OK(resservRestoreTlsCallContext(pOldContext)); if (status != NV_OK) goto done; @@ -933,10 +1001,6 @@ NvU32 *pReleaseFlags ) { - NvU32 gpuLockFlags = GPUS_LOCK_FLAGS_NONE; - if (access == LOCK_ACCESS_READ) - gpuLockFlags |= GPU_LOCK_FLAGS_READ; - if (*pReleaseFlags & RM_LOCK_RELEASE_GPU_GROUP_LOCK) { // UNLOCK: release GPU group lock @@ -1046,13 +1110,14 @@ NvHandle hParent, NvHandle *phObject, NvU32 hClass, - void *pAllocParams + void *pAllocParams, + NvU32 paramsSize ) { if (!pRmApi->bHasDefaultSecInfo) return NV_ERR_NOT_SUPPORTED; - return pRmApi->AllocWithSecInfo(pRmApi, hClient, hParent, phObject, hClass, NV_PTR_TO_NvP64(pAllocParams), + return pRmApi->AllocWithSecInfo(pRmApi, hClient, hParent, phObject, hClass, NV_PTR_TO_NvP64(pAllocParams), paramsSize, RMAPI_ALLOC_FLAGS_NONE, NvP64_NULL, &pRmApi->defaultSecInfo); } @@ -1064,13 +1129,14 @@ NvHandle hParent, NvHandle hObject, NvU32 hClass, - void *pAllocParams + void *pAllocParams, + NvU32 paramsSize ) { if (!pRmApi->bHasDefaultSecInfo) return NV_ERR_NOT_SUPPORTED; - return pRmApi->AllocWithSecInfo(pRmApi, hClient, hParent, &hObject, hClass, NV_PTR_TO_NvP64(pAllocParams), + return pRmApi->AllocWithSecInfo(pRmApi, hClient, hParent, &hObject, hClass, NV_PTR_TO_NvP64(pAllocParams), paramsSize, RMAPI_ALLOC_FLAGS_NONE, NvP64_NULL, &pRmApi->defaultSecInfo); } @@ -1083,6 +1149,7 @@ NvHandle *phObject, NvU32 hClass, NvP64 pAllocParams, + NvU32 paramsSize, NvU32 flags, NvP64 pRightsRequested, API_SECURITY_INFO *pSecInfo @@ -1141,6 +1208,7 @@ phObject, hClass, pAllocParams, + paramsSize, flags, allocInitStates, pLockInfo, @@ -1272,6 +1340,7 @@ NvHandle *phObject, NvU32 hClass, NvP64 pAllocParams, + NvU32 paramsSize, NvU32 flags, NvP64 pRightsRequested, API_SECURITY_INFO *pSecInfo @@ -1283,7 +1352,7 @@ threadStateInit(&threadState, THREAD_STATE_FLAGS_NONE); status = rmapiAllocWithSecInfo(pRmApi, hClient, hParent, phObject, hClass, - pAllocParams, flags, pRightsRequested, pSecInfo); + pAllocParams, paramsSize, flags, pRightsRequested, pSecInfo); threadStateFree(&threadState, THREAD_STATE_FLAGS_NONE); @@ -1392,7 +1461,7 @@ } NV_STATUS -rmapiFreeClientList +rmapiDisableClients ( RM_API *pRmApi, NvHandle *phClientList, @@ -1402,11 +1471,11 @@ if (!pRmApi->bHasDefaultSecInfo) return NV_ERR_NOT_SUPPORTED; - return pRmApi->FreeClientListWithSecInfo(pRmApi, phClientList, numClients, &pRmApi->defaultSecInfo); + return pRmApi->DisableClientsWithSecInfo(pRmApi, phClientList, numClients, &pRmApi->defaultSecInfo); } NV_STATUS -rmapiFreeClientListWithSecInfo +rmapiDisableClientsWithSecInfo ( RM_API *pRmApi, NvHandle *phClientList, @@ -1414,12 +1483,11 @@ API_SECURITY_INFO *pSecInfo ) { - NV_STATUS status; OBJSYS *pSys = SYS_GET_INSTANCE(); NvU32 lockState = 0; NvU32 i; - NV_PRINTF(LEVEL_INFO, "Nv01FreeClientList: numClients: %d\n", numClients); + NV_PRINTF(LEVEL_INFO, "numClients: %d\n", numClients); if (!pRmApi->bRmSemaInternal && osAcquireRmSema(pSys->pSema) != NV_OK) return NV_ERR_INVALID_LOCK_STATE; @@ -1433,27 +1501,18 @@ for (i = 0; i < numClients; ++i) rmapiControlCacheFreeClientEntry(phClientList[i]); - status = serverFreeClientList(&g_resServ, phClientList, numClients, lockState, pSecInfo); + serverMarkClientListDisabled(&g_resServ, phClientList, numClients, lockState, pSecInfo); if (!pRmApi->bRmSemaInternal) osReleaseRmSema(pSys->pSema, NULL); - if (status == NV_OK) - { - NV_PRINTF(LEVEL_INFO, "Nv01FreeClientList: free complete\n"); - } - else - { - NV_PRINTF(LEVEL_WARNING, - "Nv01FreeList: free failed; status: %s (0x%08x)\n", - nvstatusToString(status), status); - } + NV_PRINTF(LEVEL_INFO, "Disable clients complete\n"); - return status; + return NV_OK; } NV_STATUS -rmapiFreeClientListWithSecInfoTls +rmapiDisableClientsWithSecInfoTls ( RM_API *pRmApi, NvHandle *phClientList, @@ -1466,7 +1525,7 @@ threadStateInit(&threadState, THREAD_STATE_FLAGS_NONE); - status = rmapiFreeClientListWithSecInfo(pRmApi, phClientList, numClients, pSecInfo); + status = rmapiDisableClientsWithSecInfo(pRmApi, phClientList, numClients, pSecInfo); threadStateFree(&threadState, THREAD_STATE_FLAGS_NONE); diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/kernel/rmapi/binary_api.c nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/kernel/rmapi/binary_api.c --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/kernel/rmapi/binary_api.c 2023-10-25 20:21:29.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/kernel/rmapi/binary_api.c 2024-03-05 22:14:02.000000000 +0000 @@ -56,7 +56,7 @@ return NV_OK; } -NV_STATUS +NV_STATUS binapiControl_IMPL ( BinaryApi *pResource, @@ -93,9 +93,9 @@ rmGpuGroupLockRelease(gpuMaskRelease, GPUS_LOCK_FLAGS_NONE); } return status; -} +} -NV_STATUS +NV_STATUS binapiprivControl_IMPL ( BinaryApiPrivileged *pResource, @@ -106,15 +106,15 @@ // check if CMD is NULL, return early if (RMCTRL_IS_NULL_CMD(pParams->cmd)) return NV_OK; - + // Add check if privileged client if (pParams->secInfo.privLevel >= RS_PRIV_LEVEL_USER_ROOT) { return binapiControl_IMPL(staticCast(pResource, BinaryApi), pCallContext, pParams); } - else + else { return NV_ERR_INSUFFICIENT_PERMISSIONS; } -} +} diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/kernel/rmapi/client.c nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/kernel/rmapi/client.c --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/kernel/rmapi/client.c 2023-10-25 20:21:29.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/kernel/rmapi/client.c 2024-03-05 22:14:02.000000000 +0000 @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 1993-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 1993-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -82,6 +82,8 @@ pClient->pSecurityToken = NULL; pClient->pOSInfo = pSecInfo->clientOSInfo; + pClient->cachedPrivilege = pSecInfo->privLevel; + // TODO: Revisit in M2, see GPUSWSEC-1176 if (RMCFG_FEATURE_PLATFORM_GSP && IS_VGPU_GSP_PLUGIN_OFFLOAD_ENABLED(pGpu)) { @@ -96,10 +98,10 @@ else { pClient->ProcID = osGetCurrentProcess(); + if (pClient->cachedPrivilege <= RS_PRIV_LEVEL_USER_ROOT) + pClient->pOsPidInfo = osGetPidInfo(); } - pClient->cachedPrivilege = pSecInfo->privLevel; - // Set user-friendly client name from current process osGetCurrentProcessName(pClient->name, NV_PROC_NAME_MAX_LENGTH); @@ -128,7 +130,7 @@ { NV_PRINTF(LEVEL_WARNING, "NVRM_RPC: Failed to set host client resource handle range %x\n", status); - return status; + goto out; } } @@ -139,7 +141,7 @@ { NV_PRINTF(LEVEL_WARNING, "Failed to set host client restricted resource handle range. Status=%x\n", status); - return status; + goto out; } if (!rmGpuLockIsOwner()) @@ -148,7 +150,7 @@ if ((status = rmGpuLocksAcquire(GPUS_LOCK_FLAGS_NONE, RM_LOCK_MODULES_CLIENT)) != NV_OK) { NV_ASSERT(0); - return status; + goto out; } bReleaseLock = NV_TRUE; } @@ -169,7 +171,7 @@ PUID_TOKEN pUidToken = osGetCurrentUidToken(); UserInfo *pUserInfo = NULL; - if (RMCFG_FEATURE_PLATFORM_GSP && IS_VGPU_GSP_PLUGIN_OFFLOAD_ENABLED(pGpu)) + if (RMCFG_FEATURE_PLATFORM_GSP) { pClient->pSecurityToken = pSecurityToken; } @@ -206,6 +208,13 @@ if (status == NV_OK && pParams->pAllocParams != NULL) *(NvHandle*)(pParams->pAllocParams) = pParams->hClient; +out: + if (status != NV_OK) + { + osPutPidInfo(pClient->pOsPidInfo); + pClient->pOsPidInfo = NULL; + } + return status; } @@ -230,6 +239,8 @@ // Free any association of the client with existing third-party p2p object CliUnregisterFromThirdPartyP2P(pClient); + osPutPidInfo(pClient->pOsPidInfo); + // // Free all of the devices of the client (do it in reverse order to // facilitate tear down of things like ctxdmas, etc) @@ -554,27 +565,21 @@ return NV_OK; } -static RmClient *handleToObject(NvHandle hClient) -{ - RmClient *pClient; - return (NV_OK == serverutilGetClientUnderLock(hClient, &pClient)) ? pClient : NULL; -} - RS_PRIV_LEVEL rmclientGetCachedPrivilegeByHandle(NvHandle hClient) { - RmClient *pClient = handleToObject(hClient); + RmClient *pClient = serverutilGetClientUnderLock(hClient); return pClient ? rmclientGetCachedPrivilege(pClient) : RS_PRIV_LEVEL_USER; } NvBool rmclientIsAdminByHandle(NvHandle hClient, RS_PRIV_LEVEL privLevel) { - RmClient *pClient = handleToObject(hClient); + RmClient *pClient = serverutilGetClientUnderLock(hClient); return pClient ? rmclientIsAdmin(pClient, privLevel) : NV_FALSE; } NvBool rmclientSetClientFlagsByHandle(NvHandle hClient, NvU32 clientFlags) { - RmClient *pClient = handleToObject(hClient); + RmClient *pClient = serverutilGetClientUnderLock(hClient); if (pClient) rmclientSetClientFlags(pClient, clientFlags); return !!pClient; @@ -582,20 +587,20 @@ void rmclientPromoteDebuggerStateByHandle(NvHandle hClient, NvU32 newMinimumState) { - RmClient *pClient = handleToObject(hClient); + RmClient *pClient = serverutilGetClientUnderLock(hClient); if (pClient) _rmclientPromoteDebuggerState(pClient, newMinimumState); } void *rmclientGetSecurityTokenByHandle(NvHandle hClient) { - RmClient *pClient = handleToObject(hClient); + RmClient *pClient = serverutilGetClientUnderLock(hClient); return pClient ? rmclientGetSecurityToken(pClient) : NULL; } NV_STATUS rmclientUserClientSecurityCheckByHandle(NvHandle hClient, const API_SECURITY_INFO *pSecInfo) { - RmClient *pClient = handleToObject(hClient); + RmClient *pClient = serverutilGetClientUnderLock(hClient); // // Return early if it's a null object. This is probably the allocation of @@ -857,7 +862,7 @@ RS_PRIV_LEVEL privLevel ) { - RmClient *pClient = handleToObject(hClient); + RmClient *pClient = serverutilGetClientUnderLock(hClient); if (pClient == NULL) { return NV_FALSE; @@ -888,7 +893,7 @@ NvU32 capability ) { - RmClient *pClient = handleToObject(hClient); + RmClient *pClient = serverutilGetClientUnderLock(hClient); if (pClient == NULL) { return NV_FALSE; @@ -959,7 +964,7 @@ NvU64 key2 = (NvU64)(staticCast(pClient, RsClient))->hClient; OsInfoMapSubmap *pSubmap = NULL; RmClient **pFind = NULL; - + pFind = multimapFindItem(&g_osInfoList, key1, key2); if (pFind != NULL) multimapRemoveItem(&g_osInfoList, pFind); @@ -967,8 +972,8 @@ pSubmap = multimapFindSubmap(&g_osInfoList, key1); if (pSubmap == NULL || multimapCountSubmapItems(&g_osInfoList, pSubmap) > 0) return NV_OK; - + multimapRemoveSubmap(&g_osInfoList, pSubmap); - + return NV_OK; } diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/kernel/rmapi/client_resource.c nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/kernel/rmapi/client_resource.c --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/kernel/rmapi/client_resource.c 2023-10-25 20:21:29.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/kernel/rmapi/client_resource.c 2024-03-05 22:14:02.000000000 +0000 @@ -61,6 +61,7 @@ #include "jt.h" #include "nvop.h" #include "diagnostics/gpu_acct.h" +#include "platform/platform_request_handler.h" #include "gpu/external_device/gsync.h" #include "mem_mgr/virt_mem_mgr.h" #include "diagnostics/journal.h" @@ -210,6 +211,31 @@ return resShareCallback_IMPL(staticCast(pRmCliRes, RsResource), pInvokingClient, pParentRef, pSharePolicy); } +NV_STATUS +cliresControl_Prologue_IMPL +( + RmClientResource *pRmCliRes, + CALL_CONTEXT *pCallContext, + RS_RES_CONTROL_PARAMS_INTERNAL *pParams +) +{ + NV_STATUS status = serverDeserializeCtrlDown(pCallContext, pParams->cmd, &pParams->pParams, &pParams->paramsSize, &pParams->flags); + + return status; +} + +void +cliresControl_Epilogue_IMPL +( + RmClientResource *pRmCliRes, + CALL_CONTEXT *pCallContext, + RS_RES_CONTROL_PARAMS_INTERNAL *pParams +) +{ + NV_ASSERT_OK(serverSerializeCtrlUp(pCallContext, pParams->cmd, &pParams->pParams, &pParams->paramsSize, &pParams->flags)); + serverFreeSerializeStructures(pCallContext, pParams->pParams); +} + // **************************************************************************** // Helper functions // **************************************************************************** @@ -232,7 +258,8 @@ return NV_ERR_INVALID_ARGUMENT; } - if (NV_OK != serverutilGetClientUnderLock(hClient, &pClient)) + pClient = serverutilGetClientUnderLock(hClient); + if (pClient == NULL) return NV_ERR_INVALID_CLIENT; CliGetEventNotificationList(hClient, hClient, NULL, &pEventNotification); @@ -283,9 +310,9 @@ ) { NvU32 Head, Tail; - RmClient *pClient; + RmClient *pClient = serverutilGetClientUnderLock(hClient); - if (NV_OK != serverutilGetClientUnderLock(hClient, &pClient)) + if (pClient == NULL) return NV_ERR_INVALID_CLIENT; Head = pClient->CliSysEventInfo.systemEventsQueue.Head; @@ -819,15 +846,12 @@ NvBool bDoCopyOut = NV_FALSE; void* pInOutData = NULL; NV_STATUS status = NV_OK; - OBJOS *pOS = NULL; pGpu = gpumgrGetSomeGpu(); if (pGpu == NULL) { return NV_ERR_INVALID_REQUEST; } - pOS = GPU_GET_OS(pGpu); - inDataSize = pAcpiMethodParams->inDataSize; outDataSize = pAcpiMethodParams->outDataSize; inOutDataSize = (NvU32) NV_MAX(inDataSize, outDataSize); @@ -865,38 +889,38 @@ { case NV0000_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_DSM_NVOP_OPTIMUSCAPS: { - outStatus = pOS->osCallACPI_DSM(pGpu, - ACPI_DSM_FUNCTION_NVOP, - NVOP_FUNC_OPTIMUSCAPS, - (NvU32*) pInOutData, - &outDataSize); + outStatus = osCallACPI_DSM(pGpu, + ACPI_DSM_FUNCTION_NVOP, + NVOP_FUNC_OPTIMUSCAPS, + (NvU32*) pInOutData, + &outDataSize); break; } case NV0000_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_DSM_NVOP_OPTIMUSFLAG: { - outStatus = pOS->osCallACPI_DSM(pGpu, - ACPI_DSM_FUNCTION_NVOP, - NVOP_FUNC_OPTIMUSFLAG, - (NvU32*) pInOutData, - (NvU16*) &outDataSize); + outStatus = osCallACPI_DSM(pGpu, + ACPI_DSM_FUNCTION_NVOP, + NVOP_FUNC_OPTIMUSFLAG, + (NvU32*) pInOutData, + (NvU16*) &outDataSize); break; } case NV0000_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_DSM_JT_CAPS: { - outStatus = pOS->osCallACPI_DSM(pGpu, - ACPI_DSM_FUNCTION_JT, - JT_FUNC_CAPS, - (NvU32*) pInOutData, - (NvU16*) &outDataSize); + outStatus = osCallACPI_DSM(pGpu, + ACPI_DSM_FUNCTION_JT, + JT_FUNC_CAPS, + (NvU32*) pInOutData, + (NvU16*) &outDataSize); break; } case NV0000_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_DSM_JT_PLATPOLICY: { - outStatus = pOS->osCallACPI_DSM(pGpu, - ACPI_DSM_FUNCTION_JT, - JT_FUNC_PLATPOLICY, - (NvU32*) pInOutData, - (NvU16*) &outDataSize); + outStatus = osCallACPI_DSM(pGpu, + ACPI_DSM_FUNCTION_JT, + JT_FUNC_PLATPOLICY, + (NvU32*) pInOutData, + (NvU16*) &outDataSize); break; } default: @@ -987,7 +1011,7 @@ pCpuInfoParams->family = pSys->cpuInfo.family; pCpuInfoParams->model = pSys->cpuInfo.model; pCpuInfoParams->stepping = pSys->cpuInfo.stepping; - pCpuInfoParams->bSEVEnabled = (sysGetStaticConfig(pSys))->bOsSevEnabled; + pCpuInfoParams->bSEVEnabled = (sysGetStaticConfig(pSys))->bOsCCEnabled; portMemCopy(pCpuInfoParams->name, sizeof (pCpuInfoParams->name), pSys->cpuInfo.name, sizeof (pCpuInfoParams->name)); @@ -1919,6 +1943,99 @@ } +NV_STATUS +cliresCtrlCmdSystemPfmreqhndlrControl_IMPL +( + RmClientResource *pRmCliRes, + NV0000_CTRL_SYSTEM_PFM_REQ_HNDLR_CONTROL_PARAMS *controlParams +) +{ + OBJSYS *pSys = NULL; + PlatformRequestHandler *pPlatformRequestHandler = NULL; + NV_STATUS ret = NV_OK; + NvU32 data = 0; + + pSys = SYS_GET_INSTANCE(); + if (!pSys) + { + return NV_ERR_INVALID_REQUEST; + } + + data = controlParams->data; + + pPlatformRequestHandler = SYS_GET_PFM_REQ_HNDLR(pSys); + if (!pPlatformRequestHandler) + { + return NV_ERR_INVALID_REQUEST; + } + + ret = pfmreqhndlrControl(pPlatformRequestHandler, controlParams->command, controlParams->locale, &data); + + if (NV_OK == ret) + { + controlParams->data = data; + } + else + { + controlParams->data = NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CMD_DEF_INVALID; + } + + return ret; +} + +NV_STATUS +cliresCtrlCmdSystemPfmreqhndlrBatchControl_IMPL +( + RmClientResource *pRmCliRes, + NV0000_CTRL_SYSTEM_PFM_REQ_HNDLR_BATCH_CONTROL_PARAMS *controlParams +) +{ + OBJSYS *pSys = NULL; + PlatformRequestHandler *pPlatformRequestHandler = NULL; + NvU32 data = 0; + NvU32 i = 0; + NvU32 cnt = 0; + + if (controlParams->cmdCount > NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_BATCH_COMMAND_MAX) + { + return NV_ERR_INVALID_REQUEST; + } + + pSys = SYS_GET_INSTANCE(); + if (!pSys) + { + NV_ASSERT(pSys); + return NV_ERR_INVALID_REQUEST; + } + + pPlatformRequestHandler = SYS_GET_PFM_REQ_HNDLR(pSys); + if (!pPlatformRequestHandler) + { + NV_ASSERT(pPlatformRequestHandler); + return NV_ERR_INVALID_REQUEST; + } + + for (i = 0; i < controlParams->cmdCount; i++) + { + data = controlParams->cmdData[i].data; + if (pfmreqhndlrControl(pPlatformRequestHandler, + controlParams->cmdData[i].command, + controlParams->cmdData[i].locale, &data) == NV_OK) + { + controlParams->cmdData[i].data = data; + cnt++; + } + else + { + controlParams->cmdData[i].data = NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CMD_DEF_INVALID; + } + } + + controlParams->succeeded = cnt; + + return NV_OK; +} + /*! * Helper to build config data from unpacked table data, * static config v2.0/2.1. @@ -2500,8 +2617,6 @@ NV0000_CTRL_CMD_SYSTEM_NVPCF_GET_POWER_MODE_INFO_PARAMS *pParams ) { - OBJSYS *pSys = NULL; - OBJOS *pOS = NULL; NvU32 rc = NV_OK; OBJGPU *pGpu = NULL; NV_STATUS status = NV_OK; @@ -2514,20 +2629,6 @@ return NV_ERR_INVALID_REQUEST; } - pSys = SYS_GET_INSTANCE(); - if (pSys == NULL) - { - NV_ASSERT(pSys); - return NV_ERR_INVALID_REQUEST; - } - - pOS = SYS_GET_OS(pSys); - if (pOS == NULL) - { - NV_ASSERT(pOS); - return NV_ERR_INVALID_REQUEST; - } - pGpu = gpumgrGetGpuFromId(pParams->gpuId); if (pGpu == NULL) @@ -2547,11 +2648,11 @@ NvU32 supportedFuncs; dsmDataSize = sizeof(supportedFuncs); - if ((rc = pOS->osCallACPI_DSM(pGpu, - acpiDsmFunction, - acpiDsmSubFunction, - &supportedFuncs, - &dsmDataSize)) != NV_OK) + if ((rc = osCallACPI_DSM(pGpu, + acpiDsmFunction, + acpiDsmSubFunction, + &supportedFuncs, + &dsmDataSize)) != NV_OK) { NV_PRINTF(LEVEL_WARNING, "Unable to retrieve NVPCF supported functions. Possibly not supported by SBIOS " @@ -2587,11 +2688,11 @@ dynamicTable_1x.entries[0] = NVPCF0100_CTRL_DYNAMIC_TABLE_1X_INPUT_CMD_GET_TPP; dsmDataSize = sizeof(dynamicTable_1x); - if ((rc = pOS->osCallACPI_DSM(pGpu, - ACPI_DSM_FUNCTION_NVPCF, - NVPCF0100_CTRL_CONFIG_DSM_1X_FUNC_GET_DYNAMIC_PARAMS, - (NvU32*)(&dynamicTable_1x), - &dsmDataSize)) != NV_OK) + if ((rc = osCallACPI_DSM(pGpu, + ACPI_DSM_FUNCTION_NVPCF, + NVPCF0100_CTRL_CONFIG_DSM_1X_FUNC_GET_DYNAMIC_PARAMS, + (NvU32*)(&dynamicTable_1x), + &dsmDataSize)) != NV_OK) { NV_PRINTF(LEVEL_WARNING, "Unable to retrieve NVPCF dynamic data. Possibly not supported by SBIOS " @@ -2633,7 +2734,7 @@ portMemCopy(pData + sizeof(header), sizeof(common), &common, sizeof(common)); portMemCopy(pData + sizeof(header) + sizeof(common), sizeof(entries), entries, sizeof(entries)); - if ((rc = pOS->osCallACPI_DSM(pGpu, + if ((rc = osCallACPI_DSM(pGpu, ACPI_DSM_FUNCTION_NVPCF_2X, NVPCF0100_CTRL_CONFIG_DSM_2X_FUNC_GET_DYNAMIC_PARAMS, (NvU32 *)pData, @@ -2737,7 +2838,7 @@ pData = portMemAllocNonPaged(dataSize); - if ((rc = pOS->osCallACPI_DSM(pGpu, + if ((rc = osCallACPI_DSM(pGpu, ACPI_DSM_FUNCTION_NVPCF_2X, NVPCF0100_CTRL_CONFIG_DSM_2X_FUNC_GET_STATIC_CONFIG_TABLES, (NvU32 *)pData, @@ -3183,6 +3284,7 @@ ) { OBJGPU *pGpu; + NvBool bLoopback = pP2PParams->gpuCount == 2 && pP2PParams->gpuIds[0] == pP2PParams->gpuIds[1]; if (RMCFG_FEATURE_PLATFORM_GSP) { @@ -3203,7 +3305,7 @@ } return CliGetSystemP2pCaps(pP2PParams->gpuIds, - pP2PParams->gpuCount, + bLoopback ? 1 : pP2PParams->gpuCount, &pP2PParams->p2pCaps, &pP2PParams->p2pOptimalReadCEs, &pP2PParams->p2pOptimalWriteCEs, @@ -3644,9 +3746,9 @@ ) { NvHandle hClient = RES_GET_CLIENT_HANDLE(pRmCliRes); - RmClient *pClient; + RmClient *pClient = serverutilGetClientUnderLock(hClient); - if (NV_OK != serverutilGetClientUnderLock(hClient, &pClient)) + if (pClient == NULL) return NV_ERR_INVALID_CLIENT; pClient->SubProcessID = pParams->subProcessID; @@ -3668,9 +3770,9 @@ ) { NvHandle hClient = RES_GET_CLIENT_HANDLE(pRmCliRes); - RmClient *pClient; + RmClient *pClient = serverutilGetClientUnderLock(hClient); - if (NV_OK != serverutilGetClientUnderLock(hClient, &pClient)) + if (pClient == NULL) return NV_ERR_INVALID_CLIENT; pClient->bIsSubProcessDisabled = pParams->bIsSubProcessDisabled; @@ -3904,6 +4006,7 @@ switch (memType) { case ADDR_SYSMEM: + case ADDR_EGM: pParams->addrSpaceType = NV0000_CTRL_CMD_CLIENT_GET_ADDR_SPACE_TYPE_SYSMEM; break; case ADDR_FBMEM: @@ -4045,9 +4148,10 @@ callContext.pResourceRef = pObjectRef; callContext.secInfo = pCallContext->secInfo; - resservSwapTlsCallContext(&pOldCallContext, &callContext); + NV_ASSERT_OK_OR_RETURN(resservSwapTlsCallContext(&pOldCallContext, &callContext)); + status = clientShareResource(pClient, pObjectRef, pSharePolicy, &callContext); - resservRestoreTlsCallContext(pOldCallContext); + NV_ASSERT_OK(resservRestoreTlsCallContext(pOldCallContext)); if (status != NV_OK) return status; @@ -4173,6 +4277,27 @@ return gpumgrSetGpuInitDisabledNvlinks(pParams->gpuId, pParams->mask, pParams->bSkipHwNvlinkDisable); } +NV_STATUS +cliresCtrlCmdGpuSetNvlinkBwMode_IMPL +( + RmClientResource *pRmCliRes, + NV0000_CTRL_GPU_SET_NVLINK_BW_MODE_PARAMS *pParams +) +{ + return gpumgrSetGpuNvlinkBwMode(pParams->mode); +} + +NV_STATUS +cliresCtrlCmdGpuGetNvlinkBwMode_IMPL +( + RmClientResource *pRmCliRes, + NV0000_CTRL_GPU_GET_NVLINK_BW_MODE_PARAMS *pParams +) +{ + pParams->mode = gpumgrGetGpuNvlinkBwMode(); + return NV_OK; +} + /*! * @brief Get Rcerr Rpt. Returns an Rc Error report form the circular buffer. * @@ -4190,7 +4315,6 @@ NvU32 gpuAttachCount = 0; NvU32 gpuIdx = 0; OBJGPU *pGpu = NULL; - NvU32 processId = osGetCurrentProcess(); NV_ASSERT_OK_OR_RETURN(gpumgrGetGpuAttachInfo(&gpuAttachCount, &gpuMask)); @@ -4205,7 +4329,7 @@ pParams->flags = 0; if (!RMCFG_FEATURE_PLATFORM_GSP) { - pParams->processId = processId; + pParams->processId = osGetCurrentProcess(); } if ((status = krcCliresCtrlNvdGetRcerrRptCheckPermissions_HAL( @@ -4216,75 +4340,66 @@ return status; } - if (IS_GSP_CLIENT(pGpu)) { - NV0000_CTRL_CMD_NVD_GET_RCERR_RPT_PARAMS *pLocalParams = - portMemAllocNonPaged(sizeof *pLocalParams); + Journal *pRcDB = SYS_GET_RCDB(SYS_GET_INSTANCE()); + RmRCCommonJournal_RECORD *pCommon; - NV_CHECK_OR_RETURN(LEVEL_INFO, pLocalParams != NULL, NV_ERR_NO_MEMORY); - - // - // Pre-GSP, RcDiagRec from all GPUs were stored in kernel sysmem in a - // single RING_BUFFER_LOG. - // - // With GSP, each GPU its own separate RING_BUFFER_LOG. We need to - // search in all of them. - // - // However, we will always return only the first matching record in all - // cases (similar to pre-GSP behavior) - // - for (; pGpu != NULL ; pGpu = gpumgrGetNextGpu(gpuMask, &gpuIdx)) + status = rcdbGetRcDiagRecBoundaries(pRcDB, + &pParams->startIdx, + &pParams->endIdx, + pParams->owner, + pParams->processId); + if (status != NV_OK) { - RM_API *pRmApi = GPU_GET_PHYSICAL_RMAPI(pGpu); - portMemSet(pLocalParams, 0, sizeof(*pLocalParams)); - pLocalParams->reqIdx = pParams->reqIdx; - pLocalParams->owner = pParams->owner; - pLocalParams->processId = pParams->processId; - - status = pRmApi->Control(pRmApi, - RES_GET_CLIENT_HANDLE(pRmCliRes), - RES_GET_HANDLE(pRmCliRes), - NV0000_CTRL_CMD_NVD_GET_RCERR_RPT, - pLocalParams, - sizeof *pLocalParams); - if (status == NV_OK && - (pLocalParams->flags & - NV0000_CTRL_CMD_NVD_RCERR_RPT_FLAGS_DATA_VALID)) - { - // - // Each RING_BUFFER_LOG can contain MAX_RCDB_RCDIAG_WRAP_BUFF - // RmRcDiag_RECORD. We will multiply indices returned to the - // client by this value so the GPU can be uniquely identified - // (in addition to GPUTag) from - // NV0000_CTRL_CMD_NVD_GET_RCERR_RPT_PARAMS.rptIdx - // - // Note that this will result in clients receivinga rptIdx value - // larger than MAX_RCDB_RCDIAG_WRAP_BUFF. - // - NvU16 indexOffset = gpuIdx * MAX_RCDB_RCDIAG_WRAP_BUFF; - - *pParams = *pLocalParams; - pParams->startIdx += indexOffset; - pParams->endIdx += indexOffset; - pParams->rptIdx += indexOffset; + return status; + } - break; - } + pParams->flags |= NV0000_CTRL_CMD_NVD_RCERR_RPT_FLAGS_RANGE_VALID; - if (status == NV_ERR_BUSY_RETRY) + { + NV_STATUS localStatus = rcdbGetRcDiagRec(pRcDB, + pParams->reqIdx, + &pCommon, + pParams->owner, + pParams->processId); + switch (localStatus) { - // - // To avoid the case where we silently fail to find a record - // because we skipped over to the next Gpu on getting a - // BUSY_RETRY on one of the Gpus (which might have contained the - // record). - // - break; + case NV_OK: + break; + case NV_ERR_BUSY_RETRY: + return localStatus; + default: + return status; } } - portMemFree(pLocalParams); - pLocalParams = NULL; + if (pCommon != NULL) + { + NvU32 i = 0; + RmRcDiag_RECORD *pRecord = (RmRcDiag_RECORD *)&pCommon[1]; + + pParams->GPUTag = pCommon->GPUTag; + pParams->rptIdx = pRecord->idx; + pParams->rptTime = pRecord->timeStamp; + pParams->rptType = pRecord->type; + pParams->rptCount = pRecord->count; + pParams->flags |= pRecord->flags; + + for (i = 0; i < pRecord->count; ++i) + { + pParams->report[i].tag = pRecord->data[i].tag; + pParams->report[i].value = pRecord->data[i].value; + pParams->report[i].attribute = pRecord->data[i].attribute; + } + for (; i < NV0000_CTRL_CMD_NVD_RCERR_RPT_MAX_ENTRIES; ++i) + { + pParams->report[i].tag = + NV0000_CTRL_CMD_NVD_RCERR_RPT_REG_EMPTY; + pParams->report[i].value = 0; + pParams->report[i].attribute = 0; + } + pParams->flags |= NV0000_CTRL_CMD_NVD_RCERR_RPT_FLAGS_DATA_VALID; + } } return status; @@ -4436,7 +4551,7 @@ ) { NV_STATUS status = NV_OK; - portMemSet(pParams, 0, sizeof(*pParams)); + status = pfmreqhndlrGetPerfSensorCounters(pParams, PFM_REQ_HNDLR_PSR_PUB_TAG); return status; } @@ -4448,11 +4563,30 @@ ) { NV_STATUS status = NV_OK; - portMemSet(pParams, 0, sizeof(*pParams)); + status = pfmreqhndlrGetPerfSensorCounters(pParams, 0); return status; } // GPS HOSUNGK DELETE after KMD, NvAPI changes are made +NV_STATUS +cliresCtrlCmdSystemGpsControl_IMPL +( + RmClientResource *pRmCliRes, + NV0000_CTRL_SYSTEM_GPS_CONTROL_PARAMS *controlParams +) +{ + return NV_OK; +} + +NV_STATUS +cliresCtrlCmdSystemGpsBatchControl_IMPL +( + RmClientResource *pRmCliRes, + NV0000_CTRL_SYSTEM_GPS_BATCH_CONTROL_PARAMS *controlParams +) +{ + return NV_OK; +} NV_STATUS cliresCtrlCmdSystemGetPerfSensorCounters_IMPL @@ -4473,3 +4607,4 @@ { return NV_OK; } + diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/kernel/rmapi/client_resource_sli.c nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/kernel/rmapi/client_resource_sli.c --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/kernel/rmapi/client_resource_sli.c 1970-01-01 00:00:00.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/kernel/rmapi/client_resource_sli.c 2024-03-05 22:14:02.000000000 +0000 @@ -0,0 +1,52 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2020-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#include "core/core.h" +#include "core/locks.h" +#include "rmapi/client_resource.h" + +#include "platform/sli/sli.h" +#include "resserv/rs_client.h" +#include "resserv/rs_server.h" +#include "resserv/rs_access_map.h" + +#include "ctrl/ctrl0000/ctrl0000gpu.h" + +// +// cliresCtrlCmdGpuGetVideoLinks +// +// Lock Requirements: +// Assert that API lock held on entry +// No GPUs lock +// +NV_STATUS +cliresCtrlCmdGpuGetVideoLinks_IMPL +( + RmClientResource *pRmCliRes, + NV0000_CTRL_GPU_GET_VIDEO_LINKS_PARAMS *pParams +) +{ + LOCK_ASSERT_AND_RETURN(rmapiLockIsOwner()); + + return gpumgrGetSliLinks(pParams); +} diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/kernel/rmapi/control.c nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/kernel/rmapi/control.c --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/kernel/rmapi/control.c 2023-10-25 20:21:30.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/kernel/rmapi/control.c 2024-03-05 22:14:02.000000000 +0000 @@ -69,7 +69,6 @@ rmControl_Deferred(RmCtrlDeferredCmd* pRmCtrlDeferredCmd) { RmCtrlParams rmCtrlParams; - RmClient *pClient; NvU8 paramBuffer[RMCTRL_DEFERRED_MAX_PARAM_SIZE]; NV_STATUS status; RS_LOCK_INFO lockInfo = {0}; @@ -108,7 +107,7 @@ // client was checked when we came in through rmControl() // but check again to make sure it's still good - if (serverutilGetClientUnderLock(rmCtrlParams.hClient, &pClient) != NV_OK) + if (serverutilGetClientUnderLock(rmCtrlParams.hClient) == NULL) { status = NV_ERR_INVALID_CLIENT; goto exit; @@ -262,8 +261,11 @@ RMAPI_PARAM_COPY_INIT(*pParamCopy, pRmCtrlParams->pParams, pUserParams, 1, paramsSize); - if (pCookie->apiCopyFlags & RMCTRL_API_COPY_FLAGS_SKIP_COPYIN) + if (pCookie->apiCopyFlags & RMCTRL_API_COPY_FLAGS_SKIP_COPYIN_ZERO_BUFFER) + { pParamCopy->flags |= RMAPI_PARAM_COPY_FLAGS_SKIP_COPYIN; + pParamCopy->flags |= RMAPI_PARAM_COPY_FLAGS_ZERO_BUFFER; + } rmStatus = rmapiParamsAcquire(pParamCopy, (pRmCtrlParams->secInfo.paramLocation == PARAM_LOCATION_USER)); if (rmStatus != NV_OK) @@ -272,7 +274,12 @@ rmStatus = embeddedParamCopyIn(pEmbeddedParamCopies, pRmCtrlParams); if (rmStatus != NV_OK) + { + rmapiParamsRelease(pParamCopy); + pRmCtrlParams->pParams = NvP64_VALUE(pUserParams); + pCookie->bFreeParamCopy = NV_FALSE; return rmStatus; + } pCookie->bFreeEmbeddedCopy = NV_TRUE; return NV_OK; @@ -388,7 +395,6 @@ _rmapiRmControl(NvHandle hClient, NvHandle hObject, NvU32 cmd, NvP64 pUserParams, NvU32 paramsSize, NvU32 flags, RM_API *pRmApi, API_SECURITY_INFO *pSecInfo) { OBJSYS *pSys = SYS_GET_INSTANCE(); - RmClient *pClient; RmCtrlParams rmCtrlParams; RS_CONTROL_COOKIE rmCtrlExecuteCookie = {0}; NvBool bIsRaisedIrqlCmd; @@ -396,6 +402,10 @@ NvBool bInternalRequest; NV_STATUS rmStatus = NV_OK; RS_LOCK_INFO lockInfo = {0}; + NvU32 ctrlFlags = 0; + NvU32 ctrlAccessRight = 0; + NvU32 ctrlParamsSize = 0; + NV_STATUS getCtrlInfoStatus; RMTRACE_RMAPI(_RMCTRL_ENTRY, cmd); @@ -464,7 +474,7 @@ } // Potential race condition if run lockless? - if (serverutilGetClientUnderLock(hClient, &pClient) != NV_OK) + if (serverutilGetClientUnderLock(hClient) == NULL) { rmStatus = NV_ERR_INVALID_CLIENT; goto done; @@ -482,12 +492,17 @@ } } + getCtrlInfoStatus = rmapiutilGetControlInfo(cmd, &ctrlFlags, &ctrlAccessRight, &ctrlParamsSize); + // error check parameters - if (((paramsSize != 0) && (pUserParams == (NvP64) 0)) || - ((paramsSize == 0) && (pUserParams != (NvP64) 0))) + if (((paramsSize != 0) && (pUserParams == (NvP64) 0)) || + ((paramsSize == 0) && (pUserParams != (NvP64) 0)) + || ((getCtrlInfoStatus == NV_OK) && (paramsSize != ctrlParamsSize)) + ) { - NV_PRINTF(LEVEL_WARNING, "bad params: ptr " NvP64_fmt " size: 0x%x\n", - pUserParams, paramsSize); + NV_PRINTF(LEVEL_WARNING, + "bad params: cmd:0x%x ptr " NvP64_fmt " size: 0x%x expect size: 0x%x\n", + cmd, pUserParams, paramsSize, ctrlParamsSize); rmStatus = NV_ERR_INVALID_ARGUMENT; goto done; } @@ -514,6 +529,17 @@ lockInfo.flags |= RM_LOCK_FLAGS_NO_API_LOCK; } + if (getCtrlInfoStatus == NV_OK) + { + // + // The output of CACHEABLE RMCTRL do not depend on the input. + // Skip param copy and clear the buffer in case the uninitialized + // buffer leaks information to clients. + // + if (ctrlFlags & RMCTRL_FLAGS_CACHEABLE) + rmCtrlParams.pCookie->apiCopyFlags |= RMCTRL_API_COPY_FLAGS_SKIP_COPYIN_ZERO_BUFFER; + } + // // Three separate rmctrl command modes: // @@ -574,24 +600,41 @@ // Normal rmctrl request. // - if (rmapiCmdIsCacheable(cmd, NV_FALSE)) + if (getCtrlInfoStatus == NV_OK) { - rmCtrlParams.pCookie->apiCopyFlags |= RMCTRL_API_COPY_FLAGS_SKIP_COPYIN; - rmCtrlParams.pCookie->apiCopyFlags |= RMCTRL_API_COPY_FLAGS_FORCE_SKIP_COPYOUT_ON_ERROR; + if (rmapiControlIsCacheable(ctrlFlags, ctrlAccessRight, NV_FALSE)) + { + rmCtrlParams.pCookie->apiCopyFlags |= RMCTRL_API_COPY_FLAGS_FORCE_SKIP_COPYOUT_ON_ERROR; - serverControlApiCopyIn(&g_resServ, &rmCtrlParams, rmCtrlParams.pCookie); - rmStatus = rmapiControlCacheGet(hClient, hObject, cmd, rmCtrlParams.pParams, paramsSize); - serverControlApiCopyOut(&g_resServ, &rmCtrlParams, rmCtrlParams.pCookie, rmStatus); + rmStatus = serverControlApiCopyIn(&g_resServ, &rmCtrlParams, + rmCtrlParams.pCookie); + if (rmStatus == NV_OK) + { + rmStatus = rmapiControlCacheGet(hClient, hObject, cmd, + rmCtrlParams.pParams, + paramsSize); + + // rmStatus is passed in for error handling + rmStatus = serverControlApiCopyOut(&g_resServ, + &rmCtrlParams, + rmCtrlParams.pCookie, + rmStatus); + } - if (rmStatus == NV_OK) - { - goto done; - } - else - { - // reset cookie if cache get failed - portMemSet(rmCtrlParams.pCookie, 0, sizeof(RS_CONTROL_COOKIE)); - rmCtrlParams.pCookie->apiCopyFlags |= RMCTRL_API_COPY_FLAGS_SET_CONTROL_CACHE; + if (rmStatus == NV_OK) + { + goto done; + } + else + { + // reset cookie if cache get failed + portMemSet(rmCtrlParams.pCookie, 0, sizeof(RS_CONTROL_COOKIE)); + rmCtrlParams.pCookie->apiCopyFlags |= RMCTRL_API_COPY_FLAGS_SET_CONTROL_CACHE; + + // re-initialize the flag if it's cleaned + if (ctrlFlags & RMCTRL_FLAGS_CACHEABLE) + rmCtrlParams.pCookie->apiCopyFlags |= RMCTRL_API_COPY_FLAGS_SKIP_COPYIN_ZERO_BUFFER; + } } } @@ -822,7 +865,7 @@ NvU32 controlFlags = pRmCtrlExecuteCookie->ctrlFlags; if (controlFlags == 0 && !RMCFG_FEATURE_PLATFORM_GSP && areAllGpusInOffloadMode) { - NV_STATUS status = rmapiutilGetControlInfo(pRmCtrlParams->cmd, &controlFlags, NULL); + NV_STATUS status = rmapiutilGetControlInfo(pRmCtrlParams->cmd, &controlFlags, NULL, NULL); if (status != NV_OK) { NV_PRINTF(LEVEL_INFO, @@ -856,7 +899,7 @@ return NV_OK; } - if (pRmCtrlExecuteCookie->ctrlFlags & RMCTRL_FLAGS_API_LOCK_READONLY) + if (controlFlags & RMCTRL_FLAGS_API_LOCK_READONLY) { *pAccess = LOCK_ACCESS_READ; } @@ -883,7 +926,7 @@ // we already own the GPUs Lock. // if ((pLockInfo->state & RM_LOCK_STATES_GPUS_LOCK_ACQUIRED) || - (pRmCtrlExecuteCookie->ctrlFlags & RMCTRL_FLAGS_NO_GPUS_LOCK) || + (controlFlags & RMCTRL_FLAGS_NO_GPUS_LOCK) || (pRmCtrlParams->flags & NVOS54_FLAGS_IRQL_RAISED) || (pRmCtrlParams->flags & NVOS54_FLAGS_LOCK_BYPASS)) { @@ -892,7 +935,7 @@ } else { - if ((pRmCtrlExecuteCookie->ctrlFlags & RMCTRL_FLAGS_GPU_LOCK_DEVICE_ONLY) || + if ((controlFlags & RMCTRL_FLAGS_GPU_LOCK_DEVICE_ONLY) || (g_resServ.bRouteToPhysicalLockBypass && bUseGspLockingMode)) { pLockInfo->flags |= RM_LOCK_FLAGS_NO_GPUS_LOCK; @@ -904,7 +947,7 @@ pLockInfo->flags &= ~RM_LOCK_FLAGS_GPU_GROUP_LOCK; } - if (pRmCtrlExecuteCookie->ctrlFlags & RMCTRL_FLAGS_GPU_LOCK_READONLY) + if (controlFlags & RMCTRL_FLAGS_GPU_LOCK_READONLY) *pAccess = LOCK_ACCESS_READ; } @@ -991,7 +1034,7 @@ NV_STATUS status; THREAD_STATE_NODE threadState; - NvU8 stackAllocator[TLS_ISR_ALLOCATOR_SIZE]; + NvU8 stackAllocator[2*TLS_ISR_ALLOCATOR_SIZE]; PORT_MEM_ALLOCATOR* pIsrAllocator = portMemAllocatorCreateOnExistingBlock(stackAllocator, sizeof(stackAllocator)); tlsIsrInit(pIsrAllocator); diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/kernel/rmapi/deprecated_context.c nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/kernel/rmapi/deprecated_context.c --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/kernel/rmapi/deprecated_context.c 2023-10-25 20:21:30.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/kernel/rmapi/deprecated_context.c 2024-03-05 22:14:03.000000000 +0000 @@ -29,13 +29,13 @@ static NV_STATUS _rmAllocForDeprecatedApi(DEPRECATED_CONTEXT *_pContext, NvHandle hClient, NvHandle hParent, - NvHandle *phObject, NvU32 hClass, void *pAllocParams) + NvHandle *phObject, NvU32 hClass, void *pAllocParams, NvU32 paramsSize) { DEPRECATED_CONTEXT_EXT *pContext = (DEPRECATED_CONTEXT_EXT *)_pContext; RM_API *pRmApi = pContext->pRmApi; return pRmApi->AllocWithSecInfo(pRmApi, hClient, hParent, phObject, - hClass, NV_PTR_TO_NvP64(pAllocParams), + hClass, NV_PTR_TO_NvP64(pAllocParams), paramsSize, RMAPI_ALLOC_FLAGS_NONE, NvP64_NULL, &pContext->secInfo); } diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/kernel/rmapi/embedded_param_copy.c nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/kernel/rmapi/embedded_param_copy.c --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/kernel/rmapi/embedded_param_copy.c 2023-10-25 20:21:30.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/kernel/rmapi/embedded_param_copy.c 2024-03-05 22:14:03.000000000 +0000 @@ -218,7 +218,8 @@ NvU32 paramsCnt = 1; NvU32 i, j = 0; - if (pRmCtrlParams->secInfo.paramLocation == PARAM_LOCATION_KERNEL) + if ((pRmCtrlParams->secInfo.paramLocation == PARAM_LOCATION_KERNEL) || + (pRmCtrlParams->flags & NVOS54_FLAGS_FINN_SERIALIZED)) { return NV_OK; } @@ -765,7 +766,8 @@ NV_STATUS status = NV_OK; void* pParams = pRmCtrlParams->pParams; - if (pRmCtrlParams->secInfo.paramLocation == PARAM_LOCATION_KERNEL) + if ((pRmCtrlParams->secInfo.paramLocation == PARAM_LOCATION_KERNEL) || + (pRmCtrlParams->flags & NVOS54_FLAGS_FINN_SERIALIZED)) { return NV_OK; } @@ -886,7 +888,7 @@ case NV83DE_CTRL_CMD_DEBUG_WRITE_MEMORY: { CHECK_PARAMS_OR_RETURN(pRmCtrlParams, NV83DE_CTRL_DEBUG_WRITE_MEMORY_PARAMS); - + status = rmapiParamsRelease(¶mCopies[0]); ((NV83DE_CTRL_DEBUG_WRITE_MEMORY_PARAMS*)pRmCtrlParams->pParams)->buffer = paramCopies[0].pUserParams; break; diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/kernel/rmapi/entry_points.c nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/kernel/rmapi/entry_points.c --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/kernel/rmapi/entry_points.c 2023-10-25 20:21:30.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/kernel/rmapi/entry_points.c 2024-03-05 22:14:03.000000000 +0000 @@ -217,7 +217,7 @@ XlateUserModeArgsToSecInfo(bUserModeArgs, NV_FALSE, &secInfo); pArgs->status = pRmApi->AllocWithSecInfo(pRmApi, pArgs->hRoot, pArgs->hObjectParent, &pArgs->hObjectNew, - pArgs->hClass, pArgs->pAllocParms, RMAPI_ALLOC_FLAGS_NONE, + pArgs->hClass, pArgs->pAllocParms, pArgs->paramsSize, RMAPI_ALLOC_FLAGS_NONE, NvP64_NULL, &secInfo); } // end of Nv04Alloc() @@ -241,7 +241,7 @@ RM_API *pRmApi = rmapiGetInterface(RMAPI_EXTERNAL); pArgs->status = pRmApi->AllocWithSecInfo(pRmApi, pArgs->hRoot, pArgs->hObjectParent, &pArgs->hObjectNew, - pArgs->hClass, pArgs->pAllocParms, RMAPI_ALLOC_FLAGS_NONE, + pArgs->hClass, pArgs->pAllocParms, pArgs->paramsSize, RMAPI_ALLOC_FLAGS_NONE, NvP64_NULL, &secInfo); } // end of _nv04AllocWithSecInfo() @@ -264,12 +264,16 @@ ) { RM_API *pRmApi = rmapiGetInterface(RMAPI_EXTERNAL); + NvU32 flags = RMAPI_ALLOC_FLAGS_NONE; API_SECURITY_INFO secInfo; XlateUserModeArgsToSecInfo(bUserModeArgs, NV_FALSE, &secInfo); + if (pArgs->flags & NVOS64_FLAGS_FINN_SERIALIZED) + flags |= RMAPI_ALLOC_FLAGS_SERIALIZED; + pArgs->status = pRmApi->AllocWithSecInfo(pRmApi, pArgs->hRoot, pArgs->hObjectParent, &pArgs->hObjectNew, - pArgs->hClass, pArgs->pAllocParms, RMAPI_ALLOC_FLAGS_NONE, + pArgs->hClass, pArgs->pAllocParms, pArgs->paramsSize, flags, pArgs->pRightsRequested, &secInfo); } // end of _nv04AllocWithAccess() @@ -280,9 +284,13 @@ ) { RM_API *pRmApi = rmapiGetInterface(RMAPI_EXTERNAL); + NvU32 flags = RMAPI_ALLOC_FLAGS_NONE; + + if (pArgs->flags & NVOS64_FLAGS_FINN_SERIALIZED) + flags |= RMAPI_ALLOC_FLAGS_SERIALIZED; pArgs->status = pRmApi->AllocWithSecInfo(pRmApi, pArgs->hRoot, pArgs->hObjectParent, &pArgs->hObjectNew, - pArgs->hClass, pArgs->pAllocParms, RMAPI_ALLOC_FLAGS_NONE, + pArgs->hClass, pArgs->pAllocParms, pArgs->paramsSize, flags, pArgs->pRightsRequested, &secInfo); } // end of _nv04AllocWithAccessSecInfo() diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/kernel/rmapi/entry_points.h nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/kernel/rmapi/entry_points.h --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/kernel/rmapi/entry_points.h 2023-10-25 20:21:30.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/kernel/rmapi/entry_points.h 2024-03-05 22:14:03.000000000 +0000 @@ -35,7 +35,8 @@ NvHandle hParent, NvHandle *phObject, NvU32 hClass, - void *pAllocParams + void *pAllocParams, + NvU32 paramsSize ); NV_STATUS @@ -46,7 +47,8 @@ NvHandle hParent, NvHandle hObject, NvU32 hClass, - void *pAllocParams + void *pAllocParams, + NvU32 paramsSize ); NV_STATUS @@ -58,6 +60,7 @@ NvHandle *phObject, NvU32 hClass, NvP64 pAllocParams, + NvU32 paramsSize, NvU32 flags, NvP64 pRightsRequired, API_SECURITY_INFO *pSecInfo @@ -72,6 +75,7 @@ NvHandle *phObject, NvU32 hClass, NvP64 pAllocParams, + NvU32 paramsSize, NvU32 flags, NvP64 pRightsRequired, API_SECURITY_INFO *pSecInfo @@ -106,7 +110,7 @@ ); NV_STATUS -rmapiFreeClientList +rmapiDisableClients ( RM_API *pRmApi, NvHandle *phClientList, @@ -114,7 +118,7 @@ ); NV_STATUS -rmapiFreeClientListWithSecInfo +rmapiDisableClientsWithSecInfo ( RM_API *pRmApi, NvHandle *phClientList, @@ -123,7 +127,7 @@ ); NV_STATUS -rmapiFreeClientListWithSecInfoTls +rmapiDisableClientsWithSecInfoTls ( RM_API *pRmApi, NvHandle *phClientList, diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/kernel/rmapi/event.c nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/kernel/rmapi/event.c --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/kernel/rmapi/event.c 2023-10-25 20:21:30.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/kernel/rmapi/event.c 2024-03-05 22:14:03.000000000 +0000 @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 1993-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 1993-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -188,7 +188,7 @@ if (rmStatus == NV_OK) rmStatus = registerEventNotification(ppEventNotification, - pRsClient->hClient, + pRsClient, pEvent->hNotifierResource, pResourceRef->hResource, pNv0050AllocParams->notifyIndex, @@ -285,9 +285,11 @@ // host, if we are in guest OS (where IS_VIRTUAL(pGpu) is true), // do an RPC to the host to do the hardware update. // - if (IS_VIRTUAL_WITHOUT_SRIOV(pGpu) || + if ( + !(IS_GSP_CLIENT(pGpu) && (pNotifierRef->internalClassId == classId(KernelHostVgpuDeviceApi))) && + (IS_VIRTUAL_WITHOUT_SRIOV(pGpu) || (IS_GSP_CLIENT(pGpu) && pNotifierRef->internalClassId != classId(ContextDma)) || - (IS_VIRTUAL_WITH_SRIOV(pGpu) && !((*ppEventNotification)->bNonStallIntrEvent))) + (IS_VIRTUAL_WITH_SRIOV(pGpu) && !((*ppEventNotification)->bNonStallIntrEvent)))) { // // In SR-IOV enabled systems, nonstall events are registered @@ -494,11 +496,11 @@ Event **ppEvent ) { - RmClient *pClient; RsClient *pRsClient; RsResourceRef *pResourceRef; + RmClient *pClient = serverutilGetClientUnderLock(hClient); - if (NV_OK != serverutilGetClientUnderLock(hClient, &pClient)) + if (pClient == NULL) return NV_FALSE; pRsClient = staticCast(pClient, RsClient); diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/kernel/rmapi/event_buffer.c nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/kernel/rmapi/event_buffer.c --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/kernel/rmapi/event_buffer.c 2023-10-25 20:21:30.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/kernel/rmapi/event_buffer.c 2024-03-05 22:14:03.000000000 +0000 @@ -208,7 +208,7 @@ RM_API *pRmApi = rmapiGetInterface(RMAPI_GPU_LOCK_INTERNAL); NvHandle hMemory = RES_GET_HANDLE(pMemory); - if (!bKernel) + if ((!bKernel) && bUsingVgpuStagingBuffer) { status = pRmApi->DupObject(pRmApi, hMapperClient, @@ -269,7 +269,7 @@ RM_API *pRmApi = rmapiGetInterface(RMAPI_GPU_LOCK_INTERNAL); NvHandle hMemory = RES_GET_HANDLE(pMemory); - if (!bKernel) + if ((!bKernel) && bUsingVgpuStagingBuffer) { status = pRmApi->DupObject(pRmApi, hMapperClient, @@ -330,7 +330,7 @@ RM_API *pRmApi = rmapiGetInterface(RMAPI_GPU_LOCK_INTERNAL); NvHandle hMemory = RES_GET_HANDLE(pMemory); - if (!bKernel) + if ((!bKernel) && bUsingVgpuStagingBuffer) { status = pRmApi->DupObject(pRmApi, hMapperClient, @@ -619,9 +619,7 @@ // NvTelemetry requires a valid subdevice if (updateTelemetry && pEventBuffer->hSubDevice) { - NvHandle hClient = RES_GET_CLIENT_HANDLE(pEventBuffer); - NvHandle hDevice; - OBJGPU *pGpu; + Subdevice *pSubDevice; status = rmGpuGroupLockAcquire(pEventBuffer->subDeviceInst, GPU_LOCK_GRP_SUBDEVICE, @@ -630,7 +628,12 @@ if (status != NV_OK) return status; - status = CliSetSubDeviceContext(hClient, pEventBuffer->hSubDevice, &hDevice, &pGpu); + status = subdeviceGetByHandle(RES_GET_CLIENT(pEventBuffer), + pEventBuffer->hSubDevice, &pSubDevice); + if (status != NV_OK) + return status; + + GPU_RES_SET_THREAD_BC_STATE(pSubDevice); rmGpuGroupLockRelease(gpuMask, GPUS_LOCK_FLAGS_NONE); } diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/kernel/rmapi/event_notification.c nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/kernel/rmapi/event_notification.c --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/kernel/rmapi/event_notification.c 2023-10-25 20:21:30.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/kernel/rmapi/event_notification.c 2024-03-05 22:14:03.000000000 +0000 @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 1993-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 1993-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -361,7 +361,7 @@ // // Iterate through the pending notifications and call the OS to send them. // Note that osNotifyEvent may need to be preemptible, so this is done - // outside of the spinlock-protected critical section. + // outside of the spinlock-protected critical section. // PendingEventNotifyListIter it = listIterAll(pPending); while (listIterNext(&it)) @@ -559,7 +559,7 @@ NV_STATUS registerEventNotification ( PEVENTNOTIFICATION *ppEventNotification, - NvHandle hEventClient, + RsClient *pEventClient, NvHandle hNotifier, NvHandle hEvent, NvU32 NotifyIndex, @@ -568,13 +568,13 @@ NvBool bUserOsEventHandle ) { + NvHandle hEventClient = pEventClient->hClient; Subdevice *pSubDevice; PEVENTNOTIFICATION pTargetEvent = NULL; NV_STATUS rmStatus = NV_OK, rmTmpStatus = NV_OK; OBJGPU *pGpu; NvBool bNonStallIntrEvent = NV_FALSE; RM_ENGINE_TYPE rmEngineId; - NvHandle hDevice; RsResourceRef *pResourceRef; Memory *pSemMemory = NULL; @@ -592,7 +592,7 @@ // For non-stall interrupt, the event parent type is NV20_SUBDEVICE, so we can locate // the correct OBJGPU and attach to its per-engine non-stall event list. // - if ((serverutilGetResourceRef(hEventClient, hNotifier, &pResourceRef) != NV_OK) || + if ((clientGetResourceRef(pEventClient, hNotifier, &pResourceRef) != NV_OK) || (!dynamicCast(pResourceRef->pResource, Subdevice))) { rmStatus = NV_ERR_INVALID_ARGUMENT; @@ -600,13 +600,10 @@ } pSubDevice = dynamicCast(pResourceRef->pResource, Subdevice); - hDevice = RES_GET_PARENT_HANDLE(pSubDevice); - if (CliSetSubDeviceContext(hEventClient, RES_GET_HANDLE(pSubDevice), &hDevice, &pGpu) != NV_OK) - { - rmStatus = NV_ERR_INVALID_ARGUMENT; - goto free_entry; - } + pGpu = GPU_RES_GET_GPU(pSubDevice); + + GPU_RES_SET_THREAD_BC_STATE(pSubDevice); rmStatus = eventGetEngineTypeFromSubNotifyIndex( DRF_VAL(0005, _NOTIFY_INDEX, _INDEX, NotifyIndex), &rmEngineId); @@ -789,7 +786,6 @@ PEVENTNOTIFICATION pTargetEvent = NULL; Subdevice *pSubDevice; RsResourceRef *pResourceRef; - NvHandle hDevice; RM_ENGINE_TYPE rmEngineId; OBJGPU *pGpu; @@ -813,13 +809,11 @@ } pSubDevice = dynamicCast(pResourceRef->pResource, Subdevice); - hDevice = RES_GET_PARENT_HANDLE(pSubDevice); - if (CliSetSubDeviceContext(hEventClient, RES_GET_HANDLE(pSubDevice), &hDevice, &pGpu) != NV_OK) - { - rmStatus = NV_ERR_INVALID_ARGUMENT; - goto free_entry; - } + // Fetch pGpu and hDevice, set the threadstate to the pGpu + pGpu = GPU_RES_GET_GPU(pSubDevice); + + GPU_RES_SET_THREAD_BC_STATE(pSubDevice); rmStatus = eventGetEngineTypeFromSubNotifyIndex(pTargetEvent->NotifyIndex, &rmEngineId); diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/kernel/rmapi/mapping.c nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/kernel/rmapi/mapping.c --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/kernel/rmapi/mapping.c 2023-10-25 20:21:30.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/kernel/rmapi/mapping.c 2024-03-05 22:14:04.000000000 +0000 @@ -35,7 +35,7 @@ #include "gpu/mem_mgr/mem_desc.h" #include "gpu/mem_mgr/mem_mgr.h" -static NvU32 +static NvU64 _getMappingPageSize ( RsResourceRef *pMappableRef @@ -113,7 +113,7 @@ if (pVirtualMemory != NULL) { - NvU32 pageSize = RM_PAGE_SIZE; + NvU64 pageSize = RM_PAGE_SIZE; if (pVirtualMemory->bOptimizePageTableMempoolUsage) { diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/kernel/rmapi/mapping_cpu.c nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/kernel/rmapi/mapping_cpu.c --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/kernel/rmapi/mapping_cpu.c 2023-10-25 20:21:31.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/kernel/rmapi/mapping_cpu.c 2024-03-05 22:14:04.000000000 +0000 @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 1993-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 1993-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -48,6 +48,8 @@ static void RmUnmapBusAperture (OBJGPU *, NvP64, NvU64, NvBool, NvP64); +#include "gpu/conf_compute/conf_compute.h" + typedef struct RS_CPU_MAP_PARAMS RmMapParams; typedef struct RS_CPU_UNMAP_PARAMS RmUnmapParams; @@ -176,8 +178,7 @@ KernelBus *pKernelBus = NULL; MemoryManager *pMemoryManager = NULL; KernelMemorySystem *pKernelMemorySystem = NULL; - RsClient *pRsClient; - RmClient *pRmClient; + RmClient *pClient; RsResourceRef *pContextRef; RsResourceRef *pMemoryRef; Memory *pMemoryInfo; // TODO: rename this field. pMemoryInfo is the legacy name. @@ -206,8 +207,10 @@ pKernelMemorySystem = GPU_GET_KERNEL_MEMORY_SYSTEM(pGpu); } - NV_ASSERT_OK_OR_RETURN(serverGetClientUnderLock(&g_resServ, pMapParams->hClient, &pRsClient)); - NV_ASSERT_OK_OR_RETURN(clientGetResourceRef(pRsClient, pMapParams->hMemory, &pMemoryRef)); + pClient = serverutilGetClientUnderLock(pMapParams->hClient); + NV_ASSERT_OR_ELSE(pClient != NULL, return NV_ERR_INVALID_CLIENT); + NV_ASSERT_OK_OR_RETURN(clientGetResourceRef(staticCast(pClient, RsClient), + pMapParams->hMemory, &pMemoryRef)); pMemoryInfo = dynamicCast(pMemoryRef->pResource, Memory); NV_ASSERT_OR_RETURN(pMemoryInfo != NULL, NV_ERR_NOT_SUPPORTED); @@ -228,12 +231,32 @@ // // CPU to directly access protected memory is allowed on MODS // + // The check below is for VPR and should be skipped for Hopper CC + if ((pGpu != NULL) && !gpuIsCCFeatureEnabled(pGpu)) + { if ((pMemoryInfo->Flags & NVOS32_ALLOC_FLAGS_PROTECTED) && (pMapParams->protect != NV_PROTECT_WRITEABLE) && ! RMCFG_FEATURE_PLATFORM_MODS) { return NV_ERR_NOT_SUPPORTED; } + } + + if ((pGpu != NULL) && (pMemoryInfo->Flags & NVOS32_ALLOC_FLAGS_PROTECTED)) + { + ConfidentialCompute *pCC = GPU_GET_CONF_COMPUTE(pGpu); + // + // If neither BAR1 nor PCIE as a whole is trusted, fail the mapping + // for allocations in CPR region. Mapping should still succeed for + // allocations in non-CPR region + // + if ((pCC != NULL) && !pCC->ccStaticInfo.bIsBar1Trusted && + !pCC->ccStaticInfo.bIsPcieTrusted) + { + NV_ASSERT(0); + return NV_ERR_NOT_SUPPORTED; + } + } if (!pMapParams->bKernel && FLD_TEST_DRF(OS32, _ATTR2, _PROTECTION_USER, _READ_ONLY, pMemoryInfo->Attr2) && @@ -278,6 +301,7 @@ } bIsSysmem = (effectiveAddrSpace == ADDR_SYSMEM); + bIsSysmem = bIsSysmem || (effectiveAddrSpace == ADDR_EGM); if (dynamicCast(pMemoryInfo, FlaMemory) != NULL) { @@ -331,7 +355,6 @@ } else { - NV_ASSERT(DRF_VAL(OS33, _FLAGS, _BUS, pMapParams->flags) == NVOS33_FLAGS_BUS_NVLINK_COHERENT); // // Allocating mapping for user mode client @@ -437,6 +460,8 @@ NV_ASSERT(pGpu->busInfo.gpuPhysFbAddr); { + Device *pDevice = NULL; + // Below, we only map one GPU's address for CPU access, so we can use UNICAST here NvU32 busMapFbFlags = BUS_MAP_FB_FLAGS_MAP_UNICAST; if(DRF_VAL(OS33, _FLAGS, _MAPPING, pMapParams->flags) == NVOS33_FLAGS_MAPPING_DIRECT) @@ -458,15 +483,18 @@ // WAR for Bug 3564398, need to allocate doorbell for windows differently if (RMCFG_FEATURE_PLATFORM_WINDOWS_LDDM && - memdescGetFlag(pMemDesc, MEMDESC_FLAGS_MAP_SYSCOH_OVER_BAR1)) + memdescGetFlag(pMemDesc, MEMDESC_FLAGS_MAP_SYSCOH_OVER_BAR1)) { busMapFbFlags |= BUS_MAP_FB_FLAGS_MAP_DOWNWARDS; } + (void) deviceGetByHandle(staticCast(pClient, RsClient), + pMapParams->hDevice, &pDevice); + rmStatus = kbusMapFbAperture_HAL(pGpu, pKernelBus, pMemDesc, pMapParams->offset, &gpuVirtAddr, &gpuMapLength, - busMapFbFlags, pMapParams->hClient); + busMapFbFlags, pDevice); } if (rmStatus != NV_OK) @@ -584,13 +612,12 @@ { RS_PRIV_LEVEL privLevel; - pRmClient = dynamicCast(pRsClient, RmClient); - if (pRmClient == NULL) - return NV_ERR_OPERATING_SYSTEM; - - privLevel = rmclientGetCachedPrivilege(pRmClient); - if (!rmclientIsAdmin(pRmClient, privLevel) && !memdescGetFlag(pMemDesc, MEMDESC_FLAGS_SKIP_REGMEM_PRIV_CHECK)) + privLevel = rmclientGetCachedPrivilege(pClient); + if (!rmclientIsAdmin(pClient, privLevel) && + !memdescGetFlag(pMemDesc, MEMDESC_FLAGS_SKIP_REGMEM_PRIV_CHECK)) + { return NV_ERR_PROTECTION_FAULT; + } if (DRF_VAL(OS33, _FLAGS, _MEM_SPACE, pMapParams->flags) == NVOS33_FLAGS_MEM_SPACE_USER) { @@ -816,8 +843,7 @@ ) { NV_STATUS rmStatus; - RsClient *pRsClient; - RmClient *pRmClient; + RmClient *pClient; RsResourceRef *pMemoryRef; NvHandle hClient = pMapParams->hClient; NvHandle hParent = hClient; @@ -831,16 +857,15 @@ return NV_ERR_INVALID_FLAGS; // Populate Resource Server information - NV_ASSERT_OK_OR_RETURN(serverGetClientUnderLock(&g_resServ, hClient, &pRsClient)); + pClient = serverutilGetClientUnderLock(hClient); + NV_ASSERT_OR_ELSE(pClient != NULL, return NV_ERR_INVALID_CLIENT); // Validate hClient - pRmClient = dynamicCast(pRsClient, RmClient); - if (pRmClient == NULL) - return NV_ERR_OPERATING_SYSTEM; - privLevel = rmclientGetCachedPrivilege(pRmClient); + privLevel = rmclientGetCachedPrivilege(pClient); // RS-TODO: Assert if this fails after all objects are converted - NV_ASSERT_OK_OR_RETURN(clientGetResourceRef(pRsClient, pMapParams->hMemory, &pMemoryRef)); + NV_ASSERT_OK_OR_RETURN(clientGetResourceRef(staticCast(pClient, RsClient), + pMapParams->hMemory, &pMemoryRef)); if (pMemoryRef->pParentRef != NULL) hParent = pMemoryRef->pParentRef->hResource; @@ -860,7 +885,9 @@ NV_ASSERT_OR_RETURN(hParent != hClient, NV_ERR_INVALID_OBJECT_PARENT); RsResourceRef *pContextRef; - rmStatus = clientGetResourceRef(pRsClient, pMapParams->hDevice, &pContextRef); + rmStatus = clientGetResourceRef(staticCast(pClient, RsClient), + pMapParams->hDevice, &pContextRef); + if (rmStatus != NV_OK) return rmStatus; @@ -918,8 +945,7 @@ { OBJGPU *pGpu = NULL; NV_STATUS rmStatus; - RsClient *pRsClient; - RmClient *pRmClient; + RmClient *pClient; RsResourceRef *pMemoryRef; NvHandle hClient = pUnmapParams->hClient; NvHandle hParent = hClient; @@ -932,16 +958,15 @@ void *pProcessHandle = NULL; // Populate Resource Server information - NV_ASSERT_OK_OR_RETURN(serverGetClientUnderLock(&g_resServ, hClient, &pRsClient)); + pClient = serverutilGetClientUnderLock(hClient); + NV_ASSERT_OR_ELSE(pClient != NULL, return NV_ERR_INVALID_CLIENT); // check if we have a user or kernel RM client - pRmClient = dynamicCast(pRsClient, RmClient); - if (pRmClient == NULL) - return NV_ERR_OPERATING_SYSTEM; - privLevel = rmclientGetCachedPrivilege(pRmClient); + privLevel = rmclientGetCachedPrivilege(pClient); // RS-TODO: Assert if this fails after all objects are converted - NV_ASSERT_OK_OR_RETURN(clientGetResourceRef(pRsClient, hMemory, &pMemoryRef)); + NV_ASSERT_OK_OR_RETURN(clientGetResourceRef(staticCast(pClient, RsClient), + hMemory, &pMemoryRef)); if (pMemoryRef->pParentRef != NULL) hParent = pMemoryRef->pParentRef->hResource; @@ -956,7 +981,9 @@ NV_ASSERT_OR_RETURN(hParent != hClient, NV_ERR_INVALID_OBJECT_PARENT); RsResourceRef *pContextRef; - rmStatus = clientGetResourceRef(pRsClient, pUnmapParams->hDevice, &pContextRef); + rmStatus = clientGetResourceRef(staticCast(pClient, RsClient), + pUnmapParams->hDevice, &pContextRef); + if (rmStatus != NV_OK) return rmStatus; @@ -1185,8 +1212,8 @@ API_SECURITY_INFO *pSecInfo ) { - return rmapiMapToCpuWithSecInfoV2(pRmApi, hClient, - hDevice, hMemory, offset, length, ppCpuVirtAddr, + return rmapiMapToCpuWithSecInfoV2(pRmApi, hClient, + hDevice, hMemory, offset, length, ppCpuVirtAddr, &flags, pSecInfo); } diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/kernel/rmapi/mapping_list.c nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/kernel/rmapi/mapping_list.c --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/kernel/rmapi/mapping_list.c 2023-10-25 20:21:31.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/kernel/rmapi/mapping_list.c 2024-03-05 22:14:04.000000000 +0000 @@ -104,38 +104,35 @@ // allocates/initializes a new CLI_DMA_MAPPING_INFO. // // Ideally, we would know the dmaOffset by now but we typically don't. Thus the caller needs -// to call intermapRegisterDmaMapping() to record the dma mapping at the proper hDevice/dmaOffset location +// to call intermapRegisterDmaMapping() to record the dma mapping at the proper dmaOffset location // NV_STATUS intermapCreateDmaMapping ( RsClient *pClient, - RsResourceRef *pMemoryRef, - NvHandle hDevice, - NvHandle hMemCtx, + VirtualMemory *pVirtualMemory, PCLI_DMA_MAPPING_INFO *ppDmaMapping, NvU32 flags ) { - VirtualMemory *pVirtualMemory; Memory *pMemory = NULL; PCLI_DMA_MAPPING_INFO pDmaMapping; OBJVASPACE *pVAS = NULL; // Mapping is always virtual memory object - if (memGetByHandleAndDevice(pClient, hMemCtx, hDevice, &pMemory) != NV_OK) + if (pVirtualMemory == NULL) { - return NV_ERR_INVALID_OBJECT_HANDLE; + return NV_ERR_INVALID_ARGUMENT; } - pVirtualMemory = dynamicCast(pMemory, VirtualMemory); + pMemory = dynamicCast(pVirtualMemory, Memory); - if ((pMemory->pMemDesc == NULL) || (pVirtualMemory == NULL)) + if (pMemory->pMemDesc == NULL) { return NV_ERR_INVALID_ARGUMENT; } - if (vaspaceGetByHandleOrDeviceDefault(pClient, hDevice, pVirtualMemory->hVASpace, &pVAS) != NV_OK) + if (vaspaceGetByHandleOrDeviceDefault(pClient, RES_GET_HANDLE(pMemory->pDevice), pVirtualMemory->hVASpace, &pVAS) != NV_OK) { return NV_ERR_INVALID_ARGUMENT; } @@ -149,7 +146,6 @@ // initialize the dma mapping info (not registered yet) portMemSet(pDmaMapping, 0, sizeof(CLI_DMA_MAPPING_INFO)); - pDmaMapping->hDevice = hDevice; pDmaMapping->DmaOffset = 0; pDmaMapping->bP2P = NV_FALSE; pDmaMapping->Flags = flags; // NV0S46_* @@ -160,191 +156,130 @@ } // -// registers/stores a pDmaMapping created by intermapCreateDmaMapping() at the hDevice/dmaOffset. +// registers/stores a pDmaMapping created by intermapCreateDmaMapping() at the dmaOffset. // -// important: we assume the hDevice/dmaOffset does NOT change (needs to be re-registerd) +// important: we assume the dmaOffset does NOT change (needs to be re-registerd) // NV_STATUS intermapRegisterDmaMapping ( RsClient *pClient, - NvHandle hDevice, - NvHandle hMemCtx, + VirtualMemory *pVirtualMemory, PCLI_DMA_MAPPING_INFO pDmaMapping, NvU64 dmaOffset, NvU32 gpuMask ) { NV_STATUS rmStatus = NV_OK; - VirtualMemory *pVirtualMemory = NULL; PNODE pNode; - PNODE *ppDmaMappingList; - PCLI_DMA_MAPPING_INFO pDmaMappingFirst, pDmaMappingNext; - - // eventually remove Next/Prev once all other linear list based on PCLI_DMA_MAPPING_INFO are gone... - NV_ASSERT(!pDmaMapping->Next && !pDmaMapping->Prev); - - NV_CHECK_OK_OR_RETURN(LEVEL_SILENT, - virtmemGetByHandleAndDevice(pClient, hMemCtx, hDevice, &pVirtualMemory)); - - // the top level consists of lists sorted by hDevice - already created the hDevice specific list? - if (btreeSearch(hDevice, &pNode, pVirtualMemory->pDmaMappingList) != NV_OK) - { - // create a NODE for all pDmaMappings of this hDevice - pNode = portMemAllocNonPaged(sizeof(NODE)); - if (NULL == pNode) - { - return NV_ERR_INSUFFICIENT_RESOURCES; - } - portMemSet(pNode, 0, sizeof(NODE)); - pNode->keyStart = hDevice; - pNode->keyEnd = hDevice; - pNode->Data = NULL; - - // register the hDevice list itself - rmStatus = btreeInsert(pNode, &pVirtualMemory->pDmaMappingList); - if (rmStatus != NV_OK) - { - portMemFree(pNode); - return rmStatus; - } - } - - NV_ASSERT(pNode); - ppDmaMappingList = (PNODE*)&pNode->Data; + NvU64 alignment = 0; pDmaMapping->gpuMask = gpuMask; - // the second level consists of CLI_DMA_MAPPING_INFO sorted by dmaOffset - - if (DRF_VAL(OS46, _FLAGS, _DMA_UNICAST_REUSE_ALLOC, pDmaMapping->Flags) == - NVOS46_FLAGS_DMA_UNICAST_REUSE_ALLOC_FALSE) + if (FLD_TEST_DRF(OS46, _FLAGS, _DMA_UNICAST_REUSE_ALLOC, _TRUE, pDmaMapping->Flags)) { - NvU64 alignment = 0; + CLI_DMA_MAPPING_INFO *pDmaMappingFirst; + CLI_DMA_MAPPING_INFO *pDmaMappingCurrent; - if (pDmaMapping->pMemDesc->pGpu != NULL) - { - OBJGPU *pGpu = pDmaMapping->pMemDesc->pGpu; - // - // For verify purposes we should allow small page override for mapping. - // This will be used for testing VASpace interop. - // However, this info is not captured in the DMA mapping info for guest. - // So explicitly check for this case in guest. - // - if (IS_VIRTUAL_WITH_SRIOV(pGpu) - && RMCFG_FEATURE_PLATFORM_MODS - && FLD_TEST_DRF(OS46, _FLAGS, _PAGE_SIZE, _4KB, pDmaMapping->Flags) - && kgmmuIsVaspaceInteropSupported(GPU_GET_KERNEL_GMMU(pGpu)) - ) - { - alignment = RM_PAGE_SIZE; - } - else - { - alignment = (NvU64)memdescGetPageSize(memdescGetMemDescFromGpu(pDmaMapping->pMemDesc, pGpu), - pDmaMapping->addressTranslation); - } - } + // The node for this DMA offset should be already created + NV_CHECK_OK_OR_RETURN(LEVEL_ERROR, btreeSearch(dmaOffset, &pNode, pVirtualMemory->pDmaMappingList)); + pDmaMappingFirst = (CLI_DMA_MAPPING_INFO *)pNode->Data; - // - // In some cases page size may not be set (e.g. NV50, AMODEL, VGPU). - // Ideally we should fix all paths for consistency, but for now - // allowing fallback to unaligned tracking (no worse than before). - // - // TODO: Revisit this with memdesc page size cleanup. - // - if (alignment == 0) + NV_CHECK_OR_RETURN(LEVEL_ERROR, pDmaMappingFirst->DmaOffset == pDmaMapping->DmaOffset && + pDmaMappingFirst->pMemDesc->Size == pDmaMapping->pMemDesc->Size, + NV_ERR_INVALID_ARGUMENT); + + // Check gpuMasks for consistency + NV_CHECK_OR_RETURN(LEVEL_ERROR, (pDmaMappingFirst->gpuMask & (pDmaMappingFirst->gpuMask - 1)) == 0, NV_ERR_INVALID_ARGUMENT); + NV_CHECK_OR_RETURN(LEVEL_ERROR, (pDmaMapping->gpuMask & (pDmaMapping->gpuMask - 1)) == 0, NV_ERR_INVALID_ARGUMENT); + pDmaMappingCurrent = pDmaMappingFirst; + while (pDmaMappingCurrent != NULL) { - alignment = 1; + NV_CHECK_OR_RETURN(LEVEL_ERROR, (pDmaMapping->gpuMask & pDmaMappingCurrent->gpuMask) == 0, NV_ERR_INVALID_ARGUMENT); + pDmaMappingCurrent = pDmaMappingCurrent->pNext; } - // create the node for this dmaOffset - pNode = portMemAllocNonPaged(sizeof(NODE)); - if (NULL == pNode) - { - return NV_ERR_INSUFFICIENT_RESOURCES; - } - portMemSet(pNode, 0, sizeof(NODE)); + // Insert the gpuMask element to the list + pDmaMapping->pNext = pDmaMappingFirst; + pNode->Data = pDmaMapping; + return NV_OK; + } + + if (pDmaMapping->pMemDesc->pGpu != NULL) + { + OBJGPU *pGpu = pDmaMapping->pMemDesc->pGpu; // - // For normal GPU devices, track the mapping over its entire - // virtual range so overlapping mappings are caught. - // - // keyStart and keyEnd must be aligned to the physical page size to - // ensure no page can be mapped twice. - // (e.g. small pages mapped into the leftovers of a big page). - // - // NOTE: Unfortunately this check occurs after the internal mapping - // has already taken place, so the state is already corrupted. - // Failure here means "Oops, your're screwed." - // - // For Fermi+ we have added checks in the internal mapping code - // that will fail safely. + // For verify purposes we should allow small page override for mapping. + // This will be used for testing VASpace interop. + // However, this info is not captured in the DMA mapping info for guest. + // So explicitly check for this case in guest. // - pNode->keyStart = RM_ALIGN_DOWN(dmaOffset, alignment); - pNode->keyEnd = RM_ALIGN_UP(dmaOffset + pDmaMapping->pMemDesc->Size, - alignment) - 1; - pNode->Data = pDmaMapping; - - // register the 'dmaOffset' list itself - rmStatus = btreeInsert(pNode, ppDmaMappingList); - if (rmStatus != NV_OK) + if (IS_VIRTUAL_WITH_SRIOV(pGpu) + && RMCFG_FEATURE_PLATFORM_MODS + && FLD_TEST_DRF(OS46, _FLAGS, _PAGE_SIZE, _4KB, pDmaMapping->Flags) + && kgmmuIsVaspaceInteropSupported(GPU_GET_KERNEL_GMMU(pGpu)) + ) { - NV_PRINTF(LEVEL_ERROR, - "Failed to insert new mapping node for range 0x%llX-0x%llX!\n", - pNode->keyStart, pNode->keyEnd); - DBG_BREAKPOINT(); - portMemFree(pNode); - return rmStatus; + alignment = RM_PAGE_SIZE; } - } - else - { - // The node for this DMA offset should be already created - rmStatus = btreeSearch(dmaOffset, &pNode, *ppDmaMappingList); - if (rmStatus != NV_OK) + else { - NV_PRINTF(LEVEL_ERROR, - "Failed to find existing mapping node for offset 0x%llX!\n", - dmaOffset); - DBG_BREAKPOINT(); - return rmStatus; + alignment = memdescGetPageSize(memdescGetMemDescFromGpu(pDmaMapping->pMemDesc, pGpu), + pDmaMapping->addressTranslation); } + } - NV_ASSERT(pNode); - pDmaMappingFirst = (PCLI_DMA_MAPPING_INFO)pNode->Data; + // + // In some cases page size may not be set (e.g. NV50, AMODEL, VGPU). + // Ideally we should fix all paths for consistency, but for now + // allowing fallback to unaligned tracking (no worse than before). + // + // TODO: Revisit this with memdesc page size cleanup. + // + if (alignment == 0) + { + alignment = 1; + } - // check that we do not exceed the original mapping length - if (pDmaMapping->pMemDesc->Size > pDmaMappingFirst->pMemDesc->Size) - { - NV_PRINTF(LEVEL_ERROR, - "Mapping length 0x%llX exceeds existing mapping length of 0x%llX!\n", - pDmaMapping->pMemDesc->Size, - pDmaMappingFirst->pMemDesc->Size); - DBG_BREAKPOINT(); - return NV_ERR_INVALID_LIMIT; - } + // create the node for this dmaOffset + pNode = portMemAllocNonPaged(sizeof(NODE)); + if (NULL == pNode) + { + return NV_ERR_INSUFFICIENT_RESOURCES; + } + portMemSet(pNode, 0, sizeof(NODE)); - // Insert the gpuMask element to the list - pDmaMapping->Next = pDmaMappingFirst; - pDmaMappingFirst->Prev = pDmaMapping; - pNode->Data = pDmaMapping; + // + // For normal GPU devices, track the mapping over its entire + // virtual range so overlapping mappings are caught. + // + // keyStart and keyEnd must be aligned to the physical page size to + // ensure no page can be mapped twice. + // (e.g. small pages mapped into the leftovers of a big page). + // + // NOTE: Unfortunately this check occurs after the internal mapping + // has already taken place, so the state is already corrupted. + // Failure here means "Oops, your're screwed." + // + // For Fermi+ we have added checks in the internal mapping code + // that will fail safely. + // + pNode->keyStart = RM_ALIGN_DOWN(dmaOffset, alignment); + pNode->keyEnd = RM_ALIGN_UP(dmaOffset + pDmaMapping->pMemDesc->Size, + alignment) - 1; + pNode->Data = pDmaMapping; - // Change the other mappings to remove this gpuMask from them - pDmaMapping = pDmaMapping->Next; - while (pDmaMapping) - { - pDmaMappingNext = pDmaMapping->Next; - if (pDmaMapping->gpuMask & gpuMask) - { - pDmaMapping->gpuMask &= ~gpuMask; - if (pDmaMapping->gpuMask == 0) - { - // free the pDmaMapping itself - intermapFreeDmaMapping(pDmaMapping); - } - } - pDmaMapping = pDmaMappingNext; - } + // register the 'dmaOffset' list itself + rmStatus = btreeInsert(pNode, &pVirtualMemory->pDmaMappingList); + if (rmStatus != NV_OK) + { + NV_PRINTF(LEVEL_ERROR, + "Failed to insert new mapping node for range 0x%llX-0x%llX!\n", + pNode->keyStart, pNode->keyEnd); + DBG_BREAKPOINT(); + portMemFree(pNode); + return rmStatus; } return NV_OK; @@ -354,115 +289,52 @@ intermapDelDmaMapping ( RsClient *pClient, - NvHandle hDevice, - NvHandle hMemCtx, + VirtualMemory *pVirtualMemory, NvU64 dmaOffset, - NvU32 gpuMask, - NvBool *pbUnmapped + NvU32 gpuMask ) { - NV_STATUS rmStatus = NV_OK; - VirtualMemory *pVirtualMemory = NULL; - PCLI_DMA_MAPPING_INFO pDmaMapping, pDmaMappingNext, pDmaMappingPrev; - PNODE pDeviceNode; - PNODE pOffsetNode; PNODE pNode; - - if (pbUnmapped != NULL) - *pbUnmapped = NV_FALSE; - - // Mapping is always virtual memory object - NV_CHECK_OK_OR_RETURN(LEVEL_SILENT, - virtmemGetByHandleAndDevice(pClient, hMemCtx, hDevice, &pVirtualMemory)); - - // first find the list specific to the hDevice - rmStatus = btreeSearch(hDevice, &pDeviceNode, pVirtualMemory->pDmaMappingList); - if (rmStatus != NV_OK) - { - return rmStatus; - } + CLI_DMA_MAPPING_INFO *pDmaMapping; + CLI_DMA_MAPPING_INFO *pDmaMappingPrev = NULL; // then get the node belonging to the search offset - rmStatus = btreeSearch(dmaOffset, &pOffsetNode, (PNODE)pDeviceNode->Data); - if (rmStatus != NV_OK) - { - return rmStatus; - } - - pDmaMapping = pOffsetNode->Data; + NV_ASSERT_OK_OR_RETURN(btreeSearch(dmaOffset, &pNode, pVirtualMemory->pDmaMappingList)); - // Remove the first dma mappings intersecting with this GPU mask + pDmaMapping = (CLI_DMA_MAPPING_INFO *)pNode->Data; while (pDmaMapping != NULL) { - pDmaMappingNext = pDmaMapping->Next; - if (pDmaMapping->gpuMask & gpuMask) { - // Remove the element - pDmaMappingPrev = pDmaMapping->Prev; + CLI_DMA_MAPPING_INFO *pDmaMappingNext = pDmaMapping->pNext; + NV_ASSERT_OR_RETURN(pDmaMapping->gpuMask == gpuMask, NV_ERR_INVALID_ARGUMENT); + + // Remove the element if (pDmaMappingPrev != NULL) { - pDmaMappingPrev->Next = pDmaMappingNext; + pDmaMappingPrev->pNext = pDmaMappingNext; } - else + else if (pDmaMappingNext != NULL) { - pOffsetNode->Data = pDmaMappingNext; + pNode->Data = pDmaMappingNext; } - - if (pDmaMappingNext != NULL) + else { - pDmaMappingNext->Prev = pDmaMappingPrev; + NV_ASSERT_OK_OR_RETURN(btreeUnlink(pNode, &pVirtualMemory->pDmaMappingList)); + portMemFree(pNode); } - // free the pDmaMapping itself intermapFreeDmaMapping(pDmaMapping); - - if (pbUnmapped != NULL) - *pbUnmapped = NV_TRUE; - - break; + return NV_OK; } - - pDmaMapping = pDmaMappingNext; + pDmaMappingPrev = pDmaMapping; + pDmaMapping = pDmaMapping->pNext; } - // Is the list empty ? - if (pOffsetNode->Data == NULL) - { - // unlink the node - rmStatus = btreeSearch(dmaOffset, &pNode, (PNODE)pDeviceNode->Data); - if (rmStatus != NV_OK) - { - return rmStatus; - } - - rmStatus = btreeUnlink(pNode, (PNODE*)&pDeviceNode->Data); - if (rmStatus == NV_OK) - { - // free the node memory itself - portMemFree(pOffsetNode); - - // is our dmaOffset list empty now? - if (pDeviceNode->Data == NULL) - { - // remove the whole hDevice list - rmStatus = btreeSearch(hDevice, &pNode, pVirtualMemory->pDmaMappingList); - if (rmStatus != NV_OK) - { - return rmStatus; - } - - rmStatus = btreeUnlink(pNode, &pVirtualMemory->pDmaMappingList); - if (rmStatus == NV_OK) - { - portMemFree(pDeviceNode); - } - } - } - } - - return rmStatus; + // mapping with the right gpuMask was not found + NV_ASSERT(0); + return NV_ERR_OBJECT_NOT_FOUND; } void @@ -477,62 +349,46 @@ portMemFree(pDmaMapping); } -static NvBool -_getDmaMappingInfoFromMemory +/*! + * @brief Lookup mapping info in a virtual memory allocation + */ +CLI_DMA_MAPPING_INFO * +intermapGetDmaMapping ( VirtualMemory *pVirtualMemory, - NvHandle hDevice, NvU64 dmaOffset, - NvU32 gpuMask, - PCLI_DMA_MAPPING_INFO *ppDmaMappingInfo + NvU32 gpuMask ) { - PNODE pDmaMappingList; PNODE pNode; - PCLI_DMA_MAPPING_INFO pDmaMappingInfo; + CLI_DMA_MAPPING_INFO *pDmaMapping; + + // get the node belonging to the search offset + if (btreeSearch(dmaOffset, &pNode, pVirtualMemory->pDmaMappingList) != NV_OK) + return NULL; - // first find the list specific to the hDevice - pDmaMappingList = pVirtualMemory->pDmaMappingList; - if (btreeSearch(hDevice, &pNode, pDmaMappingList) == NV_OK) + pDmaMapping = pNode->Data; + + while (pDmaMapping != NULL) { - pDmaMappingList = (PNODE)pNode->Data; - NV_ASSERT(pDmaMappingList); + if (pDmaMapping->gpuMask & gpuMask) + return pDmaMapping; - // then get the node belonging to the search offset - if (btreeSearch(dmaOffset, &pNode, pDmaMappingList) == NV_OK) - { - // Then look for the GPU mask - pDmaMappingInfo = pNode->Data; - while (pDmaMappingInfo) - { - if (pDmaMappingInfo->gpuMask & gpuMask) - { - // Returns the first mapping that intersects with this gpu mask. - break; - } - pDmaMappingInfo = pDmaMappingInfo->Next; - } - if (pDmaMappingInfo != NULL) - { - *ppDmaMappingInfo = pDmaMappingInfo; - return NV_TRUE; - } - } + pDmaMapping = pDmaMapping->pNext; } - return NV_FALSE; + + return pDmaMapping; } /*! - * @brief Lookup mapping info in memory context or VA space + * @brief Lookup mapping info in VA space * - * This is useful when processing SW methods. We can find the hVASpace - * from the channel context uniquely. Previous lookup within the whole - * client could mistakenly find an alias on another device. + * This is useful for semaphores/notifiers when processing SW methods. */ NvBool CliGetDmaMappingInfo ( - NvHandle hClient, + RsClient *pClient, NvHandle hDevice, NvHandle hMemCtx, NvU64 dmaOffset, @@ -541,15 +397,9 @@ ) { VirtualMemory *pVirtualMemory; - RsClient *pClient; Device *pDevice; NODE *pNode; NV_STATUS status; - NvBool bFound; - - status = serverGetClientUnderLock(&g_resServ, hClient, &pClient); - if (status != NV_OK) - return NV_FALSE; // Try a non-zero handle as a NVxx_MEMORY_VIRTUAL object if (hMemCtx != NV01_NULL_OBJECT) @@ -564,7 +414,9 @@ pVirtualMemory = dynamicCast(pMemCtxRef->pResource, VirtualMemory); if (pVirtualMemory != NULL) { - return _getDmaMappingInfoFromMemory(pVirtualMemory, hDevice, dmaOffset, gpuMask, ppDmaMappingInfo); + + *ppDmaMappingInfo = intermapGetDmaMapping(pVirtualMemory, dmaOffset, gpuMask); + return *ppDmaMappingInfo != NULL; } } @@ -580,13 +432,12 @@ btreeEnumNext(&pNode, pDevice->DevMemoryTable); if ((pVirtualMemory != NULL) && - virtmemMatchesVASpace(pVirtualMemory, hClient, hMemCtx)) + virtmemMatchesVASpace(pVirtualMemory, pClient->hClient, hMemCtx)) { - bFound = _getDmaMappingInfoFromMemory(pVirtualMemory, hDevice, - dmaOffset, gpuMask, - ppDmaMappingInfo); - if (bFound) - return bFound; + *ppDmaMappingInfo = intermapGetDmaMapping(pVirtualMemory, dmaOffset, gpuMask); + + if (*ppDmaMappingInfo != NULL) + return NV_TRUE; } } @@ -604,22 +455,19 @@ // don't iterate if we didn't get a empty list *ppFirstDmaMapping = NULL; portMemSet(pIt, 0, sizeof(*pIt)); - if (pDmaMappingList != NULL) - { - // find the first hDevice list - pIt->pDmaMappingList = pDmaMappingList; - btreeEnumStart(0, &pIt->pCurrentList, pIt->pDmaMappingList); - if (pIt->pCurrentList != NULL) - { - // find the first pDmaMapping of the hDevice list (hDevice lists can't be empty *ever*) - NV_ASSERT(pIt->pCurrentList->Data); - btreeEnumStart(0, &pIt->pNextDmaMapping, pIt->pCurrentList->Data); - NV_ASSERT(pIt->pNextDmaMapping); - NV_ASSERT(pIt->pNextDmaMapping->Data); - CliGetDmaMappingNext(ppFirstDmaMapping, pIt); - } - } + if (pDmaMappingList == NULL) + return; + + // find the first pDmaMapping + pIt->pDmaMappingList = pDmaMappingList; + btreeEnumStart(0, &pIt->pNextDmaMapping, pIt->pDmaMappingList); + + if (pIt->pNextDmaMapping == NULL) + return; + + NV_ASSERT(pIt->pNextDmaMapping->Data); + CliGetDmaMappingNext(ppFirstDmaMapping, pIt); } void @@ -631,37 +479,23 @@ { PCLI_DMA_MAPPING_INFO pDmaMapping = NULL; - // are we done with all hDevice lists? - if ((pIt->pDmaMappingList != NULL) && - (pIt->pCurrentList != NULL) && - (pIt->pNextDmaMapping != NULL)) + if (pIt->pNextDmaMapping != NULL) { // return the current node. NV_ASSERT(pIt->pNextDmaMapping->Data); pDmaMapping = (PCLI_DMA_MAPPING_INFO)pIt->pNextDmaMapping->Data; - // iterate to the next DmaOffset (so the caller is free to delete the node) - btreeEnumNext(&pIt->pNextDmaMapping, pIt->pCurrentList); + // not supporting legacy _DMA_UNICAST_REUSE_ALLOC case + NV_ASSERT(pDmaMapping->pNext == NULL); - // reached the end of the hDevice list? move to next hDevice - if (pIt->pNextDmaMapping == NULL) - { - btreeEnumNext(&pIt->pCurrentList, pIt->pDmaMappingList); - if (pIt->pCurrentList != NULL) - { - // restart iteration process for the new list - NV_ASSERT(pIt->pCurrentList->Data); - btreeEnumStart(0, &pIt->pNextDmaMapping, pIt->pCurrentList->Data); - NV_ASSERT(pIt->pNextDmaMapping); - } - } + // iterate to the next DmaOffset (so the caller is free to delete the node) + btreeEnumNext(&pIt->pNextDmaMapping, pIt->pDmaMappingList); } // stop iterating once we hit the end of list [or something bad happened] if (pDmaMapping == NULL) { pIt->pDmaMappingList = NULL; - pIt->pCurrentList = NULL; pIt->pNextDmaMapping = NULL; } *ppDmaMapping = pDmaMapping; diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/kernel/rmapi/nv_gpu_ops.c nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/kernel/rmapi/nv_gpu_ops.c --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/kernel/rmapi/nv_gpu_ops.c 2023-10-25 20:21:31.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/kernel/rmapi/nv_gpu_ops.c 2024-03-05 22:14:04.000000000 +0000 @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 2013-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2013-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -21,9 +21,15 @@ * DEALINGS IN THE SOFTWARE. */ +// FIXME XXX +#define NVOC_GPU_INSTANCE_SUBSCRIPTION_H_PRIVATE_ACCESS_ALLOWED + #include "core/prelude.h" +// FIXME XXX +#define NVOC_KERNEL_GRAPHICS_MANAGER_H_PRIVATE_ACCESS_ALLOWED + #include #include #include // NV01_MEMORY_SYSTEM @@ -33,6 +39,7 @@ #include // NV50_MEMORY_VIRTUAL #include #include +#include // KEPLER_CHANNEL_GROUP_A #include #include #include @@ -65,9 +72,12 @@ #include #include #include +#include // NV_CONFIDENTIAL_COMPUTE #include // HOPPER_USERMODE_A #include // HOPPER_DMA_COPY_A #include // HOPPER_COMPUTE_A +#include // HOPPER_SEC2_WORK_LAUNCH_A +#include #include #include @@ -84,6 +94,7 @@ #include #include #include +#include #include #include @@ -98,7 +109,6 @@ #include #include #include -#include #include #include #include @@ -123,8 +133,11 @@ #include #include +#include #include +#include + #define NV_GPU_OPS_NUM_GPFIFO_ENTRIES_DEFAULT 1024 #define NV_GPU_SMALL_PAGESIZE (4 * 1024) @@ -145,7 +158,7 @@ typedef struct { - NvU32 pageSize; // default is 4k or 64k else use pagesize = 2M. + NvU64 pageSize; // default is 4k or 64k else use pagesize = 2M. NvU64 alignment; } gpuVaAllocInfo; @@ -221,6 +234,9 @@ NvU32 deviceInstance; NvU32 subdeviceInstance; NvU32 gpuId; + + // TODO: Bug 3906861: The info struct contains many of these fields. Find + // and remove the redundant fields from this top level. NvU32 hostClass; NvU32 ceClass; NvU32 sec2Class; @@ -232,9 +248,7 @@ struct gpuSession *session; NvU8 gpuUUID[NV_GPU_UUID_LEN]; gpuFbInfo fbInfo; - UVM_LINK_TYPE sysmemLink; - NvU32 sysmemLinkRateMBps; - NvBool connectedToSwitch; + gpuInfo info; MemdescMap kern2PhysDescrMap; @@ -263,25 +277,34 @@ } dummyGpuAlloc; }; +struct gpuTsg +{ + NvHandle tsgHandle; + struct gpuAddressSpace *vaSpace; + UVM_GPU_CHANNEL_ENGINE_TYPE engineType; + + // Index of the engine the TSG is bound to. + // Ignored if engineType is anything other than + // UVM_GPU_CHANNEL_ENGINE_TYPE_CE. + NvU32 engineIndex; + + // True when the GPU does not support TSG for the engineType. + NvBool isFakeTsg; +}; + struct gpuChannel { + const struct gpuTsg *tsg; NvHandle channelHandle; + NvHandle engineHandle; NvU32 hwRunlistId; NvU32 hwChannelId; - UVM_GPU_CHANNEL_ENGINE_TYPE engineType; - - // If engineType is CE, engineIndex is a zero-based offset from - // RM_ENGINE_TYPE_COPY0. If engineType is GR, engineIndex is a - // zero-based offset from NV2080_ENGINE_TYPE_GR0. - NvU32 engineIndex; - struct gpuAddressSpace *vaSpace; NvU64 gpFifo; NvNotification *errorNotifier; NvU64 errorNotifierOffset; NvU64 *gpFifoEntries; NvU32 fifoEntries; KeplerAControlGPFifo *controlPage; - struct gpuObject *nextAttachedEngine; NvHandle hFaultCancelSwMethodClass; volatile unsigned *workSubmissionOffset; NvU32 workSubmissionToken; @@ -291,6 +314,8 @@ UVM_BUFFER_LOCATION gpFifoLoc; UVM_BUFFER_LOCATION gpPutLoc; NvBool retainedDummyAlloc; + NvBool bClientRegionGpuMappingNeeded; + NvU64 clientRegionGpuAddr; }; // Add 3 to include local ctx buffer, patch context buffer and PM ctxsw buffer @@ -323,13 +348,6 @@ NvHandle hChannelRetainer; }; -struct gpuObject -{ - NvHandle handle; - NvU32 type; - struct gpuObject *next; -}; - struct allocFlags { NvBool bGetKernelVA; @@ -398,16 +416,14 @@ NvHandle handle, void *ptr, NvU32 flags); -static NV_STATUS allocNvlinkStatusForSubdevice(struct gpuDevice *device, - NV2080_CTRL_CMD_NVLINK_GET_NVLINK_STATUS_PARAMS **nvlinkStatusOut); +static NV_STATUS allocNvlinkStatus(NvHandle hClient, + NvHandle hSubDevice, + NV2080_CTRL_CMD_NVLINK_GET_NVLINK_STATUS_PARAMS **nvlinkStatusOut); static NvU32 getNvlinkConnectionToNpu(const NV2080_CTRL_CMD_NVLINK_GET_NVLINK_STATUS_PARAMS *nvlinkStatus, NvBool *atomicSupported, NvU32 *linkBandwidthMBps); static NvU32 getNvlinkConnectionToSwitch(const NV2080_CTRL_CMD_NVLINK_GET_NVLINK_STATUS_PARAMS *nvlinkStatus, NvU32 *linkBandwidthMBps); -static NV_STATUS getC2CConnectionToCpu(struct gpuDevice *device, - NvBool *connectedToCpu, - NvU32 *linkBandwidthMBps); static NV_STATUS nvGpuOpsGetMemoryByHandle(NvHandle hClient, NvHandle hMemory, Memory **ppMemory); static void _nvGpuOpsReleaseChannel(gpuRetainedChannel *retainedChannel); static NV_STATUS _nvGpuOpsRetainChannelResources(struct gpuDevice *device, @@ -417,6 +433,10 @@ gpuChannelInstanceInfo *channelInstanceInfo); static void _nvGpuOpsReleaseChannelResources(gpuRetainedChannel *retainedChannel); +static NV_STATUS +nvGpuOpsQueryGpuConfidentialComputeCaps(NvHandle hClient, + UvmGpuConfComputeCaps *pGpuConfComputeCaps); + /* * This function will lock the RM API lock according to rmApiLockFlags, and then * examine numLocksNeeded. If this is 0, no GPU locks will be acquired. If it @@ -603,7 +623,7 @@ *hClient = NV01_NULL_OBJECT; status = pRmApi->Alloc(pRmApi, NV01_NULL_OBJECT, NV01_NULL_OBJECT, - hClient, NV01_ROOT, hClient); + hClient, NV01_ROOT, hClient, sizeof(*hClient)); if (status != NV_OK) { return status; @@ -693,7 +713,7 @@ // any CPU BAR1 PCIE writes prior to updating GPPUT. This is only needed // when the bus is non-coherent and when not in ZeroFB (where there can't be // any BAR1 mappings). - return device->sysmemLink < UVM_LINK_TYPE_NVLINK_2 && !device->fbInfo.bZeroFb; + return device->info.sysmemLink < UVM_LINK_TYPE_NVLINK_2 && !device->fbInfo.bZeroFb; } static NV_STATUS nvGpuOpsVaSpaceRetainDummyAlloc(struct gpuAddressSpace *vaSpace) @@ -710,6 +730,12 @@ if (vaSpace->dummyGpuAlloc.refCount > 0) goto done; + // When HCC is enabled the allocation happens in CPR vidmem + // The dummy BAR1 pointer read mechanism won't work when + // BAR1 access to CPR vidmem is sealed off as part of HCC + // production settings. Creating dummy BAR1 mapping can + // also be avoided when doorbell is in BAR1. + flags.bGetKernelVA = NV_FALSE; status = nvGpuOpsGpuMalloc(vaSpace, NV_FALSE, @@ -911,7 +937,8 @@ session->handle, &device->handle, NV01_DEVICE_0, - &nv0080AllocParams); + &nv0080AllocParams, + sizeof(nv0080AllocParams)); if (status != NV_OK) goto cleanup_device_desc; @@ -1114,7 +1141,8 @@ device->subhandle, &rmSubDevice->eccMasterHandle, GF100_SUBDEVICE_MASTER, - &tempPtr); + &tempPtr, + sizeof(tempPtr)); if (status != NV_OK) goto done; @@ -1176,7 +1204,8 @@ device->subhandle, &rmSubDevice->eccCallbackHandle, NV01_EVENT_KERNEL_CALLBACK_EX, - &pParams->allocDbe); + &pParams->allocDbe, + sizeof(pParams->allocDbe)); if (status != NV_OK) goto done; @@ -1434,7 +1463,8 @@ device->handle, &device->subhandle, NV20_SUBDEVICE_0, - &nv2080AllocParams); + &nv2080AllocParams, + sizeof(nv2080AllocParams)); if (status != NV_OK) goto cleanup_subdevice_desc; rmSubDevice->subDeviceHandle = device->subhandle; @@ -1482,6 +1512,13 @@ return device->rmDevice->arch >= GPU_ARCHITECTURE_AMPERE; } +// Assume ...->Ampere->Ada->Hopper->... +static NvBool isDeviceHopperPlus(const struct gpuDevice *device) +{ + NV_ASSERT(device->rmDevice); + return (device->rmDevice->arch >= GPU_ARCHITECTURE_HOPPER) && (device->rmDevice->arch != GPU_ARCHITECTURE_ADA); +} + static UVM_LINK_TYPE rmControlToUvmNvlinkVersion(NvU32 nvlinkVersion) { if (nvlinkVersion == NV2080_CTRL_NVLINK_STATUS_NVLINK_VERSION_INVALID) @@ -1567,9 +1604,9 @@ return nvStatus; } -// Return the PCIE link cap max speed associated with the given GPU in -// megabytes per seconds.. -static NV_STATUS getPCIELinkRateMBps(struct gpuDevice *device, NvU32 *pcieLinkRate) +// Return the PCIE link cap max speed associated with the given subdevice in +// megabytes per second. +static NV_STATUS getPCIELinkRateMBps(NvHandle hClient, NvHandle hSubDevice, NvU32 *pcieLinkRate) { // PCI Express Base Specification: https://www.pcisig.com/specifications/pciexpress const NvU32 PCIE_1_ENCODING_RATIO_TOTAL = 10; @@ -1582,8 +1619,8 @@ const NvU32 PCIE_4_ENCODING_RATIO_EFFECTIVE = 128; const NvU32 PCIE_5_ENCODING_RATIO_TOTAL = 130; const NvU32 PCIE_5_ENCODING_RATIO_EFFECTIVE = 128; - const NvU32 PCIE_6_ENCODING_RATIO_TOTAL = 130; - const NvU32 PCIE_6_ENCODING_RATIO_EFFECTIVE = 128; + const NvU32 PCIE_6_ENCODING_RATIO_TOTAL = 256; + const NvU32 PCIE_6_ENCODING_RATIO_EFFECTIVE = 242; RM_API *pRmApi = rmapiGetInterface(RMAPI_EXTERNAL_KERNEL); NV2080_CTRL_BUS_INFO busInfo = {0}; @@ -1596,8 +1633,8 @@ busInfoParams.busInfoList = NV_PTR_TO_NvP64(&busInfo); NV_STATUS status = pRmApi->Control(pRmApi, - device->session->handle, - device->subhandle, + hClient, + hSubDevice, NV2080_CTRL_CMD_BUS_GET_INFO, &busInfoParams, sizeof(busInfoParams)); @@ -1656,13 +1693,6 @@ NV_STATUS status; struct gpuDevice *device = NULL; NV0000_CTRL_GPU_GET_UUID_INFO_PARAMS gpuIdInfoParams = {{0}}; - NV2080_CTRL_BUS_GET_INFO_V2_PARAMS *busInfoParams; - NV2080_CTRL_CMD_NVLINK_GET_NVLINK_STATUS_PARAMS *nvlinkStatus; - NvU32 nvlinkVersion; - NvU32 sysmemLink; - NvU32 linkBandwidthMBps; - NvU32 sysmemConnType; - NvBool atomicSupported; RM_API *pRmApi = rmapiGetInterface(RMAPI_EXTERNAL_KERNEL); OBJGPU *pGpu; @@ -1687,6 +1717,8 @@ device->subdeviceInstance = gpuIdInfoParams.subdeviceInstance; device->gpuId = gpuIdInfoParams.gpuId; + portMemCopy(&device->info, sizeof(device->info), pGpuInfo, sizeof(*pGpuInfo)); + status = nvGpuOpsRmDeviceCreate(device); if (status != NV_OK) goto cleanup_device_obj; @@ -1737,109 +1769,6 @@ if (status != NV_OK) goto cleanup_ecc; - busInfoParams = portMemAllocNonPaged(sizeof(*busInfoParams)); - if (busInfoParams == NULL) - { - status = NV_ERR_INSUFFICIENT_RESOURCES; - goto cleanup_ecc; - } - portMemSet(busInfoParams, 0, sizeof(*busInfoParams)); - busInfoParams->busInfoListSize = 1; - busInfoParams->busInfoList[0].index = NV2080_CTRL_BUS_INFO_INDEX_SYSMEM_CONNECTION_TYPE; - status = pRmApi->Control(pRmApi, - device->session->handle, - device->subhandle, - NV2080_CTRL_CMD_BUS_GET_INFO_V2, - busInfoParams, - sizeof(*busInfoParams)); - if (status != NV_OK) - { - portMemFree(busInfoParams); - goto cleanup_ecc; - } - - sysmemConnType = busInfoParams->busInfoList[0].data; - portMemFree(busInfoParams); - - sysmemLink = UVM_LINK_TYPE_NONE; - switch (sysmemConnType) - { - case NV2080_CTRL_BUS_INFO_INDEX_SYSMEM_CONNECTION_TYPE_NVLINK: - { - status = allocNvlinkStatusForSubdevice(device, &nvlinkStatus); - if (status != NV_OK) - goto cleanup_ecc; - - nvlinkVersion = getNvlinkConnectionToNpu(nvlinkStatus, - &atomicSupported, - &linkBandwidthMBps); - - sysmemLink = rmControlToUvmNvlinkVersion(nvlinkVersion); - - portMemFree(nvlinkStatus); - nvlinkStatus = NULL; - break; - } - case NV2080_CTRL_BUS_INFO_INDEX_SYSMEM_CONNECTION_TYPE_C2C: - { - NvBool c2cConnectedToCpu = NV_FALSE; - - status = getC2CConnectionToCpu(device, &c2cConnectedToCpu, &linkBandwidthMBps); - if (status != NV_OK) - goto cleanup_ecc; - - if (c2cConnectedToCpu == NV_FALSE) - { - NV_ASSERT(0); - status = NV_ERR_INVALID_STATE; - goto cleanup_ecc; - } - - sysmemLink = UVM_LINK_TYPE_C2C; - break; - } - case NV2080_CTRL_BUS_INFO_INDEX_SYSMEM_CONNECTION_TYPE_PCIE: - { - sysmemLink = UVM_LINK_TYPE_PCIE; - status = getPCIELinkRateMBps(device, &linkBandwidthMBps); - if (status != NV_OK) - goto cleanup_ecc; - break; - } - default: - { - NV_PRINTF(LEVEL_ERROR, "Unsupported sysmem connection type: %d\n", - sysmemConnType); - NV_ASSERT(0); - break; - } - } - - NV_PRINTF(LEVEL_INFO, "sysmem link type: %d bw: %u\n", sysmemLink, linkBandwidthMBps); - - NV_ASSERT(sysmemLink != UVM_LINK_TYPE_NONE); - device->sysmemLink = sysmemLink; - device->sysmemLinkRateMBps = linkBandwidthMBps; - - status = allocNvlinkStatusForSubdevice(device, &nvlinkStatus); - if (status != NV_OK) - goto cleanup_ecc; - nvlinkVersion = getNvlinkConnectionToSwitch(nvlinkStatus, - &linkBandwidthMBps); - - if (rmControlToUvmNvlinkVersion(nvlinkVersion) != UVM_LINK_TYPE_NONE) - { - NV_ASSERT(rmControlToUvmNvlinkVersion(nvlinkVersion) != UVM_LINK_TYPE_NVLINK_1); - - // If the GPU is ever connected to the CPU via a switch, sysmemLink - // and sysmemLinkRateMBps need to be updated accordingly. - NV_ASSERT(sysmemConnType != NV2080_CTRL_BUS_INFO_INDEX_SYSMEM_CONNECTION_TYPE_NVLINK); - - device->connectedToSwitch = NV_TRUE; - } - - portMemFree(nvlinkStatus); - mapInit(&device->kern2PhysDescrMap, portMemAllocatorGetGlobalNonPaged()); status = rmapiLockAcquire(RMAPI_LOCK_FLAGS_READ, RM_LOCK_MODULES_GPU_OPS); @@ -2093,7 +2022,8 @@ device->session->handle, device->handle, &gpuVaSpace->handle, FERMI_VASPACE_A, - &vaParams); + &vaParams, + sizeof(vaParams)); if (status != NV_OK) { goto cleanup_struct; @@ -2243,8 +2173,9 @@ // Get the NVLink connection status for the given device. On success, caller is // responsible of freeing the memory. -static NV_STATUS allocNvlinkStatusForSubdevice(struct gpuDevice *device, - NV2080_CTRL_CMD_NVLINK_GET_NVLINK_STATUS_PARAMS **nvlinkStatusOut) +static NV_STATUS allocNvlinkStatus(NvHandle hClient, + NvHandle hSubDevice, + NV2080_CTRL_CMD_NVLINK_GET_NVLINK_STATUS_PARAMS **nvlinkStatusOut) { NV_STATUS status; NV2080_CTRL_CMD_NVLINK_GET_NVLINK_STATUS_PARAMS *nvlinkStatus; @@ -2258,8 +2189,8 @@ portMemSet(nvlinkStatus, 0, sizeof(*nvlinkStatus)); status = pRmApi->Control(pRmApi, - device->session->handle, - device->subhandle, + hClient, + hSubDevice, NV2080_CTRL_CMD_NVLINK_GET_NVLINK_STATUS, nvlinkStatus, sizeof(*nvlinkStatus)); @@ -2342,7 +2273,8 @@ return version; } -static NV_STATUS getC2CConnectionToCpu(struct gpuDevice *device, +static NV_STATUS getC2CConnectionToCpu(NvHandle hClient, + NvHandle hSubDevice, NvBool *connectedToCpu, NvU32 *linkBandwidthMBps) { @@ -2353,8 +2285,8 @@ *linkBandwidthMBps = 0; NV_ASSERT_OK_OR_RETURN(pRmApi->Control(pRmApi, - device->session->handle, - device->subhandle, + hClient, + hSubDevice, NV2080_CTRL_CMD_BUS_GET_C2C_INFO, ¶ms, sizeof(params))); @@ -2462,8 +2394,7 @@ // communicate through P9 NPUs static NV_STATUS gpusHaveNpuNvlink(NV2080_CTRL_CMD_NVLINK_GET_NVLINK_STATUS_PARAMS *nvlinkStatus1, NV2080_CTRL_CMD_NVLINK_GET_NVLINK_STATUS_PARAMS *nvlinkStatus2, - NvU32 *nvlinkVersion, - NvU32 *linkBandwidthMBps) + NvU32 *nvlinkVersion) { NvU32 nvlinkVersion1, nvlinkVersion2; NvU32 tmpLinkBandwidthMBps; @@ -2502,11 +2433,6 @@ // access B. *nvlinkVersion = NV_MIN(nvlinkVersion1, nvlinkVersion2); - // Link bandwidth not provided because the intermediate link rate could - // vary a lot with system topologies & current load, making this bandwidth - // obsolete. - *linkBandwidthMBps = 0; - return NV_OK; } @@ -2614,7 +2540,7 @@ *nvlinkVersion = NV2080_CTRL_NVLINK_STATUS_NVLINK_VERSION_INVALID; - if (device1->connectedToSwitch && device2->connectedToSwitch) + if (device1->info.connectedToSwitch && device2->info.connectedToSwitch) { nvlinkVersion1 = getNvlinkConnectionToSwitch(nvlinkStatus1, &linkBandwidthMBps1); @@ -2684,11 +2610,15 @@ if (!p2pCapsParams) return NV_ERR_INVALID_ARGUMENT; - status = allocNvlinkStatusForSubdevice(device1, &nvlinkStatus1); + status = allocNvlinkStatus(device1->session->handle, + device1->subhandle, + &nvlinkStatus1); if (status != NV_OK) goto cleanup; - status = allocNvlinkStatusForSubdevice(device2, &nvlinkStatus2); + status = allocNvlinkStatus(device2->session->handle, + device2->subhandle, + &nvlinkStatus2); if (status != NV_OK) goto cleanup; @@ -2705,26 +2635,27 @@ if (p2pCaps.indirectAccessSupported) { NvU32 nvlinkVersion; - NvU32 linkBandwidthMBps; NvU32 p2pLink; status = gpusHaveNpuNvlink(nvlinkStatus1, nvlinkStatus2, - &nvlinkVersion, - &linkBandwidthMBps); + &nvlinkVersion); if (status != NV_OK) goto cleanup; p2pLink = rmControlToUvmNvlinkVersion(nvlinkVersion); NV_ASSERT(p2pLink >= UVM_LINK_TYPE_NVLINK_2); - NV_ASSERT(linkBandwidthMBps == 0); p2pCapsParams->indirectAccess = NV_TRUE; p2pCapsParams->p2pLink = p2pLink; p2pCapsParams->optimalNvlinkWriteCEs[0] = p2pCaps.optimalNvlinkWriteCEs[0]; p2pCapsParams->optimalNvlinkWriteCEs[1] = p2pCaps.optimalNvlinkWriteCEs[1]; - p2pCapsParams->totalLinkLineRateMBps = linkBandwidthMBps; + + // Link bandwidth not provided because the intermediate link rate could + // vary a lot with system topologies & current load, making this bandwidth + // obsolete. + p2pCapsParams->totalLinkLineRateMBps = 0; } else if (p2pCaps.accessSupported) { @@ -2760,11 +2691,15 @@ { NvU32 linkBandwidthMBps1, linkBandwidthMBps2; - status = getPCIELinkRateMBps(device1, &linkBandwidthMBps1); + status = getPCIELinkRateMBps(device1->session->handle, + device1->subhandle, + &linkBandwidthMBps1); if (status != NV_OK) goto cleanup; - status = getPCIELinkRateMBps(device2, &linkBandwidthMBps2); + status = getPCIELinkRateMBps(device2->session->handle, + device2->subhandle, + &linkBandwidthMBps2); if (status != NV_OK) goto cleanup; @@ -3009,10 +2944,10 @@ ( OBJGPU *pGpu, MEMORY_DESCRIPTOR *pMemDesc, - NvU32 *pPageSize + NvU64 *pPageSize ) { - NvU32 pageSize; + NvU64 pageSize; MemoryManager *pMemoryManager = GPU_GET_MEMORY_MANAGER(pGpu); NV_STATUS status; @@ -3062,7 +2997,8 @@ GMMU_ENTRY_VALUE pte = {{0}}; NvU64 fabricBaseAddress = NVLINK_INVALID_FABRIC_ADDR; - NvU32 kind, pageSize; + NvU32 kind; + NvU64 pageSize; NvU32 skipPteCount; NvBool vol, atomic, readOnly; NvBool encrypted, privileged; @@ -3077,6 +3013,7 @@ NvU64 gpaOffset; NvBool *isPLCable = NULL; NvU64 *guestPhysicalAddress = NULL; + NvU64 mappingPageSize = pGpuExternalMappingInfo->mappingPageSize; NV_ASSERT(!memdescHasSubDeviceMemDescs(pMemDesc)); @@ -3086,6 +3023,21 @@ if (status != NV_OK) return status; + // + // Default mappingPageSize to allocation's page size if passed as 0. + // If mappingPageSize is non-zero, it must be a multiple of pageSize. + // Also, mapping page size cannot be larger than alloc page size. + // + if (mappingPageSize == 0) + { + mappingPageSize = pageSize; + } + else if ((mappingPageSize > pageSize) || + (pageSize % mappingPageSize != 0)) + { + return NV_ERR_INVALID_ARGUMENT; + } + // memdescGetSize returns the requested size of the allocation. But, the // actual allocation size could be larger than the requested size due // to alignment requirement. So, make sure the correct size is used. @@ -3098,10 +3050,10 @@ if ((offset + size) > allocSize) return NV_ERR_INVALID_LIMIT; - if ((size & (pageSize - 1)) != 0) + if ((size & (mappingPageSize - 1)) != 0) return NV_ERR_INVALID_ARGUMENT; - if ((offset & (pageSize - 1)) != 0) + if ((offset & (mappingPageSize - 1)) != 0) return NV_ERR_INVALID_ARGUMENT; pGVAS = dynamicCast(pVAS, OBJGVASPACE); @@ -3109,7 +3061,7 @@ // Get the GMMU format pFmt = gvaspaceGetGmmuFmt(pGVAS, pMappingGpu); pPteFmt = (GMMU_FMT_PTE*)pFmt->pPte; - pLevelFmt = mmuFmtFindLevelWithPageShift(pFmt->pRoot, BIT_IDX_32(pageSize)); + pLevelFmt = mmuFmtFindLevelWithPageShift(pFmt->pRoot, BIT_IDX_64(mappingPageSize)); oldKind = newKind = memdescGetPteKindForGpu(pMemDesc, pMappingGpu); if (pMemory) @@ -3162,7 +3114,18 @@ isCompressedKind = memmgrIsKind_HAL(pMemoryManager, FB_IS_KIND_COMPRESSIBLE, kind); - pteCount = NV_MIN((pGpuExternalMappingInfo->pteBufferSize / pLevelFmt->entrySize), (mappingSize / pageSize)); + // + // Specifying mapping page size for compressed + // allocations is not yet supported. + // + if (isCompressedKind && (pGpuExternalMappingInfo->mappingPageSize != 0) && + (pGpuExternalMappingInfo->mappingPageSize != pageSize)) + { + return NV_ERR_NOT_SUPPORTED; + } + + pteCount = NV_MIN((pGpuExternalMappingInfo->pteBufferSize / pLevelFmt->entrySize), + (mappingSize / mappingPageSize)); if (!pteCount) return NV_ERR_BUFFER_TOO_SMALL; @@ -3274,7 +3237,8 @@ // it requires IOMMU mappings to be set up and these are different for each // GPU. The IOMMU mappings are currently added by nvGpuOpsDupMemory(). // - memdescGetPhysAddrsForGpu(pMemDesc, pMappingGpu, AT_GPU, offset, pageSize, pteCount, physicalAddresses); + memdescGetPhysAddrsForGpu(pMemDesc, pMappingGpu, AT_GPU, offset, mappingPageSize, + pteCount, physicalAddresses); kgmmuEncodePhysAddrs(pKernelGmmu, aperture, physicalAddresses, fabricBaseAddress, pteCount); @@ -3299,7 +3263,7 @@ for (iter = 0; iter < pteCount; iter++) { guestPhysicalAddress[iter] = gpaOffset; - gpaOffset += pageSize; + gpaOffset += mappingPageSize; } isPLCable = portMemAllocNonPaged((NvU32)pteCount * sizeof(*isPLCable)); @@ -3311,7 +3275,7 @@ portMemSet(isPLCable, 0, ((NvU32)pteCount * sizeof(*isPLCable))); - NV_RM_RPC_GET_PLCABLE_ADDRESS_KIND(pMappingGpu, guestPhysicalAddress, pageSize, (NvU32)pteCount, + NV_RM_RPC_GET_PLCABLE_ADDRESS_KIND(pMappingGpu, guestPhysicalAddress, mappingPageSize, (NvU32)pteCount, isPLCable, status); if (status != NV_OK) goto done; @@ -3356,7 +3320,8 @@ } else { - bEnablePlc = kmemsysIsPagePLCable_HAL(pMappingGpu, pKernelMemorySystem, offset, pageSize); + bEnablePlc = kmemsysIsPagePLCable_HAL(pMappingGpu, pKernelMemorySystem, + offset, mappingPageSize); } if (!bEnablePlc) @@ -3378,11 +3343,11 @@ portMemCopy(&pGpuExternalMappingInfo->pteBuffer[iter * skipPteCount], pLevelFmt->entrySize, pte.v8, pLevelFmt->entrySize); - offset += pageSize; + offset += mappingPageSize; } pGpuExternalMappingInfo->numWrittenPtes = pteCount; - pGpuExternalMappingInfo->numRemainingPtes = (mappingSize / pageSize) - pteCount; + pGpuExternalMappingInfo->numRemainingPtes = (mappingSize / mappingPageSize) - pteCount; pGpuExternalMappingInfo->pteSize = pLevelFmt->entrySize; done: @@ -3481,8 +3446,6 @@ (memdescGetAddressSpace(pAdjustedMemDesc) == ADDR_FABRIC_MC) || (memdescGetAddressSpace(pAdjustedMemDesc) == ADDR_FABRIC_V2)) { - KernelNvlink *pKernelNvlink = GPU_GET_KERNEL_NVLINK(pMappingGpu); - isPeerSupported = NV_TRUE; pPeerGpu = pAdjustedMemDesc->pGpu; peerId = BUS_INVALID_PEER; @@ -3497,10 +3460,21 @@ if (pPeerGpu != NULL) { - if ((pKernelNvlink != NULL) && - knvlinkIsNvlinkP2pSupported(pMappingGpu, pKernelNvlink, pPeerGpu)) + if (IS_VIRTUAL_WITH_SRIOV(pMappingGpu) && + !gpuIsWarBug200577889SriovHeavyEnabled(pMappingGpu)) { - peerId = kbusGetPeerId_HAL(pMappingGpu, GPU_GET_KERNEL_BUS(pMappingGpu), pPeerGpu); + peerId = kbusGetNvlinkPeerId_HAL(pMappingGpu, + GPU_GET_KERNEL_BUS(pMappingGpu), + pPeerGpu); + } + else + { + KernelNvlink *pKernelNvlink = GPU_GET_KERNEL_NVLINK(pMappingGpu); + if ((pKernelNvlink != NULL) && + knvlinkIsNvlinkP2pSupported(pMappingGpu, pKernelNvlink, pPeerGpu)) + { + peerId = kbusGetPeerId_HAL(pMappingGpu, GPU_GET_KERNEL_BUS(pMappingGpu), pPeerGpu); + } } } else @@ -3706,6 +3680,17 @@ memAllocParams.flags |= NVOS32_ALLOC_FLAGS_PERSISTENT_VIDMEM; // + // Indicate to the RM that the allocation should be in unprotected memory. + // If the Confidential Computing feature is not enabled on the system, this + // flag has no effect. + // + if (allocInfo->bUnprotected) + { + memAllocParams.attr2 = FLD_SET_DRF(OS32, _ATTR2, _MEMORY_PROTECTION, + _UNPROTECTED, memAllocParams.attr2); + } + + // // vid heap ctrl has a different policy as compared to other internal APIS // it expects the gpu lock to not be held. This means we have to drop the gpu lock // here. It is safe in this scenario because we still have the API lock and nothing @@ -3718,7 +3703,8 @@ isSystemMemory ? device->handle : device->subhandle, &physHandle, isSystemMemory ? NV01_MEMORY_SYSTEM : NV01_MEMORY_LOCAL_USER, - &memAllocParams), done); + &memAllocParams, + sizeof(memAllocParams)), done); if (allocInfo->bContiguousPhysAlloc) allocInfo->gpuPhysOffset = memAllocParams.offset; @@ -3796,7 +3782,8 @@ vaSpace->device->handle, &memDesc->handle, NV50_MEMORY_VIRTUAL, - &memAllocParams), done); + &memAllocParams, + sizeof(memAllocParams)), done); memDesc->address = (NvU64)memAllocParams.offset; memDesc->size = length; memDesc->childHandle = physHandle; @@ -3826,7 +3813,7 @@ static NV_STATUS nvGpuOpsMapGpuMemory(struct gpuAddressSpace *vaSpace, NvU64 vaOffset, NvLength length, - NvU32 pageSize, + NvU64 pageSize, NvU64 *gpuOffset, struct allocFlags flags) { @@ -3834,7 +3821,7 @@ NV_STATUS status; NvU64 mappedVa = 0; NvU32 mapFlags = 0; - NvU32 mapPageSize = 0; + NvU64 mapPageSize = 0; RM_API *pRmApi = rmapiGetInterface(RMAPI_EXTERNAL_KERNEL); if (!vaSpace || !gpuOffset) @@ -3947,6 +3934,38 @@ return status; } +// This function is generic and can be used outside CC as well. +// As of today the only caller of this function is under CC checks +// Hence this is also protected under the same checks. Otherwise, +// builds will fail. +static void nvGpuOpsUnmapGpuMemory(struct gpuAddressSpace *vaSpace, + NvU64 gpuOffset) +{ + gpuMemDesc *memDescVa = NULL; + RM_API *pRmApi = rmapiGetInterface(RMAPI_EXTERNAL_KERNEL); + + NV_ASSERT(vaSpace != NULL); + + portSyncRwLockAcquireRead(vaSpace->allocationsLock); + NV_ASSERT_OK(findDescriptor(vaSpace->allocations, gpuOffset, (void**)&memDescVa)); + portSyncRwLockReleaseRead(vaSpace->allocationsLock); + + NV_ASSERT(memDescVa != NULL); + NV_ASSERT(memDescVa->handle != 0); + NV_ASSERT(memDescVa->childHandle != 0); + NV_ASSERT(memDescVa->address == gpuOffset); + + NV_ASSERT_OK(pRmApi->Unmap(pRmApi, + vaSpace->device->session->handle, + vaSpace->device->handle, + memDescVa->handle, + memDescVa->childHandle, + NV04_MAP_MEMORY_FLAGS_NONE, + gpuOffset)); + + return; +} + static void nvGpuOpsFreeVirtual(struct gpuAddressSpace *vaSpace, NvU64 vaOffset) { RM_API *pRmApi = rmapiGetInterface(RMAPI_EXTERNAL_KERNEL); @@ -4106,7 +4125,7 @@ return status; } -NV_STATUS nvGpuOpsPmaAllocPages(void *pPma, NvLength pageCount, NvU32 pageSize, +NV_STATUS nvGpuOpsPmaAllocPages(void *pPma, NvLength pageCount, NvU64 pageSize, gpuPmaAllocationOptions *pPmaAllocOptions, NvU64 *pPages) { @@ -4149,7 +4168,7 @@ NV_STATUS nvGpuOpsPmaPinPages(void *pPma, NvU64 *pPages, NvLength pageCount, - NvU32 pageSize, + NvU64 pageSize, NvU32 flags) { NV_STATUS status; @@ -4173,7 +4192,7 @@ NV_STATUS nvGpuOpsPmaUnpinPages(void *pPma, NvU64 *pPages, NvLength pageCount, - NvU32 pageSize) + NvU64 pageSize) { NV_STATUS status; THREAD_STATE_NODE threadState; @@ -4197,7 +4216,7 @@ void nvGpuOpsPmaFreePages(void *pPma, NvU64 *pPages, NvLength pageCount, - NvU32 pageSize, + NvU64 pageSize, NvU32 flags) { THREAD_STATE_NODE threadState; @@ -4231,8 +4250,8 @@ params.pChannelList = NV_PTR_TO_NvP64(hwChannelId); return pRmApi->Control(pRmApi, - channel->vaSpace->device->session->handle, - channel->vaSpace->device->handle, + channel->tsg->vaSpace->device->session->handle, + channel->tsg->vaSpace->device->handle, NV0080_CTRL_CMD_FIFO_GET_CHANNELLIST, ¶ms, sizeof(params)); @@ -4280,16 +4299,18 @@ subDeviceDesc *rmSubDevice = device->rmSubDevice; NvU32 usermodeClass = VOLTA_USERMODE_A; void *pParams = NULL; + NvU32 paramsSize = 0; NV_HOPPER_USERMODE_A_PARAMS hopperParams = { .bBar1Mapping = NV_TRUE, .bPriv = NV_FALSE }; - if (device->rmDevice->arch >= GPU_ARCHITECTURE_HOPPER) + if (isDeviceHopperPlus(device)) { usermodeClass = HOPPER_USERMODE_A; pParams = &hopperParams; + paramsSize = sizeof(hopperParams); } NV_ASSERT(isDeviceVoltaPlus(device)); @@ -4301,7 +4322,9 @@ device->subhandle, ®ionHandle, usermodeClass, - pParams); + pParams, + paramsSize); + if (NV_OK != status) return status; @@ -4368,17 +4391,68 @@ (NV_CHANNELGPFIFO_NOTIFICATION_TYPE_WORK_SUBMIT_TOKEN * sizeof(NvNotification)) + NV_OFFSETOF(NvNotification, info32)); + { + OBJGPU *pGpu; + RsClient *pClient; + Device *pDevice; + + status = serverGetClientUnderLock(&g_resServ, session->handle, &pClient); + if (status != NV_OK) + return status; + + status = deviceGetByHandle(pClient, device->handle, &pDevice); + if (status != NV_OK) + return status; + + pGpu = GPU_RES_GET_GPU(pDevice); + + // Map the usermode region in channel's vaspace + if (gpuIsCCFeatureEnabled(pGpu)) + { + NvU64 vaOffset = 0; + NvU64 gpuOffset = 0; + gpuVaAllocInfo vaAllocInfo = {0}; + struct allocFlags flags = {0}; + + NV_ASSERT(isDeviceHopperPlus(device)); + + status = nvGpuOpsAllocVirtual(vaSpace, NVC361_NV_USERMODE__SIZE, &vaOffset, + rmSubDevice->clientRegionHandle, + flags, &vaAllocInfo); + if (status != NV_OK) + return status; + + status = nvGpuOpsMapGpuMemory(vaSpace, vaOffset, NVC361_NV_USERMODE__SIZE, + vaAllocInfo.pageSize, &gpuOffset, flags); + if (status != NV_OK) + { + nvGpuOpsFreeVirtual(vaSpace, vaOffset); + return status; + } + + channel->bClientRegionGpuMappingNeeded = NV_TRUE; + channel->clientRegionGpuAddr = gpuOffset; + } + } + return status; } static NvBool channelNeedsDummyAlloc(struct gpuChannel *channel) { - return channel->gpPutLoc == UVM_BUFFER_LOCATION_SYS && deviceNeedsDummyAlloc(channel->vaSpace->device); + if (deviceNeedsDummyAlloc(channel->tsg->vaSpace->device)) + { + return isDeviceHopperPlus(channel->tsg->vaSpace->device) ? + channel->gpPutLoc == UVM_BUFFER_LOCATION_VID : + channel->gpPutLoc == UVM_BUFFER_LOCATION_SYS; + } + + return NV_FALSE; } static NV_STATUS channelRetainDummyAlloc(struct gpuChannel *channel, gpuChannelInfo *channelInfo) { - struct gpuAddressSpace *vaSpace = channel->vaSpace; + struct gpuAddressSpace *vaSpace = channel->tsg->vaSpace; NV_STATUS status; if (!channelNeedsDummyAlloc(channel)) @@ -4399,32 +4473,34 @@ if (channel != NULL && channel->retainedDummyAlloc) { NV_ASSERT(channelNeedsDummyAlloc(channel)); - nvGpuOpsVaSpaceReleaseDummyAlloc(channel->vaSpace); + nvGpuOpsVaSpaceReleaseDummyAlloc(channel->tsg->vaSpace); } } -static RM_ENGINE_TYPE channelEngineType(const struct gpuChannel *channel) +static RM_ENGINE_TYPE tsgEngineType(const struct gpuTsg *tsg) { - if (channel->engineType == UVM_GPU_CHANNEL_ENGINE_TYPE_CE) - return RM_ENGINE_TYPE_COPY(channel->engineIndex); - else if (channel->engineType == UVM_GPU_CHANNEL_ENGINE_TYPE_SEC2) + NV_ASSERT(tsg->engineType == UVM_GPU_CHANNEL_ENGINE_TYPE_CE || tsg->engineType == UVM_GPU_CHANNEL_ENGINE_TYPE_SEC2); + + if (tsg->engineType == UVM_GPU_CHANNEL_ENGINE_TYPE_SEC2) return RM_ENGINE_TYPE_SEC2; else - return RM_ENGINE_TYPE_GR(channel->engineIndex); + return RM_ENGINE_TYPE_COPY(tsg->engineIndex); } -static NV_STATUS channelAllocate(struct gpuAddressSpace *vaSpace, - UVM_GPU_CHANNEL_ENGINE_TYPE engineType, +static NV_STATUS channelAllocate(const gpuTsgHandle tsg, const gpuChannelAllocParams *params, struct gpuChannel **channelHandle, gpuChannelInfo *channelInfo) { NV_STATUS status; + nvGpuOpsLockSet acquiredLocks; + struct gpuAddressSpace *vaSpace = NULL; struct gpuChannel *channel = NULL; struct gpuDevice *device = NULL; struct gpuSession *session = NULL; void *cpuMap = NULL; NvHandle hErrorNotifier; + NvHandle hTsg; struct ChannelAllocInfo *pAllocInfo = NULL; void *gpfifoCtrl = NULL; PCLI_DMA_MAPPING_INFO pDmaMappingInfo = NULL; @@ -4437,20 +4513,12 @@ UVM_BUFFER_LOCATION gpPutLoc; NvLength gpFifoSize, errorNotifierSize; RM_API *pRmApi = rmapiGetInterface(RMAPI_EXTERNAL_KERNEL); - - if (!vaSpace || !channelHandle || !params || !channelInfo) - return NV_ERR_INVALID_ARGUMENT; + RsClient *pClient; if (params->numGpFifoEntries == 0) return NV_ERR_INVALID_ARGUMENT; - if (engineType != UVM_GPU_CHANNEL_ENGINE_TYPE_CE && - engineType != UVM_GPU_CHANNEL_ENGINE_TYPE_GR && - engineType != UVM_GPU_CHANNEL_ENGINE_TYPE_SEC2) - return NV_ERR_INVALID_ARGUMENT; - - // TODO: Bug 2458492: Ampere-SMC Verify GR/CE indices within partition/SMC Engine - + vaSpace = tsg->vaSpace; device = vaSpace->device; NV_ASSERT(device); session = device->session; @@ -4509,21 +4577,32 @@ portMemSet(channel, 0, sizeof(*channel)); - channel->vaSpace = vaSpace; + channel->tsg = tsg; channel->fifoEntries = params->numGpFifoEntries; channel->gpFifoLoc = gpFifoLoc; channel->gpPutLoc = gpPutLoc; - // Remember which engine we are using, so that RC recovery can reset it if - // it hangs: - channel->engineType = engineType; - channel->engineIndex = params->engineIndex; - gpFifoSize = (NvLength)params->numGpFifoEntries * NVA06F_GP_ENTRY__SIZE; // If the allocation is vidmem ask RM to allocate persistent vidmem pAllocInfo->gpuAllocInfo.bPersistentVidmem = NV_TRUE; + if (gpuIsCCorApmFeatureEnabled(pGpu)) + { + // Gpfifo can be placed in one of the following locations + // 1. Unprotected sysmem in case of both APM and HCC + // 2. Unprotected vidmem in case of APM + // 3. Protected vidmem in case of HCC + if ((gpFifoLoc == UVM_BUFFER_LOCATION_SYS) || gpuIsApmFeatureEnabled(pGpu)) + { + pAllocInfo->gpuAllocInfo.bUnprotected = NV_TRUE; + } + else + { + pAllocInfo->gpuAllocInfo.bUnprotected = NV_FALSE; + } + } + // 1. Allocate the GPFIFO entries. Dont pass any special flags. flags.bGetKernelVA = NV_FALSE; status = nvGpuOpsGpuMalloc(vaSpace, @@ -4536,13 +4615,18 @@ goto cleanup_free_memory; // 2. Map the gpfifo entries - status = nvGpuOpsMemoryCpuMap(vaSpace, - channel->gpFifo, - gpFifoSize, - &cpuMap, - PAGE_SIZE_DEFAULT); - if (status != NV_OK) - goto cleanup_free_gpfifo_entries; + // Skip this whenever HCC is enabled and GPFIFO is in vidmem. CPU access + // to vidmem is blocked in that scenario + if (!gpuIsCCFeatureEnabled(pGpu) || (gpFifoLoc == UVM_BUFFER_LOCATION_SYS)) + { + status = nvGpuOpsMemoryCpuMap(vaSpace, + channel->gpFifo, + gpFifoSize, + &cpuMap, + PAGE_SIZE_DEFAULT); + if (status != NV_OK) + goto cleanup_free_gpfifo_entries; + } channel->gpFifoEntries = (NvU64 *) cpuMap; @@ -4551,6 +4635,12 @@ // sufficiently large to also accommodate any other channel // notifiers, and request a kernel VA and CPU caching. // + if (gpuIsCCorApmFeatureEnabled(pGpu)) + { + // Put notifier in unprotected sysmem + pAllocInfo->gpuAllocInfo.bUnprotected = NV_TRUE; + } + flags.bGetKernelVA = NV_TRUE; errorNotifierSize = sizeof(NvNotification) * NV_CHANNELGPFIFO_NOTIFICATION_TYPE__SIZE_1; @@ -4575,23 +4665,24 @@ // 4. Find and share the VA with UVM driver // TODO: Acquired because CliGetDmaMappingInfo expects RMAPI lock. Necessary? - status = rmapiLockAcquire(RMAPI_LOCK_FLAGS_READ, RM_LOCK_MODULES_GPU_OPS); + status = _nvGpuOpsLocksAcquire(RMAPI_LOCK_FLAGS_READ, session->handle, &pClient, 0, + 0, 0, &acquiredLocks); if (status != NV_OK) goto cleanup_free_virtual; - if (!CliGetDmaMappingInfo(session->handle, + if (!CliGetDmaMappingInfo(pClient, device->handle, hErrorNotifier, channel->errorNotifierOffset, gpumgrGetDeviceGpuMask(device->deviceInstance), &pDmaMappingInfo)) { - rmapiLockRelease(); + _nvGpuOpsLocksRelease(&acquiredLocks); status = NV_ERR_GENERIC; goto cleanup_free_virtual; } - rmapiLockRelease(); + _nvGpuOpsLocksRelease(&acquiredLocks); // // RM uses the parent subdevice index to fill the notifier on SYSMEM. So use the same. @@ -4615,12 +4706,30 @@ pAllocInfo->gpFifoAllocParams.gpFifoOffset = channel->gpFifo; pAllocInfo->gpFifoAllocParams.gpFifoEntries = channel->fifoEntries; - // If zero then it will attach to the device address space - pAllocInfo->gpFifoAllocParams.hVASpace = vaSpace->handle; - pAllocInfo->gpFifoAllocParams.engineType = gpuGetNv2080EngineType(channelEngineType(channel)); if (isDeviceVoltaPlus(device)) { + if (gpuIsCCorApmFeatureEnabled(pGpu)) + { + // All channels are allocated as secure when the Confidential + // Computing feature is enabled. + pAllocInfo->gpFifoAllocParams.flags = FLD_SET_DRF(OS04, _FLAGS, _CC_SECURE, _TRUE, + pAllocInfo->gpFifoAllocParams.flags); + + // USERD can be placed in one of the following locations + // 1. Unprotected sysmem in case of both APM and HCC + // 2. Unprotected vidmem in case of APM + // 3. Protected vidmem in case of HCC + if ((gpPutLoc == UVM_BUFFER_LOCATION_SYS) || gpuIsApmFeatureEnabled(pGpu)) + { + pAllocInfo->gpuAllocInfo.bUnprotected = NV_TRUE; + } + else + { + pAllocInfo->gpuAllocInfo.bUnprotected = NV_FALSE; + } + } + flags.bGetKernelVA = NV_FALSE; status = nvGpuOpsGpuMalloc(vaSpace, gpPutLoc == UVM_BUFFER_LOCATION_SYS, @@ -4638,21 +4747,46 @@ pAllocInfo->gpFifoAllocParams.userdOffset[gpumgrGetSubDeviceInstanceFromGpu(pGpu)] = 0; SLI_LOOP_END - status = nvGpuOpsMemoryCpuMap(vaSpace, - channel->userdGpuAddr, - sizeof(KeplerAControlGPFifo), - &gpfifoCtrl, - PAGE_SIZE_DEFAULT); - if (status != NV_OK) - goto cleanup_free_virtual; + // Skip this whenever HCC is enabled and USERD is in vidmem. CPU access + // to vidmem is blocked in that scenario. + if (!gpuIsCCFeatureEnabled(pGpu) || (gpPutLoc == UVM_BUFFER_LOCATION_SYS)) + { + status = nvGpuOpsMemoryCpuMap(vaSpace, + channel->userdGpuAddr, + sizeof(KeplerAControlGPFifo), + &gpfifoCtrl, + PAGE_SIZE_DEFAULT); + if (status != NV_OK) + goto cleanup_free_virtual; + } + } + + pAllocInfo->gpFifoAllocParams.engineType = gpuGetNv2080EngineType(tsgEngineType(channel->tsg)); + + if (channel->tsg->isFakeTsg) + { + // The internal RM TSG requires a valid vaSpace object. + pAllocInfo->gpFifoAllocParams.hVASpace = vaSpace->handle; + + // Not a Tsg, device handle parents a channel when RM internal TSG is + // used. + hTsg = device->handle; + } + else + { + // If zero then it will attach to the TSG address space. + pAllocInfo->gpFifoAllocParams.hVASpace = NV01_NULL_OBJECT; + hTsg = channel->tsg->tsgHandle; } channel->channelHandle = NV01_NULL_OBJECT; - status = pRmApi->Alloc(pRmApi, session->handle, - device->handle, + status = pRmApi->Alloc(pRmApi, + session->handle, + hTsg, &channel->channelHandle, device->hostClass, - &pAllocInfo->gpFifoAllocParams); + &pAllocInfo->gpFifoAllocParams, + sizeof(pAllocInfo->gpFifoAllocParams)); if (status != NV_OK) { goto cleanup_free_virtual; @@ -4663,7 +4797,7 @@ status = kfifoEngineInfoXlate_HAL(pGpu, pKernelFifo, ENGINE_INFO_TYPE_RM_ENGINE_TYPE, - (NvU32)channelEngineType(channel), + (NvU32)tsgEngineType(channel->tsg), ENGINE_INFO_TYPE_RUNLIST, &channel->hwRunlistId); if (status != NV_OK) @@ -4691,12 +4825,18 @@ channel->controlPage = gpfifoCtrl; - status = channelRetainDummyAlloc(channel, channelInfo); - if (status != NV_OK) - goto cleanup_free_controlpage; + // We create a BAR1 pointer inside channelRetainDummyAlloc and issue reads + // on the same to push pending BAR1 writes to vidmem. With HCC, BAR1 access + // to vidmem is blocked and hence there is no point creating the pointer + if (!gpuIsCCFeatureEnabled(pGpu)) + { + status = channelRetainDummyAlloc(channel, channelInfo); + if (status != NV_OK) + goto cleanup_free_controlpage; + } // Allocate the SW method class for fault cancel - if (isDevicePascalPlus(device) && (engineType != UVM_GPU_CHANNEL_ENGINE_TYPE_SEC2)) + if (isDevicePascalPlus(device) && (channel->tsg->engineType != UVM_GPU_CHANNEL_ENGINE_TYPE_SEC2)) { channel->hFaultCancelSwMethodClass = NV01_NULL_OBJECT; status = pRmApi->Alloc(pRmApi, @@ -4704,7 +4844,8 @@ channel->channelHandle, &channel->hFaultCancelSwMethodClass, GP100_UVM_SW, - NULL); + NULL, + 0); if (status != NV_OK) goto cleanup_free_controlpage; } @@ -4712,8 +4853,8 @@ portMemFree(pAllocInfo); *channelHandle = channel; - channelInfo->gpGet = &channel->controlPage->GPGet; - channelInfo->gpPut = &channel->controlPage->GPPut; + channelInfo->gpGet = (channel->controlPage != NULL) ? &channel->controlPage->GPGet : NULL; + channelInfo->gpPut = (channel->controlPage != NULL) ? &channel->controlPage->GPPut : NULL; channelInfo->gpFifoEntries = channel->gpFifoEntries; channelInfo->channelClassNum = device->hostClass; channelInfo->numGpFifoEntries = channel->fifoEntries; @@ -4721,6 +4862,10 @@ channelInfo->hwRunlistId = channel->hwRunlistId; channelInfo->hwChannelId = channel->hwChannelId; + channelInfo->gpFifoGpuVa = channel->gpFifo; + channelInfo->gpPutGpuVa = channel->userdGpuAddr + NV_OFFSETOF(KeplerAControlGPFifo, GPPut); + channelInfo->gpGetGpuVa = channel->userdGpuAddr + NV_OFFSETOF(KeplerAControlGPFifo, GPGet); + return NV_OK; cleanup_free_controlpage: @@ -4754,7 +4899,6 @@ static NV_STATUS engineAllocate(struct gpuChannel *channel, gpuChannelInfo *channelInfo, UVM_GPU_CHANNEL_ENGINE_TYPE engineType) { NV_STATUS status = NV_OK; - struct gpuObject *object = NULL; NVB0B5_ALLOCATION_PARAMETERS ceAllocParams = {0}; NVA06F_CTRL_GPFIFO_SCHEDULE_PARAMS channelGrpParams = {0}; struct gpuAddressSpace *vaSpace = NULL; @@ -4762,49 +4906,45 @@ struct gpuSession *session = NULL; RM_API *pRmApi = rmapiGetInterface(RMAPI_EXTERNAL_KERNEL); NvU32 class; + NvU32 paramsSize; void *params; NV_ASSERT(channel); NV_ASSERT(channelInfo); - NV_ASSERT(channel->engineType == UVM_GPU_CHANNEL_ENGINE_TYPE_CE || - channel->engineType == UVM_GPU_CHANNEL_ENGINE_TYPE_SEC2); - - // TODO: Bug 2458492: Ampere-SMC Verify GR/CE indices within partition + NV_ASSERT(engineType == UVM_GPU_CHANNEL_ENGINE_TYPE_CE || engineType == UVM_GPU_CHANNEL_ENGINE_TYPE_SEC2); - vaSpace = channel->vaSpace; + vaSpace = channel->tsg->vaSpace; NV_ASSERT(vaSpace); device = vaSpace->device; NV_ASSERT(device); session = device->session; NV_ASSERT(session); - object = portMemAllocNonPaged(sizeof(*object)); - if (object == NULL) - return NV_ERR_NO_MEMORY; - - object->handle = NV01_NULL_OBJECT; - if (engineType == UVM_GPU_CHANNEL_ENGINE_TYPE_CE) { ceAllocParams.version = NVB0B5_ALLOCATION_PARAMETERS_VERSION_1; - ceAllocParams.engineType = NV2080_ENGINE_TYPE_COPY(channel->engineIndex); + ceAllocParams.engineType = NV2080_ENGINE_TYPE_COPY(channel->tsg->engineIndex); params = &ceAllocParams; + paramsSize = sizeof(ceAllocParams); class = device->ceClass; } else { params = NULL; + paramsSize = 0; class = device->sec2Class; } + channel->engineHandle = NV01_NULL_OBJECT; status = pRmApi->Alloc(pRmApi, session->handle, channel->channelHandle, - &object->handle, + &channel->engineHandle, class, - params); + params, + paramsSize); if (status != NV_OK) - goto cleanup_free_memory; + return status; // In volta+ gpus, the channel has a submission offset used as doorbell. if (isDeviceVoltaPlus(device)) @@ -4816,6 +4956,11 @@ channelInfo->workSubmissionOffset = channel->workSubmissionOffset; channelInfo->workSubmissionToken = channel->workSubmissionToken; channelInfo->pWorkSubmissionToken = channel->pWorkSubmissionToken; + if (channel->bClientRegionGpuMappingNeeded) + { + channelInfo->workSubmissionOffsetGpuVa = channel->clientRegionGpuAddr + + NVC361_NOTIFY_CHANNEL_PENDING; + } } // Schedule the channel @@ -4830,45 +4975,47 @@ if (status != NV_OK) goto cleanup_free_engine; - object->next = channel->nextAttachedEngine; - channel->nextAttachedEngine = object; - object->type = class; - return NV_OK; cleanup_free_engine: - pRmApi->Free(pRmApi, session->handle, object->handle); -cleanup_free_memory: - portMemFree(object); + pRmApi->Free(pRmApi, session->handle, channel->engineHandle); + channel->engineHandle = NV01_NULL_OBJECT; return status; } -NV_STATUS nvGpuOpsChannelAllocate(struct gpuAddressSpace *vaSpace, +NV_STATUS nvGpuOpsChannelAllocate(const gpuTsgHandle tsg, const gpuChannelAllocParams *params, struct gpuChannel **channelHandle, gpuChannelInfo *channelInfo) { NV_STATUS status; - UVM_GPU_CHANNEL_ENGINE_TYPE channelType = params->engineType; + UVM_GPU_CHANNEL_ENGINE_TYPE channelType; + + if (!tsg || !channelHandle || !params || !channelInfo) + return NV_ERR_INVALID_ARGUMENT; - NV_ASSERT_OR_RETURN((channelType == UVM_GPU_CHANNEL_ENGINE_TYPE_CE || channelType == UVM_GPU_CHANNEL_ENGINE_TYPE_SEC2), NV_ERR_NOT_SUPPORTED); + channelType = tsg->engineType; + NV_ASSERT(channelType == UVM_GPU_CHANNEL_ENGINE_TYPE_CE || channelType == UVM_GPU_CHANNEL_ENGINE_TYPE_SEC2); - status = channelAllocate(vaSpace, channelType, params, - channelHandle, channelInfo); + status = channelAllocate(tsg, params, channelHandle, channelInfo); if (status != NV_OK) return status; status = engineAllocate(*channelHandle, channelInfo, channelType); if (status != NV_OK) - nvGpuOpsChannelDestroy(*channelHandle); + goto cleanup_free_channel; + + return NV_OK; +cleanup_free_channel: + nvGpuOpsChannelDestroy(*channelHandle); + *channelHandle = NULL; return status; + } void nvGpuOpsChannelDestroy(struct gpuChannel *channel) { - struct gpuObject *nextEngine; - struct gpuObject *currEngine; NvU32 pid = osGetCurrentProcess(); struct gpuAddressSpace *vaSpace = NULL; struct gpuDevice *device = NULL; @@ -4878,26 +5025,17 @@ if (!channel) return; - vaSpace = channel->vaSpace; + NV_ASSERT(channel->tsg); + vaSpace = channel->tsg->vaSpace; NV_ASSERT(vaSpace); device = vaSpace->device; NV_ASSERT(device); session = device->session; NV_ASSERT(session); - // destroy the engines under this channel - if (channel->nextAttachedEngine) - { - currEngine = channel->nextAttachedEngine; - nextEngine = currEngine; - do - { - currEngine = nextEngine; - nextEngine = currEngine->next; - pRmApi->Free(pRmApi, session->handle, currEngine->handle); - portMemFree(currEngine); - } while (nextEngine != NULL); - } + // destroy the engine associated with the channel. + if (channel->engineHandle != NV01_NULL_OBJECT) + pRmApi->Free(pRmApi, session->handle, channel->engineHandle); // Tear down the channel if (isDevicePascalPlus(device)) @@ -4919,6 +5057,13 @@ pid); } + if (channel->bClientRegionGpuMappingNeeded) + { + NV_ASSERT(isDeviceHopperPlus(device)); + nvGpuOpsUnmapGpuMemory(vaSpace, channel->clientRegionGpuAddr); + nvGpuOpsFreeVirtual(vaSpace, channel->clientRegionGpuAddr); + } + // Free the channel pRmApi->Free(pRmApi, session->handle, channel->channelHandle); @@ -4933,6 +5078,105 @@ portMemFree(channel); } +NV_STATUS nvGpuOpsTsgAllocate(struct gpuAddressSpace *vaSpace, + const gpuTsgAllocParams *params, + struct gpuTsg **tsgHandle) +{ + NV_STATUS status; + struct gpuDevice *device = NULL; + struct gpuSession *session = NULL; + struct gpuTsg *tsg = NULL; + RM_API *pRmApi = rmapiGetInterface(RMAPI_EXTERNAL_KERNEL); + NV_CHANNEL_GROUP_ALLOCATION_PARAMETERS tsgParams = { 0 }; + UVM_GPU_CHANNEL_ENGINE_TYPE engineType; + + if (!vaSpace || !params || !tsgHandle) + return NV_ERR_INVALID_ARGUMENT; + + engineType = params->engineType; + + if (engineType != UVM_GPU_CHANNEL_ENGINE_TYPE_CE && + engineType != UVM_GPU_CHANNEL_ENGINE_TYPE_SEC2) + return NV_ERR_INVALID_ARGUMENT; + + tsg = portMemAllocNonPaged(sizeof(*tsg)); + if (tsg == NULL) + return NV_ERR_NO_MEMORY; + + portMemSet(tsg, 0, sizeof(*tsg)); + + device = vaSpace->device; + NV_ASSERT(device); + session = device->session; + NV_ASSERT(session); + + tsg->vaSpace = vaSpace; + tsg->engineType = engineType; + tsg->engineIndex = params->engineIndex; + + // TSG is supported for any engine type starting on Volta. Prior to Volta + // only GR/compute channels use TSGs. nvGpuOps only allocates channels/TSGs + // for CE and SEC2 engine types. + tsg->isFakeTsg = !isDeviceVoltaPlus(device); + tsg->tsgHandle = NV01_NULL_OBJECT; + + if (tsg->isFakeTsg) + { + *tsgHandle = tsg; + return NV_OK; + } + + tsgParams.hVASpace = vaSpace->handle; + tsgParams.engineType = gpuGetNv2080EngineType(tsgEngineType(tsg)); + + status = pRmApi->Alloc(pRmApi, + session->handle, + device->handle, + &tsg->tsgHandle, + KEPLER_CHANNEL_GROUP_A, + &tsgParams, + sizeof(tsgParams)); + if (status != NV_OK) + goto cleanup_free_tsg; + + *tsgHandle = tsg; + + return NV_OK; + +cleanup_free_tsg: + portMemFree(tsg); + + return status; +} + +void nvGpuOpsTsgDestroy(struct gpuTsg *tsg) +{ + if (!tsg) + return; + + // RM takes care of freeing its internal TSG in the channel destruction + // path. + if (!tsg->isFakeTsg) + { + struct gpuAddressSpace *vaSpace = NULL; + struct gpuDevice *device = NULL; + struct gpuSession *session = NULL; + RM_API *pRmApi = rmapiGetInterface(RMAPI_EXTERNAL_KERNEL); + + vaSpace = tsg->vaSpace; + NV_ASSERT(vaSpace); + device = vaSpace->device; + NV_ASSERT(device); + session = device->session; + NV_ASSERT(session); + + // Free the TSG + pRmApi->Free(pRmApi, session->handle, tsg->tsgHandle); + } + + portMemFree(tsg); +} + static NV_STATUS trackDescriptor(PNODE *pRoot, NvU64 key, void *desc) { PNODE btreeNode; @@ -5037,7 +5281,7 @@ NvU64 memory, NvLength length, void **cpuPtr, - NvU32 pageSize) + NvU64 pageSize) { gpuMemDesc *memDesc = NULL; cpuMappingDesc *cpuMapDesc = NULL; @@ -5222,9 +5466,7 @@ NV_STATUS status; nvGpuOpsLockSet acquiredLocks; THREAD_STATE_NODE threadState; - OBJGPU *pGpu = NULL; - KernelMemorySystem *pKernelMemorySystem; - NV0000_CTRL_GPU_GET_ID_INFO_PARAMS infoParams = {0}; + NV0000_CTRL_GPU_GET_ID_INFO_V2_PARAMS infoParams = {0}; struct gpuSession *session = device->session; RM_API *pRmApi = rmapiGetInterface(RMAPI_GPU_LOCK_INTERNAL); @@ -5236,23 +5478,15 @@ return status; } - caps->sysmemLink = device->sysmemLink; - caps->sysmemLinkRateMBps = device->sysmemLinkRateMBps; - caps->connectedToSwitch = device->connectedToSwitch; - infoParams.gpuId = device->gpuId; status = pRmApi->Control(pRmApi, session->handle, session->handle, - NV0000_CTRL_CMD_GPU_GET_ID_INFO, + NV0000_CTRL_CMD_GPU_GET_ID_INFO_V2, &infoParams, sizeof(infoParams)); if (status != NV_OK) - { - _nvGpuOpsLocksRelease(&acquiredLocks); - threadStateFree(&threadState, THREAD_STATE_FLAGS_NONE); - return status; - } + goto cleanup; if (infoParams.numaId != NV0000_CTRL_NO_NUMA_NODE) { @@ -5260,51 +5494,10 @@ caps->numaNodeId = infoParams.numaId; } - status = CliSetGpuContext(session->handle, device->handle, &pGpu, NULL); - if (status != NV_OK) - { - _nvGpuOpsLocksRelease(&acquiredLocks); - threadStateFree(&threadState, THREAD_STATE_FLAGS_NONE); - return status; - } - - pKernelMemorySystem = GPU_GET_KERNEL_MEMORY_SYSTEM(pGpu); - if (!pKernelMemorySystem) - { - _nvGpuOpsLocksRelease(&acquiredLocks); - threadStateFree(&threadState, THREAD_STATE_FLAGS_NONE); - return NV_ERR_OBJECT_NOT_FOUND; - } - - if (pGpu->getProperty(pGpu, PDB_PROP_GPU_ATS_SUPPORTED)) - { - caps->systemMemoryWindowStart = pKernelMemorySystem->coherentCpuFbBase; - caps->systemMemoryWindowSize = pKernelMemorySystem->coherentCpuFbEnd - - pKernelMemorySystem->coherentCpuFbBase; - } - else - { - caps->systemMemoryWindowStart = 0; - caps->systemMemoryWindowSize = 0; - } - - if (device->connectedToSwitch) - { - KernelNvlink *pKernelNvlink = GPU_GET_KERNEL_NVLINK(pGpu); - if (pKernelNvlink == NULL) - { - caps->nvswitchMemoryWindowStart = NVLINK_INVALID_FABRIC_ADDR; - } - else - { - caps->nvswitchMemoryWindowStart = knvlinkGetUniqueFabricBaseAddress( - pGpu, pKernelNvlink); - } - } - +cleanup: _nvGpuOpsLocksRelease(&acquiredLocks); threadStateFree(&threadState, THREAD_STATE_FLAGS_NONE); - return NV_OK; + return status; } static NV_STATUS findVaspaceFromPid(unsigned pid, unsigned gpuId, @@ -5339,8 +5532,12 @@ if (!pGpu) return NV_ERR_INVALID_ARGUMENT; - pSubDevice = CliGetSubDeviceInfoFromGpu(pRsClient->hClient, - pGpu); + status = subdeviceGetByGpu(pRsClient, pGpu, &pSubDevice); + + if (status != NV_OK) + continue; + + GPU_RES_SET_THREAD_BC_STATE(pSubDevice); status = deviceGetByGpu(pRsClient, pGpu, NV_TRUE, &pDevice); if (status == NV_OK) @@ -5474,6 +5671,211 @@ return status; } +static NV_STATUS +nvGpuOpsQueryGpuConfidentialComputeCaps(NvHandle hClient, + UvmGpuConfComputeCaps *pGpuConfComputeCaps) +{ + NV_CONFIDENTIAL_COMPUTE_ALLOC_PARAMS confComputeAllocParams = {0}; + NV_CONF_COMPUTE_CTRL_CMD_SYSTEM_GET_CAPABILITIES_PARAMS confComputeParams = {0}; + RM_API *pRmApi = rmapiGetInterface(RMAPI_EXTERNAL_KERNEL); + NvHandle hConfCompute = 0; + NV_STATUS status = NV_OK; + + confComputeAllocParams.hClient = hClient; + status = pRmApi->Alloc(pRmApi, + hClient, + hClient, + &hConfCompute, + NV_CONFIDENTIAL_COMPUTE, + &confComputeAllocParams, + sizeof(confComputeAllocParams)); + if (status == NV_ERR_INVALID_CLASS) + { + pGpuConfComputeCaps->mode = UVM_GPU_CONF_COMPUTE_MODE_NONE; + return NV_OK; + } + else + { + NV_ASSERT_OK_OR_RETURN(status); + } + + NV_ASSERT_OK_OR_GOTO(status, + pRmApi->Control(pRmApi, + hClient, + hConfCompute, + NV_CONF_COMPUTE_CTRL_CMD_SYSTEM_GET_CAPABILITIES, + &confComputeParams, + sizeof(confComputeParams)), + cleanup); + + if (confComputeParams.ccFeature == NV_CONF_COMPUTE_SYSTEM_FEATURE_APM_ENABLED) + { + pGpuConfComputeCaps->mode = UVM_GPU_CONF_COMPUTE_MODE_APM; + } + else if (confComputeParams.ccFeature == NV_CONF_COMPUTE_SYSTEM_FEATURE_HCC_ENABLED) + { + pGpuConfComputeCaps->mode = UVM_GPU_CONF_COMPUTE_MODE_HCC; + } + +cleanup: + pRmApi->Free(pRmApi, hClient, hConfCompute); + return status; +} + +static NV_STATUS getSysmemLinkInfo(NvHandle hClient, + NvHandle hSubDevice, + gpuInfo *pGpuInfo) +{ + NvU32 sysmemConnType; + NV2080_CTRL_BUS_GET_INFO_V2_PARAMS *busInfoParams; + RM_API *pRmApi = rmapiGetInterface(RMAPI_EXTERNAL_KERNEL); + NV_STATUS status; + + pGpuInfo->sysmemLink = UVM_LINK_TYPE_NONE; + + busInfoParams = portMemAllocNonPaged(sizeof(*busInfoParams)); + if (busInfoParams == NULL) + return NV_ERR_INSUFFICIENT_RESOURCES; + + portMemSet(busInfoParams, 0, sizeof(*busInfoParams)); + busInfoParams->busInfoListSize = 1; + busInfoParams->busInfoList[0].index = NV2080_CTRL_BUS_INFO_INDEX_SYSMEM_CONNECTION_TYPE; + status = pRmApi->Control(pRmApi, + hClient, + hSubDevice, + NV2080_CTRL_CMD_BUS_GET_INFO_V2, + busInfoParams, + sizeof(*busInfoParams)); + sysmemConnType = busInfoParams->busInfoList[0].data; + portMemFree(busInfoParams); + + if (status != NV_OK) + return status; + + switch (sysmemConnType) + { + case NV2080_CTRL_BUS_INFO_INDEX_SYSMEM_CONNECTION_TYPE_NVLINK: + { + NV2080_CTRL_CMD_NVLINK_GET_NVLINK_STATUS_PARAMS *nvlinkStatus; + NvU32 nvlinkVersion; + NvBool atomicSupported; + + status = allocNvlinkStatus(hClient, hSubDevice, &nvlinkStatus); + if (status != NV_OK) + return status; + + nvlinkVersion = getNvlinkConnectionToNpu(nvlinkStatus, + &atomicSupported, + &pGpuInfo->sysmemLinkRateMBps); + + pGpuInfo->sysmemLink = rmControlToUvmNvlinkVersion(nvlinkVersion); + + portMemFree(nvlinkStatus); + break; + } + case NV2080_CTRL_BUS_INFO_INDEX_SYSMEM_CONNECTION_TYPE_C2C: + { + NvBool c2cConnectedToCpu = NV_FALSE; + + status = getC2CConnectionToCpu(hClient, + hSubDevice, + &c2cConnectedToCpu, + &pGpuInfo->sysmemLinkRateMBps); + if (status != NV_OK) + return status; + + if (c2cConnectedToCpu == NV_FALSE) + { + NV_ASSERT(0); + return NV_ERR_INVALID_STATE; + } + + pGpuInfo->sysmemLink = UVM_LINK_TYPE_C2C; + break; + } + case NV2080_CTRL_BUS_INFO_INDEX_SYSMEM_CONNECTION_TYPE_PCIE: + { + pGpuInfo->sysmemLink = UVM_LINK_TYPE_PCIE; + status = getPCIELinkRateMBps(hClient, hSubDevice, &pGpuInfo->sysmemLinkRateMBps); + if (status != NV_OK) + return status; + break; + } + default: + { + NV_PRINTF(LEVEL_ERROR, "Unsupported sysmem connection type: %d\n", + sysmemConnType); + break; + } + } + + NV_PRINTF(LEVEL_INFO, "sysmem link type: %d bw: %u\n", pGpuInfo->sysmemLink, pGpuInfo->sysmemLinkRateMBps); + NV_ASSERT(pGpuInfo->sysmemLink != UVM_LINK_TYPE_NONE); + return NV_OK; +} + +static NV_STATUS getSystemMemoryWindow(OBJGPU *pGpu, gpuInfo *pGpuInfo) +{ + KernelMemorySystem *pKernelMemorySystem = GPU_GET_KERNEL_MEMORY_SYSTEM(pGpu); + + if (!pKernelMemorySystem) + return NV_ERR_OBJECT_NOT_FOUND; + + if (pGpu->getProperty(pGpu, PDB_PROP_GPU_ATS_SUPPORTED)) + { + pGpuInfo->systemMemoryWindowStart = pKernelMemorySystem->coherentCpuFbBase; + pGpuInfo->systemMemoryWindowSize = pKernelMemorySystem->coherentCpuFbEnd - + pKernelMemorySystem->coherentCpuFbBase; + } + else + { + pGpuInfo->systemMemoryWindowStart = 0; + pGpuInfo->systemMemoryWindowSize = 0; + } + + return NV_OK; +} + +static NV_STATUS getNvswitchInfo(OBJGPU *pGpu, + NvHandle hClient, + NvHandle hSubDevice, + gpuInfo *pGpuInfo) +{ + NV2080_CTRL_CMD_NVLINK_GET_NVLINK_STATUS_PARAMS *nvlinkStatus; + NvU32 nvlinkVersion; + NvU32 linkBandwidthMBps; + NV_STATUS status; + + pGpuInfo->connectedToSwitch = NV_FALSE; + + status = allocNvlinkStatus(hClient, hSubDevice, &nvlinkStatus); + if (status != NV_OK) + return status; + + nvlinkVersion = getNvlinkConnectionToSwitch(nvlinkStatus, &linkBandwidthMBps); + + if (rmControlToUvmNvlinkVersion(nvlinkVersion) != UVM_LINK_TYPE_NONE) + { + KernelNvlink *pKernelNvlink = GPU_GET_KERNEL_NVLINK(pGpu); + + NV_ASSERT(rmControlToUvmNvlinkVersion(nvlinkVersion) != UVM_LINK_TYPE_NVLINK_1); + pGpuInfo->connectedToSwitch = NV_TRUE; + + if (pKernelNvlink == NULL) + { + pGpuInfo->nvswitchMemoryWindowStart = NVLINK_INVALID_FABRIC_ADDR; + } + else + { + pGpuInfo->nvswitchMemoryWindowStart = knvlinkGetUniqueFabricBaseAddress(pGpu, pKernelNvlink); + } + } + + portMemFree(nvlinkStatus); + + return NV_OK; +} + NV_STATUS nvGpuOpsGetGpuInfo(const NvProcessorUuid *pUuid, const gpuClientInfo *pGpuClientInfo, gpuInfo *pGpuInfo) @@ -5536,7 +5938,8 @@ clientHandle, &deviceHandle, NV01_DEVICE_0, - &nv0080AllocParams); + &nv0080AllocParams, + sizeof(nv0080AllocParams)); if (NV_OK != status) goto cleanup; @@ -5548,7 +5951,8 @@ deviceHandle, &subDeviceHandle, NV20_SUBDEVICE_0, - &nv2080AllocParams); + &nv2080AllocParams, + sizeof(nv2080AllocParams)); if (NV_OK != status) goto cleanup; @@ -5645,6 +6049,24 @@ pGpuInfo->isSimulated = (simulationInfoParams.type != NV2080_CTRL_GPU_GET_SIMULATION_INFO_TYPE_NONE); + portMemSet(&pGpuInfo->gpuConfComputeCaps, 0, sizeof(pGpuInfo->gpuConfComputeCaps)); + + status = nvGpuOpsQueryGpuConfidentialComputeCaps(clientHandle, &pGpuInfo->gpuConfComputeCaps); + if (status != NV_OK) + goto cleanup; + + status = getSysmemLinkInfo(clientHandle, subDeviceHandle, pGpuInfo); + if (status != NV_OK) + goto cleanup; + + status = getSystemMemoryWindow(pGpu, pGpuInfo); + if (status != NV_OK) + goto cleanup; + + status = getNvswitchInfo(pGpu, clientHandle, subDeviceHandle, pGpuInfo); + if (status != NV_OK) + goto cleanup; + cleanup: if (isSubdeviceAllocated) pRmApi->Free(pRmApi, clientHandle, subDeviceHandle); @@ -5754,7 +6176,7 @@ threadStateInit(&threadState, THREAD_STATE_FLAGS_NONE); status = _nvGpuOpsLocksAcquireAll(RMAPI_LOCK_FLAGS_READ, - channel->vaSpace->device->session->handle, + channel->tsg->vaSpace->device->session->handle, NULL, &acquiredLocks); if (status != NV_OK) @@ -5766,13 +6188,13 @@ *bEccDbeSet = NV_FALSE; // Do anything only if ECC is enabled on this device - if (channel->vaSpace->device->rmSubDevice->bEccEnabled) + if (channel->tsg->vaSpace->device->rmSubDevice->bEccEnabled) { portMemSet(&eccStatus, 0, sizeof(eccStatus)); status = pRmApi->Control(pRmApi, - channel->vaSpace->device->session->handle, - channel->vaSpace->device->subhandle, + channel->tsg->vaSpace->device->session->handle, + channel->tsg->vaSpace->device->subhandle, NV2080_CTRL_CMD_GPU_QUERY_ECC_STATUS, &eccStatus, sizeof(eccStatus)); @@ -5854,7 +6276,8 @@ static NvBool memdescIsSysmem(PMEMORY_DESCRIPTOR pMemDesc) { - return memdescGetAddressSpace(pMemDesc) == ADDR_SYSMEM; + return (memdescGetAddressSpace(pMemDesc) == ADDR_SYSMEM) && + !(memdescGetFlag(pMemDesc, MEMDESC_FLAGS_MAP_SYSCOH_OVER_BAR1)); } static NV_STATUS dupMemory(struct gpuDevice *device, @@ -5874,11 +6297,12 @@ FABRIC_VASPACE *pFabricVAS = NULL; OBJGPU *pMappingGpu; RM_API *pRmApi = rmapiGetInterface(RMAPI_GPU_LOCK_INTERNAL); + RsClient *pSessionClient; RsResourceRef *pResourceRef; RsResourceRef *pParentRef; + Subdevice *pSubdevice; struct gpuSession *session; NvHandle hParent; - NvHandle hSubDevice; NvBool bIsIndirectPeer = NV_FALSE; if (!device || !hDupMemory) @@ -5889,21 +6313,22 @@ threadStateInit(&threadState, THREAD_STATE_FLAGS_NONE); // RS-TODO use dual client locking - status = _nvGpuOpsLocksAcquireAll(RMAPI_LOCK_FLAGS_NONE, NV01_NULL_OBJECT, NULL, &acquiredLocks); + status = _nvGpuOpsLocksAcquireAll(RMAPI_LOCK_FLAGS_NONE, device->session->handle, + &pSessionClient, &acquiredLocks); if (status != NV_OK) { threadStateFree(&threadState, THREAD_STATE_FLAGS_NONE); return status; } - status = CliSetSubDeviceContext(device->session->handle, - device->subhandle, - &hSubDevice, - &pMappingGpu); - + status = subdeviceGetByHandle(pSessionClient, device->subhandle, &pSubdevice); if (status != NV_OK) goto done; + pMappingGpu = GPU_RES_GET_GPU(pSubdevice); + + GPU_RES_SET_THREAD_BC_STATE(pSubdevice); + // Get all the necessary information about the memory status = nvGpuOpsGetMemoryByHandle(hClient, hPhysMemory, @@ -6299,7 +6724,8 @@ { switch (class) { - + case HOPPER_SEC2_WORK_LAUNCH_A: + return NV_TRUE; default: return NV_FALSE; } @@ -6813,8 +7239,9 @@ Memory *pMemory = NULL; OBJGPU *pMappingGpu = NULL; RM_API *pRmApi = rmapiGetInterface(RMAPI_GPU_LOCK_INTERNAL); + RsClient *pClient; + Subdevice *pSubdevice; NvHandle hClient; - NvHandle hSubDevice; if (!device) return NV_ERR_INVALID_ARGUMENT; @@ -6822,20 +7249,21 @@ hClient = device->session->handle; threadStateInit(&threadState, THREAD_STATE_FLAGS_NONE); - status = _nvGpuOpsLocksAcquire(RMAPI_LOCK_FLAGS_READ, hClient, NULL, 0, 0, 0, &acquiredLocks); + status = _nvGpuOpsLocksAcquire(RMAPI_LOCK_FLAGS_READ, hClient, &pClient, 0, 0, 0, &acquiredLocks); if (status != NV_OK) { threadStateFree(&threadState, THREAD_STATE_FLAGS_NONE); return status; } - status = CliSetSubDeviceContext(device->session->handle, - device->subhandle, - &hSubDevice, - &pMappingGpu); + status = subdeviceGetByHandle(pClient, device->subhandle, &pSubdevice); if (status != NV_OK) goto out; + pMappingGpu = GPU_RES_GET_GPU(pSubdevice); + + GPU_RES_SET_THREAD_BC_STATE(pSubdevice); + status = nvGpuOpsGetMemoryByHandle(device->session->handle, hPhysHandle, &pMemory); @@ -6865,8 +7293,24 @@ NVB069_ALLOCATION_PARAMETERS faultBufferAllocParams = {0}; NVB069_CTRL_FAULTBUFFER_GET_SIZE_PARAMS sizeParams = {0}; NVB069_CTRL_CMD_FAULTBUFFER_GET_REGISTER_MAPPINGS_PARAMS registermappingsParams = {0}; - void *bufferAddress; + void *bufferAddress = NULL; + NvU32 faultBufferSize = 0; RM_API *pRmApi = rmapiGetInterface(RMAPI_EXTERNAL_KERNEL); + RsClient *pClient; + Device *pDevice; + NvHandle hClient = device->session->handle; + NvHandle hDevice = device->handle; + UvmFaultMetadataPacket *bufferMetadata = NULL; + + status = serverGetClientUnderLock(&g_resServ, hClient, &pClient); + if (status != NV_OK) + return status; + + status = deviceGetByHandle(pClient, hDevice, &pDevice); + if (status != NV_OK) + return status; + + pFaultInfo->pDevice = pDevice; pFaultInfo->faultBufferHandle = NV01_NULL_OBJECT; status = pRmApi->Alloc(pRmApi, @@ -6874,40 +7318,47 @@ device->subhandle, &pFaultInfo->faultBufferHandle, device->faultBufferClass, - &faultBufferAllocParams); + &faultBufferAllocParams, + sizeof(faultBufferAllocParams)); if (status != NV_OK) goto cleanup; - // Get the Size of the fault buffer - status = pRmApi->Control(pRmApi, - session->handle, - pFaultInfo->faultBufferHandle, - NVB069_CTRL_CMD_FAULTBUFFER_GET_SIZE, - &sizeParams, - sizeof(sizeParams)); - if (status != NV_OK) - goto cleanup_fault_buffer; - // Map the fault buffer pointer to CPU - status = pRmApi->MapToCpu(pRmApi, - session->handle, - device->subhandle, - pFaultInfo->faultBufferHandle, - 0, - pFaultInfo->replayable.bufferSize, - &bufferAddress, - 0); - if (status != NV_OK) - goto cleanup_fault_buffer; + OBJGPU *pGpu; - status = pRmApi->Control(pRmApi, - session->handle, - pFaultInfo->faultBufferHandle, - NVB069_CTRL_CMD_FAULTBUFFER_GET_REGISTER_MAPPINGS, - ®istermappingsParams, - sizeof(registermappingsParams)); - if (status != NV_OK) - goto cleanup_fault_buffer; + pGpu = GPU_RES_GET_GPU(pDevice); + // + // When Hopper CC is enabled, UVM won't have direct access to the replayable + // HW fault buffer. Instead, it will be using a shadow fault buffer in + // unprotected sysmem and GSP-RM will be copying encrypted fault packets from the + // HW fault buffer to this shadow buffer + // + if (!gpuIsCCFeatureEnabled(pGpu) || !gpuIsGspOwnedFaultBuffersEnabled(pGpu)) + { + // Get the Size of the fault buffer + status = pRmApi->Control(pRmApi, + session->handle, + pFaultInfo->faultBufferHandle, + NVB069_CTRL_CMD_FAULTBUFFER_GET_SIZE, + &sizeParams, + sizeof(sizeParams)); + if (status != NV_OK) + goto cleanup_fault_buffer; + + faultBufferSize = sizeParams.faultBufferSize; + + // Map the fault buffer pointer to CPU + status = pRmApi->MapToCpu(pRmApi, + session->handle, + device->subhandle, + pFaultInfo->faultBufferHandle, + 0, + pFaultInfo->replayable.bufferSize, + &bufferAddress, + 0); + if (status != NV_OK) + goto cleanup_fault_buffer; + } if (isDeviceVoltaPlus(device)) { @@ -6925,8 +7376,56 @@ pFaultInfo->nonReplayable.shadowBufferAddress = (void *)NvP64_VALUE(nonReplayableFaultsParams.pShadowBuffer); pFaultInfo->nonReplayable.shadowBufferContext = (void *)NvP64_VALUE(nonReplayableFaultsParams.pShadowBufferContext); pFaultInfo->nonReplayable.bufferSize = nonReplayableFaultsParams.bufferSize; + pFaultInfo->nonReplayable.shadowBufferMetadata = (UvmFaultMetadataPacket *)NvP64_VALUE(nonReplayableFaultsParams.pShadowBufferMetadata); } + if (gpuIsCCFeatureEnabled(pGpu) && gpuIsGspOwnedFaultBuffersEnabled(pGpu)) + { + NVC369_CTRL_MMU_FAULT_BUFFER_REGISTER_REPLAY_BUF_PARAMS replayableFaultsParams = {0}; + + // Allocate a shadow buffer for replayable faults in case Hopper CC is enabled + status = pRmApi->Control(pRmApi, + session->handle, + pFaultInfo->faultBufferHandle, + NVC369_CTRL_CMD_MMU_FAULT_BUFFER_REGISTER_REPLAY_BUF, + &replayableFaultsParams, + sizeof(replayableFaultsParams)); + if (status != NV_OK) + goto cleanup_fault_buffer; + + bufferAddress = (void *)NvP64_VALUE(replayableFaultsParams.pShadowBuffer); + faultBufferSize = replayableFaultsParams.bufferSize; + + // Make sure that the UVM and RM sizes of the metadata packet are equal. + ct_assert(sizeof(GMMU_FAULT_PACKET_METADATA) == sizeof(UvmFaultMetadataPacket)); + bufferMetadata = (UvmFaultMetadataPacket *)NvP64_VALUE(replayableFaultsParams.pShadowBufferMetadata); + + // Get the register mappings for non-replayable fault buffer + portMemSet(®istermappingsParams, 0, sizeof(registermappingsParams)); + + registermappingsParams.faultBufferType = NVB069_CTRL_FAULT_BUFFER_NON_REPLAYABLE; + status = pRmApi->Control(pRmApi, + session->handle, + pFaultInfo->faultBufferHandle, + NVB069_CTRL_CMD_FAULTBUFFER_GET_REGISTER_MAPPINGS, + ®istermappingsParams, + sizeof(registermappingsParams)); + if (status != NV_OK) + goto cleanup_fault_buffer; + + pFaultInfo->nonReplayable.pFaultBufferPut = (NvU32*)(NvUPtr)registermappingsParams.pFaultBufferPut; + } + + registermappingsParams.faultBufferType = NVB069_CTRL_FAULT_BUFFER_REPLAYABLE; + status = pRmApi->Control(pRmApi, + session->handle, + pFaultInfo->faultBufferHandle, + NVB069_CTRL_CMD_FAULTBUFFER_GET_REGISTER_MAPPINGS, + ®istermappingsParams, + sizeof(registermappingsParams)); + if (status != NV_OK) + goto cleanup_fault_buffer; + pFaultInfo->replayable.pFaultBufferGet = (NvU32*)(NvUPtr)registermappingsParams.pFaultBufferGet; pFaultInfo->replayable.pFaultBufferPut = (NvU32*)(NvUPtr)registermappingsParams.pFaultBufferPut; pFaultInfo->replayable.pFaultBufferInfo = (NvU32*)(NvUPtr)registermappingsParams.pFaultBufferInfo; @@ -6935,31 +7434,52 @@ pFaultInfo->replayable.pPmcIntrEnClear = (NvU32*)(NvUPtr)registermappingsParams.pPmcIntrEnClear; pFaultInfo->replayable.replayableFaultMask = registermappingsParams.replayableFaultMask; pFaultInfo->replayable.pPrefetchCtrl = (NvU32*)(NvUPtr)registermappingsParams.pPrefetchCtrl; - pFaultInfo->replayable.bufferSize = sizeParams.faultBufferSize; + pFaultInfo->replayable.bufferSize = faultBufferSize; pFaultInfo->replayable.bufferAddress = bufferAddress; + pFaultInfo->replayable.bufferMetadata = bufferMetadata; + + if (gpuIsCCFeatureEnabled(pGpu) && gpuIsGspOwnedFaultBuffersEnabled(pGpu)) + { + KernelGmmu *pKernelGmmu = GPU_GET_KERNEL_GMMU(pGpu); + + pFaultInfo->replayable.bUvmOwnsHwFaultBuffer = NV_FALSE; + pFaultInfo->replayable.cslCtx.ctx = (struct ccslContext_t *) kgmmuGetShadowFaultBufferCslContext(pGpu, pKernelGmmu, REPLAYABLE_FAULT_BUFFER); + if (pFaultInfo->replayable.cslCtx.ctx == NULL) + { + NV_PRINTF(LEVEL_ERROR, "Replayable buffer CSL context not allocated\n"); + goto cleanup_fault_buffer; + } + } + else + { + pFaultInfo->replayable.bUvmOwnsHwFaultBuffer = NV_TRUE; + } return NV_OK; cleanup_fault_buffer: - gpuDeviceUnmapCpuFreeHandle(device, - pFaultInfo->faultBufferHandle, - pFaultInfo->replayable.bufferAddress, - 0); + if (!gpuIsCCFeatureEnabled(pGpu) || !gpuIsGspOwnedFaultBuffersEnabled(pGpu)) + { + gpuDeviceUnmapCpuFreeHandle(device, + pFaultInfo->faultBufferHandle, + pFaultInfo->replayable.bufferAddress, + 0); + } cleanup: portMemSet(pFaultInfo, 0, sizeof(*pFaultInfo)); return status; } NV_STATUS nvGpuOpsInitAccessCntrInfo(struct gpuDevice *device, - gpuAccessCntrInfo *pAccessCntrInfo) + gpuAccessCntrInfo *pAccessCntrInfo, + NvU32 accessCntrIndex) { struct gpuSession *session = device->session; NV_STATUS status = NV_OK; - NvU32 accessCntrBufferAllocParams = {0}; + NV_ACCESS_COUNTER_NOTIFY_BUFFER_ALLOC_PARAMS accessCntrBufferAllocParams = {0}; NVC365_CTRL_ACCESS_CNTR_BUFFER_GET_SIZE_PARAMS sizeParams = {0}; NVC365_CTRL_ACCESS_CNTR_BUFFER_GET_REGISTER_MAPPINGS_PARAMS registermappings; void *bufferAddress; - NV0080_CTRL_BIF_GET_DMA_BASE_SYSMEM_ADDR_PARAMS getDmaBaseSysmemAddrParams = {0}; RM_API *pRmApi = rmapiGetInterface(RMAPI_EXTERNAL_KERNEL); OBJGPU *pGpu = NULL; @@ -6972,13 +7492,15 @@ if (status != NV_OK) return status; + accessCntrBufferAllocParams.accessCounterIndex = accessCntrIndex; pAccessCntrInfo->accessCntrBufferHandle = NV01_NULL_OBJECT; status = pRmApi->Alloc(pRmApi, session->handle, device->subhandle, &pAccessCntrInfo->accessCntrBufferHandle, device->accessCounterBufferClass, - &accessCntrBufferAllocParams); + &accessCntrBufferAllocParams, + sizeof(accessCntrBufferAllocParams)); if (status != NV_OK) goto cleanup; @@ -7012,15 +7534,6 @@ if (status != NV_OK) goto cleanup_access_ctr_buffer; - status = pRmApi->Control(pRmApi, - session->handle, - device->handle, - NV0080_CTRL_CMD_BIF_GET_DMA_BASE_SYSMEM_ADDR, - &getDmaBaseSysmemAddrParams, - sizeof(getDmaBaseSysmemAddrParams)); - if (status != NV_OK) - goto cleanup_access_ctr_buffer; - pAccessCntrInfo->pAccessCntrBufferGet = (NvU32*)(NvUPtr)registermappings.pAccessCntrBufferGet; pAccessCntrInfo->pAccessCntrBufferPut = (NvU32*)(NvUPtr)registermappings.pAccessCntrBufferPut; pAccessCntrInfo->pAccessCntrBufferFull = (NvU32*)(NvUPtr)registermappings.pAccessCntrBufferFull; @@ -7028,7 +7541,6 @@ pAccessCntrInfo->pHubIntrEnSet = (NvU32*)(NvUPtr)registermappings.pHubIntrEnSet; pAccessCntrInfo->pHubIntrEnClear = (NvU32*)(NvUPtr)registermappings.pHubIntrEnClear; pAccessCntrInfo->accessCounterMask = registermappings.accessCntrMask; - pAccessCntrInfo->baseDmaSysmemAddr = getDmaBaseSysmemAddrParams.baseDmaSysmemAddr; return NV_OK; @@ -7182,6 +7694,14 @@ NV_STATUS status = NV_OK; RM_API *pRmApi = rmapiGetInterface(RMAPI_EXTERNAL_KERNEL); + OBJGPU *pGpu; + + status = rmapiLockAcquire(RMAPI_LOCK_FLAGS_READ, RM_LOCK_MODULES_GPU_OPS); + NV_ASSERT(status == NV_OK); + status = CliSetGpuContext(device->session->handle, device->handle, &pGpu, NULL); + NV_ASSERT(status == NV_OK); + rmapiLockRelease(); + if (pFaultInfo->faultBufferHandle && isDeviceVoltaPlus(device)) { NVC369_CTRL_MMU_FAULT_BUFFER_UNREGISTER_NON_REPLAY_BUF_PARAMS params = {0}; @@ -7197,10 +7717,27 @@ NV_ASSERT(status == NV_OK); } - gpuDeviceUnmapCpuFreeHandle(device, - pFaultInfo->faultBufferHandle, - pFaultInfo->replayable.bufferAddress, - 0); + if (pFaultInfo->faultBufferHandle && gpuIsCCFeatureEnabled(pGpu) && gpuIsGspOwnedFaultBuffersEnabled(pGpu)) + { + NVC369_CTRL_MMU_FAULT_BUFFER_UNREGISTER_REPLAY_BUF_PARAMS params = {0}; + + params.pShadowBuffer = NV_PTR_TO_NvP64(pFaultInfo->replayable.bufferAddress); + + status = pRmApi->Control(pRmApi, + device->session->handle, + pFaultInfo->faultBufferHandle, + NVC369_CTRL_CMD_MMU_FAULT_BUFFER_UNREGISTER_REPLAY_BUF, + ¶ms, + sizeof(params)); + NV_ASSERT(status == NV_OK); + } + else + { + gpuDeviceUnmapCpuFreeHandle(device, + pFaultInfo->faultBufferHandle, + pFaultInfo->replayable.bufferAddress, + 0); + } portMemSet(pFaultInfo, 0, sizeof(gpuFaultInfo)); return status; @@ -7209,72 +7746,214 @@ NV_STATUS nvGpuOpsHasPendingNonReplayableFaults(gpuFaultInfo *pFaultInfo, NvBool *hasPendingFaults) { - GMMU_SHADOW_FAULT_BUF *pQueue = - (GMMU_SHADOW_FAULT_BUF *) pFaultInfo->nonReplayable.shadowBufferAddress; + NV_STATUS status = NV_OK; - if (!pQueue || !hasPendingFaults) + if (hasPendingFaults == NULL) return NV_ERR_INVALID_ARGUMENT; - *hasPendingFaults = !queueIsEmpty(pQueue); + if (pFaultInfo->pDevice == NULL) + return NV_ERR_INVALID_ARGUMENT; - return NV_OK; + OBJGPU *pGpu; + + pGpu = GPU_RES_GET_GPU(pFaultInfo->pDevice); + + // + // In case of GSP owned HW fault buffers, CPU-RM maintains the get pointer. + // The PUT pointer is updated by GSP in a PRI and CPU-RM just reads the same. + // GET != PUT implies pending faults in the shadow buffer + // + if (gpuIsCCFeatureEnabled(pGpu) && gpuIsGspOwnedFaultBuffersEnabled(pGpu)) + { + KernelGmmu *pKernelGmmu = GPU_GET_KERNEL_GMMU(pGpu); + + *hasPendingFaults = (pFaultInfo->nonReplayable.shadowBufferGet != + kgmmuReadShadowBufPutIndex_HAL(pGpu, + pKernelGmmu, + NON_REPLAYABLE_FAULT_BUFFER)); + + } + else + { + GMMU_SHADOW_FAULT_BUF *pQueue = + (GMMU_SHADOW_FAULT_BUF *) pFaultInfo->nonReplayable.shadowBufferAddress; + + if (pQueue == NULL) + return NV_ERR_INVALID_ARGUMENT; + + *hasPendingFaults = !queueIsEmpty(pQueue); + } + + return status; } NV_STATUS nvGpuOpsGetNonReplayableFaults(gpuFaultInfo *pFaultInfo, void *faultBuffer, NvU32 *numFaults) { - GMMU_SHADOW_FAULT_BUF *pQueue = - (GMMU_SHADOW_FAULT_BUF *) pFaultInfo->nonReplayable.shadowBufferAddress; - QueueContext *pQueueCtx = - (QueueContext *) pFaultInfo->nonReplayable.shadowBufferContext; + NV_STATUS status = NV_OK; - if (!pQueue || !faultBuffer || !numFaults) + if (faultBuffer == NULL || numFaults == NULL) + return NV_ERR_INVALID_ARGUMENT; + + if (pFaultInfo->pDevice == NULL) return NV_ERR_INVALID_ARGUMENT; *numFaults = 0; - // Copy all faults in the client shadow fault buffer to the given buffer - while (queuePopAndCopyNonManaged(pQueue, pQueueCtx, faultBuffer)) + OBJGPU *pGpu; + + pGpu = GPU_RES_GET_GPU(pFaultInfo->pDevice); + + if (gpuIsCCFeatureEnabled(pGpu) && gpuIsGspOwnedFaultBuffersEnabled(pGpu)) { - ++(*numFaults); - faultBuffer = (char *)faultBuffer + NVC369_BUF_SIZE; + KernelGmmu *pKernelGmmu = GPU_GET_KERNEL_GMMU(pGpu); + NvU32 shadowBufferPutIndex; + NvU32 shadowBufferGetIndex; + NvU32 maxFaultBufferEntries; + struct ccslContext_t *cslCtx; + + cslCtx = (struct ccslContext_t *) kgmmuGetShadowFaultBufferCslContext(pGpu, pKernelGmmu, NON_REPLAYABLE_FAULT_BUFFER); + if (cslCtx == NULL) + { + NV_PRINTF(LEVEL_ERROR, "Non Replayable buffer CSL context not allocated\n"); + return NV_ERR_INVALID_STATE; + } + + maxFaultBufferEntries = pFaultInfo->nonReplayable.bufferSize / NVC369_BUF_SIZE; + shadowBufferGetIndex = pFaultInfo->nonReplayable.shadowBufferGet; + shadowBufferPutIndex = kgmmuReadShadowBufPutIndex_HAL(pGpu, + pKernelGmmu, + NON_REPLAYABLE_FAULT_BUFFER); + // Copy the fault packets as long as GET != PUT + while (shadowBufferGetIndex != shadowBufferPutIndex) + { + UvmFaultMetadataPacket metadata; + NvU8 *pShadowBuffer = (NvU8 *)pFaultInfo->nonReplayable.shadowBufferAddress; + UvmFaultMetadataPacket *pShadowBufferMetadata = pFaultInfo->nonReplayable.shadowBufferMetadata; + + ++(*numFaults); + + portMemCopy(&metadata, sizeof(UvmFaultMetadataPacket), + pShadowBufferMetadata + shadowBufferGetIndex, + sizeof(UvmFaultMetadataPacket)); + + // Sanity check valid bit is present, even though Non-Replayable handling relies on the PRI values. + if (metadata.valid != GMMU_FAULT_PACKET_METADATA_VALID_YES) + { + return NV_ERR_INVALID_STATE; + } + + // + // A read memory barrier here ensures that the valid bit check is performed before a decryption is attempted. + // This is needed for architectures like PowerPC and ARM where read instructions can be reordered. + // + portAtomicMemoryFenceLoad(); + + status = ccslDecrypt(cslCtx, + sizeof(GMMU_FAULT_PACKET), + pShadowBuffer + (shadowBufferGetIndex * NVC369_BUF_SIZE), + NULL, + &metadata.valid, + sizeof(metadata.valid), + faultBuffer, + metadata.authTag); + if (status != NV_OK) + { + NV_PRINTF(LEVEL_ERROR, "Fault buffer packet decryption failed with status = 0x%x\n", status); + return status; + } + + // Clear the plaintext valid bit and authTag. + portMemSet(pShadowBufferMetadata + shadowBufferGetIndex, + 0x0, + sizeof(UvmFaultMetadataPacket)); + + shadowBufferGetIndex = (shadowBufferGetIndex + 1) % maxFaultBufferEntries; + faultBuffer = (NvU8 *)faultBuffer + NVC369_BUF_SIZE; + } + // Update the GET pointer + pFaultInfo->nonReplayable.shadowBufferGet = shadowBufferGetIndex; } + else + { + GMMU_SHADOW_FAULT_BUF *pQueue = + (GMMU_SHADOW_FAULT_BUF *) pFaultInfo->nonReplayable.shadowBufferAddress; + QueueContext *pQueueCtx = + (QueueContext *) pFaultInfo->nonReplayable.shadowBufferContext; - return NV_OK; + if (pQueue == NULL) + return NV_ERR_INVALID_ARGUMENT; + + // Copy all faults in the client shadow fault buffer to the given buffer + while (queuePopAndCopyNonManaged(pQueue, pQueueCtx, faultBuffer)) + { + ++(*numFaults); + faultBuffer = (char *)faultBuffer + NVC369_BUF_SIZE; + } + } + + return status; +} + +NV_STATUS nvGpuOpsFlushReplayableFaultBuffer(struct gpuDevice *device) +{ + NV_STATUS status; + NvHandle hClient = device->session->handle; + RsClient *pClient; + Device *pDevice; + OBJGPU *pGpu; + KernelGmmu *pKernelGmmu; + + status = serverGetClientUnderLock(&g_resServ, hClient, &pClient); + if (status != NV_OK) + return NV_ERR_INVALID_ARGUMENT; + + status = deviceGetByHandle(pClient, device->handle, &pDevice); + if (status != NV_OK) + return NV_ERR_INVALID_ARGUMENT; + + GPU_RES_SET_THREAD_BC_STATE(pDevice); + + pGpu = GPU_RES_GET_GPU(pDevice); + pKernelGmmu = GPU_GET_KERNEL_GMMU(pGpu); + + return kgmmuIssueReplayableFaultBufferFlush_HAL(pGpu, pKernelGmmu); } static NV_STATUS nvGpuOpsVerifyChannel(struct gpuAddressSpace *vaSpace, - NvHandle hClient, + RsClient *pClient, NvHandle hKernelChannel, OBJGPU **pGpu, KernelChannel **ppKernelChannel) { NV_STATUS status = NV_OK; - NvHandle hDevice, hSubDevice; + NvHandle hDevice; OBJVASPACE *pVAS = NULL; OBJGPU *pVaSpaceGpu; - RsClient *pClient; + RsClient *pSessionClient; + Subdevice *pSubdevice; NV_ASSERT_OR_RETURN(ppKernelChannel != NULL, NV_ERR_INVALID_ARGUMENT); - status = serverGetClientUnderLock(&g_resServ, vaSpace->device->session->handle, &pClient); + status = serverGetClientUnderLock(&g_resServ, vaSpace->device->session->handle, + &pSessionClient); if (status != NV_OK) return status; - status = vaspaceGetByHandleOrDeviceDefault(pClient, + status = vaspaceGetByHandleOrDeviceDefault(pSessionClient, vaSpace->device->handle, vaSpace->handle, &pVAS); if (status != NV_OK) return status; - status = CliGetKernelChannel(hClient, hKernelChannel, ppKernelChannel); + status = CliGetKernelChannel(pClient, hKernelChannel, ppKernelChannel); if (status != NV_OK) return NV_ERR_INVALID_OBJECT_HANDLE; hDevice = RES_GET_HANDLE(GPU_RES_GET_DEVICE(*ppKernelChannel)); - status = CliSetGpuContext(hClient, hDevice, pGpu, NULL); + status = CliSetGpuContext(pClient->hClient, hDevice, pGpu, NULL); if (status != NV_OK) return status; @@ -7291,13 +7970,15 @@ // In SLI config, RM's internal allocations such as channel instance // are tracked with a memdesc per subdevice. Hence, Get the correct pGpu. - status = CliSetSubDeviceContext(vaSpace->device->session->handle, - vaSpace->device->subhandle, - &hSubDevice, - pGpu); + status = subdeviceGetByHandle(pSessionClient, vaSpace->device->subhandle, + &pSubdevice); if (status != NV_OK) return status; + *pGpu = GPU_RES_GET_GPU(pSubdevice); + + GPU_RES_SET_THREAD_BC_STATE(pSubdevice); + return NV_OK; } @@ -7598,6 +8279,7 @@ { nvGpuOpsLockSet acquiredLocks; THREAD_STATE_NODE threadState; + RsClient *pClient; KernelChannel *pKernelChannel = NULL; OBJGPU *pGpu = NULL; gpuRetainedChannel *channel = NULL; @@ -7615,7 +8297,7 @@ threadStateInit(&threadState, THREAD_STATE_FLAGS_NONE); status = _nvGpuOpsLocksAcquireAll(RMAPI_LOCK_FLAGS_READ, hClient, - NULL, + &pClient, &acquiredLocks); if (status != NV_OK) { @@ -7626,7 +8308,7 @@ device = vaSpace->device; rmSubDevice = device->rmSubDevice; - status = nvGpuOpsVerifyChannel(vaSpace, hClient, hKernelChannel, &pGpu, + status = nvGpuOpsVerifyChannel(vaSpace, pClient, hKernelChannel, &pGpu, &pKernelChannel); if (status != NV_OK) { @@ -7696,7 +8378,8 @@ hChannelParent, &channel->hChannelRetainer, UVM_CHANNEL_RETAINER, - &channelRetainerParams); + &channelRetainerParams, + sizeof(channelRetainerParams)); if (status != NV_OK) goto error; @@ -7921,7 +8604,7 @@ MEMORY_DESCRIPTOR **ppMemDesc) { NvU32 j; - NvU32 pageSize = pCtxBufferInfo->pageSize; + NvU64 pageSize = pCtxBufferInfo->pageSize; NvU32 numBufferPages = NV_ROUNDUP(pCtxBufferInfo->size, pageSize) / pageSize; MEMORY_DESCRIPTOR *pMemDesc = NULL; MEMORY_DESCRIPTOR *pBufferHandle = (MEMORY_DESCRIPTOR *) pCtxBufferInfo->bufferHandle; @@ -8208,19 +8891,24 @@ NV_STATUS status = NV_OK; nvGpuOpsLockSet acquiredLocks; THREAD_STATE_NODE threadState; - NvHandle hSubDevice; PMEMORY_DESCRIPTOR pMemDesc = NULL; OBJGPU *pMappingGpu = NULL; OBJVASPACE *pVAS = NULL; RsClient *pClient; + Subdevice *pSubDevice; if (!vaSpace || !resourceDescriptor || !pGpuExternalMappingInfo) return NV_ERR_INVALID_ARGUMENT; + if (pGpuExternalMappingInfo->mappingPageSize != 0) + { + return NV_ERR_NOT_SUPPORTED; + } + threadStateInit(&threadState, THREAD_STATE_FLAGS_NONE); status = _nvGpuOpsLocksAcquireAll(RMAPI_LOCK_FLAGS_READ, vaSpace->device->session->handle, - NULL, + &pClient, &acquiredLocks); if (status != NV_OK) { @@ -8230,10 +8918,7 @@ pMemDesc = (MEMORY_DESCRIPTOR *) NvP64_VALUE(resourceDescriptor); - status = CliSetSubDeviceContext(vaSpace->device->session->handle, - vaSpace->device->subhandle, - &hSubDevice, - &pMappingGpu); + status = subdeviceGetByHandle(pClient, vaSpace->device->subhandle, &pSubDevice); if (status != NV_OK) { _nvGpuOpsLocksRelease(&acquiredLocks); @@ -8241,6 +8926,10 @@ return status; } + pMappingGpu = GPU_RES_GET_GPU(pSubDevice); + + GPU_RES_SET_THREAD_BC_STATE(pSubDevice); + if (pMemDesc->pGpu != pMappingGpu) { _nvGpuOpsLocksRelease(&acquiredLocks); @@ -8257,14 +8946,6 @@ return NV_ERR_NOT_SUPPORTED; } - status = serverGetClientUnderLock(&g_resServ, vaSpace->device->session->handle, &pClient); - if (status != NV_OK) - { - _nvGpuOpsLocksRelease(&acquiredLocks); - threadStateFree(&threadState, THREAD_STATE_FLAGS_NONE); - return status; - } - status = vaspaceGetByHandleOrDeviceDefault(pClient, vaSpace->device->handle, vaSpace->handle, @@ -8459,6 +9140,9 @@ ct_assert(NV_OFFSETOF(UvmPmaStatistics, numPages2m) == NV_OFFSETOF(PMA_STATS, num2mbPages)); ct_assert(NV_OFFSETOF(UvmPmaStatistics, numFreePages64k) == NV_OFFSETOF(PMA_STATS, numFreeFrames)); ct_assert(NV_OFFSETOF(UvmPmaStatistics, numFreePages2m) == NV_OFFSETOF(PMA_STATS, numFree2mbPages)); +ct_assert(NV_OFFSETOF(UvmPmaStatistics, numPages2mProtected) == NV_OFFSETOF(PMA_STATS, num2mbPagesProtected)); +ct_assert(NV_OFFSETOF(UvmPmaStatistics, numFreePages64kProtected) == NV_OFFSETOF(PMA_STATS, numFreeFramesProtected)); +ct_assert(NV_OFFSETOF(UvmPmaStatistics, numFreePages2mProtected) == NV_OFFSETOF(PMA_STATS, numFree2mbPagesProtected)); /*! * Retrieve the PMA (Physical Memory Allocator) object initialized by RM @@ -8497,53 +9181,51 @@ return status; } - status = CliSetGpuContext(session->handle, device->handle, &pGpu, NULL); - if (status != NV_OK) - { - _nvGpuOpsLocksRelease(&acquiredLocks); - threadStateFree(&threadState, THREAD_STATE_FLAGS_NONE); - return NV_ERR_OBJECT_NOT_FOUND; - } + NV_CHECK_OK_OR_GOTO(status, LEVEL_ERROR, + CliSetGpuContext(session->handle, device->handle, &pGpu, NULL), + done); pMemoryManager = GPU_GET_MEMORY_MANAGER(pGpu); - if (pMemoryManager == NULL) - { - _nvGpuOpsLocksRelease(&acquiredLocks); - threadStateFree(&threadState, THREAD_STATE_FLAGS_NONE); - return NV_ERR_OBJECT_NOT_FOUND; - } + NV_CHECK_OR_ELSE(LEVEL_ERROR, + pMemoryManager != NULL, + status = NV_ERR_OBJECT_NOT_FOUND; goto done; ); if (IS_MIG_IN_USE(pGpu)) { KernelMIGManager *pKernelMIGManager = GPU_GET_KERNEL_MIG_MANAGER(pGpu); + RsClient *pClient; + Device *pDevice; - status = kmigmgrGetMemoryPartitionHeapFromClient(pGpu, pKernelMIGManager, session->handle, &pHeap); - if (status != NV_OK) - return status; + NV_ASSERT_OK_OR_GOTO(status, + serverGetClientUnderLock(&g_resServ, session->handle, &pClient), + done); + + NV_ASSERT_OK_OR_GOTO(status, + deviceGetByHandle(pClient, device->handle, &pDevice), + done); + + NV_CHECK_OK_OR_GOTO(status, LEVEL_ERROR, + kmigmgrGetMemoryPartitionHeapFromDevice(pGpu, pKernelMIGManager, pDevice, &pHeap), + done); } else pHeap = GPU_GET_HEAP(pGpu); - if (pHeap == NULL) - { - _nvGpuOpsLocksRelease(&acquiredLocks); - threadStateFree(&threadState, THREAD_STATE_FLAGS_NONE); - return NV_ERR_OBJECT_NOT_FOUND; - } - - if (!memmgrIsPmaInitialized(pMemoryManager)) - { - _nvGpuOpsLocksRelease(&acquiredLocks); - threadStateFree(&threadState, THREAD_STATE_FLAGS_NONE); - return NV_ERR_OBJECT_NOT_FOUND; - } + NV_CHECK_OR_ELSE(LEVEL_ERROR, + pHeap != NULL, + status = NV_ERR_OBJECT_NOT_FOUND; goto done; ); + + NV_CHECK_OR_ELSE(LEVEL_ERROR, + memmgrIsPmaInitialized(pMemoryManager), + status = NV_ERR_OBJECT_NOT_FOUND; goto done; ); *pPmaObject = (void *)&pHeap->pmaObject; *pPmaStats = (const UvmPmaStatistics *)&pHeap->pmaObject.pmaStats; +done: _nvGpuOpsLocksRelease(&acquiredLocks); threadStateFree(&threadState, THREAD_STATE_FLAGS_NONE); - return NV_OK; + return status; } NV_STATUS nvGpuOpsP2pObjectCreate(struct gpuDevice *device1, @@ -8575,7 +9257,7 @@ session = device1->session; hTemp = NV01_NULL_OBJECT; - status = pRmApi->Alloc(pRmApi, session->handle, session->handle, &hTemp, NV50_P2P, &p2pAllocParams); + status = pRmApi->Alloc(pRmApi, session->handle, session->handle, &hTemp, NV50_P2P, &p2pAllocParams, sizeof(p2pAllocParams)); if (status == NV_OK) *hP2pObject = hTemp; @@ -8979,3 +9661,136 @@ ppMemory); } +NV_STATUS nvGpuOpsCcslContextInit(struct ccslContext_t **ctx, + struct gpuChannel *channel) +{ + if ((ctx == NULL) || (channel == NULL)) + { + return NV_ERR_INVALID_ARGUMENT; + } + + return ccslContextInitViaChannel(ctx, channel->tsg->vaSpace->device->session->handle, channel->channelHandle); +} + +NV_STATUS nvGpuOpsCcslContextClear(struct ccslContext_t *ctx) +{ + if (ctx == NULL) + { + return NV_ERR_INVALID_ARGUMENT; + } + + ccslContextClear(ctx); + return NV_OK; +} + +NV_STATUS nvGpuOpsCcslRotateIv(struct ccslContext_t *ctx, NvU8 direction) +{ + if (ctx == NULL) + { + return NV_ERR_INVALID_ARGUMENT; + } + + return ccslRotateIv(ctx, direction); +} + +NV_STATUS nvGpuOpsCcslEncryptWithIv(struct ccslContext_t *ctx, + NvU32 bufferSize, + NvU8 const *inputBuffer, + NvU8 *encryptIv, + NvU8 *outputBuffer, + NvU8 *authTagBuffer) +{ + if (ctx == NULL) + { + return NV_ERR_INVALID_ARGUMENT; + } + return ccslEncryptWithIv(ctx, bufferSize, inputBuffer, encryptIv, NULL, 0, + outputBuffer, authTagBuffer); +} + +NV_STATUS nvGpuOpsCcslEncrypt(struct ccslContext_t *ctx, + NvU32 bufferSize, + NvU8 const *inputBuffer, + NvU8 *outputBuffer, + NvU8 *authTagBuffer) +{ + if (ctx == NULL) + { + return NV_ERR_INVALID_ARGUMENT; + } + + return ccslEncrypt(ctx, bufferSize, inputBuffer, NULL, 0, + outputBuffer, authTagBuffer); +} + +NV_STATUS nvGpuOpsCcslDecrypt(struct ccslContext_t *ctx, + NvU32 bufferSize, + NvU8 const *inputBuffer, + NvU8 const *decryptIv, + NvU8 *outputBuffer, + NvU8 const *addAuthData, + NvU32 addAuthDataSize, + NvU8 const *authTagBuffer) +{ + if (ctx == NULL) + { + return NV_ERR_INVALID_ARGUMENT; + } + + return ccslDecrypt(ctx, bufferSize, inputBuffer, decryptIv, addAuthData, addAuthDataSize, + outputBuffer, authTagBuffer); +} + +NV_STATUS nvGpuOpsCcslSign(struct ccslContext_t *ctx, + NvU32 bufferSize, + NvU8 const *inputBuffer, + NvU8 *authTagBuffer) +{ + if (ctx == NULL) + { + return NV_ERR_INVALID_ARGUMENT; + } + + return ccslSign(ctx, bufferSize, inputBuffer, authTagBuffer); +} + +NV_STATUS nvGpuOpsQueryMessagePool(struct ccslContext_t *ctx, + NvU8 direction, + NvU64 *messageNum) +{ + if (ctx == NULL) + { + return NV_ERR_INVALID_ARGUMENT; + } + + switch (direction) + { + case UVM_CSL_OPERATION_ENCRYPT: + return ccslQueryMessagePool(ctx, CCSL_DIR_HOST_TO_DEVICE, messageNum); + case UVM_CSL_OPERATION_DECRYPT: + return ccslQueryMessagePool(ctx, CCSL_DIR_DEVICE_TO_HOST, messageNum); + default: + return NV_ERR_INVALID_ARGUMENT; + } +} + +NV_STATUS nvGpuOpsIncrementIv(struct ccslContext_t *ctx, + NvU8 direction, + NvU64 increment, + NvU8 *iv) +{ + if (ctx == NULL) + { + return NV_ERR_INVALID_ARGUMENT; + } + + switch (direction) + { + case UVM_CSL_OPERATION_ENCRYPT: + return ccslIncrementIv(ctx, CCSL_DIR_HOST_TO_DEVICE, increment, iv); + case UVM_CSL_OPERATION_DECRYPT: + return ccslIncrementIv(ctx, CCSL_DIR_DEVICE_TO_HOST, increment, iv); + default: + return NV_ERR_INVALID_ARGUMENT; + } +} diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/kernel/rmapi/param_copy.c nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/kernel/rmapi/param_copy.c --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/kernel/rmapi/param_copy.c 2023-10-25 20:21:31.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/kernel/rmapi/param_copy.c 2024-03-05 22:14:04.000000000 +0000 @@ -73,6 +73,10 @@ pParamCopy->flags |= RMAPI_PARAM_COPY_FLAGS_IS_DIRECT_USAGE; pKernelParams = NvP64_VALUE(pParamCopy->pUserParams); + + if (pParamCopy->flags & RMAPI_PARAM_COPY_FLAGS_ZERO_BUFFER) + portMemSet(pKernelParams, 0, pParamCopy->paramsSize); + goto done; } diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/kernel/rmapi/resource.c nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/kernel/rmapi/resource.c --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/kernel/rmapi/resource.c 2023-10-25 20:21:31.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/kernel/rmapi/resource.c 2024-03-05 22:14:04.000000000 +0000 @@ -225,24 +225,67 @@ } NV_STATUS +rmresControlSerialization_Prologue_IMPL +( + RmResource *pResource, + CALL_CONTEXT *pCallContext, + RS_RES_CONTROL_PARAMS_INTERNAL *pParams +) +{ + OBJGPU *pGpu = gpumgrGetGpu(pResource->rpcGpuInstance); + + if (pGpu != NULL && + ((IS_VIRTUAL(pGpu) && (pParams->pCookie->ctrlFlags & RMCTRL_FLAGS_ROUTE_TO_VGPU_HOST)) || + (IS_GSP_CLIENT(pGpu) && (pParams->pCookie->ctrlFlags & RMCTRL_FLAGS_ROUTE_TO_PHYSICAL)))) + { + return serverSerializeCtrlDown(pCallContext, pParams->cmd, &pParams->pParams, &pParams->paramsSize, &pParams->flags); + } + else + { + NV_CHECK_OK_OR_RETURN(LEVEL_ERROR, serverDeserializeCtrlDown(pCallContext, pParams->cmd, &pParams->pParams, &pParams->paramsSize, &pParams->flags)); + } + + return NV_OK; +} + +void +rmresControlSerialization_Epilogue_IMPL +( + RmResource *pResource, + CALL_CONTEXT *pCallContext, + RS_RES_CONTROL_PARAMS_INTERNAL *pParams +) +{ + OBJGPU *pGpu = gpumgrGetGpu(pResource->rpcGpuInstance); + + if (pGpu != NULL && + ((IS_VIRTUAL(pGpu) && (pParams->pCookie->ctrlFlags & RMCTRL_FLAGS_ROUTE_TO_VGPU_HOST)) || + (IS_GSP_CLIENT(pGpu) && (pParams->pCookie->ctrlFlags & RMCTRL_FLAGS_ROUTE_TO_PHYSICAL)))) + { + NV_ASSERT_OK(serverDeserializeCtrlUp(pCallContext, pParams->cmd, &pParams->pParams, &pParams->paramsSize, &pParams->flags)); + } + + NV_ASSERT_OK(serverSerializeCtrlUp(pCallContext, pParams->cmd, &pParams->pParams, &pParams->paramsSize, &pParams->flags)); + serverFreeSerializeStructures(pCallContext, pParams->pParams); +} + +NV_STATUS rmresControl_Prologue_IMPL ( - RmResource *pResource, - CALL_CONTEXT *pCallContext, + RmResource *pResource, + CALL_CONTEXT *pCallContext, RS_RES_CONTROL_PARAMS_INTERNAL *pParams ) { NV_STATUS status = NV_OK; OBJGPU *pGpu = gpumgrGetGpu(pResource->rpcGpuInstance); - if (pGpu == NULL) - return NV_OK; - - if ((IS_VIRTUAL(pGpu) && (pParams->pCookie->ctrlFlags & RMCTRL_FLAGS_ROUTE_TO_VGPU_HOST)) || - (IS_GSP_CLIENT(pGpu) && (pParams->pCookie->ctrlFlags & RMCTRL_FLAGS_ROUTE_TO_PHYSICAL))) + if (pGpu != NULL && + ((IS_VIRTUAL(pGpu) && (pParams->pCookie->ctrlFlags & RMCTRL_FLAGS_ROUTE_TO_VGPU_HOST)) || + (IS_GSP_CLIENT(pGpu) && (pParams->pCookie->ctrlFlags & RMCTRL_FLAGS_ROUTE_TO_PHYSICAL)))) { // - // GPU lock is required to protect the RPC buffers. + // GPU lock is required to protect the RPC buffers. // However, some controls have ROUTE_TO_PHYSICAL + NO_GPUS_LOCK flags set. // This is not valid in offload mode, but is in monolithic. // In those cases, just acquire the lock for the RPC @@ -272,6 +315,7 @@ return (status == NV_OK) ? NV_WARN_NOTHING_TO_DO : status; } + return NV_OK; } diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/kernel/rmapi/resource_desc.c nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/kernel/rmapi/resource_desc.c --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/kernel/rmapi/resource_desc.c 2023-10-25 20:21:31.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/kernel/rmapi/resource_desc.c 2024-03-05 22:14:04.000000000 +0000 @@ -109,7 +109,7 @@ #undef RS_OPTIONAL #undef RS_NONE -#define NUM_ENTRIES_DESC_LIST NV_ARRAY_ELEMENTS32(g_RsResourceDescList) +#define NUM_ENTRIES_DESC_LIST NV_ARRAY_ELEMENTS(g_RsResourceDescList) void RsResInfoInitialize(void) { diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/kernel/rmapi/resource_desc.h nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/kernel/rmapi/resource_desc.h --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/kernel/rmapi/resource_desc.h 2023-10-25 20:21:31.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/kernel/rmapi/resource_desc.h 2024-03-05 22:14:04.000000000 +0000 @@ -26,32 +26,7 @@ #include "nvtypes.h" #include "nvoc/runtime.h" #include "resserv/rs_access_rights.h" - -// Flags for RS_ENTRY -#define RS_FLAGS_NONE 0 - -#define RS_FLAGS_ACQUIRE_GPUS_LOCK_ON_ALLOC NVBIT(0) ///< GPUs Lock is acquired on allocation -#define RS_FLAGS_ACQUIRE_GPUS_LOCK_ON_FREE NVBIT(1) ///< GPUs Lock is acquired for free -#define RS_FLAGS_ACQUIRE_GPUS_LOCK (RS_FLAGS_ACQUIRE_GPUS_LOCK_ON_ALLOC | RS_FLAGS_ACQUIRE_GPUS_LOCK_ON_FREE) - -#define RS_FLAGS_ACQUIRE_GPU_GROUP_LOCK_ON_ALLOC NVBIT(2) ///< GPU Group Lock is acquired on allocation -#define RS_FLAGS_ACQUIRE_GPU_GROUP_LOCK_ON_FREE NVBIT(3) ///< GPU Group Lock is acquired for free -#define RS_FLAGS_ACQUIRE_GPU_GROUP_LOCK (RS_FLAGS_ACQUIRE_GPU_GROUP_LOCK_ON_ALLOC | RS_FLAGS_ACQUIRE_GPU_GROUP_LOCK_ON_FREE) - -#define RS_FLAGS_ALLOC_RPC_TO_VGPU_HOST NVBIT(4) ///< Issue RPC to host to allocate resource for virtual GPUs - -#define RS_FLAGS_ACQUIRE_RO_API_LOCK_ON_ALLOC NVBIT(5) ///< Acquire the RO API lock for allocation, default is RW API lock - -#define RS_FLAGS_ALLOC_RPC_TO_PHYS_RM NVBIT(6) ///< Issue RPC to allocate resource in physical RM - -#define RS_FLAGS_ALLOC_RPC_TO_ALL (RS_FLAGS_ALLOC_RPC_TO_VGPU_HOST | RS_FLAGS_ALLOC_RPC_TO_PHYS_RM) - -#define RS_FLAGS_INTERNAL_ONLY NVBIT(7) ///< Class cannot be allocated outside of RM - -#define RS_FLAGS_CHANNEL_DESCENDANT_COMMON (RS_FLAGS_ACQUIRE_GPUS_LOCK | RS_FLAGS_ALLOC_RPC_TO_ALL) - -#define RS_FREE_PRIORITY_DEFAULT 0 -#define RS_FREE_PRIORITY_HIGH 1 ///< Resources with this priority will be freed ahead of others +#include "resource_desc_flags.h" /** * Information about a RsResource subclass. diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/kernel/rmapi/resource_desc_flags.h nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/kernel/rmapi/resource_desc_flags.h --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/kernel/rmapi/resource_desc_flags.h 1970-01-01 00:00:00.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/kernel/rmapi/resource_desc_flags.h 2024-03-05 22:14:05.000000000 +0000 @@ -0,0 +1,58 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2016-2021 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ +#ifndef _RESOURCE_DESC_FLAGS_H_ +#define _RESOURCE_DESC_FLAGS_H_ + +// Flags for RS_ENTRY +#define RS_FLAGS_NONE 0 + +#define RS_FLAGS_ACQUIRE_GPUS_LOCK_ON_ALLOC NVBIT(0) ///< GPUs Lock is acquired on allocation +#define RS_FLAGS_ACQUIRE_GPUS_LOCK_ON_FREE NVBIT(1) ///< GPUs Lock is acquired for free +#define RS_FLAGS_ACQUIRE_GPUS_LOCK (RS_FLAGS_ACQUIRE_GPUS_LOCK_ON_ALLOC | RS_FLAGS_ACQUIRE_GPUS_LOCK_ON_FREE) + +#define RS_FLAGS_ACQUIRE_GPU_GROUP_LOCK_ON_ALLOC NVBIT(2) ///< GPU Group Lock is acquired on allocation +#define RS_FLAGS_ACQUIRE_GPU_GROUP_LOCK_ON_FREE NVBIT(3) ///< GPU Group Lock is acquired for free +#define RS_FLAGS_ACQUIRE_GPU_GROUP_LOCK (RS_FLAGS_ACQUIRE_GPU_GROUP_LOCK_ON_ALLOC | RS_FLAGS_ACQUIRE_GPU_GROUP_LOCK_ON_FREE) + +#define RS_FLAGS_ALLOC_RPC_TO_VGPU_HOST NVBIT(4) ///< Issue RPC to host to allocate resource for virtual GPUs + +#define RS_FLAGS_ACQUIRE_RO_API_LOCK_ON_ALLOC NVBIT(5) ///< Acquire the RO API lock for allocation, default is RW API lock + +#define RS_FLAGS_ALLOC_RPC_TO_PHYS_RM NVBIT(6) ///< Issue RPC to allocate resource in physical RM + +#define RS_FLAGS_ALLOC_RPC_TO_ALL (RS_FLAGS_ALLOC_RPC_TO_VGPU_HOST | RS_FLAGS_ALLOC_RPC_TO_PHYS_RM) + +#define RS_FLAGS_INTERNAL_ONLY NVBIT(7) ///< Class cannot be allocated outside of RM + +#define RS_FLAGS_CHANNEL_DESCENDANT_COMMON (RS_FLAGS_ACQUIRE_GPUS_LOCK | RS_FLAGS_ALLOC_RPC_TO_ALL) + +#define RS_FREE_PRIORITY_DEFAULT 0 +#define RS_FREE_PRIORITY_HIGH 1 ///< Resources with this priority will be freed ahead of others + +#define RS_FLAGS_ALLOC_NON_PRIVILEGED NVBIT(8) ///< Class is non privileged + +#define RS_FLAGS_ALLOC_PRIVILEGED NVBIT(9) ///< Class requires at least admin privilege + +#define RS_FLAGS_ALLOC_KERNEL_PRIVILEGED NVBIT(10) ///< Class requires at least kernel privilege + +#endif // _RESOURCE_DESC_FLAGS_H_ diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/kernel/rmapi/resource_list.h nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/kernel/rmapi/resource_list.h --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/kernel/rmapi/resource_list.h 2023-10-25 20:21:31.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/kernel/rmapi/resource_list.h 2024-03-05 22:14:05.000000000 +0000 @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 2016-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2016-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -97,7 +97,7 @@ /* Parents */ RS_LIST(classId(RmClientResource)), /* Alloc Param Info */ RS_NONE, /* Resource Free Priority */ RS_FREE_PRIORITY_DEFAULT, - /* Flags */ RS_FLAGS_NONE, + /* Flags */ RS_FLAGS_ALLOC_NON_PRIVILEGED, /* Required Access Rights */ RS_ACCESS_NONE ) RS_ENTRY( @@ -107,7 +107,7 @@ /* Parents */ RS_LIST(classId(RmClientResource)), /* Alloc Param Info */ RS_REQUIRED(NV000F_ALLOCATION_PARAMETERS), /* Resource Free Priority */ RS_FREE_PRIORITY_DEFAULT, - /* Flags */ RS_FLAGS_ACQUIRE_GPUS_LOCK, + /* Flags */ RS_FLAGS_ALLOC_NON_PRIVILEGED | RS_FLAGS_ACQUIRE_GPUS_LOCK, /* Required Access Rights */ RS_ACCESS_NONE ) RS_ENTRY( @@ -117,7 +117,7 @@ /* Parents */ RS_LIST(classId(RmClientResource)), /* Alloc Param Info */ RS_OPTIONAL(NvHandle), /* Resource Free Priority */ RS_FREE_PRIORITY_DEFAULT, - /* Flags */ RS_FLAGS_ACQUIRE_GPUS_LOCK, + /* Flags */ RS_FLAGS_ALLOC_NON_PRIVILEGED | RS_FLAGS_ACQUIRE_GPUS_LOCK, /* Required Access Rights */ RS_ACCESS_NONE ) RS_ENTRY( @@ -127,7 +127,17 @@ /* Parents */ RS_LIST(classId(RmClientResource)), /* Alloc Param Info */ RS_REQUIRED(NV_EVENT_BUFFER_ALLOC_PARAMETERS), /* Resource Free Priority */ RS_FREE_PRIORITY_DEFAULT, - /* Flags */ RS_FLAGS_ACQUIRE_GPUS_LOCK, + /* Flags */ RS_FLAGS_ALLOC_NON_PRIVILEGED | RS_FLAGS_ACQUIRE_GPUS_LOCK, + /* Required Access Rights */ RS_ACCESS_NONE +) +RS_ENTRY( + /* External Class */ NV_SEMAPHORE_SURFACE, + /* Internal Class */ SemaphoreSurface, + /* Multi-Instance */ NV_TRUE, + /* Parents */ RS_LIST(classId(Subdevice)), + /* Alloc Param Info */ RS_REQUIRED(NV_SEMAPHORE_SURFACE_ALLOC_PARAMETERS), + /* Resource Free Priority */ RS_FREE_PRIORITY_DEFAULT, + /* Flags */ RS_FLAGS_ALLOC_NON_PRIVILEGED | RS_FLAGS_ACQUIRE_GPUS_LOCK, /* Required Access Rights */ RS_ACCESS_NONE ) RS_ENTRY( @@ -137,7 +147,7 @@ /* Parents */ RS_LIST(classId(RmClientResource)), /* Alloc Param Info */ RS_REQUIRED(NV503B_ALLOC_PARAMETERS), /* Resource Free Priority */ RS_FREE_PRIORITY_DEFAULT, - /* Flags */ RS_FLAGS_ACQUIRE_GPUS_LOCK, + /* Flags */ RS_FLAGS_ALLOC_NON_PRIVILEGED | RS_FLAGS_ACQUIRE_GPUS_LOCK, /* Required Access Rights */ RS_ACCESS_NONE ) RS_ENTRY( @@ -147,7 +157,7 @@ /* Parents */ RS_LIST(classId(RmClientResource)), /* Alloc Param Info */ RS_REQUIRED(NV0060_ALLOC_PARAMETERS), /* Resource Free Priority */ RS_FREE_PRIORITY_DEFAULT, - /* Flags */ RS_FLAGS_NONE, + /* Flags */ RS_FLAGS_ALLOC_NON_PRIVILEGED, /* Required Access Rights */ RS_ACCESS_NONE ) RS_ENTRY( @@ -157,7 +167,7 @@ /* Parents */ RS_LIST(classId(RmClientResource)), /* Alloc Param Info */ RS_OPTIONAL(NV0080_ALLOC_PARAMETERS), /* Resource Free Priority */ RS_FREE_PRIORITY_DEFAULT, - /* Flags */ RS_FLAGS_ACQUIRE_GPUS_LOCK | RS_FLAGS_ACQUIRE_RO_API_LOCK_ON_ALLOC, + /* Flags */ RS_FLAGS_ALLOC_NON_PRIVILEGED | RS_FLAGS_ACQUIRE_GPUS_LOCK | RS_FLAGS_ACQUIRE_RO_API_LOCK_ON_ALLOC, /* Required Access Rights */ RS_ACCESS_NONE ) RS_ENTRY( @@ -167,7 +177,7 @@ /* Parents */ RS_LIST(classId(Device)), /* Alloc Param Info */ RS_REQUIRED(NV83DE_ALLOC_PARAMETERS), /* Resource Free Priority */ RS_FREE_PRIORITY_DEFAULT, - /* Flags */ RS_FLAGS_ACQUIRE_GPUS_LOCK | RS_FLAGS_ALLOC_RPC_TO_ALL | RS_FLAGS_ACQUIRE_RO_API_LOCK_ON_ALLOC, + /* Flags */ RS_FLAGS_ALLOC_NON_PRIVILEGED | RS_FLAGS_ACQUIRE_GPUS_LOCK | RS_FLAGS_ALLOC_RPC_TO_ALL | RS_FLAGS_ACQUIRE_RO_API_LOCK_ON_ALLOC, /* Required Access Rights */ RS_ACCESS_NONE ) RS_ENTRY( @@ -177,7 +187,7 @@ /* Parents */ RS_LIST(classId(RmClientResource)), /* Alloc Param Info */ RS_REQUIRED(NV30F1_ALLOC_PARAMETERS), /* Resource Free Priority */ RS_FREE_PRIORITY_DEFAULT, - /* Flags */ RS_FLAGS_ACQUIRE_GPUS_LOCK, + /* Flags */ RS_FLAGS_ALLOC_NON_PRIVILEGED | RS_FLAGS_ACQUIRE_GPUS_LOCK, /* Required Access Rights */ RS_ACCESS_NONE ) RS_ENTRY( @@ -187,7 +197,7 @@ /* Parents */ RS_LIST(classId(Subdevice), classId(KernelChannel), classId(KernelChannelGroupApi)), /* Alloc Param Info */ RS_NONE, /* Resource Free Priority */ RS_FREE_PRIORITY_DEFAULT, - /* Flags */ RS_FLAGS_ACQUIRE_GPUS_LOCK | RS_FLAGS_ALLOC_RPC_TO_PHYS_RM, + /* Flags */ RS_FLAGS_ALLOC_NON_PRIVILEGED | RS_FLAGS_ACQUIRE_GPUS_LOCK | RS_FLAGS_ALLOC_RPC_TO_PHYS_RM, /* Required Access Rights */ RS_ACCESS_NONE ) RS_ENTRY( @@ -197,7 +207,7 @@ /* Parents */ RS_LIST(classId(Subdevice)), /* Alloc Param Info */ RS_REQUIRED(NVB2CC_ALLOC_PARAMETERS), /* Resource Free Priority */ RS_FREE_PRIORITY_DEFAULT, - /* Flags */ RS_FLAGS_ACQUIRE_GPUS_LOCK, + /* Flags */ RS_FLAGS_ALLOC_NON_PRIVILEGED | RS_FLAGS_ACQUIRE_GPUS_LOCK, /* Required Access Rights */ RS_ACCESS_NONE ) RS_ENTRY( @@ -207,7 +217,7 @@ /* Parents */ RS_LIST(classId(Device)), /* Alloc Param Info */ RS_NONE, /* Resource Free Priority */ RS_FREE_PRIORITY_DEFAULT, - /* Flags */ RS_FLAGS_ACQUIRE_GPUS_LOCK, + /* Flags */ RS_FLAGS_ALLOC_NON_PRIVILEGED | RS_FLAGS_ACQUIRE_GPUS_LOCK, /* Required Access Rights */ RS_ACCESS_NONE ) RS_ENTRY( @@ -217,7 +227,7 @@ /* Parents */ RS_LIST(classId(Device)), /* Alloc Param Info */ RS_NONE, /* Resource Free Priority */ RS_FREE_PRIORITY_DEFAULT, - /* Flags */ RS_FLAGS_ACQUIRE_GPUS_LOCK_ON_FREE | RS_FLAGS_ALLOC_RPC_TO_ALL, + /* Flags */ RS_FLAGS_ALLOC_NON_PRIVILEGED | RS_FLAGS_ACQUIRE_GPUS_LOCK_ON_FREE | RS_FLAGS_ALLOC_RPC_TO_ALL, /* Required Access Rights */ RS_ACCESS_NONE ) /* Channels can have a CHANNEL_GROUP, a DEVICE, or a CONTEXT_SHARE (starting in Volta) as parents */ @@ -229,7 +239,7 @@ /* Parents */ RS_LIST(classId(Device), classId(KernelChannelGroupApi)), /* Alloc Param Info */ RS_REQUIRED(NV_CHANNEL_ALLOC_PARAMS), /* Resource Free Priority */ RS_FREE_PRIORITY_HIGH, - /* Flags */ RS_FLAGS_ACQUIRE_GPUS_LOCK_ON_FREE | RS_FLAGS_ACQUIRE_RO_API_LOCK_ON_ALLOC, + /* Flags */ RS_FLAGS_ALLOC_NON_PRIVILEGED | RS_FLAGS_ACQUIRE_GPUS_LOCK_ON_FREE | RS_FLAGS_ACQUIRE_RO_API_LOCK_ON_ALLOC, /* Required Access Rights */ RS_ACCESS_NONE ) RS_ENTRY( @@ -239,7 +249,7 @@ /* Parents */ RS_LIST(classId(Device), classId(KernelChannelGroupApi)), /* Alloc Param Info */ RS_REQUIRED(NV_CHANNEL_ALLOC_PARAMS), /* Resource Free Priority */ RS_FREE_PRIORITY_HIGH, - /* Flags */ RS_FLAGS_ACQUIRE_GPUS_LOCK_ON_FREE | RS_FLAGS_ACQUIRE_RO_API_LOCK_ON_ALLOC, + /* Flags */ RS_FLAGS_ALLOC_NON_PRIVILEGED | RS_FLAGS_ACQUIRE_GPUS_LOCK_ON_FREE | RS_FLAGS_ACQUIRE_RO_API_LOCK_ON_ALLOC, /* Required Access Rights */ RS_ACCESS_NONE ) RS_ENTRY( @@ -249,7 +259,7 @@ /* Parents */ RS_LIST(classId(Device), classId(KernelChannelGroupApi)), /* Alloc Param Info */ RS_REQUIRED(NV_CHANNEL_ALLOC_PARAMS), /* Resource Free Priority */ RS_FREE_PRIORITY_HIGH, - /* Flags */ RS_FLAGS_ACQUIRE_GPUS_LOCK_ON_FREE | RS_FLAGS_ACQUIRE_RO_API_LOCK_ON_ALLOC, + /* Flags */ RS_FLAGS_ALLOC_NON_PRIVILEGED | RS_FLAGS_ACQUIRE_GPUS_LOCK_ON_FREE | RS_FLAGS_ACQUIRE_RO_API_LOCK_ON_ALLOC, /* Required Access Rights */ RS_ACCESS_NONE ) RS_ENTRY( @@ -259,7 +269,7 @@ /* Parents */ RS_LIST(classId(Device), classId(KernelChannelGroupApi)), /* Alloc Param Info */ RS_REQUIRED(NV_CHANNEL_ALLOC_PARAMS), /* Resource Free Priority */ RS_FREE_PRIORITY_HIGH, - /* Flags */ RS_FLAGS_ACQUIRE_GPUS_LOCK_ON_FREE | RS_FLAGS_ACQUIRE_RO_API_LOCK_ON_ALLOC, + /* Flags */ RS_FLAGS_ALLOC_NON_PRIVILEGED | RS_FLAGS_ACQUIRE_GPUS_LOCK_ON_FREE | RS_FLAGS_ACQUIRE_RO_API_LOCK_ON_ALLOC, /* Required Access Rights */ RS_ACCESS_NONE ) RS_ENTRY( @@ -269,7 +279,7 @@ /* Parents */ RS_LIST(classId(Device), classId(KernelChannelGroupApi)), /* Alloc Param Info */ RS_REQUIRED(NV_CHANNEL_ALLOC_PARAMS), /* Resource Free Priority */ RS_FREE_PRIORITY_HIGH, - /* Flags */ RS_FLAGS_ACQUIRE_GPUS_LOCK_ON_FREE | RS_FLAGS_ACQUIRE_RO_API_LOCK_ON_ALLOC, + /* Flags */ RS_FLAGS_ALLOC_NON_PRIVILEGED | RS_FLAGS_ACQUIRE_GPUS_LOCK_ON_FREE | RS_FLAGS_ACQUIRE_RO_API_LOCK_ON_ALLOC, /* Required Access Rights */ RS_ACCESS_NONE ) RS_ENTRY( @@ -279,7 +289,7 @@ /* Parents */ RS_LIST(classId(Device), classId(KernelChannelGroupApi)), /* Alloc Param Info */ RS_REQUIRED(NV_CHANNEL_ALLOC_PARAMS), /* Resource Free Priority */ RS_FREE_PRIORITY_HIGH, - /* Flags */ RS_FLAGS_ACQUIRE_GPUS_LOCK_ON_FREE | RS_FLAGS_ACQUIRE_RO_API_LOCK_ON_ALLOC, + /* Flags */ RS_FLAGS_ALLOC_NON_PRIVILEGED | RS_FLAGS_ACQUIRE_GPUS_LOCK_ON_FREE | RS_FLAGS_ACQUIRE_RO_API_LOCK_ON_ALLOC, /* Required Access Rights */ RS_ACCESS_NONE ) RS_ENTRY( @@ -289,7 +299,7 @@ /* Parents */ RS_LIST(classId(Device), classId(KernelChannelGroupApi)), /* Alloc Param Info */ RS_REQUIRED(NV_CHANNEL_ALLOC_PARAMS), /* Resource Free Priority */ RS_FREE_PRIORITY_HIGH, - /* Flags */ RS_FLAGS_ACQUIRE_GPUS_LOCK_ON_FREE | RS_FLAGS_ACQUIRE_RO_API_LOCK_ON_ALLOC, + /* Flags */ RS_FLAGS_ALLOC_NON_PRIVILEGED | RS_FLAGS_ACQUIRE_GPUS_LOCK_ON_FREE | RS_FLAGS_ACQUIRE_RO_API_LOCK_ON_ALLOC, /* Required Access Rights */ RS_ACCESS_NONE ) RS_ENTRY( @@ -299,7 +309,7 @@ /* Parents */ RS_LIST(classId(Device), classId(KernelChannelGroupApi)), /* Alloc Param Info */ RS_REQUIRED(NV_CHANNEL_ALLOC_PARAMS), /* Resource Free Priority */ RS_FREE_PRIORITY_HIGH, - /* Flags */ RS_FLAGS_ACQUIRE_GPUS_LOCK_ON_FREE | RS_FLAGS_ACQUIRE_RO_API_LOCK_ON_ALLOC, + /* Flags */ RS_FLAGS_ALLOC_NON_PRIVILEGED | RS_FLAGS_ACQUIRE_GPUS_LOCK_ON_FREE | RS_FLAGS_ACQUIRE_RO_API_LOCK_ON_ALLOC, /* Required Access Rights */ RS_ACCESS_NONE ) RS_ENTRY( @@ -309,7 +319,7 @@ /* Parents */ RS_LIST(classId(Device), classId(KernelChannelGroupApi)), /* Alloc Param Info */ RS_REQUIRED(NV_CHANNEL_ALLOC_PARAMS), /* Resource Free Priority */ RS_FREE_PRIORITY_HIGH, - /* Flags */ RS_FLAGS_ACQUIRE_GPUS_LOCK_ON_FREE | RS_FLAGS_ACQUIRE_RO_API_LOCK_ON_ALLOC, + /* Flags */ RS_FLAGS_ALLOC_NON_PRIVILEGED | RS_FLAGS_ACQUIRE_GPUS_LOCK_ON_FREE | RS_FLAGS_ACQUIRE_RO_API_LOCK_ON_ALLOC, /* Required Access Rights */ RS_ACCESS_NONE ) RS_ENTRY( @@ -319,7 +329,7 @@ /* Parents */ RS_LIST(classId(Device), classId(KernelChannelGroupApi)), /* Alloc Param Info */ RS_REQUIRED(NV_UVM_CHANNEL_RETAINER_ALLOC_PARAMS), /* Resource Free Priority */ RS_FREE_PRIORITY_HIGH, - /* Flags */ RS_FLAGS_ACQUIRE_GPUS_LOCK | RS_FLAGS_ALLOC_RPC_TO_ALL | RS_FLAGS_ACQUIRE_RO_API_LOCK_ON_ALLOC, + /* Flags */ RS_FLAGS_ALLOC_KERNEL_PRIVILEGED | RS_FLAGS_ACQUIRE_GPUS_LOCK | RS_FLAGS_ALLOC_RPC_TO_ALL | RS_FLAGS_ACQUIRE_RO_API_LOCK_ON_ALLOC, /* Required Access Rights */ RS_ACCESS_NONE ) RS_ENTRY( @@ -329,7 +339,7 @@ /* Parents */ RS_LIST(classId(KernelChannelGroupApi)), /* Alloc Param Info */ RS_REQUIRED(NV_CTXSHARE_ALLOCATION_PARAMETERS), /* Resource Free Priority */ RS_FREE_PRIORITY_DEFAULT, - /* Flags */ RS_FLAGS_ACQUIRE_GPUS_LOCK | RS_FLAGS_ALLOC_RPC_TO_ALL, + /* Flags */ RS_FLAGS_ALLOC_NON_PRIVILEGED | RS_FLAGS_ACQUIRE_GPUS_LOCK | RS_FLAGS_ALLOC_RPC_TO_ALL, /* Required Access Rights */ RS_ACCESS_NONE ) RS_ENTRY( @@ -339,7 +349,7 @@ /* Parents */ RS_LIST(classId(KernelChannelGroupApi), classId(KernelChannel)), /* Alloc Param Info */ RS_NONE, /* Resource Free Priority */ RS_FREE_PRIORITY_DEFAULT, - /* Flags */ RS_FLAGS_ACQUIRE_GPUS_LOCK | RS_FLAGS_ACQUIRE_RO_API_LOCK_ON_ALLOC | RS_FLAGS_INTERNAL_ONLY, + /* Flags */ RS_FLAGS_ALLOC_NON_PRIVILEGED | RS_FLAGS_ACQUIRE_GPUS_LOCK | RS_FLAGS_ACQUIRE_RO_API_LOCK_ON_ALLOC | RS_FLAGS_INTERNAL_ONLY, /* Required Access Rights */ RS_ACCESS_NONE ) RS_ENTRY( @@ -349,7 +359,7 @@ /* Parents */ RS_LIST(classId(Device)), /* Alloc Param Info */ RS_OPTIONAL(NV2080_ALLOC_PARAMETERS), /* Resource Free Priority */ RS_FREE_PRIORITY_DEFAULT, - /* Flags */ RS_FLAGS_ACQUIRE_GPUS_LOCK | RS_FLAGS_ACQUIRE_RO_API_LOCK_ON_ALLOC, + /* Flags */ RS_FLAGS_ALLOC_NON_PRIVILEGED | RS_FLAGS_ACQUIRE_GPUS_LOCK | RS_FLAGS_ACQUIRE_RO_API_LOCK_ON_ALLOC, /* Required Access Rights */ RS_ACCESS_NONE ) RS_ENTRY( @@ -359,7 +369,7 @@ /* Parents */ RS_LIST(classId(Subdevice)), /* Alloc Param Info */ RS_OPTIONAL(NV2081_ALLOC_PARAMETERS), /* Resource Free Priority */ RS_FREE_PRIORITY_DEFAULT, - /* Flags */ RS_FLAGS_ACQUIRE_GPUS_LOCK | RS_FLAGS_ACQUIRE_RO_API_LOCK_ON_ALLOC | RS_FLAGS_ALLOC_RPC_TO_PHYS_RM, + /* Flags */ RS_FLAGS_ALLOC_NON_PRIVILEGED | RS_FLAGS_ACQUIRE_GPUS_LOCK | RS_FLAGS_ACQUIRE_RO_API_LOCK_ON_ALLOC | RS_FLAGS_ALLOC_RPC_TO_PHYS_RM, /* Required Access Rights */ RS_ACCESS_NONE ) RS_ENTRY( @@ -369,7 +379,7 @@ /* Parents */ RS_LIST(classId(Subdevice)), /* Alloc Param Info */ RS_OPTIONAL(NV2082_ALLOC_PARAMETERS), /* Resource Free Priority */ RS_FREE_PRIORITY_DEFAULT, - /* Flags */ RS_FLAGS_ACQUIRE_GPUS_LOCK | RS_FLAGS_ACQUIRE_RO_API_LOCK_ON_ALLOC | RS_FLAGS_ALLOC_RPC_TO_PHYS_RM, + /* Flags */ RS_FLAGS_ALLOC_PRIVILEGED | RS_FLAGS_ACQUIRE_GPUS_LOCK | RS_FLAGS_ACQUIRE_RO_API_LOCK_ON_ALLOC | RS_FLAGS_ALLOC_RPC_TO_PHYS_RM, /* Required Access Rights */ RS_ACCESS_NONE ) RS_ENTRY( @@ -379,7 +389,7 @@ /* Parents */ RS_LIST(classId(Device)), /* Alloc Param Info */ RS_REQUIRED(NV_CHANNEL_GROUP_ALLOCATION_PARAMETERS), /* Resource Free Priority */ RS_FREE_PRIORITY_HIGH, - /* Flags */ RS_FLAGS_ACQUIRE_GPUS_LOCK_ON_FREE | RS_FLAGS_ACQUIRE_RO_API_LOCK_ON_ALLOC, + /* Flags */ RS_FLAGS_ALLOC_NON_PRIVILEGED | RS_FLAGS_ACQUIRE_GPUS_LOCK_ON_FREE | RS_FLAGS_ACQUIRE_RO_API_LOCK_ON_ALLOC, /* Required Access Rights */ RS_ACCESS_NONE ) RS_ENTRY( @@ -389,7 +399,7 @@ /* Parents */ RS_LIST(classId(Device)), /* Alloc Param Info */ RS_NONE, /* Resource Free Priority */ RS_FREE_PRIORITY_DEFAULT, - /* Flags */ RS_FLAGS_ACQUIRE_GPUS_LOCK, + /* Flags */ RS_FLAGS_ALLOC_NON_PRIVILEGED | RS_FLAGS_ACQUIRE_GPUS_LOCK, /* Required Access Rights */ RS_ACCESS_NONE ) RS_ENTRY( @@ -399,7 +409,17 @@ /* Parents */ RS_LIST(classId(Device), classId(Subdevice)), /* Alloc Param Info */ RS_REQUIRED(NV_MEMORY_ALLOCATION_PARAMS), /* Resource Free Priority */ RS_FREE_PRIORITY_DEFAULT, - /* Flags */ RS_FLAGS_ACQUIRE_GPUS_LOCK_ON_FREE | RS_FLAGS_ACQUIRE_RO_API_LOCK_ON_ALLOC, + /* Flags */ RS_FLAGS_ALLOC_NON_PRIVILEGED | RS_FLAGS_ACQUIRE_GPUS_LOCK_ON_FREE | RS_FLAGS_ACQUIRE_RO_API_LOCK_ON_ALLOC, + /* Required Access Rights */ RS_ACCESS_NONE +) +RS_ENTRY( + /* External Class */ NV_MEMORY_EXTENDED_USER, + /* Internal Class */ ExtendedGpuMemory, + /* Multi-Instance */ NV_TRUE, + /* Parents */ RS_LIST(classId(Device), classId(Subdevice)), + /* Alloc Param Info */ RS_REQUIRED(NV_MEMORY_ALLOCATION_PARAMS), + /* Resource Free Priority */ RS_FREE_PRIORITY_DEFAULT, + /* Flags */ RS_FLAGS_ALLOC_NON_PRIVILEGED | RS_FLAGS_ACQUIRE_GPUS_LOCK_ON_FREE | RS_FLAGS_ACQUIRE_RO_API_LOCK_ON_ALLOC, /* Required Access Rights */ RS_ACCESS_NONE ) RS_ENTRY( @@ -409,7 +429,7 @@ /* Parents */ RS_LIST(classId(Device)), /* Alloc Param Info */ RS_REQUIRED(NV_PHYSICAL_MEMORY_ALLOCATION_PARAMS), /* Resource Free Priority */ RS_FREE_PRIORITY_DEFAULT, - /* Flags */ RS_FLAGS_ACQUIRE_GPUS_LOCK, + /* Flags */ RS_FLAGS_ALLOC_PRIVILEGED | RS_FLAGS_ACQUIRE_GPUS_LOCK, /* Required Access Rights */ RS_ACCESS_NONE ) RS_ENTRY( @@ -419,7 +439,7 @@ /* Parents */ RS_LIST(classId(Device)), /* Alloc Param Info */ RS_REQUIRED(NV_MEMORY_ALLOCATION_PARAMS), /* Resource Free Priority */ RS_FREE_PRIORITY_DEFAULT, - /* Flags */ RS_FLAGS_ACQUIRE_GPUS_LOCK_ON_FREE | RS_FLAGS_ACQUIRE_RO_API_LOCK_ON_ALLOC, + /* Flags */ RS_FLAGS_ALLOC_NON_PRIVILEGED | RS_FLAGS_ACQUIRE_GPUS_LOCK_ON_FREE | RS_FLAGS_ACQUIRE_RO_API_LOCK_ON_ALLOC, /* Required Access Rights */ RS_ACCESS_NONE ) RS_ENTRY( @@ -429,7 +449,7 @@ /* Parents */ RS_LIST(classId(Device)), /* Alloc Param Info */ RS_REQUIRED(NV_MEMORY_ALLOCATION_PARAMS), /* Resource Free Priority */ RS_FREE_PRIORITY_DEFAULT, - /* Flags */ RS_FLAGS_ACQUIRE_GPUS_LOCK | RS_FLAGS_ACQUIRE_RO_API_LOCK_ON_ALLOC, + /* Flags */ RS_FLAGS_ALLOC_NON_PRIVILEGED | RS_FLAGS_ACQUIRE_GPUS_LOCK | RS_FLAGS_ACQUIRE_RO_API_LOCK_ON_ALLOC, /* Required Access Rights */ RS_ACCESS_NONE ) RS_ENTRY( @@ -439,7 +459,7 @@ /* Parents */ RS_LIST(classId(Device)), /* Alloc Param Info */ RS_REQUIRED(NV_MEMORY_VIRTUAL_ALLOCATION_PARAMS), /* Resource Free Priority */ RS_FREE_PRIORITY_DEFAULT, - /* Flags */ RS_FLAGS_ACQUIRE_GPUS_LOCK, + /* Flags */ RS_FLAGS_ALLOC_NON_PRIVILEGED | RS_FLAGS_ACQUIRE_GPUS_LOCK, /* Required Access Rights */ RS_ACCESS_NONE ) RS_ENTRY( @@ -449,7 +469,7 @@ /* Parents */ RS_LIST(classId(Subdevice)), /* Alloc Param Info */ RS_REQUIRED(NV_MEMORY_MAPPER_ALLOCATION_PARAMS), /* Resource Free Priority */ RS_FREE_PRIORITY_DEFAULT, - /* Flags */ RS_FLAGS_ACQUIRE_GPUS_LOCK_ON_FREE | RS_FLAGS_ACQUIRE_RO_API_LOCK_ON_ALLOC, + /* Flags */ RS_FLAGS_ALLOC_NON_PRIVILEGED | RS_FLAGS_ACQUIRE_GPUS_LOCK_ON_FREE | RS_FLAGS_ACQUIRE_RO_API_LOCK_ON_ALLOC, /* Required Access Rights */ RS_ACCESS_NONE ) RS_ENTRY( @@ -459,7 +479,7 @@ /* Parents */ RS_LIST(classId(Device)), /* Alloc Param Info */ RS_REQUIRED(NV_OS_DESC_MEMORY_ALLOCATION_PARAMS), /* Resource Free Priority */ RS_FREE_PRIORITY_DEFAULT, - /* Flags */ RS_FLAGS_ACQUIRE_GPU_GROUP_LOCK | RS_FLAGS_ACQUIRE_RO_API_LOCK_ON_ALLOC, + /* Flags */ RS_FLAGS_ALLOC_NON_PRIVILEGED | RS_FLAGS_ACQUIRE_GPU_GROUP_LOCK | RS_FLAGS_ACQUIRE_RO_API_LOCK_ON_ALLOC, /* Required Access Rights */ RS_ACCESS_NONE ) RS_ENTRY( @@ -469,7 +489,7 @@ /* Parents */ RS_LIST(classId(RmClientResource)), /* Alloc Param Info */ RS_REQUIRED(NV_MEMORY_ALLOCATION_PARAMS), /* Resource Free Priority */ RS_FREE_PRIORITY_DEFAULT, - /* Flags */ RS_FLAGS_NONE, + /* Flags */ RS_FLAGS_ALLOC_NON_PRIVILEGED, /* Required Access Rights */ RS_ACCESS_NONE ) RS_ENTRY( @@ -479,7 +499,7 @@ /* Parents */ RS_LIST(classId(Device)), /* Alloc Param Info */ RS_NONE, /* Resource Free Priority */ RS_FREE_PRIORITY_DEFAULT, - /* Flags */ RS_FLAGS_ACQUIRE_GPUS_LOCK, + /* Flags */ RS_FLAGS_ALLOC_PRIVILEGED | RS_FLAGS_ACQUIRE_GPUS_LOCK, /* Required Access Rights */ RS_ACCESS_NONE ) RS_ENTRY( @@ -489,7 +509,7 @@ /* Parents */ RS_LIST(classId(Device), classId(Subdevice)), /* Alloc Param Info */ RS_REQUIRED(NV_MEMORY_HW_RESOURCES_ALLOCATION_PARAMS), /* Resource Free Priority */ RS_FREE_PRIORITY_DEFAULT, - /* Flags */ RS_FLAGS_ACQUIRE_GPU_GROUP_LOCK, + /* Flags */ RS_FLAGS_ALLOC_NON_PRIVILEGED | RS_FLAGS_ACQUIRE_GPU_GROUP_LOCK, /* Required Access Rights */ RS_ACCESS_NONE ) RS_ENTRY( @@ -499,7 +519,7 @@ /* Parents */ RS_LIST(classId(Device), classId(Subdevice)), /* Alloc Param Info */ RS_REQUIRED(NV_MEMORY_LIST_ALLOCATION_PARAMS), /* Resource Free Priority */ RS_FREE_PRIORITY_DEFAULT, - /* Flags */ RS_FLAGS_ACQUIRE_GPUS_LOCK, + /* Flags */ RS_FLAGS_ALLOC_PRIVILEGED | RS_FLAGS_ACQUIRE_GPUS_LOCK, /* Required Access Rights */ RS_ACCESS_NONE ) RS_ENTRY( @@ -509,7 +529,7 @@ /* Parents */ RS_LIST(classId(Device), classId(Subdevice)), /* Alloc Param Info */ RS_REQUIRED(NV_MEMORY_LIST_ALLOCATION_PARAMS), /* Resource Free Priority */ RS_FREE_PRIORITY_DEFAULT, - /* Flags */ RS_FLAGS_ACQUIRE_GPUS_LOCK, + /* Flags */ RS_FLAGS_ALLOC_PRIVILEGED | RS_FLAGS_ACQUIRE_GPUS_LOCK, /* Required Access Rights */ RS_ACCESS_NONE ) RS_ENTRY( @@ -519,7 +539,7 @@ /* Parents */ RS_LIST(classId(Device), classId(Subdevice)), /* Alloc Param Info */ RS_REQUIRED(NV_MEMORY_LIST_ALLOCATION_PARAMS), /* Resource Free Priority */ RS_FREE_PRIORITY_DEFAULT, - /* Flags */ RS_FLAGS_ACQUIRE_GPUS_LOCK, + /* Flags */ RS_FLAGS_ALLOC_PRIVILEGED | RS_FLAGS_ACQUIRE_GPUS_LOCK, /* Required Access Rights */ RS_ACCESS_NONE ) RS_ENTRY( @@ -529,7 +549,7 @@ /* Parents */ RS_LIST(classId(Device)), /* Alloc Param Info */ RS_REQUIRED(NV_FLA_MEMORY_ALLOCATION_PARAMS), /* Resource Free Priority */ RS_FREE_PRIORITY_DEFAULT, - /* Flags */ RS_FLAGS_ACQUIRE_GPUS_LOCK, + /* Flags */ RS_FLAGS_ALLOC_NON_PRIVILEGED | RS_FLAGS_ACQUIRE_GPUS_LOCK, /* Required Access Rights */ RS_ACCESS_NONE ) RS_ENTRY( @@ -539,7 +559,7 @@ /* Parents */ RS_LIST(classId(Subdevice)), /* Alloc Param Info */ RS_REQUIRED(NV00F8_ALLOCATION_PARAMETERS), /* Resource Free Priority */ RS_FREE_PRIORITY_DEFAULT, - /* Flags */ RS_FLAGS_ACQUIRE_GPUS_LOCK | RS_FLAGS_ACQUIRE_RO_API_LOCK_ON_ALLOC, + /* Flags */ RS_FLAGS_ALLOC_NON_PRIVILEGED | RS_FLAGS_ACQUIRE_GPUS_LOCK | RS_FLAGS_ACQUIRE_RO_API_LOCK_ON_ALLOC, /* Required Access Rights */ RS_ACCESS_NONE ) RS_ENTRY( @@ -549,7 +569,7 @@ /* Parents */ RS_LIST(classId(Device), classId(Subdevice)), /* Alloc Param Info */ RS_REQUIRED(NV_VASPACE_ALLOCATION_PARAMETERS), /* Resource Free Priority */ RS_FREE_PRIORITY_DEFAULT, - /* Flags */ RS_FLAGS_ACQUIRE_GPUS_LOCK_ON_FREE | RS_FLAGS_ACQUIRE_RO_API_LOCK_ON_ALLOC, + /* Flags */ RS_FLAGS_ALLOC_NON_PRIVILEGED | RS_FLAGS_ACQUIRE_GPUS_LOCK_ON_FREE | RS_FLAGS_ACQUIRE_RO_API_LOCK_ON_ALLOC, /* Required Access Rights */ RS_ACCESS_NONE ) RS_ENTRY( @@ -559,7 +579,7 @@ /* Parents */ RS_LIST(classId(RmClientResource)), /* Alloc Param Info */ RS_REQUIRED(NV00FD_ALLOCATION_PARAMETERS), /* Resource Free Priority */ RS_FREE_PRIORITY_DEFAULT, - /* Flags */ RS_FLAGS_ACQUIRE_RO_API_LOCK_ON_ALLOC, + /* Flags */ RS_FLAGS_ALLOC_NON_PRIVILEGED | RS_FLAGS_ACQUIRE_GPUS_LOCK_ON_FREE | RS_FLAGS_ACQUIRE_RO_API_LOCK_ON_ALLOC, /* Required Access Rights */ RS_ACCESS_NONE ) /* Subdevice Children: */ @@ -570,7 +590,7 @@ /* Parents */ RS_LIST(classId(Subdevice)), /* Alloc Param Info */ RS_NONE, /* Resource Free Priority */ RS_FREE_PRIORITY_DEFAULT, - /* Flags */ RS_FLAGS_ACQUIRE_GPUS_LOCK, + /* Flags */ RS_FLAGS_ALLOC_NON_PRIVILEGED | RS_FLAGS_ACQUIRE_GPUS_LOCK, /* Required Access Rights */ RS_ACCESS_NONE ) RS_ENTRY( @@ -580,7 +600,7 @@ /* Parents */ RS_LIST(classId(Subdevice)), /* Alloc Param Info */ RS_REQUIRED(NVA084_ALLOC_PARAMETERS), /* Resource Free Priority */ RS_FREE_PRIORITY_DEFAULT, - /* Flags */ RS_FLAGS_ACQUIRE_GPUS_LOCK, + /* Flags */ RS_FLAGS_ALLOC_NON_PRIVILEGED | RS_FLAGS_ACQUIRE_GPUS_LOCK, /* Required Access Rights */ RS_ACCESS_NONE ) RS_ENTRY( @@ -590,7 +610,7 @@ /* Parents */ RS_LIST(classId(Subdevice)), /* Alloc Param Info */ RS_OPTIONAL(NV503C_ALLOC_PARAMETERS), /* Resource Free Priority */ RS_FREE_PRIORITY_DEFAULT, - /* Flags */ RS_FLAGS_ACQUIRE_GPUS_LOCK | RS_FLAGS_ACQUIRE_RO_API_LOCK_ON_ALLOC, + /* Flags */ RS_FLAGS_ALLOC_NON_PRIVILEGED | RS_FLAGS_ACQUIRE_GPUS_LOCK | RS_FLAGS_ACQUIRE_RO_API_LOCK_ON_ALLOC, /* Required Access Rights */ RS_ACCESS_NONE ) RS_ENTRY( @@ -600,7 +620,17 @@ /* Parents */ RS_LIST(classId(Subdevice)), /* Alloc Param Info */ RS_NONE, /* Resource Free Priority */ RS_FREE_PRIORITY_DEFAULT, - /* Flags */ RS_FLAGS_CHANNEL_DESCENDANT_COMMON | RS_FLAGS_ACQUIRE_RO_API_LOCK_ON_ALLOC, + /* Flags */ RS_FLAGS_ALLOC_NON_PRIVILEGED | RS_FLAGS_CHANNEL_DESCENDANT_COMMON | RS_FLAGS_ACQUIRE_RO_API_LOCK_ON_ALLOC, + /* Required Access Rights */ RS_ACCESS_NONE +) +RS_ENTRY( + /* External Class */ GF100_SUBDEVICE_INFOROM, + /* Internal Class */ GenericEngineApi, + /* Multi-Instance */ NV_TRUE, + /* Parents */ RS_LIST(classId(Subdevice)), + /* Alloc Param Info */ RS_NONE, + /* Resource Free Priority */ RS_FREE_PRIORITY_DEFAULT, + /* Flags */ RS_FLAGS_ALLOC_NON_PRIVILEGED | RS_FLAGS_ACQUIRE_GPUS_LOCK | RS_FLAGS_ACQUIRE_RO_API_LOCK_ON_ALLOC | RS_FLAGS_ALLOC_RPC_TO_PHYS_RM, /* Required Access Rights */ RS_ACCESS_NONE ) RS_ENTRY( @@ -610,7 +640,7 @@ /* Parents */ RS_LIST(classId(Subdevice)), /* Alloc Param Info */ RS_NONE, /* Resource Free Priority */ RS_FREE_PRIORITY_DEFAULT, - /* Flags */ RS_FLAGS_ACQUIRE_GPUS_LOCK, + /* Flags */ RS_FLAGS_ALLOC_NON_PRIVILEGED | RS_FLAGS_ACQUIRE_GPUS_LOCK, /* Required Access Rights */ RS_ACCESS_NONE ) RS_ENTRY( @@ -620,7 +650,7 @@ /* Parents */ RS_LIST(classId(Subdevice)), /* Alloc Param Info */ RS_NONE, /* Resource Free Priority */ RS_FREE_PRIORITY_DEFAULT, - /* Flags */ RS_FLAGS_ACQUIRE_GPUS_LOCK | RS_FLAGS_ALLOC_RPC_TO_PHYS_RM, + /* Flags */ RS_FLAGS_ALLOC_NON_PRIVILEGED | RS_FLAGS_ACQUIRE_GPUS_LOCK | RS_FLAGS_ALLOC_RPC_TO_PHYS_RM, /* Required Access Rights */ RS_ACCESS_NONE ) RS_ENTRY( @@ -630,7 +660,7 @@ /* Parents */ RS_LIST(classId(Subdevice)), /* Alloc Param Info */ RS_NONE, /* Resource Free Priority */ RS_FREE_PRIORITY_DEFAULT, - /* Flags */ RS_FLAGS_ACQUIRE_GPUS_LOCK | RS_FLAGS_ALLOC_RPC_TO_ALL, + /* Flags */ RS_FLAGS_ALLOC_NON_PRIVILEGED | RS_FLAGS_ACQUIRE_GPUS_LOCK | RS_FLAGS_ALLOC_RPC_TO_ALL, /* Required Access Rights */ RS_ACCESS_NONE ) RS_ENTRY( @@ -640,7 +670,7 @@ /* Parents */ RS_LIST(classId(Subdevice)), /* Alloc Param Info */ RS_NONE, /* Resource Free Priority */ RS_FREE_PRIORITY_DEFAULT, - /* Flags */ RS_FLAGS_ACQUIRE_GPUS_LOCK | RS_FLAGS_ALLOC_RPC_TO_ALL, + /* Flags */ RS_FLAGS_ALLOC_NON_PRIVILEGED | RS_FLAGS_ACQUIRE_GPUS_LOCK | RS_FLAGS_ALLOC_RPC_TO_ALL, /* Required Access Rights */ RS_ACCESS_NONE ) RS_ENTRY( @@ -650,7 +680,7 @@ /* Parents */ RS_LIST(classId(Subdevice)), /* Alloc Param Info */ RS_REQUIRED(NV00DB_ALLOCATION_PARAMETERS), /* Resource Free Priority */ RS_FREE_PRIORITY_DEFAULT, - /* Flags */ RS_FLAGS_ACQUIRE_GPUS_LOCK, + /* Flags */ RS_FLAGS_ALLOC_NON_PRIVILEGED | RS_FLAGS_ACQUIRE_GPUS_LOCK, /* Required Access Rights */ RS_ACCESS_NONE ) RS_ENTRY( @@ -660,7 +690,7 @@ /* Parents */ RS_LIST(classId(Subdevice)), /* Alloc Param Info */ RS_REQUIRED(NV00DE_ALLOC_PARAMETERS), /* Resource Free Priority */ RS_FREE_PRIORITY_DEFAULT, - /* Flags */ RS_FLAGS_ACQUIRE_GPU_GROUP_LOCK, + /* Flags */ RS_FLAGS_ALLOC_NON_PRIVILEGED | RS_FLAGS_ACQUIRE_GPU_GROUP_LOCK, /* Required Access Rights */ RS_ACCESS_NONE ) RS_ENTRY( @@ -670,7 +700,7 @@ /* Parents */ RS_LIST(classId(Subdevice)), /* Alloc Param Info */ RS_NONE, /* Resource Free Priority */ RS_FREE_PRIORITY_DEFAULT, - /* Flags */ RS_FLAGS_ACQUIRE_GPUS_LOCK, + /* Flags */ RS_FLAGS_ALLOC_NON_PRIVILEGED | RS_FLAGS_ACQUIRE_GPUS_LOCK, /* Required Access Rights */ RS_ACCESS_NONE ) RS_ENTRY( @@ -680,7 +710,7 @@ /* Parents */ RS_LIST(classId(Subdevice)), /* Alloc Param Info */ RS_NONE, /* Resource Free Priority */ RS_FREE_PRIORITY_DEFAULT, - /* Flags */ RS_FLAGS_ACQUIRE_GPUS_LOCK, + /* Flags */ RS_FLAGS_ALLOC_NON_PRIVILEGED | RS_FLAGS_ACQUIRE_GPUS_LOCK, /* Required Access Rights */ RS_ACCESS_NONE ) RS_ENTRY( @@ -690,7 +720,7 @@ /* Parents */ RS_LIST(classId(Subdevice)), /* Alloc Param Info */ RS_NONE, /* Resource Free Priority */ RS_FREE_PRIORITY_DEFAULT, - /* Flags */ RS_FLAGS_ACQUIRE_GPUS_LOCK, + /* Flags */ RS_FLAGS_ALLOC_NON_PRIVILEGED | RS_FLAGS_ACQUIRE_GPUS_LOCK, /* Required Access Rights */ RS_ACCESS_NONE ) RS_ENTRY( @@ -700,7 +730,7 @@ /* Parents */ RS_LIST(classId(Subdevice)), /* Alloc Param Info */ RS_OPTIONAL(NV_HOPPER_USERMODE_A_PARAMS), /* Resource Free Priority */ RS_FREE_PRIORITY_DEFAULT, - /* Flags */ RS_FLAGS_ACQUIRE_GPUS_LOCK, + /* Flags */ RS_FLAGS_ALLOC_NON_PRIVILEGED | RS_FLAGS_ACQUIRE_GPUS_LOCK, /* Required Access Rights */ RS_ACCESS_NONE ) RS_ENTRY( @@ -710,7 +740,7 @@ /* Parents */ RS_LIST(classId(Subdevice)), /* Alloc Param Info */ RS_NONE, /* Resource Free Priority */ RS_FREE_PRIORITY_DEFAULT, - /* Flags */ RS_FLAGS_ACQUIRE_GPUS_LOCK, + /* Flags */ RS_FLAGS_ALLOC_PRIVILEGED | RS_FLAGS_ACQUIRE_GPUS_LOCK, /* Required Access Rights */ RS_ACCESS_NONE ) RS_ENTRY( @@ -720,7 +750,7 @@ /* Parents */ RS_LIST(classId(Subdevice)), /* Alloc Param Info */ RS_NONE, /* Resource Free Priority */ RS_FREE_PRIORITY_DEFAULT, - /* Flags */ RS_FLAGS_ACQUIRE_GPUS_LOCK, + /* Flags */ RS_FLAGS_ALLOC_PRIVILEGED | RS_FLAGS_ACQUIRE_GPUS_LOCK, /* Required Access Rights */ RS_ACCESS_NONE ) RS_ENTRY( @@ -730,7 +760,7 @@ /* Parents */ RS_LIST(classId(Subdevice)), /* Alloc Param Info */ RS_NONE, /* Resource Free Priority */ RS_FREE_PRIORITY_DEFAULT, - /* Flags */ RS_FLAGS_ACQUIRE_GPUS_LOCK, + /* Flags */ RS_FLAGS_ALLOC_PRIVILEGED | RS_FLAGS_ACQUIRE_GPUS_LOCK, /* Required Access Rights */ RS_ACCESS_NONE ) RS_ENTRY( @@ -740,17 +770,27 @@ /* Parents */ RS_LIST(classId(Subdevice)), /* Alloc Param Info */ RS_NONE, /* Resource Free Priority */ RS_FREE_PRIORITY_DEFAULT, - /* Flags */ RS_FLAGS_ACQUIRE_GPUS_LOCK | RS_FLAGS_ACQUIRE_RO_API_LOCK_ON_ALLOC, + /* Flags */ RS_FLAGS_ALLOC_KERNEL_PRIVILEGED | RS_FLAGS_ACQUIRE_GPUS_LOCK | RS_FLAGS_ACQUIRE_RO_API_LOCK_ON_ALLOC, /* Required Access Rights */ RS_ACCESS_NONE ) RS_ENTRY( /* External Class */ ACCESS_COUNTER_NOTIFY_BUFFER, /* Internal Class */ AccessCounterBuffer, + /* Multi-Instance */ NV_TRUE, + /* Parents */ RS_LIST(classId(Subdevice)), + /* Alloc Param Info */ RS_REQUIRED(NV_ACCESS_COUNTER_NOTIFY_BUFFER_ALLOC_PARAMS), + /* Resource Free Priority */ RS_FREE_PRIORITY_DEFAULT, + /* Flags */ RS_FLAGS_ALLOC_NON_PRIVILEGED | RS_FLAGS_ACQUIRE_GPUS_LOCK, + /* Required Access Rights */ RS_ACCESS_NONE +) +RS_ENTRY( + /* External Class */ MMU_VIDMEM_ACCESS_BIT_BUFFER, + /* Internal Class */ VidmemAccessBitBuffer, /* Multi-Instance */ NV_FALSE, /* Parents */ RS_LIST(classId(Subdevice)), - /* Alloc Param Info */ RS_NONE, + /* Alloc Param Info */ RS_REQUIRED(NV_VIDMEM_ACCESS_BIT_ALLOCATION_PARAMS), /* Resource Free Priority */ RS_FREE_PRIORITY_DEFAULT, - /* Flags */ RS_FLAGS_ACQUIRE_GPUS_LOCK, + /* Flags */ RS_FLAGS_ALLOC_PRIVILEGED | RS_FLAGS_ACQUIRE_GPUS_LOCK | RS_FLAGS_ALLOC_RPC_TO_PHYS_RM, /* Required Access Rights */ RS_ACCESS_NONE ) RS_ENTRY( @@ -760,7 +800,7 @@ /* Parents */ RS_LIST(classId(Subdevice)), /* Alloc Param Info */ RS_REQUIRED(NVC637_ALLOCATION_PARAMETERS), /* Resource Free Priority */ RS_FREE_PRIORITY_DEFAULT, - /* Flags */ RS_FLAGS_ACQUIRE_GPUS_LOCK | RS_FLAGS_ALLOC_RPC_TO_ALL, + /* Flags */ RS_FLAGS_ALLOC_NON_PRIVILEGED | RS_FLAGS_ACQUIRE_GPUS_LOCK | RS_FLAGS_ALLOC_RPC_TO_ALL, /* Required Access Rights */ RS_ACCESS_NONE ) RS_ENTRY( @@ -770,7 +810,7 @@ /* Parents */ RS_LIST(classId(GPUInstanceSubscription)), /* Alloc Param Info */ RS_REQUIRED(NVC638_ALLOCATION_PARAMETERS), /* Resource Free Priority */ RS_FREE_PRIORITY_DEFAULT, - /* Flags */ RS_FLAGS_ACQUIRE_GPUS_LOCK | RS_FLAGS_ALLOC_RPC_TO_ALL, + /* Flags */ RS_FLAGS_ALLOC_NON_PRIVILEGED | RS_FLAGS_ACQUIRE_GPUS_LOCK | RS_FLAGS_ALLOC_RPC_TO_ALL, /* Required Access Rights */ RS_ACCESS_NONE ) RS_ENTRY( @@ -780,7 +820,7 @@ /* Parents */ RS_LIST(classId(RmClientResource)), /* Alloc Param Info */ RS_REQUIRED(NVC639_ALLOCATION_PARAMETERS), /* Resource Free Priority */ RS_FREE_PRIORITY_DEFAULT, - /* Flags */ RS_FLAGS_NONE, + /* Flags */ RS_FLAGS_ALLOC_NON_PRIVILEGED, /* Required Access Rights */ RS_ACCESS_NONE ) RS_ENTRY( @@ -790,7 +830,7 @@ /* Parents */ RS_LIST(classId(RmClientResource)), /* Alloc Param Info */ RS_REQUIRED(NVC640_ALLOCATION_PARAMETERS), /* Resource Free Priority */ RS_FREE_PRIORITY_DEFAULT, - /* Flags */ RS_FLAGS_NONE, + /* Flags */ RS_FLAGS_ALLOC_NON_PRIVILEGED, /* Required Access Rights */ RS_ACCESS_NONE ) /* Display classes: */ @@ -801,7 +841,7 @@ /* Parents */ RS_LIST(classId(Device)), /* Alloc Param Info */ RS_NONE, /* Resource Free Priority */ RS_FREE_PRIORITY_DEFAULT, - /* Flags */ RS_FLAGS_ACQUIRE_GPUS_LOCK | RS_FLAGS_ALLOC_RPC_TO_ALL, + /* Flags */ RS_FLAGS_ALLOC_PRIVILEGED | RS_FLAGS_ACQUIRE_GPUS_LOCK | RS_FLAGS_ALLOC_RPC_TO_ALL, /* Required Access Rights */ RS_ACCESS_NONE ) RS_ENTRY( @@ -811,7 +851,7 @@ /* Parents */ RS_LIST(classId(Device)), /* Alloc Param Info */ RS_NONE, /* Resource Free Priority */ RS_FREE_PRIORITY_DEFAULT, - /* Flags */ RS_FLAGS_ACQUIRE_GPUS_LOCK | RS_FLAGS_ALLOC_RPC_TO_ALL, + /* Flags */ RS_FLAGS_ALLOC_PRIVILEGED | RS_FLAGS_ACQUIRE_GPUS_LOCK | RS_FLAGS_ALLOC_RPC_TO_ALL, /* Required Access Rights */ RS_ACCESS_NONE ) RS_ENTRY( @@ -821,7 +861,7 @@ /* Parents */ RS_LIST(classId(Device)), /* Alloc Param Info */ RS_NONE, /* Resource Free Priority */ RS_FREE_PRIORITY_DEFAULT, - /* Flags */ RS_FLAGS_ACQUIRE_GPUS_LOCK | RS_FLAGS_ALLOC_RPC_TO_ALL, + /* Flags */ RS_FLAGS_ALLOC_PRIVILEGED | RS_FLAGS_ACQUIRE_GPUS_LOCK | RS_FLAGS_ALLOC_RPC_TO_ALL, /* Required Access Rights */ RS_ACCESS_NONE ) RS_ENTRY( @@ -831,7 +871,7 @@ /* Parents */ RS_LIST(classId(Device)), /* Alloc Param Info */ RS_NONE, /* Resource Free Priority */ RS_FREE_PRIORITY_DEFAULT, - /* Flags */ RS_FLAGS_ALLOC_RPC_TO_ALL, + /* Flags */ RS_FLAGS_ALLOC_PRIVILEGED | RS_FLAGS_ALLOC_RPC_TO_ALL, /* Required Access Rights */ RS_ACCESS_NONE ) RS_ENTRY( @@ -841,7 +881,7 @@ /* Parents */ RS_LIST(classId(Device)), /* Alloc Param Info */ RS_NONE, /* Resource Free Priority */ RS_FREE_PRIORITY_DEFAULT, - /* Flags */ RS_FLAGS_ACQUIRE_GPUS_LOCK_ON_FREE | RS_FLAGS_ALLOC_RPC_TO_ALL, + /* Flags */ RS_FLAGS_ALLOC_NON_PRIVILEGED | RS_FLAGS_ACQUIRE_GPUS_LOCK_ON_FREE | RS_FLAGS_ALLOC_RPC_TO_ALL, /* Required Access Rights */ RS_ACCESS_NONE ) RS_ENTRY( @@ -851,7 +891,7 @@ /* Parents */ RS_LIST(classId(Device), classId(Subdevice)), /* Alloc Param Info */ RS_REQUIRED(NV_VBLANK_CALLBACK_ALLOCATION_PARAMETERS), /* Resource Free Priority */ RS_FREE_PRIORITY_DEFAULT, - /* Flags */ RS_FLAGS_ACQUIRE_GPUS_LOCK, + /* Flags */ RS_FLAGS_ALLOC_KERNEL_PRIVILEGED | RS_FLAGS_ACQUIRE_GPUS_LOCK, /* Required Access Rights */ RS_ACCESS_NONE ) RS_ENTRY( @@ -861,7 +901,7 @@ /* Parents */ RS_LIST(classId(DispCommon)), /* Alloc Param Info */ RS_REQUIRED(NV0092_RG_LINE_CALLBACK_ALLOCATION_PARAMETERS), /* Resource Free Priority */ RS_FREE_PRIORITY_DEFAULT, - /* Flags */ RS_FLAGS_ACQUIRE_GPUS_LOCK, + /* Flags */ RS_FLAGS_ALLOC_KERNEL_PRIVILEGED | RS_FLAGS_ACQUIRE_GPUS_LOCK, /* Required Access Rights */ RS_ACCESS_NONE ) RS_ENTRY( @@ -871,7 +911,7 @@ /* Parents */ RS_LIST(classId(NvDispApi)), /* Alloc Param Info */ RS_REQUIRED(NV50VAIO_CHANNELPIO_ALLOCATION_PARAMETERS), /* Resource Free Priority */ RS_FREE_PRIORITY_DEFAULT, - /* Flags */ RS_FLAGS_ACQUIRE_GPUS_LOCK | RS_FLAGS_ALLOC_RPC_TO_ALL, + /* Flags */ RS_FLAGS_ALLOC_PRIVILEGED | RS_FLAGS_ACQUIRE_GPUS_LOCK | RS_FLAGS_ALLOC_RPC_TO_ALL, /* Required Access Rights */ RS_ACCESS_NONE ) RS_ENTRY( @@ -881,7 +921,7 @@ /* Parents */ RS_LIST(classId(NvDispApi)), /* Alloc Param Info */ RS_REQUIRED(NV50VAIO_CHANNELPIO_ALLOCATION_PARAMETERS), /* Resource Free Priority */ RS_FREE_PRIORITY_DEFAULT, - /* Flags */ RS_FLAGS_ACQUIRE_GPUS_LOCK | RS_FLAGS_ALLOC_RPC_TO_ALL, + /* Flags */ RS_FLAGS_ALLOC_PRIVILEGED | RS_FLAGS_ACQUIRE_GPUS_LOCK | RS_FLAGS_ALLOC_RPC_TO_ALL, /* Required Access Rights */ RS_ACCESS_NONE ) RS_ENTRY( @@ -891,7 +931,7 @@ /* Parents */ RS_LIST(classId(NvDispApi)), /* Alloc Param Info */ RS_REQUIRED(NV50VAIO_CHANNELDMA_ALLOCATION_PARAMETERS), /* Resource Free Priority */ RS_FREE_PRIORITY_DEFAULT, - /* Flags */ RS_FLAGS_ACQUIRE_GPUS_LOCK | RS_FLAGS_ALLOC_RPC_TO_ALL, + /* Flags */ RS_FLAGS_ALLOC_PRIVILEGED | RS_FLAGS_ACQUIRE_GPUS_LOCK | RS_FLAGS_ALLOC_RPC_TO_ALL, /* Required Access Rights */ RS_ACCESS_NONE ) RS_ENTRY( @@ -901,7 +941,7 @@ /* Parents */ RS_LIST(classId(NvDispApi)), /* Alloc Param Info */ RS_REQUIRED(NV50VAIO_CHANNELDMA_ALLOCATION_PARAMETERS), /* Resource Free Priority */ RS_FREE_PRIORITY_DEFAULT, - /* Flags */ RS_FLAGS_ACQUIRE_GPUS_LOCK | RS_FLAGS_ALLOC_RPC_TO_ALL, + /* Flags */ RS_FLAGS_ALLOC_PRIVILEGED | RS_FLAGS_ACQUIRE_GPUS_LOCK | RS_FLAGS_ALLOC_RPC_TO_ALL, /* Required Access Rights */ RS_ACCESS_NONE ) RS_ENTRY( @@ -911,7 +951,7 @@ /* Parents */ RS_LIST(classId(NvDispApi)), /* Alloc Param Info */ RS_REQUIRED(NV50VAIO_CHANNELDMA_ALLOCATION_PARAMETERS), /* Resource Free Priority */ RS_FREE_PRIORITY_DEFAULT, - /* Flags */ RS_FLAGS_ACQUIRE_GPUS_LOCK | RS_FLAGS_ALLOC_RPC_TO_ALL, + /* Flags */ RS_FLAGS_ALLOC_PRIVILEGED | RS_FLAGS_ACQUIRE_GPUS_LOCK | RS_FLAGS_ALLOC_RPC_TO_ALL, /* Required Access Rights */ RS_ACCESS_NONE ) RS_ENTRY( @@ -921,7 +961,7 @@ /* Parents */ RS_LIST(classId(NvDispApi)), /* Alloc Param Info */ RS_NONE, /* Resource Free Priority */ RS_FREE_PRIORITY_DEFAULT, - /* Flags */ RS_FLAGS_ACQUIRE_GPUS_LOCK, + /* Flags */ RS_FLAGS_ALLOC_PRIVILEGED | RS_FLAGS_ACQUIRE_GPUS_LOCK, /* Required Access Rights */ RS_ACCESS_NONE ) RS_ENTRY( @@ -931,7 +971,7 @@ /* Parents */ RS_LIST(classId(NvDispApi)), /* Alloc Param Info */ RS_REQUIRED(NV50VAIO_CHANNELDMA_ALLOCATION_PARAMETERS), /* Resource Free Priority */ RS_FREE_PRIORITY_DEFAULT, - /* Flags */ RS_FLAGS_ACQUIRE_GPUS_LOCK | RS_FLAGS_ALLOC_RPC_TO_ALL, + /* Flags */ RS_FLAGS_ALLOC_PRIVILEGED | RS_FLAGS_ACQUIRE_GPUS_LOCK | RS_FLAGS_ALLOC_RPC_TO_ALL, /* Required Access Rights */ RS_ACCESS_NONE ) RS_ENTRY( @@ -941,10 +981,19 @@ /* Parents */ RS_LIST(classId(NvDispApi)), /* Alloc Param Info */ RS_REQUIRED(NV50VAIO_CHANNELDMA_ALLOCATION_PARAMETERS), /* Resource Free Priority */ RS_FREE_PRIORITY_DEFAULT, - /* Flags */ RS_FLAGS_ACQUIRE_GPUS_LOCK | RS_FLAGS_ALLOC_RPC_TO_ALL, + /* Flags */ RS_FLAGS_ALLOC_PRIVILEGED | RS_FLAGS_ACQUIRE_GPUS_LOCK | RS_FLAGS_ALLOC_RPC_TO_ALL, + /* Required Access Rights */ RS_ACCESS_NONE +) +RS_ENTRY( + /* External Class */ NVC77D_CORE_CHANNEL_DMA, + /* Internal Class */ DispChannelDma, + /* Multi-Instance */ NV_TRUE, + /* Parents */ RS_LIST(classId(NvDispApi)), + /* Alloc Param Info */ RS_REQUIRED(NV50VAIO_CHANNELDMA_ALLOCATION_PARAMETERS), + /* Resource Free Priority */ RS_FREE_PRIORITY_DEFAULT, + /* Flags */ RS_FLAGS_ALLOC_PRIVILEGED | RS_FLAGS_ACQUIRE_GPUS_LOCK | RS_FLAGS_ALLOC_RPC_TO_ALL, /* Required Access Rights */ RS_ACCESS_NONE ) - RS_ENTRY( NVC77D_CORE_CHANNEL_DMA, DispChannelDma, NV_TRUE, RS_LIST(classId(NvDispApi)), RS_REQUIRED(NV50VAIO_CHANNELDMA_ALLOCATION_PARAMETERS), RS_FREE_PRIORITY_DEFAULT, RS_FLAGS_ACQUIRE_GPUS_LOCK | RS_FLAGS_ALLOC_RPC_TO_ALL, RS_ACCESS_NONE ) RS_ENTRY( /* External Class */ NVC77F_ANY_CHANNEL_DMA, /* Internal Class */ DispChannelDma, @@ -952,7 +1001,7 @@ /* Parents */ RS_LIST(classId(NvDispApi)), /* Alloc Param Info */ RS_REQUIRED(NV50VAIO_CHANNELDMA_ALLOCATION_PARAMETERS), /* Resource Free Priority */ RS_FREE_PRIORITY_DEFAULT, - /* Flags */ RS_FLAGS_ACQUIRE_GPUS_LOCK, + /* Flags */ RS_FLAGS_ALLOC_PRIVILEGED | RS_FLAGS_ACQUIRE_GPUS_LOCK, /* Required Access Rights */ RS_ACCESS_NONE ) RS_ENTRY( @@ -962,7 +1011,7 @@ /* Parents */ RS_LIST(classId(NvDispApi)), /* Alloc Param Info */ RS_REQUIRED(NV50VAIO_CHANNELDMA_ALLOCATION_PARAMETERS), /* Resource Free Priority */ RS_FREE_PRIORITY_DEFAULT, - /* Flags */ RS_FLAGS_ACQUIRE_GPUS_LOCK | RS_FLAGS_ALLOC_RPC_TO_ALL, + /* Flags */ RS_FLAGS_ALLOC_PRIVILEGED | RS_FLAGS_ACQUIRE_GPUS_LOCK | RS_FLAGS_ALLOC_RPC_TO_ALL, /* Required Access Rights */ RS_ACCESS_NONE ) RS_ENTRY( @@ -972,7 +1021,7 @@ /* Parents */ RS_LIST(classId(NvDispApi)), /* Alloc Param Info */ RS_NONE, /* Resource Free Priority */ RS_FREE_PRIORITY_DEFAULT, - /* Flags */ RS_FLAGS_ACQUIRE_GPUS_LOCK, + /* Flags */ RS_FLAGS_ALLOC_PRIVILEGED | RS_FLAGS_ACQUIRE_GPUS_LOCK, /* Required Access Rights */ RS_ACCESS_NONE ) RS_ENTRY( @@ -982,7 +1031,7 @@ /* Parents */ RS_LIST(classId(NvDispApi)), /* Alloc Param Info */ RS_NONE, /* Resource Free Priority */ RS_FREE_PRIORITY_DEFAULT, - /* Flags */ RS_FLAGS_ACQUIRE_GPUS_LOCK, + /* Flags */ RS_FLAGS_ALLOC_PRIVILEGED | RS_FLAGS_ACQUIRE_GPUS_LOCK, /* Required Access Rights */ RS_ACCESS_NONE ) /* Classes allocated under channel: */ @@ -993,7 +1042,7 @@ /* Parents */ RS_LIST(classId(KernelChannel)), /* Alloc Param Info */ RS_REQUIRED(NV9072_ALLOCATION_PARAMETERS), /* Resource Free Priority */ RS_FREE_PRIORITY_DEFAULT, - /* Flags */ RS_FLAGS_CHANNEL_DESCENDANT_COMMON| RS_FLAGS_ALLOC_RPC_TO_ALL, + /* Flags */ RS_FLAGS_ALLOC_NON_PRIVILEGED | RS_FLAGS_CHANNEL_DESCENDANT_COMMON | RS_FLAGS_ALLOC_RPC_TO_ALL, /* Required Access Rights */ RS_ACCESS_NONE ) RS_ENTRY( @@ -1003,7 +1052,7 @@ /* Parents */ RS_LIST(classId(KernelChannel)), /* Alloc Param Info */ RS_NONE, /* Resource Free Priority */ RS_FREE_PRIORITY_DEFAULT, - /* Flags */ RS_FLAGS_CHANNEL_DESCENDANT_COMMON, + /* Flags */ RS_FLAGS_ALLOC_NON_PRIVILEGED | RS_FLAGS_CHANNEL_DESCENDANT_COMMON, /* Required Access Rights */ RS_ACCESS_NONE ) RS_ENTRY( @@ -1013,7 +1062,7 @@ /* Parents */ RS_LIST(classId(KernelChannel)), /* Alloc Param Info */ RS_OPTIONAL(NV5080_ALLOC_PARAMS), /* Resource Free Priority */ RS_FREE_PRIORITY_DEFAULT, - /* Flags */ RS_FLAGS_CHANNEL_DESCENDANT_COMMON, + /* Flags */ RS_FLAGS_ALLOC_NON_PRIVILEGED | RS_FLAGS_CHANNEL_DESCENDANT_COMMON, /* Required Access Rights */ RS_ACCESS_NONE ) RS_ENTRY( @@ -1023,7 +1072,7 @@ /* Parents */ RS_LIST(classId(KernelChannel)), /* Alloc Param Info */ RS_NONE, /* Resource Free Priority */ RS_FREE_PRIORITY_DEFAULT, - /* Flags */ RS_FLAGS_CHANNEL_DESCENDANT_COMMON, + /* Flags */ RS_FLAGS_ALLOC_PRIVILEGED | RS_FLAGS_CHANNEL_DESCENDANT_COMMON, /* Required Access Rights */ RS_ACCESS_NONE ) RS_ENTRY( @@ -1033,7 +1082,7 @@ /* Parents */ RS_LIST(classId(KernelChannel)), /* Alloc Param Info */ RS_NONE, /* Resource Free Priority */ RS_FREE_PRIORITY_DEFAULT, - /* Flags */ RS_FLAGS_CHANNEL_DESCENDANT_COMMON, + /* Flags */ RS_FLAGS_ALLOC_NON_PRIVILEGED | RS_FLAGS_CHANNEL_DESCENDANT_COMMON, /* Required Access Rights */ RS_ACCESS_NONE ) RS_ENTRY( @@ -1043,7 +1092,7 @@ /* Parents */ RS_LIST(classId(KernelChannel)), /* Alloc Param Info */ RS_OPTIONAL(NVB0B5_ALLOCATION_PARAMETERS), /* Resource Free Priority */ RS_FREE_PRIORITY_DEFAULT, - /* Flags */ RS_FLAGS_CHANNEL_DESCENDANT_COMMON | RS_FLAGS_ACQUIRE_RO_API_LOCK_ON_ALLOC, + /* Flags */ RS_FLAGS_ALLOC_NON_PRIVILEGED | RS_FLAGS_CHANNEL_DESCENDANT_COMMON | RS_FLAGS_ACQUIRE_RO_API_LOCK_ON_ALLOC, /* Required Access Rights */ RS_ACCESS_NONE ) RS_ENTRY( @@ -1053,7 +1102,7 @@ /* Parents */ RS_LIST(classId(KernelChannel)), /* Alloc Param Info */ RS_OPTIONAL(NVB0B5_ALLOCATION_PARAMETERS), /* Resource Free Priority */ RS_FREE_PRIORITY_DEFAULT, - /* Flags */ RS_FLAGS_CHANNEL_DESCENDANT_COMMON | RS_FLAGS_ACQUIRE_RO_API_LOCK_ON_ALLOC, + /* Flags */ RS_FLAGS_ALLOC_NON_PRIVILEGED | RS_FLAGS_CHANNEL_DESCENDANT_COMMON | RS_FLAGS_ACQUIRE_RO_API_LOCK_ON_ALLOC, /* Required Access Rights */ RS_ACCESS_NONE ) RS_ENTRY( @@ -1063,7 +1112,7 @@ /* Parents */ RS_LIST(classId(KernelChannel)), /* Alloc Param Info */ RS_OPTIONAL(NVB0B5_ALLOCATION_PARAMETERS), /* Resource Free Priority */ RS_FREE_PRIORITY_DEFAULT, - /* Flags */ RS_FLAGS_CHANNEL_DESCENDANT_COMMON | RS_FLAGS_ACQUIRE_RO_API_LOCK_ON_ALLOC, + /* Flags */ RS_FLAGS_ALLOC_NON_PRIVILEGED | RS_FLAGS_CHANNEL_DESCENDANT_COMMON | RS_FLAGS_ACQUIRE_RO_API_LOCK_ON_ALLOC, /* Required Access Rights */ RS_ACCESS_NONE ) RS_ENTRY( @@ -1073,7 +1122,7 @@ /* Parents */ RS_LIST(classId(KernelChannel)), /* Alloc Param Info */ RS_OPTIONAL(NVB0B5_ALLOCATION_PARAMETERS), /* Resource Free Priority */ RS_FREE_PRIORITY_DEFAULT, - /* Flags */ RS_FLAGS_CHANNEL_DESCENDANT_COMMON | RS_FLAGS_ACQUIRE_RO_API_LOCK_ON_ALLOC, + /* Flags */ RS_FLAGS_ALLOC_NON_PRIVILEGED | RS_FLAGS_CHANNEL_DESCENDANT_COMMON | RS_FLAGS_ACQUIRE_RO_API_LOCK_ON_ALLOC, /* Required Access Rights */ RS_ACCESS_NONE ) RS_ENTRY( @@ -1083,7 +1132,7 @@ /* Parents */ RS_LIST(classId(KernelChannel)), /* Alloc Param Info */ RS_OPTIONAL(NVB0B5_ALLOCATION_PARAMETERS), /* Resource Free Priority */ RS_FREE_PRIORITY_DEFAULT, - /* Flags */ RS_FLAGS_CHANNEL_DESCENDANT_COMMON | RS_FLAGS_ACQUIRE_RO_API_LOCK_ON_ALLOC, + /* Flags */ RS_FLAGS_ALLOC_NON_PRIVILEGED | RS_FLAGS_CHANNEL_DESCENDANT_COMMON | RS_FLAGS_ACQUIRE_RO_API_LOCK_ON_ALLOC, /* Required Access Rights */ RS_ACCESS_NONE ) RS_ENTRY( @@ -1093,7 +1142,7 @@ /* Parents */ RS_LIST(classId(KernelChannel)), /* Alloc Param Info */ RS_OPTIONAL(NVB0B5_ALLOCATION_PARAMETERS), /* Resource Free Priority */ RS_FREE_PRIORITY_DEFAULT, - /* Flags */ RS_FLAGS_CHANNEL_DESCENDANT_COMMON | RS_FLAGS_ACQUIRE_RO_API_LOCK_ON_ALLOC, + /* Flags */ RS_FLAGS_ALLOC_NON_PRIVILEGED | RS_FLAGS_CHANNEL_DESCENDANT_COMMON | RS_FLAGS_ACQUIRE_RO_API_LOCK_ON_ALLOC, /* Required Access Rights */ RS_ACCESS_NONE ) RS_ENTRY( @@ -1103,7 +1152,7 @@ /* Parents */ RS_LIST(classId(KernelChannel)), /* Alloc Param Info */ RS_OPTIONAL(NV_BSP_ALLOCATION_PARAMETERS), /* Resource Free Priority */ RS_FREE_PRIORITY_DEFAULT, - /* Flags */ RS_FLAGS_CHANNEL_DESCENDANT_COMMON, + /* Flags */ RS_FLAGS_ALLOC_NON_PRIVILEGED | RS_FLAGS_CHANNEL_DESCENDANT_COMMON, /* Required Access Rights */ RS_ACCESS_NONE ) RS_ENTRY( @@ -1113,7 +1162,7 @@ /* Parents */ RS_LIST(classId(KernelChannel)), /* Alloc Param Info */ RS_OPTIONAL(NV_BSP_ALLOCATION_PARAMETERS), /* Resource Free Priority */ RS_FREE_PRIORITY_DEFAULT, - /* Flags */ RS_FLAGS_CHANNEL_DESCENDANT_COMMON, + /* Flags */ RS_FLAGS_ALLOC_NON_PRIVILEGED | RS_FLAGS_CHANNEL_DESCENDANT_COMMON, /* Required Access Rights */ RS_ACCESS_NONE ) RS_ENTRY( @@ -1123,7 +1172,7 @@ /* Parents */ RS_LIST(classId(KernelChannel)), /* Alloc Param Info */ RS_OPTIONAL(NV_BSP_ALLOCATION_PARAMETERS), /* Resource Free Priority */ RS_FREE_PRIORITY_DEFAULT, - /* Flags */ RS_FLAGS_CHANNEL_DESCENDANT_COMMON, + /* Flags */ RS_FLAGS_ALLOC_NON_PRIVILEGED | RS_FLAGS_CHANNEL_DESCENDANT_COMMON, /* Required Access Rights */ RS_ACCESS_NONE ) RS_ENTRY( @@ -1133,7 +1182,7 @@ /* Parents */ RS_LIST(classId(KernelChannel)), /* Alloc Param Info */ RS_OPTIONAL(NV_BSP_ALLOCATION_PARAMETERS), /* Resource Free Priority */ RS_FREE_PRIORITY_DEFAULT, - /* Flags */ RS_FLAGS_CHANNEL_DESCENDANT_COMMON, + /* Flags */ RS_FLAGS_ALLOC_NON_PRIVILEGED | RS_FLAGS_CHANNEL_DESCENDANT_COMMON, /* Required Access Rights */ RS_ACCESS_NONE ) RS_ENTRY( @@ -1143,7 +1192,7 @@ /* Parents */ RS_LIST(classId(KernelChannel)), /* Alloc Param Info */ RS_OPTIONAL(NV_BSP_ALLOCATION_PARAMETERS), /* Resource Free Priority */ RS_FREE_PRIORITY_DEFAULT, - /* Flags */ RS_FLAGS_CHANNEL_DESCENDANT_COMMON, + /* Flags */ RS_FLAGS_ALLOC_NON_PRIVILEGED | RS_FLAGS_CHANNEL_DESCENDANT_COMMON, /* Required Access Rights */ RS_ACCESS_NONE ) RS_ENTRY( @@ -1153,7 +1202,7 @@ /* Parents */ RS_LIST(classId(KernelChannel)), /* Alloc Param Info */ RS_OPTIONAL(NV_NVJPG_ALLOCATION_PARAMETERS), /* Resource Free Priority */ RS_FREE_PRIORITY_DEFAULT, - /* Flags */ RS_FLAGS_CHANNEL_DESCENDANT_COMMON, + /* Flags */ RS_FLAGS_ALLOC_NON_PRIVILEGED | RS_FLAGS_CHANNEL_DESCENDANT_COMMON, /* Required Access Rights */ RS_ACCESS_NONE ) RS_ENTRY( @@ -1163,7 +1212,7 @@ /* Parents */ RS_LIST(classId(KernelChannel)), /* Alloc Param Info */ RS_OPTIONAL(NV_NVJPG_ALLOCATION_PARAMETERS), /* Resource Free Priority */ RS_FREE_PRIORITY_DEFAULT, - /* Flags */ RS_FLAGS_CHANNEL_DESCENDANT_COMMON, + /* Flags */ RS_FLAGS_ALLOC_NON_PRIVILEGED | RS_FLAGS_CHANNEL_DESCENDANT_COMMON, /* Required Access Rights */ RS_ACCESS_NONE ) RS_ENTRY( @@ -1173,7 +1222,7 @@ /* Parents */ RS_LIST(classId(KernelChannel)), /* Alloc Param Info */ RS_OPTIONAL(NV_NVJPG_ALLOCATION_PARAMETERS), /* Resource Free Priority */ RS_FREE_PRIORITY_DEFAULT, - /* Flags */ RS_FLAGS_CHANNEL_DESCENDANT_COMMON, + /* Flags */ RS_FLAGS_ALLOC_NON_PRIVILEGED | RS_FLAGS_CHANNEL_DESCENDANT_COMMON, /* Required Access Rights */ RS_ACCESS_NONE ) RS_ENTRY( @@ -1183,7 +1232,7 @@ /* Parents */ RS_LIST(classId(KernelChannel)), /* Alloc Param Info */ RS_OPTIONAL(NV_OFA_ALLOCATION_PARAMETERS), /* Resource Free Priority */ RS_FREE_PRIORITY_DEFAULT, - /* Flags */ RS_FLAGS_CHANNEL_DESCENDANT_COMMON, + /* Flags */ RS_FLAGS_ALLOC_NON_PRIVILEGED | RS_FLAGS_CHANNEL_DESCENDANT_COMMON, /* Required Access Rights */ RS_ACCESS_NONE ) RS_ENTRY( @@ -1193,7 +1242,7 @@ /* Parents */ RS_LIST(classId(KernelChannel)), /* Alloc Param Info */ RS_OPTIONAL(NV_OFA_ALLOCATION_PARAMETERS), /* Resource Free Priority */ RS_FREE_PRIORITY_DEFAULT, - /* Flags */ RS_FLAGS_CHANNEL_DESCENDANT_COMMON, + /* Flags */ RS_FLAGS_ALLOC_NON_PRIVILEGED | RS_FLAGS_CHANNEL_DESCENDANT_COMMON, /* Required Access Rights */ RS_ACCESS_NONE ) RS_ENTRY( @@ -1203,7 +1252,7 @@ /* Parents */ RS_LIST(classId(KernelChannel)), /* Alloc Param Info */ RS_OPTIONAL(NV_OFA_ALLOCATION_PARAMETERS), /* Resource Free Priority */ RS_FREE_PRIORITY_DEFAULT, - /* Flags */ RS_FLAGS_CHANNEL_DESCENDANT_COMMON, + /* Flags */ RS_FLAGS_ALLOC_NON_PRIVILEGED | RS_FLAGS_CHANNEL_DESCENDANT_COMMON, /* Required Access Rights */ RS_ACCESS_NONE ) RS_ENTRY( @@ -1213,7 +1262,7 @@ /* Parents */ RS_LIST(classId(KernelChannel)), /* Alloc Param Info */ RS_OPTIONAL(NV_OFA_ALLOCATION_PARAMETERS), /* Resource Free Priority */ RS_FREE_PRIORITY_DEFAULT, - /* Flags */ RS_FLAGS_CHANNEL_DESCENDANT_COMMON, + /* Flags */ RS_FLAGS_ALLOC_NON_PRIVILEGED | RS_FLAGS_CHANNEL_DESCENDANT_COMMON, /* Required Access Rights */ RS_ACCESS_NONE ) RS_ENTRY( @@ -1223,7 +1272,7 @@ /* Parents */ RS_LIST(classId(KernelChannel)), /* Alloc Param Info */ RS_OPTIONAL(NV_MSENC_ALLOCATION_PARAMETERS), /* Resource Free Priority */ RS_FREE_PRIORITY_DEFAULT, - /* Flags */ RS_FLAGS_CHANNEL_DESCENDANT_COMMON, + /* Flags */ RS_FLAGS_ALLOC_NON_PRIVILEGED | RS_FLAGS_CHANNEL_DESCENDANT_COMMON, /* Required Access Rights */ RS_ACCESS_NONE ) RS_ENTRY( @@ -1233,7 +1282,7 @@ /* Parents */ RS_LIST(classId(KernelChannel)), /* Alloc Param Info */ RS_OPTIONAL(NV_MSENC_ALLOCATION_PARAMETERS), /* Resource Free Priority */ RS_FREE_PRIORITY_DEFAULT, - /* Flags */ RS_FLAGS_CHANNEL_DESCENDANT_COMMON, + /* Flags */ RS_FLAGS_ALLOC_NON_PRIVILEGED | RS_FLAGS_CHANNEL_DESCENDANT_COMMON, /* Required Access Rights */ RS_ACCESS_NONE ) RS_ENTRY( @@ -1243,7 +1292,7 @@ /* Parents */ RS_LIST(classId(KernelChannel)), /* Alloc Param Info */ RS_OPTIONAL(NV_MSENC_ALLOCATION_PARAMETERS), /* Resource Free Priority */ RS_FREE_PRIORITY_DEFAULT, - /* Flags */ RS_FLAGS_CHANNEL_DESCENDANT_COMMON, + /* Flags */ RS_FLAGS_ALLOC_NON_PRIVILEGED | RS_FLAGS_CHANNEL_DESCENDANT_COMMON, /* Required Access Rights */ RS_ACCESS_NONE ) RS_ENTRY( @@ -1253,7 +1302,17 @@ /* Parents */ RS_LIST(classId(KernelChannel)), /* Alloc Param Info */ RS_OPTIONAL(NV_MSENC_ALLOCATION_PARAMETERS), /* Resource Free Priority */ RS_FREE_PRIORITY_DEFAULT, - /* Flags */ RS_FLAGS_CHANNEL_DESCENDANT_COMMON, + /* Flags */ RS_FLAGS_ALLOC_NON_PRIVILEGED | RS_FLAGS_CHANNEL_DESCENDANT_COMMON, + /* Required Access Rights */ RS_ACCESS_NONE +) +RS_ENTRY( + /* External Class */ HOPPER_SEC2_WORK_LAUNCH_A, + /* Internal Class */ Sec2Context, + /* Multi-Instance */ NV_TRUE, + /* Parents */ RS_LIST(classId(KernelChannel)), + /* Alloc Param Info */ RS_NONE, + /* Resource Free Priority */ RS_FREE_PRIORITY_DEFAULT, + /* Flags */ RS_FLAGS_ALLOC_NON_PRIVILEGED | RS_FLAGS_CHANNEL_DESCENDANT_COMMON, /* Required Access Rights */ RS_ACCESS_NONE ) RS_ENTRY( @@ -1263,7 +1322,7 @@ /* Parents */ RS_LIST(classId(KernelChannel)), /* Alloc Param Info */ RS_OPTIONAL(NV_GR_ALLOCATION_PARAMETERS), /* Resource Free Priority */ RS_FREE_PRIORITY_DEFAULT, - /* Flags */ RS_FLAGS_CHANNEL_DESCENDANT_COMMON | RS_FLAGS_ACQUIRE_RO_API_LOCK_ON_ALLOC, + /* Flags */ RS_FLAGS_ALLOC_NON_PRIVILEGED | RS_FLAGS_CHANNEL_DESCENDANT_COMMON | RS_FLAGS_ACQUIRE_RO_API_LOCK_ON_ALLOC, /* Required Access Rights */ RS_ACCESS_NONE ) RS_ENTRY( @@ -1273,7 +1332,7 @@ /* Parents */ RS_LIST(classId(KernelChannel)), /* Alloc Param Info */ RS_OPTIONAL(NV_GR_ALLOCATION_PARAMETERS), /* Resource Free Priority */ RS_FREE_PRIORITY_DEFAULT, - /* Flags */ RS_FLAGS_CHANNEL_DESCENDANT_COMMON | RS_FLAGS_ACQUIRE_RO_API_LOCK_ON_ALLOC, + /* Flags */ RS_FLAGS_ALLOC_NON_PRIVILEGED | RS_FLAGS_CHANNEL_DESCENDANT_COMMON | RS_FLAGS_ACQUIRE_RO_API_LOCK_ON_ALLOC, /* Required Access Rights */ RS_ACCESS_NONE ) RS_ENTRY( @@ -1283,7 +1342,7 @@ /* Parents */ RS_LIST(classId(KernelChannel)), /* Alloc Param Info */ RS_OPTIONAL(NV_GR_ALLOCATION_PARAMETERS), /* Resource Free Priority */ RS_FREE_PRIORITY_DEFAULT, - /* Flags */ RS_FLAGS_CHANNEL_DESCENDANT_COMMON | RS_FLAGS_ACQUIRE_RO_API_LOCK_ON_ALLOC, + /* Flags */ RS_FLAGS_ALLOC_NON_PRIVILEGED | RS_FLAGS_CHANNEL_DESCENDANT_COMMON | RS_FLAGS_ACQUIRE_RO_API_LOCK_ON_ALLOC, /* Required Access Rights */ RS_ACCESS_NONE ) RS_ENTRY( @@ -1293,7 +1352,7 @@ /* Parents */ RS_LIST(classId(KernelChannel)), /* Alloc Param Info */ RS_OPTIONAL(NV_GR_ALLOCATION_PARAMETERS), /* Resource Free Priority */ RS_FREE_PRIORITY_DEFAULT, - /* Flags */ RS_FLAGS_CHANNEL_DESCENDANT_COMMON | RS_FLAGS_ACQUIRE_RO_API_LOCK_ON_ALLOC, + /* Flags */ RS_FLAGS_ALLOC_NON_PRIVILEGED | RS_FLAGS_CHANNEL_DESCENDANT_COMMON | RS_FLAGS_ACQUIRE_RO_API_LOCK_ON_ALLOC, /* Required Access Rights */ RS_ACCESS_NONE ) RS_ENTRY( @@ -1303,7 +1362,7 @@ /* Parents */ RS_LIST(classId(KernelChannel)), /* Alloc Param Info */ RS_OPTIONAL(NV_GR_ALLOCATION_PARAMETERS), /* Resource Free Priority */ RS_FREE_PRIORITY_DEFAULT, - /* Flags */ RS_FLAGS_CHANNEL_DESCENDANT_COMMON | RS_FLAGS_ACQUIRE_RO_API_LOCK_ON_ALLOC, + /* Flags */ RS_FLAGS_ALLOC_NON_PRIVILEGED | RS_FLAGS_CHANNEL_DESCENDANT_COMMON | RS_FLAGS_ACQUIRE_RO_API_LOCK_ON_ALLOC, /* Required Access Rights */ RS_ACCESS_NONE ) RS_ENTRY( @@ -1313,7 +1372,7 @@ /* Parents */ RS_LIST(classId(KernelChannel)), /* Alloc Param Info */ RS_OPTIONAL(NV_GR_ALLOCATION_PARAMETERS), /* Resource Free Priority */ RS_FREE_PRIORITY_DEFAULT, - /* Flags */ RS_FLAGS_CHANNEL_DESCENDANT_COMMON | RS_FLAGS_ACQUIRE_RO_API_LOCK_ON_ALLOC, + /* Flags */ RS_FLAGS_ALLOC_NON_PRIVILEGED | RS_FLAGS_CHANNEL_DESCENDANT_COMMON | RS_FLAGS_ACQUIRE_RO_API_LOCK_ON_ALLOC, /* Required Access Rights */ RS_ACCESS_NONE ) RS_ENTRY( @@ -1323,7 +1382,7 @@ /* Parents */ RS_LIST(classId(KernelChannel)), /* Alloc Param Info */ RS_OPTIONAL(NV_GR_ALLOCATION_PARAMETERS), /* Resource Free Priority */ RS_FREE_PRIORITY_DEFAULT, - /* Flags */ RS_FLAGS_CHANNEL_DESCENDANT_COMMON | RS_FLAGS_ACQUIRE_RO_API_LOCK_ON_ALLOC, + /* Flags */ RS_FLAGS_ALLOC_NON_PRIVILEGED | RS_FLAGS_CHANNEL_DESCENDANT_COMMON | RS_FLAGS_ACQUIRE_RO_API_LOCK_ON_ALLOC, /* Required Access Rights */ RS_ACCESS_NONE ) RS_ENTRY( @@ -1333,7 +1392,7 @@ /* Parents */ RS_LIST(classId(KernelChannel)), /* Alloc Param Info */ RS_OPTIONAL(NV_GR_ALLOCATION_PARAMETERS), /* Resource Free Priority */ RS_FREE_PRIORITY_DEFAULT, - /* Flags */ RS_FLAGS_CHANNEL_DESCENDANT_COMMON | RS_FLAGS_ACQUIRE_RO_API_LOCK_ON_ALLOC, + /* Flags */ RS_FLAGS_ALLOC_NON_PRIVILEGED | RS_FLAGS_CHANNEL_DESCENDANT_COMMON | RS_FLAGS_ACQUIRE_RO_API_LOCK_ON_ALLOC, /* Required Access Rights */ RS_ACCESS_NONE ) RS_ENTRY( @@ -1343,7 +1402,7 @@ /* Parents */ RS_LIST(classId(KernelChannel)), /* Alloc Param Info */ RS_OPTIONAL(NV_GR_ALLOCATION_PARAMETERS), /* Resource Free Priority */ RS_FREE_PRIORITY_DEFAULT, - /* Flags */ RS_FLAGS_CHANNEL_DESCENDANT_COMMON | RS_FLAGS_ACQUIRE_RO_API_LOCK_ON_ALLOC, + /* Flags */ RS_FLAGS_ALLOC_NON_PRIVILEGED | RS_FLAGS_CHANNEL_DESCENDANT_COMMON | RS_FLAGS_ACQUIRE_RO_API_LOCK_ON_ALLOC, /* Required Access Rights */ RS_ACCESS_NONE ) RS_ENTRY( @@ -1353,7 +1412,7 @@ /* Parents */ RS_LIST(classId(KernelChannel)), /* Alloc Param Info */ RS_OPTIONAL(NV_GR_ALLOCATION_PARAMETERS), /* Resource Free Priority */ RS_FREE_PRIORITY_DEFAULT, - /* Flags */ RS_FLAGS_CHANNEL_DESCENDANT_COMMON | RS_FLAGS_ACQUIRE_RO_API_LOCK_ON_ALLOC, + /* Flags */ RS_FLAGS_ALLOC_NON_PRIVILEGED | RS_FLAGS_CHANNEL_DESCENDANT_COMMON | RS_FLAGS_ACQUIRE_RO_API_LOCK_ON_ALLOC, /* Required Access Rights */ RS_ACCESS_NONE ) RS_ENTRY( @@ -1363,7 +1422,7 @@ /* Parents */ RS_LIST(classId(KernelChannel)), /* Alloc Param Info */ RS_OPTIONAL(NV_GR_ALLOCATION_PARAMETERS), /* Resource Free Priority */ RS_FREE_PRIORITY_DEFAULT, - /* Flags */ RS_FLAGS_CHANNEL_DESCENDANT_COMMON | RS_FLAGS_ACQUIRE_RO_API_LOCK_ON_ALLOC, + /* Flags */ RS_FLAGS_ALLOC_NON_PRIVILEGED | RS_FLAGS_CHANNEL_DESCENDANT_COMMON | RS_FLAGS_ACQUIRE_RO_API_LOCK_ON_ALLOC, /* Required Access Rights */ RS_ACCESS_NONE ) RS_ENTRY( @@ -1373,7 +1432,7 @@ /* Parents */ RS_LIST(classId(KernelChannel)), /* Alloc Param Info */ RS_OPTIONAL(NV_GR_ALLOCATION_PARAMETERS), /* Resource Free Priority */ RS_FREE_PRIORITY_DEFAULT, - /* Flags */ RS_FLAGS_CHANNEL_DESCENDANT_COMMON | RS_FLAGS_ACQUIRE_RO_API_LOCK_ON_ALLOC, + /* Flags */ RS_FLAGS_ALLOC_NON_PRIVILEGED | RS_FLAGS_CHANNEL_DESCENDANT_COMMON | RS_FLAGS_ACQUIRE_RO_API_LOCK_ON_ALLOC, /* Required Access Rights */ RS_ACCESS_NONE ) RS_ENTRY( @@ -1383,7 +1442,7 @@ /* Parents */ RS_ANY_PARENT, /* Alloc Param Info */ RS_REQUIRED(NV_CONTEXT_DMA_ALLOCATION_PARAMS), /* Resource Free Priority */ RS_FREE_PRIORITY_DEFAULT, - /* Flags */ RS_FLAGS_ACQUIRE_GPUS_LOCK, + /* Flags */ RS_FLAGS_ALLOC_NON_PRIVILEGED | RS_FLAGS_ACQUIRE_GPUS_LOCK, /* Required Access Rights */ RS_ACCESS_NONE ) RS_ENTRY( @@ -1393,7 +1452,7 @@ /* Parents */ RS_ANY_PARENT, /* Alloc Param Info */ RS_REQUIRED(NV0005_ALLOC_PARAMETERS), /* Resource Free Priority */ RS_FREE_PRIORITY_DEFAULT, - /* Flags */ RS_FLAGS_ACQUIRE_GPUS_LOCK, + /* Flags */ RS_FLAGS_ALLOC_NON_PRIVILEGED | RS_FLAGS_ACQUIRE_GPUS_LOCK, /* Required Access Rights */ RS_ACCESS_NONE ) RS_ENTRY( @@ -1403,7 +1462,7 @@ /* Parents */ RS_ANY_PARENT, /* Alloc Param Info */ RS_REQUIRED(NV0005_ALLOC_PARAMETERS), /* Resource Free Priority */ RS_FREE_PRIORITY_DEFAULT, - /* Flags */ RS_FLAGS_ACQUIRE_GPUS_LOCK, + /* Flags */ RS_FLAGS_ALLOC_NON_PRIVILEGED | RS_FLAGS_ACQUIRE_GPUS_LOCK, /* Required Access Rights */ RS_ACCESS_NONE ) RS_ENTRY( @@ -1413,7 +1472,7 @@ /* Parents */ RS_ANY_PARENT, /* Alloc Param Info */ RS_REQUIRED(NV0005_ALLOC_PARAMETERS), /* Resource Free Priority */ RS_FREE_PRIORITY_DEFAULT, - /* Flags */ RS_FLAGS_ACQUIRE_GPUS_LOCK, + /* Flags */ RS_FLAGS_ALLOC_NON_PRIVILEGED | RS_FLAGS_ACQUIRE_GPUS_LOCK, /* Required Access Rights */ RS_ACCESS_NONE ) RS_ENTRY( @@ -1423,7 +1482,17 @@ /* Parents */ RS_ANY_PARENT, /* Alloc Param Info */ RS_REQUIRED(NV0005_ALLOC_PARAMETERS), /* Resource Free Priority */ RS_FREE_PRIORITY_DEFAULT, - /* Flags */ RS_FLAGS_ACQUIRE_GPUS_LOCK, + /* Flags */ RS_FLAGS_ALLOC_NON_PRIVILEGED | RS_FLAGS_ACQUIRE_GPUS_LOCK, + /* Required Access Rights */ RS_ACCESS_NONE +) +RS_ENTRY( + /* External Class */ NV_CONFIDENTIAL_COMPUTE, + /* Internal Class */ ConfidentialComputeApi, + /* Multi-Instance */ NV_TRUE, + /* Parents */ RS_LIST(classId(RmClientResource)), + /* Alloc Param Info */ RS_OPTIONAL(NV_CONFIDENTIAL_COMPUTE_ALLOC_PARAMS), + /* Resource Free Priority */ RS_FREE_PRIORITY_DEFAULT, + /* Flags */ RS_FLAGS_ALLOC_NON_PRIVILEGED | RS_FLAGS_ACQUIRE_GPUS_LOCK, /* Required Access Rights */ RS_ACCESS_NONE ) RS_ENTRY( @@ -1433,9 +1502,21 @@ /* Parents */ RS_LIST(classId(Subdevice)), /* Alloc Param Info */ RS_NONE, /* Resource Free Priority */ RS_FREE_PRIORITY_DEFAULT, - /* Flags */ RS_FLAGS_ACQUIRE_GPUS_LOCK, + /* Flags */ RS_FLAGS_ALLOC_NON_PRIVILEGED | RS_FLAGS_ACQUIRE_GPUS_LOCK, + /* Required Access Rights */ RS_ACCESS_NONE +) +#if RMCFG_CLASS_NV_CE_UTILS && (defined(DEBUG) || defined(DEVELOP)) +RS_ENTRY( + /* External Class */ NV_CE_UTILS, + /* Internal Class */ CeUtilsApi, + /* Multi-Instance */ NV_TRUE, + /* Parents */ RS_LIST(classId(Subdevice)), + /* Alloc Param Info */ RS_REQUIRED(NV0050_ALLOCATION_PARAMETERS), + /* Resource Free Priority */ RS_FREE_PRIORITY_DEFAULT, + /* Flags */ RS_FLAGS_ACQUIRE_GPUS_LOCK | RS_FLAGS_ALLOC_PRIVILEGED, /* Required Access Rights */ RS_ACCESS_NONE ) +#endif // Undefine the entry macro to simplify call sites #undef RS_ENTRY diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/kernel/rmapi/resource_list_required_includes.h nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/kernel/rmapi/resource_list_required_includes.h --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/kernel/rmapi/resource_list_required_includes.h 2023-10-25 20:21:31.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/kernel/rmapi/resource_list_required_includes.h 2024-03-05 22:14:05.000000000 +0000 @@ -45,28 +45,10 @@ #include "nvos.h" -#if RMCFG_CLASS_GF100_CHANNEL_GPFIFO || \ - RMCFG_CLASS_KEPLER_CHANNEL_GPFIFO_A || \ - RMCFG_CLASS_KEPLER_CHANNEL_GPFIFO_B || \ - RMCFG_CLASS_KEPLER_CHANNEL_GPFIFO_C || \ - RMCFG_CLASS_MAXWELL_CHANNEL_GPFIFO_A || \ - RMCFG_CLASS_PASCAL_CHANNEL_GPFIFO_A || \ - RMCFG_CLASS_VOLTA_CHANNEL_GPFIFO_A || \ - RMCFG_CLASS_TURING_CHANNEL_GPFIFO_A || \ - RMCFG_CLASS_AMPERE_CHANNEL_GPFIFO_A || \ - RMCFG_CLASS_HOPPER_CHANNEL_GPFIFO_A #include "alloc/alloc_channel.h" -#endif -#if RMCFG_CLASS_MAXWELL_DMA_COPY_A || \ - RMCFG_CLASS_PASCAL_DMA_COPY_A || \ - RMCFG_CLASS_PASCAL_DMA_COPY_B || \ - RMCFG_CLASS_VOLTA_DMA_COPY_A || \ - RMCFG_CLASS_TURING_DMA_COPY_A || \ - RMCFG_CLASS_AMPERE_DMA_COPY_A || \ - RMCFG_CLASS_AMPERE_DMA_COPY_B || \ - RMCFG_CLASS_HOPPER_DMA_COPY_A #include "class/clb0b5sw.h" -#endif + +#include "alloc/alloc_access_counter_buffer.h" #endif /* ifndef RESOURCE_LIST_REQUIRED_INCLUDES_H */ diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/kernel/rmapi/rmapi.c nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/kernel/rmapi/rmapi.c --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/kernel/rmapi/rmapi.c 2023-10-25 20:21:32.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/kernel/rmapi/rmapi.c 2024-03-05 22:14:05.000000000 +0000 @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 1993-2021 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 1993-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -44,7 +44,8 @@ NvU64 timestamp; LOCK_TRACE_INFO traceInfo; NvU64 tlsEntryId; - + volatile NvU32 contentionCount; + NvU32 lowPriorityAging; } RMAPI_LOCK; RsServer g_resServ; @@ -178,8 +179,8 @@ pRmApi->AllocWithHandle = rmapiAllocWithHandle; pRmApi->AllocWithSecInfo = pRmApi->bTlsInternal ? rmapiAllocWithSecInfo : rmapiAllocWithSecInfoTls; - pRmApi->FreeClientList = rmapiFreeClientList; - pRmApi->FreeClientListWithSecInfo = pRmApi->bTlsInternal ? rmapiFreeClientListWithSecInfo : rmapiFreeClientListWithSecInfoTls; + pRmApi->DisableClients = rmapiDisableClients; + pRmApi->DisableClientsWithSecInfo = pRmApi->bTlsInternal ? rmapiDisableClientsWithSecInfo : rmapiDisableClientsWithSecInfoTls; pRmApi->Free = rmapiFree; pRmApi->FreeWithSecInfo = pRmApi->bTlsInternal ? rmapiFreeWithSecInfo : rmapiFreeWithSecInfoTls; @@ -216,6 +217,65 @@ return &g_RmApiList[rmapiType]; } +static void +_rmapiUnrefGpuAccessNeeded +( + NvU32 gpuMask +) +{ + NvU32 gpuInstance = 0; + OBJGPU *pGpu = NULL; + + while ((pGpu = gpumgrGetNextGpu(gpuMask, &gpuInstance)) != NULL) + { + osUnrefGpuAccessNeeded(pGpu->pOsGpuInfo); + } +} + +static NV_STATUS +_rmapiRefGpuAccessNeeded +( + NvU32 *pGpuMask +) +{ + NV_STATUS status = NV_OK; + NvU32 mask = 0; + NvU32 gpuInstance = 0; + OBJGPU *pGpu = NULL; + + status = gpumgrGetGpuAttachInfo(NULL, &mask); + if (status != NV_OK) + { + return status; + } + + while ((pGpu = gpumgrGetNextGpu(mask, &gpuInstance)) != NULL) + { + status = osRefGpuAccessNeeded(pGpu->pOsGpuInfo); + if (status != NV_OK) + { + goto unref; + } + + /* + *_rmapiRefGpuAccessNeeded records the gpuMask + * during ref up and this is used to unref exact same + * GPUs in _rmapiUnrefGpuAccessNeeded. This is done + * to protect against obtaining incorrect pGpu if the mask + * changes due to a RM_API called between ref/unref + * sequence. + */ + *pGpuMask |= (1 << pGpu->gpuInstance); + } + +unref: + if (status != NV_OK) + { + _rmapiUnrefGpuAccessNeeded(*pGpuMask); + } + return status; +} + NV_STATUS rmapiPrologue ( @@ -224,6 +284,49 @@ ) { NV_STATUS status = NV_OK; + NvBool bApiLockTaken = NV_FALSE; + NvU32 mask; + + NV_ASSERT_OR_RETURN(pRmApi != NULL, NV_ERR_INVALID_ARGUMENT); + NV_ASSERT_OR_RETURN(pContext != NULL, NV_ERR_INVALID_ARGUMENT); + + /* + * Check for external clients. This condition is checked here + * in order to avoid a check at all caller sites of + * rmapiPrologue. Effectively rmapiprologue is a no-op for + * internal clients. + */ + if (!pRmApi->bTlsInternal) + { + mask = osGetDynamicPowerSupportMask(); + if (!mask) + return status; + /* + * NOTE1: Callers of rmapiPro{Epi}logue function call may call + * it with or without API lock taken. Hence, we check here + * whether API lock has been taken. We take API lock if + * it not taken already. + * We obtain the pGPU by using the gpuMask in + * _rmapiRef{Unref}GpuAccessNeeded. This needs API lock to be + * safe against init/teardown of GPUs while we ref/unref + * the GPUs. We release the lock after we have finished + * with ref/unref, if we had taken it. + */ + if (!rmapiLockIsOwner()) + { + status = rmapiLockAcquire(RMAPI_LOCK_FLAGS_READ, RM_LOCK_MODULES_CLIENT); + if (status != NV_OK) + { + return status; + } + bApiLockTaken = NV_TRUE; + } + status = _rmapiRefGpuAccessNeeded(&pContext->gpuMask); + if (bApiLockTaken == NV_TRUE) + { + rmapiLockRelease(); + } + } return status; } @@ -234,6 +337,43 @@ RM_API_CONTEXT *pContext ) { + NV_STATUS status = NV_OK; + NvBool bApiLockTaken = NV_FALSE; + NvU32 mask; + + NV_ASSERT_OR_RETURN_VOID(pRmApi != NULL); + NV_ASSERT_OR_RETURN_VOID(pContext != NULL); + + /* + * Check for external clients. This condition is checked here + * in order to avoid a check at all caller sites of + * rmapiEpilogue. Effectively rmapiEpilogue is a no-op for + * internal clients. + */ + if (!pRmApi->bTlsInternal) + { + mask = osGetDynamicPowerSupportMask(); + if (!mask) + return; + + /* Please see NOTE1 */ + if (!rmapiLockIsOwner()) + { + status = rmapiLockAcquire(RMAPI_LOCK_FLAGS_READ, RM_LOCK_MODULES_CLIENT); + if (status != NV_OK) + { + return; + } + bApiLockTaken = NV_TRUE; + } + + _rmapiUnrefGpuAccessNeeded(pContext->gpuMask); + + if (bApiLockTaken == NV_TRUE) + { + rmapiLockRelease(); + } + } } void @@ -291,6 +431,14 @@ g_resServ.bUnlockedParamCopy = NV_TRUE; NvU32 val = 0; + + if ((osReadRegistryDword(NULL, + NV_REG_STR_RM_LOCKING_LOW_PRIORITY_AGING, + &val) == NV_OK)) + { + g_RmApiLock.lowPriorityAging = val; + } + if ((osReadRegistryDword(NULL, NV_REG_STR_RM_PARAM_COPY_NO_LOCK, &val) == NV_OK)) @@ -356,6 +504,7 @@ } else { + // Conditional acquires don't care about contention or priority if (portSyncRwLockAcquireWriteConditional(g_RmApiLock.pLock)) { g_RmApiLock.threadId = threadId; @@ -375,7 +524,23 @@ else { - portSyncRwLockAcquireWrite(g_RmApiLock.pLock); + if (flags & RMAPI_LOCK_FLAGS_LOW_PRIORITY) + { + NvS32 age = g_RmApiLock.lowPriorityAging; + portSyncRwLockAcquireWrite(g_RmApiLock.pLock); + while ((g_RmApiLock.contentionCount > 0) && (age--)) + { + portSyncRwLockReleaseWrite(g_RmApiLock.pLock); + osDelay(10); + portSyncRwLockAcquireWrite(g_RmApiLock.pLock); + } + } + else + { + portAtomicIncrementU32(&g_RmApiLock.contentionCount); + portSyncRwLockAcquireWrite(g_RmApiLock.pLock); + portAtomicDecrementU32(&g_RmApiLock.contentionCount); + } g_RmApiLock.threadId = threadId; } } @@ -741,7 +906,7 @@ { pClient = *it.pValue; pRsClient = staticCast(pClient, RsClient); - + NV_CHECK_OR_ELSE_STR(LEVEL_ERROR, pClient->pOSInfo == pOSInfo, "*** OS info mismatch", continue); pClientHandleList[k++] = pRsClient->hClient; diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/kernel/rmapi/rmapi_cache.c nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/kernel/rmapi/rmapi_cache.c --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/kernel/rmapi/rmapi_cache.c 2023-10-25 20:21:32.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/kernel/rmapi/rmapi_cache.c 2024-03-05 22:14:05.000000000 +0000 @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 2020-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2020-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -31,6 +31,9 @@ #include "rmapi/rmapi.h" #include "rmapi/rmapi_utils.h" #include "ctrl/ctrl0000/ctrl0000system.h" +#include "ctrl/ctrl2080/ctrl2080gpu.h" +#include "ctrl/ctrl2080/ctrl2080fifo.h" +#include "ctrl/ctrl2080/ctrl2080bus.h" typedef struct { @@ -48,7 +51,7 @@ // Stores the cached control value. // Each submap in the multimap stores the cached control value for one GPU. // The key to find a submap is GPU Instance stored in ObjectToGpuInstMap -// +// // The key inside the submap is the control command // The value inside the submap is the cached control value for the command // @@ -81,12 +84,37 @@ PORT_RWLOCK *pLock; } RmapiControlCache; +enum CACHE_LOCK_TYPE +{ + LOCK_EXCLUSIVE, + LOCK_SHARED +}; + +static void _cacheLockAcquire(enum CACHE_LOCK_TYPE lockType) +{ + if (lockType == LOCK_EXCLUSIVE) + portSyncRwLockAcquireWrite(RmapiControlCache.pLock); + else + portSyncRwLockAcquireRead(RmapiControlCache.pLock); +} + +static void _cacheLockRelease(enum CACHE_LOCK_TYPE lockType) +{ + if (lockType == LOCK_EXCLUSIVE) + portSyncRwLockReleaseWrite(RmapiControlCache.pLock); + else + portSyncRwLockReleaseRead(RmapiControlCache.pLock); +} + +static RmapiControlCacheEntry* _getOrInitCacheEntry(NvU64 key1, NvU64 key2, NvBool bSet, + NvU32 allocSize, NvBool *pbParamAllocated); + NvBool rmapiControlIsCacheable(NvU32 flags, NvU32 accessRight, NvBool bAllowInternal) { if (RmapiControlCache.mode == NV0000_CTRL_SYSTEM_RMCTRL_CACHE_MODE_CTRL_MODE_DISABLE) return NV_FALSE; - if (!(flags & RMCTRL_FLAGS_CACHEABLE)) + if (!(flags & RMCTRL_FLAGS_CACHEABLE_ANY)) return NV_FALSE; // @@ -119,7 +147,7 @@ NvU32 flags; NvU32 accessRight; - if (rmapiutilGetControlInfo(cmd, &flags, &accessRight) != NV_OK) + if (rmapiutilGetControlInfo(cmd, &flags, &accessRight, NULL) != NV_OK) return NV_FALSE; return rmapiControlIsCacheable(flags, accessRight, bAllowInternal); @@ -169,7 +197,7 @@ NV_PRINTF(LEVEL_INFO, "gpu inst set for 0x%x 0x%x: 0x%x\n", hClient, hObject, gpuInst); - portSyncRwLockAcquireWrite(RmapiControlCache.pLock); + _cacheLockAcquire(LOCK_EXCLUSIVE); entry = mapFind(&RmapiControlCache.objectToGpuInstMap, _handlesToGpuInstKey(hClient, hObject)); if (entry != NULL) @@ -193,7 +221,7 @@ *entry = gpuInst; done: - portSyncRwLockReleaseWrite(RmapiControlCache.pLock); + _cacheLockRelease(LOCK_EXCLUSIVE); return status; } @@ -258,7 +286,7 @@ } } -NV_STATUS rmapiControlCacheGet +static NV_STATUS _rmapiControlCacheGet ( NvHandle hClient, NvHandle hObject, @@ -271,11 +299,14 @@ NvU32 gpuInst; NV_STATUS status = NV_OK; - if (RmapiControlCache.mode == NV0000_CTRL_SYSTEM_RMCTRL_CACHE_MODE_CTRL_MODE_VERIFY_ONLY) - return NV_ERR_OBJECT_NOT_FOUND; + _cacheLockAcquire(LOCK_SHARED); - NV_PRINTF(LEVEL_INFO, "control cache lookup for 0x%x 0x%x 0x%x\n", hClient, hObject, cmd); - portSyncRwLockAcquireRead(RmapiControlCache.pLock); + if (rmapiControlCacheGetMode() == NV0000_CTRL_SYSTEM_RMCTRL_CACHE_MODE_CTRL_MODE_DISABLE) + { + // unexpected mode change. + status = NV_ERR_INVALID_STATE; + goto done; + } if (_isCmdSystemWide(cmd)) { @@ -288,7 +319,7 @@ goto done; } - entry = multimapFindItem(&RmapiControlCache.gpusControlCache, gpuInst, cmd); + entry = _getOrInitCacheEntry(gpuInst, cmd, NV_FALSE, 0, NULL); if (entry == NULL || entry->params == NULL) { status = NV_ERR_OBJECT_NOT_FOUND; @@ -296,13 +327,12 @@ } portMemCopy(params, paramsSize, entry->params, paramsSize); - NV_PRINTF(LEVEL_INFO, "control cache for 0x%x 0x%x 0x%x: entry %p\n", hClient, hObject, cmd, entry); done: - portSyncRwLockReleaseRead(RmapiControlCache.pLock); + _cacheLockRelease(LOCK_SHARED); return status; } -NV_STATUS rmapiControlCacheSet +static NV_STATUS _rmapiControlCacheSet ( NvHandle hClient, NvHandle hObject, @@ -313,12 +343,17 @@ { NV_STATUS status = NV_OK; RmapiControlCacheEntry* entry = NULL; - GpusControlCacheSubmap* insertedSubmap = NULL; NvU32 gpuInst; + NvBool bParamsAllocated; - NV_PRINTF(LEVEL_INFO, "control cache set for 0x%x 0x%x 0x%x\n", hClient, hObject, cmd); + _cacheLockAcquire(LOCK_EXCLUSIVE); - portSyncRwLockAcquireWrite(RmapiControlCache.pLock); + if (rmapiControlCacheGetMode() == NV0000_CTRL_SYSTEM_RMCTRL_CACHE_MODE_CTRL_MODE_DISABLE) + { + // unexpected mode change. + status = NV_ERR_INVALID_STATE; + goto done; + } if (_isCmdSystemWide(cmd)) { @@ -331,23 +366,7 @@ goto done; } - entry = multimapFindItem(&RmapiControlCache.gpusControlCache, gpuInst, cmd); - - if (entry == NULL) - { - if (multimapFindSubmap(&RmapiControlCache.gpusControlCache, gpuInst) == NULL) - { - insertedSubmap = multimapInsertSubmap(&RmapiControlCache.gpusControlCache, gpuInst); - if (insertedSubmap == NULL) - { - status = NV_ERR_NO_MEMORY; - goto done; - } - } - - entry = multimapInsertItemNew(&RmapiControlCache.gpusControlCache, gpuInst, cmd); - } - + entry = _getOrInitCacheEntry(gpuInst, cmd, NV_TRUE, paramsSize, &bParamsAllocated); if (entry == NULL) { status = NV_ERR_NO_MEMORY; @@ -355,13 +374,15 @@ } // - // Skip duplicated cache insertion. Duplicated cache set happens when + // A succeeded getOrInit call without params allocated implies + // duplicated cache insertion that should be skipped. + // Duplicated cache set happens when // 1. Parallel controls call into RM before first cache set. // All threads will attempt cache set after the control calls. // 2. Cache already set by RPC to GSP path // 3. Cache in verify only mode // - if (entry->params != NULL) + if (!bParamsAllocated) { if (RmapiControlCache.mode == NV0000_CTRL_SYSTEM_RMCTRL_CACHE_MODE_CTRL_MODE_VERIFY_ONLY) { @@ -371,34 +392,630 @@ goto done; } - entry->params = portMemAllocNonPaged(paramsSize); + portMemCopy(entry->params, paramsSize, params, paramsSize); + +done: + _cacheLockRelease(LOCK_EXCLUSIVE); + return status; +} + +// +// Common function to find existing or generate new cache entry +// For cache get, we return the cache map query result directly +// For cache set, we generate new cache entry if there's no existing entry +// in the map. +// +// key1 [IN] +// First key for the multimap entry +// key2 [IN] +// Second key for the multimap entry +// bSet [IN] +// If the query is for cache set or cache get +// allocSize [IN] +// For cache set only. +// The size to allocate for new cache entry +// pbParamsAllocated [OUT] +// For cache set only. +// Indicate if we allocated new memory for cache entry +// A cache set without memory allocation implies there's an existng entry. +// +static RmapiControlCacheEntry* +_getOrInitCacheEntry +( + NvU64 key1, + NvU64 key2, + NvBool bSet, + NvU32 allocSize, + NvBool *pbParamsAllocated +) +{ + RmapiControlCacheEntry *entry = NULL; + GpusControlCacheSubmap *insertedSubmap = NULL; + + entry = multimapFindItem(&RmapiControlCache.gpusControlCache, key1, key2); + + // for cache get, return map find result directly + if (!bSet) + return entry; + + // for cache set, try to init entry if not valid + if (entry == NULL) + { + if (multimapFindSubmap(&RmapiControlCache.gpusControlCache, key1) == NULL) + { + insertedSubmap = multimapInsertSubmap(&RmapiControlCache.gpusControlCache, key1); + if (insertedSubmap == NULL) + goto failed; + } + + entry = multimapInsertItemNew(&RmapiControlCache.gpusControlCache, key1, key2); + } + + if (entry == NULL) + goto failed_free_submap; + if (entry->params == NULL) { + entry->params = portMemAllocNonPaged(allocSize); + if (entry->params == NULL) + goto failed_free_entry; + + portMemSet(entry->params, 0, allocSize); + + if (pbParamsAllocated != NULL) + *pbParamsAllocated = NV_TRUE; + } + else if (pbParamsAllocated != NULL) + { + *pbParamsAllocated = NV_FALSE; + } + + return entry; + +failed_free_entry: + if (entry != NULL) + multimapRemoveItem(&RmapiControlCache.gpusControlCache, entry); +failed_free_submap: + if (insertedSubmap != NULL) + multimapRemoveSubmap(&RmapiControlCache.gpusControlCache, insertedSubmap); +failed: + return NULL; +} + +static NvBool _isGpuGetInfoIndexCacheable(NvU32 index) +{ + switch (index) + { + case NV2080_CTRL_GPU_INFO_INDEX_MINOR_REVISION_EXT: + case NV2080_CTRL_GPU_INFO_INDEX_NETLIST_REV0: + case NV2080_CTRL_GPU_INFO_INDEX_NETLIST_REV1: + case NV2080_CTRL_GPU_INFO_INDEX_SYSMEM_ACCESS: + case NV2080_CTRL_GPU_INFO_INDEX_GEMINI_BOARD: + case NV2080_CTRL_GPU_INFO_INDEX_SURPRISE_REMOVAL_POSSIBLE: + case NV2080_CTRL_GPU_INFO_INDEX_GLOBAL_POISON_FUSE_ENABLED: + case NV2080_CTRL_GPU_INFO_INDEX_GPU_SR_SUPPORT: + case NV2080_CTRL_GPU_INFO_INDEX_SPLIT_VAS_MGMT_SERVER_CLIENT_RM: + case NV2080_CTRL_GPU_INFO_INDEX_GPU_SM_VERSION: + case NV2080_CTRL_GPU_INFO_INDEX_4K_PAGE_ISOLATION_REQUIRED: + case NV2080_CTRL_GPU_INFO_INDEX_DISPLAY_ENABLED: + case NV2080_CTRL_GPU_INFO_INDEX_MOBILE_CONFIG_ENABLED: + case NV2080_CTRL_GPU_INFO_INDEX_GPU_PROFILING_CAPABILITY: + case NV2080_CTRL_GPU_INFO_INDEX_GPU_DEBUGGING_CAPABILITY: + case NV2080_CTRL_GPU_INFO_INDEX_CMP_SKU: + case NV2080_CTRL_GPU_INFO_INDEX_DMABUF_CAPABILITY: + return NV_TRUE; + default: + return NV_FALSE; + } +} + +static NvBool _isFifoGetInfoIndexCacheable(NvU32 index) +{ + switch (index) + { + case NV2080_CTRL_FIFO_INFO_INDEX_INSTANCE_TOTAL: + case NV2080_CTRL_FIFO_INFO_INDEX_MAX_CHANNEL_GROUPS: + case NV2080_CTRL_FIFO_INFO_INDEX_MAX_CHANNELS_PER_GROUP: + case NV2080_CTRL_FIFO_INFO_INDEX_MAX_SUBCONTEXT_PER_GROUP: + case NV2080_CTRL_FIFO_INFO_INDEX_BAR1_USERD_START_OFFSET: + case NV2080_CTRL_FIFO_INFO_INDEX_DEFAULT_CHANNEL_TIMESLICE: + return NV_TRUE; + default: + return NV_FALSE; + } +} + +static NvBool _isBusGetInfoIndexCacheable(NvU32 index) +{ + switch (index) + { + case NV2080_CTRL_BUS_INFO_INDEX_TYPE: + case NV2080_CTRL_BUS_INFO_INDEX_INTLINE: + case NV2080_CTRL_BUS_INFO_INDEX_CAPS: + case NV2080_CTRL_BUS_INFO_INDEX_PCIE_DOWNSTREAM_LINK_CAPS: + case NV2080_CTRL_BUS_INFO_INDEX_COHERENT_DMA_FLAGS: + case NV2080_CTRL_BUS_INFO_INDEX_NONCOHERENT_DMA_FLAGS: + case NV2080_CTRL_BUS_INFO_INDEX_BUS_NUMBER: + case NV2080_CTRL_BUS_INFO_INDEX_DEVICE_NUMBER: + case NV2080_CTRL_BUS_INFO_INDEX_DOMAIN_NUMBER: + case NV2080_CTRL_BUS_INFO_INDEX_INTERFACE_TYPE: + case NV2080_CTRL_BUS_INFO_INDEX_GPU_INTERFACE_TYPE: + return NV_TRUE; + default: + return NV_FALSE; + } +} + +static NvBool _isGetInfoIndexCacheable(NvU32 cmd, NvU32 index) +{ + switch (cmd) + { + case NV2080_CTRL_CMD_GPU_GET_INFO_V2: + return _isGpuGetInfoIndexCacheable(index); + case NV2080_CTRL_CMD_FIFO_GET_INFO: + return _isFifoGetInfoIndexCacheable(index); + case NV2080_CTRL_CMD_BUS_GET_INFO_V2: + return _isBusGetInfoIndexCacheable(index); + } + + return NV_FALSE; +} + +// +// For GET_INFO controls, we use an array of getInfoCacheEntry to store the +// cached value. +// +// The length of the array is the max list length of each control and is +// enough to store the cached value of all indexes. +// +// The Nth item in the array, array[N], represent the cache state of the info +// whose index value is N. If the info is cached, array[N].valid is NV_TRUE +// and the cached value is stored in array[N].data. +// array[N].valid is NV_FALSE if the info is not cached. +// +typedef struct GetInfoCacheEntry { + NvBool valid; + NvU32 data; +} GetInfoCacheEntry; + +static NV_STATUS _getInfoCacheHandler +( + NvHandle hClient, + NvHandle hObject, + NvU32 cmd, + NVXXXX_CTRL_XXX_INFO *pInfo, + NvU32 listSize, + NvU32 listSizeLimit, + NvBool bSet +) +{ + NV_STATUS status = NV_OK; + NvU32 i = 0; + NvU32 gpuInst; + RmapiControlCacheEntry *entry = NULL; + GetInfoCacheEntry *cachedTable = NULL; + const NvU32 allocSize = sizeof(GetInfoCacheEntry) * listSizeLimit; + enum CACHE_LOCK_TYPE lockType = bSet ? LOCK_EXCLUSIVE : LOCK_SHARED; + + if (listSize <= 0 || listSize > listSizeLimit || pInfo == NULL) + { + return NV_ERR_INVALID_PARAMETER; + } + + _cacheLockAcquire(lockType); + + if (rmapiControlCacheGetMode() == NV0000_CTRL_SYSTEM_RMCTRL_CACHE_MODE_CTRL_MODE_DISABLE) + { + // unexpected mode change. + status = NV_ERR_INVALID_STATE; + goto done; + } + + status = _rmapiControlCacheGetGpuInstForObject(hClient, hObject, &gpuInst); + if (status != NV_OK) + goto done; + + entry = _getOrInitCacheEntry(gpuInst, cmd, bSet, allocSize, NULL); + + if (entry == NULL || entry->params == NULL) + { + status = bSet ? NV_ERR_NO_MEMORY : NV_ERR_OBJECT_NOT_FOUND; + goto done; + } + + cachedTable = (GetInfoCacheEntry*)entry->params; + + for (i = 0; i < listSize; ++i) + { + const NvU32 index = pInfo[i].index; + + if (index >= listSizeLimit) + { + status = NV_ERR_INVALID_ARGUMENT; + goto done; + } + + if (bSet) + { + if (_isGetInfoIndexCacheable(cmd, index)) + { + if (cachedTable[index].valid) + { + NV_ASSERT(cachedTable[index].data == pInfo[i].data); + } + else + { + cachedTable[index].valid = NV_TRUE; + cachedTable[index].data = pInfo[i].data; + } + } + } + else + { + // if any of the entry is not cacheable or not in the cache, skip the whole cmd + if (!_isGetInfoIndexCacheable(cmd, index) || !cachedTable[index].valid) + { + status = NV_ERR_OBJECT_NOT_FOUND; + goto done; + } + } + } + + if (!bSet) + { + for (i = 0; i < listSize; ++i) + pInfo[i].data = cachedTable[pInfo[i].index].data; + } + +done: + + if (status != NV_OK && bSet) + { + if (entry != NULL) + { + portMemFree(entry->params); + multimapRemoveItem(&RmapiControlCache.gpusControlCache, entry); + } + } + + _cacheLockRelease(lockType); + + return status; +} + +typedef struct GpuNameStringCacheEntry +{ + NvBool bAsciiValid; + NvBool bUnicodeValid; + NvU8 ascii[NV2080_GPU_MAX_NAME_STRING_LENGTH]; + NvU16 unicode[NV2080_GPU_MAX_NAME_STRING_LENGTH]; +} GpuNameStringCacheEntry; + +NV_STATUS _gpuNameStringGet +( + NvHandle hClient, + NvHandle hObject, + NV2080_CTRL_GPU_GET_NAME_STRING_PARAMS *pParams +) +{ + NvU32 gpuInst; + NV_STATUS status = NV_OK; + RmapiControlCacheEntry *entry = NULL; + GpuNameStringCacheEntry *cachedParams = NULL; + + _cacheLockAcquire(LOCK_SHARED); + + if (rmapiControlCacheGetMode() == NV0000_CTRL_SYSTEM_RMCTRL_CACHE_MODE_CTRL_MODE_DISABLE) + { + // unexpected mode change. + status = NV_ERR_INVALID_STATE; + goto done; + } + + status = _rmapiControlCacheGetGpuInstForObject(hClient, hObject, &gpuInst); + if (status != NV_OK) + goto done; + + entry = _getOrInitCacheEntry(gpuInst, NV2080_CTRL_CMD_GPU_GET_NAME_STRING, + NV_FALSE, 0, NULL); + if (entry == NULL || entry->params == NULL) + { + status = NV_ERR_OBJECT_NOT_FOUND; + goto done; + } + + cachedParams = (GpuNameStringCacheEntry *)entry->params; + + switch (pParams->gpuNameStringFlags) + { + case NV2080_CTRL_GPU_GET_NAME_STRING_FLAGS_TYPE_ASCII: + if (!cachedParams->bAsciiValid) + { + status = NV_ERR_OBJECT_NOT_FOUND; + goto done; + } + portMemCopy(pParams->gpuNameString.ascii, + sizeof(pParams->gpuNameString.ascii), + cachedParams->ascii, + sizeof(pParams->gpuNameString.ascii)); + break; + + case NV2080_CTRL_GPU_GET_NAME_STRING_FLAGS_TYPE_UNICODE: + if (!cachedParams->bUnicodeValid) + { + status = NV_ERR_OBJECT_NOT_FOUND; + goto done; + } + portMemCopy(pParams->gpuNameString.unicode, + sizeof(pParams->gpuNameString.unicode), + cachedParams->unicode, + sizeof(pParams->gpuNameString.unicode)); + break; + + default: + NV_PRINTF(LEVEL_ERROR, "Unknown gpu name string flag: %u\n", pParams->gpuNameStringFlags); + status = NV_ERR_OBJECT_NOT_FOUND; + goto done; + } +done: + _cacheLockRelease(LOCK_SHARED); + return status; +} + +NV_STATUS _gpuNameStringSet +( + NvHandle hClient, + NvHandle hObject, + const NV2080_CTRL_GPU_GET_NAME_STRING_PARAMS *pParams +) +{ + NvU32 gpuInst; + NV_STATUS status; + RmapiControlCacheEntry *entry = NULL; + GpuNameStringCacheEntry *cachedParams = NULL; + + _cacheLockAcquire(LOCK_EXCLUSIVE); + + if (rmapiControlCacheGetMode() == NV0000_CTRL_SYSTEM_RMCTRL_CACHE_MODE_CTRL_MODE_DISABLE) + { + // unexpected mode change. + status = NV_ERR_INVALID_STATE; + goto done; + } + + status = _rmapiControlCacheGetGpuInstForObject(hClient, hObject, &gpuInst); + if (status != NV_OK) + goto done; + + entry = _getOrInitCacheEntry(gpuInst, NV2080_CTRL_CMD_GPU_GET_NAME_STRING, + NV_TRUE, sizeof(GpuNameStringCacheEntry), NULL); + if (entry == NULL) + { status = NV_ERR_NO_MEMORY; goto done; } - portMemCopy(entry->params, paramsSize, params, paramsSize); - NV_PRINTF(LEVEL_INFO, - "control cache set for 0x%x 0x%x 0x%x succeed, entry: %p\n", - hClient, hObject, cmd, entry); + cachedParams = (GpuNameStringCacheEntry *)entry->params; + + switch (pParams->gpuNameStringFlags) + { + case NV2080_CTRL_GPU_GET_NAME_STRING_FLAGS_TYPE_ASCII: + if (cachedParams->bAsciiValid) + { + NV_ASSERT( + portMemCmp(pParams->gpuNameString.ascii, + cachedParams->ascii, + sizeof(pParams->gpuNameString.ascii)) == 0); + } + else + { + portMemCopy(cachedParams->ascii, + sizeof(pParams->gpuNameString.ascii), + pParams->gpuNameString.ascii, + sizeof(pParams->gpuNameString.ascii)); + cachedParams->bAsciiValid = NV_TRUE; + } + break; + + case NV2080_CTRL_GPU_GET_NAME_STRING_FLAGS_TYPE_UNICODE: + if (cachedParams->bUnicodeValid) + { + NV_ASSERT( + portMemCmp(pParams->gpuNameString.unicode, + cachedParams->unicode, + sizeof(pParams->gpuNameString.unicode)) == 0); + } + else + { + portMemCopy(cachedParams->unicode, + sizeof(pParams->gpuNameString.unicode), + pParams->gpuNameString.unicode, + sizeof(pParams->gpuNameString.unicode)); + cachedParams->bUnicodeValid = NV_TRUE; + } + break; + + default: + NV_PRINTF(LEVEL_ERROR, "Unknown gpu name string flag: %u\n", pParams->gpuNameStringFlags); + status = NV_ERR_INVALID_PARAMETER; + goto done; + } done: if (status != NV_OK) { - /* To avoid leaking memory, remove the newly inserted empty submap and entry */ if (entry != NULL) { - portMemFree(entry->params); + if (entry->params) + portMemFree(entry->params); multimapRemoveItem(&RmapiControlCache.gpusControlCache, entry); } + } + _cacheLockRelease(LOCK_EXCLUSIVE); - if (insertedSubmap != NULL) - multimapRemoveSubmap(&RmapiControlCache.gpusControlCache, insertedSubmap); + return status; +} + +NV_STATUS _rmapiControlCacheGetByInput +( + NvHandle hClient, + NvHandle hObject, + NvU32 cmd, + void* params, + NvU32 paramsSize +) +{ + switch (cmd) + { + case NV2080_CTRL_CMD_GPU_GET_INFO_V2: + return _getInfoCacheHandler(hClient, hObject, cmd, + ((NV2080_CTRL_GPU_GET_INFO_V2_PARAMS*)params)->gpuInfoList, + ((NV2080_CTRL_GPU_GET_INFO_V2_PARAMS*)params)->gpuInfoListSize, + NV2080_CTRL_GPU_INFO_MAX_LIST_SIZE, + NV_FALSE); + + case NV2080_CTRL_CMD_FIFO_GET_INFO: + return _getInfoCacheHandler(hClient, hObject, cmd, + ((NV2080_CTRL_FIFO_GET_INFO_PARAMS*)params)->fifoInfoTbl, + ((NV2080_CTRL_FIFO_GET_INFO_PARAMS*)params)->fifoInfoTblSize, + NV2080_CTRL_FIFO_GET_INFO_MAX_ENTRIES, + NV_FALSE); + + case NV2080_CTRL_CMD_BUS_GET_INFO_V2: + return _getInfoCacheHandler(hClient, hObject, cmd, + ((NV2080_CTRL_BUS_GET_INFO_V2_PARAMS*)params)->busInfoList, + ((NV2080_CTRL_BUS_GET_INFO_V2_PARAMS*)params)->busInfoListSize, + NV2080_CTRL_BUS_INFO_MAX_LIST_SIZE, + NV_FALSE); + + case NV2080_CTRL_CMD_GPU_GET_NAME_STRING: + return _gpuNameStringGet(hClient, hObject, params); + default: + NV_PRINTF(LEVEL_WARNING, "No implementation for cacheable by input cmd 0x%x\n", cmd); + return NV_ERR_OBJECT_NOT_FOUND; + } +} + +NV_STATUS _rmapiControlCacheSetByInput +( + NvHandle hClient, + NvHandle hObject, + NvU32 cmd, + void* params, + NvU32 paramsSize +) +{ + switch (cmd) + { + case NV2080_CTRL_CMD_GPU_GET_INFO_V2: + return _getInfoCacheHandler(hClient, hObject, cmd, + ((NV2080_CTRL_GPU_GET_INFO_V2_PARAMS*)params)->gpuInfoList, + ((NV2080_CTRL_GPU_GET_INFO_V2_PARAMS*)params)->gpuInfoListSize, + NV2080_CTRL_GPU_INFO_MAX_LIST_SIZE, + NV_TRUE); + + case NV2080_CTRL_CMD_FIFO_GET_INFO: + return _getInfoCacheHandler(hClient, hObject, cmd, + ((NV2080_CTRL_FIFO_GET_INFO_PARAMS*)params)->fifoInfoTbl, + ((NV2080_CTRL_FIFO_GET_INFO_PARAMS*)params)->fifoInfoTblSize, + NV2080_CTRL_FIFO_GET_INFO_MAX_ENTRIES, + NV_TRUE); + + case NV2080_CTRL_CMD_BUS_GET_INFO_V2: + return _getInfoCacheHandler(hClient, hObject, cmd, + ((NV2080_CTRL_BUS_GET_INFO_V2_PARAMS*)params)->busInfoList, + ((NV2080_CTRL_BUS_GET_INFO_V2_PARAMS*)params)->busInfoListSize, + NV2080_CTRL_BUS_INFO_MAX_LIST_SIZE, + NV_TRUE); + + case NV2080_CTRL_CMD_GPU_GET_NAME_STRING: + return _gpuNameStringSet(hClient, hObject, params); + default: + NV_PRINTF(LEVEL_WARNING, "No implementation for cacheable by input cmd 0x%x\n", cmd); + return NV_ERR_OBJECT_NOT_FOUND; + } +} + +NV_STATUS rmapiControlCacheGet +( + NvHandle hClient, + NvHandle hObject, + NvU32 cmd, + void* params, + NvU32 paramsSize +) +{ + NV_STATUS status = NV_OK; + NvU32 flags = 0; + NvU32 ctrlParamsSize; + + if (RmapiControlCache.mode == NV0000_CTRL_SYSTEM_RMCTRL_CACHE_MODE_CTRL_MODE_VERIFY_ONLY) + return NV_ERR_OBJECT_NOT_FOUND; + + status = rmapiutilGetControlInfo(cmd, &flags, NULL, &ctrlParamsSize); + if (status != NV_OK) + goto done; + + NV_CHECK_OR_ELSE(LEVEL_ERROR, + (params != NULL && paramsSize == ctrlParamsSize), + status = NV_ERR_INVALID_PARAMETER; goto done); + + switch ((flags & RMCTRL_FLAGS_CACHEABLE_ANY)) + { + case RMCTRL_FLAGS_CACHEABLE: + status = _rmapiControlCacheGet(hClient, hObject, cmd, params, paramsSize); + break; + case RMCTRL_FLAGS_CACHEABLE_BY_INPUT: + status = _rmapiControlCacheGetByInput(hClient, hObject, cmd, params, paramsSize); + break; + default: + NV_PRINTF(LEVEL_ERROR, "Invalid cacheable flag 0x%x for cmd 0x%x\n", flags, cmd); + status = NV_ERR_INVALID_PARAMETER; + goto done; } - portSyncRwLockReleaseWrite(RmapiControlCache.pLock); +done: + NV_PRINTF(LEVEL_INFO, "control cache get for 0x%x 0x%x 0x%x status: 0x%x\n", hClient, hObject, cmd, status); + return status; +} +NV_STATUS rmapiControlCacheSet +( + NvHandle hClient, + NvHandle hObject, + NvU32 cmd, + void* params, + NvU32 paramsSize +) +{ + NV_STATUS status = NV_OK; + NvU32 flags = 0; + NvU32 ctrlParamsSize; + + status = rmapiutilGetControlInfo(cmd, &flags, NULL, &ctrlParamsSize); + if (status != NV_OK) + goto done; + + NV_CHECK_OR_ELSE(LEVEL_ERROR, + (params != NULL && paramsSize == ctrlParamsSize), + status = NV_ERR_INVALID_PARAMETER; goto done); + + switch ((flags & RMCTRL_FLAGS_CACHEABLE_ANY)) + { + case RMCTRL_FLAGS_CACHEABLE: + status = _rmapiControlCacheSet(hClient, hObject, cmd, params, paramsSize); + break; + case RMCTRL_FLAGS_CACHEABLE_BY_INPUT: + status = _rmapiControlCacheSetByInput(hClient, hObject, cmd, params, paramsSize); + break; + default: + NV_PRINTF(LEVEL_ERROR, "Invalid cacheable flag 0x%x for cmd 0x%x\n", flags, cmd); + status = NV_ERR_INVALID_PARAMETER; + goto done; + } + +done: + NV_PRINTF(LEVEL_INFO, "control cache set for 0x%x 0x%x 0x%x status: 0x%x\n", hClient, hObject, cmd, status); return status; } @@ -431,20 +1048,21 @@ { GpusControlCacheSubmap* submap; - portSyncRwLockAcquireWrite(RmapiControlCache.pLock); + _cacheLockAcquire(LOCK_EXCLUSIVE); + submap = multimapFindSubmap(&RmapiControlCache.gpusControlCache, gpuInst); if (submap != NULL) _freeSubmap(submap); - portSyncRwLockReleaseWrite(RmapiControlCache.pLock); + _cacheLockRelease(LOCK_EXCLUSIVE); } void rmapiControlCacheFreeClientEntry(NvHandle hClient) { - portSyncRwLockAcquireWrite(RmapiControlCache.pLock); + _cacheLockAcquire(LOCK_EXCLUSIVE); _rmapiControlCacheFreeGpuInstForClient(hClient); - portSyncRwLockReleaseWrite(RmapiControlCache.pLock); + _cacheLockRelease(LOCK_EXCLUSIVE); } void rmapiControlCacheFreeObjectEntry(NvHandle hClient, NvHandle hObject) @@ -455,9 +1073,9 @@ return; } - portSyncRwLockAcquireWrite(RmapiControlCache.pLock); + _cacheLockAcquire(LOCK_EXCLUSIVE); _rmapiControlCacheFreeGpuInstForObject(hClient, hObject); - portSyncRwLockReleaseWrite(RmapiControlCache.pLock); + _cacheLockRelease(LOCK_EXCLUSIVE); } void rmapiControlCacheFree(void) @@ -476,17 +1094,13 @@ portSyncRwLockDestroy(RmapiControlCache.pLock); } -// -// Changing cache mode cause race conditions on cacheability check and cache get/set. -// When the race condition happens, we may -// 1. Skip cache access when cache enabled -// 2. Access cache when cache disabled -// In the current design, these do not cause any error to the control data. -// void rmapiControlCacheSetMode(NvU32 mode) { NV_PRINTF(LEVEL_INFO, "Set rmapi control cache mode to 0x%x\n", mode); + + _cacheLockAcquire(LOCK_EXCLUSIVE); RmapiControlCache.mode = mode; + _cacheLockRelease(LOCK_EXCLUSIVE); } NvU32 rmapiControlCacheGetMode(void) diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/kernel/rmapi/rmapi_finn.c nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/kernel/rmapi/rmapi_finn.c --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/kernel/rmapi/rmapi_finn.c 1970-01-01 00:00:00.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/kernel/rmapi/rmapi_finn.c 2024-03-05 22:14:05.000000000 +0000 @@ -0,0 +1,609 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#include "resserv/resserv.h" +#include "rmapi/rmapi.h" + +#include "ctrl/ctrlxxxx.h" + +#include "g_finn_rm_api.h" + +/** + * Serialize parameters for servicing command + * + * If unserialized params are passed in, try to serialize into CALL_CONTEXT. + * If serialized params are passed in, set CALL_CONTEXT variables. + * + * Caller's parameters pointer and size will be overridden and restored on *CtrlUp call + */ +NV_STATUS +serverSerializeCtrlDown +( + CALL_CONTEXT *pCallContext, + NvU32 cmd, + void **ppParams, + NvU32 *pParamsSize, + NvU32 *flags +) +{ + if (!(*flags & NVOS54_FLAGS_FINN_SERIALIZED)) + { + NV_STATUS status; + NvU8 *pSerBuffer; + const NvU32 interface_id = (DRF_VAL(XXXX, _CTRL_CMD, _CLASS, cmd) << 8) | + DRF_VAL(XXXX, _CTRL_CMD, _CATEGORY, cmd); + const NvU32 message_id = DRF_VAL(XXXX, _CTRL_CMD, _INDEX, cmd); + NvU32 serializedSize = (NvU32)FinnRmApiGetSerializedSize(interface_id, message_id, *ppParams); + + pCallContext->pDeserializedParams = *ppParams; + pCallContext->deserializedSize = *pParamsSize; + + // Nothing to do if FINN doesn't support serializing this control + if (serializedSize == 0) + return NV_OK; + + // Assume we've already serialized if it exists + if (pCallContext->pSerializedParams != NULL) + { + NV_ASSERT_OR_RETURN(pCallContext->serializedSize == serializedSize, NV_ERR_INVALID_STATE); + return NV_OK; + } + else + { + pSerBuffer = portMemAllocNonPaged(serializedSize); + if (pSerBuffer == NULL) + return NV_ERR_INSUFFICIENT_RESOURCES; + + pCallContext->pSerializedParams = (FINN_RM_API *)pSerBuffer; + } + + status = FinnRmApiSerializeDown(interface_id, message_id, *ppParams, pSerBuffer, serializedSize); + + if (status != NV_OK) + { + NV_PRINTF(LEVEL_ERROR, + "Serialization failed for cmd 0x%06x with status %s (0x%02x)\n", + cmd, nvAssertStatusToString(status), status); + portMemFree(pCallContext->pSerializedParams); + pCallContext->pSerializedParams = NULL; + return status; + } + + pCallContext->serializedSize = serializedSize; + *flags |= NVOS54_FLAGS_FINN_SERIALIZED; + + // Override passed in parameters + *ppParams = pCallContext->pSerializedParams; + *pParamsSize = pCallContext->serializedSize; + pCallContext->bLocalSerialization = NV_TRUE; + } + else + { + // Params are already serialized, just copy them in + pCallContext->pSerializedParams = *ppParams; + pCallContext->serializedSize = *pParamsSize; + } + + return NV_OK; +} + +/** + * Deserialize parameters for servicing command + * + * If serialized params are passed in, deserialize them into CALL_CONTEXT. + * If deserialized params are passed in, set CALL_CONTEXT variables. + * + * Caller's parameters pointer and size will be overridden and restored on *CtrlUp call + */ +NV_STATUS +serverDeserializeCtrlDown +( + CALL_CONTEXT *pCallContext, + NvU32 cmd, + void **ppParams, + NvU32 *pParamsSize, + NvU32 *flags +) +{ + if (*flags & NVOS54_FLAGS_FINN_SERIALIZED) + { + NV_STATUS status; + NvU8 *pSerBuffer; + void *pDeserParams; + const NvU32 interface_id = (DRF_VAL(XXXX, _CTRL_CMD, _CLASS, cmd) << 8) | + DRF_VAL(XXXX, _CTRL_CMD, _CATEGORY, cmd); + const NvU32 message_id = DRF_VAL(XXXX, _CTRL_CMD, _INDEX, cmd); + NvU32 unserializedSize = (NvU32)FinnRmApiGetUnserializedSize(interface_id, message_id); + + // Report error if FINN can't deserialize but RM is reporting the control as serialized + if (unserializedSize == 0) + return NV_ERR_LIB_RM_VERSION_MISMATCH; + + // Assume we've already deserialized if it exists + if (pCallContext->pDeserializedParams != NULL) + { + NV_ASSERT_OR_RETURN(pCallContext->deserializedSize == unserializedSize, NV_ERR_INVALID_STATE); + return NV_OK; + } + else + { + pDeserParams = portMemAllocNonPaged(unserializedSize); + if (pDeserParams == NULL) + return NV_ERR_INSUFFICIENT_RESOURCES; + + pCallContext->pDeserializedParams = pDeserParams; + } + + pSerBuffer = (NvU8 *)*ppParams; + + status = FinnRmApiDeserializeDown(pSerBuffer, *pParamsSize, pDeserParams, unserializedSize); + + if (status != NV_OK) + { + NV_PRINTF(LEVEL_ERROR, + "Deserialization failed for cmd 0x%06x with status %s (0x%02x)\n", + cmd, nvAssertStatusToString(status), status); + portMemFree(pCallContext->pDeserializedParams); + pCallContext->pDeserializedParams = NULL; + return status; + } + + pCallContext->deserializedSize = unserializedSize; + pCallContext->pSerializedParams = *ppParams; + pCallContext->serializedSize = *pParamsSize; + + // Override passed in parameters + *ppParams = pCallContext->pDeserializedParams; + *pParamsSize = pCallContext->deserializedSize; + } + else + { + // Not serialized, copy into deser params + pCallContext->pDeserializedParams = *ppParams; + pCallContext->deserializedSize = *pParamsSize; + } + + // Automatically request reserialization in case the control goes to GSP + pCallContext->bReserialize = NV_TRUE; + + return NV_OK; +} + +/** + * Serialize parameters for returning from command + * + * If serialized params are passed in, serialize into them from CALL_CONTEXT deserialized params. + * If deserialized params are passed in, unset the serialized flag. We expect that this means that + * the parameters were serialized locally and not by the caller. + * + * Caller's parameters pointer and size will be restored from *CtrlDown call + */ +NV_STATUS +serverSerializeCtrlUp +( + CALL_CONTEXT *pCallContext, + NvU32 cmd, + void **ppParams, + NvU32 *pParamsSize, + NvU32 *flags +) +{ + // + // We add NVOS54_FLAGS_FINN_SERIALIZED if the control can be serialized but wasn't in serverSerializeCtrlDown + // We don't want to return a serialized buffer if one wasn't given to us in the first place + // + if ((*flags & NVOS54_FLAGS_FINN_SERIALIZED) && !pCallContext->bLocalSerialization) + { + NV_STATUS status; + NvU8 *pSerBuffer; + void *pDeserBuffer; + const NvU32 interface_id = (DRF_VAL(XXXX, _CTRL_CMD, _CLASS, cmd) << 8) | + DRF_VAL(XXXX, _CTRL_CMD, _CATEGORY, cmd); + const NvU32 message_id = DRF_VAL(XXXX, _CTRL_CMD, _INDEX, cmd); + + // Should be serialized at this point. Expect that serializedSize is set otherwise something is wrong + if (pCallContext->serializedSize == 0) + return NV_ERR_INVALID_STATE; + + pSerBuffer = (NvU8 *) pCallContext->pSerializedParams; + pDeserBuffer = (NvU8 *) pCallContext->pDeserializedParams; + + if (pSerBuffer == NULL) + return NV_ERR_INVALID_STATE; + + // It's possible that we have nothing to do if we're just passing parameters along + if (pDeserBuffer == NULL) + return NV_OK; + + status = FinnRmApiSerializeUp(interface_id, message_id, pDeserBuffer, pSerBuffer, pCallContext->serializedSize); + if (status != NV_OK) + { + NV_PRINTF(LEVEL_ERROR, + "Serialization failed for cmd 0x%06x with status %s (0x%02x)\n", + cmd, nvAssertStatusToString(status), status); + return status; + } + + *ppParams = pCallContext->pSerializedParams; + *pParamsSize = pCallContext->serializedSize; + } + else if (*flags & NVOS54_FLAGS_FINN_SERIALIZED) + { + // We serialized the control. Unset the flag + *flags &= ~NVOS54_FLAGS_FINN_SERIALIZED; + } + + return NV_OK; +} + +/** + * Deserialize parameters for returning from command + * + * If serialized params are passed in with the serialized flag set, do nothing. We expect this means we are just + * passing along the parameters to another layer. + * If deserialized params are passed in with the serialized flag set, unset flag and deserialize into params. + * We expect that this means that the parameters were serialized locally and not by the caller. + * If deserialized params are passed in without the flag set just copy to CALL_CONTEXT + * + * Caller's parameters pointer and size will be restored from *CtrlDown call + */ +NV_STATUS +serverDeserializeCtrlUp +( + CALL_CONTEXT *pCallContext, + NvU32 cmd, + void **ppParams, + NvU32 *pParamsSize, + NvU32 *flags +) +{ + if (*flags & NVOS54_FLAGS_FINN_SERIALIZED) + { + NV_STATUS status; + NvU8 *pSerBuffer; + void *pDeserBuffer; + const NvU32 interface_id = (DRF_VAL(XXXX, _CTRL_CMD, _CLASS, cmd) << 8) | + DRF_VAL(XXXX, _CTRL_CMD, _CATEGORY, cmd); + const NvU32 message_id = DRF_VAL(XXXX, _CTRL_CMD, _INDEX, cmd); + NvU32 unserializedSize = (NvU32)FinnRmApiGetUnserializedSize(interface_id, message_id); + + if (!pCallContext->bLocalSerialization) + { + // We didn't serialize down, so don't deserialize up + return NV_OK; + } + else + { + // Serialized, but not passing back up serialized params, clear flag + *flags &= ~NVOS54_FLAGS_FINN_SERIALIZED; + } + + // Report error if FINN can't deserialize but RM is reporting the control as serialized + if (unserializedSize == 0) + return NV_ERR_LIB_RM_VERSION_MISMATCH; + + // DeserializeUp expects pointers to be set up already + pDeserBuffer = pCallContext->pDeserializedParams; + if (pDeserBuffer == NULL) + return NV_ERR_INVALID_STATE; + + pSerBuffer = (NvU8 *) pCallContext->pSerializedParams; + if (pSerBuffer == NULL) + return NV_ERR_INVALID_STATE; + + status = FinnRmApiDeserializeUp(pSerBuffer, pCallContext->serializedSize, pDeserBuffer, unserializedSize); + + if (status != NV_OK) + { + NV_PRINTF(LEVEL_ERROR, + "Deserialization failed for cmd 0x%06x with status %s (0x%02x)\n", + cmd, nvAssertStatusToString(status), status); + return status; + } + + pCallContext->deserializedSize = unserializedSize; + + *ppParams = pCallContext->pDeserializedParams; + *pParamsSize = pCallContext->deserializedSize; + } + + return NV_OK; +} + +NV_STATUS +serverSerializeAllocDown +( + CALL_CONTEXT *pCallContext, + NvU32 classId, + void **ppParams, + NvU32 *pParamsSize, + NvU32 *flags +) +{ + const NvU32 interface_id = NV_RM_ALLOC_INTERFACE_INTERFACE_ID; + const NvU32 message_id = classId; + if (!(*flags & RMAPI_ALLOC_FLAGS_SERIALIZED)) + { + NV_STATUS status; + NvU8 *pSerBuffer; + NvU32 serializedSize = (NvU32)FinnRmApiGetSerializedSize(interface_id, message_id, *ppParams); + + pCallContext->pDeserializedParams = *ppParams; + pCallContext->deserializedSize = *pParamsSize; + + // Nothing to do if FINN doesn't support serializing this allocation + if (serializedSize == 0) + return NV_OK; + + // Assume we've already serialized if it exists + if (pCallContext->pSerializedParams != NULL) + { + NV_ASSERT_OR_RETURN(pCallContext->serializedSize == serializedSize, NV_ERR_INVALID_STATE); + return NV_OK; + } + else + { + pSerBuffer = portMemAllocNonPaged(serializedSize); + if (pSerBuffer == NULL) + return NV_ERR_INSUFFICIENT_RESOURCES; + + pCallContext->pSerializedParams = (FINN_RM_API *)pSerBuffer; + } + + status = FinnRmApiSerializeDown(interface_id, message_id, *ppParams, pSerBuffer, serializedSize); + + if (status != NV_OK) + { + NV_PRINTF(LEVEL_ERROR, + "Serialization failed for classId 0x%06x with status %s (0x%02x)\n", + classId, nvAssertStatusToString(status), status); + portMemFree(pCallContext->pSerializedParams); + pCallContext->pSerializedParams = NULL; + return status; + } + + pCallContext->serializedSize = serializedSize; + *flags |= RMAPI_ALLOC_FLAGS_SERIALIZED; + *ppParams = pCallContext->pSerializedParams; + *pParamsSize = serializedSize; + pCallContext->bLocalSerialization = NV_TRUE; + } + else + { + // Params are already serialized, just copy them in + pCallContext->pSerializedParams = *ppParams; + pCallContext->serializedSize = *pParamsSize; + } + + return NV_OK; +} + + +NV_STATUS +serverDeserializeAllocDown +( + CALL_CONTEXT *pCallContext, + NvU32 classId, + void **ppParams, + NvU32 *pParamsSize, + NvU32 *flags +) +{ + const NvU32 interface_id = NV_RM_ALLOC_INTERFACE_INTERFACE_ID; + const NvU32 message_id = classId; + if (*flags & RMAPI_ALLOC_FLAGS_SERIALIZED) + { + NV_STATUS status; + NvU8 *pSerBuffer; + void *pDeserParams; + NvU32 unserializedSize = (NvU32)FinnRmApiGetUnserializedSize(interface_id, message_id); + + // Report error if FINN can't deserialize but RM is reporting the alloc as serialized + if (unserializedSize == 0) + return NV_ERR_LIB_RM_VERSION_MISMATCH; + + // Assume we've already deserialized if it exists + if (pCallContext->pDeserializedParams != NULL) + { + NV_ASSERT_OR_RETURN(pCallContext->deserializedSize == unserializedSize, NV_ERR_INVALID_STATE); + return NV_OK; + } + else + { + pDeserParams = portMemAllocNonPaged(unserializedSize); + if (pDeserParams == NULL) + return NV_ERR_INSUFFICIENT_RESOURCES; + + pCallContext->pDeserializedParams = pDeserParams; + } + + pSerBuffer = (NvU8 *)*ppParams; + + status = FinnRmApiDeserializeDown(pSerBuffer, *pParamsSize, pDeserParams, unserializedSize); + + if (status != NV_OK) + { + NV_PRINTF(LEVEL_ERROR, + "Deserialization failed for classId 0x%06x with status %s (0x%02x)\n", + classId, nvAssertStatusToString(status), status); + portMemFree(pCallContext->pDeserializedParams); + pCallContext->pDeserializedParams = NULL; + return status; + } + + pCallContext->serializedSize = *pParamsSize; + pCallContext->deserializedSize = unserializedSize; + pCallContext->pSerializedParams = *ppParams; + + *ppParams = pCallContext->pDeserializedParams; + *pParamsSize = pCallContext->deserializedSize; + } + else + { + // Not serialized, copy into deser params + pCallContext->pDeserializedParams = *ppParams; + pCallContext->deserializedSize = *pParamsSize; + } + + // Automatically request reserialization in case the alloc goes to GSP + pCallContext->bReserialize = NV_TRUE; + + return NV_OK; +} + +NV_STATUS +serverSerializeAllocUp +( + CALL_CONTEXT *pCallContext, + NvU32 classId, + void **ppParams, + NvU32 *pParamsSize, + NvU32 *flags +) +{ + // + // We add RMAPI_ALLOC_FLAGS_SERIALIZED if the alloc can be serialized but wasn't in serverSerializeAllocDown + // We don't want to return a serialized buffer if one wasn't given to us in the first place + // Check if pSerializedParams matches pParams to make sure the caller expects serialized info returned + // + if ((*flags & RMAPI_ALLOC_FLAGS_SERIALIZED) && !pCallContext->bLocalSerialization) + { + NV_STATUS status; + NvU8 *pSerBuffer; + void *pDeserBuffer; + const NvU32 interface_id = NV_RM_ALLOC_INTERFACE_INTERFACE_ID; + const NvU32 message_id = classId; + + // Should be serialized at this point. Expect that serializedSize is set otherwise something is wrong + if (pCallContext->serializedSize == 0) + return NV_ERR_INVALID_STATE; + + pSerBuffer = (NvU8 *) pCallContext->pSerializedParams; + pDeserBuffer = (NvU8 *) pCallContext->pDeserializedParams; + + if (pSerBuffer == NULL) + return NV_ERR_INVALID_STATE; + + // It's possible that we have nothing to do if we're just passing parameters along + if (pDeserBuffer == NULL) + return NV_OK; + + status = FinnRmApiSerializeUp(interface_id, message_id, pDeserBuffer, pSerBuffer, pCallContext->serializedSize); + if (status != NV_OK) + { + NV_PRINTF(LEVEL_ERROR, + "Serialization failed for classId 0x%06x with status %s (0x%02x)\n", + classId, nvAssertStatusToString(status), status); + return status; + } + + *ppParams = pCallContext->pSerializedParams; + *pParamsSize = pCallContext->serializedSize; + } + else if (*flags & RMAPI_ALLOC_FLAGS_SERIALIZED) + { + // We serialized the alloc. Unset the flag + *flags &= ~RMAPI_ALLOC_FLAGS_SERIALIZED; + } + + return NV_OK; +} + +NV_STATUS +serverDeserializeAllocUp +( + CALL_CONTEXT *pCallContext, + NvU32 classId, + void **ppParams, + NvU32 *pParamsSize, + NvU32 *flags +) +{ + const NvU32 interface_id = NV_RM_ALLOC_INTERFACE_INTERFACE_ID; + const NvU32 message_id = classId; + if (*flags & RMAPI_ALLOC_FLAGS_SERIALIZED) + { + NV_STATUS status; + NvU8 *pSerBuffer; + void *pDeserBuffer; + NvU32 unserializedSize = (NvU32)FinnRmApiGetUnserializedSize(interface_id, message_id); + + if (!pCallContext->bLocalSerialization) + { + // We didn't serialize down, so don't deserialize up + return NV_OK; + } + else + { + // Serialized, but not passing back up serialized params, clear flag + *flags &= ~RMAPI_ALLOC_FLAGS_SERIALIZED; + } + + // Report error if FINN can't deserialize but RM is reporting the alloc as serialized + if (unserializedSize == 0) + return NV_ERR_LIB_RM_VERSION_MISMATCH; + + // DeserializeUp expects pointers to be set up already + pDeserBuffer = pCallContext->pDeserializedParams; + if (pDeserBuffer == NULL) + return NV_ERR_INVALID_STATE; + + pSerBuffer = (NvU8 *) pCallContext->pSerializedParams; + if (pSerBuffer == NULL) + return NV_ERR_INVALID_STATE; + + status = FinnRmApiDeserializeUp(pSerBuffer, pCallContext->serializedSize, pDeserBuffer, unserializedSize); + + if (status != NV_OK) + { + NV_PRINTF(LEVEL_ERROR, + "Deserialization failed for classId 0x%06x with status %s (0x%02x)\n", + classId, nvAssertStatusToString(status), status); + return status; + } + + pCallContext->deserializedSize = unserializedSize; + *ppParams = pCallContext->pDeserializedParams; + *pParamsSize = unserializedSize; + } + + return NV_OK; +} + +void +serverFreeSerializeStructures +( + CALL_CONTEXT *pCallContext, + void *pParams +) +{ + if (pCallContext->pSerializedParams != pParams) + portMemFree(pCallContext->pSerializedParams); + if (pCallContext->pDeserializedParams != pParams) + portMemFree(pCallContext->pDeserializedParams); + + pCallContext->pSerializedParams = NULL; + pCallContext->pDeserializedParams = NULL; + pCallContext->serializedSize = 0; + pCallContext->deserializedSize = 0; +} diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/kernel/rmapi/rmapi_stubs.c nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/kernel/rmapi/rmapi_stubs.c --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/kernel/rmapi/rmapi_stubs.c 2023-10-25 20:21:32.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/kernel/rmapi/rmapi_stubs.c 2024-03-05 22:14:05.000000000 +0000 @@ -24,19 +24,19 @@ static NV_STATUS _rmapiAlloc_STUB(RM_API *pRmApi, NvHandle hClient, NvHandle hParent, - NvHandle *phObject, NvU32 hClass, void *pAllocParams) + NvHandle *phObject, NvU32 hClass, void *pAllocParams, NvU32 paramsSize) { return NV_ERR_NOT_SUPPORTED; } static NV_STATUS _rmapiAllocWithHandle_STUB(RM_API *pRmApi, NvHandle hClient, NvHandle hParent, - NvHandle hObject, NvU32 hClass, void *pAllocParams) + NvHandle hObject, NvU32 hClass, void *pAllocParams, NvU32 paramsSize) { return NV_ERR_NOT_SUPPORTED; } static NV_STATUS _rmapiAllocWithSecInfo_STUB(RM_API *pRmApi, NvHandle hClient, NvHandle hParent, - NvHandle *phObject, NvU32 hClass, NvP64 pAllocParams, + NvHandle *phObject, NvU32 hClass, NvP64 pAllocParams, NvU32 paramsSize, NvU32 flags, NvP64 pRightsRequested, API_SECURITY_INFO *pSecInfo) { return NV_ERR_NOT_SUPPORTED; @@ -53,12 +53,12 @@ return NV_ERR_NOT_SUPPORTED; } -static NV_STATUS _rmapiFreeClientList_STUB(RM_API *pRmApi, NvHandle *phClientList, NvU32 numClients) +static NV_STATUS _rmapiDisableClients_STUB(RM_API *pRmApi, NvHandle *phClientList, NvU32 numClients) { return NV_ERR_NOT_SUPPORTED; } -static NV_STATUS _rmapiFreeClientListWithSecInfo_STUB(RM_API *pRmApi, NvHandle *phClientList, +static NV_STATUS _rmapiDisableClientsWithSecInfo_STUB(RM_API *pRmApi, NvHandle *phClientList, NvU32 numClients, API_SECURITY_INFO *pSecInfo) { return NV_ERR_NOT_SUPPORTED; @@ -163,8 +163,8 @@ pRmApi->AllocWithSecInfo = _rmapiAllocWithSecInfo_STUB; pRmApi->Free = _rmapiFree_STUB; pRmApi->FreeWithSecInfo = _rmapiFreeWithSecInfo_STUB; - pRmApi->FreeClientList = _rmapiFreeClientList_STUB; - pRmApi->FreeClientListWithSecInfo = _rmapiFreeClientListWithSecInfo_STUB; + pRmApi->DisableClients = _rmapiDisableClients_STUB; + pRmApi->DisableClientsWithSecInfo = _rmapiDisableClientsWithSecInfo_STUB; pRmApi->Control = _rmapiControl_STUB; pRmApi->ControlWithSecInfo = _rmapiControlWithSecInfo_STUB; pRmApi->ControlPrefetch = _rmapiControlPrefetch_STUB; diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/kernel/rmapi/rmapi_utils.c nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/kernel/rmapi/rmapi_utils.c --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/kernel/rmapi/rmapi_utils.c 2023-10-25 20:21:32.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/kernel/rmapi/rmapi_utils.c 2024-03-05 22:14:05.000000000 +0000 @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 2020-2020 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2020-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -57,7 +57,8 @@ NV01_NULL_OBJECT, NV01_NULL_OBJECT, NV01_ROOT, - &hClient), + &hClient, + sizeof(hClient)), cleanup); // Allocate a device @@ -75,7 +76,8 @@ hClient, hDevice, NV01_DEVICE_0, - &nv0080AllocParams), + &nv0080AllocParams, + sizeof(nv0080AllocParams)), cleanup); // Allocate a subDevice @@ -92,7 +94,8 @@ hDevice, hSubDevice, NV20_SUBDEVICE_0, - &nv2080AllocParams), + &nv2080AllocParams, + sizeof(nv2080AllocParams)), cleanup); *phClient = hClient; @@ -152,7 +155,8 @@ ( NvU32 cmd, NvU32 *pFlags, - NvU32 *pAccessRight + NvU32 *pAccessRight, + NvU32 *pParamsSize ) { RS_RESOURCE_DESC *pResourceDesc = RsResInfoByExternalClassId(DRF_VAL(XXXX, _CTRL_CMD, _CLASS, cmd)); @@ -173,6 +177,9 @@ if (pAccessRight != NULL) *pAccessRight = pMethodDef->accessRight; + if (pParamsSize != NULL) + *pParamsSize = pMethodDef->paramSize; + return NV_OK; } } diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/kernel/rmapi/rpc_common.c nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/kernel/rmapi/rpc_common.c --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/kernel/rmapi/rpc_common.c 2023-10-25 20:21:32.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/kernel/rmapi/rpc_common.c 2024-03-05 22:14:06.000000000 +0000 @@ -49,7 +49,7 @@ #undef RPC_MESSAGE_STRUCTURES #undef RPC_MESSAGE_GENERIC_UNION -void rpcRmApiSetup(OBJGPU *pGpu) +static void rpcRmApiSetup(OBJGPU *pGpu) { // // Physical RMAPI is already initialized for monolithic, and this function diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/kernel/rmapi/rs_utils.c nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/kernel/rmapi/rs_utils.c --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/kernel/rmapi/rs_utils.c 2023-10-25 20:21:32.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/kernel/rmapi/rs_utils.c 2024-03-05 22:14:06.000000000 +0000 @@ -101,28 +101,20 @@ return NV_OK; } -NV_STATUS -serverutilGetClientUnderLock +RmClient +*serverutilGetClientUnderLock ( - NvHandle hClient, - RmClient **ppClient + NvHandle hClient ) { NV_STATUS status; RsClient *pRsClient; - RmClient *pClient; status = serverGetClientUnderLock(&g_resServ, hClient, &pRsClient); if (status != NV_OK) - return status; - - pClient = dynamicCast(pRsClient, RmClient); - NV_ASSERT(pClient != NULL); - - if (ppClient) - *ppClient = pClient; + return NULL; - return NV_OK; + return dynamicCast(pRsClient, RmClient); } RmClient @@ -238,9 +230,9 @@ NvHandle hObject ) { - RmClient *pClient; + RmClient *pClient = serverutilGetClientUnderLock(hClient); - return ((NV_OK == serverutilGetClientUnderLock(hClient, &pClient)) && + return ((pClient != NULL) && (NV_OK == clientValidateNewResourceHandle(staticCast(pClient, RsClient), hObject, NV_TRUE))); } @@ -257,7 +249,9 @@ // LOCK TEST: we should have the API lock here LOCK_ASSERT_AND_RETURN(rmapiLockIsOwner()); - if (NV_OK != serverutilGetClientUnderLock(hClient, &pClient)) + pClient = serverutilGetClientUnderLock(hClient); + + if (pClient == NULL) return NV_ERR_INVALID_CLIENT; status = clientGenResourceHandle(staticCast(pClient, RsClient), returnHandle); diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/kernel/virtualization/common_vgpu_mgr.c nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/kernel/virtualization/common_vgpu_mgr.c --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/kernel/virtualization/common_vgpu_mgr.c 2023-10-25 20:21:32.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/kernel/virtualization/common_vgpu_mgr.c 2024-03-05 22:14:06.000000000 +0000 @@ -22,6 +22,8 @@ */ #include "virtualization/common_vgpu_mgr.h" +#include "virtualization/hypervisor/hypervisor.h" + #include "ctrl/ctrl2080/ctrl2080gpu.h" void @@ -36,6 +38,7 @@ VGPU_TYPE *vgpuTypeInfo, NvU32 gfid, NvU32 *pChidOffset, + NvU32 *pChannelCount, NvHandle hClient, NvU32 numChannels, NvU32 engineFifoListNumEntries, @@ -51,6 +54,7 @@ OBJGPU *pGpu, NvU32 gfid, NvU32 *pChidOffset, + NvU32 *pChannelCount, NvHandle hClient, NvU32 engineFifoListNumEntries, FIFO_ENGINE_LIST *engineFifoList diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/kernel/virtualization/hypervisor/hypervisor.c nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/kernel/virtualization/hypervisor/hypervisor.c --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/kernel/virtualization/hypervisor/hypervisor.c 2023-10-25 20:21:33.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/kernel/virtualization/hypervisor/hypervisor.c 2024-03-05 22:14:06.000000000 +0000 @@ -33,7 +33,7 @@ static HYPERVISOR_OPS _hypervisorOps[OS_HYPERVISOR_UNKNOWN]; -static NV_STATUS _hypervisorDetection_HVM(OBJHYPERVISOR *, OBJOS *, NvU32 *); +static NV_STATUS _hypervisorDetection_HVM(OBJHYPERVISOR *, OBJOS *); static NvBool _hypervisorCheckVirtualPcieP2PApproval(OBJHYPERVISOR *, NvU32); // Because M$ compiler doesn't support C99 we have to initialize @@ -63,8 +63,6 @@ return NV_OK; } -static NvU32 _leaf; - NvBool hypervisorPcieP2pDetection_IMPL ( OBJHYPERVISOR *pHypervisor, @@ -91,7 +89,7 @@ if (hypervisorIsVgxHyper()) goto found_one; - if ((rmStatus = _hypervisorDetection_HVM(pHypervisor, pOS, &_leaf)) != NV_OK) + if ((rmStatus = _hypervisorDetection_HVM(pHypervisor, pOS)) != NV_OK) return rmStatus; if ((rmStatus = _hypervisorOps[pHypervisor->type].hypervisorPostDetection(pOS, &pHypervisor->bIsHVMGuest)) != NV_OK) @@ -123,15 +121,13 @@ static NV_STATUS _hypervisorDetection_HVM ( OBJHYPERVISOR *pHypervisor, - OBJOS *pOS, - NvU32 *pLeaf + OBJOS *pOS ) { +#if defined(NVCPU_X86_64) NvU32 i = 0, base, eax = 0; NvU32 vmmSignature[3]; - - NV_ASSERT_OR_RETURN(pLeaf, NV_ERR_INVALID_ARGUMENT); - *pLeaf = 0; + NvU32 leaf = 0; for (base = 0x40000000; base < 0x40001000; base += 0x100) { @@ -153,16 +149,103 @@ if (!portMemCmp(_hypervisorOps[i].hypervisorSig, vmmSignature, sizeof(vmmSignature))) { - if (base > *pLeaf) + if (base > leaf) { - *pLeaf = base; + leaf = base; pHypervisor->type = i; } } } } - return *pLeaf ? NV_OK : NV_ERR_NOT_SUPPORTED; + return leaf ? NV_OK : NV_ERR_NOT_SUPPORTED; +#elif defined(NVCPU_AARCH64) + void *pSmbiosTable = NULL; + NvU8 *tableStart = NULL; + NvU64 i = 0; + NvU64 totalLength = 0; + NvU64 numSubTypes; + NvU32 version; + NvBool bIsVM = NV_FALSE; + + if (osGetSmbiosTable(&pSmbiosTable, &totalLength, &numSubTypes, &version) != NV_OK) + { + NV_PRINTF(LEVEL_WARNING, "SMBIOS is NOT supported!\n"); + return NV_ERR_NOT_SUPPORTED; + } + + NV_ASSERT_OR_RETURN(pSmbiosTable, NV_ERR_INVALID_POINTER); + tableStart = (NvU8 *)pSmbiosTable; + + // Traverse SMBIOS table to locate 'BIOS Information (Type 0)' struct + while (i < totalLength) + { + NvU8 *structStart; + NvU8 structType; + NvU8 structLength; + + // SMBIOS Spec: https://www.dmtf.org/sites/default/files/standards/documents/DSP0134_3.4.0.pdf + // Each SMBIOS struct has a formatted section followed by optional strings section. + // type of struct is at byte offset 0. + // length of formatted section is at byte offset 1. + // optional strings section starts at byte offset structLength. + // struct end is marked with two null bytes. + + if ((i + 2ULL) <= totalLength) + { + structStart = &tableStart[i]; + structType = structStart[0]; + structLength = structStart[1]; + } + else + { + break; + } + + if (structType == 0x7f) + { + // 'End-of-Table (Type 127)' struct reached, stop traversing further. + break; + } + + // traverse formatted section + i += structLength; + + // traverse optional strings section until start of two null bytes + while (((i + 2ULL) <= totalLength) && (tableStart[i] || tableStart[i + 1])) + i++; + + // ensure that entire struct (including last two null bytes) is within tableLength + if ((i + 2ULL) <= totalLength) + { + if (structType == 0x0) + { + // found 'BIOS Information (Type 0)' struct. + // check Bit 4 of 'BIOS Characteristics Extention Byte 2' - offset 0x13 + if ((structLength > 0x13) && (structStart[0x13] & NVBIT(4))) + { + bIsVM = NV_TRUE; + } + break; + } + } + + // traverse over two null bytes at end of a struct + i += 2; + } + + osPutSmbiosTable(pSmbiosTable, totalLength); + + if (bIsVM) + { + pHypervisor->type = OS_HYPERVISOR_KVM; + return NV_OK; + } + + return NV_ERR_NOT_SUPPORTED; +#else + return NV_ERR_NOT_SUPPORTED; +#endif } HYPERVISOR_TYPE hypervisorGetHypervisorType_IMPL(OBJHYPERVISOR *pHypervisor) @@ -172,6 +255,12 @@ return OS_HYPERVISOR_UNKNOWN; } +void hypervisorSetHypervisorType_IMPL(OBJHYPERVISOR *pHypervisor, HYPERVISOR_TYPE type) +{ + pHypervisor->type = type; + pHypervisor->bDetected = type != OS_HYPERVISOR_UNKNOWN; +} + static NvBool _hypervisorCheckVirtualPcieP2PApproval ( OBJHYPERVISOR *pHypervisor, diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/kernel/virtualization/kernel_hostvgpudeviceapi.c nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/kernel/virtualization/kernel_hostvgpudeviceapi.c --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/kernel/virtualization/kernel_hostvgpudeviceapi.c 2023-10-25 20:21:33.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/kernel/virtualization/kernel_hostvgpudeviceapi.c 2024-03-05 22:14:07.000000000 +0000 @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 2021-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2021-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -179,20 +179,19 @@ } NV_STATUS -kernelhostvgpudeviceapiCtrlCmdSetSriovState_IMPL +kernelhostvgpudeviceapiCtrlCmdGetBarMappingRanges_IMPL ( KernelHostVgpuDeviceApi *pKernelHostVgpuDeviceApi, - NVA084_CTRL_KERNEL_HOST_VGPU_DEVICE_SET_SRIOV_STATE_PARAMS *pSetSriovStateParams + NVA084_CTRL_KERNEL_HOST_VGPU_DEVICE_GET_BAR_MAPPING_RANGES_PARAMS *pParams ) { return NV_ERR_NOT_SUPPORTED; } NV_STATUS -kernelhostvgpudeviceapiCtrlCmdSetGuestId_IMPL +kernelhostvgpudeviceapiCtrlCmdRestoreDefaultExecPartition_IMPL ( - KernelHostVgpuDeviceApi *pKernelHostVgpuDeviceApi, - NVA084_CTRL_KERNEL_HOST_VGPU_DEVICE_SET_GUEST_ID_PARAMS *pParams + KernelHostVgpuDeviceApi *pKernelHostVgpuDeviceApi ) { return NV_ERR_NOT_SUPPORTED; diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/kernel/virtualization/kernel_vgpu_mgr.c nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/kernel/virtualization/kernel_vgpu_mgr.c --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/kernel/virtualization/kernel_vgpu_mgr.c 2023-10-25 20:21:33.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/kernel/virtualization/kernel_vgpu_mgr.c 2024-03-05 22:14:07.000000000 +0000 @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 2012-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2012-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -111,14 +111,14 @@ /* * @brief Sets Guest(VM) ID for the requested hostvgpudevice * - * @param pParams NVA084_CTRL_KERNEL_HOST_VGPU_DEVICE_SET_GUEST_ID_PARAMS Pointer + * @param pParams SET_GUEST_ID_PARAMS Pointer * @param pKernelHostVgpuDevice Device for which Vm ID need to be set * @param pGpu OBJGPU pointer * * @return NV_STATUS */ NV_STATUS -kvgpumgrRegisterGuestId(NVA084_CTRL_KERNEL_HOST_VGPU_DEVICE_SET_GUEST_ID_PARAMS *pParams, +kvgpumgrRegisterGuestId(SET_GUEST_ID_PARAMS *pParams, KERNEL_HOST_VGPU_DEVICE *pKernelHostVgpuDevice, OBJGPU *pGpu) { return NV_ERR_NOT_SUPPORTED; @@ -215,6 +215,14 @@ } NV_STATUS +kvgpumgrValidateSwizzId(OBJGPU *pGpu, + NvU32 vgpuTypeId, + NvU32 swizzId) +{ + return NV_ERR_NOT_SUPPORTED; +} + +NV_STATUS kvgpumgrGetPartitionFlag(NvU32 vgpuTypeId, NvU32 *partitionFlag) { return NV_ERR_INVALID_ARGUMENT; @@ -317,3 +325,14 @@ { return NV_ERR_OBJECT_NOT_FOUND; } + +NV_STATUS +kvgpuMgrRestoreSmcExecPart +( + OBJGPU *pGpu, + KERNEL_HOST_VGPU_DEVICE *pKernelHostVgpuDevice, + KERNEL_MIG_GPU_INSTANCE *pKernelMIGGpuInstance +) +{ + return NV_ERR_NOT_SUPPORTED; +} diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/kernel/virtualization/vgpuconfigapi.c nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/kernel/virtualization/vgpuconfigapi.c --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/kernel/virtualization/vgpuconfigapi.c 2023-10-25 20:21:33.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/kernel/virtualization/vgpuconfigapi.c 2024-03-05 22:14:07.000000000 +0000 @@ -231,3 +231,14 @@ { return NV_ERR_NOT_SUPPORTED; } + +NV_STATUS +vgpuconfigapiCtrlCmdVgpuConfigValidateSwizzId_IMPL +( + VgpuConfigApi *pVgpuConfigApi, + NVA081_CTRL_VGPU_CONFIG_VALIDATE_SWIZZID_PARAMS *pParams +) +{ + return NV_ERR_NOT_SUPPORTED; +} + diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/lib/base_utils.c nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/lib/base_utils.c --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/lib/base_utils.c 2023-10-25 20:21:33.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/lib/base_utils.c 2024-03-05 22:14:07.000000000 +0000 @@ -330,6 +330,44 @@ return string; } +/*! + * @brief Convert unsigned long long hex int to char* + * + * @param[in] value to be converted to string + * @param[in] targetStrLen Denoted the converted string Length + * @param[out] *string is the char array to be have the converted data + * + * @return the converted string + */ +char * +nvU64ToStr +( + NvU64 value, + char *string, + NvU32 targetStrLen +) +{ + char tempBuffer[65]; + NvU32 base = 16; + NvU32 rem = 0; + NvU32 inx = 0; + + for (inx = 0; inx < targetStrLen; inx++) + { + rem = value % base; + value = value / base; + tempBuffer[inx] = (rem > 9)? (rem - 10) + 'a' : rem + '0'; + } + + for(inx = 0; inx < targetStrLen; inx++) + { + string[inx] = tempBuffer[targetStrLen - inx - 1]; + } + + string[targetStrLen] = '\0'; + + return string; +} /** * @brief Get the string length diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/lib/protobuf/prbutil.c nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/lib/protobuf/prbutil.c --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/lib/protobuf/prbutil.c 2023-10-25 20:21:34.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/lib/protobuf/prbutil.c 2024-03-05 22:14:07.000000000 +0000 @@ -40,7 +40,7 @@ */ NV_STATUS -prbEncGpuRegs(POBJGPU pGpu, IO_APERTURE *pAperture, NvU64 offset, NvU32 numRegs, +prbEncGpuRegs(POBJGPU pGpu, IoAperture *pAperture, NvU64 offset, NvU32 numRegs, PRB_ENCODER *pPrbEnc, const PRB_FIELD_DESC *fieldDesc) { NV_STATUS status; @@ -137,7 +137,7 @@ */ NV_STATUS -prbEncGpuRegSliceTbl(POBJGPU pGpu, IO_APERTURE *pAperture, const PRB_GPU_REG_TABLE *pTbl, NvU32 numEntries, NvU32 base, +prbEncGpuRegSliceTbl(POBJGPU pGpu, IoAperture *pAperture, const PRB_GPU_REG_TABLE *pTbl, NvU32 numEntries, NvU32 base, PRB_ENCODER *pPrbEnc, const PRB_FIELD_DESC *fieldDesc) { NV_STATUS status = NV_OK; // Init keeps the Mac compiler quiet @@ -228,7 +228,7 @@ */ NV_STATUS -prbEncGpuRegSliceIndexedTbl(POBJGPU pGpu, IO_APERTURE *pAperture, const PRB_GPU_REG_INDEXED_TABLE *pTbl, NvU32 numEntries, +prbEncGpuRegSliceIndexedTbl(POBJGPU pGpu, IoAperture *pAperture, const PRB_GPU_REG_INDEXED_TABLE *pTbl, NvU32 numEntries, NvU32 base, NvU32 index, PRB_ENCODER *pPrbEnc, const PRB_FIELD_DESC *fieldDesc) { NV_STATUS status = NV_OK; // Init keeps the Mac compiler quiet @@ -316,7 +316,7 @@ */ NV_STATUS -prbEncGpuRegSliceOffset(POBJGPU pGpu, IO_APERTURE *pAperture, const NvU32 *pOffset, NvU32 numEntries, +prbEncGpuRegSliceOffset(POBJGPU pGpu, IoAperture *pAperture, const NvU32 *pOffset, NvU32 numEntries, NvU32 base, PRB_ENCODER *pPrbEnc, const PRB_FIELD_DESC *pFieldDesc) { NV_STATUS status = NV_OK; // if numEntries == 0 @@ -388,7 +388,7 @@ */ NV_STATUS -prbEncGpuRegOffset(POBJGPU pGpu, IO_APERTURE *pAperture, const NvU32 *pOffset, NvU32 numEntries, +prbEncGpuRegOffset(POBJGPU pGpu, IoAperture *pAperture, const NvU32 *pOffset, NvU32 numEntries, PRB_ENCODER *pPrbEnc, const PRB_FIELD_DESC *pFieldDesc) { return prbEncGpuRegSliceOffset(pGpu, pAperture, pOffset, numEntries, 0, pPrbEnc, pFieldDesc); @@ -406,7 +406,7 @@ */ NV_STATUS -prbEncGpuRegTbl(POBJGPU pGpu, IO_APERTURE *pAperture, const PRB_GPU_REG_TABLE *pTbl, NvU32 numEntries, +prbEncGpuRegTbl(POBJGPU pGpu, IoAperture *pAperture, const PRB_GPU_REG_TABLE *pTbl, NvU32 numEntries, PRB_ENCODER *pPrbEnc, const PRB_FIELD_DESC *fieldDesc) { return prbEncGpuRegSliceTbl(pGpu, pAperture, pTbl, numEntries, 0, pPrbEnc, fieldDesc); diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/lib/ref_count.c nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/lib/ref_count.c --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/lib/ref_count.c 2023-10-25 20:21:34.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/lib/ref_count.c 2024-03-05 22:14:08.000000000 +0000 @@ -415,7 +415,7 @@ * PDB property enabled * @param[in] bSuppressStateChange - Indicates whether the state change (and * its callback) should be suppressed - * @param[out] bNodeIsRemoved - Whether the requester is removed from + * @param[out] bNodeIsRemoved - Whether the requester is removed from * requesterTree. * * @returns NV_OK if the requester's references are successfully removed from diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/lib/zlib/inflate.c nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/lib/zlib/inflate.c --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/lib/zlib/inflate.c 2023-10-25 20:21:34.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/lib/zlib/inflate.c 2024-03-05 22:14:08.000000000 +0000 @@ -892,7 +892,7 @@ NV_STATUS utilGzInit(const NvU8 *zArray, NvU8* oBuffer, NvU32 numTotalBytes, NvU8* window, PGZ_INFLATE_STATE pGzState) { portMemSet(pGzState, 0, sizeof(GZ_INFLATE_STATE)); - portMemSet(window, 0, sizeof(GZ_SLIDE_WINDOW_SIZE)); + portMemSet(window, 0, GZ_SLIDE_WINDOW_SIZE); pGzState->inbuf = (NvU8*)zArray; pGzState->outbuf = oBuffer; diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/libraries/containers/btree/btree.c nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/libraries/containers/btree/btree.c --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/libraries/containers/btree/btree.c 2023-10-25 20:21:34.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/libraries/containers/btree/btree.c 2024-03-05 22:14:08.000000000 +0000 @@ -114,7 +114,7 @@ ) { NV_STATUS status; - + status = NV_OK; if (pNode == NULL) { @@ -157,7 +157,7 @@ } } - // red black tree property: Every red node that is not a leaf has only black children. + // red black tree property: Every red node that is not a leaf has only black children. if (pNode->isRed) { if (pNode->left && pNode->left->isRed) @@ -182,7 +182,7 @@ NODE *pNode ) { - NV_STATUS status; + NV_STATUS status; status = NV_OK; if (pNode) { @@ -206,7 +206,7 @@ ) { NV_STATUS status; - + status = NV_OK; if (pRoot) { @@ -227,7 +227,7 @@ } return (status); } - + #else // // Validate nothing. @@ -460,7 +460,7 @@ { NV_ASSERT (!(x == NULL && parentOfX == NULL)); // NULL nodes are sentinel nodes. If we delete a sentinel node (x==NULL) it - // must have a parent node (or be the root). Hence, parentOfX == NULL with + // must have a parent node (or be the root). Hence, parentOfX == NULL with // x==NULL is never possible (tree invariant) if ((parentOfX != NULL) && (x == parentOfX->left)) @@ -755,7 +755,7 @@ PNODE *pNode, PNODE root ) -{ +{ // no nodes ? NODE *current = NULL; VALIDATE_NODE(*pNode); @@ -821,7 +821,7 @@ // // Frees all the nodes and data stored in them. -// Don't use if the nodes were allocated within other structs +// Don't use if the nodes were allocated within other structs // (e.g. if the Node is embedded within the struct pointed by its "Data" field) // NV_STATUS diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/libraries/containers/eheap/eheap_old.c nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/libraries/containers/eheap/eheap_old.c --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/libraries/containers/eheap/eheap_old.c 2023-10-25 20:21:34.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/libraries/containers/eheap/eheap_old.c 2024-03-05 22:14:08.000000000 +0000 @@ -376,19 +376,19 @@ if (blockFree == NULL) goto failed; - do + do { - desiredOffset = NV_ALIGN_DOWN(blockFree->begin, pHeap->ownerGranularity) + offsetAlign; + desiredOffset = NV_ALIGN_DOWN(blockFree->begin, pHeap->ownerGranularity) + offsetAlign; while (desiredOffset + allocSize - 1 <= blockFree->end) { desiredOffsetLo = NV_ALIGN_DOWN(desiredOffset, pHeap->ownerGranularity); - desiredOffsetHi = (((desiredOffset % pHeap->ownerGranularity) == 0) ? + desiredOffsetHi = (((desiredOffset % pHeap->ownerGranularity) == 0) ? NV_ALIGN_UP((desiredOffset + 1), pHeap->ownerGranularity) : NV_ALIGN_UP(desiredOffset, pHeap->ownerGranularity)); if ((desiredOffset >= blockFree->begin) && - ((desiredOffsetLo >= blockFree->begin) && + ((desiredOffsetLo >= blockFree->begin) && (desiredOffsetHi <= blockFree->end))) { if (_eheapCheckOwnership(pHeap, pIsolationID, desiredOffset, @@ -403,8 +403,8 @@ desiredOffset += pHeap->ownerGranularity; } - - blockFree = blockFree->nextFree; + + blockFree = blockFree->nextFree; } while (blockFree != pHeap->pFreeBlockList); @@ -456,7 +456,7 @@ desiredOffset + allocSize - 1, blockFree, checker)) { break; - } + } } // we have a match, now remove it from the pool @@ -571,7 +571,7 @@ allocLo = allocAl; allocHi = allocAl + allocSize - 1; - if (_eheapCheckOwnership(pHeap, pIsolationID, allocLo, allocHi, blockFree, checker)) + if (_eheapCheckOwnership(pHeap, pIsolationID, allocLo, allocHi, blockFree, checker)) { goto alloc_done; } @@ -1075,8 +1075,8 @@ { NV_RANGE range = rangeMake(pHeap->rangeLo, pHeap->rangeHi); - if (pBytesFree) - { + if (pBytesFree) + { *pBytesFree = pHeap->free; } if (pBytesTotal) @@ -1100,14 +1100,14 @@ PEMEMBLOCK blockFirstFree, blockFree; NvU64 freeBlockSize = 0; NvU64 largestFreeOffset = 0; - NvU64 largestFreeSize = 0; + NvU64 largestFreeSize = 0; NvU32 numFreeBlocks = 0; if (pUsableBytesFree) *pUsableBytesFree = 0; blockFirstFree = pHeap->pFreeBlockList; - if (blockFirstFree) + if (blockFirstFree) { NV_ASSERT( range.lo <= range.hi ); @@ -1385,7 +1385,7 @@ { EMEMBLOCK *pTmpBlock; NvU64 checkLo = NV_ALIGN_DOWN(allocLo, pHeap->ownerGranularity); - NvU64 checkHi = (((allocHi % pHeap->ownerGranularity) == 0) ? + NvU64 checkHi = (((allocHi % pHeap->ownerGranularity) == 0) ? NV_ALIGN_UP((allocHi + 1), pHeap->ownerGranularity) : NV_ALIGN_UP(allocHi, pHeap->ownerGranularity)); NvU64 check; @@ -1407,7 +1407,7 @@ if (!pComparator(pIsolationID, pTmpBlock->pData)) { return NV_FALSE; - } + } } check = pTmpBlock->end + 1; diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/libraries/containers/list.c nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/libraries/containers/list.c --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/libraries/containers/list.c 2023-10-25 20:21:34.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/libraries/containers/list.c 2024-03-05 22:14:08.000000000 +0000 @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 2015-2015 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2015-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -122,7 +122,12 @@ return listInsertNew_IMPL(pList, listHead_IMPL(&(pList->base))); } -void *listInsertValue_IMPL(NonIntrusiveList *pList, void *pNext, void *pValue) +void *listInsertValue_IMPL +( + NonIntrusiveList *pList, + void *pNext, + const void *pValue +) { void *pCurrent; @@ -135,12 +140,12 @@ return portMemCopy(pCurrent, pList->valueSize, pValue, pList->valueSize); } -void *listAppendValue_IMPL(NonIntrusiveList *pList, void *pValue) +void *listAppendValue_IMPL(NonIntrusiveList *pList, const void *pValue) { return listInsertValue_IMPL(pList, NULL, pValue); } -void *listPrependValue_IMPL(NonIntrusiveList *pList, void *pValue) +void *listPrependValue_IMPL(NonIntrusiveList *pList, const void *pValue) { return listInsertValue_IMPL(pList, listHead_IMPL(&(pList->base)), pValue); } diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/libraries/containers/map.c nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/libraries/containers/map.c --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/libraries/containers/map.c 2023-10-25 20:21:34.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/libraries/containers/map.c 2024-03-05 22:14:08.000000000 +0000 @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 2015-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2015-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -191,7 +191,7 @@ ( NonIntrusiveMap *pMap, NvU64 key, - void *pValue + const void *pValue ) { void *pCurrent; @@ -202,8 +202,7 @@ if (NULL == pCurrent) return NULL; - return portMemCopy(pCurrent, pMap->valueSize, pValue, - pMap->valueSize); + return portMemCopy(pCurrent, pMap->valueSize, pValue, pMap->valueSize); } NvBool mapInsertExisting_IMPL diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/libraries/containers/multimap.c nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/libraries/containers/multimap.c --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/libraries/containers/multimap.c 2023-10-25 20:21:34.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/libraries/containers/multimap.c 2024-03-05 22:14:08.000000000 +0000 @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 2018-2018 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2018-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -161,9 +161,9 @@ void *multimapInsertItemValue_IMPL ( MultimapBase *pBase, - NvU64 submapKey, - NvU64 itemKey, - void *pValue + NvU64 submapKey, + NvU64 itemKey, + const void *pValue ) { void *pLeaf; @@ -299,7 +299,7 @@ void *pItem = mapFindGEQ_IMPL(&pSubmap->base, 0); if (NULL != pItem) return pItem; - + pSubmap = mapNext_IMPL(&pBase->map.base, pSubmap); } @@ -317,7 +317,7 @@ void *pItem = mapFindLEQ_IMPL(&pSubmap->base, NV_U64_MAX); if (NULL != pItem) return pItem; - + pSubmap = mapPrev_IMPL(&pBase->map.base, pSubmap); } @@ -335,7 +335,7 @@ portMemSet(&it, 0, sizeof(it)); it.pMultimap = pBase; - + NV_ASSERT_OR_RETURN(NULL != pBase, it); if (pBase->itemCount == 0 || pFirst == NULL || pLast == NULL) diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/libraries/containers/ringbuf.c nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/libraries/containers/ringbuf.c --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/libraries/containers/ringbuf.c 1970-01-01 00:00:00.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/libraries/containers/ringbuf.c 2024-03-05 22:14:08.000000000 +0000 @@ -0,0 +1,233 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2022-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ +#include "containers/ringbuf.h" + +/* + * @brief Initialize ring buffer given pre-allocated array for storage + * + * @param pBase + * Pointer to RingBufBase structure + * @param logSz + * Log base 2 of total size of storage, in # of elements + * @param arr + * Storage for ring buffer + * + * @returns NvBool + * NV_TRUE if unable to construct, NV_FALSE otherwise + */ +NvBool +ringbufConstruct_IMPL +( + RingBufBase *pBase, + NvU64 logSz, + void *arr +) +{ + pBase->head = 0; + pBase->tail = 0; + pBase->logSz = logSz; + pBase->arr = arr; + return pBase->arr == NULL; +} + +/* + * @brief Initialize dynamic ring buffer given a PORT_MEM_ALLOCATOR + * + * @param pBase + * Pointer to RingBufBase structure + * @param logSz + * Log base 2 of total size of storage, in # of elements + * @param eleSz + * Size per element + * @param pAlloc + * Pointer to PORT_MEM_ALLOCATOR + * + * @returns NvBool + * NV_TRUE if unable to construct, NV_FALSE otherwise + */ +NvBool +ringbufConstructDynamic_IMPL +( + RingBufBase *pBase, + NvU64 logSz, + NvU64 eleSz, + PORT_MEM_ALLOCATOR *pAlloc +) +{ + NV_ASSERT_OR_RETURN(logSz < 64, NV_TRUE); + return ringbufConstruct_IMPL(pBase, logSz, PORT_ALLOC(pAlloc, eleSz << logSz)); +} + +/* + * @brief Destroy a dynamic ring buffer + * + * @param pBase + * Pointer to RingBufBase structure + * @param pAlloc + * Pointer to PORT_MEM_ALLOCATOR used to construct Ring Buffer + * + * @returns void + */ +void +ringbufDestruct_IMPL +( + RingBufBase *pBase, + void *pAlloc +) +{ + if ((pAlloc != NULL) && (pBase->arr != NULL)) + { + PORT_FREE((PORT_MEM_ALLOCATOR *) pAlloc, pBase->arr); + pBase->arr = 0; + pBase->logSz = 0; + } +} + +/* + * @brief Peek up to *pMax elements from a ring buffer + * + * @param pBase + * Pointer to RingBufBase structure + * @param eleSz + * Size per element + * @param pMax + * Initially a pointer to number of elements to try to fetch. Returns number of elements actually gotten + * + * @returns void * + * Pointer to the start of the ringbuffer area containing pMax elements, NULL if *pMax == 0, initially or finally + */ +void * +ringbufPeekN_IMPL +( + RingBufBase *pBase, + NvU64 eleSz, + NvU64 *pMax +) +{ + NvU64 mask = RINGBUF_ARRAY_MASK(pBase); + NvU8 *ret = &pBase->arr[(pBase->tail & mask)*eleSz]; + NvU64 max = NV_ALIGN_UP64(pBase->tail + 1llu, RINGBUF_ARRAY_SIZE(pBase)); + max = max > pBase->head ? pBase->head : max; + max -= pBase->tail; + + NV_ASSERT_OR_RETURN(pMax != NULL, NULL); + + max = (max > *pMax) ? *pMax : max; + *pMax = max; + return max == 0 ? NULL : ret; +} + +/* + * @brief Pop up to *pMax elements from a ring buffer + * + * @param pBase + * Pointer to RingBufBase structure + * @param eleSz + * Size per element + * @param pMax + * Initially a pointer to number of elements to try to fetch. Returns number of elements actually gotten + * + * @returns void * + * Pointer to the start of the ringbuffer area containing pMax elements, NULL if *pMax == 0, initially or finally + */ +void * +ringbufPopN_IMPL +( + RingBufBase *pBase, + NvU64 eleSz, + NvU64 *pMax +) +{ + void *ret = ringbufPeekN_IMPL(pBase, eleSz, pMax); + + NV_CHECK_OR_RETURN(LEVEL_INFO, ret != NULL, NULL); + + pBase->tail += *pMax; + return ret; +} + +/* + * @brief Append num elements to the ringbuffer + * + * @param pBase + * Pointer to RingBufBase structure + * @param eleSz + * Size per element + * @param pEle + * Pointer to buffer with num elements + * @param num + * Number of elements + * @param bOverwrite + * Whether to overwrite existing elements in ring buffer + * + * @returns NvBool + * NV_TRUE if success, NV_FALSE otherwise + */ +NvBool +ringbufAppendN_IMPL +( + RingBufBase *pBase, + NvU64 eleSz, + NvU8 *pEle, + NvU64 num, + NvBool bOverwrite +) +{ + if ((RINGBUF_ARRAY_SIZE(pBase) - (bOverwrite ? 0llu : (pBase->head - pBase->tail))) < num) + { + return NV_FALSE; + } + + while (num != 0) + { + NvU64 mask = RINGBUF_ARRAY_MASK(pBase); + NvU8 *pPtr = &pBase->arr[(pBase->head & mask) * eleSz]; + NvU64 max = NV_ALIGN_UP64(pBase->head + 1llu, RINGBUF_ARRAY_SIZE(pBase)); + max -= pBase->head; + max = (max > num) ? num : max; + portMemCopy(pPtr, max * eleSz, pEle, max * eleSz); + pBase->head += max; + pEle = &pEle[max * eleSz]; + num -= max; + } + pBase->tail = (pBase->head - pBase->tail) > (1llu<logSz) ? (pBase->head - (1llu<logSz)) : pBase->tail; + return NV_TRUE; +} + +/* + * @brief Get current size of ring buffer + * + * @param pBase + * Pointer to RingBufBase structure + * + * @returns NvU64 + * Number of elements currently in ring buffer + */ +NvU64 +ringbufCurrentSize_IMPL +( + RingBufBase *pBase +) +{ + return pBase->head - pBase->tail; +} \ No newline at end of file diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/libraries/containers/vector.c nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/libraries/containers/vector.c --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/libraries/containers/vector.c 1970-01-01 00:00:00.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/libraries/containers/vector.c 2024-03-05 22:14:09.000000000 +0000 @@ -0,0 +1,450 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2015-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + #include "containers/vector.h" + +CONT_VTABLE_DEFN(Vector, vectIterRange_IMPL, NULL); + +/** + * Check if the given index is contained in vector, that is if + * ((index >= 0) && (index < pVector->size)) + */ +static NvBool _vectIndexCheck(Vector *pVector, NvU32 index); + +/** + * Reallocates container. + * + * Allocate a memory of 'newSize' bytes, then copy 'copySize' bytes from the old + * vector memory to the new one. + */ +static NvBool _vectReallocHelper(Vector *pVector, NvU32 newSize, NvU32 copySize); + +NV_STATUS vectInit_IMPL +( + Vector *pVector, + PORT_MEM_ALLOCATOR *pAllocator, + NvU32 capacity, + NvU32 valueSize +) +{ + NV_ASSERT_OR_RETURN(pVector != NULL, NV_ERR_INVALID_ARGUMENT); + NV_ASSERT_OR_RETURN(pAllocator != NULL, NV_ERR_INVALID_ARGUMENT); + NV_CHECKED_ONLY(pVector->versionNumber++); + + portMemSet(pVector, 0, sizeof(*pVector)); + CONT_VTABLE_INIT(Vector, pVector); + pVector->pAllocator = pAllocator; + pVector->valueSize = valueSize; + pVector->capacity = capacity; + pVector->size = 0; + + if (capacity > 0) + { + pVector->pHead = PORT_ALLOC(pVector->pAllocator, + capacity * pVector->valueSize); + if (NULL == pVector->pHead) + { + return NV_ERR_NO_MEMORY; + } + + portMemSet(pVector->pHead, 0, capacity * pVector->valueSize); + } + return NV_OK; +} + +void vectDestroy_IMPL(Vector *pVector) +{ + NV_ASSERT_OR_RETURN_VOID(pVector != NULL); + NV_CHECKED_ONLY(pVector->versionNumber++); + + PORT_FREE(pVector->pAllocator, pVector->pHead); + pVector->pHead = NULL; + pVector->capacity = 0; + pVector->size = 0; +} + +void *vectAt_IMPL +( + Vector *pVector, + NvU32 index +) +{ + NV_ASSERT_OR_RETURN(pVector != NULL, NULL); + if ((pVector->size == 0) || !_vectIndexCheck(pVector, index)) + { + return NULL; + } + return (void *)((NvU8 *)pVector->pHead + index * pVector->valueSize); +} + +NvU32 vectCapacity_IMPL +( + Vector *pVector +) +{ + NV_ASSERT_OR_RETURN(pVector != NULL, 0); + return pVector->capacity; +} + +NvU32 vectCount_IMPL +( + Vector *pVector +) +{ + NV_ASSERT_OR_RETURN(pVector != NULL, 0); + return pVector->size; +} + +NvBool vectIsEmpty_IMPL +( + Vector *pVector +) +{ + NV_ASSERT_OR_RETURN(pVector != NULL, 0); + + return pVector->size == 0; +} + +NV_STATUS vectTrim_IMPL +( + Vector *pVector, + NvU32 n +) +{ + NV_ASSERT_OR_RETURN(pVector != NULL, NV_ERR_INVALID_ARGUMENT); + NV_CHECKED_ONLY(pVector->versionNumber++); + + if (n > pVector->capacity) + { + return NV_OK; + } + + if (n < pVector->size) + { + n = pVector->size; + } + + if (!_vectReallocHelper(pVector, + n * pVector->valueSize, + pVector->size * pVector->valueSize)) + { + return NV_ERR_NO_MEMORY; + } + return NV_OK; +} + +NV_STATUS vectReserve_IMPL +( + Vector *pVector, + NvU32 n +) +{ + NV_ASSERT_OR_RETURN(pVector != NULL, NV_ERR_INVALID_ARGUMENT); + NV_ASSERT_OR_RETURN(n > 0, NV_ERR_INVALID_ARGUMENT); + NV_CHECKED_ONLY(pVector->versionNumber++); + + if (n > pVector->capacity) + { + if (!_vectReallocHelper(pVector, + n * pVector->valueSize, + pVector->size * pVector->valueSize)) + { + return NV_ERR_NO_MEMORY; + } + } + return NV_OK; +} + +void *vectInsert_IMPL +( + Vector *pVector, + NvU32 index, + const void *pData +) +{ + void *dst; + void *src; + NvU32 i; + NV_ASSERT_OR_RETURN(pVector != NULL, NULL); + NV_CHECKED_ONLY(pVector->versionNumber++); + if (pVector->size != index) + { + NV_ASSERT_OR_RETURN(_vectIndexCheck(pVector, index), NULL); + } + if (pVector->size + 1 > pVector->capacity) + { + // resize the container by the factor of 2, newcapacity = capacity * 2 + NvU32 newCapacity = pVector->capacity == 0 ? 10 : pVector->capacity * 2; + + if (!_vectReallocHelper(pVector, + newCapacity * pVector->valueSize, + pVector->size * pVector->valueSize)) + return NULL; + } + + for (i = pVector->size; i > index; i--) + { + dst = (void *)((NvU8 *)pVector->pHead + i * pVector->valueSize); + src = (void *)((NvU8 *)pVector->pHead + (i - 1) * pVector->valueSize); + portMemCopy(dst, pVector->valueSize, src, pVector->valueSize); + } + pVector->size++; + dst = (void *)((NvU8 *)pVector->pHead + index * pVector->valueSize); + portMemCopy(dst, pVector->valueSize, pData, pVector->valueSize); + + return dst; +} + +void vectRemove_IMPL +( + Vector *pVector, + NvU32 index +) +{ + void *src; + void *dst; + NvU32 i; + NV_ASSERT_OR_RETURN_VOID(pVector != NULL); + NV_CHECKED_ONLY(pVector->versionNumber++); + NV_ASSERT_OR_RETURN_VOID(_vectIndexCheck(pVector, index)); + + for (i = index; i < pVector->size - 1; i++) + { + dst = (void *)((NvU8 *)pVector->pHead + i * pVector->valueSize); + src = (void *)((NvU8 *)pVector->pHead + (i + 1) * pVector->valueSize); + portMemCopy(dst, pVector->valueSize, src, pVector->valueSize); + } + + pVector->size--; +} + +void *vectAppend_IMPL +( + Vector *pVector, + const void *pData +) +{ + return vectInsert_IMPL(pVector, pVector->size, pData); +} + +void *vectPrepend_IMPL +( + Vector *pVector, + const void *pData +) +{ + return vectInsert_IMPL(pVector, 0, pData); +} + +VectorIterBase vectIterRange_IMPL +( + Vector *pVector, + void *pFirst, + void *pLast +) +{ + VectorIterBase it; + NvU32 first = ~0U; + NvU32 last = ~0U; + NV_ASSERT(pVector != NULL); + + if (pFirst != NULL) + { + first = (NvU32)(((NvU8 *)pFirst - (NvU8 *)pVector->pHead) / + pVector->valueSize); + } + if (pLast != NULL) + { + last = (NvU32)(((NvU8 *)pLast - (NvU8 *)pVector->pHead) / + pVector->valueSize); + } + + NV_CHECKED_ONLY(it.versionNumber = pVector->versionNumber); + if ((pVector->size == 0) || (pFirst == NULL) || (first >= pVector->size) || + (pLast == NULL) || (last >= pVector->size)) + { + it.pVector = pVector; + it.nextIndex = -1; + it.prevIndex = -1; + it.firstIndex = -1; + it.lastIndex = -1; + it.bForward = NV_TRUE; + it.pValue = NULL; + return it; + } + it.pVector = pVector; + it.nextIndex = first; + it.prevIndex = last; + it.firstIndex = first; + it.lastIndex = last; + it.bForward = (first <= last); + it.pValue = NULL; + return it; +} + +NvBool vectIterNext_IMPL +( + VectorIterBase *pIter, + void **ppValue +) +{ + NV_ASSERT_OR_RETURN(pIter != NULL, NV_FALSE); + NV_ASSERT_OR_RETURN(ppValue != NULL, NV_FALSE); + + if (pIter->nextIndex == -1) + { + return NV_FALSE; + } + + NV_ASSERT_CHECKED(pIter->versionNumber == pIter->pVector->versionNumber); + + *ppValue = (void *)((NvU8 *)pIter->pVector->pHead + + pIter->nextIndex * pIter->pVector->valueSize); + + pIter->prevIndex = pIter->bForward ? pIter->nextIndex - 1 : + pIter->nextIndex + 1; + + if (pIter->nextIndex == pIter->lastIndex) + { + pIter->nextIndex = -1; + } + else + { + pIter->nextIndex = pIter->bForward ? pIter->nextIndex + 1 : + pIter->nextIndex - 1; + } + + return NV_TRUE; +} + +NvBool vectIterPrev_IMPL +( + VectorIterBase *pIter, + void **ppValue +) +{ + NV_ASSERT_OR_RETURN(pIter != NULL, NV_FALSE); + NV_ASSERT_OR_RETURN(ppValue != NULL, NV_FALSE); + + if (pIter->prevIndex == -1) + { + return NV_FALSE; + } + + NV_ASSERT_CHECKED(pIter->versionNumber == pIter->pVector->versionNumber); + + *ppValue = (void *)((NvU8 *)pIter->pVector->pHead + + pIter->prevIndex * pIter->pVector->valueSize); + + pIter->nextIndex = pIter->bForward ? pIter->prevIndex + 1 : + pIter->prevIndex - 1; + + if (pIter->prevIndex == pIter->firstIndex) + { + pIter->prevIndex = -1; + } + else + { + pIter->prevIndex = pIter->bForward ? pIter->prevIndex - 1 : + pIter->prevIndex + 1; + } + + return NV_TRUE; +} + +static NvBool _vectReallocHelper +( + Vector *pVector, + NvU32 newSize, + NvU32 copySize +) +{ + void *pNewArray; + void *pCopiedArray; + + NV_ASSERT_OR_RETURN(newSize >= copySize, NV_FALSE); + + pNewArray = PORT_ALLOC(pVector->pAllocator, newSize); + if (pNewArray == NULL && newSize > 0) + { + return NV_FALSE; + } + portMemSet(pNewArray, 0, newSize); + + if (copySize > 0) + { + pCopiedArray = portMemCopy(pNewArray, newSize, + pVector->pHead, copySize); + if (NULL == pCopiedArray) + { + NV_ASSERT(pCopiedArray); + PORT_FREE(pVector->pAllocator, pNewArray); + return NV_FALSE; + } + + PORT_FREE(pVector->pAllocator, pVector->pHead); + pNewArray = pCopiedArray; + } + + pVector->pHead = pNewArray; + pVector->capacity = newSize / pVector->valueSize; + pVector->size = copySize / pVector->valueSize; + + return NV_TRUE; +} + +static NvBool _vectIndexCheck +( + Vector *pVector, + NvU32 index +) +{ + void *pActualOffset, *pLastElem; + + if (pVector->size == 0) + { + return NV_FALSE; + } + + pActualOffset = (void *)((NvU8 *)pVector->pHead + + index * pVector->valueSize); + + pLastElem = (void *)((NvU8 *)pVector->pHead + + (pVector->size - 1) * pVector->valueSize); + + return ((void *)pVector->pHead <= pActualOffset && + pActualOffset <= (void *)pLastElem); +} + +NvBool vectIsValid_IMPL(void *pVect) +{ +#if NV_TYPEOF_SUPPORTED + return NV_TRUE; +#else + if (CONT_VTABLE_VALID((Vector*)pVect)) + return NV_TRUE; + + NV_ASSERT_FAILED("vtable not valid!"); + CONT_VTABLE_INIT(Vector, (Vector*)pVect); + return NV_FALSE; +#endif +} diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/libraries/crashcat/crashcat_engine.c nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/libraries/crashcat/crashcat_engine.c --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/libraries/crashcat/crashcat_engine.c 1970-01-01 00:00:00.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/libraries/crashcat/crashcat_engine.c 2024-03-05 22:14:09.000000000 +0000 @@ -0,0 +1,365 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#define NVOC_CRASHCAT_ENGINE_H_PRIVATE_ACCESS_ALLOWED +#include "crashcat/crashcat_engine.h" +#include "crashcat/crashcat_queue.h" +#include "crashcat/crashcat_wayfinder.h" +#include "utils/nvassert.h" +#include "nv-crashcat-decoder.h" + +static NV_INLINE NvU64 _crashcatEngineComputeDescriptorKey(NV_CRASHCAT_MEM_APERTURE, NvU64); +static CrashCatBufferDescriptor *_crashcatEngineCreateBufferDescriptor(CrashCatEngine *, + NV_CRASHCAT_MEM_APERTURE, + NvU64, NvU64, void *); +static NV_INLINE void _crashcatEngineDestroyBufferDescriptor(CrashCatEngine *, + CrashCatBufferDescriptor *); +static void *_crashcatEngineMapBufferDescriptor(CrashCatEngine *, CrashCatBufferDescriptor *); +static void _crashcatEngineUnmapBufferDescriptor(CrashCatEngine *, CrashCatBufferDescriptor *); + +NV_STATUS crashcatEngineLoadWayfinder_IMPL(CrashCatEngine *pCrashCatEng) +{ + NvU32 wfl0Offset = crashcatEngineGetWFL0Offset(pCrashCatEng); + NvU32 wfl0 = crashcatEnginePriRead(pCrashCatEng, wfl0Offset); + + // Has the L0 wayfinder been populated yet? + if (!crashcatWayfinderL0Valid(wfl0)) + return NV_WARN_NOTHING_TO_DO; + + NV_CHECK_OK_OR_RETURN(LEVEL_ERROR, + objCreate(&pCrashCatEng->pWayfinder, pCrashCatEng, CrashCatWayfinder, + crashcatWayfinderL0Version(wfl0), // halspec args + wfl0)); // constructor args + + return NV_OK; +} + +CrashCatReport *crashcatEngineGetNextCrashReport_IMPL(CrashCatEngine *pCrashCatEng) +{ + // Don't attempt to probe for reports if CrashCat is not configured + if (!crashcatEngineConfigured(pCrashCatEng)) + return NULL; + + // No reports if there's no wayfinder yet + if ((pCrashCatEng->pWayfinder == NULL) && + (crashcatEngineLoadWayfinder(pCrashCatEng) != NV_OK)) + return NULL; + + CrashCatQueue *pQueue = crashcatWayfinderGetReportQueue_HAL(pCrashCatEng->pWayfinder); + if (pQueue != NULL) + return crashcatQueueConsumeNextReport_HAL(pQueue); + + return NULL; +} + +NV_STATUS crashcatEngineConstruct_IMPL +( + CrashCatEngine *pCrashCatEng +) +{ + mapInitIntrusive(&pCrashCatEng->registeredCrashBuffers); + mapInitIntrusive(&pCrashCatEng->mappedCrashBuffers); + + return NV_OK; +} + +void crashcatEngineDestruct_IMPL +( + CrashCatEngine *pCrashCatEng +) +{ + crashcatEngineUnload(pCrashCatEng); + + // All buffers should be unmapped and unregistered before the destructor is called + NV_ASSERT(mapCount(&pCrashCatEng->mappedCrashBuffers) == 0); + NV_ASSERT(mapCount(&pCrashCatEng->registeredCrashBuffers) == 0); + + mapDestroy(&pCrashCatEng->mappedCrashBuffers); + mapDestroy(&pCrashCatEng->registeredCrashBuffers); +} + +void crashcatEngineUnload_IMPL +( + CrashCatEngine *pCrashCatEng +) +{ + objDelete(pCrashCatEng->pWayfinder); +} + +// Non-NVOC wrapper to handle variadic arguments +void crashcatEnginePrintf(CrashCatEngine *pCrashCatEng, NvBool bReportStart, const char *fmt, ...) +{ + va_list args; + va_start(args, fmt); + // Dispatches virtual function with va_list + crashcatEngineVprintf(pCrashCatEng, bReportStart, fmt, args); + va_end(args); +} + +static NV_INLINE NvU64 _crashcatEngineComputeDescriptorKey +( + NV_CRASHCAT_MEM_APERTURE aperture, + NvU64 offset +) +{ + // Offset should be at least 8-byte aligned so that the aperture bits can be stuffed + NV_ASSERT_CHECKED((offset & (sizeof(NvU64) - 1)) == 0); + return (offset | (NvU64)aperture); +} + +static CrashCatBufferDescriptor *_crashcatEngineCreateBufferDescriptor +( + CrashCatEngine *pCrashCatEng, + NV_CRASHCAT_MEM_APERTURE aperture, + NvU64 offset, + NvU64 size, + void *pEngPriv +) +{ + CrashCatBufferDescriptor *pBufDesc = portMemAllocNonPaged(sizeof(*pBufDesc)); + if (pBufDesc == NULL) + return NULL; + + portMemSet(pBufDesc, 0, sizeof(*pBufDesc)); + + pBufDesc->bRegistered = NV_FALSE; + pBufDesc->aperture = aperture; + pBufDesc->physOffset = offset; + pBufDesc->size = size; + pBufDesc->pEngPriv = pEngPriv; + + return pBufDesc; +} + +static NV_INLINE void _crashcatEngineDestroyBufferDescriptor +( + CrashCatEngine *pCrashCatEng, + CrashCatBufferDescriptor *pBufDesc +) +{ + portMemFree(pBufDesc); +} + +static void *_crashcatEngineMapBufferDescriptor +( + CrashCatEngine *pCrashCatEng, + CrashCatBufferDescriptor *pBufDesc +) +{ + void *ptr = NULL; + + switch (pBufDesc->aperture) + { + case NV_CRASHCAT_MEM_APERTURE_SYSGPA: + case NV_CRASHCAT_MEM_APERTURE_FBGPA: + { + ptr = crashcatEngineMapBufferDescriptor(pCrashCatEng, pBufDesc); + NV_CHECK_OR_RETURN(LEVEL_ERROR, ptr != NULL, NULL); + break; + } + case NV_CRASHCAT_MEM_APERTURE_DMEM: + case NV_CRASHCAT_MEM_APERTURE_EMEM: + { + ptr = portMemAllocNonPaged(pBufDesc->size); + NV_CHECK_OR_RETURN(LEVEL_ERROR, ptr != NULL, NULL); + break; + } + default: + NV_PRINTF(LEVEL_WARNING, + "Unknown CrashCat aperture ID 0x%02x (offset = 0x%" NvU64_fmtx + ", size = 0x%" NvU64_fmtx ")\n", + pBufDesc->aperture, pBufDesc->physOffset, pBufDesc->size); + break; + } + + return ptr; +} + +static void _crashcatEngineUnmapBufferDescriptor +( + CrashCatEngine *pCrashCatEng, + CrashCatBufferDescriptor *pBufDesc +) +{ + switch (pBufDesc->aperture) + { + case NV_CRASHCAT_MEM_APERTURE_SYSGPA: + case NV_CRASHCAT_MEM_APERTURE_FBGPA: + crashcatEngineUnmapBufferDescriptor(pCrashCatEng, pBufDesc); + break; + case NV_CRASHCAT_MEM_APERTURE_DMEM: + case NV_CRASHCAT_MEM_APERTURE_EMEM: + portMemFree(pBufDesc->pMapping); + break; + default: + NV_PRINTF(LEVEL_WARNING, + "Unknown CrashCat aperture ID 0x%02x (offset = 0x%" NvU64_fmtx + ", size = 0x%" NvU64_fmtx ")\n", + pBufDesc->aperture, pBufDesc->physOffset, pBufDesc->size); + break; + } +} + +NV_STATUS crashcatEngineRegisterCrashBuffer_IMPL +( + CrashCatEngine *pCrashCatEng, + NV_CRASHCAT_MEM_APERTURE aperture, + NvU64 offset, + NvU64 size, + void *pEngPriv +) +{ + NV_CHECK_OR_RETURN(LEVEL_INFO, (aperture == NV_CRASHCAT_MEM_APERTURE_SYSGPA) || + (aperture == NV_CRASHCAT_MEM_APERTURE_FBGPA), + NV_ERR_INVALID_ARGUMENT); + NV_CHECK_OR_RETURN(LEVEL_INFO, size > 0, NV_ERR_INVALID_ARGUMENT); + NV_CHECK_OR_RETURN(LEVEL_INFO, pEngPriv != NULL, NV_ERR_INVALID_ARGUMENT); + + // Create a crashcat buffer descriptor and register in the registeredCrashBuffers + CrashCatBufferDescriptor *pBufDesc = _crashcatEngineCreateBufferDescriptor(pCrashCatEng, + aperture, + offset, size, + pEngPriv); + if (pBufDesc == NULL) + return NV_ERR_NO_MEMORY; + + pBufDesc->bRegistered = NV_TRUE; + + NvU64 key = _crashcatEngineComputeDescriptorKey(aperture, offset); + if (!mapInsertExisting(&pCrashCatEng->registeredCrashBuffers, key, pBufDesc)) + { + _crashcatEngineDestroyBufferDescriptor(pCrashCatEng, pBufDesc); + return NV_ERR_INSERT_DUPLICATE_NAME; + } + + return NV_OK; +} + +void crashcatEngineUnregisterCrashBuffer_IMPL +( + CrashCatEngine *pCrashCatEng, + NV_CRASHCAT_MEM_APERTURE aperture, + NvU64 offset, + NvU64 size +) +{ + NvU64 key = _crashcatEngineComputeDescriptorKey(aperture, offset); + CrashCatBufferDescriptor *pBufDesc = mapFind(&pCrashCatEng->registeredCrashBuffers, key); + if (pBufDesc == NULL) + return; + + NV_ASSERT_CHECKED(pBufDesc->size == size); + + // + // CrashCat should be unloaded from the engine before unregistering the crash buffer. + // Unload will unmap all buffers. + // + NV_ASSERT_CHECKED(pBufDesc->pMapping == NULL); + + mapRemove(&pCrashCatEng->registeredCrashBuffers, pBufDesc); + _crashcatEngineDestroyBufferDescriptor(pCrashCatEng, pBufDesc); +} + +void *crashcatEngineMapCrashBuffer_IMPL +( + CrashCatEngine *pCrashCatEng, + NV_CRASHCAT_MEM_APERTURE aperture, + NvU64 offset, + NvU64 size +) +{ + NvU64 key = _crashcatEngineComputeDescriptorKey(aperture, offset); + CrashCatBufferDescriptor *pBufDesc = mapFind(&pCrashCatEng->registeredCrashBuffers, key); + + // Sysmem buffers always need to be pre-registered + if ((aperture != NV_CRASHCAT_MEM_APERTURE_SYSGPA) && (pBufDesc == NULL)) + pBufDesc = _crashcatEngineCreateBufferDescriptor(pCrashCatEng, aperture, + offset, size, NULL); + + NV_CHECK_OR_RETURN(LEVEL_ERROR, pBufDesc != NULL, NULL); + NV_ASSERT_CHECKED(pBufDesc->size == size); + + pBufDesc->pMapping = _crashcatEngineMapBufferDescriptor(pCrashCatEng, pBufDesc); + + if ((pBufDesc->pMapping == NULL) || + !mapInsertExisting(&pCrashCatEng->mappedCrashBuffers, (NvU64)pBufDesc->pMapping, pBufDesc)) + { + if (pBufDesc->pMapping != NULL) + { + _crashcatEngineUnmapBufferDescriptor(pCrashCatEng, pBufDesc); + pBufDesc->pMapping = NULL; + } + + // + // If this wasn't a registered buffer descriptor, it was created above, so destroy it + // before returning. + // + if (!pBufDesc->bRegistered) + _crashcatEngineDestroyBufferDescriptor(pCrashCatEng, pBufDesc); + + return NULL; + } + + return pBufDesc->pMapping; +} + +void crashcatEngineUnmapCrashBuffer_IMPL +( + CrashCatEngine *pCrashCatEng, + void *ptr +) +{ + CrashCatBufferDescriptor *pBufDesc = mapFind(&pCrashCatEng->mappedCrashBuffers, (NvU64)ptr); + if (pBufDesc == NULL) + return; + + NV_ASSERT_CHECKED(ptr == pBufDesc->pMapping); + + mapRemove(&pCrashCatEng->mappedCrashBuffers, pBufDesc); + _crashcatEngineUnmapBufferDescriptor(pCrashCatEng, pBufDesc); + pBufDesc->pMapping = NULL; + + // If this was not a registered buffer, destroy the buffered descriptor now + if (!pBufDesc->bRegistered) + _crashcatEngineDestroyBufferDescriptor(pCrashCatEng, pBufDesc); +} + +void crashcatEngineSyncCrashBuffer_IMPL +( + CrashCatEngine *pCrashCatEng, + void *ptr, + NvU32 offset, + NvU32 size +) +{ + CrashCatBufferDescriptor *pBufDesc = mapFind(&pCrashCatEng->mappedCrashBuffers, (NvU64)ptr); + + NV_ASSERT_OR_RETURN_VOID(pBufDesc != NULL); + + // Direct-map buffers don't require any sync + if ((pBufDesc->aperture == NV_CRASHCAT_MEM_APERTURE_SYSGPA) || + (pBufDesc->aperture == NV_CRASHCAT_MEM_APERTURE_FBGPA)) + return; + + crashcatEngineSyncBufferDescriptor(pCrashCatEng, pBufDesc, offset, size); +} diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/libraries/crashcat/crashcat_queue.c nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/libraries/crashcat/crashcat_queue.c --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/libraries/crashcat/crashcat_queue.c 1970-01-01 00:00:00.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/libraries/crashcat/crashcat_queue.c 2024-03-05 22:14:09.000000000 +0000 @@ -0,0 +1,42 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#define NVOC_CRASHCAT_QUEUE_H_PRIVATE_ACCESS_ALLOWED +#include "crashcat/crashcat_queue.h" +#include "crashcat/crashcat_engine.h" + +NV_STATUS crashcatQueueConstruct_IMPL(CrashCatQueue *pQueue, CrashCatQueueConfig *pConfig) +{ + pQueue->pEngine = CRASHCAT_GET_ENGINE(pQueue); + pQueue->config = *pConfig; + pQueue->pMapping = crashcatEngineMapCrashBuffer(pQueue->pEngine, pQueue->config.aperture, + pQueue->config.offset, pQueue->config.size); + NV_CHECK_OR_RETURN(LEVEL_WARNING, pQueue->pMapping != NULL, NV_ERR_INVALID_OBJECT_BUFFER); + + return NV_OK; +} + +void crashcatQueueDestruct_IMPL(CrashCatQueue *pQueue) +{ + crashcatEngineUnmapCrashBuffer(pQueue->pEngine, pQueue->pMapping); +} \ No newline at end of file diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/libraries/crashcat/crashcat_report.c nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/libraries/crashcat/crashcat_report.c --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/libraries/crashcat/crashcat_report.c 1970-01-01 00:00:00.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/libraries/crashcat/crashcat_report.c 2024-03-05 22:14:09.000000000 +0000 @@ -0,0 +1,164 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#define NVOC_CRASHCAT_REPORT_H_PRIVATE_ACCESS_ALLOWED +#include "crashcat/crashcat_report.h" +#include "crashcat/crashcat_engine.h" +#include "utils/nvassert.h" + +NV_STATUS crashcatReportConstruct_IMPL +( + CrashCatReport *pReport, + void **ppReportBytes, + NvLength numBytes +) +{ + // Cache the CrashCatEngine pointer for quick access during logging + pReport->pEngine = CRASHCAT_GET_ENGINE(pReport); + + // Extract the report bytes into our structured report record + void *pBufferStart = *ppReportBytes; + *ppReportBytes = crashcatReportExtract_HAL(pReport, pBufferStart, numBytes); + if (pBufferStart == *ppReportBytes) + { + NV_PRINTF(LEVEL_ERROR, "no report data extracted from %" NvUPtr_fmtu " bytes\n", numBytes); + return NV_ERR_INVALID_DATA; + } + + return NV_OK; +} + +void crashcatReportLog_IMPL(CrashCatReport *pReport) +{ + NV_CRASHCAT_PACKET_TYPE packetType; + + NV_ASSERT_OR_RETURN_VOID((pReport->validTags & NVBIT(NV_CRASHCAT_PACKET_TYPE_REPORT)) != 0); + + // TODO: acquire mutex to prevent multi-line reports interleaving + + crashcatReportLogSource_HAL(pReport); + crashcatReportLogReporter_HAL(pReport); + + // Log additional data associated with the report + FOR_EACH_INDEX_IN_MASK(32, packetType, + pReport->validTags & ~NVBIT(NV_CRASHCAT_PACKET_TYPE_REPORT)) + { + switch (packetType) + { + case NV_CRASHCAT_PACKET_TYPE_RISCV64_CSR_STATE: + crashcatReportLogRiscv64CsrState_HAL(pReport); + break; + case NV_CRASHCAT_PACKET_TYPE_RISCV64_GPR_STATE: + crashcatReportLogRiscv64GprState_HAL(pReport); + break; + case NV_CRASHCAT_PACKET_TYPE_RISCV64_TRACE: + crashcatReportLogRiscv64Traces_HAL(pReport); + break; + case NV_CRASHCAT_PACKET_TYPE_IO32_STATE: + crashcatReportLogIo32State_HAL(pReport); + break; + default: + NV_PRINTF(LEVEL_WARNING, "unrecognized packet type 0x%02x\n", packetType); + break; + } + } + FOR_EACH_INDEX_IN_MASK_END; + + crashcatEnginePrintf(pReport->pEngine, NV_FALSE, + CRASHCAT_LOG_PREFIX "------------[ end crash report ]------------"); +} + +// xcause CSR format and codes are a backward-compatible part of the RISC-V standard +#define RISCV_CSR_XCAUSE_EXCODE 4:0 +#define RISCV_CSR_XCAUSE_EXCODE_IAMA 0x00000000 +#define RISCV_CSR_XCAUSE_EXCODE_IACC_FAULT 0x00000001 +#define RISCV_CSR_XCAUSE_EXCODE_ILL 0x00000002 +#define RISCV_CSR_XCAUSE_EXCODE_BKPT 0x00000003 +#define RISCV_CSR_XCAUSE_EXCODE_LAMA 0x00000004 +#define RISCV_CSR_XCAUSE_EXCODE_LACC_FAULT 0x00000005 +#define RISCV_CSR_XCAUSE_EXCODE_SAMA 0x00000006 +#define RISCV_CSR_XCAUSE_EXCODE_SACC_FAULT 0x00000007 +#define RISCV_CSR_XCAUSE_EXCODE_UCALL 0x00000008 +#define RISCV_CSR_XCAUSE_EXCODE_SCALL 0x00000009 +#define RISCV_CSR_XCAUSE_EXCODE_MCALL 0x0000000b +#define RISCV_CSR_XCAUSE_EXCODE_IPAGE_FAULT 0x0000000c +#define RISCV_CSR_XCAUSE_EXCODE_LPAGE_FAULT 0x0000000d +#define RISCV_CSR_XCAUSE_EXCODE_SPAGE_FAULT 0x0000000f +#define RISCV_CSR_XCAUSE_EXCODE_U_SWINT 0x00000000 +#define RISCV_CSR_XCAUSE_EXCODE_S_SWINT 0x00000001 +#define RISCV_CSR_XCAUSE_EXCODE_M_SWINT 0x00000003 +#define RISCV_CSR_XCAUSE_EXCODE_U_TINT 0x00000004 +#define RISCV_CSR_XCAUSE_EXCODE_S_TINT 0x00000005 +#define RISCV_CSR_XCAUSE_EXCODE_M_TINT 0x00000007 +#define RISCV_CSR_XCAUSE_EXCODE_U_EINT 0x00000008 +#define RISCV_CSR_XCAUSE_EXCODE_S_EINT 0x00000009 +#define RISCV_CSR_XCAUSE_EXCODE_M_EINT 0x0000000b +#define RISCV_CSR_XCAUSE_INT 63:63 + +#define RISCV_CSR_XCAUSE_EXCODE_CASE(code, str) \ + case RISCV_CSR_XCAUSE_EXCODE_ ## code: return MAKE_NV_PRINTF_STR(str) + +const char *crashcatReportRiscvCauseToString(NvU64 xcause) +{ + NvBool bIntr = (NvBool)REF_VAL64(RISCV_CSR_XCAUSE_INT, xcause); + NvU8 excode = (NvU8)REF_VAL64(RISCV_CSR_XCAUSE_EXCODE, xcause); + + if (bIntr) + { + switch (excode) + { + RISCV_CSR_XCAUSE_EXCODE_CASE(U_SWINT, "user software interrupt"); + RISCV_CSR_XCAUSE_EXCODE_CASE(S_SWINT, "supervisor software interrupt"); + RISCV_CSR_XCAUSE_EXCODE_CASE(M_SWINT, "machine software interrupt"); + RISCV_CSR_XCAUSE_EXCODE_CASE(U_TINT, "user timer interrupt"); + RISCV_CSR_XCAUSE_EXCODE_CASE(S_TINT, "supervisor timer interrupt"); + RISCV_CSR_XCAUSE_EXCODE_CASE(M_TINT, "machine timer interrupt"); + RISCV_CSR_XCAUSE_EXCODE_CASE(U_EINT, "user external interrupt"); + RISCV_CSR_XCAUSE_EXCODE_CASE(S_EINT, "supervisor external interrupt"); + RISCV_CSR_XCAUSE_EXCODE_CASE(M_EINT, "machine external interrupt"); + default: return MAKE_NV_PRINTF_STR("unknown interrupt"); + } + } + else + { + switch (excode) + { + RISCV_CSR_XCAUSE_EXCODE_CASE(IAMA, "instruction address misaligned"); + RISCV_CSR_XCAUSE_EXCODE_CASE(IACC_FAULT, "instruction access fault"); + RISCV_CSR_XCAUSE_EXCODE_CASE(ILL, "illegal instruction"); + RISCV_CSR_XCAUSE_EXCODE_CASE(BKPT, "breakpoint"); + RISCV_CSR_XCAUSE_EXCODE_CASE(LAMA, "load address misaligned"); + RISCV_CSR_XCAUSE_EXCODE_CASE(LACC_FAULT, "load access fault"); + RISCV_CSR_XCAUSE_EXCODE_CASE(SAMA, "store address misaligned"); + RISCV_CSR_XCAUSE_EXCODE_CASE(SACC_FAULT, "store access fault"); + RISCV_CSR_XCAUSE_EXCODE_CASE(UCALL, "environment call from U-mode"); + RISCV_CSR_XCAUSE_EXCODE_CASE(SCALL, "environment call from S-mode"); + RISCV_CSR_XCAUSE_EXCODE_CASE(MCALL, "environment call from M-mode"); + RISCV_CSR_XCAUSE_EXCODE_CASE(IPAGE_FAULT, "instruction access page fault"); + RISCV_CSR_XCAUSE_EXCODE_CASE(LPAGE_FAULT, "load access page fault"); + RISCV_CSR_XCAUSE_EXCODE_CASE(SPAGE_FAULT, "store access page fault"); + default: return MAKE_NV_PRINTF_STR("unknown exception"); + } + } +} +#undef RISCV_CSR_MCAUSE_EXCODE_CASE diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/libraries/crashcat/crashcat_wayfinder.c nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/libraries/crashcat/crashcat_wayfinder.c --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/libraries/crashcat/crashcat_wayfinder.c 1970-01-01 00:00:00.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/libraries/crashcat/crashcat_wayfinder.c 2024-03-05 22:14:09.000000000 +0000 @@ -0,0 +1,39 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#define NVOC_CRASHCAT_WAYFINDER_H_PRIVATE_ACCESS_ALLOWED +#include "crashcat/crashcat_wayfinder.h" +#include "crashcat/crashcat_queue.h" +#include "crashcat/crashcat_report.h" + +NV_STATUS crashcatWayfinderConstruct_IMPL(CrashCatWayfinder *pWayfinder, NvU32 wfl0) +{ + crashcatWayfinderSetWFL0_HAL(pWayfinder, wfl0); + + return NV_OK; +} + +void crashcatWayfinderDestruct_IMPL(CrashCatWayfinder *pWayfinder) +{ + objDelete(pWayfinder->pQueue); +} diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/libraries/crashcat/v1/crashcat_queue_v1.c nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/libraries/crashcat/v1/crashcat_queue_v1.c --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/libraries/crashcat/v1/crashcat_queue_v1.c 1970-01-01 00:00:00.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/libraries/crashcat/v1/crashcat_queue_v1.c 2024-03-05 22:14:09.000000000 +0000 @@ -0,0 +1,146 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#define NVOC_CRASHCAT_QUEUE_H_PRIVATE_ACCESS_ALLOWED +#include "crashcat/crashcat_queue.h" +#include "crashcat/crashcat_engine.h" +#include "crashcat/crashcat_report.h" +#include "utils/nvassert.h" +#include "nv-crashcat-decoder.h" + +static NV_STATUS _getCrashCatReportHalspecArgs +( + void *pBuf, + NvU8 *pFormatVersion, + NvU64 *pImplementerSig +) +{ + NvCrashCatPacketHeader_V1 header = *(NvCrashCatPacketHeader_V1 *)pBuf; + + // Verify the report data looks sane + NV_CHECK_OR_RETURN(LEVEL_ERROR, crashcatPacketHeaderValid(header), NV_ERR_INVALID_DATA); + + *pFormatVersion = crashcatPacketHeaderFormatVersion(header); + switch (*pFormatVersion) + { + default: + // Fall through for backward compatibility if version is not recognized + case NV_CRASHCAT_PACKET_FORMAT_VERSION_1: + { + NvCrashCatReport_V1 *pReport = (NvCrashCatReport_V1 *)pBuf; + *pImplementerSig = pReport->implementerSignature; + break; + } + } + + return NV_OK; +} + +CrashCatReport *crashcatQueueConsumeNextReport_V1(CrashCatQueue *pQueue) +{ + const NvU32 size = pQueue->config.size; + const NvU32 put = crashcatEnginePriRead(pQueue->pEngine, pQueue->config.putRegOffset); + NvU32 get = crashcatEnginePriRead(pQueue->pEngine, pQueue->config.getRegOffset); + + NV_CHECK_OR_RETURN(LEVEL_ERROR, get < size, NULL); + NV_CHECK_OR_RETURN(LEVEL_ERROR, put < size, NULL); + NV_CHECK_OR_RETURN(LEVEL_SILENT, put != get, NULL); // Nothing to read + + NvU32 readSize; + void *pBuf; + NvBool bAllocated = NV_FALSE; + + if (put > get) + { + // We can read directly from the mapping + readSize = put - get; + crashcatEngineSyncCrashBuffer(pQueue->pEngine, pQueue->pMapping, get, readSize); + pBuf = (void *)((NvUPtr)pQueue->pMapping + get); + } + else if (put == 0) + { + // Buffer just wrapped, but we can still read directly from the mapping + readSize = size - get; + crashcatEngineSyncCrashBuffer(pQueue->pEngine, pQueue->pMapping, get, readSize); + pBuf = (void *)((NvUPtr)pQueue->pMapping + get); + } + else + { + // Need to handle wraparound, allocate a temporary buffer to simplify decoding + NvU32 preWrapSize = size - get; + NvU32 postWrapSize = put; + readSize = preWrapSize + postWrapSize; + pBuf = portMemAllocNonPaged(readSize); + NV_CHECK_OR_RETURN(LEVEL_ERROR, pBuf != NULL, NULL); + bAllocated = NV_TRUE; + + crashcatEngineSyncCrashBuffer(pQueue->pEngine, pQueue->pMapping, get, preWrapSize); + portMemCopy(pBuf, preWrapSize, + (void *)((NvUPtr)pQueue->pMapping + get), preWrapSize); + + crashcatEngineSyncCrashBuffer(pQueue->pEngine, pQueue->pMapping, 0, postWrapSize); + portMemCopy((void *)((NvUPtr)pBuf + preWrapSize), postWrapSize, + pQueue->pMapping, postWrapSize); + } + + // + // To create the CrashCatReport object, we pass the implementer signature as a halspec arg. + // The implementer signature location is technically report-version-specific, so we need a + // little adapter logic to get the right one before the report is created. + // + CrashCatReport *pReport = NULL; + void *pReadBuf = pBuf; + NV_STATUS status = NV_ERR_INVALID_DATA; + NvU8 reportFormatVersion; + NvU64 reportImplementer; + + NV_CHECK_OK_OR_GOTO(status, LEVEL_ERROR, + _getCrashCatReportHalspecArgs(pBuf, &reportFormatVersion, &reportImplementer), + updateGetPointer); + + NV_CHECK_OK(status, LEVEL_ERROR, + objCreate(&pReport, pQueue, CrashCatReport, + reportFormatVersion, reportImplementer, + &pReadBuf, readSize)); + +updateGetPointer: + // + // Update the get pointer based on how many bytes were read, or skip it all if there was an + // extraction failure, so that we don't flood the logs with repeated failed extraction attempts. + // TODO: log raw data somewhere so the failure can be analyzed. + // + { + NvU64 diff = (NvU64)pReadBuf - (NvU64)pBuf; + if ((status != NV_OK) || (diff == 0)) + diff = readSize; + + NV_ASSERT_CHECKED(NvU64_HI32(diff) == 0); + get = (get + NvU64_LO32(diff)) % size; + crashcatEnginePriWrite(pQueue->pEngine, pQueue->config.getRegOffset, get); + } + + if (bAllocated) + portMemFree(pBuf); + + return pReport; +} diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/libraries/crashcat/v1/crashcat_report_v1.c nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/libraries/crashcat/v1/crashcat_report_v1.c --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/libraries/crashcat/v1/crashcat_report_v1.c 1970-01-01 00:00:00.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/libraries/crashcat/v1/crashcat_report_v1.c 2024-03-05 22:14:09.000000000 +0000 @@ -0,0 +1,547 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#define NVOC_CRASHCAT_REPORT_H_PRIVATE_ACCESS_ALLOWED +#include "crashcat/crashcat_report.h" +#include "crashcat/crashcat_engine.h" +#include "utils/nvassert.h" +#include "nv-crashcat-decoder.h" + +static NV_INLINE NvUPtr ptrDiff(void *pStart, void *pEnd) +{ + return (NvUPtr)pEnd - (NvUPtr)pStart; +} + +static NV_INLINE void *advancePtr(void *pStart, void *pEnd, NvUPtr *pBytesRemaining) +{ + *pBytesRemaining -= ptrDiff(pStart, pEnd); + return pEnd; +} + +static NV_INLINE NvCrashCatPacketHeader_V1 crashcatReadPacketHeader(void *pHdr) +{ + return *(NvCrashCatPacketHeader_V1 *)pHdr; +} + +void crashcatReportDestruct_V1(CrashCatReport *pReport) +{ + portMemFree(pReport->v1.pRiscv64StackTrace); + portMemFree(pReport->v1.pRiscv64PcTrace); + portMemFree(pReport->v1.pIo32State); +} + +void *crashcatReportExtract_V1 +( + CrashCatReport *pReport, + void *pReportBytes, + NvLength bytesRemaining +) +{ + // Check for the base report first + void *pStart = pReportBytes; + void *pEnd = crashcatReportExtractReport_HAL(pReport, pStart, bytesRemaining); + + // If nothing was extracted, there's nothing more to do + if (pEnd == pStart) + return pStart; + + NV_ASSERT_OR_RETURN(pStart < pEnd, pStart); + + // + // Pull out additional report data until we've exhausted the buffer or the start of the next + // report is found. + // + for (pStart = advancePtr(pStart, pEnd, &bytesRemaining); + bytesRemaining > 0; + pStart = advancePtr(pStart, pEnd, &bytesRemaining)) + { + NvCrashCatPacketHeader_V1 hdr = crashcatReadPacketHeader(pStart); + + // Not a valid header, nothing else to do here + if (!crashcatPacketHeaderValid(hdr)) + { + NV_PRINTF(LEVEL_WARNING, + "Invalid packet header (0x%" NvU64_fmtx ") found, skipping %" NvUPtr_fmtu + " bytes remaining\n", hdr, bytesRemaining); + pEnd = (void *)((NvUPtr)pStart + bytesRemaining); + continue; + } + + NV_CRASHCAT_PACKET_TYPE packetType = crashcatPacketHeaderV1Type(hdr); + + // This is the next report (which may have a different format version) + if (packetType == NV_CRASHCAT_PACKET_TYPE_REPORT) + break; + + switch (packetType) + { + case NV_CRASHCAT_PACKET_TYPE_RISCV64_CSR_STATE: + pEnd = crashcatReportExtractRiscv64CsrState_HAL(pReport, pStart, bytesRemaining); + break; + case NV_CRASHCAT_PACKET_TYPE_RISCV64_GPR_STATE: + pEnd = crashcatReportExtractRiscv64GprState_HAL(pReport, pStart, bytesRemaining); + break; + case NV_CRASHCAT_PACKET_TYPE_RISCV64_TRACE: + pEnd = crashcatReportExtractRiscv64Trace_HAL(pReport, pStart, bytesRemaining); + break; + case NV_CRASHCAT_PACKET_TYPE_IO32_STATE: + pEnd = crashcatReportExtractIo32State_HAL(pReport, pStart, bytesRemaining); + break; + default: + NV_PRINTF(LEVEL_WARNING, "Unsupported V1 packet type 0x%02x\n", packetType); + break; + } + + // Did packet extraction fail? + if (pEnd == pStart) + { + NvLength dataSize = crashcatPacketHeaderPayloadSize(hdr) + + sizeof(NvCrashCatPacketHeader_V1); + NV_PRINTF(LEVEL_WARNING, + "Unable to extract packet type 0x%02x (%" NvUPtr_fmtu " bytes), skipping\n", + packetType, dataSize); + pEnd = (void *)((NvUPtr)pStart + dataSize); + continue; + } + } + + return pStart; +} + +void *crashcatReportExtractReport_V1 +( + CrashCatReport *pReport, + void *pReportBytes, + NvLength bytesRemaining +) +{ + if (bytesRemaining < sizeof(NvCrashCatReport_V1)) + { + NV_PRINTF(LEVEL_WARNING, + "Not enough data (%" NvUPtr_fmtu " bytes) to decode NvCrashCatReport_V1\n", + bytesRemaining); + return pReportBytes; + } + + NvCrashCatPacketHeader_V1 hdr = crashcatReadPacketHeader(pReportBytes); + const NvLength expPayloadSize = sizeof(pReport->v1.report) + - sizeof(pReport->v1.report.header); + if (!crashcatPacketHeaderValid(hdr) || + (crashcatPacketHeaderFormatVersion(hdr) != NV_CRASHCAT_PACKET_FORMAT_VERSION_1) || + (crashcatPacketHeaderPayloadSize(hdr) != expPayloadSize)) + { + NV_PRINTF(LEVEL_WARNING, "Invalid V1 report header 0x%" NvU64_fmtx "\n", hdr); + return pReportBytes; + } + + pReport->v1.report = *(NvCrashCatReport_V1 *)pReportBytes; + pReport->validTags |= NVBIT(NV_CRASHCAT_PACKET_TYPE_REPORT); + + return (void *)((NvUPtr)pReportBytes + sizeof(NvCrashCatReport_V1)); +} + +void *crashcatReportExtractRiscv64CsrState_V1 +( + CrashCatReport *pReport, + void *pReportBytes, + NvLength bytesRemaining +) +{ + if (bytesRemaining < sizeof(NvCrashCatRiscv64CsrState_V1)) + { + NV_PRINTF(LEVEL_WARNING, + "Not enough data (%" NvUPtr_fmtu " bytes) to decode NvCrashCatRiscv64CsrState_V1\n", + bytesRemaining); + return pReportBytes; + } + + NvCrashCatPacketHeader_V1 hdr = crashcatReadPacketHeader(pReportBytes); + const NvLength expPayloadSize = sizeof(pReport->v1.riscv64CsrState) + - sizeof(pReport->v1.riscv64CsrState.header); + if (!crashcatPacketHeaderValid(hdr) || + (crashcatPacketHeaderFormatVersion(hdr) != NV_CRASHCAT_PACKET_FORMAT_VERSION_1) || + (crashcatPacketHeaderPayloadSize(hdr) != expPayloadSize)) + { + NV_PRINTF(LEVEL_WARNING, "Invalid V1 RISCV CSR state header 0x%" NvU64_fmtx "\n", hdr); + return pReportBytes; + } + + pReport->v1.riscv64CsrState = *(NvCrashCatRiscv64CsrState_V1 *)pReportBytes; + pReport->validTags |= NVBIT(NV_CRASHCAT_PACKET_TYPE_RISCV64_CSR_STATE); + + return (void *)((NvUPtr)pReportBytes + sizeof(NvCrashCatRiscv64CsrState_V1)); +} + +void *crashcatReportExtractRiscv64GprState_V1 +( + CrashCatReport *pReport, + void *pReportBytes, + NvLength bytesRemaining +) +{ + if (bytesRemaining < sizeof(NvCrashCatRiscv64GprState_V1)) + { + NV_PRINTF(LEVEL_WARNING, + "Not enough data (%" NvUPtr_fmtu " bytes) to decode NvCrashCatRiscv64GprState_V1\n", + bytesRemaining); + return pReportBytes; + } + + NvCrashCatPacketHeader_V1 hdr = crashcatReadPacketHeader(pReportBytes); + const NvLength expPayloadSize = sizeof(pReport->v1.riscv64GprState) + - sizeof(pReport->v1.riscv64GprState.header); + if (!crashcatPacketHeaderValid(hdr) || + (crashcatPacketHeaderFormatVersion(hdr) != NV_CRASHCAT_PACKET_FORMAT_VERSION_1) || + (crashcatPacketHeaderPayloadSize(hdr) != expPayloadSize)) + { + NV_PRINTF(LEVEL_WARNING, "Invalid V1 RISCV GPR state header 0x%" NvU64_fmtx "\n", hdr); + return pReportBytes; + } + + pReport->v1.riscv64GprState = *(NvCrashCatRiscv64GprState_V1 *)pReportBytes; + pReport->validTags |= NVBIT(NV_CRASHCAT_PACKET_TYPE_RISCV64_GPR_STATE); + + return (void *)((NvUPtr)pReportBytes + sizeof(NvCrashCatRiscv64GprState_V1)); +} + +void *crashcatReportExtractRiscv64Trace_V1 +( + CrashCatReport *pReport, + void *pReportBytes, + NvLength bytesRemaining +) +{ + if (bytesRemaining < sizeof(NvCrashCatPacketHeader_V1)) + { + NV_PRINTF(LEVEL_WARNING, + "Not enough data (%" NvUPtr_fmtu " bytes) to decode NvCrashCatRiscv64Trace_V1\n", + bytesRemaining); + return pReportBytes; + } + + NvCrashCatPacketHeader_V1 hdr = crashcatReadPacketHeader(pReportBytes); + if (!crashcatPacketHeaderValid(hdr) || + (crashcatPacketHeaderFormatVersion(hdr) != NV_CRASHCAT_PACKET_FORMAT_VERSION_1)) + { + NV_PRINTF(LEVEL_WARNING, "Invalid V1 trace packet header 0x%" NvU64_fmtx "\n", hdr); + return pReportBytes; + } + + // Allocate the buffer for the trace + const NvU32 payloadSize = crashcatPacketHeaderPayloadSize(hdr); + const NvLength sizeBytes = sizeof(NvCrashCatRiscv64Trace_V1) + payloadSize; + NV_CHECK_OR_RETURN(LEVEL_ERROR, payloadSize > 0, pReportBytes); + + NvCrashCatRiscv64Trace_V1 *pRiscv64Trace = portMemAllocNonPaged(sizeBytes); + NV_CHECK_OR_RETURN(LEVEL_ERROR, pRiscv64Trace != NULL, pReportBytes); + + portMemCopy(pRiscv64Trace, sizeBytes, pReportBytes, sizeBytes); + + // + // We support both stack and PC traces in one report. They share a tag bit (will be set if + // either are present). + // + switch (crashcatRiscv64TraceV1Type(pRiscv64Trace)) + { + case NV_CRASHCAT_TRACE_TYPE_STACK: + if (pReport->v1.pRiscv64StackTrace != NULL) + { + NV_PRINTF(LEVEL_WARNING, + "Only one stack trace packet is supported, discarding the old one\n"); + portMemFree(pReport->v1.pRiscv64StackTrace); + } + + pReport->v1.pRiscv64StackTrace = pRiscv64Trace; + pReport->validTags |= NVBIT(NV_CRASHCAT_PACKET_TYPE_RISCV64_TRACE); + break; + case NV_CRASHCAT_TRACE_TYPE_NVRVTB: + if (pReport->v1.pRiscv64PcTrace != NULL) + { + NV_PRINTF(LEVEL_WARNING, + "Only one PC trace packet is supported, discarding the old one\n"); + portMemFree(pReport->v1.pRiscv64PcTrace); + } + + pReport->v1.pRiscv64PcTrace = pRiscv64Trace; + pReport->validTags |= NVBIT(NV_CRASHCAT_PACKET_TYPE_RISCV64_TRACE); + break; + default: + NV_PRINTF(LEVEL_WARNING, "Unknown CrashCat trace type (0x%x), discarding\n", + crashcatRiscv64TraceV1Type(pRiscv64Trace)); + portMemFree(pRiscv64Trace); + break; + } + + return (void *)((NvUPtr)pReportBytes + sizeBytes); +} + +void *crashcatReportExtractIo32State_V1 +( + CrashCatReport *pReport, + void *pReportBytes, + NvLength bytesRemaining +) +{ + if (bytesRemaining < sizeof(NvCrashCatPacketHeader_V1)) + { + NV_PRINTF(LEVEL_WARNING, + "Not enough data (%" NvUPtr_fmtu " bytes) to decode NvCrashCatIo32State_V1\n", + bytesRemaining); + return pReportBytes; + } + + // + // TODO: support multiple IO32_STATE packets. This implementation assumes there will be only + // one, and always keeps the first one. + // + if ((pReport->validTags & NVBIT(NV_CRASHCAT_PACKET_TYPE_IO32_STATE)) != 0) + { + NV_PRINTF(LEVEL_WARNING, "Report already contains valid reg32 data, skipping\n"); + return pReportBytes; + } + + NvCrashCatPacketHeader_V1 hdr = crashcatReadPacketHeader(pReportBytes); + if (!crashcatPacketHeaderValid(hdr) || + (crashcatPacketHeaderFormatVersion(hdr) != NV_CRASHCAT_PACKET_FORMAT_VERSION_1)) + { + NV_PRINTF(LEVEL_WARNING, "Invalid V1 reg32 state header 0x%" NvU64_fmtx "\n", hdr); + return pReportBytes; + } + + // Allocate the buffer for the register state. + const NvU32 payloadSize = crashcatPacketHeaderPayloadSize(hdr); + const NvLength sizeBytes = sizeof(NvCrashCatIo32State_V1) + payloadSize; + NV_CHECK_OR_RETURN(LEVEL_ERROR, payloadSize > 0, pReportBytes); + + pReport->v1.pIo32State = portMemAllocNonPaged(sizeBytes); + NV_CHECK_OR_RETURN(LEVEL_ERROR, pReport->v1.pIo32State != NULL, pReportBytes); + + portMemCopy(pReport->v1.pIo32State, sizeBytes, pReportBytes, sizeBytes); + pReport->validTags |= NVBIT(NV_CRASHCAT_PACKET_TYPE_IO32_STATE); + + return (void *)((NvUPtr)pReportBytes + sizeBytes); +} + + +void crashcatReportLogRiscv64CsrState_V1(CrashCatReport *pReport) +{ + NvCrashCatRiscv64CsrState_V1 *pCsrStateV1 = &pReport->v1.riscv64CsrState; + NV_CRASHCAT_RISCV_MODE mode = crashcatRiscv64CsrStateV1Mode(pCsrStateV1); + + // + // TODO: this equates M-mode with NVRISCV 1.x (e.g., mbadaddr vs stval). This happens to be + // correct as of this writing because there isn't an M-mode implementer on NVRISCV 2.x+, + // but we should have a way of distinguishing in the protocol. + // + CRASHCAT_REPORT_LOG_PACKET_TYPE(pReport, "RISC-V CSR State:"); + switch (mode) + { + case NV_CRASHCAT_RISCV_MODE_M: + CRASHCAT_REPORT_LOG_DATA(pReport, + "mstatus:0x%016" NvU64_fmtx " mscratch:0x%016" NvU64_fmtx " mie:0x%016" NvU64_fmtx " mip:0x%016" NvU64_fmtx, + pCsrStateV1->xstatus, pCsrStateV1->xscratch, pCsrStateV1->xie, pCsrStateV1->xip); + CRASHCAT_REPORT_LOG_DATA(pReport, + " mepc:0x%016" NvU64_fmtx " mbadaddr:0x%016" NvU64_fmtx " mcause:0x%016" NvU64_fmtx, + pCsrStateV1->xepc, pCsrStateV1->xtval, pCsrStateV1->xcause); + break; + case NV_CRASHCAT_RISCV_MODE_S: + CRASHCAT_REPORT_LOG_DATA(pReport, + "sstatus:0x%016" NvU64_fmtx " sscratch:0x%016" NvU64_fmtx " sie:0x%016" NvU64_fmtx " sip:0x%016" NvU64_fmtx, + pCsrStateV1->xstatus, pCsrStateV1->xscratch, pCsrStateV1->xie, pCsrStateV1->xip); + CRASHCAT_REPORT_LOG_DATA(pReport, + " sepc:0x%016" NvU64_fmtx " stval:0x%016" NvU64_fmtx " scause:0x%016" NvU64_fmtx, + pCsrStateV1->xepc, pCsrStateV1->xtval, pCsrStateV1->xcause); + break; + default: + // We don't expect CSR dumps from other modes + NV_PRINTF(LEVEL_WARNING, "Unexpected RISC-V mode (%u) CSR dump\n", mode); + CRASHCAT_REPORT_LOG_DATA(pReport, + "xstatus:0x%016" NvU64_fmtx " xscratch:0x%016" NvU64_fmtx " xie:0x%016" NvU64_fmtx " xip:0x%016" NvU64_fmtx, + pCsrStateV1->xstatus, pCsrStateV1->xscratch, pCsrStateV1->xie, pCsrStateV1->xip); + CRASHCAT_REPORT_LOG_DATA(pReport, + " xepc:0x%016" NvU64_fmtx " xtval:0x%016" NvU64_fmtx " xcause:0x%016" NvU64_fmtx, + pCsrStateV1->xepc, pCsrStateV1->xtval, pCsrStateV1->xcause); + break; + } +} + +void crashcatReportLogRiscv64GprState_V1(CrashCatReport *pReport) +{ + NvCrashCatRiscv64GprState_V1 *pGprStateV1 = &pReport->v1.riscv64GprState; + + // TODO: log the mode of the GPR state + CRASHCAT_REPORT_LOG_PACKET_TYPE(pReport, "RISC-V GPR State:"); + CRASHCAT_REPORT_LOG_DATA(pReport, + "ra:0x%016" NvU64_fmtx " sp:0x%016" NvU64_fmtx " gp:0x%016" NvU64_fmtx " tp:0x%016" NvU64_fmtx, + pGprStateV1->ra, pGprStateV1->sp, pGprStateV1->gp, pGprStateV1->tp); + CRASHCAT_REPORT_LOG_DATA(pReport, + "a0:0x%016" NvU64_fmtx " a1:0x%016" NvU64_fmtx " a2:0x%016" NvU64_fmtx " a3:0x%016" NvU64_fmtx, + pGprStateV1->a0, pGprStateV1->a1, pGprStateV1->a2, pGprStateV1->a3); + CRASHCAT_REPORT_LOG_DATA(pReport, + "a4:0x%016" NvU64_fmtx " a5:0x%016" NvU64_fmtx " a6:0x%016" NvU64_fmtx " a7:0x%016" NvU64_fmtx, + pGprStateV1->a4, pGprStateV1->a5, pGprStateV1->a6, pGprStateV1->a7); + CRASHCAT_REPORT_LOG_DATA(pReport, + "s0:0x%016" NvU64_fmtx " s1:0x%016" NvU64_fmtx " s2:0x%016" NvU64_fmtx " s3:0x%016" NvU64_fmtx, + pGprStateV1->s0, pGprStateV1->s1, pGprStateV1->s2, pGprStateV1->s3); + CRASHCAT_REPORT_LOG_DATA(pReport, + "s4:0x%016" NvU64_fmtx " s5:0x%016" NvU64_fmtx " s6:0x%016" NvU64_fmtx " s7:0x%016" NvU64_fmtx, + pGprStateV1->s4, pGprStateV1->s5, pGprStateV1->s6, pGprStateV1->s7); + CRASHCAT_REPORT_LOG_DATA(pReport, + "s8:0x%016" NvU64_fmtx " s9:0x%016" NvU64_fmtx " s10:0x%016" NvU64_fmtx " s11:0x%016" NvU64_fmtx, + pGprStateV1->s8, pGprStateV1->s9, pGprStateV1->s10, pGprStateV1->s11); + CRASHCAT_REPORT_LOG_DATA(pReport, + "t0:0x%016" NvU64_fmtx " t1:0x%016" NvU64_fmtx " t2:0x%016" NvU64_fmtx " t3:0x%016" NvU64_fmtx, + pGprStateV1->t0, pGprStateV1->t1, pGprStateV1->t2, pGprStateV1->t3); + CRASHCAT_REPORT_LOG_DATA(pReport, + "t4:0x%016" NvU64_fmtx " t5:0x%016" NvU64_fmtx " t6:0x%016" NvU64_fmtx, + pGprStateV1->t4, pGprStateV1->t5, pGprStateV1->t6); +} + +static NV_INLINE const char *crashcatRiscv64TraceTypeToString_V1(NV_CRASHCAT_TRACE_TYPE traceType) +{ + switch (traceType) + { + case NV_CRASHCAT_TRACE_TYPE_STACK: return MAKE_NV_PRINTF_STR("Stack"); + case NV_CRASHCAT_TRACE_TYPE_NVRVTB: return MAKE_NV_PRINTF_STR("PC"); + default: return MAKE_NV_PRINTF_STR("Address"); + } +} + +static void crashcatReportLogRiscv64Trace_V1 +( + CrashCatReport *pReport, + NvCrashCatRiscv64Trace_V1 *pTraceV1 +) +{ + NvU16 entries = crashcatPacketHeaderPayloadSize(pTraceV1->header) >> 3; + NV_CRASHCAT_TRACE_TYPE traceType = crashcatRiscv64TraceV1Type(pTraceV1); + + // TODO: log the mode of the trace using implementer terminology (e.g., kernel/task) + CRASHCAT_REPORT_LOG_PACKET_TYPE(pReport, "%s Trace:", + crashcatRiscv64TraceTypeToString_V1(traceType)); + + if (traceType == NV_CRASHCAT_TRACE_TYPE_NVRVTB) + { + // PC traces are too long with each entry on its own line + const NvU8 ENTRIES_PER_LINE = 5; + NvU16 idx; + for (idx = 0; idx < (entries / ENTRIES_PER_LINE) * ENTRIES_PER_LINE; + idx += ENTRIES_PER_LINE) + { + CRASHCAT_REPORT_LOG_DATA(pReport, + "0x%016" NvU64_fmtx " 0x%016" NvU64_fmtx " 0x%016" NvU64_fmtx " " + "0x%016" NvU64_fmtx " 0x%016" NvU64_fmtx, + pTraceV1->addr[idx + 0], pTraceV1->addr[idx + 1], pTraceV1->addr[idx + 2], + pTraceV1->addr[idx + 3], pTraceV1->addr[idx + 4]); + } + + switch (entries - idx) + { + case 4: + CRASHCAT_REPORT_LOG_DATA(pReport, + "0x%016" NvU64_fmtx " 0x%016" NvU64_fmtx " 0x%016" NvU64_fmtx " " + "0x%016" NvU64_fmtx, + pTraceV1->addr[idx + 0], pTraceV1->addr[idx + 1], pTraceV1->addr[idx + 2], + pTraceV1->addr[idx + 3]); + break; + case 3: + CRASHCAT_REPORT_LOG_DATA(pReport, + "0x%016" NvU64_fmtx " 0x%016" NvU64_fmtx " 0x%016" NvU64_fmtx, + pTraceV1->addr[idx + 0], pTraceV1->addr[idx + 1], pTraceV1->addr[idx + 2]); + break; + case 2: + CRASHCAT_REPORT_LOG_DATA(pReport, "0x%016" NvU64_fmtx " 0x%016" NvU64_fmtx, + pTraceV1->addr[idx + 0], pTraceV1->addr[idx + 1]); + break; + case 1: + CRASHCAT_REPORT_LOG_DATA(pReport, "0x%016" NvU64_fmtx, pTraceV1->addr[idx + 0]); + break; + default: + break; + } + } + else + { + for (NvU16 idx = 0; idx < entries; idx++) + CRASHCAT_REPORT_LOG_DATA(pReport, "0x%016" NvU64_fmtx, pTraceV1->addr[idx]); + } +} + +void crashcatReportLogRiscv64Traces_V1(CrashCatReport *pReport) +{ + if (pReport->v1.pRiscv64StackTrace != NULL) + crashcatReportLogRiscv64Trace_V1(pReport, pReport->v1.pRiscv64StackTrace); + if (pReport->v1.pRiscv64PcTrace != NULL) + crashcatReportLogRiscv64Trace_V1(pReport, pReport->v1.pRiscv64PcTrace); +} + +static NV_INLINE const char *crashcatIo32ApertureToString_V1(NV_CRASHCAT_IO_APERTURE aperture) +{ + switch (aperture) + { + case NV_CRASHCAT_IO_APERTURE_INTIO: return MAKE_NV_PRINTF_STR("Local I/O"); + case NV_CRASHCAT_IO_APERTURE_EXTIO: return MAKE_NV_PRINTF_STR("External I/O"); + default: return MAKE_NV_PRINTF_STR("Additional"); + } +} + +void crashcatReportLogIo32State_V1(CrashCatReport *pReport) +{ + NvCrashCatIo32State_V1 *pIo32StateV1 = pReport->v1.pIo32State; + NvU16 entries = crashcatPacketHeaderPayloadSize(pIo32StateV1->header) >> 3; + NV_CRASHCAT_IO_APERTURE aperture = crashcatIo32StateV1Aperture(pIo32StateV1); + CRASHCAT_REPORT_LOG_PACKET_TYPE(pReport, "%s Register State:", + crashcatIo32ApertureToString_V1(aperture)); + + // Print 4 registers on a line to save space + const NvU8 REGS_PER_LINE = 4; + NvU16 idx; + for (idx = 0; idx < (entries / REGS_PER_LINE) * REGS_PER_LINE; idx += REGS_PER_LINE) + CRASHCAT_REPORT_LOG_DATA(pReport, + "0x%08x:0x%08x 0x%08x:0x%08x 0x%08x:0x%08x 0x%08x:0x%08x", + pIo32StateV1->regs[idx + 0].offset, pIo32StateV1->regs[idx + 0].value, + pIo32StateV1->regs[idx + 1].offset, pIo32StateV1->regs[idx + 1].value, + pIo32StateV1->regs[idx + 2].offset, pIo32StateV1->regs[idx + 2].value, + pIo32StateV1->regs[idx + 3].offset, pIo32StateV1->regs[idx + 3].value); + + switch (entries - idx) + { + case 3: + CRASHCAT_REPORT_LOG_DATA(pReport, "0x%08x:0x%08x 0x%08x:0x%08x 0x%08x:0x%08x", + pIo32StateV1->regs[idx + 0].offset, pIo32StateV1->regs[idx + 0].value, + pIo32StateV1->regs[idx + 1].offset, pIo32StateV1->regs[idx + 1].value, + pIo32StateV1->regs[idx + 2].offset, pIo32StateV1->regs[idx + 2].value); + break; + case 2: + CRASHCAT_REPORT_LOG_DATA(pReport, "0x%08x:0x%08x 0x%08x:0x%08x", + pIo32StateV1->regs[idx + 0].offset, pIo32StateV1->regs[idx + 0].value, + pIo32StateV1->regs[idx + 1].offset, pIo32StateV1->regs[idx + 1].value); + break; + case 1: + CRASHCAT_REPORT_LOG_DATA(pReport, "0x%08x:0x%08x", + pIo32StateV1->regs[idx + 0].offset, pIo32StateV1->regs[idx + 0].value); + break; + default: + break; + } +} diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/libraries/crashcat/v1/crashcat_wayfinder_v1.c nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/libraries/crashcat/v1/crashcat_wayfinder_v1.c --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/libraries/crashcat/v1/crashcat_wayfinder_v1.c 1970-01-01 00:00:00.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/libraries/crashcat/v1/crashcat_wayfinder_v1.c 2024-03-05 22:14:09.000000000 +0000 @@ -0,0 +1,125 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#define NVOC_CRASHCAT_WAYFINDER_H_PRIVATE_ACCESS_ALLOWED +#include "crashcat/crashcat_wayfinder.h" +#include "crashcat/crashcat_engine.h" +#include "crashcat/crashcat_queue.h" +#include "crashcat/crashcat_report.h" +#include "utils/nvassert.h" +#include "nv-crashcat-decoder.h" + +void crashcatWayfinderSetWFL0_V1(CrashCatWayfinder *pWayfinder, NvU32 wfl0) +{ + pWayfinder->v1.wfl0 = wfl0; +} + +CrashCatQueue *crashcatWayfinderGetReportQueue_V1(CrashCatWayfinder *pWayfinder) +{ + if (pWayfinder->pQueue != NULL) + return pWayfinder->pQueue; + + // + // If we've already decoded WFL1 but don't have a queue, queue control object creation failed + // and is unlikely to succeed on subsequent attempts, and we don't want to spam the logs. + // + if (pWayfinder->v1.wfl1 != 0) + return NULL; + + CrashCatEngine *pEngine = CRASHCAT_GET_ENGINE(pWayfinder); + NV_CRASHCAT_SCRATCH_GROUP_ID wfl1Location = + crashcatWayfinderL0V1Wfl1Location(pWayfinder->v1.wfl0); + + // Read the L1 wayfinder to locate the queue + const NvU32 *pScratchOffsets = crashcatEngineGetScratchOffsets(pEngine, wfl1Location); + if (pScratchOffsets == NULL) + { + NV_PRINTF(LEVEL_ERROR, "invalid WFL1 scratch location %u\n", wfl1Location); + return NULL; + } + + // + // In NV_CRASHCAT_WAYFINDER_VERSION_1, the WFL1 contains two 32-bit values specifying the queue + // location, so we only need to read two registers. Where the scratch group contains 4 + // registers, the other two will be used for the queue control. + // + if ((pScratchOffsets[0] == 0) || (pScratchOffsets[1] == 0)) + { + NV_PRINTF(LEVEL_ERROR, "insufficiently-sized L1 wayfinder scratch location %u\n", + wfl1Location); + return NULL; + } + + // Have we already decoded WFL1? + if (pWayfinder->v1.wfl1 == 0) + { + pWayfinder->v1.wfl1 = + ((NvU64)crashcatEnginePriRead(pEngine, pScratchOffsets[1]) << 32) | + crashcatEnginePriRead(pEngine, pScratchOffsets[0]); + } + + CrashCatQueueConfig queueConfig; + + queueConfig.aperture = crashcatWayfinderL1V1QueueAperture(pWayfinder->v1.wfl1); + queueConfig.size = crashcatWayfinderL1V1QueueSize(pWayfinder->v1.wfl1); + queueConfig.offset = crashcatWayfinderL1V1QueueOffset(pWayfinder->v1.wfl1); + + if ((pScratchOffsets[2] != 0) && (pScratchOffsets[3] != 0)) + { + // + // If the scratch group has at least 4 32-bit registers, the 3rd and 4th are used for queue + // put and get, respectively. + // + queueConfig.putRegOffset = pScratchOffsets[2]; + queueConfig.getRegOffset = pScratchOffsets[3]; + } + else + { + // + // If there are only 2 scratch registers in the group, the WFL1 is erased and the registers + // are reused for queue put and get, respectively. + // + queueConfig.putRegOffset = pScratchOffsets[0]; + queueConfig.getRegOffset = pScratchOffsets[1]; + + crashcatEnginePriWrite(pEngine, queueConfig.getRegOffset, 0); + crashcatEnginePriWrite(pEngine, queueConfig.putRegOffset, 0); + + // + // Producer watches WFL0 and waits for the _WFL1_LOCATION bits to be set to _NONE + // before it will update the queue put pointer. + // + NvU32 wfl0Offset = crashcatEngineGetWFL0Offset(pEngine); + NvU32 wfl0 = FLD_SET_DRF64(_CRASHCAT, _WAYFINDER_L0_V1, _WFL1_LOCATION, _NONE, + pWayfinder->v1.wfl0); + crashcatEnginePriWrite(pEngine, wfl0Offset, wfl0); + } + + // Create the queue control object + NV_STATUS status; + NV_CHECK_OK_OR_ELSE(status, LEVEL_ERROR, + objCreate(&pWayfinder->pQueue, pWayfinder, CrashCatQueue, &queueConfig), + return NULL); + + return pWayfinder->pQueue; +} diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/libraries/crashcat/v1/impl/crashcat_report_v1_generic.c nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/libraries/crashcat/v1/impl/crashcat_report_v1_generic.c --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/libraries/crashcat/v1/impl/crashcat_report_v1_generic.c 1970-01-01 00:00:00.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/libraries/crashcat/v1/impl/crashcat_report_v1_generic.c 2024-03-05 22:14:10.000000000 +0000 @@ -0,0 +1,81 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#define NVOC_CRASHCAT_REPORT_H_PRIVATE_ACCESS_ALLOWED +#include "crashcat/crashcat_report.h" +#include "crashcat/crashcat_engine.h" +#include "nv-crashcat-decoder.h" + +static inline const char crashcatReportModeToChar_GENERIC(NV_CRASHCAT_RISCV_MODE mode) +{ + switch (mode) + { + case NV_CRASHCAT_RISCV_MODE_M: return 'M'; + case NV_CRASHCAT_RISCV_MODE_S: return 'S'; + case NV_CRASHCAT_RISCV_MODE_U: return 'U'; + default: return '?'; + } +} + +static inline const char *crashcatReportCauseTypeToString_GENERIC(NV_CRASHCAT_CAUSE_TYPE causeType) +{ + switch (causeType) + { + case NV_CRASHCAT_CAUSE_TYPE_EXCEPTION: return MAKE_NV_PRINTF_STR("exception"); + case NV_CRASHCAT_CAUSE_TYPE_PANIC: return MAKE_NV_PRINTF_STR("panic"); + case NV_CRASHCAT_CAUSE_TYPE_TIMEOUT: return MAKE_NV_PRINTF_STR("timeout"); + default: return MAKE_NV_PRINTF_STR("unknown failure"); + } +} + +void crashcatReportLogSource_V1_GENERIC(CrashCatReport *pReport) +{ + NvCrashCatReport_V1 *pReportV1 = &pReport->v1.report; + NvCrashCatNvriscvPartition partition = crashcatReportV1SourcePartition(pReportV1); + NvCrashCatNvriscvUcodeId ucodeId = crashcatReportV1SourceUcodeId(pReportV1); + NV_CRASHCAT_RISCV_MODE riscvMode = crashcatReportV1SourceMode(pReportV1); + NV_CRASHCAT_CAUSE_TYPE causeType = crashcatReportV1SourceCauseType(pReportV1); + + crashcatEnginePrintf(pReport->pEngine, NV_TRUE, + "%s in partition:%u ucode:%u [%c-mode] @ pc:0x%" NvU64_fmtx ", data:0x%" NvU64_fmtx, + crashcatReportCauseTypeToString_GENERIC(causeType), partition, ucodeId, + crashcatReportModeToChar_GENERIC(riscvMode), pReportV1->sourcePc, pReportV1->sourceData); +} + +void crashcatReportLogReporter_V1_GENERIC(CrashCatReport *pReport) +{ + NvCrashCatReport_V1 *pReportV1 = &pReport->v1.report; + NvCrashCatNvriscvPartition partition = crashcatReportV1ReporterPartition(pReportV1); + NvCrashCatNvriscvUcodeId ucodeId = crashcatReportV1ReporterUcodeId(pReportV1); + NV_CRASHCAT_RISCV_MODE riscvMode = crashcatReportV1ReporterMode(pReportV1); + + // + // Though this is technically not a separate packet, we use the CRASHCAT_REPORT_LOG_PACKET_TYPE + // macro to get the correct prefix/indentation for the reporter information. + // + CRASHCAT_REPORT_LOG_PACKET_TYPE(pReport, + "Reported by partition:%u ucode:%u [%c-mode] version:%u @ %u", + partition, ucodeId, crashcatReportModeToChar_GENERIC(riscvMode), + crashcatReportV1ReporterVersion(pReportV1), + crashcatReportV1ReporterTimestamp(pReportV1)); +} diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/libraries/crashcat/v1/impl/crashcat_report_v1_libos2.c nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/libraries/crashcat/v1/impl/crashcat_report_v1_libos2.c --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/libraries/crashcat/v1/impl/crashcat_report_v1_libos2.c 1970-01-01 00:00:00.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/libraries/crashcat/v1/impl/crashcat_report_v1_libos2.c 2024-03-05 22:14:10.000000000 +0000 @@ -0,0 +1,137 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#define NVOC_CRASHCAT_REPORT_H_PRIVATE_ACCESS_ALLOWED +#include "crashcat/crashcat_report.h" +#include "crashcat/crashcat_engine.h" +#include "libos_v2_crashcat.h" +#include "utils/nvprintf.h" +#include "nv-crashcat-decoder.h" + +static inline const char *crashcatReportModeToString_LIBOS2(NV_CRASHCAT_RISCV_MODE mode) +{ + switch (mode) + { + case NV_CRASHCAT_RISCV_MODE_M: + case NV_CRASHCAT_RISCV_MODE_S: + return MAKE_NV_PRINTF_STR("kernel"); + case NV_CRASHCAT_RISCV_MODE_U: + return MAKE_NV_PRINTF_STR("task"); + default: + return MAKE_NV_PRINTF_STR("unspecified"); + } +} + +static inline const char *crashcatReportPanicReasonToString_LIBOS2(LibosPanicReason reason) +{ +#define LIBOS_PANIC_REASON_CASE(reason, str) \ + case LibosPanicReason ## reason: return MAKE_NV_PRINTF_STR(str) + switch (reason) + { + LIBOS_PANIC_REASON_CASE(UnrecoverableTaskCrash, "unrecoverable task crash"); + LIBOS_PANIC_REASON_CASE(UnhandledState, "unhandled state"); + LIBOS_PANIC_REASON_CASE(InvalidConfiguration, "invalid configuration"); + LIBOS_PANIC_REASON_CASE(FatalHardwareError, "fatal hardware error"); + LIBOS_PANIC_REASON_CASE(InsufficientResources, "insufficient resources"); + LIBOS_PANIC_REASON_CASE(Timeout, "timeout"); + LIBOS_PANIC_REASON_CASE(EnvCallFailed, "environment call failed"); + LIBOS_PANIC_REASON_CASE(SspStackCheckFailed, "stack smashing detected"); + LIBOS_PANIC_REASON_CASE(AsanMemoryError, "asan memory error detected"); + LIBOS_PANIC_REASON_CASE(Test, "test"); + LIBOS_PANIC_REASON_CASE(ProgrammingError, "programming error"); + LIBOS_PANIC_REASON_CASE(DebugAssertionFailed, "debug assertion failed"); + default: return MAKE_NV_PRINTF_STR("unknown error"); + } +} + +void crashcatReportLogSource_V1_LIBOS2(CrashCatReport *pReport) +{ + NvCrashCatReport_V1 *pReportV1 = &pReport->v1.report; + + NvU8 taskId = crashcatReportV1SourceLibos2TaskId(pReportV1); + +#define CRASHCAT_LOG_LIBOS2_SOURCE(fmt, ...) \ + if (taskId == NV_CRASHCAT_REPORT_V1_SOURCE_ID_LIBOS2_TASK_ID_UNSPECIFIED) \ + crashcatEnginePrintf(pReport->pEngine, NV_TRUE, fmt, __VA_ARGS__ ); \ + else \ + crashcatEnginePrintf(pReport->pEngine, NV_TRUE, fmt ", task:%u", __VA_ARGS__, taskId) + + const char *pModeStr = crashcatReportModeToString_LIBOS2(crashcatReportV1SourceMode(pReportV1)); + switch (crashcatReportV1SourceCauseType(pReportV1)) + { + case NV_CRASHCAT_CAUSE_TYPE_EXCEPTION: + { + // Kernel or task unhandled exception - the sourceData is the xcause value + NvU64 xcause = pReportV1->sourceData; + CRASHCAT_LOG_LIBOS2_SOURCE( + "%s exception: %s (cause:0x%" NvU64_fmtx ") @ pc:0x%" NvU64_fmtx, + pModeStr, crashcatReportRiscvCauseToString(xcause), xcause, + pReportV1->sourcePc); + break; + } + case NV_CRASHCAT_CAUSE_TYPE_TIMEOUT: + { + // Task timeout (no way for libos2 to self-report kernel timeouts) + CRASHCAT_LOG_LIBOS2_SOURCE( + "%s timeout @ pc:0x%" NvU64_fmtx, pModeStr, pReportV1->sourcePc); + break; + } + case NV_CRASHCAT_CAUSE_TYPE_PANIC: + { + // Kernel or task panic + LibosPanicReason reason = crashcatReportV1SourceCauseLibos2Reason(pReportV1); + CRASHCAT_LOG_LIBOS2_SOURCE( + "%s panic: %s (%u) @ pc:0x%" NvU64_fmtx ", aux:0x%" NvU64_fmtx, + pModeStr, crashcatReportPanicReasonToString_LIBOS2(reason), + reason, pReportV1->sourcePc, pReportV1->sourceData); + break; + } + } +} + +void crashcatReportLogReporter_V1_LIBOS2(CrashCatReport *pReport) +{ + NvCrashCatReport_V1 *pReportV1 = &pReport->v1.report; + NvU8 taskId = crashcatReportV1ReporterLibos2TaskId(pReportV1); + + // + // Though this is technically not a separate packet, we use the CRASHCAT_REPORT_LOG_PACKET_TYPE + // macro to get the correct prefix/indentation for the reporter information. + // + if (taskId == NV_CRASHCAT_REPORT_V1_REPORTER_ID_LIBOS2_TASK_ID_UNSPECIFIED) + { + CRASHCAT_REPORT_LOG_PACKET_TYPE(pReport, "Reported by libos kernel v%u.%u [%u] @ %u", + crashcatReportV1ReporterVersionLibos2Major(pReportV1), + crashcatReportV1ReporterVersionLibos2Minor(pReportV1), + crashcatReportV1ReporterVersionLibos2Cl(pReportV1), + crashcatReportV1ReporterTimestamp(pReportV1)); + } + else + { + CRASHCAT_REPORT_LOG_PACKET_TYPE(pReport, "Reported by libos task:%u v%u.%u [%u] @ ts:%u", + taskId, crashcatReportV1ReporterVersionLibos2Major(pReportV1), + crashcatReportV1ReporterVersionLibos2Minor(pReportV1), + crashcatReportV1ReporterVersionLibos2Cl(pReportV1), + crashcatReportV1ReporterTimestamp(pReportV1)); + } +} diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/libraries/crashcat/v1/impl/crashcat_report_v1_libos3.c nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/libraries/crashcat/v1/impl/crashcat_report_v1_libos3.c --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/libraries/crashcat/v1/impl/crashcat_report_v1_libos3.c 1970-01-01 00:00:00.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/libraries/crashcat/v1/impl/crashcat_report_v1_libos3.c 2024-03-05 22:14:10.000000000 +0000 @@ -0,0 +1,149 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#define NVOC_CRASHCAT_REPORT_H_PRIVATE_ACCESS_ALLOWED +#include "crashcat/crashcat_report.h" +#include "crashcat/crashcat_engine.h" +#include "libos_v3_crashcat.h" +#include "utils/nvprintf.h" +#include "nv-crashcat-decoder.h" + +static inline const char *crashcatReportModeToString_LIBOS3(NV_CRASHCAT_RISCV_MODE mode) +{ + switch (mode) + { + case NV_CRASHCAT_RISCV_MODE_M: + return MAKE_NV_PRINTF_STR("monitor"); + case NV_CRASHCAT_RISCV_MODE_S: + return MAKE_NV_PRINTF_STR("kernel"); + case NV_CRASHCAT_RISCV_MODE_U: + return MAKE_NV_PRINTF_STR("task"); + default: + return MAKE_NV_PRINTF_STR("unspecified"); + } +} + +static inline const char *crashcatReportPanicReasonToString_LIBOS3(LibosPanicReason reason) +{ +#define LIBOS_PANIC_REASON_CASE(reason, str) \ + case LibosPanicReason ## reason: return MAKE_NV_PRINTF_STR(str) + + switch (reason) + { + LIBOS_PANIC_REASON_CASE(UnhandledState, "unhandled state"); + LIBOS_PANIC_REASON_CASE(InvalidConfiguration, "invalid configuration"); + LIBOS_PANIC_REASON_CASE(FatalHardwareError, "fatal hardware error"); + LIBOS_PANIC_REASON_CASE(InsufficientResources, "insufficient resources"); + LIBOS_PANIC_REASON_CASE(Timeout, "timeout"); + LIBOS_PANIC_REASON_CASE(EnvCallFailed, "environment call failed"); + LIBOS_PANIC_REASON_CASE(AsanMemoryError, "asan memory error detected"); + LIBOS_PANIC_REASON_CASE(ProgrammingError, "programming error"); + LIBOS_PANIC_REASON_CASE(AssertionFailed, "condition failed"); + LIBOS_PANIC_REASON_CASE(TrapKernelPanic, "unhandled trap"); + LIBOS_PANIC_REASON_CASE(TrapInstruction, "instruction access fault"); + default: return MAKE_NV_PRINTF_STR("unknown error"); + } +} + +void crashcatReportLogSource_V1_LIBOS3(CrashCatReport *pReport) +{ + NvCrashCatReport_V1 *pReportV1 = &pReport->v1.report; + + NvU8 taskId = crashcatReportV1SourceLibos3TaskId(pReportV1); + NvCrashCatNvriscvPartition sourcePartition = crashcatReportV1ReporterPartition(pReportV1); + NvCrashCatNvriscvUcodeId sourceUcodeId = crashcatReportV1ReporterUcodeId(pReportV1); + +#define CRASHCAT_LOG_LIBOS3_SOURCE(fmt, ...) \ + if (taskId == NV_CRASHCAT_REPORT_V1_SOURCE_ID_LIBOS3_TASK_ID_UNSPECIFIED) \ + crashcatEnginePrintf(pReport->pEngine, NV_TRUE, fmt ", partition:%u#%u", \ + __VA_ARGS__, sourcePartition, sourceUcodeId); \ + else \ + crashcatEnginePrintf(pReport->pEngine, NV_TRUE, fmt ", partition:%u#%u, task:%u", \ + __VA_ARGS__, sourcePartition, sourceUcodeId, taskId) + + const char *pModeStr = crashcatReportModeToString_LIBOS3(crashcatReportV1SourceMode(pReportV1)); + switch (crashcatReportV1SourceCauseType(pReportV1)) + { + case NV_CRASHCAT_CAUSE_TYPE_EXCEPTION: + { + // Kernel or task unhandled exception - the sourceData is the xcause value + NvU64 xcause = pReportV1->sourceData; + CRASHCAT_LOG_LIBOS3_SOURCE( + "%s exception: %s (cause:0x%" NvU64_fmtx ") @ pc:0x%" NvU64_fmtx, + pModeStr, crashcatReportRiscvCauseToString(xcause), + xcause, pReportV1->sourcePc); + break; + } + case NV_CRASHCAT_CAUSE_TYPE_TIMEOUT: + { + // Task timeout (no way for libos3 to self-report kernel timeouts) + CRASHCAT_LOG_LIBOS3_SOURCE( + "%s timeout @ pc:0x%" NvU64_fmtx, + pModeStr, pReportV1->sourcePc); + break; + } + case NV_CRASHCAT_CAUSE_TYPE_PANIC: + { + // Kernel or task panic + LibosPanicReason reason = crashcatReportV1SourceCauseLibos3Reason(pReportV1); + CRASHCAT_LOG_LIBOS3_SOURCE( + "%s panic: %s (%u) @ pc:0x%" NvU64_fmtx ", aux:0x%" NvU64_fmtx, + pModeStr, crashcatReportPanicReasonToString_LIBOS3(reason), reason, + pReportV1->sourcePc, pReportV1->sourceData); + break; + } + } +} + +void crashcatReportLogReporter_V1_LIBOS3(CrashCatReport *pReport) +{ + NvCrashCatReport_V1 *pReportV1 = &pReport->v1.report; + NvU8 taskId = crashcatReportV1ReporterLibos3TaskId(pReportV1); + + // + // Though this is technically not a separate packet, we use the CRASHCAT_REPORT_LOG_PACKET_TYPE + // macro to get the correct prefix/indentation for the reporter information. + // + if (taskId == NV_CRASHCAT_REPORT_V1_REPORTER_ID_LIBOS3_TASK_ID_UNSPECIFIED) + { + CRASHCAT_REPORT_LOG_PACKET_TYPE(pReport, + "Reported by libos partition:%u#%u kernel v%u.%u [%u] @ ts:%u", + crashcatReportV1ReporterPartition(pReportV1), + crashcatReportV1ReporterUcodeId(pReportV1), + crashcatReportV1ReporterVersionLibos3Major(pReportV1), + crashcatReportV1ReporterVersionLibos3Minor(pReportV1), + crashcatReportV1ReporterVersionLibos3Cl(pReportV1), + crashcatReportV1ReporterTimestamp(pReportV1)); + } + else + { + CRASHCAT_REPORT_LOG_PACKET_TYPE(pReport, + "Reported by libos partition:%u#%u task:%u v%u.%u [%u] @ ts:%u", + crashcatReportV1ReporterPartition(pReportV1), + crashcatReportV1ReporterUcodeId(pReportV1), + taskId, crashcatReportV1ReporterVersionLibos3Major(pReportV1), + crashcatReportV1ReporterVersionLibos3Minor(pReportV1), + crashcatReportV1ReporterVersionLibos3Cl(pReportV1), + crashcatReportV1ReporterTimestamp(pReportV1)); + } +} diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/libraries/eventbuffer/eventbufferproducer.c nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/libraries/eventbuffer/eventbufferproducer.c --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/libraries/eventbuffer/eventbufferproducer.c 2023-10-25 20:21:35.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/libraries/eventbuffer/eventbufferproducer.c 2024-03-05 22:14:10.000000000 +0000 @@ -26,7 +26,7 @@ // // This file contains generic event buffer producer implementation for adding variable length data -// +// // Data format: // // Event Record buffer holds fixed size records @@ -112,7 +112,7 @@ RECORD_BUFFER_INFO* pRecordBuffer = &info->recordBuffer; pRecordBuffer->pHeader->recordGet = get; - // used for notification + // used for notification _eventBufferUpdateRecordBufferCount(info); // dropCounts get reset on every updateGet call @@ -192,7 +192,7 @@ } } -NV_EVENT_BUFFER_RECORD* +NV_EVENT_BUFFER_RECORD* _eventBufferGetFreeRecord(EVENT_BUFFER_PRODUCER_INFO *info) { RECORD_BUFFER_INFO* pRecInfo = &info->recordBuffer; diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/libraries/ioaccess/ioaccess.c nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/libraries/ioaccess/ioaccess.c --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/libraries/ioaccess/ioaccess.c 2023-10-25 20:21:35.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/libraries/ioaccess/ioaccess.c 2024-03-05 22:14:10.000000000 +0000 @@ -25,66 +25,21 @@ #include "utils/nvprintf.h" #include "nvport/nvport.h" -/*! - * @brief: Allocate and initialize an IO_APERTURE instance. - * - * @param[out] ppAperture pointer to the new IO_APERTURE. - * @param[in] pParentAperture pointer to the parent of the new IO_APERTURE. - * @param[in] pDevice pointer to IO_DEVICE of the APERTURE. - * @param[in] offset offset from the parent APERTURE's baseAddress. - * @param[in] length length of the APERTURE. - * - * @return NV_OK upon success - * NV_ERR* otherwise. - */ -NV_STATUS -ioaccessCreateIOAperture -( - IO_APERTURE **ppAperture, - IO_APERTURE *pParentAperture, - IO_DEVICE *pDevice, - NvU32 offset, - NvU32 length -) -{ - NV_STATUS status = NV_OK; - IO_APERTURE *pAperture = portMemAllocNonPaged(sizeof(IO_APERTURE)); - - if (pAperture == NULL) - { - return NV_ERR_NO_MEMORY; - } - - portMemSet(pAperture, 0, sizeof(IO_APERTURE)); - - status = ioaccessInitIOAperture(pAperture, pParentAperture, pDevice, offset, length); - if (status != NV_OK) - { - portMemFree(pAperture); - } - else - { - *ppAperture = pAperture; - } - - return status; -} - - +#if !((defined(NVRM) || defined(RMCFG_FEATURE_PLATFORM_GSP)) && !defined(NVWATCH)) /*! * Initialize an IO_APERTURE instance. This enables initialization for derived IO_APERTURE instances * that are not allocated via CreateIOAperture. - * + * * @param[in,out] pAperture pointer to IO_APERTURE instance to be initialized. * @param[in] pParentAperture pointer to parent of the new IO_APERTURE. * @param[in] pDevice pointer to IO_DEVICE of the APERTURE. * @param[in] offset offset from the parent APERTURE's baseAddress. * @param[in] length length of the APERTURE. - * + * * @return NV_OK when inputs are valid. */ NV_STATUS -ioaccessInitIOAperture +ioaccessInitIOAperture ( IO_APERTURE *pAperture, IO_APERTURE *pParentAperture, @@ -120,7 +75,7 @@ // Check if the child Aperture strides beyond the parent's boundary. if ((length + offset) > pParentAperture->length) { - NV_PRINTF(LEVEL_WARNING, + NV_PRINTF(LEVEL_WARNING, "Child aperture crosses parent's boundary, length %u offset %u, Parent's length %u\n", length, offset, pParentAperture->length); } @@ -135,12 +90,4 @@ return NV_OK; } - -void -ioaccessDestroyIOAperture -( - IO_APERTURE *pAperture -) -{ - portMemFree(pAperture); -} +#endif // !((defined(NVRM) || defined(RMCFG_FEATURE_PLATFORM_GSP)) && !defined(NVWATCH)) diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/libraries/libspdm/2.3.1/include/hal/base.h nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/libraries/libspdm/2.3.1/include/hal/base.h --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/libraries/libspdm/2.3.1/include/hal/base.h 1970-01-01 00:00:00.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/libraries/libspdm/2.3.1/include/hal/base.h 2024-03-05 22:14:10.000000000 +0000 @@ -0,0 +1,87 @@ +/** + * Copyright Notice: + * Copyright 2021-2022 DMTF. All rights reserved. + * License: BSD 3-Clause License. For full text see link: https://github.com/DMTF/libspdm/blob/main/LICENSE.md + **/ + +#ifndef BASE_H +#define BASE_H + +#ifndef LIBSPDM_STDINT_ALT + +#include + +/* LIBSPDM_OPENSSL_STDINT_WORKAROUND */ + +/* This is a workaround for OpenSSL compilation problems when used with + * on Windows platforms built with Visual Studio. Including pulls in + * , which causes the type size_t to be defined. The size_t type + * depends on if _WIN32 or _WIN64 is defined. The default if neither is defined + * is the 32-bit version of size_t. */ + +/* Our OpenSSL compilation requires _WIN32 and _WIN64 to NOT be defined. + * This will force the to use the wrong 32-bit definition of size_t + * if we are compiling as 64-bit. This 32-bit definition then does not agree with + * the 64-bit definition defined in libspdm and generates compile errors. */ + +/* To workaround this issue, LIBSPDM_OPENSSL_STDINT_WORKAROUND was created + * that is only defined for compilation via tha makefile of the OpenSSL library + * portion of libspdm. */ + +/* This will lead to _WIN32 and _WIN64 to be NOT defined when reaching the OpenSSL + * portions of a compilation unit (header files + c file), thus meeting the + * no Win32/Win64 requirement for OpenSSL, but will still be defined when compiling + * the file in the compilation unit (and getting the right size_t). */ + +/* In the future libspdm intends to use the Windows native compilation flags and defines, + * in place of the UEFI profile / personality. */ + +#ifdef LIBSPDM_OPENSSL_STDINT_WORKAROUND +#undef _WIN32 +#undef _WIN64 +#endif + +#else /* LIBSPDM_STDINT_ALT */ +#include LIBSPDM_STDINT_ALT +#endif /* LIBSPDM_STDINT_ALT */ + +#ifndef LIBSPDM_STDBOOL_ALT +#include +#else +#include LIBSPDM_STDBOOL_ALT +#endif + +#ifndef LIBSPDM_STDDEF_ALT +#include +#else +#include LIBSPDM_STDDEF_ALT +#endif + +/** + * Return the minimum of two operands. + * + * This macro returns the minimal of two operand specified by a and b. + * Both a and b must be the same numerical types, signed or unsigned. + * + * @param a The first operand with any numerical type. + * @param b The second operand. It should be the same any numerical type with a. + * + * @return Minimum of two operands. + * + **/ +#define LIBSPDM_MIN(a, b) (((a) < (b)) ? (a) : (b)) + +/** + * Return the number of elements in an array. + * + * @param array An object of array type. Array is only used as an argument to + * the sizeof operator, therefore Array is never evaluated. The + * caller is responsible for ensuring that Array's type is not + * incomplete; that is, Array must have known constant size. + * + * @return The number of elements in Array. The result has type size_t. + * + **/ +#define LIBSPDM_ARRAY_SIZE(array) (sizeof(array) / sizeof((array)[0])) + +#endif /* BASE_H */ diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/libraries/libspdm/2.3.1/include/hal/library/cryptlib/cryptlib_aead.h nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/libraries/libspdm/2.3.1/include/hal/library/cryptlib/cryptlib_aead.h --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/libraries/libspdm/2.3.1/include/hal/library/cryptlib/cryptlib_aead.h 1970-01-01 00:00:00.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/libraries/libspdm/2.3.1/include/hal/library/cryptlib/cryptlib_aead.h 2024-03-05 22:14:10.000000000 +0000 @@ -0,0 +1,211 @@ +/** + * Copyright Notice: + * Copyright 2021-2022 DMTF. All rights reserved. + * License: BSD 3-Clause License. For full text see link: https://github.com/DMTF/libspdm/blob/main/LICENSE.md + **/ + +#ifndef CRYPTLIB_AEAD_H +#define CRYPTLIB_AEAD_H + +/*===================================================================================== + * Authenticated Encryption with Associated data (AEAD) Cryptography Primitives + *===================================================================================== + */ + +#if LIBSPDM_AEAD_GCM_SUPPORT +/** + * Performs AEAD AES-GCM authenticated encryption on a data buffer and additional authenticated + * data. + * + * iv_size must be 12, otherwise false is returned. + * key_size must be 16 or 32, otherwise false is returned. + * tag_size must be 12, 13, 14, 15, 16, otherwise false is returned. + * + * @param[in] key Pointer to the encryption key. + * @param[in] key_size Size of the encryption key in bytes. + * @param[in] iv Pointer to the IV value. + * @param[in] iv_size Size of the IV value in bytes. + * @param[in] a_data Pointer to the additional authenticated data. + * @param[in] a_data_size Size of the additional authenticated data in bytes. + * @param[in] data_in Pointer to the input data buffer to be encrypted. + * @param[in] data_in_size Size of the input data buffer in bytes. + * @param[out] tag_out Pointer to a buffer that receives the authentication tag output. + * @param[in] tag_size Size of the authentication tag in bytes. + * @param[out] data_out Pointer to a buffer that receives the encryption output. + * @param[out] data_out_size Size of the output data buffer in bytes. + * + * @retval true AEAD AES-GCM authenticated encryption succeeded. + * @retval false AEAD AES-GCM authenticated encryption failed. + **/ +extern bool libspdm_aead_aes_gcm_encrypt(const uint8_t *key, size_t key_size, + const uint8_t *iv, size_t iv_size, + const uint8_t *a_data, size_t a_data_size, + const uint8_t *data_in, size_t data_in_size, + uint8_t *tag_out, size_t tag_size, + uint8_t *data_out, size_t *data_out_size); + +/** + * Performs AEAD AES-GCM authenticated decryption on a data buffer and additional authenticated + * data. + * + * iv_size must be 12, otherwise false is returned. + * key_size must be 16 or 32, otherwise false is returned. + * tag_size must be 12, 13, 14, 15, 16, otherwise false is returned. + * + * If data verification fails, false is returned. + * + * @param[in] key Pointer to the encryption key. + * @param[in] key_size Size of the encryption key in bytes. + * @param[in] iv Pointer to the IV value. + * @param[in] iv_size Size of the IV value in bytes. + * @param[in] a_data Pointer to the additional authenticated data. + * @param[in] a_data_size Size of the additional authenticated data in bytes. + * @param[in] data_in Pointer to the input data buffer to be decrypted. + * @param[in] data_in_size Size of the input data buffer in bytes. + * @param[in] tag Pointer to a buffer that contains the authentication tag. + * @param[in] tag_size Size of the authentication tag in bytes. + * @param[out] data_out Pointer to a buffer that receives the decryption output. + * @param[out] data_out_size Size of the output data buffer in bytes. + * + * @retval true AEAD AES-GCM authenticated decryption succeeded. + * @retval false AEAD AES-GCM authenticated decryption failed. + **/ +extern bool libspdm_aead_aes_gcm_decrypt(const uint8_t *key, size_t key_size, + const uint8_t *iv, size_t iv_size, + const uint8_t *a_data, size_t a_data_size, + const uint8_t *data_in, size_t data_in_size, + const uint8_t *tag, size_t tag_size, + uint8_t *data_out, size_t *data_out_size); +#endif /* LIBSPDM_AEAD_GCM_SUPPORT */ + +#if LIBSPDM_AEAD_CHACHA20_POLY1305_SUPPORT +/** + * Performs AEAD ChaCha20Poly1305 authenticated encryption on a data buffer and additional + * authenticated data. + * + * iv_size must be 12, otherwise false is returned. + * key_size must be 32, otherwise false is returned. + * tag_size must be 16, otherwise false is returned. + * + * @param[in] key Pointer to the encryption key. + * @param[in] key_size Size of the encryption key in bytes. + * @param[in] iv Pointer to the IV value. + * @param[in] iv_size Size of the IV value in bytes. + * @param[in] a_data Pointer to the additional authenticated data. + * @param[in] a_data_size Size of the additional authenticated data in bytes. + * @param[in] data_in Pointer to the input data buffer to be encrypted. + * @param[in] data_in_size Size of the input data buffer in bytes. + * @param[out] tag_out Pointer to a buffer that receives the authentication tag output. + * @param[in] tag_size Size of the authentication tag in bytes. + * @param[out] data_out Pointer to a buffer that receives the encryption output. + * @param[out] data_out_size Size of the output data buffer in bytes. + * + * @retval true AEAD ChaCha20Poly1305 authenticated encryption succeeded. + * @retval false AEAD ChaCha20Poly1305 authenticated encryption failed. + **/ +extern bool libspdm_aead_chacha20_poly1305_encrypt( + const uint8_t *key, size_t key_size, const uint8_t *iv, + size_t iv_size, const uint8_t *a_data, size_t a_data_size, + const uint8_t *data_in, size_t data_in_size, uint8_t *tag_out, + size_t tag_size, uint8_t *data_out, size_t *data_out_size); + +/** + * Performs AEAD ChaCha20Poly1305 authenticated decryption on a data buffer and additional authenticated data (AAD). + * + * iv_size must be 12, otherwise false is returned. + * key_size must be 32, otherwise false is returned. + * tag_size must be 16, otherwise false is returned. + * + * If data verification fails, false is returned. + * + * @param[in] key Pointer to the encryption key. + * @param[in] key_size Size of the encryption key in bytes. + * @param[in] iv Pointer to the IV value. + * @param[in] iv_size Size of the IV value in bytes. + * @param[in] a_data Pointer to the additional authenticated data. + * @param[in] a_data_size Size of the additional authenticated data in bytes. + * @param[in] data_in Pointer to the input data buffer to be decrypted. + * @param[in] data_in_size Size of the input data buffer in bytes. + * @param[in] tag Pointer to a buffer that contains the authentication tag. + * @param[in] tag_size Size of the authentication tag in bytes. + * @param[out] data_out Pointer to a buffer that receives the decryption output. + * @param[out] data_out_size Size of the output data buffer in bytes. + * + * @retval true AEAD ChaCha20Poly1305 authenticated decryption succeeded. + * @retval false AEAD ChaCha20Poly1305 authenticated decryption failed. + * + **/ +extern bool libspdm_aead_chacha20_poly1305_decrypt( + const uint8_t *key, size_t key_size, const uint8_t *iv, + size_t iv_size, const uint8_t *a_data, size_t a_data_size, + const uint8_t *data_in, size_t data_in_size, const uint8_t *tag, + size_t tag_size, uint8_t *data_out, size_t *data_out_size); +#endif /* LIBSPDM_AEAD_CHACHA20_POLY1305_SUPPORT */ + +#if LIBSPDM_AEAD_SM4_SUPPORT +/** + * Performs AEAD SM4-GCM authenticated encryption on a data buffer and additional authenticated + * data. + * + * iv_size must be 12, otherwise false is returned. + * key_size must be 16, otherwise false is returned. + * tag_size must be 16, otherwise false is returned. + * + * @param[in] key Pointer to the encryption key. + * @param[in] key_size Size of the encryption key in bytes. + * @param[in] iv Pointer to the IV value. + * @param[in] iv_size Size of the IV value in bytes. + * @param[in] a_data Pointer to the additional authenticated data. + * @param[in] a_data_size Size of the additional authenticated data in bytes. + * @param[in] data_in Pointer to the input data buffer to be encrypted. + * @param[in] data_in_size Size of the input data buffer in bytes. + * @param[out] tag_out Pointer to a buffer that receives the authentication tag output. + * @param[in] tag_size Size of the authentication tag in bytes. + * @param[out] data_out Pointer to a buffer that receives the encryption output. + * @param[out] data_out_size Size of the output data buffer in bytes. + * + * @retval true AEAD SM4-GCM authenticated encryption succeeded. + * @retval false AEAD SM4-GCM authenticated encryption failed. + **/ +extern bool libspdm_aead_sm4_gcm_encrypt(const uint8_t *key, size_t key_size, + const uint8_t *iv, size_t iv_size, + const uint8_t *a_data, size_t a_data_size, + const uint8_t *data_in, size_t data_in_size, + uint8_t *tag_out, size_t tag_size, + uint8_t *data_out, size_t *data_out_size); + +/** + * Performs AEAD SM4-GCM authenticated decryption on a data buffer and additional authenticated + * data. + * + * iv_size must be 12, otherwise false is returned. + * key_size must be 16, otherwise false is returned. + * tag_size must be 16, otherwise false is returned. + * + * If data verification fails, false is returned. + * + * @param[in] key Pointer to the encryption key. + * @param[in] key_size Size of the encryption key in bytes. + * @param[in] iv Pointer to the IV value. + * @param[in] iv_size Size of the IV value in bytes. + * @param[in] a_data Pointer to the additional authenticated data. + * @param[in] a_data_size Size of the additional authenticated data in bytes. + * @param[in] data_in Pointer to the input data buffer to be decrypted. + * @param[in] data_in_size Size of the input data buffer in bytes. + * @param[in] tag Pointer to a buffer that contains the authentication tag. + * @param[in] tag_size Size of the authentication tag in bytes. + * @param[out] data_out Pointer to a buffer that receives the decryption output. + * @param[out] data_out_size Size of the output data buffer in bytes. + * + * @retval true AEAD SM4-GCM authenticated decryption succeeded. + * @retval false AEAD SM4-GCM authenticated decryption failed. + **/ +extern bool libspdm_aead_sm4_gcm_decrypt(const uint8_t *key, size_t key_size, + const uint8_t *iv, size_t iv_size, + const uint8_t *a_data, size_t a_data_size, + const uint8_t *data_in, size_t data_in_size, + const uint8_t *tag, size_t tag_size, + uint8_t *data_out, size_t *data_out_size); +#endif /* LIBSPDM_AEAD_SM4_SUPPORT */ + +#endif /* CRYPTLIB_AEAD_H */ diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/libraries/libspdm/2.3.1/include/hal/library/cryptlib/cryptlib_cert.h nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/libraries/libspdm/2.3.1/include/hal/library/cryptlib/cryptlib_cert.h --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/libraries/libspdm/2.3.1/include/hal/library/cryptlib/cryptlib_cert.h 1970-01-01 00:00:00.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/libraries/libspdm/2.3.1/include/hal/library/cryptlib/cryptlib_cert.h 2024-03-05 22:14:11.000000000 +0000 @@ -0,0 +1,416 @@ +/** + * Copyright Notice: + * Copyright 2021-2022 DMTF. All rights reserved. + * License: BSD 3-Clause License. For full text see link: https://github.com/DMTF/libspdm/blob/main/LICENSE.md + **/ + +#ifndef CRYPTLIB_CERT_H +#define CRYPTLIB_CERT_H + +/** + * Retrieve the tag and length of the tag. + * + * @param ptr The position in the ASN.1 data. + * @param end End of data. + * @param length The variable that will receive the length. + * @param tag The expected tag. + * + * @retval true Get tag successful. + * @retval false Failed to get tag or tag not match. + **/ +extern bool libspdm_asn1_get_tag(uint8_t **ptr, const uint8_t *end, size_t *length, uint32_t tag); + +/** + * Retrieve the subject bytes from one X.509 certificate. + * + * If cert is NULL, then return false. + * If subject_size is NULL, then return false. + * If this interface is not supported, then return false. + * + * @param[in] cert Pointer to the DER-encoded X509 certificate. + * @param[in] cert_size Size of the X509 certificate in bytes. + * @param[out] cert_subject Pointer to the retrieved certificate subject bytes. + * @param[in, out] subject_size The size in bytes of the cert_subject buffer on input, + * and the size of buffer returned cert_subject on output. + * + * @retval true The certificate subject retrieved successfully. + * @retval false Invalid certificate, or the subject_size is too small for the result. + * The subject_size will be updated with the required size. + * @retval false This interface is not supported. + **/ +extern bool libspdm_x509_get_subject_name(const uint8_t *cert, size_t cert_size, + uint8_t *cert_subject, + size_t *subject_size); + +/** + * Retrieve the version from one X.509 certificate. + * + * If cert is NULL, then return false. + * If cert_size is 0, then return false. + * If this interface is not supported, then return false. + * + * @param[in] cert Pointer to the DER-encoded X509 certificate. + * @param[in] cert_size Size of the X509 certificate in bytes. + * @param[out] version Pointer to the retrieved version integer. + * + * @retval true + * @retval false + **/ +extern bool libspdm_x509_get_version(const uint8_t *cert, size_t cert_size, size_t *version); + +/** + * Retrieve the serialNumber from one X.509 certificate. + * + * If cert is NULL, then return false. + * If cert_size is 0, then return false. + * If this interface is not supported, then return false. + * + * @param[in] cert Pointer to the DER-encoded X509 certificate. + * @param[in] cert_size Size of the X509 certificate in bytes. + * @param[out] serial_number Pointer to the retrieved certificate serial_number bytes. + * @param[in, out] serial_number_size The size in bytes of the serial_number buffer on input, + * and the size of buffer returned serial_number on output. + * + * @retval true + * @retval false + **/ +extern bool libspdm_x509_get_serial_number(const uint8_t *cert, size_t cert_size, + uint8_t *serial_number, + size_t *serial_number_size); + +/** + * Retrieve the issuer bytes from one X.509 certificate. + * + * If cert is NULL, then return false. + * If issuer_size is NULL, then return false. + * If this interface is not supported, then return false. + * + * @param[in] cert Pointer to the DER-encoded X509 certificate. + * @param[in] cert_size Size of the X509 certificate in bytes. + * @param[out] cert_issuer Pointer to the retrieved certificate subject bytes. + * @param[in, out] issuer_size The size in bytes of the cert_issuer buffer on input, + * and the size of buffer returned cert_issuer on output. + * + * @retval true The certificate issuer retrieved successfully. + * @retval false Invalid certificate, or the issuer_size is too small for the result. + * The issuer_size will be updated with the required size. + * @retval false This interface is not supported. + **/ +extern bool libspdm_x509_get_issuer_name(const uint8_t *cert, size_t cert_size, + uint8_t *cert_issuer, + size_t *issuer_size); + +/** + * Retrieve Extension data from one X.509 certificate. + * + * @param[in] cert Pointer to the DER-encoded X509 certificate. + * @param[in] cert_size Size of the X509 certificate in bytes. + * @param[in] oid Object identifier buffer + * @param[in] oid_size Object identifier buffer size + * @param[out] extension_data Extension bytes. + * @param[in, out] extension_data_size Extension bytes size. + * + * @retval true + * @retval false + **/ +extern bool libspdm_x509_get_extension_data(const uint8_t *cert, size_t cert_size, + const uint8_t *oid, size_t oid_size, + uint8_t *extension_data, + size_t *extension_data_size); + +/** + * Retrieve the Validity from one X.509 certificate + * + * If cert is NULL, then return false. + * If CertIssuerSize is NULL, then return false. + * If this interface is not supported, then return false. + * + * @param[in] cert Pointer to the DER-encoded X509 certificate. + * @param[in] cert_size Size of the X509 certificate in bytes. + * @param[out] from notBefore Pointer to date_time object. + * @param[in,out] from_size notBefore date_time object size. + * @param[out] to notAfter Pointer to date_time object. + * @param[in,out] to_size notAfter date_time object size. + * + * Note: libspdm_x509_compare_date_time to compare date_time oject + * x509SetDateTime to get a date_time object from a date_time_str + * + * @retval true The certificate Validity retrieved successfully. + * @retval false Invalid certificate, or Validity retrieve failed. + * @retval false This interface is not supported. + **/ +extern bool libspdm_x509_get_validity(const uint8_t *cert, size_t cert_size, + uint8_t *from, size_t *from_size, uint8_t *to, + size_t *to_size); + +/** + * Format a date_time object into DataTime buffer + * + * If date_time_str is NULL, then return false. + * If date_time_size is NULL, then return false. + * If this interface is not supported, then return false. + * + * @param[in] date_time_str date_time string like YYYYMMDDhhmmssZ + * Ref: https://www.w3.org/TR/NOTE-datetime + * Z stand for UTC time + * @param[out] date_time Pointer to a date_time object. + * @param[in,out] date_time_size date_time object buffer size. + * + * @retval true + * @retval false + **/ +extern bool libspdm_x509_set_date_time(const char *date_time_str, void *date_time, + size_t *date_time_size); + +/** + * Compare date_time1 object and date_time2 object. + * + * If date_time1 is NULL, then return -2. + * If date_time2 is NULL, then return -2. + * If date_time1 == date_time2, then return 0 + * If date_time1 > date_time2, then return 1 + * If date_time1 < date_time2, then return -1 + * + * @param[in] date_time1 Pointer to a date_time Ojbect + * @param[in] date_time2 Pointer to a date_time Object + * + * @retval 0 If date_time1 == date_time2 + * @retval 1 If date_time1 > date_time2 + * @retval -1 If date_time1 < date_time2 + **/ +extern int32_t libspdm_x509_compare_date_time(const void *date_time1, const void *date_time2); + +/** + * Retrieve the key usage from one X.509 certificate. + * + * @param[in] cert Pointer to the DER-encoded X509 certificate. + * @param[in] cert_size Size of the X509 certificate in bytes. + * @param[out] usage Key usage (LIBSPDM_CRYPTO_X509_KU_*) + * + * @retval true The certificate key usage retrieved successfully. + * @retval false Invalid certificate, or usage is NULL + * @retval false This interface is not supported. + **/ +extern bool libspdm_x509_get_key_usage(const uint8_t *cert, size_t cert_size, size_t *usage); + +/** + * Retrieve the Extended key usage from one X.509 certificate. + * + * @param[in] cert Pointer to the DER-encoded X509 certificate. + * @param[in] cert_size Size of the X509 certificate in bytes. + * @param[out] usage Key usage bytes. + * @param[in, out] usage_size Key usage buffer sizs in bytes. + * + * @retval true + * @retval false + **/ +extern bool libspdm_x509_get_extended_key_usage(const uint8_t *cert, + size_t cert_size, uint8_t *usage, + size_t *usage_size); + +/** + * Retrieve the basic constraints from one X.509 certificate. + * + * @param[in] cert Pointer to the DER-encoded X509 certificate. + * @param[in] cert_size Size of the X509 certificate in bytes. + * @param[out] basic_constraints Basic constraints bytes. + * @param[in, out] basic_constraints_size Basic constraints buffer sizs in bytes. + * + * @retval true + * @retval false + **/ +extern bool libspdm_x509_get_extended_basic_constraints(const uint8_t *cert, + size_t cert_size, + uint8_t *basic_constraints, + size_t *basic_constraints_size); + +/** + * Verify one X509 certificate was issued by the trusted CA. + * + * If cert is NULL, then return false. + * If ca_cert is NULL, then return false. + * If this interface is not supported, then return false. + * + * @param[in] cert Pointer to the DER-encoded X509 certificate to be verified. + * @param[in] cert_size Size of the X509 certificate in bytes. + * @param[in] ca_cert Pointer to the DER-encoded trusted CA certificate. + * @param[in] ca_cert_size Size of the CA Certificate in bytes. + * + * @retval true The certificate was issued by the trusted CA. + * @retval false Invalid certificate or the certificate was not issued by the given + * trusted CA. + * @retval false This interface is not supported. + * + **/ +extern bool libspdm_x509_verify_cert(const uint8_t *cert, size_t cert_size, + const uint8_t *ca_cert, size_t ca_cert_size); + +/** + * Verify one X509 certificate was issued by the trusted CA. + * + * @param[in] cert_chain One or more ASN.1 DER-encoded X.509 certificates + * where the first certificate is signed by the Root + * Certificate or is the Root Cerificate itself. and + * subsequent cerificate is signed by the preceding + * cerificate. + * @param[in] cert_chain_length Total length of the certificate chain, in bytes. + * + * @param[in] root_cert Trusted Root Certificate buffer. + * + * @param[in] root_cert_length Trusted Root Certificate buffer length. + * + * @retval true All cerificates were issued by the first certificate in X509Certchain. + * @retval false Invalid certificate or the certificate was not issued by the given + * trusted CA. + **/ +extern bool libspdm_x509_verify_cert_chain(const uint8_t *root_cert, size_t root_cert_length, + const uint8_t *cert_chain, + size_t cert_chain_length); + +/** + * Get one X509 certificate from cert_chain. + * + * @param[in] cert_chain One or more ASN.1 DER-encoded X.509 certificates + * where the first certificate is signed by the Root + * Certificate or is the Root Cerificate itself. and + * subsequent cerificate is signed by the preceding + * cerificate. + * @param[in] cert_chain_length Total length of the certificate chain, in bytes. + * + * @param[in] cert_index Index of certificate. If index is -1 indecate the + * last certificate in cert_chain. + * + * @param[out] cert The certificate at the index of cert_chain. + * @param[out] cert_length The length certificate at the index of cert_chain. + * + * @retval true Success. + * @retval false Failed to get certificate from certificate chain. + **/ +extern bool libspdm_x509_get_cert_from_cert_chain(const uint8_t *cert_chain, + size_t cert_chain_length, + const int32_t cert_index, const uint8_t **cert, + size_t *cert_length); + +#if (LIBSPDM_RSA_SSA_SUPPORT) || (LIBSPDM_RSA_PSS_SUPPORT) +/** + * Retrieve the RSA public key from one DER-encoded X509 certificate. + * + * If cert is NULL, then return false. + * If rsa_context is NULL, then return false. + * If this interface is not supported, then return false. + * + * @param[in] cert Pointer to the DER-encoded X509 certificate. + * @param[in] cert_size Size of the X509 certificate in bytes. + * @param[out] rsa_context Pointer to new-generated RSA context which contain the retrieved + * RSA public key component. Use libspdm_rsa_free() function to free the + * resource. + * + * @retval true RSA public key was retrieved successfully. + * @retval false Fail to retrieve RSA public key from X509 certificate. + * @retval false This interface is not supported. + **/ +extern bool libspdm_rsa_get_public_key_from_x509(const uint8_t *cert, size_t cert_size, + void **rsa_context); +#endif /* (LIBSPDM_RSA_SSA_SUPPORT) || (LIBSPDM_RSA_PSS_SUPPORT) */ + +#if LIBSPDM_ECDSA_SUPPORT +/** + * Retrieve the EC public key from one DER-encoded X509 certificate. + * + * @param[in] cert Pointer to the DER-encoded X509 certificate. + * @param[in] cert_size Size of the X509 certificate in bytes. + * @param[out] ec_context Pointer to new-generated EC DSA context which contain the retrieved + * EC public key component. Use libspdm_ec_free() function to free the + * resource. + * + * If cert is NULL, then return false. + * If ec_context is NULL, then return false. + * + * @retval true EC public key was retrieved successfully. + * @retval false Fail to retrieve EC public key from X509 certificate. + * + **/ +extern bool libspdm_ec_get_public_key_from_x509(const uint8_t *cert, size_t cert_size, + void **ec_context); +#endif /* LIBSPDM_ECDSA_SUPPORT */ + +#if (LIBSPDM_EDDSA_ED25519_SUPPORT) || (LIBSPDM_EDDSA_ED448_SUPPORT) +/** + * Retrieve the Ed public key from one DER-encoded X509 certificate. + * + * @param[in] cert Pointer to the DER-encoded X509 certificate. + * @param[in] cert_size Size of the X509 certificate in bytes. + * @param[out] ecd_context Pointer to new-generated Ed DSA context which contain the retrieved + * Ed public key component. Use libspdm_ecd_free() function to free the + * resource. + * + * If cert is NULL, then return false. + * If ecd_context is NULL, then return false. + * + * @retval true Ed public key was retrieved successfully. + * @retval false Fail to retrieve Ed public key from X509 certificate. + * + **/ +extern bool libspdm_ecd_get_public_key_from_x509(const uint8_t *cert, size_t cert_size, + void **ecd_context); +#endif /* (LIBSPDM_EDDSA_ED25519_SUPPORT) || (LIBSPDM_EDDSA_ED448_SUPPORT) */ + +#if LIBSPDM_SM2_DSA_SUPPORT +/** + * Retrieve the sm2 public key from one DER-encoded X509 certificate. + * + * @param[in] cert Pointer to the DER-encoded X509 certificate. + * @param[in] cert_size Size of the X509 certificate in bytes. + * @param[out] sm2_context Pointer to new-generated sm2 context which contain the retrieved + * sm2 public key component. Use sm2_free() function to free the + * resource. + * + * If cert is NULL, then return false. + * If sm2_context is NULL, then return false. + * + * @retval true sm2 public key was retrieved successfully. + * @retval false Fail to retrieve sm2 public key from X509 certificate. + * + **/ +extern bool libspdm_sm2_get_public_key_from_x509(const uint8_t *cert, size_t cert_size, + void **sm2_context); +#endif /* LIBSPDM_SM2_DSA_SUPPORT */ + +#if LIBSPDM_ENABLE_CAPABILITY_GET_CSR_CAP +/** + * Generate a CSR. + * + * @param[in] hash_nid hash algo for sign + * @param[in] asym_nid asym algo for sign + * + * @param[in] requester_info requester info to gen CSR + * @param[in] requester_info_length The len of requester info + * + * @param[in] context Pointer to asymmetric context + * @param[in] subject_name Subject name: should be break with ',' in the middle + * example: "C=AA,CN=BB" + * + * Subject names should contain a comma-separated list of OID types and values: + * The valid OID type name is in: + * {"CN", "commonName", "C", "countryName", "O", "organizationName","L", + * "OU", "organizationalUnitName", "ST", "stateOrProvinceName", "emailAddress", + * "serialNumber", "postalAddress", "postalCode", "dnQualifier", "title", + * "SN","givenName","GN", "initials", "pseudonym", "generationQualifier", "domainComponent", "DC"}. + * Note: The object of C and countryName should be CSR Supported Country Codes + * + * @param[in] csr_len For input, csr_len is the size of store CSR buffer. + * For output, csr_len is CSR len for DER format + * @param[in] csr_pointer For input, csr_pointer is buffer address to store CSR. + * For output, csr_pointer is address for stored CSR. + * The csr_pointer address will be changed. + * + * @retval true Success. + * @retval false Failed to gen CSR. + **/ +extern bool libspdm_gen_x509_csr(size_t hash_nid, size_t asym_nid, + uint8_t *requester_info, size_t requester_info_length, + void *context, char *subject_name, + size_t *csr_len, uint8_t **csr_pointer); +#endif /* LIBSPDM_ENABLE_CAPABILITY_GET_CSR_CAP */ + +#endif /* CRYPTLIB_CERT_H */ diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/libraries/libspdm/2.3.1/include/hal/library/cryptlib/cryptlib_dh.h nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/libraries/libspdm/2.3.1/include/hal/library/cryptlib/cryptlib_dh.h --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/libraries/libspdm/2.3.1/include/hal/library/cryptlib/cryptlib_dh.h 1970-01-01 00:00:00.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/libraries/libspdm/2.3.1/include/hal/library/cryptlib/cryptlib_dh.h 2024-03-05 22:14:11.000000000 +0000 @@ -0,0 +1,98 @@ +/** + * Copyright Notice: + * Copyright 2021-2022 DMTF. All rights reserved. + * License: BSD 3-Clause License. For full text see link: https://github.com/DMTF/libspdm/blob/main/LICENSE.md + **/ + +#ifndef CRYPTLIB_DH_H +#define CRYPTLIB_DH_H + +/*===================================================================================== + * Diffie-Hellman Key Exchange Primitives + *===================================================================================== + */ + +#if LIBSPDM_FFDHE_SUPPORT +/** + * Allocates and initializes one Diffie-Hellman context for subsequent use with the NID. + * + * @param nid cipher NID + * + * @return Pointer to the Diffie-Hellman context that has been initialized. + * If the allocations fails, libspdm_dh_new_by_nid() returns NULL. + * If the interface is not supported, libspdm_dh_new_by_nid() returns NULL. + **/ +extern void *libspdm_dh_new_by_nid(size_t nid); + +/** + * Release the specified DH context. + * + * @param[in] dh_context Pointer to the DH context to be released. + **/ +void libspdm_dh_free(void *dh_context); + +/** + * Generates DH public key. + * + * This function generates random secret exponent, and computes the public key, which is + * returned via parameter public_key and public_key_size. DH context is updated accordingly. + * If the public_key buffer is too small to hold the public key, false is returned and + * public_key_size is set to the required buffer size to obtain the public key. + * + * If dh_context is NULL, then return false. + * If public_key_size is NULL, then return false. + * If public_key_size is large enough but public_key is NULL, then return false. + * If this interface is not supported, then return false. + * + * For FFDHE2048, the public_size is 256. + * For FFDHE3072, the public_size is 384. + * For FFDHE4096, the public_size is 512. + * + * @param[in, out] dh_context Pointer to the DH context. + * @param[out] public_key Pointer to the buffer to receive generated public key. + * @param[in, out] public_key_size On input, the size of public_key buffer in bytes. + * On output, the size of data returned in public_key buffer in + * bytes. + * + * @retval true DH public key generation succeeded. + * @retval false DH public key generation failed. + * @retval false public_key_size is not large enough. + * @retval false This interface is not supported. + **/ +extern bool libspdm_dh_generate_key(void *dh_context, uint8_t *public_key, size_t *public_key_size); + +/** + * Computes exchanged common key. + * + * Given peer's public key, this function computes the exchanged common key, based on its own + * context including value of prime modulus and random secret exponent. + * + * If dh_context is NULL, then return false. + * If peer_public_key is NULL, then return false. + * If key_size is NULL, then return false. + * If key is NULL, then return false. + * If key_size is not large enough, then return false. + * If this interface is not supported, then return false. + * + * For FFDHE2048, the peer_public_size and key_size is 256. + * For FFDHE3072, the peer_public_size and key_size is 384. + * For FFDHE4096, the peer_public_size and key_size is 512. + * + * @param[in, out] dh_context Pointer to the DH context. + * @param[in] peer_public_key Pointer to the peer's public key. + * @param[in] peer_public_key_size size of peer's public key in bytes. + * @param[out] key Pointer to the buffer to receive generated key. + * @param[in, out] key_size On input, the size of key buffer in bytes. + * On output, the size of data returned in key buffer in + * bytes. + * + * @retval true DH exchanged key generation succeeded. + * @retval false DH exchanged key generation failed. + * @retval false key_size is not large enough. + * @retval false This interface is not supported. + **/ +extern bool libspdm_dh_compute_key(void *dh_context, const uint8_t *peer_public_key, + size_t peer_public_key_size, uint8_t *key, + size_t *key_size); +#endif /* LIBSPDM_FFDHE_SUPPORT */ +#endif /* CRYPTLIB_DH_H */ diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/libraries/libspdm/2.3.1/include/hal/library/cryptlib/cryptlib_ec.h nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/libraries/libspdm/2.3.1/include/hal/library/cryptlib/cryptlib_ec.h --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/libraries/libspdm/2.3.1/include/hal/library/cryptlib/cryptlib_ec.h 1970-01-01 00:00:00.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/libraries/libspdm/2.3.1/include/hal/library/cryptlib/cryptlib_ec.h 2024-03-05 22:14:11.000000000 +0000 @@ -0,0 +1,162 @@ +/** + * Copyright Notice: + * Copyright 2021-2022 DMTF. All rights reserved. + * License: BSD 3-Clause License. For full text see link: https://github.com/DMTF/libspdm/blob/main/LICENSE.md + **/ + +#ifndef CRYPTLIB_EC_H +#define CRYPTLIB_EC_H + +/*===================================================================================== + * Elliptic Curve Primitives + *=====================================================================================*/ + +#if (LIBSPDM_ECDHE_SUPPORT) || (LIBSPDM_ECDSA_SUPPORT) +/** + * Allocates and Initializes one Elliptic Curve context for subsequent use with the NID. + * + * @param nid cipher NID + * + * @return Pointer to the Elliptic Curve context that has been initialized. + * If the allocations fails, libspdm_ec_new_by_nid() returns NULL. + **/ +extern void *libspdm_ec_new_by_nid(size_t nid); + +/** + * Release the specified EC context. + * + * @param[in] ec_context Pointer to the EC context to be released. + **/ +extern void libspdm_ec_free(void *ec_context); +#endif /* (LIBSPDM_ECDHE_SUPPORT) || (LIBSPDM_ECDSA_SUPPORT) */ + +#if LIBSPDM_ECDHE_SUPPORT +/** + * Generates EC key and returns EC public key (X, Y). + * + * This function generates random secret, and computes the public key (X, Y), which is + * returned via parameter public, public_size. + * X is the first half of public with size being public_size / 2, + * Y is the second half of public with size being public_size / 2. + * EC context is updated accordingly. + * If the public buffer is too small to hold the public X, Y, false is returned and + * public_size is set to the required buffer size to obtain the public X, Y. + * + * For P-256, the public_size is 64. first 32-byte is X, second 32-byte is Y. + * For P-384, the public_size is 96. first 48-byte is X, second 48-byte is Y. + * For P-521, the public_size is 132. first 66-byte is X, second 66-byte is Y. + * + * If ec_context is NULL, then return false. + * If public_size is NULL, then return false. + * If public_size is large enough but public is NULL, then return false. + * + * @param[in, out] ec_context Pointer to the EC context. + * @param[out] public Pointer to the buffer to receive generated public X,Y. + * @param[in, out] public_size On input, the size of public buffer in bytes. + * On output, the size of data returned in public buffer in bytes. + * + * @retval true EC public X,Y generation succeeded. + * @retval false EC public X,Y generation failed. + * @retval false public_size is not large enough. + **/ +extern bool libspdm_ec_generate_key(void *ec_context, uint8_t *public_key, size_t *public_key_size); + +/** + * Computes exchanged common key. + * + * Given peer's public key (X, Y), this function computes the exchanged common key, + * based on its own context including value of curve parameter and random secret. + * X is the first half of peer_public with size being peer_public_size / 2, + * Y is the second half of peer_public with size being peer_public_size / 2. + * + * If ec_context is NULL, then return false. + * If peer_public is NULL, then return false. + * If peer_public_size is 0, then return false. + * If key is NULL, then return false. + * If key_size is not large enough, then return false. + * + * For P-256, the peer_public_size is 64. first 32-byte is X, second 32-byte is Y. + * The key_size is 32. + * For P-384, the peer_public_size is 96. first 48-byte is X, second 48-byte is Y. + * The key_size is 48. + * For P-521, the peer_public_size is 132. first 66-byte is X, second 66-byte is Y. + * The key_size is 66. + * + * @param[in, out] ec_context Pointer to the EC context. + * @param[in] peer_public Pointer to the peer's public X,Y. + * @param[in] peer_public_size Size of peer's public X,Y in bytes. + * @param[out] key Pointer to the buffer to receive generated key. + * @param[in, out] key_size On input, the size of key buffer in bytes. + * On output, the size of data returned in key buffer in bytes. + * + * @retval true EC exchanged key generation succeeded. + * @retval false EC exchanged key generation failed. + * @retval false key_size is not large enough. + **/ +extern bool libspdm_ec_compute_key(void *ec_context, const uint8_t *peer_public, + size_t peer_public_size, uint8_t *key, + size_t *key_size); +#endif /* LIBSPDM_ECDHE_SUPPORT */ + +#if LIBSPDM_ECDSA_SUPPORT +/** + * Carries out the EC-DSA signature. + * + * This function carries out the EC-DSA signature. + * If the signature buffer is too small to hold the contents of signature, false + * is returned and sig_size is set to the required buffer size to obtain the signature. + * + * If ec_context is NULL, then return false. + * If message_hash is NULL, then return false. + * If hash_size need match the hash_nid. hash_nid could be SHA256, SHA384, SHA512, SHA3_256, + * SHA3_384, SHA3_512. + * If sig_size is large enough but signature is NULL, then return false. + * + * For P-256, the sig_size is 64. first 32-byte is R, second 32-byte is S. + * For P-384, the sig_size is 96. first 48-byte is R, second 48-byte is S. + * For P-521, the sig_size is 132. first 66-byte is R, second 66-byte is S. + * + * @param[in] ec_context Pointer to EC context for signature generation. + * @param[in] hash_nid hash NID + * @param[in] message_hash Pointer to octet message hash to be signed. + * @param[in] hash_size Size of the message hash in bytes. + * @param[out] signature Pointer to buffer to receive EC-DSA signature. + * @param[in, out] sig_size On input, the size of signature buffer in bytes. + * On output, the size of data returned in signature buffer in bytes. + * + * @retval true signature successfully generated in EC-DSA. + * @retval false signature generation failed. + * @retval false sig_size is too small. + **/ +extern bool libspdm_ecdsa_sign(void *ec_context, size_t hash_nid, + const uint8_t *message_hash, size_t hash_size, + uint8_t *signature, size_t *sig_size); + +/** + * Verifies the EC-DSA signature. + * + * If ec_context is NULL, then return false. + * If message_hash is NULL, then return false. + * If signature is NULL, then return false. + * If hash_size need match the hash_nid. hash_nid could be SHA256, SHA384, SHA512, SHA3_256, + * SHA3_384, SHA3_512. + * + * For P-256, the sig_size is 64. first 32-byte is R, second 32-byte is S. + * For P-384, the sig_size is 96. first 48-byte is R, second 48-byte is S. + * For P-521, the sig_size is 132. first 66-byte is R, second 66-byte is S. + * + * @param[in] ec_context Pointer to EC context for signature verification. + * @param[in] hash_nid hash NID + * @param[in] message_hash Pointer to octet message hash to be checked. + * @param[in] hash_size Size of the message hash in bytes. + * @param[in] signature Pointer to EC-DSA signature to be verified. + * @param[in] sig_size Size of signature in bytes. + * + * @retval true Valid signature encoded in EC-DSA. + * @retval false Invalid signature or invalid EC context. + **/ +extern bool libspdm_ecdsa_verify(void *ec_context, size_t hash_nid, + const uint8_t *message_hash, size_t hash_size, + const uint8_t *signature, size_t sig_size); +#endif /* LIBSPDM_ECDSA_SUPPORT */ +#endif /* CRYPTLIB_EC_H */ diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/libraries/libspdm/2.3.1/include/hal/library/cryptlib/cryptlib_ecd.h nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/libraries/libspdm/2.3.1/include/hal/library/cryptlib/cryptlib_ecd.h --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/libraries/libspdm/2.3.1/include/hal/library/cryptlib/cryptlib_ecd.h 1970-01-01 00:00:00.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/libraries/libspdm/2.3.1/include/hal/library/cryptlib/cryptlib_ecd.h 2024-03-05 22:14:11.000000000 +0000 @@ -0,0 +1,100 @@ +/** + * Copyright Notice: + * Copyright 2021-2022 DMTF. All rights reserved. + * License: BSD 3-Clause License. For full text see link: https://github.com/DMTF/libspdm/blob/main/LICENSE.md + **/ + +#ifndef CRYPTLIB_ECD_H +#define CRYPTLIB_ECD_H + +/*===================================================================================== + * Edwards-Curve Primitives + *=====================================================================================*/ + +#if (LIBSPDM_EDDSA_ED25519_SUPPORT) || (LIBSPDM_EDDSA_ED448_SUPPORT) +/** + * Allocates and Initializes one Edwards-Curve context for subsequent use with the NID. + * + * @param nid cipher NID + * + * @return Pointer to the Edwards-Curve context that has been initialized. + * If the allocations fails, libspdm_ecd_new_by_nid() returns NULL. + **/ +extern void *libspdm_ecd_new_by_nid(size_t nid); + +/** + * Release the specified Ed context. + * + * @param[in] ecd_context Pointer to the Ed context to be released. + **/ +extern void libspdm_ecd_free(void *ecd_context); + +/** + * Carries out the Ed-DSA signature. + * + * This function carries out the Ed-DSA signature. + * If the signature buffer is too small to hold the contents of signature, false + * is returned and sig_size is set to the required buffer size to obtain the signature. + * + * If ecd_context is NULL, then return false. + * If message is NULL, then return false. + * hash_nid must be NULL. + * If sig_size is large enough but signature is NULL, then return false. + * + * For ed25519, context must be NULL and context_size must be 0. + * For ed448, context must be maximum of 255 octets. + * + * For ed25519, the sig_size is 64. first 32-byte is R, second 32-byte is S. + * For ed448, the sig_size is 114. first 57-byte is R, second 57-byte is S. + * + * @param[in] ecd_context Pointer to Ed context for signature generation. + * @param[in] hash_nid hash NID + * @param[in] context The EDDSA signing context. + * @param[in] context_size Size of EDDSA signing context. + * @param[in] message Pointer to octet message to be signed (before hash). + * @param[in] size size of the message in bytes. + * @param[out] signature Pointer to buffer to receive Ed-DSA signature. + * @param[in, out] sig_size On input, the size of signature buffer in bytes. + * On output, the size of data returned in signature buffer in bytes. + * + * @retval true signature successfully generated in Ed-DSA. + * @retval false signature generation failed. + * @retval false sig_size is too small. + **/ +extern bool libspdm_eddsa_sign(const void *ecd_context, size_t hash_nid, + const uint8_t *context, size_t context_size, + const uint8_t *message, size_t size, uint8_t *signature, + size_t *sig_size); + +/** + * Verifies the Ed-DSA signature. + * + * If ecd_context is NULL, then return false. + * If message is NULL, then return false. + * If signature is NULL, then return false. + * hash_nid must be NULL. + * + * For ed25519, context must be NULL and context_size must be 0. + * For ed448, context must be maximum of 255 octets. + * + * For ed25519, the sig_size is 64. first 32-byte is R, second 32-byte is S. + * For ed448, the sig_size is 114. first 57-byte is R, second 57-byte is S. + * + * @param[in] ecd_context Pointer to Ed context for signature verification. + * @param[in] hash_nid hash NID + * @param[in] context The EDDSA signing context. + * @param[in] context_size Size of EDDSA signing context. + * @param[in] message Pointer to octet message to be checked (before hash). + * @param[in] size Size of the message in bytes. + * @param[in] signature Pointer to Ed-DSA signature to be verified. + * @param[in] sig_size Size of signature in bytes. + * + * @retval true Valid signature encoded in Ed-DSA. + * @retval false Invalid signature or invalid Ed context. + **/ +extern bool libspdm_eddsa_verify(const void *ecd_context, size_t hash_nid, + const uint8_t *context, size_t context_size, + const uint8_t *message, size_t size, + const uint8_t *signature, size_t sig_size); +#endif /* (LIBSPDM_EDDSA_ED25519_SUPPORT) || (LIBSPDM_EDDSA_ED448_SUPPORT) */ +#endif /* CRYPTLIB_ECD_H */ diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/libraries/libspdm/2.3.1/include/hal/library/cryptlib/cryptlib_hash.h nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/libraries/libspdm/2.3.1/include/hal/library/cryptlib/cryptlib_hash.h --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/libraries/libspdm/2.3.1/include/hal/library/cryptlib/cryptlib_hash.h 1970-01-01 00:00:00.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/libraries/libspdm/2.3.1/include/hal/library/cryptlib/cryptlib_hash.h 2024-03-05 22:14:11.000000000 +0000 @@ -0,0 +1,772 @@ +/** + * Copyright Notice: + * Copyright 2021-2022 DMTF. All rights reserved. + * License: BSD 3-Clause License. For full text see link: https://github.com/DMTF/libspdm/blob/main/LICENSE.md + **/ + +#ifndef CRYPTLIB_HASH_H +#define CRYPTLIB_HASH_H + +/* SHA-256 digest size in bytes. */ +#define LIBSPDM_SHA256_DIGEST_SIZE 32 + +/* SHA-384 digest size in bytes. */ +#define LIBSPDM_SHA384_DIGEST_SIZE 48 + +/* SHA-512 digest size in bytes. */ +#define LIBSPDM_SHA512_DIGEST_SIZE 64 + +/* SHA3-256 digest size in bytes. */ +#define LIBSPDM_SHA3_256_DIGEST_SIZE 32 + +/* SHA3-384 digest size in bytes. */ +#define LIBSPDM_SHA3_384_DIGEST_SIZE 48 + +/* SHA3-512 digest size in bytes. */ +#define LIBSPDM_SHA3_512_DIGEST_SIZE 64 + +/* SM3_256 digest size in bytes. */ +#define LIBSPDM_SM3_256_DIGEST_SIZE 32 + +/*===================================================================================== + * One-way cryptographic hash SHA2 primitives. + *===================================================================================== + */ +#if LIBSPDM_SHA256_SUPPORT +/** + * Allocates and initializes one HASH_CTX context for subsequent SHA-256 use. + * + * @return Pointer to the HASH_CTX context that has been initialized. + * If the allocations fails, sha256_new() returns NULL. * + **/ +extern void *libspdm_sha256_new(void); + +/** + * Release the specified HASH_CTX context. + * + * @param[in] sha256_context Pointer to the HASH_CTX context to be released. + **/ +extern void libspdm_sha256_free(void *sha256_context); + +/** + * Initializes user-supplied memory pointed to by sha256_context as SHA-256 hash context for + * subsequent use. + * + * If sha256_context is NULL, then return false. + * + * @param[out] sha256_context Pointer to SHA-256 context being initialized. + * + * @retval true SHA-256 context initialization succeeded. + * @retval false SHA-256 context initialization failed. + **/ +extern bool libspdm_sha256_init(void *sha256_context); + +/** + * Makes a copy of an existing SHA-256 context. + * + * If sha256_context is NULL, then return false. + * If new_sha256_context is NULL, then return false. + * If this interface is not supported, then return false. + * + * @param[in] sha256_context Pointer to SHA-256 context being copied. + * @param[out] new_sha256_context Pointer to new SHA-256 context. + * + * @retval true SHA-256 context copy succeeded. + * @retval false SHA-256 context copy failed. + * @retval false This interface is not supported. + **/ +extern bool libspdm_sha256_duplicate(const void *sha256_context, void *new_sha256_context); + +/** + * Digests the input data and updates SHA-256 context. + * + * This function performs SHA-256 digest on a data buffer of the specified size. + * It can be called multiple times to compute the digest of long or discontinuous data streams. + * SHA-256 context should be already correctly initialized by libspdm_sha256_init(), and must not + * have been finalized by libspdm_sha256_final(). Behavior with invalid context is undefined. + * + * If sha256_context is NULL, then return false. + * + * @param[in, out] sha256_context Pointer to the SHA-256 context. + * @param[in] data Pointer to the buffer containing the data to be hashed. + * @param[in] data_size Size of data buffer in bytes. + * + * @retval true SHA-256 data digest succeeded. + * @retval false SHA-256 data digest failed. + **/ +extern bool libspdm_sha256_update(void *sha256_context, const void *data, size_t data_size); + +/** + * Completes computation of the SHA-256 digest value. + * + * This function completes SHA-256 hash computation and populates the digest value into + * the specified memory. After this function has been called, the SHA-256 context cannot + * be used again. SHA-256 context should be already correctly initialized by libspdm_sha256_init(), + * and must not have been finalized by libspdm_sha256_final(). Behavior with invalid SHA-256 context + * is undefined. + * + * If sha256_context is NULL, then return false. + * If hash_value is NULL, then return false. + * + * @param[in, out] sha256_context Pointer to the SHA-256 context. + * @param[out] hash_value Pointer to a buffer that receives the SHA-256 digest + * value (32 bytes). + * + * @retval true SHA-256 digest computation succeeded. + * @retval false SHA-256 digest computation failed. + **/ +extern bool libspdm_sha256_final(void *sha256_context, uint8_t *hash_value); + +/** + * Computes the SHA-256 message digest of an input data buffer. + * + * This function performs the SHA-256 message digest of a given data buffer, and places + * the digest value into the specified memory. + * + * If this interface is not supported, then return false. + * + * @param[in] data Pointer to the buffer containing the data to be hashed. + * @param[in] data_size Size of data buffer in bytes. + * @param[out] hash_value Pointer to a buffer that receives the SHA-256 digest value (32 bytes). + * + * @retval true SHA-256 digest computation succeeded. + * @retval false SHA-256 digest computation failed. + * @retval false This interface is not supported. + **/ +extern bool libspdm_sha256_hash_all(const void *data, size_t data_size, uint8_t *hash_value); +#endif /* LIBSPDM_SHA256_SUPPORT */ + +#if LIBSPDM_SHA384_SUPPORT +/** + * Allocates and initializes one HASH_CTX context for subsequent SHA-384 use. + * + * @return Pointer to the HASH_CTX context that has been initialized. + * If the allocations fails, libspdm_sha384_new() returns NULL. + **/ +extern void *libspdm_sha384_new(void); + +/** + * Release the specified HASH_CTX context. + * + * @param[in] sha384_context Pointer to the HASH_CTX context to be released. + **/ +extern void libspdm_sha384_free(void *sha384_context); + +/** + * Initializes user-supplied memory pointed to by sha384_context as SHA-384 hash context for + * subsequent use. + * + * If sha384_context is NULL, then return false. + * + * @param[out] sha384_context Pointer to SHA-384 context being initialized. + * + * @retval true SHA-384 context initialization succeeded. + * @retval false SHA-384 context initialization failed. + **/ +extern bool libspdm_sha384_init(void *sha384_context); + +/** + * Makes a copy of an existing SHA-384 context. + * + * If sha384_context is NULL, then return false. + * If new_sha384_context is NULL, then return false. + * If this interface is not supported, then return false. + * + * @param[in] sha384_context Pointer to SHA-384 context being copied. + * @param[out] new_sha384_context Pointer to new SHA-384 context. + * + * @retval true SHA-384 context copy succeeded. + * @retval false SHA-384 context copy failed. + * @retval false This interface is not supported. + **/ +extern bool libspdm_sha384_duplicate(const void *sha384_context, void *new_sha384_context); + +/** + * Digests the input data and updates SHA-384 context. + * + * This function performs SHA-384 digest on a data buffer of the specified size. + * It can be called multiple times to compute the digest of long or discontinuous data streams. + * SHA-384 context should be already correctly initialized by libspdm_sha384_init(), and must not + * have been finalized by libspdm_sha384_final(). Behavior with invalid context is undefined. + * + * If sha384_context is NULL, then return false. + * + * @param[in, out] sha384_context Pointer to the SHA-384 context. + * @param[in] data Pointer to the buffer containing the data to be hashed. + * @param[in] data_size Size of data buffer in bytes. + * + * @retval true SHA-384 data digest succeeded. + * @retval false SHA-384 data digest failed. + **/ +extern bool libspdm_sha384_update(void *sha384_context, const void *data, size_t data_size); + +/** + * Completes computation of the SHA-384 digest value. + * + * This function completes SHA-384 hash computation and populates the digest value into + * the specified memory. After this function has been called, the SHA-384 context cannot + * be used again. SHA-384 context should be already correctly initialized by libspdm_sha384_init(), + * and must not have been finalized by libspdm_sha384_final(). Behavior with invalid SHA-384 context + * is undefined. + * + * If sha384_context is NULL, then return false. + * If hash_value is NULL, then return false. + * + * @param[in, out] sha384_context Pointer to the SHA-384 context. + * @param[out] hash_value Pointer to a buffer that receives the SHA-384 digest + * value (48 bytes). + * + * @retval true SHA-384 digest computation succeeded. + * @retval false SHA-384 digest computation failed. + **/ +extern bool libspdm_sha384_final(void *sha384_context, uint8_t *hash_value); + +/** + * Computes the SHA-384 message digest of an input data buffer. + * + * This function performs the SHA-384 message digest of a given data buffer, and places + * the digest value into the specified memory. + * + * If this interface is not supported, then return false. + * + * @param[in] data Pointer to the buffer containing the data to be hashed. + * @param[in] data_size Size of data buffer in bytes. + * @param[out] hash_value Pointer to a buffer that receives the SHA-384 digest value (48 bytes). + * + * @retval true SHA-384 digest computation succeeded. + * @retval false SHA-384 digest computation failed. + * @retval false This interface is not supported. + **/ +extern bool libspdm_sha384_hash_all(const void *data, size_t data_size, uint8_t *hash_value); +#endif /* LIBSPDM_SHA384_SUPPORT */ + +#if LIBSPDM_SHA512_SUPPORT +/** + * Allocates and initializes one HASH_CTX context for subsequent SHA-512 use. + * + * @return Pointer to the HASH_CTX context that has been initialized. + * If the allocations fails, libspdm_sha512_new() returns NULL. + **/ +extern void *libspdm_sha512_new(void); + +/** + * Release the specified HASH_CTX context. + * + * @param[in] sha512_context Pointer to the HASH_CTX context to be released. + **/ +extern void libspdm_sha512_free(void *sha512_context); + +/** + * Initializes user-supplied memory pointed by sha512_context as SHA-512 hash context for + * subsequent use. + * + * If sha512_context is NULL, then return false. + * + * @param[out] sha512_context Pointer to SHA-512 context being initialized. + * + * @retval true SHA-512 context initialization succeeded. + * @retval false SHA-512 context initialization failed. + **/ +extern bool libspdm_sha512_init(void *sha512_context); + +/** + * Makes a copy of an existing SHA-512 context. + * + * If sha512_context is NULL, then return false. + * If new_sha512_context is NULL, then return false. + * If this interface is not supported, then return false. + * + * @param[in] sha512_context Pointer to SHA-512 context being copied. + * @param[out] new_sha512_context Pointer to new SHA-512 context. + * + * @retval true SHA-512 context copy succeeded. + * @retval false SHA-512 context copy failed. + * @retval false This interface is not supported. + **/ +extern bool libspdm_sha512_duplicate(const void *sha512_context, void *new_sha512_context); + +/** + * Digests the input data and updates SHA-512 context. + * + * This function performs SHA-512 digest on a data buffer of the specified size. + * It can be called multiple times to compute the digest of long or discontinuous data streams. + * SHA-512 context should be already correctly initialized by libspdm_sha512_init(), and must not + * have been finalized by libspdm_sha512_final(). Behavior with invalid context is undefined. + * + * If sha512_context is NULL, then return false. + * + * @param[in, out] sha512_context Pointer to the SHA-512 context. + * @param[in] data Pointer to the buffer containing the data to be hashed. + * @param[in] data_size Size of data buffer in bytes. + * + * @retval true SHA-512 data digest succeeded. + * @retval false SHA-512 data digest failed. + **/ +extern bool libspdm_sha512_update(void *sha512_context, const void *data, size_t data_size); + +/** + * Completes computation of the SHA-512 digest value. + * + * This function completes SHA-512 hash computation and populates the digest value into + * the specified memory. After this function has been called, the SHA-512 context cannot + * be used again. SHA-512 context should be already correctly initialized by libspdm_sha512_init(), + * and must not have been finalized by libspdm_sha512_final(). Behavior with invalid SHA-512 context + * is undefined. + * + * If sha512_context is NULL, then return false. + * If hash_value is NULL, then return false. + * + * @param[in, out] sha512_context Pointer to the SHA-512 context. + * @param[out] hash_value Pointer to a buffer that receives the SHA-512 digest + * value (64 bytes). + * + * @retval true SHA-512 digest computation succeeded. + * @retval false SHA-512 digest computation failed. + **/ +extern bool libspdm_sha512_final(void *sha512_context, uint8_t *hash_value); + +/** + * Computes the SHA-512 message digest of an input data buffer. + * + * This function performs the SHA-512 message digest of a given data buffer, and places + * the digest value into the specified memory. + * + * If this interface is not supported, then return false. + * + * @param[in] data Pointer to the buffer containing the data to be hashed. + * @param[in] data_size Size of data buffer in bytes. + * @param[out] hash_value Pointer to a buffer that receives the SHA-512 digest value (64 bytes). + * + * @retval true SHA-512 digest computation succeeded. + * @retval false SHA-512 digest computation failed. + * @retval false This interface is not supported. + **/ +extern bool libspdm_sha512_hash_all(const void *data, size_t data_size, uint8_t *hash_value); +#endif /* LIBSPDM_SHA512_SUPPORT */ + +/*===================================================================================== + * One-way cryptographic hash SHA3 primitives. + *===================================================================================== + */ +#if LIBSPDM_SHA3_256_SUPPORT +/** + * Allocates and initializes one HASH_CTX context for subsequent SHA3-256 use. + * + * @return Pointer to the HASH_CTX context that has been initialized. + * If the allocations fails, libspdm_sha3_256_new() returns NULL. + **/ +extern void *libspdm_sha3_256_new(void); + +/** + * Release the specified HASH_CTX context. + * + * @param[in] sha3_256_context Pointer to the HASH_CTX context to be released. + **/ +extern void libspdm_sha3_256_free(void *sha3_256_context); + +/** + * Initializes user-supplied memory pointed by sha3_256_context as SHA3-256 hash context for + * subsequent use. + * + * If sha3_256_context is NULL, then return false. + * + * @param[out] sha3_256_context Pointer to SHA3-256 context being initialized. + * + * @retval true SHA3-256 context initialization succeeded. + * @retval false SHA3-256 context initialization failed. + **/ +extern bool libspdm_sha3_256_init(void *sha3_256_context); + +/** + * Makes a copy of an existing SHA3-256 context. + * + * If sha3_256_context is NULL, then return false. + * If new_sha3_256_context is NULL, then return false. + * If this interface is not supported, then return false. + * + * @param[in] sha3_256_context Pointer to SHA3-256 context being copied. + * @param[out] new_sha3_256_context Pointer to new SHA3-256 context. + * + * @retval true SHA3-256 context copy succeeded. + * @retval false SHA3-256 context copy failed. + * @retval false This interface is not supported. + **/ +extern bool libspdm_sha3_256_duplicate(const void *sha3_256_context, void *new_sha3_256_context); + +/** + * Digests the input data and updates SHA3-256 context. + * + * This function performs SHA3-256 digest on a data buffer of the specified size. + * It can be called multiple times to compute the digest of long or discontinuous data streams. + * SHA3-256 context should be already correctly initialized by libspdm_sha3_256_init(), and must not + * have been finalized by libspdm_sha3_256_final(). Behavior with invalid context is undefined. + * + * If sha3_256_context is NULL, then return false. + * + * @param[in, out] sha3_256_context Pointer to the SHA3-256 context. + * @param[in] data Pointer to the buffer containing the data to be hashed. + * @param[in] data_size size of data buffer in bytes. + * + * @retval true SHA3-256 data digest succeeded. + * @retval false SHA3-256 data digest failed. + **/ +extern bool libspdm_sha3_256_update(void *sha3_256_context, const void *data, size_t data_size); + +/** + * Completes computation of the SHA3-256 digest value. + * + * This function completes SHA3-256 hash computation and populates the digest value into + * the specified memory. After this function has been called, the SHA3-512 context cannot + * be used again. SHA3-256 context should be already correctly initialized by + * libspdm_sha3_256_init(), and must not have been finalized by libspdm_sha3_256_final(). + * Behavior with invalid SHA3-256 context is undefined. + * + * If sha3_256_context is NULL, then return false. + * If hash_value is NULL, then return false. + * + * @param[in, out] sha3_256_context Pointer to the SHA3-256 context. + * @param[out] hash_value Pointer to a buffer that receives the SHA3-256 digest + * value (32 bytes). + * + * @retval true SHA3-256 digest computation succeeded. + * @retval false SHA3-256 digest computation failed. + **/ +extern bool libspdm_sha3_256_final(void *sha3_256_context, uint8_t *hash_value); + +/** + * Computes the SHA3-256 message digest of an input data buffer. + * + * This function performs the SHA3-256 message digest of a given data buffer, and places + * the digest value into the specified memory. + * + * If this interface is not supported, then return false. + * + * @param[in] data Pointer to the buffer containing the data to be hashed. + * @param[in] data_size Size of data buffer in bytes. + * @param[out] hash_value Pointer to a buffer that receives the SHA3-256 digest value (32 bytes). + * + * @retval true SHA3-256 digest computation succeeded. + * @retval false SHA3-256 digest computation failed. + * @retval false This interface is not supported. + **/ +extern bool libspdm_sha3_256_hash_all(const void *data, size_t data_size, uint8_t *hash_value); +#endif /* LIBSPDM_SHA3_256_SUPPORT */ + +#if LIBSPDM_SHA3_384_SUPPORT +/** + * Allocates and initializes one HASH_CTX context for subsequent SHA3-384 use. + * + * @return Pointer to the HASH_CTX context that has been initialized. + * If the allocations fails, libspdm_sha3_384_new() returns NULL. + **/ +extern void *libspdm_sha3_384_new(void); + +/** + * Release the specified HASH_CTX context. + * + * @param[in] sha3_384_context Pointer to the HASH_CTX context to be released. + **/ +extern void libspdm_sha3_384_free(void *sha3_384_context); + +/** + * Initializes user-supplied memory pointed by sha3_384_context as SHA3-384 hash context for + * subsequent use. + * + * If sha3_384_context is NULL, then return false. + * + * @param[out] sha3_384_context Pointer to SHA3-384 context being initialized. + * + * @retval true SHA3-384 context initialization succeeded. + * @retval false SHA3-384 context initialization failed. + **/ +extern bool libspdm_sha3_384_init(void *sha3_384_context); + +/** + * Makes a copy of an existing SHA3-384 context. + * + * If sha3_384_context is NULL, then return false. + * If new_sha3_384_context is NULL, then return false. + * If this interface is not supported, then return false. + * + * @param[in] sha3_384_context Pointer to SHA3-384 context being copied. + * @param[out] new_sha3_384_context Pointer to new SHA3-384 context. + * + * @retval true SHA3-384 context copy succeeded. + * @retval false SHA3-384 context copy failed. + * @retval false This interface is not supported. + **/ +extern bool libspdm_sha3_384_duplicate(const void *sha3_384_context, void *new_sha3_384_context); + +/** + * Digests the input data and updates SHA3-384 context. + * + * This function performs SHA3-384 digest on a data buffer of the specified size. + * It can be called multiple times to compute the digest of long or discontinuous data streams. + * SHA3-384 context should be already correctly initialized by libspdm_sha3_384_init(), and must not + * have been finalized by libspdm_sha3_384_final(). Behavior with invalid context is undefined. + * + * If sha3_384_context is NULL, then return false. + * + * @param[in, out] sha3_384_context Pointer to the SHA3-384 context. + * @param[in] data Pointer to the buffer containing the data to be hashed. + * @param[in] data_size Size of data buffer in bytes. + * + * @retval true SHA3-384 data digest succeeded. + * @retval false SHA3-384 data digest failed. + **/ +extern bool libspdm_sha3_384_update(void *sha3_384_context, const void *data, size_t data_size); + +/** + * Completes computation of the SHA3-384 digest value. + * + * This function completes SHA3-384 hash computation and populates the digest value into + * the specified memory. After this function has been called, the SHA3-384 context cannot + * be used again. SHA3-384 context should be already correctly initialized by + * libspdm_sha3_384_init(), and must not have been finalized by libspdm_sha3_384_final(). + * Behavior with invalid SHA3-384 context is undefined. + * + * If sha3_384_context is NULL, then return false. + * If hash_value is NULL, then return false. + * + * @param[in, out] sha3_384_context Pointer to the SHA3-384 context. + * @param[out] hash_value Pointer to a buffer that receives the SHA3-384 digest + * value (48 bytes). + * + * @retval true SHA3-384 digest computation succeeded. + * @retval false SHA3-384 digest computation failed. + * + **/ +extern bool libspdm_sha3_384_final(void *sha3_384_context, uint8_t *hash_value); + +/** + * Computes the SHA3-384 message digest of an input data buffer. + * + * This function performs the SHA3-384 message digest of a given data buffer, and places + * the digest value into the specified memory. + * + * If this interface is not supported, then return false. + * + * @param[in] data Pointer to the buffer containing the data to be hashed. + * @param[in] data_size Size of data buffer in bytes. + * @param[out] hash_value Pointer to a buffer that receives the SHA3-384 digest value (48 bytes). + * + * @retval true SHA3-384 digest computation succeeded. + * @retval false SHA3-384 digest computation failed. + * @retval false This interface is not supported. + **/ +extern bool libspdm_sha3_384_hash_all(const void *data, size_t data_size, uint8_t *hash_value); +#endif /* LIBSPDM_SHA3_384_SUPPORT */ + +#if LIBSPDM_SHA3_512_SUPPORT +/** + * Allocates and initializes one HASH_CTX context for subsequent SHA3-512 use. + * + * @return Pointer to the HASH_CTX context that has been initialized. + * If the allocations fails, libspdm_sha3_512_new() returns NULL. + **/ +extern void *libspdm_sha3_512_new(void); + +/** + * Release the specified HASH_CTX context. + * + * @param[in] sha3_512_context Pointer to the HASH_CTX context to be released. + **/ +extern void libspdm_sha3_512_free(void *sha3_512_context); + +/** + * Initializes user-supplied memory pointed by sha3_512_context as SHA3-512 hash context for + * subsequent use. + * + * If sha3_512_context is NULL, then return false. + * + * @param[out] sha3_512_context Pointer to SHA3-512 context being initialized. + * + * @retval true SHA3-512 context initialization succeeded. + * @retval false SHA3-512 context initialization failed. + **/ +extern bool libspdm_sha3_512_init(void *sha3_512_context); + +/** + * Makes a copy of an existing SHA3-512 context. + * + * If sha3_512_context is NULL, then return false. + * If new_sha3_512_context is NULL, then return false. + * If this interface is not supported, then return false. + * + * @param[in] sha3_512_context Pointer to SHA3-512 context being copied. + * @param[out] new_sha3_512_context Pointer to new SHA3-512 context. + * + * @retval true SHA3-512 context copy succeeded. + * @retval false SHA3-512 context copy failed. + * @retval false This interface is not supported. + * + **/ +extern bool libspdm_sha3_512_duplicate(const void *sha3_512_context, void *new_sha3_512_context); + +/** + * Digests the input data and updates SHA3-512 context. + * + * This function performs SHA3-512 digest on a data buffer of the specified size. + * It can be called multiple times to compute the digest of long or discontinuous data streams. + * SHA3-512 context should be already correctly initialized by libspdm_sha3_512_init(), and must not + * have been finalized by libspdm_sha3_512_final(). Behavior with invalid context is undefined. + * + * If sha3_512_context is NULL, then return false. + * + * @param[in, out] sha3_512_context Pointer to the SHA3-512 context. + * @param[in] data Pointer to the buffer containing the data to be hashed. + * @param[in] data_size Size of data buffer in bytes. + * + * @retval true SHA3-512 data digest succeeded. + * @retval false SHA3-512 data digest failed. + **/ +extern bool libspdm_sha3_512_update(void *sha3_512_context, const void *data, size_t data_size); + +/** + * Completes computation of the SHA3-512 digest value. + * + * This function completes SHA3-512 hash computation and populates the digest value into + * the specified memory. After this function has been called, the SHA3-512 context cannot + * be used again. SHA3-512 context should be already correctly initialized by + * libspdm_sha3_512_init(), and must not have been finalized by libspdm_sha3_512_final(). + * Behavior with invalid SHA3-512 context is undefined. + * + * If sha3_512_context is NULL, then return false. + * If hash_value is NULL, then return false. + * + * @param[in, out] sha3_512_context Pointer to the SHA3-512 context. + * @param[out] hash_value Pointer to a buffer that receives the SHA3-512 digest + * value (64 bytes). + * + * @retval true SHA3-512 digest computation succeeded. + * @retval false SHA3-512 digest computation failed. + **/ +extern bool libspdm_sha3_512_final(void *sha3_512_context, uint8_t *hash_value); + +/** + * Computes the SHA3-512 message digest of an input data buffer. + * + * This function performs the SHA3-512 message digest of a given data buffer, and places + * the digest value into the specified memory. + * + * If this interface is not supported, then return false. + * + * @param[in] data Pointer to the buffer containing the data to be hashed. + * @param[in] data_size Size of data buffer in bytes. + * @param[out] hash_value Pointer to a buffer that receives the SHA3-512 digest value (64 bytes). + * + * @retval true SHA3-512 digest computation succeeded. + * @retval false SHA3-512 digest computation failed. + * @retval false This interface is not supported. + **/ +extern bool libspdm_sha3_512_hash_all(const void *data, size_t data_size, uint8_t *hash_value); +#endif /* LIBSPDM_SHA3_512_SUPPORT */ + +/*===================================================================================== + * One-Way Cryptographic hash SM3 Primitives + *===================================================================================== + */ + +#if LIBSPDM_SM3_256_SUPPORT +/** + * Allocates and initializes one HASH_CTX context for subsequent SM3-256 use. + * + * @return Pointer to the HASH_CTX context that has been initialized. + * If the allocations fails, libspdm_sm3_256_new() returns NULL. + **/ +extern void *libspdm_sm3_256_new(void); + +/** + * Release the specified HASH_CTX context. + * + * @param[in] sm3_context Pointer to the HASH_CTX context to be released. + **/ +extern void libspdm_sm3_256_free(void *sm3_context); + +/** + * Initializes user-supplied memory pointed by sm3_context as SM3 hash context for + * subsequent use. + * + * If sm3_context is NULL, then return false. + * + * @param[out] sm3_context Pointer to SM3 context being initialized. + * + * @retval true SM3 context initialization succeeded. + * @retval false SM3 context initialization failed. + **/ +extern bool libspdm_sm3_256_init(void *sm3_context); + +/** + * Makes a copy of an existing SM3 context. + * + * If sm3_context is NULL, then return false. + * If new_sm3_context is NULL, then return false. + * If this interface is not supported, then return false. + * + * @param[in] sm3_context Pointer to SM3 context being copied. + * @param[out] new_sm3_context Pointer to new SM3 context. + * + * @retval true SM3 context copy succeeded. + * @retval false SM3 context copy failed. + * @retval false This interface is not supported. + **/ +extern bool libspdm_sm3_256_duplicate(const void *sm3_context, void *new_sm3_context); + +/** + * Digests the input data and updates SM3 context. + * + * This function performs SM3 digest on a data buffer of the specified size. + * It can be called multiple times to compute the digest of long or discontinuous data streams. + * SM3 context should be already correctly initialized by sm3_init(), and should not be finalized + * by sm3_final(). Behavior with invalid context is undefined. + * + * If sm3_context is NULL, then return false. + * + * @param[in, out] sm3_context Pointer to the SM3 context. + * @param[in] data Pointer to the buffer containing the data to be hashed. + * @param[in] data_size Size of data buffer in bytes. + * + * @retval true SM3 data digest succeeded. + * @retval false SM3 data digest failed. + **/ +extern bool libspdm_sm3_256_update(void *sm3_context, const void *data, size_t data_size); + +/** + * Completes computation of the SM3 digest value. + * + * This function completes SM3 hash computation and retrieves the digest value into + * the specified memory. After this function has been called, the SM3 context cannot + * be used again. SM3 context should be already correctly initialized by sm3_init(), and should not + * be finalized by sm3_final(). Behavior with invalid SM3 context is undefined. + * + * If sm3_context is NULL, then return false. + * If hash_value is NULL, then return false. + * + * @param[in, out] sm3_context Pointer to the SM3 context. + * @param[out] hash_value Pointer to a buffer that receives the SM3 digest value (32 bytes). + * + * @retval true SM3 digest computation succeeded. + * @retval false SM3 digest computation failed. + **/ +extern bool libspdm_sm3_256_final(void *sm3_context, uint8_t *hash_value); + +/** + * Computes the SM3 message digest of an input data buffer. + * + * This function performs the SM3 message digest of a given data buffer, and places + * the digest value into the specified memory. + * + * If this interface is not supported, then return false. + * + * @param[in] data Pointer to the buffer containing the data to be hashed. + * @param[in] data_size Size of data buffer in bytes. + * @param[out] hash_value Pointer to a buffer that receives the SM3 digest value (32 bytes). + * + * @retval true SM3 digest computation succeeded. + * @retval false SM3 digest computation failed. + * @retval false This interface is not supported. + **/ +extern bool libspdm_sm3_256_hash_all(const void *data, size_t data_size, uint8_t *hash_value); +#endif /* LIBSPDM_SM3_256_SUPPORT */ + +#endif /* CRYPTLIB_HASH_H */ diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/libraries/libspdm/2.3.1/include/hal/library/cryptlib/cryptlib_hkdf.h nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/libraries/libspdm/2.3.1/include/hal/library/cryptlib/cryptlib_hkdf.h --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/libraries/libspdm/2.3.1/include/hal/library/cryptlib/cryptlib_hkdf.h 1970-01-01 00:00:00.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/libraries/libspdm/2.3.1/include/hal/library/cryptlib/cryptlib_hkdf.h 2024-03-05 22:14:11.000000000 +0000 @@ -0,0 +1,266 @@ +/** + * Copyright Notice: + * Copyright 2021-2022 DMTF. All rights reserved. + * License: BSD 3-Clause License. For full text see link: https://github.com/DMTF/libspdm/blob/main/LICENSE.md + **/ + +#ifndef CRYPTLIB_HKDF_H +#define CRYPTLIB_HKDF_H + +/*===================================================================================== + * Key Derivation Function Primitives + *=====================================================================================*/ + +#if LIBSPDM_SHA256_SUPPORT +/** + * Derive SHA-256 HMAC-based Extract key Derivation Function (HKDF). + * + * @param[in] key Pointer to the user-supplied key. + * @param[in] key_size Key size in bytes. + * @param[in] salt Pointer to the salt value. + * @param[in] salt_size Salt size in bytes. + * @param[out] prk_out Pointer to buffer to receive prk value. + * @param[in] prk_out_size Size of prk bytes to generate. + * + * @retval true Hkdf generated successfully. + * @retval false Hkdf generation failed. + **/ +extern bool libspdm_hkdf_sha256_extract(const uint8_t *key, size_t key_size, + const uint8_t *salt, size_t salt_size, + uint8_t *prk_out, size_t prk_out_size); + +/** + * Derive SHA256 HMAC-based Expand key Derivation Function (HKDF). + * + * @param[in] prk Pointer to the user-supplied key. + * @param[in] prk_size Key size in bytes. + * @param[in] info Pointer to the application specific info. + * @param[in] info_size Info size in bytes. + * @param[out] out Pointer to buffer to receive hkdf value. + * @param[in] out_size Size of hkdf bytes to generate. + * + * @retval true Hkdf generated successfully. + * @retval false Hkdf generation failed. + **/ +extern bool libspdm_hkdf_sha256_expand(const uint8_t *prk, size_t prk_size, + const uint8_t *info, size_t info_size, + uint8_t *out, size_t out_size); +#endif /* LIBSPDM_SHA256_SUPPORT */ + +#if LIBSPDM_SHA384_SUPPORT +/** + * Derive SHA384 HMAC-based Extract key Derivation Function (HKDF). + * + * @param[in] key Pointer to the user-supplied key. + * @param[in] key_size Key size in bytes. + * @param[in] salt Pointer to the salt value. + * @param[in] salt_size Salt size in bytes. + * @param[out] prk_out Pointer to buffer to receive hkdf value. + * @param[in] prk_out_size Size of hkdf bytes to generate. + * + * @retval true Hkdf generated successfully. + * @retval false Hkdf generation failed. + **/ +extern bool libspdm_hkdf_sha384_extract(const uint8_t *key, size_t key_size, + const uint8_t *salt, size_t salt_size, + uint8_t *prk_out, size_t prk_out_size); + +/** + * Derive SHA384 HMAC-based Expand key Derivation Function (HKDF). + * + * @param[in] prk Pointer to the user-supplied key. + * @param[in] prk_size Key size in bytes. + * @param[in] info Pointer to the application specific info. + * @param[in] info_size Info size in bytes. + * @param[out] out Pointer to buffer to receive hkdf value. + * @param[in] out_size Size of hkdf bytes to generate. + * + * @retval true Hkdf generated successfully. + * @retval false Hkdf generation failed. + **/ +extern bool libspdm_hkdf_sha384_expand(const uint8_t *prk, size_t prk_size, + const uint8_t *info, size_t info_size, + uint8_t *out, size_t out_size); +#endif /* LIBSPDM_SHA384_SUPPORT */ + +#if LIBSPDM_SHA512_SUPPORT +/** + * Derive SHA512 HMAC-based Extract key Derivation Function (HKDF). + * + * @param[in] key Pointer to the user-supplied key. + * @param[in] key_size Key size in bytes. + * @param[in] salt Pointer to the salt value. + * @param[in] salt_size Salt size in bytes. + * @param[out] prk_out Pointer to buffer to receive hkdf value. + * @param[in] prk_out_size Size of hkdf bytes to generate. + * + * @retval true Hkdf generated successfully. + * @retval false Hkdf generation failed. + **/ +extern bool libspdm_hkdf_sha512_extract(const uint8_t *key, size_t key_size, + const uint8_t *salt, size_t salt_size, + uint8_t *prk_out, size_t prk_out_size); + +/** + * Derive SHA512 HMAC-based Expand key Derivation Function (HKDF). + * + * @param[in] prk Pointer to the user-supplied key. + * @param[in] prk_size Key size in bytes. + * @param[in] info Pointer to the application specific info. + * @param[in] info_size Info size in bytes. + * @param[out] out Pointer to buffer to receive hkdf value. + * @param[in] out_size Size of hkdf bytes to generate. + * + * @retval true Hkdf generated successfully. + * @retval false Hkdf generation failed. + **/ +extern bool libspdm_hkdf_sha512_expand(const uint8_t *prk, size_t prk_size, + const uint8_t *info, size_t info_size, + uint8_t *out, size_t out_size); +#endif /* LIBSPDM_SHA512_SUPPORT */ + +#if LIBSPDM_SHA3_256_SUPPORT +/** + * Derive SHA3_256 HMAC-based Extract key Derivation Function (HKDF). + * + * @param[in] key Pointer to the user-supplied key. + * @param[in] key_size Key size in bytes. + * @param[in] salt Pointer to the salt value. + * @param[in] salt_size Salt size in bytes. + * @param[out] prk_out Pointer to buffer to receive hkdf value. + * @param[in] prk_out_size Size of hkdf bytes to generate. + * + * @retval true Hkdf generated successfully. + * @retval false Hkdf generation failed. + **/ +extern bool libspdm_hkdf_sha3_256_extract(const uint8_t *key, size_t key_size, + const uint8_t *salt, size_t salt_size, + uint8_t *prk_out, size_t prk_out_size); + +/** + * Derive SHA3_256 HMAC-based Expand key Derivation Function (HKDF). + * + * @param[in] prk Pointer to the user-supplied key. + * @param[in] prk_size Key size in bytes. + * @param[in] info Pointer to the application specific info. + * @param[in] info_size Info size in bytes. + * @param[out] out Pointer to buffer to receive hkdf value. + * @param[in] out_size Size of hkdf bytes to generate. + * + * @retval true Hkdf generated successfully. + * @retval false Hkdf generation failed. + **/ +extern bool libspdm_hkdf_sha3_256_expand(const uint8_t *prk, size_t prk_size, + const uint8_t *info, size_t info_size, + uint8_t *out, size_t out_size); +#endif /* LIBSPDM_SHA3_256_SUPPORT */ + +#if LIBSPDM_SHA3_384_SUPPORT +/** + * Derive SHA3_384 HMAC-based Extract key Derivation Function (HKDF). + * + * @param[in] key Pointer to the user-supplied key. + * @param[in] key_size Key size in bytes. + * @param[in] salt Pointer to the salt value. + * @param[in] salt_size Salt size in bytes. + * @param[out] prk_out Pointer to buffer to receive hkdf value. + * @param[in] prk_out_size Size of hkdf bytes to generate. + * + * @retval true Hkdf generated successfully. + * @retval false Hkdf generation failed. + **/ +extern bool libspdm_hkdf_sha3_384_extract(const uint8_t *key, size_t key_size, + const uint8_t *salt, size_t salt_size, + uint8_t *prk_out, size_t prk_out_size); + +/** + * Derive SHA3_384 HMAC-based Expand key Derivation Function (HKDF). + * + * @param[in] prk Pointer to the user-supplied key. + * @param[in] prk_size Key size in bytes. + * @param[in] info Pointer to the application specific info. + * @param[in] info_size Info size in bytes. + * @param[out] out Pointer to buffer to receive hkdf value. + * @param[in] out_size Size of hkdf bytes to generate. + * + * @retval true Hkdf generated successfully. + * @retval false Hkdf generation failed. + **/ +extern bool libspdm_hkdf_sha3_384_expand(const uint8_t *prk, size_t prk_size, + const uint8_t *info, size_t info_size, + uint8_t *out, size_t out_size); +#endif /* LIBSPDM_SHA3_384_SUPPORT */ + +#if LIBSPDM_SHA3_512_SUPPORT +/** + * Derive SHA3_512 HMAC-based Extract key Derivation Function (HKDF). + * + * @param[in] key Pointer to the user-supplied key. + * @param[in] key_size Key size in bytes. + * @param[in] salt Pointer to the salt value. + * @param[in] salt_size Salt size in bytes. + * @param[out] prk_out Pointer to buffer to receive hkdf value. + * @param[in] prk_out_size Size of hkdf bytes to generate. + * + * @retval true Hkdf generated successfully. + * @retval false Hkdf generation failed. + **/ +extern bool libspdm_hkdf_sha3_512_extract(const uint8_t *key, size_t key_size, + const uint8_t *salt, size_t salt_size, + uint8_t *prk_out, size_t prk_out_size); + +/** + * Derive SHA3_512 HMAC-based Expand key Derivation Function (HKDF). + * + * @param[in] prk Pointer to the user-supplied key. + * @param[in] prk_size Key size in bytes. + * @param[in] info Pointer to the application specific info. + * @param[in] info_size Info size in bytes. + * @param[out] out Pointer to buffer to receive hkdf value. + * @param[in] out_size Size of hkdf bytes to generate. + * + * @retval true Hkdf generated successfully. + * @retval false Hkdf generation failed. + **/ +extern bool libspdm_hkdf_sha3_512_expand(const uint8_t *prk, size_t prk_size, + const uint8_t *info, size_t info_size, + uint8_t *out, size_t out_size); +#endif /* LIBSPDM_SHA3_512_SUPPORT */ + +#if LIBSPDM_SM3_256_SUPPORT +/** + * Derive SM3_256 HMAC-based Extract key Derivation Function (HKDF). + * + * @param[in] key Pointer to the user-supplied key. + * @param[in] key_size Key size in bytes. + * @param[in] salt Pointer to the salt value. + * @param[in] salt_size Salt size in bytes. + * @param[out] prk_out Pointer to buffer to receive hkdf value. + * @param[in] prk_out_size Size of hkdf bytes to generate. + * + * @retval true Hkdf generated successfully. + * @retval false Hkdf generation failed. + **/ +extern bool libspdm_hkdf_sm3_256_extract(const uint8_t *key, size_t key_size, + const uint8_t *salt, size_t salt_size, + uint8_t *prk_out, size_t prk_out_size); + +/** + * Derive SM3_256 HMAC-based Expand key Derivation Function (HKDF). + * + * @param[in] prk Pointer to the user-supplied key. + * @param[in] prk_size Key size in bytes. + * @param[in] info Pointer to the application specific info. + * @param[in] info_size Info size in bytes. + * @param[out] out Pointer to buffer to receive hkdf value. + * @param[in] out_size Size of hkdf bytes to generate. + * + * @retval true Hkdf generated successfully. + * @retval false Hkdf generation failed. + **/ +extern bool libspdm_hkdf_sm3_256_expand(const uint8_t *prk, size_t prk_size, + const uint8_t *info, size_t info_size, + uint8_t *out, size_t out_size); +#endif /* LIBSPDM_SM3_256_SUPPORT */ + +#endif /* CRYPTLIB_HKDF_H */ diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/libraries/libspdm/2.3.1/include/hal/library/cryptlib/cryptlib_mac.h nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/libraries/libspdm/2.3.1/include/hal/library/cryptlib/cryptlib_mac.h --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/libraries/libspdm/2.3.1/include/hal/library/cryptlib/cryptlib_mac.h 1970-01-01 00:00:00.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/libraries/libspdm/2.3.1/include/hal/library/cryptlib/cryptlib_mac.h 2024-03-05 22:14:11.000000000 +0000 @@ -0,0 +1,833 @@ +/** + * Copyright Notice: + * Copyright 2021-2022 DMTF. All rights reserved. + * License: BSD 3-Clause License. For full text see link: https://github.com/DMTF/libspdm/blob/main/LICENSE.md + **/ + +#ifndef CRYPTLIB_MAC_H +#define CRYPTLIB_MAC_H + +/*===================================================================================== + * Message Authentication Code (MAC) Primitives + *===================================================================================== + */ + +#if LIBSPDM_SHA256_SUPPORT +/** + * Allocates and initializes one HMAC_CTX context for subsequent HMAC-SHA256 use. + * + * @return Pointer to the HMAC_CTX context that has been initialized. + * If the allocations fails, libspdm_hmac_sha256_new() returns NULL. + **/ +extern void *libspdm_hmac_sha256_new(void); + +/** + * Release the specified HMAC_CTX context. + * + * @param[in] hmac_sha256_ctx Pointer to the HMAC_CTX context to be released. + **/ +extern void libspdm_hmac_sha256_free(void *hmac_sha256_ctx); + +/** + * Set user-supplied key for subsequent use. It must be done before any + * calling to libspdm_hmac_sha256_update(). + * + * If hmac_sha256_ctx is NULL, then return false. + * If this interface is not supported, then return false. + * + * @param[out] hmac_sha256_ctx Pointer to HMAC-SHA256 context. + * @param[in] key Pointer to the user-supplied key. + * @param[in] key_size Key size in bytes. + * + * @retval true The key is set successfully. + * @retval false The key is set unsuccessfully. + * @retval false This interface is not supported. + **/ +extern bool libspdm_hmac_sha256_set_key(void *hmac_sha256_ctx, const uint8_t *key, size_t key_size); + +/** + * Makes a copy of an existing HMAC-SHA256 context. + * + * If hmac_sha256_ctx is NULL, then return false. + * If new_hmac_sha256_ctx is NULL, then return false. + * If this interface is not supported, then return false. + * + * @param[in] hmac_sha256_ctx Pointer to HMAC-SHA256 context being copied. + * @param[out] new_hmac_sha256_ctx Pointer to new HMAC-SHA256 context. + * + * @retval true HMAC-SHA256 context copy succeeded. + * @retval false HMAC-SHA256 context copy failed. + * @retval false This interface is not supported. + **/ +extern bool libspdm_hmac_sha256_duplicate(const void *hmac_sha256_ctx, void *new_hmac_sha256_ctx); + +/** + * Digests the input data and updates HMAC-SHA256 context. + * + * This function performs HMAC-SHA256 digest on a data buffer of the specified size. + * It can be called multiple times to compute the digest of long or discontinuous data streams. + * HMAC-SHA256 context should be initialized by libspdm_hmac_sha256_new(), and should not be + * finalized by libspdm_hmac_sha256_final(). Behavior with invalid context is undefined. + * + * If hmac_sha256_ctx is NULL, then return false. + * If this interface is not supported, then return false. + * + * @param[in, out] hmac_sha256_ctx Pointer to the HMAC-SHA256 context. + * @param[in] data Pointer to the buffer containing the data to be digested. + * @param[in] data_size Size of data buffer in bytes. + * + * @retval true HMAC-SHA256 data digest succeeded. + * @retval false HMAC-SHA256 data digest failed. + * @retval false This interface is not supported. + **/ +extern bool libspdm_hmac_sha256_update(void *hmac_sha256_ctx, const void *data, size_t data_size); + +/** + * Completes computation of the HMAC-SHA256 digest value. + * + * This function completes HMAC-SHA256 hash computation and retrieves the digest value into + * the specified memory. After this function has been called, the HMAC-SHA256 context cannot + * be used again. HMAC-SHA256 context should be initialized by libspdm_hmac_sha256_new(), and should + * not be finalized by libspdm_hmac_sha256_final(). Behavior with invalid HMAC-SHA256 context is + * undefined. + * + * If hmac_sha256_ctx is NULL, then return false. + * If hmac_value is NULL, then return false. + * If this interface is not supported, then return false. + * + * @param[in, out] hmac_sha256_ctx Pointer to the HMAC-SHA256 context. + * @param[out] hmac_value Pointer to a buffer that receives the HMAC-SHA256 digest + * value (32 bytes). + * + * @retval true HMAC-SHA256 digest computation succeeded. + * @retval false HMAC-SHA256 digest computation failed. + * @retval false This interface is not supported. + **/ +extern bool libspdm_hmac_sha256_final(void *hmac_sha256_ctx, uint8_t *hmac_value); + +/** + * Computes the HMAC-SHA256 digest of a input data buffer. + * + * This function performs the HMAC-SHA256 digest of a given data buffer, and places + * the digest value into the specified memory. + * + * If this interface is not supported, then return false. + * + * @param[in] data Pointer to the buffer containing the data to be digested. + * @param[in] data_size Size of data buffer in bytes. + * @param[in] key Pointer to the user-supplied key. + * @param[in] key_size Key size in bytes. + * @param[out] hmac_value Pointer to a buffer that receives the HMAC-SHA256 digest + * value (32 bytes). + * + * @retval true HMAC-SHA256 digest computation succeeded. + * @retval false HMAC-SHA256 digest computation failed. + * @retval false This interface is not supported. + **/ +extern bool libspdm_hmac_sha256_all(const void *data, size_t data_size, + const uint8_t *key, size_t key_size, + uint8_t *hmac_value); +#endif /* LIBSPDM_SHA256_SUPPORT */ + +#if LIBSPDM_SHA384_SUPPORT +/** + * Allocates and initializes one HMAC_CTX context for subsequent HMAC-SHA384 use. + * + * @return Pointer to the HMAC_CTX context that has been initialized. + * If the allocations fails, libspdm_hmac_sha384_new() returns NULL. + **/ +extern void *libspdm_hmac_sha384_new(void); + +/** + * Release the specified HMAC_CTX context. + * + * @param[in] hmac_sha384_ctx Pointer to the HMAC_CTX context to be released. + **/ +extern void libspdm_hmac_sha384_free(void *hmac_sha384_ctx); + +/** + * Set user-supplied key for subsequent use. It must be done before any + * calling to libspdm_hmac_sha384_update(). + * + * If hmac_sha384_ctx is NULL, then return false. + * If this interface is not supported, then return false. + * + * @param[out] hmac_sha384_ctx Pointer to HMAC-SHA384 context. + * @param[in] key Pointer to the user-supplied key. + * @param[in] key_size key size in bytes. + * + * @retval true The key is set successfully. + * @retval false The key is set unsuccessfully. + * @retval false This interface is not supported. + **/ +extern bool libspdm_hmac_sha384_set_key(void *hmac_sha384_ctx, const uint8_t *key, size_t key_size); + +/** + * Makes a copy of an existing HMAC-SHA384 context. + * + * If hmac_sha384_ctx is NULL, then return false. + * If new_hmac_sha384_ctx is NULL, then return false. + * If this interface is not supported, then return false. + * + * @param[in] hmac_sha384_ctx Pointer to HMAC-SHA384 context being copied. + * @param[out] new_hmac_sha384_ctx Pointer to new HMAC-SHA384 context. + * + * @retval true HMAC-SHA384 context copy succeeded. + * @retval false HMAC-SHA384 context copy failed. + * @retval false This interface is not supported. + **/ +extern bool libspdm_hmac_sha384_duplicate(const void *hmac_sha384_ctx, void *new_hmac_sha384_ctx); + +/** + * Digests the input data and updates HMAC-SHA384 context. + * + * This function performs HMAC-SHA384 digest on a data buffer of the specified size. + * It can be called multiple times to compute the digest of long or discontinuous data streams. + * HMAC-SHA384 context should be initialized by libspdm_hmac_sha384_new(), and should not be + * finalized by libspdm_hmac_sha384_final(). Behavior with invalid context is undefined. + * + * If hmac_sha384_ctx is NULL, then return false. + * If this interface is not supported, then return false. + * + * @param[in, out] hmac_sha384_ctx Pointer to the HMAC-SHA384 context. + * @param[in] data Pointer to the buffer containing the data to be digested. + * @param[in] data_size Size of data buffer in bytes. + * + * @retval true HMAC-SHA384 data digest succeeded. + * @retval false HMAC-SHA384 data digest failed. + * @retval false This interface is not supported. + **/ +extern bool libspdm_hmac_sha384_update(void *hmac_sha384_ctx, const void *data, size_t data_size); + +/** + * Completes computation of the HMAC-SHA384 digest value. + * + * This function completes HMAC-SHA384 hash computation and retrieves the digest value into + * the specified memory. After this function has been called, the HMAC-SHA384 context cannot + * be used again. HMAC-SHA384 context should be initialized by libspdm_hmac_sha384_new(), and should + * not be finalized by libspdm_hmac_sha384_final(). Behavior with invalid HMAC-SHA384 context is + * undefined. + * + * If hmac_sha384_ctx is NULL, then return false. + * If hmac_value is NULL, then return false. + * If this interface is not supported, then return false. + * + * @param[in, out] hmac_sha384_ctx Pointer to the HMAC-SHA384 context. + * @param[out] hmac_value Pointer to a buffer that receives the HMAC-SHA384 digest + * value (48 bytes). + * + * @retval true HMAC-SHA384 digest computation succeeded. + * @retval false HMAC-SHA384 digest computation failed. + * @retval false This interface is not supported. + **/ +extern bool libspdm_hmac_sha384_final(void *hmac_sha384_ctx, uint8_t *hmac_value); + +/** + * Computes the HMAC-SHA384 digest of a input data buffer. + * + * This function performs the HMAC-SHA384 digest of a given data buffer, and places + * the digest value into the specified memory. + * + * If this interface is not supported, then return false. + * + * @param[in] data Pointer to the buffer containing the data to be digested. + * @param[in] data_size Size of data buffer in bytes. + * @param[in] key Pointer to the user-supplied key. + * @param[in] key_size Key size in bytes. + * @param[out] hmac_value Pointer to a buffer that receives the HMAC-SHA384 digest + * value (48 bytes). + * + * @retval true HMAC-SHA384 digest computation succeeded. + * @retval false HMAC-SHA384 digest computation failed. + * @retval false This interface is not supported. + **/ +extern bool libspdm_hmac_sha384_all(const void *data, size_t data_size, + const uint8_t *key, size_t key_size, + uint8_t *hmac_value); +#endif /* LIBSPDM_SHA384_SUPPORT */ + +#if LIBSPDM_SHA512_SUPPORT +/** + * Allocates and initializes one HMAC_CTX context for subsequent HMAC-SHA512 use. + * + * @return Pointer to the HMAC_CTX context that has been initialized. + * If the allocations fails, libspdm_hmac_sha512_new() returns NULL. + **/ +extern void *libspdm_hmac_sha512_new(void); + +/** + * Release the specified HMAC_CTX context. + * + * @param[in] hmac_sha512_ctx Pointer to the HMAC_CTX context to be released. + **/ +extern void libspdm_hmac_sha512_free(void *hmac_sha512_ctx); + +/** + * Set user-supplied key for subsequent use. It must be done before any + * calling to libspdm_hmac_sha512_update(). + * + * If hmac_sha512_ctx is NULL, then return false. + * If this interface is not supported, then return false. + * + * @param[out] hmac_sha512_ctx Pointer to HMAC-SHA512 context. + * @param[in] key Pointer to the user-supplied key. + * @param[in] key_size Key size in bytes. + * + * @retval true The key is set successfully. + * @retval false The key is set unsuccessfully. + * @retval false This interface is not supported. + **/ +extern bool libspdm_hmac_sha512_set_key(void *hmac_sha512_ctx, const uint8_t *key, size_t key_size); + +/** + * Makes a copy of an existing HMAC-SHA512 context. + * + * If hmac_sha512_ctx is NULL, then return false. + * If new_hmac_sha512_ctx is NULL, then return false. + * If this interface is not supported, then return false. + * + * @param[in] hmac_sha512_ctx Pointer to HMAC-SHA512 context being copied. + * @param[out] new_hmac_sha512_ctx Pointer to new HMAC-SHA512 context. + * + * @retval true HMAC-SHA512 context copy succeeded. + * @retval false HMAC-SHA512 context copy failed. + * @retval false This interface is not supported. + **/ +extern bool libspdm_hmac_sha512_duplicate(const void *hmac_sha512_ctx, void *new_hmac_sha512_ctx); + +/** + * Digests the input data and updates HMAC-SHA512 context. + * + * This function performs HMAC-SHA512 digest on a data buffer of the specified size. + * It can be called multiple times to compute the digest of long or discontinuous data streams. + * HMAC-SHA512 context should be initialized by libspdm_hmac_sha512_new(), and should not be + * finalized by libspdm_hmac_sha512_final(). Behavior with invalid context is undefined. + * + * If hmac_sha512_ctx is NULL, then return false. + * If this interface is not supported, then return false. + * + * @param[in, out] hmac_sha512_ctx Pointer to the HMAC-SHA512 context. + * @param[in] data Pointer to the buffer containing the data to be digested. + * @param[in] data_size Size of data buffer in bytes. + * + * @retval true HMAC-SHA512 data digest succeeded. + * @retval false HMAC-SHA512 data digest failed. + * @retval false This interface is not supported. + **/ +extern bool libspdm_hmac_sha512_update(void *hmac_sha512_ctx, const void *data, size_t data_size); + +/** + * Completes computation of the HMAC-SHA512 digest value. + * + * This function completes HMAC-SHA512 hash computation and retrieves the digest value into + * the specified memory. After this function has been called, the HMAC-SHA512 context cannot + * be used again. HMAC-SHA512 context should be initialized by libspdm_hmac_sha512_new(), and should + * not be finalized by libspdm_hmac_sha512_final(). Behavior with invalid HMAC-SHA512 context is + * undefined. + * + * If hmac_sha512_ctx is NULL, then return false. + * If hmac_value is NULL, then return false. + * If this interface is not supported, then return false. + * + * @param[in, out] hmac_sha512_ctx Pointer to the HMAC-SHA512 context. + * @param[out] hmac_value Pointer to a buffer that receives the HMAC-SHA512 digest + * value (64 bytes). + * + * @retval true HMAC-SHA512 digest computation succeeded. + * @retval false HMAC-SHA512 digest computation failed. + * @retval false This interface is not supported. + **/ +extern bool libspdm_hmac_sha512_final(void *hmac_sha512_ctx, uint8_t *hmac_value); + +/** + * Computes the HMAC-SHA512 digest of a input data buffer. + * + * This function performs the HMAC-SHA512 digest of a given data buffer, and places + * the digest value into the specified memory. + * + * If this interface is not supported, then return false. + * + * @param[in] data Pointer to the buffer containing the data to be digested. + * @param[in] data_size Size of data buffer in bytes. + * @param[in] key Pointer to the user-supplied key. + * @param[in] key_size Key size in bytes. + * @param[out] hmac_value Pointer to a buffer that receives the HMAC-SHA512 digest + * value (64 bytes). + * + * @retval true HMAC-SHA512 digest computation succeeded. + * @retval false HMAC-SHA512 digest computation failed. + * @retval false This interface is not supported. + * + **/ +extern bool libspdm_hmac_sha512_all(const void *data, size_t data_size, + const uint8_t *key, size_t key_size, + uint8_t *hmac_value); +#endif /* LIBSPDM_SHA512_SUPPORT */ + +#if LIBSPDM_SHA3_256_SUPPORT +/** + * Allocates and initializes one HMAC_CTX context for subsequent HMAC-SHA3-256 use. + * + * @return Pointer to the HMAC_CTX context that has been initialized. + * If the allocations fails, libspdm_hmac_sha3_256_new() returns NULL. + **/ +extern void *libspdm_hmac_sha3_256_new(void); + +/** + * Release the specified HMAC_CTX context. + * + * @param[in] hmac_sha3_256_ctx Pointer to the HMAC_CTX context to be released. + **/ +extern void libspdm_hmac_sha3_256_free(void *hmac_sha3_256_ctx); + +/** + * Set user-supplied key for subsequent use. It must be done before any + * calling to libspdm_hmac_sha3_256_update(). + * + * If hmac_sha3_256_ctx is NULL, then return false. + * + * @param[out] hmac_sha3_256_ctx Pointer to HMAC-SHA3-256 context. + * @param[in] key Pointer to the user-supplied key. + * @param[in] key_size Key size in bytes. + * + * @retval true The key is set successfully. + * @retval false The key is set unsuccessfully. + **/ +extern bool libspdm_hmac_sha3_256_set_key(void *hmac_sha3_256_ctx, + const uint8_t *key, + size_t key_size); + +/** + * Makes a copy of an existing HMAC-SHA3-256 context. + * + * If hmac_sha3_256_ctx is NULL, then return false. + * If new_hmac_sha3_256_ctx is NULL, then return false. + * + * @param[in] hmac_sha3_256_ctx Pointer to HMAC-SHA3-256 context being copied. + * @param[out] new_hmac_sha3_256_ctx Pointer to new HMAC-SHA3-256 context. + * + * @retval true HMAC-SHA3-256 context copy succeeded. + * @retval false HMAC-SHA3-256 context copy failed. + **/ +extern bool libspdm_hmac_sha3_256_duplicate(const void *hmac_sha3_256_ctx, + void *new_hmac_sha3_256_ctx); + +/** + * Digests the input data and updates HMAC-SHA3-256 context. + * + * This function performs HMAC-SHA3-256 digest on a data buffer of the specified size. + * It can be called multiple times to compute the digest of long or discontinuous data streams. + * HMAC-SHA3-256 context should be initialized by libspdm_hmac_sha3_256_new(), and should not be + * finalized by libspdm_hmac_sha3_256_final(). Behavior with invalid context is undefined. + * + * If hmac_sha3_256_ctx is NULL, then return false. + * + * @param[in, out] hmac_sha3_256_ctx Pointer to the HMAC-SHA3-256 context. + * @param[in] data Pointer to the buffer containing the data to be digested. + * @param[in] data_size Size of data buffer in bytes. + * + * @retval true HMAC-SHA3-256 data digest succeeded. + * @retval false HMAC-SHA3-256 data digest failed. + **/ +extern bool libspdm_hmac_sha3_256_update(void *hmac_sha3_256_ctx, + const void *data, size_t data_size); + +/** + * Completes computation of the HMAC-SHA3-256 digest value. + * + * This function completes HMAC-SHA3-256 hash computation and retrieves the digest value into + * the specified memory. After this function has been called, the HMAC-SHA3-256 context cannot + * be used again. HMAC-SHA3-256 context should be initialized by libspdm_hmac_sha3_256_new(), and + * should not be finalized by libspdm_hmac_sha3_256_final(). Behavior with invalid HMAC-SHA3-256 + * context is undefined. + * + * If hmac_sha3_256_ctx is NULL, then return false. + * If hmac_value is NULL, then return false. + * + * @param[in, out] hmac_sha3_256_ctx Pointer to the HMAC-SHA3-256 context. + * @param[out] hmac_value Pointer to a buffer that receives the HMAC-SHA3-256 digest + * value (32 bytes). + * + * @retval true HMAC-SHA3-256 digest computation succeeded. + * @retval false HMAC-SHA3-256 digest computation failed. + **/ +extern bool libspdm_hmac_sha3_256_final(void *hmac_sha3_256_ctx, uint8_t *hmac_value); + +/** + * Computes the HMAC-SHA3-256 digest of a input data buffer. + * + * This function performs the HMAC-SHA3-256 digest of a given data buffer, and places + * the digest value into the specified memory. + * + * If this interface is not supported, then return false. + * + * @param[in] data Pointer to the buffer containing the data to be digested. + * @param[in] data_size Size of data buffer in bytes. + * @param[in] key Pointer to the user-supplied key. + * @param[in] key_size Key size in bytes. + * @param[out] hmac_value Pointer to a buffer that receives the HMAC-SHA3-256 digest + * value (32 bytes). + * + * @retval true HMAC-SHA3-256 digest computation succeeded. + * @retval false HMAC-SHA3-256 digest computation failed. + * @retval false This interface is not supported. + **/ +extern bool libspdm_hmac_sha3_256_all(const void *data, size_t data_size, + const uint8_t *key, size_t key_size, + uint8_t *hmac_value); +#endif /* LIBSPDM_SHA3_256_SUPPORT */ + +#if LIBSPDM_SHA3_384_SUPPORT +/** + * Allocates and initializes one HMAC_CTX context for subsequent HMAC-SHA3-384 use. + * + * @return Pointer to the HMAC_CTX context that has been initialized. + * If the allocations fails, libspdm_hmac_sha3_384_new() returns NULL. + **/ +extern void *libspdm_hmac_sha3_384_new(void); + +/** + * Release the specified HMAC_CTX context. + * + * @param[in] hmac_sha3_384_ctx Pointer to the HMAC_CTX context to be released. + **/ +extern void libspdm_hmac_sha3_384_free(void *hmac_sha3_384_ctx); + +/** + * Set user-supplied key for subsequent use. It must be done before any + * calling to libspdm_hmac_sha3_384_update(). + * + * If hmac_sha3_384_ctx is NULL, then return false. + * If this interface is not supported, then return false. + * + * @param[out] hmac_sha3_384_ctx Pointer to HMAC-SHA3-384 context. + * @param[in] key Pointer to the user-supplied key. + * @param[in] key_size Key size in bytes. + * + * @retval true The key is set successfully. + * @retval false The key is set unsuccessfully. + * @retval false This interface is not supported. + **/ +extern bool libspdm_hmac_sha3_384_set_key(void *hmac_sha3_384_ctx, + const uint8_t *key, + size_t key_size); + +/** + * Makes a copy of an existing HMAC-SHA3-384 context. + * + * If hmac_sha3_384_ctx is NULL, then return false. + * If new_hmac_sha3_384_ctx is NULL, then return false. + * If this interface is not supported, then return false. + * + * @param[in] hmac_sha3_384_ctx Pointer to HMAC-SHA3-384 context being copied. + * @param[out] new_hmac_sha3_384_ctx Pointer to new HMAC-SHA3-384 context. + * + * @retval true HMAC-SHA3-384 context copy succeeded. + * @retval false HMAC-SHA3-384 context copy failed. + * @retval false This interface is not supported. + **/ +extern bool libspdm_hmac_sha3_384_duplicate(const void *hmac_sha3_384_ctx, + void *new_hmac_sha3_384_ctx); + +/** + * Digests the input data and updates HMAC-SHA3-384 context. + * + * This function performs HMAC-SHA3-384 digest on a data buffer of the specified size. + * It can be called multiple times to compute the digest of long or discontinuous data streams. + * HMAC-SHA3-384 context should be initialized by libspdm_hmac_sha3_384_new(), and should not be + * finalized by libspdm_hmac_sha3_384_final(). Behavior with invalid context is undefined. + * + * If hmac_sha3_384_ctx is NULL, then return false. + * If this interface is not supported, then return false. + * + * @param[in, out] hmac_sha3_384_ctx Pointer to the HMAC-SHA3-384 context. + * @param[in] data Pointer to the buffer containing the data to be digested. + * @param[in] data_size Size of data buffer in bytes. + * + * @retval true HMAC-SHA3-384 data digest succeeded. + * @retval false HMAC-SHA3-384 data digest failed. + * @retval false This interface is not supported. + **/ +extern bool libspdm_hmac_sha3_384_update(void *hmac_sha3_384_ctx, const void *data, + size_t data_size); + +/** + * Completes computation of the HMAC-SHA3-384 digest value. + * + * This function completes HMAC-SHA3-384 hash computation and retrieves the digest value into + * the specified memory. After this function has been called, the HMAC-SHA3-384 context cannot + * be used again. HMAC-SHA3-384 context should be initialized by libspdm_hmac_sha3_384_new(), and + * should not be finalized by libspdm_hmac_sha3_384_final(). Behavior with invalid HMAC-SHA3-384 + * context is undefined. + * + * If hmac_sha3_384_ctx is NULL, then return false. + * If hmac_value is NULL, then return false. + * If this interface is not supported, then return false. + * + * @param[in, out] hmac_sha3_384_ctx Pointer to the HMAC-SHA3-384 context. + * @param[out] hmac_value Pointer to a buffer that receives the HMAC-SHA3-384 digest + * value (48 bytes). + * + * @retval true HMAC-SHA3-384 digest computation succeeded. + * @retval false HMAC-SHA3-384 digest computation failed. + * @retval false This interface is not supported. + **/ +extern bool libspdm_hmac_sha3_384_final(void *hmac_sha3_384_ctx, uint8_t *hmac_value); + +/** + * Computes the HMAC-SHA3-384 digest of a input data buffer. + * + * This function performs the HMAC-SHA3-384 digest of a given data buffer, and places + * the digest value into the specified memory. + * + * If this interface is not supported, then return false. + * + * @param[in] data Pointer to the buffer containing the data to be digested. + * @param[in] data_size Size of data buffer in bytes. + * @param[in] key Pointer to the user-supplied key. + * @param[in] key_size Key size in bytes. + * @param[out] hmac_value Pointer to a buffer that receives the HMAC-SHA3-384 digest + * value (48 bytes). + * + * @retval true HMAC-SHA3-384 digest computation succeeded. + * @retval false HMAC-SHA3-384 digest computation failed. + * @retval false This interface is not supported. + **/ +extern bool libspdm_hmac_sha3_384_all(const void *data, size_t data_size, + const uint8_t *key, size_t key_size, + uint8_t *hmac_value); +#endif /* LIBSPDM_SHA3_384_SUPPORT */ + +#if LIBSPDM_SHA3_512_SUPPORT +/** + * Allocates and initializes one HMAC_CTX context for subsequent HMAC-SHA3-512 use. + * + * @return Pointer to the HMAC_CTX context that has been initialized. + * If the allocations fails, libspdm_hmac_sha3_512_new() returns NULL. + **/ +extern void *libspdm_hmac_sha3_512_new(void); + +/** + * Release the specified HMAC_CTX context. + * + * @param[in] hmac_sha3_512_ctx Pointer to the HMAC_CTX context to be released. + **/ +extern void libspdm_hmac_sha3_512_free(void *hmac_sha3_512_ctx); + +/** + * Set user-supplied key for subsequent use. It must be done before any + * calling to libspdm_hmac_sha3_512_update(). + * + * If hmac_sha3_512_ctx is NULL, then return false. + * If this interface is not supported, then return false. + * + * @param[out] hmac_sha3_512_ctx Pointer to HMAC-SHA3-512 context. + * @param[in] key Pointer to the user-supplied key. + * @param[in] key_size Key size in bytes. + * + * @retval true The key is set successfully. + * @retval false The key is set unsuccessfully. + * @retval false This interface is not supported. + **/ +extern bool libspdm_hmac_sha3_512_set_key(void *hmac_sha3_512_ctx, + const uint8_t *key, + size_t key_size); + +/** + * Makes a copy of an existing HMAC-SHA3-512 context. + * + * If hmac_sha3_512_ctx is NULL, then return false. + * If new_hmac_sha3_512_ctx is NULL, then return false. + * If this interface is not supported, then return false. + * + * @param[in] hmac_sha3_512_ctx Pointer to HMAC-SHA3-512 context being copied. + * @param[out] new_hmac_sha3_512_ctx Pointer to new HMAC-SHA3-512 context. + * + * @retval true HMAC-SHA3-512 context copy succeeded. + * @retval false HMAC-SHA3-512 context copy failed. + * @retval false This interface is not supported. + **/ +extern bool libspdm_hmac_sha3_512_duplicate(const void *hmac_sha3_512_ctx, + void *new_hmac_sha3_512_ctx); + +/** + * Digests the input data and updates HMAC-SHA3-512 context. + * + * This function performs HMAC-SHA3-512 digest on a data buffer of the specified size. + * It can be called multiple times to compute the digest of long or discontinuous data streams. + * HMAC-SHA3-512 context should be initialized by libspdm_hmac_sha3_512_new(), and should not be + * finalized by libspdm_hmac_sha3_512_final(). Behavior with invalid context is undefined. + * + * If hmac_sha3_512_ctx is NULL, then return false. + * If this interface is not supported, then return false. + * + * @param[in, out] hmac_sha3_512_ctx Pointer to the HMAC-SHA3-512 context. + * @param[in] data Pointer to the buffer containing the data to be digested. + * @param[in] data_size Size of data buffer in bytes. + * + * @retval true HMAC-SHA3-512 data digest succeeded. + * @retval false HMAC-SHA3-512 data digest failed. + * @retval false This interface is not supported. + **/ +extern bool libspdm_hmac_sha3_512_update(void *hmac_sha3_512_ctx, + const void *data, size_t data_size); + +/** + * Completes computation of the HMAC-SHA3-512 digest value. + * + * This function completes HMAC-SHA3-512 hash computation and retrieves the digest value into + * the specified memory. After this function has been called, the HMAC-SHA3-512 context cannot + * be used again. HMAC-SHA3-512 context should be initialized by libspdm_hmac_sha3_512_new(), and + * should not be finalized by libspdm_hmac_sha3_512_final(). Behavior with invalid HMAC-SHA3-512 + * context is undefined. + * + * If hmac_sha3_512_ctx is NULL, then return false. + * If hmac_value is NULL, then return false. + * If this interface is not supported, then return false. + * + * @param[in, out] hmac_sha3_512_ctx Pointer to the HMAC-SHA3-512 context. + * @param[out] hmac_value Pointer to a buffer that receives the HMAC-SHA3-512 digest + * value (64 bytes). + * + * @retval true HMAC-SHA3-512 digest computation succeeded. + * @retval false HMAC-SHA3-512 digest computation failed. + * @retval false This interface is not supported. + **/ +extern bool libspdm_hmac_sha3_512_final(void *hmac_sha3_512_ctx, uint8_t *hmac_value); + +/** + * Computes the HMAC-SHA3-512 digest of a input data buffer. + * + * This function performs the HMAC-SHA3-512 digest of a given data buffer, and places + * the digest value into the specified memory. + * + * If this interface is not supported, then return false. + * + * @param[in] data Pointer to the buffer containing the data to be digested. + * @param[in] data_size Size of data buffer in bytes. + * @param[in] key Pointer to the user-supplied key. + * @param[in] key_size Key size in bytes. + * @param[out] hmac_value Pointer to a buffer that receives the HMAC-SHA3-512 digest + * value (64 bytes). + * + * @retval true HMAC-SHA3-512 digest computation succeeded. + * @retval false HMAC-SHA3-512 digest computation failed. + * @retval false This interface is not supported. + **/ +extern bool libspdm_hmac_sha3_512_all(const void *data, size_t data_size, + const uint8_t *key, size_t key_size, + uint8_t *hmac_value); +#endif /* LIBSPDM_SHA3_512_SUPPORT */ + +#if LIBSPDM_SM3_256_SUPPORT +/** + * Allocates and initializes one HMAC_CTX context for subsequent HMAC-SM3-256 use. + * + * @return Pointer to the HMAC_CTX context that has been initialized. + * If the allocations fails, libspdm_hmac_sm3_256_new() returns NULL. + **/ +extern void *libspdm_hmac_sm3_256_new(void); + +/** + * Release the specified HMAC_CTX context. + * + * @param[in] hmac_sm3_256_ctx Pointer to the HMAC_CTX context to be released. + **/ +extern void libspdm_hmac_sm3_256_free(void *hmac_sm3_256_ctx); + +/** + * Set user-supplied key for subsequent use. It must be done before any + * calling to libspdm_hmac_sm3_256_update(). + * + * If hmac_sm3_256_ctx is NULL, then return false. + * + * @param[out] hmac_sm3_256_ctx Pointer to HMAC-SM3-256 context. + * @param[in] key Pointer to the user-supplied key. + * @param[in] key_size Key size in bytes. + * + * @retval true The key is set successfully. + * @retval false The key is set unsuccessfully. + **/ +extern bool libspdm_hmac_sm3_256_set_key(void *hmac_sm3_256_ctx, + const uint8_t *key, size_t key_size); + +/** + * Makes a copy of an existing HMAC-SM3-256 context. + * + * If hmac_sm3_256_ctx is NULL, then return false. + * If new_hmac_sm3_256_ctx is NULL, then return false. + * + * @param[in] hmac_sm3_256_ctx Pointer to HMAC-SM3-256 context being copied. + * @param[out] new_hmac_sm3_256_ctx Pointer to new HMAC-SM3-256 context. + * + * @retval true HMAC-SM3-256 context copy succeeded. + * @retval false HMAC-SM3-256 context copy failed. + **/ +extern bool libspdm_hmac_sm3_256_duplicate(const void *hmac_sm3_256_ctx, + void *new_hmac_sm3_256_ctx); + +/** + * Digests the input data and updates HMAC-SM3-256 context. + * + * This function performs HMAC-SM3-256 digest on a data buffer of the specified size. + * It can be called multiple times to compute the digest of long or discontinuous data streams. + * HMAC-SM3-256 context should be initialized by libspdm_hmac_sm3_256_new(), and should not be + * finalized by libspdm_hmac_sm3_256_final(). Behavior with invalid context is undefined. + * + * If hmac_sm3_256_ctx is NULL, then return false. + * + * @param[in, out] hmac_sm3_256_ctx Pointer to the HMAC-SM3-256 context. + * @param[in] data Pointer to the buffer containing the data to be digested. + * @param[in] data_size Size of data buffer in bytes. + * + * @retval true HMAC-SM3-256 data digest succeeded. + * @retval false HMAC-SM3-256 data digest failed. + **/ +extern bool libspdm_hmac_sm3_256_update(void *hmac_sm3_256_ctx, const void *data, size_t data_size); + +/** + * Completes computation of the HMAC-SM3-256 digest value. + * + * This function completes HMAC-SM3-256 hash computation and retrieves the digest value into + * the specified memory. After this function has been called, the HMAC-SM3-256 context cannot + * be used again. HMAC-SM3-256 context should be initialized by libspdm_hmac_sm3_256_new(), and + * should not be finalized by libspdm_hmac_sm3_256_final(). Behavior with invalid HMAC-SM3-256 + * context is undefined. + * + * If hmac_sm3_256_ctx is NULL, then return false. + * If hmac_value is NULL, then return false. + * + * @param[in, out] hmac_sm3_256_ctx Pointer to the HMAC-SM3-256 context. + * @param[out] hmac_value Pointer to a buffer that receives the HMAC-SM3-256 digest + * value (32 bytes). + * + * @retval true HMAC-SM3-256 digest computation succeeded. + * @retval false HMAC-SM3-256 digest computation failed. + **/ +extern bool libspdm_hmac_sm3_256_final(void *hmac_sm3_256_ctx, uint8_t *hmac_value); + +/** + * Computes the HMAC-SM3-256 digest of a input data buffer. + * + * This function performs the HMAC-SM3-256 digest of a given data buffer, and places + * the digest value into the specified memory. + * + * If this interface is not supported, then return false. + * + * @param[in] data Pointer to the buffer containing the data to be digested. + * @param[in] data_size Size of data buffer in bytes. + * @param[in] key Pointer to the user-supplied key. + * @param[in] key_size Key size in bytes. + * @param[out] hmac_value Pointer to a buffer that receives the HMAC-SM3-256 digest + * value (32 bytes). + * + * @retval true HMAC-SM3-256 digest computation succeeded. + * @retval false HMAC-SM3-256 digest computation failed. + * @retval false This interface is not supported. + **/ +extern bool libspdm_hmac_sm3_256_all(const void *data, size_t data_size, + const uint8_t *key, size_t key_size, + uint8_t *hmac_value); +#endif /* LIBSPDM_SM3_256_SUPPORT */ + +#endif /* CRYPTLIB_MAC_H */ diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/libraries/libspdm/2.3.1/include/hal/library/cryptlib/cryptlib_rng.h nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/libraries/libspdm/2.3.1/include/hal/library/cryptlib/cryptlib_rng.h --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/libraries/libspdm/2.3.1/include/hal/library/cryptlib/cryptlib_rng.h 1970-01-01 00:00:00.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/libraries/libspdm/2.3.1/include/hal/library/cryptlib/cryptlib_rng.h 2024-03-05 22:14:11.000000000 +0000 @@ -0,0 +1,30 @@ +/** + * Copyright Notice: + * Copyright 2021-2022 DMTF. All rights reserved. + * License: BSD 3-Clause License. For full text see link: https://github.com/DMTF/libspdm/blob/main/LICENSE.md + **/ + +#ifndef CRYPTLIB_RNG_H +#define CRYPTLIB_RNG_H + +/*===================================================================================== + * Random Number Generation Primitive + *=====================================================================================*/ + +/** + * Generates a random byte stream of the specified size. If initialization, testing, or seeding of + * the (pseudo)random number generator is required it should be done before this function is called. + * + * If output is NULL, then return false. + * If this interface is not supported, then return false. + * + * @param[out] output Pointer to buffer to receive random value. + * @param[in] size Size of random bytes to generate. + * + * @retval true Random byte stream generated successfully. + * @retval false Generation of random byte stream failed. + * @retval false This interface is not supported. + **/ +extern bool libspdm_random_bytes(uint8_t *output, size_t size); + +#endif /* CRYPTLIB_RNG_H */ diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/libraries/libspdm/2.3.1/include/hal/library/cryptlib/cryptlib_rsa.h nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/libraries/libspdm/2.3.1/include/hal/library/cryptlib/cryptlib_rsa.h --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/libraries/libspdm/2.3.1/include/hal/library/cryptlib/cryptlib_rsa.h 1970-01-01 00:00:00.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/libraries/libspdm/2.3.1/include/hal/library/cryptlib/cryptlib_rsa.h 2024-03-05 22:14:11.000000000 +0000 @@ -0,0 +1,264 @@ +/** + * Copyright Notice: + * Copyright 2021-2022 DMTF. All rights reserved. + * License: BSD 3-Clause License. For full text see link: https://github.com/DMTF/libspdm/blob/main/LICENSE.md + **/ + +#ifndef CRYPTLIB_RSA_H +#define CRYPTLIB_RSA_H + +/*===================================================================================== + * RSA Cryptography Primitives + *===================================================================================== + */ + +#if (LIBSPDM_RSA_SSA_SUPPORT) || (LIBSPDM_RSA_PSS_SUPPORT) +/* RSA key Tags Definition used in libspdm_rsa_set_key() function for key component + * identification. + */ +typedef enum { + LIBSPDM_RSA_KEY_N, /*< RSA public Modulus (N)*/ + LIBSPDM_RSA_KEY_E, /*< RSA public exponent (e)*/ + LIBSPDM_RSA_KEY_D, /*< RSA Private exponent (d)*/ + LIBSPDM_RSA_KEY_P, /*< RSA secret prime factor of Modulus (p)*/ + LIBSPDM_RSA_KEY_Q, /*< RSA secret prime factor of Modules (q)*/ + LIBSPDM_RSA_KEY_DP, /*< p's CRT exponent (== d mod (p - 1))*/ + LIBSPDM_RSA_KEY_DQ, /*< q's CRT exponent (== d mod (q - 1))*/ + LIBSPDM_RSA_KEY_Q_INV /*< The CRT coefficient (== 1/q mod p)*/ +} libspdm_rsa_key_tag_t; + +/** + * Allocates and initializes one RSA context for subsequent use. + * + * @return Pointer to the RSA context that has been initialized. + * If the allocations fails, libspdm_rsa_new() returns NULL. + **/ +extern void *libspdm_rsa_new(void); + +/** + * Release the specified RSA context. + * + * If rsa_context is NULL, then return false. + * + * @param[in] rsa_context Pointer to the RSA context to be released. + **/ +extern void libspdm_rsa_free(void *rsa_context); + +/** + * Sets the tag-designated key component into the established RSA context. + * + * This function sets the tag-designated RSA key component into the established + * RSA context from the user-specified non-negative integer (octet string format + * represented in RSA PKCS#1). + * If big_number is NULL, then the specified key component in RSA context is cleared. + * If rsa_context is NULL, then return false. + * + * @param[in, out] rsa_context Pointer to RSA context being set. + * @param[in] key_tag tag of RSA key component being set. + * @param[in] big_number Pointer to octet integer buffer. + * If NULL, then the specified key component in RSA + * context is cleared. + * @param[in] bn_size Size of big number buffer in bytes. + * If big_number is NULL, then it is ignored. + * + * @retval true RSA key component was set successfully. + * @retval false Invalid RSA key component tag. + **/ +extern bool libspdm_rsa_set_key(void *rsa_context, const libspdm_rsa_key_tag_t key_tag, + const uint8_t *big_number, size_t bn_size); + +/** + * Gets the tag-designated RSA key component from the established RSA context. + * + * This function retrieves the tag-designated RSA key component from the + * established RSA context as a non-negative integer (octet string format + * represented in RSA PKCS#1). + * If specified key component has not been set or has been cleared, then returned + * bn_size is set to 0. + * If the big_number buffer is too small to hold the contents of the key, false + * is returned and bn_size is set to the required buffer size to obtain the key. + * + * If rsa_context is NULL, then return false. + * If bn_size is NULL, then return false. + * If bn_size is large enough but big_number is NULL, then return false. + * If this interface is not supported, then return false. + * + * @param[in, out] rsa_context Pointer to RSA context being set. + * @param[in] key_tag Tag of RSA key component being set. + * @param[out] big_number Pointer to octet integer buffer. + * @param[in, out] bn_size On input, the size of big number buffer in bytes. + * On output, the size of data returned in big number buffer in bytes. + * + * @retval true RSA key component was retrieved successfully. + * @retval false Invalid RSA key component tag. + * @retval false bn_size is too small. + * @retval false This interface is not supported. + **/ +extern bool libspdm_rsa_get_key(void *rsa_context, const libspdm_rsa_key_tag_t key_tag, + uint8_t *big_number, size_t *bn_size); + +/** + * Generates RSA key components. + * + * This function generates RSA key components. It takes RSA public exponent E and + * length in bits of RSA modulus N as input, and generates all key components. + * If public_exponent is NULL, the default RSA public exponent (0x10001) will be used. + * + * If rsa_context is NULL, then return false. + * If this interface is not supported, then return false. + * + * @param[in, out] rsa_context Pointer to RSA context being set. + * @param[in] modulus_length Length of RSA modulus N in bits. + * @param[in] public_exponent Pointer to RSA public exponent. + * @param[in] public_exponent_size Size of RSA public exponent buffer in bytes. + * + * @retval true RSA key component was generated successfully. + * @retval false Invalid RSA key component tag. + * @retval false This interface is not supported. + **/ +extern bool libspdm_rsa_generate_key(void *rsa_context, size_t modulus_length, + const uint8_t *public_exponent, + size_t public_exponent_size); + +/** + * Validates key components of RSA context. + * NOTE: This function performs integrity checks on all the RSA key material, so + * the RSA key structure must contain all the private key data. + * + * This function validates key components of RSA context in following aspects: + * - Whether p is a prime + * - Whether q is a prime + * - Whether n = p * q + * - Whether d*e = 1 mod lcm(p-1,q-1) + * + * If rsa_context is NULL, then return false. + * If this interface is not supported, then return false. + * + * @param[in] rsa_context Pointer to RSA context to check. + * + * @retval true RSA key components are valid. + * @retval false RSA key components are not valid. + * @retval false This interface is not supported. + **/ +extern bool libspdm_rsa_check_key(void *rsa_context); +#endif /* (LIBSPDM_RSA_SSA_SUPPORT) || (LIBSPDM_RSA_PSS_SUPPORT) */ + +#if LIBSPDM_RSA_SSA_SUPPORT +/** + * Carries out the RSA-SSA signature generation with EMSA-PKCS1-v1_5 encoding scheme. + * + * This function carries out the RSA-SSA signature generation with EMSA-PKCS1-v1_5 encoding scheme + * defined in RSA PKCS#1. If the signature buffer is too small to hold the contents of signature, + * false is returned and sig_size is set to the required buffer size to obtain the signature. + * + * If rsa_context is NULL, then return false. + * If message_hash is NULL, then return false. + * If hash_size need match the hash_nid. hash_nid could be SHA256, SHA384, SHA512, SHA3_256, + * SHA3_384, SHA3_512. + * If sig_size is large enough but signature is NULL, then return false. + * If this interface is not supported, then return false. + * + * @param[in] rsa_context Pointer to RSA context for signature generation. + * @param[in] hash_nid hash NID + * @param[in] message_hash Pointer to octet message hash to be signed. + * @param[in] hash_size Size of the message hash in bytes. + * @param[out] signature Pointer to buffer to receive RSA PKCS1-v1_5 signature. + * @param[in, out] sig_size On input, the size of signature buffer in bytes. + * On output, the size of data returned in signature buffer in bytes. + * + * @retval true signature successfully generated in PKCS1-v1_5. + * @retval false signature generation failed. + * @retval false sig_size is too small. + * @retval false This interface is not supported. + **/ +extern bool libspdm_rsa_pkcs1_sign_with_nid(void *rsa_context, size_t hash_nid, + const uint8_t *message_hash, + size_t hash_size, uint8_t *signature, + size_t *sig_size); + +/** + * Verifies the RSA-SSA signature with EMSA-PKCS1-v1_5 encoding scheme defined in RSA PKCS#1. + * + * If rsa_context is NULL, then return false. + * If message_hash is NULL, then return false. + * If signature is NULL, then return false. + * If hash_size need match the hash_nid. hash_nid could be SHA256, SHA384, SHA512, SHA3_256, + * SHA3_384, SHA3_512. + * + * @param[in] rsa_context Pointer to RSA context for signature verification. + * @param[in] hash_nid hash NID + * @param[in] message_hash Pointer to octet message hash to be checked. + * @param[in] hash_size Size of the message hash in bytes. + * @param[in] signature Pointer to RSA PKCS1-v1_5 signature to be verified. + * @param[in] sig_size Size of signature in bytes. + * + * @retval true Valid signature encoded in PKCS1-v1_5. + * @retval false Invalid signature or invalid RSA context. + **/ +extern bool libspdm_rsa_pkcs1_verify_with_nid(void *rsa_context, size_t hash_nid, + const uint8_t *message_hash, + size_t hash_size, const uint8_t *signature, + size_t sig_size); +#endif /* LIBSPDM_RSA_SSA_SUPPORT */ + +#if LIBSPDM_RSA_PSS_SUPPORT +/** + * Carries out the RSA-SSA signature generation with EMSA-PSS encoding scheme. + * + * This function carries out the RSA-SSA signature generation with EMSA-PSS encoding scheme defined + * in RSA PKCS#1 v2.2. + * + * The salt length is same as digest length. + * + * If the signature buffer is too small to hold the contents of signature, false + * is returned and sig_size is set to the required buffer size to obtain the signature. + * + * If rsa_context is NULL, then return false. + * If message_hash is NULL, then return false. + * If hash_size need match the hash_nid. nid could be SHA256, SHA384, SHA512, SHA3_256, SHA3_384, + * SHA3_512. + * If sig_size is large enough but signature is NULL, then return false. + * + * @param[in] rsa_context Pointer to RSA context for signature generation. + * @param[in] hash_nid hash NID + * @param[in] message_hash Pointer to octet message hash to be signed. + * @param[in] hash_size Size of the message hash in bytes. + * @param[out] signature Pointer to buffer to receive RSA-SSA PSS signature. + * @param[in, out] sig_size On input, the size of signature buffer in bytes. + * On output, the size of data returned in signature buffer in bytes. + * + * @retval true signature successfully generated in RSA-SSA PSS. + * @retval false signature generation failed. + * @retval false sig_size is too small. + **/ +extern bool libspdm_rsa_pss_sign(void *rsa_context, size_t hash_nid, + const uint8_t *message_hash, size_t hash_size, + uint8_t *signature, size_t *sig_size); + +/** + * Verifies the RSA-SSA signature with EMSA-PSS encoding scheme defined in + * RSA PKCS#1 v2.2. + * + * The salt length is same as digest length. + * + * If rsa_context is NULL, then return false. + * If message_hash is NULL, then return false. + * If signature is NULL, then return false. + * If hash_size need match the hash_nid. nid could be SHA256, SHA384, SHA512, SHA3_256, SHA3_384, + * SHA3_512. + * + * @param[in] rsa_context Pointer to RSA context for signature verification. + * @param[in] hash_nid hash NID + * @param[in] message_hash Pointer to octet message hash to be checked. + * @param[in] hash_size Size of the message hash in bytes. + * @param[in] signature Pointer to RSA-SSA PSS signature to be verified. + * @param[in] sig_size Size of signature in bytes. + * + * @retval true Valid signature encoded in RSA-SSA PSS. + * @retval false Invalid signature or invalid RSA context. + **/ +extern bool libspdm_rsa_pss_verify(void *rsa_context, size_t hash_nid, + const uint8_t *message_hash, size_t hash_size, + const uint8_t *signature, size_t sig_size); +#endif /* LIBSPDM_RSA_PSS_SUPPORT */ +#endif /* CRYPTLIB_RSA_H */ diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/libraries/libspdm/2.3.1/include/hal/library/cryptlib/cryptlib_sm2.h nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/libraries/libspdm/2.3.1/include/hal/library/cryptlib/cryptlib_sm2.h --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/libraries/libspdm/2.3.1/include/hal/library/cryptlib/cryptlib_sm2.h 1970-01-01 00:00:00.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/libraries/libspdm/2.3.1/include/hal/library/cryptlib/cryptlib_sm2.h 2024-03-05 22:14:11.000000000 +0000 @@ -0,0 +1,194 @@ +/** + * Copyright Notice: + * Copyright 2021-2022 DMTF. All rights reserved. + * License: BSD 3-Clause License. For full text see link: https://github.com/DMTF/libspdm/blob/main/LICENSE.md + **/ + +#ifndef CRYPTLIB_SM2_H +#define CRYPTLIB_SM2_H + +/*===================================================================================== + * Shang-Mi2 Primitives + *=====================================================================================*/ + +#if LIBSPDM_SM2_DSA_SUPPORT +/** + * Allocates and Initializes one Shang-Mi2 context for subsequent use. + * + * @param nid cipher NID + * + * @return Pointer to the Shang-Mi2 context that has been initialized. + * If the allocations fails, sm2_new_by_nid() returns NULL. + **/ +extern void *libspdm_sm2_dsa_new_by_nid(size_t nid); + +/** + * Release the specified sm2 context. + * + * @param[in] sm2_context Pointer to the sm2 context to be released. + **/ +extern void libspdm_sm2_dsa_free(void *sm2_context); + +/** + * Carries out the SM2 signature, based upon GB/T 32918.2-2016: SM2 - Part2. + * + * This function carries out the SM2 signature. + * If the signature buffer is too small to hold the contents of signature, false + * is returned and sig_size is set to the required buffer size to obtain the signature. + * + * If sm2_context is NULL, then return false. + * If message is NULL, then return false. + * hash_nid must be SM3_256. + * If sig_size is large enough but signature is NULL, then return false. + * + * The id_a_size must be smaller than 2^16-1. + * The sig_size is 64. first 32-byte is R, second 32-byte is S. + * + * @param[in] sm2_context Pointer to sm2 context for signature generation. + * @param[in] hash_nid hash NID + * @param[in] id_a The ID-A of the signing context. + * @param[in] id_a_size Size of ID-A signing context. + * @param[in] message Pointer to octet message to be signed (before hash). + * @param[in] size Size of the message in bytes. + * @param[out] signature Pointer to buffer to receive SM2 signature. + * @param[in, out] sig_size On input, the size of signature buffer in bytes. + * On output, the size of data returned in signature buffer in bytes. + * + * @retval true signature successfully generated in SM2. + * @retval false signature generation failed. + * @retval false sig_size is too small. + **/ +extern bool libspdm_sm2_dsa_sign(const void *sm2_context, size_t hash_nid, + const uint8_t *id_a, size_t id_a_size, + const uint8_t *message, size_t size, + uint8_t *signature, size_t *sig_size); + +/** + * Verifies the SM2 signature, based upon GB/T 32918.2-2016: SM2 - Part2. + * + * If sm2_context is NULL, then return false. + * If message is NULL, then return false. + * If signature is NULL, then return false. + * hash_nid must be SM3_256. + * + * The id_a_size must be smaller than 2^16-1. + * The sig_size is 64. first 32-byte is R, second 32-byte is S. + * + * @param[in] sm2_context Pointer to SM2 context for signature verification. + * @param[in] hash_nid hash NID + * @param[in] id_a The ID-A of the signing context. + * @param[in] id_a_size Size of ID-A signing context. + * @param[in] message Pointer to octet message to be checked (before hash). + * @param[in] size Size of the message in bytes. + * @param[in] signature Pointer to SM2 signature to be verified. + * @param[in] sig_size Size of signature in bytes. + * + * @retval true Valid signature encoded in SM2. + * @retval false Invalid signature or invalid sm2 context. + * + **/ +extern bool libspdm_sm2_dsa_verify(const void *sm2_context, size_t hash_nid, + const uint8_t *id_a, size_t id_a_size, + const uint8_t *message, size_t size, + const uint8_t *signature, size_t sig_size); +#endif /* LIBSPDM_SM2_DSA_SUPPORT */ + +#if LIBSPDM_SM2_KEY_EXCHANGE_SUPPORT +/** + * Allocates and Initializes one Shang-Mi2 context for subsequent use. + * + * @param nid cipher NID + * + * @return Pointer to the Shang-Mi2 context that has been initialized. + * If the allocations fails, sm2_new_by_nid() returns NULL. + **/ +extern void *libspdm_sm2_key_exchange_new_by_nid(size_t nid); + +/** + * Release the specified sm2 context. + * + * @param[in] sm2_context Pointer to the sm2 context to be released. + * + **/ +extern void libspdm_sm2_key_exchange_free(void *sm2_context); + +/** + * Initialize the specified sm2 context. + * + * @param[in] sm2_context Pointer to the sm2 context to be released. + * @param[in] hash_nid hash NID, only SM3 is valid. + * @param[in] id_a The ID-A of the key exchange context. + * @param[in] id_a_size Size of ID-A key exchange context. + * @param[in] id_b The ID-B of the key exchange context. + * @param[in] id_b_size Size of ID-B key exchange context. + * @param[in] is_initiator If the caller is initiator. + * + * @retval true sm2 context is initialized. + * @retval false sm2 context is not initialized. + **/ +extern bool libspdm_sm2_key_exchange_init(const void *sm2_context, size_t hash_nid, + const uint8_t *id_a, size_t id_a_size, + const uint8_t *id_b, size_t id_b_size, + bool is_initiator); + +/** + * Generates sm2 key and returns sm2 public key (X, Y), based upon GB/T 32918.3-2016: SM2 - Part3. + * + * This function generates random secret, and computes the public key (X, Y), which is + * returned via parameter public, public_size. + * X is the first half of public with size being public_size / 2, + * Y is the second half of public with size being public_size / 2. + * sm2 context is updated accordingly. + * If the public buffer is too small to hold the public X, Y, false is returned and + * public_size is set to the required buffer size to obtain the public X, Y. + * + * The public_size is 64. first 32-byte is X, second 32-byte is Y. + * + * If sm2_context is NULL, then return false. + * If public_size is NULL, then return false. + * If public_size is large enough but public is NULL, then return false. + * + * @param[in, out] sm2_context Pointer to the sm2 context. + * @param[out] public_data Pointer to the buffer to receive generated public X,Y. + * @param[in, out] public_size On input, the size of public buffer in bytes. + * On output, the size of data returned in public buffer in bytes. + * + * @retval true sm2 public X,Y generation succeeded. + * @retval false sm2 public X,Y generation failed. + * @retval false public_size is not large enough. + **/ +extern bool libspdm_sm2_key_exchange_generate_key(void *sm2_context, uint8_t *public_data, + size_t *public_size); + +/** + * Computes exchanged common key, based upon GB/T 32918.3-2016: SM2 - Part3. + * + * Given peer's public key (X, Y), this function computes the exchanged common key, + * based on its own context including value of curve parameter and random secret. + * X is the first half of peer_public with size being peer_public_size / 2, + * Y is the second half of peer_public with size being peer_public_size / 2. + * + * If sm2_context is NULL, then return false. + * If peer_public is NULL, then return false. + * If peer_public_size is 0, then return false. + * If key is NULL, then return false. + * + * The id_a_size and id_b_size must be smaller than 2^16-1. + * The peer_public_size is 64. first 32-byte is X, second 32-byte is Y. + * The key_size must be smaller than 2^32-1, limited by KDF function. + * + * @param[in, out] sm2_context Pointer to the sm2 context. + * @param[in] peer_public Pointer to the peer's public X,Y. + * @param[in] peer_public_size Size of peer's public X,Y in bytes. + * @param[out] key Pointer to the buffer to receive generated key. + * @param[in] key_size On input, the size of key buffer in bytes. + * + * @retval true sm2 exchanged key generation succeeded. + * @retval false sm2 exchanged key generation failed. + **/ +extern bool libspdm_sm2_key_exchange_compute_key(void *sm2_context, + const uint8_t *peer_public, + size_t peer_public_size, uint8_t *key, + size_t *key_size); +#endif /* LIBSPDM_SM2_KEY_EXCHANGE_SUPPORT */ +#endif /* CRYPTLIB_SM2_H */ diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/libraries/libspdm/2.3.1/include/hal/library/cryptlib.h nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/libraries/libspdm/2.3.1/include/hal/library/cryptlib.h --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/libraries/libspdm/2.3.1/include/hal/library/cryptlib.h 1970-01-01 00:00:00.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/libraries/libspdm/2.3.1/include/hal/library/cryptlib.h 2024-03-05 22:14:10.000000000 +0000 @@ -0,0 +1,109 @@ +/** + * Copyright Notice: + * Copyright 2021-2022 DMTF. All rights reserved. + * License: BSD 3-Clause License. For full text see link: https://github.com/DMTF/libspdm/blob/main/LICENSE.md + **/ + +/** @file + * Defines base cryptographic library APIs. + * The Base Cryptographic Library provides implementations of basic cryptography + * primitives (hash Serials, HMAC, AES, RSA, Diffie-Hellman, Elliptic Curve, etc) for security + * functionality enabling. + **/ + +#ifndef CRYPTLIB_H +#define CRYPTLIB_H + +#include "internal/libspdm_lib_config.h" + +#define LIBSPDM_CRYPTO_NID_NULL 0x0000 + +/* Hash */ +#define LIBSPDM_CRYPTO_NID_SHA256 0x0001 +#define LIBSPDM_CRYPTO_NID_SHA384 0x0002 +#define LIBSPDM_CRYPTO_NID_SHA512 0x0003 +#define LIBSPDM_CRYPTO_NID_SHA3_256 0x0004 +#define LIBSPDM_CRYPTO_NID_SHA3_384 0x0005 +#define LIBSPDM_CRYPTO_NID_SHA3_512 0x0006 +#define LIBSPDM_CRYPTO_NID_SM3_256 0x0007 + +/* Signing */ +#define LIBSPDM_CRYPTO_NID_RSASSA2048 0x0101 +#define LIBSPDM_CRYPTO_NID_RSASSA3072 0x0102 +#define LIBSPDM_CRYPTO_NID_RSASSA4096 0x0103 +#define LIBSPDM_CRYPTO_NID_RSAPSS2048 0x0104 +#define LIBSPDM_CRYPTO_NID_RSAPSS3072 0x0105 +#define LIBSPDM_CRYPTO_NID_RSAPSS4096 0x0106 +#define LIBSPDM_CRYPTO_NID_ECDSA_NIST_P256 0x0107 +#define LIBSPDM_CRYPTO_NID_ECDSA_NIST_P384 0x0108 +#define LIBSPDM_CRYPTO_NID_ECDSA_NIST_P521 0x0109 +#define LIBSPDM_CRYPTO_NID_SM2_DSA_P256 0x010A +#define LIBSPDM_CRYPTO_NID_EDDSA_ED25519 0x010B +#define LIBSPDM_CRYPTO_NID_EDDSA_ED448 0x010C + +/* Key Exchange */ +#define LIBSPDM_CRYPTO_NID_FFDHE2048 0x0201 +#define LIBSPDM_CRYPTO_NID_FFDHE3072 0x0202 +#define LIBSPDM_CRYPTO_NID_FFDHE4096 0x0203 +#define LIBSPDM_CRYPTO_NID_SECP256R1 0x0204 +#define LIBSPDM_CRYPTO_NID_SECP384R1 0x0205 +#define LIBSPDM_CRYPTO_NID_SECP521R1 0x0206 +#define LIBSPDM_CRYPTO_NID_SM2_KEY_EXCHANGE_P256 0x0207 +#define LIBSPDM_CRYPTO_NID_CURVE_X25519 0x0208 +#define LIBSPDM_CRYPTO_NID_CURVE_X448 0x0209 + +/* AEAD */ +#define LIBSPDM_CRYPTO_NID_AES_128_GCM 0x0301 +#define LIBSPDM_CRYPTO_NID_AES_256_GCM 0x0302 +#define LIBSPDM_CRYPTO_NID_CHACHA20_POLY1305 0x0303 +#define LIBSPDM_CRYPTO_NID_SM4_128_GCM 0x0304 + +/* X.509 v3 key usage extension flags. */ +#define LIBSPDM_CRYPTO_X509_KU_DIGITAL_SIGNATURE 0x80 /* bit 0 */ +#define LIBSPDM_CRYPTO_X509_KU_NON_REPUDIATION 0x40 /* bit 1 */ +#define LIBSPDM_CRYPTO_X509_KU_KEY_ENCIPHERMENT 0x20 /* bit 2 */ +#define LIBSPDM_CRYPTO_X509_KU_DATA_ENCIPHERMENT 0x10 /* bit 3 */ +#define LIBSPDM_CRYPTO_X509_KU_KEY_AGREEMENT 0x08 /* bit 4 */ +#define LIBSPDM_CRYPTO_X509_KU_KEY_CERT_SIGN 0x04 /* bit 5 */ +#define LIBSPDM_CRYPTO_X509_KU_CRL_SIGN 0x02 /* bit 6 */ +#define LIBSPDM_CRYPTO_X509_KU_ENCIPHER_ONLY 0x01 /* bit 7 */ +#define LIBSPDM_CRYPTO_X509_KU_DECIPHER_ONLY 0x8000 /* bit 8 */ + +/* These constants comply with the DER encoded ASN.1 type tags. */ +#define LIBSPDM_CRYPTO_ASN1_BOOLEAN 0x01 +#define LIBSPDM_CRYPTO_ASN1_INTEGER 0x02 +#define LIBSPDM_CRYPTO_ASN1_BIT_STRING 0x03 +#define LIBSPDM_CRYPTO_ASN1_OCTET_STRING 0x04 +#define LIBSPDM_CRYPTO_ASN1_NULL 0x05 +#define LIBSPDM_CRYPTO_ASN1_OID 0x06 +#define LIBSPDM_CRYPTO_ASN1_UTF8_STRING 0x0C +#define LIBSPDM_CRYPTO_ASN1_SEQUENCE 0x10 +#define LIBSPDM_CRYPTO_ASN1_SET 0x11 +#define LIBSPDM_CRYPTO_ASN1_PRINTABLE_STRING 0x13 +#define LIBSPDM_CRYPTO_ASN1_T61_STRING 0x14 +#define LIBSPDM_CRYPTO_ASN1_IA5_STRING 0x16 +#define LIBSPDM_CRYPTO_ASN1_UTC_TIME 0x17 +#define LIBSPDM_CRYPTO_ASN1_GENERALIZED_TIME 0x18 +#define LIBSPDM_CRYPTO_ASN1_UNIVERSAL_STRING 0x1C +#define LIBSPDM_CRYPTO_ASN1_BMP_STRING 0x1E +#define LIBSPDM_CRYPTO_ASN1_PRIMITIVE 0x00 +#define LIBSPDM_CRYPTO_ASN1_CONSTRUCTED 0x20 +#define LIBSPDM_CRYPTO_ASN1_CONTEXT_SPECIFIC 0x80 + +#define LIBSPDM_CRYPTO_ASN1_TAG_CLASS_MASK 0xC0 +#define LIBSPDM_CRYPTO_ASN1_TAG_PC_MASK 0x20 +#define LIBSPDM_CRYPTO_ASN1_TAG_VALUE_MASK 0x1F + +#include "hal/library/cryptlib/cryptlib_hash.h" +#include "hal/library/cryptlib/cryptlib_mac.h" +#include "hal/library/cryptlib/cryptlib_aead.h" +#include "hal/library/cryptlib/cryptlib_cert.h" +#include "hal/library/cryptlib/cryptlib_hkdf.h" +#include "hal/library/cryptlib/cryptlib_rsa.h" +#include "hal/library/cryptlib/cryptlib_ec.h" +#include "hal/library/cryptlib/cryptlib_dh.h" +#include "hal/library/cryptlib/cryptlib_ecd.h" +#include "hal/library/cryptlib/cryptlib_sm2.h" +#include "hal/library/cryptlib/cryptlib_rng.h" + +#endif /* CRYPTLIB_H */ diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/libraries/libspdm/2.3.1/include/hal/library/debuglib.h nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/libraries/libspdm/2.3.1/include/hal/library/debuglib.h --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/libraries/libspdm/2.3.1/include/hal/library/debuglib.h 1970-01-01 00:00:00.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/libraries/libspdm/2.3.1/include/hal/library/debuglib.h 2024-03-05 22:14:12.000000000 +0000 @@ -0,0 +1,116 @@ +/** + * Copyright Notice: + * Copyright 2021-2022 DMTF. All rights reserved. + * License: BSD 3-Clause License. For full text see link: https://github.com/DMTF/libspdm/blob/main/LICENSE.md + **/ + +#ifndef DEBUG_LIB_H +#define DEBUG_LIB_H + +/** @file + * Provides services to print debug and assert messages to a debug output device. + * + * The debug library supports debug print and asserts based on a combination of macros and code. + * The debug library can be turned on and off so that the debug code does not increase the size of + * an image. + **/ + +#include "internal/libspdm_lib_config.h" + +#if LIBSPDM_DEBUG_PRINT_ENABLE + +/* Declare bits for the error_level parameter of libspdm_debug_print(). */ +#define LIBSPDM_DEBUG_INFO 0x00000040 +#define LIBSPDM_DEBUG_ERROR 0x80000000 + +/** + * Prints a debug message to the debug output device if the specified error level is enabled. + * + * @param error_level The error level of the debug message, either LIBSPDM_DEBUG_INFO or + * LIBSPDM_DEBUG_ERROR. + * @param format The format string for the debug message to print. + * @param ... The variable argument list whose contents are accessed + * based on the format string specified by format. + **/ +extern void libspdm_debug_print(size_t error_level, const char *format, ...); +#endif /* LIBSPDM_DEBUG_PRINT_ENABLE */ + +#if LIBSPDM_DEBUG_ASSERT_ENABLE +/** + * Prints an assert message containing a filename, line number, and description. + * This may be followed by a breakpoint or a dead loop. + * + * @param file_name The pointer to the name of the source file that generated the assert + * condition. + * @param line_number The line number in the source file that generated the assert condition + * @param description The pointer to the description of the assert condition. + * + **/ +extern void libspdm_debug_assert(const char *file_name, size_t line_number, + const char *description); +#endif /* LIBSPDM_DEBUG_ASSERT_ENABLE */ + +/** + * LIBSPDM_ASSERT(expression) - Macro that calls libspdm_debug_assert() if an expression evaluates + * to false. It is enabled through the LIBSPDM_DEBUG_ASSERT_ENABLE + * macro. + * + * @param expression Boolean expression. + **/ +#if LIBSPDM_DEBUG_ASSERT_ENABLE +#define LIBSPDM_ASSERT(expression) \ + do { \ + if (!(expression)) { \ + libspdm_debug_assert(__FILE__, __LINE__, #expression); \ + } \ + } while (false) +#else +#define LIBSPDM_ASSERT(expression) +#endif + +/** + * LIBSPDM_DEBUG(level, format_string, argument_list...) - Macro that calls libspdm_debug_print(). + * It is enabled through the + * LIBSPDM_PRINT_ENABLE macro. + * @param print_level Either LIBSPDM_DEBUG_INFO or LIBSPDM_DEBUG_ERROR. + * @param format_string Formatted string. + * @param argument_list List of arguments. + * + * Note that format_string and argument_list are the same as those defined by the C printf function. + **/ +#if LIBSPDM_DEBUG_PRINT_ENABLE +#define LIBSPDM_DEBUG(expression) \ + do { \ + LIBSPDM_DEBUG_INTERNAL(expression); \ + } while (false) + +#define LIBSPDM_DEBUG_PRINT_INTERNAL(print_level, ...) \ + do { \ + libspdm_debug_print(print_level, ## __VA_ARGS__); \ + } while (false) + +#define LIBSPDM_DEBUG_INTERNAL(expression) LIBSPDM_DEBUG_PRINT_INTERNAL expression +#else +#define LIBSPDM_DEBUG(expression) +#endif + +/** + * LIBSPDM_DEBUG_CODE(expression) - Macro that defines a section of debug source code. + * It is enabled through the LIBSPDM_BLOCK_ENABLE macro. + * + * @param expression One or more lines of expressions that are used for debugging and should not + * affect the behavior of functional code. + **/ +#if LIBSPDM_DEBUG_BLOCK_ENABLE +#define LIBSPDM_DEBUG_CODE(expression) \ + do { \ + uint8_t __debug_code_local; \ + expression \ + __debug_code_local = 0; \ + __debug_code_local++; \ + } while (false) +#else +#define LIBSPDM_DEBUG_CODE(expression) +#endif + +#endif /* DEBUG_LIB_H */ diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/libraries/libspdm/2.3.1/include/hal/library/memlib.h nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/libraries/libspdm/2.3.1/include/hal/library/memlib.h --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/libraries/libspdm/2.3.1/include/hal/library/memlib.h 1970-01-01 00:00:00.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/libraries/libspdm/2.3.1/include/hal/library/memlib.h 2024-03-05 22:14:12.000000000 +0000 @@ -0,0 +1,113 @@ +/** + * Copyright Notice: + * Copyright 2021-2022 DMTF. All rights reserved. + * License: BSD 3-Clause License. For full text see link: https://github.com/DMTF/libspdm/blob/main/LICENSE.md + **/ + +/** @file + * Provides copy memory, fill memory, zero memory, and GUID functions. + * + * The Base Memory Library provides optimized implementations for common memory-based operations. + * These functions should be used in place of coding your own loops to do equivalent common functions. + * This allows optimized library implementations to help increase performance. + **/ + +#ifndef BASE_MEMORY_LIB +#define BASE_MEMORY_LIB + +/** + * Copies bytes from a source buffer to a destination buffer. + * + * This function copies "src_len" bytes from "src_buf" to "dst_buf". + * + * Asserts and returns a non-zero value if any of the following are true: + * 1) "src_buf" or "dst_buf" are NULL. + * 2) "src_len" or "dst_len" is greater than (SIZE_MAX >> 1). + * 3) "src_len" is greater than "dst_len". + * 4) "src_buf" and "dst_buf" overlap. + * + * If any of these cases fail, a non-zero value is returned. Additionally if + * "dst_buf" points to a non-NULL value and "dst_len" is valid, then "dst_len" + * bytes of "dst_buf" are zeroed. + * + * This function follows the C11 cppreference description of memcpy_s. + * https://en.cppreference.com/w/c/string/byte/memcpy + * The cppreferece description does NOT allow the source or destination + * buffers to be NULL. + * + * This function differs from the Microsoft and Safeclib memcpy_s implementations + * in that the Microsoft and Safeclib implementations allow for NULL source and + * destinations pointers when the number of bytes to copy (src_len) is zero. + * + * In addition the Microsoft and Safeclib memcpy_s functions return different + * negative values on error. For best support, clients should generally check + * against zero for success or failure. + * + * @param dst_buf Destination buffer to copy to. + * @param dst_len Maximum length in bytes of the destination buffer. + * @param src_buf Source buffer to copy from. + * @param src_len The number of bytes to copy from the source buffer. + * + * @return 0 on success. non-zero on error. + * + **/ +int libspdm_copy_mem(void *dst_buf, size_t dst_len, + const void *src_buf, size_t src_len); + +/** + * Fills a target buffer with a byte value, and returns the target buffer. + * + * This function fills length bytes of buffer with value, and returns buffer. + * + * If length is greater than (MAX_ADDRESS - buffer + 1), then ASSERT(). + * + * @param buffer The memory to set. + * @param length The number of bytes to set. + * @param value The value with which to fill length bytes of buffer. + * + * @return buffer. + * + **/ +void *libspdm_set_mem(void *buffer, size_t length, uint8_t value); + +/** + * Fills a target buffer with zeros, and returns the target buffer. + * + * This function fills length bytes of buffer with zeros, and returns buffer. + * + * If length > 0 and buffer is NULL, then ASSERT(). + * If length is greater than (MAX_ADDRESS - buffer + 1), then ASSERT(). + * + * @param buffer The pointer to the target buffer to fill with zeros. + * @param length The number of bytes in buffer to fill with zeros. + * + * @return buffer. + * + **/ +void *libspdm_zero_mem(void *buffer, size_t length); + +/** + * Compares the contents of two buffers in const time. + * + * This function compares length bytes of source_buffer to length bytes of destination_buffer. + * If all length bytes of the two buffers are identical, then 0 is returned. Otherwise, the + * value returned is the first mismatched byte in source_buffer subtracted from the first + * mismatched byte in destination_buffer. + * + * If length > 0 and destination_buffer is NULL, then ASSERT(). + * If length > 0 and source_buffer is NULL, then ASSERT(). + * If length is greater than (MAX_ADDRESS - destination_buffer + 1), then ASSERT(). + * If length is greater than (MAX_ADDRESS - source_buffer + 1), then ASSERT(). + * + * @param destination_buffer A pointer to the destination buffer to compare. + * @param source_buffer A pointer to the source buffer to compare. + * @param length The number of bytes to compare. + * + * @return 0 All length bytes of the two buffers are identical. + * @retval Non-zero There is mismatched between source_buffer and destination_buffer. + * + **/ +int32_t libspdm_const_compare_mem(const void *destination_buffer, + const void *source_buffer, size_t length); + +#endif /* BASE_MEMORY_LIB */ diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/libraries/libspdm/2.3.1/include/hal/library/platform_lib.h nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/libraries/libspdm/2.3.1/include/hal/library/platform_lib.h --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/libraries/libspdm/2.3.1/include/hal/library/platform_lib.h 1970-01-01 00:00:00.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/libraries/libspdm/2.3.1/include/hal/library/platform_lib.h 2024-03-05 22:14:12.000000000 +0000 @@ -0,0 +1,57 @@ +/** + * Copyright Notice: + * Copyright 2022 DMTF. All rights reserved. + * License: BSD 3-Clause License. For full text see link: https://github.com/DMTF/libspdm/blob/main/LICENSE.md + **/ +#ifndef PLATFORM_LIB_H +#define PLATFORM_LIB_H + +#include "hal/base.h" +#include "internal/libspdm_lib_config.h" + +/** + * Suspends the execution of the current thread until the time-out interval elapses. + * This API is deprecated. Please use libspdm_sleep_in_us(). + * + * @param milliseconds The time interval for which execution is to be suspended, in milliseconds. + * + **/ +void libspdm_sleep(uint64_t milliseconds); + +/** + * Suspends the execution of the current thread until the time-out interval elapses. + * + * @param microseconds The time interval for which execution is to be suspended, in milliseconds. + * + **/ +void libspdm_sleep_in_us(uint64_t microseconds); + +#if LIBSPDM_ENABLE_CAPABILITY_HBEAT_CAP +/** + * If no heartbeat arrives in seconds, the watchdog timeout event + * should terminate the session. + * + * @param session_id Indicate the SPDM session ID. + * @param seconds heartbeat period, in seconds. + * + **/ +bool libspdm_start_watchdog(uint32_t session_id, uint16_t seconds); + +/** + * stop watchdog. + * + * @param session_id Indicate the SPDM session ID. + * + **/ +bool libspdm_stop_watchdog(uint32_t session_id); + +/** + * Reset the watchdog in heartbeat response. + * + * @param session_id Indicate the SPDM session ID. + * + **/ +bool libspdm_reset_watchdog(uint32_t session_id); +#endif /* LIBSPDM_ENABLE_CAPABILITY_HBEAT_CAP */ + +#endif /* PLATFORM_LIB_H */ diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/libraries/libspdm/2.3.1/include/industry_standard/spdm.h nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/libraries/libspdm/2.3.1/include/industry_standard/spdm.h --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/libraries/libspdm/2.3.1/include/industry_standard/spdm.h 1970-01-01 00:00:00.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/libraries/libspdm/2.3.1/include/industry_standard/spdm.h 2024-03-05 22:14:12.000000000 +0000 @@ -0,0 +1,992 @@ +/** + * Copyright Notice: + * Copyright 2021-2022 DMTF. All rights reserved. + * License: BSD 3-Clause License. For full text see link: https://github.com/DMTF/libspdm/blob/main/LICENSE.md + **/ + +/** @file + * Definitions of DSP0274 Security Protocol & data Model Specification (SPDM) + * version 1.2.0 in Distributed Management Task Force (DMTF). + **/ + +#ifndef SPDM_H +#define SPDM_H + +#pragma pack(1) + +/* 3 means SPDM spec 1.0, 1.1, 1.2 */ +#define SPDM_MAX_VERSION_COUNT 3 +#define SPDM_MAX_SLOT_COUNT 8 +#define SPDM_MAX_OPAQUE_DATA_SIZE 1024 + +#define SPDM_NONCE_SIZE 32 +#define SPDM_RANDOM_DATA_SIZE 32 + +/* SPDM response code (1.0) */ +#define SPDM_DIGESTS 0x01 +#define SPDM_CERTIFICATE 0x02 +#define SPDM_CHALLENGE_AUTH 0x03 +#define SPDM_VERSION 0x04 +#define SPDM_MEASUREMENTS 0x60 +#define SPDM_CAPABILITIES 0x61 +#define SPDM_ALGORITHMS 0x63 +#define SPDM_VENDOR_DEFINED_RESPONSE 0x7E +#define SPDM_ERROR 0x7F + +/* SPDM response code (1.1) */ +#define SPDM_KEY_EXCHANGE_RSP 0x64 +#define SPDM_FINISH_RSP 0x65 +#define SPDM_PSK_EXCHANGE_RSP 0x66 +#define SPDM_PSK_FINISH_RSP 0x67 +#define SPDM_HEARTBEAT_ACK 0x68 +#define SPDM_KEY_UPDATE_ACK 0x69 +#define SPDM_ENCAPSULATED_REQUEST 0x6A +#define SPDM_ENCAPSULATED_RESPONSE_ACK 0x6B +#define SPDM_END_SESSION_ACK 0x6C + +/* SPDM response code (1.2) */ +#define SPDM_CSR 0x6D +#define SPDM_SET_CERTIFICATE_RSP 0x6E +#define SPDM_CHUNK_SEND_ACK 0x05 +#define SPDM_CHUNK_RESPONSE 0x06 + +/* SPDM request code (1.0) */ +#define SPDM_GET_DIGESTS 0x81 +#define SPDM_GET_CERTIFICATE 0x82 +#define SPDM_CHALLENGE 0x83 +#define SPDM_GET_VERSION 0x84 +#define SPDM_GET_MEASUREMENTS 0xE0 +#define SPDM_GET_CAPABILITIES 0xE1 +#define SPDM_NEGOTIATE_ALGORITHMS 0xE3 +#define SPDM_VENDOR_DEFINED_REQUEST 0xFE +#define SPDM_RESPOND_IF_READY 0xFF + +/* SPDM request code (1.1) */ +#define SPDM_KEY_EXCHANGE 0xE4 +#define SPDM_FINISH 0xE5 +#define SPDM_PSK_EXCHANGE 0xE6 +#define SPDM_PSK_FINISH 0xE7 +#define SPDM_HEARTBEAT 0xE8 +#define SPDM_KEY_UPDATE 0xE9 +#define SPDM_GET_ENCAPSULATED_REQUEST 0xEA +#define SPDM_DELIVER_ENCAPSULATED_RESPONSE 0xEB +#define SPDM_END_SESSION 0xEC + +/* SPDM request code (1.2) */ +#define SPDM_GET_CSR 0xED +#define SPDM_SET_CERTIFICATE 0xEE +#define SPDM_CHUNK_SEND 0x85 +#define SPDM_CHUNK_GET 0x86 + +/* SPDM message header*/ +typedef struct { + uint8_t spdm_version; + uint8_t request_response_code; + uint8_t param1; + uint8_t param2; +} spdm_message_header_t; + +#define SPDM_MESSAGE_VERSION_10 0x10 +#define SPDM_MESSAGE_VERSION_11 0x11 +#define SPDM_MESSAGE_VERSION_12 0x12 +#define SPDM_MESSAGE_VERSION SPDM_MESSAGE_VERSION_10 + +/* SPDM GET_VERSION request */ +typedef struct { + spdm_message_header_t header; + /* param1 == RSVD + * param2 == RSVD*/ +} spdm_get_version_request_t; + + +/* SPDM GET_VERSION response */ +typedef struct { + spdm_message_header_t header; + /* param1 == RSVD + * param2 == RSVD*/ + uint8_t reserved; + uint8_t version_number_entry_count; + /*spdm_version_number_t version_number_entry[version_number_entry_count];*/ +} spdm_version_response_t; + +/* SPDM VERSION structure + * bit[15:12] major_version + * bit[11:8] minor_version + * bit[7:4] update_version_number + * bit[3:0] alpha*/ +typedef uint16_t spdm_version_number_t; +#define SPDM_VERSION_NUMBER_SHIFT_BIT 8 + +#define SPDM_VERSION_1_2_SIGNING_PREFIX_CONTEXT "dmtf-spdm-v1.2.*" +#define SPDM_VERSION_1_2_SIGNING_PREFIX_CONTEXT_SIZE \ + (sizeof(SPDM_VERSION_1_2_SIGNING_PREFIX_CONTEXT) - 1) +#define SPDM_VERSION_1_2_SIGNING_CONTEXT_SIZE 100 + +/* SPDM GET_CAPABILITIES request */ +typedef struct { + spdm_message_header_t header; + /* param1 == RSVD + * param2 == RSVD + * Below field is added in 1.1.*/ + uint8_t reserved; + uint8_t ct_exponent; + uint16_t reserved2; + uint32_t flags; + /* Below field is added in 1.2.*/ + uint32_t data_transfer_size; + uint32_t max_spdm_msg_size; +} spdm_get_capabilities_request_t; + +/* SPDM GET_CAPABILITIES response*/ + +typedef struct { + spdm_message_header_t header; + /* param1 == RSVD + * param2 == RSVD*/ + uint8_t reserved; + uint8_t ct_exponent; + uint16_t reserved2; + uint32_t flags; + /* Below field is added in 1.2.*/ + uint32_t data_transfer_size; + uint32_t max_spdm_msg_size; +} spdm_capabilities_response_t; + +#define SPDM_MIN_DATA_TRANSFER_SIZE_VERSION_12 42 + +/* SPDM GET_CAPABILITIES request flags (1.1) */ +#define SPDM_GET_CAPABILITIES_REQUEST_FLAGS_CERT_CAP 0x00000002 +#define SPDM_GET_CAPABILITIES_REQUEST_FLAGS_CHAL_CAP 0x00000004 +#define SPDM_GET_CAPABILITIES_REQUEST_FLAGS_ENCRYPT_CAP 0x00000040 +#define SPDM_GET_CAPABILITIES_REQUEST_FLAGS_MAC_CAP 0x00000080 +#define SPDM_GET_CAPABILITIES_REQUEST_FLAGS_MUT_AUTH_CAP 0x00000100 +#define SPDM_GET_CAPABILITIES_REQUEST_FLAGS_KEY_EX_CAP 0x00000200 +#define SPDM_GET_CAPABILITIES_REQUEST_FLAGS_PSK_CAP (0x00000400 | 0x00000800) +#define SPDM_GET_CAPABILITIES_REQUEST_FLAGS_PSK_CAP_REQUESTER 0x00000400 +#define SPDM_GET_CAPABILITIES_REQUEST_FLAGS_ENCAP_CAP 0x00001000 +#define SPDM_GET_CAPABILITIES_REQUEST_FLAGS_HBEAT_CAP 0x00002000 +#define SPDM_GET_CAPABILITIES_REQUEST_FLAGS_KEY_UPD_CAP 0x00004000 +#define SPDM_GET_CAPABILITIES_REQUEST_FLAGS_HANDSHAKE_IN_THE_CLEAR_CAP 0x00008000 +#define SPDM_GET_CAPABILITIES_REQUEST_FLAGS_PUB_KEY_ID_CAP 0x00010000 + +/* SPDM GET_CAPABILITIES request flags (1.2) */ +#define SPDM_GET_CAPABILITIES_REQUEST_FLAGS_CHUNK_CAP 0x00020000 + +/* SPDM GET_CAPABILITIES response flags (1.0) */ +#define SPDM_GET_CAPABILITIES_RESPONSE_FLAGS_CACHE_CAP 0x00000001 +#define SPDM_GET_CAPABILITIES_RESPONSE_FLAGS_CERT_CAP 0x00000002 +#define SPDM_GET_CAPABILITIES_RESPONSE_FLAGS_CHAL_CAP 0x00000004 +#define SPDM_GET_CAPABILITIES_RESPONSE_FLAGS_MEAS_CAP (0x00000008 | 0x00000010) +#define SPDM_GET_CAPABILITIES_RESPONSE_FLAGS_MEAS_CAP_NO_SIG 0x00000008 +#define SPDM_GET_CAPABILITIES_RESPONSE_FLAGS_MEAS_CAP_SIG 0x00000010 +#define SPDM_GET_CAPABILITIES_RESPONSE_FLAGS_MEAS_FRESH_CAP 0x00000020 + +/* SPDM GET_CAPABILITIES response flags (1.1) */ +#define SPDM_GET_CAPABILITIES_RESPONSE_FLAGS_ENCRYPT_CAP 0x00000040 +#define SPDM_GET_CAPABILITIES_RESPONSE_FLAGS_MAC_CAP 0x00000080 +#define SPDM_GET_CAPABILITIES_RESPONSE_FLAGS_MUT_AUTH_CAP 0x00000100 +#define SPDM_GET_CAPABILITIES_RESPONSE_FLAGS_KEY_EX_CAP 0x00000200 +#define SPDM_GET_CAPABILITIES_RESPONSE_FLAGS_PSK_CAP (0x00000400 | 0x00000800) +#define SPDM_GET_CAPABILITIES_RESPONSE_FLAGS_PSK_CAP_RESPONDER 0x00000400 +#define SPDM_GET_CAPABILITIES_RESPONSE_FLAGS_PSK_CAP_RESPONDER_WITH_CONTEXT 0x00000800 +#define SPDM_GET_CAPABILITIES_RESPONSE_FLAGS_ENCAP_CAP 0x00001000 +#define SPDM_GET_CAPABILITIES_RESPONSE_FLAGS_HBEAT_CAP 0x00002000 +#define SPDM_GET_CAPABILITIES_RESPONSE_FLAGS_KEY_UPD_CAP 0x00004000 +#define SPDM_GET_CAPABILITIES_RESPONSE_FLAGS_HANDSHAKE_IN_THE_CLEAR_CAP 0x00008000 +#define SPDM_GET_CAPABILITIES_RESPONSE_FLAGS_PUB_KEY_ID_CAP 0x00010000 + +/* SPDM GET_CAPABILITIES request flags (1.2) */ +#define SPDM_GET_CAPABILITIES_RESPONSE_FLAGS_CHUNK_CAP 0x00020000 +#define SPDM_GET_CAPABILITIES_RESPONSE_FLAGS_ALIAS_CERT_CAP 0x00040000 + +/* SPDM GET_CAPABILITIES response flags (1.2.1)*/ +#define SPDM_GET_CAPABILITIES_RESPONSE_FLAGS_SET_CERT_CAP 0x00080000 +#define SPDM_GET_CAPABILITIES_RESPONSE_FLAGS_CSR_CAP 0x00100000 +#define SPDM_GET_CAPABILITIES_RESPONSE_FLAGS_CERT_INSTALL_RESET_CAP 0x00200000 + +/* SPDM NEGOTIATE_ALGORITHMS request */ +typedef struct { + spdm_message_header_t header; + /* param1 == Number of Algorithms Structure Tables + * param2 == RSVD*/ + uint16_t length; + uint8_t measurement_specification; + /* other_params_support is added in 1.2. + * BIT[0:3]=opaque_data_format support, BIT[4:7]=reserved*/ + uint8_t other_params_support; + uint32_t base_asym_algo; + uint32_t base_hash_algo; + uint8_t reserved2[12]; + uint8_t ext_asym_count; + uint8_t ext_hash_count; + uint16_t reserved3; + /*spdm_extended_algorithm_t ext_asym[ext_asym_count]; + * spdm_extended_algorithm_t ext_hash[ext_hash_count]; + * Below field is added in 1.1. + * spdm_negotiate_algorithms_struct_table_t alg_struct[param1];*/ +} spdm_negotiate_algorithms_request_t; + +#define SPDM_NEGOTIATE_ALGORITHMS_REQUEST_MAX_LENGTH_VERSION_10 0x40 +#define SPDM_NEGOTIATE_ALGORITHMS_REQUEST_MAX_LENGTH_VERSION_11 0x80 +#define SPDM_NEGOTIATE_ALGORITHMS_REQUEST_MAX_LENGTH_VERSION_12 0x80 +#define SPDM_NEGOTIATE_ALGORITHMS_REQUEST_MAX_EXT_ALG_COUNT_VERSION_10 0x08 +#define SPDM_NEGOTIATE_ALGORITHMS_REQUEST_MAX_EXT_ALG_COUNT_VERSION_11 0x14 +#define SPDM_NEGOTIATE_ALGORITHMS_REQUEST_MAX_EXT_ALG_COUNT_VERSION_12 0x14 + +typedef struct { + uint8_t alg_type; + uint8_t alg_count; /* BIT[0:3]=ext_alg_count, BIT[4:7]=fixed_alg_byte_count*/ + /*uint8_t alg_supported[fixed_alg_byte_count]; + * uint32_t alg_external[ext_alg_count];*/ +} spdm_negotiate_algorithms_struct_table_t; + +#define SPDM_NEGOTIATE_ALGORITHMS_STRUCT_TABLE_ALG_TYPE_DHE 2 +#define SPDM_NEGOTIATE_ALGORITHMS_STRUCT_TABLE_ALG_TYPE_AEAD 3 +#define SPDM_NEGOTIATE_ALGORITHMS_STRUCT_TABLE_ALG_TYPE_REQ_BASE_ASYM_ALG 4 +#define SPDM_NEGOTIATE_ALGORITHMS_STRUCT_TABLE_ALG_TYPE_KEY_SCHEDULE 5 + +typedef struct { + uint8_t alg_type; + uint8_t alg_count; + uint16_t alg_supported; +} spdm_negotiate_algorithms_common_struct_table_t; + + +/* SPDM NEGOTIATE_ALGORITHMS request base_asym_algo/REQ_BASE_ASYM_ALG */ +#define SPDM_ALGORITHMS_BASE_ASYM_ALGO_TPM_ALG_RSASSA_2048 0x00000001 +#define SPDM_ALGORITHMS_BASE_ASYM_ALGO_TPM_ALG_RSAPSS_2048 0x00000002 +#define SPDM_ALGORITHMS_BASE_ASYM_ALGO_TPM_ALG_RSASSA_3072 0x00000004 +#define SPDM_ALGORITHMS_BASE_ASYM_ALGO_TPM_ALG_RSAPSS_3072 0x00000008 +#define SPDM_ALGORITHMS_BASE_ASYM_ALGO_TPM_ALG_ECDSA_ECC_NIST_P256 0x00000010 +#define SPDM_ALGORITHMS_BASE_ASYM_ALGO_TPM_ALG_RSASSA_4096 0x00000020 +#define SPDM_ALGORITHMS_BASE_ASYM_ALGO_TPM_ALG_RSAPSS_4096 0x00000040 +#define SPDM_ALGORITHMS_BASE_ASYM_ALGO_TPM_ALG_ECDSA_ECC_NIST_P384 0x00000080 +#define SPDM_ALGORITHMS_BASE_ASYM_ALGO_TPM_ALG_ECDSA_ECC_NIST_P521 0x00000100 + +/* SPDM NEGOTIATE_ALGORITHMS request base_asym_algo/REQ_BASE_ASYM_ALG (1.2) */ +#define SPDM_ALGORITHMS_BASE_ASYM_ALGO_TPM_ALG_SM2_ECC_SM2_P256 0x00000200 +#define SPDM_ALGORITHMS_BASE_ASYM_ALGO_EDDSA_ED25519 0x00000400 +#define SPDM_ALGORITHMS_BASE_ASYM_ALGO_EDDSA_ED448 0x00000800 + +/* SPDM NEGOTIATE_ALGORITHMS request base_hash_algo */ +#define SPDM_ALGORITHMS_BASE_HASH_ALGO_TPM_ALG_SHA_256 0x00000001 +#define SPDM_ALGORITHMS_BASE_HASH_ALGO_TPM_ALG_SHA_384 0x00000002 +#define SPDM_ALGORITHMS_BASE_HASH_ALGO_TPM_ALG_SHA_512 0x00000004 +#define SPDM_ALGORITHMS_BASE_HASH_ALGO_TPM_ALG_SHA3_256 0x00000008 +#define SPDM_ALGORITHMS_BASE_HASH_ALGO_TPM_ALG_SHA3_384 0x00000010 +#define SPDM_ALGORITHMS_BASE_HASH_ALGO_TPM_ALG_SHA3_512 0x00000020 + +/* SPDM NEGOTIATE_ALGORITHMS request base_hash_algo (1.2) */ +#define SPDM_ALGORITHMS_BASE_HASH_ALGO_TPM_ALG_SM3_256 0x00000040 + +/* SPDM NEGOTIATE_ALGORITHMS request DHE */ +#define SPDM_ALGORITHMS_DHE_NAMED_GROUP_FFDHE_2048 0x00000001 +#define SPDM_ALGORITHMS_DHE_NAMED_GROUP_FFDHE_3072 0x00000002 +#define SPDM_ALGORITHMS_DHE_NAMED_GROUP_FFDHE_4096 0x00000004 +#define SPDM_ALGORITHMS_DHE_NAMED_GROUP_SECP_256_R1 0x00000008 +#define SPDM_ALGORITHMS_DHE_NAMED_GROUP_SECP_384_R1 0x00000010 +#define SPDM_ALGORITHMS_DHE_NAMED_GROUP_SECP_521_R1 0x00000020 + +/* SPDM NEGOTIATE_ALGORITHMS request DHE (1.2) */ +#define SPDM_ALGORITHMS_DHE_NAMED_GROUP_SM2_P256 0x00000040 + +/* SPDM NEGOTIATE_ALGORITHMS request AEAD */ +#define SPDM_ALGORITHMS_AEAD_CIPHER_SUITE_AES_128_GCM 0x00000001 +#define SPDM_ALGORITHMS_AEAD_CIPHER_SUITE_AES_256_GCM 0x00000002 +#define SPDM_ALGORITHMS_AEAD_CIPHER_SUITE_CHACHA20_POLY1305 0x00000004 + +/* SPDM NEGOTIATE_ALGORITHMS request AEAD (1.2) */ +#define SPDM_ALGORITHMS_AEAD_CIPHER_SUITE_AEAD_SM4_GCM 0x00000008 + +/* SPDM NEGOTIATE_ALGORITHMS request KEY_SCHEDULE */ +#define SPDM_ALGORITHMS_KEY_SCHEDULE_HMAC_HASH 0x00000001 + +/* SPDM NEGOTIATE_ALGORITHMS response */ +typedef struct { + spdm_message_header_t header; + /* param1 == Number of Algorithms Structure Tables + * param2 == RSVD*/ + uint16_t length; + uint8_t measurement_specification_sel; + /* other_params_selection is added in 1.2. + * BIT[0:3]=opaque_data_format select, BIT[4:7]=reserved*/ + uint8_t other_params_selection; + uint32_t measurement_hash_algo; + uint32_t base_asym_sel; + uint32_t base_hash_sel; + uint8_t reserved2[12]; + uint8_t ext_asym_sel_count; + uint8_t ext_hash_sel_count; + uint16_t reserved3; + /*spdm_extended_algorithm_t ext_asym_sel[ext_asym_sel_count]; + * spdm_extended_algorithm_t ext_hash_sel[ext_hash_sel_count]; + * Below field is added in 1.1. + * spdm_negotiate_algorithms_struct_table_t alg_struct[param1];*/ +} spdm_algorithms_response_t; + +/* SPDM NEGOTIATE_ALGORITHMS response measurement_hash_algo */ +#define SPDM_ALGORITHMS_MEASUREMENT_HASH_ALGO_RAW_BIT_STREAM_ONLY 0x00000001 +#define SPDM_ALGORITHMS_MEASUREMENT_HASH_ALGO_TPM_ALG_SHA_256 0x00000002 +#define SPDM_ALGORITHMS_MEASUREMENT_HASH_ALGO_TPM_ALG_SHA_384 0x00000004 +#define SPDM_ALGORITHMS_MEASUREMENT_HASH_ALGO_TPM_ALG_SHA_512 0x00000008 +#define SPDM_ALGORITHMS_MEASUREMENT_HASH_ALGO_TPM_ALG_SHA3_256 0x00000010 +#define SPDM_ALGORITHMS_MEASUREMENT_HASH_ALGO_TPM_ALG_SHA3_384 0x00000020 +#define SPDM_ALGORITHMS_MEASUREMENT_HASH_ALGO_TPM_ALG_SHA3_512 0x00000040 + +/* SPDM NEGOTIATE_ALGORITHMS response measurement_hash_algo (1.2) */ +#define SPDM_ALGORITHMS_MEASUREMENT_HASH_ALGO_TPM_ALG_SM3_256 0x00000080 + +/* SPDM Opaque Data Format (1.2) */ +#define SPDM_ALGORITHMS_OPAQUE_DATA_FORMAT_0 0x00000001 +#define SPDM_ALGORITHMS_OPAQUE_DATA_FORMAT_1 0x00000002 +#define SPDM_ALGORITHMS_OPAQUE_DATA_FORMAT_MASK 0xF + +/* SPDM Opaque Data Format 1 (1.2) */ +typedef struct { + uint8_t total_elements; + uint8_t reserved[3]; + /*opaque_element_table_t opaque_list[];*/ +} spdm_general_opaque_data_table_header_t; + +/* SPDM extended algorithm */ +typedef struct { + uint8_t registry_id; + uint8_t reserved; + uint16_t algorithm_id; +} spdm_extended_algorithm_t; + +/* SPDM registry_id */ +#define SPDM_REGISTRY_ID_DMTF 0 +#define SPDM_REGISTRY_ID_TCG 1 +#define SPDM_REGISTRY_ID_USB 2 +#define SPDM_REGISTRY_ID_PCISIG 3 +#define SPDM_REGISTRY_ID_IANA 4 +#define SPDM_REGISTRY_ID_HDBASET 5 +#define SPDM_REGISTRY_ID_MIPI 6 +#define SPDM_REGISTRY_ID_CXL 7 +#define SPDM_REGISTRY_ID_JEDEC 8 + +/* SPDM GET_DIGESTS request */ +typedef struct { + spdm_message_header_t header; + /* param1 == RSVD + * param2 == RSVD*/ +} spdm_get_digest_request_t; + +/* SPDM GET_DIGESTS response */ +typedef struct { + spdm_message_header_t header; + /* param1 == RSVD + * param2 == slot_mask + * uint8_t digest[digest_size][slot_count];*/ +} spdm_digest_response_t; + + +/* SPDM GET_CERTIFICATE request */ +typedef struct { + spdm_message_header_t header; + /* param1 == BIT[0:3]=slot_id, BIT[4:7]=RSVD + * param2 == RSVD*/ + uint16_t offset; + uint16_t length; +} spdm_get_certificate_request_t; + +#define SPDM_GET_CERTIFICATE_REQUEST_SLOT_ID_MASK 0xF + +/* SPDM GET_CERTIFICATE response */ +typedef struct { + spdm_message_header_t header; + /* param1 == BIT[0:3]=slot_id, BIT[4:7]=RSVD + * param2 == RSVD*/ + uint16_t portion_length; + uint16_t remainder_length; + /*uint8_t cert_chain[portion_length];*/ +} spdm_certificate_response_t; + +#define SPDM_CERTIFICATE_RESPONSE_SLOT_ID_MASK 0xF +typedef struct { + /* Total length of the certificate chain, in bytes, + * including all fields in this table.*/ + + uint16_t length; + uint16_t reserved; + + /* digest of the Root Certificate. + * Note that Root Certificate is ASN.1 DER-encoded for this digest. + * The hash size is determined by the SPDM device.*/ + + /*uint8_t root_hash[hash_size];*/ + + /* One or more ASN.1 DER-encoded X509v3 certificates where the first certificate is signed by the Root + * Certificate or is the Root Certificate itself and each subsequent certificate is signed by the preceding + * certificate. The last certificate is the Leaf Certificate.*/ + + /*uint8_t certificates[length - 4 - hash_size];*/ +} spdm_cert_chain_t; + +/* SPDM CHALLENGE request */ +typedef struct { + spdm_message_header_t header; + /* param1 == slot_id + * param2 == HashType*/ + uint8_t nonce[32]; +} spdm_challenge_request_t; + +/* SPDM CHALLENGE response */ +typedef struct { + spdm_message_header_t header; + /* param1 == ResponseAttribute, BIT[0:3]=slot_id, BIT[4:6]=RSVD, BIT[7]=basic_mut_auth(deprecated in 1.2) + * param2 == slot_mask + * uint8_t cert_chain_hash[digest_size]; + * uint8_t nonce[32]; + * uint8_t measurement_summary_hash[digest_size]; + * uint16_t opaque_length; + * uint8_t opaque_data[opaque_length]; + * uint8_t signature[key_size];*/ +} spdm_challenge_auth_response_t; + +/* SPDM CHALLENGE request HashType */ +#define SPDM_CHALLENGE_REQUEST_NO_MEASUREMENT_SUMMARY_HASH 0 +#define SPDM_CHALLENGE_REQUEST_TCB_COMPONENT_MEASUREMENT_HASH 1 +#define SPDM_CHALLENGE_REQUEST_ALL_MEASUREMENTS_HASH 0xFF + +#define SPDM_CHALLENGE_AUTH_RESPONSE_ATTRIBUTE_SLOT_ID_MASK 0xF +#define SPDM_CHALLENGE_AUTH_RESPONSE_ATTRIBUTE_BASIC_MUT_AUTH_REQ 0x00000080 /* Deprecated in SPDM 1.2*/ + +#define SPDM_CHALLENGE_AUTH_SIGN_CONTEXT "responder-challenge_auth signing" +#define SPDM_CHALLENGE_AUTH_SIGN_CONTEXT_SIZE (sizeof(SPDM_CHALLENGE_AUTH_SIGN_CONTEXT) - 1) +#define SPDM_MUT_CHALLENGE_AUTH_SIGN_CONTEXT "requester-challenge_auth signing" +#define SPDM_MUT_CHALLENGE_AUTH_SIGN_CONTEXT_SIZE (sizeof(SPDM_MUT_CHALLENGE_AUTH_SIGN_CONTEXT) - 1) + +/* SPDM GET_MEASUREMENTS request */ +typedef struct { + spdm_message_header_t header; + /* param1 == Attributes + * param2 == measurement_operation*/ + uint8_t nonce[32]; + /* Below field is added in 1.1.*/ + uint8_t slot_id_param; /* BIT[0:3]=slot_id, BIT[4:7]=RSVD*/ +} spdm_get_measurements_request_t; + +#define SPDM_GET_MEASUREMENTS_REQUEST_SLOT_ID_MASK 0xF + +/* SPDM GET_MEASUREMENTS request Attributes */ +#define SPDM_GET_MEASUREMENTS_REQUEST_ATTRIBUTES_GENERATE_SIGNATURE 0x00000001 +#define SPDM_GET_MEASUREMENTS_REQUEST_ATTRIBUTES_RAW_BIT_STREAM_REQUESTED 0x00000002 + +/* SPDM GET_MEASUREMENTS request measurement_operation */ +#define SPDM_GET_MEASUREMENTS_REQUEST_MEASUREMENT_OPERATION_TOTAL_NUMBER_OF_MEASUREMENTS 0 + +/*SPDM_GET_MEASUREMENTS_REQUEST_MEASUREMENT_OPERATION_INDEX */ +#define SPDM_GET_MEASUREMENTS_REQUEST_MEASUREMENT_OPERATION_ALL_MEASUREMENTS 0xFF + + +/* SPDM MEASUREMENTS block common header */ +typedef struct { + uint8_t index; + uint8_t measurement_specification; + uint16_t measurement_size; + /*uint8_t measurement[measurement_size];*/ +} spdm_measurement_block_common_header_t; + +#define SPDM_MEASUREMENT_BLOCK_HEADER_SPECIFICATION_DMTF 0x00000001 + +/* SPDM MEASUREMENTS block DMTF header */ +typedef struct { + uint8_t dmtf_spec_measurement_value_type; + uint16_t dmtf_spec_measurement_value_size; + /*uint8_t Dmtf_spec_measurement_value[dmtf_spec_measurement_value_size];*/ +} spdm_measurement_block_dmtf_header_t; + +typedef struct { + spdm_measurement_block_common_header_t measurement_block_common_header; + spdm_measurement_block_dmtf_header_t measurement_block_dmtf_header; + /*uint8_t hash_value[hash_size];*/ +} spdm_measurement_block_dmtf_t; + +/* SPDM MEASUREMENTS block MeasurementValueType */ +#define SPDM_MEASUREMENT_BLOCK_MEASUREMENT_TYPE_IMMUTABLE_ROM 0 +#define SPDM_MEASUREMENT_BLOCK_MEASUREMENT_TYPE_MUTABLE_FIRMWARE 1 +#define SPDM_MEASUREMENT_BLOCK_MEASUREMENT_TYPE_HARDWARE_CONFIGURATION 2 +#define SPDM_MEASUREMENT_BLOCK_MEASUREMENT_TYPE_FIRMWARE_CONFIGURATION 3 +#define SPDM_MEASUREMENT_BLOCK_MEASUREMENT_TYPE_MEASUREMENT_MANIFEST 4 +#define SPDM_MEASUREMENT_BLOCK_MEASUREMENT_TYPE_DEVICE_MODE 5 +#define SPDM_MEASUREMENT_BLOCK_MEASUREMENT_TYPE_VERSION 6 +#define SPDM_MEASUREMENT_BLOCK_MEASUREMENT_TYPE_SECURE_VERSION_NUMBER 7 +#define SPDM_MEASUREMENT_BLOCK_MEASUREMENT_TYPE_MASK 0x7 +#define SPDM_MEASUREMENT_BLOCK_MEASUREMENT_TYPE_RAW_BIT_STREAM 0x00000080 + +/* SPDM MEASUREMENTS block index */ +#define SPDM_MEASUREMENT_BLOCK_MEASUREMENT_INDEX_MEASUREMENT_MANIFEST 0xFD +#define SPDM_MEASUREMENT_BLOCK_MEASUREMENT_INDEX_DEVICE_MODE 0xFE + +/* SPDM MEASUREMENTS device mode */ +typedef struct { + uint32_t operational_mode_capabilties; + uint32_t operational_mode_state; + uint32_t device_mode_capabilties; + uint32_t device_mode_state; +} spdm_measurements_device_mode_t; + +#define SPDM_MEASUREMENT_DEVICE_OPERATION_MODE_MANUFACTURING_MODE 0x00000001 +#define SPDM_MEASUREMENT_DEVICE_OPERATION_MODE_VALIDATION_MODE 0x00000002 +#define SPDM_MEASUREMENT_DEVICE_OPERATION_MODE_NORMAL_MODE 0x00000004 +#define SPDM_MEASUREMENT_DEVICE_OPERATION_MODE_RECOVERY_MODE 0x00000008 +#define SPDM_MEASUREMENT_DEVICE_OPERATION_MODE_RMA_MODE 0x00000010 +#define SPDM_MEASUREMENT_DEVICE_OPERATION_MODE_DECOMMISSIONED_MODE 0x00000020 + +#define SPDM_MEASUREMENT_DEVICE_MODE_NON_INVASIVE_DEBUG_MODE_IS_ACTIVE 0x00000001 +#define SPDM_MEASUREMENT_DEVICE_MODE_INVASIVE_DEBUG_MODE_IS_ACTIVE 0x00000002 +#define SPDM_MEASUREMENT_DEVICE_MODE_NON_INVASIVE_DEBUG_MODE_HAS_BEEN_ACTIVE 0x00000004 +#define SPDM_MEASUREMENT_DEVICE_MODE_INVASIVE_DEBUG_MODE_HAS_BEEN_ACTIVE 0x00000008 +#define SPDM_MEASUREMENT_DEVICE_MODE_INVASIVE_DEBUG_MODE_HAS_BEEN_ACTIVE_AFTER_MFG 0x00000010 + +/* SPDM MEASUREMENTS SVN */ +typedef uint64_t spdm_measurements_secure_version_number_t; + +/* SPDM GET_MEASUREMENTS response */ +typedef struct { + spdm_message_header_t header; + /* param1 == TotalNumberOfMeasurement/RSVD + * param2 == BIT[0:3]=slot_id, BIT[4:5]=content changed, BIT[6:7]=RSVD*/ + uint8_t number_of_blocks; + uint8_t measurement_record_length[3]; + /*uint8_t measurement_record[measurement_record_length]; + * uint8_t nonce[32]; + * uint16_t opaque_length; + * uint8_t opaque_data[opaque_length]; + * uint8_t signature[key_size];*/ +} spdm_measurements_response_t; + +#define SPDM_MEASUREMENTS_RESPONSE_SLOT_ID_MASK 0xF + +/* SPDM MEASUREMENTS content changed */ +#define SPDM_MEASUREMENTS_RESPONSE_CONTENT_CHANGE_MASK 0x30 +#define SPDM_MEASUREMENTS_RESPONSE_CONTENT_CHANGE_NO_DETECTION 0x00 +#define SPDM_MEASUREMENTS_RESPONSE_CONTENT_CHANGE_DETECTED 0x10 +#define SPDM_MEASUREMENTS_RESPONSE_CONTENT_NO_CHANGE_DETECTED 0x20 + +#define SPDM_MEASUREMENTS_SIGN_CONTEXT "responder-measurements signing" +#define SPDM_MEASUREMENTS_SIGN_CONTEXT_SIZE (sizeof(SPDM_MEASUREMENTS_SIGN_CONTEXT) - 1) + +/* SPDM ERROR response */ +typedef struct { + spdm_message_header_t header; + /* param1 == Error Code + * param2 == Error data + * uint8_t extended_error_data[32];*/ +} spdm_error_response_t; + +#define SPDM_EXTENDED_ERROR_DATA_MAX_SIZE 32 + +/* SPDM error code */ +#define SPDM_ERROR_CODE_INVALID_REQUEST 0x01 +#define SPDM_ERROR_CODE_BUSY 0x03 +#define SPDM_ERROR_CODE_UNEXPECTED_REQUEST 0x04 +#define SPDM_ERROR_CODE_UNSPECIFIED 0x05 +#define SPDM_ERROR_CODE_UNSUPPORTED_REQUEST 0x07 +#define SPDM_ERROR_CODE_VERSION_MISMATCH 0x41 +#define SPDM_ERROR_CODE_RESPONSE_NOT_READY 0x42 +#define SPDM_ERROR_CODE_REQUEST_RESYNCH 0x43 +#define SPDM_ERROR_CODE_VENDOR_DEFINED 0xFF + +/* SPDM error code (1.1) */ +#define SPDM_ERROR_CODE_INVALID_SESSION 0x02 /* Deprecated in SPDM 1.2*/ +#define SPDM_ERROR_CODE_DECRYPT_ERROR 0x06 +#define SPDM_ERROR_CODE_REQUEST_IN_FLIGHT 0x08 +#define SPDM_ERROR_CODE_INVALID_RESPONSE_CODE 0x09 +#define SPDM_ERROR_CODE_SESSION_LIMIT_EXCEEDED 0x0A + +/* SPDM error code (1.2) */ +#define SPDM_ERROR_CODE_SESSION_REQUIRED 0x0B +#define SPDM_ERROR_CODE_RESET_REQUIRED 0x0C +#define SPDM_ERROR_CODE_RESPONSE_TOO_LARGE 0x0D +#define SPDM_ERROR_CODE_REQUEST_TOO_LARGE 0x0E +#define SPDM_ERROR_CODE_LARGE_RESPONSE 0x0F +#define SPDM_ERROR_CODE_MESSAGE_LOST 0x10 + +/* SPDM ResponseNotReady extended data */ +typedef struct { + uint8_t rd_exponent; + uint8_t request_code; + uint8_t token; + uint8_t rd_tm; +} spdm_error_data_response_not_ready_t; + +typedef struct { + spdm_message_header_t header; + /* param1 == Error Code + * param2 == Error data*/ + spdm_error_data_response_not_ready_t extend_error_data; +} spdm_error_response_data_response_not_ready_t; + +/* SPDM LargeResponse extended data */ +typedef struct { + uint8_t handle; +} spdm_error_data_large_response_t; + +typedef struct { + spdm_message_header_t header; + /* param1 == Error Code + * param2 == Error data*/ + spdm_error_data_large_response_t extend_error_data; +} spdm_error_response_large_response_t; + +/* SPDM RESPONSE_IF_READY request */ +typedef struct { + spdm_message_header_t header; + /* param1 == request_code + * param2 == token*/ +} spdm_response_if_ready_request_t; + +/* SPDM VENDOR_DEFINED request */ +typedef struct { + spdm_message_header_t header; + /* param1 == RSVD + * param2 == RSVD*/ + uint16_t standard_id; + uint8_t len; + /*uint8_t vendor_id[len]; + * uint16_t payload_length; + * uint8_t vendor_defined_payload[payload_length];*/ +} spdm_vendor_defined_request_msg_t; + +/* SPDM VENDOR_DEFINED response */ +typedef struct { + spdm_message_header_t header; + /* param1 == RSVD + * param2 == RSVD*/ + uint16_t standard_id; + uint8_t len; + /*uint8_t vendor_id[len]; + * uint16_t payload_length; + * uint8_t vendor_defined_payload[payload_length];*/ +} spdm_vendor_defined_response_msg_t; + +/* Below command is defined in SPDM 1.1 */ + +/* SPDM KEY_EXCHANGE request */ +typedef struct { + spdm_message_header_t header; + /* param1 == HashType + * param2 == slot_id*/ + uint16_t req_session_id; + /* session_policy is added in 1.2.*/ + uint8_t session_policy; + uint8_t reserved; + uint8_t random_data[32]; + /*uint8_t exchange_data[D]; + * uint16_t opaque_length; + * uint8_t opaque_data[opaque_length];*/ +} spdm_key_exchange_request_t; + +/* SPDM KEY_EXCHANGE request session_policy */ +#define SPDM_KEY_EXCHANGE_REQUEST_SESSION_POLICY_TERMINATION_POLICY_RUNTIME_UPDATE 0x00000001 + +/* SPDM KEY_EXCHANGE request HashType */ +#define SPDM_KEY_EXCHANGE_REQUEST_NO_MEASUREMENT_SUMMARY_HASH 0 +#define SPDM_KEY_EXCHANGE_REQUEST_TCB_COMPONENT_MEASUREMENT_HASH 1 +#define SPDM_KEY_EXCHANGE_REQUEST_ALL_MEASUREMENTS_HASH 0xFF + +/* SPDM KEY_EXCHANGE response */ +typedef struct { + spdm_message_header_t header; + /* param1 == heartbeat_period + * param2 == RSVD*/ + uint16_t rsp_session_id; + uint8_t mut_auth_requested; + uint8_t req_slot_id_param; + uint8_t random_data[32]; + /*uint8_t exchange_data[D]; + * uint8_t measurement_summary_hash[digest_size]; + * uint16_t opaque_length; + * uint8_t opaque_data[opaque_length]; + * uint8_t signature[S]; + * uint8_t verify_data[H];*/ +} spdm_key_exchange_response_t; + +/* SPDM KEY_EXCHANGE response mut_auth_requested */ +#define SPDM_KEY_EXCHANGE_RESPONSE_MUT_AUTH_REQUESTED 0x00000001 +#define SPDM_KEY_EXCHANGE_RESPONSE_MUT_AUTH_REQUESTED_WITH_ENCAP_REQUEST 0x00000002 +#define SPDM_KEY_EXCHANGE_RESPONSE_MUT_AUTH_REQUESTED_WITH_GET_DIGESTS 0x00000004 + +#define SPDM_KEY_EXCHANGE_RESPONSE_SIGN_CONTEXT "responder-key_exchange_rsp signing" +#define SPDM_KEY_EXCHANGE_RESPONSE_SIGN_CONTEXT_SIZE \ + (sizeof(SPDM_KEY_EXCHANGE_RESPONSE_SIGN_CONTEXT) - 1) + +#define SPDM_VERSION_1_2_KEY_EXCHANGE_REQUESTER_CONTEXT "Requester-KEP-dmtf-spdm-v1.2" +#define SPDM_VERSION_1_2_KEY_EXCHANGE_REQUESTER_CONTEXT_SIZE \ + (sizeof(SPDM_VERSION_1_2_KEY_EXCHANGE_REQUESTER_CONTEXT) - 1) + +#define SPDM_VERSION_1_2_KEY_EXCHANGE_RESPONDER_CONTEXT "Responder-KEP-dmtf-spdm-v1.2" +#define SPDM_VERSION_1_2_KEY_EXCHANGE_RESPONDER_CONTEXT_SIZE \ + (sizeof(SPDM_VERSION_1_2_KEY_EXCHANGE_RESPONDER_CONTEXT) - 1) + +/* SPDM FINISH request */ +typedef struct { + spdm_message_header_t header; + /* param1 == signature_included + * param2 == req_slot_id + * uint8_t signature[S]; + * uint8_t verify_data[H];*/ +} spdm_finish_request_t; + +/* SPDM FINISH request signature_included */ +#define SPDM_FINISH_REQUEST_ATTRIBUTES_SIGNATURE_INCLUDED 0x00000001 + +/* SPDM FINISH response */ +typedef struct { + spdm_message_header_t header; + /* param1 == RSVD + * param2 == RSVD + * uint8_t verify_data[H];*/ +} spdm_finish_response_t; + +#define SPDM_FINISH_SIGN_CONTEXT "requester-finish signing" +#define SPDM_FINISH_SIGN_CONTEXT_SIZE (sizeof(SPDM_FINISH_SIGN_CONTEXT) - 1) + +/* SPDM PSK_EXCHANGE request */ +typedef struct { + spdm_message_header_t header; + /* param1 == HashType + * param2 == RSVD/session_policy (1.2)*/ + uint16_t req_session_id; + uint16_t psk_hint_length; + uint16_t context_length; + uint16_t opaque_length; + /*uint8_t psk_hint[psk_hint_length]; + * uint8_t context[context_length]; + * uint8_t opaque_data[opaque_length];*/ +} spdm_psk_exchange_request_t; + +/* SPDM PSK_EXCHANGE response */ +typedef struct { + spdm_message_header_t header; + /* param1 == heartbeat_period + * param2 == RSVD*/ + uint16_t rsp_session_id; + uint16_t reserved; + uint16_t context_length; + uint16_t opaque_length; + /*uint8_t measurement_summary_hash[digest_size]; + * uint8_t context[context_length]; + * uint8_t opaque_data[opaque_length]; + * uint8_t verify_data[H];*/ +} spdm_psk_exchange_response_t; + +/* SPDM PSK_FINISH request */ +typedef struct { + spdm_message_header_t header; + /* param1 == RSVD + * param2 == RSVD + * uint8_t verify_data[H];*/ +} spdm_psk_finish_request_t; + +/* SPDM PSK_FINISH response */ +typedef struct { + spdm_message_header_t header; + /* param1 == RSVD + * param2 == RSVD*/ +} spdm_psk_finish_response_t; + + +/* SPDM HEARTBEAT request */ +typedef struct { + spdm_message_header_t header; + /* param1 == RSVD + * param2 == RSVD*/ +} spdm_heartbeat_request_t; + +/* SPDM HEARTBEAT response */ +typedef struct { + spdm_message_header_t header; + /* param1 == RSVD + * param2 == RSVD*/ +} spdm_heartbeat_response_t; + +/* SPDM KEY_UPDATE request */ +typedef struct { + spdm_message_header_t header; + /* param1 == key_operation + * param2 == tag*/ +} spdm_key_update_request_t; + +/* SPDM KEY_UPDATE Operations table */ +#define SPDM_KEY_UPDATE_OPERATIONS_TABLE_UPDATE_KEY 1 +#define SPDM_KEY_UPDATE_OPERATIONS_TABLE_UPDATE_ALL_KEYS 2 +#define SPDM_KEY_UPDATE_OPERATIONS_TABLE_VERIFY_NEW_KEY 3 + +/* SPDM KEY_UPDATE response */ +typedef struct { + spdm_message_header_t header; + /* param1 == key_operation + * param2 == tag*/ +} spdm_key_update_response_t; + +/* SPDM GET_ENCAPSULATED_REQUEST request */ +typedef struct { + spdm_message_header_t header; + /* param1 == RSVD + * param2 == RSVD*/ +} spdm_get_encapsulated_request_request_t; + +/* SPDM ENCAPSULATED_REQUEST response */ +typedef struct { + spdm_message_header_t header; + /* param1 == request_id + * param2 == RSVD + * uint8_t encapsulated_request[];*/ +} spdm_encapsulated_request_response_t; + +/* SPDM DELIVER_ENCAPSULATED_RESPONSE request */ +typedef struct { + spdm_message_header_t header; + /* param1 == request_id + * param2 == RSVD + * uint8_t encapsulated_response[];*/ +} spdm_deliver_encapsulated_response_request_t; + +/* SPDM ENCAPSULATED_RESPONSE_ACK response */ +typedef struct { + spdm_message_header_t header; + /* param1 == request_id + * param2 == payload_type*/ + + /* below 4 bytes are added in 1.2.*/ + uint8_t ack_request_id; + uint8_t reserved[3]; + + /*uint8_t encapsulated_request[];*/ +} spdm_encapsulated_response_ack_response_t; + +/* SPDM ENCAPSULATED_RESPONSE_ACK_RESPONSE payload Type */ +#define SPDM_ENCAPSULATED_RESPONSE_ACK_RESPONSE_PAYLOAD_TYPE_ABSENT 0 +#define SPDM_ENCAPSULATED_RESPONSE_ACK_RESPONSE_PAYLOAD_TYPE_PRESENT 1 +#define SPDM_ENCAPSULATED_RESPONSE_ACK_RESPONSE_PAYLOAD_TYPE_REQ_SLOT_NUMBER 2 + +/* SPDM END_SESSION request */ +typedef struct { + spdm_message_header_t header; + /* param1 == end_session_request_attributes + * param2 == RSVD*/ +} spdm_end_session_request_t; + +/* SPDM END_SESSION request Attributes */ +#define SPDM_END_SESSION_REQUEST_ATTRIBUTES_PRESERVE_NEGOTIATED_STATE_CLEAR 0x00000001 + +/* SPDM END_SESSION response */ +typedef struct { + spdm_message_header_t header; + /* param1 == RSVD + * param2 == RSVD*/ +} spdm_end_session_response_t; + +/* SPDM SET_CERTIFICATE request */ +typedef struct { + spdm_message_header_t header; + /* param1 == BIT[0:3]=slot_id, BIT[4:7]=RSVD + * param2 == RSVD + * void * cert_chain*/ +} spdm_set_certificate_request_t; + +/* SPDM SET_CERTIFICATE_RSP response */ +typedef struct { + spdm_message_header_t header; + /* param1 == BIT[0:3]=slot_id, BIT[4:7]=RSVD + * param2 == RSVD*/ +} spdm_set_certificate_response_t; + +/* SPDM GET_CSR request */ +typedef struct { + spdm_message_header_t header; + /* param1 == RSVD + * param2 == RSVD*/ + uint16_t requester_info_length; + uint16_t opaque_data_length; + /* uint8_t RequesterInfo[requester_info_length]; + * uint8_t opaque_data[opaque_data_length]; */ +} spdm_get_csr_request_t; + +/* SPDM CSR response */ +typedef struct { + spdm_message_header_t header; + /* param1 == RSVD + * param2 == RSVD*/ + uint16_t csr_length; + uint16_t reserved; +} spdm_csr_response_t; + +/* SPDM CHUNK_SEND request */ +typedef struct { + spdm_message_header_t header; + /* param1 - Request Attributes + * param2 - Handle */ + uint16_t chunk_seq_no; + uint16_t reserved; + uint32_t chunk_size; + + /* uint32_t large_message_size; + * uint8_t spdm_chunk[chunk_size]; */ +} spdm_chunk_send_request_t; + +#define SPDM_CHUNK_SEND_REQUEST_ATTRIBUTE_LAST_CHUNK (1 << 0) + +/* SPDM CHUNK_SEND_ACK response */ +typedef struct { + spdm_message_header_t header; + /* param1 - Response Attributes + * param2 - Handle */ + uint16_t chunk_seq_no; + /* uint8_t response_to_large_request[variable] */ +} spdm_chunk_send_ack_response_t; + +#define SPDM_CHUNK_SEND_ACK_RESPONSE_ATTRIBUTE_EARLY_ERROR_DETECTED (1 << 0) + +/* SPDM CHUNK_GET request */ +typedef struct { + spdm_message_header_t header; + /* param1 - Reserved + * param2 - Handle */ + uint16_t chunk_seq_no; +} spdm_chunk_get_request_t; + +/* SPDM CHUNK_RESPONSE response */ +typedef struct { + spdm_message_header_t header; + /* param1 - Response Attributes + * param2 - Handle */ + uint16_t chunk_seq_no; + uint16_t reserved; + uint32_t chunk_size; + + /* uint32_t large_message_size; + * uint8_t spdm_chunk[chunk_size]; */ +} spdm_chunk_response_response_t; + +#define SPDM_CHUNK_GET_RESPONSE_ATTRIBUTE_LAST_CHUNK (1 << 0) + +#pragma pack() + +#define SPDM_VERSION_1_1_BIN_CONCAT_LABEL "spdm1.1 " +#define SPDM_VERSION_1_2_BIN_CONCAT_LABEL "spdm1.2 " +#define SPDM_BIN_STR_0_LABEL "derived" +#define SPDM_BIN_STR_1_LABEL "req hs data" +#define SPDM_BIN_STR_2_LABEL "rsp hs data" +#define SPDM_BIN_STR_3_LABEL "req app data" +#define SPDM_BIN_STR_4_LABEL "rsp app data" +#define SPDM_BIN_STR_5_LABEL "key" +#define SPDM_BIN_STR_6_LABEL "iv" +#define SPDM_BIN_STR_7_LABEL "finished" +#define SPDM_BIN_STR_8_LABEL "exp master" +#define SPDM_BIN_STR_9_LABEL "traffic upd" + +/** + * The maximum amount of time in microseconds the Responder has to provide a response + * to requests that do not require cryptographic processing. + **/ +#define SPDM_ST1_VALUE_US 100000 + +#define SPDM_OID_EXTENSION {0x2B, 0x06, 0x01, 0x04, 0x01, 0x83, 0x1C, 0x82, 0x12, 0x06} +#define SPDM_OID_HARDWARE_IDENTITY {0x2B, 0x06, 0x01, 0x04, 0x01, 0x83, 0x1C, 0x82, 0x12, 0x02} + +#endif /* SPDM_H */ diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/libraries/libspdm/2.3.1/include/industry_standard/spdm_secured_message.h nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/libraries/libspdm/2.3.1/include/industry_standard/spdm_secured_message.h --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/libraries/libspdm/2.3.1/include/industry_standard/spdm_secured_message.h 1970-01-01 00:00:00.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/libraries/libspdm/2.3.1/include/industry_standard/spdm_secured_message.h 2024-03-05 22:14:12.000000000 +0000 @@ -0,0 +1,127 @@ +/** + * Copyright Notice: + * Copyright 2021-2022 DMTF. All rights reserved. + * License: BSD 3-Clause License. For full text see link: https://github.com/DMTF/libspdm/blob/main/LICENSE.md + **/ + +/** @file + * Definitions of DSP0277 Secured Messages using SPDM Specification + * version 1.0.0 in Distributed Management Task Force (DMTF). + **/ + +#ifndef SPDM_SECURED_MESSAGE_H +#define SPDM_SECURED_MESSAGE_H + +#pragma pack(1) + + +/* ENC+AUTH session:*/ + +/* +-----------------+ + * | ApplicationData |----------------------------------------------------- + * +-----------------+ | + * V + * +---------------------------------+----------------------------------+-------+------+---+ + * |SPDM_SECURED_MESSAGE_ADATA_HEADER|SPDM_SECURED_MESSAGE_CIPHER_HEADER|AppData|Random|MAC| + * | SessionId | SeqNum (O) | Length | ApplicationDataLength | | (O) | | + * +---------------------------------+----------------------------------+-------+------+---+ + * | | | | + * --------------------------------- ------------------------------------------------- --- + * | | | + * V V V + * AssociatedData EncryptedData AeadTag + */ + +/* (O) means Optional or Transport Layer Specific.*/ + +/* AUTH session:*/ + +/* +-----------------+ + * | ApplicationData |------------------ + * +-----------------+ | + * V + * +---------------------------------+-------+---+ + * |SPDM_SECURED_MESSAGE_ADATA_HEADER|AppData|MAC| + * | SessionId | SeqNum (T) | length | | | + * +---------------------------------+-------+---+ + * | | | + * ----------------------------------------- --- + * | | + * V V + * AssociatedData AeadTag + */ + + +typedef struct { + uint32_t session_id; +} spdm_secured_message_a_data_header1_t; + +/* The length of sequence_number between HEADER_1 and HEADER_2 is transport specific.*/ + +typedef struct { + uint16_t length; /* The length of the remaining data, including application_data_length(O), payload, Random(O) and MAC.*/ +} spdm_secured_message_a_data_header2_t; + +typedef struct { + uint16_t application_data_length; /* The length of the payload*/ +} spdm_secured_message_cipher_header_t; + + +/* Secured Messages opaque data format*/ + +#define SECURED_MESSAGE_OPAQUE_DATA_SPEC_ID 0x444D5446 +#define SECURED_MESSAGE_OPAQUE_VERSION 0x1 + +typedef struct { + uint32_t spec_id; /* SECURED_MESSAGE_OPAQUE_DATA_SPEC_ID*/ + uint8_t opaque_version; /* SECURED_MESSAGE_OPAQUE_VERSION*/ + uint8_t total_elements; + uint16_t reserved; + /*opaque_element_table_t opaque_list[];*/ +} secured_message_general_opaque_data_table_header_t; + +typedef struct { + uint8_t id; + uint8_t vendor_len; + /*uint8_t vendor_id[vendor_len]; + * uint16_t opaque_element_data_len; + * uint8_t opaque_element_data[opaque_element_data_len]; + * uint8_t align_padding[];*/ +} opaque_element_table_header_t; + +#define SECURED_MESSAGE_OPAQUE_ELEMENT_SMDATA_DATA_VERSION 0x1 + +typedef struct { + uint8_t id; /* SPDM_REGISTRY_ID_DMTF*/ + uint8_t vendor_len; + uint16_t opaque_element_data_len; + /*uint8_t sm_data_version; + * uint8_t sm_data_id; + * uint8_t sm_data[];*/ +} secured_message_opaque_element_table_header_t; + +typedef struct { + uint8_t sm_data_version; /* SECURED_MESSAGE_OPAQUE_ELEMENT_SMDATA_DATA_VERSION*/ + uint8_t sm_data_id; /* SECURED_MESSAGE_OPAQUE_ELEMENT_SMDATA_ID_VERSION_SELECTION*/ +} secured_message_opaque_element_header_t; + +#define SECURED_MESSAGE_OPAQUE_ELEMENT_SMDATA_ID_VERSION_SELECTION 0x0 + +typedef struct { + uint8_t sm_data_version; /* SECURED_MESSAGE_OPAQUE_ELEMENT_SMDATA_DATA_VERSION*/ + uint8_t sm_data_id; /* SECURED_MESSAGE_OPAQUE_ELEMENT_SMDATA_ID_VERSION_SELECTION*/ + spdm_version_number_t selected_version; +} secured_message_opaque_element_version_selection_t; + +#define SECURED_MESSAGE_OPAQUE_ELEMENT_SMDATA_ID_SUPPORTED_VERSION 0x1 + +typedef struct { + uint8_t sm_data_version; /* SECURED_MESSAGE_OPAQUE_ELEMENT_SMDATA_DATA_VERSION*/ + uint8_t sm_data_id; /* SECURED_MESSAGE_OPAQUE_ELEMENT_SMDATA_ID_SUPPORTED_VERSION*/ + uint8_t version_count; + /*spdm_version_number_t versions_list[version_count];*/ +} secured_message_opaque_element_supported_version_t; + +#pragma pack() + +#endif /* SPDM_SECURED_MESSAGE_H */ diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/libraries/libspdm/2.3.1/include/internal/libspdm_common_lib.h nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/libraries/libspdm/2.3.1/include/internal/libspdm_common_lib.h --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/libraries/libspdm/2.3.1/include/internal/libspdm_common_lib.h 1970-01-01 00:00:00.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/libraries/libspdm/2.3.1/include/internal/libspdm_common_lib.h 2024-03-05 22:14:12.000000000 +0000 @@ -0,0 +1,1298 @@ +/** + * Copyright Notice: + * Copyright 2021-2022 DMTF. All rights reserved. + * License: BSD 3-Clause License. For full text see link: https://github.com/DMTF/libspdm/blob/main/LICENSE.md + **/ + +#ifndef SPDM_COMMON_LIB_INTERNAL_H +#define SPDM_COMMON_LIB_INTERNAL_H + +#include "library/spdm_common_lib.h" +#include "library/spdm_secured_message_lib.h" +#include "library/spdm_return_status.h" +#include "library/spdm_crypt_lib.h" +#include "library/spdm_device_secret_lib.h" + +#define INVALID_SESSION_ID 0 + +typedef struct { + uint8_t spdm_version_count; + spdm_version_number_t spdm_version[SPDM_MAX_VERSION_COUNT]; +} libspdm_device_version_t; + +typedef struct { + uint8_t ct_exponent; + uint64_t rtt; + uint32_t st1; + uint32_t flags; + uint32_t data_transfer_size; + uint32_t max_spdm_msg_size; +} libspdm_device_capability_t; + +typedef struct { + uint8_t measurement_spec; + uint8_t other_params_support; + uint32_t measurement_hash_algo; + uint32_t base_asym_algo; + uint32_t base_hash_algo; + uint16_t dhe_named_group; + uint16_t aead_cipher_suite; + uint16_t req_base_asym_alg; + uint16_t key_schedule; +} libspdm_device_algorithm_t; + +typedef struct { +#if LIBSPDM_RECORD_TRANSCRIPT_DATA_SUPPORT + uint8_t buffer[LIBSPDM_MAX_CERT_CHAIN_SIZE]; + size_t buffer_size; +#else + uint8_t buffer_hash[LIBSPDM_MAX_HASH_SIZE]; + uint32_t buffer_hash_size; + /* leaf cert public key of the peer */ + void *leaf_cert_public_key; +#endif +} libspdm_peer_used_cert_chain_t; + +typedef struct { + /* Local device info */ + libspdm_device_version_t version; + libspdm_device_capability_t capability; + libspdm_device_algorithm_t algorithm; + libspdm_device_version_t secured_message_version; + + /* My Certificate */ + const void *local_cert_chain_provision[SPDM_MAX_SLOT_COUNT]; + size_t local_cert_chain_provision_size[SPDM_MAX_SLOT_COUNT]; + /* My provisioned certificate (for slot_id - 0xFF, default 0)*/ + uint8_t provisioned_slot_id; + + /* Peer Root Certificate */ + const void *peer_root_cert_provision[LIBSPDM_MAX_ROOT_CERT_SUPPORT]; + size_t peer_root_cert_provision_size[LIBSPDM_MAX_ROOT_CERT_SUPPORT]; + + /* Peer CertificateChain + * Whether it contains the root certificate or not, + * it should be equal to the one returned from peer by get_certificate*/ + const void *peer_cert_chain_provision; + size_t peer_cert_chain_provision_size; + + /* Peer Cert verify*/ + libspdm_verify_spdm_cert_chain_func verify_peer_spdm_cert_chain; + + /* PSK provision locally*/ + size_t psk_hint_size; + const void *psk_hint; + + /* opaque_data provision locally*/ + size_t opaque_challenge_auth_rsp_size; + uint8_t *opaque_challenge_auth_rsp; + size_t opaque_measurement_rsp_size; + uint8_t *opaque_measurement_rsp; + + /* Responder policy*/ + bool basic_mut_auth_requested; + uint8_t mut_auth_requested; + uint8_t heartbeat_period; + + /*The device role*/ + bool is_requester; +} libspdm_local_context_t; + +typedef struct { + /* Connection State */ + libspdm_connection_state_t connection_state; + + /* Peer device info (negotiated) */ + spdm_version_number_t version; + libspdm_device_capability_t capability; + libspdm_device_algorithm_t algorithm; + spdm_version_number_t secured_message_version; + + /* Peer digests buffer */ + uint8_t peer_digest_slot_mask; + uint8_t peer_total_digest_buffer[LIBSPDM_MAX_HASH_SIZE * SPDM_MAX_SLOT_COUNT]; + + /* Peer CertificateChain */ + libspdm_peer_used_cert_chain_t peer_used_cert_chain[SPDM_MAX_SLOT_COUNT]; + uint8_t peer_used_cert_chain_slot_id; + + /* Local Used CertificateChain (for responder, or requester in mut auth) */ + const uint8_t *local_used_cert_chain_buffer; + size_t local_used_cert_chain_buffer_size; +} libspdm_connection_info_t; + +typedef struct { + size_t max_buffer_size; + size_t buffer_size; + /*uint8_t buffer[max_buffer_size];*/ +} libspdm_managed_buffer_t; + +typedef struct { + size_t max_buffer_size; + size_t buffer_size; + uint8_t buffer[LIBSPDM_MAX_MESSAGE_BUFFER_SIZE]; +} libspdm_large_managed_buffer_t; + +typedef struct { + size_t max_buffer_size; + size_t buffer_size; + uint8_t buffer[LIBSPDM_MAX_MESSAGE_MEDIUM_BUFFER_SIZE]; +} libspdm_medium_managed_buffer_t; + +typedef struct { + size_t max_buffer_size; + size_t buffer_size; + uint8_t buffer[LIBSPDM_MAX_MESSAGE_SMALL_BUFFER_SIZE]; +} libspdm_small_managed_buffer_t; + +/* signature = Sign(SK, hash(M1)) + * Verify(PK, hash(M2), signature)*/ + +/* M1/M2 = Concatenate (A, B, C) + * A = Concatenate (GET_VERSION, VERSION, GET_CAPABILITIES, CAPABILITIES, NEGOTIATE_ALGORITHMS, ALGORITHMS) + * B = Concatenate (GET_DIGEST, DIGEST, GET_CERTFICATE, CERTIFICATE) + * C = Concatenate (CHALLENGE, CHALLENGE_AUTH\signature)*/ + +/* Mut M1/M2 = Concatenate (MutB, MutC) + * MutB = Concatenate (GET_DIGEST, DIGEST, GET_CERTFICATE, CERTIFICATE) + * MutC = Concatenate (CHALLENGE, CHALLENGE_AUTH\signature)*/ + +/* signature = Sign(SK, hash(L1)) + * Verify(PK, hash(L2), signature)*/ + +/* L1/L2 = Concatenate (M) + * M = Concatenate (GET_MEASUREMENT, MEASUREMENT\signature)*/ + +typedef struct { + /* the message_a must be plan text because we do not know the algorithm yet.*/ + libspdm_small_managed_buffer_t message_a; +#if LIBSPDM_RECORD_TRANSCRIPT_DATA_SUPPORT + libspdm_large_managed_buffer_t message_b; + libspdm_small_managed_buffer_t message_c; + libspdm_large_managed_buffer_t message_mut_b; + libspdm_small_managed_buffer_t message_mut_c; + libspdm_large_managed_buffer_t message_m; +#else + void *digest_context_m1m2; + void *digest_context_mut_m1m2; + void *digest_context_l1l2; +#endif +} libspdm_transcript_t; + +/* TH for KEY_EXCHANGE response signature: Concatenate (A, Ct, K) + * Ct = certificate chain + * K = Concatenate (KEY_EXCHANGE request, KEY_EXCHANGE response\signature+verify_data)*/ + +/* TH for KEY_EXCHANGE response HMAC: Concatenate (A, Ct, K) + * Ct = certificate chain + * K = Concatenate (KEY_EXCHANGE request, KEY_EXCHANGE response\verify_data)*/ + +/* TH for FINISH request signature: Concatenate (A, Ct, K, CM, F) + * Ct = certificate chain + * K = Concatenate (KEY_EXCHANGE request, KEY_EXCHANGE response)*/ +/* CM = mutual certificate chain * + * F = Concatenate (FINISH request\signature+verify_data)*/ + +/* TH for FINISH response HMAC: Concatenate (A, Ct, K, CM, F) + * Ct = certificate chain + * K = Concatenate (KEY_EXCHANGE request, KEY_EXCHANGE response)*/ +/* CM = mutual certificate chain * + * F = Concatenate (FINISH request\verify_data)*/ + +/* th1: Concatenate (A, Ct, K) + * Ct = certificate chain + * K = Concatenate (KEY_EXCHANGE request, KEY_EXCHANGE response)*/ + +/* th2: Concatenate (A, Ct, K, CM, F) + * Ct = certificate chain + * K = Concatenate (KEY_EXCHANGE request, KEY_EXCHANGE response)*/ +/* CM = mutual certificate chain * + * F = Concatenate (FINISH request, FINISH response)*/ + +/* TH for PSK_EXCHANGE response HMAC: Concatenate (A, K) + * K = Concatenate (PSK_EXCHANGE request, PSK_EXCHANGE response\verify_data)*/ + +/* TH for PSK_FINISH response HMAC: Concatenate (A, K, F) + * K = Concatenate (PSK_EXCHANGE request, PSK_EXCHANGE response) + * F = Concatenate (PSK_FINISH request\verify_data)*/ + +/* TH1_PSK1: Concatenate (A, K) + * K = Concatenate (PSK_EXCHANGE request, PSK_EXCHANGE response\verify_data)*/ + +/* TH1_PSK2: Concatenate (A, K, F) + * K = Concatenate (PSK_EXCHANGE request, PSK_EXCHANGE response) + * F = Concatenate (PSK_FINISH request\verify_data)*/ + +/* TH2_PSK: Concatenate (A, K, F) + * K = Concatenate (PSK_EXCHANGE request, PSK_EXCHANGE response) + * F = Concatenate (PSK_FINISH request, PSK_FINISH response)*/ + +typedef struct { +#if LIBSPDM_RECORD_TRANSCRIPT_DATA_SUPPORT + libspdm_large_managed_buffer_t message_k; + libspdm_large_managed_buffer_t message_f; + libspdm_large_managed_buffer_t message_m; +#else + bool message_f_initialized; + void *digest_context_th; + void *digest_context_l1l2; + /* this is back up for message F reset.*/ + void *digest_context_th_backup; +#endif +} libspdm_session_transcript_t; + +typedef struct { + uint32_t session_id; + bool use_psk; + uint8_t mut_auth_requested; + uint8_t end_session_attributes; + uint8_t session_policy; + uint8_t heartbeat_period; + libspdm_session_transcript_t session_transcript; + /* Register for the last KEY_UPDATE token and operation (responder only)*/ + spdm_key_update_request_t last_key_update_request; + void *secured_message_context; +} libspdm_session_info_t; + +#define LIBSPDM_MAX_ENCAP_REQUEST_OP_CODE_SEQUENCE_COUNT 3 +typedef struct { + /* Valid OpCode: GET_DIEGST/GET_CERTIFICATE/CHALLENGE/KEY_UPDATE + * The last one is 0x00, as terminator.*/ + uint8_t request_op_code_sequence[LIBSPDM_MAX_ENCAP_REQUEST_OP_CODE_SEQUENCE_COUNT + 1]; + uint8_t request_op_code_count; + uint8_t current_request_op_code; + uint8_t request_id; + uint8_t req_slot_id; + spdm_message_header_t last_encap_request_header; + size_t last_encap_request_size; + uint16_t cert_chain_total_len; + libspdm_large_managed_buffer_t certificate_chain_buffer; +} libspdm_encap_context_t; + +#if LIBSPDM_ENABLE_CAPABILITY_CHUNK_CAP || LIBSPDM_ENABLE_CHUNK_CAP +typedef struct { + bool chunk_in_use; + uint8_t chunk_handle; + uint16_t chunk_seq_no; + size_t chunk_bytes_transferred; + + void* large_message; + size_t large_message_size; + size_t large_message_capacity; +} libspdm_chunk_info_t; + +typedef struct { + libspdm_chunk_info_t send; + libspdm_chunk_info_t get; +} libspdm_chunk_context_t; +#endif /* LIBSPDM_ENABLE_CAPABILITY_CHUNK_CAP */ + +#if LIBSPDM_ENABLE_MSG_LOG +typedef struct { + void *buffer; + size_t max_buffer_size; + uint32_t mode; + size_t buffer_size; + uint32_t status; +} libspdm_msg_log_t; +#endif /* LIBSPDM_ENABLE_MSG_LOG */ + +#define libspdm_context_struct_version 0x2 + +typedef struct { + uint32_t version; + + /* IO information */ + libspdm_device_send_message_func send_message; + libspdm_device_receive_message_func receive_message; + + /* + * reserved for request and response in the main dispatch function in SPDM responder. + * this buffer is the transport message recived from spdm_context->receive_message() + * or sent to spdm_context->send_message(). + * This message may be SPDM transport message or secured SPDM transport message. + **/ + libspdm_device_acquire_sender_buffer_func acquire_sender_buffer; + libspdm_device_release_sender_buffer_func release_sender_buffer; + libspdm_device_acquire_receiver_buffer_func acquire_receiver_buffer; + libspdm_device_release_receiver_buffer_func release_receiver_buffer; + + /* Transport Layer information */ + libspdm_transport_encode_message_func transport_encode_message; + libspdm_transport_decode_message_func transport_decode_message; + libspdm_transport_get_header_size_func transport_get_header_size; + + /* Cached plain text command + * If the command is cipher text, decrypt then cache it. */ + uint8_t last_spdm_request[LIBSPDM_MAX_MESSAGE_BUFFER_SIZE]; + size_t last_spdm_request_size; + + /* scratch buffer */ + uint8_t *scratch_buffer; + size_t scratch_buffer_size; + /* sender buffer */ + uint8_t *sender_buffer; + size_t sender_buffer_size; + /* receiver buffer */ + uint8_t *receiver_buffer; + size_t receiver_buffer_size; + + /* Cache session_id in this spdm_message, only valid for secured message. */ + uint32_t last_spdm_request_session_id; + bool last_spdm_request_session_id_valid; + + /* Cache the error in libspdm_process_request. It is handled in libspdm_build_response. */ + libspdm_error_struct_t last_spdm_error; + + /* Register GetResponse function (responder only) */ + size_t get_response_func; + + /* Register GetEncapResponse function (requester only) */ + size_t get_encap_response_func; + libspdm_encap_context_t encap_context; + + /* Register spdm_session_state_callback function (responder only) + * Register can know the state after StartSession / EndSession. */ + size_t spdm_session_state_callback[LIBSPDM_MAX_SESSION_STATE_CALLBACK_NUM]; + + /* Register spdm_connection_state_callback function (responder only) + * Register can know the connection state such as negotiated. */ + size_t spdm_connection_state_callback[LIBSPDM_MAX_CONNECTION_STATE_CALLBACK_NUM]; + + /* Register libspdm_key_update_callback function (responder only) + * Register can know when session keys are updated during KEY_UPDATE operations. */ + size_t spdm_key_update_callback[LIBSPDM_MAX_KEY_UPDATE_CALLBACK_NUM]; + + libspdm_local_context_t local_context; + + libspdm_connection_info_t connection_info; + libspdm_transcript_t transcript; + + libspdm_session_info_t session_info[LIBSPDM_MAX_SESSION_COUNT]; + + /* Cache lastest session ID for HANDSHAKE_IN_THE_CLEAR */ + uint32_t latest_session_id; + + /* Register for Responder state, be initial to Normal (responder only) */ + libspdm_response_state_t response_state; + + /* Cached data for SPDM_ERROR_CODE_RESPONSE_NOT_READY/SPDM_RESPOND_IF_READY */ + spdm_error_data_response_not_ready_t error_data; + uint8_t cache_spdm_request[LIBSPDM_MAX_MESSAGE_BUFFER_SIZE]; + size_t cache_spdm_request_size; + uint8_t current_token; + + /* Register for the retry times when receive "BUSY" Error response (requester only) */ + uint8_t retry_times; + bool crypto_request; + + /* App context data for use by application */ + void *app_context_data_ptr; + + /* See LIBSPDM_DATA_HANDLE_ERROR_RETURN_POLICY_*. */ + uint8_t handle_error_return_policy; + +#if LIBSPDM_ENABLE_CAPABILITY_CHUNK_CAP || LIBSPDM_ENABLE_CHUNK_CAP + /* Chunk specific context */ + libspdm_chunk_context_t chunk_context; +#endif /* LIBSPDM_ENABLE_CAPABILITY_CHUNK_CAP */ + +#if LIBSPDM_ENABLE_MSG_LOG + libspdm_msg_log_t msg_log; +#endif /* LIBSPDM_ENABLE_MSG_LOG */ +} libspdm_context_t; + +#define LIBSPDM_CONTEXT_SIZE_WITHOUT_SECURED_CONTEXT (sizeof(libspdm_context_t)) +#define LIBSPDM_CONTEXT_SIZE_ALL (LIBSPDM_CONTEXT_SIZE_WITHOUT_SECURED_CONTEXT + \ + LIBSPDM_SECURED_MESSAGE_CONTEXT_SIZE * LIBSPDM_MAX_SESSION_COUNT) + +#if LIBSPDM_DEBUG_PRINT_ENABLE +/** + * This function dump raw data. + * + * @param data raw data + * @param size raw data size + **/ +void libspdm_internal_dump_hex_str(const uint8_t *data, size_t size); +#define LIBSPDM_INTERNAL_DUMP_HEX_STR(data, size) libspdm_internal_dump_hex_str(data, size) + +/** + * This function dump raw data. + * + * @param data raw data + * @param size raw data size + **/ +void libspdm_internal_dump_data(const uint8_t *data, size_t size); +#define LIBSPDM_INTERNAL_DUMP_DATA(data, size) libspdm_internal_dump_data(data, size) + +/** + * This function dump raw data with colume format. + * + * @param data raw data + * @param size raw data size + **/ +void libspdm_internal_dump_hex(const uint8_t *data, size_t size); +#define LIBSPDM_INTERNAL_DUMP_HEX(data, size) libspdm_internal_dump_hex(data, size) + +#else /* LIBSPDM_DEBUG_PRINT_ENABLE */ +#define LIBSPDM_INTERNAL_DUMP_HEX(data, size) +#define LIBSPDM_INTERNAL_DUMP_HEX_STR(data, size) +#define LIBSPDM_INTERNAL_DUMP_DATA(data, size) +#endif /* LIBSPDM_DEBUG_PRINT_ENABLE */ + +/** + * Append a new data buffer to the managed buffer. + * + * @param managed_buffer The managed buffer to be appended. + * @param buffer The address of the data buffer to be appended to the managed buffer. + * @param buffer_size The size in bytes of the data buffer to be appended to the managed buffer. + * + * @retval RETURN_SUCCESS The new data buffer is appended to the managed buffer. + * @retval RETURN_BUFFER_TOO_SMALL The managed buffer is too small to be appended. + **/ +libspdm_return_t libspdm_append_managed_buffer(void *managed_buffer, + const void *buffer, size_t buffer_size); + +/** + * Reset the managed buffer. + * The buffer_size is reset to 0. + * The max_buffer_size is unchanged. + * The buffer is not freed. + * + * @param managed_buffer The managed buffer to be shrinked. + **/ +void libspdm_reset_managed_buffer(void *managed_buffer); + +/** + * Return the size of managed buffer. + * + * @param managed_buffer The managed buffer. + * + * @return the size of managed buffer. + **/ +size_t libspdm_get_managed_buffer_size(void *managed_buffer); + +/** + * Return the address of managed buffer. + * + * @param managed_buffer The managed buffer. + * + * @return the address of managed buffer. + **/ +void *libspdm_get_managed_buffer(void *managed_buffer); + +/** + * Init the managed buffer. + * + * @param managed_buffer The managed buffer. + * @param max_buffer_size The maximum size in bytes of the managed buffer. + **/ +void libspdm_init_managed_buffer(void *managed_buffer, size_t max_buffer_size); + +/** + * Reset message buffer in SPDM context according to request code. + * + * @param spdm_context A pointer to the SPDM context. + * @param spdm_session_info A pointer to the SPDM session context. + * @param spdm_request The SPDM request code. + */ +void libspdm_reset_message_buffer_via_request_code(void *context, void *session_info, + uint8_t request_code); + +/** + * This function initializes the session info. + * + * @param spdm_context A pointer to the SPDM context. + * @param session_id The SPDM session ID. + **/ +void libspdm_session_info_init(libspdm_context_t *spdm_context, + libspdm_session_info_t *session_info, + uint32_t session_id, bool use_psk); + +/** + * Set the psk_hint to a session info. + * + * @param session_info A pointer to a session info. + * @param psk_hint Indicate the PSK hint. + * @param psk_hint_size The size in bytes of the PSK hint. + */ +void libspdm_session_info_set_psk_hint(libspdm_session_info_t *session_info, + const void *psk_hint, + size_t psk_hint_size); + +/** + * This function returns if a given version is supported based upon the GET_VERSION/VERSION. + * + * @param spdm_context A pointer to the SPDM context. + * @param version The SPDM version. + * + * @retval true the version is supported. + * @retval false the version is not supported. + **/ +bool libspdm_is_version_supported(const libspdm_context_t *spdm_context, uint8_t version); + +/** + * This function returns connection version negotiated by GET_VERSION/VERSION. + * + * @param spdm_context A pointer to the SPDM context. + * + * @return the connection version. + **/ +uint8_t libspdm_get_connection_version(const libspdm_context_t *spdm_context); + +/** + * This function returns if a capablities flag is supported in current SPDM connection. + * + * @param spdm_context A pointer to the SPDM context. + * @param is_requester Is the function called from a requester. + * @param requester_capabilities_flag The requester capabilities flag to be checked + * @param responder_capabilities_flag The responder capabilities flag to be checked + * + * @retval true the capablities flag is supported. + * @retval false the capablities flag is not supported. + **/ +bool libspdm_is_capabilities_flag_supported(const libspdm_context_t *spdm_context, + bool is_requester, + uint32_t requester_capabilities_flag, + uint32_t responder_capabilities_flag); + +/** + * This function generates the certificate chain hash. + * + * @param spdm_context A pointer to the SPDM context. + * @param slot_id The slot index of the certificate chain. + * @param signature The buffer to store the certificate chain hash. + * + * @retval true certificate chain hash is generated. + * @retval false certificate chain hash is not generated. + **/ +bool libspdm_generate_cert_chain_hash(libspdm_context_t *spdm_context, + size_t slot_id, uint8_t *hash); + +/** + * This function verifies the digest. + * + * @param spdm_context A pointer to the SPDM context. + * @param digest The digest data buffer. + * @param digest_count size of the digest data buffer. + * + * @retval true digest verification pass. + * @retval false digest verification fail. + **/ +bool libspdm_verify_peer_digests(libspdm_context_t *spdm_context, + const void *digest, size_t digest_count); + +/** + * This function verifies peer certificate chain buffer including spdm_cert_chain_t header. + * + * @param spdm_context A pointer to the SPDM context. + * @param cert_chain_buffer Certitiface chain buffer including spdm_cert_chain_t header. + * @param cert_chain_buffer_size size in bytes of the certitiface chain buffer. + * @param trust_anchor A buffer to hold the trust_anchor which is used to validate the peer certificate, if not NULL. + * @param trust_anchor_size A buffer to hold the trust_anchor_size, if not NULL. + * @param is_requester Indicates if it is a requester message. + * + * @retval true Peer certificate chain buffer verification passed. + * @retval false Peer certificate chain buffer verification failed. + **/ +bool libspdm_verify_peer_cert_chain_buffer(libspdm_context_t *spdm_context, + const void *cert_chain_buffer, + size_t cert_chain_buffer_size, + const void **trust_anchor, + size_t *trust_anchor_size, + bool is_requester); + +/** + * This function generates the challenge signature based upon m1m2 for authentication. + * + * @param spdm_context A pointer to the SPDM context. + * @param is_requester Indicate of the signature generation for a requester or a responder. + * @param signature The buffer to store the challenge signature. + * + * @retval true challenge signature is generated. + * @retval false challenge signature is not generated. + **/ +bool libspdm_generate_challenge_auth_signature(libspdm_context_t *spdm_context, + bool is_requester, + uint8_t *signature); + +/** + * This function verifies the certificate chain hash. + * + * @param spdm_context A pointer to the SPDM context. + * @param certificate_chain_hash The certificate chain hash data buffer. + * @param certificate_chain_hash_size size in bytes of the certificate chain hash data buffer. + * + * @retval true hash verification pass. + * @retval false hash verification fail. + **/ +bool libspdm_verify_certificate_chain_hash(libspdm_context_t *spdm_context, + const void *certificate_chain_hash, + size_t certificate_chain_hash_size); + +/** + * This function verifies the challenge signature based upon m1m2. + * + * @param spdm_context A pointer to the SPDM context. + * @param is_requester Indicate of the signature verification for a requester or a responder. + * @param sign_data The signature data buffer. + * @param sign_data_size size in bytes of the signature data buffer. + * + * @retval true signature verification pass. + * @retval false signature verification fail. + **/ +bool libspdm_verify_challenge_auth_signature(libspdm_context_t *spdm_context, + bool is_requester, + const void *sign_data, + size_t sign_data_size); + +/** + * This function calculate the measurement summary hash size. + * + * @param spdm_context A pointer to the SPDM context. + * @param is_requester Is the function called from a requester. + * @param measurement_summary_hash_type The type of the measurement summary hash. + * + * @return 0 measurement summary hash type is invalid, NO_MEAS hash type or no MEAS capabilities. + * @return measurement summary hash size according to type. + **/ +uint32_t libspdm_get_measurement_summary_hash_size(libspdm_context_t *spdm_context, + bool is_requester, + uint8_t measurement_summary_hash_type); + +/* + * This function calculates l1l2. + * If session_info is NULL, this function will use M cache of SPDM context, + * else will use M cache of SPDM session context. + * + * @param spdm_context A pointer to the SPDM context. + * @param session_info A pointer to the SPDM session context. + * @param l1l2 The buffer to store the l1l2. + * + * @retval RETURN_SUCCESS l1l2 is calculated. + */ +bool libspdm_calculate_l1l2(void *context, void *session_info, + libspdm_large_managed_buffer_t *l1l2); + +/* + * This function calculates l1l2 hash. + * If session_info is NULL, this function will use M cache of SPDM context, + * else will use M cache of SPDM session context. + * + * @param spdm_context A pointer to the SPDM context. + * @param session_info A pointer to the SPDM session context. + * @param l1l2_hash_size size in bytes of the l1l2 hash + * @param l1l2_hash The buffer to store the l1l2 hash + * + * @retval RETURN_SUCCESS l1l2 is calculated. + */ +bool libspdm_calculate_l1l2_hash(void *context, void *session_info, + size_t *l1l2_hash_size, void *l1l2_hash); + +/** + * Get element from multi element opaque data by element id. + * + * This function should be called in + * libspdm_process_opaque_data_supported_version_data/libspdm_process_opaque_data_version_selection_data. + * + * @param[in] data_in_size Size of multi element opaque data. + * @param[in] data_in A pointer to the multi element opaque data. + * @param[in] element_id Element id. + * @param[in] sm_data_id ID for the Secured Message data type. + * @param[out] get_element_ptr Pointer to store finded element. + * + * @retval true Get element successfully + * @retval false Get element failed + **/ +bool libspdm_get_element_from_opaque_data(libspdm_context_t *spdm_context, + size_t data_in_size, const void *data_in, + uint8_t element_id, uint8_t sm_data_id, + const void **get_element_ptr, size_t *get_element_len); + +/** + * Return the size in bytes of opaque data supported version. + * + * This function should be called in libspdm_process_opaque_data_supported_version_data. + * + * @param version_count Secure version count. + * + * @return The size in bytes of opaque data supported version. + **/ +size_t libspdm_get_untrusted_opaque_data_supported_version_data_size( + libspdm_context_t *spdm_context, uint8_t version_count); + +/** + * Return the size in bytes of opaque data supproted version. + * + * This function should be called in KEY_EXCHANGE/PSK_EXCHANGE request generation. + * + * @return the size in bytes of opaque data supproted version. + **/ +size_t libspdm_get_opaque_data_supported_version_data_size(libspdm_context_t *spdm_context); + +/** + * Return the size in bytes of opaque data version selection. + * + * This function should be called in KEY_EXCHANGE/PSK_EXCHANGE response generation. + * + * @return the size in bytes of opaque data version selection. + **/ +size_t libspdm_get_opaque_data_version_selection_data_size(const libspdm_context_t *spdm_context); + +/** + * Return the SPDMversion field of the version number struct. + * + * @param ver Spdm version number struct. + * + * @return the SPDMversion of the version number struct. + **/ +uint8_t libspdm_get_version_from_version_number(const spdm_version_number_t ver); + +/** + * Sort SPDMversion in descending order. + * + * @param spdm_context A pointer to the SPDM context. + * @param ver_set A pointer to the version set. + * @param ver_num Version number. + */ +void libspdm_version_number_sort(spdm_version_number_t *ver_set, size_t ver_num); + +/** + * Negotiate SPDMversion for connection. + * ver_set is the local version set of requester, res_ver_set is the version set of responder. + * + * @param common_version A pointer to store the common version. + * @param req_ver_set A pointer to the requester version set. + * @param req_ver_num Version number of requester. + * @param res_ver_set A pointer to the responder version set. + * @param res_ver_num Version number of responder. + * + * @retval true Negotiation successfully, connect version be saved to common_version. + * @retval false Negotiation failed. + */ +bool libspdm_negotiate_connection_version(spdm_version_number_t *common_version, + spdm_version_number_t *req_ver_set, + size_t req_ver_num, + const spdm_version_number_t *res_ver_set, + size_t res_ver_num); + +/** + * Acquire a device sender buffer for transport layer message. + * + * @param context A pointer to the SPDM context. + * @param max_msg_size size in bytes of the maximum size of sender buffer. + * @param msg_buf_ptr A pointer to a sender buffer. + * + * @retval RETURN_SUCCESS The sender buffer is acquired. + **/ +libspdm_return_t libspdm_acquire_sender_buffer ( + libspdm_context_t *spdm_context, size_t *max_msg_size, void **msg_buf_ptr); + +/** + * Release a device sender buffer for transport layer message. + * + * @param context A pointer to the SPDM context. + * + * @retval RETURN_SUCCESS The sender buffer is Released. + **/ +void libspdm_release_sender_buffer (libspdm_context_t *spdm_context); + +/** + * Get the sender buffer. + * + * @param context A pointer to the SPDM context. + * @param sender_buffer Buffer address of the sender buffer. + * @param sender_buffer_size Size of the sender buffer. + * + **/ +void libspdm_get_sender_buffer ( + libspdm_context_t *spdm_context, + void **sender_buffer, + size_t *sender_buffer_size); + +/** + * Acquire a device receiver buffer for transport layer message. + * + * @param context A pointer to the SPDM context. + * @param max_msg_size size in bytes of the maximum size of receiver buffer. + * @param msg_buf_pt A pointer to a receiver buffer. + * + * @retval RETURN_SUCCESS The receiver buffer is acquired. + **/ +libspdm_return_t libspdm_acquire_receiver_buffer ( + libspdm_context_t *spdm_context, size_t *max_msg_size, void **msg_buf_ptr); + +/** + * Release a device receiver buffer for transport layer message. + * + * @param context A pointer to the SPDM context. + * + * @retval RETURN_SUCCESS The receiver buffer is Released. + **/ +void libspdm_release_receiver_buffer (libspdm_context_t *spdm_context); + +/** + * Get the receiver buffer. + * + * @param context A pointer to the SPDM context. + * @param receiver_buffer Buffer address of the receiver buffer. + * @param receiver_buffer_size Size of the receiver buffer. + * + **/ +void libspdm_get_receiver_buffer ( + libspdm_context_t *spdm_context, + void **receiver_buffer, + size_t *receiver_buffer_size); + +/** + * Get the certificate slot mask + * + * @param[in] context A pointer to the SPDM context. + * + * @retval slot_mask get slot mask + **/ +uint8_t libspdm_get_cert_slot_mask (libspdm_context_t *spdm_context); + +/** + * Get the certificate slot count + * + * @param[in] context A pointer to the SPDM context. + * + * @retval slot_count get slot count + **/ +uint8_t libspdm_get_cert_slot_count(libspdm_context_t *spdm_context); + +#if LIBSPDM_ENABLE_MSG_LOG +void libspdm_append_msg_log(void *context, void *message, size_t message_size); +#endif + +/** + * Reset message A cache in SPDM context. + * + * @param spdm_context A pointer to the SPDM context. + **/ +void libspdm_reset_message_a(void *spdm_context); + +/** + * Reset message B cache in SPDM context. + * + * @param spdm_context A pointer to the SPDM context. + **/ +void libspdm_reset_message_b(void *spdm_context); + +/** + * Reset message C cache in SPDM context. + * + * @param spdm_context A pointer to the SPDM context. + **/ +void libspdm_reset_message_c(void *spdm_context); + +/** + * Reset message MutB cache in SPDM context. + * + * @param spdm_context A pointer to the SPDM context. + **/ +void libspdm_reset_message_mut_b(void *spdm_context); + +/** + * Reset message MutC cache in SPDM context. + * + * @param spdm_context A pointer to the SPDM context. + **/ +void libspdm_reset_message_mut_c(void *spdm_context); + +/** + * Reset message M cache in SPDM context. + * If session_info is NULL, this function will use M cache of SPDM context, + * else will use M cache of SPDM session context. + * + * @param spdm_context A pointer to the SPDM context. + * @param session_info A pointer to the SPDM session context. + **/ +void libspdm_reset_message_m(void *context, void *session_info); + +/** + * Reset message K cache in SPDM context. + * + * @param spdm_context A pointer to the SPDM context. + * @param spdm_session_info A pointer to the SPDM session context. + **/ +void libspdm_reset_message_k(void *context, void *spdm_session_info); + +/** + * Reset message F cache in SPDM context. + * + * @param spdm_context A pointer to the SPDM context. + * @param spdm_session_info A pointer to the SPDM session context. + **/ +void libspdm_reset_message_f(void *context, void *spdm_session_info); + +/** + * Append message A cache in SPDM context. + * + * @param spdm_context A pointer to the SPDM context. + * @param message Message buffer. + * @param message_size Size in bytes of message buffer. + * + * @return RETURN_SUCCESS message is appended. + * @return RETURN_OUT_OF_RESOURCES message is not appended because the internal cache is full. + **/ +libspdm_return_t libspdm_append_message_a(void *spdm_context, const void *message, + size_t message_size); +/** + * Append message B cache in SPDM context. + * + * @param spdm_context A pointer to the SPDM context. + * @param message Message buffer. + * @param message_size Size in bytes of message buffer. + * + * @return RETURN_SUCCESS message is appended. + * @return RETURN_OUT_OF_RESOURCES message is not appended because the internal cache is full. + **/ +libspdm_return_t libspdm_append_message_b(void *spdm_context, const void *message, + size_t message_size); + +/** + * Append message C cache in SPDM context. + * + * @param spdm_context A pointer to the SPDM context. + * @param message Message buffer. + * @param message_size Size in bytes of message buffer. + * + * @return RETURN_SUCCESS message is appended. + * @return RETURN_OUT_OF_RESOURCES message is not appended because the internal cache is full. + **/ +libspdm_return_t libspdm_append_message_c(void *spdm_context, const void *message, + size_t message_size); + +/** + * Append message MutB cache in SPDM context. + * + * @param spdm_context A pointer to the SPDM context. + * @param message Message buffer. + * @param message_size Size in bytes of message buffer. + * + * @return RETURN_SUCCESS message is appended. + * @return RETURN_OUT_OF_RESOURCES message is not appended because the internal cache is full. + **/ +libspdm_return_t libspdm_append_message_mut_b(void *spdm_context, const void *message, + size_t message_size); + +/** + * Append message MutC cache in SPDM context. + * + * @param spdm_context A pointer to the SPDM context. + * @param message Message buffer. + * @param message_size Size in bytes of message buffer. + * + * @return RETURN_SUCCESS message is appended. + * @return RETURN_OUT_OF_RESOURCES message is not appended because the internal cache is full. + **/ +libspdm_return_t libspdm_append_message_mut_c(void *spdm_context, const void *message, + size_t message_size); + +/** + * Append message M cache in SPDM context. + * If session_info is NULL, this function will use M cache of SPDM context, + * else will use M cache of SPDM session context. + * + * @param spdm_context A pointer to the SPDM context. + * @param session_info A pointer to the SPDM session context. + * @param message Message buffer. + * @param message_size Size in bytes of message buffer. + * + * @return RETURN_SUCCESS message is appended. + * @return RETURN_OUT_OF_RESOURCES message is not appended because the internal cache is full. + **/ +libspdm_return_t libspdm_append_message_m(void *context, void *session_info, + const void *message, size_t message_size); + +/** + * Append message K cache in SPDM context. + * + * @param spdm_context A pointer to the SPDM context. + * @param spdm_session_info A pointer to the SPDM session context. + * @param is_requester Indicate of the key generation for a requester or a responder. + * @param message Message buffer. + * @param message_size Size in bytes of message buffer. + * + * @return RETURN_SUCCESS message is appended. + * @return RETURN_OUT_OF_RESOURCES message is not appended because the internal cache is full. + **/ +libspdm_return_t libspdm_append_message_k(void *context, void *spdm_session_info, + bool is_requester, const void *message, + size_t message_size); + +/** + * Append message F cache in SPDM context. + * + * @param spdm_context A pointer to the SPDM context. + * @param spdm_session_info A pointer to the SPDM session context. + * @param is_requester Indicate of the key generation for a requester or a responder. + * @param message Message buffer. + * @param message_size Size in bytes of message buffer. + * + * @return RETURN_SUCCESS message is appended. + * @return RETURN_OUT_OF_RESOURCES message is not appended because the internal cache is full. + **/ +libspdm_return_t libspdm_append_message_f(void *context, void *spdm_session_info, + bool is_requester, const void *message, + size_t message_size); + +/** + * This function generates a session ID by concatenating req_session_id and rsp_session_id. + * + * @param[in] req_session_id + * @param[in] rsp_session_id + * + * @return Session ID. + **/ +uint32_t libspdm_generate_session_id(uint16_t req_session_id, uint16_t rsp_session_id); + +/** + * This function assigns a new session ID. + * + * @param spdm_context A pointer to the SPDM context. + * @param session_id The SPDM session ID. + * + * @return session info associated with this new session ID. + **/ +void *libspdm_assign_session_id(void *spdm_context, uint32_t session_id, bool use_psk); + +/** + * This function frees a session ID. + * + * @param spdm_context A pointer to the SPDM context. + * @param session_id The SPDM session ID. + **/ +void libspdm_free_session_id(void *spdm_context, uint32_t session_id); + +#if LIBSPDM_RECORD_TRANSCRIPT_DATA_SUPPORT +/* + * This function calculates current TH data with message A and message K. + * + * @param spdm_context A pointer to the SPDM context. + * @param session_info The SPDM session ID. + * @param cert_chain_buffer Certitiface chain buffer with spdm_cert_chain_t header. + * @param cert_chain_buffer_size Size in bytes of the certitiface chain buffer. + * @param th_data_buffer_size Size in bytes of the th_data_buffer + * @param th_data_buffer The buffer to store the th_data_buffer + * + * @retval RETURN_SUCCESS current TH data is calculated. + */ +bool libspdm_calculate_th_for_exchange( + void *spdm_context, void *spdm_session_info, + const uint8_t *cert_chain_buffer, size_t cert_chain_buffer_size, + size_t *th_data_buffer_size, void *th_data_buffer); +#else +/* + * This function calculates current TH hash with message A and message K. + * + * @param spdm_context A pointer to the SPDM context. + * @param session_info The SPDM session ID. + * @param th_hash_buffer_size Size in bytes of the th_hash_buffer + * @param th_hash_buffer The buffer to store the th_hash_buffer + * + * @retval RETURN_SUCCESS current TH hash is calculated. + */ +bool libspdm_calculate_th_hash_for_exchange( + void *context, void *spdm_session_info, + size_t *th_hash_buffer_size, void *th_hash_buffer); + +/* + * This function calculates current TH hmac with message A and message K, with response finished_key. + * + * @param spdm_context A pointer to the SPDM context. + * @param session_info The SPDM session ID. + * @param th_hmac_buffer_size Size in bytes of the th_hmac_buffer + * @param th_hmac_buffer The buffer to store the th_hmac_buffer + * + * @retval RETURN_SUCCESS current TH hmac is calculated. + */ +bool libspdm_calculate_th_hmac_for_exchange_rsp( + void *context, void *spdm_session_info, bool is_requester, + size_t *th_hmac_buffer_size, void *th_hmac_buffer); +#endif + +#if LIBSPDM_RECORD_TRANSCRIPT_DATA_SUPPORT +/* + * This function calculates current TH data with message A, message K and message F. + * + * @param spdm_context A pointer to the SPDM context. + * @param session_info The SPDM session ID. + * @param cert_chain_buffer Certitiface chain buffer with spdm_cert_chain_t header. + * @param cert_chain_buffer_size Size in bytes of the certitiface chain buffer. + * @param mut_cert_chain_buffer Certitiface chain buffer with spdm_cert_chain_t header in mutual authentication. + * @param mut_cert_chain_buffer_size Size in bytes of the certitiface chain buffer in mutual authentication. + * @param th_data_buffer_size Size in bytes of the th_data_buffer. + * @param th_data_buffer The buffer to store the th_data_buffer + * + * @retval RETURN_SUCCESS current TH data is calculated. + */ +bool libspdm_calculate_th_for_finish(void *spdm_context, + void *spdm_session_info, + const uint8_t *cert_chain_buffer, + size_t cert_chain_buffer_size, + const uint8_t *mut_cert_chain_buffer, + size_t mut_cert_chain_buffer_size, + size_t *th_data_buffer_size, + void *th_data_buffer); +#else +/* + * This function calculates current TH hash with message A, message K and message F. + * + * @param spdm_context A pointer to the SPDM context. + * @param session_info The SPDM session ID. + * @param th_hash_buffer_size Size in bytes of the th_hash_buffer + * @param th_hash_buffer The buffer to store the th_hash_buffer + * + * @retval RETURN_SUCCESS current TH hash is calculated. + */ +bool libspdm_calculate_th_hash_for_finish(void *spdm_context, + void *spdm_session_info, + size_t *th_hash_buffer_size, + void *th_hash_buffer); + +/* + * This function calculates current TH hmac with message A, message K and message F, with response finished_key. + * + * @param spdm_context A pointer to the SPDM context. + * @param session_info The SPDM session ID. + * @param th_hmac_buffer_size Size in bytes of the th_hmac_buffer + * @param th_hmac_buffer The buffer to store the th_hmac_buffer + * + * @retval RETURN_SUCCESS current TH hmac is calculated. + */ +bool libspdm_calculate_th_hmac_for_finish_rsp(void *spdm_context, + void *spdm_session_info, + size_t *th_hmac_buffer_size, + void *th_hmac_buffer); + +/* + * This function calculates current TH hmac with message A, message K and message F, with request finished_key. + * + * @param spdm_context A pointer to the SPDM context. + * @param session_info The SPDM session ID. + * @param th_hmac_buffer_size Size in bytes of the th_hmac_buffer + * @param th_hmac_buffer The buffer to store the th_hmac_buffer + * + * @retval RETURN_SUCCESS current TH hmac is calculated. + */ +bool libspdm_calculate_th_hmac_for_finish_req(void *spdm_context, + void *spdm_session_info, + size_t *th_hmac_buffer_size, + void *th_hmac_buffer); +#endif + +/* + * This function calculates th1 hash. + * + * @param spdm_context A pointer to the SPDM context. + * @param session_info The SPDM session ID. + * @param is_requester Indicate of the key generation for a requester or a responder. + * @param th1_hash_data Th1 hash. + * + * @retval RETURN_SUCCESS th1 hash is calculated. + */ +bool libspdm_calculate_th1_hash(void *spdm_context, + void *spdm_session_info, + bool is_requester, + uint8_t *th1_hash_data); + +/* + * This function calculates th2 hash. + * + * @param spdm_context A pointer to the SPDM context. + * @param session_info The SPDM session ID. + * @param is_requester Indicate of the key generation for a requester or a responder. + * @param th1_hash_data Th2 hash + * + * @retval RETURN_SUCCESS th2 hash is calculated. + */ +bool libspdm_calculate_th2_hash(void *spdm_context, + void *spdm_session_info, + bool is_requester, + uint8_t *th2_hash_data); + +/** + * Reads a 24-bit value from memory that may be unaligned. + * + * @param buffer The pointer to a 24-bit value that may be unaligned. + * + * @return The 24-bit value read from buffer. + **/ +uint32_t libspdm_read_uint24(const uint8_t *buffer); + +/** + * Writes a 24-bit value to memory that may be unaligned. + * + * @param buffer The pointer to a 24-bit value that may be unaligned. + * @param value 24-bit value to write to buffer. + **/ +void libspdm_write_uint24(uint8_t *buffer, uint32_t value); + +/** + * Reads a 16-bit value from memory that may be unaligned. + * + * @param buffer The pointer to a 16-bit value that may be unaligned. + * + * @return The 16-bit value read from buffer. + **/ +uint16_t libspdm_read_uint16(const uint8_t *buffer); + +/** + * Writes a 16-bit value to memory that may be unaligned. + * + * @param buffer The pointer to a 16-bit value that may be unaligned. + * @param value 16-bit value to write to buffer. + **/ +void libspdm_write_uint16(uint8_t *buffer, uint16_t value); + +/** + * Reads a 32-bit value from memory that may be unaligned. + * + * @param buffer The pointer to a 32-bit value that may be unaligned. + * + * @return The 32-bit value read from buffer. + **/ +uint32_t libspdm_read_uint32(const uint8_t *buffer); + +/** + * Writes a 32-bit value to memory that may be unaligned. + * + * @param buffer The pointer to a 32-bit value that may be unaligned. + * @param value 32-bit value to write to buffer. + **/ +void libspdm_write_uint32(uint8_t *buffer, uint32_t value); + +/** + * Reads a 64-bit value from memory that may be unaligned. + * + * @param buffer The pointer to a 64-bit value that may be unaligned. + * + * @return The 64-bit value read from buffer. + **/ +uint64_t libspdm_read_uint64(const uint8_t *buffer); + +/** + * Writes a 64-bit value to memory that may be unaligned. + * + * @param buffer The pointer to a 64-bit value that may be unaligned. + * @param value 64-bit value to write to buffer. + **/ +void libspdm_write_uint64(uint8_t *buffer, uint64_t value); + +/** + * Determine if bitmask has at most one bit set. + * + * @param mask The bitmask to be tested. + * + * @return true At most one bit is set. + * @return false More than one bit is set. + */ +static inline bool libspdm_onehot0(uint32_t mask) +{ + return !mask || !(mask & (mask - 1)); +} + +#endif /* SPDM_COMMON_LIB_INTERNAL_H */ diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/libraries/libspdm/2.3.1/include/internal/libspdm_crypt_lib.h nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/libraries/libspdm/2.3.1/include/internal/libspdm_crypt_lib.h --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/libraries/libspdm/2.3.1/include/internal/libspdm_crypt_lib.h 1970-01-01 00:00:00.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/libraries/libspdm/2.3.1/include/internal/libspdm_crypt_lib.h 2024-03-05 22:14:12.000000000 +0000 @@ -0,0 +1,10 @@ +/** + * Copyright Notice: + * Copyright 2021-2022 DMTF. All rights reserved. + * License: BSD 3-Clause License. For full text see link: https://github.com/DMTF/libspdm/blob/main/LICENSE.md + **/ + +#include "library/spdm_crypt_lib.h" +#include "hal/library/cryptlib.h" +#include "hal/library/debuglib.h" +#include "hal/library/memlib.h" diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/libraries/libspdm/2.3.1/include/internal/libspdm_lib_config.h nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/libraries/libspdm/2.3.1/include/internal/libspdm_lib_config.h --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/libraries/libspdm/2.3.1/include/internal/libspdm_lib_config.h 1970-01-01 00:00:00.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/libraries/libspdm/2.3.1/include/internal/libspdm_lib_config.h 2024-03-05 22:14:13.000000000 +0000 @@ -0,0 +1,55 @@ +/** + * Copyright Notice: + * Copyright 2021-2022 DMTF. All rights reserved. + * License: BSD 3-Clause License. For full text see link: https://github.com/DMTF/libspdm/blob/main/LICENSE.md + **/ + +#ifndef LIBSPDM_LIB_CONFIG_H +#define LIBSPDM_LIB_CONFIG_H + +#ifndef LIBSPDM_CONFIG +#include "library/spdm_lib_config.h" +#else +#include LIBSPDM_CONFIG +#endif + +#if defined(LIBSPDM_ENABLE_SET_CERTIFICATE_CAP) && \ + !defined(LIBSPDM_ENABLE_CAPABILITY_SET_CERTIFICATE_CAP) +#warning LIBSPDM_ENABLE_SET_CERTIFICATE_CAP is deprecated. Use \ + LIBSPDM_ENABLE_CAPABILITY_SET_CERTIFICATE_CAP instead. This warning will be removed in a \ + future release. +#endif /* defined(LIBSPDM_ENABLE_SET_CERTIFICATE_CAP) */ + +#if defined(LIBSPDM_ENABLE_CHUNK_CAP) && !defined(LIBSPDM_ENABLE_CAPABILITY_CHUNK_CAP) +#warning LIBSPDM_ENABLE_CHUNK_CAP is deprecated. Use LIBSPDM_ENABLE_CAPABILITY_CHUNK_CAP \ + instead. This warning will be removed in a future release. +#endif /* defined(LIBSPDM_ENABLE_CHUNK_CAP) */ + +#if defined(MDEPKG_NDEBUG) && !defined(LIBSPDM_DEBUG_ENABLE) +#warning MDEPKG_NDEBUG is deprecated. Use LIBSPDM_DEBUG_ENABLE \ + instead. This warning will be removed in a future release. +#endif /* defined(MDEPKG_NDEBUG) */ + +#if defined(LIBSPDM_DEBUG_ENABLE) +#undef LIBSPDM_DEBUG_ASSERT_ENABLE +#undef LIBSPDM_DEBUG_PRINT_ENABLE +#undef LIBSPDM_DEBUG_BLOCK_ENABLE + +#define LIBSPDM_DEBUG_ASSERT_ENABLE (LIBSPDM_DEBUG_ENABLE) +#define LIBSPDM_DEBUG_PRINT_ENABLE (LIBSPDM_DEBUG_ENABLE) +#define LIBSPDM_DEBUG_BLOCK_ENABLE (LIBSPDM_DEBUG_ENABLE) +#elif defined(MDEPKG_NDEBUG) +#undef LIBSPDM_DEBUG_ASSERT_ENABLE +#undef LIBSPDM_DEBUG_PRINT_ENABLE +#undef LIBSPDM_DEBUG_BLOCK_ENABLE + +#define LIBSPDM_DEBUG_ASSERT_ENABLE 0 +#define LIBSPDM_DEBUG_PRINT_ENABLE 0 +#define LIBSPDM_DEBUG_BLOCK_ENABLE 0 +#endif /* defined(LIBSPDM_DEBUG_ENABLE) */ + +#if LIBSPDM_CHECK_MACRO +#include "internal/libspdm_macro_check.h" +#endif /* LIBSPDM_CHECK_MACRO */ + +#endif /* LIBSPDM_LIB_CONFIG_H */ diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/libraries/libspdm/2.3.1/include/internal/libspdm_macro_check.h nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/libraries/libspdm/2.3.1/include/internal/libspdm_macro_check.h --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/libraries/libspdm/2.3.1/include/internal/libspdm_macro_check.h 1970-01-01 00:00:00.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/libraries/libspdm/2.3.1/include/internal/libspdm_macro_check.h 2024-03-05 22:14:13.000000000 +0000 @@ -0,0 +1,44 @@ +/** + * Copyright Notice: + * Copyright 2021-2022 DMTF. All rights reserved. + * License: BSD 3-Clause License. For full text see link: https://github.com/DMTF/libspdm/blob/main/LICENSE.md + **/ + +#ifndef LIBSPDM_MACRO_CHECK_H +#define LIBSPDM_MACRO_CHECK_H + +#define LIBSPDM_ASYM_ALGO_SUPPORT \ + ((LIBSPDM_RSA_SSA_SUPPORT) || (LIBSPDM_RSA_PSS_SUPPORT) || (LIBSPDM_ECDSA_SUPPORT) || \ + (LIBSPDM_SM2_DSA_SUPPORT) || (LIBSPDM_EDDSA_ED25519_SUPPORT) || (LIBSPDM_EDDSA_ED448_SUPPORT)) + +#define LIBSPDM_DHE_ALGO_SUPPORT \ + ((LIBSPDM_FFDHE_SUPPORT) || (LIBSPDM_ECDHE_SUPPORT) || (LIBSPDM_SM2_KEY_EXCHANGE_SUPPORT)) + +#if (LIBSPDM_ENABLE_CAPABILITY_KEY_EX_CAP) && !LIBSPDM_ASYM_ALGO_SUPPORT + #error If KEY_EX_CAP is enabled then at least one asymmetric algorithm must also be enabled. +#endif + +#if (LIBSPDM_ENABLE_CAPABILITY_CERT_CAP) && !LIBSPDM_ASYM_ALGO_SUPPORT + #error If CERT_CAP is enabled then at least one asymmetric algorithm must also be enabled. +#endif + +#if (LIBSPDM_ENABLE_CAPABILITY_CHAL_CAP) && !LIBSPDM_ASYM_ALGO_SUPPORT + #error If CHAL_CAP is enabled then at least one asymmetric algorithm must also be enabled. +#endif + +#if (LIBSPDM_ENABLE_CAPABILITY_KEY_EX_CAP) && !LIBSPDM_DHE_ALGO_SUPPORT + #error If KEY_EX_CAP is enabled then at least one DHE algorithm must also be enabled. +#endif + +#if ((LIBSPDM_MAX_VERSION_COUNT) == 0) || ((LIBSPDM_MAX_VERSION_COUNT) > 255) + #error LIBSPDM_MAX_VERSION_COUNT must be between 1 and 255 inclusive. +#endif + +#if (LIBSPDM_MAX_SESSION_COUNT) > 65535 + #error LIBSPDM_MAX_SESSION_COUNT must be less than 65536. +#endif + +#undef LIBSPDM_ASYM_ALGO_SUPPORT +#undef LIBSPDM_DHE_ALGO_SUPPORT + +#endif /* LIBSPDM_MACRO_CHECK_H */ diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/libraries/libspdm/2.3.1/include/internal/libspdm_requester_lib.h nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/libraries/libspdm/2.3.1/include/internal/libspdm_requester_lib.h --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/libraries/libspdm/2.3.1/include/internal/libspdm_requester_lib.h 1970-01-01 00:00:00.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/libraries/libspdm/2.3.1/include/internal/libspdm_requester_lib.h 2024-03-05 22:14:13.000000000 +0000 @@ -0,0 +1,555 @@ +/** + * Copyright Notice: + * Copyright 2021-2022 DMTF. All rights reserved. + * License: BSD 3-Clause License. For full text see link: https://github.com/DMTF/libspdm/blob/main/LICENSE.md + **/ + +#ifndef SPDM_REQUESTER_LIB_INTERNAL_H +#define SPDM_REQUESTER_LIB_INTERNAL_H + +#include "library/spdm_requester_lib.h" +#include "library/spdm_secured_message_lib.h" +#include "internal/libspdm_common_lib.h" + +/** + * This function handles simple error code. + * + * @param spdm_context A pointer to the SPDM context. + * @param error_code Indicate the error code. + * + * @retval RETURN_NO_RESPONSE If the error code is BUSY. + * @retval RETURN_DEVICE_ERROR If the error code is REQUEST_RESYNCH or others. + **/ +libspdm_return_t libspdm_handle_simple_error_response(void *context, uint8_t error_code); + +/** + * This function handles the error response. + * + * The SPDM response code must be SPDM_ERROR. + * For error code RESPONSE_NOT_READY, this function sends RESPOND_IF_READY and receives an expected SPDM response. + * For error code BUSY, this function shrinks the managed buffer, and return RETURN_NO_RESPONSE. + * For error code REQUEST_RESYNCH, this function shrinks the managed buffer, clears connection_state, and return RETURN_DEVICE_ERROR. + * For error code DECRYPT_ERROR, end the session: free session id and session key, return RETURN_SECURITY_VIOLATION. + * For any other error code, this function shrinks the managed buffer, and return RETURN_DEVICE_ERROR. + * + * @param spdm_context A pointer to the SPDM context. + * @param session_id Indicates if it is a secured message protected via SPDM session. + * If session_id is NULL, it is a normal message. + * If session_id is NOT NULL, it is a secured message. + * @param response_size The size of the response. + * On input, it means the size in bytes of response data buffer. + * On output, it means the size in bytes of copied response data buffer if RETURN_SUCCESS is returned. + * @param response The SPDM response message. + * @param original_request_code Indicate the original request code. + * @param expected_response_code Indicate the expected response code. + * @param expected_response_size Indicate the expected response size. + * + * @retval RETURN_SUCCESS The error code is RESPONSE_NOT_READY. The RESPOND_IF_READY is sent and an expected SPDM response is received. + * @retval RETURN_NO_RESPONSE The error code is BUSY. + * @retval RETURN_DEVICE_ERROR The error code is REQUEST_RESYNCH or others. + * @retval RETURN_DEVICE_ERROR A device error occurs when communicates with the device. + * @retval RETURN_SECURITY_VIOLATION The error code is DECRYPT_ERROR and session_id is NOT NULL. + **/ +libspdm_return_t libspdm_handle_error_response_main( + libspdm_context_t *spdm_context, const uint32_t *session_id, + size_t *response_size, void **response, + uint8_t original_request_code, uint8_t expected_response_code, + size_t expected_response_size); + +/** + * This function handles the error response handling for large responses. + * Will retrieve the large response in chunks if supported and necessary. + * + * @param spdm_context A pointer to the SPDM context. + * @param session_id Indicates if it is a secured message protected via SPDM session. + * If session_id is NULL, it is a normal message. + * If session_id is NOT NULL, it is a secured message. + * @param inout_response_size The size of the response. + * On input, expected to be the size of an error response. + * On output, the large response size after being retrieved in chunks. + * @param response The error response on input. Large response on output. + * @param response_capacity The maximum capacity of the response buffer. + * + * @retval libspdm_return_t An error value or success. + **/ +libspdm_return_t libspdm_handle_error_large_response( + libspdm_context_t* spdm_context, + const uint32_t* session_id, + size_t* inout_response_size, + void* inout_response, + size_t response_capacity); + +/** + * This function sends GET_VERSION and receives VERSION. + * + * @param spdm_context A pointer to the SPDM context. + * + * @retval RETURN_SUCCESS The GET_VERSION is sent and the VERSION is received. + * @retval RETURN_DEVICE_ERROR A device error occurs when communicates with the device. + **/ +libspdm_return_t libspdm_get_version(libspdm_context_t *spdm_context, + uint8_t *version_number_entry_count, + spdm_version_number_t *version_number_entry); + +/** + * This function sends GET_CAPABILITIES and receives CAPABILITIES. + * + * @param spdm_context A pointer to the SPDM context. + * @param RequesterCTExponent RequesterCTExponent to the GET_CAPABILITIES request. + * @param RequesterFlags RequesterFlags to the GET_CAPABILITIES request. + * @param ResponderCTExponent ResponderCTExponent from the CAPABILITIES response. + * @param ResponderFlags ResponderFlags from the CAPABILITIES response. + * + * @retval RETURN_SUCCESS The GET_CAPABILITIES is sent and the CAPABILITIES is received. + * @retval RETURN_DEVICE_ERROR A device error occurs when communicates with the device. + **/ +libspdm_return_t libspdm_get_capabilities(libspdm_context_t *spdm_context); + +/** + * This function sends NEGOTIATE_ALGORITHMS and receives ALGORITHMS. + * + * @param spdm_context A pointer to the SPDM context. + * + * @retval RETURN_SUCCESS The NEGOTIATE_ALGORITHMS is sent and the ALGORITHMS is received. + * @retval RETURN_DEVICE_ERROR A device error occurs when communicates with the device. + **/ +libspdm_return_t libspdm_negotiate_algorithms(libspdm_context_t *spdm_context); + +#if LIBSPDM_ENABLE_CAPABILITY_KEY_EX_CAP +/** + * This function sends KEY_EXCHANGE and receives KEY_EXCHANGE_RSP for SPDM key exchange. + * + * @param spdm_context A pointer to the SPDM context. + * @param measurement_hash_type measurement_hash_type to the KEY_EXCHANGE request. + * @param slot_id slot_id to the KEY_EXCHANGE request. + * @param session_policy The policy for the session. + * @param session_id session_id from the KEY_EXCHANGE_RSP response. + * @param heartbeat_period heartbeat_period from the KEY_EXCHANGE_RSP response. + * @param req_slot_id_param req_slot_id_param from the KEY_EXCHANGE_RSP response. + * @param measurement_hash measurement_hash from the KEY_EXCHANGE_RSP response. + * + * @retval RETURN_SUCCESS The KEY_EXCHANGE is sent and the KEY_EXCHANGE_RSP is received. + * @retval RETURN_DEVICE_ERROR A device error occurs when communicates with the device. + **/ +libspdm_return_t libspdm_send_receive_key_exchange( + libspdm_context_t *spdm_context, uint8_t measurement_hash_type, + uint8_t slot_id, uint8_t session_policy, uint32_t *session_id, + uint8_t *heartbeat_period, + uint8_t *req_slot_id_param, void *measurement_hash); + +/** + * This function sends KEY_EXCHANGE and receives KEY_EXCHANGE_RSP for SPDM key exchange. + * + * @param spdm_context A pointer to the SPDM context. + * @param measurement_hash_type measurement_hash_type to the KEY_EXCHANGE request. + * @param slot_id slot_id to the KEY_EXCHANGE request. + * @param session_policy The policy for the session. + * @param session_id session_id from the KEY_EXCHANGE_RSP response. + * @param heartbeat_period heartbeat_period from the KEY_EXCHANGE_RSP response. + * @param req_slot_id_param req_slot_id_param from the KEY_EXCHANGE_RSP response. + * @param measurement_hash measurement_hash from the KEY_EXCHANGE_RSP response. + * @param requester_random_in A buffer to hold the requester random (32 bytes) as input, if not NULL. + * @param requester_random A buffer to hold the requester random (32 bytes), if not NULL. + * @param responder_random A buffer to hold the responder random (32 bytes), if not NULL. + * + * @retval RETURN_SUCCESS The KEY_EXCHANGE is sent and the KEY_EXCHANGE_RSP is received. + * @retval RETURN_DEVICE_ERROR A device error occurs when communicates with the device. + **/ +libspdm_return_t libspdm_send_receive_key_exchange_ex( + libspdm_context_t *spdm_context, uint8_t measurement_hash_type, + uint8_t slot_id, uint8_t session_policy, uint32_t *session_id, + uint8_t *heartbeat_period, + uint8_t *req_slot_id_param, void *measurement_hash, + const void *requester_random_in, + void *requester_random, + void *responder_random); + +/** + * This function sends FINISH and receives FINISH_RSP for SPDM finish. + * + * @param spdm_context A pointer to the SPDM context. + * @param session_id session_id to the FINISH request. + * @param req_slot_id_param req_slot_id_param to the FINISH request. + * + * @retval RETURN_SUCCESS The FINISH is sent and the FINISH_RSP is received. + * @retval RETURN_DEVICE_ERROR A device error occurs when communicates with the device. + **/ +libspdm_return_t libspdm_send_receive_finish(libspdm_context_t *spdm_context, + uint32_t session_id, + uint8_t req_slot_id_param); +#endif /* LIBSPDM_ENABLE_CAPABILITY_KEY_EX_CAP */ + +#if LIBSPDM_ENABLE_CAPABILITY_PSK_EX_CAP +/** + * This function sends PSK_EXCHANGE and receives PSK_EXCHANGE_RSP for SPDM PSK exchange. + * + * @param spdm_context A pointer to the SPDM context. + * @param measurement_hash_type measurement_hash_type to the PSK_EXCHANGE request. + * @param session_policy The policy for the session. + * @param session_id session_id from the PSK_EXCHANGE_RSP response. + * @param heartbeat_period heartbeat_period from the PSK_EXCHANGE_RSP response. + * @param measurement_hash measurement_hash from the PSK_EXCHANGE_RSP response. + * + * @retval RETURN_SUCCESS The PSK_EXCHANGE is sent and the PSK_EXCHANGE_RSP is received. + * @retval RETURN_DEVICE_ERROR A device error occurs when communicates with the device. + **/ +libspdm_return_t libspdm_send_receive_psk_exchange(libspdm_context_t *spdm_context, + uint8_t measurement_hash_type, + uint8_t session_policy, + uint32_t *session_id, + uint8_t *heartbeat_period, + void *measurement_hash); + +/** + * This function sends PSK_EXCHANGE and receives PSK_EXCHANGE_RSP for SPDM PSK exchange. + * + * @param spdm_context A pointer to the SPDM context. + * @param measurement_hash_type measurement_hash_type to the PSK_EXCHANGE request. + * @param session_policy The policy for the session. + * @param session_id session_id from the PSK_EXCHANGE_RSP response. + * @param heartbeat_period heartbeat_period from the PSK_EXCHANGE_RSP response. + * @param measurement_hash measurement_hash from the PSK_EXCHANGE_RSP response. + * @param requester_context_in A buffer to hold the requester context as input, if not NULL. + * @param requester_context_in_size The size of requester_context_in. + * It must be 32 bytes at least, but not exceed LIBSPDM_PSK_CONTEXT_LENGTH. + * @param requester_context A buffer to hold the requester context, if not NULL. + * @param requester_context_size On input, the size of requester_context buffer. + * On output, the size of data returned in requester_context buffer. + * It must be 32 bytes at least. + * @param responder_context A buffer to hold the responder context, if not NULL. + * @param responder_context_size On input, the size of requester_context buffer. + * On output, the size of data returned in requester_context buffer. + * It could be 0 if device does not support context. + * + * @retval RETURN_SUCCESS The PSK_EXCHANGE is sent and the PSK_EXCHANGE_RSP is received. + * @retval RETURN_DEVICE_ERROR A device error occurs when communicates with the device. + **/ +libspdm_return_t libspdm_send_receive_psk_exchange_ex(libspdm_context_t *spdm_context, + uint8_t measurement_hash_type, + uint8_t session_policy, + uint32_t *session_id, + uint8_t *heartbeat_period, + void *measurement_hash, + const void *requester_context_in, + size_t requester_context_in_size, + void *requester_context, + size_t *requester_context_size, + void *responder_context, + size_t *responder_context_size); + +/** + * This function sends PSK_FINISH and receives PSK_FINISH_RSP for SPDM PSK finish. + * + * @param spdm_context A pointer to the SPDM context. + * @param session_id session_id to the PSK_FINISH request. + * + * @retval RETURN_SUCCESS The PSK_FINISH is sent and the PSK_FINISH_RSP is received. + * @retval RETURN_DEVICE_ERROR A device error occurs when communicates with the device. + **/ +libspdm_return_t libspdm_send_receive_psk_finish(libspdm_context_t *spdm_context, + uint32_t session_id); +#endif /* LIBSPDM_ENABLE_CAPABILITY_PSK_EX_CAP */ + +#if (LIBSPDM_ENABLE_CAPABILITY_KEY_EX_CAP) || (LIBSPDM_ENABLE_CAPABILITY_PSK_EX_CAP) +/** + * This function sends END_SESSION and receives END_SESSION_ACK for SPDM session end. + * + * @param spdm_context A pointer to the SPDM context. + * @param session_id session_id to the END_SESSION request. + * @param end_session_attributes end_session_attributes to the END_SESSION_ACK request. + * + * @retval RETURN_SUCCESS The END_SESSION is sent and the END_SESSION_ACK is received. + * @retval RETURN_DEVICE_ERROR A device error occurs when communicates with the device. + **/ +libspdm_return_t libspdm_send_receive_end_session(libspdm_context_t *spdm_context, + uint32_t session_id, + uint8_t end_session_attributes); +#endif /* (LIBSPDM_ENABLE_CAPABILITY_KEY_EX_CAP) || (LIBSPDM_ENABLE_CAPABILITY_PSK_EX_CAP) */ + +#if (LIBSPDM_ENABLE_CAPABILITY_MUT_AUTH_CAP) || (LIBSPDM_ENABLE_CAPABILITY_ENCAP_CAP) +/** + * This function executes a series of SPDM encapsulated requests and receives SPDM encapsulated responses. + * + * This function starts with the first encapsulated request (such as GET_ENCAPSULATED_REQUEST) + * and ends with last encapsulated response (such as RESPONSE_PAYLOAD_TYPE_ABSENT or RESPONSE_PAYLOAD_TYPE_SLOT_NUMBER). + * + * @param spdm_context A pointer to the SPDM context. + * @param session_id Indicate if the encapsulated request is a secured message. + * If session_id is NULL, it is a normal message. + * If session_id is NOT NULL, it is a secured message. + * @param mut_auth_requested Indicate of the mut_auth_requested through KEY_EXCHANGE or CHALLENG response. + * @param req_slot_id_param req_slot_id_param from the RESPONSE_PAYLOAD_TYPE_REQ_SLOT_NUMBER. + * + * @retval RETURN_SUCCESS The SPDM Encapsulated requests are sent and the responses are received. + * @retval RETURN_DEVICE_ERROR A device error occurs when communicates with the device. + **/ +libspdm_return_t libspdm_encapsulated_request(libspdm_context_t *spdm_context, + const uint32_t *session_id, + uint8_t mut_auth_requested, + uint8_t *req_slot_id_param); + +/** + * Process the SPDM encapsulated GET_DIGESTS request and return the response. + * + * @param spdm_context A pointer to the SPDM context. + * @param request_size size in bytes of the request data. + * @param request A pointer to the request data. + * @param response_size size in bytes of the response data. + * On input, it means the size in bytes of response data buffer. + * On output, it means the size in bytes of copied response data buffer if RETURN_SUCCESS is returned, + * and means the size in bytes of desired response data buffer if RETURN_BUFFER_TOO_SMALL is returned. + * @param response A pointer to the response data. + * + * @retval RETURN_SUCCESS The request is processed and the response is returned. + * @retval RETURN_BUFFER_TOO_SMALL The buffer is too small to hold the data. + * @retval RETURN_DEVICE_ERROR A device error occurs when communicates with the device. + * @retval RETURN_SECURITY_VIOLATION Any verification fails. + **/ +libspdm_return_t libspdm_get_encap_response_digest(void *context, + size_t request_size, + void *request, + size_t *response_size, + void *response); + +/** + * Process the SPDM encapsulated GET_CERTIFICATE request and return the response. + * + * @param spdm_context A pointer to the SPDM context. + * @param request_size size in bytes of the request data. + * @param request A pointer to the request data. + * @param response_size size in bytes of the response data. + * On input, it means the size in bytes of response data buffer. + * On output, it means the size in bytes of copied response data buffer if RETURN_SUCCESS is returned, + * and means the size in bytes of desired response data buffer if RETURN_BUFFER_TOO_SMALL is returned. + * @param response A pointer to the response data. + * + * @retval RETURN_SUCCESS The request is processed and the response is returned. + * @retval RETURN_BUFFER_TOO_SMALL The buffer is too small to hold the data. + * @retval RETURN_DEVICE_ERROR A device error occurs when communicates with the device. + * @retval RETURN_SECURITY_VIOLATION Any verification fails. + **/ +libspdm_return_t libspdm_get_encap_response_certificate(void *context, + size_t request_size, + void *request, + size_t *response_size, + void *response); + +/** + * Process the SPDM encapsulated CHALLENGE request and return the response. + * + * @param spdm_context A pointer to the SPDM context. + * @param request_size size in bytes of the request data. + * @param request A pointer to the request data. + * @param response_size size in bytes of the response data. + * On input, it means the size in bytes of response data buffer. + * On output, it means the size in bytes of copied response data buffer if RETURN_SUCCESS is returned, + * and means the size in bytes of desired response data buffer if RETURN_BUFFER_TOO_SMALL is returned. + * @param response A pointer to the response data. + * + * @retval RETURN_SUCCESS The request is processed and the response is returned. + * @retval RETURN_BUFFER_TOO_SMALL The buffer is too small to hold the data. + * @retval RETURN_DEVICE_ERROR A device error occurs when communicates with the device. + * @retval RETURN_SECURITY_VIOLATION Any verification fails. + **/ +libspdm_return_t libspdm_get_encap_response_challenge_auth( + void *context, size_t request_size, void *request, + size_t *response_size, void *response); + +/** + * Process the SPDM encapsulated KEY_UPDATE request and return the response. + * + * @param spdm_context A pointer to the SPDM context. + * @param request_size size in bytes of the request data. + * @param request A pointer to the request data. + * @param response_size size in bytes of the response data. + * On input, it means the size in bytes of response data buffer. + * On output, it means the size in bytes of copied response data buffer if RETURN_SUCCESS is returned, + * and means the size in bytes of desired response data buffer if RETURN_BUFFER_TOO_SMALL is returned. + * @param response A pointer to the response data. + * + * @retval RETURN_SUCCESS The request is processed and the response is returned. + * @retval RETURN_BUFFER_TOO_SMALL The buffer is too small to hold the data. + * @retval RETURN_DEVICE_ERROR A device error occurs when communicates with the device. + * @retval RETURN_SECURITY_VIOLATION Any verification fails. + **/ +libspdm_return_t libspdm_get_encap_response_key_update(void *context, + size_t request_size, + void *request, + size_t *response_size, + void *response); +#endif /* (LIBSPDM_ENABLE_CAPABILITY_MUT_AUTH_CAP) || (LIBSPDM_ENABLE_CAPABILITY_ENCAP_CAP)*/ + +/** + * Send an SPDM request to a device. + * + * @param spdm_context The SPDM context for the device. + * @param session_id Indicate if the request is a secured message. + * If session_id is NULL, it is a normal message. + * If session_id is NOT NULL, it is a secured message. + * @param request_size size in bytes of the request data buffer. + * @param request A pointer to a destination buffer to store the request. + * The caller is responsible for having + * either implicit or explicit ownership of the buffer. + * For normal message, requester pointer point to transport_message + transport header size + * For secured message, requester pointer will point to the scratch buffer + transport header size in spdm_context. + * + * @retval RETURN_SUCCESS The SPDM request is sent successfully. + * @retval RETURN_DEVICE_ERROR A device error occurs when the SPDM request is sent to the device. + **/ +libspdm_return_t libspdm_send_spdm_request(libspdm_context_t *spdm_context, + const uint32_t *session_id, + size_t request_size, void *request); + +/** + * Receive an SPDM response from a device. + * + * @param spdm_context The SPDM context for the device. + * @param session_id Indicate if the response is a secured message. + * If session_id is NULL, it is a normal message. + * If session_id is NOT NULL, it is a secured message. + * @param response_size size in bytes of the response data buffer. + * @param response A pointer to a destination buffer to store the response. + * The caller is responsible for having + * either implicit or explicit ownership of the buffer. + * For normal message, response pointer still point to original transport_message. + * For secured message, response pointer will point to the scratch buffer in spdm_context. + * + * @retval RETURN_SUCCESS The SPDM response is received successfully. + * @retval RETURN_DEVICE_ERROR A device error occurs when the SPDM response is received from the device. + **/ +libspdm_return_t libspdm_receive_spdm_response(libspdm_context_t *spdm_context, + const uint32_t *session_id, + size_t *response_size, + void **response); + +/** + * This function allocates half of session ID for a requester. + * + * @param spdm_context A pointer to the SPDM context. + * + * @return half of session ID for a requester. + **/ +uint16_t libspdm_allocate_req_session_id(libspdm_context_t *spdm_context); + +/** + * Build opaque data supported version. + * + * This function should be called in KEY_EXCHANGE/PSK_EXCHANGE request generation. + * + * @param data_out_size Size in bytes of the data_out. + * On input, it means the size in bytes of data_out buffer. + * On output, it means the size in bytes of copied data_out buffer if RETURN_SUCCESS is returned, + * and means the size in bytes of desired data_out buffer if RETURN_BUFFER_TOO_SMALL is returned. + * @param data_out A pointer to the desination buffer to store the opaque data supported version. + **/ +libspdm_return_t libspdm_build_opaque_data_supported_version_data(libspdm_context_t *spdm_context, + size_t *data_out_size, + void *data_out); + +/** + * Process opaque data version selection. + * + * This function should be called in KEY_EXCHANGE/PSK_EXCHANGE response parsing in requester. + * + * @param data_in_size Size in bytes of the data_in. + * @param data_in A pointer to the buffer to store the opaque data version selection. + **/ +libspdm_return_t libspdm_process_opaque_data_version_selection_data(libspdm_context_t *spdm_context, + size_t data_in_size, + void *data_in); + +#if LIBSPDM_ENABLE_CAPABILITY_MUT_AUTH_CAP +/** + * This function generates the finish signature based upon TH. + * + * @param spdm_context A pointer to the SPDM context. + * @param session_info The session info of an SPDM session. + * @param signature The buffer to store the finish signature. + * + * @retval true finish signature is generated. + * @retval false finish signature is not generated. + **/ +bool libspdm_generate_finish_req_signature(libspdm_context_t *spdm_context, + libspdm_session_info_t *session_info, + uint8_t *signature); +#endif + +/** + * This function generates the finish HMAC based upon TH. + * + * @param spdm_context A pointer to the SPDM context. + * @param session_info The session info of an SPDM session. + * @param hmac The buffer to store the finish HMAC. + * + * @retval true finish HMAC is generated. + * @retval false finish HMAC is not generated. + **/ +bool libspdm_generate_finish_req_hmac(libspdm_context_t *spdm_context, + libspdm_session_info_t *session_info, + void *hmac); + +/** + * This function verifies the finish HMAC based upon TH. + * + * @param spdm_context A pointer to the SPDM context. + * @param session_info The session info of an SPDM session. + * @param hmac_data The HMAC data buffer. + * @param hmac_data_size Size in bytes of the HMAC data buffer. + * + * @retval true HMAC verification pass. + * @retval false HMAC verification fail. + **/ +bool libspdm_verify_finish_rsp_hmac(libspdm_context_t *spdm_context, + libspdm_session_info_t *session_info, + const void *hmac_data, size_t hmac_data_size); + +/** + * This function verifies the key exchange HMAC based upon TH. + * + * @param spdm_context A pointer to the SPDM context. + * @param session_info The session info of an SPDM session. + * @param hmac_data The HMAC data buffer. + * @param hmac_data_size Size in bytes of the HMAC data buffer. + * + * @retval true HMAC verification pass. + * @retval false HMAC verification fail. + **/ +bool libspdm_verify_key_exchange_rsp_hmac(libspdm_context_t *spdm_context, + libspdm_session_info_t *session_info, + const void *hmac_data, + size_t hmac_data_size); + +/** + * This function verifies the key exchange signature based upon TH. + * + * @param spdm_context A pointer to the SPDM context. + * @param session_info The session info of an SPDM session. + * @param sign_data The signature data buffer. + * @param sign_data_size size in bytes of the signature data buffer. + * + * @retval true signature verification pass. + * @retval false signature verification fail. + **/ +bool libspdm_verify_key_exchange_rsp_signature( + libspdm_context_t *spdm_context, libspdm_session_info_t *session_info, + const void *sign_data, const size_t sign_data_size); + +/** + * This function verifies the measurement signature based upon l1l2. + * If session_info is NULL, this function will use M cache of SPDM context, + * else will use M cache of SPDM session context. + * + * @param spdm_context A pointer to the SPDM context. + * @param session_info A pointer to the SPDM session context. + * @param sign_data The signature data buffer. + * @param sign_data_size size in bytes of the signature data buffer. + * + * @retval true signature verification pass. + * @retval false signature verification fail. + **/ +bool libspdm_verify_measurement_signature(libspdm_context_t *spdm_context, + libspdm_session_info_t *session_info, + const void *sign_data, + size_t sign_data_size); + +#endif /* SPDM_REQUESTER_LIB_INTERNAL_H */ diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/libraries/libspdm/2.3.1/include/internal/libspdm_responder_lib.h nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/libraries/libspdm/2.3.1/include/internal/libspdm_responder_lib.h --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/libraries/libspdm/2.3.1/include/internal/libspdm_responder_lib.h 1970-01-01 00:00:00.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/libraries/libspdm/2.3.1/include/internal/libspdm_responder_lib.h 2024-03-05 22:14:13.000000000 +0000 @@ -0,0 +1,870 @@ +/** + * Copyright Notice: + * Copyright 2021-2022 DMTF. All rights reserved. + * License: BSD 3-Clause License. For full text see link: https://github.com/DMTF/libspdm/blob/main/LICENSE.md + **/ + +#ifndef SPDM_RESPONDER_LIB_INTERNAL_H +#define SPDM_RESPONDER_LIB_INTERNAL_H + +#include "library/spdm_responder_lib.h" +#include "library/spdm_secured_message_lib.h" +#include "internal/libspdm_common_lib.h" + +/** + * Process the SPDM request and return the response. + * + * @param spdm_context A pointer to the SPDM context. + * @param request_size size in bytes of the request data. + * @param request A pointer to the request data. + * @param response_size size in bytes of the response data. + * On input, it means the size in bytes of response data buffer. + * On output, it means the size in bytes of copied response data buffer if RETURN_SUCCESS is returned, + * and means the size in bytes of desired response data buffer if RETURN_BUFFER_TOO_SMALL is returned. + * @param response A pointer to the response data. + * + * @retval RETURN_SUCCESS The request is processed and the response is returned. + * @retval RETURN_BUFFER_TOO_SMALL The buffer is too small to hold the data. + * @retval RETURN_DEVICE_ERROR A device error occurs when communicates with the device. + * @retval RETURN_SECURITY_VIOLATION Any verification fails. + **/ +typedef libspdm_return_t (*libspdm_get_spdm_response_func)( + void *spdm_context, size_t request_size, const void *request, + size_t *response_size, void *response); + +/** + * Build the response when the response state is incorrect. + * + * @param spdm_context A pointer to the SPDM context. + * @param request_code The SPDM request code. + * @param response_size size in bytes of the response data. + * On input, it means the size in bytes of response data buffer. + * On output, it means the size in bytes of copied response data buffer if RETURN_SUCCESS is returned, + * and means the size in bytes of desired response data buffer if RETURN_BUFFER_TOO_SMALL is returned. + * @param response A pointer to the response data. + * + * @retval RETURN_SUCCESS The response is returned. + * @retval RETURN_BUFFER_TOO_SMALL The buffer is too small to hold the data. + * @retval RETURN_DEVICE_ERROR A device error occurs when communicates with the device. + * @retval RETURN_SECURITY_VIOLATION Any verification fails. + **/ +libspdm_return_t libspdm_responder_handle_response_state(void *spdm_context, + uint8_t request_code, + size_t *response_size, + void *response); + +/** + * Process the SPDM RESPONSE_IF_READY request and return the response. + * + * @param spdm_context A pointer to the SPDM context. + * @param request_size size in bytes of the request data. + * @param request A pointer to the request data. + * @param response_size size in bytes of the response data. + * On input, it means the size in bytes of response data buffer. + * On output, it means the size in bytes of copied response data buffer if RETURN_SUCCESS is returned, + * and means the size in bytes of desired response data buffer if RETURN_BUFFER_TOO_SMALL is returned. + * @param response A pointer to the response data. + * + * @retval RETURN_SUCCESS The request is processed and the response is returned. + * @retval RETURN_BUFFER_TOO_SMALL The buffer is too small to hold the data. + * @retval RETURN_DEVICE_ERROR A device error occurs when communicates with the device. + * @retval RETURN_SECURITY_VIOLATION Any verification fails. + **/ +libspdm_return_t libspdm_get_response_respond_if_ready(void *spdm_context, + size_t request_size, + const void *request, + size_t *response_size, + void *response); + +/** + * Process the SPDM GET_VERSION request and return the response. + * + * @param spdm_context A pointer to the SPDM context. + * @param request_size size in bytes of the request data. + * @param request A pointer to the request data. + * @param response_size size in bytes of the response data. + * On input, it means the size in bytes of response data buffer. + * On output, it means the size in bytes of copied response data buffer if RETURN_SUCCESS is returned, + * and means the size in bytes of desired response data buffer if RETURN_BUFFER_TOO_SMALL is returned. + * @param response A pointer to the response data. + * + * @retval RETURN_SUCCESS The request is processed and the response is returned. + * @retval RETURN_BUFFER_TOO_SMALL The buffer is too small to hold the data. + * @retval RETURN_DEVICE_ERROR A device error occurs when communicates with the device. + * @retval RETURN_SECURITY_VIOLATION Any verification fails. + **/ +libspdm_return_t libspdm_get_response_version(void *spdm_context, + size_t request_size, const void *request, + size_t *response_size, + void *response); + +/** + * Process the SPDM GET_CAPABILITIES request and return the response. + * + * @param spdm_context A pointer to the SPDM context. + * @param request_size size in bytes of the request data. + * @param request A pointer to the request data. + * @param response_size size in bytes of the response data. + * On input, it means the size in bytes of response data buffer. + * On output, it means the size in bytes of copied response data buffer if RETURN_SUCCESS is returned, + * and means the size in bytes of desired response data buffer if RETURN_BUFFER_TOO_SMALL is returned. + * @param response A pointer to the response data. + * + * @retval RETURN_SUCCESS The request is processed and the response is returned. + * @retval RETURN_BUFFER_TOO_SMALL The buffer is too small to hold the data. + * @retval RETURN_DEVICE_ERROR A device error occurs when communicates with the device. + * @retval RETURN_SECURITY_VIOLATION Any verification fails. + **/ +libspdm_return_t libspdm_get_response_capabilities(void *spdm_context, + size_t request_size, + const void *request, + size_t *response_size, + void *response); + +/** + * Process the SPDM NEGOTIATE_ALGORITHMS request and return the response. + * + * @param spdm_context A pointer to the SPDM context. + * @param request_size size in bytes of the request data. + * @param request A pointer to the request data. + * @param response_size size in bytes of the response data. + * On input, it means the size in bytes of response data buffer. + * On output, it means the size in bytes of copied response data buffer if RETURN_SUCCESS is returned, + * and means the size in bytes of desired response data buffer if RETURN_BUFFER_TOO_SMALL is returned. + * @param response A pointer to the response data. + * + * @retval RETURN_SUCCESS The request is processed and the response is returned. + * @retval RETURN_BUFFER_TOO_SMALL The buffer is too small to hold the data. + * @retval RETURN_DEVICE_ERROR A device error occurs when communicates with the device. + * @retval RETURN_SECURITY_VIOLATION Any verification fails. + **/ +libspdm_return_t libspdm_get_response_algorithms(void *spdm_context, + size_t request_size, + const void *request, + size_t *response_size, + void *response); + +#if LIBSPDM_ENABLE_CAPABILITY_CERT_CAP +/** + * Process the SPDM GET_DIGESTS request and return the response. + * + * @param spdm_context A pointer to the SPDM context. + * @param request_size size in bytes of the request data. + * @param request A pointer to the request data. + * @param response_size size in bytes of the response data. + * On input, it means the size in bytes of response data buffer. + * On output, it means the size in bytes of copied response data buffer if RETURN_SUCCESS is returned, + * and means the size in bytes of desired response data buffer if RETURN_BUFFER_TOO_SMALL is returned. + * @param response A pointer to the response data. + * + * @retval RETURN_SUCCESS The request is processed and the response is returned. + * @retval RETURN_BUFFER_TOO_SMALL The buffer is too small to hold the data. + * @retval RETURN_DEVICE_ERROR A device error occurs when communicates with the device. + * @retval RETURN_SECURITY_VIOLATION Any verification fails. + **/ +libspdm_return_t libspdm_get_response_digests(void *spdm_context, + size_t request_size, const void *request, + size_t *response_size, + void *response); +/** + * Process the SPDM GET_CERTIFICATE request and return the response. + * + * @param spdm_context A pointer to the SPDM context. + * @param request_size size in bytes of the request data. + * @param request A pointer to the request data. + * @param response_size size in bytes of the response data. + * On input, it means the size in bytes of response data buffer. + * On output, it means the size in bytes of copied response data buffer if RETURN_SUCCESS is returned, + * and means the size in bytes of desired response data buffer if RETURN_BUFFER_TOO_SMALL is returned. + * @param response A pointer to the response data. + * + * @retval RETURN_SUCCESS The request is processed and the response is returned. + * @retval RETURN_BUFFER_TOO_SMALL The buffer is too small to hold the data. + * @retval RETURN_DEVICE_ERROR A device error occurs when communicates with the device. + * @retval RETURN_SECURITY_VIOLATION Any verification fails. + **/ + +libspdm_return_t libspdm_get_response_certificate(void *spdm_context, + size_t request_size, + const void *request, + size_t *response_size, + void *response); +#endif /* LIBSPDM_ENABLE_CAPABILITY_CERT_CAP */ + +#if LIBSPDM_ENABLE_CAPABILITY_CHAL_CAP +/** + * Process the SPDM CHALLENGE request and return the response. + * + * @param spdm_context A pointer to the SPDM context. + * @param request_size size in bytes of the request data. + * @param request A pointer to the request data. + * @param response_size size in bytes of the response data. + * On input, it means the size in bytes of response data buffer. + * On output, it means the size in bytes of copied response data buffer if RETURN_SUCCESS is returned, + * and means the size in bytes of desired response data buffer if RETURN_BUFFER_TOO_SMALL is returned. + * @param response A pointer to the response data. + * + * @retval RETURN_SUCCESS The request is processed and the response is returned. + * @retval RETURN_BUFFER_TOO_SMALL The buffer is too small to hold the data. + * @retval RETURN_DEVICE_ERROR A device error occurs when communicates with the device. + * @retval RETURN_SECURITY_VIOLATION Any verification fails. + **/ +libspdm_return_t libspdm_get_response_challenge_auth(void *spdm_context, + size_t request_size, + const void *request, + size_t *response_size, + void *response); +#endif /* LIBSPDM_ENABLE_CAPABILITY_CHAL_CAP */ + +#if LIBSPDM_ENABLE_CAPABILITY_MEAS_CAP +/** + * Process the SPDM GET_MEASUREMENT request and return the response. + * + * @param spdm_context A pointer to the SPDM context. + * @param request_size size in bytes of the request data. + * @param request A pointer to the request data. + * @param response_size size in bytes of the response data. + * On input, it means the size in bytes of response data buffer. + * On output, it means the size in bytes of copied response data buffer if RETURN_SUCCESS is returned, + * and means the size in bytes of desired response data buffer if RETURN_BUFFER_TOO_SMALL is returned. + * @param response A pointer to the response data. + * + * @retval RETURN_SUCCESS The request is processed and the response is returned. + * @retval RETURN_BUFFER_TOO_SMALL The buffer is too small to hold the data. + * @retval RETURN_DEVICE_ERROR A device error occurs when communicates with the device. + * @retval RETURN_SECURITY_VIOLATION Any verification fails. + **/ +libspdm_return_t libspdm_get_response_measurements(void *spdm_context, + size_t request_size, + const void *request, + size_t *response_size, + void *response); +#endif /* LIBSPDM_ENABLE_CAPABILITY_MEAS_CAP */ + +#if LIBSPDM_ENABLE_CAPABILITY_KEY_EX_CAP +/** + * Process the SPDM KEY_EXCHANGE request and return the response. + * + * @param spdm_context A pointer to the SPDM context. + * @param request_size size in bytes of the request data. + * @param request A pointer to the request data. + * @param response_size size in bytes of the response data. + * On input, it means the size in bytes of response data buffer. + * On output, it means the size in bytes of copied response data buffer if RETURN_SUCCESS is returned, + * and means the size in bytes of desired response data buffer if RETURN_BUFFER_TOO_SMALL is returned. + * @param response A pointer to the response data. + * + * @retval RETURN_SUCCESS The request is processed and the response is returned. + * @retval RETURN_BUFFER_TOO_SMALL The buffer is too small to hold the data. + * @retval RETURN_DEVICE_ERROR A device error occurs when communicates with the device. + * @retval RETURN_SECURITY_VIOLATION Any verification fails. + **/ +libspdm_return_t libspdm_get_response_key_exchange(void *spdm_context, + size_t request_size, + const void *request, + size_t *response_size, + void *response); + +/** + * Process the SPDM FINISH request and return the response. + * + * @param spdm_context A pointer to the SPDM context. + * @param request_size size in bytes of the request data. + * @param request A pointer to the request data. + * @param response_size size in bytes of the response data. + * On input, it means the size in bytes of response data buffer. + * On output, it means the size in bytes of copied response data buffer if RETURN_SUCCESS is returned, + * and means the size in bytes of desired response data buffer if RETURN_BUFFER_TOO_SMALL is returned. + * @param response A pointer to the response data. + * + * @retval RETURN_SUCCESS The request is processed and the response is returned. + * @retval RETURN_BUFFER_TOO_SMALL The buffer is too small to hold the data. + * @retval RETURN_DEVICE_ERROR A device error occurs when communicates with the device. + * @retval RETURN_SECURITY_VIOLATION Any verification fails. + **/ +libspdm_return_t libspdm_get_response_finish(void *spdm_context, + size_t request_size, const void *request, + size_t *response_size, + void *response); +#endif /* LIBSPDM_ENABLE_CAPABILITY_KEY_EX_CAP */ + +#if LIBSPDM_ENABLE_CAPABILITY_PSK_EX_CAP +/** + * Process the SPDM PSK_EXCHANGE request and return the response. + * + * @param spdm_context A pointer to the SPDM context. + * @param request_size size in bytes of the request data. + * @param request A pointer to the request data. + * @param response_size size in bytes of the response data. + * On input, it means the size in bytes of response data buffer. + * On output, it means the size in bytes of copied response data buffer if RETURN_SUCCESS is returned, + * and means the size in bytes of desired response data buffer if RETURN_BUFFER_TOO_SMALL is returned. + * @param response A pointer to the response data. + * + * @retval RETURN_SUCCESS The request is processed and the response is returned. + * @retval RETURN_BUFFER_TOO_SMALL The buffer is too small to hold the data. + * @retval RETURN_DEVICE_ERROR A device error occurs when communicates with the device. + * @retval RETURN_SECURITY_VIOLATION Any verification fails. + **/ +libspdm_return_t libspdm_get_response_psk_exchange(void *spdm_context, + size_t request_size, + const void *request, + size_t *response_size, + void *response); + +/** + * Process the SPDM PSK_FINISH request and return the response. + * + * @param spdm_context A pointer to the SPDM context. + * @param request_size size in bytes of the request data. + * @param request A pointer to the request data. + * @param response_size size in bytes of the response data. + * On input, it means the size in bytes of response data buffer. + * On output, it means the size in bytes of copied response data buffer if RETURN_SUCCESS is returned, + * and means the size in bytes of desired response data buffer if RETURN_BUFFER_TOO_SMALL is returned. + * @param response A pointer to the response data. + * + * @retval RETURN_SUCCESS The request is processed and the response is returned. + * @retval RETURN_BUFFER_TOO_SMALL The buffer is too small to hold the data. + * @retval RETURN_DEVICE_ERROR A device error occurs when communicates with the device. + * @retval RETURN_SECURITY_VIOLATION Any verification fails. + **/ +libspdm_return_t libspdm_get_response_psk_finish(void *spdm_context, + size_t request_size, + const void *request, + size_t *response_size, + void *response); +#endif /* LIBSPDM_ENABLE_CAPABILITY_PSK_EX_CAP */ + +#if (LIBSPDM_ENABLE_CAPABILITY_KEY_EX_CAP) || (LIBSPDM_ENABLE_CAPABILITY_PSK_EX_CAP) +/** + * Process the SPDM END_SESSION request and return the response. + * + * @param spdm_context A pointer to the SPDM context. + * @param request_size size in bytes of the request data. + * @param request A pointer to the request data. + * @param response_size size in bytes of the response data. + * On input, it means the size in bytes of response data buffer. + * On output, it means the size in bytes of copied response data buffer if RETURN_SUCCESS is returned, + * and means the size in bytes of desired response data buffer if RETURN_BUFFER_TOO_SMALL is returned. + * @param response A pointer to the response data. + * + * @retval RETURN_SUCCESS The request is processed and the response is returned. + * @retval RETURN_BUFFER_TOO_SMALL The buffer is too small to hold the data. + * @retval RETURN_DEVICE_ERROR A device error occurs when communicates with the device. + * @retval RETURN_SECURITY_VIOLATION Any verification fails. + **/ +libspdm_return_t libspdm_get_response_end_session(void *spdm_context, + size_t request_size, + const void *request, + size_t *response_size, + void *response); + +/** + * Process the SPDM KEY_UPDATE request and return the response. + * + * @param spdm_context A pointer to the SPDM context. + * @param request_size size in bytes of the request data. + * @param request A pointer to the request data. + * @param response_size size in bytes of the response data. + * On input, it means the size in bytes of response data buffer. + * On output, it means the size in bytes of copied response data buffer if RETURN_SUCCESS is returned, + * and means the size in bytes of desired response data buffer if RETURN_BUFFER_TOO_SMALL is returned. + * @param response A pointer to the response data. + * + * @retval RETURN_SUCCESS The request is processed and the response is returned. + * @retval RETURN_BUFFER_TOO_SMALL The buffer is too small to hold the data. + * @retval RETURN_DEVICE_ERROR A device error occurs when communicates with the device. + * @retval RETURN_SECURITY_VIOLATION Any verification fails. + **/ +libspdm_return_t libspdm_get_response_key_update(void *spdm_context, + size_t request_size, + const void *request, + size_t *response_size, + void *response); + +/** + * Process the SPDM HEARTBEAT request and return the response. + * + * @param spdm_context A pointer to the SPDM context. + * @param request_size size in bytes of the request data. + * @param request A pointer to the request data. + * @param response_size size in bytes of the response data. + * On input, it means the size in bytes of response data buffer. + * On output, it means the size in bytes of copied response data buffer if RETURN_SUCCESS is returned, + * and means the size in bytes of desired response data buffer if RETURN_BUFFER_TOO_SMALL is returned. + * @param response A pointer to the response data. + * + * @retval RETURN_SUCCESS The request is processed and the response is returned. + * @retval RETURN_BUFFER_TOO_SMALL The buffer is too small to hold the data. + * @retval RETURN_DEVICE_ERROR A device error occurs when communicates with the device. + * @retval RETURN_SECURITY_VIOLATION Any verification fails. + **/ +libspdm_return_t libspdm_get_response_heartbeat(void *spdm_context, + size_t request_size, + const void *request, + size_t *response_size, + void *response); +#endif /* (LIBSPDM_ENABLE_CAPABILITY_KEY_EX_CAP) || (LIBSPDM_ENABLE_CAPABILITY_PSK_EX_CAP) */ + +#if (LIBSPDM_ENABLE_CAPABILITY_MUT_AUTH_CAP) || (LIBSPDM_ENABLE_CAPABILITY_ENCAP_CAP) +/** + * Process the SPDM ENCAPSULATED_REQUEST request and return the response. + * + * @param spdm_context A pointer to the SPDM context. + * @param request_size size in bytes of the request data. + * @param request A pointer to the request data. + * @param response_size size in bytes of the response data. + * On input, it means the size in bytes of response data buffer. + * On output, it means the size in bytes of copied response data buffer if RETURN_SUCCESS is returned, + * and means the size in bytes of desired response data buffer if RETURN_BUFFER_TOO_SMALL is returned. + * @param response A pointer to the response data. + * + * @retval RETURN_SUCCESS The request is processed and the response is returned. + * @retval RETURN_BUFFER_TOO_SMALL The buffer is too small to hold the data. + * @retval RETURN_DEVICE_ERROR A device error occurs when communicates with the device. + * @retval RETURN_SECURITY_VIOLATION Any verification fails. + **/ +libspdm_return_t libspdm_get_response_encapsulated_request( + void *spdm_context, size_t request_size, const void *request, + size_t *response_size, void *response); + +/** + * Process the SPDM ENCAPSULATED_RESPONSE_ACK request and return the response. + * + * @param spdm_context A pointer to the SPDM context. + * @param request_size size in bytes of the request data. + * @param request A pointer to the request data. + * @param response_size size in bytes of the response data. + * On input, it means the size in bytes of response data buffer. + * On output, it means the size in bytes of copied response data buffer if RETURN_SUCCESS is returned, + * and means the size in bytes of desired response data buffer if RETURN_BUFFER_TOO_SMALL is returned. + * @param response A pointer to the response data. + * + * @retval RETURN_SUCCESS The request is processed and the response is returned. + * @retval RETURN_BUFFER_TOO_SMALL The buffer is too small to hold the data. + * @retval RETURN_DEVICE_ERROR A device error occurs when communicates with the device. + * @retval RETURN_SECURITY_VIOLATION Any verification fails. + **/ +libspdm_return_t libspdm_get_response_encapsulated_response_ack( + void *spdm_context, size_t request_size, const void *request, + size_t *response_size, void *response); + +/** + * Get the SPDM encapsulated GET_DIGESTS request. + * + * @param spdm_context A pointer to the SPDM context. + * @param encap_request_size size in bytes of the encapsulated request data. + * On input, it means the size in bytes of encapsulated request data buffer. + * On output, it means the size in bytes of copied encapsulated request data buffer if RETURN_SUCCESS is returned, + * and means the size in bytes of desired encapsulated request data buffer if RETURN_BUFFER_TOO_SMALL is returned. + * @param encap_request A pointer to the encapsulated request data. + * + * @retval RETURN_SUCCESS The encapsulated request is returned. + * @retval RETURN_BUFFER_TOO_SMALL The buffer is too small to hold the data. + **/ +libspdm_return_t libspdm_get_encap_request_get_digest(libspdm_context_t *spdm_context, + size_t *encap_request_size, + void *encap_request); + +/** + * Process the SPDM encapsulated DIGESTS response. + * + * @param spdm_context A pointer to the SPDM context. + * @param encap_response_size size in bytes of the encapsulated response data. + * @param encap_response A pointer to the encapsulated response data. + * @param need_continue Indicate if encapsulated communication need continue. + * + * @retval RETURN_SUCCESS The encapsulated response is processed. + * @retval RETURN_BUFFER_TOO_SMALL The buffer is too small to hold the data. + * @retval RETURN_SECURITY_VIOLATION Any verification fails. + **/ +libspdm_return_t libspdm_process_encap_response_digest( + libspdm_context_t *spdm_context, size_t encap_response_size, + const void *encap_response, bool *need_continue); + + +/** + * Get the SPDM encapsulated GET_CERTIFICATE request. + * + * @param spdm_context A pointer to the SPDM context. + * @param encap_request_size size in bytes of the encapsulated request data. + * On input, it means the size in bytes of encapsulated request data buffer. + * On output, it means the size in bytes of copied encapsulated request data buffer if RETURN_SUCCESS is returned, + * and means the size in bytes of desired encapsulated request data buffer if RETURN_BUFFER_TOO_SMALL is returned. + * @param encap_request A pointer to the encapsulated request data. + * + * @retval RETURN_SUCCESS The encapsulated request is returned. + * @retval RETURN_BUFFER_TOO_SMALL The buffer is too small to hold the data. + **/ +libspdm_return_t libspdm_get_encap_request_get_certificate(libspdm_context_t *spdm_context, + size_t *encap_request_size, + void *encap_request); + +/** + * Process the SPDM encapsulated CERTIFICATE response. + * + * @param spdm_context A pointer to the SPDM context. + * @param encap_response_size size in bytes of the encapsulated response data. + * @param encap_response A pointer to the encapsulated response data. + * @param need_continue Indicate if encapsulated communication need continue. + * + * @retval RETURN_SUCCESS The encapsulated response is processed. + * @retval RETURN_BUFFER_TOO_SMALL The buffer is too small to hold the data. + * @retval RETURN_SECURITY_VIOLATION Any verification fails. + **/ +libspdm_return_t libspdm_process_encap_response_certificate( + libspdm_context_t *spdm_context, size_t encap_response_size, + const void *encap_response, bool *need_continue); + +/** + * Get the SPDM encapsulated CHALLENGE request. + * + * @param spdm_context A pointer to the SPDM context. + * @param encap_request_size size in bytes of the encapsulated request data. + * On input, it means the size in bytes of encapsulated request data buffer. + * On output, it means the size in bytes of copied encapsulated request data buffer if RETURN_SUCCESS is returned, + * and means the size in bytes of desired encapsulated request data buffer if RETURN_BUFFER_TOO_SMALL is returned. + * @param encap_request A pointer to the encapsulated request data. + * + * @retval RETURN_SUCCESS The encapsulated request is returned. + * @retval RETURN_BUFFER_TOO_SMALL The buffer is too small to hold the data. + **/ +libspdm_return_t libspdm_get_encap_request_challenge(libspdm_context_t *spdm_context, + size_t *encap_request_size, + void *encap_request); + +/** + * Process the SPDM encapsulated CHALLENGE_AUTH response. + * + * @param spdm_context A pointer to the SPDM context. + * @param encap_response_size size in bytes of the encapsulated response data. + * @param encap_response A pointer to the encapsulated response data. + * @param need_continue Indicate if encapsulated communication need continue. + * + * @retval RETURN_SUCCESS The encapsulated response is processed. + * @retval RETURN_BUFFER_TOO_SMALL The buffer is too small to hold the data. + * @retval RETURN_SECURITY_VIOLATION Any verification fails. + **/ +libspdm_return_t libspdm_process_encap_response_challenge_auth( + libspdm_context_t *spdm_context, size_t encap_response_size, + const void *encap_response, bool *need_continue); + +/** + * Get the SPDM encapsulated KEY_UPDATE request. + * + * @param spdm_context A pointer to the SPDM context. + * @param encap_request_size size in bytes of the encapsulated request data. + * On input, it means the size in bytes of encapsulated request data buffer. + * On output, it means the size in bytes of copied encapsulated request data buffer if RETURN_SUCCESS is returned, + * and means the size in bytes of desired encapsulated request data buffer if RETURN_BUFFER_TOO_SMALL is returned. + * @param encap_request A pointer to the encapsulated request data. + * + * @retval RETURN_SUCCESS The encapsulated request is returned. + * @retval RETURN_BUFFER_TOO_SMALL The buffer is too small to hold the data. + **/ +libspdm_return_t +libspdm_get_encap_request_key_update(libspdm_context_t *spdm_context, + size_t *encap_request_size, + void *encap_request); + +/** + * Process the SPDM encapsulated KEY_UPDATE response. + * + * @param spdm_context A pointer to the SPDM context. + * @param encap_response_size size in bytes of the encapsulated response data. + * @param encap_response A pointer to the encapsulated response data. + * @param need_continue Indicate if encapsulated communication need continue. + * + * @retval RETURN_SUCCESS The encapsulated response is processed. + * @retval RETURN_BUFFER_TOO_SMALL The buffer is too small to hold the data. + * @retval RETURN_SECURITY_VIOLATION Any verification fails. + **/ +libspdm_return_t libspdm_process_encap_response_key_update( + libspdm_context_t *spdm_context, size_t encap_response_size, + const void *encap_response, bool *need_continue); +#endif /* (LIBSPDM_ENABLE_CAPABILITY_MUT_AUTH_CAP) || (LIBSPDM_ENABLE_CAPABILITY_ENCAP_CAP)*/ + +/** + * Return the GET_SPDM_RESPONSE function via request code. + * + * @param request_code The SPDM request code. + * + * @return GET_SPDM_RESPONSE function according to the request code. + **/ +libspdm_get_spdm_response_func libspdm_get_response_func_via_request_code(uint8_t request_code); + +#if (LIBSPDM_ENABLE_CAPABILITY_MUT_AUTH_CAP) || (LIBSPDM_ENABLE_CAPABILITY_ENCAP_CAP) +/** + * This function initializes the mut_auth encapsulated state. + * + * @param spdm_context A pointer to the SPDM context. + * @param mut_auth_requested Indicate of the mut_auth_requested through KEY_EXCHANGE response. + **/ +void libspdm_init_mut_auth_encap_state(libspdm_context_t *spdm_context, uint8_t mut_auth_requested); + +/** + * This function initializes the basic_mut_auth encapsulated state. + * + * @param spdm_context A pointer to the SPDM context. + **/ +void libspdm_init_basic_mut_auth_encap_state(libspdm_context_t *spdm_context); +#endif /* (LIBSPDM_ENABLE_CAPABILITY_MUT_AUTH_CAP) || (LIBSPDM_ENABLE_CAPABILITY_ENCAP_CAP)*/ + +/** + * This function handles the encap error response. + * + * @param spdm_context A pointer to the SPDM context. + * @param error_code Indicate the error code. + * + * @retval RETURN_DEVICE_ERROR A device error occurs when communicates with the device. + **/ +libspdm_return_t libspdm_handle_encap_error_response_main( + libspdm_context_t *spdm_context, uint8_t error_code); + +/** + * Set session_state to an SPDM secured message context and trigger callback. + * + * @param spdm_context A pointer to the SPDM context. + * @param session_id Indicate the SPDM session ID. + * @param session_state Indicate the SPDM session state. + */ +void libspdm_set_session_state(libspdm_context_t *spdm_context, + uint32_t session_id, + libspdm_session_state_t session_state); + +/** + * Set connection_state to an SPDM context and trigger callback. + * + * @param spdm_context A pointer to the SPDM context. + * @param connection_state Indicate the SPDM connection state. + */ +void libspdm_set_connection_state(libspdm_context_t *spdm_context, + libspdm_connection_state_t connection_state); + +#if LIBSPDM_ENABLE_CAPABILITY_GET_CSR_CAP +/** + * Process the SPDM GET_CSR request and return the response. + * + * @param spdm_context A pointer to the SPDM context. + * @param request_size size in bytes of the request data. + * @param request A pointer to the request data. + * @param response_size size in bytes of the response data. + * On input, it means the size in bytes of response data buffer. + * On output, it means the size in bytes of copied response data buffer if RETURN_SUCCESS is returned, + * and means the size in bytes of desired response data buffer if RETURN_BUFFER_TOO_SMALL is returned. + * @param response A pointer to the response data. + * + * @retval RETURN_SUCCESS The request is processed and the response is returned. + * @retval RETURN_BUFFER_TOO_SMALL The buffer is too small to hold the data. + * @retval RETURN_DEVICE_ERROR A device error occurs when communicates with the device. + * @retval RETURN_SECURITY_VIOLATION Any verification fails. + **/ +libspdm_return_t libspdm_get_response_csr(void *context, size_t request_size, + const void *request, size_t *response_size, + void *response); +#endif /* LIBSPDM_ENABLE_CAPABILITY_GET_CSR_CAP */ + +#if LIBSPDM_ENABLE_CAPABILITY_SET_CERTIFICATE_CAP || LIBSPDM_ENABLE_SET_CERTIFICATE_CAP +/** + * Process the SPDM SET_CERTIFICATE request and return the response. + * + * @param spdm_context A pointer to the SPDM context. + * @param request_size size in bytes of the request data. + * @param request A pointer to the request data. + * @param response_size size in bytes of the response data. + * On input, it means the size in bytes of response data buffer. + * On output, it means the size in bytes of copied response data buffer if RETURN_SUCCESS is returned, + * and means the size in bytes of desired response data buffer if RETURN_BUFFER_TOO_SMALL is returned. + * @param response A pointer to the response data. + * + * @retval RETURN_SUCCESS The request is processed and the response is returned. + * @retval RETURN_BUFFER_TOO_SMALL The buffer is too small to hold the data. + * @retval RETURN_DEVICE_ERROR A device error occurs when communicates with the device. + * @retval RETURN_SECURITY_VIOLATION Any verification fails. + **/ +libspdm_return_t libspdm_get_response_set_certificate(void *context, size_t request_size, + const void *request, + size_t *response_size, + void *response); +#endif /* LIBSPDM_ENABLE_CAPABILITY_SET_CERTIFICATE_CAP */ + +#if LIBSPDM_ENABLE_CAPABILITY_CHUNK_CAP || LIBSPDM_ENABLE_CHUNK_CAP +/** + * Process the SPDM CHUNK_GET request and return the response. + * + * @param spdm_context A pointer to the SPDM context. + * @param request_size size in bytes of the request data. + * @param request A pointer to the request data. + * @param response_size size in bytes of the response data. + * On input, it means the size in bytes of response data buffer. + * On output, it means the size in bytes of copied response data buffer if RETURN_SUCCESS is returned, + * and means the size in bytes of desired response data buffer if RETURN_BUFFER_TOO_SMALL is returned. + * @param response A pointer to the response data. + * + * @retval RETURN_SUCCESS The request is processed and the response is returned. + * @retval RETURN_BUFFER_TOO_SMALL The buffer is too small to hold the data. + * @retval RETURN_DEVICE_ERROR A device error occurs when communicates with the device. + * @retval RETURN_SECURITY_VIOLATION Any verification fails. + **/ +libspdm_return_t libspdm_get_response_chunk_get(void* context, + size_t request_size, + const void* request, + size_t* response_size, + void* response); + +/** + * Process the SPDM CHUNK_SEND request and return the response. + * + * @param spdm_context A pointer to the SPDM context. + * @param request_size size in bytes of the request data. + * @param request A pointer to the request data. + * @param response_size size in bytes of the response data. + * On input, it means the size in bytes of response data buffer. + * On output, it means the size in bytes of copied response data buffer if RETURN_SUCCESS is returned, + * and means the size in bytes of desired response data buffer if RETURN_BUFFER_TOO_SMALL is returned. + * @param response A pointer to the response data. + * + * @retval RETURN_SUCCESS The request is processed and the response is returned. + * @retval RETURN_BUFFER_TOO_SMALL The buffer is too small to hold the data. + * @retval RETURN_DEVICE_ERROR A device error occurs when communicates with the device. + * @retval RETURN_SECURITY_VIOLATION Any verification fails. + **/ +libspdm_return_t libspdm_get_response_chunk_send(void* context, + size_t request_size, + const void* request, + size_t* response_size, + void* response); + +#endif /* LIBSPDM_ENABLE_CAPABILITY_CHUNK_CAP */ + +/** + * This function allocates half of session ID for a responder. + * + * @param spdm_context A pointer to the SPDM context. + * + * @return half of session ID for a responder. + **/ +uint16_t libspdm_allocate_rsp_session_id(const libspdm_context_t *spdm_context); + +/** + * Build opaque data version selection. + * + * This function should be called in KEY_EXCHANGE/PSK_EXCHANGE response generation. + * + * @param data_out_size Size in bytes of the data_out. + * On input, it means the size in bytes of data_out buffer. + * On output, it means the size in bytes of copied data_out buffer if RETURN_SUCCESS is returned, + * and means the size in bytes of desired data_out buffer if RETURN_BUFFER_TOO_SMALL is returned. + * @param data_out A pointer to the desination buffer to store the opaque data version selection. + **/ +libspdm_return_t +libspdm_build_opaque_data_version_selection_data(const libspdm_context_t *spdm_context, + size_t *data_out_size, + void *data_out); + +/** + * Process opaque data supported version. + * + * This function should be called in KEY_EXCHANGE/PSK_EXCHANGE request parsing in responder. + * + * @param data_in_size Size in bytes of the data_in. + * @param data_in A pointer to the buffer to store the opaque data supported version. + **/ +libspdm_return_t +libspdm_process_opaque_data_supported_version_data(libspdm_context_t *spdm_context, + size_t data_in_size, + const void *data_in); + +/** + * This function verifies the finish HMAC based upon TH. + * + * @param spdm_context A pointer to the SPDM context. + * @param session_info The session info of an SPDM session. + * @param hmac_data The HMAC data buffer. + * @param hmac_data_size Size in bytes of the HMAC data buffer. + * + * @retval true HMAC verification pass. + * @retval false HMAC verification fail. + **/ +bool libspdm_verify_finish_req_hmac(libspdm_context_t *spdm_context, + libspdm_session_info_t *session_info, + const uint8_t *hmac, size_t hmac_size); + +#if LIBSPDM_ENABLE_CAPABILITY_MUT_AUTH_CAP +/** + * This function verifies the finish signature based upon TH. + * + * @param spdm_context A pointer to the SPDM context. + * @param session_info The session info of an SPDM session. + * @param sign_data The signature data buffer. + * @param sign_data_size size in bytes of the signature data buffer. + * + * @retval true signature verification pass. + * @retval false signature verification fail. + **/ +bool libspdm_verify_finish_req_signature(libspdm_context_t *spdm_context, + libspdm_session_info_t *session_info, + const void *sign_data, + const size_t sign_data_size); +#endif + +/** + * This function generates the finish HMAC based upon TH. + * + * @param spdm_context A pointer to the SPDM context. + * @param session_info The session info of an SPDM session. + * @param hmac The buffer to store the finish HMAC. + * + * @retval true finish HMAC is generated. + * @retval false finish HMAC is not generated. + **/ +bool libspdm_generate_finish_rsp_hmac(libspdm_context_t *spdm_context, + libspdm_session_info_t *session_info, + uint8_t *hmac); + +/** + * This function generates the key exchange HMAC based upon TH. + * + * @param spdm_context A pointer to the SPDM context. + * @param session_info The session info of an SPDM session. + * @param hmac The buffer to store the key exchange HMAC. + * + * @retval true key exchange HMAC is generated. + * @retval false key exchange HMAC is not generated. + **/ +bool libspdm_generate_key_exchange_rsp_hmac(libspdm_context_t *spdm_context, + libspdm_session_info_t *session_info, + uint8_t *hmac); + +/** + * This function generates the key exchange signature based upon TH. + * + * @param spdm_context A pointer to the SPDM context. + * @param session_info The session info of an SPDM session. + * @param signature The buffer to store the key exchange signature. + * + * @retval true key exchange signature is generated. + * @retval false key exchange signature is not generated. + **/ +bool libspdm_generate_key_exchange_rsp_signature(libspdm_context_t *spdm_context, + libspdm_session_info_t *session_info, + uint8_t *signature); + +/** + * This function generates the measurement signature to response message based upon l1l2. + * If session_info is NULL, this function will use M cache of SPDM context, + * else will use M cache of SPDM session context. + * + * @param spdm_context A pointer to the SPDM context. + * @param session_info A pointer to the SPDM session context. + * @param signature The buffer to store the signature. + * + * @retval true measurement signature is generated. + * @retval false measurement signature is not generated. + **/ +bool libspdm_generate_measurement_signature(libspdm_context_t *spdm_context, + libspdm_session_info_t *session_info, + uint8_t *signature); + +#endif /* SPDM_RESPONDER_LIB_INTERNAL_H */ diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/libraries/libspdm/2.3.1/include/internal/libspdm_secured_message_lib.h nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/libraries/libspdm/2.3.1/include/internal/libspdm_secured_message_lib.h --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/libraries/libspdm/2.3.1/include/internal/libspdm_secured_message_lib.h 1970-01-01 00:00:00.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/libraries/libspdm/2.3.1/include/internal/libspdm_secured_message_lib.h 2024-03-05 22:14:13.000000000 +0000 @@ -0,0 +1,79 @@ +/** + * Copyright Notice: + * Copyright 2021-2022 DMTF. All rights reserved. + * License: BSD 3-Clause License. For full text see link: https://github.com/DMTF/libspdm/blob/main/LICENSE.md + **/ + +#ifndef SPDM_SECURED_MESSAGE_LIB_INTERNAL_H +#define SPDM_SECURED_MESSAGE_LIB_INTERNAL_H + +#include "library/spdm_secured_message_lib.h" +#include "library/spdm_crypt_lib.h" +#include "library/spdm_device_secret_lib.h" +#include "internal/libspdm_common_lib.h" +#include "hal/library/memlib.h" +#include "hal/library/cryptlib.h" + +typedef struct { + uint8_t dhe_secret[LIBSPDM_MAX_DHE_KEY_SIZE]; + uint8_t handshake_secret[LIBSPDM_MAX_HASH_SIZE]; + uint8_t master_secret[LIBSPDM_MAX_HASH_SIZE]; +} libspdm_session_info_struct_master_secret_t; + +typedef struct { + uint8_t request_handshake_secret[LIBSPDM_MAX_HASH_SIZE]; + uint8_t response_handshake_secret[LIBSPDM_MAX_HASH_SIZE]; + uint8_t request_finished_key[LIBSPDM_MAX_HASH_SIZE]; + uint8_t response_finished_key[LIBSPDM_MAX_HASH_SIZE]; + uint8_t request_handshake_encryption_key[LIBSPDM_MAX_AEAD_KEY_SIZE]; + uint8_t request_handshake_salt[LIBSPDM_MAX_AEAD_IV_SIZE]; + uint64_t request_handshake_sequence_number; + uint8_t response_handshake_encryption_key[LIBSPDM_MAX_AEAD_KEY_SIZE]; + uint8_t response_handshake_salt[LIBSPDM_MAX_AEAD_IV_SIZE]; + uint64_t response_handshake_sequence_number; +} libspdm_session_info_struct_handshake_secret_t; + +typedef struct { + uint8_t request_data_secret[LIBSPDM_MAX_HASH_SIZE]; + uint8_t response_data_secret[LIBSPDM_MAX_HASH_SIZE]; + uint8_t request_data_encryption_key[LIBSPDM_MAX_AEAD_KEY_SIZE]; + uint8_t request_data_salt[LIBSPDM_MAX_AEAD_IV_SIZE]; + uint64_t request_data_sequence_number; + uint8_t response_data_encryption_key[LIBSPDM_MAX_AEAD_KEY_SIZE]; + uint8_t response_data_salt[LIBSPDM_MAX_AEAD_IV_SIZE]; + uint64_t response_data_sequence_number; +} libspdm_session_info_struct_application_secret_t; + +typedef struct { + libspdm_session_type_t session_type; + spdm_version_number_t version; + spdm_version_number_t secured_message_version; + uint32_t base_hash_algo; + uint16_t dhe_named_group; + uint16_t aead_cipher_suite; + uint16_t key_schedule; + size_t hash_size; + size_t dhe_key_size; + size_t aead_key_size; + size_t aead_iv_size; + size_t aead_tag_size; + bool use_psk; + libspdm_session_state_t session_state; + libspdm_session_info_struct_master_secret_t master_secret; + libspdm_session_info_struct_handshake_secret_t handshake_secret; + libspdm_session_info_struct_application_secret_t application_secret; + libspdm_session_info_struct_application_secret_t application_secret_backup; + bool requester_backup_valid; + bool responder_backup_valid; + size_t psk_hint_size; + uint8_t psk_hint[LIBSPDM_PSK_MAX_HINT_LENGTH]; + uint8_t export_master_secret[LIBSPDM_MAX_HASH_SIZE]; + + /* Cache the error in libspdm_decode_secured_message. + * It is handled in libspdm_build_response. */ + libspdm_error_struct_t last_spdm_error; +} libspdm_secured_message_context_t; + +#define LIBSPDM_SECURED_MESSAGE_CONTEXT_SIZE (sizeof(libspdm_secured_message_context_t)) + +#endif /* SPDM_SECURED_MESSAGE_LIB_INTERNAL_H */ diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/libraries/libspdm/2.3.1/include/library/spdm_common_lib.h nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/libraries/libspdm/2.3.1/include/library/spdm_common_lib.h --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/libraries/libspdm/2.3.1/include/library/spdm_common_lib.h 1970-01-01 00:00:00.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/libraries/libspdm/2.3.1/include/library/spdm_common_lib.h 2024-03-05 22:14:13.000000000 +0000 @@ -0,0 +1,795 @@ +/** + * Copyright Notice: + * Copyright 2021-2022 DMTF. All rights reserved. + * License: BSD 3-Clause License. For full text see link: https://github.com/DMTF/libspdm/blob/main/LICENSE.md + **/ + +#ifndef SPDM_COMMON_LIB_H +#define SPDM_COMMON_LIB_H + +#include "internal/libspdm_lib_config.h" +#include "hal/base.h" +#include "library/spdm_secured_message_lib.h" +#include "library/spdm_return_status.h" + +/* Connection: When a host sends messgages to a device, they create a connection. + * The host can and only can create one connection with one device. + * The host may create multiple connections with multiple devices at same time. + * A connection can be unique identified by the connected device. + * The message exchange in a connection is plain text.*/ + +/* Session: In one connection with one device, a host may create multiple sessions. + * The session starts with via KEY_EXCHANGE or PSK_EXCHANGE, and step with END_SESSION. + * A session can be unique identified by a session ID, returned from the device. + * The message exchange in a session is cipher text.*/ + +typedef enum { + /* SPDM parameter */ + LIBSPDM_DATA_SPDM_VERSION, + LIBSPDM_DATA_SECURED_MESSAGE_VERSION, + + /* SPDM capability */ + LIBSPDM_DATA_CAPABILITY_FLAGS, + LIBSPDM_DATA_CAPABILITY_CT_EXPONENT, + LIBSPDM_DATA_CAPABILITY_RTT_US, + LIBSPDM_DATA_CAPABILITY_DATA_TRANSFER_SIZE, + LIBSPDM_DATA_CAPABILITY_MAX_SPDM_MSG_SIZE, + + /* SPDM algorithm setting */ + LIBSPDM_DATA_MEASUREMENT_SPEC, + LIBSPDM_DATA_MEASUREMENT_HASH_ALGO, + LIBSPDM_DATA_BASE_ASYM_ALGO, + LIBSPDM_DATA_BASE_HASH_ALGO, + LIBSPDM_DATA_DHE_NAME_GROUP, + LIBSPDM_DATA_AEAD_CIPHER_SUITE, + LIBSPDM_DATA_REQ_BASE_ASYM_ALG, + LIBSPDM_DATA_KEY_SCHEDULE, + LIBSPDM_DATA_OTHER_PARAMS_SUPPORT, + + /* Connection State */ + LIBSPDM_DATA_CONNECTION_STATE, + + /* response_state */ + LIBSPDM_DATA_RESPONSE_STATE, + + /* Certificate info */ + LIBSPDM_DATA_LOCAL_PUBLIC_CERT_CHAIN, + /* LIBSPDM_DATA_LOCAL_SLOT_COUNT is deprecated. Do not use it. Reserved only. */ + LIBSPDM_DATA_LOCAL_SLOT_COUNT, + LIBSPDM_DATA_PEER_PUBLIC_ROOT_CERT, + LIBSPDM_DATA_PEER_PUBLIC_CERT_CHAIN, + LIBSPDM_DATA_BASIC_MUT_AUTH_REQUESTED, + LIBSPDM_DATA_MUT_AUTH_REQUESTED, + LIBSPDM_DATA_HEARTBEAT_PERIOD, + + /* Negotiated result */ + LIBSPDM_DATA_LOCAL_USED_CERT_CHAIN_BUFFER, + LIBSPDM_DATA_PEER_USED_CERT_CHAIN_BUFFER, + LIBSPDM_DATA_PEER_SLOT_MASK, + LIBSPDM_DATA_PEER_TOTAL_DIGEST_BUFFER, + + /* Pre-shared key Hint + * If PSK is present, then PSK_EXCHANGE is used. + * Otherwise, the KEY_EXCHANGE is used. */ + LIBSPDM_DATA_PSK_HINT, + + /* SessionData */ + LIBSPDM_DATA_SESSION_USE_PSK, + LIBSPDM_DATA_SESSION_MUT_AUTH_REQUESTED, + LIBSPDM_DATA_SESSION_END_SESSION_ATTRIBUTES, + LIBSPDM_DATA_SESSION_POLICY, + + /* App context data that can be used by the application + * during callback functions such libspdm_device_send_message_func. */ + LIBSPDM_DATA_APP_CONTEXT_DATA, + + /** + * The LIBSPDM_DATA_HANDLE_ERROR_RETURN_POLICY 0x00000001 control to generate SPDM_ERROR_CODE_DECRYPT_ERROR response or drop the request silently. + * If the 0x00000001 is not set, generate SPDM_ERROR_CODE_DECRYPT_ERROR response. + * If the 0x00000001 set, drop the request silently. + **/ + LIBSPDM_DATA_HANDLE_ERROR_RETURN_POLICY, + + /* VCA cached for CACHE_CAP in 1.2 for transcript. */ + LIBSPDM_DATA_VCA_CACHE, + + /* My provisioned certificate slot_id (for slot_id - 0xFF, default 0)*/ + LIBSPDM_DATA_LOCAL_PUBLIC_CERT_CHAIN_DEFAULT_SLOT_ID, + + /* if the context is for a requester. It only needs to be set in VCA cache. + * In normal flow, the value is set in GET_VERSION or VERSION automatically. + * false means responder + * true means requester + **/ + LIBSPDM_DATA_IS_REQUESTER, + + /* MAX */ + LIBSPDM_DATA_MAX +} libspdm_data_type_t; + +/** + * It controls to generate SPDM_ERROR_CODE_DECRYPT_ERROR response or drop the request silently. + * If the 0x1 is not set, generate SPDM_ERROR_CODE_DECRYPT_ERROR response. + * If the 0x1 set, drop the request silently. + **/ +#define LIBSPDM_DATA_HANDLE_ERROR_RETURN_POLICY_DROP_ON_DECRYPT_ERROR 0x1 + +#define LIBSPDM_MSG_LOG_STATUS_BUFFER_FULL 1 +#define LIBSPDM_MSG_LOG_MODE_ENABLE 1 + +typedef enum { + LIBSPDM_DATA_LOCATION_LOCAL, + LIBSPDM_DATA_LOCATION_CONNECTION, + LIBSPDM_DATA_LOCATION_SESSION, + LIBSPDM_DATA_LOCATION_MAX +} libspdm_data_location_t; + +typedef struct { + libspdm_data_location_t location; + /* data_type specific: + * session_id for the negoatiated key. + * SlotId for the certificate. + * req_slot_id + measurement_hash_type for LIBSPDM_DATA_MUT_AUTH_REQUESTED*/ + uint8_t additional_data[4]; +} libspdm_data_parameter_t; + +typedef enum { + /* Before GET_VERSION/VERSION */ + LIBSPDM_CONNECTION_STATE_NOT_STARTED, + + /* After GET_VERSION/VERSION */ + LIBSPDM_CONNECTION_STATE_AFTER_VERSION, + + /* After GET_CAPABILITIES/CAPABILITIES */ + LIBSPDM_CONNECTION_STATE_AFTER_CAPABILITIES, + + /* After NEGOTIATE_ALGORITHMS/ALGORITHMS */ + LIBSPDM_CONNECTION_STATE_NEGOTIATED, + + /* After GET_DIGESTS/DIGESTS */ + LIBSPDM_CONNECTION_STATE_AFTER_DIGESTS, + + /* After GET_CERTIFICATE/CERTIFICATE */ + LIBSPDM_CONNECTION_STATE_AFTER_CERTIFICATE, + + /* After CHALLENGE/CHALLENGE_AUTH, and ENCAP CALLENGE/CHALLENG_AUTH if MUT_AUTH is enabled. */ + LIBSPDM_CONNECTION_STATE_AUTHENTICATED, + + /* MAX */ + LIBSPDM_CONNECTION_STATE_MAX +} libspdm_connection_state_t; + +typedef enum { + /* Normal response. */ + LIBSPDM_RESPONSE_STATE_NORMAL, + + /* Other component is busy. */ + LIBSPDM_RESPONSE_STATE_BUSY, + + /* Hardware is not ready. */ + LIBSPDM_RESPONSE_STATE_NOT_READY, + + /* Firmware Update is done. Need resync. */ + LIBSPDM_RESPONSE_STATE_NEED_RESYNC, + + /* Processing Encapsulated message. */ + LIBSPDM_RESPONSE_STATE_PROCESSING_ENCAP, + + /* MAX */ + LIBSPDM_RESPONSE_STATE_MAX +} libspdm_response_state_t; + +/** + * Set an SPDM context data. + * + * @param spdm_context A pointer to the SPDM context. + * @param data_type Type of the SPDM context data. + * @param parameter Type specific parameter of the SPDM context data. + * @param data A pointer to the SPDM context data. + * @param data_size Size in bytes of the SPDM context data. + * + * @retval RETURN_SUCCESS The SPDM context data is set successfully. + * @retval RETURN_INVALID_PARAMETER The data is NULL or the data_type is zero. + * @retval RETURN_UNSUPPORTED The data_type is unsupported. + * @retval RETURN_ACCESS_DENIED The data_type cannot be set. + * @retval RETURN_NOT_READY data is not ready to set. + **/ +libspdm_return_t libspdm_set_data(void *spdm_context, + libspdm_data_type_t data_type, + const libspdm_data_parameter_t *parameter, void *data, + size_t data_size); + +/** + * Get an SPDM context data. + * + * @param spdm_context A pointer to the SPDM context. + * @param data_type Type of the SPDM context data. + * @param parameter Type specific parameter of the SPDM context data. + * @param data A pointer to the SPDM context data. + * @param data_size Size in bytes of the SPDM context data. + * On input, it means the size in bytes of data buffer. + * On output, it means the size in bytes of copied data buffer if RETURN_SUCCESS, + * and means the size in bytes of desired data buffer if RETURN_BUFFER_TOO_SMALL. + * + * @retval RETURN_SUCCESS The SPDM context data is set successfully. + * @retval RETURN_INVALID_PARAMETER The data_size is NULL or the data is NULL and *data_size is not zero. + * @retval RETURN_UNSUPPORTED The data_type is unsupported. + * @retval RETURN_NOT_FOUND The data_type cannot be found. + * @retval RETURN_NOT_READY The data is not ready to return. + * @retval RETURN_BUFFER_TOO_SMALL The buffer is too small to hold the data. + **/ +libspdm_return_t libspdm_get_data(void *spdm_context, + libspdm_data_type_t data_type, + const libspdm_data_parameter_t *parameter, + void *data, size_t *data_size); + +/** + * Get the last SPDM error struct of an SPDM context. + * + * @param spdm_context A pointer to the SPDM context. + * @param last_spdm_error Last SPDM error struct of an SPDM context. + */ +void libspdm_get_last_spdm_error_struct(void *spdm_context, + libspdm_error_struct_t *last_spdm_error); + +/** + * Set the last SPDM error struct of an SPDM context. + * + * @param spdm_context A pointer to the SPDM context. + * @param last_spdm_error Last SPDM error struct of an SPDM context. + */ +void libspdm_set_last_spdm_error_struct(void *spdm_context, + libspdm_error_struct_t *last_spdm_error); + +/** + * Initialize an SPDM context, as well as all secured message contexts, + * in the specified locations. + * + * The size in bytes of the spdm_context can be returned by + * libspdm_get_context_size_without_secured_context. + * + * The size in bytes of a single secured message context can be returned by + * libspdm_secured_message_get_context_size. + * + * @param spdm_context A pointer to the SPDM context. + * @param secured_contexts An array of pointers, with each entry containing + * the location of a secured message context. + * @param num_secured_contexts Number of secured message contexts to initialize. + * Currently, only LIBSPDM_MAX_SESSION_COUNT is supported. + * In future releases, lesser values may be supported. + * + * @retval RETURN_SUCCESS Contexts are initialized. + * @retval RETURN_DEVICE_ERROR Context initialization failed. + */ +libspdm_return_t libspdm_init_context_with_secured_context(void *spdm_context, + void **secured_contexts, + size_t num_secured_contexts); + +/** + * Initialize an SPDM context, as well as secured message contexts. + * The secured message contexts are appended to the context structure. + * + * The total size in bytes of the spdm_context and all secured message + * contexts can be returned by libspdm_get_context_size(). + * + * @param spdm_context A pointer to the SPDM context. + * + * @retval RETURN_SUCCESS context is initialized. + * @retval RETURN_DEVICE_ERROR context initialization failed. + */ +libspdm_return_t libspdm_init_context(void *spdm_context); + +/** + * Reset an SPDM context. + * + * The size in bytes of the spdm_context can be returned by libspdm_get_context_size. + * + * @param spdm_context A pointer to the SPDM context. + */ +void libspdm_reset_context(void *spdm_context); + +/** + * Free the memory of contexts within the SPDM context. + * These are typically contexts whose memory has been allocated by the cryptography library. + * This function does not free the SPDM context itself. + * + * @param[in] spdm_context A pointer to the SPDM context. + * + */ +void libspdm_deinit_context(void *spdm_context); + +/** + * Return the size in bytes of the SPDM context. This includes all + * secured message context data as well. + * + * For just the SPDM context size, use libspdm_get_context_size_without_secured_context. + * + * @return the size in bytes of the SPDM context and secured message contexts. + **/ +size_t libspdm_get_context_size(void); + +/** + * Return the size in bytes of just the SPDM context, without secured message context. + * + * For the complete context size, use libspdm_get_context_size. + * + * @return the size in bytes of the SPDM context. + **/ +size_t libspdm_get_context_size_without_secured_context(void); + +/** + * Send an SPDM transport layer message to a device. + * + * The message is an SPDM message with transport layer wrapper, + * or a secured SPDM message with transport layer wrapper. + * + * For requester, the message is a transport layer SPDM request. + * For responder, the message is a transport layer SPDM response. + * + * @param spdm_context A pointer to the SPDM context. + * @param message_size Size in bytes of the message data buffer. + * @param message A pointer to a destination buffer to store the message. + * The caller is responsible for having either implicit or explicit ownership + * of the buffer. The message pointer shall be inside of + * [msg_buf_ptr, msg_buf_ptr + max_msg_size] from acquired sender_buffer. + * @param timeout The timeout, in us units, to use for the execution of the message. A + * timeout value of 0 means that this function will wait indefinitely for the + * message to execute. If timeout is greater than zero, then this function + * will return RETURN_TIMEOUT if the time required to execute the message is + * greater than timeout. + * + * @retval RETURN_SUCCESS The SPDM message is sent successfully. + * @retval RETURN_DEVICE_ERROR A device error occurs when the SPDM message is sent to the device. + * @retval RETURN_INVALID_PARAMETER The message is NULL or the message_size is zero. + * @retval RETURN_TIMEOUT A timeout occurred while waiting for the SPDM message + * to execute. + **/ +typedef libspdm_return_t (*libspdm_device_send_message_func)(void *spdm_context, + size_t message_size, + const void *message, + uint64_t timeout); + +/** + * Receive an SPDM transport layer message from a device. + * + * The message is an SPDM message with transport layer wrapper, + * or a secured SPDM message with transport layer wrapper. + * + * For requester, the message is a transport layer SPDM response. + * For responder, the message is a transport layer SPDM request. + * + * @param spdm_context A pointer to the SPDM context. + * @param message_size Size in bytes of the message data buffer. + * @param message A pointer to a destination buffer to store the message. + * The caller is responsible for having either implicit or explicit ownership + * of the buffer. On input, the message pointer shall be msg_buf_ptr from + * acquired receiver_buffer. On output, the message pointer shall be inside of + * [msg_buf_ptr, msg_buf_ptr + max_msg_size] from acquired receiver_buffer. + * @param timeout The timeout, in us units, to use for the execution of the message. A + * timeout value of 0 means that this function will wait indefinitely for the + * message to execute. If timeout is greater than zero, then this function + * will return RETURN_TIMEOUT if the time required to execute the message is + * greater than timeout. + * + * @retval RETURN_SUCCESS The SPDM message is received successfully. + * @retval RETURN_DEVICE_ERROR A device error occurs when the SPDM message is received from the device. + * @retval RETURN_INVALID_PARAMETER The message is NULL, message_size is NULL or + * the *message_size is zero. + * @retval RETURN_TIMEOUT A timeout occurred while waiting for the SPDM message + * to execute. + **/ +typedef libspdm_return_t (*libspdm_device_receive_message_func)( + void *spdm_context, size_t *message_size, void **message, + uint64_t timeout); + +/** + * Register SPDM device input/output functions. + * + * This function must be called after libspdm_init_context, and before any SPDM communication. + * + * @param spdm_context A pointer to the SPDM context. + * @param send_message The fuction to send an SPDM transport layer message. + * @param receive_message The fuction to receive an SPDM transport layer message. + **/ +void libspdm_register_device_io_func( + void *spdm_context, libspdm_device_send_message_func send_message, + libspdm_device_receive_message_func receive_message); + +/** + * Acquire a device sender buffer for transport layer message. + * + * The max_msg_size must be larger than + * MAX (non-secure Transport Message Header Size + + * SPDM_CAPABILITIES.DataTransferSize + + * max alignment pad size (transport specific), + * secure Transport Message Header Size + + * sizeof(spdm_secured_message_a_data_header1_t) + + * length of sequence_number (transport specific) + + * sizeof(spdm_secured_message_a_data_header2_t) + + * sizeof(spdm_secured_message_cipher_header_t) + + * App Message Header Size (transport specific) + + * SPDM_CAPABILITIES.DataTransferSize + + * maximum random data size (transport specific) + + * AEAD MAC size (16) + + * max alignment pad size (transport specific)) + * + * For MCTP, + * Transport Message Header Size = sizeof(mctp_message_header_t) + * length of sequence_number = 2 + * App Message Header Size = sizeof(mctp_message_header_t) + * maximum random data size = MCTP_MAX_RANDOM_NUMBER_COUNT + * max alignment pad size = 0 + * For PCI_DOE, + * Transport Message Header Size = sizeof(pci_doe_data_object_header_t) + * length of sequence_number = 0 + * App Message Header Size = 0 + * maximum random data size = 0 + * max alignment pad size = 3 + * + * @param context A pointer to the SPDM context. + * @param max_msg_size Size in bytes of the maximum size of sender buffer. + * @param msg_buf_ptr A pointer to a sender buffer. + * + * @retval LIBSPDM_STATUS_SUCCESS The sender buffer has been acquired. + * @retval LIBSPDM_STATUS_ACQUIRE_FAIL Unable to acquire sender buffer. + **/ +typedef libspdm_return_t (*libspdm_device_acquire_sender_buffer_func)( + void *spdm_context, size_t *max_msg_size, void **msg_buf_ptr); + +/** + * Release a device sender buffer for transport layer message. + * + * @param context A pointer to the SPDM context. + * @param msg_buf_ptr A pointer to a sender buffer. + * + * @retval RETURN_SUCCESS The sender buffer is Released. + **/ +typedef void (*libspdm_device_release_sender_buffer_func)(void *spdm_context, + const void *msg_buf_ptr); + +/** + * Acquire a device receiver buffer for transport layer message. + * + * The max_msg_size must be larger than + * MAX (non-secure Transport Message Header Size + + * SPDM_CAPABILITIES.DataTransferSize + + * max alignment pad size (transport specific), + * secure Transport Message Header Size + + * sizeof(spdm_secured_message_a_data_header1_t) + + * length of sequence_number (transport specific) + + * sizeof(spdm_secured_message_a_data_header2_t) + + * sizeof(spdm_secured_message_cipher_header_t) + + * App Message Header Size (transport specific) + + * SPDM_CAPABILITIES.DataTransferSize + + * maximum random data size (transport specific) + + * AEAD MAC size (16) + + * max alignment pad size (transport specific)) + * + * For MCTP, + * Transport Message Header Size = sizeof(mctp_message_header_t) + * length of sequence_number = 2 + * App Message Header Size = sizeof(mctp_message_header_t) + * maximum random data size = MCTP_MAX_RANDOM_NUMBER_COUNT + * max alignment pad size = 0 + * For PCI_DOE, + * Transport Message Header Size = sizeof(pci_doe_data_object_header_t) + * length of sequence_number = 0 + * App Message Header Size = 0 + * maximum random data size = 0 + * max alignment pad size = 3 + * + * @param context A pointer to the SPDM context. + * @param max_msg_size Size in bytes of the maximum size of receiver buffer. + * @param msg_buf_pt A pointer to a receiver buffer. + * + * @retval LIBSPDM_STATUS_SUCCESS The receiver buffer has been acquired. + * @retval LIBSPDM_STATUS_ACQUIRE_FAIL Unable to acquire receiver buffer. + **/ +typedef libspdm_return_t (*libspdm_device_acquire_receiver_buffer_func)( + void *spdm_context, size_t *max_msg_size, void **msg_buf_ptr); + +/** + * Release a device receiver buffer for transport layer message. + * + * @param context A pointer to the SPDM context. + * @param msg_buf_ptr A pointer to a receiver buffer. + * + * @retval RETURN_SUCCESS The receiver buffer is Released. + **/ +typedef void (*libspdm_device_release_receiver_buffer_func)(void *spdm_context, + const void *msg_buf_ptr); + +/** + * Register SPDM device buffer management functions. + * + * This function must be called after libspdm_init_context, and before any SPDM communication. + * + * @param spdm_context A pointer to the SPDM context. + * @param acquire_sender_buffer The fuction to acquire transport layer sender buffer. + * @param release_sender_buffer The fuction to release transport layer sender buffer. + * @param acquire_receiver_buffer The fuction to acquire transport layer receiver buffer. + * @param release_receiver_buffer The fuction to release transport layer receiver buffer. + **/ +void libspdm_register_device_buffer_func( + void *spdm_context, + libspdm_device_acquire_sender_buffer_func acquire_sender_buffer, + libspdm_device_release_sender_buffer_func release_sender_buffer, + libspdm_device_acquire_receiver_buffer_func acquire_receiver_buffer, + libspdm_device_release_receiver_buffer_func release_receiver_buffer); + +/** + * Encode an SPDM or APP message to a transport layer message. + * + * For normal SPDM message, it adds the transport layer wrapper. + * For secured SPDM message, it encrypts a secured message then adds the transport layer wrapper. + * For secured APP message, it encrypts a secured message then adds the transport layer wrapper. + * + * The APP message is encoded to a secured message directly in SPDM session. + * The APP message format is defined by the transport layer. + * Take MCTP as example: APP message == MCTP header (MCTP_MESSAGE_TYPE_SPDM) + SPDM message + * + * @param spdm_context A pointer to the SPDM context. + * @param session_id Indicates if it is a secured message protected via SPDM session. + * If session_id is NULL, it is a normal message. + * If session_id is not NULL, it is a secured message. + * @param is_app_message Indicates if it is an APP message or SPDM message. + * @param is_requester Indicates if it is a requester message. + * @param message_size Size in bytes of the message data buffer. + * @param message A pointer to a source buffer to store the message. + * For normal message, it shall point to the acquired sender buffer. + * For secured message, it shall point to the scratch buffer in spdm_context. + * @param transport_message_size Size in bytes of the transport message data buffer. + * @param transport_message A pointer to a destination buffer to store the transport message. + * On input, it shall be msg_buf_ptr from sender buffer. + * On output, it will point to acquired sender buffer. + * + * @retval RETURN_SUCCESS The message is encoded successfully. + * @retval RETURN_INVALID_PARAMETER The message is NULL or the message_size is zero. + **/ +typedef libspdm_return_t (*libspdm_transport_encode_message_func)( + void *spdm_context, const uint32_t *session_id, bool is_app_message, + bool is_requester, size_t message_size, + void *message, size_t *transport_message_size, + void **transport_message); + +/** + * Decode an SPDM or APP message from a transport layer message. + * + * For normal SPDM message, it removes the transport layer wrapper, + * For secured SPDM message, it removes the transport layer wrapper, then decrypts and verifies a secured message. + * For secured APP message, it removes the transport layer wrapper, then decrypts and verifies a secured message. + * + * The APP message is decoded from a secured message directly in SPDM session. + * The APP message format is defined by the transport layer. + * Take MCTP as example: APP message == MCTP header (MCTP_MESSAGE_TYPE_SPDM) + SPDM message + * + * @param spdm_context A pointer to the SPDM context. + * @param session_id Indicates if it is a secured message protected via SPDM session. + * If session_id is NULL, it is a normal message. + * If session_id is not NULL, it is a secured message. + * @param is_app_message Indicates if it is an APP message or SPDM message. + * @param is_requester Indicates if it is a requester message. + * @param transport_message_size Size in bytes of the transport message data buffer. + * @param transport_message A pointer to a source buffer to store the transport message. + * For normal message or secured message, it shall point to acquired receiver buffer. + * @param message_size Size in bytes of the message data buffer. + * @param message A pointer to a destination buffer to store the message. + * On input, it shall point to the scratch buffer in spdm_context. + * On output, for normal message, it will point to the original receiver buffer. + * On output, for secured message, it will point to the scratch buffer in spdm_context. + * + * @retval RETURN_SUCCESS The message is decoded successfully. + * @retval RETURN_INVALID_PARAMETER The message is NULL or the message_size is zero. + * @retval RETURN_UNSUPPORTED The transport_message is unsupported. + **/ +typedef libspdm_return_t (*libspdm_transport_decode_message_func)( + void *spdm_context, uint32_t **session_id, + bool *is_app_message, bool is_requester, + size_t transport_message_size, void *transport_message, + size_t *message_size, void **message); + +/** + * Return the maximum transport layer message header size. + * Transport Message Header Size + sizeof(spdm_secured_message_cipher_header_t)) + * + * For MCTP, Transport Message Header Size = sizeof(mctp_message_header_t) + * For PCI_DOE, Transport Message Header Size = sizeof(pci_doe_data_object_header_t) + * + * @param spdm_context A pointer to the SPDM context. + * + * @return size of maximum transport layer message header size + **/ +typedef uint32_t (*libspdm_transport_get_header_size_func)(void *spdm_context); + +/** + * Register SPDM transport layer encode/decode functions for SPDM or APP messages. + * + * This function must be called after libspdm_init_context, and before any SPDM communication. + * + * @param spdm_context A pointer to the SPDM context. + * @param transport_encode_message The fuction to encode an SPDM or APP message to a transport layer message. + * @param transport_decode_message The fuction to decode an SPDM or APP message from a transport layer message. + * @param transport_get_header_size The fuction to get the maximum transport layer message header size. + **/ +void libspdm_register_transport_layer_func( + void *spdm_context, + libspdm_transport_encode_message_func transport_encode_message, + libspdm_transport_decode_message_func transport_decode_message, + libspdm_transport_get_header_size_func transport_get_header_size); + +/** + * Get the size of required scratch buffer. + * + * The SPDM Integrator must call libspdm_get_sizeof_required_scratch_buffer to get the size, + * then allocate enough scratch buffer and call libspdm_set_scratch_buffer(). + * + * @param context A pointer to the SPDM context. + * + * @return the size of required scratch buffer. + **/ +size_t libspdm_get_sizeof_required_scratch_buffer (void *spdm_context); + +/** + * Set the scratch buffer. + * + * The size of scratch buffer must be larger than the value returned in + * libspdm_get_sizeof_required_scratch_buffer(). + * + * This function must be called after libspdm_init_context, and before any SPDM communication. + * + * @param spdm_context A pointer to the SPDM context. + * @param scratch_buffer Buffer address of the scratch buffer. + * @param scratch_buffer_size Size of the scratch buffer. + * + **/ +void libspdm_set_scratch_buffer ( + void *spdm_context, + void *scratch_buffer, + size_t scratch_buffer_size); + +/** + * Get the scratch buffer. + * + * @param spdm_context A pointer to the SPDM context. + * @param scratch_buffer Buffer address of the scratch buffer. + * @param scratch_buffer_size Size of the scratch buffer. + * + **/ +void libspdm_get_scratch_buffer ( + void *spdm_context, + void **scratch_buffer, + size_t *scratch_buffer_size); + +/** + * Verify a SPDM cert chain in a slot. + * + * This function shall verify: + * 1) The integrity of the certificate chain. (Root Cert Hash->Root Cert->Cert Chain) + * 2) The trust anchor. (Root Cert Hash/Root cert matches the trust anchor) + * + * The function shall check the negotiated hash algorithm to check root cert hash. + * The function shall check the negotiated (req) asym algorithm to determine if it is right cert chain. + * + * The function returns error if either of above is not satisfied. + * + * @param spdm_context A pointer to the SPDM context. + * @param slot_id The number of slot for the certificate chain. + * @param cert_chain_size Indicate the size in bytes of the certificate chain. + * @param cert_chain A pointer to the buffer storing the certificate chain + * returned from GET_CERTIFICATE. It starts with spdm_cert_chain_t. + * @param trust_anchor A buffer to hold the trust_anchor which is used to validate the peer certificate, if not NULL. + * @param trust_anchor_size A buffer to hold the trust_anchor_size, if not NULL. + * + * @retval RETURN_SUCCESS The cert chain verification pass. + * @retval RETURN_SECURIY_VIOLATION The cert chain verification fail. + **/ +typedef bool (*libspdm_verify_spdm_cert_chain_func)( + void *spdm_context, uint8_t slot_id, + size_t cert_chain_size, const void *cert_chain, + const void **trust_anchor, + size_t *trust_anchor_size); + +/** + * Register SPDM certificate verification functions for SPDM GET_CERTIFICATE in requester or responder. + * It is called after GET_CERTIFICATE gets a full certificate chain from peer. + * + * If it is NOT registered, the default verification in SPDM lib will be used. It verifies: + * 1) The integrity of the certificate chain, (Root Cert Hash->Root Cert->Cert Chain), according to X.509. + * 2) The trust anchor, according LIBSPDM_DATA_PEER_PUBLIC_ROOT_CERT or LIBSPDM_DATA_PEER_PUBLIC_CERT_CHAIN. + * If it is registered, SPDM lib will use this function to verify the certificate. + * + * This function must be called after libspdm_init_context, and before any SPDM communication. + * + * @param spdm_context A pointer to the SPDM context. + * @param verify_certificate The fuction to verify an SPDM certificate after GET_CERTIFICATE. + **/ +void libspdm_register_verify_spdm_cert_chain_func( + void *spdm_context, + const libspdm_verify_spdm_cert_chain_func verify_spdm_cert_chain); + +/** + * This function gets the session info via session ID. + * + * @param spdm_context A pointer to the SPDM context. + * @param session_id The SPDM session ID. + * + * @return session info. + **/ +void *libspdm_get_session_info_via_session_id(void *spdm_context, uint32_t session_id); + +/** + * This function gets the secured message context via session ID. + * + * @param spdm_context A pointer to the SPDM context. + * @param session_id The SPDM session ID. + * + * @return secured message context. + **/ +void *libspdm_get_secured_message_context_via_session_id(void *spdm_context, uint32_t session_id); + +/** + * This function gets the secured message context via session ID. + * + * @param spdm_session_info A pointer to the SPDM context. + * + * @return secured message context. + **/ +void *libspdm_get_secured_message_context_via_session_info(void *spdm_session_info); + +/** + * This function returns peer certificate chain buffer including spdm_cert_chain_t header. + * + * @param spdm_context A pointer to the SPDM context. + * @param cert_chain_buffer Certitiface chain buffer including spdm_cert_chain_t header. + * @param cert_chain_buffer_size Size in bytes of the certitiface chain buffer. + * + * @retval true Peer certificate chain buffer including spdm_cert_chain_t header is returned. + * @retval false Peer certificate chain buffer including spdm_cert_chain_t header is not found. + **/ +bool libspdm_get_peer_cert_chain_buffer(void *spdm_context, + const void **cert_chain_buffer, + size_t *cert_chain_buffer_size); + +/** + * This function returns peer certificate chain data without spdm_cert_chain_t header. + * + * @param spdm_context A pointer to the SPDM context. + * @param cert_chain_data Certitiface chain data without spdm_cert_chain_t header. + * @param cert_chain_data_size Size in bytes of the certitiface chain data. + * + * @retval true Peer certificate chain data without spdm_cert_chain_t header is returned. + * @retval false Peer certificate chain data without spdm_cert_chain_t header is not found. + **/ +bool libspdm_get_peer_cert_chain_data(void *spdm_context, + const void **cert_chain_data, + size_t *cert_chain_data_size); + +/** + * This function returns local used certificate chain buffer including spdm_cert_chain_t header. + * + * @param spdm_context A pointer to the SPDM context. + * @param cert_chain_buffer Certitiface chain buffer including spdm_cert_chain_t header. + * @param cert_chain_buffer_size Size in bytes of the certitiface chain buffer. + * + * @retval true Local used certificate chain buffer including spdm_cert_chain_t header is returned. + * @retval false Local used certificate chain buffer including spdm_cert_chain_t header is not found. + **/ +bool libspdm_get_local_cert_chain_buffer(void *spdm_context, + const void **cert_chain_buffer, + size_t *cert_chain_buffer_size); + +/** + * This function returns local used certificate chain data without spdm_cert_chain_t header. + * + * @param spdm_context A pointer to the SPDM context. + * @param cert_chain_data Certitiface chain data without spdm_cert_chain_t header. + * @param cert_chain_data_size Size in bytes of the certitiface chain data. + * + * @retval true Local used certificate chain data without spdm_cert_chain_t header is returned. + * @retval false Local used certificate chain data without spdm_cert_chain_t header is not found. + **/ +bool libspdm_get_local_cert_chain_data(void *spdm_context, + const void **cert_chain_data, + size_t *cert_chain_data_size); + +#endif /* SPDM_COMMON_LIB_H */ diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/libraries/libspdm/2.3.1/include/library/spdm_crypt_lib.h nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/libraries/libspdm/2.3.1/include/library/spdm_crypt_lib.h --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/libraries/libspdm/2.3.1/include/library/spdm_crypt_lib.h 1970-01-01 00:00:00.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/libraries/libspdm/2.3.1/include/library/spdm_crypt_lib.h 2024-03-05 22:14:13.000000000 +0000 @@ -0,0 +1,877 @@ +/** + * Copyright Notice: + * Copyright 2021-2022 DMTF. All rights reserved. + * License: BSD 3-Clause License. For full text see link: https://github.com/DMTF/libspdm/blob/main/LICENSE.md + **/ + +#ifndef SPDM_CRYPT_LIB_H +#define SPDM_CRYPT_LIB_H + +#include "internal/libspdm_lib_config.h" + +#include "hal/base.h" +#include "industry_standard/spdm.h" + +#define LIBSPDM_MAX_DHE_KEY_SIZE 512 +#define LIBSPDM_MAX_ASYM_KEY_SIZE 512 +#define LIBSPDM_MAX_HASH_SIZE 64 +#define LIBSPDM_MAX_AEAD_KEY_SIZE 32 +#define LIBSPDM_MAX_AEAD_IV_SIZE 12 +#define LIBSPDM_MAX_AEAD_TAG_SIZE 16 + +/** + * This function returns the SPDM hash algorithm size. + * + * @param base_hash_algo SPDM base_hash_algo + * + * @return SPDM hash algorithm size. + **/ +uint32_t libspdm_get_hash_size(uint32_t base_hash_algo); + +/** + * Return cipher ID, based upon the negotiated hash algorithm. + * + * @param base_hash_algo SPDM base_hash_algo + * + * @return hash cipher ID + **/ +size_t libspdm_get_hash_nid(uint32_t base_hash_algo); + +/** + * Allocates and initializes one HASH_CTX context for subsequent hash use. + * + * @param base_hash_algo SPDM base_hash_algo + * + * @return Pointer to the HASH_CTX context that has been initialized. + * If the allocations fails, libspdm_hash_new() returns NULL. + **/ +void *libspdm_hash_new(uint32_t base_hash_algo); + +/** + * Release the specified HASH_CTX context. + * + * @param base_hash_algo SPDM base_hash_algo + * @param hash_context Pointer to the HASH_CTX context to be released. + **/ +void libspdm_hash_free(uint32_t base_hash_algo, void *hash_context); + +/** + * Initializes user-supplied memory pointed by hash_context as hash context for + * subsequent use. + * + * @param base_hash_algo SPDM base_hash_algo + * @param hash_context Pointer to hash context being initialized. + * + * @retval true Hash context initialization succeeded. + * @retval false Hash context initialization failed. + **/ +bool libspdm_hash_init(uint32_t base_hash_algo, void *hash_context); + +/** + * Makes a copy of an existing hash context. + * + * If hash_ctx is NULL, then return false. + * If new_hash_ctx is NULL, then return false. + * + * @param[in] hash_ctx Pointer to hash context being copied. + * @param[out] new_hash_ctx Pointer to new hash context. + * + * @retval true Hash context copy succeeded. + * @retval false Hash context copy failed. + **/ +bool libspdm_hash_duplicate(uint32_t base_hash_algo, const void *hash_ctx, void *new_hash_ctx); + +/** + * Digests the input data and updates hash context. + * + * This function performs hash digest on a data buffer of the specified size. + * It can be called multiple times to compute the digest of long or discontinuous data streams. + * Hash context should be already correctly initialized by hash_init(), and should not be finalized + * by hash_final(). Behavior with invalid context is undefined. + * + * If hash_context is NULL, then return false. + * + * @param[in, out] hash_context Pointer to the MD context. + * @param[in] data Pointer to the buffer containing the data to be hashed. + * @param[in] data_size Size of data buffer in bytes. + * + * @retval true Hash data digest succeeded. + * @retval false Hash data digest failed. + **/ +bool libspdm_hash_update(uint32_t base_hash_algo, void *hash_context, + const void *data, size_t data_size); + +/** + * Completes computation of the hash digest value. + * + * This function completes hash computation and retrieves the digest value into + * the specified memory. After this function has been called, the hash context cannot + * be used again. + * hash context should be already correctly initialized by hash_init(), and should not be + * finalized by hash_final(). Behavior with invalid hash context is undefined. + * + * If hash_context is NULL, then return false. + * If hash_value is NULL, then return false. + * + * @param[in, out] hash_context Pointer to the hash context. + * @param[out] hash_value Pointer to a buffer that receives the hash digest value. + * + * @retval true Hash digest computation succeeded. + * @retval false Hash digest computation failed. + **/ +bool libspdm_hash_final(uint32_t base_hash_algo, void *hash_context, uint8_t *hash_value); + +/** + * Allocates and initializes one HMAC context for subsequent use. + * + * @param base_hash_algo SPDM base_hash_algo + * + * @return Pointer to the HMAC context that has been initialized. + * If the allocations fails, libspdm_hash_new() returns NULL. + **/ +void *libspdm_hmac_new(uint32_t base_hash_algo); + +/** + * Release the specified HMAC context. + * + * @param base_hash_algo SPDM base_hash_algo + * @param hmac_ctx Pointer to the HMAC context to be released. + **/ +void libspdm_hmac_free(uint32_t base_hash_algo, void *hmac_ctx); + +/** + * Set user-supplied key for subsequent use. It must be done before any + * calling to hmac_update(). + * + * If hmac_ctx is NULL, then return false. + * + * @param[out] hmac_ctx Pointer to HMAC context. + * @param[in] key Pointer to the user-supplied key. + * @param[in] key_size Key size in bytes. + * + * @retval true The key is set successfully. + * @retval false The key is set unsuccessfully. + * + **/ +bool libspdm_hmac_init(uint32_t base_hash_algo, + void *hmac_ctx, + const uint8_t *key, + size_t key_size); + +/** + * Makes a copy of an existing HMAC context. + * + * If hmac_ctx is NULL, then return false. + * If new_hmac_ctx is NULL, then return false. + * + * @param[in] hmac_ctx Pointer to HMAC context being copied. + * @param[out] new_hmac_ctx Pointer to new HMAC context. + * + * @retval true HMAC context copy succeeded. + * @retval false HMAC context copy failed. + * + **/ +bool libspdm_hmac_duplicate(uint32_t base_hash_algo, const void *hmac_ctx, void *new_hmac_ctx); + +/** + * Digests the input data and updates HMAC context. + * + * This function performs HMAC digest on a data buffer of the specified size. + * It can be called multiple times to compute the digest of long or discontinuous data streams. + * HMAC context should be initialized by hmac_new(), and should not be finalized + * by hmac_final(). Behavior with invalid context is undefined. + * + * If hmac_ctx is NULL, then return false. + * + * @param[in, out] hmac_ctx Pointer to the HMAC context. + * @param[in] data Pointer to the buffer containing the data to be digested. + * @param[in] data_size Size of data buffer in bytes. + * + * @retval true HMAC data digest succeeded. + * @retval false HMAC data digest failed. + * + **/ +bool libspdm_hmac_update(uint32_t base_hash_algo, + void *hmac_ctx, const void *data, + size_t data_size); + +/** + * Completes computation of the HMAC digest value. + * + * This function completes HMAC hash computation and retrieves the digest value into + * the specified memory. After this function has been called, the HMAC context cannot + * be used again. + * + * If hmac_ctx is NULL, then return false. + * If hmac_value is NULL, then return false. + * + * @param[in, out] hmac_ctx Pointer to the HMAC context. + * @param[out] hmac_value Pointer to a buffer that receives the HMAC digest value. + * + * @retval true HMAC digest computation succeeded. + * @retval false HMAC digest computation failed. + * + **/ +bool libspdm_hmac_final(uint32_t base_hash_algo, void *hmac_ctx, uint8_t *hmac_value); + +/** + * Computes the hash of a input data buffer, based upon the negotiated hash algorithm. + * + * This function performs the hash of a given data buffer, and return the hash value. + * + * @param base_hash_algo SPDM base_hash_algo + * @param data Pointer to the buffer containing the data to be hashed. + * @param data_size Size of data buffer in bytes. + * @param hash_value Pointer to a buffer that receives the hash value. + * + * @retval true Hash computation succeeded. + * @retval false Hash computation failed. + **/ +bool libspdm_hash_all(uint32_t base_hash_algo, const void *data, + size_t data_size, uint8_t *hash_value); + +/** + * This function returns the SPDM measurement hash algorithm size. + * + * @param measurement_hash_algo SPDM measurement_hash_algo. + * + * @return SPDM measurement hash algorithm size. + * @return 0xFFFFFFFF for RAW_BIT_STREAM_ONLY. + **/ +uint32_t libspdm_get_measurement_hash_size(uint32_t measurement_hash_algo); + +/** + * Computes the HMAC of a input data buffer, based upon the negotiated HMAC algorithm. + * + * This function performs the HMAC of a given data buffer, and return the hash value. + * + * @param base_hash_algo SPDM base_hash_algo + * @param data Pointer to the buffer containing the data to be HMACed. + * @param data_size Size of data buffer in bytes. + * @param key Pointer to the user-supplied key. + * @param key_size Key size in bytes. + * @param hash_value Pointer to a buffer that receives the HMAC value. + * + * @retval true HMAC computation succeeded. + * @retval false HMAC computation failed. + **/ +bool libspdm_hmac_all(uint32_t base_hash_algo, const void *data, + size_t data_size, const uint8_t *key, + size_t key_size, uint8_t *hmac_value); + +/** + * Derive HMAC-based Extract key Derivation Function (HKDF) Extract, based upon the negotiated HKDF + * algorithm. + * + * @param ikm Pointer to the input key material. + * @param ikm_size Key size in bytes. + * @param salt Pointer to the salt value. + * @param salt_size Salt size in bytes. + * @param prk_out Pointer to buffer to receive hkdf value. + * @param prk_out_size Size of hkdf bytes to generate. + * + * @retval true Hkdf generated successfully. + * @retval false Hkdf generation failed. + **/ +bool libspdm_hkdf_extract(uint32_t base_hash_algo, const uint8_t *ikm, size_t ikm_size, + const uint8_t *salt, size_t salt_size, + uint8_t *prk_out, size_t prk_out_size); + +/** + * Derive HMAC-based Expand key Derivation Function (HKDF) Expand, based upon the negotiated HKDF + * algorithm. + * + * @param base_hash_algo SPDM base_hash_algo + * @param prk Pointer to the user-supplied key. + * @param prk_size Key size in bytes. + * @param info Pointer to the application specific info. + * @param info_size Info size in bytes. + * @param out Pointer to buffer to receive hkdf value. + * @param out_size Size of hkdf bytes to generate. + * + * @retval true Hkdf generated successfully. + * @retval false Hkdf generation failed. + **/ +bool libspdm_hkdf_expand(uint32_t base_hash_algo, const uint8_t *prk, + size_t prk_size, const uint8_t *info, + size_t info_size, uint8_t *out, size_t out_size); + +/** + * This function returns the SPDM asymmetric algorithm size. + * + * @param base_asym_algo SPDM base_hash_algo + * + * @return SPDM asymmetric algorithm size. + **/ +uint32_t libspdm_get_asym_signature_size(uint32_t base_asym_algo); + +/** + * Retrieve the asymmetric public key from one DER-encoded X509 certificate, + * based upon negotiated asymmetric algorithm. + * + * @param base_asym_algo SPDM base_asym_algo + * @param cert Pointer to the DER-encoded X509 certificate. + * @param cert_size Size of the X509 certificate in bytes. + * @param context Pointer to new-generated asymmetric context which contain the retrieved + * public key component. Use libspdm_asym_free() function to free the + * resource. + * + * @retval true Public key was retrieved successfully. + * @retval false Fail to retrieve public key from X509 certificate. + **/ +bool libspdm_asym_get_public_key_from_x509(uint32_t base_asym_algo, + const uint8_t *cert, + size_t cert_size, + void **context); + +/** + * Release the specified asymmetric context, based upon negotiated asymmetric algorithm. + * + * @param base_asym_algo SPDM base_asym_algo + * @param context Pointer to the asymmetric context to be released. + **/ +void libspdm_asym_free(uint32_t base_asym_algo, void *context); + +/** + * Verifies the asymmetric signature, based upon negotiated asymmetric algorithm. + * + * @param base_asym_algo SPDM base_asym_algo + * @param base_hash_algo SPDM base_hash_algo + * @param context Pointer to asymmetric context for signature verification. + * @param message Pointer to octet message to be checked (before hash). + * @param message_size Size of the message in bytes. + * @param signature Pointer to asymmetric signature to be verified. + * @param sig_size Size of signature in bytes. + * + * @retval true Valid asymmetric signature. + * @retval false Invalid asymmetric signature or invalid asymmetric context. + **/ +bool libspdm_asym_verify( + spdm_version_number_t spdm_version, uint8_t op_code, + uint32_t base_asym_algo, uint32_t base_hash_algo, + void *context, const uint8_t *message, + size_t message_size, const uint8_t *signature, + size_t sig_size); + +/** + * Verifies the asymmetric signature, based upon negotiated asymmetric algorithm. + * + * @param base_asym_algo SPDM base_asym_algo + * @param base_hash_algo SPDM base_hash_algo + * @param context Pointer to asymmetric context for signature verification. + * @param message_hash Pointer to octet message hash to be checked (after hash). + * @param hash_size Size of the hash in bytes. + * @param signature Pointer to asymmetric signature to be verified. + * @param sig_size Size of signature in bytes. + * + * @retval true Valid asymmetric signature. + * @retval false Invalid asymmetric signature or invalid asymmetric context. + **/ +bool libspdm_asym_verify_hash( + spdm_version_number_t spdm_version, uint8_t op_code, + uint32_t base_asym_algo, uint32_t base_hash_algo, + void *context, const uint8_t *message_hash, + size_t hash_size, const uint8_t *signature, + size_t sig_size); + +/** + * Carries out the signature generation. + * + * If the signature buffer is too small to hold the contents of signature, false + * is returned and sig_size is set to the required buffer size to obtain the signature. + * + * @param base_asym_algo SPDM base_asym_algo + * @param base_hash_algo SPDM base_hash_algo + * @param context Pointer to asymmetric context for signature generation. + * @param message Pointer to octet message to be signed (before hash). + * @param message_size Size of the message in bytes. + * @param signature Pointer to buffer to receive signature. + * @param sig_size On input, the size of signature buffer in bytes. + * On output, the size of data returned in signature buffer in bytes. + * + * @retval true Signature successfully generated. + * @retval false Signature generation failed. + * @retval false sig_size is too small. + **/ +bool libspdm_asym_sign( + spdm_version_number_t spdm_version, uint8_t op_code, + uint32_t base_asym_algo, uint32_t base_hash_algo, + void *context, const uint8_t *message, + size_t message_size, uint8_t *signature, + size_t *sig_size); + +/** + * Carries out the signature generation. + * + * If the signature buffer is too small to hold the contents of signature, false + * is returned and sig_size is set to the required buffer size to obtain the signature. + * + * @param base_asym_algo SPDM base_asym_algo + * @param base_hash_algo SPDM base_hash_algo + * @param context Pointer to asymmetric context for signature generation. + * @param message_hash Pointer to octet message hash to be signed (after hash). + * @param hash_size Size of the hash in bytes. + * @param signature Pointer to buffer to receive signature. + * @param sig_size On input, the size of signature buffer in bytes. + * On output, the size of data returned in signature buffer in bytes. + * + * @retval true Signature successfully generated. + * @retval false Signature generation failed. + * @retval false sig_size is too small. + **/ +bool libspdm_asym_sign_hash( + spdm_version_number_t spdm_version, uint8_t op_code, + uint32_t base_asym_algo, uint32_t base_hash_algo, + void *context, const uint8_t *message_hash, + size_t hash_size, uint8_t *signature, + size_t *sig_size); + +/** + * This function returns the SPDM requester asymmetric algorithm size. + * + * @param req_base_asym_alg SPDM req_base_asym_alg + * + * @return SPDM requester asymmetric algorithm size. + **/ +uint32_t libspdm_get_req_asym_signature_size(uint16_t req_base_asym_alg); + +/** + * Retrieve the asymmetric public key from one DER-encoded X509 certificate, + * based upon negotiated requester asymmetric algorithm. + * + * @param req_base_asym_alg SPDM req_base_asym_alg + * @param cert Pointer to the DER-encoded X509 certificate. + * @param cert_size Size of the X509 certificate in bytes. + * @param context Pointer to new-generated asymmetric context which contain the + * retrieved public key component. Use libspdm_asym_free() function to + * free the resource. + * + * @retval true Public key was retrieved successfully. + * @retval false Fail to retrieve public key from X509 certificate. + **/ +bool libspdm_req_asym_get_public_key_from_x509(uint16_t req_base_asym_alg, + const uint8_t *cert, + size_t cert_size, + void **context); + +/** + * Release the specified asymmetric context, based upon negotiated requester asymmetric algorithm. + * + * @param req_base_asym_alg SPDM req_base_asym_alg + * @param context Pointer to the asymmetric context to be released. + **/ +void libspdm_req_asym_free(uint16_t req_base_asym_alg, void *context); + +/** + * Verifies the asymmetric signature, based upon negotiated requester asymmetric algorithm. + * + * @param req_base_asym_alg SPDM req_base_asym_alg + * @param base_hash_algo SPDM base_hash_algo + * @param context Pointer to asymmetric context for signature verification. + * @param message Pointer to octet message to be checked (before hash). + * @param message_size Size of the message in bytes. + * @param signature Pointer to asymmetric signature to be verified. + * @param sig_size Size of signature in bytes. + * + * @retval true Valid asymmetric signature. + * @retval false Invalid asymmetric signature or invalid asymmetric context. + **/ +bool libspdm_req_asym_verify( + spdm_version_number_t spdm_version, uint8_t op_code, + uint16_t req_base_asym_alg, + uint32_t base_hash_algo, void *context, + const uint8_t *message, size_t message_size, + const uint8_t *signature, size_t sig_size); + +/** + * Verifies the asymmetric signature, based upon negotiated requester asymmetric algorithm. + * + * @param req_base_asym_alg SPDM req_base_asym_alg + * @param base_hash_algo SPDM base_hash_algo + * @param context Pointer to asymmetric context for signature verification. + * @param message_hash Pointer to octet message hash to be checked (after hash). + * @param hash_size Size of the hash in bytes. + * @param signature Pointer to asymmetric signature to be verified. + * @param sig_size Size of signature in bytes. + * + * @retval true Valid asymmetric signature. + * @retval false Invalid asymmetric signature or invalid asymmetric context. + **/ +bool libspdm_req_asym_verify_hash( + spdm_version_number_t spdm_version, uint8_t op_code, + uint16_t req_base_asym_alg, + uint32_t base_hash_algo, void *context, + const uint8_t *message_hash, size_t hash_size, + const uint8_t *signature, size_t sig_size); + +/** + * Carries out the signature generation. + * + * If the signature buffer is too small to hold the contents of signature, false + * is returned and sig_size is set to the required buffer size to obtain the signature. + * + * @param req_base_asym_alg SPDM req_base_asym_alg + * @param base_hash_algo SPDM base_hash_algo + * @param context Pointer to asymmetric context for signature generation. + * @param message Pointer to octet message to be signed (before hash). + * @param message_size Size of the message in bytes. + * @param signature Pointer to buffer to receive signature. + * @param sig_size On input, the size of signature buffer in bytes. + * On output, the size of data returned in signature buffer in bytes. + * + * @retval true Signature successfully generated. + * @retval false Signature generation failed. + * @retval false sig_size is too small. + **/ +bool libspdm_req_asym_sign( + spdm_version_number_t spdm_version, uint8_t op_code, + uint16_t req_base_asym_alg, + uint32_t base_hash_algo, void *context, + const uint8_t *message, size_t message_size, + uint8_t *signature, size_t *sig_size); + +/** + * Carries out the signature generation. + * + * If the signature buffer is too small to hold the contents of signature, false + * is returned and sig_size is set to the required buffer size to obtain the signature. + * + * @param req_base_asym_alg SPDM req_base_asym_alg + * @param base_hash_algo SPDM base_hash_algo + * @param context Pointer to asymmetric context for signature generation. + * @param message_hash Pointer to octet message hash to be signed (after hash). + * @param hash_size Size of the hash in bytes. + * @param signature Pointer to buffer to receive signature. + * @param sig_size On input, the size of signature buffer in bytes. + * On output, the size of data returned in signature buffer in bytes. + * + * @retval true Signature successfully generated. + * @retval false Signature generation failed. + * @retval false sig_size is too small. + **/ +bool libspdm_req_asym_sign_hash( + spdm_version_number_t spdm_version, uint8_t op_code, + uint16_t req_base_asym_alg, + uint32_t base_hash_algo, void *context, + const uint8_t *message_hash, size_t hash_size, + uint8_t *signature, size_t *sig_size); + +/** + * This function returns the SPDM DHE algorithm key size. + * + * @param dhe_named_group SPDM dhe_named_group + * + * @return SPDM DHE algorithm key size. + **/ +uint32_t libspdm_get_dhe_pub_key_size(uint16_t dhe_named_group); + +/** + * Allocates and Initializes one Diffie-Hellman Ephemeral (DHE) context for subsequent use, + * based upon negotiated DHE algorithm. + * + * @param dhe_named_group SPDM dhe_named_group + * @param is_initiator If the caller is initiator. + * + * @return Pointer to the Diffie-Hellman context that has been initialized. + **/ +void *libspdm_dhe_new(spdm_version_number_t spdm_version, + uint16_t dhe_named_group, bool is_initiator); + +/** + * Release the specified DHE context, based upon negotiated DHE algorithm. + * + * @param dhe_named_group SPDM dhe_named_group + * @param context Pointer to the DHE context to be released. + **/ +void libspdm_dhe_free(uint16_t dhe_named_group, void *context); + +/** + * Generates DHE public key, based upon negotiated DHE algorithm. + * + * This function generates random secret exponent, and computes the public key, which is + * returned via parameter public_key and public_key_size. DH context is updated accordingly. + * If the public_key buffer is too small to hold the public key, false is returned and + * public_key_size is set to the required buffer size to obtain the public key. + * + * @param dhe_named_group SPDM dhe_named_group + * @param context Pointer to the DHE context. + * @param public_key Pointer to the buffer to receive generated public key. + * @param public_key_size On input, the size of public_key buffer in bytes. + * On output, the size of data returned in public_key buffer in bytes. + * + * @retval true DHE public key generation succeeded. + * @retval false DHE public key generation failed. + * @retval false public_key_size is not large enough. + **/ +bool libspdm_dhe_generate_key(uint16_t dhe_named_group, void *context, + uint8_t *public_key, + size_t *public_key_size); + +/** + * Computes exchanged common key, based upon negotiated DHE algorithm. + * + * Given peer's public key, this function computes the exchanged common key, based on its own + * context including value of prime modulus and random secret exponent. + * + * @param dhe_named_group SPDM dhe_named_group + * @param context Pointer to the DHE context. + * @param peer_public_key Pointer to the peer's public key. + * @param peer_public_key_size Size of peer's public key in bytes. + * @param key Pointer to the buffer to receive generated key. + * @param key_size On input, the size of key buffer in bytes. + * On output, the size of data returned in key buffer in bytes. + * + * @retval true DHE exchanged key generation succeeded. + * @retval false DHE exchanged key generation failed. + * @retval false key_size is not large enough. + **/ +bool libspdm_dhe_compute_key(uint16_t dhe_named_group, void *context, + const uint8_t *peer_public, + size_t peer_public_size, uint8_t *key, + size_t *key_size); + +/** + * This function returns the SPDM AEAD algorithm key size. + * + * @param aead_cipher_suite SPDM aead_cipher_suite + * + * @return SPDM AEAD algorithm key size. + **/ +uint32_t libspdm_get_aead_key_size(uint16_t aead_cipher_suite); + +/** + * This function returns the SPDM AEAD algorithm iv size. + * + * @param aead_cipher_suite SPDM aead_cipher_suite + * + * @return SPDM AEAD algorithm iv size. + **/ +uint32_t libspdm_get_aead_iv_size(uint16_t aead_cipher_suite); + +/** + * This function returns the SPDM AEAD algorithm tag size. + * + * @param aead_cipher_suite SPDM aead_cipher_suite + * + * @return SPDM AEAD algorithm tag size. + **/ +uint32_t libspdm_get_aead_tag_size(uint16_t aead_cipher_suite); + +/** + * Performs AEAD authenticated encryption on a data buffer and additional authenticated data (AAD), + * based upon negotiated AEAD algorithm. + * + * @param aead_cipher_suite SPDM aead_cipher_suite + * @param key Pointer to the encryption key. + * @param key_size Size of the encryption key in bytes. + * @param iv Pointer to the IV value. + * @param iv_size Size of the IV value in bytes. + * @param a_data Pointer to the additional authenticated data (AAD). + * @param a_data_size Size of the additional authenticated data (AAD) in bytes. + * @param data_in Pointer to the input data buffer to be encrypted. + * @param data_in_size Size of the input data buffer in bytes. + * @param tag_out Pointer to a buffer that receives the authentication tag output. + * @param tag_size Size of the authentication tag in bytes. + * @param data_out Pointer to a buffer that receives the encryption output. + * @param data_out_size Size of the output data buffer in bytes. + * + * @retval true AEAD authenticated encryption succeeded. + * @retval false AEAD authenticated encryption failed. + **/ +bool libspdm_aead_encryption(const spdm_version_number_t secured_message_version, + uint16_t aead_cipher_suite, const uint8_t *key, + size_t key_size, const uint8_t *iv, + size_t iv_size, const uint8_t *a_data, + size_t a_data_size, const uint8_t *data_in, + size_t data_in_size, uint8_t *tag_out, + size_t tag_size, uint8_t *data_out, + size_t *data_out_size); + +/** + * Performs AEAD authenticated decryption on a data buffer and additional authenticated data (AAD), + * based upon negotiated AEAD algorithm. + * + * @param aead_cipher_suite SPDM aead_cipher_suite + * @param key Pointer to the encryption key. + * @param key_size Size of the encryption key in bytes. + * @param iv Pointer to the IV value. + * @param iv_size Size of the IV value in bytes. + * @param a_data Pointer to the additional authenticated data (AAD). + * @param a_data_size Size of the additional authenticated data (AAD) in bytes. + * @param data_in Pointer to the input data buffer to be decrypted. + * @param data_in_size Size of the input data buffer in bytes. + * @param tag Pointer to a buffer that contains the authentication tag. + * @param tag_size Size of the authentication tag in bytes. + * @param data_out Pointer to a buffer that receives the decryption output. + * @param data_out_size Size of the output data buffer in bytes. + * + * @retval true AEAD authenticated decryption succeeded. + * @retval false AEAD authenticated decryption failed. + **/ +bool libspdm_aead_decryption(const spdm_version_number_t secured_message_version, + uint16_t aead_cipher_suite, const uint8_t *key, + size_t key_size, const uint8_t *iv, + size_t iv_size, const uint8_t *a_data, + size_t a_data_size, const uint8_t *data_in, + size_t data_in_size, const uint8_t *tag, + size_t tag_size, uint8_t *data_out, + size_t *data_out_size); + +/** + * Generates a random byte stream of the specified size. + * + * @param spdm_context A pointer to the SPDM context. + * @param size Size of random bytes to generate. + * @param rand Pointer to buffer to receive random value. + **/ +bool libspdm_get_random_number(size_t size, uint8_t *rand); + +/** + * Certificate Check for SPDM leaf cert. + * + * @param[in] cert Pointer to the DER-encoded certificate data. + * @param[in] cert_size The size of certificate data in bytes. + * @param[in] base_asym_algo SPDM base_asym_algo + * @param[in] base_hash_algo SPDM base_hash_algo + * @param[in] is_device_cert_model If true, the cert chain is DeviceCert model. + * If false, the cert chain is AliasCert model. + * + * @retval true Success. + * @retval false Certificate is not valid. + **/ +bool libspdm_x509_certificate_check(const uint8_t *cert, size_t cert_size, + uint32_t base_asym_algo, uint32_t base_hash_algo, + bool is_device_cert_model); + +/** + * Return certificate is root cert or not. + * Certificate is considered as a root certificate if the subjectname equal issuername. + * + * @param[in] cert Pointer to the DER-encoded certificate data. + * @param[in] cert_size The size of certificate data in bytes. + * + * @retval true Certificate is self-signed. + * @retval false Certificate is not self-signed. + **/ +bool libspdm_is_root_certificate(const uint8_t *cert, size_t cert_size); + +/** + * Retrieve the SubjectAltName from SubjectAltName Bytes. + * + * @param[in] buffer Pointer to subjectAltName oct bytes. + * @param[in] len Size of buffer in bytes. + * @param[out] name_buffer Buffer to contain the retrieved certificate + * SubjectAltName. At most name_buffer_size bytes will be + * written. Maybe NULL in order to determine the size + * buffer needed. + * @param[in,out] name_buffer_size The size in bytes of the name buffer on input, + * and the size of buffer returned name on output. + * If name_buffer is NULL then the amount of space needed + * in buffer (including the final null) is returned. + * @param[out] oid OID of otherName + * @param[in,out] oid_size The buffersize for required OID + * + * @retval true Get the subjectAltName string successfully + * @retval failed Get the subjectAltName string failed + **/ +bool libspdm_get_dmtf_subject_alt_name_from_bytes( + uint8_t *buffer, const size_t len, char *name_buffer, + size_t *name_buffer_size, uint8_t *oid, + size_t *oid_size); + +/** + * Retrieve the SubjectAltName from one X.509 certificate. + * + * @param[in] cert Pointer to the DER-encoded X509 certificate. + * @param[in] cert_size Size of the X509 certificate in bytes. + * @param[out] name_buffer Buffer to contain the retrieved certificate + * SubjectAltName. At most name_buffer_size bytes will be + * written. Maybe NULL in order to determine the size + * buffer needed. + * @param[in,out] name_buffer_size The size in bytes of the name buffer on input, + * and the size of buffer returned name on output. + * If name_buffer is NULL then the amount of space needed + * in buffer (including the final null) is returned. + * @param[out] oid OID of otherName + * @param[in,out] oid_size The buffersize for required OID + * + * @retval true Get the subjectAltName string successfully + * @retval failed Get the subjectAltName string failed + **/ +bool libspdm_get_dmtf_subject_alt_name(const uint8_t *cert, const size_t cert_size, + char *name_buffer, + size_t *name_buffer_size, + uint8_t *oid, size_t *oid_size); + +/** + * This function verifies the integrity of certificate chain data without spdm_cert_chain_t header. + * + * @param cert_chain_data The certificate chain data without spdm_cert_chain_t header. + * @param cert_chain_data_size Size in bytes of the certificate chain data. + * @param base_hash_algo SPDM base_hash_algo + * @param base_asym_algo SPDM base_asym_algo + * @param is_device_cert_model If true, the cert chain is DeviceCert model. + * If false, the cert chain is AliasCert model. + * + * @retval true Certificate chain data integrity verification pass. + * @retval false Certificate chain data integrity verification fail. + **/ +bool libspdm_verify_cert_chain_data(uint8_t *cert_chain_data, size_t cert_chain_data_size, + uint32_t base_asym_algo, uint32_t base_hash_algo, + bool is_device_cert_model); + +/** + * This function verifies the integrity of certificate chain buffer including + * spdm_cert_chain_t header. + * + * @param base_hash_algo SPDM base_hash_algo + * @param base_asym_algo SPDM base_asym_algo + * @param cert_chain_buffer The certificate chain buffer including spdm_cert_chain_t header. + * @param cert_chain_buffer_size Size in bytes of the certificate chain buffer. + * @param is_device_cert_model If true, the cert chain is DeviceCert model. + * If false, the cert chain is AliasCert model. + * + * @retval true Certificate chain buffer integrity verification pass. + * @retval false Certificate chain buffer integrity verification fail. + **/ +bool libspdm_verify_certificate_chain_buffer(uint32_t base_hash_algo, uint32_t base_asym_algo, + const void *cert_chain_buffer, + size_t cert_chain_buffer_size, + bool is_device_cert_model); + +/** + * Retrieve the asymmetric public key from one DER-encoded X509 certificate, + * based upon negotiated asymmetric or requester asymmetric algorithm. + * + * + * @param base_hash_algo SPDM base_hash_algo. + * @param base_asym_alg SPDM base_asym_algo or req_base_asym_alg. + * @param cert_chain_data Certitiface chain data without spdm_cert_chain_t header. + * @param cert_chain_data_size Size in bytes of the certitiface chain data. + * @param public_key Pointer to new-generated asymmetric context which contain the + * retrieved public key component. + * + * @retval true Public key was retrieved successfully. + * @retval false Fail to retrieve public key from X509 certificate. + **/ +bool libspdm_get_leaf_cert_public_key_from_cert_chain(uint32_t base_hash_algo, + uint32_t base_asym_alg, + uint8_t *cert_chain_data, + size_t cert_chain_data_size, + void **public_key); + +/** + * Verify req info format refer to PKCS#10. + * + * @param[in] req_info Requester info to gen CSR. + * @param[in] req_info_len The len of requester info. + * + * @retval true Vaild req info, have three situations: + * 1: no req_info + * 2: good format req_info without attributes + * 3: good format req_info with good format attributes + * @retval false Invaild req info. + **/ +bool libspdm_verify_req_info(uint8_t *req_info, uint16_t req_info_len); + +#endif /* SPDM_CRYPT_LIB_H */ diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/libraries/libspdm/2.3.1/include/library/spdm_device_secret_lib.h nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/libraries/libspdm/2.3.1/include/library/spdm_device_secret_lib.h --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/libraries/libspdm/2.3.1/include/library/spdm_device_secret_lib.h 1970-01-01 00:00:00.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/libraries/libspdm/2.3.1/include/library/spdm_device_secret_lib.h 2024-03-05 22:14:13.000000000 +0000 @@ -0,0 +1,256 @@ +/** + * Copyright Notice: + * Copyright 2021-2022 DMTF. All rights reserved. + * License: BSD 3-Clause License. For full text see link: https://github.com/DMTF/libspdm/blob/main/LICENSE.md + **/ + +#ifndef SPDM_DEVICE_SECRET_LIB_H +#define SPDM_DEVICE_SECRET_LIB_H + +#include "internal/libspdm_lib_config.h" + +#include "hal/base.h" +#include "industry_standard/spdm.h" +#include "hal/library/debuglib.h" +#include "hal/library/memlib.h" +#include "hal/library/cryptlib.h" +#include "library/spdm_crypt_lib.h" +#include "library/spdm_return_status.h" + +#if LIBSPDM_ENABLE_CAPABILITY_MEAS_CAP +/** + * Collect the device measurement. + * + * libspdm will call this function to retrieve the measurements for a device. + * The "measurement_index" parameter indicates the measurement requested. + * + * @param measurement_specification Indicates the measurement specification. + * Must be a SPDM_MEASUREMENT_BLOCK_HEADER_SPECIFICATION_* value in spdm.h. + * + * @param measurement_hash_algo Indicates the measurement hash algorithm. + * Must be SPDM_ALGORITHMS_MEASUREMENT_HASH_ALGO_* value in spdm.h. + * + * @param measurement_index The index of the measurement to collect. + * + * A value of [0x0] requests only the total number of measurements to be returned + * in "measurements_count". The parameters "measurements" and + * "measurements_size" will be left unmodified. + * + * A value of [1-0xFE] requests a single measurement for that measurement index + * be returned. On success, "measurements_count" will be set to 1 and the + * "measurements" and "measurements_size" fields will be set based + * on the single measurement. An invalid measurement index will cause + * "measurements_count" to return 0. + * + * A value of [0xFF] requests all measurements be returned. + * On success, "measurements_count", "measurements", and "measurements_size" + * fields will be set with data from all measurements. + * + * @param measurements_count + * + * When "measurement_index" is zero, returns the total count of + * measurements available for the device. None of the actual measurements are + * returned however, and "measurements" and "measurements_size" are unmodified. + * + * When "measurement_index" is non-zero, returns the number of measurements + * returned in "measurements" and "measurements_size". If "measurements_index" + * is an invalid index not supported by the device, "measurements_count" will + * return 0. + * + * @param measurements + * + * A pointer to a destination buffer to store the concatenation of all device + * measurement blocks. This buffer will only be modified if + * "measurement_index" is non-zero. + * + * @param measurements_size + * + * On input, indicates the size in bytes of the destination buffer. + * On output, indicates the total size in bytes of all device measurement + * blocks in the buffer. This field should only be modified if + * "measurement_index" is non-zero. + * + * @retval RETURN_SUCCESS Successfully returned measurement_count, + * measurements, measurements_size. + * @retval RETURN_BUFFER_TOO_SMALL measurements buffer too small for measurements. + * @retval RETURN_INVALID_PARAMETER Invalid parameter passed to function. + * @retval RETURN_NOT_FOUND Unsupported measurement index. + * @retval RETURN_*** Any other RETURN_ error from base.h + * indicating the type of failure + **/ +libspdm_return_t libspdm_measurement_collection( + spdm_version_number_t spdm_version, + uint8_t measurement_specification, + uint32_t measurement_hash_algo, + uint8_t measurement_index, + uint8_t request_attribute, + uint8_t *content_changed, + uint8_t *measurements_count, + void *measurements, + size_t *measurements_size); + +/** + * This function calculates the measurement summary hash. + * + * @param spdm_version The spdm version. + * @param base_hash_algo The hash algo to use on summary. + * @param measurement_specification Indicates the measurement specification. + * It must align with measurement_specification + * (SPDM_MEASUREMENT_BLOCK_HEADER_SPECIFICATION_*) + * @param measurement_hash_algo Indicates the measurement hash algorithm. + * It must align with measurement_hash_alg + * (SPDM_ALGORITHMS_MEASUREMENT_HASH_ALGO_*) + * + * @param measurement_summary_hash_type The type of the measurement summary hash. + * @param measurement_summary_hash The buffer to store the measurement summary hash. + * @param measurement_summary_hash_size The size in bytes of the buffer. + * + * @retval true measurement summary hash is generated or skipped. + * @retval false measurement summary hash is not generated. + **/ +bool libspdm_generate_measurement_summary_hash( + spdm_version_number_t spdm_version, + uint32_t base_hash_algo, + uint8_t measurement_specification, + uint32_t measurement_hash_algo, + uint8_t measurement_summary_hash_type, + uint8_t *measurement_summary_hash, + size_t *measurement_summary_hash_size); +#endif /* LIBSPDM_ENABLE_CAPABILITY_MEAS_CAP */ + +#if LIBSPDM_ENABLE_CAPABILITY_MUT_AUTH_CAP +/** + * Sign an SPDM message data. + * + * @param req_base_asym_alg Indicates the signing algorithm. + * @param base_hash_algo Indicates the hash algorithm. + * @param is_data_hash Indicate the message type. true: raw message before hash, false: message hash. + * @param message A pointer to a message to be signed. + * @param message_size The size in bytes of the message to be signed. + * @param signature A pointer to a destination buffer to store the signature. + * @param sig_size On input, indicates the size in bytes of the destination buffer to store the signature. + * On output, indicates the size in bytes of the signature in the buffer. + * + * @retval true signing success. + * @retval false signing fail. + **/ +bool libspdm_requester_data_sign( + spdm_version_number_t spdm_version, + uint8_t op_code, + uint16_t req_base_asym_alg, + uint32_t base_hash_algo, bool is_data_hash, + const uint8_t *message, size_t message_size, + uint8_t *signature, size_t *sig_size); +#endif /* LIBSPDM_ENABLE_CAPABILITY_MUT_AUTH_CAP */ + +/** + * Sign an SPDM message data. + * + * @param base_asym_algo Indicates the signing algorithm. + * @param base_hash_algo Indicates the hash algorithm. + * @param is_data_hash Indicate the message type. true: raw message before hash, false: message hash. + * @param message A pointer to a message to be signed. + * @param message_size The size in bytes of the message to be signed. + * @param signature A pointer to a destination buffer to store the signature. + * @param sig_size On input, indicates the size in bytes of the destination buffer to store the signature. + * On output, indicates the size in bytes of the signature in the buffer. + * + * @retval true signing success. + * @retval false signing fail. + **/ +bool libspdm_responder_data_sign( + spdm_version_number_t spdm_version, + uint8_t op_code, + uint32_t base_asym_algo, + uint32_t base_hash_algo, bool is_data_hash, + const uint8_t *message, size_t message_size, + uint8_t *signature, size_t *sig_size); + +#if LIBSPDM_ENABLE_CAPABILITY_PSK_EX_CAP +/** + * Derive HMAC-based Expand key Derivation Function (HKDF) Expand, based upon the negotiated HKDF algorithm. + * + * @param base_hash_algo Indicates the hash algorithm. + * @param psk_hint Pointer to the user-supplied PSK Hint. + * @param psk_hint_size PSK Hint size in bytes. + * @param info Pointer to the application specific info. + * @param info_size info size in bytes. + * @param out Pointer to buffer to receive hkdf value. + * @param out_size size of hkdf bytes to generate. + * + * @retval true Hkdf generated successfully. + * @retval false Hkdf generation failed. + **/ +bool libspdm_psk_handshake_secret_hkdf_expand( + spdm_version_number_t spdm_version, + uint32_t base_hash_algo, const uint8_t *psk_hint, + size_t psk_hint_size, const uint8_t *info, + size_t info_size, uint8_t *out, size_t out_size); + +/** + * Derive HMAC-based Expand key Derivation Function (HKDF) Expand, based upon the negotiated HKDF algorithm. + * + * @param base_hash_algo Indicates the hash algorithm. + * @param psk_hint Pointer to the user-supplied PSK Hint. + * @param psk_hint_size PSK Hint size in bytes. + * @param info Pointer to the application specific info. + * @param info_size info size in bytes. + * @param out Pointer to buffer to receive hkdf value. + * @param out_size size of hkdf bytes to generate. + * + * @retval true Hkdf generated successfully. + * @retval false Hkdf generation failed. + **/ +bool libspdm_psk_master_secret_hkdf_expand( + spdm_version_number_t spdm_version, + uint32_t base_hash_algo, + const uint8_t *psk_hint, + size_t psk_hint_size, + const uint8_t *info, + size_t info_size, uint8_t *out, + size_t out_size); +#endif /* LIBSPDM_ENABLE_CAPABILITY_PSK_EX_CAP */ + +#if LIBSPDM_ENABLE_CAPABILITY_SET_CERTIFICATE_CAP +/** + * This function sends SET_CERTIFICATE + * to set certificate from the device. + * + * + * @param[in] slot_id The number of slot for the certificate chain. + * @param[in] cert_chain The pointer for the certificate chain to set. + * @param[in] cert_chain_size The size of the certificate chain to set. + * + * @retval true Set certificate to NV successfully. + * @retval false Set certificate to NV unsuccessfully. + **/ +bool libspdm_write_certificate_to_nvm(uint8_t slot_id, const void * cert_chain, + size_t cert_chain_size); +#endif /* LIBSPDM_ENABLE_CAPABILITY_SET_CERTIFICATE_CAP */ + +#if LIBSPDM_ENABLE_CAPABILITY_GET_CSR_CAP +/** + * Gen CSR + * + * @param[in] base_hash_algo hash algo for sign + * @param[in] base_asym_algo asym public key to set + * @param[in] need_reset device need reset for gen csr + * + * @param[in] requester_info requester info to gen CSR + * @param[in] requester_info_length The len of requester info + * + * @param[in] csr_len For input, csr_len is the size of store CSR buffer. + * For output, csr_len is CSR len for DER format + * @param[in] csr_pointer For input, csr_pointer is buffer address to store CSR. + * For output, csr_pointer is address for stored CSR. + * The csr_pointer address will be changed. + * + * @retval true Success. + * @retval false Failed to gen CSR. + **/ +bool libspdm_gen_csr(uint32_t base_hash_algo, uint32_t base_asym_algo, bool *need_reset, + uint8_t *requester_info, size_t requester_info_length, + size_t *csr_len, uint8_t **csr_pointer); +#endif /* LIBSPDM_ENABLE_CAPABILITY_GET_CSR_CAP */ + +#endif /* SPDM_DEVICE_SECRET_LIB_H */ diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/libraries/libspdm/2.3.1/include/library/spdm_lib_config.h nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/libraries/libspdm/2.3.1/include/library/spdm_lib_config.h --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/libraries/libspdm/2.3.1/include/library/spdm_lib_config.h 1970-01-01 00:00:00.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/libraries/libspdm/2.3.1/include/library/spdm_lib_config.h 2024-03-05 22:14:13.000000000 +0000 @@ -0,0 +1,415 @@ +/** + * Copyright Notice: + * Copyright 2021-2022 DMTF. All rights reserved. + * License: BSD 3-Clause License. For full text see link: https://github.com/DMTF/libspdm/blob/main/LICENSE.md + **/ + +#ifndef SPDM_LIB_CONFIG_H +#define SPDM_LIB_CONFIG_H + +/* Enables assertions and debug printing. When `LIBSPDM_DEBUG_ENABLE` is defined it overrides or + * sets the values of `LIBSPDM_DEBUG_PRINT_ENABLE`, `LIBSPDM_DEBUG_ASSERT_ENABLE`, and + * `LIBSPDM_BLOCK_ENABLE` to the value of `LIBSPDM_DEBUG_ENABLE`. + * + * Note that if this file is used with CMake and `DTARGET=Release` is defined, then all debugging + * is disabled. + */ +#ifndef LIBSPDM_DEBUG_ENABLE +#define LIBSPDM_DEBUG_ENABLE 1 +#endif + +/* The SPDM specification allows a Responder to return up to 256 version entries in the `VERSION` + * response to the Requester, including duplicate entries. For a Requester this value specifies the + * maximum number of entries that libspdm will tolerate in a `VERSION` response before returning an + * error. A similiar macro, `SPDM_MAX_VERSION_COUNT`, exists for the Responder. However this macro + * is not meant to be configured by the Integrator. + */ +#ifndef LIBSPDM_MAX_VERSION_COUNT +#define LIBSPDM_MAX_VERSION_COUNT 5 +#endif + +/* This value specifies the maximum size, in bytes, of the `PSK_EXCHANGE.RequesterContext` and, + * if supported by the Responder, `PSK_EXCHANGE_RSP.ResponderContext` fields. The fields are + * typically random or monotonically increasing numbers. + */ +#ifndef LIBSPDM_PSK_CONTEXT_LENGTH +#define LIBSPDM_PSK_CONTEXT_LENGTH LIBSPDM_MAX_HASH_SIZE +#endif +/* This value specifies the maximum size, in bytes, of the `PSK_EXCHANGE.PSKHint` field.*/ +#ifndef LIBSPDM_PSK_MAX_HINT_LENGTH +#define LIBSPDM_PSK_MAX_HINT_LENGTH 16 +#endif + +/* libspdm allows an Integrator to specify multiple root certificates as trust anchors when + * verifying certificate chains from an endpoint. This value specifies the maximum number of root + * certificates that libspdm can support. + */ +#ifndef LIBSPDM_MAX_ROOT_CERT_SUPPORT +#define LIBSPDM_MAX_ROOT_CERT_SUPPORT 10 +#endif + +/* If the Responder supports it a Requester is allowed to establish multiple secure sessions with + * the Responder. This value specifies the maximum number of sessions libspdm can support. + */ +#ifndef LIBSPDM_MAX_SESSION_COUNT +#define LIBSPDM_MAX_SESSION_COUNT 4 +#endif +/* This value specifies the maximum size, in bytes, of a certificate chain that can be stored in a + * libspdm context. + */ +#ifndef LIBSPDM_MAX_CERT_CHAIN_SIZE +#define LIBSPDM_MAX_CERT_CHAIN_SIZE 0x1000 +#endif +#ifndef LIBSPDM_MAX_MEASUREMENT_RECORD_SIZE +#define LIBSPDM_MAX_MEASUREMENT_RECORD_SIZE 0x1000 +#endif +/* Partial certificates can be retrieved from a Requester or Responder and through multiple messages + * the complete certificate chain can be constructed. This value specifies the maximum size, + * in bytes, of a partial certificate that can be sent or received. + */ +#ifndef LIBSPDM_MAX_CERT_CHAIN_BLOCK_LEN +#define LIBSPDM_MAX_CERT_CHAIN_BLOCK_LEN 1024 +#endif + +#ifndef LIBSPDM_MAX_MESSAGE_BUFFER_SIZE +#define LIBSPDM_MAX_MESSAGE_BUFFER_SIZE 0x1200 +#endif +#ifndef LIBSPDM_MAX_MESSAGE_SMALL_BUFFER_SIZE +#define LIBSPDM_MAX_MESSAGE_SMALL_BUFFER_SIZE 0x100 /* to hold message_a before negotiate*/ +#endif +#ifndef LIBSPDM_MAX_MESSAGE_MEDIUM_BUFFER_SIZE +#define LIBSPDM_MAX_MESSAGE_MEDIUM_BUFFER_SIZE 0x300 /* to hold message_k before finished_key is ready*/ +#endif + +/* If the Responder replies with a Busy `ERROR` response to a request then the Requester is free to + * retry sending the request. This value specifies the maximum number of times libspdm will retry + * sending the request before returning an error. If its value is 0 then libspdm will not send any + * retry requests. + */ +#ifndef LIBSPDM_MAX_REQUEST_RETRY_TIMES +#define LIBSPDM_MAX_REQUEST_RETRY_TIMES 3 +#endif +#ifndef LIBSPDM_MAX_SESSION_STATE_CALLBACK_NUM +#define LIBSPDM_MAX_SESSION_STATE_CALLBACK_NUM 4 +#endif +#ifndef LIBSPDM_MAX_CONNECTION_STATE_CALLBACK_NUM +#define LIBSPDM_MAX_CONNECTION_STATE_CALLBACK_NUM 4 +#endif +#ifndef LIBSPDM_MAX_KEY_UPDATE_CALLBACK_NUM +#define LIBSPDM_MAX_KEY_UPDATE_CALLBACK_NUM 4 +#endif + +#ifndef LIBSPDM_MAX_CSR_SIZE +#define LIBSPDM_MAX_CSR_SIZE 0x1000 +#endif + +/* To ensure integrity in communication between the Requester and the Responder libspdm calculates + * cryptographic digests and signatures over multiple requests and responses. This value specifies + * whether libspdm will use a running calculation over the transcript, where requests and responses + * are discarded as they are cryptographically consumed, or whether libspdm will buffer the entire + * transcript before calculating the digest or signature. + */ +#ifndef LIBSPDM_RECORD_TRANSCRIPT_DATA_SUPPORT +#define LIBSPDM_RECORD_TRANSCRIPT_DATA_SUPPORT 0 +#endif + + +/* Cryptography Configuration + * In each category, at least one should be selected. + * NOTE: Not all combination can be supported. E.g. Don't mix NIST algo with SMx.*/ + +#ifndef LIBSPDM_RSA_SSA_SUPPORT +#define LIBSPDM_RSA_SSA_SUPPORT 1 +#endif +#ifndef LIBSPDM_RSA_PSS_SUPPORT +#define LIBSPDM_RSA_PSS_SUPPORT 1 +#endif +#ifndef LIBSPDM_ECDSA_SUPPORT +#define LIBSPDM_ECDSA_SUPPORT 1 +#endif +#ifndef LIBSPDM_SM2_DSA_SUPPORT +#define LIBSPDM_SM2_DSA_SUPPORT 1 +#endif +#ifndef LIBSPDM_EDDSA_ED25519_SUPPORT +#define LIBSPDM_EDDSA_ED25519_SUPPORT 1 +#endif +#ifndef LIBSPDM_EDDSA_ED448_SUPPORT +#define LIBSPDM_EDDSA_ED448_SUPPORT 1 +#endif + +#ifndef LIBSPDM_FFDHE_SUPPORT +#define LIBSPDM_FFDHE_SUPPORT 1 +#endif +#ifndef LIBSPDM_ECDHE_SUPPORT +#define LIBSPDM_ECDHE_SUPPORT 1 +#endif +#ifndef LIBSPDM_SM2_KEY_EXCHANGE_SUPPORT +#define LIBSPDM_SM2_KEY_EXCHANGE_SUPPORT 1 +#endif + +#ifndef LIBSPDM_AEAD_GCM_SUPPORT +#define LIBSPDM_AEAD_GCM_SUPPORT 1 +#endif +#ifndef LIBSPDM_AEAD_CHACHA20_POLY1305_SUPPORT +#define LIBSPDM_AEAD_CHACHA20_POLY1305_SUPPORT 1 +#endif +#ifndef LIBSPDM_AEAD_SM4_SUPPORT +#define LIBSPDM_AEAD_SM4_SUPPORT 1 +#endif + +#ifndef LIBSPDM_SHA256_SUPPORT +#define LIBSPDM_SHA256_SUPPORT 1 +#endif +#ifndef LIBSPDM_SHA384_SUPPORT +#define LIBSPDM_SHA384_SUPPORT 1 +#endif +#ifndef LIBSPDM_SHA512_SUPPORT +#define LIBSPDM_SHA512_SUPPORT 1 +#endif +#ifndef LIBSPDM_SHA3_256_SUPPORT +#define LIBSPDM_SHA3_256_SUPPORT 1 +#endif +#ifndef LIBSPDM_SHA3_384_SUPPORT +#define LIBSPDM_SHA3_384_SUPPORT 1 +#endif +#ifndef LIBSPDM_SHA3_512_SUPPORT +#define LIBSPDM_SHA3_512_SUPPORT 1 +#endif +#ifndef LIBSPDM_SM3_256_SUPPORT +#define LIBSPDM_SM3_256_SUPPORT 1 +#endif + +/* Code space optimization for Optional request/response messages.*/ + +/* Consumers of libspdm may wish to not fully implement all of the optional + * SPDM request/response messages. Therefore we have provided these + * SPDM_ENABLE_CAPABILITY_***_CAP compile time switches as an optimization + * disable the code (#if 0) related to said optional capability, thereby + * reducing the code space used in the image.*/ + +/* A single switch may enable/disable a single capability or group of related + * capabilities.*/ + +/* LIBSPDM_ENABLE_CAPABILITY_CERT_CAP - Enable/Disable single CERT capability. + * LIBSPDM_ENABLE_CAPABILITY_CHAL_CAP - Enable/Disable single CHAL capability. + * LIBSPDM_ENABLE_CAPABILTIY_MEAS_CAP - Enable/Disables multiple MEAS capabilities: + * (MEAS_CAP_NO_SIG, MEAS_CAP_SIG, MEAS_FRESH_CAP)*/ + +/* LIBSPDM_ENABLE_CAPABILITY_KEY_EX_CAP - Enable/Disable single Key Exchange capability. + * LIBSPDM_ENABLE_CAPABILITY_PSK_EX_CAP - Enable/Disable PSK_EX and PSK_FINISH.*/ + +/* LIBSPDM_ENABLE_CAPABILITY_MUT_AUTH_CAP - Enable/Disable mutual authentication. +* LIBSPDM_ENABLE_CAPABILITY_ENCAP_CAP - Enable/Disable encapsulated message.*/ + +/* LIBSPDM_ENABLE_CAPABILITY_GET_CSR_CAP - Enable/Disable get csr capability. + * LIBSPDM_ENABLE_CAPABILITY_SET_CERTIFICATE_CAP - Enable/Disable set certificate capability. */ + +#ifndef LIBSPDM_ENABLE_CAPABILITY_CERT_CAP +#define LIBSPDM_ENABLE_CAPABILITY_CERT_CAP 1 +#endif + +#ifndef LIBSPDM_ENABLE_CAPABILITY_CHAL_CAP +#define LIBSPDM_ENABLE_CAPABILITY_CHAL_CAP 1 +#endif + +#ifndef LIBSPDM_ENABLE_CAPABILITY_MEAS_CAP +#define LIBSPDM_ENABLE_CAPABILITY_MEAS_CAP 1 +#endif + +#ifndef LIBSPDM_ENABLE_CAPABILITY_KEY_EX_CAP +#define LIBSPDM_ENABLE_CAPABILITY_KEY_EX_CAP 1 +#endif + +#ifndef LIBSPDM_ENABLE_CAPABILITY_PSK_EX_CAP +#define LIBSPDM_ENABLE_CAPABILITY_PSK_EX_CAP 1 +#endif + +#ifndef LIBSPDM_ENABLE_CAPABILITY_HBEAT_CAP +#define LIBSPDM_ENABLE_CAPABILITY_HBEAT_CAP 1 +#endif + +#ifndef LIBSPDM_ENABLE_CAPABILITY_MUT_AUTH_CAP +#define LIBSPDM_ENABLE_CAPABILITY_MUT_AUTH_CAP 1 +#endif + +#ifndef LIBSPDM_ENABLE_CAPABILITY_ENCAP_CAP +#define LIBSPDM_ENABLE_CAPABILITY_ENCAP_CAP 1 +#endif + +#ifndef LIBSPDM_ENABLE_CAPABILITY_GET_CSR_CAP +#define LIBSPDM_ENABLE_CAPABILITY_GET_CSR_CAP 1 +#endif + +#ifndef LIBSPDM_ENABLE_CAPABILITY_SET_CERTIFICATE_CAP +#define LIBSPDM_ENABLE_CAPABILITY_SET_CERTIFICATE_CAP 1 +#endif + +#ifndef LIBSPDM_ENABLE_CAPABILITY_CHUNK_CAP +#define LIBSPDM_ENABLE_CAPABILITY_CHUNK_CAP 1 +#endif + +/* + * MinDataTransferSize = 42 + * + * H = HashLen = HmacLen = [32, 64] + * S = SigLen = [64, 512] + * D = ExchangeDataLen = [64, 512] + * R = RequesterContextLen >= 32 + * R = ResponderContextLen >= 0 + * O = OpaqueDataLen <= 1024 + * + * Max Chunk No = 1, if (message size <= 42) + * Max Chunk No = [(message size + 4) / 30] roundup, if (message size > 42) + * + * +==========================+==========================================+=========+ + * | Command | Size |MaxChunk | + * +==========================+==========================================+=========+ + * | GET_VERSION | 4 | 1 | + * | VERSION {1.0, 1.1, 1.2} | 6 + 2 * 3 = 12 | 1 | + * +--------------------------+------------------------------------------+---------+ + * | GET_CAPABILITIES 1.2 | 20 | 1 | + * | CAPABILITIES 1.2 | 20 | 1 | + * +--------------------------+------------------------------------------+---------+ + * | ERROR | 4 | 1 | + * | ERROR(ResponseTooLarge) | 4 + 4 = 8 | 1 | + * | ERROR(LargeResponse) | 4 + 1 = 5 | 1 | + * | ERROR(ResponseNotReady) | 4 + 4 = 8 | 1 | + * +--------------------------+------------------------------------------+---------+ + * | CHUNK_SEND header | 12 + L0 (0 or 4) | 1 | + * | CHUNK_RESPONSE header | 12 + L0 (0 or 4) | 1 | + * +==========================+==========================================+=========+ + * | NEGOTIATE_ALGORITHMS 1.2 | 32 + 4 * 4 = 48 | 2 | + * | ALGORITHMS 1.2 | 36 + 4 * 4 = 52 | 2 | + * +--------------------------+------------------------------------------+---------+ + * | GET_DIGESTS 1.2 | 4 | 1 | + * | DIGESTS 1.2 | 4 + H * SlotNum = [36, 516] | [1, 18] | + * +--------------------------+------------------------------------------+---------+ + * | GET_CERTIFICATE 1.2 | 8 | 1 | + * | CERTIFICATE 1.2 | 8 + PortionLen | [1, ] | + * +--------------------------+------------------------------------------+---------+ + * | CHALLENGE 1.2 | 40 | 1 | + * | CHALLENGE_AUTH 1.2 | 38 + H * 2 + S [+ O] = [166, 678] | [6, 23] | + * +--------------------------+------------------------------------------+---------+ + * | GET_MEASUREMENTS 1.2 | 5 + Nounce (0 or 32) | 1 | + * | MEASUREMENTS 1.2 | 42 + MeasRecLen (+ S) [+ O] = [106, 554] | [4, 19] | + * +--------------------------+------------------------------------------+---------+ + * | KEY_EXCHANGE 1.2 | 42 + D [+ O] = [106, 554] | [4, 19] | + * | KEY_EXCHANGE_RSP 1.2 | 42 + D + H + S (+ H) [+ O] = [234, 1194] | [8, 40] | + * +--------------------------+------------------------------------------+---------+ + * | FINISH 1.2 | 4 (+ S) + H = [100, 580] | [4, 20] | + * | FINISH_RSP 1.2 | 4 (+ H) = [36, 69] | [1, 3] | + * +--------------------------+------------------------------------------+---------+ + * | PSK_EXCHANGE 1.2 | 12 [+ PSKHint] + R [+ O] = 44 | 2 | + * | PSK_EXCHANGE_RSP 1.2 | 12 + R + H (+ H) [+ O] = [108, 172] | [4, 6] | + * +--------------------------+------------------------------------------+---------+ + * | PSK_FINISH 1.2 | 4 + H = [36, 68] | [1, 3] | + * | PSK_FINISH_RSP 1.2 | 4 | 1 | + * +--------------------------+------------------------------------------+---------+ + * | GET_CSR 1.2 | 8 + RequesterInfoLen [+ O] | [1, ] | + * | CSR 1.2 | 8 + CSRLength | [1, ] | + * +--------------------------+------------------------------------------+---------+ + * | SET_CERTIFICATE 1.2 | 4 + CertChainLen | [1, ] | + * | SET_CERTIFICATE_RSP 1.2 | 4 | 1 | + * +==========================+==========================================+=========+ + */ + +/* Maximum size of a large SPDM message. + * If chunk is unsupported, it must be same as LIBSPDM_DATA_TRANSFER_SIZE. + * If chunk is supported, it must be larger than LIBSPDM_DATA_TRANSFER_SIZE. + * It matches MaxSPDMmsgSize in SPDM specification. */ +#ifndef LIBSPDM_MAX_SPDM_MSG_SIZE +#define LIBSPDM_MAX_SPDM_MSG_SIZE LIBSPDM_MAX_MESSAGE_BUFFER_SIZE +#endif + +/* Maximum size of a single SPDM message. + * It matches DataTransferSize in SPDM specification. */ +#ifndef LIBSPDM_DATA_TRANSFER_SIZE +#define LIBSPDM_DATA_TRANSFER_SIZE LIBSPDM_MAX_MESSAGE_BUFFER_SIZE +#endif + +/* Required sender/receive buffer in device io. + * NOTE: This is transport specific. Below configuration is just an example. + * +-------+--------+---------------------------+------+--+------+---+--------+-----+ + * | TYPE |TransHdr| EncryptionHeader |AppHdr| |Random|MAC|AlignPad|FINAL| + * | | |SessionId|SeqNum|Len|AppLen| | | | | | | + * +-------+--------+---------------------------+------+ +------+---+--------+-----+ + * | MCTP | 1 | 4 | 2 | 2 | 2 | 1 | | 32 | 12| 0 | 56 | + * |PCI_DOE| 8 | 4 | 0 | 2 | 2 | 0 | | 0 | 12| 3 | 31 | + * +-------+--------+---------------------------+------+--+------+---+--------+-----+ + */ +#ifndef LIBSPDM_TRANSPORT_ADDITIONAL_SIZE +#define LIBSPDM_TRANSPORT_ADDITIONAL_SIZE 64 +#endif +#ifndef LIBSPDM_SENDER_RECEIVE_BUFFER_SIZE +#define LIBSPDM_SENDER_RECEIVE_BUFFER_SIZE (LIBSPDM_DATA_TRANSFER_SIZE + \ + LIBSPDM_TRANSPORT_ADDITIONAL_SIZE) +#endif + + +/* Required scratch buffer size for libspdm internal usage. + * It may be used to hold the encrypted/decrypted message and/or last sent/received message. + * It may be used to hold the large request/response and intermediate send/receive buffer + * in case of chunking. + * + * If chunking is not supported, it may be just LIBSPDM_SENDER_RECEIVE_BUFFER_SIZE. + * If chunking is supported, it should be at least below. + * + * +---------------+--------------+--------------------------+------------------------------+ + * |SECURE_MESSAGE |LARGE_MESSAGE | SENDER_RECEIVER | LARGE_SENDER_RECEIVER | + * +---------------+--------------+--------------------------+------------------------------+ + * |<-Secure msg ->|<-Large msg ->|<-Snd/Rcv buf for chunk ->|<-Snd/Rcv buf for large msg ->| + * + * The value is NOT configurable. + * The value MAY be changed in different libspdm version. + * It is exposed here, just in case the libspdm consumer wants to configure the setting at build time. + */ +#if LIBSPDM_ENABLE_CAPABILITY_CHUNK_CAP + +/* first section */ +#define LIBSPDM_SCRATCH_BUFFER_SECURE_MESSAGE_OFFSET 0 + +#define LIBSPDM_SCRATCH_BUFFER_SECURE_MESSAGE_CAPACITY (LIBSPDM_MAX_SPDM_MSG_SIZE) + +/* second section */ +#define LIBSPDM_SCRATCH_BUFFER_LARGE_MESSAGE_OFFSET (LIBSPDM_SCRATCH_BUFFER_SECURE_MESSAGE_CAPACITY) + +#define LIBSPDM_SCRATCH_BUFFER_LARGE_MESSAGE_CAPACITY (LIBSPDM_MAX_SPDM_MSG_SIZE) + +/* third section */ +#define LIBSPDM_SCRATCH_BUFFER_SENDER_RECEIVER_OFFSET \ + (LIBSPDM_SCRATCH_BUFFER_SECURE_MESSAGE_CAPACITY + \ + LIBSPDM_SCRATCH_BUFFER_LARGE_MESSAGE_CAPACITY) + +#define LIBSPDM_SCRATCH_BUFFER_SENDER_RECEIVER_CAPACITY (LIBSPDM_MAX_SPDM_MSG_SIZE) + +/* fourth section */ +#define LIBSPDM_SCRATCH_BUFFER_LARGE_SENDER_RECEIVER_OFFSET \ + (LIBSPDM_SCRATCH_BUFFER_SECURE_MESSAGE_CAPACITY + \ + LIBSPDM_SCRATCH_BUFFER_LARGE_MESSAGE_CAPACITY + \ + LIBSPDM_SCRATCH_BUFFER_SENDER_RECEIVER_CAPACITY) + +#define LIBSPDM_SCRATCH_BUFFER_LARGE_SENDER_RECEIVER_CAPACITY (LIBSPDM_MAX_SPDM_MSG_SIZE) + +#define LIBSPDM_SCRATCH_BUFFER_SIZE (LIBSPDM_SCRATCH_BUFFER_SECURE_MESSAGE_CAPACITY + \ + LIBSPDM_SCRATCH_BUFFER_LARGE_MESSAGE_CAPACITY + \ + LIBSPDM_SCRATCH_BUFFER_SENDER_RECEIVER_CAPACITY + \ + LIBSPDM_SCRATCH_BUFFER_LARGE_SENDER_RECEIVER_CAPACITY \ + ) + +#else +#define LIBSPDM_SCRATCH_BUFFER_SIZE (LIBSPDM_SENDER_RECEIVE_BUFFER_SIZE) +#endif + +/* Enable message logging. + * See https://github.com/DMTF/libspdm/blob/main/doc/user_guide.md#message-logging + * for more information */ +#ifndef LIBSPDM_ENABLE_MSG_LOG +#define LIBSPDM_ENABLE_MSG_LOG 1 +#endif + +/* Enable macro checking during compilation. */ +#ifndef LIBSPDM_CHECK_MACRO +#define LIBSPDM_CHECK_MACRO 0 +#endif + +#endif /* SPDM_LIB_CONFIG_H */ diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/libraries/libspdm/2.3.1/include/library/spdm_requester_lib.h nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/libraries/libspdm/2.3.1/include/library/spdm_requester_lib.h --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/libraries/libspdm/2.3.1/include/library/spdm_requester_lib.h 1970-01-01 00:00:00.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/libraries/libspdm/2.3.1/include/library/spdm_requester_lib.h 2024-03-05 22:14:14.000000000 +0000 @@ -0,0 +1,804 @@ +/** + * Copyright Notice: + * Copyright 2021-2022 DMTF. All rights reserved. + * License: BSD 3-Clause License. For full text see link: https://github.com/DMTF/libspdm/blob/main/LICENSE.md + **/ + +#ifndef SPDM_REQUESTER_LIB_H +#define SPDM_REQUESTER_LIB_H + +#include "library/spdm_common_lib.h" + +/** + * Send an SPDM or an APP request to a device. + * + * @param spdm_context The SPDM context for the device. + * @param session_id Indicate if the request is a secured message. + * If session_id is NULL, it is a normal message. + * If session_id is NOT NULL, it is a secured message. + * @param is_app_message Indicates if it is an APP message or SPDM message. + * @param request_size Size in bytes of the request data buffer. + * @param request A pointer to a destination buffer to store the request. + * The caller is responsible for having either implicit or explicit ownership + * of the buffer. + * For normal message, requester pointer point to transport_message + transport header size + * For secured message, requester pointer will point to the scratch buffer + transport header size in spdm_context. + * + * @retval RETURN_SUCCESS The SPDM request is sent successfully. + * @retval RETURN_DEVICE_ERROR A device error occurs when the SPDM request is sent to the device. + **/ +libspdm_return_t libspdm_send_request(void *spdm_context, const uint32_t *session_id, + bool is_app_message, + size_t request_size, void *request); + +/** + * Receive an SPDM or an APP response from a device. + * + * @param spdm_context The SPDM context for the device. + * @param session_id Indicate if the response is a secured message. + * If session_id is NULL, it is a normal message. + * If session_id is NOT NULL, it is a secured message. + * @param is_app_message Indicates if it is an APP message or SPDM message. + * @param response_size Size in bytes of the response data buffer. + * @param response A pointer to a destination buffer to store the response. + * The caller is responsible for having either implicit or explicit + * ownership of the buffer. + * For normal message, response pointer still point to original transport_message. + * For secured message, response pointer will point to the scratch buffer in spdm_context. + * + * @retval RETURN_SUCCESS The SPDM response is received successfully. + * @retval RETURN_DEVICE_ERROR A device error occurs when the SPDM response is received from the device. + **/ +libspdm_return_t libspdm_receive_response(void *spdm_context, + const uint32_t *session_id, + bool is_app_message, + size_t *response_size, + void **response); + +/** + * This function sends GET_VERSION, GET_CAPABILITIES, NEGOTIATE_ALGORITHMS + * to initialize the connection with SPDM responder. + * + * Before this function, the requester configuration data can be set via libspdm_set_data. + * After this function, the negotiated configuration data can be got via libspdm_get_data. + * + * @param spdm_context A pointer to the SPDM context. + * @param get_version_only If the requester sends GET_VERSION only or not. + * + * @retval RETURN_SUCCESS The connection is initialized successfully. + * @retval RETURN_DEVICE_ERROR A device error occurs when communicates with the device. + **/ +libspdm_return_t libspdm_init_connection(void *spdm_context, bool get_version_only); + +/** + * This function sends GET_DIGEST to get all digest of the certificate chains from device. + * + * If the peer certificate chain is deployed, this function also verifies the digest with the + * certificate chain. + * + * TotalDigestSize = sizeof(digest) * count in slot_mask + * + * @param spdm_context A pointer to the SPDM context. + * @param slot_mask The slots which deploy the CertificateChain. + * @param total_digest_buffer A pointer to a destination buffer to store the digest buffer. + * + * @retval RETURN_SUCCESS The digests are got successfully. + * @retval RETURN_DEVICE_ERROR A device error occurs when communicates with the device. + * @retval RETURN_SECURITY_VIOLATION Any verification fails. + **/ +libspdm_return_t libspdm_get_digest(void *spdm_context, uint8_t *slot_mask, + void *total_digest_buffer); + +/** + * This function sends GET_DIGESTS and receives DIGESTS. It may retry GET_DIGESTS multiple times + * if the Responder replies with a Busy error. + * + * If the peer certificate chain is deployed, this function also verifies the digest with the + * certificate chain. + * + * TotalDigestSize = sizeof(digest) * count in slot_mask + * + * @param context A pointer to the SPDM context. + * @param session_id Indicates if it is a secured message protected via SPDM session. + * If session_id is NULL, it is a normal message. + * If session_id is not NULL, it is a secured message. + * @param slot_mask Bitmask of the slots that contain certificates. + * @param total_digest_buffer A pointer to a destination buffer to store the digests. + * + * @retval LIBSPDM_STATUS_SUCCESS + * GET_DIGETS was sent and DIGESTS was received. + * @retval LIBSPDM_STATUS_INVALID_STATE_LOCAL + * Cannot send GET_DIGESTS due to Requester's state. + * @retval LIBSPDM_STATUS_UNSUPPORTED_CAP + * Cannot send GET_DIGESTS because the Requester's and/or Responder's CERT_CAP = 0. + * @retval LIBSPDM_STATUS_INVALID_MSG_SIZE + * The size of the DIGESTS response is invalid. + * @retval LIBSPDM_STATUS_INVALID_MSG_FIELD + * The DIGESTS response contains one or more invalid fields. + * @retval LIBSPDM_STATUS_ERROR_PEER + * The Responder returned an unexpected error. + * @retval LIBSPDM_STATUS_BUSY_PEER + * The Responder continually returned Busy error messages. + * @retval LIBSPDM_STATUS_RESYNCH_PEER + * The Responder returned a RequestResynch error message. + * @retval LIBSPDM_STATUS_BUFFER_FULL + * The buffer used to store transcripts is exhausted. + * @retval LIBSPDM_STATUS_VERIF_FAIL + * The digest of the stored certificate chain does not match the digest returned by + * the Responder. + * Note: This return value may be removed in the future. + **/ +libspdm_return_t libspdm_get_digest_in_session(void *context, const uint32_t *session_id, + uint8_t *slot_mask, void *total_digest_buffer); + +/** + * This function sends GET_CERTIFICATE to get certificate chain in one slot from device. + * + * This function verify the integrity of the certificate chain. + * root_hash -> Root certificate -> Intermediate certificate -> Leaf certificate. + * + * If the peer root certificate hash is deployed, + * this function also verifies the digest with the root hash in the certificate chain. + * + * @param spdm_context A pointer to the SPDM context. + * @param slot_id The number of slot for the certificate chain. + * @param cert_chain_size On input, indicate the size in bytes of the destination buffer to store the digest buffer. + * On output, indicate the size in bytes of the certificate chain. + * @param cert_chain A pointer to a destination buffer to store the certificate chain. + * + * @retval RETURN_SUCCESS The certificate chain is got successfully. + * @retval RETURN_DEVICE_ERROR A device error occurs when communicates with the device. + * @retval RETURN_SECURITY_VIOLATION Any verification fails. + **/ +libspdm_return_t libspdm_get_certificate(void *spdm_context, uint8_t slot_id, + size_t *cert_chain_size, + void *cert_chain); + +/** + * This function sends GET_CERTIFICATE to get certificate chain in one slot from device. + * + * This function verify the integrity of the certificate chain. + * root_hash -> Root certificate -> Intermediate certificate -> Leaf certificate. + * + * If the peer root certificate hash is deployed, + * this function also verifies the digest with the root hash in the certificate chain. + * + * @param spdm_context A pointer to the SPDM context. + * @param slot_id The number of slot for the certificate chain. + * @param cert_chain_size On input, indicate the size in bytes of the destination buffer to store the digest buffer. + * On output, indicate the size in bytes of the certificate chain. + * @param cert_chain A pointer to a destination buffer to store the certificate chain. + * @param trust_anchor A buffer to hold the trust_anchor which is used to validate the peer certificate, if not NULL. + * @param trust_anchor_size A buffer to hold the trust_anchor_size, if not NULL. + * + * @retval RETURN_SUCCESS The certificate chain is got successfully. + * @retval RETURN_DEVICE_ERROR A device error occurs when communicates with the device. + * @retval RETURN_SECURITY_VIOLATION Any verification fails. + **/ +libspdm_return_t libspdm_get_certificate_ex(void *context, uint8_t slot_id, + size_t *cert_chain_size, + void *cert_chain, + const void **trust_anchor, + size_t *trust_anchor_size); + +/** + * This function sends GET_CERTIFICATE to get certificate chain in one slot from device. + * + * This function verify the integrity of the certificate chain. + * root_hash -> Root certificate -> Intermediate certificate -> Leaf certificate. + * + * If the peer root certificate hash is deployed, + * this function also verifies the digest with the root hash in the certificate chain. + * + * @param spdm_context A pointer to the SPDM context. + * @param session_id Indicates if it is a secured message protected via SPDM session. + * If session_id is NULL, it is a normal message. + * If session_id is NOT NULL, it is a secured message. + * @param slot_id The number of slot for the certificate chain. + * @param cert_chain_size On input, indicate the size in bytes of the destination buffer to store the digest buffer. + * On output, indicate the size in bytes of the certificate chain. + * @param cert_chain A pointer to a destination buffer to store the certificate chain. + * @param trust_anchor A buffer to hold the trust_anchor which is used to validate the peer certificate, if not NULL. + * @param trust_anchor_size A buffer to hold the trust_anchor_size, if not NULL. + * + * @retval RETURN_SUCCESS The certificate chain is got successfully. + * @retval RETURN_DEVICE_ERROR A device error occurs when communicates with the device. + * @retval RETURN_SECURITY_VIOLATION Any verification fails. + **/ +libspdm_return_t libspdm_get_certificate_in_session(void *context, const uint32_t *session_id, + uint8_t slot_id, + size_t *cert_chain_size, + void *cert_chain, + const void **trust_anchor, + size_t *trust_anchor_size); + +/** + * This function sends GET_CERTIFICATE to get certificate chain in one slot from device. + * + * This function verify the integrity of the certificate chain. + * root_hash -> Root certificate -> Intermediate certificate -> Leaf certificate. + * + * If the peer root certificate hash is deployed, + * this function also verifies the digest with the root hash in the certificate chain. + * + * @param spdm_context A pointer to the SPDM context. + * @param slot_id The number of slot for the certificate chain. + * @param length LIBSPDM_MAX_CERT_CHAIN_BLOCK_LEN. + * @param cert_chain_size On input, indicate the size in bytes of the destination buffer to store the digest buffer. + * On output, indicate the size in bytes of the certificate chain. + * @param cert_chain A pointer to a destination buffer to store the certificate chain. + * + * @retval RETURN_SUCCESS The certificate chain is got successfully. + * @retval RETURN_DEVICE_ERROR A device error occurs when communicates with the device. + * @retval RETURN_SECURITY_VIOLATION Any verification fails. + **/ +libspdm_return_t libspdm_get_certificate_choose_length(void *spdm_context, + uint8_t slot_id, + uint16_t length, + size_t *cert_chain_size, + void *cert_chain); + +/** + * This function sends GET_CERTIFICATE to get certificate chain in one slot from device. + * + * This function verify the integrity of the certificate chain. + * root_hash -> Root certificate -> Intermediate certificate -> Leaf certificate. + * + * If the peer root certificate hash is deployed, + * this function also verifies the digest with the root hash in the certificate chain. + * + * @param spdm_context A pointer to the SPDM context. + * @param slot_id The number of slot for the certificate chain. + * @param length LIBSPDM_MAX_CERT_CHAIN_BLOCK_LEN. + * @param cert_chain_size On input, indicate the size in bytes of the destination buffer to store the digest buffer. + * On output, indicate the size in bytes of the certificate chain. + * @param cert_chain A pointer to a destination buffer to store the certificate chain. + * @param trust_anchor A buffer to hold the trust_anchor which is used to validate the peer certificate, if not NULL. + * @param trust_anchor_size A buffer to hold the trust_anchor_size, if not NULL. + * + * @retval RETURN_SUCCESS The certificate chain is got successfully. + * @retval RETURN_DEVICE_ERROR A device error occurs when communicates with the device. + * @retval RETURN_SECURITY_VIOLATION Any verification fails. + **/ +libspdm_return_t libspdm_get_certificate_choose_length_ex(void *context, + uint8_t slot_id, + uint16_t length, + size_t *cert_chain_size, + void *cert_chain, + const void **trust_anchor, + size_t *trust_anchor_size); + +/** + * This function sends GET_CERTIFICATE and receives CERTIFICATE. It may retry GET_CERTIFICATE + * multiple times if the Responder replies with a Busy error. + * + * This function verify the integrity of the certificate chain. + * root_hash -> Root certificate -> Intermediate certificate -> Leaf certificate. + * + * If the peer root certificate hash is deployed, + * this function also verifies the digest with the root hash in the certificate chain. + * + * @param spdm_context A pointer to the SPDM context. + * @param slot_id The number of slot for the certificate chain. + * @param cert_chain_size On input, indicate the size in bytes of the destination buffer to store + * the digest buffer. + * On output, indicate the size in bytes of the certificate chain. + * @param cert_chain A pointer to a destination buffer to store the certificate chain. + * @param trust_anchor A buffer to hold the trust_anchor which is used to validate the peer + * certificate, if not NULL. + * @param trust_anchor_size A buffer to hold the trust_anchor_size, if not NULL. + * + * @retval LIBSPDM_STATUS_SUCCESS + * GET_CERTIFICATE was sent and CERTIFICATE was received. + * @retval LIBSPDM_STATUS_INVALID_STATE_LOCAL + * Cannot send GET_CERTIFICATE due to Requester's state. + * @retval LIBSPDM_STATUS_UNSUPPORTED_CAP + * Cannot send GET_CERTIFICATE because the Requester's and/or Responder's CERT_CAP = 0. + * @retval LIBSPDM_STATUS_INVALID_MSG_SIZE + * The size of the CERTIFICATE response is invalid. + * @retval LIBSPDM_STATUS_INVALID_MSG_FIELD + * The CERTIFICATE response contains one or more invalid fields. + * @retval LIBSPDM_STATUS_ERROR_PEER + * The Responder returned an unexpected error. + * @retval LIBSPDM_STATUS_BUSY_PEER + * The Responder continually returned Busy error messages. + * @retval LIBSPDM_STATUS_RESYNCH_PEER + * The Responder returned a RequestResynch error message. + * @retval LIBSPDM_STATUS_BUFFER_FULL + * The buffer used to store transcripts is exhausted. + * @retval LIBSPDM_STATUS_VERIF_FAIL + * Verification of the certificate chain failed. + * @retval LIBSPDM_STATUS_INVALID_CERT + * The certificate is unable to be parsed or contains invalid field values. + * @retval LIBSPDM_STATUS_CRYPTO_ERROR + * A generic cryptography error occurred. + **/ +libspdm_return_t libspdm_get_certificate_choose_length_in_session(void *context, + const uint32_t *session_id, + uint8_t slot_id, + uint16_t length, + size_t *cert_chain_size, + void *cert_chain, + const void **trust_anchor, + size_t *trust_anchor_size); + +/** + * This function sends CHALLENGE to authenticate the device based upon the key in one slot. + * + * This function verifies the signature in the challenge auth. + * + * If basic mutual authentication is requested from the responder, + * this function also perform the basic mutual authentication. + * + * @param spdm_context A pointer to the SPDM context. + * @param slot_id The number of slot for the challenge. + * @param measurement_hash_type The type of the measurement hash. + * @param measurement_hash A pointer to a destination buffer to store the measurement hash. + * @param slot_mask A pointer to a destination to store the slot mask. + * + * @retval RETURN_SUCCESS The challenge auth is got successfully. + * @retval RETURN_DEVICE_ERROR A device error occurs when communicates with the device. + * @retval RETURN_SECURITY_VIOLATION Any verification fails. + **/ +libspdm_return_t libspdm_challenge(void *spdm_context, uint8_t slot_id, + uint8_t measurement_hash_type, + void *measurement_hash, + uint8_t *slot_mask); + +/** + * This function sends CHALLENGE to authenticate the device based upon the key in one slot. + * + * This function verifies the signature in the challenge auth. + * + * If basic mutual authentication is requested from the responder, + * this function also perform the basic mutual authentication. + * + * @param spdm_context A pointer to the SPDM context. + * @param slot_id The number of slot for the challenge. + * @param measurement_hash_type The type of the measurement hash. + * @param measurement_hash A pointer to a destination buffer to store the measurement hash. + * @param slot_mask A pointer to a destination to store the slot mask. + * @param requester_nonce_in A buffer to hold the requester nonce (32 bytes) as input, if not NULL. + * @param requester_nonce A buffer to hold the requester nonce (32 bytes), if not NULL. + * @param responder_nonce A buffer to hold the responder nonce (32 bytes), if not NULL. + * + * @retval RETURN_SUCCESS The challenge auth is got successfully. + * @retval RETURN_DEVICE_ERROR A device error occurs when communicates with the device. + * @retval RETURN_SECURITY_VIOLATION Any verification fails. + **/ +libspdm_return_t libspdm_challenge_ex(void *context, uint8_t slot_id, + uint8_t measurement_hash_type, + void *measurement_hash, + uint8_t *slot_mask, + const void *requester_nonce_in, + void *requester_nonce, + void *responder_nonce); + +/** + * This function sends GET_MEASUREMENT + * to get measurement from the device. + * + * If the signature is requested, this function verifies the signature of the measurement. + * + * @param spdm_context A pointer to the SPDM context. + * @param session_id Indicates if it is a secured message protected via SPDM session. + * If session_id is NULL, it is a normal message. + * If session_id is NOT NULL, it is a secured message. + * @param request_attribute The request attribute of the request message. + * @param measurement_operation The measurement operation of the request message. + * @param slot_id The number of slot for the certificate chain. + * @param content_changed The measurement content changed output param. + * @param number_of_blocks The number of blocks of the measurement record. + * @param measurement_record_length On input, indicate the size in bytes of the destination buffer to store the measurement record. + * On output, indicate the size in bytes of the measurement record. + * @param measurement_record A pointer to a destination buffer to store the measurement record. + * + * @retval RETURN_SUCCESS The measurement is got successfully. + * @retval RETURN_DEVICE_ERROR A device error occurs when communicates with the device. + * @retval RETURN_SECURITY_VIOLATION Any verification fails. + **/ +libspdm_return_t libspdm_get_measurement(void *spdm_context, const uint32_t *session_id, + uint8_t request_attribute, + uint8_t measurement_operation, + uint8_t slot_id, + uint8_t *content_changed, + uint8_t *number_of_blocks, + uint32_t *measurement_record_length, + void *measurement_record); + +/** + * This function sends GET_MEASUREMENT to get measurement from the device. + * + * If the signature is requested, this function verifies the signature of the measurement. + * + * @param spdm_context A pointer to the SPDM context. + * @param session_id Indicates if it is a secured message protected via SPDM session. + * If session_id is NULL, it is a normal message. + * If session_id is NOT NULL, it is a secured message. + * @param request_attribute The request attribute of the request message. + * @param measurement_operation The measurement operation of the request message. + * @param slot_id The number of slot for the certificate chain. + * @param content_changed The measurement content changed output param. + * @param number_of_blocks The number of blocks of the measurement record. + * @param measurement_record_length On input, indicate the size in bytes of the destination buffer to store the measurement record. + * On output, indicate the size in bytes of the measurement record. + * @param measurement_record A pointer to a destination buffer to store the measurement record. + * @param requester_nonce_in A buffer to hold the requester nonce (32 bytes) as input, if not NULL. + * @param requester_nonce A buffer to hold the requester nonce (32 bytes), if not NULL. + * @param responder_nonce A buffer to hold the responder nonce (32 bytes), if not NULL. + * + * @retval RETURN_SUCCESS The measurement is got successfully. + * @retval RETURN_DEVICE_ERROR A device error occurs when communicates with the device. + * @retval RETURN_SECURITY_VIOLATION Any verification fails. + **/ +libspdm_return_t libspdm_get_measurement_ex(void *context, const uint32_t *session_id, + uint8_t request_attribute, + uint8_t measurement_operation, + uint8_t slot_id, + uint8_t *content_changed, + uint8_t *number_of_blocks, + uint32_t *measurement_record_length, + void *measurement_record, + const void *requester_nonce_in, + void *requester_nonce, + void *responder_nonce); + +#if (LIBSPDM_ENABLE_CAPABILITY_KEY_EX_CAP) || (LIBSPDM_ENABLE_CAPABILITY_PSK_EX_CAP) +/** + * This function sends KEY_EXCHANGE/FINISH or PSK_EXCHANGE/PSK_FINISH + * to start an SPDM Session. + * + * If encapsulated mutual authentication is requested from the responder, + * this function also perform the encapsulated mutual authentication. + * + * @param spdm_context A pointer to the SPDM context. + * @param use_psk False means to use KEY_EXCHANGE/FINISH to start a session. + * True means to use PSK_EXCHANGE/PSK_FINISH to start a session. + * @param measurement_hash_type The type of the measurement hash. + * @param slot_id The number of slot for the certificate chain. + * @param session_policy The policy for the session. + * @param session_id The session ID of the session. + * @param heartbeat_period The heartbeat period for the session. + * @param measurement_hash A pointer to a destination buffer to store the measurement hash. + * + * @retval RETURN_SUCCESS The SPDM session is started. + * @retval RETURN_DEVICE_ERROR A device error occurs when communicates with the device. + * @retval RETURN_SECURITY_VIOLATION Any verification fails. + **/ +libspdm_return_t libspdm_start_session(void *spdm_context, bool use_psk, + uint8_t measurement_hash_type, + uint8_t slot_id, + uint8_t session_policy, + uint32_t *session_id, + uint8_t *heartbeat_period, + void *measurement_hash); + +/** + * This function sends KEY_EXCHANGE/FINISH or PSK_EXCHANGE/PSK_FINISH to start an SPDM Session. + * + * If encapsulated mutual authentication is requested from the responder, + * this function also perform the encapsulated mutual authentication. + * + * @param spdm_context A pointer to the SPDM context. + * @param use_psk False means to use KEY_EXCHANGE/FINISH to start a session. + * True means to use PSK_EXCHANGE/PSK_FINISH to start a session. + * @param measurement_hash_type The type of the measurement hash. + * @param slot_id The number of slot for the certificate chain. + * @param session_policy The policy for the session. + * @param session_id The session ID of the session. + * @param heartbeat_period The heartbeat period for the session. + * @param measurement_hash A pointer to a destination buffer to store the measurement hash. + * @param requester_random_in A buffer to hold the requester random as input, if not NULL. + * @param requester_random_in_size The size of requester_random_in. + * If use_psk is false, it must be 32 bytes. + * If use_psk is true, it means the PSK context and must be 32 bytes at least, + * but not exceed LIBSPDM_PSK_CONTEXT_LENGTH. + * @param requester_random A buffer to hold the requester random, if not NULL. + * @param requester_random_size On input, the size of requester_random buffer. + * On output, the size of data returned in requester_random buffer. + * If use_psk is false, it must be 32 bytes. + * If use_psk is true, it means the PSK context and must be 32 bytes at least. + * @param responder_random A buffer to hold the responder random, if not NULL. + * @param responder_random_size On input, the size of requester_random buffer. + * On output, the size of data returned in requester_random buffer. + * If use_psk is false, it must be 32 bytes. + * If use_psk is true, it means the PSK context. It could be 0 if device does not support context. + * + * @retval RETURN_SUCCESS The SPDM session is started. + * @retval RETURN_DEVICE_ERROR A device error occurs when communicates with the device. + * @retval RETURN_SECURITY_VIOLATION Any verification fails. + **/ +libspdm_return_t libspdm_start_session_ex(void *spdm_context, bool use_psk, + uint8_t measurement_hash_type, + uint8_t slot_id, + uint8_t session_policy, + uint32_t *session_id, + uint8_t *heartbeat_period, + void *measurement_hash, + const void *requester_random_in, + size_t requester_random_in_size, + void *requester_random, + size_t *requester_random_size, + void *responder_random, + size_t *responder_random_size); + +/** + * This function sends END_SESSION to stop an SPDM Session. + * + * @param spdm_context A pointer to the SPDM context. + * @param session_id The session ID of the session. + * @param end_session_attributes The end session attribute for the session. + * + * @retval RETURN_SUCCESS The SPDM session is stopped. + * @retval RETURN_DEVICE_ERROR A device error occurs when communicates with the device. + * @retval RETURN_SECURITY_VIOLATION Any verification fails. + **/ +libspdm_return_t libspdm_stop_session(void *spdm_context, uint32_t session_id, + uint8_t end_session_attributes); +#endif /* (LIBSPDM_ENABLE_CAPABILITY_KEY_EX_CAP) || (LIBSPDM_ENABLE_CAPABILITY_PSK_EX_CAP) */ + +/** + * Send and receive an SPDM or APP message. + * + * The SPDM message can be a normal message or a secured message in SPDM session. + * + * The APP message is encoded to a secured message directly in SPDM session. + * The APP message format is defined by the transport layer. + * Take MCTP as example: APP message == MCTP header (MCTP_MESSAGE_TYPE_SPDM) + SPDM message + * + * @param spdm_context A pointer to the SPDM context. + * @param session_id Indicates if it is a secured message protected via SPDM session. + * If session_id is NULL, it is a normal message. + * If session_id is NOT NULL, it is a secured message. + * @param is_app_message Indicates if it is an APP message or SPDM message. + * @param request A pointer to the request data. + * @param request_size Size in bytes of the request data. + * @param response A pointer to the response data. + * @param response_size Size in bytes of the response data. + * On input, it means the size in bytes of response data buffer. + * On output, it means the size in bytes of copied response data buffer if RETURN_SUCCESS is returned, + * and means the size in bytes of desired response data buffer if RETURN_BUFFER_TOO_SMALL is returned. + * + * @retval RETURN_SUCCESS The SPDM request is set successfully. + * @retval RETURN_BUFFER_TOO_SMALL The buffer is too small to hold the data. + * @retval RETURN_DEVICE_ERROR A device error occurs when communicates with the device. + * @retval RETURN_SECURITY_VIOLATION Any verification fails. + **/ +libspdm_return_t libspdm_send_receive_data(void *spdm_context, + const uint32_t *session_id, + bool is_app_message, + const void *request, size_t request_size, + void *response, + size_t *response_size); + +/** + * This function sends HEARTBEAT + * to an SPDM Session. + * + * @param spdm_context A pointer to the SPDM context. + * @param session_id The session ID of the session. + * + * @retval RETURN_SUCCESS The heartbeat is sent and received. + * @retval RETURN_DEVICE_ERROR A device error occurs when communicates with the device. + * @retval RETURN_SECURITY_VIOLATION Any verification fails. + **/ +libspdm_return_t libspdm_heartbeat(void *spdm_context, uint32_t session_id); + +/** + * This function sends KEY_UPDATE + * to update keys for an SPDM Session. + * + * After keys are updated, this function also uses VERIFY_NEW_KEY to verify the key. + * + * @param spdm_context A pointer to the SPDM context. + * @param session_id The session ID of the session. + * @param single_direction true means the operation is UPDATE_KEY. + * false means the operation is UPDATE_ALL_KEYS. + * + * @retval RETURN_SUCCESS The keys of the session are updated. + * @retval RETURN_DEVICE_ERROR A device error occurs when communicates with the device. + * @retval RETURN_SECURITY_VIOLATION Any verification fails. + **/ +libspdm_return_t libspdm_key_update(void *spdm_context, uint32_t session_id, bool single_direction); + +/** + * This function executes a series of SPDM encapsulated requests and receives SPDM encapsulated responses. + * + * This function starts with the first encapsulated request (such as GET_ENCAPSULATED_REQUEST) + * and ends with last encapsulated response (such as RESPONSE_PAYLOAD_TYPE_ABSENT or RESPONSE_PAYLOAD_TYPE_SLOT_NUMBER). + * + * @param spdm_context A pointer to the SPDM context. + * @param session_id Indicate if the encapsulated request is a secured message. + * If session_id is NULL, it is a normal message. + * If session_id is not NULL, it is a secured message. + * + * @retval RETURN_SUCCESS The SPDM Encapsulated requests are sent and the responses are received. + * @retval RETURN_DEVICE_ERROR A device error occurs when communicates with the device. + **/ +libspdm_return_t libspdm_send_receive_encap_request(void *spdm_context, const uint32_t *session_id); + +/** + * Process the encapsulated request and return the encapsulated response. + * + * @param spdm_context A pointer to the SPDM context. + * @param spdm_request_size Size in bytes of the request data. + * @param spdm_request A pointer to the request data. + * @param spdm_response_size Size in bytes of the response data. + * On input, it means the size in bytes of response data buffer. + * On output, it means the size in bytes of copied response data buffer if RETURN_SUCCESS is returned, + * and means the size in bytes of desired response data buffer if RETURN_BUFFER_TOO_SMALL is returned. + * @param spdm_response A pointer to the response data. + * + * @retval RETURN_SUCCESS The request is processed and the response is returned. + * @retval RETURN_BUFFER_TOO_SMALL The buffer is too small to hold the data. + * @retval RETURN_DEVICE_ERROR A device error occurs when communicates with the device. + * @retval RETURN_SECURITY_VIOLATION Any verification fails. + **/ +typedef libspdm_return_t (*libspdm_get_encap_response_func)( + void *spdm_context, size_t spdm_request_size, + void *spdm_request, size_t *spdm_response_size, + void *spdm_response); + +/** + * Register an SPDM encapsulated message process function. + * + * If the default encapsulated message process function cannot handle the encapsulated message, + * this function will be invoked. + * + * @param spdm_context A pointer to the SPDM context. + * @param get_encap_response_func The function to process the encapsuled message. + **/ +void libspdm_register_get_encap_response_func(void *spdm_context, + const libspdm_get_encap_response_func + get_encap_response_func); + +/** + * Generate encapsulated ERROR message. + * + * This function can be called in libspdm_get_encap_response_func. + * + * @param spdm_context A pointer to the SPDM context. + * @param error_code The error code of the message. + * @param error_data The error data of the message. + * @param spdm_response_size Size in bytes of the response data. + * On input, it means the size in bytes of data buffer. + * On output, it means the size in bytes of copied data buffer if RETURN_SUCCESS is returned, + * and means the size in bytes of desired data buffer if RETURN_BUFFER_TOO_SMALL is returned. + * @param spdm_response A pointer to the response data. + * + * @retval RETURN_SUCCESS The error message is generated. + * @retval RETURN_BUFFER_TOO_SMALL The buffer is too small to hold the data. + **/ +libspdm_return_t libspdm_generate_encap_error_response( + const void *spdm_context, uint8_t error_code, uint8_t error_data, + size_t *spdm_response_size, void *spdm_response); + +/** + * Generate encapsulated ERROR message with extended error data. + * + * This function can be called in libspdm_get_encap_response_func. + * + * @param spdm_context A pointer to the SPDM context. + * @param error_code The error code of the message. + * @param error_data The error data of the message. + * @param extended_error_data_size The size in bytes of the extended error data. + * @param extended_error_data A pointer to the extended error data. + * @param spdm_response_size Size in bytes of the response data. + * On input, it means the size in bytes of response data buffer. + * On output, it means the size in bytes of copied response data buffer if RETURN_SUCCESS is returned, + * and means the size in bytes of desired response data buffer if RETURN_BUFFER_TOO_SMALL is returned. + * @param spdm_response A pointer to the response data. + * + * @retval RETURN_SUCCESS The error message is generated. + * @retval RETURN_BUFFER_TOO_SMALL The buffer is too small to hold the data. + **/ +libspdm_return_t libspdm_generate_encap_extended_error_response( + const void *spdm_context, uint8_t error_code, uint8_t error_data, + size_t extended_error_data_size, const uint8_t *extended_error_data, + size_t *spdm_response_size, void *spdm_response); + +#if LIBSPDM_ENABLE_CAPABILITY_GET_CSR_CAP +/** + * This function sends GET_CSR + * to get csr from the device. + * + * @param[in] context A pointer to the SPDM context. + * @param[in] requester_info Requester info to gen CSR + * @param[in] requester_info_length The length of requester info + * @param[in] opaque_data opaque data. + * @param[in] opaque_data_length The length of opaque data. + * @param[in] session_id Indicates if it is a secured message protected via SPDM session. + * If session_id is NULL, it is a normal message. + * If session_id is NOT NULL, it is a secured message. + * @param[out] csr Address to store CSR. + * @param[out] csr_len On input, *csr_len indicates the max csr buffer size. + * On output, *csr_len indicates the actual csr buffer size. + * + * @retval RETURN_SUCCESS The measurement is got successfully. + * @retval RETURN_DEVICE_ERROR A device error occurs when communicates with the device. + * @retval RETURN_SECURITY_VIOLATION Any verification fails. + **/ +libspdm_return_t libspdm_get_csr(void *context, + void *requester_info, uint16_t requester_info_length, + void *opaque_data, uint16_t opaque_data_length, + const uint32_t *session_id, + void *csr, size_t *csr_len); +#endif /*LIBSPDM_ENABLE_CAPABILITY_GET_CSR_CAP*/ + +#if LIBSPDM_ENABLE_CAPABILITY_SET_CERTIFICATE_CAP || LIBSPDM_ENABLE_SET_CERTIFICATE_CAP +/** + * This function try to send SET_CERTIFICATE + * to set certificate from the device. + * + * @param context A pointer to the SPDM context. + * @param slot_id The number of slot for the certificate chain. + * @param cert_chain The pointer for the certificate chain to set. + * The cert chain is a full SPDM certificate chain, including Length and Root Cert Hash. + * @param cert_chain_size The size of the certificate chain to set. + * @param session_id Indicates if it is a secured message protected via SPDM session. + * If session_id is NULL, it is a normal message. + * If session_id is NOT NULL, it is a secured message. + * + * @retval RETURN_SUCCESS The measurement is got successfully. + * @retval RETURN_DEVICE_ERROR A device error occurs when communicates with the device. + * @retval RETURN_SECURITY_VIOLATION Any verification fails. + **/ +libspdm_return_t libspdm_set_certificate(void * context, uint8_t slot_id, + void * cert_chain, size_t cert_chain_size, + const uint32_t *session_id); + +#endif /* LIBSPDM_ENABLE_CAPABILITY_SET_CERTIFICATE_CAP */ + +#if LIBSPDM_ENABLE_MSG_LOG +/* For now these functions are only available to the Requester. They may become available to the + * Responder at a later time. + */ + +/** + * This function initializes message logging. The caller must provide a buffer and the buffer's + * size. + * + * @param context A pointer to the SPDM context. + * @param msg_buffer A pointer to a caller-provided buffer. + * @param msg_buffer_size The size of the buffer in bytes. It must be greater than zero. + **/ +void libspdm_init_msg_log (void *context, void *msg_buffer, size_t msg_buffer_size); + +/** + * This function sets the mode in which the message logger operates. + * + * @param context A pointer to the SPDM context. + * @param mode A bitmask specifying the mode in which the message logger operates. + * LIBSPDM_MSG_LOG_MODE_ENABLE - when set the message logger is active. + */ +void libspdm_set_msg_log_mode (void *context, uint32_t mode); + +/** + * This function returns the status of the message logger. + * + * @param context A pointer to the SPDM context. + * + * @retval uint32_t A bitmask giving the status of the message logger. + * LIBSPDM_MSG_LOG_STATUS_BUFFER_FULL - if set the message logging buffer has + * reached capacity. + */ +uint32_t libspdm_get_msg_log_status (void *context); + +/** + * This function returns the size of the message log. + * + * @param context A pointer to the SPDM context. + * @retval size_t The size of the message log in bytes. + */ +size_t libspdm_get_msg_log_size (void *context); + +/** + * This function resets the message log while retaining the message buffer and maximum size given in + * libspdm_init_msg_log. + * + * @param context A pointer to the SPDM context. + */ +void libspdm_reset_msg_log (void *context); +#endif /* LIBSPDM_ENABLE_MSG_LOG */ + +#endif /* SPDM_REQUESTER_LIB_H */ diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/libraries/libspdm/2.3.1/include/library/spdm_responder_lib.h nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/libraries/libspdm/2.3.1/include/library/spdm_responder_lib.h --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/libraries/libspdm/2.3.1/include/library/spdm_responder_lib.h 1970-01-01 00:00:00.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/libraries/libspdm/2.3.1/include/library/spdm_responder_lib.h 2024-03-05 22:14:14.000000000 +0000 @@ -0,0 +1,257 @@ +/** + * Copyright Notice: + * Copyright 2021-2022 DMTF. All rights reserved. + * License: BSD 3-Clause License. For full text see link: https://github.com/DMTF/libspdm/blob/main/LICENSE.md + **/ + +#ifndef SPDM_RESPONDER_LIB_H +#define SPDM_RESPONDER_LIB_H + +#include "library/spdm_common_lib.h" + +/** + * Process the SPDM or APP request and return the response. + * + * The APP message is encoded to a secured message directly in SPDM session. + * The APP message format is defined by the transport layer. + * Take MCTP as example: APP message == MCTP header (MCTP_MESSAGE_TYPE_SPDM) + SPDM message + * + * @param spdm_context A pointer to the SPDM context. + * @param session_id Indicates if it is a secured message protected via SPDM session. + * If session_id is NULL, it is a normal message. + * If session_id is NOT NULL, it is a secured message. + * @param is_app_message Indicates if it is an APP message or SPDM message. + * @param request_size size in bytes of the request data. + * @param request A pointer to the request data. + * @param response_size size in bytes of the response data. + * On input, it means the size in bytes of response data buffer. + * On output, it means the size in bytes of copied response data buffer if RETURN_SUCCESS is returned, + * and means the size in bytes of desired response data buffer if RETURN_BUFFER_TOO_SMALL is returned. + * @param response A pointer to the response data. + * + * @retval RETURN_SUCCESS The request is processed and the response is returned. + * @retval RETURN_BUFFER_TOO_SMALL The buffer is too small to hold the data. + * @retval RETURN_DEVICE_ERROR A device error occurs when communicates with the device. + * @retval RETURN_SECURITY_VIOLATION Any verification fails. + * @retval RETURN_UNSUPPORTED Just ignore this message: return UNSUPPORTED and clear response_size. + * Continue the dispatch without send response. + **/ +typedef libspdm_return_t (*libspdm_get_response_func)( + void *spdm_context, const uint32_t *session_id, bool is_app_message, + size_t request_size, const void *request, size_t *response_size, + void *response); + +/** + * Register an SPDM or APP message process function. + * + * If the default message process function cannot handle the message, + * this function will be invoked. + * + * @param spdm_context A pointer to the SPDM context. + * @param get_response_func The function to process the encapsuled message. + **/ +void libspdm_register_get_response_func( + void *spdm_context, libspdm_get_response_func get_response_func); + +/** + * Process a SPDM request from a device. + * + * @param spdm_context The SPDM context for the device. + * @param session_id Indicate if the request is a secured message. + * If session_id is NULL, it is a normal message. + * If session_id is NOT NULL, it is a secured message. + * @param is_app_message Indicates if it is an APP message or SPDM message. + * @param request_size size in bytes of the request data buffer. + * @param request A pointer to a destination buffer to store the request. + * The caller is responsible for having + * either implicit or explicit ownership of the buffer. + * + * @retval RETURN_SUCCESS The SPDM request is received successfully. + * @retval RETURN_DEVICE_ERROR A device error occurs when the SPDM request is received from the device. + **/ +libspdm_return_t libspdm_process_request(void *spdm_context, + uint32_t **session_id, + bool *is_app_message, + size_t request_size, void *request); + +/** + * Build a SPDM response to a device. + * + * @param spdm_context The SPDM context for the device. + * @param session_id Indicate if the response is a secured message. + * If session_id is NULL, it is a normal message. + * If session_id is NOT NULL, it is a secured message. + * @param is_app_message Indicates if it is an APP message or SPDM message. + * @param response_size size in bytes of the response data buffer. + * @param response A pointer to a destination buffer to store the response. + * The caller is responsible for having + * either implicit or explicit ownership of the buffer. + * + * @retval RETURN_SUCCESS The SPDM response is sent successfully. + * @retval RETURN_DEVICE_ERROR A device error occurs when the SPDM response is sent to the device. + * @retval RETURN_UNSUPPORTED Just ignore this message: return UNSUPPORTED and clear response_size. + * Continue the dispatch without send response. + **/ +libspdm_return_t libspdm_build_response(void *spdm_context, const uint32_t *session_id, + bool is_app_message, + size_t *response_size, + void **response); + +/** + * This is the main dispatch function in SPDM responder. + * + * It receives one request message, processes it and sends the response message. + * + * It should be called in a while loop or an timer/interrupt handler. + * + * @param spdm_context A pointer to the SPDM context. + * + * @retval RETURN_SUCCESS One SPDM request message is processed. + * @retval RETURN_DEVICE_ERROR A device error occurs when communicates with the device. + * @retval RETURN_UNSUPPORTED One request message is not supported. + **/ +libspdm_return_t libspdm_responder_dispatch_message(void *spdm_context); + +/** + * Generate ERROR message. + * + * This function can be called in libspdm_get_response_func. + * + * @param spdm_context A pointer to the SPDM context. + * @param error_code The error code of the message. + * @param error_data The error data of the message. + * @param spdm_response_size size in bytes of the response data. + * On input, it means the size in bytes of response data buffer. + * On output, it means the size in bytes of copied response data buffer if RETURN_SUCCESS is returned, + * and means the size in bytes of desired response data buffer if RETURN_BUFFER_TOO_SMALL is returned. + * @param spdm_response A pointer to the response data. + * + * @retval RETURN_SUCCESS The error message is generated. + * @retval RETURN_BUFFER_TOO_SMALL The buffer is too small to hold the data. + **/ +libspdm_return_t libspdm_generate_error_response(const void *spdm_context, + uint8_t error_code, + uint8_t error_data, + size_t *spdm_response_size, + void *spdm_response); + +/** + * Generate ERROR message with extended error data. + * + * This function can be called in libspdm_get_response_func. + * + * @param spdm_context A pointer to the SPDM context. + * @param error_code The error code of the message. + * @param error_data The error data of the message. + * @param extended_error_data_size The size in bytes of the extended error data. + * @param extended_error_data A pointer to the extended error data. + * @param spdm_response_size size in bytes of the response data. + * On input, it means the size in bytes of response data buffer. + * On output, it means the size in bytes of copied response data buffer if RETURN_SUCCESS is returned, + * and means the size in bytes of desired response data buffer if RETURN_BUFFER_TOO_SMALL is returned. + * @param spdm_response A pointer to the response data. + * + * @retval RETURN_SUCCESS The error message is generated. + * @retval RETURN_BUFFER_TOO_SMALL The buffer is too small to hold the data. + **/ +libspdm_return_t libspdm_generate_extended_error_response( + const void *context, uint8_t error_code, uint8_t error_data, + size_t extended_error_data_size, const uint8_t *extended_error_data, + size_t *spdm_response_size, void *spdm_response); + +/** + * Notify the session state to a session APP. + * + * @param spdm_context A pointer to the SPDM context. + * @param session_id The session_id of a session. + * @param session_state The state of a session. + **/ +typedef void (*libspdm_session_state_callback_func)( + void *spdm_context, uint32_t session_id, + libspdm_session_state_t session_state); + +/** + * Register an SPDM state callback function. + * + * This function can be called multiple times to let different session APPs register its own callback. + * + * @param spdm_context A pointer to the SPDM context. + * @param spdm_session_state_callback The function to be called in SPDM session state change. + * + * @retval RETURN_SUCCESS The callback is registered. + * @retval RETURN_ALREADY_STARTED No enough memory to register the callback. + **/ +libspdm_return_t libspdm_register_session_state_callback_func( + void *spdm_context, + libspdm_session_state_callback_func spdm_session_state_callback); + +/** + * Notify the connection state to an SPDM context register. + * + * @param spdm_context A pointer to the SPDM context. + * @param connection_state Indicate the SPDM connection state. + **/ +typedef void (*libspdm_connection_state_callback_func)( + void *spdm_context, libspdm_connection_state_t connection_state); + +/** + * Register an SPDM connection state callback function. + * + * This function can be called multiple times to let different register its own callback. + * + * @param spdm_context A pointer to the SPDM context. + * @param spdm_connection_state_callback The function to be called in SPDM connection state change. + * + * @retval RETURN_SUCCESS The callback is registered. + * @retval RETURN_ALREADY_STARTED No enough memory to register the callback. + **/ +libspdm_return_t libspdm_register_connection_state_callback_func( + void *spdm_context, + libspdm_connection_state_callback_func spdm_connection_state_callback); + +/** + * Notify the key update operation to an SPDM context register. + * + * @param spdm_context A pointer to the SPDM context. + * @param session_id Session ID for the keys being updated. + * @param key_update_operation Indicate the key update operation. + * @param key_update_action Indicate the direction of the key update. + **/ +typedef void (*libspdm_key_update_callback_func)( + void *spdm_context, uint32_t session_id, libspdm_key_update_operation_t key_update_op, + libspdm_key_update_action_t key_update_action); + +/** + * Notify the key update operation to an SPDM context register. + * + * @param spdm_context A pointer to the SPDM context. + * @param session_id Session ID for the keys being updated. + * @param key_update_operation Indicate the key update operation. + * @param key_update_action Indicate the direction of the key update. + **/ +void libspdm_trigger_key_update_callback( + void *spdm_context, uint32_t session_id, libspdm_key_update_operation_t key_update_op, + libspdm_key_update_action_t key_update_action); + +/** + * Register a key update callback function. + * + * This function can be called multiple times to register multiple callbacks. + * + * @param spdm_context A pointer to the SPDM context. + * @param spdm_key_update_callback The function to be called in key update operation. + * + * @retval RETURN_SUCCESS The callback is registered. + * @retval RETURN_ALREADY_STARTED No enough memory to register the callback. + **/ +libspdm_return_t libspdm_register_key_update_callback_func( + void *spdm_context, libspdm_key_update_callback_func spdm_key_update_callback); + +/** + * This function initializes the key_update encapsulated state. + * + * @param spdm_context A pointer to the SPDM context. + **/ +void libspdm_init_key_update_encap_state(void *spdm_context); + +#endif /*SPDM_RESPONDER_LIB_H */ diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/libraries/libspdm/2.3.1/include/library/spdm_return_status.h nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/libraries/libspdm/2.3.1/include/library/spdm_return_status.h --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/libraries/libspdm/2.3.1/include/library/spdm_return_status.h 1970-01-01 00:00:00.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/libraries/libspdm/2.3.1/include/library/spdm_return_status.h 2024-03-05 22:14:14.000000000 +0000 @@ -0,0 +1,185 @@ +/** + * Copyright Notice: + * Copyright 2021-2022 DMTF. All rights reserved. + * License: BSD 3-Clause License. For full text see link: https://github.com/DMTF/libspdm/blob/main/LICENSE.md + **/ + +#ifndef SPDM_RETURN_STATUS_H +#define SPDM_RETURN_STATUS_H + +#ifndef LIBSPDM_STDINT_ALT +#include +#else +#include LIBSPDM_STDINT_ALT +#endif + +/* The layout of libspdm_return_t is + * [31:28] - Severity + * [27:24] - Reserved + * [23:16] - Source + * [15:00] - Code + */ +typedef uint32_t libspdm_return_t; + +/* Returns 1 if severity is LIBSPDM_SEVERITY_SUCCESS else it returns 0. */ +#define LIBSPDM_STATUS_IS_SUCCESS(status) \ + (LIBSPDM_STATUS_SEVERITY(status) == LIBSPDM_SEVERITY_SUCCESS) + +/* Returns 1 if severity is LIBSPDM_SEVERITY_ERROR else it returns 0. */ +#define LIBSPDM_STATUS_IS_ERROR(status) \ + (LIBSPDM_STATUS_SEVERITY(status) == LIBSPDM_SEVERITY_ERROR) + +/* Returns the severity of the status. */ +#define LIBSPDM_STATUS_SEVERITY(status) (((status) >> 28) & 0xf) + +/* Returns the source of the status. */ +#define LIBSPDM_STATUS_SOURCE(status) (((status) >> 16) & 0xff) + +#define LIBSPDM_SEVERITY_SUCCESS 0x0 +#define LIBSPDM_SEVERITY_ERROR 0x8 + +#define LIBSPDM_SOURCE_SUCCESS 0x00 +#define LIBSPDM_SOURCE_CORE 0x01 +#define LIBSPDM_SOURCE_CRYPTO 0x02 +#define LIBSPDM_SOURCE_CERT_PARSE 0x03 + +/*LIBSPSM_SOURCE_TRANSPORT is deprecated. Do not use it. Reserved only.*/ +#define LIBSPSM_SOURCE_TRANSPORT 0x04 + +#define LIBSPDM_SOURCE_TRANSPORT 0x04 +#define LIBSPDM_SOURCE_MEAS_COLLECT 0x05 +#define LIBSPDM_SOURCE_RNG 0x06 + +#define LIBSPDM_STATUS_CONSTRUCT(severity, source, code) \ + ((libspdm_return_t)(((severity) << 28) | ((source) << 16) | (code))) + +/* Success status is always 0x00000000. */ +#define LIBSPDM_STATUS_SUCCESS \ + LIBSPDM_STATUS_CONSTRUCT(LIBSPDM_SEVERITY_SUCCESS, LIBSPDM_SOURCE_SUCCESS, 0x0000) + +#define LIBSPDM_RET_ON_ERR(status) \ + do { \ + if (LIBSPDM_STATUS_IS_ERROR(status)) { \ + return (status); \ + } \ + } \ + while (0) + +/* - Core Errors - */ + +/* The function input parameter is invalid. */ +#define LIBSPDM_STATUS_INVALID_PARAMETER \ + LIBSPDM_STATUS_CONSTRUCT(LIBSPDM_SEVERITY_ERROR, LIBSPDM_SOURCE_CORE, 0x0001) + +/* Unable to complete operation due to unsupported capabilities by either the caller, the peer, + * or both. */ +#define LIBSPDM_STATUS_UNSUPPORTED_CAP \ + LIBSPDM_STATUS_CONSTRUCT(LIBSPDM_SEVERITY_ERROR, LIBSPDM_SOURCE_CORE, 0x0002) + +/* Unable to complete operation due to caller's state. */ +#define LIBSPDM_STATUS_INVALID_STATE_LOCAL \ + LIBSPDM_STATUS_CONSTRUCT(LIBSPDM_SEVERITY_ERROR, LIBSPDM_SOURCE_CORE, 0x0003) + +/* Unable to complete operation due to peer's state. */ +#define LIBSPDM_STATUS_INVALID_STATE_PEER \ + LIBSPDM_STATUS_CONSTRUCT(LIBSPDM_SEVERITY_ERROR, LIBSPDM_SOURCE_CORE, 0x0004) + +/* The received message contains one or more invalid message fields. */ +#define LIBSPDM_STATUS_INVALID_MSG_FIELD \ + LIBSPDM_STATUS_CONSTRUCT(LIBSPDM_SEVERITY_ERROR, LIBSPDM_SOURCE_CORE, 0x0005) + +/* The received message's size is invalid. */ +#define LIBSPDM_STATUS_INVALID_MSG_SIZE \ + LIBSPDM_STATUS_CONSTRUCT(LIBSPDM_SEVERITY_ERROR, LIBSPDM_SOURCE_CORE, 0x0006) + +/* Unable to derive a common set of versions, algorithms, etc. */ +#define LIBSPDM_STATUS_NEGOTIATION_FAIL \ + LIBSPDM_STATUS_CONSTRUCT(LIBSPDM_SEVERITY_ERROR, LIBSPDM_SOURCE_CORE, 0x0007) + +/* Received a Busy error message. */ +#define LIBSPDM_STATUS_BUSY_PEER \ + LIBSPDM_STATUS_CONSTRUCT(LIBSPDM_SEVERITY_ERROR, LIBSPDM_SOURCE_CORE, 0x0008) + +/* Received a NotReady error message. */ +#define LIBSPDM_STATUS_NOT_READY_PEER \ + LIBSPDM_STATUS_CONSTRUCT(LIBSPDM_SEVERITY_ERROR, LIBSPDM_SOURCE_CORE, 0x0009) + +/* Received an unexpected error message. */ +#define LIBSPDM_STATUS_ERROR_PEER \ + LIBSPDM_STATUS_CONSTRUCT(LIBSPDM_SEVERITY_ERROR, LIBSPDM_SOURCE_CORE, 0x000a) + +/* Received a RequestResynch error message. */ +#define LIBSPDM_STATUS_RESYNCH_PEER \ + LIBSPDM_STATUS_CONSTRUCT(LIBSPDM_SEVERITY_ERROR, LIBSPDM_SOURCE_CORE, 0x000b) + +/* Unable to append new data to buffer due to resource exhaustion. */ +#define LIBSPDM_STATUS_BUFFER_FULL \ + LIBSPDM_STATUS_CONSTRUCT(LIBSPDM_SEVERITY_ERROR, LIBSPDM_SOURCE_CORE, 0x000c) + +/* Unable to return data because caller does not provide big enough buffer. */ +#define LIBSPDM_STATUS_BUFFER_TOO_SMALL \ + LIBSPDM_STATUS_CONSTRUCT(LIBSPDM_SEVERITY_ERROR, LIBSPDM_SOURCE_CORE, 0x000d) + +/* Unable to allocate more session. */ +#define LIBSPDM_STATUS_SESSION_NUMBER_EXCEED \ + LIBSPDM_STATUS_CONSTRUCT(LIBSPDM_SEVERITY_ERROR, LIBSPDM_SOURCE_CORE, 0x000e) + +/* Decrypt error from peer. */ +#define LIBSPDM_STATUS_SESSION_MSG_ERROR \ + LIBSPDM_STATUS_CONSTRUCT(LIBSPDM_SEVERITY_ERROR, LIBSPDM_SOURCE_CORE, 0x000f) + +/* Unable to acquire resource. */ +#define LIBSPDM_STATUS_ACQUIRE_FAIL \ + LIBSPDM_STATUS_CONSTRUCT(LIBSPDM_SEVERITY_ERROR, LIBSPDM_SOURCE_CORE, 0x0010) + +/* Re-triable decrypt error from peer - must rollback to backup keys. */ +#define LIBSPDM_STATUS_SESSION_TRY_DISCARD_KEY_UPDATE \ + LIBSPDM_STATUS_CONSTRUCT(LIBSPDM_SEVERITY_ERROR, LIBSPDM_SOURCE_CORE, 0x0011) + +/* - Cryptography Errors - */ + +/* Generic failure originating from the cryptography module. */ +#define LIBSPDM_STATUS_CRYPTO_ERROR \ + LIBSPDM_STATUS_CONSTRUCT(LIBSPDM_SEVERITY_ERROR, LIBSPDM_SOURCE_CRYPTO, 0x0000) + +/* Verification of the provided signature digest, signature, or AEAD tag failed. */ +#define LIBSPDM_STATUS_VERIF_FAIL \ + LIBSPDM_STATUS_CONSTRUCT(LIBSPDM_SEVERITY_ERROR, LIBSPDM_SOURCE_CRYPTO, 0x0001) + +/* AEAD sequence number overflow. */ +#define LIBSPDM_STATUS_SEQUENCE_NUMBER_OVERFLOW \ + LIBSPDM_STATUS_CONSTRUCT(LIBSPDM_SEVERITY_ERROR, LIBSPDM_SOURCE_CRYPTO, 0x0002) + +/* - Certificate Parsing Errors - */ + +/* Certificate is malformed or does not comply to x.509 standard. */ +#define LIBSPDM_STATUS_INVALID_CERT \ + LIBSPDM_STATUS_CONSTRUCT(LIBSPDM_SEVERITY_ERROR, LIBSPDM_SOURCE_CERT_PARSE, 0x0000) + +/* - Transport Errors - */ + +/* Unable to send message to peer. */ +#define LIBSPDM_STATUS_SEND_FAIL \ + LIBSPDM_STATUS_CONSTRUCT(LIBSPDM_SEVERITY_ERROR, LIBSPDM_SOURCE_TRANSPORT, 0x0000) + +/* Unable to receive message from peer. */ +#define LIBSPDM_STATUS_RECEIVE_FAIL \ + LIBSPDM_STATUS_CONSTRUCT(LIBSPDM_SEVERITY_ERROR, LIBSPDM_SOURCE_TRANSPORT, 0x0001) + +/* - Measurement Collection Errors - */ + +/* Unable to collect measurement because of invalid index. */ +#define LIBSPDM_STATUS_MEAS_INVALID_INDEX \ + LIBSPDM_STATUS_CONSTRUCT(LIBSPDM_SEVERITY_ERROR, LIBSPDM_SOURCE_MEAS_COLLECT, 0x0000) + +/* Unable to collect measurement because of internal error. */ +#define LIBSPDM_STATUS_MEAS_INTERNAL_ERROR \ + LIBSPDM_STATUS_CONSTRUCT(LIBSPDM_SEVERITY_ERROR, LIBSPDM_SOURCE_MEAS_COLLECT, 0x0001) + +/* - Random Number Generation Errors - */ + +/* Unable to produce random number due to lack of entropy. */ +#define LIBSPDM_STATUS_LOW_ENTROPY \ + LIBSPDM_STATUS_CONSTRUCT(LIBSPDM_SEVERITY_ERROR, LIBSPDM_SOURCE_RNG, 0x0000) + +#endif diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/libraries/libspdm/2.3.1/include/library/spdm_secured_message_lib.h nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/libraries/libspdm/2.3.1/include/library/spdm_secured_message_lib.h --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/libraries/libspdm/2.3.1/include/library/spdm_secured_message_lib.h 1970-01-01 00:00:00.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/libraries/libspdm/2.3.1/include/library/spdm_secured_message_lib.h 2024-03-05 22:14:14.000000000 +0000 @@ -0,0 +1,650 @@ +/** + * Copyright Notice: + * Copyright 2021-2022 DMTF. All rights reserved. + * License: BSD 3-Clause License. For full text see link: https://github.com/DMTF/libspdm/blob/main/LICENSE.md + **/ + +#ifndef SPDM_SECURED_MESSAGE_LIB_H +#define SPDM_SECURED_MESSAGE_LIB_H + +#include "hal/base.h" +#include "industry_standard/spdm.h" +#include "industry_standard/spdm_secured_message.h" +#include "library/spdm_return_status.h" + +typedef enum { + LIBSPDM_SESSION_TYPE_NONE, + LIBSPDM_SESSION_TYPE_MAC_ONLY, + LIBSPDM_SESSION_TYPE_ENC_MAC, + LIBSPDM_SESSION_TYPE_MAX +} libspdm_session_type_t; + +typedef enum { + /* Before send KEY_EXCHANGE/PSK_EXCHANGE or after END_SESSION */ + LIBSPDM_SESSION_STATE_NOT_STARTED, + + /* After send KEY_EXHCNAGE, before send FINISH */ + LIBSPDM_SESSION_STATE_HANDSHAKING, + + /* After send FINISH, before END_SESSION */ + LIBSPDM_SESSION_STATE_ESTABLISHED, + + /* MAX */ + LIBSPDM_SESSION_STATE_MAX +} libspdm_session_state_t; + +/** + * Return the size in bytes of a single SPDM secured message context. + * + * @return the size in bytes of a single SPDM secured message context. + **/ +size_t libspdm_secured_message_get_context_size(void); + +/** + * Initialize an SPDM secured message context. + * + * The size in bytes of the spdm_secured_message_context can be returned by libspdm_secured_message_get_context_size. + * + * @param spdm_secured_message_context A pointer to the SPDM secured message context. + */ +void libspdm_secured_message_init_context(void *spdm_secured_message_context); + +/** + * Set use_psk to an SPDM secured message context. + * + * @param spdm_secured_message_context A pointer to the SPDM secured message context. + * @param use_psk Indicate if the SPDM session use PSK. + */ +void libspdm_secured_message_set_use_psk(void *spdm_secured_message_context, bool use_psk); + +/** + * Set session_state to an SPDM secured message context. + * + * @param spdm_secured_message_context A pointer to the SPDM secured message context. + * @param session_state Indicate the SPDM session state. + */ +void libspdm_secured_message_set_session_state( + void *spdm_secured_message_context, + libspdm_session_state_t session_state); + +/** + * Return session_state of an SPDM secured message context. + * + * @param spdm_secured_message_context A pointer to the SPDM secured message context. + * + * @return the SPDM session state. + */ +libspdm_session_state_t +libspdm_secured_message_get_session_state(void *spdm_secured_message_context); + +/** + * Set session_type to an SPDM secured message context. + * + * @param spdm_secured_message_context A pointer to the SPDM secured message context. + * @param session_type Indicate the SPDM session type. + */ +void libspdm_secured_message_set_session_type(void *spdm_secured_message_context, + libspdm_session_type_t session_type); + +/** + * Set algorithm to an SPDM secured message context. + * + * @param spdm_secured_message_context A pointer to the SPDM secured message context. + * @param base_hash_algo Indicate the negotiated base_hash_algo for the SPDM session. + * @param dhe_named_group Indicate the negotiated dhe_named_group for the SPDM session. + * @param aead_cipher_suite Indicate the negotiated aead_cipher_suite for the SPDM session. + * @param key_schedule Indicate the negotiated key_schedule for the SPDM session. + */ +void libspdm_secured_message_set_algorithms(void *spdm_secured_message_context, + const spdm_version_number_t version, + const spdm_version_number_t secured_message_version, + uint32_t base_hash_algo, + uint16_t dhe_named_group, + uint16_t aead_cipher_suite, + uint16_t key_schedule); + +/** + * Set the psk_hint to an SPDM secured message context. + * + * @param spdm_secured_message_context A pointer to the SPDM secured message context. + * @param psk_hint Indicate the PSK hint. + * @param psk_hint_size The size in bytes of the PSK hint. + */ +void libspdm_secured_message_set_psk_hint(void *spdm_secured_message_context, + const void *psk_hint, + size_t psk_hint_size); + +/** + * Import the DHE Secret to an SPDM secured message context. + * + * @param spdm_secured_message_context A pointer to the SPDM secured message context. + * @param dhe_secret Indicate the DHE secret. + * @param dhe_secret_size The size in bytes of the DHE secret. + * + * @retval RETURN_SUCCESS DHE Secret is imported. + */ +bool +libspdm_secured_message_import_dhe_secret(void *spdm_secured_message_context, + const void *dhe_secret, + size_t dhe_secret_size); + +/** + * Export the Export Master Secret from an SPDM secured message context. + * + * The size of the Export Master Secret is the size of the digest of the negotiated hash algorithm. + * If the size of the destination buffer is less than the size of the Export Master Secret then + * the first export_master_secret_size bytes are copied. + * + * @param spdm_secured_message_context A pointer to the SPDM secured message context. + * @param export_master_secret A pointer to the buffer to store the export_master_secret. + * @param export_master_secret_size On input, the size of the destination buffer. + * On output, the lesser of either the size of the destination + * buffer or the size of the Export Master Secret. + */ +bool libspdm_secured_message_export_master_secret( + void *spdm_secured_message_context, void *export_master_secret, + size_t *export_master_secret_size); + +/** + * Erase the Export Master Secret from an SPDM secured message context. This is typically called + * after libspdm_secured_message_export_master_secret(). + * + * @param spdm_secured_message_context A pointer to the SPDM secured message context. + */ +void libspdm_secured_message_clear_export_master_secret(void *spdm_secured_message_context); + +#define LIBSPDM_SECURE_SESSION_KEYS_STRUCT_VERSION 1 + +#pragma pack(1) +typedef struct { + uint32_t version; + uint32_t aead_key_size; + uint32_t aead_iv_size; + /* uint8_t request_data_encryption_key[aead_key_size]; + * uint8_t request_data_salt[aead_iv_size]; + * uint64_t request_data_sequence_number; + * uint8_t response_data_encryption_key[aead_key_size]; + * uint8_t response_data_salt[aead_iv_size]; + * uint64_t response_data_sequence_number;*/ +} libspdm_secure_session_keys_struct_t; +#pragma pack() + +/** + * Export the session_keys from an SPDM secured message context. + * + * @param spdm_secured_message_context A pointer to the SPDM secured message context. + * @param session_keys Indicate the buffer to store the session_keys in libspdm_secure_session_keys_struct_t. + * @param session_keys_size The size in bytes of the session_keys in libspdm_secure_session_keys_struct_t. + * + * @retval RETURN_SUCCESS session_keys are exported. + */ +bool libspdm_secured_message_export_session_keys(void *spdm_secured_message_context, + void *session_keys, + size_t *session_keys_size); + +/** + * Import the session_keys from an SPDM secured message context. + * + * @param spdm_secured_message_context A pointer to the SPDM secured message context. + * @param session_keys Indicate the buffer to store the session_keys in libspdm_secure_session_keys_struct_t. + * @param session_keys_size The size in bytes of the session_keys in libspdm_secure_session_keys_struct_t. + * + * @retval RETURN_SUCCESS session_keys are imported. + */ +bool libspdm_secured_message_import_session_keys(void *spdm_secured_message_context, + const void *session_keys, + size_t session_keys_size); + +/** + * Allocates and Initializes one Diffie-Hellman Ephemeral (DHE) context for subsequent use, + * based upon negotiated DHE algorithm. + * + * @param dhe_named_group SPDM dhe_named_group + * @param is_initiator if the caller is initiator. + * true: initiator + * false: not an initiator + * + * @return Pointer to the Diffie-Hellman context that has been initialized. + **/ +void *libspdm_secured_message_dhe_new(spdm_version_number_t spdm_version, + uint16_t dhe_named_group, bool is_initiator); + +/** + * Release the specified DHE context, + * based upon negotiated DHE algorithm. + * + * @param dhe_named_group SPDM dhe_named_group + * @param dhe_context Pointer to the DHE context to be released. + **/ +void libspdm_secured_message_dhe_free(uint16_t dhe_named_group, void *dhe_context); + +/** + * Generates DHE public key, + * based upon negotiated DHE algorithm. + * + * This function generates random secret exponent, and computes the public key, which is + * returned via parameter public_key and public_key_size. DH context is updated accordingly. + * If the public_key buffer is too small to hold the public key, false is returned and + * public_key_size is set to the required buffer size to obtain the public key. + * + * @param dhe_named_group SPDM dhe_named_group + * @param dhe_context Pointer to the DHE context. + * @param public_key Pointer to the buffer to receive generated public key. + * @param public_key_size On input, the size of public_key buffer in bytes. + * On output, the size of data returned in public_key buffer in bytes. + * + * @retval true DHE public key generation succeeded. + * @retval false DHE public key generation failed. + * @retval false public_key_size is not large enough. + **/ +bool libspdm_secured_message_dhe_generate_key(uint16_t dhe_named_group, + void *dhe_context, + uint8_t *public_key, + size_t *public_key_size); + +/** + * Computes exchanged common key, + * based upon negotiated DHE algorithm. + * + * Given peer's public key, this function computes the exchanged common key, based on its own + * context including value of prime modulus and random secret exponent. + * + * @param dhe_named_group SPDM dhe_named_group + * @param dhe_context Pointer to the DHE context. + * @param peer_public_key Pointer to the peer's public key. + * @param peer_public_key_size size of peer's public key in bytes. + * @param spdm_secured_message_context A pointer to the SPDM secured message context. + * + * @retval true DHE exchanged key generation succeeded. + * @retval false DHE exchanged key generation failed. + * @retval false key_size is not large enough. + **/ +bool libspdm_secured_message_dhe_compute_key( + uint16_t dhe_named_group, void *dhe_context, + const uint8_t *peer_public, size_t peer_public_size, + void *spdm_secured_message_context); + +/** + * This function is used to clear handshake secret. + * + * @param spdm_secured_message_context A pointer to the SPDM secured message context. + **/ +void libspdm_clear_handshake_secret(void *spdm_secured_message_context); + +/** + * This function is used to clear the master secret; + * + * @param spdm_secured_message_context A pointer to the SPDM secured message context. + **/ +void libspdm_clear_master_secret(void *spdm_secured_message_context); + +/** + * Allocates and initializes one HMAC context for subsequent use, with request_finished_key. + * + * @param spdm_secured_message_context A pointer to the SPDM secured message context. + * + * @return Pointer to the HMAC context that has been initialized. + **/ +void *libspdm_hmac_new_with_request_finished_key(void *spdm_secured_message_context); + +/** + * Release the specified HMAC context, with request_finished_key. + * + * @param spdm_secured_message_context A pointer to the SPDM secured message context. + * @param hmac_ctx Pointer to the HMAC context to be released. + **/ +void libspdm_hmac_free_with_request_finished_key( + void *spdm_secured_message_context, void *hmac_ctx); + +/** + * Set request_finished_key for subsequent use. It must be done before any + * calling to hmac_update(). + * + * @param spdm_secured_message_context A pointer to the SPDM secured message context. + * @param hmac_ctx Pointer to HMAC context. + * + * @retval true The key is set successfully. + * @retval false The key is set unsuccessfully. + **/ +bool libspdm_hmac_init_with_request_finished_key( + void *spdm_secured_message_context, void *hmac_ctx); + +/** + * Makes a copy of an existing HMAC context, with request_finished_key. + * + * @param spdm_secured_message_context A pointer to the SPDM secured message context. + * @param hmac_ctx Pointer to HMAC context being copied. + * @param new_hmac_ctx Pointer to new HMAC context. + * + * @retval true HMAC context copy succeeded. + * @retval false HMAC context copy failed. + **/ +bool libspdm_hmac_duplicate_with_request_finished_key( + void *spdm_secured_message_context, + const void *hmac_ctx, void *new_hmac_ctx); + +/** + * Digests the input data and updates HMAC context, with request_finished_key. + * + * @param spdm_secured_message_context A pointer to the SPDM secured message context. + * @param hmac_ctx Pointer to HMAC context being copied. + * @param data Pointer to the buffer containing the data to be digested. + * @param data_size size of data buffer in bytes. + * + * @retval true HMAC data digest succeeded. + * @retval false HMAC data digest failed. + **/ +bool libspdm_hmac_update_with_request_finished_key( + void *spdm_secured_message_context, + void *hmac_ctx, const void *data, + size_t data_size); + +/** + * Completes computation of the HMAC digest value, with request_finished_key. + * + * @param spdm_secured_message_context A pointer to the SPDM secured message context. + * @param hmac_ctx Pointer to HMAC context being copied. + * @param hmac_value Pointer to a buffer that receives the HMAC digest value + * + * @retval true HMAC data digest succeeded. + * @retval false HMAC data digest failed. + **/ +bool libspdm_hmac_final_with_request_finished_key( + void *spdm_secured_message_context, + void *hmac_ctx, uint8_t *hmac_value); + +/** + * Computes the HMAC of a input data buffer, with request_finished_key. + * + * @param spdm_secured_message_context A pointer to the SPDM secured message context. + * @param data Pointer to the buffer containing the data to be HMACed. + * @param data_size size of data buffer in bytes. + * @param hash_value Pointer to a buffer that receives the HMAC value. + * + * @retval true HMAC computation succeeded. + * @retval false HMAC computation failed. + **/ +bool libspdm_hmac_all_with_request_finished_key(void *spdm_secured_message_context, + const void *data, size_t data_size, + uint8_t *hmac_value); + +/** + * Allocates and initializes one HMAC context for subsequent use, with response_finished_key. + * + * @param spdm_secured_message_context A pointer to the SPDM secured message context. + * + * @return Pointer to the HMAC context that has been initialized. + **/ +void *libspdm_hmac_new_with_response_finished_key(void *spdm_secured_message_context); + +/** + * Release the specified HMAC context, with response_finished_key. + * + * @param spdm_secured_message_context A pointer to the SPDM secured message context. + * @param hmac_ctx Pointer to the HMAC context to be released. + **/ +void libspdm_hmac_free_with_response_finished_key( + void *spdm_secured_message_context, void *hmac_ctx); + +/** + * Set response_finished_key for subsequent use. It must be done before any + * calling to hmac_update(). + * + * @param spdm_secured_message_context A pointer to the SPDM secured message context. + * @param hmac_ctx Pointer to HMAC context. + * + * @retval true The key is set successfully. + * @retval false The key is set unsuccessfully. + **/ +bool libspdm_hmac_init_with_response_finished_key( + void *spdm_secured_message_context, void *hmac_ctx); + +/** + * Makes a copy of an existing HMAC context, with response_finished_key. + * + * @param spdm_secured_message_context A pointer to the SPDM secured message context. + * @param hmac_ctx Pointer to HMAC context being copied. + * @param new_hmac_ctx Pointer to new HMAC context. + * + * @retval true HMAC context copy succeeded. + * @retval false HMAC context copy failed. + **/ +bool libspdm_hmac_duplicate_with_response_finished_key( + void *spdm_secured_message_context, + const void *hmac_ctx, void *new_hmac_ctx); + +/** + * Digests the input data and updates HMAC context, with response_finished_key. + * + * @param spdm_secured_message_context A pointer to the SPDM secured message context. + * @param hmac_ctx Pointer to HMAC context being copied. + * @param data Pointer to the buffer containing the data to be digested. + * @param data_size size of data buffer in bytes. + * + * @retval true HMAC data digest succeeded. + * @retval false HMAC data digest failed. + **/ +bool libspdm_hmac_update_with_response_finished_key( + void *spdm_secured_message_context, + void *hmac_ctx, const void *data, + size_t data_size); + +/** + * Completes computation of the HMAC digest value, with response_finished_key. + * + * @param spdm_secured_message_context A pointer to the SPDM secured message context. + * @param hmac_ctx Pointer to HMAC context being copied. + * @param hmac_value Pointer to a buffer that receives the HMAC digest value + * + * @retval true HMAC data digest succeeded. + * @retval false HMAC data digest failed. + **/ +bool libspdm_hmac_final_with_response_finished_key( + void *spdm_secured_message_context, + void *hmac_ctx, uint8_t *hmac_value); + +/** + * Computes the HMAC of a input data buffer, with response_finished_key. + * + * @param spdm_secured_message_context A pointer to the SPDM secured message context. + * @param data Pointer to the buffer containing the data to be HMACed. + * @param data_size size of data buffer in bytes. + * @param hash_value Pointer to a buffer that receives the HMAC value. + * + * @retval true HMAC computation succeeded. + * @retval false HMAC computation failed. + **/ +bool libspdm_hmac_all_with_response_finished_key( + void *spdm_secured_message_context, const void *data, + size_t data_size, uint8_t *hmac_value); + +/** + * This function concatenates binary data, which is used as info in HKDF expand later. + * + * @param label An ascii string label for the libspdm_bin_concat. + * @param label_size The size in bytes of the ASCII string label, not including NULL terminator. + * @param context A pre-defined hash value as the context for the libspdm_bin_concat. + * @param length 16 bits length for the libspdm_bin_concat. + * @param hash_size The size in bytes of the context hash. + * @param out_bin The buffer to store the output binary. + * @param out_bin_size The size in bytes for the out_bin. + **/ +void libspdm_bin_concat(spdm_version_number_t spdm_version, + const char *label, size_t label_size, + const uint8_t *context, uint16_t length, + size_t hash_size, uint8_t *out_bin, + size_t *out_bin_size); + +/** + * This function generates SPDM HandshakeKey for a session. + * + * @param spdm_secured_message_context A pointer to the SPDM secured message context. + * @param th1_hash_data th1 hash + * + * @retval RETURN_SUCCESS SPDM HandshakeKey for a session is generated. + **/ +bool libspdm_generate_session_handshake_key(void *spdm_secured_message_context, + const uint8_t *th1_hash_data); + +/** + * This function generates SPDM DataKey for a session. + * + * @param spdm_secured_message_context A pointer to the SPDM secured message context. + * @param th2_hash_data th2 hash + * + * @retval RETURN_SUCCESS SPDM DataKey for a session is generated. + **/ +bool libspdm_generate_session_data_key(void *spdm_secured_message_context, + const uint8_t *th2_hash_data); + +typedef enum { + LIBSPDM_KEY_UPDATE_OPERATION_CREATE_UPDATE, + LIBSPDM_KEY_UPDATE_OPERATION_COMMIT_UPDATE, + LIBSPDM_KEY_UPDATE_OPERATION_DISCARD_UPDATE, + LIBSPDM_KEY_UPDATE_OPERATION_MAX +} libspdm_key_update_operation_t; + +typedef enum { + LIBSPDM_KEY_UPDATE_ACTION_REQUESTER, + LIBSPDM_KEY_UPDATE_ACTION_RESPONDER, + LIBSPDM_KEY_UPDATE_ACTION_MAX +} libspdm_key_update_action_t; + +/** + * This function creates the updates of SPDM DataKey for a session. + * + * @param spdm_secured_message_context A pointer to the SPDM secured message context. + * @param action Indicate of the key update action. + * + * @retval RETURN_SUCCESS SPDM DataKey update is created. + **/ +bool libspdm_create_update_session_data_key(void *spdm_secured_message_context, + libspdm_key_update_action_t action); + +/** + * This function activates the update of SPDM DataKey for a session. + * + * @param spdm_secured_message_context A pointer to the SPDM secured message context. + * @param action Indicate of the key update action. + * @param use_new_key Indicate if the new key should be used. + * + * @retval RETURN_SUCCESS SPDM DataKey update is activated. + **/ +bool libspdm_activate_update_session_data_key(void *spdm_secured_message_context, + libspdm_key_update_action_t action, + bool use_new_key); + +/** + * Get sequence number in an SPDM secure message. + * + * This value is transport layer specific. + * + * @param sequence_number The current sequence number used to encode or decode message. + * @param sequence_number_buffer A buffer to hold the sequence number output used in the secured message. + * The size in byte of the output buffer shall be 8. + * + * @return size in byte of the sequence_number_buffer. + * It shall be no greater than 8. + * 0 means no sequence number is required. + **/ +typedef uint8_t (*libspdm_secured_message_get_sequence_number_func)( + uint64_t sequence_number, uint8_t *sequence_number_buffer); + +/** + * Return max random number count in an SPDM secure message. + * + * This value is transport layer specific. + * + * @return Max random number count in an SPDM secured message. + * 0 means no randum number is required. + **/ +typedef uint32_t (*libspdm_secured_message_get_max_random_number_count_func)(void); + +#define SPDM_SECURED_MESSAGE_CALLBACKS_VERSION 1 + +typedef struct { + uint32_t version; + libspdm_secured_message_get_sequence_number_func get_sequence_number; + libspdm_secured_message_get_max_random_number_count_func get_max_random_number_count; +} libspdm_secured_message_callbacks_t; + +typedef struct { + uint8_t error_code; + uint32_t session_id; +} libspdm_error_struct_t; + +/** + * Encode an application message to a secured message. + * + * @param spdm_secured_message_context A pointer to the SPDM secured message context. + * @param session_id The session ID of the SPDM session. + * @param is_requester Indicates if it is a requester message. + * @param app_message_size size in bytes of the application message data buffer. + * @param app_message A pointer to a source buffer to store the application message. + * It shall point to the scratch buffer in spdm_context. + * On input, the app_message pointer shall point to a big enough buffer. + * Before app_message, there is room for spdm_secured_message_cipher_header_t. + * After (app_message + app_message_size), there is room for random bytes. + * @param secured_message_size size in bytes of the secured message data buffer. + * @param secured_message A pointer to a destination buffer to store the secured message. + * It shall point to the acquired sender buffer. + * @param spdm_secured_message_callbacks A pointer to a secured message callback functions structure. + * + * @retval RETURN_SUCCESS The application message is encoded successfully. + * @retval RETURN_INVALID_PARAMETER The message is NULL or the message_size is zero. + **/ +libspdm_return_t libspdm_encode_secured_message( + void *spdm_secured_message_context, uint32_t session_id, + bool is_requester, size_t app_message_size, + void *app_message, size_t *secured_message_size, + void *secured_message, + const libspdm_secured_message_callbacks_t *spdm_secured_message_callbacks); + +/** + * Decode an application message from a secured message. + * + * @param spdm_secured_message_context A pointer to the SPDM secured message context. + * @param session_id The session ID of the SPDM session. + * @param is_requester Indicates if it is a requester message. + * @param secured_message_size size in bytes of the secured message data buffer. + * @param secured_message A pointer to a source buffer to store the secured message. + * It shall point to the acquired receiver buffer. + * @param app_message_size size in bytes of the application message data buffer. + * @param app_message A pointer to a destination buffer to store the application message. + * It shall point to the scratch buffer in spdm_context. + * On input, the app_message pointer shall point to a big enough buffer to hold the decrypted message + * On output, the app_message pointer shall be inside of [app_message, app_message + app_message_size] + * @param spdm_secured_message_callbacks A pointer to a secured message callback functions structure. + * + * @retval RETURN_SUCCESS The application message is decoded successfully. + * @retval RETURN_INVALID_PARAMETER The message is NULL or the message_size is zero. + * @retval RETURN_UNSUPPORTED The secured_message is unsupported. + **/ +libspdm_return_t libspdm_decode_secured_message( + void *spdm_secured_message_context, uint32_t session_id, + bool is_requester, size_t secured_message_size, + void *secured_message, size_t *app_message_size, + void **app_message, + const libspdm_secured_message_callbacks_t *spdm_secured_message_callbacks); + +/** + * Get the last SPDM error struct of an SPDM secured message context. + * + * @param spdm_secured_message_context A pointer to the SPDM secured message context. + * @param last_spdm_error Last SPDM error struct of an SPDM secured message context. + */ +void libspdm_secured_message_get_last_spdm_error_struct( + void *spdm_secured_message_context, + libspdm_error_struct_t *last_spdm_error); + +/** + * Set the last SPDM error struct of an SPDM secured message context. + * + * @param spdm_secured_message_context A pointer to the SPDM secured message context. + * @param last_spdm_error Last SPDM error struct of an SPDM secured message context. + */ +void libspdm_secured_message_set_last_spdm_error_struct( + void *spdm_secured_message_context, + const libspdm_error_struct_t *last_spdm_error); + +#endif /* SPDM_SECURED_MESSAGE_LIB_H */ diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/libraries/libspdm/2.3.1/library/spdm_common_lib/libspdm_com_context_data.c nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/libraries/libspdm/2.3.1/library/spdm_common_lib/libspdm_com_context_data.c --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/libraries/libspdm/2.3.1/library/spdm_common_lib/libspdm_com_context_data.c 1970-01-01 00:00:00.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/libraries/libspdm/2.3.1/library/spdm_common_lib/libspdm_com_context_data.c 2024-03-05 22:14:14.000000000 +0000 @@ -0,0 +1,2420 @@ +/** + * Copyright Notice: + * Copyright 2021-2022 DMTF. All rights reserved. + * License: BSD 3-Clause License. For full text see link: https://github.com/DMTF/libspdm/blob/main/LICENSE.md + **/ + +#include "internal/libspdm_common_lib.h" +#include "internal/libspdm_secured_message_lib.h" + +/** + * Returns if an SPDM data_type requires session info. + * + * @param data_type SPDM data type. + * + * @retval true session info is required. + * @retval false session info is not required. + **/ +static bool need_session_info_for_data(libspdm_data_type_t data_type) +{ + switch (data_type) { + case LIBSPDM_DATA_SESSION_USE_PSK: + case LIBSPDM_DATA_SESSION_MUT_AUTH_REQUESTED: + case LIBSPDM_DATA_SESSION_END_SESSION_ATTRIBUTES: + case LIBSPDM_DATA_SESSION_POLICY: + return true; + default: + return false; + } +} + +/** + * Set an SPDM context data. + * + * @param spdm_context A pointer to the SPDM context. + * @param data_type Type of the SPDM context data. + * @param parameter Type specific parameter of the SPDM context data. + * @param data A pointer to the SPDM context data. + * @param data_size size in bytes of the SPDM context data. + * + * @retval RETURN_SUCCESS The SPDM context data is set successfully. + * @retval RETURN_INVALID_PARAMETER The data is NULL or the data_type is zero. + * @retval RETURN_UNSUPPORTED The data_type is unsupported. + * @retval RETURN_ACCESS_DENIED The data_type cannot be set. + * @retval RETURN_NOT_READY data is not ready to set. + **/ +libspdm_return_t libspdm_set_data(void *context, libspdm_data_type_t data_type, + const libspdm_data_parameter_t *parameter, void *data, + size_t data_size) +{ + libspdm_context_t *spdm_context; + uint32_t session_id; + libspdm_session_info_t *session_info; + uint8_t slot_id; + uint8_t mut_auth_requested; + uint8_t root_cert_index; +#if !(LIBSPDM_RECORD_TRANSCRIPT_DATA_SUPPORT) + bool status; +#endif + + if (context == NULL || data == NULL || data_type >= LIBSPDM_DATA_MAX) { + return LIBSPDM_STATUS_INVALID_PARAMETER; + } + + spdm_context = context; + + if (need_session_info_for_data(data_type)) { + if (parameter->location != LIBSPDM_DATA_LOCATION_SESSION) { + return LIBSPDM_STATUS_INVALID_PARAMETER; + } + session_id = *(const uint32_t *)parameter->additional_data; + session_info = libspdm_get_session_info_via_session_id(spdm_context, session_id); + if (session_info == NULL) { + return LIBSPDM_STATUS_INVALID_PARAMETER; + } + } else { + session_info = NULL; + } + + switch (data_type) { + case LIBSPDM_DATA_SPDM_VERSION: + LIBSPDM_ASSERT (data_size <= sizeof(spdm_version_number_t) * SPDM_MAX_VERSION_COUNT); + if (parameter->location == LIBSPDM_DATA_LOCATION_CONNECTION) { + /* Only have one connected version */ + LIBSPDM_ASSERT (data_size == sizeof(spdm_version_number_t)); + libspdm_copy_mem(&(spdm_context->connection_info.version), + sizeof(spdm_context->connection_info.version), + data, + sizeof(spdm_version_number_t)); + } else { + spdm_context->local_context.version.spdm_version_count = + (uint8_t)(data_size / sizeof(spdm_version_number_t)); + libspdm_copy_mem(spdm_context->local_context.version.spdm_version, + sizeof(spdm_context->local_context.version.spdm_version), + data, + spdm_context->local_context.version.spdm_version_count * + sizeof(spdm_version_number_t)); + } + break; + case LIBSPDM_DATA_SECURED_MESSAGE_VERSION: + LIBSPDM_ASSERT (data_size <= sizeof(spdm_version_number_t) * SPDM_MAX_VERSION_COUNT); + if (parameter->location == LIBSPDM_DATA_LOCATION_CONNECTION) { + /* Only have one connected version */ + LIBSPDM_ASSERT (data_size == sizeof(spdm_version_number_t)); + libspdm_copy_mem(&(spdm_context->connection_info.secured_message_version), + sizeof(spdm_context->connection_info.secured_message_version), + data, + sizeof(spdm_version_number_t)); + } else { + spdm_context->local_context.secured_message_version + .spdm_version_count = (uint8_t)(data_size / sizeof(spdm_version_number_t)); + libspdm_copy_mem(spdm_context->local_context + .secured_message_version.spdm_version, + sizeof(spdm_context->local_context + .secured_message_version.spdm_version), + data, + spdm_context->local_context.secured_message_version. + spdm_version_count * sizeof(spdm_version_number_t)); + } + break; + case LIBSPDM_DATA_CAPABILITY_FLAGS: + if (data_size != sizeof(uint32_t)) { + return LIBSPDM_STATUS_INVALID_PARAMETER; + } + + #if !(LIBSPDM_ENABLE_CAPABILITY_CERT_CAP) + LIBSPDM_ASSERT(((*(uint32_t *)data) & SPDM_GET_CAPABILITIES_RESPONSE_FLAGS_CERT_CAP) == 0); + #endif /* !LIBSPDM_ENABLE_CAPABILITY_CERT_CAP */ + + #if !(LIBSPDM_ENABLE_CAPABILITY_CHAL_CAP) + LIBSPDM_ASSERT(((*(uint32_t *)data) & SPDM_GET_CAPABILITIES_RESPONSE_FLAGS_CHAL_CAP) == 0); + #endif /* !LIBSPDM_ENABLE_CAPABILITY_CHAL_CAP */ + + #if !(LIBSPDM_ENABLE_CAPABILITY_MEAS_CAP) + LIBSPDM_ASSERT(((*(uint32_t *)data) & SPDM_GET_CAPABILITIES_RESPONSE_FLAGS_MEAS_CAP) == 0); + #endif /* !LIBSPDM_ENABLE_CAPABILITY_MEAS_CAP */ + + #if !(LIBSPDM_ENABLE_CAPABILITY_KEY_EX_CAP) + LIBSPDM_ASSERT(((*(uint32_t *)data) & SPDM_GET_CAPABILITIES_RESPONSE_FLAGS_KEY_EX_CAP) == + 0); + #endif /* !LIBSPDM_ENABLE_CAPABILITY_KEY_EX_CAP */ + + #if !(LIBSPDM_ENABLE_CAPABILITY_PSK_EX_CAP) + LIBSPDM_ASSERT(((*(uint32_t *)data) & SPDM_GET_CAPABILITIES_RESPONSE_FLAGS_PSK_CAP) == 0); + #endif /* !LIBSPDM_ENABLE_CAPABILITY_PSK_EX_CAP */ + + if (parameter->location == LIBSPDM_DATA_LOCATION_CONNECTION) { + spdm_context->connection_info.capability.flags = *(uint32_t *)data; + } else { + spdm_context->local_context.capability.flags = *(uint32_t *)data; + } + break; + case LIBSPDM_DATA_CAPABILITY_CT_EXPONENT: + if (data_size != sizeof(uint8_t)) { + return LIBSPDM_STATUS_INVALID_PARAMETER; + } + spdm_context->local_context.capability.ct_exponent = *(uint8_t *)data; + break; + case LIBSPDM_DATA_CAPABILITY_RTT_US: + if (data_size != sizeof(uint64_t)) { + return LIBSPDM_STATUS_INVALID_PARAMETER; + } + spdm_context->local_context.capability.rtt = *(uint64_t *)data; + break; + case LIBSPDM_DATA_CAPABILITY_DATA_TRANSFER_SIZE: + if (data_size != sizeof(uint32_t)) { + return LIBSPDM_STATUS_INVALID_PARAMETER; + } + /* Only allow set smaller value*/ + LIBSPDM_ASSERT (*(uint32_t *)data <= LIBSPDM_MAX_MESSAGE_BUFFER_SIZE); + spdm_context->local_context.capability.data_transfer_size = *(uint32_t *)data; + break; + case LIBSPDM_DATA_CAPABILITY_MAX_SPDM_MSG_SIZE: + if (data_size != sizeof(uint32_t)) { + return LIBSPDM_STATUS_INVALID_PARAMETER; + } + /* Only allow set smaller value. Need different value for CHUNK - TBD*/ + LIBSPDM_ASSERT (*(uint32_t *)data <= LIBSPDM_MAX_MESSAGE_BUFFER_SIZE); + spdm_context->local_context.capability.max_spdm_msg_size = *(uint32_t *)data; + break; + case LIBSPDM_DATA_MEASUREMENT_SPEC: + if (data_size != sizeof(uint8_t)) { + return LIBSPDM_STATUS_INVALID_PARAMETER; + } + if (parameter->location == LIBSPDM_DATA_LOCATION_CONNECTION) { + spdm_context->connection_info.algorithm.measurement_spec = *(uint8_t *)data; + } else { + spdm_context->local_context.algorithm.measurement_spec = *(uint8_t *)data; + } + break; + case LIBSPDM_DATA_MEASUREMENT_HASH_ALGO: + if (data_size != sizeof(uint32_t)) { + return LIBSPDM_STATUS_INVALID_PARAMETER; + } + if (parameter->location == LIBSPDM_DATA_LOCATION_CONNECTION) { + spdm_context->connection_info.algorithm.measurement_hash_algo = *(uint32_t *)data; + } else { + spdm_context->local_context.algorithm.measurement_hash_algo = *(uint32_t *)data; + } + break; + case LIBSPDM_DATA_BASE_ASYM_ALGO: + if (data_size != sizeof(uint32_t)) { + return LIBSPDM_STATUS_INVALID_PARAMETER; + } + if (parameter->location == LIBSPDM_DATA_LOCATION_CONNECTION) { + spdm_context->connection_info.algorithm.base_asym_algo = *(uint32_t *)data; + } else { + spdm_context->local_context.algorithm.base_asym_algo = *(uint32_t *)data; + } + break; + case LIBSPDM_DATA_BASE_HASH_ALGO: + if (data_size != sizeof(uint32_t)) { + return LIBSPDM_STATUS_INVALID_PARAMETER; + } + if (parameter->location == LIBSPDM_DATA_LOCATION_CONNECTION) { + spdm_context->connection_info.algorithm.base_hash_algo = *(uint32_t *)data; + } else { + spdm_context->local_context.algorithm.base_hash_algo = *(uint32_t *)data; + } + break; + case LIBSPDM_DATA_DHE_NAME_GROUP: + if (data_size != sizeof(uint16_t)) { + return LIBSPDM_STATUS_INVALID_PARAMETER; + } + if (parameter->location == LIBSPDM_DATA_LOCATION_CONNECTION) { + spdm_context->connection_info.algorithm.dhe_named_group = *(uint16_t *)data; + } else { + spdm_context->local_context.algorithm.dhe_named_group = *(uint16_t *)data; + } + break; + case LIBSPDM_DATA_AEAD_CIPHER_SUITE: + if (data_size != sizeof(uint16_t)) { + return LIBSPDM_STATUS_INVALID_PARAMETER; + } + if (parameter->location == LIBSPDM_DATA_LOCATION_CONNECTION) { + spdm_context->connection_info.algorithm.aead_cipher_suite = *(uint16_t *)data; + } else { + spdm_context->local_context.algorithm.aead_cipher_suite = *(uint16_t *)data; + } + break; + case LIBSPDM_DATA_REQ_BASE_ASYM_ALG: + if (data_size != sizeof(uint16_t)) { + return LIBSPDM_STATUS_INVALID_PARAMETER; + } + if (parameter->location == LIBSPDM_DATA_LOCATION_CONNECTION) { + spdm_context->connection_info.algorithm.req_base_asym_alg = *(uint16_t *)data; + } else { + spdm_context->local_context.algorithm.req_base_asym_alg = *(uint16_t *)data; + } + break; + case LIBSPDM_DATA_KEY_SCHEDULE: + if (data_size != sizeof(uint16_t)) { + return LIBSPDM_STATUS_INVALID_PARAMETER; + } + if (parameter->location == LIBSPDM_DATA_LOCATION_CONNECTION) { + spdm_context->connection_info.algorithm.key_schedule = *(uint16_t *)data; + } else { + spdm_context->local_context.algorithm.key_schedule = *(uint16_t *)data; + } + break; + case LIBSPDM_DATA_OTHER_PARAMS_SUPPORT: + if (data_size != sizeof(uint8_t)) { + return LIBSPDM_STATUS_INVALID_PARAMETER; + } + if (parameter->location == LIBSPDM_DATA_LOCATION_CONNECTION) { + spdm_context->connection_info.algorithm.other_params_support = *(uint8_t *)data; + } else { + spdm_context->local_context.algorithm.other_params_support = *(uint8_t *)data; + } + break; + case LIBSPDM_DATA_CONNECTION_STATE: + if (data_size != sizeof(uint32_t)) { + return LIBSPDM_STATUS_INVALID_PARAMETER; + } + spdm_context->connection_info.connection_state = *(uint32_t *)data; + break; + case LIBSPDM_DATA_RESPONSE_STATE: + if (data_size != sizeof(uint32_t)) { + return LIBSPDM_STATUS_INVALID_PARAMETER; + } + spdm_context->response_state = *(uint32_t *)data; + break; + case LIBSPDM_DATA_PEER_PUBLIC_ROOT_CERT: + root_cert_index = 0; + while (spdm_context->local_context.peer_root_cert_provision[root_cert_index] != NULL) { + root_cert_index++; + if (root_cert_index >= LIBSPDM_MAX_ROOT_CERT_SUPPORT) { + return LIBSPDM_STATUS_BUFFER_FULL; + } + } + spdm_context->local_context.peer_root_cert_provision_size[root_cert_index] = data_size; + spdm_context->local_context.peer_root_cert_provision[root_cert_index] = data; + break; + case LIBSPDM_DATA_PEER_PUBLIC_CERT_CHAIN: + spdm_context->local_context.peer_cert_chain_provision_size = data_size; + spdm_context->local_context.peer_cert_chain_provision = data; + break; + case LIBSPDM_DATA_LOCAL_PUBLIC_CERT_CHAIN: + slot_id = parameter->additional_data[0]; + if (slot_id >= SPDM_MAX_SLOT_COUNT) { + return LIBSPDM_STATUS_INVALID_PARAMETER; + } + spdm_context->local_context.local_cert_chain_provision_size[slot_id] = data_size; + spdm_context->local_context.local_cert_chain_provision[slot_id] = data; + break; + case LIBSPDM_DATA_LOCAL_PUBLIC_CERT_CHAIN_DEFAULT_SLOT_ID: + if (data_size != sizeof(uint8_t)) { + return LIBSPDM_STATUS_INVALID_PARAMETER; + } + if (*(uint8_t *)data >= SPDM_MAX_SLOT_COUNT) { + return LIBSPDM_STATUS_INVALID_PARAMETER; + } + spdm_context->local_context.provisioned_slot_id = *(uint8_t *)data; + break; + case LIBSPDM_DATA_LOCAL_USED_CERT_CHAIN_BUFFER: + if (data_size > LIBSPDM_MAX_CERT_CHAIN_SIZE) { + return LIBSPDM_STATUS_BUFFER_FULL; + } + spdm_context->connection_info.local_used_cert_chain_buffer_size = data_size; + spdm_context->connection_info.local_used_cert_chain_buffer = data; + break; + case LIBSPDM_DATA_PEER_USED_CERT_CHAIN_BUFFER: + slot_id = parameter->additional_data[0]; + if (slot_id >= SPDM_MAX_SLOT_COUNT) { + return LIBSPDM_STATUS_INVALID_PARAMETER; + } + if (data_size > LIBSPDM_MAX_CERT_CHAIN_SIZE) { + return LIBSPDM_STATUS_BUFFER_FULL; + } + spdm_context->connection_info.peer_used_cert_chain_slot_id = slot_id; +#if LIBSPDM_RECORD_TRANSCRIPT_DATA_SUPPORT + spdm_context->connection_info.peer_used_cert_chain[slot_id].buffer_size = data_size; + libspdm_copy_mem(spdm_context->connection_info.peer_used_cert_chain[slot_id].buffer, + sizeof(spdm_context->connection_info.peer_used_cert_chain[slot_id].buffer), + data, data_size); +#else + status = libspdm_hash_all( + spdm_context->connection_info.algorithm.base_hash_algo, + data, data_size, + spdm_context->connection_info.peer_used_cert_chain[slot_id].buffer_hash); + if (!status) { + return LIBSPDM_STATUS_CRYPTO_ERROR; + } + + spdm_context->connection_info.peer_used_cert_chain[slot_id].buffer_hash_size = + libspdm_get_hash_size(spdm_context->connection_info.algorithm.base_hash_algo); + + status = false; +#if (LIBSPDM_RSA_SSA_SUPPORT) || (LIBSPDM_RSA_PSS_SUPPORT) + if (!status) { + status = libspdm_rsa_get_public_key_from_x509( + data, data_size, + &spdm_context->connection_info.peer_used_cert_chain[slot_id].leaf_cert_public_key); + } +#endif +#if LIBSPDM_ECDSA_SUPPORT + if (!status) { + status = libspdm_ec_get_public_key_from_x509( + data, data_size, + &spdm_context->connection_info.peer_used_cert_chain[slot_id].leaf_cert_public_key); + } +#endif +#if (LIBSPDM_EDDSA_ED25519_SUPPORT) || (LIBSPDM_EDDSA_ED448_SUPPORT) + if (!status) { + status = libspdm_ecd_get_public_key_from_x509( + data, data_size, + &spdm_context->connection_info.peer_used_cert_chain[slot_id].leaf_cert_public_key); + } +#endif +#if LIBSPDM_SM2_DSA_SUPPORT + if (!status) { + status = libspdm_sm2_get_public_key_from_x509( + data, data_size, + &spdm_context->connection_info.peer_used_cert_chain[slot_id].leaf_cert_public_key); + } +#endif + if (!status) { + return LIBSPDM_STATUS_INVALID_CERT; + } +#endif + break; + case LIBSPDM_DATA_BASIC_MUT_AUTH_REQUESTED: + if (data_size != sizeof(bool)) { + return LIBSPDM_STATUS_INVALID_PARAMETER; + } + mut_auth_requested = *(uint8_t *)data; + if (((mut_auth_requested != 0) && (mut_auth_requested != 1))) { + return LIBSPDM_STATUS_INVALID_PARAMETER; + } + spdm_context->local_context.basic_mut_auth_requested = mut_auth_requested; + spdm_context->encap_context.request_id = 0; + spdm_context->encap_context.req_slot_id = parameter->additional_data[0]; + break; + case LIBSPDM_DATA_MUT_AUTH_REQUESTED: + if (data_size != sizeof(uint8_t)) { + return LIBSPDM_STATUS_INVALID_PARAMETER; + } + mut_auth_requested = *(uint8_t *)data; + if (((mut_auth_requested != 0) && + (mut_auth_requested != + SPDM_KEY_EXCHANGE_RESPONSE_MUT_AUTH_REQUESTED) && + (mut_auth_requested != + SPDM_KEY_EXCHANGE_RESPONSE_MUT_AUTH_REQUESTED_WITH_ENCAP_REQUEST) && + (mut_auth_requested != + SPDM_KEY_EXCHANGE_RESPONSE_MUT_AUTH_REQUESTED_WITH_GET_DIGESTS))) { + return LIBSPDM_STATUS_INVALID_PARAMETER; + } + spdm_context->local_context.mut_auth_requested = mut_auth_requested; + spdm_context->encap_context.request_id = 0; + spdm_context->encap_context.req_slot_id = parameter->additional_data[0]; + break; + case LIBSPDM_DATA_HEARTBEAT_PERIOD: + if (data_size != sizeof(uint8_t)) { + return LIBSPDM_STATUS_INVALID_PARAMETER; + } + spdm_context->local_context.heartbeat_period = *(uint8_t *)data; + break; + case LIBSPDM_DATA_PSK_HINT: + if (data_size > LIBSPDM_PSK_MAX_HINT_LENGTH) { + return LIBSPDM_STATUS_INVALID_PARAMETER; + } + spdm_context->local_context.psk_hint_size = data_size; + spdm_context->local_context.psk_hint = data; + break; + case LIBSPDM_DATA_SESSION_USE_PSK: + if (data_size != sizeof(bool)) { + return LIBSPDM_STATUS_INVALID_PARAMETER; + } + session_info->use_psk = *(bool *)data; + break; + case LIBSPDM_DATA_SESSION_MUT_AUTH_REQUESTED: + if (data_size != sizeof(uint8_t)) { + return LIBSPDM_STATUS_INVALID_PARAMETER; + } + session_info->mut_auth_requested = *(uint8_t *)data; + break; + case LIBSPDM_DATA_SESSION_END_SESSION_ATTRIBUTES: + if (data_size != sizeof(uint8_t)) { + return LIBSPDM_STATUS_INVALID_PARAMETER; + } + session_info->end_session_attributes = *(uint8_t *)data; + break; + case LIBSPDM_DATA_SESSION_POLICY: + if (data_size != sizeof(uint8_t)) { + return LIBSPDM_STATUS_INVALID_PARAMETER; + } + session_info->session_policy = *(uint8_t *)data; + break; + case LIBSPDM_DATA_APP_CONTEXT_DATA: + if (data_size != sizeof(void *) || *(void **)data == NULL) { + return LIBSPDM_STATUS_INVALID_PARAMETER; + } + spdm_context->app_context_data_ptr = *(void **)data; + break; + case LIBSPDM_DATA_HANDLE_ERROR_RETURN_POLICY: + if (data_size != sizeof(uint8_t)) { + return LIBSPDM_STATUS_INVALID_PARAMETER; + } + spdm_context->handle_error_return_policy = *(uint8_t *)data; + break; + case LIBSPDM_DATA_VCA_CACHE: + if (data_size > sizeof(spdm_context->transcript.message_a.buffer)) { + return LIBSPDM_STATUS_INVALID_PARAMETER; + } + spdm_context->transcript.message_a.buffer_size = data_size; + libspdm_copy_mem(spdm_context->transcript.message_a.buffer, + sizeof(spdm_context->transcript.message_a.buffer), + data, data_size); + break; + case LIBSPDM_DATA_IS_REQUESTER: + if (data_size != sizeof(bool)) { + return LIBSPDM_STATUS_INVALID_PARAMETER; + } + spdm_context->local_context.is_requester = *(bool *)data; + break; + default: + return LIBSPDM_STATUS_UNSUPPORTED_CAP; + break; + } + + return LIBSPDM_STATUS_SUCCESS; +} + +/** + * Get an SPDM context data. + * + * @param spdm_context A pointer to the SPDM context. + * @param data_type Type of the SPDM context data. + * @param parameter Type specific parameter of the SPDM context data. + * @param data A pointer to the SPDM context data. + * @param data_size size in bytes of the SPDM context data. + * On input, it means the size in bytes of data buffer. + * On output, it means the size in bytes of copied data buffer if RETURN_SUCCESS, + * and means the size in bytes of desired data buffer if RETURN_BUFFER_TOO_SMALL. + * + * @retval RETURN_SUCCESS The SPDM context data is set successfully. + * @retval RETURN_INVALID_PARAMETER The data_size is NULL or the data is NULL and *data_size is not zero. + * @retval RETURN_UNSUPPORTED The data_type is unsupported. + * @retval RETURN_NOT_FOUND The data_type cannot be found. + * @retval RETURN_NOT_READY The data is not ready to return. + * @retval RETURN_BUFFER_TOO_SMALL The buffer is too small to hold the data. + **/ +libspdm_return_t libspdm_get_data(void *context, libspdm_data_type_t data_type, + const libspdm_data_parameter_t *parameter, + void *data, size_t *data_size) +{ + libspdm_context_t *spdm_context; + size_t target_data_size; + void *target_data; + uint32_t session_id; + libspdm_session_info_t *session_info; + size_t digest_size; + size_t digest_count; + size_t index; + + if (context == NULL || data == NULL || data_size == NULL || data_type >= LIBSPDM_DATA_MAX) { + return LIBSPDM_STATUS_INVALID_PARAMETER; + } + + spdm_context = context; + + if (need_session_info_for_data(data_type)) { + if (parameter->location != LIBSPDM_DATA_LOCATION_SESSION) { + return LIBSPDM_STATUS_INVALID_PARAMETER; + } + session_id = *(const uint32_t *)parameter->additional_data; + session_info = libspdm_get_session_info_via_session_id(spdm_context, session_id); + if (session_info == NULL) { + return LIBSPDM_STATUS_INVALID_PARAMETER; + } + } else { + session_info = NULL; + } + + switch (data_type) { + case LIBSPDM_DATA_SPDM_VERSION: + if (parameter->location != LIBSPDM_DATA_LOCATION_CONNECTION) { + return LIBSPDM_STATUS_INVALID_PARAMETER; + } + target_data_size = sizeof(spdm_version_number_t); + target_data = &(spdm_context->connection_info.version); + break; + case LIBSPDM_DATA_SECURED_MESSAGE_VERSION: + if (parameter->location != LIBSPDM_DATA_LOCATION_CONNECTION) { + return LIBSPDM_STATUS_INVALID_PARAMETER; + } + target_data_size = sizeof(spdm_version_number_t); + target_data = &(spdm_context->connection_info.secured_message_version); + break; + case LIBSPDM_DATA_CAPABILITY_FLAGS: + target_data_size = sizeof(uint32_t); + if (parameter->location == LIBSPDM_DATA_LOCATION_CONNECTION) { + target_data = &spdm_context->connection_info.capability.flags; + } else { + target_data = &spdm_context->local_context.capability.flags; + } + break; + case LIBSPDM_DATA_CAPABILITY_CT_EXPONENT: + target_data_size = sizeof(uint8_t); + if (parameter->location == LIBSPDM_DATA_LOCATION_CONNECTION) { + target_data = &spdm_context->connection_info.capability.ct_exponent; + } else { + target_data = &spdm_context->local_context.capability.ct_exponent; + } + break; + case LIBSPDM_DATA_CAPABILITY_DATA_TRANSFER_SIZE: + target_data_size = sizeof(uint32_t); + if (parameter->location == LIBSPDM_DATA_LOCATION_CONNECTION) { + target_data = &spdm_context->connection_info.capability.data_transfer_size; + } else { + target_data = &spdm_context->local_context.capability.data_transfer_size; + } + break; + case LIBSPDM_DATA_CAPABILITY_MAX_SPDM_MSG_SIZE: + target_data_size = sizeof(uint32_t); + if (parameter->location == LIBSPDM_DATA_LOCATION_CONNECTION) { + target_data = &spdm_context->connection_info.capability.max_spdm_msg_size; + } else { + target_data = &spdm_context->local_context.capability.max_spdm_msg_size; + } + break; + case LIBSPDM_DATA_MEASUREMENT_SPEC: + if (parameter->location != LIBSPDM_DATA_LOCATION_CONNECTION) { + return LIBSPDM_STATUS_INVALID_PARAMETER; + } + target_data_size = sizeof(uint8_t); + target_data = &spdm_context->connection_info.algorithm.measurement_spec; + break; + case LIBSPDM_DATA_MEASUREMENT_HASH_ALGO: + if (parameter->location != LIBSPDM_DATA_LOCATION_CONNECTION) { + return LIBSPDM_STATUS_INVALID_PARAMETER; + } + target_data_size = sizeof(uint32_t); + target_data = &spdm_context->connection_info.algorithm.measurement_hash_algo; + break; + case LIBSPDM_DATA_BASE_ASYM_ALGO: + if (parameter->location != LIBSPDM_DATA_LOCATION_CONNECTION) { + return LIBSPDM_STATUS_INVALID_PARAMETER; + } + target_data_size = sizeof(uint32_t); + target_data = &spdm_context->connection_info.algorithm.base_asym_algo; + break; + case LIBSPDM_DATA_BASE_HASH_ALGO: + if (parameter->location != LIBSPDM_DATA_LOCATION_CONNECTION) { + return LIBSPDM_STATUS_INVALID_PARAMETER; + } + target_data_size = sizeof(uint32_t); + target_data = &spdm_context->connection_info.algorithm.base_hash_algo; + break; + case LIBSPDM_DATA_DHE_NAME_GROUP: + if (parameter->location != LIBSPDM_DATA_LOCATION_CONNECTION) { + return LIBSPDM_STATUS_INVALID_PARAMETER; + } + target_data_size = sizeof(uint16_t); + target_data = &spdm_context->connection_info.algorithm.dhe_named_group; + break; + case LIBSPDM_DATA_AEAD_CIPHER_SUITE: + if (parameter->location != LIBSPDM_DATA_LOCATION_CONNECTION) { + return LIBSPDM_STATUS_INVALID_PARAMETER; + } + target_data_size = sizeof(uint16_t); + target_data = &spdm_context->connection_info.algorithm.aead_cipher_suite; + break; + case LIBSPDM_DATA_REQ_BASE_ASYM_ALG: + if (parameter->location != LIBSPDM_DATA_LOCATION_CONNECTION) { + return LIBSPDM_STATUS_INVALID_PARAMETER; + } + target_data_size = sizeof(uint16_t); + target_data = &spdm_context->connection_info.algorithm.req_base_asym_alg; + break; + case LIBSPDM_DATA_KEY_SCHEDULE: + if (parameter->location != LIBSPDM_DATA_LOCATION_CONNECTION) { + return LIBSPDM_STATUS_INVALID_PARAMETER; + } + target_data_size = sizeof(uint16_t); + target_data = &spdm_context->connection_info.algorithm.key_schedule; + break; + case LIBSPDM_DATA_OTHER_PARAMS_SUPPORT: + if (parameter->location != LIBSPDM_DATA_LOCATION_CONNECTION) { + return LIBSPDM_STATUS_INVALID_PARAMETER; + } + target_data_size = sizeof(uint8_t); + target_data = &spdm_context->connection_info.algorithm.other_params_support; + break; + case LIBSPDM_DATA_CONNECTION_STATE: + if (parameter->location != LIBSPDM_DATA_LOCATION_CONNECTION) { + return LIBSPDM_STATUS_INVALID_PARAMETER; + } + target_data_size = sizeof(uint32_t); + target_data = &spdm_context->connection_info.connection_state; + break; + case LIBSPDM_DATA_RESPONSE_STATE: + target_data_size = sizeof(uint32_t); + target_data = &spdm_context->response_state; + break; + case LIBSPDM_DATA_PEER_SLOT_MASK: + target_data_size = sizeof(uint8_t); + target_data = &spdm_context->connection_info.peer_digest_slot_mask; + break; + case LIBSPDM_DATA_PEER_TOTAL_DIGEST_BUFFER: + digest_count = 0; + for (index = 0; index < SPDM_MAX_SLOT_COUNT; index++) { + if (spdm_context->connection_info.peer_digest_slot_mask & (1 << index)) { + digest_count++; + } + } + digest_size = libspdm_get_hash_size(spdm_context->connection_info.algorithm.base_hash_algo); + target_data_size = digest_size * digest_count; + target_data = spdm_context->connection_info.peer_total_digest_buffer; + break; + case LIBSPDM_DATA_SESSION_USE_PSK: + target_data_size = sizeof(bool); + target_data = &session_info->use_psk; + break; + case LIBSPDM_DATA_SESSION_MUT_AUTH_REQUESTED: + target_data_size = sizeof(uint8_t); + target_data = &session_info->mut_auth_requested; + break; + case LIBSPDM_DATA_SESSION_END_SESSION_ATTRIBUTES: + target_data_size = sizeof(uint8_t); + target_data = &session_info->end_session_attributes; + break; + case LIBSPDM_DATA_SESSION_POLICY: + target_data_size = sizeof(uint8_t); + target_data = &session_info->session_policy; + break; + case LIBSPDM_DATA_APP_CONTEXT_DATA: + target_data_size = sizeof(void *); + target_data = &spdm_context->app_context_data_ptr; + break; + case LIBSPDM_DATA_HANDLE_ERROR_RETURN_POLICY: + target_data_size = sizeof(uint8_t); + target_data = &spdm_context->handle_error_return_policy; + break; + case LIBSPDM_DATA_VCA_CACHE: + target_data_size = spdm_context->transcript.message_a.buffer_size; + target_data = spdm_context->transcript.message_a.buffer; + break; + default: + return LIBSPDM_STATUS_UNSUPPORTED_CAP; + break; + } + + if (*data_size < target_data_size) { + *data_size = target_data_size; + return LIBSPDM_STATUS_BUFFER_TOO_SMALL; + } + libspdm_copy_mem(data, *data_size, target_data, target_data_size); + *data_size = target_data_size; + + return LIBSPDM_STATUS_SUCCESS; +} + +/** + * Reset message A cache in SPDM context. + * + * @param spdm_context A pointer to the SPDM context. + **/ +void libspdm_reset_message_a(void *context) +{ + libspdm_context_t *spdm_context; + + spdm_context = context; + libspdm_reset_managed_buffer(&spdm_context->transcript.message_a); +} + +/** + * Reset message B cache in SPDM context. + * + * @param spdm_context A pointer to the SPDM context. + **/ +void libspdm_reset_message_b(void *context) +{ + libspdm_context_t *spdm_context; + + spdm_context = context; +#if LIBSPDM_RECORD_TRANSCRIPT_DATA_SUPPORT + libspdm_reset_managed_buffer(&spdm_context->transcript.message_b); +#else + if (spdm_context->transcript.digest_context_m1m2 != NULL) { + libspdm_hash_free (spdm_context->connection_info.algorithm.base_hash_algo, + spdm_context->transcript.digest_context_m1m2); + spdm_context->transcript.digest_context_m1m2 = NULL; + } +#endif +} + +/** + * Reset message C cache in SPDM context. + * + * @param spdm_context A pointer to the SPDM context. + **/ +void libspdm_reset_message_c(void *context) +{ + libspdm_context_t *spdm_context; + + spdm_context = context; +#if LIBSPDM_RECORD_TRANSCRIPT_DATA_SUPPORT + libspdm_reset_managed_buffer(&spdm_context->transcript.message_c); +#else + if (spdm_context->transcript.digest_context_m1m2 != NULL) { + libspdm_hash_free (spdm_context->connection_info.algorithm.base_hash_algo, + spdm_context->transcript.digest_context_m1m2); + spdm_context->transcript.digest_context_m1m2 = NULL; + } +#endif +} + +/** + * Reset message MutB cache in SPDM context. + * + * @param spdm_context A pointer to the SPDM context. + **/ +void libspdm_reset_message_mut_b(void *context) +{ + libspdm_context_t *spdm_context; + + spdm_context = context; +#if LIBSPDM_RECORD_TRANSCRIPT_DATA_SUPPORT + libspdm_reset_managed_buffer(&spdm_context->transcript.message_mut_b); +#else + if (spdm_context->transcript.digest_context_mut_m1m2 != NULL) { + libspdm_hash_free (spdm_context->connection_info.algorithm.base_hash_algo, + spdm_context->transcript.digest_context_mut_m1m2); + spdm_context->transcript.digest_context_mut_m1m2 = NULL; + } +#endif +} + +/** + * Reset message MutC cache in SPDM context. + * + * @param spdm_context A pointer to the SPDM context. + **/ +void libspdm_reset_message_mut_c(void *context) +{ + libspdm_context_t *spdm_context; + + spdm_context = context; +#if LIBSPDM_RECORD_TRANSCRIPT_DATA_SUPPORT + libspdm_reset_managed_buffer(&spdm_context->transcript.message_mut_c); +#else + if (spdm_context->transcript.digest_context_mut_m1m2 != NULL) { + libspdm_hash_free (spdm_context->connection_info.algorithm.base_hash_algo, + spdm_context->transcript.digest_context_mut_m1m2); + spdm_context->transcript.digest_context_mut_m1m2 = NULL; + } +#endif +} + +/** + * Reset message M cache in SPDM context. + * If session_info is NULL, this function will use M cache of SPDM context, + * else will use M cache of SPDM session context. + * + * @param spdm_context A pointer to the SPDM context. + * @param session_info A pointer to the SPDM session context. + **/ +void libspdm_reset_message_m(void *context, void *session_info) +{ + libspdm_context_t *spdm_context; + libspdm_session_info_t *spdm_session_info; + + spdm_context = context; + spdm_session_info = session_info; +#if LIBSPDM_RECORD_TRANSCRIPT_DATA_SUPPORT + if (spdm_session_info == NULL) { + libspdm_reset_managed_buffer(&spdm_context->transcript.message_m); + } else { + libspdm_reset_managed_buffer(&spdm_session_info->session_transcript.message_m); + } +#else + if (spdm_session_info == NULL) { + if (spdm_context->transcript.digest_context_l1l2 != NULL) { + libspdm_hash_free (spdm_context->connection_info.algorithm.base_hash_algo, + spdm_context->transcript.digest_context_l1l2); + spdm_context->transcript.digest_context_l1l2 = NULL; + } + } else { + if (spdm_session_info->session_transcript.digest_context_l1l2 != NULL) { + libspdm_hash_free (spdm_context->connection_info.algorithm.base_hash_algo, + spdm_session_info->session_transcript.digest_context_l1l2); + spdm_session_info->session_transcript.digest_context_l1l2 = NULL; + } + } +#endif +} + +/** + * Reset message K cache in SPDM context. + * + * @param spdm_context A pointer to the SPDM context. + * @param spdm_session_info A pointer to the SPDM session context. + **/ +void libspdm_reset_message_k(void *context, void *session_info) +{ + libspdm_session_info_t *spdm_session_info; + + spdm_session_info = session_info; +#if LIBSPDM_RECORD_TRANSCRIPT_DATA_SUPPORT + libspdm_reset_managed_buffer(&spdm_session_info->session_transcript.message_k); +#else + { + libspdm_context_t *spdm_context; + + spdm_context = context; + + if (spdm_session_info->session_transcript.digest_context_th != NULL) { + libspdm_hash_free (spdm_context->connection_info.algorithm.base_hash_algo, + spdm_session_info->session_transcript.digest_context_th); + spdm_session_info->session_transcript.digest_context_th = NULL; + } + if (spdm_session_info->session_transcript.digest_context_th_backup != NULL) { + libspdm_hash_free (spdm_context->connection_info.algorithm.base_hash_algo, + spdm_session_info->session_transcript.digest_context_th_backup); + spdm_session_info->session_transcript.digest_context_th_backup = NULL; + } + } +#endif +} + +/** + * Reset message F cache in SPDM context. + * + * @param spdm_context A pointer to the SPDM context. + * @param spdm_session_info A pointer to the SPDM session context. + **/ +void libspdm_reset_message_f(void *context, void *session_info) +{ + libspdm_session_info_t *spdm_session_info; + + spdm_session_info = session_info; +#if LIBSPDM_RECORD_TRANSCRIPT_DATA_SUPPORT + libspdm_reset_managed_buffer(&spdm_session_info->session_transcript.message_f); +#else + { + libspdm_context_t *spdm_context; + + spdm_context = context; + + if (spdm_session_info->session_transcript.digest_context_th != NULL) { + libspdm_hash_free (spdm_context->connection_info.algorithm.base_hash_algo, + spdm_session_info->session_transcript.digest_context_th); + spdm_session_info->session_transcript.digest_context_th = + spdm_session_info->session_transcript.digest_context_th_backup; + spdm_session_info->session_transcript.digest_context_th_backup = NULL; + } + spdm_session_info->session_transcript.message_f_initialized = false; + } +#endif +} + +/** + * Reset message buffer in SPDM context according to request code. + * + * @param spdm_context A pointer to the SPDM context. + * @param spdm_session_info A pointer to the SPDM session context. + * @param spdm_request The SPDM request code. + */ +void libspdm_reset_message_buffer_via_request_code(void *context, void *session_info, + uint8_t request_code) +{ + libspdm_context_t *spdm_context; + + spdm_context = context; + /** + * Any request other than SPDM_GET_MEASUREMENTS resets L1/L2 + */ + if (request_code != SPDM_GET_MEASUREMENTS) { + libspdm_reset_message_m(spdm_context, session_info); + } + /** + * If the Requester issued GET_MEASUREMENTS or KEY_EXCHANGE or FINISH or PSK_EXCHANGE + * or PSK_FINISH or KEY_UPDATE or HEARTBEAT or GET_ENCAPSULATED_REQUEST or DELIVER_ENCAPSULATED_RESPONSE + * or END_SESSSION request(s) and skipped CHALLENGE completion, M1 and M2 are reset to null. + */ + switch (request_code) + { + case SPDM_KEY_EXCHANGE: + case SPDM_GET_MEASUREMENTS: + case SPDM_FINISH: + case SPDM_PSK_EXCHANGE: + case SPDM_PSK_FINISH: + case SPDM_KEY_UPDATE: + case SPDM_HEARTBEAT: + case SPDM_GET_ENCAPSULATED_REQUEST: + case SPDM_END_SESSION: + if (spdm_context->connection_info.connection_state < + LIBSPDM_CONNECTION_STATE_AUTHENTICATED) { + libspdm_reset_message_b(spdm_context); + libspdm_reset_message_c(spdm_context); + libspdm_reset_message_mut_b(spdm_context); + libspdm_reset_message_mut_c(spdm_context); + } + break; + case SPDM_DELIVER_ENCAPSULATED_RESPONSE: + if (spdm_context->connection_info.connection_state < + LIBSPDM_CONNECTION_STATE_AUTHENTICATED) { + libspdm_reset_message_b(spdm_context); + libspdm_reset_message_c(spdm_context); + } + break; + case SPDM_GET_DIGESTS: + libspdm_reset_message_b(spdm_context); + break; + default: + break; + } +} +/** + * Append message A cache in SPDM context. + * + * @param spdm_context A pointer to the SPDM context. + * @param message message buffer. + * @param message_size size in bytes of message buffer. + * + * @return RETURN_SUCCESS message is appended. + * @return RETURN_OUT_OF_RESOURCES message is not appended because the internal cache is full. + **/ +libspdm_return_t libspdm_append_message_a(void *context, const void *message, size_t message_size) +{ + libspdm_context_t *spdm_context; + + spdm_context = context; + return libspdm_append_managed_buffer(&spdm_context->transcript.message_a, + message, message_size); +} + +/** + * Append message B cache in SPDM context. + * + * @param spdm_context A pointer to the SPDM context. + * @param message message buffer. + * @param message_size size in bytes of message buffer. + * + * @return RETURN_SUCCESS message is appended. + * @return RETURN_OUT_OF_RESOURCES message is not appended because the internal cache is full. + **/ +libspdm_return_t libspdm_append_message_b(void *context, const void *message, size_t message_size) +{ + libspdm_context_t *spdm_context; + + spdm_context = context; +#if LIBSPDM_RECORD_TRANSCRIPT_DATA_SUPPORT + return libspdm_append_managed_buffer(&spdm_context->transcript.message_b, + message, message_size); +#else + { + bool result; + + if (spdm_context->transcript.digest_context_m1m2 == NULL) { + spdm_context->transcript.digest_context_m1m2 = libspdm_hash_new ( + spdm_context->connection_info.algorithm.base_hash_algo); + if (spdm_context->transcript.digest_context_m1m2 == NULL) { + return LIBSPDM_STATUS_CRYPTO_ERROR; + } + result = libspdm_hash_init (spdm_context->connection_info.algorithm.base_hash_algo, + spdm_context->transcript.digest_context_m1m2); + if (!result) { + libspdm_hash_free (spdm_context->connection_info.algorithm.base_hash_algo, + spdm_context->transcript.digest_context_m1m2); + spdm_context->transcript.digest_context_m1m2 = NULL; + return LIBSPDM_STATUS_CRYPTO_ERROR; + } + result = libspdm_hash_update (spdm_context->connection_info.algorithm.base_hash_algo, + spdm_context->transcript.digest_context_m1m2, + libspdm_get_managed_buffer(&spdm_context->transcript. + message_a), + libspdm_get_managed_buffer_size(&spdm_context->transcript. + message_a)); + if (!result) { + libspdm_hash_free (spdm_context->connection_info.algorithm.base_hash_algo, + spdm_context->transcript.digest_context_m1m2); + spdm_context->transcript.digest_context_m1m2 = NULL; + return LIBSPDM_STATUS_CRYPTO_ERROR; + } + } + + result = libspdm_hash_update (spdm_context->connection_info.algorithm.base_hash_algo, + spdm_context->transcript.digest_context_m1m2, message, + message_size); + if (!result) { + libspdm_hash_free (spdm_context->connection_info.algorithm.base_hash_algo, + spdm_context->transcript.digest_context_m1m2); + spdm_context->transcript.digest_context_m1m2 = NULL; + return LIBSPDM_STATUS_CRYPTO_ERROR; + } + + return LIBSPDM_STATUS_SUCCESS; + } +#endif +} + +/** + * Append message C cache in SPDM context. + * + * @param spdm_context A pointer to the SPDM context. + * @param message message buffer. + * @param message_size size in bytes of message buffer. + * + * @return RETURN_SUCCESS message is appended. + * @return RETURN_OUT_OF_RESOURCES message is not appended because the internal cache is full. + **/ +libspdm_return_t libspdm_append_message_c(void *context, const void *message, size_t message_size) +{ + libspdm_context_t *spdm_context; + + spdm_context = context; +#if LIBSPDM_RECORD_TRANSCRIPT_DATA_SUPPORT + return libspdm_append_managed_buffer(&spdm_context->transcript.message_c, + message, message_size); +#else + { + bool result; + + if (spdm_context->transcript.digest_context_m1m2 == NULL) { + spdm_context->transcript.digest_context_m1m2 = libspdm_hash_new ( + spdm_context->connection_info.algorithm.base_hash_algo); + if (spdm_context->transcript.digest_context_m1m2 == NULL) { + return LIBSPDM_STATUS_CRYPTO_ERROR; + } + result = libspdm_hash_init (spdm_context->connection_info.algorithm.base_hash_algo, + spdm_context->transcript.digest_context_m1m2); + if (!result) { + libspdm_hash_free (spdm_context->connection_info.algorithm.base_hash_algo, + spdm_context->transcript.digest_context_m1m2); + spdm_context->transcript.digest_context_m1m2 = NULL; + return LIBSPDM_STATUS_CRYPTO_ERROR; + } + result = libspdm_hash_update (spdm_context->connection_info.algorithm.base_hash_algo, + spdm_context->transcript.digest_context_m1m2, + libspdm_get_managed_buffer(&spdm_context->transcript. + message_a), + libspdm_get_managed_buffer_size(&spdm_context->transcript. + message_a)); + if (!result) { + libspdm_hash_free (spdm_context->connection_info.algorithm.base_hash_algo, + spdm_context->transcript.digest_context_m1m2); + spdm_context->transcript.digest_context_m1m2 = NULL; + return LIBSPDM_STATUS_CRYPTO_ERROR; + } + } + + result = libspdm_hash_update (spdm_context->connection_info.algorithm.base_hash_algo, + spdm_context->transcript.digest_context_m1m2, message, + message_size); + if (!result) { + libspdm_hash_free (spdm_context->connection_info.algorithm.base_hash_algo, + spdm_context->transcript.digest_context_m1m2); + spdm_context->transcript.digest_context_m1m2 = NULL; + return LIBSPDM_STATUS_CRYPTO_ERROR; + } + + return LIBSPDM_STATUS_SUCCESS; + } +#endif +} + +/** + * Append message MutB cache in SPDM context. + * + * @param spdm_context A pointer to the SPDM context. + * @param message message buffer. + * @param message_size size in bytes of message buffer. + * + * @return RETURN_SUCCESS message is appended. + * @return RETURN_OUT_OF_RESOURCES message is not appended because the internal cache is full. + **/ +libspdm_return_t libspdm_append_message_mut_b(void *context, const void *message, + size_t message_size) +{ + libspdm_context_t *spdm_context; + + spdm_context = context; +#if LIBSPDM_RECORD_TRANSCRIPT_DATA_SUPPORT + return libspdm_append_managed_buffer(&spdm_context->transcript.message_mut_b, + message, message_size); +#else + { + bool result; + + if (spdm_context->transcript.digest_context_mut_m1m2 == NULL) { + spdm_context->transcript.digest_context_mut_m1m2 = libspdm_hash_new ( + spdm_context->connection_info.algorithm.base_hash_algo); + if (spdm_context->transcript.digest_context_mut_m1m2 == NULL) { + return LIBSPDM_STATUS_CRYPTO_ERROR; + } + result = libspdm_hash_init (spdm_context->connection_info.algorithm.base_hash_algo, + spdm_context->transcript.digest_context_mut_m1m2); + if (!result) { + libspdm_hash_free (spdm_context->connection_info.algorithm.base_hash_algo, + spdm_context->transcript.digest_context_mut_m1m2); + spdm_context->transcript.digest_context_mut_m1m2 = NULL; + return LIBSPDM_STATUS_CRYPTO_ERROR; + } + if ((spdm_context->connection_info.version >> SPDM_VERSION_NUMBER_SHIFT_BIT) > + SPDM_MESSAGE_VERSION_11) { + + /* Need append VCA since 1.2 script */ + result = libspdm_hash_update ( + spdm_context->connection_info.algorithm.base_hash_algo, + spdm_context->transcript.digest_context_mut_m1m2, + libspdm_get_managed_buffer(&spdm_context->transcript.message_a), + libspdm_get_managed_buffer_size(&spdm_context->transcript. + message_a)); + if (!result) { + libspdm_hash_free (spdm_context->connection_info.algorithm.base_hash_algo, + spdm_context->transcript.digest_context_mut_m1m2); + spdm_context->transcript.digest_context_mut_m1m2 = NULL; + return LIBSPDM_STATUS_CRYPTO_ERROR; + } + } + } + + result = libspdm_hash_update (spdm_context->connection_info.algorithm.base_hash_algo, + spdm_context->transcript.digest_context_mut_m1m2, message, + message_size); + if (!result) { + libspdm_hash_free (spdm_context->connection_info.algorithm.base_hash_algo, + spdm_context->transcript.digest_context_mut_m1m2); + spdm_context->transcript.digest_context_mut_m1m2 = NULL; + return LIBSPDM_STATUS_CRYPTO_ERROR; + } + + return LIBSPDM_STATUS_SUCCESS; + } +#endif +} + +/** + * Append message MutC cache in SPDM context. + * + * @param spdm_context A pointer to the SPDM context. + * @param message message buffer. + * @param message_size size in bytes of message buffer. + * + * @return RETURN_SUCCESS message is appended. + * @return RETURN_OUT_OF_RESOURCES message is not appended because the internal cache is full. + **/ +libspdm_return_t libspdm_append_message_mut_c(void *context, const void *message, + size_t message_size) +{ + libspdm_context_t *spdm_context; + + spdm_context = context; +#if LIBSPDM_RECORD_TRANSCRIPT_DATA_SUPPORT + return libspdm_append_managed_buffer(&spdm_context->transcript.message_mut_c, + message, message_size); +#else + { + bool result; + + if (spdm_context->transcript.digest_context_mut_m1m2 == NULL) { + spdm_context->transcript.digest_context_mut_m1m2 = libspdm_hash_new ( + spdm_context->connection_info.algorithm.base_hash_algo); + if (spdm_context->transcript.digest_context_mut_m1m2 == NULL) { + return LIBSPDM_STATUS_CRYPTO_ERROR; + } + result = libspdm_hash_init (spdm_context->connection_info.algorithm.base_hash_algo, + spdm_context->transcript.digest_context_mut_m1m2); + if (!result) { + libspdm_hash_free (spdm_context->connection_info.algorithm.base_hash_algo, + spdm_context->transcript.digest_context_mut_m1m2); + spdm_context->transcript.digest_context_mut_m1m2 = NULL; + return LIBSPDM_STATUS_CRYPTO_ERROR; + } + if ((spdm_context->connection_info.version >> SPDM_VERSION_NUMBER_SHIFT_BIT) > + SPDM_MESSAGE_VERSION_11) { + + /* Need append VCA since 1.2 script */ + result = libspdm_hash_update ( + spdm_context->connection_info.algorithm.base_hash_algo, + spdm_context->transcript.digest_context_mut_m1m2, + libspdm_get_managed_buffer(&spdm_context->transcript.message_a), + libspdm_get_managed_buffer_size(&spdm_context->transcript. + message_a)); + if (!result) { + libspdm_hash_free (spdm_context->connection_info.algorithm.base_hash_algo, + spdm_context->transcript.digest_context_mut_m1m2); + spdm_context->transcript.digest_context_mut_m1m2 = NULL; + return LIBSPDM_STATUS_CRYPTO_ERROR; + } + } + } + + result = libspdm_hash_update (spdm_context->connection_info.algorithm.base_hash_algo, + spdm_context->transcript.digest_context_mut_m1m2, message, + message_size); + if (!result) { + libspdm_hash_free (spdm_context->connection_info.algorithm.base_hash_algo, + spdm_context->transcript.digest_context_mut_m1m2); + spdm_context->transcript.digest_context_mut_m1m2 = NULL; + return LIBSPDM_STATUS_CRYPTO_ERROR; + } + + return LIBSPDM_STATUS_SUCCESS; + } +#endif +} + +/** + * Append message M cache in SPDM context. + * If session_info is NULL, this function will use M cache of SPDM context, + * else will use M cache of SPDM session context. + * + * @param spdm_context A pointer to the SPDM context. + * @param session_info A pointer to the SPDM session context. + * @param message message buffer. + * @param message_size size in bytes of message buffer. + * + * @return RETURN_SUCCESS message is appended. + * @return RETURN_OUT_OF_RESOURCES message is not appended because the internal cache is full. + **/ +libspdm_return_t libspdm_append_message_m(void *context, void *session_info, + const void *message, size_t message_size) +{ + libspdm_context_t *spdm_context; + libspdm_session_info_t *spdm_session_info; + + spdm_context = context; + spdm_session_info = session_info; +#if LIBSPDM_RECORD_TRANSCRIPT_DATA_SUPPORT + if (spdm_session_info == NULL) { + return libspdm_append_managed_buffer(&spdm_context->transcript.message_m, + message, message_size); + } else { + return libspdm_append_managed_buffer(&spdm_session_info->session_transcript.message_m, + message, message_size); + } +#else + { + bool result; + + if (spdm_session_info == NULL) { + if (spdm_context->transcript.digest_context_l1l2 == NULL) { + spdm_context->transcript.digest_context_l1l2 = libspdm_hash_new ( + spdm_context->connection_info.algorithm.base_hash_algo); + if (spdm_context->transcript.digest_context_l1l2 == NULL) { + return LIBSPDM_STATUS_CRYPTO_ERROR; + } + result = libspdm_hash_init (spdm_context->connection_info.algorithm.base_hash_algo, + spdm_context->transcript.digest_context_l1l2); + if (!result) { + libspdm_hash_free (spdm_context->connection_info.algorithm.base_hash_algo, + spdm_context->transcript.digest_context_l1l2); + spdm_context->transcript.digest_context_l1l2 = NULL; + return LIBSPDM_STATUS_CRYPTO_ERROR; + } + if ((spdm_context->connection_info.version >> SPDM_VERSION_NUMBER_SHIFT_BIT) > + SPDM_MESSAGE_VERSION_11) { + + /* Need append VCA since 1.2 script */ + result = libspdm_hash_update ( + spdm_context->connection_info.algorithm.base_hash_algo, + spdm_context->transcript.digest_context_l1l2, + libspdm_get_managed_buffer( + &spdm_context->transcript.message_a), + libspdm_get_managed_buffer_size(&spdm_context->transcript. + message_a)); + if (!result) { + libspdm_hash_free (spdm_context->connection_info.algorithm.base_hash_algo, + spdm_context->transcript.digest_context_l1l2); + spdm_context->transcript.digest_context_l1l2 = NULL; + return LIBSPDM_STATUS_CRYPTO_ERROR; + } + } + } + result = libspdm_hash_update (spdm_context->connection_info.algorithm.base_hash_algo, + spdm_context->transcript.digest_context_l1l2, message, + message_size); + if (!result) { + libspdm_hash_free (spdm_context->connection_info.algorithm.base_hash_algo, + spdm_context->transcript.digest_context_l1l2); + spdm_context->transcript.digest_context_l1l2 = NULL; + return LIBSPDM_STATUS_CRYPTO_ERROR; + } + } else { + if (spdm_session_info->session_transcript.digest_context_l1l2 == NULL) { + spdm_session_info->session_transcript.digest_context_l1l2 = libspdm_hash_new ( + spdm_context->connection_info.algorithm.base_hash_algo); + if (spdm_session_info->session_transcript.digest_context_l1l2 == NULL) { + return LIBSPDM_STATUS_CRYPTO_ERROR; + } + result = libspdm_hash_init (spdm_context->connection_info.algorithm.base_hash_algo, + spdm_session_info->session_transcript.digest_context_l1l2); + if (!result) { + libspdm_hash_free (spdm_context->connection_info.algorithm.base_hash_algo, + spdm_session_info->session_transcript.digest_context_l1l2); + spdm_session_info->session_transcript.digest_context_l1l2 = NULL; + return LIBSPDM_STATUS_CRYPTO_ERROR; + } + if ((spdm_context->connection_info.version >> SPDM_VERSION_NUMBER_SHIFT_BIT) > + SPDM_MESSAGE_VERSION_11) { + + /* Need append VCA since 1.2 script*/ + + result = libspdm_hash_update ( + spdm_context->connection_info.algorithm.base_hash_algo, + spdm_session_info->session_transcript.digest_context_l1l2, + libspdm_get_managed_buffer( + &spdm_context->transcript.message_a), + libspdm_get_managed_buffer_size(&spdm_context->transcript. + message_a)); + if (!result) { + libspdm_hash_free (spdm_context->connection_info.algorithm.base_hash_algo, + spdm_session_info->session_transcript.digest_context_l1l2); + spdm_session_info->session_transcript.digest_context_l1l2 = NULL; + return LIBSPDM_STATUS_CRYPTO_ERROR; + } + } + } + result = libspdm_hash_update (spdm_context->connection_info.algorithm.base_hash_algo, + spdm_session_info->session_transcript.digest_context_l1l2, + message, message_size); + if (!result) { + libspdm_hash_free (spdm_context->connection_info.algorithm.base_hash_algo, + spdm_session_info->session_transcript.digest_context_l1l2); + spdm_session_info->session_transcript.digest_context_l1l2 = NULL; + return LIBSPDM_STATUS_CRYPTO_ERROR; + } + } + + return LIBSPDM_STATUS_SUCCESS; + } +#endif +} + +/** + * Append message K cache in SPDM context. + * + * @param spdm_context A pointer to the SPDM context. + * @param spdm_session_info A pointer to the SPDM session context. + * @param is_requester Indicate of the key generation for a requester or a responder. + * @param message message buffer. + * @param message_size size in bytes of message buffer. + * + * @return RETURN_SUCCESS message is appended. + * @return RETURN_OUT_OF_RESOURCES message is not appended because the internal cache is full. + **/ +libspdm_return_t libspdm_append_message_k(void *context, void *session_info, + bool is_requester, const void *message, + size_t message_size) +{ + libspdm_session_info_t *spdm_session_info; + + spdm_session_info = session_info; +#if LIBSPDM_RECORD_TRANSCRIPT_DATA_SUPPORT + return libspdm_append_managed_buffer( + &spdm_session_info->session_transcript.message_k, message, + message_size); +#else + { + libspdm_context_t *spdm_context; + uint8_t *cert_chain_buffer; + size_t cert_chain_buffer_size; + bool result; + uint8_t cert_chain_buffer_hash[LIBSPDM_MAX_HASH_SIZE]; + uint32_t hash_size; + uint8_t slot_id; + + hash_size = 0; + spdm_context = context; + slot_id = spdm_context->connection_info.peer_used_cert_chain_slot_id; + + if (spdm_session_info->session_transcript.digest_context_th == NULL) { + if (!spdm_session_info->use_psk) { + LIBSPDM_ASSERT(slot_id < SPDM_MAX_SLOT_COUNT); + if (is_requester) { + if(spdm_context->connection_info.peer_used_cert_chain[slot_id].buffer_hash_size + != 0) { + hash_size = + spdm_context->connection_info.peer_used_cert_chain[slot_id]. + buffer_hash_size; + libspdm_copy_mem(cert_chain_buffer_hash, + sizeof(cert_chain_buffer_hash), + spdm_context->connection_info.peer_used_cert_chain[slot_id].buffer_hash, + hash_size); + } else { + result = libspdm_get_peer_cert_chain_buffer( + spdm_context, (const void **)&cert_chain_buffer, + &cert_chain_buffer_size); + if (!result) { + return LIBSPDM_STATUS_INVALID_STATE_PEER; + } + hash_size = libspdm_get_hash_size( + spdm_context->connection_info.algorithm.base_hash_algo); + result = libspdm_hash_all( + spdm_context->connection_info.algorithm.base_hash_algo, + cert_chain_buffer, cert_chain_buffer_size, + cert_chain_buffer_hash); + if (!result) { + return LIBSPDM_STATUS_CRYPTO_ERROR; + } + + } + } else { + result = libspdm_get_local_cert_chain_buffer( + spdm_context, (const void **)&cert_chain_buffer, &cert_chain_buffer_size); + + if (!result) { + return LIBSPDM_STATUS_INVALID_STATE_LOCAL; + } + hash_size = libspdm_get_hash_size( + spdm_context->connection_info.algorithm.base_hash_algo); + result = libspdm_hash_all( + spdm_context->connection_info.algorithm.base_hash_algo, + cert_chain_buffer, cert_chain_buffer_size, + cert_chain_buffer_hash); + if (!result) { + return LIBSPDM_STATUS_CRYPTO_ERROR; + } + } + } + } + + + /* prepare digest_context_th*/ + + if (spdm_session_info->session_transcript.digest_context_th == NULL) { + spdm_session_info->session_transcript.digest_context_th = libspdm_hash_new ( + spdm_context->connection_info.algorithm.base_hash_algo); + if (spdm_session_info->session_transcript.digest_context_th == NULL) { + return LIBSPDM_STATUS_CRYPTO_ERROR; + } + result = libspdm_hash_init (spdm_context->connection_info.algorithm.base_hash_algo, + spdm_session_info->session_transcript.digest_context_th); + if (!result) { + libspdm_hash_free (spdm_context->connection_info.algorithm.base_hash_algo, + spdm_session_info->session_transcript.digest_context_th); + return LIBSPDM_STATUS_CRYPTO_ERROR; + } + result = libspdm_hash_update (spdm_context->connection_info.algorithm.base_hash_algo, + spdm_session_info->session_transcript.digest_context_th, + libspdm_get_managed_buffer(&spdm_context->transcript. + message_a), + libspdm_get_managed_buffer_size( + &spdm_context->transcript.message_a)); + if (!result) { + libspdm_hash_free (spdm_context->connection_info.algorithm.base_hash_algo, + spdm_session_info->session_transcript.digest_context_th); + return LIBSPDM_STATUS_CRYPTO_ERROR; + } + if (!spdm_session_info->use_psk) { + result = libspdm_hash_update ( + spdm_context->connection_info.algorithm.base_hash_algo, + spdm_session_info->session_transcript.digest_context_th, + cert_chain_buffer_hash, hash_size); + if (!result) { + libspdm_hash_free (spdm_context->connection_info.algorithm.base_hash_algo, + spdm_session_info->session_transcript.digest_context_th); + return LIBSPDM_STATUS_CRYPTO_ERROR; + } + } + } + result = libspdm_hash_update (spdm_context->connection_info.algorithm.base_hash_algo, + spdm_session_info->session_transcript.digest_context_th, + message, + message_size); + if (!result) { + libspdm_hash_free (spdm_context->connection_info.algorithm.base_hash_algo, + spdm_session_info->session_transcript.digest_context_th); + return LIBSPDM_STATUS_CRYPTO_ERROR; + } + return LIBSPDM_STATUS_SUCCESS; + } +#endif +} + +/** + * Append message F cache in SPDM context. + * + * @param spdm_context A pointer to the SPDM context. + * @param spdm_session_info A pointer to the SPDM session context. + * @param is_requester Indicate of the key generation for a requester or a responder. + * @param message message buffer. + * @param message_size size in bytes of message buffer. + * + * @return RETURN_SUCCESS message is appended. + * @return RETURN_OUT_OF_RESOURCES message is not appended because the internal cache is full. + **/ +libspdm_return_t libspdm_append_message_f(void *context, void *session_info, + bool is_requester, const void *message, + size_t message_size) +{ + libspdm_session_info_t *spdm_session_info; + + spdm_session_info = session_info; +#if LIBSPDM_RECORD_TRANSCRIPT_DATA_SUPPORT + return libspdm_append_managed_buffer( + &spdm_session_info->session_transcript.message_f, message, + message_size); +#else + { + libspdm_context_t *spdm_context; + const uint8_t *mut_cert_chain_buffer; + size_t mut_cert_chain_buffer_size; + bool result; + uint8_t mut_cert_chain_buffer_hash[LIBSPDM_MAX_HASH_SIZE]; + uint32_t hash_size; + libspdm_return_t status; + uint8_t slot_id; + + hash_size = 0; + spdm_context = context; + slot_id = spdm_context->connection_info.peer_used_cert_chain_slot_id; + + if (!spdm_session_info->session_transcript.message_f_initialized) { + + /* digest_context_th might be NULL in unit test, where message_k is hardcoded. */ + if (spdm_session_info->session_transcript.digest_context_th == NULL) { + status = libspdm_append_message_k (context, session_info, is_requester, NULL, 0); + if (LIBSPDM_STATUS_IS_ERROR(status)) { + return status; + } + } + + if (!spdm_session_info->use_psk && spdm_session_info->mut_auth_requested) { + if (is_requester) { + result = libspdm_get_local_cert_chain_buffer( + spdm_context, + (const void **)&mut_cert_chain_buffer, + &mut_cert_chain_buffer_size); + if (!result) { + return LIBSPDM_STATUS_INVALID_STATE_LOCAL; + } + hash_size = libspdm_get_hash_size( + spdm_context->connection_info.algorithm.base_hash_algo); + result = libspdm_hash_all( + spdm_context->connection_info.algorithm.base_hash_algo, + mut_cert_chain_buffer, mut_cert_chain_buffer_size, + mut_cert_chain_buffer_hash); + if (!result) { + return LIBSPDM_STATUS_CRYPTO_ERROR; + } + } else { + LIBSPDM_ASSERT(slot_id < SPDM_MAX_SLOT_COUNT); + if (spdm_context->connection_info.peer_used_cert_chain[slot_id].buffer_hash_size + != 0) { + hash_size = + spdm_context->connection_info.peer_used_cert_chain[slot_id]. + buffer_hash_size; + libspdm_copy_mem(mut_cert_chain_buffer_hash, + sizeof(mut_cert_chain_buffer_hash), + spdm_context->connection_info.peer_used_cert_chain[slot_id].buffer_hash, + hash_size); + } else { + result = libspdm_get_peer_cert_chain_buffer( + spdm_context, + (const void **)&mut_cert_chain_buffer, + &mut_cert_chain_buffer_size); + if (!result) { + return LIBSPDM_STATUS_INVALID_STATE_PEER; + } + hash_size = libspdm_get_hash_size( + spdm_context->connection_info.algorithm.base_hash_algo); + result = libspdm_hash_all( + spdm_context->connection_info.algorithm.base_hash_algo, + mut_cert_chain_buffer, mut_cert_chain_buffer_size, + mut_cert_chain_buffer_hash); + if (!result) { + return LIBSPDM_STATUS_CRYPTO_ERROR; + } + } + } + } + + /* It is first time call, backup current message_k context + * this backup will be used in reset_message_f.*/ + + LIBSPDM_ASSERT (spdm_session_info->session_transcript.digest_context_th != NULL); + spdm_session_info->session_transcript.digest_context_th_backup = libspdm_hash_new ( + spdm_context->connection_info.algorithm.base_hash_algo); + if (spdm_session_info->session_transcript.digest_context_th_backup == NULL) { + return LIBSPDM_STATUS_CRYPTO_ERROR; + } + result = libspdm_hash_duplicate (spdm_context->connection_info.algorithm.base_hash_algo, + spdm_session_info->session_transcript.digest_context_th, + spdm_session_info->session_transcript.digest_context_th_backup); + if (!result) { + libspdm_hash_free (spdm_context->connection_info.algorithm.base_hash_algo, + spdm_session_info->session_transcript.digest_context_th_backup); + spdm_session_info->session_transcript.digest_context_th_backup = NULL; + return LIBSPDM_STATUS_CRYPTO_ERROR; + } + } + + + /* prepare digest_context_th*/ + + LIBSPDM_ASSERT (spdm_session_info->session_transcript.digest_context_th != NULL); + if (!spdm_session_info->session_transcript.message_f_initialized) { + if (!spdm_session_info->use_psk && spdm_session_info->mut_auth_requested) { + result = libspdm_hash_update ( + spdm_context->connection_info.algorithm.base_hash_algo, + spdm_session_info->session_transcript.digest_context_th, + mut_cert_chain_buffer_hash, hash_size); + if (!result) { + libspdm_hash_free (spdm_context->connection_info.algorithm.base_hash_algo, + spdm_session_info->session_transcript.digest_context_th); + spdm_session_info->session_transcript.digest_context_th = NULL; + return LIBSPDM_STATUS_CRYPTO_ERROR; + } + } + } + result = libspdm_hash_update (spdm_context->connection_info.algorithm.base_hash_algo, + spdm_session_info->session_transcript.digest_context_th, + message, + message_size); + if (!result) { + libspdm_hash_free (spdm_context->connection_info.algorithm.base_hash_algo, + spdm_session_info->session_transcript.digest_context_th); + spdm_session_info->session_transcript.digest_context_th = NULL; + return LIBSPDM_STATUS_CRYPTO_ERROR; + } + + spdm_session_info->session_transcript.message_f_initialized = true; + return LIBSPDM_STATUS_SUCCESS; + } +#endif +} + +/** + * This function returns if a given version is supported based upon the GET_VERSION/VERSION. + * + * @param spdm_context A pointer to the SPDM context. + * @param version The SPDM version. + * + * @retval true the version is supported. + * @retval false the version is not supported. + **/ +bool libspdm_is_version_supported(const libspdm_context_t *spdm_context, uint8_t version) +{ + if (version == (spdm_context->connection_info.version >> SPDM_VERSION_NUMBER_SHIFT_BIT)) { + return true; + } + + return false; +} + +/** + * This function returns connection version negotiated by GET_VERSION/VERSION. + * + * @param spdm_context A pointer to the SPDM context. + * + * @return the connection version. + **/ +uint8_t libspdm_get_connection_version(const libspdm_context_t *spdm_context) +{ + return (uint8_t)(spdm_context->connection_info.version >> SPDM_VERSION_NUMBER_SHIFT_BIT); +} + +/** + * This function returns if a capablities flag is supported in current SPDM connection. + * + * @param spdm_context A pointer to the SPDM context. + * @param is_requester Is the function called from a requester. + * @param requester_capabilities_flag The requester capabilities flag to be checked + * @param responder_capabilities_flag The responder capabilities flag to be checked + * + * @retval true the capablities flag is supported. + * @retval false the capablities flag is not supported. + **/ +bool libspdm_is_capabilities_flag_supported(const libspdm_context_t *spdm_context, + bool is_requester, + uint32_t requester_capabilities_flag, + uint32_t responder_capabilities_flag) +{ + uint32_t negotiated_requester_capabilities_flag; + uint32_t negotiated_responder_capabilities_flag; + + if (is_requester) { + negotiated_requester_capabilities_flag = spdm_context->local_context.capability.flags; + negotiated_responder_capabilities_flag = spdm_context->connection_info.capability.flags; + } else { + negotiated_requester_capabilities_flag = spdm_context->connection_info.capability.flags; + negotiated_responder_capabilities_flag = spdm_context->local_context.capability.flags; + } + + if (((requester_capabilities_flag == 0) || + ((negotiated_requester_capabilities_flag & + requester_capabilities_flag) != 0)) && + ((responder_capabilities_flag == 0) || + ((negotiated_responder_capabilities_flag & + responder_capabilities_flag) != 0))) { + return true; + } else { + return false; + } +} + +/** + * Register SPDM device input/output functions. + * + * This function must be called after libspdm_init_context, and before any SPDM communication. + * + * @param spdm_context A pointer to the SPDM context. + * @param send_message The fuction to send an SPDM transport layer message. + * @param receive_message The fuction to receive an SPDM transport layer message. + **/ +void libspdm_register_device_io_func( + void *context, libspdm_device_send_message_func send_message, + libspdm_device_receive_message_func receive_message) +{ + libspdm_context_t *spdm_context; + + spdm_context = context; + spdm_context->send_message = send_message; + spdm_context->receive_message = receive_message; +} + +/** + * Register SPDM device buffer management functions. + * + * This function must be called after libspdm_init_context, and before any SPDM communication. + * + * @param spdm_context A pointer to the SPDM context. + * @param acquire_sender_buffer The fuction to acquire transport layer sender buffer. + * @param release_sender_buffer The fuction to release transport layer sender buffer. + * @param acquire_receiver_buffer The fuction to acquire transport layer receiver buffer. + * @param release_receiver_buffer The fuction to release transport layer receiver buffer. + **/ +void libspdm_register_device_buffer_func( + void *context, + libspdm_device_acquire_sender_buffer_func acquire_sender_buffer, + libspdm_device_release_sender_buffer_func release_sender_buffer, + libspdm_device_acquire_receiver_buffer_func acquire_receiver_buffer, + libspdm_device_release_receiver_buffer_func release_receiver_buffer) +{ + libspdm_context_t *spdm_context; + + spdm_context = context; + spdm_context->acquire_sender_buffer = acquire_sender_buffer; + spdm_context->release_sender_buffer = release_sender_buffer; + spdm_context->acquire_receiver_buffer = acquire_receiver_buffer; + spdm_context->release_receiver_buffer = release_receiver_buffer; +} + +/** + * Register SPDM transport layer encode/decode functions for SPDM or APP messages. + * + * This function must be called after libspdm_init_context, and before any SPDM communication. + * + * @param spdm_context A pointer to the SPDM context. + * @param transport_encode_message The fuction to encode an SPDM or APP message to a transport layer message. + * @param transport_decode_message The fuction to decode an SPDM or APP message from a transport layer message. + * @param transport_get_header_size The fuction to get the maximum transport layer message header size. + **/ +void libspdm_register_transport_layer_func( + void *context, + libspdm_transport_encode_message_func transport_encode_message, + libspdm_transport_decode_message_func transport_decode_message, + libspdm_transport_get_header_size_func transport_get_header_size) +{ + libspdm_context_t *spdm_context; + + spdm_context = context; + spdm_context->transport_encode_message = transport_encode_message; + spdm_context->transport_decode_message = transport_decode_message; + spdm_context->transport_get_header_size = transport_get_header_size; +} + +/** + * Register SPDM certificate verification functions for SPDM GET_CERTIFICATE in requester or responder. + * It is called after GET_CERTIFICATE gets a full certificate chain from peer. + * + * If it is NOT registered, the default verification in SPDM lib will be used. It verifies: + * 1) The integrity of the certificate chain, (Root Cert Hash->Root Cert->Cert Chain), according to X.509. + * 2) The trust anchor, according LIBSPDM_DATA_PEER_PUBLIC_ROOT_CERT or LIBSPDM_DATA_PEER_PUBLIC_CERT_CHAIN. + * If it is registered, SPDM lib will use this function to verify the certificate. + * + * This function must be called after libspdm_init_context, and before any SPDM communication. + * + * @param context A pointer to the SPDM context. + * @param verify_spdm_cert_chain The fuction to verify an SPDM certificate after GET_CERTIFICATE. + **/ +void libspdm_register_verify_spdm_cert_chain_func( + void *context, + const libspdm_verify_spdm_cert_chain_func verify_spdm_cert_chain) +{ + libspdm_context_t *spdm_context; + + spdm_context = context; + spdm_context->local_context.verify_peer_spdm_cert_chain = verify_spdm_cert_chain; +} + +/** + * Get the size of required scratch buffer. + * + * The SPDM Integrator must call libspdm_get_sizeof_required_scratch_buffer to get the size, + * then allocate enough scratch buffer and call libspdm_set_scratch_buffer(). + * + * @param context A pointer to the SPDM context. + * + * @return the size of required scratch buffer. + **/ +size_t libspdm_get_sizeof_required_scratch_buffer ( + void *context) +{ + return LIBSPDM_SCRATCH_BUFFER_SIZE; +} + +/** + * Set the scratch buffer. + * + * This function must be called after libspdm_init_context, and before any SPDM communication. + * + * @param context A pointer to the SPDM context. + * @param scratch_buffer Buffer address of the scratch buffer. + * @param scratch_buffer_size Size of the scratch buffer. + * + **/ +void libspdm_set_scratch_buffer ( + void *context, + void *scratch_buffer, + size_t scratch_buffer_size) +{ + libspdm_context_t *spdm_context; + + spdm_context = context; + LIBSPDM_ASSERT (scratch_buffer_size >= LIBSPDM_SCRATCH_BUFFER_SIZE); + spdm_context->scratch_buffer = scratch_buffer; + spdm_context->scratch_buffer_size = scratch_buffer_size; +} + +/** + * Get the scratch buffer. + * + * @param context A pointer to the SPDM context. + * @param scratch_buffer Buffer address of the scratch buffer. + * @param scratch_buffer_size Size of the scratch buffer. + * + **/ +void libspdm_get_scratch_buffer ( + void *context, + void **scratch_buffer, + size_t *scratch_buffer_size) +{ + libspdm_context_t *spdm_context; + + spdm_context = context; + LIBSPDM_ASSERT (spdm_context->scratch_buffer != NULL); + LIBSPDM_ASSERT (spdm_context->scratch_buffer_size >= LIBSPDM_SCRATCH_BUFFER_SIZE); + *scratch_buffer = spdm_context->scratch_buffer; + *scratch_buffer_size = spdm_context->scratch_buffer_size; +} + +/** + * Acquire a device sender buffer for transport layer message. + * + * @param context A pointer to the SPDM context. + * @param max_msg_size size in bytes of the maximum size of sender buffer. + * @param msg_buf_ptr A pointer to a sender buffer. + * + * @retval RETURN_SUCCESS The sender buffer is acquired. + **/ +libspdm_return_t libspdm_acquire_sender_buffer ( + libspdm_context_t *spdm_context, size_t *max_msg_size, void **msg_buf_ptr) +{ + libspdm_return_t status; + + LIBSPDM_ASSERT (spdm_context->sender_buffer == NULL); + LIBSPDM_ASSERT (spdm_context->sender_buffer_size == 0); + status = spdm_context->acquire_sender_buffer (spdm_context, max_msg_size, msg_buf_ptr); + if (status != LIBSPDM_STATUS_SUCCESS) { + return status; + } + spdm_context->sender_buffer = *msg_buf_ptr; + spdm_context->sender_buffer_size = *max_msg_size; + #if LIBSPDM_ENABLE_CAPABILITY_CHUNK_CAP || LIBSPDM_ENABLE_CHUNK_CAP + /* it return scratch buffer, because the requester need build message there.*/ + *msg_buf_ptr = spdm_context->scratch_buffer + + LIBSPDM_SCRATCH_BUFFER_LARGE_SENDER_RECEIVER_OFFSET; + *max_msg_size = LIBSPDM_SCRATCH_BUFFER_LARGE_SENDER_RECEIVER_CAPACITY; + #endif + return LIBSPDM_STATUS_SUCCESS; +} + +/** + * Release a device sender buffer for transport layer message. + * + * @param context A pointer to the SPDM context. + * + * @retval RETURN_SUCCESS The sender buffer is Released. + **/ +void libspdm_release_sender_buffer (libspdm_context_t *spdm_context) +{ + LIBSPDM_ASSERT(spdm_context->sender_buffer != NULL); + LIBSPDM_ASSERT(spdm_context->sender_buffer_size != 0); + + spdm_context->release_sender_buffer (spdm_context, spdm_context->sender_buffer); + spdm_context->sender_buffer = NULL; + spdm_context->sender_buffer_size = 0; +} + +/** + * Get the sender buffer. + * + * @param context A pointer to the SPDM context. + * @param receiver_buffer Buffer address of the sender buffer. + * @param receiver_buffer_size Size of the sender buffer. + * + **/ +void libspdm_get_sender_buffer ( + libspdm_context_t *spdm_context, + void **sender_buffer, + size_t *sender_buffer_size) +{ + *sender_buffer = spdm_context->sender_buffer; + *sender_buffer_size = spdm_context->sender_buffer_size; +} + +/** + * Acquire a device receiver buffer for transport layer message. + * + * @param context A pointer to the SPDM context. + * @param max_msg_size size in bytes of the maximum size of receiver buffer. + * @param msg_buf_pt A pointer to a receiver buffer. + * + * @retval RETURN_SUCCESS The receiver buffer is acquired. + **/ +libspdm_return_t libspdm_acquire_receiver_buffer ( + libspdm_context_t *spdm_context, size_t *max_msg_size, void **msg_buf_ptr) +{ + libspdm_return_t status; + + LIBSPDM_ASSERT (spdm_context->receiver_buffer == NULL); + LIBSPDM_ASSERT (spdm_context->receiver_buffer_size == 0); + status = spdm_context->acquire_receiver_buffer (spdm_context, max_msg_size, msg_buf_ptr); + if (status != LIBSPDM_STATUS_SUCCESS) { + return status; + } + spdm_context->receiver_buffer = *msg_buf_ptr; + spdm_context->receiver_buffer_size = *max_msg_size; + #if LIBSPDM_ENABLE_CAPABILITY_CHUNK_CAP || LIBSPDM_ENABLE_CHUNK_CAP + /* it return scratch buffer, because the requester need build message there.*/ + *msg_buf_ptr = spdm_context->scratch_buffer + + LIBSPDM_SCRATCH_BUFFER_LARGE_SENDER_RECEIVER_OFFSET; + *max_msg_size = LIBSPDM_SCRATCH_BUFFER_LARGE_SENDER_RECEIVER_CAPACITY; + #endif + return LIBSPDM_STATUS_SUCCESS; +} + +/** + * Release a device receiver buffer for transport layer message. + * + * @param context A pointer to the SPDM context. + * + * @retval RETURN_SUCCESS The receiver buffer is Released. + **/ +void libspdm_release_receiver_buffer (libspdm_context_t *spdm_context) +{ + LIBSPDM_ASSERT(spdm_context->receiver_buffer != NULL); + LIBSPDM_ASSERT(spdm_context->receiver_buffer_size != 0); + + spdm_context->release_receiver_buffer (spdm_context, spdm_context->receiver_buffer); + spdm_context->receiver_buffer = NULL; + spdm_context->receiver_buffer_size = 0; +} + +/** + * Get the receiver buffer. + * + * @param context A pointer to the SPDM context. + * @param receiver_buffer Buffer address of the receiver buffer. + * @param receiver_buffer_size Size of the receiver buffer. + * + **/ +void libspdm_get_receiver_buffer ( + libspdm_context_t *spdm_context, + void **receiver_buffer, + size_t *receiver_buffer_size) +{ + *receiver_buffer = spdm_context->receiver_buffer; + *receiver_buffer_size = spdm_context->receiver_buffer_size; +} + +/** + * Get the last SPDM error struct of an SPDM context. + * + * @param spdm_context A pointer to the SPDM context. + * @param last_spdm_error Last SPDM error struct of an SPDM context. + */ +void libspdm_get_last_spdm_error_struct(void *context, libspdm_error_struct_t *last_spdm_error) +{ + libspdm_context_t *spdm_context; + + spdm_context = context; + libspdm_copy_mem(last_spdm_error, sizeof(libspdm_error_struct_t), + &spdm_context->last_spdm_error,sizeof(libspdm_error_struct_t)); +} + +/** + * Set the last SPDM error struct of an SPDM context. + * + * @param spdm_context A pointer to the SPDM context. + * @param last_spdm_error Last SPDM error struct of an SPDM context. + */ +void libspdm_set_last_spdm_error_struct(void *context, libspdm_error_struct_t *last_spdm_error) +{ + libspdm_context_t *spdm_context; + + spdm_context = context; + libspdm_copy_mem(&spdm_context->last_spdm_error, sizeof(spdm_context->last_spdm_error), + last_spdm_error, sizeof(libspdm_error_struct_t)); +} + +/** + * Initialize an SPDM context, as well as all secured message contexts, + * in the specified locations. + * + * The size in bytes of the spdm_context can be returned by + * libspdm_get_context_size_without_secured_context. + * + * The size in bytes of a single secured message context can be returned by + * libspdm_secured_message_get_context_size. + * + * @param spdm_context A pointer to the SPDM context. + * @param secured_contexts An array of pointers, with each entry containing + * the location of a secured message context. + * @param num_secured_contexts Number of secured message contexts to initialize. + * Currently, only LIBSPDM_MAX_SESSION_COUNT is supported. + * + * @retval RETURN_SUCCESS Contexts are initialized. + * @retval RETURN_DEVICE_ERROR Context initialization failed. + */ +libspdm_return_t libspdm_init_context_with_secured_context(void *context, + void **secured_contexts, + size_t num_secured_contexts) +{ + libspdm_context_t *spdm_context; + size_t index; + + LIBSPDM_ASSERT(context != NULL); + LIBSPDM_ASSERT(secured_contexts != NULL); + LIBSPDM_ASSERT(num_secured_contexts == LIBSPDM_MAX_SESSION_COUNT); + + spdm_context = context; + libspdm_zero_mem(spdm_context, sizeof(libspdm_context_t)); + spdm_context->version = libspdm_context_struct_version; + spdm_context->transcript.message_a.max_buffer_size = + sizeof(spdm_context->transcript.message_a.buffer); +#if LIBSPDM_RECORD_TRANSCRIPT_DATA_SUPPORT + spdm_context->transcript.message_b.max_buffer_size = + sizeof(spdm_context->transcript.message_b.buffer); + spdm_context->transcript.message_c.max_buffer_size = + sizeof(spdm_context->transcript.message_c.buffer); + spdm_context->transcript.message_mut_b.max_buffer_size = + sizeof(spdm_context->transcript.message_mut_b.buffer); + spdm_context->transcript.message_mut_c.max_buffer_size = + sizeof(spdm_context->transcript.message_mut_c.buffer); + spdm_context->transcript.message_m.max_buffer_size = + sizeof(spdm_context->transcript.message_m.buffer); +#endif + spdm_context->retry_times = LIBSPDM_MAX_REQUEST_RETRY_TIMES; + spdm_context->response_state = LIBSPDM_RESPONSE_STATE_NORMAL; + spdm_context->current_token = 0; + spdm_context->local_context.version.spdm_version_count = 3; + spdm_context->local_context.version.spdm_version[0] = SPDM_MESSAGE_VERSION_10 << + SPDM_VERSION_NUMBER_SHIFT_BIT; + spdm_context->local_context.version.spdm_version[1] = SPDM_MESSAGE_VERSION_11 << + SPDM_VERSION_NUMBER_SHIFT_BIT; + spdm_context->local_context.version.spdm_version[2] = SPDM_MESSAGE_VERSION_12 << + SPDM_VERSION_NUMBER_SHIFT_BIT; + spdm_context->local_context.secured_message_version.spdm_version_count = 2; + spdm_context->local_context.secured_message_version.spdm_version[0] = + SPDM_MESSAGE_VERSION_10 << SPDM_VERSION_NUMBER_SHIFT_BIT; + spdm_context->local_context.secured_message_version.spdm_version[1] = + SPDM_MESSAGE_VERSION_11 << SPDM_VERSION_NUMBER_SHIFT_BIT; + spdm_context->local_context.capability.st1 = SPDM_ST1_VALUE_US; + + spdm_context->encap_context.certificate_chain_buffer.max_buffer_size = + sizeof(spdm_context->encap_context.certificate_chain_buffer.buffer); + + /* From the config.h, need different value for CHUNK - TBD*/ + spdm_context->local_context.capability.data_transfer_size = LIBSPDM_DATA_TRANSFER_SIZE; + spdm_context->local_context.capability.max_spdm_msg_size = LIBSPDM_MAX_SPDM_MSG_SIZE; + + for (index = 0; index < num_secured_contexts; index++) { + if (secured_contexts[index] == NULL) { + return LIBSPDM_STATUS_INVALID_PARAMETER; + } + + spdm_context->session_info[index].secured_message_context = secured_contexts[index]; + libspdm_secured_message_init_context( + spdm_context->session_info[index] + .secured_message_context); + } + + return LIBSPDM_STATUS_SUCCESS; +} + +/** + * Initialize an SPDM context, as well as secured message contexts. + * The secured message contexts are appended to the context structure. + * + * The total size in bytes of the spdm_context and all secured message + * contexts can be returned by libspdm_get_context_size(). + * + * @param spdm_context A pointer to the SPDM context. + * + * @retval RETURN_SUCCESS context is initialized. + * @retval RETURN_DEVICE_ERROR context initialization failed. + */ +libspdm_return_t libspdm_init_context(void *context) +{ + libspdm_context_t *spdm_context; + void *secured_context; + void *secured_contexts[LIBSPDM_MAX_SESSION_COUNT]; + size_t secured_context_size; + size_t index; + + LIBSPDM_ASSERT(context != NULL); + + /* libspdm_get_context_size() allocates space for all secured message + * contexts. They are appended to the general SPDM context. */ + spdm_context = context; + secured_context = (void *)((size_t)(spdm_context + 1)); + secured_context_size = libspdm_secured_message_get_context_size(); + + for (index = 0; index < LIBSPDM_MAX_SESSION_COUNT; index++) + { + secured_contexts[index] = + (uint8_t *)secured_context + secured_context_size * index; + } + + return libspdm_init_context_with_secured_context(context, + secured_contexts, + LIBSPDM_MAX_SESSION_COUNT); +} + +/** + * Reset an SPDM context. + * + * The size in bytes of the spdm_context can be returned by libspdm_get_context_size. + * + * @param spdm_context A pointer to the SPDM context. + */ +void libspdm_reset_context(void *context) +{ + libspdm_context_t *spdm_context; + size_t index; + + spdm_context = context; + + /*Clear all info about last connection*/ + + /*need clear session info to free context before algo is zeroed.*/ + for (index = 0; index < LIBSPDM_MAX_SESSION_COUNT; index++) + { + libspdm_session_info_init(spdm_context, + &spdm_context->session_info[index], + INVALID_SESSION_ID, + false); + } + + spdm_context->connection_info.connection_state = LIBSPDM_CONNECTION_STATE_NOT_STARTED; + libspdm_zero_mem(&spdm_context->connection_info.version, sizeof(spdm_version_number_t)); + libspdm_zero_mem(&spdm_context->connection_info.capability, + sizeof(libspdm_device_capability_t)); + libspdm_zero_mem(&spdm_context->connection_info.algorithm, sizeof(libspdm_device_algorithm_t)); + libspdm_zero_mem(&spdm_context->last_spdm_error, sizeof(libspdm_error_struct_t)); + libspdm_zero_mem(&spdm_context->encap_context, sizeof(libspdm_encap_context_t)); + spdm_context->connection_info.local_used_cert_chain_buffer_size = 0; + spdm_context->connection_info.local_used_cert_chain_buffer = NULL; + spdm_context->cache_spdm_request_size = 0; + spdm_context->retry_times = LIBSPDM_MAX_REQUEST_RETRY_TIMES; + spdm_context->response_state = LIBSPDM_RESPONSE_STATE_NORMAL; + spdm_context->current_token = 0; + spdm_context->last_spdm_request_session_id = INVALID_SESSION_ID; + spdm_context->last_spdm_request_session_id_valid = false; + spdm_context->last_spdm_request_size = 0; + spdm_context->encap_context.certificate_chain_buffer.max_buffer_size = + sizeof(spdm_context->encap_context.certificate_chain_buffer.buffer); + + #if LIBSPDM_ENABLE_MSG_LOG + spdm_context->msg_log.buffer = NULL; + spdm_context->msg_log.max_buffer_size = 0; + spdm_context->msg_log.buffer_size = 0; + spdm_context->msg_log.mode = 0; + spdm_context->msg_log.status = 0; + #endif /* LIBSPDM_ENABLE_MSG_LOG */ +} + +/** + * Free the memory of contexts within the SPDM context. + * These are typically contexts whose memory has been allocated by the cryptography library. + * This function does not free the SPDM context itself. + * + * @param[in] spdm_context A pointer to the SPDM context. + * + */ +void libspdm_deinit_context(void *context) +{ +#if !(LIBSPDM_RECORD_TRANSCRIPT_DATA_SUPPORT) + libspdm_context_t *spdm_context; + void *pubkey_context; + bool is_requester; + uint8_t slot_index; + + spdm_context = context; + is_requester = spdm_context->local_context.is_requester; + + for (slot_index = 0; slot_index < SPDM_MAX_SLOT_COUNT; slot_index++) { + pubkey_context = spdm_context->connection_info.peer_used_cert_chain[slot_index]. + leaf_cert_public_key; + + if (pubkey_context != NULL) { + if (is_requester) { + libspdm_asym_free( + spdm_context->connection_info.algorithm.base_asym_algo, pubkey_context); + } else { + libspdm_req_asym_free( + spdm_context->connection_info.algorithm.req_base_asym_alg, pubkey_context); + } + + pubkey_context = NULL; + spdm_context->connection_info.peer_used_cert_chain[slot_index]. + leaf_cert_public_key = NULL; + } + } + +#endif +} + +/** + * Return the size in bytes of the SPDM context. This includes all + * secured message context data as well. + * + * For just the SPDM context size, use libspdm_get_context_size_without_secured_context. + * + * @return the size in bytes of the SPDM context and secured message contexts. + **/ +size_t libspdm_get_context_size(void) +{ + size_t size; + + size = sizeof(libspdm_context_t) + + libspdm_secured_message_get_context_size() * LIBSPDM_MAX_SESSION_COUNT; + LIBSPDM_ASSERT (size == LIBSPDM_CONTEXT_SIZE_ALL); + return size; +} + +/** + * Return the size in bytes of just the SPDM context, without secured message context. + * + * For the complete context size, use libspdm_get_context_size. + * + * @return the size in bytes of the SPDM context. + **/ +size_t libspdm_get_context_size_without_secured_context(void) +{ + size_t size; + + size = sizeof(libspdm_context_t); + LIBSPDM_ASSERT (size == LIBSPDM_CONTEXT_SIZE_WITHOUT_SECURED_CONTEXT); + return size; +} + +/** + * Return the SPDMversion field of the version number struct. + * + * @param ver Spdm version number struct. + * + * @return the SPDMversion of the version number struct. + **/ +uint8_t libspdm_get_version_from_version_number(const spdm_version_number_t ver) +{ + return (uint8_t)(ver >> SPDM_VERSION_NUMBER_SHIFT_BIT); +} + +/** + * Sort SPDMversion in descending order. + * + * @param spdm_context A pointer to the SPDM context. + * @param ver_set A pointer to the version set. + * @param ver_num Version number. + */ +void libspdm_version_number_sort(spdm_version_number_t *ver_set, size_t ver_num) +{ + size_t index; + size_t index_sort; + size_t index_max; + spdm_version_number_t version; + + /* Select sort */ + if (ver_num > 1) { + for (index_sort = 0; index_sort < ver_num; index_sort++) { + index_max = index_sort; + for (index = index_sort + 1; index < ver_num; index++) { + /* if ver_ser[index] higher than ver_set[index_max] */ + if (ver_set[index] > ver_set[index_max]) { + index_max = index; + } + } + /* swap ver_ser[index_min] and ver_set[index_sort] */ + version = ver_set[index_sort]; + ver_set[index_sort] = ver_set[index_max]; + ver_set[index_max] = version; + } + } +} + +/** + * Negotiate SPDMversion for connection. + * ver_set is the local version set of requester, res_ver_set is the version set of responder. + * + * @param common_version A pointer to store the common version. + * @param req_ver_set A pointer to the requester version set. + * @param req_ver_num Version number of requester. + * @param res_ver_set A pointer to the responder version set. + * @param res_ver_num Version number of responder. + * + * @retval true Negotiation successfully, connect version be saved to common_version. + * @retval false Negotiation failed. + */ +bool libspdm_negotiate_connection_version(spdm_version_number_t *common_version, + spdm_version_number_t *req_ver_set, + size_t req_ver_num, + const spdm_version_number_t *res_ver_set, + size_t res_ver_num) +{ + spdm_version_number_t req_version_list[LIBSPDM_MAX_VERSION_COUNT]; + spdm_version_number_t res_version_list[LIBSPDM_MAX_VERSION_COUNT]; + size_t req_index; + size_t res_index; + + if (req_ver_num > LIBSPDM_MAX_VERSION_COUNT || res_ver_num > LIBSPDM_MAX_VERSION_COUNT) { + return false; + } + + if (req_ver_set == NULL || req_ver_num == 0 || res_ver_set == NULL || res_ver_num == 0) { + return false; + } + + libspdm_zero_mem(req_version_list, sizeof(spdm_version_number_t) * LIBSPDM_MAX_VERSION_COUNT); + libspdm_zero_mem(res_version_list, sizeof(spdm_version_number_t) * LIBSPDM_MAX_VERSION_COUNT); + + libspdm_copy_mem(req_version_list, sizeof(spdm_version_number_t) * LIBSPDM_MAX_VERSION_COUNT, + req_ver_set, sizeof(spdm_version_number_t) * req_ver_num); + libspdm_copy_mem(res_version_list, sizeof(spdm_version_number_t) * LIBSPDM_MAX_VERSION_COUNT, + res_ver_set, sizeof(spdm_version_number_t) * res_ver_num); + + /* Sort SPDMversion in descending order. */ + libspdm_version_number_sort(req_version_list, req_ver_num); + libspdm_version_number_sort(res_version_list, res_ver_num); + + /** + * Find highest same version and make req_index point to it. + * If not found, return false. + **/ + for (res_index = 0; res_index < res_ver_num; res_index++) { + for (req_index = 0; req_index < req_ver_num; req_index++) { + if (libspdm_get_version_from_version_number(req_version_list[req_index]) == + libspdm_get_version_from_version_number(res_version_list[res_index])) { + *common_version = req_version_list[req_index]; + return true; + } + } + } + return false; +} diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/libraries/libspdm/2.3.1/library/spdm_common_lib/libspdm_com_context_data_session.c nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/libraries/libspdm/2.3.1/library/spdm_common_lib/libspdm_com_context_data_session.c --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/libraries/libspdm/2.3.1/library/spdm_common_lib/libspdm_com_context_data_session.c 1970-01-01 00:00:00.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/libraries/libspdm/2.3.1/library/spdm_common_lib/libspdm_com_context_data_session.c 2024-03-05 22:14:14.000000000 +0000 @@ -0,0 +1,266 @@ +/** + * Copyright Notice: + * Copyright 2021-2022 DMTF. All rights reserved. + * License: BSD 3-Clause License. For full text see link: https://github.com/DMTF/libspdm/blob/main/LICENSE.md + **/ + +#include "internal/libspdm_common_lib.h" + +/** + * This function initializes the session info. + * + * @param spdm_context A pointer to the SPDM context. + * @param session_id The SPDM session ID. + **/ +void libspdm_session_info_init(libspdm_context_t *spdm_context, + libspdm_session_info_t *session_info, + uint32_t session_id, bool use_psk) +{ + libspdm_session_type_t session_type; + uint32_t capabilities_flag; + + capabilities_flag = spdm_context->connection_info.capability.flags & + spdm_context->local_context.capability.flags; + switch (capabilities_flag & + (SPDM_GET_CAPABILITIES_REQUEST_FLAGS_ENCRYPT_CAP | + SPDM_GET_CAPABILITIES_REQUEST_FLAGS_MAC_CAP)) { + case 0: + session_type = LIBSPDM_SESSION_TYPE_NONE; + break; + case (SPDM_GET_CAPABILITIES_REQUEST_FLAGS_ENCRYPT_CAP | + SPDM_GET_CAPABILITIES_REQUEST_FLAGS_MAC_CAP): + session_type = LIBSPDM_SESSION_TYPE_ENC_MAC; + break; + case SPDM_GET_CAPABILITIES_REQUEST_FLAGS_MAC_CAP: + session_type = LIBSPDM_SESSION_TYPE_MAC_ONLY; + break; + default: + LIBSPDM_ASSERT(false); + session_type = LIBSPDM_SESSION_TYPE_MAX; + break; + } + +#if !(LIBSPDM_RECORD_TRANSCRIPT_DATA_SUPPORT) + if (session_info->session_transcript.digest_context_th != NULL) { + libspdm_hash_free (spdm_context->connection_info.algorithm.base_hash_algo, + session_info->session_transcript.digest_context_th); + session_info->session_transcript.digest_context_th = NULL; + } + if (session_info->session_transcript.digest_context_th_backup != NULL) { + libspdm_hash_free (spdm_context->connection_info.algorithm.base_hash_algo, + session_info->session_transcript.digest_context_th_backup); + session_info->session_transcript.digest_context_th_backup = NULL; + } +#endif + + libspdm_zero_mem (&(session_info->last_key_update_request), sizeof(spdm_key_update_request_t)); + libspdm_zero_mem(session_info, offsetof(libspdm_session_info_t, secured_message_context)); + libspdm_secured_message_init_context(session_info->secured_message_context); + session_info->session_id = session_id; + session_info->use_psk = use_psk; + libspdm_secured_message_set_use_psk(session_info->secured_message_context, use_psk); + libspdm_secured_message_set_session_type(session_info->secured_message_context, session_type); + libspdm_secured_message_set_algorithms( + session_info->secured_message_context, + spdm_context->connection_info.version, + spdm_context->connection_info.secured_message_version, + spdm_context->connection_info.algorithm.base_hash_algo, + spdm_context->connection_info.algorithm.dhe_named_group, + spdm_context->connection_info.algorithm.aead_cipher_suite, + spdm_context->connection_info.algorithm.key_schedule); +#if LIBSPDM_RECORD_TRANSCRIPT_DATA_SUPPORT + session_info->session_transcript.message_k.max_buffer_size = + sizeof(session_info->session_transcript.message_k.buffer); + session_info->session_transcript.message_f.max_buffer_size = + sizeof(session_info->session_transcript.message_f.buffer); + session_info->session_transcript.message_m.max_buffer_size = + sizeof(session_info->session_transcript.message_m.buffer); +#endif +} + +/** + * Set the psk_hint to a session info. + * + * @param session_info A pointer to a session info. + * @param psk_hint Indicate the PSK hint. + * @param psk_hint_size The size in bytes of the PSK hint. + */ +void libspdm_session_info_set_psk_hint(libspdm_session_info_t *session_info, + const void *psk_hint, + size_t psk_hint_size) +{ + libspdm_secured_message_set_psk_hint( + session_info->secured_message_context, + psk_hint, + psk_hint_size); +} + +/** + * This function gets the session info via session ID. + * + * @param spdm_context A pointer to the SPDM context. + * @param session_id The SPDM session ID. + * + * @return session info. + **/ +void *libspdm_get_session_info_via_session_id(void *context, uint32_t session_id) +{ + libspdm_context_t *spdm_context; + libspdm_session_info_t *session_info; + size_t index; + + if (session_id == INVALID_SESSION_ID) { + LIBSPDM_DEBUG((LIBSPDM_DEBUG_ERROR, + "libspdm_get_session_info_via_session_id - Invalid session_id\n")); + LIBSPDM_ASSERT(false); + return NULL; + } + + spdm_context = context; + + session_info = (libspdm_session_info_t *)spdm_context->session_info; + for (index = 0; index < LIBSPDM_MAX_SESSION_COUNT; index++) { + if (session_info[index].session_id == session_id) { + return &session_info[index]; + } + } + + LIBSPDM_DEBUG((LIBSPDM_DEBUG_ERROR, + "libspdm_get_session_info_via_session_id - not found session_id\n")); + return NULL; +} + +/** + * This function gets the secured message context via session ID. + * + * @param spdm_context A pointer to the SPDM context. + * @param session_id The SPDM session ID. + * + * @return secured message context. + **/ +void *libspdm_get_secured_message_context_via_session_id(void *spdm_context, uint32_t session_id) +{ + libspdm_session_info_t *session_info; + + session_info = libspdm_get_session_info_via_session_id(spdm_context, session_id); + if (session_info == NULL) { + return NULL; + } else { + return session_info->secured_message_context; + } +} + +/** + * This function gets the secured message context via session ID. + * + * @param spdm_session_info A pointer to the SPDM context. + * + * @return secured message context. + **/ +void *libspdm_get_secured_message_context_via_session_info(void *spdm_session_info) +{ + libspdm_session_info_t *session_info; + + session_info = spdm_session_info; + if (session_info == NULL) { + return NULL; + } else { + return session_info->secured_message_context; + } +} + +/** + * This function generate a new session ID by concatnating req_session_id and rsp_session_id. + * + * @param[in] req_session_id + * @param[in] rsp_session_id + * + * @return this new session ID. + **/ +uint32_t libspdm_generate_session_id(uint16_t req_session_id, uint16_t rsp_session_id) +{ + uint32_t session_id; + session_id = (rsp_session_id << 16) | req_session_id; + return session_id; +} + +/** + * This function assigns a new session ID. + * + * @param spdm_context A pointer to the SPDM context. + * @param session_id The SPDM session ID. + * + * @return session info associated with this new session ID. + **/ +void *libspdm_assign_session_id(void *context, uint32_t session_id, bool use_psk) +{ + libspdm_context_t *spdm_context; + libspdm_session_info_t *session_info; + size_t index; + + spdm_context = context; + + if (session_id == INVALID_SESSION_ID) { + LIBSPDM_DEBUG((LIBSPDM_DEBUG_ERROR, "libspdm_assign_session_id - Invalid session_id\n")); + LIBSPDM_ASSERT(false); + return NULL; + } + + session_info = spdm_context->session_info; + + for (index = 0; index < LIBSPDM_MAX_SESSION_COUNT; index++) { + if (session_info[index].session_id == session_id) { + LIBSPDM_DEBUG((LIBSPDM_DEBUG_ERROR, + "libspdm_assign_session_id - Duplicated session_id\n")); + LIBSPDM_ASSERT(false); + return NULL; + } + } + + for (index = 0; index < LIBSPDM_MAX_SESSION_COUNT; index++) { + if (session_info[index].session_id == INVALID_SESSION_ID) { + libspdm_session_info_init(spdm_context, + &session_info[index], session_id, + use_psk); + spdm_context->latest_session_id = session_id; + return &session_info[index]; + } + } + + LIBSPDM_DEBUG((LIBSPDM_DEBUG_ERROR, "libspdm_assign_session_id - MAX session_id\n")); + return NULL; +} + +/** + * This function frees a session ID. + * + * @param spdm_context A pointer to the SPDM context. + * @param session_id The SPDM session ID. + **/ +void libspdm_free_session_id(void *context, uint32_t session_id) +{ + libspdm_context_t *spdm_context; + libspdm_session_info_t *session_info; + size_t index; + + spdm_context = context; + + if (session_id == INVALID_SESSION_ID) { + LIBSPDM_DEBUG((LIBSPDM_DEBUG_ERROR, "libspdm_free_session_id - Invalid session_id\n")); + LIBSPDM_ASSERT(false); + return; + } + + session_info = spdm_context->session_info; + for (index = 0; index < LIBSPDM_MAX_SESSION_COUNT; index++) { + if (session_info[index].session_id == session_id) { + libspdm_session_info_init(spdm_context, + &session_info[index], + INVALID_SESSION_ID, false); + return; + } + } + + LIBSPDM_DEBUG((LIBSPDM_DEBUG_ERROR, "libspdm_free_session_id - MAX session_id\n")); + LIBSPDM_ASSERT(false); +} diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/libraries/libspdm/2.3.1/library/spdm_common_lib/libspdm_com_crypto_service.c nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/libraries/libspdm/2.3.1/library/spdm_common_lib/libspdm_com_crypto_service.c --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/libraries/libspdm/2.3.1/library/spdm_common_lib/libspdm_com_crypto_service.c 1970-01-01 00:00:00.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/libraries/libspdm/2.3.1/library/spdm_common_lib/libspdm_com_crypto_service.c 2024-03-05 22:14:14.000000000 +0000 @@ -0,0 +1,1147 @@ +/** + * Copyright Notice: + * Copyright 2021-2022 DMTF. All rights reserved. + * License: BSD 3-Clause License. For full text see link: https://github.com/DMTF/libspdm/blob/main/LICENSE.md + **/ + +#include "internal/libspdm_common_lib.h" + +/** + * This function returns peer certificate chain buffer including spdm_cert_chain_t header. + * + * @param spdm_context A pointer to the SPDM context. + * @param cert_chain_buffer Certitiface chain buffer including spdm_cert_chain_t header. + * @param cert_chain_buffer_size size in bytes of the certitiface chain buffer. + * + * @retval true Peer certificate chain buffer including spdm_cert_chain_t header is returned. + * @retval false Peer certificate chain buffer including spdm_cert_chain_t header is not found. + **/ +bool libspdm_get_peer_cert_chain_buffer(void *context, + const void **cert_chain_buffer, + size_t *cert_chain_buffer_size) +{ + libspdm_context_t *spdm_context; +#if LIBSPDM_RECORD_TRANSCRIPT_DATA_SUPPORT + uint8_t slot_id; +#endif + + spdm_context = context; +#if LIBSPDM_RECORD_TRANSCRIPT_DATA_SUPPORT + slot_id = spdm_context->connection_info.peer_used_cert_chain_slot_id; + LIBSPDM_ASSERT(slot_id < SPDM_MAX_SLOT_COUNT); + if (spdm_context->connection_info.peer_used_cert_chain[slot_id].buffer_size != 0) { + *cert_chain_buffer = spdm_context->connection_info.peer_used_cert_chain[slot_id].buffer; + *cert_chain_buffer_size = spdm_context->connection_info + .peer_used_cert_chain[slot_id].buffer_size; + return true; + } +#endif + if (spdm_context->local_context.peer_cert_chain_provision_size != 0) { + *cert_chain_buffer = spdm_context->local_context.peer_cert_chain_provision; + *cert_chain_buffer_size = spdm_context->local_context.peer_cert_chain_provision_size; + return true; + } + return false; +} + +/** + * This function returns peer certificate chain data without spdm_cert_chain_t header. + * + * @param spdm_context A pointer to the SPDM context. + * @param cert_chain_data Certitiface chain data without spdm_cert_chain_t header. + * @param cert_chain_data_size size in bytes of the certitiface chain data. + * + * @retval true Peer certificate chain data without spdm_cert_chain_t header is returned. + * @retval false Peer certificate chain data without spdm_cert_chain_t header is not found. + **/ +bool libspdm_get_peer_cert_chain_data(void *context, + const void **cert_chain_data, + size_t *cert_chain_data_size) +{ + libspdm_context_t *spdm_context; + bool result; + size_t hash_size; + + spdm_context = context; + + result = libspdm_get_peer_cert_chain_buffer(spdm_context, cert_chain_data, + cert_chain_data_size); + if (!result) { + return false; + } + + hash_size = libspdm_get_hash_size(spdm_context->connection_info.algorithm.base_hash_algo); + + *cert_chain_data = (const uint8_t *)*cert_chain_data + sizeof(spdm_cert_chain_t) + hash_size; + *cert_chain_data_size = *cert_chain_data_size - (sizeof(spdm_cert_chain_t) + hash_size); + + return true; +} + +/** + * This function returns local used certificate chain buffer including spdm_cert_chain_t header. + * + * @param spdm_context A pointer to the SPDM context. + * @param cert_chain_buffer Certitiface chain buffer including spdm_cert_chain_t header. + * @param cert_chain_buffer_size size in bytes of the certitiface chain buffer. + * + * @retval true Local used certificate chain buffer including spdm_cert_chain_t header is returned. + * @retval false Local used certificate chain buffer including spdm_cert_chain_t header is not found. + **/ +bool libspdm_get_local_cert_chain_buffer(void *context, + const void **cert_chain_buffer, + size_t *cert_chain_buffer_size) +{ + libspdm_context_t *spdm_context; + + spdm_context = context; + if (spdm_context->connection_info.local_used_cert_chain_buffer_size != 0) { + *cert_chain_buffer = spdm_context->connection_info.local_used_cert_chain_buffer; + *cert_chain_buffer_size = spdm_context->connection_info.local_used_cert_chain_buffer_size; + return true; + } + return false; +} + +/** + * This function returns local used certificate chain data without spdm_cert_chain_t header. + * + * @param spdm_context A pointer to the SPDM context. + * @param cert_chain_data Certitiface chain data without spdm_cert_chain_t header. + * @param cert_chain_data_size size in bytes of the certitiface chain data. + * + * @retval true Local used certificate chain data without spdm_cert_chain_t header is returned. + * @retval false Local used certificate chain data without spdm_cert_chain_t header is not found. + **/ +bool libspdm_get_local_cert_chain_data(void *context, + const void **cert_chain_data, + size_t *cert_chain_data_size) +{ + libspdm_context_t *spdm_context; + bool result; + size_t hash_size; + + spdm_context = context; + + result = libspdm_get_local_cert_chain_buffer(spdm_context, cert_chain_data, + cert_chain_data_size); + if (!result) { + return false; + } + + hash_size = libspdm_get_hash_size(spdm_context->connection_info.algorithm.base_hash_algo); + + *cert_chain_data = (const uint8_t *)*cert_chain_data + sizeof(spdm_cert_chain_t) + hash_size; + *cert_chain_data_size = *cert_chain_data_size - (sizeof(spdm_cert_chain_t) + hash_size); + return true; +} + +#if LIBSPDM_RECORD_TRANSCRIPT_DATA_SUPPORT +/* + * This function calculates l1l2. + * If session_info is NULL, this function will use M cache of SPDM context, + * else will use M cache of SPDM session context. + * + * @param spdm_context A pointer to the SPDM context. + * @param session_info A pointer to the SPDM session context. + * @param l1l2 The buffer to store the l1l2. + * + * @retval RETURN_SUCCESS l1l2 is calculated. + */ +bool libspdm_calculate_l1l2(void *context, void *session_info, + libspdm_large_managed_buffer_t *l1l2) +{ + libspdm_context_t *spdm_context; + libspdm_return_t status; + libspdm_session_info_t *spdm_session_info; + + spdm_context = context; + spdm_session_info = session_info; + + libspdm_init_managed_buffer(l1l2, LIBSPDM_MAX_MESSAGE_BUFFER_SIZE); + + if ((spdm_context->connection_info.version >> SPDM_VERSION_NUMBER_SHIFT_BIT) > + SPDM_MESSAGE_VERSION_11) { + + /* Need append VCA since 1.2 script*/ + + LIBSPDM_DEBUG((LIBSPDM_DEBUG_INFO, "message_a data :\n")); + LIBSPDM_INTERNAL_DUMP_HEX( + libspdm_get_managed_buffer(&spdm_context->transcript.message_a), + libspdm_get_managed_buffer_size(&spdm_context->transcript.message_a)); + status = libspdm_append_managed_buffer( + l1l2, + libspdm_get_managed_buffer(&spdm_context->transcript.message_a), + libspdm_get_managed_buffer_size(&spdm_context->transcript.message_a)); + if (LIBSPDM_STATUS_IS_ERROR(status)) { + return false; + } + } + + if (spdm_session_info == NULL) { + LIBSPDM_DEBUG((LIBSPDM_DEBUG_INFO, "message_m data :\n")); + LIBSPDM_INTERNAL_DUMP_HEX( + libspdm_get_managed_buffer(&spdm_context->transcript.message_m), + libspdm_get_managed_buffer_size(&spdm_context->transcript.message_m)); + status = libspdm_append_managed_buffer( + l1l2, + libspdm_get_managed_buffer(&spdm_context->transcript.message_m), + libspdm_get_managed_buffer_size(&spdm_context->transcript.message_m)); + } else { + LIBSPDM_DEBUG((LIBSPDM_DEBUG_INFO, "use message_m in session :\n")); + LIBSPDM_INTERNAL_DUMP_HEX( + libspdm_get_managed_buffer(&spdm_session_info->session_transcript.message_m), + libspdm_get_managed_buffer_size(&spdm_session_info->session_transcript.message_m)); + status = libspdm_append_managed_buffer( + l1l2, + libspdm_get_managed_buffer(&spdm_session_info->session_transcript.message_m), + libspdm_get_managed_buffer_size(&spdm_session_info->session_transcript.message_m)); + } + if (LIBSPDM_STATUS_IS_ERROR(status)) { + return false; + } + + /* Debug code only - calculate and print value of l1l2 hash*/ + LIBSPDM_DEBUG_CODE( + uint8_t hash_data[LIBSPDM_MAX_HASH_SIZE]; + uint32_t hash_size = libspdm_get_hash_size( + spdm_context->connection_info.algorithm.base_hash_algo); + if (!libspdm_hash_all( + spdm_context->connection_info.algorithm.base_hash_algo, + libspdm_get_managed_buffer(l1l2), + libspdm_get_managed_buffer_size(l1l2), hash_data)) { + return false; + } + LIBSPDM_DEBUG((LIBSPDM_DEBUG_INFO, "l1l2 hash - ")); + LIBSPDM_INTERNAL_DUMP_DATA(hash_data, hash_size); + LIBSPDM_DEBUG((LIBSPDM_DEBUG_INFO, "\n")); + ); + + return true; +} +#else +/* + * This function calculates l1l2 hash. + * If session_info is NULL, this function will use M cache of SPDM context, + * else will use M cache of SPDM session context. + * + * @param spdm_context A pointer to the SPDM context. + * @param session_info A pointer to the SPDM session context. + * @param l1l2_hash_size size in bytes of the l1l2 hash + * @param l1l2_hash The buffer to store the l1l2 hash + * + * @retval RETURN_SUCCESS l1l2 is calculated. + */ +bool libspdm_calculate_l1l2_hash(void *context, void *session_info, + size_t *l1l2_hash_size, void *l1l2_hash) +{ + libspdm_context_t *spdm_context; + libspdm_session_info_t *spdm_session_info; + bool result; + + uint32_t hash_size; + + spdm_context = context; + spdm_session_info = session_info; + + hash_size = libspdm_get_hash_size(spdm_context->connection_info.algorithm.base_hash_algo); + + if (spdm_session_info == NULL) { + result = libspdm_hash_final (spdm_context->connection_info.algorithm.base_hash_algo, + spdm_context->transcript.digest_context_l1l2, l1l2_hash); + } else { + LIBSPDM_DEBUG((LIBSPDM_DEBUG_INFO, "use message_m in session :\n")); + result = libspdm_hash_final (spdm_context->connection_info.algorithm.base_hash_algo, + spdm_session_info->session_transcript.digest_context_l1l2, + l1l2_hash); + } + if (!result) { + return false; + } + LIBSPDM_DEBUG((LIBSPDM_DEBUG_INFO, "l1l2 hash - ")); + LIBSPDM_INTERNAL_DUMP_DATA(l1l2_hash, hash_size); + LIBSPDM_DEBUG((LIBSPDM_DEBUG_INFO, "\n")); + + *l1l2_hash_size = hash_size; + + return true; +} +#endif /* LIBSPDM_RECORD_TRANSCRIPT_DATA_SUPPORT */ + +#if LIBSPDM_RECORD_TRANSCRIPT_DATA_SUPPORT +/* + * This function calculates m1m2. + * + * @param spdm_context A pointer to the SPDM context. + * @param is_mut Indicate if this is from mutual authentication. + * @param m1m2 The buffer to store the m1m2 + * + * @retval RETURN_SUCCESS m1m2 is calculated. + */ +static bool libspdm_calculate_m1m2(void *context, bool is_mut, + libspdm_large_managed_buffer_t *m1m2) +{ + libspdm_context_t *spdm_context; + libspdm_return_t status; + + spdm_context = context; + + libspdm_init_managed_buffer(m1m2, LIBSPDM_MAX_MESSAGE_BUFFER_SIZE); + + if (is_mut) { + if ((spdm_context->connection_info.version >> SPDM_VERSION_NUMBER_SHIFT_BIT) > + SPDM_MESSAGE_VERSION_11) { + LIBSPDM_DEBUG((LIBSPDM_DEBUG_INFO, "message_a data :\n")); + LIBSPDM_INTERNAL_DUMP_HEX( + libspdm_get_managed_buffer(&spdm_context->transcript.message_a), + libspdm_get_managed_buffer_size(&spdm_context->transcript.message_a)); + status = libspdm_append_managed_buffer( + m1m2, + libspdm_get_managed_buffer(&spdm_context->transcript.message_a), + libspdm_get_managed_buffer_size(&spdm_context->transcript.message_a)); + if (LIBSPDM_STATUS_IS_ERROR(status)) { + return false; + } + } + + LIBSPDM_DEBUG((LIBSPDM_DEBUG_INFO, "message_mut_b data :\n")); + LIBSPDM_INTERNAL_DUMP_HEX( + libspdm_get_managed_buffer(&spdm_context->transcript.message_mut_b), + libspdm_get_managed_buffer_size(&spdm_context->transcript.message_mut_b)); + status = libspdm_append_managed_buffer( + m1m2, + libspdm_get_managed_buffer(&spdm_context->transcript.message_mut_b), + libspdm_get_managed_buffer_size(&spdm_context->transcript.message_mut_b)); + if (LIBSPDM_STATUS_IS_ERROR(status)) { + return false; + } + + LIBSPDM_DEBUG((LIBSPDM_DEBUG_INFO, "message_mut_c data :\n")); + LIBSPDM_INTERNAL_DUMP_HEX( + libspdm_get_managed_buffer(&spdm_context->transcript.message_mut_c), + libspdm_get_managed_buffer_size(&spdm_context->transcript.message_mut_c)); + status = libspdm_append_managed_buffer( + m1m2, + libspdm_get_managed_buffer(&spdm_context->transcript.message_mut_c), + libspdm_get_managed_buffer_size(&spdm_context->transcript.message_mut_c)); + if (LIBSPDM_STATUS_IS_ERROR(status)) { + return false; + } + + /* Debug code only - calculate and print value of m1m2 mut hash*/ + LIBSPDM_DEBUG_CODE( + uint8_t hash_data[LIBSPDM_MAX_HASH_SIZE]; + uint32_t hash_size = libspdm_get_hash_size( + spdm_context->connection_info.algorithm.base_hash_algo); + if (!libspdm_hash_all( + spdm_context->connection_info.algorithm.base_hash_algo, + libspdm_get_managed_buffer(m1m2), + libspdm_get_managed_buffer_size(m1m2), hash_data)) { + return false; + } + LIBSPDM_DEBUG((LIBSPDM_DEBUG_INFO, "m1m2 Mut hash - ")); + LIBSPDM_INTERNAL_DUMP_DATA(hash_data, hash_size); + LIBSPDM_DEBUG((LIBSPDM_DEBUG_INFO, "\n")); + ); + + } else { + LIBSPDM_DEBUG((LIBSPDM_DEBUG_INFO, "message_a data :\n")); + LIBSPDM_INTERNAL_DUMP_HEX( + libspdm_get_managed_buffer(&spdm_context->transcript.message_a), + libspdm_get_managed_buffer_size(&spdm_context->transcript.message_a)); + status = libspdm_append_managed_buffer( + m1m2, + libspdm_get_managed_buffer(&spdm_context->transcript.message_a), + libspdm_get_managed_buffer_size(&spdm_context->transcript.message_a)); + if (LIBSPDM_STATUS_IS_ERROR(status)) { + return false; + } + + LIBSPDM_DEBUG((LIBSPDM_DEBUG_INFO, "message_b data :\n")); + LIBSPDM_INTERNAL_DUMP_HEX( + libspdm_get_managed_buffer(&spdm_context->transcript.message_b), + libspdm_get_managed_buffer_size(&spdm_context->transcript.message_b)); + status = libspdm_append_managed_buffer( + m1m2, + libspdm_get_managed_buffer(&spdm_context->transcript.message_b), + libspdm_get_managed_buffer_size(&spdm_context->transcript.message_b)); + if (LIBSPDM_STATUS_IS_ERROR(status)) { + return false; + } + + LIBSPDM_DEBUG((LIBSPDM_DEBUG_INFO, "message_c data :\n")); + LIBSPDM_INTERNAL_DUMP_HEX( + libspdm_get_managed_buffer(&spdm_context->transcript.message_c), + libspdm_get_managed_buffer_size(&spdm_context->transcript.message_c)); + status = libspdm_append_managed_buffer( + m1m2, + libspdm_get_managed_buffer(&spdm_context->transcript.message_c), + libspdm_get_managed_buffer_size(&spdm_context->transcript.message_c)); + if (LIBSPDM_STATUS_IS_ERROR(status)) { + return false; + } + + /* Debug code only - calculate and print value of m1m2 hash*/ + LIBSPDM_DEBUG_CODE( + uint8_t hash_data[LIBSPDM_MAX_HASH_SIZE]; + uint32_t hash_size = libspdm_get_hash_size( + spdm_context->connection_info.algorithm.base_hash_algo); + if (!libspdm_hash_all( + spdm_context->connection_info.algorithm.base_hash_algo, + libspdm_get_managed_buffer(m1m2), + libspdm_get_managed_buffer_size(m1m2), hash_data)) { + return false; + } + LIBSPDM_DEBUG((LIBSPDM_DEBUG_INFO, "m1m2 hash - ")); + LIBSPDM_INTERNAL_DUMP_DATA(hash_data, hash_size); + LIBSPDM_DEBUG((LIBSPDM_DEBUG_INFO, "\n")); + ); + } + + return true; +} +#else +/* + * This function calculates m1m2 hash. + * + * @param spdm_context A pointer to the SPDM context. + * @param is_mut Indicate if this is from mutual authentication. + * @param m1m2_hash_size size in bytes of the m1m2 hash + * @param m1m2_hash The buffer to store the m1m2 hash + * + * @retval RETURN_SUCCESS m1m2 is calculated. + */ +static bool libspdm_calculate_m1m2_hash(void *context, bool is_mut, + size_t *m1m2_hash_size, + void *m1m2_hash) +{ + libspdm_context_t *spdm_context; + uint32_t hash_size; + bool result; + + spdm_context = context; + + hash_size = libspdm_get_hash_size(spdm_context->connection_info.algorithm.base_hash_algo); + + if (is_mut) { + result = libspdm_hash_final (spdm_context->connection_info.algorithm.base_hash_algo, + spdm_context->transcript.digest_context_mut_m1m2, m1m2_hash); + if (!result) { + return false; + } + LIBSPDM_DEBUG((LIBSPDM_DEBUG_INFO, "m1m2 Mut hash - ")); + LIBSPDM_INTERNAL_DUMP_DATA(m1m2_hash, hash_size); + LIBSPDM_DEBUG((LIBSPDM_DEBUG_INFO, "\n")); + + } else { + result = libspdm_hash_final (spdm_context->connection_info.algorithm.base_hash_algo, + spdm_context->transcript.digest_context_m1m2, m1m2_hash); + if (!result) { + return false; + } + LIBSPDM_DEBUG((LIBSPDM_DEBUG_INFO, "m1m2 hash - ")); + LIBSPDM_INTERNAL_DUMP_DATA(m1m2_hash, hash_size); + LIBSPDM_DEBUG((LIBSPDM_DEBUG_INFO, "\n")); + } + + *m1m2_hash_size = hash_size; + + return true; +} +#endif + +/** + * This function generates the certificate chain hash. + * + * @param spdm_context A pointer to the SPDM context. + * @param slot_id The slot index of the certificate chain. + * @param signature The buffer to store the certificate chain hash. + * + * @retval true certificate chain hash is generated. + * @retval false certificate chain hash is not generated. + **/ +bool libspdm_generate_cert_chain_hash(libspdm_context_t *spdm_context, + size_t slot_id, uint8_t *hash) +{ + LIBSPDM_ASSERT(slot_id < SPDM_MAX_SLOT_COUNT); + return libspdm_hash_all( + spdm_context->connection_info.algorithm.base_hash_algo, + spdm_context->local_context.local_cert_chain_provision[slot_id], + spdm_context->local_context.local_cert_chain_provision_size[slot_id], hash); +} + +/** + * Get the certificate slot mask + * + * @param[in] context A pointer to the SPDM context. + * + * @retval slot_mask get slot mask + **/ +uint8_t libspdm_get_cert_slot_mask(libspdm_context_t *spdm_context) +{ + size_t index; + uint8_t slot_mask; + + slot_mask = 0; + for (index = 0; index < SPDM_MAX_SLOT_COUNT; index++) { + if (spdm_context->local_context.local_cert_chain_provision[index] != NULL) { + slot_mask |= (1 << index); + } + } + + return slot_mask; +} + +/** + * Get the certificate slot count + * + * @param[in] context A pointer to the SPDM context. + * + * @retval slot_count get slot count + **/ +uint8_t libspdm_get_cert_slot_count(libspdm_context_t *spdm_context) +{ + size_t index; + uint8_t slot_count; + + slot_count = 0; + for (index = 0; index < SPDM_MAX_SLOT_COUNT; index++) { + if (spdm_context->local_context.local_cert_chain_provision[index] != NULL) { + slot_count++; + } + } + + return slot_count; +} + +/** + * This function verifies the digest. + * + * @param spdm_context A pointer to the SPDM context. + * @param digest The digest data buffer. + * @param digest_count size of the digest data buffer. + * + * @retval true digest verification pass. + * @retval false digest verification fail. + **/ +bool libspdm_verify_peer_digests(libspdm_context_t *spdm_context, const void *digest, + size_t digest_count) +{ + size_t hash_size; + const uint8_t *hash_buffer; + uint8_t cert_chain_buffer_hash[LIBSPDM_MAX_HASH_SIZE]; + const uint8_t *cert_chain_buffer; + size_t cert_chain_buffer_size; + size_t index; + bool result; + + cert_chain_buffer = spdm_context->local_context.peer_cert_chain_provision; + cert_chain_buffer_size = spdm_context->local_context.peer_cert_chain_provision_size; + if ((cert_chain_buffer != NULL) && (cert_chain_buffer_size != 0)) { + hash_size = libspdm_get_hash_size(spdm_context->connection_info.algorithm.base_hash_algo); + hash_buffer = digest; + + result = libspdm_hash_all( + spdm_context->connection_info.algorithm.base_hash_algo, + cert_chain_buffer, cert_chain_buffer_size, + cert_chain_buffer_hash); + if (!result) { + LIBSPDM_DEBUG((LIBSPDM_DEBUG_INFO, + "!!! verify_peer_digests - FAIL (hash calculation) !!!\n")); + return false; + } + + for (index = 0; index < digest_count; index++) + { + if (libspdm_const_compare_mem(hash_buffer, cert_chain_buffer_hash, hash_size) == 0) { + LIBSPDM_DEBUG((LIBSPDM_DEBUG_INFO, "!!! verify_peer_digests - PASS !!!\n")); + return true; + } + hash_buffer += hash_size; + } + + LIBSPDM_DEBUG((LIBSPDM_DEBUG_INFO, "!!! verify_peer_digests - FAIL !!!\n")); + return false; + } else { + LIBSPDM_DEBUG((LIBSPDM_DEBUG_INFO, "!!! verify_peer_digests - PASS !!!\n")); + } + return true; +} + +/** + * This function verifies peer certificate chain buffer including spdm_cert_chain_t header. + * + * @param spdm_context A pointer to the SPDM context. + * @param cert_chain_buffer Certitiface chain buffer including spdm_cert_chain_t header. + * @param cert_chain_buffer_size size in bytes of the certitiface chain buffer. + * @param trust_anchor A buffer to hold the trust_anchor which is used to validate the peer certificate, if not NULL. + * @param trust_anchor_size A buffer to hold the trust_anchor_size, if not NULL. + * @param is_requester Indicates if it is a requester message. + * + * @retval true Peer certificate chain buffer verification passed. + * @retval false Peer certificate chain buffer verification failed. + **/ +bool libspdm_verify_peer_cert_chain_buffer(libspdm_context_t *spdm_context, + const void *cert_chain_buffer, + size_t cert_chain_buffer_size, + const void **trust_anchor, + size_t *trust_anchor_size, + bool is_requester) +{ + const uint8_t *cert_chain_data; + size_t cert_chain_data_size; + const uint8_t *root_cert; + size_t root_cert_size; + uint8_t root_cert_hash[LIBSPDM_MAX_HASH_SIZE]; + size_t root_cert_hash_size; + const uint8_t *received_root_cert; + size_t received_root_cert_size; + bool result; + uint8_t root_cert_index; + bool is_device_cert_model; + + if((spdm_context->connection_info.capability.flags & + SPDM_GET_CAPABILITIES_RESPONSE_FLAGS_ALIAS_CERT_CAP) == 0) { + is_device_cert_model = true; + } else { + is_device_cert_model = false; + } + + if (is_requester) { + result = libspdm_verify_certificate_chain_buffer( + spdm_context->connection_info.algorithm.base_hash_algo, + spdm_context->connection_info.algorithm.base_asym_algo, + cert_chain_buffer, cert_chain_buffer_size, is_device_cert_model); + } else { + result = libspdm_verify_certificate_chain_buffer( + spdm_context->connection_info.algorithm.base_hash_algo, + spdm_context->connection_info.algorithm.req_base_asym_alg, + cert_chain_buffer, cert_chain_buffer_size, is_device_cert_model); + } + if (!result) { + return false; + } + + root_cert_index = 0; + root_cert = spdm_context->local_context.peer_root_cert_provision[root_cert_index]; + root_cert_size = spdm_context->local_context.peer_root_cert_provision_size[root_cert_index]; + cert_chain_data = spdm_context->local_context.peer_cert_chain_provision; + cert_chain_data_size = spdm_context->local_context.peer_cert_chain_provision_size; + + root_cert_hash_size = libspdm_get_hash_size( + spdm_context->connection_info.algorithm.base_hash_algo); + + if ((root_cert != NULL) && (root_cert_size != 0)) { + while ((root_cert != NULL) && (root_cert_size != 0)) { + result = libspdm_hash_all( + spdm_context->connection_info.algorithm.base_hash_algo, + root_cert, root_cert_size, root_cert_hash); + if (!result) { + LIBSPDM_DEBUG((LIBSPDM_DEBUG_INFO, + "!!! verify_peer_cert_chain_buffer - FAIL (hash calculation) !!!\n")); + return false; + } + + if (libspdm_const_compare_mem((const uint8_t *)cert_chain_buffer + + sizeof(spdm_cert_chain_t), + root_cert_hash, root_cert_hash_size) == 0) { + break; + } + + #if (LIBSPDM_MAX_ROOT_CERT_SUPPORT) > 1 + if ((root_cert_index < ((LIBSPDM_MAX_ROOT_CERT_SUPPORT) -1)) && + (spdm_context->local_context.peer_root_cert_provision[root_cert_index + 1] != + NULL)) { + root_cert_index++; + root_cert = spdm_context->local_context.peer_root_cert_provision[root_cert_index]; + root_cert_size = + spdm_context->local_context.peer_root_cert_provision_size[root_cert_index]; + } else + #endif /* LIBSPDM_MAX_ROOT_CERT_SUPPORT */ + { + LIBSPDM_DEBUG((LIBSPDM_DEBUG_INFO, + "!!! verify_peer_cert_chain_buffer - " + "FAIL (all root cert hash mismatch) !!!\n")); + return false; + } + } + + result = libspdm_x509_get_cert_from_cert_chain( + (const uint8_t *)cert_chain_buffer + sizeof(spdm_cert_chain_t) + root_cert_hash_size, + cert_chain_buffer_size - sizeof(spdm_cert_chain_t) - root_cert_hash_size, + 0, &received_root_cert, &received_root_cert_size); + if (!result) { + LIBSPDM_DEBUG((LIBSPDM_DEBUG_INFO, + "!!! verify_peer_cert_chain_buffer - FAIL (cert retrieval fail) !!!\n")); + return false; + } + if (libspdm_is_root_certificate(received_root_cert, received_root_cert_size)) { + if ((root_cert != NULL) && + (libspdm_const_compare_mem(received_root_cert, root_cert, root_cert_size) != 0)) { + LIBSPDM_DEBUG((LIBSPDM_DEBUG_INFO, + "!!! verify_peer_cert_chain_buffer - " + "FAIL (root cert mismatch) !!!\n")); + return false; + } + } else { + if (!libspdm_x509_verify_cert(received_root_cert, received_root_cert_size, + root_cert, root_cert_size)) { + LIBSPDM_DEBUG((LIBSPDM_DEBUG_INFO, + "!!! verify_peer_cert_chain_buffer - " + "FAIL (received root cert verify failed)!!!\n")); + return false; + } + } + if (trust_anchor != NULL) { + *trust_anchor = root_cert; + } + if (trust_anchor_size != NULL) { + *trust_anchor_size = root_cert_size; + } + } else if ((cert_chain_data != NULL) && (cert_chain_data_size != 0)) { + /* Whether it contains the root certificate or not, + * it should be equal to the one provisioned in trusted environment*/ + if (cert_chain_data_size != cert_chain_buffer_size) { + LIBSPDM_DEBUG((LIBSPDM_DEBUG_INFO, "!!! verify_peer_cert_chain_buffer - FAIL !!!\n")); + return false; + } + if (libspdm_const_compare_mem(cert_chain_buffer, cert_chain_data, + cert_chain_buffer_size) != 0) { + LIBSPDM_DEBUG((LIBSPDM_DEBUG_INFO, "!!! verify_peer_cert_chain_buffer - FAIL !!!\n")); + return false; + } + if (trust_anchor != NULL) { + *trust_anchor = cert_chain_data + sizeof(spdm_cert_chain_t) + + libspdm_get_hash_size( + spdm_context->connection_info.algorithm.base_hash_algo); + } + if (trust_anchor_size != NULL) { + *trust_anchor_size = cert_chain_data_size; + } + } + /* + * When there is no root_cert and cert_chain_data in local_context, the return is true too. + * No provision means the caller wants to verify the trust anchor of the cert chain. + */ + LIBSPDM_DEBUG((LIBSPDM_DEBUG_INFO, "!!! verify_peer_cert_chain_buffer - PASS !!!\n")); + + return true; +} + +/** + * This function generates the challenge signature based upon m1m2 for authentication. + * + * @param spdm_context A pointer to the SPDM context. + * @param is_requester Indicate of the signature generation for a requester or a responder. + * @param signature The buffer to store the challenge signature. + * + * @retval true challenge signature is generated. + * @retval false challenge signature is not generated. + **/ +bool libspdm_generate_challenge_auth_signature(libspdm_context_t *spdm_context, + bool is_requester, + uint8_t *signature) +{ + bool result; + size_t signature_size; +#if LIBSPDM_RECORD_TRANSCRIPT_DATA_SUPPORT + libspdm_large_managed_buffer_t m1m2; + uint8_t *m1m2_buffer; + size_t m1m2_buffer_size; +#else + uint8_t m1m2_hash[LIBSPDM_MAX_HASH_SIZE]; + size_t m1m2_hash_size; +#endif + +#if LIBSPDM_RECORD_TRANSCRIPT_DATA_SUPPORT + result = libspdm_calculate_m1m2(spdm_context, is_requester, &m1m2); + m1m2_buffer = libspdm_get_managed_buffer(&m1m2); + m1m2_buffer_size = libspdm_get_managed_buffer_size(&m1m2); +#else + m1m2_hash_size = sizeof(m1m2_hash); + result = libspdm_calculate_m1m2_hash(spdm_context, is_requester, &m1m2_hash_size, &m1m2_hash); +#endif + if (is_requester) { + libspdm_reset_message_mut_b(spdm_context); + libspdm_reset_message_mut_c(spdm_context); + } else { + libspdm_reset_message_b(spdm_context); + libspdm_reset_message_c(spdm_context); + } + if (!result) { + return false; + } + + if (is_requester) { +#if LIBSPDM_ENABLE_CAPABILITY_MUT_AUTH_CAP + signature_size = libspdm_get_req_asym_signature_size( + spdm_context->connection_info.algorithm.req_base_asym_alg); +#if LIBSPDM_RECORD_TRANSCRIPT_DATA_SUPPORT + result = libspdm_requester_data_sign( + spdm_context->connection_info.version, SPDM_CHALLENGE_AUTH, + spdm_context->connection_info.algorithm.req_base_asym_alg, + spdm_context->connection_info.algorithm.base_hash_algo, + false, m1m2_buffer, m1m2_buffer_size, signature, &signature_size); +#else + result = libspdm_requester_data_sign( + spdm_context->connection_info.version, SPDM_CHALLENGE_AUTH, + spdm_context->connection_info.algorithm.req_base_asym_alg, + spdm_context->connection_info.algorithm.base_hash_algo, + true, m1m2_hash, m1m2_hash_size, signature, &signature_size); +#endif +#else /* LIBSPDM_ENABLE_CAPABILITY_MUT_AUTH_CAP */ + result = false; +#endif /* LIBSPDM_ENABLE_CAPABILITY_MUT_AUTH_CAP */ + } else { + signature_size = libspdm_get_asym_signature_size( + spdm_context->connection_info.algorithm.base_asym_algo); +#if LIBSPDM_RECORD_TRANSCRIPT_DATA_SUPPORT + result = libspdm_responder_data_sign( + spdm_context->connection_info.version, SPDM_CHALLENGE_AUTH, + spdm_context->connection_info.algorithm.base_asym_algo, + spdm_context->connection_info.algorithm.base_hash_algo, + false, m1m2_buffer, m1m2_buffer_size, signature, + &signature_size); +#else + result = libspdm_responder_data_sign( + spdm_context->connection_info.version, SPDM_CHALLENGE_AUTH, + spdm_context->connection_info.algorithm.base_asym_algo, + spdm_context->connection_info.algorithm.base_hash_algo, + true, m1m2_hash, m1m2_hash_size, signature, + &signature_size); +#endif + } + + return result; +} + +/** + * This function verifies the certificate chain hash. + * + * @param spdm_context A pointer to the SPDM context. + * @param certificate_chain_hash The certificate chain hash data buffer. + * @param certificate_chain_hash_size size in bytes of the certificate chain hash data buffer. + * + * @retval true hash verification pass. + * @retval false hash verification fail. + **/ +bool libspdm_verify_certificate_chain_hash(libspdm_context_t *spdm_context, + const void *certificate_chain_hash, + size_t certificate_chain_hash_size) +{ + size_t hash_size; + uint8_t cert_chain_buffer_hash[LIBSPDM_MAX_HASH_SIZE]; + const uint8_t *cert_chain_buffer; + size_t cert_chain_buffer_size; + bool result; +#if !(LIBSPDM_RECORD_TRANSCRIPT_DATA_SUPPORT) + uint8_t slot_id; +#endif + +#if LIBSPDM_RECORD_TRANSCRIPT_DATA_SUPPORT + result = libspdm_get_peer_cert_chain_buffer(spdm_context, + (const void **)&cert_chain_buffer, + &cert_chain_buffer_size); + if (!result) { + return false; + } + + hash_size = libspdm_get_hash_size(spdm_context->connection_info.algorithm.base_hash_algo); + + result = libspdm_hash_all(spdm_context->connection_info.algorithm.base_hash_algo, + cert_chain_buffer, cert_chain_buffer_size, + cert_chain_buffer_hash); + if (!result) { + LIBSPDM_DEBUG((LIBSPDM_DEBUG_INFO, + "!!! verify_certificate_chain_hash - FAIL (hash calculation) !!!\n")); + return false; + } + + if (hash_size != certificate_chain_hash_size) { + LIBSPDM_DEBUG((LIBSPDM_DEBUG_INFO, "!!! verify_certificate_chain_hash - FAIL !!!\n")); + return false; + } + if (libspdm_const_compare_mem(certificate_chain_hash, cert_chain_buffer_hash, + certificate_chain_hash_size) != 0) { + LIBSPDM_DEBUG((LIBSPDM_DEBUG_INFO, "!!! verify_certificate_chain_hash - FAIL !!!\n")); + return false; + } +#else + slot_id = spdm_context->connection_info.peer_used_cert_chain_slot_id; + LIBSPDM_ASSERT(slot_id < SPDM_MAX_SLOT_COUNT); + if (spdm_context->connection_info.peer_used_cert_chain[slot_id].buffer_hash_size != 0) { + if (spdm_context->connection_info.peer_used_cert_chain[slot_id].buffer_hash_size != + certificate_chain_hash_size) { + LIBSPDM_DEBUG((LIBSPDM_DEBUG_INFO, "!!! verify_certificate_chain_hash - FAIL !!!\n")); + return false; + } + + if (libspdm_const_compare_mem(certificate_chain_hash, + spdm_context->connection_info.peer_used_cert_chain[slot_id]. + buffer_hash, certificate_chain_hash_size) != 0) { + LIBSPDM_DEBUG((LIBSPDM_DEBUG_INFO, "!!! verify_certificate_chain_hash - FAIL !!!\n")); + return false; + } + + } else { + result = libspdm_get_peer_cert_chain_buffer(spdm_context, + (const void **)&cert_chain_buffer, + &cert_chain_buffer_size); + if (!result) { + return false; + } + + hash_size = libspdm_get_hash_size(spdm_context->connection_info.algorithm.base_hash_algo); + + result = libspdm_hash_all(spdm_context->connection_info.algorithm.base_hash_algo, + cert_chain_buffer, cert_chain_buffer_size, + cert_chain_buffer_hash); + if (!result) { + LIBSPDM_DEBUG((LIBSPDM_DEBUG_INFO, + "!!! verify_certificate_chain_hash - FAIL (hash calculation) !!!\n")); + return false; + } + + if (hash_size != certificate_chain_hash_size) { + LIBSPDM_DEBUG((LIBSPDM_DEBUG_INFO, "!!! verify_certificate_chain_hash - FAIL !!!\n")); + return false; + } + if (libspdm_const_compare_mem(certificate_chain_hash, cert_chain_buffer_hash, + certificate_chain_hash_size) != 0) { + LIBSPDM_DEBUG((LIBSPDM_DEBUG_INFO, "!!! verify_certificate_chain_hash - FAIL !!!\n")); + return false; + } + } +#endif + LIBSPDM_DEBUG((LIBSPDM_DEBUG_INFO, "!!! verify_certificate_chain_hash - PASS !!!\n")); + return true; +} + +/** + * This function verifies the challenge signature based upon m1m2. + * + * @param spdm_context A pointer to the SPDM context. + * @param is_requester Indicate of the signature verification for a requester or a responder. + * @param sign_data The signature data buffer. + * @param sign_data_size size in bytes of the signature data buffer. + * + * @retval true signature verification pass. + * @retval false signature verification fail. + **/ +bool libspdm_verify_challenge_auth_signature(libspdm_context_t *spdm_context, + bool is_requester, + const void *sign_data, + size_t sign_data_size) +{ + bool result; + const uint8_t *cert_buffer; + size_t cert_buffer_size; + void *context; + const uint8_t *cert_chain_data; + size_t cert_chain_data_size; +#if LIBSPDM_RECORD_TRANSCRIPT_DATA_SUPPORT + libspdm_large_managed_buffer_t m1m2; + uint8_t *m1m2_buffer; + size_t m1m2_buffer_size; +#else + uint8_t m1m2_hash[LIBSPDM_MAX_HASH_SIZE]; + size_t m1m2_hash_size; + uint8_t slot_id; +#endif + +#if LIBSPDM_RECORD_TRANSCRIPT_DATA_SUPPORT + result = libspdm_calculate_m1m2(spdm_context, !is_requester, &m1m2); +#else + m1m2_hash_size = sizeof(m1m2_hash); + result = libspdm_calculate_m1m2_hash(spdm_context, !is_requester, &m1m2_hash_size, &m1m2_hash); +#endif + if (is_requester) { + libspdm_reset_message_b(spdm_context); + libspdm_reset_message_c(spdm_context); + } else { + libspdm_reset_message_mut_b(spdm_context); + libspdm_reset_message_mut_c(spdm_context); + } + if (!result) { + return false; + } + +#if LIBSPDM_RECORD_TRANSCRIPT_DATA_SUPPORT + result = libspdm_get_peer_cert_chain_data( + spdm_context, (const void **)&cert_chain_data, &cert_chain_data_size); + if (!result) { + return false; + } + + /* Get leaf cert from cert chain*/ + result = libspdm_x509_get_cert_from_cert_chain(cert_chain_data, + cert_chain_data_size, -1, + &cert_buffer, &cert_buffer_size); + if (!result) { + return false; + } + + m1m2_buffer = libspdm_get_managed_buffer(&m1m2); + m1m2_buffer_size = libspdm_get_managed_buffer_size(&m1m2); + + if (is_requester) { + result = libspdm_asym_get_public_key_from_x509( + spdm_context->connection_info.algorithm.base_asym_algo, + cert_buffer, cert_buffer_size, &context); + if (!result) { + return false; + } + + result = libspdm_asym_verify( + spdm_context->connection_info.version, SPDM_CHALLENGE_AUTH, + spdm_context->connection_info.algorithm.base_asym_algo, + spdm_context->connection_info.algorithm.base_hash_algo, + context, m1m2_buffer, m1m2_buffer_size, sign_data, sign_data_size); + libspdm_asym_free( + spdm_context->connection_info.algorithm.base_asym_algo, context); + } else { + result = libspdm_req_asym_get_public_key_from_x509( + spdm_context->connection_info.algorithm.req_base_asym_alg, + cert_buffer, cert_buffer_size, &context); + if (!result) { + return false; + } + + result = libspdm_req_asym_verify( + spdm_context->connection_info.version, SPDM_CHALLENGE_AUTH, + spdm_context->connection_info.algorithm.req_base_asym_alg, + spdm_context->connection_info.algorithm.base_hash_algo, + context, m1m2_buffer, m1m2_buffer_size, sign_data, sign_data_size); + libspdm_req_asym_free(spdm_context->connection_info.algorithm.req_base_asym_alg, context); + } +#else + slot_id = spdm_context->connection_info.peer_used_cert_chain_slot_id; + LIBSPDM_ASSERT(slot_id < SPDM_MAX_SLOT_COUNT); + if (is_requester) { + if (spdm_context->connection_info.peer_used_cert_chain[slot_id].leaf_cert_public_key != + NULL) { + context = + spdm_context->connection_info.peer_used_cert_chain[slot_id].leaf_cert_public_key; + result = libspdm_asym_verify_hash( + spdm_context->connection_info.version, SPDM_CHALLENGE_AUTH, + spdm_context->connection_info.algorithm.base_asym_algo, + spdm_context->connection_info.algorithm.base_hash_algo, + context, m1m2_hash, m1m2_hash_size, sign_data, sign_data_size); + if (!result) { + LIBSPDM_DEBUG((LIBSPDM_DEBUG_INFO, "!!! verify_challenge_signature - FAIL !!!\n")); + return false; + } + return true; + } + + } else { + if (spdm_context->connection_info.peer_used_cert_chain[slot_id].leaf_cert_public_key != + NULL) { + context = + spdm_context->connection_info.peer_used_cert_chain[slot_id].leaf_cert_public_key; + result = libspdm_req_asym_verify_hash( + spdm_context->connection_info.version, SPDM_CHALLENGE_AUTH, + spdm_context->connection_info.algorithm.req_base_asym_alg, + spdm_context->connection_info.algorithm.base_hash_algo, + context, m1m2_hash, m1m2_hash_size, sign_data, sign_data_size); + if (!result) { + LIBSPDM_DEBUG((LIBSPDM_DEBUG_INFO, "!!! verify_challenge_signature - FAIL !!!\n")); + return false; + } + return true; + } + } + + result = libspdm_get_peer_cert_chain_data( + spdm_context, (const void **)&cert_chain_data, &cert_chain_data_size); + if (!result) { + return false; + } + + + /* Get leaf cert from cert chain*/ + + result = libspdm_x509_get_cert_from_cert_chain(cert_chain_data, + cert_chain_data_size, -1, + &cert_buffer, &cert_buffer_size); + if (!result) { + return false; + } + + if (is_requester) { + result = libspdm_asym_get_public_key_from_x509( + spdm_context->connection_info.algorithm.base_asym_algo, + cert_buffer, cert_buffer_size, &context); + if (!result) { + return false; + } + + result = libspdm_asym_verify_hash( + spdm_context->connection_info.version, SPDM_CHALLENGE_AUTH, + spdm_context->connection_info.algorithm.base_asym_algo, + spdm_context->connection_info.algorithm.base_hash_algo, + context, m1m2_hash, m1m2_hash_size, sign_data, + sign_data_size); + libspdm_asym_free(spdm_context->connection_info.algorithm.base_asym_algo, context); + } else { + result = libspdm_req_asym_get_public_key_from_x509( + spdm_context->connection_info.algorithm.req_base_asym_alg, + cert_buffer, cert_buffer_size, &context); + if (!result) { + return false; + } + + result = libspdm_req_asym_verify_hash( + spdm_context->connection_info.version, SPDM_CHALLENGE_AUTH, + spdm_context->connection_info.algorithm.req_base_asym_alg, + spdm_context->connection_info.algorithm.base_hash_algo, + context, m1m2_hash, m1m2_hash_size, sign_data, sign_data_size); + libspdm_req_asym_free(spdm_context->connection_info.algorithm.req_base_asym_alg, context); + } +#endif + if (!result) { + LIBSPDM_DEBUG((LIBSPDM_DEBUG_INFO, + "!!! verify_challenge_signature - FAIL !!!\n")); + return false; + } + + LIBSPDM_DEBUG((LIBSPDM_DEBUG_INFO, "!!! verify_challenge_signature - PASS !!!\n")); + + return true; +} + +/** + * This function calculate the measurement summary hash size. + * + * @param spdm_context A pointer to the SPDM context. + * @param is_requester Is the function called from a requester. + * @param measurement_summary_hash_type The type of the measurement summary hash. + * + * @return 0 measurement summary hash type is invalid, NO_MEAS hash type or no MEAS capabilities. + * @return measurement summary hash size according to type. + **/ +uint32_t +libspdm_get_measurement_summary_hash_size(libspdm_context_t *spdm_context, + bool is_requester, + uint8_t measurement_summary_hash_type) +{ + if (!libspdm_is_capabilities_flag_supported( + spdm_context, is_requester, 0, + SPDM_GET_CAPABILITIES_RESPONSE_FLAGS_MEAS_CAP)) { + return 0; + } + + switch (measurement_summary_hash_type) { + case SPDM_CHALLENGE_REQUEST_NO_MEASUREMENT_SUMMARY_HASH: + return 0; + break; + + case SPDM_CHALLENGE_REQUEST_TCB_COMPONENT_MEASUREMENT_HASH: + case SPDM_CHALLENGE_REQUEST_ALL_MEASUREMENTS_HASH: + return libspdm_get_hash_size(spdm_context->connection_info.algorithm.base_hash_algo); + break; + default: + return 0; + break; + } +} diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/libraries/libspdm/2.3.1/library/spdm_common_lib/libspdm_com_crypto_service_session.c nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/libraries/libspdm/2.3.1/library/spdm_common_lib/libspdm_com_crypto_service_session.c --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/libraries/libspdm/2.3.1/library/spdm_common_lib/libspdm_com_crypto_service_session.c 1970-01-01 00:00:00.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/libraries/libspdm/2.3.1/library/spdm_common_lib/libspdm_com_crypto_service_session.c 2024-03-05 22:14:14.000000000 +0000 @@ -0,0 +1,686 @@ +/** + * Copyright Notice: + * Copyright 2021-2022 DMTF. All rights reserved. + * License: BSD 3-Clause License. For full text see link: https://github.com/DMTF/libspdm/blob/main/LICENSE.md + **/ + +#include "internal/libspdm_common_lib.h" + +#if LIBSPDM_RECORD_TRANSCRIPT_DATA_SUPPORT +/* + * This function calculates current TH data with message A and message K. + * + * @param spdm_context A pointer to the SPDM context. + * @param session_info The SPDM session ID. + * @param cert_chain_buffer Certitiface chain buffer with spdm_cert_chain_t header. + * @param cert_chain_buffer_size size in bytes of the certitiface chain buffer. + * @param th_data_buffer_size size in bytes of the th_data_buffer + * @param th_data_buffer The buffer to store the th_data_buffer + * + * @retval RETURN_SUCCESS current TH data is calculated. + */ +bool libspdm_calculate_th_for_exchange( + void *context, void *spdm_session_info, const uint8_t *cert_chain_buffer, + size_t cert_chain_buffer_size, + size_t *th_data_buffer_size, void *th_data_buffer) +{ + libspdm_context_t *spdm_context; + libspdm_session_info_t *session_info; + uint8_t cert_chain_buffer_hash[LIBSPDM_MAX_HASH_SIZE]; + uint32_t hash_size; + libspdm_return_t status; + libspdm_large_managed_buffer_t th_curr; + bool result; + size_t th_data_buffer_capacity; + + spdm_context = context; + session_info = spdm_session_info; + + hash_size = libspdm_get_hash_size(spdm_context->connection_info.algorithm.base_hash_algo); + + LIBSPDM_ASSERT(*th_data_buffer_size >= LIBSPDM_MAX_MESSAGE_BUFFER_SIZE); + libspdm_init_managed_buffer(&th_curr, LIBSPDM_MAX_MESSAGE_BUFFER_SIZE); + + LIBSPDM_DEBUG((LIBSPDM_DEBUG_INFO, "message_a data :\n")); + LIBSPDM_INTERNAL_DUMP_HEX( + libspdm_get_managed_buffer(&spdm_context->transcript.message_a), + libspdm_get_managed_buffer_size(&spdm_context->transcript.message_a)); + status = libspdm_append_managed_buffer( + &th_curr, + libspdm_get_managed_buffer(&spdm_context->transcript.message_a), + libspdm_get_managed_buffer_size(&spdm_context->transcript.message_a)); + if (LIBSPDM_STATUS_IS_ERROR(status)) { + return false; + } + + if (cert_chain_buffer != NULL) { + LIBSPDM_DEBUG((LIBSPDM_DEBUG_INFO, "th_message_ct data :\n")); + LIBSPDM_INTERNAL_DUMP_HEX(cert_chain_buffer, cert_chain_buffer_size); + result = libspdm_hash_all( + spdm_context->connection_info.algorithm.base_hash_algo, + cert_chain_buffer, cert_chain_buffer_size, + cert_chain_buffer_hash); + if (!result) { + return false; + } + status = libspdm_append_managed_buffer(&th_curr, cert_chain_buffer_hash, hash_size); + if (LIBSPDM_STATUS_IS_ERROR(status)) { + return false; + } + } + + LIBSPDM_DEBUG((LIBSPDM_DEBUG_INFO, "message_k data :\n")); + LIBSPDM_INTERNAL_DUMP_HEX( + libspdm_get_managed_buffer(&session_info->session_transcript.message_k), + libspdm_get_managed_buffer_size(&session_info->session_transcript.message_k)); + status = libspdm_append_managed_buffer( + &th_curr, + libspdm_get_managed_buffer(&session_info->session_transcript.message_k), + libspdm_get_managed_buffer_size(&session_info->session_transcript.message_k)); + if (LIBSPDM_STATUS_IS_ERROR(status)) { + return false; + } + + th_data_buffer_capacity = *th_data_buffer_size; + *th_data_buffer_size = libspdm_get_managed_buffer_size(&th_curr); + libspdm_copy_mem(th_data_buffer, th_data_buffer_capacity, + libspdm_get_managed_buffer(&th_curr), *th_data_buffer_size); + + return true; +} +#else +/* + * This function calculates current TH hash with message A and message K. + * + * @param spdm_context A pointer to the SPDM context. + * @param session_info The SPDM session ID. + * @param th_hash_buffer_size size in bytes of the th_hash_buffer + * @param th_hash_buffer The buffer to store the th_hash_buffer + * + * @retval RETURN_SUCCESS current TH hash is calculated. + */ +bool libspdm_calculate_th_hash_for_exchange( + void *context, void *spdm_session_info, + size_t *th_hash_buffer_size, void *th_hash_buffer) +{ + libspdm_context_t *spdm_context; + libspdm_session_info_t *session_info; + uint32_t hash_size; + void *digest_context_th; + bool result; + + spdm_context = context; + session_info = spdm_session_info; + + hash_size = libspdm_get_hash_size(spdm_context->connection_info.algorithm.base_hash_algo); + + LIBSPDM_ASSERT(*th_hash_buffer_size >= hash_size); + + /* duplicate the th context, because we still need use original context to continue.*/ + digest_context_th = libspdm_hash_new (spdm_context->connection_info.algorithm.base_hash_algo); + if (digest_context_th == NULL) { + return false; + } + result = libspdm_hash_duplicate (spdm_context->connection_info.algorithm.base_hash_algo, + session_info->session_transcript.digest_context_th, + digest_context_th); + if (!result) { + libspdm_hash_free (spdm_context->connection_info.algorithm.base_hash_algo, + digest_context_th); + return false; + } + result = libspdm_hash_final (spdm_context->connection_info.algorithm.base_hash_algo, + digest_context_th, th_hash_buffer); + libspdm_hash_free (spdm_context->connection_info.algorithm.base_hash_algo, digest_context_th); + if (!result) { + return false; + } + + *th_hash_buffer_size = hash_size; + + return true; +} + +/* + * This function calculates current TH hmac with message A and message K, with response finished_key. + * + * @param spdm_context A pointer to the SPDM context. + * @param session_info The SPDM session ID. + * @param th_hmac_buffer_size size in bytes of the th_hmac_buffer + * @param th_hmac_buffer The buffer to store the th_hmac_buffer + * + * @retval RETURN_SUCCESS current TH hmac is calculated. + */ +bool libspdm_calculate_th_hmac_for_exchange_rsp( + void *context, void *spdm_session_info, bool is_requester, + size_t *th_hmac_buffer_size, void *th_hmac_buffer) +{ + libspdm_context_t *spdm_context; + libspdm_session_info_t *session_info; + void *secured_message_context; + uint32_t hash_size; + void *hash_context_th; + uint8_t hash_data[LIBSPDM_MAX_HASH_SIZE]; + bool result; + + spdm_context = context; + session_info = spdm_session_info; + secured_message_context = session_info->secured_message_context; + + hash_size = libspdm_get_hash_size(spdm_context->connection_info.algorithm.base_hash_algo); + + LIBSPDM_ASSERT(*th_hmac_buffer_size >= hash_size); + + /* duplicate the th context, because we still need use original context to continue.*/ + hash_context_th = libspdm_hash_new (spdm_context->connection_info.algorithm.base_hash_algo); + if (hash_context_th == NULL) { + return false; + } + result = libspdm_hash_duplicate (spdm_context->connection_info.algorithm.base_hash_algo, + session_info->session_transcript.digest_context_th, + hash_context_th); + if (!result) { + libspdm_hash_free (spdm_context->connection_info.algorithm.base_hash_algo, hash_context_th); + return false; + } + result = libspdm_hash_final (spdm_context->connection_info.algorithm.base_hash_algo, + hash_context_th, hash_data); + libspdm_hash_free (spdm_context->connection_info.algorithm.base_hash_algo, hash_context_th); + if (!result) { + return false; + } + + result = libspdm_hmac_all_with_response_finished_key (secured_message_context, + hash_data, hash_size, th_hmac_buffer); + if (!result) { + return false; + } + *th_hmac_buffer_size = hash_size; + + return true; +} +#endif + +#if LIBSPDM_RECORD_TRANSCRIPT_DATA_SUPPORT +/* + * This function calculates current TH data with message A, message K and message F. + * + * @param spdm_context A pointer to the SPDM context. + * @param session_info The SPDM session ID. + * @param cert_chain_buffer Certitiface chain buffer with spdm_cert_chain_t header. + * @param cert_chain_buffer_size size in bytes of the certitiface chain buffer. + * @param mut_cert_chain_buffer Certitiface chain buffer with spdm_cert_chain_t header in mutual authentication. + * @param mut_cert_chain_buffer_size size in bytes of the certitiface chain buffer in mutual authentication. + * @param th_data_buffer_size size in bytes of the th_data_buffer + * @param th_data_buffer The buffer to store the th_data_buffer + * + * @retval RETURN_SUCCESS current TH data is calculated. + */ +bool libspdm_calculate_th_for_finish(void *context, + void *spdm_session_info, + const uint8_t *cert_chain_buffer, + size_t cert_chain_buffer_size, + const uint8_t *mut_cert_chain_buffer, + size_t mut_cert_chain_buffer_size, + size_t *th_data_buffer_size, + void *th_data_buffer) +{ + libspdm_context_t *spdm_context; + libspdm_session_info_t *session_info; + uint8_t cert_chain_buffer_hash[LIBSPDM_MAX_HASH_SIZE]; + uint8_t mut_cert_chain_buffer_hash[LIBSPDM_MAX_HASH_SIZE]; + uint32_t hash_size; + libspdm_return_t status; + libspdm_large_managed_buffer_t th_curr; + bool result; + size_t th_data_buffer_capacity; + + spdm_context = context; + session_info = spdm_session_info; + + hash_size = libspdm_get_hash_size(spdm_context->connection_info.algorithm.base_hash_algo); + + LIBSPDM_ASSERT(*th_data_buffer_size >= LIBSPDM_MAX_MESSAGE_BUFFER_SIZE); + libspdm_init_managed_buffer(&th_curr, LIBSPDM_MAX_MESSAGE_BUFFER_SIZE); + + LIBSPDM_DEBUG((LIBSPDM_DEBUG_INFO, "message_a data :\n")); + LIBSPDM_INTERNAL_DUMP_HEX( + libspdm_get_managed_buffer(&spdm_context->transcript.message_a), + libspdm_get_managed_buffer_size(&spdm_context->transcript.message_a)); + status = libspdm_append_managed_buffer( + &th_curr, + libspdm_get_managed_buffer(&spdm_context->transcript.message_a), + libspdm_get_managed_buffer_size(&spdm_context->transcript.message_a)); + if (LIBSPDM_STATUS_IS_ERROR(status)) { + return false; + } + + if (cert_chain_buffer != NULL) { + LIBSPDM_DEBUG((LIBSPDM_DEBUG_INFO, "th_message_ct data :\n")); + LIBSPDM_INTERNAL_DUMP_HEX(cert_chain_buffer, cert_chain_buffer_size); + result = libspdm_hash_all( + spdm_context->connection_info.algorithm.base_hash_algo, + cert_chain_buffer, cert_chain_buffer_size, + cert_chain_buffer_hash); + if (!result) { + return false; + } + status = libspdm_append_managed_buffer(&th_curr, cert_chain_buffer_hash, hash_size); + if (LIBSPDM_STATUS_IS_ERROR(status)) { + return false; + } + } + + LIBSPDM_DEBUG((LIBSPDM_DEBUG_INFO, "message_k data :\n")); + LIBSPDM_INTERNAL_DUMP_HEX( + libspdm_get_managed_buffer(&session_info->session_transcript.message_k), + libspdm_get_managed_buffer_size(&session_info->session_transcript.message_k)); + status = libspdm_append_managed_buffer( + &th_curr, + libspdm_get_managed_buffer(&session_info->session_transcript.message_k), + libspdm_get_managed_buffer_size(&session_info->session_transcript.message_k)); + if (LIBSPDM_STATUS_IS_ERROR(status)) { + return false; + } + + if (mut_cert_chain_buffer != NULL) { + LIBSPDM_DEBUG((LIBSPDM_DEBUG_INFO, "th_message_cm data :\n")); + LIBSPDM_INTERNAL_DUMP_HEX(mut_cert_chain_buffer, mut_cert_chain_buffer_size); + result = libspdm_hash_all( + spdm_context->connection_info.algorithm.base_hash_algo, + mut_cert_chain_buffer, mut_cert_chain_buffer_size, + mut_cert_chain_buffer_hash); + if (!result) { + return false; + } + status = libspdm_append_managed_buffer(&th_curr, mut_cert_chain_buffer_hash, hash_size); + if (LIBSPDM_STATUS_IS_ERROR(status)) { + return false; + } + } + + LIBSPDM_DEBUG((LIBSPDM_DEBUG_INFO, "message_f data :\n")); + LIBSPDM_INTERNAL_DUMP_HEX( + libspdm_get_managed_buffer(&session_info->session_transcript.message_f), + libspdm_get_managed_buffer_size(&session_info->session_transcript.message_f)); + status = libspdm_append_managed_buffer( + &th_curr, + libspdm_get_managed_buffer(&session_info->session_transcript.message_f), + libspdm_get_managed_buffer_size(&session_info->session_transcript.message_f)); + if (LIBSPDM_STATUS_IS_ERROR(status)) { + return false; + } + + th_data_buffer_capacity = *th_data_buffer_size; + *th_data_buffer_size = libspdm_get_managed_buffer_size(&th_curr); + libspdm_copy_mem(th_data_buffer, th_data_buffer_capacity, + libspdm_get_managed_buffer(&th_curr), *th_data_buffer_size); + + return true; +} +#else +/* + * This function calculates current TH hash with message A, message K and message F. + * + * @param spdm_context A pointer to the SPDM context. + * @param session_info The SPDM session ID. + * @param th_hash_buffer_size size in bytes of the th_hash_buffer + * @param th_hash_buffer The buffer to store the th_hash_buffer + * + * @retval RETURN_SUCCESS current TH hash is calculated. + */ +bool libspdm_calculate_th_hash_for_finish(void *context, + void *spdm_session_info, + size_t *th_hash_buffer_size, + void *th_hash_buffer) +{ + libspdm_context_t *spdm_context; + libspdm_session_info_t *session_info; + uint32_t hash_size; + void *digest_context_th; + bool result; + + spdm_context = context; + session_info = spdm_session_info; + + hash_size = libspdm_get_hash_size(spdm_context->connection_info.algorithm.base_hash_algo); + + LIBSPDM_ASSERT(*th_hash_buffer_size >= hash_size); + + /* duplicate the th context, because we still need use original context to continue.*/ + digest_context_th = libspdm_hash_new (spdm_context->connection_info.algorithm.base_hash_algo); + if (digest_context_th == NULL) { + return false; + } + result = libspdm_hash_duplicate (spdm_context->connection_info.algorithm.base_hash_algo, + session_info->session_transcript.digest_context_th, + digest_context_th); + if (!result) { + libspdm_hash_free (spdm_context->connection_info.algorithm.base_hash_algo, + digest_context_th); + return false; + } + result = libspdm_hash_final (spdm_context->connection_info.algorithm.base_hash_algo, + digest_context_th, th_hash_buffer); + libspdm_hash_free (spdm_context->connection_info.algorithm.base_hash_algo, digest_context_th); + if (!result) { + return false; + } + + *th_hash_buffer_size = hash_size; + + return true; +} + +/* + * This function calculates current TH hmac with message A, message K and message F, with response finished_key. + * + * @param spdm_context A pointer to the SPDM context. + * @param session_info The SPDM session ID. + * @param th_hmac_buffer_size size in bytes of the th_hmac_buffer + * @param th_hmac_buffer The buffer to store the th_hmac_buffer + * + * @retval RETURN_SUCCESS current TH hmac is calculated. + */ +bool libspdm_calculate_th_hmac_for_finish_rsp(void *context, + void *spdm_session_info, + size_t *th_hmac_buffer_size, + void *th_hmac_buffer) +{ + libspdm_context_t *spdm_context; + libspdm_session_info_t *session_info; + void *secured_message_context; + uint32_t hash_size; + void *hash_context_th; + uint8_t hash_data[LIBSPDM_MAX_HASH_SIZE]; + bool result; + + spdm_context = context; + session_info = spdm_session_info; + secured_message_context = session_info->secured_message_context; + + hash_size = libspdm_get_hash_size(spdm_context->connection_info.algorithm.base_hash_algo); + + LIBSPDM_ASSERT(*th_hmac_buffer_size >= hash_size); + LIBSPDM_ASSERT(session_info->session_transcript.digest_context_th != NULL); + + /* duplicate the th context, because we still need use original context to continue.*/ + hash_context_th = libspdm_hash_new (spdm_context->connection_info.algorithm.base_hash_algo); + if (hash_context_th == NULL) { + return false; + } + result = libspdm_hash_duplicate (spdm_context->connection_info.algorithm.base_hash_algo, + session_info->session_transcript.digest_context_th, + hash_context_th); + if (!result) { + libspdm_hash_free (spdm_context->connection_info.algorithm.base_hash_algo, hash_context_th); + return false; + } + result = libspdm_hash_final (spdm_context->connection_info.algorithm.base_hash_algo, + hash_context_th, hash_data); + libspdm_hash_free (spdm_context->connection_info.algorithm.base_hash_algo, hash_context_th); + if (!result) { + return false; + } + + result = libspdm_hmac_all_with_response_finished_key (secured_message_context, + hash_data, hash_size, th_hmac_buffer); + if (!result) { + return false; + } + *th_hmac_buffer_size = hash_size; + + return true; +} + +/* + * This function calculates current TH hmac with message A, message K and message F, with request finished_key. + * + * @param spdm_context A pointer to the SPDM context. + * @param session_info The SPDM session ID. + * @param th_hmac_buffer_size size in bytes of the th_hmac_buffer + * @param th_hmac_buffer The buffer to store the th_hmac_buffer + * + * @retval RETURN_SUCCESS current TH hmac is calculated. + */ +bool libspdm_calculate_th_hmac_for_finish_req(void *context, + void *spdm_session_info, + size_t *th_hmac_buffer_size, + void *th_hmac_buffer) +{ + libspdm_context_t *spdm_context; + libspdm_session_info_t *session_info; + void *secured_message_context; + uint32_t hash_size; + void *hash_context_th; + uint8_t hash_data[LIBSPDM_MAX_HASH_SIZE]; + bool result; + + spdm_context = context; + session_info = spdm_session_info; + secured_message_context = session_info->secured_message_context; + + hash_size = libspdm_get_hash_size(spdm_context->connection_info.algorithm.base_hash_algo); + + LIBSPDM_ASSERT(*th_hmac_buffer_size >= hash_size); + LIBSPDM_ASSERT(session_info->session_transcript.digest_context_th != NULL); + + /* duplicate the th context, because we still need use original context to continue.*/ + hash_context_th = libspdm_hash_new (spdm_context->connection_info.algorithm.base_hash_algo); + if (hash_context_th == NULL) { + return false; + } + result = libspdm_hash_duplicate (spdm_context->connection_info.algorithm.base_hash_algo, + session_info->session_transcript.digest_context_th, + hash_context_th); + if (!result) { + libspdm_hash_free (spdm_context->connection_info.algorithm.base_hash_algo, hash_context_th); + return false; + } + result = libspdm_hash_final (spdm_context->connection_info.algorithm.base_hash_algo, + hash_context_th, hash_data); + libspdm_hash_free (spdm_context->connection_info.algorithm.base_hash_algo, hash_context_th); + if (!result) { + return false; + } + + result = libspdm_hmac_all_with_request_finished_key (secured_message_context, + hash_data, hash_size, th_hmac_buffer); + if (!result) { + return false; + } + *th_hmac_buffer_size = hash_size; + + return true; +} +#endif + +/* + * This function calculates th1 hash. + * + * @param spdm_context A pointer to the SPDM context. + * @param session_info The SPDM session ID. + * @param is_requester Indicate of the key generation for a requester or a responder. + * @param th1_hash_data th1 hash + * + * @retval RETURN_SUCCESS th1 hash is calculated. + */ +bool libspdm_calculate_th1_hash(void *context, + void *spdm_session_info, + bool is_requester, + uint8_t *th1_hash_data) +{ + libspdm_context_t *spdm_context; + libspdm_session_info_t *session_info; + bool result; +#if LIBSPDM_RECORD_TRANSCRIPT_DATA_SUPPORT + uint8_t *cert_chain_buffer; + size_t cert_chain_buffer_size; + uint8_t th_curr_data[LIBSPDM_MAX_MESSAGE_BUFFER_SIZE]; + size_t th_curr_data_size; +#endif +#if !(LIBSPDM_RECORD_TRANSCRIPT_DATA_SUPPORT) || (LIBSPDM_DEBUG_PRINT_ENABLE) + size_t hash_size; +#endif + spdm_context = context; + + LIBSPDM_DEBUG((LIBSPDM_DEBUG_INFO, "Calc th1 hash ...\n")); + + session_info = spdm_session_info; + +#if !(LIBSPDM_RECORD_TRANSCRIPT_DATA_SUPPORT) || (LIBSPDM_DEBUG_PRINT_ENABLE) + hash_size = libspdm_get_hash_size(spdm_context->connection_info.algorithm.base_hash_algo); +#endif +#if LIBSPDM_RECORD_TRANSCRIPT_DATA_SUPPORT + if (!session_info->use_psk) { + if (is_requester) { + result = libspdm_get_peer_cert_chain_buffer( + spdm_context, (const void **)&cert_chain_buffer, + &cert_chain_buffer_size); + } else { + result = libspdm_get_local_cert_chain_buffer( + spdm_context, (const void **)&cert_chain_buffer, + &cert_chain_buffer_size); + } + if (!result) { + return false; + } + } else { + cert_chain_buffer = NULL; + cert_chain_buffer_size = 0; + } + + th_curr_data_size = sizeof(th_curr_data); + result = libspdm_calculate_th_for_exchange( + spdm_context, session_info, cert_chain_buffer, + cert_chain_buffer_size, &th_curr_data_size, th_curr_data); + if (!result) { + return false; + } + + result = libspdm_hash_all(spdm_context->connection_info.algorithm.base_hash_algo, + th_curr_data, th_curr_data_size, th1_hash_data); + if (!result) { + return false; + } +#else + result = libspdm_calculate_th_hash_for_exchange( + spdm_context, session_info, &hash_size, th1_hash_data); + if (!result) { + return false; + } +#endif + LIBSPDM_DEBUG((LIBSPDM_DEBUG_INFO, "th1 hash - ")); + LIBSPDM_INTERNAL_DUMP_DATA(th1_hash_data, hash_size); + LIBSPDM_DEBUG((LIBSPDM_DEBUG_INFO, "\n")); + + return true; +} + +/* + * This function calculates th2 hash. + * + * @param spdm_context A pointer to the SPDM context. + * @param session_info The SPDM session ID. + * @param is_requester Indicate of the key generation for a requester or a responder. + * @param th1_hash_data th2 hash + * + * @retval RETURN_SUCCESS th2 hash is calculated. + */ +bool libspdm_calculate_th2_hash(void *context, + void *spdm_session_info, + bool is_requester, + uint8_t *th2_hash_data) +{ + libspdm_context_t *spdm_context; + libspdm_session_info_t *session_info; + bool result; +#if LIBSPDM_RECORD_TRANSCRIPT_DATA_SUPPORT + uint8_t *cert_chain_buffer; + size_t cert_chain_buffer_size; + uint8_t *mut_cert_chain_buffer; + size_t mut_cert_chain_buffer_size; + uint8_t th_curr_data[LIBSPDM_MAX_MESSAGE_BUFFER_SIZE]; + size_t th_curr_data_size; +#endif +#if !(LIBSPDM_RECORD_TRANSCRIPT_DATA_SUPPORT) || (LIBSPDM_DEBUG_PRINT_ENABLE) + size_t hash_size; +#endif + + spdm_context = context; + + LIBSPDM_DEBUG((LIBSPDM_DEBUG_INFO, "Calc th2 hash ...\n")); + + session_info = spdm_session_info; + +#if !(LIBSPDM_RECORD_TRANSCRIPT_DATA_SUPPORT) || (LIBSPDM_DEBUG_PRINT_ENABLE) + hash_size = libspdm_get_hash_size(spdm_context->connection_info.algorithm.base_hash_algo); +#endif + +#if LIBSPDM_RECORD_TRANSCRIPT_DATA_SUPPORT + if (!session_info->use_psk) { + if (is_requester) { + result = libspdm_get_peer_cert_chain_buffer( + spdm_context, (const void **)&cert_chain_buffer, + &cert_chain_buffer_size); + } else { + result = libspdm_get_local_cert_chain_buffer( + spdm_context, (const void **)&cert_chain_buffer, + &cert_chain_buffer_size); + } + if (!result) { + return false; + } + if (session_info->mut_auth_requested) { + if (is_requester) { + result = libspdm_get_local_cert_chain_buffer( + spdm_context, + (const void **)&mut_cert_chain_buffer, + &mut_cert_chain_buffer_size); + } else { + result = libspdm_get_peer_cert_chain_buffer( + spdm_context, + (const void **)&mut_cert_chain_buffer, + &mut_cert_chain_buffer_size); + } + if (!result) { + return false; + } + } else { + mut_cert_chain_buffer = NULL; + mut_cert_chain_buffer_size = 0; + } + } else { + cert_chain_buffer = NULL; + cert_chain_buffer_size = 0; + mut_cert_chain_buffer = NULL; + mut_cert_chain_buffer_size = 0; + } + + th_curr_data_size = sizeof(th_curr_data); + result = libspdm_calculate_th_for_finish( + spdm_context, session_info, cert_chain_buffer, + cert_chain_buffer_size, mut_cert_chain_buffer, + mut_cert_chain_buffer_size, &th_curr_data_size, th_curr_data); + if (!result) { + return false; + } + + result = libspdm_hash_all(spdm_context->connection_info.algorithm.base_hash_algo, + th_curr_data, th_curr_data_size, th2_hash_data); + if (!result) { + return false; + } +#else + result = libspdm_calculate_th_hash_for_finish( + spdm_context, session_info, &hash_size, th2_hash_data); + if (!result) { + return false; + } +#endif + LIBSPDM_DEBUG((LIBSPDM_DEBUG_INFO, "th2 hash - ")); + LIBSPDM_INTERNAL_DUMP_DATA(th2_hash_data, hash_size); + LIBSPDM_DEBUG((LIBSPDM_DEBUG_INFO, "\n")); + + return true; +} diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/libraries/libspdm/2.3.1/library/spdm_common_lib/libspdm_com_msg_log.c nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/libraries/libspdm/2.3.1/library/spdm_common_lib/libspdm_com_msg_log.c --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/libraries/libspdm/2.3.1/library/spdm_common_lib/libspdm_com_msg_log.c 1970-01-01 00:00:00.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/libraries/libspdm/2.3.1/library/spdm_common_lib/libspdm_com_msg_log.c 2024-03-05 22:14:14.000000000 +0000 @@ -0,0 +1,102 @@ +/** + * Copyright Notice: + * Copyright 2021-2022 DMTF. All rights reserved. + * License: BSD 3-Clause License. For full text see link: https://github.com/DMTF/libspdm/blob/main/LICENSE.md + **/ + +#include "internal/libspdm_common_lib.h" + +#if LIBSPDM_ENABLE_MSG_LOG +void libspdm_init_msg_log (void *context, void *msg_buffer, size_t msg_buffer_size) +{ + libspdm_context_t *spdm_context; + + LIBSPDM_ASSERT((context != NULL) && (msg_buffer != NULL)); + LIBSPDM_ASSERT(msg_buffer_size != 0); + + spdm_context = context; + spdm_context->msg_log.buffer = msg_buffer; + spdm_context->msg_log.max_buffer_size = msg_buffer_size; + spdm_context->msg_log.buffer_size = 0; + spdm_context->msg_log.mode = 0; + spdm_context->msg_log.status = 0; +} + +void libspdm_set_msg_log_mode (void *context, uint32_t mode) +{ + libspdm_context_t *spdm_context; + + LIBSPDM_ASSERT(context != NULL); + + spdm_context = context; + spdm_context->msg_log.mode = mode; +} + +uint32_t libspdm_get_msg_log_status (void *context) +{ + libspdm_context_t *spdm_context; + + LIBSPDM_ASSERT(context != NULL); + + spdm_context = context; + + return spdm_context->msg_log.status; +} + +size_t libspdm_get_msg_log_size (void *context) +{ + libspdm_context_t *spdm_context; + + LIBSPDM_ASSERT(context != NULL); + + spdm_context = context; + + return spdm_context->msg_log.buffer_size; +} + +void libspdm_reset_msg_log (void *context) +{ + libspdm_context_t *spdm_context; + + LIBSPDM_ASSERT(context != NULL); + + spdm_context = context; + + spdm_context->msg_log.buffer_size = 0; + spdm_context->msg_log.mode = 0; + spdm_context->msg_log.status = 0; +} + +void libspdm_append_msg_log(void *context, void *message, size_t message_size) +{ + libspdm_context_t *spdm_context; + + LIBSPDM_ASSERT((context != NULL) && (message != NULL)); + + spdm_context = context; + + if (((spdm_context->msg_log.mode & LIBSPDM_MSG_LOG_MODE_ENABLE) != 0) && + ((spdm_context->msg_log.status & LIBSPDM_MSG_LOG_STATUS_BUFFER_FULL) == 0)) { + if (spdm_context->msg_log.buffer_size + message_size > + spdm_context->msg_log.max_buffer_size) { + libspdm_copy_mem((uint8_t *)spdm_context->msg_log.buffer + + spdm_context->msg_log.buffer_size, + spdm_context->msg_log.max_buffer_size, message, + spdm_context->msg_log.max_buffer_size - + spdm_context->msg_log.buffer_size); + spdm_context->msg_log.status |= LIBSPDM_MSG_LOG_STATUS_BUFFER_FULL; + spdm_context->msg_log.buffer_size = spdm_context->msg_log.max_buffer_size; + } else { + libspdm_copy_mem((uint8_t *)spdm_context->msg_log.buffer + + spdm_context->msg_log.buffer_size, + spdm_context->msg_log.max_buffer_size, message, message_size); + spdm_context->msg_log.buffer_size += message_size; + } + + LIBSPDM_DEBUG((LIBSPDM_DEBUG_INFO, "Message Logging Status = [%x] Buffer Size = [%x] " + "Max Buffer Size = [%x]\n", spdm_context->msg_log.status, + spdm_context->msg_log.buffer_size, spdm_context->msg_log.max_buffer_size)); + LIBSPDM_INTERNAL_DUMP_HEX(spdm_context->msg_log.buffer, spdm_context->msg_log.buffer_size); + } +} +#endif /* LIBSPDM_ENABLE_MSG_LOG */ diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/libraries/libspdm/2.3.1/library/spdm_common_lib/libspdm_com_opaque_data.c nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/libraries/libspdm/2.3.1/library/spdm_common_lib/libspdm_com_opaque_data.c --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/libraries/libspdm/2.3.1/library/spdm_common_lib/libspdm_com_opaque_data.c 1970-01-01 00:00:00.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/libraries/libspdm/2.3.1/library/spdm_common_lib/libspdm_com_opaque_data.c 2024-03-05 22:14:15.000000000 +0000 @@ -0,0 +1,232 @@ +/** + * Copyright Notice: + * Copyright 2021-2022 DMTF. All rights reserved. + * License: BSD 3-Clause License. For full text see link: https://github.com/DMTF/libspdm/blob/main/LICENSE.md + **/ + +#include "internal/libspdm_common_lib.h" + +/** + * Return the size in bytes of opaque data version selection. + * + * This function should be called in KEY_EXCHANGE/PSK_EXCHANGE response generation. + * + * @return the size in bytes of opaque data version selection. + **/ +size_t libspdm_get_opaque_data_version_selection_data_size(const libspdm_context_t *spdm_context) +{ + size_t size; + + if (spdm_context->local_context.secured_message_version.spdm_version_count == 0) { + return 0; + } + + if (libspdm_get_connection_version (spdm_context) >= SPDM_MESSAGE_VERSION_12) { + size = sizeof(spdm_general_opaque_data_table_header_t) + + sizeof(secured_message_opaque_element_table_header_t) + + sizeof(secured_message_opaque_element_version_selection_t); + } else { + size = sizeof(secured_message_general_opaque_data_table_header_t) + + sizeof(secured_message_opaque_element_table_header_t) + + sizeof(secured_message_opaque_element_version_selection_t); + } + /* Add Padding*/ + return (size + 3) & ~3; +} + +/** + * Return the size in bytes of opaque data supported version. + * + * This function should be called in KEY_EXCHANGE/PSK_EXCHANGE request generation. + * + * @return the size in bytes of opaque data supported version. + **/ +size_t libspdm_get_opaque_data_supported_version_data_size(libspdm_context_t *spdm_context) +{ + size_t size; + + if (spdm_context->local_context.secured_message_version.spdm_version_count == 0) { + return 0; + } + + if (libspdm_get_connection_version (spdm_context) >= SPDM_MESSAGE_VERSION_12) { + size = sizeof(spdm_general_opaque_data_table_header_t) + + sizeof(secured_message_opaque_element_table_header_t) + + sizeof(secured_message_opaque_element_supported_version_t) + + sizeof(spdm_version_number_t) * + spdm_context->local_context.secured_message_version.spdm_version_count; + } else { + size = sizeof(secured_message_general_opaque_data_table_header_t) + + sizeof(secured_message_opaque_element_table_header_t) + + sizeof(secured_message_opaque_element_supported_version_t) + + sizeof(spdm_version_number_t) * + spdm_context->local_context.secured_message_version.spdm_version_count; + } + /* Add Padding*/ + return (size + 3) & ~3; +} + +/** + * Return the size in bytes of opaque data supported version. + * + * This function should be called in libspdm_process_opaque_data_supported_version_data. + * + * @param version_count Secure version count. + * + * @return the size in bytes of opaque data supported version. + **/ +size_t libspdm_get_untrusted_opaque_data_supported_version_data_size( + libspdm_context_t *spdm_context, uint8_t version_count) +{ + size_t size; + + if (libspdm_get_connection_version (spdm_context) >= SPDM_MESSAGE_VERSION_12) { + size = sizeof(spdm_general_opaque_data_table_header_t) + + sizeof(secured_message_opaque_element_table_header_t) + + sizeof(secured_message_opaque_element_supported_version_t) + + sizeof(spdm_version_number_t) * version_count; + } else { + size = sizeof(secured_message_general_opaque_data_table_header_t) + + sizeof(secured_message_opaque_element_table_header_t) + + sizeof(secured_message_opaque_element_supported_version_t) + + sizeof(spdm_version_number_t) * version_count; + } + /* Add Padding*/ + return (size + 3) & ~3; +} + +/** + * Get element from multi element opaque data by element id. + * + * This function should be called in + * libspdm_process_opaque_data_supported_version_data/libspdm_process_opaque_data_version_selection_data. + * + * @param[in] data_in_size size of multi element opaque data. + * @param[in] data_in A pointer to the multi element opaque data. + * @param[in] element_id element id. + * @param[in] sm_data_id sm_data_id to identifiy for the Secured Message data type. + * @param[out] get_element_ptr pointer to store finded element + * + * @retval true get element successfully + * @retval false get element failed + **/ +bool libspdm_get_element_from_opaque_data(libspdm_context_t *spdm_context, + size_t data_in_size, const void *data_in, + uint8_t element_id, uint8_t sm_data_id, + const void **get_element_ptr, size_t *get_element_len) +{ + const secured_message_general_opaque_data_table_header_t + *general_opaque_data_table_header; + const spdm_general_opaque_data_table_header_t + *spdm_general_opaque_data_table_header; + const secured_message_opaque_element_table_header_t + *opaque_element_table_header; + const secured_message_opaque_element_header_t + * secured_message_element_header; + + bool result; + uint8_t element_num; + uint8_t element_index; + size_t data_element_size; + size_t current_element_len; + size_t total_element_len; + + total_element_len = 0; + result = false; + + /*check parameter in*/ + if (element_id > SPDM_REGISTRY_ID_JEDEC) { + return false; + } + if ((data_in_size == 0) || (data_in == NULL)) { + return false; + } + + if (libspdm_get_connection_version (spdm_context) >= SPDM_MESSAGE_VERSION_12) { + spdm_general_opaque_data_table_header = data_in; + if (data_in_size < sizeof(spdm_general_opaque_data_table_header_t)) { + return false; + } + if (spdm_general_opaque_data_table_header->total_elements < 1) { + return false; + } + opaque_element_table_header = (const void *)(spdm_general_opaque_data_table_header + 1); + + element_num = spdm_general_opaque_data_table_header->total_elements; + + data_element_size = data_in_size - sizeof(spdm_general_opaque_data_table_header_t); + } else { + general_opaque_data_table_header = data_in; + if (data_in_size < sizeof(secured_message_general_opaque_data_table_header_t)) { + return false; + } + if ((general_opaque_data_table_header->spec_id != + SECURED_MESSAGE_OPAQUE_DATA_SPEC_ID) || + (general_opaque_data_table_header->opaque_version != + SECURED_MESSAGE_OPAQUE_VERSION) || + (general_opaque_data_table_header->total_elements < 1)) { + return false; + } + opaque_element_table_header = (const void *)(general_opaque_data_table_header + 1); + + element_num = general_opaque_data_table_header->total_elements; + + data_element_size = data_in_size - + sizeof(secured_message_general_opaque_data_table_header_t); + } + + for (element_index = 0; element_index < element_num; element_index++) { + /*ensure the opaque_element_table_header is valid*/ + if (total_element_len + sizeof(secured_message_opaque_element_table_header_t) > + data_element_size) { + return false; + } + + /*check element header id*/ + if ((opaque_element_table_header->id > SPDM_REGISTRY_ID_JEDEC) || + (opaque_element_table_header->vendor_len != 0)) { + return false; + } + + current_element_len = sizeof(secured_message_opaque_element_table_header_t) + + opaque_element_table_header->opaque_element_data_len; + /* Add Padding*/ + current_element_len = (current_element_len + 3) & ~3; + + total_element_len += current_element_len; + + if (data_element_size < total_element_len) { + return false; + } + + if (opaque_element_table_header->id == element_id) { + secured_message_element_header = (const void *)(opaque_element_table_header + 1); + if ((const uint8_t *)secured_message_element_header + + sizeof(secured_message_opaque_element_header_t) > + (const uint8_t *)data_in + data_in_size) { + return false; + } + + if ((secured_message_element_header->sm_data_id == sm_data_id) && + (secured_message_element_header->sm_data_version == + SECURED_MESSAGE_OPAQUE_ELEMENT_SMDATA_DATA_VERSION)) { + /*get element by element id*/ + *get_element_ptr = opaque_element_table_header; + *get_element_len = current_element_len; + result = true; + } + } + + /*move to next element*/ + opaque_element_table_header = (const secured_message_opaque_element_table_header_t *) + ((const uint8_t *)opaque_element_table_header + + current_element_len); + } + + /*ensure data size is right*/ + if (data_element_size != total_element_len) { + return false; + } + + return result; +} diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/libraries/libspdm/2.3.1/library/spdm_common_lib/libspdm_com_support.c nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/libraries/libspdm/2.3.1/library/spdm_common_lib/libspdm_com_support.c --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/libraries/libspdm/2.3.1/library/spdm_common_lib/libspdm_com_support.c 1970-01-01 00:00:00.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/libraries/libspdm/2.3.1/library/spdm_common_lib/libspdm_com_support.c 2024-03-05 22:14:15.000000000 +0000 @@ -0,0 +1,231 @@ +/** + * Copyright Notice: + * Copyright 2021-2022 DMTF. All rights reserved. + * License: BSD 3-Clause License. For full text see link: https://github.com/DMTF/libspdm/blob/main/LICENSE.md + **/ + +#include "internal/libspdm_common_lib.h" + +#if LIBSPDM_DEBUG_PRINT_ENABLE +void libspdm_internal_dump_hex_str(const uint8_t *data, size_t size) +{ + size_t index; + for (index = 0; index < size; index++) { + LIBSPDM_DEBUG((LIBSPDM_DEBUG_INFO, "%02x", (size_t)data[index])); + } +} + +void libspdm_internal_dump_data(const uint8_t *data, size_t size) +{ + size_t index; + for (index = 0; index < size; index++) { + LIBSPDM_DEBUG((LIBSPDM_DEBUG_INFO, "%02x ", (size_t)data[index])); + } +} + +void libspdm_internal_dump_hex(const uint8_t *data, size_t size) +{ + size_t index; + size_t count; + size_t left; + + #define COLUMN_SIZE (16 * 2) + + count = size / COLUMN_SIZE; + left = size % COLUMN_SIZE; + for (index = 0; index < count; index++) { + LIBSPDM_DEBUG((LIBSPDM_DEBUG_INFO, "%04x: ", index * COLUMN_SIZE)); + LIBSPDM_INTERNAL_DUMP_DATA(data + index * COLUMN_SIZE, COLUMN_SIZE); + LIBSPDM_DEBUG((LIBSPDM_DEBUG_INFO, "\n")); + } + + if (left != 0) { + LIBSPDM_DEBUG((LIBSPDM_DEBUG_INFO, "%04x: ", index * COLUMN_SIZE)); + LIBSPDM_INTERNAL_DUMP_DATA(data + index * COLUMN_SIZE, left); + LIBSPDM_DEBUG((LIBSPDM_DEBUG_INFO, "\n")); + } +} +#endif /* LIBSPDM_DEBUG_PRINT_ENABLE */ + +/** + * Reads a 24-bit value from memory that may be unaligned. + * + * @param buffer The pointer to a 24-bit value that may be unaligned. + * + * @return The 24-bit value read from buffer. + **/ +uint32_t libspdm_read_uint24(const uint8_t *buffer) +{ + return (uint32_t)(buffer[0] | buffer[1] << 8 | buffer[2] << 16); +} + +/** + * Writes a 24-bit value to memory that may be unaligned. + * + * @param buffer The pointer to a 24-bit value that may be unaligned. + * @param value 24-bit value to write to buffer. + **/ +void libspdm_write_uint24(uint8_t *buffer, uint32_t value) +{ + buffer[0] = (uint8_t)(value & 0xFF); + buffer[1] = (uint8_t)((value >> 8) & 0xFF); + buffer[2] = (uint8_t)((value >> 16) & 0xFF); +} + +/** + * Reads a 16-bit value from memory that may be unaligned. + * + * @param buffer The pointer to a 16-bit value that may be unaligned. + * + * @return The 16-bit value read from buffer. + **/ +uint16_t libspdm_read_uint16(const uint8_t *buffer) +{ + return (uint16_t)(buffer[0] | buffer[1] << 8); +} + +/** + * Writes a 16-bit value to memory that may be unaligned. + * + * @param buffer The pointer to a 16-bit value that may be unaligned. + * @param value 16-bit value to write to buffer. + **/ +void libspdm_write_uint16(uint8_t *buffer, uint16_t value) +{ + buffer[0] = (uint8_t)(value & 0xFF); + buffer[1] = (uint8_t)((value >> 8) & 0xFF); +} + +/** + * Reads a 32-bit value from memory that may be unaligned. + * + * @param buffer The pointer to a 32-bit value that may be unaligned. + * + * @return The 32-bit value read from buffer. + **/ +uint32_t libspdm_read_uint32(const uint8_t *buffer) +{ + return (uint32_t)(buffer[0] | buffer[1] << 8 | buffer[2] << 16 | buffer[3] << 24); +} + +/** + * Writes a 32-bit value to memory that may be unaligned. + * + * @param buffer The pointer to a 32-bit value that may be unaligned. + * @param value 32-bit value to write to buffer. + **/ +void libspdm_write_uint32(uint8_t *buffer, uint32_t value) +{ + buffer[0] = (uint8_t)(value & 0xFF); + buffer[1] = (uint8_t)((value >> 8) & 0xFF); + buffer[2] = (uint8_t)((value >> 16) & 0xFF); + buffer[3] = (uint8_t)((value >> 24) & 0xFF); +} + +/** + * Reads a 64-bit value from memory that may be unaligned. + * + * @param buffer The pointer to a 64-bit value that may be unaligned. + * + * @return The 64-bit value read from buffer. + **/ +uint64_t libspdm_read_uint64(const uint8_t *buffer) +{ + return (uint64_t)(buffer[0]) | + ((uint64_t)(buffer[1]) << 8) | + ((uint64_t)(buffer[2]) << 16) | + ((uint64_t)(buffer[3]) << 24) | + ((uint64_t)(buffer[4]) << 32) | + ((uint64_t)(buffer[5]) << 40) | + ((uint64_t)(buffer[6]) << 48) | + ((uint64_t)(buffer[7]) << 56); +} + +/** + * Writes a 64-bit value to memory that may be unaligned. + * + * @param buffer The pointer to a 64-bit value that may be unaligned. + * @param value 64-bit value to write to buffer. + **/ +void libspdm_write_uint64(uint8_t *buffer, uint64_t value) +{ + buffer[0] = (uint8_t)(value & 0xFF); + buffer[1] = (uint8_t)((value >> 8) & 0xFF); + buffer[2] = (uint8_t)((value >> 16) & 0xFF); + buffer[3] = (uint8_t)((value >> 24) & 0xFF); + buffer[4] = (uint8_t)((value >> 32) & 0xFF); + buffer[5] = (uint8_t)((value >> 40) & 0xFF); + buffer[6] = (uint8_t)((value >> 48) & 0xFF); + buffer[7] = (uint8_t)((value >> 56) & 0xFF); +} + +libspdm_return_t libspdm_append_managed_buffer(void *m_buffer, const void *buffer, + size_t buffer_size) +{ + libspdm_managed_buffer_t *managed_buffer; + + LIBSPDM_ASSERT(buffer != NULL); + + if (buffer_size == 0) { + return LIBSPDM_STATUS_SUCCESS; + } + + managed_buffer = m_buffer; + + LIBSPDM_ASSERT(buffer_size != 0); + LIBSPDM_ASSERT(managed_buffer->max_buffer_size >= managed_buffer->buffer_size); + + if (buffer_size > managed_buffer->max_buffer_size - managed_buffer->buffer_size) { + /* Do not LIBSPDM_ASSERT here, because command processor will append message from external.*/ + LIBSPDM_DEBUG((LIBSPDM_DEBUG_ERROR, + "libspdm_append_managed_buffer 0x%x fail, rest 0x%x only\n", + (uint32_t)buffer_size, + (uint32_t)(managed_buffer->max_buffer_size - managed_buffer->buffer_size))); + return LIBSPDM_STATUS_BUFFER_FULL; + } + LIBSPDM_ASSERT(buffer_size <= managed_buffer->max_buffer_size - managed_buffer->buffer_size); + + libspdm_copy_mem((uint8_t *)(managed_buffer + 1) + managed_buffer->buffer_size, + buffer_size, buffer, buffer_size); + managed_buffer->buffer_size += buffer_size; + + return LIBSPDM_STATUS_SUCCESS; +} + +void libspdm_reset_managed_buffer(void *m_buffer) +{ + libspdm_managed_buffer_t *managed_buffer; + + managed_buffer = m_buffer; + managed_buffer->buffer_size = 0; + + libspdm_zero_mem(managed_buffer + 1, managed_buffer->max_buffer_size); +} + +size_t libspdm_get_managed_buffer_size(void *m_buffer) +{ + libspdm_managed_buffer_t *managed_buffer; + + managed_buffer = m_buffer; + + return managed_buffer->buffer_size; +} + +void *libspdm_get_managed_buffer(void *m_buffer) +{ + libspdm_managed_buffer_t *managed_buffer; + + managed_buffer = m_buffer; + + return (managed_buffer + 1); +} + +void libspdm_init_managed_buffer(void *m_buffer, size_t max_buffer_size) +{ + libspdm_managed_buffer_t *managed_buffer; + + managed_buffer = m_buffer; + managed_buffer->max_buffer_size = max_buffer_size; + + libspdm_reset_managed_buffer(m_buffer); +} diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/libraries/libspdm/2.3.1/library/spdm_crypt_lib/libspdm_crypt_aead.c nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/libraries/libspdm/2.3.1/library/spdm_crypt_lib/libspdm_crypt_aead.c --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/libraries/libspdm/2.3.1/library/spdm_crypt_lib/libspdm_crypt_aead.c 1970-01-01 00:00:00.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/libraries/libspdm/2.3.1/library/spdm_crypt_lib/libspdm_crypt_aead.c 2024-03-05 22:14:15.000000000 +0000 @@ -0,0 +1,159 @@ +/** + * Copyright Notice: + * Copyright 2021-2022 DMTF. All rights reserved. + * License: BSD 3-Clause License. For full text see link: https://github.com/DMTF/libspdm/blob/main/LICENSE.md + **/ + +#include "internal/libspdm_crypt_lib.h" + +uint32_t libspdm_get_aead_key_size(uint16_t aead_cipher_suite) +{ + switch (aead_cipher_suite) { + case SPDM_ALGORITHMS_AEAD_CIPHER_SUITE_AES_128_GCM: + return 16; + case SPDM_ALGORITHMS_AEAD_CIPHER_SUITE_AES_256_GCM: + return 32; + case SPDM_ALGORITHMS_AEAD_CIPHER_SUITE_CHACHA20_POLY1305: + return 32; + case SPDM_ALGORITHMS_AEAD_CIPHER_SUITE_AEAD_SM4_GCM: + return 16; + default: + return 0; + } +} + +uint32_t libspdm_get_aead_iv_size(uint16_t aead_cipher_suite) +{ + switch (aead_cipher_suite) { + case SPDM_ALGORITHMS_AEAD_CIPHER_SUITE_AES_128_GCM: + return 12; + case SPDM_ALGORITHMS_AEAD_CIPHER_SUITE_AES_256_GCM: + return 12; + case SPDM_ALGORITHMS_AEAD_CIPHER_SUITE_CHACHA20_POLY1305: + return 12; + case SPDM_ALGORITHMS_AEAD_CIPHER_SUITE_AEAD_SM4_GCM: + return 12; + default: + return 0; + } +} + +uint32_t libspdm_get_aead_tag_size(uint16_t aead_cipher_suite) +{ + switch (aead_cipher_suite) { + case SPDM_ALGORITHMS_AEAD_CIPHER_SUITE_AES_128_GCM: + return 16; + case SPDM_ALGORITHMS_AEAD_CIPHER_SUITE_AES_256_GCM: + return 16; + case SPDM_ALGORITHMS_AEAD_CIPHER_SUITE_CHACHA20_POLY1305: + return 16; + case SPDM_ALGORITHMS_AEAD_CIPHER_SUITE_AEAD_SM4_GCM: + return 16; + default: + return 0; + } +} + +bool libspdm_aead_encryption(const spdm_version_number_t secured_message_version, + uint16_t aead_cipher_suite, const uint8_t *key, + size_t key_size, const uint8_t *iv, + size_t iv_size, const uint8_t *a_data, + size_t a_data_size, const uint8_t *data_in, + size_t data_in_size, uint8_t *tag_out, + size_t tag_size, uint8_t *data_out, + size_t *data_out_size) +{ + switch (aead_cipher_suite) { + case SPDM_ALGORITHMS_AEAD_CIPHER_SUITE_AES_128_GCM: +#if LIBSPDM_AEAD_GCM_SUPPORT + return libspdm_aead_aes_gcm_encrypt(key, key_size, iv, iv_size, a_data, + a_data_size, data_in, data_in_size, tag_out, + tag_size, data_out, data_out_size); +#else + LIBSPDM_ASSERT(false); + return false; +#endif + case SPDM_ALGORITHMS_AEAD_CIPHER_SUITE_AES_256_GCM: +#if LIBSPDM_AEAD_GCM_SUPPORT + return libspdm_aead_aes_gcm_encrypt(key, key_size, iv, iv_size, a_data, + a_data_size, data_in, data_in_size, tag_out, + tag_size, data_out, data_out_size); +#else + LIBSPDM_ASSERT(false); + return false; +#endif + case SPDM_ALGORITHMS_AEAD_CIPHER_SUITE_CHACHA20_POLY1305: +#if LIBSPDM_AEAD_CHACHA20_POLY1305_SUPPORT + return libspdm_aead_chacha20_poly1305_encrypt(key, key_size, iv, iv_size, a_data, + a_data_size, data_in, data_in_size, tag_out, + tag_size, data_out, data_out_size); +#else + LIBSPDM_ASSERT(false); + return false; +#endif + case SPDM_ALGORITHMS_AEAD_CIPHER_SUITE_AEAD_SM4_GCM: +#if LIBSPDM_AEAD_SM4_SUPPORT + return libspdm_aead_sm4_gcm_encrypt(key, key_size, iv, iv_size, a_data, + a_data_size, data_in, data_in_size, tag_out, + tag_size, data_out, data_out_size); +#else + LIBSPDM_ASSERT(false); + return false; +#endif + default: + LIBSPDM_ASSERT(false); + return false; + } +} + +bool libspdm_aead_decryption(const spdm_version_number_t secured_message_version, + uint16_t aead_cipher_suite, const uint8_t *key, + size_t key_size, const uint8_t *iv, + size_t iv_size, const uint8_t *a_data, + size_t a_data_size, const uint8_t *data_in, + size_t data_in_size, const uint8_t *tag, + size_t tag_size, uint8_t *data_out, + size_t *data_out_size) +{ + switch (aead_cipher_suite) { + case SPDM_ALGORITHMS_AEAD_CIPHER_SUITE_AES_128_GCM: +#if LIBSPDM_AEAD_GCM_SUPPORT + return libspdm_aead_aes_gcm_decrypt(key, key_size, iv, iv_size, a_data, + a_data_size, data_in, data_in_size, tag, + tag_size, data_out, data_out_size); +#else + LIBSPDM_ASSERT(false); + return false; +#endif + case SPDM_ALGORITHMS_AEAD_CIPHER_SUITE_AES_256_GCM: +#if LIBSPDM_AEAD_GCM_SUPPORT + return libspdm_aead_aes_gcm_decrypt(key, key_size, iv, iv_size, a_data, + a_data_size, data_in, data_in_size, tag, + tag_size, data_out, data_out_size); +#else + LIBSPDM_ASSERT(false); + return false; +#endif + case SPDM_ALGORITHMS_AEAD_CIPHER_SUITE_CHACHA20_POLY1305: +#if LIBSPDM_AEAD_CHACHA20_POLY1305_SUPPORT + return libspdm_aead_chacha20_poly1305_decrypt(key, key_size, iv, iv_size, a_data, + a_data_size, data_in, data_in_size, tag, + tag_size, data_out, data_out_size); +#else + LIBSPDM_ASSERT(false); + return false; +#endif + case SPDM_ALGORITHMS_AEAD_CIPHER_SUITE_AEAD_SM4_GCM: +#if LIBSPDM_AEAD_SM4_SUPPORT + return libspdm_aead_sm4_gcm_decrypt(key, key_size, iv, iv_size, a_data, + a_data_size, data_in, data_in_size, tag, + tag_size, data_out, data_out_size); +#else + LIBSPDM_ASSERT(false); + return false; +#endif + default: + LIBSPDM_ASSERT(false); + return false; + } +} diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/libraries/libspdm/2.3.1/library/spdm_crypt_lib/libspdm_crypt_asym.c nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/libraries/libspdm/2.3.1/library/spdm_crypt_lib/libspdm_crypt_asym.c --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/libraries/libspdm/2.3.1/library/spdm_crypt_lib/libspdm_crypt_asym.c 1970-01-01 00:00:00.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/libraries/libspdm/2.3.1/library/spdm_crypt_lib/libspdm_crypt_asym.c 2024-03-05 22:14:15.000000000 +0000 @@ -0,0 +1,1154 @@ +/** + * Copyright Notice: + * Copyright 2021-2022 DMTF. All rights reserved. + * License: BSD 3-Clause License. For full text see link: https://github.com/DMTF/libspdm/blob/main/LICENSE.md + **/ + +#include "internal/libspdm_crypt_lib.h" + +typedef struct { + bool is_requester; + uint8_t op_code; + const void *context; + size_t context_size; + size_t zero_pad_size; +} libspdm_signing_context_str_t; + +static const libspdm_signing_context_str_t m_libspdm_signing_context_str_table[] = { + {false, SPDM_CHALLENGE_AUTH, SPDM_CHALLENGE_AUTH_SIGN_CONTEXT, + SPDM_CHALLENGE_AUTH_SIGN_CONTEXT_SIZE, 36 - SPDM_CHALLENGE_AUTH_SIGN_CONTEXT_SIZE}, + {true, SPDM_CHALLENGE_AUTH, SPDM_MUT_CHALLENGE_AUTH_SIGN_CONTEXT, + SPDM_MUT_CHALLENGE_AUTH_SIGN_CONTEXT_SIZE, 36 - SPDM_MUT_CHALLENGE_AUTH_SIGN_CONTEXT_SIZE}, + {false, SPDM_MEASUREMENTS, SPDM_MEASUREMENTS_SIGN_CONTEXT, SPDM_MEASUREMENTS_SIGN_CONTEXT_SIZE, + 36 - SPDM_MEASUREMENTS_SIGN_CONTEXT_SIZE}, + {false, SPDM_KEY_EXCHANGE_RSP, SPDM_KEY_EXCHANGE_RESPONSE_SIGN_CONTEXT, + SPDM_KEY_EXCHANGE_RESPONSE_SIGN_CONTEXT_SIZE, + 36 - SPDM_KEY_EXCHANGE_RESPONSE_SIGN_CONTEXT_SIZE}, + {true, SPDM_FINISH, SPDM_FINISH_SIGN_CONTEXT, SPDM_FINISH_SIGN_CONTEXT_SIZE, + 36 - SPDM_FINISH_SIGN_CONTEXT_SIZE}, +}; + +#if LIBSPDM_RSA_SSA_SUPPORT +static bool libspdm_rsa_pkcs1_sign_with_nid_wrap (void *context, size_t hash_nid, + const uint8_t *param, size_t param_size, + const uint8_t *message, + size_t message_size, uint8_t *signature, + size_t *sig_size) +{ + return libspdm_rsa_pkcs1_sign_with_nid (context, hash_nid, + message, message_size, signature, sig_size); +} +#endif + +#if LIBSPDM_RSA_PSS_SUPPORT +static bool libspdm_rsa_pss_sign_wrap (void *context, size_t hash_nid, + const uint8_t *param, size_t param_size, + const uint8_t *message, + size_t message_size, uint8_t *signature, + size_t *sig_size) +{ + return libspdm_rsa_pss_sign (context, hash_nid, + message, message_size, signature, sig_size); +} +#endif + +#if LIBSPDM_ECDSA_SUPPORT +static bool libspdm_ecdsa_sign_wrap (void *context, size_t hash_nid, + const uint8_t *param, size_t param_size, + const uint8_t *message, + size_t message_size, uint8_t *signature, + size_t *sig_size) +{ + return libspdm_ecdsa_sign (context, hash_nid, + message, message_size, signature, sig_size); +} +#endif + +#if (LIBSPDM_EDDSA_ED25519_SUPPORT) || (LIBSPDM_EDDSA_ED448_SUPPORT) +static bool libspdm_eddsa_sign_wrap (void *context, size_t hash_nid, + const uint8_t *param, size_t param_size, + const uint8_t *message, + size_t message_size, uint8_t *signature, + size_t *sig_size) +{ + return libspdm_eddsa_sign (context, hash_nid, param, param_size, + message, message_size, signature, sig_size); +} +#endif + +#if LIBSPDM_SM2_DSA_SUPPORT +static bool libspdm_sm2_dsa_sign_wrap (void *context, size_t hash_nid, + const uint8_t *param, size_t param_size, + const uint8_t *message, + size_t message_size, uint8_t *signature, + size_t *sig_size) +{ + return libspdm_sm2_dsa_sign (context, hash_nid, param, param_size, + message, message_size, signature, sig_size); +} +#endif + +/** + * Get the SPDM signing context string, which is required since SPDM 1.2. + * + * @param spdm_version negotiated SPDM version + * @param op_code the SPDM opcode which requires the signing + * @param is_requester indicate if the signing is from a requester + * @param context_size SPDM signing context size + **/ +static const void *libspdm_get_signing_context_string ( + spdm_version_number_t spdm_version, + uint8_t op_code, + bool is_requester, + size_t *context_size) +{ + size_t index; + + /* It is introduced in SPDM 1.2*/ + LIBSPDM_ASSERT((spdm_version >> SPDM_VERSION_NUMBER_SHIFT_BIT) > SPDM_MESSAGE_VERSION_11); + + for (index = 0; index < LIBSPDM_ARRAY_SIZE(m_libspdm_signing_context_str_table); index++) { + if (m_libspdm_signing_context_str_table[index].is_requester == is_requester && + m_libspdm_signing_context_str_table[index].op_code == op_code) { + *context_size = m_libspdm_signing_context_str_table[index].context_size; + return m_libspdm_signing_context_str_table[index].context; + } + } + LIBSPDM_ASSERT(false); + return NULL; +} + +/** + * Create SPDM signing context, which is required since SPDM 1.2. + * + * @param spdm_version negotiated SPDM version + * @param op_code the SPDM opcode which requires the signing + * @param is_requester indicate if the signing is from a requester + * @param spdm_signing_context SPDM signing context + **/ +static void libspdm_create_signing_context ( + spdm_version_number_t spdm_version, + uint8_t op_code, + bool is_requester, + void *spdm_signing_context) +{ + size_t index; + char *context_str; + + /* It is introduced in SPDM 1.2*/ + LIBSPDM_ASSERT((spdm_version >> SPDM_VERSION_NUMBER_SHIFT_BIT) > SPDM_MESSAGE_VERSION_11); + + /* So far, it only leaves 1 bytes for version*/ + LIBSPDM_ASSERT((((spdm_version >> 12) & 0xF) < 10) && + (((spdm_version >> 8) & 0xF) < 10)); + + context_str = spdm_signing_context; + for (index = 0; index < 4; index++) { + libspdm_copy_mem(context_str, + SPDM_VERSION_1_2_SIGNING_PREFIX_CONTEXT_SIZE, + SPDM_VERSION_1_2_SIGNING_PREFIX_CONTEXT, + SPDM_VERSION_1_2_SIGNING_PREFIX_CONTEXT_SIZE); + /* patch the version*/ + context_str[11] = (char)('0' + ((spdm_version >> 12) & 0xF)); + context_str[13] = (char)('0' + ((spdm_version >> 8) & 0xF)); + context_str[15] = (char)('*'); + context_str += SPDM_VERSION_1_2_SIGNING_PREFIX_CONTEXT_SIZE; + } + for (index = 0; index < LIBSPDM_ARRAY_SIZE(m_libspdm_signing_context_str_table); index++) { + if (m_libspdm_signing_context_str_table[index].is_requester == is_requester && + m_libspdm_signing_context_str_table[index].op_code == op_code) { + libspdm_zero_mem ( + context_str, + m_libspdm_signing_context_str_table[index].zero_pad_size); + libspdm_copy_mem(context_str + m_libspdm_signing_context_str_table[index].zero_pad_size, + m_libspdm_signing_context_str_table[index].context_size, + m_libspdm_signing_context_str_table[index].context, + m_libspdm_signing_context_str_table[index].context_size); + return; + } + } + LIBSPDM_ASSERT(false); +} + +uint32_t libspdm_get_asym_signature_size(uint32_t base_asym_algo) +{ + switch (base_asym_algo) { + case SPDM_ALGORITHMS_BASE_ASYM_ALGO_TPM_ALG_RSASSA_2048: + case SPDM_ALGORITHMS_BASE_ASYM_ALGO_TPM_ALG_RSAPSS_2048: + return 256; + case SPDM_ALGORITHMS_BASE_ASYM_ALGO_TPM_ALG_RSASSA_3072: + case SPDM_ALGORITHMS_BASE_ASYM_ALGO_TPM_ALG_RSAPSS_3072: + return 384; + case SPDM_ALGORITHMS_BASE_ASYM_ALGO_TPM_ALG_RSASSA_4096: + case SPDM_ALGORITHMS_BASE_ASYM_ALGO_TPM_ALG_RSAPSS_4096: + return 512; + case SPDM_ALGORITHMS_BASE_ASYM_ALGO_TPM_ALG_ECDSA_ECC_NIST_P256: + return 32 * 2; + case SPDM_ALGORITHMS_BASE_ASYM_ALGO_TPM_ALG_ECDSA_ECC_NIST_P384: + return 48 * 2; + case SPDM_ALGORITHMS_BASE_ASYM_ALGO_TPM_ALG_ECDSA_ECC_NIST_P521: + return 66 * 2; + case SPDM_ALGORITHMS_BASE_ASYM_ALGO_TPM_ALG_SM2_ECC_SM2_P256: + return 32 * 2; + case SPDM_ALGORITHMS_BASE_ASYM_ALGO_EDDSA_ED25519: + return 32 * 2; + case SPDM_ALGORITHMS_BASE_ASYM_ALGO_EDDSA_ED448: + return 57 * 2; + default: + return 0; + } +} + +static bool libspdm_asym_sign_wrap (void *context, size_t hash_nid, uint32_t base_asym_algo, + const uint8_t *param, size_t param_size, + const uint8_t *message, size_t message_size, + uint8_t *signature, size_t *sig_size) +{ + switch (base_asym_algo) { + case SPDM_ALGORITHMS_BASE_ASYM_ALGO_TPM_ALG_RSASSA_2048: + case SPDM_ALGORITHMS_BASE_ASYM_ALGO_TPM_ALG_RSASSA_3072: + case SPDM_ALGORITHMS_BASE_ASYM_ALGO_TPM_ALG_RSASSA_4096: +#if LIBSPDM_RSA_SSA_SUPPORT + return libspdm_rsa_pkcs1_sign_with_nid_wrap(context, hash_nid, + param, param_size, + message, message_size, + signature, sig_size); +#else + LIBSPDM_ASSERT(false); + return false; +#endif + case SPDM_ALGORITHMS_BASE_ASYM_ALGO_TPM_ALG_RSAPSS_2048: + case SPDM_ALGORITHMS_BASE_ASYM_ALGO_TPM_ALG_RSAPSS_3072: + case SPDM_ALGORITHMS_BASE_ASYM_ALGO_TPM_ALG_RSAPSS_4096: +#if LIBSPDM_RSA_PSS_SUPPORT + return libspdm_rsa_pss_sign_wrap(context, hash_nid, + param, param_size, + message, message_size, + signature, sig_size); +#else + LIBSPDM_ASSERT(false); + return false; +#endif + case SPDM_ALGORITHMS_BASE_ASYM_ALGO_TPM_ALG_ECDSA_ECC_NIST_P256: + case SPDM_ALGORITHMS_BASE_ASYM_ALGO_TPM_ALG_ECDSA_ECC_NIST_P384: + case SPDM_ALGORITHMS_BASE_ASYM_ALGO_TPM_ALG_ECDSA_ECC_NIST_P521: +#if LIBSPDM_ECDSA_SUPPORT + return libspdm_ecdsa_sign_wrap(context, hash_nid, + param, param_size, + message, message_size, + signature, sig_size); +#else + LIBSPDM_ASSERT(false); + return false; +#endif + case SPDM_ALGORITHMS_BASE_ASYM_ALGO_EDDSA_ED25519: + case SPDM_ALGORITHMS_BASE_ASYM_ALGO_EDDSA_ED448: +#if (LIBSPDM_EDDSA_ED25519_SUPPORT) || (LIBSPDM_EDDSA_ED448_SUPPORT) + return libspdm_eddsa_sign_wrap(context, hash_nid, + param, param_size, + message, message_size, + signature, sig_size); +#else + LIBSPDM_ASSERT(false); + return false; +#endif + case SPDM_ALGORITHMS_BASE_ASYM_ALGO_TPM_ALG_SM2_ECC_SM2_P256: +#if LIBSPDM_SM2_DSA_SUPPORT + return libspdm_sm2_dsa_sign_wrap(context, hash_nid, + param, param_size, + message, message_size, + signature, sig_size); +#else + LIBSPDM_ASSERT(false); + return false; +#endif + default: + LIBSPDM_ASSERT(false); + return false; + } +} + +void libspdm_asym_free(uint32_t base_asym_algo, void *context) +{ + switch (base_asym_algo) { + case SPDM_ALGORITHMS_BASE_ASYM_ALGO_TPM_ALG_RSASSA_2048: + case SPDM_ALGORITHMS_BASE_ASYM_ALGO_TPM_ALG_RSASSA_3072: + case SPDM_ALGORITHMS_BASE_ASYM_ALGO_TPM_ALG_RSASSA_4096: + case SPDM_ALGORITHMS_BASE_ASYM_ALGO_TPM_ALG_RSAPSS_2048: + case SPDM_ALGORITHMS_BASE_ASYM_ALGO_TPM_ALG_RSAPSS_3072: + case SPDM_ALGORITHMS_BASE_ASYM_ALGO_TPM_ALG_RSAPSS_4096: +#if (LIBSPDM_RSA_SSA_SUPPORT) || (LIBSPDM_RSA_PSS_SUPPORT) + libspdm_rsa_free(context); +#else + LIBSPDM_ASSERT(false); +#endif + break; + case SPDM_ALGORITHMS_BASE_ASYM_ALGO_TPM_ALG_ECDSA_ECC_NIST_P256: + case SPDM_ALGORITHMS_BASE_ASYM_ALGO_TPM_ALG_ECDSA_ECC_NIST_P384: + case SPDM_ALGORITHMS_BASE_ASYM_ALGO_TPM_ALG_ECDSA_ECC_NIST_P521: +#if LIBSPDM_ECDSA_SUPPORT + libspdm_ec_free(context); +#else + LIBSPDM_ASSERT(false); +#endif + break; + case SPDM_ALGORITHMS_BASE_ASYM_ALGO_EDDSA_ED25519: + case SPDM_ALGORITHMS_BASE_ASYM_ALGO_EDDSA_ED448: +#if (LIBSPDM_EDDSA_ED25519_SUPPORT) || (LIBSPDM_EDDSA_ED448_SUPPORT) + libspdm_ecd_free(context); +#else + LIBSPDM_ASSERT(false); +#endif + break; + case SPDM_ALGORITHMS_BASE_ASYM_ALGO_TPM_ALG_SM2_ECC_SM2_P256: +#if LIBSPDM_SM2_DSA_SUPPORT + libspdm_sm2_dsa_free(context); +#else + LIBSPDM_ASSERT(false); +#endif + break; + default: + LIBSPDM_ASSERT(false); + break; + } +} + +/** + * Return if asymmetric function need message hash. + * + * @param base_asym_algo SPDM base_asym_algo + * + * @retval true asymmetric function need message hash + * @retval false asymmetric function need raw message + **/ +static bool libspdm_asym_func_need_hash(uint32_t base_asym_algo) +{ + switch (base_asym_algo) { + case SPDM_ALGORITHMS_BASE_ASYM_ALGO_TPM_ALG_RSASSA_2048: + case SPDM_ALGORITHMS_BASE_ASYM_ALGO_TPM_ALG_RSASSA_3072: + case SPDM_ALGORITHMS_BASE_ASYM_ALGO_TPM_ALG_RSASSA_4096: + case SPDM_ALGORITHMS_BASE_ASYM_ALGO_TPM_ALG_RSAPSS_2048: + case SPDM_ALGORITHMS_BASE_ASYM_ALGO_TPM_ALG_RSAPSS_3072: + case SPDM_ALGORITHMS_BASE_ASYM_ALGO_TPM_ALG_RSAPSS_4096: + return true; + case SPDM_ALGORITHMS_BASE_ASYM_ALGO_TPM_ALG_ECDSA_ECC_NIST_P256: + case SPDM_ALGORITHMS_BASE_ASYM_ALGO_TPM_ALG_ECDSA_ECC_NIST_P384: + case SPDM_ALGORITHMS_BASE_ASYM_ALGO_TPM_ALG_ECDSA_ECC_NIST_P521: + return true; + case SPDM_ALGORITHMS_BASE_ASYM_ALGO_EDDSA_ED25519: + case SPDM_ALGORITHMS_BASE_ASYM_ALGO_EDDSA_ED448: + case SPDM_ALGORITHMS_BASE_ASYM_ALGO_TPM_ALG_SM2_ECC_SM2_P256: + return false; + default: + LIBSPDM_ASSERT(false); + break; + } + + return false; +} + +#if LIBSPDM_RSA_SSA_SUPPORT +static bool libspdm_rsa_pkcs1_verify_with_nid_wrap (void *context, size_t hash_nid, + const uint8_t *param, size_t param_size, + const uint8_t *message, + size_t message_size, + const uint8_t *signature, + size_t sig_size) +{ + return libspdm_rsa_pkcs1_verify_with_nid (context, hash_nid, + message, message_size, signature, sig_size); +} +#endif + +#if LIBSPDM_RSA_PSS_SUPPORT +static bool libspdm_rsa_pss_verify_wrap (void *context, size_t hash_nid, + const uint8_t *param, size_t param_size, + const uint8_t *message, + size_t message_size, + const uint8_t *signature, + size_t sig_size) +{ + return libspdm_rsa_pss_verify (context, hash_nid, message, message_size, signature, sig_size); +} +#endif + +#if LIBSPDM_ECDSA_SUPPORT +bool libspdm_ecdsa_verify_wrap (void *context, size_t hash_nid, + const uint8_t *param, size_t param_size, + const uint8_t *message, + size_t message_size, + const uint8_t *signature, + size_t sig_size) +{ + return libspdm_ecdsa_verify (context, hash_nid, message, message_size, signature, sig_size); +} +#endif + +#if (LIBSPDM_EDDSA_ED25519_SUPPORT) || (LIBSPDM_EDDSA_ED448_SUPPORT) +bool libspdm_eddsa_verify_wrap (void *context, size_t hash_nid, + const uint8_t *param, size_t param_size, + const uint8_t *message, + size_t message_size, + const uint8_t *signature, + size_t sig_size) +{ + return libspdm_eddsa_verify (context, hash_nid, param, param_size, + message, message_size, signature, sig_size); +} +#endif + +#if LIBSPDM_SM2_DSA_SUPPORT +bool libspdm_sm2_dsa_verify_wrap (void *context, size_t hash_nid, + const uint8_t *param, size_t param_size, + const uint8_t *message, + size_t message_size, + const uint8_t *signature, + size_t sig_size) +{ + return libspdm_sm2_dsa_verify (context, hash_nid, param, param_size, + message, message_size, signature, sig_size); +} +#endif + +static bool libspdm_asym_verify_wrap( + void *context, size_t hash_nid, uint32_t base_asym_algo, + const uint8_t *param, size_t param_size, + const uint8_t *message, size_t message_size, + const uint8_t *signature, size_t sig_size) +{ + switch (base_asym_algo) { + case SPDM_ALGORITHMS_BASE_ASYM_ALGO_TPM_ALG_RSASSA_2048: + case SPDM_ALGORITHMS_BASE_ASYM_ALGO_TPM_ALG_RSASSA_3072: + case SPDM_ALGORITHMS_BASE_ASYM_ALGO_TPM_ALG_RSASSA_4096: +#if LIBSPDM_RSA_SSA_SUPPORT + return libspdm_rsa_pkcs1_verify_with_nid_wrap(context, hash_nid, + param, param_size, + message, message_size, + signature, sig_size); +#else + LIBSPDM_ASSERT(false); + return false; +#endif + case SPDM_ALGORITHMS_BASE_ASYM_ALGO_TPM_ALG_RSAPSS_2048: + case SPDM_ALGORITHMS_BASE_ASYM_ALGO_TPM_ALG_RSAPSS_3072: + case SPDM_ALGORITHMS_BASE_ASYM_ALGO_TPM_ALG_RSAPSS_4096: +#if LIBSPDM_RSA_PSS_SUPPORT + return libspdm_rsa_pss_verify_wrap(context, hash_nid, + param, param_size, + message, message_size, + signature, sig_size); +#else + LIBSPDM_ASSERT(false); + return false; +#endif + case SPDM_ALGORITHMS_BASE_ASYM_ALGO_TPM_ALG_ECDSA_ECC_NIST_P256: + case SPDM_ALGORITHMS_BASE_ASYM_ALGO_TPM_ALG_ECDSA_ECC_NIST_P384: + case SPDM_ALGORITHMS_BASE_ASYM_ALGO_TPM_ALG_ECDSA_ECC_NIST_P521: +#if LIBSPDM_ECDSA_SUPPORT + return libspdm_ecdsa_verify_wrap(context, hash_nid, + param, param_size, + message, message_size, + signature, sig_size); +#else + LIBSPDM_ASSERT(false); + return false; +#endif + case SPDM_ALGORITHMS_BASE_ASYM_ALGO_EDDSA_ED25519: + case SPDM_ALGORITHMS_BASE_ASYM_ALGO_EDDSA_ED448: +#if (LIBSPDM_EDDSA_ED25519_SUPPORT) || (LIBSPDM_EDDSA_ED448_SUPPORT) + return libspdm_eddsa_verify_wrap(context, hash_nid, + param, param_size, + message, message_size, + signature, sig_size); +#else + LIBSPDM_ASSERT(false); + return false; +#endif + case SPDM_ALGORITHMS_BASE_ASYM_ALGO_TPM_ALG_SM2_ECC_SM2_P256: +#if LIBSPDM_SM2_DSA_SUPPORT + return libspdm_sm2_dsa_verify_wrap(context, hash_nid, + param, param_size, + message, message_size, + signature, sig_size); +#else + LIBSPDM_ASSERT(false); + return false; +#endif + default: + LIBSPDM_ASSERT(false); + return false; + } +} + +bool libspdm_asym_verify( + spdm_version_number_t spdm_version, uint8_t op_code, + uint32_t base_asym_algo, uint32_t base_hash_algo, + void *context, const uint8_t *message, + size_t message_size, const uint8_t *signature, + size_t sig_size) +{ + bool need_hash; + uint8_t message_hash[LIBSPDM_MAX_HASH_SIZE]; + size_t hash_size; + bool result; + size_t hash_nid; + uint8_t spdm12_signing_context_with_hash[SPDM_VERSION_1_2_SIGNING_CONTEXT_SIZE + + LIBSPDM_MAX_HASH_SIZE]; + const void *param; + size_t param_size; + + hash_nid = libspdm_get_hash_nid(base_hash_algo); + need_hash = libspdm_asym_func_need_hash(base_asym_algo); + + param = NULL; + param_size = 0; + + if ((spdm_version >> SPDM_VERSION_NUMBER_SHIFT_BIT) > SPDM_MESSAGE_VERSION_11) { + /* Need use SPDM 1.2 signing. */ + switch (base_asym_algo) { + case SPDM_ALGORITHMS_BASE_ASYM_ALGO_TPM_ALG_SM2_ECC_SM2_P256: + param = ""; + param_size = 0; + break; + case SPDM_ALGORITHMS_BASE_ASYM_ALGO_EDDSA_ED25519: + hash_nid = LIBSPDM_CRYPTO_NID_NULL; + break; + case SPDM_ALGORITHMS_BASE_ASYM_ALGO_EDDSA_ED448: + hash_nid = LIBSPDM_CRYPTO_NID_NULL; + param = libspdm_get_signing_context_string (spdm_version, op_code, false, ¶m_size); + break; + default: + /* pass thru for rest algorithm */ + break; + } + + libspdm_create_signing_context (spdm_version, op_code, false, + spdm12_signing_context_with_hash); + hash_size = libspdm_get_hash_size(base_hash_algo); + result = libspdm_hash_all(base_hash_algo, message, message_size, + &spdm12_signing_context_with_hash[ + SPDM_VERSION_1_2_SIGNING_CONTEXT_SIZE]); + if (!result) { + return false; + } + + /* re-assign message and message_size for signing */ + hash_size = libspdm_get_hash_size(base_hash_algo); + message = spdm12_signing_context_with_hash; + message_size = SPDM_VERSION_1_2_SIGNING_CONTEXT_SIZE + hash_size; + + /* Passthru */ + } + + if (need_hash) { + hash_size = libspdm_get_hash_size(base_hash_algo); + result = libspdm_hash_all(base_hash_algo, message, message_size, message_hash); + if (!result) { + return false; + } + return libspdm_asym_verify_wrap(context, hash_nid, base_asym_algo, + param, param_size, + message_hash, hash_size, + signature, sig_size); + } else { + return libspdm_asym_verify_wrap(context, hash_nid, base_asym_algo, + param, param_size, + message, message_size, + signature, sig_size); + } +} + +bool libspdm_asym_verify_hash( + spdm_version_number_t spdm_version, uint8_t op_code, + uint32_t base_asym_algo, uint32_t base_hash_algo, + void *context, const uint8_t *message_hash, + size_t hash_size, const uint8_t *signature, + size_t sig_size) +{ + bool need_hash; + uint8_t *message; + size_t message_size; + uint8_t full_message_hash[LIBSPDM_MAX_HASH_SIZE]; + bool result; + size_t hash_nid; + uint8_t spdm12_signing_context_with_hash[SPDM_VERSION_1_2_SIGNING_CONTEXT_SIZE + + LIBSPDM_MAX_HASH_SIZE]; + const void *param; + size_t param_size; + + hash_nid = libspdm_get_hash_nid(base_hash_algo); + need_hash = libspdm_asym_func_need_hash(base_asym_algo); + LIBSPDM_ASSERT (hash_size == libspdm_get_hash_size(base_hash_algo)); + + param = NULL; + param_size = 0; + + if ((spdm_version >> SPDM_VERSION_NUMBER_SHIFT_BIT) > SPDM_MESSAGE_VERSION_11) { + /* Need use SPDM 1.2 signing */ + switch (base_asym_algo) { + case SPDM_ALGORITHMS_BASE_ASYM_ALGO_TPM_ALG_SM2_ECC_SM2_P256: + param = ""; + param_size = 0; + break; + case SPDM_ALGORITHMS_BASE_ASYM_ALGO_EDDSA_ED25519: + hash_nid = LIBSPDM_CRYPTO_NID_NULL; + break; + case SPDM_ALGORITHMS_BASE_ASYM_ALGO_EDDSA_ED448: + hash_nid = LIBSPDM_CRYPTO_NID_NULL; + param = libspdm_get_signing_context_string (spdm_version, op_code, false, ¶m_size); + break; + default: + /* pass thru for rest algorithm */ + break; + } + + libspdm_create_signing_context (spdm_version, op_code, false, + spdm12_signing_context_with_hash); + libspdm_copy_mem(&spdm12_signing_context_with_hash[SPDM_VERSION_1_2_SIGNING_CONTEXT_SIZE], + sizeof(spdm12_signing_context_with_hash) + - (&spdm12_signing_context_with_hash[SPDM_VERSION_1_2_SIGNING_CONTEXT_SIZE] + - spdm12_signing_context_with_hash), + message_hash, hash_size); + + /* assign message and message_size for signing */ + message = spdm12_signing_context_with_hash; + message_size = SPDM_VERSION_1_2_SIGNING_CONTEXT_SIZE + hash_size; + + if (need_hash) { + result = libspdm_hash_all(base_hash_algo, message, message_size, full_message_hash); + if (!result) { + return false; + } + return libspdm_asym_verify_wrap(context, hash_nid, base_asym_algo, + param, param_size, + full_message_hash, hash_size, + signature, sig_size); + } else { + return libspdm_asym_verify_wrap(context, hash_nid, base_asym_algo, + param, param_size, + message, message_size, + signature, sig_size); + } + + /* SPDM 1.2 signing done. */ + } + + if (need_hash) { + return libspdm_asym_verify_wrap(context, hash_nid, base_asym_algo, + param, param_size, + message_hash, hash_size, + signature, sig_size); + } else { + LIBSPDM_ASSERT(false); + return false; + } +} + +bool libspdm_asym_sign( + spdm_version_number_t spdm_version, uint8_t op_code, + uint32_t base_asym_algo, uint32_t base_hash_algo, + void *context, const uint8_t *message, + size_t message_size, uint8_t *signature, + size_t *sig_size) +{ + bool need_hash; + uint8_t message_hash[LIBSPDM_MAX_HASH_SIZE]; + size_t hash_size; + bool result; + size_t hash_nid; + uint8_t spdm12_signing_context_with_hash[SPDM_VERSION_1_2_SIGNING_CONTEXT_SIZE + + LIBSPDM_MAX_HASH_SIZE]; + const void *param; + size_t param_size; + + hash_nid = libspdm_get_hash_nid(base_hash_algo); + need_hash = libspdm_asym_func_need_hash(base_asym_algo); + + param = NULL; + param_size = 0; + + if ((spdm_version >> SPDM_VERSION_NUMBER_SHIFT_BIT) > SPDM_MESSAGE_VERSION_11) { + /* Need use SPDM 1.2 signing */ + switch (base_asym_algo) { + case SPDM_ALGORITHMS_BASE_ASYM_ALGO_TPM_ALG_SM2_ECC_SM2_P256: + param = ""; + param_size = 0; + break; + case SPDM_ALGORITHMS_BASE_ASYM_ALGO_EDDSA_ED25519: + hash_nid = LIBSPDM_CRYPTO_NID_NULL; + break; + case SPDM_ALGORITHMS_BASE_ASYM_ALGO_EDDSA_ED448: + hash_nid = LIBSPDM_CRYPTO_NID_NULL; + param = libspdm_get_signing_context_string (spdm_version, op_code, false, ¶m_size); + break; + default: + /* pass thru for rest algorithm */ + break; + } + + libspdm_create_signing_context (spdm_version, op_code, false, + spdm12_signing_context_with_hash); + hash_size = libspdm_get_hash_size(base_hash_algo); + result = libspdm_hash_all(base_hash_algo, message, message_size, + &spdm12_signing_context_with_hash[ + SPDM_VERSION_1_2_SIGNING_CONTEXT_SIZE]); + if (!result) { + return false; + } + + /* re-assign message and message_size for signing */ + hash_size = libspdm_get_hash_size(base_hash_algo); + message = spdm12_signing_context_with_hash; + message_size = SPDM_VERSION_1_2_SIGNING_CONTEXT_SIZE + hash_size; + + /* Passthru*/ + } + + if (need_hash) { + hash_size = libspdm_get_hash_size(base_hash_algo); + result = libspdm_hash_all(base_hash_algo, message, message_size, message_hash); + if (!result) { + return false; + } + return libspdm_asym_sign_wrap(context, hash_nid, base_asym_algo, + param, param_size, + message_hash, hash_size, + signature, sig_size); + } else { + return libspdm_asym_sign_wrap(context, hash_nid, base_asym_algo, + param, param_size, + message, message_size, + signature, sig_size); + } +} + +bool libspdm_asym_sign_hash( + spdm_version_number_t spdm_version, uint8_t op_code, + uint32_t base_asym_algo, uint32_t base_hash_algo, + void *context, const uint8_t *message_hash, + size_t hash_size, uint8_t *signature, + size_t *sig_size) +{ + bool need_hash; + uint8_t *message; + size_t message_size; + uint8_t full_message_hash[LIBSPDM_MAX_HASH_SIZE]; + bool result; + size_t hash_nid; + uint8_t spdm12_signing_context_with_hash[SPDM_VERSION_1_2_SIGNING_CONTEXT_SIZE + + LIBSPDM_MAX_HASH_SIZE]; + const void *param; + size_t param_size; + + hash_nid = libspdm_get_hash_nid(base_hash_algo); + need_hash = libspdm_asym_func_need_hash(base_asym_algo); + LIBSPDM_ASSERT (hash_size == libspdm_get_hash_size(base_hash_algo)); + + param = NULL; + param_size = 0; + + if ((spdm_version >> SPDM_VERSION_NUMBER_SHIFT_BIT) > SPDM_MESSAGE_VERSION_11) { + /* Need use SPDM 1.2 signing */ + switch (base_asym_algo) { + case SPDM_ALGORITHMS_BASE_ASYM_ALGO_TPM_ALG_SM2_ECC_SM2_P256: + param = ""; + param_size = 0; + break; + case SPDM_ALGORITHMS_BASE_ASYM_ALGO_EDDSA_ED25519: + hash_nid = LIBSPDM_CRYPTO_NID_NULL; + break; + case SPDM_ALGORITHMS_BASE_ASYM_ALGO_EDDSA_ED448: + hash_nid = LIBSPDM_CRYPTO_NID_NULL; + param = libspdm_get_signing_context_string (spdm_version, op_code, false, ¶m_size); + break; + default: + /* pass thru for rest algorithm */ + break; + } + + libspdm_create_signing_context (spdm_version, op_code, false, + spdm12_signing_context_with_hash); + libspdm_copy_mem(&spdm12_signing_context_with_hash[SPDM_VERSION_1_2_SIGNING_CONTEXT_SIZE], + sizeof(spdm12_signing_context_with_hash) + - (&spdm12_signing_context_with_hash[SPDM_VERSION_1_2_SIGNING_CONTEXT_SIZE] + - spdm12_signing_context_with_hash), + message_hash, hash_size); + + /* assign message and message_size for signing */ + message = spdm12_signing_context_with_hash; + message_size = SPDM_VERSION_1_2_SIGNING_CONTEXT_SIZE + hash_size; + + if (need_hash) { + result = libspdm_hash_all(base_hash_algo, message, message_size, full_message_hash); + if (!result) { + return false; + } + return libspdm_asym_sign_wrap(context, hash_nid, base_asym_algo, + param, param_size, + full_message_hash, hash_size, + signature, sig_size); + } else { + return libspdm_asym_sign_wrap(context, hash_nid, base_asym_algo, + param, param_size, + message, message_size, + signature, sig_size); + } + + /* SPDM 1.2 signing done. */ + } + + if (need_hash) { + return libspdm_asym_sign_wrap(context, hash_nid, base_asym_algo, + param, param_size, + message_hash, hash_size, + signature, sig_size); + } else { + LIBSPDM_ASSERT (false); + return false; + } +} + +uint32_t libspdm_get_req_asym_signature_size(uint16_t req_base_asym_alg) +{ + return libspdm_get_asym_signature_size(req_base_asym_alg); +} + +void libspdm_req_asym_free(uint16_t req_base_asym_alg, void *context) +{ + libspdm_asym_free(req_base_asym_alg, context); +} + +bool libspdm_req_asym_func_need_hash(uint16_t req_base_asym_alg) +{ + return libspdm_asym_func_need_hash(req_base_asym_alg); +} + +bool libspdm_req_asym_verify( + spdm_version_number_t spdm_version, uint8_t op_code, + uint16_t req_base_asym_alg, + uint32_t base_hash_algo, void *context, + const uint8_t *message, size_t message_size, + const uint8_t *signature, size_t sig_size) +{ + bool need_hash; + uint8_t message_hash[LIBSPDM_MAX_HASH_SIZE]; + size_t hash_size; + bool result; + size_t hash_nid; + uint8_t spdm12_signing_context_with_hash[SPDM_VERSION_1_2_SIGNING_CONTEXT_SIZE + + LIBSPDM_MAX_HASH_SIZE]; + const void *param; + size_t param_size; + + hash_nid = libspdm_get_hash_nid(base_hash_algo); + need_hash = libspdm_req_asym_func_need_hash(req_base_asym_alg); + + param = NULL; + param_size = 0; + + if ((spdm_version >> SPDM_VERSION_NUMBER_SHIFT_BIT) > SPDM_MESSAGE_VERSION_11) { + /* Need use SPDM 1.2 signing */ + switch (req_base_asym_alg) { + case SPDM_ALGORITHMS_BASE_ASYM_ALGO_TPM_ALG_SM2_ECC_SM2_P256: + param = ""; + param_size = 0; + break; + case SPDM_ALGORITHMS_BASE_ASYM_ALGO_EDDSA_ED25519: + hash_nid = LIBSPDM_CRYPTO_NID_NULL; + break; + case SPDM_ALGORITHMS_BASE_ASYM_ALGO_EDDSA_ED448: + hash_nid = LIBSPDM_CRYPTO_NID_NULL; + param = libspdm_get_signing_context_string (spdm_version, op_code, true, ¶m_size); + break; + default: + /* pass thru for rest algorithm */ + break; + } + + libspdm_create_signing_context (spdm_version, op_code, true, + spdm12_signing_context_with_hash); + hash_size = libspdm_get_hash_size(base_hash_algo); + result = libspdm_hash_all(base_hash_algo, message, message_size, + &spdm12_signing_context_with_hash[ + SPDM_VERSION_1_2_SIGNING_CONTEXT_SIZE]); + if (!result) { + return false; + } + + /* re-assign message and message_size for signing */ + hash_size = libspdm_get_hash_size(base_hash_algo); + message = spdm12_signing_context_with_hash; + message_size = SPDM_VERSION_1_2_SIGNING_CONTEXT_SIZE + hash_size; + + /* Passthru */ + } + + if (need_hash) { + hash_size = libspdm_get_hash_size(base_hash_algo); + result = libspdm_hash_all(base_hash_algo, message, message_size, message_hash); + if (!result) { + return false; + } + return libspdm_asym_verify_wrap(context, hash_nid, req_base_asym_alg, + param, param_size, + message_hash, hash_size, + signature, sig_size); + } else { + return libspdm_asym_verify_wrap(context, hash_nid, req_base_asym_alg, + param, param_size, + message, message_size, + signature, sig_size); + } +} + +bool libspdm_req_asym_verify_hash( + spdm_version_number_t spdm_version, uint8_t op_code, + uint16_t req_base_asym_alg, + uint32_t base_hash_algo, void *context, + const uint8_t *message_hash, size_t hash_size, + const uint8_t *signature, size_t sig_size) +{ + bool need_hash; + uint8_t *message; + size_t message_size; + uint8_t full_message_hash[LIBSPDM_MAX_HASH_SIZE]; + bool result; + size_t hash_nid; + uint8_t spdm12_signing_context_with_hash[SPDM_VERSION_1_2_SIGNING_CONTEXT_SIZE + + LIBSPDM_MAX_HASH_SIZE]; + const void *param; + size_t param_size; + + hash_nid = libspdm_get_hash_nid(base_hash_algo); + need_hash = libspdm_req_asym_func_need_hash(req_base_asym_alg); + LIBSPDM_ASSERT (hash_size == libspdm_get_hash_size(base_hash_algo)); + + param = NULL; + param_size = 0; + + if ((spdm_version >> SPDM_VERSION_NUMBER_SHIFT_BIT) > SPDM_MESSAGE_VERSION_11) { + /* Need use SPDM 1.2 signing */ + switch (req_base_asym_alg) { + case SPDM_ALGORITHMS_BASE_ASYM_ALGO_TPM_ALG_SM2_ECC_SM2_P256: + param = ""; + param_size = 0; + break; + case SPDM_ALGORITHMS_BASE_ASYM_ALGO_EDDSA_ED25519: + hash_nid = LIBSPDM_CRYPTO_NID_NULL; + break; + case SPDM_ALGORITHMS_BASE_ASYM_ALGO_EDDSA_ED448: + hash_nid = LIBSPDM_CRYPTO_NID_NULL; + param = libspdm_get_signing_context_string (spdm_version, op_code, true, ¶m_size); + break; + default: + /* pass thru for rest algorithm */ + break; + } + + libspdm_create_signing_context (spdm_version, op_code, true, + spdm12_signing_context_with_hash); + libspdm_copy_mem(&spdm12_signing_context_with_hash[SPDM_VERSION_1_2_SIGNING_CONTEXT_SIZE], + sizeof(spdm12_signing_context_with_hash) + - (&spdm12_signing_context_with_hash[SPDM_VERSION_1_2_SIGNING_CONTEXT_SIZE] + - spdm12_signing_context_with_hash), + message_hash, hash_size); + + /* assign message and message_size for signing */ + message = spdm12_signing_context_with_hash; + message_size = SPDM_VERSION_1_2_SIGNING_CONTEXT_SIZE + hash_size; + + if (need_hash) { + result = libspdm_hash_all(base_hash_algo, message, message_size, + full_message_hash); + if (!result) { + return false; + } + return libspdm_asym_verify_wrap(context, hash_nid, req_base_asym_alg, + param, param_size, + full_message_hash, hash_size, + signature, sig_size); + } else { + return libspdm_asym_verify_wrap(context, hash_nid, req_base_asym_alg, + param, param_size, + message, message_size, + signature, sig_size); + } + /* SPDM 1.2 signing done. */ + } + + if (need_hash) { + return libspdm_asym_verify_wrap(context, hash_nid, req_base_asym_alg, + param, param_size, + message_hash, hash_size, + signature, sig_size); + } else { + LIBSPDM_ASSERT (false); + return false; + } +} + +bool libspdm_req_asym_sign( + spdm_version_number_t spdm_version, uint8_t op_code, + uint16_t req_base_asym_alg, + uint32_t base_hash_algo, void *context, + const uint8_t *message, size_t message_size, + uint8_t *signature, size_t *sig_size) +{ + bool need_hash; + uint8_t message_hash[LIBSPDM_MAX_HASH_SIZE]; + size_t hash_size; + bool result; + size_t hash_nid; + uint8_t spdm12_signing_context_with_hash[SPDM_VERSION_1_2_SIGNING_CONTEXT_SIZE + + LIBSPDM_MAX_HASH_SIZE]; + const void *param; + size_t param_size; + + hash_nid = libspdm_get_hash_nid(base_hash_algo); + need_hash = libspdm_req_asym_func_need_hash(req_base_asym_alg); + + param = NULL; + param_size = 0; + + if ((spdm_version >> SPDM_VERSION_NUMBER_SHIFT_BIT) > SPDM_MESSAGE_VERSION_11) { + /* Need use SPDM 1.2 signing */ + switch (req_base_asym_alg) { + case SPDM_ALGORITHMS_BASE_ASYM_ALGO_TPM_ALG_SM2_ECC_SM2_P256: + param = ""; + param_size = 0; + break; + case SPDM_ALGORITHMS_BASE_ASYM_ALGO_EDDSA_ED25519: + hash_nid = LIBSPDM_CRYPTO_NID_NULL; + break; + case SPDM_ALGORITHMS_BASE_ASYM_ALGO_EDDSA_ED448: + hash_nid = LIBSPDM_CRYPTO_NID_NULL; + param = libspdm_get_signing_context_string (spdm_version, op_code, true, ¶m_size); + break; + default: + /* pass thru for rest algorithm */ + break; + } + + libspdm_create_signing_context (spdm_version, op_code, true, + spdm12_signing_context_with_hash); + hash_size = libspdm_get_hash_size(base_hash_algo); + result = libspdm_hash_all(base_hash_algo, message, message_size, + &spdm12_signing_context_with_hash[ + SPDM_VERSION_1_2_SIGNING_CONTEXT_SIZE]); + if (!result) { + return false; + } + + /* re-assign message and message_size for signing */ + hash_size = libspdm_get_hash_size(base_hash_algo); + message = spdm12_signing_context_with_hash; + message_size = SPDM_VERSION_1_2_SIGNING_CONTEXT_SIZE + hash_size; + + /* Passthru */ + } + + if (need_hash) { + hash_size = libspdm_get_hash_size(base_hash_algo); + result = libspdm_hash_all(base_hash_algo, message, message_size, + message_hash); + if (!result) { + return false; + } + return libspdm_asym_sign_wrap(context, hash_nid, req_base_asym_alg, + param, param_size, + message_hash, hash_size, + signature, sig_size); + } else { + return libspdm_asym_sign_wrap(context, hash_nid, req_base_asym_alg, + param, param_size, + message, message_size, + signature, sig_size); + } +} + +bool libspdm_req_asym_sign_hash( + spdm_version_number_t spdm_version, uint8_t op_code, + uint16_t req_base_asym_alg, + uint32_t base_hash_algo, void *context, + const uint8_t *message_hash, size_t hash_size, + uint8_t *signature, size_t *sig_size) +{ + bool need_hash; + uint8_t *message; + size_t message_size; + uint8_t full_message_hash[LIBSPDM_MAX_HASH_SIZE]; + bool result; + size_t hash_nid; + uint8_t spdm12_signing_context_with_hash[SPDM_VERSION_1_2_SIGNING_CONTEXT_SIZE + + LIBSPDM_MAX_HASH_SIZE]; + const void *param; + size_t param_size; + + hash_nid = libspdm_get_hash_nid(base_hash_algo); + need_hash = libspdm_req_asym_func_need_hash(req_base_asym_alg); + LIBSPDM_ASSERT (hash_size == libspdm_get_hash_size(base_hash_algo)); + + param = NULL; + param_size = 0; + + if ((spdm_version >> SPDM_VERSION_NUMBER_SHIFT_BIT) > SPDM_MESSAGE_VERSION_11) { + /* Need use SPDM 1.2 signing */ + switch (req_base_asym_alg) { + case SPDM_ALGORITHMS_BASE_ASYM_ALGO_TPM_ALG_SM2_ECC_SM2_P256: + param = ""; + param_size = 0; + break; + case SPDM_ALGORITHMS_BASE_ASYM_ALGO_EDDSA_ED25519: + hash_nid = LIBSPDM_CRYPTO_NID_NULL; + break; + case SPDM_ALGORITHMS_BASE_ASYM_ALGO_EDDSA_ED448: + hash_nid = LIBSPDM_CRYPTO_NID_NULL; + param = libspdm_get_signing_context_string (spdm_version, op_code, true, ¶m_size); + break; + default: + /* pass thru for rest algorithm */ + break; + } + + libspdm_create_signing_context (spdm_version, op_code, true, + spdm12_signing_context_with_hash); + libspdm_copy_mem(&spdm12_signing_context_with_hash[SPDM_VERSION_1_2_SIGNING_CONTEXT_SIZE], + sizeof(spdm12_signing_context_with_hash) + - (&spdm12_signing_context_with_hash[SPDM_VERSION_1_2_SIGNING_CONTEXT_SIZE] + - spdm12_signing_context_with_hash), + message_hash, hash_size); + + /* assign message and message_size for signing */ + message = spdm12_signing_context_with_hash; + message_size = SPDM_VERSION_1_2_SIGNING_CONTEXT_SIZE + hash_size; + + if (need_hash) { + result = libspdm_hash_all(base_hash_algo, message, message_size, + full_message_hash); + if (!result) { + return false; + } + return libspdm_asym_sign_wrap(context, hash_nid, req_base_asym_alg, + param, param_size, + full_message_hash, hash_size, + signature, sig_size); + } else { + return libspdm_asym_sign_wrap(context, hash_nid, req_base_asym_alg, + param, param_size, + message, message_size, + signature, sig_size); + } + + /* SPDM 1.2 signing done. */ + } + + if (need_hash) { + return libspdm_asym_sign_wrap(context, hash_nid, req_base_asym_alg, + param, param_size, + message_hash, hash_size, + signature, sig_size); + } else { + LIBSPDM_ASSERT (false); + return false; + } +} diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/libraries/libspdm/2.3.1/library/spdm_crypt_lib/libspdm_crypt_cert.c nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/libraries/libspdm/2.3.1/library/spdm_crypt_lib/libspdm_crypt_cert.c --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/libraries/libspdm/2.3.1/library/spdm_crypt_lib/libspdm_crypt_cert.c 1970-01-01 00:00:00.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/libraries/libspdm/2.3.1/library/spdm_crypt_lib/libspdm_crypt_cert.c 2024-03-05 22:14:15.000000000 +0000 @@ -0,0 +1,1325 @@ +/** + * Copyright Notice: + * Copyright 2021-2022 DMTF. All rights reserved. + * License: BSD 3-Clause License. For full text see link: https://github.com/DMTF/libspdm/blob/main/LICENSE.md + **/ + +#include "internal/libspdm_crypt_lib.h" + +/**pathLenConstraint is optional. + * In https://www.pkisolutions.com/basic-constraints-certificate-extension/: + * pathLenConstraint: How many CAs are allowed in the chain below current CA certificate. + * This setting has no meaning for end entity certificates. + **/ + +/** + * leaf cert spdm extension len + * len > 2 * (spdm id-DMTF-spdm size + 2) + **/ + +#ifndef SPDM_EXTENDSION_LEN +#define SPDM_EXTENDSION_LEN 30 +#endif + +/*max public key encryption algo oid len*/ +#ifndef LIBSPDM_MAX_ENCRYPTION_ALGO_OID_LEN +#define LIBSPDM_MAX_ENCRYPTION_ALGO_OID_LEN 10 +#endif + +/*leaf cert basic constraints len,CA = false: 30 03 01 01 00*/ +#ifndef BASIC_CONSTRAINTS_CA_LEN +#define BASIC_CONSTRAINTS_CA_LEN 5 +#endif + +/** + * 0x02 is integer; + * 0x82 indicates that the length is expressed in two bytes; + * 0x01 and 0x01 are rsa key len; + **/ +#define KEY_ENCRY_ALGO_RSA2048_FLAG {0x02, 0x82, 0x01, 0x01} +#define KEY_ENCRY_ALGO_RSA3072_FLAG {0x02, 0x82, 0x01, 0x81} +#define KEY_ENCRY_ALGO_RSA4096_FLAG {0x02, 0x82, 0x02, 0x01} + +/* the other case is ASN1 code different when integer is 1 on highest position*/ +#define KEY_ENCRY_ALGO_RSA2048_FLAG_OTHER {0x02, 0x82, 0x01, 0x00} +#define KEY_ENCRY_ALGO_RSA3072_FLAG_OTHER {0x02, 0x82, 0x01, 0x80} +#define KEY_ENCRY_ALGO_RSA4096_FLAG_OTHER {0x02, 0x82, 0x02, 0x00} + +/** + * https://oidref.com/1.2.840.10045.3.1.7 + * ECC256 curve OID: 1.2.840.10045.3.1.7 + * https://oidref.com/1.3.132.0.34 + * ECC384 curve OID: 1.3.132.0.34 + * https://oidref.com/1.3.132.0.35 + * ECC521 curve OID: 1.3.132.0.35 + **/ +#define KEY_ENCRY_ALGO_ECC256_OID {0x2A, 0x86, 0x48, 0xCE, 0x3D, 0x03, 0x01, 0x07} +#define KEY_ENCRY_ALGO_ECC384_OID {0x2B, 0x81, 0x04, 0x00, 0x22} +#define KEY_ENCRY_ALGO_ECC521_OID {0x2B, 0x81, 0x04, 0x00, 0x23} + +/** + * EDxxx OID: https://datatracker.ietf.org/doc/html/rfc8420 + * ED448 OID: 1.3.101.113 + * ED25519 OID: 1.3.101.112 + **/ +#define ENCRY_ALGO_ED25519_OID {0x2B, 0x65, 0x70} +#define ENCRY_ALGO_ED448_OID {0x2B, 0x65, 0x71} + +/** + * Retrieve the asymmetric public key from one DER-encoded X509 certificate. + * + * @param cert Pointer to the DER-encoded X509 certificate. + * @param cert_size Size of the X509 certificate in bytes. + * @param context Pointer to new-generated asymmetric context which contain the retrieved public + * key component. Use libspdm_asym_free() function to free the resource. + * + * @retval true public key was retrieved successfully. + * @retval false Fail to retrieve public key from X509 certificate. + **/ +typedef bool (*libspdm_asym_get_public_key_from_x509_func)(const uint8_t *cert, + size_t cert_size, + void **context); + +/** + * Return asymmetric GET_PUBLIC_KEY_FROM_X509 function, based upon the negotiated asymmetric algorithm. + * + * @param base_asym_algo SPDM base_asym_algo + * + * @return asymmetric GET_PUBLIC_KEY_FROM_X509 function + **/ +libspdm_asym_get_public_key_from_x509_func +static libspdm_get_asym_get_public_key_from_x509(uint32_t base_asym_algo) +{ + switch (base_asym_algo) { + case SPDM_ALGORITHMS_BASE_ASYM_ALGO_TPM_ALG_RSASSA_2048: + case SPDM_ALGORITHMS_BASE_ASYM_ALGO_TPM_ALG_RSASSA_3072: + case SPDM_ALGORITHMS_BASE_ASYM_ALGO_TPM_ALG_RSASSA_4096: + case SPDM_ALGORITHMS_BASE_ASYM_ALGO_TPM_ALG_RSAPSS_2048: + case SPDM_ALGORITHMS_BASE_ASYM_ALGO_TPM_ALG_RSAPSS_3072: + case SPDM_ALGORITHMS_BASE_ASYM_ALGO_TPM_ALG_RSAPSS_4096: +#if (LIBSPDM_RSA_SSA_SUPPORT) || (LIBSPDM_RSA_PSS_SUPPORT) + return libspdm_rsa_get_public_key_from_x509; +#else + LIBSPDM_ASSERT(false); + break; +#endif + case SPDM_ALGORITHMS_BASE_ASYM_ALGO_TPM_ALG_ECDSA_ECC_NIST_P256: + case SPDM_ALGORITHMS_BASE_ASYM_ALGO_TPM_ALG_ECDSA_ECC_NIST_P384: + case SPDM_ALGORITHMS_BASE_ASYM_ALGO_TPM_ALG_ECDSA_ECC_NIST_P521: +#if LIBSPDM_ECDSA_SUPPORT + return libspdm_ec_get_public_key_from_x509; +#else + LIBSPDM_ASSERT(false); + break; +#endif + case SPDM_ALGORITHMS_BASE_ASYM_ALGO_EDDSA_ED25519: + case SPDM_ALGORITHMS_BASE_ASYM_ALGO_EDDSA_ED448: +#if (LIBSPDM_EDDSA_ED25519_SUPPORT) || (LIBSPDM_EDDSA_ED448_SUPPORT) + return libspdm_ecd_get_public_key_from_x509; +#else + LIBSPDM_ASSERT(false); + break; +#endif + case SPDM_ALGORITHMS_BASE_ASYM_ALGO_TPM_ALG_SM2_ECC_SM2_P256: +#if LIBSPDM_SM2_DSA_SUPPORT + return libspdm_sm2_get_public_key_from_x509; +#else + LIBSPDM_ASSERT(false); + break; +#endif + default: + LIBSPDM_ASSERT(false); + break; + } + + return NULL; +} + +/** + * Retrieve the asymmetric public key from one DER-encoded X509 certificate, + * based upon negotiated asymmetric algorithm. + * + * @param base_asym_algo SPDM base_asym_algo + * @param cert Pointer to the DER-encoded X509 certificate. + * @param cert_size size of the X509 certificate in bytes. + * @param context Pointer to new-generated asymmetric context which contain the retrieved public key component. + * Use libspdm_asym_free() function to free the resource. + * + * @retval true public key was retrieved successfully. + * @retval false Fail to retrieve public key from X509 certificate. + **/ +bool libspdm_asym_get_public_key_from_x509(uint32_t base_asym_algo, + const uint8_t *cert, + size_t cert_size, + void **context) +{ + libspdm_asym_get_public_key_from_x509_func get_public_key_from_x509_function; + get_public_key_from_x509_function = libspdm_get_asym_get_public_key_from_x509(base_asym_algo); + if (get_public_key_from_x509_function == NULL) { + return false; + } + return get_public_key_from_x509_function(cert, cert_size, context); +} + +/** + * Return requester asymmetric GET_PUBLIC_KEY_FROM_X509 function, based upon the negotiated requester asymmetric algorithm. + * + * @param req_base_asym_alg SPDM req_base_asym_alg + * + * @return requester asymmetric GET_PUBLIC_KEY_FROM_X509 function + **/ +static libspdm_asym_get_public_key_from_x509_func +libspdm_get_req_asym_get_public_key_from_x509(uint16_t req_base_asym_alg) +{ + return libspdm_get_asym_get_public_key_from_x509(req_base_asym_alg); +} + +/** + * Retrieve the asymmetric public key from one DER-encoded X509 certificate, + * based upon negotiated requester asymmetric algorithm. + * + * @param req_base_asym_alg SPDM req_base_asym_alg + * @param cert Pointer to the DER-encoded X509 certificate. + * @param cert_size size of the X509 certificate in bytes. + * @param context Pointer to new-generated asymmetric context which contain the retrieved public key component. + * Use libspdm_asym_free() function to free the resource. + * + * @retval true public key was retrieved successfully. + * @retval false Fail to retrieve public key from X509 certificate. + **/ +bool libspdm_req_asym_get_public_key_from_x509(uint16_t req_base_asym_alg, + const uint8_t *cert, + size_t cert_size, + void **context) +{ + libspdm_asym_get_public_key_from_x509_func get_public_key_from_x509_function; + get_public_key_from_x509_function = + libspdm_get_req_asym_get_public_key_from_x509(req_base_asym_alg); + if (get_public_key_from_x509_function == NULL) { + return false; + } + return get_public_key_from_x509_function(cert, cert_size, context); +} + +/** + * Check the X509 DataTime is within a valid range. + * + * @param spdm_context A pointer to the SPDM context. + * @param from notBefore Pointer to date_time object. + * @param from_size notBefore date_time object size. + * @param to notAfter Pointer to date_time object. + * @param to_size notAfter date_time object size. + * + * @retval true verification pass. + * @retval false verification fail. + **/ +static bool libspdm_internal_x509_date_time_check(const uint8_t *from, + size_t from_size, + const uint8_t *to, + size_t to_size) +{ + int32_t ret; + bool status; + uint8_t f0[64]; + uint8_t t0[64]; + size_t f0_size; + size_t t0_size; + + f0_size = 64; + t0_size = 64; + + status = libspdm_x509_set_date_time("19700101000000Z", f0, &f0_size); + if (!status) { + return false; + } + + status = libspdm_x509_set_date_time("99991231235959Z", t0, &t0_size); + if (!status) { + return false; + } + + /* from >= f0*/ + ret = libspdm_x509_compare_date_time(from, f0); + if (ret < 0) { + return false; + } + + /* to <= t0*/ + ret = libspdm_x509_compare_date_time(t0, to); + if (ret < 0) { + return false; + } + + return true; +} + +/** + * This function returns the SPDM public key encryption algorithm OID len. + * + * @param[in] base_asym_algo SPDM base_asym_algo + * + * @return SPDM public key encryption algorithms OID len. + **/ +static uint32_t libspdm_get_public_key_algo_OID_len(uint32_t base_asym_algo) +{ + switch (base_asym_algo) { + case SPDM_ALGORITHMS_BASE_ASYM_ALGO_TPM_ALG_RSASSA_2048: + case SPDM_ALGORITHMS_BASE_ASYM_ALGO_TPM_ALG_RSAPSS_2048: + case SPDM_ALGORITHMS_BASE_ASYM_ALGO_TPM_ALG_RSASSA_3072: + case SPDM_ALGORITHMS_BASE_ASYM_ALGO_TPM_ALG_RSAPSS_3072: + case SPDM_ALGORITHMS_BASE_ASYM_ALGO_TPM_ALG_RSASSA_4096: + case SPDM_ALGORITHMS_BASE_ASYM_ALGO_TPM_ALG_RSAPSS_4096: + return 4; + case SPDM_ALGORITHMS_BASE_ASYM_ALGO_TPM_ALG_ECDSA_ECC_NIST_P256: + return 8; + case SPDM_ALGORITHMS_BASE_ASYM_ALGO_TPM_ALG_ECDSA_ECC_NIST_P384: + case SPDM_ALGORITHMS_BASE_ASYM_ALGO_TPM_ALG_ECDSA_ECC_NIST_P521: + return 5; + case SPDM_ALGORITHMS_BASE_ASYM_ALGO_EDDSA_ED25519: + case SPDM_ALGORITHMS_BASE_ASYM_ALGO_EDDSA_ED448: + return 3; + default: + LIBSPDM_ASSERT(false); + return false; + } +} + +/** + * This function get the SPDM public key encryption algorithm OID. + * + * @param[in] base_asym_algo SPDM base_asym_algo + * @param[in,out] oid SPDM public key encryption algorithm OID + * @param[in,out] oid_other Other SPDM public key encryption algorithm OID + * because of ASN1 code for integer + * + * @retval true get OID sucessful. + * @retval false get OID fail. + **/ +static bool libspdm_get_public_key_algo_OID(uint32_t base_asym_algo, uint8_t *oid, + uint8_t *oid_other) +{ + uint32_t oid_len; + oid_len = libspdm_get_public_key_algo_OID_len(base_asym_algo); + + switch (base_asym_algo) { + case SPDM_ALGORITHMS_BASE_ASYM_ALGO_TPM_ALG_RSASSA_2048: + case SPDM_ALGORITHMS_BASE_ASYM_ALGO_TPM_ALG_RSAPSS_2048: { + uint8_t encry_algo_oid_rsa2048[] = KEY_ENCRY_ALGO_RSA2048_FLAG; + uint8_t encry_algo_oid_rsa2048_ohter[] = KEY_ENCRY_ALGO_RSA2048_FLAG_OTHER; + libspdm_copy_mem(oid, oid_len, encry_algo_oid_rsa2048, oid_len); + libspdm_copy_mem(oid_other, oid_len, encry_algo_oid_rsa2048_ohter, oid_len); + break; + } + case SPDM_ALGORITHMS_BASE_ASYM_ALGO_TPM_ALG_RSASSA_3072: + case SPDM_ALGORITHMS_BASE_ASYM_ALGO_TPM_ALG_RSAPSS_3072: { + uint8_t encry_algo_oid_rsa3072[] = KEY_ENCRY_ALGO_RSA3072_FLAG; + uint8_t encry_algo_oid_rsa3072_ohter[] = KEY_ENCRY_ALGO_RSA3072_FLAG_OTHER; + libspdm_copy_mem(oid, oid_len, encry_algo_oid_rsa3072, oid_len); + libspdm_copy_mem(oid_other, oid_len, encry_algo_oid_rsa3072_ohter, oid_len); + break; + } + case SPDM_ALGORITHMS_BASE_ASYM_ALGO_TPM_ALG_RSASSA_4096: + case SPDM_ALGORITHMS_BASE_ASYM_ALGO_TPM_ALG_RSAPSS_4096: { + uint8_t encry_algo_oid_rsa4096[] = KEY_ENCRY_ALGO_RSA4096_FLAG; + uint8_t encry_algo_oid_rsa4096_ohter[] = KEY_ENCRY_ALGO_RSA4096_FLAG_OTHER; + libspdm_copy_mem(oid, oid_len, encry_algo_oid_rsa4096, oid_len); + libspdm_copy_mem(oid_other, oid_len, encry_algo_oid_rsa4096_ohter, oid_len); + break; + } + + case SPDM_ALGORITHMS_BASE_ASYM_ALGO_TPM_ALG_ECDSA_ECC_NIST_P256: { + uint8_t encry_algo_oid_ecc256[] = KEY_ENCRY_ALGO_ECC256_OID; + libspdm_copy_mem(oid, oid_len, encry_algo_oid_ecc256, oid_len); + break; + } + case SPDM_ALGORITHMS_BASE_ASYM_ALGO_TPM_ALG_ECDSA_ECC_NIST_P384: { + uint8_t encry_algo_oid_ecc384[] = KEY_ENCRY_ALGO_ECC384_OID; + libspdm_copy_mem(oid, oid_len, encry_algo_oid_ecc384, oid_len); + break; + } + case SPDM_ALGORITHMS_BASE_ASYM_ALGO_TPM_ALG_ECDSA_ECC_NIST_P521: { + uint8_t encry_algo_oid_ecc521[] = KEY_ENCRY_ALGO_ECC521_OID; + libspdm_copy_mem(oid, oid_len, encry_algo_oid_ecc521, oid_len); + break; + } + + /*sm2 oid TBD*/ + case SPDM_ALGORITHMS_BASE_ASYM_ALGO_TPM_ALG_SM2_ECC_SM2_P256: + return true; + + case SPDM_ALGORITHMS_BASE_ASYM_ALGO_EDDSA_ED25519: { + uint8_t encry_algo_oid_ed25519[] = ENCRY_ALGO_ED25519_OID; + libspdm_copy_mem(oid, oid_len, encry_algo_oid_ed25519, oid_len); + break; + } + case SPDM_ALGORITHMS_BASE_ASYM_ALGO_EDDSA_ED448: { + uint8_t encry_algo_oid_ed448[] = ENCRY_ALGO_ED448_OID; + libspdm_copy_mem(oid, oid_len, encry_algo_oid_ed448, oid_len); + break; + } + + default: + LIBSPDM_ASSERT(false); + return false; + } + + return true; +} + +/** + * Verify cert public key encryption algorithm is matched to negotiated base_aysm algo + * + * @param[in] cert Pointer to the DER-encoded certificate data. + * @param[in] cert_size The size of certificate data in bytes. + * @param[in] base_asym_algo SPDM base_asym_algo + * @param[out] oid cert public key encryption algorithm OID + * @param[in] oid_size the buffer size for required OID + * + * @retval true get public key oid from cert successfully + * @retval false get public key oid from cert fail + **/ +static bool libspdm_get_public_key_oid(const uint8_t *cert, size_t cert_size, + uint8_t *oid, size_t oid_size, uint32_t base_asym_algo) +{ + bool ret; + uint8_t *ptr; + int32_t length; + size_t obj_len; + uint8_t *end; + uint8_t index; + uint8_t sequence_time; + + length = (int32_t)cert_size; + ptr = (uint8_t*)(size_t)cert; + obj_len = 0; + end = ptr + length; + ret = true; + + /* TBSCertificate have 5 sequence before subjectPublicKeyInfo*/ + sequence_time = 5; + + /*all cert sequence*/ + ret = libspdm_asn1_get_tag(&ptr, end, &obj_len, + LIBSPDM_CRYPTO_ASN1_SEQUENCE | LIBSPDM_CRYPTO_ASN1_CONSTRUCTED); + if (!ret) { + return false; + } + + /*TBSCertificate sequence*/ + ret = libspdm_asn1_get_tag(&ptr, end, &obj_len, + LIBSPDM_CRYPTO_ASN1_SEQUENCE | LIBSPDM_CRYPTO_ASN1_CONSTRUCTED); + if (!ret) { + return false; + } + + end = ptr + obj_len; + /*version*/ + ret = libspdm_asn1_get_tag(&ptr, end, &obj_len, + LIBSPDM_CRYPTO_ASN1_CONTEXT_SPECIFIC | + LIBSPDM_CRYPTO_ASN1_CONSTRUCTED); + if (!ret) { + return false; + } + + ptr += obj_len; + /*serialNumber*/ + ret = libspdm_asn1_get_tag(&ptr, end, &obj_len, LIBSPDM_CRYPTO_ASN1_INTEGER); + if (!ret) { + return false; + } + + /** + * signature AlgorithmIdentifier, + * issuer Name, + * validity Validity, + * subject Name, + * subjectPublicKeyInfo + **/ + for (index = 0; index < sequence_time; index++) { + ptr += obj_len; + ret = libspdm_asn1_get_tag(&ptr, end, &obj_len, + LIBSPDM_CRYPTO_ASN1_SEQUENCE | LIBSPDM_CRYPTO_ASN1_CONSTRUCTED); + if (!ret) { + return false; + } + } + + switch (base_asym_algo) + { + case SPDM_ALGORITHMS_BASE_ASYM_ALGO_TPM_ALG_RSASSA_2048: + case SPDM_ALGORITHMS_BASE_ASYM_ALGO_TPM_ALG_RSAPSS_2048: + case SPDM_ALGORITHMS_BASE_ASYM_ALGO_TPM_ALG_RSASSA_3072: + case SPDM_ALGORITHMS_BASE_ASYM_ALGO_TPM_ALG_RSAPSS_3072: + case SPDM_ALGORITHMS_BASE_ASYM_ALGO_TPM_ALG_RSASSA_4096: + case SPDM_ALGORITHMS_BASE_ASYM_ALGO_TPM_ALG_RSAPSS_4096: + ret = libspdm_asn1_get_tag(&ptr, end, &obj_len, + LIBSPDM_CRYPTO_ASN1_SEQUENCE | LIBSPDM_CRYPTO_ASN1_CONSTRUCTED); + if (!ret) { + return false; + } + + ptr += obj_len; + ret = libspdm_asn1_get_tag(&ptr, end, &obj_len, LIBSPDM_CRYPTO_ASN1_BIT_STRING); + if (!ret) { + return false; + } + + /*get rsa key len*/ + ptr++; + ret = libspdm_asn1_get_tag(&ptr, end, &obj_len, + LIBSPDM_CRYPTO_ASN1_SEQUENCE | LIBSPDM_CRYPTO_ASN1_CONSTRUCTED); + if (!ret) { + return false; + } + libspdm_copy_mem(oid, oid_size, ptr, oid_size); + break; + case SPDM_ALGORITHMS_BASE_ASYM_ALGO_TPM_ALG_ECDSA_ECC_NIST_P256: + case SPDM_ALGORITHMS_BASE_ASYM_ALGO_TPM_ALG_ECDSA_ECC_NIST_P384: + case SPDM_ALGORITHMS_BASE_ASYM_ALGO_TPM_ALG_ECDSA_ECC_NIST_P521: + ret = libspdm_asn1_get_tag(&ptr, end, &obj_len, + LIBSPDM_CRYPTO_ASN1_SEQUENCE | LIBSPDM_CRYPTO_ASN1_CONSTRUCTED); + if (!ret) { + return false; + } + ret = libspdm_asn1_get_tag(&ptr, end, &obj_len, LIBSPDM_CRYPTO_ASN1_OID); + if (!ret) { + return false; + } + + /*get ecc second oid*/ + ptr +=obj_len; + ret = libspdm_asn1_get_tag(&ptr, end, &obj_len, LIBSPDM_CRYPTO_ASN1_OID); + if (!ret) { + return false; + } + + if (oid_size != obj_len) { + return false; + } + + libspdm_copy_mem(oid, oid_size, ptr, obj_len); + break; + case SPDM_ALGORITHMS_BASE_ASYM_ALGO_EDDSA_ED25519: + case SPDM_ALGORITHMS_BASE_ASYM_ALGO_EDDSA_ED448: + ret = libspdm_asn1_get_tag(&ptr, end, &obj_len, + LIBSPDM_CRYPTO_ASN1_SEQUENCE | LIBSPDM_CRYPTO_ASN1_CONSTRUCTED); + if (!ret) { + return false; + } + + /*get eddsa oid*/ + ret = libspdm_asn1_get_tag(&ptr, end, &obj_len, LIBSPDM_CRYPTO_ASN1_OID); + if (!ret) { + return false; + } + + if (oid_size != obj_len) { + return false; + } + + libspdm_copy_mem(oid, oid_size, ptr, obj_len); + break; + default: + LIBSPDM_ASSERT(false); + return false; + } + + return true; +} + +/** + * Verify cert public key encryption algorithm is matched to negotiated base_aysm algo + * + * @param[in] cert Pointer to the DER-encoded certificate data. + * @param[in] cert_size The size of certificate data in bytes. + * @param[in] base_asym_algo SPDM base_asym_algo + * + * @retval true verify pass + * @retval false verify fail + **/ +static bool libspdm_verify_cert_subject_public_key_info(const uint8_t *cert, size_t cert_size, + uint32_t base_asym_algo) +{ + size_t oid_len; + bool status; + + /*public key encrypt algo OID from cert*/ + uint8_t cert_public_key_crypt_algo_oid[LIBSPDM_MAX_ENCRYPTION_ALGO_OID_LEN]; + /*public key encrypt algo OID from libspdm stored*/ + uint8_t libspdm_public_key_crypt_algo_oid[LIBSPDM_MAX_ENCRYPTION_ALGO_OID_LEN]; + uint8_t libspdm_public_key_crypt_algo_oid_other[LIBSPDM_MAX_ENCRYPTION_ALGO_OID_LEN]; + + libspdm_zero_mem(libspdm_public_key_crypt_algo_oid, LIBSPDM_MAX_ENCRYPTION_ALGO_OID_LEN); + libspdm_zero_mem(libspdm_public_key_crypt_algo_oid_other, LIBSPDM_MAX_ENCRYPTION_ALGO_OID_LEN); + + /*work around: skip the sm2*/ + if (base_asym_algo == SPDM_ALGORITHMS_BASE_ASYM_ALGO_TPM_ALG_SM2_ECC_SM2_P256) { + return true; + } + + oid_len = libspdm_get_public_key_algo_OID_len(base_asym_algo); + if(oid_len == 0) { + return false; + } + /*get public key encrypt algo OID from libspdm stored*/ + status = libspdm_get_public_key_algo_OID(base_asym_algo, + libspdm_public_key_crypt_algo_oid, + libspdm_public_key_crypt_algo_oid_other); + if (!status) { + return status; + } + + /*get public key encrypt algo OID from cert*/ + status = libspdm_get_public_key_oid(cert, cert_size, cert_public_key_crypt_algo_oid, oid_len, + base_asym_algo); + if (!status || (libspdm_const_compare_mem(cert_public_key_crypt_algo_oid, + libspdm_public_key_crypt_algo_oid, oid_len) && + libspdm_const_compare_mem(cert_public_key_crypt_algo_oid, + libspdm_public_key_crypt_algo_oid_other, oid_len))) { + return false; + } + + return status; +} + +/** + * Verify leaf cert basic_constraints CA is false + * + * @param[in] cert Pointer to the DER-encoded certificate data. + * @param[in] cert_size The size of certificate data in bytes. + * + * @retval true verify pass,two case: 1.basic constraints is not present in cert; + * 2. cert basic_constraints CA is false; + * @retval false verify fail + **/ +static bool libspdm_verify_leaf_cert_basic_constraints(const uint8_t *cert, size_t cert_size) +{ + bool status; + /*basic_constraints from cert*/ + uint8_t cert_basic_constraints[BASIC_CONSTRAINTS_CA_LEN]; + size_t len; + + /*leaf cert basic_constraints case1: CA: false and CA object is excluded */ + #define BASIC_CONSTRAINTS_STRING_CASE1 {0x30, 0x00} + uint8_t basic_constraints_case1[] = BASIC_CONSTRAINTS_STRING_CASE1; + + /*leaf cert basic_constraints case2: CA: false */ + #define BASIC_CONSTRAINTS_STRING_CASE2 {0x30, 0x03, 0x01, 0x01, 0x00} + uint8_t basic_constraints_case2[] = BASIC_CONSTRAINTS_STRING_CASE2; + + len = BASIC_CONSTRAINTS_CA_LEN; + + status = libspdm_x509_get_extended_basic_constraints(cert, cert_size, + cert_basic_constraints, &len); + + if (len == 0) { + /* basic constraints is not present in cert */ + return true; + } else if (!status ) { + return false; + } + + if ((len == sizeof(basic_constraints_case1)) && + (!libspdm_const_compare_mem(cert_basic_constraints, + basic_constraints_case1, + sizeof(basic_constraints_case1)))) { + return true; + } + + if ((len == sizeof(basic_constraints_case2)) && + (!libspdm_const_compare_mem(cert_basic_constraints, + basic_constraints_case2, + sizeof(basic_constraints_case2)))) { + return true; + } + + return false; +} + +/** + * Verify leaf cert extend spdm OID + * + * @param[in] cert Pointer to the DER-encoded certificate data. + * @param[in] cert_size The size of certificate data in bytes. + * + * @retval true verify pass + * @retval false verify fail,two case: 1. return is not RETURN_SUCCESS or RETURN_NOT_FOUND; + * 2. hardware_identity_oid is found in AliasCert model; + **/ +static bool libspdm_verify_leaf_cert_eku_spdm_OID(const uint8_t *cert, size_t cert_size, + bool is_device_cert_model) +{ + bool status; + bool find_sucessful; + uint8_t spdm_extension[SPDM_EXTENDSION_LEN]; + size_t index; + size_t len; + + /* SPDM defined OID */ + + uint8_t oid_spdm_extension[] = SPDM_OID_EXTENSION; + uint8_t hardware_identity_oid[] = SPDM_OID_HARDWARE_IDENTITY; + + len = SPDM_EXTENDSION_LEN; + + if (cert == NULL || cert_size == 0) { + return false; + } + + status = libspdm_x509_get_extension_data(cert, cert_size, + (const uint8_t *)oid_spdm_extension, + sizeof(oid_spdm_extension), + spdm_extension, + &len); + + if(len == 0) { + return true; + } else if(!status) { + return false; + } + + /*find the spdm hardware identity OID*/ + find_sucessful = false; + for(index = 0; index <= len - sizeof(hardware_identity_oid); index++) { + if (!libspdm_const_compare_mem(spdm_extension + index, hardware_identity_oid, + sizeof(hardware_identity_oid))) { + find_sucessful = true; + break; + } + } + + if ((find_sucessful) && (!is_device_cert_model)) { + /* Hardware_identity_OID is found in alias cert model */ + return false; + } else { + return true; + } +} + +/** + * Certificate Check for SPDM leaf cert. + * + * @param[in] cert Pointer to the DER-encoded certificate data. + * @param[in] cert_size The size of certificate data in bytes. + * @param[in] base_asym_algo SPDM base_asym_algo + * @param[in] base_hash_algo SPDM base_hash_algo + * @param[in] is_device_cert_model If true, the cert chain is DeviceCert model; + * If false, the cert chain is AliasCert model; + * + * @retval true Success. + * @retval false Certificate is not valid + **/ +bool libspdm_x509_certificate_check(const uint8_t *cert, size_t cert_size, + uint32_t base_asym_algo, + uint32_t base_hash_algo, + bool is_device_cert_model) +{ + uint8_t end_cert_from[64]; + size_t end_cert_from_len; + uint8_t end_cert_to[64]; + size_t end_cert_to_len; + size_t asn1_buffer_len; + bool status; + size_t cert_version; + size_t value; + void *context; + + if (cert == NULL || cert_size == 0) { + return false; + } + + status = true; + context = NULL; + end_cert_from_len = 64; + end_cert_to_len = 64; + + /* 1. version*/ + cert_version = 0; + status = libspdm_x509_get_version(cert, cert_size, &cert_version); + if (!status) { + goto cleanup; + } + if (cert_version != 2) { + status = false; + goto cleanup; + } + + /* 2. serial_number*/ + asn1_buffer_len = 0; + status = libspdm_x509_get_serial_number(cert, cert_size, NULL, &asn1_buffer_len); + if (asn1_buffer_len == 0) { + status = false; + goto cleanup; + } + + /* 3. Verify public key algorithm. */ + status = libspdm_verify_cert_subject_public_key_info(cert, cert_size, base_asym_algo); + if (!status) { + goto cleanup; + } + + /* 4. issuer_name*/ + asn1_buffer_len = 0; + status = libspdm_x509_get_issuer_name(cert, cert_size, NULL, &asn1_buffer_len); + if (asn1_buffer_len == 0) { + status = false; + goto cleanup; + } + + /* 5. subject_name*/ + asn1_buffer_len = 0; + status = libspdm_x509_get_subject_name(cert, cert_size, NULL, &asn1_buffer_len); + if (asn1_buffer_len == 0) { + status = false; + goto cleanup; + } + + /* 6. validaity*/ + status = libspdm_x509_get_validity(cert, cert_size, end_cert_from, + &end_cert_from_len, end_cert_to, + &end_cert_to_len); + if (!status) { + goto cleanup; + } + + status = libspdm_internal_x509_date_time_check( + end_cert_from, end_cert_from_len, end_cert_to, end_cert_to_len); + if (!status) { + goto cleanup; + } + + /* 7. subject_public_key*/ + status = libspdm_asym_get_public_key_from_x509(base_asym_algo, cert, cert_size, &context); + if (!status) { + goto cleanup; + } + + /* 8. key_usage*/ + value = 0; + status = libspdm_x509_get_key_usage(cert, cert_size, &value); + if (!status) { + goto cleanup; + } + if (LIBSPDM_CRYPTO_X509_KU_DIGITAL_SIGNATURE & value) { + status = true; + } else { + status = false; + goto cleanup; + } + + /* 9. verify SPDM extension OID*/ + status = libspdm_verify_leaf_cert_eku_spdm_OID(cert, cert_size, is_device_cert_model); + if (!status) { + goto cleanup; + } + + /* 10. verify basic constraints*/ + status = libspdm_verify_leaf_cert_basic_constraints(cert, cert_size); + if (!status) { + goto cleanup; + } + + /* 11. extended_key_usage*/ + value = 0; + status = libspdm_x509_get_extended_key_usage(cert, cert_size, NULL, &value); + if (value == 0) { + status = false; + goto cleanup; + } + status = true; + +cleanup: + libspdm_asym_free(base_asym_algo, context); + return status; +} + +/** + * Return certificate is root cert or not. + * Certificate is considered as a root certificate if the subjectname equal issuername. + * + * @param[in] cert Pointer to the DER-encoded certificate data. + * @param[in] cert_size The size of certificate data in bytes. + * + * @retval true Certificate is self-signed. + * @retval false Certificate is not self-signed. + **/ +bool libspdm_is_root_certificate(const uint8_t *cert, size_t cert_size) +{ + uint8_t issuer_name[LIBSPDM_MAX_MESSAGE_SMALL_BUFFER_SIZE]; + size_t issuer_name_len; + uint8_t subject_name[LIBSPDM_MAX_MESSAGE_SMALL_BUFFER_SIZE]; + size_t subject_name_len; + bool result; + + if (cert == NULL || cert_size == 0) { + return false; + } + + /* 1. issuer_name*/ + issuer_name_len = LIBSPDM_MAX_MESSAGE_SMALL_BUFFER_SIZE; + result = libspdm_x509_get_issuer_name(cert, cert_size, issuer_name, &issuer_name_len); + if (!result) { + return false; + } + + /* 2. subject_name*/ + subject_name_len = LIBSPDM_MAX_MESSAGE_SMALL_BUFFER_SIZE; + result = libspdm_x509_get_subject_name(cert, cert_size, subject_name, &subject_name_len); + if (!result) { + return false; + } + + if (issuer_name_len != subject_name_len) { + return false; + } + if (libspdm_const_compare_mem(issuer_name, subject_name, issuer_name_len) != 0) { + return false; + } + + return true; +} + +/** + * Retrieve the SubjectAltName from SubjectAltName Bytes. + * + * @param[in] buffer Pointer to subjectAltName oct bytes. + * @param[in] len size of buffer in bytes. + * @param[out] name_buffer buffer to contain the retrieved certificate + * SubjectAltName. At most name_buffer_size bytes will be + * written. Maybe NULL in order to determine the size + * buffer needed. + * @param[in,out] name_buffer_size The size in bytes of the name buffer on input, + * and the size of buffer returned name on output. + * If name_buffer is NULL then the amount of space needed + * in buffer (including the final null) is returned. + * @param[out] oid OID of otherName + * @param[in,out] oid_size the buffersize for required OID + * + * @retval true get the subjectAltName string successfully + * @retval failed get the subjectAltName string failed + **/ +bool libspdm_get_dmtf_subject_alt_name_from_bytes( + uint8_t *buffer, const size_t len, char *name_buffer, + size_t *name_buffer_size, uint8_t *oid, + size_t *oid_size) +{ + uint8_t *ptr; + int32_t length; + size_t obj_len; + int32_t ret; + + /*copy mem variable*/ + volatile uint8_t* dst; + const volatile uint8_t* src; + size_t dst_len; + size_t src_len; + + length = (int32_t)len; + ptr = buffer; + obj_len = 0; + + /* Sequence*/ + ret = libspdm_asn1_get_tag(&ptr, ptr + length, &obj_len, + LIBSPDM_CRYPTO_ASN1_SEQUENCE | LIBSPDM_CRYPTO_ASN1_CONSTRUCTED); + if (!ret) { + return false; + } + + ret = libspdm_asn1_get_tag(&ptr, ptr + obj_len, &obj_len, + LIBSPDM_CRYPTO_ASN1_CONTEXT_SPECIFIC | + LIBSPDM_CRYPTO_ASN1_CONSTRUCTED); + + ret = libspdm_asn1_get_tag(&ptr, ptr + obj_len, &obj_len, LIBSPDM_CRYPTO_ASN1_OID); + if (!ret) { + return false; + } + /* CopyData to OID*/ + if (*oid_size < (size_t)obj_len) { + *oid_size = (size_t)obj_len; + return false; + } + if (oid != NULL) { + libspdm_copy_mem(oid, *oid_size, ptr, obj_len); + *oid_size = obj_len; + } + + /* Move to next element*/ + ptr += obj_len; + + ret = libspdm_asn1_get_tag(&ptr, (uint8_t *)(buffer + length), &obj_len, + LIBSPDM_CRYPTO_ASN1_CONTEXT_SPECIFIC | + LIBSPDM_CRYPTO_ASN1_CONSTRUCTED); + ret = libspdm_asn1_get_tag(&ptr, (uint8_t *)(buffer + length), &obj_len, + LIBSPDM_CRYPTO_ASN1_UTF8_STRING); + if (!ret) { + return false; + } + + if (*name_buffer_size < (size_t)obj_len + 1) { + *name_buffer_size = (size_t)obj_len + 1; + return false; + } + + /* the src and dst adress are overlap, + * When the function is called by libspdm_get_dmtf_subject_alt_name. + * libspdm_copy_mem can not be uesed */ + if ((name_buffer != NULL) && (ptr != NULL)) { + dst = (volatile uint8_t*) name_buffer; + src = (const volatile uint8_t*) ptr; + dst_len = *name_buffer_size; + src_len = obj_len; + + /* Check for case where "dst_len" may be invalid. Do not zero "dst" in this case. */ + if (dst_len > (SIZE_MAX >> 1)) { + LIBSPDM_ASSERT(0); + return false; + } + + /* Guard against invalid lengths. Zero "dst" in these cases. */ + if (src_len > dst_len || + src_len > (SIZE_MAX >> 1)) { + libspdm_zero_mem(name_buffer, dst_len); + LIBSPDM_ASSERT(0); + return false; + } + + while (src_len-- != 0) { + *(dst++) = *(src++); + } + + /*encode name buffer to string*/ + *name_buffer_size = obj_len + 1; + name_buffer[obj_len] = 0; + return true; + } + + return false; +} + +/** + * Retrieve the SubjectAltName from one X.509 certificate. + * + * @param[in] cert Pointer to the DER-encoded X509 certificate. + * @param[in] cert_size size of the X509 certificate in bytes. + * @param[out] name_buffer buffer to contain the retrieved certificate + * SubjectAltName. At most name_buffer_size bytes will be + * written. Maybe NULL in order to determine the size + * buffer needed. + * @param[in,out] name_buffer_size The size in bytes of the name buffer on input, + * and the size of buffer returned name on output. + * If name_buffer is NULL then the amount of space needed + * in buffer (including the final null) is returned. + * @param[out] oid OID of otherName + * @param[in,out] oid_size the buffersize for required OID + * + * @retval true get the subjectAltName string successfully + * @retval failed get the subjectAltName string failed + **/ +bool libspdm_get_dmtf_subject_alt_name(const uint8_t *cert, const size_t cert_size, + char *name_buffer, + size_t *name_buffer_size, + uint8_t *oid, size_t *oid_size) +{ + bool status; + size_t extension_data_size; + uint8_t oid_subject_alt_name[] = { 0x55, 0x1D, 0x11 }; + + extension_data_size = 0; + status = libspdm_x509_get_extension_data(cert, cert_size, + oid_subject_alt_name, + sizeof(oid_subject_alt_name), NULL, + &extension_data_size); + if (status || (extension_data_size == 0)) { + *name_buffer_size = 0; + return false; + } + if (extension_data_size > *name_buffer_size) { + *name_buffer_size = extension_data_size; + return false; + } + status = + libspdm_x509_get_extension_data(cert, cert_size, + oid_subject_alt_name, + sizeof(oid_subject_alt_name), + (uint8_t *)name_buffer, name_buffer_size); + if (!status) { + return status; + } + + return libspdm_get_dmtf_subject_alt_name_from_bytes( + (uint8_t *)name_buffer, *name_buffer_size, name_buffer, + name_buffer_size, oid, oid_size); +} + +/** + * This function verifies the integrity of certificate chain data without spdm_cert_chain_t header. + * + * @param cert_chain_data The certificate chain data without spdm_cert_chain_t header. + * @param cert_chain_data_size size in bytes of the certificate chain data. + * @param base_hash_algo SPDM base_hash_algo + * @param base_asym_algo SPDM base_asym_algo + * @param is_device_cert_model If true, the cert chain is DeviceCert model; + * If false, the cert chain is AliasCert model; + * + * @retval true certificate chain data integrity verification pass. + * @retval false certificate chain data integrity verification fail. + **/ +bool libspdm_verify_cert_chain_data(uint8_t *cert_chain_data, size_t cert_chain_data_size, + uint32_t base_asym_algo, uint32_t base_hash_algo, + bool is_device_cert_model) +{ + const uint8_t *root_cert_buffer; + size_t root_cert_buffer_size; + const uint8_t *leaf_cert_buffer; + size_t leaf_cert_buffer_size; + + if (cert_chain_data_size > + 0xFFFF - (sizeof(spdm_cert_chain_t) + LIBSPDM_MAX_HASH_SIZE)) { + LIBSPDM_DEBUG((LIBSPDM_DEBUG_INFO, + "!!! VerifyCertificateChainData - FAIL (chain size too large) !!!\n")); + return false; + } + + if (!libspdm_x509_get_cert_from_cert_chain( + cert_chain_data, cert_chain_data_size, 0, &root_cert_buffer, + &root_cert_buffer_size)) { + LIBSPDM_DEBUG((LIBSPDM_DEBUG_INFO, + "!!! VerifyCertificateChainData - FAIL (get root certificate failed)!!!\n")); + return false; + } + + if (!libspdm_x509_verify_cert_chain(root_cert_buffer, root_cert_buffer_size, + cert_chain_data, cert_chain_data_size)) { + LIBSPDM_DEBUG((LIBSPDM_DEBUG_INFO, + "!!! VerifyCertificateChainData - FAIL (cert chain verify failed)!!!\n")); + return false; + } + + if (!libspdm_x509_get_cert_from_cert_chain( + cert_chain_data, cert_chain_data_size, -1, + &leaf_cert_buffer, &leaf_cert_buffer_size)) { + LIBSPDM_DEBUG((LIBSPDM_DEBUG_INFO, + "!!! VerifyCertificateChainData - FAIL (get leaf certificate failed)!!!\n")); + return false; + } + + if (!libspdm_x509_certificate_check(leaf_cert_buffer, leaf_cert_buffer_size, + base_asym_algo, base_hash_algo, + is_device_cert_model)) { + LIBSPDM_DEBUG((LIBSPDM_DEBUG_INFO, + "!!! VerifyCertificateChainData - FAIL (leaf certificate check failed)!!!\n")); + return false; + } + + return true; +} + +bool libspdm_verify_certificate_chain_buffer(uint32_t base_hash_algo, uint32_t base_asym_algo, + const void *cert_chain_buffer, + size_t cert_chain_buffer_size, + bool is_device_cert_model) +{ + const uint8_t *cert_chain_data; + size_t cert_chain_data_size; + const uint8_t *first_cert_buffer; + size_t first_cert_buffer_size; + size_t hash_size; + uint8_t calc_root_cert_hash[LIBSPDM_MAX_HASH_SIZE]; + const uint8_t *leaf_cert_buffer; + size_t leaf_cert_buffer_size; + bool result; + const spdm_cert_chain_t *cert_chain_header; + + hash_size = libspdm_get_hash_size(base_hash_algo); + + if (cert_chain_buffer_size <= sizeof(spdm_cert_chain_t) + hash_size) { + LIBSPDM_DEBUG((LIBSPDM_DEBUG_INFO, + "!!! VerifyCertificateChainBuffer - FAIL (buffer too small) !!!\n")); + return false; + } + + cert_chain_header = cert_chain_buffer; + if (cert_chain_header->length != cert_chain_buffer_size) { + LIBSPDM_DEBUG((LIBSPDM_DEBUG_INFO, + "!!! VerifyCertificateChainBuffer - FAIL (cert_chain->length mismatch) !!!\n")); + return false; + } + + cert_chain_data = (const uint8_t *)cert_chain_buffer + sizeof(spdm_cert_chain_t) + hash_size; + cert_chain_data_size = cert_chain_buffer_size - sizeof(spdm_cert_chain_t) - hash_size; + if (!libspdm_x509_get_cert_from_cert_chain( + cert_chain_data, cert_chain_data_size, 0, &first_cert_buffer, + &first_cert_buffer_size)) { + LIBSPDM_DEBUG((LIBSPDM_DEBUG_INFO, + "!!! VerifyCertificateChainBuffer - FAIL (get root certificate failed)!!!\n")); + return false; + } + + if (libspdm_is_root_certificate(first_cert_buffer, first_cert_buffer_size)) { + result = libspdm_hash_all(base_hash_algo, first_cert_buffer, first_cert_buffer_size, + calc_root_cert_hash); + if (!result) { + LIBSPDM_DEBUG((LIBSPDM_DEBUG_INFO, + "!!! VerifyCertificateChainBuffer - FAIL (hash calculation fail) !!!\n")); + return false; + } + if (libspdm_const_compare_mem((const uint8_t *)cert_chain_buffer + + sizeof(spdm_cert_chain_t), + calc_root_cert_hash, hash_size) != 0) { + LIBSPDM_DEBUG((LIBSPDM_DEBUG_INFO, + "!!! VerifyCertificateChainBuffer - FAIL (cert root hash mismatch) !!!\n")); + return false; + } + LIBSPDM_DEBUG((LIBSPDM_DEBUG_INFO, + "!!! VerifyCertificateChainBuffer - PASS (cert root hash match) !!!\n")); + } + + /*If the number of certificates in the certificate chain is more than 1, + * other certificates need to be verified.*/ + if (cert_chain_data_size > first_cert_buffer_size) { + if (!libspdm_x509_verify_cert_chain(first_cert_buffer, first_cert_buffer_size, + cert_chain_data + first_cert_buffer_size, + cert_chain_data_size - first_cert_buffer_size)) { + LIBSPDM_DEBUG((LIBSPDM_DEBUG_INFO, + "!!! VerifyCertificateChainBuffer - FAIL (cert chain verify failed)!!!\n")); + return false; + } + } + + if (!libspdm_x509_get_cert_from_cert_chain( + cert_chain_data, cert_chain_data_size, -1, + &leaf_cert_buffer, &leaf_cert_buffer_size)) { + LIBSPDM_DEBUG((LIBSPDM_DEBUG_INFO, + "!!! VerifyCertificateChainBuffer - FAIL (get leaf certificate failed)!!!\n")); + return false; + } + + if (!libspdm_x509_certificate_check(leaf_cert_buffer, leaf_cert_buffer_size, + base_asym_algo, base_hash_algo, + is_device_cert_model)) { + LIBSPDM_DEBUG((LIBSPDM_DEBUG_INFO, + "!!! VerifyCertificateChainBuffer - FAIL (leaf certificate check failed)!!!\n")); + return false; + } + + return true; +} + +bool libspdm_get_leaf_cert_public_key_from_cert_chain(uint32_t base_hash_algo, + uint32_t base_asym_alg, + uint8_t *cert_chain_data, + size_t cert_chain_data_size, + void **public_key) +{ + size_t hash_size; + const uint8_t *cert_buffer; + size_t cert_buffer_size; + bool result; + + hash_size = libspdm_get_hash_size(base_hash_algo); + + cert_chain_data = cert_chain_data + sizeof(spdm_cert_chain_t) + hash_size; + cert_chain_data_size = cert_chain_data_size - (sizeof(spdm_cert_chain_t) + hash_size); + + /* Get leaf cert from cert chain */ + result = libspdm_x509_get_cert_from_cert_chain(cert_chain_data, + cert_chain_data_size, -1, + &cert_buffer, &cert_buffer_size); + if (!result) { + return false; + } + + result = libspdm_asym_get_public_key_from_x509( + base_asym_alg, + cert_buffer, cert_buffer_size, public_key); + if (!result) { + return false; + } + + return true; +} + +bool libspdm_verify_req_info(uint8_t *req_info, uint16_t req_info_len) +{ + bool ret; + uint8_t *ptr; + int32_t length; + size_t obj_len; + uint8_t *end; + + length = (int32_t)req_info_len; + ptr = req_info; + obj_len = 0; + end = ptr + length; + ret = true; + + if (req_info_len == 0) { + return true; + } + + /*req_info sequence*/ + ret = libspdm_asn1_get_tag(&ptr, end, &obj_len, + LIBSPDM_CRYPTO_ASN1_SEQUENCE | LIBSPDM_CRYPTO_ASN1_CONSTRUCTED); + if (!ret) { + return false; + } + + /*integer:version*/ + ret = libspdm_asn1_get_tag(&ptr, end, &obj_len, LIBSPDM_CRYPTO_ASN1_INTEGER); + if (!ret) { + return false; + } else { + ptr += obj_len; + } + + /*sequence:subject name*/ + ret = libspdm_asn1_get_tag(&ptr, end, &obj_len, + LIBSPDM_CRYPTO_ASN1_SEQUENCE | LIBSPDM_CRYPTO_ASN1_CONSTRUCTED); + if (!ret) { + return false; + } else { + ptr += obj_len; + } + + /*sequence:subject pkinfo*/ + ret = libspdm_asn1_get_tag(&ptr, end, &obj_len, + LIBSPDM_CRYPTO_ASN1_SEQUENCE | LIBSPDM_CRYPTO_ASN1_CONSTRUCTED); + if (!ret) { + return false; + } else { + ptr += obj_len; + } + + /*[0]: attributes*/ + ret = libspdm_asn1_get_tag(&ptr, end, &obj_len, + LIBSPDM_CRYPTO_ASN1_CONTEXT_SPECIFIC | + LIBSPDM_CRYPTO_ASN1_CONSTRUCTED); + /*req_info format error, don't have attributes tag*/ + if (!ret) { + return false; + } + + /*there is no attributes object*/ + if (ptr == end) { + return true; + } + + /*there is some attributes object: 0,1,2 ...*/ + while (ret) + { + ret = libspdm_asn1_get_tag(&ptr, end, &obj_len, + LIBSPDM_CRYPTO_ASN1_SEQUENCE | + LIBSPDM_CRYPTO_ASN1_CONSTRUCTED); + if (ret) { + ptr += obj_len; + } else { + break; + } + } + + if (ptr == end) { + return true; + } else { + return false; + } +} diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/libraries/libspdm/2.3.1/library/spdm_crypt_lib/libspdm_crypt_dhe.c nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/libraries/libspdm/2.3.1/library/spdm_crypt_lib/libspdm_crypt_dhe.c --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/libraries/libspdm/2.3.1/library/spdm_crypt_lib/libspdm_crypt_dhe.c 1970-01-01 00:00:00.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/libraries/libspdm/2.3.1/library/spdm_crypt_lib/libspdm_crypt_dhe.c 2024-03-05 22:14:15.000000000 +0000 @@ -0,0 +1,270 @@ +/** + * Copyright Notice: + * Copyright 2021-2022 DMTF. All rights reserved. + * License: BSD 3-Clause License. For full text see link: https://github.com/DMTF/libspdm/blob/main/LICENSE.md + **/ + +#include "internal/libspdm_crypt_lib.h" + +/** + * This function returns the SPDM DHE algorithm key size. + * + * @param dhe_named_group SPDM dhe_named_group + * + * @return SPDM DHE algorithm key size. + **/ +uint32_t libspdm_get_dhe_pub_key_size(uint16_t dhe_named_group) +{ + switch (dhe_named_group) { + case SPDM_ALGORITHMS_DHE_NAMED_GROUP_FFDHE_2048: + return 256; + case SPDM_ALGORITHMS_DHE_NAMED_GROUP_FFDHE_3072: + return 384; + case SPDM_ALGORITHMS_DHE_NAMED_GROUP_FFDHE_4096: + return 512; + case SPDM_ALGORITHMS_DHE_NAMED_GROUP_SECP_256_R1: + return 32 * 2; + case SPDM_ALGORITHMS_DHE_NAMED_GROUP_SECP_384_R1: + return 48 * 2; + case SPDM_ALGORITHMS_DHE_NAMED_GROUP_SECP_521_R1: + return 66 * 2; + case SPDM_ALGORITHMS_DHE_NAMED_GROUP_SM2_P256: + return 32 * 2; + default: + return 0; + } +} + +/** + * Return cipher ID, based upon the negotiated DHE algorithm. + * + * @param dhe_named_group SPDM dhe_named_group + * + * @return DHE cipher ID + **/ +static size_t libspdm_get_dhe_nid(uint16_t dhe_named_group) +{ + switch (dhe_named_group) { + case SPDM_ALGORITHMS_DHE_NAMED_GROUP_FFDHE_2048: + return LIBSPDM_CRYPTO_NID_FFDHE2048; + case SPDM_ALGORITHMS_DHE_NAMED_GROUP_FFDHE_3072: + return LIBSPDM_CRYPTO_NID_FFDHE3072; + case SPDM_ALGORITHMS_DHE_NAMED_GROUP_FFDHE_4096: + return LIBSPDM_CRYPTO_NID_FFDHE4096; + case SPDM_ALGORITHMS_DHE_NAMED_GROUP_SECP_256_R1: + return LIBSPDM_CRYPTO_NID_SECP256R1; + case SPDM_ALGORITHMS_DHE_NAMED_GROUP_SECP_384_R1: + return LIBSPDM_CRYPTO_NID_SECP384R1; + case SPDM_ALGORITHMS_DHE_NAMED_GROUP_SECP_521_R1: + return LIBSPDM_CRYPTO_NID_SECP521R1; + case SPDM_ALGORITHMS_DHE_NAMED_GROUP_SM2_P256: + return LIBSPDM_CRYPTO_NID_SM2_KEY_EXCHANGE_P256; + default: + return LIBSPDM_CRYPTO_NID_NULL; + } +} + +void *libspdm_dhe_new(spdm_version_number_t spdm_version, + uint16_t dhe_named_group, bool is_initiator) +{ + size_t nid; + void *context; + + nid = libspdm_get_dhe_nid(dhe_named_group); + if (nid == 0) { + return NULL; + } + + switch (dhe_named_group) { + case SPDM_ALGORITHMS_DHE_NAMED_GROUP_FFDHE_2048: + case SPDM_ALGORITHMS_DHE_NAMED_GROUP_FFDHE_3072: + case SPDM_ALGORITHMS_DHE_NAMED_GROUP_FFDHE_4096: +#if LIBSPDM_FFDHE_SUPPORT + context = libspdm_dh_new_by_nid(nid); +#else + LIBSPDM_ASSERT(false); + return NULL; +#endif + break; + case SPDM_ALGORITHMS_DHE_NAMED_GROUP_SECP_256_R1: + case SPDM_ALGORITHMS_DHE_NAMED_GROUP_SECP_384_R1: + case SPDM_ALGORITHMS_DHE_NAMED_GROUP_SECP_521_R1: +#if LIBSPDM_ECDHE_SUPPORT + context = libspdm_ec_new_by_nid(nid); +#else + LIBSPDM_ASSERT(false); + return NULL; +#endif + break; + case SPDM_ALGORITHMS_DHE_NAMED_GROUP_SM2_P256: +#if LIBSPDM_SM2_KEY_EXCHANGE_SUPPORT + context = libspdm_sm2_key_exchange_new_by_nid(nid); +#else + LIBSPDM_ASSERT(false); + return NULL; +#endif + break; + default: + LIBSPDM_ASSERT(false); + return NULL; + } + +#if LIBSPDM_SM2_KEY_EXCHANGE_SUPPORT + if (dhe_named_group == SPDM_ALGORITHMS_DHE_NAMED_GROUP_SM2_P256) { + bool result; + uint8_t spdm12_key_change_requester_context[ + SPDM_VERSION_1_2_KEY_EXCHANGE_REQUESTER_CONTEXT_SIZE]; + uint8_t spdm12_key_change_responder_context[ + SPDM_VERSION_1_2_KEY_EXCHANGE_RESPONDER_CONTEXT_SIZE]; + + libspdm_copy_mem(spdm12_key_change_requester_context, + sizeof(spdm12_key_change_requester_context), + SPDM_VERSION_1_2_KEY_EXCHANGE_REQUESTER_CONTEXT, + SPDM_VERSION_1_2_KEY_EXCHANGE_REQUESTER_CONTEXT_SIZE); + libspdm_copy_mem(spdm12_key_change_responder_context, + sizeof(spdm12_key_change_responder_context), + SPDM_VERSION_1_2_KEY_EXCHANGE_RESPONDER_CONTEXT, + SPDM_VERSION_1_2_KEY_EXCHANGE_RESPONDER_CONTEXT_SIZE); + /* patch the version*/ + spdm12_key_change_requester_context[25] = (char)('0' + ((spdm_version >> 12) & 0xF)); + spdm12_key_change_requester_context[27] = (char)('0' + ((spdm_version >> 8) & 0xF)); + spdm12_key_change_responder_context[25] = (char)('0' + ((spdm_version >> 12) & 0xF)); + spdm12_key_change_responder_context[27] = (char)('0' + ((spdm_version >> 8) & 0xF)); + + result = libspdm_sm2_key_exchange_init (context, LIBSPDM_CRYPTO_NID_SM3_256, + spdm12_key_change_requester_context, + SPDM_VERSION_1_2_KEY_EXCHANGE_REQUESTER_CONTEXT_SIZE, + spdm12_key_change_responder_context, + SPDM_VERSION_1_2_KEY_EXCHANGE_RESPONDER_CONTEXT_SIZE, + is_initiator); + if (!result) { + libspdm_sm2_key_exchange_free (context); + return NULL; + } + } +#endif /* LIBSPDM_SM2_KEY_EXCHANGE_SUPPORT */ + + return context; +} + +void libspdm_dhe_free(uint16_t dhe_named_group, void *context) +{ + switch (dhe_named_group) { + case SPDM_ALGORITHMS_DHE_NAMED_GROUP_FFDHE_2048: + case SPDM_ALGORITHMS_DHE_NAMED_GROUP_FFDHE_3072: + case SPDM_ALGORITHMS_DHE_NAMED_GROUP_FFDHE_4096: +#if LIBSPDM_FFDHE_SUPPORT + libspdm_dh_free(context); +#else + LIBSPDM_ASSERT(false); +#endif + break; + case SPDM_ALGORITHMS_DHE_NAMED_GROUP_SECP_256_R1: + case SPDM_ALGORITHMS_DHE_NAMED_GROUP_SECP_384_R1: + case SPDM_ALGORITHMS_DHE_NAMED_GROUP_SECP_521_R1: +#if LIBSPDM_ECDHE_SUPPORT + libspdm_ec_free(context); +#else + LIBSPDM_ASSERT(false); +#endif + break; + case SPDM_ALGORITHMS_DHE_NAMED_GROUP_SM2_P256: +#if LIBSPDM_SM2_KEY_EXCHANGE_SUPPORT + libspdm_sm2_key_exchange_free(context); +#else + LIBSPDM_ASSERT(false); +#endif + break; + default: + LIBSPDM_ASSERT(false); + break; + } +} + +bool libspdm_dhe_generate_key(uint16_t dhe_named_group, void *context, + uint8_t *public_key, + size_t *public_key_size) +{ + switch (dhe_named_group) { + case SPDM_ALGORITHMS_DHE_NAMED_GROUP_FFDHE_2048: + case SPDM_ALGORITHMS_DHE_NAMED_GROUP_FFDHE_3072: + case SPDM_ALGORITHMS_DHE_NAMED_GROUP_FFDHE_4096: +#if LIBSPDM_FFDHE_SUPPORT + return libspdm_dh_generate_key(context, public_key, public_key_size); +#else + LIBSPDM_ASSERT(false); + return false; +#endif + case SPDM_ALGORITHMS_DHE_NAMED_GROUP_SECP_256_R1: + case SPDM_ALGORITHMS_DHE_NAMED_GROUP_SECP_384_R1: + case SPDM_ALGORITHMS_DHE_NAMED_GROUP_SECP_521_R1: +#if LIBSPDM_ECDHE_SUPPORT + return libspdm_ec_generate_key(context, public_key, public_key_size); +#else + LIBSPDM_ASSERT(false); + return false; +#endif + case SPDM_ALGORITHMS_DHE_NAMED_GROUP_SM2_P256: +#if LIBSPDM_SM2_KEY_EXCHANGE_SUPPORT + return libspdm_sm2_key_exchange_generate_key(context, public_key, public_key_size); +#else + LIBSPDM_ASSERT(false); + return false; +#endif + default: + LIBSPDM_ASSERT(false); + return false; + } +} + +bool libspdm_dhe_compute_key(uint16_t dhe_named_group, void *context, + const uint8_t *peer_public, + size_t peer_public_size, uint8_t *key, + size_t *key_size) +{ +#if LIBSPDM_SM2_KEY_EXCHANGE_SUPPORT + bool ret; +#endif + + switch (dhe_named_group) { + case SPDM_ALGORITHMS_DHE_NAMED_GROUP_FFDHE_2048: + case SPDM_ALGORITHMS_DHE_NAMED_GROUP_FFDHE_3072: + case SPDM_ALGORITHMS_DHE_NAMED_GROUP_FFDHE_4096: +#if LIBSPDM_FFDHE_SUPPORT + return libspdm_dh_compute_key(context, peer_public, peer_public_size, key, key_size); +#else + LIBSPDM_ASSERT(false); + return false; +#endif + case SPDM_ALGORITHMS_DHE_NAMED_GROUP_SECP_256_R1: + case SPDM_ALGORITHMS_DHE_NAMED_GROUP_SECP_384_R1: + case SPDM_ALGORITHMS_DHE_NAMED_GROUP_SECP_521_R1: +#if LIBSPDM_ECDHE_SUPPORT + return libspdm_ec_compute_key(context, peer_public, peer_public_size, key, key_size); +#else + LIBSPDM_ASSERT(false); + return false; +#endif + case SPDM_ALGORITHMS_DHE_NAMED_GROUP_SM2_P256: +#if LIBSPDM_SM2_KEY_EXCHANGE_SUPPORT + ret = libspdm_sm2_key_exchange_compute_key(context, peer_public, + peer_public_size, key, key_size); + if (!ret) { + return false; + } else { + /* SM2 key exchange can generate arbitrary length key_size. + * SPDM requires SM2 key_size to be 16. */ + LIBSPDM_ASSERT (*key_size >= 16); + *key_size = 16; + + return true; + } +#else + LIBSPDM_ASSERT(false); + return false; +#endif + default: + LIBSPDM_ASSERT(false); + return false; + } +} diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/libraries/libspdm/2.3.1/library/spdm_crypt_lib/libspdm_crypt_hash.c nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/libraries/libspdm/2.3.1/library/spdm_crypt_lib/libspdm_crypt_hash.c --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/libraries/libspdm/2.3.1/library/spdm_crypt_lib/libspdm_crypt_hash.c 1970-01-01 00:00:00.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/libraries/libspdm/2.3.1/library/spdm_crypt_lib/libspdm_crypt_hash.c 2024-03-05 22:14:15.000000000 +0000 @@ -0,0 +1,477 @@ +/** + * Copyright Notice: + * Copyright 2021-2022 DMTF. All rights reserved. + * License: BSD 3-Clause License. For full text see link: https://github.com/DMTF/libspdm/blob/main/LICENSE.md + **/ + +#include "internal/libspdm_crypt_lib.h" + +uint32_t libspdm_get_hash_size(uint32_t base_hash_algo) +{ + switch (base_hash_algo) { + case SPDM_ALGORITHMS_BASE_HASH_ALGO_TPM_ALG_SHA_256: + case SPDM_ALGORITHMS_BASE_HASH_ALGO_TPM_ALG_SHA3_256: + return 32; + case SPDM_ALGORITHMS_BASE_HASH_ALGO_TPM_ALG_SHA_384: + case SPDM_ALGORITHMS_BASE_HASH_ALGO_TPM_ALG_SHA3_384: + return 48; + case SPDM_ALGORITHMS_BASE_HASH_ALGO_TPM_ALG_SHA_512: + case SPDM_ALGORITHMS_BASE_HASH_ALGO_TPM_ALG_SHA3_512: + return 64; + case SPDM_ALGORITHMS_BASE_HASH_ALGO_TPM_ALG_SM3_256: + return 32; + default: + return 0; + } +} + +size_t libspdm_get_hash_nid(uint32_t base_hash_algo) +{ + switch (base_hash_algo) { + case SPDM_ALGORITHMS_BASE_HASH_ALGO_TPM_ALG_SHA_256: + return LIBSPDM_CRYPTO_NID_SHA256; + case SPDM_ALGORITHMS_BASE_HASH_ALGO_TPM_ALG_SHA_384: + return LIBSPDM_CRYPTO_NID_SHA384; + case SPDM_ALGORITHMS_BASE_HASH_ALGO_TPM_ALG_SHA_512: + return LIBSPDM_CRYPTO_NID_SHA512; + case SPDM_ALGORITHMS_BASE_HASH_ALGO_TPM_ALG_SHA3_256: + return LIBSPDM_CRYPTO_NID_SHA3_256; + case SPDM_ALGORITHMS_BASE_HASH_ALGO_TPM_ALG_SHA3_384: + return LIBSPDM_CRYPTO_NID_SHA3_384; + case SPDM_ALGORITHMS_BASE_HASH_ALGO_TPM_ALG_SHA3_512: + return LIBSPDM_CRYPTO_NID_SHA3_512; + case SPDM_ALGORITHMS_BASE_HASH_ALGO_TPM_ALG_SM3_256: + return LIBSPDM_CRYPTO_NID_SM3_256; + default: + return LIBSPDM_CRYPTO_NID_NULL; + } +} + +void *libspdm_hash_new(uint32_t base_hash_algo) +{ + switch (base_hash_algo) { + case SPDM_ALGORITHMS_BASE_HASH_ALGO_TPM_ALG_SHA_256: +#if LIBSPDM_SHA256_SUPPORT + return libspdm_sha256_new(); +#else + LIBSPDM_ASSERT(false); + return NULL; +#endif + case SPDM_ALGORITHMS_BASE_HASH_ALGO_TPM_ALG_SHA_384: +#if LIBSPDM_SHA384_SUPPORT + return libspdm_sha384_new(); +#else + LIBSPDM_ASSERT(false); + return NULL; +#endif + case SPDM_ALGORITHMS_BASE_HASH_ALGO_TPM_ALG_SHA_512: +#if LIBSPDM_SHA512_SUPPORT + return libspdm_sha512_new(); +#else + LIBSPDM_ASSERT(false); + return NULL; +#endif + case SPDM_ALGORITHMS_BASE_HASH_ALGO_TPM_ALG_SHA3_256: +#if LIBSPDM_SHA3_256_SUPPORT + return libspdm_sha3_256_new(); +#else + LIBSPDM_ASSERT(false); + return NULL; +#endif + case SPDM_ALGORITHMS_BASE_HASH_ALGO_TPM_ALG_SHA3_384: +#if LIBSPDM_SHA3_384_SUPPORT + return libspdm_sha3_384_new(); +#else + LIBSPDM_ASSERT(false); + return NULL; +#endif + case SPDM_ALGORITHMS_BASE_HASH_ALGO_TPM_ALG_SHA3_512: +#if LIBSPDM_SHA3_512_SUPPORT + return libspdm_sha3_512_new(); +#else + LIBSPDM_ASSERT(false); + return NULL; +#endif + case SPDM_ALGORITHMS_BASE_HASH_ALGO_TPM_ALG_SM3_256: +#if LIBSPDM_SM3_256_SUPPORT + return libspdm_sm3_256_new(); +#else + LIBSPDM_ASSERT(false); + return NULL; +#endif + default: + LIBSPDM_ASSERT(false); + return NULL; + } +} + +void libspdm_hash_free(uint32_t base_hash_algo, void *hash_context) +{ + switch (base_hash_algo) { + case SPDM_ALGORITHMS_BASE_HASH_ALGO_TPM_ALG_SHA_256: +#if LIBSPDM_SHA256_SUPPORT + libspdm_sha256_free(hash_context); +#else + LIBSPDM_ASSERT(false); +#endif + break; + case SPDM_ALGORITHMS_BASE_HASH_ALGO_TPM_ALG_SHA_384: +#if LIBSPDM_SHA384_SUPPORT + libspdm_sha384_free(hash_context); +#else + LIBSPDM_ASSERT(false); +#endif + break; + case SPDM_ALGORITHMS_BASE_HASH_ALGO_TPM_ALG_SHA_512: +#if LIBSPDM_SHA512_SUPPORT + libspdm_sha512_free(hash_context); +#else + LIBSPDM_ASSERT(false); +#endif + break; + case SPDM_ALGORITHMS_BASE_HASH_ALGO_TPM_ALG_SHA3_256: +#if LIBSPDM_SHA3_256_SUPPORT + libspdm_sha3_256_free(hash_context); +#else + LIBSPDM_ASSERT(false); +#endif + break; + case SPDM_ALGORITHMS_BASE_HASH_ALGO_TPM_ALG_SHA3_384: +#if LIBSPDM_SHA3_384_SUPPORT + libspdm_sha3_384_free(hash_context); +#else + LIBSPDM_ASSERT(false); +#endif + break; + case SPDM_ALGORITHMS_BASE_HASH_ALGO_TPM_ALG_SHA3_512: +#if LIBSPDM_SHA3_512_SUPPORT + libspdm_sha3_512_free(hash_context); +#else + LIBSPDM_ASSERT(false); +#endif + break; + case SPDM_ALGORITHMS_BASE_HASH_ALGO_TPM_ALG_SM3_256: +#if LIBSPDM_SM3_256_SUPPORT + libspdm_sm3_256_free(hash_context); +#else + LIBSPDM_ASSERT(false); +#endif + break; + default: + LIBSPDM_ASSERT(false); + break; + } +} + +bool libspdm_hash_init(uint32_t base_hash_algo, void *hash_context) +{ + switch (base_hash_algo) { + case SPDM_ALGORITHMS_BASE_HASH_ALGO_TPM_ALG_SHA_256: +#if LIBSPDM_SHA256_SUPPORT + return libspdm_sha256_init(hash_context); +#else + LIBSPDM_ASSERT(false); + return false; +#endif + case SPDM_ALGORITHMS_BASE_HASH_ALGO_TPM_ALG_SHA_384: +#if LIBSPDM_SHA384_SUPPORT + return libspdm_sha384_init(hash_context); +#else + LIBSPDM_ASSERT(false); + return false; +#endif + case SPDM_ALGORITHMS_BASE_HASH_ALGO_TPM_ALG_SHA_512: +#if LIBSPDM_SHA512_SUPPORT + return libspdm_sha512_init(hash_context); +#else + LIBSPDM_ASSERT(false); + return false; +#endif + case SPDM_ALGORITHMS_BASE_HASH_ALGO_TPM_ALG_SHA3_256: +#if LIBSPDM_SHA3_256_SUPPORT + return libspdm_sha3_256_init(hash_context); +#else + LIBSPDM_ASSERT(false); + return false; +#endif + case SPDM_ALGORITHMS_BASE_HASH_ALGO_TPM_ALG_SHA3_384: +#if LIBSPDM_SHA3_384_SUPPORT + return libspdm_sha3_384_init(hash_context); +#else + LIBSPDM_ASSERT(false); + return false; +#endif + case SPDM_ALGORITHMS_BASE_HASH_ALGO_TPM_ALG_SHA3_512: +#if LIBSPDM_SHA3_512_SUPPORT + return libspdm_sha3_512_init(hash_context); +#else + LIBSPDM_ASSERT(false); + return false; +#endif + case SPDM_ALGORITHMS_BASE_HASH_ALGO_TPM_ALG_SM3_256: +#if LIBSPDM_SM3_256_SUPPORT + return libspdm_sm3_256_init(hash_context); +#else + LIBSPDM_ASSERT(false); + return false; +#endif + default: + LIBSPDM_ASSERT(false); + return false; + } +} + +bool libspdm_hash_duplicate(uint32_t base_hash_algo, const void *hash_ctx, void *new_hash_ctx) +{ + switch (base_hash_algo) { + case SPDM_ALGORITHMS_BASE_HASH_ALGO_TPM_ALG_SHA_256: +#if LIBSPDM_SHA256_SUPPORT + return libspdm_sha256_duplicate(hash_ctx, new_hash_ctx); +#else + LIBSPDM_ASSERT(false); + return false; +#endif + case SPDM_ALGORITHMS_BASE_HASH_ALGO_TPM_ALG_SHA_384: +#if LIBSPDM_SHA384_SUPPORT + return libspdm_sha384_duplicate(hash_ctx, new_hash_ctx); +#else + LIBSPDM_ASSERT(false); + return false; +#endif + case SPDM_ALGORITHMS_BASE_HASH_ALGO_TPM_ALG_SHA_512: +#if LIBSPDM_SHA512_SUPPORT + return libspdm_sha512_duplicate(hash_ctx, new_hash_ctx); +#else + LIBSPDM_ASSERT(false); + return false; +#endif + case SPDM_ALGORITHMS_BASE_HASH_ALGO_TPM_ALG_SHA3_256: +#if LIBSPDM_SHA3_256_SUPPORT + return libspdm_sha3_256_duplicate(hash_ctx, new_hash_ctx); +#else + LIBSPDM_ASSERT(false); + return false; +#endif + case SPDM_ALGORITHMS_BASE_HASH_ALGO_TPM_ALG_SHA3_384: +#if LIBSPDM_SHA3_384_SUPPORT + return libspdm_sha3_384_duplicate(hash_ctx, new_hash_ctx); +#else + LIBSPDM_ASSERT(false); + return false; +#endif + case SPDM_ALGORITHMS_BASE_HASH_ALGO_TPM_ALG_SHA3_512: +#if LIBSPDM_SHA3_512_SUPPORT + return libspdm_sha3_512_duplicate(hash_ctx, new_hash_ctx); +#else + LIBSPDM_ASSERT(false); + return false; +#endif + case SPDM_ALGORITHMS_BASE_HASH_ALGO_TPM_ALG_SM3_256: +#if LIBSPDM_SM3_256_SUPPORT + return libspdm_sm3_256_duplicate(hash_ctx, new_hash_ctx); +#else + LIBSPDM_ASSERT(false); + return false; +#endif + default: + LIBSPDM_ASSERT(false); + return false; + } +} + +bool libspdm_hash_update(uint32_t base_hash_algo, void *hash_context, + const void *data, size_t data_size) +{ + switch (base_hash_algo) { + case SPDM_ALGORITHMS_BASE_HASH_ALGO_TPM_ALG_SHA_256: +#if LIBSPDM_SHA256_SUPPORT + return libspdm_sha256_update(hash_context, data, data_size); +#else + LIBSPDM_ASSERT(false); + return false; +#endif + case SPDM_ALGORITHMS_BASE_HASH_ALGO_TPM_ALG_SHA_384: +#if LIBSPDM_SHA384_SUPPORT + return libspdm_sha384_update(hash_context, data, data_size); +#else + LIBSPDM_ASSERT(false); + return false; +#endif + case SPDM_ALGORITHMS_BASE_HASH_ALGO_TPM_ALG_SHA_512: +#if LIBSPDM_SHA512_SUPPORT + return libspdm_sha512_update(hash_context, data, data_size); +#else + LIBSPDM_ASSERT(false); + return false; +#endif + case SPDM_ALGORITHMS_BASE_HASH_ALGO_TPM_ALG_SHA3_256: +#if LIBSPDM_SHA3_256_SUPPORT + return libspdm_sha3_256_update(hash_context, data, data_size); +#else + LIBSPDM_ASSERT(false); + return false; +#endif + case SPDM_ALGORITHMS_BASE_HASH_ALGO_TPM_ALG_SHA3_384: +#if LIBSPDM_SHA3_384_SUPPORT + return libspdm_sha3_384_update(hash_context, data, data_size); +#else + LIBSPDM_ASSERT(false); + return false; +#endif + case SPDM_ALGORITHMS_BASE_HASH_ALGO_TPM_ALG_SHA3_512: +#if LIBSPDM_SHA3_512_SUPPORT + return libspdm_sha3_512_update(hash_context, data, data_size); +#else + LIBSPDM_ASSERT(false); + return false; +#endif + case SPDM_ALGORITHMS_BASE_HASH_ALGO_TPM_ALG_SM3_256: +#if LIBSPDM_SM3_256_SUPPORT + return libspdm_sm3_256_update(hash_context, data, data_size); +#else + LIBSPDM_ASSERT(false); + return false; +#endif + default: + LIBSPDM_ASSERT(false); + return false; + } +} + +bool libspdm_hash_final(uint32_t base_hash_algo, void *hash_context, uint8_t *hash_value) +{ + switch (base_hash_algo) { + case SPDM_ALGORITHMS_BASE_HASH_ALGO_TPM_ALG_SHA_256: +#if LIBSPDM_SHA256_SUPPORT + return libspdm_sha256_final(hash_context, hash_value); +#else + LIBSPDM_ASSERT(false); + return false; +#endif + case SPDM_ALGORITHMS_BASE_HASH_ALGO_TPM_ALG_SHA_384: +#if LIBSPDM_SHA384_SUPPORT + return libspdm_sha384_final(hash_context, hash_value); +#else + LIBSPDM_ASSERT(false); + return false; +#endif + case SPDM_ALGORITHMS_BASE_HASH_ALGO_TPM_ALG_SHA_512: +#if LIBSPDM_SHA512_SUPPORT + return libspdm_sha512_final(hash_context, hash_value); +#else + LIBSPDM_ASSERT(false); + return false; +#endif + case SPDM_ALGORITHMS_BASE_HASH_ALGO_TPM_ALG_SHA3_256: +#if LIBSPDM_SHA3_256_SUPPORT + return libspdm_sha3_256_final(hash_context, hash_value); +#else + LIBSPDM_ASSERT(false); + return false; +#endif + case SPDM_ALGORITHMS_BASE_HASH_ALGO_TPM_ALG_SHA3_384: +#if LIBSPDM_SHA3_384_SUPPORT + return libspdm_sha3_384_final(hash_context, hash_value); +#else + LIBSPDM_ASSERT(false); + return false; +#endif + case SPDM_ALGORITHMS_BASE_HASH_ALGO_TPM_ALG_SHA3_512: +#if LIBSPDM_SHA3_512_SUPPORT + return libspdm_sha3_512_final(hash_context, hash_value); +#else + LIBSPDM_ASSERT(false); + return false; +#endif + case SPDM_ALGORITHMS_BASE_HASH_ALGO_TPM_ALG_SM3_256: +#if LIBSPDM_SM3_256_SUPPORT + return libspdm_sm3_256_final(hash_context, hash_value); +#else + LIBSPDM_ASSERT(false); + return false; +#endif + default: + LIBSPDM_ASSERT(false); + return false; + } +} + +bool libspdm_hash_all(uint32_t base_hash_algo, const void *data, + size_t data_size, uint8_t *hash_value) +{ + switch (base_hash_algo) { + case SPDM_ALGORITHMS_BASE_HASH_ALGO_TPM_ALG_SHA_256: +#if LIBSPDM_SHA256_SUPPORT + return libspdm_sha256_hash_all(data, data_size, hash_value); +#else + LIBSPDM_ASSERT(false); + return false; +#endif + case SPDM_ALGORITHMS_BASE_HASH_ALGO_TPM_ALG_SHA_384: +#if LIBSPDM_SHA384_SUPPORT + return libspdm_sha384_hash_all(data, data_size, hash_value); +#else + LIBSPDM_ASSERT(false); + return false; +#endif + case SPDM_ALGORITHMS_BASE_HASH_ALGO_TPM_ALG_SHA_512: +#if LIBSPDM_SHA512_SUPPORT + return libspdm_sha512_hash_all(data, data_size, hash_value); +#else + LIBSPDM_ASSERT(false); + return false; +#endif + case SPDM_ALGORITHMS_BASE_HASH_ALGO_TPM_ALG_SHA3_256: +#if LIBSPDM_SHA3_256_SUPPORT + return libspdm_sha3_256_hash_all(data, data_size, hash_value); +#else + LIBSPDM_ASSERT(false); + return false; +#endif + case SPDM_ALGORITHMS_BASE_HASH_ALGO_TPM_ALG_SHA3_384: +#if LIBSPDM_SHA3_384_SUPPORT + return libspdm_sha3_384_hash_all(data, data_size, hash_value); +#else + LIBSPDM_ASSERT(false); + return false; +#endif + case SPDM_ALGORITHMS_BASE_HASH_ALGO_TPM_ALG_SHA3_512: +#if LIBSPDM_SHA3_512_SUPPORT + return libspdm_sha3_512_hash_all(data, data_size, hash_value); +#else + LIBSPDM_ASSERT(false); + return false; +#endif + case SPDM_ALGORITHMS_BASE_HASH_ALGO_TPM_ALG_SM3_256: +#if LIBSPDM_SM3_256_SUPPORT + return libspdm_sm3_256_hash_all(data, data_size, hash_value); +#else + LIBSPDM_ASSERT(false); + return false; +#endif + default: + LIBSPDM_ASSERT(false); + return false; + } +} + +uint32_t libspdm_get_measurement_hash_size(uint32_t measurement_hash_algo) +{ + switch (measurement_hash_algo) { + case SPDM_ALGORITHMS_MEASUREMENT_HASH_ALGO_TPM_ALG_SHA_256: + case SPDM_ALGORITHMS_MEASUREMENT_HASH_ALGO_TPM_ALG_SHA3_256: + return 32; + case SPDM_ALGORITHMS_MEASUREMENT_HASH_ALGO_TPM_ALG_SHA_384: + case SPDM_ALGORITHMS_MEASUREMENT_HASH_ALGO_TPM_ALG_SHA3_384: + return 48; + case SPDM_ALGORITHMS_MEASUREMENT_HASH_ALGO_TPM_ALG_SHA_512: + case SPDM_ALGORITHMS_MEASUREMENT_HASH_ALGO_TPM_ALG_SHA3_512: + return 64; + case SPDM_ALGORITHMS_MEASUREMENT_HASH_ALGO_TPM_ALG_SM3_256: + return 32; + case SPDM_ALGORITHMS_MEASUREMENT_HASH_ALGO_RAW_BIT_STREAM_ONLY: + return 0xFFFFFFFF; + default: + return 0; + } +} diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/libraries/libspdm/2.3.1/library/spdm_crypt_lib/libspdm_crypt_hkdf.c nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/libraries/libspdm/2.3.1/library/spdm_crypt_lib/libspdm_crypt_hkdf.c --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/libraries/libspdm/2.3.1/library/spdm_crypt_lib/libspdm_crypt_hkdf.c 1970-01-01 00:00:00.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/libraries/libspdm/2.3.1/library/spdm_crypt_lib/libspdm_crypt_hkdf.c 2024-03-05 22:14:15.000000000 +0000 @@ -0,0 +1,127 @@ +/** + * Copyright Notice: + * Copyright 2021-2022 DMTF. All rights reserved. + * License: BSD 3-Clause License. For full text see link: https://github.com/DMTF/libspdm/blob/main/LICENSE.md + **/ + +#include "internal/libspdm_crypt_lib.h" + +bool libspdm_hkdf_extract(uint32_t base_hash_algo, const uint8_t *ikm, size_t ikm_size, + const uint8_t *salt, size_t salt_size, + uint8_t *prk_out, size_t prk_out_size) +{ + switch (base_hash_algo) { + case SPDM_ALGORITHMS_BASE_HASH_ALGO_TPM_ALG_SHA_256: +#if LIBSPDM_SHA256_SUPPORT + return libspdm_hkdf_sha256_extract(ikm, ikm_size, salt, salt_size, prk_out, prk_out_size); +#else + LIBSPDM_ASSERT(false); + return false; +#endif + case SPDM_ALGORITHMS_BASE_HASH_ALGO_TPM_ALG_SHA_384: +#if LIBSPDM_SHA384_SUPPORT + return libspdm_hkdf_sha384_extract(ikm, ikm_size, salt, salt_size, prk_out, prk_out_size); +#else + LIBSPDM_ASSERT(false); + return false; +#endif + case SPDM_ALGORITHMS_BASE_HASH_ALGO_TPM_ALG_SHA_512: +#if LIBSPDM_SHA512_SUPPORT + return libspdm_hkdf_sha512_extract(ikm, ikm_size, salt, salt_size, prk_out, prk_out_size); +#else + LIBSPDM_ASSERT(false); + return false; +#endif + case SPDM_ALGORITHMS_BASE_HASH_ALGO_TPM_ALG_SHA3_256: +#if LIBSPDM_SHA3_256_SUPPORT + return libspdm_hkdf_sha3_256_extract(ikm, ikm_size, salt, salt_size, prk_out, prk_out_size); +#else + LIBSPDM_ASSERT(false); + return false; +#endif + case SPDM_ALGORITHMS_BASE_HASH_ALGO_TPM_ALG_SHA3_384: +#if LIBSPDM_SHA3_384_SUPPORT + return libspdm_hkdf_sha3_384_extract(ikm, ikm_size, salt, salt_size, prk_out, prk_out_size); +#else + LIBSPDM_ASSERT(false); + return false; +#endif + case SPDM_ALGORITHMS_BASE_HASH_ALGO_TPM_ALG_SHA3_512: +#if LIBSPDM_SHA3_512_SUPPORT + return libspdm_hkdf_sha3_512_extract(ikm, ikm_size, salt, salt_size, prk_out, prk_out_size); +#else + LIBSPDM_ASSERT(false); + return false; +#endif + case SPDM_ALGORITHMS_BASE_HASH_ALGO_TPM_ALG_SM3_256: +#if LIBSPDM_SM3_256_SUPPORT + return libspdm_hkdf_sm3_256_extract(ikm, ikm_size, salt, salt_size, prk_out, prk_out_size); +#else + LIBSPDM_ASSERT(false); + return false; +#endif + default: + LIBSPDM_ASSERT(false); + return false; + } +} + +bool libspdm_hkdf_expand(uint32_t base_hash_algo, const uint8_t *prk, + size_t prk_size, const uint8_t *info, + size_t info_size, uint8_t *out, size_t out_size) +{ + switch (base_hash_algo) { + case SPDM_ALGORITHMS_BASE_HASH_ALGO_TPM_ALG_SHA_256: +#if LIBSPDM_SHA256_SUPPORT + return libspdm_hkdf_sha256_expand(prk, prk_size, info, info_size, out, out_size); +#else + LIBSPDM_ASSERT(false); + return false; +#endif + case SPDM_ALGORITHMS_BASE_HASH_ALGO_TPM_ALG_SHA_384: +#if LIBSPDM_SHA384_SUPPORT + return libspdm_hkdf_sha384_expand(prk, prk_size, info, info_size, out, out_size); +#else + LIBSPDM_ASSERT(false); + return false; +#endif + case SPDM_ALGORITHMS_BASE_HASH_ALGO_TPM_ALG_SHA_512: +#if LIBSPDM_SHA512_SUPPORT + return libspdm_hkdf_sha512_expand(prk, prk_size, info, info_size, out, out_size); +#else + LIBSPDM_ASSERT(false); + return false; +#endif + case SPDM_ALGORITHMS_BASE_HASH_ALGO_TPM_ALG_SHA3_256: +#if LIBSPDM_SHA3_256_SUPPORT + return libspdm_hkdf_sha3_256_expand(prk, prk_size, info, info_size, out, out_size); +#else + LIBSPDM_ASSERT(false); + return false; +#endif + case SPDM_ALGORITHMS_BASE_HASH_ALGO_TPM_ALG_SHA3_384: +#if LIBSPDM_SHA3_384_SUPPORT + return libspdm_hkdf_sha3_384_expand(prk, prk_size, info, info_size, out, out_size); +#else + LIBSPDM_ASSERT(false); + return false; +#endif + case SPDM_ALGORITHMS_BASE_HASH_ALGO_TPM_ALG_SHA3_512: +#if LIBSPDM_SHA3_512_SUPPORT + return libspdm_hkdf_sha3_512_expand(prk, prk_size, info, info_size, out, out_size); +#else + LIBSPDM_ASSERT(false); + return false; +#endif + case SPDM_ALGORITHMS_BASE_HASH_ALGO_TPM_ALG_SM3_256: +#if LIBSPDM_SM3_256_SUPPORT + return libspdm_hkdf_sm3_256_expand(prk, prk_size, info, info_size, out, out_size); +#else + LIBSPDM_ASSERT(false); + return false; +#endif + default: + LIBSPDM_ASSERT(false); + return false; + } +} diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/libraries/libspdm/2.3.1/library/spdm_crypt_lib/libspdm_crypt_hmac.c nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/libraries/libspdm/2.3.1/library/spdm_crypt_lib/libspdm_crypt_hmac.c --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/libraries/libspdm/2.3.1/library/spdm_crypt_lib/libspdm_crypt_hmac.c 1970-01-01 00:00:00.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/libraries/libspdm/2.3.1/library/spdm_crypt_lib/libspdm_crypt_hmac.c 2024-03-05 22:14:15.000000000 +0000 @@ -0,0 +1,419 @@ +/** + * Copyright Notice: + * Copyright 2021-2022 DMTF. All rights reserved. + * License: BSD 3-Clause License. For full text see link: https://github.com/DMTF/libspdm/blob/main/LICENSE.md + **/ + +#include "internal/libspdm_crypt_lib.h" + +void *libspdm_hmac_new(uint32_t base_hash_algo) +{ + switch (base_hash_algo) { + case SPDM_ALGORITHMS_BASE_HASH_ALGO_TPM_ALG_SHA_256: +#if LIBSPDM_SHA256_SUPPORT + return libspdm_hmac_sha256_new(); +#else + LIBSPDM_ASSERT(false); + return false; +#endif + case SPDM_ALGORITHMS_BASE_HASH_ALGO_TPM_ALG_SHA_384: +#if LIBSPDM_SHA384_SUPPORT + return libspdm_hmac_sha384_new(); +#else + LIBSPDM_ASSERT(false); + return false; +#endif + case SPDM_ALGORITHMS_BASE_HASH_ALGO_TPM_ALG_SHA_512: +#if LIBSPDM_SHA512_SUPPORT + return libspdm_hmac_sha512_new(); +#else + LIBSPDM_ASSERT(false); + return false; +#endif + case SPDM_ALGORITHMS_BASE_HASH_ALGO_TPM_ALG_SHA3_256: +#if LIBSPDM_SHA3_256_SUPPORT + return libspdm_hmac_sha3_256_new(); +#else + LIBSPDM_ASSERT(false); + return false; +#endif + case SPDM_ALGORITHMS_BASE_HASH_ALGO_TPM_ALG_SHA3_384: +#if LIBSPDM_SHA3_384_SUPPORT + return libspdm_hmac_sha3_384_new(); +#else + LIBSPDM_ASSERT(false); + return false; +#endif + case SPDM_ALGORITHMS_BASE_HASH_ALGO_TPM_ALG_SHA3_512: +#if LIBSPDM_SHA3_512_SUPPORT + return libspdm_hmac_sha3_512_new(); +#else + LIBSPDM_ASSERT(false); + return false; +#endif + case SPDM_ALGORITHMS_BASE_HASH_ALGO_TPM_ALG_SM3_256: +#if LIBSPDM_SM3_256_SUPPORT + return libspdm_hmac_sm3_256_new(); +#else + LIBSPDM_ASSERT(false); + return false; +#endif + default: + LIBSPDM_ASSERT(false); + return false; + } +} + +void libspdm_hmac_free(uint32_t base_hash_algo, void *hmac_ctx) +{ + switch (base_hash_algo) { + case SPDM_ALGORITHMS_BASE_HASH_ALGO_TPM_ALG_SHA_256: +#if LIBSPDM_SHA256_SUPPORT + libspdm_hmac_sha256_free(hmac_ctx); +#else + LIBSPDM_ASSERT(false); +#endif + break; + case SPDM_ALGORITHMS_BASE_HASH_ALGO_TPM_ALG_SHA_384: +#if LIBSPDM_SHA384_SUPPORT + libspdm_hmac_sha384_free(hmac_ctx); +#else + LIBSPDM_ASSERT(false); +#endif + break; + case SPDM_ALGORITHMS_BASE_HASH_ALGO_TPM_ALG_SHA_512: +#if LIBSPDM_SHA512_SUPPORT + libspdm_hmac_sha512_free(hmac_ctx); +#else + LIBSPDM_ASSERT(false); +#endif + break; + case SPDM_ALGORITHMS_BASE_HASH_ALGO_TPM_ALG_SHA3_256: +#if LIBSPDM_SHA3_256_SUPPORT + libspdm_hmac_sha3_256_free(hmac_ctx); +#else + LIBSPDM_ASSERT(false); +#endif + break; + case SPDM_ALGORITHMS_BASE_HASH_ALGO_TPM_ALG_SHA3_384: +#if LIBSPDM_SHA3_384_SUPPORT + libspdm_hmac_sha3_384_free(hmac_ctx); +#else + LIBSPDM_ASSERT(false); +#endif + break; + case SPDM_ALGORITHMS_BASE_HASH_ALGO_TPM_ALG_SHA3_512: +#if LIBSPDM_SHA3_512_SUPPORT + libspdm_hmac_sha3_512_free(hmac_ctx); +#else + LIBSPDM_ASSERT(false); +#endif + break; + case SPDM_ALGORITHMS_BASE_HASH_ALGO_TPM_ALG_SM3_256: +#if LIBSPDM_SM3_256_SUPPORT + libspdm_hmac_sm3_256_free(hmac_ctx); +#else + LIBSPDM_ASSERT(false); +#endif + break; + default: + LIBSPDM_ASSERT(false); + break; + } +} + +bool libspdm_hmac_init(uint32_t base_hash_algo, + void *hmac_ctx, const uint8_t *key, + size_t key_size) +{ + switch (base_hash_algo) { + case SPDM_ALGORITHMS_BASE_HASH_ALGO_TPM_ALG_SHA_256: +#if LIBSPDM_SHA256_SUPPORT + return libspdm_hmac_sha256_set_key(hmac_ctx, key, key_size); +#else + LIBSPDM_ASSERT(false); + return false; +#endif + case SPDM_ALGORITHMS_BASE_HASH_ALGO_TPM_ALG_SHA_384: +#if LIBSPDM_SHA384_SUPPORT + return libspdm_hmac_sha384_set_key(hmac_ctx, key, key_size); +#else + LIBSPDM_ASSERT(false); + return false; +#endif + case SPDM_ALGORITHMS_BASE_HASH_ALGO_TPM_ALG_SHA_512: +#if LIBSPDM_SHA512_SUPPORT + return libspdm_hmac_sha512_set_key(hmac_ctx, key, key_size); +#else + LIBSPDM_ASSERT(false); + return false; +#endif + case SPDM_ALGORITHMS_BASE_HASH_ALGO_TPM_ALG_SHA3_256: +#if LIBSPDM_SHA3_256_SUPPORT + return libspdm_hmac_sha3_256_set_key(hmac_ctx, key, key_size); +#else + LIBSPDM_ASSERT(false); + return false; +#endif + case SPDM_ALGORITHMS_BASE_HASH_ALGO_TPM_ALG_SHA3_384: +#if LIBSPDM_SHA3_384_SUPPORT + return libspdm_hmac_sha3_384_set_key(hmac_ctx, key, key_size); +#else + LIBSPDM_ASSERT(false); + return false; +#endif + case SPDM_ALGORITHMS_BASE_HASH_ALGO_TPM_ALG_SHA3_512: +#if LIBSPDM_SHA3_512_SUPPORT + return libspdm_hmac_sha3_512_set_key(hmac_ctx, key, key_size); +#else + LIBSPDM_ASSERT(false); + return false; +#endif + case SPDM_ALGORITHMS_BASE_HASH_ALGO_TPM_ALG_SM3_256: +#if LIBSPDM_SM3_256_SUPPORT + return libspdm_hmac_sm3_256_set_key(hmac_ctx, key, key_size); +#else + LIBSPDM_ASSERT(false); + return false; +#endif + default: + LIBSPDM_ASSERT(false); + return false; + } +} + +bool libspdm_hmac_duplicate(uint32_t base_hash_algo, const void *hmac_ctx, void *new_hmac_ctx) +{ + switch (base_hash_algo) { + case SPDM_ALGORITHMS_BASE_HASH_ALGO_TPM_ALG_SHA_256: +#if LIBSPDM_SHA256_SUPPORT + return libspdm_hmac_sha256_duplicate(hmac_ctx, new_hmac_ctx); +#else + LIBSPDM_ASSERT(false); + return false; +#endif + case SPDM_ALGORITHMS_BASE_HASH_ALGO_TPM_ALG_SHA_384: +#if LIBSPDM_SHA384_SUPPORT + return libspdm_hmac_sha384_duplicate(hmac_ctx, new_hmac_ctx); +#else + LIBSPDM_ASSERT(false); + return false; +#endif + case SPDM_ALGORITHMS_BASE_HASH_ALGO_TPM_ALG_SHA_512: +#if LIBSPDM_SHA512_SUPPORT + return libspdm_hmac_sha512_duplicate(hmac_ctx, new_hmac_ctx); +#else + LIBSPDM_ASSERT(false); + return false; +#endif + case SPDM_ALGORITHMS_BASE_HASH_ALGO_TPM_ALG_SHA3_256: +#if LIBSPDM_SHA3_256_SUPPORT + return libspdm_hmac_sha3_256_duplicate(hmac_ctx, new_hmac_ctx); +#else + LIBSPDM_ASSERT(false); + return false; +#endif + case SPDM_ALGORITHMS_BASE_HASH_ALGO_TPM_ALG_SHA3_384: +#if LIBSPDM_SHA3_384_SUPPORT + return libspdm_hmac_sha3_384_duplicate(hmac_ctx, new_hmac_ctx); +#else + LIBSPDM_ASSERT(false); + return false; +#endif + case SPDM_ALGORITHMS_BASE_HASH_ALGO_TPM_ALG_SHA3_512: +#if LIBSPDM_SHA3_512_SUPPORT + return libspdm_hmac_sha3_512_duplicate(hmac_ctx, new_hmac_ctx); +#else + LIBSPDM_ASSERT(false); + return false; +#endif + case SPDM_ALGORITHMS_BASE_HASH_ALGO_TPM_ALG_SM3_256: +#if LIBSPDM_SM3_256_SUPPORT + return libspdm_hmac_sm3_256_duplicate(hmac_ctx, new_hmac_ctx); +#else + LIBSPDM_ASSERT(false); + return false; +#endif + default: + LIBSPDM_ASSERT(false); + return false; + } +} + +bool libspdm_hmac_update(uint32_t base_hash_algo, + void *hmac_ctx, const void *data, + size_t data_size) +{ + switch (base_hash_algo) { + case SPDM_ALGORITHMS_BASE_HASH_ALGO_TPM_ALG_SHA_256: +#if LIBSPDM_SHA256_SUPPORT + return libspdm_hmac_sha256_update(hmac_ctx, data, data_size); +#else + LIBSPDM_ASSERT(false); + return false; +#endif + case SPDM_ALGORITHMS_BASE_HASH_ALGO_TPM_ALG_SHA_384: +#if LIBSPDM_SHA384_SUPPORT + return libspdm_hmac_sha384_update(hmac_ctx, data, data_size); +#else + LIBSPDM_ASSERT(false); + return false; +#endif + case SPDM_ALGORITHMS_BASE_HASH_ALGO_TPM_ALG_SHA_512: +#if LIBSPDM_SHA512_SUPPORT + return libspdm_hmac_sha512_update(hmac_ctx, data, data_size); +#else + LIBSPDM_ASSERT(false); + return false; +#endif + case SPDM_ALGORITHMS_BASE_HASH_ALGO_TPM_ALG_SHA3_256: +#if LIBSPDM_SHA3_256_SUPPORT + return libspdm_hmac_sha3_256_update(hmac_ctx, data, data_size); +#else + LIBSPDM_ASSERT(false); + return false; +#endif + case SPDM_ALGORITHMS_BASE_HASH_ALGO_TPM_ALG_SHA3_384: +#if LIBSPDM_SHA3_384_SUPPORT + return libspdm_hmac_sha3_384_update(hmac_ctx, data, data_size); +#else + LIBSPDM_ASSERT(false); + return false; +#endif + case SPDM_ALGORITHMS_BASE_HASH_ALGO_TPM_ALG_SHA3_512: +#if LIBSPDM_SHA3_512_SUPPORT + return libspdm_hmac_sha3_512_update(hmac_ctx, data, data_size); +#else + LIBSPDM_ASSERT(false); + return false; +#endif + case SPDM_ALGORITHMS_BASE_HASH_ALGO_TPM_ALG_SM3_256: +#if LIBSPDM_SM3_256_SUPPORT + return libspdm_hmac_sm3_256_update(hmac_ctx, data, data_size); +#else + LIBSPDM_ASSERT(false); + return false; +#endif + default: + LIBSPDM_ASSERT(false); + return false; + } +} + +bool libspdm_hmac_final(uint32_t base_hash_algo, void *hmac_ctx, uint8_t *hmac_value) +{ + switch (base_hash_algo) { + case SPDM_ALGORITHMS_BASE_HASH_ALGO_TPM_ALG_SHA_256: +#if LIBSPDM_SHA256_SUPPORT + return libspdm_hmac_sha256_final(hmac_ctx, hmac_value); +#else + LIBSPDM_ASSERT(false); + return false; +#endif + case SPDM_ALGORITHMS_BASE_HASH_ALGO_TPM_ALG_SHA_384: +#if LIBSPDM_SHA384_SUPPORT + return libspdm_hmac_sha384_final(hmac_ctx, hmac_value); +#else + LIBSPDM_ASSERT(false); + return false; +#endif + case SPDM_ALGORITHMS_BASE_HASH_ALGO_TPM_ALG_SHA_512: +#if LIBSPDM_SHA512_SUPPORT + return libspdm_hmac_sha512_final(hmac_ctx, hmac_value); +#else + LIBSPDM_ASSERT(false); + return false; +#endif + case SPDM_ALGORITHMS_BASE_HASH_ALGO_TPM_ALG_SHA3_256: +#if LIBSPDM_SHA3_256_SUPPORT + return libspdm_hmac_sha3_256_final(hmac_ctx, hmac_value); +#else + LIBSPDM_ASSERT(false); + return false; +#endif + case SPDM_ALGORITHMS_BASE_HASH_ALGO_TPM_ALG_SHA3_384: +#if LIBSPDM_SHA3_384_SUPPORT + return libspdm_hmac_sha3_384_final(hmac_ctx, hmac_value); +#else + LIBSPDM_ASSERT(false); + return false; +#endif + case SPDM_ALGORITHMS_BASE_HASH_ALGO_TPM_ALG_SHA3_512: +#if LIBSPDM_SHA3_512_SUPPORT + return libspdm_hmac_sha3_512_final(hmac_ctx, hmac_value); +#else + LIBSPDM_ASSERT(false); + return false; +#endif + case SPDM_ALGORITHMS_BASE_HASH_ALGO_TPM_ALG_SM3_256: +#if LIBSPDM_SM3_256_SUPPORT + return libspdm_hmac_sm3_256_final(hmac_ctx, hmac_value); +#else + LIBSPDM_ASSERT(false); + return false; +#endif + default: + LIBSPDM_ASSERT(false); + return false; + } +} + +bool libspdm_hmac_all(uint32_t base_hash_algo, const void *data, + size_t data_size, const uint8_t *key, + size_t key_size, uint8_t *hmac_value) +{ + switch (base_hash_algo) { + case SPDM_ALGORITHMS_BASE_HASH_ALGO_TPM_ALG_SHA_256: +#if LIBSPDM_SHA256_SUPPORT + return libspdm_hmac_sha256_all(data, data_size, key, key_size, hmac_value); +#else + LIBSPDM_ASSERT(false); + return false; +#endif + case SPDM_ALGORITHMS_BASE_HASH_ALGO_TPM_ALG_SHA_384: +#if LIBSPDM_SHA384_SUPPORT + return libspdm_hmac_sha384_all(data, data_size, key, key_size, hmac_value); +#else + LIBSPDM_ASSERT(false); + return false; +#endif + case SPDM_ALGORITHMS_BASE_HASH_ALGO_TPM_ALG_SHA_512: +#if LIBSPDM_SHA512_SUPPORT + return libspdm_hmac_sha512_all(data, data_size, key, key_size, hmac_value); +#else + LIBSPDM_ASSERT(false); + return false; +#endif + case SPDM_ALGORITHMS_BASE_HASH_ALGO_TPM_ALG_SHA3_256: +#if LIBSPDM_SHA3_256_SUPPORT + return libspdm_hmac_sha3_256_all(data, data_size, key, key_size, hmac_value); +#else + LIBSPDM_ASSERT(false); + return false; +#endif + case SPDM_ALGORITHMS_BASE_HASH_ALGO_TPM_ALG_SHA3_384: +#if LIBSPDM_SHA3_384_SUPPORT + return libspdm_hmac_sha3_384_all(data, data_size, key, key_size, hmac_value); +#else + LIBSPDM_ASSERT(false); + return false; +#endif + case SPDM_ALGORITHMS_BASE_HASH_ALGO_TPM_ALG_SHA3_512: +#if LIBSPDM_SHA3_512_SUPPORT + return libspdm_hmac_sha3_512_all(data, data_size, key, key_size, hmac_value); +#else + LIBSPDM_ASSERT(false); + return false; +#endif + case SPDM_ALGORITHMS_BASE_HASH_ALGO_TPM_ALG_SM3_256: +#if LIBSPDM_SM3_256_SUPPORT + return libspdm_hmac_sm3_256_all(data, data_size, key, key_size, hmac_value); +#else + LIBSPDM_ASSERT(false); + return false; +#endif + default: + LIBSPDM_ASSERT(false); + return false; + } +} diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/libraries/libspdm/2.3.1/library/spdm_crypt_lib/libspdm_crypt_rng.c nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/libraries/libspdm/2.3.1/library/spdm_crypt_lib/libspdm_crypt_rng.c --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/libraries/libspdm/2.3.1/library/spdm_crypt_lib/libspdm_crypt_rng.c 1970-01-01 00:00:00.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/libraries/libspdm/2.3.1/library/spdm_crypt_lib/libspdm_crypt_rng.c 2024-03-05 22:14:16.000000000 +0000 @@ -0,0 +1,15 @@ +/** + * Copyright Notice: + * Copyright 2021-2022 DMTF. All rights reserved. + * License: BSD 3-Clause License. For full text see link: https://github.com/DMTF/libspdm/blob/main/LICENSE.md + **/ + +#include "internal/libspdm_crypt_lib.h" + +bool libspdm_get_random_number(size_t size, uint8_t *rand) +{ + if (size == 0) { + return true; + } + return libspdm_random_bytes(rand, size); +} diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/libraries/libspdm/2.3.1/library/spdm_requester_lib/libspdm_req_common.c nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/libraries/libspdm/2.3.1/library/spdm_requester_lib/libspdm_req_common.c --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/libraries/libspdm/2.3.1/library/spdm_requester_lib/libspdm_req_common.c 1970-01-01 00:00:00.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/libraries/libspdm/2.3.1/library/spdm_requester_lib/libspdm_req_common.c 2024-03-05 22:14:16.000000000 +0000 @@ -0,0 +1,174 @@ +/** + * Copyright Notice: + * Copyright 2021-2022 DMTF. All rights reserved. + * License: BSD 3-Clause License. For full text see link: https://github.com/DMTF/libspdm/blob/main/LICENSE.md + **/ + +#include "internal/libspdm_requester_lib.h" + +uint16_t libspdm_allocate_req_session_id(libspdm_context_t *spdm_context) +{ + uint16_t req_session_id; + libspdm_session_info_t *session_info; + size_t index; + + session_info = spdm_context->session_info; + for (index = 0; index < LIBSPDM_MAX_SESSION_COUNT; index++) { + if ((session_info[index].session_id & 0xFFFF) == (INVALID_SESSION_ID & 0xFFFF)) { + req_session_id = (uint16_t)(0xFFFF - index); + return req_session_id; + } + } + + LIBSPDM_DEBUG((LIBSPDM_DEBUG_ERROR, "libspdm_allocate_req_session_id - MAX session_id\n")); + return (INVALID_SESSION_ID & 0xFFFF); +} + +libspdm_return_t libspdm_build_opaque_data_supported_version_data(libspdm_context_t *spdm_context, + size_t *data_out_size, + void *data_out) +{ + size_t final_data_size; + secured_message_general_opaque_data_table_header_t + *general_opaque_data_table_header; + spdm_general_opaque_data_table_header_t + *spdm_general_opaque_data_table_header; + secured_message_opaque_element_table_header_t + *opaque_element_table_header; + secured_message_opaque_element_supported_version_t + *opaque_element_support_version; + spdm_version_number_t *versions_list; + void *end; + + if (spdm_context->local_context.secured_message_version.spdm_version_count == 0) { + *data_out_size = 0; + return LIBSPDM_STATUS_SUCCESS; + } + + final_data_size = libspdm_get_opaque_data_supported_version_data_size(spdm_context); + if (*data_out_size < final_data_size) { + *data_out_size = final_data_size; + return LIBSPDM_STATUS_BUFFER_TOO_SMALL; + } + if (libspdm_get_connection_version (spdm_context) >= SPDM_MESSAGE_VERSION_12) { + spdm_general_opaque_data_table_header = data_out; + spdm_general_opaque_data_table_header->total_elements = 1; + libspdm_write_uint24(spdm_general_opaque_data_table_header->reserved, 0); + opaque_element_table_header = (void *)(spdm_general_opaque_data_table_header + 1); + } else { + general_opaque_data_table_header = data_out; + general_opaque_data_table_header->spec_id = SECURED_MESSAGE_OPAQUE_DATA_SPEC_ID; + general_opaque_data_table_header->opaque_version = SECURED_MESSAGE_OPAQUE_VERSION; + general_opaque_data_table_header->total_elements = 1; + general_opaque_data_table_header->reserved = 0; + opaque_element_table_header = (void *)(general_opaque_data_table_header + 1); + } + + opaque_element_table_header->id = SPDM_REGISTRY_ID_DMTF; + opaque_element_table_header->vendor_len = 0; + opaque_element_table_header->opaque_element_data_len = + sizeof(secured_message_opaque_element_supported_version_t) + + sizeof(spdm_version_number_t) * + spdm_context->local_context.secured_message_version.spdm_version_count; + + opaque_element_support_version = (void *)(opaque_element_table_header + 1); + opaque_element_support_version->sm_data_version = + SECURED_MESSAGE_OPAQUE_ELEMENT_SMDATA_DATA_VERSION; + opaque_element_support_version->sm_data_id = + SECURED_MESSAGE_OPAQUE_ELEMENT_SMDATA_ID_SUPPORTED_VERSION; + opaque_element_support_version->version_count = + spdm_context->local_context.secured_message_version.spdm_version_count; + + versions_list = (void *)(opaque_element_support_version + 1); + libspdm_copy_mem(versions_list, + *data_out_size - ((uint8_t*)versions_list - (uint8_t*)data_out), + spdm_context->local_context.secured_message_version.spdm_version, + spdm_context->local_context.secured_message_version.spdm_version_count * + sizeof(spdm_version_number_t)); + + /* Zero Padding. *data_out_size does not need to be changed, because data is 0 padded */ + end = versions_list + spdm_context->local_context.secured_message_version.spdm_version_count; + libspdm_zero_mem(end, (size_t)data_out + final_data_size - (size_t)end); + + return LIBSPDM_STATUS_SUCCESS; +} + +/** + * Process opaque data version selection. + * + * This function should be called in KEY_EXCHANGE/PSK_EXCHANGE response parsing in requester. + * + * @param data_in_size size in bytes of the data_in. + * @param data_in A pointer to the buffer to store the opaque data version selection. + * + * @retval RETURN_SUCCESS The opaque data version selection is processed successfully. + * @retval RETURN_UNSUPPORTED The data_in is NOT opaque data version selection. + **/ +libspdm_return_t libspdm_process_opaque_data_version_selection_data(libspdm_context_t *spdm_context, + size_t data_in_size, + void *data_in) +{ + const secured_message_opaque_element_table_header_t + *opaque_element_table_header; + const secured_message_opaque_element_version_selection_t + *opaque_element_version_section; + + bool result; + uint8_t secured_message_version_index; + const void *get_element_ptr; + size_t get_element_len; + + result = false; + get_element_ptr = NULL; + + if (spdm_context->local_context.secured_message_version.spdm_version_count == 0) { + return LIBSPDM_STATUS_SUCCESS; + } + + result = libspdm_get_element_from_opaque_data( + spdm_context, data_in_size, + data_in, SPDM_REGISTRY_ID_DMTF, + SECURED_MESSAGE_OPAQUE_ELEMENT_SMDATA_ID_VERSION_SELECTION, + &get_element_ptr, &get_element_len); + if ((!result) || (get_element_ptr == NULL)) { + LIBSPDM_DEBUG((LIBSPDM_DEBUG_INFO,"get element error!\n")); + return LIBSPDM_STATUS_INVALID_MSG_FIELD; + } + + opaque_element_table_header = (const secured_message_opaque_element_table_header_t*) + get_element_ptr; + + /*check for selection vesion data*/ + if ((opaque_element_table_header->vendor_len != 0) || + (opaque_element_table_header->opaque_element_data_len != + sizeof(secured_message_opaque_element_version_selection_t))) { + return LIBSPDM_STATUS_INVALID_MSG_FIELD; + } + opaque_element_version_section = (const void *)(opaque_element_table_header + 1); + + if ((const uint8_t *)opaque_element_version_section + + sizeof(secured_message_opaque_element_version_selection_t) > + (const uint8_t *)opaque_element_table_header + get_element_len) { + return LIBSPDM_STATUS_INVALID_MSG_FIELD; + } + + for (secured_message_version_index = 0; + secured_message_version_index < + spdm_context->local_context.secured_message_version.spdm_version_count; + secured_message_version_index++) { + if (libspdm_get_version_from_version_number(opaque_element_version_section-> + selected_version) + == + libspdm_get_version_from_version_number( + spdm_context->local_context.secured_message_version.spdm_version[ + secured_message_version_index])) { + libspdm_copy_mem(&(spdm_context->connection_info.secured_message_version), + sizeof(spdm_context->connection_info.secured_message_version), + &(opaque_element_version_section->selected_version), + sizeof(spdm_version_number_t)); + return LIBSPDM_STATUS_SUCCESS; + } + } + + return LIBSPDM_STATUS_UNSUPPORTED_CAP; +} diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/libraries/libspdm/2.3.1/library/spdm_requester_lib/libspdm_req_communication.c nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/libraries/libspdm/2.3.1/library/spdm_requester_lib/libspdm_req_communication.c --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/libraries/libspdm/2.3.1/library/spdm_requester_lib/libspdm_req_communication.c 1970-01-01 00:00:00.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/libraries/libspdm/2.3.1/library/spdm_requester_lib/libspdm_req_communication.c 2024-03-05 22:14:16.000000000 +0000 @@ -0,0 +1,368 @@ +/** + * Copyright Notice: + * Copyright 2021-2022 DMTF. All rights reserved. + * License: BSD 3-Clause License. For full text see link: https://github.com/DMTF/libspdm/blob/main/LICENSE.md + **/ + +#include "internal/libspdm_requester_lib.h" + +libspdm_return_t libspdm_init_connection(void *context, bool get_version_only) +{ + libspdm_return_t status; + libspdm_context_t *spdm_context; + + spdm_context = context; + + status = libspdm_get_version(spdm_context, NULL, NULL); + if (LIBSPDM_STATUS_IS_ERROR(status)) { + return status; + } + + if (!get_version_only) { + status = libspdm_get_capabilities(spdm_context); + if (LIBSPDM_STATUS_IS_ERROR(status)) { + return status; + } + status = libspdm_negotiate_algorithms(spdm_context); + if (LIBSPDM_STATUS_IS_ERROR(status)) { + return status; + } + } + return LIBSPDM_STATUS_SUCCESS; +} + +#if (LIBSPDM_ENABLE_CAPABILITY_KEY_EX_CAP) || (LIBSPDM_ENABLE_CAPABILITY_PSK_EX_CAP) +libspdm_return_t libspdm_start_session(void *context, bool use_psk, + uint8_t measurement_hash_type, + uint8_t slot_id, + uint8_t session_policy, + uint32_t *session_id, + uint8_t *heartbeat_period, + void *measurement_hash) +{ + libspdm_return_t status; + libspdm_context_t *spdm_context; + + #if LIBSPDM_ENABLE_CAPABILITY_KEY_EX_CAP + libspdm_session_info_t *session_info; + uint8_t req_slot_id_param; + #endif /* LIBSPDM_ENABLE_CAPABILITY_KEY_EX_CAP*/ + + spdm_context = context; + status = LIBSPDM_STATUS_UNSUPPORTED_CAP; + + if (!use_psk) { + #if LIBSPDM_ENABLE_CAPABILITY_KEY_EX_CAP + status = libspdm_send_receive_key_exchange( + spdm_context, measurement_hash_type, slot_id, session_policy, + session_id, heartbeat_period, &req_slot_id_param, + measurement_hash); + if (LIBSPDM_STATUS_IS_ERROR(status)) { + LIBSPDM_DEBUG((LIBSPDM_DEBUG_INFO, + "libspdm_start_session - libspdm_send_receive_key_exchange - %p\n", + status)); + return status; + } + + session_info = libspdm_get_session_info_via_session_id(spdm_context, *session_id); + if (session_info == NULL) { + LIBSPDM_ASSERT(false); + return LIBSPDM_STATUS_INVALID_STATE_LOCAL; + } + + switch (session_info->mut_auth_requested) { + case 0: + break; + case SPDM_KEY_EXCHANGE_RESPONSE_MUT_AUTH_REQUESTED: +#if !(LIBSPDM_ENABLE_CAPABILITY_MUT_AUTH_CAP) + LIBSPDM_DEBUG((LIBSPDM_DEBUG_INFO, + "libspdm_start_session - unsupported mut_auth_requested - 0x%x\n", + session_info->mut_auth_requested)); + return LIBSPDM_STATUS_INVALID_MSG_FIELD; +#endif + break; + case SPDM_KEY_EXCHANGE_RESPONSE_MUT_AUTH_REQUESTED_WITH_ENCAP_REQUEST: + case SPDM_KEY_EXCHANGE_RESPONSE_MUT_AUTH_REQUESTED_WITH_GET_DIGESTS: +#if (LIBSPDM_ENABLE_CAPABILITY_MUT_AUTH_CAP) || (LIBSPDM_ENABLE_CAPABILITY_ENCAP_CAP) + status = libspdm_encapsulated_request( + spdm_context, session_id, + session_info->mut_auth_requested, + &req_slot_id_param); + LIBSPDM_DEBUG((LIBSPDM_DEBUG_INFO, + "libspdm_start_session - libspdm_encapsulated_request - %p\n", status)); + if (LIBSPDM_STATUS_IS_ERROR(status)) { + return status; + } +#else + LIBSPDM_DEBUG((LIBSPDM_DEBUG_INFO, + "libspdm_start_session - unsupported mut_auth_requested - 0x%x\n", + session_info->mut_auth_requested)); + return LIBSPDM_STATUS_INVALID_MSG_FIELD; +#endif + break; + default: + LIBSPDM_DEBUG((LIBSPDM_DEBUG_INFO, + "libspdm_start_session - unknown mut_auth_requested - 0x%x\n", + session_info->mut_auth_requested)); + return LIBSPDM_STATUS_INVALID_MSG_FIELD; + } + + if (req_slot_id_param == 0xF) { + req_slot_id_param = 0xFF; + } + status = libspdm_send_receive_finish(spdm_context, *session_id, req_slot_id_param); + LIBSPDM_DEBUG((LIBSPDM_DEBUG_INFO, + "libspdm_start_session - libspdm_send_receive_finish - %p\n", status)); + #else /* LIBSPDM_ENABLE_CAPABILITY_KEY_EX_CAP*/ + LIBSPDM_ASSERT(false); + return LIBSPDM_STATUS_UNSUPPORTED_CAP; + #endif /* LIBSPDM_ENABLE_CAPABILITY_KEY_EX_CAP*/ + } else { + #if LIBSPDM_ENABLE_CAPABILITY_PSK_EX_CAP + status = libspdm_send_receive_psk_exchange( + spdm_context, measurement_hash_type, session_policy, session_id, + heartbeat_period, measurement_hash); + if (LIBSPDM_STATUS_IS_ERROR(status)) { + LIBSPDM_DEBUG((LIBSPDM_DEBUG_INFO, + "libspdm_start_session - libspdm_send_receive_psk_exchange - %p\n", + status)); + return status; + } + + /* send PSK_FINISH only if Responder supports context.*/ + if (libspdm_is_capabilities_flag_supported( + spdm_context, true, 0, + SPDM_GET_CAPABILITIES_RESPONSE_FLAGS_PSK_CAP_RESPONDER_WITH_CONTEXT)) { + status = libspdm_send_receive_psk_finish(spdm_context, *session_id); + LIBSPDM_DEBUG((LIBSPDM_DEBUG_INFO, + "libspdm_start_session - libspdm_send_receive_psk_finish - %p\n", + status)); + } + #endif /* LIBSPDM_ENABLE_CAPABILITY_PSK_EX_CAP*/ + } + return status; +} + +libspdm_return_t libspdm_start_session_ex(void *context, bool use_psk, + uint8_t measurement_hash_type, + uint8_t slot_id, + uint8_t session_policy, + uint32_t *session_id, + uint8_t *heartbeat_period, + void *measurement_hash, + const void *requester_random_in, + size_t requester_random_in_size, + void *requester_random, + size_t *requester_random_size, + void *responder_random, + size_t *responder_random_size) +{ + libspdm_return_t status; + libspdm_context_t *spdm_context; + + #if LIBSPDM_ENABLE_CAPABILITY_KEY_EX_CAP + libspdm_session_info_t *session_info; + uint8_t req_slot_id_param; + #endif /* LIBSPDM_ENABLE_CAPABILITY_KEY_EX_CAP */ + + spdm_context = context; + status = LIBSPDM_STATUS_UNSUPPORTED_CAP; + + if (!use_psk) { + #if LIBSPDM_ENABLE_CAPABILITY_KEY_EX_CAP + LIBSPDM_ASSERT ( + requester_random_in_size == 0 || requester_random_in_size == SPDM_RANDOM_DATA_SIZE); + LIBSPDM_ASSERT ( + requester_random_size == NULL || *requester_random_size == SPDM_RANDOM_DATA_SIZE); + LIBSPDM_ASSERT ( + responder_random_size == NULL || *responder_random_size == SPDM_RANDOM_DATA_SIZE); + status = libspdm_send_receive_key_exchange_ex( + spdm_context, measurement_hash_type, slot_id, session_policy, + session_id, heartbeat_period, &req_slot_id_param, + measurement_hash, requester_random_in, + requester_random, responder_random); + if (LIBSPDM_STATUS_IS_ERROR(status)) { + LIBSPDM_DEBUG((LIBSPDM_DEBUG_INFO, + "libspdm_start_session - libspdm_send_receive_key_exchange - %p\n", + status)); + return status; + } + + session_info = libspdm_get_session_info_via_session_id(spdm_context, *session_id); + if (session_info == NULL) { + LIBSPDM_ASSERT(false); + return LIBSPDM_STATUS_INVALID_STATE_LOCAL; + } + + switch (session_info->mut_auth_requested) { + case 0: + break; + case SPDM_KEY_EXCHANGE_RESPONSE_MUT_AUTH_REQUESTED: +#if !(LIBSPDM_ENABLE_CAPABILITY_MUT_AUTH_CAP) + LIBSPDM_DEBUG((LIBSPDM_DEBUG_INFO, + "libspdm_start_session - unsupported mut_auth_requested - 0x%x\n", + session_info->mut_auth_requested)); + return LIBSPDM_STATUS_INVALID_MSG_FIELD; +#endif + break; + case SPDM_KEY_EXCHANGE_RESPONSE_MUT_AUTH_REQUESTED_WITH_ENCAP_REQUEST: + case SPDM_KEY_EXCHANGE_RESPONSE_MUT_AUTH_REQUESTED_WITH_GET_DIGESTS: +#if (LIBSPDM_ENABLE_CAPABILITY_MUT_AUTH_CAP) || (LIBSPDM_ENABLE_CAPABILITY_ENCAP_CAP) + status = libspdm_encapsulated_request( + spdm_context, session_id, + session_info->mut_auth_requested, + &req_slot_id_param); + LIBSPDM_DEBUG((LIBSPDM_DEBUG_INFO, + "libspdm_start_session - libspdm_encapsulated_request - %p\n", status)); + if (LIBSPDM_STATUS_IS_ERROR(status)) { + return status; + } +#else + LIBSPDM_DEBUG((LIBSPDM_DEBUG_INFO, + "libspdm_start_session - unsupported mut_auth_requested - 0x%x\n", + session_info->mut_auth_requested)); + return LIBSPDM_STATUS_INVALID_MSG_FIELD; +#endif + break; + default: + LIBSPDM_DEBUG((LIBSPDM_DEBUG_INFO, + "libspdm_start_session - unknown mut_auth_requested - 0x%x\n", + session_info->mut_auth_requested)); + return LIBSPDM_STATUS_INVALID_MSG_FIELD; + } + + if (req_slot_id_param == 0xF) { + req_slot_id_param = 0xFF; + } + status = libspdm_send_receive_finish(spdm_context, *session_id, req_slot_id_param); + LIBSPDM_DEBUG((LIBSPDM_DEBUG_INFO, + "libspdm_start_session - libspdm_send_receive_finish - %p\n", status)); + #else /* LIBSPDM_ENABLE_CAPABILITY_KEY_EX_CAP*/ + LIBSPDM_ASSERT(false); + return LIBSPDM_STATUS_UNSUPPORTED_CAP; + #endif /* LIBSPDM_ENABLE_CAPABILITY_KEY_EX_CAP*/ + } else { + #if LIBSPDM_ENABLE_CAPABILITY_PSK_EX_CAP + status = libspdm_send_receive_psk_exchange_ex( + spdm_context, measurement_hash_type, session_policy, session_id, + heartbeat_period, measurement_hash, + requester_random_in, requester_random_in_size, + requester_random, requester_random_size, + responder_random, responder_random_size); + if (LIBSPDM_STATUS_IS_ERROR(status)) { + LIBSPDM_DEBUG((LIBSPDM_DEBUG_INFO, + "libspdm_start_session - libspdm_send_receive_psk_exchange - %p\n", + status)); + return status; + } + + /* send PSK_FINISH only if Responder supports context.*/ + if (libspdm_is_capabilities_flag_supported( + spdm_context, true, 0, + SPDM_GET_CAPABILITIES_RESPONSE_FLAGS_PSK_CAP_RESPONDER_WITH_CONTEXT)) { + status = libspdm_send_receive_psk_finish(spdm_context, *session_id); + LIBSPDM_DEBUG((LIBSPDM_DEBUG_INFO, + "libspdm_start_session - libspdm_send_receive_psk_finish - %p\n", + status)); + } + #else /* LIBSPDM_ENABLE_CAPABILITY_PSK_EX_CAP*/ + LIBSPDM_ASSERT(false); + return LIBSPDM_STATUS_UNSUPPORTED_CAP; + #endif /* LIBSPDM_ENABLE_CAPABILITY_PSK_EX_CAP*/ + } + + return status; +} + +libspdm_return_t libspdm_stop_session(void *context, uint32_t session_id, + uint8_t end_session_attributes) +{ + libspdm_return_t status; + libspdm_context_t *spdm_context; + + spdm_context = context; + + status = libspdm_send_receive_end_session(spdm_context, session_id, end_session_attributes); + LIBSPDM_DEBUG((LIBSPDM_DEBUG_INFO, "libspdm_stop_session - %p\n", status)); + + return status; +} +#endif /* (LIBSPDM_ENABLE_CAPABILITY_KEY_EX_CAP) || (LIBSPDM_ENABLE_CAPABILITY_PSK_EX_CAP) */ + +libspdm_return_t libspdm_send_receive_data(void *context, const uint32_t *session_id, + bool is_app_message, + const void *request, size_t request_size, + void *response, + size_t *response_size) +{ + libspdm_return_t status; + libspdm_context_t *spdm_context; + spdm_message_header_t *spdm_request; + size_t spdm_request_size; + spdm_error_response_t *spdm_response; + size_t spdm_response_size; + uint8_t *message; + size_t message_size; + size_t transport_header_size; + + spdm_context = context; + spdm_response = response; + + transport_header_size = spdm_context->transport_get_header_size(spdm_context); + status = libspdm_acquire_sender_buffer (spdm_context, &message_size, (void **)&message); + if (LIBSPDM_STATUS_IS_ERROR(status)) { + return status; + } + LIBSPDM_ASSERT (message_size >= transport_header_size); + spdm_request = (void *)(message + transport_header_size); + spdm_request_size = message_size - transport_header_size; + libspdm_copy_mem (spdm_request, spdm_request_size, request, request_size); + spdm_request_size = request_size; + + status = libspdm_send_request(spdm_context, session_id, is_app_message, + spdm_request_size, spdm_request); + if (LIBSPDM_STATUS_IS_ERROR(status)) { + libspdm_release_sender_buffer (spdm_context); + return status; + } + libspdm_release_sender_buffer (spdm_context); + + /* receive */ + + status = libspdm_acquire_receiver_buffer (spdm_context, &message_size, (void **)&message); + if (LIBSPDM_STATUS_IS_ERROR(status)) { + return status; + } + LIBSPDM_ASSERT (message_size >= transport_header_size); + spdm_response = (void *)(message); + spdm_response_size = message_size; + + status = libspdm_receive_response(spdm_context, session_id, is_app_message, + &spdm_response_size, (void **)&spdm_response); + if (LIBSPDM_STATUS_IS_ERROR(status)) { + libspdm_release_receiver_buffer (spdm_context); + return status; + } + + if (spdm_response->header.request_response_code == SPDM_ERROR) { + if ((spdm_response->header.param1 == SPDM_ERROR_CODE_DECRYPT_ERROR) && + (session_id != NULL)) { + libspdm_free_session_id(spdm_context, *session_id); + libspdm_release_receiver_buffer (spdm_context); + return LIBSPDM_STATUS_SESSION_MSG_ERROR; + } + } + + if (*response_size >= spdm_response_size) { + libspdm_copy_mem (response, *response_size, spdm_response, spdm_response_size); + *response_size = spdm_response_size; + } else { + *response_size = spdm_response_size; + libspdm_release_receiver_buffer (spdm_context); + return LIBSPDM_STATUS_BUFFER_TOO_SMALL; + } + + libspdm_release_receiver_buffer (spdm_context); + + return LIBSPDM_STATUS_SUCCESS; +} diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/libraries/libspdm/2.3.1/library/spdm_requester_lib/libspdm_req_end_session.c nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/libraries/libspdm/2.3.1/library/spdm_requester_lib/libspdm_req_end_session.c --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/libraries/libspdm/2.3.1/library/spdm_requester_lib/libspdm_req_end_session.c 1970-01-01 00:00:00.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/libraries/libspdm/2.3.1/library/spdm_requester_lib/libspdm_req_end_session.c 2024-03-05 22:14:16.000000000 +0000 @@ -0,0 +1,165 @@ +/** + * Copyright Notice: + * Copyright 2021-2022 DMTF. All rights reserved. + * License: BSD 3-Clause License. For full text see link: https://github.com/DMTF/libspdm/blob/main/LICENSE.md + **/ + +#include "internal/libspdm_requester_lib.h" + +#if (LIBSPDM_ENABLE_CAPABILITY_KEY_EX_CAP) || (LIBSPDM_ENABLE_CAPABILITY_PSK_EX_CAP) + +#pragma pack(1) +typedef struct { + spdm_message_header_t header; + uint8_t dummy_data[sizeof(spdm_error_data_response_not_ready_t)]; +} libspdm_end_session_response_mine_t; +#pragma pack() + +/** + * This function sends END_SESSION and receives END_SESSION_ACK for SPDM session end. + * + * @param spdm_context A pointer to the SPDM context. + * @param session_id session_id to the END_SESSION request. + * @param end_session_attributes end_session_attributes to the END_SESSION_ACK request. + * + * @retval RETURN_SUCCESS The END_SESSION is sent and the END_SESSION_ACK is received. + * @retval RETURN_DEVICE_ERROR A device error occurs when communicates with the device. + **/ +static libspdm_return_t libspdm_try_send_receive_end_session(libspdm_context_t *spdm_context, + uint32_t session_id, + uint8_t end_session_attributes) +{ + libspdm_return_t status; + spdm_end_session_request_t *spdm_request; + size_t spdm_request_size; + libspdm_end_session_response_mine_t *spdm_response; + size_t spdm_response_size; + libspdm_session_info_t *session_info; + libspdm_session_state_t session_state; + uint8_t *message; + size_t message_size; + size_t transport_header_size; + + if (spdm_context->connection_info.connection_state < + LIBSPDM_CONNECTION_STATE_NEGOTIATED) { + return LIBSPDM_STATUS_INVALID_STATE_LOCAL; + } + session_info = libspdm_get_session_info_via_session_id(spdm_context, session_id); + if (session_info == NULL) { + LIBSPDM_ASSERT(false); + return LIBSPDM_STATUS_INVALID_STATE_LOCAL; + } + session_state = libspdm_secured_message_get_session_state( + session_info->secured_message_context); + if (session_state != LIBSPDM_SESSION_STATE_ESTABLISHED) { + return LIBSPDM_STATUS_INVALID_STATE_LOCAL; + } + + if (!libspdm_is_capabilities_flag_supported( + spdm_context, true, 0, + SPDM_GET_CAPABILITIES_RESPONSE_FLAGS_CACHE_CAP)) { + end_session_attributes = 0; + } + + transport_header_size = spdm_context->transport_get_header_size(spdm_context); + status = libspdm_acquire_sender_buffer (spdm_context, &message_size, (void **)&message); + if (LIBSPDM_STATUS_IS_ERROR(status)) { + return status; + } + LIBSPDM_ASSERT (message_size >= transport_header_size); + spdm_request = (void *)(message + transport_header_size); + spdm_request_size = message_size - transport_header_size; + + spdm_request->header.spdm_version = libspdm_get_connection_version (spdm_context); + spdm_request->header.request_response_code = SPDM_END_SESSION; + spdm_request->header.param1 = end_session_attributes; + spdm_request->header.param2 = 0; + + spdm_request_size = sizeof(spdm_end_session_request_t); + status = libspdm_send_spdm_request(spdm_context, &session_id, spdm_request_size, spdm_request); + if (LIBSPDM_STATUS_IS_ERROR(status)) { + libspdm_release_sender_buffer (spdm_context); + return status; + } + + libspdm_reset_message_buffer_via_request_code(spdm_context, session_info, SPDM_END_SESSION); + + libspdm_release_sender_buffer (spdm_context); + spdm_request = (void *)spdm_context->last_spdm_request; + + /* receive */ + + status = libspdm_acquire_receiver_buffer (spdm_context, &message_size, (void **)&message); + if (LIBSPDM_STATUS_IS_ERROR(status)) { + return status; + } + LIBSPDM_ASSERT (message_size >= transport_header_size); + spdm_response = (void *)(message); + spdm_response_size = message_size; + + libspdm_zero_mem(spdm_response, spdm_response_size); + status = libspdm_receive_spdm_response( + spdm_context, &session_id, &spdm_response_size, (void **)&spdm_response); + if (LIBSPDM_STATUS_IS_ERROR(status)) { + goto receive_done; + } + if (spdm_response_size < sizeof(spdm_message_header_t)) { + status = LIBSPDM_STATUS_INVALID_MSG_SIZE; + goto receive_done; + } + if (spdm_response->header.spdm_version != spdm_request->header.spdm_version) { + status = LIBSPDM_STATUS_INVALID_MSG_FIELD; + goto receive_done; + } + if (spdm_response->header.request_response_code == SPDM_ERROR) { + status = libspdm_handle_error_response_main( + spdm_context, &session_id, &spdm_response_size, + (void **)&spdm_response, SPDM_END_SESSION, SPDM_END_SESSION_ACK, + sizeof(libspdm_end_session_response_mine_t)); + if (LIBSPDM_STATUS_IS_ERROR(status)) { + goto receive_done; + } + } else if (spdm_response->header.request_response_code != SPDM_END_SESSION_ACK) { + status = LIBSPDM_STATUS_INVALID_MSG_FIELD; + goto receive_done; + } + if (spdm_response_size != sizeof(spdm_end_session_response_t)) { + status = LIBSPDM_STATUS_INVALID_MSG_SIZE; + goto receive_done; + } + + session_info->end_session_attributes = end_session_attributes; + + libspdm_secured_message_set_session_state( + session_info->secured_message_context, + LIBSPDM_SESSION_STATE_NOT_STARTED); + libspdm_free_session_id(spdm_context, session_id); + + status = LIBSPDM_STATUS_SUCCESS; + +receive_done: + libspdm_release_receiver_buffer (spdm_context); + return status; +} + +libspdm_return_t libspdm_send_receive_end_session(libspdm_context_t *spdm_context, + uint32_t session_id, + uint8_t end_session_attributes) +{ + size_t retry; + libspdm_return_t status; + + spdm_context->crypto_request = true; + retry = spdm_context->retry_times; + do { + status = libspdm_try_send_receive_end_session( + spdm_context, session_id, end_session_attributes); + if (LIBSPDM_STATUS_BUSY_PEER != status) { + return status; + } + } while (retry-- != 0); + + return status; +} + +#endif /* (LIBSPDM_ENABLE_CAPABILITY_KEY_EX_CAP) || (LIBSPDM_ENABLE_CAPABILITY_PSK_EX_CAP) */ diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/libraries/libspdm/2.3.1/library/spdm_requester_lib/libspdm_req_finish.c nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/libraries/libspdm/2.3.1/library/spdm_requester_lib/libspdm_req_finish.c --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/libraries/libspdm/2.3.1/library/spdm_requester_lib/libspdm_req_finish.c 1970-01-01 00:00:00.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/libraries/libspdm/2.3.1/library/spdm_requester_lib/libspdm_req_finish.c 2024-03-05 22:14:16.000000000 +0000 @@ -0,0 +1,576 @@ +/** + * Copyright Notice: + * Copyright 2021-2022 DMTF. All rights reserved. + * License: BSD 3-Clause License. For full text see link: https://github.com/DMTF/libspdm/blob/main/LICENSE.md + **/ + +#include "internal/libspdm_requester_lib.h" + +#if LIBSPDM_ENABLE_CAPABILITY_KEY_EX_CAP + +#pragma pack(1) +typedef struct { + spdm_message_header_t header; + uint8_t signature[LIBSPDM_MAX_ASYM_KEY_SIZE]; + uint8_t verify_data[LIBSPDM_MAX_HASH_SIZE]; +} libspdm_finish_request_mine_t; + +typedef struct { + spdm_message_header_t header; + uint8_t verify_data[LIBSPDM_MAX_HASH_SIZE]; +} libspdm_finish_response_mine_t; +#pragma pack() + +bool libspdm_verify_finish_rsp_hmac(libspdm_context_t *spdm_context, + libspdm_session_info_t *session_info, + const void *hmac_data, size_t hmac_data_size) +{ + size_t hash_size; + uint8_t calc_hmac_data[LIBSPDM_MAX_HASH_SIZE]; + bool result; +#if LIBSPDM_RECORD_TRANSCRIPT_DATA_SUPPORT + uint8_t *cert_chain_buffer; + size_t cert_chain_buffer_size; + uint8_t *mut_cert_chain_buffer; + size_t mut_cert_chain_buffer_size; + uint8_t th_curr_data[LIBSPDM_MAX_MESSAGE_BUFFER_SIZE]; + size_t th_curr_data_size; + uint8_t hash_data[LIBSPDM_MAX_HASH_SIZE]; +#endif + + hash_size = libspdm_get_hash_size(spdm_context->connection_info.algorithm.base_hash_algo); + LIBSPDM_ASSERT(hash_size == hmac_data_size); + +#if LIBSPDM_RECORD_TRANSCRIPT_DATA_SUPPORT + result = libspdm_get_peer_cert_chain_buffer( + spdm_context, (const void **)&cert_chain_buffer, &cert_chain_buffer_size); + if (!result) { + return false; + } + + if (session_info->mut_auth_requested) { + result = libspdm_get_local_cert_chain_buffer( + spdm_context, (const void **)&mut_cert_chain_buffer, + &mut_cert_chain_buffer_size); + if (!result) { + return false; + } + } else { + mut_cert_chain_buffer = NULL; + mut_cert_chain_buffer_size = 0; + } + th_curr_data_size = sizeof(th_curr_data); + result = libspdm_calculate_th_for_finish( + spdm_context, session_info, cert_chain_buffer, + cert_chain_buffer_size, mut_cert_chain_buffer, + mut_cert_chain_buffer_size, &th_curr_data_size, th_curr_data); + if (!result) { + return false; + } + + result = libspdm_hash_all (spdm_context->connection_info.algorithm.base_hash_algo, + th_curr_data, th_curr_data_size, hash_data); + if (!result) { + return false; + } + + result = libspdm_hmac_all_with_response_finished_key( + session_info->secured_message_context, hash_data, + hash_size, calc_hmac_data); + if (!result) { + return false; + } +#else + result = libspdm_calculate_th_hmac_for_finish_rsp( + spdm_context, session_info, &hash_size, calc_hmac_data); + if (!result) { + return false; + } +#endif + LIBSPDM_DEBUG((LIBSPDM_DEBUG_INFO, "th_curr hmac - ")); + LIBSPDM_INTERNAL_DUMP_DATA(calc_hmac_data, hash_size); + LIBSPDM_DEBUG((LIBSPDM_DEBUG_INFO, "\n")); + + if (libspdm_const_compare_mem(calc_hmac_data, hmac_data, hash_size) != 0) { + LIBSPDM_DEBUG((LIBSPDM_DEBUG_INFO, "!!! verify_finish_rsp_hmac - FAIL !!!\n")); + return false; + } + LIBSPDM_DEBUG((LIBSPDM_DEBUG_INFO, "!!! verify_finish_rsp_hmac - PASS !!!\n")); + + return true; +} + +bool libspdm_generate_finish_req_hmac(libspdm_context_t *spdm_context, + libspdm_session_info_t *session_info, + void *hmac) +{ + size_t hash_size; + uint8_t calc_hmac_data[LIBSPDM_MAX_HASH_SIZE]; + bool result; +#if LIBSPDM_RECORD_TRANSCRIPT_DATA_SUPPORT + uint8_t *cert_chain_buffer; + size_t cert_chain_buffer_size; + uint8_t *mut_cert_chain_buffer; + size_t mut_cert_chain_buffer_size; + uint8_t th_curr_data[LIBSPDM_MAX_MESSAGE_BUFFER_SIZE]; + size_t th_curr_data_size; + uint8_t hash_data[LIBSPDM_MAX_HASH_SIZE]; +#endif + + hash_size = libspdm_get_hash_size(spdm_context->connection_info.algorithm.base_hash_algo); + +#if LIBSPDM_RECORD_TRANSCRIPT_DATA_SUPPORT + result = libspdm_get_peer_cert_chain_buffer( + spdm_context, (const void **)&cert_chain_buffer, &cert_chain_buffer_size); + if (!result) { + return false; + } + + if (session_info->mut_auth_requested) { + result = libspdm_get_local_cert_chain_buffer( + spdm_context, (const void **)&mut_cert_chain_buffer, + &mut_cert_chain_buffer_size); + if (!result) { + return false; + } + } else { + mut_cert_chain_buffer = NULL; + mut_cert_chain_buffer_size = 0; + } + + th_curr_data_size = sizeof(th_curr_data); + result = libspdm_calculate_th_for_finish( + spdm_context, session_info, cert_chain_buffer, + cert_chain_buffer_size, mut_cert_chain_buffer, + mut_cert_chain_buffer_size, &th_curr_data_size, th_curr_data); + if (!result) { + return false; + } + + result = libspdm_hash_all (spdm_context->connection_info.algorithm.base_hash_algo, + th_curr_data, th_curr_data_size, hash_data); + if (!result) { + return false; + } + + result = libspdm_hmac_all_with_request_finished_key( + session_info->secured_message_context, hash_data, + hash_size, calc_hmac_data); + if (!result) { + return false; + } +#else + result = libspdm_calculate_th_hmac_for_finish_req( + spdm_context, session_info, &hash_size, calc_hmac_data); + if (!result) { + return false; + } +#endif + LIBSPDM_DEBUG((LIBSPDM_DEBUG_INFO, "th_curr hmac - ")); + LIBSPDM_INTERNAL_DUMP_DATA(calc_hmac_data, hash_size); + LIBSPDM_DEBUG((LIBSPDM_DEBUG_INFO, "\n")); + + libspdm_copy_mem(hmac, hash_size, calc_hmac_data, hash_size); + + return true; +} + +#if LIBSPDM_ENABLE_CAPABILITY_MUT_AUTH_CAP + +bool libspdm_generate_finish_req_signature(libspdm_context_t *spdm_context, + libspdm_session_info_t *session_info, + uint8_t *signature) +{ + bool result; + size_t signature_size; +#if LIBSPDM_RECORD_TRANSCRIPT_DATA_SUPPORT + uint8_t *cert_chain_buffer; + size_t cert_chain_buffer_size; + uint8_t *mut_cert_chain_buffer; + size_t mut_cert_chain_buffer_size; + uint8_t th_curr_data[LIBSPDM_MAX_MESSAGE_BUFFER_SIZE]; + size_t th_curr_data_size; +#endif +#if !(LIBSPDM_RECORD_TRANSCRIPT_DATA_SUPPORT) || (LIBSPDM_DEBUG_PRINT_ENABLE) + size_t hash_size; +#endif +#if ((LIBSPDM_RECORD_TRANSCRIPT_DATA_SUPPORT) && (LIBSPDM_DEBUG_BLOCK_ENABLE)) || \ + !(LIBSPDM_RECORD_TRANSCRIPT_DATA_SUPPORT) + uint8_t hash_data[LIBSPDM_MAX_HASH_SIZE]; +#endif + + signature_size = libspdm_get_req_asym_signature_size( + spdm_context->connection_info.algorithm.req_base_asym_alg); + +#if !(LIBSPDM_RECORD_TRANSCRIPT_DATA_SUPPORT) || (LIBSPDM_DEBUG_PRINT_ENABLE) + hash_size = libspdm_get_hash_size(spdm_context->connection_info.algorithm.base_hash_algo); +#endif + +#if LIBSPDM_RECORD_TRANSCRIPT_DATA_SUPPORT + result = libspdm_get_peer_cert_chain_buffer( + spdm_context, (const void **)&cert_chain_buffer, &cert_chain_buffer_size); + if (!result) { + return false; + } + + result = libspdm_get_local_cert_chain_buffer(spdm_context, + (const void **)&mut_cert_chain_buffer, + &mut_cert_chain_buffer_size); + if (!result) { + return false; + } + + th_curr_data_size = sizeof(th_curr_data); + result = libspdm_calculate_th_for_finish( + spdm_context, session_info, cert_chain_buffer, + cert_chain_buffer_size, mut_cert_chain_buffer, + mut_cert_chain_buffer_size, &th_curr_data_size, th_curr_data); + if (!result) { + return false; + } + + /* Debug code only - required for debug print of th_curr below*/ + LIBSPDM_DEBUG_CODE( + if (!libspdm_hash_all( + spdm_context->connection_info.algorithm.base_hash_algo, + th_curr_data, th_curr_data_size, hash_data)) { + return false; + } + ); +#else + result = libspdm_calculate_th_hash_for_finish( + spdm_context, session_info, &hash_size, hash_data); + if (!result) { + return false; + } +#endif + LIBSPDM_DEBUG((LIBSPDM_DEBUG_INFO, "th_curr hash - ")); + LIBSPDM_INTERNAL_DUMP_DATA(hash_data, hash_size); + LIBSPDM_DEBUG((LIBSPDM_DEBUG_INFO, "\n")); + +#if LIBSPDM_RECORD_TRANSCRIPT_DATA_SUPPORT + result = libspdm_requester_data_sign( + spdm_context->connection_info.version, SPDM_FINISH, + spdm_context->connection_info.algorithm.req_base_asym_alg, + spdm_context->connection_info.algorithm.base_hash_algo, + false, th_curr_data, th_curr_data_size, signature, &signature_size); +#else + result = libspdm_requester_data_sign( + spdm_context->connection_info.version, SPDM_FINISH, + spdm_context->connection_info.algorithm.req_base_asym_alg, + spdm_context->connection_info.algorithm.base_hash_algo, + true, hash_data, hash_size, signature, &signature_size); +#endif + if (result) { + LIBSPDM_DEBUG((LIBSPDM_DEBUG_INFO, "signature - ")); + LIBSPDM_INTERNAL_DUMP_DATA(signature, signature_size); + LIBSPDM_DEBUG((LIBSPDM_DEBUG_INFO, "\n")); + } + + return result; +} +#endif /* LIBSPDM_ENABLE_CAPABILITY_MUT_AUTH_CAP */ + +/** + * This function sends FINISH and receives FINISH_RSP for SPDM finish. + * + * @param spdm_context A pointer to the SPDM context. + * @param session_id session_id to the FINISH request. + * @param req_slot_id_param req_slot_id_param to the FINISH request. + * + * @retval RETURN_SUCCESS The FINISH is sent and the FINISH_RSP is received. + * @retval RETURN_DEVICE_ERROR A device error occurs when communicates with the device. + **/ +static libspdm_return_t libspdm_try_send_receive_finish(libspdm_context_t *spdm_context, + uint32_t session_id, + uint8_t req_slot_id_param) +{ + libspdm_return_t status; + libspdm_finish_request_mine_t *spdm_request; + size_t spdm_request_size; + size_t signature_size; + size_t hmac_size; + libspdm_finish_response_mine_t *spdm_response; + size_t spdm_response_size; + libspdm_session_info_t *session_info; + uint8_t *ptr; + bool result; + uint8_t th2_hash_data[LIBSPDM_MAX_HASH_SIZE]; + libspdm_session_state_t session_state; + uint8_t *message; + size_t message_size; + size_t transport_header_size; + + /* -=[Check Parameters Phase]=- */ + session_info = libspdm_get_session_info_via_session_id(spdm_context, session_id); + if (session_info == NULL) { + status = LIBSPDM_STATUS_INVALID_PARAMETER; + goto error; + } + + /* -=[Verify State Phase]=- */ + if (!libspdm_is_capabilities_flag_supported( + spdm_context, true, + SPDM_GET_CAPABILITIES_REQUEST_FLAGS_KEY_EX_CAP, + SPDM_GET_CAPABILITIES_RESPONSE_FLAGS_KEY_EX_CAP)) { + status = LIBSPDM_STATUS_UNSUPPORTED_CAP; + goto error; + } + + if (spdm_context->connection_info.connection_state < LIBSPDM_CONNECTION_STATE_NEGOTIATED) { + status = LIBSPDM_STATUS_INVALID_STATE_LOCAL; + goto error; + } + + session_state = libspdm_secured_message_get_session_state( + session_info->secured_message_context); + if (session_state != LIBSPDM_SESSION_STATE_HANDSHAKING) { + status = LIBSPDM_STATUS_INVALID_STATE_LOCAL; + goto error; + } + if (session_info->mut_auth_requested != 0) { + if ((req_slot_id_param >= SPDM_MAX_SLOT_COUNT) && (req_slot_id_param != 0xFF)) { + status = LIBSPDM_STATUS_INVALID_PARAMETER; + goto error; + } + } else { + if (req_slot_id_param != 0) { + status = LIBSPDM_STATUS_INVALID_PARAMETER; + goto error; + } + } + + /* -=[Construct Request Phase]=- */ + transport_header_size = spdm_context->transport_get_header_size(spdm_context); + status = libspdm_acquire_sender_buffer (spdm_context, &message_size, (void **)&message); + if (LIBSPDM_STATUS_IS_ERROR(status)) { + goto error; + } + LIBSPDM_ASSERT (message_size >= transport_header_size); + spdm_request = (void *)(message + transport_header_size); + spdm_request_size = message_size - transport_header_size; + + spdm_request->header.spdm_version = libspdm_get_connection_version (spdm_context); + spdm_request->header.request_response_code = SPDM_FINISH; + spdm_request->header.param1 = 0; + spdm_request->header.param2 = 0; + signature_size = 0; +#if LIBSPDM_ENABLE_CAPABILITY_MUT_AUTH_CAP + if (session_info->mut_auth_requested) { + spdm_request->header.param1 = SPDM_FINISH_REQUEST_ATTRIBUTES_SIGNATURE_INCLUDED; + spdm_request->header.param2 = req_slot_id_param; + signature_size = libspdm_get_req_asym_signature_size( + spdm_context->connection_info.algorithm.req_base_asym_alg); + } +#endif + + if (req_slot_id_param == 0xFF) { + req_slot_id_param = spdm_context->local_context.provisioned_slot_id; + } + + if (session_info->mut_auth_requested) { + LIBSPDM_ASSERT(req_slot_id_param < SPDM_MAX_SLOT_COUNT); + spdm_context->connection_info.local_used_cert_chain_buffer = + spdm_context->local_context.local_cert_chain_provision[req_slot_id_param]; + spdm_context->connection_info.local_used_cert_chain_buffer_size = + spdm_context->local_context.local_cert_chain_provision_size[req_slot_id_param]; + } + + hmac_size = libspdm_get_hash_size(spdm_context->connection_info.algorithm.base_hash_algo); + spdm_request_size = sizeof(spdm_finish_request_t) + signature_size + hmac_size; + ptr = spdm_request->signature; + + status = libspdm_append_message_f(spdm_context, session_info, true, (uint8_t *)spdm_request, + sizeof(spdm_finish_request_t)); + if (LIBSPDM_STATUS_IS_ERROR(status)) { + libspdm_release_sender_buffer (spdm_context); + status = LIBSPDM_STATUS_BUFFER_FULL; + goto error; + } +#if LIBSPDM_ENABLE_CAPABILITY_MUT_AUTH_CAP + if (session_info->mut_auth_requested) { + result = libspdm_generate_finish_req_signature(spdm_context, session_info, ptr); + if (!result) { + libspdm_release_sender_buffer (spdm_context); + status = LIBSPDM_STATUS_CRYPTO_ERROR; + goto error; + } + status = libspdm_append_message_f(spdm_context, session_info, true, ptr, signature_size); + if (LIBSPDM_STATUS_IS_ERROR(status)) { + libspdm_release_sender_buffer (spdm_context); + status = LIBSPDM_STATUS_BUFFER_FULL; + goto error; + } + ptr += signature_size; + } +#endif + + result = libspdm_generate_finish_req_hmac(spdm_context, session_info, ptr); + if (!result) { + libspdm_release_sender_buffer (spdm_context); + status = LIBSPDM_STATUS_CRYPTO_ERROR; + goto error; + } + + status = libspdm_append_message_f(spdm_context, session_info, true, ptr, hmac_size); + if (LIBSPDM_STATUS_IS_ERROR(status)) { + libspdm_release_sender_buffer (spdm_context); + status = LIBSPDM_STATUS_BUFFER_FULL; + goto error; + } + + /* -=[Send Request Phase]=- */ + status = libspdm_send_spdm_request(spdm_context, &session_id, spdm_request_size, spdm_request); + if (LIBSPDM_STATUS_IS_ERROR(status)) { + libspdm_release_sender_buffer (spdm_context); + goto error; + } + + libspdm_reset_message_buffer_via_request_code(spdm_context, session_info, SPDM_FINISH); + + libspdm_release_sender_buffer (spdm_context); + spdm_request = (void *)spdm_context->last_spdm_request; + + /* -=[Receive Response Phase]=- */ + status = libspdm_acquire_receiver_buffer (spdm_context, &message_size, (void **)&message); + if (LIBSPDM_STATUS_IS_ERROR(status)) { + goto error; + } + LIBSPDM_ASSERT (message_size >= transport_header_size); + spdm_response = (void *)(message); + spdm_response_size = message_size; + + libspdm_zero_mem(spdm_response, spdm_response_size); + status = libspdm_receive_spdm_response( + spdm_context, &session_id, &spdm_response_size, (void **)&spdm_response); + if (LIBSPDM_STATUS_IS_ERROR(status)) { + goto receive_done; + } + + /* -=[Validate Response Phase]=- */ + if (spdm_response_size < sizeof(spdm_message_header_t)) { + status = LIBSPDM_STATUS_INVALID_MSG_SIZE; + goto receive_done; + } + if (spdm_response->header.spdm_version != spdm_request->header.spdm_version) { + status = LIBSPDM_STATUS_INVALID_MSG_FIELD; + goto receive_done; + } + if (spdm_response->header.request_response_code == SPDM_ERROR) { + if (spdm_response->header.param1 == SPDM_ERROR_CODE_DECRYPT_ERROR) { + status = LIBSPDM_STATUS_SESSION_MSG_ERROR; + goto receive_done; + } + if (spdm_response->header.param1 != SPDM_ERROR_CODE_RESPONSE_NOT_READY) { + libspdm_reset_message_f (spdm_context, session_info); + } + status = libspdm_handle_error_response_main( + spdm_context, &session_id, + &spdm_response_size, (void **)&spdm_response, + SPDM_FINISH, SPDM_FINISH_RSP, + sizeof(libspdm_finish_response_mine_t)); + if (LIBSPDM_STATUS_IS_ERROR(status)) { + goto receive_done; + } + } else if (spdm_response->header.request_response_code != SPDM_FINISH_RSP) { + status = LIBSPDM_STATUS_INVALID_MSG_FIELD; + goto receive_done; + } + + if (!libspdm_is_capabilities_flag_supported( + spdm_context, true, + SPDM_GET_CAPABILITIES_REQUEST_FLAGS_HANDSHAKE_IN_THE_CLEAR_CAP, + SPDM_GET_CAPABILITIES_RESPONSE_FLAGS_HANDSHAKE_IN_THE_CLEAR_CAP)) { + hmac_size = 0; + } + + if (spdm_response_size != sizeof(spdm_finish_response_t) + hmac_size) { + status = LIBSPDM_STATUS_INVALID_MSG_SIZE; + goto receive_done; + } + + status = libspdm_append_message_f(spdm_context, session_info, true, spdm_response, + sizeof(spdm_finish_response_t)); + if (LIBSPDM_STATUS_IS_ERROR(status)) { + status = LIBSPDM_STATUS_BUFFER_FULL; + goto receive_done; + } + + if (libspdm_is_capabilities_flag_supported( + spdm_context, true, + SPDM_GET_CAPABILITIES_REQUEST_FLAGS_HANDSHAKE_IN_THE_CLEAR_CAP, + SPDM_GET_CAPABILITIES_RESPONSE_FLAGS_HANDSHAKE_IN_THE_CLEAR_CAP)) { + LIBSPDM_DEBUG((LIBSPDM_DEBUG_INFO, "verify_data (0x%x):\n", hmac_size)); + LIBSPDM_INTERNAL_DUMP_HEX(spdm_response->verify_data, hmac_size); + result = libspdm_verify_finish_rsp_hmac(spdm_context, session_info, + spdm_response->verify_data, + hmac_size); + if (!result) { + status = LIBSPDM_STATUS_VERIF_FAIL; + goto receive_done; + } + + status = libspdm_append_message_f( + spdm_context, session_info, true, + (uint8_t *)spdm_response + + sizeof(spdm_finish_response_t), + hmac_size); + if (LIBSPDM_STATUS_IS_ERROR(status)) { + status = LIBSPDM_STATUS_BUFFER_FULL; + goto receive_done; + } + } + + /* -=[Process Response Phase]=- */ + LIBSPDM_DEBUG((LIBSPDM_DEBUG_INFO, "libspdm_generate_session_data_key[%x]\n", session_id)); + result = libspdm_calculate_th2_hash(spdm_context, session_info, true, th2_hash_data); + if (!result) { + status = LIBSPDM_STATUS_CRYPTO_ERROR; + goto receive_done; + } + result = libspdm_generate_session_data_key( + session_info->secured_message_context, th2_hash_data); + if (!result) { + status = LIBSPDM_STATUS_CRYPTO_ERROR; + goto receive_done; + } + + /* -=[Update State Phase]=- */ + libspdm_secured_message_set_session_state( + session_info->secured_message_context, LIBSPDM_SESSION_STATE_ESTABLISHED); + + libspdm_release_receiver_buffer (spdm_context); + + return LIBSPDM_STATUS_SUCCESS; + +receive_done: + libspdm_release_receiver_buffer (spdm_context); +error: + if (status != LIBSPDM_STATUS_BUSY_PEER) { + libspdm_free_session_id(spdm_context, session_id); + } + + return status; +} + +libspdm_return_t libspdm_send_receive_finish(libspdm_context_t *spdm_context, + uint32_t session_id, + uint8_t req_slot_id_param) +{ + size_t retry; + libspdm_return_t status; + + spdm_context->crypto_request = true; + retry = spdm_context->retry_times; + do { + status = libspdm_try_send_receive_finish(spdm_context, session_id, + req_slot_id_param); + if (status != LIBSPDM_STATUS_BUSY_PEER) { + return status; + } + } while (retry-- != 0); + + return status; +} + +#endif /* LIBSPDM_ENABLE_CAPABILITY_KEY_EX_CAP*/ diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/libraries/libspdm/2.3.1/library/spdm_requester_lib/libspdm_req_get_capabilities.c nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/libraries/libspdm/2.3.1/library/spdm_requester_lib/libspdm_req_get_capabilities.c --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/libraries/libspdm/2.3.1/library/spdm_requester_lib/libspdm_req_get_capabilities.c 1970-01-01 00:00:00.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/libraries/libspdm/2.3.1/library/spdm_requester_lib/libspdm_req_get_capabilities.c 2024-03-05 22:14:16.000000000 +0000 @@ -0,0 +1,337 @@ +/** + * Copyright Notice: + * Copyright 2021-2022 DMTF. All rights reserved. + * License: BSD 3-Clause License. For full text see link: https://github.com/DMTF/libspdm/blob/main/LICENSE.md + **/ + +#include "internal/libspdm_requester_lib.h" + +/** + * This function validates the Responder's capabilities. + * + * @param capabilities_flag The Responder's CAPABILITIES.Flags field. + * @param version The SPDM message version. + * + * @retval true The field is valid. + * @retval false The field is invalid. + **/ +static bool validate_responder_capability(uint32_t capabilities_flag, uint8_t version) +{ + /*uint8_t cache_cap = (uint8_t)(capabilities_flag)&0x01;*/ + const uint8_t cert_cap = (uint8_t)(capabilities_flag >> 1) & 0x01; + const uint8_t chal_cap = (uint8_t)(capabilities_flag >> 2) & 0x01; + const uint8_t meas_cap = (uint8_t)(capabilities_flag >> 3) & 0x03; + const uint8_t meas_fresh_cap = (uint8_t)(capabilities_flag >> 5) & 0x01; + const uint8_t encrypt_cap = (uint8_t)(capabilities_flag >> 6) & 0x01; + const uint8_t mac_cap = (uint8_t)(capabilities_flag >> 7) & 0x01; + const uint8_t mut_auth_cap = (uint8_t)(capabilities_flag >> 8) & 0x01; + const uint8_t key_ex_cap = (uint8_t)(capabilities_flag >> 9) & 0x01; + const uint8_t psk_cap = (uint8_t)(capabilities_flag >> 10) & 0x03; + const uint8_t encap_cap = (uint8_t)(capabilities_flag >> 12) & 0x01; + const uint8_t hbeat_cap = (uint8_t)(capabilities_flag >> 13) & 0x01; + const uint8_t key_upd_cap = (uint8_t)(capabilities_flag >> 14) & 0x01; + const uint8_t handshake_in_the_clear_cap = (uint8_t)(capabilities_flag >> 15) & 0x01; + const uint8_t pub_key_id_cap = (uint8_t)(capabilities_flag >> 16) & 0x01; + /* uint8_t chunk_cap = (uint8_t)(capabilities_flag >> 17) & 0x01; */ + const uint8_t alias_cert_cap = (uint8_t)(capabilities_flag >> 18) & 0x01; + const uint8_t set_cert_cap = (uint8_t)(capabilities_flag >> 19) & 0x01; + const uint8_t csr_cap = (uint8_t)(capabilities_flag >> 20) & 0x01; + const uint8_t cert_install_reset_cap = (uint8_t)(capabilities_flag >> 21) & 0x01; + + /* Checks common to all SPDM versions. */ + + /* Illegal to return reserved value. */ + if (meas_cap == 3) { + return false; + } + + /* If MEAS_FRESH_CAP is set then MEAS_CAP must be set. */ + if ((meas_cap == 0) && (meas_fresh_cap == 1)) { + return false; + } + + if (version == SPDM_MESSAGE_VERSION_10) { + /* If measurements are not signed then CERT_CAP must equal CHAL_CAP. + * If measurements are signed then CERT_CAP must be set. */ + if ((meas_cap == 0) || (meas_cap == 1)) { + if (cert_cap != chal_cap) { + return false; + } + } else if (meas_cap == 2) { + if (cert_cap == 0) { + return false; + } + } + return true; + } + + /* Checks common to 1.1 and 1.2. */ + if ((version == SPDM_MESSAGE_VERSION_11) || (version == SPDM_MESSAGE_VERSION_12)) { + /* Illegal to return reserved values. */ + if (psk_cap == 3) { + return false; + } + + /* Checks that originate from key exchange capabilities. */ + if ((key_ex_cap == 1) || (psk_cap != 0)) { + if ((mac_cap == 0) && (encrypt_cap == 0)) { + return false; + } + } else { + if ((mac_cap == 1) || (encrypt_cap == 1) || (handshake_in_the_clear_cap == 1) || + (hbeat_cap == 1) || (key_upd_cap == 1)) { + return false; + } + } + if ((key_ex_cap == 0) && (psk_cap != 0)) { + if (handshake_in_the_clear_cap == 1) { + return false; + } + } + + /* Checks that originate from certificate or public key capabilities. */ + if ((cert_cap == 1) || (pub_key_id_cap == 1)) { + /* Certificate capabilities and public key capabilities cannot both be set. */ + if ((cert_cap == 1) && (pub_key_id_cap == 1)) { + return false; + } + if ((chal_cap == 0) && (key_ex_cap == 0) && ((meas_cap == 0) || (meas_cap == 1))) { + return false; + } + } else { + /* If certificates or public keys are not enabled then these capabilities + * cannot be enabled. */ + if ((chal_cap == 1) || (key_ex_cap == 1) || (meas_cap == 2) || (mut_auth_cap == 1)) { + return false; + } + } + } + + /* Checks specific to 1.1. */ + if (version == SPDM_MESSAGE_VERSION_11) { + if ((mut_auth_cap == 1) && (encap_cap == 0)) { + return false; + } + } + + /* Checks specific to 1.2. */ + if (version == SPDM_MESSAGE_VERSION_12) { + if ((cert_cap == 0) && ((alias_cert_cap == 1) || (set_cert_cap == 1))) { + return false; + } + if ((csr_cap == 1) && (set_cert_cap == 0)) { + return false; + } + if ((cert_install_reset_cap == 1) && (csr_cap == 0) && (set_cert_cap == 0)) { + return false; + } + } + + return true; +} + +/** + * This function sends GET_CAPABILITIES and receives CAPABILITIES. + * + * @param spdm_context A pointer to the SPDM context. + * + * @retval LIBSPDM_STATUS_SUCCESS + * GET_CAPABILITIES was sent and CAPABILITIES was received. + * @retval LIBSPDM_STATUS_INVALID_STATE_LOCAL + * Cannot send GET_CAPABILITIES due to Requester's state. Send GET_VERSION first. + * @retval LIBSPDM_STATUS_INVALID_MSG_SIZE + * The size of the CAPABILITIES response is invalid. + * @retval LIBSPDM_STATUS_INVALID_MSG_FIELD + * The CAPABILITIES response contains one or more invalid fields. + * @retval LIBSPDM_STATUS_ERROR_PEER + * The Responder returned an unexpected error. + * @retval LIBSPDM_STATUS_BUSY_PEER + * The Responder continually returned Busy error messages. + * @retval LIBSPDM_STATUS_RESYNCH_PEER + * The Responder returned a RequestResynch error message. + * @retval LIBSPDM_STATUS_BUFFER_FULL + * The buffer used to store transcripts is exhausted. + **/ +static libspdm_return_t libspdm_try_get_capabilities(libspdm_context_t *spdm_context) +{ + libspdm_return_t status; + spdm_get_capabilities_request_t *spdm_request; + size_t spdm_request_size; + spdm_capabilities_response_t *spdm_response; + size_t spdm_response_size; + uint8_t *message; + size_t message_size; + size_t transport_header_size; + + /* -=[Verify State Phase]=- */ + if (spdm_context->connection_info.connection_state != LIBSPDM_CONNECTION_STATE_AFTER_VERSION) { + return LIBSPDM_STATUS_INVALID_STATE_LOCAL; + } + libspdm_reset_message_buffer_via_request_code(spdm_context, NULL, SPDM_GET_CAPABILITIES); + + /* -=[Construct Request Phase]=- */ + transport_header_size = spdm_context->transport_get_header_size(spdm_context); + status = libspdm_acquire_sender_buffer (spdm_context, &message_size, (void **)&message); + if (LIBSPDM_STATUS_IS_ERROR(status)) { + return status; + } + LIBSPDM_ASSERT (message_size >= transport_header_size); + spdm_request = (void *)(message + transport_header_size); + + libspdm_zero_mem(spdm_request, sizeof(spdm_get_capabilities_request_t)); + spdm_request->header.spdm_version = libspdm_get_connection_version (spdm_context); + if (spdm_request->header.spdm_version >= SPDM_MESSAGE_VERSION_12) { + spdm_request_size = sizeof(spdm_get_capabilities_request_t); + } else if (spdm_request->header.spdm_version >= SPDM_MESSAGE_VERSION_11) { + spdm_request_size = sizeof(spdm_get_capabilities_request_t) - + sizeof(spdm_request->data_transfer_size) - + sizeof(spdm_request->max_spdm_msg_size); + } else { + spdm_request_size = sizeof(spdm_request->header); + } + spdm_request->header.request_response_code = SPDM_GET_CAPABILITIES; + spdm_request->header.param1 = 0; + spdm_request->header.param2 = 0; + spdm_request->ct_exponent = spdm_context->local_context.capability.ct_exponent; + spdm_request->flags = spdm_context->local_context.capability.flags; + spdm_request->data_transfer_size = spdm_context->local_context.capability.data_transfer_size; + spdm_request->max_spdm_msg_size = spdm_context->local_context.capability.max_spdm_msg_size; + + /* -=[Send Request Phase]=- */ + status = libspdm_send_spdm_request(spdm_context, NULL, spdm_request_size, spdm_request); + if (LIBSPDM_STATUS_IS_ERROR(status)) { + libspdm_release_sender_buffer (spdm_context); + return status; + } + libspdm_release_sender_buffer (spdm_context); + spdm_request = (void *)spdm_context->last_spdm_request; + + /* -=[Receive Response Phase]=- */ + status = libspdm_acquire_receiver_buffer (spdm_context, &message_size, (void **)&message); + if (LIBSPDM_STATUS_IS_ERROR(status)) { + return status; + } + LIBSPDM_ASSERT (message_size >= transport_header_size); + spdm_response = (void *)(message); + spdm_response_size = message_size; + + libspdm_zero_mem(spdm_response, spdm_response_size); + status = libspdm_receive_spdm_response(spdm_context, NULL, &spdm_response_size, + (void **)&spdm_response); + if (LIBSPDM_STATUS_IS_ERROR(status)) { + goto receive_done; + } + + /* -=[Validate Response Phase]=- */ + if (spdm_response_size < sizeof(spdm_message_header_t)) { + status = LIBSPDM_STATUS_INVALID_MSG_SIZE; + goto receive_done; + } + if (spdm_response->header.spdm_version != spdm_request->header.spdm_version) { + status = LIBSPDM_STATUS_INVALID_MSG_FIELD; + goto receive_done; + } + if (spdm_response->header.request_response_code == SPDM_ERROR) { + status = libspdm_handle_simple_error_response( + spdm_context, spdm_response->header.param1); + if (LIBSPDM_STATUS_IS_ERROR(status)) { + goto receive_done; + } + } else if (spdm_response->header.request_response_code != SPDM_CAPABILITIES) { + status = LIBSPDM_STATUS_INVALID_MSG_FIELD; + goto receive_done; + } + if (spdm_response->header.spdm_version >= SPDM_MESSAGE_VERSION_12) { + if (spdm_response_size < sizeof(spdm_capabilities_response_t)) { + status = LIBSPDM_STATUS_INVALID_MSG_SIZE; + goto receive_done; + } + } else { + if (spdm_response_size < sizeof(spdm_capabilities_response_t) - + sizeof(spdm_response->data_transfer_size) - sizeof(spdm_response->max_spdm_msg_size)) { + status = LIBSPDM_STATUS_INVALID_MSG_SIZE; + goto receive_done; + } + } + if (spdm_request->header.spdm_version >= SPDM_MESSAGE_VERSION_12) { + spdm_response_size = sizeof(spdm_capabilities_response_t); + } else { + spdm_response_size = sizeof(spdm_capabilities_response_t) - + sizeof(spdm_response->data_transfer_size) - + sizeof(spdm_response->max_spdm_msg_size); + } + + if (!validate_responder_capability(spdm_response->flags, spdm_response->header.spdm_version)) { + status = LIBSPDM_STATUS_INVALID_MSG_FIELD; + goto receive_done; + } + if (spdm_response->header.spdm_version >= SPDM_MESSAGE_VERSION_12) { + if ((spdm_response->data_transfer_size < SPDM_MIN_DATA_TRANSFER_SIZE_VERSION_12) || + (spdm_response->data_transfer_size > spdm_response->max_spdm_msg_size)) { + status = LIBSPDM_STATUS_INVALID_MSG_FIELD; + goto receive_done; + } + + if (((spdm_response->flags & SPDM_GET_CAPABILITIES_RESPONSE_FLAGS_CHUNK_CAP) == 0) && + (spdm_response->data_transfer_size != spdm_response->max_spdm_msg_size)) { + status = LIBSPDM_STATUS_INVALID_MSG_FIELD; + goto receive_done; + } + } + + /* -=[Process Response Phase]=- */ + status = libspdm_append_message_a(spdm_context, spdm_request, spdm_request_size); + if (LIBSPDM_STATUS_IS_ERROR(status)) { + status = LIBSPDM_STATUS_BUFFER_FULL; + goto receive_done; + } + + status = libspdm_append_message_a(spdm_context, spdm_response, spdm_response_size); + if (LIBSPDM_STATUS_IS_ERROR(status)) { + status = LIBSPDM_STATUS_BUFFER_FULL; + goto receive_done; + } + + spdm_context->connection_info.capability.ct_exponent = spdm_response->ct_exponent; + spdm_context->connection_info.capability.flags = spdm_response->flags; + + if (spdm_response->header.spdm_version >= SPDM_MESSAGE_VERSION_12) { + spdm_context->connection_info.capability.data_transfer_size = + spdm_response->data_transfer_size; + spdm_context->connection_info.capability.max_spdm_msg_size = + spdm_response->max_spdm_msg_size; + } else { + spdm_context->connection_info.capability.data_transfer_size = 0; + spdm_context->connection_info.capability.max_spdm_msg_size = 0; + } + + /* -=[Update State Phase]=- */ + spdm_context->connection_info.connection_state = LIBSPDM_CONNECTION_STATE_AFTER_CAPABILITIES; + status = LIBSPDM_STATUS_SUCCESS; + + /* -=[Log Message Phase]=- */ + #if LIBSPDM_ENABLE_MSG_LOG + libspdm_append_msg_log(spdm_context, spdm_response, spdm_response_size); + #endif /* LIBSPDM_ENABLE_MSG_LOG */ + +receive_done: + libspdm_release_receiver_buffer (spdm_context); + return status; +} + +libspdm_return_t libspdm_get_capabilities(libspdm_context_t *spdm_context) +{ + size_t retry; + libspdm_return_t status; + + spdm_context->crypto_request = false; + retry = spdm_context->retry_times; + do { + status = libspdm_try_get_capabilities(spdm_context); + if (status != LIBSPDM_STATUS_BUSY_PEER) { + return status; + } + } while (retry-- != 0); + + return status; +} diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/libraries/libspdm/2.3.1/library/spdm_requester_lib/libspdm_req_get_certificate.c nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/libraries/libspdm/2.3.1/library/spdm_requester_lib/libspdm_req_get_certificate.c --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/libraries/libspdm/2.3.1/library/spdm_requester_lib/libspdm_req_get_certificate.c 1970-01-01 00:00:00.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/libraries/libspdm/2.3.1/library/spdm_requester_lib/libspdm_req_get_certificate.c 2024-03-05 22:14:16.000000000 +0000 @@ -0,0 +1,511 @@ +/** + * Copyright Notice: + * Copyright 2021-2022 DMTF. All rights reserved. + * License: BSD 3-Clause License. For full text see link: https://github.com/DMTF/libspdm/blob/main/LICENSE.md + **/ + +#include "internal/libspdm_requester_lib.h" + +#if LIBSPDM_ENABLE_CAPABILITY_CERT_CAP + +// NVIDIA_EDIT: Include malloclib for dynamic allocation. +#include "library/malloclib.h" + +#pragma pack(1) +typedef struct { + spdm_message_header_t header; + uint16_t portion_length; + uint16_t remainder_length; + uint8_t cert_chain[LIBSPDM_MAX_CERT_CHAIN_BLOCK_LEN]; +} libspdm_certificate_response_max_t; +#pragma pack() + +/** + * This function sends GET_CERTIFICATE and receives CERTIFICATE. + * + * This function verify the integrity of the certificate chain. + * root_hash -> Root certificate -> Intermediate certificate -> Leaf certificate. + * + * If the peer root certificate hash is deployed, + * this function also verifies the digest with the root hash in the certificate chain. + * + * @param spdm_context A pointer to the SPDM context. + * @param slot_id The number of slot for the certificate chain. + * @param cert_chain_size On input, indicate the size in bytes of the destination buffer to store + * the digest buffer. + * On output, indicate the size in bytes of the certificate chain. + * @param cert_chain A pointer to a destination buffer to store the certificate chain. + * @param trust_anchor A buffer to hold the trust_anchor which is used to validate the peer + * certificate, if not NULL. + * @param trust_anchor_size A buffer to hold the trust_anchor_size, if not NULL. + * + * @retval LIBSPDM_STATUS_SUCCESS + * GET_CERTIFICATE was sent and CERTIFICATE was received. + * @retval LIBSPDM_STATUS_INVALID_STATE_LOCAL + * Cannot send GET_CERTIFICATE due to Requester's state. + * @retval LIBSPDM_STATUS_UNSUPPORTED_CAP + * Cannot send GET_CERTIFICATE because the Requester's and/or Responder's CERT_CAP = 0. + * @retval LIBSPDM_STATUS_INVALID_MSG_SIZE + * The size of the CERTIFICATE response is invalid. + * @retval LIBSPDM_STATUS_INVALID_MSG_FIELD + * The CERTIFICATE response contains one or more invalid fields. + * @retval LIBSPDM_STATUS_ERROR_PEER + * The Responder returned an unexpected error. + * @retval LIBSPDM_STATUS_BUSY_PEER + * The Responder continually returned Busy error messages. + * @retval LIBSPDM_STATUS_RESYNCH_PEER + * The Responder returned a RequestResynch error message. + * @retval LIBSPDM_STATUS_BUFFER_FULL + * The buffer used to store transcripts is exhausted. + * @retval LIBSPDM_STATUS_VERIF_FAIL + * Verification of the certificate chain failed. + * @retval LIBSPDM_STATUS_INVALID_CERT + * The certificate is unable to be parsed or contains invalid field values. + * @retval LIBSPDM_STATUS_CRYPTO_ERROR + * A generic cryptography error occurred. + **/ +static libspdm_return_t libspdm_try_get_certificate(void *context, const uint32_t *session_id, + uint8_t slot_id, + uint16_t length, + size_t *cert_chain_size, + void *cert_chain, + const void **trust_anchor, + size_t *trust_anchor_size) +{ + bool result; + libspdm_return_t status; + spdm_get_certificate_request_t *spdm_request; + size_t spdm_request_size; + libspdm_certificate_response_max_t *spdm_response; + size_t spdm_response_size; + libspdm_large_managed_buffer_t *certificate_chain_buffer; + libspdm_context_t *spdm_context; + uint16_t total_responder_cert_chain_buffer_length; + size_t cert_chain_capacity; + uint16_t remainder_length; + uint8_t *message; + size_t message_size; + size_t transport_header_size; + libspdm_session_info_t *session_info; + libspdm_session_state_t session_state; + bool chunk_enabled; + + // + // NVIDIA_EDIT: To avoid massive stack usage, changed the certificate buffer from + // allocation on stack to dynamic memory. Changed return patterns where + // necessary to ensure memory is freed. + // + certificate_chain_buffer = (libspdm_large_managed_buffer_t *) + allocate_zero_pool(sizeof(libspdm_large_managed_buffer_t)); + if (certificate_chain_buffer == NULL) { + return LIBSPDM_STATUS_BUFFER_FULL; + } + + /* -=[Check Parameters Phase]=- */ + LIBSPDM_ASSERT(slot_id < SPDM_MAX_SLOT_COUNT); + + /* -=[Verify State Phase]=- */ + spdm_context = context; + + if (!libspdm_is_capabilities_flag_supported( + spdm_context, true, 0, + SPDM_GET_CAPABILITIES_RESPONSE_FLAGS_CERT_CAP)) { + status = LIBSPDM_STATUS_UNSUPPORTED_CAP; + goto done; + } + if (spdm_context->connection_info.connection_state < LIBSPDM_CONNECTION_STATE_NEGOTIATED) { + status = LIBSPDM_STATUS_INVALID_STATE_LOCAL; + goto done; + } + + session_info = NULL; + if (session_id != NULL) { + session_info = libspdm_get_session_info_via_session_id( + spdm_context, *session_id); + if (session_info == NULL) { + LIBSPDM_ASSERT(false); + status = LIBSPDM_STATUS_INVALID_STATE_LOCAL; + goto done; + } + session_state = libspdm_secured_message_get_session_state( + session_info->secured_message_context); + if (session_state != LIBSPDM_SESSION_STATE_ESTABLISHED) { + status = LIBSPDM_STATUS_INVALID_STATE_LOCAL; + goto done; + } + } + + libspdm_reset_message_buffer_via_request_code(spdm_context, session_info, SPDM_GET_CERTIFICATE); + + libspdm_init_managed_buffer(certificate_chain_buffer, LIBSPDM_MAX_MESSAGE_BUFFER_SIZE); + + chunk_enabled = + libspdm_is_capabilities_flag_supported(spdm_context, true, + SPDM_GET_CAPABILITIES_REQUEST_FLAGS_CHUNK_CAP, + SPDM_GET_CAPABILITIES_RESPONSE_FLAGS_CHUNK_CAP); + + if (chunk_enabled) { + length = 0xffff; + } else { + length = LIBSPDM_MIN(length, LIBSPDM_MAX_CERT_CHAIN_BLOCK_LEN); + } + + remainder_length = 0; + total_responder_cert_chain_buffer_length = 0; + + transport_header_size = spdm_context->transport_get_header_size(spdm_context); + + do { + /* -=[Construct Request Phase]=- */ + status = libspdm_acquire_sender_buffer (spdm_context, &message_size, (void **)&message); + if (LIBSPDM_STATUS_IS_ERROR(status)) { + goto done; + } + LIBSPDM_ASSERT (message_size >= transport_header_size); + spdm_request = (void *)(message + transport_header_size); + spdm_request_size = message_size - transport_header_size; + + spdm_request->header.spdm_version = libspdm_get_connection_version (spdm_context); + spdm_request->header.request_response_code = SPDM_GET_CERTIFICATE; + spdm_request->header.param1 = slot_id; + spdm_request->header.param2 = 0; + spdm_request->offset = (uint16_t)libspdm_get_managed_buffer_size(certificate_chain_buffer); + if (spdm_request->offset == 0) { + spdm_request->length = length; + } else { + spdm_request->length = LIBSPDM_MIN(length, remainder_length); + } + spdm_request_size = sizeof(spdm_get_certificate_request_t); + LIBSPDM_DEBUG((LIBSPDM_DEBUG_INFO, "request (offset 0x%x, size 0x%x):\n", + spdm_request->offset, spdm_request->length)); + + /* -=[Send Request Phase]=- */ + status = + libspdm_send_spdm_request(spdm_context, session_id, spdm_request_size, spdm_request); + if (LIBSPDM_STATUS_IS_ERROR(status)) { + libspdm_release_sender_buffer (spdm_context); + status = LIBSPDM_STATUS_SEND_FAIL; + goto done; + } + libspdm_release_sender_buffer (spdm_context); + spdm_request = (void *)spdm_context->last_spdm_request; + + /* -=[Receive Response Phase]=- */ + status = libspdm_acquire_receiver_buffer (spdm_context, &message_size, (void **)&message); + if (LIBSPDM_STATUS_IS_ERROR(status)) { + goto done; + } + LIBSPDM_ASSERT (message_size >= transport_header_size); + spdm_response = (void *)(message); + spdm_response_size = message_size; + + libspdm_zero_mem(spdm_response, spdm_response_size); + status = libspdm_receive_spdm_response(spdm_context, session_id, + &spdm_response_size, + (void **)&spdm_response); + if (LIBSPDM_STATUS_IS_ERROR(status)) { + libspdm_release_receiver_buffer (spdm_context); + status = LIBSPDM_STATUS_RECEIVE_FAIL; + goto done; + } + + /* -=[Validate Response Phase]=- */ + if (spdm_response_size < sizeof(spdm_message_header_t)) { + libspdm_release_receiver_buffer (spdm_context); + status = LIBSPDM_STATUS_INVALID_MSG_SIZE; + goto done; + } + if (spdm_response->header.spdm_version != spdm_request->header.spdm_version) { + libspdm_release_receiver_buffer (spdm_context); + status = LIBSPDM_STATUS_INVALID_MSG_FIELD; + goto done; + } + if (spdm_response->header.request_response_code == SPDM_ERROR) { + status = libspdm_handle_error_response_main( + spdm_context, session_id, + &spdm_response_size, + (void **)&spdm_response, SPDM_GET_CERTIFICATE, + SPDM_CERTIFICATE, + sizeof(libspdm_certificate_response_max_t)); + if (LIBSPDM_STATUS_IS_ERROR(status)) { + libspdm_release_receiver_buffer (spdm_context); + goto done; + } + } else if (spdm_response->header.request_response_code != + SPDM_CERTIFICATE) { + libspdm_release_receiver_buffer (spdm_context); + status = LIBSPDM_STATUS_INVALID_MSG_FIELD; + goto done; + } + if (spdm_response_size < sizeof(spdm_certificate_response_t)) { + libspdm_release_receiver_buffer (spdm_context); + status = LIBSPDM_STATUS_INVALID_MSG_SIZE; + goto done; + } + if ((spdm_response->portion_length > spdm_request->length) || + (spdm_response->portion_length == 0)) { + libspdm_release_receiver_buffer (spdm_context); + status = LIBSPDM_STATUS_INVALID_MSG_FIELD; + goto done; + } + if ((spdm_response->header.param1 & SPDM_CERTIFICATE_RESPONSE_SLOT_ID_MASK) != slot_id) { + libspdm_release_receiver_buffer (spdm_context); + status = LIBSPDM_STATUS_INVALID_MSG_FIELD; + goto done; + } + if (spdm_response_size < sizeof(spdm_certificate_response_t) + + spdm_response->portion_length) { + libspdm_release_receiver_buffer (spdm_context); + status = LIBSPDM_STATUS_INVALID_MSG_SIZE; + goto done; + } + if (spdm_request->offset == 0) { + total_responder_cert_chain_buffer_length = spdm_response->portion_length + + spdm_response->remainder_length; + } else if (spdm_request->offset + spdm_response->portion_length + + spdm_response->remainder_length != total_responder_cert_chain_buffer_length) { + libspdm_release_receiver_buffer (spdm_context); + status = LIBSPDM_STATUS_INVALID_MSG_FIELD; + goto done; + } + if (chunk_enabled && (spdm_response->remainder_length != 0)) { + libspdm_release_receiver_buffer (spdm_context); + status = LIBSPDM_STATUS_INVALID_MSG_FIELD; + goto done; + } + + /* -=[Process Response Phase]=- */ + remainder_length = spdm_response->remainder_length; + spdm_response_size = sizeof(spdm_certificate_response_t) + spdm_response->portion_length; + + if (session_id == NULL) { + status = libspdm_append_message_b(spdm_context, spdm_request, spdm_request_size); + if (LIBSPDM_STATUS_IS_ERROR(status)) { + libspdm_release_receiver_buffer (spdm_context); + status = LIBSPDM_STATUS_BUFFER_FULL; + goto done; + } + status = libspdm_append_message_b(spdm_context, spdm_response, spdm_response_size); + if (LIBSPDM_STATUS_IS_ERROR(status)) { + libspdm_release_receiver_buffer (spdm_context); + status = LIBSPDM_STATUS_BUFFER_FULL; + goto done; + } + } + + LIBSPDM_DEBUG((LIBSPDM_DEBUG_INFO, "Certificate (offset 0x%x, size 0x%x):\n", + spdm_request->offset, spdm_response->portion_length)); + LIBSPDM_INTERNAL_DUMP_HEX(spdm_response->cert_chain, spdm_response->portion_length); + + status = libspdm_append_managed_buffer(certificate_chain_buffer, + spdm_response->cert_chain, + spdm_response->portion_length); + if (LIBSPDM_STATUS_IS_ERROR(status)) { + libspdm_release_receiver_buffer (spdm_context); + status = LIBSPDM_STATUS_BUFFER_FULL; + goto done; + } + if (spdm_context->connection_info.connection_state < + LIBSPDM_CONNECTION_STATE_AFTER_CERTIFICATE) { + spdm_context->connection_info.connection_state = + LIBSPDM_CONNECTION_STATE_AFTER_CERTIFICATE; + } + + libspdm_release_receiver_buffer (spdm_context); + } while (remainder_length != 0); + + if (spdm_context->local_context.verify_peer_spdm_cert_chain != NULL) { + result = spdm_context->local_context.verify_peer_spdm_cert_chain ( + spdm_context, slot_id, libspdm_get_managed_buffer_size(certificate_chain_buffer), + libspdm_get_managed_buffer(certificate_chain_buffer), + trust_anchor, trust_anchor_size); + if (!result) { + status = LIBSPDM_STATUS_VERIF_FAIL; + goto done; + } + } else { + result = libspdm_verify_peer_cert_chain_buffer( + spdm_context, libspdm_get_managed_buffer(certificate_chain_buffer), + libspdm_get_managed_buffer_size(certificate_chain_buffer), + trust_anchor, trust_anchor_size, true); + if (!result) { + status = LIBSPDM_STATUS_VERIF_FAIL; + goto done; + } + } + + spdm_context->connection_info.peer_used_cert_chain_slot_id = slot_id; +#if LIBSPDM_RECORD_TRANSCRIPT_DATA_SUPPORT + spdm_context->connection_info.peer_used_cert_chain[slot_id].buffer_size = + libspdm_get_managed_buffer_size(certificate_chain_buffer); + libspdm_copy_mem(spdm_context->connection_info.peer_used_cert_chain[slot_id].buffer, + sizeof(spdm_context->connection_info.peer_used_cert_chain[slot_id].buffer), + libspdm_get_managed_buffer(certificate_chain_buffer), + libspdm_get_managed_buffer_size(certificate_chain_buffer)); +#else + result = libspdm_hash_all( + spdm_context->connection_info.algorithm.base_hash_algo, + libspdm_get_managed_buffer(certificate_chain_buffer), + libspdm_get_managed_buffer_size(certificate_chain_buffer), + spdm_context->connection_info.peer_used_cert_chain[slot_id].buffer_hash); + if (!result) { + status = LIBSPDM_STATUS_CRYPTO_ERROR; + goto done; + } + + spdm_context->connection_info.peer_used_cert_chain[slot_id].buffer_hash_size = + libspdm_get_hash_size(spdm_context->connection_info.algorithm.base_hash_algo); + + result = libspdm_get_leaf_cert_public_key_from_cert_chain( + spdm_context->connection_info.algorithm.base_hash_algo, + spdm_context->connection_info.algorithm.base_asym_algo, + libspdm_get_managed_buffer(certificate_chain_buffer), + libspdm_get_managed_buffer_size(certificate_chain_buffer), + &spdm_context->connection_info.peer_used_cert_chain[slot_id].leaf_cert_public_key); + if (!result) { + status = LIBSPDM_STATUS_INVALID_CERT; + goto done; + } +#endif + + if (cert_chain_size != NULL) { + if (*cert_chain_size < + libspdm_get_managed_buffer_size(certificate_chain_buffer)) { + *cert_chain_size = libspdm_get_managed_buffer_size( + certificate_chain_buffer); + status = LIBSPDM_STATUS_BUFFER_FULL; + goto done; + } + cert_chain_capacity = *cert_chain_size; + *cert_chain_size = libspdm_get_managed_buffer_size(certificate_chain_buffer); + if (cert_chain != NULL) { + libspdm_copy_mem(cert_chain, + cert_chain_capacity, + libspdm_get_managed_buffer(certificate_chain_buffer), + libspdm_get_managed_buffer_size(certificate_chain_buffer)); + } + } + + status = LIBSPDM_STATUS_SUCCESS; +done: + free_pool(certificate_chain_buffer); + + return status; +} + +libspdm_return_t libspdm_get_certificate(void *context, uint8_t slot_id, + size_t *cert_chain_size, + void *cert_chain) +{ + return libspdm_get_certificate_choose_length(context, slot_id, + LIBSPDM_MAX_CERT_CHAIN_BLOCK_LEN, + cert_chain_size, cert_chain); +} + +libspdm_return_t libspdm_get_certificate_ex(void *context, uint8_t slot_id, + size_t *cert_chain_size, + void *cert_chain, + const void **trust_anchor, + size_t *trust_anchor_size) +{ + return libspdm_get_certificate_choose_length_ex(context, slot_id, + LIBSPDM_MAX_CERT_CHAIN_BLOCK_LEN, + cert_chain_size, cert_chain, + trust_anchor, trust_anchor_size); +} + +libspdm_return_t libspdm_get_certificate_in_session(void *context, const uint32_t *session_id, + uint8_t slot_id, + size_t *cert_chain_size, + void *cert_chain, + const void **trust_anchor, + size_t *trust_anchor_size) +{ + return libspdm_get_certificate_choose_length_in_session(context, + session_id, + slot_id, + LIBSPDM_MAX_CERT_CHAIN_BLOCK_LEN, + cert_chain_size, cert_chain, + trust_anchor, trust_anchor_size); +} + +libspdm_return_t libspdm_get_certificate_choose_length(void *context, + uint8_t slot_id, + uint16_t length, + size_t *cert_chain_size, + void *cert_chain) +{ + libspdm_context_t *spdm_context; + size_t retry; + libspdm_return_t status; + + spdm_context = context; + spdm_context->crypto_request = true; + retry = spdm_context->retry_times; + do { + status = libspdm_try_get_certificate(spdm_context, NULL, slot_id, length, + cert_chain_size, cert_chain, NULL, NULL); + if (status != LIBSPDM_STATUS_BUSY_PEER) { + return status; + } + } while (retry-- != 0); + + return status; +} + +libspdm_return_t libspdm_get_certificate_choose_length_ex(void *context, + uint8_t slot_id, + uint16_t length, + size_t *cert_chain_size, + void *cert_chain, + const void **trust_anchor, + size_t *trust_anchor_size) +{ + libspdm_context_t *spdm_context; + size_t retry; + libspdm_return_t status; + + spdm_context = context; + spdm_context->crypto_request = true; + retry = spdm_context->retry_times; + do { + status = libspdm_try_get_certificate(spdm_context, NULL, slot_id, length, + cert_chain_size, cert_chain, trust_anchor, + trust_anchor_size); + if (status != LIBSPDM_STATUS_BUSY_PEER) { + return status; + } + } while (retry-- != 0); + + return status; +} + +libspdm_return_t libspdm_get_certificate_choose_length_in_session(void *context, + const uint32_t *session_id, + uint8_t slot_id, + uint16_t length, + size_t *cert_chain_size, + void *cert_chain, + const void **trust_anchor, + size_t *trust_anchor_size) +{ + libspdm_context_t *spdm_context; + size_t retry; + libspdm_return_t status; + + spdm_context = context; + spdm_context->crypto_request = true; + retry = spdm_context->retry_times; + do { + status = libspdm_try_get_certificate(spdm_context, session_id, slot_id, length, + cert_chain_size, cert_chain, trust_anchor, + trust_anchor_size); + if (status != LIBSPDM_STATUS_BUSY_PEER) { + return status; + } + } while (retry-- != 0); + + return status; +} + +#endif /* LIBSPDM_ENABLE_CAPABILITY_CERT_CAP*/ diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/libraries/libspdm/2.3.1/library/spdm_requester_lib/libspdm_req_get_digests.c nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/libraries/libspdm/2.3.1/library/spdm_requester_lib/libspdm_req_get_digests.c --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/libraries/libspdm/2.3.1/library/spdm_requester_lib/libspdm_req_get_digests.c 1970-01-01 00:00:00.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/libraries/libspdm/2.3.1/library/spdm_requester_lib/libspdm_req_get_digests.c 2024-03-05 22:14:16.000000000 +0000 @@ -0,0 +1,273 @@ +/** + * Copyright Notice: + * Copyright 2021-2022 DMTF. All rights reserved. + * License: BSD 3-Clause License. For full text see link: https://github.com/DMTF/libspdm/blob/main/LICENSE.md + **/ + +#include "internal/libspdm_requester_lib.h" + +#if LIBSPDM_ENABLE_CAPABILITY_CERT_CAP + +#pragma pack(1) +typedef struct { + spdm_message_header_t header; + uint8_t digest[LIBSPDM_MAX_HASH_SIZE * SPDM_MAX_SLOT_COUNT]; +} libspdm_digests_response_max_t; +#pragma pack() + +/** + * This function sends GET_DIGESTS and receives DIGESTS * + * + * @param context A pointer to the SPDM context. + * @param slot_mask Bitmask of the slots that contain certificates. + * @param total_digest_buffer A pointer to a destination buffer to store the digests. + * + * @retval LIBSPDM_STATUS_SUCCESS + * GET_DIGETS was sent and DIGESTS was received. + * @retval LIBSPDM_STATUS_INVALID_STATE_LOCAL + * Cannot send GET_DIGESTS due to Requester's state. + * @retval LIBSPDM_STATUS_UNSUPPORTED_CAP + * Cannot send GET_DIGESTS because the Requester's and/or Responder's CERT_CAP = 0. + * @retval LIBSPDM_STATUS_INVALID_MSG_SIZE + * The size of the DIGESTS response is invalid. + * @retval LIBSPDM_STATUS_INVALID_MSG_FIELD + * The DIGESTS response contains one or more invalid fields. + * @retval LIBSPDM_STATUS_ERROR_PEER + * The Responder returned an unexpected error. + * @retval LIBSPDM_STATUS_BUSY_PEER + * The Responder continually returned Busy error messages. + * @retval LIBSPDM_STATUS_RESYNCH_PEER + * The Responder returned a RequestResynch error message. + * @retval LIBSPDM_STATUS_BUFFER_FULL + * The buffer used to store transcripts is exhausted. + * @retval LIBSPDM_STATUS_VERIF_FAIL + * The digest of the stored certificate chain does not match the digest returned by + * the Responder. + * Note: This return value may be removed in the future. + **/ +static libspdm_return_t libspdm_try_get_digest(void *context, const uint32_t *session_id, + uint8_t *slot_mask, + void *total_digest_buffer) +{ + bool result; + libspdm_return_t status; + spdm_get_digest_request_t *spdm_request; + size_t spdm_request_size; + libspdm_digests_response_max_t *spdm_response; + size_t spdm_response_size; + size_t digest_size; + size_t digest_count; + size_t index; + libspdm_context_t *spdm_context; + uint8_t *message; + size_t message_size; + size_t transport_header_size; + libspdm_session_info_t *session_info; + libspdm_session_state_t session_state; + + spdm_context = context; + + /* -=[Verify State Phase]=- */ + if (!libspdm_is_capabilities_flag_supported( + spdm_context, true, 0, + SPDM_GET_CAPABILITIES_RESPONSE_FLAGS_CERT_CAP)) { + return LIBSPDM_STATUS_UNSUPPORTED_CAP; + } + if (spdm_context->connection_info.connection_state < LIBSPDM_CONNECTION_STATE_NEGOTIATED) { + return LIBSPDM_STATUS_INVALID_STATE_LOCAL; + } + + session_info = NULL; + if (session_id != NULL) { + session_info = libspdm_get_session_info_via_session_id(spdm_context, *session_id); + if (session_info == NULL) { + return LIBSPDM_STATUS_INVALID_STATE_LOCAL; + } + session_state = libspdm_secured_message_get_session_state( + session_info->secured_message_context); + if (session_state != LIBSPDM_SESSION_STATE_ESTABLISHED) { + return LIBSPDM_STATUS_INVALID_STATE_LOCAL; + } + } + + libspdm_reset_message_buffer_via_request_code(spdm_context, session_info, SPDM_GET_DIGESTS); + + /* -=[Construct Request Phase]=- */ + transport_header_size = spdm_context->transport_get_header_size(spdm_context); + status = libspdm_acquire_sender_buffer (spdm_context, &message_size, (void **)&message); + if (LIBSPDM_STATUS_IS_ERROR(status)) { + return status; + } + LIBSPDM_ASSERT (message_size >= transport_header_size); + spdm_request = (void *)(message + transport_header_size); + spdm_request_size = message_size - transport_header_size; + + spdm_request->header.spdm_version = libspdm_get_connection_version (spdm_context); + spdm_request->header.request_response_code = SPDM_GET_DIGESTS; + spdm_request->header.param1 = 0; + spdm_request->header.param2 = 0; + spdm_request_size = sizeof(spdm_get_digest_request_t); + + /* -=[Send Request Phase]=- */ + status = libspdm_send_spdm_request(spdm_context, session_id, spdm_request_size, spdm_request); + if (LIBSPDM_STATUS_IS_ERROR(status)) { + libspdm_release_sender_buffer (spdm_context); + return status; + } + libspdm_release_sender_buffer (spdm_context); + spdm_request = (void *)spdm_context->last_spdm_request; + + /* -=[Receive Response Phase]=- */ + status = libspdm_acquire_receiver_buffer (spdm_context, &message_size, (void **)&message); + if (LIBSPDM_STATUS_IS_ERROR(status)) { + return status; + } + LIBSPDM_ASSERT (message_size >= transport_header_size); + spdm_response = (void *)(message); + spdm_response_size = message_size; + + libspdm_zero_mem(spdm_response, spdm_response_size); + status = libspdm_receive_spdm_response( + spdm_context, session_id, &spdm_response_size, (void **)&spdm_response); + if (LIBSPDM_STATUS_IS_ERROR(status)) { + goto receive_done; + } + + /* -=[Validate Response Phase]=- */ + if (spdm_response_size < sizeof(spdm_message_header_t)) { + status = LIBSPDM_STATUS_INVALID_MSG_SIZE; + goto receive_done; + } + if (spdm_response->header.spdm_version != spdm_request->header.spdm_version) { + status = LIBSPDM_STATUS_INVALID_MSG_FIELD; + goto receive_done; + } + if (spdm_response->header.request_response_code == SPDM_ERROR) { + status = libspdm_handle_error_response_main( + spdm_context, session_id, + &spdm_response_size, + (void **)&spdm_response, SPDM_GET_DIGESTS, SPDM_DIGESTS, + sizeof(libspdm_digests_response_max_t)); + if (LIBSPDM_STATUS_IS_ERROR(status)) { + goto receive_done; + } + } else if (spdm_response->header.request_response_code != SPDM_DIGESTS) { + status = LIBSPDM_STATUS_INVALID_MSG_FIELD; + goto receive_done; + } + if (spdm_response_size < sizeof(spdm_digest_response_t)) { + status = LIBSPDM_STATUS_INVALID_MSG_SIZE; + goto receive_done; + } + + digest_size = libspdm_get_hash_size(spdm_context->connection_info.algorithm.base_hash_algo); + if (slot_mask != NULL) { + *slot_mask = spdm_response->header.param2; + } + + digest_count = 0; + for (index = 0; index < SPDM_MAX_SLOT_COUNT; index++) { + if (spdm_response->header.param2 & (1 << index)) { + digest_count++; + } + } + if (digest_count == 0) { + status = LIBSPDM_STATUS_INVALID_MSG_FIELD; + goto receive_done; + } + + if (spdm_response_size < sizeof(spdm_digest_response_t) + digest_count * digest_size) { + status = LIBSPDM_STATUS_INVALID_MSG_SIZE; + goto receive_done; + } + spdm_response_size = sizeof(spdm_digest_response_t) + digest_count * digest_size; + + /* -=[Process Response Phase]=- */ + if (session_id == NULL) { + status = libspdm_append_message_b(spdm_context, spdm_request, spdm_request_size); + if (LIBSPDM_STATUS_IS_ERROR(status)) { + status = LIBSPDM_STATUS_BUFFER_FULL; + goto receive_done; + } + + status = libspdm_append_message_b(spdm_context, spdm_response, spdm_response_size); + if (LIBSPDM_STATUS_IS_ERROR(status)) { + status = LIBSPDM_STATUS_BUFFER_FULL; + goto receive_done; + } + } + + for (index = 0; index < digest_count; index++) { + LIBSPDM_DEBUG((LIBSPDM_DEBUG_INFO, "digest (0x%x) - ", index)); + LIBSPDM_INTERNAL_DUMP_DATA(&spdm_response->digest[digest_size * index], digest_size); + LIBSPDM_DEBUG((LIBSPDM_DEBUG_INFO, "\n")); + } + + result = libspdm_verify_peer_digests(spdm_context, spdm_response->digest, digest_count); + if (!result) { + status = LIBSPDM_STATUS_VERIF_FAIL; + goto receive_done; + } + + if (total_digest_buffer != NULL) { + libspdm_copy_mem(total_digest_buffer, digest_size * digest_count, + spdm_response->digest, digest_size * digest_count); + } + + spdm_context->connection_info.peer_digest_slot_mask = spdm_response->header.param2; + libspdm_copy_mem( + spdm_context->connection_info.peer_total_digest_buffer, + sizeof(spdm_context->connection_info.peer_total_digest_buffer), + spdm_response->digest, digest_size * digest_count); + + /* -=[Update State Phase]=- */ + if (spdm_context->connection_info.connection_state < LIBSPDM_CONNECTION_STATE_AFTER_DIGESTS) { + spdm_context->connection_info.connection_state = LIBSPDM_CONNECTION_STATE_AFTER_DIGESTS; + } + status = LIBSPDM_STATUS_SUCCESS; + +receive_done: + libspdm_release_receiver_buffer (spdm_context); + return status; +} + +libspdm_return_t libspdm_get_digest(void *context, uint8_t *slot_mask, void *total_digest_buffer) +{ + libspdm_context_t *spdm_context; + size_t retry; + libspdm_return_t status; + + spdm_context = context; + spdm_context->crypto_request = true; + retry = spdm_context->retry_times; + do { + status = libspdm_try_get_digest(spdm_context, NULL, slot_mask, total_digest_buffer); + if (status != LIBSPDM_STATUS_BUSY_PEER) { + return status; + } + } while (retry-- != 0); + + return status; +} + +libspdm_return_t libspdm_get_digest_in_session(void *context, const uint32_t *session_id, + uint8_t *slot_mask, void *total_digest_buffer) +{ + libspdm_context_t *spdm_context; + size_t retry; + libspdm_return_t status; + + spdm_context = context; + spdm_context->crypto_request = true; + retry = spdm_context->retry_times; + do { + status = libspdm_try_get_digest(spdm_context, session_id, slot_mask, total_digest_buffer); + if (status != LIBSPDM_STATUS_BUSY_PEER) { + return status; + } + } while (retry-- != 0); + + return status; +} + +#endif /*LIBSPDM_ENABLE_CAPABILITY_CERT_CAP*/ diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/libraries/libspdm/2.3.1/library/spdm_requester_lib/libspdm_req_get_measurements.c nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/libraries/libspdm/2.3.1/library/spdm_requester_lib/libspdm_req_get_measurements.c --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/libraries/libspdm/2.3.1/library/spdm_requester_lib/libspdm_req_get_measurements.c 1970-01-01 00:00:00.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/libraries/libspdm/2.3.1/library/spdm_requester_lib/libspdm_req_get_measurements.c 2024-03-05 22:14:17.000000000 +0000 @@ -0,0 +1,679 @@ +/** + * Copyright Notice: + * Copyright 2021-2022 DMTF. All rights reserved. + * License: BSD 3-Clause License. For full text see link: https://github.com/DMTF/libspdm/blob/main/LICENSE.md + **/ + +#include "internal/libspdm_requester_lib.h" + +#if LIBSPDM_ENABLE_CAPABILITY_MEAS_CAP + +bool libspdm_verify_measurement_signature(libspdm_context_t *spdm_context, + libspdm_session_info_t *session_info, + const void *sign_data, + size_t sign_data_size) +{ + bool result; + const uint8_t *cert_buffer; + size_t cert_buffer_size; + void *context; + const uint8_t *cert_chain_data; + size_t cert_chain_data_size; +#if LIBSPDM_RECORD_TRANSCRIPT_DATA_SUPPORT + libspdm_large_managed_buffer_t l1l2; + uint8_t *l1l2_buffer; + size_t l1l2_buffer_size; +#else + uint8_t l1l2_hash[LIBSPDM_MAX_HASH_SIZE]; + size_t l1l2_hash_size; + uint8_t slot_id; +#endif + +#if LIBSPDM_RECORD_TRANSCRIPT_DATA_SUPPORT + result = libspdm_calculate_l1l2(spdm_context, session_info, &l1l2); +#else + l1l2_hash_size = sizeof(l1l2_hash); + result = libspdm_calculate_l1l2_hash(spdm_context, session_info, &l1l2_hash_size, l1l2_hash); +#endif + libspdm_reset_message_m(spdm_context, session_info); + if (!result) { + return false; + } + +#if LIBSPDM_RECORD_TRANSCRIPT_DATA_SUPPORT + l1l2_buffer = libspdm_get_managed_buffer(&l1l2); + l1l2_buffer_size = libspdm_get_managed_buffer_size(&l1l2); + + result = libspdm_get_peer_cert_chain_data( + spdm_context, (const void **)&cert_chain_data, &cert_chain_data_size); + if (!result) { + return false; + } + + /* Get leaf cert from cert chain*/ + result = libspdm_x509_get_cert_from_cert_chain(cert_chain_data, + cert_chain_data_size, -1, + &cert_buffer, &cert_buffer_size); + if (!result) { + return false; + } + + result = libspdm_asym_get_public_key_from_x509( + spdm_context->connection_info.algorithm.base_asym_algo, + cert_buffer, cert_buffer_size, &context); + if (!result) { + return false; + } + + result = libspdm_asym_verify( + spdm_context->connection_info.version, SPDM_MEASUREMENTS, + spdm_context->connection_info.algorithm.base_asym_algo, + spdm_context->connection_info.algorithm.base_hash_algo, context, + l1l2_buffer, l1l2_buffer_size, sign_data, sign_data_size); + libspdm_asym_free(spdm_context->connection_info.algorithm.base_asym_algo, context); +#else + slot_id = spdm_context->connection_info.peer_used_cert_chain_slot_id; + LIBSPDM_ASSERT(slot_id < SPDM_MAX_SLOT_COUNT); + if (spdm_context->connection_info.peer_used_cert_chain[slot_id].leaf_cert_public_key != NULL) { + result = libspdm_asym_verify_hash( + spdm_context->connection_info.version, SPDM_MEASUREMENTS, + spdm_context->connection_info.algorithm.base_asym_algo, + spdm_context->connection_info.algorithm.base_hash_algo, + spdm_context->connection_info.peer_used_cert_chain[slot_id].leaf_cert_public_key, + l1l2_hash, l1l2_hash_size, sign_data, sign_data_size); + if (!result) { + LIBSPDM_DEBUG((LIBSPDM_DEBUG_INFO, "!!! verify_measurement_signature - FAIL !!!\n")); + return false; + } + + LIBSPDM_DEBUG((LIBSPDM_DEBUG_INFO, "!!! verify_measurement_signature - PASS !!!\n")); + return true; + } + + result = libspdm_get_peer_cert_chain_data( + spdm_context, (const void **)&cert_chain_data, &cert_chain_data_size); + if (!result) { + return false; + } + + /* Get leaf cert from cert chain */ + result = libspdm_x509_get_cert_from_cert_chain(cert_chain_data, + cert_chain_data_size, -1, + &cert_buffer, &cert_buffer_size); + if (!result) { + return false; + } + + result = libspdm_asym_get_public_key_from_x509( + spdm_context->connection_info.algorithm.base_asym_algo, + cert_buffer, cert_buffer_size, &context); + if (!result) { + return false; + } + + result = libspdm_asym_verify_hash( + spdm_context->connection_info.version, SPDM_MEASUREMENTS, + spdm_context->connection_info.algorithm.base_asym_algo, + spdm_context->connection_info.algorithm.base_hash_algo, context, + l1l2_hash, l1l2_hash_size, sign_data, sign_data_size); + libspdm_asym_free(spdm_context->connection_info.algorithm.base_asym_algo, context); +#endif + if (!result) { + LIBSPDM_DEBUG((LIBSPDM_DEBUG_INFO, "!!! verify_measurement_signature - FAIL !!!\n")); + return false; + } + + LIBSPDM_DEBUG((LIBSPDM_DEBUG_INFO, "!!! verify_measurement_signature - PASS !!!\n")); + return true; +} + +/** + * This function sends GET_MEASUREMENT to get measurement from the device. + * If the signature is requested this function verifies the signature of the measurement. + * + * @param context A pointer to the SPDM context. + * @param session_id Indicates if it is a secured message protected via SPDM session. + * If session_id is NULL, it is a normal message. + * If session_id is not NULL, it is a secured message. + * @param request_attribute The request attribute of the request message. + * @param measurement_operation The measurement operation of the request message. + * @param slot_id The number of slot for the certificate chain. + * @param content_changed The measurement content changed output param. + * @param number_of_blocks The number of blocks of the measurement record. + * @param measurement_record_length On input, indicate the size in bytes of the destination buffer + * to store the measurement record. + * On output, indicate the size in bytes of the measurement record. + * @param measurement_record A pointer to a destination buffer to store the measurement record. + * @param requester_nonce_in If not NULL, a buffer that holds the requester nonce (32 bytes) + * @param requester_nonce If not NULL, a buffer to hold the requester nonce (32 bytes). + * @param responder_nonce If not NULL, a buffer to hold the responder nonce (32 bytes). + * + **/ +static libspdm_return_t libspdm_try_get_measurement(void *context, const uint32_t *session_id, + uint8_t request_attribute, + uint8_t measurement_operation, + uint8_t slot_id_param, + uint8_t *content_changed, + uint8_t *number_of_blocks, + uint32_t *measurement_record_length, + void *measurement_record, + const void *requester_nonce_in, + void *requester_nonce, + void *responder_nonce) +{ + bool result; + libspdm_return_t status; + spdm_get_measurements_request_t *spdm_request; + size_t spdm_request_size; + spdm_measurements_response_t *spdm_response; + size_t spdm_response_size; + uint32_t measurement_record_data_length; + uint8_t *measurement_record_data; + spdm_measurement_block_common_header_t *measurement_block_header; + uint32_t measurement_block_size; + uint8_t measurement_block_count; + uint8_t *ptr; + void *nonce; + uint16_t opaque_length; + void *signature; + size_t signature_size; + libspdm_context_t *spdm_context; + libspdm_session_info_t *session_info; + libspdm_session_state_t session_state; + uint8_t *message; + size_t message_size; + size_t transport_header_size; + + spdm_context = context; + + /* -=[Check Parameters Phase]=- */ + LIBSPDM_ASSERT((slot_id_param < SPDM_MAX_SLOT_COUNT) || (slot_id_param == 0xF)); + LIBSPDM_ASSERT((slot_id_param != 0xf) || + (spdm_context->local_context.peer_cert_chain_provision_size != 0)); + + /* -=[Verify State Phase]=- */ + if (!libspdm_is_capabilities_flag_supported( + spdm_context, true, 0, + SPDM_GET_CAPABILITIES_RESPONSE_FLAGS_MEAS_CAP)) { + return LIBSPDM_STATUS_UNSUPPORTED_CAP; + } + + LIBSPDM_ASSERT(spdm_context->local_context.algorithm.measurement_spec != 0); + + if (spdm_context->connection_info.connection_state < LIBSPDM_CONNECTION_STATE_NEGOTIATED) { + return LIBSPDM_STATUS_INVALID_STATE_LOCAL; + } + + if (session_id == NULL) { + session_info = NULL; + } else { + session_info = libspdm_get_session_info_via_session_id(spdm_context, *session_id); + if (session_info == NULL) { + return LIBSPDM_STATUS_INVALID_STATE_LOCAL; + } + session_state = libspdm_secured_message_get_session_state( + session_info->secured_message_context); + if (session_state != LIBSPDM_SESSION_STATE_ESTABLISHED) { + return LIBSPDM_STATUS_INVALID_STATE_LOCAL; + } + } + + if (libspdm_is_capabilities_flag_supported( + spdm_context, true, 0, + SPDM_GET_CAPABILITIES_RESPONSE_FLAGS_MEAS_CAP_NO_SIG) && + ((request_attribute & SPDM_GET_MEASUREMENTS_REQUEST_ATTRIBUTES_GENERATE_SIGNATURE) != 0)) { + return LIBSPDM_STATUS_INVALID_PARAMETER; + } + + if ((request_attribute & SPDM_GET_MEASUREMENTS_REQUEST_ATTRIBUTES_GENERATE_SIGNATURE) != 0) { + signature_size = libspdm_get_asym_signature_size( + spdm_context->connection_info.algorithm.base_asym_algo); + } else { + signature_size = 0; + } + + libspdm_reset_message_buffer_via_request_code(spdm_context, NULL, SPDM_GET_MEASUREMENTS); + + /* -=[Construct Request Phase]=- */ + if (slot_id_param != 0xf) { + spdm_context->connection_info.peer_used_cert_chain_slot_id = slot_id_param; + } else { + spdm_context->connection_info.peer_used_cert_chain_slot_id = + spdm_context->local_context.provisioned_slot_id; + } + transport_header_size = spdm_context->transport_get_header_size(spdm_context); + status = libspdm_acquire_sender_buffer (spdm_context, &message_size, (void **)&message); + if (LIBSPDM_STATUS_IS_ERROR(status)) { + return status; + } + LIBSPDM_ASSERT (message_size >= transport_header_size); + spdm_request = (void *)(message + transport_header_size); + spdm_request_size = message_size - transport_header_size; + + spdm_request->header.spdm_version = libspdm_get_connection_version (spdm_context); + spdm_request->header.request_response_code = SPDM_GET_MEASUREMENTS; + spdm_request->header.param1 = request_attribute; + spdm_request->header.param2 = measurement_operation; + if ((request_attribute & SPDM_GET_MEASUREMENTS_REQUEST_ATTRIBUTES_GENERATE_SIGNATURE) != 0) { + if (spdm_request->header.spdm_version >= SPDM_MESSAGE_VERSION_11) { + spdm_request_size = sizeof(spdm_get_measurements_request_t); + } else { + spdm_request_size = sizeof(spdm_get_measurements_request_t) - + sizeof(spdm_request->slot_id_param); + } + + if (requester_nonce_in == NULL) { + if(!libspdm_get_random_number(SPDM_NONCE_SIZE, spdm_request->nonce)) { + libspdm_release_sender_buffer (spdm_context); + return LIBSPDM_STATUS_LOW_ENTROPY; + } + } else { + libspdm_copy_mem(spdm_request->nonce, sizeof(spdm_request->nonce), + requester_nonce_in, SPDM_NONCE_SIZE); + } + LIBSPDM_DEBUG((LIBSPDM_DEBUG_INFO, "ClientNonce - ")); + LIBSPDM_INTERNAL_DUMP_DATA(spdm_request->nonce, SPDM_NONCE_SIZE); + LIBSPDM_DEBUG((LIBSPDM_DEBUG_INFO, "\n")); + spdm_request->slot_id_param = slot_id_param; + + if (requester_nonce != NULL) { + libspdm_copy_mem(requester_nonce, SPDM_NONCE_SIZE, + spdm_request->nonce, SPDM_NONCE_SIZE); + } + } else { + spdm_request_size = sizeof(spdm_request->header); + + if (requester_nonce != NULL) { + libspdm_zero_mem (requester_nonce, SPDM_NONCE_SIZE); + } + } + + /* -=[Send Request Phase]=- */ + status = libspdm_send_spdm_request(spdm_context, session_id, spdm_request_size, spdm_request); + if (LIBSPDM_STATUS_IS_ERROR(status)) { + libspdm_release_sender_buffer (spdm_context); + return status; + } + libspdm_release_sender_buffer (spdm_context); + spdm_request = (void *)spdm_context->last_spdm_request; + + /* -=[Receive Response Phase]=- */ + status = libspdm_acquire_receiver_buffer (spdm_context, &message_size, (void **)&message); + if (LIBSPDM_STATUS_IS_ERROR(status)) { + return status; + } + LIBSPDM_ASSERT (message_size >= transport_header_size); + spdm_response = (void *)(message); + spdm_response_size = message_size; + + libspdm_zero_mem(spdm_response, spdm_response_size); + status = libspdm_receive_spdm_response( + spdm_context, session_id, &spdm_response_size, (void **)&spdm_response); + if (LIBSPDM_STATUS_IS_ERROR(status)) { + goto receive_done; + } + + /* -=[Validate Response Phase]=- */ + if (spdm_response_size < sizeof(spdm_message_header_t)) { + status = LIBSPDM_STATUS_INVALID_MSG_SIZE; + goto receive_done; + } + if (spdm_response->header.spdm_version != spdm_request->header.spdm_version) { + status = LIBSPDM_STATUS_INVALID_MSG_FIELD; + goto receive_done; + } + if (spdm_response->header.request_response_code == SPDM_ERROR) { + status = libspdm_handle_error_response_main( + spdm_context, session_id, + &spdm_response_size, (void **)&spdm_response, + SPDM_GET_MEASUREMENTS, SPDM_MEASUREMENTS, + message_size); + if (LIBSPDM_STATUS_IS_ERROR(status)) { + goto receive_done; + } + } else if (spdm_response->header.request_response_code != SPDM_MEASUREMENTS) { + libspdm_reset_message_m(spdm_context, session_info); + status = LIBSPDM_STATUS_INVALID_MSG_FIELD; + goto receive_done; + } + if (spdm_response_size < sizeof(spdm_measurements_response_t)) { + status = LIBSPDM_STATUS_INVALID_MSG_SIZE; + goto receive_done; + } + if (measurement_operation == + SPDM_GET_MEASUREMENTS_REQUEST_MEASUREMENT_OPERATION_TOTAL_NUMBER_OF_MEASUREMENTS) { + if (spdm_response->number_of_blocks != 0) { + libspdm_reset_message_m(spdm_context, session_info); + status = LIBSPDM_STATUS_INVALID_MSG_FIELD; + goto receive_done; + } + } else if (measurement_operation == + SPDM_GET_MEASUREMENTS_REQUEST_MEASUREMENT_OPERATION_ALL_MEASUREMENTS) { + if (spdm_response->number_of_blocks == 0) { + status = LIBSPDM_STATUS_INVALID_MSG_FIELD; + goto receive_done; + } + } else { + if (spdm_response->number_of_blocks != 1) { + status = LIBSPDM_STATUS_INVALID_MSG_FIELD; + goto receive_done; + } + } + + measurement_record_data_length = libspdm_read_uint24(spdm_response->measurement_record_length); + if (measurement_operation == + SPDM_GET_MEASUREMENTS_REQUEST_MEASUREMENT_OPERATION_TOTAL_NUMBER_OF_MEASUREMENTS) { + if (measurement_record_data_length != 0) { + libspdm_reset_message_m(spdm_context, session_info); + status = LIBSPDM_STATUS_INVALID_MSG_FIELD; + goto receive_done; + } + } else { + if (spdm_response_size < + sizeof(spdm_measurements_response_t) + + measurement_record_data_length) { + status = LIBSPDM_STATUS_INVALID_MSG_SIZE; + goto receive_done; + } + LIBSPDM_DEBUG((LIBSPDM_DEBUG_INFO, "measurement_record_length - 0x%06x\n", + measurement_record_data_length)); + } + + measurement_record_data = (void *)(spdm_response + 1); + + if ((request_attribute & SPDM_GET_MEASUREMENTS_REQUEST_ATTRIBUTES_GENERATE_SIGNATURE) != 0) { + if (spdm_response_size < + sizeof(spdm_measurements_response_t) + + measurement_record_data_length + SPDM_NONCE_SIZE + sizeof(uint16_t)) { + libspdm_reset_message_m(spdm_context, session_info); + status = LIBSPDM_STATUS_INVALID_MSG_SIZE; + goto receive_done; + } + if ((spdm_response->header.spdm_version >= SPDM_MESSAGE_VERSION_11) && + ((spdm_response->header.param2 & SPDM_MEASUREMENTS_RESPONSE_SLOT_ID_MASK) + != slot_id_param)) { + libspdm_reset_message_m(spdm_context, session_info); + status = LIBSPDM_STATUS_INVALID_MSG_FIELD; + goto receive_done; + } + ptr = measurement_record_data + measurement_record_data_length; + nonce = ptr; + LIBSPDM_DEBUG((LIBSPDM_DEBUG_INFO, "nonce (0x%x) - ", SPDM_NONCE_SIZE)); + LIBSPDM_INTERNAL_DUMP_DATA(nonce, SPDM_NONCE_SIZE); + LIBSPDM_DEBUG((LIBSPDM_DEBUG_INFO, "\n")); + ptr += SPDM_NONCE_SIZE; + if (responder_nonce != NULL) { + libspdm_copy_mem(responder_nonce, SPDM_NONCE_SIZE, nonce, SPDM_NONCE_SIZE); + } + + opaque_length = *(uint16_t *)ptr; + if (opaque_length > SPDM_MAX_OPAQUE_DATA_SIZE) { + status = LIBSPDM_STATUS_INVALID_MSG_FIELD; + goto receive_done; + } + ptr += sizeof(uint16_t); + + if (spdm_response_size < + sizeof(spdm_measurements_response_t) + + measurement_record_data_length + SPDM_NONCE_SIZE + + sizeof(uint16_t) + opaque_length + signature_size) { + status = LIBSPDM_STATUS_INVALID_MSG_SIZE; + goto receive_done; + } + spdm_response_size = sizeof(spdm_measurements_response_t) + + measurement_record_data_length + + SPDM_NONCE_SIZE + sizeof(uint16_t) + + opaque_length + signature_size; + + /* -=[Process Response Phase]=- */ + status = libspdm_append_message_m(spdm_context, session_info, spdm_request, + spdm_request_size); + if (LIBSPDM_STATUS_IS_ERROR(status)) { + status = LIBSPDM_STATUS_BUFFER_FULL; + goto receive_done; + } + + status = libspdm_append_message_m(spdm_context, session_info, spdm_response, + spdm_response_size - signature_size); + if (LIBSPDM_STATUS_IS_ERROR(status)) { + libspdm_reset_message_m(spdm_context, session_info); + status = LIBSPDM_STATUS_BUFFER_FULL; + goto receive_done; + } + + LIBSPDM_DEBUG_CODE( + void *opaque; + opaque = ptr; + LIBSPDM_DEBUG((LIBSPDM_DEBUG_INFO, "opaque (0x%x):\n", opaque_length)); + LIBSPDM_INTERNAL_DUMP_HEX(opaque, opaque_length); + ); + ptr += opaque_length; + + signature = ptr; + LIBSPDM_DEBUG((LIBSPDM_DEBUG_INFO, "signature (0x%x):\n", signature_size)); + LIBSPDM_INTERNAL_DUMP_HEX(signature, signature_size); + + result = libspdm_verify_measurement_signature( + spdm_context, session_info, signature, signature_size); + if (!result) { + libspdm_reset_message_m(spdm_context, session_info); + status = LIBSPDM_STATUS_VERIF_FAIL; + goto receive_done; + } + + libspdm_reset_message_m(spdm_context, session_info); + } else { + if (spdm_response_size < + sizeof(spdm_measurements_response_t) + + measurement_record_data_length + sizeof(uint16_t)) { + status = LIBSPDM_STATUS_INVALID_MSG_SIZE; + goto receive_done; + } + ptr = measurement_record_data + measurement_record_data_length; + + nonce = ptr; + LIBSPDM_DEBUG((LIBSPDM_DEBUG_INFO, "nonce (0x%x) - ", SPDM_NONCE_SIZE)); + LIBSPDM_INTERNAL_DUMP_DATA(nonce, SPDM_NONCE_SIZE); + LIBSPDM_DEBUG((LIBSPDM_DEBUG_INFO, "\n")); + ptr += SPDM_NONCE_SIZE; + if (responder_nonce != NULL) { + libspdm_copy_mem(responder_nonce, SPDM_NONCE_SIZE, nonce, SPDM_NONCE_SIZE); + } + + opaque_length = *(uint16_t *)ptr; + if (opaque_length > SPDM_MAX_OPAQUE_DATA_SIZE) { + status = LIBSPDM_STATUS_INVALID_MSG_FIELD; + goto receive_done; + } + ptr += sizeof(uint16_t); + + if (spdm_response_size < + sizeof(spdm_measurements_response_t) + + measurement_record_data_length + SPDM_NONCE_SIZE + + sizeof(uint16_t) + opaque_length) { + status = LIBSPDM_STATUS_INVALID_MSG_SIZE; + goto receive_done; + } + spdm_response_size = sizeof(spdm_measurements_response_t) + + measurement_record_data_length + + SPDM_NONCE_SIZE + sizeof(uint16_t) + + opaque_length; + + status = libspdm_append_message_m(spdm_context, session_info, spdm_request, + spdm_request_size); + if (LIBSPDM_STATUS_IS_ERROR(status)) { + status = LIBSPDM_STATUS_BUFFER_FULL; + goto receive_done; + } + + status = libspdm_append_message_m(spdm_context, session_info, spdm_response, + spdm_response_size); + if (LIBSPDM_STATUS_IS_ERROR(status)) { + libspdm_reset_message_m(spdm_context, session_info); + status = LIBSPDM_STATUS_BUFFER_FULL; + goto receive_done; + } + } + + if (content_changed != NULL) { + *content_changed = 0; + if ((spdm_response->header.spdm_version >= SPDM_MESSAGE_VERSION_12) && + ((request_attribute & + SPDM_GET_MEASUREMENTS_REQUEST_ATTRIBUTES_GENERATE_SIGNATURE) != 0)) { + *content_changed = + (spdm_response->header.param2 & SPDM_MEASUREMENTS_RESPONSE_CONTENT_CHANGE_MASK); + } + } + if (measurement_operation == + SPDM_GET_MEASUREMENTS_REQUEST_MEASUREMENT_OPERATION_TOTAL_NUMBER_OF_MEASUREMENTS) { + *number_of_blocks = spdm_response->header.param1; + if (*number_of_blocks == 0xFF) { + /* the number of block cannot be 0xFF, because index 0xFF will brings confusing.*/ + status = LIBSPDM_STATUS_INVALID_MSG_FIELD; + goto receive_done; + } + if (*number_of_blocks == 0x0) { + /* the number of block cannot be 0x0, because a responder without measurement should clear capability flags.*/ + status = LIBSPDM_STATUS_INVALID_MSG_FIELD; + goto receive_done; + } + } else { + *number_of_blocks = spdm_response->number_of_blocks; + if (*measurement_record_length < measurement_record_data_length) { + status = LIBSPDM_STATUS_BUFFER_TOO_SMALL; + goto receive_done; + } + if (measurement_record_data_length < sizeof(spdm_measurement_block_common_header_t)) { + status = LIBSPDM_STATUS_INVALID_MSG_FIELD; + goto receive_done; + } + + measurement_block_size = 0; + measurement_block_count = 1; + while (measurement_block_size < measurement_record_data_length) { + measurement_block_header = + (spdm_measurement_block_common_header_t *)&measurement_record_data + [measurement_block_size]; + if (measurement_block_header->measurement_size > + measurement_record_data_length - + ((uint8_t *)measurement_block_header - + (uint8_t *)measurement_record_data)) { + status = LIBSPDM_STATUS_INVALID_MSG_FIELD; + goto receive_done; + } + if (measurement_block_header->measurement_specification == 0 || + (measurement_block_header->measurement_specification & + (measurement_block_header->measurement_specification - 1))) { + status = LIBSPDM_STATUS_INVALID_MSG_FIELD; + goto receive_done; + } + if (measurement_block_header->measurement_specification != + spdm_context->connection_info.algorithm.measurement_spec) { + status = LIBSPDM_STATUS_INVALID_MSG_FIELD; + goto receive_done; + } + if (measurement_block_header->index == 0 || measurement_block_header->index == 0xFF) { + status = LIBSPDM_STATUS_INVALID_MSG_FIELD; + goto receive_done; + } + if (measurement_operation != + SPDM_GET_MEASUREMENTS_REQUEST_MEASUREMENT_OPERATION_ALL_MEASUREMENTS) { + if (measurement_block_header->index != measurement_operation) { + status = LIBSPDM_STATUS_INVALID_MSG_FIELD; + goto receive_done; + } + } + if (measurement_block_count > *number_of_blocks) { + status = LIBSPDM_STATUS_INVALID_MSG_FIELD; + goto receive_done; + } + measurement_block_count++; + measurement_block_size = (uint32_t)( + measurement_block_size + + sizeof(spdm_measurement_block_common_header_t) + + measurement_block_header->measurement_size); + } + + *measurement_record_length = measurement_record_data_length; + libspdm_copy_mem(measurement_record, + measurement_record_data_length, + measurement_record_data, + measurement_record_data_length); + } + + status = LIBSPDM_STATUS_SUCCESS; + + /* -=[Log Message Phase]=- */ + #if LIBSPDM_ENABLE_MSG_LOG + libspdm_append_msg_log(spdm_context, spdm_response, spdm_response_size); + #endif /* LIBSPDM_ENABLE_MSG_LOG */ + +receive_done: + libspdm_release_receiver_buffer (spdm_context); + return status; +} + +libspdm_return_t libspdm_get_measurement(void *context, const uint32_t *session_id, + uint8_t request_attribute, + uint8_t measurement_operation, + uint8_t slot_id_param, + uint8_t *content_changed, + uint8_t *number_of_blocks, + uint32_t *measurement_record_length, + void *measurement_record) +{ + libspdm_context_t *spdm_context; + size_t retry; + libspdm_return_t status; + + spdm_context = context; + spdm_context->crypto_request = true; + retry = spdm_context->retry_times; + do { + status = libspdm_try_get_measurement( + spdm_context, session_id, request_attribute, + measurement_operation, slot_id_param, content_changed, number_of_blocks, + measurement_record_length, measurement_record, NULL, NULL, NULL); + if (LIBSPDM_STATUS_BUSY_PEER != status) { + return status; + } + } while (retry-- != 0); + + return status; +} + +libspdm_return_t libspdm_get_measurement_ex(void *context, const uint32_t *session_id, + uint8_t request_attribute, + uint8_t measurement_operation, + uint8_t slot_id_param, + uint8_t *content_changed, + uint8_t *number_of_blocks, + uint32_t *measurement_record_length, + void *measurement_record, + const void *requester_nonce_in, + void *requester_nonce, + void *responder_nonce) +{ + libspdm_context_t *spdm_context; + size_t retry; + libspdm_return_t status; + + spdm_context = context; + spdm_context->crypto_request = true; + retry = spdm_context->retry_times; + do { + status = libspdm_try_get_measurement( + spdm_context, session_id, request_attribute, + measurement_operation, slot_id_param, content_changed, number_of_blocks, + measurement_record_length, measurement_record, + requester_nonce_in, + requester_nonce, responder_nonce); + if (status != LIBSPDM_STATUS_BUSY_PEER) { + return status; + } + } while (retry-- != 0); + + return status; +} + +#endif /* LIBSPDM_ENABLE_CAPABILITY_MEAS_CAP*/ diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/libraries/libspdm/2.3.1/library/spdm_requester_lib/libspdm_req_get_version.c nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/libraries/libspdm/2.3.1/library/spdm_requester_lib/libspdm_req_get_version.c --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/libraries/libspdm/2.3.1/library/spdm_requester_lib/libspdm_req_get_version.c 1970-01-01 00:00:00.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/libraries/libspdm/2.3.1/library/spdm_requester_lib/libspdm_req_get_version.c 2024-03-05 22:14:17.000000000 +0000 @@ -0,0 +1,222 @@ +/** + * Copyright Notice: + * Copyright 2021-2022 DMTF. All rights reserved. + * License: BSD 3-Clause License. For full text see link: https://github.com/DMTF/libspdm/blob/main/LICENSE.md + **/ + +#include "internal/libspdm_requester_lib.h" + +#pragma pack(1) +typedef struct { + spdm_message_header_t header; + uint8_t reserved; + uint8_t version_number_entry_count; + spdm_version_number_t version_number_entry[LIBSPDM_MAX_VERSION_COUNT]; +} libspdm_version_response_max_t; +#pragma pack() + +/** + * This function sends GET_VERSION and receives VERSION. + * + * @param spdm_context A pointer to the SPDM context. + * @param version_count The number of SPDM versions that the Responder supports. + * @param VersionNumberEntries The list of SPDM versions that the Responder supports. + * + * @retval LIBSPDM_STATUS_SUCCESS + * GET_VERSION was sent and VERSION was received. + * @retval LIBSPDM_STATUS_INVALID_MSG_SIZE + * The size of the VERSION response is invalid. + * @retval LIBSPDM_STATUS_INVALID_MSG_FIELD + * The VERSION response contains one or more invalid fields. + * @retval LIBSPDM_STATUS_ERROR_PEER + * The Responder returned an unexpected error. + * @retval LIBSPDM_STATUS_BUSY_PEER + * The Responder continually returned Busy error messages. + * @retval LIBSPDM_STATUS_RESYNCH_PEER + * The Responder returned a RequestResynch error message. + * @retval LIBSPDM_STATUS_NEGOTIATION_FAIL + * The Requester and Responder do not support a common SPDM version. + **/ +static libspdm_return_t libspdm_try_get_version(libspdm_context_t *spdm_context, + uint8_t *version_number_entry_count, + spdm_version_number_t *version_number_entry) +{ + libspdm_return_t status; + bool result; + spdm_get_version_request_t *spdm_request; + size_t spdm_request_size; + libspdm_version_response_max_t *spdm_response; + size_t spdm_response_size; + spdm_version_number_t common_version; + uint8_t *message; + size_t message_size; + size_t transport_header_size; + + /* -=[Set State Phase]=- */ + libspdm_reset_message_a(spdm_context); + libspdm_reset_message_b(spdm_context); + libspdm_reset_message_c(spdm_context); + libspdm_reset_context(spdm_context); + libspdm_reset_message_buffer_via_request_code(spdm_context, NULL, SPDM_GET_VERSION); + + /* -=[Construct Request Phase]=- */ + transport_header_size = spdm_context->transport_get_header_size(spdm_context); + status = libspdm_acquire_sender_buffer (spdm_context, &message_size, (void **)&message); + if (LIBSPDM_STATUS_IS_ERROR(status)) { + return status; + } + LIBSPDM_ASSERT (message_size >= transport_header_size); + spdm_request = (void *)(message + transport_header_size); + spdm_request_size = message_size - transport_header_size; + + spdm_request->header.spdm_version = SPDM_MESSAGE_VERSION_10; + spdm_request->header.request_response_code = SPDM_GET_VERSION; + spdm_request->header.param1 = 0; + spdm_request->header.param2 = 0; + spdm_request_size = sizeof(spdm_get_version_request_t); + + /* -=[Send Request Phase]=- */ + status = libspdm_send_spdm_request(spdm_context, NULL, spdm_request_size, spdm_request); + if (LIBSPDM_STATUS_IS_ERROR(status)) { + libspdm_release_sender_buffer (spdm_context); + return status; + } + libspdm_release_sender_buffer (spdm_context); + spdm_request = (void *)spdm_context->last_spdm_request; + + /* -=[Receive Response Phase]=- */ + status = libspdm_acquire_receiver_buffer (spdm_context, &message_size, (void **)&message); + if (LIBSPDM_STATUS_IS_ERROR(status)) { + return status; + } + LIBSPDM_ASSERT (message_size >= transport_header_size); + spdm_response = (void *)(message); + spdm_response_size = message_size; + + libspdm_zero_mem(spdm_response, spdm_response_size); + status = libspdm_receive_spdm_response(spdm_context, NULL, &spdm_response_size, + (void **)&spdm_response); + if (LIBSPDM_STATUS_IS_ERROR(status)) { + goto receive_done; + } + + /* -=[Validate Response Phase]=- */ + if (spdm_response_size < sizeof(spdm_message_header_t)) { + status = LIBSPDM_STATUS_INVALID_MSG_SIZE; + goto receive_done; + } + if (spdm_response->header.spdm_version != SPDM_MESSAGE_VERSION_10) { + status = LIBSPDM_STATUS_INVALID_MSG_FIELD; + goto receive_done; + } + if (spdm_response->header.request_response_code == SPDM_ERROR) { + status = libspdm_handle_simple_error_response(spdm_context, spdm_response->header.param1); + if (LIBSPDM_STATUS_IS_ERROR(status)) { + goto receive_done; + } + } else if (spdm_response->header.request_response_code != SPDM_VERSION) { + status = LIBSPDM_STATUS_INVALID_MSG_FIELD; + goto receive_done; + } + if (spdm_response_size < sizeof(spdm_version_response_t)) { + status = LIBSPDM_STATUS_INVALID_MSG_SIZE; + goto receive_done; + } + if (spdm_response->version_number_entry_count > LIBSPDM_MAX_VERSION_COUNT) { + status = LIBSPDM_STATUS_INVALID_MSG_FIELD; + goto receive_done; + } + if (spdm_response->version_number_entry_count == 0) { + status = LIBSPDM_STATUS_INVALID_MSG_FIELD; + goto receive_done; + } + if (spdm_response_size < sizeof(spdm_version_response_t) + + spdm_response->version_number_entry_count * sizeof(spdm_version_number_t)) { + status = LIBSPDM_STATUS_INVALID_MSG_SIZE; + goto receive_done; + } + spdm_response_size = sizeof(spdm_version_response_t) + + spdm_response->version_number_entry_count * sizeof(spdm_version_number_t); + + /* -=[Process Response Phase]=- */ + status = libspdm_append_message_a(spdm_context, spdm_request, spdm_request_size); + if (LIBSPDM_STATUS_IS_ERROR(status)) { + goto receive_done; + } + + status = libspdm_append_message_a(spdm_context, spdm_response, spdm_response_size); + if (LIBSPDM_STATUS_IS_ERROR(status)) { + libspdm_reset_message_a(spdm_context); + goto receive_done; + } + + result = libspdm_negotiate_connection_version ( + &common_version, + spdm_context->local_context.version.spdm_version, + spdm_context->local_context.version.spdm_version_count, + spdm_response->version_number_entry, + spdm_response->version_number_entry_count); + if (result == false) { + libspdm_reset_message_a(spdm_context); + status = LIBSPDM_STATUS_NEGOTIATION_FAIL; + goto receive_done; + } + + libspdm_copy_mem(&(spdm_context->connection_info.version), + sizeof(spdm_context->connection_info.version), + &(common_version), sizeof(spdm_version_number_t)); + + if (version_number_entry_count != NULL && version_number_entry != NULL) { + if (*version_number_entry_count < spdm_response->version_number_entry_count) { + *version_number_entry_count = spdm_response->version_number_entry_count; + libspdm_reset_message_a(spdm_context); + status = LIBSPDM_STATUS_BUFFER_TOO_SMALL; + goto receive_done; + } else { + *version_number_entry_count = spdm_response->version_number_entry_count; + libspdm_copy_mem(version_number_entry, + spdm_response->version_number_entry_count * + sizeof(spdm_version_number_t), + spdm_response->version_number_entry, + spdm_response->version_number_entry_count * + sizeof(spdm_version_number_t)); + libspdm_version_number_sort (version_number_entry, *version_number_entry_count); + } + } + + /* -=[Update State Phase]=- */ + spdm_context->connection_info.connection_state = LIBSPDM_CONNECTION_STATE_AFTER_VERSION; + status = LIBSPDM_STATUS_SUCCESS; + + /* -=[Log Message Phase]=- */ + #if LIBSPDM_ENABLE_MSG_LOG + libspdm_append_msg_log(spdm_context, spdm_response, spdm_response_size); + #endif /* LIBSPDM_ENABLE_MSG_LOG */ + + /*Set the role of device*/ + spdm_context->local_context.is_requester = true; + +receive_done: + libspdm_release_receiver_buffer (spdm_context); + return status; +} + +libspdm_return_t libspdm_get_version(libspdm_context_t *spdm_context, + uint8_t *version_number_entry_count, + spdm_version_number_t *version_number_entry) +{ + size_t retry; + libspdm_return_t status; + + spdm_context->crypto_request = false; + retry = spdm_context->retry_times; + do { + status = libspdm_try_get_version(spdm_context, + version_number_entry_count, version_number_entry); + if (status != LIBSPDM_STATUS_BUSY_PEER) { + return status; + } + } while (retry-- != 0); + + return status; +} diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/libraries/libspdm/2.3.1/library/spdm_requester_lib/libspdm_req_handle_error_response.c nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/libraries/libspdm/2.3.1/library/spdm_requester_lib/libspdm_req_handle_error_response.c --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/libraries/libspdm/2.3.1/library/spdm_requester_lib/libspdm_req_handle_error_response.c 1970-01-01 00:00:00.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/libraries/libspdm/2.3.1/library/spdm_requester_lib/libspdm_req_handle_error_response.c 2024-03-05 22:14:17.000000000 +0000 @@ -0,0 +1,418 @@ +/** + * Copyright Notice: + * Copyright 2021-2022 DMTF. All rights reserved. + * License: BSD 3-Clause License. For full text see link: https://github.com/DMTF/libspdm/blob/main/LICENSE.md + **/ + +#include "internal/libspdm_requester_lib.h" +#include "hal/library/platform_lib.h" + +/** + * This function sends RESPOND_IF_READY and receives an expected SPDM response. + * + * @param spdm_context A pointer to the SPDM context. + * @param response_size The size of the response. + * On input, it means the size in bytes of response data buffer. + * On output, it means the size in bytes of copied response data buffer if RETURN_SUCCESS is returned. + * @param response The SPDM response message. + * @param expected_response_code Indicate the expected response code. + * @param expected_response_size Indicate the expected response size. + * + * @retval RETURN_SUCCESS The RESPOND_IF_READY is sent and an expected SPDM response is received. + * @retval RETURN_DEVICE_ERROR A device error occurs when communicates with the device. + **/ +static libspdm_return_t libspdm_requester_respond_if_ready(libspdm_context_t *spdm_context, + const uint32_t *session_id, + size_t *response_size, + void **response, + uint8_t expected_response_code, + size_t expected_response_size) +{ + libspdm_return_t status; + spdm_response_if_ready_request_t *spdm_request; + size_t spdm_request_size; + spdm_message_header_t *spdm_response; + uint8_t *message; + size_t message_size; + size_t transport_header_size; + + /* the response might be in response buffer in normal SPDM message + * or it is in scratch buffer in case of secure SPDM message + * the response buffer is in acquired state, so we release it*/ + libspdm_release_receiver_buffer (spdm_context); + + /* now we can get sender buffer */ + transport_header_size = spdm_context->transport_get_header_size(spdm_context); + status = libspdm_acquire_sender_buffer (spdm_context, &message_size, (void **)&message); + if (LIBSPDM_STATUS_IS_ERROR(status)) { + return status; + } + LIBSPDM_ASSERT (message_size >= transport_header_size); + spdm_request = (void *)(message + transport_header_size); + spdm_request_size = message_size - transport_header_size; + + spdm_context->crypto_request = true; + spdm_request->header.spdm_version = libspdm_get_connection_version (spdm_context); + spdm_request->header.request_response_code = SPDM_RESPOND_IF_READY; + spdm_request->header.param1 = spdm_context->error_data.request_code; + spdm_request->header.param2 = spdm_context->error_data.token; + spdm_request_size = sizeof(spdm_response_if_ready_request_t); + status = libspdm_send_spdm_request(spdm_context, session_id, + spdm_request_size, spdm_request); + if (LIBSPDM_STATUS_IS_ERROR(status)) { + libspdm_release_sender_buffer (spdm_context); + /* need acquire response buffer, so that the caller can release it */ + status = libspdm_acquire_receiver_buffer (spdm_context, response_size, response); + return status; + } + libspdm_release_sender_buffer (spdm_context); + spdm_request = (void *)spdm_context->last_spdm_request; + + /* receive + * do not release response buffer in case of error, because caller will release it*/ + + status = libspdm_acquire_receiver_buffer (spdm_context, response_size, response); + if (LIBSPDM_STATUS_IS_ERROR(status)) { + return status; + } + LIBSPDM_ASSERT (*response_size >= transport_header_size); + + libspdm_zero_mem(*response, *response_size); + status = libspdm_receive_spdm_response(spdm_context, session_id, + response_size, response); + if (LIBSPDM_STATUS_IS_ERROR(status)) { + return status; + } + spdm_response = (void *)(*response); + if (*response_size < sizeof(spdm_message_header_t)) { + return LIBSPDM_STATUS_INVALID_MSG_SIZE; + } + if (spdm_response->spdm_version != spdm_request->header.spdm_version) { + return LIBSPDM_STATUS_INVALID_MSG_FIELD; + } + if (spdm_response->request_response_code == SPDM_ERROR) { + status = libspdm_handle_simple_error_response(spdm_context, spdm_response->param1); + return status; + } + if (spdm_response->request_response_code != expected_response_code) { + return LIBSPDM_STATUS_INVALID_MSG_FIELD; + } + /* For response like SPDM_ALGORITHMS, we just can expect the max response size*/ + if (*response_size > expected_response_size) { + return LIBSPDM_STATUS_INVALID_MSG_SIZE; + } + return LIBSPDM_STATUS_SUCCESS; +} + +libspdm_return_t libspdm_handle_simple_error_response(void *context, uint8_t error_code) +{ + libspdm_context_t *spdm_context; + + spdm_context = context; + + if (error_code == SPDM_ERROR_CODE_RESPONSE_NOT_READY) { + return LIBSPDM_STATUS_NOT_READY_PEER; + } + + if (error_code == SPDM_ERROR_CODE_BUSY) { + return LIBSPDM_STATUS_BUSY_PEER; + } + + if (error_code == SPDM_ERROR_CODE_REQUEST_RESYNCH) { + spdm_context->connection_info.connection_state = + LIBSPDM_CONNECTION_STATE_NOT_STARTED; + return LIBSPDM_STATUS_RESYNCH_PEER; + } + + return LIBSPDM_STATUS_ERROR_PEER; +} + +/** + * This function handles RESPONSE_NOT_READY error code. + * + * @param spdm_context A pointer to the SPDM context. + * @param response_size The size of the response. + * On input, it means the size in bytes of response data buffer. + * On output, it means the size in bytes of copied response data buffer if RETURN_SUCCESS is returned. + * @param response The SPDM response message. + * @param original_request_code Indicate the orginal request code. + * @param expected_response_code Indicate the expected response code. + * @param expected_response_size Indicate the expected response size. + * + * @retval RETURN_SUCCESS The RESPOND_IF_READY is sent and an expected SPDM response is received. + * @retval RETURN_DEVICE_ERROR A device error occurs when communicates with the device. + **/ +static libspdm_return_t libspdm_handle_response_not_ready(libspdm_context_t *spdm_context, + const uint32_t *session_id, + size_t *response_size, + void **response, + uint8_t original_request_code, + uint8_t expected_response_code, + size_t expected_response_size) +{ + spdm_error_response_t *spdm_response; + spdm_error_data_response_not_ready_t *extend_error_data; + + if(*response_size != sizeof(spdm_error_response_t) + + sizeof(spdm_error_data_response_not_ready_t)) { + return LIBSPDM_STATUS_INVALID_MSG_SIZE; + } + + spdm_response = *response; + extend_error_data = + (spdm_error_data_response_not_ready_t *)(spdm_response + 1); + LIBSPDM_ASSERT(spdm_response->header.request_response_code == SPDM_ERROR); + LIBSPDM_ASSERT(spdm_response->header.param1 == + SPDM_ERROR_CODE_RESPONSE_NOT_READY); + if (extend_error_data->request_code != original_request_code) { + return LIBSPDM_STATUS_INVALID_MSG_FIELD; + } + + spdm_context->error_data.rd_exponent = extend_error_data->rd_exponent; + spdm_context->error_data.request_code = extend_error_data->request_code; + spdm_context->error_data.token = extend_error_data->token; + spdm_context->error_data.rd_tm = extend_error_data->rd_tm; + + libspdm_sleep_in_us((2 << extend_error_data->rd_exponent)); + return libspdm_requester_respond_if_ready(spdm_context, session_id, + response_size, response, + expected_response_code, + expected_response_size); +} + +#if (LIBSPDM_ENABLE_CAPABILITY_CHUNK_CAP) || (LIBSPDM_ENABLE_CHUNK_CAP) +libspdm_return_t libspdm_handle_error_large_response( + libspdm_context_t *spdm_context, + const uint32_t *session_id, + size_t *inout_response_size, + void *inout_response, + size_t response_capacity) +{ + libspdm_return_t status; + uint8_t chunk_handle; + spdm_error_response_t* error_response; + spdm_error_data_large_response_t* extend_error_data; + + spdm_chunk_get_request_t* spdm_request; + size_t spdm_request_size; + spdm_chunk_response_response_t* spdm_response; + uint8_t* message; + size_t message_size; + size_t transport_header_size; + + uint8_t* scratch_buffer; + size_t scratch_buffer_size; + uint16_t chunk_seq_no; + uint8_t* chunk_ptr; + uint8_t* large_response; + size_t large_response_capacity; + size_t large_response_size; + size_t large_response_size_so_far; + + /* Fail if requester or responder does not support chunk cap */ + if (!libspdm_is_capabilities_flag_supported( + spdm_context, true, + SPDM_GET_CAPABILITIES_REQUEST_FLAGS_CHUNK_CAP, + SPDM_GET_CAPABILITIES_RESPONSE_FLAGS_CHUNK_CAP)) { + return LIBSPDM_STATUS_ERROR_PEER; + } + + if (*inout_response_size < sizeof(spdm_error_response_t) + + sizeof(spdm_error_data_large_response_t)) { + return LIBSPDM_STATUS_INVALID_MSG_SIZE; + } + + error_response = inout_response; + extend_error_data = + (spdm_error_data_large_response_t*)(error_response + 1); + chunk_handle = extend_error_data->handle; + + /* now we can get sender buffer */ + transport_header_size = spdm_context->transport_get_header_size(spdm_context); + + libspdm_get_scratch_buffer(spdm_context, (void**)&scratch_buffer, &scratch_buffer_size); + LIBSPDM_ASSERT(scratch_buffer_size >= LIBSPDM_SCRATCH_BUFFER_SIZE); + + /* The first LIBSPDM_SENDER_RECEIVE_BUFFER_SIZE bytes of the scratch + * buffer may be used for other purposes. Use only after that section. */ + large_response = scratch_buffer + LIBSPDM_SCRATCH_BUFFER_LARGE_MESSAGE_OFFSET; + large_response_capacity = LIBSPDM_SCRATCH_BUFFER_LARGE_MESSAGE_CAPACITY; + + /* Temporary send/receive buffers for chunking are in the scratch space */ + message = scratch_buffer + LIBSPDM_SCRATCH_BUFFER_SENDER_RECEIVER_OFFSET; + message_size = LIBSPDM_SCRATCH_BUFFER_SENDER_RECEIVER_CAPACITY; + + libspdm_zero_mem(large_response, large_response_capacity); + large_response_size = 0; + large_response_size_so_far = 0; + chunk_seq_no = 0; + + do { + LIBSPDM_ASSERT(message_size >= transport_header_size); + spdm_request = (spdm_chunk_get_request_t*)(void*) (message + transport_header_size); + spdm_request_size = message_size - transport_header_size; + + spdm_request->header.spdm_version = libspdm_get_connection_version(spdm_context); + spdm_request->header.request_response_code = SPDM_CHUNK_GET; + spdm_request->header.param1 = 0; + spdm_request->header.param2 = chunk_handle; + spdm_request->chunk_seq_no = chunk_seq_no; + spdm_request_size = sizeof(spdm_chunk_get_request_t); + + LIBSPDM_DEBUG((LIBSPDM_DEBUG_ERROR, + "CHUNK_GET Handle %d SeqNo %d\n", chunk_handle, chunk_seq_no)); + + status = libspdm_send_spdm_request(spdm_context, session_id, + spdm_request_size, spdm_request); + spdm_request = NULL; + spdm_request_size = 0; + if (LIBSPDM_STATUS_IS_ERROR(status)) { + break; + } + + libspdm_zero_mem(message, message_size); + void* response = message; + size_t response_size = message_size; + + status = libspdm_receive_spdm_response( + spdm_context, session_id, + &response_size, &response); + + if (LIBSPDM_STATUS_IS_ERROR(status)) { + break; + } + spdm_response = (void*) (response); + if (spdm_response->header.spdm_version != libspdm_get_connection_version(spdm_context)) { + status = LIBSPDM_STATUS_INVALID_MSG_FIELD; + break; + } + if (spdm_response->header.request_response_code == SPDM_ERROR) { + status = libspdm_handle_simple_error_response(spdm_context, + spdm_response->header.param1); + break; + } + if (spdm_response->header.request_response_code != SPDM_CHUNK_RESPONSE) { + status = LIBSPDM_STATUS_INVALID_MSG_FIELD; + break; + } + if (chunk_seq_no == 0) { + + if (response_size + < (sizeof(spdm_chunk_response_response_t) + sizeof(uint32_t))) { + status = LIBSPDM_STATUS_INVALID_MSG_SIZE; + break; + } + if (response_size < SPDM_MIN_DATA_TRANSFER_SIZE_VERSION_12) { + status = LIBSPDM_STATUS_INVALID_MSG_SIZE; + break; + } + + if (spdm_response->chunk_size + < SPDM_MIN_DATA_TRANSFER_SIZE_VERSION_12 + - sizeof(spdm_chunk_response_response_t) + - sizeof(uint32_t)) { + status = LIBSPDM_STATUS_INVALID_MSG_SIZE; + break; + } + + large_response_size = *(uint32_t*) (spdm_response + 1); + chunk_ptr = (uint8_t*) (((uint32_t*) (spdm_response + 1)) + 1); + + if (spdm_response->chunk_size > large_response_size) { + status = LIBSPDM_STATUS_INVALID_MSG_FIELD; + break; + } + if (large_response_size > large_response_capacity) { + status = LIBSPDM_STATUS_BUFFER_TOO_SMALL; + break; + } + } + else { + if (response_size < sizeof(spdm_chunk_response_response_t)) { + status = LIBSPDM_STATUS_INVALID_MSG_SIZE; + break; + } + if (spdm_response->chunk_size + large_response_size_so_far > large_response_size) { + status = LIBSPDM_STATUS_INVALID_MSG_SIZE; + break; + } + + if (!(spdm_response->header.param1 & SPDM_CHUNK_GET_RESPONSE_ATTRIBUTE_LAST_CHUNK)) + { + if (response_size < SPDM_MIN_DATA_TRANSFER_SIZE_VERSION_12) { + status = LIBSPDM_STATUS_INVALID_MSG_SIZE; + break; + } + if (spdm_response->chunk_size + < SPDM_MIN_DATA_TRANSFER_SIZE_VERSION_12 + - sizeof(spdm_chunk_response_response_t)) { + status = LIBSPDM_STATUS_INVALID_MSG_SIZE; + break; + } + } + + chunk_ptr = (uint8_t*) (spdm_response + 1); + } + + if (spdm_response->chunk_seq_no != chunk_seq_no) { + status = LIBSPDM_STATUS_INVALID_MSG_FIELD; + break; + } + + libspdm_copy_mem(large_response + large_response_size_so_far, + large_response_size - large_response_size_so_far, + chunk_ptr, spdm_response->chunk_size); + + large_response_size_so_far += spdm_response->chunk_size; + + chunk_seq_no++; + + } while (LIBSPDM_STATUS_IS_SUCCESS(status) + && large_response_size_so_far < large_response_size + && !(spdm_response->header.param1 & SPDM_CHUNK_GET_RESPONSE_ATTRIBUTE_LAST_CHUNK)); + + + if (LIBSPDM_STATUS_IS_SUCCESS(status)) { + if (large_response_size_so_far != large_response_size) { + status = LIBSPDM_STATUS_INVALID_MSG_FIELD; + } + else if (large_response_size <= response_capacity) + { + libspdm_copy_mem(inout_response, response_capacity, + large_response, large_response_size); + *inout_response_size = large_response_size; + + LIBSPDM_INTERNAL_DUMP_HEX(large_response, large_response_size); + } + } + + return status; +} +#endif /* LIBSPDM_ENABLE_CAPABILITY_CHUNK_CAP */ + +libspdm_return_t libspdm_handle_error_response_main( + libspdm_context_t *spdm_context, const uint32_t *session_id, + size_t *response_size, void **response, + uint8_t original_request_code, uint8_t expected_response_code, + size_t expected_response_size) +{ + spdm_message_header_t *spdm_response; + + spdm_response = *response; + LIBSPDM_ASSERT(spdm_response->request_response_code == SPDM_ERROR); + + if ((spdm_response->param1 == SPDM_ERROR_CODE_DECRYPT_ERROR) && + (session_id != NULL)) { + libspdm_free_session_id(spdm_context, *session_id); + return LIBSPDM_STATUS_SESSION_MSG_ERROR; + } else if(spdm_response->param1 == SPDM_ERROR_CODE_RESPONSE_NOT_READY) { + return libspdm_handle_response_not_ready(spdm_context, session_id, + response_size, response, + original_request_code, + expected_response_code, + expected_response_size); + } else { + return libspdm_handle_simple_error_response(spdm_context, + spdm_response->param1); + } +} diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/libraries/libspdm/2.3.1/library/spdm_requester_lib/libspdm_req_key_exchange.c nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/libraries/libspdm/2.3.1/library/spdm_requester_lib/libspdm_req_key_exchange.c --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/libraries/libspdm/2.3.1/library/spdm_requester_lib/libspdm_req_key_exchange.c 1970-01-01 00:00:00.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/libraries/libspdm/2.3.1/library/spdm_requester_lib/libspdm_req_key_exchange.c 2024-03-05 22:14:17.000000000 +0000 @@ -0,0 +1,777 @@ +/** + * Copyright Notice: + * Copyright 2021-2022 DMTF. All rights reserved. + * License: BSD 3-Clause License. For full text see link: https://github.com/DMTF/libspdm/blob/main/LICENSE.md + **/ + +#include "internal/libspdm_requester_lib.h" + +#if LIBSPDM_ENABLE_CAPABILITY_KEY_EX_CAP + +#pragma pack(1) +typedef struct { + spdm_message_header_t header; + uint16_t req_session_id; + uint8_t session_policy; + uint8_t reserved; + uint8_t random_data[SPDM_RANDOM_DATA_SIZE]; + uint8_t exchange_data[LIBSPDM_MAX_DHE_KEY_SIZE]; + uint16_t opaque_length; + uint8_t opaque_data[SPDM_MAX_OPAQUE_DATA_SIZE]; +} libspdm_key_exchange_request_mine_t; + +typedef struct { + spdm_message_header_t header; + uint16_t rsp_session_id; + uint8_t mut_auth_requested; + uint8_t req_slot_id_param; + uint8_t random_data[SPDM_RANDOM_DATA_SIZE]; + uint8_t exchange_data[LIBSPDM_MAX_DHE_KEY_SIZE]; + uint8_t measurement_summary_hash[LIBSPDM_MAX_HASH_SIZE]; + uint16_t opaque_length; + uint8_t opaque_data[SPDM_MAX_OPAQUE_DATA_SIZE]; + uint8_t signature[LIBSPDM_MAX_ASYM_KEY_SIZE]; + uint8_t verify_data[LIBSPDM_MAX_HASH_SIZE]; +} libspdm_key_exchange_response_max_t; +#pragma pack() + +bool libspdm_verify_key_exchange_rsp_hmac(libspdm_context_t *spdm_context, + libspdm_session_info_t *session_info, + const void *hmac_data, + size_t hmac_data_size) +{ + size_t hash_size; + uint8_t calc_hmac_data[LIBSPDM_MAX_HASH_SIZE]; + bool result; +#if LIBSPDM_RECORD_TRANSCRIPT_DATA_SUPPORT + uint8_t *cert_chain_buffer; + size_t cert_chain_buffer_size; + uint8_t th_curr_data[LIBSPDM_MAX_MESSAGE_BUFFER_SIZE]; + size_t th_curr_data_size; + uint8_t hash_data[LIBSPDM_MAX_HASH_SIZE]; +#endif + + hash_size = libspdm_get_hash_size(spdm_context->connection_info.algorithm.base_hash_algo); + LIBSPDM_ASSERT(hash_size == hmac_data_size); + +#if LIBSPDM_RECORD_TRANSCRIPT_DATA_SUPPORT + result = libspdm_get_peer_cert_chain_buffer( + spdm_context, (const void **)&cert_chain_buffer, &cert_chain_buffer_size); + if (!result) { + return false; + } + + th_curr_data_size = sizeof(th_curr_data); + result = libspdm_calculate_th_for_exchange( + spdm_context, session_info, cert_chain_buffer, + cert_chain_buffer_size, &th_curr_data_size, th_curr_data); + if (!result) { + return false; + } + + result = libspdm_hash_all (spdm_context->connection_info.algorithm.base_hash_algo, + th_curr_data, th_curr_data_size, hash_data); + if (!result) { + return false; + } + + result = libspdm_hmac_all_with_response_finished_key( + session_info->secured_message_context, hash_data, + hash_size, calc_hmac_data); + if (!result) { + return false; + } +#else + result = libspdm_calculate_th_hmac_for_exchange_rsp( + spdm_context, session_info, true, &hash_size, calc_hmac_data); + if (!result) { + return false; + } +#endif + LIBSPDM_DEBUG((LIBSPDM_DEBUG_INFO, "th_curr hmac - ")); + LIBSPDM_INTERNAL_DUMP_DATA(calc_hmac_data, hash_size); + LIBSPDM_DEBUG((LIBSPDM_DEBUG_INFO, "\n")); + + if (libspdm_const_compare_mem(calc_hmac_data, hmac_data, hash_size) != 0) { + LIBSPDM_DEBUG((LIBSPDM_DEBUG_INFO, "!!! verify_key_exchange_hmac - FAIL !!!\n")); + return false; + } + LIBSPDM_DEBUG((LIBSPDM_DEBUG_INFO, "!!! verify_key_exchange_hmac - PASS !!!\n")); + + return true; +} + +bool libspdm_verify_key_exchange_rsp_signature( + libspdm_context_t *spdm_context, libspdm_session_info_t *session_info, + const void *sign_data, const size_t sign_data_size) +{ + bool result; + const uint8_t *cert_chain_data; + size_t cert_chain_data_size; + const uint8_t *cert_buffer; + size_t cert_buffer_size; + void *context; +#if LIBSPDM_RECORD_TRANSCRIPT_DATA_SUPPORT + uint8_t *cert_chain_buffer; + size_t cert_chain_buffer_size; + uint8_t th_curr_data[LIBSPDM_MAX_MESSAGE_BUFFER_SIZE]; + size_t th_curr_data_size; +#else + uint8_t slot_id; +#endif +#if !(LIBSPDM_RECORD_TRANSCRIPT_DATA_SUPPORT) || (LIBSPDM_DEBUG_PRINT_ENABLE) + size_t hash_size; + uint8_t hash_data[LIBSPDM_MAX_HASH_SIZE]; + + hash_size = libspdm_get_hash_size(spdm_context->connection_info.algorithm.base_hash_algo); +#endif + +#if LIBSPDM_RECORD_TRANSCRIPT_DATA_SUPPORT + result = libspdm_get_peer_cert_chain_buffer( + spdm_context, (const void **)&cert_chain_buffer, &cert_chain_buffer_size); + if (!result) { + return false; + } + + th_curr_data_size = sizeof(th_curr_data); + result = libspdm_calculate_th_for_exchange( + spdm_context, session_info, cert_chain_buffer, + cert_chain_buffer_size, &th_curr_data_size, th_curr_data); + if (!result) { + return false; + } + + /* Debug code only - required for debug print of th_curr hash below*/ + LIBSPDM_DEBUG_CODE( + if (!libspdm_hash_all( + spdm_context->connection_info.algorithm.base_hash_algo, + th_curr_data, th_curr_data_size, hash_data)) { + return false; + } + ); +#else + result = libspdm_calculate_th_hash_for_exchange( + spdm_context, session_info, &hash_size, hash_data); + if (!result) { + return false; + } +#endif + LIBSPDM_DEBUG((LIBSPDM_DEBUG_INFO, "th_curr hash - ")); + LIBSPDM_INTERNAL_DUMP_DATA(hash_data, hash_size); + LIBSPDM_DEBUG((LIBSPDM_DEBUG_INFO, "\n")); + + LIBSPDM_DEBUG((LIBSPDM_DEBUG_INFO, "signature - ")); + LIBSPDM_INTERNAL_DUMP_DATA(sign_data, sign_data_size); + LIBSPDM_DEBUG((LIBSPDM_DEBUG_INFO, "\n")); + + #if LIBSPDM_RECORD_TRANSCRIPT_DATA_SUPPORT + /* Get leaf cert from cert chain */ + result = libspdm_get_peer_cert_chain_data( + spdm_context, (const void **)&cert_chain_data, &cert_chain_data_size); + if (!result) { + return false; + } + result = libspdm_x509_get_cert_from_cert_chain(cert_chain_data, + cert_chain_data_size, -1, + &cert_buffer, &cert_buffer_size); + if (!result) { + return false; + } + + result = libspdm_asym_get_public_key_from_x509( + spdm_context->connection_info.algorithm.base_asym_algo, + cert_buffer, cert_buffer_size, &context); + if (!result) { + return false; + } + + result = libspdm_asym_verify( + spdm_context->connection_info.version, SPDM_KEY_EXCHANGE_RSP, + spdm_context->connection_info.algorithm.base_asym_algo, + spdm_context->connection_info.algorithm.base_hash_algo, context, + th_curr_data, th_curr_data_size, sign_data, sign_data_size); + libspdm_asym_free(spdm_context->connection_info.algorithm.base_asym_algo, context); +#else + slot_id = spdm_context->connection_info.peer_used_cert_chain_slot_id; + LIBSPDM_ASSERT(slot_id < SPDM_MAX_SLOT_COUNT); + if (spdm_context->connection_info.peer_used_cert_chain[slot_id].leaf_cert_public_key != NULL) { + result = libspdm_asym_verify_hash( + spdm_context->connection_info.version, SPDM_KEY_EXCHANGE_RSP, + spdm_context->connection_info.algorithm.base_asym_algo, + spdm_context->connection_info.algorithm.base_hash_algo, + spdm_context->connection_info.peer_used_cert_chain[slot_id].leaf_cert_public_key, + hash_data, hash_size, sign_data, sign_data_size); + } else { + /* Get leaf cert from cert chain*/ + result = libspdm_get_peer_cert_chain_data( + spdm_context, (const void **)&cert_chain_data, &cert_chain_data_size); + if (!result) { + return false; + } + result = libspdm_x509_get_cert_from_cert_chain(cert_chain_data, + cert_chain_data_size, -1, + &cert_buffer, &cert_buffer_size); + if (!result) { + return false; + } + + result = libspdm_asym_get_public_key_from_x509( + spdm_context->connection_info.algorithm.base_asym_algo, + cert_buffer, cert_buffer_size, &context); + if (!result) { + return false; + } + + result = libspdm_asym_verify_hash( + spdm_context->connection_info.version, SPDM_KEY_EXCHANGE_RSP, + spdm_context->connection_info.algorithm.base_asym_algo, + spdm_context->connection_info.algorithm.base_hash_algo, context, + hash_data, hash_size, sign_data, sign_data_size); + libspdm_asym_free(spdm_context->connection_info.algorithm.base_asym_algo, context); + } +#endif + if (!result) { + LIBSPDM_DEBUG((LIBSPDM_DEBUG_INFO, "!!! verify_key_exchange_signature - FAIL !!!\n")); + return false; + } + LIBSPDM_DEBUG((LIBSPDM_DEBUG_INFO, "!!! verify_key_exchange_signature - PASS !!!\n")); + + return true; +} + +/** + * This function sends KEY_EXCHANGE and receives KEY_EXCHANGE_RSP for SPDM key exchange. + * + * @param spdm_context A pointer to the SPDM context. + * @param measurement_hash_type Measurement_hash_type to the KEY_EXCHANGE request. + * @param slot_id slot_id to the KEY_EXCHANGE request. + * @param session_policy The policy for the session. + * @param session_id session_id from the KEY_EXCHANGE_RSP response. + * @param heartbeat_period Heartbeat_period from the KEY_EXCHANGE_RSP response. + * @param req_slot_id_param req_slot_id_param from the KEY_EXCHANGE_RSP response. + * @param measurement_hash Measurement_hash from the KEY_EXCHANGE_RSP response. + * @param requester_nonce_in If not NULL, a buffer that holds the requester nonce (32 bytes) + * @param requester_nonce If not NULL, a buffer to hold the requester nonce (32 bytes). + * @param responder_nonce If not NULL, a buffer to hold the responder nonce (32 bytes). + **/ +static libspdm_return_t libspdm_try_send_receive_key_exchange( + libspdm_context_t *spdm_context, uint8_t measurement_hash_type, + uint8_t slot_id, uint8_t session_policy, uint32_t *session_id, + uint8_t *heartbeat_period, + uint8_t *req_slot_id_param, void *measurement_hash, + const void *requester_random_in, + void *requester_random, + void *responder_random) +{ + bool result; + libspdm_return_t status; + libspdm_key_exchange_request_mine_t *spdm_request; + size_t spdm_request_size; + libspdm_key_exchange_response_max_t *spdm_response; + size_t spdm_response_size; + size_t dhe_key_size; + uint32_t measurement_summary_hash_size; + uint32_t signature_size; + uint32_t hmac_size; + uint8_t *ptr; + void *measurement_summary_hash; + uint16_t opaque_length; + uint8_t *signature; + uint8_t *verify_data; + void *dhe_context; + uint16_t req_session_id; + uint16_t rsp_session_id; + libspdm_session_info_t *session_info; + size_t opaque_key_exchange_req_size; + uint8_t th1_hash_data[LIBSPDM_MAX_HASH_SIZE]; + uint8_t *message; + size_t message_size; + size_t transport_header_size; + uint8_t mut_auth_requested; + + /* -=[Check Parameters Phase]=- */ + LIBSPDM_ASSERT((slot_id < SPDM_MAX_SLOT_COUNT) || (slot_id == 0xff)); + LIBSPDM_ASSERT((slot_id != 0xff) || + (spdm_context->local_context.peer_cert_chain_provision_size != 0)); + + /* -=[Verify State Phase]=- */ + if (!libspdm_is_capabilities_flag_supported( + spdm_context, true, + SPDM_GET_CAPABILITIES_REQUEST_FLAGS_KEY_EX_CAP, + SPDM_GET_CAPABILITIES_RESPONSE_FLAGS_KEY_EX_CAP)) { + return LIBSPDM_STATUS_UNSUPPORTED_CAP; + } + if (spdm_context->connection_info.connection_state < LIBSPDM_CONNECTION_STATE_NEGOTIATED) { + return LIBSPDM_STATUS_INVALID_STATE_LOCAL; + } + + req_session_id = libspdm_allocate_req_session_id(spdm_context); + if (req_session_id == ((INVALID_SESSION_ID & 0xFFFF0000) >> 16)) + { + return LIBSPDM_STATUS_SESSION_NUMBER_EXCEED; + } + + libspdm_reset_message_buffer_via_request_code(spdm_context, NULL, SPDM_KEY_EXCHANGE); + + /* -=[Construct Request Phase]=- */ + if (slot_id != 0xff) { + spdm_context->connection_info.peer_used_cert_chain_slot_id = slot_id; + } else { + spdm_context->connection_info.peer_used_cert_chain_slot_id = + spdm_context->local_context.provisioned_slot_id; + } + transport_header_size = spdm_context->transport_get_header_size(spdm_context); + status = libspdm_acquire_sender_buffer (spdm_context, &message_size, (void **)&message); + if (LIBSPDM_STATUS_IS_ERROR(status)) { + return status; + } + LIBSPDM_ASSERT (message_size >= transport_header_size); + spdm_request = (void *)(message + transport_header_size); + spdm_request_size = message_size - transport_header_size; + + spdm_request->header.spdm_version = libspdm_get_connection_version (spdm_context); + spdm_request->header.request_response_code = SPDM_KEY_EXCHANGE; + spdm_request->header.param1 = measurement_hash_type; + spdm_request->header.param2 = slot_id; + if (requester_random_in == NULL) { + if(!libspdm_get_random_number(SPDM_RANDOM_DATA_SIZE, spdm_request->random_data)) { + libspdm_release_sender_buffer (spdm_context); + return LIBSPDM_STATUS_LOW_ENTROPY; + } + } else { + libspdm_copy_mem(spdm_request->random_data, sizeof(spdm_request->random_data), + requester_random_in, SPDM_RANDOM_DATA_SIZE); + } + LIBSPDM_DEBUG((LIBSPDM_DEBUG_INFO, "ClientRandomData (0x%x) - ", + SPDM_RANDOM_DATA_SIZE)); + LIBSPDM_INTERNAL_DUMP_DATA(spdm_request->random_data, SPDM_RANDOM_DATA_SIZE); + LIBSPDM_DEBUG((LIBSPDM_DEBUG_INFO, "\n")); + if (requester_random != NULL) { + libspdm_copy_mem(requester_random, SPDM_RANDOM_DATA_SIZE, + spdm_request->random_data, SPDM_RANDOM_DATA_SIZE); + } + + spdm_request->req_session_id = req_session_id; + if (spdm_request->header.spdm_version >= SPDM_MESSAGE_VERSION_12) { + spdm_request->session_policy = session_policy; + } else { + spdm_request->session_policy = 0; + } + spdm_request->reserved = 0; + + ptr = spdm_request->exchange_data; + dhe_key_size = libspdm_get_dhe_pub_key_size( + spdm_context->connection_info.algorithm.dhe_named_group); + dhe_context = libspdm_secured_message_dhe_new( + spdm_context->connection_info.version, + spdm_context->connection_info.algorithm.dhe_named_group, true); + if (dhe_context == NULL) { + libspdm_release_sender_buffer (spdm_context); + return LIBSPDM_STATUS_CRYPTO_ERROR; + } + + result = libspdm_secured_message_dhe_generate_key( + spdm_context->connection_info.algorithm.dhe_named_group, + dhe_context, ptr, &dhe_key_size); + if (!result) { + libspdm_secured_message_dhe_free( + spdm_context->connection_info.algorithm.dhe_named_group, dhe_context); + libspdm_release_sender_buffer (spdm_context); + return LIBSPDM_STATUS_CRYPTO_ERROR; + } + LIBSPDM_DEBUG((LIBSPDM_DEBUG_INFO, "ClientKey (0x%x):\n", dhe_key_size)); + LIBSPDM_INTERNAL_DUMP_HEX(ptr, dhe_key_size); + ptr += dhe_key_size; + + opaque_key_exchange_req_size = + libspdm_get_opaque_data_supported_version_data_size(spdm_context); + *(uint16_t *)ptr = (uint16_t)opaque_key_exchange_req_size; + ptr += sizeof(uint16_t); + status = libspdm_build_opaque_data_supported_version_data( + spdm_context, &opaque_key_exchange_req_size, ptr); + LIBSPDM_ASSERT(status == LIBSPDM_STATUS_SUCCESS); + ptr += opaque_key_exchange_req_size; + + spdm_request_size = (size_t)ptr - (size_t)spdm_request; + + /* -=[Send Request Phase]=- */ + status = libspdm_send_spdm_request(spdm_context, NULL, spdm_request_size, spdm_request); + if (LIBSPDM_STATUS_IS_ERROR(status)) { + libspdm_secured_message_dhe_free( + spdm_context->connection_info.algorithm.dhe_named_group, dhe_context); + libspdm_release_sender_buffer (spdm_context); + return status; + } + libspdm_release_sender_buffer (spdm_context); + spdm_request = (void *)spdm_context->last_spdm_request; + + /* -=[Receive Response Phase]=- */ + status = libspdm_acquire_receiver_buffer (spdm_context, &message_size, (void **)&message); + if (LIBSPDM_STATUS_IS_ERROR(status)) { + libspdm_secured_message_dhe_free( + spdm_context->connection_info.algorithm.dhe_named_group, dhe_context); + return status; + } + LIBSPDM_ASSERT (message_size >= transport_header_size); + spdm_response = (void *)(message); + spdm_response_size = message_size; + + libspdm_zero_mem(spdm_response, spdm_response_size); + status = libspdm_receive_spdm_response( + spdm_context, NULL, &spdm_response_size, (void **)&spdm_response); + if (LIBSPDM_STATUS_IS_ERROR(status)) { + libspdm_secured_message_dhe_free( + spdm_context->connection_info.algorithm.dhe_named_group, dhe_context); + goto receive_done; + } + + /* -=[Validate Response Phase]=- */ + if (spdm_response_size < sizeof(spdm_message_header_t)) { + libspdm_secured_message_dhe_free( + spdm_context->connection_info.algorithm.dhe_named_group, dhe_context); + status = LIBSPDM_STATUS_INVALID_MSG_SIZE; + goto receive_done; + } + if (spdm_response->header.spdm_version != spdm_request->header.spdm_version) { + libspdm_secured_message_dhe_free( + spdm_context->connection_info.algorithm.dhe_named_group, dhe_context); + status = LIBSPDM_STATUS_INVALID_MSG_FIELD; + goto receive_done; + } + if (spdm_response->header.request_response_code == SPDM_ERROR) { + status = libspdm_handle_error_response_main( + spdm_context, NULL, &spdm_response_size, + (void **)&spdm_response, SPDM_KEY_EXCHANGE, + SPDM_KEY_EXCHANGE_RSP, sizeof(libspdm_key_exchange_response_max_t)); + if (LIBSPDM_STATUS_IS_ERROR(status)) { + libspdm_secured_message_dhe_free( + spdm_context->connection_info.algorithm.dhe_named_group, dhe_context); + goto receive_done; + } + } else if (spdm_response->header.request_response_code != SPDM_KEY_EXCHANGE_RSP) { + libspdm_secured_message_dhe_free( + spdm_context->connection_info.algorithm.dhe_named_group, dhe_context); + status = LIBSPDM_STATUS_INVALID_MSG_FIELD; + goto receive_done; + } + if (spdm_response_size < sizeof(spdm_key_exchange_response_t)) { + libspdm_secured_message_dhe_free( + spdm_context->connection_info.algorithm.dhe_named_group, dhe_context); + status = LIBSPDM_STATUS_INVALID_MSG_SIZE; + goto receive_done; + } + + if (!libspdm_is_capabilities_flag_supported( + spdm_context, true, + SPDM_GET_CAPABILITIES_REQUEST_FLAGS_HBEAT_CAP, + SPDM_GET_CAPABILITIES_RESPONSE_FLAGS_HBEAT_CAP)) { + if (spdm_response->header.param1 != 0) { + libspdm_secured_message_dhe_free( + spdm_context->connection_info.algorithm.dhe_named_group, dhe_context); + status = LIBSPDM_STATUS_INVALID_MSG_FIELD; + goto receive_done; + } + } + if (heartbeat_period != NULL) { + *heartbeat_period = spdm_response->header.param1; + } + + *req_slot_id_param = spdm_response->req_slot_id_param & 0xf; + mut_auth_requested = spdm_response->mut_auth_requested & 0x7; + + if (mut_auth_requested != 0) { + if (!libspdm_is_capabilities_flag_supported( + spdm_context, true, + SPDM_GET_CAPABILITIES_REQUEST_FLAGS_MUT_AUTH_CAP, + SPDM_GET_CAPABILITIES_RESPONSE_FLAGS_MUT_AUTH_CAP)) { + libspdm_secured_message_dhe_free( + spdm_context->connection_info.algorithm.dhe_named_group, dhe_context); + status = LIBSPDM_STATUS_INVALID_MSG_FIELD; + goto receive_done; + } + if ((mut_auth_requested != SPDM_KEY_EXCHANGE_RESPONSE_MUT_AUTH_REQUESTED) && + (mut_auth_requested != + SPDM_KEY_EXCHANGE_RESPONSE_MUT_AUTH_REQUESTED_WITH_ENCAP_REQUEST) && + (mut_auth_requested != + SPDM_KEY_EXCHANGE_RESPONSE_MUT_AUTH_REQUESTED_WITH_GET_DIGESTS)) { + libspdm_secured_message_dhe_free( + spdm_context->connection_info.algorithm.dhe_named_group, dhe_context); + status = LIBSPDM_STATUS_INVALID_MSG_FIELD; + goto receive_done; + } + if ((*req_slot_id_param != 0xF) && (*req_slot_id_param >= SPDM_MAX_SLOT_COUNT)) { + libspdm_secured_message_dhe_free( + spdm_context->connection_info.algorithm.dhe_named_group, dhe_context); + status = LIBSPDM_STATUS_INVALID_MSG_FIELD; + goto receive_done; + } + if ((mut_auth_requested != SPDM_KEY_EXCHANGE_RESPONSE_MUT_AUTH_REQUESTED) && + (*req_slot_id_param != 0)) { + libspdm_secured_message_dhe_free( + spdm_context->connection_info.algorithm.dhe_named_group, dhe_context); + status = LIBSPDM_STATUS_INVALID_MSG_FIELD; + goto receive_done; + } + } else if (*req_slot_id_param != 0) { + libspdm_secured_message_dhe_free( + spdm_context->connection_info.algorithm.dhe_named_group, dhe_context); + status = LIBSPDM_STATUS_INVALID_MSG_FIELD; + goto receive_done; + } + + signature_size = libspdm_get_asym_signature_size( + spdm_context->connection_info.algorithm.base_asym_algo); + measurement_summary_hash_size = libspdm_get_measurement_summary_hash_size( + spdm_context, true, measurement_hash_type); + hmac_size = libspdm_get_hash_size(spdm_context->connection_info.algorithm.base_hash_algo); + + if (libspdm_is_capabilities_flag_supported( + spdm_context, true, + SPDM_GET_CAPABILITIES_REQUEST_FLAGS_HANDSHAKE_IN_THE_CLEAR_CAP, + SPDM_GET_CAPABILITIES_RESPONSE_FLAGS_HANDSHAKE_IN_THE_CLEAR_CAP)) { + hmac_size = 0; + } + + if (spdm_response_size < + sizeof(spdm_key_exchange_response_t) + dhe_key_size + + measurement_summary_hash_size + sizeof(uint16_t) + signature_size + hmac_size) { + libspdm_secured_message_dhe_free( + spdm_context->connection_info.algorithm.dhe_named_group, dhe_context); + status = LIBSPDM_STATUS_INVALID_MSG_SIZE; + goto receive_done; + } + + LIBSPDM_DEBUG((LIBSPDM_DEBUG_INFO, "ServerRandomData (0x%x) - ", SPDM_RANDOM_DATA_SIZE)); + LIBSPDM_INTERNAL_DUMP_DATA(spdm_response->random_data, SPDM_RANDOM_DATA_SIZE); + LIBSPDM_DEBUG((LIBSPDM_DEBUG_INFO, "\n")); + if (responder_random != NULL) { + libspdm_copy_mem(responder_random, SPDM_RANDOM_DATA_SIZE, + spdm_response->random_data, SPDM_RANDOM_DATA_SIZE); + } + + LIBSPDM_DEBUG((LIBSPDM_DEBUG_INFO, "ServerKey (0x%x):\n", dhe_key_size)); + LIBSPDM_INTERNAL_DUMP_HEX(spdm_response->exchange_data, dhe_key_size); + + ptr = spdm_response->exchange_data; + ptr += dhe_key_size; + + measurement_summary_hash = ptr; + LIBSPDM_DEBUG((LIBSPDM_DEBUG_INFO, "measurement_summary_hash (0x%x) - ", + measurement_summary_hash_size)); + LIBSPDM_INTERNAL_DUMP_DATA(measurement_summary_hash, measurement_summary_hash_size); + LIBSPDM_DEBUG((LIBSPDM_DEBUG_INFO, "\n")); + + ptr += measurement_summary_hash_size; + + opaque_length = *(uint16_t *)ptr; + if (opaque_length > SPDM_MAX_OPAQUE_DATA_SIZE) { + libspdm_secured_message_dhe_free( + spdm_context->connection_info.algorithm.dhe_named_group, dhe_context); + status = LIBSPDM_STATUS_INVALID_MSG_FIELD; + goto receive_done; + } + ptr += sizeof(uint16_t); + if (spdm_response_size < + sizeof(spdm_key_exchange_response_t) + dhe_key_size + + measurement_summary_hash_size + sizeof(uint16_t) + + opaque_length + signature_size + hmac_size) { + libspdm_secured_message_dhe_free( + spdm_context->connection_info.algorithm.dhe_named_group, dhe_context); + status = LIBSPDM_STATUS_INVALID_MSG_SIZE; + goto receive_done; + } + if (opaque_length != 0) { + status = libspdm_process_opaque_data_version_selection_data( + spdm_context, opaque_length, ptr); + if (LIBSPDM_STATUS_IS_ERROR(status)) { + libspdm_secured_message_dhe_free( + spdm_context->connection_info.algorithm.dhe_named_group, dhe_context); + status = LIBSPDM_STATUS_INVALID_MSG_FIELD; + goto receive_done; + } + } + + ptr += opaque_length; + + spdm_response_size = sizeof(spdm_key_exchange_response_t) + + dhe_key_size + measurement_summary_hash_size + + sizeof(uint16_t) + opaque_length + signature_size + hmac_size; + + rsp_session_id = spdm_response->rsp_session_id; + *session_id = libspdm_generate_session_id(req_session_id, rsp_session_id); + session_info = libspdm_assign_session_id(spdm_context, *session_id, false); + + if (session_info == NULL) { + libspdm_secured_message_dhe_free( + spdm_context->connection_info.algorithm.dhe_named_group, dhe_context); + status = LIBSPDM_STATUS_SESSION_NUMBER_EXCEED; + goto receive_done; + } + + /* -=[Process Response Phase]=- */ + status = libspdm_append_message_k(spdm_context, session_info, true, spdm_request, + spdm_request_size); + if (LIBSPDM_STATUS_IS_ERROR(status)) { + libspdm_free_session_id(spdm_context, *session_id); + libspdm_secured_message_dhe_free( + spdm_context->connection_info.algorithm.dhe_named_group, dhe_context); + status = LIBSPDM_STATUS_BUFFER_FULL; + goto receive_done; + } + + status = libspdm_append_message_k(spdm_context, session_info, true, spdm_response, + spdm_response_size - signature_size - hmac_size); + if (LIBSPDM_STATUS_IS_ERROR(status)) { + libspdm_free_session_id(spdm_context, *session_id); + libspdm_secured_message_dhe_free( + spdm_context->connection_info.algorithm.dhe_named_group, dhe_context); + status = LIBSPDM_STATUS_BUFFER_FULL; + goto receive_done; + } + + signature = ptr; + LIBSPDM_DEBUG((LIBSPDM_DEBUG_INFO, "signature (0x%x):\n", signature_size)); + LIBSPDM_INTERNAL_DUMP_HEX(signature, signature_size); + ptr += signature_size; + result = libspdm_verify_key_exchange_rsp_signature( + spdm_context, session_info, signature, signature_size); + if (!result) { + libspdm_free_session_id(spdm_context, *session_id); + libspdm_secured_message_dhe_free( + spdm_context->connection_info.algorithm.dhe_named_group, dhe_context); + status = LIBSPDM_STATUS_VERIF_FAIL; + goto receive_done; + } + + status = libspdm_append_message_k(spdm_context, session_info, true, signature, signature_size); + if (LIBSPDM_STATUS_IS_ERROR(status)) { + libspdm_free_session_id(spdm_context, *session_id); + libspdm_secured_message_dhe_free( + spdm_context->connection_info.algorithm.dhe_named_group, dhe_context); + status = LIBSPDM_STATUS_BUFFER_FULL; + goto receive_done; + } + + result = libspdm_secured_message_dhe_compute_key( + spdm_context->connection_info.algorithm.dhe_named_group, + dhe_context, spdm_response->exchange_data, dhe_key_size, + session_info->secured_message_context); + libspdm_secured_message_dhe_free( + spdm_context->connection_info.algorithm.dhe_named_group, dhe_context); + if (!result) { + libspdm_free_session_id(spdm_context, *session_id); + status = LIBSPDM_STATUS_CRYPTO_ERROR; + goto receive_done; + } + + LIBSPDM_DEBUG((LIBSPDM_DEBUG_INFO, "libspdm_generate_session_handshake_key[%x]\n", + *session_id)); + result = libspdm_calculate_th1_hash(spdm_context, session_info, true, th1_hash_data); + if (!result) { + libspdm_free_session_id(spdm_context, *session_id); + return LIBSPDM_STATUS_CRYPTO_ERROR; + } + result = libspdm_generate_session_handshake_key( + session_info->secured_message_context, th1_hash_data); + if (!result) { + libspdm_free_session_id(spdm_context, *session_id); + status = LIBSPDM_STATUS_CRYPTO_ERROR; + goto receive_done; + } + + if (!libspdm_is_capabilities_flag_supported( + spdm_context, true, + SPDM_GET_CAPABILITIES_REQUEST_FLAGS_HANDSHAKE_IN_THE_CLEAR_CAP, + SPDM_GET_CAPABILITIES_RESPONSE_FLAGS_HANDSHAKE_IN_THE_CLEAR_CAP)) { + verify_data = ptr; + LIBSPDM_DEBUG((LIBSPDM_DEBUG_INFO, "verify_data (0x%x):\n", hmac_size)); + LIBSPDM_INTERNAL_DUMP_HEX(verify_data, hmac_size); + result = libspdm_verify_key_exchange_rsp_hmac( + spdm_context, session_info, verify_data, hmac_size); + if (!result) { + libspdm_free_session_id(spdm_context, *session_id); + status = LIBSPDM_STATUS_VERIF_FAIL; + goto receive_done; + } + ptr += hmac_size; + + status = libspdm_append_message_k(spdm_context, session_info, true, verify_data, hmac_size); + if (LIBSPDM_STATUS_IS_ERROR(status)) { + libspdm_free_session_id(spdm_context, *session_id); + status = LIBSPDM_STATUS_BUFFER_FULL; + goto receive_done; + } + } + + if (measurement_hash != NULL) { + libspdm_copy_mem(measurement_hash, measurement_summary_hash_size, + measurement_summary_hash, measurement_summary_hash_size); + } + session_info->heartbeat_period = spdm_response->header.param1; + session_info->mut_auth_requested = mut_auth_requested; + session_info->session_policy = session_policy; + + /* -=[Update State Phase]=- */ + libspdm_secured_message_set_session_state( + session_info->secured_message_context, LIBSPDM_SESSION_STATE_HANDSHAKING); + + status = LIBSPDM_STATUS_SUCCESS; + +receive_done: + libspdm_release_receiver_buffer (spdm_context); + return status; +} + +libspdm_return_t libspdm_send_receive_key_exchange( + libspdm_context_t *spdm_context, uint8_t measurement_hash_type, + uint8_t slot_id, uint8_t session_policy, uint32_t *session_id, + uint8_t *heartbeat_period, + uint8_t *req_slot_id_param, void *measurement_hash) +{ + size_t retry; + libspdm_return_t status; + + spdm_context->crypto_request = true; + retry = spdm_context->retry_times; + do { + status = libspdm_try_send_receive_key_exchange( + spdm_context, measurement_hash_type, slot_id, session_policy, + session_id, heartbeat_period, req_slot_id_param, + measurement_hash, NULL, NULL, NULL); + if (status != LIBSPDM_STATUS_BUSY_PEER) { + return status; + } + } while (retry-- != 0); + + return status; +} + +libspdm_return_t libspdm_send_receive_key_exchange_ex( + libspdm_context_t *spdm_context, uint8_t measurement_hash_type, + uint8_t slot_id, uint8_t session_policy, uint32_t *session_id, + uint8_t *heartbeat_period, + uint8_t *req_slot_id_param, void *measurement_hash, + const void *requester_random_in, + void *requester_random, + void *responder_random) +{ + size_t retry; + libspdm_return_t status; + + spdm_context->crypto_request = true; + retry = spdm_context->retry_times; + do { + status = libspdm_try_send_receive_key_exchange( + spdm_context, measurement_hash_type, slot_id, session_policy, + session_id, heartbeat_period, req_slot_id_param, + measurement_hash, requester_random_in, + requester_random, responder_random); + if (LIBSPDM_STATUS_BUSY_PEER != status) { + return status; + } + } while (retry-- != 0); + + return status; +} + +#endif /* LIBSPDM_ENABLE_CAPABILITY_KEY_EX_CAP */ diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/libraries/libspdm/2.3.1/library/spdm_requester_lib/libspdm_req_key_update.c nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/libraries/libspdm/2.3.1/library/spdm_requester_lib/libspdm_req_key_update.c --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/libraries/libspdm/2.3.1/library/spdm_requester_lib/libspdm_req_key_update.c 1970-01-01 00:00:00.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/libraries/libspdm/2.3.1/library/spdm_requester_lib/libspdm_req_key_update.c 2024-03-05 22:14:17.000000000 +0000 @@ -0,0 +1,326 @@ +/** + * Copyright Notice: + * Copyright 2021-2022 DMTF. All rights reserved. + * License: BSD 3-Clause License. For full text see link: https://github.com/DMTF/libspdm/blob/main/LICENSE.md + **/ + +#include "internal/libspdm_requester_lib.h" + +#pragma pack(1) +typedef struct { + spdm_message_header_t header; + uint8_t dummy_data[sizeof(spdm_error_data_response_not_ready_t)]; +} libspdm_key_update_response_mine_t; +#pragma pack() + +/** + * This function sends KEY_UPDATE + * to update keys for an SPDM Session. + * + * After keys are updated, this function also uses VERIFY_NEW_KEY to verify the key. + * + * @param spdm_context A pointer to the SPDM context. + * @param session_id The session ID of the session. + * @param single_direction true means the operation is UPDATE_KEY. + * false means the operation is UPDATE_ALL_KEYS. + * @param key_updated true means the operation is to verify key(s). + * false means the operation is to update and verify key(s). + * + * @retval RETURN_SUCCESS The keys of the session are updated. + * @retval RETURN_DEVICE_ERROR A device error occurs when communicates with the device. + * @retval RETURN_SECURITY_VIOLATION Any verification fails. + **/ +static libspdm_return_t libspdm_try_key_update(void *context, uint32_t session_id, + bool single_direction, bool *key_updated) +{ + libspdm_return_t status; + bool result; + spdm_key_update_request_t *spdm_request; + size_t spdm_request_size; + libspdm_key_update_response_mine_t *spdm_response; + size_t spdm_response_size; + libspdm_context_t *spdm_context; + libspdm_session_info_t *session_info; + libspdm_session_state_t session_state; + uint8_t *message; + size_t message_size; + size_t transport_header_size; + + spdm_context = context; + if (!libspdm_is_capabilities_flag_supported( + spdm_context, true, + SPDM_GET_CAPABILITIES_REQUEST_FLAGS_KEY_UPD_CAP, + SPDM_GET_CAPABILITIES_RESPONSE_FLAGS_KEY_UPD_CAP)) { + return LIBSPDM_STATUS_UNSUPPORTED_CAP; + } + + if (spdm_context->connection_info.connection_state < + LIBSPDM_CONNECTION_STATE_NEGOTIATED) { + return LIBSPDM_STATUS_INVALID_STATE_LOCAL; + } + session_info = + libspdm_get_session_info_via_session_id(spdm_context, session_id); + if (session_info == NULL) { + LIBSPDM_ASSERT(false); + return LIBSPDM_STATUS_INVALID_STATE_LOCAL; + } + session_state = libspdm_secured_message_get_session_state( + session_info->secured_message_context); + if (session_state != LIBSPDM_SESSION_STATE_ESTABLISHED) { + return LIBSPDM_STATUS_INVALID_STATE_LOCAL; + } + + libspdm_reset_message_buffer_via_request_code(spdm_context, session_info, SPDM_KEY_UPDATE); + + if(!(*key_updated)) { + + /* Update key*/ + + transport_header_size = spdm_context->transport_get_header_size(spdm_context); + status = libspdm_acquire_sender_buffer (spdm_context, &message_size, (void **)&message); + if (LIBSPDM_STATUS_IS_ERROR(status)) { + return status; + } + LIBSPDM_ASSERT (message_size >= transport_header_size); + spdm_request = (void *)(message + transport_header_size); + spdm_request_size = message_size - transport_header_size; + + spdm_request->header.spdm_version = libspdm_get_connection_version (spdm_context); + spdm_request->header.request_response_code = SPDM_KEY_UPDATE; + if (single_direction) { + spdm_request->header.param1 = SPDM_KEY_UPDATE_OPERATIONS_TABLE_UPDATE_KEY; + } else { + spdm_request->header.param1 = SPDM_KEY_UPDATE_OPERATIONS_TABLE_UPDATE_ALL_KEYS; + } + spdm_request->header.param2 = 0; + + if(!libspdm_get_random_number(sizeof(spdm_request->header.param2), + &spdm_request->header.param2)) { + libspdm_release_sender_buffer (spdm_context); + return LIBSPDM_STATUS_LOW_ENTROPY; + } + + spdm_request_size = sizeof(spdm_key_update_request_t); + + /* If updating both, create new responder key*/ + if (!single_direction) { + LIBSPDM_DEBUG((LIBSPDM_DEBUG_INFO, + "libspdm_create_update_session_data_key[%x] Responder\n", + session_id)); + result = libspdm_create_update_session_data_key( + session_info->secured_message_context, + LIBSPDM_KEY_UPDATE_ACTION_RESPONDER); + if (!result) { + libspdm_release_sender_buffer (spdm_context); + return LIBSPDM_STATUS_CRYPTO_ERROR; + } + } + + status = libspdm_send_spdm_request(spdm_context, &session_id, + spdm_request_size, spdm_request); + if (LIBSPDM_STATUS_IS_ERROR(status)) { + libspdm_release_sender_buffer (spdm_context); + return status; + } + + libspdm_release_sender_buffer (spdm_context); + spdm_request = (void *)spdm_context->last_spdm_request; + + /* receive */ + + status = libspdm_acquire_receiver_buffer (spdm_context, &message_size, (void **)&message); + if (LIBSPDM_STATUS_IS_ERROR(status)) { + return status; + } + LIBSPDM_ASSERT (message_size >= transport_header_size); + spdm_response = (void *)(message); + spdm_response_size = message_size; + + libspdm_zero_mem(spdm_response, spdm_response_size); + status = libspdm_receive_spdm_response( + spdm_context, &session_id, &spdm_response_size, (void **)&spdm_response); + + if (!LIBSPDM_STATUS_IS_ERROR(status)) { + if (spdm_response_size < sizeof(spdm_message_header_t)) { + status = LIBSPDM_STATUS_INVALID_MSG_SIZE; + } else if (spdm_response->header.spdm_version != spdm_request->header.spdm_version) { + status = LIBSPDM_STATUS_INVALID_MSG_FIELD; + } else if (spdm_response->header.request_response_code == SPDM_ERROR) { + status = libspdm_handle_error_response_main( + spdm_context, &session_id, + &spdm_response_size, (void **)&spdm_response, + SPDM_KEY_UPDATE, SPDM_KEY_UPDATE_ACK, + sizeof(libspdm_key_update_response_mine_t)); + } else if ((spdm_response->header.request_response_code != + SPDM_KEY_UPDATE_ACK) || + (spdm_response->header.param1 != spdm_request->header.param1) || + (spdm_response->header.param2 != spdm_request->header.param2)) { + status = LIBSPDM_STATUS_INVALID_MSG_FIELD; + } + } + + if (LIBSPDM_STATUS_IS_ERROR(status)) { + if (!single_direction) { + LIBSPDM_DEBUG((LIBSPDM_DEBUG_INFO, + "libspdm_activate_update_session_data_key[%x] Responder old\n", + session_id)); + result = libspdm_activate_update_session_data_key( + session_info->secured_message_context, + LIBSPDM_KEY_UPDATE_ACTION_RESPONDER, false); + if (!result) { + libspdm_release_receiver_buffer (spdm_context); + return LIBSPDM_STATUS_CRYPTO_ERROR; + } + } + libspdm_release_receiver_buffer (spdm_context); + return status; + } + + if (!single_direction) { + LIBSPDM_DEBUG((LIBSPDM_DEBUG_INFO, + "libspdm_activate_update_session_data_key[%x] Responder new\n", + session_id, LIBSPDM_KEY_UPDATE_ACTION_RESPONDER)); + result = libspdm_activate_update_session_data_key( + session_info->secured_message_context, + LIBSPDM_KEY_UPDATE_ACTION_RESPONDER, true); + if (!result) { + libspdm_release_receiver_buffer (spdm_context); + return LIBSPDM_STATUS_CRYPTO_ERROR; + } + } + + LIBSPDM_DEBUG((LIBSPDM_DEBUG_INFO, + "libspdm_create_update_session_data_key[%x] Requester\n", + session_id)); + result = libspdm_create_update_session_data_key( + session_info->secured_message_context, + LIBSPDM_KEY_UPDATE_ACTION_REQUESTER); + if (!result) { + libspdm_release_receiver_buffer (spdm_context); + return LIBSPDM_STATUS_CRYPTO_ERROR; + } + LIBSPDM_DEBUG((LIBSPDM_DEBUG_INFO, + "libspdm_activate_update_session_data_key[%x] Requester new\n", + session_id)); + result = libspdm_activate_update_session_data_key( + session_info->secured_message_context, + LIBSPDM_KEY_UPDATE_ACTION_REQUESTER, true); + if (!result) { + libspdm_release_receiver_buffer (spdm_context); + return LIBSPDM_STATUS_CRYPTO_ERROR; + } + + libspdm_release_receiver_buffer (spdm_context); + } + + *key_updated = true; + + + /* Verify key*/ + + transport_header_size = spdm_context->transport_get_header_size(spdm_context); + status = libspdm_acquire_sender_buffer (spdm_context, &message_size, (void **)&message); + if (LIBSPDM_STATUS_IS_ERROR(status)) { + return status; + } + LIBSPDM_ASSERT (message_size >= transport_header_size); + spdm_request = (void *)(message + transport_header_size); + spdm_request_size = message_size - transport_header_size; + + spdm_request->header.spdm_version = libspdm_get_connection_version (spdm_context); + spdm_request->header.request_response_code = SPDM_KEY_UPDATE; + spdm_request->header.param1 = + SPDM_KEY_UPDATE_OPERATIONS_TABLE_VERIFY_NEW_KEY; + spdm_request->header.param2 = 1; + if(!libspdm_get_random_number(sizeof(spdm_request->header.param2), + &spdm_request->header.param2)) { + libspdm_release_sender_buffer (spdm_context); + return LIBSPDM_STATUS_LOW_ENTROPY; + } + spdm_request_size = sizeof(spdm_key_update_request_t); + + status = libspdm_send_spdm_request(spdm_context, &session_id, + spdm_request_size, spdm_request); + if (LIBSPDM_STATUS_IS_ERROR(status)) { + libspdm_release_sender_buffer (spdm_context); + return status; + } + libspdm_release_sender_buffer (spdm_context); + spdm_request = (void *)spdm_context->last_spdm_request; + + /* receive */ + + status = libspdm_acquire_receiver_buffer (spdm_context, &message_size, (void **)&message); + if (LIBSPDM_STATUS_IS_ERROR(status)) { + return status; + } + LIBSPDM_ASSERT (message_size >= transport_header_size); + spdm_response = (void *)(message); + spdm_response_size = message_size; + + libspdm_zero_mem(spdm_response, spdm_response_size); + status = libspdm_receive_spdm_response( + spdm_context, &session_id, &spdm_response_size, (void **)&spdm_response); + if (LIBSPDM_STATUS_IS_ERROR(status)) { + libspdm_release_receiver_buffer (spdm_context); + return status; + } + if (spdm_response_size < sizeof(spdm_message_header_t)) { + LIBSPDM_DEBUG((LIBSPDM_DEBUG_INFO, "SpdmVerifyKey[%x] Failed\n", session_id)); + libspdm_release_receiver_buffer (spdm_context); + return LIBSPDM_STATUS_INVALID_MSG_SIZE; + } + + if (spdm_response->header.spdm_version != spdm_request->header.spdm_version) { + libspdm_release_receiver_buffer (spdm_context); + return LIBSPDM_STATUS_INVALID_MSG_FIELD; + } + if (spdm_response->header.request_response_code == SPDM_ERROR) { + status = libspdm_handle_error_response_main( + spdm_context, &session_id, + &spdm_response_size, (void **)&spdm_response, + SPDM_KEY_UPDATE, SPDM_KEY_UPDATE_ACK, + sizeof(libspdm_key_update_response_mine_t)); + if (LIBSPDM_STATUS_IS_ERROR(status)) { + LIBSPDM_DEBUG((LIBSPDM_DEBUG_INFO, "SpdmVerifyKey[%x] Failed\n", session_id)); + libspdm_release_receiver_buffer (spdm_context); + return status; + } + } + + if ((spdm_response->header.request_response_code != + SPDM_KEY_UPDATE_ACK) || + (spdm_response->header.param1 != spdm_request->header.param1) || + (spdm_response->header.param2 != spdm_request->header.param2)) { + LIBSPDM_DEBUG((LIBSPDM_DEBUG_INFO, "SpdmVerifyKey[%x] Failed\n", session_id)); + libspdm_release_receiver_buffer (spdm_context); + return LIBSPDM_STATUS_INVALID_MSG_FIELD; + } + LIBSPDM_DEBUG((LIBSPDM_DEBUG_INFO, "SpdmVerifyKey[%x] Success\n", session_id)); + + libspdm_release_receiver_buffer (spdm_context); + return LIBSPDM_STATUS_SUCCESS; +} + +libspdm_return_t libspdm_key_update(void *context, uint32_t session_id, + bool single_direction) +{ + libspdm_context_t *spdm_context; + size_t retry; + libspdm_return_t status; + bool key_updated; + + spdm_context = context; + key_updated = false; + spdm_context->crypto_request = true; + retry = spdm_context->retry_times; + do { + status = libspdm_try_key_update(context, session_id, + single_direction, &key_updated); + if (LIBSPDM_STATUS_BUSY_PEER != status) { + return status; + } + } while (retry-- != 0); + + return status; +} diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/libraries/libspdm/2.3.1/library/spdm_requester_lib/libspdm_req_negotiate_algorithms.c nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/libraries/libspdm/2.3.1/library/spdm_requester_lib/libspdm_req_negotiate_algorithms.c --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/libraries/libspdm/2.3.1/library/spdm_requester_lib/libspdm_req_negotiate_algorithms.c 1970-01-01 00:00:00.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/libraries/libspdm/2.3.1/library/spdm_requester_lib/libspdm_req_negotiate_algorithms.c 2024-03-05 22:14:17.000000000 +0000 @@ -0,0 +1,531 @@ +/** + * Copyright Notice: + * Copyright 2021-2022 DMTF. All rights reserved. + * License: BSD 3-Clause License. For full text see link: https://github.com/DMTF/libspdm/blob/main/LICENSE.md + **/ + +#include "internal/libspdm_requester_lib.h" + +#pragma pack(1) +typedef struct { + spdm_message_header_t header; + uint16_t length; + uint8_t measurement_specification; + uint8_t other_params_support; + uint32_t base_asym_algo; + uint32_t base_hash_algo; + uint8_t reserved2[12]; + uint8_t ext_asym_count; + uint8_t ext_hash_count; + uint16_t reserved3; + spdm_negotiate_algorithms_common_struct_table_t struct_table[4]; +} libspdm_negotiate_algorithms_request_mine_t; + +typedef struct { + spdm_message_header_t header; + uint16_t length; + uint8_t measurement_specification_sel; + uint8_t other_params_selection; + uint32_t measurement_hash_algo; + uint32_t base_asym_sel; + uint32_t base_hash_sel; + uint8_t reserved2[12]; + uint8_t ext_asym_sel_count; + uint8_t ext_hash_sel_count; + uint16_t reserved3; + uint32_t ext_asym_sel; + uint32_t ext_hash_sel; + spdm_negotiate_algorithms_common_struct_table_t struct_table[4]; +} libspdm_algorithms_response_max_t; +#pragma pack() + +/** + * This function sends NEGOTIATE_ALGORITHMS and receives ALGORITHMS. + * + * @param spdm_context A pointer to the SPDM context. + * + * @retval LIBSPDM_STATUS_SUCCESS + * NEGOTIATE_ALGORITHMS was sent and ALGORITHMS was received. + * @retval LIBSPDM_STATUS_INVALID_STATE_LOCAL + * Cannot send NEGOTIATE_ALGORITHMS due to Requester's state. + * @retval LIBSPDM_STATUS_INVALID_MSG_SIZE + * The size of the ALGORITHMS response is invalid. + * @retval LIBSPDM_STATUS_INVALID_MSG_FIELD + * The ALGORITHMS response contains one or more invalid fields. + * @retval LIBSPDM_STATUS_ERROR_PEER + * The Responder returned an unexpected error. + * @retval LIBSPDM_STATUS_BUSY_PEER + * The Responder continually returned Busy error messages. + * @retval LIBSPDM_STATUS_RESYNCH_PEER + * The Responder returned a RequestResynch error message. + * @retval LIBSPDM_STATUS_BUFFER_FULL + * The buffer used to store transcripts is exhausted. + * @retval LIBSPDM_STATUS_NEGOTIATION_FAIL + * The Requester and Responder could not agree on mutual algorithms. + * Note: This return value may be removed in the future. + **/ +static libspdm_return_t libspdm_try_negotiate_algorithms(libspdm_context_t *spdm_context) +{ + libspdm_return_t status; + libspdm_negotiate_algorithms_request_mine_t *spdm_request; + size_t spdm_request_size; + libspdm_algorithms_response_max_t *spdm_response; + size_t spdm_response_size; + uint32_t algo_size; + size_t index; + spdm_negotiate_algorithms_common_struct_table_t *struct_table; + uint8_t fixed_alg_size; + uint8_t ext_alg_count; + uint8_t *message; + size_t message_size; + size_t transport_header_size; + uint8_t alg_type_pre; + + /* -=[Verify State Phase]=- */ + if (spdm_context->connection_info.connection_state != + LIBSPDM_CONNECTION_STATE_AFTER_CAPABILITIES) { + return LIBSPDM_STATUS_INVALID_STATE_LOCAL; + } + + libspdm_reset_message_buffer_via_request_code(spdm_context, NULL, SPDM_NEGOTIATE_ALGORITHMS); + + /* -=[Construct Request Phase]=- */ + transport_header_size = spdm_context->transport_get_header_size(spdm_context); + status = libspdm_acquire_sender_buffer (spdm_context, &message_size, (void **)&message); + if (LIBSPDM_STATUS_IS_ERROR(status)) { + return status; + } + LIBSPDM_ASSERT (message_size >= transport_header_size); + spdm_request = (void *)(message + transport_header_size); + spdm_request_size = message_size - transport_header_size; + + libspdm_zero_mem(spdm_request, sizeof(libspdm_negotiate_algorithms_request_mine_t)); + spdm_request->header.spdm_version = libspdm_get_connection_version (spdm_context); + if (spdm_request->header.spdm_version >= SPDM_MESSAGE_VERSION_11) { + spdm_request->length = sizeof(libspdm_negotiate_algorithms_request_mine_t); + /* Number of Algorithms Structure Tables*/ + spdm_request->header.param1 = 4; + } else { + spdm_request->length = sizeof(libspdm_negotiate_algorithms_request_mine_t) - + sizeof(spdm_request->struct_table); + spdm_request->header.param1 = 0; + } + spdm_request->header.request_response_code = SPDM_NEGOTIATE_ALGORITHMS; + spdm_request->header.param2 = 0; + spdm_request->measurement_specification = + spdm_context->local_context.algorithm.measurement_spec; + if (spdm_request->header.spdm_version >= SPDM_MESSAGE_VERSION_12) { + spdm_request->other_params_support = + spdm_context->local_context.algorithm.other_params_support; + } + spdm_request->base_asym_algo = spdm_context->local_context.algorithm.base_asym_algo; + spdm_request->base_hash_algo = spdm_context->local_context.algorithm.base_hash_algo; + spdm_request->ext_asym_count = 0; + spdm_request->ext_hash_count = 0; + spdm_request->struct_table[0].alg_type = SPDM_NEGOTIATE_ALGORITHMS_STRUCT_TABLE_ALG_TYPE_DHE; + spdm_request->struct_table[0].alg_count = 0x20; + spdm_request->struct_table[0].alg_supported = + spdm_context->local_context.algorithm.dhe_named_group; + spdm_request->struct_table[1].alg_type = SPDM_NEGOTIATE_ALGORITHMS_STRUCT_TABLE_ALG_TYPE_AEAD; + spdm_request->struct_table[1].alg_count = 0x20; + spdm_request->struct_table[1].alg_supported = + spdm_context->local_context.algorithm.aead_cipher_suite; + spdm_request->struct_table[2].alg_type = + SPDM_NEGOTIATE_ALGORITHMS_STRUCT_TABLE_ALG_TYPE_REQ_BASE_ASYM_ALG; + spdm_request->struct_table[2].alg_count = 0x20; + spdm_request->struct_table[2].alg_supported = + spdm_context->local_context.algorithm.req_base_asym_alg; + spdm_request->struct_table[3].alg_type = + SPDM_NEGOTIATE_ALGORITHMS_STRUCT_TABLE_ALG_TYPE_KEY_SCHEDULE; + spdm_request->struct_table[3].alg_count = 0x20; + spdm_request->struct_table[3].alg_supported = + spdm_context->local_context.algorithm.key_schedule; + spdm_request_size = spdm_request->length; + + /* -=[Send Request Phase]=- */ + status = libspdm_send_spdm_request(spdm_context, NULL, spdm_request_size, spdm_request); + if (LIBSPDM_STATUS_IS_ERROR(status)) { + libspdm_release_sender_buffer (spdm_context); + return status; + } + libspdm_release_sender_buffer (spdm_context); + spdm_request = (void *)spdm_context->last_spdm_request; + + /* -=[Receive Response Phase]=- */ + status = libspdm_acquire_receiver_buffer (spdm_context, &message_size, (void **)&message); + if (LIBSPDM_STATUS_IS_ERROR(status)) { + return status; + } + LIBSPDM_ASSERT (message_size >= transport_header_size); + spdm_response = (void *)(message); + spdm_response_size = message_size; + + libspdm_zero_mem(spdm_response, spdm_response_size); + status = libspdm_receive_spdm_response(spdm_context, NULL, &spdm_response_size, + (void **)&spdm_response); + if (LIBSPDM_STATUS_IS_ERROR(status)) { + goto receive_done; + } + + /* -=[Validate Response Phase]=- */ + if (spdm_response_size < sizeof(spdm_message_header_t)) { + status = LIBSPDM_STATUS_INVALID_MSG_SIZE; + goto receive_done; + } + if (spdm_response->header.spdm_version != spdm_request->header.spdm_version) { + status = LIBSPDM_STATUS_INVALID_MSG_FIELD; + goto receive_done; + } + if (spdm_response->header.request_response_code == SPDM_ERROR) { + status = libspdm_handle_simple_error_response(spdm_context, spdm_response->header.param1); + if (LIBSPDM_STATUS_IS_ERROR(status)) { + goto receive_done; + } + } else if (spdm_response->header.request_response_code != SPDM_ALGORITHMS) { + status = LIBSPDM_STATUS_INVALID_MSG_FIELD; + goto receive_done; + } + if (spdm_response_size < sizeof(spdm_algorithms_response_t)) { + status = LIBSPDM_STATUS_INVALID_MSG_SIZE; + goto receive_done; + } + if (!libspdm_onehot0(spdm_response->measurement_specification_sel)) { + status = LIBSPDM_STATUS_INVALID_MSG_FIELD; + goto receive_done; + } + if (!libspdm_onehot0(spdm_response->measurement_hash_algo)) { + status = LIBSPDM_STATUS_INVALID_MSG_FIELD; + goto receive_done; + } + if (!libspdm_onehot0(spdm_response->base_asym_sel)) { + status = LIBSPDM_STATUS_INVALID_MSG_FIELD; + goto receive_done; + } + if (!libspdm_onehot0(spdm_response->base_hash_sel)) { + status = LIBSPDM_STATUS_INVALID_MSG_FIELD; + goto receive_done; + } + if (spdm_response->ext_asym_sel_count > 0) { + status = LIBSPDM_STATUS_INVALID_MSG_FIELD; + goto receive_done; + } + if (spdm_response->ext_hash_sel_count > 0) { + status = LIBSPDM_STATUS_INVALID_MSG_FIELD; + goto receive_done; + } + if (spdm_response_size < + sizeof(spdm_algorithms_response_t) + + sizeof(uint32_t) * spdm_response->ext_asym_sel_count + + sizeof(uint32_t) * spdm_response->ext_hash_sel_count + + sizeof(spdm_negotiate_algorithms_common_struct_table_t) * spdm_response->header.param1) { + status = LIBSPDM_STATUS_INVALID_MSG_SIZE; + goto receive_done; + } + struct_table = + (void *)((size_t)spdm_response + + sizeof(spdm_algorithms_response_t) + + sizeof(uint32_t) * spdm_response->ext_asym_sel_count + + sizeof(uint32_t) * spdm_response->ext_hash_sel_count); + if (spdm_response->header.spdm_version >= SPDM_MESSAGE_VERSION_11) { + alg_type_pre = struct_table->alg_type; + /* header.param1 is implictly checked through spdm_response_size. */ + for (index = 0; index < spdm_response->header.param1; index++) { + if ((size_t)spdm_response + spdm_response_size < (size_t)struct_table) { + status = LIBSPDM_STATUS_INVALID_MSG_SIZE; + goto receive_done; + } + if ((size_t)spdm_response + spdm_response_size - (size_t)struct_table < + sizeof(spdm_negotiate_algorithms_common_struct_table_t)) { + status = LIBSPDM_STATUS_INVALID_MSG_SIZE; + goto receive_done; + } + if ((struct_table->alg_type < SPDM_NEGOTIATE_ALGORITHMS_STRUCT_TABLE_ALG_TYPE_DHE) || + (struct_table->alg_type > + SPDM_NEGOTIATE_ALGORITHMS_STRUCT_TABLE_ALG_TYPE_KEY_SCHEDULE)) { + status = LIBSPDM_STATUS_INVALID_MSG_FIELD; + goto receive_done; + } + /* AlgType shall monotonically increase for subsequent entries. */ + if ((index != 0) && (struct_table->alg_type <= alg_type_pre)) { + status = LIBSPDM_STATUS_INVALID_MSG_FIELD; + goto receive_done; + } + alg_type_pre = struct_table->alg_type; + fixed_alg_size = (struct_table->alg_count >> 4) & 0xF; + ext_alg_count = struct_table->alg_count & 0xF; + if (fixed_alg_size != 2) { + status = LIBSPDM_STATUS_INVALID_MSG_FIELD; + goto receive_done; + } + if (ext_alg_count > 0) { + status = LIBSPDM_STATUS_INVALID_MSG_FIELD; + goto receive_done; + } + if (!libspdm_onehot0(struct_table->alg_supported)) { + status = LIBSPDM_STATUS_INVALID_MSG_FIELD; + goto receive_done; + } + if ((size_t)spdm_response + spdm_response_size - + (size_t)struct_table - sizeof(spdm_negotiate_algorithms_common_struct_table_t) < + sizeof(uint32_t) * ext_alg_count) { + status = LIBSPDM_STATUS_INVALID_MSG_SIZE; + goto receive_done; + } + struct_table = + (void *)((size_t)struct_table + + sizeof(spdm_negotiate_algorithms_common_struct_table_t) + + sizeof(uint32_t) * ext_alg_count); + } + } + + spdm_response_size = (size_t)struct_table - (size_t)spdm_response; + if (spdm_response_size != spdm_response->length) { + status = LIBSPDM_STATUS_INVALID_MSG_SIZE; + goto receive_done; + } + + /* -=[Process Response Phase]=- */ + status = libspdm_append_message_a(spdm_context, spdm_request, spdm_request_size); + if (LIBSPDM_STATUS_IS_ERROR(status)) { + status = LIBSPDM_STATUS_BUFFER_FULL; + goto receive_done; + } + + status = libspdm_append_message_a(spdm_context, spdm_response, spdm_response_size); + if (LIBSPDM_STATUS_IS_ERROR(status)) { + status = LIBSPDM_STATUS_BUFFER_FULL; + goto receive_done; + } + + spdm_context->connection_info.algorithm.measurement_spec = + spdm_response->measurement_specification_sel; + if (spdm_response->header.spdm_version >= SPDM_MESSAGE_VERSION_12) { + spdm_context->connection_info.algorithm.other_params_support = + spdm_response->other_params_selection; + } + spdm_context->connection_info.algorithm.measurement_hash_algo = + spdm_response->measurement_hash_algo; + spdm_context->connection_info.algorithm.base_asym_algo = spdm_response->base_asym_sel; + spdm_context->connection_info.algorithm.base_hash_algo = spdm_response->base_hash_sel; + + if (libspdm_is_capabilities_flag_supported( + spdm_context, true, 0, + SPDM_GET_CAPABILITIES_RESPONSE_FLAGS_MEAS_CAP) && + (spdm_request->measurement_specification != 0)) { + if (spdm_context->connection_info.algorithm.measurement_spec != + SPDM_MEASUREMENT_BLOCK_HEADER_SPECIFICATION_DMTF) { + status = LIBSPDM_STATUS_INVALID_MSG_FIELD; + goto receive_done; + } + algo_size = libspdm_get_measurement_hash_size( + spdm_context->connection_info.algorithm.measurement_hash_algo); + if (algo_size == 0) { + status = LIBSPDM_STATUS_NEGOTIATION_FAIL; + goto receive_done; + } + } + + if (libspdm_is_capabilities_flag_supported( + spdm_context, true, 0, + SPDM_GET_CAPABILITIES_RESPONSE_FLAGS_CERT_CAP) || + libspdm_is_capabilities_flag_supported( + spdm_context, true, 0, + SPDM_GET_CAPABILITIES_RESPONSE_FLAGS_CHAL_CAP) || + libspdm_is_capabilities_flag_supported( + spdm_context, true, 0, + SPDM_GET_CAPABILITIES_RESPONSE_FLAGS_MEAS_CAP_SIG) || + libspdm_is_capabilities_flag_supported( + spdm_context, true, + SPDM_GET_CAPABILITIES_REQUEST_FLAGS_KEY_EX_CAP, + SPDM_GET_CAPABILITIES_RESPONSE_FLAGS_KEY_EX_CAP) || + libspdm_is_capabilities_flag_supported( + spdm_context, true, + SPDM_GET_CAPABILITIES_REQUEST_FLAGS_PSK_CAP, + SPDM_GET_CAPABILITIES_RESPONSE_FLAGS_PSK_CAP)) { + algo_size = libspdm_get_hash_size(spdm_context->connection_info.algorithm.base_hash_algo); + if (algo_size == 0) { + status = LIBSPDM_STATUS_NEGOTIATION_FAIL; + goto receive_done; + } + if ((spdm_context->connection_info.algorithm.base_hash_algo & + spdm_context->local_context.algorithm.base_hash_algo) == 0) { + status = LIBSPDM_STATUS_NEGOTIATION_FAIL; + goto receive_done; + } + } + + if (libspdm_is_capabilities_flag_supported( + spdm_context, true, 0, + SPDM_GET_CAPABILITIES_RESPONSE_FLAGS_CERT_CAP) || + libspdm_is_capabilities_flag_supported( + spdm_context, true, 0, + SPDM_GET_CAPABILITIES_RESPONSE_FLAGS_CHAL_CAP) || + libspdm_is_capabilities_flag_supported( + spdm_context, true, 0, + SPDM_GET_CAPABILITIES_RESPONSE_FLAGS_MEAS_CAP_SIG) || + libspdm_is_capabilities_flag_supported( + spdm_context, true, + SPDM_GET_CAPABILITIES_REQUEST_FLAGS_KEY_EX_CAP, + SPDM_GET_CAPABILITIES_RESPONSE_FLAGS_KEY_EX_CAP)) { + algo_size = libspdm_get_asym_signature_size( + spdm_context->connection_info.algorithm.base_asym_algo); + if (algo_size == 0) { + status = LIBSPDM_STATUS_NEGOTIATION_FAIL; + goto receive_done; + } + if ((spdm_context->connection_info.algorithm.base_asym_algo & + spdm_context->local_context.algorithm.base_asym_algo) == 0) { + status = LIBSPDM_STATUS_NEGOTIATION_FAIL; + goto receive_done; + } + } + + if (spdm_response->header.spdm_version >= SPDM_MESSAGE_VERSION_11) { + struct_table = + (void *)((size_t)spdm_response + + sizeof(spdm_algorithms_response_t) + + sizeof(uint32_t) * spdm_response->ext_asym_sel_count + + sizeof(uint32_t) * spdm_response->ext_hash_sel_count); + for (index = 0; index < spdm_response->header.param1; index++) { + switch (struct_table->alg_type) { + case SPDM_NEGOTIATE_ALGORITHMS_STRUCT_TABLE_ALG_TYPE_DHE: + spdm_context->connection_info.algorithm.dhe_named_group = + struct_table->alg_supported; + break; + case SPDM_NEGOTIATE_ALGORITHMS_STRUCT_TABLE_ALG_TYPE_AEAD: + spdm_context->connection_info.algorithm.aead_cipher_suite = + struct_table->alg_supported; + break; + case SPDM_NEGOTIATE_ALGORITHMS_STRUCT_TABLE_ALG_TYPE_REQ_BASE_ASYM_ALG: + spdm_context->connection_info.algorithm.req_base_asym_alg = + struct_table->alg_supported; + break; + case SPDM_NEGOTIATE_ALGORITHMS_STRUCT_TABLE_ALG_TYPE_KEY_SCHEDULE: + spdm_context->connection_info.algorithm.key_schedule = + struct_table->alg_supported; + break; + } + ext_alg_count = struct_table->alg_count & 0xF; + struct_table = + (void *)((size_t)struct_table + + sizeof(spdm_negotiate_algorithms_common_struct_table_t) + + sizeof(uint32_t) * ext_alg_count); + } + + if (libspdm_is_capabilities_flag_supported( + spdm_context, true, + SPDM_GET_CAPABILITIES_REQUEST_FLAGS_KEY_EX_CAP, + SPDM_GET_CAPABILITIES_RESPONSE_FLAGS_KEY_EX_CAP)) { + algo_size = libspdm_get_dhe_pub_key_size( + spdm_context->connection_info.algorithm.dhe_named_group); + if (algo_size == 0) { + status = LIBSPDM_STATUS_NEGOTIATION_FAIL; + goto receive_done; + } + if ((spdm_context->connection_info.algorithm.dhe_named_group & + spdm_context->local_context.algorithm.dhe_named_group) == 0) { + status = LIBSPDM_STATUS_NEGOTIATION_FAIL; + goto receive_done; + } + } + if (libspdm_is_capabilities_flag_supported( + spdm_context, true, + SPDM_GET_CAPABILITIES_REQUEST_FLAGS_ENCRYPT_CAP, + SPDM_GET_CAPABILITIES_RESPONSE_FLAGS_ENCRYPT_CAP) || + libspdm_is_capabilities_flag_supported( + spdm_context, true, + SPDM_GET_CAPABILITIES_REQUEST_FLAGS_MAC_CAP, + SPDM_GET_CAPABILITIES_RESPONSE_FLAGS_MAC_CAP)) { + algo_size = libspdm_get_aead_key_size( + spdm_context->connection_info.algorithm.aead_cipher_suite); + if (algo_size == 0) { + status = LIBSPDM_STATUS_NEGOTIATION_FAIL; + goto receive_done; + } + if ((spdm_context->connection_info.algorithm.aead_cipher_suite & + spdm_context->local_context.algorithm.aead_cipher_suite) == 0) { + status = LIBSPDM_STATUS_NEGOTIATION_FAIL; + goto receive_done; + } + } + if (libspdm_is_capabilities_flag_supported( + spdm_context, true, + SPDM_GET_CAPABILITIES_REQUEST_FLAGS_MUT_AUTH_CAP, + SPDM_GET_CAPABILITIES_RESPONSE_FLAGS_MUT_AUTH_CAP)) { + algo_size = libspdm_get_req_asym_signature_size( + spdm_context->connection_info.algorithm.req_base_asym_alg); + if (algo_size == 0) { + status = LIBSPDM_STATUS_NEGOTIATION_FAIL; + goto receive_done; + } + if ((spdm_context->connection_info.algorithm.req_base_asym_alg & + spdm_context->local_context.algorithm.req_base_asym_alg) == 0) { + status = LIBSPDM_STATUS_NEGOTIATION_FAIL; + goto receive_done; + } + } + if (libspdm_is_capabilities_flag_supported( + spdm_context, true, + SPDM_GET_CAPABILITIES_REQUEST_FLAGS_KEY_EX_CAP, + SPDM_GET_CAPABILITIES_RESPONSE_FLAGS_KEY_EX_CAP) || + libspdm_is_capabilities_flag_supported( + spdm_context, true, + SPDM_GET_CAPABILITIES_REQUEST_FLAGS_PSK_CAP, + SPDM_GET_CAPABILITIES_RESPONSE_FLAGS_PSK_CAP)) { + if (spdm_context->connection_info.algorithm.key_schedule != + SPDM_ALGORITHMS_KEY_SCHEDULE_HMAC_HASH) { + status = LIBSPDM_STATUS_NEGOTIATION_FAIL; + goto receive_done; + } + if ((spdm_context->connection_info.algorithm.key_schedule & + spdm_context->local_context.algorithm.key_schedule) == 0) { + status = LIBSPDM_STATUS_NEGOTIATION_FAIL; + goto receive_done; + } + if (spdm_response->header.spdm_version >= SPDM_MESSAGE_VERSION_12) { + if ((spdm_context->connection_info.algorithm.other_params_support & + SPDM_ALGORITHMS_OPAQUE_DATA_FORMAT_MASK) != + SPDM_ALGORITHMS_OPAQUE_DATA_FORMAT_1) { + status = LIBSPDM_STATUS_NEGOTIATION_FAIL; + goto receive_done; + } + } + } + } else { + spdm_context->connection_info.algorithm.dhe_named_group = 0; + spdm_context->connection_info.algorithm.aead_cipher_suite = 0; + spdm_context->connection_info.algorithm.req_base_asym_alg = 0; + spdm_context->connection_info.algorithm.key_schedule = 0; + } + + /* -=[Update State Phase]=- */ + spdm_context->connection_info.connection_state = LIBSPDM_CONNECTION_STATE_NEGOTIATED; + + /* -=[Log Message Phase]=- */ + #if LIBSPDM_ENABLE_MSG_LOG + libspdm_append_msg_log(spdm_context, spdm_response, spdm_response_size); + #endif /* LIBSPDM_ENABLE_MSG_LOG */ + + status = LIBSPDM_STATUS_SUCCESS; + +receive_done: + libspdm_release_receiver_buffer (spdm_context); + return status; +} + +libspdm_return_t libspdm_negotiate_algorithms(libspdm_context_t *spdm_context) +{ + size_t retry; + libspdm_return_t status; + + spdm_context->crypto_request = false; + retry = spdm_context->retry_times; + do { + status = libspdm_try_negotiate_algorithms(spdm_context); + if (status != LIBSPDM_STATUS_BUSY_PEER) { + return status; + } + } while (retry-- != 0); + + return status; +} diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/libraries/libspdm/2.3.1/library/spdm_requester_lib/libspdm_req_send_receive.c nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/libraries/libspdm/2.3.1/library/spdm_requester_lib/libspdm_req_send_receive.c --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/libraries/libspdm/2.3.1/library/spdm_requester_lib/libspdm_req_send_receive.c 1970-01-01 00:00:00.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/libraries/libspdm/2.3.1/library/spdm_requester_lib/libspdm_req_send_receive.c 2024-03-05 22:14:17.000000000 +0000 @@ -0,0 +1,685 @@ +/** + * Copyright Notice: + * Copyright 2021-2022 DMTF. All rights reserved. + * License: BSD 3-Clause License. For full text see link: https://github.com/DMTF/libspdm/blob/main/LICENSE.md + **/ + +#include "internal/libspdm_requester_lib.h" + +libspdm_return_t libspdm_send_request(void *context, const uint32_t *session_id, + bool is_app_message, + size_t request_size, void *request) +{ + libspdm_context_t *spdm_context; + libspdm_return_t status; + uint8_t *message; + size_t message_size; + uint64_t timeout; + uint8_t *scratch_buffer; + size_t scratch_buffer_size; + size_t transport_header_size; + uint8_t *sender_buffer; + size_t sender_buffer_size; + + spdm_context = context; + + LIBSPDM_DEBUG((LIBSPDM_DEBUG_INFO, "libspdm_send_spdm_request[%x] (0x%x): \n", + (session_id != NULL) ? *session_id : 0x0, request_size)); + LIBSPDM_INTERNAL_DUMP_HEX(request, request_size); + + transport_header_size = spdm_context->transport_get_header_size(spdm_context); + libspdm_get_scratch_buffer(spdm_context, (void**) &scratch_buffer, &scratch_buffer_size); + libspdm_get_sender_buffer(spdm_context, (void**) &sender_buffer, &sender_buffer_size); + + /* This is a problem because original code assumes request is in the sender buffer, + * when it can really be using the scratch space for chunking. + * Did not want to modify ally request handlers to pass this information, + * so just making the determination here by examining scratch/sender buffers. + * This may be something that should be refactored in the future. */ + #if (LIBSPDM_ENABLE_CAPABILITY_CHUNK_CAP) || (LIBSPDM_ENABLE_CHUNK_CAP) + if ((uint8_t*) request >= sender_buffer && + (uint8_t*)request < sender_buffer + sender_buffer_size) { + message = sender_buffer; + message_size = sender_buffer_size; + } + else { + if ((uint8_t*)request >= scratch_buffer + LIBSPDM_SCRATCH_BUFFER_SENDER_RECEIVER_OFFSET + && (uint8_t*)request < scratch_buffer + LIBSPDM_SCRATCH_BUFFER_SENDER_RECEIVER_OFFSET + + LIBSPDM_SCRATCH_BUFFER_SENDER_RECEIVER_CAPACITY) { + message = scratch_buffer + LIBSPDM_SCRATCH_BUFFER_SENDER_RECEIVER_OFFSET; + message_size = LIBSPDM_SCRATCH_BUFFER_SENDER_RECEIVER_CAPACITY; + } else if ((uint8_t*)request >= + scratch_buffer + LIBSPDM_SCRATCH_BUFFER_LARGE_SENDER_RECEIVER_OFFSET + && (uint8_t*)request < + scratch_buffer + LIBSPDM_SCRATCH_BUFFER_LARGE_SENDER_RECEIVER_OFFSET + + LIBSPDM_SCRATCH_BUFFER_LARGE_SENDER_RECEIVER_CAPACITY) { + message = scratch_buffer + LIBSPDM_SCRATCH_BUFFER_LARGE_SENDER_RECEIVER_OFFSET; + message_size = LIBSPDM_SCRATCH_BUFFER_LARGE_SENDER_RECEIVER_CAPACITY; + } + } + #else /* LIBSPDM_ENABLE_CAPABILITY_CHUNK_CAP */ + message = sender_buffer; + message_size = sender_buffer_size; + #endif /* LIBSPDM_ENABLE_CAPABILITY_CHUNK_CAP */ + + if (session_id != NULL) { + /* For secure message, message is in sender buffer, we need copy it to scratch buffer. + * transport_message is always in sender buffer. */ + + libspdm_copy_mem (scratch_buffer + transport_header_size, + scratch_buffer_size - transport_header_size, + request, request_size); + request = scratch_buffer + transport_header_size; + } + + /* backup it to last_spdm_request, because the caller wants to compare it with response */ + if (((const spdm_message_header_t *)request)->request_response_code != SPDM_RESPOND_IF_READY + && ((const spdm_message_header_t *)request)->request_response_code != SPDM_CHUNK_GET + && ((const spdm_message_header_t*) request)->request_response_code != SPDM_CHUNK_SEND) { + libspdm_copy_mem (spdm_context->last_spdm_request, + sizeof(spdm_context->last_spdm_request), + request, + request_size + ); + spdm_context->last_spdm_request_size = request_size; + } + + status = spdm_context->transport_encode_message( + spdm_context, session_id, is_app_message, true, request_size, + request, &message_size, (void **)&message); + if (LIBSPDM_STATUS_IS_ERROR(status)) { + LIBSPDM_DEBUG((LIBSPDM_DEBUG_INFO, "transport_encode_message status - %p\n", + status)); + return status; + } + + timeout = spdm_context->local_context.capability.rtt; + + status = spdm_context->send_message(spdm_context, message_size, message, + timeout); + if (LIBSPDM_STATUS_IS_ERROR(status)) { + LIBSPDM_DEBUG((LIBSPDM_DEBUG_INFO, "libspdm_send_spdm_request[%x] status - %p\n", + (session_id != NULL) ? *session_id : 0x0, status)); + } + + return status; +} + +libspdm_return_t libspdm_receive_response(void *context, const uint32_t *session_id, + bool is_app_message, + size_t *response_size, + void **response) +{ + libspdm_context_t *spdm_context; + void *temp_session_context; + libspdm_return_t status; + uint8_t *message; + size_t message_size; + uint32_t *message_session_id; + bool is_message_app_message; + uint64_t timeout; + size_t transport_header_size; + uint8_t *scratch_buffer; + size_t scratch_buffer_size; + void *backup_response; + size_t backup_response_size; + bool reset_key_update; + bool result; + + spdm_context = context; + + if (spdm_context->crypto_request) { + timeout = spdm_context->local_context.capability.rtt + + ((uint64_t)2 << spdm_context->connection_info.capability.ct_exponent); + } else { + timeout = spdm_context->local_context.capability.rtt + + spdm_context->local_context.capability.st1; + } + + message = *response; + message_size = *response_size; + status = spdm_context->receive_message(spdm_context, &message_size, + (void **)&message, timeout); + if (LIBSPDM_STATUS_IS_ERROR(status)) { + LIBSPDM_DEBUG((LIBSPDM_DEBUG_INFO, + "libspdm_receive_spdm_response[%x] status - %p\n", + (session_id != NULL) ? *session_id : 0x0, status)); + return status; + } + + message_session_id = NULL; + is_message_app_message = false; + + /* always use scratch buffer to response. + * if it is secured message, this scratch buffer will be used. + * if it is normal message, the response ptr will point to receiver buffer. */ + transport_header_size = spdm_context->transport_get_header_size(spdm_context); + libspdm_get_scratch_buffer (spdm_context, (void **)&scratch_buffer, &scratch_buffer_size); + #if LIBSPDM_ENABLE_CAPABILITY_CHUNK_CAP || LIBSPDM_ENABLE_CHUNK_CAP + *response = scratch_buffer + LIBSPDM_SCRATCH_BUFFER_SECURE_MESSAGE_OFFSET + + transport_header_size; + *response_size = LIBSPDM_SCRATCH_BUFFER_SECURE_MESSAGE_CAPACITY - transport_header_size; + #else + *response = scratch_buffer + transport_header_size; + *response_size = scratch_buffer_size - transport_header_size; + #endif + + backup_response = *response; + backup_response_size = *response_size; + + status = spdm_context->transport_decode_message( + spdm_context, &message_session_id, &is_message_app_message, + false, message_size, message, response_size, response); + + reset_key_update = false; + temp_session_context = NULL; + + if (status == LIBSPDM_STATUS_SESSION_TRY_DISCARD_KEY_UPDATE) { + /* Failed to decode, but have backup keys. Try rolling back before aborting. + * message_session_id must be valid for us to have attempted decryption. */ + if (message_session_id == NULL) { + return LIBSPDM_STATUS_INVALID_STATE_LOCAL; + } + temp_session_context = libspdm_get_secured_message_context_via_session_id( + spdm_context, *message_session_id); + if (temp_session_context == NULL) { + return LIBSPDM_STATUS_INVALID_STATE_LOCAL; + } + + result = libspdm_activate_update_session_data_key( + temp_session_context, LIBSPDM_KEY_UPDATE_ACTION_RESPONDER, false); + if (!result) { + return LIBSPDM_STATUS_INVALID_STATE_LOCAL; + } + + /* Retry decoding message with backup Requester key. + * Must reset some of the parameters in case they were modified */ + message_session_id = NULL; + is_message_app_message = false; + *response = backup_response; + *response_size = backup_response_size; + status = spdm_context->transport_decode_message( + spdm_context, &message_session_id, &is_message_app_message, + false, message_size, message, response_size, response); + + reset_key_update = true; + } + + if (session_id != NULL) { + if (message_session_id == NULL) { + LIBSPDM_DEBUG((LIBSPDM_DEBUG_INFO, + "libspdm_receive_spdm_response[%x] GetSessionId - NULL\n", + (session_id != NULL) ? *session_id : 0x0)); + goto error; + } + if (*message_session_id != *session_id) { + LIBSPDM_DEBUG((LIBSPDM_DEBUG_INFO, + "libspdm_receive_spdm_response[%x] GetSessionId - %x\n", + (session_id != NULL) ? *session_id : 0x0, + *message_session_id)); + goto error; + } + } else { + if (message_session_id != NULL) { + LIBSPDM_DEBUG((LIBSPDM_DEBUG_INFO, + "libspdm_receive_spdm_response[%x] GetSessionId - %x\n", + (session_id != NULL) ? *session_id : 0x0, + *message_session_id)); + goto error; + } + } + + if ((is_app_message && !is_message_app_message) || + (!is_app_message && is_message_app_message)) { + LIBSPDM_DEBUG((LIBSPDM_DEBUG_INFO, + "libspdm_receive_spdm_response[%x] app_message mismatch\n", + (session_id != NULL) ? *session_id : 0x0)); + goto error; + } + + LIBSPDM_DEBUG((LIBSPDM_DEBUG_INFO, "libspdm_receive_spdm_response[%x] (0x%x): \n", + (session_id != NULL) ? *session_id : 0x0, *response_size)); + if (LIBSPDM_STATUS_IS_ERROR(status)) { + LIBSPDM_DEBUG((LIBSPDM_DEBUG_INFO, + "libspdm_receive_spdm_response[%x] status - %p\n", + (session_id != NULL) ? *session_id : 0x0, status)); + } else { + LIBSPDM_INTERNAL_DUMP_HEX(*response, *response_size); + } + + /* Handle special case: + * If the Responder returns RESPONSE_NOT_READY error to KEY_UPDATE, the Requester needs + * to activate backup key to parse the error. Then later the Responder will return SUCCESS, + * the Requester needs new key. So we need to restore the environment by + * libspdm_create_update_session_data_key() again.*/ + if (reset_key_update) + { + /* temp_session_context and message_session_id must necessarily + * be valid for us to reach here. */ + if (temp_session_context == NULL || message_session_id == NULL) { + return LIBSPDM_STATUS_INVALID_STATE_LOCAL; + } + result = libspdm_create_update_session_data_key( + temp_session_context, LIBSPDM_KEY_UPDATE_ACTION_RESPONDER); + if (!result) { + return LIBSPDM_STATUS_INVALID_STATE_LOCAL; + } + } + + return status; + +error: + if (spdm_context->last_spdm_error.error_code == SPDM_ERROR_CODE_DECRYPT_ERROR) { + return LIBSPDM_STATUS_SESSION_MSG_ERROR; + } else { + return LIBSPDM_STATUS_RECEIVE_FAIL; + } +} + +#if (LIBSPDM_ENABLE_CAPABILITY_CHUNK_CAP) || (LIBSPDM_ENABLE_CHUNK_CAP) +libspdm_return_t libspdm_handle_large_request( + libspdm_context_t *spdm_context, + const uint32_t *session_id, + size_t request_size, void *request) +{ + libspdm_return_t status; + + spdm_chunk_send_request_t *spdm_request; + size_t spdm_request_size; + spdm_chunk_send_ack_response_t *spdm_response; + uint8_t *message; + size_t message_size; + void *response; + size_t response_size; + size_t transport_header_size; + + uint8_t *scratch_buffer; + size_t scratch_buffer_size; + + uint8_t *chunk_ptr; + size_t copy_size; + libspdm_chunk_info_t *send_info; + + /* Fail if requester or responder does not support chunk cap */ + if (!libspdm_is_capabilities_flag_supported( + spdm_context, true, + SPDM_GET_CAPABILITIES_REQUEST_FLAGS_CHUNK_CAP, + SPDM_GET_CAPABILITIES_RESPONSE_FLAGS_CHUNK_CAP)) { + return LIBSPDM_STATUS_ERROR_PEER; + } + + /* now we can get sender buffer */ + transport_header_size = spdm_context->transport_get_header_size(spdm_context); + + libspdm_get_scratch_buffer(spdm_context, (void**) &scratch_buffer, &scratch_buffer_size); + LIBSPDM_ASSERT(scratch_buffer_size >= LIBSPDM_SCRATCH_BUFFER_SIZE); + + /* Temporary send/receive buffers for chunking are in the scratch space */ + message = scratch_buffer + LIBSPDM_SCRATCH_BUFFER_SENDER_RECEIVER_OFFSET; + message_size = LIBSPDM_SCRATCH_BUFFER_SENDER_RECEIVER_CAPACITY; + + send_info = &spdm_context->chunk_context.send; + send_info->chunk_in_use = true; + + /* The first section of the scratch + * buffer may be used for other purposes. Use only after that section. */ + send_info->large_message = scratch_buffer + LIBSPDM_SCRATCH_BUFFER_LARGE_MESSAGE_OFFSET; + send_info->large_message_capacity = LIBSPDM_SCRATCH_BUFFER_LARGE_MESSAGE_CAPACITY; + + libspdm_zero_mem(send_info->large_message, send_info->large_message_capacity); + libspdm_copy_mem(send_info->large_message, send_info->large_message_capacity, + request, request_size); + + send_info->large_message_size = request_size; + send_info->chunk_bytes_transferred = 0; + send_info->chunk_seq_no = 0; + request = NULL; /* Invalidate to prevent accidental use. */ + request_size = 0; + + do { + LIBSPDM_ASSERT(send_info->large_message_capacity >= transport_header_size); + spdm_request = (spdm_chunk_send_request_t*) ((uint8_t*) message + transport_header_size); + spdm_request_size = message_size - transport_header_size; + + spdm_request->header.spdm_version = libspdm_get_connection_version(spdm_context); + spdm_request->header.request_response_code = SPDM_CHUNK_SEND; + spdm_request->header.param1 = 0; + spdm_request->header.param2 = send_info->chunk_handle; + spdm_request->chunk_seq_no = send_info->chunk_seq_no; + spdm_request->reserved = 0; + chunk_ptr = (uint8_t*) (spdm_request + 1); + + if (spdm_context->connection_info.capability.data_transfer_size + - sizeof(spdm_chunk_send_request_t) + < (send_info->large_message_size - send_info->chunk_bytes_transferred)) { + + copy_size = spdm_context->connection_info.capability.data_transfer_size + - sizeof(spdm_chunk_send_request_t); + } + else { + copy_size = (send_info->large_message_size - send_info->chunk_bytes_transferred); + } + + if (send_info->chunk_seq_no == 0) { + *(uint32_t*) (spdm_request + 1) = (uint32_t) send_info->large_message_size; + chunk_ptr += sizeof(uint32_t); + copy_size -= sizeof(uint32_t); + } + + spdm_request->chunk_size = (uint32_t) copy_size; + + libspdm_copy_mem( + chunk_ptr, spdm_request_size - ((uint8_t*) spdm_request - (uint8_t*) message), + (uint8_t*)send_info->large_message + send_info->chunk_bytes_transferred, copy_size); + + send_info->chunk_bytes_transferred += copy_size; + if (send_info->chunk_bytes_transferred >= send_info->large_message_size) { + spdm_request->header.param1 |= SPDM_CHUNK_SEND_REQUEST_ATTRIBUTE_LAST_CHUNK; + } + + spdm_request_size = (chunk_ptr + copy_size) - (uint8_t*)spdm_request; + status = libspdm_send_request( + spdm_context, session_id, false, + spdm_request_size, spdm_request); + + spdm_request = NULL; + spdm_request_size = 0; + + if (LIBSPDM_STATUS_IS_ERROR(status)) { + break; + } + + response = message; + response_size = message_size; + + libspdm_zero_mem(response, response_size); + + status = libspdm_receive_response( + spdm_context, session_id, false, + &response_size, &response); + + if (LIBSPDM_STATUS_IS_ERROR(status)) { + break; + } + spdm_response = (void*) (response); + + if (response_size < sizeof(spdm_message_header_t)) { + status = LIBSPDM_STATUS_INVALID_MSG_SIZE; + break; + } + if (spdm_response->header.spdm_version != libspdm_get_connection_version(spdm_context)) { + status = LIBSPDM_STATUS_INVALID_MSG_FIELD; + break; + } + + if (spdm_response->header.request_response_code == SPDM_ERROR + && spdm_response->header.param1 == SPDM_ERROR_CODE_LARGE_RESPONSE) { + + /* It is possible that the CHUNK_SEND_ACK + chunk response is larger + * than the DATA_TRANSFER_SIZE. In this case an ERROR_LARGE_RESPONSE + * is returned directly in the response buffer rather than part of + * the CHUNK_SEND_ACK. Store this error response in scratch buffer + * to be handled when reading response. Also note that in this case + * of large response, the CHUNK_SEND_ACK portion is not sent. + * Only the response portion that requires the CHUNK_GET is sent */ + if (response_size < send_info->large_message_capacity) { + libspdm_copy_mem( + send_info->large_message, send_info->large_message_capacity, + spdm_response, response_size); + send_info->large_message_size = response_size; + break; + } + else { + status = LIBSPDM_STATUS_INVALID_MSG_SIZE; + break; + } + } else { + if (spdm_response->header.request_response_code != SPDM_CHUNK_SEND_ACK) { + status = LIBSPDM_STATUS_INVALID_MSG_FIELD; + break; + } + + if (response_size < sizeof(spdm_chunk_send_ack_response_t)) { + status = LIBSPDM_STATUS_INVALID_MSG_SIZE; + break; + } + if (spdm_response->header.param1 + & SPDM_CHUNK_SEND_ACK_RESPONSE_ATTRIBUTE_EARLY_ERROR_DETECTED) { + + /* Store the error response in scratch buffer to be read by + * libspdm_receive_spdm_response and returned to its caller + * and handled in the error response handling flow */ + libspdm_copy_mem( + send_info->large_message, + send_info->large_message_capacity, + (uint8_t*) (spdm_response + 1), + response_size - sizeof(spdm_chunk_send_ack_response_t)); + + send_info->large_message_size = + (response_size - sizeof(spdm_chunk_send_ack_response_t)); + + status = LIBSPDM_STATUS_SUCCESS; + break; + } + if (spdm_response->header.param2 != send_info->chunk_handle) { + status = LIBSPDM_STATUS_INVALID_MSG_FIELD; + break; + } + if (send_info->chunk_seq_no != spdm_response->chunk_seq_no) { + status = LIBSPDM_STATUS_INVALID_MSG_FIELD; + break; + } + + chunk_ptr = (uint8_t*) (spdm_response + 1); + send_info->chunk_seq_no++; + + if (send_info->chunk_bytes_transferred >= send_info->large_message_size) { + + /* All bytes have been transferred. Store response in scratch buffer + * to be read by libspdm_receive_spdm_response */ + libspdm_copy_mem( + send_info->large_message, send_info->large_message_capacity, + chunk_ptr, response_size - sizeof(spdm_chunk_send_ack_response_t)); + send_info->large_message_size = + (response_size - sizeof(spdm_chunk_send_ack_response_t)); + break; + } + } + + } while (LIBSPDM_STATUS_IS_SUCCESS(status) + && send_info->chunk_bytes_transferred < send_info->large_message_size); + + if (LIBSPDM_STATUS_IS_ERROR(status)) { + + send_info->chunk_in_use = false; + send_info->chunk_handle++; /* Implicit wrap-around*/ + send_info->chunk_seq_no = 0; + send_info->chunk_bytes_transferred = 0; + send_info->large_message = NULL; + send_info->large_message_size = 0; + } + + return status; +} +#endif /* LIBSPDM_ENABLE_CAPABILITY_CHUNK_CAP */ + +libspdm_return_t libspdm_send_spdm_request(libspdm_context_t *spdm_context, + const uint32_t *session_id, + size_t request_size, void *request) +{ + libspdm_session_info_t *session_info; + libspdm_session_state_t session_state; + libspdm_return_t status; + + if ((spdm_context->connection_info.capability.data_transfer_size != 0) && + (request_size > spdm_context->connection_info.capability.data_transfer_size) && + !libspdm_is_capabilities_flag_supported( + spdm_context, true, + SPDM_GET_CAPABILITIES_REQUEST_FLAGS_CHUNK_CAP, + SPDM_GET_CAPABILITIES_RESPONSE_FLAGS_CHUNK_CAP)) { + return LIBSPDM_STATUS_SEND_FAIL; + } + + if ((session_id != NULL) && + libspdm_is_capabilities_flag_supported( + spdm_context, true, + SPDM_GET_CAPABILITIES_REQUEST_FLAGS_HANDSHAKE_IN_THE_CLEAR_CAP, + SPDM_GET_CAPABILITIES_RESPONSE_FLAGS_HANDSHAKE_IN_THE_CLEAR_CAP)) { + session_info = libspdm_get_session_info_via_session_id( + spdm_context, *session_id); + LIBSPDM_ASSERT(session_info != NULL); + if (session_info == NULL) { + return LIBSPDM_STATUS_INVALID_STATE_LOCAL; + } + session_state = libspdm_secured_message_get_session_state( + session_info->secured_message_context); + if ((session_state == LIBSPDM_SESSION_STATE_HANDSHAKING) && + !session_info->use_psk) { + session_id = NULL; + } + } + + if (((const spdm_message_header_t*) request)->request_response_code != SPDM_GET_VERSION + && ((const spdm_message_header_t*) request)->request_response_code != SPDM_GET_CAPABILITIES + && spdm_context->connection_info.capability.data_transfer_size != 0 + && request_size > spdm_context->connection_info.capability.data_transfer_size) { + + #if LIBSPDM_ENABLE_CAPABILITY_CHUNK_CAP || LIBSPDM_ENABLE_CHUNK_CAP + /* libspdm_send_request is not called with the original request in this flow. + * This leads to the last_spdm_request field not having the original request value. + * The caller assumes the request has been copied to last_spdm_request, + * so that it can compare last_spdm_request's fields with response fields + * Therefore the request must be copied to last_spdm_request here. */ + + if (((const spdm_message_header_t*) request)->request_response_code != SPDM_RESPOND_IF_READY + && ((const spdm_message_header_t*) request)->request_response_code != SPDM_CHUNK_GET + && ((const spdm_message_header_t*) request)->request_response_code != SPDM_CHUNK_SEND) { + libspdm_copy_mem( + spdm_context->last_spdm_request, sizeof(spdm_context->last_spdm_request), + request, request_size); + spdm_context->last_spdm_request_size = request_size; + } + + status = libspdm_handle_large_request( + spdm_context, session_id, request_size, request); + #else /* LIBSPDM_ENABLE_CAPABILITY_CHUNK_CAP*/ + status = LIBSPDM_STATUS_BUFFER_TOO_SMALL; + #endif /* LIBSPDM_ENABLE_CAPABILITY_CHUNK_CAP*/ + } + else + { + status = libspdm_send_request(spdm_context, session_id, false, request_size, request); + } + + #if LIBSPDM_ENABLE_MSG_LOG + if (status == LIBSPDM_STATUS_SUCCESS) { + libspdm_append_msg_log(spdm_context, request, request_size); + } + #endif + + return status; +} + +libspdm_return_t libspdm_receive_spdm_response(libspdm_context_t *spdm_context, + const uint32_t *session_id, + size_t *response_size, + void **response) +{ + libspdm_return_t status; + libspdm_session_info_t *session_info; + libspdm_session_state_t session_state; + + #if (LIBSPDM_ENABLE_CAPABILITY_CHUNK_CAP) || (LIBSPDM_ENABLE_CHUNK_CAP) + spdm_message_header_t *spdm_response; + size_t response_capacity; + libspdm_chunk_info_t *send_info; + #endif /* LIBSPDM_ENABLE_CAPABILITY_CHUNK_CAP */ + + if ((session_id != NULL) && + libspdm_is_capabilities_flag_supported( + spdm_context, true, + SPDM_GET_CAPABILITIES_REQUEST_FLAGS_HANDSHAKE_IN_THE_CLEAR_CAP, + SPDM_GET_CAPABILITIES_RESPONSE_FLAGS_HANDSHAKE_IN_THE_CLEAR_CAP)) { + session_info = libspdm_get_session_info_via_session_id( + spdm_context, *session_id); + LIBSPDM_ASSERT(session_info != NULL); + if (session_info == NULL) { + return LIBSPDM_STATUS_INVALID_STATE_LOCAL; + } + session_state = libspdm_secured_message_get_session_state( + session_info->secured_message_context); + if ((session_state == LIBSPDM_SESSION_STATE_HANDSHAKING) && + !session_info->use_psk) { + session_id = NULL; + } + } + + #if !(LIBSPDM_ENABLE_CAPABILITY_CHUNK_CAP) && !(LIBSPDM_ENABLE_CHUNK_CAP) + status = libspdm_receive_response(spdm_context, session_id, false, response_size, response); + #else /* LIBSPDM_ENABLE_CAPABILITY_CHUNK_CAP */ + send_info = &spdm_context->chunk_context.send; + if (send_info->chunk_in_use) { + libspdm_copy_mem(*response, *response_size, + send_info->large_message, send_info->large_message_size); + *response_size = send_info->large_message_size; + response_capacity = send_info->large_message_capacity; + + /* This response may either be an actual response or ERROR_LARGE_RESPONSE, + * the latter which should be handled in the large response handler. */ + + send_info->chunk_in_use = false; + send_info->chunk_handle++; /* Implicit wrap-around*/ + send_info->chunk_seq_no = 0; + send_info->chunk_bytes_transferred = 0; + send_info->large_message = NULL; + send_info->large_message_size = 0; + send_info->large_message_capacity = 0; + status = LIBSPDM_STATUS_SUCCESS; + } + else { + response_capacity = *response_size; + status = libspdm_receive_response(spdm_context, session_id, false, + response_size, response); + if (LIBSPDM_STATUS_IS_ERROR(status)) { + goto receive_done; + } + } + + spdm_response = (spdm_message_header_t*) (*response); + + if (*response_size < sizeof(spdm_message_header_t)) { + status = LIBSPDM_STATUS_INVALID_MSG_SIZE; + goto receive_done; + } + + if (spdm_response->request_response_code == SPDM_ERROR + && spdm_response->param1 == SPDM_ERROR_CODE_LARGE_RESPONSE) { + + status = libspdm_handle_error_large_response( + spdm_context, session_id, + response_size, (void*) spdm_response, response_capacity); + + if (LIBSPDM_STATUS_IS_ERROR(status)) { + goto receive_done; + } + + if (*response_size < sizeof(spdm_message_header_t)) { + status = LIBSPDM_STATUS_INVALID_MSG_SIZE; + goto receive_done; + } + + /* Per the spec, SPDM_VERSION and SPDM_CAPABILITIES shall not be chunked + * and should be an unexpected error. */ + if (spdm_response->request_response_code == SPDM_VERSION || + spdm_response->request_response_code == SPDM_CAPABILITIES + ) { + status = LIBSPDM_STATUS_INVALID_MSG_FIELD; + goto receive_done; + } + } + +receive_done: + #endif /* LIBSPDM_ENABLE_CAPABILITY_CHUNK_CAP */ + + return status; +} diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/libraries/libspdm/2.3.1/library/spdm_secured_message_lib/libspdm_secmes_context_data.c nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/libraries/libspdm/2.3.1/library/spdm_secured_message_lib/libspdm_secmes_context_data.c --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/libraries/libspdm/2.3.1/library/spdm_secured_message_lib/libspdm_secmes_context_data.c 1970-01-01 00:00:00.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/libraries/libspdm/2.3.1/library/spdm_secured_message_lib/libspdm_secmes_context_data.c 2024-03-05 22:14:17.000000000 +0000 @@ -0,0 +1,398 @@ +/** + * Copyright Notice: + * Copyright 2021-2022 DMTF. All rights reserved. + * License: BSD 3-Clause License. For full text see link: https://github.com/DMTF/libspdm/blob/main/LICENSE.md + **/ + +#include "internal/libspdm_secured_message_lib.h" + +/** + * Return the size in bytes of a single SPDM secured message context. + * + * @return the size in bytes of a single SPDM secured message context. + **/ +size_t libspdm_secured_message_get_context_size(void) +{ + size_t size; + + size = sizeof(libspdm_secured_message_context_t); + LIBSPDM_ASSERT (size == LIBSPDM_SECURED_MESSAGE_CONTEXT_SIZE); + return size; +} + +/** + * Initialize an SPDM secured message context. + * + * The size in bytes of the spdm_secured_message_context can be returned by libspdm_secured_message_get_context_size. + * + * @param spdm_secured_message_context A pointer to the SPDM secured message context. + */ +void libspdm_secured_message_init_context(void *spdm_secured_message_context) +{ + libspdm_secured_message_context_t *secured_message_context; + + secured_message_context = spdm_secured_message_context; + libspdm_zero_mem(secured_message_context, sizeof(libspdm_secured_message_context_t)); +} + +/** + * Set use_psk to an SPDM secured message context. + * + * @param spdm_secured_message_context A pointer to the SPDM secured message context. + * @param use_psk Indicate if the SPDM session use PSK. + */ +void libspdm_secured_message_set_use_psk(void *spdm_secured_message_context, bool use_psk) +{ + libspdm_secured_message_context_t *secured_message_context; + + secured_message_context = spdm_secured_message_context; + secured_message_context->use_psk = use_psk; +} + +/** + * Set session_state to an SPDM secured message context. + * + * @param spdm_secured_message_context A pointer to the SPDM secured message context. + * @param session_state Indicate the SPDM session state. + */ +void libspdm_secured_message_set_session_state( + void *spdm_secured_message_context, + libspdm_session_state_t session_state) +{ + libspdm_secured_message_context_t *secured_message_context; + + secured_message_context = spdm_secured_message_context; + secured_message_context->session_state = session_state; + + if (session_state == LIBSPDM_SESSION_STATE_ESTABLISHED) { + /* session handshake key should be zeroized after handshake phase. */ + libspdm_clear_handshake_secret(secured_message_context); + libspdm_clear_master_secret(secured_message_context); + } +} + +/** + * Return session_state of an SPDM secured message context. + * + * @param spdm_secured_message_context A pointer to the SPDM secured message context. + * + * @return the SPDM session state. + */ +libspdm_session_state_t +libspdm_secured_message_get_session_state(void *spdm_secured_message_context) +{ + libspdm_secured_message_context_t *secured_message_context; + + secured_message_context = spdm_secured_message_context; + return secured_message_context->session_state; +} + +/** + * Set session_type to an SPDM secured message context. + * + * @param spdm_secured_message_context A pointer to the SPDM secured message context. + * @param session_type Indicate the SPDM session type. + */ +void libspdm_secured_message_set_session_type(void *spdm_secured_message_context, + libspdm_session_type_t session_type) +{ + libspdm_secured_message_context_t *secured_message_context; + + secured_message_context = spdm_secured_message_context; + secured_message_context->session_type = session_type; +} + +/** + * Set algorithm to an SPDM secured message context. + * + * @param spdm_secured_message_context A pointer to the SPDM secured message context. + * @param base_hash_algo Indicate the negotiated base_hash_algo for the SPDM session. + * @param dhe_named_group Indicate the negotiated dhe_named_group for the SPDM session. + * @param aead_cipher_suite Indicate the negotiated aead_cipher_suite for the SPDM session. + * @param key_schedule Indicate the negotiated key_schedule for the SPDM session. + */ +void libspdm_secured_message_set_algorithms(void *spdm_secured_message_context, + const spdm_version_number_t version, + const spdm_version_number_t secured_message_version, + uint32_t base_hash_algo, + uint16_t dhe_named_group, + uint16_t aead_cipher_suite, + uint16_t key_schedule) +{ + libspdm_secured_message_context_t *secured_message_context; + + secured_message_context = spdm_secured_message_context; + secured_message_context->version = version; + secured_message_context->secured_message_version = secured_message_version; + secured_message_context->base_hash_algo = base_hash_algo; + secured_message_context->dhe_named_group = dhe_named_group; + secured_message_context->aead_cipher_suite = aead_cipher_suite; + secured_message_context->key_schedule = key_schedule; + + secured_message_context->hash_size = + libspdm_get_hash_size(secured_message_context->base_hash_algo); + secured_message_context->dhe_key_size = libspdm_get_dhe_pub_key_size( + secured_message_context->dhe_named_group); + secured_message_context->aead_key_size = libspdm_get_aead_key_size( + secured_message_context->aead_cipher_suite); + secured_message_context->aead_iv_size = libspdm_get_aead_iv_size( + secured_message_context->aead_cipher_suite); + secured_message_context->aead_tag_size = libspdm_get_aead_tag_size( + secured_message_context->aead_cipher_suite); +} + +/** + * Set the psk_hint to an SPDM secured message context. + * + * @param spdm_secured_message_context A pointer to the SPDM secured message context. + * @param psk_hint Indicate the PSK hint. + * @param psk_hint_size The size in bytes of the PSK hint. + */ +void libspdm_secured_message_set_psk_hint(void *spdm_secured_message_context, + const void *psk_hint, + size_t psk_hint_size) +{ + libspdm_secured_message_context_t *secured_message_context; + + secured_message_context = spdm_secured_message_context; + if ((psk_hint != NULL) && (psk_hint_size > 0)) { + secured_message_context->psk_hint_size = psk_hint_size; + libspdm_copy_mem(secured_message_context->psk_hint, + LIBSPDM_PSK_MAX_HINT_LENGTH, + psk_hint, + psk_hint_size); + } +} + +/** + * Import the DHE Secret to an SPDM secured message context. + * + * @param spdm_secured_message_context A pointer to the SPDM secured message context. + * @param dhe_secret Indicate the DHE secret. + * @param dhe_secret_size The size in bytes of the DHE secret. + * + * @retval RETURN_SUCCESS DHE Secret is imported. + */ +bool libspdm_secured_message_import_dhe_secret(void *spdm_secured_message_context, + const void *dhe_secret, + size_t dhe_secret_size) +{ + libspdm_secured_message_context_t *secured_message_context; + + secured_message_context = spdm_secured_message_context; + if (dhe_secret_size > secured_message_context->dhe_key_size) { + return false; + } + secured_message_context->dhe_key_size = dhe_secret_size; + libspdm_copy_mem(secured_message_context->master_secret.dhe_secret, + sizeof(secured_message_context->master_secret.dhe_secret), + dhe_secret, dhe_secret_size); + return true; +} + +bool libspdm_secured_message_export_master_secret( + void *spdm_secured_message_context, void *export_master_secret, + size_t *export_master_secret_size) +{ + libspdm_secured_message_context_t *secured_message_context; + + secured_message_context = spdm_secured_message_context; + + if (*export_master_secret_size > secured_message_context->hash_size) { + *export_master_secret_size = secured_message_context->hash_size; + } + + libspdm_copy_mem(export_master_secret, *export_master_secret_size, + secured_message_context->export_master_secret, + *export_master_secret_size); + + return true; +} + +void libspdm_secured_message_clear_export_master_secret(void *spdm_secured_message_context) +{ + libspdm_secured_message_context_t *secured_message_context; + + LIBSPDM_ASSERT(spdm_secured_message_context != NULL); + + secured_message_context = spdm_secured_message_context; + + libspdm_zero_mem(secured_message_context->export_master_secret, + sizeof(secured_message_context->export_master_secret)); +} + +/** + * Export the session_keys from an SPDM secured message context. + * + * @param spdm_secured_message_context A pointer to the SPDM secured message context. + * @param session_keys Indicate the buffer to store the session_keys in libspdm_secure_session_keys_struct_t. + * @param session_keys_size The size in bytes of the session_keys in libspdm_secure_session_keys_struct_t. + * + * @retval RETURN_SUCCESS session_keys are exported. + */ +bool libspdm_secured_message_export_session_keys(void *spdm_secured_message_context, + void *session_keys, + size_t *session_keys_size) +{ + libspdm_secured_message_context_t *secured_message_context; + size_t struct_size; + libspdm_secure_session_keys_struct_t *session_keys_struct; + uint8_t *ptr; + + secured_message_context = spdm_secured_message_context; + struct_size = sizeof(libspdm_secure_session_keys_struct_t) + + (secured_message_context->aead_key_size + + secured_message_context->aead_iv_size + sizeof(uint64_t)) * 2; + + if (*session_keys_size < struct_size) { + *session_keys_size = struct_size; + return false; + } + + session_keys_struct = session_keys; + session_keys_struct->version = LIBSPDM_SECURE_SESSION_KEYS_STRUCT_VERSION; + session_keys_struct->aead_key_size = (uint32_t)secured_message_context->aead_key_size; + session_keys_struct->aead_iv_size = (uint32_t)secured_message_context->aead_iv_size; + + ptr = (void *)(session_keys_struct + 1); + libspdm_copy_mem(ptr, + *session_keys_size - (ptr - (uint8_t*)session_keys), + secured_message_context->application_secret.request_data_encryption_key, + secured_message_context->aead_key_size); + ptr += secured_message_context->aead_key_size; + libspdm_copy_mem(ptr, + *session_keys_size - (ptr - (uint8_t*)session_keys), + secured_message_context->application_secret.request_data_salt, + secured_message_context->aead_iv_size); + ptr += secured_message_context->aead_iv_size; + libspdm_copy_mem(ptr, + *session_keys_size - (ptr - (uint8_t*)session_keys), + &secured_message_context->application_secret.request_data_sequence_number, + sizeof(uint64_t)); + ptr += sizeof(uint64_t); + libspdm_copy_mem(ptr, + *session_keys_size - (ptr - (uint8_t*)session_keys), + secured_message_context->application_secret.response_data_encryption_key, + secured_message_context->aead_key_size); + ptr += secured_message_context->aead_key_size; + libspdm_copy_mem(ptr, + *session_keys_size - (ptr - (uint8_t*)session_keys), + secured_message_context->application_secret.response_data_salt, + secured_message_context->aead_iv_size); + ptr += secured_message_context->aead_iv_size; + libspdm_copy_mem(ptr, + *session_keys_size - (ptr - (uint8_t*)session_keys), + &secured_message_context->application_secret.response_data_sequence_number, + sizeof(uint64_t)); + ptr += sizeof(uint64_t); + return true; +} + +/** + * Import the session_keys from an SPDM secured message context. + * + * @param spdm_secured_message_context A pointer to the SPDM secured message context. + * @param session_keys Indicate the buffer to store the session_keys in libspdm_secure_session_keys_struct_t. + * @param session_keys_size The size in bytes of the session_keys in libspdm_secure_session_keys_struct_t. + * + * @retval RETURN_SUCCESS session_keys are imported. + */ +bool +libspdm_secured_message_import_session_keys(void *spdm_secured_message_context, + const void *session_keys, + size_t session_keys_size) +{ + libspdm_secured_message_context_t *secured_message_context; + size_t struct_size; + const libspdm_secure_session_keys_struct_t *session_keys_struct; + const uint8_t *ptr; + + secured_message_context = spdm_secured_message_context; + struct_size = sizeof(libspdm_secure_session_keys_struct_t) + + (secured_message_context->aead_key_size + + secured_message_context->aead_iv_size + sizeof(uint64_t)) * 2; + + if (session_keys_size != struct_size) { + return false; + } + + session_keys_struct = session_keys; + if ((session_keys_struct->version != + LIBSPDM_SECURE_SESSION_KEYS_STRUCT_VERSION) || + (session_keys_struct->aead_key_size != + secured_message_context->aead_key_size) || + (session_keys_struct->aead_iv_size != + secured_message_context->aead_iv_size)) { + return false; + } + + ptr = (const void *)(session_keys_struct + 1); + libspdm_copy_mem(secured_message_context->application_secret.request_data_encryption_key, + sizeof(secured_message_context->application_secret + .request_data_encryption_key), + ptr, secured_message_context->aead_key_size); + ptr += secured_message_context->aead_key_size; + libspdm_copy_mem(secured_message_context->application_secret.request_data_salt, + sizeof(secured_message_context->application_secret + .request_data_salt), + ptr, secured_message_context->aead_iv_size); + ptr += secured_message_context->aead_iv_size; + libspdm_copy_mem(&secured_message_context->application_secret.request_data_sequence_number, + sizeof(secured_message_context->application_secret + .request_data_sequence_number), + ptr, sizeof(uint64_t)); + ptr += sizeof(uint64_t); + libspdm_copy_mem(secured_message_context->application_secret + .response_data_encryption_key, + sizeof(secured_message_context->application_secret + .response_data_encryption_key), + ptr, secured_message_context->aead_key_size); + ptr += secured_message_context->aead_key_size; + libspdm_copy_mem(secured_message_context->application_secret.response_data_salt, + sizeof(secured_message_context->application_secret.response_data_salt), + ptr, secured_message_context->aead_iv_size); + ptr += secured_message_context->aead_iv_size; + libspdm_copy_mem(&secured_message_context->application_secret.response_data_sequence_number, + sizeof(secured_message_context->application_secret + .response_data_sequence_number), + ptr, sizeof(uint64_t)); + ptr += sizeof(uint64_t); + return true; +} + +/** + * Get the last SPDM error struct of an SPDM context. + * + * @param spdm_context A pointer to the SPDM context. + * @param last_spdm_error Last SPDM error struct of an SPDM context. + */ +void libspdm_secured_message_get_last_spdm_error_struct( + void *spdm_secured_message_context, + libspdm_error_struct_t *last_spdm_error) +{ + libspdm_secured_message_context_t *secured_message_context; + + secured_message_context = spdm_secured_message_context; + libspdm_copy_mem(last_spdm_error, sizeof(libspdm_error_struct_t), + &secured_message_context->last_spdm_error, + sizeof(libspdm_error_struct_t)); +} + +/** + * Set the last SPDM error struct of an SPDM context. + * + * @param spdm_context A pointer to the SPDM context. + * @param last_spdm_error Last SPDM error struct of an SPDM context. + */ +void libspdm_secured_message_set_last_spdm_error_struct( + void *spdm_secured_message_context, + const libspdm_error_struct_t *last_spdm_error) +{ + libspdm_secured_message_context_t *secured_message_context; + + secured_message_context = spdm_secured_message_context; + libspdm_copy_mem(&secured_message_context->last_spdm_error, + sizeof(secured_message_context->last_spdm_error), + last_spdm_error, + sizeof(libspdm_error_struct_t)); +} diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/libraries/libspdm/2.3.1/library/spdm_secured_message_lib/libspdm_secmes_encode_decode.c nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/libraries/libspdm/2.3.1/library/spdm_secured_message_lib/libspdm_secmes_encode_decode.c --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/libraries/libspdm/2.3.1/library/spdm_secured_message_lib/libspdm_secmes_encode_decode.c 1970-01-01 00:00:00.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/libraries/libspdm/2.3.1/library/spdm_secured_message_lib/libspdm_secmes_encode_decode.c 2024-03-05 22:14:17.000000000 +0000 @@ -0,0 +1,580 @@ +/** + * Copyright Notice: + * Copyright 2021-2022 DMTF. All rights reserved. + * License: BSD 3-Clause License. For full text see link: https://github.com/DMTF/libspdm/blob/main/LICENSE.md + **/ + +#include "internal/libspdm_secured_message_lib.h" + +/** + * Encode an application message to a secured message. + * + * @param spdm_secured_message_context A pointer to the SPDM secured message context. + * @param session_id The session ID of the SPDM session. + * @param is_requester Indicates if it is a requester message. + * @param app_message_size size in bytes of the application message data buffer. + * @param app_message A pointer to a source buffer to store the application message. + * It shall point to the scratch buffer in spdm_context. + * Before app_message, there is room for spdm_secured_message_cipher_header_t. + * After (app_message + app_message_size), there is room for random bytes. + * @param secured_message_size size in bytes of the secured message data buffer. + * @param secured_message A pointer to a destination buffer to store the secured message. + * It shall point to the acquired sender buffer. + * @param spdm_secured_message_callbacks A pointer to a secured message callback functions structure. + * + * @retval RETURN_SUCCESS The application message is encoded successfully. + * @retval RETURN_INVALID_PARAMETER The message is NULL or the message_size is zero. + **/ +libspdm_return_t libspdm_encode_secured_message( + void *spdm_secured_message_context, uint32_t session_id, + bool is_requester, size_t app_message_size, + void *app_message, size_t *secured_message_size, + void *secured_message, + const libspdm_secured_message_callbacks_t *spdm_secured_message_callbacks) +{ + libspdm_secured_message_context_t *secured_message_context; + size_t total_secured_message_size; + size_t plain_text_size; + size_t cipher_text_size; + size_t aead_pad_size; + size_t aead_tag_size; + size_t aead_key_size; + size_t aead_iv_size; + uint8_t *a_data; + uint8_t *enc_msg; + uint8_t *dec_msg; + uint8_t *tag; + spdm_secured_message_a_data_header1_t *record_header1; + spdm_secured_message_a_data_header2_t *record_header2; + size_t record_header_size; + spdm_secured_message_cipher_header_t *enc_msg_header; + bool result; + uint8_t key[LIBSPDM_MAX_AEAD_KEY_SIZE]; + uint8_t salt[LIBSPDM_MAX_AEAD_IV_SIZE]; + uint64_t sequence_number; + uint64_t sequence_num_in_header; + uint8_t sequence_num_in_header_size; + libspdm_session_type_t session_type; + uint32_t rand_count; + uint32_t max_rand_count; + libspdm_session_state_t session_state; + + secured_message_context = spdm_secured_message_context; + + session_type = secured_message_context->session_type; + LIBSPDM_ASSERT((session_type == LIBSPDM_SESSION_TYPE_MAC_ONLY) || + (session_type == LIBSPDM_SESSION_TYPE_ENC_MAC)); + session_state = secured_message_context->session_state; + LIBSPDM_ASSERT((session_state == LIBSPDM_SESSION_STATE_HANDSHAKING) || + (session_state == LIBSPDM_SESSION_STATE_ESTABLISHED)); + + aead_tag_size = secured_message_context->aead_tag_size; + aead_key_size = secured_message_context->aead_key_size; + aead_iv_size = secured_message_context->aead_iv_size; + + switch (session_state) { + case LIBSPDM_SESSION_STATE_HANDSHAKING: + if (is_requester) { + libspdm_copy_mem(key, sizeof(key), + secured_message_context->handshake_secret + .request_handshake_encryption_key, + secured_message_context->aead_key_size); + libspdm_copy_mem(salt, sizeof(salt), + secured_message_context->handshake_secret.request_handshake_salt, + secured_message_context->aead_iv_size); + sequence_number = secured_message_context->handshake_secret + .request_handshake_sequence_number; + } else { + libspdm_copy_mem(key, sizeof(key), + secured_message_context->handshake_secret + .response_handshake_encryption_key, + secured_message_context->aead_key_size); + libspdm_copy_mem(salt, sizeof(salt), + secured_message_context->handshake_secret.response_handshake_salt, + secured_message_context->aead_iv_size); + sequence_number = secured_message_context->handshake_secret + .response_handshake_sequence_number; + } + break; + case LIBSPDM_SESSION_STATE_ESTABLISHED: + if (is_requester) { + libspdm_copy_mem(key, sizeof(key), + secured_message_context->application_secret + .request_data_encryption_key, + secured_message_context->aead_key_size); + libspdm_copy_mem(salt, sizeof(salt), + secured_message_context->application_secret.request_data_salt, + secured_message_context->aead_iv_size); + sequence_number = secured_message_context->application_secret + .request_data_sequence_number; + } else { + libspdm_copy_mem(key, sizeof(key), + secured_message_context->application_secret + .response_data_encryption_key, + secured_message_context->aead_key_size); + libspdm_copy_mem(salt, sizeof(salt), + secured_message_context->application_secret.response_data_salt, + secured_message_context->aead_iv_size); + sequence_number = secured_message_context->application_secret + .response_data_sequence_number; + } + break; + default: + LIBSPDM_ASSERT(false); + return LIBSPDM_STATUS_INVALID_STATE_LOCAL; + break; + } + + if (sequence_number == (uint64_t)-1) { + return LIBSPDM_STATUS_SEQUENCE_NUMBER_OVERFLOW; + } + + *(uint64_t *)salt = *(uint64_t *)salt ^ sequence_number; + + sequence_num_in_header = 0; + sequence_num_in_header_size = spdm_secured_message_callbacks->get_sequence_number( + sequence_number, (uint8_t *)&sequence_num_in_header); + LIBSPDM_ASSERT(sequence_num_in_header_size <= sizeof(sequence_num_in_header)); + + sequence_number++; + if (session_state == LIBSPDM_SESSION_STATE_HANDSHAKING) { + if (is_requester) { + secured_message_context->handshake_secret.request_handshake_sequence_number = + sequence_number; + } else { + secured_message_context->handshake_secret.response_handshake_sequence_number = + sequence_number; + } + } + else { + if (is_requester) { + secured_message_context->application_secret.request_data_sequence_number = + sequence_number; + } else { + secured_message_context->application_secret.response_data_sequence_number = + sequence_number; + } + } + + record_header_size = sizeof(spdm_secured_message_a_data_header1_t) + + sequence_num_in_header_size + + sizeof(spdm_secured_message_a_data_header2_t); + + switch (session_type) { + case LIBSPDM_SESSION_TYPE_ENC_MAC: + max_rand_count = spdm_secured_message_callbacks->get_max_random_number_count(); + if (max_rand_count != 0) { + rand_count = 0; + result = libspdm_get_random_number(sizeof(rand_count), (uint8_t *)&rand_count); + if (!result) { + return LIBSPDM_STATUS_LOW_ENTROPY; + } + rand_count = (uint8_t)((rand_count % max_rand_count) + 1); + } else { + rand_count = 0; + } + + plain_text_size = sizeof(spdm_secured_message_cipher_header_t) + app_message_size + + rand_count; + cipher_text_size = plain_text_size; + aead_pad_size = cipher_text_size - plain_text_size; + total_secured_message_size = record_header_size + cipher_text_size + aead_tag_size; + + LIBSPDM_ASSERT(*secured_message_size >= total_secured_message_size); + if (*secured_message_size < total_secured_message_size) { + *secured_message_size = total_secured_message_size; + return LIBSPDM_STATUS_BUFFER_TOO_SMALL; + } + *secured_message_size = total_secured_message_size; + record_header1 = (void *)secured_message; + record_header2 = (void *)((uint8_t *)record_header1 + + sizeof(spdm_secured_message_a_data_header1_t) + + sequence_num_in_header_size); + record_header1->session_id = session_id; + libspdm_copy_mem(record_header1 + 1, + *secured_message_size + - ((uint8_t*)(record_header1 + 1) - (uint8_t*)secured_message), + &sequence_num_in_header, + sequence_num_in_header_size); + record_header2->length = (uint16_t)(cipher_text_size + aead_tag_size); + + enc_msg_header = + (void *)((uint8_t *)app_message - sizeof(spdm_secured_message_cipher_header_t)); + enc_msg_header->application_data_length = (uint16_t)app_message_size; + result = libspdm_get_random_number(rand_count, + (uint8_t *)enc_msg_header + + sizeof(spdm_secured_message_cipher_header_t) + + app_message_size); + if (!result) { + return LIBSPDM_STATUS_LOW_ENTROPY; + } + libspdm_zero_mem((uint8_t *)enc_msg_header + plain_text_size, aead_pad_size); + + a_data = (uint8_t *)record_header1; + enc_msg = (uint8_t *)(record_header2 + 1); + dec_msg = (uint8_t *)enc_msg_header; + tag = (uint8_t *)record_header1 + record_header_size + + cipher_text_size; + + result = libspdm_aead_encryption( + secured_message_context->secured_message_version, + secured_message_context->aead_cipher_suite, key, + aead_key_size, salt, aead_iv_size, (uint8_t *)a_data, + record_header_size, dec_msg, cipher_text_size, tag, + aead_tag_size, enc_msg, &cipher_text_size); + break; + + case LIBSPDM_SESSION_TYPE_MAC_ONLY: + total_secured_message_size = + record_header_size + app_message_size + aead_tag_size; + + LIBSPDM_ASSERT(*secured_message_size >= total_secured_message_size); + if (*secured_message_size < total_secured_message_size) { + *secured_message_size = total_secured_message_size; + return LIBSPDM_STATUS_BUFFER_TOO_SMALL; + } + *secured_message_size = total_secured_message_size; + record_header1 = (void *)secured_message; + record_header2 = + (void *)((uint8_t *)record_header1 + + sizeof(spdm_secured_message_a_data_header1_t) + + sequence_num_in_header_size); + record_header1->session_id = session_id; + libspdm_copy_mem(record_header1 + 1, + *secured_message_size + - ((uint8_t*)(record_header1 + 1) - (uint8_t*)secured_message), + &sequence_num_in_header, + sequence_num_in_header_size); + record_header2->length = + (uint16_t)(app_message_size + aead_tag_size); + libspdm_copy_mem(record_header2 + 1, + *secured_message_size + - ((uint8_t*)(record_header2 + 1) - (uint8_t*)secured_message), + app_message, app_message_size); + a_data = (uint8_t *)record_header1; + tag = (uint8_t *)record_header1 + record_header_size + app_message_size; + + result = libspdm_aead_encryption( + secured_message_context->secured_message_version, + secured_message_context->aead_cipher_suite, key, + aead_key_size, salt, aead_iv_size, (uint8_t *)a_data, + record_header_size + app_message_size, NULL, 0, tag, + aead_tag_size, NULL, NULL); + break; + + default: + LIBSPDM_ASSERT(false); + return LIBSPDM_STATUS_UNSUPPORTED_CAP; + } + if (!result) { + return LIBSPDM_STATUS_CRYPTO_ERROR; + } + return LIBSPDM_STATUS_SUCCESS; +} + +/** + * Decode an application message from a secured message. + * + * @param spdm_secured_message_context A pointer to the SPDM secured message context. + * @param session_id The session ID of the SPDM session. + * @param is_requester Indicates if it is a requester message. + * @param secured_message_size size in bytes of the secured message data buffer. + * @param secured_message A pointer to a source buffer to store the secured message. + * It shall point to the acquired receiver buffer. + * @param app_message_size size in bytes of the application message data buffer. + * @param app_message A pointer to a destination buffer to store the application message. + * It shall point to the scratch buffer in spdm_context. + * On input, the app_message pointer shall point to a big enough buffer to hold the decrypted message + * On output, the app_message pointer shall be inside of [app_message, app_message + app_message_size] + * @param spdm_secured_message_callbacks A pointer to a secured message callback functions structure. + * + * @retval RETURN_SUCCESS The application message is decoded successfully. + * @retval RETURN_INVALID_PARAMETER The message is NULL or the message_size is zero. + * @retval RETURN_UNSUPPORTED The secured_message is unsupported. + **/ +libspdm_return_t libspdm_decode_secured_message( + void *spdm_secured_message_context, uint32_t session_id, + bool is_requester, size_t secured_message_size, + void *secured_message, size_t *app_message_size, + void **app_message, + const libspdm_secured_message_callbacks_t *spdm_secured_message_callbacks) +{ + libspdm_secured_message_context_t *secured_message_context; + size_t plain_text_size; + size_t cipher_text_size; + size_t aead_tag_size; + size_t aead_key_size; + size_t aead_iv_size; + const uint8_t *a_data; + const uint8_t *enc_msg; + uint8_t *dec_msg; + const uint8_t *tag; + spdm_secured_message_a_data_header1_t *record_header1; + spdm_secured_message_a_data_header2_t *record_header2; + size_t record_header_size; + spdm_secured_message_cipher_header_t *enc_msg_header; + bool result; + uint8_t key[LIBSPDM_MAX_AEAD_KEY_SIZE]; + uint8_t salt[LIBSPDM_MAX_AEAD_IV_SIZE]; + uint64_t sequence_number; + uint64_t sequence_num_in_header; + uint8_t sequence_num_in_header_size; + libspdm_session_type_t session_type; + libspdm_session_state_t session_state; + libspdm_error_struct_t spdm_error; + + spdm_error.error_code = 0; + spdm_error.session_id = 0; + libspdm_secured_message_set_last_spdm_error_struct(spdm_secured_message_context, &spdm_error); + + spdm_error.error_code = SPDM_ERROR_CODE_DECRYPT_ERROR; + spdm_error.session_id = session_id; + + secured_message_context = spdm_secured_message_context; + + session_type = secured_message_context->session_type; + LIBSPDM_ASSERT((session_type == LIBSPDM_SESSION_TYPE_MAC_ONLY) || + (session_type == LIBSPDM_SESSION_TYPE_ENC_MAC)); + session_state = secured_message_context->session_state; + LIBSPDM_ASSERT((session_state == LIBSPDM_SESSION_STATE_HANDSHAKING) || + (session_state == LIBSPDM_SESSION_STATE_ESTABLISHED)); + + aead_tag_size = secured_message_context->aead_tag_size; + aead_key_size = secured_message_context->aead_key_size; + aead_iv_size = secured_message_context->aead_iv_size; + + switch (session_state) { + case LIBSPDM_SESSION_STATE_HANDSHAKING: + if (is_requester) { + libspdm_copy_mem(key, sizeof(key), + secured_message_context->handshake_secret + .request_handshake_encryption_key, + secured_message_context->aead_key_size); + libspdm_copy_mem(salt, sizeof(salt), + secured_message_context->handshake_secret + .request_handshake_salt, + secured_message_context->aead_iv_size); + sequence_number = + secured_message_context->handshake_secret.request_handshake_sequence_number; + } else { + libspdm_copy_mem(key, sizeof(key), + secured_message_context->handshake_secret + .response_handshake_encryption_key, + secured_message_context->aead_key_size); + libspdm_copy_mem(salt, sizeof(salt), + secured_message_context->handshake_secret + .response_handshake_salt, + secured_message_context->aead_iv_size); + sequence_number = + secured_message_context->handshake_secret.response_handshake_sequence_number; + } + break; + case LIBSPDM_SESSION_STATE_ESTABLISHED: + if (is_requester) { + libspdm_copy_mem(key, sizeof(key), + secured_message_context->application_secret + .request_data_encryption_key, + secured_message_context->aead_key_size); + libspdm_copy_mem(salt, sizeof(salt), + secured_message_context->application_secret + .request_data_salt, + secured_message_context->aead_iv_size); + sequence_number = + secured_message_context->application_secret.request_data_sequence_number; + } else { + libspdm_copy_mem(key, sizeof(key), + secured_message_context->application_secret + .response_data_encryption_key, + secured_message_context->aead_key_size); + libspdm_copy_mem(salt, sizeof(salt), + secured_message_context->application_secret + .response_data_salt, + secured_message_context->aead_iv_size); + sequence_number = + secured_message_context->application_secret.response_data_sequence_number; + } + break; + default: + LIBSPDM_ASSERT(false); + return LIBSPDM_STATUS_INVALID_STATE_LOCAL; + } + + if (sequence_number == (uint64_t)-1) { + libspdm_secured_message_set_last_spdm_error_struct( + spdm_secured_message_context, &spdm_error); + return LIBSPDM_STATUS_SEQUENCE_NUMBER_OVERFLOW; + } + + *(uint64_t *)salt = *(uint64_t *)salt ^ sequence_number; + + sequence_num_in_header = 0; + sequence_num_in_header_size = + spdm_secured_message_callbacks->get_sequence_number( + sequence_number, (uint8_t *)&sequence_num_in_header); + LIBSPDM_ASSERT(sequence_num_in_header_size <= sizeof(sequence_num_in_header)); + + sequence_number++; + if (session_state == LIBSPDM_SESSION_STATE_HANDSHAKING) { + if (is_requester) { + secured_message_context->handshake_secret.request_handshake_sequence_number = + sequence_number; + } else { + secured_message_context->handshake_secret.response_handshake_sequence_number = + sequence_number; + } + } + else { + if (is_requester) { + secured_message_context->application_secret.request_data_sequence_number = + sequence_number; + } else { + secured_message_context->application_secret.response_data_sequence_number = + sequence_number; + } + } + + record_header_size = sizeof(spdm_secured_message_a_data_header1_t) + + sequence_num_in_header_size + + sizeof(spdm_secured_message_a_data_header2_t); + + switch (session_type) { + case LIBSPDM_SESSION_TYPE_ENC_MAC: + if (secured_message_size < record_header_size + aead_tag_size) { + libspdm_secured_message_set_last_spdm_error_struct( + spdm_secured_message_context, &spdm_error); + return LIBSPDM_STATUS_INVALID_MSG_SIZE; + } + record_header1 = secured_message; + record_header2 = + (void *)((uint8_t *)record_header1 + + sizeof(spdm_secured_message_a_data_header1_t) + + sequence_num_in_header_size); + if (record_header1->session_id != session_id) { + libspdm_secured_message_set_last_spdm_error_struct( + spdm_secured_message_context, &spdm_error); + return LIBSPDM_STATUS_INVALID_MSG_FIELD; + } + if (libspdm_const_compare_mem(record_header1 + 1, &sequence_num_in_header, + sequence_num_in_header_size) != 0) { + libspdm_secured_message_set_last_spdm_error_struct( + spdm_secured_message_context, &spdm_error); + return LIBSPDM_STATUS_INVALID_MSG_FIELD; + } + if (record_header2->length > secured_message_size - record_header_size) { + libspdm_secured_message_set_last_spdm_error_struct( + spdm_secured_message_context, &spdm_error); + return LIBSPDM_STATUS_INVALID_MSG_SIZE; + } + if (record_header2->length < aead_tag_size) { + libspdm_secured_message_set_last_spdm_error_struct( + spdm_secured_message_context, &spdm_error); + return LIBSPDM_STATUS_INVALID_MSG_SIZE; + } + cipher_text_size = (record_header2->length - aead_tag_size); + if (cipher_text_size > *app_message_size) { + return LIBSPDM_STATUS_BUFFER_TOO_SMALL; + } + libspdm_zero_mem(*app_message, *app_message_size); + enc_msg_header = (void *)(record_header2 + 1); + a_data = (const uint8_t *)record_header1; + enc_msg = (const uint8_t *)enc_msg_header; + dec_msg = (uint8_t *)*app_message; + enc_msg_header = (void *)dec_msg; + tag = (const uint8_t *)record_header1 + record_header_size + cipher_text_size; + result = libspdm_aead_decryption( + secured_message_context->secured_message_version, + secured_message_context->aead_cipher_suite, key, + aead_key_size, salt, aead_iv_size, a_data, + record_header_size, enc_msg, cipher_text_size, tag, + aead_tag_size, dec_msg, &cipher_text_size); + if (!result) { + /* Backup keys are valid, fail and alert rollback and retry is possible. */ + if ((is_requester && secured_message_context->requester_backup_valid) || + ((!is_requester) && secured_message_context->responder_backup_valid)) { + return LIBSPDM_STATUS_SESSION_TRY_DISCARD_KEY_UPDATE; + } + + libspdm_secured_message_set_last_spdm_error_struct( + spdm_secured_message_context, &spdm_error); + return LIBSPDM_STATUS_CRYPTO_ERROR; + } + plain_text_size = enc_msg_header->application_data_length; + if (plain_text_size > cipher_text_size) { + libspdm_secured_message_set_last_spdm_error_struct( + spdm_secured_message_context, &spdm_error); + return LIBSPDM_STATUS_INVALID_MSG_SIZE; + } + + LIBSPDM_ASSERT(*app_message_size >= plain_text_size); + *app_message = enc_msg_header + 1; + *app_message_size = plain_text_size; + break; + + case LIBSPDM_SESSION_TYPE_MAC_ONLY: + if (secured_message_size < record_header_size + aead_tag_size) { + libspdm_secured_message_set_last_spdm_error_struct( + spdm_secured_message_context, &spdm_error); + return LIBSPDM_STATUS_INVALID_MSG_SIZE; + } + record_header1 = secured_message; + record_header2 = + (void *)((uint8_t *)record_header1 + + sizeof(spdm_secured_message_a_data_header1_t) + + sequence_num_in_header_size); + if (record_header1->session_id != session_id) { + libspdm_secured_message_set_last_spdm_error_struct( + spdm_secured_message_context, &spdm_error); + return LIBSPDM_STATUS_INVALID_MSG_FIELD; + } + if (libspdm_const_compare_mem(record_header1 + 1, &sequence_num_in_header, + sequence_num_in_header_size) != 0) { + libspdm_secured_message_set_last_spdm_error_struct( + spdm_secured_message_context, &spdm_error); + return LIBSPDM_STATUS_INVALID_MSG_FIELD; + } + if (record_header2->length > + secured_message_size - record_header_size) { + libspdm_secured_message_set_last_spdm_error_struct( + spdm_secured_message_context, &spdm_error); + return LIBSPDM_STATUS_INVALID_MSG_SIZE; + } + if (record_header2->length < aead_tag_size) { + libspdm_secured_message_set_last_spdm_error_struct( + spdm_secured_message_context, &spdm_error); + return LIBSPDM_STATUS_INVALID_MSG_SIZE; + } + a_data = (uint8_t *)record_header1; + tag = (uint8_t *)record_header1 + record_header_size + + record_header2->length - aead_tag_size; + result = libspdm_aead_decryption( + secured_message_context->secured_message_version, + secured_message_context->aead_cipher_suite, key, + aead_key_size, salt, aead_iv_size, a_data, + record_header_size + record_header2->length - + aead_tag_size, + NULL, 0, tag, aead_tag_size, NULL, NULL); + if (!result) { + /* Backup keys are valid, fail and alert rollback and retry is possible. */ + if ((is_requester && secured_message_context->requester_backup_valid) || + ((!is_requester) && secured_message_context->responder_backup_valid)) { + return LIBSPDM_STATUS_SESSION_TRY_DISCARD_KEY_UPDATE; + } + + libspdm_secured_message_set_last_spdm_error_struct( + spdm_secured_message_context, &spdm_error); + return LIBSPDM_STATUS_CRYPTO_ERROR; + } + + plain_text_size = record_header2->length - aead_tag_size; + LIBSPDM_ASSERT(*app_message_size >= plain_text_size); + *app_message = record_header2 + 1; + *app_message_size = plain_text_size; + break; + + default: + LIBSPDM_ASSERT(false); + return LIBSPDM_STATUS_UNSUPPORTED_CAP; + } + + return LIBSPDM_STATUS_SUCCESS; +} diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/libraries/libspdm/2.3.1/library/spdm_secured_message_lib/libspdm_secmes_key_exchange.c nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/libraries/libspdm/2.3.1/library/spdm_secured_message_lib/libspdm_secmes_key_exchange.c --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/libraries/libspdm/2.3.1/library/spdm_secured_message_lib/libspdm_secmes_key_exchange.c 1970-01-01 00:00:00.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/libraries/libspdm/2.3.1/library/spdm_secured_message_lib/libspdm_secmes_key_exchange.c 2024-03-05 22:14:18.000000000 +0000 @@ -0,0 +1,108 @@ +/** + * Copyright Notice: + * Copyright 2021-2022 DMTF. All rights reserved. + * License: BSD 3-Clause License. For full text see link: https://github.com/DMTF/libspdm/blob/main/LICENSE.md + **/ + +#include "internal/libspdm_secured_message_lib.h" + +/** + * Allocates and Initializes one Diffie-Hellman Ephemeral (DHE) context for subsequent use, + * based upon negotiated DHE algorithm. + * + * @param dhe_named_group SPDM dhe_named_group + * @param is_initiator if the caller is initiator. + * true: initiator + * false: not an initiator + * + * @return Pointer to the Diffie-Hellman context that has been initialized. + **/ +void *libspdm_secured_message_dhe_new(spdm_version_number_t spdm_version, + uint16_t dhe_named_group, bool is_initiator) +{ + return libspdm_dhe_new(spdm_version, dhe_named_group, is_initiator); +} + +/** + * Release the specified DHE context, + * based upon negotiated DHE algorithm. + * + * @param dhe_named_group SPDM dhe_named_group + * @param dhe_context Pointer to the DHE context to be released. + **/ +void libspdm_secured_message_dhe_free(uint16_t dhe_named_group, void *dhe_context) +{ + libspdm_dhe_free(dhe_named_group, dhe_context); +} + +/** + * Generates DHE public key, + * based upon negotiated DHE algorithm. + * + * This function generates random secret exponent, and computes the public key, which is + * returned via parameter public_key and public_key_size. DH context is updated accordingly. + * If the public_key buffer is too small to hold the public key, false is returned and + * public_key_size is set to the required buffer size to obtain the public key. + * + * @param dhe_named_group SPDM dhe_named_group + * @param dhe_context Pointer to the DHE context. + * @param public_key Pointer to the buffer to receive generated public key. + * @param public_key_size On input, the size of public_key buffer in bytes. + * On output, the size of data returned in public_key buffer in bytes. + * + * @retval true DHE public key generation succeeded. + * @retval false DHE public key generation failed. + * @retval false public_key_size is not large enough. + **/ +bool libspdm_secured_message_dhe_generate_key(uint16_t dhe_named_group, + void *dhe_context, + uint8_t *public_key, + size_t *public_key_size) +{ + return libspdm_dhe_generate_key(dhe_named_group, dhe_context, public_key, public_key_size); +} + +/** + * Computes exchanged common key, + * based upon negotiated DHE algorithm. + * + * Given peer's public key, this function computes the exchanged common key, based on its own + * context including value of prime modulus and random secret exponent. + * + * @param dhe_named_group SPDM dhe_named_group + * @param dhe_context Pointer to the DHE context. + * @param peer_public_key Pointer to the peer's public key. + * @param peer_public_key_size size of peer's public key in bytes. + * @param key Pointer to the buffer to receive generated key. + * @param spdm_secured_message_context A pointer to the SPDM secured message context. + * + * @retval true DHE exchanged key generation succeeded. + * @retval false DHE exchanged key generation failed. + * @retval false key_size is not large enough. + **/ +bool libspdm_secured_message_dhe_compute_key( + uint16_t dhe_named_group, void *dhe_context, + const uint8_t *peer_public, size_t peer_public_size, + void *spdm_secured_message_context) +{ + libspdm_secured_message_context_t *secured_message_context; + uint8_t final_key[LIBSPDM_MAX_DHE_KEY_SIZE]; + size_t final_key_size; + bool ret; + + secured_message_context = spdm_secured_message_context; + + final_key_size = sizeof(final_key); + ret = libspdm_dhe_compute_key(dhe_named_group, dhe_context, peer_public, + peer_public_size, final_key, + &final_key_size); + if (!ret) { + return ret; + } + libspdm_copy_mem(secured_message_context->master_secret.dhe_secret, + sizeof(secured_message_context->master_secret.dhe_secret), + final_key, final_key_size); + libspdm_zero_mem(final_key, final_key_size); + secured_message_context->dhe_key_size = final_key_size; + return true; +} diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/libraries/libspdm/2.3.1/library/spdm_secured_message_lib/libspdm_secmes_session.c nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/libraries/libspdm/2.3.1/library/spdm_secured_message_lib/libspdm_secmes_session.c --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/libraries/libspdm/2.3.1/library/spdm_secured_message_lib/libspdm_secmes_session.c 1970-01-01 00:00:00.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/libraries/libspdm/2.3.1/library/spdm_secured_message_lib/libspdm_secmes_session.c 2024-03-05 22:14:18.000000000 +0000 @@ -0,0 +1,1113 @@ +/** + * Copyright Notice: + * Copyright 2021-2022 DMTF. All rights reserved. + * License: BSD 3-Clause License. For full text see link: https://github.com/DMTF/libspdm/blob/main/LICENSE.md + **/ + +#include "internal/libspdm_secured_message_lib.h" + +/** + * This function concatenates binary data, which is used as info in HKDF expand later. + * + * @param label An ascii string label for the libspdm_bin_concat. + * @param label_size The size in bytes of the ASCII string label, not including NULL terminator. + * @param context A pre-defined hash value as the context for the libspdm_bin_concat. + * @param length 16 bits length for the libspdm_bin_concat. + * @param hash_size The size in bytes of the context hash. + * @param out_bin The buffer to store the output binary. + * @param out_bin_size The size in bytes for the out_bin. + **/ +void libspdm_bin_concat(spdm_version_number_t spdm_version, + const char *label, size_t label_size, + const uint8_t *context, uint16_t length, + size_t hash_size, uint8_t *out_bin, + size_t *out_bin_size) +{ + size_t final_size; + + /* The correct version characters (1.1 or 1.2) will replace the x.x. */ + #define LIBSPDM_BIN_CONCAT_LABEL "spdmx.x " + + final_size = sizeof(uint16_t) + sizeof(LIBSPDM_BIN_CONCAT_LABEL) - 1 + label_size; + if (context != NULL) { + final_size += hash_size; + } + + LIBSPDM_ASSERT(*out_bin_size >= final_size); + + *out_bin_size = final_size; + + libspdm_copy_mem(out_bin, *out_bin_size, &length, sizeof(uint16_t)); + libspdm_copy_mem(out_bin + sizeof(uint16_t), *out_bin_size - sizeof(uint16_t), + LIBSPDM_BIN_CONCAT_LABEL, sizeof(LIBSPDM_BIN_CONCAT_LABEL) - 1); + + /* Patch the version. */ + out_bin[6] = (char)('0' + ((spdm_version >> 12) & 0xF)); + out_bin[8] = (char)('0' + ((spdm_version >> 8) & 0xF)); + libspdm_copy_mem(out_bin + sizeof(uint16_t) + sizeof(LIBSPDM_BIN_CONCAT_LABEL) - 1, + *out_bin_size - (sizeof(uint16_t) + sizeof(LIBSPDM_BIN_CONCAT_LABEL) - 1), + label, label_size); + + if (context != NULL) { + libspdm_copy_mem(out_bin + sizeof(uint16_t) + sizeof(LIBSPDM_BIN_CONCAT_LABEL) - + 1 + label_size, + *out_bin_size - (sizeof(uint16_t) + sizeof(LIBSPDM_BIN_CONCAT_LABEL) - + 1 + label_size), context, hash_size); + } + + #undef LIBSPDM_BIN_CONCAT_LABEL +} + +/** + * This function generates SPDM AEAD key and IV for a session. + * + * @param spdm_secured_message_context A pointer to the SPDM secured message context. + * @param major_secret The major secret. + * @param key The buffer to store the AEAD key. + * @param iv The buffer to store the AEAD IV. + * + * @retval RETURN_SUCCESS SPDM AEAD key and IV for a session is generated. + **/ +bool libspdm_generate_aead_key_and_iv( + libspdm_secured_message_context_t *secured_message_context, + const uint8_t *major_secret, uint8_t *key, uint8_t *iv) +{ + bool status; + size_t hash_size; + size_t key_length; + size_t iv_length; + uint8_t bin_str5[128]; + size_t bin_str5_size; + uint8_t bin_str6[128]; + size_t bin_str6_size; + + hash_size = secured_message_context->hash_size; + key_length = secured_message_context->aead_key_size; + iv_length = secured_message_context->aead_iv_size; + + bin_str5_size = sizeof(bin_str5); + libspdm_bin_concat(secured_message_context->version, + SPDM_BIN_STR_5_LABEL, sizeof(SPDM_BIN_STR_5_LABEL) - 1, + NULL, (uint16_t)key_length, hash_size, bin_str5, + &bin_str5_size); + + LIBSPDM_DEBUG((LIBSPDM_DEBUG_INFO, "bin_str5 (0x%x):\n", bin_str5_size)); + LIBSPDM_INTERNAL_DUMP_HEX(bin_str5, bin_str5_size); + status = libspdm_hkdf_expand(secured_message_context->base_hash_algo, + major_secret, hash_size, bin_str5, + bin_str5_size, key, key_length); + if (!status) { + return false; + } + LIBSPDM_DEBUG((LIBSPDM_DEBUG_INFO, "key (0x%x) - ", key_length)); + LIBSPDM_INTERNAL_DUMP_DATA(key, key_length); + LIBSPDM_DEBUG((LIBSPDM_DEBUG_INFO, "\n")); + + bin_str6_size = sizeof(bin_str6); + libspdm_bin_concat(secured_message_context->version, + SPDM_BIN_STR_6_LABEL, sizeof(SPDM_BIN_STR_6_LABEL) - 1, + NULL, (uint16_t)iv_length, hash_size, bin_str6, + &bin_str6_size); + + LIBSPDM_DEBUG((LIBSPDM_DEBUG_INFO, "bin_str6 (0x%x):\n", bin_str6_size)); + LIBSPDM_INTERNAL_DUMP_HEX(bin_str6, bin_str6_size); + status = libspdm_hkdf_expand(secured_message_context->base_hash_algo, + major_secret, hash_size, bin_str6, + bin_str6_size, iv, iv_length); + if (!status) { + return false; + } + LIBSPDM_DEBUG((LIBSPDM_DEBUG_INFO, "iv (0x%x) - ", iv_length)); + LIBSPDM_INTERNAL_DUMP_DATA(iv, iv_length); + LIBSPDM_DEBUG((LIBSPDM_DEBUG_INFO, "\n")); + + return true; +} + +/** + * This function generates SPDM finished_key for a session. + * + * @param spdm_secured_message_context A pointer to the SPDM secured message context. + * @param handshake_secret The handshake secret. + * @param finished_key The buffer to store the finished key. + * + * @retval RETURN_SUCCESS SPDM finished_key for a session is generated. + **/ +bool libspdm_generate_finished_key( + libspdm_secured_message_context_t *secured_message_context, + const uint8_t *handshake_secret, uint8_t *finished_key) +{ + bool status; + size_t hash_size; + uint8_t bin_str7[128]; + size_t bin_str7_size; + + hash_size = secured_message_context->hash_size; + + bin_str7_size = sizeof(bin_str7); + libspdm_bin_concat(secured_message_context->version, + SPDM_BIN_STR_7_LABEL, sizeof(SPDM_BIN_STR_7_LABEL) - 1, + NULL, (uint16_t)hash_size, hash_size, bin_str7, + &bin_str7_size); + + LIBSPDM_DEBUG((LIBSPDM_DEBUG_INFO, "bin_str7 (0x%x):\n", bin_str7_size)); + LIBSPDM_INTERNAL_DUMP_HEX(bin_str7, bin_str7_size); + status = libspdm_hkdf_expand(secured_message_context->base_hash_algo, + handshake_secret, hash_size, bin_str7, + bin_str7_size, finished_key, hash_size); + if (!status) { + return false; + } + LIBSPDM_DEBUG((LIBSPDM_DEBUG_INFO, "finished_key (0x%x) - ", hash_size)); + LIBSPDM_INTERNAL_DUMP_DATA(finished_key, hash_size); + LIBSPDM_DEBUG((LIBSPDM_DEBUG_INFO, "\n")); + + return true; +} + +/** + * This function generates SPDM HandshakeKey for a session. + * + * @param spdm_secured_message_context A pointer to the SPDM secured message context. + * @param th1_hash_data th1 hash + * + * @retval RETURN_SUCCESS SPDM HandshakeKey for a session is generated. + **/ +bool libspdm_generate_session_handshake_key(void *spdm_secured_message_context, + const uint8_t *th1_hash_data) +{ + bool status; + size_t hash_size; + uint8_t bin_str0[128]; + size_t bin_str0_size; + uint8_t bin_str1[128]; + size_t bin_str1_size; + uint8_t bin_str2[128]; + size_t bin_str2_size; + libspdm_secured_message_context_t *secured_message_context; + uint8_t zero_filled_buffer[LIBSPDM_MAX_HASH_SIZE]; + + secured_message_context = spdm_secured_message_context; + + hash_size = secured_message_context->hash_size; + + bin_str0_size = sizeof(bin_str0); + libspdm_bin_concat(secured_message_context->version, + SPDM_BIN_STR_0_LABEL, sizeof(SPDM_BIN_STR_0_LABEL) - 1, + NULL, (uint16_t)hash_size, hash_size, bin_str0, + &bin_str0_size); + + LIBSPDM_DEBUG((LIBSPDM_DEBUG_INFO, "bin_str0 (0x%x):\n", bin_str0_size)); + LIBSPDM_INTERNAL_DUMP_HEX(bin_str0, bin_str0_size); + + if (!(secured_message_context->use_psk)) { + LIBSPDM_DEBUG((LIBSPDM_DEBUG_INFO, "[DHE Secret]: ")); + LIBSPDM_INTERNAL_DUMP_HEX_STR( + secured_message_context->master_secret.dhe_secret, + secured_message_context->dhe_key_size); + LIBSPDM_DEBUG((LIBSPDM_DEBUG_INFO, "\n")); + libspdm_zero_mem(zero_filled_buffer, sizeof(zero_filled_buffer)); + status = libspdm_hkdf_extract( + secured_message_context->base_hash_algo, + secured_message_context->master_secret.dhe_secret, + secured_message_context->dhe_key_size, + zero_filled_buffer, hash_size, + secured_message_context->master_secret.handshake_secret, hash_size); + if (!status) { + return false; + } + LIBSPDM_DEBUG((LIBSPDM_DEBUG_INFO, "handshake_secret (0x%x) - ", hash_size)); + LIBSPDM_INTERNAL_DUMP_DATA( + secured_message_context->master_secret.handshake_secret, + hash_size); + LIBSPDM_DEBUG((LIBSPDM_DEBUG_INFO, "\n")); + } + + bin_str1_size = sizeof(bin_str1); + libspdm_bin_concat(secured_message_context->version, + SPDM_BIN_STR_1_LABEL, sizeof(SPDM_BIN_STR_1_LABEL) - 1, + th1_hash_data, (uint16_t)hash_size, hash_size, + bin_str1, &bin_str1_size); + + LIBSPDM_DEBUG((LIBSPDM_DEBUG_INFO, "bin_str1 (0x%x):\n", bin_str1_size)); + LIBSPDM_INTERNAL_DUMP_HEX(bin_str1, bin_str1_size); + + #if LIBSPDM_ENABLE_CAPABILITY_PSK_EX_CAP + if (secured_message_context->use_psk) { + status = libspdm_psk_handshake_secret_hkdf_expand( + secured_message_context->version, + secured_message_context->base_hash_algo, + secured_message_context->psk_hint, + secured_message_context->psk_hint_size, bin_str1, + bin_str1_size, + secured_message_context->handshake_secret.request_handshake_secret, + hash_size); + + if (!status) { + return false; + } + } + #endif /* LIBSPDM_ENABLE_CAPABILITY_PSK_EX_CAP */ + if (!(secured_message_context->use_psk)) { + status = libspdm_hkdf_expand( + secured_message_context->base_hash_algo, + secured_message_context->master_secret.handshake_secret, + hash_size, bin_str1, bin_str1_size, + secured_message_context->handshake_secret.request_handshake_secret, + hash_size); + + if (!status) { + return false; + } + } + + LIBSPDM_DEBUG((LIBSPDM_DEBUG_INFO, "request_handshake_secret (0x%x) - ", hash_size)); + LIBSPDM_INTERNAL_DUMP_DATA(secured_message_context->handshake_secret + .request_handshake_secret, + hash_size); + LIBSPDM_DEBUG((LIBSPDM_DEBUG_INFO, "\n")); + bin_str2_size = sizeof(bin_str2); + libspdm_bin_concat(secured_message_context->version, + SPDM_BIN_STR_2_LABEL, sizeof(SPDM_BIN_STR_2_LABEL) - 1, + th1_hash_data, (uint16_t)hash_size, hash_size, + bin_str2, &bin_str2_size); + + LIBSPDM_DEBUG((LIBSPDM_DEBUG_INFO, "bin_str2 (0x%x):\n", bin_str2_size)); + LIBSPDM_INTERNAL_DUMP_HEX(bin_str2, bin_str2_size); + + #if LIBSPDM_ENABLE_CAPABILITY_PSK_EX_CAP + if (secured_message_context->use_psk) { + status = libspdm_psk_handshake_secret_hkdf_expand( + secured_message_context->version, + secured_message_context->base_hash_algo, + secured_message_context->psk_hint, + secured_message_context->psk_hint_size, bin_str2, + bin_str2_size, + secured_message_context->handshake_secret.response_handshake_secret, + hash_size); + + if (!status) { + return false; + } + } + #endif /* LIBSPDM_ENABLE_CAPABILITY_PSK_EX_CAP */ + if (!(secured_message_context->use_psk)) { + status = libspdm_hkdf_expand( + secured_message_context->base_hash_algo, + secured_message_context->master_secret.handshake_secret, + hash_size, bin_str2, bin_str2_size, + secured_message_context->handshake_secret.response_handshake_secret, + hash_size); + + if (!status) { + return false; + } + } + + LIBSPDM_DEBUG((LIBSPDM_DEBUG_INFO, "response_handshake_secret (0x%x) - ", hash_size)); + LIBSPDM_INTERNAL_DUMP_DATA(secured_message_context->handshake_secret.response_handshake_secret, + hash_size); + LIBSPDM_DEBUG((LIBSPDM_DEBUG_INFO, "\n")); + + status = libspdm_generate_finished_key( + secured_message_context, + secured_message_context->handshake_secret + .request_handshake_secret, + secured_message_context->handshake_secret.request_finished_key); + if (!status) { + return status; + } + + status = libspdm_generate_finished_key( + secured_message_context, + secured_message_context->handshake_secret.response_handshake_secret, + secured_message_context->handshake_secret.response_finished_key); + if (!status) { + return status; + } + + status = libspdm_generate_aead_key_and_iv(secured_message_context, + secured_message_context->handshake_secret + .request_handshake_secret, + secured_message_context->handshake_secret + .request_handshake_encryption_key, + secured_message_context->handshake_secret + .request_handshake_salt); + if (!status) { + return status; + } + secured_message_context->handshake_secret.request_handshake_sequence_number = 0; + + status = libspdm_generate_aead_key_and_iv( + secured_message_context, + secured_message_context->handshake_secret.response_handshake_secret, + secured_message_context->handshake_secret.response_handshake_encryption_key, + secured_message_context->handshake_secret.response_handshake_salt); + if (!status) { + return status; + } + + secured_message_context->handshake_secret.response_handshake_sequence_number = 0; + libspdm_zero_mem(secured_message_context->master_secret.dhe_secret, LIBSPDM_MAX_DHE_KEY_SIZE); + + return true; +} + +/** + * This function generates SPDM DataKey for a session. + * + * @param spdm_secured_message_context A pointer to the SPDM secured message context. + * @param th2_hash_data th2 hash + * + * @retval RETURN_SUCCESS SPDM DataKey for a session is generated. + **/ +bool libspdm_generate_session_data_key(void *spdm_secured_message_context, + const uint8_t *th2_hash_data) +{ + bool status; + size_t hash_size; + uint8_t salt1[64]; + uint8_t bin_str0[128]; + size_t bin_str0_size; + uint8_t bin_str3[128]; + size_t bin_str3_size; + uint8_t bin_str4[128]; + size_t bin_str4_size; + uint8_t bin_str8[128]; + size_t bin_str8_size; + libspdm_secured_message_context_t *secured_message_context; + uint8_t zero_filled_buffer[LIBSPDM_MAX_HASH_SIZE]; + + secured_message_context = spdm_secured_message_context; + + hash_size = secured_message_context->hash_size; + + if (!(secured_message_context->use_psk)) { + bin_str0_size = sizeof(bin_str0); + libspdm_bin_concat(secured_message_context->version, + SPDM_BIN_STR_0_LABEL, + sizeof(SPDM_BIN_STR_0_LABEL) - 1, NULL, + (uint16_t)hash_size, hash_size, bin_str0, + &bin_str0_size); + + status = libspdm_hkdf_expand( + secured_message_context->base_hash_algo, + secured_message_context->master_secret.handshake_secret, + hash_size, bin_str0, bin_str0_size, salt1, hash_size); + if (!status) { + return false; + } + LIBSPDM_DEBUG((LIBSPDM_DEBUG_INFO, "salt1 (0x%x) - ", hash_size)); + LIBSPDM_INTERNAL_DUMP_DATA(salt1, hash_size); + LIBSPDM_DEBUG((LIBSPDM_DEBUG_INFO, "\n")); + + libspdm_zero_mem(zero_filled_buffer, sizeof(zero_filled_buffer)); + status = libspdm_hkdf_extract( + secured_message_context->base_hash_algo, + zero_filled_buffer, hash_size, salt1, hash_size, + secured_message_context->master_secret.master_secret, hash_size); + if (!status) { + return false; + } + LIBSPDM_DEBUG((LIBSPDM_DEBUG_INFO, "master_secret (0x%x) - ", hash_size)); + LIBSPDM_INTERNAL_DUMP_DATA( + secured_message_context->master_secret.master_secret, + hash_size); + LIBSPDM_DEBUG((LIBSPDM_DEBUG_INFO, "\n")); + } + + bin_str3_size = sizeof(bin_str3); + libspdm_bin_concat(secured_message_context->version, + SPDM_BIN_STR_3_LABEL, sizeof(SPDM_BIN_STR_3_LABEL) - 1, + th2_hash_data, (uint16_t)hash_size, hash_size, + bin_str3, &bin_str3_size); + + LIBSPDM_DEBUG((LIBSPDM_DEBUG_INFO, "bin_str3 (0x%x):\n", bin_str3_size)); + LIBSPDM_INTERNAL_DUMP_HEX(bin_str3, bin_str3_size); + + #if LIBSPDM_ENABLE_CAPABILITY_PSK_EX_CAP + if (secured_message_context->use_psk) { + status = libspdm_psk_master_secret_hkdf_expand( + secured_message_context->version, + secured_message_context->base_hash_algo, + secured_message_context->psk_hint, + secured_message_context->psk_hint_size, bin_str3, + bin_str3_size, + secured_message_context->application_secret.request_data_secret, + hash_size); + + if (!status) { + return false; + } + } + #endif /* LIBSPDM_ENABLE_CAPABILITY_PSK_EX_CAP */ + if (!(secured_message_context->use_psk)) { + status = libspdm_hkdf_expand( + secured_message_context->base_hash_algo, + secured_message_context->master_secret.master_secret, + hash_size, bin_str3, bin_str3_size, + secured_message_context->application_secret.request_data_secret, + hash_size); + + if (!status) { + return false; + } + } + + LIBSPDM_DEBUG((LIBSPDM_DEBUG_INFO, "request_data_secret (0x%x) - ", hash_size)); + LIBSPDM_INTERNAL_DUMP_DATA( + secured_message_context->application_secret.request_data_secret, + hash_size); + LIBSPDM_DEBUG((LIBSPDM_DEBUG_INFO, "\n")); + bin_str4_size = sizeof(bin_str4); + libspdm_bin_concat(secured_message_context->version, + SPDM_BIN_STR_4_LABEL, sizeof(SPDM_BIN_STR_4_LABEL) - 1, + th2_hash_data, (uint16_t)hash_size, hash_size, + bin_str4, &bin_str4_size); + + LIBSPDM_DEBUG((LIBSPDM_DEBUG_INFO, "bin_str4 (0x%x):\n", bin_str4_size)); + LIBSPDM_INTERNAL_DUMP_HEX(bin_str4, bin_str4_size); + + #if LIBSPDM_ENABLE_CAPABILITY_PSK_EX_CAP + if (secured_message_context->use_psk) { + status = libspdm_psk_master_secret_hkdf_expand( + secured_message_context->version, + secured_message_context->base_hash_algo, + secured_message_context->psk_hint, + secured_message_context->psk_hint_size, bin_str4, + bin_str4_size, + secured_message_context->application_secret.response_data_secret, + hash_size); + + if (!status) { + return false; + } + } + #endif /* LIBSPDM_ENABLE_CAPABILITY_PSK_EX_CAP */ + if (!(secured_message_context->use_psk)) { + status = libspdm_hkdf_expand( + secured_message_context->base_hash_algo, + secured_message_context->master_secret.master_secret, + hash_size, bin_str4, bin_str4_size, + secured_message_context->application_secret.response_data_secret, + hash_size); + + if (!status) { + return false; + } + } + + LIBSPDM_DEBUG((LIBSPDM_DEBUG_INFO, "response_data_secret (0x%x) - ", hash_size)); + LIBSPDM_INTERNAL_DUMP_DATA( + secured_message_context->application_secret.response_data_secret, + hash_size); + LIBSPDM_DEBUG((LIBSPDM_DEBUG_INFO, "\n")); + + bin_str8_size = sizeof(bin_str8); + libspdm_bin_concat(secured_message_context->version, + SPDM_BIN_STR_8_LABEL, sizeof(SPDM_BIN_STR_8_LABEL) - 1, + th2_hash_data, (uint16_t)hash_size, hash_size, + bin_str8, &bin_str8_size); + + LIBSPDM_DEBUG((LIBSPDM_DEBUG_INFO, "bin_str8 (0x%x):\n", bin_str8_size)); + LIBSPDM_INTERNAL_DUMP_HEX(bin_str8, bin_str8_size); + + #if LIBSPDM_ENABLE_CAPABILITY_PSK_EX_CAP + if (secured_message_context->use_psk) { + status = libspdm_psk_master_secret_hkdf_expand( + secured_message_context->version, + secured_message_context->base_hash_algo, + secured_message_context->psk_hint, + secured_message_context->psk_hint_size, bin_str8, + bin_str8_size, + secured_message_context->export_master_secret, + hash_size); + + if (!status) { + return false; + } + } + #endif /* LIBSPDM_ENABLE_CAPABILITY_PSK_EX_CAP */ + if (!(secured_message_context->use_psk)) { + status = libspdm_hkdf_expand( + secured_message_context->base_hash_algo, + secured_message_context->master_secret.master_secret, + hash_size, bin_str8, bin_str8_size, + secured_message_context->export_master_secret, + hash_size); + + if (!status) { + return false; + } + } + + LIBSPDM_DEBUG((LIBSPDM_DEBUG_INFO, "export_master_secret (0x%x) - ", hash_size)); + LIBSPDM_INTERNAL_DUMP_DATA( + secured_message_context->export_master_secret, hash_size); + LIBSPDM_DEBUG((LIBSPDM_DEBUG_INFO, "\n")); + + status = libspdm_generate_aead_key_and_iv( + secured_message_context, + secured_message_context->application_secret.request_data_secret, + secured_message_context->application_secret.request_data_encryption_key, + secured_message_context->application_secret.request_data_salt); + if (!status) { + return status; + } + secured_message_context->application_secret.request_data_sequence_number = 0; + + status = libspdm_generate_aead_key_and_iv( + secured_message_context, + secured_message_context->application_secret.response_data_secret, + secured_message_context->application_secret.response_data_encryption_key, + secured_message_context->application_secret.response_data_salt); + if (!status) { + return status; + } + secured_message_context->application_secret.response_data_sequence_number = 0; + + return true; +} + +/** + * This function creates the updates of SPDM DataKey for a session. + * + * @param spdm_secured_message_context A pointer to the SPDM secured message context. + * @param action Indicate of the key update action. + * + * @retval RETURN_SUCCESS SPDM DataKey update is created. + **/ +bool libspdm_create_update_session_data_key(void *spdm_secured_message_context, + libspdm_key_update_action_t action) +{ + bool status; + size_t hash_size; + uint8_t bin_str9[128]; + size_t bin_str9_size; + libspdm_secured_message_context_t *secured_message_context; + + secured_message_context = spdm_secured_message_context; + + hash_size = secured_message_context->hash_size; + + bin_str9_size = sizeof(bin_str9); + libspdm_bin_concat(secured_message_context->version, + SPDM_BIN_STR_9_LABEL, sizeof(SPDM_BIN_STR_9_LABEL) - 1, + NULL, (uint16_t)hash_size, hash_size, bin_str9, + &bin_str9_size); + + LIBSPDM_DEBUG((LIBSPDM_DEBUG_INFO, "bin_str9 (0x%x):\n", bin_str9_size)); + LIBSPDM_INTERNAL_DUMP_HEX(bin_str9, bin_str9_size); + + if (action == LIBSPDM_KEY_UPDATE_ACTION_REQUESTER) { + libspdm_copy_mem(&secured_message_context->application_secret_backup + .request_data_secret, + sizeof(secured_message_context->application_secret_backup + .request_data_secret), + &secured_message_context->application_secret + .request_data_secret, + LIBSPDM_MAX_HASH_SIZE); + libspdm_copy_mem(&secured_message_context->application_secret_backup + .request_data_encryption_key, + sizeof(secured_message_context->application_secret_backup + .request_data_encryption_key), + &secured_message_context->application_secret + .request_data_encryption_key, + LIBSPDM_MAX_AEAD_KEY_SIZE); + libspdm_copy_mem(&secured_message_context->application_secret_backup + .request_data_salt, + sizeof(secured_message_context->application_secret_backup + .request_data_salt), + &secured_message_context->application_secret + .request_data_salt, + LIBSPDM_MAX_AEAD_IV_SIZE); + secured_message_context->application_secret_backup + .request_data_sequence_number = + secured_message_context->application_secret.request_data_sequence_number; + + status = libspdm_hkdf_expand( + secured_message_context->base_hash_algo, + secured_message_context->application_secret.request_data_secret, + hash_size, bin_str9, bin_str9_size, + secured_message_context->application_secret.request_data_secret, + hash_size); + if (!status) { + return false; + } + LIBSPDM_DEBUG((LIBSPDM_DEBUG_INFO, "RequestDataSecretUpdate (0x%x) - ", hash_size)); + LIBSPDM_INTERNAL_DUMP_DATA(secured_message_context->application_secret.request_data_secret, + hash_size); + LIBSPDM_DEBUG((LIBSPDM_DEBUG_INFO, "\n")); + + status = libspdm_generate_aead_key_and_iv( + secured_message_context, + secured_message_context->application_secret.request_data_secret, + secured_message_context->application_secret.request_data_encryption_key, + secured_message_context->application_secret.request_data_salt); + if (!status) { + return status; + } + secured_message_context->application_secret.request_data_sequence_number = 0; + + secured_message_context->requester_backup_valid = true; + } else if (action == LIBSPDM_KEY_UPDATE_ACTION_RESPONDER) { + libspdm_copy_mem(&secured_message_context->application_secret_backup + .response_data_secret, + sizeof(secured_message_context->application_secret_backup + .response_data_secret), + &secured_message_context->application_secret + .response_data_secret, + LIBSPDM_MAX_HASH_SIZE); + libspdm_copy_mem(&secured_message_context->application_secret_backup + .response_data_encryption_key, + sizeof(secured_message_context->application_secret_backup + .response_data_encryption_key), + &secured_message_context->application_secret + .response_data_encryption_key, + LIBSPDM_MAX_AEAD_KEY_SIZE); + libspdm_copy_mem(&secured_message_context->application_secret_backup + .response_data_salt, + sizeof(secured_message_context->application_secret_backup + .response_data_salt), + &secured_message_context->application_secret + .response_data_salt, + LIBSPDM_MAX_AEAD_IV_SIZE); + secured_message_context->application_secret_backup + .response_data_sequence_number = + secured_message_context->application_secret.response_data_sequence_number; + + status = libspdm_hkdf_expand( + secured_message_context->base_hash_algo, + secured_message_context->application_secret.response_data_secret, + hash_size, bin_str9, bin_str9_size, + secured_message_context->application_secret.response_data_secret, + hash_size); + if (!status) { + return false; + } + LIBSPDM_DEBUG((LIBSPDM_DEBUG_INFO, "ResponseDataSecretUpdate (0x%x) - ", + hash_size)); + LIBSPDM_INTERNAL_DUMP_DATA(secured_message_context->application_secret.response_data_secret, + hash_size); + LIBSPDM_DEBUG((LIBSPDM_DEBUG_INFO, "\n")); + + status = libspdm_generate_aead_key_and_iv( + secured_message_context, + secured_message_context->application_secret.response_data_secret, + secured_message_context->application_secret.response_data_encryption_key, + secured_message_context->application_secret.response_data_salt); + if (!status) { + return status; + } + secured_message_context->application_secret.response_data_sequence_number = 0; + + secured_message_context->responder_backup_valid = true; + } else { + return false; + } + + return true; +} + +void libspdm_clear_handshake_secret(void *spdm_secured_message_context) +{ + libspdm_secured_message_context_t *secured_message_context; + + secured_message_context = spdm_secured_message_context; + + libspdm_zero_mem(secured_message_context->master_secret.handshake_secret, + LIBSPDM_MAX_HASH_SIZE); + libspdm_zero_mem(&(secured_message_context->handshake_secret), + sizeof(libspdm_session_info_struct_handshake_secret_t)); + + secured_message_context->requester_backup_valid = false; + secured_message_context->responder_backup_valid = false; +} + +void libspdm_clear_master_secret(void *spdm_secured_message_context) +{ + libspdm_secured_message_context_t *secured_message_context; + + secured_message_context = spdm_secured_message_context; + + libspdm_zero_mem(secured_message_context->master_secret.master_secret, LIBSPDM_MAX_HASH_SIZE); +} + +/** + * This function activates the update of SPDM DataKey for a session. + * + * @param spdm_secured_message_context A pointer to the SPDM secured message context. + * @param action Indicate of the key update action. + * @param use_new_key Indicate if the new key should be used. + * + * @retval RETURN_SUCCESS SPDM DataKey update is activated. + **/ +bool libspdm_activate_update_session_data_key(void *spdm_secured_message_context, + libspdm_key_update_action_t action, + bool use_new_key) +{ + libspdm_secured_message_context_t *secured_message_context; + + secured_message_context = spdm_secured_message_context; + + if (!use_new_key) { + if ((action == LIBSPDM_KEY_UPDATE_ACTION_REQUESTER) && + secured_message_context->requester_backup_valid) { + libspdm_copy_mem(&secured_message_context->application_secret + .request_data_secret, + sizeof(secured_message_context->application_secret + .request_data_secret), + &secured_message_context + ->application_secret_backup + .request_data_secret, + LIBSPDM_MAX_HASH_SIZE); + libspdm_copy_mem(&secured_message_context->application_secret + .request_data_encryption_key, + sizeof(secured_message_context->application_secret + .request_data_encryption_key), + &secured_message_context + ->application_secret_backup + .request_data_encryption_key, + LIBSPDM_MAX_AEAD_KEY_SIZE); + libspdm_copy_mem(&secured_message_context->application_secret + .request_data_salt, + sizeof(secured_message_context->application_secret + .request_data_salt), + &secured_message_context + ->application_secret_backup + .request_data_salt, + LIBSPDM_MAX_AEAD_IV_SIZE); + secured_message_context->application_secret + .request_data_sequence_number = + secured_message_context->application_secret_backup.request_data_sequence_number; + } else if ((action == LIBSPDM_KEY_UPDATE_ACTION_RESPONDER) && + secured_message_context->responder_backup_valid) { + libspdm_copy_mem(&secured_message_context->application_secret + .response_data_secret, + sizeof(secured_message_context->application_secret + .response_data_secret), + &secured_message_context + ->application_secret_backup + .response_data_secret, + LIBSPDM_MAX_HASH_SIZE); + libspdm_copy_mem(&secured_message_context->application_secret + .response_data_encryption_key, + sizeof(secured_message_context->application_secret + .response_data_encryption_key), + &secured_message_context + ->application_secret_backup + .response_data_encryption_key, + LIBSPDM_MAX_AEAD_KEY_SIZE); + libspdm_copy_mem(&secured_message_context->application_secret + .response_data_salt, + sizeof(secured_message_context->application_secret + .response_data_salt), + &secured_message_context + ->application_secret_backup + .response_data_salt, + LIBSPDM_MAX_AEAD_IV_SIZE); + secured_message_context->application_secret.response_data_sequence_number = + secured_message_context->application_secret_backup.response_data_sequence_number; + } + } + + if (action == LIBSPDM_KEY_UPDATE_ACTION_REQUESTER) { + libspdm_zero_mem(&secured_message_context->application_secret_backup.request_data_secret, + LIBSPDM_MAX_HASH_SIZE); + libspdm_zero_mem(&secured_message_context->application_secret_backup + .request_data_encryption_key, + LIBSPDM_MAX_AEAD_KEY_SIZE); + libspdm_zero_mem(&secured_message_context->application_secret_backup.request_data_salt, + LIBSPDM_MAX_AEAD_IV_SIZE); + secured_message_context->application_secret_backup.request_data_sequence_number = 0; + secured_message_context->requester_backup_valid = false; + } else if (action == LIBSPDM_KEY_UPDATE_ACTION_RESPONDER) { + libspdm_zero_mem(&secured_message_context->application_secret_backup.response_data_secret, + LIBSPDM_MAX_HASH_SIZE); + libspdm_zero_mem(&secured_message_context->application_secret_backup + .response_data_encryption_key, + LIBSPDM_MAX_AEAD_KEY_SIZE); + libspdm_zero_mem(&secured_message_context->application_secret_backup.response_data_salt, + LIBSPDM_MAX_AEAD_IV_SIZE); + secured_message_context->application_secret_backup.response_data_sequence_number = 0; + secured_message_context->responder_backup_valid = false; + } + + return true; +} + +/** + * Allocates and initializes one HMAC context for subsequent use, with request_finished_key. + * + * @param spdm_secured_message_context A pointer to the SPDM secured message context. + * + * @return Pointer to the HMAC context that has been initialized. + **/ +void *libspdm_hmac_new_with_request_finished_key(void *spdm_secured_message_context) +{ + libspdm_secured_message_context_t *secured_message_context; + + secured_message_context = spdm_secured_message_context; + return libspdm_hmac_new(secured_message_context->base_hash_algo); +} + +/** + * Release the specified HMAC context, with request_finished_key. + * + * @param spdm_secured_message_context A pointer to the SPDM secured message context. + * @param hmac_ctx Pointer to the HMAC context to be released. + **/ +void libspdm_hmac_free_with_request_finished_key( + void *spdm_secured_message_context, void *hmac_ctx) +{ + libspdm_secured_message_context_t *secured_message_context; + + secured_message_context = spdm_secured_message_context; + libspdm_hmac_free(secured_message_context->base_hash_algo, hmac_ctx); +} + +/** + * Set request_finished_key for subsequent use. It must be done before any + * calling to hmac_update(). + * + * @param spdm_secured_message_context A pointer to the SPDM secured message context. + * @param hmac_ctx Pointer to HMAC context. + * + * @retval true The key is set successfully. + * @retval false The key is set unsuccessfully. + **/ +bool libspdm_hmac_init_with_request_finished_key( + void *spdm_secured_message_context, void *hmac_ctx) +{ + libspdm_secured_message_context_t *secured_message_context; + + secured_message_context = spdm_secured_message_context; + return libspdm_hmac_init( + secured_message_context->base_hash_algo, hmac_ctx, + secured_message_context->handshake_secret.request_finished_key, + secured_message_context->hash_size); +} + +/** + * Makes a copy of an existing HMAC context, with request_finished_key. + * + * @param spdm_secured_message_context A pointer to the SPDM secured message context. + * @param hmac_ctx Pointer to HMAC context being copied. + * @param new_hmac_ctx Pointer to new HMAC context. + * + * @retval true HMAC context copy succeeded. + * @retval false HMAC context copy failed. + **/ +bool libspdm_hmac_duplicate_with_request_finished_key( + void *spdm_secured_message_context, + const void *hmac_ctx, void *new_hmac_ctx) +{ + libspdm_secured_message_context_t *secured_message_context; + + secured_message_context = spdm_secured_message_context; + return libspdm_hmac_duplicate(secured_message_context->base_hash_algo, hmac_ctx, new_hmac_ctx); +} + +/** + * Digests the input data and updates HMAC context, with request_finished_key. + * + * @param spdm_secured_message_context A pointer to the SPDM secured message context. + * @param hmac_ctx Pointer to HMAC context being copied. + * @param data Pointer to the buffer containing the data to be digested. + * @param data_size size of data buffer in bytes. + * + * @retval true HMAC data digest succeeded. + * @retval false HMAC data digest failed. + **/ +bool libspdm_hmac_update_with_request_finished_key( + void *spdm_secured_message_context, + void *hmac_ctx, const void *data, + size_t data_size) +{ + libspdm_secured_message_context_t *secured_message_context; + + secured_message_context = spdm_secured_message_context; + return libspdm_hmac_update(secured_message_context->base_hash_algo, hmac_ctx, data, data_size); +} + +/** + * Completes computation of the HMAC digest value, with request_finished_key. + * + * @param spdm_secured_message_context A pointer to the SPDM secured message context. + * @param hmac_ctx Pointer to HMAC context being copied. + * @param hmac_value Pointer to a buffer that receives the HMAC digest value + * + * @retval true HMAC data digest succeeded. + * @retval false HMAC data digest failed. + **/ +bool libspdm_hmac_final_with_request_finished_key( + void *spdm_secured_message_context, + void *hmac_ctx, uint8_t *hmac_value) +{ + libspdm_secured_message_context_t *secured_message_context; + + secured_message_context = spdm_secured_message_context; + return libspdm_hmac_final(secured_message_context->base_hash_algo, hmac_ctx, hmac_value); +} + +/** + * Computes the HMAC of a input data buffer, with request_finished_key. + * + * @param spdm_secured_message_context A pointer to the SPDM secured message context. + * @param data Pointer to the buffer containing the data to be HMACed. + * @param data_size size of data buffer in bytes. + * @param hash_value Pointer to a buffer that receives the HMAC value. + * + * @retval true HMAC computation succeeded. + * @retval false HMAC computation failed. + **/ +bool libspdm_hmac_all_with_request_finished_key(void *spdm_secured_message_context, + const void *data, size_t data_size, + uint8_t *hmac_value) +{ + libspdm_secured_message_context_t *secured_message_context; + + secured_message_context = spdm_secured_message_context; + return libspdm_hmac_all( + secured_message_context->base_hash_algo, data, data_size, + secured_message_context->handshake_secret.request_finished_key, + secured_message_context->hash_size, hmac_value); +} + +/** + * Allocates and initializes one HMAC context for subsequent use, with response_finished_key. + * + * @param spdm_secured_message_context A pointer to the SPDM secured message context. + * + * @return Pointer to the HMAC context that has been initialized. + **/ +void *libspdm_hmac_new_with_response_finished_key(void *spdm_secured_message_context) +{ + libspdm_secured_message_context_t *secured_message_context; + + secured_message_context = spdm_secured_message_context; + return libspdm_hmac_new(secured_message_context->base_hash_algo); +} + +/** + * Release the specified HMAC context, with response_finished_key. + * + * @param spdm_secured_message_context A pointer to the SPDM secured message context. + * @param hmac_ctx Pointer to the HMAC context to be released. + **/ +void libspdm_hmac_free_with_response_finished_key( + void *spdm_secured_message_context, void *hmac_ctx) +{ + libspdm_secured_message_context_t *secured_message_context; + + secured_message_context = spdm_secured_message_context; + libspdm_hmac_free(secured_message_context->base_hash_algo, hmac_ctx); +} + +/** + * Set response_finished_key for subsequent use. It must be done before any + * calling to hmac_update(). + * + * @param spdm_secured_message_context A pointer to the SPDM secured message context. + * @param hmac_ctx Pointer to HMAC context. + * + * @retval true The key is set successfully. + * @retval false The key is set unsuccessfully. + **/ +bool libspdm_hmac_init_with_response_finished_key( + void *spdm_secured_message_context, void *hmac_ctx) +{ + libspdm_secured_message_context_t *secured_message_context; + + secured_message_context = spdm_secured_message_context; + return libspdm_hmac_init( + secured_message_context->base_hash_algo, hmac_ctx, + secured_message_context->handshake_secret.response_finished_key, + secured_message_context->hash_size); +} + +/** + * Makes a copy of an existing HMAC context, with response_finished_key. + * + * @param spdm_secured_message_context A pointer to the SPDM secured message context. + * @param hmac_ctx Pointer to HMAC context being copied. + * @param new_hmac_ctx Pointer to new HMAC context. + * + * @retval true HMAC context copy succeeded. + * @retval false HMAC context copy failed. + **/ +bool libspdm_hmac_duplicate_with_response_finished_key( + void *spdm_secured_message_context, + const void *hmac_ctx, void *new_hmac_ctx) +{ + libspdm_secured_message_context_t *secured_message_context; + + secured_message_context = spdm_secured_message_context; + return libspdm_hmac_duplicate(secured_message_context->base_hash_algo, hmac_ctx, new_hmac_ctx); +} + +/** + * Digests the input data and updates HMAC context, with response_finished_key. + * + * @param spdm_secured_message_context A pointer to the SPDM secured message context. + * @param hmac_ctx Pointer to HMAC context being copied. + * @param data Pointer to the buffer containing the data to be digested. + * @param data_size size of data buffer in bytes. + * + * @retval true HMAC data digest succeeded. + * @retval false HMAC data digest failed. + **/ +bool libspdm_hmac_update_with_response_finished_key( + void *spdm_secured_message_context, + void *hmac_ctx, const void *data, + size_t data_size) +{ + libspdm_secured_message_context_t *secured_message_context; + + secured_message_context = spdm_secured_message_context; + return libspdm_hmac_update(secured_message_context->base_hash_algo, hmac_ctx, data, data_size); +} + +/** + * Completes computation of the HMAC digest value, with response_finished_key. + * + * @param spdm_secured_message_context A pointer to the SPDM secured message context. + * @param hmac_ctx Pointer to HMAC context being copied. + * @param hmac_value Pointer to a buffer that receives the HMAC digest value + * + * @retval true HMAC data digest succeeded. + * @retval false HMAC data digest failed. + **/ +bool libspdm_hmac_final_with_response_finished_key( + void *spdm_secured_message_context, + void *hmac_ctx, uint8_t *hmac_value) +{ + libspdm_secured_message_context_t *secured_message_context; + + secured_message_context = spdm_secured_message_context; + return libspdm_hmac_final(secured_message_context->base_hash_algo, hmac_ctx, hmac_value); +} + +/** + * Computes the HMAC of a input data buffer, with response_finished_key. + * + * @param spdm_secured_message_context A pointer to the SPDM secured message context. + * @param data Pointer to the buffer containing the data to be HMACed. + * @param data_size size of data buffer in bytes. + * @param hash_value Pointer to a buffer that receives the HMAC value. + * + * @retval true HMAC computation succeeded. + * @retval false HMAC computation failed. + **/ +bool libspdm_hmac_all_with_response_finished_key( + void *spdm_secured_message_context, const void *data, + size_t data_size, uint8_t *hmac_value) +{ + libspdm_secured_message_context_t *secured_message_context; + + secured_message_context = spdm_secured_message_context; + return libspdm_hmac_all( + secured_message_context->base_hash_algo, data, data_size, + secured_message_context->handshake_secret.response_finished_key, + secured_message_context->hash_size, hmac_value); +} diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/libraries/libspdm/2.3.1/os_stub/include/library/malloclib.h nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/libraries/libspdm/2.3.1/os_stub/include/library/malloclib.h --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/libraries/libspdm/2.3.1/os_stub/include/library/malloclib.h 1970-01-01 00:00:00.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/libraries/libspdm/2.3.1/os_stub/include/library/malloclib.h 2024-03-05 22:14:18.000000000 +0000 @@ -0,0 +1,64 @@ +/** + * Copyright Notice: + * Copyright 2021-2022 DMTF. All rights reserved. + * License: BSD 3-Clause License. For full text see link: https://github.com/DMTF/libspdm/blob/main/LICENSE.md + **/ + +/** @file + * Provides services to allocate and free memory buffers of various memory types and alignments. + * + * The Memory Allocation Library abstracts various common memory allocation operations. This library + * allows code to be written in a phase-independent manner because the allocation of memory in PEI, DXE, + * and SMM (for example) is done via a different mechanism. Using a common library interface makes it + * much easier to port algorithms from phase to phase. + **/ + +#ifndef __MEMORY_ALLOCATION_LIB_H__ +#define __MEMORY_ALLOCATION_LIB_H__ + +/** + * Allocates a buffer of type EfiBootServicesData. + * + * Allocates the number bytes specified by AllocationSize of type EfiBootServicesData and returns a + * pointer to the allocated buffer. If AllocationSize is 0, then a valid buffer of 0 size is + * returned. If there is not enough memory remaining to satisfy the request, then NULL is returned. + * + * @param AllocationSize The number of bytes to allocate. + * + * @return A pointer to the allocated buffer or NULL if allocation fails. + * + **/ +void *allocate_pool(size_t AllocationSize); + +/** + * Allocates and zeros a buffer of type EfiBootServicesData. + * + * Allocates the number bytes specified by AllocationSize of type EfiBootServicesData, clears the + * buffer with zeros, and returns a pointer to the allocated buffer. If AllocationSize is 0, then a + * valid buffer of 0 size is returned. If there is not enough memory remaining to satisfy the + * request, then NULL is returned. + * + * @param AllocationSize The number of bytes to allocate and zero. + * + * @return A pointer to the allocated buffer or NULL if allocation fails. + * + **/ +void *allocate_zero_pool(size_t AllocationSize); + +/** + * Frees a buffer that was previously allocated with one of the pool allocation functions in the + * Memory Allocation Library. + * + * Frees the buffer specified by buffer. buffer must have been allocated on a previous call to the + * pool allocation services of the Memory Allocation Library. If it is not possible to free pool + * resources, then this function will perform no actions. + * + * If buffer was not allocated with a pool allocation function in the Memory Allocation Library, + * then ASSERT(). + * + * @param buffer Pointer to the buffer to free. + * + **/ +void free_pool(void *buffer); + +#endif diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/libraries/libspdm/2.3.1/os_stub/include/library/rnglib.h nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/libraries/libspdm/2.3.1/os_stub/include/library/rnglib.h --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/libraries/libspdm/2.3.1/os_stub/include/library/rnglib.h 1970-01-01 00:00:00.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/libraries/libspdm/2.3.1/os_stub/include/library/rnglib.h 2024-03-05 22:14:18.000000000 +0000 @@ -0,0 +1,27 @@ +/** + * Copyright Notice: + * Copyright 2021-2022 DMTF. All rights reserved. + * License: BSD 3-Clause License. For full text see link: https://github.com/DMTF/libspdm/blob/main/LICENSE.md + **/ + +/** @file + * Provides random number generator services. + **/ + +#ifndef __RNG_LIB_H__ +#define __RNG_LIB_H__ + +/** + * Generates a 64-bit random number. + * + * if rand is NULL, then ASSERT(). + * + * @param[out] rand_data buffer pointer to store the 64-bit random value. + * + * @retval true Random number generated successfully. + * @retval false Failed to generate the random number. + * + **/ +bool libspdm_get_random_number_64(uint64_t *rand_data); + +#endif /* __RNG_LIB_H__*/ diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/libraries/libspdm/2.3.1/os_stub/memlib/compare_mem.c nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/libraries/libspdm/2.3.1/os_stub/memlib/compare_mem.c --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/libraries/libspdm/2.3.1/os_stub/memlib/compare_mem.c 1970-01-01 00:00:00.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/libraries/libspdm/2.3.1/os_stub/memlib/compare_mem.c 2024-03-05 22:14:18.000000000 +0000 @@ -0,0 +1,49 @@ +/** + * Copyright Notice: + * Copyright 2021-2022 DMTF. All rights reserved. + * License: BSD 3-Clause License. For full text see link: https://github.com/DMTF/libspdm/blob/main/LICENSE.md + **/ + +/** @file + * libspdm_const_compare_mem() implementation. + **/ + +#include "base.h" + +/** + * Compares the contents of two buffers in const time. + * + * This function compares length bytes of source_buffer to length bytes of destination_buffer. + * If all length bytes of the two buffers are identical, then 0 is returned. Otherwise, the + * value returned is the first mismatched byte in source_buffer subtracted from the first + * mismatched byte in destination_buffer. + * + * If length > 0 and destination_buffer is NULL, then LIBSPDM_ASSERT(). + * If length > 0 and source_buffer is NULL, then LIBSPDM_ASSERT(). + * If length is greater than (MAX_ADDRESS - destination_buffer + 1), then LIBSPDM_ASSERT(). + * If length is greater than (MAX_ADDRESS - source_buffer + 1), then LIBSPDM_ASSERT(). + * + * @param destination_buffer A pointer to the destination buffer to compare. + * @param source_buffer A pointer to the source buffer to compare. + * @param length The number of bytes to compare. + * + * @return 0 All length bytes of the two buffers are identical. + * @retval Non-zero There is mismatched between source_buffer and destination_buffer. + * + **/ +int32_t libspdm_const_compare_mem(const void *destination_buffer, + const void *source_buffer, size_t length) +{ + const volatile uint8_t *pointer_dst; + const volatile uint8_t *pointer_src; + uint8_t delta; + + pointer_dst = (const uint8_t *)destination_buffer; + pointer_src = (const uint8_t *)source_buffer; + delta = 0; + while ((length-- != 0)) { + delta |= *(pointer_dst++) ^ *(pointer_src++); + } + + return delta; +} diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/libraries/libspdm/2.3.1/os_stub/platform_lib_null/time_linux.c nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/libraries/libspdm/2.3.1/os_stub/platform_lib_null/time_linux.c --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/libraries/libspdm/2.3.1/os_stub/platform_lib_null/time_linux.c 1970-01-01 00:00:00.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/libraries/libspdm/2.3.1/os_stub/platform_lib_null/time_linux.c 2024-03-05 22:14:18.000000000 +0000 @@ -0,0 +1,17 @@ +/** + * Copyright Notice: + * Copyright 2022 DMTF. All rights reserved. + * License: BSD 3-Clause License. For full text see link: https://github.com/DMTF/libspdm/blob/main/LICENSE.md + **/ + +#include + +/** + * Suspends the execution of the current thread until the time-out interval elapses. + * + * @param microseconds The time interval for which execution is to be suspended, in milliseconds. + * + **/ +void libspdm_sleep_in_us(uint64_t microseconds) +{ +} diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/libraries/libspdm/2.3.1/os_stub/platform_lib_null/watchdog.c nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/libraries/libspdm/2.3.1/os_stub/platform_lib_null/watchdog.c --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/libraries/libspdm/2.3.1/os_stub/platform_lib_null/watchdog.c 1970-01-01 00:00:00.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/libraries/libspdm/2.3.1/os_stub/platform_lib_null/watchdog.c 2024-03-05 22:14:18.000000000 +0000 @@ -0,0 +1,45 @@ +/** + * Copyright Notice: + * Copyright 2022 DMTF. All rights reserved. + * License: BSD 3-Clause License. For full text see link: https://github.com/DMTF/libspdm/blob/main/LICENSE.md + **/ + +#include "base.h" +#include "internal/libspdm_lib_config.h" + +#if LIBSPDM_ENABLE_CAPABILITY_HBEAT_CAP +/** + * If no heartbeat arrives in seconds, the watchdog timeout event + * should terminate the session. + * + * @param session_id Indicate the SPDM session ID. + * @param seconds heartbeat period, in seconds. + * + **/ +bool libspdm_start_watchdog(uint32_t session_id, uint16_t seconds) +{ + return true; +} + +/** + * stop watchdog. + * + * @param session_id Indicate the SPDM session ID. + * + **/ +bool libspdm_stop_watchdog(uint32_t session_id) +{ + return true; +} + +/** + * Reset the watchdog in heartbeat response. + * + * @param session_id Indicate the SPDM session ID. + * + **/ +bool libspdm_reset_watchdog(uint32_t session_id) +{ + return true; +} +#endif /* LIBSPDM_ENABLE_CAPABILITY_HBEAT_CAP */ diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/libraries/libspdm/2.3.1/os_stub/spdm_crypt_ext_lib/cryptlib_ext.h nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/libraries/libspdm/2.3.1/os_stub/spdm_crypt_ext_lib/cryptlib_ext.h --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/libraries/libspdm/2.3.1/os_stub/spdm_crypt_ext_lib/cryptlib_ext.h 1970-01-01 00:00:00.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/libraries/libspdm/2.3.1/os_stub/spdm_crypt_ext_lib/cryptlib_ext.h 2024-03-05 22:14:18.000000000 +0000 @@ -0,0 +1,668 @@ +/** + * Copyright Notice: + * Copyright 2021-2022 DMTF. All rights reserved. + * License: BSD 3-Clause License. For full text see link: https://github.com/DMTF/libspdm/blob/main/LICENSE.md + **/ + +#ifndef CRYPTLIB_EXT_H +#define CRYPTLIB_EXT_H + +#include "hal/base.h" + +/** + * Retrieve the common name (CN) string from one X.509 certificate. + * + * @param[in] cert Pointer to the DER-encoded X509 certificate. + * @param[in] cert_size Size of the X509 certificate in bytes. + * @param[out] common_name Buffer to contain the retrieved certificate common + * name string (UTF8). At most common_name_size bytes will be + * written and the string will be null terminated. May be + * NULL in order to determine the size buffer needed. + * @param[in,out] common_name_size The size in bytes of the common_name buffer on input, + * and the size of buffer returned common_name on output. + * If common_name is NULL then the amount of space needed + * in buffer (including the final null) is returned. + * + * @retval true + * @retval false + **/ +extern bool libspdm_x509_get_common_name(const uint8_t *cert, size_t cert_size, + char *common_name, + size_t *common_name_size); + +/** + * Retrieve the organization name (O) string from one X.509 certificate. + * + * @param[in] cert Pointer to the DER-encoded X509 certificate. + * @param[in] cert_size Size of the X509 certificate in bytes. + * @param[out] name_buffer Buffer to contain the retrieved certificate organization + * name string. At most name_buffer_size bytes will be + * written and the string will be null terminated. May be + * NULL in order to determine the size buffer needed. + * @param[in,out] name_buffer_size The size in bytes of the name buffer on input, + * and the size of buffer returned name on output. + * If name_buffer is NULL then the amount of space needed + * in buffer (including the final null) is returned. + * + * @retval true + * @retval false + **/ +extern bool libspdm_x509_get_organization_name(const uint8_t *cert, size_t cert_size, + char *name_buffer, + size_t *name_buffer_size); + +/** + * Retrieve the issuer common name (CN) string from one X.509 certificate. + * + * @param[in] cert Pointer to the DER-encoded X509 certificate. + * @param[in] cert_size Size of the X509 certificate in bytes. + * @param[out] common_name Buffer to contain the retrieved certificate issuer common + * name string. At most common_name_size bytes will be + * written and the string will be null terminated. May be + * NULL in order to determine the size buffer needed. + * @param[in,out] common_name_size The size in bytes of the common_name buffer on input, + * and the size of buffer returned common_name on output. + * If common_name is NULL then the amount of space needed + * in buffer (including the final null) is returned. + * + * @retval true + * @retval false + **/ +extern bool libspdm_x509_get_issuer_common_name(const uint8_t *cert, size_t cert_size, + char *common_name, + size_t *common_name_size); + +/** + * Retrieve the issuer organization name (O) string from one X.509 certificate. + * + * @param[in] cert Pointer to the DER-encoded X509 certificate. + * @param[in] cert_size Size of the X509 certificate in bytes. + * @param[out] name_buffer Buffer to contain the retrieved certificate issuer organization + * name string. At most name_buffer_size bytes will be + * written and the string will be null terminated. May be + * NULL in order to determine the size buffer needed. + * @param[in,out] name_buffer_size The size in bytes of the name buffer on input, + * and the size of buffer returned name on output. + * If name_buffer is NULL then the amount of space needed + * in buffer (including the final null) is returned. + * + * @retval true + * @retval false + **/ +extern bool libspdm_x509_get_issuer_orgnization_name(const uint8_t *cert, size_t cert_size, + char *name_buffer, + size_t *name_buffer_size); + +/** + * Retrieve the signature algorithm from one X.509 certificate. + * + * @param[in] cert Pointer to the DER-encoded X509 certificate. + * @param[in] cert_size Size of the X509 certificate in bytes. + * @param[out] oid Signature algorithm Object identifier buffer. + * @param[in,out] oid_size Signature algorithm Object identifier buffer size. + * + * @retval true + * @retval false + **/ +extern bool libspdm_x509_get_signature_algorithm(const uint8_t *cert, + size_t cert_size, uint8_t *oid, + size_t *oid_size); + +/** + * Construct a X509 object from DER-encoded certificate data. + * + * If cert is NULL, then return false. + * If single_x509_cert is NULL, then return false. + * If this interface is not supported, then return false. + * + * @param[in] cert Pointer to the DER-encoded certificate data. + * @param[in] cert_size The size of certificate data in bytes. + * @param[out] single_x509_cert The generated X509 object. + * + * @retval true The X509 object generation succeeded. + * @retval false The operation failed. + * @retval false This interface is not supported. + **/ +extern bool libspdm_x509_construct_certificate(const uint8_t *cert, size_t cert_size, + uint8_t **single_x509_cert); + +/** + * Construct a X509 stack object from a list of DER-encoded certificate data. + * + * If x509_stack is NULL, then return false. + * If this interface is not supported, then return false. + * + * @param[in, out] x509_stack On input, pointer to an existing or NULL X509 stack object. + * On output, pointer to the X509 stack object with new + * inserted X509 certificate. + * @param ... A list of DER-encoded single certificate data followed + * by certificate size. A NULL terminates the list. The + * pairs are the arguments to libspdm_x509_construct_certificate(). + * + * @retval true The X509 stack construction succeeded. + * @retval false The construction operation failed. + * @retval false This interface is not supported. + **/ +extern bool libspdm_x509_construct_certificate_stack(uint8_t **x509_stack, ...); + +/** + * Release the specified X509 object. + * + * If the interface is not supported, then ASSERT(). + * + * @param[in] x509_cert Pointer to the X509 object to be released. + **/ +extern void libspdm_x509_free(void *x509_cert); + +/** + * Release the specified X509 stack object. + * + * If the interface is not supported, then ASSERT(). + * + * @param[in] x509_stack Pointer to the X509 stack object to be released. + **/ +extern void libspdm_x509_stack_free(void *x509_stack); + +/** + * Retrieve the TBSCertificate from one given X.509 certificate. + * + * @param[in] cert Pointer to the given DER-encoded X509 certificate. + * @param[in] cert_size size of the X509 certificate in bytes. + * @param[out] tbs_cert DER-Encoded to-Be-Signed certificate. + * @param[out] tbs_cert_size size of the TBS certificate in bytes. + * + * If cert is NULL, then return false. + * If tbs_cert is NULL, then return false. + * If tbs_cert_size is NULL, then return false. + * If this interface is not supported, then return false. + * + * @retval true The TBSCertificate was retrieved successfully. + * @retval false Invalid X.509 certificate. + **/ +extern bool libspdm_x509_get_tbs_cert(const uint8_t *cert, size_t cert_size, + uint8_t **tbs_cert, size_t *tbs_cert_size); + +/** + * Retrieve the RSA Private key from the password-protected PEM key data. + * + * If pem_data is NULL, then return false. + * If rsa_context is NULL, then return false. + * If this interface is not supported, then return false. + * + * @param[in] pem_data Pointer to the PEM-encoded key data to be retrieved. + * @param[in] pem_size Size of the PEM key data in bytes. + * @param[in] password NULL-terminated passphrase used for encrypted PEM key data. + * @param[out] rsa_context Pointer to new-generated RSA context which contain the retrieved + * RSA private key component. Use libspdm_rsa_free() function to free the + * resource. + * + * @retval true RSA Private key was retrieved successfully. + * @retval false Invalid PEM key data or incorrect password. + * @retval false This interface is not supported. + **/ +extern bool libspdm_rsa_get_private_key_from_pem(const uint8_t *pem_data, + size_t pem_size, + const char *password, + void **rsa_context); + +/** + * Retrieve the EC Private key from the password-protected PEM key data. + * + * @param[in] pem_data Pointer to the PEM-encoded key data to be retrieved. + * @param[in] pem_size Size of the PEM key data in bytes. + * @param[in] password NULL-terminated passphrase used for encrypted PEM key data. + * @param[out] ec_context Pointer to new-generated EC DSA context which contain the retrieved + * EC private key component. Use libspdm_ec_free() function to free the + * resource. + * + * If pem_data is NULL, then return false. + * If ec_context is NULL, then return false. + * + * @retval true EC Private key was retrieved successfully. + * @retval false Invalid PEM key data or incorrect password. + * + **/ +extern bool libspdm_ec_get_private_key_from_pem(const uint8_t *pem_data, size_t pem_size, + const char *password, + void **ec_context); + +/** + * Retrieve the Ed Private key from the password-protected PEM key data. + * + * @param[in] pem_data Pointer to the PEM-encoded key data to be retrieved. + * @param[in] pem_size Size of the PEM key data in bytes. + * @param[in] password NULL-terminated passphrase used for encrypted PEM key data. + * @param[out] ecd_context Pointer to new-generated Ed DSA context which contain the retrieved + * Ed private key component. Use libspdm_ecd_free() function to free the + * resource. + * + * If pem_data is NULL, then return false. + * If ecd_context is NULL, then return false. + * + * @retval true Ed Private key was retrieved successfully. + * @retval false Invalid PEM key data or incorrect password. + **/ +extern bool libspdm_ecd_get_private_key_from_pem(const uint8_t *pem_data, + size_t pem_size, + const char *password, + void **ecd_context); + +/** + * Retrieve the sm2 Private key from the password-protected PEM key data. + * + * @param[in] pem_data Pointer to the PEM-encoded key data to be retrieved. + * @param[in] pem_size Size of the PEM key data in bytes. + * @param[in] password NULL-terminated passphrase used for encrypted PEM key data. + * @param[out] sm2_context Pointer to new-generated sm2 context which contain the retrieved + * sm2 private key component. Use sm2_free() function to free the + * resource. + * + * If pem_data is NULL, then return false. + * If sm2_context is NULL, then return false. + * + * @retval true sm2 Private key was retrieved successfully. + * @retval false Invalid PEM key data or incorrect password. + * + **/ +extern bool libspdm_sm2_get_private_key_from_pem(const uint8_t *pem_data, + size_t pem_size, + const char *password, + void **sm2_context); + +/** + * Derive key data using HMAC-SHA256 based KDF. + * + * @param[in] key Pointer to the user-supplied key. + * @param[in] key_size Key size in bytes. + * @param[in] salt Pointer to the salt value. + * @param[in] salt_size Salt size in bytes. + * @param[in] info Pointer to the application specific info. + * @param[in] info_size Info size in bytes. + * @param[out] out Pointer to buffer to receive hkdf value. + * @param[in] out_size Size of hkdf bytes to generate. + * + * @retval true Hkdf generated successfully. + * @retval false Hkdf generation failed. + **/ +extern bool libspdm_hkdf_sha256_extract_and_expand(const uint8_t *key, size_t key_size, + const uint8_t *salt, size_t salt_size, + const uint8_t *info, size_t info_size, + uint8_t *out, size_t out_size); + +/** + * Derive key data using HMAC-SHA384 based KDF. + * + * @param[in] key Pointer to the user-supplied key. + * @param[in] key_size Key size in bytes. + * @param[in] salt Pointer to the salt value. + * @param[in] salt_size Salt size in bytes. + * @param[in] info Pointer to the application specific info. + * @param[in] info_size Info size in bytes. + * @param[out] out Pointer to buffer to receive hkdf value. + * @param[in] out_size Size of hkdf bytes to generate. + * + * @retval true Hkdf generated successfully. + * @retval false Hkdf generation failed. + **/ +extern bool libspdm_hkdf_sha384_extract_and_expand(const uint8_t *key, size_t key_size, + const uint8_t *salt, size_t salt_size, + const uint8_t *info, size_t info_size, + uint8_t *out, size_t out_size); + +/** + * Derive key data using HMAC-SHA512 based KDF. + * + * @param[in] key Pointer to the user-supplied key. + * @param[in] key_size Key size in bytes. + * @param[in] salt Pointer to the salt value. + * @param[in] salt_size Salt size in bytes. + * @param[in] info Pointer to the application specific info. + * @param[in] info_size Info size in bytes. + * @param[out] out Pointer to buffer to receive hkdf value. + * @param[in] out_size Size of hkdf bytes to generate. + * + * @retval true Hkdf generated successfully. + * @retval false Hkdf generation failed. + **/ +extern bool libspdm_hkdf_sha512_extract_and_expand(const uint8_t *key, size_t key_size, + const uint8_t *salt, size_t salt_size, + const uint8_t *info, size_t info_size, + uint8_t *out, size_t out_size); + +/** + * Derive SHA3_256 HMAC-based Extract-and-Expand key Derivation Function (HKDF). + * + * @param[in] key Pointer to the user-supplied key. + * @param[in] key_size Key size in bytes. + * @param[in] salt Pointer to the salt value. + * @param[in] salt_size Salt size in bytes. + * @param[in] info Pointer to the application specific info. + * @param[in] info_size Info size in bytes. + * @param[out] out Pointer to buffer to receive hkdf value. + * @param[in] out_size Size of hkdf bytes to generate. + * + * @retval true Hkdf generated successfully. + * @retval false Hkdf generation failed. + **/ +extern bool libspdm_hkdf_sha3_256_extract_and_expand(const uint8_t *key, size_t key_size, + const uint8_t *salt, size_t salt_size, + const uint8_t *info, size_t info_size, + uint8_t *out, size_t out_size); + +/** + * Derive SHA3_384 HMAC-based Extract-and-Expand key Derivation Function (HKDF). + * + * @param[in] key Pointer to the user-supplied key. + * @param[in] key_size Key size in bytes. + * @param[in] salt Pointer to the salt value. + * @param[in] salt_size Salt size in bytes. + * @param[in] info Pointer to the application specific info. + * @param[in] info_size Info size in bytes. + * @param[out] out Pointer to buffer to receive hkdf value. + * @param[in] out_size Size of hkdf bytes to generate. + * + * @retval true Hkdf generated successfully. + * @retval false Hkdf generation failed. + **/ +extern bool libspdm_hkdf_sha3_384_extract_and_expand(const uint8_t *key, size_t key_size, + const uint8_t *salt, size_t salt_size, + const uint8_t *info, size_t info_size, + uint8_t *out, size_t out_size); + +/** + * Derive SHA3_512 HMAC-based Extract-and-Expand key Derivation Function (HKDF). + * + * @param[in] key Pointer to the user-supplied key. + * @param[in] key_size Key size in bytes. + * @param[in] salt Pointer to the salt value. + * @param[in] salt_size Salt size in bytes. + * @param[in] info Pointer to the application specific info. + * @param[in] info_size Info size in bytes. + * @param[out] out Pointer to buffer to receive hkdf value. + * @param[in] out_size Size of hkdf bytes to generate. + * + * @retval true Hkdf generated successfully. + * @retval false Hkdf generation failed. + **/ +extern bool libspdm_hkdf_sha3_512_extract_and_expand(const uint8_t *key, size_t key_size, + const uint8_t *salt, size_t salt_size, + const uint8_t *info, size_t info_size, + uint8_t *out, size_t out_size); + +/** + * Derive SM3_256 HMAC-based Extract-and-Expand key Derivation Function (HKDF). + * + * @param[in] key Pointer to the user-supplied key. + * @param[in] key_size Key size in bytes. + * @param[in] salt Pointer to the salt value. + * @param[in] salt_size Salt size in bytes. + * @param[in] info Pointer to the application specific info. + * @param[in] info_size Info size in bytes. + * @param[out] out Pointer to buffer to receive hkdf value. + * @param[in] out_size Size of hkdf bytes to generate. + * + * @retval true Hkdf generated successfully. + * @retval false Hkdf generation failed. + **/ +extern bool libspdm_hkdf_sm3_256_extract_and_expand(const uint8_t *key, size_t key_size, + const uint8_t *salt, size_t salt_size, + const uint8_t *info, size_t info_size, + uint8_t *out, size_t out_size); + +/** + * Sets the public key component into the established EC context. + * + * For P-256, the public_size is 64. first 32-byte is X, second 32-byte is Y. + * For P-384, the public_size is 96. first 48-byte is X, second 48-byte is Y. + * For P-521, the public_size is 132. first 66-byte is X, second 66-byte is Y. + * + * @param[in, out] ec_context Pointer to EC context being set. + * @param[in] public Pointer to the buffer to receive generated public X,Y. + * @param[in] public_size The size of public buffer in bytes. + * + * @retval true EC public key component was set successfully. + * @retval false Invalid EC public key component. + **/ +extern bool libspdm_ec_set_pub_key(void *ec_context, const uint8_t *public_key, + size_t public_key_size); + +/** + * Sets the private key component into the established EC context. + * + * For P-256, the private_key_size is 32 byte. + * For P-384, the private_key_size is 48 byte. + * For P-521, the private_key_size is 66 byte. + * + * @param[in, out] ec_context Pointer to EC context being set. + * @param[in] private_key Pointer to the private key buffer. + * @param[in] private_key_size The size of private key buffer in bytes. + * + * @retval true EC private key component was set successfully. + * @retval false Invalid EC private key component. + * + **/ +extern bool libspdm_ec_set_priv_key(void *ec_context, const uint8_t *private_key, + size_t private_key_size); + +/** + * Gets the public key component from the established EC context. + * + * For P-256, the public_size is 64. first 32-byte is X, second 32-byte is Y. + * For P-384, the public_size is 96. first 48-byte is X, second 48-byte is Y. + * For P-521, the public_size is 132. first 66-byte is X, second 66-byte is Y. + * + * @param[in, out] ec_context Pointer to EC context being set. + * @param[out] public Pointer to the buffer to receive generated public X,Y. + * @param[in, out] public_size On input, the size of public buffer in bytes. + * On output, the size of data returned in public buffer in bytes. + * + * @retval true EC key component was retrieved successfully. + * @retval false Invalid EC key component. + **/ +extern bool libspdm_ec_get_pub_key(void *ec_context, uint8_t *public_key, size_t *public_key_size); + +/** + * Validates key components of EC context. + * NOTE: This function performs integrity checks on all the EC key material, so + * the EC key structure must contain all the private key data. + * + * If ec_context is NULL, then return false. + * + * @param[in] ec_context Pointer to EC context to check. + * + * @retval true EC key components are valid. + * @retval false EC key components are not valid. + **/ +extern bool libspdm_ec_check_key(const void *ec_context); + +/** + * Sets the public key component into the established Ed context. + * + * For ed25519, the public_size is 32. + * For ed448, the public_size is 57. + * + * @param[in, out] ecd_context Pointer to Ed context being set. + * @param[in] public_key Pointer to the buffer to receive generated public X,Y. + * @param[in] public_size The size of public buffer in bytes. + * + * @retval true Ed public key component was set successfully. + * @retval false Invalid EC public key component. + **/ +extern bool libspdm_ecd_set_pub_key(void *ecd_context, const uint8_t *public_key, + size_t public_key_size); + +/** + * Gets the public key component from the established Ed context. + * + * For ed25519, the public_size is 32. + * For ed448, the public_size is 57. + * + * @param[in, out] ecd_context Pointer to Ed context being set. + * @param[out] public Pointer to the buffer to receive generated public X,Y. + * @param[in, out] public_size On input, the size of public buffer in bytes. + * On output, the size of data returned in public buffer in bytes. + * + * @retval true Ed key component was retrieved successfully. + * @retval false Invalid EC public key component. + **/ +extern bool libspdm_ecd_get_pub_key(void *ecd_context, uint8_t *public_key, + size_t *public_key_size); + +/** + * Validates key components of Ed context. + * NOTE: This function performs integrity checks on all the Ed key material, so + * the Ed key structure must contain all the private key data. + * + * If ecd_context is NULL, then return false. + * + * @param[in] ecd_context Pointer to Ed context to check. + * + * @retval true Ed key components are valid. + * @retval false Ed key components are not valid. + **/ +extern bool libspdm_ecd_check_key(const void *ecd_context); + +/** + * Generates Ed key and returns Ed public key. + * + * For ed25519, the public_size is 32. + * For ed448, the public_size is 57. + * + * If ecd_context is NULL, then return false. + * If public_size is NULL, then return false. + * If public_size is large enough but public is NULL, then return false. + * + * @param[in, out] ecd_context Pointer to the Ed context. + * @param[out] public_key Pointer to the buffer to receive generated public key. + * @param[in, out] public_key_size On input, the size of public buffer in bytes. + * On output, the size of data returned in public buffer in bytes. + * + * @retval true Ed public key generation succeeded. + * @retval false Ed public key generation failed. + * @retval false public_size is not large enough. + **/ +extern bool libspdm_ecd_generate_key(void *ecd_context, uint8_t *public_key, + size_t *public_key_size); + +/** + * Generates DH parameter. + * + * Given generator g, and length of prime number p in bits, this function generates p, + * and sets DH context according to value of g and p. + * + * If dh_context is NULL, then return false. + * If prime is NULL, then return false. + * If this interface is not supported, then return false. + * + * @param[in, out] dh_context Pointer to the DH context. + * @param[in] generator Value of generator. + * @param[in] prime_length Length in bits of prime to be generated. + * @param[out] prime Pointer to the buffer to receive the generated prime number. + * + * @retval true DH parameter generation succeeded. + * @retval false Value of generator is not supported. + * @retval false Random number generator fails to generate random prime number with prime_length. + * @retval false This interface is not supported. + **/ +extern bool libspdm_dh_generate_parameter(void *dh_context, size_t generator, + size_t prime_length, uint8_t *prime); + +/** + * Sets generator and prime parameters for DH. + * + * Given generator g, and prime number p, this function and sets DH context accordingly. + * + * If dh_context is NULL, then return false. + * If prime is NULL, then return false. + * If this interface is not supported, then return false. + * + * @param[in, out] dh_context Pointer to the DH context. + * @param[in] generator Value of generator. + * @param[in] prime_length Length in bits of prime to be generated. + * @param[in] prime Pointer to the prime number. + * + * @retval true DH parameter setting succeeded. + * @retval false Value of generator is not supported. + * @retval false Value of generator is not suitable for the prime. + * @retval false Value of prime is not a prime number. + * @retval false Value of prime is not a safe prime number. + * @retval false This interface is not supported. + **/ +extern bool libspdm_dh_set_parameter(void *dh_context, size_t generator, + size_t prime_length, const uint8_t *prime); + +/** + * Sets the public key component into the established sm2 context. + * + * The public_size is 64. first 32-byte is X, second 32-byte is Y. + * + * @param[in, out] ec_context Pointer to sm2 context being set. + * @param[in] public_key Pointer to the buffer to receive generated public X,Y. + * @param[in] public_key_size The size of public buffer in bytes. + * + * @retval true sm2 public key component was set successfully. + * @retval false Invalid sm2 public key component. + **/ +extern bool libspdm_sm2_dsa_set_pub_key(void *sm2_context, const uint8_t *public_key, + size_t public_key_size); + +/** + * Gets the public key component from the established sm2 context. + * + * The public_size is 64. first 32-byte is X, second 32-byte is Y. + * + * @param[in, out] sm2_context Pointer to sm2 context being set. + * @param[out] public_key Pointer to the buffer to receive generated public X,Y. + * @param[in, out] public_key_size On input, the size of public buffer in bytes. + * On output, the size of data returned in public buffer in bytes. + * + * @retval true sm2 key component was retrieved successfully. + * @retval false Invalid sm2 key component. + **/ +extern bool libspdm_sm2_dsa_get_pub_key(void *sm2_context, uint8_t *public_key, + size_t *public_key_size); + +/** + * Validates key components of sm2 context. + * NOTE: This function performs integrity checks on all the sm2 key material, so + * the sm2 key structure must contain all the private key data. + * + * If sm2_context is NULL, then return false. + * + * @param[in] sm2_context Pointer to sm2 context to check. + * + * @retval true sm2 key components are valid. + * @retval false sm2 key components are not valid. + **/ +extern bool libspdm_sm2_dsa_check_key(const void *sm2_context); + +/** + * Generates sm2 key and returns sm2 public key (X, Y), based upon GB/T 32918.3-2016: SM2 - Part3. + * + * This function generates random secret, and computes the public key (X, Y), which is + * returned via parameter public, public_size. + * X is the first half of public with size being public_size / 2, + * Y is the second half of public with size being public_size / 2. + * sm2 context is updated accordingly. + * If the public buffer is too small to hold the public X, Y, false is returned and + * public_size is set to the required buffer size to obtain the public X, Y. + * + * The public_size is 64. first 32-byte is X, second 32-byte is Y. + * + * If sm2_context is NULL, then return false. + * If public_size is NULL, then return false. + * If public_size is large enough but public is NULL, then return false. + * + * @param[in, out] sm2_context Pointer to the sm2 context. + * @param[out] public_data Pointer to the buffer to receive generated public X,Y. + * @param[in, out] public_size On input, the size of public buffer in bytes. + * On output, the size of data returned in public buffer in bytes. + * + * @retval true sm2 public X,Y generation succeeded. + * @retval false sm2 public X,Y generation failed. + * @retval false public_size is not large enough. + **/ +extern bool libspdm_sm2_dsa_generate_key(void *sm2_context, uint8_t *public_data, + size_t *public_size); + +#endif /* CRYPTLIB_EXT_H */ diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/libraries/libspdm/2.3.1/os_stub/spdm_device_secret_lib_null/lib.c nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/libraries/libspdm/2.3.1/os_stub/spdm_device_secret_lib_null/lib.c --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/libraries/libspdm/2.3.1/os_stub/spdm_device_secret_lib_null/lib.c 1970-01-01 00:00:00.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/libraries/libspdm/2.3.1/os_stub/spdm_device_secret_lib_null/lib.c 2024-03-05 22:14:18.000000000 +0000 @@ -0,0 +1,105 @@ +/** + * Copyright Notice: + * Copyright 2021-2022 DMTF. All rights reserved. + * License: BSD 3-Clause License. For full text see link: https://github.com/DMTF/libspdm/blob/main/LICENSE.md + **/ + +/** @file + * SPDM common library. + * It follows the SPDM Specification. + **/ + +#include "library/spdm_device_secret_lib.h" + +#if LIBSPDM_ENABLE_CAPABILITY_MEAS_CAP +libspdm_return_t libspdm_measurement_collection( + spdm_version_number_t spdm_version, + uint8_t measurement_specification, + uint32_t measurement_hash_algo, + uint8_t mesurements_index, + uint8_t request_attribute, + uint8_t *content_changed, + uint8_t *device_measurement_count, + void *device_measurement, + size_t *device_measurement_size) +{ + return LIBSPDM_STATUS_UNSUPPORTED_CAP; +} + +bool libspdm_generate_measurement_summary_hash( + spdm_version_number_t spdm_version, + uint32_t base_hash_algo, + uint8_t measurement_specification, + uint32_t measurement_hash_algo, + uint8_t measurement_summary_hash_type, + uint8_t *measurement_summary_hash, + size_t *measurement_summary_hash_size) +{ + return false; +} +#endif /* LIBSPDM_ENABLE_CAPABILITY_MEAS_CAP */ + +#if LIBSPDM_ENABLE_CAPABILITY_MUT_AUTH_CAP +bool libspdm_requester_data_sign( + spdm_version_number_t spdm_version, uint8_t op_code, + uint16_t req_base_asym_alg, + uint32_t base_hash_algo, bool is_data_hash, + const uint8_t *message, size_t message_size, + uint8_t *signature, size_t *sig_size) +{ + return false; +} +#endif /* LIBSPDM_ENABLE_CAPABILITY_MUT_AUTH_CAP */ + +bool libspdm_responder_data_sign( + spdm_version_number_t spdm_version, uint8_t op_code, + uint32_t base_asym_algo, + uint32_t base_hash_algo, bool is_data_hash, + const uint8_t *message, size_t message_size, + uint8_t *signature, size_t *sig_size) +{ + return false; +} + +#if LIBSPDM_ENABLE_CAPABILITY_PSK_EX_CAP +bool libspdm_psk_handshake_secret_hkdf_expand( + spdm_version_number_t spdm_version, + uint32_t base_hash_algo, + const uint8_t *psk_hint, + size_t psk_hint_size, + const uint8_t *info, + size_t info_size, + uint8_t *out, size_t out_size) +{ + return false; +} + +bool libspdm_psk_master_secret_hkdf_expand( + spdm_version_number_t spdm_version, + uint32_t base_hash_algo, + const uint8_t *psk_hint, + size_t psk_hint_size, + const uint8_t *info, + size_t info_size, uint8_t *out, + size_t out_size) +{ + return false; +} +#endif /* LIBSPDM_ENABLE_CAPABILITY_PSK_EX_CAP */ + +#if LIBSPDM_ENABLE_CAPABILITY_SET_CERTIFICATE_CAP +bool libspdm_write_certificate_to_nvm(uint8_t slot_id, const void * cert_chain, + size_t cert_chain_size) +{ + return false; +} +#endif /* LIBSPDM_ENABLE_CAPABILITY_SET_CERTIFICATE_CAP */ + +#if LIBSPDM_ENABLE_CAPABILITY_GET_CSR_CAP +bool libspdm_gen_csr(uint32_t base_hash_algo, uint32_t base_asym_algo, bool *need_reset, + uint8_t *requester_info, size_t requester_info_length, + size_t *csr_len, uint8_t **csr_pointer) +{ + return false; +} +#endif /* LIBSPDM_ENABLE_CAPABILITY_GET_CSR_CAP */ diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/libraries/libspdm/nvidia/nvspdm_crypt_null.c nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/libraries/libspdm/nvidia/nvspdm_crypt_null.c --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/libraries/libspdm/nvidia/nvspdm_crypt_null.c 1970-01-01 00:00:00.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/libraries/libspdm/nvidia/nvspdm_crypt_null.c 2024-03-05 22:14:19.000000000 +0000 @@ -0,0 +1,54 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + + +// +// Included libspdm copyright alongside NVIDIA copyright, as these functions +// are copied from libspdm cryptlib_null files. Meant to more easily stub out +// cryptography functions when not needed. +// + +/** + * Copyright Notice: + * Copyright 2021-2022 DMTF. All rights reserved. + * License: BSD 3-Clause License. For full text see link: https://github.com/DMTF/libspdm/blob/main/LICENSE.md + **/ + + +// Use headers directly so we don't rely on internal_crypt_lib.h +#include +#include "library/debuglib.h" +#include "library/memlib.h" +#include "library/cryptlib.h" +#include +// Stub out all crypto functions that we do not support. + +bool libspdm_ec_get_private_key_from_pem(const uint8_t *pem_data, size_t pem_size, + const char *password, + void **ec_context) +{ + LIBSPDM_ASSERT(false); + return false; +} + + diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/libraries/libspdm/nvidia/nvspdm_cryptlib_extensions.h nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/libraries/libspdm/nvidia/nvspdm_cryptlib_extensions.h --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/libraries/libspdm/nvidia/nvspdm_cryptlib_extensions.h 1970-01-01 00:00:00.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/libraries/libspdm/nvidia/nvspdm_cryptlib_extensions.h 2024-03-05 22:14:19.000000000 +0000 @@ -0,0 +1,41 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + + +bool libspdm_aead_gcm_prealloc(void **context); +void libspdm_aead_free(void *context); +bool libspdm_aead_aes_gcm_encrypt_prealloc(void *context, + const uint8_t *key, size_t key_size, + const uint8_t *iv, size_t iv_size, + const uint8_t *a_data, size_t a_data_size, + const uint8_t *data_in, size_t data_in_size, + uint8_t *tag_out, size_t tag_size, + uint8_t *data_out, size_t *data_out_size); +bool libspdm_aead_aes_gcm_decrypt_prealloc(void *context, + const uint8_t *key, size_t key_size, + const uint8_t *iv, size_t iv_size, + const uint8_t *a_data, size_t a_data_size, + const uint8_t *data_in, size_t data_in_size, + const uint8_t *tag, size_t tag_size, + uint8_t *data_out, size_t *data_out_size); + diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/libraries/libspdm/nvidia/nvspdm_debuglib.c nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/libraries/libspdm/nvidia/nvspdm_debuglib.c --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/libraries/libspdm/nvidia/nvspdm_debuglib.c 1970-01-01 00:00:00.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/libraries/libspdm/nvidia/nvspdm_debuglib.c 2024-03-05 22:14:19.000000000 +0000 @@ -0,0 +1,58 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2021-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#include "gpu/gpu.h" +#include "base.h" +#include "libraries/utils/nvprintf.h" + +static bool g_libspdmAssertHit = false; + +/* + * Checking and clear libspdm assert status. + * Any assert in libspdm we need to return error and stop processing. + * Returns true if no assert detected, false if assert detected. + */ +bool +nvspdm_check_and_clear_libspdm_assert(void) +{ + bool bAssertHit = g_libspdmAssertHit; + + // Clear assert status before returning. + g_libspdmAssertHit = false; + + // Function is successful on no assert, failing on assert. + return !bAssertHit; +} + +void +libspdm_debug_assert +( + const char *file_name, + size_t line_number, + const char *description +) +{ + NV_PRINTF (LEVEL_ERROR, "libspdm assertion hit!\n"); + g_libspdmAssertHit = NV_TRUE; + DBG_BREAKPOINT(); +} diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/libraries/libspdm/nvidia/nvspdm_malloclib.c nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/libraries/libspdm/nvidia/nvspdm_malloclib.c --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/libraries/libspdm/nvidia/nvspdm_malloclib.c 1970-01-01 00:00:00.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/libraries/libspdm/nvidia/nvspdm_malloclib.c 2024-03-05 22:14:19.000000000 +0000 @@ -0,0 +1,49 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2021-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#include "nvport/nvport.h" +#include + +void *allocate_pool(size_t AllocationSize) +{ + return portMemAllocNonPaged((NvLength)AllocationSize); +} + +void *allocate_zero_pool(size_t AllocationSize) +{ + void * ptr = portMemAllocNonPaged((NvLength)AllocationSize); + + if (ptr == NULL) + { + return ptr; + } + + portMemSet(ptr, 0, AllocationSize); + + return ptr; +} + +void free_pool(void *buffer) +{ + portMemFree(buffer); +} diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/libraries/libspdm/nvidia/nvspdm_memlib.c nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/libraries/libspdm/nvidia/nvspdm_memlib.c --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/libraries/libspdm/nvidia/nvspdm_memlib.c 1970-01-01 00:00:00.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/libraries/libspdm/nvidia/nvspdm_memlib.c 2024-03-05 22:14:19.000000000 +0000 @@ -0,0 +1,147 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +/** + * Copyright Notice: + * Copyright 2021-2022 DMTF. All rights reserved. + * License: BSD 3-Clause License. For full text see link: https://github.com/DMTF/libspdm/blob/main/LICENSE.md + **/ + +// Included libSPDM copyright, as file is NV-authored but uses libSPDM code. + +#include "base.h" +#include "library/debuglib.h" +#include "hal/library/memlib.h" +#include "nvport/nvport.h" // NvPort Header + +/** + * Fills a target buffer with a byte value, and returns the target buffer. + * + * This function fills length bytes of buffer with value, and returns buffer. + * + * If length is greater than (MAX_ADDRESS - buffer + 1), then LIBSPDM_ASSERT(). + * + * @param buffer The memory to set. + * @param length The number of bytes to set. + * @param value The value with which to fill length bytes of buffer. + * + * @return buffer. + * + **/ +void *libspdm_set_mem(void *buffer, size_t length, uint8_t value) +{ + return portMemSet(buffer, value, length); +} + + +/** + * Copies bytes from a source buffer to a destination buffer. + * + * This function copies "src_len" bytes from "src_buf" to "dst_buf". + * + * Asserts and returns a non-zero value if any of the following are true: + * 1) "src_buf" or "dst_buf" are NULL. + * 2) "src_len" or "dst_len" is greater than (SIZE_MAX >> 1). + * 3) "src_len" is greater than "dst_len". + * 4) "src_buf" and "dst_buf" overlap. + * + * If any of these cases fail, a non-zero value is returned. Additionally if + * "dst_buf" points to a non-NULL value and "dst_len" is valid, then "dst_len" + * bytes of "dst_buf" are zeroed. + * + * This function follows the C11 cppreference description of memcpy_s. + * https://en.cppreference.com/w/c/string/byte/memcpy + * The cppreferece description does NOT allow the source or destination + * buffers to be NULL. + * + * This function differs from the Microsoft and Safeclib memcpy_s implementations + * in that the Microsoft and Safeclib implementations allow for NULL source and + * destinations pointers when the number of bytes to copy (src_len) is zero. + * + * In addition the Microsoft and Safeclib memcpy_s functions return different + * negative values on error. For best support, clients should generally check + * against zero for success or failure. + * + * @param dst_buf Destination buffer to copy to. + * @param dst_len Maximum length in bytes of the destination buffer. + * @param src_buf Source buffer to copy from. + * @param src_len The number of bytes to copy from the source buffer. + * + * @return 0 on success. non-zero on error. + * + **/ +int libspdm_copy_mem(void *dst_buf, size_t dst_len, + const void *src_buf, size_t src_len) +{ + volatile void *pRet = NULL; + + /* Check for case where "dst" or "dst_len" may be invalid. + * Do not zero "dst" in this case. */ + if (dst_buf == NULL || dst_len > (SIZE_MAX >> 1)) { + LIBSPDM_ASSERT(0); + return -1; + } + + /* Gaurd against invalid source. Zero "dst" in this case. */ + if (src_buf == NULL) { + LIBSPDM_ASSERT(0); + return -1; + } + + /* Guard against invalid lengths. Zero "dst" in these cases. */ + if (src_len > dst_len || + src_len > (SIZE_MAX >> 1)) { + + LIBSPDM_ASSERT(0); + return -1; + } + + pRet = portMemCopy(dst_buf, dst_len, src_buf, src_len); + + if (pRet == NULL) + { + LIBSPDM_ASSERT(0); + return -1; + } + + return 0; +} + +/** + * Fills a target buffer with zeros, and returns the target buffer. + * + * This function fills length bytes of buffer with zeros, and returns buffer. + * + * If length > 0 and buffer is NULL, then LIBSPDM_ASSERT(). + * If length is greater than (MAX_ADDRESS - buffer + 1), then LIBSPDM_ASSERT(). + * + * @param buffer The pointer to the target buffer to fill with zeros. + * @param length The number of bytes in buffer to fill with zeros. + * + * @return buffer. + * + **/ +void *libspdm_zero_mem(void *buffer, size_t length) +{ + return portMemSet(buffer, 0, length); +} diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/libraries/libspdm/nvidia/nvspdm_rmconfig.h nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/libraries/libspdm/nvidia/nvspdm_rmconfig.h --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/libraries/libspdm/nvidia/nvspdm_rmconfig.h 1970-01-01 00:00:00.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/libraries/libspdm/nvidia/nvspdm_rmconfig.h 2024-03-05 22:14:19.000000000 +0000 @@ -0,0 +1,129 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2022-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef _NVSPDM_RMCONFIG_H_ +#define _NVSPDM_RMCONFIG_H_ + +// +// NOTE: Any updates to macros must first test a local build with LIBSPDM_CHECK_MACRO +// set to 1! This ensures the macro combination is valid. Kept at 0 since adds +// overhead to build otherwise. +// +#define LIBSPDM_CHECK_MACRO 0 + +// +// RM's configuration values for libspdm. Replaces default values in spdm_lib_config.h. +// Must define LIBSPDM_CONFIG in CFLAGS during build in order to successfully replace. +// +#define LIBSPDM_MAX_VERSION_COUNT 5 +#define LIBSPDM_MAX_SESSION_COUNT 1 + +#define LIBSPDM_PSK_CONTEXT_LENGTH LIBSPDM_MAX_HASH_SIZE +#define LIBSPDM_PSK_MAX_HINT_LENGTH 16 + +#define LIBSPDM_MAX_ROOT_CERT_SUPPORT 1 + +#define LIBSPDM_MAX_MEASUREMENT_BLOCK_COUNT 64 +#define LIBSPDM_MAX_MEASUREMENT_RECORD_SIZE 0x1000 + +#define LIBSPDM_MAX_CERT_CHAIN_SIZE 0x1000 +#define LIBSPDM_MAX_CERT_CHAIN_BLOCK_LEN 1024 + +#define LIBSPDM_MAX_MESSAGE_BUFFER_SIZE 0x1100 +#define LIBSPDM_MAX_MESSAGE_SMALL_BUFFER_SIZE 0x100 +#define LIBSPDM_MAX_MESSAGE_MEDIUM_BUFFER_SIZE 0x300 + +// Do not retry messages. +#define LIBSPDM_MAX_REQUEST_RETRY_TIMES 0 + +// We don't expect to use callbacks, nonzero value is required for compilation. +#define LIBSPDM_MAX_SESSION_STATE_CALLBACK_NUM 1 +#define LIBSPDM_MAX_CONNECTION_STATE_CALLBACK_NUM 1 +#define LIBSPDM_MAX_KEY_UPDATE_CALLBACK_NUM 1 + +// CSR's are not supported. +#define LIBSPDM_MAX_CSR_SIZE 0x0 + +// Use running hash over recording all transcript data. +#define LIBSPDM_RECORD_TRANSCRIPT_DATA_SUPPORT 0 + +#define LIBSPDM_ECDSA_SUPPORT 1 +#define LIBSPDM_RSA_SSA_SUPPORT 0 +#define LIBSPDM_RSA_PSS_SUPPORT 0 +#define LIBSPDM_SM2_DSA_SUPPORT 0 +#define LIBSPDM_EDDSA_ED25519_SUPPORT 0 +#define LIBSPDM_EDDSA_ED448_SUPPORT 0 + +#define LIBSPDM_ECDHE_SUPPORT 1 +#define LIBSPDM_FFDHE_SUPPORT 0 +#define LIBSPDM_SM2_KEY_EXCHANGE_SUPPORT 0 + +#define LIBSPDM_AEAD_GCM_SUPPORT 1 +#define LIBSPDM_AEAD_CHACHA20_POLY1305_SUPPORT 0 +#define LIBSPDM_AEAD_SM4_SUPPORT 0 + +#define LIBSPDM_SHA256_SUPPORT 1 +#define LIBSPDM_SHA384_SUPPORT 1 +#define LIBSPDM_SHA512_SUPPORT 0 +#define LIBSPDM_SHA3_256_SUPPORT 0 +#define LIBSPDM_SHA3_384_SUPPORT 0 +#define LIBSPDM_SHA3_512_SUPPORT 0 +#define LIBSPDM_SM3_256_SUPPORT 0 + +#define LIBSPDM_ENABLE_CAPABILITY_CERT_CAP 1 +#define LIBSPDM_ENABLE_CAPABILITY_MEAS_CAP 1 +#define LIBSPDM_ENABLE_CAPABILITY_KEY_EX_CAP 1 +#define LIBSPDM_ENABLE_CAPABILITY_CHAL_CAP 0 +#define LIBSPDM_ENABLE_CAPABILITY_PSK_EX_CAP 0 +#define LIBSPDM_ENABLE_CAPABILITY_HBEAT_CAP 0 +#define LIBSPDM_ENABLE_CAPABILITY_MUT_AUTH_CAP 0 +#define LIBSPDM_ENABLE_CAPABILITY_ENCAP_CAP 0 +#define LIBSPDM_ENABLE_CAPABILITY_GET_CSR_CAP 0 +#define LIBSPDM_ENABLE_CAPABILITY_SET_CERTIFICATE_CAP 0 +#define LIBSPDM_ENABLE_CAPABILITY_CHUNK_CAP 0 + +// Compiler will complain if these deprecated aliases of above macros are not defined. +#define LIBSPDM_ENABLE_CHUNK_CAP 0 +#define LIBSPDM_ENABLE_SET_CERTIFICATE_CAP 0 + +#define LIBSPDM_MAX_SPDM_MSG_SIZE LIBSPDM_MAX_MESSAGE_BUFFER_SIZE +#define LIBSPDM_DATA_TRANSFER_SIZE LIBSPDM_MAX_MESSAGE_BUFFER_SIZE + +#define LIBSPDM_TRANSPORT_ADDITIONAL_SIZE 64 +#define LIBSPDM_SENDER_RECEIVE_BUFFER_SIZE (LIBSPDM_DATA_TRANSFER_SIZE + \ + LIBSPDM_TRANSPORT_ADDITIONAL_SIZE) + +#define LIBSPDM_SCRATCH_BUFFER_SIZE (LIBSPDM_SENDER_RECEIVE_BUFFER_SIZE) + +// +// We want debug asserts enabled, but we don't care about debug prints or the debug blocks. +// Don't define LIBSPDM_DEBUG_ENABLE, as it will override these settings below. +// +#define LIBSPDM_DEBUG_ASSERT_ENABLE 1 +#define LIBSPDM_DEBUG_PRINT_ENABLE 0 +#define LIBSPDM_DEBUG_BLOCK_ENABLE 0 + +// Enable in version 3.0 when we can use to replace transcript WAR. +#define LIBSPDM_ENABLE_MSG_LOG 0 + +#endif // _NVSPDM_RMCONFIG_H_ diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/libraries/libspdm/nvidia/nvspdm_rng.c nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/libraries/libspdm/nvidia/nvspdm_rng.c --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/libraries/libspdm/nvidia/nvspdm_rng.c 1970-01-01 00:00:00.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/libraries/libspdm/nvidia/nvspdm_rng.c 2024-03-05 22:14:19.000000000 +0000 @@ -0,0 +1,48 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2021-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#include "os/os.h" +#include + +/** + * Generates a 64-bit random number. + * + * if rand is NULL, then LIBSPDM_ASSERT(). + * + * @param[out] rand_data buffer pointer to store the 64-bit random value. + * + * @retval true Random number generated successfully. + * @retval false Failed to generate the random number. + * + **/ +bool libspdm_get_random_number_64(uint64_t *rand_data) +{ + NV_STATUS status = NV_ERR_GENERIC; + + if (rand_data == NULL) + { + return false; + } + status = osGetRandomBytes((uint8_t *)rand_data, sizeof(uint64_t)); + return (status == NV_OK); +} diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/libraries/libspdm/nvidia/openspdm.mk nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/libraries/libspdm/nvidia/openspdm.mk --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/libraries/libspdm/nvidia/openspdm.mk 1970-01-01 00:00:00.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/libraries/libspdm/nvidia/openspdm.mk 2024-02-22 04:53:42.000000000 +0000 @@ -0,0 +1,99 @@ +# SPDX-FileCopyrightText: Copyright (c) 2022-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. +# SPDX-License-Identifier: MIT +# +# Permission is hereby granted, free of charge, to any person obtaining a +# copy of this software and associated documentation files (the "Software"), +# to deal in the Software without restriction, including without limitation +# the rights to use, copy, modify, merge, publish, distribute, sublicense, +# and/or sell copies of the Software, and to permit persons to whom the +# Software is furnished to do so, subject to the following conditions: +# +# The above copyright notice and this permission notice shall be included in +# all copies or substantial portions of the Software. +# +# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +# THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER +# LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING +# FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER +# DEALINGS IN THE SOFTWARE. + +# +# Description: This makefile allows for the compilation of the libspdm +# open-source library, in order to implement an SPDM Requester in RM. +# + +LIBSPDM_SOURCES := +LIBSPDM_INCLUDES := +LIBSPDM_DEFINES := +NV_USE_LIBSPDM := 0 + +# Set some common path defines for readability. +LIBSPDM_SOURCE_DIR := src/libraries/libspdm +LIBSPDM_VERSION := 2.3.1 + +# List all files which depend on libspdm headers under LIBSPDM_SOURCES. + +# NVIDIA-authored module code which depends on libspdm headers. +LIBSPDM_SOURCES += src/kernel/gpu/spdm/spdm.c +LIBSPDM_SOURCES += src/kernel/gpu/spdm/arch/hopper/spdm_gh100.c +LIBSPDM_SOURCES += src/kernel/gpu/spdm/arch/hopper/spdm_certs_gh100.c +LIBSPDM_SOURCES += src/kernel/gpu/conf_compute/ccsl.c +LIBSPDM_SOURCES += src/kernel/gpu/conf_compute/arch/hopper/conf_compute_keystore_gh100.c + +# NVIDIA-authored platform code +LIBSPDM_SOURCES += $(LIBSPDM_SOURCE_DIR)/nvidia/nvspdm_crypt_null.c +LIBSPDM_SOURCES += $(LIBSPDM_SOURCE_DIR)/nvidia/nvspdm_debuglib.c +LIBSPDM_SOURCES += $(LIBSPDM_SOURCE_DIR)/nvidia/nvspdm_malloclib.c +LIBSPDM_SOURCES += $(LIBSPDM_SOURCE_DIR)/nvidia/nvspdm_rng.c +LIBSPDM_SOURCES += $(LIBSPDM_SOURCE_DIR)/nvidia/nvspdm_memlib.c + +# libspdm source files +LIBSPDM_SOURCES += $(LIBSPDM_SOURCE_DIR)/$(LIBSPDM_VERSION)/library/spdm_common_lib/libspdm_com_context_data.c +LIBSPDM_SOURCES += $(LIBSPDM_SOURCE_DIR)/$(LIBSPDM_VERSION)/library/spdm_common_lib/libspdm_com_context_data_session.c +LIBSPDM_SOURCES += $(LIBSPDM_SOURCE_DIR)/$(LIBSPDM_VERSION)/library/spdm_common_lib/libspdm_com_crypto_service.c +LIBSPDM_SOURCES += $(LIBSPDM_SOURCE_DIR)/$(LIBSPDM_VERSION)/library/spdm_common_lib/libspdm_com_crypto_service_session.c +LIBSPDM_SOURCES += $(LIBSPDM_SOURCE_DIR)/$(LIBSPDM_VERSION)/library/spdm_common_lib/libspdm_com_msg_log.c +LIBSPDM_SOURCES += $(LIBSPDM_SOURCE_DIR)/$(LIBSPDM_VERSION)/library/spdm_common_lib/libspdm_com_opaque_data.c +LIBSPDM_SOURCES += $(LIBSPDM_SOURCE_DIR)/$(LIBSPDM_VERSION)/library/spdm_common_lib/libspdm_com_support.c +LIBSPDM_SOURCES += $(LIBSPDM_SOURCE_DIR)/$(LIBSPDM_VERSION)/library/spdm_crypt_lib/libspdm_crypt_aead.c +LIBSPDM_SOURCES += $(LIBSPDM_SOURCE_DIR)/$(LIBSPDM_VERSION)/library/spdm_crypt_lib/libspdm_crypt_asym.c +LIBSPDM_SOURCES += $(LIBSPDM_SOURCE_DIR)/$(LIBSPDM_VERSION)/library/spdm_crypt_lib/libspdm_crypt_cert.c +LIBSPDM_SOURCES += $(LIBSPDM_SOURCE_DIR)/$(LIBSPDM_VERSION)/library/spdm_crypt_lib/libspdm_crypt_dhe.c +LIBSPDM_SOURCES += $(LIBSPDM_SOURCE_DIR)/$(LIBSPDM_VERSION)/library/spdm_crypt_lib/libspdm_crypt_hash.c +LIBSPDM_SOURCES += $(LIBSPDM_SOURCE_DIR)/$(LIBSPDM_VERSION)/library/spdm_crypt_lib/libspdm_crypt_hkdf.c +LIBSPDM_SOURCES += $(LIBSPDM_SOURCE_DIR)/$(LIBSPDM_VERSION)/library/spdm_crypt_lib/libspdm_crypt_hmac.c +LIBSPDM_SOURCES += $(LIBSPDM_SOURCE_DIR)/$(LIBSPDM_VERSION)/library/spdm_crypt_lib/libspdm_crypt_rng.c +LIBSPDM_SOURCES += $(LIBSPDM_SOURCE_DIR)/$(LIBSPDM_VERSION)/library/spdm_requester_lib/libspdm_req_common.c +LIBSPDM_SOURCES += $(LIBSPDM_SOURCE_DIR)/$(LIBSPDM_VERSION)/library/spdm_requester_lib/libspdm_req_communication.c +LIBSPDM_SOURCES += $(LIBSPDM_SOURCE_DIR)/$(LIBSPDM_VERSION)/library/spdm_requester_lib/libspdm_req_end_session.c +LIBSPDM_SOURCES += $(LIBSPDM_SOURCE_DIR)/$(LIBSPDM_VERSION)/library/spdm_requester_lib/libspdm_req_finish.c +LIBSPDM_SOURCES += $(LIBSPDM_SOURCE_DIR)/$(LIBSPDM_VERSION)/library/spdm_requester_lib/libspdm_req_get_capabilities.c +LIBSPDM_SOURCES += $(LIBSPDM_SOURCE_DIR)/$(LIBSPDM_VERSION)/library/spdm_requester_lib/libspdm_req_get_certificate.c +LIBSPDM_SOURCES += $(LIBSPDM_SOURCE_DIR)/$(LIBSPDM_VERSION)/library/spdm_requester_lib/libspdm_req_get_digests.c +LIBSPDM_SOURCES += $(LIBSPDM_SOURCE_DIR)/$(LIBSPDM_VERSION)/library/spdm_requester_lib/libspdm_req_get_measurements.c +LIBSPDM_SOURCES += $(LIBSPDM_SOURCE_DIR)/$(LIBSPDM_VERSION)/library/spdm_requester_lib/libspdm_req_get_version.c +LIBSPDM_SOURCES += $(LIBSPDM_SOURCE_DIR)/$(LIBSPDM_VERSION)/library/spdm_requester_lib/libspdm_req_handle_error_response.c +LIBSPDM_SOURCES += $(LIBSPDM_SOURCE_DIR)/$(LIBSPDM_VERSION)/library/spdm_requester_lib/libspdm_req_key_exchange.c +LIBSPDM_SOURCES += $(LIBSPDM_SOURCE_DIR)/$(LIBSPDM_VERSION)/library/spdm_requester_lib/libspdm_req_key_update.c +LIBSPDM_SOURCES += $(LIBSPDM_SOURCE_DIR)/$(LIBSPDM_VERSION)/library/spdm_requester_lib/libspdm_req_negotiate_algorithms.c +LIBSPDM_SOURCES += $(LIBSPDM_SOURCE_DIR)/$(LIBSPDM_VERSION)/library/spdm_requester_lib/libspdm_req_send_receive.c +LIBSPDM_SOURCES += $(LIBSPDM_SOURCE_DIR)/$(LIBSPDM_VERSION)/library/spdm_secured_message_lib/libspdm_secmes_context_data.c +LIBSPDM_SOURCES += $(LIBSPDM_SOURCE_DIR)/$(LIBSPDM_VERSION)/library/spdm_secured_message_lib/libspdm_secmes_encode_decode.c +LIBSPDM_SOURCES += $(LIBSPDM_SOURCE_DIR)/$(LIBSPDM_VERSION)/library/spdm_secured_message_lib/libspdm_secmes_key_exchange.c +LIBSPDM_SOURCES += $(LIBSPDM_SOURCE_DIR)/$(LIBSPDM_VERSION)/library/spdm_secured_message_lib/libspdm_secmes_session.c +LIBSPDM_SOURCES += $(LIBSPDM_SOURCE_DIR)/$(LIBSPDM_VERSION)/os_stub/memlib/compare_mem.c +LIBSPDM_SOURCES += $(LIBSPDM_SOURCE_DIR)/$(LIBSPDM_VERSION)/os_stub/spdm_device_secret_lib_null/lib.c +LIBSPDM_SOURCES += $(LIBSPDM_SOURCE_DIR)/$(LIBSPDM_VERSION)/os_stub/platform_lib_null/watchdog.c +LIBSPDM_SOURCES += $(LIBSPDM_SOURCE_DIR)/$(LIBSPDM_VERSION)/os_stub/platform_lib_null/time_linux.c + +# Add all libspdm include paths required for the above LIBSPDM_SOURCES to LIBSPDM_INCLUDES. +LIBSPDM_INCLUDES += $(LIBSPDM_SOURCE_DIR)/$(LIBSPDM_VERSION)/include +LIBSPDM_INCLUDES += $(LIBSPDM_SOURCE_DIR)/$(LIBSPDM_VERSION)/include/hal +LIBSPDM_INCLUDES += $(LIBSPDM_SOURCE_DIR)/$(LIBSPDM_VERSION)/os_stub/include +LIBSPDM_INCLUDES += $(LIBSPDM_SOURCE_DIR)/$(LIBSPDM_VERSION)/os_stub +LIBSPDM_INCLUDES += $(LIBSPDM_SOURCE_DIR)/nvidia + +# Override the default libspdm configuration with our own. +LIBSPDM_DEFINES += LIBSPDM_CONFIG=\"nvspdm_rmconfig.h\" diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/libraries/mmu/gmmu_fmt.c nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/libraries/mmu/gmmu_fmt.c --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/libraries/mmu/gmmu_fmt.c 2023-10-25 20:21:35.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/libraries/mmu/gmmu_fmt.c 2024-03-05 22:14:19.000000000 +0000 @@ -148,7 +148,7 @@ { NvU32 i, compPageIndex, endCompPageIndex; NvU64 offset = surfOffset; - const NvU32 pageSize = NvU64_LO32(mmuFmtLevelPageSize(pLevel)); + const NvU64 pageSize = mmuFmtLevelPageSize(pLevel); const NV_FIELD_DESC32 *pCtlSubIndexFld = &pFmt->pPte->fldCompTagSubIndex; NvU32 ctlSubIndexMask = 0; NvU32 ctlSubIndexShift = 0; diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/libraries/mmu/mmu_walk.c nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/libraries/mmu/mmu_walk.c --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/libraries/mmu/mmu_walk.c 2023-10-25 20:21:35.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/libraries/mmu/mmu_walk.c 2024-03-05 22:14:20.000000000 +0000 @@ -224,9 +224,12 @@ ) { const MMU_WALK_LEVEL *pLevel = &pWalk->root; - while (pLevel->pFmt != pLevelFmt) + while (pLevel != NULL && pLevel->pFmt != pLevelFmt) { NvU32 subLevel; + + NV_ASSERT_OR_RETURN(pLevel->pFmt != NULL, NULL); + // Single sub-level always continues. if (1 == pLevel->pFmt->numSubLevels) { @@ -302,7 +305,7 @@ NvU32 entryIndexHi = mmuFmtVirtAddrToEntryIndex(pLevel->pFmt, vaHi); NvU32 entryIndex; NvU32 index; - NvU32 entryIndexFillStart; + NvU32 entryIndexFillStart = 0; NvU32 entryIndexFillEnd; NvU32 pendingFillCount = 0; @@ -688,7 +691,7 @@ NvU32 entryIndexHi = mmuFmtVirtAddrToEntryIndex(pLevel->pFmt, vaHi); NvU32 entryIndex; NvU32 index; - NvU32 entryIndexFillStart; + NvU32 entryIndexFillStart = 0; NvU32 entryIndexFillEnd; NvU32 pendingFillCount = 0; @@ -917,10 +920,10 @@ // Acquire root level instance memory. NV_ASSERT_OK_OR_RETURN( _mmuWalkLevelInstAcquire(pWalk, &pWalk->root, vaLo, vaHi, - NV_TRUE, NV_FALSE, bCommit, &bChanged, + NV_TRUE, NV_FALSE, bCommit, &bChanged, &pLevelInst, NV_FALSE /*bInitNv4k*/)); - // We check pLevelInst to catch the corner case, where Commit() is called before PDB allocation. + // We check pLevelInst to catch the corner case, where Commit() is called before PDB allocation. if (bChanged || (bCommit && pLevelInst)) { NvBool bDone; @@ -1065,12 +1068,12 @@ } /** - * @brief Calculate target entry indices that covers VA range for + * @brief Calculate target entry indices that covers VA range for * source entries - * - * @details For example, entry 1 in 64K PT is aligned to 4K PT entry 0 to + * + * @details For example, entry 1 in 64K PT is aligned to 4K PT entry 0 to * 15. 4K PTE 1 to 18 will be covered by 64K PTE 0 to 1. - * + * * It is introduced by NV4K encoding. Updating big page table * according to small page table requires index transfering * @@ -1087,7 +1090,7 @@ const MMU_FMT_LEVEL *pPageFmtIn, const NvU32 indexLoIn, const NvU32 indexHiIn, - const MMU_FMT_LEVEL *pPageFmtOut, + const MMU_FMT_LEVEL *pPageFmtOut, NvU32 *pIndexLoOut, NvU32 *pIndexHiOut ) @@ -1181,29 +1184,29 @@ /** * @brief Resolve upcoming state conflicts before mmu walk operations - * + * * @example Say we are to mmuWalkMap VA range [vaLo, vaHi] on small PT. - * Assume we have 4K PT and 64K PT as our small PT and big PT, and [vaLo, vaHi] + * Assume we have 4K PT and 64K PT as our small PT and big PT, and [vaLo, vaHi] * is a strict subset of VA range covered by BigPTE[1, 3] and SmallPTE[18, 61]. * Let's say BigPTE[1, 3] are sparse right now. - * + * * To resolve the conflict, we need to preserve sparse state for part of the * VA range that is not going to be mapped. We need to move those states from * BigPT to SmallPT. - * + * * Before: * BigPTE[1, 3]: sparse, SmallPTE[16 - 63]: invalid * (BigPTE[1, 3] and SmallPTE[16 - 63] are VA aligned) * After: * BigPTE[1, 3]: invalid, SmallPTE[16 - 17]: sparse * SmallPTE[18 - 61]: invalid, will later be mapped - * SmallPTE[62 - 63]: sparse + * SmallPTE[62 - 63]: sparse * * @example If we are to mmuWalkMap on big PT instead of samll PT, * and sparse state was on small PT, we just need to invalidate the small PTEs. - * + * * Before: - * BigPTE[1, 3]: invalid, + * BigPTE[1, 3]: invalid, * SmallPTE[16 - 63]: sparse * After: * BigPTE[1, 3]: invalid, will later be mapped @@ -1250,7 +1253,7 @@ { entryIndexLo = mmuFmtVirtAddrToEntryIndex(pLevelFmtSmall, clippedVaLo); entryIndexHi = mmuFmtVirtAddrToEntryIndex(pLevelFmtSmall, clippedVaHi); - mmuFmtCalcAlignedEntryIndices(pLevelFmtSmall, entryIndexLo, + mmuFmtCalcAlignedEntryIndices(pLevelFmtSmall, entryIndexLo, entryIndexHi, pLevelFmtBig, &indexLo_Big, &indexHi_Big); mmuFmtCalcAlignedEntryIndices(pLevelFmtBig, indexLo_Big, indexHi_Big, pLevelFmtSmall, &indexLo_Small, &indexHi_Small); @@ -1428,11 +1431,11 @@ const NvU32 entryIndexHi = (pLevelInst->memSize / pLevel->pFmt->entrySize) - 1; NvU32 progress = 0; - // + // // default state for new entries // NV4K for big page table if ATS is enabled - // - MMU_WALK_FILL_STATE newEntryState = bInitNv4k ? MMU_WALK_FILL_NV4K : + // + MMU_WALK_FILL_STATE newEntryState = bInitNv4k ? MMU_WALK_FILL_NV4K : MMU_WALK_FILL_INVALID; NV_ASSERT(NULL != pLevelInst->pMemDesc); @@ -1574,10 +1577,10 @@ } } - // + // // the loop was reversed for NV4K, if there are multiple sublevels // handling small PT first, then the big PT - // + // for (i = numSubLevels; i > 0; --i) { NvBool bChanged = NV_FALSE; @@ -1585,12 +1588,12 @@ NvBool bTarget = (subLevelIdx == subLevel); NvBool bInitNv4k = NV_FALSE; - // + // // If NV4K is required (when ATS is enabled), acquire 64K PT // whenever the 4K PT has been acquired and 64K PT was not // there - // - if (pWalk->flags.bAtsEnabled && subLevelIdx == 0 && + // + if (pWalk->flags.bAtsEnabled && subLevelIdx == 0 && numSubLevels > 1 && !pOpParams->bRelease) { if (pSubLevelInsts[1] != NULL) @@ -1608,7 +1611,7 @@ _mmuWalkLevelInstAcquire(pWalk, pLevel->subLevels + subLevelIdx, vaLo, vaLimit, bTarget, pOpParams->bRelease, pOpParams->bCommit, - &bChanged, &pSubLevelInsts[subLevelIdx], + &bChanged, &pSubLevelInsts[subLevelIdx], bInitNv4k)); if (NULL == pSubLevelInsts[subLevelIdx]) { @@ -1695,7 +1698,7 @@ { if (pWalk->flags.bAtsEnabled) { - if (pSubLevelInsts[0]->numNv4k == + if (pSubLevelInsts[0]->numNv4k == mmuFmtLevelEntryCount(pLevel->subLevels[0].pFmt) && (0 == pSubLevelInsts[0]->numReserved) && (pSubMemDescs[1] == NULL || bChanged == NV_TRUE)) @@ -1703,7 +1706,7 @@ bChanged = NV_TRUE; continue; } - else + else { state = MMU_ENTRY_STATE_IS_PDE; pSubMemDescs[subLevel] = pSubLevelInst->pMemDesc; diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/libraries/mmu/mmu_walk_fill.c nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/libraries/mmu/mmu_walk_fill.c --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/libraries/mmu/mmu_walk_fill.c 2023-10-25 20:21:35.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/libraries/mmu/mmu_walk_fill.c 2024-03-05 22:14:20.000000000 +0000 @@ -29,9 +29,9 @@ static NV_STATUS _mmuWalkPostFillPTETasks ( - const MMU_WALK *pWalk, - MMU_WALK_LEVEL *pLevel, - const NvU32 entryIndexLo, + const MMU_WALK *pWalk, + MMU_WALK_LEVEL *pLevel, + const NvU32 entryIndexLo, const NvU32 entryIndexHi, const MMU_WALK_FILL_STATE fillState, const NvU64 vaLo @@ -41,17 +41,17 @@ /** * @brief Fill a VA range to a constant state for levels below the root. * - * @details This function is of MmuWalkOp function type. Used by + * @details This function is of MmuWalkOp function type. Used by * mmuWalkUnmap and mmuWalkSparsify, which fills INVALID and SPARSE - * states to the target page levels respectively. - * With NV4K introduced with VOLTA ATS, cross PT inconsistency - * during unmapping and sparsifying is handled here. - * - * @todo Recover from failure. It is difficult to do because rollbacks + * states to the target page levels respectively. + * With NV4K introduced with VOLTA ATS, cross PT inconsistency + * during unmapping and sparsifying is handled here. + * + * @todo Recover from failure. It is difficult to do because rollbacks * are costly and complex. Do we really want recovery or asserts? * If the later one, we can replace those recovery codes with * asserts. - * + * * @copydoc MmuWalkCBOpFunc * * @return NV_OK on success @@ -114,7 +114,7 @@ // Clear out the PTEs modulo number of entries in table // We do a modulo of number of entries in the table so that // we do not exceed the allocated sysmem page. - // + // pWalk->pCb->FillEntries(pWalk->pUserCtx, pLevel->pFmt, pWalk->pStagingBuffer, @@ -127,7 +127,7 @@ pWalk->pCb->WriteBuffer(pWalk->pUserCtx, pWalk->pStagingBuffer, pLevelInst->pMemDesc, - entryIndexLo, + entryIndexLo, entryIndexHi, numEntries, pLevel->pFmt->entrySize); @@ -212,14 +212,14 @@ } /** - * @brief Determines if entries indexLo to indexHi (inclusive) are + * @brief Determines if entries indexLo to indexHi (inclusive) are * all invalid. * * @param pLevelInst The level instance * @param[in] indexLo The index lower * @param[in] indexHi The index higher * - * @return True if no level instance or all entries are invalid, + * @return True if no level instance or all entries are invalid, * False otherwise. */ static NvBool @@ -247,13 +247,13 @@ /** * @brief Post PTE filling tasks to handle cross PTs inconsistency - * + * * @details Helper function inside mmuWalkFill PT level to update 64K PTEs - * after mmuWalkFill operation complete. It gathers mmuWalkFill + * after mmuWalkFill operation complete. It gathers mmuWalkFill * target entry index range and fillState as input and update * 64K PTEs accordingly. The function doesn't handle extra page - * table allocations and deallocations. It relies on - * _mmuWalkPdeAcquire and _mmuWalkPdeRelease to prepare and + * table allocations and deallocations. It relies on + * _mmuWalkPdeAcquire and _mmuWalkPdeRelease to prepare and * cleanup page levels accordingly. * * @todo Recovery on failure. Same discussion as in mmuWalkFill. @@ -269,9 +269,9 @@ */ static NV_STATUS _mmuWalkPostFillPTETasks ( - const MMU_WALK *pWalk, - MMU_WALK_LEVEL *pLevel, - const NvU32 entryIndexLo, + const MMU_WALK *pWalk, + MMU_WALK_LEVEL *pLevel, + const NvU32 entryIndexLo, const NvU32 entryIndexHi, const MMU_WALK_FILL_STATE fillState, const NvU64 virtAddr @@ -279,13 +279,13 @@ { const MMU_FMT_LEVEL *pFmtLevel = pLevel->pFmt; - // + // // NV4K is only necessary for ATS // Only update 64K PTEs on invalidation, not on sparsifying - // + // if (pWalk->flags.bAtsEnabled && fillState == MMU_WALK_FILL_INVALID) { - const NvU32 pageSize = NvU64_LO32(mmuFmtLevelPageSize(pFmtLevel)); + const NvU64 pageSize = mmuFmtLevelPageSize(pFmtLevel); NvU32 progress = 0; NvU32 entryIndex = 0; @@ -304,10 +304,10 @@ btreeSearch(vaLevelBase, (NODE**)&pLevel4KInst, (NODE*)pLevel4K->pInstances); - // + // // if 4K page table was modified in mmuWalkFill // check the range and update 64K PTEs accordingly - // + // if (pageSize == 0x1000) { // get involved 64K PTEs and 4K PTEs @@ -327,14 +327,14 @@ // otherwise check the head and tail groups else { - if (indexLo_4K < entryIndexLo && + if (indexLo_4K < entryIndexLo && !_isRangeAllInvalid(pLevel4KInst, indexLo_4K, entryIndexLo - 1)) { indexLo_64K++; } if (indexHi_4K > entryIndexHi && - !_isRangeAllInvalid(pLevel4KInst, entryIndexHi + 1, + !_isRangeAllInvalid(pLevel4KInst, entryIndexHi + 1, indexHi_4K)) { indexHi_64K--; @@ -344,8 +344,8 @@ // update 64K PT given the indexes calculated above if (indexLo_64K <= indexHi_64K) { - pWalk->pCb->FillEntries(pWalk->pUserCtx, pLevel64K->pFmt, - pLevel64KInst->pMemDesc, indexLo_64K, indexHi_64K, + pWalk->pCb->FillEntries(pWalk->pUserCtx, pLevel64K->pFmt, + pLevel64KInst->pMemDesc, indexLo_64K, indexHi_64K, MMU_WALK_FILL_NV4K, &progress); NV_ASSERT_OR_RETURN(progress == indexHi_64K - indexLo_64K + 1, NV_ERR_INVALID_STATE); @@ -353,28 +353,28 @@ for (entryIndex = indexLo_64K; entryIndex <= indexHi_64K; entryIndex++) { - mmuWalkSetEntryState(pLevel64KInst, entryIndex, + mmuWalkSetEntryState(pLevel64KInst, entryIndex, MMU_ENTRY_STATE_NV4K); } } } - // + // // if 64K page table is invalidated in mmuWalkFill // correct the state as NV4K // @todo move this portion to mmuWalkFill - // + // else if (pageSize == 0x10000) { - mmuFmtCalcAlignedEntryIndices(pLevel64K->pFmt, entryIndexLo, + mmuFmtCalcAlignedEntryIndices(pLevel64K->pFmt, entryIndexLo, entryIndexHi, pLevel4K->pFmt, &indexLo_4K, &indexHi_4K); // the 4K PTE should have already been invalid - NV_ASSERT_OR_RETURN(_isRangeAllInvalid(pLevel4KInst, indexLo_4K, + NV_ASSERT_OR_RETURN(_isRangeAllInvalid(pLevel4KInst, indexLo_4K, indexHi_4K), NV_ERR_INVALID_STATE); // Set 64K PTEs NV4K - pWalk->pCb->FillEntries(pWalk->pUserCtx, pLevel64K->pFmt, - pLevel64KInst->pMemDesc, entryIndexLo, entryIndexHi, + pWalk->pCb->FillEntries(pWalk->pUserCtx, pLevel64K->pFmt, + pLevel64KInst->pMemDesc, entryIndexLo, entryIndexHi, MMU_WALK_FILL_NV4K, &progress); NV_ASSERT_OR_RETURN(progress == entryIndexHi - entryIndexLo + 1, NV_ERR_INVALID_STATE); diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/libraries/mmu/mmu_walk_private.h nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/libraries/mmu/mmu_walk_private.h --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/libraries/mmu/mmu_walk_private.h 2023-10-25 20:21:36.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/libraries/mmu/mmu_walk_private.h 2024-03-05 22:14:20.000000000 +0000 @@ -357,7 +357,7 @@ mmuFmtCalcAlignedEntryIndices(const MMU_FMT_LEVEL *pPageFmtIn, const NvU32 indexLoIn, const NvU32 indexHiIn, - const MMU_FMT_LEVEL *pPageFmtOut, + const MMU_FMT_LEVEL *pPageFmtOut, NvU32 *pIndexLoOut, NvU32 *pIndexHiOut); diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/libraries/nvoc/src/runtime.c nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/libraries/nvoc/src/runtime.c --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/libraries/nvoc/src/runtime.c 2023-10-25 20:21:36.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/libraries/nvoc/src/runtime.c 2024-03-05 22:14:21.000000000 +0000 @@ -74,6 +74,34 @@ void objAddChild_IMPL(Object *pObj, Object *pChild) { NV_ASSERT(pChild->pParent == NULL); + +#if defined(DEBUG) + if (pChild->createFlags & NVOC_OBJ_CREATE_FLAGS_IN_PLACE_CONSTRUCT) + { + // + // For objects constructed in place it is possible to call objCreate() twice without calling objDelete() + // This results in a loop in parent's child list, making it endless + // This check is supposed to make catching this issue easier without affecting perf + // + Object *pCurrentChild = pObj->childTree.pChild; + + while (pCurrentChild != NULL) + { + if (pCurrentChild == pChild) + { +#if NV_PRINTF_STRINGS_ALLOWED + portDbgPrintf("NVOC: %s: class %s called in-place objCreate() twice without calling objDelete()", + __FUNCTION__, + objGetClassInfo(pChild)->name); +#endif // NV_PRINTF_STRINGS_ALLOWED + PORT_BREAKPOINT_DEBUG(); + } + + pCurrentChild = pCurrentChild->childTree.pSibling; + } + } +#endif // defined(DEBUG) + pChild->pParent = pObj; pChild->childTree.pSibling = pObj->childTree.pChild; pObj->childTree.pChild = pChild; @@ -116,6 +144,25 @@ return pObj->pParent; } +NV_STATUS __nvoc_handleObjCreateMemAlloc(NvU32 createFlags, NvU32 allocSize, void **ppLocalPtr, void **ppThis) +{ + if (allocSize == 0 || ppThis == NULL || ppLocalPtr == NULL) + return NV_ERR_INVALID_PARAMETER; + + if (createFlags & NVOC_OBJ_CREATE_FLAGS_IN_PLACE_CONSTRUCT) + { + *ppLocalPtr = *ppThis; + } + else + { + *ppLocalPtr = portMemAllocNonPaged(allocSize); + if (*ppLocalPtr == NULL) + return NV_ERR_NO_MEMORY; + } + + return NV_OK; +} + //! Internal backing method for objDelete. void __nvoc_objDelete(Dynamic *pDynamic) { @@ -147,7 +194,8 @@ } pDerivedObj = __nvoc_fullyDerive(pDynamic); - portMemFree(pDerivedObj); + if (!(pObj->createFlags & NVOC_OBJ_CREATE_FLAGS_IN_PLACE_CONSTRUCT)) + portMemFree(pDerivedObj); } //! Internal method to fill out an object's RTTI pointers from a class definition. diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/libraries/nvport/cpu/cpu_common.c nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/libraries/nvport/cpu/cpu_common.c --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/libraries/nvport/cpu/cpu_common.c 2023-10-25 20:21:37.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/libraries/nvport/cpu/cpu_common.c 2024-03-05 22:14:21.000000000 +0000 @@ -46,7 +46,7 @@ if (PORT_CPU_GET_IMC_BAR_DESC_INIT_STATE() == NV_TRUE) { // - // If PORT_CPU_GET_IMC_BAR_DESC_INIT_STATE is true then + // If PORT_CPU_GET_IMC_BAR_DESC_INIT_STATE is true then // portCpuExFreeImcBarDesc will be supported. Adding following check // to avoid compile time issues // diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/libraries/nvport/cpu/cpu_x86_amd64.c nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/libraries/nvport/cpu/cpu_x86_amd64.c --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/libraries/nvport/cpu/cpu_x86_amd64.c 2023-10-25 20:21:37.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/libraries/nvport/cpu/cpu_x86_amd64.c 2024-03-05 22:14:21.000000000 +0000 @@ -53,18 +53,18 @@ portMemSet(cpuInfo, 0, sizeof(cpuInfo)); status = portCpuCpuId(cpuInfo, PORT_CPU_CPUID_STD_FUN_BASIC, PORT_CPU_CPUID_STD_SUBFUN_0); - if (status != NV_OK) + if (status != NV_OK) { PORT_BREAKPOINT_DEBUG(); return status; } - if (function_id > cpuInfo[0]) + if (function_id > cpuInfo[0]) { PORT_BREAKPOINT_DEBUG(); return NV_ERR_NOT_SUPPORTED; } - + return NV_OK; } @@ -74,15 +74,15 @@ NvU32 cpuInfo[4]; NvU32 model; NvU32 family; - - if (pCpuVersion == NULL) + + if (pCpuVersion == NULL) { PORT_BREAKPOINT_DEBUG(); return NV_ERR_INVALID_ARGUMENT; } status = portCpuCheckStdFunSupport(PORT_CPU_CPUID_STD_FUN_VERSION); - if (status != NV_OK) + if (status != NV_OK) { PORT_BREAKPOINT_DEBUG(); return status; @@ -91,7 +91,7 @@ portMemSet(cpuInfo, 0U, sizeof(cpuInfo)); status = portCpuCpuId(cpuInfo, PORT_CPU_CPUID_STD_FUN_VERSION, PORT_CPU_CPUID_STD_SUBFUN_0); - if (status != NV_OK) + if (status != NV_OK) { PORT_BREAKPOINT_DEBUG(); return status; @@ -100,17 +100,17 @@ pCpuVersion->steppingId = PORT_CPU_CPUID_GET_STEPPING_ID(cpuInfo[0]); family = PORT_CPU_CPUID_GET_FAMILY(cpuInfo[0]); model = PORT_CPU_CPUID_GET_MODEL(cpuInfo[0]); - if ((family == 0x0FU) || (family == 0x06U)) + if ((family == 0x0FU) || (family == 0x06U)) { model |= PORT_CPU_CPUID_GET_EXT_MODEL(cpuInfo[0]) << PORT_CPU_CPUID_MODEL_SHIFT; } - - if (family == 0x0FU) + + if (family == 0x0FU) { family += PORT_CPU_CPUID_GET_EXT_FAMILY(cpuInfo[0]); } - + pCpuVersion->family = family; switch (pCpuVersion->family) { @@ -121,7 +121,7 @@ // Unknown famliy, ignore model. break; } - + pCpuVersion->brandIndex = PORT_CPU_CPUID_GET_BRAND_INDEX(cpuInfo[1]); pCpuVersion->localApicId = PORT_CPU_CPUID_GET_LOCAL_APIC_ID(cpuInfo[1]); pCpuVersion->processorType = PORT_CPU_CPUID_GET_PROCESSOR_TYPE(cpuInfo[1]); @@ -135,14 +135,14 @@ NV_STATUS status; NvU32 cpuInfo[4]; - if (pCpuFeatures == NULL) + if (pCpuFeatures == NULL) { PORT_BREAKPOINT_DEBUG(); return NV_ERR_INVALID_ARGUMENT; } status = portCpuCheckStdFunSupport(PORT_CPU_CPUID_STD_FUN_VERSION); - if (status != NV_OK) + if (status != NV_OK) { PORT_BREAKPOINT_DEBUG(); return status; @@ -151,7 +151,7 @@ portMemSet(cpuInfo, 0U, sizeof(cpuInfo)); status = portCpuCpuId(cpuInfo, PORT_CPU_CPUID_STD_FUN_VERSION, PORT_CPU_CPUID_STD_SUBFUN_0); - if (status != NV_OK) + if (status != NV_OK) { PORT_BREAKPOINT_DEBUG(); return status; @@ -276,7 +276,7 @@ pCpuFeatures->TM = PORT_CPU_CPUID_FEATURE_GET_BIT(cpuInfo[3], PORT_CPU_CPUID_FEATURE_TM_BIT); pCpuFeatures->PBE = PORT_CPU_CPUID_FEATURE_GET_BIT(cpuInfo[3], - PORT_CPU_CPUID_FEATURE_PBE_BIT); + PORT_CPU_CPUID_FEATURE_PBE_BIT); return NV_OK; } @@ -286,14 +286,14 @@ NV_STATUS status; NvU32 cpuInfo[4]; - if (pCpuArchPerfMonitor == NULL) + if (pCpuArchPerfMonitor == NULL) { PORT_BREAKPOINT_DEBUG(); return NV_ERR_INVALID_ARGUMENT; } status = portCpuCheckStdFunSupport(PORT_CPU_CPUID_STD_FUN_TPM); - if (status != NV_OK) + if (status != NV_OK) { PORT_BREAKPOINT_DEBUG(); return status; @@ -302,7 +302,7 @@ portMemSet(cpuInfo, 0U, sizeof(cpuInfo)); status = portCpuCpuId(cpuInfo, PORT_CPU_CPUID_STD_FUN_ARCH_PERF_MONITOR, PORT_CPU_CPUID_STD_SUBFUN_0); - if (status != NV_OK) + if (status != NV_OK) { PORT_BREAKPOINT_DEBUG(); return status; @@ -371,13 +371,13 @@ return status; } - pCpuTPMFeatures->DTS = PORT_CPU_CPUID_FEATURE_GET_BIT(cpuInfo[0], + pCpuTPMFeatures->DTS = PORT_CPU_CPUID_FEATURE_GET_BIT(cpuInfo[0], PORT_CPU_CPUID_TPM_FEATURE_DTS_BIT); pCpuTPMFeatures->IntelTurboBoost = PORT_CPU_CPUID_FEATURE_GET_BIT(cpuInfo[0], PORT_CPU_CPUID_TPM_FEATURE_ITB_BIT); - pCpuTPMFeatures->ARAT = PORT_CPU_CPUID_FEATURE_GET_BIT(cpuInfo[0], + pCpuTPMFeatures->ARAT = PORT_CPU_CPUID_FEATURE_GET_BIT(cpuInfo[0], PORT_CPU_CPUID_TPM_FEATURE_ARAT_BIT); - pCpuTPMFeatures->PLN = PORT_CPU_CPUID_FEATURE_GET_BIT(cpuInfo[0], + pCpuTPMFeatures->PLN = PORT_CPU_CPUID_FEATURE_GET_BIT(cpuInfo[0], PORT_CPU_CPUID_TPM_FEATURE_PLN_BIT); pCpuTPMFeatures->ECMD = PORT_CPU_CPUID_FEATURE_GET_BIT(cpuInfo[0], PORT_CPU_CPUID_TPM_FEATURE_ECMD_BIT); @@ -399,21 +399,21 @@ PORT_CPU_CPUID_TPM_FEATURE_ITBMT30_BIT); pCpuTPMFeatures->HWPCapabilities = PORT_CPU_CPUID_FEATURE_GET_BIT(cpuInfo[0], PORT_CPU_CPUID_TPM_FEATURE_HWP_CAPABILITIES_BIT); - pCpuTPMFeatures->HWPPECI = PORT_CPU_CPUID_FEATURE_GET_BIT(cpuInfo[0], + pCpuTPMFeatures->HWPPECI = PORT_CPU_CPUID_FEATURE_GET_BIT(cpuInfo[0], PORT_CPU_CPUID_TPM_FEATURE_HWPPECI_BIT); - pCpuTPMFeatures->FLEXHWP = PORT_CPU_CPUID_FEATURE_GET_BIT(cpuInfo[0], + pCpuTPMFeatures->FLEXHWP = PORT_CPU_CPUID_FEATURE_GET_BIT(cpuInfo[0], PORT_CPU_CPUID_TPM_FEATURE_FLEXHWP_BIT); - pCpuTPMFeatures->FAM = PORT_CPU_CPUID_FEATURE_GET_BIT(cpuInfo[0], + pCpuTPMFeatures->FAM = PORT_CPU_CPUID_FEATURE_GET_BIT(cpuInfo[0], PORT_CPU_CPUID_TPM_FEATURE_FAM_BIT); - pCpuTPMFeatures->ILPHWPRequest = PORT_CPU_CPUID_FEATURE_GET_BIT(cpuInfo[0], + pCpuTPMFeatures->ILPHWPRequest = PORT_CPU_CPUID_FEATURE_GET_BIT(cpuInfo[0], PORT_CPU_CPUID_TPM_FEATURE_ILPHWP_REQUEST_BIT); - pCpuTPMFeatures->NoOfInterruptThresholdsInDTS = + pCpuTPMFeatures->NoOfInterruptThresholdsInDTS = PORT_CPU_CPUID_FEATURE_GET_BIT(cpuInfo[1], PORT_CPU_CPUID_TPM_FEATURE_NFITI_DTS_BIT); - pCpuTPMFeatures->HCFC = PORT_CPU_CPUID_FEATURE_GET_BIT(cpuInfo[2], + pCpuTPMFeatures->HCFC = PORT_CPU_CPUID_FEATURE_GET_BIT(cpuInfo[2], PORT_CPU_CPUID_TPM_FEATURE_HCFC_BIT); - pCpuTPMFeatures->PEBP = PORT_CPU_CPUID_FEATURE_GET_BIT(cpuInfo[2], + pCpuTPMFeatures->PEBP = PORT_CPU_CPUID_FEATURE_GET_BIT(cpuInfo[2], PORT_CPU_CPUID_TPM_FEATURE_PEBP_BIT); return NV_OK; @@ -444,7 +444,7 @@ PORT_BREAKPOINT_DEBUG(); return status; } - + switch (PORT_CPU_EXT_TOPOLOGY_ENUM_GET_LEVEL_TYPE(cpuInfo[2])) { case PORT_CPU_EXT_TOPOLOGY_ENUM_LEVEL_TYPE_SMT: @@ -459,11 +459,11 @@ cond = NV_FALSE; break; } - + pCpuInfo->physicalCoreCount = pCpuInfo->logicalCoreCount / pCpuInfo->threadCountPerCore; sub++; } while (cond == NV_TRUE); - + return NV_OK; } diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/libraries/nvport/cpu/cpu_x86_amd64.h nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/libraries/nvport/cpu/cpu_x86_amd64.h --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/libraries/nvport/cpu/cpu_x86_amd64.h 2023-10-25 20:21:37.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/libraries/nvport/cpu/cpu_x86_amd64.h 2024-03-05 22:14:22.000000000 +0000 @@ -86,7 +86,7 @@ #define PORT_CPU_CPUID_STEPPING_ID_SHIFT 0U #define PORT_CPU_CPUID_GET_STEPPING_ID(a) ((a) \ & 0x0000000FU) - + #define PORT_CPU_CPUID_MODEL_MASK 0x000000F0U #define PORT_CPU_CPUID_MODEL_SHIFT 4U #define PORT_CPU_CPUID_GET_MODEL(a) (((a) \ @@ -131,30 +131,30 @@ & 0xFF000000U)\ >> 24U) -#define PORT_CPU_CPUID_FEATURE_SSE3_BIT (1U << 0U) -#define PORT_CPU_CPUID_FEATURE_PCLMULQDQ_BIT (1U << 1U) +#define PORT_CPU_CPUID_FEATURE_SSE3_BIT (1U << 0U) +#define PORT_CPU_CPUID_FEATURE_PCLMULQDQ_BIT (1U << 1U) #define PORT_CPU_CPUID_FEATURE_DTES64_BIT (1U << 2U) -#define PORT_CPU_CPUID_FEATURE_MONITOR_BIT (1U << 3U) -#define PORT_CPU_CPUID_FEATURE_DSCPL_BIT (1U << 4U) +#define PORT_CPU_CPUID_FEATURE_MONITOR_BIT (1U << 3U) +#define PORT_CPU_CPUID_FEATURE_DSCPL_BIT (1U << 4U) #define PORT_CPU_CPUID_FEATURE_VMX_BIT (1U << 5U) #define PORT_CPU_CPUID_FEATURE_SMX_BIT (1U << 6U) -#define PORT_CPU_CPUID_FEATURE_EIST_BIT (1U << 7U) +#define PORT_CPU_CPUID_FEATURE_EIST_BIT (1U << 7U) #define PORT_CPU_CPUID_FEATURE_TM2_BIT (1U << 8U) #define PORT_CPU_CPUID_FEATURE_SSSE3_BIT (1U << 9U) -#define PORT_CPU_CPUID_FEATURE_CNXTID_BIT (1U << 10U) +#define PORT_CPU_CPUID_FEATURE_CNXTID_BIT (1U << 10U) #define PORT_CPU_CPUID_FEATURE_SDBG_BIT (1U << 11U) #define PORT_CPU_CPUID_FEATURE_FMA_BIT (1U << 12U) -#define PORT_CPU_CPUID_FEATURE_CMPXCHG16B_BIT (1U << 13U) -#define PORT_CPU_CPUID_FEATURE_XTPRUPDATECONTROL_BIT (1U << 14U) -#define PORT_CPU_CPUID_FEATURE_PDCM_BIT (1U << 15U) +#define PORT_CPU_CPUID_FEATURE_CMPXCHG16B_BIT (1U << 13U) +#define PORT_CPU_CPUID_FEATURE_XTPRUPDATECONTROL_BIT (1U << 14U) +#define PORT_CPU_CPUID_FEATURE_PDCM_BIT (1U << 15U) #define PORT_CPU_CPUID_FEATURE_PCID_BIT (1U << 17U) -#define PORT_CPU_CPUID_FEATURE_DCA_BIT (1U << 18U) +#define PORT_CPU_CPUID_FEATURE_DCA_BIT (1U << 18U) #define PORT_CPU_CPUID_FEATURE_SSE41_BIT (1U << 19U) -#define PORT_CPU_CPUID_FEATURE_SSE42_BIT (1U << 20U) -#define PORT_CPU_CPUID_FEATURE_x2APIC_BIT (1U << 21U) +#define PORT_CPU_CPUID_FEATURE_SSE42_BIT (1U << 20U) +#define PORT_CPU_CPUID_FEATURE_x2APIC_BIT (1U << 21U) #define PORT_CPU_CPUID_FEATURE_MOVBE_BIT (1U << 22U) #define PORT_CPU_CPUID_FEATURE_POPCNT_BIT (1U << 23U) -#define PORT_CPU_CPUID_FEATURE_TSCDEADLINE_BIT (1U << 24U) +#define PORT_CPU_CPUID_FEATURE_TSCDEADLINE_BIT (1U << 24U) #define PORT_CPU_CPUID_FEATURE_AES_BIT (1U << 25U) #define PORT_CPU_CPUID_FEATURE_XSAVE_BIT (1U << 26U) #define PORT_CPU_CPUID_FEATURE_OSXSAVE_BIT (1U << 27U) @@ -164,30 +164,30 @@ #define PORT_CPU_CPUID_FEATURE_FPU_BIT (1U << 0U) #define PORT_CPU_CPUID_FEATURE_VME_BIT (1U << 1U) -#define PORT_CPU_CPUID_FEATURE_DE_BIT (1U << 2U) -#define PORT_CPU_CPUID_FEATURE_PSE_BIT (1U << 3U) +#define PORT_CPU_CPUID_FEATURE_DE_BIT (1U << 2U) +#define PORT_CPU_CPUID_FEATURE_PSE_BIT (1U << 3U) #define PORT_CPU_CPUID_FEATURE_TSC_BIT (1U << 4U) -#define PORT_CPU_CPUID_FEATURE_MSR_BIT (1U << 5U) +#define PORT_CPU_CPUID_FEATURE_MSR_BIT (1U << 5U) #define PORT_CPU_CPUID_FEATURE_PAE_BIT (1U << 6U) #define PORT_CPU_CPUID_FEATURE_MCE_BIT (1U << 7U) #define PORT_CPU_CPUID_FEATURE_CX8_BIT (1U << 8U) -#define PORT_CPU_CPUID_FEATURE_APIC_BIT (1U << 9U) +#define PORT_CPU_CPUID_FEATURE_APIC_BIT (1U << 9U) #define PORT_CPU_CPUID_FEATURE_SEP_BIT (1U << 11U) -#define PORT_CPU_CPUID_FEATURE_MTRR_BIT (1U << 12U) -#define PORT_CPU_CPUID_FEATURE_PGE_BIT (1U << 13U) +#define PORT_CPU_CPUID_FEATURE_MTRR_BIT (1U << 12U) +#define PORT_CPU_CPUID_FEATURE_PGE_BIT (1U << 13U) #define PORT_CPU_CPUID_FEATURE_MCA_BIT (1U << 14U) -#define PORT_CPU_CPUID_FEATURE_CMOV_BIT (1U << 15U) +#define PORT_CPU_CPUID_FEATURE_CMOV_BIT (1U << 15U) #define PORT_CPU_CPUID_FEATURE_PAT_BIT (1U << 16U) -#define PORT_CPU_CPUID_FEATURE_PSE36_BIT (1U << 17U) -#define PORT_CPU_CPUID_FEATURE_PSN_BIT (1U << 18U) +#define PORT_CPU_CPUID_FEATURE_PSE36_BIT (1U << 17U) +#define PORT_CPU_CPUID_FEATURE_PSN_BIT (1U << 18U) #define PORT_CPU_CPUID_FEATURE_CLFSH_BIT (1U << 19U) -#define PORT_CPU_CPUID_FEATURE_DS_BIT (1U << 21U) +#define PORT_CPU_CPUID_FEATURE_DS_BIT (1U << 21U) #define PORT_CPU_CPUID_FEATURE_ACPI_BIT (1U << 22U) -#define PORT_CPU_CPUID_FEATURE_MMX_BIT (1U << 23U) -#define PORT_CPU_CPUID_FEATURE_FXSR_BIT (1U << 24U) -#define PORT_CPU_CPUID_FEATURE_SSE_BIT (1U << 25U) +#define PORT_CPU_CPUID_FEATURE_MMX_BIT (1U << 23U) +#define PORT_CPU_CPUID_FEATURE_FXSR_BIT (1U << 24U) +#define PORT_CPU_CPUID_FEATURE_SSE_BIT (1U << 25U) #define PORT_CPU_CPUID_FEATURE_SSE2_BIT (1U << 26U) -#define PORT_CPU_CPUID_FEATURE_SS_BIT (1U << 27U) +#define PORT_CPU_CPUID_FEATURE_SS_BIT (1U << 27U) #define PORT_CPU_CPUID_FEATURE_HTT_BIT (1U << 28U) #define PORT_CPU_CPUID_FEATURE_TM_BIT (1U << 29U) #define PORT_CPU_CPUID_FEATURE_PBE_BIT (1U << 31U) @@ -209,7 +209,7 @@ #define PORT_CPU_CPUID_TPM_FEATURE_HWPPECI_BIT (1U << 15U) #define PORT_CPU_CPUID_TPM_FEATURE_FLEXHWP_BIT (1U << 16U) #define PORT_CPU_CPUID_TPM_FEATURE_FAM_BIT (1U << 17U) -#define PORT_CPU_CPUID_TPM_FEATURE_ILPHWP_REQUEST_BIT (1U << 18U) +#define PORT_CPU_CPUID_TPM_FEATURE_ILPHWP_REQUEST_BIT (1U << 18U) #define PORT_CPU_CPUID_TPM_FEATURE_NFITI_DTS_BIT (1U << 0U) @@ -223,7 +223,7 @@ // Bits 7:0 of CPUID.0AH.EAX indicate the version of the Performance Monitor #define PORT_CPU_ARCH_PERF_MONITOR_VERSION_ID(a) ((a) & 0xFFU) // -// Bits 15:8 of CPUID.0AH.EAX indicate the number of performance +// Bits 15:8 of CPUID.0AH.EAX indicate the number of performance // counters available on the logical processor // #define PORT_CPU_ARCH_PERF_MONITOR_COUNTERS(a) (((a) & 0xFF00U)\ diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/libraries/nvport/crypto/crypto_random_xorshift.c nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/libraries/nvport/crypto/crypto_random_xorshift.c --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/libraries/nvport/crypto/crypto_random_xorshift.c 2023-10-25 20:21:37.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/libraries/nvport/crypto/crypto_random_xorshift.c 2024-03-05 22:14:22.000000000 +0000 @@ -47,9 +47,9 @@ */ #define XORSHIFT_STATE_QWORDS 2 -struct PORT_CRYPTO_PRNG -{ - NvU64 state[XORSHIFT_STATE_QWORDS]; +struct PORT_CRYPTO_PRNG +{ + NvU64 state[XORSHIFT_STATE_QWORDS]; }; PORT_CRYPTO_PRNG *portCryptoDefaultGenerator; @@ -83,10 +83,10 @@ /** * @brief Initializes a xorshift state from a 64bit seed. Performed using a * splitmix64 PRNG. - * + * * Adapted from: https://xorshift.di.unimi.it/splitmix64.c */ -static void _initState(NvU64 seed64, NvU64 state[XORSHIFT_STATE_QWORDS]) +static void _initState(NvU64 seed64, NvU64 state[XORSHIFT_STATE_QWORDS]) { NvU32 i; for (i = 0; i < XORSHIFT_STATE_QWORDS; i++) @@ -103,14 +103,14 @@ * * Adapted from: https://xorshift.di.unimi.it/xorshift128plus.c */ -static NvU64 _xorshift128plus_GetU64(NvU64 state[2]) +static NvU64 _xorshift128plus_GetU64(NvU64 state[2]) { NvU64 s1 = state[0]; const NvU64 s0 = state[1]; state[0] = s0; s1 ^= s1 << 23; // a state[1] = s1 ^ s0 ^ (s1 >> 18) ^ (s0 >> 5); // b, c - return state[1] + s0; + return state[1] + s0; } PORT_CRYPTO_PRNG *portCryptoPseudoRandomGeneratorCreate(NvU64 seed) @@ -124,7 +124,7 @@ return pPrng; } -void portCryptoPseudoRandomGeneratorDestroy(PORT_CRYPTO_PRNG *pPrng) +void portCryptoPseudoRandomGeneratorDestroy(PORT_CRYPTO_PRNG *pPrng) { portMemFree(pPrng); } @@ -150,7 +150,7 @@ * we cannot fill the misaligned section first, then copy aligned qwords, * and then fill the remainder - That way we lose some bytes */ - + // Maybe require 64bit alignment for buffers: // PORT_ASSERT_CHECKED(portUtilCheckAlignment(pBuffer, sizeof(NvU64))); diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/libraries/nvport/memory/memory_tracking.c nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/libraries/nvport/memory/memory_tracking.c --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/libraries/nvport/memory/memory_tracking.c 2023-10-25 20:21:37.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/libraries/nvport/memory/memory_tracking.c 2024-03-05 22:14:22.000000000 +0000 @@ -60,17 +60,17 @@ #else // // We can just stub out the atomic operations for non-atomic ones and not waste -// waste cycles on synchronization +// cycles on synchronization // -#define PORT_MEM_ATOMIC_ADD_SIZE(pVal, val) (*((NvSPtr *)pVal) += val) -#define PORT_MEM_ATOMIC_SUB_SIZE(pVal, val) (*((NvSPtr *)pVal) -= val) -#define PORT_MEM_ATOMIC_DEC_U32(pVal) (--(*((NvU32 *)pVal))) -#define PORT_MEM_ATOMIC_INC_U32(pVal) (++(*((NvU32 *)pVal))) -#define PORT_MEM_ATOMIC_SET_U32(pVal, val) (*((NvU32 *)pVal) = val) +#define PORT_MEM_ATOMIC_ADD_SIZE(pVal, val) (*((volatile NvSPtr *)pVal) += val) +#define PORT_MEM_ATOMIC_SUB_SIZE(pVal, val) (*((volatile NvSPtr *)pVal) -= val) +#define PORT_MEM_ATOMIC_DEC_U32(pVal) (--(*((volatile NvU32 *)pVal))) +#define PORT_MEM_ATOMIC_INC_U32(pVal) (++(*((volatile NvU32 *)pVal))) +#define PORT_MEM_ATOMIC_SET_U32(pVal, val) (*((volatile NvU32 *)pVal) = val) #define PORT_MEM_ATOMIC_CAS_SIZE(pVal, newVal, oldVal) \ - ((*pVal == oldVal) ? ((*((NvSPtr *)pVal) = newVal), NV_TRUE) : NV_FALSE) + ((*pVal == oldVal) ? ((*((volatile NvSPtr *)pVal) = newVal), NV_TRUE) : NV_FALSE) #define PORT_MEM_ATOMIC_CAS_U32(pVal, newVal, oldVal) \ - ((*pVal == oldVal) ? ((*((NvU32 *)pVal) = newVal), NV_TRUE) : NV_FALSE) + ((*pVal == oldVal) ? ((*((volatile NvU32 *)pVal) = newVal), NV_TRUE) : NV_FALSE) #endif // !PORT_MEM_THREAD_SAFE_ALLOCATIONS struct PORT_MEM_ALLOCATOR_IMPL @@ -156,12 +156,67 @@ PORT_MEM_LOCK_RELEASE(lock); \ } while (0) - +// +// All memory tracking globals are contained in this structure +// +static struct PORT_MEM_GLOBALS +{ + PORT_MEM_ALLOCATOR_TRACKING mainTracking; + void *trackingLock; + struct + { + PORT_MEM_ALLOCATOR paged; + PORT_MEM_ALLOCATOR nonPaged; + PORT_MEM_ALLOCATOR_IMPL pagedImpl; + PORT_MEM_ALLOCATOR_IMPL nonPagedImpl; + } alloc; + NvU32 initCount; + NvU32 totalAllocators; +#if PORT_MEM_TRACK_USE_LIMIT + NvBool bLimitEnabled; + NvLength limitPid[PORT_MEM_LIMIT_MAX_PIDS]; + NvLength counterPid[PORT_MEM_LIMIT_MAX_PIDS]; +#endif +} portMemGlobals; // // Memory counter implementation // #if PORT_MEM_TRACK_USE_COUNTER +#if PORT_MEM_TRACK_ALLOC_SIZE +static NV_INLINE NvLength +_portMemExTrackingGetAllocUsableSizeWrapper +( + void *pMem +) +{ +#if PORT_IS_FUNC_SUPPORTED(portMemExTrackingGetAllocUsableSize) + // + // blockSize in PORT_MEM_HEADER does not include the size of the header/ + // footer, but the underlying malloc implementation doesn't know about + // those. Account for them here. + // + NvLength allocSize = portMemExTrackingGetAllocUsableSize(PORT_MEM_SUB_HEADER_PTR(pMem)); + PORT_ASSERT_CHECKED(allocSize > PORT_MEM_STAGING_SIZE); + return allocSize - PORT_MEM_STAGING_SIZE; +#elif PORT_MEM_HEADER_HAS_BLOCK_SIZE + return PORT_MEM_SUB_HEADER_PTR(pMem)->blockSize; +#endif +} +static NV_INLINE void +_portMemExTrackingSetOrGetAllocUsableSize +( + void *pMem, + NvLength *pSize +) +{ +#if PORT_MEM_HEADER_HAS_BLOCK_SIZE + PORT_MEM_SUB_HEADER_PTR(pMem)->blockSize = *pSize; +#else + *pSize = _portMemExTrackingGetAllocUsableSizeWrapper(pMem); +#endif +} +#endif // PORT_MEM_TRACK_ALLOC_SIZE static NV_INLINE void _portMemCounterInit ( @@ -182,49 +237,72 @@ activeAllocs = PORT_MEM_ATOMIC_INC_U32(&pCounter->activeAllocs); PORT_MEM_ATOMIC_INC_U32(&pCounter->totalAllocs); -#if PORT_MEM_TRACK_USE_FENCEPOSTS +#if PORT_MEM_TRACK_ALLOC_SIZE + // + // activeSize is only tracked on configurations where we can retrieve the + // allocation size from allocation metadata in _portMemCounterDec. + // activeSize = PORT_MEM_ATOMIC_ADD_SIZE(&pCounter->activeSize, size); #endif + + // + // Note: this can overflow on 32-bit platforms if we exceed 4GB cumulative + // allocations. It's not trivial to fix, since NvPort doesn't emulate 64-bit + // atomics on 32-bit platforms, so just assume this doesn't happen (or + // doesn't matter too much if it does, since it's only for reporting). + // PORT_MEM_ATOMIC_ADD_SIZE(&pCounter->totalSize, size); - // Atomically compare the peak value with the active, and update if greater. - while (1) - { - NvU32 peakAllocs = pCounter->peakAllocs; - if (activeAllocs <= peakAllocs) - break; - PORT_MEM_ATOMIC_CAS_U32(&pCounter->peakAllocs, activeAllocs, peakAllocs); - } - while (1) + // Update the peak stats, if we're updating the peakSize { + NvU32 peakAllocs; NvLength peakSize = pCounter->peakSize; - if (activeSize <= peakSize) - break; - PORT_MEM_ATOMIC_CAS_SIZE(&pCounter->peakSize, activeSize, peakSize); + while (activeSize > peakSize) + { + PORT_MEM_ATOMIC_CAS_SIZE(&pCounter->peakSize, activeSize, peakSize); + peakSize = pCounter->peakSize; + } + + // + // Ensure peakAllocs stays (approximately) in sync with peakSize, rather + // than always taking the greatest peakAllocs, so that the peak stats + // report is consistent. + // + do + { + peakAllocs = pCounter->peakAllocs; + + // + // Only attempt to update the peakAllocs if activeSize is still the + // peakSize. + // + if (activeSize != pCounter->peakSize) + break; + } while (!PORT_MEM_ATOMIC_CAS_U32(&pCounter->peakAllocs, activeAllocs, peakAllocs)); } } static NV_INLINE void _portMemCounterDec ( PORT_MEM_COUNTER *pCounter, - void *pMem + NvLength size ) { - PORT_UNREFERENCED_VARIABLE(pMem); PORT_MEM_ATOMIC_DEC_U32(&pCounter->activeAllocs); -#if PORT_MEM_TRACK_USE_FENCEPOSTS - PORT_MEM_ATOMIC_SUB_SIZE(&pCounter->activeSize, - ((PORT_MEM_HEADER *)pMem-1)->fence.blockSize); +#if PORT_MEM_TRACK_ALLOC_SIZE + PORT_MEM_ATOMIC_SUB_SIZE(&pCounter->activeSize, size); +#else + PORT_UNREFERENCED_VARIABLE(size); #endif } #define PORT_MEM_COUNTER_INIT(pCounter) _portMemCounterInit(pCounter) #define PORT_MEM_COUNTER_INC(pCounter, size) _portMemCounterInc(pCounter, size) -#define PORT_MEM_COUNTER_DEC(pCounter, pMem) _portMemCounterDec(pCounter, pMem) +#define PORT_MEM_COUNTER_DEC(pCounter, size) _portMemCounterDec(pCounter, size) #else #define PORT_MEM_COUNTER_INIT(x) -#define PORT_MEM_COUNTER_INC(x, y) -#define PORT_MEM_COUNTER_DEC(x, y) +#define PORT_MEM_COUNTER_INC(x, y) PORT_UNREFERENCED_VARIABLE(y) +#define PORT_MEM_COUNTER_DEC(x, y) PORT_UNREFERENCED_VARIABLE(y) #endif // COUNTER @@ -247,7 +325,6 @@ PORT_MEM_FOOTER *pTail = (PORT_MEM_FOOTER*)((NvU8*)pMem + size); pHead->fence.pAllocator = pAlloc; - pHead->fence.blockSize = size; pHead->fence.magic = PORT_MEM_FENCE_HEAD_MAGIC; pTail->fence.magic = PORT_MEM_FENCE_TAIL_MAGIC; } @@ -256,12 +333,12 @@ _portMemFenceCheck ( PORT_MEM_ALLOCATOR *pAlloc, - void *pMem + void *pMem, + NvLength size ) { PORT_MEM_HEADER *pHead = (PORT_MEM_HEADER*)pMem - 1; - PORT_MEM_FOOTER *pTail = (PORT_MEM_FOOTER*) - ((NvU8*)pMem + pHead->fence.blockSize); + PORT_MEM_FOOTER *pTail = (PORT_MEM_FOOTER*)((NvU8*)pMem + size); if (pHead->fence.magic != PORT_MEM_FENCE_HEAD_MAGIC || pTail->fence.magic != PORT_MEM_FENCE_TAIL_MAGIC) @@ -279,11 +356,11 @@ } } -#define PORT_MEM_FENCE_CHECK(pAlloc, pMem) _portMemFenceCheck(pAlloc, pMem) -#define PORT_MEM_FENCE_INIT(pAlloc, pMem, size) _portMemFenceInit(pAlloc, pMem, size) +#define PORT_MEM_FENCE_CHECK(pAlloc, pMem, size) _portMemFenceCheck(pAlloc, pMem, size) +#define PORT_MEM_FENCE_INIT(pAlloc, pMem, size) _portMemFenceInit(pAlloc, pMem, size) #else #define PORT_MEM_FENCE_INIT(x, y, z) -#define PORT_MEM_FENCE_CHECK(x, y) +#define PORT_MEM_FENCE_CHECK(x, y, z) #endif // FENCEPOSTS @@ -409,7 +486,7 @@ { NvP64 address; NvP64 allocator; - NvU64 size; // if size is 0, it is a free() call, not alloc() + NvLength size; // if size is 0, it is a free() call, not alloc() } PORT_MEM_LOG_ENTRY; #define PORT_MEM_TRACK_LOG_TAG 0x70726d74 @@ -481,8 +558,8 @@ static void *_portMemAllocatorAllocExistingWrapper(PORT_MEM_ALLOCATOR *pAlloc, NvLength length); static void _portMemAllocatorFreeExistingWrapper(PORT_MEM_ALLOCATOR *pAlloc, void *pMem); -static void _portMemTrackingRelease(PORT_MEM_ALLOCATOR_TRACKING *pTracking); -static void _portMemTrackAlloc(PORT_MEM_ALLOCATOR_TRACKING *pTracking, void *pMem, NvLength size PORT_MEM_CALLERINFO_COMMA_TYPE_PARAM); +static void _portMemTrackingRelease(PORT_MEM_ALLOCATOR_TRACKING *pTracking, NvBool bReportLeaks); +static void _portMemTrackAlloc(PORT_MEM_ALLOCATOR_TRACKING *pTracking, void *pMem, NvLength size, NvU32 pid PORT_MEM_CALLERINFO_COMMA_TYPE_PARAM); static void _portMemTrackFree(PORT_MEM_ALLOCATOR_TRACKING *pTracking, void *pMem); @@ -508,34 +585,11 @@ #endif // -// All memory tracking globals are contained in this structure -// -static struct PORT_MEM_GLOBALS -{ - PORT_MEM_ALLOCATOR_TRACKING mainTracking; - void *trackingLock; - struct - { - PORT_MEM_ALLOCATOR paged; - PORT_MEM_ALLOCATOR nonPaged; - PORT_MEM_ALLOCATOR_IMPL pagedImpl; - PORT_MEM_ALLOCATOR_IMPL nonPagedImpl; - } alloc; - NvU32 initCount; - NvU32 totalAllocators; -#if PORT_MEM_TRACK_USE_LIMIT - NvBool bLimitEnabled; - NvU64 limitPid[PORT_MEM_LIMIT_MAX_PIDS]; - NvU64 counterPid[PORT_MEM_LIMIT_MAX_PIDS]; -#endif -} portMemGlobals; - -// // Per-process heap limiting implementation // #if PORT_MEM_TRACK_USE_LIMIT static NV_INLINE void -_portMemLimitInc(NvU32 pid, void *pMem, NvU64 size) +_portMemLimitInc(NvU32 pid, void *pMem, NvLength size) { PORT_MEM_HEADER *pMemHeader = PORT_MEM_SUB_HEADER_PTR(pMem); pMemHeader->pid = pid; @@ -544,14 +598,13 @@ if ((pid > 0) && (pid <= PORT_MEM_LIMIT_MAX_PIDS)) { NvU32 pidIdx = pid - 1; - pMemHeader->blockSize = size; PORT_MEM_ATOMIC_ADD_SIZE(&portMemGlobals.counterPid[pidIdx], size); } } } static NV_INLINE void -_portMemLimitDec(void *pMem) +_portMemLimitDec(void *pMem, NvLength size) { if (portMemGlobals.bLimitEnabled) { @@ -561,21 +614,21 @@ if ((pid > 0) && (pid <= PORT_MEM_LIMIT_MAX_PIDS)) { NvU32 pidIdx = pid - 1; - if (portMemGlobals.counterPid[pidIdx] < pMemHeader->blockSize) + if (portMemGlobals.counterPid[pidIdx] < size) { PORT_MEM_PRINT_ERROR("memory free error: counter underflow\n"); PORT_BREAKPOINT_CHECKED(); } else { - PORT_MEM_ATOMIC_SUB_SIZE(&portMemGlobals.counterPid[pidIdx], pMemHeader->blockSize); + PORT_MEM_ATOMIC_SUB_SIZE(&portMemGlobals.counterPid[pidIdx], size); } } } } static NV_INLINE NvBool -_portMemLimitExceeded(NvU32 pid, NvU64 size) +_portMemLimitExceeded(NvU32 pid, NvLength size) { NvBool bExceeded = NV_FALSE; @@ -586,7 +639,7 @@ NvU32 pidIdx = pid - 1; if ((size + portMemGlobals.counterPid[pidIdx]) > portMemGlobals.limitPid[pidIdx]) { - PORT_MEM_PRINT_ERROR("memory allocation denied; PID %d exceeded per-process heap limit of 0x%llx\n", + PORT_MEM_PRINT_ERROR("memory allocation denied; PID %d exceeded per-process heap limit of %"NvUPtr_fmtu"\n", pid, portMemGlobals.limitPid[pidIdx]); bExceeded = NV_TRUE; } @@ -596,11 +649,20 @@ } #define PORT_MEM_LIMIT_INC(pid, pMem, size) _portMemLimitInc(pid, pMem, size) -#define PORT_MEM_LIMIT_DEC(pMem) _portMemLimitDec(pMem) +#define PORT_MEM_LIMIT_DEC(pMem, size) _portMemLimitDec(pMem, size) #define PORT_MEM_LIMIT_EXCEEDED(pid, size) _portMemLimitExceeded(pid, size) #else -#define PORT_MEM_LIMIT_INC(pid, pMem, size) -#define PORT_MEM_LIMIT_DEC(pMem) +#define PORT_MEM_LIMIT_INC(pid, pMem, size) \ + do { \ + PORT_UNREFERENCED_VARIABLE(pid); \ + PORT_UNREFERENCED_VARIABLE(pMem); \ + PORT_UNREFERENCED_VARIABLE(size); \ + } while (0) +#define PORT_MEM_LIMIT_DEC(pMem, size) \ + do { \ + PORT_UNREFERENCED_VARIABLE(pMem); \ + PORT_UNREFERENCED_VARIABLE(size); \ + } while (0) #define PORT_MEM_LIMIT_EXCEEDED(pid, size) (NV_FALSE) #endif // PORT_MEM_TRACK_USE_LIMIT @@ -649,6 +711,11 @@ if (PORT_MEM_TRACK_USE_FENCEPOSTS) { + // + // Distinct paged and non-paged allocators require PORT_MEM_TRACK_USE_FENCEPOSTS + // so that the correct allocator can be looked up from the fenceposts in the + // portMemFree path. + // portMemGlobals.alloc.paged.pImpl = &portMemGlobals.alloc.pagedImpl; portMemGlobals.alloc.nonPaged.pImpl = &portMemGlobals.alloc.nonPagedImpl; @@ -682,19 +749,19 @@ #if (PORT_MEM_TRACK_PRINT_LEVEL > PORT_MEM_TRACK_PRINT_LEVEL_SILENT) if (!bForceSilent) { - portMemPrintTrackingInfo(NULL); + portMemPrintAllTrackingInfo(); } #endif PORT_MEM_LOG_DESTROY(); if (PORT_MEM_TRACK_USE_FENCEPOSTS) { - _portMemTrackingRelease(&portMemGlobals.alloc.nonPaged.pImpl->tracking); - _portMemTrackingRelease(&portMemGlobals.alloc.paged.pImpl->tracking); + _portMemTrackingRelease(&portMemGlobals.alloc.nonPaged.pImpl->tracking, NV_FALSE); + _portMemTrackingRelease(&portMemGlobals.alloc.paged.pImpl->tracking, NV_FALSE); } else { - _portMemTrackingRelease(&portMemGlobals.alloc.pagedImpl.tracking); + _portMemTrackingRelease(&portMemGlobals.alloc.pagedImpl.tracking, NV_FALSE); } PORT_MEM_LOCK_DESTROY(portMemGlobals.trackingLock); @@ -702,7 +769,6 @@ portMemSet(&portMemGlobals, 0, sizeof(portMemGlobals)); } - void * portMemAllocPaged ( @@ -835,7 +901,7 @@ PORT_BREAKPOINT_CHECKED(); return; } - _portMemTrackingRelease(pAllocator->pTracking); + _portMemTrackingRelease(pAllocator->pTracking, NV_TRUE); PORT_MEM_PRINT_INFO("Released allocator %p\n", pAllocator); if (pAllocator->_portRelease != NULL) @@ -882,7 +948,7 @@ #if PORT_MEM_TRACK_USE_LIMIT void -portMemInitializeAllocatorTrackingLimit(NvU32 pid, NvU64 limit, NvBool bLimitEnabled) +portMemInitializeAllocatorTrackingLimit(NvU32 pid, NvLength limit, NvBool bLimitEnabled) { NvU32 pidIdx = pid - 1; portMemGlobals.limitPid[pidIdx] = limit; @@ -898,9 +964,7 @@ PORT_MEM_CALLERINFO_COMMA_TYPE_PARAM ) { -#if PORT_MEM_TRACK_USE_LIMIT NvU32 pid = 0; -#endif void *pMem = NULL; if (pAlloc == NULL) { @@ -945,9 +1009,8 @@ if (pMem != NULL) { pMem = PORT_MEM_ADD_HEADER_PTR(pMem); - _portMemTrackAlloc(_portMemGetTracking(pAlloc), pMem, length + _portMemTrackAlloc(_portMemGetTracking(pAlloc), pMem, length, pid PORT_MEM_CALLERINFO_COMMA_PARAM); - PORT_MEM_LIMIT_INC(pid, pMem, length); } return pMem; } @@ -965,7 +1028,6 @@ } if (pMem != NULL) { - PORT_MEM_LIMIT_DEC(pMem); _portMemTrackFree(_portMemGetTracking(pAlloc), pMem); pMem = PORT_MEM_SUB_HEADER_PTR(pMem); pAlloc->_portFree(pAlloc, pMem); @@ -975,128 +1037,133 @@ void portMemPrintTrackingInfo ( - const PORT_MEM_ALLOCATOR *pAllocator + const PORT_MEM_ALLOCATOR_TRACKING *pTracking ) { - PORT_MEM_ALLOCATOR_TRACKING *pTracking = _portMemGetTracking(pAllocator); + if (pTracking == NULL) + pTracking = &portMemGlobals.mainTracking; - portDbgPrintf("[NvPort] *************************************************\n"); + if (pTracking == &portMemGlobals.mainTracking) + portDbgPrintf("[NvPort] ******** Aggregate Memory Tracking ********\n"); + else if ((pTracking == portMemGlobals.alloc.nonPaged.pTracking) && + (pTracking == portMemGlobals.alloc.paged.pTracking)) + portDbgPrintf("[NvPort] ******** Global Allocator Tracking ********\n"); + else if (pTracking == portMemGlobals.alloc.nonPaged.pTracking) + portDbgPrintf("[NvPort] ******** Global Non-Paged Memory Allocator Tracking ********\n"); + else if (pTracking == portMemGlobals.alloc.paged.pTracking) + portDbgPrintf("[NvPort] ******** Global Paged Memory Allocator Tracking ********\n"); + else + portDbgPrintf("[NvPort] ******** Memory Allocator %p Tracking ******** \n", pTracking->pAllocator); - if (pAllocator == NULL) - { - portDbgPrintf("NvPort memory tracking information for all allocations:\n"); - } + if (pTracking->counter.activeAllocs != 0) + portDbgPrintf(" !!! MEMORY LEAK DETECTED (%u blocks) !!!\n", + pTracking->counter.activeAllocs); - if (pTracking == NULL) +#if PORT_MEM_TRACK_USE_CALLERINFO { - portDbgPrintf("Allocator %p initialized before portMemInitialize(); no tracking info.\n", pAllocator); - return; + portDbgPrintf(" Allocator acquired " + PORT_MEM_CALLERINFO_PRINT_ARGS(pTracking->callerInfo)); } +#endif - for (;;) - { - if (pTracking->pAllocator == NULL) - { - portDbgPrintf("NULL allocator for tracker %p:\n", pTracking); - goto next_tracking; - } - - portDbgPrintf("NvPort memory tracking information for allocator %p:\n", - pTracking->pAllocator); - -#if PORT_MEM_TRACK_USE_CALLERINFO - { - portDbgPrintf(" Allocator acquired " - PORT_MEM_CALLERINFO_PRINT_ARGS(pTracking->callerInfo)); - } +#if PORT_IS_FUNC_SUPPORTED(portMemExTrackingGetHeapSize) + // + // Heap is shared across all allocators, so only print it with the + // aggregate stats. + // + if (pTracking == _portMemGetTracking(NULL)) + portDbgPrintf(" HEAP: %"NvUPtr_fmtu" bytes\n", portMemExTrackingGetHeapSize()); #endif #if PORT_IS_FUNC_SUPPORTED(portMemExTrackingGetActiveStats) - { - PORT_MEM_TRACK_ALLOCATOR_STATS stats; + { + PORT_MEM_TRACK_ALLOCATOR_STATS stats; - portMemSet(&stats, 0, sizeof(stats)); + portMemSet(&stats, 0, sizeof(stats)); - portMemExTrackingGetActiveStats(pTracking->pAllocator, &stats); + portMemExTrackingGetActiveStats(pTracking->pAllocator, &stats); - // - // rmtest_gsp test script (dvs_gsp_sanity.sh) depends on this print, so do not change - // format without updating script! - // - portDbgPrintf("ACTIVE: %u allocations, %llu bytes allocated (%llu useful, %llu meta)\n", - stats.numAllocations, - (NvU64) stats.allocatedSize, - (NvU64) stats.usefulSize, - (NvU64) stats.metaSize); - } + // + // rmtest_gsp test script (dvs_gsp_sanity.sh) depends on this print, so do not change + // format without updating script! + // + portDbgPrintf(" ACTIVE: %u allocations, %"NvUPtr_fmtu" bytes allocated (%"NvUPtr_fmtu" useful, %"NvUPtr_fmtu" meta)\n", + stats.numAllocations, + stats.allocatedSize, + stats.usefulSize, + stats.metaSize); + } #endif #if PORT_IS_FUNC_SUPPORTED(portMemExTrackingGetTotalStats) - { - PORT_MEM_TRACK_ALLOCATOR_STATS stats; + { + PORT_MEM_TRACK_ALLOCATOR_STATS stats; - portMemSet(&stats, 0, sizeof(stats)); + portMemSet(&stats, 0, sizeof(stats)); - portMemExTrackingGetTotalStats(pTracking->pAllocator, &stats); - portDbgPrintf("TOTAL: %u allocations, %llu bytes allocated (%llu useful, %llu meta)\n", - stats.numAllocations, - (NvU64) stats.allocatedSize, - (NvU64) stats.usefulSize, - (NvU64) stats.metaSize); - } + portMemExTrackingGetTotalStats(pTracking->pAllocator, &stats); + portDbgPrintf(" TOTAL: %u allocations, %"NvUPtr_fmtu" bytes allocated (%"NvUPtr_fmtu" useful, %"NvUPtr_fmtu" meta)\n", + stats.numAllocations, + stats.allocatedSize, + stats.usefulSize, + stats.metaSize); + } #endif #if PORT_IS_FUNC_SUPPORTED(portMemExTrackingGetPeakStats) - { - PORT_MEM_TRACK_ALLOCATOR_STATS stats; + { + PORT_MEM_TRACK_ALLOCATOR_STATS stats; - portMemSet(&stats, 0, sizeof(stats)); + portMemSet(&stats, 0, sizeof(stats)); - portMemExTrackingGetPeakStats(pTracking->pAllocator, &stats); - portDbgPrintf("PEAK: %u allocations, %llu bytes allocated (%llu useful, %llu meta)\n", - stats.numAllocations, - (NvU64) stats.allocatedSize, - (NvU64) stats.usefulSize, - (NvU64) stats.metaSize); - } + portMemExTrackingGetPeakStats(pTracking->pAllocator, &stats); + portDbgPrintf(" PEAK: %u allocations, %"NvUPtr_fmtu" bytes allocated (%"NvUPtr_fmtu" useful, %"NvUPtr_fmtu" meta)\n", + stats.numAllocations, + stats.allocatedSize, + stats.usefulSize, + stats.metaSize); + } #endif #if PORT_IS_FUNC_SUPPORTED(portMemExTrackingGetNext) - { - PORT_MEM_TRACK_ALLOC_INFO info; - NvBool bPrinted = NV_FALSE; - void *iterator = NULL; + { + PORT_MEM_TRACK_ALLOC_INFO info; + NvBool bPrinted = NV_FALSE; + void *iterator = NULL; - do + do + { + if (portMemExTrackingGetNext(pTracking->pAllocator, &info, &iterator) != NV_OK) { - if (portMemExTrackingGetNext(pTracking->pAllocator, &info, &iterator) != NV_OK) - { - portDbgPrintf("(no active allocations)\n"); - break; - } - else if (!bPrinted) - { - portDbgPrintf("Currently active allocations:\n"); - bPrinted = NV_TRUE; - } - portDbgPrintf(" - A:%p - 0x%p [%8llu bytes] T=%llu ", - info.pAllocator, - info.pMemory, - (NvU64)info.size, - info.timestamp); - portDbgPrintf(PORT_MEM_CALLERINFO_PRINT_ARGS(info.callerInfo)); - } while (iterator != NULL); - } + portDbgPrintf(" (no active allocations)\n"); + break; + } + else if (!bPrinted) + { + portDbgPrintf(" Currently active allocations:\n"); + bPrinted = NV_TRUE; + } + portDbgPrintf(" - A:%p - 0x%p [%8"NvUPtr_fmtu" bytes] T=%llu ", + info.pAllocator, + info.pMemory, + info.size, + info.timestamp); + portDbgPrintf(PORT_MEM_CALLERINFO_PRINT_ARGS(info.callerInfo)); + } while (iterator != NULL); + } #endif +} -next_tracking: - portDbgPrintf("[NvPort] *************************************************\n"); - - if ((pAllocator != NULL) || (pTracking->pNext == &portMemGlobals.mainTracking)) - break; - - pTracking = pTracking->pNext; - } +void +portMemPrintAllTrackingInfo(void) +{ + const PORT_MEM_ALLOCATOR_TRACKING *pTracking = &portMemGlobals.mainTracking; + PORT_MEM_LOCK_ACQUIRE(portMemGlobals.trackingLock); + do + { + portMemPrintTrackingInfo(pTracking); + } while ((pTracking = pTracking->pNext) != &portMemGlobals.mainTracking); + PORT_MEM_LOCK_RELEASE(portMemGlobals.trackingLock); } #if portMemExTrackingGetActiveStats_SUPPORTED @@ -1198,7 +1265,7 @@ // Populate pInfo pInfo->pMemory = pHead + 1; - pInfo->size = pHead->fence.blockSize; + pInfo->size = _portMemExTrackingGetAllocUsableSizeWrapper(pInfo->pMemory); pInfo->pAllocator = pHead->fence.pAllocator; pInfo->timestamp = 0; @@ -1213,18 +1280,18 @@ static void _portMemTrackingRelease ( - PORT_MEM_ALLOCATOR_TRACKING *pTracking + PORT_MEM_ALLOCATOR_TRACKING *pTracking, + NvBool bReportLeaks ) { if (pTracking == NULL) return; - if (pTracking->counter.activeAllocs != 0) - { - PORT_MEM_PRINT_ERROR("Allocator %p released with memory allocations\n", pTracking->pAllocator); #if (PORT_MEM_TRACK_PRINT_LEVEL > PORT_MEM_TRACK_PRINT_LEVEL_SILENT) - portMemPrintTrackingInfo(pTracking->pAllocator); + if (bReportLeaks && (pTracking->counter.activeAllocs != 0)) + portMemPrintTrackingInfo(pTracking); +#else + PORT_UNREFERENCED_VARIABLE(bReportLeaks); #endif - } PORT_LOCKED_LIST_UNLINK(&portMemGlobals.mainTracking, pTracking, portMemGlobals.trackingLock); PORT_MEM_LIST_DESTROY(pTracking); @@ -1236,17 +1303,29 @@ ( PORT_MEM_ALLOCATOR_TRACKING *pTracking, void *pMem, - NvLength size + NvLength size, + NvU32 pid PORT_MEM_CALLERINFO_COMMA_TYPE_PARAM ) { PORT_UNREFERENCED_VARIABLE(pMem); if (pTracking == NULL) return; - PORT_MEM_PRINT_INFO("Allocating %u bytes at address %p", size, pMem); + +#if PORT_MEM_TRACK_ALLOC_SIZE + // + // Either set the block size in the header, or override it with the value + // from the underlying allocator (which may be bigger than what was + // requested). This keeps the counters consistent with the free path. + // + _portMemExTrackingSetOrGetAllocUsableSize(pMem, &size); +#endif + + PORT_MEM_PRINT_INFO("Allocated %"NvUPtr_fmtu" bytes at address %p", size, pMem); PORT_MEM_PRINT_INFO(PORT_MEM_CALLERINFO_PRINT_ARGS(PORT_MEM_CALLERINFO_PARAM)); PORT_MEM_COUNTER_INC(&pTracking->counter, size); PORT_MEM_COUNTER_INC(&portMemGlobals.mainTracking.counter, size); + PORT_MEM_LIMIT_INC(pid, pMem, size); PORT_MEM_FENCE_INIT(pTracking->pAllocator, pMem, size); PORT_MEM_LIST_ADD(pTracking, pMem); @@ -1261,13 +1340,22 @@ void *pMem ) { + NvLength size = 0; + if (pTracking == NULL) return; + +#if PORT_MEM_TRACK_ALLOC_SIZE + size = _portMemExTrackingGetAllocUsableSizeWrapper(pMem); + PORT_MEM_PRINT_INFO("Freeing %"NvUPtr_fmtu"-byte block at address %p\n", size, pMem); +#else PORT_MEM_PRINT_INFO("Freeing block at address %p\n", pMem); +#endif - PORT_MEM_COUNTER_DEC(&pTracking->counter, pMem); - PORT_MEM_COUNTER_DEC(&portMemGlobals.mainTracking.counter, pMem); + PORT_MEM_COUNTER_DEC(&pTracking->counter, size); + PORT_MEM_COUNTER_DEC(&portMemGlobals.mainTracking.counter, size); + PORT_MEM_LIMIT_DEC(pMem, size); - PORT_MEM_FENCE_CHECK(pTracking->pAllocator, pMem); + PORT_MEM_FENCE_CHECK(pTracking->pAllocator, pMem, size); PORT_MEM_LIST_REMOVE(pTracking, pMem); PORT_MEM_LOG_FREE(pTracking->pAllocator, pMem); } @@ -1356,6 +1444,14 @@ pAllocator->pTracking = NULL; // No tracking for this allocator pAllocator->pImpl = (PORT_MEM_ALLOCATOR_IMPL*)(pAllocator + 1); + + // + // PORT_MEM_BITVECTOR (pAllocator->pImpl) and PORT_MEM_ALLOCATOR_TRACKING (pAllocator->pImpl->tracking) + // are mutually exclusively used. + // When pAllocator->pTracking = NULL the data in pAllocator->pImpl->tracking is not used and instead + // pBitVector uses the same meory location. + // When pAllocator->pImpl->tracking there is no usage of PORT_MEM_BITVECTOR + // pBitVector = (PORT_MEM_BITVECTOR*)(pAllocator->pImpl); pBitVector->pSpinlock = pSpinlock; @@ -1387,7 +1483,7 @@ } portMemSet(pBitVector->bits, 0, bitVectorSize); - PORT_MEM_PRINT_INFO("Acquired preallocated block allocator %p (%llu bytes) ", pAllocator, (NvU64)blockSizeBytes); + PORT_MEM_PRINT_INFO("Acquired preallocated block allocator %p (%"NvUPtr_fmtu" bytes) ", pAllocator, blockSizeBytes); PORT_MEM_PRINT_INFO(PORT_MEM_CALLERINFO_PRINT_ARGS(PORT_MEM_CALLERINFO_PARAM)); return pAllocator; } @@ -1456,6 +1552,10 @@ { portSyncSpinlockRelease(pSpinlock); } + if (pMem == NULL) + { + PORT_MEM_PRINT_ERROR("Memory allocation failed.\n"); + } return pMem; } diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/libraries/nvport/memory/memory_unix_kernel_os.c nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/libraries/nvport/memory/memory_unix_kernel_os.c --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/libraries/nvport/memory/memory_unix_kernel_os.c 2023-10-25 20:21:37.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/libraries/nvport/memory/memory_unix_kernel_os.c 2024-03-05 22:14:22.000000000 +0000 @@ -194,12 +194,12 @@ } // Large allocations (>KMALLOC_LIMIT) will fail, but it is safe to call -NvBool +NvBool portMemExSafeForPagedAlloc(void) { return NV_TRUE; } -NvBool +NvBool portMemExSafeForNonPagedAlloc(void) { return NV_TRUE; diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/libraries/poolalloc/poolalloc.c nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/libraries/poolalloc/poolalloc.c --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/libraries/poolalloc/poolalloc.c 2023-10-25 20:21:38.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/libraries/poolalloc/poolalloc.c 2024-03-05 22:14:23.000000000 +0000 @@ -26,10 +26,6 @@ #include "utils/nvprintf.h" #include "utils/nvassert.h" -// Local defines -#define LOG_ENTER NV_PRINTF(LEVEL_INFO, "--> %s at line %d\n", __FUNCTION__, __LINE__) -#define LOG_EXIT NV_PRINTF(LEVEL_INFO, "<-- %s at line %d\n", __FUNCTION__, __LINE__) - // Local function declarations. static NvU32 ntz_64 (NvU64 bits); static NvU32 countZeros(NvU64 bits); @@ -56,10 +52,10 @@ return ((NvU32)(bz + b5 + b4 + b3 + b2 + b1 + b0)); } -static void +static void _setBitmap ( - NvU64 *bitmap, + NvU64 *bitmap, NvU32 index ) { @@ -126,8 +122,8 @@ it = listIterAll(pList); while (listIterNext(&it)) { - NV_PRINTF_EX(POOLALLOC, LEVEL_NOTICE, - "=> [pageAddr: 0x%llx, bitmap: 0x%llx]", + NV_PRINTF_EX(POOLALLOC, LEVEL_NOTICE, + "=> [pageAddr: 0x%llx, bitmap: 0x%llx]", it.pValue->pageAddr, it.pValue->bitmap); } NV_PRINTF_EX(POOLALLOC, LEVEL_NOTICE, "\n"); @@ -137,7 +133,7 @@ static void allocFreeList ( - POOLALLOC *pPool, + POOLALLOC *pPool, POOLALLOC_HANDLE *pPageHandle ) { @@ -167,7 +163,7 @@ static void allocPartialList ( - POOLALLOC *pPool, + POOLALLOC *pPool, POOLALLOC_HANDLE *pPageHandle ) { @@ -202,9 +198,9 @@ ) { #if defined(DEBUG_VERBOSE) - NV_PRINTF(LEVEL_NOTICE, "upstreamPageSize = %dKB, allocPageSize = %d%s\n", - (pPool->upstreamPageSize >> 10), - (pPool->allocPageSize >> 10) ? pPool->allocPageSize >> 10 : + NV_PRINTF(LEVEL_NOTICE, "upstreamPageSize = %lldKB, allocPageSize = %lld%s\n", + (pPool->upstreamPageSize >> 10), + (pPool->allocPageSize >> 10) ? pPool->allocPageSize >> 10 : pPool->allocPageSize, (pPool->allocPageSize >> 10) ? "KB" : "B"); NV_PRINTF_EX(POOLALLOC, LEVEL_NOTICE, "freeList => "); @@ -220,8 +216,8 @@ POOLALLOC * poolInitialize ( - NvU32 upstreamPageSize, - NvU32 allocPageSize, + NvU64 upstreamPageSize, + NvU64 allocPageSize, allocCallback_t allocCb, freeCallback_t freeCb, void *ctxPtr, @@ -230,7 +226,6 @@ ) { POOLALLOC *pPool; - LOG_ENTER; pPool = PORT_ALLOC(pAllocator, sizeof(*pPool)); if (pPool == NULL) @@ -240,7 +235,7 @@ pPool->upstreamPageSize = upstreamPageSize; pPool->allocPageSize = allocPageSize; - pPool->ratio = upstreamPageSize / allocPageSize; + pPool->ratio = (NvU32)(upstreamPageSize / allocPageSize); pPool->flags = flags; (pPool->callBackInfo).allocCb = allocCb; @@ -253,10 +248,9 @@ listInitIntrusive(&pPool->fullList); listInitIntrusive(&pPool->partialList); - NV_PRINTF(LEVEL_INFO, "Initialized pool with upstreamPageSize = %dB, allocPageSize = %dB and autoPopulate %s\n", + NV_PRINTF(LEVEL_INFO, "Initialized pool with upstreamPageSize = %lldB, allocPageSize = %lldB and autoPopulate %s\n", pPool->upstreamPageSize, pPool->allocPageSize, ((pPool->flags & NV_RMPOOL_FLAGS_AUTO_POPULATE_ENABLE) ? "enabled" : "disabled")); - LOG_EXIT; return pPool; } @@ -268,53 +262,63 @@ NvU64 numPages ) { - NvU64 i, freeLength; + NvU64 i, freeLength, totalAlloc; + NV_STATUS status = NV_ERR_NO_MEMORY; allocCallback_t allocCb; - POOLALLOC_HANDLE pageHandle; + POOLALLOC_HANDLE *pPageHandle = NULL; + POOLNODE *pNode = NULL; - LOG_ENTER; if (pPool == NULL || (pPool->callBackInfo).allocCb == NULL) { - LOG_EXIT; return NV_ERR_INVALID_ARGUMENT; } freeLength = listCount(&pPool->freeList); if (freeLength >= numPages) { - LOG_EXIT; return NV_OK; } + totalAlloc = numPages - freeLength; + allocCb = (pPool->callBackInfo).allocCb; - for (i = 0; i < (numPages - freeLength); i++) - { - if ((*allocCb)((pPool->callBackInfo).pUpstreamCtx, - pPool->upstreamPageSize, &pageHandle) == NV_OK) - { - POOLNODE *pNode; + pPageHandle = PORT_ALLOC(pPool->pAllocator, totalAlloc * sizeof(POOLALLOC_HANDLE)); + NV_ASSERT_OR_GOTO(pPageHandle != NULL, free_none); - pNode = PORT_ALLOC(pPool->pAllocator, sizeof(*pNode)); - listPrependExisting(&pPool->freeList, pNode); + NV_ASSERT_OK_OR_GOTO(status, + allocCb(pPool->callBackInfo.pUpstreamCtx, pPool->upstreamPageSize, + totalAlloc, pPageHandle), + free_page); - pNode->pageAddr = pageHandle.address; - pNode->bitmap = NV_U64_MAX; - pNode->pParent = pageHandle.pMetadata; - } - else - { - LOG_EXIT; - return NV_ERR_NO_MEMORY; - } + status = NV_ERR_NO_MEMORY; + + for (i = 0; i < totalAlloc; i++) + { + pNode = PORT_ALLOC(pPool->pAllocator, sizeof(POOLNODE)); + NV_ASSERT_OR_GOTO(pNode != NULL, free_alloc); + + listPrependExisting(&pPool->freeList, pNode); + pNode->pageAddr = pPageHandle[i].address; + pNode->bitmap = NV_U64_MAX; + pNode->pParent = pPageHandle[i].pMetadata; } + status = NV_OK; freeLength = listCount(&pPool->freeList); NV_ASSERT(freeLength == numPages); - - LOG_EXIT; - return NV_OK; + goto free_page; +free_alloc: + for(; i < totalAlloc; i++) + { + pPool->callBackInfo.freeCb(pPool->callBackInfo.pUpstreamCtx, + pPool->upstreamPageSize, &pPageHandle[i]); + } +free_page: + PORT_FREE(pPool->pAllocator, pPageHandle); +free_none: + return status; } @@ -328,17 +332,14 @@ NvU64 i, freeLength; freeCallback_t freeCb; - LOG_ENTER; if (pPool == NULL || (pPool->callBackInfo).freeCb == NULL) { - LOG_EXIT; return; } freeLength = listCount(&pPool->freeList); if (freeLength <= preserveNum) { - LOG_EXIT; return; } @@ -362,7 +363,6 @@ freeLength = listCount(&pPool->freeList); NV_ASSERT(freeLength == preserveNum); - LOG_EXIT; } @@ -377,13 +377,10 @@ { allocCallback_t allocCb; - LOG_ENTER; - // Trying allocating from the partial list first. if (listCount(&pPool->partialList) > 0) { allocPartialList(pPool, pPageHandle); - LOG_EXIT; return NV_OK; } @@ -391,19 +388,18 @@ if (listCount(&pPool->freeList) > 0) { allocFreeList(pPool, pPageHandle); - LOG_EXIT; return NV_OK; } allocCb = (pPool->callBackInfo).allocCb; // - // Nothing left in free list as well!! Populate the pool if it is configured to be auto-populated + // Nothing left in free list as well!! Populate the pool if it is configured to be auto-populated // Once we have free list then allocate from free list. // if (FLD_TEST_DRF(_RMPOOL, _FLAGS, _AUTO_POPULATE, _ENABLE, pPool->flags)) { - if ((*allocCb)(pPool->callBackInfo.pUpstreamCtx, pPool->upstreamPageSize, pPageHandle) == NV_OK) + if ((*allocCb)(pPool->callBackInfo.pUpstreamCtx, pPool->upstreamPageSize, 1, pPageHandle) == NV_OK) { POOLNODE *pNode; @@ -416,18 +412,15 @@ allocFreeList(pPool, pPageHandle); - LOG_EXIT; return NV_OK; } } - LOG_EXIT; - return NV_ERR_NO_MEMORY; } -NV_STATUS +NV_STATUS poolAllocateContig ( POOLALLOC *pPool, @@ -442,8 +435,6 @@ PoolPageHandleListIter it; NvU64 prevAddr, curAddr; - LOG_ENTER; - // can't allocate more than one upstream chunk NV_ASSERT_OR_RETURN(numPages <= pPool->ratio, NV_ERR_INVALID_ARGUMENT); @@ -510,8 +501,6 @@ NvU32 freeIdx; NvU64 address, baseAddr; - LOG_ENTER; - address = pPageHandle->address; pNode = (POOLNODE *) (pPageHandle->pMetadata); baseAddr = pNode->pageAddr; @@ -548,8 +537,6 @@ listPrependExisting(&pPool->freeList, pNode); } } - - LOG_EXIT; } @@ -559,15 +546,12 @@ POOLALLOC *pPool ) { - LOG_ENTER; - // call back to free all the pages poolListDestroy(&pPool->fullList, pPool); poolListDestroy(&pPool->partialList, pPool); poolListDestroy(&pPool->freeList, pPool); PORT_FREE(pPool->pAllocator, pPool); - LOG_EXIT; } void diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/libraries/prereq_tracker/prereq_tracker.c nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/libraries/prereq_tracker/prereq_tracker.c --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/libraries/prereq_tracker/prereq_tracker.c 2023-10-25 20:21:38.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/libraries/prereq_tracker/prereq_tracker.c 2024-03-05 22:14:23.000000000 +0000 @@ -107,7 +107,7 @@ // Put together a mask of PREREQ_IDs which are both satisfied and requested // We do not keep track of satisfied prereqs until armed, so we have no existing // state to worry about here. - // + // NV_ASSERT_OK_OR_RETURN(bitVectorAnd(&requestedAndSatisfied, &pPrereq->requested, &pTracker->satisfied)); diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/libraries/resserv/src/rs_client.c nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/libraries/resserv/src/rs_client.c --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/libraries/resserv/src/rs_client.c 2023-10-25 20:21:39.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/libraries/resserv/src/rs_client.c 2024-03-05 22:14:23.000000000 +0000 @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 2015-2021 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2015-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -62,15 +62,6 @@ NvHandle hResource, NvU32 classId, RsResourceRef **ppResourceRef); /** - * Release all CPU address mappings for a resource - * - * @param[in] pClient Client that owns the resource - * @param[in] pCallContext Caller information (which includes the resource reference whose mappings will be freed) - * @param[in] pLockInfo Information about which locks are already held, for recursive calls - */ -static NV_STATUS _clientUnmapResourceRefMappings(RsClient *pClient, CALL_CONTEXT *pCallContext, RS_LOCK_INFO *pLockInfo); - -/** * Release all CPU address mappings that reference this resource * * @param[in] pClient Client that owns the resource @@ -111,7 +102,7 @@ status = clientSetHandleGenerator(pClient, 0, 0); if (status != NV_OK) return status; - + pClient->bActive = NV_TRUE; status = clientSetRestrictedRange(pClient, 0, 0); @@ -290,10 +281,10 @@ return NV_OK; } -NV_STATUS +NV_STATUS clientSetRestrictedRange_IMPL ( - RsClient *pClient, + RsClient *pClient, NvHandle handleRangeStart, NvU32 handleRangeSize ) @@ -532,7 +523,7 @@ callContext.secInfo = *pParams->pSecInfo; callContext.pLockInfo = pParams->pLockInfo; - resservSwapTlsCallContext(&pOldContext, &callContext); + NV_ASSERT_OK_OR_RETURN(resservSwapTlsCallContext(&pOldContext, &callContext)); // // Kernel clients are allowed to dup anything, unless they request otherwise. @@ -544,7 +535,7 @@ (pServer->bRsAccessEnabled || (pParams->pSrcClient->hClient != pClient->hClient))) { RS_ACCESS_MASK rightsRequired; - + portMemSet(&rightsRequired, 0, sizeof(rightsRequired)); RS_ACCESS_MASK_ADD(&rightsRequired, RS_ACCESS_DUP_OBJECT); @@ -569,7 +560,7 @@ } } - resservRestoreTlsCallContext(pOldContext); + NV_ASSERT_OK(resservRestoreTlsCallContext(pOldContext)); if (status != NV_OK) return status; @@ -677,9 +668,11 @@ } callContext.secInfo = *pParams->pSecInfo; - resservSwapTlsCallContext(&pOldContext, &callContext); + NV_ASSERT_OK_OR_GOTO(status, + resservSwapTlsCallContext(&pOldContext, &callContext), fail); + status = resservResourceFactory(pServer->pAllocator, &callContext, pParams, &pResource); - resservRestoreTlsCallContext(pOldContext); + NV_ASSERT_OK(resservRestoreTlsCallContext(pOldContext)); if (status != NV_OK) goto fail; @@ -733,6 +726,8 @@ fail: if (pResource != NULL) { + NV_STATUS callContextStatus; + RS_RES_FREE_PARAMS_INTERNAL params; pOldContext = NULL; @@ -747,11 +742,20 @@ callContext.pResourceRef = pResourceRef; callContext.pLockInfo = pParams->pLockInfo; - resservSwapTlsCallContext(&pOldContext, &callContext); - resSetFreeParams(pResource, &callContext, ¶ms); + callContextStatus = resservSwapTlsCallContext(&pOldContext, &callContext); + if (callContextStatus == NV_OK) + { + resSetFreeParams(pResource, &callContext, ¶ms); + + objDelete(pResource); + NV_ASSERT_OK(resservRestoreTlsCallContext(pOldContext)); + } + else + { + NV_PRINTF(LEVEL_ERROR, "Failed to set call context! Error: 0x%x\n", + callContextStatus); + } - objDelete(pResource); - resservRestoreTlsCallContext(pOldContext); } if (pResourceRef != NULL) @@ -794,7 +798,7 @@ pResource = pResourceRef->pResource; pParentRef = pResourceRef->pParentRef; - if (!pParams->bInvalidateOnly && pResourceRef->bInvalidated) + if (pResourceRef->bInvalidated) goto done; portMemSet(&callContext, 0, sizeof(callContext)); @@ -807,13 +811,15 @@ if (pParams->pSecInfo != NULL) callContext.secInfo = *pParams->pSecInfo; - resservSwapTlsCallContext(&pOldContext, &callContext); + NV_ASSERT_OK_OR_GOTO(status, + resservSwapTlsCallContext(&pOldContext, &callContext), done); + resSetFreeParams(pResource, &callContext, pParams); resPreDestruct(pResource); // Remove all CPU mappings - _clientUnmapResourceRefMappings(pClient, &callContext, pParams->pLockInfo); + clientUnmapResourceRefMappings(pClient, &callContext, pParams->pLockInfo); _clientUnmapBackRefMappings(pClient, &callContext, pParams->pLockInfo); // Remove all inter-mappings @@ -834,7 +840,7 @@ pResourceRef->pResource = NULL; - resservRestoreTlsCallContext(pOldContext); + NV_ASSERT_OK(resservRestoreTlsCallContext(pOldContext)); done: if (!pParams->bInvalidateOnly) @@ -881,14 +887,15 @@ if (pSecInfo != NULL) callContext.secInfo = *pSecInfo; - resservSwapTlsCallContext(&pOldContext, &callContext); + NV_ASSERT_OK_OR_RETURN(resservSwapTlsCallContext(&pOldContext, &callContext)); + status = resUnmap(pResourceRef->pResource, &callContext, pCpuMapping); - resservRestoreTlsCallContext(pOldContext); + NV_ASSERT_OK(resservRestoreTlsCallContext(pOldContext)); if (status != NV_OK) { - NV_PRINTF(LEVEL_ERROR, "hClient %x: Failed to unmap cpu mapping: hResource: %x error: 0x%x\n", - pClient->hClient, + NV_PRINTF(LEVEL_ERROR, "hClient %x: Failed to unmap cpu mapping: hResource: %x error: 0x%x\n", + pClient->hClient, pResourceRef->hResource, status); @@ -950,7 +957,7 @@ } hFirst = hResource; - do + do { hResource = pClient->handleRangeStart + ((pClient->handleGenIdx++) % pClient->handleRangeSize); status = clientValidateNewResourceHandle(pClient, hResource, NV_FALSE); @@ -1082,7 +1089,7 @@ } NV_STATUS -_clientUnmapResourceRefMappings +clientUnmapResourceRefMappings ( RsClient *pClient, CALL_CONTEXT *pCallContext, @@ -1102,8 +1109,8 @@ portMemSet(&lockInfo, 0, sizeof(lockInfo)); params.hClient = pClient->hClient; - params.hDevice = (pCpuMapping->pContextRef == NULL) - ? pClient->hClient + params.hDevice = (pCpuMapping->pContextRef == NULL) + ? pClient->hClient : pCpuMapping->pContextRef->hResource; params.hMemory = pResourceRef->hResource; params.pLinearAddress = pCpuMapping->pLinearAddress; @@ -1256,7 +1263,7 @@ pMapping = listHead(&pMapperRef->interMappings); while (pMapping != NULL) { - status = _unmapInterMapping(pCallContext->pServer, pClient, pMapperRef, + status = _unmapInterMapping(pCallContext->pServer, pClient, pMapperRef, pMapping, pLockInfo, &pCallContext->secInfo); if (status != NV_OK) { @@ -1295,7 +1302,7 @@ RsResourceRef *pMapperRef = pBackRefItem->pMapperRef; RsInterMapping *pMapping = pBackRefItem->pMapping; - status = _unmapInterMapping(pCallContext->pServer, pClient, pMapperRef, + status = _unmapInterMapping(pCallContext->pServer, pClient, pMapperRef, pMapping, pLockInfo, &pCallContext->secInfo); if (status != NV_OK) { @@ -1364,7 +1371,7 @@ ( RsClient *pClient, NvHandle hResource, - NvBool bRestrict + NvBool bRestrict ) { // @@ -1667,7 +1674,7 @@ pResourceRef = bUseIdx ? *pIt->idxIt.pValue : pIt->mapIt.pValue; if (bUseIdx || - ((pResourceRef == pIt->pScopeRef) || + ((pResourceRef == pIt->pScopeRef) || (refHasAncestor(pResourceRef, pIt->pScopeRef)))) { NvBool bMatch = NV_TRUE; diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/libraries/resserv/src/rs_resource.c nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/libraries/resserv/src/rs_resource.c --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/libraries/resserv/src/rs_resource.c 2023-10-25 20:21:39.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/libraries/resserv/src/rs_resource.c 2024-03-05 22:14:24.000000000 +0000 @@ -121,10 +121,10 @@ const struct NVOC_EXPORTED_METHOD_DEF **ppEntry ) { - const struct NVOC_EXPORTED_METHOD_DEF *pEntry; - NvU32 cmd = pRsParams->cmd; + const struct NVOC_EXPORTED_METHOD_DEF *pEntry; + NvU32 cmd = pRsParams->cmd; - *ppEntry = NULL; + *ppEntry = NULL; pEntry = objGetExportedMethodDef(staticCast(objFullyDerive(pResource), Dynamic), cmd); if (pEntry == NULL) @@ -184,6 +184,10 @@ if (status != NV_OK) return status; + status = resControlSerialization_Prologue(pResource, pCallContext, pRsParams); + if (status != NV_OK) + goto done; + status = resControl_Prologue(pResource, pCallContext, pRsParams); if ((status != NV_OK) && (status != NV_WARN_NOTHING_TO_DO)) goto done; @@ -207,6 +211,7 @@ else { CONTROL_EXPORT_FNPTR pFunc = ((CONTROL_EXPORT_FNPTR) pEntry->pFunc); + status = pFunc(pDynamicObj, pRsParams->pParams); } } @@ -214,6 +219,7 @@ resControl_Epilogue(pResource, pCallContext, pRsParams); done: + resControlSerialization_Epilogue(pResource, pCallContext, pRsParams); status = serverControl_Epilogue(pServer, pRsParams, access, &releaseFlags, status); return status; @@ -231,6 +237,27 @@ } NV_STATUS +resControlSerialization_Prologue_IMPL +( + RsResource *pResource, + CALL_CONTEXT *pCallContext, + RS_RES_CONTROL_PARAMS_INTERNAL *pParams +) +{ + return NV_OK; +} + +void +resControlSerialization_Epilogue_IMPL +( + RsResource *pResource, + CALL_CONTEXT *pCallContext, + RS_RES_CONTROL_PARAMS_INTERNAL *pParams +) +{ +} + +NV_STATUS resControl_Prologue_IMPL ( RsResource *pResource, @@ -767,15 +794,20 @@ RsResourceRef *pDependantRef ) { + NV_STATUS status; + // dependencies are implicit between a parent resource reference and child resource reference if (refHasAncestor(pDependantRef, pResourceRef)) return NV_OK; - indexAdd(&pDependantRef->depBackRefMap, pResourceRef->internalClassId, pResourceRef); + status = indexAdd(&pDependantRef->depBackRefMap, pResourceRef->internalClassId, pResourceRef); + if (status != NV_OK) + return status; + return indexAdd(&pResourceRef->depRefMap, pDependantRef->internalClassId, pDependantRef); } -NV_STATUS +void refRemoveDependant ( RsResourceRef *pResourceRef, @@ -783,7 +815,7 @@ ) { indexRemove(&pDependantRef->depBackRefMap, pResourceRef->internalClassId, pResourceRef); - return indexRemove(&pResourceRef->depRefMap, pDependantRef->internalClassId, pDependantRef); + indexRemove(&pResourceRef->depRefMap, pDependantRef->internalClassId, pDependantRef); } NvBool diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/libraries/resserv/src/rs_server.c nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/libraries/resserv/src/rs_server.c --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/libraries/resserv/src/rs_server.c 2023-10-25 20:21:39.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/libraries/resserv/src/rs_server.c 2024-03-05 22:14:24.000000000 +0000 @@ -20,7 +20,7 @@ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * DEALINGS IN THE SOFTWARE. */ - + #define NVOC_RS_SERVER_H_PRIVATE_ACCESS_ALLOWED #include "nvlog_inc.h" #include "resserv/resserv.h" @@ -273,6 +273,9 @@ goto fail; } + listInitIntrusive(&pServer->disabledClientList); + pServer->pDisabledClientListLock = portSyncSpinlockCreate(pAllocator); + return NV_OK; fail: @@ -336,6 +339,9 @@ listDestroy(&pServer->pClientSortedList[i]); } + listDestroy(&pServer->disabledClientList); + portSyncSpinlockDestroy(pServer->pDisabledClientListLock); + PORT_FREE(pServer->pAllocator, pServer->pClientSortedList); mapDestroy(&pServer->shareMap); listDestroy(&pServer->defaultInheritedSharePolicyList); @@ -412,6 +418,13 @@ clientFreeAccessBackRefs(pClient, pServer); + if (pClient->bDisabled) + { + portSyncSpinlockAcquire(pServer->pDisabledClientListLock); + listRemove(&pServer->disabledClientList, pClient); + portSyncSpinlockRelease(pServer->pDisabledClientListLock); + } + objDelete(pClient); listRemoveFirstByValue(&pServer->pClientSortedList[hClient & RS_CLIENT_HANDLE_BUCKET_MASK], &pClientEntry); @@ -626,6 +639,7 @@ RS_LOCK_INFO *pLockInfo; RsClient *pSecondClient = NULL; NvHandle hSecondClient; + CALL_CONTEXT callContext = {0}; if (!pServer->bConstructed) return NV_ERR_NOT_READY; @@ -648,6 +662,10 @@ if (status == NV_OK) { + NV_CHECK_OK_OR_GOTO(status, LEVEL_ERROR, + serverDeserializeAllocDown(&callContext, pParams->externalClassId, &pParams->pAllocParams, &pParams->paramsSize, &pParams->allocFlags), + done); + if (bClientAlloc) { status = serverAllocClient(pServer, pParams); @@ -729,6 +747,10 @@ } } + NV_CHECK_OK_OR_CAPTURE_FIRST_ERROR(status, LEVEL_ERROR, + serverSerializeAllocUp(&callContext, pParams->externalClassId, &pParams->pAllocParams, &pParams->paramsSize, &pParams->allocFlags)); + serverFreeSerializeStructures(&callContext, pParams->pAllocParams); + serverTopLock_Epilogue(pServer, topLockAccess, pLockInfo, &releaseFlags); // copyout as needed, being careful not to overwrite a useful status value @@ -857,7 +879,7 @@ } NV_STATUS -serverFreeClientList +serverMarkClientListDisabled ( RsServer *pServer, NvHandle *phClientList, @@ -866,34 +888,121 @@ API_SECURITY_INFO *pSecInfo ) { - NvU32 i, j; + NvU32 i; + for (i = 0; i < numClients; ++i) + { + RS_CLIENT_FREE_PARAMS params; + portMemSet(¶ms, 0, sizeof(params)); + + if (phClientList[i] == 0) + continue; + + params.hClient = phClientList[i]; + params.bDisableOnly = NV_TRUE; + params.state = freeState; + params.pSecInfo = pSecInfo; + + // If individual calls fail not much to do, just log error and move on + NV_ASSERT_OK(serverFreeClient(pServer, ¶ms)); + } + + return NV_OK; +} + +// Returns pServer->pNextDisabledClient and advances it by one node ahead +static RsClient * +_getNextDisabledClient(RsServer *pServer) +{ + RsClient *pClient; + portSyncSpinlockAcquire(pServer->pDisabledClientListLock); + + pClient = + (pServer->pNextDisabledClient != NULL) ? + pServer->pNextDisabledClient : + listHead(&pServer->disabledClientList); + + pServer->pNextDisabledClient = + (pClient != NULL) ? + listNext(&pServer->disabledClientList, pClient) : + listHead(&pServer->disabledClientList); + + portSyncSpinlockRelease(pServer->pDisabledClientListLock); + return pClient; +} + +NV_STATUS serverFreeDisabledClients +( + RsServer *pServer, + NvU32 freeState, + NvU32 limit +) +{ + RsClient *pClient; + RS_RES_FREE_PARAMS params; + API_SECURITY_INFO secInfo; + RS_LOCK_INFO lockInfo; + NV_STATUS status = NV_OK; // - // Call serverFreeClient twice; first for high priority resources - // then again for remaining resources + // Only allow one instance of this function at a time. + // Multiple calls can happen if one thread requested delayed free via worker, + // while another tries to flush disabled clients immediately. + // It doesn't matter which one ends up running, they all free everything // - for (i = 0; i < 2; ++i) + static volatile NvU32 inProgress; + if (!portAtomicCompareAndSwapU32(&inProgress, 1, 0)) + return NV_ERR_IN_USE; + + portMemSet(¶ms, 0, sizeof(params)); + portMemSet(&secInfo, 0, sizeof(secInfo)); + portMemSet(&lockInfo, 0, sizeof(lockInfo)); + + secInfo.privLevel = RS_PRIV_LEVEL_KERNEL; + secInfo.paramLocation = PARAM_LOCATION_KERNEL; + lockInfo.state = freeState; + params.pLockInfo = &lockInfo; + params.pSecInfo = &secInfo; + + while ((pClient = _getNextDisabledClient(pServer))) { - for (j = 0; j < numClients; ++j) - { - RS_CLIENT_FREE_PARAMS params; - portMemSet(¶ms, 0, sizeof(params)); + NV_ASSERT(pClient->bDisabled); - if (phClientList[j] == 0) - continue; + params.hClient = pClient->hClient; + params.hResource = pClient->hClient; + + // + // We call serverFreeClient twice; first for high priority resources + // then again for remaining resources + // + if (!pClient->bHighPriorityFreeDone) + { + params.bHiPriOnly = NV_TRUE; + pClient->bHighPriorityFreeDone = NV_TRUE; + } + else + { + params.bHiPriOnly = NV_FALSE; + } - params.hClient = phClientList[j]; - params.bHiPriOnly = (i == 0); - params.state = freeState; - params.pSecInfo = pSecInfo; + serverFreeResourceTree(pServer, ¶ms); - serverFreeClient(pServer, ¶ms); + // + // If limit is 0, it'll wrap-around and count down from 0xFFFFFFFF + // But RS_CLIENT_HANDLE_MAX is well below that, so it effectively + // means process all of them + // + if (--limit == 0) + { + status = NV_WARN_MORE_PROCESSING_REQUIRED; + break; } } - return NV_OK; + portAtomicSetU32(&inProgress, 0); + return status; } + NV_STATUS serverFreeResourceTree ( @@ -960,6 +1069,44 @@ pParams->pResourceRef = pResourceRef; freeStack.pResourceRef = pResourceRef; + if (pParams->bDisableOnly) + { + if (!pClient->bDisabled) + { + pClient->bDisabled = NV_TRUE; + portSyncSpinlockAcquire(pServer->pDisabledClientListLock); + listAppendExisting(&pServer->disabledClientList, pClient); + portSyncSpinlockRelease(pServer->pDisabledClientListLock); + } + else + { + status = NV_ERR_INVALID_STATE; + goto done; + } + + pClient->bActive = NV_FALSE; + status = NV_OK; + + // Unmap all CPU mappings + { + CALL_CONTEXT callContext; + RS_ITERATOR it; + portMemSet(&callContext, 0, sizeof(callContext)); + callContext.pServer = pServer; + callContext.pClient = pClient; + callContext.pLockInfo = pLockInfo; + + it = clientRefIter(pClient, NULL, 0, RS_ITERATE_DESCENDANTS, NV_TRUE); + while (clientRefIterNext(pClient, &it)) + { + callContext.pResourceRef = it.pResourceRef; + clientUnmapResourceRefMappings(pClient, &callContext, pLockInfo); + } + } + + goto done; + } + if (pParams->bInvalidateOnly && pResourceRef->bInvalidated) { status = NV_OK; @@ -1197,9 +1344,11 @@ } pLockInfo->pContextRef = pResourceRef->pParentRef; - resservSwapTlsCallContext(&pOldContext, &callContext); + NV_ASSERT_OK_OR_GOTO(status, + resservSwapTlsCallContext(&pOldContext, &callContext), done); + status = resControl(pResourceRef->pResource, &callContext, pParams); - resservRestoreTlsCallContext(pOldContext); + NV_ASSERT_OK(resservRestoreTlsCallContext(pOldContext)); done: @@ -1374,7 +1523,8 @@ callContext.pResourceRef = pResourceRef; callContext.secInfo = *pParams->pSecInfo; callContext.pLockInfo = pParams->pLockInfo; - resservSwapTlsCallContext(&pOldContext, &callContext); + NV_ASSERT_OK_OR_GOTO(status, + resservSwapTlsCallContext(&pOldContext, &callContext), done); if (hClientOwner == hClientTarget) { @@ -1397,7 +1547,7 @@ goto restore_context; restore_context: - resservRestoreTlsCallContext(pOldContext); + NV_ASSERT_OK(resservRestoreTlsCallContext(pOldContext)); // NV_PRINTF(LEVEL_INFO, "hClientOwner %x: Shared hResource: %x with hClientTarget: %x\n", // hClientOwner, pParams->hResource, hClientTarget); @@ -1484,9 +1634,11 @@ callContext.secInfo = *pParams->pSecInfo; callContext.pLockInfo = pParams->pLockInfo; - resservSwapTlsCallContext(&pOldContext, &callContext); + NV_ASSERT_OK_OR_GOTO(status, + resservSwapTlsCallContext(&pOldContext, &callContext), done); + status = clientShareResource(pClient, pResourceRef, pParams->pSharePolicy, &callContext); - resservRestoreTlsCallContext(pOldContext); + NV_ASSERT_OK(resservRestoreTlsCallContext(pOldContext)); if (status != NV_OK) goto done; @@ -1588,9 +1740,11 @@ if (pParams->pSecInfo != NULL) callContext.secInfo = *pParams->pSecInfo; - resservSwapTlsCallContext(&pOldContext, &callContext); + NV_ASSERT_OK_OR_GOTO(status, + resservSwapTlsCallContext(&pOldContext, &callContext), done); + status = resMap(pResource, &callContext, pParams, pCpuMapping); - resservRestoreTlsCallContext(pOldContext); + NV_ASSERT_OK(resservRestoreTlsCallContext(pOldContext)); if (status != NV_OK) goto done; @@ -1763,7 +1917,9 @@ if (pParams->pSecInfo != NULL) callContext.secInfo = *pParams->pSecInfo; - resservSwapTlsCallContext(&pOldContext, &callContext); + NV_ASSERT_OK_OR_GOTO(status, + resservSwapTlsCallContext(&pOldContext, &callContext), done); + bRestoreCallContext = NV_TRUE; status = refAddInterMapping(pMapperRef, pMappableRef, pContextRef, &pMapping); @@ -1787,7 +1943,7 @@ serverInterMap_Epilogue(pServer, pParams, &releaseFlags); if (bRestoreCallContext) - resservRestoreTlsCallContext(pOldContext); + NV_ASSERT_OK(resservRestoreTlsCallContext(pOldContext)); if (status != NV_OK) { @@ -1877,7 +2033,9 @@ if (pLockInfo->pContextRef == NULL) pLockInfo->pContextRef = pContextRef; - resservSwapTlsCallContext(&pOldContext, &callContext); + NV_ASSERT_OK_OR_GOTO(status, + resservSwapTlsCallContext(&pOldContext, &callContext), done); + bRestoreCallContext = NV_TRUE; status = serverResLock_Prologue(pServer, LOCK_ACCESS_WRITE, pLockInfo, &releaseFlags); @@ -1898,7 +2056,7 @@ serverResLock_Epilogue(pServer, LOCK_ACCESS_WRITE, pLockInfo, &releaseFlags); if (bRestoreCallContext) - resservRestoreTlsCallContext(pOldContext); + NV_ASSERT_OK(resservRestoreTlsCallContext(pOldContext)); _serverUnlockClientWithLockInfo(pServer, LOCK_ACCESS_WRITE, pParams->hClient, pLockInfo, &releaseFlags); serverTopLock_Epilogue(pServer, topLockAccess, pLockInfo, &releaseFlags); @@ -2653,12 +2811,15 @@ portMemSet(&lockInfo, 0, sizeof(lockInfo)); portMemSet(¶ms, 0, sizeof(params)); - params.hClient = pParams->hClient; - params.hResource = pParams->hClient; - params.bHiPriOnly = pParams->bHiPriOnly; - lockInfo.state = pParams->state; - params.pLockInfo = &lockInfo; - params.pSecInfo = pParams->pSecInfo; + + lockInfo.state = pParams->state; + lockInfo.flags = RS_LOCK_FLAGS_LOW_PRIORITY; + params.pLockInfo = &lockInfo; + params.hClient = pParams->hClient; + params.hResource = pParams->hClient; + params.bHiPriOnly = pParams->bHiPriOnly; + params.bDisableOnly = pParams->bDisableOnly; + params.pSecInfo = pParams->pSecInfo; return serverFreeResourceTree(pServer, ¶ms); } @@ -2878,7 +3039,7 @@ status = objCreateDynamicWithFlags(&pDynamic, pHalspecParent, (const NVOC_CLASS_INFO*)(const void*)pClassInfo, - flags); + flags); if (status != NV_OK) return status; @@ -3005,6 +3166,131 @@ return NV_FALSE; } +#if RS_STANDALONE +NV_STATUS +serverSerializeCtrlDown +( + CALL_CONTEXT *pCallContext, + NvU32 cmd, + void **ppParams, + NvU32 *pParamsSize, + NvU32 *flags +) +{ + return NV_OK; +} + +NV_STATUS +serverDeserializeCtrlDown +( + CALL_CONTEXT *pCallContext, + NvU32 cmd, + void **ppParams, + NvU32 *pParamsSize, + NvU32 *flags +) +{ + return NV_OK; +} + +NV_STATUS +serverSerializeCtrlUp +( + CALL_CONTEXT *pCallContext, + NvU32 cmd, + void **ppParams, + NvU32 *pParamsSize, + NvU32 *flags +) +{ + return NV_OK; +} + +NV_STATUS +serverDeserializeCtrlUp +( + CALL_CONTEXT *pCallContext, + NvU32 cmd, + void **ppParams, + NvU32 *pParamsSize, + NvU32 *flags +) +{ + return NV_OK; +} + +NV_STATUS +serverSerializeAllocDown +( + CALL_CONTEXT *pCallContext, + NvU32 classId, + void **ppParams, + NvU32 *pParamsSize, + NvU32 *flags +) +{ + return NV_OK; +} + +NV_STATUS +serverDeserializeAllocDown +( + CALL_CONTEXT *pCallContext, + NvU32 classId, + void **ppParams, + NvU32 *pParamsSize, + NvU32 *flags +) +{ + return NV_OK; +} + +NV_STATUS +serverSerializeAllocUp +( + CALL_CONTEXT *pCallContext, + NvU32 classId, + void **ppParams, + NvU32 *pParamsSize, + NvU32 *flags +) +{ + return NV_OK; +} + +NV_STATUS +serverDeserializeAllocUp +( + CALL_CONTEXT *pCallContext, + NvU32 classId, + void **pParams, + NvU32 *pParamsSize, + NvU32 *flags +) +{ + return NV_OK; +} + +void +serverFreeSerializeStructures +( + CALL_CONTEXT *pCallContext, + void *pParams +) +{ +} +#endif // RS_STANDALONE + +void +serverDisableReserializeControl +( + CALL_CONTEXT *pCallContext +) +{ + NV_CHECK_OR_RETURN_VOID(LEVEL_INFO, pCallContext != NULL); + pCallContext->bReserialize = NV_FALSE; +} + #if (RS_PROVIDES_API_STATE) NV_STATUS serverAllocApiCopyIn diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/libraries/utils/nvassert.c nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/libraries/utils/nvassert.c --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/src/libraries/utils/nvassert.c 2023-10-25 20:21:39.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/src/libraries/utils/nvassert.c 2024-03-05 22:14:24.000000000 +0000 @@ -35,6 +35,9 @@ #include "os/os.h" #include "nvrm_registry.h" #include "rmconfig.h" +#include "gpu/gpu.h" +#include "gpu/gpu_user_shared_data.h" +#include "class/cl00de.h" #elif !defined(RMCFG_FEATURE_ENABLED) #define RMCFG_FEATURE_x 0 #endif @@ -55,18 +58,36 @@ #if defined(GSP_PLUGIN_BUILD) || (defined(NVRM) && NVCPU_IS_RISCV64) #if NV_JOURNAL_ASSERT_ENABLE +static void +_logAssertCount(void) +{ + static NvU32 assertCount = 0; + NV00DE_SHARED_DATA *pSharedData; + + if (g_pGpu == NULL) + { + return; + } + + pSharedData = gpushareddataWriteStart(g_pGpu); + pSharedData->gspAssertCount = ++assertCount; + gpushareddataWriteFinish(g_pGpu); +} + /* * Helper function for NV_ASSERT_FAILED */ void nvAssertFailed(void) { + _logAssertCount(); NV_JOURNAL_ASSERT_FAILURE(NV_RM_ASSERT_UNKNOWN_LINE_NUM, portUtilGetReturnAddress()); } void nvAssertOkFailed(NvU32 status) { + _logAssertCount(); NV_JOURNAL_ASSERT_FAILURE_STATUS(NV_RM_ASSERT_UNKNOWN_LINE_NUM, portUtilGetReturnAddress(), status); } #endif diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/srcs.mk nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/srcs.mk --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia/srcs.mk 2023-10-25 20:22:29.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia/srcs.mk 2024-03-05 22:15:26.000000000 +0000 @@ -5,14 +5,22 @@ SRCS += generated/g_all_dcl_pb.c SRCS += generated/g_binary_api_nvoc.c SRCS += generated/g_bindata.c +SRCS += generated/g_ccsl_nvoc.c +SRCS += generated/g_ce_utils_nvoc.c SRCS += generated/g_channel_descendant_nvoc.c SRCS += generated/g_chips2halspec_nvoc.c SRCS += generated/g_chipset_nvoc.c SRCS += generated/g_client_nvoc.c SRCS += generated/g_client_resource_nvoc.c SRCS += generated/g_compute_instance_subscription_nvoc.c +SRCS += generated/g_conf_compute_api_nvoc.c +SRCS += generated/g_conf_compute_nvoc.c SRCS += generated/g_console_mem_nvoc.c SRCS += generated/g_context_dma_nvoc.c +SRCS += generated/g_crashcat_engine_nvoc.c +SRCS += generated/g_crashcat_queue_nvoc.c +SRCS += generated/g_crashcat_report_nvoc.c +SRCS += generated/g_crashcat_wayfinder_nvoc.c SRCS += generated/g_dbgbuffer_nvoc.c SRCS += generated/g_deferred_api_nvoc.c SRCS += generated/g_device_nvoc.c @@ -22,6 +30,7 @@ SRCS += generated/g_disp_objs_nvoc.c SRCS += generated/g_disp_sf_user_nvoc.c SRCS += generated/g_dispsw_nvoc.c +SRCS += generated/g_egm_mem_nvoc.c SRCS += generated/g_eng_state_nvoc.c SRCS += generated/g_engines_pb.c SRCS += generated/g_event_buffer_nvoc.c @@ -32,6 +41,7 @@ SRCS += generated/g_fla_mem_nvoc.c SRCS += generated/g_fm_session_api_nvoc.c SRCS += generated/g_generic_engine_nvoc.c +SRCS += generated/g_gpu_access_nvoc.c SRCS += generated/g_gpu_acct_nvoc.c SRCS += generated/g_gpu_boost_mgr_nvoc.c SRCS += generated/g_gpu_class_list.c @@ -59,6 +69,7 @@ SRCS += generated/g_intr_nvoc.c SRCS += generated/g_intr_service_nvoc.c SRCS += generated/g_io_vaspace_nvoc.c +SRCS += generated/g_ioaccess_nvoc.c SRCS += generated/g_journal_nvoc.c SRCS += generated/g_journal_pb.c SRCS += generated/g_kern_bus_nvoc.c @@ -77,6 +88,7 @@ SRCS += generated/g_kernel_channel_group_api_nvoc.c SRCS += generated/g_kernel_channel_group_nvoc.c SRCS += generated/g_kernel_channel_nvoc.c +SRCS += generated/g_kernel_crashcat_engine_nvoc.c SRCS += generated/g_kernel_ctxshare_nvoc.c SRCS += generated/g_kernel_falcon_nvoc.c SRCS += generated/g_kernel_fifo_nvoc.c @@ -122,6 +134,7 @@ SRCS += generated/g_p2p_api_nvoc.c SRCS += generated/g_phys_mem_nvoc.c SRCS += generated/g_platform_nvoc.c +SRCS += generated/g_platform_request_handler_nvoc.c SRCS += generated/g_prereq_tracker_nvoc.c SRCS += generated/g_profiler_v1_nvoc.c SRCS += generated/g_profiler_v2_nvoc.c @@ -136,6 +149,10 @@ SRCS += generated/g_rs_client_nvoc.c SRCS += generated/g_rs_resource_nvoc.c SRCS += generated/g_rs_server_nvoc.c +SRCS += generated/g_sec2_context_nvoc.c +SRCS += generated/g_sec2_utils_nvoc.c +SRCS += generated/g_sem_surf_nvoc.c +SRCS += generated/g_spdm_nvoc.c SRCS += generated/g_standard_mem_nvoc.c SRCS += generated/g_subdevice_diag_nvoc.c SRCS += generated/g_subdevice_nvoc.c @@ -157,6 +174,7 @@ SRCS += generated/g_vblank_callback_nvoc.c SRCS += generated/g_vgpuconfigapi_nvoc.c SRCS += generated/g_video_mem_nvoc.c +SRCS += generated/g_vidmem_access_bit_buffer_nvoc.c SRCS += generated/g_virt_mem_allocator_nvoc.c SRCS += generated/g_virt_mem_mgr_nvoc.c SRCS += generated/g_virt_mem_range_nvoc.c @@ -242,6 +260,7 @@ SRCS += ../common/nvswitch/kernel/spi_nvswitch.c SRCS += arch/nvalloc/unix/src/asm/x86/nv_cpuid.c SRCS += arch/nvalloc/unix/src/asm/x86/nv_rdcr.c +SRCS += arch/nvalloc/unix/src/dynamic-power.c SRCS += arch/nvalloc/unix/src/escape.c SRCS += arch/nvalloc/unix/src/exports-stubs.c SRCS += arch/nvalloc/unix/src/gcc_helper.c @@ -258,13 +277,21 @@ SRCS += arch/nvalloc/unix/src/subdevice_ctrl_os_unix.c SRCS += arch/nvalloc/unix/src/unix_console.c SRCS += arch/nvalloc/unix/src/unix_intr.c +SRCS += arch/nvalloc/unix/src/vbioscall.c +SRCS += arch/nvalloc/unix/x86emu/debug.c +SRCS += arch/nvalloc/unix/x86emu/decode.c +SRCS += arch/nvalloc/unix/x86emu/fpu.c +SRCS += arch/nvalloc/unix/x86emu/ops.c +SRCS += arch/nvalloc/unix/x86emu/ops2.c +SRCS += arch/nvalloc/unix/x86emu/prim_ops.c +SRCS += arch/nvalloc/unix/x86emu/sys.c SRCS += interface/deprecated/rmapi_deprecated_allocmemory.c SRCS += interface/deprecated/rmapi_deprecated_control.c SRCS += interface/deprecated/rmapi_deprecated_misc.c SRCS += interface/deprecated/rmapi_deprecated_utils.c SRCS += interface/deprecated/rmapi_deprecated_vidheapctrl.c SRCS += interface/deprecated/rmapi_gss_legacy_control.c -SRCS += interface/rmapi/src/finn_rm_api.c +SRCS += interface/rmapi/src/g_finn_rm_api.c SRCS += kernel/nvd/nv/dbgbuffer.c SRCS += kernel/nvd/nv/nvdctrl.c SRCS += kernel/vgpu/nv/objvgpu.c @@ -293,8 +320,10 @@ SRCS += src/kernel/gpu/arch/ampere/kern_gpu_ga100.c SRCS += src/kernel/gpu/arch/hopper/kern_gpu_gh100.c SRCS += src/kernel/gpu/arch/maxwell/kern_gpu_gm107.c +SRCS += src/kernel/gpu/arch/pascal/kern_gpu_gp100.c SRCS += src/kernel/gpu/arch/turing/kern_gpu_tu102.c SRCS += src/kernel/gpu/audio/hda_codec_api.c +SRCS += src/kernel/gpu/bif/arch/ada/kernel_bif_ad102.c SRCS += src/kernel/gpu/bif/arch/ampere/kernel_bif_ga100.c SRCS += src/kernel/gpu/bif/arch/hopper/kernel_bif_gh100.c SRCS += src/kernel/gpu/bif/arch/maxwell/kernel_bif_gm107.c @@ -327,6 +356,12 @@ SRCS += src/kernel/gpu/ce/kernel_ce_context.c SRCS += src/kernel/gpu/ce/kernel_ce_ctrl.c SRCS += src/kernel/gpu/ce/kernel_ce_shared.c +SRCS += src/kernel/gpu/conf_compute/arch/hopper/conf_compute_gh100.c +SRCS += src/kernel/gpu/conf_compute/arch/hopper/conf_compute_keystore_gh100.c +SRCS += src/kernel/gpu/conf_compute/ccsl.c +SRCS += src/kernel/gpu/conf_compute/conf_compute.c +SRCS += src/kernel/gpu/conf_compute/conf_compute_api.c +SRCS += src/kernel/gpu/conf_compute/conf_compute_keystore.c SRCS += src/kernel/gpu/deferred_api.c SRCS += src/kernel/gpu/device.c SRCS += src/kernel/gpu/device_ctrl.c @@ -341,7 +376,7 @@ SRCS += src/kernel/gpu/disp/disp_object_kern_ctrl_minimal.c SRCS += src/kernel/gpu/disp/disp_objs.c SRCS += src/kernel/gpu/disp/disp_sf_user.c -SRCS += src/kernel/gpu/disp/head/arch/v04/kernel_head_gpu_0400.c +SRCS += src/kernel/gpu/disp/head/arch/v04/kernel_head_0400.c SRCS += src/kernel/gpu/disp/head/kernel_head.c SRCS += src/kernel/gpu/disp/inst_mem/arch/v03/disp_inst_mem_0300.c SRCS += src/kernel/gpu/disp/inst_mem/disp_inst_mem.c @@ -358,24 +393,24 @@ SRCS += src/kernel/gpu/external_device/kern_external_device.c SRCS += src/kernel/gpu/falcon/arch/ampere/kernel_falcon_ga100.c SRCS += src/kernel/gpu/falcon/arch/ampere/kernel_falcon_ga102.c +SRCS += src/kernel/gpu/falcon/arch/turing/kernel_crashcat_engine_tu102.c SRCS += src/kernel/gpu/falcon/arch/turing/kernel_falcon_tu102.c +SRCS += src/kernel/gpu/falcon/kernel_crashcat_engine.c SRCS += src/kernel/gpu/falcon/kernel_falcon.c +SRCS += src/kernel/gpu/falcon/kernel_falcon_ctrl.c SRCS += src/kernel/gpu/fifo/arch/ampere/kernel_channel_ga100.c SRCS += src/kernel/gpu/fifo/arch/ampere/kernel_channel_ga10b.c SRCS += src/kernel/gpu/fifo/arch/ampere/kernel_fifo_ga100.c SRCS += src/kernel/gpu/fifo/arch/ampere/kernel_fifo_ga102.c SRCS += src/kernel/gpu/fifo/arch/hopper/kernel_channel_gh100.c SRCS += src/kernel/gpu/fifo/arch/hopper/kernel_fifo_gh100.c -SRCS += src/kernel/gpu/fifo/arch/hopper/usermode_api_gh100.c SRCS += src/kernel/gpu/fifo/arch/maxwell/kernel_channel_gm107.c -SRCS += src/kernel/gpu/fifo/arch/maxwell/kernel_channel_group_gm107.c SRCS += src/kernel/gpu/fifo/arch/maxwell/kernel_fifo_gm107.c SRCS += src/kernel/gpu/fifo/arch/pascal/kernel_fifo_gp102.c SRCS += src/kernel/gpu/fifo/arch/turing/kernel_fifo_tu102.c SRCS += src/kernel/gpu/fifo/arch/volta/kernel_channel_group_gv100.c SRCS += src/kernel/gpu/fifo/arch/volta/kernel_channel_gv100.c SRCS += src/kernel/gpu/fifo/arch/volta/kernel_fifo_gv100.c -SRCS += src/kernel/gpu/fifo/arch/volta/usermode_api_gv100.c SRCS += src/kernel/gpu/fifo/channel_descendant.c SRCS += src/kernel/gpu/fifo/kernel_channel.c SRCS += src/kernel/gpu/fifo/kernel_channel_group.c @@ -449,6 +484,7 @@ SRCS += src/kernel/gpu/intr/intr.c SRCS += src/kernel/gpu/intr/intr_service.c SRCS += src/kernel/gpu/intr/swintr.c +SRCS += src/kernel/gpu/kern_gpu_power.c SRCS += src/kernel/gpu/mc/arch/ampere/kernel_mc_ga100.c SRCS += src/kernel/gpu/mc/arch/maxwell/kernel_mc_gm107.c SRCS += src/kernel/gpu/mc/kernel_mc.c @@ -468,6 +504,8 @@ SRCS += src/kernel/gpu/mem_mgr/arch/turing/mem_mgr_tu102.c SRCS += src/kernel/gpu/mem_mgr/arch/turing/mem_mgr_tu102_base.c SRCS += src/kernel/gpu/mem_mgr/arch/volta/mem_mgr_gv100.c +SRCS += src/kernel/gpu/mem_mgr/ce_utils.c +SRCS += src/kernel/gpu/mem_mgr/channel_utils.c SRCS += src/kernel/gpu/mem_mgr/context_dma.c SRCS += src/kernel/gpu/mem_mgr/dma.c SRCS += src/kernel/gpu/mem_mgr/fbsr.c @@ -484,11 +522,12 @@ SRCS += src/kernel/gpu/mem_mgr/mem_utils.c SRCS += src/kernel/gpu/mem_mgr/method_notification.c SRCS += src/kernel/gpu/mem_mgr/objheap.c -SRCS += src/kernel/gpu/mem_mgr/phys_mem_allocator/addrtree.c SRCS += src/kernel/gpu/mem_mgr/phys_mem_allocator/numa.c SRCS += src/kernel/gpu/mem_mgr/phys_mem_allocator/phys_mem_allocator.c SRCS += src/kernel/gpu/mem_mgr/phys_mem_allocator/phys_mem_allocator_util.c SRCS += src/kernel/gpu/mem_mgr/phys_mem_allocator/regmap.c +SRCS += src/kernel/gpu/mem_mgr/sec2_utils.c +SRCS += src/kernel/gpu/mem_mgr/sem_surf.c SRCS += src/kernel/gpu/mem_mgr/vaspace_api.c SRCS += src/kernel/gpu/mem_mgr/virt_mem_allocator.c SRCS += src/kernel/gpu/mem_mgr/virt_mem_allocator_vgpu.c @@ -531,6 +570,7 @@ SRCS += src/kernel/gpu/mmu/mmu_fault_buffer_ctrl.c SRCS += src/kernel/gpu/mmu/mmu_trace.c SRCS += src/kernel/gpu/mmu/uvm_sw.c +SRCS += src/kernel/gpu/mmu/vidmem_access_bit_buffer_v2.c SRCS += src/kernel/gpu/nvdec/kernel_nvdec_ctx.c SRCS += src/kernel/gpu/nvdec/kernel_nvdec_engdesc.c SRCS += src/kernel/gpu/nvenc/kernel_nvenc_ctx.c @@ -560,7 +600,6 @@ SRCS += src/kernel/gpu/perf/kern_perf_pm.c SRCS += src/kernel/gpu/perf/kern_perf_pwr.c SRCS += src/kernel/gpu/perf/kern_perfbuffer.c -SRCS += src/kernel/gpu/pmu/arch/ada/kern_pmu_ad102.c SRCS += src/kernel/gpu/pmu/kern_pmu.c SRCS += src/kernel/gpu/rc/kernel_rc.c SRCS += src/kernel/gpu/rc/kernel_rc_callback.c @@ -572,8 +611,14 @@ SRCS += src/kernel/gpu/rc/kernel_rc_watchdog_ctrl.c SRCS += src/kernel/gpu/sec2/arch/ampere/kernel_sec2_ga100.c SRCS += src/kernel/gpu/sec2/arch/ampere/kernel_sec2_ga102.c +SRCS += src/kernel/gpu/sec2/arch/hopper/kernel_sec2_gh100.c SRCS += src/kernel/gpu/sec2/arch/turing/kernel_sec2_tu102.c SRCS += src/kernel/gpu/sec2/kernel_sec2.c +SRCS += src/kernel/gpu/sec2/sec2_context.c +SRCS += src/kernel/gpu/spdm/arch/hopper/spdm_certs_gh100.c +SRCS += src/kernel/gpu/spdm/arch/hopper/spdm_gh100.c +SRCS += src/kernel/gpu/spdm/arch/hopper/spdm_module.c +SRCS += src/kernel/gpu/spdm/spdm.c SRCS += src/kernel/gpu/subdevice/generic_engine.c SRCS += src/kernel/gpu/subdevice/subdevice.c SRCS += src/kernel/gpu/subdevice/subdevice_ctrl_event_kernel.c @@ -604,8 +649,10 @@ SRCS += src/kernel/gpu_mgr/gpu_group.c SRCS += src/kernel/gpu_mgr/gpu_mgmt_api.c SRCS += src/kernel/gpu_mgr/gpu_mgr.c +SRCS += src/kernel/gpu_mgr/gpu_mgr_sli.c SRCS += src/kernel/mem_mgr/console_mem.c SRCS += src/kernel/mem_mgr/ctx_buf_pool.c +SRCS += src/kernel/mem_mgr/egm_mem.c SRCS += src/kernel/mem_mgr/fabric_vaspace.c SRCS += src/kernel/mem_mgr/fla_mem.c SRCS += src/kernel/mem_mgr/gpu_vaspace.c @@ -645,11 +692,15 @@ SRCS += src/kernel/platform/nbsi/nbsi_osrg.c SRCS += src/kernel/platform/p2p/p2p_caps.c SRCS += src/kernel/platform/platform.c +SRCS += src/kernel/platform/platform_request_handler.c +SRCS += src/kernel/platform/platform_request_handler_ctrl.c +SRCS += src/kernel/platform/sli/sli.c SRCS += src/kernel/power/gpu_boost_mgr.c SRCS += src/kernel/rmapi/alloc_free.c SRCS += src/kernel/rmapi/binary_api.c SRCS += src/kernel/rmapi/client.c SRCS += src/kernel/rmapi/client_resource.c +SRCS += src/kernel/rmapi/client_resource_sli.c SRCS += src/kernel/rmapi/control.c SRCS += src/kernel/rmapi/deprecated_context.c SRCS += src/kernel/rmapi/embedded_param_copy.c @@ -666,6 +717,7 @@ SRCS += src/kernel/rmapi/resource_desc.c SRCS += src/kernel/rmapi/rmapi.c SRCS += src/kernel/rmapi/rmapi_cache.c +SRCS += src/kernel/rmapi/rmapi_finn.c SRCS += src/kernel/rmapi/rmapi_stubs.c SRCS += src/kernel/rmapi/rmapi_utils.c SRCS += src/kernel/rmapi/rpc_common.c @@ -692,9 +744,63 @@ SRCS += src/libraries/containers/map.c SRCS += src/libraries/containers/multimap.c SRCS += src/libraries/containers/queue.c +SRCS += src/libraries/containers/ringbuf.c +SRCS += src/libraries/containers/vector.c +SRCS += src/libraries/crashcat/crashcat_engine.c +SRCS += src/libraries/crashcat/crashcat_queue.c +SRCS += src/libraries/crashcat/crashcat_report.c +SRCS += src/libraries/crashcat/crashcat_wayfinder.c +SRCS += src/libraries/crashcat/v1/crashcat_queue_v1.c +SRCS += src/libraries/crashcat/v1/crashcat_report_v1.c +SRCS += src/libraries/crashcat/v1/crashcat_wayfinder_v1.c +SRCS += src/libraries/crashcat/v1/impl/crashcat_report_v1_generic.c +SRCS += src/libraries/crashcat/v1/impl/crashcat_report_v1_libos2.c +SRCS += src/libraries/crashcat/v1/impl/crashcat_report_v1_libos3.c SRCS += src/libraries/eventbuffer/eventbufferproducer.c SRCS += src/libraries/fnv_hash/fnv_hash.c SRCS += src/libraries/ioaccess/ioaccess.c +SRCS += src/libraries/libspdm/2.3.1/library/spdm_common_lib/libspdm_com_context_data.c +SRCS += src/libraries/libspdm/2.3.1/library/spdm_common_lib/libspdm_com_context_data_session.c +SRCS += src/libraries/libspdm/2.3.1/library/spdm_common_lib/libspdm_com_crypto_service.c +SRCS += src/libraries/libspdm/2.3.1/library/spdm_common_lib/libspdm_com_crypto_service_session.c +SRCS += src/libraries/libspdm/2.3.1/library/spdm_common_lib/libspdm_com_msg_log.c +SRCS += src/libraries/libspdm/2.3.1/library/spdm_common_lib/libspdm_com_opaque_data.c +SRCS += src/libraries/libspdm/2.3.1/library/spdm_common_lib/libspdm_com_support.c +SRCS += src/libraries/libspdm/2.3.1/library/spdm_crypt_lib/libspdm_crypt_aead.c +SRCS += src/libraries/libspdm/2.3.1/library/spdm_crypt_lib/libspdm_crypt_asym.c +SRCS += src/libraries/libspdm/2.3.1/library/spdm_crypt_lib/libspdm_crypt_cert.c +SRCS += src/libraries/libspdm/2.3.1/library/spdm_crypt_lib/libspdm_crypt_dhe.c +SRCS += src/libraries/libspdm/2.3.1/library/spdm_crypt_lib/libspdm_crypt_hash.c +SRCS += src/libraries/libspdm/2.3.1/library/spdm_crypt_lib/libspdm_crypt_hkdf.c +SRCS += src/libraries/libspdm/2.3.1/library/spdm_crypt_lib/libspdm_crypt_hmac.c +SRCS += src/libraries/libspdm/2.3.1/library/spdm_crypt_lib/libspdm_crypt_rng.c +SRCS += src/libraries/libspdm/2.3.1/library/spdm_requester_lib/libspdm_req_common.c +SRCS += src/libraries/libspdm/2.3.1/library/spdm_requester_lib/libspdm_req_communication.c +SRCS += src/libraries/libspdm/2.3.1/library/spdm_requester_lib/libspdm_req_end_session.c +SRCS += src/libraries/libspdm/2.3.1/library/spdm_requester_lib/libspdm_req_finish.c +SRCS += src/libraries/libspdm/2.3.1/library/spdm_requester_lib/libspdm_req_get_capabilities.c +SRCS += src/libraries/libspdm/2.3.1/library/spdm_requester_lib/libspdm_req_get_certificate.c +SRCS += src/libraries/libspdm/2.3.1/library/spdm_requester_lib/libspdm_req_get_digests.c +SRCS += src/libraries/libspdm/2.3.1/library/spdm_requester_lib/libspdm_req_get_measurements.c +SRCS += src/libraries/libspdm/2.3.1/library/spdm_requester_lib/libspdm_req_get_version.c +SRCS += src/libraries/libspdm/2.3.1/library/spdm_requester_lib/libspdm_req_handle_error_response.c +SRCS += src/libraries/libspdm/2.3.1/library/spdm_requester_lib/libspdm_req_key_exchange.c +SRCS += src/libraries/libspdm/2.3.1/library/spdm_requester_lib/libspdm_req_key_update.c +SRCS += src/libraries/libspdm/2.3.1/library/spdm_requester_lib/libspdm_req_negotiate_algorithms.c +SRCS += src/libraries/libspdm/2.3.1/library/spdm_requester_lib/libspdm_req_send_receive.c +SRCS += src/libraries/libspdm/2.3.1/library/spdm_secured_message_lib/libspdm_secmes_context_data.c +SRCS += src/libraries/libspdm/2.3.1/library/spdm_secured_message_lib/libspdm_secmes_encode_decode.c +SRCS += src/libraries/libspdm/2.3.1/library/spdm_secured_message_lib/libspdm_secmes_key_exchange.c +SRCS += src/libraries/libspdm/2.3.1/library/spdm_secured_message_lib/libspdm_secmes_session.c +SRCS += src/libraries/libspdm/2.3.1/os_stub/memlib/compare_mem.c +SRCS += src/libraries/libspdm/2.3.1/os_stub/platform_lib_null/time_linux.c +SRCS += src/libraries/libspdm/2.3.1/os_stub/platform_lib_null/watchdog.c +SRCS += src/libraries/libspdm/2.3.1/os_stub/spdm_device_secret_lib_null/lib.c +SRCS += src/libraries/libspdm/nvidia/nvspdm_crypt_null.c +SRCS += src/libraries/libspdm/nvidia/nvspdm_debuglib.c +SRCS += src/libraries/libspdm/nvidia/nvspdm_malloclib.c +SRCS += src/libraries/libspdm/nvidia/nvspdm_memlib.c +SRCS += src/libraries/libspdm/nvidia/nvspdm_rng.c SRCS += src/libraries/mmu/gmmu_fmt.c SRCS += src/libraries/mmu/mmu_fmt.c SRCS += src/libraries/mmu/mmu_walk.c diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia-modeset/Makefile nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia-modeset/Makefile --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia-modeset/Makefile 2023-10-25 20:22:13.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia-modeset/Makefile 2024-03-05 22:11:42.000000000 +0000 @@ -105,6 +105,7 @@ CFLAGS += -ffunction-sections CFLAGS += -fdata-sections CFLAGS += -ffreestanding +CFLAGS += -fno-stack-protector CONDITIONAL_CFLAGS += $(call TEST_CC_ARG, -Wformat-overflow=2) CONDITIONAL_CFLAGS += $(call TEST_CC_ARG, -Wformat-truncation=1) diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia-modeset/include/dp/nvdp-connector.h nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia-modeset/include/dp/nvdp-connector.h --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia-modeset/include/dp/nvdp-connector.h 2023-10-25 20:22:33.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia-modeset/include/dp/nvdp-connector.h 2024-03-05 22:12:10.000000000 +0000 @@ -47,7 +47,9 @@ const NvU32 displayId, const NVDpyIdList dpyIdList, const enum NvKmsDpyAttributeCurrentColorSpaceValue colorSpace, - NVHwModeTimingsEvo *pTimings); + const enum NvKmsDpyAttributeColorBpcValue colorBpc, + const NVHwModeTimingsEvo *pTimings, + const NVDscInfoEvoRec *pDscInfo); void nvDPLibFreeModesetState(NVDPLibModesetStatePtr pDpLibModesetState); @@ -59,21 +61,28 @@ const NvU32 displayId, const NVDpyIdList dpyIdList, const enum NvKmsDpyAttributeCurrentColorSpaceValue colorSpace, + const enum NvKmsDpyAttributeColorBpcValue colorBpc, const struct NvKmsModeValidationParams *pModeValidationParams, - NVHwModeTimingsEvo *pTimings); + const NVHwModeTimingsEvo *pTimings, + const NvBool b2Heads1Or, + NVDscInfoEvoRec *pDscInfo); NvBool nvDPEndValidation(NVDispEvoPtr pDispEvo); NvBool nvDPValidateModeForDpyEvo( const NVDpyEvoRec *pDpyEvo, const enum NvKmsDpyAttributeCurrentColorSpaceValue colorSpace, + const enum NvKmsDpyAttributeColorBpcValue colorBpc, const struct NvKmsModeValidationParams *pModeValidationParams, - NVHwModeTimingsEvo *pTimings); + const NVHwModeTimingsEvo *pTimings, + const NvBool b2Heads1Or, + NVDscInfoEvoRec *pDscInfo); void nvDPPreSetMode(NVDPLibConnectorPtr pDpLibConnector, const NVEvoModesetUpdateState *pModesetUpdateState); -void nvDPPostSetMode(NVDPLibConnectorPtr pDpLibConnector); +void nvDPPostSetMode(NVDPLibConnectorPtr pDpLibConnector, + const NVEvoModesetUpdateState *pModesetUpdateState); void nvDPPause(NVDPLibConnectorPtr pNVDpLibConnector); diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia-modeset/include/dp/nvdp-device.h nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia-modeset/include/dp/nvdp-device.h --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia-modeset/include/dp/nvdp-device.h 2023-10-25 20:22:33.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia-modeset/include/dp/nvdp-device.h 2024-03-05 22:12:11.000000000 +0000 @@ -35,6 +35,7 @@ NvBool nvDPGetEDID(const NVDpyEvoRec *pDpyEvo, void *buffer, unsigned int size); void nvDPGetDpyGUID(NVDpyEvoPtr pDpyEvo); void nvDPDpyFree(NVDpyEvoPtr pDpyEvo); +NvBool nvDPDpyIsDscPossible(const NVDpyEvoRec *pDpyEvo); #ifdef __cplusplus }; diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia-modeset/include/nvkms-3dvision.h nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia-modeset/include/nvkms-3dvision.h --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia-modeset/include/nvkms-3dvision.h 2023-10-25 20:22:33.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia-modeset/include/nvkms-3dvision.h 2024-03-05 22:12:11.000000000 +0000 @@ -26,7 +26,7 @@ #include "nvkms-types.h" -void nv3DVisionAuthenticationEvo(NVDispEvoRec *pDispEvo, const NvU32 head); +void nv3DVisionAuthenticationEvo(NVDispEvoRec *pDispEvo, const NvU32 apiHead); void nvDpyCheck3DVisionCapsEvo(NVDpyEvoPtr pDpyEvo); NvBool @@ -34,6 +34,6 @@ NVEvoInfoStringPtr pInfoString); void nvDisable3DVisionAegis(const NVDpyEvoRec *pDpyEvo); void nvSendHwModeTimingsToAegisEvo(const NVDispEvoRec *pDispEvo, - const NvU32 head); + const NvU32 apiHead); #endif /* __NVKMS_3DVISION_H__ */ diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia-modeset/include/nvkms-cursor.h nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia-modeset/include/nvkms-cursor.h --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia-modeset/include/nvkms-cursor.h 2023-10-25 20:22:34.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia-modeset/include/nvkms-cursor.h 2024-03-05 22:12:11.000000000 +0000 @@ -36,14 +36,14 @@ NVDispEvoPtr pDispEvo, const struct NvKmsPerOpenDev *pOpenDevice, const NVEvoApiHandlesRec *pOpenDevSurfaceHandles, - NvU32 head, + NvU32 apiHead, const struct NvKmsSetCursorImageCommonParams *pParams); void nvEvoMoveCursorInternal(NVDispEvoPtr pDispEvo, NvU32 head, NvS16 x, NvS16 y); -void nvEvoMoveCursor(NVDispEvoPtr pDispEvo, NvU32 head, - const struct NvKmsMoveCursorCommonParams *pParams); +void nvMoveCursor(NVDispEvoPtr pDispEvo, const NvU32 apiHead, + const struct NvKmsMoveCursorCommonParams *pParams); NvBool nvAllocCursorEvo(NVDevEvoPtr pDevEvo); void nvFreeCursorEvo(NVDevEvoPtr pDevEvo); diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia-modeset/include/nvkms-dpy-override.h nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia-modeset/include/nvkms-dpy-override.h --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia-modeset/include/nvkms-dpy-override.h 1970-01-01 00:00:00.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia-modeset/include/nvkms-dpy-override.h 2024-03-05 22:12:11.000000000 +0000 @@ -0,0 +1,63 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef __NVKMS_DPY_OVERRIDE_H__ +#define __NVKMS_DPY_OVERRIDE_H__ + +#include "nvkms-types.h" + +#ifdef __cplusplus +extern "C" { +#endif + +typedef struct _DpyOverride { + NVListRec entry; + + NvU32 gpuId; + char name[NVKMS_DPY_NAME_SIZE]; + + NvBool connected; + NVEdidRec edid; +} NVDpyOverrideRec, *NVDpyOverridePtr; + +NVDpyOverrideRec *nvCreateDpyOverride(NvU32 gpuId, + const char *name, + NvBool connected, + const char *edid, + size_t edidSize); + +void nvDeleteDpyOverride(NvU32 gpuId, const char *name); + +void nvLogDpyOverrides(NvU32 gpuId, NVEvoInfoStringPtr pInfoStr); + +NVDpyOverridePtr nvDpyEvoGetOverride(const NVDpyEvoRec *pDpyEvo); +size_t nvReadDpyOverrideEdid(const NVDpyOverrideRec *pDpyOverride, NvU8 *buff, + size_t len); + +void nvClearDpyOverrides(void); + +#ifdef __cplusplus +}; +#endif + +#endif /* __NVKMS_DPY_OVERRIDE_H__ */ diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia-modeset/include/nvkms-dpy.h nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia-modeset/include/nvkms-dpy.h --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia-modeset/include/nvkms-dpy.h 2023-10-25 20:22:34.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia-modeset/include/nvkms-dpy.h 2024-03-05 22:12:11.000000000 +0000 @@ -76,11 +76,15 @@ NvBool nvDpyIsAdaptiveSync(const NVDpyEvoRec *pDpyEvo); -NvBool nvDpyIsAdaptiveSyncDefaultlisted(const NVParsedEdidEvoRec *pParsedEdid); +NvBool nvDpyIsAdaptiveSyncDefaultlisted(const NVDpyEvoRec *pDpyEvo); enum NvKmsDpyAttributeDigitalSignalValue nvGetDefaultDpyAttributeDigitalSignalValue(const NVConnectorEvoRec *pConnectorEvo); +NVColorFormatInfoRec nvGetColorFormatInfo(const NVDpyEvoRec *pDpyEvo); + +NvU32 nvDpyGetPossibleApiHeadsMask(const NVDpyEvoRec *pDpyEvo); + #ifdef __cplusplus }; #endif diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia-modeset/include/nvkms-evo-states.h nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia-modeset/include/nvkms-evo-states.h --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia-modeset/include/nvkms-evo-states.h 2023-10-25 20:22:34.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia-modeset/include/nvkms-evo-states.h 2024-03-05 22:12:12.000000000 +0000 @@ -50,6 +50,8 @@ NV_EVO_REM_FRAME_LOCK_CLIENT, NV_EVO_ENABLE_VRR, NV_EVO_DISABLE_VRR, + NV_EVO_ENABLE_MERGE_MODE, + NV_EVO_DISABLE_MERGE_MODE, NV_EVO_ADD_FRAME_LOCK_REF, NV_EVO_REM_FRAME_LOCK_REF, NV_EVO_ADD_SLI_SECONDARY, @@ -72,6 +74,8 @@ /* nvkms-hw-states.c */ +NvBool nvEvoLockHWStateNoChange(NVDispEvoPtr, NVEvoSubDevPtr, const NvU32 *pHeads); +NvBool nvEvoLockHWStateMergeMode(NVDispEvoPtr, NVEvoSubDevPtr, const NvU32 *pHeads); NvBool nvEvoLockHWStateNoLock(NVDispEvoPtr, NVEvoSubDevPtr, const NvU32 *pHeads); NvBool nvEvoLockHWStateLockHeads(NVDispEvoPtr, NVEvoSubDevPtr, const NvU32 *pHeads); NvBool nvEvoLockHWStateFrameLockClient(NVDispEvoPtr, NVEvoSubDevPtr, const NvU32 *pHeads); diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia-modeset/include/nvkms-evo.h nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia-modeset/include/nvkms-evo.h --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia-modeset/include/nvkms-evo.h 2023-10-25 20:22:34.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia-modeset/include/nvkms-evo.h 2024-03-05 22:12:12.000000000 +0000 @@ -25,7 +25,6 @@ #define __NVKMS_H__ #include "nvkms-types.h" -#include "nvkms-modeset-types.h" #include "nvkms-api.h" #ifdef __cplusplus @@ -40,6 +39,7 @@ NVEvoModesetUpdateState *pModesetUpdateState); void nvEvoAttachConnector(NVConnectorEvoRec *pConnectorEvo, const NvU32 head, + const NvU32 isPrimaryHead, NVDPLibModesetStatePtr pDpLibModesetState, NVEvoModesetUpdateState *pModesetUpdateState); void nvEvoUpdateAndKickOff(const NVDispEvoRec *pDispEvo, NvBool sync, @@ -85,6 +85,9 @@ void nvUnionUsageBounds(const struct NvKmsUsageBounds *a, const struct NvKmsUsageBounds *b, struct NvKmsUsageBounds *ret); +void nvIntersectUsageBounds(const struct NvKmsUsageBounds *a, + const struct NvKmsUsageBounds *b, + struct NvKmsUsageBounds *ret); NvBool UsageBoundsEqual(const struct NvKmsUsageBounds *a, const struct NvKmsUsageBounds *b); NvU64 nvEvoGetFormatsWithEqualOrLowerUsageBound( @@ -113,7 +116,7 @@ void nvChooseDitheringEvo( const NVConnectorEvoRec *pConnectorEvo, - const enum nvKmsPixelDepth pixelDepth, + enum NvKmsDpyAttributeColorBpcValue bpc, const NVDpyAttributeRequestedDitheringConfig *pReqDithering, NVDpyAttributeCurrentDitheringConfig *pCurrDithering); @@ -126,6 +129,7 @@ NvBool nvEnableFrameLockEvo(NVDispEvoPtr pDispEvo); NvBool nvDisableFrameLockEvo(NVDispEvoPtr pDispEvo); NvBool nvQueryRasterLockEvo(const NVDpyEvoRec *pDpyEvo, NvS64 *val); +void nvInvalidateTopologiesEvo(void); NvBool nvSetFlipLockEvo(NVDpyEvoPtr pDpyEvo, NvS64 value); NvBool nvGetFlipLockEvo(const NVDpyEvoRec *pDpyEvo, NvS64 *pValue); NvBool nvAllowFlipLockEvo(NVDispEvoPtr pDispEvo, NvS64 value); @@ -160,18 +164,28 @@ NvBool nvConstructHwModeTimingsImpCheckEvo( const NVConnectorEvoRec *pConnectorEvo, - NVHwModeTimingsEvoPtr pTimings, - const struct NvKmsModeValidationParams *pParams, - NVEvoInfoStringPtr pInfoString, - const int head); - -NvBool nvDowngradeHwModeTimingsDpPixelDepthEvo( - NVHwModeTimingsEvoPtr pTimings, + const NVHwModeTimingsEvo *pTimings, + const NvBool enableDsc, + const NvBool b2Heads1Or, const enum NvKmsDpyAttributeCurrentColorSpaceValue colorSpace, - const enum NvKmsDpyAttributeColorRangeValue colorRange); + const enum NvKmsDpyAttributeColorBpcValue colorBpc, + const struct NvKmsModeValidationParams *pParams, + NVHwModeTimingsEvo timings[NVKMS_MAX_HEADS_PER_DISP], + NvU32 *pNumHeads, + NVEvoInfoStringPtr pInfoString); + +NvBool nvDowngradeColorSpaceAndBpc( + const NVColorFormatInfoRec *pSupportedColorFormats, + enum NvKmsDpyAttributeCurrentColorSpaceValue *pColorSpace, + enum NvKmsDpyAttributeColorBpcValue *pColorBpc, + enum NvKmsDpyAttributeColorRangeValue *pColorRange); NvBool nvDPValidateModeEvo(NVDpyEvoPtr pDpyEvo, NVHwModeTimingsEvoPtr pTimings, + enum NvKmsDpyAttributeCurrentColorSpaceValue *pColorSpace, + enum NvKmsDpyAttributeColorBpcValue *pColorBpc, + const NvBool b2Heads1Or, + NVDscInfoEvoRec *pDscInfo, const struct NvKmsModeValidationParams *pParams); NvBool nvEvoUpdateHwModeTimingsViewPort( @@ -186,7 +200,10 @@ const NVConnectorEvoRec *pConnectorEvo; const struct NvKmsUsageBounds *pUsage; NvU32 activeRmId; + enum nvKmsPixelDepth pixelDepth; NVHwModeTimingsEvoPtr pTimings; + NvBool enableDsc; + NvBool b2Heads1Or; } NVValidateImpOneDispHeadParamsRec; NvBool nvValidateImpOneDisp( @@ -212,19 +229,27 @@ NvBool nvFrameLockServerPossibleEvo(const NVDpyEvoRec *pDpyEvo); NvBool nvFrameLockClientPossibleEvo(const NVDpyEvoRec *pDpyEvo); -void nvEvoSetLut(NVDispEvoPtr pDispEvo, NvU32 head, NvBool kickoff, +void nvEvoSetLut(NVDispEvoPtr pDispEvo, NvU32 apiHead, NvBool kickoff, const struct NvKmsSetLutCommonParams *pParams); NvBool nvValidateSetLutCommonParams( const NVDevEvoRec *pDevEvo, const struct NvKmsSetLutCommonParams *pParams); -void nvChooseCurrentColorSpaceAndRangeEvo( - enum nvKmsPixelDepth pixelDepth, +NvBool nvChooseColorRangeEvo( + enum NvKmsOutputTf tf, + const enum NvKmsDpyAttributeColorRangeValue requestedColorRange, + const enum NvKmsDpyAttributeCurrentColorSpaceValue colorSpace, + const enum NvKmsDpyAttributeColorBpcValue colorBpc, + enum NvKmsDpyAttributeColorRangeValue *pColorRange); + +NvBool nvChooseCurrentColorSpaceAndRangeEvo( + const NVDpyEvoRec *pDpyEvo, enum NvYuv420Mode yuv420Mode, enum NvKmsOutputTf tf, const enum NvKmsDpyAttributeRequestedColorSpaceValue requestedColorSpace, const enum NvKmsDpyAttributeColorRangeValue requestedColorRange, enum NvKmsDpyAttributeCurrentColorSpaceValue *pCurrentColorSpace, + enum NvKmsDpyAttributeColorBpcValue *pCurrentColorBpc, enum NvKmsDpyAttributeColorRangeValue *pCurrentColorRange); void nvUpdateCurrentHardwareColorSpaceAndRangeEvo( @@ -234,7 +259,8 @@ const enum NvKmsDpyAttributeColorRangeValue colorRange, NVEvoUpdateState *pUpdateState); -NvBool nvAssignSOREvo(NVConnectorEvoPtr pConnectorEvo, NvU32 sorExcludeMask); +NvBool nvAssignSOREvo(const NVDispEvoRec *pDispEvo, const NvU32 displayId, + const NvBool b2Heads1Or, const NvU32 sorExcludeMask); void nvSetSwapBarrierNotifyEvo(NVDispEvoPtr pDispEvo, NvBool enable, NvBool isPre); @@ -253,8 +279,8 @@ NvBool *needsEarlyUpdate, NVEvoUpdateState *updateState); -void nvEvoUpdateCurrentPalette(NVDispEvoPtr pDispEvo, - NvU32 head, NvBool kickOff); +void nvEvoSetLUTContextDma(NVDispEvoPtr pDispEvo, + const NvU32 head, NVEvoUpdateState *pUpdateState); NvBool nvEvoPollForNoMethodPending(NVDevEvoPtr pDevEvo, const NvU32 sd, @@ -293,7 +319,7 @@ NvBool nvFramelockSetControlUnsyncEvo(NVDispEvoPtr pDispEvo, const NvU32 headMask, NvBool server); -NvBool nvIsHDRCapableHead(NVDispEvoPtr pDispEvo, +NvBool nvIsHDRCapableHead(const NVDispEvoRec *pDispEvo, NvU32 apiHead); NvU32 nvGetHDRSrcMaxLum(const NVFlipChannelEvoHwState *pHwState); @@ -306,9 +332,65 @@ NvBool nvIsCscMatrixIdentity(const struct NvKmsCscMatrix *matrix); +enum nvKmsPixelDepth nvEvoColorSpaceBpcToPixelDepth( + const enum NvKmsDpyAttributeCurrentColorSpaceValue colorSpace, + const enum NvKmsDpyAttributeColorBpcValue colorBpc); + void nvSuspendDevEvo(NVDevEvoRec *pDevEvo); NvBool nvResumeDevEvo(NVDevEvoRec *pDevEvo); +NvBool nvGetDefaultColorSpace( + const NVColorFormatInfoRec *pColorFormatsInfo, + enum NvKmsDpyAttributeCurrentColorSpaceValue *pColorSpace, + enum NvKmsDpyAttributeColorBpcValue *pColorBpc); + +static inline void nvEvoSetFlipOccurredEvent(const NVDispEvoRec *pDispEvo, + const NvU32 head, + const NvU32 layer, + struct nvkms_ref_ptr *ref_ptr, + NVEvoModesetUpdateState + *pModesetUpdate) +{ + nvAssert((head < pDispEvo->pDevEvo->numHeads) && + (layer < pDispEvo->pDevEvo->head[head].numLayers)); + pModesetUpdate->flipOccurredEvent[head].layer[layer].ref_ptr = ref_ptr; + pModesetUpdate->flipOccurredEvent[head].layer[layer].changed = TRUE; +} + +void nvEvoPreModesetRegisterFlipOccurredEvent(NVDispEvoRec *pDispEvo, + const NvU32 head, + const NVEvoModesetUpdateState + *pModesetUpdate); + +void nvEvoPostModesetUnregisterFlipOccurredEvent(NVDispEvoRec *pDispEvo, + const NvU32 head, + const NVEvoModesetUpdateState + *pModesetUpdate); + +void nvEvoLockStateSetMergeMode(NVDispEvoPtr pDispEvo); + +void nvEvoEnableMergeModePreModeset(NVDispEvoRec *pDispEvo, + const NvU32 headsMask, + NVEvoUpdateState *pUpdateState); +void nvEvoEnableMergeModePostModeset(NVDispEvoRec *pDispEvo, + const NvU32 headsMask, + NVEvoUpdateState *pUpdateState); +void nvEvoDisableMergeMode(NVDispEvoRec *pDispEvo, + const NvU32 headsMask, + NVEvoUpdateState *pUpdateState); + +void nvEvoDisableHwYUV420Packer(const NVDispEvoRec *pDispEvo, + const NvU32 head, + NVEvoUpdateState *pUpdateState); + +NvBool nvEvoGetSingleTileHwModeTimings(const NVHwModeTimingsEvo *pSrc, + const NvU32 numTiles, + NVHwModeTimingsEvo *pDst); + +NvBool nvEvoUse2Heads1OR(const NVDpyEvoRec *pDpyEvo, + const NVHwModeTimingsEvo *pTimings, + const struct NvKmsModeValidationParams *pParams); + #ifdef __cplusplus }; #endif diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia-modeset/include/nvkms-evo1.h nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia-modeset/include/nvkms-evo1.h --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia-modeset/include/nvkms-evo1.h 2023-10-25 20:22:34.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia-modeset/include/nvkms-evo1.h 2024-03-05 22:12:12.000000000 +0000 @@ -38,7 +38,8 @@ void nvEvo1SetDscParams(const NVDispEvoRec *pDispEvo, const NvU32 head, - const NVHwModeTimingsEvo *pTimings); + const NVDscInfoEvoRec *pDscInfo, + const enum nvKmsPixelDepth pixelDepth); NVEvoChannel* nvEvo1AllocateCoreChannel(NVDevEvoRec *pDevEvo); void nvEvo1FreeCoreChannel(NVDevEvoRec *pDevEvo, NVEvoChannel *pChannel); diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia-modeset/include/nvkms-flip-workarea.h nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia-modeset/include/nvkms-flip-workarea.h --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia-modeset/include/nvkms-flip-workarea.h 2023-10-25 20:22:34.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia-modeset/include/nvkms-flip-workarea.h 2024-03-05 22:12:12.000000000 +0000 @@ -26,6 +26,22 @@ #include "nvkms-types.h" +typedef struct { + struct { + enum NvKmsOutputTf tf; + enum NvKmsDpyAttributeCurrentColorSpaceValue colorSpace; + enum NvKmsDpyAttributeColorBpcValue colorBpc; + enum NvKmsDpyAttributeColorRangeValue colorRange; + } hdr; + + struct NvKmsPoint viewPortPointIn; + + struct { + NvU32 viewPortPointIn : 1; + NvU32 hdr : 1; + } dirty; +} NVProposedFlipStateOneApiHead; + struct NvKmsFlipWorkArea { struct { NvBool changed; @@ -43,6 +59,14 @@ NVFlipEvoHwState oldState; } head[NVKMS_MAX_HEADS_PER_DISP]; } sd[NVKMS_MAX_SUBDEVICES]; + + struct { + struct { + NVProposedFlipStateOneApiHead proposedFlipState; + } apiHead[NVKMS_MAX_HEADS_PER_DISP]; + } disp[NVKMS_MAX_SUBDEVICES]; + + NVEvoUpdateState updateState; }; #endif /* __NVKMS_FLIP_WORKAREA_H__ */ diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia-modeset/include/nvkms-flip.h nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia-modeset/include/nvkms-flip.h --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia-modeset/include/nvkms-flip.h 2023-10-25 20:22:34.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia-modeset/include/nvkms-flip.h 2024-03-05 22:12:12.000000000 +0000 @@ -27,77 +27,19 @@ #include "nvkms-types.h" -void nvClearFlipEvoHwState( - NVFlipEvoHwState *pFlipState); - -void nvInitFlipEvoHwState( - const NVDevEvoRec *pDevEvo, - const NvU32 sd, - const NvU32 head, - NVFlipEvoHwState *pFlipState); - -NvBool nvAssignSurfaceArray( - const NVDevEvoRec *pDevEvo, - const NVEvoApiHandlesRec *pOpenDevSurfaceHandles, - const NvKmsSurfaceHandle surfaceHandles[NVKMS_MAX_EYES], - const NvBool isUsedByCursorChannel, - const NvBool isUsedByLayerChannel, - NVSurfaceEvoPtr pSurfaceEvos[NVKMS_MAX_EYES]); - -NvBool -nvAssignCursorSurface(const struct NvKmsPerOpenDev *pOpenDev, - const NVDevEvoRec *pDevEvo, - const struct NvKmsSetCursorImageCommonParams *pImgParams, - NVSurfaceEvoPtr *pSurfaceEvo); - -NvBool nvUpdateFlipEvoHwState( +NvBool nvCheckFlipPermissions( const struct NvKmsPerOpenDev *pOpenDev, const NVDevEvoRec *pDevEvo, const NvU32 sd, - const NvU32 head, - const struct NvKmsFlipCommonParams *pParams, - NVFlipEvoHwState *pFlipState, - NvBool allowVrr); - -void -nvOverrideScalingUsageBounds(const NVDevEvoRec *pDevEvo, - NvU32 head, - NVFlipEvoHwState *pFlipState, - const struct NvKmsUsageBounds *pPossibleUsage); - -NvBool nvValidateFlipEvoHwState( - const NVDevEvoRec *pDevEvo, - const NvU32 head, - const NVHwModeTimingsEvo *pTimings, - const NVFlipEvoHwState *pFlipState); - -void -nvUpdateSurfacesFlipRefCount( - NVDevEvoPtr pDevEvo, - const NvU32 head, - NVFlipEvoHwState *pFlipState, - NvBool increase); - -void nvFlipEvoOneHead( - NVDevEvoPtr pDevEvo, - const NvU32 sd, - const NvU32 head, - const NVFlipEvoHwState *pFlipState, - NvBool allowFlipLock, - NVEvoUpdateState *updateState); - -void nvEvoCancelPostFlipIMPTimer( - NVDevEvoPtr pDevEvo); - -void nvFillPostSyncptReplyOneChannel( - NVEvoChannel *pChannel, - enum NvKmsSyncptType postType, - struct NvKmsSyncpt *postSyncpt, - const NVFlipSyncObjectEvoHwState *pHwSyncObject); + const NvU32 apiHead, + const struct NvKmsFlipCommonParams *pParams); NvBool nvFlipEvo(NVDevEvoPtr pDevEvo, const struct NvKmsPerOpenDev *pOpenDev, - const struct NvKmsFlipRequest *request, + const struct NvKmsFlipRequestOneHead *pFlipHead, + NvU32 numFlipHeads, + NvBool commit, + NvBool allowVrr, struct NvKmsFlipReply *reply, NvBool skipUpdate, NvBool allowFlipLock); @@ -117,4 +59,47 @@ const NvU16 x, const NvU16 y); +NvU32 nvApiHeadGetActiveViewportOffset(NVDispEvoRec *pDispEvo, + NvU32 apiHead); + +void nvApiHeadIdleMainLayerChannels(NVDevEvoRec *pDevEvo, + const NvU32 apiHeadMaskPerSd[NVKMS_MAX_SUBDEVICES]); + +void nvApiHeadUpdateFlipLock(NVDevEvoRec *pDevEvo, + const NvU32 apiHeadMaskPerSd[NVKMS_MAX_SUBDEVICES], + const NvBool enable); + +void nvCancelSDRTransitionTimer(NVDispApiHeadStateEvoRec *pApiHeadState); + +NvBool nvIdleMainLayerChannelCheckIdleOneApiHead(NVDispEvoPtr pDispEvo, + NvU32 apiHead); + +#define NV_SURFACE_USAGE_MASK_CURSOR 0:0 +#define NV_SURFACE_USAGE_MASK_CURSOR_DISABLE 0 +#define NV_SURFACE_USAGE_MASK_CURSOR_ENABLE 1 +#define NV_SURFACE_USAGE_MASK_LAYER(_n) (3+(3*(_n))):(1+(3*(_n))) + +#define NV_SURFACE_USAGE_MASK_LAYER_SEMAPHORE 1:1 +#define NV_SURFACE_USAGE_MASK_LAYER_SEMAPHORE_DISABLE 0 +#define NV_SURFACE_USAGE_MASK_LAYER_SEMAPHORE_ENABLE 1 +#define NV_SURFACE_USAGE_MASK_LAYER_NOTIFIER 2:2 +#define NV_SURFACE_USAGE_MASK_LAYER_NOTIFIER_DISABLE 0 +#define NV_SURFACE_USAGE_MASK_LAYER_NOTIFIER_ENABLE 1 +#define NV_SURFACE_USAGE_MASK_LAYER_SCANOUT 0:0 +#define NV_SURFACE_USAGE_MASK_LAYER_SCANOUT_DISABLE 0 +#define NV_SURFACE_USAGE_MASK_LAYER_SCANOUT_ENABLE 1 + +NvU32 nvCollectSurfaceUsageMaskOneApiHead(const NVDispEvoRec *pDispEvo, + const NvU32 apiHead, + NVSurfaceEvoPtr pSurfaceEvo); + +void nvIdleLayerChannels(NVDevEvoRec *pDevEvo, + NvU32 layerMaskPerSdApiHead[NVKMS_MAX_SUBDEVICES][NVKMS_MAX_HEADS_PER_DISP]); + +void nvEvoClearSurfaceUsage(NVDevEvoRec *pDevEvo, + NVSurfaceEvoPtr pSurfaceEvo); + +NvBool nvIdleBaseChannelOneApiHead(NVDispEvoRec *pDispEvo, NvU32 apiHead, + NvBool *pStoppedBase); + #endif /* __NVKMS_FLIP_H__ */ diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia-modeset/include/nvkms-hdmi.h nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia-modeset/include/nvkms-hdmi.h --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia-modeset/include/nvkms-hdmi.h 2023-10-25 20:22:34.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia-modeset/include/nvkms-hdmi.h 2024-03-05 22:12:12.000000000 +0000 @@ -62,8 +62,11 @@ NvBool nvHdmiDpySupportsFrl(const NVDpyEvoRec *pDpyEvo); NvBool nvHdmiFrlQueryConfig(const NVDpyEvoRec *pDpyEvo, const NvModeTimings *pModeTimings, - NVHwModeTimingsEvo *pTimings, - const struct NvKmsModeValidationParams *pParams); + const NVHwModeTimingsEvo *pHwTimings, + const NvBool b2Heads1Or, + const struct NvKmsModeValidationParams *pValidationParams, + HDMI_FRL_CONFIG *pConfig, + NVDscInfoEvoRec *pDscInfo); void nvHdmiFrlClearConfig(NVDispEvoRec *pDispEvo, NvU32 activeRmId); void nvHdmiFrlSetConfig(NVDispEvoRec *pDispEvo, NvU32 head); @@ -71,6 +74,16 @@ const NVDpyEvoRec *pDpyEvo, NVDispHeadAudioStateEvoRec *pAudioState); +NvBool nvHdmiTimingsNeedFrl(const NVDpyEvoRec *pDpyEvo, + const NVHwModeTimingsEvo *pHwTimings); + +static inline NvBool nvHdmiDpySupportsDsc(const NVDpyEvoRec *pDpyEvo) +{ + return nvDpyIsHdmiEvo(pDpyEvo) && + pDpyEvo->parsedEdid.valid && + pDpyEvo->parsedEdid.info.hdmiForumInfo.dsc_1p2; +} + #ifdef __cplusplus }; #endif diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia-modeset/include/nvkms-headsurface-config.h nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia-modeset/include/nvkms-headsurface-config.h --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia-modeset/include/nvkms-headsurface-config.h 2023-10-25 20:22:34.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia-modeset/include/nvkms-headsurface-config.h 2024-03-05 22:12:12.000000000 +0000 @@ -25,7 +25,6 @@ #define __NVKMS_HEADSURFACE_CONFIG_H__ #include "nvkms-types.h" -#include "nvkms-modeset-types.h" /* NVProposedModeSetHwState */ #include "nvkms-softfloat.h" /* NvKmsMatrixF32 */ #include "nvidia-headsurface-types.h" /* NvHsStaticWarpMesh */ #include "g_shader_names.h" /* ProgramName */ diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia-modeset/include/nvkms-headsurface-ioctl.h nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia-modeset/include/nvkms-headsurface-ioctl.h --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia-modeset/include/nvkms-headsurface-ioctl.h 2023-10-25 20:22:35.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia-modeset/include/nvkms-headsurface-ioctl.h 2024-03-05 22:12:12.000000000 +0000 @@ -42,7 +42,10 @@ NvBool nvHsIoctlFlip( NVDevEvoPtr pDevEvo, const struct NvKmsPerOpenDev *pOpenDev, - const struct NvKmsFlipRequest *pRequest, + const struct NvKmsFlipRequestOneHead *pFlipHead, + NvU32 numFlipHeads, + NvBool commit, + NvBool allowVrr, struct NvKmsFlipReply *pReply); #endif /* __NVKMS_HEADSURFACE_IOCTL_H__ */ diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia-modeset/include/nvkms-headsurface-priv.h nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia-modeset/include/nvkms-headsurface-priv.h --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia-modeset/include/nvkms-headsurface-priv.h 2023-10-25 20:22:35.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia-modeset/include/nvkms-headsurface-priv.h 2024-03-05 22:12:13.000000000 +0000 @@ -159,7 +159,7 @@ typedef struct _NVHsChannelFlipQueueEntry { NVListRec flipQueueEntry; - NVFlipChannelEvoHwState hwState; + NVHsLayerRequestedFlipState hwState; } NVHsChannelFlipQueueEntry; typedef struct _NVHsChannelEvoRec { @@ -184,11 +184,11 @@ } nv2d; /* - * NvKmsFlipParams is too large to declare on the stack. We preallocate it - * here so that we don't have to allocate and free it on every headSurface - * flip. + * Flip request parameters are too large to declare on the stack. We + * preallocate them here so that we don't have to allocate and free them on + * every headSurface flip. */ - struct NvKmsFlipParams scratchParams; + struct NvKmsFlipRequestOneHead scratchParams; /* * The index into NVDevEvoRec::apiHeadSurfaceAllDisps[apiHead]::surface[] to use @@ -246,7 +246,7 @@ */ struct { - NVFlipChannelEvoHwState current; + NVHsLayerRequestedFlipState current; NVListRec queue; } flipQueue[NVKMS_MAX_LAYERS_PER_HEAD]; @@ -272,10 +272,10 @@ NvBool usingRgIntrForSwapGroups; /* - * Handle to the RG line interrupt callback object. This is needed to + * Pointer to the RG line interrupt callback object. This is needed to * enabled and disable the RG interrupt callback. */ - NvU32 rgIntrCallbackObjectHandle; + NVRgLine1CallbackPtr pRgIntrCallback; #if NVKMS_PROCFS_ENABLE @@ -495,7 +495,7 @@ } /*! - * Get the last NVFlipChannelEvoHwState entry in the pHsChannel's flip queue for + * Get the last NVHsLayerRequestedFlipState entry in the pHsChannel's flip queue for * the specified layer. * * If the flip queue is empty, return the 'current' entry. Otherwise, return @@ -503,7 +503,7 @@ * * This function cannot fail. */ -static inline const NVFlipChannelEvoHwState *HsGetLastFlipQueueEntry( +static inline const NVHsLayerRequestedFlipState *HsGetLastFlipQueueEntry( const NVHsChannelEvoRec *pHsChannel, const NvU8 layer) { diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia-modeset/include/nvkms-headsurface.h nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia-modeset/include/nvkms-headsurface.h --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia-modeset/include/nvkms-headsurface.h 2023-10-25 20:22:35.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia-modeset/include/nvkms-headsurface.h 2024-03-05 22:12:13.000000000 +0000 @@ -26,6 +26,14 @@ #include "nvkms-types.h" +typedef struct _NVHsLayerRequestedFlipStateRec { + NVSurfaceEvoPtr pSurfaceEvo[NVKMS_MAX_EYES]; + NVFlipCompletionNotifierEvoHwState completionNotifier; + NVFlipSyncObjectEvoHwState syncObject; + NvBool perEyeStereoFlip; + NvU8 minPresentInterval; +} NVHsLayerRequestedFlipState; + NvU64 nvHsMapSurfaceToDevice( const NVDevEvoRec *pDevEvo, const NvU32 rmHandle, @@ -61,7 +69,7 @@ void nvHsPushFlipQueueEntry( NVHsChannelEvoPtr pHsChannel, const NvU8 layer, - const NVFlipChannelEvoHwState *pHwState); + const NVHsLayerRequestedFlipState *pHwState); void nvHsDrainFlipQueue( NVHsChannelEvoPtr pHsChannel); @@ -120,7 +128,7 @@ NVEvoInfoStringRec *pInfoString, NVDevEvoRec *pDevEvo, NvU32 dispIndex, - NvU32 head); + NvU32 apiHead); #endif #endif /* __NVKMS_HEADSURFACE_H__ */ diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia-modeset/include/nvkms-hw-flip.h nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia-modeset/include/nvkms-hw-flip.h --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia-modeset/include/nvkms-hw-flip.h 1970-01-01 00:00:00.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia-modeset/include/nvkms-hw-flip.h 2024-03-05 22:12:12.000000000 +0000 @@ -0,0 +1,128 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2014 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef __NVKMS_HW_FLIP_H__ +#define __NVKMS_HW_FLIP_H__ + + +#include "nvkms-types.h" +#include "nvkms-flip-workarea.h" + +NvBool nvIsLayerDirty(const struct NvKmsFlipCommonParams *pParams, + const NvU32 layer); + +void nvClearFlipEvoHwState( + NVFlipEvoHwState *pFlipState); + +void nvInitFlipEvoHwState( + const NVDevEvoRec *pDevEvo, + const NvU32 sd, + const NvU32 head, + NVFlipEvoHwState *pFlipState); + +NvBool nvUpdateFlipEvoHwState( + const struct NvKmsPerOpenDev *pOpenDev, + const NVDevEvoRec *pDevEvo, + const NvU32 sd, + const NvU32 head, + const struct NvKmsFlipCommonParams *pParams, + const NVHwModeTimingsEvo *pTimings, + const NvU8 tilePosition, + NVFlipEvoHwState *pFlipState, + NvBool allowVrr); + +void +nvOverrideScalingUsageBounds(const NVDevEvoRec *pDevEvo, + NvU32 head, + NVFlipEvoHwState *pFlipState, + const struct NvKmsUsageBounds *pPossibleUsage); + +NvBool nvValidateFlipEvoHwState( + const NVDevEvoRec *pDevEvo, + const NvU32 head, + const NVHwModeTimingsEvo *pTimings, + const NVFlipEvoHwState *pFlipState); + +void +nvUpdateSurfacesFlipRefCount( + NVDevEvoPtr pDevEvo, + const NvU32 head, + NVFlipEvoHwState *pFlipState, + NvBool increase); + +void nvFlipEvoOneHead( + NVDevEvoPtr pDevEvo, + const NvU32 sd, + const NvU32 head, + const NVT_HDR_STATIC_METADATA *pHdrInfo, + const NVFlipEvoHwState *pFlipState, + NvBool allowFlipLock, + NVEvoUpdateState *updateState); + +void nvEvoCancelPostFlipIMPTimer( + NVDevEvoPtr pDevEvo); + +void nvFillPostSyncptReplyOneChannel( + NVEvoChannel *pChannel, + enum NvKmsSyncptType postType, + struct NvKmsSyncpt *postSyncpt, + const NVFlipSyncObjectEvoHwState *pHwSyncObject); + +NvBool nvAllocatePreFlipBandwidth(NVDevEvoPtr pDevEvo, + struct NvKmsFlipWorkArea *pWorkArea); + +void nvPreFlip(NVDevEvoRec *pDevEvo, + struct NvKmsFlipWorkArea *pWorkArea, + const NvBool applyAllowVrr, + const NvBool allowVrr, + const NvBool skipUpdate); + +void nvPostFlip(NVDevEvoRec *pDevEvo, + struct NvKmsFlipWorkArea *pWorkArea, + const NvBool skipUpdate, + const NvBool applyAllowVrr, + NvS32 *pVrrSemaphoreIndex); + +NvBool nvPrepareToDoPreFlip(NVDevEvoRec *pDevEvo, + struct NvKmsFlipWorkArea *pWorkArea); + +NvBool nvAssignNVFlipEvoHwState(NVDevEvoRec *pDevEvo, + const struct NvKmsPerOpenDev *pOpenDev, + const NvU32 sd, + const NvU32 head, + const struct NvKmsFlipCommonParams *pParams, + const NvBool allowVrr, + NVFlipEvoHwState *pFlipHwState); + +void nvIdleMainLayerChannels( + NVDevEvoPtr pDevEvo, + const NVEvoChannelMask *idleChannelMaskPerSd, + NvBool allowStopBase); + +NvBool nvNeedToToggleFlipLock(const NVDispEvoRec *pDispEvo, + const NvU32 head, const NvBool enable); + +void nvToggleFlipLockPerDisp(NVDispEvoRec *pDispEvo, const NvU32 headMask, + const NvBool enable); + +#endif /* __NVKMS_HW_FLIP_H__ */ diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia-modeset/include/nvkms-lut.h nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia-modeset/include/nvkms-lut.h --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia-modeset/include/nvkms-lut.h 2023-10-25 20:22:35.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia-modeset/include/nvkms-lut.h 2024-03-05 22:12:13.000000000 +0000 @@ -50,11 +50,11 @@ static inline void nvCancelLutUpdateEvo( const NVDispEvoRec *pDispEvo, - const NvU32 head) + const NvU32 apiHead) { NVDevEvoRec *pDevEvo = pDispEvo->pDevEvo; - nvkms_free_timer(pDevEvo->lut.head[head].disp[pDispEvo->displayOwner].updateTimer); - pDevEvo->lut.head[head].disp[pDispEvo->displayOwner].updateTimer = NULL; + nvkms_free_timer(pDevEvo->lut.apiHead[apiHead].disp[pDispEvo->displayOwner].updateTimer); + pDevEvo->lut.apiHead[apiHead].disp[pDispEvo->displayOwner].updateTimer = NULL; } #ifdef __cplusplus diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia-modeset/include/nvkms-modeset-types.h nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia-modeset/include/nvkms-modeset-types.h --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia-modeset/include/nvkms-modeset-types.h 2023-10-25 20:22:35.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia-modeset/include/nvkms-modeset-types.h 2024-03-05 22:12:13.000000000 +0000 @@ -29,26 +29,36 @@ #include "nvkms-types.h" typedef struct { + NvU32 hwHeadsMask; + struct NvKmsModeValidationParams modeValidationParams; NVHwModeTimingsEvo timings; - NVDpyIdList dpyIdList; - NVConnectorEvoRec *pConnectorEvo; + struct NvKmsPoint viewPortPointIn; NvU32 activeRmId; + NVDpyIdList dpyIdList; + NVAttributesSetEvoRec attributes; struct NvKmsSetLutCommonParams lut; + NVDispStereoParamsEvoRec stereo; + NVDscInfoEvoRec dscInfo; + NVDispHeadInfoFrameStateEvoRec infoFrame; NvU8 allowFlipLockGroup; - NVAttributesSetEvoRec attributes; - struct NvKmsModeValidationParams modeValidationParams; - NvBool changed : 1; - NvBool allowGsync : 1; - NvBool hs10bpcHint : 1; - enum NvKmsAllowAdaptiveSync allowAdaptiveSync; - NvU32 vrrOverrideMinRefreshRate; + enum NvKmsOutputTf tf; + NvBool colorSpaceSpecified : 1; + NvBool colorRangeSpecified : 1; + NvBool hs10bpcHint : 1; + NvBool changed : 1; +} NVProposedModeSetStateOneApiHead; + +typedef struct { + NvU8 tilePosition; + NVHwModeTimingsEvo timings; + NVConnectorEvoRec *pConnectorEvo; + HDMI_FRL_CONFIG hdmiFrlConfig; NVDPLibModesetStatePtr pDpLibModesetState; NVDispHeadAudioStateEvoRec audio; - NVDispHeadInfoFrameStateEvoRec infoFrame; - enum NvKmsOutputTf tf; } NVProposedModeSetHwStateOneHead; typedef struct { + NVProposedModeSetStateOneApiHead apiHead[NVKMS_MAX_HEADS_PER_DISP]; NVProposedModeSetHwStateOneHead head[NVKMS_MAX_HEADS_PER_DISP]; } NVProposedModeSetHwStateOneDisp; @@ -64,12 +74,13 @@ NvBool allowHeadSurfaceInNvKms : 1; } NVProposedModeSetHwState; -struct _NVEvoModesetUpdateState { - NVEvoUpdateState updateState; - NVDpyIdList connectorIds; - const NVDPLibModesetStateRec - *pDpLibModesetState[NVKMS_MAX_HEADS_PER_DISP]; - NvBool windowMappingChanged; -}; +static inline void nvAssignHwHeadsMaskProposedApiHead( + NVProposedModeSetStateOneApiHead *pProposedApiHead, + const NvU32 hwHeadsMask) +{ + pProposedApiHead->hwHeadsMask = hwHeadsMask; + pProposedApiHead->attributes.numberOfHardwareHeadsUsed = + nvPopCount32(hwHeadsMask); +} #endif /* __NVKMS_MODESET_TYPES_H__ */ diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia-modeset/include/nvkms-modeset-workarea.h nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia-modeset/include/nvkms-modeset-workarea.h --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia-modeset/include/nvkms-modeset-workarea.h 2023-10-25 20:22:35.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia-modeset/include/nvkms-modeset-workarea.h 2024-03-05 22:12:13.000000000 +0000 @@ -31,14 +31,15 @@ struct { NVFlipEvoHwState newState; NVFlipEvoHwState oldState; - NvU32 oldActiveRmId; } head[NVKMS_MAX_HEADS_PER_DISP]; + struct { + NvU32 oldActiveRmId; + } apiHead[NVKMS_MAX_HEADS_PER_DISP]; + NVDpyIdList changedDpyIdList; - NVDpyIdList sorAssignedConnectorsList; NvU32 assignedSorMask; - } sd[NVKMS_MAX_SUBDEVICES]; NVHsConfig hsConfig; NVEvoUpdateState earlyUpdateState; diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia-modeset/include/nvkms-modeset.h nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia-modeset/include/nvkms-modeset.h --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia-modeset/include/nvkms-modeset.h 2023-10-25 20:22:35.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia-modeset/include/nvkms-modeset.h 2024-03-05 22:12:13.000000000 +0000 @@ -48,19 +48,12 @@ NvBool bypassComposition, NvBool doRasterLock); -typedef NvBool (*NVShutDownHeadsTestFunc)( +typedef NvBool (*NVShutDownApiHeadsTestFunc)( const NVDispEvoRec *pDispEvo, - const NvU32 head); + const NvU32 apiHead); -void nvShutDownHeads(NVDevEvoPtr pDevEvo, NVShutDownHeadsTestFunc pTestFunc); - -NVVBlankCallbackPtr nvRegisterVBlankCallback(NVDispEvoPtr pDispEvo, - NvU32 head, - NVVBlankCallbackProc pCallback, - void *pUserData); -void nvUnregisterVBlankCallback(NVDispEvoPtr pDispEvo, - NvU32 head, - NVVBlankCallbackPtr pCallback); +void nvShutDownApiHeads(NVDevEvoPtr pDevEvo, + NVShutDownApiHeadsTestFunc pTestFunc); NVVBlankCallbackPtr nvApiHeadRegisterVBlankCallback(NVDispEvoPtr pDispEvo, @@ -69,13 +62,18 @@ void *pUserData); void nvApiHeadUnregisterVBlankCallback(NVDispEvoPtr pDispEvo, - const NvU32 apiHead, NVVBlankCallbackPtr pCallback); -NvU32 -nvApiHeadAddRgLine1Callback(const NVDispEvoRec *pDispEvo, +NVRgLine1CallbackPtr +nvApiHeadAddRgLine1Callback(NVDispEvoRec *pDispEvo, const NvU32 apiHead, - NV0092_REGISTER_RG_LINE_CALLBACK_FN pCallback); + NVRgLine1CallbackProc pCallbackProc, + void *pUserData); + +void nvApiHeadGetScanLine(const NVDispEvoRec *pDispEvo, + const NvU32 apiHead, + NvU16 *pScanLine, + NvBool *pInBlankingPeriod); #ifdef __cplusplus }; diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia-modeset/include/nvkms-prealloc-types.h nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia-modeset/include/nvkms-prealloc-types.h --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia-modeset/include/nvkms-prealloc-types.h 2023-10-25 20:22:35.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia-modeset/include/nvkms-prealloc-types.h 2024-03-05 22:12:14.000000000 +0000 @@ -37,6 +37,11 @@ PREALLOC_TYPE_HS_INIT_CONFIG_HW_TIMINGS, PREALLOC_TYPE_VALIDATE_PROPOSED_MODESET_HW_STATE, PREALLOC_TYPE_VALIDATE_MODE_HW_MODE_TIMINGS, + PREALLOC_TYPE_VALIDATE_MODE_HDMI_FRL_CONFIG, + PREALLOC_TYPE_VALIDATE_MODE_DSC_INFO, + PREALLOC_TYPE_MODE_SET_REPLY_TMP_USAGE_BOUNDS, + PREALLOC_TYPE_VALIDATE_MODE_IMP_OUT_HW_MODE_TIMINGS, + PREALLOC_TYPE_VALIDATE_MODE_TMP_USAGE_BOUNDS, PREALLOC_TYPE_MAX }; diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia-modeset/include/nvkms-private.h nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia-modeset/include/nvkms-private.h --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia-modeset/include/nvkms-private.h 2023-10-25 20:22:35.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia-modeset/include/nvkms-private.h 2024-03-05 22:12:14.000000000 +0000 @@ -47,9 +47,8 @@ const enum NvKmsFrameLockAttribute attribute, const NvS64 value); -void nvSendFlipOccurredEventEvo( - const NVDevEvoRec *pDevEvo, - NVEvoChannelMask channelMask); +void nvSendFlipOccurredEventEvo(const NVDispEvoRec *pDispEvo, + const NvU32 apiHead, const NvU32 layer); void nvSendUnicastEvent(struct NvKmsPerOpen *pOpen); diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia-modeset/include/nvkms-rm.h nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia-modeset/include/nvkms-rm.h --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia-modeset/include/nvkms-rm.h 2023-10-25 20:22:36.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia-modeset/include/nvkms-rm.h 2024-03-05 22:12:14.000000000 +0000 @@ -126,16 +126,19 @@ NvBool nvRmQueryDpAuxLog(NVDispEvoRec *pDispEvo, NvS64 *pValue); NvU64 nvRmGetGpuTime(NVDevEvoPtr pDevEvo); NvBool nvRmSetGc6Allowed(NVDevEvoPtr pDevEvo, NvBool allowed); -NvU32 nvRmAddRgLine1Callback( - const NVDispEvoRec *pDispEvo, - NvU32 head, - NV0092_REGISTER_RG_LINE_CALLBACK_FN pCallback); +NVRgLine1CallbackPtr +nvRmAddRgLine1Callback(NVDispEvoRec *pDispEvo, + NvU32 head, + NVRgLine1CallbackProc pCallbackProc, + void *pUserData); void nvRmRemoveRgLine1Callback(const NVDispEvoRec *pDispEvo, - NvU32 callbackObjectHandle); + NVRgLine1CallbackPtr pCallback); + NvU32 nvRmAddVBlankCallback( const NVDispEvoRec *pDispEvo, NvU32 head, - OSVBLANKCALLBACKPROC pCallback); + OSVBLANKCALLBACKPROC pCallback, + void *pParam2); void nvRmRemoveVBlankCallback(const NVDispEvoRec *pDispEvo, NvU32 callbackObjectHandle); void nvRmMuxInit(NVDevEvoPtr pDevEvo); @@ -147,6 +150,9 @@ void nvRmRegisterBacklight(NVDispEvoRec *pDispEvo); void nvRmUnregisterBacklight(NVDispEvoRec *pDispEvo); +void nvRmAllocCoreRGSyncpts(NVDevEvoPtr pDevEvo); +void nvRmFreeCoreRGSyncpts(NVDevEvoPtr pDevEvo); + #ifdef __cplusplus }; #endif diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia-modeset/include/nvkms-types.h nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia-modeset/include/nvkms-types.h --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia-modeset/include/nvkms-types.h 2023-10-25 20:22:36.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia-modeset/include/nvkms-types.h 2024-03-05 22:12:14.000000000 +0000 @@ -141,6 +141,7 @@ typedef struct _NVDispEvoRec *NVDispEvoPtr; typedef struct _NVParsedEdidEvoRec *NVParsedEdidEvoPtr; typedef struct _NVVBlankCallbackRec *NVVBlankCallbackPtr; +typedef struct _NVRgLine1CallbackRec *NVRgLine1CallbackPtr; typedef struct _NVDpyEvoRec *NVDpyEvoPtr; typedef struct _NVLutSurfaceEvo *NVLutSurfaceEvoPtr; typedef struct _NVFrameLockEvo *NVFrameLockEvoPtr; @@ -148,6 +149,8 @@ typedef struct _NVSurfaceEvoRec NVSurfaceEvoRec, *NVSurfaceEvoPtr; typedef struct _NVDeferredRequestFifoRec *NVDeferredRequestFifoPtr; typedef struct _NVSwapGroupRec *NVSwapGroupPtr; +typedef struct _NVEvoModesetUpdateState NVEvoModesetUpdateState; +typedef struct _NVEvoRasterLockTopology *RasterLockTopologyPtr; /* * _NVHs*EvoRec are defined in nvkms-headsurface-priv.h; they are intentionally @@ -165,9 +168,6 @@ /* _nv_dplibtimer is defined in nvdp-timer.hpp */ typedef struct _nv_dplibtimer NVDPLibTimerRec, *NVDPLibTimerPtr; -/* _NVEvoModesetUpdateState defined in nvkms-modeset-types.h */ -typedef struct _NVEvoModesetUpdateState NVEvoModesetUpdateState; - typedef struct _NVEvoApiHandlesRec { void **pointers; /* Dynamically allocated array of pointers. */ NvU32 numPointers; /* Number of elements in pointers array. */ @@ -184,6 +184,10 @@ /* Whether this is sysmem, or vidmem accessed through a BAR1 mapping. */ NvBool isBar1Mapping; + struct { + NvU8 vrrNotifierNextSlot; + } vrrNotifierHead[NV_MAX_HEADS]; + void *subDeviceAddress[NVKMS_MAX_SUBDEVICES]; } NVEvoDma, *NVEvoDmaPtr; @@ -263,6 +267,7 @@ typedef struct { NvBool usable; + NvU32 maxPClkKHz; NvBool supportsHDMIYUV420HW; NVEvoScalerCaps scalerCaps; } NVEvoHeadCaps; @@ -385,6 +390,20 @@ } NVEvoUpdateState; +struct _NVEvoModesetUpdateState { + NVEvoUpdateState updateState; + NVDpyIdList connectorIds; + const NVDPLibModesetStateRec + *pDpLibModesetState[NVKMS_MAX_HEADS_PER_DISP]; + NvBool windowMappingChanged; + struct { + struct _NVEvoModesetUpdateStateOneLayer { + struct nvkms_ref_ptr *ref_ptr; + NvBool changed; + } layer[NVKMS_MAX_LAYERS_PER_HEAD]; + } flipOccurredEvent[NVKMS_MAX_HEADS_PER_DISP]; +}; + typedef struct { struct { NVEvoChannelMask channelMask; @@ -393,7 +412,6 @@ typedef struct { NvU8 validTimeStampBits; - NvU8 legacyNotifierFormatSizeBytes; NvBool tearingFlips :1; NvBool vrrTearingFlips :1; NvBool perEyeStereoFlips :1; @@ -420,6 +438,8 @@ NvU32 hCtxDma; /*! handle of syncpt object */ NvU32 hSyncpt; + /*! stores syncpt max value */ + NvU32 syncptMaxVal; } NVEvoSyncpt; /* Tracks internal state of a vblank sync object. */ @@ -455,8 +475,8 @@ NVDmaBufferEvoRec pb; NVOS10_EVENT_KERNEL_CALLBACK_EX completionNotifierEventCallback; + const struct nvkms_ref_ptr *completionNotifierEventRefPtr; NvU32 completionNotifierEventHandle; - struct nvkms_ref_ptr *ref_ptr; /* * GV100 timestamped flips need a duplicate update which only changes @@ -512,6 +532,13 @@ NVEvoLockPin flipLockPin; NVEvoLockPin stereoPin; + NvBool mergeMode; + NvBool setLockOffsetX; + + NvU32 stallLockPin; + NvBool useStallLockPin; + NvBool crashLockUnstallMode; + /* * Whether or not this GPU is stereo locked. True if all heads are either * frame or raster locked, and all heads are driving non-interlaced modes. @@ -644,6 +671,19 @@ } maxDownscaleFactors; } NVFlipChannelEvoHwState; +enum NvKmsDpyAttributeColorBpcValue { + NV_KMS_DPY_ATTRIBUTE_CURRENT_COLOR_BPC_UNKNOWN = 0, + NV_KMS_DPY_ATTRIBUTE_CURRENT_COLOR_BPC_10 = 10, + NV_KMS_DPY_ATTRIBUTE_CURRENT_COLOR_BPC_8 = 8, + NV_KMS_DPY_ATTRIBUTE_CURRENT_COLOR_BPC_6 = 6, +}; + +typedef struct _NVColorFormatInfoRec { + struct { + enum NvKmsDpyAttributeColorBpcValue maxBpc; + } rgb444, yuv444, yuv422; +} NVColorFormatInfoRec; + typedef struct { struct NvKmsPoint viewPortPointIn; NVFlipCursorEvoHwState cursor; @@ -838,6 +878,9 @@ struct NvKmsCompositionCapabilities cursorCompositionCaps; NvU16 validLayerRRTransforms; struct NvKmsLayerCapabilities layerCaps[NVKMS_MAX_LAYERS_PER_HEAD]; + NvU8 legacyNotifierFormatSizeBytes[NVKMS_MAX_LAYERS_PER_HEAD]; + NvU8 dpYCbCr422MaxBpc; + NvU8 hdmiYCbCr422MaxBpc; } NVEvoCapsRec; typedef struct { @@ -1154,7 +1197,7 @@ NvU8 curLUTIndex; nvkms_timer_handle_t *updateTimer; } disp[NVKMS_MAX_SUBDEVICES]; - } head[NVKMS_MAX_HEADS_PER_DISP]; + } apiHead[NVKMS_MAX_HEADS_PER_DISP]; NVLutSurfaceEvoPtr defaultLut; enum NvKmsLUTState defaultBaseLUTState[NVKMS_MAX_SUBDEVICES]; enum NvKmsLUTState defaultOutputLUTState[NVKMS_MAX_SUBDEVICES]; @@ -1178,6 +1221,29 @@ } apiHead[NVKMS_MAX_HEADS_PER_DISP]; } NVDevEvoRec; +static inline NvBool nvEvoIsConsoleActive(const NVDevEvoRec *pDevEvo) +{ + /* + * If (pDevEvo->modesetOwner == NULL) that means either the vbios + * console or the NVKMS console might be active. + */ + if (pDevEvo->modesetOwner == NULL) { + return TRUE; + } + + /* + * If (pDevEvo->modesetOwner != NULL) but + * pDevEvo->modesetOwnerChanged is TRUE, that means the modeset + * ownership is grabbed by the external client but it hasn't + * performed any modeset and the console is still active. + */ + if ((pDevEvo->modesetOwner != NULL) && pDevEvo->modesetOwnerChanged) { + return TRUE; + } + + return FALSE; +} + /* * The NVHwModeTimingsEvo structure stores all the values necessary to * perform a modeset with EVO @@ -1230,6 +1296,8 @@ NVKMS_PIXEL_DEPTH_18_444, NVKMS_PIXEL_DEPTH_24_444, NVKMS_PIXEL_DEPTH_30_444, + NVKMS_PIXEL_DEPTH_20_422, + NVKMS_PIXEL_DEPTH_16_422, }; enum nvKmsTimingsProtocol { @@ -1248,6 +1316,52 @@ NVKMS_PROTOCOL_PIOR_EXT_TMDS_ENC, }; +enum NVDscInfoEvoType { + NV_DSC_INFO_EVO_TYPE_DISABLED = 0, + NV_DSC_INFO_EVO_TYPE_HDMI = 1, + NV_DSC_INFO_EVO_TYPE_DP = 3, +}; + +enum NVDscEvoMode { + NV_DSC_EVO_MODE_SINGLE = 0, + NV_DSC_EVO_MODE_DUAL = 1, +}; + +typedef struct _NVDscInfoEvoRec { + union { + /* DisplayPort Display Stream Compression */ + struct { + /* + * The DSC target bits per pixel (bpp) rate value multiplied by 16 that + * is being used by the DSC encoder. + * + * It maps respectively to {pps4[1:0], pps5[7:0]}. + */ + NvU32 bitsPerPixelX16; + + /* + * The DSC picture parameter set (PPS), which the DSC encoder must + * communicate to the decoder. + */ + NvU32 pps[DSC_MAX_PPS_SIZE_DWORD]; + enum NVDscEvoMode dscMode; + } dp; + + struct { + NvU32 bitsPerPixelX16; + NvU32 pps[HDMI_DSC_MAX_PPS_SIZE_DWORD]; + NvU32 dscHActiveBytes; + NvU32 dscHActiveTriBytes; + NvU32 dscHBlankTriBytes; + NvU32 dscTBlankToTTotalRatioX1k; + NvU32 hblankMin; + enum NVDscEvoMode dscMode; + } hdmi; + }; + + enum NVDscInfoEvoType type; +} NVDscInfoEvoRec; + /* * This structure defines all of the values necessary to program mode timings * on EVO hardware. @@ -1264,7 +1378,6 @@ NvU32 pixelClock; /* in kHz */ enum nvKmsTimingsProtocol protocol; - enum nvKmsPixelDepth pixelDepth; /* * yuv420Mode reflects whether this mode requires YUV 4:2:0 decimation into * a half-width output through headsurface (SW YUV420) or >=nvdisplay 4.0 HW @@ -1297,35 +1410,11 @@ struct { /* The vrr type for which this mode is adjusted. */ enum NvKmsDpyVRRType type; + NvU32 timeoutMicroseconds; + NvBool needsSwFramePacing; } vrr; - /* DisplayPort Display Stream Compression */ - struct { - NvBool enable; - - /* - * The DSC target bits per pixel (bpp) rate value multiplied by 16 that - * is being used by the DSC encoder. - * - * It maps respectively to {pps4[1:0], pps5[7:0]}. - */ - NvU32 bitsPerPixelX16; - - /* - * The DSC picture parameter set (PPS), which the DSC encoder must - * communicate to the decoder. - */ - NvU32 pps[DSC_MAX_PPS_SIZE_DWORD]; - } dpDsc; - - HDMI_FRL_CONFIG hdmiFrlConfig; - NVHwModeViewPortEvo viewPort; - - struct { - enum NvKmsStereoMode mode; - NvBool isAegis; - } stereo; } NVHwModeTimingsEvo; static inline NvBool nvIsAdaptiveSyncDpyVrrType(enum NvKmsDpyVRRType type) @@ -1473,7 +1562,6 @@ NvU32 legacyTypeIndex; NvU32 physicalIndex; NvU32 physicalLocation; - NvU32 validHeadMask; NvU32 dfpInfo; /* DFP info query through NV0073_CTRL_CMD_DFP_GET_INFO */ @@ -1487,25 +1575,32 @@ NvU32 ditherAlgo; /* Hardware heads attached to assigned OR */ NvU32 ownerHeadMask[NV_EVO_MAX_ORS]; - /* ORs mask assigned to this connector */ - NvU32 mask; + /* The mask of secondary ORs assigned to this connector */ + NvU32 secondaryMask; + /* The primary OR assigned to this connector */ + NvU32 primary; } or; - struct { - NvBool ycbcr422Capable; - NvBool ycbcr444Capable; - } colorSpaceCaps; - NvEldCase audioDevEldCase[NV_MAX_AUDIO_DEVICE_ENTRIES]; + + NvBool isHdmiEnabled; } NVConnectorEvoRec; +static inline NvU32 nvConnectorGetORMaskEvo(const NVConnectorEvoRec *pConnectorEvo) +{ + if (pConnectorEvo->or.primary != NV_INVALID_OR) { + return NVBIT(pConnectorEvo->or.primary) | pConnectorEvo->or.secondaryMask; + } + return 0x0; +} + static inline NvU32 nvConnectorGetAttachedHeadMaskEvo( const NVConnectorEvoRec *pConnectorEvo) { NvU32 headMask = 0x0; NvU32 orIndex; - FOR_EACH_INDEX_IN_MASK(32, orIndex, pConnectorEvo->or.mask) { + FOR_EACH_INDEX_IN_MASK(32, orIndex, nvConnectorGetORMaskEvo(pConnectorEvo)) { headMask |= pConnectorEvo->or.ownerHeadMask[orIndex]; } FOR_EACH_INDEX_IN_MASK_END; @@ -1515,27 +1610,8 @@ static inline NvBool nvIsConnectorActiveEvo(const NVConnectorEvoRec *pConnectorEvo) { - NvU32 orIndex; - - FOR_EACH_INDEX_IN_MASK(32, orIndex, pConnectorEvo->or.mask) { - if (pConnectorEvo->or.ownerHeadMask[orIndex] != 0x0) { - return TRUE; - } - } FOR_EACH_INDEX_IN_MASK_END; - - return FALSE; -} - -/* - * In case of 2-Heads-1-OR: NV0073_CTRL_CMD_DFP_ASSIGN_SOR assigns 2 SORs, - * lowest SOR index is for primary head. - */ -static inline NvU32 nvEvoConnectorGetPrimaryOr( - const NVConnectorEvoRec *pConnectorEvo) -{ - return (pConnectorEvo->or.mask == 0x0 ? - NV_INVALID_OR : - BIT_IDX_32(LOWESTBIT(pConnectorEvo->or.mask))); + return (pConnectorEvo->or.primary != NV_INVALID_OR) && + (pConnectorEvo->or.ownerHeadMask[pConnectorEvo->or.primary] != 0x0); } typedef struct _NVDpyAttributeCurrentDitheringConfigRec { @@ -1558,6 +1634,10 @@ * stored in NVDpyEvoRec::requestedColor(Space, Range}. The structure stores * the actual color space and color range in use. * + * nvChooseCurrentColorSpaceAndRangeEvo() chooses the actual color + * space, color bpc, and color range, for a dpy. It sets colorBpc + * to the max bpc supported by the given dpy. + * * Since YUV444 mode only allows limited color range, changes to the * current color space may trigger changes to the current color * range (see nvChooseCurrentColorSpaceAndRangeEvo()). @@ -1566,6 +1646,7 @@ * HEAD_SET_PROCAMP and applied in the headSurface composite shader. */ enum NvKmsDpyAttributeCurrentColorSpaceValue colorSpace; + enum NvKmsDpyAttributeColorBpcValue colorBpc; enum NvKmsDpyAttributeColorRangeValue colorRange; NVDpyAttributeCurrentDitheringConfig dithering; @@ -1580,6 +1661,8 @@ } imageSharpening; enum NvKmsDpyAttributeDigitalSignalValue digitalSignal; + + NvU8 numberOfHardwareHeadsUsed; } NVAttributesSetEvoRec; #define NV_EVO_DEFAULT_ATTRIBUTES_SET \ @@ -1595,8 +1678,19 @@ .imageSharpening = { \ .value = NV_EVO_IMAGE_SHARPENING_DEFAULT, \ }, \ + .numberOfHardwareHeadsUsed = 0, \ } +struct NvKmsVrrFramePacingInfo { + /* Whether sw frame pacing is active. */ + NvBool framePacingActive; + + /* Memory handle for vidmem buffer */ + NvHandle memoryHandle; + + /* Shared data to be updated by RM */ + NV0073_CTRL_RM_VRR_SHARED_DATA *pData; +}; typedef struct _NVEldEvoRec { NvU32 size; @@ -1620,11 +1714,21 @@ NvBool hdTimings; } NVDispHeadInfoFrameStateEvoRec; +typedef enum _NVEvoMergeMode { + NV_EVO_MERGE_MODE_DISABLED, + NV_EVO_MERGE_MODE_SETUP, + NV_EVO_MERGE_MODE_PRIMARY, + NV_EVO_MERGE_MODE_SECONDARY, +} NVEvoMergeMode; + /* * This structure stores information about the active per-head display state. */ typedef struct _NVDispHeadStateEvoRec { + struct NvKmsVrrFramePacingInfo vrrFramePacingInfo; + NvU32 displayRate; + /*! Cached, to preserve across modesets. */ struct NvKmsModeValidationParams modeValidationParams; @@ -1663,37 +1767,53 @@ NVHwModeTimingsEvo timings; NVConnectorEvoRec *pConnectorEvo; /* NULL if the head is not active */ - /* - * Each head can have up to NVKMS_MAX_VBLANK_SYNC_OBJECTS_PER_HEAD - * programmable Core semaphores. - * - * The numVblankSyncObjectsCreated will ideally always be equal to - * NVKMS_MAX_VBLANK_SYNC_OBJECTS_PER_HEAD, but could be lower if errors - * occured during syncpt allocation in nvRMSetupEvoCoreChannel(). - */ - NvU8 numVblankSyncObjectsCreated; - NVVblankSyncObjectRec vblankSyncObjects[NVKMS_MAX_VBLANK_SYNC_OBJECTS_PER_HEAD]; - NVDispHeadAudioStateEvoRec audio; + HDMI_FRL_CONFIG hdmiFrlConfig; - NvU32 rmVBlankCallbackHandle; - NVListRec vblankCallbackList; + NVDscInfoEvoRec dscInfo; + + enum nvKmsPixelDepth pixelDepth; + + NVDispHeadAudioStateEvoRec audio; enum NvKmsOutputTf tf; struct { enum NvKmsHDROutputState outputState; struct NvKmsHDRStaticMetadata staticMetadata; - nvkms_timer_handle_t *sdrTransitionTimer; } hdr; + struct { + NVLutSurfaceEvoPtr pCurrSurface; + NvBool outputLutEnabled : 1; + NvBool baseLutEnabled : 1; + } lut; + /* * The api head can be mapped onto the N harware heads, a frame presented * by the api head gets split horizontally into N tiles, 'tilePosition' * describe the tile presented by this hardware head. */ NvU8 tilePosition; + + NVEvoMergeMode mergeMode; + /* + * XXX[2Heads1OR] Implement per api-head frame pacing and remove + * NVDispEvoRec::mergeModeVrrSecondaryHeadMask. + */ + NvU32 mergeModeVrrSecondaryHeadMask; } NVDispHeadStateEvoRec; +typedef struct _NVDispStereoParamsEvoRec { + enum NvKmsStereoMode mode; + NvBool isAegis; +} NVDispStereoParamsEvoRec; + +typedef struct _NVDispFlipOccurredEventDataEvoRec { + NVDispEvoPtr pDispEvo; + NvU32 apiHead; + NvU32 layer; +} NVDispFlipOccurredEventDataEvoRec; + typedef struct _NVDispApiHeadStateEvoRec { /* * The mask of hardware heads mapped onto this api head, @@ -1704,6 +1824,9 @@ NVDpyIdList activeDpys; /* Empty if the head is not active */ NVAttributesSetEvoRec attributes; + enum NvKmsOutputTf tf; + nvkms_timer_handle_t *hdrToSdrTransitionTimer; + /* * Hardware timings which are split across hardware heads. * @@ -1713,10 +1836,31 @@ */ NVHwModeTimingsEvo timings; + NVDispStereoParamsEvoRec stereo; + struct NvKmsPoint viewPortPointIn; NVDispHeadInfoFrameStateEvoRec infoFrame; + /* + * Each head can have up to NVKMS_MAX_VBLANK_SYNC_OBJECTS_PER_HEAD + * programmable Core semaphores. + * + * The numVblankSyncObjectsCreated will ideally always be equal to + * NVKMS_MAX_VBLANK_SYNC_OBJECTS_PER_HEAD, but could be lower if errors + * occured during syncpt allocation in nvRMSetupEvoCoreChannel(). + */ + NvU8 numVblankSyncObjectsCreated; + NVVblankSyncObjectRec vblankSyncObjects[NVKMS_MAX_VBLANK_SYNC_OBJECTS_PER_HEAD]; + + struct { + struct nvkms_ref_ptr *ref_ptr; + NVDispFlipOccurredEventDataEvoRec data; + } flipOccurredEvent[NVKMS_MAX_LAYERS_PER_HEAD]; + + NvU32 rmVBlankCallbackHandle; + NVListRec vblankCallbackList; + NvBool hs10bpcHint : 1; } NVDispApiHeadStateEvoRec; @@ -1814,17 +1958,11 @@ NvBool dpAuxLoggingEnabled; struct nvkms_backlight_device *backlightDevice; -} NVDispEvoRec; - -/* - * XXX[2Head1OR] Remove nvHardwareHeadToApiHead(), before implementing logic to - * map multiple hardware heads onto the single api head. - */ -static inline NvU32 nvHardwareHeadToApiHead(const NvU32 head) -{ - return head; -} + NvU32 vrrSetTimeoutEventUsageCount; + NVOS10_EVENT_KERNEL_CALLBACK_EX vrrSetTimeoutCallback; + NvU32 vrrSetTimeoutEventHandle; +} NVDispEvoRec; static inline NvU32 GetNextHwHead(NvU32 hwHeadsMask, const NvU32 prevHwHead) { @@ -1845,12 +1983,17 @@ FOR_EACH_EVO_HW_HEAD_IN_MASK((__pDispEvo)->apiHeadState[(__apiHead)].hwHeadsMask, \ (__hwHead)) +static inline NvU32 nvGetPrimaryHwHeadFromMask(const NvU32 hwHeadsMask) +{ + return GetNextHwHead(hwHeadsMask, NV_INVALID_HEAD); +} + static inline NvU32 nvGetPrimaryHwHead(const NVDispEvoRec *pDispEvo, const NvU32 apiHead) { return (apiHead != NV_INVALID_HEAD) ? - GetNextHwHead(pDispEvo->apiHeadState[apiHead].hwHeadsMask, - NV_INVALID_HEAD) : NV_INVALID_HEAD; + nvGetPrimaryHwHeadFromMask(pDispEvo->apiHeadState[apiHead].hwHeadsMask) : + NV_INVALID_HEAD; } typedef enum { @@ -1874,15 +2017,24 @@ } NVParsedEdidEvoRec; typedef void (*NVVBlankCallbackProc)(NVDispEvoRec *pDispEvo, - const NvU32 head, NVVBlankCallbackPtr pCallbackData); typedef struct _NVVBlankCallbackRec { NVListRec vblankCallbackListEntry; NVVBlankCallbackProc pCallback; void *pUserData; + NvU32 apiHead; } NVVBlankCallbackRec; +typedef void (*NVRgLine1CallbackProc)(NVDispEvoRec *pDispEvo, + const NvU32 head, + NVRgLine1CallbackPtr pCallbackData); + +typedef struct _NVRgLine1CallbackRec { + NVRgLine1CallbackProc pCallbackProc; + void *pUserData; +} NVRgLine1CallbackRec; + typedef struct _NVDpyAttributeRequestedDitheringConfigRec { enum NvKmsDpyAttributeRequestedDitheringValue state; enum NvKmsDpyAttributeRequestedDitheringDepthValue depth; @@ -1975,8 +2127,9 @@ struct { enum NvKmsDpyVRRType type; + NvU32 edidTimeoutMicroseconds; + NvBool needsSwFramePacing; } vrr; - } NVDpyEvoRec; static inline NvBool nvDpyEvoIsDPMST(const NVDpyEvoRec *pDpyEvo) @@ -2240,7 +2393,12 @@ NvU32 allocRefCnt; /* Only used for dynamically allocated LUTs */ + NvU64 gpuAddress; void *subDeviceAddress[NVKMS_MAX_SUBDEVICES]; + + /* Keep track of prefetched surfaces. */ + NvU32 difrLastPrefetchPass; + } NVLutSurfaceEvoRec; typedef struct _NVFrameLockEvo { @@ -2285,11 +2443,19 @@ NvBool videoModeReadOnly; /* If video mode is read-only */ + NvU32 maxMulDivValue; /* Max sync multiply/divide value */ + + NvBool mulDivSupported; /* Whether this board supports setting a sync + * multiplier/divider; maxMulDivValue is only + * valid if this is true */ + /* Current device state */ enum NvKmsFrameLockAttributePolarityValue polarity; NvU32 syncDelay; NvU32 syncInterval; enum NvKmsFrameLockAttributeVideoModeValue videoMode; + NvU8 mulDivValue; + enum NvKmsFrameLockAttributeMulDivModeValue mulDivMode; NvBool testMode; } NVFrameLockEvoRec; @@ -2534,6 +2700,9 @@ struct NvKmsPerOpen *nvKmsPerOpen; + RasterLockTopologyPtr globalTopologies; + NvU32 numGlobalTopos; + } NVEvoGlobal; extern NVEvoGlobal nvEvoGlobal; @@ -2559,6 +2728,9 @@ struct { /* pTimings == NULL => this head is disabled */ const NVHwModeTimingsEvo *pTimings; + NvBool enableDsc; + NvBool b2Heads1Or; + enum nvKmsPixelDepth pixelDepth; const struct NvKmsUsageBounds *pUsage; NvU32 displayId; NvU32 orIndex; @@ -2632,6 +2804,8 @@ typedef const struct _nv_evo_hal { void (*SetRasterParams) (NVDevEvoPtr pDevEvo, int head, const NVHwModeTimingsEvo *pTimings, + const NvU8 tilePosition, + const NVDscInfoEvoRec *pDscInfo, const NVEvoColorRec *pOverscanColor, NVEvoUpdateState *updateState); void (*SetProcAmp) (NVDispEvoPtr pDispEvo, const NvU32 head, @@ -2643,6 +2817,7 @@ void (*HeadSetControlOR) (NVDevEvoPtr pDevEvo, const int head, const NVHwModeTimingsEvo *pTimings, + const enum nvKmsPixelDepth pixelDepth, const NvBool colorSpaceOverride, NVEvoUpdateState *updateState); void (*ORSetControl) (NVDevEvoPtr pDevEvo, @@ -2786,7 +2961,8 @@ void (*SetDscParams) (const NVDispEvoRec *pDispEvo, const NvU32 head, - const NVHwModeTimingsEvo *pTimings); + const NVDscInfoEvoRec *pDscInfo, + const enum nvKmsPixelDepth pixelDepth); void (*EnableMidFrameAndDWCFWatermark)(NVDevEvoPtr pDevEvo, NvU32 sd, @@ -2805,6 +2981,11 @@ const NVEvoScalerCaps* (*GetWindowScalingCaps)(const NVDevEvoRec *pDevEvo); + void (*SetMergeMode)(const NVDispEvoRec *pDispEvo, + const NvU32 head, + const NVEvoMergeMode mode, + NVEvoUpdateState* pUpdateState); + struct { NvU32 supportsNonInterlockedUsageBoundsUpdate :1; NvU32 supportsDisplayRate :1; @@ -2822,6 +3003,7 @@ NvU32 supportsSynchronizedOverlayPositionUpdate :1; NvU32 supportsVblankSyncObjects :1; NvU32 requiresScalingTapsInBothDimensions :1; + NvU32 supportsMergeMode :1; NvU32 supportedDitheringModes; size_t impStructSize; @@ -2872,6 +3054,15 @@ &b->layer[layer].scaling); } +static inline void nvAssignHwHeadsMaskApiHeadState( + NVDispApiHeadStateEvoRec *pApiHeadState, + const NvU32 hwHeadsMask) +{ + pApiHeadState->hwHeadsMask = hwHeadsMask; + pApiHeadState->attributes.numberOfHardwareHeadsUsed = + nvPopCount32(hwHeadsMask); +} + #ifdef __cplusplus }; #endif diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia-modeset/include/nvkms-utils-flip.h nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia-modeset/include/nvkms-utils-flip.h --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia-modeset/include/nvkms-utils-flip.h 1970-01-01 00:00:00.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia-modeset/include/nvkms-utils-flip.h 2024-03-05 22:12:15.000000000 +0000 @@ -0,0 +1,73 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2014 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef __NVKMS_FLIP_UTILS_H__ +#define __NVKMS_FLIP_UTILS_H__ + + +#include "nvkms-types.h" + +NvBool nvAssignSurfaceArray( + const NVDevEvoRec *pDevEvo, + const NVEvoApiHandlesRec *pOpenDevSurfaceHandles, + const NvKmsSurfaceHandle surfaceHandles[NVKMS_MAX_EYES], + const NvBool isUsedByCursorChannel, + const NvBool isUsedByLayerChannel, + NVSurfaceEvoPtr pSurfaceEvos[NVKMS_MAX_EYES]); + +NvBool nvAssignNIsoEvoHwState( + const NVDevEvoRec *pDevEvo, + const NVEvoApiHandlesRec *pOpenDevSurfaceHandles, + const struct NvKmsNIsoSurface *pParamsNIso, + const NvBool notifier, /* TRUE=notifier; FALSE=semaphore */ + const NvU32 layer, + NVFlipNIsoSurfaceEvoHwState *pNIsoState); + +NvBool nvAssignCompletionNotifierEvoHwState( + const NVDevEvoRec *pDevEvo, + const NVEvoApiHandlesRec *pOpenDevSurfaceHandles, + const struct NvKmsCompletionNotifierDescription *pParamsNotif, + const NvU32 layer, + NVFlipCompletionNotifierEvoHwState *pNotif); + +NvBool nvAssignSemaphoreEvoHwState( + const NVDevEvoRec *pDevEvo, + const NVEvoApiHandlesRec *pOpenDevSurfaceHandles, + const NvU32 layer, + const NvU32 sd, + const struct NvKmsChannelSyncObjects *pChannelSyncObjects, + NVFlipSyncObjectEvoHwState *pFlipSyncObject); + +NvBool nvValidatePerLayerCompParams( + const struct NvKmsCompositionParams *pCompParams, + const struct NvKmsCompositionCapabilities *pCaps, + NVSurfaceEvoPtr pSurfaceEvo); + +NvBool +nvAssignCursorSurface(const struct NvKmsPerOpenDev *pOpenDev, + const NVDevEvoRec *pDevEvo, + const struct NvKmsSetCursorImageCommonParams *pImgParams, + NVSurfaceEvoPtr *pSurfaceEvo); + + +#endif /* __NVKMS_FLIP_UTILS_H__ */ diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia-modeset/include/nvkms-vrr.h nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia-modeset/include/nvkms-vrr.h --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia-modeset/include/nvkms-vrr.h 2023-10-25 20:22:36.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia-modeset/include/nvkms-vrr.h 2024-03-05 22:12:15.000000000 +0000 @@ -25,17 +25,31 @@ #define __NVKMS_VRR_H__ #include "nvkms-types.h" -#include "nvkms-modeset-types.h" #ifdef __cplusplus extern "C" { #endif +enum NvKmsDpyVRRType +nvGetAllowedDpyVrrType(const NVDpyEvoRec *pDpyEvo, + const NvModeTimings *pTimings, + enum NvKmsStereoMode stereoMode, + const NvBool allowGsync, + const enum NvKmsAllowAdaptiveSync allowAdaptiveSync); +void nvAdjustHwModeTimingsForVrrEvo(NVHwModeTimingsEvoPtr pTimings, + const enum NvKmsDpyVRRType vrrType, + const NvU32 edidTimeoutMicroseconds, + const NvU32 vrrOverrideMinRefreshRate, + const NvBool needsSwFramePacing); +NvU16 nvPrepareNextVrrNotifier(NVEvoChannelPtr pChannel, NvU32 sd, NvU32 head); +void nvTrackAndDelayFlipForVrrSwFramePacing(NVDispEvoPtr pDispEvo, + const struct NvKmsVrrFramePacingInfo *pVrrFramePacingInfo, + NVFlipChannelEvoHwState *pFlip); + void nvAllocVrrEvo(NVDevEvoPtr pDevEvo); void nvFreeVrrEvo(NVDevEvoPtr pDevEvo); void nvDisableVrr(NVDevEvoPtr pDevEvo); -void nvEnableVrr(NVDevEvoPtr pDevEvo, - const struct NvKmsSetModeRequest *pRequest); +void nvEnableVrr(NVDevEvoPtr pDevEvo); void nvCancelVrrFrameReleaseTimers(NVDevEvoPtr pDevEvo); void nvSetVrrActive(NVDevEvoPtr pDevEvo, NvBool active); void nvApplyVrrBaseFlipOverrides(const NVDispEvoRec *pDispEvo, NvU32 head, @@ -45,7 +59,7 @@ NvS32 nvIncVrrSemaphoreIndex(NVDevEvoPtr pDevEvo); void nvTriggerVrrUnstallMoveCursor(NVDispEvoPtr pDispEvo); void nvTriggerVrrUnstallSetCursorImage(NVDispEvoPtr pDispEvo, - NvBool ctxDmaChanged); + NvBool elvReleased); void nvGetDpyMinRefreshRateValidValues( const NVHwModeTimingsEvo *pTimings, const enum NvKmsDpyVRRType vrrType, diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia-modeset/interface/nvkms-api.h nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia-modeset/interface/nvkms-api.h --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia-modeset/interface/nvkms-api.h 2023-10-25 20:22:36.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia-modeset/interface/nvkms-api.h 2024-03-05 22:12:15.000000000 +0000 @@ -355,6 +355,7 @@ NVKMS_MODE_VALIDATION_REQUIRE_BOOT_CLOCKS = (1 << 16), NVKMS_MODE_VALIDATION_ALLOW_DP_INTERLACED = (1 << 17), NVKMS_MODE_VALIDATION_NO_INTERLACED_MODES = (1 << 18), + NVKMS_MODE_VALIDATION_MAX_ONE_HARDWARE_HEAD = (1 << 19), }; /*! @@ -1277,9 +1278,6 @@ NvKmsConnectorSignalFormat signalFormat; NvU32 physicalIndex; NvU32 physicalLocation; - - /* Bitmask of valid heads to drive dpy(s) on this connector. */ - NvU32 headMask; }; struct NvKmsQueryConnectorStaticDataParams { @@ -1343,6 +1341,8 @@ char dpAddress[NVKMS_DP_ADDRESS_STRING_LENGTH]; NvBool mobileInternal; NvBool isDpMST; + /* Bitmask of valid heads to drive this dpy. */ + NvU32 headMask; }; struct NvKmsQueryDpyStaticDataParams { @@ -1930,13 +1930,7 @@ */ enum NvKmsSetModeOneHeadStatus status; - /*! - * The identifier that we use to talk to RM about the display - * device(s) driven by this head. For DP MST, it is the identifier - * of the DisplayPort library group to which the MST device belongs. - * Otherwise, it is the identifier of the connector. - */ - NvU32 activeRmId; + NvU32 hwHead; /*! * The usage bounds that may be possible on this head based on the ISO @@ -1981,6 +1975,7 @@ NVKMS_SET_MODE_ONE_DISP_STATUS_FAILED_DISPLAY_PORT_BANDWIDTH_CHECK = 3, NVKMS_SET_MODE_ONE_DISP_STATUS_INCOMPATIBLE_DPYS = 4, NVKMS_SET_MODE_ONE_DISP_STATUS_DUPLICATE_DPYS = 5, + NVKMS_SET_MODE_ONE_DISP_STATUS_FAILED_TO_ASSIGN_HARDWARE_HEADS = 6, }; struct NvKmsSetModeOneDispReply { @@ -2120,24 +2115,25 @@ /*! * NVKMS_IOCTL_FLIP: Flip one or more heads on the subdevices of a device. * - * At least one head on one subdevice must be specified in a flip request. + * At least one head must be specified in a flip request, and at most + * NV_MAX_FLIP_REQUEST_HEADS may be specified. */ -struct NvKmsFlipRequestOneSubDevice { - /*! - * The bit mask of which head[] elements to look at on this disp. - */ - NvU32 requestedHeadsBitMask; - struct NvKmsFlipCommonParams head[NVKMS_MAX_HEADS_PER_DISP]; +struct NvKmsFlipRequestOneHead { + NvU32 sd; + NvU32 head; + struct NvKmsFlipCommonParams flip; }; +#define NV_MAX_FLIP_REQUEST_HEADS (NV_MAX_SUBDEVICES * NV_MAX_HEADS) + struct NvKmsFlipRequest { NvKmsDeviceHandle deviceHandle; - /* - * sd[n] corresponds to bit N in NvKmsAllocDeviceReply::subDeviceMask. - */ - struct NvKmsFlipRequestOneSubDevice sd[NVKMS_MAX_SUBDEVICES]; + /* Pointer to an array of length 'numFlipHeads'; each entry in the array is + * of type 'struct NvKmsFlipRequestOneHead'. */ + NvU64 pFlipHead NV_ALIGN_BYTES(8); + NvU32 numFlipHeads; /*! * When a flip request is made, NVKMS will first perform @@ -2166,10 +2162,6 @@ NV_KMS_VRR_FLIP_ADAPTIVE_SYNC, }; -struct NvKmsFlipReplyOneSubDevice { - struct NvKmsFlipCommonReplyOneHead head[NVKMS_MAX_HEADS_PER_DISP]; -}; - struct NvKmsFlipReply { /*! * If vrrFlipType != NV_KMS_VRR_FLIP_NON_VRR, then VRR was used for the @@ -2189,9 +2181,10 @@ enum NvKmsVrrFlipType vrrFlipType; /*! - * sd[n] corresponds to bit N in NvKmsAllocDeviceReply::subDeviceMask. + * Entries correspond to the heads specified in + * NvKmsFlipRequest::pFlipHead, in the same order. */ - struct NvKmsFlipReplyOneSubDevice sd[NVKMS_MAX_SUBDEVICES]; + struct NvKmsFlipCommonReplyOneHead flipHead[NV_MAX_FLIP_REQUEST_HEADS]; }; struct NvKmsFlipParams { @@ -2520,6 +2513,7 @@ enum NvKmsDpyAttribute { NV_KMS_DPY_ATTRIBUTE_BACKLIGHT_BRIGHTNESS = 0, NV_KMS_DPY_ATTRIBUTE_SCANLINE, + NV_KMS_DPY_ATTRIBUTE_HW_HEAD, NV_KMS_DPY_ATTRIBUTE_HEAD, NV_KMS_DPY_ATTRIBUTE_REQUESTED_DITHERING, NV_KMS_DPY_ATTRIBUTE_REQUESTED_DITHERING_MODE, @@ -2558,6 +2552,8 @@ NV_KMS_DPY_ATTRIBUTE_DISPLAYPORT_CONNECTOR_TYPE, NV_KMS_DPY_ATTRIBUTE_DISPLAYPORT_IS_MULTISTREAM, NV_KMS_DPY_ATTRIBUTE_DISPLAYPORT_SINK_IS_AUDIO_CAPABLE, + + NV_KMS_DPY_ATTRIBUTE_NUMBER_OF_HARDWARE_HEADS_USED, }; /*! Values for the NV_KMS_DPY_ATTRIBUTE_REQUESTED_DITHERING attribute. */ @@ -2603,7 +2599,6 @@ NV_KMS_DPY_ATTRIBUTE_CURRENT_COLOR_SPACE_YCbCr422 = 1, NV_KMS_DPY_ATTRIBUTE_CURRENT_COLOR_SPACE_YCbCr444 = 2, NV_KMS_DPY_ATTRIBUTE_CURRENT_COLOR_SPACE_YCbCr420 = 3, - NV_KMS_DPY_ATTRIBUTE_CURRENT_COLOR_SPACE_BT2020RGB = 4, }; /*! Values for the NV_KMS_DPY_ATTRIBUTE_DIGITAL_SIGNAL attribute. */ @@ -2828,6 +2823,8 @@ NV_KMS_FRAMELOCK_ATTRIBUTE_SYNC_RATE, NV_KMS_FRAMELOCK_ATTRIBUTE_SYNC_RATE_4, NV_KMS_FRAMELOCK_ATTRIBUTE_INCOMING_HOUSE_SYNC_RATE, + NV_KMS_FRAMELOCK_ATTRIBUTE_MULTIPLY_DIVIDE_VALUE, + NV_KMS_FRAMELOCK_ATTRIBUTE_MULTIPLY_DIVIDE_MODE, }; /*! Values for the NV_KMS_FRAMELOCK_ATTRIBUTE_POLARITY attribute. */ @@ -2865,6 +2862,12 @@ NV_KMS_FRAMELOCK_ATTRIBUTE_PORT_STATUS_OUTPUT = 1, }; +/*! Values for the NV_KMS_FRAMELOCK_ATTRIBUTE_MULTIPLY_DIVIDE_MODE attribute. */ +enum NvKmsFrameLockAttributeMulDivModeValue { + NV_KMS_FRAMELOCK_ATTRIBUTE_MULTIPLY_DIVIDE_MODE_MULTIPLY = 0, + NV_KMS_FRAMELOCK_ATTRIBUTE_MULTIPLY_DIVIDE_MODE_DIVIDE = 1, +}; + struct NvKmsSetFrameLockAttributeRequest { NvKmsFrameLockHandle frameLockHandle; enum NvKmsFrameLockAttribute attribute; @@ -3243,14 +3246,11 @@ * permissions. * * - The modeset owner can optionally revoke any previously granted - * permissions with NVKMS_IOCTL_REVOKE_PERMISSIONS. + * permissions with NVKMS_IOCTL_REVOKE_PERMISSIONS. This can be + * device-scope for all of a type, or just a set of permissions. * * Notes: * - * - NVKMS_IOCTL_REVOKE_PERMISSIONS has device-scope. It could be - * made finer-grained (e.g., take the file descriptor that was used - * to grant permissions) if that were needed. - * * - NvKmsPermissions::disp[n] corresponds to the disp named by * NvKmsAllocDeviceReply::dispHandles[n]. * @@ -3357,10 +3357,15 @@ /* * A bitmask of permission types to be revoked for this device. - * It should be the bitwise 'or' of one or more + * It should be the bitwise 'or' of any number of * NVBIT(NV_KMS_PERMISSIONS_TYPE_*) values. */ NvU32 permissionsTypeBitmask; + + /* + * If permissionsTypeBitmask is 0, instead revoke only these permissions. + */ + struct NvKmsPermissions permissions; }; struct NvKmsRevokePermissionsReply { diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia-modeset/kapi/interface/nvkms-kapi.h nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia-modeset/kapi/interface/nvkms-kapi.h --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia-modeset/kapi/interface/nvkms-kapi.h 2023-10-25 20:22:37.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia-modeset/kapi/interface/nvkms-kapi.h 2024-03-05 22:12:16.000000000 +0000 @@ -165,8 +165,6 @@ NvU32 physicalIndex; - NvU32 headMask; - NvKmsConnectorSignalFormat signalFormat; NvKmsConnectorType type; @@ -194,6 +192,7 @@ NvU32 numPossibleClones; NvKmsKapiDisplay possibleCloneHandles[NVKMS_KAPI_MAX_CLONE_DISPLAYS]; + NvU32 headMask; }; struct NvKmsKapiSyncpt { @@ -520,14 +519,23 @@ ); /*! - * Revoke modeset permissions previously granted. This currently applies for all - * previous grant requests for this device. + * Revoke permissions previously granted. Only one (dispIndex, head, + * display) is currently supported. + * + * \param [in] device A device returned by allocateDevice(). * - * \param [in] device A device returned by allocateDevice(). + * \param [in] head head of display. + * + * \param [in] display The display to revoke. * * \return NV_TRUE on success, NV_FALSE on failure. */ - NvBool (*revokePermissions)(struct NvKmsKapiDevice *device); + NvBool (*revokePermissions) + ( + struct NvKmsKapiDevice *device, + NvU32 head, + NvKmsKapiDisplay display + ); /*! * Registers for notification, via @@ -1065,6 +1073,21 @@ NvU64 *pPages ); + /*! + * Check if this memory object can be scanned out for display. + * + * \param [in] device A device allocated using allocateDevice(). + * + * \param [in] memory The memory object to check for display support. + * + * \return NV_TRUE if this memory can be displayed, NV_FALSE if not. + */ + NvBool (*isMemoryValidForDisplay) + ( + const struct NvKmsKapiDevice *device, + const struct NvKmsKapiMemory *memory + ); + /* * Import SGT as a memory handle. * diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia-modeset/kapi/src/nvkms-kapi-channelevent.c nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia-modeset/kapi/src/nvkms-kapi-channelevent.c --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia-modeset/kapi/src/nvkms-kapi-channelevent.c 2023-10-25 20:22:37.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia-modeset/kapi/src/nvkms-kapi-channelevent.c 1970-01-01 00:00:00.000000000 +0000 @@ -1,170 +0,0 @@ -/* - * SPDX-FileCopyrightText: Copyright (c) 2016 NVIDIA CORPORATION & AFFILIATES. All rights reserved. - * SPDX-License-Identifier: MIT - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER - * DEALINGS IN THE SOFTWARE. - */ - -#include "nvidia-modeset-os-interface.h" - -#include "nvkms-rmapi.h" - -#include "nvkms-kapi.h" -#include "nvkms-kapi-private.h" -#include "nvkms-kapi-internal.h" - -#include "class/cl0005.h" - -struct NvKmsKapiChannelEvent { - struct NvKmsKapiDevice *device; - - NvKmsChannelEventProc *proc; - void *data; - - struct NvKmsKapiPrivAllocateChannelEventParams nvKmsParams; - - NvHandle hCallbacks[NVKMS_KAPI_MAX_EVENT_CHANNELS]; - NVOS10_EVENT_KERNEL_CALLBACK_EX rmCallback; -}; - -static void ChannelEventHandler(void *arg1, void *arg2, NvHandle hEvent, - NvU32 data, NvU32 status) -{ - struct NvKmsKapiChannelEvent *cb = arg1; - cb->proc(cb->data, 0); -} - -void nvKmsKapiFreeChannelEvent -( - struct NvKmsKapiDevice *device, - struct NvKmsKapiChannelEvent *cb -) -{ - int i; - - if (device == NULL || cb == NULL) { - return; - } - - for (i = 0; i < NVKMS_KAPI_MAX_EVENT_CHANNELS; ++i) { - if (!cb->hCallbacks[i]) { - continue; - } - - nvRmApiFree(device->hRmClient, - device->hRmClient, - cb->hCallbacks[i]); - - nvFreeUnixRmHandle(&device->handleAllocator, - cb->hCallbacks[i]); - } - - nvKmsKapiFree(cb); -} - -struct NvKmsKapiChannelEvent* nvKmsKapiAllocateChannelEvent -( - struct NvKmsKapiDevice *device, - NvKmsChannelEventProc *proc, - void *data, - NvU64 nvKmsParamsUser, - NvU64 nvKmsParamsSize -) -{ - int status, i; - struct NvKmsKapiChannelEvent *cb = NULL; - - if (device == NULL || proc == NULL) { - goto fail; - } - - cb = nvKmsKapiCalloc(1, sizeof(*cb)); - if (cb == NULL) { - goto fail; - } - - /* Verify the driver-private params size and copy it in from userspace */ - - if (nvKmsParamsSize != sizeof(cb->nvKmsParams)) { - nvKmsKapiLogDebug( - "NVKMS private memory import parameter size mismatch - " - "expected: 0x%llx, caller specified: 0x%llx", - (NvU64)sizeof(cb->nvKmsParams), nvKmsParamsSize); - goto fail; - } - - status = nvkms_copyin(&cb->nvKmsParams, - nvKmsParamsUser, sizeof(cb->nvKmsParams)); - if (status != 0) { - nvKmsKapiLogDebug( - "NVKMS private memory import parameters could not be read from " - "userspace"); - goto fail; - } - - cb->device = device; - - cb->proc = proc; - cb->data = data; - - cb->rmCallback.func = ChannelEventHandler; - cb->rmCallback.arg = cb; - - for (i = 0; i < NVKMS_KAPI_MAX_EVENT_CHANNELS; ++i) { - NV0005_ALLOC_PARAMETERS eventParams = { }; - NvU32 ret; - - if (!cb->nvKmsParams.hChannels[i]) { - continue; - } - - cb->hCallbacks[i] = nvGenerateUnixRmHandle(&device->handleAllocator); - if (cb->hCallbacks[i] == 0x0) { - nvKmsKapiLogDeviceDebug(device, - "Failed to allocate event callback handle for channel 0x%x", - cb->nvKmsParams.hChannels[i]); - goto fail; - } - - eventParams.hParentClient = cb->nvKmsParams.hClient; - eventParams.hClass = NV01_EVENT_KERNEL_CALLBACK_EX; - eventParams.notifyIndex = 0; - eventParams.data = NV_PTR_TO_NvP64(&cb->rmCallback); - - ret = nvRmApiAlloc(device->hRmClient, - cb->nvKmsParams.hChannels[i], - cb->hCallbacks[i], - NV01_EVENT_KERNEL_CALLBACK_EX, - &eventParams); - if (ret != NVOS_STATUS_SUCCESS) { - nvKmsKapiLogDeviceDebug(device, - "Failed to allocate event callback for channel 0x%x", - cb->nvKmsParams.hChannels[i]); - nvFreeUnixRmHandle(&device->handleAllocator, cb->hCallbacks[i]); - cb->hCallbacks[i] = 0; - goto fail; - } - } - - return cb; - -fail: - nvKmsKapiFreeChannelEvent(device, cb); - return NULL; -} diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia-modeset/kapi/src/nvkms-kapi-sync.c nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia-modeset/kapi/src/nvkms-kapi-sync.c --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia-modeset/kapi/src/nvkms-kapi-sync.c 1970-01-01 00:00:00.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia-modeset/kapi/src/nvkms-kapi-sync.c 2024-03-05 22:12:17.000000000 +0000 @@ -0,0 +1,170 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2016 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#include "nvidia-modeset-os-interface.h" + +#include "nvkms-rmapi.h" + +#include "nvkms-kapi.h" +#include "nvkms-kapi-private.h" +#include "nvkms-kapi-internal.h" + +#include "class/cl0005.h" + +struct NvKmsKapiChannelEvent { + struct NvKmsKapiDevice *device; + + NvKmsChannelEventProc *proc; + void *data; + + struct NvKmsKapiPrivAllocateChannelEventParams nvKmsParams; + + NvHandle hCallbacks[NVKMS_KAPI_MAX_EVENT_CHANNELS]; + NVOS10_EVENT_KERNEL_CALLBACK_EX rmCallback; +}; + +static void ChannelEventHandler(void *arg1, void *arg2, NvHandle hEvent, + NvU32 data, NvU32 status) +{ + struct NvKmsKapiChannelEvent *cb = arg1; + cb->proc(cb->data, 0); +} + +void nvKmsKapiFreeChannelEvent +( + struct NvKmsKapiDevice *device, + struct NvKmsKapiChannelEvent *cb +) +{ + int i; + + if (device == NULL || cb == NULL) { + return; + } + + for (i = 0; i < NVKMS_KAPI_MAX_EVENT_CHANNELS; ++i) { + if (!cb->hCallbacks[i]) { + continue; + } + + nvRmApiFree(device->hRmClient, + device->hRmClient, + cb->hCallbacks[i]); + + nvFreeUnixRmHandle(&device->handleAllocator, + cb->hCallbacks[i]); + } + + nvKmsKapiFree(cb); +} + +struct NvKmsKapiChannelEvent* nvKmsKapiAllocateChannelEvent +( + struct NvKmsKapiDevice *device, + NvKmsChannelEventProc *proc, + void *data, + NvU64 nvKmsParamsUser, + NvU64 nvKmsParamsSize +) +{ + int status, i; + struct NvKmsKapiChannelEvent *cb = NULL; + + if (device == NULL || proc == NULL) { + goto fail; + } + + cb = nvKmsKapiCalloc(1, sizeof(*cb)); + if (cb == NULL) { + goto fail; + } + + /* Verify the driver-private params size and copy it in from userspace */ + + if (nvKmsParamsSize != sizeof(cb->nvKmsParams)) { + nvKmsKapiLogDebug( + "NVKMS private memory import parameter size mismatch - " + "expected: 0x%llx, caller specified: 0x%llx", + (NvU64)sizeof(cb->nvKmsParams), nvKmsParamsSize); + goto fail; + } + + status = nvkms_copyin(&cb->nvKmsParams, + nvKmsParamsUser, sizeof(cb->nvKmsParams)); + if (status != 0) { + nvKmsKapiLogDebug( + "NVKMS private memory import parameters could not be read from " + "userspace"); + goto fail; + } + + cb->device = device; + + cb->proc = proc; + cb->data = data; + + cb->rmCallback.func = ChannelEventHandler; + cb->rmCallback.arg = cb; + + for (i = 0; i < NVKMS_KAPI_MAX_EVENT_CHANNELS; ++i) { + NV0005_ALLOC_PARAMETERS eventParams = { }; + NvU32 ret; + + if (!cb->nvKmsParams.hChannels[i]) { + continue; + } + + cb->hCallbacks[i] = nvGenerateUnixRmHandle(&device->handleAllocator); + if (cb->hCallbacks[i] == 0x0) { + nvKmsKapiLogDeviceDebug(device, + "Failed to allocate event callback handle for channel 0x%x", + cb->nvKmsParams.hChannels[i]); + goto fail; + } + + eventParams.hParentClient = cb->nvKmsParams.hClient; + eventParams.hClass = NV01_EVENT_KERNEL_CALLBACK_EX; + eventParams.notifyIndex = 0; + eventParams.data = NV_PTR_TO_NvP64(&cb->rmCallback); + + ret = nvRmApiAlloc(device->hRmClient, + cb->nvKmsParams.hChannels[i], + cb->hCallbacks[i], + NV01_EVENT_KERNEL_CALLBACK_EX, + &eventParams); + if (ret != NVOS_STATUS_SUCCESS) { + nvKmsKapiLogDeviceDebug(device, + "Failed to allocate event callback for channel 0x%x", + cb->nvKmsParams.hChannels[i]); + nvFreeUnixRmHandle(&device->handleAllocator, cb->hCallbacks[i]); + cb->hCallbacks[i] = 0; + goto fail; + } + } + + return cb; + +fail: + nvKmsKapiFreeChannelEvent(device, cb); + return NULL; +} diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia-modeset/kapi/src/nvkms-kapi.c nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia-modeset/kapi/src/nvkms-kapi.c --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia-modeset/kapi/src/nvkms-kapi.c 2023-10-25 20:22:37.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia-modeset/kapi/src/nvkms-kapi.c 2024-03-05 22:12:17.000000000 +0000 @@ -43,11 +43,13 @@ #include /* NV0000_CTRL_CMD_GPU_GET_ID_INFO_V2 */ #include /* NV0000_CTRL_CMD_OS_UNIX_IMPORT_OBJECT_FROM_FD */ +#include /* NV0000_CTRL_CMD_CLIENT_GET_ADDR_SPACE_TYPE_VIDMEM */ #include /* NV0080_CTRL_CMD_GPU_GET_NUM_SUBDEVICES */ #include /* NV0080_CTRL_CMD_FB_GET_CAPS_V2 */ #include /* NV2080_CTRL_CMD_OS_UNIX_GC6_BLOCKER_REFCNT */ #include "ctrl/ctrl003e.h" /* NV003E_CTRL_CMD_GET_SURFACE_PHYS_PAGES */ +#include "ctrl/ctrl0041.h" /* NV0041_CTRL_SURFACE_INFO */ ct_assert(NVKMS_KAPI_LAYER_PRIMARY_IDX == NVKMS_MAIN_LAYER); @@ -880,11 +882,20 @@ sizeof(paramsGrant)); } -static NvBool RevokePermissions(struct NvKmsKapiDevice *device) +static NvBool RevokePermissions +( + struct NvKmsKapiDevice *device, + NvU32 head, + NvKmsKapiDisplay display +) { struct NvKmsRevokePermissionsParams paramsRevoke = { }; + struct NvKmsPermissions *perm = ¶msRevoke.request.permissions; + NvU32 dispIdx = device->dispIdx; - if (device == NULL) { + + if (dispIdx >= ARRAY_LEN(perm->modeset.disp) || + head >= ARRAY_LEN(perm->modeset.disp[0].head) || device == NULL) { return NV_FALSE; } @@ -892,8 +903,11 @@ return NV_TRUE; } + perm->type = NV_KMS_PERMISSIONS_TYPE_MODESET; + perm->modeset.disp[dispIdx].head[head].dpyIdList = + nvAddDpyIdToEmptyDpyIdList(nvNvU32ToDpyId(display)); + paramsRevoke.request.deviceHandle = device->hKmsDevice; - paramsRevoke.request.permissionsTypeBitmask = NVBIT(NV_KMS_PERMISSIONS_TYPE_MODESET); return nvkms_ioctl_from_kapi(device->pKmsOpen, NVKMS_IOCTL_REVOKE_PERMISSIONS, ¶msRevoke, @@ -1119,8 +1133,6 @@ info->physicalIndex = paramsConnector.reply.physicalIndex; - info->headMask = paramsConnector.reply.headMask; - info->signalFormat = paramsConnector.reply.signalFormat; info->type = paramsConnector.reply.type; @@ -1176,7 +1188,7 @@ info->dpAddress[sizeof(paramsDpyStatic.reply.dpAddress) - 1] = '\0'; info->internal = paramsDpyStatic.reply.mobileInternal; - + info->headMask = paramsDpyStatic.reply.headMask; done: return status; @@ -1814,6 +1826,57 @@ return NV_TRUE; } +/* + * Check if the memory we are creating this framebuffer with is valid. We + * cannot scan out sysmem or compressed buffers. + * + * If we cannot use this memory for display it may be resident in sysmem + * or may belong to another GPU. + */ +static NvBool IsMemoryValidForDisplay +( + const struct NvKmsKapiDevice *device, + const struct NvKmsKapiMemory *memory +) +{ + NV_STATUS status; + NV0041_CTRL_SURFACE_INFO surfaceInfo = {}; + NV0041_CTRL_GET_SURFACE_INFO_PARAMS surfaceInfoParams = {}; + + if (device == NULL || memory == NULL) { + return NV_FALSE; + } + + /* + * Don't do these checks on tegra. Tegra has different capabilities. + * Here we always say display is possible so we never fail framebuffer + * creation. + */ + if (device->isSOC) { + return NV_TRUE; + } + + /* Get the type of address space this memory is in, i.e. vidmem or sysmem */ + surfaceInfo.index = NV0041_CTRL_SURFACE_INFO_INDEX_ADDR_SPACE_TYPE; + + surfaceInfoParams.surfaceInfoListSize = 1; + surfaceInfoParams.surfaceInfoList = (NvP64)&surfaceInfo; + + status = nvRmApiControl(device->hRmClient, + memory->hRmHandle, + NV0041_CTRL_CMD_GET_SURFACE_INFO, + &surfaceInfoParams, + sizeof(surfaceInfoParams)); + if (status != NV_OK) { + nvKmsKapiLogDeviceDebug(device, + "Failed to get memory location of RM memory object 0x%x", + memory->hRmHandle); + return NV_FALSE; + } + + return surfaceInfo.data == NV0000_CTRL_CMD_CLIENT_GET_ADDR_SPACE_TYPE_VIDMEM; +} + static void FreeMemoryPages ( NvU64 *pPages @@ -2344,10 +2407,9 @@ static NvBool AssignSyncObjectConfig( struct NvKmsKapiDevice *device, const struct NvKmsKapiLayerConfig *pLayerConfig, - struct NvKmsChannelSyncObjects *pSyncObject, - NvBool bFromKmsSetMode) + struct NvKmsChannelSyncObjects *pSyncObject) { - if (!device->supportsSyncpts || bFromKmsSetMode) { + if (!device->supportsSyncpts) { if (pLayerConfig->syncptParams.preSyncptSpecified || pLayerConfig->syncptParams.postSyncptRequested) { return NV_FALSE; @@ -2497,8 +2559,7 @@ ret = AssignSyncObjectConfig(device, layerConfig, - ¶ms->layer[layer].syncObjects.val, - bFromKmsSetMode); + ¶ms->layer[layer].syncObjects.val); if (ret == NV_FALSE) { return ret; } @@ -2598,8 +2659,7 @@ ret = AssignSyncObjectConfig(device, layerConfig, - ¶ms->layer[NVKMS_MAIN_LAYER].syncObjects.val, - bFromKmsSetMode); + ¶ms->layer[NVKMS_MAIN_LAYER].syncObjects.val); if (ret == NV_FALSE) { return ret; } @@ -2877,90 +2937,89 @@ struct NvKmsKapiModeSetReplyConfig *replyConfig, const NvBool commit) { - NvBool bChanged = NV_FALSE; struct NvKmsFlipParams *params = NULL; + struct NvKmsFlipRequestOneHead *pFlipHead = NULL; NvBool status = NV_TRUE; - NvU32 i; + NvU32 i, head; - params = nvKmsKapiCalloc(1, sizeof(*params)); + /* Allocate space for the params structure, plus space for each possible + * head. */ + params = nvKmsKapiCalloc(1, + sizeof(*params) + sizeof(pFlipHead[0]) * NVKMS_KAPI_MAX_HEADS); if (params == NULL) { return NV_FALSE; } + /* The flipHead array was allocated in the same block above. */ + pFlipHead = (struct NvKmsFlipRequestOneHead *)(params + 1); + params->request.deviceHandle = device->hKmsDevice; params->request.commit = commit; params->request.allowVrr = NV_FALSE; + params->request.pFlipHead = nvKmsPointerToNvU64(pFlipHead); + params->request.numFlipHeads = 0; + for (head = 0; + head < ARRAY_LEN(requestedConfig->headRequestedConfig); head++) { - for (i = 0; i < ARRAY_LEN(params->request.sd); i++) { - struct NvKmsFlipRequestOneSubDevice *sdParams = ¶ms->request.sd[i]; - NvU32 head; - - if ((device->subDeviceMask & (1 << i)) == 0x0) { - continue; - } - - for (head = 0; - head < ARRAY_LEN(requestedConfig->headRequestedConfig); head++) { - - const struct NvKmsKapiHeadRequestedConfig *headRequestedConfig = - &requestedConfig->headRequestedConfig[head]; - const struct NvKmsKapiHeadModeSetConfig *headModeSetConfig = - &headRequestedConfig->modeSetConfig; - enum NvKmsOutputTf tf; + const struct NvKmsKapiHeadRequestedConfig *headRequestedConfig = + &requestedConfig->headRequestedConfig[head]; + const struct NvKmsKapiHeadModeSetConfig *headModeSetConfig = + &headRequestedConfig->modeSetConfig; + enum NvKmsOutputTf tf; - struct NvKmsFlipCommonParams *flipParams = &sdParams->head[head]; + struct NvKmsFlipCommonParams *flipParams = NULL; - NvU32 layer; + NvU32 layer; - if (!IsHeadConfigValid(params, requestedConfig, headModeSetConfig, head)) { - continue; - } + if (!IsHeadConfigValid(params, requestedConfig, headModeSetConfig, head)) { + continue; + } - sdParams->requestedHeadsBitMask |= 1 << head; + pFlipHead[params->request.numFlipHeads].sd = 0; + pFlipHead[params->request.numFlipHeads].head = head; + flipParams = &pFlipHead[params->request.numFlipHeads].flip; + params->request.numFlipHeads++; - NvKmsKapiCursorConfigToKms(&headRequestedConfig->cursorRequestedConfig, - flipParams, - NV_FALSE /* bFromKmsSetMode */); - - for (layer = 0; - layer < ARRAY_LEN(headRequestedConfig->layerRequestedConfig); - layer++) { - - const struct NvKmsKapiLayerRequestedConfig - *layerRequestedConfig = - &headRequestedConfig->layerRequestedConfig[layer]; - - status = NvKmsKapiLayerConfigToKms(device, - layerRequestedConfig, - layer, - head, - flipParams, - commit, - NV_FALSE /* bFromKmsSetMode */); + NvKmsKapiCursorConfigToKms(&headRequestedConfig->cursorRequestedConfig, + flipParams, + NV_FALSE /* bFromKmsSetMode */); - if (status != NV_TRUE) { - goto done; - } + for (layer = 0; + layer < ARRAY_LEN(headRequestedConfig->layerRequestedConfig); + layer++) { - bChanged = NV_TRUE; - } + const struct NvKmsKapiLayerRequestedConfig + *layerRequestedConfig = + &headRequestedConfig->layerRequestedConfig[layer]; + + status = NvKmsKapiLayerConfigToKms(device, + layerRequestedConfig, + layer, + head, + flipParams, + commit, + NV_FALSE /* bFromKmsSetMode */); - status = GetOutputTransferFunction(headRequestedConfig, &tf); if (status != NV_TRUE) { goto done; } + } + + status = GetOutputTransferFunction(headRequestedConfig, &tf); + if (status != NV_TRUE) { + goto done; + } - flipParams->tf.val = tf; - flipParams->tf.specified = NV_TRUE; + flipParams->tf.val = tf; + flipParams->tf.specified = NV_TRUE; - if (headModeSetConfig->vrrEnabled) { - params->request.allowVrr = NV_TRUE; - } + if (headModeSetConfig->vrrEnabled) { + params->request.allowVrr = NV_TRUE; } } - if (!bChanged) { + if (params->request.numFlipHeads == 0) { goto done; } @@ -2975,58 +3034,44 @@ goto done; } - if (!bChanged || !commit) { + if (!commit) { goto done; } /*! fill back flip reply */ - for (i = 0; i < ARRAY_LEN(params->request.sd); i++) { - - struct NvKmsFlipReplyOneSubDevice *sdReplyParams = ¶ms->reply.sd[i]; + for (i = 0; i < params->request.numFlipHeads; i++) { + const struct NvKmsKapiHeadRequestedConfig *headRequestedConfig = + &requestedConfig->headRequestedConfig[pFlipHead[i].head]; - NvU32 head; - - if ((device->subDeviceMask & (1 << i)) == 0x0) { - continue; - } + struct NvKmsKapiHeadReplyConfig *headReplyConfig = + &replyConfig->headReplyConfig[pFlipHead[i].head]; - for (head = 0; - head < ARRAY_LEN(requestedConfig->headRequestedConfig); - head++) { - - const struct NvKmsKapiHeadRequestedConfig *headRequestedConfig = - &requestedConfig->headRequestedConfig[head]; - - struct NvKmsKapiHeadReplyConfig *headReplyConfig = - &replyConfig->headReplyConfig[head]; - - const struct NvKmsKapiHeadModeSetConfig *headModeSetConfig = - &headRequestedConfig->modeSetConfig; + const struct NvKmsKapiHeadModeSetConfig *headModeSetConfig = + &headRequestedConfig->modeSetConfig; - struct NvKmsFlipCommonReplyOneHead *flipParams = &sdReplyParams->head[head]; + struct NvKmsFlipCommonReplyOneHead *flipParams = ¶ms->reply.flipHead[i]; - NvU32 layer; + NvU32 layer; - if (!IsHeadConfigValid(params, requestedConfig, headModeSetConfig, head)) { - continue; - } + if (!IsHeadConfigValid(params, requestedConfig, headModeSetConfig, pFlipHead[i].head)) { + continue; + } - for (layer = 0; - layer < ARRAY_LEN(headRequestedConfig->layerRequestedConfig); - layer++) { - - const struct NvKmsKapiLayerConfig *layerRequestedConfig = - &headRequestedConfig->layerRequestedConfig[layer].config; - - struct NvKmsKapiLayerReplyConfig *layerReplyConfig = - &headReplyConfig->layerReplyConfig[layer]; - - /*! initialize explicitly to -1 as 0 is valid file descriptor */ - layerReplyConfig->postSyncptFd = -1; - if (layerRequestedConfig->syncptParams.postSyncptRequested) { - layerReplyConfig->postSyncptFd = - flipParams->layer[layer].postSyncpt.u.fd; - } + for (layer = 0; + layer < ARRAY_LEN(headRequestedConfig->layerRequestedConfig); + layer++) { + + const struct NvKmsKapiLayerConfig *layerRequestedConfig = + &headRequestedConfig->layerRequestedConfig[layer].config; + + struct NvKmsKapiLayerReplyConfig *layerReplyConfig = + &headReplyConfig->layerReplyConfig[layer]; + + /*! initialize explicitly to -1 as 0 is valid file descriptor */ + layerReplyConfig->postSyncptFd = -1; + if (layerRequestedConfig->syncptParams.postSyncptRequested) { + layerReplyConfig->postSyncptFd = + flipParams->layer[layer].postSyncpt.u.fd; } } } @@ -3059,25 +3104,11 @@ const struct NvKmsKapiHeadModeSetConfig *headModeSetConfig = &headRequestedConfig->modeSetConfig; - const struct NvKmsKapiLayerRequestedConfig *primaryLayerRequestedConfig = - &headRequestedConfig->layerRequestedConfig[NVKMS_KAPI_LAYER_PRIMARY_IDX]; - if ((requestedConfig->headsMask & (1 << head)) == 0x0) { continue; } - /* - * Source width/height of primary layer represents width/height of - * ViewPortIn. Destination X, Y, width and height of primary layer - * represents dimensions of ViewPortOut. To apply changes in - * width/height of ViewPortIn and/or changes dimensions of - * ViewPortOut requires full modeset. - */ - bRequiredModeset = - primaryLayerRequestedConfig->flags.srcWHChanged || - primaryLayerRequestedConfig->flags.dstXYChanged || - primaryLayerRequestedConfig->flags.dstWHChanged || headRequestedConfig->flags.activeChanged || headRequestedConfig->flags.displaysChanged || headRequestedConfig->flags.modeChanged; @@ -3287,5 +3318,7 @@ funcsTable->getMemoryPages = GetMemoryPages; funcsTable->freeMemoryPages = FreeMemoryPages; + funcsTable->isMemoryValidForDisplay = IsMemoryValidForDisplay; + return NV_TRUE; } diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia-modeset/os-interface/include/nvidia-modeset-os-interface.h nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia-modeset/os-interface/include/nvidia-modeset-os-interface.h --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia-modeset/os-interface/include/nvidia-modeset-os-interface.h 2023-10-25 20:22:37.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia-modeset/os-interface/include/nvidia-modeset-os-interface.h 2024-03-05 22:12:17.000000000 +0000 @@ -40,17 +40,31 @@ #include "nv_stdarg.h" enum NvKmsSyncPtOp { + /* + * Call into Tegra's kernel nvhost driver, and allocate a syncpoint that can + * be exclusively used by the caller. Internally, this operation will call + * get() to set the initial refcount of the syncpoint to 1. + */ NVKMS_SYNCPT_OP_ALLOC, - NVKMS_SYNCPT_OP_GET, + /* + * Decrease the refcount of an already allocated syncpoint. Once the + * refcount drops to 0, the syncpoint will be returned to the free pool that + * nvhost manages, so PUT can also be used to balance out an ALLOC. + */ NVKMS_SYNCPT_OP_PUT, - NVKMS_SYNCPT_OP_INCR_MAX, - NVKMS_SYNCPT_OP_CPU_INCR, + /* + * Extract syncpt id and thresh from the sync-file file descriptor + */ NVKMS_SYNCPT_OP_FD_TO_ID_AND_THRESH, + /* + * Create dma-fence from syncpt id and thresh value and create sync_file + * file descriptor for the dma-fence handle created. + */ NVKMS_SYNCPT_OP_ID_AND_THRESH_TO_FD, + /* + * read syncpt minimum value of given syncpt + */ NVKMS_SYNCPT_OP_READ_MINVAL, - NVKMS_SYNCPT_OP_READ_MAXVAL, - NVKMS_SYNCPT_OP_SET_MIN_EQ_MAX, - NVKMS_SYNCPT_OP_SET_MAXVAL, }; typedef struct { @@ -62,23 +76,9 @@ struct { NvU32 id; /* in */ - } get; - - struct { - NvU32 id; /* in */ } put; struct { - NvU32 id; /* in */ - NvU32 incr; /* in */ - NvU32 value; /* out */ - } incr_max; - - struct { - NvU32 id; /* in */ - } cpu_incr; - - struct { NvS32 fd; /* in */ NvU32 id; /* out */ NvU32 thresh; /* out */ @@ -94,25 +94,12 @@ NvU32 id; /* in */ NvU32 minval; /* out */ } read_minval; - - struct { - NvU32 id; /* in */ - NvU32 maxval; /* out */ - } read_maxval; - - struct { - NvU32 id; /* in */ - } set_min_eq_max; - - struct { - NvU32 id; /* in */ - NvU32 val; /* in */ - } set_maxval; } NvKmsSyncPtOpParams; NvBool nvkms_output_rounding_fix(void); NvBool nvkms_disable_vrr_memclk_switch(void); +NvBool nvkms_opportunistic_display_sync(void); void nvkms_call_rm (void *ops); void* nvkms_alloc (size_t size, diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia-modeset/os-interface/include/nvkms.h nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia-modeset/os-interface/include/nvkms.h --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia-modeset/os-interface/include/nvkms.h 2023-10-25 20:22:37.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia-modeset/os-interface/include/nvkms.h 2024-03-05 22:12:18.000000000 +0000 @@ -42,6 +42,20 @@ char *buffer, size_t size, nvkms_procfs_out_string_func_t *outString); +/* max number of loops to prevent hanging the kernel if an edge case is hit */ +#define NVKMS_READ_FILE_MAX_LOOPS 1000 +/* max size for any file read by the config system */ +#define NVKMS_READ_FILE_MAX_SIZE 8192 + +/* + * The read file callback should allocate a buffer pointed to by *buff, fill it + * with the contents of fname, and return the size of the buffer. Buffer is not + * guaranteed to be null-terminated. The caller is responsible for freeing the + * buffer with nvkms_free, not nvFree. + */ +typedef size_t nvkms_config_read_file_func_t(char *fname, + char ** const buff); + typedef struct { const char *name; nvkms_procfs_proc_t *func; @@ -74,6 +88,9 @@ void nvKmsGetProcFiles(const nvkms_procfs_file_t **ppProcFiles); +NvBool nvKmsReadConf(const char *buff, size_t size, + nvkms_config_read_file_func_t readfile); + void nvKmsKapiHandleEventQueueChange ( struct NvKmsKapiDevice *device diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia-modeset/src/dp/nvdp-connector-event-sink.cpp nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia-modeset/src/dp/nvdp-connector-event-sink.cpp --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia-modeset/src/dp/nvdp-connector-event-sink.cpp 2023-10-25 20:22:37.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia-modeset/src/dp/nvdp-connector-event-sink.cpp 2024-03-05 22:12:18.000000000 +0000 @@ -39,6 +39,8 @@ namespace nvkmsDisplayPort { +static void EnableVRR(NVDpyEvoPtr pDpyEvo); + ConnectorEventSink::ConnectorEventSink(NVConnectorEvoPtr pConnectorEvo) : pConnectorEvo(pConnectorEvo) { @@ -221,6 +223,131 @@ } } +static bool DpyHasVRREDID(NVDpyEvoPtr pDpyEvo) +{ + return pDpyEvo->parsedEdid.valid && + pDpyEvo->parsedEdid.info.nvdaVsdbInfo.valid && + // As of this writing, only version 1 is defined. + pDpyEvo->parsedEdid.info.nvdaVsdbInfo.vsdbVersion == 1 && + pDpyEvo->parsedEdid.info.nvdaVsdbInfo.vrrData.v1.supportsVrr; +} + +static void EnableVRR(NVDpyEvoPtr pDpyEvo) +{ + NVDispEvoPtr pDispEvo = pDpyEvo->pDispEvo; + DisplayPort::Device *device = pDpyEvo->dp.pDpLibDevice->device; + const NvBool dispSupportsVrr = nvDispSupportsVrr(pDispEvo); + + if (pDpyEvo->internal) { + // VRR + notebooks not supported, yet + pDpyEvo->vrr.type = NVKMS_DPY_VRR_TYPE_NONE; + return; + } + + // If the DP library already has the monitor VRR-enabled, then we don't need to + // do it again, but we should still update the minimum refresh rate from the + // EDID if one is available. + const bool alreadyEnabled = device->isVrrMonitorEnabled() && + device->isVrrDriverEnabled(); + + if (DpyHasVRREDID(pDpyEvo) && !alreadyEnabled) { + // Perform VRR enablement whenever the monitor supports VRR, but only + // record it as actually enabled if the rest of the system supports VRR. + // Other state such as the availability of NV_CTRL_GSYNC_ALLOWED is + // keyed off of the presence of a dpy with vrr.type != + // NVKMS_DPY_VRR_TYPE_NONE. + if (device->startVrrEnablement() && dispSupportsVrr) { + pDpyEvo->vrr.type = NVKMS_DPY_VRR_TYPE_GSYNC; + } else { + pDpyEvo->vrr.type = NVKMS_DPY_VRR_TYPE_NONE; + } + + if ((pDpyEvo->vrr.type == NVKMS_DPY_VRR_TYPE_NONE) && dispSupportsVrr) { + nvEvoLogDisp(pDispEvo, EVO_LOG_WARN, + "%s: Failed to initialize G-SYNC", + pDpyEvo->name); + } + } else if (pDispEvo->pDevEvo->caps.supportsDP13 && + device->getIgnoreMSACap()) { + // DP monitors indicate Adaptive-Sync support through the + // MSA_TIMING_PAR_IGNORED bit in the DOWN_STREAM_PORT_COUNT register + // (DP spec 1.4a section 2.2.4.1.1) + if (dispSupportsVrr) { + if (nvDpyIsAdaptiveSyncDefaultlisted(pDpyEvo)) { + pDpyEvo->vrr.type = + NVKMS_DPY_VRR_TYPE_ADAPTIVE_SYNC_DEFAULTLISTED; + } else { + pDpyEvo->vrr.type = + NVKMS_DPY_VRR_TYPE_ADAPTIVE_SYNC_NON_DEFAULTLISTED; + } + } else { + pDpyEvo->vrr.type = NVKMS_DPY_VRR_TYPE_NONE; + } + + if (pDispEvo->pDevEvo->hal->caps.supportsDisplayRate) { + pDpyEvo->vrr.needsSwFramePacing = dispSupportsVrr; + } + } else { + // Assign pDpyEvo->vrr.type independent of DpyHasVRREDID(), so that if + // the monitor is successfully reenabled by the DP library before it + // calls notifyZombieStateChange(), it'll pick up the correct state. If + // reenablement succeeds, the monitor supports VRR even if we haven't + // read an EDID that says it does yet. + if (alreadyEnabled && dispSupportsVrr) { + pDpyEvo->vrr.type = NVKMS_DPY_VRR_TYPE_GSYNC; + } else { + pDpyEvo->vrr.type = NVKMS_DPY_VRR_TYPE_NONE; + } + } + + if (pDpyEvo->parsedEdid.valid && nvDpyIsAdaptiveSync(pDpyEvo)) { + // Adaptive-Sync minimum refresh rate is either in DisplayID (Display + // ID spec 1.3 section 4.6 Video Timing Range Limits) or EDID (EDID + // spec 1.4 section 3.10.3.3 Display Range Limits & Additional Timing + // Descriptor Definition) + int minRR = 0; + if (pDpyEvo->parsedEdid.info.ext_displayid.version) { + minRR = pDpyEvo->parsedEdid.info.ext_displayid.range_limits[0].vfreq_min; + } + + if (minRR == 0) { + NvU32 i; + for (i = 0; i < NVT_EDID_MAX_LONG_DISPLAY_DESCRIPTOR; i++) { + if (pDpyEvo->parsedEdid.info.ldd[i].tag == + NVT_EDID_DISPLAY_DESCRIPTOR_DRL) { + minRR = pDpyEvo->parsedEdid.info.ldd[i].u.range_limit.min_v_rate; + } + } + } + + if (minRR == 0) { + // Adaptive sync does not support self refresh (zero timeout) + nvEvoLogDisp(pDispEvo, EVO_LOG_WARN, + "%s: G-SYNC Compatible: EDID min refresh rate " + "invalid, disabling G-SYNC Compatible.", + pDpyEvo->name); + pDpyEvo->vrr.type = NVKMS_DPY_VRR_TYPE_NONE; + pDpyEvo->vrr.needsSwFramePacing = FALSE; + } else { + pDpyEvo->vrr.edidTimeoutMicroseconds = 1000000 / minRR; + } + } else if (DpyHasVRREDID(pDpyEvo)) { + // Update the minimum refresh rate if a VRR EDID block is present. + const int minRR = + pDpyEvo->parsedEdid.info.nvdaVsdbInfo.vrrData.v1.minRefreshRate; + + if (minRR == 0) { + // Zero indicates that no refreshes are required (i.e. the panel is + // self-refreshing). + pDpyEvo->vrr.edidTimeoutMicroseconds = 0; + } else { + // Round the timeout down. It's better to refresh the panel too soon + // than too late. + pDpyEvo->vrr.edidTimeoutMicroseconds = 1000000 / minRR; + } + } +} + // when we get this event, the DP lib has done link training and the // EDID has been read (by the DP lib) void ConnectorEventSink::newDevice(DisplayPort::Device *device) @@ -395,12 +522,20 @@ sendEvent = TRUE; } + // Don't reset VRR enablement here. Though normally NVKMS initiates VRR + // enablement, the DP library needs to initiate VRR re-enablement of a + // zombie device itself before performing link training or else the + // monitor might remain blank if a VRR stream is active when it's + // plugged back in. } else { if (!pDpLibDevice->isPlugged && dev->isPlugged()) { pDpLibDevice->isPlugged = TRUE; sendEvent = TRUE; } + // Determine whether the DP library reenabled VRR on this display. + EnableVRR(pDpyEvo); + nvDPAddDeviceToActiveGroup(pDpyEvo); } @@ -486,6 +621,8 @@ // 27000000. Convert back to NV-CONTROL's defines. linkRate /= 27000000; + nvkmsDisplayPort::EnableVRR(pDpyEvo); + switch (pDpLibDevice->device->getConnectorType()) { case DisplayPort::connectorDisplayPort: connectorType = NV_KMS_DPY_ATTRIBUTE_DISPLAYPORT_CONNECTOR_TYPE_DISPLAYPORT; diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia-modeset/src/dp/nvdp-connector.cpp nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia-modeset/src/dp/nvdp-connector.cpp --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia-modeset/src/dp/nvdp-connector.cpp 2023-10-25 20:22:38.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia-modeset/src/dp/nvdp-connector.cpp 2024-03-05 22:12:18.000000000 +0000 @@ -30,7 +30,6 @@ #include "nvkms-evo.h" #include "nvkms-types.h" #include "nvkms-modeset.h" -#include "nvkms-modeset-types.h" #include "nvkms-utils.h" #include "nvkms-rmapi.h" @@ -109,7 +108,10 @@ pNVDpLibConnector->plugged = connected; - if (connected && !nvAssignSOREvo(pConnectorEvo, 0 /* sorExcludeMask */)) { + if (connected && !nvAssignSOREvo(pConnectorEvo->pDispEvo, + nvDpyIdToNvU32(pConnectorEvo->displayId), + FALSE /* b2Heads1Or */, + 0 /* sorExcludeMask */)) { // DPLib takes care of skipping LT on unassigned SOR Display. } @@ -199,67 +201,30 @@ return pGroup; } -/*! - * Returns the bits per pixel for the pixel depth value given - * - * \param[in] pixelDepth nvKmsPixelDepth value - * - * \return The pixel depth configured by this enum value - */ -static NvU32 GetSORBpp( - const enum nvKmsPixelDepth pixelDepth, - const enum NvKmsDpyAttributeCurrentColorSpaceValue colorSpace) -{ - NvU32 bpc = nvPixelDepthToBitsPerComponent(pixelDepth); - if (bpc == 0) { - nvAssert(!"Unrecognized SOR pixel depth"); - /* XXX Assume lowest ? */ - bpc = 6; - } - - /* - * In YUV420, HW is programmed with RGB color space and full color range. - * The color space conversion and color range compression happen in a - * headSurface composite shader. - * - * XXX Add support for - * NV_KMS_DPY_ATTRIBUTE_CURRENT_COLOR_SPACE_YCbCr422 over DP. - */ - nvAssert(colorSpace == NV_KMS_DPY_ATTRIBUTE_CURRENT_COLOR_SPACE_YCbCr420 || - colorSpace == NV_KMS_DPY_ATTRIBUTE_CURRENT_COLOR_SPACE_YCbCr444 || - colorSpace == NV_KMS_DPY_ATTRIBUTE_CURRENT_COLOR_SPACE_RGB); - - /* For RGB/YCbCr444, each pixel is always 3 components. For YCbCr/YUV420, - * we currently always scan out from the headSurface as RGB. */ - return bpc * 3; -} - -/* XXX Instead of tracking pixelDepth, you should track bpc and calculate bpp - * from bpc + colorSpace. */ -static NvU32 GetBpc( - const enum nvKmsPixelDepth pixelDepth, - const enum NvKmsDpyAttributeCurrentColorSpaceValue colorSpace) -{ - NvU32 bpc = nvPixelDepthToBitsPerComponent(pixelDepth); - if (bpc == 0) { - nvAssert(!"Unrecognized SOR pixel depth"); - /* XXX Assume lowest ? */ - return 6; +static NvU32 GetColorDepth( + const enum NvKmsDpyAttributeCurrentColorSpaceValue colorSpace, + const enum NvKmsDpyAttributeColorBpcValue colorBpc) +{ + switch (colorSpace) { + case NV_KMS_DPY_ATTRIBUTE_CURRENT_COLOR_SPACE_YCbCr420: + /* + * In YUV420, HW is programmed with RGB color space and full color + * range. The color space conversion and color range compression + * happen in a headSurface composite shader. + */ + case NV_KMS_DPY_ATTRIBUTE_CURRENT_COLOR_SPACE_YCbCr444: + case NV_KMS_DPY_ATTRIBUTE_CURRENT_COLOR_SPACE_RGB: + /* + * For RGB/YCbCr444, each pixel is always 3 components. For + * YCbCr/YUV420, we currently always scan out from the headSurface + * as RGB. + */ + return colorBpc * 3; + case NV_KMS_DPY_ATTRIBUTE_CURRENT_COLOR_SPACE_YCbCr422: + return colorBpc * 2; } - /* - * In YUV420, HW is programmed with RGB color space and full color range. - * The color space conversion and color range compression happen in a - * headSurface composite shader. - * - * XXX Add support for - * NV_KMS_DPY_ATTRIBUTE_CURRENT_COLOR_SPACE_YCbCr422 over DP. - */ - nvAssert(colorSpace == NV_KMS_DPY_ATTRIBUTE_CURRENT_COLOR_SPACE_YCbCr420 || - colorSpace == NV_KMS_DPY_ATTRIBUTE_CURRENT_COLOR_SPACE_YCbCr444 || - colorSpace == NV_KMS_DPY_ATTRIBUTE_CURRENT_COLOR_SPACE_RGB); - - return bpc; + return 0; } static void SetDPMSATiming(const NVDispEvoRec *pDispEvo, @@ -319,6 +284,7 @@ const NvU32 displayId, const NVHwModeTimingsEvo *pTimings, const enum NvKmsDpyAttributeCurrentColorSpaceValue colorSpace, + const enum NvKmsDpyAttributeColorBpcValue colorBpc, DisplayPort::DpModesetParams *pParams) { pParams->modesetInfo.pixelClockHz = pTimings->pixelClock * 1000; @@ -330,10 +296,8 @@ pParams->modesetInfo.surfaceHeight = nvEvoVisibleHeight(pTimings); pParams->modesetInfo.depth = - GetSORBpp(pTimings->pixelDepth, colorSpace); - - pParams->modesetInfo.bitsPerComponent = - GetBpc(pTimings->pixelDepth, colorSpace); + GetColorDepth(colorSpace, colorBpc); + pParams->modesetInfo.bitsPerComponent = colorBpc; pParams->colorFormat = dpColorFormat_Unknown; switch (colorSpace) { @@ -350,7 +314,6 @@ pParams->colorFormat = dpColorFormat_YCbCr422; break; case NV_KMS_DPY_ATTRIBUTE_CURRENT_COLOR_SPACE_RGB: - case NV_KMS_DPY_ATTRIBUTE_CURRENT_COLOR_SPACE_BT2020RGB: pParams->colorFormat = dpColorFormat_RGB; break; } @@ -366,7 +329,9 @@ const NvU32 displayId, const NVDpyIdList dpyIdList, const enum NvKmsDpyAttributeCurrentColorSpaceValue colorSpace, - NVHwModeTimingsEvo *pTimings) + const enum NvKmsDpyAttributeColorBpcValue colorBpc, + const NVHwModeTimingsEvo *pTimings, + const NVDscInfoEvoRec *pDscInfo) { bool found = false; const NVDPLibConnectorRec *pDpLibConnector = NULL; @@ -399,8 +364,9 @@ displayId, pTimings, colorSpace, + colorBpc, &pDpLibModesetState->modesetParams); - if (pTimings->dpDsc.enable) { + if (pDscInfo->type == NV_DSC_INFO_EVO_TYPE_DP) { pDpLibModesetState->modesetParams.modesetInfo.bEnableDsc = true; /* @@ -409,8 +375,22 @@ * output compressed stream. */ pDpLibModesetState->modesetParams.modesetInfo.depth = - pTimings->dpDsc.bitsPerPixelX16; + pDscInfo->dp.bitsPerPixelX16; + + switch (pDscInfo->dp.dscMode) { + case NV_DSC_EVO_MODE_SINGLE: + pDpLibModesetState->modesetParams.modesetInfo.mode = + DSC_SINGLE; + break; + case NV_DSC_EVO_MODE_DUAL: + pDpLibModesetState->modesetParams.modesetInfo.mode = + DSC_DUAL; + break; + } + } else { + nvAssert(pDscInfo->type == NV_DSC_INFO_EVO_TYPE_DISABLED); } + pDpLibModesetState->dpyIdList = dpyIdList; return pDpLibModesetState; @@ -438,8 +418,11 @@ const NvU32 displayId, const NVDpyIdList dpyIdList, const enum NvKmsDpyAttributeCurrentColorSpaceValue colorSpace, + const enum NvKmsDpyAttributeColorBpcValue colorBpc, const struct NvKmsModeValidationParams *pModeValidationParams, - NVHwModeTimingsEvo *pTimings) + const NVHwModeTimingsEvo *pTimings, + const NvBool b2Heads1Or, + NVDscInfoEvoRec *pDscInfo) { const NVDpyEvoRec *pDpyEvo; const NVDPLibConnectorRec *pDpLibConnector = NULL; @@ -491,12 +474,24 @@ displayId, pTimings, colorSpace, + colorBpc, pModesetParams); + if (b2Heads1Or) { + pModesetParams->modesetInfo.mode = DSC_DUAL; + } + dpDscParams.bCheckWithDsc = true; dpDscParams.forceDsc = pModeValidationParams->forceDsc ? DisplayPort::DSC_FORCE_ENABLE : DisplayPort::DSC_DEFAULT; + /* + * 2Heads1Or requires either YUV420 or DSC; if b2Heads1Or is enabled + * but YUV420 is not, force DSC. + */ + if (b2Heads1Or && (pTimings->yuv420Mode != NV_YUV420_MODE_HW)) { + dpDscParams.forceDsc = DisplayPort::DSC_FORCE_ENABLE; + } dpDscParams.bitsPerPixelX16 = pModeValidationParams->dscOverrideBitsPerPixelX16; dpDscParams.pDscOutParams = pDscOutParams; @@ -505,14 +500,30 @@ pGroup, *pModesetParams, &dpDscParams); - if (ret) { - pTimings->dpDsc.enable = dpDscParams.bEnableDsc; - pTimings->dpDsc.bitsPerPixelX16 = dpDscParams.bitsPerPixelX16; + if (ret && b2Heads1Or) { + /* + * 2Heads1OR requires either YUV420 or DSC; + * dpDscParams.bEnableDsc is assigned by compoundQueryAttach(). + */ + nvAssert(dpDscParams.bEnableDsc || + (pTimings->yuv420Mode == NV_YUV420_MODE_HW)); + } - ct_assert(sizeof(pTimings->dpDsc.pps) == sizeof(pDscOutParams->PPS)); + if (ret && (pDscInfo != NULL)) { + nvkms_memset(pDscInfo, 0, sizeof(*pDscInfo)); - nvkms_memcpy(pTimings->dpDsc.pps, - pDscOutParams->PPS, sizeof(pTimings->dpDsc.pps)); + if (dpDscParams.bEnableDsc) { + pDscInfo->type = NV_DSC_INFO_EVO_TYPE_DP; + + pDscInfo->dp.dscMode = b2Heads1Or ? + NV_DSC_EVO_MODE_DUAL : NV_DSC_EVO_MODE_SINGLE; + pDscInfo->dp.bitsPerPixelX16 = dpDscParams.bitsPerPixelX16; + ct_assert(sizeof(pDscInfo->dp.pps) == sizeof(pDscOutParams->PPS)); + nvkms_memcpy(pDscInfo->dp.pps, pDscOutParams->PPS, + sizeof(pDscInfo->dp.pps)); + } else { + pDscInfo->type = NV_DSC_INFO_EVO_TYPE_DISABLED; + } } done: @@ -549,8 +560,11 @@ NvBool nvDPValidateModeForDpyEvo( const NVDpyEvoRec *pDpyEvo, const enum NvKmsDpyAttributeCurrentColorSpaceValue colorSpace, + const enum NvKmsDpyAttributeColorBpcValue colorBpc, const struct NvKmsModeValidationParams *pModeValidationParams, - NVHwModeTimingsEvo *pTimings) + const NVHwModeTimingsEvo *pTimings, + const NvBool b2Heads1Or, + NVDscInfoEvoRec *pDscInfo) { const NVConnectorEvoRec *pConnectorEvo = pDpyEvo->pConnectorEvo; @@ -565,8 +579,11 @@ 0 /* displayId */, nvAddDpyIdToEmptyDpyIdList(pDpyEvo->id), colorSpace, + colorBpc, pModeValidationParams, - pTimings); + pTimings, + b2Heads1Or, + pDscInfo); connector->endCompoundQuery(); return ret; @@ -679,10 +696,11 @@ if ((newHeadMask & NVBIT(head)) != 0x0 && (oldHeadMask & NVBIT(head)) == 0x0) { - NotifyAttachBegin(pDpLibConnector, - head, - pModesetUpdateState->pDpLibModesetState[head]); - + if (pModesetUpdateState->pDpLibModesetState[head] != NULL) { + NotifyAttachBegin(pDpLibConnector, + head, + pModesetUpdateState->pDpLibModesetState[head]); + } } else if ((newHeadMask & NVBIT(head)) == 0x0 && (oldHeadMask & NVBIT(head)) != 0x0) { @@ -697,7 +715,8 @@ * update. The function should be called for each of affected(change in * head-connector attachment) DpLib connectors, before commit. */ -void nvDPPostSetMode(NVDPLibConnectorPtr pDpLibConnector) +void nvDPPostSetMode(NVDPLibConnectorPtr pDpLibConnector, + const NVEvoModesetUpdateState *pModesetUpdateState) { const NVConnectorEvoRec *pConnectorEvo = pDpLibConnector->pConnectorEvo; @@ -711,8 +730,9 @@ if ((newHeadMask & NVBIT(head)) != 0x0 && (oldHeadMask & NVBIT(head)) == 0x0) { - NotifyAttachEnd(pDpLibConnector, head); - + if (pModesetUpdateState->pDpLibModesetState[head] != NULL) { + NotifyAttachEnd(pDpLibConnector, head); + } } else if ((newHeadMask & NVBIT(head)) == 0x0 && (oldHeadMask & NVBIT(head)) != 0x0) { @@ -764,7 +784,7 @@ params.dpLink = pConnectorEvo->or.protocol == NV0073_CTRL_SPECIFIC_OR_PROTOCOL_SOR_DP_A ? 0 : 1; - params.sorIndex = nvEvoConnectorGetPrimaryOr(pConnectorEvo); + params.sorIndex = pConnectorEvo->or.primary; NvU32 ret = nvRmApiControl( nvEvoGlobal.clientHandle, @@ -799,7 +819,7 @@ */ static NvU32 GetFirmwareHead(NVConnectorEvoPtr pConnectorEvo) { - NvU32 orIndex = nvEvoConnectorGetPrimaryOr(pConnectorEvo); + NvU32 orIndex = pConnectorEvo->or.primary; if (orIndex == NV_INVALID_OR || pConnectorEvo->or.ownerHeadMask[orIndex] == 0) { @@ -820,7 +840,8 @@ FOR_ALL_EVO_CONNECTORS(pOtherConnectorEvo, pDispEvo) { if (pOtherConnectorEvo != pConnectorEvo && nvIsConnectorActiveEvo(pOtherConnectorEvo) && - (pOtherConnectorEvo->or.mask & pConnectorEvo->or.mask) != 0x0) { + (pOtherConnectorEvo->or.primary == pConnectorEvo->or.primary)) { + nvAssert(pOtherConnectorEvo->or.primary != NV_INVALID_OR); return true; } } @@ -868,7 +889,10 @@ pNVDpLibConnector->plugged = plugged; if (plugged && !pNVDpLibConnector->headInFirmware) { - NvBool ret = nvAssignSOREvo(pConnectorEvo, 0 /* sorExcludeMask */); + NvBool ret = nvAssignSOREvo(pDispEvo, + nvDpyIdToNvU32(pConnectorEvo->displayId), + FALSE /* b2Heads1Or */, + 0 /* sorExcludeMask */); nvAssert(ret); if (!ret) { @@ -930,13 +954,17 @@ } static NvBool IsDpSinkMstCapableForceSst(const NVDispEvoRec *pDispEvo, - const NvU32 head) + const NvU32 apiHead) { - const NVDispHeadStateEvoRec *pHeadState = &pDispEvo->headState[head]; - const NVConnectorEvoRec *pConnectorEvo = pHeadState->pConnectorEvo; + const NVDispApiHeadStateEvoRec *pApiHeadState = + &pDispEvo->apiHeadState[apiHead]; + const NVDpyEvoRec *pDpyEvo = + nvGetOneArbitraryDpyEvo(pApiHeadState->activeDpys, pDispEvo); + const NVConnectorEvoRec *pConnectorEvo = (pDpyEvo != NULL) ? + pDpyEvo->pConnectorEvo : NULL; - if (pConnectorEvo == NULL || - pConnectorEvo->pDpLibConnector == NULL) { + if ((pConnectorEvo == NULL) || + (pConnectorEvo->pDpLibConnector == NULL)) { return FALSE; } @@ -948,11 +976,15 @@ static NvBool IsDpLinkTransitionWaitingForHeadShutDown( const NVDispEvoRec *pDispEvo, - const NvU32 head) + const NvU32 apiHead) { - const NVDispHeadStateEvoRec *pHeadState = &pDispEvo->headState[head]; - return pHeadState->pConnectorEvo && - nvDPIsLinkAwaitingTransition(pHeadState->pConnectorEvo); + const NVDispApiHeadStateEvoRec *pApiHeadState = + &pDispEvo->apiHeadState[apiHead]; + const NVDpyEvoRec *pDpyEvo = + nvGetOneArbitraryDpyEvo(pApiHeadState->activeDpys, pDispEvo); + + return (pDpyEvo != NULL) && + nvDPIsLinkAwaitingTransition(pDpyEvo->pConnectorEvo); } void nvDPSetAllowMultiStreaming(NVDevEvoPtr pDevEvo, NvBool allowMST) @@ -979,7 +1011,7 @@ return; } - nvShutDownHeads(pDevEvo, IsDpSinkMstCapableForceSst); + nvShutDownApiHeads(pDevEvo, IsDpSinkMstCapableForceSst); /* * Heads driving MST capable sinks in force SST mode, are shut down. Now you @@ -1004,8 +1036,8 @@ } /* Shut down all DisplayPort heads that need to transition to/from SST. */ - nvShutDownHeads(pDevEvo, - IsDpLinkTransitionWaitingForHeadShutDown); + nvShutDownApiHeads(pDevEvo, + IsDpLinkTransitionWaitingForHeadShutDown); /* * Handle any pending timers the DP library scheduled to notify us diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia-modeset/src/dp/nvdp-device.cpp nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia-modeset/src/dp/nvdp-device.cpp --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia-modeset/src/dp/nvdp-device.cpp 2023-10-25 20:22:38.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia-modeset/src/dp/nvdp-device.cpp 2024-03-05 22:12:18.000000000 +0000 @@ -146,3 +146,12 @@ pDpyEvo->pConnectorEvo->pDpLibConnector->evtSink->lostDevice(device); } + +NvBool nvDPDpyIsDscPossible(const NVDpyEvoRec *pDpyEvo) +{ + if (!nvDpyUsesDPLib(pDpyEvo) || + (pDpyEvo->dp.pDpLibDevice == NULL)) { + return FALSE; + } + return pDpyEvo->dp.pDpLibDevice->device->isDSCPossible(); +} diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia-modeset/src/dp/nvdp-evo-interface.cpp nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia-modeset/src/dp/nvdp-evo-interface.cpp --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia-modeset/src/dp/nvdp-evo-interface.cpp 2023-10-25 20:22:38.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia-modeset/src/dp/nvdp-evo-interface.cpp 2024-03-05 22:12:18.000000000 +0000 @@ -110,7 +110,7 @@ NvU32 EvoInterface::getSorIndex() { - return nvEvoConnectorGetPrimaryOr(pConnectorEvo); + return pConnectorEvo->or.primary; } NvU32 EvoInterface::getLinkIndex() diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia-modeset/src/g_nvkms-evo-states.c nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia-modeset/src/g_nvkms-evo-states.c --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia-modeset/src/g_nvkms-evo-states.c 2023-10-25 20:22:38.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia-modeset/src/g_nvkms-evo-states.c 2024-03-05 22:12:19.000000000 +0000 @@ -50,6 +50,8 @@ static NvBool EvoLockStateLockHeadsFrameLockServerManyHeadsPlusRef(NVDispEvoPtr, NVEvoSubDevPtr, NVEvoLockAction, const NvU32 *pHeads); static NvBool EvoLockStateLockHeadsFrameLockServerPlusRef(NVDispEvoPtr, NVEvoSubDevPtr, NVEvoLockAction, const NvU32 *pHeads); static NvBool EvoLockStateLockHeadsPlusRef(NVDispEvoPtr, NVEvoSubDevPtr, NVEvoLockAction, const NvU32 *pHeads); +static NvBool EvoLockStateMergeMode(NVDispEvoPtr, NVEvoSubDevPtr, NVEvoLockAction, const NvU32 *pHeads); +static NvBool EvoLockStateMergeModeVrr(NVDispEvoPtr, NVEvoSubDevPtr, NVEvoLockAction, const NvU32 *pHeads); static NvBool EvoLockStateNoLock(NVDispEvoPtr, NVEvoSubDevPtr, NVEvoLockAction, const NvU32 *pHeads); static NvBool EvoLockStateSliLastSecondary(NVDispEvoPtr, NVEvoSubDevPtr, NVEvoLockAction, const NvU32 *pHeads); static NvBool EvoLockStateSliLastSecondaryFrameLockClient(NVDispEvoPtr, NVEvoSubDevPtr, NVEvoLockAction, const NvU32 *pHeads); @@ -1407,6 +1409,59 @@ } } +static NvBool EvoLockStateMergeMode( + NVDispEvoPtr pDispEvo, + NVEvoSubDevPtr pEvoSubDev, + NVEvoLockAction action, + const NvU32 *pHeads +) +{ + NvBool queryOnly = pHeads == NULL; + + switch (action) { + + case NV_EVO_DISABLE_MERGE_MODE: + if (!queryOnly) { + nvEvoLockHWStateNoLock(pDispEvo, pEvoSubDev, pHeads); + pEvoSubDev->scanLockState = EvoLockStateNoLock; + } + return TRUE; + + case NV_EVO_ENABLE_VRR: + if (!queryOnly) { + nvEvoLockHWStateNoChange(pDispEvo, pEvoSubDev, pHeads); + pEvoSubDev->scanLockState = EvoLockStateMergeModeVrr; + } + return TRUE; + + default: + return FALSE; + } +} + +static NvBool EvoLockStateMergeModeVrr( + NVDispEvoPtr pDispEvo, + NVEvoSubDevPtr pEvoSubDev, + NVEvoLockAction action, + const NvU32 *pHeads +) +{ + NvBool queryOnly = pHeads == NULL; + + switch (action) { + + case NV_EVO_DISABLE_VRR: + if (!queryOnly) { + nvEvoLockHWStateMergeMode(pDispEvo, pEvoSubDev, pHeads); + pEvoSubDev->scanLockState = EvoLockStateMergeMode; + } + return TRUE; + + default: + return FALSE; + } +} + static NvBool EvoLockStateNoLock( NVDispEvoPtr pDispEvo, NVEvoSubDevPtr pEvoSubDev, @@ -1467,6 +1522,13 @@ } return TRUE; + case NV_EVO_ENABLE_MERGE_MODE: + if (!queryOnly) { + nvEvoLockHWStateMergeMode(pDispEvo, pEvoSubDev, pHeads); + pEvoSubDev->scanLockState = EvoLockStateMergeMode; + } + return TRUE; + default: return FALSE; } diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia-modeset/src/nvkms-3dvision.c nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia-modeset/src/nvkms-3dvision.c --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia-modeset/src/nvkms-3dvision.c 2023-10-25 20:22:38.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia-modeset/src/nvkms-3dvision.c 2024-03-05 22:12:19.000000000 +0000 @@ -24,7 +24,7 @@ #include "nvkms-types.h" #include "nvkms-3dvision.h" -void nv3DVisionAuthenticationEvo(NVDispEvoRec *pDispEvo, const NvU32 head) +void nv3DVisionAuthenticationEvo(NVDispEvoRec *pDispEvo, const NvU32 apiHead) { return; } @@ -47,7 +47,7 @@ } void nvSendHwModeTimingsToAegisEvo(const NVDispEvoRec *pDispEvo, - const NvU32 head) + const NvU32 apiHead) { return; } diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia-modeset/src/nvkms-attributes.c nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia-modeset/src/nvkms-attributes.c --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia-modeset/src/nvkms-attributes.c 2023-10-25 20:22:38.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia-modeset/src/nvkms-attributes.c 2024-03-05 22:12:20.000000000 +0000 @@ -31,6 +31,7 @@ #include "nvkms-rmapi.h" #include "nvos.h" #include "nvkms-stereo.h" +#include "nvkms-hdmi.h" #include // NV0073_CTRL_CMD_DP_GET_LINK_CONFIG_* @@ -196,6 +197,14 @@ return TRUE; } +static NvBool GetHwHead(const NVDpyEvoRec *pDpyEvo, NvS64 *pHead) +{ + NvU32 primaryHwHead = + nvGetPrimaryHwHead(pDpyEvo->pDispEvo, pDpyEvo->apiHead); + *pHead = (NvS64)primaryHwHead; + return TRUE; +} + static NvBool DitherConfigurationAllowed(const NVDpyEvoRec *pDpyEvo) { NVDispEvoPtr pDispEvo = pDpyEvo->pDispEvo; @@ -210,7 +219,6 @@ const NVConnectorEvoRec *pConnectorEvo = pDpyEvo->pConnectorEvo; NVDispEvoRec *pDispEvo = pConnectorEvo->pDispEvo; NVDispApiHeadStateEvoRec *pApiHeadState; - enum nvKmsPixelDepth pixelDepth; NvU32 head; if (pDpyEvo->apiHead == NV_INVALID_HEAD) { @@ -221,16 +229,8 @@ nvAssert((pApiHeadState->hwHeadsMask) != 0x0 && (nvDpyIdIsInDpyIdList(pDpyEvo->id, pApiHeadState->activeDpys))); - head = nvGetPrimaryHwHead(pDispEvo, pDpyEvo->apiHead); - pixelDepth = pDispEvo->headState[head].timings.pixelDepth; -#if defined(DEBUG) - FOR_EACH_EVO_HW_HEAD_IN_MASK(pApiHeadState->hwHeadsMask, head) { - nvAssert(pixelDepth == pDispEvo->headState[head].timings.pixelDepth); - } -#endif - nvChooseDitheringEvo(pConnectorEvo, - pixelDepth, + pApiHeadState->attributes.colorBpc, &pDpyEvo->requestedDithering, &pApiHeadState->attributes.dithering); @@ -613,10 +613,12 @@ */ static void DpyPostColorSpaceOrRangeSetEvo(NVDpyEvoPtr pDpyEvo) { + enum NvKmsDpyAttributeCurrentColorSpaceValue colorSpace; + enum NvKmsDpyAttributeColorBpcValue colorBpc; + enum NvKmsDpyAttributeColorRangeValue colorRange; NVEvoUpdateState updateState = { }; NVDispEvoRec *pDispEvo = pDpyEvo->pDispEvo; NVDispApiHeadStateEvoRec *pApiHeadState; - enum nvKmsPixelDepth pixelDepth; enum NvYuv420Mode yuv420Mode; enum NvKmsOutputTf tf; NvU32 head; @@ -630,13 +632,12 @@ (nvDpyIdIsInDpyIdList(pDpyEvo->id, pApiHeadState->activeDpys))); head = nvGetPrimaryHwHead(pDispEvo, pDpyEvo->apiHead); - pixelDepth = pDispEvo->headState[head].timings.pixelDepth; yuv420Mode = pDispEvo->headState[head].timings.yuv420Mode; tf = pDispEvo->headState[head].tf; #if defined(DEBUG) FOR_EACH_EVO_HW_HEAD_IN_MASK(pApiHeadState->hwHeadsMask, head) { - nvAssert(pixelDepth == pDispEvo->headState[head].timings.pixelDepth); nvAssert(yuv420Mode == pDispEvo->headState[head].timings.yuv420Mode); + nvAssert(tf == pDispEvo->headState[head].tf); } #endif @@ -644,21 +645,45 @@ * Choose current colorSpace and colorRange based on the current mode * timings and the requested color space and range. */ - nvChooseCurrentColorSpaceAndRangeEvo(pixelDepth, - yuv420Mode, - tf, - pDpyEvo->requestedColorSpace, - pDpyEvo->requestedColorRange, - &pApiHeadState->attributes.colorSpace, - &pApiHeadState->attributes.colorRange); + if (!nvChooseCurrentColorSpaceAndRangeEvo(pDpyEvo, + yuv420Mode, + tf, + pDpyEvo->requestedColorSpace, + pDpyEvo->requestedColorRange, + &colorSpace, + &colorBpc, + &colorRange)) { + nvAssert(!"Failed to choose current color space and color range"); + return; + } + + /* For DP, neither color space nor bpc can be changed without a modeset */ + if (nvConnectorUsesDPLib(pDpyEvo->pConnectorEvo) && + ((pApiHeadState->attributes.colorSpace != colorSpace) || + (pApiHeadState->attributes.colorBpc != colorBpc))) { + return; + } + + pApiHeadState->attributes.colorSpace = colorSpace; + pApiHeadState->attributes.colorRange = colorRange; + pApiHeadState->attributes.colorBpc = colorBpc; /* Update hardware's current colorSpace and colorRange */ FOR_EACH_EVO_HW_HEAD_IN_MASK(pApiHeadState->hwHeadsMask, head) { + enum nvKmsPixelDepth newPixelDepth = + nvEvoColorSpaceBpcToPixelDepth(pApiHeadState->attributes.colorSpace, + pApiHeadState->attributes.colorBpc); + nvUpdateCurrentHardwareColorSpaceAndRangeEvo(pDispEvo, head, pApiHeadState->attributes.colorSpace, pApiHeadState->attributes.colorRange, &updateState); + + if (newPixelDepth != pDispEvo->headState[head].pixelDepth) { + pDispEvo->headState[head].pixelDepth = newPixelDepth; + nvEvoHeadSetControlOR(pDispEvo, head, &updateState); + } } /* Update InfoFrames as needed. */ @@ -672,15 +697,18 @@ static NvU32 DpyGetValidColorSpaces(const NVDpyEvoRec *pDpyEvo) { + const NVDevEvoRec *pDevEvo = pDpyEvo->pDispEvo->pDevEvo; NvU32 val = (1 << NV_KMS_DPY_ATTRIBUTE_REQUESTED_COLOR_SPACE_RGB); - if (pDpyEvo->pConnectorEvo->colorSpaceCaps.ycbcr422Capable && - pDpyEvo->colorSpaceCaps.ycbcr422Capable) { + if ((nvDpyIsHdmiEvo(pDpyEvo) && + (pDevEvo->caps.hdmiYCbCr422MaxBpc != 0)) || + (nvConnectorUsesDPLib(pDpyEvo->pConnectorEvo) && + (pDevEvo->caps.dpYCbCr422MaxBpc != 0))) { val |= (1 << NV_KMS_DPY_ATTRIBUTE_REQUESTED_COLOR_SPACE_YCbCr422); } - if (pDpyEvo->pConnectorEvo->colorSpaceCaps.ycbcr444Capable && - pDpyEvo->colorSpaceCaps.ycbcr444Capable) { + if (nvDpyIsHdmiEvo(pDpyEvo) || + nvConnectorUsesDPLib(pDpyEvo->pConnectorEvo)) { val |= (1 << NV_KMS_DPY_ATTRIBUTE_REQUESTED_COLOR_SPACE_YCbCr444); } @@ -1057,16 +1085,85 @@ static NvBool GetVrrMinRefreshRate(const NVDpyEvoRec *pDpyEvo, NvS64 *pValue) { - return FALSE; + NvU32 timeoutMicroseconds; + const NVDispEvoRec *pDispEvo = pDpyEvo->pDispEvo; + NvU32 head; + + if (pDpyEvo->apiHead == NV_INVALID_HEAD) { + return FALSE; + } + + head = nvGetPrimaryHwHead(pDispEvo, pDpyEvo->apiHead); + nvAssert(head != NV_INVALID_HEAD); + timeoutMicroseconds = + pDispEvo->headState[head].timings.vrr.timeoutMicroseconds; +#if defined(DEBUG) + { + NvU32 h; + FOR_EACH_EVO_HW_HEAD(pDispEvo, pDpyEvo->apiHead, h) { + nvAssert(timeoutMicroseconds == + pDispEvo->headState[h].timings.vrr.timeoutMicroseconds); + } + } +#endif + + *pValue = timeoutMicroseconds ? (1000000 / timeoutMicroseconds) : 0; + + return TRUE; } static NvBool GetVrrMinRefreshRateValidValues( const NVDpyEvoRec *pDpyEvo, struct NvKmsAttributeValidValuesCommonReply *pValidValues) { - return FALSE; + NvU32 minMinRefreshRate, maxMinRefreshRate; + const NVDispEvoRec *pDispEvo = pDpyEvo->pDispEvo; + NvU32 head; + + if (pDpyEvo->apiHead == NV_INVALID_HEAD) { + return FALSE; + } + + head = nvGetPrimaryHwHead(pDispEvo, pDpyEvo->apiHead); + nvAssert(head != NV_INVALID_HEAD); + nvGetDpyMinRefreshRateValidValues(&pDispEvo->headState[head].timings, + pDpyEvo->vrr.type, + pDpyEvo->vrr.edidTimeoutMicroseconds, + &minMinRefreshRate, + &maxMinRefreshRate); +#if defined(DEBUG) + { + NvU32 h; + FOR_EACH_EVO_HW_HEAD(pDispEvo, pDpyEvo->apiHead, h) { + NvU32 tmpMinMinRefreshRate, tmpMaxMinRefreshRate; + + nvGetDpyMinRefreshRateValidValues(&pDispEvo->headState[h].timings, + pDpyEvo->vrr.type, + pDpyEvo->vrr.edidTimeoutMicroseconds, + &tmpMinMinRefreshRate, + &tmpMaxMinRefreshRate); + + nvAssert(tmpMinMinRefreshRate == minMinRefreshRate); + nvAssert(tmpMaxMinRefreshRate == maxMinRefreshRate); + } + } +#endif + + nvAssert(pValidValues->type == NV_KMS_ATTRIBUTE_TYPE_RANGE); + + pValidValues->u.range.min = minMinRefreshRate; + pValidValues->u.range.max = maxMinRefreshRate; + + return TRUE; } +static NvBool GetNumberOfHardwareHeadsUsed( + const NVDpyEvoRec *pDpyEvo, + NvS64 *pNumHwHeadsUsed) +{ + *pNumHwHeadsUsed = pDpyEvo->currentAttributes.numberOfHardwareHeadsUsed; + return TRUE; +} static const struct { NvBool (*set)(NVDpyEvoPtr pDpyEvo, NvS64 value); NvBool (*get)(const NVDpyEvoRec *pDpyEvo, NvS64 *pValue); @@ -1093,6 +1190,12 @@ .getValidValues = NULL, .type = NV_KMS_ATTRIBUTE_TYPE_INTEGER, }, + [NV_KMS_DPY_ATTRIBUTE_HW_HEAD] = { + .set = NULL, + .get = GetHwHead, + .getValidValues = NULL, + .type = NV_KMS_ATTRIBUTE_TYPE_INTEGER, + }, [NV_KMS_DPY_ATTRIBUTE_REQUESTED_DITHERING] = { .set = SetDithering, .get = GetDithering, @@ -1249,6 +1352,12 @@ .getValidValues = GetVrrMinRefreshRateValidValues, .type = NV_KMS_ATTRIBUTE_TYPE_RANGE, }, + [NV_KMS_DPY_ATTRIBUTE_NUMBER_OF_HARDWARE_HEADS_USED] = { + .set = NULL, + .get = GetNumberOfHardwareHeadsUsed, + .getValidValues = NULL, + .type = NV_KMS_ATTRIBUTE_TYPE_INTEGER, + }, }; /*! diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia-modeset/src/nvkms-conf.c nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia-modeset/src/nvkms-conf.c --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia-modeset/src/nvkms-conf.c 1970-01-01 00:00:00.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia-modeset/src/nvkms-conf.c 2024-03-05 22:12:20.000000000 +0000 @@ -0,0 +1,599 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#include "nvkms-utils.h" +#include "nvkms-dpy-override.h" + +static NvBool CharIsSpace(char c) +{ + return (c == ' ' || /* space */ + c == '\f' || /* form feed */ + c == '\n' || /* line feed */ + c == '\r' || /* carriage return */ + c == '\t' || /* horizontal tab */ + c == '\v'); /* vertical tab */ +} + +/* Display Override Conf File Initialization */ +static inline NvU8 AsciiHexCharToNibble(char hex) +{ + if (hex >= '0' && hex <= '9') { + return hex - '0'; + } else if (hex >= 'A' && hex <= 'F') { + return hex - 'A' + 0xA; + } else if (hex >= 'a' && hex <= 'f') { + return hex - 'a' + 0xA; + } else { + return 0xFF; + } +} + +/* bin should be able to hold at least (size / 2) bytes */ +static size_t AsciiHexToBin(char *bin, const char *hex, size_t size) +{ + size_t hi, bi; + NvBool highNibble = TRUE; + NvU8 upnib = 0; + + if (hex == NULL || bin == NULL) { + return 0; + } + if (bin >= hex && bin <= hex + size) { + /* + * Although, theoretically, decoding ascii hex in place should work + * fine - each set of 2 characters encodes 1 byte - it's best to avoid + * the complexity + */ + nvAssert(!"ASCII hex would be decoded in place."); + return 0; + } + + for(hi = 0, bi = 0; hi < size; hi++) { + NvU8 nibble; + + if (CharIsSpace(hex[hi])) { + continue; + } + + nibble = AsciiHexCharToNibble(hex[hi]); + if (nibble > 0xF) { + return 0; /* invalid character */ + } + + if (highNibble) { + upnib = nibble << 4; + } else { + bin[bi++] = upnib | nibble; + } + highNibble = !highNibble; + } + + if (!highNibble) { + return 0; /* odd number of hex chars */ + } + + return bi; +} + +#define SUBPARSER(name) static NvBool Subparser_ ## name( \ + const char *key, \ + const char *value, \ + nvkms_config_read_file_func_t readfile) + +SUBPARSER(override) +{ + size_t i; + size_t idLen = 0; + size_t valLen = nvkms_strlen(value); + + NvU32 gpuId = NV0000_CTRL_GPU_INVALID_ID; + const char *name = NULL; + + static nv_gpu_info_t devs[NV_MAX_GPUS]; + NvU32 numdevs = nvkms_enumerate_gpus(devs); + + if (key[0] == '[') { + while (key[idLen] != 0 && key[idLen] != ']') { + idLen++; + } + } + + while (key[idLen] != 0 && key[idLen] != '.') { + idLen++; + } + + /* Get the GPU ID */ + if (key[0] == '[') { + /* GPU PCI Address */ + NvU32 domain = 0xFFFFFFFF, temp = 0; + NvU8 bus = 0xFF, slot = 0xFF, function = 0xFF; + size_t j; + + for (i = 1, j = 0; (key[i] != 0) && (key[i] != ']') && (j < 4); i++) { + if (key[i] == ':') { + if (j == 0) { + domain = temp; + } else if (j == 1) { + bus = (NvU8)temp; + } else { + break; + } + j++; + temp = 0; + } else if (key[i] == '.') { + if (j == 2) { + slot = (NvU8)temp; + } else { + break; + } + j++; + temp = 0; + } else { + NvU8 nibble = AsciiHexCharToNibble(key[i]); + if (nibble > 0xF) { + break; + } + temp <<= 4; + temp |= nibble; + } + } + + if (j == 3) { + function = (NvU8)temp; + j++; + } + + if (j != 4) { + nvEvoLog(EVO_LOG_WARN, "Syntax error in override entry: " + "Error reading PCI Address: %.*s " + "(%zu fields read)", (int)idLen, key, j); + nvClearDpyOverrides(); + return FALSE; + } + + for (size_t i = 0; i < numdevs; i++) { + if (devs[i].pci_info.domain == domain && + devs[i].pci_info.bus == bus && + devs[i].pci_info.slot == slot && + devs[i].pci_info.function == function) { + + gpuId = devs[i].gpu_id; + break; + } + } + if (gpuId == NV0000_CTRL_GPU_INVALID_ID) { + nvEvoLog(EVO_LOG_WARN, "Error in override entry: " + "No GPU with PCI Address %04x:%02hhx:%02hhx.%hhx", + domain, bus, slot, function); + nvClearDpyOverrides(); + return FALSE; + } + } else if (idLen == 5 && nvkms_memcmp(key, "tegra", 5) == 0){ + gpuId = NVKMS_DEVICE_ID_TEGRA; + } else { + nvEvoLog(EVO_LOG_WARN, "Syntax error in override entry: " + "Unknown GPU designator: %.*s", (int)idLen, key); + return FALSE; + } + + /* Get the dpy name */ + if (key[idLen] != '.' || key[idLen + 1] == 0) { + nvEvoLog(EVO_LOG_WARN, "Syntax error in override entry: " + "Expected '.' followed by display name"); + return FALSE; + } + name = key + (idLen + 1); + + /* Get the edid */ + if (value[0] == '"' && value[valLen - 1] == '"') { + valLen -= 2; + value += 1; + } + + if (value[0] == '/') { + size_t bufflen = 0; + char *buff = NULL; + + if (readfile != NULL) { + char *fname = nvCalloc(valLen + 1, 1); + nvkms_memcpy(fname, value, valLen); + bufflen = readfile(fname, &buff); + nvFree(fname); + } + + if (bufflen == 0) { + nvEvoLog(EVO_LOG_WARN, "Error in override entry: " + "Error opening EDID file: %.*s", (int)valLen, value); + nvClearDpyOverrides(); + return FALSE; + } + + nvCreateDpyOverride(gpuId, name, TRUE, buff, bufflen); + nvkms_free(buff, bufflen); + } else if (valLen == 12 && nvkms_memcmp(value, "disconnected", 12) == 0) { + nvCreateDpyOverride(gpuId, name, FALSE, NULL, 0); + } else { + char *edidBuf = nvCalloc(valLen / 2, 1); + size_t decoded = AsciiHexToBin(edidBuf, value, valLen); + if (decoded == 0) { + nvEvoLog(EVO_LOG_WARN, "Error in override entry: " + "Error decoding ASCII hex: %.*s\n", (int)valLen, value); + nvFree(edidBuf); + nvClearDpyOverrides(); + return FALSE; + } + + nvCreateDpyOverride(gpuId, name, TRUE, edidBuf, decoded); + nvFree(edidBuf); + } + + return TRUE; +} + +#undef SUBPARSER + +static NvBool Subparse( + const char *keyhead, + const char *keytail, + const char *value, + nvkms_config_read_file_func_t readfile) +{ +#define SUBPARSE(name) if (nvkms_strcmp(keyhead, #name) == 0) { \ + return Subparser_ ## name(keytail, value, readfile); \ +} + SUBPARSE(override); + nvEvoLog(EVO_LOG_WARN, "Error reading configuration file: " + "Parser not found for key: %s.%s", keyhead, keytail); + return FALSE; +#undef SUBPARSE +} + +#define ST_KEYHEAD 0 /* read head of key */ +#define ST_KEYTAIL 1 /* read tail of key */ +#define ST_VALUE 2 /* read value of key */ +#define ST_EQUALS 3 /* expect '=' */ +#define ST_SEND 4 /* send values */ + +/* + * This function implements a state machine: + * KEYHEAD -> KEYTAIL : when a '.' is read + * KEYHEAD -> EQUALS : when whitespace is read + * KEYHEAD -> VALUE : when '=' is read + * KEYTAIL -> EQUALS : when whitespace is read + * KEYTAIL -> VALUE : when '=' is read + * EQUALS -> VALUE : when '=' is read + * VALUE -> SEND : when whitespace is read + * SEND -> KEYHEAD : consumes no input but sends strings to further parser functions + * + * Here, whitespace means any block of one or more whitespace characters, as + * determined by the CharIsSpace() helper function. Whitespace only causes state + * transitions if at least one non-whitespace character has been read in that + * state + * + * When a '#' is read, all input is consumed until a '\n' is read or the end of + * the buffer is reached. This input is treated as whitespace for the purposes + * of the above state transitions and is considered part of any surrounding + * whitespace + * + * When a '"', '(', '{', '[', or '<' is read while in KEYHEAD, KEYTAIL, or VALUE, + * a substate is entered which consumes all input until a corresponding '"', ')', + * '}', ']', or '>' is read. While in this substate, '.', whitespace, '=', and '#' + * do not cause state transitions. + * + * While in KEYHEAD, KEYTAIL, or VALUE, all consumed input which does not cause + * state transitions are added to the corresponding string to be passed to + * further parser functions. + * + * NOTE: buff is not guaranteed to be NULL-terminated + */ +NvBool nvKmsReadConf( + const char *buff, + size_t size, + nvkms_config_read_file_func_t readfile) +{ + size_t i; + NvBool ret = FALSE; /* set false until success noted */ + + int state = ST_KEYHEAD; /* state machine's current state */ + char watchfor = 0; /* marker for paired char blocks */ + const char *ptr = NULL; /* pointer into buffer */ + char *strs[3] = { NULL, NULL, NULL }; /* alloced strings to be copied to */ + size_t lens[3] = { 0, 0, 0 }; /* lengths of strings in strs */ + + /* named pointers into strs */ + char ** const keyhead = &strs[ST_KEYHEAD]; + char ** const keytail = &strs[ST_KEYTAIL]; + char ** const value = &strs[ST_VALUE]; + + /* verify that there's always a string allocated in each of the slots */ + for (i = 0; i < 3; ++i) { + strs[i] = nvCalloc(1, 1); + if (strs[i] == NULL) { + nvEvoLog(EVO_LOG_WARN, "Error reading configuration file: " + "Out of memory"); + goto teardown; + } + lens[i] = 1; + } + +#define COPYPTR() do { \ + size_t strlen; \ + nvAssert(ptr != NULL); \ + nvAssert(state == ST_KEYHEAD || state == ST_KEYTAIL || state == ST_VALUE); \ + strlen = (buff + i) - ptr; \ + if (lens[state] < strlen + 1) { \ + /* allocate strlen + 1 to ensure a null terminator */ \ + nvFree(strs[state]); \ + strs[state] = nvCalloc(strlen + 1, 1); \ + if (strs[state] == NULL) { \ + nvEvoLog(EVO_LOG_WARN, "Error reading configuration file: " \ + "Out of memory"); \ + goto teardown; \ + } \ + lens[state] = strlen + 1; \ + } \ + nvkms_memcpy(strs[state], ptr, strlen); \ + strs[state][strlen] = 0; \ + ptr = NULL; \ +} while (0) + + for (i = 0; i < size; i++) { + /* + * If watchfor is set, then either we're in a comment or we're in a + * paired block. If we're in a comment (watchfor == '\n'), then we + * want ptr to be NULL, so that the comment isn't included in content. + * If we're not in a comment (watchfor == '"', ')', '}', ']', or '>'), + * we want ptr to be non-NULL, so that the paired block is included in + * the content. + */ + nvAssert(watchfor == 0 || + (watchfor != '\n' && ptr != NULL) || + (watchfor == '\n' && ptr == NULL)); + + if (state == ST_KEYHEAD) { + if (watchfor == 0) { + if (buff[i] == '.') { + if (ptr == NULL) { + nvEvoLog(EVO_LOG_WARN, "Syntax error in configuration file: " + "'.' at start of key"); + goto teardown; + } + + COPYPTR(); + state = ST_KEYTAIL; + } else if (buff[i] == '=') { + if (ptr == NULL) { + nvEvoLog(EVO_LOG_WARN, "Syntax error in configuration file: " + "key expected before '='"); + goto teardown; + } + + COPYPTR(); + state = ST_VALUE; + } else if (buff[i] == '"') { + if (ptr == NULL) { + ptr = buff + i; + } + watchfor = '"'; + } else if (buff[i] == '(') { + if (ptr == NULL) { + ptr = buff + i; + } + watchfor = ')'; + } else if (buff[i] == '{') { + if (ptr == NULL) { + ptr = buff + i; + } + watchfor = '}'; + } else if (buff[i] == '[') { + if (ptr == NULL) { + ptr = buff + i; + } + watchfor = ']'; + } else if (buff[i] == '<') { + if (ptr == NULL) { + ptr = buff + i; + } + watchfor = '>'; + } else if (buff[i] == '#') { + if (ptr != NULL) { + COPYPTR(); + state = ST_EQUALS; + } + watchfor = '\n'; + } else if (CharIsSpace(buff[i])) { + if (ptr != NULL) { + COPYPTR(); + state = ST_EQUALS; + } + } else if (ptr == NULL) { + ptr = buff + i; + } + } else if (buff[i] == watchfor) { + watchfor = 0; + } + } else if (state == ST_KEYTAIL) { + if (watchfor == 0) { + if (buff[i] == '=') { + if (ptr == NULL) { + nvEvoLog(EVO_LOG_WARN, "Syntax error in configuration file: " + "identifier expected after '.' in \"%s\" key", + *keyhead); + goto teardown; + } + + COPYPTR(); + state = ST_VALUE; + } else if (buff[i] == '"') { + if (ptr == NULL) { + ptr = buff + i; + } + watchfor = '"'; + } else if (buff[i] == '(') { + if (ptr == NULL) { + ptr = buff + i; + } + watchfor = ')'; + } else if (buff[i] == '{') { + if (ptr == NULL) { + ptr = buff + i; + } + watchfor = '}'; + } else if (buff[i] == '[') { + if (ptr == NULL) { + ptr = buff + i; + } + watchfor = ']'; + } else if (buff[i] == '<') { + if (ptr == NULL) { + ptr = buff + i; + } + watchfor = '>'; + } else if (buff[i] == '#') { + if (ptr != NULL) { + COPYPTR(); + state = ST_EQUALS; + } + watchfor = '\n'; + } else if (CharIsSpace(buff[i])) { + if (ptr != NULL) { + COPYPTR(); + state = ST_EQUALS; + } + } else if (ptr == NULL) { + ptr = buff + i; + } + } else if (buff[i] == watchfor) { + watchfor = 0; + } + } else if (state == ST_EQUALS) { + nvAssert(ptr == NULL); + /* watchfor should only ever be set if we're in a comment */ + nvAssert(watchfor == 0 || watchfor == '\n'); + + if (watchfor == 0) { + if (buff[i] == '=') { + state = ST_VALUE; + } else if (buff[i] == '#') { + watchfor = '\n'; + } else if (!CharIsSpace(buff[i])) { + nvEvoLog(EVO_LOG_WARN, "Syntax error in configuration file: " + "expected '=' before value"); + goto teardown; + } + } else if (buff[i] == watchfor) { + watchfor = 0; + } + + } else if (state == ST_VALUE) { + if (watchfor == 0) { + if (buff[i] == '=') { + nvEvoLog(EVO_LOG_WARN, "Syntax error in configuration file: " + "unexpected '=' in value"); + goto teardown; + } else if (buff[i] == '"') { + if (ptr == NULL) { + ptr = buff + i; + } + watchfor = '"'; + } else if (buff[i] == '(') { + if (ptr == NULL) { + ptr = buff + i; + } + watchfor = ')'; + } else if (buff[i] == '{') { + if (ptr == NULL) { + ptr = buff + i; + } + watchfor = '}'; + } else if (buff[i] == '[') { + if (ptr == NULL) { + ptr = buff + i; + } + watchfor = ']'; + } else if (buff[i] == '<') { + if (ptr == NULL) { + ptr = buff + i; + } + watchfor = '>'; + } else if (buff[i] == '#') { + if (ptr != NULL) { + COPYPTR(); + state = ST_SEND; + } + watchfor = '\n'; + } else if (CharIsSpace(buff[i])) { + if (ptr != NULL) { + COPYPTR(); + state = ST_SEND; + } + } else if (ptr == NULL) { + ptr = buff + i; + } + } else if (buff[i] == watchfor) { + watchfor = 0; + } + } else if (state == ST_SEND) { + if (!Subparse(*keyhead, *keytail, *value, readfile)) { + goto teardown; + } + state = ST_KEYHEAD; + (*keyhead)[0] = 0; + (*keytail)[0] = 0; + (*value)[0] = 0; + i--; /* don't consume input */ + } else { + nvAssert(!"Invalid state!"); + } + } + + if (state == ST_SEND) { + if (!Subparse(*keyhead, *keytail, *value, readfile)) { + goto teardown; + } + } else if ((state != ST_KEYHEAD) || (ptr != NULL)) { + /* + * if state is KEYHEAD and ptr is NULL, then we've just got trailing + * whitespace or comments, which is valid syntax + */ + nvEvoLog(EVO_LOG_WARN, "Syntax error in configuration file: " + "trailing input after last key-value pair"); + goto teardown; + } + + ret = TRUE; + + /* fallthrough */ +teardown: + for (i = 0; i < 3; i++) { + nvFree(strs[i]); + } + return ret; +#undef COPYPTR +} + +#undef ST_KEYHEAD +#undef ST_KEYTAIL +#undef ST_VALUE +#undef ST_EQUALS +#undef ST_SEND diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia-modeset/src/nvkms-console-restore.c nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia-modeset/src/nvkms-console-restore.c --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia-modeset/src/nvkms-console-restore.c 2023-10-25 20:22:38.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia-modeset/src/nvkms-console-restore.c 2024-03-05 22:12:20.000000000 +0000 @@ -51,7 +51,9 @@ params.request.dpyId = pDpyEvo->id; params.request.modeIndex = index++; - params.request.modeValidation.overrides = NVKMS_MODE_VALIDATION_REQUIRE_BOOT_CLOCKS; + params.request.modeValidation.overrides = + NVKMS_MODE_VALIDATION_REQUIRE_BOOT_CLOCKS | + NVKMS_MODE_VALIDATION_MAX_ONE_HARDWARE_HEAD; nvValidateModeIndex(pDpyEvo, ¶ms.request, ¶ms.reply); @@ -114,74 +116,93 @@ static void FlipBaseToNull(NVDevEvoPtr pDevEvo) { - struct NvKmsFlipParams *pParams = nvCalloc(1, sizeof(*pParams)); - struct NvKmsFlipRequest *pRequest; + struct NvKmsFlipRequestOneHead *pFlipApiHead = NULL; + NvU32 numFlipApiHeads = 0, i; NvU32 sd; NVDispEvoPtr pDispEvo; NvBool ret = TRUE; - if (!pParams) { + /* First count the number of active heads. */ + FOR_ALL_EVO_DISPLAYS(pDispEvo, sd, pDevEvo) { + NvU32 apiHead; + for (apiHead = 0; apiHead < pDevEvo->numApiHeads; apiHead++) { + if (!nvApiHeadIsActive(pDispEvo, apiHead)) { + continue; + } + numFlipApiHeads++; + } + } + + if (numFlipApiHeads == 0) { + // If no heads require changes, there's nothing to do. + return; + } + + /* Allocate an array of head structures */ + pFlipApiHead = nvCalloc(numFlipApiHeads, sizeof(pFlipApiHead[0])); + + if (!pFlipApiHead) { nvEvoLogDevDebug(pDevEvo, EVO_LOG_WARN, "Failed to allocate flip parameters for console restore base flip " "to NULL"); return; } - pRequest = &pParams->request; - + i = 0; FOR_ALL_EVO_DISPLAYS(pDispEvo, sd, pDevEvo) { - struct NvKmsFlipRequestOneSubDevice *pRequestSd = - &pRequest->sd[sd]; - NvU32 head; - for (head = 0; head < pDevEvo->numHeads; head++) { - struct NvKmsFlipCommonParams *pRequestHead = - &pRequestSd->head[head]; + NvU32 apiHead; + for (apiHead = 0; apiHead < pDevEvo->numApiHeads; apiHead++) { + struct NvKmsFlipCommonParams *pRequestApiHead = NULL; NvU32 layer; - if (!nvHeadIsActive(pDispEvo, head)) { + if (!nvApiHeadIsActive(pDispEvo, apiHead)) { continue; } - pRequestSd->requestedHeadsBitMask |= NVBIT(head); + pFlipApiHead[i].sd = sd; + pFlipApiHead[i].head = apiHead; + pRequestApiHead = &pFlipApiHead[i].flip; + i++; + nvAssert(i <= numFlipApiHeads); - for (layer = 0; layer < pDevEvo->head[head].numLayers; layer++) { - pRequestHead->layer[layer].surface.specified = TRUE; + for (layer = 0; layer < pDevEvo->apiHead[apiHead].numLayers; layer++) { + pRequestApiHead->layer[layer].surface.specified = TRUE; // No need to specify sizeIn/sizeOut as we are flipping NULL surface. - pRequestHead->layer[layer].compositionParams.specified = TRUE; - pRequestHead->layer[layer].completionNotifier.specified = TRUE; - pRequestHead->layer[layer].syncObjects.specified = TRUE; + pRequestApiHead->layer[layer].compositionParams.specified = TRUE; + pRequestApiHead->layer[layer].completionNotifier.specified = TRUE; + pRequestApiHead->layer[layer].syncObjects.specified = TRUE; // Disable HDR - pRequestHead->tf.val = NVKMS_OUTPUT_TF_NONE; - pRequestHead->tf.specified = TRUE; - pRequestHead->layer[layer].hdr.enabled = FALSE; - pRequestHead->layer[layer].hdr.specified = TRUE; - pRequestHead->layer[layer].colorspace.val = + pRequestApiHead->tf.val = NVKMS_OUTPUT_TF_NONE; + pRequestApiHead->tf.specified = TRUE; + pRequestApiHead->layer[layer].hdr.enabled = FALSE; + pRequestApiHead->layer[layer].hdr.specified = TRUE; + pRequestApiHead->layer[layer].colorspace.val = NVKMS_INPUT_COLORSPACE_NONE; - pRequestHead->layer[layer].colorspace.specified = TRUE; + pRequestApiHead->layer[layer].colorspace.specified = TRUE; } - - pRequest->commit = TRUE; } } - // If no heads require changes, there's nothing to do. - if (pRequest->commit) { - ret = nvFlipEvo(pDevEvo, pDevEvo->pNvKmsOpenDev, pRequest, - &pParams->reply, FALSE /* skipUpdate */, - FALSE /* allowFlipLock */); - } - nvFree(pParams); + ret = nvFlipEvo(pDevEvo, pDevEvo->pNvKmsOpenDev, + pFlipApiHead, + numFlipApiHeads, + TRUE /* commit */, + FALSE /* allowVrr */, + NULL /* pReply */, + FALSE /* skipUpdate */, + FALSE /* allowFlipLock */); + nvFree(pFlipApiHead); if (!ret) { nvAssert(!"Console restore failed to flip base to NULL"); } FOR_ALL_EVO_DISPLAYS(pDispEvo, sd, pDevEvo) { - NvU32 head; - for (head = 0; head < pDevEvo->numHeads; head++) { + NvU32 apiHead; + for (apiHead = 0; apiHead < pDevEvo->numApiHeads; apiHead++) { NvBool stoppedBase; - ret = nvRMIdleBaseChannel(pDevEvo, head, sd, &stoppedBase); + ret = nvIdleBaseChannelOneApiHead(pDispEvo, apiHead, &stoppedBase); if (!ret) { nvAssert(!"Console restore failed to idle base"); } @@ -189,13 +210,55 @@ } } +/*! + * Return the mask of active api heads on this pDispEvo. + */ +static NvU32 GetActiveApiHeadMask(NVDispEvoPtr pDispEvo) +{ + NvU32 apiHead; + NvU32 apiHeadMask = 0; + + for (apiHead = 0; apiHead < NVKMS_MAX_HEADS_PER_DISP; apiHead++) { + if (nvApiHeadIsActive(pDispEvo, apiHead)) { + apiHeadMask |= 1 << apiHead; + } + } + + return apiHeadMask; +} + +static NvU32 PickApiHead(const NVDpyEvoRec *pDpyEvo, + const NvU32 availableApiHeadsMask) +{ + const NvU32 possibleApiHeads = availableApiHeadsMask & + nvDpyGetPossibleApiHeadsMask(pDpyEvo); + const NvU32 activeApiHeadsMask = + GetActiveApiHeadMask(pDpyEvo->pDispEvo); + + if (possibleApiHeads == 0) { + return NV_INVALID_HEAD; + } + + if ((pDpyEvo->apiHead != NV_INVALID_HEAD) && + ((NVBIT(pDpyEvo->apiHead) & possibleApiHeads) != 0x0)) { + return pDpyEvo->apiHead; + } + + if ((possibleApiHeads & ~activeApiHeadsMask) != 0x0) { + return BIT_IDX_32(LOWESTBIT(possibleApiHeads & + ~activeApiHeadsMask)); + } + + return BIT_IDX_32(LOWESTBIT(possibleApiHeads)); +} + static NvBool InitModeOneHeadRequest( NVDpyEvoRec *pDpyEvo, NVSurfaceEvoPtr pSurfaceEvo, const struct NvKmsMode *pOverrideMode, const struct NvKmsSize *pOverrideViewPortSizeIn, const struct NvKmsPoint *pOverrideViewPortPointIn, - const NvU32 head, + const NvU32 apiHead, struct NvKmsSetModeOneHeadRequest *pRequestHead) { @@ -218,7 +281,8 @@ pRequestHead->dpyIdList = nvAddDpyIdToEmptyDpyIdList(pDpyEvo->id); pRequestHead->modeValidationParams.overrides = - NVKMS_MODE_VALIDATION_REQUIRE_BOOT_CLOCKS; + NVKMS_MODE_VALIDATION_REQUIRE_BOOT_CLOCKS | + NVKMS_MODE_VALIDATION_MAX_ONE_HARDWARE_HEAD; if (pOverrideViewPortSizeIn != NULL) { pRequestHead->viewPortSizeIn = *pOverrideViewPortSizeIn; } else { @@ -242,7 +306,7 @@ pFlip->layer[NVKMS_MAIN_LAYER].sizeIn.val; /* Disable other layers except Main */ - for (layer = 0; layer < pDevEvo->head[head].numLayers; layer++) { + for (layer = 0; layer < pDevEvo->apiHead[apiHead].numLayers; layer++) { if (layer == NVKMS_MAIN_LAYER) { pFlip->layer[layer].csc.matrix = NVKMS_IDENTITY_CSC_MATRIX; @@ -272,24 +336,21 @@ NVSurfaceEvoPtr pSurfaceEvo, struct NvKmsSetModeParams *pParams, const NvU32 dispIndex, - NvU32 *pAvailableHeadsMask) + NvU32 *pAvailableApiHeadsMask) { NvBool ret = FALSE; - const NvU32 possibleHeads = *pAvailableHeadsMask & - pDpyEvo->pConnectorEvo->validHeadMask; + const NvU32 apiHead = PickApiHead(pDpyEvo, *pAvailableApiHeadsMask); - if (possibleHeads == 0 || pDpyEvo->isVrHmd) { + if ((apiHead == NV_INVALID_HEAD) || pDpyEvo->isVrHmd) { goto done; } - const NvU32 head = BIT_IDX_32(LOWESTBIT(possibleHeads)); - NVDispEvoRec *pDispEvo = pDpyEvo->pDispEvo; struct NvKmsSetModeRequest *pRequest = &pParams->request; struct NvKmsSetModeOneDispRequest *pRequestDisp = &pRequest->disp[dispIndex]; struct NvKmsSetModeOneHeadRequest *pRequestHead = - &pRequestDisp->head[head]; + &pRequestDisp->head[apiHead]; NVDevEvoRec *pDevEvo = pDispEvo->pDevEvo; @@ -298,7 +359,7 @@ NULL /* Use default Mode */, NULL /* Use default ViewPortSizeIn */, NULL /* Use default ViewPortPointIn */, - head, + apiHead, pRequestHead)) { goto done; } @@ -331,7 +392,7 @@ pRequestHead->viewPortOutSpecified = TRUE; } - *pAvailableHeadsMask &= ~NVBIT(head); + *pAvailableApiHeadsMask &= ~NVBIT(apiHead); ret = TRUE; @@ -492,7 +553,7 @@ struct NvKmsSetModeParams *pParams, const NvU32 dispIndex, NVDpyIdList tiledDisplayDpysList, - NvU32 *pAvailableHeadsMask) + NvU32 *pAvailableApiHeadsMask) { NVDevEvoRec *pDevEvo = pDispEvo->pDevEvo; /* @@ -516,16 +577,16 @@ struct NvKmsSetModeRequest *pRequest = &pParams->request; struct NvKmsSetModeOneDispRequest *pRequestDisp = &pRequest->disp[dispIndex]; - NvU32 firstClaimedHead = NV_INVALID_HEAD; - NvU32 claimedHeadMask = 0x0; + NvU32 firstClaimedApiHead = NV_INVALID_HEAD; + NvU32 claimedApiHeadMask = 0x0; NVDpyEvoRec *pDpyEvo; - NvU32 head; + NvU32 apiHead; /* * Return failure if not enough number of heads available to construct * modeset request for Tiled-Display. */ - if (nvPopCount32(*pAvailableHeadsMask) < + if (nvPopCount32(*pAvailableApiHeadsMask) < nvCountDpyIdsInDpyIdList(tiledDisplayDpysList)) { return FALSE; } @@ -546,20 +607,20 @@ .x = pDpyDisplayIdInfo->tile_location.x * viewPortSizeIn.width, .y = pDpyDisplayIdInfo->tile_location.y * viewPortSizeIn.height }; - const NvU32 possibleHeads = *pAvailableHeadsMask & - pDpyEvo->pConnectorEvo->validHeadMask & - ~claimedHeadMask; + const NvU32 localAvailableApiHeadsMask = + *pAvailableApiHeadsMask & ~claimedApiHeadMask; + const NvU32 apiHead = PickApiHead(pDpyEvo, + localAvailableApiHeadsMask); - if (possibleHeads == 0 || pDpyEvo->isVrHmd) { + if ((apiHead == NV_INVALID_HEAD) || pDpyEvo->isVrHmd) { goto failed; } - const NvU32 head = BIT_IDX_32(LOWESTBIT(possibleHeads)); struct NvKmsSetModeOneHeadRequest *pRequestHead = - &pRequestDisp->head[head]; + &pRequestDisp->head[apiHead]; struct NvKmsMode mode; - if (firstClaimedHead == NV_INVALID_HEAD) { + if (firstClaimedApiHead == NV_INVALID_HEAD) { /* * Find mode of native dimensions reported in Tiled-Display * information. @@ -572,20 +633,20 @@ goto failed; } - firstClaimedHead = head; + firstClaimedApiHead = apiHead; } else { /* All tiles should support same set of modes */ - mode = pRequestDisp->head[firstClaimedHead].mode; + mode = pRequestDisp->head[firstClaimedApiHead].mode; } - claimedHeadMask |= NVBIT(head); + claimedApiHeadMask |= NVBIT(apiHead); if (!InitModeOneHeadRequest(pDpyEvo, pSurfaceEvo, &mode, &viewPortSizeIn, &viewPortPointIn, - head, + apiHead, pRequestHead)) { goto failed; } @@ -601,19 +662,19 @@ FALSE /* doRasterLock */)) { goto failed; } - *pAvailableHeadsMask &= ~claimedHeadMask; + *pAvailableApiHeadsMask &= ~claimedApiHeadMask; return TRUE; failed: - for (head = 0; head < ARRAY_LEN(pRequestDisp->head); head++) { - if ((NVBIT(head) & claimedHeadMask) == 0x0) { + for (apiHead = 0; apiHead < ARRAY_LEN(pRequestDisp->head); apiHead++) { + if ((NVBIT(apiHead) & claimedApiHeadMask) == 0x0) { continue; } - nvkms_memset(&pRequestDisp->head[head], + nvkms_memset(&pRequestDisp->head[apiHead], 0, - sizeof(pRequestDisp->head[head])); + sizeof(pRequestDisp->head[apiHead])); } return FALSE; @@ -625,12 +686,15 @@ NVDispEvoPtr pDispEvo; FOR_ALL_EVO_DISPLAYS(pDispEvo, i, pDevEvo) { - NvU32 head; + NvU32 apiHead; - for (head = 0; head < pDevEvo->numHeads; head++) { - const NVDispHeadStateEvoRec *pHeadState = - &pDispEvo->headState[head]; - const NVConnectorEvoRec *pConnectorEvo = pHeadState->pConnectorEvo; + for (apiHead = 0; apiHead < pDevEvo->numApiHeads; apiHead++) { + const NVDispApiHeadStateEvoRec *pApiHeadState = + &pDispEvo->apiHeadState[apiHead]; + const NVDpyEvoRec *pDpyEvo = + nvGetOneArbitraryDpyEvo(pApiHeadState->activeDpys, pDispEvo); + const NVConnectorEvoRec *pConnectorEvo = (pDpyEvo != NULL) ? + pDpyEvo->pConnectorEvo : NULL; if ((pConnectorEvo != NULL) && nvConnectorUsesDPLib(pConnectorEvo)) { @@ -655,12 +719,14 @@ * If a framebuffer console surface was successfully imported from RM, then use * the core channel to set a mode that displays it. * - * Enables as many heads as possible in a clone configuration. In first pass - * for connected boot dpys and in second pass for other remaining dpys: + * This enables as many heads as possible in a clone configuration. + * In the first pass we select connected active dpys, in the second pass + * any other connected boot dpys, and in a third pass any other + * remaining connected dpys: * - * 1. Populate modeset request to enable given dpy. + * 1. Populate modeset request to enable the given dpy. * - * 2. Do modeset request validation, if fails then disable scaling. If + * 2. Do modeset request validation, if it fails then disable scaling. If * modeset request validation fails even after disabling scaling then do not * enable that dpy. * @@ -724,13 +790,17 @@ // Construct the request. // // To start with, try to enable as many connected dpys as possible, - // preferring boot displays first. + // preferring the connected active displays first. struct NvKmsSetModeRequest *pRequest = ¶ms->request; NvBool foundDpysConfigForConsoleRestore = FALSE; FOR_ALL_EVO_DISPLAYS(pDispEvo, dispIndex, pDevEvo) { - NvU32 availableHeadsMask = NVBIT(pDevEvo->numHeads) - 1; + NvU32 availableApiHeadsMask = NVBIT(pDevEvo->numApiHeads) - 1; NVDpyIdList connectedDpys = UpdateConnectedDpys(pDispEvo); + const NVDpyIdList activeDpys = nvActiveDpysOnDispEvo(pDispEvo); + const NVDpyIdList connectedActiveDpys = + nvIntersectDpyIdListAndDpyIdList(connectedDpys, + activeDpys); const NVDpyIdList connectedBootDpys = nvIntersectDpyIdListAndDpyIdList(connectedDpys, pDispEvo->bootDisplays); @@ -739,7 +809,7 @@ int pass; pRequest->requestedDispsBitMask |= NVBIT(dispIndex); - pRequestDisp->requestedHeadsBitMask = availableHeadsMask; + pRequestDisp->requestedHeadsBitMask = availableApiHeadsMask; // Only enable heads on the subdevice that actually contains the // console. @@ -749,19 +819,24 @@ NVDpyIdList handledDpysList = nvEmptyDpyIdList(); - for (pass = 0; pass < 2; pass++) { + for (pass = 0; pass < 3; pass++) { NVDpyIdList candidateDpys; NVDpyEvoPtr pDpyEvo; - if (availableHeadsMask == 0) { + if (availableApiHeadsMask == 0) { break; } if (pass == 0) { - candidateDpys = connectedBootDpys; - } else { + candidateDpys = connectedActiveDpys; + } else if (pass == 1) { + candidateDpys = nvDpyIdListMinusDpyIdList(connectedBootDpys, + connectedActiveDpys); + } else if (pass == 2) { candidateDpys = nvDpyIdListMinusDpyIdList(connectedDpys, connectedBootDpys); + candidateDpys = nvDpyIdListMinusDpyIdList(candidateDpys, + connectedActiveDpys); } FOR_ALL_EVO_DPYS(pDpyEvo, candidateDpys, pDispEvo) { @@ -773,7 +848,7 @@ &pDpyEvo->parsedEdid.info.ext_displayid : NULL; NvBool done = FALSE; - if (availableHeadsMask == 0) { + if (availableApiHeadsMask == 0) { break; } @@ -807,7 +882,7 @@ params, dispIndex, tiledDisplayInfo.detectedDpysList, - &availableHeadsMask); + &availableApiHeadsMask); isTiledDisplayEnable = done; } @@ -828,7 +903,7 @@ pSurfaceEvo, params, dispIndex, - &availableHeadsMask); + &availableApiHeadsMask); isTiledDisplayEnable = done && tiledDisplayInfo.isCapToScaleSingleTile; } @@ -875,7 +950,7 @@ /* If console restore failed then simply shut down all heads */ if (!ret) { - nvShutDownHeads(pDevEvo, NULL /* pTestFunc, shut down all heads */); + nvShutDownApiHeads(pDevEvo, NULL /* pTestFunc, shut down all heads */); } // If restoring the console from here succeeded, then skip triggering RM's diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia-modeset/src/nvkms-cursor.c nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia-modeset/src/nvkms-cursor.c --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia-modeset/src/nvkms-cursor.c 2023-10-25 20:22:38.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia-modeset/src/nvkms-cursor.c 2024-03-05 22:12:20.000000000 +0000 @@ -89,13 +89,13 @@ } static void -SetCursorImage(NVDispEvoPtr pDispEvo, - const NvU32 head, - NVSurfaceEvoRec *pSurfaceEvoNew, - const struct NvKmsCompositionParams *pCursorCompParams) +SetCursorImageOneHead(NVDispEvoPtr pDispEvo, + const NvU32 head, + NVSurfaceEvoRec *pSurfaceEvoNew, + const struct NvKmsCompositionParams *pCursorCompParams, + NVEvoUpdateState *pUpdateState) { NVDevEvoPtr pDevEvo = pDispEvo->pDevEvo; - NVEvoUpdateState updateState = { }; const NvU32 sd = pDispEvo->displayOwner; NvBool changed = FALSE; @@ -131,51 +131,79 @@ pDevEvo, head, pDevEvo->gpus[sd].headState[head].cursor.pSurfaceEvo, - &updateState, + pUpdateState, &pDevEvo->gpus[sd].headState[head].cursor.cursorCompParams); - nvEvoUpdateAndKickOff(pDispEvo, FALSE, &updateState, - TRUE /* releaseElv */); nvPopEvoSubDevMask(pDevEvo); } +} + +static void +SetCursorImage(NVDispEvoPtr pDispEvo, + const NvU32 apiHead, + NVSurfaceEvoRec *pSurfaceEvoNew, + const struct NvKmsCompositionParams *pCursorCompParams) +{ + NVDevEvoRec *pDevEvo = pDispEvo->pDevEvo; + const NVDispApiHeadStateEvoRec *pApiHeadState = + &pDispEvo->apiHeadState[apiHead]; + NvU32 head; + NVEvoUpdateState updateState = { }; + NvBool changed = FALSE; + + FOR_EACH_EVO_HW_HEAD_IN_MASK(pApiHeadState->hwHeadsMask, head) { + SetCursorImageOneHead(pDispEvo, + head, + pSurfaceEvoNew, + pCursorCompParams, + &updateState); + } - if (pSurfaceEvoNew) { - nvTriggerVrrUnstallSetCursorImage(pDispEvo, changed); + if (!nvIsUpdateStateEmpty(pDevEvo, &updateState)) { + nvEvoUpdateAndKickOff(pDispEvo, FALSE, &updateState, + TRUE /* releaseElv */); + changed = TRUE; } + + /* + * Unconditionally trigger an unstall: even if the cursor image or + * composition didn't change, clients setting the cursor image would expect + * a VRR unstall. Also, if the cursor changed from an image to no image + * (i.e., hiding the cursor), that should trigger a VRR unstall, too. + */ + nvTriggerVrrUnstallSetCursorImage(pDispEvo, changed); } static NvBool FlipCursorImage(NVDispEvoPtr pDispEvo, const struct NvKmsPerOpenDev *pOpenDevice, - NvU32 head, + NvU32 apiHead, const struct NvKmsSetCursorImageCommonParams *pImageParams) { const NvU32 sd = pDispEvo->displayOwner; NvBool ret; - struct NvKmsFlipParams *pFlipParams; - struct NvKmsFlipRequest *pFlipRequest; + struct NvKmsFlipRequestOneHead *pFlipHead = + nvCalloc(1, sizeof(*pFlipHead)); - pFlipParams = nvCalloc(1, sizeof(*pFlipParams)); - if (pFlipParams == NULL) { + if (pFlipHead == NULL) { return FALSE; } - pFlipRequest = &pFlipParams->request; - - pFlipRequest->sd[sd].head[head].cursor.image = *pImageParams; - pFlipRequest->sd[sd].head[head].cursor.imageSpecified = TRUE; - - pFlipRequest->sd[sd].requestedHeadsBitMask = NVBIT(head); - - pFlipRequest->commit = TRUE; + pFlipHead->sd = sd; + pFlipHead->head = apiHead; + pFlipHead->flip.cursor.image = *pImageParams; + pFlipHead->flip.cursor.imageSpecified = TRUE; ret = nvFlipEvo(pDispEvo->pDevEvo, pOpenDevice, - pFlipRequest, - &pFlipParams->reply, + pFlipHead, + 1 /* numFlipHeads */, + TRUE /* commit */, + FALSE /* allowVrr */, + NULL /* pReply */, FALSE /* skipUpdate */, FALSE /* allowFlipLock */); - nvFree(pFlipParams); + nvFree(pFlipHead); return ret; } @@ -184,7 +212,7 @@ NVDispEvoPtr pDispEvo, const struct NvKmsPerOpenDev *pOpenDevice, const NVEvoApiHandlesRec *pOpenDevSurfaceHandles, - NvU32 head, + NvU32 apiHead, const struct NvKmsSetCursorImageCommonParams *pParams) { NVDevEvoPtr pDevEvo = pDispEvo->pDevEvo; @@ -206,25 +234,32 @@ pDevEvo->capsBits, NV5070_CTRL_SYSTEM_CAPS_BUG_2052012_GLITCHY_MCLK_SWITCH)) { const NvU32 sd = pDispEvo->displayOwner; - - NVSurfaceEvoPtr pSurfaceEvoOld = - pDevEvo->gpus[sd].headState[head].cursor.pSurfaceEvo; - - if ((pSurfaceEvoOld != pSurfaceEvoNew) && - (pSurfaceEvoOld == NULL || pSurfaceEvoNew == NULL)) { - flipCursorImage = TRUE; + const NVDispApiHeadStateEvoRec *pApiHeadState = + &pDispEvo->apiHeadState[apiHead]; + NvU32 head; + + FOR_EACH_EVO_HW_HEAD_IN_MASK(pApiHeadState->hwHeadsMask, head) { + NVSurfaceEvoPtr pSurfaceEvoOld = + pDevEvo->gpus[sd].headState[head].cursor.pSurfaceEvo; + + if ((pSurfaceEvoOld != pSurfaceEvoNew) && + (pSurfaceEvoOld == NULL || pSurfaceEvoNew == NULL)) { + flipCursorImage = TRUE; + break; + } } } if (flipCursorImage) { return FlipCursorImage(pDispEvo, - pOpenDevice, head, pParams); + pOpenDevice, apiHead, pParams); } SetCursorImage(pDispEvo, - head, + apiHead, pSurfaceEvoNew, &pParams->cursorCompParams); + return TRUE; } @@ -244,19 +279,42 @@ } } -void nvEvoMoveCursor(NVDispEvoPtr pDispEvo, NvU32 head, - const struct NvKmsMoveCursorCommonParams *pParams) +void nvMoveCursor(NVDispEvoPtr pDispEvo, const NvU32 apiHead, + const struct NvKmsMoveCursorCommonParams *pParams) { NVDevEvoPtr pDevEvo = pDispEvo->pDevEvo; - const NvU32 sd = pDispEvo->displayOwner; + const NVDispApiHeadStateEvoRec *pApiHeadState = + &pDispEvo->apiHeadState[apiHead]; + NvU16 hwViewportInWidth; + NvU32 head, headCount; /* XXX NVKMS TODO: validate x,y against current viewport in? */ - pDevEvo->gpus[sd].headState[head].cursor.x = pParams->x; - pDevEvo->gpus[sd].headState[head].cursor.y = pParams->y; + nvAssert(apiHead != NV_INVALID_HEAD); + + headCount = 0; + FOR_EACH_EVO_HW_HEAD_IN_MASK(pApiHeadState->hwHeadsMask, head) { + const NVDispHeadStateEvoRec *pHeadState = &pDispEvo->headState[head]; + const NVHwModeTimingsEvo *pTimings = &pHeadState->timings; + const NvU32 sd = pDispEvo->displayOwner; - nvEvoMoveCursorInternal(pDispEvo, - head, pParams->x, pParams->y); + if (headCount == 0) { + hwViewportInWidth = pTimings->viewPort.in.width; + } else { + nvAssert(hwViewportInWidth == pTimings->viewPort.in.width); + } + + pDevEvo->gpus[sd].headState[head].cursor.x = + pParams->x - (hwViewportInWidth * pHeadState->tilePosition); + pDevEvo->gpus[sd].headState[head].cursor.y = pParams->y; + + nvEvoMoveCursorInternal(pDispEvo, + head, + pDevEvo->gpus[sd].headState[head].cursor.x, + pDevEvo->gpus[sd].headState[head].cursor.y); + + headCount++; + } } // Allocate and map cursor position PIO channels diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia-modeset/src/nvkms-difr.c nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia-modeset/src/nvkms-difr.c --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia-modeset/src/nvkms-difr.c 2023-10-25 20:22:39.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia-modeset/src/nvkms-difr.c 2024-03-05 22:12:20.000000000 +0000 @@ -145,13 +145,32 @@ NvU32 prefetchPass; } NVDIFRStateEvoRec; +/* + * Prefetch parameters for DMA copy. + */ +typedef struct { + NvUPtr surfGpuAddress; + size_t surfSizeBytes; + enum NvKmsSurfaceMemoryFormat surfFormat; + NvU32 surfPitchBytes; +} NVDIFRPrefetchParams; + static NvBool AllocDIFRPushChannel(NVDIFRStateEvoPtr pDifr); static void FreeDIFRPushChannel(NVDIFRStateEvoPtr pDifr); static NvBool AllocDIFRCopyEngine(NVDIFRStateEvoPtr pDifr); static void FreeDIFRCopyEngine(NVDIFRStateEvoPtr pDifr); + static NvU32 PrefetchSingleSurface(NVDIFRStateEvoPtr pDifr, - NVSurfaceEvoPtr pSurfaceEvo, + NVDIFRPrefetchParams *pParams, size_t *remainingCache); +static NvBool PrefetchHelperSurfaceEvo(NVDIFRStateEvoPtr pDifr, + size_t *cacheRemaining, + NVSurfaceEvoPtr pSurfaceEvo, + NvU32 *status); +static NvBool PrefetchHelperLutSurface(NVDIFRStateEvoPtr pDifr, + size_t *cacheRemaining, + NVLutSurfaceEvoPtr pLutSurface, + NvU32 *status); static NvBool SetDisabledState(NVDIFRStateEvoPtr pDifr, NvBool shouldDisable); @@ -247,15 +266,20 @@ NVDevEvoPtr pDevEvo = pDifr->pDevEvo; NVEvoSubDevPtr pSubDev; NVEvoSubDevHeadStatePtr pHeadState; - NVSurfaceEvoPtr pSurface; size_t cacheRemaining = l2CacheSize; NvU32 layer; NvU32 head; + NvU32 apiHead; NvU32 eye; + NvU32 i; NvU32 status; - /* If DIFR is disabled it's because we know we were or will be flipping. */ - if (pDifr->hwDisabled) { + /* + * If DIFR is disabled it's because we know we were or will be flipping, or + * if console is active then the scanout surfaces will get updated by the + * OS console driver without any knowledge of NVKMS. + */ + if (pDifr->hwDisabled || nvEvoIsConsoleActive(pDevEvo)) { return NV2080_CTRL_LPWR_DIFR_PREFETCH_FAIL_OS_FLIPS_ENABLED; } @@ -266,45 +290,73 @@ /* Get new prefetch pass counter for this iteration. */ pDifr->prefetchPass++; + /* + * Start by prefetching the cursor surface and image surfaces from + * present layers. + */ for (head = 0; head < pDevEvo->numHeads; head++) { - for (layer = 0; layer < pDevEvo->head[head].numLayers; layer++) { - for (eye = 0; eye < NVKMS_MAX_EYES; eye++) { - NvU32 prefetchStatus; + pHeadState = &pSubDev->headState[head]; - pHeadState = &pSubDev->headState[head]; - pSurface = pHeadState->layer[layer].pSurfaceEvo[eye]; + if (!PrefetchHelperSurfaceEvo(pDifr, + &cacheRemaining, + pHeadState->cursor.pSurfaceEvo, + &status)) { + goto out; + } - if (!pSurface) { - continue; - } + for (layer = 0; layer <= pDevEvo->head[head].numLayers; layer++) { + for (eye = 0; eye < NVKMS_MAX_EYES; eye++) { - if (pSurface->noDisplayCaching) { - status = - NV2080_CTRL_LPWR_DIFR_PREFETCH_FAIL_OS_FLIPS_ENABLED; - break; + if (!PrefetchHelperSurfaceEvo(pDifr, + &cacheRemaining, + pHeadState->layer[layer].pSurfaceEvo[eye], + &status)) { + goto out; } + } - /* - * If we see the same pSurface twice (UBB, multi-head X - * screens, etc) we only ever want to prefetch it once - * within a single nvDIFRPrefetchSurfaces() call. - */ - if (pSurface->difrLastPrefetchPass == pDifr->prefetchPass) { - continue; - } + /* + * Prefetch per-layer LUTs, if any, but skip null LUTs and + * duplicates already prefetched. + */ + if (!PrefetchHelperLutSurface(pDifr, + &cacheRemaining, + pHeadState->layer[layer].inputLut.pLutSurfaceEvo, + &status)) { + goto out; + } - pSurface->difrLastPrefetchPass = pDifr->prefetchPass; - prefetchStatus = PrefetchSingleSurface(pDevEvo->pDifrState, - pSurface, - &cacheRemaining); - if (prefetchStatus != NV2080_CTRL_LPWR_DIFR_PREFETCH_SUCCESS) { - status = prefetchStatus; - break; - } + if (!PrefetchHelperLutSurface(pDifr, + &cacheRemaining, + pHeadState->layer[layer].tmoLut.pLutSurfaceEvo, + &status)) { + goto out; + } + } + } + + /* + * Finally prefetch the known main LUTs. + */ + if (!PrefetchHelperLutSurface(pDifr, + &cacheRemaining, + pDevEvo->lut.defaultLut, + &status)) { + goto out; + } + + for (apiHead = 0; apiHead < pDevEvo->numApiHeads; apiHead++) { + for (i = 0; i < ARRAY_LEN(pDevEvo->lut.apiHead[apiHead].LUT); i++) { + if (!PrefetchHelperLutSurface(pDifr, + &cacheRemaining, + pDevEvo->lut.apiHead[apiHead].LUT[i], + &status)) { + goto out; } } } +out: return status; } @@ -429,7 +481,7 @@ } static NvU32 PrefetchSingleSurface(NVDIFRStateEvoPtr pDifr, - NVSurfaceEvoPtr pSurfaceEvo, + NVDIFRPrefetchParams *pParams, size_t *cacheRemaining) { NvPushChannelPtr p = &pDifr->prefetchPushChannel; @@ -437,12 +489,10 @@ NvGpuSemaphore *semaphore = (NvGpuSemaphore *) nvPushGetNotifierCpuAddress(p, 0, 0); const NvKmsSurfaceMemoryFormatInfo *finfo = - nvKmsGetSurfaceMemoryFormatInfo(pSurfaceEvo->format); + nvKmsGetSurfaceMemoryFormatInfo(pParams->surfFormat); NvU32 componentSizes; - NvU32 pitch; NvU32 line_length_in; NvU32 line_count; - size_t surfaceSize; NvU64 starttime; NvU64 endtime; @@ -487,37 +537,25 @@ /* * Compute some dimensional values to obtain correct blob size for - * prefetching. + * prefetching. Use the given pitch and calculate the number of lines + * needed to cover the whole memory region. */ - pitch = pSurfaceEvo->planes[0].pitch; - line_length_in = pSurfaceEvo->widthInPixels; - line_count = pSurfaceEvo->heightInPixels; - - if (pSurfaceEvo->layout == NvKmsSurfaceMemoryLayoutBlockLinear) { - pitch *= NVKMS_BLOCK_LINEAR_GOB_WIDTH; - } + nvAssert(pParams->surfPitchBytes % finfo->rgb.bytesPerPixel == 0); + line_length_in = pParams->surfPitchBytes / finfo->rgb.bytesPerPixel; - surfaceSize = pitch * line_count; + nvAssert(pParams->surfSizeBytes % pParams->surfPitchBytes == 0); + line_count = pParams->surfSizeBytes / pParams->surfPitchBytes; /* * Greedy strategy: assume all surfaces will fit in the supplied L2 size but * the first one that doesn't will cause the prefetch request to fail. If we * run out of cache then DIFR will disable itself until the next modeset. */ - if (*cacheRemaining < surfaceSize) { + if (*cacheRemaining < pParams->surfSizeBytes) { return NV2080_CTRL_LPWR_DIFR_PREFETCH_FAIL_INSUFFICIENT_L2_SIZE; } - /* - * TODO: we should probably round up to the nearest cacheline size or maybe - * up to pSurfaceEvo->planes[0].rmObjectSizeInBytes, if greater? - * - * Using the total size of the surface pixel data (in bytes) seems to work - * but surface allocations can be larger than that and I'm not sure if DIFR - * needs only surfaceSize bytes in the cache or if the h/w will end up - * reading some non-visible alignment/padding areas as well. - */ - *cacheRemaining -= surfaceSize; + *cacheRemaining -= pParams->surfSizeBytes; /* * Push buffer DMA copy and semaphore programming. @@ -534,18 +572,27 @@ nvPushImmedVal(p, NVA06F_SUBCHANNEL_COPY_ENGINE, NVA0B5_SET_REMAP_CONST_A, 0); nvPushMethod(p, NVA06F_SUBCHANNEL_COPY_ENGINE, NVA0B5_OFFSET_IN_UPPER, 2); - nvPushSetMethodDataU64(p, pSurfaceEvo->gpuAddress); + nvPushSetMethodDataU64(p, pParams->surfGpuAddress); nvPushMethod(p, NVA06F_SUBCHANNEL_COPY_ENGINE, NVA0B5_OFFSET_OUT_UPPER, 2); - nvPushSetMethodDataU64(p, pSurfaceEvo->gpuAddress); + nvPushSetMethodDataU64(p, pParams->surfGpuAddress); + + /* + * We don't expect phenomally large pitches but the .mfs for DMA copy + * defines PitchIn/PitchOut to be of signed 32-bit type for all + * architectures so assert that the value will be what h/w understands. + */ + nvAssert(pParams->surfPitchBytes <= NV_S32_MAX); + nvPushMethod(p, NVA06F_SUBCHANNEL_COPY_ENGINE, NVA0B5_PITCH_IN, 1); - nvPushSetMethodData(p, pitch); + nvPushSetMethodData(p, pParams->surfPitchBytes); nvPushMethod(p, NVA06F_SUBCHANNEL_COPY_ENGINE, NVA0B5_PITCH_OUT, 1); - nvPushSetMethodData(p, pitch); + nvPushSetMethodData(p, pParams->surfPitchBytes); nvPushMethod(p, NVA06F_SUBCHANNEL_COPY_ENGINE, NVA0B5_LINE_LENGTH_IN, 1); nvPushSetMethodData(p, line_length_in); nvPushMethod(p, NVA06F_SUBCHANNEL_COPY_ENGINE, NVA0B5_LINE_COUNT, 1); nvPushSetMethodData(p, line_count); + nvAssert(pParams->surfPitchBytes * line_count == pParams->surfSizeBytes); nvPushMethod(p, NVA06F_SUBCHANNEL_COPY_ENGINE, NVA0B5_LAUNCH_DMA, 1); nvPushSetMethodData @@ -605,6 +652,88 @@ return NV2080_CTRL_LPWR_DIFR_PREFETCH_FAIL_CE_HW_ERROR; } +static NvBool PrefetchHelperSurfaceEvo(NVDIFRStateEvoPtr pDifr, + size_t *cacheRemaining, + NVSurfaceEvoPtr pSurfaceEvo, + NvU32 *status) +{ + NVDIFRPrefetchParams params; + + nvAssert(*status == NV2080_CTRL_LPWR_DIFR_PREFETCH_SUCCESS); + + if (!pSurfaceEvo) { + return TRUE; + } + + if (pSurfaceEvo->noDisplayCaching) { + *status = NV2080_CTRL_LPWR_DIFR_PREFETCH_FAIL_OS_FLIPS_ENABLED; + return FALSE; + } + + /* + * If we see the same SurfaceEvo twice (UBB, multi-head X screens, etc) + * we only ever want to prefetch it once within a single + * nvDIFRPrefetchSurfaces() call. + */ + if (pSurfaceEvo->difrLastPrefetchPass == pDifr->prefetchPass) { + return TRUE; + } + + /* + * Update pass counter even if we fail later: we want to try each + * surface only once. + */ + pSurfaceEvo->difrLastPrefetchPass = pDifr->prefetchPass; + + /* Collect copy parameters and do the prefetch. */ + params.surfGpuAddress = pSurfaceEvo->gpuAddress; + params.surfSizeBytes = pSurfaceEvo->planes[0].rmObjectSizeInBytes; + params.surfPitchBytes = pSurfaceEvo->planes[0].pitch; + params.surfFormat = pSurfaceEvo->format; + + if (pSurfaceEvo->layout == NvKmsSurfaceMemoryLayoutBlockLinear) { + params.surfPitchBytes *= NVKMS_BLOCK_LINEAR_GOB_WIDTH; + } + + *status = PrefetchSingleSurface(pDifr, ¶ms, cacheRemaining); + + return *status == NV2080_CTRL_LPWR_DIFR_PREFETCH_SUCCESS; +} + +static NvBool PrefetchHelperLutSurface(NVDIFRStateEvoPtr pDifr, + size_t *cacheRemaining, + NVLutSurfaceEvoPtr pLutSurface, + NvU32 *status) +{ + NVDIFRPrefetchParams params; + + nvAssert(*status == NV2080_CTRL_LPWR_DIFR_PREFETCH_SUCCESS); + + if (!pLutSurface) { + return TRUE; + } + + /* + * LUTs are often shared so we only want to prefetch (or consider) each + * LUT at most once during the prefetch process. + */ + if (pLutSurface->difrLastPrefetchPass == pDifr->prefetchPass) { + return TRUE; + } + + pLutSurface->difrLastPrefetchPass = pDifr->prefetchPass; + + /* Collect copy parameters and do the prefetch. */ + params.surfGpuAddress = (NvUPtr)pLutSurface->gpuAddress; + params.surfSizeBytes = pLutSurface->size; + params.surfPitchBytes = pLutSurface->size; + params.surfFormat = NvKmsSurfaceMemoryFormatI8; + + *status = PrefetchSingleSurface(pDifr, ¶ms, cacheRemaining); + + return *status == NV2080_CTRL_LPWR_DIFR_PREFETCH_SUCCESS; +} + /* * Set DIFR disabled state in H/W. Return true if state was changed and it * was successfully signalled downstream. diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia-modeset/src/nvkms-dpy-override.c nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia-modeset/src/nvkms-dpy-override.c --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia-modeset/src/nvkms-dpy-override.c 1970-01-01 00:00:00.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia-modeset/src/nvkms-dpy-override.c 2024-03-05 22:12:20.000000000 +0000 @@ -0,0 +1,264 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + + +#include "nvkms-utils.h" +#include "nvkms-dpy-override.h" + +#include "nv_list.h" + +static NVListRec dpyOverrideList = NV_LIST_INIT(&dpyOverrideList); + +#define FOR_ALL_DPY_OVERRIDES(_pDpyOverride) \ + nvListForEachEntry(_pDpyOverride, &dpyOverrideList, entry) +#define FOR_ALL_DPY_OVERRIDES_SAFE(_pDpyOverride, _next) \ + nvListForEachEntry_safe(_pDpyOverride, _next, &dpyOverrideList, entry) + +#define DPY_OVERRIDE_MATCHES(_pDpyOverride, _gpuId, _name) \ + ((_pDpyOverride->gpuId == _gpuId) && \ + !nvkms_strcmp(_pDpyOverride->name, _name)) + +static NvBool DpyOverrideReadEdid(NVDpyOverrideRec *dpy, + const char *buffer, + size_t size) +{ + if ((dpy->edid.length != size) || (dpy->edid.buffer == NULL)) { + NvU8 *newbuf = nvRealloc(dpy->edid.buffer, size); + if (newbuf == NULL) { + return FALSE; + } + dpy->edid.buffer = newbuf; + dpy->edid.length = size; + } + + nvkms_memcpy(dpy->edid.buffer, buffer, size); + return TRUE; +} + + +/* + * Creates a display override on the given GPU for the given display name. + * If the override already exists it will be overwritten. + * + * \param[in] gpuId The ID of the GPU on which to create the display + * override, as returned in nvkms_enumerate_gpus() + * \param[in] name The name of the display to override in + * PROTOCOL-Index format, e.g. HDMI-0. + * \param[in] edid A buffer containing EDID data for the override. + * \param[in] edidSize The size of the edid buffer. + * + * \return A pointer to the created or edited NVDpyOverrideRec, or NULL if + * creation failed. + */ +NVDpyOverrideRec *nvCreateDpyOverride(NvU32 gpuId, + const char *name, + NvBool connected, + const char *edid, + size_t edidSize) +{ + NVDpyOverridePtr pDpyOverride; + size_t namelen, cpsz; + NvBool found = FALSE; + + /* if such a display override already exists, let it be changed */ + FOR_ALL_DPY_OVERRIDES(pDpyOverride) { + if (DPY_OVERRIDE_MATCHES(pDpyOverride, gpuId, name)) { + + found = TRUE; + break; + } + } + + /* if such a display override doesn't exist, create a new one */ + if (!found) { + pDpyOverride = nvCalloc(1, sizeof(*pDpyOverride)); + if (pDpyOverride == NULL) { + nvEvoLog(EVO_LOG_WARN, "Failed allocating data for display override"); + return NULL; + } + + nvListAdd(&pDpyOverride->entry, &dpyOverrideList); + + namelen = nvkms_strlen(name); + cpsz = namelen > NVKMS_DPY_NAME_SIZE - 1 ? NVKMS_DPY_NAME_SIZE - 1 + : namelen; + + nvkms_memcpy(pDpyOverride->name, name, cpsz); + pDpyOverride->gpuId = gpuId; + } + + pDpyOverride->connected = connected; + if (connected && !DpyOverrideReadEdid(pDpyOverride, edid, edidSize)) { + nvEvoLog(EVO_LOG_WARN, "Failed reading EDID"); + nvListDel(&pDpyOverride->entry); + nvFree(pDpyOverride); + return NULL; + } + + return pDpyOverride; +} + +/* + * Deletes a display override on the given GPU for the given display name. + * + * \param[in] gpuId The ID of the GPU on which to delete the display + * override, as returned in nvkms_enumerate_gpus() + * \param[in] name The name of the display whose override to delete in + * PROTOCOL-Index format, e.g. HDMI-0. + */ +void nvDeleteDpyOverride(NvU32 gpuId, const char *name) +{ + NVDpyOverridePtr pDpyOverride; + + /* If such a display override already exists, delete it */ + FOR_ALL_DPY_OVERRIDES(pDpyOverride) { + if (DPY_OVERRIDE_MATCHES(pDpyOverride, gpuId, name)) { + + nvListDel(&pDpyOverride->entry); + nvFree(pDpyOverride); + return; /* This makes using nvListForEachEntry safe. */ + } + } +} + +/* + * Logs a list of currently active override names to pInfoStr for a given + * GPU. + * + * \param[in] gpuId The ID of the GPU whose overrides to print, as + * returned in nvkms_enumerate_gpus() + * \param[in] pInfoStr A pointer to the NVEvoInfoString to log to. + */ +void nvLogDpyOverrides(NvU32 gpuId, NVEvoInfoStringPtr pInfoStr) +{ + NVDpyOverridePtr pDpyOverride; + FOR_ALL_DPY_OVERRIDES(pDpyOverride) { + if (pDpyOverride->gpuId == gpuId) { + nvEvoLogInfoString(pInfoStr, "%s", pDpyOverride->name); + } + } +} + +/* + * Checks if there is a matching, valid, and enabled NVDpyOverrideRec for the + * pDpyEvo in the global display override list and returns it if it is found. + * O(N) in length of display override list + * + * \param[in] pDpyEvo The display to check for an override. + * + * \return The NVDpyOverrideRec override for the pDpyEvo, or NULL if it isn't + * found. + */ +NVDpyOverridePtr nvDpyEvoGetOverride(const NVDpyEvoRec *pDpyEvo) +{ + NVDevEvoPtr pDevEvo; + NVDispEvoPtr pDispEvo; + NVSubDeviceEvoPtr pSubDevice; + NVDpyOverridePtr it; + + if (pDpyEvo == NULL) { + return NULL; + } + + /* + * Don't override DP MST displays, because there could be multiple attached + * to the single connector, which would result in the number of displays + * this override creates being dependent on the number of plugged in + * displays, which seems incorrect for this feature + */ + if (nvDpyEvoIsDPMST(pDpyEvo)) { + return NULL; + } + pDispEvo = pDpyEvo->pDispEvo; + pDevEvo = pDispEvo->pDevEvo; + + pSubDevice = pDevEvo->pSubDevices[pDispEvo->displayOwner]; + + FOR_ALL_DPY_OVERRIDES(it) { + /* Ensure valid and enabled override */ + if ((it->edid.length == 0) || (it->edid.buffer == NULL)) { + continue; + } + + /* + * Both NVDpyOverrideRec.gpuId and NVSubDeviceEvoRec.gpuId ultimately + * derive from nvRmApiControl(NV2080_CTRL_CMD_GPU_GET_ID), so we can + * use them to match GPUs. Additionally, NVConnectorEvo.name is of the + * format TYPE-N, e.g. HDMI-0, but pDpyEvo.name may have additional + * qualifiers (e.g., an existing EDID-derived name). + */ + if (DPY_OVERRIDE_MATCHES(it, pSubDevice->gpuId, pDpyEvo->pConnectorEvo->name)) { + + nvEvoLogDebug(EVO_LOG_INFO, "NVDpyOverrideRec found: %s\n", + it->name); + return it; + } + } + + return NULL; +} + +/* + * Reads the EDID data from a given NVDpyOverrideRec into the buffer buff. + * Does not write to the buffer if the operation fails. + * + * \param[in] pDpyOverride The override from which to read the EDID data. + * \param[out] buff A pointer to a buffer into which to read + * the override's EDID data. + * \param[in] len The length of the buffer. + * + * \return The number of bytes written into the buffer, or 0 if the operation + * failed. + */ +size_t nvReadDpyOverrideEdid(const NVDpyOverrideRec *pDpyOverride, + NvU8 *buff, size_t len) +{ + if ((pDpyOverride == NULL) || + (buff == NULL) || + (pDpyOverride->edid.length == 0) || + (pDpyOverride->edid.length > len)) { + return 0; + } + + nvkms_memcpy(buff, pDpyOverride->edid.buffer, + pDpyOverride->edid.length); + return pDpyOverride->edid.length; +} + +/* + * Delete all display overrides. This should only ever be called during shutdown + * of NVKMS or to cleanup when display override initialization fails. + */ +void nvClearDpyOverrides(void) +{ + NVDpyOverridePtr pDpyOverride, tmp; + FOR_ALL_DPY_OVERRIDES_SAFE(pDpyOverride, tmp) { + nvListDel(&pDpyOverride->entry); + if (pDpyOverride->edid.buffer != NULL) { + nvFree(pDpyOverride->edid.buffer); + } + nvFree(pDpyOverride); + } + + nvAssert(nvListIsEmpty(&dpyOverrideList)); +} diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia-modeset/src/nvkms-dpy.c nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia-modeset/src/nvkms-dpy.c --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia-modeset/src/nvkms-dpy.c 2023-10-25 20:22:39.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia-modeset/src/nvkms-dpy.c 2024-03-05 22:12:20.000000000 +0000 @@ -26,6 +26,7 @@ #include "nvkms-evo.h" #include "nvkms-dpy.h" +#include "nvkms-dpy-override.h" #include "nvkms-hdmi.h" #include "nvkms-rm.h" #include "nvkms-rmapi.h" @@ -653,7 +654,7 @@ if (pDevEvo->gpus != NULL) { NVEvoSorCaps *sorCaps = pDevEvo->gpus[displayOwner].capabilities.sor; - NvU32 orIndex = nvEvoConnectorGetPrimaryOr(pConnectorEvo); + NvU32 orIndex = pConnectorEvo->or.primary; if (NV0073_CTRL_SYSTEM_GET_CAP(pDevEvo->commonCapsBits, NV0073_CTRL_SYSTEM_CAPS_CROSS_BAR_SUPPORTED)) { @@ -681,7 +682,10 @@ * those driving heads, we don't need to exclude RM from * selecting any SOR, so an sorExcludeMask of 0 is appropriate. */ - if (nvAssignSOREvo(pConnectorEvo, 0) && + if (nvAssignSOREvo(pDispEvo, + nvDpyIdToNvU32(pConnectorEvo->displayId), + FALSE /* b2Heads1Or */, + 0 /* sorExcludeMask */) && nvHdmiFrlAssessLink(pDpyEvo)) { /* * Note that although we "assessed" the link above, the @@ -1379,6 +1383,12 @@ { NVT_TYPE_CUST_AUTO, "Customized Auto Timings" }, { NVT_TYPE_CUST_MANUAL, "Customized Manual Timings" }, { NVT_TYPE_CVT_RB_2,"Reduced Blanking Coordinated Video Timings, v2" }, + { NVT_TYPE_DMT_RB_2, "Display Monitor Timings, V2" }, + { NVT_TYPE_DISPLAYID_7, "DisplayID Type 7 Timings" }, + { NVT_TYPE_DISPLAYID_8, "DisplayID Type 8 Timings" }, + { NVT_TYPE_DISPLAYID_9, "DisplayID Type 9 Timings" }, + { NVT_TYPE_DISPLAYID_10, "DisplayID Type 10 Timings" }, + { NVT_TYPE_CVT_RB_3, "Reduced Blanking Coordinated Video Timings, v3" }, }; /* @@ -1425,6 +1435,16 @@ case NVT_TYPE_CUST_AUTO: case NVT_TYPE_CUST_MANUAL: case NVT_TYPE_CVT_RB_2: + case NVT_TYPE_DMT_RB_2: + case NVT_TYPE_DISPLAYID_7: + case NVT_TYPE_DISPLAYID_8: + case NVT_TYPE_DISPLAYID_9: + case NVT_TYPE_DISPLAYID_10: + case NVT_TYPE_CVT_RB_3: + /* + * XXX temporarily disable the warning so that additional + * NVT_TYPEs_ can be added to nvtiming.h. Bug 3849339. + */ default: break; } @@ -2415,7 +2435,6 @@ { const NVDispHeadStateEvoRec *pHeadState = &pDispEvo->headState[head]; - const NVHwModeTimingsEvo *pTimings = &pHeadState->timings; NV0073_CTRL_SPECIFIC_SET_OD_PACKET_PARAMS params = { 0 }; NVDevEvoPtr pDevEvo = pDispEvo->pDevEvo; NvU32 ret; @@ -2448,11 +2467,11 @@ sdp->db.pixEncoding = SDP_VSC_PIX_ENC_YCBCR420; sdp->db.colorimetryFormat = SDP_VSC_COLOR_FMT_YCBCR_COLORIMETRY_ITU_R_BT709; - switch (pTimings->pixelDepth) { - case NVKMS_PIXEL_DEPTH_30_444: + switch (pAttributesSet->colorBpc) { + case NV_KMS_DPY_ATTRIBUTE_CURRENT_COLOR_BPC_10: sdp->db.bitDepth = SDP_VSC_BIT_DEPTH_YCBCR_10BPC; break; - case NVKMS_PIXEL_DEPTH_24_444: + case NV_KMS_DPY_ATTRIBUTE_CURRENT_COLOR_BPC_8: sdp->db.bitDepth = SDP_VSC_BIT_DEPTH_YCBCR_8BPC; break; default: @@ -2547,10 +2566,13 @@ NvBool nvDpyRequiresDualLinkEvo(const NVDpyEvoRec *pDpyEvo, const NVHwModeTimingsEvo *pTimings) { + const NvU32 pixelClock = (pTimings->yuv420Mode == NV_YUV420_MODE_HW) ? + (pTimings->pixelClock / 2) : pTimings->pixelClock; + // Dual link HDMI is not possible. nvAssert(!(nvDpyIsHdmiEvo(pDpyEvo) && - (pTimings->pixelClock > pDpyEvo->maxSingleLinkPixelClockKHz))); - return (pTimings->pixelClock > pDpyEvo->maxSingleLinkPixelClockKHz); + (pixelClock > pDpyEvo->maxSingleLinkPixelClockKHz))); + return (pixelClock > pDpyEvo->maxSingleLinkPixelClockKHz); } /*! @@ -2702,14 +2724,49 @@ struct NvKmsQueryDpyDynamicDataParams *pParams) { NVDispEvoPtr pDispEvo = pDpyEvo->pDispEvo; - const struct NvKmsQueryDpyDynamicDataRequest *pRequest = &pParams->request; + struct NvKmsQueryDpyDynamicDataRequest *pRequest = &pParams->request; struct NvKmsQueryDpyDynamicDataReply *pReply = &pParams->reply; NVConnectorEvoPtr pConnectorEvo = pDpyEvo->pConnectorEvo; NVDpyIdList connectedList; NVDpyIdList oneDpyIdList = nvAddDpyIdToEmptyDpyIdList(pDpyEvo->id); + NVDpyOverridePtr pDpyOverride = nvDpyEvoGetOverride(pDpyEvo); nvkms_memset(pReply, 0, sizeof(*pReply)); + if (pDpyOverride != NULL) { + if (pDpyOverride->connected && !pRequest->forceDisconnected) { + /* + * If display is overridden as connected, treat the request as if it + * had both forceConnected and overrideEdid set, unless the request + * had forceDisconnected set. + * + * If the request already had an EDID override, honor that EDID instead + * of the display override EDID. + */ + NvBool old = pRequest->forceConnected; + pRequest->forceConnected = TRUE; + + if (!pRequest->overrideEdid) { + size_t len = nvReadDpyOverrideEdid(pDpyOverride, + pRequest->edid.buffer, + ARRAY_LEN(pRequest->edid.buffer)); + + if (len != 0) { + pRequest->overrideEdid = TRUE; + pRequest->edid.bufferSize = len; + } else { + pRequest->forceConnected = old; + } + } + } else if (!pDpyOverride->connected && !pRequest->forceConnected) { + /* + * If display is overriden as disconnected, treat the request as if it + * had forceDisconnected set, unless the request had forceConnected set. + */ + pRequest->forceDisconnected = TRUE; + } + } + /* * Check for the connection state of the dpy. * @@ -2844,6 +2901,7 @@ newAttributes.dithering.mode = NV_KMS_DPY_ATTRIBUTE_CURRENT_DITHERING_MODE_NONE; newAttributes.digitalSignal = nvGetDefaultDpyAttributeDigitalSignalValue(pDpyEvo->pConnectorEvo); + newAttributes.numberOfHardwareHeadsUsed = 0; } if (newAttributes.colorSpace != @@ -2902,18 +2960,194 @@ newAttributes.digitalSignal); } + if (newAttributes.numberOfHardwareHeadsUsed != + pDpyEvo->currentAttributes.numberOfHardwareHeadsUsed) { + nvSendDpyAttributeChangedEventEvo( + pDpyEvo, + NV_KMS_DPY_ATTRIBUTE_NUMBER_OF_HARDWARE_HEADS_USED, + newAttributes.numberOfHardwareHeadsUsed); + } + pDpyEvo->currentAttributes = newAttributes; } // Returns TRUE if this display is capable of Adaptive-Sync NvBool nvDpyIsAdaptiveSync(const NVDpyEvoRec *pDpyEvo) { - return FALSE; + return ((pDpyEvo->vrr.type == + NVKMS_DPY_VRR_TYPE_ADAPTIVE_SYNC_DEFAULTLISTED) || + (pDpyEvo->vrr.type == + NVKMS_DPY_VRR_TYPE_ADAPTIVE_SYNC_NON_DEFAULTLISTED)); } // Returns TRUE if this display is in the Adaptive-Sync defaultlist -NvBool nvDpyIsAdaptiveSyncDefaultlisted(const NVParsedEdidEvoRec *pParsedEdid) +NvBool nvDpyIsAdaptiveSyncDefaultlisted(const NVDpyEvoRec *pDpyEvo) { - return FALSE; + NV0073_CTRL_SPECIFIC_DEFAULT_ADAPTIVESYNC_DISPLAY_PARAMS params = { }; + NVDispEvoPtr pDispEvo = pDpyEvo->pDispEvo; + NVDevEvoPtr pDevEvo = pDispEvo->pDevEvo; + NvU32 ret; + + if (!pDpyEvo->parsedEdid.valid) { + return FALSE; + } + + params.manufacturerID = pDpyEvo->parsedEdid.info.manuf_id; + params.productID = pDpyEvo->parsedEdid.info.product_id; + + ret = nvRmApiControl(nvEvoGlobal.clientHandle, + pDevEvo->displayCommonHandle, + NV0073_CTRL_CMD_SPECIFIC_DEFAULT_ADAPTIVESYNC_DISPLAY, + ¶ms, sizeof(params)); + + if (ret != NVOS_STATUS_SUCCESS) { + nvEvoLogDisp(pDispEvo, EVO_LOG_ERROR, + "Failed to query default adaptivesync listing for %s", pDpyEvo->name); + return FALSE; + } + + return params.bDefaultAdaptivesync; } +static enum NvKmsDpyAttributeColorBpcValue GetYuv422MaxBpc( + const NVDpyEvoRec *pDpyEvo) +{ + const NVT_EDID_CEA861_INFO *p861Info = + &pDpyEvo->parsedEdid.info.ext861; + + nvAssert(nvDpyIsHdmiEvo(pDpyEvo) || + nvConnectorUsesDPLib(pDpyEvo->pConnectorEvo)); + + if (!pDpyEvo->parsedEdid.valid || + !pDpyEvo->parsedEdid.info.input.isDigital) { + return NV_KMS_DPY_ATTRIBUTE_CURRENT_COLOR_BPC_UNKNOWN; + } + + if (pDpyEvo->parsedEdid.info.version >= NVT_EDID_VER_1_4) { + if (pDpyEvo->parsedEdid.info.u.feature_ver_1_4_digital.support_ycrcb_422) { + if (pDpyEvo->parsedEdid.info.input.u.digital.bpc >= 10) { + return NV_KMS_DPY_ATTRIBUTE_CURRENT_COLOR_BPC_10; + } else if (pDpyEvo->parsedEdid.info.input.u.digital.bpc >= 8) { + return NV_KMS_DPY_ATTRIBUTE_CURRENT_COLOR_BPC_8; + } + } + } else { + nvAssert(!nvConnectorUsesDPLib(pDpyEvo->pConnectorEvo)); + + if (p861Info->revision >= NVT_CEA861_REV_A && + !!(p861Info->basic_caps & NVT_CEA861_CAP_YCbCr_422)) { + return NV_KMS_DPY_ATTRIBUTE_CURRENT_COLOR_BPC_10; + } + } + + return NV_KMS_DPY_ATTRIBUTE_CURRENT_COLOR_BPC_UNKNOWN; +} + +NVColorFormatInfoRec nvGetColorFormatInfo(const NVDpyEvoRec *pDpyEvo) +{ + const NVConnectorEvoRec *pConnectorEvo = + pDpyEvo->pConnectorEvo; + NVColorFormatInfoRec colorFormatsInfo = { }; + + if (pConnectorEvo->legacyType == + NV0073_CTRL_SPECIFIC_DISPLAY_TYPE_CRT) { + + colorFormatsInfo.rgb444.maxBpc = + NV_KMS_DPY_ATTRIBUTE_CURRENT_COLOR_BPC_10; + } else if (pConnectorEvo->legacyType == + NV0073_CTRL_SPECIFIC_DISPLAY_TYPE_DFP) { + + if (pConnectorEvo->signalFormat == + NVKMS_CONNECTOR_SIGNAL_FORMAT_DSI) { + + if (pDpyEvo->parsedEdid.valid) { + switch (pDpyEvo->parsedEdid.info.input.u.digital.bpc) { + case 10: + colorFormatsInfo.rgb444.maxBpc = + NV_KMS_DPY_ATTRIBUTE_CURRENT_COLOR_BPC_10; + break; + case 6: + colorFormatsInfo.rgb444.maxBpc = + NV_KMS_DPY_ATTRIBUTE_CURRENT_COLOR_BPC_6; + break; + default: + nvAssert(!"Unsupported bpc for DSI"); + // fall through + case 8: + colorFormatsInfo.rgb444.maxBpc = + NV_KMS_DPY_ATTRIBUTE_CURRENT_COLOR_BPC_8; + break; + } + } else { + colorFormatsInfo.rgb444.maxBpc = + NV_KMS_DPY_ATTRIBUTE_CURRENT_COLOR_BPC_8; + } + } else if (nvConnectorUsesDPLib(pDpyEvo->pConnectorEvo)) { + + if (pDpyEvo->parsedEdid.valid && + pDpyEvo->parsedEdid.info.input.isDigital && + pDpyEvo->parsedEdid.info.version >= NVT_EDID_VER_1_4) { + if (pDpyEvo->parsedEdid.info.input.u.digital.bpc >= 10) { + colorFormatsInfo.rgb444.maxBpc = + NV_KMS_DPY_ATTRIBUTE_CURRENT_COLOR_BPC_10; + } else if (pDpyEvo->parsedEdid.info.input.u.digital.bpc < 8) { + colorFormatsInfo.rgb444.maxBpc = + NV_KMS_DPY_ATTRIBUTE_CURRENT_COLOR_BPC_6; + } else { + colorFormatsInfo.rgb444.maxBpc = + NV_KMS_DPY_ATTRIBUTE_CURRENT_COLOR_BPC_8; + colorFormatsInfo.yuv444.maxBpc = + NV_KMS_DPY_ATTRIBUTE_CURRENT_COLOR_BPC_8; + } + + colorFormatsInfo.yuv422.maxBpc = GetYuv422MaxBpc(pDpyEvo); + } else { + colorFormatsInfo.rgb444.maxBpc = + NV_KMS_DPY_ATTRIBUTE_CURRENT_COLOR_BPC_8; + } + } else { + + colorFormatsInfo.rgb444.maxBpc = + NV_KMS_DPY_ATTRIBUTE_CURRENT_COLOR_BPC_8; + if (nvDpyIsHdmiEvo(pDpyEvo)) { + colorFormatsInfo.yuv444.maxBpc = + NV_KMS_DPY_ATTRIBUTE_CURRENT_COLOR_BPC_8; + colorFormatsInfo.yuv422.maxBpc = + GetYuv422MaxBpc(pDpyEvo); + } + } + } + + return colorFormatsInfo; +} + +NvU32 nvDpyGetPossibleApiHeadsMask(const NVDpyEvoRec *pDpyEvo) +{ + NvU32 possibleApiHeadMask = 0x0; + NvU32 possibleNumLayers = NVKMS_MAX_LAYERS_PER_HEAD; + const NVDevEvoRec *pDevEvo = pDpyEvo->pDispEvo->pDevEvo; + + /* + * DSI supports only the hardware head-0 assigment, and the + * dp-serializer dpys are bound to the specific hardware head; + * the modeset client can be allowed to choose only those + * api-heads to drive these dpys which has the number of layers + * less than or equal to the number of layers supported by the + * bound hardware heads. + */ + if (pDpyEvo->pConnectorEvo->signalFormat == + NVKMS_CONNECTOR_SIGNAL_FORMAT_DSI) { + possibleNumLayers = pDevEvo->head[0].numLayers; + } else if (nvConnectorIsDPSerializer(pDpyEvo->pConnectorEvo)) { + const NvU32 boundHead = pDpyEvo->dp.serializerStreamIndex; + possibleNumLayers = pDevEvo->head[boundHead].numLayers; + } + + for (NvU32 apiHead = 0; apiHead < pDevEvo->numApiHeads; apiHead++) { + if (pDevEvo->apiHead[apiHead].numLayers <= possibleNumLayers) { + possibleApiHeadMask |= NVBIT(apiHead); + } + } + + return possibleApiHeadMask; +} diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia-modeset/src/nvkms-evo.c nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia-modeset/src/nvkms-evo.c --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia-modeset/src/nvkms-evo.c 2023-10-25 20:22:39.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia-modeset/src/nvkms-evo.c 2024-03-05 22:12:21.000000000 +0000 @@ -25,6 +25,7 @@ #include "nvkms-evo-states.h" #include "dp/nvdp-connector.h" +#include "dp/nvdp-device.h" #include "nvkms-console-restore.h" #include "nvkms-rm.h" #include "nvkms-dpy.h" @@ -34,6 +35,7 @@ #include "nvkms-modepool.h" #include "nvkms-evo.h" #include "nvkms-flip.h" +#include "nvkms-hw-flip.h" #include "nvkms-dma.h" #include "nvkms-framelock.h" #include "nvkms-utils.h" @@ -79,13 +81,29 @@ /* * This struct is used to describe a single set of GPUs to lock together by * GetRasterLockTopologies(). - * It is initialized to pDispEvoOrder[i] == NULL, and when filled in NULL is - * used as a terminator. */ -typedef struct { +typedef struct _NVEvoRasterLockTopology { + NvU32 numDisps; NVDispEvoPtr pDispEvoOrder[NVKMS_MAX_SUBDEVICES]; } RasterLockTopology; +/* + * These are used hold additional state for each DispEvo during building of + * topologies. + */ +typedef struct +{ + NVDispEvoPtr pDispEvo; + NvU32 gpuId; + RasterLockTopology *topo; +} DispEntry; + +typedef struct +{ + /* Array of DispEvos and their assigned topologies. */ + NvU32 numDisps; + DispEntry disps[NVKMS_MAX_SUBDEVICES]; +} DispEvoList; static void EvoSetViewportPointIn(NVDispEvoPtr pDispEvo, NvU32 head, NvU16 x, NvU16 y, @@ -93,8 +111,9 @@ static void GetRasterLockPin(NVDispEvoPtr pDispEvo0, NvU32 head0, NVDispEvoPtr pDispEvo1, NvU32 head1, NVEvoLockPin *serverPin, NVEvoLockPin *clientPin); -static NvBool EvoWaitForLock(NVDevEvoPtr pDevEvo, - NvU32 sd, NvU32 head, NvU32 type); +static NvBool EvoWaitForLock(const NVDevEvoRec *pDevEvo, const NvU32 sd, + const NvU32 head, const NvU32 type, + NvU64 *pStartTime); static void EvoUpdateHeadParams(const NVDispEvoRec *pDispEvo, NvU32 head, NVEvoUpdateState *updateState); @@ -111,7 +130,7 @@ static void UpdateEvoLockState(void); static void ScheduleLutUpdate(NVDispEvoRec *pDispEvo, - const NvU32 head, const NvU32 data, + const NvU32 apiHead, const NvU32 data, const NvU64 usec); NVEvoGlobal nvEvoGlobal = { @@ -122,6 +141,8 @@ .debugMemoryAllocationList = NV_LIST_INIT(&nvEvoGlobal.debugMemoryAllocationList), #endif /* DEBUG */ + .globalTopologies = NULL, + .numGlobalTopos = 0 }; /* @@ -247,10 +268,19 @@ const NVDispHeadStateEvoRec *pHeadState = &pDispEvo->headState[head]; const NVHwModeTimingsEvo *pTimings = &pHeadState->timings; NVDevEvoPtr pDevEvo = pDispEvo->pDevEvo; - const NvU32 orIndex = nvEvoConnectorGetPrimaryOr(pConnectorEvo); + NvU32 orIndex; - nvAssert(orIndex != NV_INVALID_OR); - nvAssert(pConnectorEvo->or.ownerHeadMask[orIndex] & NVBIT(head)); + for (orIndex = 0; + orIndex < ARRAY_LEN(pConnectorEvo->or.ownerHeadMask); orIndex++) { + if ((pConnectorEvo->or.ownerHeadMask[orIndex] & NVBIT(head)) != 0x0) { + break; + } + } + + if (orIndex >= ARRAY_LEN(pConnectorEvo->or.ownerHeadMask)) { + nvAssert(!"Not found attached OR"); + return; + } pConnectorEvo->or.ownerHeadMask[orIndex] &= ~NVBIT(head); @@ -279,8 +309,35 @@ pModesetUpdateState->connectorIds); } +static +NvU32 GetSorIndexToAttachConnector(const NVConnectorEvoRec *pConnectorEvo, + const NvBool isPrimaryHead) +{ + NvU32 orIndex = NV_INVALID_OR; + + nvAssert(isPrimaryHead || + (pConnectorEvo->or.type == NV0073_CTRL_SPECIFIC_OR_TYPE_SOR)); + + if (isPrimaryHead || + (pConnectorEvo->or.type != NV0073_CTRL_SPECIFIC_OR_TYPE_SOR)) { + orIndex = pConnectorEvo->or.primary; + } else { + NvU32 i; + + FOR_EACH_INDEX_IN_MASK(32, i, pConnectorEvo->or.secondaryMask) { + if (pConnectorEvo->or.ownerHeadMask[i] == 0x0) { + orIndex = i; + break; + } + } FOR_EACH_INDEX_IN_MASK_END; + } + + return orIndex; +} + void nvEvoAttachConnector(NVConnectorEvoRec *pConnectorEvo, const NvU32 head, + const NvU32 isPrimaryHead, NVDPLibModesetStatePtr pDpLibModesetState, NVEvoModesetUpdateState *pModesetUpdateState) { @@ -289,7 +346,8 @@ const NVDispHeadStateEvoRec *pHeadState = &pDispEvo->headState[head]; const NVHwModeTimingsEvo *pTimings = &pHeadState->timings; NVDevEvoPtr pDevEvo = pDispEvo->pDevEvo; - const NvU32 orIndex = nvEvoConnectorGetPrimaryOr(pConnectorEvo); + NvU32 orIndex = + GetSorIndexToAttachConnector(pConnectorEvo, isPrimaryHead); NvU32 i; nvAssert(orIndex != NV_INVALID_OR); @@ -676,6 +734,9 @@ return; } + nvEvoLogInfoString(pInfoString, + "Adjusting Mode Timings for Quadro Sync Compatibility"); + ret = nvRmApiControl(nvEvoGlobal.clientHandle, pDispEvo->pFrameLockEvo->device, NV30F1_CTRL_CMD_GSYNC_GET_OPTIMIZED_TIMING, @@ -686,12 +747,13 @@ nvAssert(!"Failed to convert to Quadro Sync safe timing"); /* do not apply the timings returned by RM if the call failed */ return; + } else if (!gsyncOptTimingParams.bOptimized) { + nvEvoLogInfoString(pInfoString, " Timings Unchanged."); + return; } nvConstructNvModeTimingsFromHwModeTimings(pTimings, &modeTimings); - nvEvoLogInfoString(pInfoString, - "Adjusting Mode Timings for Quadro Sync Compatibility"); nvEvoLogInfoString(pInfoString, " Old Timings:"); nvEvoLogModeValidationModeTimings(pInfoString, &modeTimings); @@ -782,6 +844,15 @@ #endif } +void nvEvoDisableHwYUV420Packer(const NVDispEvoRec *pDispEvo, + const NvU32 head, + NVEvoUpdateState *pUpdateState) +{ + NVDevEvoPtr pDevEvo = pDispEvo->pDevEvo; + pDevEvo->gpus[pDispEvo->displayOwner].headControl[head].hwYuv420 = FALSE; + EvoUpdateHeadParams(pDispEvo, head, pUpdateState); +} + /* * Send the raster timings for the pDpyEvo to EVO. */ @@ -792,6 +863,8 @@ NVDevEvoPtr pDevEvo = pDispEvo->pDevEvo; const NVDispHeadStateEvoRec *pHeadState = &pDispEvo->headState[head]; const NVHwModeTimingsEvo *pTimings = &pHeadState->timings; + const NVDscInfoEvoRec *pDscInfo = &pHeadState->dscInfo; + const enum nvKmsPixelDepth pixelDepth = pHeadState->pixelDepth; NVEvoColorRec overscanColor; nvPushEvoSubDevMaskDisp(pDispEvo); @@ -799,7 +872,8 @@ NV_YUV420_MODE_SW)); pDevEvo->hal->SetRasterParams(pDevEvo, head, - pTimings, &overscanColor, updateState); + pTimings, pHeadState->tilePosition, + pDscInfo, &overscanColor, updateState); // Set the head parameters pDevEvo->gpus[pDispEvo->displayOwner].headControl[head].interlaced = @@ -815,15 +889,14 @@ * the HDMI library. */ nvAssert(!((pTimings->yuv420Mode == NV_YUV420_MODE_HW) && - (pTimings->dpDsc.enable || - pTimings->hdmiFrlConfig.dscInfo.bEnableDSC))); + (pDscInfo->type != NV_DSC_INFO_EVO_TYPE_DISABLED))); pDevEvo->gpus[pDispEvo->displayOwner].headControl[head].hwYuv420 = (pTimings->yuv420Mode == NV_YUV420_MODE_HW); EvoUpdateHeadParams(pDispEvo, head, updateState); - pDevEvo->hal->SetDscParams(pDispEvo, head, pTimings); + pDevEvo->hal->SetDscParams(pDispEvo, head, pDscInfo, pixelDepth); nvPopEvoSubDevMask(pDevEvo); } @@ -835,11 +908,11 @@ * This involves incrementing *numTopologies, reallocating the topos array, and * initializing the new entry. */ -static RasterLockTopology *growTopologies(RasterLockTopology *topos, +static RasterLockTopology *GrowTopologies(RasterLockTopology *topos, unsigned int *numTopologies) { RasterLockTopology *newTopos, *topo; - unsigned int i, numTopos; + unsigned int numTopos; numTopos = *numTopologies; @@ -847,26 +920,290 @@ newTopos = nvRealloc(topos, numTopos * sizeof(RasterLockTopology)); if (!newTopos) { nvFree(topos); + *numTopologies = 0; return NULL; } topo = &newTopos[numTopos - 1]; - - for (i = 0; i < NVKMS_MAX_SUBDEVICES; i++) { - topo->pDispEvoOrder[i] = NULL; - } + topo->numDisps = 0; *numTopologies = numTopos; return newTopos; -} /* growTopologies() */ +} /* GrowTopologies() */ + +static RasterLockTopology *CopyAndAppendTopology(RasterLockTopology *topos, + unsigned int *numTopos, + const RasterLockTopology *source) +{ + RasterLockTopology *dest; + + topos = GrowTopologies(topos, numTopos); + if (topos) { + dest = &topos[*numTopos - 1]; + nvkms_memcpy(dest, source, sizeof(RasterLockTopology)); + } + + return topos; +} + +static void AddDispEvoIntoTopology(RasterLockTopology *topo, NVDispEvoPtr pDispEvo) +{ + NvU32 i; + + /* + * The extent of a topology is the largest number of GPUs that can be + * linked together. + */ + nvAssert(topo->numDisps < NVKMS_MAX_SUBDEVICES); + + /* Caller should keep track of not adding duplicate entries. */ + for (i = 0; i < topo->numDisps; i++) { + nvAssert(topo->pDispEvoOrder[i] != pDispEvo); + } + + /* Add to the end of the array. */ + topo->pDispEvoOrder[topo->numDisps] = pDispEvo; + topo->numDisps++; +} + +static const RasterLockTopology *FindTopologyForDispEvo( + const RasterLockTopology *topos, + unsigned int numTopologies, + const NVDispEvoPtr pDispEvo) +{ + const RasterLockTopology *topo; + NvU32 i; + + for (topo = topos; topo < topos + numTopologies; topo++) { + for (i = 0; i < topo->numDisps; i++) { + if (topo->pDispEvoOrder[i] == pDispEvo) { + return topo; + } + } + } + + return NULL; +} + +static DispEntry *DispEvoListFindDispByGpuId (DispEvoList *list, NvU32 gpuId) +{ + NvU32 i; + + for (i = 0; i < list->numDisps; i++) { + if (list->disps[i].gpuId == gpuId) { + return &list->disps[i]; + } + } + + return NULL; +} + +static void DispEvoListInit(DispEvoList *list) +{ + list->numDisps = 0; +} + +static void DispEvoListAppend(DispEvoList *list, NVDispEvoPtr pDispEvo) +{ + nvAssert(DispEvoListFindDispByGpuId( + list, nvGpuIdOfDispEvo(pDispEvo)) == NULL); + + nvAssert(list->numDisps < ARRAY_LEN(list->disps)); + list->disps[list->numDisps].pDispEvo = pDispEvo; + list->disps[list->numDisps].gpuId = nvGpuIdOfDispEvo(pDispEvo); + list->disps[list->numDisps].topo = NULL; + list->numDisps++; +} + +/* + * Helper function to look up, for a gpuId, the list of connected GPUs in + * NV0000_CTRL_GPU_GET_VIDEO_LINKS_PARAMS. + */ +static NV0000_CTRL_GPU_VIDEO_LINKS *FindLinksForGpuId( + NV0000_CTRL_GPU_GET_VIDEO_LINKS_PARAMS *vidLinksParams, + NvU32 gpuId) +{ + NvU32 i; + + for (i = 0; i < NV0000_CTRL_GPU_MAX_ATTACHED_GPUS; i++) { + if (vidLinksParams->links[i].gpuId == NV0000_CTRL_GPU_INVALID_ID) { + break; + } + + if (vidLinksParams->links[i].gpuId == gpuId) { + return &vidLinksParams->links[i]; + } + } + + return NULL; +} + +static void BuildTopologyFromVideoLinks(DispEvoList *list, + RasterLockTopology *topo, + NvU32 gpuId, + NV0000_CTRL_GPU_GET_VIDEO_LINKS_PARAMS *vidLinksParams) +{ + DispEntry *dispEntry; + NV0000_CTRL_GPU_VIDEO_LINKS *links; + NvU32 i; + + /* Find the correct DispEntry for the gpuId. If we can't find one the + * gpuId must be pointing to a DevEvo that was not listed in our + * DevEvoList: ignore these links at this point. */ + dispEntry = DispEvoListFindDispByGpuId(list, gpuId); + if (!dispEntry) { + return; + } + + /* + * Unless we've seen this gpuId already add into current topology and + * try to discover bridged GPUs. + */ + if (!dispEntry->topo) { + /* Assign in the current topology. */ + AddDispEvoIntoTopology(topo, dispEntry->pDispEvo); + dispEntry->topo = topo; + + /* First, get the links for this gpuId. */ + links = FindLinksForGpuId(vidLinksParams, gpuId); + + /* Recurse into connected GPUs. */ + if (links) { + for (i = 0; i < NV0000_CTRL_GPU_MAX_VIDEO_LINKS; i++) { + if (links->connectedGpuIds[i] == NV0000_CTRL_GPU_INVALID_ID) { + break; + } + + BuildTopologyFromVideoLinks(list, + topo, + links->connectedGpuIds[i], + vidLinksParams); + } + } + } +} + +/* + * Stateless (RM SLI/client SLI agnostic) discovery of bridged GPUs: build + * topologies for all non-RM SLI devices based on the found GPU links. + * + * This function and BuildTopologyFromVideoLinks() implement a simple + * algorithm that puts clusters of bridged GPUs into distinct topologies. + * Here's an outline of how we basically generate the final topologies: + * + * 1. Create a DispEvoList array to hold topology state for all the DispEvo + * objects in the system. + * + * 2. Query RM for an array of video links for each GPU. + * + * 3. As long as the DispEvoList contains DispEvos of the given pDevEvo + * without a topology, find the first occurrence of such, create a new + * topology, and populate it by recursively adding the DispEvo and all + * its connected DispEvos into the new topology. + * + * 4. Once all known DispEvos are assigned the result will be a list of + * global RasterLockTopologies, each of which hosts DispEvos that are + * connected together. + * + * The result of this function should be cached once and later used to + * cheaply look up the appropriate, immutable topology for a DispEvo. + * + */ +static RasterLockTopology *GetGpuTopologyStateless(unsigned int *numTopologies) +{ + RasterLockTopology *topos = NULL; + RasterLockTopology *topo; + DispEvoList evoList; + NVDevEvoPtr pCurDev; + NVDispEvoPtr pCurDisp; + NV0000_CTRL_GPU_GET_VIDEO_LINKS_PARAMS *vidLinksParams; + NvU32 sd; + NvU32 i; + + DispEvoListInit(&evoList); + + /* + * First create an array of DispEntries to hold some state for all the + * DispEvos in the system. + */ + FOR_ALL_EVO_DEVS(pCurDev) { + /* + * Only include non RM SLI devices so as to not clash with multi-GPU + * RM SLI devices. + */ + if (pCurDev->numSubDevices == 1) { + FOR_ALL_EVO_DISPLAYS(pCurDisp, sd, pCurDev) { + DispEvoListAppend(&evoList, pCurDisp); + } + } + } + + /* + * Ask RM about the currently known video links. + */ + vidLinksParams = nvCalloc(1, sizeof(*vidLinksParams)); + if (!vidLinksParams) { + return NULL; + } + + if (nvRmApiControl(nvEvoGlobal.clientHandle, + nvEvoGlobal.clientHandle, + NV0000_CTRL_CMD_GPU_GET_VIDEO_LINKS, + vidLinksParams, + sizeof(*vidLinksParams)) == NVOS_STATUS_SUCCESS) { + + for (i = 0; i < evoList.numDisps; i++) { + /* + * Create a new topology starting from the first DispEvo not yet + * assigned into a topology, and all GPUs possibly reachable + * from it through bridges. + * + * TODO: Consider if we should only ever start a new topology + * with a GPU that has only one connection and not two. Then the + * topology's pDispEvoOrder would always start from a "leaf" GPU + * of a linkage graph. But will the GPU links always be linear + * and non-branching? NV0000_CTRL_GPU_GET_VIDEO_LINKS_PARAMS + * makes it possible to represent GPUs with any number of links. + * Either FinishModesetOneTopology() must be able to handle that + * (in which case this is not a concern) or we must be able to + * trust that only 0-2 links will be reported per GPU. + */ + if (evoList.disps[i].topo) { + continue; + } + + topos = GrowTopologies(topos, numTopologies); + if (!topos) { + nvFree(vidLinksParams); + return NULL; + } + + topo = &topos[*numTopologies - 1]; + + BuildTopologyFromVideoLinks(&evoList, + topo, + evoList.disps[i].gpuId, + vidLinksParams); + } + + nvFree(vidLinksParams); + nvAssert(*numTopologies > 0); + return topos; + } + + nvFree(vidLinksParams); + nvFree(topos); + return NULL; +} /* * GetRasterLockTopologies() - Determine which GPUs to consider for locking (or * unlocking) displays. This is one of the following: * 1. SLI video bridge order, if SLI is enabled; - * 2. A single GPU, + * 2. GPUs linked through rasterlock pins, no SLI (like in clientSLI); + * 3. A single GPU, * in that order. * * Note that we still go through the same codepaths for the last degenerate @@ -899,7 +1236,7 @@ if (params.ConnectionCount > 0) { RasterLockTopology *topo; - topos = growTopologies(topos, numTopologies); + topos = GrowTopologies(topos, numTopologies); if (!topos) { return NULL; @@ -925,28 +1262,64 @@ nvAssert(pDevEvo->pDispEvo[sd] != NULL); /* SLI Mosaic. */ - topo->pDispEvoOrder[i] = pDevEvo->pDispEvo[sd]; + AddDispEvoIntoTopology(topo, pDevEvo->pDispEvo[sd]); } } - } else { - /* Single GPU or bridgeless SLI */ - NVDispEvoPtr pDispEvo; - unsigned int sd; + if (*numTopologies > 0) { + return topos; + } + } + + /* + * Client SLI: Create a RasterLockTopology from pDevEvo's only DispEvo + * and other DispEvos potentially bridged to that. + */ - FOR_ALL_EVO_DISPLAYS(pDispEvo, sd, pDevEvo) { + if (pDevEvo->numSubDevices == 1) { + /* Get-or-create cached rasterlock topology for this device. */ + if (!nvEvoGlobal.globalTopologies) { + nvEvoGlobal.globalTopologies = + GetGpuTopologyStateless(&nvEvoGlobal.numGlobalTopos); + } - RasterLockTopology *topo; - topos = growTopologies(topos, numTopologies); + /* Look for a cached topo containing this device's DispEvo. */ + if (nvEvoGlobal.globalTopologies && nvEvoGlobal.numGlobalTopos > 0) { + const RasterLockTopology *foundTopo = + FindTopologyForDispEvo(nvEvoGlobal.globalTopologies, + nvEvoGlobal.numGlobalTopos, + pDevEvo->pDispEvo[0]); - if (!topos) { - return NULL; + /* Make a copy of it and add to 'topos'. */ + if (foundTopo) { + topos = CopyAndAppendTopology(topos, numTopologies, foundTopo); } + } - topo = &topos[*numTopologies - 1]; + if (*numTopologies > 0) { + return topos; + } + } + + /* + * Single GPU or bridgeless SLI. We create a topology for each + * individual DispEvo. + */ - topo->pDispEvoOrder[0] = pDispEvo; + NVDispEvoPtr pDispEvo; + unsigned int sd; + + FOR_ALL_EVO_DISPLAYS(pDispEvo, sd, pDevEvo) { + RasterLockTopology *topo; + topos = GrowTopologies(topos, numTopologies); + + if (!topos) { + return NULL; } + + topo = &topos[*numTopologies - 1]; + + AddDispEvoIntoTopology(topo, pDispEvo); } return topos; @@ -1054,17 +1427,19 @@ } for (topo = topos; topo < topos + numTopos; topo++) { - int maxDisps = 0, i; - - for (i = 0; i < NVKMS_MAX_SUBDEVICES && topo->pDispEvoOrder[i]; i++) { - maxDisps = i; - } + int i; - for (i = maxDisps; i >= 0; i--) { + for (i = (int)topo->numDisps - 1; i >= 0; i--) { NVDispEvoPtr pDispEvo = topo->pDispEvoOrder[i]; NVDevEvoPtr pDevEvo = pDispEvo->pDevEvo; NvU32 sd = pDispEvo->displayOwner; - NVEvoSubDevPtr pEvoSubDev = &pDevEvo->gpus[sd]; + NVEvoSubDevPtr pEvoSubDev; + + if (pDevEvo->gpus == NULL) { + continue; + } + + pEvoSubDev = &pDevEvo->gpus[sd]; /* Initialize the assembly state */ SyncEvoLockState(); @@ -1249,9 +1624,59 @@ pDevEvo->sli.bridge.powered = enable; } +void nvEvoLockStateSetMergeMode(NVDispEvoPtr pDispEvo) +{ + NVDevEvoPtr pDevEvo = pDispEvo->pDevEvo; + NVEvoSubDevPtr pEvoSubDev = &pDevEvo->gpus[pDispEvo->displayOwner]; + NvU32 activeHeads[NVKMS_MAX_HEADS_PER_DISP + 1]; + NvU32 mergeModeHeads[NVKMS_MAX_HEADS_PER_DISP + 1]; + NvU32 numMergeModeHeads = 0; + NvU32 numActiveHeads = 0; + NvBool needUpdate = FALSE; + + for (NvU32 head = 0; head < NVKMS_MAX_HEADS_PER_DISP; head++) { + if (nvHeadIsActive(pDispEvo, head)) { + if (pDispEvo->headState[head].mergeMode != + NV_EVO_MERGE_MODE_DISABLED) { + mergeModeHeads[numMergeModeHeads++] = head; + } + activeHeads[numActiveHeads++] = head; + } + } + mergeModeHeads[numMergeModeHeads] = NV_INVALID_HEAD; + activeHeads[numActiveHeads] = NV_INVALID_HEAD; + + SyncEvoLockState(); + + if (pEvoSubDev->scanLockState(pDispEvo, pEvoSubDev, + NV_EVO_DISABLE_MERGE_MODE, NULL)) { + pEvoSubDev->scanLockState(pDispEvo, pEvoSubDev, + NV_EVO_DISABLE_MERGE_MODE, activeHeads); + needUpdate = TRUE; + } + + if (numMergeModeHeads > 0) { + nvAssert(pDevEvo->hal->caps.supportsMergeMode); + if (pEvoSubDev->scanLockState(pDispEvo, + pEvoSubDev, + NV_EVO_ENABLE_MERGE_MODE, + mergeModeHeads)) { + needUpdate = TRUE; + } else { + nvEvoLogDispDebug(pDispEvo, EVO_LOG_ERROR, + "Failed to enable lock state merge mode"); + } + } + + if (needUpdate) { + UpdateEvoLockState(); + } +} + /* * FinishModesetOneTopology() - Set up raster lock between GPUs, if applicable, - * for one RasterLockTopology. Called in a loop from nvFinishModesetEvo(). + * unless disabled via kernel module parameter, for one RasterLockTopology. + * Called in a loop from nvFinishModesetEvo(). */ static void FinishModesetOneTopology(RasterLockTopology *topo) @@ -1265,12 +1690,22 @@ NvBool flipLockPossible = TRUE; unsigned int i, j; NvU8 allowFlipLockGroup = 0; + NVDevEvoPtr pDevEvoFlipLockGroup = NULL; + NvBool mergeModeInUse = FALSE; + + if (!nvkms_opportunistic_display_sync()) { + /* If opportunistic display sync is disabled, do not attempt rasterlock. */ + return; + } /* - * First, look for devices with VRR enabled. If we find any, go into the - * special VRR framelock mode and don't try to rasterlock any other heads. + * First, look for devices with VRR enabled. If we find any, go into the + * special VRR framelock mode. + * + * If we find devices with VRR or merge mode enabled, don't try to + * rasterlock any other heads. */ - for (i = 0; i < NVKMS_MAX_SUBDEVICES && pDispEvoOrder[i]; i++) { + for (i = 0; i < topo->numDisps; i++) { NVDispEvoPtr pDispEvo = pDispEvoOrder[i]; NvU32 sd = pDispEvo->displayOwner; NVDevEvoPtr pDevEvo = pDispEvo->pDevEvo; @@ -1278,7 +1713,20 @@ unsigned int numVrrHeads = 0; NvU32 head; - if (!pDevEvo->gpus || !pDevEvo->vrr.enabled) { + if (!pDevEvo->gpus) { + continue; + } + + for (head = 0; head < NVKMS_MAX_HEADS_PER_DISP; head++) { + if (nvHeadIsActive(pDispEvo, head)) { + if (pDispEvo->headState[head].mergeMode != + NV_EVO_MERGE_MODE_DISABLED) { + mergeModeInUse = TRUE; + } + } + } + + if (!pDevEvo->vrr.enabled) { continue; } @@ -1298,7 +1746,7 @@ } } - if (vrrInUse) { + if (vrrInUse || mergeModeInUse) { return; } @@ -1309,7 +1757,7 @@ * use. For now, only attempt locking if all heads on the device have * compatible timings and consecutive in the video bridge order. */ - for (i = 0; i < NVKMS_MAX_SUBDEVICES && pDispEvoOrder[i]; i++) { + for (i = 0; i < topo->numDisps; i++) { NVDispEvoPtr pDispEvo = pDispEvoOrder[i]; NVDevEvoPtr pDevEvo = pDispEvo->pDevEvo; NvU32 head; @@ -1349,10 +1797,16 @@ /* * Only flip lock if all of the heads are in the same * allowFlipLockGroup. + * + * Also, for now, only allow fliplocking if all heads are on + * GPUs with the same pDevEvo (i.e., single GPU or RM-linked + * SLI). */ if (allowFlipLockGroup == 0) { allowFlipLockGroup = pHeadState->allowFlipLockGroup; - } else if (allowFlipLockGroup != pHeadState->allowFlipLockGroup) { + pDevEvoFlipLockGroup = pDevEvo; + } else if (allowFlipLockGroup != pHeadState->allowFlipLockGroup || + pDevEvoFlipLockGroup != pDevEvo) { flipLockPossible = FALSE; } @@ -1381,7 +1835,7 @@ * Finally, actually set up locking: go through the video bridge order * setting it up. */ - for (i = 0; i < NVKMS_MAX_SUBDEVICES && pDispEvoOrder[i]; i++) { + for (i = 0; i < topo->numDisps; i++) { NVDispEvoPtr pDispEvo = pDispEvoOrder[i]; NvU32 sd = pDispEvo->displayOwner; NVDevEvoPtr pDevEvo = pDispEvo->pDevEvo; @@ -1542,6 +1996,7 @@ for (j = 0; j < usedHeads; j++) { NvU32 tmpHead = head[j]; + NvU64 startTime = 0; NVEvoLockPin pin = nvEvoGetPinForSignal(pDispEvo, &pDevEvo->gpus[sd], @@ -1549,7 +2004,8 @@ /* Wait for the raster lock to sync in.. */ if (pin == NV_EVO_LOCK_PIN_ERROR || - !EvoWaitForLock(pDevEvo, sd, tmpHead, EVO_RASTER_LOCK)) { + !EvoWaitForLock(pDevEvo, sd, tmpHead, EVO_RASTER_LOCK, + &startTime)) { flipLockPossible = FALSE; break; } @@ -1584,8 +2040,10 @@ * flips in the base channel. */ for (j = 0; j < usedHeads; j++) { + NvU64 startTime = 0; if (flipLockPossible && - !EvoWaitForLock(pDevEvo, sd, head[j], EVO_FLIP_LOCK)) { + !EvoWaitForLock(pDevEvo, sd, head[j], EVO_FLIP_LOCK, + &startTime)) { flipLockPossible = FALSE; break; } @@ -1640,54 +2098,131 @@ pUpdateState); } +NvBool nvGetDefaultColorSpace( + const NVColorFormatInfoRec *pColorFormatsInfo, + enum NvKmsDpyAttributeCurrentColorSpaceValue *pColorSpace, + enum NvKmsDpyAttributeColorBpcValue *pColorBpc) +{ + if (pColorFormatsInfo->rgb444.maxBpc != + NV_KMS_DPY_ATTRIBUTE_CURRENT_COLOR_BPC_UNKNOWN) { + *pColorSpace = NV_KMS_DPY_ATTRIBUTE_CURRENT_COLOR_SPACE_RGB; + *pColorBpc = pColorFormatsInfo->rgb444.maxBpc; + return TRUE; + } + + if (pColorFormatsInfo->yuv444.maxBpc != + NV_KMS_DPY_ATTRIBUTE_CURRENT_COLOR_BPC_UNKNOWN) { + *pColorSpace = NV_KMS_DPY_ATTRIBUTE_CURRENT_COLOR_SPACE_YCbCr444; + *pColorBpc = pColorFormatsInfo->yuv444.maxBpc; + return TRUE; + } + + if (pColorFormatsInfo->yuv422.maxBpc != + NV_KMS_DPY_ATTRIBUTE_CURRENT_COLOR_BPC_UNKNOWN) { + *pColorSpace = NV_KMS_DPY_ATTRIBUTE_CURRENT_COLOR_SPACE_YCbCr422; + *pColorBpc = pColorFormatsInfo->yuv422.maxBpc; + return TRUE; + } + + return FALSE; +} + +NvBool nvChooseColorRangeEvo( + enum NvKmsOutputTf tf, + const enum NvKmsDpyAttributeColorRangeValue requestedColorRange, + const enum NvKmsDpyAttributeCurrentColorSpaceValue colorSpace, + const enum NvKmsDpyAttributeColorBpcValue colorBpc, + enum NvKmsDpyAttributeColorRangeValue *pColorRange) +{ + /* Hardware supports BPC_6 only for RGB */ + nvAssert((colorSpace == NV_KMS_DPY_ATTRIBUTE_CURRENT_COLOR_SPACE_RGB) || + (colorBpc != NV_KMS_DPY_ATTRIBUTE_CURRENT_COLOR_BPC_6)); + + if ((colorSpace == NV_KMS_DPY_ATTRIBUTE_CURRENT_COLOR_SPACE_RGB) && + (colorBpc == NV_KMS_DPY_ATTRIBUTE_CURRENT_COLOR_BPC_6)) { + /* At depth 18 only RGB and full range are allowed */ + if (tf == NVKMS_OUTPUT_TF_PQ) { + /* NVKMS_OUTPUT_TF_PQ requires limited color range */ + return FALSE; + } + *pColorRange = NV_KMS_DPY_ATTRIBUTE_COLOR_RANGE_FULL; + } else if ((colorSpace == NV_KMS_DPY_ATTRIBUTE_CURRENT_COLOR_SPACE_YCbCr444) || + (colorSpace == NV_KMS_DPY_ATTRIBUTE_CURRENT_COLOR_SPACE_YCbCr422) || + (colorSpace == NV_KMS_DPY_ATTRIBUTE_CURRENT_COLOR_SPACE_YCbCr420) || + (tf == NVKMS_OUTPUT_TF_PQ)) { + /* Both YUV and NVKMS_OUTPUT_TF_PQ requires limited color range. */ + *pColorRange = NV_KMS_DPY_ATTRIBUTE_COLOR_RANGE_LIMITED; + } else { + *pColorRange = requestedColorRange; + } + + return TRUE; +} /*! - * Choose current colorSpace and colorRange based on the current mode timings - * and the requested color space and range, and notify clients of any changes. - * - * This needs to be called during a modeset when YUV420 mode may have been - * enabled or disabled, as well as when the requested color space or range have - * changed. + * Choose current colorSpace and colorRange for the given dpy based on + * the dpy's color format capailities, the given modeset parameters (YUV420 + * mode and output transfer function) and the requested color space and range. * - * RGB/YUV would be selected for DFP, only RGB would be selected for CRT and - * only YUV would be selected for TV. + * This needs to be called during a modeset as well as when the requested color + * space or range have changed. * * If SW YUV420 mode is enabled, EVO HW is programmed with default (RGB color * space, FULL color range) values, and the real values are used in a * headSurface composite shader. */ -void nvChooseCurrentColorSpaceAndRangeEvo( - enum nvKmsPixelDepth pixelDepth, +NvBool nvChooseCurrentColorSpaceAndRangeEvo( + const NVDpyEvoRec *pDpyEvo, enum NvYuv420Mode yuv420Mode, enum NvKmsOutputTf tf, const enum NvKmsDpyAttributeRequestedColorSpaceValue requestedColorSpace, const enum NvKmsDpyAttributeColorRangeValue requestedColorRange, enum NvKmsDpyAttributeCurrentColorSpaceValue *pCurrentColorSpace, + enum NvKmsDpyAttributeColorBpcValue *pCurrentColorBpc, enum NvKmsDpyAttributeColorRangeValue *pCurrentColorRange) { enum NvKmsDpyAttributeCurrentColorSpaceValue newColorSpace = NV_KMS_DPY_ATTRIBUTE_CURRENT_COLOR_SPACE_RGB; + enum NvKmsDpyAttributeColorBpcValue newColorBpc = + NV_KMS_DPY_ATTRIBUTE_CURRENT_COLOR_BPC_10; enum NvKmsDpyAttributeColorRangeValue newColorRange = NV_KMS_DPY_ATTRIBUTE_COLOR_RANGE_FULL; + const NVColorFormatInfoRec colorFormatsInfo = + nvGetColorFormatInfo(pDpyEvo); - /* At depth 18 only RGB and full range are allowed */ - if (pixelDepth == NVKMS_PIXEL_DEPTH_18_444) { - goto done; - } + // XXX HDR TODO: Handle other transfer functions + // XXX HDR TODO: Handle YUV + if (tf == NVKMS_OUTPUT_TF_PQ) { + /* + * If the head is currently in PQ output mode, we override the + * requested color space with RGB. We cannot support yuv420Mode in + * that configuration, so fail in that case. + */ + if (yuv420Mode != NV_YUV420_MODE_NONE) { + return FALSE; + } - /* - * If the current mode timing requires YUV420 compression, we override the - * requested color space with YUV420. - * - * If the head is currently in PQ output mode, we override the requested - * color space with BT2020. - */ - if (yuv420Mode != NV_YUV420_MODE_NONE) { + /* + * At depth 18 only RGB and full range are allowed. Also, + * NVKMS_OUTPUT_TF_PQ requires limited range, which we can't do at + * depth 18; fail in that case. + */ + if (colorFormatsInfo.rgb444.maxBpc == + NV_KMS_DPY_ATTRIBUTE_CURRENT_COLOR_BPC_6) { + return FALSE; + } + newColorSpace = NV_KMS_DPY_ATTRIBUTE_CURRENT_COLOR_SPACE_RGB; + newColorBpc = colorFormatsInfo.rgb444.maxBpc; + } else if (yuv420Mode != NV_YUV420_MODE_NONE) { + /* + * If the current mode timing requires YUV420 compression, we override the + * requested color space with YUV420. + */ newColorSpace = NV_KMS_DPY_ATTRIBUTE_CURRENT_COLOR_SPACE_YCbCr420; - } else if (tf == NVKMS_OUTPUT_TF_PQ) { - // XXX HDR TODO: Handle other transfer functions - // XXX HDR TODO: Handle YUV - newColorSpace = NV_KMS_DPY_ATTRIBUTE_CURRENT_COLOR_SPACE_BT2020RGB; + newColorBpc = NV_KMS_DPY_ATTRIBUTE_CURRENT_COLOR_BPC_8; + + nvAssert(colorFormatsInfo.rgb444.maxBpc >= + NV_KMS_DPY_ATTRIBUTE_CURRENT_COLOR_BPC_8); } else { /* * Note this is an assignment between different enum types. Checking the @@ -1697,31 +2232,38 @@ switch (requestedColorSpace) { case NV_KMS_DPY_ATTRIBUTE_REQUESTED_COLOR_SPACE_RGB: newColorSpace = NV_KMS_DPY_ATTRIBUTE_CURRENT_COLOR_SPACE_RGB; + newColorBpc = colorFormatsInfo.rgb444.maxBpc; break; case NV_KMS_DPY_ATTRIBUTE_REQUESTED_COLOR_SPACE_YCbCr422: newColorSpace = NV_KMS_DPY_ATTRIBUTE_CURRENT_COLOR_SPACE_YCbCr422; + newColorBpc = colorFormatsInfo.yuv422.maxBpc; break; case NV_KMS_DPY_ATTRIBUTE_REQUESTED_COLOR_SPACE_YCbCr444: newColorSpace = NV_KMS_DPY_ATTRIBUTE_CURRENT_COLOR_SPACE_YCbCr444; + newColorBpc = colorFormatsInfo.yuv444.maxBpc; break; default: nvAssert(!"Invalid Requested ColorSpace"); } + + if ((newColorBpc == + NV_KMS_DPY_ATTRIBUTE_CURRENT_COLOR_BPC_UNKNOWN) && + !nvGetDefaultColorSpace(&colorFormatsInfo, &newColorSpace, + &newColorBpc)) { + return FALSE; + } } - /* Only limited color range is allowed in YUV and BT2020 colorimetry. */ - if ((newColorSpace == NV_KMS_DPY_ATTRIBUTE_CURRENT_COLOR_SPACE_YCbCr444) || - (newColorSpace == NV_KMS_DPY_ATTRIBUTE_CURRENT_COLOR_SPACE_YCbCr422) || - (newColorSpace == NV_KMS_DPY_ATTRIBUTE_CURRENT_COLOR_SPACE_YCbCr420) || - (newColorSpace == NV_KMS_DPY_ATTRIBUTE_CURRENT_COLOR_SPACE_BT2020RGB)) { - newColorRange = NV_KMS_DPY_ATTRIBUTE_COLOR_RANGE_LIMITED; - } else { - newColorRange = requestedColorRange; + if (!nvChooseColorRangeEvo(tf, requestedColorRange, newColorSpace, + newColorBpc, &newColorRange)) { + return FALSE; } -done: *pCurrentColorSpace = newColorSpace; *pCurrentColorRange = newColorRange; + *pCurrentColorBpc = newColorBpc; + + return TRUE; } void nvUpdateCurrentHardwareColorSpaceAndRangeEvo( @@ -1737,11 +2279,21 @@ nvAssert(pConnectorEvo != NULL); - // In SW YUV420 mode, HW is programmed with RGB color space and full color - // range. The color space conversion and color range compression happen - // in a headSurface composite shader. - if ((pHeadState->timings.yuv420Mode == NV_YUV420_MODE_SW) && + if (pHeadState->tf == NVKMS_OUTPUT_TF_PQ) { + nvAssert(pHeadState->timings.yuv420Mode == NV_YUV420_MODE_NONE); + nvAssert(colorSpace == NV_KMS_DPY_ATTRIBUTE_CURRENT_COLOR_SPACE_RGB); + nvAssert(colorRange == NV_KMS_DPY_ATTRIBUTE_COLOR_RANGE_LIMITED); + + pHeadState->procAmp.colorimetry = NVT_COLORIMETRY_BT2020RGB; + pHeadState->procAmp.colorRange = NVT_COLOR_RANGE_LIMITED; + pHeadState->procAmp.colorFormat = NVT_COLOR_FORMAT_RGB; + } else if ((pHeadState->timings.yuv420Mode == NV_YUV420_MODE_SW) && (colorSpace == NV_KMS_DPY_ATTRIBUTE_CURRENT_COLOR_SPACE_YCbCr420)) { + /* + * In SW YUV420 mode, HW is programmed with RGB color space and full + * color range. The color space conversion and color range compression + * happen in a headSurface composite shader. + */ pHeadState->procAmp.colorimetry = NVT_COLORIMETRY_RGB; pHeadState->procAmp.colorRange = NVT_COLOR_RANGE_FULL; pHeadState->procAmp.colorFormat = NVT_COLOR_FORMAT_RGB; @@ -1754,7 +2306,6 @@ // Set color format switch (colorSpace) { case NV_KMS_DPY_ATTRIBUTE_CURRENT_COLOR_SPACE_RGB: - case NV_KMS_DPY_ATTRIBUTE_CURRENT_COLOR_SPACE_BT2020RGB: pHeadState->procAmp.colorFormat = NVT_COLOR_FORMAT_RGB; break; case NV_KMS_DPY_ATTRIBUTE_CURRENT_COLOR_SPACE_YCbCr444: @@ -1777,9 +2328,6 @@ case NV_KMS_DPY_ATTRIBUTE_CURRENT_COLOR_SPACE_RGB: pHeadState->procAmp.colorimetry = NVT_COLORIMETRY_RGB; break; - case NV_KMS_DPY_ATTRIBUTE_CURRENT_COLOR_SPACE_BT2020RGB: - pHeadState->procAmp.colorimetry = NVT_COLORIMETRY_BT2020RGB; - break; case NV_KMS_DPY_ATTRIBUTE_CURRENT_COLOR_SPACE_YCbCr444: case NV_KMS_DPY_ATTRIBUTE_CURRENT_COLOR_SPACE_YCbCr422: case NV_KMS_DPY_ATTRIBUTE_CURRENT_COLOR_SPACE_YCbCr420: @@ -1806,17 +2354,17 @@ nvAssert(!"ERROR: invalid pDpyEvo->type"); } - // Only advertise YCbCr444 or YCbCr422 when the corresponding - // colorSpaceCaps is TRUE. - if ((colorSpace == NV_KMS_DPY_ATTRIBUTE_CURRENT_COLOR_SPACE_YCbCr444) && - !pConnectorEvo->colorSpaceCaps.ycbcr444Capable) { - nvAssert(!"!pConnectorEvo->colorSpaceCaps.ycbcr444Capable"); - } - - if ((colorSpace == NV_KMS_DPY_ATTRIBUTE_CURRENT_COLOR_SPACE_YCbCr422) && - !pConnectorEvo->colorSpaceCaps.ycbcr422Capable) { - nvAssert(!"!pConnectorEvo->colorSpaceCaps.ycbcr422Capable"); - } + /* YCbCr444 should be advertise only for DisplayPort and HDMI */ + nvAssert((colorSpace != NV_KMS_DPY_ATTRIBUTE_CURRENT_COLOR_SPACE_YCbCr444) || + nvConnectorUsesDPLib(pConnectorEvo) || + pConnectorEvo->isHdmiEnabled); + + /* YcbCr422 should be advertised only for HDMI and DP on supported GPUs */ + nvAssert((colorSpace != NV_KMS_DPY_ATTRIBUTE_CURRENT_COLOR_SPACE_YCbCr422) || + (((pDevEvo->caps.hdmiYCbCr422MaxBpc != 0) && + pConnectorEvo->isHdmiEnabled)) || + ((pDevEvo->caps.dpYCbCr422MaxBpc != 0) && + nvConnectorUsesDPLib(pConnectorEvo))); switch (colorRange) { case NV_KMS_DPY_ATTRIBUTE_COLOR_RANGE_FULL: @@ -1836,7 +2384,7 @@ (pHeadState->procAmp.colorRange != NVT_COLOR_RANGE_LIMITED))); // Limited color range is not allowed with 18bpp mode - nvAssert(!((pHeadState->timings.pixelDepth == NVKMS_PIXEL_DEPTH_18_444) && + nvAssert(!((pHeadState->pixelDepth == NVKMS_PIXEL_DEPTH_18_444) && (pHeadState->procAmp.colorRange == NVT_COLOR_RANGE_LIMITED))); nvPushEvoSubDevMaskDisp(pDispEvo); @@ -1854,6 +2402,7 @@ NVDevEvoPtr pDevEvo = pDispEvo->pDevEvo; const NVDispHeadStateEvoPtr pHeadState = &pDispEvo->headState[head]; const NVHwModeTimingsEvo *pTimings = &pHeadState->timings; + const enum nvKmsPixelDepth pixelDepth = pHeadState->pixelDepth; NvBool colorSpaceOverride = FALSE; /* @@ -1874,7 +2423,7 @@ // Only set up the actual output for SLI primary. nvPushEvoSubDevMask(pDevEvo, 1 << pDispEvo->displayOwner); - pDevEvo->hal->HeadSetControlOR(pDevEvo, head, pTimings, + pDevEvo->hal->HeadSetControlOR(pDevEvo, head, pTimings, pixelDepth, colorSpaceOverride, pUpdateState); @@ -1913,7 +2462,7 @@ */ void nvChooseDitheringEvo( const NVConnectorEvoRec *pConnectorEvo, - const enum nvKmsPixelDepth pixelDepth, + enum NvKmsDpyAttributeColorBpcValue bpc, const NVDpyAttributeRequestedDitheringConfig *pReqDithering, NVDpyAttributeCurrentDitheringConfig *pCurrDithering) { @@ -1989,10 +2538,9 @@ * which lowers the color depth, consider that while applying * dithering effects. */ - NvU32 dpBits = nvPixelDepthToBitsPerComponent(pixelDepth); - if (dpBits == 0) { + if (bpc == 0) { nvAssert(!"Unknown dpBits"); - dpBits = 8; + bpc = 8; } /* @@ -2002,7 +2550,7 @@ * * XXX TODO: nvdisplay can dither to 10 bpc. */ - if ((dpBits <= 8) && (lutBits > dpBits)) { + if ((bpc <= 8) && (lutBits > bpc)) { if (pReqDithering->state == NV_KMS_DPY_ATTRIBUTE_REQUESTED_DITHERING_AUTO) { currDithering.enabled = TRUE; @@ -2011,10 +2559,10 @@ if (pReqDithering->depth == NV_KMS_DPY_ATTRIBUTE_REQUESTED_DITHERING_DEPTH_AUTO) { - if (dpBits <= 6) { + if (bpc <= 6) { currDithering.depth = NV_KMS_DPY_ATTRIBUTE_CURRENT_DITHERING_DEPTH_6_BITS; - } else if (dpBits <= 8) { + } else if (bpc <= 8) { currDithering.depth = NV_KMS_DPY_ATTRIBUTE_CURRENT_DITHERING_DEPTH_8_BITS; } @@ -2104,7 +2652,7 @@ { NVEvoHeadControlPtr pHC = &pDevEvo->gpus[sd].headControlAssy[head]; - return (!pHC->interlaced && + return (!pHC->interlaced && !pHC->mergeMode && ((pHC->serverLock != NV_EVO_NO_LOCK) || (pHC->clientLock != NV_EVO_NO_LOCK))); } @@ -2992,12 +3540,20 @@ NVDispEvoPtr pDispEvo = pDpyEvo->pDispEvo; NVDevEvoPtr pDevEvo = pDispEvo->pDevEvo; NVEvoSubDevPtr pEvoSubDev; + const NvU32 apiHead = pDpyEvo->apiHead; + const NvU32 head = nvGetPrimaryHwHead(pDispEvo, apiHead); + NVEvoHeadControlPtr pHC; + /* - * XXX[2Heads1OR] Loop over hardware heads to determine if this api-head - * is rasterlocked with any other api-head. + * XXX[2Heads1OR] The EVO lock state machine is not currently supported with + * 2Heads1OR, the api head is expected to be mapped onto a single + * hardware head (which is the primary hardware head) if 2Heads1OR is not + * active and the EVO lock state machine is in use. */ - const NvU32 head = pDpyEvo->apiHead; - NVEvoHeadControlPtr pHC; + if ((apiHead == NV_INVALID_HEAD) || + (nvPopCount32(pDispEvo->apiHeadState[apiHead].hwHeadsMask) != 1)) { + return FALSE; + } if ((head == NV_INVALID_HEAD) || (pDevEvo->gpus == NULL)) { return FALSE; @@ -3012,6 +3568,16 @@ return TRUE; } +void nvInvalidateTopologiesEvo(void) +{ + if (nvEvoGlobal.globalTopologies) { + nvFree(nvEvoGlobal.globalTopologies); + + nvEvoGlobal.globalTopologies = NULL; + nvEvoGlobal.numGlobalTopos = 0; + } +} + /* * Return the surface format usage bounds that NVKMS will program for the * requested format. @@ -3083,6 +3649,14 @@ NVEvoSubDevPtr pEvoSubDev = &pDevEvo->gpus[pDispEvo->displayOwner]; NVEvoHeadControlPtr pHC = &pEvoSubDev->headControl[head]; + /* + * XXX: [2Heads1OR] If head is locked in the merge mode then its flip-lock + * state can not be changed. + */ + if (pHC->mergeMode) { + return FALSE; + } + if (needsEarlyUpdate) { *needsEarlyUpdate = FALSE; } @@ -3158,15 +3732,22 @@ NvU32 *val, NvBool set) { NVDispEvoPtr pDispEvo = pDpyEvo->pDispEvo; - /* - * XXX[2Heads1OR] Loop over hardware heads to determine is this api-head - * is rasterlocked with any other api-head and flip lock is not prohibited - * on its corresponding hardware heads. - */ - const NvU32 head = pDpyEvo->apiHead; + const NvU32 apiHead = pDpyEvo->apiHead; + const NvU32 head = nvGetPrimaryHwHead(pDispEvo, apiHead); NVEvoUpdateState updateState = { }; NvBool ret; + /* + * XXX[2Heads1OR] The EVO lock state machine is not currently supported with + * 2Heads1OR, the api head is expected to be mapped onto a single + * hardware head (which is the primary hardware head) if 2Heads1OR is not + * active and the EVO lock state machine is in use. + */ + if ((apiHead == NV_INVALID_HEAD) || + (nvPopCount32(pDispEvo->apiHeadState[apiHead].hwHeadsMask) != 1)) { + return FALSE; + } + if (head == NV_INVALID_HEAD) { return FALSE; } @@ -3212,9 +3793,12 @@ NVEvoSubDevPtr pEvoSubDev = &pDevEvo->gpus[pDispEvo->displayOwner]; for (head = 0; head < NVKMS_MAX_HEADS_PER_DISP; head++) { - NVEvoHeadControlPtr pHC = NULL; - - if (!nvHeadIsActive(pDispEvo, head)) { + NVEvoHeadControlPtr pHC = &pEvoSubDev->headControl[head]; + /* + * XXX: [2Heads1OR] If head is locked in the merge mode then its flip-lock + * state can not be changed. + */ + if (!nvHeadIsActive(pDispEvo, head) || pHC->mergeMode) { continue; } @@ -3225,8 +3809,6 @@ continue; } - pHC = &pEvoSubDev->headControl[head]; - if (pHC->flipLock) { needUpdate = TRUE; @@ -3253,14 +3835,16 @@ NVEvoSubDevPtr pEvoSubDev = &pDevEvo->gpus[pDispEvo->displayOwner]; for (head = 0; head < NVKMS_MAX_HEADS_PER_DISP; head++) { - NVEvoHeadControlPtr pHC = NULL; + NVEvoHeadControlPtr pHC = &pEvoSubDev->headControl[head]; - if (!nvHeadIsActive(pDispEvo, head)) { + /* + * XXX: [2Heads1OR] If head is locked in the merge mode then its flip-lock + * state can not be changed. + */ + if (!nvHeadIsActive(pDispEvo, head) || pHC->mergeMode) { continue; } - pHC = &pEvoSubDev->headControl[head]; - if (!pHC->flipLock && HEAD_MASK_QUERY(pEvoSubDev->flipLockEnabledForSliHeadMask, head)) { @@ -3412,47 +3996,46 @@ nvPopEvoSubDevMask(pDevEvo); } -static inline NvU32 LUTNotifierForHead(const NvU32 head) +static inline NvU32 LUTNotifierForApiHead(const NvU32 apiHead) { - nvAssert(head != NV_INVALID_HEAD); - return 1 + head; + nvAssert(apiHead != NV_INVALID_HEAD); + return 1 + apiHead; } -//****************************************************************************** -// -// Function: EvoUpdateCurrentPalette -// -// Description: Setting the palette -// -// Arguments: -// -// Return Value: None. -// -//****************************************************************************** -void nvEvoUpdateCurrentPalette(NVDispEvoPtr pDispEvo, - NvU32 head, NvBool kickOff) +void nvEvoSetLUTContextDma(NVDispEvoPtr pDispEvo, + const NvU32 head, NVEvoUpdateState *pUpdateState) { NVDevEvoPtr pDevEvo = pDispEvo->pDevEvo; const NVDispHeadStateEvoRec *pHeadState = &pDispEvo->headState[head]; + + pDevEvo->hal->SetLUTContextDma(pDispEvo, + head, + pHeadState->lut.pCurrSurface, + pHeadState->lut.baseLutEnabled, + pHeadState->lut.outputLutEnabled, + pUpdateState, + pHeadState->bypassComposition); +} + +static void EvoUpdateCurrentPalette(NVDispEvoPtr pDispEvo, const NvU32 apiHead) +{ + NVDevEvoPtr pDevEvo = pDispEvo->pDevEvo; + NVDispApiHeadStateEvoRec *pApiHeadState = + &pDispEvo->apiHeadState[apiHead]; const int dispIndex = pDispEvo->displayOwner; - NvU8 lutIndex = pDevEvo->lut.head[head].disp[dispIndex].curLUTIndex; + NvU32 head; NVEvoUpdateState updateState = { }; - pDevEvo->hal->SetLUTContextDma( - pDispEvo, - head, - pDevEvo->lut.head[head].LUT[lutIndex], - pDevEvo->lut.head[head].disp[dispIndex].curBaseLutEnabled, - pDevEvo->lut.head[head].disp[dispIndex].curOutputLutEnabled, - &updateState, - pHeadState->bypassComposition); + FOR_EACH_EVO_HW_HEAD_IN_MASK(pApiHeadState->hwHeadsMask, head) { + nvEvoSetLUTContextDma(pDispEvo, head, &updateState); + } /* * EVO2 does not set LUT context DMA if the core channel * doesn't have a scanout surface set, in that case there is no update * state to kickoff. */ - if (kickOff && !nvIsUpdateStateEmpty(pDevEvo, &updateState)) { + if (!nvIsUpdateStateEmpty(pDevEvo, &updateState)) { // Clear the completion notifier and kick off an update. Wait for it // here if NV_CTRL_SYNCHRONOUS_PALETTE_UPDATES is enabled. Otherwise, // don't wait for the notifier -- it'll be checked the next time a LUT @@ -3460,10 +4043,10 @@ EvoUpdateAndKickOffWithNotifier(pDispEvo, TRUE, /* notify */ FALSE, /* sync */ - LUTNotifierForHead(head), + LUTNotifierForApiHead(apiHead), &updateState, TRUE /* releaseElv */); - pDevEvo->lut.head[head].disp[dispIndex].waitForPreviousUpdate = TRUE; + pDevEvo->lut.apiHead[apiHead].disp[dispIndex].waitForPreviousUpdate = TRUE; } } @@ -3568,51 +4151,296 @@ return TRUE; } -static void InitApiHeadState(NVDevEvoRec *pDevEvo) +static void UnregisterFlipOccurredEventOneHead(NVDispEvoRec *pDispEvo, + const NvU32 head) { - NVDispEvoRec *pDispEvo; - NvU32 dispIndex; - NvU32 head; + NVDevEvoRec *pDevEvo = pDispEvo->pDevEvo; + NvU32 layer; - nvAssert(pDevEvo->numApiHeads == pDevEvo->numHeads); + /* XXX NVKMS TODO: need disp-scope in event */ + if (pDispEvo->displayOwner != 0) { + return; + } - for (head = 0; head < pDevEvo->numHeads; head++) { - NvU32 apiHead = nvHardwareHeadToApiHead(head); - pDevEvo->apiHead[apiHead].numLayers = - pDevEvo->head[head].numLayers; + for (layer = 0; layer < pDevEvo->head[head].numLayers; layer++) { + NVEvoChannelPtr pChannel = pDevEvo->head[head].layer[layer]; + + nvAssert((pChannel->completionNotifierEventHandle == 0) || + (pChannel->completionNotifierEventRefPtr != NULL)); + + if (pChannel->completionNotifierEventHandle != 0) { + nvRmApiFree(nvEvoGlobal.clientHandle, + pChannel->pb.channel_handle, + pChannel->completionNotifierEventHandle); + nvFreeUnixRmHandle(&pDevEvo->handleAllocator, + pChannel->completionNotifierEventHandle); + pChannel->completionNotifierEventHandle = 0; + pChannel->completionNotifierEventRefPtr = NULL; + } + } +} + +static void ClearApiHeadStateOneDisp(NVDispEvoRec *pDispEvo) +{ + NvU32 apiHead; + + /* + * Unregister all the flip-occurred event callbacks which are + * registered with the (api-head, layer) pair event data, + * before destroying the api-head states. + */ + for (NvU32 head = 0; head < pDispEvo->pDevEvo->numHeads; head++) { + UnregisterFlipOccurredEventOneHead(pDispEvo, head); } + for (apiHead = 0; apiHead < ARRAY_LEN(pDispEvo->apiHeadState); apiHead++) { + NvU32 layer; + NVDispApiHeadStateEvoRec *pApiHeadState = + &pDispEvo->apiHeadState[apiHead]; + nvAssert(nvListIsEmpty(&pApiHeadState->vblankCallbackList)); + for (layer = 0; layer < ARRAY_LEN(pApiHeadState->flipOccurredEvent); layer++) { + if (pApiHeadState->flipOccurredEvent[layer].ref_ptr != NULL) { + nvkms_free_ref_ptr(pApiHeadState->flipOccurredEvent[layer].ref_ptr); + pApiHeadState->flipOccurredEvent[layer].ref_ptr = NULL; + } + } + } + + nvkms_memset(pDispEvo->apiHeadState, 0, sizeof(pDispEvo->apiHeadState)); +} + +static void ClearApiHeadState(NVDevEvoRec *pDevEvo) +{ + NvU32 dispIndex; + NVDispEvoRec *pDispEvo; + + nvRmFreeCoreRGSyncpts(pDevEvo); + FOR_ALL_EVO_DISPLAYS(pDispEvo, dispIndex, pDevEvo) { - for (head = 0; head < pDevEvo->numHeads; head++) { - NvU32 apiHead = nvHardwareHeadToApiHead(head); + ClearApiHeadStateOneDisp(pDispEvo); + } - pDispEvo->apiHeadState[apiHead].hwHeadsMask = NVBIT(head); - pDispEvo->apiHeadState[apiHead].attributes = - NV_EVO_DEFAULT_ATTRIBUTES_SET; - - if (pDispEvo->headState[head].pConnectorEvo != NULL) { - const NVConnectorEvoRec *pConnectorEvo = - pDispEvo->headState[head].pConnectorEvo; + nvkms_memset(pDevEvo->apiHead, 0, sizeof(pDevEvo->apiHead)); +} - /* - * Use the pDpyEvo for the connector, since we may not have one - * for display id if it's a dynamic one. - */ - NVDpyEvoRec *pDpyEvo = nvGetDpyEvoFromDispEvo(pDispEvo, - pConnectorEvo->displayId); +static NvBool InitApiHeadStateOneDisp(NVDispEvoRec *pDispEvo) +{ + NvU32 usedApiHeadsMask = 0x0; + const NVDevEvoRec *pDevEvo = pDispEvo->pDevEvo; + + for (NvU32 apiHead = 0; apiHead < ARRAY_LEN(pDispEvo->apiHeadState); apiHead++) { + NvU32 layer; + NVDispApiHeadStateEvoRec *pApiHeadState = + &pDispEvo->apiHeadState[apiHead]; - nvAssert(pDpyEvo->apiHead == NV_INVALID_HEAD); + pApiHeadState->activeDpys = nvEmptyDpyIdList(); + pApiHeadState->attributes = NV_EVO_DEFAULT_ATTRIBUTES_SET; - pDpyEvo->apiHead = apiHead; - pDispEvo->apiHeadState[apiHead].activeDpys = - nvAddDpyIdToEmptyDpyIdList(pConnectorEvo->displayId); - } else { - pDispEvo->apiHeadState[apiHead].activeDpys = nvEmptyDpyIdList(); + nvListInit(&pApiHeadState->vblankCallbackList); + + for (layer = 0; layer < ARRAY_LEN(pApiHeadState->flipOccurredEvent); layer++) { + pApiHeadState->flipOccurredEvent[layer].ref_ptr = + nvkms_alloc_ref_ptr(&pApiHeadState->flipOccurredEvent[layer].data); + if (pApiHeadState->flipOccurredEvent[layer].ref_ptr == NULL) { + goto failed; } + + pApiHeadState->flipOccurredEvent[layer].data = + (NVDispFlipOccurredEventDataEvoRec) { + .pDispEvo = pDispEvo, + .apiHead = apiHead, + .layer = layer, + }; + } + } + + for (NvU32 head = 0; head < pDevEvo->numHeads; head++) { + if (pDispEvo->headState[head].pConnectorEvo != NULL) { + NvU32 apiHead; + const NVConnectorEvoRec *pConnectorEvo = + pDispEvo->headState[head].pConnectorEvo; + + /* Find unused api-head which support the equal number of layers */ + for (apiHead = 0; apiHead < pDevEvo->numApiHeads; apiHead++) { + if ((NVBIT(apiHead) & usedApiHeadsMask) != 0x0) { + continue; + } + + if (pDevEvo->apiHead[apiHead].numLayers == + pDevEvo->head[head].numLayers) { + usedApiHeadsMask |= NVBIT(apiHead); + break; + } + } + nvAssert(apiHead < pDevEvo->numApiHeads); + + /* + * Use the pDpyEvo for the connector, since we may not have one + * for display id if it's a dynamic one. + */ + NVDpyEvoRec *pDpyEvo = nvGetDpyEvoFromDispEvo(pDispEvo, + pConnectorEvo->displayId); + + nvAssert(pDpyEvo->apiHead == NV_INVALID_HEAD); + + pDpyEvo->apiHead = apiHead; + nvAssignHwHeadsMaskApiHeadState( + &pDispEvo->apiHeadState[apiHead], + NVBIT(head)); + pDispEvo->apiHeadState[apiHead].activeDpys = + nvAddDpyIdToEmptyDpyIdList(pConnectorEvo->displayId); + } + } + + return TRUE; + +failed: + ClearApiHeadStateOneDisp(pDispEvo); + + return FALSE; +} + +static void +CompletionNotifierEventDeferredWork(void *dataPtr, NvU32 dataU32) +{ + NVDispFlipOccurredEventDataEvoRec *pEventData = dataPtr; + + nvSendFlipOccurredEventEvo(pEventData->pDispEvo, pEventData->apiHead, + pEventData->layer); +} + +static void CompletionNotifierEvent(void *arg, void *pEventDataVoid, + NvU32 hEvent, NvU32 Data, NV_STATUS Status) +{ + (void) nvkms_alloc_timer_with_ref_ptr( + CompletionNotifierEventDeferredWork, /* callback */ + arg, /* argument (this is a ref_ptr to NVDispFlipOccurredEventDataEvoRec) */ + 0, /* dataU32 */ + 0); /* timeout: schedule the work immediately */ +} + +void nvEvoPreModesetRegisterFlipOccurredEvent(NVDispEvoRec *pDispEvo, + const NvU32 head, + const NVEvoModesetUpdateState + *pModesetUpdate) +{ + NVDevEvoRec *pDevEvo = pDispEvo->pDevEvo; + NvU32 layer; + + /* XXX NVKMS TODO: need disp-scope in event */ + if (pDispEvo->displayOwner != 0) { + return; + } + + for (layer = 0; layer < pDevEvo->head[head].numLayers; layer++) { + NVEvoChannelPtr pChannel = pDevEvo->head[head].layer[layer]; + const struct _NVEvoModesetUpdateStateOneLayer *pLayer = + &pModesetUpdate->flipOccurredEvent[head].layer[layer]; + + if (!pLayer->changed || + (pLayer->ref_ptr == NULL) || + (pLayer->ref_ptr == pChannel->completionNotifierEventRefPtr)) { + continue; + } + + nvAssert((pChannel->completionNotifierEventHandle == 0) && + (pChannel->completionNotifierEventRefPtr == NULL)); + + pChannel->completionNotifierEventHandle = + nvGenerateUnixRmHandle(&pDevEvo->handleAllocator); + + if (!nvRmRegisterCallback(pDevEvo, + &pChannel->completionNotifierEventCallback, + pLayer->ref_ptr, + pChannel->pb.channel_handle, + pChannel->completionNotifierEventHandle, + CompletionNotifierEvent, + 0)) { + nvFreeUnixRmHandle(&pDevEvo->handleAllocator, + pChannel->completionNotifierEventHandle); + pChannel->completionNotifierEventHandle = 0; + } else { + pChannel->completionNotifierEventRefPtr = pLayer->ref_ptr; } } } +void nvEvoPostModesetUnregisterFlipOccurredEvent(NVDispEvoRec *pDispEvo, + const NvU32 head, + const NVEvoModesetUpdateState + *pModesetUpdate) +{ + NVDevEvoRec *pDevEvo = pDispEvo->pDevEvo; + NvU32 layer; + + /* XXX NVKMS TODO: need disp-scope in event */ + if (pDispEvo->displayOwner != 0) { + return; + } + + for (layer = 0; layer < pDevEvo->head[head].numLayers; layer++) { + NVEvoChannelPtr pChannel = pDevEvo->head[head].layer[layer]; + const struct _NVEvoModesetUpdateStateOneLayer *pLayer = + &pModesetUpdate->flipOccurredEvent[head].layer[layer]; + + if (!pLayer->changed || + (pLayer->ref_ptr != NULL) || + (pChannel->completionNotifierEventHandle == 0)) { + + /* + * If the flip occurred event of this layer is updated to get + * enabled (pLayer->ref_ptr != NULL) then that update should have + * been already processed by + * nvEvoPreModesetRegisterFlipOccurredEvent() and + * pChannel->completionNotifierEventRefPtr == pLayer->ref_ptr. + */ + nvAssert(!pLayer->changed || + (pChannel->completionNotifierEventHandle == 0) || + (pChannel->completionNotifierEventRefPtr == + pLayer->ref_ptr)); + continue; + } + + nvRmApiFree(nvEvoGlobal.clientHandle, + pChannel->pb.channel_handle, + pChannel->completionNotifierEventHandle); + nvFreeUnixRmHandle(&pDevEvo->handleAllocator, + pChannel->completionNotifierEventHandle); + pChannel->completionNotifierEventHandle = 0; + pChannel->completionNotifierEventRefPtr = NULL; + } +} + +static NvBool InitApiHeadState(NVDevEvoRec *pDevEvo) +{ + NVDispEvoRec *pDispEvo; + NvU32 dispIndex; + + /* + * For every hardware head, there should be at least one api-head + * which supports the equal number of layer. + */ + nvAssert(pDevEvo->numApiHeads == pDevEvo->numHeads); + for (NvU32 head = 0; head < pDevEvo->numHeads; head++) { + pDevEvo->apiHead[head].numLayers = pDevEvo->head[head].numLayers; + } + + FOR_ALL_EVO_DISPLAYS(pDispEvo, dispIndex, pDevEvo) { + if (!InitApiHeadStateOneDisp(pDispEvo)) { + goto failed; + } + } + + nvRmAllocCoreRGSyncpts(pDevEvo); + + return TRUE; + +failed: + ClearApiHeadState(pDevEvo); + + return FALSE; +} + /*! * Allocate the EVO core channel. * @@ -3778,6 +4606,12 @@ goto failed; } + if (!InitApiHeadState(pDevEvo)) { + nvEvoLogDev(pDevEvo, EVO_LOG_ERROR, + "Failed to initialize the api heads."); + goto failed; + } + FOR_ALL_EVO_DISPLAYS(pDispEvo, dispIndex, pDevEvo) { nvRmRegisterBacklight(pDispEvo); } @@ -3790,8 +4624,6 @@ } } - InitApiHeadState(pDevEvo); - return TRUE; failed: @@ -3801,9 +4633,10 @@ } /*! - * Clear the pConnectorEvo->or.mask tracking. + * Clear the pConnectorEvo->or.primary and pConnectorEvo->or.secondaryMask + * tracking. */ -static void ClearSORAssignmentsOneDisp(NVDispEvoPtr pDispEvo) +static void ClearSORAssignmentsOneDisp(const NVDispEvoRec *pDispEvo) { NVConnectorEvoPtr pConnectorEvo; @@ -3815,14 +4648,16 @@ continue; } - pConnectorEvo->or.mask = 0x0; + pConnectorEvo->or.primary = NV_INVALID_OR; + pConnectorEvo->or.secondaryMask = 0x0; } } /*! - * Update pConnectorEvo->or.mask from the list given to us by RM. + * Update pConnectorEvo->or.primary and pConnectorEvo->or.secondaryMask from + * the list given to us by RM. */ -static void RefreshSORAssignments(NVDispEvoPtr pDispEvo, +static void RefreshSORAssignments(const NVDispEvoRec *pDispEvo, const NV0073_CTRL_DFP_ASSIGN_SOR_PARAMS *pParams) { NVConnectorEvoPtr pConnectorEvo; @@ -3841,22 +4676,38 @@ sorIndex < ARRAY_LEN(pParams->sorAssignList) && sorIndex < ARRAY_LEN(pConnectorEvo->or.ownerHeadMask); sorIndex++) { - if ((pParams->sorAssignList[sorIndex] & displayId) == displayId) { - pConnectorEvo->or.mask |= NVBIT(sorIndex); + if ((pParams->sorAssignListWithTag[sorIndex].displayMask & + displayId) == displayId) { + if ((pParams->sorAssignListWithTag[sorIndex].sorType == + NV0073_CTRL_DFP_SOR_TYPE_SINGLE) || + (pParams->sorAssignListWithTag[sorIndex].sorType == + NV0073_CTRL_DFP_SOR_TYPE_2H1OR_PRIMARY)) { + pConnectorEvo->or.primary = sorIndex; + } else { + nvAssert(pParams->sorAssignListWithTag[sorIndex].sorType == + NV0073_CTRL_DFP_SOR_TYPE_2H1OR_SECONDARY); + pConnectorEvo->or.secondaryMask |= NVBIT(sorIndex); + } } } + + nvAssert((pConnectorEvo->or.secondaryMask == 0) || + (pConnectorEvo->or.primary != NV_INVALID_OR)); } } /* - * Ask RM to assign an SOR for the given connector. + * Ask RM to assign an SOR to given displayId. + * + * In 2Heads1OR MST case, this function gets called with the dynamic displayId. * * Note that this assignment may be temporary. This function will always call * RM, and unless the connector is currently in use (i.e., being driven by a * head), a previously-assigned SOR may be reused. * * The RM will either: - * a) return an SOR that's already assigned/attached to this connector, or + * a) return an SOR that's already assigned/attached + * to root port of this displayId, or * b) pick a new "unused" SOR, assign and attach it to this connector, and * return that -- where "unused" means both not being actively driven by a * head and not in the "exclude mask" argument. @@ -3881,39 +4732,25 @@ * finishes the "assessment", the SOR is again eligible for reuse. * * Because of the potential for SOR reuse, nvAssignSOREvo() will always call - * RefreshSORAssignments() to update pConnectorEvo->or.mask on *every* - * connector after calling NV0073_CTRL_CMD_DFP_ASSIGN_SOR for *any* connector. + * RefreshSORAssignments() to update pConnectorEvo->or.primary and + * pConnectorEvo->or.secondaryMask on *every* connector after calling + * NV0073_CTRL_CMD_DFP_ASSIGN_SOR for *any* connector. */ -NvBool nvAssignSOREvo(NVConnectorEvoPtr pConnectorEvo, NvU32 sorExcludeMask) +NvBool nvAssignSOREvo(const NVDispEvoRec *pDispEvo, const NvU32 displayId, + const NvBool b2Heads1Or, const NvU32 sorExcludeMask) { - NVDispEvoPtr pDispEvo = pConnectorEvo->pDispEvo; - NVDevEvoPtr pDevEvo = pDispEvo->pDevEvo; - - NvU32 displayId = 0x0; - + const NVDevEvoRec *pDevEvo = pDispEvo->pDevEvo; NV0073_CTRL_DFP_ASSIGN_SOR_PARAMS params = { 0 }; NvU32 ret; - /* - * Skip assigning an SOR for non-SOR connectors or if an SOR is already - * assigned. - */ - if (pConnectorEvo->or.type != NV0073_CTRL_SPECIFIC_OR_TYPE_SOR) { - return TRUE; - } - if (!NV0073_CTRL_SYSTEM_GET_CAP(pDevEvo->commonCapsBits, NV0073_CTRL_SYSTEM_CAPS_CROSS_BAR_SUPPORTED)) { return TRUE; } - /* Mode-set is not possible without SOR */ - nvAssert(!nvIsConnectorActiveEvo(pConnectorEvo)); - - displayId = nvDpyIdToNvU32(pConnectorEvo->displayId); - params.subDeviceInstance = pDispEvo->displayOwner; params.displayId = displayId; + params.bIs2Head1Or = b2Heads1Or; params.sorExcludeMask = sorExcludeMask; ret = nvRmApiControl(nvEvoGlobal.clientHandle, @@ -3927,7 +4764,6 @@ } RefreshSORAssignments(pDispEvo, ¶ms); - nvAssert(pConnectorEvo->or.mask != 0); return TRUE; } @@ -3938,25 +4774,23 @@ const NVConnectorEvoRec *pConnectorEvo; FOR_ALL_EVO_CONNECTORS(pConnectorEvo, pDispEvo) { - NvU32 i; - - if (pConnectorEvo->or.type != NV0073_CTRL_SPECIFIC_OR_TYPE_SOR) { + if ((pConnectorEvo->or.type != NV0073_CTRL_SPECIFIC_OR_TYPE_SOR) || + (pConnectorEvo->or.primary == NV_INVALID_OR)) { continue; } - FOR_EACH_INDEX_IN_MASK(32, i, pConnectorEvo->or.mask) { - /* - * RM populates same sor index into more than one connectors if - * they are are DCC partners, this checks make sure SOR - * assignment happens only for a single connector. The sor - * assignment call before modeset/dp-link-training makes sure - * assignment happens for the correct connector. - */ - if (sorAssignList[i] != NULL) { - continue; - } - sorAssignList[i] = pConnectorEvo; - } FOR_EACH_INDEX_IN_MASK_END + /* + * RM populates same sor index into more than one connectors if + * they are are DCC partners, this checks make sure SOR + * assignment happens only for a single connector. The sor + * assignment call before modeset/dp-link-training makes sure + * assignment happens for the correct connector. + */ + if (sorAssignList[pConnectorEvo->or.primary] != NULL) { + continue; + } + sorAssignList[pConnectorEvo->or.primary] = + pConnectorEvo; } } @@ -4037,7 +4871,7 @@ * restore the assignment, might be in use by the boot display setup * by vbios/gop driver. */ - nvShutDownHeads(pDevEvo, NULL /* pTestFunc, shut down all heads */); + nvShutDownApiHeads(pDevEvo, NULL /* pTestFunc, shut down all heads */); FOR_ALL_EVO_DISPLAYS(pDispEvo, dispIndex, pDevEvo) { RestoreSorAssignList(pDispEvo, disp[dispIndex].sorAssignList); @@ -4052,18 +4886,6 @@ nvFreeCoreChannelEvo(pDevEvo); } -static void ClearApiHeadState(NVDevEvoRec *pDevEvo) -{ - NvU32 dispIndex; - NVDispEvoRec *pDispEvo; - - nvkms_memset(pDevEvo->apiHead, 0, sizeof(pDevEvo->apiHead)); - - FOR_ALL_EVO_DISPLAYS(pDispEvo, dispIndex, pDevEvo) { - nvkms_memset(pDispEvo->apiHeadState, 0, sizeof(pDispEvo->apiHeadState)); - } -} - /*! * Free the EVO core channel. * @@ -4301,6 +5123,37 @@ nvPopEvoSubDevMask(pDevEvo); } +static void LayerSetPositionOneApiHead(NVDispEvoRec *pDispEvo, + const NvU32 apiHead, + const NvU32 layer, + const NvS16 x, + const NvS16 y, + NVEvoUpdateState *pUpdateState) +{ + NVDevEvoPtr pDevEvo = pDispEvo->pDevEvo; + const NVDispApiHeadStateEvoRec *pApiHeadState = + &pDispEvo->apiHeadState[apiHead]; + const NvU32 sd = pDispEvo->displayOwner; + NvU32 head; + + FOR_EACH_EVO_HW_HEAD_IN_MASK(pApiHeadState->hwHeadsMask, head) { + NVEvoSubDevHeadStateRec *pSdHeadState = + &pDevEvo->gpus[sd].headState[head]; + + if ((pSdHeadState->layer[layer].outputPosition.x != x) || + (pSdHeadState->layer[layer].outputPosition.y != y)) { + NVEvoChannelPtr pChannel = + pDevEvo->head[head].layer[layer]; + + pSdHeadState->layer[layer].outputPosition.x = x; + pSdHeadState->layer[layer].outputPosition.y = y; + + pDevEvo->hal->SetImmPointOut(pDevEvo, pChannel, sd, pUpdateState, + x, y); + } + } +} + NvBool nvLayerSetPositionEvo( NVDevEvoPtr pDevEvo, const struct NvKmsSetLayerPositionRequest *pRequest) @@ -4315,29 +5168,29 @@ * state. */ FOR_ALL_EVO_DISPLAYS(pDispEvo, sd, pDevEvo) { - NvU32 head; + NvU32 apiHead; if ((pRequest->requestedDispsBitMask & NVBIT(sd)) == 0) { continue; } - for (head = 0; head < NVKMS_MAX_HEADS_PER_DISP; head++) { + for (apiHead = 0; apiHead < NVKMS_MAX_HEADS_PER_DISP; apiHead++) { NvU32 layer; if ((pRequest->disp[sd].requestedHeadsBitMask & - NVBIT(head)) == 0) { + NVBIT(apiHead)) == 0) { continue; } - if (!nvHeadIsActive(pDispEvo, head)) { + if (!nvApiHeadIsActive(pDispEvo, apiHead)) { continue; } - for (layer = 0; layer < pDevEvo->head[head].numLayers; layer++) { - const NvS16 x = pRequest->disp[sd].head[head].layerPosition[layer].x; - const NvS16 y = pRequest->disp[sd].head[head].layerPosition[layer].y; + for (layer = 0; layer < pDevEvo->apiHead[apiHead].numLayers; layer++) { + const NvS16 x = pRequest->disp[sd].head[apiHead].layerPosition[layer].x; + const NvS16 y = pRequest->disp[sd].head[apiHead].layerPosition[layer].y; - if ((pRequest->disp[sd].head[head].requestedLayerBitMask & + if ((pRequest->disp[sd].head[apiHead].requestedLayerBitMask & NVBIT(layer)) == 0x0) { continue; } @@ -4358,47 +5211,36 @@ /* Checks in above block passed, so make the requested changes. */ FOR_ALL_EVO_DISPLAYS(pDispEvo, sd, pDevEvo) { - NvU32 head; + NvU32 apiHead; if ((pRequest->requestedDispsBitMask & NVBIT(sd)) == 0) { continue; } - for (head = 0; head < NVKMS_MAX_HEADS_PER_DISP; head++) { + for (apiHead = 0; apiHead < NVKMS_MAX_HEADS_PER_DISP; apiHead++) { NVEvoUpdateState updateState = { }; - NVEvoSubDevHeadStateRec *pSdHeadState = - &pDevEvo->gpus[sd].headState[head]; NvU32 layer; if ((pRequest->disp[sd].requestedHeadsBitMask & - NVBIT(head)) == 0) { + NVBIT(apiHead)) == 0) { continue; } - if (!nvHeadIsActive(pDispEvo, head)) { + if (!nvApiHeadIsActive(pDispEvo, apiHead)) { continue; } - for (layer = 0; layer < pDevEvo->head[head].numLayers; layer++) { - const NvS16 x = pRequest->disp[sd].head[head].layerPosition[layer].x; - const NvS16 y = pRequest->disp[sd].head[head].layerPosition[layer].y; + for (layer = 0; layer < pDevEvo->apiHead[apiHead].numLayers; layer++) { + const NvS16 x = pRequest->disp[sd].head[apiHead].layerPosition[layer].x; + const NvS16 y = pRequest->disp[sd].head[apiHead].layerPosition[layer].y; - if ((pRequest->disp[sd].head[head].requestedLayerBitMask & + if ((pRequest->disp[sd].head[apiHead].requestedLayerBitMask & NVBIT(layer)) == 0x0) { continue; } - if ((pSdHeadState->layer[layer].outputPosition.x != x) || - (pSdHeadState->layer[layer].outputPosition.y != y)) { - - NVEvoChannelPtr pChannel = pDevEvo->head[head].layer[layer]; - - pSdHeadState->layer[layer].outputPosition.x = x; - pSdHeadState->layer[layer].outputPosition.y = y; - - pDevEvo->hal->SetImmPointOut(pDevEvo, pChannel, sd, - &updateState, x, y); - } + LayerSetPositionOneApiHead(pDispEvo, apiHead, layer, x, y, + &updateState); } pDevEvo->hal->Update(pDevEvo, &updateState, TRUE /* releaseElv */); @@ -4419,49 +5261,71 @@ NvBool nvConstructHwModeTimingsImpCheckEvo( const NVConnectorEvoRec *pConnectorEvo, - NVHwModeTimingsEvoPtr pTimings, + const NVHwModeTimingsEvo *pTimings, + const NvBool enableDsc, + const NvBool b2Heads1Or, + const enum NvKmsDpyAttributeCurrentColorSpaceValue colorSpace, + const enum NvKmsDpyAttributeColorBpcValue colorBpc, const struct NvKmsModeValidationParams *pParams, - NVEvoInfoStringPtr pInfoString, - const int head) + NVHwModeTimingsEvo timings[NVKMS_MAX_HEADS_PER_DISP], + NvU32 *pNumHeads, + NVEvoInfoStringPtr pInfoString) { + NvU32 head; + NvU32 activeRmId; + const NvU32 numHeads = b2Heads1Or ? 2 : 1; NVValidateImpOneDispHeadParamsRec timingsParams[NVKMS_MAX_HEADS_PER_DISP]; NvBool requireBootClocks = !!(pParams->overrides & NVKMS_MODE_VALIDATION_REQUIRE_BOOT_CLOCKS); NvU32 ret; - /* bypass this checking if the user disabled IMP */ + activeRmId = nvRmAllocDisplayId(pConnectorEvo->pDispEvo, + nvAddDpyIdToEmptyDpyIdList(pConnectorEvo->displayId)); + if (activeRmId == 0x0) { + return FALSE; + } + + nvkms_memset(&timingsParams, 0, sizeof(timingsParams)); + + for (head = 0; head < numHeads; head++) { + timingsParams[head].pConnectorEvo = pConnectorEvo; + timingsParams[head].activeRmId = activeRmId; + timingsParams[head].pixelDepth = + nvEvoColorSpaceBpcToPixelDepth(colorSpace, colorBpc); + if (!nvEvoGetSingleTileHwModeTimings(pTimings, numHeads, + &timings[head])) { + ret = FALSE; + goto done; + } + timingsParams[head].pTimings = &timings[head]; + timingsParams[head].enableDsc = enableDsc; + timingsParams[head].b2Heads1Or = b2Heads1Or; + timingsParams[head].pUsage = &timings[head].viewPort.guaranteedUsage; + } + /* bypass this checking if the user disabled IMP */ if ((pParams->overrides & NVKMS_MODE_VALIDATION_NO_EXTENDED_GPU_CAPABILITIES_CHECK) != 0) { - return TRUE; + ret = TRUE; + } else { + ret = nvValidateImpOneDispDowngrade(pConnectorEvo->pDispEvo, timingsParams, + requireBootClocks, + NV_EVO_REALLOCATE_BANDWIDTH_MODE_NONE, + /* downgradePossibleHeadsBitMask */ + (NVBIT(NVKMS_MAX_HEADS_PER_DISP) - 1UL)); } - nvkms_memset(&timingsParams, 0, sizeof(timingsParams)); - - timingsParams[head].pConnectorEvo = pConnectorEvo; - timingsParams[head].activeRmId = - nvRmAllocDisplayId( - pConnectorEvo->pDispEvo, - nvAddDpyIdToEmptyDpyIdList(pConnectorEvo->displayId)); - if (timingsParams[head].activeRmId == 0x0) { - return FALSE; - } - timingsParams[head].pTimings = pTimings; - timingsParams[head].pUsage = &pTimings->viewPort.guaranteedUsage; - - ret = nvValidateImpOneDispDowngrade(pConnectorEvo->pDispEvo, timingsParams, - requireBootClocks, - NV_EVO_REALLOCATE_BANDWIDTH_MODE_NONE, - /* downgradePossibleHeadsBitMask */ - (NVBIT(NVKMS_MAX_HEADS_PER_DISP) - 1UL)); - if (!ret) { + if (ret) { + *pNumHeads = numHeads; + } else { nvEvoLogInfoString(pInfoString, "ViewPort %dx%d exceeds hardware capabilities.", pTimings->viewPort.out.width, pTimings->viewPort.out.height); } - nvRmFreeDisplayId(pConnectorEvo->pDispEvo, timingsParams[head].activeRmId); +done: + nvRmFreeDisplayId(pConnectorEvo->pDispEvo, activeRmId); return ret; } @@ -4683,27 +5547,6 @@ return TRUE; } -/* Query the HDMI 2.1 FRL configuration, if applicable. */ -static NvBool QueryHdmiFrlConfig(const NVDpyEvoRec *pDpyEvo, - const struct - NvKmsModeValidationParams *pParams, - const NvModeTimings *pModeTimings, - NVHwModeTimingsEvoPtr pTimings, - NVEvoInfoStringPtr pInfoString) -{ - /* TODO: apply any overrides from ModeValidationParams. */ - if (!nvHdmiFrlQueryConfig(pDpyEvo, - pModeTimings, - pTimings, - pParams)) { - nvEvoLogInfoString(pInfoString, - "Unable to determine HDMI 2.1 Fixed Rate Link configuration."); - return FALSE; - } - - return TRUE; -} - void nvInitScalingUsageBounds(const NVDevEvoRec *pDevEvo, struct NvKmsScalingUsageBounds *pScaling) { @@ -5162,7 +6005,11 @@ if (pConnectorEvo->or.type == NV0073_CTRL_SPECIFIC_OR_TYPE_SOR) { /* Override protocol if this mode requires HDMI FRL. */ - if (pTimings->hdmiFrlConfig.frlRate != HDMI_FRL_DATA_RATE_NONE) { + if (nvDpyIsHdmiEvo(pDpyEvo) && + nvHdmiTimingsNeedFrl(pDpyEvo, pTimings)) { + if (!nvHdmiDpySupportsFrl(pDpyEvo)) { + return FALSE; + } nvAssert(nvDpyIsHdmiEvo(pDpyEvo)); nvAssert(rmProtocol == NV0073_CTRL_SPECIFIC_OR_PROTOCOL_SOR_SINGLE_TMDS_A || rmProtocol == NV0073_CTRL_SPECIFIC_OR_PROTOCOL_SOR_SINGLE_TMDS_B); @@ -5282,24 +6129,16 @@ ConstructHwModeTimingsFromNvModeTimings(pModeTimings, pTimings); - ret = QueryHdmiFrlConfig(pDpyEvo, pParams, - pModeTimings, pTimings, - pInfoString); - - if (!ret) { - return FALSE; - } - ret = GetDfpProtocol(pDpyEvo, pTimings); if (!ret) { - return FALSE; + return ret; } ret = ApplyDualLinkRequirements(pDpyEvo, pParams, pTimings, pInfoString); if (!ret) { - return FALSE; + return ret; } return ConstructHwModeTimingsViewPort(pDpyEvo->pDispEvo, pTimings, @@ -5307,44 +6146,61 @@ pViewPortOut); } -NvBool nvDowngradeHwModeTimingsDpPixelDepthEvo( - NVHwModeTimingsEvoPtr pTimings, +static NvBool DowngradeColorBpc( const enum NvKmsDpyAttributeCurrentColorSpaceValue colorSpace, - const enum NvKmsDpyAttributeColorRangeValue colorRange) + enum NvKmsDpyAttributeColorBpcValue *pColorBpc, + enum NvKmsDpyAttributeColorRangeValue *pColorRange) { - /* - * In YUV420, HW is programmed with RGB color space and full color range. - * The color space conversion and color range compression happen in a - * headSurface composite shader. - * - * XXX Add support for - * NV_KMS_DPY_ATTRIBUTE_CURRENT_COLOR_SPACE_YCbCr422 over DP. - */ - nvAssert(colorSpace == NV_KMS_DPY_ATTRIBUTE_CURRENT_COLOR_SPACE_YCbCr420 || - colorSpace == NV_KMS_DPY_ATTRIBUTE_CURRENT_COLOR_SPACE_YCbCr444 || - colorSpace == NV_KMS_DPY_ATTRIBUTE_CURRENT_COLOR_SPACE_RGB); - - switch (pTimings->pixelDepth) { - case NVKMS_PIXEL_DEPTH_18_444: - /* Cannot downgrade pixelDepth further. */ - return FALSE; - - case NVKMS_PIXEL_DEPTH_24_444: - /* At depth 18 only RGB and full range are allowed */ - if ((colorSpace != NV_KMS_DPY_ATTRIBUTE_CURRENT_COLOR_SPACE_RGB) || - (colorRange != NV_KMS_DPY_ATTRIBUTE_COLOR_RANGE_FULL)) { + switch (*pColorBpc) { + case NV_KMS_DPY_ATTRIBUTE_CURRENT_COLOR_BPC_10: + *pColorBpc = NV_KMS_DPY_ATTRIBUTE_CURRENT_COLOR_BPC_8; + break; + case NV_KMS_DPY_ATTRIBUTE_CURRENT_COLOR_BPC_8: + /* At depth 18 only RGB and full range are allowed */ + if (colorSpace == NV_KMS_DPY_ATTRIBUTE_CURRENT_COLOR_SPACE_RGB) { + *pColorBpc = NV_KMS_DPY_ATTRIBUTE_CURRENT_COLOR_BPC_6; + *pColorRange = NV_KMS_DPY_ATTRIBUTE_COLOR_RANGE_FULL; + } else { + return FALSE; + } + break; + case NV_KMS_DPY_ATTRIBUTE_CURRENT_COLOR_BPC_UNKNOWN: + case NV_KMS_DPY_ATTRIBUTE_CURRENT_COLOR_BPC_6: return FALSE; - } - pTimings->pixelDepth = NVKMS_PIXEL_DEPTH_18_444; - break; - case NVKMS_PIXEL_DEPTH_30_444: - pTimings->pixelDepth = NVKMS_PIXEL_DEPTH_24_444; - break; } return TRUE; } +NvBool nvDowngradeColorSpaceAndBpc( + const NVColorFormatInfoRec *pSupportedColorFormats, + enum NvKmsDpyAttributeCurrentColorSpaceValue *pColorSpace, + enum NvKmsDpyAttributeColorBpcValue *pColorBpc, + enum NvKmsDpyAttributeColorRangeValue *pColorRange) +{ + if (DowngradeColorBpc(*pColorSpace, pColorBpc, pColorRange)) { + return TRUE; + } + + switch (*pColorSpace) { + case NV_KMS_DPY_ATTRIBUTE_CURRENT_COLOR_SPACE_RGB: /* fallthrough */ + case NV_KMS_DPY_ATTRIBUTE_CURRENT_COLOR_SPACE_YCbCr444: + if (pSupportedColorFormats->yuv422.maxBpc != + NV_KMS_DPY_ATTRIBUTE_CURRENT_COLOR_BPC_UNKNOWN) { + *pColorSpace = NV_KMS_DPY_ATTRIBUTE_CURRENT_COLOR_SPACE_YCbCr422; + *pColorBpc = pSupportedColorFormats->yuv422.maxBpc; + *pColorRange = NV_KMS_DPY_ATTRIBUTE_COLOR_RANGE_LIMITED; + return TRUE; + } + break; + case NV_KMS_DPY_ATTRIBUTE_CURRENT_COLOR_SPACE_YCbCr422: /* fallthrough */ + case NV_KMS_DPY_ATTRIBUTE_CURRENT_COLOR_SPACE_YCbCr420: + break; + } + + return FALSE; +} + /* * nvDPValidateModeEvo() - For DP devices handled by the DP lib, check DP * bandwidth and pick the best possible/supported pixel depth to use for @@ -5353,19 +6209,18 @@ NvBool nvDPValidateModeEvo(NVDpyEvoPtr pDpyEvo, NVHwModeTimingsEvoPtr pTimings, + enum NvKmsDpyAttributeCurrentColorSpaceValue *pColorSpace, + enum NvKmsDpyAttributeColorBpcValue *pColorBpc, + const NvBool b2Heads1Or, + NVDscInfoEvoRec *pDscInfo, const struct NvKmsModeValidationParams *pParams) { NVConnectorEvoPtr pConnectorEvo = pDpyEvo->pConnectorEvo; - /* XXX Add support for - * NV_KMS_DPY_ATTRIBUTE_CURRENT_COLOR_SPACE_YCbCr422 over DP. */ - const enum NvKmsDpyAttributeCurrentColorSpaceValue colorSpace = - (pTimings->yuv420Mode != NV_YUV420_MODE_NONE) ? - NV_KMS_DPY_ATTRIBUTE_CURRENT_COLOR_SPACE_YCbCr420 : - NV_KMS_DPY_ATTRIBUTE_CURRENT_COLOR_SPACE_RGB; - const enum NvKmsDpyAttributeColorRangeValue colorRange = - (colorSpace == NV_KMS_DPY_ATTRIBUTE_CURRENT_COLOR_SPACE_RGB) ? - NV_KMS_DPY_ATTRIBUTE_COLOR_RANGE_FULL : - NV_KMS_DPY_ATTRIBUTE_COLOR_RANGE_LIMITED; + enum NvKmsDpyAttributeCurrentColorSpaceValue colorSpace = *pColorSpace; + enum NvKmsDpyAttributeColorBpcValue colorBpc = *pColorBpc; + enum NvKmsDpyAttributeColorRangeValue colorRange; + const NVColorFormatInfoRec supportedColorFormats = + nvGetColorFormatInfo(pDpyEvo); /* Only do this for DP devices. */ if (!nvConnectorUsesDPLib(pConnectorEvo)) { @@ -5377,18 +6232,21 @@ return TRUE; } + if (colorSpace != NV_KMS_DPY_ATTRIBUTE_CURRENT_COLOR_SPACE_RGB) { + colorRange = NV_KMS_DPY_ATTRIBUTE_COLOR_RANGE_LIMITED; + } else { + colorRange = NV_KMS_DPY_ATTRIBUTE_COLOR_RANGE_FULL; + } + nvAssert(nvDpyUsesDPLib(pDpyEvo)); nvAssert(pConnectorEvo->or.type == NV0073_CTRL_SPECIFIC_OR_TYPE_SOR); - nvAssert(pTimings->pixelDepth == NVKMS_PIXEL_DEPTH_30_444 || - pTimings->pixelDepth == NVKMS_PIXEL_DEPTH_24_444 || - pTimings->pixelDepth == NVKMS_PIXEL_DEPTH_18_444); - tryAgain: - if (!nvDPValidateModeForDpyEvo(pDpyEvo, colorSpace, pParams, pTimings)) { - if (nvDowngradeHwModeTimingsDpPixelDepthEvo(pTimings, - colorSpace, colorRange)) { + if (!nvDPValidateModeForDpyEvo(pDpyEvo, colorSpace, colorBpc, pParams, + pTimings, b2Heads1Or, pDscInfo)) { + if (nvDowngradeColorSpaceAndBpc(&supportedColorFormats, &colorSpace, + &colorBpc, &colorRange)) { goto tryAgain; } /* @@ -5399,11 +6257,11 @@ return FALSE; } + *pColorSpace = colorSpace; + *pColorBpc = colorBpc; return TRUE; } - - /* * Construct the hardware values to program EVO for the specified * NVModeTimings @@ -5450,54 +6308,6 @@ TweakTimingsForGsync(pDpyEvo, pTimings, pInfoString, pParams->stereoMode); } - /* Defaults, should match EVO displayClass_02.mfs values for _DEFAULT */ - if (pConnectorEvo->legacyType == NV0073_CTRL_SPECIFIC_DISPLAY_TYPE_CRT) { - pTimings->pixelDepth = NVKMS_PIXEL_DEPTH_30_444; - } else if (pConnectorEvo->legacyType == - NV0073_CTRL_SPECIFIC_DISPLAY_TYPE_DFP) { - - if (pConnectorEvo->signalFormat == NVKMS_CONNECTOR_SIGNAL_FORMAT_DSI) { - switch (pDpyEvo->parsedEdid.info.input.u.digital.bpc) { - case 10: - pTimings->pixelDepth = NVKMS_PIXEL_DEPTH_30_444; - break; - case 6: - pTimings->pixelDepth = NVKMS_PIXEL_DEPTH_18_444; - break; - default: - nvAssert(!"Invalid Pixel Depth for DSI"); - // fall through - case 8: - pTimings->pixelDepth = NVKMS_PIXEL_DEPTH_24_444; - break; - } - } else if (nvConnectorUsesDPLib(pDpyEvo->pConnectorEvo)) { - // Pick displayport pixel depths for raster timings. - // Start off picking best possible depth based on monitor caps - // If the monitor doesn't have an EDID version 1.4 or higher, assume - // it's 8. - if (pDpyEvo->parsedEdid.valid && - pDpyEvo->parsedEdid.info.input.isDigital && - pDpyEvo->parsedEdid.info.version >= NVT_EDID_VER_1_4) { - if (pDpyEvo->parsedEdid.info.input.u.digital.bpc >= 10) { - pTimings->pixelDepth = NVKMS_PIXEL_DEPTH_30_444; - } else if (pDpyEvo->parsedEdid.info.input.u.digital.bpc < 8) { - pTimings->pixelDepth = NVKMS_PIXEL_DEPTH_18_444; - } else { - pTimings->pixelDepth = NVKMS_PIXEL_DEPTH_24_444; - } - } else { - pTimings->pixelDepth = NVKMS_PIXEL_DEPTH_24_444; - } - } else { - /* TMDS default */ - pTimings->pixelDepth = NVKMS_PIXEL_DEPTH_24_444; - } - } - - pTimings->stereo.mode = pParams->stereoMode; - pTimings->stereo.isAegis = pDpyEvo->stereo3DVision.isAegis; - return TRUE; } @@ -6061,6 +6871,9 @@ } pImpInput->head[head].pTimings = timingsParams[head].pTimings; + pImpInput->head[head].enableDsc = timingsParams[head].enableDsc; + pImpInput->head[head].b2Heads1Or = timingsParams[head].b2Heads1Or; + pImpInput->head[head].pixelDepth = timingsParams[head].pixelDepth; pImpInput->head[head].displayId = timingsParams[head].activeRmId; pImpInput->head[head].orType = pConnectorEvo->or.type; pImpInput->head[head].pUsage = timingsParams[head].pUsage; @@ -6069,10 +6882,9 @@ NV0073_CTRL_SYSTEM_CAPS_CROSS_BAR_SUPPORTED) || pConnectorEvo->or.type != NV0073_CTRL_SPECIFIC_OR_TYPE_SOR) { - nvAssert(pConnectorEvo->or.mask != 0x0); + nvAssert(pConnectorEvo->or.primary != NV_INVALID_OR); - pImpInput->head[head].orIndex = - nvEvoConnectorGetPrimaryOr(pConnectorEvo); + pImpInput->head[head].orIndex = pConnectorEvo->or.primary; continue; } @@ -6441,16 +7253,47 @@ } } /* GetRasterLockPin */ -static NvU32 -UpdateLUTTimer(NVDispEvoPtr pDispEvo, const NvU32 head, NvBool baseLutEnabled, - NvBool outputLutEnabled) +static void EvoIncrementCurrentLutIndex(NVDispEvoRec *pDispEvo, + const NvU32 apiHead, + const NvBool baseLutEnabled, + const NvBool outputLutEnabled) { - NVDevEvoPtr pDevEvo = pDispEvo->pDevEvo; + NvU32 head; const int dispIndex = pDispEvo->displayOwner; - const int numLUTs = ARRAY_LEN(pDevEvo->lut.head[head].LUT); + NVDevEvoRec *pDevEvo = pDispEvo->pDevEvo; + const int numLUTs = ARRAY_LEN(pDevEvo->lut.apiHead[apiHead].LUT); + NVDispApiHeadStateEvoRec *pApiHeadState = + &pDispEvo->apiHeadState[apiHead]; + + pDevEvo->lut.apiHead[apiHead].disp[dispIndex].curLUTIndex++; + pDevEvo->lut.apiHead[apiHead].disp[dispIndex].curLUTIndex %= numLUTs; + pDevEvo->lut.apiHead[apiHead].disp[dispIndex].curBaseLutEnabled = baseLutEnabled; + pDevEvo->lut.apiHead[apiHead].disp[dispIndex].curOutputLutEnabled = outputLutEnabled; + + FOR_EACH_EVO_HW_HEAD_IN_MASK(pApiHeadState->hwHeadsMask, head) { + const NvU32 curLutIndex = + pDevEvo->lut.apiHead[apiHead].disp[dispIndex].curLUTIndex; + NVDispHeadStateEvoRec *pHeadState = &pDispEvo->headState[head]; + + pHeadState->lut.outputLutEnabled = + pDevEvo->lut.apiHead[apiHead].disp[dispIndex].curOutputLutEnabled; + pHeadState->lut.baseLutEnabled = + pDevEvo->lut.apiHead[apiHead].disp[dispIndex].curBaseLutEnabled; + pHeadState->lut.pCurrSurface = + pDevEvo->lut.apiHead[apiHead].LUT[curLutIndex]; + + } +} + +static NvU32 UpdateLUTTimer(NVDispEvoPtr pDispEvo, + const NvU32 apiHead, + const NvBool baseLutEnabled, + const NvBool outputLutEnabled) +{ + NVDevEvoPtr pDevEvo = pDispEvo->pDevEvo; if (!pDevEvo->hal->IsCompNotifierComplete(pDispEvo, - LUTNotifierForHead(head))) { + LUTNotifierForApiHead(apiHead))) { // If the notifier is still pending, then the previous update is still // pending and further LUT changes should continue to go into the third // buffer. Reschedule the timer for another 10 ms. @@ -6458,12 +7301,10 @@ } // Update the current LUT index and kick off an update. - pDevEvo->lut.head[head].disp[dispIndex].curLUTIndex++; - pDevEvo->lut.head[head].disp[dispIndex].curLUTIndex %= numLUTs; - pDevEvo->lut.head[head].disp[dispIndex].curBaseLutEnabled = baseLutEnabled; - pDevEvo->lut.head[head].disp[dispIndex].curOutputLutEnabled = outputLutEnabled; + EvoIncrementCurrentLutIndex(pDispEvo, apiHead, baseLutEnabled, + outputLutEnabled); - nvEvoUpdateCurrentPalette(pDispEvo, head, TRUE); + EvoUpdateCurrentPalette(pDispEvo, apiHead); // Return 0 to cancel the timer. return 0; @@ -6472,31 +7313,31 @@ static void UpdateLUTTimerNVKMS(void *dataPtr, NvU32 dataU32) { NVDispEvoPtr pDispEvo = dataPtr; - const NvU32 head = DRF_VAL(UPDATE_LUT_TIMER_NVKMS, _DATAU32, _HEAD, + const NvU32 apiHead = DRF_VAL(UPDATE_LUT_TIMER_NVKMS, _DATAU32, _HEAD, dataU32); const NvBool baseLutEnabled = FLD_TEST_DRF(UPDATE_LUT_TIMER_NVKMS, _DATAU32, _BASE_LUT, _ENABLE, dataU32); const NvBool outputLutEnabled = FLD_TEST_DRF(UPDATE_LUT_TIMER_NVKMS, _DATAU32, _OUTPUT_LUT, _ENABLE, dataU32); - NvU32 ret = UpdateLUTTimer(pDispEvo, head, baseLutEnabled, + NvU32 ret = UpdateLUTTimer(pDispEvo, apiHead, baseLutEnabled, outputLutEnabled); if (ret != 0) { - ScheduleLutUpdate(pDispEvo, head, dataU32, ret * 1000); + ScheduleLutUpdate(pDispEvo, apiHead, dataU32, ret * 1000); } } static void ScheduleLutUpdate(NVDispEvoRec *pDispEvo, - const NvU32 head, const NvU32 data, + const NvU32 apiHead, const NvU32 data, const NvU64 usec) { NVDevEvoRec *pDevEvo = pDispEvo->pDevEvo; /* Cancel previous update */ - nvCancelLutUpdateEvo(pDispEvo, head); + nvCancelLutUpdateEvo(pDispEvo, apiHead); /* schedule a new timer */ - pDevEvo->lut.head[head].disp[pDispEvo->displayOwner].updateTimer = + pDevEvo->lut.apiHead[apiHead].disp[pDispEvo->displayOwner].updateTimer = nvkms_alloc_timer(UpdateLUTTimerNVKMS, pDispEvo, data, usec); @@ -6513,7 +7354,6 @@ static NVEvoLutDataRec *GetNewLutBuffer( const NVDispEvoRec *pDispEvo, - NvU32 head, const struct NvKmsSetLutCommonParams *pParams) { const NVDevEvoRec *pDevEvo = pDispEvo->pDevEvo; @@ -6590,7 +7430,7 @@ /* - * Update the head's LUT with the given colors. + * Update the api head's LUT with the given colors. * * The color LUT is triple-buffered. * @@ -6611,21 +7451,21 @@ * kick off an update. No new timer needs to be scheduled. */ -void nvEvoSetLut(NVDispEvoPtr pDispEvo, NvU32 head, NvBool kickoff, +void nvEvoSetLut(NVDispEvoPtr pDispEvo, NvU32 apiHead, NvBool kickoff, const struct NvKmsSetLutCommonParams *pParams) { NVDevEvoPtr pDevEvo = pDispEvo->pDevEvo; const int dispIndex = pDispEvo->displayOwner; - const int curLUT = pDevEvo->lut.head[head].disp[dispIndex].curLUTIndex; + const int curLUT = pDevEvo->lut.apiHead[apiHead].disp[dispIndex].curLUTIndex; const NvBool waitForPreviousUpdate = - pDevEvo->lut.head[head].disp[dispIndex].waitForPreviousUpdate; - const int numLUTs = ARRAY_LEN(pDevEvo->lut.head[head].LUT); + pDevEvo->lut.apiHead[apiHead].disp[dispIndex].waitForPreviousUpdate; + const int numLUTs = ARRAY_LEN(pDevEvo->lut.apiHead[apiHead].LUT); const int lutToFill = (curLUT + 1) % numLUTs; - NVLutSurfaceEvoPtr pSurfEvo = pDevEvo->lut.head[head].LUT[lutToFill]; + NVLutSurfaceEvoPtr pSurfEvo = pDevEvo->lut.apiHead[apiHead].LUT[lutToFill]; NvBool baseLutEnabled = - pDevEvo->lut.head[head].disp[dispIndex].curBaseLutEnabled ; + pDevEvo->lut.apiHead[apiHead].disp[dispIndex].curBaseLutEnabled ; NvBool outputLutEnabled = - pDevEvo->lut.head[head].disp[dispIndex].curOutputLutEnabled; + pDevEvo->lut.apiHead[apiHead].disp[dispIndex].curOutputLutEnabled; if (!pParams->input.specified && !pParams->output.specified) { return; @@ -6643,7 +7483,7 @@ if ((pParams->input.specified && pParams->input.end != 0) || (pParams->output.specified && pParams->output.enabled)) { - NVEvoLutDataRec *pLUTBuffer = GetNewLutBuffer(pDispEvo, head, pParams); + NVEvoLutDataRec *pLUTBuffer = GetNewLutBuffer(pDispEvo, pParams); if (pLUTBuffer == NULL) { nvEvoLogDev(pDevEvo, EVO_LOG_WARN, @@ -6658,12 +7498,11 @@ } /* Kill a pending timer */ - nvCancelLutUpdateEvo(pDispEvo, head); + nvCancelLutUpdateEvo(pDispEvo, apiHead); if (!kickoff) { - pDevEvo->lut.head[head].disp[dispIndex].curBaseLutEnabled = baseLutEnabled; - pDevEvo->lut.head[head].disp[dispIndex].curOutputLutEnabled = outputLutEnabled; - pDevEvo->lut.head[head].disp[dispIndex].curLUTIndex = lutToFill; + EvoIncrementCurrentLutIndex(pDispEvo, apiHead, baseLutEnabled, + outputLutEnabled); return; } @@ -6673,31 +7512,30 @@ // is synchronous. NvBool previousUpdateComplete = pDevEvo->hal->IsCompNotifierComplete(pDispEvo, - LUTNotifierForHead(head)); + LUTNotifierForApiHead(apiHead)); if (!waitForPreviousUpdate || previousUpdateComplete || pParams->synchronous) { // Kick off an update now. - pDevEvo->lut.head[head].disp[dispIndex].curLUTIndex = lutToFill; - pDevEvo->lut.head[head].disp[dispIndex].curBaseLutEnabled = baseLutEnabled; - pDevEvo->lut.head[head].disp[dispIndex].curOutputLutEnabled = outputLutEnabled; - nvEvoUpdateCurrentPalette(pDispEvo, head, TRUE); + EvoIncrementCurrentLutIndex(pDispEvo, apiHead, baseLutEnabled, + outputLutEnabled); + EvoUpdateCurrentPalette(pDispEvo, apiHead); // If this LUT update is synchronous, then sync before returning. if (pParams->synchronous && - pDevEvo->lut.head[head].disp[dispIndex].waitForPreviousUpdate) { + pDevEvo->lut.apiHead[apiHead].disp[dispIndex].waitForPreviousUpdate) { pDevEvo->hal->WaitForCompNotifier(pDispEvo, - LUTNotifierForHead(head)); - pDevEvo->lut.head[head].disp[dispIndex].waitForPreviousUpdate = + LUTNotifierForApiHead(apiHead)); + pDevEvo->lut.apiHead[apiHead].disp[dispIndex].waitForPreviousUpdate = FALSE; } } else { // Schedule a timer to kick off an update later. // XXX 5 ms is a guess. We could probably look at this pDpy's refresh // rate to come up with a more reasonable estimate. - NvU32 dataU32 = DRF_NUM(UPDATE_LUT_TIMER_NVKMS, _DATAU32, _HEAD, head); + NvU32 dataU32 = DRF_NUM(UPDATE_LUT_TIMER_NVKMS, _DATAU32, _HEAD, apiHead); - nvAssert((head & ~0xff) == 0); + nvAssert((apiHead & ~0xff) == 0); if (baseLutEnabled) { dataU32 |= DRF_DEF(UPDATE_LUT_TIMER_NVKMS, _DATAU32, _BASE_LUT, @@ -6709,7 +7547,7 @@ _ENABLE); } - ScheduleLutUpdate(pDispEvo, head, dataU32, 5 * 1000); + ScheduleLutUpdate(pDispEvo, apiHead, dataU32, 5 * 1000); } } @@ -7110,12 +7948,12 @@ // Note that we use pDev and subdevice here instead of pDisp since this is used // per-subdev in SLI (including the pDispEvo->numSubDevices > 1 case). // -static NvBool EvoWaitForLock(NVDevEvoPtr pDevEvo, - NvU32 sd, NvU32 head, NvU32 type) +static NvBool EvoWaitForLock(const NVDevEvoRec *pDevEvo, const NvU32 sd, + const NvU32 head, const NvU32 type, + NvU64 *pStartTime) { NV5070_CTRL_CMD_GET_RG_STATUS_PARAMS status = { }; NvU32 ret; - NvU64 startTime = 0; nvAssert(type == EVO_RASTER_LOCK || type == EVO_FLIP_LOCK); @@ -7153,7 +7991,7 @@ break; } - if (nvExceedsTimeoutUSec(&startTime, LOCK_TIMEOUT)) { + if (nvExceedsTimeoutUSec(pStartTime, LOCK_TIMEOUT)) { nvEvoLogDev(pDevEvo, EVO_LOG_ERROR, "SLI lock timeout exceeded (type %d)", type); return FALSE; @@ -7286,7 +8124,7 @@ dma, pConnectorEvo, pTimings->protocol, - nvEvoConnectorGetPrimaryOr(pConnectorEvo), + pConnectorEvo->or.primary, head, pDispEvo->displayOwner, &updateState); @@ -7331,9 +8169,14 @@ if (pConnectorEvo != NULL && pConnectorEvo->or.type == NV0073_CTRL_SPECIFIC_OR_TYPE_SOR) { - nvAssert(pConnectorEvo->or.mask != 0x0); - - activeSorMask |= pConnectorEvo->or.mask; + NvU32 orIndex; + nvAssert(pConnectorEvo->or.primary != NV_INVALID_OR); + FOR_EACH_INDEX_IN_MASK(32, orIndex, nvConnectorGetORMaskEvo(pConnectorEvo)) { + if (pConnectorEvo->or.ownerHeadMask[orIndex] == 0x0) { + continue; + } + activeSorMask |= NVBIT(orIndex); + } FOR_EACH_INDEX_IN_MASK_END; } } @@ -7392,7 +8235,7 @@ NvBool reTrain) { const NvU32 displayId = nvDpyIdToNvU32(pConnectorEvo->displayId); - const NvU32 sorNumber = nvEvoConnectorGetPrimaryOr(pConnectorEvo); + const NvU32 sorNumber = pConnectorEvo->or.primary; const NvU32 headMask = nvConnectorGetAttachedHeadMaskEvo(pConnectorEvo); NvBool force = NV_FALSE; NVDevEvoPtr pDevEvo = pDispEvo->pDevEvo; @@ -7548,7 +8391,7 @@ } } -NvBool nvIsHDRCapableHead(NVDispEvoPtr pDispEvo, +NvBool nvIsHDRCapableHead(const NVDispEvoRec *pDispEvo, NvU32 apiHead) { const NVDpyEvoRec *pDpyEvo; @@ -7682,3 +8525,258 @@ return TRUE; } + +enum nvKmsPixelDepth nvEvoColorSpaceBpcToPixelDepth( + const enum NvKmsDpyAttributeCurrentColorSpaceValue colorSpace, + const enum NvKmsDpyAttributeColorBpcValue colorBpc) +{ + switch (colorSpace) { + case NV_KMS_DPY_ATTRIBUTE_CURRENT_COLOR_SPACE_RGB: + case NV_KMS_DPY_ATTRIBUTE_CURRENT_COLOR_SPACE_YCbCr444: + case NV_KMS_DPY_ATTRIBUTE_CURRENT_COLOR_SPACE_YCbCr420: + switch (colorBpc) { + case NV_KMS_DPY_ATTRIBUTE_CURRENT_COLOR_BPC_10: + return NVKMS_PIXEL_DEPTH_30_444; + case NV_KMS_DPY_ATTRIBUTE_CURRENT_COLOR_BPC_8: + return NVKMS_PIXEL_DEPTH_24_444; + case NV_KMS_DPY_ATTRIBUTE_CURRENT_COLOR_BPC_UNKNOWN: /* fallthrough */ + case NV_KMS_DPY_ATTRIBUTE_CURRENT_COLOR_BPC_6: + return NVKMS_PIXEL_DEPTH_18_444; + } + break; + case NV_KMS_DPY_ATTRIBUTE_CURRENT_COLOR_SPACE_YCbCr422: + nvAssert(colorBpc != NV_KMS_DPY_ATTRIBUTE_CURRENT_COLOR_BPC_6); + switch (colorBpc) { + case NV_KMS_DPY_ATTRIBUTE_CURRENT_COLOR_BPC_10: + return NVKMS_PIXEL_DEPTH_20_422; + case NV_KMS_DPY_ATTRIBUTE_CURRENT_COLOR_BPC_6: /* fallthrough */ + case NV_KMS_DPY_ATTRIBUTE_CURRENT_COLOR_BPC_UNKNOWN: /* fallthrough */ + case NV_KMS_DPY_ATTRIBUTE_CURRENT_COLOR_BPC_8: + return NVKMS_PIXEL_DEPTH_16_422; + } + break; + } + + return NVKMS_PIXEL_DEPTH_18_444; +} + +void nvEvoEnableMergeModePreModeset(NVDispEvoRec *pDispEvo, + const NvU32 headsMask, + NVEvoUpdateState *pUpdateState) +{ + const NVDevEvoRec *pDevEvo = pDispEvo->pDevEvo; + const NvU32 sd = pDispEvo->displayOwner; + const NvU32 primaryHead = nvGetPrimaryHwHeadFromMask(headsMask); + NvU32 head; + + nvAssert(pDevEvo->hal->caps.supportsMergeMode); + nvAssert((nvPopCount32(headsMask) > 1) && + (primaryHead != NV_INVALID_HEAD)); + + FOR_EACH_EVO_HW_HEAD_IN_MASK(headsMask, head) { + NVDispHeadStateEvoRec *pHeadState = &pDispEvo->headState[head]; + const NVHwModeTimingsEvo *pTimings = &pHeadState->timings; + NVEvoHeadControl *pHC = + &pDevEvo->gpus[sd].headControl[head]; + + nvAssert(pHeadState->mergeMode == + NV_EVO_MERGE_MODE_DISABLED); + + /* + * Heads requires to be raster locked before they transition to + * PRIMARY/SECONDARY merge mode. + * + * SETUP should be the intermediate state before head transition to + * PRIMARY/SECONDARY merge mode. During SETUP state, there is no pixel + * transmission from secondary to primary head, RG fetches and drops + * pixels, viewport gets filled by the special gray/black pixels. + */ + pHeadState->mergeMode = NV_EVO_MERGE_MODE_SETUP; + pDevEvo->hal->SetMergeMode(pDispEvo, head, pHeadState->mergeMode, + pUpdateState); + + nvAssert((pHC->serverLock == NV_EVO_NO_LOCK) && + (pHC->clientLock == NV_EVO_NO_LOCK)); + + if (head == primaryHead) { + pHC->serverLock = NV_EVO_RASTER_LOCK; + pHC->serverLockPin = NV_EVO_LOCK_PIN_INTERNAL(primaryHead); + pHC->setLockOffsetX = TRUE; + } else { + pHC->clientLock = NV_EVO_RASTER_LOCK; + pHC->clientLockPin = NV_EVO_LOCK_PIN_INTERNAL(primaryHead); + if (pTimings->vrr.type != NVKMS_DPY_VRR_TYPE_NONE) { + pHC->clientLockoutWindow = 4; + pHC->useStallLockPin = TRUE; + pHC->stallLockPin = NV_EVO_LOCK_PIN_INTERNAL(primaryHead); + } else { + pHC->clientLockoutWindow = 2; + } + } + + if (pTimings->vrr.type != NVKMS_DPY_VRR_TYPE_NONE) { + pHC->crashLockUnstallMode = TRUE; + } + pHC->stereoLocked = FALSE; + + EvoUpdateHeadParams(pDispEvo, head, pUpdateState); + } +} + +void nvEvoEnableMergeModePostModeset(NVDispEvoRec *pDispEvo, + const NvU32 headsMask, + NVEvoUpdateState *pUpdateState) +{ + const NVDevEvoRec *pDevEvo = pDispEvo->pDevEvo; + const NvU32 sd = pDispEvo->displayOwner; + const NvU32 primaryHead = nvGetPrimaryHwHeadFromMask(headsMask); + NvU64 startTime = 0; + NvU32 head; + + nvAssert(pDevEvo->hal->caps.supportsMergeMode); + nvAssert((nvPopCount32(headsMask) > 1) && + (primaryHead != NV_INVALID_HEAD)); + + FOR_EACH_EVO_HW_HEAD_IN_MASK(headsMask, head) { + nvAssert(pDispEvo->headState[head].mergeMode == + NV_EVO_MERGE_MODE_SETUP); + + if (!EvoWaitForLock(pDevEvo, sd, head, EVO_RASTER_LOCK, + &startTime)) { + nvEvoLogDispDebug(pDispEvo, EVO_LOG_ERROR, "Raster lock timeout"); + return; + } + } + + FOR_EACH_EVO_HW_HEAD_IN_MASK(headsMask, head) { + NVDispHeadStateEvoRec *pHeadState = &pDispEvo->headState[head]; + NVEvoHeadControl *pHC = &pDevEvo->gpus[sd].headControl[head]; + + pHC->flipLockPin = NV_EVO_LOCK_PIN_INTERNAL(primaryHead); + pHC->flipLock = TRUE; + + EvoUpdateHeadParams(pDispEvo, head, pUpdateState); + + pHeadState->mergeMode = (head == primaryHead) ? + NV_EVO_MERGE_MODE_PRIMARY : NV_EVO_MERGE_MODE_SECONDARY; + pDevEvo->hal->SetMergeMode(pDispEvo, head, pHeadState->mergeMode, + pUpdateState); + } +} + +void nvEvoDisableMergeMode(NVDispEvoRec *pDispEvo, + const NvU32 headsMask, + NVEvoUpdateState *pUpdateState) +{ + const NVDevEvoRec *pDevEvo = pDispEvo->pDevEvo; + const NvU32 sd = pDispEvo->displayOwner; + NvU32 head; + + nvAssert(pDevEvo->hal->caps.supportsMergeMode); + nvAssert(nvPopCount32(headsMask) > 1); + + FOR_EACH_EVO_HW_HEAD_IN_MASK(headsMask, head) { + NVDispHeadStateEvoRec *pHeadState = &pDispEvo->headState[head]; + NVEvoHeadControl *pHC = + &pDevEvo->gpus[sd].headControl[head]; + + pHeadState->mergeMode = NV_EVO_MERGE_MODE_DISABLED; + pDevEvo->hal->SetMergeMode(pDispEvo, head, pHeadState->mergeMode, + pUpdateState); + + pHC->serverLock = NV_EVO_NO_LOCK; + pHC->serverLockPin = NV_EVO_LOCK_PIN_INTERNAL(0); + pHC->clientLock = NV_EVO_NO_LOCK; + pHC->clientLockPin = NV_EVO_LOCK_PIN_INTERNAL(0); + pHC->clientLockoutWindow = 0; + pHC->setLockOffsetX = FALSE; + pHC->flipLockPin = NV_EVO_LOCK_PIN_INTERNAL(0); + pHC->flipLock = FALSE; + pHC->useStallLockPin = FALSE; + pHC->stallLockPin = NV_EVO_LOCK_PIN_INTERNAL(0); + pHC->crashLockUnstallMode = FALSE; + + + EvoUpdateHeadParams(pDispEvo, head, pUpdateState); + } +} + +NvBool nvEvoGetSingleTileHwModeTimings(const NVHwModeTimingsEvo *pSrc, + const NvU32 numTiles, + NVHwModeTimingsEvo *pDst) +{ + if (numTiles == 1) { + *pDst = *pSrc; + return TRUE; + } + + if ((numTiles == 0) || + (pSrc->viewPort.out.xAdjust != 0) || + (pSrc->viewPort.out.width != nvEvoVisibleWidth(pSrc))) { + return FALSE; + } + + if (((pSrc->rasterSize.x % numTiles) != 0) || + (((pSrc->rasterSyncEnd.x + 1) % numTiles) != 0) || + (((pSrc->rasterBlankEnd.x + 1) % numTiles) != 0) || + (((pSrc->rasterBlankStart.x + 1) % numTiles) != 0) || + ((pSrc->pixelClock % numTiles) != 0) || + ((pSrc->viewPort.in.width % numTiles) != 0)) { + return FALSE; + } + + *pDst = *pSrc; + + pDst->rasterSize.x /= numTiles; + pDst->rasterSyncEnd.x /= numTiles; + pDst->rasterBlankEnd.x /= numTiles; + pDst->rasterBlankStart.x /= numTiles; + + pDst->pixelClock /= numTiles; + + pDst->viewPort.out.width /= numTiles; + pDst->viewPort.in.width /= numTiles; + + return TRUE; +} + +NvBool nvEvoUse2Heads1OR(const NVDpyEvoRec *pDpyEvo, + const NVHwModeTimingsEvo *pTimings, + const struct NvKmsModeValidationParams *pParams) +{ + const NVDispEvoRec *pDispEvo = pDpyEvo->pDispEvo; + const NvU32 sd = pDispEvo->displayOwner; + const NVEvoHeadCaps *pHeadCaps = + &pDispEvo->pDevEvo->gpus[sd].capabilities.head[0]; + + /* The 2Heads1OR mode can not be used if GPU does not + * support merge mode, or */ + if (!pDispEvo->pDevEvo->hal->caps.supportsMergeMode || + /* the 2Heads1OR mode is forced disabled by client, or */ + ((pParams->overrides & + NVKMS_MODE_VALIDATION_MAX_ONE_HARDWARE_HEAD) != 0) || + /* the given dpy does not support the display stream compression + * and the given mode timings are not using the hardware YUV420 + * packer, or */ + (!nvDPDpyIsDscPossible(pDpyEvo) && !nvHdmiDpySupportsDsc(pDpyEvo) && + (pTimings->yuv420Mode != NV_YUV420_MODE_HW)) || + /* the non-centered viewport out does not work with 2Heads1OR mode + * an for simplicity disable all customized viewport out, or */ + (pTimings->viewPort.out.width != nvEvoVisibleWidth(pTimings)) || + (pTimings->viewPort.out.xAdjust != 0) || + /* either HVisible, HSyncWidth, HBackPorch, HForntPorch, + * pixelClock, or viewPortIn width is odd and can not be split + * equally across two heads, or */ + ((pTimings->rasterSize.x & 1 ) != 0) || + ((pTimings->rasterSyncEnd.x & 1) != 1) || + ((pTimings->rasterBlankEnd.x & 1) != 1) || + ((pTimings->rasterBlankStart.x & 1) != 1) || + ((pTimings->pixelClock & 1) != 0) || + ((pTimings->viewPort.in.width & 1) != 0)) { + return FALSE; + } + + /* Use 2Heads1OR mode only if the required pixel clock is greater than the + * maximum pixel clock support by a head. */ + return (pTimings->pixelClock > pHeadCaps->maxPClkKHz); +} diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia-modeset/src/nvkms-evo1.c nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia-modeset/src/nvkms-evo1.c --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia-modeset/src/nvkms-evo1.c 2023-10-25 20:22:39.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia-modeset/src/nvkms-evo1.c 2024-03-05 22:12:21.000000000 +0000 @@ -94,6 +94,7 @@ static void AssignPerHeadImpParams(const NVDevEvoRec *pDevEvo, NV5070_CTRL_CMD_IS_MODE_POSSIBLE_PARAMS *pImp, const NVHwModeTimingsEvo *pTimings, + const enum nvKmsPixelDepth pixelDepth, const struct NvKmsUsageBounds *pUsage, const int head, const int orNumber, @@ -312,7 +313,7 @@ /* pixel depth */ - switch (pTimings->pixelDepth) { + switch (pixelDepth) { case NVKMS_PIXEL_DEPTH_18_444: pImp->Head[head].outputResourcePixelDepthBPP = NV5070_CTRL_IS_MODE_POSSIBLE_OUTPUT_RESOURCE_PIXEL_DEPTH_BPP_18_444; @@ -325,6 +326,14 @@ pImp->Head[head].outputResourcePixelDepthBPP = NV5070_CTRL_IS_MODE_POSSIBLE_OUTPUT_RESOURCE_PIXEL_DEPTH_BPP_30_444; break; + case NVKMS_PIXEL_DEPTH_16_422: + pImp->Head[head].outputResourcePixelDepthBPP = + NV5070_CTRL_IS_MODE_POSSIBLE_OUTPUT_RESOURCE_PIXEL_DEPTH_BPP_16_422; + break; + case NVKMS_PIXEL_DEPTH_20_422: + pImp->Head[head].outputResourcePixelDepthBPP = + NV5070_CTRL_IS_MODE_POSSIBLE_OUTPUT_RESOURCE_PIXEL_DEPTH_BPP_20_422; + break; } } @@ -351,6 +360,7 @@ AssignPerHeadImpParams(pDevEvo, pImp, pInput->head[head].pTimings, + pInput->head[head].pixelDepth, pInput->head[head].pUsage, head, pInput->head[head].orIndex, @@ -533,7 +543,8 @@ void nvEvo1SetDscParams(const NVDispEvoRec *pDispEvo, const NvU32 head, - const NVHwModeTimingsEvo *pTimings) + const NVDscInfoEvoRec *pDscInfo, + const enum nvKmsPixelDepth pixelDepth) { - nvAssert(!pTimings->dpDsc.enable); + nvAssert(pDscInfo->type == NV_DSC_INFO_EVO_TYPE_DISABLED); } diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia-modeset/src/nvkms-evo2.c nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia-modeset/src/nvkms-evo2.c --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia-modeset/src/nvkms-evo2.c 2023-10-25 20:22:39.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia-modeset/src/nvkms-evo2.c 2024-03-05 22:12:21.000000000 +0000 @@ -40,8 +40,6 @@ #include // NV917C_BASE_CHANNEL_DMA #include // GK104DispOverlayImmControlPio -#include // NV917C_SET_PRESENT_CONTROL_STEREO_FLIP_MODE -#include // NV917D_HEAD_SET_HDMI_CTRL #include // NV917E_OVERLAY_CHANNEL_DMA #include // NV917C_SET_SPARE_{PRE,POST}_UPDATE_TRAP @@ -108,8 +106,6 @@ * that it doesn't exceed 61 bits. */ .validTimeStampBits = 61, - /* The size of the legacy overlay notifier format. */ - .legacyNotifierFormatSizeBytes = NV_DISP_NOTIFICATION_2_SIZEOF, /* Overlay does not support tearing/immediate flips. */ .tearingFlips = FALSE, .vrrTearingFlips = FALSE, @@ -126,22 +122,15 @@ * that it doesn't exceed 61 bits. */ .validTimeStampBits = 61, - /* The size of the legacy base format. */ - .legacyNotifierFormatSizeBytes = NV_DISP_BASE_NOTIFIER_1_SIZEOF, /* Base supports tearing/immediate flips. */ .tearingFlips = TRUE, - /* Some 9x7c classes support VRR; may be overridden at runtime. */ - .vrrTearingFlips = FALSE, + /* Base supports VRR tearing flips. */ + .vrrTearingFlips = TRUE, /* Base supports per-eye stereo flips. */ .perEyeStereoFlips = TRUE, }; pChannel->caps = BaseCaps; - - /* Base supports VRR tearing flips for class 917c and up. */ - if (pChannel->hwclass >= NV917C_BASE_CHANNEL_DMA) { - pChannel->caps.vrrTearingFlips = TRUE; - } } } @@ -339,6 +328,8 @@ */ static void EvoSetRasterParams91(NVDevEvoPtr pDevEvo, int head, const NVHwModeTimingsEvo *pTimings, + const NvU8 tilePosition, + const NVDscInfoEvoRec *pDscInfo, const NVEvoColorRec *pOverscanColor, NVEvoUpdateState *updateState) { @@ -347,6 +338,9 @@ DRF_DEF(917D, _HEAD_SET_HDMI_CTRL, _STEREO3D_STRUCTURE, _FRAME_PACKED) | DRF_NUM(917D, _HEAD_SET_HDMI_CTRL, _HDMI_VIC, 0); + nvAssert(tilePosition == 0); + nvAssert(pDscInfo->type == NV_DSC_INFO_EVO_TYPE_DISABLED); + EvoSetRasterParams90(pDevEvo, head, pTimings, pOverscanColor, updateState); @@ -707,6 +701,10 @@ return NV917D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_PIXEL_DEPTH_BPP_24_444; case NVKMS_PIXEL_DEPTH_30_444: return NV917D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_PIXEL_DEPTH_BPP_30_444; + case NVKMS_PIXEL_DEPTH_16_422: + return NV917D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_PIXEL_DEPTH_BPP_16_422; + case NVKMS_PIXEL_DEPTH_20_422: + return NV917D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_PIXEL_DEPTH_BPP_20_422; } nvAssert(!"Unexpected pixel depth"); return NV917D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_PIXEL_DEPTH_BPP_24_444; @@ -715,10 +713,11 @@ static void EvoHeadSetControlOR90(NVDevEvoPtr pDevEvo, const int head, const NVHwModeTimingsEvo *pTimings, + const enum nvKmsPixelDepth pixelDepth, const NvBool colorSpaceOverride, NVEvoUpdateState *updateState) { - const NvU32 hwPixelDepth = EvoGetPixelDepth90(pTimings->pixelDepth); + const NvU32 hwPixelDepth = EvoGetPixelDepth90(pixelDepth); const NvU16 colorSpaceFlag = nvEvo1GetColorSpaceFlag(pDevEvo, colorSpaceOverride); NVEvoChannelPtr pChannel = pDevEvo->core; @@ -1376,16 +1375,12 @@ const NVFlipCursorEvoHwState *pSdCursorState = &pSdHeadState->cursor; const NVDispEvoRec *pDispEvo = pDevEvo->gpus[sd].pDispEvo; - const int dispIndex = pDispEvo->displayOwner; - NvU8 curLutIndex = pDevEvo->lut.head[head].disp[dispIndex].curLUTIndex; + const NVDispHeadStateEvoRec *pHeadState = &pDispEvo->headState[head]; - NvBool enableOutputLut = - pDevEvo->lut.head[head].disp[dispIndex].curOutputLutEnabled; - NvBool enableBaseLut = - pDevEvo->lut.head[head].disp[dispIndex].curBaseLutEnabled; + NvBool enableOutputLut = pHeadState->lut.outputLutEnabled; + NvBool enableBaseLut = pHeadState->lut.baseLutEnabled; - NVLutSurfaceEvoPtr pCurLutSurfEvo = - pDevEvo->lut.head[head].LUT[curLutIndex]; + NVLutSurfaceEvoPtr pCurLutSurfEvo = pHeadState->lut.pCurrSurface; NvU32 lutCtxdma = pCurLutSurfEvo != NULL ? pCurLutSurfEvo->dispCtxDma : 0x0; @@ -1845,9 +1840,8 @@ const NVSurfaceEvoRec *pNewSurfaceEvo) { const NVDispEvoRec *pDispEvo = pDevEvo->gpus[sd].pDispEvo; - const int dispIndex = pDispEvo->displayOwner; - NvBool enableBaseLut = - pDevEvo->lut.head[head].disp[dispIndex].curBaseLutEnabled; + const NVDispHeadStateEvoRec *pHeadState = &pDispEvo->headState[head]; + NvBool enableBaseLut = pHeadState->lut.baseLutEnabled; const NVSurfaceEvoRec *pCurrCoreSurfaceEvo = pDevEvo->pSubDevices[sd]->pCoreChannelSurface[head]; @@ -2529,8 +2523,11 @@ REF_VAL(NV##cl##_CORE_NOTIFIER_##n##_CAPABILITIES_CAP_HEAD##i##_##x##_MAX_PIXELS##t##TAP444, \ (pCaps)[NV##cl##_CORE_NOTIFIER_##n##_CAPABILITIES_CAP_HEAD##i##_##x])) -#define NV_EVO2_CAP_GET_HEAD(cl, n, pEvoCaps, i, x, y, z, pCaps) \ +#define NV_EVO2_CAP_GET_HEAD(cl, n, pEvoCaps, i, x, y, z, a, pCaps) \ (pEvoCaps)->head[(i)].usable = TRUE; \ + (pEvoCaps)->head[(i)].maxPClkKHz = \ + DRF_VAL(cl##_CORE_NOTIFIER_##n, _CAPABILITIES_CAP_HEAD##i##_##a, _PCLK_MAX, \ + (pCaps)[NV##cl##_CORE_NOTIFIER_##n##_CAPABILITIES_CAP_HEAD##i##_##a]) * 10000; \ (pEvoCaps)->head[(i)].scalerCaps.present = TRUE; \ NV_EVO2_CAP_GET_HEAD_MAX_PIXELS(cl, n, pEvoCaps, i, x, 5, pCaps); \ NV_EVO2_CAP_GET_HEAD_MAX_PIXELS(cl, n, pEvoCaps, i, y, 3, pCaps); \ @@ -2581,10 +2578,10 @@ pEvoCaps->misc.supportsDSI = FALSE; // Heads - NV_EVO2_CAP_GET_HEAD(917D, 3, pEvoCaps, 0, 53, 54, 55, pCaps); - NV_EVO2_CAP_GET_HEAD(917D, 3, pEvoCaps, 1, 61, 62, 63, pCaps); - NV_EVO2_CAP_GET_HEAD(917D, 3, pEvoCaps, 2, 69, 70, 71, pCaps); - NV_EVO2_CAP_GET_HEAD(917D, 3, pEvoCaps, 3, 77, 78, 79, pCaps); + NV_EVO2_CAP_GET_HEAD(917D, 3, pEvoCaps, 0, 53, 54, 55, 56, pCaps); + NV_EVO2_CAP_GET_HEAD(917D, 3, pEvoCaps, 1, 61, 62, 63, 64, pCaps); + NV_EVO2_CAP_GET_HEAD(917D, 3, pEvoCaps, 2, 69, 70, 71, 72, pCaps); + NV_EVO2_CAP_GET_HEAD(917D, 3, pEvoCaps, 3, 77, 78, 79, 80, pCaps); // SORs NV_EVO2_CAP_GET_SOR(917D, 3, pEvoCaps, 0, 20, 21, pCaps); @@ -2613,8 +2610,15 @@ for (layer = 0; layer < ARRAY_LEN(pDevEvo->caps.layerCaps); layer++) { - pDevEvo->caps.layerCaps[layer].supportsWindowMode = - (layer != NVKMS_MAIN_LAYER); + if (layer != NVKMS_MAIN_LAYER) { + pDevEvo->caps.layerCaps[layer].supportsWindowMode = TRUE; + pDevEvo->caps.legacyNotifierFormatSizeBytes[layer] = + NV_DISP_NOTIFICATION_2_SIZEOF; + } else { + pDevEvo->caps.layerCaps[layer].supportsWindowMode = FALSE; + pDevEvo->caps.legacyNotifierFormatSizeBytes[layer] = + NV_DISP_BASE_NOTIFIER_1_SIZEOF; + } } pDevEvo->caps.cursorCompositionCaps = @@ -3855,6 +3859,7 @@ EvoClearSurfaceUsage91, /* ClearSurfaceUsage */ EvoComputeWindowScalingTaps91, /* ComputeWindowScalingTaps */ NULL, /* GetWindowScalingCaps */ + NULL, /* SetMergeMode */ { /* caps */ FALSE, /* supportsNonInterlockedUsageBoundsUpdate */ FALSE, /* supportsDisplayRate */ @@ -3872,6 +3877,7 @@ FALSE, /* supportsSynchronizedOverlayPositionUpdate */ FALSE, /* supportsVblankSyncObjects */ TRUE, /* requiresScalingTapsInBothDimensions */ + FALSE, /* supportsMergeMode */ NV_EVO2_SUPPORTED_DITHERING_MODES, /* supportedDitheringModes */ sizeof(NV5070_CTRL_CMD_IS_MODE_POSSIBLE_PARAMS), /* impStructSize */ NV_EVO_SCALER_1TAP, /* minScalerTaps */ diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia-modeset/src/nvkms-evo3.c nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia-modeset/src/nvkms-evo3.c --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia-modeset/src/nvkms-evo3.c 2023-10-25 20:22:39.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia-modeset/src/nvkms-evo3.c 2024-03-05 22:12:21.000000000 +0000 @@ -33,10 +33,10 @@ #include "nvkms-softfloat.h" #include "nvkms-evo.h" #include "nvkms-evo1.h" -#include "nvkms-modeset-types.h" #include "nvkms-prealloc.h" #include "nv-float.h" #include "nvkms-dpy.h" +#include "nvkms-vrr.h" #include @@ -1269,10 +1269,10 @@ return TRUE; } -static void EvoSetRasterParamsC3(NVDevEvoPtr pDevEvo, int head, - const NVHwModeTimingsEvo *pTimings, - const NVEvoColorRec *pOverscanColor, - NVEvoUpdateState *updateState) +static void EvoSetRasterParams3(NVDevEvoPtr pDevEvo, int head, + const NVHwModeTimingsEvo *pTimings, + const NVEvoColorRec *pOverscanColor, + NVEvoUpdateState *updateState) { NVEvoChannelPtr pChannel = pDevEvo->core; /* XXXnvdisplay: Convert these for YCbCr, as necessary */ @@ -1377,6 +1377,118 @@ nvDmaSetEvoMethodData(pChannel, hdmiStereoCtrl); } +static void EvoSetRasterParamsC3(NVDevEvoPtr pDevEvo, int head, + const NVHwModeTimingsEvo *pTimings, + const NvU8 tilePosition, + const NVDscInfoEvoRec *pDscInfo, + const NVEvoColorRec *pOverscanColor, + NVEvoUpdateState *updateState) +{ + nvAssert(tilePosition == 0); + EvoSetRasterParams3(pDevEvo, head, pTimings, pOverscanColor, updateState); +} + +static void EvoSetRasterParams5(NVDevEvoPtr pDevEvo, int head, + const NVHwModeTimingsEvo *pTimings, + const NvU8 tilePosition, + const NVEvoColorRec *pOverscanColor, + NVEvoUpdateState *updateState) +{ + NVEvoChannelPtr pChannel = pDevEvo->core; + + /* These methods should only apply to a single pDpy */ + nvAssert(pDevEvo->subDevMaskStackDepth > 0); + + nvUpdateUpdateState(pDevEvo, updateState, pChannel); + + EvoSetRasterParams3(pDevEvo, head, pTimings, pOverscanColor, updateState); + + nvDmaSetStartEvoMethod(pChannel, NVC57D_HEAD_SET_TILE_POSITION(head), 1); + nvDmaSetEvoMethodData(pChannel, + DRF_NUM(C57D, _HEAD_SET_TILE_POSITION, _X, tilePosition) | + DRF_NUM(C57D, _HEAD_SET_TILE_POSITION, _Y, 0)); +} + +static void EvoSetRasterParamsC5(NVDevEvoPtr pDevEvo, int head, + const NVHwModeTimingsEvo *pTimings, + const NvU8 tilePosition, + const NVDscInfoEvoRec *pDscInfo, + const NVEvoColorRec *pOverscanColor, + NVEvoUpdateState *updateState) +{ + nvAssert(pDscInfo->type != NV_DSC_INFO_EVO_TYPE_HDMI); + EvoSetRasterParams5(pDevEvo, head, pTimings, tilePosition, pOverscanColor, + updateState); +} + +static NvU32 GetHdmiDscHBlankPixelTarget(const NVHwModeTimingsEvo *pTimings, + const NVDscInfoEvoRec *pDscInfo) +{ + nvAssert((pDscInfo->dp.dscMode == NV_DSC_EVO_MODE_DUAL) || + (pDscInfo->dp.dscMode == NV_DSC_EVO_MODE_SINGLE)); + + const NvU32 hblankMin = + (pDscInfo->dp.dscMode == NV_DSC_EVO_MODE_DUAL) ? + ((pDscInfo->hdmi.hblankMin + 1) / 2) : + pDscInfo->hdmi.hblankMin; + + NvU32 hBlankPixelTarget = + NV_UNSIGNED_DIV_CEIL((pTimings->rasterSize.x * + pDscInfo->hdmi.dscTBlankToTTotalRatioX1k), + 1000); + + hBlankPixelTarget = NV_MAX(hblankMin, hBlankPixelTarget); + + if (pDscInfo->dp.dscMode == NV_DSC_EVO_MODE_DUAL) { + hBlankPixelTarget += (hBlankPixelTarget % 2); + } + + return hBlankPixelTarget; +} + +static void EvoSetRasterParamsC6(NVDevEvoPtr pDevEvo, int head, + const NVHwModeTimingsEvo *pTimings, + const NvU8 tilePosition, + const NVDscInfoEvoRec *pDscInfo, + const NVEvoColorRec *pOverscanColor, + NVEvoUpdateState *updateState) +{ + NvU32 rasterHBlankDelay; + NVEvoChannelPtr pChannel = pDevEvo->core; + + /* These methods should only apply to a single pDpy */ + nvAssert(pDevEvo->subDevMaskStackDepth > 0); + + nvUpdateUpdateState(pDevEvo, updateState, pChannel); + + EvoSetRasterParams5(pDevEvo, head, pTimings, tilePosition, pOverscanColor, + updateState); + + if (pDscInfo->type == NV_DSC_INFO_EVO_TYPE_HDMI) { + const NvU32 hBlank = pTimings->rasterSize.x - + pTimings->rasterBlankStart.x + pTimings->rasterBlankEnd.x; + const NvU32 hBlankPixelTarget = + GetHdmiDscHBlankPixelTarget(pTimings, pDscInfo); + + const NvU32 headSetRasterHBlankDelayStart = + pTimings->rasterSize.x - pTimings->rasterBlankStart.x - 2; + const NvU32 headSetRasterHBlankDelayEnd = + hBlankPixelTarget - hBlank + headSetRasterHBlankDelayStart; + + rasterHBlankDelay = + DRF_NUM(C67D, _HEAD_SET_RASTER_HBLANK_DELAY, _BLANK_START, + headSetRasterHBlankDelayStart); + rasterHBlankDelay |= + DRF_NUM(C67D, _HEAD_SET_RASTER_HBLANK_DELAY, _BLANK_END, + headSetRasterHBlankDelayEnd); + } else { + rasterHBlankDelay = 0; + } + + nvDmaSetStartEvoMethod(pChannel, NVC67D_HEAD_SET_RASTER_HBLANK_DELAY(head), 1); + nvDmaSetEvoMethodData(pChannel, rasterHBlankDelay); +} + static void EvoSetProcAmpC3(NVDispEvoPtr pDispEvo, const NvU32 head, NVEvoUpdateState *updateState) { @@ -1980,6 +2092,18 @@ nvDmaSetStartEvoMethod(pChannel, NVC37D_HEAD_SET_LOCK_CHAIN(head), 1); nvDmaSetEvoMethodData(pChannel, DRF_NUM(C37D, _HEAD_SET_LOCK_CHAIN, _POSITION, pHC->lockChainPosition)); + +/* XXX temporary WAR; see bug 4028718 */ +#if !defined(NVC37D_HEAD_SET_LOCK_OFFSET) +#define NVC37D_HEAD_SET_LOCK_OFFSET(a) (0x00002040 + (a)*0x00000400) +#define NVC37D_HEAD_SET_LOCK_OFFSET_X 14:0 +#define NVC37D_HEAD_SET_LOCK_OFFSET_Y 30:16 +#endif + + nvDmaSetStartEvoMethod(pChannel, NVC37D_HEAD_SET_LOCK_OFFSET(head), 1); + nvDmaSetEvoMethodData(pChannel, pHC->setLockOffsetX ? + DRF_NUM(C37D, _HEAD_SET_LOCK_OFFSET, _X, + 27) : 0); } static void EvoSetHeadRefClkC3(NVDevEvoPtr pDevEvo, int head, NvBool external, @@ -2078,6 +2202,11 @@ return NVC37D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_PIXEL_DEPTH_BPP_24_444; case NVKMS_PIXEL_DEPTH_30_444: return NVC37D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_PIXEL_DEPTH_BPP_30_444; + case NVKMS_PIXEL_DEPTH_16_422: + return NVC37D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_PIXEL_DEPTH_BPP_16_422; + case NVKMS_PIXEL_DEPTH_20_422: + return NVC37D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_PIXEL_DEPTH_BPP_20_422; + } nvAssert(!"Unexpected pixel depth"); return NVC37D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_PIXEL_DEPTH_BPP_24_444; @@ -2189,11 +2318,12 @@ static void EvoHeadSetControlORC3(NVDevEvoPtr pDevEvo, const int head, const NVHwModeTimingsEvo *pTimings, + const enum nvKmsPixelDepth pixelDepth, const NvBool colorSpaceOverride, NVEvoUpdateState *updateState) { NVEvoChannelPtr pChannel = pDevEvo->core; - const NvU32 hwPixelDepth = EvoGetPixelDepthC3(pTimings->pixelDepth); + const NvU32 hwPixelDepth = EvoGetPixelDepthC3(pixelDepth); const NvU16 colorSpaceFlag = nvEvo1GetColorSpaceFlag(pDevEvo, colorSpaceOverride); @@ -2216,11 +2346,12 @@ static void EvoHeadSetControlORC5(NVDevEvoPtr pDevEvo, const int head, const NVHwModeTimingsEvo *pTimings, + const enum nvKmsPixelDepth pixelDepth, const NvBool colorSpaceOverride, NVEvoUpdateState *updateState) { NVEvoChannelPtr pChannel = pDevEvo->core; - const NvU32 hwPixelDepth = EvoGetPixelDepthC3(pTimings->pixelDepth); + const NvU32 hwPixelDepth = EvoGetPixelDepthC3(pixelDepth); const NvU16 colorSpaceFlag = nvEvo1GetColorSpaceFlag(pDevEvo, colorSpaceOverride); @@ -2905,6 +3036,8 @@ */ static NvBool AssignPerHeadImpParams(NVC372_CTRL_IMP_HEAD *pImpHead, const NVHwModeTimingsEvo *pTimings, + const NvBool enableDsc, + const NvBool b2Heads1Or, const int head, const NVEvoScalerCaps *pScalerCaps) { @@ -2958,8 +3091,12 @@ /* Cursor width, in units of 32 pixels. Assume we use the maximum size. */ pImpHead->cursorSize32p = 256 / 32; - pImpHead->bEnableDsc = pTimings->hdmiFrlConfig.dscInfo.bEnableDSC || - pTimings->dpDsc.enable; + pImpHead->bEnableDsc = enableDsc; + + pImpHead->bIs2Head1Or = b2Heads1Or; + + pImpHead->bYUV420Format = + (pTimings->yuv420Mode == NV_YUV420_MODE_HW); return TRUE; } @@ -3071,6 +3208,8 @@ for (head = 0; head < NVKMS_MAX_HEADS_PER_DISP; head++) { const NVHwModeTimingsEvo *pTimings = pInput->head[head].pTimings; + const NvU32 enableDsc = pInput->head[head].enableDsc; + const NvBool b2Heads1Or = pInput->head[head].b2Heads1Or; const struct NvKmsUsageBounds *pUsage = pInput->head[head].pUsage; const NVHwModeViewPortEvo *pViewPort; NvU8 impHeadIndex; @@ -3088,6 +3227,8 @@ if (!AssignPerHeadImpParams(&pImp->head[impHeadIndex], pTimings, + enableDsc, + b2Heads1Or, head, &pEvoCaps->head[head].scalerCaps)) { goto done; @@ -3437,12 +3578,9 @@ acqMode = DRF_DEF(C67E, _SET_SEMAPHORE_CONTROL, _SKIP_ACQ, _TRUE); relMode = DRF_DEF(C67E, _SET_SEMAPHORE_CONTROL, _REL_MODE, _WRITE); value = pHwState->syncObject.u.syncpts.postValue; - /*! increase value in host1x hardware as well */ + /*! increase local max val as well */ if (hCtxDma != 0) { - NvKmsSyncPtOpParams params = { }; - params.incr_max.id = pChannel->postSyncpt.id; - params.incr_max.incr = 1; - nvkms_syncpt_op(NVKMS_SYNCPT_OP_INCR_MAX, ¶ms); + pChannel->postSyncpt.syncptMaxVal++; } } else { if (pHwState->syncObject.u.semaphores.releaseSurface.pSurfaceEvo != NULL) { @@ -3472,7 +3610,8 @@ EvoFlipC3Common(NVDevEvoPtr pDevEvo, NVEvoChannelPtr pChannel, const NVFlipChannelEvoHwState *pHwState, - NVEvoUpdateState *updateState) + NVEvoUpdateState *updateState, + NvU32 head) { const NvKmsSurfaceMemoryFormatInfo *pFormatInfo; NvU32 presentControl, eye; @@ -3484,12 +3623,36 @@ /* program notifier */ if (pHwState->completionNotifier.surface.pSurfaceEvo == NULL) { + /* + * if no notifier surface is attached but vrr RGLine calculations + * for frame pacing are enabled then we need to provide our own + * surface and keep getting flip completion updates. + */ + NvU32 offset; + const NvU32 sdMask = nvPeekEvoSubDevMask(pDevEvo); + const NvU32 sd = (sdMask == 0) ? 0 : __builtin_ffs(sdMask) - 1; + NVDispHeadStateEvoRec *pHeadState = &pDevEvo->pDispEvo[sd]->headState[head]; + struct NvKmsVrrFramePacingInfo *pVrrFramePacingInfo = &pHeadState->vrrFramePacingInfo; - nvDmaSetStartEvoMethod(pChannel, NVC37E_SET_CONTEXT_DMA_NOTIFIER, 1); - nvDmaSetEvoMethodData(pChannel, 0); - nvDmaSetStartEvoMethod(pChannel, NVC37E_SET_NOTIFIER_CONTROL, 1); - nvDmaSetEvoMethodData(pChannel, 0); + if (pVrrFramePacingInfo->framePacingActive) { + nvDmaSetStartEvoMethod(pChannel, NVC37E_SET_CONTEXT_DMA_NOTIFIER, 1); + nvDmaSetEvoMethodData(pChannel, + DRF_NUM(C37E, + _SET_CONTEXT_DMA_NOTIFIER, + _HANDLE, + pChannel->notifiersDma[sd].ctxHandle)); + offset = nvPrepareNextVrrNotifier(pChannel, sd, head); + nvDmaSetStartEvoMethod(pChannel, NVC37E_SET_NOTIFIER_CONTROL, 1); + nvDmaSetEvoMethodData(pChannel, + DRF_NUM(C37E, _SET_NOTIFIER_CONTROL, _OFFSET, offset) | + (DRF_DEF(C37E, _SET_NOTIFIER_CONTROL, _MODE, _WRITE_AWAKEN))); + } else { + nvDmaSetStartEvoMethod(pChannel, NVC37E_SET_CONTEXT_DMA_NOTIFIER, 1); + nvDmaSetEvoMethodData(pChannel, 0); + nvDmaSetStartEvoMethod(pChannel, NVC37E_SET_NOTIFIER_CONTROL, 1); + nvDmaSetEvoMethodData(pChannel, 0); + } } else { const NVFlipNIsoSurfaceEvoHwState *pNIso = &pHwState->completionNotifier.surface; @@ -3945,7 +4108,7 @@ NvU32 win = NV_EVO_CHANNEL_MASK_WINDOW_NUMBER(pChannel->channelMask); NvU32 head = pDevEvo->headForWindow[win]; NvBool found = FALSE; - NvU32 dispIndex = 0; + const NVDispEvoRec *pDispEvo = NULL; NvU32 sd; if ((pHwState->pSurfaceEvo[NVKMS_LEFT] == NULL) || @@ -3977,9 +4140,9 @@ for (sd = 0; sd < pDevEvo->numSubDevices; sd++) { if (nvPeekEvoSubDevMask(pDevEvo) & (1 << sd)) { if (found) { - nvAssert(dispIndex == pDevEvo->gpus[sd].pDispEvo->displayOwner); + nvAssert(pDispEvo == pDevEvo->gpus[sd].pDispEvo); } else { - dispIndex = pDevEvo->gpus[sd].pDispEvo->displayOwner; + pDispEvo = pDevEvo->gpus[sd].pDispEvo; found = TRUE; } } @@ -3993,10 +4156,7 @@ * in the surface format and curLUTIndex does not change until next * EvoSetLUTContextDma3() call which also makes sure to disable tearing. */ - const NvU32 lutIndex = - pDevEvo->lut.head[head].disp[dispIndex].curLUTIndex; - - return pDevEvo->lut.head[head].LUT[lutIndex]; + return pDispEvo->headState[head].lut.pCurrSurface; } static void @@ -4010,13 +4170,15 @@ enum NvKmsSurfaceMemoryFormat format; NVLutSurfaceEvoPtr pLutSurfaceEvo = EvoGetLutSurface3(pDevEvo, pChannel, pHwState); + NvU32 win = NV_EVO_CHANNEL_MASK_WINDOW_NUMBER(pChannel->channelMask); + NvU32 head = pDevEvo->headForWindow[win]; if (pHwState->timeStamp != 0) { InsertAdditionalTimestampFlip(pDevEvo, pChannel, pHwState, updateState); } - flip3Return = EvoFlipC3Common(pDevEvo, pChannel, pHwState, updateState); + flip3Return = EvoFlipC3Common(pDevEvo, pChannel, pHwState, updateState, head); /* program semaphore */ EvoProgramSemaphore3(pDevEvo, pChannel, pHwState); @@ -4175,7 +4337,7 @@ pLutSurfaceEvo = EvoGetLutSurface3(pDevEvo, pChannel, pHwState); } - if (!EvoFlipC3Common(pDevEvo, pChannel, pHwState, updateState)) { + if (!EvoFlipC3Common(pDevEvo, pChannel, pHwState, updateState, head)) { ConfigureTmoLut(pDevEvo, pHwState, pChannel); return; } @@ -5228,6 +5390,14 @@ // NVDisplay does not support interlaced modes. pEvoCaps->misc.supportsInterlaced = FALSE; +/* XXX temporary WAR; see bug 4028718 */ +#if !defined(NVC373_HEAD_CLK_CAP) +#define NVC373_HEAD_CLK_CAP(i) (0x5e8+(i)*4) /* RW-4A */ +#define NVC373_HEAD_CLK_CAP__SIZE_1 8 /* */ +#define NVC373_HEAD_CLK_CAP_PCLK_MAX 7:0 /* RWIUF */ +#define NVC373_HEAD_CLK_CAP_PCLK_MAX_INIT 0x00000085 /* RWI-V */ +#endif + // Heads ct_assert(ARRAY_LEN(pEvoCaps->head) >= NVC373_HEAD_CAPA__SIZE_1); for (i = 0; i < NVC373_HEAD_CAPA__SIZE_1; i++) { @@ -5235,6 +5405,12 @@ pHeadCaps->usable = FLD_IDX_TEST_DRF(C373, _SYS_CAP, _HEAD_EXISTS, i, _YES, sysCap); + if (pHeadCaps->usable) { + pHeadCaps->maxPClkKHz = + DRF_VAL(C373, _HEAD_CLK_CAP, _PCLK_MAX, + ReadCapReg(pCaps, NVC373_HEAD_CLK_CAP(i))) * 10000; + } + } // SORs @@ -6461,16 +6637,35 @@ { NVDevEvoPtr pDevEvo = pDispEvo->pDevEvo; NVEvoChannelPtr pChannel = pDevEvo->core; + NVEvoSubDevPtr pEvoSubDev = &pDevEvo->gpus[pDispEvo->displayOwner]; + NVEvoHeadControlPtr pHC = &pEvoSubDev->headControl[head]; nvUpdateUpdateState(pDevEvo, updateState, pChannel); if (enable) { + NvU32 data = DRF_DEF(C37D, _HEAD_SET_STALL_LOCK, _ENABLE, _TRUE) | + DRF_DEF(C37D, _HEAD_SET_STALL_LOCK, _MODE, _ONE_SHOT); + + if (!pHC->useStallLockPin) { + data |= DRF_DEF(C37D, _HEAD_SET_STALL_LOCK, _LOCK_PIN, _LOCK_PIN_NONE); + } else if (NV_EVO_LOCK_PIN_IS_INTERNAL(pHC->stallLockPin)) { + NvU32 pin = pHC->stallLockPin - NV_EVO_LOCK_PIN_INTERNAL_0; + data |= DRF_NUM(C37D, _HEAD_SET_STALL_LOCK, _LOCK_PIN, + NVC37D_HEAD_SET_STALL_LOCK_LOCK_PIN_INTERNAL_SCAN_LOCK(pin)); + } else { + NvU32 pin = pHC->stallLockPin - NV_EVO_LOCK_PIN_0; + data |= DRF_NUM(C37D, _HEAD_SET_STALL_LOCK, _LOCK_PIN, + NVC37D_HEAD_SET_STALL_LOCK_LOCK_PIN_LOCK_PIN(pin)); + } + + if (pHC->crashLockUnstallMode) { + data |= DRF_DEF(C37D, _HEAD_SET_STALL_LOCK, _UNSTALL_MODE, _CRASH_LOCK); + } else { + data |= DRF_DEF(C37D, _HEAD_SET_STALL_LOCK, _UNSTALL_MODE, _LINE_LOCK); + } + nvDmaSetStartEvoMethod(pChannel, NVC37D_HEAD_SET_STALL_LOCK(head), 1); - nvDmaSetEvoMethodData(pChannel, - DRF_DEF(C37D, _HEAD_SET_STALL_LOCK, _ENABLE, _TRUE) | - DRF_DEF(C37D, _HEAD_SET_STALL_LOCK, _MODE, _ONE_SHOT) | - DRF_DEF(C37D, _HEAD_SET_STALL_LOCK, _LOCK_PIN, _LOCK_PIN_NONE) | - DRF_DEF(C37D, _HEAD_SET_STALL_LOCK, _UNSTALL_MODE, _LINE_LOCK)); + nvDmaSetEvoMethodData(pChannel, data); } else { nvDmaSetStartEvoMethod(pChannel, NVC37D_HEAD_SET_STALL_LOCK(head), 1); nvDmaSetEvoMethodData(pChannel, @@ -7219,20 +7414,19 @@ rasterLine)); } -static void EvoSetHdmiFrlDscParams(const NVDispEvoRec *pDispEvo, +static void EvoSetHdmiDscParams(const NVDispEvoRec *pDispEvo, const NvU32 head, - const NVHwModeTimingsEvo *pTimings) + const NVDscInfoEvoRec *pDscInfo, + const enum nvKmsPixelDepth pixelDepth) { NVEvoChannelPtr pChannel = pDispEvo->pDevEvo->core; - const HDMI_FRL_CONFIG *pFrl = &pTimings->hdmiFrlConfig; NvU32 bpc, flatnessDetThresh; NvU32 i; nvAssert(pDispEvo->pDevEvo->hal->caps.supportsHDMIFRL && - pFrl->frlRate != HDMI_FRL_DATA_RATE_NONE && - pFrl->dscInfo.bEnableDSC); + pDscInfo->type == NV_DSC_INFO_EVO_TYPE_HDMI); - bpc = nvPixelDepthToBitsPerComponent(pTimings->pixelDepth); + bpc = nvPixelDepthToBitsPerComponent(pixelDepth); if (bpc < 8) { nvAssert(bpc >= 8); bpc = 8; @@ -7242,7 +7436,9 @@ nvDmaSetStartEvoMethod(pChannel, NVC67D_HEAD_SET_DSC_CONTROL(head), 1); nvDmaSetEvoMethodData(pChannel, DRF_DEF(C67D, _HEAD_SET_DSC_CONTROL, _ENABLE, _TRUE) | - DRF_DEF(C67D, _HEAD_SET_DSC_CONTROL, _MODE, _SINGLE) | /* TODO DUAL for 2Head1OR */ + ((pDscInfo->hdmi.dscMode == NV_DSC_EVO_MODE_DUAL) ? + DRF_DEF(C57D, _HEAD_SET_DSC_CONTROL, _MODE, _DUAL) : + DRF_DEF(C57D, _HEAD_SET_DSC_CONTROL, _MODE, _SINGLE)) | DRF_NUM(C67D, _HEAD_SET_DSC_CONTROL, _FLATNESS_DET_THRESH, flatnessDetThresh) | DRF_DEF(C67D, _HEAD_SET_DSC_CONTROL, _FULL_ICH_ERR_PRECISION, _ENABLE) | DRF_DEF(C67D, _HEAD_SET_DSC_CONTROL, _AUTO_RESET, _ENABLE) | @@ -7257,12 +7453,12 @@ DRF_NUM(C67D, _HEAD_SET_DSC_PPS_CONTROL, _SIZE, 0x21)); /* The loop below assumes the methods are tightly packed. */ - ct_assert(ARRAY_LEN(pFrl->dscInfo.pps) == 32); + ct_assert(ARRAY_LEN(pDscInfo->hdmi.pps) == 32); ct_assert((NVC67D_HEAD_SET_DSC_PPS_DATA1(0) - NVC67D_HEAD_SET_DSC_PPS_DATA0(0)) == 4); ct_assert((NVC67D_HEAD_SET_DSC_PPS_DATA31(0) - NVC67D_HEAD_SET_DSC_PPS_DATA0(0)) == (31 * 4)); - for (i = 0; i < ARRAY_LEN(pFrl->dscInfo.pps); i++) { + for (i = 0; i < ARRAY_LEN(pDscInfo->hdmi.pps); i++) { nvDmaSetStartEvoMethod(pChannel, NVC67D_HEAD_SET_DSC_PPS_DATA0(head) + (i * 4), 1); - nvDmaSetEvoMethodData(pChannel, pFrl->dscInfo.pps[i]); + nvDmaSetEvoMethodData(pChannel, pDscInfo->hdmi.pps[i]); } /* Byte 0 must be 0x7f, the rest are don't care (will be filled in by HW) */ @@ -7272,32 +7468,37 @@ nvDmaSetStartEvoMethod(pChannel, NVC67D_HEAD_SET_HDMI_DSC_HCACTIVE(head), 1); nvDmaSetEvoMethodData(pChannel, - DRF_NUM(C67D, _HEAD_SET_HDMI_DSC_HCACTIVE, _BYTES, pFrl->dscInfo.dscHActiveBytes) | - DRF_NUM(C67D, _HEAD_SET_HDMI_DSC_HCACTIVE, _TRI_BYTES, pFrl->dscInfo.dscHActiveTriBytes)); + DRF_NUM(C67D, _HEAD_SET_HDMI_DSC_HCACTIVE, _BYTES, pDscInfo->hdmi.dscHActiveBytes) | + DRF_NUM(C67D, _HEAD_SET_HDMI_DSC_HCACTIVE, _TRI_BYTES, pDscInfo->hdmi.dscHActiveTriBytes)); nvDmaSetStartEvoMethod(pChannel, NVC67D_HEAD_SET_HDMI_DSC_HCBLANK(head), 1); nvDmaSetEvoMethodData(pChannel, - DRF_NUM(C67D, _HEAD_SET_HDMI_DSC_HCBLANK, _WIDTH, pFrl->dscInfo.dscHBlankTriBytes)); + DRF_NUM(C67D, _HEAD_SET_HDMI_DSC_HCBLANK, _WIDTH, pDscInfo->hdmi.dscHBlankTriBytes)); } static void EvoSetDpDscParams(const NVDispEvoRec *pDispEvo, const NvU32 head, - const NVHwModeTimingsEvo *pTimings) + const NVDscInfoEvoRec *pDscInfo) { NVEvoChannelPtr pChannel = pDispEvo->pDevEvo->core; NvU32 flatnessDetThresh; NvU32 i; - nvAssert(pTimings->dpDsc.enable); + nvAssert(pDscInfo->type == NV_DSC_INFO_EVO_TYPE_DP); // XXX: I'm pretty sure that this is wrong. // BitsPerPixelx16 is something like (24 * 16) = 384, and 2 << (384 - 8) is // an insanely large number. - flatnessDetThresh = (2 << (pTimings->dpDsc.bitsPerPixelX16 - 8)); /* ??? */ + flatnessDetThresh = (2 << (pDscInfo->dp.bitsPerPixelX16 - 8)); /* ??? */ + + nvAssert((pDscInfo->dp.dscMode == NV_DSC_EVO_MODE_DUAL) || + (pDscInfo->dp.dscMode == NV_DSC_EVO_MODE_SINGLE)); nvDmaSetStartEvoMethod(pChannel, NVC57D_HEAD_SET_DSC_CONTROL(head), 1); nvDmaSetEvoMethodData(pChannel, DRF_DEF(C57D, _HEAD_SET_DSC_CONTROL, _ENABLE, _TRUE) | - DRF_DEF(C57D, _HEAD_SET_DSC_CONTROL, _MODE, _SINGLE) | /* TODO DUAL for 2Head1OR */ + ((pDscInfo->dp.dscMode == NV_DSC_EVO_MODE_DUAL) ? + DRF_DEF(C57D, _HEAD_SET_DSC_CONTROL, _MODE, _DUAL) : + DRF_DEF(C57D, _HEAD_SET_DSC_CONTROL, _MODE, _SINGLE)) | DRF_NUM(C57D, _HEAD_SET_DSC_CONTROL, _FLATNESS_DET_THRESH, flatnessDetThresh) | DRF_DEF(C57D, _HEAD_SET_DSC_CONTROL, _FULL_ICH_ERR_PRECISION, _ENABLE) | DRF_DEF(C57D, _HEAD_SET_DSC_CONTROL, _AUTO_RESET, _DISABLE) | @@ -7314,11 +7515,11 @@ #define NV_EVO5_NUM_HEAD_SET_DSC_PPS_DATA_DWORDS \ (((NVC57D_HEAD_SET_DSC_PPS_DATA31(0) - NVC57D_HEAD_SET_DSC_PPS_DATA0(0)) / 4) + 1) - ct_assert(NV_EVO5_NUM_HEAD_SET_DSC_PPS_DATA_DWORDS <= ARRAY_LEN(pTimings->dpDsc.pps)); + ct_assert(NV_EVO5_NUM_HEAD_SET_DSC_PPS_DATA_DWORDS <= ARRAY_LEN(pDscInfo->dp.pps)); for (i = 0; i < NV_EVO5_NUM_HEAD_SET_DSC_PPS_DATA_DWORDS; i++) { nvDmaSetStartEvoMethod(pChannel,(NVC57D_HEAD_SET_DSC_PPS_DATA0(head) + (i * 4)), 1); - nvDmaSetEvoMethodData(pChannel, pTimings->dpDsc.pps[i]); + nvDmaSetEvoMethodData(pChannel, pDscInfo->dp.pps[i]); } /* @@ -7338,18 +7539,18 @@ static void EvoSetDscParamsC5(const NVDispEvoRec *pDispEvo, const NvU32 head, - const NVHwModeTimingsEvo *pTimings) + const NVDscInfoEvoRec *pDscInfo, + const enum nvKmsPixelDepth pixelDepth) { - - if (pTimings->hdmiFrlConfig.frlRate != HDMI_FRL_DATA_RATE_NONE) { - if (pTimings->hdmiFrlConfig.dscInfo.bEnableDSC) { - EvoSetHdmiFrlDscParams(pDispEvo, head, pTimings); - } - } else if (pTimings->dpDsc.enable) { - EvoSetDpDscParams(pDispEvo, head, pTimings); + if (pDscInfo->type == NV_DSC_INFO_EVO_TYPE_HDMI) { + EvoSetHdmiDscParams(pDispEvo, head, pDscInfo, pixelDepth); + } else if (pDscInfo->type == NV_DSC_INFO_EVO_TYPE_DP) { + EvoSetDpDscParams(pDispEvo, head, pDscInfo); } else { NVEvoChannelPtr pChannel = pDispEvo->pDevEvo->core; + nvAssert(pDscInfo->type == NV_DSC_INFO_EVO_TYPE_DISABLED); + /* Disable DSC function */ nvDmaSetStartEvoMethod(pChannel, NVC57D_HEAD_SET_DSC_CONTROL(head), 1); nvDmaSetEvoMethodData(pChannel, @@ -7360,7 +7561,6 @@ nvDmaSetEvoMethodData(pChannel, DRF_DEF(C57D, _HEAD_SET_DSC_PPS_CONTROL, _ENABLE, _FALSE)); } - } static void @@ -7477,6 +7677,39 @@ return &pDevEvo->gpus[0].capabilities.window[0].scalerCaps; } +static void EvoSetMergeModeC5(const NVDispEvoRec *pDispEvo, + const NvU32 head, + const NVEvoMergeMode mode, + NVEvoUpdateState* pUpdateState) +{ + NVDevEvoRec *pDevEvo = pDispEvo->pDevEvo; + NVEvoChannelPtr pChannel = pDevEvo->core; + NvU32 data = 0x0; + + nvPushEvoSubDevMask(pDevEvo, NVBIT(pDispEvo->displayOwner)); + + nvUpdateUpdateState(pDevEvo, pUpdateState, pChannel); + + switch (mode) { + case NV_EVO_MERGE_MODE_DISABLED: + data = DRF_DEF(C57D, _HEAD_SET_RG_MERGE, _MODE, _DISABLE); + break; + case NV_EVO_MERGE_MODE_SETUP: + data = DRF_DEF(C57D, _HEAD_SET_RG_MERGE, _MODE, _SETUP); + break; + case NV_EVO_MERGE_MODE_PRIMARY: + data = DRF_DEF(C57D, _HEAD_SET_RG_MERGE, _MODE, _MASTER); + break; + case NV_EVO_MERGE_MODE_SECONDARY: + data = DRF_DEF(C57D, _HEAD_SET_RG_MERGE, _MODE, _SLAVE); + break; + } + + nvDmaSetStartEvoMethod(pChannel, NVC57D_HEAD_SET_RG_MERGE(head), 1); + nvDmaSetEvoMethodData(pChannel, data); + + nvPopEvoSubDevMask(pDevEvo); +} NVEvoHAL nvEvoC3 = { EvoSetRasterParamsC3, /* SetRasterParams */ @@ -7531,6 +7764,7 @@ NULL, /* ClearSurfaceUsage */ EvoComputeWindowScalingTapsC3, /* ComputeWindowScalingTaps */ EvoGetWindowScalingCapsC3, /* GetWindowScalingCaps */ + NULL, /* SetMergeMode */ { /* caps */ TRUE, /* supportsNonInterlockedUsageBoundsUpdate */ TRUE, /* supportsDisplayRate */ @@ -7548,6 +7782,7 @@ TRUE, /* supportsSynchronizedOverlayPositionUpdate */ FALSE, /* supportsVblankSyncObjects */ FALSE, /* requiresScalingTapsInBothDimensions */ + FALSE, /* supportsMergeMode */ NV_EVO3_SUPPORTED_DITHERING_MODES, /* supportedDitheringModes */ sizeof(NVC372_CTRL_IS_MODE_POSSIBLE_PARAMS), /* impStructSize */ NV_EVO_SCALER_2TAPS, /* minScalerTaps */ @@ -7556,7 +7791,7 @@ }; NVEvoHAL nvEvoC5 = { - EvoSetRasterParamsC3, /* SetRasterParams */ + EvoSetRasterParamsC5, /* SetRasterParams */ EvoSetProcAmpC5, /* SetProcAmp */ EvoSetHeadControlC3, /* SetHeadControl */ EvoSetHeadRefClkC3, /* SetHeadRefClk */ @@ -7608,6 +7843,7 @@ NULL, /* ClearSurfaceUsage */ EvoComputeWindowScalingTapsC5, /* ComputeWindowScalingTaps */ EvoGetWindowScalingCapsC3, /* GetWindowScalingCaps */ + EvoSetMergeModeC5, /* SetMergeMode */ { /* caps */ TRUE, /* supportsNonInterlockedUsageBoundsUpdate */ TRUE, /* supportsDisplayRate */ @@ -7625,6 +7861,7 @@ TRUE, /* supportsSynchronizedOverlayPositionUpdate */ FALSE, /* supportsVblankSyncObjects */ FALSE, /* requiresScalingTapsInBothDimensions */ + TRUE, /* supportsMergeMode */ NV_EVO3_SUPPORTED_DITHERING_MODES, /* supportedDitheringModes */ sizeof(NVC372_CTRL_IS_MODE_POSSIBLE_PARAMS), /* impStructSize */ NV_EVO_SCALER_2TAPS, /* minScalerTaps */ @@ -7633,7 +7870,7 @@ }; NVEvoHAL nvEvoC6 = { - EvoSetRasterParamsC3, /* SetRasterParams */ + EvoSetRasterParamsC6, /* SetRasterParams */ EvoSetProcAmpC5, /* SetProcAmp */ EvoSetHeadControlC3, /* SetHeadControl */ EvoSetHeadRefClkC3, /* SetHeadRefClk */ @@ -7685,6 +7922,7 @@ NULL, /* ClearSurfaceUsage */ EvoComputeWindowScalingTapsC5, /* ComputeWindowScalingTaps */ EvoGetWindowScalingCapsC3, /* GetWindowScalingCaps */ + EvoSetMergeModeC5, /* SetMergeMode */ { /* caps */ TRUE, /* supportsNonInterlockedUsageBoundsUpdate */ TRUE, /* supportsDisplayRate */ @@ -7702,6 +7940,7 @@ TRUE, /* supportsSynchronizedOverlayPositionUpdate */ TRUE, /* supportsVblankSyncObjects */ FALSE, /* requiresScalingTapsInBothDimensions */ + TRUE, /* supportsMergeMode */ NV_EVO3_SUPPORTED_DITHERING_MODES, /* supportedDitheringModes */ sizeof(NVC372_CTRL_IS_MODE_POSSIBLE_PARAMS), /* impStructSize */ NV_EVO_SCALER_2TAPS, /* minScalerTaps */ diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia-modeset/src/nvkms-flip.c nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia-modeset/src/nvkms-flip.c --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia-modeset/src/nvkms-flip.c 2023-10-25 20:22:39.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia-modeset/src/nvkms-flip.c 2024-03-05 22:12:21.000000000 +0000 @@ -24,636 +24,23 @@ #include "nvkms-dma.h" #include "nvkms-evo.h" #include "nvkms-flip.h" -#include "nvkms-flip-workarea.h" -#include "nvkms-surface.h" +#include "nvkms-hw-flip.h" +#include "nvkms-utils-flip.h" #include "nvkms-prealloc.h" #include "nvkms-private.h" -#include "nvkms-rm.h" #include "nvkms-vrr.h" -#include "nvkms-cursor.h" -#include "nvkms-types.h" #include "nvkms-dpy.h" -#include "nvkms-lut.h" -#include "nvkms-softfloat.h" - -#include "nvkms-sync.h" - -#include "nvkms-difr.h" - -static void SchedulePostFlipIMPTimer(NVDevEvoPtr pDevEvo); - -// The EVO .mfs file defines the maximum minPresentInterval to be 8. -#define NV_MAX_SWAP_INTERVAL 8 - -/*! - * Assign the elements in an NVSurfaceEvoPtr[NVKMS_MAX_EYES] array. - * - * Use NVEvoApiHandlesRec to translate an - * NvKmsSurfaceHandle[NVKMS_MAX_EYES] array into an an - * NVSurfaceEvoPtr[NVKMS_MAX_EYES] array. - * - * \param[in] pOpenDevSurfaceHandles The client's surfaces. - * \param[in] surfaceHandles The handles naming surfaces. - * \param[out] pSurfaceEvos The surface pointers. - * - * \return Return TRUE if all surfaceHandles could be successfully - * translated into pSurfaceEvos. Otherwise, return FALSE. - */ -NvBool nvAssignSurfaceArray( - const NVDevEvoRec *pDevEvo, - const NVEvoApiHandlesRec *pOpenDevSurfaceHandles, - const NvKmsSurfaceHandle surfaceHandles[NVKMS_MAX_EYES], - const NvBool isUsedByCursorChannel, - const NvBool isUsedByLayerChannel, - NVSurfaceEvoPtr pSurfaceEvos[NVKMS_MAX_EYES]) -{ - NvU32 eye; - - nvkms_memset(pSurfaceEvos, 0, sizeof(NVSurfaceEvoRec *) * NVKMS_MAX_EYES); - - for (eye = 0; eye < NVKMS_MAX_EYES; eye++) { - if (surfaceHandles[eye] != 0) { - pSurfaceEvos[eye] = - nvEvoGetSurfaceFromHandle(pDevEvo, - pOpenDevSurfaceHandles, - surfaceHandles[eye], - isUsedByCursorChannel, - isUsedByLayerChannel); - if ((pSurfaceEvos[eye] == NULL) || - (pSurfaceEvos[eye]->isoType != NVKMS_MEMORY_ISO)) { - return FALSE; - } - } - } - return TRUE; -} - - -/*! - * Assign the NVFlipNIsoSurfaceEvoHwState. - * - * Use the given NvKmsNIsoSurface to populate the - * NVFlipNIsoSurfaceEvoHwState. Validate that NvKmsNIsoSurface - * description is legitimate. - * - * \param[in] pDevEvo The device where the surface will be used. - * \param[in] pOpenDevSurfaceHandles The client's surfaces. - * \param[in] pParamsNIso The client's description of the NISO surface. - * \param[in] notifier Whether the NISO surface is a notifier. - * \param[in] pChannel The channel where the surface will be used. - * \param[out] pNIsoState The NVKMS presentation of the NISO surface. - * - * \return Return TRUE if the NVFlipNIsoSurfaceEvoHwState could be - * assigned and validated. Otherwise, return FALSE and leave - * the NVFlipNIsoSurfaceEvoHwState untouched. - */ -static NvBool AssignNIsoEvoHwState( - const NVDevEvoRec *pDevEvo, - const NVEvoApiHandlesRec *pOpenDevSurfaceHandles, - const struct NvKmsNIsoSurface *pParamsNIso, - const NvBool notifier, /* TRUE=notifier; FALSE=semaphore */ - const NVEvoChannel *pChannel, - NVFlipNIsoSurfaceEvoHwState *pNIsoState) -{ - NVSurfaceEvoPtr pSurfaceEvo; - NvU32 elementSizeInBytes = 0, offsetInBytes, maxBytes; - - nvAssert(pParamsNIso->surfaceHandle != 0); - - pSurfaceEvo = - nvEvoGetSurfaceFromHandle(pDevEvo, - pOpenDevSurfaceHandles, - pParamsNIso->surfaceHandle, - FALSE /* isUsedByCursorChannel */, - TRUE /* isUsedByLayerChannel */); - if (pSurfaceEvo == NULL) { - return FALSE; - } - - /* Attempt to validate the surface: */ - - /* Only pitch surfaces can be used */ - if (pSurfaceEvo->layout != NvKmsSurfaceMemoryLayoutPitch) { - return FALSE; - } - - if (pSurfaceEvo->isoType != NVKMS_MEMORY_NISO) { - return FALSE; - } - - if ((pParamsNIso->format != NVKMS_NISO_FORMAT_FOUR_WORD) && - (pParamsNIso->format != NVKMS_NISO_FORMAT_FOUR_WORD_NVDISPLAY) && - (pParamsNIso->format != NVKMS_NISO_FORMAT_LEGACY)) { - return FALSE; - } - - if ((pDevEvo->caps.validNIsoFormatMask & - (1 << pParamsNIso->format)) == 0) { - return FALSE; - } - - /* Check that the item fits within the surface. */ - switch (pParamsNIso->format) { - case NVKMS_NISO_FORMAT_FOUR_WORD: - case NVKMS_NISO_FORMAT_FOUR_WORD_NVDISPLAY: - elementSizeInBytes = 16; - break; - case NVKMS_NISO_FORMAT_LEGACY: - if (notifier) { - /* Legacy notifier size depends on the channel. */ - elementSizeInBytes = pChannel->caps.legacyNotifierFormatSizeBytes; - } else { - /* Legacy semaphores are always 4 bytes. */ - elementSizeInBytes = 4; - } - break; - } - -#if defined(DEBUG) - /* Assert that the size calculated by nvkms-sync library is the same as the - * one we derived from channel caps above. */ - if (notifier) { - NvBool overlay = !!(pChannel->channelMask & - NV_EVO_CHANNEL_MASK_OVERLAY_ALL); - NvU32 libSize = nvKmsSizeOfNotifier(pParamsNIso->format, overlay); - nvAssert(libSize == elementSizeInBytes); - } else { - nvAssert(nvKmsSizeOfSemaphore(pParamsNIso->format) == elementSizeInBytes); - } -#endif - /* - * offsetInWords is an NvU16 and offsetInBytes is an NvU32, so - * neither of the expressions: - * offsetInWords * 4 - * offsetInBytes + elementSizeInBytes - * should ever overflow. - */ - - ct_assert(sizeof(pParamsNIso->offsetInWords) == 2); - - offsetInBytes = ((NvU32)pParamsNIso->offsetInWords) * 4; - - /* - * Compute the upper extent of the NISO element within the surface. - */ - - maxBytes = offsetInBytes + elementSizeInBytes; - - if (maxBytes > pSurfaceEvo->planes[0].rmObjectSizeInBytes) { - return FALSE; - } - - /* EVO expects the NISO element to fit within a 4k page. */ - - if (maxBytes > 4096) { - return FALSE; - } - - /* - * XXX NVKMS TODO: Check that the surface is in vidmem if - * NV5070_CTRL_SYSTEM_CAPS_BUG_644815_DNISO_VIDMEM_ONLY - */ - - pNIsoState->pSurfaceEvo = pSurfaceEvo; - pNIsoState->format = pParamsNIso->format; - pNIsoState->offsetInWords = pParamsNIso->offsetInWords; - - return TRUE; -} - - -static NvBool AssignCompletionNotifierEvoHwState( - const NVDevEvoRec *pDevEvo, - const NVEvoApiHandlesRec *pOpenDevSurfaceHandles, - const struct NvKmsCompletionNotifierDescription *pParamsNotif, - const NVEvoChannel *pChannel, - NVFlipCompletionNotifierEvoHwState *pNotif) -{ - NvBool ret; - - nvkms_memset(pNotif, 0, sizeof(*pNotif)); - - /* If no surface is specified, we should not use a notifier. */ - if (pParamsNotif->surface.surfaceHandle == 0) { - return TRUE; - } - - ret = AssignNIsoEvoHwState(pDevEvo, - pOpenDevSurfaceHandles, - &pParamsNotif->surface, - TRUE, /* notifier */ - pChannel, - &pNotif->surface); - if (ret) { - pNotif->awaken = pParamsNotif->awaken; - } - - return ret; -} - -static NvBool AssignSemaphoreEvoHwState( - const NVDevEvoRec *pDevEvo, - const NVEvoApiHandlesRec *pOpenDevSurfaceHandles, - const NVEvoChannel *pChannel, - const NvU32 sd, - const struct NvKmsChannelSyncObjects *pChannelSyncObjects, - NVFlipSyncObjectEvoHwState *pFlipSyncObject) -{ - NvBool ret; - - nvAssert(!pChannelSyncObjects->useSyncpt); - - nvkms_memset(pFlipSyncObject, 0, sizeof(*pFlipSyncObject)); - - if (!pDevEvo->hal->caps.supportsIndependentAcqRelSemaphore) { - /*! acquire and release sema surface needs to be same */ - if (pChannelSyncObjects->u.semaphores.acquire.surface.surfaceHandle != - pChannelSyncObjects->u.semaphores.release.surface.surfaceHandle) { - return FALSE; - } - if (pChannelSyncObjects->u.semaphores.acquire.surface.format != - pChannelSyncObjects->u.semaphores.release.surface.format) { - return FALSE; - } - if (pChannelSyncObjects->u.semaphores.acquire.surface.offsetInWords != - pChannelSyncObjects->u.semaphores.release.surface.offsetInWords) { - return FALSE; - } - } - - /*! If no surface is specified, we should not use a semaphore.*/ - if (pChannelSyncObjects->u.semaphores.acquire.surface.surfaceHandle != 0) { - - ret = AssignNIsoEvoHwState( - pDevEvo, - pOpenDevSurfaceHandles, - &pChannelSyncObjects->u.semaphores.acquire.surface, - FALSE, /* notifier */ - pChannel, - &pFlipSyncObject->u.semaphores.acquireSurface); - if (ret) { - pFlipSyncObject->u.semaphores.acquireValue = - pChannelSyncObjects->u.semaphores.acquire.value; - } else { - return ret; - } - } - - /*! If no surface is specified, we should not use a semaphore.*/ - if (pChannelSyncObjects->u.semaphores.release.surface.surfaceHandle != 0) { - - ret = AssignNIsoEvoHwState( - pDevEvo, - pOpenDevSurfaceHandles, - &pChannelSyncObjects->u.semaphores.release.surface, - FALSE, /* notifier */ - pChannel, - &pFlipSyncObject->u.semaphores.releaseSurface); - if (ret) { - pFlipSyncObject->u.semaphores.releaseValue = - pChannelSyncObjects->u.semaphores.release.value; - } else { - return ret; - } - } - - return TRUE; -} - -static NvBool AssignPreSyncptEvoHwState( - const NVDevEvoRec *pDevEvo, - const struct NvKmsChannelSyncObjects *pChannelSyncObjects, - NVFlipSyncObjectEvoHwState *pFlipSyncObject) -{ - NvBool ret; - NvU32 id = 0; - NvU32 value; - enum NvKmsSyncptType preType; - - nvAssert(pChannelSyncObjects->useSyncpt); - - preType = pChannelSyncObjects->u.syncpts.pre.type; - - if (preType == NVKMS_SYNCPT_TYPE_NONE) { - return TRUE; - } - - if (preType == NVKMS_SYNCPT_TYPE_FD) { - /*! Get id from fd using nvhost API */ - NvKmsSyncPtOpParams params = { }; - params.fd_to_id_and_thresh.fd = - pChannelSyncObjects->u.syncpts.pre.u.fd; - ret = nvkms_syncpt_op(NVKMS_SYNCPT_OP_FD_TO_ID_AND_THRESH, - ¶ms); - if (!ret) { - return FALSE; - } - id = params.fd_to_id_and_thresh.id; - value = params.fd_to_id_and_thresh.thresh; - } else { - id = pChannelSyncObjects->u.syncpts.pre.u.raw.id; - value = pChannelSyncObjects->u.syncpts.pre.u.raw.value; - } - if (id >= NV_SYNCPT_GLOBAL_TABLE_LENGTH) { - return FALSE; - } - /*! Fill pre-syncpt related information in hardware state */ - pFlipSyncObject->u.syncpts.preSyncpt = id; - pFlipSyncObject->u.syncpts.preValue = value; - pFlipSyncObject->u.syncpts.isPreSyncptSpecified = TRUE; - pFlipSyncObject->usingSyncpt = TRUE; - - return TRUE; -} - -static NvBool AssignPostSyncptEvoHwState( - const NVDevEvoRec *pDevEvo, - NVEvoChannel *pChannel, - const struct NvKmsChannelSyncObjects *pChannelSyncObjects, - NVFlipSyncObjectEvoHwState *pFlipSyncObject) -{ - enum NvKmsSyncptType postType; - NvU32 threshold; - NvKmsSyncPtOpParams params = { }; - NvBool ret = TRUE; - - nvAssert(pChannelSyncObjects->useSyncpt); - - postType = pChannelSyncObjects->u.syncpts.requestedPostType; - - /*! - * It is possible that syncpt is mentioned but post-syncpt - * is not specified (case where only pre-syncpt used) - */ - if (postType == NVKMS_SYNCPT_TYPE_NONE) { - return TRUE; - } - - - /*! read max value of current syncpt id */ - params.read_maxval.id = pChannel->postSyncpt.id; - ret = nvkms_syncpt_op(NVKMS_SYNCPT_OP_READ_MAXVAL, ¶ms); - if (!ret) { - nvAssert(!"Failed syncpt op READ_MAXVAL"); - return FALSE; - } - - /*! return threshold to caller but increase only when programming hw */ - threshold = params.read_maxval.maxval + 1; - - /*! each channel associated with one post-syncpt */ - pFlipSyncObject->u.syncpts.postCtxDma = pChannel->postSyncpt.hCtxDma; - pFlipSyncObject->u.syncpts.postValue = threshold; - - pFlipSyncObject->usingSyncpt = TRUE; - - return TRUE; -} - -void nvFillPostSyncptReplyOneChannel( - NVEvoChannel *pChannel, - enum NvKmsSyncptType postType, - struct NvKmsSyncpt *postSyncpt, - const NVFlipSyncObjectEvoHwState *pHwSyncObject) -{ - if (postType == NVKMS_SYNCPT_TYPE_RAW) { - postSyncpt->u.raw.id = pChannel->postSyncpt.id; - postSyncpt->u.raw.value = pHwSyncObject->u.syncpts.postValue; - postSyncpt->type = NVKMS_SYNCPT_TYPE_RAW; - } else if (postType == NVKMS_SYNCPT_TYPE_FD) { - NvBool ret = TRUE; - NvKmsSyncPtOpParams params = { }; - params.id_and_thresh_to_fd.id = pChannel->postSyncpt.id; - params.id_and_thresh_to_fd.thresh = - pHwSyncObject->u.syncpts.postValue; - - ret = nvkms_syncpt_op(NVKMS_SYNCPT_OP_ID_AND_THRESH_TO_FD, ¶ms); - if (!ret) { - nvAssert(!"Failed syncpt op ID_AND_THRESH_TO_FD"); - return; - } - postSyncpt->u.fd = params.id_and_thresh_to_fd.fd; - postSyncpt->type = NVKMS_SYNCPT_TYPE_FD; - } -} - -static void FillPostSyncptReply( - NVDevEvoRec *pDevEvo, - NvU32 sd, - const struct NvKmsFlipRequestOneSubDevice *pRequestOneSubDevice, - struct NvKmsFlipReplyOneSubDevice *pReplyOneSubDevice, - const struct NvKmsFlipWorkArea *pWorkArea) -{ - NvU32 head; - - /*! check for valid config */ - if (!pDevEvo->supportsSyncpts) { - return; - } - - for (head = 0; head < ARRAY_LEN(pRequestOneSubDevice->head); head++) { - const struct NvKmsFlipCommonParams *pRequestParams = - &pRequestOneSubDevice->head[head]; - struct NvKmsFlipCommonReplyOneHead *pReplyParams = - &pReplyOneSubDevice->head[head]; - const NVFlipEvoHwState *pFlipState = - &pWorkArea->sd[sd].head[head].newState; - NvU32 layer; - - for (layer = 0; layer < pDevEvo->head[head].numLayers; layer++) { - if (!pRequestParams->layer[layer].syncObjects.specified || - !pRequestParams->layer[layer].syncObjects.val.useSyncpt) { - continue; - } - - nvFillPostSyncptReplyOneChannel( - pDevEvo->head[head].layer[layer], - pRequestParams->layer[layer].syncObjects.val.u.syncpts.requestedPostType, - &pReplyParams->layer[layer].postSyncpt, - &pFlipState->layer[layer].syncObject); - } - } -} - -static NvBool GetPreSyncptCtxDma(NVDevEvoRec *pDevEvo, - NVEvoChannel *pChannel, const NvU32 id) -{ - NvU32 hSyncptCtxDma, hSyncpt; - - /*! use id value to check the global table */ - if (pDevEvo->preSyncptTable[id].hCtxDma == 0) { - /*! Register - allocate and bind ctxdma to syncpt*/ - if (!nvRmEvoAllocAndBindSyncpt(pDevEvo, - pChannel, - id, - &hSyncpt, - &hSyncptCtxDma)) { - nvAssert(!"Failed to register pre-syncpt"); - return FALSE; - } - - /*! Fill the Entry in Global Table */ - pDevEvo->preSyncptTable[id].hCtxDma = hSyncptCtxDma; - pDevEvo->preSyncptTable[id].hSyncpt = hSyncpt; - pDevEvo->preSyncptTable[id].channelMask |= pChannel->channelMask; - pDevEvo->preSyncptTable[id].id = id; - } else { - /*! - * syncpt found, just bind the context dma of this syncpt - * to the window if it is not already. - */ - if ((pDevEvo->preSyncptTable[id].channelMask & - pChannel->channelMask) == 0) { - - NvU32 ret = - nvRmEvoBindDispContextDMA(pDevEvo, - pChannel, - pDevEvo->preSyncptTable[id].hCtxDma); - if (ret != NVOS_STATUS_SUCCESS) { - nvAssert(!"Failed to bind pre-syncpt with ctxdma"); - } - pDevEvo->preSyncptTable[id].channelMask |= pChannel->channelMask; - /*! hSyncpt already allocated for id*/ - } - } - - return TRUE; -} - -static NvBool RegisterPreSyncpt(NVDevEvoRec *pDevEvo, - struct NvKmsFlipWorkArea *pWorkArea) -{ - NvU32 sd; - NvU32 ret = TRUE; - const NVDispEvoRec *pDispEvo; - - pDevEvo->pAllSyncptUsedInCurrentFlip = - nvCalloc(1, sizeof(NvBool) * NV_SYNCPT_GLOBAL_TABLE_LENGTH); - if (pDevEvo->pAllSyncptUsedInCurrentFlip == NULL) { - ret = FALSE; - goto done; - } - - FOR_ALL_EVO_DISPLAYS(pDispEvo, sd, pDevEvo) { - NvU32 head; - for (head = 0; head < ARRAY_LEN(pWorkArea->sd[sd].head); head++) { - NVFlipEvoHwState *pFlipState = - &pWorkArea->sd[sd].head[head].newState; - NvU32 layer; - - for (layer = 0; layer < ARRAY_LEN(pFlipState->layer); layer++) { - NVFlipSyncObjectEvoHwState *pFlipSyncObject = - &pFlipState->layer[layer].syncObject; - NvU32 preSyncpt = pFlipSyncObject->u.syncpts.preSyncpt; - - if (!pFlipState->dirty.layerSyncObjects[layer] || - !pFlipSyncObject->usingSyncpt || - !pFlipSyncObject->u.syncpts.isPreSyncptSpecified) { - continue; - } - - if (!GetPreSyncptCtxDma(pDevEvo, - pDevEvo->head[head].layer[layer], - preSyncpt)) { - ret = FALSE; - goto done; - } - - pDevEvo->pAllSyncptUsedInCurrentFlip[preSyncpt] = NV_TRUE; - } - } - } - -done: - nvFree(pDevEvo->pAllSyncptUsedInCurrentFlip); - pDevEvo->pAllSyncptUsedInCurrentFlip = NULL; - - return ret; -} - -void nvClearFlipEvoHwState( - NVFlipEvoHwState *pFlipState) -{ - NvU32 i; - - nvkms_memset(pFlipState, 0, sizeof(*pFlipState)); - - for (i = 0; i < ARRAY_LEN(pFlipState->layer); i++) { - pFlipState->layer[i].cscMatrix = NVKMS_IDENTITY_CSC_MATRIX; - } -} - -/*! - * Initialize NVFlipEvoHwState with a current snapshot from headState. - */ -void nvInitFlipEvoHwState( - const NVDevEvoRec *pDevEvo, - const NvU32 sd, - const NvU32 head, - NVFlipEvoHwState *pFlipState) -{ - NVDispEvoRec *pDispEvo = pDevEvo->gpus[sd].pDispEvo; - const NVEvoSubDevHeadStateRec *pSdHeadState; - NvU32 i; - - nvClearFlipEvoHwState(pFlipState); - - if (!nvHeadIsActive(pDispEvo, head)) { - return; - } - - pSdHeadState = &pDevEvo->gpus[sd].headState[head]; - - pFlipState->viewPortPointIn = pSdHeadState->viewPortPointIn; - pFlipState->cursor = pSdHeadState->cursor; - - ct_assert(ARRAY_LEN(pFlipState->layer) == ARRAY_LEN(pSdHeadState->layer)); - - for (i = 0; i < ARRAY_LEN(pFlipState->layer); i++) { - pFlipState->layer[i] = pSdHeadState->layer[i]; - } - - // pFlipState->usage describes the usage bounds that will be necessary after - // this flip is complete. Initialize it using pSdHeadState->targetUsage, - // which describes the usage bounds that will be required just before this - // flip occurs, rather than pSdHeadState->usage, which describes the usage - // bounds currently programmed into the hardware. - // - // pSdHeadState->usage may have higher bounds than pSdHeadState->targetUsage - // if TryLoweringUsageBounds has not yet noticed that a satellite channel is - // no longer in use, or a flip to NULL in a satellite channel is pending but - // has not yet occurred. - pFlipState->usage = pSdHeadState->targetUsage; - - pFlipState->disableMidFrameAndDWCFWatermark = - pSdHeadState->targetDisableMidFrameAndDWCFWatermark; -} - - -static NvBool IsLayerDirty(const struct NvKmsFlipCommonParams *pParams, - const NvU32 layer) -{ - return pParams->layer[layer].surface.specified || - pParams->layer[layer].sizeIn.specified || - pParams->layer[layer].sizeOut.specified || - pParams->layer[layer].outputPosition.specified || - pParams->layer[layer].completionNotifier.specified || - pParams->layer[layer].syncObjects.specified || - pParams->layer[layer].compositionParams.specified || - pParams->layer[layer].csc.specified || - pParams->layer[layer].hdr.specified || - pParams->layer[layer].colorspace.specified; -} +#include "nvkms-rm.h" /*! * Check whether the flipPermissions for pOpenDev allow the flipping * requested by NvKmsFlipCommonParams. */ -static NvBool CheckFlipPermissions( +NvBool nvCheckFlipPermissions( const struct NvKmsPerOpenDev *pOpenDev, const NVDevEvoRec *pDevEvo, const NvU32 sd, - const NvU32 head, + const NvU32 apiHead, const struct NvKmsFlipCommonParams *pParams) { const int dispIndex = pDevEvo->gpus[sd].pDispEvo->displayOwner; @@ -661,7 +48,7 @@ nvGetFlipPermissionsFromOpenDev(pOpenDev); const struct NvKmsModesetPermissions *pModesetPermissions = nvGetModesetPermissionsFromOpenDev(pOpenDev); - const NvU8 allLayersMask = NVBIT(pDevEvo->head[head].numLayers) - 1; + const NvU8 allLayersMask = NVBIT(pDevEvo->apiHead[apiHead].numLayers) - 1; NvU8 layerMask = 0; NvU32 layer; @@ -669,14 +56,14 @@ nvAssert(pFlipPermissions != NULL); nvAssert(pModesetPermissions != NULL); - layerMask = pFlipPermissions->disp[dispIndex].head[head].layerMask; + layerMask = pFlipPermissions->disp[dispIndex].head[apiHead].layerMask; /* * If the client has modeset permissions for this disp+head, allow * the client to also perform flips on any layer. */ if (!nvDpyIdListIsEmpty(pModesetPermissions->disp[dispIndex]. - head[head].dpyIdList)) { + head[apiHead].dpyIdList)) { layerMask = allLayersMask; } @@ -686,8 +73,8 @@ return FALSE; } - for (layer = 0; layer < pDevEvo->head[head].numLayers; layer++) { - if (IsLayerDirty(pParams, layer) && ((layerMask & NVBIT(layer)) == 0)) { + for (layer = 0; layer < pDevEvo->apiHead[apiHead].numLayers; layer++) { + if (nvIsLayerDirty(pParams, layer) && ((layerMask & NVBIT(layer)) == 0)) { return FALSE; } } @@ -695,2425 +82,377 @@ return TRUE; } -/*! - * Determine whether a base channel flip requires a non-tearing present mode. - * - * EVO requires a non-tearing flip when certain parameters are changing. See - * NV_DISP_BASE_STATE_ERROR_052 in dispClass024XBaseUpdateErrorChecks.mfs. - */ -static NvBool FlipRequiresNonTearingMode( - const NVDevEvoRec *pDevEvo, - const NvU32 head, - const NVFlipChannelEvoHwState *pOld, - const NVFlipChannelEvoHwState *pNew) -{ - // TODO: Do we need to care about the right eye here? The error check - // doesn't. - const NVSurfaceEvoRec *pOldSurf = pOld->pSurfaceEvo[NVKMS_LEFT]; - const NVSurfaceEvoRec *pNewSurf = pNew->pSurfaceEvo[NVKMS_LEFT]; - NvU32 oldHwFormat = 0, newHwFormat = 0; - - if (pOldSurf == NULL || pNewSurf == NULL) { - return TRUE; - } - - // If these functions actually return FALSE at this point, then something is - // really wrong... - if (!pDevEvo->hal->ValidateWindowFormat( - pOldSurf->format, NULL, &oldHwFormat)) { - nvAssert(FALSE); - } - - if (!pDevEvo->hal->ValidateWindowFormat( - pNewSurf->format, NULL, &newHwFormat)) { - nvAssert(FALSE); - } - - // Commented entries are things checked in the .mfs that are not yet - // supported in NVKMS. - return // SuperSample - oldHwFormat != newHwFormat || - // Gamma - // Layout (i.e. frame, field1, or field2) - pOldSurf->widthInPixels != pNewSurf->widthInPixels || - pOldSurf->heightInPixels != pNewSurf->heightInPixels || - pOldSurf->layout != pNewSurf->layout; - // UseGainOfs - // NewBaseLut -- USE_CORE_LUT is programmed in InitChannel* - // NewOutputLut -} - - -/*! - * Apply flip overrides if necessary. - * - * 1. Override swap intervals for VRR. - * 2. If the flip is changing certain parameters, override the tearing mode. - */ -static NvBool ApplyBaseFlipOverrides( - const NVDevEvoRec *pDevEvo, +static void FillPostSyncptReplyOneApiHead( + NVDevEvoRec *pDevEvo, const NvU32 sd, - const NvU32 head, - NVFlipChannelEvoHwState *pNew, - NvBool allowVrr) -{ - const NVDispEvoRec *pDispEvo = pDevEvo->gpus[sd].pDispEvo; - const NVFlipChannelEvoHwState *pOld = - &pDevEvo->gpus[sd].headState[head].layer[NVKMS_MAIN_LAYER]; - - // Apply VRR swap interval overrides. - // - // Note that this applies the overrides whenever the client requests VRR and - // VRR is enabled, regardless of whether actually activating it later - // succeeds. - if (allowVrr) { - if (!nvHeadIsActive(pDispEvo, head)) { - // - // XXX If VRR is allowed then modeset should have happened before - // base channel flip, currently we don't know how to do modeset - // and program base channel for VRR at same time. This should be - // revisited as part of bug 1731279. - // - return FALSE; - } - nvApplyVrrBaseFlipOverrides(pDevEvo->gpus[sd].pDispEvo, head, - pOld, pNew); - } - - if (!nvHeadIsActive(pDispEvo, head)) { - // - // This is possible when modeset and base flip happening at same time, - // tearing parameter does not make sense in that case, - // it should is disabled. - // - pNew->tearing = FALSE; - } else { - // Force non-tearing mode if EVO requires it. - if (FlipRequiresNonTearingMode(pDevEvo, head, pOld, pNew)) { - pNew->tearing = FALSE; - } - } - - return TRUE; -} - -static NvBool ValidateScalingUsageBounds( - const struct NvKmsScalingUsageBounds *pS, - const struct NvKmsScalingUsageBounds *pMaxS) -{ - return (pS->maxVDownscaleFactor <= pMaxS->maxVDownscaleFactor) && - (pS->maxHDownscaleFactor <= pMaxS->maxHDownscaleFactor) && - (pS->vTaps <= pMaxS->vTaps) && - (!pS->vUpscalingAllowed || pMaxS->vUpscalingAllowed); -} - -/*! - * Validate the requested usage bounds against the specified maximums. - */ -static NvBool ValidateUsageBounds( - const NVDevEvoRec *pDevEvo, - const NvU32 head, - const struct NvKmsUsageBounds *pUsage, - const struct NvKmsUsageBounds *pGuaranteedUsage) -{ - NvU32 i; - - for (i = 0; i < pDevEvo->head[head].numLayers; i++) { - const NvU64 supportedSurfaceFormatsUnion = - pUsage->layer[i].supportedSurfaceMemoryFormats | - pGuaranteedUsage->layer[i].supportedSurfaceMemoryFormats; - - if ((pUsage->layer[i].usable && !pGuaranteedUsage->layer[i].usable) || - (supportedSurfaceFormatsUnion != - pGuaranteedUsage->layer[i].supportedSurfaceMemoryFormats) || - !ValidateScalingUsageBounds(&pUsage->layer[i].scaling, - &pGuaranteedUsage->layer[i].scaling)) { - return FALSE; - } - } - - return TRUE; -} - -/*! - * Assign pFlipState->usage. - */ -static NvBool AssignUsageBounds( - const NVDevEvoRec *pDevEvo, - const NvU32 head, - NVFlipEvoHwState *pFlipState) + const NvU32 apiHead, + const struct NvKmsFlipCommonParams *pRequestParams, + struct NvKmsFlipCommonReplyOneHead *pReplyParams, + const struct NvKmsFlipWorkArea *pWorkArea) { - struct NvKmsUsageBounds *pUsage = &pFlipState->usage; - int i; - - for (i = 0; i < pDevEvo->head[head].numLayers; i++) { - const NVFlipChannelEvoHwState *pLayerFlipState = &pFlipState->layer[i]; - - nvInitScalingUsageBounds(pDevEvo, &pUsage->layer[i].scaling); - - if (pLayerFlipState->pSurfaceEvo[NVKMS_LEFT]) { - pUsage->layer[i].usable = TRUE; - pUsage->layer[i].supportedSurfaceMemoryFormats = - nvEvoGetFormatsWithEqualOrLowerUsageBound( - pLayerFlipState->pSurfaceEvo[NVKMS_LEFT]->format, - pDevEvo->caps.layerCaps[i].supportedSurfaceMemoryFormats); - - if (pDevEvo->hal->GetWindowScalingCaps) { - const NVEvoScalerCaps *pScalerCaps = - pDevEvo->hal->GetWindowScalingCaps(pDevEvo); - - if (!nvComputeScalingUsageBounds(pScalerCaps, - pLayerFlipState->sizeIn.width, - pLayerFlipState->sizeIn.height, - pLayerFlipState->sizeOut.width, - pLayerFlipState->sizeOut.height, - pLayerFlipState->hTaps, - pLayerFlipState->vTaps, - &pUsage->layer[i].scaling)) { - return FALSE; - } - } - - if (pLayerFlipState->maxDownscaleFactors.specified) { - struct NvKmsScalingUsageBounds *pTargetScaling = - &pFlipState->usage.layer[i].scaling; - - if ((pLayerFlipState->maxDownscaleFactors.vertical < - pTargetScaling->maxVDownscaleFactor) || - (pLayerFlipState->maxDownscaleFactors.horizontal < - pTargetScaling->maxHDownscaleFactor)) { - return FALSE; - } - - pTargetScaling->maxVDownscaleFactor = - pLayerFlipState->maxDownscaleFactors.vertical; - pTargetScaling->maxHDownscaleFactor = - pLayerFlipState->maxDownscaleFactors.horizontal; - } + /* XXX[2Heads1OR] Return per hardware-head post syncpt */ + const NvU32 head = nvGetPrimaryHwHead(pDevEvo->gpus[sd].pDispEvo, apiHead); + NvU32 layer; - } else { - pUsage->layer[i].usable = FALSE; - pUsage->layer[i].supportedSurfaceMemoryFormats = 0; - } + /*! check for valid config */ + if ((head == NV_INVALID_HEAD) || !pDevEvo->supportsSyncpts) { + return; } - return TRUE; -} - -void -nvOverrideScalingUsageBounds(const NVDevEvoRec *pDevEvo, - NvU32 head, - NVFlipEvoHwState *pFlipState, - const struct NvKmsUsageBounds *pPossibleUsage) -{ - NvU32 i; - - for (i = 0; i < pDevEvo->head[head].numLayers; i++) { - const NVFlipChannelEvoHwState *pLayerFlipState = &pFlipState->layer[i]; - const struct NvKmsScalingUsageBounds *pPossibleScaling = - &pPossibleUsage->layer[i].scaling; - struct NvKmsScalingUsageBounds *pTargetScaling = - &pFlipState->usage.layer[i].scaling; + for (layer = 0; layer < ARRAY_LEN(pRequestParams->layer); layer++) { + const NVFlipEvoHwState *pFlipState = + &pWorkArea->sd[sd].head[head].newState; - if (!pFlipState->usage.layer[i].usable) { + if (!pRequestParams->layer[layer].syncObjects.specified || + !pRequestParams->layer[layer].syncObjects.val.useSyncpt) { continue; } - if (!pLayerFlipState->maxDownscaleFactors.specified) { - const NvU16 possibleV = pPossibleScaling->maxVDownscaleFactor; - const NvU16 possibleH = pPossibleScaling->maxHDownscaleFactor; - NvU16 targetV = pTargetScaling->maxVDownscaleFactor; - NvU16 targetH = pTargetScaling->maxHDownscaleFactor; - - /* - * Calculate max H/V downscale factor by quantizing the range. - * - * E.g., - * max H/V downscale factor supported by HW is 4x for 5-tap and 2x - * for 2-tap mode. If 5-tap mode is required, the target usage bound - * that nvkms will attempt to program will either allow up to 2x - * downscaling, or up to 4x downscaling. If 2-tap mode is required, - * the target usage bound that NVKMS will attempt to program will - * allow up to 2x downscaling. Example: to downscale from 4096x2160 - * -> 2731x864 in 5-tap mode, NVKMS would specify up to 2x for the - * H downscale bound (required is 1.5x), and up to 4x for the V - * downscale bound (required is 2.5x). - */ - if (targetV > NV_EVO_SCALE_FACTOR_1X) { - const NvU16 possibleMid = - NV_EVO_SCALE_FACTOR_1X + ((possibleV - NV_EVO_SCALE_FACTOR_1X) / 2); - - if (targetV <= possibleMid) { - pTargetScaling->maxVDownscaleFactor = possibleMid; - } else { - pTargetScaling->maxVDownscaleFactor = possibleV; - } - } - - if (targetH > NV_EVO_SCALE_FACTOR_1X) { - const NvU16 possibleMid = - NV_EVO_SCALE_FACTOR_1X + ((possibleH - NV_EVO_SCALE_FACTOR_1X) / 2); - - if (targetH <= possibleMid) { - pTargetScaling->maxHDownscaleFactor = possibleMid; - } else { - pTargetScaling->maxHDownscaleFactor = possibleH; - } - } - } - - pTargetScaling->vTaps = pPossibleScaling->vTaps; - pTargetScaling->vUpscalingAllowed = pPossibleScaling->vUpscalingAllowed; + nvFillPostSyncptReplyOneChannel( + pDevEvo->head[head].layer[layer], + pRequestParams->layer[layer].syncObjects.val.u.syncpts.requestedPostType, + &pReplyParams->layer[layer].postSyncpt, + &pFlipState->layer[layer].syncObject); } } -static NvBool FlipTimeStampValidForChannel( - const NVEvoChannel *pChannel, - NvU64 timeStamp) -{ - if (pChannel->caps.validTimeStampBits < 64) { - const NvU64 validTimeStampMask = - NVBIT64(pChannel->caps.validTimeStampBits) - 1; - if ((timeStamp & ~validTimeStampMask) != 0) { - return FALSE; - } - } - return TRUE; -} - -static NvBool ValidatePerLayerCompParams( - const struct NvKmsCompositionParams *pCompParams, - const struct NvKmsCompositionCapabilities *pCaps, - NVSurfaceEvoPtr pSurfaceEvo) -{ - const NvKmsSurfaceMemoryFormatInfo *pFormatInfo = (pSurfaceEvo != NULL) ? - nvKmsGetSurfaceMemoryFormatInfo(pSurfaceEvo->format) : NULL; - const enum NvKmsCompositionColorKeySelect colorKeySelect = - pCompParams->colorKeySelect; - NvU32 match; - - if ((pCaps->supportedColorKeySelects & NVBIT(colorKeySelect)) == 0x0) { - return FALSE; - } - - NVKMS_COMPOSITION_FOR_MATCH_BITS(colorKeySelect, match) { - if ((pCaps->colorKeySelect[colorKeySelect].supportedBlendModes[match] & - NVBIT(pCompParams->blendingMode[match])) == 0x0) { - return FALSE; - } - - switch (pCompParams->blendingMode[match]) { - case NVKMS_COMPOSITION_BLENDING_MODE_NON_PREMULT_ALPHA: - case NVKMS_COMPOSITION_BLENDING_MODE_PREMULT_ALPHA: - if (pCompParams->surfaceAlpha != 0) { - return FALSE; - } - break; - default: - break; - } - } - - /* Match and nomatch pixels should not use alpha blending mode at once. */ - if ((colorKeySelect != NVKMS_COMPOSITION_COLOR_KEY_SELECT_DISABLE) && - (NvKmsIsCompositionModeUseAlpha(pCompParams->blendingMode[0])) && - (NvKmsIsCompositionModeUseAlpha(pCompParams->blendingMode[1]))) { - return FALSE; - } - - /* - * If surface is NULL, no further validation required. The composition - * parameters do not take effect if surface is NULL. - */ - if (pFormatInfo == NULL || pFormatInfo->isYUV) { - return TRUE; - } - - /* Disable color keying for 8 Bpp surfaces. */ - if ((colorKeySelect == NVKMS_COMPOSITION_COLOR_KEY_SELECT_SRC) || - (colorKeySelect == NVKMS_COMPOSITION_COLOR_KEY_SELECT_DST)) { - - if (pFormatInfo->rgb.bytesPerPixel > 4) { - return FALSE; - } - } - - return TRUE; -} - -static NvBool UpdateFlipEvoHwStateTf( - const NVDevEvoRec *pDevEvo, - const struct NvKmsFlipCommonParams *pParams, - NVFlipEvoHwState *pFlipState, - const NvU32 sd, - const NvU32 head) -{ - if (!pParams->tf.specified) { - return TRUE; - } - - // If enabling HDR... - // XXX HDR TODO: Handle other transfer functions - if (pParams->tf.val == NVKMS_OUTPUT_TF_PQ) { - NVDispEvoPtr pDispEvo = pDevEvo->pDispEvo[sd]; - - // Cannot be an SLI configuration. - // XXX HDR TODO: Test SLI Mosaic + HDR and remove this check - if (pDevEvo->numSubDevices > 1) { - return FALSE; - } - - // Sink must support HDR. - if (!nvIsHDRCapableHead(pDispEvo, nvHardwareHeadToApiHead(head))) { - return FALSE; - } - } - - pFlipState->dirty.tf = TRUE; - pFlipState->tf = pParams->tf.val; - - return TRUE; -} - -static NvBool UpdateFlipEvoHwStateHDRStaticMetadata( - const NVDevEvoRec *pDevEvo, - const struct NvKmsFlipCommonParams *pParams, - NVFlipEvoHwState *pFlipState, - NVFlipChannelEvoHwState *pHwState, - const NvU32 head, - const NvU32 layer) -{ - if (pParams->layer[layer].hdr.specified) { - if (pParams->layer[layer].hdr.enabled) { - // Don't allow enabling HDR on a layer that doesn't support it. - if (!pDevEvo->caps.layerCaps[layer].supportsHDR) { - return FALSE; - } - - pHwState->hdrStaticMetadata.val = - pParams->layer[layer].hdr.staticMetadata; - } - pHwState->hdrStaticMetadata.enabled = pParams->layer[layer].hdr.enabled; - - // Only mark dirty if layer supports HDR, otherwise this is a no-op. - if (pDevEvo->caps.layerCaps[layer].supportsHDR) { - pFlipState->dirty.hdrStaticMetadata = TRUE; - } - } - - return TRUE; -} -static NvBool UpdateLayerFlipEvoHwStateCommon( - const struct NvKmsPerOpenDev *pOpenDev, - const NVDevEvoRec *pDevEvo, - const NvU32 sd, - const NvU32 head, - const NvU32 layer, +static NvBool UpdateProposedFlipStateOneApiHead( + const NVDispEvoRec *pDispEvo, + const NvU32 apiHead, const struct NvKmsFlipCommonParams *pParams, - NVFlipEvoHwState *pFlipState) + NVProposedFlipStateOneApiHead *pProposedApiHead) { - const NVEvoChannel *pChannel = pDevEvo->head[head].layer[layer]; - NVFlipChannelEvoHwState *pHwState = &pFlipState->layer[layer]; - const NVEvoApiHandlesRec *pOpenDevSurfaceHandles = - nvGetSurfaceHandlesFromOpenDevConst(pOpenDev); - NvBool ret; - - if (pParams->layer[layer].surface.specified) { - ret = nvAssignSurfaceArray(pDevEvo, - pOpenDevSurfaceHandles, - pParams->layer[layer].surface.handle, - FALSE /* isUsedByCursorChannel */, - TRUE /* isUsedByLayerChannel */, - pHwState->pSurfaceEvo); - if (!ret) { - return FALSE; - } - - /* - * Verify the (rotation, reflectionX, reflectionY) is a - * combination currently supported. - */ - if ((NVBIT(NvKmsRRParamsToCapBit(&pParams->layer[layer].surface.rrParams)) & - pDevEvo->caps.validLayerRRTransforms) == 0) { - return FALSE; - } - pHwState->rrParams = pParams->layer[layer].surface.rrParams; - - } + const NVDispApiHeadStateEvoRec *pApiHeadState = + &pDispEvo->apiHeadState[apiHead]; - /* Verify the timestamp is in the valid range for this channel. */ - if (!FlipTimeStampValidForChannel(pChannel, - pParams->layer[layer].timeStamp)) { - return FALSE; - } - pHwState->timeStamp = pParams->layer[layer].timeStamp; + if (pParams->tf.specified) { + const NVDpyEvoRec *pDpyEvo = + nvGetOneArbitraryDpyEvo(pApiHeadState->activeDpys, pDispEvo); - if (pParams->layer[layer].syncObjects.specified) { - if (!pDevEvo->supportsSyncpts && - pParams->layer[layer].syncObjects.val.useSyncpt) { - return FALSE; - } + pProposedApiHead->dirty.hdr = TRUE; + pProposedApiHead->hdr.tf = pParams->tf.val; - nvkms_memset(&pFlipState->layer[layer].syncObject, - 0, - sizeof(pFlipState->layer[layer].syncObject)); - - if (pParams->layer[layer].syncObjects.val.useSyncpt) { - ret = AssignPreSyncptEvoHwState(pDevEvo, - &pParams->layer[layer].syncObjects.val, - &pHwState->syncObject); - if (!ret) { + // If enabling HDR... + // XXX HDR TODO: Handle other transfer functions + if (pParams->tf.val == NVKMS_OUTPUT_TF_PQ) { + // Cannot be an SLI configuration. + // XXX HDR TODO: Test SLI Mosaic + HDR and remove this check + if (pDispEvo->pDevEvo->numSubDevices > 1) { return FALSE; } - pFlipState->dirty.layerSyncObjects[layer] = TRUE; - ret = AssignPostSyncptEvoHwState(pDevEvo, - pDevEvo->head[head].layer[layer], - &pParams->layer[layer].syncObjects.val, - &pHwState->syncObject); - if (!ret) { + // Sink must support HDR. + if (!nvIsHDRCapableHead(pDispEvo, apiHead)) { return FALSE; } - } else { - if (pParams->layer[layer].syncObjects.val.u.semaphores.acquire.surface.surfaceHandle != 0 || - pParams->layer[layer].syncObjects.val.u.semaphores.release.surface.surfaceHandle != 0) { - if (pParams->layer[layer].skipPendingFlips) { - return FALSE; - } - } - ret = AssignSemaphoreEvoHwState(pDevEvo, - pOpenDevSurfaceHandles, - pChannel, - sd, - &pParams->layer[layer].syncObjects.val, - &pHwState->syncObject); - if (!ret) { + /* NVKMS_OUTPUT_TF_PQ requires the RGB color space */ + if (pProposedApiHead->hdr.colorSpace != + NV_KMS_DPY_ATTRIBUTE_CURRENT_COLOR_SPACE_RGB) { return FALSE; } } - } - - if (pHwState->pSurfaceEvo[NVKMS_LEFT]) { - pHwState->minPresentInterval = - pParams->layer[layer].minPresentInterval; - } else { - /* The hardware requires that MPI be 0 when disabled. */ - pHwState->minPresentInterval = 0; - } - - if (pParams->layer[layer].sizeIn.specified) { - pHwState->sizeIn = pParams->layer[layer].sizeIn.val; - } - - if (pParams->layer[layer].sizeOut.specified) { - pHwState->sizeOut = pParams->layer[layer].sizeOut.val; - } - - /* - * If supportsWindowMode = TRUE, the sizeIn/sizeOut dimensions can be - * any arbitrary (valid) values. - * - * If supportsWindowMode = FALSE (legacy EVO main layer), the sizeIn - * /sizeOut dimensions must match the size of the surface for that layer. - * - * Note that if sizeIn/Out dimensions are invalid i.e. with a width or - * height of zero, this will be rejected by a call to - * ValidateFlipChannelEvoHwState() later in the code path. - * - * Note that if scaling is unsupported, i.e. that sizeIn cannot differ - * from sizeOut, then any unsupported configurations will be caught by the - * ComputeWindowScalingTaps() call later on in this function. - */ - if (!pDevEvo->caps.layerCaps[layer].supportsWindowMode && - (pHwState->pSurfaceEvo[NVKMS_LEFT] != NULL)) { - const NVSurfaceEvoRec *pSurfaceEvo = - pHwState->pSurfaceEvo[NVKMS_LEFT]; - - if ((pHwState->sizeIn.width != pSurfaceEvo->widthInPixels) || - (pHwState->sizeIn.height != pSurfaceEvo->heightInPixels)) { - return FALSE; - } - - if ((pHwState->sizeOut.width != pSurfaceEvo->widthInPixels) || - (pHwState->sizeOut.height != pSurfaceEvo->heightInPixels)) { - return FALSE; - } - } - - /* - * Allow the client to specify non-origin outputPosition only if the - * layer supports window mode. - * - * If window mode is unsupported but the client specifies non-origin - * outputPosition, return FALSE. - */ - if (pDevEvo->caps.layerCaps[layer].supportsWindowMode) { - if (pParams->layer[layer].outputPosition.specified) { - const NvS16 x = pParams->layer[layer].outputPosition.val.x; - const NvS16 y = pParams->layer[layer].outputPosition.val.y; - if ((pHwState->outputPosition.x != x) || - (pHwState->outputPosition.y != y)) { - pHwState->outputPosition.x = x; - pHwState->outputPosition.y = y; - pFlipState->dirty.layerPosition[layer] = TRUE; - } - } - } else if (pParams->layer[layer].outputPosition.specified && - ((pParams->layer[layer].outputPosition.val.x != 0) || - (pParams->layer[layer].outputPosition.val.y != 0))) { - return FALSE; - } - - if (pParams->layer[layer].compositionParams.specified) { - pHwState->composition = - pParams->layer[layer].compositionParams.val; - } - - if (!UpdateFlipEvoHwStateHDRStaticMetadata( - pDevEvo, pParams, pFlipState, - pHwState, head, layer)) { - return FALSE; - } - - if (pParams->layer[layer].colorspace.specified) { - pHwState->colorspace = - pParams->layer[layer].colorspace.val; - } - - if (pHwState->composition.depth == 0) { - pHwState->composition.depth = - NVKMS_MAX_LAYERS_PER_HEAD - layer; - } - - /* XXX Move ValidatePerLayerCompParams() call to nvValidateFlipEvoHwState() */ - if (!ValidatePerLayerCompParams( - &pHwState->composition, - &pDevEvo->caps.layerCaps[layer].composition, - pHwState->pSurfaceEvo[NVKMS_LEFT])) { - return FALSE; - } - - if (!pDevEvo->hal->ComputeWindowScalingTaps(pDevEvo, - pChannel, - pHwState)) { - return FALSE; - } - if (pParams->layer[layer].completionNotifier.specified) { - ret = AssignCompletionNotifierEvoHwState( - pDevEvo, - pOpenDevSurfaceHandles, - &pParams->layer[layer].completionNotifier.val, - pChannel, - &pFlipState->layer[layer].completionNotifier); - if (!ret) { + if (!nvChooseColorRangeEvo(pParams->tf.val, + pDpyEvo->requestedColorRange, + pProposedApiHead->hdr.colorSpace, + pProposedApiHead->hdr.colorBpc, + &pProposedApiHead->hdr.colorRange)) { return FALSE; } } - if (pParams->layer[layer].maxDownscaleFactors.specified) { - pFlipState->layer[layer].maxDownscaleFactors.vertical = - pParams->layer[layer].maxDownscaleFactors.vertical; - pFlipState->layer[layer].maxDownscaleFactors.horizontal = - pParams->layer[layer].maxDownscaleFactors.horizontal; - pFlipState->layer[layer].maxDownscaleFactors.specified = TRUE; - } else { - pFlipState->layer[layer].maxDownscaleFactors.vertical = 0; - pFlipState->layer[layer].maxDownscaleFactors.horizontal = 0; - pFlipState->layer[layer].maxDownscaleFactors.specified = FALSE; - } - - pFlipState->dirty.layer[layer] = TRUE; - - return TRUE; -} - -static NvBool UpdateMainLayerFlipEvoHwState( - const struct NvKmsPerOpenDev *pOpenDev, - const NVDevEvoRec *pDevEvo, - const NvU32 sd, - const NvU32 head, - const struct NvKmsFlipCommonParams *pParams, - NVFlipEvoHwState *pFlipState, - NvBool allowVrr) -{ - const NVEvoChannel *pChannel = - pDevEvo->head[head].layer[NVKMS_MAIN_LAYER]; - NVFlipChannelEvoHwState *pHwState = &pFlipState->layer[NVKMS_MAIN_LAYER]; - - if (!IsLayerDirty(pParams, NVKMS_MAIN_LAYER)) { - return TRUE; - } - - if (!UpdateLayerFlipEvoHwStateCommon(pOpenDev, pDevEvo, sd, head, - NVKMS_MAIN_LAYER, - pParams, pFlipState)) { - return FALSE; - } - - if (pParams->layer[NVKMS_MAIN_LAYER].csc.specified) { - if (pParams->layer[NVKMS_MAIN_LAYER].csc.useMain) { - return FALSE; - } else { - pHwState->cscMatrix = pParams->layer[NVKMS_MAIN_LAYER].csc.matrix; - } - } - - if (pParams->layer[NVKMS_MAIN_LAYER].surface.specified) { - if (pParams->layer[NVKMS_MAIN_LAYER].perEyeStereoFlip && - !pChannel->caps.perEyeStereoFlips) { - return FALSE; - } - - pHwState->perEyeStereoFlip = - pParams->layer[NVKMS_MAIN_LAYER].perEyeStereoFlip; - } - - if (pParams->layer[NVKMS_MAIN_LAYER].tearing && !pChannel->caps.tearingFlips) { - return FALSE; - } - - // EVO will throw an invalid argument exception if - // minPresentInterval is too large, or if tearing is enabled and - // it's not zero. - if (pParams->layer[NVKMS_MAIN_LAYER].minPresentInterval > NV_MAX_SWAP_INTERVAL || - (pParams->layer[NVKMS_MAIN_LAYER].tearing && - pParams->layer[NVKMS_MAIN_LAYER].minPresentInterval != 0)) { - return FALSE; - } - - pHwState->tearing = pParams->layer[NVKMS_MAIN_LAYER].tearing; - - if (!ApplyBaseFlipOverrides(pDevEvo, - sd, head, &pFlipState->layer[NVKMS_MAIN_LAYER], - allowVrr)) { - return FALSE; + if (pParams->viewPortIn.specified) { + pProposedApiHead->dirty.viewPortPointIn = TRUE; + pProposedApiHead->viewPortPointIn = pParams->viewPortIn.point; } - pFlipState->skipLayerPendingFlips[NVKMS_MAIN_LAYER] = - pParams->layer[NVKMS_MAIN_LAYER].skipPendingFlips; - return TRUE; } -NvBool -nvAssignCursorSurface(const struct NvKmsPerOpenDev *pOpenDev, - const NVDevEvoRec *pDevEvo, - const struct NvKmsSetCursorImageCommonParams *pImgParams, - NVSurfaceEvoPtr *pSurfaceEvo) - +void nvCancelSDRTransitionTimer(NVDispApiHeadStateEvoRec *pApiHeadState) { - const NVEvoApiHandlesRec *pOpenDevSurfaceHandles = - nvGetSurfaceHandlesFromOpenDevConst(pOpenDev); - NVSurfaceEvoPtr pSurfaceEvos[NVKMS_MAX_EYES] = { }; - - if (!nvGetCursorImageSurfaces(pDevEvo, - pOpenDevSurfaceHandles, - pImgParams, - pSurfaceEvos)) { - return FALSE; - } - - /* XXX NVKMS TODO: add support for stereo cursor */ - if (pSurfaceEvos[NVKMS_RIGHT] != NULL) { - return FALSE; - } - - if (pSurfaceEvos[NVKMS_LEFT] != NULL) { - if (!ValidatePerLayerCompParams(&pImgParams->cursorCompParams, - &pDevEvo->caps.cursorCompositionCaps, - pSurfaceEvos[NVKMS_LEFT])) { - return FALSE; - } - } - - *pSurfaceEvo = pSurfaceEvos[NVKMS_LEFT]; - - return TRUE; + nvkms_free_timer(pApiHeadState->hdrToSdrTransitionTimer); + pApiHeadState->hdrToSdrTransitionTimer = NULL; } -static NvBool UpdateCursorLayerFlipEvoHwState( - const struct NvKmsPerOpenDev *pOpenDev, - const NVDevEvoRec *pDevEvo, - const struct NvKmsFlipCommonParams *pParams, - NVFlipEvoHwState *pFlipState) +static void SDRTransition(void *dataPtr, NvU32 apiHead) { - if (pParams->cursor.imageSpecified) { - if (!nvAssignCursorSurface(pOpenDev, pDevEvo, &pParams->cursor.image, - &pFlipState->cursor.pSurfaceEvo)) { - return FALSE; - } + NvU32 head; + NVDispEvoRec *pDispEvo = dataPtr; + NVDispApiHeadStateEvoRec *pApiHeadState = + &pDispEvo->apiHeadState[apiHead]; + NVDpyEvoPtr pDpyEvo = + nvGetOneArbitraryDpyEvo(pApiHeadState->activeDpys, pDispEvo); - if (pFlipState->cursor.pSurfaceEvo != NULL) { - pFlipState->cursor.cursorCompParams = - pParams->cursor.image.cursorCompParams; - } + nvCancelSDRTransitionTimer(pApiHeadState); - pFlipState->dirty.cursorSurface = TRUE; + if (pDpyEvo == NULL) { + return; } - if (pParams->cursor.positionSpecified) { - pFlipState->cursor.x = pParams->cursor.position.x; - pFlipState->cursor.y = pParams->cursor.position.y; + nvAssert(pApiHeadState->hwHeadsMask != 0); - pFlipState->dirty.cursorPosition = TRUE; + FOR_EACH_EVO_HW_HEAD_IN_MASK(pApiHeadState->hwHeadsMask, head) { + NVDispHeadStateEvoRec *pHeadState = + &pDispEvo->headState[head]; + nvAssert(pHeadState->hdr.outputState == + NVKMS_HDR_OUTPUT_STATE_TRANSITIONING_TO_SDR); + pHeadState->hdr.outputState = NVKMS_HDR_OUTPUT_STATE_SDR; } - return TRUE; + nvUpdateInfoFrames(pDpyEvo); } -static NvBool UpdateOverlayLayerFlipEvoHwState( - const struct NvKmsPerOpenDev *pOpenDev, - const NVDevEvoRec *pDevEvo, - const NvU32 sd, - const NvU32 head, - const NvU32 layer, - const struct NvKmsFlipCommonParams *pParams, - NVFlipEvoHwState *pFlipState) +static +void ScheduleSDRTransitionTimer(NVDispEvoRec *pDispEvo, const NvU32 apiHead) { - NVFlipChannelEvoHwState *pHwState = &pFlipState->layer[layer]; - - nvAssert(layer != NVKMS_MAIN_LAYER); - - if (!IsLayerDirty(pParams, layer)) { - return TRUE; - } - - if (pParams->layer[layer].skipPendingFlips || - pParams->layer[layer].perEyeStereoFlip) { - return FALSE; - } - - if (!UpdateLayerFlipEvoHwStateCommon(pOpenDev, pDevEvo, sd, head, layer, - pParams, pFlipState)) { - return FALSE; - } + NVDispApiHeadStateEvoRec *pApiHeadState = + &pDispEvo->apiHeadState[apiHead]; - if (pParams->layer[layer].csc.specified) { - if (pParams->layer[layer].csc.useMain) { - if (pFlipState->layer[NVKMS_MAIN_LAYER].pSurfaceEvo[NVKMS_LEFT]) { - pHwState->cscMatrix = - pFlipState->layer[NVKMS_MAIN_LAYER].cscMatrix; - } - } else { - pHwState->cscMatrix = pParams->layer[layer].csc.matrix; - } - } + nvAssert(!pApiHeadState->hdrToSdrTransitionTimer); - return TRUE; + pApiHeadState->hdrToSdrTransitionTimer = + nvkms_alloc_timer(SDRTransition, + pDispEvo, + apiHead, + 2000000 /* 2 seconds */); } -/*! - * Update the NVFlipEvoHwState, using NvKmsFlipCommonParams. - * - * Propagate the requested configuration from NvKmsFlipCommonParams to - * NVFlipEvoHwState, performing steps such as translating from - * NvKmsSurfaceHandle to NVSurfaceEvoRecs. Validate the NvKmsFlipCommonParams - * parameters, but defer more general validation of the resulting - * NVFlipEvoHwState until nvValidateFlipEvoHwState(), which callers must call - * separately. - * - * The NVFlipEvoHwState should first be initialized by calling - * nvInitFlipEvoHwState(). - * - * No NVKMS hardware or software state should be altered here, because - * this function is used before we have decided to commit the proposed - * NVFlipEvoHwState to hardware. - * - * \param[in] pOpenDev The pOpenDev of the client doing the flip. - * \param[in] pDevEvo The device on which the surface image will be set. - * \param[in] sd The subdevice for the flip, as specified by the - * client. - * \param[in] head The head for the flip, as specified by the client. - * \param[in] pParams The requested flip, NvKmsFlipCommonParams. - * \param[in,out] pFlipState The resulting NVFlipEvoHwState. - * \param[in] allowVrr Whether VRR flipping should be allowed. - * \param[in] pPossibleUsage Possible usage. - * - * \return If pFlipState could be updated, return TRUE. - * Otherwise, return FALSE. - */ -NvBool nvUpdateFlipEvoHwState( - const struct NvKmsPerOpenDev *pOpenDev, - const NVDevEvoRec *pDevEvo, - const NvU32 sd, - const NvU32 head, - const struct NvKmsFlipCommonParams *pParams, - NVFlipEvoHwState *pFlipState, - NvBool allowVrr) +static NvBool GetAllowVrr(const NVDevEvoRec *pDevEvo, + const struct NvKmsFlipRequestOneHead *pFlipHead, + NvU32 numFlipHeads, + NvBool allowVrr, + NvBool *pApplyAllowVrr) { - NvU32 layer; - - if (!CheckFlipPermissions(pOpenDev, pDevEvo, sd, head, pParams)) { - return FALSE; - } - - if (pParams->viewPortIn.specified) { - pFlipState->dirty.viewPortPointIn = TRUE; - pFlipState->viewPortPointIn = pParams->viewPortIn.point; - } - - if (!UpdateCursorLayerFlipEvoHwState(pOpenDev, pDevEvo, pParams, - pFlipState)) { - return FALSE; - } - - if (!UpdateFlipEvoHwStateTf(pDevEvo, pParams, pFlipState, sd, head)) { - return FALSE; - } - - for (layer = 0; layer < pDevEvo->head[head].numLayers; layer++) { - if (layer == NVKMS_MAIN_LAYER) { - if (!UpdateMainLayerFlipEvoHwState(pOpenDev, pDevEvo, sd, head, - pParams, pFlipState, allowVrr)) { - return FALSE; - } - continue; - } - - if (!UpdateOverlayLayerFlipEvoHwState(pOpenDev, pDevEvo, sd, head, - layer, pParams, pFlipState)) { - return FALSE; - } - } + NvU32 sd, i; + const NVDispEvoRec *pDispEvo; + const NvU32 requestedApiHeadCount = numFlipHeads; + NvU32 activeApiHeadCount, dirtyMainLayerCount; - if (!AssignUsageBounds(pDevEvo, head, pFlipState)) { - return FALSE; - } + *pApplyAllowVrr = FALSE; - /* - * If there is active cursor/cropped-window(overlay) without full screen - * window(base/core) then NVKMS is supposed to disable MidFrame/DWCF - * watermark. + /*! + * Count active heads so we can make a decision about VRR + * and register syncpts if specified. */ + activeApiHeadCount = dirtyMainLayerCount = 0; - pFlipState->disableMidFrameAndDWCFWatermark = FALSE; - - if (NV5070_CTRL_SYSTEM_GET_CAP( - pDevEvo->capsBits, - NV5070_CTRL_SYSTEM_CAPS_BUG_2052012_GLITCHY_MCLK_SWITCH) && - !pFlipState->layer[NVKMS_MAIN_LAYER].pSurfaceEvo[NVKMS_LEFT]) { - - if (pFlipState->cursor.pSurfaceEvo != NULL) { - pFlipState->disableMidFrameAndDWCFWatermark = TRUE; - } else { - NvU32 layer; - - /* - * XXX TODO: Check the output size of the overlay in order - * to determine if it will be fullscreen or not. - */ - for (layer = 0; layer < pDevEvo->head[head].numLayers; layer++) { - if (layer != NVKMS_MAIN_LAYER && - pFlipState->layer[layer].pSurfaceEvo[NVKMS_LEFT] != NULL) { - pFlipState->disableMidFrameAndDWCFWatermark = TRUE; - break; - } + FOR_ALL_EVO_DISPLAYS(pDispEvo, sd, pDevEvo) { + NvU32 apiHead; + for (apiHead = 0; apiHead < pDevEvo->numApiHeads; apiHead++) { + if (nvApiHeadIsActive(pDispEvo, apiHead)) { + activeApiHeadCount++; } } } - return TRUE; -} - -/* - * Checks that if the surface is NULL (i.e. no image will be shown), various - * other elements must be NULL as well. If the surface is not NULL, verifies - * that the sizeIn/Out have nonzero values. - */ -inline static NvBool ValidateFlipChannelEvoHwState( - const NVFlipChannelEvoHwState *pState) -{ - if (pState->pSurfaceEvo[NVKMS_LEFT] != NULL) { - /* Verify sizes are valid. */ - if ((pState->sizeIn.width == 0) || (pState->sizeIn.height == 0) || - (pState->sizeOut.width == 0) || (pState->sizeOut.height == 0)) { - return FALSE; - } - - return TRUE; - } - - if (pState->completionNotifier.surface.pSurfaceEvo != NULL) { - return FALSE; - } - - if (!pState->syncObject.usingSyncpt) { - if (pState->syncObject.u.semaphores.acquireSurface.pSurfaceEvo != NULL) { - return FALSE; - } - - if (pState->syncObject.u.semaphores.releaseSurface.pSurfaceEvo != NULL) { - return FALSE; - } - } - - return TRUE; -} - -static NvBool ValidateSurfaceSize( - const NVDevEvoRec *pDevEvo, - const NVSurfaceEvoRec *pSurfaceEvo, - const struct NvKmsRect *sourceFetchRect) -{ - NvU8 planeIndex; - - if ((pSurfaceEvo->widthInPixels > pDevEvo->caps.maxWidthInPixels) || - (pSurfaceEvo->heightInPixels > pDevEvo->caps.maxHeight)) { - return FALSE; - } - - FOR_ALL_VALID_PLANES(planeIndex, pSurfaceEvo) { - - NvU64 planePitch = pSurfaceEvo->planes[planeIndex].pitch; - - /* - * Convert planePitch to units of bytes if it's currently specified in - * units of blocks. Each block is 64-bytes wide. - */ - if (pSurfaceEvo->layout == NvKmsSurfaceMemoryLayoutBlockLinear) { - planePitch <<= NVKMS_BLOCK_LINEAR_LOG_GOB_WIDTH; - } - - if (planePitch > pDevEvo->caps.maxWidthInBytes) { - return FALSE; + for (i = 0; i < numFlipHeads; i++) { + if (nvIsLayerDirty(&pFlipHead[i].flip, NVKMS_MAIN_LAYER)) { + dirtyMainLayerCount++; } } - if (!pDevEvo->hal->ValidateWindowFormat(pSurfaceEvo->format, - sourceFetchRect, - NULL)) { - return FALSE; - } - - return TRUE; -} - -static NvBool -ValidateMainFlipChannelEvoHwState(const NVDevEvoRec *pDevEvo, - const NVFlipChannelEvoHwState *pHwState, - const NVHwModeTimingsEvo *pTimings, - struct NvKmsPoint viewPortPointIn) -{ - NvU32 eye; - const NVSurfaceEvoRec *pFirstSurfaceEvo = NULL; - /* - * This struct represents the source fetch rectangle for a given surface, - * and will be populated later as such. This function doesn't explicitly set - * sourceFetchRect.{x,y} because NVKMS currently doesn't support programming - * source fetch offsets, so the init value of 0 should be fine for both of - * these fields. + * Deactivate VRR if only a subset of the heads are requested or + * only a subset of the heads are being flipped. */ - struct NvKmsRect sourceFetchRect = {0}; - - if (!ValidateFlipChannelEvoHwState(pHwState)) { - return FALSE; - } - - for (eye = 0; eye < NVKMS_MAX_EYES; eye++) { - const NVSurfaceEvoRec *pSurfaceEvo = pHwState->pSurfaceEvo[eye]; - - if (pSurfaceEvo == NULL) { - continue; - } - - if (pFirstSurfaceEvo == NULL) { - pFirstSurfaceEvo = pSurfaceEvo; - } else if (pSurfaceEvo->widthInPixels != - pFirstSurfaceEvo->widthInPixels || - pSurfaceEvo->heightInPixels != - pFirstSurfaceEvo->heightInPixels) { - return FALSE; - } - - sourceFetchRect.width = pHwState->sizeIn.width; - sourceFetchRect.height = pHwState->sizeIn.height; - - if (!ValidateSurfaceSize(pDevEvo, pSurfaceEvo, &sourceFetchRect)) { - return FALSE; - } - - /* The use of A_plus_B_greater_than_C_U16 is only valid if these - * fit in a U16 */ - nvAssert(pSurfaceEvo->widthInPixels <= NV_U16_MAX); - nvAssert(pSurfaceEvo->heightInPixels <= NV_U16_MAX); - /* And the checks above in ValidateSurfaceSize should have - * guaranteed that. */ - nvAssert(pDevEvo->caps.maxWidthInPixels <= NV_U16_MAX); - nvAssert(pDevEvo->caps.maxHeight <= NV_U16_MAX); - - /* - * Validate that the requested viewport parameters fit within the - * specified surface, unless the main layer is allowed to be smaller - * than the viewport. - */ - if (!pDevEvo->caps.layerCaps[NVKMS_MAIN_LAYER].supportsWindowMode) { - if (A_plus_B_greater_than_C_U16(viewPortPointIn.x, - pTimings->viewPort.in.width, - pSurfaceEvo->widthInPixels)) { - return FALSE; - } - - if (A_plus_B_greater_than_C_U16(viewPortPointIn.y, - pTimings->viewPort.in.height, - pSurfaceEvo->heightInPixels)) { - return FALSE; - } - } + if ((activeApiHeadCount != requestedApiHeadCount) || + (activeApiHeadCount != dirtyMainLayerCount)) { + allowVrr = FALSE; } - return TRUE; -} - -static NvBool -ValidateOverlayFlipChannelEvoHwState(const NVDevEvoRec *pDevEvo, - const NVFlipChannelEvoHwState *pHwState) -{ - const NVSurfaceEvoRec *pSurfaceEvo = pHwState->pSurfaceEvo[NVKMS_LEFT]; - /* - * This struct represents the source fetch rectangle for a given surface, - * and will be populated later as such. This function doesn't explicitly set - * sourceFetchRect.{x,y} because NVKMS currently doesn't support programming - * source fetch offsets, so the init value of 0 should be fine for both of - * these fields. + * Apply NvKmsFlipRequest::allowVrr + * only if at least one main layer is became dirty. */ - struct NvKmsRect sourceFetchRect = {0}; - - if (!ValidateFlipChannelEvoHwState(pHwState)) { - return FALSE; - } - - if (pSurfaceEvo == NULL) { - return TRUE; - } - - sourceFetchRect.width = pHwState->sizeIn.width; - sourceFetchRect.height = pHwState->sizeIn.height; - - if (!ValidateSurfaceSize(pDevEvo, pSurfaceEvo, &sourceFetchRect)) { - return FALSE; - } - - /* Validate input size against surface size. */ - if (pHwState->sizeIn.width > pSurfaceEvo->widthInPixels || - pHwState->sizeIn.height > pSurfaceEvo->heightInPixels) { - return FALSE; - } - - return TRUE; -} - -static NvBool -ValidateHDR(const NVDevEvoRec *pDevEvo, - const NvU32 head, - const NVFlipEvoHwState *pFlipState) -{ - NvU32 staticMetadataCount = 0; - NvU32 layerSupportedCount = 0; - - NvU32 layer; - - for (layer = 0; layer < pDevEvo->head[head].numLayers; layer++) { - if (pDevEvo->caps.layerCaps[layer].supportsHDR) { - layerSupportedCount++; - } - - if (pFlipState->layer[layer].hdrStaticMetadata.enabled) { - staticMetadataCount++; - - /* - * If HDR static metadata is enabled, we may need TMO. CSC11 will be - * used by NVKMS to convert from linear FP16 LMS to linear FP16 RGB. - * As such, the user-supplied precomp CSC can't be programmed into - * CSC11 in this case. - */ - if (!nvIsCscMatrixIdentity(&pFlipState->layer[layer].cscMatrix)) { - return FALSE; - } - - // Already checked in UpdateFlipEvoHwStateHDRStaticMetadata() - nvAssert(pDevEvo->caps.layerCaps[layer].supportsHDR); - } - } - - // If enabling HDR... - // XXX HDR TODO: Handle other transfer functions - if (pFlipState->tf == NVKMS_OUTPUT_TF_PQ) { - // At least one layer must have static metadata. - if (staticMetadataCount == 0) { - return FALSE; - } - - // At least one layer must support HDR, implied above. - nvAssert(layerSupportedCount != 0); - } - - // Only one layer can specify HDR static metadata. - // XXX HDR TODO: Support multiple layers with HDR static metadata - if (staticMetadataCount > 1) { - return FALSE; - } - - return TRUE; -} - -static NvBool -ValidateColorspace(const NVDevEvoRec *pDevEvo, - const NvU32 head, - const NVFlipEvoHwState *pFlipState) -{ - NvU32 layer; - - for (layer = 0; layer < pDevEvo->head[head].numLayers; layer++) { - if ((pFlipState->layer[layer].colorspace != - NVKMS_INPUT_COLORSPACE_NONE)) { - - NVSurfaceEvoPtr pSurfaceEvo = - pFlipState->layer[layer].pSurfaceEvo[NVKMS_LEFT]; - const NvKmsSurfaceMemoryFormatInfo *pFormatInfo = - (pSurfaceEvo != NULL) ? - nvKmsGetSurfaceMemoryFormatInfo(pSurfaceEvo->format) : NULL; - - // XXX HDR TODO: Support YUV. - if ((pFormatInfo == NULL) || pFormatInfo->isYUV) { - return FALSE; - } - - // FP16 is only for use with scRGB. - if ((pFlipState->layer[layer].colorspace != - NVKMS_INPUT_COLORSPACE_SCRGB_LINEAR) && - ((pSurfaceEvo->format == - NvKmsSurfaceMemoryFormatRF16GF16BF16AF16) || - (pSurfaceEvo->format == - NvKmsSurfaceMemoryFormatRF16GF16BF16XF16))) { - return FALSE; - } - - // scRGB is only compatible with FP16. - if ((pFlipState->layer[layer].colorspace == - NVKMS_INPUT_COLORSPACE_SCRGB_LINEAR) && - !((pSurfaceEvo->format == - NvKmsSurfaceMemoryFormatRF16GF16BF16AF16) || - (pSurfaceEvo->format == - NvKmsSurfaceMemoryFormatRF16GF16BF16XF16))) { - return FALSE; - } - } - } - - return TRUE; -} - -static NvU32 ValidateCompositionDepth(const NVFlipEvoHwState *pFlipState, - const NvU32 layer) -{ - NvU32 tmpLayer; - - if (pFlipState->layer[layer].pSurfaceEvo[NVKMS_LEFT] == NULL) { - return TRUE; - } - - /* Depth should be different for each of the layers owned by the head */ - for (tmpLayer = 0; tmpLayer < ARRAY_LEN(pFlipState->layer); tmpLayer++) { - if (pFlipState->layer[tmpLayer].pSurfaceEvo[NVKMS_LEFT] == NULL) { - continue; - } - - if ((tmpLayer != layer) && - (pFlipState->layer[tmpLayer].composition.depth == - pFlipState->layer[layer].composition.depth)) { - return FALSE; - } - } - - /* Depth of the main layer should be the greatest one */ - if (pFlipState->layer[NVKMS_MAIN_LAYER].pSurfaceEvo[NVKMS_LEFT] != NULL) { - if (pFlipState->layer[NVKMS_MAIN_LAYER].composition.depth < - pFlipState->layer[layer].composition.depth) { - return FALSE; - } - } - - return TRUE; -} - -/*! - * Perform validation of the the given NVFlipEvoHwState. - */ -NvBool nvValidateFlipEvoHwState( - const NVDevEvoRec *pDevEvo, - const NvU32 head, - const NVHwModeTimingsEvo *pTimings, - const NVFlipEvoHwState *pFlipState) -{ - NvU32 layer; - - for (layer = 0; layer < pDevEvo->head[head].numLayers; layer++) { - if (!ValidateCompositionDepth(pFlipState, layer)) { - return FALSE; - } - - if (layer == NVKMS_MAIN_LAYER) { - if (!ValidateMainFlipChannelEvoHwState(pDevEvo, - &pFlipState->layer[layer], - pTimings, - pFlipState->viewPortPointIn)) { - return FALSE; - } - } else { - const NVFlipChannelEvoHwState *pMainLayerState = - &pFlipState->layer[NVKMS_MAIN_LAYER]; - - /* - * No overlay layer should be enabled if the main - * layer is disabled. - */ - if ((pMainLayerState->pSurfaceEvo[NVKMS_LEFT] == NULL) && - (pFlipState->layer[layer].pSurfaceEvo[NVKMS_LEFT] != NULL)) { - return FALSE; - } - - if (!pFlipState->dirty.layer[layer]) { - continue; - } - - if (!ValidateOverlayFlipChannelEvoHwState(pDevEvo, - &pFlipState->layer[layer])) { - return FALSE; - } - } - } - - if (!ValidateHDR(pDevEvo, head, pFlipState)) { - return FALSE; - } - - if (!ValidateColorspace(pDevEvo, head, pFlipState)) { - return FALSE; + if (dirtyMainLayerCount > 0) { + *pApplyAllowVrr = TRUE; } - /* XXX NVKMS TODO: validate cursor x,y against current viewport in? */ - - return ValidateUsageBounds(pDevEvo, - head, - &pFlipState->usage, - &pTimings->viewPort.possibleUsage); + return allowVrr; } -/* - * Record in the updateState that the given channel needs interlocked - * window immediate updates. - */ -static void UpdateWinImmInterlockState(NVDevEvoPtr pDevEvo, - NVEvoUpdateState *updateState, - const NVEvoChannel *pChannel) +static void FillNvKmsFlipReply(NVDevEvoRec *pDevEvo, + struct NvKmsFlipWorkArea *pWorkArea, + const NvBool applyAllowVrr, + const NvS32 vrrSemaphoreIndex, + const struct NvKmsFlipRequestOneHead *pFlipHead, + NvU32 numFlipHeads, + struct NvKmsFlipReply *reply) { - const NvU32 subDevMask = nvPeekEvoSubDevMask(pDevEvo); - NvU32 sd; + NvU32 i; - for (sd = 0; sd < pDevEvo->numSubDevices; sd++) { - if (subDevMask & (1 << sd)) { - updateState->subdev[sd].winImmInterlockMask |= - pChannel->channelMask; - } + if (reply == NULL) { + return; } -} - -/*! - * Record in the updateState that the given channel's method are eligible for - * flip locking. - */ -static void UpdateUpdateFlipLockState(NVDevEvoPtr pDevEvo, - NVEvoUpdateState *updateState, - const NVEvoChannel *pChannel) -{ - const NvU32 subDevMask = nvPeekEvoSubDevMask(pDevEvo); - NvU32 sd; - for (sd = 0; sd < pDevEvo->numSubDevices; sd++) { - if (subDevMask & (1 << sd)) { - updateState->subdev[sd].flipLockQualifyingMask |= - pChannel->channelMask; - } + for (i = 0; i < numFlipHeads; i++) { + const NvU32 sd = pFlipHead[i].sd; + const NvU32 apiHead = pFlipHead[i].head; + + FillPostSyncptReplyOneApiHead(pDevEvo, + sd, + apiHead, + &pFlipHead[i].flip, + &reply->flipHead[i], + pWorkArea); } -} - -static void CancelSDRTransitionTimer(NVDispHeadStateEvoRec *pHeadState) -{ - nvkms_free_timer(pHeadState->hdr.sdrTransitionTimer); - pHeadState->hdr.sdrTransitionTimer = NULL; -} - -static void SDRTransition(void *dataPtr, NvU32 head) -{ - NVDispHeadStateEvoRec *pHeadState = dataPtr; - - nvAssert(pHeadState->hdr.outputState == - NVKMS_HDR_OUTPUT_STATE_TRANSITIONING_TO_SDR); - pHeadState->hdr.outputState = NVKMS_HDR_OUTPUT_STATE_SDR; - - if (pHeadState->pConnectorEvo) { - NVConnectorEvoPtr pConnectorEvo = pHeadState->pConnectorEvo; - NVDispEvoPtr pDispEvo = pConnectorEvo->pDispEvo; - NvU32 apiHead = nvHardwareHeadToApiHead(head); - NVDispApiHeadStateEvoRec *pApiHeadState = &pDispEvo->apiHeadState[apiHead]; - NVDpyEvoPtr pDpyEvo = - nvGetOneArbitraryDpyEvo(pApiHeadState->activeDpys, pDispEvo); - nvUpdateInfoFrames(pDpyEvo); + if (applyAllowVrr) { + reply->vrrFlipType = nvGetActiveVrrType(pDevEvo); + reply->vrrSemaphoreIndex = vrrSemaphoreIndex; + } else { + reply->vrrFlipType = NV_KMS_VRR_FLIP_NON_VRR; + reply->vrrSemaphoreIndex = -1; } - - CancelSDRTransitionTimer(pHeadState); } -static void ScheduleSDRTransitionTimer(NVDispHeadStateEvoRec *pHeadState, - const NvU32 head) -{ - nvAssert(!pHeadState->hdr.sdrTransitionTimer); - - pHeadState->hdr.sdrTransitionTimer = - nvkms_alloc_timer(SDRTransition, - pHeadState, - head, - 2000000 /* 2 seconds */); -} - -// Adjust from EDID-encoded maxCLL/maxFALL to actual values in units of 1 cd/m2 -static inline NvU32 MaxCvToVal(NvU32 cv) +static void InitNvKmsFlipWorkArea(const NVDevEvoRec *pDevEvo, + struct NvKmsFlipWorkArea *pWorkArea) { - // 50*2^(cv/32) - return f64_to_ui32( - f64_mul(ui32_to_f64(50), - nvKmsPow(ui32_to_f64(2), - f64_div(ui32_to_f64(cv), - ui32_to_f64(32)))), softfloat_round_near_even, FALSE); -} - -// Adjust from EDID-encoded minCLL to actual value in units of 0.0001 cd/m2 -static inline NvU32 MinCvToVal(NvU32 cv, NvU32 maxCLL) -{ - // 10,000 * (minCLL = (maxCLL * ((cv/255)^2 / 100))) - return f64_to_ui32( - f64_mul(ui32_to_f64(10000), - f64_mul(ui32_to_f64(maxCLL), - f64_div(nvKmsPow(f64_div(ui32_to_f64(cv), - ui32_to_f64(255)), - ui32_to_f64(2)), - ui32_to_f64(100)))), - softfloat_round_near_even, FALSE); -} - -static void UpdateHDR(NVDevEvoPtr pDevEvo, - const NVFlipEvoHwState *pFlipState, - const NvU32 sd, - const NvU32 head, - NVEvoUpdateState *updateState) -{ - NVDispEvoPtr pDispEvo = pDevEvo->gpus[sd].pDispEvo; - NVDispHeadStateEvoRec *pHeadState = &pDispEvo->headState[head]; - NvU32 apiHead = nvHardwareHeadToApiHead(head); - NVDispApiHeadStateEvoRec *pApiHeadState = &pDispEvo->apiHeadState[apiHead]; - NVDpyEvoRec *pDpyEvo = - nvGetOneArbitraryDpyEvo(pApiHeadState->activeDpys, pDispEvo); - NvBool dirty = FALSE; - - if (pFlipState->dirty.tf) { - // XXX HDR TODO: Handle other transfer functions - if (pFlipState->tf == NVKMS_OUTPUT_TF_PQ) { - pHeadState->hdr.outputState = NVKMS_HDR_OUTPUT_STATE_HDR; - - CancelSDRTransitionTimer(pHeadState); - } else if (pHeadState->hdr.outputState == NVKMS_HDR_OUTPUT_STATE_HDR) { - pHeadState->hdr.outputState = - NVKMS_HDR_OUTPUT_STATE_TRANSITIONING_TO_SDR; - - ScheduleSDRTransitionTimer(pHeadState, head); - } - pHeadState->tf = pFlipState->tf; - - nvChooseCurrentColorSpaceAndRangeEvo( - pHeadState->timings.pixelDepth, - pHeadState->timings.yuv420Mode, - pHeadState->tf, - pDpyEvo->requestedColorSpace, - pDpyEvo->requestedColorRange, - &pApiHeadState->attributes.colorSpace, - &pApiHeadState->attributes.colorRange); - - /* Update hardware's current colorSpace and colorRange */ - nvUpdateCurrentHardwareColorSpaceAndRangeEvo( - pDispEvo, - head, - pApiHeadState->attributes.colorSpace, - pApiHeadState->attributes.colorRange, - updateState); - - dirty = TRUE; - } - - if (pFlipState->dirty.hdrStaticMetadata) { - NvU32 layer; - NvBool found = FALSE; - for (layer = 0; layer < pDevEvo->head[head].numLayers; layer++) { - // Populate head with updated static metadata. - if (pFlipState->layer[layer].hdrStaticMetadata.enabled) { - const NVT_EDID_INFO *pInfo = &pDpyEvo->parsedEdid.info; - const NVT_HDR_STATIC_METADATA *pHdrInfo = - &pInfo->hdr_static_metadata_info; - - NvU32 targetMaxCLL = MaxCvToVal(pHdrInfo->max_cll); - - // Send this layer's metadata to the display. - pHeadState->hdr.staticMetadata = - pFlipState->layer[layer].hdrStaticMetadata.val; - - /* - * Prepare for tone mapping. If we expect to tone map and the - * EDID has valid lum values, mirror EDID lum values to prevent - * redundant tone mapping by the display. We will tone map to - * the specified maxCLL. - */ - if (nvNeedsTmoLut(pDevEvo, pDevEvo->head[head].layer[layer], - &pFlipState->layer[layer], - nvGetHDRSrcMaxLum( - &pFlipState->layer[layer]), - targetMaxCLL)) { - NvU32 targetMaxFALL = MaxCvToVal(pHdrInfo->max_fall); - if ((targetMaxCLL > 0) && - (targetMaxCLL <= 10000) && - (targetMaxCLL >= targetMaxFALL)) { - - NvU32 targetMinCLL = MinCvToVal(pHdrInfo->min_cll, - targetMaxCLL); - - pHeadState->hdr.staticMetadata. - maxDisplayMasteringLuminance = targetMaxCLL; - pHeadState->hdr.staticMetadata. - minDisplayMasteringLuminance = targetMinCLL; - pHeadState->hdr.staticMetadata.maxCLL = targetMaxCLL; - pHeadState->hdr.staticMetadata.maxFALL = targetMaxFALL; - } - } - - /* - * Only one layer can currently specify static metadata, - * verified by ValidateHDR(). - * - * XXX HDR TODO: Combine metadata from multiple layers. - */ - nvAssert(!found); - found = TRUE; - } - } - if (!found) { - nvkms_memset(&pHeadState->hdr.staticMetadata, 0, - sizeof(struct NvKmsHDRStaticMetadata)); - } - - dirty = TRUE; - } - - if (dirty) { - // Update OCSC / OLUT - nvEvoUpdateCurrentPalette(pDispEvo, head, FALSE); - - nvUpdateInfoFrames(pDpyEvo); - } -} - -/*! - * Program a flip on all requested layers on the specified head. - * - * This also updates pDispEvo->headState[head], caching what was programmed. - - * \param[in,out] pDispEvo The disp on which the flip should be performed. - * \param[in] head The head on which the flip should be performed. - * \param[in] pFlipState The description of how to update each layer. - * \param[in,out] updateState Indicates which channels require UPDATEs - */ -void nvFlipEvoOneHead( - NVDevEvoPtr pDevEvo, - const NvU32 sd, - const NvU32 head, - const NVFlipEvoHwState *pFlipState, - NvBool allowFlipLock, - NVEvoUpdateState *updateState) -{ - NVDispEvoRec *pDispEvo = pDevEvo->gpus[sd].pDispEvo; - const NvU32 apiHead = nvHardwareHeadToApiHead(head); - const NvU32 subDeviceMask = NVBIT(sd); - const NVDispHeadStateEvoRec *pHeadState = - &pDevEvo->gpus[sd].pDispEvo->headState[head]; - NvBool bypassComposition = pHeadState->bypassComposition; - NVEvoSubDevHeadStateRec *pSdHeadState = - &pDevEvo->gpus[sd].headState[head]; - NvU32 layer; + const NVDispEvoRec *pDispEvo; + NvU32 sd, head, apiHead; - /* - * Provide the pre-update hardware state (in pSdHeadState) and the new - * target state (pFlipState) to the HAL implementation so that it has the - * information it needs to implement the workaround for hardware bug - * 2193096, which requires special logic on transitions between NULL and - * non-NULL ctxdmas (and vice versa). - */ - pDevEvo->hal->FlipTransitionWAR(pDevEvo, sd, head, - pSdHeadState, pFlipState, - updateState); + nvkms_memset(pWorkArea, 0, sizeof(*pWorkArea)); /* - * Promote the software state first, such that the hardware programming - * paths below see the new state atomically. + * Initialize the work area. Note we take two snapshots of the + * current headState: newState and oldState. newState will + * describe the new configuration. After that is applied, we will + * refer to oldState to identify any surfaces that are no longer + * in use. */ - if (pFlipState->dirty.viewPortPointIn) { - pSdHeadState->viewPortPointIn = pFlipState->viewPortPointIn; - } - - if (pFlipState->dirty.cursorSurface || pFlipState->dirty.cursorPosition) { - pSdHeadState->cursor = pFlipState->cursor; - } - - for (layer = 0; layer < pDevEvo->head[head].numLayers; layer++) { - if (pFlipState->dirty.layer[layer]) { - pSdHeadState->layer[layer] = pFlipState->layer[layer]; - } - } - - if (pFlipState->dirty.viewPortPointIn) { - nvSetViewPortPointInEvo(pDevEvo->gpus[sd].pDispEvo, - head, - pFlipState->viewPortPointIn.x, - pFlipState->viewPortPointIn.y, - updateState); - } - - if (pFlipState->dirty.cursorSurface) { - nvPushEvoSubDevMask(pDevEvo, NVBIT(sd)); - pDevEvo->hal->SetCursorImage(pDevEvo, - head, - pSdHeadState->cursor.pSurfaceEvo, - updateState, - &pSdHeadState->cursor.cursorCompParams); - nvPopEvoSubDevMask(pDevEvo); - } - - if (pFlipState->dirty.cursorPosition) { - nvEvoMoveCursorInternal(pDevEvo->gpus[sd].pDispEvo, - head, - pFlipState->cursor.x, - pFlipState->cursor.y); - } - - UpdateHDR(pDevEvo, pFlipState, sd, head, updateState); - - for (layer = 0; layer < pDevEvo->head[head].numLayers; layer++) { - if (!pFlipState->dirty.layer[layer]) { - continue; - } - - if (pFlipState->dirty.layerPosition[layer]) { - /* Ensure position updates are supported on this layer. */ - nvAssert(pDevEvo->caps.layerCaps[layer].supportsWindowMode); - - pDevEvo->hal->SetImmPointOut(pDevEvo, - pDevEvo->head[head].layer[layer], - sd, - updateState, - pFlipState->layer[layer].outputPosition.x, - pFlipState->layer[layer].outputPosition.y); - - if (pDevEvo->hal->caps.supportsSynchronizedOverlayPositionUpdate) { - UpdateWinImmInterlockState(pDevEvo, updateState, - pDevEvo->head[head].layer[layer]); - } - } - - nvPushEvoSubDevMask(pDevEvo, subDeviceMask); - - /* Inform DIFR about the upcoming flip. */ - if (pDevEvo->pDifrState) { - nvDIFRNotifyFlip(pDevEvo->pDifrState); - } - - pDevEvo->hal->Flip(pDevEvo, - pDevEvo->head[head].layer[layer], - &pFlipState->layer[layer], - updateState, - bypassComposition); - if (layer == NVKMS_MAIN_LAYER && allowFlipLock) { - UpdateUpdateFlipLockState(pDevEvo, updateState, - pDevEvo->head[head].layer[layer]); - } - nvPopEvoSubDevMask(pDevEvo); - } - - pSdHeadState->targetUsage = pFlipState->usage; - - pSdHeadState->targetDisableMidFrameAndDWCFWatermark = - pFlipState->disableMidFrameAndDWCFWatermark; - - pDispEvo->apiHeadState[apiHead].viewPortPointIn = - pSdHeadState->viewPortPointIn; -} - -static void ChangeSurfaceFlipRefCount( - NVDevEvoPtr pDevEvo, - NVSurfaceEvoPtr pSurfaceEvo, - NvBool increase) -{ - if (pSurfaceEvo != NULL) { - if (increase) { - nvEvoIncrementSurfaceRefCnts(pSurfaceEvo); - } else { - nvEvoDecrementSurfaceRefCnts(pDevEvo, pSurfaceEvo); - } - } -} - -void nvUpdateSurfacesFlipRefCount( - NVDevEvoPtr pDevEvo, - const NvU32 head, - NVFlipEvoHwState *pFlipState, - NvBool increase) -{ - NvU32 i; - - ChangeSurfaceFlipRefCount( - pDevEvo, - pFlipState->cursor.pSurfaceEvo, - increase); - - for (i = 0; i < pDevEvo->head[head].numLayers; i++) { - NVFlipChannelEvoHwState *pLayerFlipState = &pFlipState->layer[i]; - - ChangeSurfaceFlipRefCount( - pDevEvo, - pLayerFlipState->pSurfaceEvo[NVKMS_LEFT], - increase); - ChangeSurfaceFlipRefCount( - pDevEvo, - pLayerFlipState->pSurfaceEvo[NVKMS_RIGHT], - increase); - ChangeSurfaceFlipRefCount( - pDevEvo, - pLayerFlipState->completionNotifier.surface.pSurfaceEvo, - increase); - - if (!pLayerFlipState->syncObject.usingSyncpt) { - ChangeSurfaceFlipRefCount( - pDevEvo, - pLayerFlipState->syncObject.u.semaphores.acquireSurface.pSurfaceEvo, - increase); - ChangeSurfaceFlipRefCount( - pDevEvo, - pLayerFlipState->syncObject.u.semaphores.releaseSurface.pSurfaceEvo, - increase); - } - } -} - -static void UnionScalingUsageBounds( - const struct NvKmsScalingUsageBounds *a, - const struct NvKmsScalingUsageBounds *b, - struct NvKmsScalingUsageBounds *ret) -{ - ret->maxVDownscaleFactor = NV_MAX(a->maxVDownscaleFactor, - b->maxVDownscaleFactor); - ret->maxHDownscaleFactor = NV_MAX(a->maxHDownscaleFactor, - b->maxHDownscaleFactor); - ret->vTaps = NV_MAX(a->vTaps, b->vTaps); - ret->vUpscalingAllowed = a->vUpscalingAllowed || b->vUpscalingAllowed; -} - -void nvUnionUsageBounds(const struct NvKmsUsageBounds *a, - const struct NvKmsUsageBounds *b, - struct NvKmsUsageBounds *ret) -{ - NvU32 i; - - nvkms_memset(ret, 0, sizeof(*ret)); - - for (i = 0; i < ARRAY_LEN(a->layer); i++) { - nvAssert(a->layer[i].usable == - !!a->layer[i].supportedSurfaceMemoryFormats); - nvAssert(b->layer[i].usable == - !!b->layer[i].supportedSurfaceMemoryFormats); - - ret->layer[i].usable = a->layer[i].usable || b->layer[i].usable; - - ret->layer[i].supportedSurfaceMemoryFormats = - a->layer[i].supportedSurfaceMemoryFormats | - b->layer[i].supportedSurfaceMemoryFormats; - - UnionScalingUsageBounds(&a->layer[i].scaling, - &b->layer[i].scaling, - &ret->layer[i].scaling); - } -} - -NvBool UsageBoundsEqual( - const struct NvKmsUsageBounds *a, - const struct NvKmsUsageBounds *b) -{ - NvU32 layer; - - for (layer = 0; layer < ARRAY_LEN(a->layer); layer++) { - if (!nvEvoLayerUsageBoundsEqual(a, b, layer)) { - return FALSE; - } - } - - return TRUE; -} - -static NvBool AllocatePreFlipBandwidth(NVDevEvoPtr pDevEvo, - struct NvKmsFlipWorkArea *pWorkArea) -{ - NVValidateImpOneDispHeadParamsRec *timingsParams = NULL; - struct NvKmsUsageBounds *currentAndNew = NULL; - struct NvKmsUsageBounds *guaranteedAndCurrent = NULL; - NVDispEvoPtr pDispEvo; - NvU32 head; - NvBool recheckIMP = FALSE; - NvBool ret = TRUE; - - if (!pDevEvo->isSOCDisplay) { - return TRUE; - } - - timingsParams = - nvCalloc(NVKMS_MAX_HEADS_PER_DISP, sizeof(*timingsParams)); - if (timingsParams == NULL) { - return FALSE; - } - - currentAndNew = - nvCalloc(NVKMS_MAX_HEADS_PER_DISP, sizeof(*currentAndNew)); - if (currentAndNew == NULL) { - nvFree(timingsParams); - return FALSE; - } - - guaranteedAndCurrent = - nvCalloc(NVKMS_MAX_HEADS_PER_DISP, sizeof(*guaranteedAndCurrent)); - if (guaranteedAndCurrent == NULL) { - nvFree(timingsParams); - nvFree(currentAndNew); - return FALSE; - } - - pDispEvo = pDevEvo->pDispEvo[0]; - - // SOC Display never has more than one disp - nvAssert(pDevEvo->nDispEvo == 1); - - for (head = 0; head < pDevEvo->numHeads; head++) { - NVDispHeadStateEvoRec *pHeadState = - &pDispEvo->headState[head]; - const struct NvKmsUsageBounds *pCurrent = - &pDevEvo->gpus[0].headState[head].preallocatedUsage; - const struct NvKmsUsageBounds *pNew = - &pWorkArea->sd[0].head[head].newState.usage; - - if (pHeadState->activeRmId == 0) { - continue; - } - - timingsParams[head].pConnectorEvo = pHeadState->pConnectorEvo; - timingsParams[head].activeRmId = pHeadState->activeRmId; - timingsParams[head].pTimings = &pHeadState->timings; - - nvUnionUsageBounds(pCurrent, pNew, ¤tAndNew[head]); - nvUnionUsageBounds(&pHeadState->timings.viewPort.guaranteedUsage, - pCurrent, &guaranteedAndCurrent[head]); - - if (!ValidateUsageBounds(pDevEvo, - head, - pNew, - &guaranteedAndCurrent[head])) { - recheckIMP = TRUE; - } - - nvUnionUsageBounds(&guaranteedAndCurrent[head], pNew, - &guaranteedAndCurrent[head]); - timingsParams[head].pUsage = &guaranteedAndCurrent[head]; - } - - if (recheckIMP) { - ret = nvValidateImpOneDisp(pDispEvo, timingsParams, - FALSE /* requireBootClocks */, - NV_EVO_REALLOCATE_BANDWIDTH_MODE_PRE, - NULL /* pMinIsoBandwidthKBPS */, - NULL /* pMinDramFloorKBPS */); - if (ret) { - for (head = 0; head < pDevEvo->numHeads; head++) { - pDevEvo->gpus[0].headState[head].preallocatedUsage = - currentAndNew[head]; - } - } - } - - nvFree(timingsParams); - nvFree(currentAndNew); - nvFree(guaranteedAndCurrent); - - if (ret) { - nvScheduleLowerDispBandwidthTimer(pDevEvo); - } - - return ret; -} - -/*! - * If the satellite channel is active then pre-NVDisplay hardware does not allow - * to change its usage bounds in non-interlock update. The nvSetUsageBoundsEvo() - * code path for pre-NVDisplay hardware, interlocks the satellite channels with - * the usage bounds update. This makes it essential to poll for - * NO_METHOD_PENDING state of the satellite channels, otherwise blocking - * pre-flip IMP update will also get stuck. - * - * It is not possible to interlock flip-locked satellite channels with the core - * channel usage bounds update; in that case, reject the flip. Do not allow - * client to make any change in surface usage bounds parameters without - * deactivating channel first, if channel is flip-locked. - */ -static NvBool PrepareToDoPreFlipIMP(NVDevEvoPtr pDevEvo, - struct NvKmsFlipWorkArea *pWorkArea) -{ - NvU64 startTime = 0; - NvU32 timeout = 2000000; /* 2 seconds */ - NvU32 sd; - - for (sd = 0; sd < pDevEvo->numSubDevices; sd++) { - NVEvoSubDevPtr pEvoSubDev = &pDevEvo->gpus[sd]; - NvU32 head; - - for (head = 0; head < pDevEvo->numHeads; head++) { - NVEvoHeadControlPtr pHC = - &pEvoSubDev->headControl[head]; - const NVEvoSubDevHeadStateRec *pCurrentFlipState = - &pDevEvo->gpus[sd].headState[head]; - const NVSurfaceEvoRec *pCurrentBaseSurf = - pCurrentFlipState->layer[NVKMS_MAIN_LAYER].pSurfaceEvo[NVKMS_LEFT]; - const struct NvKmsUsageBounds *pCurrentUsage = - &pCurrentFlipState->usage; - - NVFlipEvoHwState *pNewFlipState = - &pWorkArea->sd[sd].head[head].newState; - const NVSurfaceEvoRec *pNewBaseSurf = - pNewFlipState->layer[NVKMS_MAIN_LAYER].pSurfaceEvo[NVKMS_LEFT]; - struct NvKmsUsageBounds *pNewUsage = - &pNewFlipState->usage; - - struct NvKmsUsageBounds *pPreFlipUsage = - &pWorkArea->sd[sd].head[head].preFlipUsage; - - NvU32 layer; - - nvUnionUsageBounds(pNewUsage, pCurrentUsage, pPreFlipUsage); - - if (pDevEvo->hal->caps.supportsNonInterlockedUsageBoundsUpdate) { - /* - * NVDisplay does not interlock the satellite channel - * with its usage bounds update. - */ - continue; - } - - /* - * If head is flip-locked then do not change usage - * bounds while base channel is active. - */ - if (pHC->flipLock && - /* If the base channel is active before and after flip then - * current and new base usage bounds should be same. */ - ((pNewBaseSurf != NULL && - pCurrentBaseSurf != NULL && - !nvEvoLayerUsageBoundsEqual(pCurrentUsage, - pNewUsage, NVKMS_MAIN_LAYER)) || - /* If the base channel is active before flip then current and - * preflip base usage bounds should be same. */ - (pCurrentBaseSurf != NULL && - !nvEvoLayerUsageBoundsEqual(pCurrentUsage, - pPreFlipUsage, NVKMS_MAIN_LAYER)))) { - return FALSE; - } - - /* - * Poll for NO_METHOD_PENDING state if usage - * bounds of the channel are changed. - */ - for (layer = 0; layer < pDevEvo->head[head].numLayers; layer++) { - if (!nvEvoLayerUsageBoundsEqual(pCurrentUsage, - pPreFlipUsage, layer) && - !nvEvoPollForNoMethodPending(pDevEvo, - sd, - pDevEvo->head[head].layer[layer], - &startTime, - timeout)) { - return FALSE; - } - } - } - } - - return TRUE; -} - -/*! - * Tasks need to perform before triggering flip, they all should be done here. - * - * If necessary, raise usage bounds and/or disable MidFrameAndDWCFWatermark - * (bug 200508242) in the core channel and do an IMP update. - * - * Note that this function only raises usage bounds and/or disables - * MidFrameAndDWCFWatermark, never lowers usage bounds and/or enables - * MidFrameAndDWCFWatermark. This allows it to run before queuing a flip even - * if there are still pending flips in a base channel. - */ -static void PreFlipIMP(NVDevEvoPtr pDevEvo, - const struct NvKmsFlipWorkArea *pWorkArea) -{ - NvU32 head, sd; - NVDispEvoPtr pDispEvo; - FOR_ALL_EVO_DISPLAYS(pDispEvo, sd, pDevEvo) { - NVEvoUpdateState updateState = { }; - NvBool update = FALSE; - - for (head = 0; head < pDispEvo->pDevEvo->numHeads; head++) { - const NVFlipEvoHwState *pNewState = - &pWorkArea->sd[sd].head[head].newState; - const struct NvKmsUsageBounds *pPreFlipUsage = - &pWorkArea->sd[sd].head[head].preFlipUsage; - struct NvKmsUsageBounds *pCurrentUsage = - &pDevEvo->gpus[sd].headState[head].usage; - - if (!UsageBoundsEqual(pCurrentUsage, pPreFlipUsage)) { - update |= nvSetUsageBoundsEvo(pDevEvo, sd, head, - pPreFlipUsage, &updateState); - } - - if (!pDevEvo->gpus[sd]. - headState[head].disableMidFrameAndDWCFWatermark && - pNewState->disableMidFrameAndDWCFWatermark) { - - nvEnableMidFrameAndDWCFWatermark(pDevEvo, - sd, - head, - FALSE /* enable */, - &updateState); - update = TRUE; - } + for (head = 0; head < ARRAY_LEN(pWorkArea->sd[sd].head); head++) { + nvInitFlipEvoHwState(pDevEvo, sd, head, + &pWorkArea->sd[sd].head[head].newState); + nvInitFlipEvoHwState(pDevEvo, sd, head, + &pWorkArea->sd[sd].head[head].oldState); } - if (update) { - nvDoIMPUpdateEvo(pDispEvo, &updateState); + for (apiHead = 0; apiHead < pDevEvo->numApiHeads; apiHead++) { + NVProposedFlipStateOneApiHead *pProposedApiHead = + &pWorkArea->disp[sd].apiHead[apiHead].proposedFlipState; + const NVDispApiHeadStateEvoRec *pApiHeadState = + &pDispEvo->apiHeadState[apiHead]; + + pProposedApiHead->hdr.tf = pApiHeadState->tf; + pProposedApiHead->hdr.colorSpace = + pApiHeadState->attributes.colorSpace; + pProposedApiHead->hdr.colorBpc = + pApiHeadState->attributes.colorBpc; + pProposedApiHead->hdr.colorRange = + pApiHeadState->attributes.colorRange; + + pProposedApiHead->viewPortPointIn = + pApiHeadState->viewPortPointIn; } } } -static void LowerDispBandwidth(void *dataPtr, NvU32 dataU32) +static void FlipEvoOneApiHead(NVDispEvoRec *pDispEvo, + const NvU32 apiHead, + const struct NvKmsFlipWorkArea *pWorkArea, + const NvBool allowFlipLock, + NVEvoUpdateState *pUpdateState) { - NVValidateImpOneDispHeadParamsRec timingsParams[NVKMS_MAX_HEADS_PER_DISP]; - struct NvKmsUsageBounds *guaranteedAndCurrent; - NVDevEvoPtr pDevEvo = dataPtr; - NVDispEvoPtr pDispEvo; + NVDevEvoRec *pDevEvo = pDispEvo->pDevEvo; + const NvU32 sd = pDispEvo->displayOwner; NvU32 head; - NvBool ret; - - guaranteedAndCurrent = - nvCalloc(1, sizeof(*guaranteedAndCurrent) * NVKMS_MAX_HEADS_PER_DISP); - if (guaranteedAndCurrent == NULL) { - nvAssert(guaranteedAndCurrent != NULL); - return; - } - - nvkms_memset(&timingsParams, 0, sizeof(timingsParams)); - - pDispEvo = pDevEvo->pDispEvo[0]; - - // SOC Display never has more than one disp - nvAssert(pDevEvo->nDispEvo == 1); - - for (head = 0; head < pDevEvo->numHeads; head++) { - NVDispHeadStateEvoRec *pHeadState = - &pDispEvo->headState[head]; - const struct NvKmsUsageBounds *pGuaranteed = - &pHeadState->timings.viewPort.guaranteedUsage; - const struct NvKmsUsageBounds *pCurrent = - &pDevEvo->gpus[0].headState[head].usage; - - if (pHeadState->activeRmId == 0) { - continue; - } - - timingsParams[head].pConnectorEvo = pHeadState->pConnectorEvo; - timingsParams[head].activeRmId = pHeadState->activeRmId; - timingsParams[head].pTimings = &pHeadState->timings; - - nvUnionUsageBounds(pGuaranteed, pCurrent, &guaranteedAndCurrent[head]); - timingsParams[head].pUsage = &guaranteedAndCurrent[head]; - } - - ret = nvValidateImpOneDisp(pDispEvo, timingsParams, - FALSE /* requireBootClocks */, - NV_EVO_REALLOCATE_BANDWIDTH_MODE_POST, - NULL /* pMinIsoBandwidthKBPS */, - NULL /* pMinDramFloorKBPS */); - if (ret) { - for (head = 0; head < pDevEvo->numHeads; head++) { - pDevEvo->gpus[0].headState[head].preallocatedUsage = - pDevEvo->gpus[0].headState[head].usage; - } - } - - nvAssert(ret); - - nvFree(guaranteedAndCurrent); -} - -void nvCancelLowerDispBandwidthTimer(NVDevEvoPtr pDevEvo) -{ - nvkms_free_timer(pDevEvo->lowerDispBandwidthTimer); - pDevEvo->lowerDispBandwidthTimer = NULL; -} - -void nvScheduleLowerDispBandwidthTimer(NVDevEvoPtr pDevEvo) -{ - nvAssert(pDevEvo->isSOCDisplay); - - nvCancelLowerDispBandwidthTimer(pDevEvo); - - pDevEvo->lowerDispBandwidthTimer = - nvkms_alloc_timer(LowerDispBandwidth, - pDevEvo, - 0, /* dataU32 */ - 30000000 /* 30 seconds */); -} - -/*! - * Check whether the core, base, and overlay channels are idle (i.e. no methods - * pending in the corresponding pushbuffer) and lower the usage bounds if - * possible. - */ -static NvBool TryLoweringUsageBoundsOneHead(NVDevEvoPtr pDevEvo, NvU32 sd, - NvU32 head, - NVEvoUpdateState *updateState) -{ - const NVEvoSubDevHeadStateRec *pHeadState = - &pDevEvo->gpus[sd].headState[head]; - const struct NvKmsUsageBounds *pCurrent = &pHeadState->usage; - const struct NvKmsUsageBounds *pTarget = &pHeadState->targetUsage; - struct NvKmsUsageBounds newUsage = *pCurrent; - NvBool changed = FALSE; - NvBool scheduleLater = FALSE; - int i; - - for (i = 0; i < pDevEvo->head[head].numLayers; i++) { - if (pCurrent->layer[i].usable && !pTarget->layer[i].usable) { - NvBool isMethodPending; - - if (pDevEvo->hal->IsChannelMethodPending( - pDevEvo, - pDevEvo->head[head].layer[i], - sd, - &isMethodPending) && !isMethodPending) { - newUsage.layer[i] = pTarget->layer[i]; - changed = TRUE; - } else { - scheduleLater = TRUE; - } - } else if ((pCurrent->layer[i].usable && pTarget->layer[i].usable) && - ((pCurrent->layer[i].supportedSurfaceMemoryFormats != - pTarget->layer[i].supportedSurfaceMemoryFormats) || - (!nvEvoScalingUsageBoundsEqual(&pCurrent->layer[i].scaling, - &pTarget->layer[i].scaling)))) { - NvBool isMethodPending; - - if (pDevEvo->hal->IsChannelMethodPending( - pDevEvo, - pDevEvo->head[head].layer[i], - sd, - &isMethodPending) && !isMethodPending) { - newUsage.layer[i] = pTarget->layer[i]; - changed = TRUE; - } else { - scheduleLater = TRUE; - } - } - } - - if (scheduleLater) { - SchedulePostFlipIMPTimer(pDevEvo); - } - - if (changed) { - changed = nvSetUsageBoundsEvo(pDevEvo, sd, head, &newUsage, - updateState); - } - - return changed; -} - -static NvBool -TryEnablingMidFrameAndDWCFWatermarkOneHead(NVDevEvoPtr pDevEvo, - NvU32 sd, - NvU32 head, - NVEvoUpdateState *updateState) -{ - const NVEvoSubDevHeadStateRec *pHeadState = - &pDevEvo->gpus[sd].headState[head]; - NvBool changed = FALSE; - - if (pHeadState->disableMidFrameAndDWCFWatermark && - !pHeadState->targetDisableMidFrameAndDWCFWatermark) { - - NvBool isIdle; - - if (pDevEvo->hal->IsChannelIdle(pDevEvo, - pDevEvo->head[head].layer[NVKMS_MAIN_LAYER], - sd, - &isIdle) && isIdle) { - nvEnableMidFrameAndDWCFWatermark(pDevEvo, - sd, - head, - TRUE /* enable */, - updateState); - changed = TRUE; - } else { - // Schedule another timer to try again later. - SchedulePostFlipIMPTimer(pDevEvo); - } - } - - return changed; -} - -static void -TryToDoPostFlipIMP(void *dataPtr, NvU32 dataU32) -{ - NVDevEvoPtr pDevEvo = dataPtr; - NvU32 head, sd; - NVDispEvoPtr pDispEvo; - - pDevEvo->postFlipIMPTimer = NULL; - - FOR_ALL_EVO_DISPLAYS(pDispEvo, sd, pDevEvo) { - NVEvoUpdateState updateState = { }; - NvBool update = FALSE; - - for (head = 0; head < pDispEvo->pDevEvo->numHeads; head++) { - if (TryLoweringUsageBoundsOneHead(pDevEvo, sd, head, - &updateState)) { - update = TRUE; - } + const NVProposedFlipStateOneApiHead *pProposedApiHead = + &pWorkArea->disp[sd].apiHead[apiHead].proposedFlipState; + NVDispApiHeadStateEvoRec *pApiHeadState = + &pDispEvo->apiHeadState[apiHead]; + NVDpyEvoRec *pDpyEvo = + nvGetOneArbitraryDpyEvo(pApiHeadState->activeDpys, pDispEvo); + const NVT_EDID_INFO *pInfo = &pDpyEvo->parsedEdid.info; + const NVT_HDR_STATIC_METADATA *pHdrInfo = + &pInfo->hdr_static_metadata_info; - if (TryEnablingMidFrameAndDWCFWatermarkOneHead( - pDevEvo, - sd, - head, - &updateState)) { - update = TRUE; - } - } + nvAssert(nvApiHeadIsActive(pDispEvo, apiHead)); - if (update) { - nvDoIMPUpdateEvo(pDispEvo, &updateState); + FOR_EACH_EVO_HW_HEAD_IN_MASK(pApiHeadState->hwHeadsMask, head) { + nvFlipEvoOneHead(pDevEvo, sd, head, pHdrInfo, + &pWorkArea->sd[sd].head[head].newState, + allowFlipLock, + pUpdateState); + + if (pProposedApiHead->dirty.hdr) { + /* Update hardware's current colorSpace and colorRange */ + nvUpdateCurrentHardwareColorSpaceAndRangeEvo( + pDispEvo, + head, + pProposedApiHead->hdr.colorSpace, + pProposedApiHead->hdr.colorRange, + pUpdateState); } } -} - -static void SchedulePostFlipIMPTimer(NVDevEvoPtr pDevEvo) -{ - if (!pDevEvo->postFlipIMPTimer) { - pDevEvo->postFlipIMPTimer = - nvkms_alloc_timer( - TryToDoPostFlipIMP, - pDevEvo, - 0, /* dataU32 */ - 10000000 /* 10 seconds */); - } -} - -void nvEvoCancelPostFlipIMPTimer(NVDevEvoPtr pDevEvo) -{ - nvkms_free_timer(pDevEvo->postFlipIMPTimer); - pDevEvo->postFlipIMPTimer = NULL; -} - -/*! - * If necessary, schedule a timer to see if usage bounds can be lowered. - */ -static void SchedulePostFlipIMP(NVDevEvoPtr pDevEvo) -{ - NvU32 head, sd; - NVDispEvoPtr pDispEvo; - - // If a timer is already scheduled, do nothing. - if (pDevEvo->postFlipIMPTimer) { - return; - } - FOR_ALL_EVO_DISPLAYS(pDispEvo, sd, pDevEvo) { - for (head = 0; head < pDispEvo->pDevEvo->numHeads; head++) { - const NVEvoSubDevHeadStateRec *pHeadState = - &pDevEvo->gpus[sd].headState[head]; - - if (!UsageBoundsEqual(&pHeadState->usage, - &pHeadState->targetUsage) || - (pHeadState->disableMidFrameAndDWCFWatermark != - pHeadState->targetDisableMidFrameAndDWCFWatermark)) { + if (pProposedApiHead->dirty.hdr) { + pApiHeadState->attributes.colorSpace = + pProposedApiHead->hdr.colorSpace; + pApiHeadState->attributes.colorBpc = + pProposedApiHead->hdr.colorBpc; + pApiHeadState->attributes.colorRange = + pProposedApiHead->hdr.colorRange; - SchedulePostFlipIMPTimer(pDevEvo); - return; - } + if (pProposedApiHead->hdr.tf == NVKMS_OUTPUT_TF_PQ) { + nvCancelSDRTransitionTimer(pApiHeadState); + } else if (pApiHeadState->tf == NVKMS_OUTPUT_TF_PQ) { + ScheduleSDRTransitionTimer(pDispEvo, apiHead); } - } -} - -static NvBool GetAllowVrr(const NVDevEvoRec *pDevEvo, - const struct NvKmsFlipRequest *request, - NvBool *pApplyAllowVrr) -{ - NvU32 sd; - const NVDispEvoRec *pDispEvo; - NvU32 requestedHeadCount, activeHeadCount, dirtyMainLayerCount; - NvBool allowVrr = request->allowVrr; - - *pApplyAllowVrr = FALSE; - - /*! - * Count active and requested heads so we can make a decision about VRR - * and register syncpts if specified. - */ - requestedHeadCount = activeHeadCount = dirtyMainLayerCount = 0; - - FOR_ALL_EVO_DISPLAYS(pDispEvo, sd, pDevEvo) { - NvU32 head; - const struct NvKmsFlipRequestOneSubDevice *pRequestOneSubDevice = - &request->sd[sd]; - - for (head = 0; head < ARRAY_LEN(pRequestOneSubDevice->head); head++) { - if (nvHeadIsActive(pDispEvo, head)) { - activeHeadCount++; - } - - if ((NVBIT(head) & - pRequestOneSubDevice->requestedHeadsBitMask) != 0x0) { - requestedHeadCount++; - if (IsLayerDirty(&pRequestOneSubDevice->head[head], - NVKMS_MAIN_LAYER)) { - dirtyMainLayerCount++; - } - } - } - } + pApiHeadState->tf = pProposedApiHead->hdr.tf; - /* - * Deactivate VRR if only a subset of the heads are requested or - * only a subset of the heads are being flipped. - */ - if ((activeHeadCount != requestedHeadCount) || - (activeHeadCount != dirtyMainLayerCount)) { - allowVrr = FALSE; + nvUpdateInfoFrames(pDpyEvo); } - /* - * Apply NvKmsFlipRequest::allowVrr - * only if at least one main layer is became dirty. - */ - if (dirtyMainLayerCount > 0) { - *pApplyAllowVrr = TRUE; + if (pProposedApiHead->dirty.viewPortPointIn) { + pApiHeadState->viewPortPointIn = + pProposedApiHead->viewPortPointIn; } - - return allowVrr; } -static void SkipLayerPendingFlips(NVDevEvoRec *pDevEvo, - const NvBool trashPendingMethods, - const NvBool unblockMethodsInExecutation, - struct NvKmsFlipWorkArea *pWorkArea) +static NvU32 FlipEvo2Head1OrOneDisp(NVDispEvoRec *pDispEvo, + struct NvKmsFlipWorkArea *pWorkArea, + const NvBool skipUpdate) { - NvU64 startTime = 0; - const NvU32 timeout = 2000000; /* 2 seconds */ - struct { - struct { - struct { - NvU32 oldAccelMask; - } head[NVKMS_MAX_HEADS_PER_DISP]; - } sd[NVKMS_MAX_SUBDEVICES]; - } accelState = { }; - NvU32 sd, head; - - for (sd = 0; sd < pDevEvo->numSubDevices; sd++) { - if (!pWorkArea->sd[sd].changed) { - continue; - } - - for (head = 0; head < NVKMS_MAX_HEADS_PER_DISP; head++) { - const NVFlipEvoHwState *pFlipState = - &pWorkArea->sd[sd].head[head].newState; - - if (!pFlipState->skipLayerPendingFlips[NVKMS_MAIN_LAYER]|| - !pFlipState->dirty.layer[NVKMS_MAIN_LAYER]) { - continue; - } + NVDevEvoRec *pDevEvo = pDispEvo->pDevEvo; + NvU32 flip2Heads1OrApiHeadsMask = 0x0; - pDevEvo->hal->AccelerateChannel( - pDevEvo, - pDevEvo->head[head].layer[NVKMS_MAIN_LAYER], - sd, - trashPendingMethods, - unblockMethodsInExecutation, - &accelState.sd[sd].head[head].oldAccelMask); - } - } + for (NvU32 apiHead = 0; apiHead < NVKMS_MAX_HEADS_PER_DISP; apiHead++) { + NVDispApiHeadStateEvoRec *pApiHeadState = + &pDispEvo->apiHeadState[apiHead]; + const NvBool b2Heads1Or = + (nvPopCount32(pApiHeadState->hwHeadsMask) >= 2); - for (sd = 0; sd < pDevEvo->numSubDevices; sd++) { - if (!pWorkArea->sd[sd].changed) { + if (!nvApiHeadIsActive(pDispEvo, apiHead) || !b2Heads1Or) { continue; } - for (head = 0; head < NVKMS_MAX_HEADS_PER_DISP; head++) { - const NVFlipEvoHwState *pFlipState = - &pWorkArea->sd[sd].head[head].newState; + nvkms_memset(&pWorkArea->updateState, 0, + sizeof(pWorkArea->updateState)); - if (!pFlipState->skipLayerPendingFlips[NVKMS_MAIN_LAYER] || - !pFlipState->dirty.layer[NVKMS_MAIN_LAYER]) { - continue; - } + FlipEvoOneApiHead(pDispEvo, apiHead, pWorkArea, + TRUE /* allowFlipLock */, &pWorkArea->updateState); - if (unblockMethodsInExecutation) { - if (!nvEvoPollForNoMethodPending(pDevEvo, - sd, - pDevEvo->head[head].layer[NVKMS_MAIN_LAYER], - &startTime, - timeout)) { - nvAssert(!"Failed to idle the main layer channel"); - } - } else { - if (!nvEvoPollForEmptyChannel(pDevEvo->head[head].layer[NVKMS_MAIN_LAYER], - sd, - &startTime, - timeout)) { - nvAssert(!"Failed to empty the main layer channel"); - } - } + /* + * If api-head is using 2Heads1OR mode then it can not be flip with + * other ap-heads in a single update; because each api-head, which is + * using 2Heads1OR mode, uses different fliplock group and kicking off + * multiple fliplock groups as part of a single update call is not + * supported yet. + */ + pDevEvo->hal->Update(pDevEvo, &pWorkArea->updateState, + TRUE /* releaseElv */); + nvAssert(!skipUpdate); - pDevEvo->hal->ResetChannelAccelerators( - pDevEvo, - pDevEvo->head[head].layer[NVKMS_MAIN_LAYER], - sd, - trashPendingMethods, - unblockMethodsInExecutation, - accelState.sd[sd].head[head].oldAccelMask); - } + flip2Heads1OrApiHeadsMask |= NVBIT(apiHead); } + + return flip2Heads1OrApiHeadsMask; } /*! @@ -3137,25 +476,27 @@ */ NvBool nvFlipEvo(NVDevEvoPtr pDevEvo, const struct NvKmsPerOpenDev *pOpenDev, - const struct NvKmsFlipRequest *request, + const struct NvKmsFlipRequestOneHead *pFlipHead, + NvU32 numFlipHeads, + NvBool commit, + NvBool requestAllowVrr, struct NvKmsFlipReply *reply, NvBool skipUpdate, NvBool allowFlipLock) { - enum NvKmsVrrFlipType vrrFlipType = NV_KMS_VRR_FLIP_NON_VRR; NvS32 vrrSemaphoreIndex = -1; - NvU32 head, sd; + NvU32 apiHead, sd; NvBool applyAllowVrr = FALSE; NvBool ret = FALSE; NvBool changed = FALSE; NVDispEvoPtr pDispEvo; const NvBool allowVrr = - GetAllowVrr(pDevEvo, request, &applyAllowVrr); + GetAllowVrr(pDevEvo, pFlipHead, numFlipHeads, + requestAllowVrr, &applyAllowVrr); struct NvKmsFlipWorkArea *pWorkArea = nvPreallocGet(pDevEvo, PREALLOC_TYPE_FLIP_WORK_AREA, sizeof(*pWorkArea)); - - nvkms_memset(pWorkArea, 0, sizeof(*pWorkArea)); + NvU32 i; /* * Do not execute NVKMS_IOCTL_FLIP if the display channel yet has not @@ -3169,78 +510,48 @@ goto done; } - /* - * Initialize the work area. Note we take two snapshots of the - * current headState: newState and oldState. newState will - * describe the new configuration. After that is applied, we will - * refer to oldState to identify any surfaces that are no longer - * in use. - */ - - for (sd = 0; sd < pDevEvo->numSubDevices; sd++) { - for (head = 0; head < ARRAY_LEN(pWorkArea->sd[sd].head); head++) { - nvInitFlipEvoHwState(pDevEvo, sd, head, - &pWorkArea->sd[sd].head[head].newState); - nvInitFlipEvoHwState(pDevEvo, sd, head, - &pWorkArea->sd[sd].head[head].oldState); - } - } + InitNvKmsFlipWorkArea(pDevEvo, pWorkArea); /* Validate the flip parameters and update the work area. */ - FOR_ALL_EVO_DISPLAYS(pDispEvo, sd, pDevEvo) { - - const struct NvKmsFlipRequestOneSubDevice *pRequestOneSubDevice = - &request->sd[sd]; - - for (head = 0; head < ARRAY_LEN(pRequestOneSubDevice->head); head++) { - const NVDispHeadStateEvoRec *pHeadState; - const struct NvKmsUsageBounds *pPossibleUsage; - const NvBool headActive = nvHeadIsActive(pDispEvo, head); - - if (!(NVBIT(head) & pRequestOneSubDevice->requestedHeadsBitMask)) { - continue; - } - - if (!headActive) { - goto done; - } - - pHeadState = &pDispEvo->headState[head]; - pPossibleUsage = &pHeadState->timings.viewPort.possibleUsage; - - if (!nvUpdateFlipEvoHwState( - pOpenDev, - pDevEvo, - sd, - head, - &pRequestOneSubDevice->head[head], - &pWorkArea->sd[sd].head[head].newState, - allowVrr)) { - goto done; - } + for (i = 0; i < numFlipHeads; i++) { + const NvU32 apiHead = pFlipHead[i].head; + const NvU32 sd = pFlipHead[i].sd; + NVDispEvoPtr pDispEvo = pDevEvo->pDispEvo[sd]; + NvU32 head; + const NVDispApiHeadStateEvoRec *pApiHeadState = + &pDispEvo->apiHeadState[apiHead]; - nvOverrideScalingUsageBounds(pDevEvo, - head, - &pWorkArea->sd[sd].head[head].newState, - pPossibleUsage); - - if (!nvValidateFlipEvoHwState( - pDevEvo, - head, - &pHeadState->timings, - &pWorkArea->sd[sd].head[head].newState)) { - goto done; - } + if (!nvApiHeadIsActive(pDispEvo, apiHead)) { + goto done; + } - if (!nvSetTmoLutSurfacesEvo(pDevEvo, - &pWorkArea->sd[sd].head[head].newState, - head)) { + if (!nvCheckFlipPermissions(pOpenDev, pDevEvo, sd, apiHead, + &pFlipHead[i].flip)) { + goto done; + } + + if (!UpdateProposedFlipStateOneApiHead( + pDispEvo, + apiHead, + &pFlipHead[i].flip, + &pWorkArea->disp[sd].apiHead[apiHead].proposedFlipState)) { + goto done; + } + + FOR_EACH_EVO_HW_HEAD_IN_MASK(pApiHeadState->hwHeadsMask, head) { + if (!nvAssignNVFlipEvoHwState(pDevEvo, + pOpenDev, + sd, + head, + &pFlipHead[i].flip, + allowVrr, + &pWorkArea->sd[sd].head[head].newState)) { goto done; } - - pWorkArea->sd[sd].changed = TRUE; - changed = TRUE; } + + pWorkArea->sd[sd].changed = TRUE; + changed = TRUE; } /* If nothing changed, fail. */ @@ -3249,21 +560,17 @@ goto done; } - ret = AllocatePreFlipBandwidth(pDevEvo, pWorkArea); + ret = nvAllocatePreFlipBandwidth(pDevEvo, pWorkArea); if (!ret) { goto done; } - if (!request->commit) { + if (!commit) { ret = NV_TRUE; goto done; } - if (!RegisterPreSyncpt(pDevEvo, pWorkArea)) { - goto done; - } - - if (!PrepareToDoPreFlipIMP(pDevEvo, pWorkArea)) { + if (!nvPrepareToDoPreFlip(pDevEvo, pWorkArea)) { goto done; } @@ -3276,42 +583,10 @@ ret = TRUE; - for (sd = 0; sd < pDevEvo->numSubDevices; sd++) { - - if (!pWorkArea->sd[sd].changed) { - continue; - } - - for (head = 0; head < NVKMS_MAX_HEADS_PER_DISP; head++) { - // Increase refCnt of surfaces used AFTER flip - nvUpdateSurfacesFlipRefCount( - pDevEvo, - head, - &pWorkArea->sd[sd].head[head].newState, - NV_TRUE); - - nvRefTmoLutSurfacesEvo( - pDevEvo, - &pWorkArea->sd[sd].head[head].newState, - head); - } - } - - PreFlipIMP(pDevEvo, pWorkArea); - - if (!skipUpdate) { - /* Trash flips pending in channel which are not yet in execution */ - SkipLayerPendingFlips(pDevEvo, TRUE /* trashPendingMethods */, - FALSE /* unblockMethodsInExecutation */, - pWorkArea); - } - - if (applyAllowVrr) { - nvSetVrrActive(pDevEvo, allowVrr); - } + nvPreFlip(pDevEvo, pWorkArea, applyAllowVrr, allowVrr, skipUpdate); for (sd = 0; sd < pDevEvo->numSubDevices; sd++) { - NVEvoUpdateState updateState = { }; + NvU32 flip2Heads1OrApiHeadsMask = 0x0; if (!pWorkArea->sd[sd].changed) { continue; @@ -3319,66 +594,32 @@ pDispEvo = pDevEvo->gpus[sd].pDispEvo; - for (head = 0; head < NVKMS_MAX_HEADS_PER_DISP; head++) { - nvFlipEvoOneHead(pDevEvo, sd, head, - &pWorkArea->sd[sd].head[head].newState, - allowFlipLock, - &updateState); - } + flip2Heads1OrApiHeadsMask = + FlipEvo2Head1OrOneDisp(pDispEvo, pWorkArea, skipUpdate); - if (!skipUpdate) { - pDevEvo->hal->Update(pDevEvo, &updateState, TRUE /* releaseElv */); - } + nvkms_memset(&pWorkArea->updateState, 0, + sizeof(pWorkArea->updateState)); - for (head = 0; head < NVKMS_MAX_HEADS_PER_DISP; head++) { - // Decrease refCnt of surfaces used BEFORE the flip - nvUpdateSurfacesFlipRefCount( - pDevEvo, - head, - &pWorkArea->sd[sd].head[head].oldState, - NV_FALSE); + for (apiHead = 0; apiHead < NVKMS_MAX_HEADS_PER_DISP; apiHead++) { + if (!nvApiHeadIsActive(pDispEvo, apiHead) || + ((NVBIT(apiHead) & flip2Heads1OrApiHeadsMask) != 0x0)) { + continue; + } - nvUnrefTmoLutSurfacesEvo( - pDevEvo, - &pWorkArea->sd[sd].head[head].oldState, - head); + FlipEvoOneApiHead(pDispEvo, apiHead, pWorkArea, allowFlipLock, + &pWorkArea->updateState); } - FillPostSyncptReply(pDevEvo, - sd, - &request->sd[sd], - &reply->sd[sd], - pWorkArea); - - } - - if (!skipUpdate) { - /* Unblock flips which are stuck in execution */ - SkipLayerPendingFlips(pDevEvo, FALSE /* trashPendingMethods */, - TRUE /* unblockMethodsInExecutation */, - pWorkArea); - } - - if (applyAllowVrr) { - vrrFlipType = nvGetActiveVrrType(pDevEvo); - vrrSemaphoreIndex = nvIncVrrSemaphoreIndex(pDevEvo); - } else { - // TODO Schedule vrr unstall; per-disp/per-device? - } - - if (reply != NULL) { - reply->vrrFlipType = vrrFlipType; - reply->vrrSemaphoreIndex = vrrSemaphoreIndex; + if (!skipUpdate) { + pDevEvo->hal->Update(pDevEvo, &pWorkArea->updateState, + TRUE /* releaseElv */); + } } - if (!skipUpdate) { - // Note that usage bounds are not lowered here, because the flip - // queued by this function may not occur until later. Instead, schedule - // a timer for later to check if the usage bounds can be lowered. - SchedulePostFlipIMP(pDevEvo); + nvPostFlip(pDevEvo, pWorkArea, skipUpdate, applyAllowVrr, &vrrSemaphoreIndex); - pDevEvo->skipConsoleRestore = FALSE; - } + FillNvKmsFlipReply(pDevEvo, pWorkArea, applyAllowVrr, vrrSemaphoreIndex, + pFlipHead, numFlipHeads, reply); /* fall through */ @@ -3497,3 +738,392 @@ TRUE /* releaseElv */); } } + +NvU32 nvApiHeadGetActiveViewportOffset(NVDispEvoRec *pDispEvo, + NvU32 apiHead) +{ + NVDevEvoRec *pDevEvo = pDispEvo->pDevEvo; + const NVDispApiHeadStateEvoRec *pApiHeadState = + &pDispEvo->apiHeadState[apiHead]; + NvU32 head, headCount; + NvU32 offset = 0; + + nvAssert(apiHead != NV_INVALID_HEAD); + + headCount = 0; + FOR_EACH_EVO_HW_HEAD_IN_MASK(pApiHeadState->hwHeadsMask, head) { + if (headCount == 0) { + offset = pDevEvo->hal->GetActiveViewportOffset(pDispEvo, head); + } else { + nvAssert(offset == pDevEvo->hal->GetActiveViewportOffset(pDispEvo, head)); + } + headCount++; + } + + return offset; +} + +void nvApiHeadIdleMainLayerChannels(NVDevEvoRec *pDevEvo, + const NvU32 apiHeadMaskPerSd[NVKMS_MAX_SUBDEVICES]) +{ + NVEvoChannelMask idleChannelMaskPerSd[NVKMS_MAX_SUBDEVICES] = { }; + const NVDispEvoRec *pDispEvo; + NvU32 dispIndex, apiHead; + NvBool found = FALSE; + + FOR_ALL_EVO_DISPLAYS(pDispEvo, dispIndex, pDevEvo) { + for (apiHead = 0; apiHead < pDevEvo->numApiHeads; apiHead++) { + const NVDispApiHeadStateEvoRec *pApiHeadState = + &pDispEvo->apiHeadState[apiHead]; + NvU32 head; + + if ((apiHeadMaskPerSd[pDispEvo->displayOwner] & + NVBIT(apiHead)) == 0x0) { + continue; + } + + FOR_EACH_EVO_HW_HEAD_IN_MASK(pApiHeadState->hwHeadsMask, head) { + NVEvoChannelPtr pMainLayerChannel = + pDevEvo->head[head].layer[NVKMS_MAIN_LAYER]; + idleChannelMaskPerSd[pDispEvo->displayOwner] |= + pMainLayerChannel->channelMask; + found = TRUE; + } + } + } + + if (!found) { + return; + } + + nvIdleMainLayerChannels(pDevEvo, idleChannelMaskPerSd, + FALSE /* allowForceIdle */); +} + +void nvApiHeadUpdateFlipLock(NVDevEvoRec *pDevEvo, + const NvU32 apiHeadMaskPerSd[NVKMS_MAX_SUBDEVICES], + const NvBool enable) +{ + NvU32 dispIndex; + NVDispEvoPtr pDispEvo; + NvU32 headMaskPerSd[NVKMS_MAX_SUBDEVICES] = { }; + NVEvoChannelMask channelMaskPerSd[NVKMS_MAX_SUBDEVICES] = { }; + NvBool found = FALSE; + + /* Determine which channels need to enable or disable fliplock. */ + FOR_ALL_EVO_DISPLAYS(pDispEvo, dispIndex, pDevEvo) { + NvU32 apiHead; + for (apiHead = 0; apiHead < pDevEvo->numApiHeads; apiHead++) { + const NVDispApiHeadStateEvoRec *pApiHeadState = + &pDispEvo->apiHeadState[apiHead]; + NvU32 head; + + if ((apiHeadMaskPerSd[pDispEvo->displayOwner] & + NVBIT(apiHead)) == 0x0) { + continue; + } + + FOR_EACH_EVO_HW_HEAD_IN_MASK(pApiHeadState->hwHeadsMask, head) { + NVEvoChannelPtr pMainLayerChannel = + pDevEvo->head[head].layer[NVKMS_MAIN_LAYER]; + + if (!nvNeedToToggleFlipLock(pDispEvo, head, enable)) { + continue; + } + + if (enable) { + /* + * Override the prohibition of fliplock on pDispEvos with + * headsurface enabled (calculated earlier in + * HsConfigAllowFlipLock) to allow enabling fliplock for + * headSurface swapgroups. + */ + nvAllowFlipLockEvo(pDispEvo, TRUE /* allowFlipLock */); + } + + headMaskPerSd[pDispEvo->displayOwner] |= NVBIT(head); + channelMaskPerSd[pDispEvo->displayOwner] |= + pMainLayerChannel->channelMask; + found = TRUE; + } + } + } + + if (!found) { + return; + } + + /* + * Wait for all base channels that are enabling/disabling fliplock to be + * idle. This shouldn't timeout if we're enabling fliplock while bringing + * up swapgroups on a new head. + */ + nvIdleMainLayerChannels(pDevEvo, channelMaskPerSd, !enable /* forceIdle */); + + /* Now that all channels are idle, update fliplock. */ + FOR_ALL_EVO_DISPLAYS(pDispEvo, dispIndex, pDevEvo) { + nvToggleFlipLockPerDisp(pDispEvo, + headMaskPerSd[pDispEvo->displayOwner], + enable); + } +} + +NvBool nvIdleMainLayerChannelCheckIdleOneApiHead(NVDispEvoPtr pDispEvo, + NvU32 apiHead) +{ + NVDevEvoPtr pDevEvo = pDispEvo->pDevEvo; + const NVDispApiHeadStateEvoRec *pApiHeadState = + &pDispEvo->apiHeadState[apiHead]; + NvU32 head; + + FOR_EACH_EVO_HW_HEAD_IN_MASK(pApiHeadState->hwHeadsMask, head) { + NVEvoChannelPtr pMainLayerChannel = + pDevEvo->head[head].layer[NVKMS_MAIN_LAYER]; + NvBool isMethodPending = FALSE; + NvBool ret; + + ret = pDevEvo->hal->IsChannelMethodPending(pDevEvo, pMainLayerChannel, + pDispEvo->displayOwner, &isMethodPending); + + if (ret && isMethodPending) { + return FALSE; + } + } + + return TRUE; +} + +NvU32 nvCollectSurfaceUsageMaskOneApiHead(const NVDispEvoRec *pDispEvo, + const NvU32 apiHead, + NVSurfaceEvoPtr pSurfaceEvo) +{ + NvU32 usageMaskOneHead = 0x0; + const NVDevEvoRec *pDevEvo = pDispEvo->pDevEvo; + const NvU32 sd = pDispEvo->displayOwner; + const NVDispApiHeadStateEvoRec *pApiHeadState = + &pDispEvo->apiHeadState[apiHead]; + NvU32 head; + + if (!nvApiHeadIsActive(pDispEvo, apiHead)) { + return 0; + } + + FOR_EACH_EVO_HW_HEAD_IN_MASK(pApiHeadState->hwHeadsMask, head) { + const NVEvoSubDevHeadStateRec *pSdHeadState = + &pDevEvo->gpus[sd].headState[head]; + NvU32 layer; + + for (layer = 0; layer < pDevEvo->head[head].numLayers; layer++) { + const NVFlipChannelEvoHwState *pLayerFlipState = + &pSdHeadState->layer[layer]; + const NVFlipSyncObjectEvoHwState *pSyncObject = + &pLayerFlipState->syncObject; + NvU32 usageMaskOneLayer = 0x0; + + if ((pSurfaceEvo == pLayerFlipState->pSurfaceEvo[NVKMS_LEFT]) || + (pSurfaceEvo == pLayerFlipState->pSurfaceEvo[NVKMS_RIGHT])) { + usageMaskOneLayer = FLD_SET_DRF(_SURFACE, _USAGE_MASK_LAYER, + _SCANOUT, _ENABLE, usageMaskOneLayer); + } + + if(pSurfaceEvo == + pLayerFlipState->completionNotifier.surface.pSurfaceEvo) { + usageMaskOneLayer = FLD_SET_DRF(_SURFACE, _USAGE_MASK_LAYER, + _NOTIFIER, _ENABLE, usageMaskOneLayer); + } + + if ((!pLayerFlipState->syncObject.usingSyncpt) && + (pSurfaceEvo == + pSyncObject->u.semaphores.acquireSurface.pSurfaceEvo) && + (pSurfaceEvo == + pSyncObject->u.semaphores.releaseSurface.pSurfaceEvo)) { + usageMaskOneLayer = FLD_SET_DRF(_SURFACE, _USAGE_MASK_LAYER, + _SEMAPHORE, _ENABLE, usageMaskOneLayer); + } + + usageMaskOneHead = FLD_IDX_SET_DRF_NUM(_SURFACE, _USAGE_MASK, + _LAYER, layer, usageMaskOneLayer, usageMaskOneHead); + } + + if (pSurfaceEvo == pSdHeadState->cursor.pSurfaceEvo) { + usageMaskOneHead = FLD_SET_DRF(_SURFACE, _USAGE_MASK, + _CURSOR, _ENABLE, usageMaskOneHead); + } + } + + return usageMaskOneHead; +} + +void nvIdleLayerChannels(NVDevEvoRec *pDevEvo, + NvU32 layerMaskPerSdApiHead[NVKMS_MAX_SUBDEVICES][NVKMS_MAX_HEADS_PER_DISP]) +{ + NVEvoChannelMask channelMaskPerSd[NVKMS_MAX_SUBDEVICES] = { }; + const NVDispEvoRec *pDispEvo; + NvU32 sd; + NvU64 startTime = 0; + const NvU32 timeout = 500000; // .5 seconds + NvBool allIdle; + + FOR_ALL_EVO_DISPLAYS(pDispEvo, sd, pDevEvo) { + for (NvU32 apiHead = 0; apiHead < pDevEvo->numApiHeads; apiHead++) { + const NVDispApiHeadStateEvoRec *pApiHeadState = + &pDispEvo->apiHeadState[apiHead]; + NvU32 head; + + if (!nvApiHeadIsActive(pDispEvo, apiHead)) { + continue; + } + + FOR_EACH_EVO_HW_HEAD_IN_MASK(pApiHeadState->hwHeadsMask, head) { + for (NvU32 layer = 0; + layer < pDevEvo->head[head].numLayers; layer++) { + if ((NVBIT(layer) & + layerMaskPerSdApiHead[sd][apiHead]) != 0x0) { + channelMaskPerSd[sd] |= + pDevEvo->head[head].layer[layer]->channelMask; + } + } + } + } + } + + do { + allIdle = TRUE; + FOR_ALL_EVO_DISPLAYS(pDispEvo, sd, pDevEvo) { + + for (NvU32 head = 0; head < pDevEvo->numHeads; head++) { + NvU32 layer; + + if (!nvHeadIsActive(pDispEvo, head)) { + continue; + } + + for (layer = 0; + layer < pDevEvo->head[head].numLayers; layer++) { + NVEvoChannelPtr pLayerChannel = + pDevEvo->head[head].layer[layer]; + NvBool isMethodPending; + + if ((pLayerChannel->channelMask & + channelMaskPerSd[sd]) == 0x0) { + continue; + } + + if (pDevEvo->hal->IsChannelMethodPending(pDevEvo, + pLayerChannel, sd, &isMethodPending) && + isMethodPending) { + + allIdle = FALSE; + } else { + /* This has been completed, no need to keep trying */ + channelMaskPerSd[sd] &= ~pLayerChannel->channelMask; + } + } + } + } + + if (!allIdle) { + if (nvExceedsTimeoutUSec(&startTime, timeout)) { + break; + } + nvkms_yield(); + } + } while (!allIdle); + + /* If we timed out above, force things to be idle. */ + if (!allIdle) { + NVEvoIdleChannelState idleChannelState = { }; + NvBool tryToForceIdle = FALSE; + + FOR_ALL_EVO_DISPLAYS(pDispEvo, sd, pDevEvo) { + + for (NvU32 head = 0; head < pDevEvo->numHeads; head++) { + NvU32 layer; + + if (!nvHeadIsActive(pDispEvo, head)) { + continue; + } + + for (layer = 0; + layer < pDevEvo->head[head].numLayers; layer++) { + NVEvoChannelPtr pLayerChannel = + pDevEvo->head[head].layer[layer]; + + if ((pLayerChannel->channelMask & + channelMaskPerSd[sd]) != 0x0) { + idleChannelState.subdev[sd].channelMask |= + pLayerChannel->channelMask; + tryToForceIdle = TRUE; + } + } + } + } + + if (tryToForceIdle) { + NvBool ret = pDevEvo->hal->ForceIdleSatelliteChannel(pDevEvo, + &idleChannelState); + if (!ret) { + nvAssert(ret); + } + } + } +} + +/* + * XXX NVKMS TODO + * Make the sync more efficient: we only need to sync if the + * in-flight methods flip away from this surface. + */ +void nvEvoClearSurfaceUsage(NVDevEvoRec *pDevEvo, + NVSurfaceEvoPtr pSurfaceEvo) +{ + NvU32 head; + + /* + * If the core channel is no longer allocated, we don't need to + * sync. This assumes the channels are allocated/deallocated + * together. + */ + if (pDevEvo->core) { + + if (pDevEvo->hal->ClearSurfaceUsage != NULL) { + pDevEvo->hal->ClearSurfaceUsage(pDevEvo, pSurfaceEvo); + } + + nvRMSyncEvoChannel(pDevEvo, pDevEvo->core, __LINE__); + + for (head = 0; head < pDevEvo->numHeads; head++) { + NvU32 layer; + + for (layer = 0; layer < pDevEvo->head[head].numLayers; layer++) { + NVEvoChannelPtr pChannel = + pDevEvo->head[head].layer[layer]; + + nvRMSyncEvoChannel(pDevEvo, pChannel, __LINE__); + } + } + } +} + +NvBool nvIdleBaseChannelOneApiHead(NVDispEvoRec *pDispEvo, NvU32 apiHead, + NvBool *pStoppedBase) +{ + NvBool ret = TRUE; + NVDevEvoPtr pDevEvo = pDispEvo->pDevEvo; + const NVDispApiHeadStateEvoRec *pApiHeadState = + &pDispEvo->apiHeadState[apiHead]; + NvU32 head; + + *pStoppedBase = FALSE; + FOR_EACH_EVO_HW_HEAD_IN_MASK(pApiHeadState->hwHeadsMask, head) { + NvBool stoppedBase = FALSE; + if (!nvRMIdleBaseChannel(pDevEvo, head, + pDispEvo->displayOwner, &stoppedBase)) { + ret = FALSE; + } else if (stoppedBase) { + *pStoppedBase = TRUE; + } + } + + return ret; +} diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia-modeset/src/nvkms-framelock.c nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia-modeset/src/nvkms-framelock.c --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia-modeset/src/nvkms-framelock.c 2023-10-25 20:22:40.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia-modeset/src/nvkms-framelock.c 2024-03-05 22:12:21.000000000 +0000 @@ -440,6 +440,8 @@ pFrameLockEvo->testMode = FALSE; pFrameLockEvo->houseSyncMode = NV_KMS_FRAMELOCK_ATTRIBUTE_HOUSE_SYNC_MODE_DISABLED; + pFrameLockEvo->mulDivValue = 1; + pFrameLockEvo->mulDivMode = NV_KMS_FRAMELOCK_ATTRIBUTE_MULTIPLY_DIVIDE_MODE_MULTIPLY; /* Query the framelock revision information */ if (nvRmApiControl(nvEvoGlobal.clientHandle, @@ -482,6 +484,9 @@ pFrameLockEvo->maxSyncInterval = gsyncGetCapsParams.maxSyncInterval; pFrameLockEvo->videoModeReadOnly = !!(gsyncGetCapsParams.capFlags & NV30F1_CTRL_GSYNC_GET_CAPS_CAP_FLAGS_ONLY_GET_VIDEO_MODE); + pFrameLockEvo->mulDivSupported = !!(gsyncGetCapsParams.capFlags & + NV30F1_CTRL_GSYNC_GET_CAPS_CAP_FLAGS_MULTIPLY_DIVIDE_SYNC); + pFrameLockEvo->maxMulDivValue = gsyncGetCapsParams.maxMulDivValue; /* Determine if house sync is selectable on this frame lock device */ if (!FrameLockUseHouseSyncGetSupport(pFrameLockEvo, @@ -866,6 +871,74 @@ } /*! + * Set the sync multiply/divide value given in val. Returns FALSE if the + * assignment failed. Assigns pFrameLockEvo->mulDivValue upon success. + */ +static NvBool SetFrameLockMulDivVal(NVFrameLockEvoPtr pFrameLockEvo, NvS64 val) +{ + NV30F1_CTRL_GSYNC_SET_CONTROL_PARAMS_PARAMS + gsyncSetControlParamsParams = { 0 }; + NvU32 ret; + + if (!pFrameLockEvo->mulDivSupported || + (val > pFrameLockEvo->maxMulDivValue)) { + return FALSE; + } + + gsyncSetControlParamsParams.which = + NV30F1_CTRL_GSYNC_SET_CONTROL_SYNC_MULTIPLY_DIVIDE; + + gsyncSetControlParamsParams.syncMulDiv.multiplyDivideValue = val; + gsyncSetControlParamsParams.syncMulDiv.multiplyDivideMode = pFrameLockEvo->mulDivMode; + + ret = nvRmApiControl(nvEvoGlobal.clientHandle, + pFrameLockEvo->device, + NV30F1_CTRL_CMD_GSYNC_SET_CONTROL_PARAMS, + &gsyncSetControlParamsParams, + sizeof(gsyncSetControlParamsParams)); + + if (ret != NVOS_STATUS_SUCCESS) return FALSE; + + pFrameLockEvo->mulDivValue = val; + + return TRUE; +} + +/*! + * Set the sync multiply/divide mode given in val. Returns FALSE if the + * assignment failed. Assigns pFrameLockEvo->mulDivMode upon success. + */ +static NvBool SetFrameLockMulDivMode(NVFrameLockEvoPtr pFrameLockEvo, NvS64 val) +{ + NV30F1_CTRL_GSYNC_SET_CONTROL_PARAMS_PARAMS + gsyncSetControlParamsParams = { 0 }; + NvU32 ret; + + if (!pFrameLockEvo->mulDivSupported || + ((val != NV_KMS_FRAMELOCK_ATTRIBUTE_MULTIPLY_DIVIDE_MODE_MULTIPLY) && + (val != NV_KMS_FRAMELOCK_ATTRIBUTE_MULTIPLY_DIVIDE_MODE_DIVIDE))) { + return FALSE; + } + + gsyncSetControlParamsParams.which = + NV30F1_CTRL_GSYNC_SET_CONTROL_SYNC_MULTIPLY_DIVIDE; + + gsyncSetControlParamsParams.syncMulDiv.multiplyDivideValue = pFrameLockEvo->mulDivValue; + gsyncSetControlParamsParams.syncMulDiv.multiplyDivideMode = val; + + ret = nvRmApiControl(nvEvoGlobal.clientHandle, + pFrameLockEvo->device, + NV30F1_CTRL_CMD_GSYNC_SET_CONTROL_PARAMS, + &gsyncSetControlParamsParams, + sizeof(gsyncSetControlParamsParams)); + + if (ret != NVOS_STATUS_SUCCESS) return FALSE; + + pFrameLockEvo->mulDivMode = val; + + return TRUE; +} +/*! * Set the sync interval to the value given in val. Returns FALSE if * the assignment failed. Assigns pFrameLockEvo->syncInterval upon * success. @@ -1129,8 +1202,7 @@ NV30F1_CTRL_GSYNC_GET_CONTROL_SYNC_PARAMS gsyncGetControlSyncParams = { 0 }; NVDispEvoPtr pDispEvo = pDpyEvo->pDispEvo; NVFrameLockEvoPtr pFrameLockEvo = pDispEvo->pFrameLockEvo; - /* XXX[2Heads1OR] Get the primary hardware head. */ - const NvU32 head = pDpyEvo->apiHead; + const NvU32 head = nvGetPrimaryHwHead(pDispEvo, pDpyEvo->apiHead); const NVDispHeadStateEvoRec *pHeadState; NvU32 ret; @@ -1343,6 +1415,12 @@ if (!FrameLockSetTestMode(pFrameLockEvo, pFrameLockEvo->testMode)) { ret = FALSE; } + if (!SetFrameLockMulDivVal(pFrameLockEvo, pFrameLockEvo->mulDivValue)) { + ret = FALSE; + } + if (!SetFrameLockMulDivMode(pFrameLockEvo, pFrameLockEvo->mulDivMode)) { + ret = FALSE; + } /* Since (we think) sync is disabled, these should always be disabled */ if (!FrameLockSetWatchdog(pFrameLockEvo, FALSE)) { @@ -1453,6 +1531,61 @@ return TRUE; } +static NvBool GetFrameLockMulDivVal(const NVFrameLockEvoRec *pFrameLockEvo, + enum NvKmsFrameLockAttribute attribute, + NvS64 *val) +{ + if (!pFrameLockEvo->mulDivSupported) { + return FALSE; + } + + *val = pFrameLockEvo->mulDivValue; + + return TRUE; +} + +static NvBool GetFrameLockMulDivValValidValues( + const NVFrameLockEvoRec *pFrameLockEvo, + struct NvKmsAttributeValidValuesCommonReply *pValidValues) +{ + nvAssert(pValidValues->type == NV_KMS_ATTRIBUTE_TYPE_RANGE); + + if (!pFrameLockEvo->mulDivSupported) { + return FALSE; + } + + pValidValues->u.range.min = 1; + pValidValues->u.range.max = pFrameLockEvo->maxMulDivValue; + + return TRUE; +} + +static NvBool GetFrameLockMulDivModeValidValues( + const NVFrameLockEvoRec *pFrameLockEvo, + struct NvKmsAttributeValidValuesCommonReply *pValidValues) +{ + if (!pFrameLockEvo->mulDivSupported) { + return FALSE; + } + + nvAssert(pValidValues->type == NV_KMS_ATTRIBUTE_TYPE_INTEGER); + + return TRUE; +} + +static NvBool GetFrameLockMulDivMode(const NVFrameLockEvoRec *pFrameLockEvo, + enum NvKmsFrameLockAttribute attribute, + NvS64 *val) +{ + if (!pFrameLockEvo->mulDivSupported) { + return FALSE; + } + + *val = pFrameLockEvo->mulDivMode; + + return TRUE; +} + static NvBool SetHouseSyncMode(NVFrameLockEvoPtr pFrameLockEvo, NvS64 val) { if ((val < 0) || (val > 31)) { @@ -2086,6 +2219,18 @@ .getValidValues = NULL, .type = NV_KMS_ATTRIBUTE_TYPE_INTEGER, }, + [NV_KMS_FRAMELOCK_ATTRIBUTE_MULTIPLY_DIVIDE_VALUE] = { + .set = SetFrameLockMulDivVal, + .get = GetFrameLockMulDivVal, + .getValidValues = GetFrameLockMulDivValValidValues, + .type = NV_KMS_ATTRIBUTE_TYPE_RANGE, + }, + [NV_KMS_FRAMELOCK_ATTRIBUTE_MULTIPLY_DIVIDE_MODE] = { + .set = SetFrameLockMulDivMode, + .get = GetFrameLockMulDivMode, + .getValidValues = GetFrameLockMulDivModeValidValues, + .type = NV_KMS_ATTRIBUTE_TYPE_INTEGER, + }, }; NvBool nvSetFrameLockAttributeEvo( @@ -2172,25 +2317,43 @@ { const NVDpyEvoRec *pDpyEvo = nvGetDpyEvoFromDispEvo(pDispEvo, pDispEvo->framelock.server); - /* XXX[2Heads1OR] Get the primary hardware head. */ - return (pDpyEvo != NULL) ? pDpyEvo->apiHead : NV_INVALID_HEAD; + return (pDpyEvo != NULL) ? nvGetPrimaryHwHead(pDispEvo, pDpyEvo->apiHead) : + NV_INVALID_HEAD; } NvU32 nvGetFramelockClientHeadsMask(const NVDispEvoRec *pDispEvo) { NvU32 headsMask = 0x0; - const NVDpyEvoRec *pDpyEvo; + const NVDpyEvoRec *pServerDpyEvo, *pClientDpyEvo; - /* - * XXX[2Heads1OR] Translate api-head -> hardware-heads, and make sure to - * include the secondary hardware-head of the server dpy. - */ - FOR_ALL_EVO_DPYS(pDpyEvo, pDispEvo->framelock.clients, pDispEvo) { - if (pDpyEvo->apiHead == NV_INVALID_HEAD) { + pServerDpyEvo = nvGetDpyEvoFromDispEvo(pDispEvo, + pDispEvo->framelock.server); + if ((pServerDpyEvo != NULL) && + (pServerDpyEvo->apiHead != NV_INVALID_HEAD)) { + const NVDispApiHeadStateEvoRec *pApiHeadState = + &pDispEvo->apiHeadState[pServerDpyEvo->apiHead]; + NvU32 primaryHead = nvGetPrimaryHwHead(pDispEvo, + pServerDpyEvo->apiHead); + + nvAssert(primaryHead != NV_INVALID_HEAD); + + /* + * The secondary hardware-head of the server dpy are client of the + * primary head. + */ + headsMask |= pApiHeadState->hwHeadsMask; + headsMask &= ~NVBIT(primaryHead); + } + + FOR_ALL_EVO_DPYS(pClientDpyEvo, pDispEvo->framelock.clients, pDispEvo) { + if (pClientDpyEvo->apiHead == NV_INVALID_HEAD) { continue; } - headsMask |= NVBIT(pDpyEvo->apiHead); + const NVDispApiHeadStateEvoRec *pApiHeadState = + &pDispEvo->apiHeadState[pClientDpyEvo->apiHead]; + headsMask |= pApiHeadState->hwHeadsMask; } + return headsMask; } @@ -2205,8 +2368,13 @@ * apiHead -> pDpyEvo mapping will get implemented. */ FOR_ALL_EVO_DPYS(pDpyEvo, pDispEvo->validDisplays, pDispEvo) { - /* XXX[2Heads1OR] Get the primary hardware head. */ - if (pDpyEvo->apiHead != head) { + /* + * XXX[2Heads1OR] Framelock is currently not supported with + * 2Heads1OR, the api head is expected to be mapped onto a single + * hardware head which is the primary hardware head. + */ + if ((pDpyEvo->apiHead == NV_INVALID_HEAD) || + (nvGetPrimaryHwHead(pDispEvo, pDpyEvo->apiHead) != head)) { continue; } diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia-modeset/src/nvkms-hal.c nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia-modeset/src/nvkms-hal.c --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia-modeset/src/nvkms-hal.c 2023-10-25 20:22:40.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia-modeset/src/nvkms-hal.c 2024-03-05 22:12:21.000000000 +0000 @@ -62,6 +62,8 @@ _supportsHDMI20, \ _inputLutAppliesToBase, \ _genericPageKind, \ + _dpYCbCr422MaxBpc, \ + _hdmiYCbCr422MaxBpc, \ _validNIsoFormatMask, \ _maxPitch, \ _maxWidthInBytes, \ @@ -91,6 +93,8 @@ .genericPageKind = _genericPageKind, \ .maxRasterWidth = DRF_MASK(NV ## _classPrefix ## 7D_HEAD_SET_RASTER_SIZE_WIDTH), \ .maxRasterHeight = DRF_MASK(NV ## _classPrefix ## 7D_HEAD_SET_RASTER_SIZE_HEIGHT),\ + .dpYCbCr422MaxBpc = _dpYCbCr422MaxBpc, \ + .hdmiYCbCr422MaxBpc = _hdmiYCbCr422MaxBpc, \ } \ } @@ -173,23 +177,33 @@ const NVEvoCapsRec evoCaps; } dispTable[] = { /* - * genericPageKind---------------------+ - * inputLutAppliesToBase ---------+ | - * supportsHDMI20 -------------+ | | - * supportsDP13 ------------+ | | | - * pEvoHal --------------+ | | | | - * windowClassPrefix | | | | | - * classPrefix | | | | | | - * | | | | | | | + * hdmiYCbCr422MaxBpc-----------------------------------------+ + * dpYCbCr422MaxBpc---------------------------------------+ | + * genericPageKind---------------------+ | | + * inputLutAppliesToBase ---------+ | | | + * supportsHDMI20 -------------+ | | | | + * supportsDP13 ------------+ | | | | | + * pEvoHal --------------+ | | | | | | + * windowClassPrefix | | | | | | | + * classPrefix | | | | | | | | + * | | | | | | | | | */ - ENTRY_NVD(C7, C6, &nvEvoC6, 1, 1, 0, TURING_GENERIC_KIND), - ENTRY_NVD(C6, C6, &nvEvoC6, 1, 1, 0, TURING_GENERIC_KIND), - ENTRY_NVD(C5, C5, &nvEvoC5, 1, 1, 0, TURING_GENERIC_KIND), - ENTRY_NVD(C3, C3, &nvEvoC3, 1, 1, 0, FERMI_GENERIC_KIND), - ENTRY_EVO(98, &nvEvo94, 1, 1, 1, FERMI_GENERIC_KIND), - ENTRY_EVO(97, &nvEvo94, 1, 1, 1, FERMI_GENERIC_KIND), - ENTRY_EVO(95, &nvEvo94, 0, 1, 1, FERMI_GENERIC_KIND), - ENTRY_EVO(94, &nvEvo94, 0, 0, 1, FERMI_GENERIC_KIND), + /* Ada */ + ENTRY_NVD(C7, C6, &nvEvoC6, 1, 1, 0, TURING_GENERIC_KIND, 12, 12), + /* Ampere */ + ENTRY_NVD(C6, C6, &nvEvoC6, 1, 1, 0, TURING_GENERIC_KIND, 12, 12), + /* Turing */ + ENTRY_NVD(C5, C5, &nvEvoC5, 1, 1, 0, TURING_GENERIC_KIND, 12, 12), + /* Volta */ + ENTRY_NVD(C3, C3, &nvEvoC3, 1, 1, 0, FERMI_GENERIC_KIND, 12, 12), + /* gp10x */ + ENTRY_EVO(98, &nvEvo94, 1, 1, 1, FERMI_GENERIC_KIND, 12, 12), + /* gp100 */ + ENTRY_EVO(97, &nvEvo94, 1, 1, 1, FERMI_GENERIC_KIND, 12, 12), + /* gm20x */ + ENTRY_EVO(95, &nvEvo94, 0, 1, 1, FERMI_GENERIC_KIND, 8, 0), + /* gm10x */ + ENTRY_EVO(94, &nvEvo94, 0, 0, 1, FERMI_GENERIC_KIND, 8, 0), }; int i; diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia-modeset/src/nvkms-hdmi.c nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia-modeset/src/nvkms-hdmi.c --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia-modeset/src/nvkms-hdmi.c 2023-10-25 20:22:40.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia-modeset/src/nvkms-hdmi.c 2024-03-05 22:12:21.000000000 +0000 @@ -65,13 +65,21 @@ */ static void CalculateVideoInfoFrameColorFormat( const NVAttributesSetEvoRec *pAttributesSet, + enum NvKmsOutputTf tf, const NvU32 hdTimings, NVT_VIDEO_INFOFRAME_CTRL *pCtrl) { + /* + * If NVKMS_OUTPUT_TF_PQ is enabled, we expect the colorSpace is RGB. This + * is enforced when the colorSpace is selected. + */ + nvAssert((tf != NVKMS_OUTPUT_TF_PQ) || + (pAttributesSet->colorSpace == + NV_KMS_DPY_ATTRIBUTE_CURRENT_COLOR_SPACE_RGB)); + // sets video infoframe colorspace (RGB/YUV). switch (pAttributesSet->colorSpace) { case NV_KMS_DPY_ATTRIBUTE_CURRENT_COLOR_SPACE_RGB: - case NV_KMS_DPY_ATTRIBUTE_CURRENT_COLOR_SPACE_BT2020RGB: pCtrl->color_space = NVT_VIDEO_INFOFRAME_BYTE1_Y1Y0_RGB; break; case NV_KMS_DPY_ATTRIBUTE_CURRENT_COLOR_SPACE_YCbCr422: @@ -91,10 +99,11 @@ // sets video infoframe colorimetry. switch (pAttributesSet->colorSpace) { case NV_KMS_DPY_ATTRIBUTE_CURRENT_COLOR_SPACE_RGB: - pCtrl->colorimetry = NVT_COLORIMETRY_RGB; - break; - case NV_KMS_DPY_ATTRIBUTE_CURRENT_COLOR_SPACE_BT2020RGB: - pCtrl->colorimetry = NVT_COLORIMETRY_BT2020RGB; + if (tf == NVKMS_OUTPUT_TF_PQ) { + pCtrl->colorimetry = NVT_COLORIMETRY_BT2020RGB; + } else { + pCtrl->colorimetry = NVT_COLORIMETRY_RGB; + } break; case NV_KMS_DPY_ATTRIBUTE_CURRENT_COLOR_SPACE_YCbCr422: case NV_KMS_DPY_ATTRIBUTE_CURRENT_COLOR_SPACE_YCbCr444: @@ -322,6 +331,41 @@ } } +/*! + * Sends General Control Packet to the HDMI sink. + */ +static void SendHdmiGcp(const NVDispEvoRec *pDispEvo, + const NvU32 head, NvBool avmute) +{ + const NVDispHeadStateEvoRec *pHeadState = &pDispEvo->headState[head]; + NVDevEvoPtr pDevEvo = pDispEvo->pDevEvo; + NVHDMIPKT_RESULT ret; + + NvU8 sb0 = avmute ? HDMI_GENCTRL_PACKET_MUTE_ENABLE : + HDMI_GENCTRL_PACKET_MUTE_DISABLE; + + NvU8 sb1 = 0; + + NvU8 sb2 = NVT_HDMI_RESET_DEFAULT_PIXELPACKING_PHASE; + + NvU8 gcp[] = { + pktType_GeneralControl, 0, 0, sb0, sb1, sb2, 0, 0, 0, 0 + }; + + ret = NvHdmiPkt_PacketWrite(pDevEvo->hdmiLib.handle, + pDispEvo->displayOwner, + pHeadState->activeRmId, + head, + NVHDMIPKT_TYPE_GENERAL_CONTROL, + NVHDMIPKT_TRANSMIT_CONTROL_ENABLE_EVERY_FRAME, + sizeof(gcp), + gcp); + + if (ret != NVHDMIPKT_SUCCESS) { + nvAssert(ret == NVHDMIPKT_SUCCESS); + } +} + /* * SendInfoFrame() - Send infoframe to the hardware through the hdmipkt * library. @@ -451,7 +495,10 @@ NVT_STATUS status; - CalculateVideoInfoFrameColorFormat(pAttributesSet, hdTimings, &videoCtrl); + CalculateVideoInfoFrameColorFormat(pAttributesSet, + pDispEvo->headState[head].tf, + hdTimings, + &videoCtrl); status = NvTiming_ConstructVideoInfoframe(pEdidInfo, &videoCtrl, @@ -614,9 +661,40 @@ } } +/* + * Uses RM control to mute HDMI audio stream at source side. + */ +static void SetHdmiAudioMute(const NVDispEvoRec *pDispEvo, + const NvU32 head, const NvBool mute) +{ + NV0073_CTRL_CMD_SPECIFIC_SET_HDMI_AUDIO_MUTESTREAM_PARAMS params = { }; + const NVDispHeadStateEvoRec *pHeadState = &pDispEvo->headState[head]; + NVDevEvoPtr pDevEvo = pDispEvo->pDevEvo; + NvU32 ret; + + params.subDeviceInstance = pDispEvo->displayOwner; + params.displayId = pHeadState->activeRmId; + params.mute = (mute ? NV0073_CTRL_SPECIFIC_SET_HDMI_AUDIO_MUTESTREAM_TRUE : + NV0073_CTRL_SPECIFIC_SET_HDMI_AUDIO_MUTESTREAM_FALSE); + + ret = nvRmApiControl(nvEvoGlobal.clientHandle, + pDevEvo->displayCommonHandle, + NV0073_CTRL_CMD_SPECIFIC_SET_HDMI_AUDIO_MUTESTREAM, + ¶ms, + sizeof(params)); + + if (ret != NVOS_STATUS_SUCCESS) { + nvAssert(!"NV0073_CTRL_CMD_SPECIFIC_SET_HDMI_AUDIO_MUTESTREAM failed"); + } +} + static void EnableHdmiAudio(const NVDispEvoRec *pDispEvo, const NvU32 head, const NvBool enable) { + /* + * XXX Is it correct to use pktType_GeneralControl to mute/unmute + * the audio? pktType_GeneralControl controls both the audio and video data. + */ static const NvU8 InfoframeMutePacket[] = { pktType_GeneralControl, 0, 0, HDMI_GENCTRL_PACKET_MUTE_ENABLE, 0, 0, 0, 0, 0, 0 @@ -924,12 +1002,13 @@ return; } + pAudioState->isAudioOverHdmi = nvDpyIsHdmiEvo(pDpyEvo); + if (FillELDBuffer(displayId, nvConnectorUsesDPLib(pDpyEvo->pConnectorEvo), &pDpyEvo->parsedEdid, &pAudioState->eld, &pAudioState->maxFreqSupported)) { - pAudioState->isAudioOverHdmi = nvDpyIsHdmiEvo(pDpyEvo); pAudioState->enabled = TRUE; } } @@ -1123,52 +1202,61 @@ return; } - if (!pHeadState->audio.enabled) { - - if (enable) { - /* Make sure to remove corresponding audio device */ + if (!enable) { + /* + * This is pre modeset code path. If audio device is enabled + * (pHeadState->audio.enabled == TRUE) then invalidate ELD buffer + * before disabling audio. + */ + if (pHeadState->audio.enabled) { RmSetELDAudioCaps(pDispEvo, pConnectorEvo, - nvDpyIdToNvU32(pConnectorEvo->displayId), + pHeadState->activeRmId, deviceEntry, 0 /* maxFreqSupported */, NULL /* pEld */, - NV_ELD_POWER_ON_RESET); - } else { - /* Do nothing. The audio device is already in the disabled state. */ - } - - return; - } - - /* Invalidate ELD buffer before disabling audio */ - if (!enable) { - RmSetELDAudioCaps(pDispEvo, - pConnectorEvo, - pHeadState->activeRmId, - deviceEntry, - 0 /* maxFreqSupported */, - NULL /* pEld */, - NV_ELD_PRE_MODESET); - } + NV_ELD_PRE_MODESET); - if (nvConnectorUsesDPLib(pConnectorEvo)) { - SetDpAudioEnable(pDispEvo, head, enable); + if (nvConnectorUsesDPLib(pConnectorEvo)) { + SetDpAudioEnable(pDispEvo, head, FALSE /* enable */); + } + } } if (pHeadState->audio.isAudioOverHdmi) { EnableHdmiAudio(pDispEvo, head, enable); + SetHdmiAudioMute(pDispEvo, head, !enable /* mute */); + SendHdmiGcp(pDispEvo, head, !enable /* avmute */); } - /* Populate ELD buffer after enabling audio */ if (enable) { - RmSetELDAudioCaps(pDispEvo, - pConnectorEvo, - pHeadState->activeRmId, - deviceEntry, - pHeadState->audio.maxFreqSupported, - &pHeadState->audio.eld, - NV_ELD_POST_MODESET); + /* + * This is post modeset code path. If audio device is enabled + * (pHeadState->audio.enabled == TRUE) then populate ELD buffer after + * enabling audio, otherwise make sure to remove corresponding audio + * device. + */ + if (pHeadState->audio.enabled) { + if (nvConnectorUsesDPLib(pConnectorEvo)) { + SetDpAudioEnable(pDispEvo, head, TRUE /* enable */); + } + + RmSetELDAudioCaps(pDispEvo, + pConnectorEvo, + pHeadState->activeRmId, + deviceEntry, + pHeadState->audio.maxFreqSupported, + &pHeadState->audio.eld, + NV_ELD_POST_MODESET); + } else { + RmSetELDAudioCaps(pDispEvo, + pConnectorEvo, + nvDpyIdToNvU32(pConnectorEvo->displayId), + deviceEntry, + 0 /* maxFreqSupported */, + NULL /* pEld */, + NV_ELD_POWER_ON_RESET); + } } } @@ -1178,10 +1266,12 @@ void nvDpyUpdateHdmiPreModesetEvo(NVDpyEvoPtr pDpyEvo) { if (!nvDpyIsHdmiEvo(pDpyEvo)) { + pDpyEvo->pConnectorEvo->isHdmiEnabled = FALSE; return; } HdmiSendEnable(pDpyEvo, TRUE); + pDpyEvo->pConnectorEvo->isHdmiEnabled = TRUE; } /* @@ -1189,6 +1279,32 @@ */ void nvDpyUpdateHdmiVRRCaps(NVDpyEvoPtr pDpyEvo) { + + const NVParsedEdidEvoRec *pParsedEdid = &pDpyEvo->parsedEdid; + const NVDispEvoRec *pDispEvo = pDpyEvo->pDispEvo; + const NVDevEvoRec *pDevEvo = pDispEvo->pDevEvo; + + const NvBool gpuSupportsHDMIVRR = pDevEvo->hal->caps.supportsHDMIVRR; + + const NvBool dispSupportsVrr = nvDispSupportsVrr(pDispEvo); + + const NvU32 edidVrrMin = pParsedEdid->info.hdmiForumInfo.vrr_min; + + nvAssert(pParsedEdid->valid); + + if (dispSupportsVrr && gpuSupportsHDMIVRR && (edidVrrMin > 0)) { + if (nvDpyIsAdaptiveSyncDefaultlisted(pDpyEvo)) { + pDpyEvo->vrr.type = + NVKMS_DPY_VRR_TYPE_ADAPTIVE_SYNC_DEFAULTLISTED; + } else { + pDpyEvo->vrr.type = + NVKMS_DPY_VRR_TYPE_ADAPTIVE_SYNC_NON_DEFAULTLISTED; + } + + pDpyEvo->vrr.needsSwFramePacing = TRUE; + + pDpyEvo->vrr.edidTimeoutMicroseconds = 1000000 / edidVrrMin; + } } void nvRemoveUnusedHdmiDpAudioDevice(const NVDispEvoRec *pDispEvo) @@ -1201,7 +1317,7 @@ // Only connectors with assigned SORs can have audio. if (pConnectorEvo->or.type != NV0073_CTRL_SPECIFIC_OR_TYPE_SOR || - pConnectorEvo->or.mask == 0x0) { + pConnectorEvo->or.primary == NV_INVALID_OR) { continue; } @@ -1211,7 +1327,7 @@ // NV0073_CTRL_CMD_DFP_SET_ELD_AUDIO_CAPS takes a displayId rather than // an SOR index. See bug 1953489. if (nvIsConnectorActiveEvo(pConnectorEvo) && - (pConnectorEvo->or.mask & activeSorMask) != 0x0) { + (NVBIT(pConnectorEvo->or.primary) & activeSorMask) != 0x0) { continue; } @@ -1621,6 +1737,7 @@ sizeof(empCtrl)); empCtrl.EnableVRR = enable; + empCtrl.EnableQMS = FALSE; status = NvTiming_ConstructExtendedMetadataPacketInfoframe(&empCtrl, &empInfoFrame); @@ -1924,9 +2041,12 @@ * * Returns TRUE if FRL is needed, or FALSE otherwise. * */ -static NvBool HdmiTimingsNeedFrl(const NVDpyEvoRec *pDpyEvo, - const NvU32 pixelClock) +NvBool nvHdmiTimingsNeedFrl(const NVDpyEvoRec *pDpyEvo, + const NVHwModeTimingsEvo *pHwTimings) { + const NvU32 pixelClock = (pHwTimings->yuv420Mode == NV_YUV420_MODE_HW) ? + (pHwTimings->pixelClock / 2) : pHwTimings->pixelClock; + nvAssert(nvDpyIsHdmiEvo(pDpyEvo)); /* @@ -1936,11 +2056,47 @@ return pixelClock > pDpyEvo->maxSingleLinkPixelClockKHz; } +static NvU64 GetHdmiFrlLinkRate(HDMI_FRL_DATA_RATE frlRate) +{ + const NvU64 giga = 1000000000ULL; + NvU64 hdmiLinkRate = 0; + switch(frlRate ) + { + case HDMI_FRL_DATA_RATE_NONE: + hdmiLinkRate = 0; + break; + case HDMI_FRL_DATA_RATE_3LANES_3GBPS: + hdmiLinkRate = 3 * giga; + break; + case HDMI_FRL_DATA_RATE_3LANES_6GBPS: + case HDMI_FRL_DATA_RATE_4LANES_6GBPS: + hdmiLinkRate = 6 * giga; + break; + case HDMI_FRL_DATA_RATE_4LANES_8GBPS: + hdmiLinkRate = 8 * giga; + break; + case HDMI_FRL_DATA_RATE_4LANES_10GBPS: + hdmiLinkRate = 10 * giga; + break; + case HDMI_FRL_DATA_RATE_4LANES_12GBPS: + hdmiLinkRate = 12 * giga; + break; + case HDMI_FRL_DATA_RATE_UNSPECIFIED: + nvAssert(!"Unspecified FRL data rate"); + break; + }; + + return hdmiLinkRate; +} + NvBool nvHdmiFrlQueryConfig( const NVDpyEvoRec *pDpyEvo, const NvModeTimings *pModeTimings, - NVHwModeTimingsEvo *pHwTimings, - const struct NvKmsModeValidationParams *pValidationParams) + const NVHwModeTimingsEvo *pHwTimings, + const NvBool b2Heads1Or, + const struct NvKmsModeValidationParams *pValidationParams, + HDMI_FRL_CONFIG *pConfig, + NVDscInfoEvoRec *pDscInfo) { const NVDispEvoRec *pDispEvo = pDpyEvo->pDispEvo; const NVDevEvoRec *pDevEvo = pDispEvo->pDevEvo; @@ -1950,14 +2106,15 @@ NVT_TIMING nvtTiming = { }; NVHDMIPKT_RESULT ret; - if (!nvDpyIsHdmiEvo(pDpyEvo) || - !HdmiTimingsNeedFrl(pDpyEvo, pHwTimings->pixelClock)) { + if (pHwTimings->protocol != NVKMS_PROTOCOL_SOR_HDMI_FRL) { + nvkms_memset(pDscInfo, 0, sizeof(*pDscInfo)); + nvkms_memset(pConfig, 0, sizeof(*pConfig)); return TRUE; } - if (!nvHdmiDpySupportsFrl(pDpyEvo)) { - return FALSE; - } + nvAssert(nvDpyIsHdmiEvo(pDpyEvo) && + nvHdmiDpySupportsFrl(pDpyEvo) && + nvHdmiTimingsNeedFrl(pDpyEvo, pHwTimings)); /* See if we can find an NVT_TIMING for this mode from the EDID. */ pNvtTiming = nvFindEdidNVT_TIMING(pDpyEvo, pModeTimings, pValidationParams); @@ -2021,14 +2178,23 @@ videoTransportInfo.packing = HDMI_PIXEL_PACKING_YCbCr420; break; } - /* TODO: implement 2head1or+FRL */ - videoTransportInfo.bDualHeadMode = FALSE; + + videoTransportInfo.bDualHeadMode = b2Heads1Or; clientControl.option = HDMI_QUERY_FRL_HIGHEST_PIXEL_QUALITY; if (pValidationParams->forceDsc) { clientControl.enableDSC = TRUE; } + + /* + * 2Heads1Or requires either YUV420 or DSC; if b2Heads1Or is enabled + * but YUV420 is not, force DSC. + */ + if (b2Heads1Or && (pHwTimings->yuv420Mode != NV_YUV420_MODE_HW)) { + clientControl.enableDSC = TRUE; + } + if (pValidationParams->dscOverrideBitsPerPixelX16 != 0) { clientControl.forceBppx16 = TRUE; clientControl.bitsPerPixelX16 = @@ -2040,7 +2206,54 @@ &clientControl, &pDpyEvo->hdmi.srcCaps, &pDpyEvo->hdmi.sinkCaps, - &pHwTimings->hdmiFrlConfig); + pConfig); + + if ((ret == NVHDMIPKT_SUCCESS) && b2Heads1Or) { + /* + * 2Heads1Or requires either YUV420 or DSC; pConfig->dscInfo.bEnableDSC + * is assigned by NvHdmi_QueryFRLConfig(). + */ + nvAssert(pConfig->dscInfo.bEnableDSC || + (pHwTimings->yuv420Mode == NV_YUV420_MODE_HW)); + } + + if (ret == NVHDMIPKT_SUCCESS && (pDscInfo != NULL)) { + const NvU64 hdmiLinkRate = GetHdmiFrlLinkRate(pConfig->frlRate); + + nvAssert((hdmiLinkRate != 0) || + (pConfig->frlRate == HDMI_FRL_DATA_RATE_NONE)); + + nvkms_memset(pDscInfo, 0, sizeof(*pDscInfo)); + + if ((pConfig->frlRate != HDMI_FRL_DATA_RATE_NONE) && + pConfig->dscInfo.bEnableDSC && + (hdmiLinkRate != 0)) { + pDscInfo->type = NV_DSC_INFO_EVO_TYPE_HDMI; + pDscInfo->hdmi.dscMode = b2Heads1Or ? + NV_DSC_EVO_MODE_DUAL : NV_DSC_EVO_MODE_SINGLE; + pDscInfo->hdmi.bitsPerPixelX16 = + pConfig->dscInfo.bitsPerPixelX16; + ct_assert(sizeof(pDscInfo->hdmi.pps) == + sizeof(pConfig->dscInfo.pps)); + nvkms_memcpy(pDscInfo->hdmi.pps, + pConfig->dscInfo.pps, + sizeof(pDscInfo->hdmi.pps)); + pDscInfo->hdmi.dscHActiveBytes = + pConfig->dscInfo.dscHActiveBytes; + pDscInfo->hdmi.dscHActiveTriBytes = + pConfig->dscInfo.dscHActiveTriBytes; + pDscInfo->hdmi.dscHBlankTriBytes = + pConfig->dscInfo.dscHBlankTriBytes; + pDscInfo->hdmi.dscTBlankToTTotalRatioX1k = + pConfig->dscInfo.dscTBlankToTTotalRatioX1k; + pDscInfo->hdmi.hblankMin = + NV_UNSIGNED_DIV_CEIL(((pHwTimings->pixelClock * 1000) * + pConfig->dscInfo.dscHBlankTriBytes), + (hdmiLinkRate / 6)); + } else { + pDscInfo->type = NV_DSC_INFO_EVO_TYPE_DISABLED; + } + } return ret == NVHDMIPKT_SUCCESS; } @@ -2062,7 +2275,7 @@ const NVDevEvoRec *pDevEvo = pDispEvo->pDevEvo; NVDispHeadStateEvoRec *pHeadState = &pDispEvo->headState[head]; - HDMI_FRL_CONFIG *pFrlConfig = &pHeadState->timings.hdmiFrlConfig; + HDMI_FRL_CONFIG *pFrlConfig = &pHeadState->hdmiFrlConfig; NVHDMIPKT_RESULT ret; NvU32 retries = 0; const NvU32 MAX_RETRIES = 5; diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia-modeset/src/nvkms-headsurface-config.c nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia-modeset/src/nvkms-headsurface-config.c --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia-modeset/src/nvkms-headsurface-config.c 2023-10-25 20:22:40.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia-modeset/src/nvkms-headsurface-config.c 2024-03-05 22:12:22.000000000 +0000 @@ -27,12 +27,14 @@ #include "nvkms-headsurface-3d.h" #include "nvkms-headsurface-matrix.h" #include "nvkms-headsurface-swapgroup.h" +#include "nvkms-utils-flip.h" #include "nvkms-flip.h" #include "nvkms-utils.h" #include "nvkms-surface.h" #include "nvkms-private.h" #include "nvkms-evo.h" #include "nvkms-modeset.h" +#include "nvkms-stereo.h" #include "nvkms-prealloc.h" #include "nvidia-push-utils.h" /* nvPushIdleChannel() */ @@ -698,16 +700,16 @@ for (layer = 0; layer < ARRAY_LEN(pHsConfigOneHead->layer); layer++) { - const NVFlipChannelEvoHwState *pHwState = + const NVHsLayerRequestedFlipState *pFlipState = HsGetLastFlipQueueEntry(pHsChannel, layer); /* both structures have the same number of eyes */ ct_assert(ARRAY_LEN(pHsConfigOneHead->layer[layer].pSurfaceEvo) == - ARRAY_LEN(pHwState->pSurfaceEvo)); + ARRAY_LEN(pFlipState->pSurfaceEvo)); for (eye = NVKMS_LEFT; eye < NVKMS_MAX_EYES; eye++) { pHsConfigOneHead->layer[layer].pSurfaceEvo[eye] = - pHwState->pSurfaceEvo[eye]; + pFlipState->pSurfaceEvo[eye]; } } } @@ -1010,7 +1012,7 @@ pChannelConfig->eyeMask = NVBIT(NVKMS_LEFT); - if (pTimings->stereo.mode != NVKMS_STEREO_DISABLED) { + if (pApiHeadState->stereo.mode != NVKMS_STEREO_DISABLED) { pChannelConfig->eyeMask |= NVBIT(NVKMS_RIGHT); } @@ -1067,23 +1069,11 @@ NVHsChannelConfig *pChannelConfig = &pHsConfigOneHead->channelConfig; /* - * If (pDevEvo->modesetOwner == NULL) that means either the vbios - * console or the NVKMS console might be active, the console - * surface may not be set up to be the source of headSurface - * operations, and NVKMS may be unloaded, so we can't have the - * display rely on headSurface. + * The console surface may not be set up to be the source of + * headSurface operations, and NVKMS may be unloaded, so we can't + * have the display rely on headSurface. */ - if (pDevEvo->modesetOwner == NULL) { - continue; - } - - /* - * If (pDevEvo->modesetOwner != NULL) but - * pDevEvo->modesetOwnerChanged is TRUE, that means the modeset - * ownership is grabbed by the external client but it hasn't - * performed any modeset and the console is still active. - */ - if ((pDevEvo->modesetOwner != NULL) && pDevEvo->modesetOwnerChanged) { + if (nvEvoIsConsoleActive(pDevEvo)) { continue; } @@ -1818,7 +1808,7 @@ */ for (layer = 0; layer < ARRAY_LEN(pHsConfigOneHead->layer); layer++) { - NVFlipChannelEvoHwState hwState = { }; + NVHsLayerRequestedFlipState hwState = { }; nvkms_memset(&pHsChannel->flipQueue[layer], 0, sizeof(pHsChannel->flipQueue[layer])); @@ -1884,26 +1874,22 @@ const NVDispEvoRec *pDispEvo = pHsChannel->pDispEvo; NVDevEvoRec *pDevEvo = pDispEvo->pDevEvo; const NvU32 apiHead = pHsChannel->apiHead; - struct NvKmsFlipRequest *pRequest; - struct NvKmsFlipParams *pFlipParams; const NvU32 sd = pDispEvo->displayOwner; NvBool ret; NvU8 eye; struct NvKmsFlipCommonParams *pParamsOneHead; /* - * Use a preallocated NvKmsFlipRequest, so that we don't have to allocate + * Use preallocated memory, so that we don't have to allocate * memory here (and deal with allocation failure). */ - pFlipParams = &pHsChannel->scratchParams; - - nvkms_memset(pFlipParams, 0, sizeof(*pFlipParams)); + struct NvKmsFlipRequestOneHead *pFlipHead = &pHsChannel->scratchParams; - pRequest = &pFlipParams->request; + nvkms_memset(pFlipHead, 0, sizeof(*pFlipHead)); - pRequest->commit = NV_TRUE; - - pParamsOneHead = &pRequest->sd[sd].head[apiHead]; + pFlipHead->sd = sd; + pFlipHead->head = apiHead; + pParamsOneHead = &pFlipHead->flip; pParamsOneHead->layer[NVKMS_MAIN_LAYER].surface.specified = TRUE; @@ -1941,12 +1927,13 @@ pParamsOneHead->cursor.position = cursorPosition; pParamsOneHead->cursor.positionSpecified = TRUE; - pRequest->sd[sd].requestedHeadsBitMask = NVBIT(apiHead); - ret = nvFlipEvo(pDevEvo, pDevEvo->pNvKmsOpenDev, - pRequest, - &pFlipParams->reply, + pFlipHead, + 1 /* numFlipHeads */, + TRUE /* commit */, + FALSE /* allowVrr */, + NULL /* pReply */, FALSE /* skipUpdate */, FALSE /* allowFlipLock */); @@ -2058,112 +2045,6 @@ } } - -/*! - * Wait for idle on a set of base channels. - * - * \param[in,out] pDevEvo The device. - * \param[in] idleChannelMaskPerSd The channel masks per subdevice that - * we should wait to be idle. - * \param[in] allowStopBase Whether we should stop base or just - * assert if the idle times out. - */ -static void HsConfigIdleBaseChannels( - NVDevEvoPtr pDevEvo, - const NVEvoChannelMask *idleChannelMaskPerSd, - NvBool allowStopBase) -{ - NvU64 startTime = 0; - NvBool allChannelsIdle = FALSE; - NVDispEvoPtr pDispEvo; - NvU32 dispIndex, head; - NVEvoChannelMask busyChannelMaskPerSd[NVKMS_MAX_SUBDEVICES] = { }; - - /* - * Wait up to 2 seconds for all channels to be idle, and gather a list of - * all busy channels. - */ - while (!allChannelsIdle) { - - const NvU32 timeout = 2000000; /* 2 seconds */ - NvBool anyChannelBusy = FALSE; - - FOR_ALL_EVO_DISPLAYS(pDispEvo, dispIndex, pDevEvo) { - for (head = 0; head < pDevEvo->numHeads; head++) { - NVEvoChannelPtr pMainLayerChannel = - pDevEvo->head[head].layer[NVKMS_MAIN_LAYER]; - if (idleChannelMaskPerSd[pDispEvo->displayOwner] & - pMainLayerChannel->channelMask) { - - NvBool isMethodPending = FALSE; - if (!pDevEvo->hal->IsChannelMethodPending( - pDevEvo, - pMainLayerChannel, - pDispEvo->displayOwner, - &isMethodPending) - || isMethodPending) { - - /* Mark this channel as busy. */ - busyChannelMaskPerSd[pDispEvo->displayOwner] |= - pMainLayerChannel->channelMask; - anyChannelBusy = TRUE; - } else { - /* - * Mark this channel as no longer busy, in case its - * flip completed while we were waiting on another - * channel. - */ - busyChannelMaskPerSd[pDispEvo->displayOwner] &= - ~pMainLayerChannel->channelMask; - } - } - } - } - - if (!anyChannelBusy) { - allChannelsIdle = TRUE; - break; - } - - /* Break out of the loop if we exceed the timeout. */ - if (nvExceedsTimeoutUSec(&startTime, timeout)) { - break; - } - - nvkms_yield(); - } - - if (!allChannelsIdle) { - /* - * At least one channel was still idle after the 2 second timeout - * above. - */ - if (!allowStopBase) { - /* - * The caller of this function expected this wait for idle not to - * time out. - */ - nvEvoLogDev(pDevEvo, EVO_LOG_WARN, - "Timeout while waiting for idle."); - } else { - /* - * Idle all base channels that were still busy when the wait above - * timed out. - */ - NVEvoIdleChannelState idleChannelState = { }; - - FOR_ALL_EVO_DISPLAYS(pDispEvo, dispIndex, pDevEvo) { - idleChannelState.subdev[pDispEvo->displayOwner].channelMask = - busyChannelMaskPerSd[pDispEvo->displayOwner]; - } - - pDevEvo->hal->ForceIdleSatelliteChannelIgnoreLock( - pDevEvo, &idleChannelState); - } - } -} - - /*! * Enable or disable fliplock on all channels using headsurface for swapgroups, * waiting for idle if necessary. @@ -2171,27 +2052,19 @@ static void HsConfigUpdateFlipLockForSwapGroups(NVDevEvoPtr pDevEvo, NvBool enable) { - NvU32 dispIndex, head; + NvU32 dispIndex, apiHead; NVDispEvoPtr pDispEvo; - NVEvoChannelMask flipLockToggleChannelMaskPerSd[NVKMS_MAX_SUBDEVICES] = { }; + NvU32 flipLockToggleApiHeadMaskPerSd[NVKMS_MAX_SUBDEVICES] = { }; + NvBool found = FALSE; - /* Determine which channels need to enable or disable fliplock. */ FOR_ALL_EVO_DISPLAYS(pDispEvo, dispIndex, pDevEvo) { - - for (head = 0; head < pDevEvo->numHeads; head++) { - const NvU32 apiHead = nvHardwareHeadToApiHead(head); + for (apiHead = 0; apiHead < pDevEvo->numApiHeads; apiHead++) { NVHsChannelEvoPtr pHsChannel = pDispEvo->pHsChannel[apiHead]; if (pHsChannel == NULL) { continue; } - NVEvoSubDevPtr pEvoSubDev = &pDevEvo->gpus[pDispEvo->displayOwner]; - NVEvoHeadControlPtr pHC = &pEvoSubDev->headControl[head]; - NVEvoChannelPtr pMainLayerChannel = - pDevEvo->head[head].layer[NVKMS_MAIN_LAYER]; - NvBool setFlipLock = FALSE; - /* * This function is called in two cases, when disabling fliplock for * the pHsChannels in the previous config, and when enabling @@ -2204,82 +2077,17 @@ continue; } - if (!enable && pHC->flipLock) { - /* - * This channel is currently using fliplock in the config that - * is being torn down; idle its base channel and disable - * fliplock. - */ - setFlipLock = TRUE; - } - - if (enable && ((pHC->serverLock != NV_EVO_NO_LOCK) || - (pHC->clientLock != NV_EVO_NO_LOCK))) { - /* - * This channel will be using fliplock for swap groups in the - * new config; idle its base channel and enable fliplock. - */ - - /* - * Override the prohibition of fliplock on pDispEvos with - * headsurface enabled (calculated earlier in - * HsConfigAllowFlipLock) to allow enabling fliplock for - * headSurface swapgroups. - */ - nvAllowFlipLockEvo(pDispEvo, TRUE /* allowFlipLock */); - - nvAssert(!HEAD_MASK_QUERY(pEvoSubDev->flipLockProhibitedHeadMask, - head)); - setFlipLock = TRUE; - } - - if (!setFlipLock) { - continue; - } - - flipLockToggleChannelMaskPerSd[pDispEvo->displayOwner] |= - pMainLayerChannel->channelMask; + flipLockToggleApiHeadMaskPerSd[pDispEvo->displayOwner] |= + NVBIT(apiHead); + found = TRUE; } } - /* - * Wait for all base channels that are enabling/disabling fliplock to be - * idle. This shouldn't timeout if we're enabling fliplock while bringing - * up swapgroups on a new head. - */ - HsConfigIdleBaseChannels(pDevEvo, - flipLockToggleChannelMaskPerSd, - !enable /* allowStopBase */); - - /* Now that all channels are idle, update fliplock. */ - FOR_ALL_EVO_DISPLAYS(pDispEvo, dispIndex, pDevEvo) { - NVEvoUpdateState updateState = { }; - - if (!flipLockToggleChannelMaskPerSd[pDispEvo->displayOwner]) { - continue; - } - - for (head = 0; head < pDevEvo->numHeads; head++) { - NVEvoChannelPtr pMainLayerChannel = - pDevEvo->head[head].layer[NVKMS_MAIN_LAYER]; - if (flipLockToggleChannelMaskPerSd[pDispEvo->displayOwner] & - pMainLayerChannel->channelMask) { - - NvU32 setEnable = enable; - - if (!nvUpdateFlipLockEvoOneHead(pDispEvo, head, &setEnable, - TRUE /* set */, - NULL /* needsEarlyUpdate */, - &updateState)) { - nvEvoLogDev(pDevEvo, EVO_LOG_WARN, - "Failed to toggle fliplock for swapgroups."); - } - } - } - - nvEvoUpdateAndKickOff(pDispEvo, TRUE, &updateState, - TRUE /* releaseElv */); + if (!found) { + return; } + + nvApiHeadUpdateFlipLock(pDevEvo, flipLockToggleApiHeadMaskPerSd, enable); } /*! @@ -2303,7 +2111,7 @@ NvU32 dispIndex, apiHead; NVDispEvoPtr pDispEvo; NVHsDeviceEvoPtr pHsDevice = pDevEvo->pHsDevice; - NVEvoChannelMask hsDisableChannelMaskPerSd[NVKMS_MAX_SUBDEVICES] = { }; + NvU32 hsDisableApiHeadMaskPerSd[NVKMS_MAX_SUBDEVICES] = { }; /* * We should only get here if this configuration is going to be committed. @@ -2319,19 +2127,15 @@ /* Flip all headSurface heads to NULL. */ FOR_ALL_EVO_DISPLAYS(pDispEvo, dispIndex, pDevEvo) { - NvU32 head; - for (head = 0; head < pDevEvo->numHeads; head++) { - const NvU32 apiHead = nvHardwareHeadToApiHead(head); + NvU32 apiHead; + for (apiHead = 0; apiHead < pDevEvo->numApiHeads; apiHead++) { NVHsChannelEvoPtr pHsChannel = pDispEvo->pHsChannel[apiHead]; if (pHsChannel != NULL) { - NVEvoChannelPtr pMainLayerChannel = - pDevEvo->head[head].layer[NVKMS_MAIN_LAYER]; - hsDisableChannelMaskPerSd[pDispEvo->displayOwner] |= - pMainLayerChannel->channelMask; + hsDisableApiHeadMaskPerSd[pDispEvo->displayOwner] |= NVBIT(apiHead); if (pHsChannel->config.pixelShift == NVKMS_PIXEL_SHIFT_8K) { - nvSetStereoEvo(pDispEvo, head, FALSE); + nvSetStereo(pDispEvo, apiHead, FALSE); } if (pHsChannel->config.neededForSwapGroup) { @@ -2353,14 +2157,13 @@ } /* - * Wait for base to be idle on all channels that previously had headSurface - * enabled in order to allow semaphore releases from previous headSurface - * flips to complete. This wait should not timeout, so if it does, just - * assert instead of forcing the channels idle. - */ - HsConfigIdleBaseChannels(pDevEvo, - hsDisableChannelMaskPerSd, - FALSE /* allowStopBase */); + * Wait for main layer channels to be idle on all channels that previously + * had headSurface enabled in order to allow semaphore releases from + * previous headSurface flips to complete. This wait should not timeout, + * so if it does, just assert instead of forcing the channels idle. + */ + nvApiHeadIdleMainLayerChannels(pDevEvo, + hsDisableApiHeadMaskPerSd); /* Update bookkeeping and restore the original surface in main layer. */ FOR_ALL_EVO_DISPLAYS(pDispEvo, dispIndex, pDevEvo) { @@ -2424,7 +2227,7 @@ NVDevEvoPtr pDevEvo, NVHsConfig *pHsConfig) { - NvU32 dispIndex, head; + NvU32 dispIndex, apiHead; NVDispEvoPtr pDispEvo; NVHsDeviceEvoPtr pHsDevice = pDevEvo->pHsDevice; NvBool allowFlipLock; @@ -2438,8 +2241,7 @@ FOR_ALL_EVO_DISPLAYS(pDispEvo, dispIndex, pDevEvo) { - for (head = 0; head < pDevEvo->numHeads; head++) { - const NvU32 apiHead = nvHardwareHeadToApiHead(head); + for (apiHead = 0; apiHead < pDevEvo->numApiHeads; apiHead++) { NVHsConfigOneHead *pHsConfigOneHead = &pHsConfig->apiHead[dispIndex][apiHead]; @@ -2503,9 +2305,8 @@ /* Update surfaces. */ - for (head = 0; head < pDevEvo->numHeads; head++) { + for (apiHead = 0; apiHead < pDevEvo->numApiHeads; apiHead++) { - const NvU32 apiHead = nvHardwareHeadToApiHead(head); NVHsStateOneHeadAllDisps *pDevEvoHsConfig = &pDevEvo->apiHeadSurfaceAllDisps[apiHead]; NVHsStateOneHeadAllDisps *pHsOneHeadAllDisps = @@ -2580,8 +2381,7 @@ FOR_ALL_EVO_DISPLAYS(pDispEvo, dispIndex, pDevEvo) { - for (head = 0; head < pDevEvo->numHeads; head++) { - const NvU32 apiHead = nvHardwareHeadToApiHead(head); + for (apiHead = 0; apiHead < pDevEvo->numApiHeads; apiHead++) { NVHsChannelEvoPtr pHsChannel = pDispEvo->pHsChannel[apiHead]; const NVHsConfigOneHead *pHsConfigOneHead = &pHsConfig->apiHead[dispIndex][apiHead]; @@ -2636,7 +2436,7 @@ NV_HS_NEXT_FRAME_REQUEST_TYPE_FIRST_FRAME); if (pHsChannel->config.pixelShift == NVKMS_PIXEL_SHIFT_8K) { - nvSetStereoEvo(pDispEvo, head, TRUE); + nvSetStereo(pDispEvo, apiHead, TRUE); } } } diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia-modeset/src/nvkms-headsurface-ioctl.c nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia-modeset/src/nvkms-headsurface-ioctl.c --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia-modeset/src/nvkms-headsurface-ioctl.c 2023-10-25 20:22:40.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia-modeset/src/nvkms-headsurface-ioctl.c 2024-03-05 22:12:22.000000000 +0000 @@ -22,11 +22,14 @@ */ #include "nvkms-types.h" +#include "nvkms-private.h" #include "nvkms-headsurface.h" #include "nvkms-headsurface-ioctl.h" #include "nvkms-headsurface-priv.h" +#include "nvkms-ioctl.h" #include "nvkms-cursor.h" #include "nvkms-utils.h" +#include "nvkms-utils-flip.h" #include "nvkms-flip.h" /* @@ -51,50 +54,20 @@ * - Apply the request to the headSurface-ful heads. */ -/*! - * Assign headSurface bitmasks. - * - * Given requestedHeadsBitMask and a disp, assign a head bitmasks of the - * headSurface-ful heads and headSurface-less heads. - * - * Fail if requestedHeadsBitMask contains invalid heads. - */ -static NvBool HsIoctlGetBitMasks( - const NVDispEvoRec *pDispEvo, - const NvU32 requestedHeadsBitMask, - NvU32 *pHsMask, - NvU32 *pNonHsMask) -{ - NvU32 hsMask = 0; - NvU32 nonHsMask = 0; - NvU32 head; +typedef struct _NVHsRequestedFlipState { + struct NvKmsPoint viewPortPointIn; + NVFlipCursorEvoHwState cursor; + NVHsLayerRequestedFlipState layer[NVKMS_MAX_LAYERS_PER_HEAD]; - if (nvHasBitAboveMax(requestedHeadsBitMask, pDispEvo->pDevEvo->numHeads)) { - return FALSE; - } - - FOR_EACH_INDEX_IN_MASK(32, head, requestedHeadsBitMask) { - const NvU32 apiHead = nvHardwareHeadToApiHead(head); - if (pDispEvo->pHsChannel[apiHead] == NULL) { - nonHsMask |= NVBIT(head); - } else { - hsMask |= NVBIT(head); - } - - } FOR_EACH_INDEX_IN_MASK_END; + struct { + NvBool viewPortPointIn : 1; + NvBool cursorSurface : 1; + NvBool cursorPosition : 1; - /* - * Each bit from the original mask should be in exactly one of hsMask or - * nonHsMask. - */ - nvAssert((hsMask | nonHsMask) == requestedHeadsBitMask); - nvAssert((hsMask & nonHsMask) == 0); + NvBool layer[NVKMS_MAX_LAYERS_PER_HEAD]; + } dirty; - *pHsMask = hsMask; - *pNonHsMask = nonHsMask; - - return TRUE; -} +} NVHsRequestedFlipState; /*! * Validate the NvKmsMoveCursorCommonParams for headSurface. @@ -132,10 +105,9 @@ */ NvBool nvHsIoctlMoveCursor( NVDispEvoPtr pDispEvo, - NvU32 head, + NvU32 apiHead, const struct NvKmsMoveCursorCommonParams *pParams) { - const NvU32 apiHead = nvHardwareHeadToApiHead(head); NVHsChannelEvoRec *pHsChannel; if (apiHead > ARRAY_LEN(pDispEvo->pHsChannel)) { @@ -147,7 +119,7 @@ /* If headSurface is not used on this head, call down. */ if (pHsChannel == NULL) { - nvEvoMoveCursor(pDispEvo, head, pParams); + nvMoveCursor(pDispEvo, apiHead, pParams); return TRUE; } @@ -228,10 +200,9 @@ NVDispEvoPtr pDispEvo, const struct NvKmsPerOpenDev *pOpenDevice, const NVEvoApiHandlesRec *pOpenDevSurfaceHandles, - NvU32 head, + NvU32 apiHead, const struct NvKmsSetCursorImageCommonParams *pParams) { - const NvU32 apiHead = nvHardwareHeadToApiHead(head); NVHsChannelEvoRec *pHsChannel; NVSurfaceEvoRec *pSurfaceEvo = NULL; @@ -247,7 +218,7 @@ return nvSetCursorImage(pDispEvo, pOpenDevice, pOpenDevSurfaceHandles, - head, + apiHead, pParams); } @@ -280,36 +251,34 @@ } /*! - * Create a copy of NvKmsFlipRequest with the headSurface-ful heads removed. + * Create a copy of pFlipHead[] array with the headSurface-ful heads removed. */ -static struct NvKmsFlipRequest *HsIoctlRemoveHsHeadsFromNvKmsFlipRequest( +static struct NvKmsFlipRequestOneHead *HsIoctlRemoveHsHeadsFromNvKmsFlipHead( NVDevEvoPtr pDevEvo, - const struct NvKmsFlipRequest *pRequestOriginal, - const NvU32 hsMask[NVKMS_MAX_SUBDEVICES]) -{ - NVDispEvoPtr pDispEvo; - NvU32 head, sd; - - struct NvKmsFlipRequest *pRequest = nvAlloc(sizeof(*pRequest)); - - if (pRequest == NULL) { - return FALSE; - } - - *pRequest = *pRequestOriginal; - - FOR_ALL_EVO_DISPLAYS(pDispEvo, sd, pDevEvo) { - FOR_EACH_INDEX_IN_MASK(32, head, hsMask[sd]) { - - nvkms_memset(&pRequest->sd[sd].head[head], 0, - sizeof(pRequest->sd[sd].head[head])); - - pRequest->sd[sd].requestedHeadsBitMask &= ~NVBIT(head); - - } FOR_EACH_INDEX_IN_MASK_END; + const struct NvKmsFlipRequestOneHead *pFlipHeadOriginal, + const NvU32 numFlipHeadsOriginal, + const NvU32 numFlipHeads, + const NvU8 hsMask[NVKMS_MAX_SUBDEVICES]) +{ + struct NvKmsFlipRequestOneHead *pFlipHead = NULL; + NvU32 i, j; + + pFlipHead = nvAlloc(sizeof(*pFlipHead) * numFlipHeads); + if (pFlipHead == NULL) { + return NULL; + } + + j = 0; + for (i = 0; i < numFlipHeadsOriginal; i++) { + const NvU32 apiHead = pFlipHeadOriginal[i].head; + const NvU32 sd = pFlipHeadOriginal[i].sd; + if ((hsMask[sd] & NVBIT(apiHead)) == 0) { + pFlipHead[j++] = pFlipHeadOriginal[i]; + } } + nvAssert(j == numFlipHeads); - return pRequest; + return pFlipHead; } static void HsIoctlAssignSurfacesMaxEyes( @@ -324,7 +293,7 @@ } static NvBool HsIoctlFlipValidateOneHwState( - const NVFlipChannelEvoHwState *pHwState, + const NVHsLayerRequestedFlipState *pHwState, const NvU32 sd) { /* The semaphore surface must have a CPU mapping. */ @@ -343,74 +312,152 @@ } } - /* HeadSurface does not support timeStamp flips, yet. */ - - if (pHwState->timeStamp != 0) { - return FALSE; - } - return TRUE; } /*! - * Assign NVFlipEvoHwState. + * Assign NVHsRequestedFlipState. * - * Return TRUE if the NVFlipEvoHwState could be assigned and is valid for use by + * Return TRUE if the NVHsRequestedFlipState could be assigned and is valid for use by * headSurface. */ static NvBool HsIoctlFlipAssignHwStateOneHead( NVHsChannelEvoRec *pHsChannel, NVDevEvoPtr pDevEvo, const NvU32 sd, - const NvU32 head, + const NvU32 apiHead, const struct NvKmsPerOpenDev *pOpenDev, - const struct NvKmsFlipCommonParams *pRequestOneHead, - NVFlipEvoHwState *pFlipState) + const struct NvKmsFlipCommonParams *pParams, + NVHsRequestedFlipState *pFlipState) { + const NVEvoApiHandlesRec *pOpenDevSurfaceHandles = + nvGetSurfaceHandlesFromOpenDevConst(pOpenDev); NvU32 layer; - const struct NvKmsUsageBounds *pPossibleUsage = - &pDevEvo->gpus[sd].pDispEvo->headState[head].timings.viewPort.possibleUsage; nvAssert(pHsChannel != NULL); /* Init pFlipState using current pHsChannel state. */ - nvClearFlipEvoHwState(pFlipState); + nvkms_memset(pFlipState, 0, sizeof(*pFlipState)); pFlipState->cursor = pHsChannel->config.cursor; pFlipState->viewPortPointIn.x = pHsChannel->config.viewPortIn.x; pFlipState->viewPortPointIn.y = pHsChannel->config.viewPortIn.y; - for (layer = 0; layer < pDevEvo->head[head].numLayers; layer++) { + for (layer = 0; layer < pDevEvo->apiHead[apiHead].numLayers; layer++) { pFlipState->layer[layer] = *HsGetLastFlipQueueEntry(pHsChannel, layer); } - /* Apply pRequestOneHead to pFlipState. */ - - if (!nvUpdateFlipEvoHwState(pOpenDev, pDevEvo, sd, head, pRequestOneHead, - pFlipState, FALSE /* allowVrr */)) { + /* Apply pParams to pFlipState. */ + if (!nvCheckFlipPermissions(pOpenDev, pDevEvo, sd, apiHead, pParams)) { return FALSE; } - nvOverrideScalingUsageBounds(pDevEvo, head, pFlipState, pPossibleUsage); + if (pParams->viewPortIn.specified) { + pFlipState->dirty.viewPortPointIn = TRUE; + pFlipState->viewPortPointIn = pParams->viewPortIn.point; + } - /* Validate that the requested changes can be performed by headSurface. */ - for (layer = 0; layer < pDevEvo->head[head].numLayers; layer++) { - if (!pFlipState->dirty.layer[layer]) { - continue; + if (pParams->cursor.imageSpecified) { + if (!nvAssignCursorSurface(pOpenDev, pDevEvo, &pParams->cursor.image, + &pFlipState->cursor.pSurfaceEvo)) { + return FALSE; } - /* - * HeadSurface only supports client notifiers when running in - * swapgroup mode where each flip IOCTL will result in a real - * flip in HW. - */ - if (((pFlipState->layer[layer].completionNotifier.surface.pSurfaceEvo != NULL) || - pFlipState->layer[layer].completionNotifier.awaken) && - !pHsChannel->config.neededForSwapGroup) { + if (pFlipState->cursor.pSurfaceEvo != NULL) { + pFlipState->cursor.cursorCompParams = + pParams->cursor.image.cursorCompParams; + } + + pFlipState->dirty.cursorSurface = TRUE; + } + + if (pParams->cursor.positionSpecified) { + pFlipState->cursor.x = pParams->cursor.position.x; + pFlipState->cursor.y = pParams->cursor.position.y; + + pFlipState->dirty.cursorPosition = TRUE; + } + + for (layer = 0; layer < pDevEvo->apiHead[apiHead].numLayers; layer++) { + if (pParams->layer[layer].surface.specified) { + NvBool ret = + nvAssignSurfaceArray(pDevEvo, + pOpenDevSurfaceHandles, + pParams->layer[layer].surface.handle, + FALSE /* isUsedByCursorChannel */, + TRUE /* isUsedByLayerChannel */, + pFlipState->layer[layer].pSurfaceEvo); + if (!ret) { + return FALSE; + } + + pFlipState->dirty.layer[layer] = TRUE; + } + + if (pParams->layer[layer].syncObjects.specified) { + NvBool ret; + + if (pParams->layer[layer].syncObjects.val.useSyncpt) { + return FALSE; + } + + nvkms_memset(&pFlipState->layer[layer].syncObject, + 0, + sizeof(pFlipState->layer[layer].syncObject)); + + ret = nvAssignSemaphoreEvoHwState(pDevEvo, + pOpenDevSurfaceHandles, + layer, + sd, + &pParams->layer[layer].syncObjects.val, + &pFlipState->layer[layer].syncObject); + if (!ret) { + return FALSE; + } + + pFlipState->dirty.layer[layer] = TRUE; + } + + if (pParams->layer[layer].completionNotifier.specified && + (pParams->layer[layer].completionNotifier.val.surface.surfaceHandle != 0)) { + + /* + * HeadSurface only supports client notifiers when running in + * swapgroup mode where each flip IOCTL will result in a real + * flip in HW. + */ + if (!pHsChannel->config.neededForSwapGroup) { + return FALSE; + } + + NvBool ret = nvAssignCompletionNotifierEvoHwState( + pDevEvo, + pOpenDevSurfaceHandles, + &pParams->layer[layer].completionNotifier.val, + layer, + &pFlipState->layer[layer].completionNotifier); + if (!ret) { + return FALSE; + } + + pFlipState->dirty.layer[layer] = TRUE; + } + + /* HeadSurface does not support timeStamp flips, yet. */ + if (pParams->layer[layer].timeStamp != 0) { return FALSE; } + } + + /* XXX Reject all unhandled flip parameters */ + + /* Validate that the requested changes can be performed by headSurface. */ + for (layer = 0; layer < pDevEvo->apiHead[apiHead].numLayers; layer++) { + if (!pFlipState->dirty.layer[layer]) { + continue; + } if (!HsIoctlFlipValidateOneHwState(&pFlipState->layer[layer], sd)) { return FALSE; @@ -429,76 +476,86 @@ NvBool nvHsIoctlFlip( NVDevEvoPtr pDevEvo, const struct NvKmsPerOpenDev *pOpenDev, - const struct NvKmsFlipRequest *pRequest, + const struct NvKmsFlipRequestOneHead *pFlipHead, + NvU32 numFlipHeads, + NvBool commit, + NvBool allowVrr, struct NvKmsFlipReply *pReply) { - NvU32 head, sd; - NVDispEvoPtr pDispEvo; - NvU32 nHsHeads = 0; - NvU32 nNonHsHeads = 0; + NvU32 i; + ct_assert(NVKMS_MAX_HEADS_PER_DISP <= 8); + NvU8 hsMask[NVKMS_MAX_SUBDEVICES] = { }; + NvU8 nonHsMask[NVKMS_MAX_SUBDEVICES] = { }; + NvU32 nHsApiHeads = 0; + NvU32 nNonHsApiHeads = 0; NvBool ret = FALSE; struct { - NvU32 hsMask[NVKMS_MAX_SUBDEVICES]; - NvU32 nonHsMask[NVKMS_MAX_SUBDEVICES]; - NVFlipEvoHwState flipState + NVHsRequestedFlipState flipState [NVKMS_MAX_SUBDEVICES][NVKMS_MAX_HEADS_PER_DISP]; - } *pWorkArea = nvCalloc(1, sizeof(*pWorkArea)); - - if (pWorkArea == NULL) { - goto done; - } + } *pWorkArea = NULL; /* Take inventory of which heads are touched by the request. */ - FOR_ALL_EVO_DISPLAYS(pDispEvo, sd, pDevEvo) { + for (i = 0; i < numFlipHeads; i++) { + const NvU32 apiHead = pFlipHead[i].head; + const NvU32 sd = pFlipHead[i].sd; + NVDispEvoPtr pDispEvo = pDevEvo->pDispEvo[sd]; - if (!HsIoctlGetBitMasks(pDispEvo, - pRequest->sd[sd].requestedHeadsBitMask, - &pWorkArea->hsMask[sd], - &pWorkArea->nonHsMask[sd])) { - goto done; + if (pDispEvo->pHsChannel[apiHead] == NULL) { + nonHsMask[sd] |= NVBIT(apiHead); + nNonHsApiHeads++; + } else { + hsMask[sd] |= NVBIT(apiHead); + nHsApiHeads++; } - - nHsHeads += nvPopCount32(pWorkArea->hsMask[sd]); - nNonHsHeads += nvPopCount32(pWorkArea->nonHsMask[sd]); } + nvAssert(numFlipHeads == nNonHsApiHeads + nHsApiHeads); /* * Handle the common case: if there are no headSurface-ful heads touched by * the request, call down and return. */ - if (nHsHeads == 0) { + if (nHsApiHeads == 0) { ret = nvFlipEvo(pDevEvo, pOpenDev, - pRequest, + pFlipHead, numFlipHeads, commit, allowVrr, pReply, FALSE /* skipUpdate */, TRUE /* allowFlipLock */); goto done; } + pWorkArea = nvCalloc(1, sizeof(*pWorkArea)); + if (pWorkArea == NULL) { + goto done; + } + /* * Assign and validate flipState for any headSurface heads in the * request. */ - FOR_ALL_EVO_DISPLAYS(pDispEvo, sd, pDevEvo) { - FOR_EACH_INDEX_IN_MASK(32, head, pWorkArea->hsMask[sd]) { - const NvU32 apiHead = nvHardwareHeadToApiHead(head); - if (!HsIoctlFlipAssignHwStateOneHead( - pDispEvo->pHsChannel[apiHead], - pDevEvo, - sd, - head, - pOpenDev, - &pRequest->sd[sd].head[head], - &pWorkArea->flipState[sd][head])) { - goto done; - } + for (i = 0; i < numFlipHeads; i++) { + const NvU32 apiHead = pFlipHead[i].head; + const NvU32 sd = pFlipHead[i].sd; + NVDispEvoPtr pDispEvo = pDevEvo->pDispEvo[sd]; + + if ((hsMask[sd] & NVBIT(apiHead)) == 0) { + continue; + } - } FOR_EACH_INDEX_IN_MASK_END; + if (!HsIoctlFlipAssignHwStateOneHead( + pDispEvo->pHsChannel[apiHead], + pDevEvo, + sd, + apiHead, + pOpenDev, + &pFlipHead[i].flip, + &pWorkArea->flipState[sd][apiHead])) { + goto done; + } } /* @@ -507,25 +564,59 @@ * headSurface-ful heads removed and call down. */ - if (nNonHsHeads != 0) { + if (nNonHsApiHeads != 0) { NvBool tmp; - struct NvKmsFlipRequest *pRequestLocal = - HsIoctlRemoveHsHeadsFromNvKmsFlipRequest( - pDevEvo, pRequest, pWorkArea->hsMask); + struct NvKmsFlipRequestOneHead *pFlipHeadLocal = + HsIoctlRemoveHsHeadsFromNvKmsFlipHead( + pDevEvo, pFlipHead, numFlipHeads, nNonHsApiHeads, hsMask); - if (pRequestLocal == NULL) { + if (pFlipHeadLocal == NULL) { goto done; } tmp = nvFlipEvo(pDevEvo, pOpenDev, - pRequestLocal, + pFlipHeadLocal, nNonHsApiHeads, commit, allowVrr, pReply, FALSE /* skipUpdate */, TRUE /* allowFlipLock */); - nvFree(pRequestLocal); + // nvFlipEvo filled in pReply for the heads in pFlipHeadLocal. + // Move those replies to the right location for pFlipHead. + // + // Due to how HsIoctlRemoveHsHeadsFromNvKmsFlipHead() created + // pFlipHeadLocal, the entries will be in the same order as the + // original pFlipHead request, but some of the entries have been + // removed so the original array is longer. + // + // Iterate backwards through the local array (headLocal), which points + // to where the reply data was filled in by nvFlipEvo(). + // Keep an index into the original array (headOriginal) which points to + // the entry where the reply *should* be. This should always be >= + // headLocal. + // If the expected location for the reply is not the same as the local + // index, copy the reply to the right location and clear the local data + // (which was in the wrong place). + { + NvS32 headOriginal = numFlipHeads - 1; + NvS32 headLocal; + for (headLocal = nNonHsApiHeads - 1; headLocal >= 0; headLocal--) { + while (pFlipHead[headOriginal].sd != pFlipHeadLocal[headLocal].sd || + pFlipHead[headOriginal].head != pFlipHeadLocal[headLocal].head) { + headOriginal--; + nvAssert(headOriginal >= 0); + } + if (headOriginal != headLocal) { + nvAssert(headOriginal > headLocal); + pReply->flipHead[headOriginal] = pReply->flipHead[headLocal]; + nvkms_memset(&pReply->flipHead[headLocal], 0, + sizeof(pReply->flipHead[headLocal])); + } + } + } + + nvFree(pFlipHeadLocal); if (!tmp) { goto done; @@ -539,85 +630,95 @@ /* If this is a validation-only request, we are done. */ - if (!pRequest->commit) { + if (!commit) { goto done; } - FOR_ALL_EVO_DISPLAYS(pDispEvo, sd, pDevEvo) { - FOR_EACH_INDEX_IN_MASK(32, head, pWorkArea->hsMask[sd]) { - const NvU32 apiHead = nvHardwareHeadToApiHead(head); - NVHsChannelEvoRec *pHsChannel = pDispEvo->pHsChannel[apiHead]; - const struct NvKmsFlipCommonParams *pParams = - &pRequest->sd[sd].head[head]; - NVFlipEvoHwState *pFlipState = - &pWorkArea->flipState[sd][head]; + for (i = 0; i < numFlipHeads; i++) { + const NvU32 apiHead = pFlipHead[i].head; + const NvU32 sd = pFlipHead[i].sd; + NVDispEvoPtr pDispEvo = pDevEvo->pDispEvo[sd]; - if (!nvHeadIsActive(pDispEvo, head)) { - continue; - } + if ((hsMask[sd] & NVBIT(apiHead)) == 0) { + continue; + } - if (pParams->layer[NVKMS_MAIN_LAYER].skipPendingFlips && - pFlipState->dirty.layer[NVKMS_MAIN_LAYER]) { - nvHsIdleFlipQueue(pHsChannel, TRUE /* force */); - } - } FOR_EACH_INDEX_IN_MASK_END; + NVHsChannelEvoRec *pHsChannel = pDispEvo->pHsChannel[apiHead]; + const struct NvKmsFlipCommonParams *pParams = + &pFlipHead[i].flip; + NVHsRequestedFlipState *pFlipState = + &pWorkArea->flipState[sd][apiHead]; + + if (!nvApiHeadIsActive(pDispEvo, apiHead)) { + continue; + } + + if (pParams->layer[NVKMS_MAIN_LAYER].skipPendingFlips && + pFlipState->dirty.layer[NVKMS_MAIN_LAYER]) { + nvHsIdleFlipQueue(pHsChannel, TRUE /* force */); + } } /* Finally, update the headSurface-ful heads in the request. */ - FOR_ALL_EVO_DISPLAYS(pDispEvo, sd, pDevEvo) { - FOR_EACH_INDEX_IN_MASK(32, head, pWorkArea->hsMask[sd]) { - const NvU32 apiHead = nvHardwareHeadToApiHead(head); - const NVFlipEvoHwState *pFlipState = - &pWorkArea->flipState[sd][head]; + for (i = 0; i < numFlipHeads; i++) { + const NvU32 apiHead = pFlipHead[i].head; + const NvU32 sd = pFlipHead[i].sd; + NVDispEvoPtr pDispEvo = pDevEvo->pDispEvo[sd]; - NVHsChannelEvoRec *pHsChannel = pDispEvo->pHsChannel[apiHead]; - NvU32 layer; + if ((hsMask[sd] & NVBIT(apiHead)) == 0) { + continue; + } - nvAssert(pHsChannel != NULL); + const NVHsRequestedFlipState *pFlipState = + &pWorkArea->flipState[sd][apiHead]; - if (pFlipState->dirty.cursorPosition) { - HsIoctlMoveCursor( - pHsChannel, - pFlipState->cursor.x, - pFlipState->cursor.y); - } + NVHsChannelEvoRec *pHsChannel = pDispEvo->pHsChannel[apiHead]; + NvU32 layer; - if (pFlipState->dirty.cursorSurface) { - HsIoctlSetCursorImage( - pHsChannel, - pFlipState->cursor.pSurfaceEvo); - } + nvAssert(pHsChannel != NULL); - if (pFlipState->dirty.viewPortPointIn) { - HsIoctlPan(pHsChannel, &pFlipState->viewPortPointIn); - } + if (pFlipState->dirty.cursorPosition) { + HsIoctlMoveCursor( + pHsChannel, + pFlipState->cursor.x, + pFlipState->cursor.y); + } - /* - * XXX NVKMS HEADSURFACE TODO: Layers that are specified as part - * of the same NVKMS_IOCTL_FLIP request should be flipped - * atomically. But, layers that are specified separately should - * be allowed to flip separately. Update the headSurface flip - * queue handling to coordinate multi-layer atomic flips. - */ - for (layer = 0; layer < pDevEvo->head[head].numLayers; layer++) { - if (!pFlipState->dirty.layer[layer]) { - continue; - } + if (pFlipState->dirty.cursorSurface) { + HsIoctlSetCursorImage( + pHsChannel, + pFlipState->cursor.pSurfaceEvo); + } - if (layer == NVKMS_MAIN_LAYER) { - HsIoctlAssignSurfacesMaxEyes( - pHsChannel->flipQueueMainLayerState.pSurfaceEvo, - pFlipState->layer[layer].pSurfaceEvo); - } + if (pFlipState->dirty.viewPortPointIn) { + HsIoctlPan(pHsChannel, &pFlipState->viewPortPointIn); + } + + /* + * XXX NVKMS HEADSURFACE TODO: Layers that are specified as part + * of the same NVKMS_IOCTL_FLIP request should be flipped + * atomically. But, layers that are specified separately should + * be allowed to flip separately. Update the headSurface flip + * queue handling to coordinate multi-layer atomic flips. + */ + for (layer = 0; layer < pDevEvo->apiHead[apiHead].numLayers; layer++) { + if (!pFlipState->dirty.layer[layer]) { + continue; + } - nvHsPushFlipQueueEntry(pHsChannel, layer, &pFlipState->layer[layer]); + if (layer == NVKMS_MAIN_LAYER) { + HsIoctlAssignSurfacesMaxEyes( + pHsChannel->flipQueueMainLayerState.pSurfaceEvo, + pFlipState->layer[layer].pSurfaceEvo); + } - if (pHsChannel->config.neededForSwapGroup) { - pHsChannel->swapGroupFlipping = NV_TRUE; - } + nvHsPushFlipQueueEntry(pHsChannel, layer, &pFlipState->layer[layer]); + + if (pHsChannel->config.neededForSwapGroup) { + pHsChannel->swapGroupFlipping = NV_TRUE; } - } FOR_EACH_INDEX_IN_MASK_END; + } } done: diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia-modeset/src/nvkms-headsurface-swapgroup.c nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia-modeset/src/nvkms-headsurface-swapgroup.c --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia-modeset/src/nvkms-headsurface-swapgroup.c 2023-10-25 20:22:40.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia-modeset/src/nvkms-headsurface-swapgroup.c 2024-03-05 22:12:22.000000000 +0000 @@ -414,7 +414,7 @@ const NVDevEvoRec *pDevEvo, const struct NvKmsSwapGroupConfig *pConfig) { - const NvU32 validHeadMask = NVBIT(pDevEvo->numHeads) - 1; + const NvU32 validHeadMask = NVBIT(pDevEvo->numApiHeads) - 1; NvU32 dispIndex; for (dispIndex = 0; dispIndex < ARRAY_LEN(pConfig->disp); dispIndex++) { @@ -460,9 +460,8 @@ /* Are there heads requested that already belong to another SwapGroup? */ FOR_ALL_EVO_DISPLAYS(pDispEvo, dispIndex, pDevEvo) { - NvU32 head; - FOR_ALL_HEADS(head, pRequest->config.disp[dispIndex].headMask) { - const NvU32 apiHead = nvHardwareHeadToApiHead(head); + NvU32 apiHead; + FOR_ALL_HEADS(apiHead, pRequest->config.disp[dispIndex].headMask) { if (pDispEvo->pSwapGroup[apiHead] != NULL) { return NULL; } @@ -483,9 +482,8 @@ nvListInit(&pSwapGroup->deferredRequestFifoList); FOR_ALL_EVO_DISPLAYS(pDispEvo, dispIndex, pDevEvo) { - NvU32 head; - FOR_ALL_HEADS(head, pRequest->config.disp[dispIndex].headMask) { - const NvU32 apiHead = nvHardwareHeadToApiHead(head); + NvU32 apiHead; + FOR_ALL_HEADS(apiHead, pRequest->config.disp[dispIndex].headMask) { pDispEvo->pSwapGroup[apiHead] = pSwapGroup; } } diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia-modeset/src/nvkms-headsurface.c nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia-modeset/src/nvkms-headsurface.c --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia-modeset/src/nvkms-headsurface.c 2023-10-25 20:22:40.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia-modeset/src/nvkms-headsurface.c 2024-03-05 22:12:22.000000000 +0000 @@ -475,7 +475,7 @@ } /*! - * Read the payload of the semaphore described in the pHwState. + * Read the payload of the semaphore described in the pSemaSurface. */ static NvU32 HsFlipQueueReadSemaphore( const NVHsChannelEvoRec *pHsChannel, @@ -503,16 +503,16 @@ } /*! - * Return whether the specified pHwState is ready to flip. + * Return whether the specified pFlipState is ready to flip. */ static NvBool HsFlipQueueEntryIsReady( const NVHsChannelEvoRec *pHsChannel, - const NVFlipChannelEvoHwState *pHwState) + const NVHsLayerRequestedFlipState *pFlipState) { const NVFlipNIsoSurfaceEvoHwState *pSemaSurface = - &pHwState->syncObject.u.semaphores.acquireSurface; + &pFlipState->syncObject.u.semaphores.acquireSurface; - if (pHwState->syncObject.usingSyncpt) { + if (pFlipState->syncObject.usingSyncpt) { return TRUE; } @@ -527,9 +527,9 @@ if (pHsChannel->swapGroupFlipping) { // With swap group flipping, the client semaphore should be // written before the non-stall interrupt kicking off the flip. - nvAssert(semaphoreValue == pHwState->syncObject.u.semaphores.acquireValue); + nvAssert(semaphoreValue == pFlipState->syncObject.u.semaphores.acquireValue); } else { - if (semaphoreValue != pHwState->syncObject.u.semaphores.acquireValue) { + if (semaphoreValue != pFlipState->syncObject.u.semaphores.acquireValue) { return FALSE; } } @@ -546,44 +546,41 @@ } /*! - * Update the reference count of all the surfaces described in the pHwState. + * Update the reference count of all the surfaces described in the pFlipState. */ static void HsUpdateFlipQueueEntrySurfaceRefCount( NVDevEvoPtr pDevEvo, - const NVFlipChannelEvoHwState *pHwState, + const NVHsLayerRequestedFlipState *pFlipState, NvBool increase) { HsChangeSurfaceFlipRefCount( - pDevEvo, pHwState->pSurfaceEvo[NVKMS_LEFT], increase); + pDevEvo, pFlipState->pSurfaceEvo[NVKMS_LEFT], increase); HsChangeSurfaceFlipRefCount( - pDevEvo, pHwState->pSurfaceEvo[NVKMS_RIGHT], increase); + pDevEvo, pFlipState->pSurfaceEvo[NVKMS_RIGHT], increase); - HsChangeSurfaceFlipRefCount( - pDevEvo, pHwState->completionNotifier.surface.pSurfaceEvo, increase); - - if (!pHwState->syncObject.usingSyncpt) { + if (!pFlipState->syncObject.usingSyncpt) { HsChangeSurfaceFlipRefCount( - pDevEvo, pHwState->syncObject.u.semaphores.acquireSurface.pSurfaceEvo, increase); + pDevEvo, pFlipState->syncObject.u.semaphores.acquireSurface.pSurfaceEvo, increase); HsChangeSurfaceFlipRefCount( - pDevEvo, pHwState->syncObject.u.semaphores.releaseSurface.pSurfaceEvo, increase); + pDevEvo, pFlipState->syncObject.u.semaphores.releaseSurface.pSurfaceEvo, increase); } } /*! - * Update bookkeeping for "flipping away" from a pHwState. + * Update bookkeeping for "flipping away" from a pFlipState. */ static void HsReleaseFlipQueueEntry( NVDevEvoPtr pDevEvo, NVHsChannelEvoPtr pHsChannel, - const NVFlipChannelEvoHwState *pHwState) + const NVHsLayerRequestedFlipState *pFlipState) { /* * If a semaphore surface was specified, we can now write its release value. */ - if (!pHwState->syncObject.usingSyncpt && - pHwState->syncObject.u.semaphores.releaseSurface.pSurfaceEvo != NULL) { + if (!pFlipState->syncObject.usingSyncpt && + pFlipState->syncObject.u.semaphores.releaseSurface.pSurfaceEvo != NULL) { /* * XXX NVKMS HEADSURFACE TODO: write the timestamp in the EVO/NVDisplay @@ -595,18 +592,18 @@ */ nvHs3dReleaseSemaphore(pHsChannel, - pHwState->syncObject.u.semaphores.releaseSurface.pSurfaceEvo, - pHwState->syncObject.u.semaphores.releaseSurface.format, - pHwState->syncObject.u.semaphores.releaseSurface.offsetInWords, - pHwState->syncObject.u.semaphores.releaseValue, + pFlipState->syncObject.u.semaphores.releaseSurface.pSurfaceEvo, + pFlipState->syncObject.u.semaphores.releaseSurface.format, + pFlipState->syncObject.u.semaphores.releaseSurface.offsetInWords, + pFlipState->syncObject.u.semaphores.releaseValue, TRUE /* allPreceedingReads */); } /* - * HeadSurface no longer needs to read from the surfaces in pHwState; + * HeadSurface no longer needs to read from the surfaces in pFlipState; * decrement their reference counts. */ - HsUpdateFlipQueueEntrySurfaceRefCount(pDevEvo, pHwState, FALSE); + HsUpdateFlipQueueEntrySurfaceRefCount(pDevEvo, pFlipState, FALSE); } /*! @@ -681,12 +678,12 @@ * * \param[in,out] pHsChannel The headSurface channel. * \param[in] layer The layer of the flip queue. - * \param[in] pHwState The hwState to be pushed on the flip queue. + * \param[in] pFlipState The hwState to be pushed on the flip queue. */ void nvHsPushFlipQueueEntry( NVHsChannelEvoPtr pHsChannel, const NvU8 layer, - const NVFlipChannelEvoHwState *pHwState) + const NVHsLayerRequestedFlipState *pFlipState) { NVDevEvoPtr pDevEvo = pHsChannel->pDispEvo->pDevEvo; NVListRec *pFlipQueue = &pHsChannel->flipQueue[layer].queue; @@ -701,7 +698,7 @@ return; } - pEntry->hwState = *pHwState; + pEntry->hwState = *pFlipState; /* Increment the ref counts on the surfaces in the flip queue entry. */ @@ -722,26 +719,26 @@ * Remove the first entry in the flip queue and return it. * * If the first entry in the flipQueue is ready to be consumed by headSurface, - * remove it from the list and return it in the 'pHwState' argument. + * remove it from the list and return it in the 'pFlipState' argument. * * If this function returns TRUE, it is the caller's responsibility to * eventually call * - * HsUpdateFlipQueueEntrySurfaceRefCount(pHwState, FALSE) + * HsUpdateFlipQueueEntrySurfaceRefCount(pDevEvo, pFlipState, FALSE) * - * for the returned pHwState. + * for the returned pFlipState. * * \param[in,out] pHsChannel The headSurface channel. * \param[in] layer The layer of the flip queue. - * \param[out] pHwState The hwState that was popped off the flip queue. + * \param[out] pFlipState The hwState that was popped off the flip queue. * * \return Return TRUE if a flip queue entry was popped off the queue and - * copied into pHwState. + * copied into pFlipState. */ static NvBool HsPopFlipQueueEntry( NVHsChannelEvoPtr pHsChannel, const NvU8 layer, - NVFlipChannelEvoHwState *pHwState) + NVHsLayerRequestedFlipState *pFlipState) { NVListRec *pFlipQueue = &pHsChannel->flipQueue[layer].queue; NVHsChannelFlipQueueEntry *pEntry; @@ -758,7 +755,7 @@ return FALSE; } - *pHwState = pEntry->hwState; + *pFlipState = pEntry->hwState; nvListDel(&pEntry->flipQueueEntry); nvFree(pEntry); @@ -781,7 +778,7 @@ for (layer = 0; layer < ARRAY_LEN(pHsChannel->flipQueue); layer++) { - NVFlipChannelEvoHwState newCurrent = { }; + NVHsLayerRequestedFlipState newCurrent = { }; /* * XXX NVKMS HEADSURFACE TODO: fast forward to the last ready flip queue @@ -1206,8 +1203,6 @@ const NvBool allowFlipLock) { NVDevEvoRec *pDevEvo = pHsDevice->pDevEvo; - struct NvKmsFlipRequest *pRequest; - struct NvKmsFlipParams *pFlipParams; struct NvKmsFlipCommonParams *pParamsOneHead; NVHsNotifiersRec *pHsNotifiers = &pHsDevice->notifiers; const NvU32 sd = pHsChannel->pDispEvo->displayOwner; @@ -1215,18 +1210,16 @@ NvBool ret; /* - * Use a preallocated NvKmsFlipParams, so that we don't have to allocate + * Use preallocated memory, so that we don't have to allocate * memory here (and deal with allocation failure). */ - pFlipParams = &pHsChannel->scratchParams; - - nvkms_memset(pFlipParams, 0, sizeof(*pFlipParams)); + struct NvKmsFlipRequestOneHead *pFlipHead = &pHsChannel->scratchParams; - pRequest = &pFlipParams->request; + nvkms_memset(pFlipHead, 0, sizeof(*pFlipHead)); - pParamsOneHead = &pRequest->sd[sd].head[apiHead]; - - pRequest->commit = NV_TRUE; + pFlipHead->sd = sd; + pFlipHead->head = apiHead; + pParamsOneHead = &pFlipHead->flip; if (isFirstFlip) { /* @@ -1266,8 +1259,6 @@ pParamsOneHead->layer[NVKMS_MAIN_LAYER].completionNotifier.specified = TRUE; - pRequest->sd[sd].requestedHeadsBitMask = NVBIT(apiHead); - if (surfaceHandles[NVKMS_LEFT] != 0) { NVEvoApiHandlesRec *pOpenDevSurfaceHandles = nvGetSurfaceHandlesFromOpenDev(pDevEvo->pNvKmsOpenDev); @@ -1311,8 +1302,11 @@ ret = nvFlipEvo(pDevEvo, pDevEvo->pNvKmsOpenDev, - pRequest, - &pFlipParams->reply, + pFlipHead, + 1 /* numFlipHeads */, + TRUE /* commit */, + FALSE /* allowVrr */, + NULL /* pReply */, FALSE /* skipUpdate */, allowFlipLock); @@ -1820,11 +1814,9 @@ */ static void HsProcFsRecordScanline( const NVDispEvoRec *pDispEvo, - const NvU32 head) + const NvU32 apiHead) { #if NVKMS_PROCFS_ENABLE - const NvU32 apiHead = nvHardwareHeadToApiHead(head); - const NVDevEvoRec *pDevEvo = pDispEvo->pDevEvo; NVHsChannelEvoRec *pHsChannel = pDispEvo->pHsChannel[apiHead]; NvU16 scanLine = 0; NvBool inBlankingPeriod = FALSE; @@ -1833,7 +1825,7 @@ return; } - pDevEvo->hal->GetScanLine(pDispEvo, head, &scanLine, &inBlankingPeriod); + nvApiHeadGetScanLine(pDispEvo, apiHead, &scanLine, &inBlankingPeriod); if (inBlankingPeriod) { pHsChannel->statistics.scanLine.nInBlankingPeriod++; @@ -2137,11 +2129,12 @@ /*! * Receive RG line 1 callback, in process context with nvkms_lock held. */ -static void HsServiceRGLineInterrupt(void *dataPtr, NvU32 dataU32) +static void HsRgLine1CallbackProc(NVDispEvoRec *pDispEvo, + const NvU32 head, + NVRgLine1CallbackPtr pCallback) { - NVDispEvoRec *pDispEvo = (NVDispEvoRec *)dataPtr; - NvU32 head = dataU32; - const NvU32 apiHead = nvHardwareHeadToApiHead(head); + const NvU32 apiHead = + (NvU32)(NvUPtr)pCallback->pUserData; NVHsChannelEvoPtr pHsChannel = pDispEvo->pHsChannel[apiHead]; /* @@ -2169,7 +2162,7 @@ * flip to the render offset. */ NvU32 activeViewportOffset = - pDispEvo->pDevEvo->hal->GetActiveViewportOffset(pDispEvo, head); + nvApiHeadGetActiveViewportOffset(pDispEvo, apiHead); nvAssert((activeViewportOffset == 0) || (activeViewportOffset == pHsChannel->config.frameSize.height)); @@ -2191,7 +2184,7 @@ } else { NVHsDeviceEvoRec *pHsDevice = pDispEvo->pDevEvo->pHsDevice; - HsProcFsRecordScanline(pDispEvo, head); + HsProcFsRecordScanline(pDispEvo, apiHead); if (HsCanOmitNonSgHsUpdate(pHsChannel)) { HsProcFsRecordOmittedNonSgHsUpdate(pHsChannel); @@ -2216,10 +2209,9 @@ * */ static void HsVBlankCallback(NVDispEvoRec *pDispEvo, - const NvU32 head, NVVBlankCallbackPtr pCallbackData) { - const NvU32 apiHead = nvHardwareHeadToApiHead(head); + const NvU32 apiHead = pCallbackData->apiHead; NVHsChannelEvoPtr pHsChannel = pDispEvo->pHsChannel[apiHead]; NVHsDeviceEvoRec *pHsDevice = pDispEvo->pDevEvo->pHsDevice; @@ -2251,7 +2243,7 @@ return; } - HsProcFsRecordScanline(pDispEvo, head); + HsProcFsRecordScanline(pDispEvo, apiHead); /* * XXX NVKMS HEADSURFACE TODO: evaluate whether there has been @@ -2277,29 +2269,6 @@ } /*! - * Receive RG line 1 interrupt notification from resman. - * - * This function is registered as the kernel callback function from resman when - * the RG line 1 interrupt is generated. - * - * This function is called within resman's context, so we schedule a zero timer - * callback to process the swapgroup check and release without holding the - * resman lock. - */ -static void HsRGLineInterruptCallback(NvU32 rgIntrLine, void *param1, - NvBool bIsIrqlIsr /* unused */) -{ - void *pDispEvoRefPtr = (void *)((NvUPtr)param1 & - ~(NVKMS_MAX_HEADS_PER_DISP-1)); - NvU32 head = (NvUPtr)param1 & (NVKMS_MAX_HEADS_PER_DISP-1); - (void) nvkms_alloc_timer_with_ref_ptr( - HsServiceRGLineInterrupt, /* callback */ - pDispEvoRefPtr, /* ref_ptr */ - head, /* dataU32 */ - 0); /* usec */ -} - -/*! * Schedule vblank callbacks from resman on a specific head and subdevice. */ void nvHsAddVBlankCallback(NVHsChannelEvoPtr pHsChannel) @@ -2325,7 +2294,7 @@ */ void nvHsAddRgLine1Callback(NVHsChannelEvoPtr pHsChannel) { - const NVDispEvoRec *pDispEvo = pHsChannel->pDispEvo; + NVDispEvoRec *pDispEvo = pHsChannel->pDispEvo; NvBool found; NvU32 val; @@ -2341,12 +2310,13 @@ return; } - pHsChannel->rgIntrCallbackObjectHandle = + pHsChannel->pRgIntrCallback = nvApiHeadAddRgLine1Callback(pDispEvo, pHsChannel->apiHead, - HsRGLineInterruptCallback); + HsRgLine1CallbackProc, + (void*)(NvUPtr)pHsChannel->apiHead); - if (pHsChannel->rgIntrCallbackObjectHandle == 0) { + if (pHsChannel->pRgIntrCallback == NULL) { nvAssert(!"Failed to register headSurface RG line 1 interrupt"); } else { pHsChannel->usingRgIntrForSwapGroups = TRUE; @@ -2365,8 +2335,8 @@ if (pHsChannel->usingRgIntrForSwapGroups) { nvRmRemoveRgLine1Callback(pDispEvo, - pHsChannel->rgIntrCallbackObjectHandle); - pHsChannel->rgIntrCallbackObjectHandle = 0; + pHsChannel->pRgIntrCallback); + pHsChannel->pRgIntrCallback = NULL; } } @@ -2388,7 +2358,6 @@ NVDispEvoRec *pDispEvo = pHsChannel->pDispEvo; nvApiHeadUnregisterVBlankCallback(pDispEvo, - pHsChannel->apiHead, pHsChannel->vBlankCallback); pHsChannel->vBlankCallback = NULL; } @@ -2646,7 +2615,7 @@ static void HsProcFsFlipQueueOneEntry( NVEvoInfoStringRec *pInfoString, - const NVFlipChannelEvoHwState *pFlipState) + const NVHsLayerRequestedFlipState *pFlipState) { /* * Print the pointers by casting to NvUPtr and formatting with NvUPtr_fmtx, @@ -2847,24 +2816,23 @@ NVEvoInfoStringRec *pInfoString, NVDevEvoRec *pDevEvo, NvU32 dispIndex, - NvU32 head) + NvU32 apiHead) { NVDispEvoPtr pDispEvo = pDevEvo->pDispEvo[dispIndex]; - const NvU32 apiHead = nvHardwareHeadToApiHead(head); const NVHsChannelEvoRec *pHsChannel = pDispEvo->pHsChannel[apiHead]; const NVHsStateOneHeadAllDisps *pHsOneHeadAllDisps = &pDevEvo->apiHeadSurfaceAllDisps[apiHead]; if (pHsChannel == NULL) { nvEvoLogInfoString(pInfoString, - " headSurface[head:%02d] : disabled", head); + " headSurface[head:%02d] : disabled", apiHead); return; } nvEvoLogInfoString(pInfoString, " headSurface[head:%02d] : " "enabled (needed for: %s)", - head, HsProcFsGetNeededForString(pHsChannel)); + apiHead, HsProcFsGetNeededForString(pHsChannel)); HsProcFsFrameStatistics(pInfoString, pHsChannel); diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia-modeset/src/nvkms-hw-flip.c nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia-modeset/src/nvkms-hw-flip.c --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia-modeset/src/nvkms-hw-flip.c 1970-01-01 00:00:00.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia-modeset/src/nvkms-hw-flip.c 2024-03-05 22:12:22.000000000 +0000 @@ -0,0 +1,2884 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2014 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#include "nvkms-dma.h" +#include "nvkms-evo.h" +#include "nvkms-hw-flip.h" +#include "nvkms-utils-flip.h" +#include "nvkms-flip-workarea.h" +#include "nvkms-surface.h" +#include "nvkms-prealloc.h" +#include "nvkms-private.h" +#include "nvkms-rm.h" +#include "nvkms-vrr.h" +#include "nvkms-cursor.h" +#include "nvkms-types.h" +#include "nvkms-dpy.h" +#include "nvkms-lut.h" +#include "nvkms-softfloat.h" + +#include "nvkms-sync.h" + +#include "nvkms-difr.h" + +static void SchedulePostFlipIMPTimer(NVDevEvoPtr pDevEvo); + +// The EVO .mfs file defines the maximum minPresentInterval to be 8. +#define NV_MAX_SWAP_INTERVAL 8 + +static NvBool AssignPreSyncptEvoHwState( + const NVDevEvoRec *pDevEvo, + const struct NvKmsChannelSyncObjects *pChannelSyncObjects, + NVFlipSyncObjectEvoHwState *pFlipSyncObject) +{ + NvBool ret; + NvU32 id = 0; + NvU32 value; + enum NvKmsSyncptType preType; + + nvAssert(pChannelSyncObjects->useSyncpt); + + preType = pChannelSyncObjects->u.syncpts.pre.type; + + if (preType == NVKMS_SYNCPT_TYPE_NONE) { + return TRUE; + } + + if (preType == NVKMS_SYNCPT_TYPE_FD) { + /*! Get id from fd using nvhost API */ + NvKmsSyncPtOpParams params = { }; + params.fd_to_id_and_thresh.fd = + pChannelSyncObjects->u.syncpts.pre.u.fd; + ret = nvkms_syncpt_op(NVKMS_SYNCPT_OP_FD_TO_ID_AND_THRESH, + ¶ms); + if (!ret) { + return FALSE; + } + id = params.fd_to_id_and_thresh.id; + value = params.fd_to_id_and_thresh.thresh; + } else { + id = pChannelSyncObjects->u.syncpts.pre.u.raw.id; + value = pChannelSyncObjects->u.syncpts.pre.u.raw.value; + } + if (id >= NV_SYNCPT_GLOBAL_TABLE_LENGTH) { + return FALSE; + } + /*! Fill pre-syncpt related information in hardware state */ + pFlipSyncObject->u.syncpts.preSyncpt = id; + pFlipSyncObject->u.syncpts.preValue = value; + pFlipSyncObject->u.syncpts.isPreSyncptSpecified = TRUE; + pFlipSyncObject->usingSyncpt = TRUE; + + return TRUE; +} + +static NvBool AssignPostSyncptEvoHwState( + const NVDevEvoRec *pDevEvo, + NVEvoChannel *pChannel, + const struct NvKmsChannelSyncObjects *pChannelSyncObjects, + NVFlipSyncObjectEvoHwState *pFlipSyncObject) +{ + enum NvKmsSyncptType postType; + NvU32 threshold; + + nvAssert(pChannelSyncObjects->useSyncpt); + + postType = pChannelSyncObjects->u.syncpts.requestedPostType; + + /*! + * It is possible that syncpt is mentioned but post-syncpt + * is not specified (case where only pre-syncpt used) + */ + if (postType == NVKMS_SYNCPT_TYPE_NONE) { + return TRUE; + } + + /*! return threshold to caller but increase only when programming hw */ + threshold = pChannel->postSyncpt.syncptMaxVal + 1; + + /*! each channel associated with one post-syncpt */ + pFlipSyncObject->u.syncpts.postCtxDma = pChannel->postSyncpt.hCtxDma; + pFlipSyncObject->u.syncpts.postValue = threshold; + + pFlipSyncObject->usingSyncpt = TRUE; + + return TRUE; +} + +void nvFillPostSyncptReplyOneChannel( + NVEvoChannel *pChannel, + enum NvKmsSyncptType postType, + struct NvKmsSyncpt *postSyncpt, + const NVFlipSyncObjectEvoHwState *pHwSyncObject) +{ + if (postType == NVKMS_SYNCPT_TYPE_RAW) { + postSyncpt->u.raw.id = pChannel->postSyncpt.id; + postSyncpt->u.raw.value = pHwSyncObject->u.syncpts.postValue; + postSyncpt->type = NVKMS_SYNCPT_TYPE_RAW; + } else if (postType == NVKMS_SYNCPT_TYPE_FD) { + NvBool ret = TRUE; + NvKmsSyncPtOpParams params = { }; + params.id_and_thresh_to_fd.id = pChannel->postSyncpt.id; + params.id_and_thresh_to_fd.thresh = + pHwSyncObject->u.syncpts.postValue; + + ret = nvkms_syncpt_op(NVKMS_SYNCPT_OP_ID_AND_THRESH_TO_FD, ¶ms); + if (!ret) { + nvAssert(!"Failed syncpt op ID_AND_THRESH_TO_FD"); + return; + } + postSyncpt->u.fd = params.id_and_thresh_to_fd.fd; + postSyncpt->type = NVKMS_SYNCPT_TYPE_FD; + } +} + +static NvBool GetPreSyncptCtxDma(NVDevEvoRec *pDevEvo, + NVEvoChannel *pChannel, const NvU32 id) +{ + NvU32 hSyncptCtxDma, hSyncpt; + + /*! use id value to check the global table */ + if (pDevEvo->preSyncptTable[id].hCtxDma == 0) { + /*! Register - allocate and bind ctxdma to syncpt*/ + if (!nvRmEvoAllocAndBindSyncpt(pDevEvo, + pChannel, + id, + &hSyncpt, + &hSyncptCtxDma)) { + nvAssert(!"Failed to register pre-syncpt"); + return FALSE; + } + + /*! Fill the Entry in Global Table */ + pDevEvo->preSyncptTable[id].hCtxDma = hSyncptCtxDma; + pDevEvo->preSyncptTable[id].hSyncpt = hSyncpt; + pDevEvo->preSyncptTable[id].channelMask |= pChannel->channelMask; + pDevEvo->preSyncptTable[id].id = id; + } else { + /*! + * syncpt found, just bind the context dma of this syncpt + * to the window if it is not already. + */ + if ((pDevEvo->preSyncptTable[id].channelMask & + pChannel->channelMask) == 0) { + + NvU32 ret = + nvRmEvoBindDispContextDMA(pDevEvo, + pChannel, + pDevEvo->preSyncptTable[id].hCtxDma); + if (ret != NVOS_STATUS_SUCCESS) { + nvAssert(!"Failed to bind pre-syncpt with ctxdma"); + } + pDevEvo->preSyncptTable[id].channelMask |= pChannel->channelMask; + /*! hSyncpt already allocated for id*/ + } + } + + return TRUE; +} + +static NvBool RegisterPreSyncpt(NVDevEvoRec *pDevEvo, + struct NvKmsFlipWorkArea *pWorkArea) +{ + NvU32 sd; + NvU32 ret = TRUE; + const NVDispEvoRec *pDispEvo; + + pDevEvo->pAllSyncptUsedInCurrentFlip = + nvCalloc(1, sizeof(NvBool) * NV_SYNCPT_GLOBAL_TABLE_LENGTH); + if (pDevEvo->pAllSyncptUsedInCurrentFlip == NULL) { + ret = FALSE; + goto done; + } + + FOR_ALL_EVO_DISPLAYS(pDispEvo, sd, pDevEvo) { + NvU32 head; + for (head = 0; head < ARRAY_LEN(pWorkArea->sd[sd].head); head++) { + NVFlipEvoHwState *pFlipState = + &pWorkArea->sd[sd].head[head].newState; + NvU32 layer; + + for (layer = 0; layer < ARRAY_LEN(pFlipState->layer); layer++) { + NVFlipSyncObjectEvoHwState *pFlipSyncObject = + &pFlipState->layer[layer].syncObject; + NvU32 preSyncpt = pFlipSyncObject->u.syncpts.preSyncpt; + + if (!pFlipState->dirty.layerSyncObjects[layer] || + !pFlipSyncObject->usingSyncpt || + !pFlipSyncObject->u.syncpts.isPreSyncptSpecified) { + continue; + } + + if (!GetPreSyncptCtxDma(pDevEvo, + pDevEvo->head[head].layer[layer], + preSyncpt)) { + ret = FALSE; + goto done; + } + + pDevEvo->pAllSyncptUsedInCurrentFlip[preSyncpt] = NV_TRUE; + } + } + } + +done: + nvFree(pDevEvo->pAllSyncptUsedInCurrentFlip); + pDevEvo->pAllSyncptUsedInCurrentFlip = NULL; + + return ret; +} + +void nvClearFlipEvoHwState( + NVFlipEvoHwState *pFlipState) +{ + NvU32 i; + + nvkms_memset(pFlipState, 0, sizeof(*pFlipState)); + + for (i = 0; i < ARRAY_LEN(pFlipState->layer); i++) { + pFlipState->layer[i].cscMatrix = NVKMS_IDENTITY_CSC_MATRIX; + } +} + +/*! + * Initialize NVFlipEvoHwState with a current snapshot from headState. + */ +void nvInitFlipEvoHwState( + const NVDevEvoRec *pDevEvo, + const NvU32 sd, + const NvU32 head, + NVFlipEvoHwState *pFlipState) +{ + NVDispEvoRec *pDispEvo = pDevEvo->gpus[sd].pDispEvo; + const NVEvoSubDevHeadStateRec *pSdHeadState; + NvU32 i; + + nvClearFlipEvoHwState(pFlipState); + + if (!nvHeadIsActive(pDispEvo, head)) { + return; + } + + pSdHeadState = &pDevEvo->gpus[sd].headState[head]; + + pFlipState->viewPortPointIn = pSdHeadState->viewPortPointIn; + pFlipState->cursor = pSdHeadState->cursor; + + ct_assert(ARRAY_LEN(pFlipState->layer) == ARRAY_LEN(pSdHeadState->layer)); + + for (i = 0; i < ARRAY_LEN(pFlipState->layer); i++) { + pFlipState->layer[i] = pSdHeadState->layer[i]; + } + + // pFlipState->usage describes the usage bounds that will be necessary after + // this flip is complete. Initialize it using pSdHeadState->targetUsage, + // which describes the usage bounds that will be required just before this + // flip occurs, rather than pSdHeadState->usage, which describes the usage + // bounds currently programmed into the hardware. + // + // pSdHeadState->usage may have higher bounds than pSdHeadState->targetUsage + // if TryLoweringUsageBounds has not yet noticed that a satellite channel is + // no longer in use, or a flip to NULL in a satellite channel is pending but + // has not yet occurred. + pFlipState->usage = pSdHeadState->targetUsage; + + pFlipState->disableMidFrameAndDWCFWatermark = + pSdHeadState->targetDisableMidFrameAndDWCFWatermark; +} + + +NvBool nvIsLayerDirty(const struct NvKmsFlipCommonParams *pParams, + const NvU32 layer) +{ + return pParams->layer[layer].surface.specified || + pParams->layer[layer].sizeIn.specified || + pParams->layer[layer].sizeOut.specified || + pParams->layer[layer].outputPosition.specified || + pParams->layer[layer].completionNotifier.specified || + pParams->layer[layer].syncObjects.specified || + pParams->layer[layer].compositionParams.specified || + pParams->layer[layer].csc.specified || + pParams->layer[layer].hdr.specified || + pParams->layer[layer].colorspace.specified; +} + +/*! + * Determine whether a base channel flip requires a non-tearing present mode. + * + * EVO requires a non-tearing flip when certain parameters are changing. See + * NV_DISP_BASE_STATE_ERROR_052 in dispClass024XBaseUpdateErrorChecks.mfs. + */ +static NvBool FlipRequiresNonTearingMode( + const NVDevEvoRec *pDevEvo, + const NvU32 head, + const NVFlipChannelEvoHwState *pOld, + const NVFlipChannelEvoHwState *pNew) +{ + // TODO: Do we need to care about the right eye here? The error check + // doesn't. + const NVSurfaceEvoRec *pOldSurf = pOld->pSurfaceEvo[NVKMS_LEFT]; + const NVSurfaceEvoRec *pNewSurf = pNew->pSurfaceEvo[NVKMS_LEFT]; + NvU32 oldHwFormat = 0, newHwFormat = 0; + + if (pOldSurf == NULL || pNewSurf == NULL) { + return TRUE; + } + + // If these functions actually return FALSE at this point, then something is + // really wrong... + if (!pDevEvo->hal->ValidateWindowFormat( + pOldSurf->format, NULL, &oldHwFormat)) { + nvAssert(FALSE); + } + + if (!pDevEvo->hal->ValidateWindowFormat( + pNewSurf->format, NULL, &newHwFormat)) { + nvAssert(FALSE); + } + + // Commented entries are things checked in the .mfs that are not yet + // supported in NVKMS. + return // SuperSample + oldHwFormat != newHwFormat || + // Gamma + // Layout (i.e. frame, field1, or field2) + pOldSurf->widthInPixels != pNewSurf->widthInPixels || + pOldSurf->heightInPixels != pNewSurf->heightInPixels || + pOldSurf->layout != pNewSurf->layout; + // UseGainOfs + // NewBaseLut -- USE_CORE_LUT is programmed in InitChannel* + // NewOutputLut +} + + +/*! + * Apply flip overrides if necessary. + * + * 1. Override swap intervals for VRR. + * 2. If the flip is changing certain parameters, override the tearing mode. + */ +static NvBool ApplyBaseFlipOverrides( + const NVDevEvoRec *pDevEvo, + const NvU32 sd, + const NvU32 head, + NVFlipChannelEvoHwState *pNew, + NvBool allowVrr) +{ + const NVDispEvoRec *pDispEvo = pDevEvo->gpus[sd].pDispEvo; + const NVFlipChannelEvoHwState *pOld = + &pDevEvo->gpus[sd].headState[head].layer[NVKMS_MAIN_LAYER]; + + // Apply VRR swap interval overrides. + // + // Note that this applies the overrides whenever the client requests VRR and + // VRR is enabled, regardless of whether actually activating it later + // succeeds. + if (allowVrr) { + if (!nvHeadIsActive(pDispEvo, head)) { + // + // XXX If VRR is allowed then modeset should have happened before + // base channel flip, currently we don't know how to do modeset + // and program base channel for VRR at same time. This should be + // revisited as part of bug 1731279. + // + return FALSE; + } + nvApplyVrrBaseFlipOverrides(pDevEvo->gpus[sd].pDispEvo, head, + pOld, pNew); + } + + if (!nvHeadIsActive(pDispEvo, head)) { + // + // This is possible when modeset and base flip happening at same time, + // tearing parameter does not make sense in that case, + // it should is disabled. + // + pNew->tearing = FALSE; + } else { + // Force non-tearing mode if EVO requires it. + if (FlipRequiresNonTearingMode(pDevEvo, head, pOld, pNew)) { + pNew->tearing = FALSE; + } + } + + return TRUE; +} + +static NvBool ValidateScalingUsageBounds( + const struct NvKmsScalingUsageBounds *pS, + const struct NvKmsScalingUsageBounds *pMaxS) +{ + return (pS->maxVDownscaleFactor <= pMaxS->maxVDownscaleFactor) && + (pS->maxHDownscaleFactor <= pMaxS->maxHDownscaleFactor) && + (pS->vTaps <= pMaxS->vTaps) && + (!pS->vUpscalingAllowed || pMaxS->vUpscalingAllowed); +} + +/*! + * Validate the requested usage bounds against the specified maximums. + */ +static NvBool ValidateUsageBounds( + const NVDevEvoRec *pDevEvo, + const NvU32 head, + const struct NvKmsUsageBounds *pUsage, + const struct NvKmsUsageBounds *pGuaranteedUsage) +{ + NvU32 i; + + for (i = 0; i < pDevEvo->head[head].numLayers; i++) { + const NvU64 supportedSurfaceFormatsUnion = + pUsage->layer[i].supportedSurfaceMemoryFormats | + pGuaranteedUsage->layer[i].supportedSurfaceMemoryFormats; + + if ((pUsage->layer[i].usable && !pGuaranteedUsage->layer[i].usable) || + (supportedSurfaceFormatsUnion != + pGuaranteedUsage->layer[i].supportedSurfaceMemoryFormats) || + !ValidateScalingUsageBounds(&pUsage->layer[i].scaling, + &pGuaranteedUsage->layer[i].scaling)) { + return FALSE; + } + } + + return TRUE; +} + +/*! + * Assign pFlipState->usage. + */ +static NvBool AssignUsageBounds( + const NVDevEvoRec *pDevEvo, + const NvU32 head, + NVFlipEvoHwState *pFlipState) +{ + struct NvKmsUsageBounds *pUsage = &pFlipState->usage; + int i; + + for (i = 0; i < pDevEvo->head[head].numLayers; i++) { + const NVFlipChannelEvoHwState *pLayerFlipState = &pFlipState->layer[i]; + + nvInitScalingUsageBounds(pDevEvo, &pUsage->layer[i].scaling); + + if (pLayerFlipState->pSurfaceEvo[NVKMS_LEFT]) { + pUsage->layer[i].usable = TRUE; + pUsage->layer[i].supportedSurfaceMemoryFormats = + nvEvoGetFormatsWithEqualOrLowerUsageBound( + pLayerFlipState->pSurfaceEvo[NVKMS_LEFT]->format, + pDevEvo->caps.layerCaps[i].supportedSurfaceMemoryFormats); + + if (pDevEvo->hal->GetWindowScalingCaps) { + const NVEvoScalerCaps *pScalerCaps = + pDevEvo->hal->GetWindowScalingCaps(pDevEvo); + + if (!nvComputeScalingUsageBounds(pScalerCaps, + pLayerFlipState->sizeIn.width, + pLayerFlipState->sizeIn.height, + pLayerFlipState->sizeOut.width, + pLayerFlipState->sizeOut.height, + pLayerFlipState->hTaps, + pLayerFlipState->vTaps, + &pUsage->layer[i].scaling)) { + return FALSE; + } + } + + if (pLayerFlipState->maxDownscaleFactors.specified) { + struct NvKmsScalingUsageBounds *pTargetScaling = + &pFlipState->usage.layer[i].scaling; + + if ((pLayerFlipState->maxDownscaleFactors.vertical < + pTargetScaling->maxVDownscaleFactor) || + (pLayerFlipState->maxDownscaleFactors.horizontal < + pTargetScaling->maxHDownscaleFactor)) { + return FALSE; + } + + pTargetScaling->maxVDownscaleFactor = + pLayerFlipState->maxDownscaleFactors.vertical; + pTargetScaling->maxHDownscaleFactor = + pLayerFlipState->maxDownscaleFactors.horizontal; + } + + } else { + pUsage->layer[i].usable = FALSE; + pUsage->layer[i].supportedSurfaceMemoryFormats = 0; + } + } + + return TRUE; +} + +void +nvOverrideScalingUsageBounds(const NVDevEvoRec *pDevEvo, + NvU32 head, + NVFlipEvoHwState *pFlipState, + const struct NvKmsUsageBounds *pPossibleUsage) +{ + NvU32 i; + + for (i = 0; i < pDevEvo->head[head].numLayers; i++) { + const NVFlipChannelEvoHwState *pLayerFlipState = &pFlipState->layer[i]; + const struct NvKmsScalingUsageBounds *pPossibleScaling = + &pPossibleUsage->layer[i].scaling; + struct NvKmsScalingUsageBounds *pTargetScaling = + &pFlipState->usage.layer[i].scaling; + + if (!pFlipState->usage.layer[i].usable) { + continue; + } + + if (!pLayerFlipState->maxDownscaleFactors.specified) { + const NvU16 possibleV = pPossibleScaling->maxVDownscaleFactor; + const NvU16 possibleH = pPossibleScaling->maxHDownscaleFactor; + NvU16 targetV = pTargetScaling->maxVDownscaleFactor; + NvU16 targetH = pTargetScaling->maxHDownscaleFactor; + + /* + * Calculate max H/V downscale factor by quantizing the range. + * + * E.g., + * max H/V downscale factor supported by HW is 4x for 5-tap and 2x + * for 2-tap mode. If 5-tap mode is required, the target usage bound + * that nvkms will attempt to program will either allow up to 2x + * downscaling, or up to 4x downscaling. If 2-tap mode is required, + * the target usage bound that NVKMS will attempt to program will + * allow up to 2x downscaling. Example: to downscale from 4096x2160 + * -> 2731x864 in 5-tap mode, NVKMS would specify up to 2x for the + * H downscale bound (required is 1.5x), and up to 4x for the V + * downscale bound (required is 2.5x). + */ + if (targetV > NV_EVO_SCALE_FACTOR_1X) { + const NvU16 possibleMid = + NV_EVO_SCALE_FACTOR_1X + ((possibleV - NV_EVO_SCALE_FACTOR_1X) / 2); + + if (targetV <= possibleMid) { + pTargetScaling->maxVDownscaleFactor = possibleMid; + } else { + pTargetScaling->maxVDownscaleFactor = possibleV; + } + } + + if (targetH > NV_EVO_SCALE_FACTOR_1X) { + const NvU16 possibleMid = + NV_EVO_SCALE_FACTOR_1X + ((possibleH - NV_EVO_SCALE_FACTOR_1X) / 2); + + if (targetH <= possibleMid) { + pTargetScaling->maxHDownscaleFactor = possibleMid; + } else { + pTargetScaling->maxHDownscaleFactor = possibleH; + } + } + } + + pTargetScaling->vTaps = pPossibleScaling->vTaps; + pTargetScaling->vUpscalingAllowed = pPossibleScaling->vUpscalingAllowed; + } +} + +static NvBool FlipTimeStampValidForChannel( + const NVEvoChannel *pChannel, + NvU64 timeStamp) +{ + if (pChannel->caps.validTimeStampBits < 64) { + const NvU64 validTimeStampMask = + NVBIT64(pChannel->caps.validTimeStampBits) - 1; + if ((timeStamp & ~validTimeStampMask) != 0) { + return FALSE; + } + } + return TRUE; +} + +static NvBool UpdateFlipEvoHwStateHDRStaticMetadata( + const NVDevEvoRec *pDevEvo, + const struct NvKmsFlipCommonParams *pParams, + NVFlipEvoHwState *pFlipState, + NVFlipChannelEvoHwState *pHwState, + const NvU32 head, + const NvU32 layer) +{ + if (pParams->layer[layer].hdr.specified) { + if (pParams->layer[layer].hdr.enabled) { + // Don't allow enabling HDR on a layer that doesn't support it. + if (!pDevEvo->caps.layerCaps[layer].supportsHDR) { + return FALSE; + } + + pHwState->hdrStaticMetadata.val = + pParams->layer[layer].hdr.staticMetadata; + } + pHwState->hdrStaticMetadata.enabled = pParams->layer[layer].hdr.enabled; + + // Only mark dirty if layer supports HDR, otherwise this is a no-op. + if (pDevEvo->caps.layerCaps[layer].supportsHDR) { + pFlipState->dirty.hdrStaticMetadata = TRUE; + } + } + + return TRUE; +} + +static NvBool UpdateLayerFlipEvoHwStateCommon( + const struct NvKmsPerOpenDev *pOpenDev, + const NVDevEvoRec *pDevEvo, + const NvU32 sd, + const NvU32 head, + const NvU32 layer, + const struct NvKmsFlipCommonParams *pParams, + NVFlipEvoHwState *pFlipState) +{ + const NVEvoChannel *pChannel = pDevEvo->head[head].layer[layer]; + NVFlipChannelEvoHwState *pHwState = &pFlipState->layer[layer]; + const NVEvoApiHandlesRec *pOpenDevSurfaceHandles = + nvGetSurfaceHandlesFromOpenDevConst(pOpenDev); + NvBool ret; + + if (pParams->layer[layer].surface.specified) { + ret = nvAssignSurfaceArray(pDevEvo, + pOpenDevSurfaceHandles, + pParams->layer[layer].surface.handle, + FALSE /* isUsedByCursorChannel */, + TRUE /* isUsedByLayerChannel */, + pHwState->pSurfaceEvo); + if (!ret) { + return FALSE; + } + + /* + * Verify the (rotation, reflectionX, reflectionY) is a + * combination currently supported. + */ + if ((NVBIT(NvKmsRRParamsToCapBit(&pParams->layer[layer].surface.rrParams)) & + pDevEvo->caps.validLayerRRTransforms) == 0) { + return FALSE; + } + pHwState->rrParams = pParams->layer[layer].surface.rrParams; + + } + + /* Verify the timestamp is in the valid range for this channel. */ + if (!FlipTimeStampValidForChannel(pChannel, + pParams->layer[layer].timeStamp)) { + return FALSE; + } + pHwState->timeStamp = pParams->layer[layer].timeStamp; + + if (pParams->layer[layer].syncObjects.specified) { + if (!pDevEvo->supportsSyncpts && + pParams->layer[layer].syncObjects.val.useSyncpt) { + return FALSE; + } + + nvkms_memset(&pFlipState->layer[layer].syncObject, + 0, + sizeof(pFlipState->layer[layer].syncObject)); + + if (pParams->layer[layer].syncObjects.val.useSyncpt) { + ret = AssignPreSyncptEvoHwState(pDevEvo, + &pParams->layer[layer].syncObjects.val, + &pHwState->syncObject); + if (!ret) { + return FALSE; + } + pFlipState->dirty.layerSyncObjects[layer] = TRUE; + + ret = AssignPostSyncptEvoHwState(pDevEvo, + pDevEvo->head[head].layer[layer], + &pParams->layer[layer].syncObjects.val, + &pHwState->syncObject); + if (!ret) { + return FALSE; + } + } else { + if (pParams->layer[layer].syncObjects.val.u.semaphores.acquire.surface.surfaceHandle != 0 || + pParams->layer[layer].syncObjects.val.u.semaphores.release.surface.surfaceHandle != 0) { + if (pParams->layer[layer].skipPendingFlips) { + return FALSE; + } + } + + ret = nvAssignSemaphoreEvoHwState(pDevEvo, + pOpenDevSurfaceHandles, + layer, + sd, + &pParams->layer[layer].syncObjects.val, + &pHwState->syncObject); + if (!ret) { + return FALSE; + } + } + } + + if (pHwState->pSurfaceEvo[NVKMS_LEFT]) { + pHwState->minPresentInterval = + pParams->layer[layer].minPresentInterval; + } else { + /* The hardware requires that MPI be 0 when disabled. */ + pHwState->minPresentInterval = 0; + } + + if (pParams->layer[layer].sizeIn.specified) { + pHwState->sizeIn = pParams->layer[layer].sizeIn.val; + } + + if (pParams->layer[layer].sizeOut.specified) { + pHwState->sizeOut = pParams->layer[layer].sizeOut.val; + } + + /* + * If supportsWindowMode = TRUE, the sizeIn/sizeOut dimensions can be + * any arbitrary (valid) values. + * + * If supportsWindowMode = FALSE (legacy EVO main layer), the sizeIn + * /sizeOut dimensions must match the size of the surface for that layer. + * + * Note that if sizeIn/Out dimensions are invalid i.e. with a width or + * height of zero, this will be rejected by a call to + * ValidateFlipChannelEvoHwState() later in the code path. + * + * Note that if scaling is unsupported, i.e. that sizeIn cannot differ + * from sizeOut, then any unsupported configurations will be caught by the + * ComputeWindowScalingTaps() call later on in this function. + */ + if (!pDevEvo->caps.layerCaps[layer].supportsWindowMode && + (pHwState->pSurfaceEvo[NVKMS_LEFT] != NULL)) { + const NVSurfaceEvoRec *pSurfaceEvo = + pHwState->pSurfaceEvo[NVKMS_LEFT]; + + if ((pHwState->sizeIn.width != pSurfaceEvo->widthInPixels) || + (pHwState->sizeIn.height != pSurfaceEvo->heightInPixels)) { + return FALSE; + } + + if ((pHwState->sizeOut.width != pSurfaceEvo->widthInPixels) || + (pHwState->sizeOut.height != pSurfaceEvo->heightInPixels)) { + return FALSE; + } + } + + /* + * Allow the client to specify non-origin outputPosition only if the + * layer supports window mode. + * + * If window mode is unsupported but the client specifies non-origin + * outputPosition, return FALSE. + */ + if (pDevEvo->caps.layerCaps[layer].supportsWindowMode) { + if (pParams->layer[layer].outputPosition.specified) { + const NvS16 x = pParams->layer[layer].outputPosition.val.x; + const NvS16 y = pParams->layer[layer].outputPosition.val.y; + if ((pHwState->outputPosition.x != x) || + (pHwState->outputPosition.y != y)) { + pHwState->outputPosition.x = x; + pHwState->outputPosition.y = y; + pFlipState->dirty.layerPosition[layer] = TRUE; + } + } + } else if (pParams->layer[layer].outputPosition.specified && + ((pParams->layer[layer].outputPosition.val.x != 0) || + (pParams->layer[layer].outputPosition.val.y != 0))) { + return FALSE; + } + + if (pParams->layer[layer].compositionParams.specified) { + pHwState->composition = + pParams->layer[layer].compositionParams.val; + } + + if (!UpdateFlipEvoHwStateHDRStaticMetadata( + pDevEvo, pParams, pFlipState, + pHwState, head, layer)) { + return FALSE; + } + + if (pParams->layer[layer].colorspace.specified) { + pHwState->colorspace = + pParams->layer[layer].colorspace.val; + } + + if (pHwState->composition.depth == 0) { + pHwState->composition.depth = + NVKMS_MAX_LAYERS_PER_HEAD - layer; + } + + /* XXX Move ValidatePerLayerCompParams() call to nvValidateFlipEvoHwState() */ + if (!nvValidatePerLayerCompParams( + &pHwState->composition, + &pDevEvo->caps.layerCaps[layer].composition, + pHwState->pSurfaceEvo[NVKMS_LEFT])) { + return FALSE; + } + + if (!pDevEvo->hal->ComputeWindowScalingTaps(pDevEvo, + pChannel, + pHwState)) { + return FALSE; + } + + if (pParams->layer[layer].completionNotifier.specified) { + ret = nvAssignCompletionNotifierEvoHwState( + pDevEvo, + pOpenDevSurfaceHandles, + &pParams->layer[layer].completionNotifier.val, + layer, + &pFlipState->layer[layer].completionNotifier); + if (!ret) { + return FALSE; + } + } + + if (pParams->layer[layer].maxDownscaleFactors.specified) { + pFlipState->layer[layer].maxDownscaleFactors.vertical = + pParams->layer[layer].maxDownscaleFactors.vertical; + pFlipState->layer[layer].maxDownscaleFactors.horizontal = + pParams->layer[layer].maxDownscaleFactors.horizontal; + pFlipState->layer[layer].maxDownscaleFactors.specified = TRUE; + } else { + pFlipState->layer[layer].maxDownscaleFactors.vertical = 0; + pFlipState->layer[layer].maxDownscaleFactors.horizontal = 0; + pFlipState->layer[layer].maxDownscaleFactors.specified = FALSE; + } + + pFlipState->dirty.layer[layer] = TRUE; + + return TRUE; +} + +static NvBool UpdateMainLayerFlipEvoHwState( + const struct NvKmsPerOpenDev *pOpenDev, + const NVDevEvoRec *pDevEvo, + const NvU32 sd, + const NvU32 head, + const struct NvKmsFlipCommonParams *pParams, + NVFlipEvoHwState *pFlipState, + NvBool allowVrr) +{ + const NVEvoChannel *pChannel = + pDevEvo->head[head].layer[NVKMS_MAIN_LAYER]; + NVFlipChannelEvoHwState *pHwState = &pFlipState->layer[NVKMS_MAIN_LAYER]; + + if (!nvIsLayerDirty(pParams, NVKMS_MAIN_LAYER)) { + return TRUE; + } + + if (!UpdateLayerFlipEvoHwStateCommon(pOpenDev, pDevEvo, sd, head, + NVKMS_MAIN_LAYER, + pParams, pFlipState)) { + return FALSE; + } + + if (pParams->layer[NVKMS_MAIN_LAYER].csc.specified) { + if (pParams->layer[NVKMS_MAIN_LAYER].csc.useMain) { + return FALSE; + } else { + pHwState->cscMatrix = pParams->layer[NVKMS_MAIN_LAYER].csc.matrix; + } + } + + if (pParams->layer[NVKMS_MAIN_LAYER].surface.specified) { + if (pParams->layer[NVKMS_MAIN_LAYER].perEyeStereoFlip && + !pChannel->caps.perEyeStereoFlips) { + return FALSE; + } + + pHwState->perEyeStereoFlip = + pParams->layer[NVKMS_MAIN_LAYER].perEyeStereoFlip; + } + + if (pParams->layer[NVKMS_MAIN_LAYER].tearing && !pChannel->caps.tearingFlips) { + return FALSE; + } + + // EVO will throw an invalid argument exception if + // minPresentInterval is too large, or if tearing is enabled and + // it's not zero. + if (pParams->layer[NVKMS_MAIN_LAYER].minPresentInterval > NV_MAX_SWAP_INTERVAL || + (pParams->layer[NVKMS_MAIN_LAYER].tearing && + pParams->layer[NVKMS_MAIN_LAYER].minPresentInterval != 0)) { + return FALSE; + } + + pHwState->tearing = pParams->layer[NVKMS_MAIN_LAYER].tearing; + + if (!ApplyBaseFlipOverrides(pDevEvo, + sd, head, &pFlipState->layer[NVKMS_MAIN_LAYER], + allowVrr)) { + return FALSE; + } + + pFlipState->skipLayerPendingFlips[NVKMS_MAIN_LAYER] = + pParams->layer[NVKMS_MAIN_LAYER].skipPendingFlips; + + return TRUE; +} + +static NvBool UpdateCursorLayerFlipEvoHwState( + const struct NvKmsPerOpenDev *pOpenDev, + const NVDevEvoRec *pDevEvo, + const struct NvKmsFlipCommonParams *pParams, + const NVHwModeTimingsEvo *pTimings, + const NvU8 tilePosition, + NVFlipEvoHwState *pFlipState) +{ + if (pParams->cursor.imageSpecified) { + if (!nvAssignCursorSurface(pOpenDev, pDevEvo, &pParams->cursor.image, + &pFlipState->cursor.pSurfaceEvo)) { + return FALSE; + } + + if (pFlipState->cursor.pSurfaceEvo != NULL) { + pFlipState->cursor.cursorCompParams = + pParams->cursor.image.cursorCompParams; + } + + pFlipState->dirty.cursorSurface = TRUE; + } + + if (pParams->cursor.positionSpecified) { + pFlipState->cursor.x = (pParams->cursor.position.x - + (pTimings->viewPort.in.width * tilePosition)); + pFlipState->cursor.y = pParams->cursor.position.y; + + pFlipState->dirty.cursorPosition = TRUE; + } + + return TRUE; +} + +static NvBool UpdateOverlayLayerFlipEvoHwState( + const struct NvKmsPerOpenDev *pOpenDev, + const NVDevEvoRec *pDevEvo, + const NvU32 sd, + const NvU32 head, + const NvU32 layer, + const struct NvKmsFlipCommonParams *pParams, + NVFlipEvoHwState *pFlipState) +{ + NVFlipChannelEvoHwState *pHwState = &pFlipState->layer[layer]; + + nvAssert(layer != NVKMS_MAIN_LAYER); + + if (!nvIsLayerDirty(pParams, layer)) { + return TRUE; + } + + if (pParams->layer[layer].skipPendingFlips || + pParams->layer[layer].perEyeStereoFlip) { + return FALSE; + } + + if (!UpdateLayerFlipEvoHwStateCommon(pOpenDev, pDevEvo, sd, head, layer, + pParams, pFlipState)) { + return FALSE; + } + + if (pParams->layer[layer].csc.specified) { + if (pParams->layer[layer].csc.useMain) { + if (pFlipState->layer[NVKMS_MAIN_LAYER].pSurfaceEvo[NVKMS_LEFT]) { + pHwState->cscMatrix = + pFlipState->layer[NVKMS_MAIN_LAYER].cscMatrix; + } + } else { + pHwState->cscMatrix = pParams->layer[layer].csc.matrix; + } + } + + return TRUE; +} + +/*! + * Update the NVFlipEvoHwState, using NvKmsFlipCommonParams. + * + * Propagate the requested configuration from NvKmsFlipCommonParams to + * NVFlipEvoHwState, performing steps such as translating from + * NvKmsSurfaceHandle to NVSurfaceEvoRecs. Validate the NvKmsFlipCommonParams + * parameters, but defer more general validation of the resulting + * NVFlipEvoHwState until nvValidateFlipEvoHwState(), which callers must call + * separately. + * + * The NVFlipEvoHwState should first be initialized by calling + * nvInitFlipEvoHwState(). + * + * No NVKMS hardware or software state should be altered here, because + * this function is used before we have decided to commit the proposed + * NVFlipEvoHwState to hardware. + * + * \param[in] pOpenDev The pOpenDev of the client doing the flip. + * \param[in] pDevEvo The device on which the surface image will be set. + * \param[in] sd The subdevice for the flip, as specified by the + * client. + * \param[in] head The head for the flip, as specified by the client. + * \param[in] pParams The requested flip, NvKmsFlipCommonParams. + * \param[in] pTimings The mode timings for the flip. + * \param[in,out] pFlipState The resulting NVFlipEvoHwState. + * \param[in] allowVrr Whether VRR flipping should be allowed. + * \param[in] pPossibleUsage Possible usage. + * + * \return If pFlipState could be updated, return TRUE. + * Otherwise, return FALSE. + */ +NvBool nvUpdateFlipEvoHwState( + const struct NvKmsPerOpenDev *pOpenDev, + const NVDevEvoRec *pDevEvo, + const NvU32 sd, + const NvU32 head, + const struct NvKmsFlipCommonParams *pParams, + const NVHwModeTimingsEvo *pTimings, + const NvU8 tilePosition, + NVFlipEvoHwState *pFlipState, + NvBool allowVrr) +{ + NvU32 layer; + + if (pParams->viewPortIn.specified) { + pFlipState->dirty.viewPortPointIn = TRUE; + pFlipState->viewPortPointIn.x = pParams->viewPortIn.point.x + + (pTimings->viewPort.in.width * tilePosition); + pFlipState->viewPortPointIn.y = pParams->viewPortIn.point.y; + } + + if (!UpdateCursorLayerFlipEvoHwState(pOpenDev, pDevEvo, pParams, pTimings, + tilePosition, pFlipState)) { + return FALSE; + } + + if (pParams->tf.specified) { + pFlipState->dirty.tf = TRUE; + pFlipState->tf = pParams->tf.val; + } + + for (layer = 0; layer < pDevEvo->head[head].numLayers; layer++) { + if (layer == NVKMS_MAIN_LAYER) { + if (!UpdateMainLayerFlipEvoHwState(pOpenDev, pDevEvo, sd, head, + pParams, pFlipState, allowVrr)) { + return FALSE; + } + continue; + } + + if (!UpdateOverlayLayerFlipEvoHwState(pOpenDev, pDevEvo, sd, head, + layer, pParams, pFlipState)) { + return FALSE; + } + } + + if (!AssignUsageBounds(pDevEvo, head, pFlipState)) { + return FALSE; + } + + /* + * If there is active cursor/cropped-window(overlay) without full screen + * window(base/core) then NVKMS is supposed to disable MidFrame/DWCF + * watermark. + */ + + pFlipState->disableMidFrameAndDWCFWatermark = FALSE; + + if (NV5070_CTRL_SYSTEM_GET_CAP( + pDevEvo->capsBits, + NV5070_CTRL_SYSTEM_CAPS_BUG_2052012_GLITCHY_MCLK_SWITCH) && + !pFlipState->layer[NVKMS_MAIN_LAYER].pSurfaceEvo[NVKMS_LEFT]) { + + if (pFlipState->cursor.pSurfaceEvo != NULL) { + pFlipState->disableMidFrameAndDWCFWatermark = TRUE; + } else { + NvU32 layer; + + /* + * XXX TODO: Check the output size of the overlay in order + * to determine if it will be fullscreen or not. + */ + for (layer = 0; layer < pDevEvo->head[head].numLayers; layer++) { + if (layer != NVKMS_MAIN_LAYER && + pFlipState->layer[layer].pSurfaceEvo[NVKMS_LEFT] != NULL) { + pFlipState->disableMidFrameAndDWCFWatermark = TRUE; + break; + } + } + } + } + + return TRUE; +} + +/* + * Checks that if the surface is NULL (i.e. no image will be shown), various + * other elements must be NULL as well. If the surface is not NULL, verifies + * that the sizeIn/Out have nonzero values. + */ +inline static NvBool ValidateFlipChannelEvoHwState( + const NVFlipChannelEvoHwState *pState) +{ + if (pState->pSurfaceEvo[NVKMS_LEFT] != NULL) { + /* Verify sizes are valid. */ + if ((pState->sizeIn.width == 0) || (pState->sizeIn.height == 0) || + (pState->sizeOut.width == 0) || (pState->sizeOut.height == 0)) { + return FALSE; + } + + return TRUE; + } + + if (pState->completionNotifier.surface.pSurfaceEvo != NULL) { + return FALSE; + } + + if (!pState->syncObject.usingSyncpt) { + if (pState->syncObject.u.semaphores.acquireSurface.pSurfaceEvo != NULL) { + return FALSE; + } + + if (pState->syncObject.u.semaphores.releaseSurface.pSurfaceEvo != NULL) { + return FALSE; + } + } + + return TRUE; +} + +static NvBool ValidateSurfaceSize( + const NVDevEvoRec *pDevEvo, + const NVSurfaceEvoRec *pSurfaceEvo, + const struct NvKmsRect *sourceFetchRect) +{ + NvU8 planeIndex; + + if ((pSurfaceEvo->widthInPixels > pDevEvo->caps.maxWidthInPixels) || + (pSurfaceEvo->heightInPixels > pDevEvo->caps.maxHeight)) { + return FALSE; + } + + FOR_ALL_VALID_PLANES(planeIndex, pSurfaceEvo) { + + NvU64 planePitch = pSurfaceEvo->planes[planeIndex].pitch; + + /* + * Convert planePitch to units of bytes if it's currently specified in + * units of blocks. Each block is 64-bytes wide. + */ + if (pSurfaceEvo->layout == NvKmsSurfaceMemoryLayoutBlockLinear) { + planePitch <<= NVKMS_BLOCK_LINEAR_LOG_GOB_WIDTH; + } + + if (planePitch > pDevEvo->caps.maxWidthInBytes) { + return FALSE; + } + } + + if (!pDevEvo->hal->ValidateWindowFormat(pSurfaceEvo->format, + sourceFetchRect, + NULL)) { + return FALSE; + } + + return TRUE; +} + +static NvBool +ValidateMainFlipChannelEvoHwState(const NVDevEvoRec *pDevEvo, + const NVFlipChannelEvoHwState *pHwState, + const NVHwModeTimingsEvo *pTimings, + struct NvKmsPoint viewPortPointIn) +{ + NvU32 eye; + const NVSurfaceEvoRec *pFirstSurfaceEvo = NULL; + + /* + * This struct represents the source fetch rectangle for a given surface, + * and will be populated later as such. This function doesn't explicitly set + * sourceFetchRect.{x,y} because NVKMS currently doesn't support programming + * source fetch offsets, so the init value of 0 should be fine for both of + * these fields. + */ + struct NvKmsRect sourceFetchRect = {0}; + + if (!ValidateFlipChannelEvoHwState(pHwState)) { + return FALSE; + } + + for (eye = 0; eye < NVKMS_MAX_EYES; eye++) { + const NVSurfaceEvoRec *pSurfaceEvo = pHwState->pSurfaceEvo[eye]; + + if (pSurfaceEvo == NULL) { + continue; + } + + if (pFirstSurfaceEvo == NULL) { + pFirstSurfaceEvo = pSurfaceEvo; + } else if (pSurfaceEvo->widthInPixels != + pFirstSurfaceEvo->widthInPixels || + pSurfaceEvo->heightInPixels != + pFirstSurfaceEvo->heightInPixels) { + return FALSE; + } + + sourceFetchRect.width = pHwState->sizeIn.width; + sourceFetchRect.height = pHwState->sizeIn.height; + + if (!ValidateSurfaceSize(pDevEvo, pSurfaceEvo, &sourceFetchRect)) { + return FALSE; + } + + /* The use of A_plus_B_greater_than_C_U16 is only valid if these + * fit in a U16 */ + nvAssert(pSurfaceEvo->widthInPixels <= NV_U16_MAX); + nvAssert(pSurfaceEvo->heightInPixels <= NV_U16_MAX); + /* And the checks above in ValidateSurfaceSize should have + * guaranteed that. */ + nvAssert(pDevEvo->caps.maxWidthInPixels <= NV_U16_MAX); + nvAssert(pDevEvo->caps.maxHeight <= NV_U16_MAX); + + /* + * Validate that the requested viewport parameters fit within the + * specified surface, unless the main layer is allowed to be smaller + * than the viewport. + */ + if (!pDevEvo->caps.layerCaps[NVKMS_MAIN_LAYER].supportsWindowMode) { + if (A_plus_B_greater_than_C_U16(viewPortPointIn.x, + pTimings->viewPort.in.width, + pSurfaceEvo->widthInPixels)) { + return FALSE; + } + + if (A_plus_B_greater_than_C_U16(viewPortPointIn.y, + pTimings->viewPort.in.height, + pSurfaceEvo->heightInPixels)) { + return FALSE; + } + } + } + + return TRUE; +} + +static NvBool +ValidateOverlayFlipChannelEvoHwState(const NVDevEvoRec *pDevEvo, + const NVFlipChannelEvoHwState *pHwState) +{ + const NVSurfaceEvoRec *pSurfaceEvo = pHwState->pSurfaceEvo[NVKMS_LEFT]; + + /* + * This struct represents the source fetch rectangle for a given surface, + * and will be populated later as such. This function doesn't explicitly set + * sourceFetchRect.{x,y} because NVKMS currently doesn't support programming + * source fetch offsets, so the init value of 0 should be fine for both of + * these fields. + */ + struct NvKmsRect sourceFetchRect = {0}; + + if (!ValidateFlipChannelEvoHwState(pHwState)) { + return FALSE; + } + + if (pSurfaceEvo == NULL) { + return TRUE; + } + + sourceFetchRect.width = pHwState->sizeIn.width; + sourceFetchRect.height = pHwState->sizeIn.height; + + if (!ValidateSurfaceSize(pDevEvo, pSurfaceEvo, &sourceFetchRect)) { + return FALSE; + } + + /* Validate input size against surface size. */ + if (pHwState->sizeIn.width > pSurfaceEvo->widthInPixels || + pHwState->sizeIn.height > pSurfaceEvo->heightInPixels) { + return FALSE; + } + + return TRUE; +} + +static NvBool +ValidateHDR(const NVDevEvoRec *pDevEvo, + const NvU32 head, + const NVFlipEvoHwState *pFlipState) +{ + NvU32 staticMetadataCount = 0; + NvU32 layerSupportedCount = 0; + + NvU32 layer; + + for (layer = 0; layer < pDevEvo->head[head].numLayers; layer++) { + if (pDevEvo->caps.layerCaps[layer].supportsHDR) { + layerSupportedCount++; + } + + if (pFlipState->layer[layer].hdrStaticMetadata.enabled) { + staticMetadataCount++; + + /* + * If HDR static metadata is enabled, we may need TMO. CSC11 will be + * used by NVKMS to convert from linear FP16 LMS to linear FP16 RGB. + * As such, the user-supplied precomp CSC can't be programmed into + * CSC11 in this case. + */ + if (!nvIsCscMatrixIdentity(&pFlipState->layer[layer].cscMatrix)) { + return FALSE; + } + + // Already checked in UpdateFlipEvoHwStateHDRStaticMetadata() + nvAssert(pDevEvo->caps.layerCaps[layer].supportsHDR); + } + } + + // If enabling HDR... + // XXX HDR TODO: Handle other transfer functions + if (pFlipState->tf == NVKMS_OUTPUT_TF_PQ) { + // At least one layer must have static metadata. + if (staticMetadataCount == 0) { + return FALSE; + } + + // At least one layer must support HDR, implied above. + nvAssert(layerSupportedCount != 0); + } + + // Only one layer can specify HDR static metadata. + // XXX HDR TODO: Support multiple layers with HDR static metadata + if (staticMetadataCount > 1) { + return FALSE; + } + + return TRUE; +} + +static NvBool +ValidateColorspace(const NVDevEvoRec *pDevEvo, + const NvU32 head, + const NVFlipEvoHwState *pFlipState) +{ + NvU32 layer; + + for (layer = 0; layer < pDevEvo->head[head].numLayers; layer++) { + if ((pFlipState->layer[layer].colorspace != + NVKMS_INPUT_COLORSPACE_NONE)) { + + NVSurfaceEvoPtr pSurfaceEvo = + pFlipState->layer[layer].pSurfaceEvo[NVKMS_LEFT]; + const NvKmsSurfaceMemoryFormatInfo *pFormatInfo = + (pSurfaceEvo != NULL) ? + nvKmsGetSurfaceMemoryFormatInfo(pSurfaceEvo->format) : NULL; + + // XXX HDR TODO: Support YUV. + if ((pFormatInfo == NULL) || pFormatInfo->isYUV) { + return FALSE; + } + + // FP16 is only for use with scRGB. + if ((pFlipState->layer[layer].colorspace != + NVKMS_INPUT_COLORSPACE_SCRGB_LINEAR) && + ((pSurfaceEvo->format == + NvKmsSurfaceMemoryFormatRF16GF16BF16AF16) || + (pSurfaceEvo->format == + NvKmsSurfaceMemoryFormatRF16GF16BF16XF16))) { + return FALSE; + } + + // scRGB is only compatible with FP16. + if ((pFlipState->layer[layer].colorspace == + NVKMS_INPUT_COLORSPACE_SCRGB_LINEAR) && + !((pSurfaceEvo->format == + NvKmsSurfaceMemoryFormatRF16GF16BF16AF16) || + (pSurfaceEvo->format == + NvKmsSurfaceMemoryFormatRF16GF16BF16XF16))) { + return FALSE; + } + } + } + + return TRUE; +} + +static NvU32 ValidateCompositionDepth(const NVFlipEvoHwState *pFlipState, + const NvU32 layer) +{ + NvU32 tmpLayer; + + if (pFlipState->layer[layer].pSurfaceEvo[NVKMS_LEFT] == NULL) { + return TRUE; + } + + /* Depth should be different for each of the layers owned by the head */ + for (tmpLayer = 0; tmpLayer < ARRAY_LEN(pFlipState->layer); tmpLayer++) { + if (pFlipState->layer[tmpLayer].pSurfaceEvo[NVKMS_LEFT] == NULL) { + continue; + } + + if ((tmpLayer != layer) && + (pFlipState->layer[tmpLayer].composition.depth == + pFlipState->layer[layer].composition.depth)) { + return FALSE; + } + } + + /* Depth of the main layer should be the greatest one */ + if (pFlipState->layer[NVKMS_MAIN_LAYER].pSurfaceEvo[NVKMS_LEFT] != NULL) { + if (pFlipState->layer[NVKMS_MAIN_LAYER].composition.depth < + pFlipState->layer[layer].composition.depth) { + return FALSE; + } + } + + return TRUE; +} + +/*! + * Perform validation of the the given NVFlipEvoHwState. + */ +NvBool nvValidateFlipEvoHwState( + const NVDevEvoRec *pDevEvo, + const NvU32 head, + const NVHwModeTimingsEvo *pTimings, + const NVFlipEvoHwState *pFlipState) +{ + NvU32 layer; + + for (layer = 0; layer < pDevEvo->head[head].numLayers; layer++) { + if (!ValidateCompositionDepth(pFlipState, layer)) { + return FALSE; + } + + if (layer == NVKMS_MAIN_LAYER) { + if (!ValidateMainFlipChannelEvoHwState(pDevEvo, + &pFlipState->layer[layer], + pTimings, + pFlipState->viewPortPointIn)) { + return FALSE; + } + } else { + const NVFlipChannelEvoHwState *pMainLayerState = + &pFlipState->layer[NVKMS_MAIN_LAYER]; + + /* + * No overlay layer should be enabled if the main + * layer is disabled. + */ + if ((pMainLayerState->pSurfaceEvo[NVKMS_LEFT] == NULL) && + (pFlipState->layer[layer].pSurfaceEvo[NVKMS_LEFT] != NULL)) { + return FALSE; + } + + if (!pFlipState->dirty.layer[layer]) { + continue; + } + + if (!ValidateOverlayFlipChannelEvoHwState(pDevEvo, + &pFlipState->layer[layer])) { + return FALSE; + } + } + } + + if (!ValidateHDR(pDevEvo, head, pFlipState)) { + return FALSE; + } + + if (!ValidateColorspace(pDevEvo, head, pFlipState)) { + return FALSE; + } + + /* XXX NVKMS TODO: validate cursor x,y against current viewport in? */ + + return ValidateUsageBounds(pDevEvo, + head, + &pFlipState->usage, + &pTimings->viewPort.possibleUsage); +} + +/* + * Record in the updateState that the given channel needs interlocked + * window immediate updates. + */ +static void UpdateWinImmInterlockState(NVDevEvoPtr pDevEvo, + NVEvoUpdateState *updateState, + const NVEvoChannel *pChannel) +{ + const NvU32 subDevMask = nvPeekEvoSubDevMask(pDevEvo); + NvU32 sd; + + for (sd = 0; sd < pDevEvo->numSubDevices; sd++) { + if (subDevMask & (1 << sd)) { + updateState->subdev[sd].winImmInterlockMask |= + pChannel->channelMask; + } + } +} + +/*! + * Record in the updateState that the given channel's method are eligible for + * flip locking. + */ +static void UpdateUpdateFlipLockState(NVDevEvoPtr pDevEvo, + NVEvoUpdateState *updateState, + const NVEvoChannel *pChannel) +{ + const NvU32 subDevMask = nvPeekEvoSubDevMask(pDevEvo); + NvU32 sd; + + for (sd = 0; sd < pDevEvo->numSubDevices; sd++) { + if (subDevMask & (1 << sd)) { + updateState->subdev[sd].flipLockQualifyingMask |= + pChannel->channelMask; + } + } +} + +// Adjust from EDID-encoded maxCLL/maxFALL to actual values in units of 1 cd/m2 +static inline NvU32 MaxCvToVal(NvU32 cv) +{ + // 50*2^(cv/32) + return f64_to_ui32( + f64_mul(ui32_to_f64(50), + nvKmsPow(ui32_to_f64(2), + f64_div(ui32_to_f64(cv), + ui32_to_f64(32)))), softfloat_round_near_even, FALSE); +} + +// Adjust from EDID-encoded minCLL to actual value in units of 0.0001 cd/m2 +static inline NvU32 MinCvToVal(NvU32 cv, NvU32 maxCLL) +{ + // 10,000 * (minCLL = (maxCLL * ((cv/255)^2 / 100))) + return f64_to_ui32( + f64_mul(ui32_to_f64(10000), + f64_mul(ui32_to_f64(maxCLL), + f64_div(nvKmsPow(f64_div(ui32_to_f64(cv), + ui32_to_f64(255)), + ui32_to_f64(2)), + ui32_to_f64(100)))), + softfloat_round_near_even, FALSE); +} + +static void UpdateHDR(NVDevEvoPtr pDevEvo, + const NVFlipEvoHwState *pFlipState, + const NvU32 sd, + const NvU32 head, + const NVT_HDR_STATIC_METADATA *pHdrInfo, + NVEvoUpdateState *updateState) +{ + NVDispEvoPtr pDispEvo = pDevEvo->gpus[sd].pDispEvo; + NVDispHeadStateEvoRec *pHeadState = &pDispEvo->headState[head]; + NvBool dirty = FALSE; + + if (pFlipState->dirty.tf) { + // XXX HDR TODO: Handle other transfer functions + if (pFlipState->tf == NVKMS_OUTPUT_TF_PQ) { + pHeadState->hdr.outputState = NVKMS_HDR_OUTPUT_STATE_HDR; + } else if (pHeadState->hdr.outputState == NVKMS_HDR_OUTPUT_STATE_HDR) { + pHeadState->hdr.outputState = + NVKMS_HDR_OUTPUT_STATE_TRANSITIONING_TO_SDR; + } + pHeadState->tf = pFlipState->tf; + + dirty = TRUE; + } + + if (pFlipState->dirty.hdrStaticMetadata) { + NvU32 layer; + NvBool found = FALSE; + for (layer = 0; layer < pDevEvo->head[head].numLayers; layer++) { + // Populate head with updated static metadata. + if (pFlipState->layer[layer].hdrStaticMetadata.enabled) { + NvU32 targetMaxCLL = MaxCvToVal(pHdrInfo->max_cll); + + // Send this layer's metadata to the display. + pHeadState->hdr.staticMetadata = + pFlipState->layer[layer].hdrStaticMetadata.val; + + /* + * Prepare for tone mapping. If we expect to tone map and the + * EDID has valid lum values, mirror EDID lum values to prevent + * redundant tone mapping by the display. We will tone map to + * the specified maxCLL. + */ + if (nvNeedsTmoLut(pDevEvo, pDevEvo->head[head].layer[layer], + &pFlipState->layer[layer], + nvGetHDRSrcMaxLum( + &pFlipState->layer[layer]), + targetMaxCLL)) { + NvU32 targetMaxFALL = MaxCvToVal(pHdrInfo->max_fall); + if ((targetMaxCLL > 0) && + (targetMaxCLL <= 10000) && + (targetMaxCLL >= targetMaxFALL)) { + + NvU32 targetMinCLL = MinCvToVal(pHdrInfo->min_cll, + targetMaxCLL); + + pHeadState->hdr.staticMetadata. + maxDisplayMasteringLuminance = targetMaxCLL; + pHeadState->hdr.staticMetadata. + minDisplayMasteringLuminance = targetMinCLL; + pHeadState->hdr.staticMetadata.maxCLL = targetMaxCLL; + pHeadState->hdr.staticMetadata.maxFALL = targetMaxFALL; + } + } + + /* + * Only one layer can currently specify static metadata, + * verified by ValidateHDR(). + * + * XXX HDR TODO: Combine metadata from multiple layers. + */ + nvAssert(!found); + found = TRUE; + } + } + if (!found) { + nvkms_memset(&pHeadState->hdr.staticMetadata, 0, + sizeof(struct NvKmsHDRStaticMetadata)); + } + + dirty = TRUE; + } + + if (dirty) { + // Update OCSC / OLUT + nvEvoSetLUTContextDma(pDispEvo, head, updateState); + } +} + +/*! + * Program a flip on all requested layers on the specified head. + * + * This also updates pDispEvo->headState[head], caching what was programmed. + + * \param[in,out] pDispEvo The disp on which the flip should be performed. + * \param[in] head The head on which the flip should be performed. + * \param[in] pFlipState The description of how to update each layer. + * \param[in,out] updateState Indicates which channels require UPDATEs + */ +void nvFlipEvoOneHead( + NVDevEvoPtr pDevEvo, + const NvU32 sd, + const NvU32 head, + const NVT_HDR_STATIC_METADATA *pHdrInfo, + const NVFlipEvoHwState *pFlipState, + NvBool allowFlipLock, + NVEvoUpdateState *updateState) +{ + const NvU32 subDeviceMask = NVBIT(sd); + const NVDispHeadStateEvoRec *pHeadState = + &pDevEvo->gpus[sd].pDispEvo->headState[head]; + NvBool bypassComposition = pHeadState->bypassComposition; + NVEvoSubDevHeadStateRec *pSdHeadState = + &pDevEvo->gpus[sd].headState[head]; + NvU32 layer; + + /* + * Provide the pre-update hardware state (in pSdHeadState) and the new + * target state (pFlipState) to the HAL implementation so that it has the + * information it needs to implement the workaround for hardware bug + * 2193096, which requires special logic on transitions between NULL and + * non-NULL ctxdmas (and vice versa). + */ + pDevEvo->hal->FlipTransitionWAR(pDevEvo, sd, head, + pSdHeadState, pFlipState, + updateState); + + /* + * Promote the software state first, such that the hardware programming + * paths below see the new state atomically. + */ + if (pFlipState->dirty.viewPortPointIn) { + pSdHeadState->viewPortPointIn = pFlipState->viewPortPointIn; + } + + if (pFlipState->dirty.cursorSurface || pFlipState->dirty.cursorPosition) { + pSdHeadState->cursor = pFlipState->cursor; + } + + for (layer = 0; layer < pDevEvo->head[head].numLayers; layer++) { + if (pFlipState->dirty.layer[layer]) { + pSdHeadState->layer[layer] = pFlipState->layer[layer]; + } + } + + if (pFlipState->dirty.viewPortPointIn) { + nvSetViewPortPointInEvo(pDevEvo->gpus[sd].pDispEvo, + head, + pFlipState->viewPortPointIn.x, + pFlipState->viewPortPointIn.y, + updateState); + } + + if (pFlipState->dirty.cursorSurface) { + nvPushEvoSubDevMask(pDevEvo, NVBIT(sd)); + pDevEvo->hal->SetCursorImage(pDevEvo, + head, + pSdHeadState->cursor.pSurfaceEvo, + updateState, + &pSdHeadState->cursor.cursorCompParams); + nvPopEvoSubDevMask(pDevEvo); + } + + if (pFlipState->dirty.cursorPosition) { + nvEvoMoveCursorInternal(pDevEvo->gpus[sd].pDispEvo, + head, + pFlipState->cursor.x, + pFlipState->cursor.y); + } + + UpdateHDR(pDevEvo, pFlipState, sd, head, pHdrInfo, updateState); + + for (layer = 0; layer < pDevEvo->head[head].numLayers; layer++) { + if (!pFlipState->dirty.layer[layer]) { + continue; + } + + if (pFlipState->dirty.layerPosition[layer]) { + /* Ensure position updates are supported on this layer. */ + nvAssert(pDevEvo->caps.layerCaps[layer].supportsWindowMode); + + pDevEvo->hal->SetImmPointOut(pDevEvo, + pDevEvo->head[head].layer[layer], + sd, + updateState, + pFlipState->layer[layer].outputPosition.x, + pFlipState->layer[layer].outputPosition.y); + + if (pDevEvo->hal->caps.supportsSynchronizedOverlayPositionUpdate) { + UpdateWinImmInterlockState(pDevEvo, updateState, + pDevEvo->head[head].layer[layer]); + } + } + + nvPushEvoSubDevMask(pDevEvo, subDeviceMask); + + /* Inform DIFR about the upcoming flip. */ + if (pDevEvo->pDifrState) { + nvDIFRNotifyFlip(pDevEvo->pDifrState); + } + + pDevEvo->hal->Flip(pDevEvo, + pDevEvo->head[head].layer[layer], + &pFlipState->layer[layer], + updateState, + bypassComposition); + if (layer == NVKMS_MAIN_LAYER && allowFlipLock) { + UpdateUpdateFlipLockState(pDevEvo, updateState, + pDevEvo->head[head].layer[layer]); + } + nvPopEvoSubDevMask(pDevEvo); + } + + pSdHeadState->targetUsage = pFlipState->usage; + + pSdHeadState->targetDisableMidFrameAndDWCFWatermark = + pFlipState->disableMidFrameAndDWCFWatermark; +} + +static void ChangeSurfaceFlipRefCount( + NVDevEvoPtr pDevEvo, + NVSurfaceEvoPtr pSurfaceEvo, + NvBool increase) +{ + if (pSurfaceEvo != NULL) { + if (increase) { + nvEvoIncrementSurfaceRefCnts(pSurfaceEvo); + } else { + nvEvoDecrementSurfaceRefCnts(pDevEvo, pSurfaceEvo); + } + } +} + +void nvUpdateSurfacesFlipRefCount( + NVDevEvoPtr pDevEvo, + const NvU32 head, + NVFlipEvoHwState *pFlipState, + NvBool increase) +{ + NvU32 i; + + ChangeSurfaceFlipRefCount( + pDevEvo, + pFlipState->cursor.pSurfaceEvo, + increase); + + for (i = 0; i < pDevEvo->head[head].numLayers; i++) { + NVFlipChannelEvoHwState *pLayerFlipState = &pFlipState->layer[i]; + + ChangeSurfaceFlipRefCount( + pDevEvo, + pLayerFlipState->pSurfaceEvo[NVKMS_LEFT], + increase); + ChangeSurfaceFlipRefCount( + pDevEvo, + pLayerFlipState->pSurfaceEvo[NVKMS_RIGHT], + increase); + ChangeSurfaceFlipRefCount( + pDevEvo, + pLayerFlipState->completionNotifier.surface.pSurfaceEvo, + increase); + + if (!pLayerFlipState->syncObject.usingSyncpt) { + ChangeSurfaceFlipRefCount( + pDevEvo, + pLayerFlipState->syncObject.u.semaphores.acquireSurface.pSurfaceEvo, + increase); + ChangeSurfaceFlipRefCount( + pDevEvo, + pLayerFlipState->syncObject.u.semaphores.releaseSurface.pSurfaceEvo, + increase); + } + } +} + +static void UnionScalingUsageBounds( + const struct NvKmsScalingUsageBounds *a, + const struct NvKmsScalingUsageBounds *b, + struct NvKmsScalingUsageBounds *ret) +{ + ret->maxVDownscaleFactor = NV_MAX(a->maxVDownscaleFactor, + b->maxVDownscaleFactor); + ret->maxHDownscaleFactor = NV_MAX(a->maxHDownscaleFactor, + b->maxHDownscaleFactor); + ret->vTaps = NV_MAX(a->vTaps, b->vTaps); + ret->vUpscalingAllowed = a->vUpscalingAllowed || b->vUpscalingAllowed; +} + +void nvUnionUsageBounds(const struct NvKmsUsageBounds *a, + const struct NvKmsUsageBounds *b, + struct NvKmsUsageBounds *ret) +{ + NvU32 i; + + nvkms_memset(ret, 0, sizeof(*ret)); + + for (i = 0; i < ARRAY_LEN(a->layer); i++) { + nvAssert(a->layer[i].usable == + !!a->layer[i].supportedSurfaceMemoryFormats); + nvAssert(b->layer[i].usable == + !!b->layer[i].supportedSurfaceMemoryFormats); + + ret->layer[i].usable = a->layer[i].usable || b->layer[i].usable; + + ret->layer[i].supportedSurfaceMemoryFormats = + a->layer[i].supportedSurfaceMemoryFormats | + b->layer[i].supportedSurfaceMemoryFormats; + + UnionScalingUsageBounds(&a->layer[i].scaling, + &b->layer[i].scaling, + &ret->layer[i].scaling); + } +} + +static void IntersectScalingUsageBounds( + const struct NvKmsScalingUsageBounds *a, + const struct NvKmsScalingUsageBounds *b, + struct NvKmsScalingUsageBounds *ret) +{ + ret->maxVDownscaleFactor = NV_MIN(a->maxVDownscaleFactor, + b->maxVDownscaleFactor); + ret->maxHDownscaleFactor = NV_MIN(a->maxHDownscaleFactor, + b->maxHDownscaleFactor); + ret->vTaps = NV_MIN(a->vTaps, b->vTaps); + ret->vUpscalingAllowed = a->vUpscalingAllowed && b->vUpscalingAllowed; +} + +void nvIntersectUsageBounds(const struct NvKmsUsageBounds *a, + const struct NvKmsUsageBounds *b, + struct NvKmsUsageBounds *ret) +{ + NvU32 i; + + nvkms_memset(ret, 0, sizeof(*ret)); + + for (i = 0; i < ARRAY_LEN(a->layer); i++) { + nvAssert(a->layer[i].usable == + !!a->layer[i].supportedSurfaceMemoryFormats); + nvAssert(b->layer[i].usable == + !!b->layer[i].supportedSurfaceMemoryFormats); + + ret->layer[i].usable = a->layer[i].usable && b->layer[i].usable; + + ret->layer[i].supportedSurfaceMemoryFormats = + a->layer[i].supportedSurfaceMemoryFormats & + b->layer[i].supportedSurfaceMemoryFormats; + + IntersectScalingUsageBounds(&a->layer[i].scaling, + &b->layer[i].scaling, + &ret->layer[i].scaling); + } +} +NvBool UsageBoundsEqual( + const struct NvKmsUsageBounds *a, + const struct NvKmsUsageBounds *b) +{ + NvU32 layer; + + for (layer = 0; layer < ARRAY_LEN(a->layer); layer++) { + if (!nvEvoLayerUsageBoundsEqual(a, b, layer)) { + return FALSE; + } + } + + return TRUE; +} + +NvBool nvAllocatePreFlipBandwidth(NVDevEvoPtr pDevEvo, + struct NvKmsFlipWorkArea *pWorkArea) +{ + NVValidateImpOneDispHeadParamsRec *timingsParams = NULL; + struct NvKmsUsageBounds *currentAndNew = NULL; + struct NvKmsUsageBounds *guaranteedAndCurrent = NULL; + NVDispEvoPtr pDispEvo; + NvU32 head; + NvBool recheckIMP = FALSE; + NvBool ret = TRUE; + + if (!pDevEvo->isSOCDisplay) { + return TRUE; + } + + timingsParams = + nvCalloc(NVKMS_MAX_HEADS_PER_DISP, sizeof(*timingsParams)); + if (timingsParams == NULL) { + return FALSE; + } + + currentAndNew = + nvCalloc(NVKMS_MAX_HEADS_PER_DISP, sizeof(*currentAndNew)); + if (currentAndNew == NULL) { + nvFree(timingsParams); + return FALSE; + } + + guaranteedAndCurrent = + nvCalloc(NVKMS_MAX_HEADS_PER_DISP, sizeof(*guaranteedAndCurrent)); + if (guaranteedAndCurrent == NULL) { + nvFree(timingsParams); + nvFree(currentAndNew); + return FALSE; + } + + pDispEvo = pDevEvo->pDispEvo[0]; + + // SOC Display never has more than one disp + nvAssert(pDevEvo->nDispEvo == 1); + + for (head = 0; head < pDevEvo->numHeads; head++) { + NVDispHeadStateEvoRec *pHeadState = + &pDispEvo->headState[head]; + const struct NvKmsUsageBounds *pCurrent = + &pDevEvo->gpus[0].headState[head].preallocatedUsage; + const struct NvKmsUsageBounds *pNew = + &pWorkArea->sd[0].head[head].newState.usage; + + if (pHeadState->activeRmId == 0) { + continue; + } + + timingsParams[head].pConnectorEvo = pHeadState->pConnectorEvo; + timingsParams[head].activeRmId = pHeadState->activeRmId; + timingsParams[head].pixelDepth = pHeadState->pixelDepth; + timingsParams[head].pTimings = &pHeadState->timings; + timingsParams[head].enableDsc = (pHeadState->dscInfo.type != + NV_DSC_INFO_EVO_TYPE_DISABLED); + timingsParams[head].b2Heads1Or = + (pHeadState->mergeMode != NV_EVO_MERGE_MODE_DISABLED); + + nvUnionUsageBounds(pCurrent, pNew, ¤tAndNew[head]); + nvUnionUsageBounds(&pHeadState->timings.viewPort.guaranteedUsage, + pCurrent, &guaranteedAndCurrent[head]); + + if (!ValidateUsageBounds(pDevEvo, + head, + pNew, + &guaranteedAndCurrent[head])) { + recheckIMP = TRUE; + } + + nvUnionUsageBounds(&guaranteedAndCurrent[head], pNew, + &guaranteedAndCurrent[head]); + timingsParams[head].pUsage = &guaranteedAndCurrent[head]; + } + + if (recheckIMP) { + ret = nvValidateImpOneDisp(pDispEvo, timingsParams, + FALSE /* requireBootClocks */, + NV_EVO_REALLOCATE_BANDWIDTH_MODE_PRE, + NULL /* pMinIsoBandwidthKBPS */, + NULL /* pMinDramFloorKBPS */); + if (ret) { + for (head = 0; head < pDevEvo->numHeads; head++) { + pDevEvo->gpus[0].headState[head].preallocatedUsage = + currentAndNew[head]; + } + } + } + + nvFree(timingsParams); + nvFree(currentAndNew); + nvFree(guaranteedAndCurrent); + + if (ret) { + nvScheduleLowerDispBandwidthTimer(pDevEvo); + } + + return ret; +} + +/*! + * If the satellite channel is active then pre-NVDisplay hardware does not allow + * to change its usage bounds in non-interlock update. The nvSetUsageBoundsEvo() + * code path for pre-NVDisplay hardware, interlocks the satellite channels with + * the usage bounds update. This makes it essential to poll for + * NO_METHOD_PENDING state of the satellite channels, otherwise blocking + * pre-flip IMP update will also get stuck. + * + * It is not possible to interlock flip-locked satellite channels with the core + * channel usage bounds update; in that case, reject the flip. Do not allow + * client to make any change in surface usage bounds parameters without + * deactivating channel first, if channel is flip-locked. + */ +static NvBool PrepareToDoPreFlipIMP(NVDevEvoPtr pDevEvo, + struct NvKmsFlipWorkArea *pWorkArea) +{ + NvU64 startTime = 0; + NvU32 timeout = 2000000; /* 2 seconds */ + NvU32 sd; + + for (sd = 0; sd < pDevEvo->numSubDevices; sd++) { + NVEvoSubDevPtr pEvoSubDev = &pDevEvo->gpus[sd]; + NvU32 head; + + for (head = 0; head < pDevEvo->numHeads; head++) { + NVEvoHeadControlPtr pHC = + &pEvoSubDev->headControl[head]; + const NVEvoSubDevHeadStateRec *pCurrentFlipState = + &pDevEvo->gpus[sd].headState[head]; + const NVSurfaceEvoRec *pCurrentBaseSurf = + pCurrentFlipState->layer[NVKMS_MAIN_LAYER].pSurfaceEvo[NVKMS_LEFT]; + const struct NvKmsUsageBounds *pCurrentUsage = + &pCurrentFlipState->usage; + + NVFlipEvoHwState *pNewFlipState = + &pWorkArea->sd[sd].head[head].newState; + const NVSurfaceEvoRec *pNewBaseSurf = + pNewFlipState->layer[NVKMS_MAIN_LAYER].pSurfaceEvo[NVKMS_LEFT]; + struct NvKmsUsageBounds *pNewUsage = + &pNewFlipState->usage; + + struct NvKmsUsageBounds *pPreFlipUsage = + &pWorkArea->sd[sd].head[head].preFlipUsage; + + NvU32 layer; + + nvUnionUsageBounds(pNewUsage, pCurrentUsage, pPreFlipUsage); + + if (pDevEvo->hal->caps.supportsNonInterlockedUsageBoundsUpdate) { + /* + * NVDisplay does not interlock the satellite channel + * with its usage bounds update. + */ + continue; + } + + /* + * If head is flip-locked then do not change usage + * bounds while base channel is active. + */ + if (pHC->flipLock && + /* If the base channel is active before and after flip then + * current and new base usage bounds should be same. */ + ((pNewBaseSurf != NULL && + pCurrentBaseSurf != NULL && + !nvEvoLayerUsageBoundsEqual(pCurrentUsage, + pNewUsage, NVKMS_MAIN_LAYER)) || + /* If the base channel is active before flip then current and + * preflip base usage bounds should be same. */ + (pCurrentBaseSurf != NULL && + !nvEvoLayerUsageBoundsEqual(pCurrentUsage, + pPreFlipUsage, NVKMS_MAIN_LAYER)))) { + return FALSE; + } + + /* + * Poll for NO_METHOD_PENDING state if usage + * bounds of the channel are changed. + */ + for (layer = 0; layer < pDevEvo->head[head].numLayers; layer++) { + if (!nvEvoLayerUsageBoundsEqual(pCurrentUsage, + pPreFlipUsage, layer) && + !nvEvoPollForNoMethodPending(pDevEvo, + sd, + pDevEvo->head[head].layer[layer], + &startTime, + timeout)) { + return FALSE; + } + } + } + } + + return TRUE; +} + +/*! + * Tasks need to perform before triggering flip, they all should be done here. + * + * If necessary, raise usage bounds and/or disable MidFrameAndDWCFWatermark + * (bug 200508242) in the core channel and do an IMP update. + * + * Note that this function only raises usage bounds and/or disables + * MidFrameAndDWCFWatermark, never lowers usage bounds and/or enables + * MidFrameAndDWCFWatermark. This allows it to run before queuing a flip even + * if there are still pending flips in a base channel. + */ +static void PreFlipIMP(NVDevEvoPtr pDevEvo, + const struct NvKmsFlipWorkArea *pWorkArea) +{ + NvU32 head, sd; + NVDispEvoPtr pDispEvo; + + FOR_ALL_EVO_DISPLAYS(pDispEvo, sd, pDevEvo) { + NVEvoUpdateState updateState = { }; + NvBool update = FALSE; + + for (head = 0; head < pDispEvo->pDevEvo->numHeads; head++) { + const NVFlipEvoHwState *pNewState = + &pWorkArea->sd[sd].head[head].newState; + const struct NvKmsUsageBounds *pPreFlipUsage = + &pWorkArea->sd[sd].head[head].preFlipUsage; + struct NvKmsUsageBounds *pCurrentUsage = + &pDevEvo->gpus[sd].headState[head].usage; + + if (!UsageBoundsEqual(pCurrentUsage, pPreFlipUsage)) { + update |= nvSetUsageBoundsEvo(pDevEvo, sd, head, + pPreFlipUsage, &updateState); + } + + if (!pDevEvo->gpus[sd]. + headState[head].disableMidFrameAndDWCFWatermark && + pNewState->disableMidFrameAndDWCFWatermark) { + + nvEnableMidFrameAndDWCFWatermark(pDevEvo, + sd, + head, + FALSE /* enable */, + &updateState); + update = TRUE; + } + } + + if (update) { + nvDoIMPUpdateEvo(pDispEvo, &updateState); + } + } +} + +static void LowerDispBandwidth(void *dataPtr, NvU32 dataU32) +{ + NVValidateImpOneDispHeadParamsRec timingsParams[NVKMS_MAX_HEADS_PER_DISP]; + struct NvKmsUsageBounds *guaranteedAndCurrent; + NVDevEvoPtr pDevEvo = dataPtr; + NVDispEvoPtr pDispEvo; + NvU32 head; + NvBool ret; + + guaranteedAndCurrent = + nvCalloc(1, sizeof(*guaranteedAndCurrent) * NVKMS_MAX_HEADS_PER_DISP); + if (guaranteedAndCurrent == NULL) { + nvAssert(guaranteedAndCurrent != NULL); + return; + } + + nvkms_memset(&timingsParams, 0, sizeof(timingsParams)); + + pDispEvo = pDevEvo->pDispEvo[0]; + + // SOC Display never has more than one disp + nvAssert(pDevEvo->nDispEvo == 1); + + for (head = 0; head < pDevEvo->numHeads; head++) { + NVDispHeadStateEvoRec *pHeadState = + &pDispEvo->headState[head]; + const struct NvKmsUsageBounds *pGuaranteed = + &pHeadState->timings.viewPort.guaranteedUsage; + const struct NvKmsUsageBounds *pCurrent = + &pDevEvo->gpus[0].headState[head].usage; + + if (pHeadState->activeRmId == 0) { + continue; + } + + timingsParams[head].pConnectorEvo = pHeadState->pConnectorEvo; + timingsParams[head].activeRmId = pHeadState->activeRmId; + timingsParams[head].pixelDepth = pHeadState->pixelDepth; + timingsParams[head].pTimings = &pHeadState->timings; + timingsParams[head].enableDsc = (pHeadState->dscInfo.type != + NV_DSC_INFO_EVO_TYPE_DISABLED); + timingsParams[head].b2Heads1Or = + (pHeadState->mergeMode != NV_EVO_MERGE_MODE_DISABLED); + + nvUnionUsageBounds(pGuaranteed, pCurrent, &guaranteedAndCurrent[head]); + timingsParams[head].pUsage = &guaranteedAndCurrent[head]; + } + + ret = nvValidateImpOneDisp(pDispEvo, timingsParams, + FALSE /* requireBootClocks */, + NV_EVO_REALLOCATE_BANDWIDTH_MODE_POST, + NULL /* pMinIsoBandwidthKBPS */, + NULL /* pMinDramFloorKBPS */); + if (ret) { + for (head = 0; head < pDevEvo->numHeads; head++) { + pDevEvo->gpus[0].headState[head].preallocatedUsage = + pDevEvo->gpus[0].headState[head].usage; + } + } + + nvAssert(ret); + + nvFree(guaranteedAndCurrent); +} + +void nvCancelLowerDispBandwidthTimer(NVDevEvoPtr pDevEvo) +{ + nvkms_free_timer(pDevEvo->lowerDispBandwidthTimer); + pDevEvo->lowerDispBandwidthTimer = NULL; +} + +void nvScheduleLowerDispBandwidthTimer(NVDevEvoPtr pDevEvo) +{ + nvAssert(pDevEvo->isSOCDisplay); + + nvCancelLowerDispBandwidthTimer(pDevEvo); + + pDevEvo->lowerDispBandwidthTimer = + nvkms_alloc_timer(LowerDispBandwidth, + pDevEvo, + 0, /* dataU32 */ + 30000000 /* 30 seconds */); +} + +/*! + * Check whether the core, base, and overlay channels are idle (i.e. no methods + * pending in the corresponding pushbuffer) and lower the usage bounds if + * possible. + */ +static NvBool TryLoweringUsageBoundsOneHead(NVDevEvoPtr pDevEvo, NvU32 sd, + NvU32 head, + NVEvoUpdateState *updateState) +{ + const NVEvoSubDevHeadStateRec *pHeadState = + &pDevEvo->gpus[sd].headState[head]; + const struct NvKmsUsageBounds *pCurrent = &pHeadState->usage; + const struct NvKmsUsageBounds *pTarget = &pHeadState->targetUsage; + struct NvKmsUsageBounds newUsage = *pCurrent; + NvBool changed = FALSE; + NvBool scheduleLater = FALSE; + int i; + + for (i = 0; i < pDevEvo->head[head].numLayers; i++) { + if (pCurrent->layer[i].usable && !pTarget->layer[i].usable) { + NvBool isMethodPending; + + if (pDevEvo->hal->IsChannelMethodPending( + pDevEvo, + pDevEvo->head[head].layer[i], + sd, + &isMethodPending) && !isMethodPending) { + newUsage.layer[i] = pTarget->layer[i]; + changed = TRUE; + } else { + scheduleLater = TRUE; + } + } else if ((pCurrent->layer[i].usable && pTarget->layer[i].usable) && + ((pCurrent->layer[i].supportedSurfaceMemoryFormats != + pTarget->layer[i].supportedSurfaceMemoryFormats) || + (!nvEvoScalingUsageBoundsEqual(&pCurrent->layer[i].scaling, + &pTarget->layer[i].scaling)))) { + NvBool isMethodPending; + + if (pDevEvo->hal->IsChannelMethodPending( + pDevEvo, + pDevEvo->head[head].layer[i], + sd, + &isMethodPending) && !isMethodPending) { + newUsage.layer[i] = pTarget->layer[i]; + changed = TRUE; + } else { + scheduleLater = TRUE; + } + } + } + + if (scheduleLater) { + SchedulePostFlipIMPTimer(pDevEvo); + } + + if (changed) { + changed = nvSetUsageBoundsEvo(pDevEvo, sd, head, &newUsage, + updateState); + } + + return changed; +} + +static NvBool +TryEnablingMidFrameAndDWCFWatermarkOneHead(NVDevEvoPtr pDevEvo, + NvU32 sd, + NvU32 head, + NVEvoUpdateState *updateState) +{ + const NVEvoSubDevHeadStateRec *pHeadState = + &pDevEvo->gpus[sd].headState[head]; + NvBool changed = FALSE; + + if (pHeadState->disableMidFrameAndDWCFWatermark && + !pHeadState->targetDisableMidFrameAndDWCFWatermark) { + + NvBool isIdle; + + if (pDevEvo->hal->IsChannelIdle(pDevEvo, + pDevEvo->head[head].layer[NVKMS_MAIN_LAYER], + sd, + &isIdle) && isIdle) { + nvEnableMidFrameAndDWCFWatermark(pDevEvo, + sd, + head, + TRUE /* enable */, + updateState); + changed = TRUE; + } else { + // Schedule another timer to try again later. + SchedulePostFlipIMPTimer(pDevEvo); + } + } + + return changed; +} + +static void +TryToDoPostFlipIMP(void *dataPtr, NvU32 dataU32) +{ + NVDevEvoPtr pDevEvo = dataPtr; + NvU32 head, sd; + NVDispEvoPtr pDispEvo; + + pDevEvo->postFlipIMPTimer = NULL; + + FOR_ALL_EVO_DISPLAYS(pDispEvo, sd, pDevEvo) { + NVEvoUpdateState updateState = { }; + NvBool update = FALSE; + + for (head = 0; head < pDispEvo->pDevEvo->numHeads; head++) { + if (TryLoweringUsageBoundsOneHead(pDevEvo, sd, head, + &updateState)) { + update = TRUE; + } + + if (TryEnablingMidFrameAndDWCFWatermarkOneHead( + pDevEvo, + sd, + head, + &updateState)) { + update = TRUE; + } + } + + if (update) { + nvDoIMPUpdateEvo(pDispEvo, &updateState); + } + } +} + +static void SchedulePostFlipIMPTimer(NVDevEvoPtr pDevEvo) +{ + if (!pDevEvo->postFlipIMPTimer) { + pDevEvo->postFlipIMPTimer = + nvkms_alloc_timer( + TryToDoPostFlipIMP, + pDevEvo, + 0, /* dataU32 */ + 10000000 /* 10 seconds */); + } +} + +void nvEvoCancelPostFlipIMPTimer(NVDevEvoPtr pDevEvo) +{ + nvkms_free_timer(pDevEvo->postFlipIMPTimer); + pDevEvo->postFlipIMPTimer = NULL; +} + +/*! + * If necessary, schedule a timer to see if usage bounds can be lowered. + */ +static void SchedulePostFlipIMP(NVDevEvoPtr pDevEvo) +{ + NvU32 head, sd; + NVDispEvoPtr pDispEvo; + + // If a timer is already scheduled, do nothing. + if (pDevEvo->postFlipIMPTimer) { + return; + } + + FOR_ALL_EVO_DISPLAYS(pDispEvo, sd, pDevEvo) { + for (head = 0; head < pDispEvo->pDevEvo->numHeads; head++) { + const NVEvoSubDevHeadStateRec *pHeadState = + &pDevEvo->gpus[sd].headState[head]; + + if (!UsageBoundsEqual(&pHeadState->usage, + &pHeadState->targetUsage) || + (pHeadState->disableMidFrameAndDWCFWatermark != + pHeadState->targetDisableMidFrameAndDWCFWatermark)) { + + SchedulePostFlipIMPTimer(pDevEvo); + return; + } + } + } +} + +static void SkipLayerPendingFlips(NVDevEvoRec *pDevEvo, + const NvBool trashPendingMethods, + const NvBool unblockMethodsInExecutation, + struct NvKmsFlipWorkArea *pWorkArea) +{ + NvU64 startTime = 0; + const NvU32 timeout = 2000000; /* 2 seconds */ + struct { + struct { + struct { + NvU32 oldAccelMask; + } head[NVKMS_MAX_HEADS_PER_DISP]; + } sd[NVKMS_MAX_SUBDEVICES]; + } accelState = { }; + NvU32 sd, head; + + for (sd = 0; sd < pDevEvo->numSubDevices; sd++) { + if (!pWorkArea->sd[sd].changed) { + continue; + } + + for (head = 0; head < NVKMS_MAX_HEADS_PER_DISP; head++) { + const NVFlipEvoHwState *pFlipState = + &pWorkArea->sd[sd].head[head].newState; + + if (!pFlipState->skipLayerPendingFlips[NVKMS_MAIN_LAYER]|| + !pFlipState->dirty.layer[NVKMS_MAIN_LAYER]) { + continue; + } + + pDevEvo->hal->AccelerateChannel( + pDevEvo, + pDevEvo->head[head].layer[NVKMS_MAIN_LAYER], + sd, + trashPendingMethods, + unblockMethodsInExecutation, + &accelState.sd[sd].head[head].oldAccelMask); + } + } + + for (sd = 0; sd < pDevEvo->numSubDevices; sd++) { + if (!pWorkArea->sd[sd].changed) { + continue; + } + + for (head = 0; head < NVKMS_MAX_HEADS_PER_DISP; head++) { + const NVFlipEvoHwState *pFlipState = + &pWorkArea->sd[sd].head[head].newState; + + if (!pFlipState->skipLayerPendingFlips[NVKMS_MAIN_LAYER] || + !pFlipState->dirty.layer[NVKMS_MAIN_LAYER]) { + continue; + } + + if (unblockMethodsInExecutation) { + if (!nvEvoPollForNoMethodPending(pDevEvo, + sd, + pDevEvo->head[head].layer[NVKMS_MAIN_LAYER], + &startTime, + timeout)) { + nvAssert(!"Failed to idle the main layer channel"); + } + } else { + if (!nvEvoPollForEmptyChannel(pDevEvo->head[head].layer[NVKMS_MAIN_LAYER], + sd, + &startTime, + timeout)) { + nvAssert(!"Failed to empty the main layer channel"); + } + } + + pDevEvo->hal->ResetChannelAccelerators( + pDevEvo, + pDevEvo->head[head].layer[NVKMS_MAIN_LAYER], + sd, + trashPendingMethods, + unblockMethodsInExecutation, + accelState.sd[sd].head[head].oldAccelMask); + } + } +} + +void nvPreFlip(NVDevEvoRec *pDevEvo, + struct NvKmsFlipWorkArea *pWorkArea, + const NvBool applyAllowVrr, + const NvBool allowVrr, + const NvBool skipUpdate) +{ + NvU32 sd, head; + NVDispEvoRec *pDispEvo; + + for (sd = 0; sd < pDevEvo->numSubDevices; sd++) { + + if (!pWorkArea->sd[sd].changed) { + continue; + } + + for (head = 0; head < NVKMS_MAX_HEADS_PER_DISP; head++) { + // Increase refCnt of surfaces used AFTER flip + nvUpdateSurfacesFlipRefCount( + pDevEvo, + head, + &pWorkArea->sd[sd].head[head].newState, + NV_TRUE); + + nvRefTmoLutSurfacesEvo( + pDevEvo, + &pWorkArea->sd[sd].head[head].newState, + head); + } + } + + PreFlipIMP(pDevEvo, pWorkArea); + + if (!skipUpdate) { + /* Trash flips pending in channel which are not yet in execution */ + SkipLayerPendingFlips(pDevEvo, TRUE /* trashPendingMethods */, + FALSE /* unblockMethodsInExecutation */, + pWorkArea); + } + + if (applyAllowVrr) { + nvSetVrrActive(pDevEvo, allowVrr); + } + + /* + * Update flip metering for Frame pacing smoothing/frame splitting for direct + * drive and adaptive sync VRR, and override the flip timestamp if + * necessary. + */ + FOR_ALL_EVO_DISPLAYS(pDispEvo, sd, pDevEvo) { + for (NvU32 inputHead = 0; inputHead < pDevEvo->numHeads; inputHead++) { + const NVDispHeadStateEvoRec *pInputHeadState = + &pDispEvo->headState[inputHead]; + const struct NvKmsVrrFramePacingInfo *pInputVrrFramePacingInfo = + &pInputHeadState->vrrFramePacingInfo; + const NvU32 headsMask = pInputHeadState->mergeModeVrrSecondaryHeadMask | + NVBIT(inputHead); + + /* + * XXX[2Heads1OR] Implement per api-head frame pacing and remove this + * mergeMode check and NVDispEvoRec::mergeModeVrrSecondaryHeadMask. + */ + if (pInputHeadState->mergeMode == NV_EVO_MERGE_MODE_SECONDARY) { + continue; + } + +#if defined(DEBUG) + FOR_EACH_EVO_HW_HEAD_IN_MASK(headsMask, head) { + const NVFlipEvoHwState *pInputHeadNewState = + &pWorkArea->sd[sd].head[inputHead].newState; + const NVFlipEvoHwState *pNewState = + &pWorkArea->sd[sd].head[head].newState; + + nvAssert(pNewState->dirty.layer[NVKMS_MAIN_LAYER] == + pInputHeadNewState->dirty.layer[NVKMS_MAIN_LAYER]); + } +#endif + + FOR_EACH_EVO_HW_HEAD_IN_MASK(headsMask, head) { + NVFlipEvoHwState *pNewState = + &pWorkArea->sd[sd].head[head].newState; + if (pNewState->dirty.layer[NVKMS_MAIN_LAYER]) { + nvTrackAndDelayFlipForVrrSwFramePacing(pDispEvo, + pInputVrrFramePacingInfo, + &pNewState->layer[NVKMS_MAIN_LAYER]); + } + } + } + } +} + +void nvPostFlip(NVDevEvoRec *pDevEvo, + struct NvKmsFlipWorkArea *pWorkArea, + const NvBool skipUpdate, + const NvBool applyAllowVrr, + NvS32 *pVrrSemaphoreIndex) +{ + NvU32 sd, head; + + if (!skipUpdate) { + /* Unblock flips which are stuck in execution */ + SkipLayerPendingFlips(pDevEvo, FALSE /* trashPendingMethods */, + TRUE /* unblockMethodsInExecutation */, + pWorkArea); + } + + if (applyAllowVrr) { + *pVrrSemaphoreIndex = nvIncVrrSemaphoreIndex(pDevEvo); + } else { + // TODO Schedule vrr unstall; per-disp/per-device? + } + + for (sd = 0; sd < pDevEvo->numSubDevices; sd++) { + if (!pWorkArea->sd[sd].changed) { + continue; + } + + for (head = 0; head < NVKMS_MAX_HEADS_PER_DISP; head++) { + // Decrease refCnt of surfaces used BEFORE the flip + nvUpdateSurfacesFlipRefCount( + pDevEvo, + head, + &pWorkArea->sd[sd].head[head].oldState, + NV_FALSE); + + nvUnrefTmoLutSurfacesEvo( + pDevEvo, + &pWorkArea->sd[sd].head[head].oldState, + head); + } + } + + if (!skipUpdate) { + // Note that usage bounds are not lowered here, because the flip + // queued by this function may not occur until later. Instead, schedule + // a timer for later to check if the usage bounds can be lowered. + SchedulePostFlipIMP(pDevEvo); + + pDevEvo->skipConsoleRestore = FALSE; + } +} + +NvBool nvPrepareToDoPreFlip(NVDevEvoRec *pDevEvo, + struct NvKmsFlipWorkArea *pWorkArea) +{ + if (!RegisterPreSyncpt(pDevEvo, pWorkArea)) { + return FALSE; + } + + if (!PrepareToDoPreFlipIMP(pDevEvo, pWorkArea)) { + return FALSE; + } + + return TRUE; +} + +NvBool nvAssignNVFlipEvoHwState(NVDevEvoRec *pDevEvo, + const struct NvKmsPerOpenDev *pOpenDev, + const NvU32 sd, + const NvU32 head, + const struct NvKmsFlipCommonParams *pParams, + const NvBool allowVrr, + NVFlipEvoHwState *pFlipHwState) +{ + const NVDispEvoRec *pDispEvo = pDevEvo->gpus[sd].pDispEvo; + const NVDispHeadStateEvoRec *pHeadState = &pDispEvo->headState[head]; + const struct NvKmsUsageBounds *pPossibleUsage = + &pHeadState->timings.viewPort.possibleUsage; + + if (!nvUpdateFlipEvoHwState(pOpenDev, pDevEvo, sd, head, pParams, + &pHeadState->timings, pHeadState->tilePosition, + pFlipHwState, allowVrr)) { + return FALSE; + } + + nvOverrideScalingUsageBounds(pDevEvo, head, pFlipHwState, pPossibleUsage); + + if (!nvValidateFlipEvoHwState(pDevEvo, head, &pHeadState->timings, + pFlipHwState)) { + return FALSE; + } + + if (!nvSetTmoLutSurfacesEvo(pDevEvo, pFlipHwState, head)) { + return FALSE; + } + + return TRUE; +} + +/*! + * Wait for idle on a set of the main layer channels. + * + * \param[in,out] pDevEvo The device. + * \param[in] idleChannelMaskPerSd The channel masks per subdevice that + * we should wait to be idle. + * \param[in] allowForceIdle Whether we should force idle a channel + * or just assert if the idle times out. + */ +void nvIdleMainLayerChannels( + NVDevEvoPtr pDevEvo, + const NVEvoChannelMask *idleChannelMaskPerSd, + NvBool allowStopBase) +{ + NvU64 startTime = 0; + NvBool allChannelsIdle = FALSE; + NVDispEvoPtr pDispEvo; + NvU32 dispIndex, head; + NVEvoChannelMask busyChannelMaskPerSd[NVKMS_MAX_SUBDEVICES] = { }; + + /* + * Wait up to 2 seconds for all channels to be idle, and gather a list of + * all busy channels. + */ + while (!allChannelsIdle) { + + const NvU32 timeout = 2000000; /* 2 seconds */ + NvBool anyChannelBusy = FALSE; + + FOR_ALL_EVO_DISPLAYS(pDispEvo, dispIndex, pDevEvo) { + for (head = 0; head < pDevEvo->numHeads; head++) { + NVEvoChannelPtr pMainLayerChannel = + pDevEvo->head[head].layer[NVKMS_MAIN_LAYER]; + if (idleChannelMaskPerSd[pDispEvo->displayOwner] & + pMainLayerChannel->channelMask) { + + NvBool isMethodPending = FALSE; + if (!pDevEvo->hal->IsChannelMethodPending( + pDevEvo, + pMainLayerChannel, + pDispEvo->displayOwner, + &isMethodPending) + || isMethodPending) { + + /* Mark this channel as busy. */ + busyChannelMaskPerSd[pDispEvo->displayOwner] |= + pMainLayerChannel->channelMask; + anyChannelBusy = TRUE; + } else { + /* + * Mark this channel as no longer busy, in case its + * flip completed while we were waiting on another + * channel. + */ + busyChannelMaskPerSd[pDispEvo->displayOwner] &= + ~pMainLayerChannel->channelMask; + } + } + } + } + + if (!anyChannelBusy) { + allChannelsIdle = TRUE; + break; + } + + /* Break out of the loop if we exceed the timeout. */ + if (nvExceedsTimeoutUSec(&startTime, timeout)) { + break; + } + + nvkms_yield(); + } + + if (!allChannelsIdle) { + /* + * At least one channel was still idle after the 2 second timeout + * above. + */ + if (!allowStopBase) { + /* + * The caller of this function expected this wait for idle not to + * time out. + */ + nvEvoLogDev(pDevEvo, EVO_LOG_WARN, + "Timeout while waiting for idle."); + } else { + /* + * Idle all base channels that were still busy when the wait above + * timed out. + */ + NVEvoIdleChannelState idleChannelState = { }; + + FOR_ALL_EVO_DISPLAYS(pDispEvo, dispIndex, pDevEvo) { + idleChannelState.subdev[pDispEvo->displayOwner].channelMask = + busyChannelMaskPerSd[pDispEvo->displayOwner]; + } + + pDevEvo->hal->ForceIdleSatelliteChannelIgnoreLock( + pDevEvo, &idleChannelState); + } + } +} + +NvBool nvNeedToToggleFlipLock(const NVDispEvoRec *pDispEvo, + const NvU32 head, const NvBool enable) +{ + const NVDevEvoRec *pDevEvo = pDispEvo->pDevEvo; + const NVEvoSubDevPtr pEvoSubDev = &pDevEvo->gpus[pDispEvo->displayOwner]; + const NVEvoHeadControlPtr pHC = &pEvoSubDev->headControl[head]; + NvBool needToToggle = FALSE; + + if (!enable && pHC->flipLock) { + /* + * This channel is currently using fliplock in the config that + * is being torn down; idle its base channel and disable + * fliplock. + */ + needToToggle = TRUE; + } + + if (enable && ((pHC->serverLock != NV_EVO_NO_LOCK) || + (pHC->clientLock != NV_EVO_NO_LOCK))) { + /* + * This channel will be using fliplock for swap groups in the + * new config; idle its base channel and enable fliplock. + */ + nvAssert(!HEAD_MASK_QUERY(pEvoSubDev->flipLockProhibitedHeadMask, + head)); + needToToggle = TRUE; + } + + return needToToggle; +} + +void nvToggleFlipLockPerDisp(NVDispEvoRec *pDispEvo, const NvU32 headMask, + const NvBool enable) +{ + NvU32 head; + NVEvoUpdateState updateState = { }; + const NVDevEvoRec *pDevEvo = pDispEvo->pDevEvo; + + for (head = 0; head < pDevEvo->numHeads; head++) { + if ((headMask & NVBIT(head)) != 0x0) { + NvU32 setEnable = enable; + + if (!nvUpdateFlipLockEvoOneHead(pDispEvo, head, &setEnable, + TRUE /* set */, + NULL /* needsEarlyUpdate */, + &updateState)) { + nvEvoLogDev(pDevEvo, EVO_LOG_WARN, + "Failed to toggle fliplock for swapgroups."); + } + } + } + + if (!nvIsUpdateStateEmpty(pDevEvo, &updateState)) { + nvEvoUpdateAndKickOff(pDispEvo, TRUE, &updateState, + TRUE /* releaseElv */); + } +} diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia-modeset/src/nvkms-hw-states.c nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia-modeset/src/nvkms-hw-states.c --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia-modeset/src/nvkms-hw-states.c 2023-10-25 20:22:40.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia-modeset/src/nvkms-hw-states.c 2024-03-05 22:12:22.000000000 +0000 @@ -245,6 +245,28 @@ * change the pin here, prior to enabling flip lock. */ +NvBool nvEvoLockHWStateNoChange(NVDispEvoPtr pDispEvo, NVEvoSubDevPtr pEvoSubDev, + const NvU32 *pHeads) +{ + return TRUE; +} + +NvBool nvEvoLockHWStateMergeMode(NVDispEvoPtr pDispEvo, NVEvoSubDevPtr pEvoSubDev, + const NvU32 *pHeads) +{ + unsigned int i; + + nvAssert(pHeads != NULL && pHeads[0] != NV_INVALID_HEAD); + + for (i = 0; pHeads[i] != NV_INVALID_HEAD; i++) { + const int head = pHeads[i]; + NVEvoHeadControlPtr pHC = &pEvoSubDev->headControlAssy[head]; + pHC->mergeMode = TRUE; + } + + return TRUE; +} + NvBool nvEvoLockHWStateNoLock(NVDispEvoPtr pDispEvo, NVEvoSubDevPtr pEvoSubDev, const NvU32 *pHeads) { @@ -262,6 +284,11 @@ pHC->clientLock = NV_EVO_NO_LOCK; pHC->clientLockPin = NV_EVO_LOCK_PIN_INTERNAL(0); pHC->clientLockoutWindow = 0; + pHC->mergeMode = FALSE; + pHC->setLockOffsetX = FALSE; + pHC->useStallLockPin = FALSE; + pHC->stallLockPin = NV_EVO_LOCK_PIN_INTERNAL(0); + pHC->crashLockUnstallMode = FALSE; /* Reset the flip lock pin to internal, if not needed for SLI */ if (!HEAD_MASK_QUERY(pEvoSubDev->flipLockPinSetForSliHeadMask, head)) { diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia-modeset/src/nvkms-lut.c nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia-modeset/src/nvkms-lut.c --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia-modeset/src/nvkms-lut.c 2023-10-25 20:22:40.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia-modeset/src/nvkms-lut.c 2024-03-05 22:12:22.000000000 +0000 @@ -40,6 +40,15 @@ pDevEvo = pSurfEvo->pDevEvo; + if (pSurfEvo->gpuAddress) { + nvRmApiUnmapMemoryDma(nvEvoGlobal.clientHandle, + pDevEvo->deviceHandle, + pDevEvo->nvkmsGpuVASpace, + pSurfEvo->handle, + 0, + (NvU64)pSurfEvo->gpuAddress); + } + nvRmEvoUnMapVideoMemory(pDevEvo, pSurfEvo->handle, pSurfEvo->subDeviceAddress); @@ -141,6 +150,24 @@ goto fail; } + /* + * The GPU mapping is only needed for prefetching LUT surfaces for DIFR. + * It isn't worth failing alone but we want to keep gpuAddress coherent. + */ + ret = nvRmApiMapMemoryDma(nvEvoGlobal.clientHandle, + pDevEvo->deviceHandle, + pDevEvo->nvkmsGpuVASpace, + pSurfEvo->handle, + 0, + pSurfEvo->size, + DRF_DEF(OS46, _FLAGS, _CACHE_SNOOP, _ENABLE) | + DRF_DEF(OS46, _FLAGS, _ACCESS, _READ_ONLY), + &pSurfEvo->gpuAddress); + + if (ret != NVOS_STATUS_SUCCESS) { + pSurfEvo->gpuAddress = 0ULL; + } + return pSurfEvo; fail: @@ -358,13 +385,13 @@ NvBool nvAllocLutSurfacesEvo(NVDevEvoPtr pDevEvo) { NVDispEvoPtr pDispEvo; - NvU32 head, dispIndex, i, sd; + NvU32 apiHead, dispIndex, i, sd; - for (head = 0; head < pDevEvo->numHeads; head++) { - for (i = 0; i < ARRAY_LEN(pDevEvo->lut.head[head].LUT); i++) { - pDevEvo->lut.head[head].LUT[i] = AllocLutSurfaceEvo(pDevEvo); + for (apiHead = 0; apiHead < pDevEvo->numApiHeads; apiHead++) { + for (i = 0; i < ARRAY_LEN(pDevEvo->lut.apiHead[apiHead].LUT); i++) { + pDevEvo->lut.apiHead[apiHead].LUT[i] = AllocLutSurfaceEvo(pDevEvo); - if (pDevEvo->lut.head[head].LUT[i] == NULL) { + if (pDevEvo->lut.apiHead[apiHead].LUT[i] == NULL) { nvFreeLutSurfacesEvo(pDevEvo); return FALSE; } @@ -372,9 +399,9 @@ FOR_ALL_EVO_DISPLAYS(pDispEvo, dispIndex, pDevEvo) { // No palette has been loaded yet, so disable the LUT. - pDevEvo->lut.head[head].disp[dispIndex].waitForPreviousUpdate = FALSE; - pDevEvo->lut.head[head].disp[dispIndex].curBaseLutEnabled = FALSE; - pDevEvo->lut.head[head].disp[dispIndex].curOutputLutEnabled = FALSE; + pDevEvo->lut.apiHead[apiHead].disp[dispIndex].waitForPreviousUpdate = FALSE; + pDevEvo->lut.apiHead[apiHead].disp[dispIndex].curBaseLutEnabled = FALSE; + pDevEvo->lut.apiHead[apiHead].disp[dispIndex].curOutputLutEnabled = FALSE; } } @@ -399,13 +426,13 @@ void nvFreeLutSurfacesEvo(NVDevEvoPtr pDevEvo) { - NvU32 head, i, dispIndex; + NvU32 head, i, dispIndex, apiHead; NVDispEvoPtr pDispEvo; /* Cancel any queued LUT update timers */ FOR_ALL_EVO_DISPLAYS(pDispEvo, dispIndex, pDevEvo) { - for (head = 0; head < pDevEvo->numHeads; head++) { - nvCancelLutUpdateEvo(pDispEvo, head); + for (apiHead = 0; apiHead < pDevEvo->numApiHeads; apiHead++) { + nvCancelLutUpdateEvo(pDispEvo, apiHead); } } @@ -414,16 +441,25 @@ nvRMSyncEvoChannel(pDevEvo, pDevEvo->core, __LINE__); } + /* Clear the current lut surface stored in the hardware head state */ + FOR_ALL_EVO_DISPLAYS(pDispEvo, dispIndex, pDevEvo) { + for (head = 0; head < pDevEvo->numHeads; head++) { + pDispEvo->headState[head].lut.pCurrSurface = NULL; + pDispEvo->headState[head].lut.baseLutEnabled = FALSE; + pDispEvo->headState[head].lut.outputLutEnabled = FALSE; + } + } + if (pDevEvo->lut.defaultLut != NULL) { FreeLutSurfaceEvo(pDevEvo->lut.defaultLut); pDevEvo->lut.defaultLut = NULL; } - for (head = 0; head < pDevEvo->numHeads; head++) { - for (i = 0; i < ARRAY_LEN(pDevEvo->lut.head[head].LUT); i++) { - if (pDevEvo->lut.head[head].LUT[i] != NULL) { - FreeLutSurfaceEvo(pDevEvo->lut.head[head].LUT[i]); - pDevEvo->lut.head[head].LUT[i] = NULL; + for (apiHead = 0; apiHead < pDevEvo->numApiHeads; apiHead++) { + for (i = 0; i < ARRAY_LEN(pDevEvo->lut.apiHead[apiHead].LUT); i++) { + if (pDevEvo->lut.apiHead[apiHead].LUT[i] != NULL) { + FreeLutSurfaceEvo(pDevEvo->lut.apiHead[apiHead].LUT[i]); + pDevEvo->lut.apiHead[apiHead].LUT[i] = NULL; } } } diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia-modeset/src/nvkms-modepool.c nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia-modeset/src/nvkms-modepool.c --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia-modeset/src/nvkms-modepool.c 2023-10-25 20:22:40.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia-modeset/src/nvkms-modepool.c 2024-03-05 22:12:22.000000000 +0000 @@ -1235,7 +1235,7 @@ NvU32 maxPixelClockKHz = pDpyEvo->maxPixelClockKHz; NvU32 realPixelClock = HzToKHz(pModeTimings->pixelClockHz); - if (pModeTimings->yuv420Mode == NV_YUV420_MODE_SW) { + if (pModeTimings->yuv420Mode != NV_YUV420_MODE_NONE) { realPixelClock /= 2; } @@ -1275,7 +1275,7 @@ if ((overrides & NVKMS_MODE_VALIDATION_NO_EDID_MAX_PCLK_CHECK) == 0) { NvU32 realPixelClock = HzToKHz(pModeTimings->pixelClockHz); - if (pModeTimings->yuv420Mode == NV_YUV420_MODE_SW) { + if (pModeTimings->yuv420Mode != NV_YUV420_MODE_NONE) { realPixelClock /= 2; } @@ -1557,28 +1557,51 @@ * particular ViewPort. */ -static void LogViewPort(NVEvoInfoStringPtr pInfoString, - const NVHwModeTimingsEvo *pTimings) +static +void LogViewPort(NVEvoInfoStringPtr pInfoString, + const NVHwModeTimingsEvo timings[NVKMS_MAX_HEADS_PER_DISP], + const NvU32 numHeads) { - const NVHwModeViewPortEvo *pViewPort = &pTimings->viewPort; - const struct NvKmsRect viewPortOut = nvEvoViewPortOutClientView(pTimings); + NvU32 head; + char str[64] = { }, *s = NULL; - /* print the viewport name, size, and taps */ + nvAssert(numHeads <= 2); nvEvoLogInfoString(pInfoString, - "Viewport %dx%d+%d+%d", - viewPortOut.width, - viewPortOut.height, - viewPortOut.x, - viewPortOut.y); + "DualHead Mode: %s", (numHeads > 1) ? "Yes" : "No"); + + /* print the viewport name, size, and taps */ + nvkms_memset(str, 0, sizeof(str)); + for (head = 0, s = str; head < numHeads; head++) { + const struct NvKmsRect viewPortOut = + nvEvoViewPortOutClientView(&timings[head]); + size_t n = str + sizeof(str) - s; + s += nvkms_snprintf(s, n, "%s%dx%d+%d+%d", (s != str) ? ", " : "", + viewPortOut.width, viewPortOut.height, + viewPortOut.x, viewPortOut.x); + } + nvEvoLogInfoString(pInfoString, + "Viewport %s", str); + nvkms_memset(str, 0, sizeof(str)); + for (head = 0, s = str; head < numHeads; head++) { + const NVHwModeViewPortEvo *pViewPort = &timings[head].viewPort; + size_t n = str + sizeof(str) - s; + s += nvkms_snprintf(s, n, "%s%d", (s != str) ? ", " : "", + NVEvoScalerTapsToNum(pViewPort->hTaps)); + } nvEvoLogInfoString(pInfoString, - " Horizontal Taps %d", - NVEvoScalerTapsToNum(pViewPort->hTaps)); + " Horizontal Taps %s", str); + nvkms_memset(str, 0, sizeof(str)); + for (head = 0, s = str; head < numHeads; head++) { + const NVHwModeViewPortEvo *pViewPort = &timings[head].viewPort; + size_t n = str + sizeof(str) - s; + s += nvkms_snprintf(s, n, "%s%d", (s != str) ? ", " : "", + NVEvoScalerTapsToNum(pViewPort->vTaps)); + } nvEvoLogInfoString(pInfoString, - " Vertical Taps %d", - NVEvoScalerTapsToNum(pViewPort->hTaps)); + " Vertical Taps %s", str); } /* @@ -1598,16 +1621,34 @@ const NvModeTimings *pModeTimings = &pKmsMode->timings; NVDispEvoPtr pDispEvo = pDpyEvo->pDispEvo; NVDevEvoRec *pDevEvo = pDispEvo->pDevEvo; - + NvBool b2Heads1Or = FALSE; char localModeName[NV_MAX_MODE_NAME_LEN]; NVHwModeTimingsEvo *pTimingsEvo = nvPreallocGet(pDevEvo, PREALLOC_TYPE_VALIDATE_MODE_HW_MODE_TIMINGS, sizeof(*pTimingsEvo)); - + HDMI_FRL_CONFIG *pHdmiFrlConfig = + nvPreallocGet(pDevEvo, + PREALLOC_TYPE_VALIDATE_MODE_HDMI_FRL_CONFIG, + sizeof(*pHdmiFrlConfig)); + NVDscInfoEvoRec *pDscInfo = + nvPreallocGet(pDevEvo, + PREALLOC_TYPE_VALIDATE_MODE_DSC_INFO, + sizeof(*pDscInfo)); + NVHwModeTimingsEvo *impOutTimings = + nvPreallocGet(pDevEvo, + PREALLOC_TYPE_VALIDATE_MODE_IMP_OUT_HW_MODE_TIMINGS, + sizeof(*impOutTimings) * + NVKMS_MAX_HEADS_PER_DISP); + NvU32 impOutNumHeads = 0x0; + NvU32 head; NvBool ret = FALSE; + const NVColorFormatInfoRec supportedColorFormats = nvGetColorFormatInfo(pDpyEvo); + enum NvKmsDpyAttributeCurrentColorSpaceValue colorSpace; + enum NvKmsDpyAttributeColorBpcValue colorBpc; + if (modeName[0] == '\0') { nvBuildModeName(pModeTimings->hVisible, pModeTimings->vVisible, localModeName, sizeof(localModeName)); @@ -1617,6 +1658,9 @@ /* Initialize the EVO hwModeTimings structure */ nvkms_memset(pTimingsEvo, 0, sizeof(*pTimingsEvo)); + nvkms_memset(pHdmiFrlConfig, 0, sizeof(*pHdmiFrlConfig)); + nvkms_memset(pDscInfo, 0, sizeof(*pDscInfo)); + nvkms_memset(impOutTimings, 0, sizeof(*impOutTimings) * NVKMS_MAX_HEADS_PER_DISP); /* begin logging of ModeValidation for this mode */ @@ -1659,12 +1703,39 @@ goto done; } - if (!nvDPValidateModeEvo(pDpyEvo, pTimingsEvo, pParams)) { - LogModeValidationEnd(pDispEvo, - pInfoString, "DP Bandwidth check failed"); + b2Heads1Or = nvEvoUse2Heads1OR(pDpyEvo, pTimingsEvo, pParams); + + if (pTimingsEvo->yuv420Mode != NV_YUV420_MODE_NONE) { + colorSpace = NV_KMS_DPY_ATTRIBUTE_CURRENT_COLOR_SPACE_YCbCr420; + colorBpc = NV_KMS_DPY_ATTRIBUTE_CURRENT_COLOR_BPC_8; + } else if (!nvGetDefaultColorSpace(&supportedColorFormats, &colorSpace, + &colorBpc)) { + LogModeValidationEnd(pDispEvo, pInfoString, + "Failed to get default color space and Bpc"); goto done; } + if (nvDpyIsHdmiEvo(pDpyEvo)) { + if (!nvHdmiFrlQueryConfig(pDpyEvo, + &pKmsMode->timings, + pTimingsEvo, + b2Heads1Or, + pParams, + pHdmiFrlConfig, + pDscInfo)) { + LogModeValidationEnd(pDispEvo, pInfoString, + "Unable to determine HDMI 2.1 Fixed Rate Link configuration."); + goto done; + } + } else { + if (!nvDPValidateModeEvo(pDpyEvo, pTimingsEvo, &colorSpace, &colorBpc, + b2Heads1Or, pDscInfo, pParams)) { + LogModeValidationEnd(pDispEvo, + pInfoString, "DP Bandwidth check failed"); + goto done; + } + } + /* * Check ViewPortIn dimensions and ensure valid h/vTaps can be assigned. */ @@ -1677,22 +1748,50 @@ /* Run the raster timings through IMP checking. */ - if (!nvConstructHwModeTimingsImpCheckEvo(pDpyEvo->pConnectorEvo, - pTimingsEvo, pParams, pInfoString, - 0 /* head */)) { + pTimingsEvo, + (pDscInfo->type != + NV_DSC_INFO_EVO_TYPE_DISABLED), + b2Heads1Or, + colorSpace, + colorBpc, + pParams, + impOutTimings, + &impOutNumHeads, + pInfoString)) { LogModeValidationEnd(pDispEvo, pInfoString, "GPU extended capability check failed"); goto done; } + nvAssert(impOutNumHeads > 0); + /* Log modevalidation information about the viewport. */ - LogViewPort(pInfoString, pTimingsEvo); + LogViewPort(pInfoString, impOutTimings, impOutNumHeads); - /* Copy out the usage bounds that passed validation */ + /* + * Copy out the usage bounds that passed validation; note we intersect + * the usage bounds across the hardware heads that would be used with + * this apiHead, accumulating the results in pModeUsage. + */ + for (head = 0; head < impOutNumHeads; head++) { + if (head == 0) { + *pModeUsage = impOutTimings[0].viewPort.possibleUsage; + } else { + struct NvKmsUsageBounds *pTmpUsageBounds = + nvPreallocGet(pDevEvo, + PREALLOC_TYPE_VALIDATE_MODE_TMP_USAGE_BOUNDS, + sizeof(*pTmpUsageBounds)); + + nvIntersectUsageBounds(pModeUsage, + &impOutTimings[head].viewPort.possibleUsage, + pTmpUsageBounds); + *pModeUsage = *pTmpUsageBounds; - nvkms_memcpy(pModeUsage, &pTimingsEvo->viewPort.possibleUsage, sizeof(*pModeUsage)); + nvPreallocRelease(pDevEvo, PREALLOC_TYPE_VALIDATE_MODE_TMP_USAGE_BOUNDS); + } + } /* Whew, if we got this far, the mode is valid. */ @@ -1702,6 +1801,9 @@ done: nvPreallocRelease(pDevEvo, PREALLOC_TYPE_VALIDATE_MODE_HW_MODE_TIMINGS); + nvPreallocRelease(pDevEvo, PREALLOC_TYPE_VALIDATE_MODE_HDMI_FRL_CONFIG); + nvPreallocRelease(pDevEvo, PREALLOC_TYPE_VALIDATE_MODE_DSC_INFO); + nvPreallocRelease(pDevEvo, PREALLOC_TYPE_VALIDATE_MODE_IMP_OUT_HW_MODE_TIMINGS); return ret; } diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia-modeset/src/nvkms-modeset.c nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia-modeset/src/nvkms-modeset.c --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia-modeset/src/nvkms-modeset.c 2023-10-25 20:22:41.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia-modeset/src/nvkms-modeset.c 2024-03-05 22:12:22.000000000 +0000 @@ -72,7 +72,7 @@ * TODO: * - Would it be worthwhile to centralize SOR (re)assignment, disp-wide, * in ApplyProposedModeSetHwStateOneDisp() between the calls to - * ApplyProposedModeSetHwStateOneHeadShutDown() and + * ApplyProposedModeSetStateOneApiHeadShutDown() and * ApplyProposedModeSetHwStateOneHeadPreUpdate()? */ @@ -81,6 +81,7 @@ #include "nvkms-dpy.h" #include "nvkms-rm.h" #include "nvkms-hdmi.h" +#include "nvkms-hw-flip.h" #include "nvkms-flip.h" #include "nvkms-3dvision.h" #include "nvkms-modepool.h" @@ -88,6 +89,7 @@ #include "nvkms-private.h" #include "nvkms-vrr.h" #include "nvkms-lut.h" +#include "nvkms-dma.h" #include "dp/nvdp-connector.h" @@ -112,15 +114,15 @@ if (!committed) { /* Free new allocated RM display IDs for changed heads */ - for (head = 0; head < pDevEvo->numHeads; head++) { - NVProposedModeSetHwStateOneHead *pProposedHead = - &pProposed->disp[dispIndex].head[head]; + for (NvU32 apiHead = 0; apiHead < pDevEvo->numApiHeads; apiHead++) { + NVProposedModeSetStateOneApiHead *pProposedApiHead = + &pProposed->disp[dispIndex].apiHead[apiHead]; - if (!pProposedHead->changed || - (pProposedHead->activeRmId == 0x0)) { + if (!pProposedApiHead->changed || + (pProposedApiHead->activeRmId == 0x0)) { continue; } - nvRmFreeDisplayId(pDispEvo, pProposedHead->activeRmId); + nvRmFreeDisplayId(pDispEvo, pProposedApiHead->activeRmId); } } @@ -169,18 +171,18 @@ * allowFlipLockGroupMask. */ for (dispIndex = 0; dispIndex < ARRAY_LEN(pProposed->disp); dispIndex++) { - NvU32 head; - for (head = 0; - head < ARRAY_LEN(pProposed->disp[dispIndex].head); - head++) { + NvU32 apiHead; + for (apiHead = 0; + apiHead < ARRAY_LEN(pProposed->disp[dispIndex].apiHead); + apiHead++) { - const NVProposedModeSetHwStateOneHead *pProposedHead = - &pProposed->disp[dispIndex].head[head]; + const NVProposedModeSetStateOneApiHead *pProposedApiHead = + &pProposed->disp[dispIndex].apiHead[apiHead]; - if (pProposedHead->allowFlipLockGroup != 0) { - nvAssert(pProposedHead->allowFlipLockGroup <= 64); + if (pProposedApiHead->allowFlipLockGroup != 0) { + nvAssert(pProposedApiHead->allowFlipLockGroup <= 64); allowFlipLockGroupMask |= - NVBIT64(pProposedHead->allowFlipLockGroup - 1); + NVBIT64(pProposedApiHead->allowFlipLockGroup - 1); } } } @@ -272,7 +274,7 @@ GetColorSpaceAndColorRange( const NVDispEvoPtr pDispEvo, const struct NvKmsSetModeOneHeadRequest *pRequestHead, - NVProposedModeSetHwStateOneHead *pProposedHead) + NVProposedModeSetStateOneApiHead *pProposedApiHead) { enum NvKmsDpyAttributeColorRangeValue requestedColorRange; enum NvKmsDpyAttributeRequestedColorSpaceValue requestedColorSpace; @@ -307,20 +309,24 @@ * Choose current colorSpace and colorRange based on the current mode * timings and the requested color space and range. */ - nvChooseCurrentColorSpaceAndRangeEvo(pProposedHead->timings.pixelDepth, - pProposedHead->timings.yuv420Mode, - pProposedHead->tf, - requestedColorSpace, - requestedColorRange, - &pProposedHead->attributes.colorSpace, - &pProposedHead->attributes.colorRange); + if (!nvChooseCurrentColorSpaceAndRangeEvo(pOneArbitraryDpyEvo, + pProposedApiHead->timings.yuv420Mode, + pProposedApiHead->tf, + requestedColorSpace, + requestedColorRange, + &pProposedApiHead->attributes.colorSpace, + &pProposedApiHead->attributes.colorBpc, + &pProposedApiHead->attributes.colorRange)) { + return FALSE; + } + /* * When colorspace is specified in modeset request, it should * match the proposed colorspace. */ if (pRequestHead->colorSpaceSpecified) { NvBool ret = FALSE; - switch (pProposedHead->attributes.colorSpace) { + switch (pProposedApiHead->attributes.colorSpace) { case NV_KMS_DPY_ATTRIBUTE_CURRENT_COLOR_SPACE_RGB: ret = (pRequestHead->colorSpace == NV_KMS_DPY_ATTRIBUTE_REQUESTED_COLOR_SPACE_RGB); @@ -346,13 +352,94 @@ * match the proposed color range. */ if (pRequestHead->colorRangeSpecified && - (pProposedHead->attributes.colorRange != pRequestHead->colorRange)) { + (pProposedApiHead->attributes.colorRange != pRequestHead->colorRange)) { return FALSE; } + pProposedApiHead->colorSpaceSpecified = pRequestHead->colorSpaceSpecified; + pProposedApiHead->colorRangeSpecified = pRequestHead->colorRangeSpecified; + return TRUE; } +/* count existing unchanged and new vrr heads */ +static NvU32 CountProposedVrrApiHeads(NVDevEvoPtr pDevEvo, + const struct NvKmsSetModeRequest *pRequest) +{ + NvU32 sd; + NVDispEvoPtr pDispEvo; + NvU32 numVRRApiHeads = 0; + + FOR_ALL_EVO_DISPLAYS(pDispEvo, sd, pDevEvo) { + NvU32 apiHead; + + for (apiHead = 0; apiHead < pDevEvo->numApiHeads; apiHead++) { + const struct NvKmsSetModeOneDispRequest *pRequestDisp = + &pRequest->disp[sd]; + const struct NvKmsSetModeOneHeadRequest *pRequestHead = + &pRequestDisp->head[apiHead]; + + if (((pRequest->requestedDispsBitMask & (1 << sd)) == 0) || + ((pRequestDisp->requestedHeadsBitMask & (1 << apiHead)) == 0)) { + const NVDispApiHeadStateEvoRec *pApiHeadState = + &pDispEvo->apiHeadState[apiHead]; + + if (pApiHeadState->timings.vrr.type != NVKMS_DPY_VRR_TYPE_NONE) { + numVRRApiHeads++; + } + } else { + const NVDpyEvoRec *pDpyEvo = + nvGetOneArbitraryDpyEvo(pRequestHead->dpyIdList, pDispEvo); + + if (pDpyEvo == NULL) { + continue; + } + + if (nvGetAllowedDpyVrrType(pDpyEvo, + &pRequestHead->mode.timings, + pRequestHead->modeValidationParams.stereoMode, + pRequestHead->allowGsync, + pRequestHead->allowAdaptiveSync) != + NVKMS_DPY_VRR_TYPE_NONE) { + numVRRApiHeads++; + } + } + } + } + + return numVRRApiHeads; +} + +static void AdjustHwModeTimingsForVrr(const NVDispEvoRec *pDispEvo, + const struct NvKmsSetModeOneHeadRequest *pRequestHead, + const NvU32 prohibitAdaptiveSync, + NVHwModeTimingsEvo *pTimings) +{ + NVDpyEvoPtr pDpyEvo = + nvGetOneArbitraryDpyEvo(pRequestHead->dpyIdList, pDispEvo); + if (pDpyEvo == NULL) { + return; + } + + const NvBool allowGsync = pRequestHead->allowGsync; + const enum NvKmsAllowAdaptiveSync allowAdaptiveSync = + prohibitAdaptiveSync ? NVKMS_ALLOW_ADAPTIVE_SYNC_DISABLED : + pRequestHead->allowAdaptiveSync; + const NvU32 vrrOverrideMinRefreshRate = pRequestHead->vrrOverrideMinRefreshRate; + const enum NvKmsDpyVRRType vrrType = + nvGetAllowedDpyVrrType(pDpyEvo, + &pRequestHead->mode.timings, + pRequestHead->modeValidationParams.stereoMode, + allowGsync, + allowAdaptiveSync); + + nvAdjustHwModeTimingsForVrrEvo(pTimings, + vrrType, + pDpyEvo->vrr.edidTimeoutMicroseconds, + vrrOverrideMinRefreshRate, + pDpyEvo->vrr.needsSwFramePacing); +} + /* * Return whether headSurface is allowed. But, only honor the requestor's * setting if they are the modeset owner. Otherwise, inherit the cached value @@ -369,6 +456,538 @@ return pDevEvo->allowHeadSurfaceInNvKms; } +static void +InitNVProposedModeSetStateOneApiHead( + const NVDispEvoRec *pDispEvo, + const NvU32 apiHead, + NVProposedModeSetStateOneApiHead *pProposedApiHead) +{ +#if defined(DEBUG) + const NVDpyEvoRec *pDpyEvo = + nvGetOneArbitraryDpyEvo(pDispEvo->apiHeadState[apiHead].activeDpys, + pDispEvo); +#endif + + if (!nvApiHeadIsActive(pDispEvo, apiHead)) { + return; + } + + nvAssert(pDispEvo->apiHeadState[apiHead].hwHeadsMask != 0x0); + nvAssert(pDpyEvo != NULL); + + pProposedApiHead->hwHeadsMask = + pDispEvo->apiHeadState[apiHead].hwHeadsMask; + pProposedApiHead->timings = + pDispEvo->apiHeadState[apiHead].timings; + pProposedApiHead->dpyIdList = + pDispEvo->apiHeadState[apiHead].activeDpys; + pProposedApiHead->attributes = + pDispEvo->apiHeadState[apiHead].attributes; + pProposedApiHead->changed = FALSE; + pProposedApiHead->hs10bpcHint = + pDispEvo->apiHeadState[apiHead].hs10bpcHint; + pProposedApiHead->infoFrame = + pDispEvo->apiHeadState[apiHead].infoFrame; + pProposedApiHead->tf = pDispEvo->apiHeadState[apiHead].tf; + pProposedApiHead->viewPortPointIn = + pDispEvo->apiHeadState[apiHead].viewPortPointIn; + + NvU32 head; + NvU32 hwHeadCount = 0; + FOR_EACH_EVO_HW_HEAD_IN_MASK(pProposedApiHead->hwHeadsMask, + head) { + const NVDispHeadStateEvoRec *pHeadState = + &pDispEvo->headState[head]; + + nvAssert(pDpyEvo->pConnectorEvo == + pHeadState->pConnectorEvo); + + if (hwHeadCount == 0) { + pProposedApiHead->dscInfo = pHeadState->dscInfo; + pProposedApiHead->activeRmId = pHeadState->activeRmId; + pProposedApiHead->allowFlipLockGroup = + pHeadState->allowFlipLockGroup; + pProposedApiHead->modeValidationParams = + pHeadState->modeValidationParams; + } else { + nvAssert(nvkms_memcmp(&pProposedApiHead->dscInfo, + &pHeadState->dscInfo, + sizeof(pProposedApiHead->dscInfo)) == 0x0); + nvAssert(pProposedApiHead->activeRmId == + pHeadState->activeRmId); + nvAssert(pProposedApiHead->allowFlipLockGroup == + pHeadState->allowFlipLockGroup); + nvAssert(nvkms_memcmp(&pProposedApiHead->modeValidationParams, + &pHeadState->modeValidationParams, + sizeof(pProposedApiHead->modeValidationParams)) == 0x0); + } + } +} + +static void +InitProposedModeSetHwState(const NVDevEvoRec *pDevEvo, + const struct NvKmsPerOpenDev *pOpenDev, + NVProposedModeSetHwState *pProposed) +{ + NvU32 sd; + NVDispEvoPtr pDispEvo; + + nvkms_memset(pProposed, 0, sizeof(*pProposed)); + + /* + * If the previous modeset can not be inherited then initialize the + * proposed modeset state to shutdown all heads. + */ + if (!InheritPreviousModesetState(pDevEvo, pOpenDev)) { + FOR_ALL_EVO_DISPLAYS(pDispEvo, sd, pDevEvo) { + for (NvU32 head = 0; head < pDevEvo->numHeads; head++) { + NvU32 layer; + NVFlipEvoHwState *pFlip = &pProposed->sd[sd].head[head].flip; + for (layer = 0; layer < pDevEvo->head[head].numLayers; layer++) { + pFlip->dirty.layer[layer] = TRUE; + } + } + + for (NvU32 apiHead = 0; apiHead < pDevEvo->numApiHeads; apiHead++) { + pProposed->disp[sd].apiHead[apiHead].changed = TRUE; + } + } + } else { + FOR_ALL_EVO_DISPLAYS(pDispEvo, sd, pDevEvo) { + for (NvU32 apiHead = 0; apiHead < pDevEvo->numApiHeads; apiHead++) { + NVProposedModeSetStateOneApiHead *pProposedApiHead = + &pProposed->disp[sd].apiHead[apiHead];; + + InitNVProposedModeSetStateOneApiHead(pDispEvo, apiHead, + pProposedApiHead); + + NvU32 head; + FOR_EACH_EVO_HW_HEAD_IN_MASK(pProposedApiHead->hwHeadsMask, + head) { + const NVDispHeadStateEvoRec *pHeadState = + &pDispEvo->headState[head]; + NVProposedModeSetHwStateOneHead *pProposedHead = + &pProposed->disp[sd].head[head]; + + nvInitFlipEvoHwState(pDevEvo, sd, head, + &pProposed->sd[sd].head[head].flip); + + pProposedHead->tilePosition = pHeadState->tilePosition; + pProposedHead->timings = pHeadState->timings; + pProposedHead->pConnectorEvo = pHeadState->pConnectorEvo; + pProposedHead->hdmiFrlConfig = pHeadState->hdmiFrlConfig; + pProposedHead->audio = pHeadState->audio; + } + } + } + } +} + +static NvBool +AssignProposedModeSetNVFlipEvoHwState( + NVDevEvoRec *pDevEvo, + const struct NvKmsPerOpenDev *pOpenDev, + const NvU32 sd, + const NvU32 head, + const struct NvKmsSetModeOneHeadRequest *pRequestHead, + NVFlipEvoHwState *pFlip, + NVProposedModeSetHwStateOneHead *pProposedHead, + const NvBool commit) +{ + /* + * Clear the flipStates of all layers: + * + * The current flipState of main layer may still contain + * old surfaces (e.g., headSurface) that are no longer + * desirable or compatible with the new modeset + * configuration. + * + * Function ApplyProposedModeSetHwStateOneHeadShutDown() clears + * pSdHeadState and disables all layers. It is not possible to + * re-apply the existing flipstates because hardware releases + * sempahores when layers get disabled; this results in a stuck + * channel if you re-apply the existing flipstate which has + * the old semaphore values. + */ + + nvClearFlipEvoHwState(pFlip); + + if (commit) { + NvU32 layer; + + for (layer = 0; layer < pDevEvo->head[head].numLayers; layer++) { + pFlip->dirty.layer[layer] = TRUE; + } + } + + /*! + * Modeset path should not request pre-syncpt as it will + * not progress because this will update all of the Core and + * Window method state together, and wait for the Core + * completion notifier to signal. If any of the Window + * channels is waiting for a semaphore acquire, then this + * will stall the Core notifier as well since the Core and + * Window channels are interlocked. + */ + if (pDevEvo->supportsSyncpts && + IsPreSyncptSpecified(pDevEvo, head, &pRequestHead->flip)) { + return FALSE; + } + + if (!nvUpdateFlipEvoHwState(pOpenDev, + pDevEvo, + sd, + head, + &pRequestHead->flip, + &pProposedHead->timings, + pProposedHead->tilePosition, + pFlip, + FALSE /* allowVrr */)) { + return FALSE; + } + + /* + * EVO3 hal simulates USE_CORE_LUT behavior. + * NVDisplay window channel does allow to change the input LUT + * on immediate flips, therefore force disable tearing + * if LUT is specified. + * + * XXX NVKMS TODO: Implement separate input programming for + * base and overlay layers and remove code block. + */ + if ((pRequestHead->lut.input.specified || + pRequestHead->lut.output.specified) && + !pDevEvo->hal->caps.supportsCoreLut) { + pFlip->layer[NVKMS_MAIN_LAYER].tearing = FALSE; + } + + return TRUE; +} + +static +NvBool AssignProposedHwHeadsForDsiConnector( + const NVDispEvoRec *pDispEvo, + NVProposedModeSetHwStateOneDisp *pProposedDisp, + NvU32 *pFreeHwHeadsMask) +{ + const NVDevEvoRec *pDevEvo = pDispEvo->pDevEvo; + NvU32 freeHwHeadsMask = *pFreeHwHeadsMask; + NvU32 ret = TRUE; + + for (NvU32 apiHead = 0; apiHead < pDevEvo->numApiHeads; apiHead++) { + NVProposedModeSetStateOneApiHead *pProposedApiHead = + &pProposedDisp->apiHead[apiHead]; + const NVDpyEvoRec *pDpyEvo = + nvGetOneArbitraryDpyEvo(pProposedApiHead->dpyIdList, pDispEvo); + + if (!pProposedApiHead->changed || + nvDpyIdListIsEmpty(pProposedApiHead->dpyIdList) || + (pDpyEvo->pConnectorEvo->signalFormat != + NVKMS_CONNECTOR_SIGNAL_FORMAT_DSI)) { + continue; + } + + if (pProposedApiHead->hwHeadsMask == 0x0) { + /* DSI supports only HEAD0 assignment */ + if ((freeHwHeadsMask & NVBIT(0)) != 0x0) { + nvAssert(pDevEvo->apiHead[apiHead].numLayers <= + pDevEvo->head[0].numLayers); + nvAssignHwHeadsMaskProposedApiHead(pProposedApiHead, 0x1); + freeHwHeadsMask &= ~pProposedApiHead->hwHeadsMask; + } else { + ret = FALSE; + } + } else { + nvAssert(pProposedApiHead->hwHeadsMask == 0x1); + } + + /* There can be only one DSI dpy */ + break; + } + + *pFreeHwHeadsMask &= freeHwHeadsMask; + return ret; +} + +static +NvBool AssignProposedHwHeadsForDPSerializer( + const NVDispEvoRec *pDispEvo, + NVProposedModeSetHwStateOneDisp *pProposedDisp, + NvU32 *pFreeHwHeadsMask) +{ + const NVDevEvoRec *pDevEvo = pDispEvo->pDevEvo; + NvU32 freeHwHeadsMask = *pFreeHwHeadsMask; + NvU32 ret = TRUE; + + for (NvU32 apiHead = 0; apiHead < pDevEvo->numApiHeads; apiHead++) { + NVProposedModeSetStateOneApiHead *pProposedApiHead = + &pProposedDisp->apiHead[apiHead]; + const NVDpyEvoRec *pDpyEvo = + nvGetOneArbitraryDpyEvo(pProposedApiHead->dpyIdList, pDispEvo); + + if (!pProposedApiHead->changed || + nvDpyIdListIsEmpty(pProposedApiHead->dpyIdList) || + !nvConnectorIsDPSerializer(pDpyEvo->pConnectorEvo)) { + continue; + } + + const NvU32 boundHead = pDpyEvo->dp.serializerStreamIndex; + if (pProposedApiHead->hwHeadsMask == 0x0) { + if ((freeHwHeadsMask & NVBIT(boundHead)) != 0x0) { + nvAssert(pDevEvo->apiHead[apiHead].numLayers <= + pDevEvo->head[boundHead].numLayers); + nvAssignHwHeadsMaskProposedApiHead( + pProposedApiHead, NVBIT(boundHead)); + freeHwHeadsMask &= ~pProposedApiHead->hwHeadsMask; + } else { + ret = FALSE; + break; + } + } else { + nvAssert(pProposedApiHead->hwHeadsMask == + NVBIT(boundHead)); + } + } + + *pFreeHwHeadsMask &= freeHwHeadsMask; + return ret; +} + +static NvBool HeadIsFree(const NVDevEvoRec *pDevEvo, + const NvU32 apiHead, + const NvU32 freeHwHeadsMask, + const NvU32 head) +{ + if ((NVBIT(head) & freeHwHeadsMask) == 0x0) { + return FALSE; + } + + if (pDevEvo->apiHead[apiHead].numLayers > + pDevEvo->head[head].numLayers) { + return FALSE; + } + + return TRUE; +} + +static NvU32 GetFree2Heads1ORHeadsMask(const NVDevEvoRec *pDevEvo, + const NvU32 apiHead, + const NvU32 freeHwHeadsMask) +{ + /* + * Hardware allows to setup 2Heads1OR mode + * between head-0 and head-1, or head-2 and head-3 only. + */ + + if (HeadIsFree(pDevEvo, apiHead, freeHwHeadsMask, 0) && + HeadIsFree(pDevEvo, apiHead, freeHwHeadsMask, 1)) { + return NVBIT(0) | NVBIT(1); + } + + if (HeadIsFree(pDevEvo, apiHead, freeHwHeadsMask, 2) && + HeadIsFree(pDevEvo, apiHead, freeHwHeadsMask, 3)) { + return NVBIT(2) | NVBIT(3); + } + + return 0; +} + +static NvU32 GetFreeHeads(const NVDevEvoRec *pDevEvo, + const NvU32 apiHead, + const NvU32 freeHwHeadsMask) +{ + NvU32 foundHead = NV_INVALID_HEAD; + + for (NvS32 head = (pDevEvo->numHeads - 1); head >= 0; head--) { + if (HeadIsFree(pDevEvo, apiHead, freeHwHeadsMask, head)) { + if ((foundHead == NV_INVALID_HEAD) || + (pDevEvo->head[head].numLayers < + pDevEvo->head[foundHead].numLayers)) { + foundHead = head; + } + } + } + + return foundHead; +} + +static NvBool AssignProposedHwHeadsGeneric( + const NVDispEvoRec *pDispEvo, + NVProposedModeSetHwStateOneDisp *pProposedDisp, + NvU32 *pFreeHwHeadsMask, + const NvBool b2Heads1Or) +{ + const NVDevEvoRec *pDevEvo = pDispEvo->pDevEvo; + NvU32 freeHwHeadsMask = *pFreeHwHeadsMask; + NvU32 ret = TRUE; + + for (NvU32 apiHead = 0; apiHead < pDevEvo->numApiHeads; apiHead++) { + NVProposedModeSetStateOneApiHead *pProposedApiHead = + &pProposedDisp->apiHead[apiHead]; + const NVDpyEvoRec *pDpyEvo = + nvGetOneArbitraryDpyEvo(pProposedApiHead->dpyIdList, pDispEvo); + + if (!pProposedApiHead->changed || + nvDpyIdListIsEmpty(pProposedApiHead->dpyIdList) || + (pProposedApiHead->hwHeadsMask != 0x0)) { + continue; + } + + /* + * The hardware-head assigment for the DSI and dp-serializer dpys + * should be already done. + */ + nvAssert((pDpyEvo->pConnectorEvo->signalFormat != + NVKMS_CONNECTOR_SIGNAL_FORMAT_DSI) && + !nvConnectorIsDPSerializer(pDpyEvo->pConnectorEvo)); + + NvU32 foundHeadsMask = 0x0; + + if (b2Heads1Or) { + if (!nvEvoUse2Heads1OR( + pDpyEvo, + &pProposedApiHead->timings, + &pProposedApiHead->modeValidationParams)) { + continue; + } + foundHeadsMask = GetFree2Heads1ORHeadsMask(pDevEvo, apiHead, + freeHwHeadsMask); + } else { + nvAssert(!nvEvoUse2Heads1OR( + pDpyEvo, + &pProposedApiHead->timings, + &pProposedApiHead->modeValidationParams)); + + NvU32 foundHead = GetFreeHeads(pDevEvo, apiHead, freeHwHeadsMask); + if (foundHead != NV_INVALID_HEAD) { + foundHeadsMask = NVBIT(foundHead); + } + } + + if (foundHeadsMask != 0x0) { + nvAssignHwHeadsMaskProposedApiHead( + pProposedApiHead, foundHeadsMask); + freeHwHeadsMask &= ~pProposedApiHead->hwHeadsMask; + } else { + ret = FALSE; + goto done; + } + } + +done: + *pFreeHwHeadsMask &= freeHwHeadsMask; + return ret; +} + +static void ClearHwHeadsMaskOneApiHead(const NVDispEvoRec *pDispEvo, + const NvU32 apiHead, + NVProposedModeSetHwState *pProposed) +{ + const NvU32 sd = pDispEvo->displayOwner; + NVProposedModeSetHwStateOneDisp *pProposedDisp = + &pProposed->disp[sd]; + NVProposedModeSetStateOneApiHead *pProposedApiHead = + &pProposedDisp->apiHead[apiHead]; + NvU32 head; + + FOR_EACH_EVO_HW_HEAD_IN_MASK(pProposedApiHead->hwHeadsMask, head) { + nvkms_memset(&pProposedDisp->head[head], + 0, sizeof(pProposedDisp->head[head])); + nvkms_memset(&pProposed->sd[sd].head[head], + 0, sizeof(pProposed->sd[sd].head[head])); + } + nvAssignHwHeadsMaskProposedApiHead(pProposedApiHead, 0); +} + +static +void ClearIncompatibleHwHeadsMaskOneDisp(const NVDispEvoRec *pDispEvo, + NVProposedModeSetHwState *pProposed) +{ + const NVDevEvoRec *pDevEvo = pDispEvo->pDevEvo; + const NvU32 sd = pDispEvo->displayOwner; + NVProposedModeSetHwStateOneDisp *pProposedDisp = + &pProposed->disp[sd]; + + for (NvU32 apiHead = 0; apiHead < pDevEvo->numApiHeads; apiHead++) { + NVProposedModeSetStateOneApiHead *pProposedApiHead = + &pProposedDisp->apiHead[apiHead]; + const NVDpyEvoRec *pDpyEvo = + nvGetOneArbitraryDpyEvo(pProposedApiHead->dpyIdList, pDispEvo); + if (!pProposedApiHead->changed || (pDpyEvo == NULL)) { + continue; + } + + NvBool current2Heads1OrState = + (nvPopCount32(pProposedApiHead->hwHeadsMask) > 1); + + const NvBool new2Heads1OrState = + nvEvoUse2Heads1OR(pDpyEvo, + &pProposedApiHead->timings, + &pProposedApiHead->modeValidationParams); + + if (new2Heads1OrState != current2Heads1OrState) { + ClearHwHeadsMaskOneApiHead(pDispEvo, apiHead, pProposed); + } + } +} + +static +NvBool AssignProposedHwHeadsOneDisp(const NVDispEvoRec *pDispEvo, + NVProposedModeSetHwState *pProposed) +{ + const NvU32 sd = pDispEvo->displayOwner; + const NVDevEvoRec *pDevEvo = pDispEvo->pDevEvo; + NVProposedModeSetHwStateOneDisp *pProposedDisp = + &pProposed->disp[sd]; + NvU32 freeHwHeadsMask; + /* + * In first pass, keep the all existing api-head to + * hardware-head(s) assignment unchanged. + */ + NvU32 pass = 0; + + ClearIncompatibleHwHeadsMaskOneDisp(pDispEvo, pProposed); + +repeatHwHeadsAssigment: + freeHwHeadsMask = NVBIT(pDevEvo->numHeads) - 1; + for (NvU32 apiHead = 0; apiHead < pDevEvo->numApiHeads; apiHead++) { + const NVProposedModeSetStateOneApiHead *pProposedApiHead = + &pProposedDisp->apiHead[apiHead]; + nvAssert((pProposedApiHead->hwHeadsMask == 0) || + !nvDpyIdListIsEmpty(pProposedApiHead->dpyIdList)); + freeHwHeadsMask &= ~pProposedApiHead->hwHeadsMask; + } + + if (!AssignProposedHwHeadsForDsiConnector(pDispEvo, pProposedDisp, + &freeHwHeadsMask) || + !AssignProposedHwHeadsForDPSerializer(pDispEvo, pProposedDisp, + &freeHwHeadsMask) || + !AssignProposedHwHeadsGeneric(pDispEvo, pProposedDisp, + &freeHwHeadsMask, + TRUE /* b2Heads1Or */) || + !AssignProposedHwHeadsGeneric(pDispEvo, pProposedDisp, + &freeHwHeadsMask, + FALSE /* b2Heads1Or */)) { + if (pass == 1) { + return FALSE; + } + + /* + * In second pass, do the fresh hardware-head(s) assigment for + * the all changed api-heads. + */ + for (NvU32 apiHead = 0; apiHead < pDevEvo->numApiHeads; apiHead++) { + if (pProposedDisp->apiHead[apiHead].changed) { + ClearHwHeadsMaskOneApiHead(pDispEvo, apiHead, pProposed); + } + } + pass = 1; + goto repeatHwHeadsAssigment; + } + + return TRUE; +} + /*! * Assign the NVProposedModeSetHwState structure. * @@ -401,50 +1020,13 @@ NVDispEvoPtr pDispEvo; NvBool ret = TRUE; NvU8 allowFlipLockGroup = 0; + /* If more than one head will enable VRR on Pascal, disallow Adaptive-Sync */ + const enum NvKmsAllowAdaptiveSync prohibitAdaptiveSync = + (!pDevEvo->hal->caps.supportsDisplayRate && + (CountProposedVrrApiHeads(pDevEvo, pRequest) > 1)); /* Initialize pProposed with the current hardware configuration. */ - - FOR_ALL_EVO_DISPLAYS(pDispEvo, sd, pDevEvo) { - NvU32 head; - for (head = 0; head < pDevEvo->numHeads; head++) { - - const NVDispHeadStateEvoRec *pHeadState; - NVProposedModeSetHwStateOneHead *pProposedHead = - &pProposed->disp[sd].head[head]; - const NvU32 apiHead = nvHardwareHeadToApiHead(head); - - /* - * Case of invalid hardware head is handled inside - * nvInitFlipEvoHwState(). - */ - nvInitFlipEvoHwState(pDevEvo, sd, head, - &pProposed->sd[sd].head[head].flip); - - if (!nvHeadIsActive(pDispEvo, head)) { - continue; - } - - pHeadState = &pDispEvo->headState[head]; - - pProposedHead->timings = pHeadState->timings; - pProposedHead->dpyIdList = - pDispEvo->apiHeadState[apiHead].activeDpys; - pProposedHead->pConnectorEvo = pHeadState->pConnectorEvo; - pProposedHead->activeRmId = pHeadState->activeRmId; - pProposedHead->allowFlipLockGroup = pHeadState->allowFlipLockGroup; - pProposedHead->modeValidationParams = - pHeadState->modeValidationParams; - pProposedHead->attributes = - pDispEvo->apiHeadState[apiHead].attributes; - pProposedHead->changed = FALSE; - pProposedHead->hs10bpcHint = - pDispEvo->apiHeadState[apiHead].hs10bpcHint; - pProposedHead->audio = pHeadState->audio; - pProposedHead->infoFrame = - pDispEvo->apiHeadState[apiHead].infoFrame; - pProposedHead->tf = pHeadState->tf; - } - } + InitProposedModeSetHwState(pDevEvo, pOpenDev, pProposed); /* Update pProposed with the requested changes from the client. */ @@ -454,15 +1036,9 @@ FOR_ALL_EVO_DISPLAYS(pDispEvo, sd, pDevEvo) { const struct NvKmsSetModeOneDispRequest *pRequestDisp = &pRequest->disp[sd]; - NvBool shutDownAllHeads = FALSE; - NvU32 head; if ((pRequest->requestedDispsBitMask & (1 << sd)) == 0) { - if (!InheritPreviousModesetState(pDevEvo, pOpenDev)) { - shutDownAllHeads = TRUE; - } else { - continue; - } + continue; } NVProposedModeSetHwStateOneDisp *pProposedDisp = @@ -470,74 +1046,50 @@ pDispEvo = pDevEvo->pDispEvo[sd]; - for (head = 0; head < pDevEvo->numHeads; head++) { - + /* Construct the per api head proposed modeset state */ + for (NvU32 apiHead = 0; apiHead < pDevEvo->numApiHeads; apiHead++) { const struct NvKmsSetModeOneHeadRequest *pRequestHead = - &pRequestDisp->head[head]; - NVProposedModeSetHwStateOneHead *pProposedHead = - &pProposedDisp->head[head]; - NVDpyIdList newDpyIdList; - NvBool clearAndContinue = FALSE; + &pRequestDisp->head[apiHead]; + NVProposedModeSetStateOneApiHead *pProposedApiHead = + &pProposedDisp->apiHead[apiHead]; + const NVDpyEvoRec *pDpyEvo; - if ((pRequestDisp->requestedHeadsBitMask & (1 << head)) == 0 || - shutDownAllHeads) { - if (!InheritPreviousModesetState(pDevEvo, pOpenDev)) { - /* - * If the modeset owner is changing, implicitly shut down - * other heads not included in requestedHeadsBitMask. - */ - newDpyIdList = nvEmptyDpyIdList(); - } else { - /* - * Otherwise, just leave the head alone so it keeps its - * current configuration. - */ - continue; - } - } else { - newDpyIdList = pRequestHead->dpyIdList; - } - - /* - * If newDpyIdList is empty or do not find the valid dpy in - * newDpyIdList, then the head should be disabled. - * Clear the pProposedHead, so that no state leaks to the new - * configuration. - */ - if (nvDpyIdListIsEmpty(newDpyIdList)) { - clearAndContinue = TRUE; - } else { - const NVDpyEvoRec *pDpyEvo = - nvGetOneArbitraryDpyEvo(newDpyIdList, pDispEvo); - if (pDpyEvo != NULL) { - pProposedHead->pConnectorEvo = pDpyEvo->pConnectorEvo; - pProposedHead->changed = TRUE; - } else { - clearAndContinue = TRUE; - } + if ((pRequestDisp->requestedHeadsBitMask & (1 << apiHead)) == 0) { + /* + * Just leave the head alone so it keeps its current + * configuration. + */ + continue; } - - if (clearAndContinue) { - nvkms_memset(pProposedHead, 0, sizeof(*pProposedHead)); - pProposedHead->changed = TRUE; + pDpyEvo = nvGetOneArbitraryDpyEvo(pRequestHead->dpyIdList, pDispEvo); + if (pDpyEvo == NULL) { + /* + * If newDpyIdList is empty or does not find a valid dpy in + * newDpyIdList, then the head should be disabled. + * Clear the pProposedHead, so that no state leaks to the new + * configuration. + */ + ClearHwHeadsMaskOneApiHead(pDispEvo, apiHead, pProposed); + nvkms_memset(pProposedApiHead, 0, sizeof(*pProposedApiHead)); + pProposedApiHead->changed = TRUE; continue; } - pProposedHead->dpyIdList = newDpyIdList; - pProposedHead->activeRmId = - nvRmAllocDisplayId(pDispEvo, pProposedHead->dpyIdList); - if (pProposedHead->activeRmId == 0x0) { + pProposedApiHead->changed = TRUE; + pProposedApiHead->dpyIdList = pRequestHead->dpyIdList; + pProposedApiHead->activeRmId = + nvRmAllocDisplayId(pDispEvo, pProposedApiHead->dpyIdList); + if (pProposedApiHead->activeRmId == 0x0) { /* XXX Need separate error code? */ - pReply->disp[sd].head[head].status = + pReply->disp[sd].head[apiHead].status = NVKMS_SET_MODE_ONE_HEAD_STATUS_INVALID_DPY; ret = FALSE; continue; } - /* Verify that the requested dpys are valid on this head. */ - if ((pProposedHead->pConnectorEvo->validHeadMask & NVBIT(head)) == 0) { - pReply->disp[sd].head[head].status = + if ((nvDpyGetPossibleApiHeadsMask(pDpyEvo) & NVBIT(apiHead)) == 0) { + pReply->disp[sd].head[apiHead].status = NVKMS_SET_MODE_ONE_HEAD_STATUS_INVALID_DPY; ret = FALSE; continue; @@ -550,55 +1102,57 @@ * head so that if additional heads fail, we can report * more complete failure information to the client. */ - if (!nvGetHwModeTimings(pDispEvo, pRequestHead, - &pProposedHead->timings, &pProposedHead->infoFrame.ctrl)) { - pReply->disp[sd].head[head].status = + if (!nvGetHwModeTimings(pDispEvo, + pRequestHead, + &pProposedApiHead->timings, + &pProposedApiHead->infoFrame.ctrl)) { + pReply->disp[sd].head[apiHead].status = NVKMS_SET_MODE_ONE_HEAD_STATUS_INVALID_MODE; ret = FALSE; continue; } - pProposedHead->infoFrame.hdTimings = - nvEvoIsHDQualityVideoTimings(&pProposedHead->timings); - pProposedHead->allowFlipLockGroup = 0; - pProposedHead->modeValidationParams = + AdjustHwModeTimingsForVrr(pDispEvo, + pRequestHead, + prohibitAdaptiveSync, + &pProposedApiHead->timings); + + pProposedApiHead->stereo.mode = + pRequestHead->modeValidationParams.stereoMode; + pProposedApiHead->stereo.isAegis = pDpyEvo->stereo3DVision.isAegis; + pProposedApiHead->infoFrame.hdTimings = + nvEvoIsHDQualityVideoTimings(&pProposedApiHead->timings); + + pProposedApiHead->allowFlipLockGroup = 0; + pProposedApiHead->modeValidationParams = pRequestHead->modeValidationParams; - pProposedHead->allowGsync = pRequestHead->allowGsync; - pProposedHead->allowAdaptiveSync = pRequestHead->allowAdaptiveSync; - pProposedHead->vrrOverrideMinRefreshRate = - pRequestHead->vrrOverrideMinRefreshRate; - if (!GetColorSpaceAndColorRange(pDispEvo, pRequestHead, pProposedHead)) { - pReply->disp[sd].head[head].status = + if (!GetColorSpaceAndColorRange(pDispEvo, pRequestHead, + pProposedApiHead)) { + pReply->disp[sd].head[apiHead].status = NVKMS_SET_MODE_ONE_HEAD_STATUS_INVALID_MODE; ret = FALSE; continue; } - pProposedHead->attributes.digitalSignal = - nvGetDefaultDpyAttributeDigitalSignalValue(pProposedHead->pConnectorEvo); - if (pProposedHead->timings.hdmiFrlConfig.frlRate != - HDMI_FRL_DATA_RATE_NONE) { - nvAssert(pProposedHead->attributes.digitalSignal == + pProposedApiHead->attributes.digitalSignal = + nvGetDefaultDpyAttributeDigitalSignalValue(pDpyEvo->pConnectorEvo); + if (pProposedApiHead->timings.protocol == + NVKMS_PROTOCOL_SOR_HDMI_FRL) { + nvAssert(pProposedApiHead->attributes.digitalSignal == NV_KMS_DPY_ATTRIBUTE_DIGITAL_SIGNAL_TMDS); - pProposedHead->attributes.digitalSignal = + pProposedApiHead->attributes.digitalSignal = NV_KMS_DPY_ATTRIBUTE_DIGITAL_SIGNAL_HDMI_FRL; } - { - NVDpyEvoRec *pDpyEvo = - nvGetOneArbitraryDpyEvo(pProposedHead->dpyIdList, - pDispEvo); - - pProposedHead->attributes.dvc = - pDpyEvo->currentAttributes.dvc; - - /* Image sharpening is available when scaling is enabled. */ - pProposedHead->attributes.imageSharpening.available = - nvIsImageSharpeningAvailable(&pProposedHead->timings.viewPort); - pProposedHead->attributes.imageSharpening.value = - pDpyEvo->currentAttributes.imageSharpening.value; - } + pProposedApiHead->attributes.dvc = + pDpyEvo->currentAttributes.dvc; + + /* Image sharpening is available when scaling is enabled. */ + pProposedApiHead->attributes.imageSharpening.available = + nvIsImageSharpeningAvailable(&pProposedApiHead->timings.viewPort); + pProposedApiHead->attributes.imageSharpening.value = + pDpyEvo->currentAttributes.imageSharpening.value; /* * If InheritPreviousModesetState() returns FALSE, it implies that @@ -607,124 +1161,156 @@ * keep them disabled by default. */ if (!InheritPreviousModesetState(pDevEvo, pOpenDev)) { - pProposedHead->lut = pRequestHead->lut; + pProposedApiHead->lut = pRequestHead->lut; if (!pRequestHead->lut.input.specified) { - pProposedHead->lut.input.specified = TRUE; - pProposedHead->lut.input.end = 0; + pProposedApiHead->lut.input.specified = TRUE; + pProposedApiHead->lut.input.end = 0; } if (!pRequestHead->lut.output.specified) { - pProposedHead->lut.output.specified = TRUE; - pProposedHead->lut.output.enabled = FALSE; + pProposedApiHead->lut.output.specified = TRUE; + pProposedApiHead->lut.output.enabled = FALSE; } } else if (pRequestHead->lut.input.specified) { - pProposedHead->lut = pRequestHead->lut; + pProposedApiHead->lut = pRequestHead->lut; } else { - pProposedHead->lut.input.specified = FALSE; + pProposedApiHead->lut.input.specified = FALSE; } - NVFlipEvoHwState *pFlip = - &pProposed->sd[sd].head[head].flip; + if (pRequestHead->flip.viewPortIn.specified) { + pProposedApiHead->viewPortPointIn = + pRequestHead->flip.viewPortIn.point; + } + } /* apiHead */ - /* - * Clear the flipStates of all layers: - * - * The current flipState of main layer may still contain - * old surfaces (e.g., headSurface) that are no longer - * desirable or compatible with the new modeset - * configuration. - * - * Function ApplyProposedModeSetHwStateOneHeadShutDown() clears - * pSdHeadState and disables all layers. It is not possible to - * re-apply the existing flipstates because hardware releases - * sempahores when layers get disabled; this results in a stuck - * channel if you re-apply the existing flipstate which has - * the old semaphore values. - */ + if (!AssignProposedHwHeadsOneDisp(pDispEvo, pProposed)) { + pReply->disp[sd].status = + NVKMS_SET_MODE_ONE_DISP_STATUS_FAILED_TO_ASSIGN_HARDWARE_HEADS; + ret = FALSE; + continue; + } - nvClearFlipEvoHwState(pFlip); + /* + * Construct the per hardware head proposed modeset/flip state, and + * assign the dependant per api head modeset parameters. + */ + for (NvU32 apiHead = 0; apiHead < pDevEvo->numApiHeads; apiHead++) { + const struct NvKmsSetModeOneHeadRequest *pRequestHead; + NVProposedModeSetStateOneApiHead *pProposedApiHead = + &pProposedDisp->apiHead[apiHead]; + const NvU32 primaryHead = + nvGetPrimaryHwHeadFromMask(pProposedApiHead->hwHeadsMask); + const NvU32 numTiles = nvPopCount32(pProposedApiHead->hwHeadsMask); + const NVDpyEvoRec *pDpyEvo = + nvGetOneArbitraryDpyEvo(pProposedApiHead->dpyIdList, pDispEvo); + NVProposedModeSetHwStateOneHead *pProposedPrimaryHead; + NvU32 secondaryHeadTilePosition = 1; + NvU32 head; - if (pRequest->commit) { - NvU32 layer; + nvAssert((pProposedApiHead->hwHeadsMask != 0x0) || + (pDpyEvo == NULL)); - for (layer = 0; layer < pDevEvo->head[head].numLayers; layer++) { - pFlip->dirty.layer[layer] = TRUE; + if (!pProposedApiHead->changed || + (pProposedApiHead->hwHeadsMask == 0x0)) { + continue; + } + + nvAssert(primaryHead != NV_INVALID_HEAD); + pProposedPrimaryHead = &pProposedDisp->head[primaryHead]; + + nvAssert((pRequestDisp->requestedHeadsBitMask & (1 << apiHead)) != 0); + pRequestHead = &pRequestDisp->head[apiHead]; + + enum NvKmsSetModeOneHeadStatus status = + NVKMS_SET_MODE_ONE_HEAD_STATUS_SUCCESS; + + FOR_EACH_EVO_HW_HEAD_IN_MASK(pProposedApiHead->hwHeadsMask, head) { + NVProposedModeSetHwStateOneHead *pProposedHead = + &pProposedDisp->head[head]; + + pProposedHead->tilePosition = + (head == primaryHead) ? 0 : (secondaryHeadTilePosition++); + + if (!nvEvoGetSingleTileHwModeTimings(&pProposedApiHead->timings, + numTiles, + &pProposedHead->timings)) { + status = NVKMS_SET_MODE_ONE_HEAD_STATUS_INVALID_MODE; + break; + } + + /* + * Broadcast the connector and the requested flip state across + * the corresponding hardware heads. + */ + pProposedHead->pConnectorEvo = pDpyEvo->pConnectorEvo; + if (!AssignProposedModeSetNVFlipEvoHwState( + pDevEvo, + pOpenDev, + sd, + head, + &pRequest->disp[sd].head[apiHead], + &pProposed->sd[sd].head[head].flip, + pProposedHead, + pRequest->commit)) { + status = NVKMS_SET_MODE_ONE_HEAD_STATUS_INVALID_FLIP; + break; } } - /*! - * Modeset path should not request pre-syncpt as it will - * not progress because this will update all of the Core and - * Window method state together, and wait for the Core - * completion notifier to signal. If any of the Window - * channels is waiting for a semaphore acquire, then this - * will stall the Core notifier as well since the Core and - * Window channels are interlocked. - */ - if (pDevEvo->supportsSyncpts && - IsPreSyncptSpecified( - pDevEvo, - head, - &pRequest->disp[sd].head[head].flip)) { - pReply->disp[sd].head[head].status = - NVKMS_SET_MODE_ONE_HEAD_STATUS_INVALID_FLIP; + if (status != NVKMS_SET_MODE_ONE_HEAD_STATUS_SUCCESS) { + pReply->disp[sd].head[apiHead].status = status; ret = FALSE; - continue; /* next head */ + continue; /* next api head */ } - if (!nvUpdateFlipEvoHwState(pOpenDev, - pDevEvo, - sd, - head, - &pRequestHead->flip, - pFlip, - FALSE /* allowVrr */)) { - pReply->disp[sd].head[head].status = - NVKMS_SET_MODE_ONE_HEAD_STATUS_INVALID_FLIP; + + nvAssert(nvPopCount32(pProposedApiHead->hwHeadsMask) <= 2); + + /* + * Query the per api head HDMI FRL configuration, and pass it to + * the primary head. Save the dsc info into the per api head + * proposed modeset state, to broadcast it onto all hardware heads + * during modeset. + */ + if (!nvHdmiFrlQueryConfig(pDpyEvo, + &pRequestHead->mode.timings, + &pProposedApiHead->timings, + (nvPopCount32(pProposedApiHead->hwHeadsMask) > 1) + /* b2Heads1Or */, + &pProposedApiHead->modeValidationParams, + &pProposedPrimaryHead->hdmiFrlConfig, + &pProposedApiHead->dscInfo)) { + pReply->disp[sd].head[apiHead].status = + NVKMS_SET_MODE_ONE_HEAD_STATUS_INVALID_MODE; ret = FALSE; - continue; /* next head */ + continue; } /* + * Construct the api head audio state, and pass it + * to the primary hardware head. + */ + nvHdmiDpConstructHeadAudioState(pProposedApiHead->activeRmId, + pDpyEvo, + &pProposedPrimaryHead->audio); + + /* * If the modeset is flipping to a depth 30 surface, record this as * a hint to headSurface, so it can also allocate its surfaces at * depth 30. */ { + const NVFlipEvoHwState *pFlip = + &pProposed->sd[sd].head[primaryHead].flip; const NVSurfaceEvoRec *pSurfaceEvo = pFlip->layer[NVKMS_MAIN_LAYER].pSurfaceEvo[NVKMS_LEFT]; - pProposedHead->hs10bpcHint = + pProposedApiHead->hs10bpcHint = (pSurfaceEvo != NULL) && - (pSurfaceEvo->format == NvKmsSurfaceMemoryFormatA2B10G10R10 || - pSurfaceEvo->format == NvKmsSurfaceMemoryFormatX2B10G10R10); - } - - /* - * EVO3 hal simulates USE_CORE_LUT behavior. - * NVDisplay window channel does allow to change the input LUT - * on immediate flips, therefore force disable tearing - * if LUT is specified. - * - * XXX NVKMS TODO: Implement separate input programming for - * base and overlay layers and remove code block. - */ - if ((pRequestHead->lut.input.specified || - pRequestHead->lut.output.specified) && - !pDevEvo->hal->caps.supportsCoreLut) { - pFlip->layer[NVKMS_MAIN_LAYER].tearing = FALSE; - } - - /* Construct audio state */ - { - NVDpyEvoRec *pDpyEvo = - nvGetOneArbitraryDpyEvo(pProposedHead->dpyIdList, - pDispEvo); - - nvHdmiDpConstructHeadAudioState(pProposedHead->activeRmId, - pDpyEvo, &pProposedHead->audio); + ((pSurfaceEvo->format == NvKmsSurfaceMemoryFormatA2B10G10R10) || + (pSurfaceEvo->format == NvKmsSurfaceMemoryFormatX2B10G10R10)); } - } /* head */ + } /* apiHead */ } /* pDispEvo */ /* Assign allowFlipLockGroup for the heads specified in the request. */ @@ -732,33 +1318,28 @@ allowFlipLockGroup = GetAvailableAllowFlipLockGroupValue(pProposed); FOR_ALL_EVO_DISPLAYS(pDispEvo, sd, pDevEvo) { - - NvU32 head; - if ((pRequest->requestedDispsBitMask & NVBIT(sd)) == 0) { continue; } - for (head = 0; head < pDevEvo->numHeads; head++) { - + for (NvU32 apiHead = 0; apiHead < pDevEvo->numApiHeads; apiHead++) { const struct NvKmsSetModeOneHeadRequest *pRequestHead = - &pRequest->disp[sd].head[head]; - NVProposedModeSetHwStateOneHead *pProposedHead = - &pProposed->disp[sd].head[head]; + &pRequest->disp[sd].head[apiHead]; + NVProposedModeSetStateOneApiHead *pProposedApiHead = + &pProposed->disp[sd].apiHead[apiHead]; if ((pRequest->disp[sd].requestedHeadsBitMask & - NVBIT(head)) == 0) { + NVBIT(apiHead)) == 0) { continue; } if (pRequestHead->allowFlipLock) { - pProposedHead->allowFlipLockGroup = allowFlipLockGroup; + pProposedApiHead->allowFlipLockGroup = allowFlipLockGroup; } } } - if (ret) { - } else { + if (!ret) { ClearProposedModeSetHwState(pDevEvo, pProposed, FALSE /* committed */); } @@ -788,25 +1369,27 @@ NVValidateImpOneDispHeadParamsRec timingsParams[NVKMS_MAX_HEADS_PER_DISP]; NvBool skipImpCheck = TRUE, requireBootClocks = FALSE; NVDevEvoPtr pDevEvo = pDispEvo->pDevEvo; - NvU32 head, downgradePossibleHeadsBitMask = 0; + NvU32 downgradePossibleHeadsBitMask = 0; NVEvoReallocateBandwidthMode reallocBandwidth = pDevEvo->isSOCDisplay ? NV_EVO_REALLOCATE_BANDWIDTH_MODE_PRE : NV_EVO_REALLOCATE_BANDWIDTH_MODE_NONE; nvkms_memset(&timingsParams, 0, sizeof(timingsParams)); - for (head = 0; head < pDevEvo->numHeads; head++) { - NVProposedModeSetHwStateOneHead *pProposedHead = - &pProposedDisp->head[head]; + for (NvU32 apiHead = 0; apiHead < pDevEvo->numApiHeads; apiHead++) { + const NVProposedModeSetStateOneApiHead *pProposedApiHead = + &pProposedDisp->apiHead[apiHead]; const NvBool skipImpCheckThisHead = - (pProposedHead->modeValidationParams.overrides & + (pProposedApiHead->modeValidationParams.overrides & NVKMS_MODE_VALIDATION_NO_EXTENDED_GPU_CAPABILITIES_CHECK) != 0; const NvBool requireBootClocksThisHead = - (pProposedHead->modeValidationParams.overrides & + (pProposedApiHead->modeValidationParams.overrides & NVKMS_MODE_VALIDATION_REQUIRE_BOOT_CLOCKS) != 0; + NvU32 head; + /* * Don't try to downgrade heads which are not marked as changed. * This could lead to unchanged/not-requested heads hogging all @@ -818,19 +1401,28 @@ * to handle it. This seems to be a fair trade-off for Orin, as by * default all heads are initialized with minimal usage bounds. */ - if (pProposedHead->changed) { - downgradePossibleHeadsBitMask |= NVBIT(head); + if (pProposedApiHead->changed) { + downgradePossibleHeadsBitMask |= pProposedApiHead->hwHeadsMask; } - if (pProposedHead->pConnectorEvo == NULL) { - continue; - } + FOR_EACH_EVO_HW_HEAD_IN_MASK(pProposedApiHead->hwHeadsMask, head) { + NVProposedModeSetHwStateOneHead *pProposedHead = + &pProposedDisp->head[head]; - timingsParams[head].pConnectorEvo = pProposedHead->pConnectorEvo; - timingsParams[head].activeRmId = pProposedHead->activeRmId; - timingsParams[head].pTimings = &pProposedHead->timings; - timingsParams[head].pUsage = - &pProposedHead->timings.viewPort.guaranteedUsage; + timingsParams[head].pConnectorEvo = pProposedHead->pConnectorEvo; + timingsParams[head].activeRmId = pProposedApiHead->activeRmId; + timingsParams[head].pixelDepth = + nvEvoColorSpaceBpcToPixelDepth(pProposedApiHead->attributes.colorSpace, + pProposedApiHead->attributes.colorBpc); + timingsParams[head].pTimings = &pProposedHead->timings; + timingsParams[head].enableDsc = (pProposedApiHead->dscInfo.type != + NV_DSC_INFO_EVO_TYPE_DISABLED); + nvAssert(nvPopCount32(pProposedApiHead->hwHeadsMask) <= 2); + timingsParams[head].b2Heads1Or = + (nvPopCount32(pProposedApiHead->hwHeadsMask) > 1); + timingsParams[head].pUsage = + &pProposedHead->timings.viewPort.guaranteedUsage; + } skipImpCheck = skipImpCheck && skipImpCheckThisHead; requireBootClocks = requireBootClocks || requireBootClocksThisHead; @@ -857,25 +1449,27 @@ return FALSE; } - for (head = 0; head < pDevEvo->numHeads; head++) { - NVProposedModeSetHwStateOneHead *pProposedHead = - &pProposedDisp->head[head]; - const struct NvKmsUsageBounds *pProposedUsage; + for (NvU32 apiHead = 0; apiHead < pDevEvo->numApiHeads; apiHead++) { + const NVProposedModeSetStateOneApiHead *pProposedApiHead = + &pProposedDisp->apiHead[apiHead]; + NvU32 head; - if (pProposedHead->pConnectorEvo == NULL) { - continue; - } + FOR_EACH_EVO_HW_HEAD_IN_MASK(pProposedApiHead->hwHeadsMask, head) { + NVProposedModeSetHwStateOneHead *pProposedHead = + &pProposedDisp->head[head]; + const struct NvKmsUsageBounds *pProposedUsage; - if (pProposedHead->changed) { - pProposedUsage = &pProposed->sd[0].head[head].flip.usage; - } else { - pProposedUsage = - &pDevEvo->gpus[0].headState[head].preallocatedUsage; - } + if (pProposedApiHead->changed) { + pProposedUsage = &pProposed->sd[0].head[head].flip.usage; + } else { + pProposedUsage = + &pDevEvo->gpus[0].headState[head].preallocatedUsage; + } - nvUnionUsageBounds(&pProposedHead->timings.viewPort.guaranteedUsage, - pProposedUsage, &guaranteedAndProposed[head]); - timingsParams[head].pUsage = &guaranteedAndProposed[head]; + nvUnionUsageBounds(&pProposedHead->timings.viewPort.guaranteedUsage, + pProposedUsage, &guaranteedAndProposed[head]); + timingsParams[head].pUsage = &guaranteedAndProposed[head]; + } } ret = nvValidateImpOneDisp(pDispEvo, timingsParams, @@ -897,43 +1491,82 @@ } static NvBool SkipDisplayPortBandwidthCheck( - const NVProposedModeSetHwStateOneHead *pProposedHead) + const NVProposedModeSetStateOneApiHead *pProposedApiHead) { - return (pProposedHead->modeValidationParams.overrides & + return (pProposedApiHead->modeValidationParams.overrides & NVKMS_MODE_VALIDATION_NO_DISPLAYPORT_BANDWIDTH_CHECK) != 0; } -static NvBool DowngradeDpPixelDepth( +static NvBool DowngradeColorSpaceAndBpcOneHead( + const NVDispEvoRec *pDispEvo, + NVProposedModeSetStateOneApiHead *pProposedApiHead) +{ + enum NvKmsDpyAttributeColorRangeValue colorRange = + pProposedApiHead->attributes.colorRange; + enum NvKmsDpyAttributeCurrentColorSpaceValue colorSpace = + pProposedApiHead->attributes.colorSpace; + enum NvKmsDpyAttributeColorBpcValue colorBpc = + pProposedApiHead->attributes.colorBpc; + NVDpyEvoRec *pDpyEvo = + nvGetOneArbitraryDpyEvo(pProposedApiHead->dpyIdList, + pDispEvo); + const NVColorFormatInfoRec supportedColorFormats = + nvGetColorFormatInfo(pDpyEvo); + + if (!nvDowngradeColorSpaceAndBpc(&supportedColorFormats, + &colorSpace, &colorBpc, &colorRange)) { + return FALSE; + } + + if (pProposedApiHead->colorRangeSpecified && + (colorRange != pProposedApiHead->attributes.colorRange)) { + return FALSE; + } + + if (pProposedApiHead->colorSpaceSpecified && + (colorSpace != pProposedApiHead->attributes.colorSpace)) { + return FALSE; + } + + pProposedApiHead->attributes.colorRange = colorRange; + pProposedApiHead->attributes.colorSpace = colorSpace; + pProposedApiHead->attributes.colorBpc = colorBpc; + + return TRUE; +} + +static NvBool DowngradeColorSpaceAndBpcOneDisp( NVDispEvoPtr pDispEvo, NVProposedModeSetHwStateOneDisp *pProposedDisp, const NVConnectorEvoRec *pConnectorEvo) { - NvU32 head; + NvBool ret = FALSE; + NvU32 apiHead; /* * In DP-MST case, many heads can share same connector and dp-bandwidth * therefore its necessary to validate and downgrade dp-pixel-depth across * all head which are sharing same connector before retry. */ - for (head = 0; head < pDispEvo->pDevEvo->numHeads; head++) { - NVProposedModeSetHwStateOneHead *pProposedHead = - &pProposedDisp->head[head]; - NVHwModeTimingsEvoPtr pTimings = &pProposedHead->timings; + for (apiHead = 0; apiHead < pDispEvo->pDevEvo->numApiHeads; apiHead++) { + NVProposedModeSetStateOneApiHead *pProposedApiHead = + &pProposedDisp->apiHead[apiHead]; + const NVDpyEvoRec *pDpyEvo = + nvGetOneArbitraryDpyEvo(pProposedApiHead->dpyIdList, pDispEvo); - if (SkipDisplayPortBandwidthCheck(pProposedHead)) { + if (!pProposedApiHead->changed || + SkipDisplayPortBandwidthCheck(pProposedApiHead)) { continue; } - if ((pProposedHead->pConnectorEvo == pConnectorEvo) && - nvDowngradeHwModeTimingsDpPixelDepthEvo( - pTimings, - pProposedHead->attributes.colorSpace, - pProposedHead->attributes.colorRange)) { - return TRUE; + if ((pDpyEvo != NULL) && + (pDpyEvo->pConnectorEvo == pConnectorEvo) && + DowngradeColorSpaceAndBpcOneHead(pDispEvo, pProposedApiHead)) { + ret = TRUE; } } - return FALSE; + return ret; } /*! @@ -949,9 +1582,8 @@ NVDispEvoPtr pDispEvo, NVProposedModeSetHwStateOneDisp *pProposedDisp) { - NvU32 head; NvBool bResult = TRUE, bTryAgain = FALSE; - + const NVDevEvoRec *pDevEvo = pDispEvo->pDevEvo; tryAgain: @@ -960,28 +1592,47 @@ nvDPBeginValidation(pDispEvo); - for (head = 0; head < pDispEvo->pDevEvo->numHeads; head++) { - NVProposedModeSetHwStateOneHead *pProposedHead = - &pProposedDisp->head[head]; - NVHwModeTimingsEvoPtr pTimings = &pProposedHead->timings; + for (NvU32 apiHead = 0; apiHead < pDevEvo->numApiHeads; apiHead++) { + NVProposedModeSetStateOneApiHead *pProposedApiHead = + &pProposedDisp->apiHead[apiHead]; + const NvU32 primaryHead = + nvGetPrimaryHwHeadFromMask(pProposedApiHead->hwHeadsMask); + const NVDpyEvoRec *pDpyEvo = + nvGetOneArbitraryDpyEvo(pProposedApiHead->dpyIdList, pDispEvo); + const NvBool b2Heads1Or = + nvPopCount32(pProposedApiHead->hwHeadsMask) > 1; - if ((pProposedHead->pConnectorEvo == NULL) || - SkipDisplayPortBandwidthCheck(pProposedHead)) { + nvAssert(nvPopCount32(pProposedApiHead->hwHeadsMask) <= 2); + + if ((pDpyEvo == NULL) || + SkipDisplayPortBandwidthCheck(pProposedApiHead)) { continue; } bResult = !!nvDPLibValidateTimings(pDispEvo, - head, - pProposedHead->activeRmId, - pProposedHead->dpyIdList, - pProposedHead->attributes.colorSpace, - &pProposedHead->modeValidationParams, - pTimings); - - if (!bResult) { - if (DowngradeDpPixelDepth(pDispEvo, - pProposedDisp, - pProposedHead->pConnectorEvo)) { + primaryHead, + pProposedApiHead->activeRmId, + pProposedApiHead->dpyIdList, + pProposedApiHead->attributes.colorSpace, + pProposedApiHead->attributes.colorBpc, + &pProposedApiHead->modeValidationParams, + &pProposedApiHead->timings, + b2Heads1Or, + &pProposedApiHead->dscInfo); + + if (!bResult && pProposedApiHead->changed) { + + /* + * First, try to downgrade the pixel depth for this current head. + * If the pixel depth for this current head is not possible to + * downgrade further then try to downgrade the pixel depth of other + * changed heads which are sharing same connector and dp-bandwidth. + */ + + if (DowngradeColorSpaceAndBpcOneHead(pDispEvo, pProposedApiHead) || + DowngradeColorSpaceAndBpcOneDisp(pDispEvo, + pProposedDisp, + pDpyEvo->pConnectorEvo)) { bTryAgain = TRUE; } @@ -991,6 +1642,14 @@ */ break; + } else if (!bResult) { + + /* + * The Dp link bandwidth check fails for an unchanged head -- + * This proposed mode-set is not possible on this DP link, so fail. + */ + + break; } } @@ -1001,24 +1660,40 @@ } if (bResult) { - for (head = 0; head < pDispEvo->pDevEvo->numHeads; head++) { - NVProposedModeSetHwStateOneHead *pProposedHead = - &pProposedDisp->head[head]; + for (NvU32 apiHead = 0; apiHead < pDevEvo->numApiHeads; apiHead++) { + const NVProposedModeSetStateOneApiHead *pProposedApiHead = + &pProposedDisp->apiHead[apiHead]; + const NvU32 primaryHead = + nvGetPrimaryHwHeadFromMask(pProposedApiHead->hwHeadsMask); + const NVDpyEvoRec *pDpyEvo = + nvGetOneArbitraryDpyEvo(pProposedApiHead->dpyIdList, pDispEvo); + NVProposedModeSetHwStateOneHead *pProposedPrimaryHead; + + nvAssert((pProposedApiHead->hwHeadsMask != 0x0) || + (pDpyEvo == NULL)); + + if ((pProposedApiHead->hwHeadsMask == 0x0)) { + continue; + } + + nvAssert(primaryHead != NV_INVALID_HEAD); + pProposedPrimaryHead = &pProposedDisp->head[primaryHead]; - if ((pProposedHead->pConnectorEvo == NULL) || - !nvConnectorUsesDPLib(pProposedHead->pConnectorEvo)) { - pProposedHead->pDpLibModesetState = NULL; + if (!nvConnectorUsesDPLib(pDpyEvo->pConnectorEvo)) { + pProposedPrimaryHead->pDpLibModesetState = NULL; continue; } - pProposedHead->pDpLibModesetState = + pProposedPrimaryHead->pDpLibModesetState = nvDPLibCreateModesetState(pDispEvo, - head, - pProposedHead->activeRmId, - pProposedHead->dpyIdList, - pProposedHead->attributes.colorSpace, - &pProposedHead->timings); - if (pProposedHead->pDpLibModesetState == NULL) { + primaryHead, + pProposedApiHead->activeRmId, + pProposedApiHead->dpyIdList, + pProposedApiHead->attributes.colorSpace, + pProposedApiHead->attributes.colorBpc, + &pProposedApiHead->timings, + &pProposedApiHead->dscInfo); + if (pProposedPrimaryHead->pDpLibModesetState == NULL) { return FALSE; } } @@ -1032,28 +1707,28 @@ NVVBlankCallbackPtr pVBlankCallbackTmp = NULL; NVVBlankCallbackPtr pVBlankCallback = NULL; NVDispEvoPtr pDispEvo = dataPtr; - NvU32 head = data32; + NvU32 apiHead = data32; - if (!nvHeadIsActive(pDispEvo, head)) { + if (!nvApiHeadIsActive(pDispEvo, apiHead)) { return; } nvListForEachEntry_safe(pVBlankCallback, pVBlankCallbackTmp, - &pDispEvo->headState[head].vblankCallbackList, + &pDispEvo->apiHeadState[apiHead].vblankCallbackList, vblankCallbackListEntry) { - pVBlankCallback->pCallback(pDispEvo, head, pVBlankCallback); + pVBlankCallback->pCallback(pDispEvo, pVBlankCallback); } } static void VBlankCallback(void *pParam1, void *pParam2) { - const NvU32 head = (NvU32)(NvUPtr)pParam2; + const NvU32 apiHead = (NvU32)(NvUPtr)pParam2; (void) nvkms_alloc_timer_with_ref_ptr( VBlankCallbackDeferredWork, pParam1, /* ref_ptr to pDispEvo */ - head, /* dataU32 */ + apiHead, /* dataU32 */ 0); /* timeout: schedule the work immediately */ } @@ -1079,17 +1754,16 @@ { const NVDevEvoRec *pDevEvo = pDispEvo->pDevEvo; NVDpyIdList dpyIdList; - NvU32 head; /* * Check that the requested configuration of connectors can be * driven simultaneously. */ dpyIdList = nvEmptyDpyIdList(); - for (head = 0; head < pDevEvo->numHeads; head++) { + for (NvU32 apiHead = 0; apiHead < pDevEvo->numApiHeads; apiHead++) { NVDpyEvoPtr pDpyEvo; FOR_ALL_EVO_DPYS(pDpyEvo, - pProposedDisp->head[head].dpyIdList, pDispEvo) { + pProposedDisp->apiHead[apiHead].dpyIdList, pDispEvo) { dpyIdList = nvAddDpyIdToDpyIdList(pDpyEvo->pConnectorEvo->displayId, dpyIdList); } @@ -1104,15 +1778,15 @@ * Check that no dpyId is used by multiple heads. */ dpyIdList = nvEmptyDpyIdList(); - for (head = 0; head < NVKMS_MAX_HEADS_PER_DISP; head++) { + for (NvU32 apiHead = 0; apiHead < NVKMS_MAX_HEADS_PER_DISP; apiHead++) { /* * Intersect the proposed dpys for this head with the * accumulated list of dpys for this disp; if the intersection * is not empty, a dpy is proposed to be used on multiple - * heads. + * api heads. */ NVDpyIdList proposedDpyIdList = - pProposedDisp->head[head].dpyIdList; + pProposedDisp->apiHead[apiHead].dpyIdList; NVDpyIdList intersectedDpyIdList = nvIntersectDpyIdListAndDpyIdList(dpyIdList, proposedDpyIdList); @@ -1127,18 +1801,23 @@ /* * Check ViewPortIn dimensions and ensure valid h/vTaps can be assigned. */ - for (head = 0; head < pDevEvo->numHeads; head++) { + for (NvU32 apiHead = 0; apiHead < pDevEvo->numApiHeads; apiHead++) { + NvU32 head; + NVProposedModeSetStateOneApiHead *pProposedApiHead = + &pProposedDisp->apiHead[apiHead]; - /* XXX assume the gpus have equal capabilities */ - const NVEvoScalerCaps *pScalerCaps = - &pDevEvo->gpus[0].capabilities.head[head].scalerCaps; - const NVHwModeTimingsEvoPtr pTimings = &pProposedDisp->head[head].timings; - - if (!nvValidateHwModeTimingsViewPort(pDevEvo, pScalerCaps, pTimings, - &dummyInfoString)) { - pReplyDisp->head[head].status = - NVKMS_SET_MODE_ONE_HEAD_STATUS_INVALID_MODE; - return FALSE; + FOR_EACH_EVO_HW_HEAD_IN_MASK(pProposedApiHead->hwHeadsMask, head) { + /* XXX assume the gpus have equal capabilities */ + const NVEvoScalerCaps *pScalerCaps = + &pDevEvo->gpus[0].capabilities.head[head].scalerCaps; + const NVHwModeTimingsEvoPtr pTimings = &pProposedDisp->head[head].timings; + + if (!nvValidateHwModeTimingsViewPort(pDevEvo, pScalerCaps, pTimings, + &dummyInfoString)) { + pReplyDisp->head[apiHead].status = + NVKMS_SET_MODE_ONE_HEAD_STATUS_INVALID_MODE; + return FALSE; + } } } @@ -1156,21 +1835,20 @@ * configuration, gets finalized as part of the DisplayPort bandwidth * validation. */ - for (head = 0; head < pDevEvo->numHeads; head++) { - NVProposedModeSetHwStateOneHead *pProposedHead = - &pProposedDisp->head[head]; - NVDpyEvoRec *pDpyEvo = - nvGetOneArbitraryDpyEvo(pProposedHead->dpyIdList, - pDispEvo); + for (NvU32 apiHead = 0; apiHead < pDevEvo->numApiHeads; apiHead++) { + NVProposedModeSetStateOneApiHead *pProposedApiHead = + &pProposedDisp->apiHead[apiHead]; + const NVDpyEvoRec *pDpyEvo = + nvGetOneArbitraryDpyEvo(pProposedApiHead->dpyIdList, pDispEvo); - if (!pProposedHead->changed || (pDpyEvo == NULL)) { + if (!pProposedApiHead->changed || (pDpyEvo == NULL)) { continue; } nvChooseDitheringEvo(pDpyEvo->pConnectorEvo, - pProposedHead->timings.pixelDepth, + pProposedApiHead->attributes.colorBpc, &pDpyEvo->requestedDithering, - &pProposedHead->attributes.dithering); + &pProposedApiHead->attributes.dithering); } /* @@ -1204,27 +1882,31 @@ NVProposedModeSetHwStateOneSubDev *pProposedSd, struct NvKmsSetModeOneDispReply *pReplyDisp) { - NvU32 head; + for (NvU32 apiHead = 0; apiHead < pDevEvo->numApiHeads; apiHead++) { + NvU32 head; + const NVProposedModeSetStateOneApiHead *pProposedApiHead = + &pProposedDisp->apiHead[apiHead]; - for (head = 0; head < pDevEvo->numHeads; head++) { - if (!pProposedDisp->head[head].changed || - nvDpyIdListIsEmpty(pProposedDisp->head[head].dpyIdList)) { + if (!pProposedApiHead->changed || + nvDpyIdListIsEmpty(pProposedApiHead->dpyIdList)) { continue; } - nvOverrideScalingUsageBounds( - pDevEvo, - head, - &pProposedSd->head[head].flip, - &pProposedDisp->head[head].timings.viewPort.possibleUsage); + FOR_EACH_EVO_HW_HEAD_IN_MASK(pProposedApiHead->hwHeadsMask, head) { + nvOverrideScalingUsageBounds( + pDevEvo, + head, + &pProposedSd->head[head].flip, + &pProposedDisp->head[head].timings.viewPort.possibleUsage); - if (!nvValidateFlipEvoHwState(pDevEvo, - head, - &pProposedDisp->head[head].timings, - &pProposedSd->head[head].flip)) { - pReplyDisp->head[head].status = - NVKMS_SET_MODE_ONE_HEAD_STATUS_INVALID_FLIP; - return FALSE; + if (!nvValidateFlipEvoHwState(pDevEvo, + head, + &pProposedDisp->head[head].timings, + &pProposedSd->head[head].flip)) { + pReplyDisp->head[apiHead].status = + NVKMS_SET_MODE_ONE_HEAD_STATUS_INVALID_FLIP; + return FALSE; + } } } @@ -1310,100 +1992,66 @@ * already been assigned and need to be excluded from consideration for * the new SOR assignment request. */ -static void AssignSor(NVModeSetWorkArea *pWorkArea, - NVConnectorEvoPtr pConnectorEvo) +static void AssignSor(const NVDispEvoRec *pDispEvo, + const NVProposedModeSetStateOneApiHead *pProposedApiHead, + NVModeSetWorkArea *pWorkArea) { - const NvU32 sd = pConnectorEvo->pDispEvo->displayOwner; + const NvU32 sd = pDispEvo->displayOwner; + const NVDpyEvoRec *pDpyEvo = + nvGetOneArbitraryDpyEvo(pProposedApiHead->dpyIdList, pDispEvo); + const NVConnectorEvoRec *pConnectorEvo = pDpyEvo->pConnectorEvo; + + const NvBool b2Heads1Or = + (nvPopCount32(pProposedApiHead->hwHeadsMask) > 1); + /* + * In 2Heads1OR DP-MST case, NV0073_CTRL_CMD_DFP_ASSIGN_SOR needs + * to be called with the dynamic displayId. + */ + const NvU32 displayId = (nvDpyEvoIsDPMST(pDpyEvo) && b2Heads1Or) ? + pProposedApiHead->activeRmId : nvDpyIdToNvU32(pConnectorEvo->displayId); + /* + * There are two usecases: + * 1. Two 2Heads1OR DP-MST streams over a same connector. + * 2. One legacy and one 2Heads1OR DP-MST stream over a same connector. + * For both of these usecases, NV0073_CTRL_CMD_DFP_ASSIGN_SOR will get + * called over the same connector multiple times, + * + * Two DP-MST streams over a same connector shares a same primary SOR index. + * + * Remove the already assigned assigned primary SOR index from + * sorExcludeMask, so that NV0073_CTRL_CMD_DFP_ASSIGN_SOR + * re-use it. + */ + const NvU32 sorExcludeMask = + (pConnectorEvo->or.primary != NV_INVALID_OR) ? + (pWorkArea->sd[sd].assignedSorMask & ~NVBIT(pConnectorEvo->or.primary)) : + (pWorkArea->sd[sd].assignedSorMask); if (pConnectorEvo->or.type != NV0073_CTRL_SPECIFIC_OR_TYPE_SOR) { // Nothing to do! return; } - /* If an OR has already been assigned for this connector, we are done. */ - if (nvDpyIdIsInDpyIdList( - pConnectorEvo->displayId, - pWorkArea->sd[sd].sorAssignedConnectorsList)) { - nvAssert(pConnectorEvo->or.mask != 0x0); - return; - } - - /* - * We keep a record all the SORs assigned for this modeset, so that - * it can be used as the sorExcludeMask argument to - * nvAssignSOREvo(). - */ - if (nvAssignSOREvo( - pConnectorEvo, - pWorkArea->sd[sd].assignedSorMask /* sorExcludeMask */)) { - nvAssert(pConnectorEvo->or.mask != 0x0); - - pWorkArea->sd[sd].sorAssignedConnectorsList = - nvAddDpyIdToDpyIdList( - pConnectorEvo->displayId, - pWorkArea->sd[sd].sorAssignedConnectorsList); - pWorkArea->sd[sd].assignedSorMask |= pConnectorEvo->or.mask; + if (nvAssignSOREvo(pDispEvo, displayId, b2Heads1Or, sorExcludeMask)) { + nvAssert(pConnectorEvo->or.primary != NV_INVALID_OR); + pWorkArea->sd[sd].assignedSorMask |= nvConnectorGetORMaskEvo(pConnectorEvo); } else { nvAssert(!"Failed to assign SOR, this failure might cause hang!"); } } -static void AssignProposedUsageOneHead( - NVDevEvoPtr pDevEvo, - const NVProposedModeSetHwState *pProposed, - NvU32 head) -{ - const NVProposedModeSetHwStateOneHead *pProposedHead = - &pProposed->disp[0].head[head]; - const NVProposedModeSetHwStateOneSubDev *pProposedSd = - &pProposed->sd[0]; - - if (!pDevEvo->isSOCDisplay || (pProposedHead->pConnectorEvo == NULL)) { - return; - } - - pDevEvo->gpus[0].headState[head].preallocatedUsage = - pProposedSd->head[head].flip.usage; -} - -static NvBool IsProposedModeSetHwStateOneDispIncompatibleWithDpy -( - NVDispEvoPtr pDispEvo, - const NVProposedModeSetHwStateOneDisp *pProposedDisp, - const NVConnectorEvoRec *pConnectorEvo -) -{ - NVDevEvoPtr pDevEvo = pDispEvo->pDevEvo; - NvU32 head; - - for (head = 0; head < pDevEvo->numHeads; head++) { - - const NVProposedModeSetHwStateOneHead *pProposedHead = - &pProposedDisp->head[head]; - - if (!pProposedHead->changed) { - continue; - } - - /* - * DDC partners incompatible with each other, only one should be active - * at a time. - */ - if ((pProposedHead->pConnectorEvo != NULL) && - nvDpyIdIsInDpyIdList(pProposedHead->pConnectorEvo->displayId, - pConnectorEvo->ddcPartnerDpyIdsList)) { - return TRUE; - } - } - - return FALSE; -} - static void KickoffModesetUpdateState( NVDispEvoPtr pDispEvo, NVEvoModesetUpdateState *modesetUpdateState) { + const NVDevEvoRec *pDevEvo = pDispEvo->pDevEvo; + + for (NvU32 head = 0; head < pDevEvo->numHeads; head++) { + nvEvoPreModesetRegisterFlipOccurredEvent(pDispEvo, head, + modesetUpdateState); + } + if (!nvDpyIdListIsEmpty(modesetUpdateState->connectorIds)) { NVConnectorEvoRec *pConnectorEvo; @@ -1435,15 +2083,20 @@ } if (pConnectorEvo->pDpLibConnector != NULL) { - nvDPPostSetMode(pConnectorEvo->pDpLibConnector); + nvDPPostSetMode(pConnectorEvo->pDpLibConnector, + modesetUpdateState); } else if (nvConnectorIsDPSerializer(pConnectorEvo)) { nvDPSerializerPostSetMode(pDispEvo, pConnectorEvo); } } } - *modesetUpdateState = - (NVEvoModesetUpdateState) { }; + for (NvU32 head = 0; head < pDevEvo->numHeads; head++) { + nvEvoPostModesetUnregisterFlipOccurredEvent(pDispEvo, head, + modesetUpdateState); + } + + nvkms_memset(modesetUpdateState, 0, sizeof(*modesetUpdateState)); } /*! @@ -1451,37 +2104,97 @@ * activated display devices. */ static NvBool -IsProposedModeSetHwStateOneHeadIncompatible( +IsProposedModeSetStateOneApiHeadIncompatible( NVDispEvoPtr pDispEvo, - NvU32 head, + NvU32 apiHead, const NVProposedModeSetHwStateOneDisp *pProposedDisp) { - const NVDispHeadStateEvoRec *pHeadState = &pDispEvo->headState[head]; - NvBool isIncompatible; + const NVDevEvoRec *pDevEvo = pDispEvo->pDevEvo; + const NVProposedModeSetStateOneApiHead *pProposedApiHead = + &pProposedDisp->apiHead[apiHead]; + const NVDispApiHeadStateEvoRec *pApiHeadState = + &pDispEvo->apiHeadState[apiHead]; + const NVDpyEvoRec *pDpyEvo = + nvGetOneArbitraryDpyEvo(pApiHeadState->activeDpys, pDispEvo); + const NvBool bCurrent2Heads1Or = + (nvPopCount32(pApiHeadState->hwHeadsMask) > 1); + const NvBool bProposed2Heads1Or = + (nvPopCount32(pProposedApiHead->hwHeadsMask) > 1); + nvAssert(pDpyEvo != NULL); /* * DisplayPort devices require an EVO update when detaching the head * from the SOR, because DPlib performs link-training to powerdown * the link. So, always consider DisplayPort as incompatible. + * + * Consider this api-head incompatible if there is change in the api-head + * to hardware-head(s) mapping. + * + * Mark api-head incompatible if its current or proposed modeset state is + * using 2Heads1OR configuration: + * Even if there is no change in the hardware heads or modetimings, it is + * not possible to do modeset on the active 2Heads1OR api-head without + * shutting it down first. The modeset code path is ready to handle the + * glitchless 2Heads1OR modeset, for example NV0073_CTRL_CMD_DFP_ASSIGN_SOR + * does not handles the assignment of secondary SORs if display is already + * active and returns incorrect information which leads to segfault in + * NVKMS. */ - isIncompatible = - nvConnectorUsesDPLib(pHeadState->pConnectorEvo) || - IsProposedModeSetHwStateOneDispIncompatibleWithDpy(pDispEvo, - pProposedDisp, - pHeadState->pConnectorEvo); - - return isIncompatible; + if (nvConnectorUsesDPLib(pDpyEvo->pConnectorEvo) || + ((pProposedApiHead->hwHeadsMask != 0x0) && + (pProposedApiHead->hwHeadsMask != pApiHeadState->hwHeadsMask)) || + bCurrent2Heads1Or || bProposed2Heads1Or) { + return TRUE; + } + + for (NvU32 tmpApiHead = 0; tmpApiHead < pDevEvo->numApiHeads; tmpApiHead++) { + const NVProposedModeSetStateOneApiHead *pTmpProposedApiHead = + &pProposedDisp->apiHead[tmpApiHead]; + const NVDpyEvoRec *pDpyEvoTmp = + nvGetOneArbitraryDpyEvo(pTmpProposedApiHead->dpyIdList, pDispEvo); + + if (!pTmpProposedApiHead->changed) { + continue; + } + + /* + * DDC partners incompatible with each other, only one should be active + * at a time. + */ + if ((pDpyEvoTmp != NULL) && + nvDpyIdIsInDpyIdList(pDpyEvoTmp->pConnectorEvo->displayId, + pDpyEvo->pConnectorEvo->ddcPartnerDpyIdsList)) { + return TRUE; + } + + /* + * Consider this api-head incompatible if its current hardware heads + * are proposed to map onto the different api-head. + */ + if ((tmpApiHead != apiHead) && + ((pTmpProposedApiHead->hwHeadsMask & + pApiHeadState->hwHeadsMask) != 0x0)) { + return TRUE; + } + } + + return FALSE; } -static void DisableActiveCoreRGSyncObjects(NVDevEvoPtr pDevEvo, - NVDispHeadStateEvoPtr pHeadState, - NvU32 head, +static void DisableActiveCoreRGSyncObjects(NVDispEvoRec *pDispEvo, + const NvU32 apiHead, NVEvoUpdateState *pUpdateState) { - for (int i = 0; i < pHeadState->numVblankSyncObjectsCreated; i++) { - if (pHeadState->vblankSyncObjects[i].enabled) { + NVDevEvoRec *pDevEvo = pDispEvo->pDevEvo; + NVDispApiHeadStateEvoRec *pApiHeadState = &pDispEvo->apiHeadState[apiHead]; + + for (int i = 0; i < pApiHeadState->numVblankSyncObjectsCreated; i++) { + if (pApiHeadState->vblankSyncObjects[i].enabled) { + NvU32 head = nvGetPrimaryHwHead(pDispEvo, apiHead); + nvAssert(head != NV_INVALID_HEAD); + /* hCtxDma of 0 indicates Disable. */ pDevEvo->hal->ConfigureVblankSyncObject( pDevEvo, @@ -1490,181 +2203,328 @@ i, 0, /* hCtxDma */ pUpdateState); - pHeadState->vblankSyncObjects[i].enabled = FALSE; + pApiHeadState->vblankSyncObjects[i].enabled = FALSE; } } } +static void +ApplyProposedModeSetHwStateOneHeadShutDown( + NVDispEvoPtr pDispEvo, + NvU32 head, + const + NVProposedModeSetHwStateOneDisp + *pProposedDisp, + NVModeSetWorkArea *pWorkArea) +{ + NVDevEvoPtr pDevEvo = pDispEvo->pDevEvo; + const NvU32 sd = pDispEvo->displayOwner; + NVDispHeadStateEvoPtr pHeadState = &pDispEvo->headState[head]; + + nvHdmiDpEnableDisableAudio(pDispEvo, head, FALSE /* enable */); + + nvEvoDetachConnector(pHeadState->pConnectorEvo, head, + &pWorkArea->modesetUpdateState); + + nvEvoDisableHwYUV420Packer(pDispEvo, head, + &pWorkArea->modesetUpdateState.updateState); + + pHeadState->pConnectorEvo = NULL; + + pHeadState->bypassComposition = FALSE; + pHeadState->tilePosition = 0; + nvkms_memset(&pHeadState->timings, 0, sizeof(pHeadState->timings)); + pHeadState->activeRmId = 0; + + pHeadState->allowFlipLockGroup = 0; + + nvkms_memset(&pHeadState->audio, 0, sizeof(pHeadState->audio)); + + nvkms_memset(&pHeadState->modeValidationParams, 0, + sizeof(pHeadState->modeValidationParams)); + + nvkms_memset(&pDevEvo->gpus[sd].headState[head], 0, + sizeof(pDevEvo->gpus[sd].headState[head])); + + pDevEvo->gpus[sd].headState[head].cursor.cursorCompParams = + nvDefaultCursorCompositionParams(pDevEvo); + + for (NvU32 layer = 0; layer < pDevEvo->head[head].numLayers; layer++) { + nvEvoSetFlipOccurredEvent(pDispEvo, + head, + layer, + NULL, + &pWorkArea->modesetUpdateState); + } +} + /*! - * Send methods to shut down a head + * Send methods to shut down a api-head * * \param[in,out] pDispEvo The disp of the head. - * \param[in] head The head to consider. + * \param[in] apiHead The api head to consider. * \param[in] pProposedDisp The requested configuration of the display * \param[in/out] modesetUpdateState Structure tracking channels which need to * be updated/kicked off */ static void -ApplyProposedModeSetHwStateOneHeadShutDown( +ApplyProposedModeSetStateOneApiHeadShutDown( NVDispEvoPtr pDispEvo, - NvU32 head, + NvU32 apiHead, const NVProposedModeSetHwStateOneDisp *pProposedDisp, NVModeSetWorkArea *pWorkArea) { - NVDevEvoPtr pDevEvo = pDispEvo->pDevEvo; - NVDispHeadStateEvoPtr pHeadState; NVDpyEvoPtr pDpyEvo; - const NvU32 sd = pDispEvo->displayOwner; - NvU32 apiHead = nvHardwareHeadToApiHead(head); - NVDispApiHeadStateEvoRec *pApiHeadState = &pDispEvo->apiHeadState[apiHead]; + NVDispApiHeadStateEvoRec *pApiHeadState = + &pDispEvo->apiHeadState[apiHead]; + NvU32 head; /* * If nothing changed about this head's configuration, then we * should not shut it down. */ - if (!pProposedDisp->head[head].changed) { + if (!pProposedDisp->apiHead[apiHead].changed) { return; } /* * Otherwise, go through the shutdown process for any head that - * changed. If NVProposedModeSetHwStateOneHead::dpyIdList is + * changed. If NVProposedModeSetStateOneApiHead::dpyIdList is * empty, then we'll leave it shut down. If it is non-empty, then * ApplyProposedModeSetHwStateOneHead{Pre,Post}Update() will * update the head with its new configuration. */ - if (!nvHeadIsActive(pDispEvo, head)) { + if (!nvApiHeadIsActive(pDispEvo, apiHead)) { return; } - pHeadState = &pDispEvo->headState[head]; + nvAssert(pWorkArea->sd[pDispEvo->displayOwner]. + apiHead[apiHead].oldActiveRmId == 0); + + if (nvPopCount32(pApiHeadState->hwHeadsMask) > 1) { + nvEvoDisableMergeMode(pDispEvo, pApiHeadState->hwHeadsMask, + &pWorkArea->modesetUpdateState.updateState); + } + + FOR_EACH_EVO_HW_HEAD_IN_MASK(pApiHeadState->hwHeadsMask, head) { + const NVDispHeadStateEvoRec *pHeadState = + &pDispEvo->headState[head]; + + /* Track old activeRmId and free it after end modeset */ + if (pWorkArea->sd[pDispEvo->displayOwner].apiHead[apiHead].oldActiveRmId == 0) { + pWorkArea->sd[pDispEvo->displayOwner]. + apiHead[apiHead].oldActiveRmId = pHeadState->activeRmId; + } else { + nvAssert(pWorkArea->sd[pDispEvo->displayOwner]. + apiHead[apiHead].oldActiveRmId == pHeadState->activeRmId); + } + + ApplyProposedModeSetHwStateOneHeadShutDown(pDispEvo, head, + pProposedDisp, pWorkArea); + } + pDpyEvo = nvGetOneArbitraryDpyEvo(pApiHeadState->activeDpys, pDispEvo); + nvCancelSDRTransitionTimer(pApiHeadState); + /* * Identify and disable any active core RG sync objects. * * Note: the disable occurs at the hardware level; this intentionally does * not clear the software state tracking the existence of these sync * objects, which will be re-enabled at the hardware level in - * ApplyProposedModeSetHwStateOneHeadPreUpdate(), if the given head will be + * ApplyProposedModeSetStateOneApiHeadPreUpdate(), if the given head will be * active after the modeset. */ - DisableActiveCoreRGSyncObjects(pDevEvo, pHeadState, head, + DisableActiveCoreRGSyncObjects(pDispEvo, apiHead, &pWorkArea->modesetUpdateState.updateState); - nvDisable3DVisionAegis(pDpyEvo); + if (pApiHeadState->rmVBlankCallbackHandle != 0) { + nvRmRemoveVBlankCallback(pDispEvo, + pApiHeadState->rmVBlankCallbackHandle); + pApiHeadState->rmVBlankCallbackHandle = 0; + } - nvHdmiDpEnableDisableAudio(pDispEvo, head, FALSE /* enable */); + nvDisable3DVisionAegis(pDpyEvo); /* Cancel any pending LUT updates. */ - nvCancelLutUpdateEvo(pDispEvo, head); - - nvEvoDetachConnector(pHeadState->pConnectorEvo, head, &pWorkArea->modesetUpdateState); + nvCancelLutUpdateEvo(pDispEvo, apiHead); /* Clear software shadow state. */ - pWorkArea->sd[pDispEvo->displayOwner].changedDpyIdList = nvAddDpyIdListToDpyIdList( pApiHeadState->activeDpys, pWorkArea->sd[pDispEvo->displayOwner].changedDpyIdList); pApiHeadState->activeDpys = nvEmptyDpyIdList(); nvkms_memset(&pApiHeadState->timings, 0, sizeof(pApiHeadState->timings)); - pHeadState->pConnectorEvo = NULL; - - pHeadState->bypassComposition = FALSE; - nvkms_memset(&pHeadState->timings, 0, sizeof(pHeadState->timings)); - - /* Track old activeRmId and free it after end modeset */ - pWorkArea->sd[pDispEvo->displayOwner].head[head].oldActiveRmId = - pHeadState->activeRmId; - pHeadState->activeRmId = 0; - - pHeadState->allowFlipLockGroup = 0; - - nvkms_memset(&pHeadState->audio, 0, sizeof(pHeadState->audio)); - - nvkms_memset(&pHeadState->modeValidationParams, 0, - sizeof(pHeadState->modeValidationParams)); - - nvkms_memset(&pDevEvo->gpus[sd].headState[head], 0, - sizeof(pDevEvo->gpus[sd].headState[head])); - - pDevEvo->gpus[sd].headState[head].cursor.cursorCompParams = - nvDefaultCursorCompositionParams(pDevEvo); + nvkms_memset(&pApiHeadState->stereo, 0, sizeof(pApiHeadState->stereo)); pDpyEvo->apiHead = NV_INVALID_HEAD; + nvAssignHwHeadsMaskApiHeadState(pApiHeadState, 0x0); } static void -ApplyProposedModeSetHwStateOneDispFlip( +ApplyProposedModeSetStateOneDispFlip( NVDispEvoPtr pDispEvo, const NVProposedModeSetHwState *pProposed, const NVProposedModeSetHwStateOneDisp *pProposedDisp, NVEvoUpdateState *pUpdateState) { NVDevEvoPtr pDevEvo = pDispEvo->pDevEvo; - NvU32 head; - for (head = 0; head < pDispEvo->pDevEvo->numHeads; head++) { - const NVProposedModeSetHwStateOneHead *pProposedHead = - &pProposedDisp->head[head]; + for (NvU32 apiHead = 0; apiHead < pDevEvo->numApiHeads; apiHead++) { + const NVProposedModeSetStateOneApiHead *pProposedApiHead = + &pProposedDisp->apiHead[apiHead]; + const NVDpyEvoRec *pDpyEvo = + nvGetOneArbitraryDpyEvo(pProposedApiHead->dpyIdList, pDispEvo); const NvU32 sd = pDispEvo->displayOwner; + NvU32 head; /* - * If nothing changed about this head's configuration, then there - * is nothing to do. + * If nothing changed about this api-head's configuration or this + * api-head is disabled, then there is nothing to do. */ - if (!pProposedHead->changed) { + if (!pProposedApiHead->changed || + (pProposedApiHead->hwHeadsMask == 0)) { continue; } - /* Check for disabled heads. */ - if (pProposedHead->pConnectorEvo == NULL) { - continue; - } + nvAssert(pDpyEvo != NULL); + + FOR_EACH_EVO_HW_HEAD_IN_MASK(pProposedApiHead->hwHeadsMask, head) { + nvSetUsageBoundsEvo(pDevEvo, sd, head, + &pProposed->sd[sd].head[head].flip.usage, + pUpdateState); - nvSetUsageBoundsEvo(pDevEvo, sd, head, - &pProposed->sd[sd].head[head].flip.usage, - pUpdateState); + nvFlipEvoOneHead(pDevEvo, sd, head, + &pDpyEvo->parsedEdid.info.hdr_static_metadata_info, + &pProposed->sd[sd].head[head].flip, + FALSE /* allowFlipLock */, + pUpdateState); - nvFlipEvoOneHead(pDevEvo, sd, head, - &pProposed->sd[sd].head[head].flip, - FALSE /* allowFlipLock */, - pUpdateState); + if (pDevEvo->isSOCDisplay) { + pDevEvo->gpus[0].headState[head].preallocatedUsage = + pProposed->sd[sd].head[head].flip.usage; + } + } + + pDispEvo->apiHeadState[apiHead].viewPortPointIn = + pProposedApiHead->viewPortPointIn; } } -static void ReenableActiveCoreRGSyncObjects(NVDevEvoPtr pDevEvo, - NVDispHeadStateEvoPtr pHeadState, - NvU32 head, +static void ReEnableActiveCoreRGSyncObjects(NVDispEvoRec *pDispEvo, + const NvU32 apiHead, NVEvoUpdateState *pUpdateState) { - for (int i = 0; i < pHeadState->numVblankSyncObjectsCreated; i++) { - if (pHeadState->vblankSyncObjects[i].inUse) { + NVDevEvoRec *pDevEvo = pDispEvo->pDevEvo; + NvU32 head = nvGetPrimaryHwHead(pDispEvo, apiHead); + NVDispApiHeadStateEvoRec *pApiHeadState = &pDispEvo->apiHeadState[apiHead]; + + nvAssert(head != NV_INVALID_HEAD); + + for (int i = 0; i < pApiHeadState->numVblankSyncObjectsCreated; i++) { + if (pApiHeadState->vblankSyncObjects[i].inUse) { pDevEvo->hal->ConfigureVblankSyncObject( pDevEvo, - pHeadState->timings.rasterBlankStart.y, + pDispEvo->headState[head].timings.rasterBlankStart.y, head, i, - pHeadState->vblankSyncObjects[i].evoSyncpt.hCtxDma, + pApiHeadState->vblankSyncObjects[i].evoSyncpt.hCtxDma, pUpdateState); - pHeadState->vblankSyncObjects[i].enabled = TRUE; + pApiHeadState->vblankSyncObjects[i].enabled = TRUE; } } } +static void +ApplyProposedModeSetHwStateOneHeadPreUpdate( + NVDispEvoPtr pDispEvo, + const NVProposedModeSetStateOneApiHead *pProposedApiHead, + const NvU32 head, + const NvU32 isPrimaryHead, + const NVProposedModeSetHwStateOneHead *pProposedHead, + NvBool bypassComposition, + NVEvoModesetUpdateState *pModesetUpdateState) +{ + NVDispHeadStateEvoPtr pHeadState = &pDispEvo->headState[head]; + NVEvoUpdateState *updateState = &pModesetUpdateState->updateState; + + pHeadState->allowFlipLockGroup = pProposedApiHead->allowFlipLockGroup; + pHeadState->modeValidationParams = pProposedApiHead->modeValidationParams; + pHeadState->bypassComposition = bypassComposition; + pHeadState->activeRmId = pProposedApiHead->activeRmId; + pHeadState->pConnectorEvo = pProposedHead->pConnectorEvo; + pHeadState->tilePosition = pProposedHead->tilePosition; + pHeadState->timings = pProposedHead->timings; + pHeadState->dscInfo = pProposedApiHead->dscInfo; + pHeadState->hdmiFrlConfig = pProposedHead->hdmiFrlConfig; + pHeadState->pixelDepth = + nvEvoColorSpaceBpcToPixelDepth(pProposedApiHead->attributes.colorSpace, + pProposedApiHead->attributes.colorBpc); + pHeadState->audio = pProposedHead->audio; + + /* Update current LUT to hardware */ + nvEvoSetLUTContextDma(pDispEvo, head, updateState); + + nvEvoSetTimings(pDispEvo, head, updateState); + + nvSetDitheringEvo(pDispEvo, + head, + &pProposedApiHead->attributes.dithering, + updateState); + + nvEvoHeadSetControlOR(pDispEvo, head, updateState); + + /* Update hardware's current colorSpace and colorRange */ + nvUpdateCurrentHardwareColorSpaceAndRangeEvo(pDispEvo, + head, + pProposedApiHead->attributes.colorSpace, + pProposedApiHead->attributes.colorRange, + updateState); + + nvEvoAttachConnector(pProposedHead->pConnectorEvo, + head, + isPrimaryHead, + pProposedHead->pDpLibModesetState, + pModesetUpdateState); + + nvSetViewPortsEvo(pDispEvo, head, updateState); + + nvSetImageSharpeningEvo( + pDispEvo, + head, + pProposedApiHead->attributes.imageSharpening.value, + updateState); + + + nvSetDVCEvo(pDispEvo, head, + pProposedApiHead->attributes.dvc, + updateState); + + + nvHdmiFrlSetConfig(pDispEvo, head); + + if (isPrimaryHead) { + pHeadState->mergeModeVrrSecondaryHeadMask = + pProposedApiHead->hwHeadsMask & ~NVBIT(head); + } else { + pHeadState->mergeModeVrrSecondaryHeadMask = 0x0; + } +} + /*! - * Update the heads to be modified on this disp. + * Update the api heads to be modified on this disp. * * This should update the ASSY state of the head, but not trigger an * UPDATE method. * * \param[in,out] pDispEvo The disp of the head. - * \param[in] head The head to consider. + * \param[in] apiHead The api head to consider. * \param[in] pProposedHead The requested configuration of the head. * \param[in,out] updateState Indicates which channels require UPDATEs * \param[in] bypassComposition @@ -1672,40 +2532,41 @@ * composition pipeline bypass mode. */ static void -ApplyProposedModeSetHwStateOneHeadPreUpdate( +ApplyProposedModeSetStateOneApiHeadPreUpdate( NVDispEvoPtr pDispEvo, - NvU32 head, - const NVProposedModeSetHwState *pProposed, + const NvU32 apiHead, const NVProposedModeSetHwStateOneDisp *pProposedDisp, NVModeSetWorkArea *pWorkArea, NvBool bypassComposition) { - const NVProposedModeSetHwStateOneHead *pProposedHead = - &pProposedDisp->head[head]; + const NVDevEvoRec *pDevEvo = pDispEvo->pDevEvo; NVEvoModesetUpdateState *pModesetUpdateState = &pWorkArea->modesetUpdateState; NVEvoUpdateState *updateState = &pModesetUpdateState->updateState; - NVDispHeadStateEvoPtr pHeadState; - NVDpyEvoPtr pDpyEvo = - nvGetOneArbitraryDpyEvo(pProposedHead->dpyIdList, pDispEvo); - NvU32 apiHead = nvHardwareHeadToApiHead(head); NVDispApiHeadStateEvoRec *pApiHeadState = &pDispEvo->apiHeadState[apiHead]; + const NVProposedModeSetStateOneApiHead *pProposedApiHead = + &pProposedDisp->apiHead[apiHead]; + const NvU32 proposedPrimaryHead = + nvGetPrimaryHwHeadFromMask(pProposedApiHead->hwHeadsMask); + NVDpyEvoPtr pDpyEvo = + nvGetOneArbitraryDpyEvo(pProposedApiHead->dpyIdList, pDispEvo); + NvU32 head; /* * If nothing changed about this head's configuration, then there * is nothing to do. */ - if (!pProposedHead->changed) { + if (!pProposedApiHead->changed) { return; } /* Check for disabled heads. */ - if (pProposedHead->pConnectorEvo == NULL) { + if (nvDpyIdListIsEmpty(pProposedApiHead->dpyIdList)) { /* - * ApplyProposedModeSetHwStateOneHeadShutDown() should have + * ApplyProposedModeSetStateOneApiHeadShutDown() should have * already been called for this head. */ - nvAssert(!nvHeadIsActive(pDispEvo, head)); + nvAssert(!nvApiHeadIsActive(pDispEvo, apiHead)); return; } @@ -1714,92 +2575,88 @@ return; } + /* + * pDevEvo->apiHead[apiHead].numLayers is the number of layers which are + * visible to nvkms clients, and that number should be less than or equal + * to pDevEvo->head[proposedPrimaryHead].numLayers. + * + * If (pDevEvo->head[proposedPrimaryHead].numLayers > + * pDevEvo->apiHead[apiHead].numLayers) then the extra per hardware-head + * layers remain unused and there is no need to register the completion + * notifier callback for those extra per hardware-head layers. + */ + + nvAssert(pDevEvo->head[proposedPrimaryHead].numLayers >= + pDevEvo->apiHead[apiHead].numLayers); + + for (NvU32 layer = 0; layer < + pDevEvo->apiHead[apiHead].numLayers; layer++) { + nvEvoSetFlipOccurredEvent(pDispEvo, + proposedPrimaryHead, + layer, + pApiHeadState->flipOccurredEvent[layer]. + ref_ptr, + &pWorkArea->modesetUpdateState); + } + pApiHeadState->hwHeadsMask = pProposedApiHead->hwHeadsMask; pDpyEvo->apiHead = apiHead; - AssignSor(pWorkArea, pProposedHead->pConnectorEvo); + AssignSor(pDispEvo, pProposedApiHead, pWorkArea); nvDpyUpdateHdmiPreModesetEvo(pDpyEvo); - pHeadState = &pDispEvo->headState[head]; - - pHeadState->bypassComposition = bypassComposition; - - pHeadState->activeRmId = pProposedHead->activeRmId; - /* * Cache the list of active pDpys for this head, as well as the * mode timings. */ - pApiHeadState->activeDpys = pProposedHead->dpyIdList; - pApiHeadState->timings = pProposedHead->timings; + pApiHeadState->activeDpys = pProposedApiHead->dpyIdList; + pApiHeadState->timings = pProposedApiHead->timings; + pApiHeadState->stereo = pProposedApiHead->stereo; pWorkArea->sd[pDispEvo->displayOwner].changedDpyIdList = nvAddDpyIdListToDpyIdList( pApiHeadState->activeDpys, pWorkArea->sd[pDispEvo->displayOwner].changedDpyIdList); - nvAssert(pDpyEvo->pConnectorEvo == pProposedHead->pConnectorEvo); - pHeadState->pConnectorEvo = pProposedHead->pConnectorEvo; - - pHeadState->timings = pProposedHead->timings; - - pHeadState->audio = pProposedHead->audio; - pApiHeadState->infoFrame = pProposedHead->infoFrame; - - AssignProposedUsageOneHead(pDispEvo->pDevEvo, pProposed, head); + pApiHeadState->infoFrame = pProposedApiHead->infoFrame; - nvSendHwModeTimingsToAegisEvo(pDispEvo, head); + nvSendHwModeTimingsToAegisEvo(pDispEvo, apiHead); /* Set LUT settings */ - nvEvoSetLut(pDispEvo, head, FALSE /* kickoff */, &pProposedHead->lut); - - /* Update current LUT to hardware */ - nvEvoUpdateCurrentPalette(pDispEvo, head, FALSE /* kickoff */); - - nvEvoSetTimings(pDispEvo, head, updateState); - - nvSetDitheringEvo(pDispEvo, - head, - &pProposedHead->attributes.dithering, - updateState); - - nvEvoHeadSetControlOR(pDispEvo, head, updateState); - - /* Update hardware's current colorSpace and colorRange */ - nvUpdateCurrentHardwareColorSpaceAndRangeEvo(pDispEvo, - head, - pProposedHead->attributes.colorSpace, - pProposedHead->attributes.colorRange, - updateState); - - nvEvoAttachConnector(pProposedHead->pConnectorEvo, - head, - pProposedHead->pDpLibModesetState, - pModesetUpdateState); - - nvSetViewPortsEvo(pDispEvo, head, updateState); + nvEvoSetLut(pDispEvo, apiHead, FALSE /* kickoff */, &pProposedApiHead->lut); - nvSetImageSharpeningEvo( - pDispEvo, - head, - pProposedHead->attributes.imageSharpening.value, - updateState); + FOR_EACH_EVO_HW_HEAD_IN_MASK(pProposedApiHead->hwHeadsMask, head) { + const NvBool isPrimaryHead = (head == proposedPrimaryHead); + nvAssert(pDpyEvo->pConnectorEvo == + pProposedDisp->head[head].pConnectorEvo); - nvSetDVCEvo(pDispEvo, head, - pProposedHead->attributes.dvc, - updateState); - - - nvHdmiFrlSetConfig(pDispEvo, head); + ApplyProposedModeSetHwStateOneHeadPreUpdate(pDispEvo, pProposedApiHead, + head, isPrimaryHead, &pProposedDisp->head[head], + bypassComposition, pModesetUpdateState); + } /* * Re-enable any active sync objects, configuring them in accordance with * the new timings. */ - ReenableActiveCoreRGSyncObjects(pDispEvo->pDevEvo, pHeadState, head, - updateState); + ReEnableActiveCoreRGSyncObjects(pDispEvo, apiHead, updateState); - pApiHeadState->attributes = pProposedHead->attributes; + nvAssert(pApiHeadState->rmVBlankCallbackHandle == 0); + if (!nvListIsEmpty(&pApiHeadState->vblankCallbackList)) { + pApiHeadState->rmVBlankCallbackHandle = + nvRmAddVBlankCallback(pDispEvo, proposedPrimaryHead, + VBlankCallback, (void *)(NvUPtr)apiHead); + } + + pApiHeadState->attributes = pProposedApiHead->attributes; + pApiHeadState->tf = pProposedApiHead->tf; + pApiHeadState->hs10bpcHint = pProposedApiHead->hs10bpcHint; + + if (nvPopCount32(pProposedApiHead->hwHeadsMask) > 1) { + nvEvoEnableMergeModePreModeset(pDispEvo, + pProposedApiHead->hwHeadsMask, + &pModesetUpdateState->updateState); + } } @@ -1809,81 +2666,81 @@ * PreUpdate() will have already been called on this head, and an * UPDATE method sent. * - * \param[in,out] pDispEvo The disp of the head. - * \param[in] head The head to consider. - * \param[in] pProposedHead The requested configuration of the head. + * \param[in,out] pDispEvo The disp of the head. + * \param[in] apihead The api head to consider. + * \param[in] pProposedApiHead The requested configuration of the api head. */ static void -ApplyProposedModeSetHwStateOneHeadPostUpdate(NVDispEvoPtr pDispEvo, - NvU32 head, - const - NVProposedModeSetHwStateOneHead - *pProposedHead) +ApplyProposedModeSetStateOneApiHeadPostModesetUpdate( + NVDispEvoPtr pDispEvo, + NvU32 apiHead, + const NVProposedModeSetStateOneApiHead *pProposedApiHead, + NVEvoUpdateState *pUpdateState) { - NVDispHeadStateEvoRec *pHeadState; + NvU32 head; NVDpyEvoRec *pDpyEvo; - NvU32 apiHead = nvHardwareHeadToApiHead(head); NVDispApiHeadStateEvoRec *pApiHeadState = &pDispEvo->apiHeadState[apiHead]; /* * If nothing changed about this head's configuration, then there * is nothing to do. */ - if (!pProposedHead->changed) { + if (!pProposedApiHead->changed) { return; } - if (!nvHeadIsActive(pDispEvo, head)) { + if (!nvApiHeadIsActive(pDispEvo, apiHead)) { return; } - /* - * Cache configuration state in the headState, so that - * AssignProposedModeSetHwState() can preserve the configuration - * if this head is left alone in the next NvKmsSetModeRequest. - */ - pHeadState = &pDispEvo->headState[head]; + if (nvPopCount32(pProposedApiHead->hwHeadsMask) > 1) { + nvEvoEnableMergeModePostModeset(pDispEvo, + pProposedApiHead->hwHeadsMask, + pUpdateState); + } pDpyEvo = nvGetOneArbitraryDpyEvo(pApiHeadState->activeDpys, pDispEvo); nvAssert(pDpyEvo != NULL); - pHeadState->allowFlipLockGroup = pProposedHead->allowFlipLockGroup; - pHeadState->modeValidationParams = pProposedHead->modeValidationParams; - pApiHeadState->hs10bpcHint = pProposedHead->hs10bpcHint; - nvUpdateInfoFrames(pDpyEvo); /* Perform 3D vision authentication */ - nv3DVisionAuthenticationEvo(pDispEvo, head); + nv3DVisionAuthenticationEvo(pDispEvo, apiHead); - nvHdmiDpEnableDisableAudio(pDispEvo, head, TRUE /* enable */); + FOR_EACH_EVO_HW_HEAD_IN_MASK(pApiHeadState->hwHeadsMask, head) { + nvHdmiDpEnableDisableAudio(pDispEvo, head, TRUE /* enable */); + } } /* - * Shut down all heads that are incompatible with pProposedDisp. This + * Shut down all api-heads that are incompatible with pProposedDisp. This * requires doing an update immediately. */ static void -KickoffProposedModeSetHwStateIncompatibleHeadsShutDown( +KickoffProposedModeSetStateIncompatibleApiHeadsShutDown( NVDispEvoPtr pDispEvo, const NVProposedModeSetHwStateOneDisp *pProposedDisp, NVModeSetWorkArea *pWorkArea) { - NvU32 head; + const NVDevEvoRec *pDevEvo = pDispEvo->pDevEvo; NvBool foundIncompatibleHead = FALSE; NvU32 clearHdmiFrlActiveRmId[NVKMS_MAX_HEADS_PER_DISP] = { }; NVDpyIdList proposedActiveConnectorsList = nvEmptyDpyIdList(); NVDpyIdList currActiveConnectorsList = nvEmptyDpyIdList(); NVDpyIdList proposedInactiveConnectorList, unionOfActiveConnectorList; - for (head = 0; head < pDispEvo->pDevEvo->numHeads; head++) { - NVDpyId activeConnectorId = - (pDispEvo->headState[head].pConnectorEvo != NULL) ? - pDispEvo->headState[head].pConnectorEvo->displayId : + for (NvU32 apiHead = 0; apiHead < pDevEvo->numApiHeads; apiHead++) { + const NVDpyEvoRec *pActiveDpyEvo = + nvGetOneArbitraryDpyEvo(pDispEvo->apiHeadState[apiHead].activeDpys, + pDispEvo); + const NVDpyEvoRec *pProposedDpyEvo = + nvGetOneArbitraryDpyEvo(pProposedDisp->apiHead[apiHead].dpyIdList, + pDispEvo); + NVDpyId activeConnectorId = (pActiveDpyEvo != NULL) ? + pActiveDpyEvo->pConnectorEvo->displayId : nvInvalidDpyId(); - NVDpyId proposedConnectorId = - (pProposedDisp->head[head].pConnectorEvo != NULL) ? - pProposedDisp->head[head].pConnectorEvo->displayId : + NVDpyId proposedConnectorId = (pProposedDpyEvo != NULL) ? + pProposedDpyEvo->pConnectorEvo->displayId : nvInvalidDpyId(); currActiveConnectorsList = @@ -1902,15 +2759,21 @@ nvAddDpyIdListToDpyIdList(proposedActiveConnectorsList, currActiveConnectorsList); - for (head = 0; head < pDispEvo->pDevEvo->numHeads; head++) { + for (NvU32 apiHead = 0; apiHead < pDevEvo->numApiHeads; apiHead++) { NvBool thisHeadIncompatible = FALSE; - const NVConnectorEvoRec *pCurrConnectorEvo = - pDispEvo->headState[head].pConnectorEvo; - if (!pProposedDisp->head[head].changed || !nvHeadIsActive(pDispEvo, head)) { + if (!pProposedDisp->apiHead[apiHead].changed || + !nvApiHeadIsActive(pDispEvo, apiHead)) { continue; } + const NVDpyEvoRec *pCurrDpyEvo = + nvGetOneArbitraryDpyEvo(pDispEvo->apiHeadState[apiHead].activeDpys, + pDispEvo); + const NVConnectorEvoRec *pCurrConnectorEvo = + pCurrDpyEvo->pConnectorEvo; + + /* * If the number of current active connectors + proposed active * connectors is greater than number of heads then modeset is under @@ -1923,6 +2786,10 @@ * In this situation, all the connectors which are not going active * after modeset, mark them incompatible and shut down them before * triggering modeset on all the active connectors. + * + * [2Heads1OR] XXX This incompatibility check will not work because in + * the 2Heads1OR configuration two heads gets attached to a single + * connector. */ if (nvCountDpyIdsInDpyIdList(unionOfActiveConnectorList) > pDispEvo->pDevEvo->numHeads && @@ -1932,25 +2799,36 @@ } /* if the *new* timings are FRL, then we need to shut down the head. */ - if (pProposedDisp->head[head].timings.hdmiFrlConfig.frlRate != - HDMI_FRL_DATA_RATE_NONE) { + if (pProposedDisp->apiHead[apiHead].timings.protocol == + NVKMS_PROTOCOL_SOR_HDMI_FRL) { thisHeadIncompatible = TRUE; } /* if the *old* timings are FRL, then we need to shut down the head and * clear the FRL config. */ - if (pDispEvo->headState[head].timings.hdmiFrlConfig.frlRate != - HDMI_FRL_DATA_RATE_NONE) { + if (pDispEvo->apiHeadState[apiHead].timings.protocol == + NVKMS_PROTOCOL_SOR_HDMI_FRL) { + NvU32 head; thisHeadIncompatible = TRUE; /* cache the activeRmId since it will be cleared below, but * we don't want to actually call into the HDMI library until * afterwards. */ - clearHdmiFrlActiveRmId[head] = pDispEvo->headState[head].activeRmId; + FOR_EACH_EVO_HW_HEAD_IN_MASK( + pDispEvo->apiHeadState[apiHead].hwHeadsMask, + head) { + if (clearHdmiFrlActiveRmId[apiHead] == 0) { + clearHdmiFrlActiveRmId[apiHead] = + pDispEvo->headState[head].activeRmId; + } else { + nvAssert(clearHdmiFrlActiveRmId[apiHead] == + pDispEvo->headState[head].activeRmId); + } + } } - if (IsProposedModeSetHwStateOneHeadIncompatible(pDispEvo, - head, - pProposedDisp)) { + if (IsProposedModeSetStateOneApiHeadIncompatible(pDispEvo, + apiHead, + pProposedDisp)) { thisHeadIncompatible = TRUE; } @@ -1958,9 +2836,9 @@ continue; } - ApplyProposedModeSetHwStateOneHeadShutDown( + ApplyProposedModeSetStateOneApiHeadShutDown( pDispEvo, - head, + apiHead, pProposedDisp, pWorkArea); @@ -1970,11 +2848,11 @@ /* Submit UPDATE method and kick off, to shut down incompatible heads. */ if (foundIncompatibleHead) { KickoffModesetUpdateState(pDispEvo, &pWorkArea->modesetUpdateState); - for (head = 0; head < pDispEvo->pDevEvo->numHeads; head++) { - if (clearHdmiFrlActiveRmId[head] == 0) { + for (NvU32 apiHead = 0; apiHead < pDevEvo->numHeads; apiHead++) { + if (clearHdmiFrlActiveRmId[apiHead] == 0) { continue; } - nvHdmiFrlClearConfig(pDispEvo, clearHdmiFrlActiveRmId[head]); + nvHdmiFrlClearConfig(pDispEvo, clearHdmiFrlActiveRmId[apiHead]); } } } @@ -2002,23 +2880,22 @@ */ const NvBool decoupleFlipUpdates = pModesetUpdateState->windowMappingChanged; - NvU32 head; /* Send methods to shut down any other unused heads, but don't update yet. */ - for (head = 0; head < pDispEvo->pDevEvo->numHeads; head++) { - ApplyProposedModeSetHwStateOneHeadShutDown( + for (NvU32 apiHead = 0; apiHead < pDevEvo->numApiHeads; apiHead++) { + ApplyProposedModeSetStateOneApiHeadShutDown( pDispEvo, - head, + apiHead, pProposedDisp, pWorkArea); } /* Apply pre-UPDATE modifications for any enabled heads. */ - for (head = 0; head < pDispEvo->pDevEvo->numHeads; head++) { - ApplyProposedModeSetHwStateOneHeadPreUpdate( + for (NvU32 apiHead = 0; + apiHead < pDispEvo->pDevEvo->numApiHeads; apiHead++) { + ApplyProposedModeSetStateOneApiHeadPreUpdate( pDispEvo, - head, - pProposed, + apiHead, pProposedDisp, pWorkArea, bypassComposition); @@ -2026,7 +2903,7 @@ if (!decoupleFlipUpdates) { /* Merge modeset and flip state updates together */ - ApplyProposedModeSetHwStateOneDispFlip( + ApplyProposedModeSetStateOneDispFlip( pDispEvo, pProposed, pProposedDisp, @@ -2040,7 +2917,7 @@ if (decoupleFlipUpdates) { NVEvoUpdateState flipUpdateState = { }; - ApplyProposedModeSetHwStateOneDispFlip( + ApplyProposedModeSetStateOneDispFlip( pDispEvo, pProposed, pProposedDisp, @@ -2053,16 +2930,22 @@ nvRemoveUnusedHdmiDpAudioDevice(pDispEvo); - /* Apply post-UPDATE modifications for any enabled heads. */ - for (head = 0; head < pDispEvo->pDevEvo->numHeads; head++) { + { + NVEvoUpdateState updateState = { }; - const NVProposedModeSetHwStateOneHead *pProposedHead = - &pProposedDisp->head[head]; + /* Apply post-MODESET-UPDATE modifications for any enabled api-heads. */ + for (NvU32 apiHead = 0; apiHead < pDevEvo->numApiHeads; apiHead++) { + ApplyProposedModeSetStateOneApiHeadPostModesetUpdate( + pDispEvo, + apiHead, + &pProposedDisp->apiHead[apiHead], + &updateState); + } - ApplyProposedModeSetHwStateOneHeadPostUpdate( - pDispEvo, - head, - pProposedHead); + if (!nvIsUpdateStateEmpty(pDevEvo, &updateState)) { + pDevEvo->hal->Update(pDevEvo, &updateState, + TRUE /* releaseElv */); + } } } @@ -2190,7 +3073,7 @@ "Unexpectedly failed to lock to max DRAM pre-modeset!"); } - KickoffProposedModeSetHwStateIncompatibleHeadsShutDown( + KickoffProposedModeSetStateIncompatibleApiHeadsShutDown( pDispEvo, pProposedDisp, pWorkArea); @@ -2202,6 +3085,8 @@ bypassComposition, pWorkArea); + nvEvoLockStateSetMergeMode(pDispEvo); + /* * This function waits for 2 frames to make sure that the final IMP * arbitration settings have been programmed by the post-SV3 worker thread @@ -2261,14 +3146,14 @@ FOR_ALL_EVO_DISPLAYS(pDispEvo, dispIndex, pDevEvo) { - NvU32 head; + NvU32 apiHead; pReply->disp[dispIndex].status = NVKMS_SET_MODE_ONE_DISP_STATUS_SUCCESS; - for (head = 0; head < pDevEvo->numHeads; head++) { + for (apiHead = 0; apiHead < pDevEvo->numApiHeads; apiHead++) { - pReply->disp[dispIndex].head[head].status = + pReply->disp[dispIndex].head[apiHead].status = NVKMS_SET_MODE_ONE_HEAD_STATUS_SUCCESS; } } @@ -2299,7 +3184,7 @@ const struct NvKmsSetModeRequest *pRequest, struct NvKmsSetModeReply *pReply) { - NvU32 dispIndex, head; + NvU32 dispIndex, apiHead; NvBool ret = TRUE; const struct NvKmsModesetPermissions *pPermissions = @@ -2339,13 +3224,13 @@ ret = FALSE; } - for (head = 0; head < NVKMS_MAX_HEADS_PER_DISP; head++) { + for (apiHead = 0; apiHead < NVKMS_MAX_HEADS_PER_DISP; apiHead++) { - if ((pRequestDisp->requestedHeadsBitMask & (1 << head)) == 0) { + if ((pRequestDisp->requestedHeadsBitMask & (1 << apiHead)) == 0) { continue; } - if (head >= pDevEvo->numHeads) { + if (apiHead >= pDevEvo->numApiHeads) { pReply->disp[dispIndex].status = NVKMS_SET_MODE_ONE_DISP_STATUS_INVALID_REQUESTED_HEADS_BITMASK; ret = FALSE; @@ -2353,17 +3238,17 @@ } const NVDpyIdList permDpyIdList = - pPermissions->disp[dispIndex].head[head].dpyIdList; + pPermissions->disp[dispIndex].head[apiHead].dpyIdList; const struct NvKmsSetModeOneHeadRequest *pRequestHead = - &pRequestDisp->head[head]; + &pRequestDisp->head[apiHead]; /* * Does the client have permission to touch this head at * all? */ if (pRequest->commit && nvDpyIdListIsEmpty(permDpyIdList)) { - pReply->disp[dispIndex].head[head].status = + pReply->disp[dispIndex].head[apiHead].status = NVKMS_SET_MODE_ONE_HEAD_STATUS_INVALID_PERMISSIONS; ret = FALSE; continue; @@ -2384,7 +3269,7 @@ if (pRequest->commit && !nvDpyIdListIsASubSetofDpyIdList(pRequestHead->dpyIdList, permDpyIdList)) { - pReply->disp[dispIndex].head[head].status = + pReply->disp[dispIndex].head[apiHead].status = NVKMS_SET_MODE_ONE_HEAD_STATUS_INVALID_PERMISSIONS; ret = FALSE; continue; @@ -2396,14 +3281,14 @@ if (!nvDpyIdListIsASubSetofDpyIdList( pRequestHead->dpyIdList, pDevEvo->pDispEvo[dispIndex]->validDisplays)) { - pReply->disp[dispIndex].head[head].status = + pReply->disp[dispIndex].head[apiHead].status = NVKMS_SET_MODE_ONE_HEAD_STATUS_INVALID_DPY; ret = FALSE; continue; } if (!nvValidateSetLutCommonParams(pDevEvo, &pRequestHead->lut)) { - pReply->disp[dispIndex].head[head].status = + pReply->disp[dispIndex].head[apiHead].status = NVKMS_SET_MODE_ONE_HEAD_STATUS_INVALID_LUT; ret = FALSE; continue; @@ -2448,7 +3333,7 @@ * \param[out] pReply The reply to the client. */ static void -AssignReplySuccess(const NVDevEvoRec *pDevEvo, +AssignReplySuccess(NVDevEvoRec *pDevEvo, const struct NvKmsSetModeRequest *pRequest, struct NvKmsSetModeReply *pReply, const NVModeSetWorkArea *pWorkArea) @@ -2459,8 +3344,6 @@ nvkms_memset(pReply, 0, sizeof(*pReply)); FOR_ALL_EVO_DISPLAYS(pDispEvo, dispIndex, pDevEvo) { - - NvU32 head; const struct NvKmsSetModeOneDispRequest *pRequestDisp = &pRequest->disp[dispIndex]; @@ -2468,39 +3351,71 @@ continue; } - for (head = 0; head < pDevEvo->numHeads; head++) { - const NvU32 apiHead = nvHardwareHeadToApiHead(head); + for (NvU32 apiHead = 0; apiHead < pDevEvo->numApiHeads; apiHead++) { const struct NvKmsSetModeOneHeadRequest *pRequestHead = - &pRequestDisp->head[head]; + &pRequestDisp->head[apiHead]; struct NvKmsSetModeOneHeadReply *pReplyHead = - &pReply->disp[dispIndex].head[head]; + &pReply->disp[dispIndex].head[apiHead]; - if ((pRequestDisp->requestedHeadsBitMask & (1 << head)) == 0) { + if ((pRequestDisp->requestedHeadsBitMask & (1 << apiHead)) == 0) { continue; } pReplyHead->status = NVKMS_SET_MODE_ONE_HEAD_STATUS_SUCCESS; - if (nvDpyIdListIsEmpty(pRequestHead->dpyIdList)) { - pReplyHead->activeRmId = 0; - } else { - const NVDispHeadStateEvoRec *pHeadState = - &pDispEvo->headState[head]; - pReplyHead->activeRmId = pHeadState->activeRmId; - pReplyHead->possibleUsage = pHeadState->timings.viewPort.possibleUsage; - pReplyHead->guaranteedUsage = pHeadState->timings.viewPort.guaranteedUsage; + if (!nvDpyIdListIsEmpty(pRequestHead->dpyIdList)) { + const NVDispApiHeadStateEvoRec *pApiHeadState = + &pDispEvo->apiHeadState[apiHead]; + const NvU32 primaryHwHead = + nvGetPrimaryHwHeadFromMask(pApiHeadState->hwHeadsMask); + + nvAssert((pApiHeadState->hwHeadsMask != 0x0) && + (primaryHwHead != NV_INVALID_HEAD)); + + struct NvKmsUsageBounds *pTmpUsageBounds = + nvPreallocGet(pDevEvo, + PREALLOC_TYPE_MODE_SET_REPLY_TMP_USAGE_BOUNDS, + sizeof(*pTmpUsageBounds)); + NvU32 head; + + pReplyHead->possibleUsage = pDispEvo->headState[primaryHwHead]. + timings.viewPort.possibleUsage; + pReplyHead->guaranteedUsage = pDispEvo->headState[primaryHwHead]. + timings.viewPort.guaranteedUsage; + FOR_EACH_EVO_HW_HEAD_IN_MASK(pApiHeadState->hwHeadsMask, head) { + const NVDispHeadStateEvoRec *pHeadState = + &pDispEvo->headState[head]; + + nvIntersectUsageBounds(&pReplyHead->possibleUsage, + &pHeadState->timings.viewPort.possibleUsage, + pTmpUsageBounds); + pReplyHead->possibleUsage = *pTmpUsageBounds; + + nvIntersectUsageBounds(&pReplyHead->guaranteedUsage, + &pHeadState->timings.viewPort.guaranteedUsage, + pTmpUsageBounds); + pReplyHead->guaranteedUsage = *pTmpUsageBounds; + } + + nvPreallocRelease(pDevEvo, + PREALLOC_TYPE_MODE_SET_REPLY_TMP_USAGE_BOUNDS); + pReplyHead->usingHeadSurface = (pDispEvo->pHsChannel[apiHead] != NULL); pReplyHead->vrrEnabled = - (pDispEvo->headState[head].timings.vrr.type != + (pApiHeadState->timings.vrr.type != NVKMS_DPY_VRR_TYPE_NONE); + pReplyHead->hwHead = primaryHwHead; + + FillPostSyncptReplyForModeset( + pDevEvo, + primaryHwHead, + &pRequestHead->flip, + &pReplyHead->flipReply, + &pWorkArea->sd[dispIndex].head[primaryHwHead].newState); + } else { + pReplyHead->hwHead = NV_INVALID_HEAD; } - FillPostSyncptReplyForModeset( - pDevEvo, - head, - &pRequestHead->flip, - &pReplyHead->flipReply, - &pWorkArea->sd[dispIndex].head[head].newState); } } } @@ -2523,12 +3438,16 @@ NvU32 dispIndex; FOR_ALL_EVO_DISPLAYS(pDispEvo, dispIndex, pDevEvo) { - NvU32 head, dpyMask = 0; + const NVProposedModeSetHwStateOneDisp *pProposedDisp = + &pProposed->disp[dispIndex]; + NvU32 apiHead, dpyMask = 0; /* Compute dpyMask: take all the dpyIds on this dispIndex. */ - for (head = 0; head < NVKMS_MAX_HEADS_PER_DISP; head++) { - dpyMask |= - nvDpyIdListToNvU32(pProposed->disp[dispIndex].head[head].dpyIdList); + for (apiHead = 0; apiHead < + ARRAY_LEN(pProposedDisp->apiHead); apiHead++) { + const NVProposedModeSetStateOneApiHead *pProposedApiHead = + &pProposedDisp->apiHead[apiHead]; + dpyMask |= nvDpyIdListToNvU32(pProposedApiHead->dpyIdList); } nvRmBeginEndModeset(pDispEvo, beginOrEnd, dpyMask); @@ -2802,7 +3721,7 @@ bypassComposition); } - nvEnableVrr(pDevEvo, pRequest); + nvEnableVrr(pDevEvo); /* * Cache whether HS in NVKMS is allowed, so we can make consistent @@ -2827,8 +3746,6 @@ pDevEvo->modesetOwnerChanged = FALSE; FOR_ALL_EVO_DISPLAYS(pDispEvo, dispIndex, pDevEvo) { - NvU32 head; - /* * In case of successful commit, update current attribute values and * free old display IDs. @@ -2841,11 +3758,11 @@ nvDpyUpdateCurrentAttributes(pDpyEvo); } - for (head = 0; head < pDevEvo->numHeads; head++) { - if (pWorkArea->sd[dispIndex].head[head].oldActiveRmId != 0x0) { + for (NvU32 apiHead = 0; apiHead < pDevEvo->numApiHeads; apiHead++) { + if (pWorkArea->sd[dispIndex].apiHead[apiHead].oldActiveRmId != 0x0) { nvRmFreeDisplayId( pDispEvo, - pWorkArea->sd[dispIndex].head[head].oldActiveRmId); + pWorkArea->sd[dispIndex].apiHead[apiHead].oldActiveRmId); } } } @@ -2878,7 +3795,7 @@ * Register a callback to activate when vblank is reached on a given head. * * \param[in,out] pDispEvo The display engine to register the callback on. - * \param[in] head The head to register the callback on. + * \param[in] apiHead The api head to register the callback on. * \param[in] pCallback The function to call when vblank is reached on the * provided pDispEvo+head combination. * \param[in] pUserData A pointer to caller-provided custom data. @@ -2886,11 +3803,20 @@ * \return Returns a pointer to a NVVBlankCallbackRec structure if the * registration was successful. Otherwise, return NULL. */ -NVVBlankCallbackPtr nvRegisterVBlankCallback(NVDispEvoPtr pDispEvo, - NvU32 head, - NVVBlankCallbackProc pCallback, - void *pUserData) +NVVBlankCallbackPtr +nvApiHeadRegisterVBlankCallback(NVDispEvoPtr pDispEvo, + const NvU32 apiHead, + NVVBlankCallbackProc pCallback, + void *pUserData) { + /* + * All the hardware heads mapped on the input api head should be + * rasterlocked, and should trigger vblank callback exactly at same time; + * therefore it is sufficient to register vblank callback only with the + * primary hardware head. + */ + const NvU32 head = nvGetPrimaryHwHead(pDispEvo, apiHead); + NVDispApiHeadStateEvoRec *pApiHeadState = &pDispEvo->apiHeadState[apiHead]; NVVBlankCallbackPtr pVBlankCallback = NULL; pVBlankCallback = nvCalloc(1, sizeof(*pVBlankCallback)); @@ -2900,84 +3826,65 @@ pVBlankCallback->pCallback = pCallback; pVBlankCallback->pUserData = pUserData; + pVBlankCallback->apiHead = apiHead; nvListAppend(&pVBlankCallback->vblankCallbackListEntry, - &pDispEvo->headState[head].vblankCallbackList); + &pApiHeadState->vblankCallbackList); - // If this is the first entry in the list, register the vblank callback - if (pDispEvo->headState[head].rmVBlankCallbackHandle == 0) { + nvAssert((head != NV_INVALID_HEAD) || + (pApiHeadState->rmVBlankCallbackHandle == 0)); - pDispEvo->headState[head].rmVBlankCallbackHandle = - nvRmAddVBlankCallback(pDispEvo, - head, - VBlankCallback); + // If this is the first entry in the list, register the vblank callback + if ((head != NV_INVALID_HEAD) && + (pApiHeadState->rmVBlankCallbackHandle == 0)) { + pApiHeadState->rmVBlankCallbackHandle = + nvRmAddVBlankCallback(pDispEvo, head, VBlankCallback, + (void *)(NvUPtr)apiHead); } - return pVBlankCallback; -} -NVVBlankCallbackPtr -nvApiHeadRegisterVBlankCallback(NVDispEvoPtr pDispEvo, - const NvU32 apiHead, - NVVBlankCallbackProc pCallback, - void *pUserData) -{ - /* - * All the hardware heads mapped on the input api head should be - * rasterlocked, and should trigger vblank callback exactly at same time; - * therefore it is sufficient to register vblank callback only with the - * primary hardware head. - */ - const NvU32 head = nvGetPrimaryHwHead(pDispEvo, apiHead); - if (head == NV_INVALID_HEAD) { - return NULL; - } - return nvRegisterVBlankCallback(pDispEvo, head, pCallback, pUserData); + return pVBlankCallback; } /*! - * Un-register a vblank callback for a given head. + * Un-register a vblank callback for a given api head. * * \param[in,out] pDispEvo The display engine to register the callback on. - * \param[in] head The head to register the callback on. * \param[in] pCallback A pointer to the NVVBlankCallbackRec to un-register. * */ -void nvUnregisterVBlankCallback(NVDispEvoPtr pDispEvo, - NvU32 head, - NVVBlankCallbackPtr pCallback) +void nvApiHeadUnregisterVBlankCallback(NVDispEvoPtr pDispEvo, + NVVBlankCallbackPtr pCallback) { + const NvU32 apiHead = pCallback->apiHead; + NVDispApiHeadStateEvoRec *pApiHeadState = &pDispEvo->apiHeadState[apiHead]; + const NvU32 head = nvGetPrimaryHwHead(pDispEvo, apiHead); + nvListDel(&pCallback->vblankCallbackListEntry); nvFree(pCallback); + nvAssert((head != NV_INVALID_HEAD) || + (pApiHeadState->rmVBlankCallbackHandle == 0)); + // If there are no more callbacks, disable the RM-level callback - if (nvListIsEmpty(&pDispEvo->headState[head].vblankCallbackList)) { + if (nvListIsEmpty(&pApiHeadState->vblankCallbackList) && + (head != NV_INVALID_HEAD) && + (pApiHeadState->rmVBlankCallbackHandle != 0)) { nvRmRemoveVBlankCallback(pDispEvo, - pDispEvo->headState[head].rmVBlankCallbackHandle); - - pDispEvo->headState[head].rmVBlankCallbackHandle = 0; - } -} - -void nvApiHeadUnregisterVBlankCallback(NVDispEvoPtr pDispEvo, - const NvU32 apiHead, - NVVBlankCallbackPtr pCallback) -{ - const NvU32 head = nvGetPrimaryHwHead(pDispEvo, apiHead); - if (head == NV_INVALID_HEAD) { - return; + pApiHeadState->rmVBlankCallbackHandle); + pApiHeadState->rmVBlankCallbackHandle = 0; } - nvUnregisterVBlankCallback(pDispEvo, head, pCallback); } /*! - * Perform a modeset that disables some or all heads. + * Perform a modeset that disables some or all api heads. * * \param[in] pDevEvo The device to shut down. * \param[in] pTestFunc The pointer to test function, identifying heads * targeted to shut down. If NULL then shut down * all heads. */ -void nvShutDownHeads(NVDevEvoPtr pDevEvo, NVShutDownHeadsTestFunc pTestFunc) +void nvShutDownApiHeads(NVDevEvoPtr pDevEvo, + NVShutDownApiHeadsTestFunc pTestFunc) { if (pDevEvo->displayHandle != 0) { struct NvKmsSetModeParams *params = @@ -2992,20 +3899,20 @@ req = ¶ms->request; FOR_ALL_EVO_DISPLAYS(pDispEvo, dispIndex, pDevEvo) { - NvU32 head; + NvU32 apiHead; req->requestedDispsBitMask |= NVBIT(dispIndex); - for (head = 0; head < pDevEvo->numHeads; head++) { + for (apiHead = 0; apiHead < pDevEvo->numApiHeads; apiHead++) { /* * XXX pTestFunc isn't honored by nvSetDispModeEvo()'s * InheritPreviousModesetState() logic. */ - if (pTestFunc && !pTestFunc(pDispEvo, head)) { + if (pTestFunc && !pTestFunc(pDispEvo, apiHead)) { continue; } dirty = TRUE; - req->disp[dispIndex].requestedHeadsBitMask |= NVBIT(head); + req->disp[dispIndex].requestedHeadsBitMask |= NVBIT(apiHead); } } @@ -3029,7 +3936,7 @@ if (pDevEvo->coreInitMethodsPending) { FOR_ALL_EVO_DISPLAYS(pDispEvo, dispIndex, pDevEvo) { req->disp[dispIndex].requestedHeadsBitMask |= - NVBIT(pDevEvo->numHeads) - 1; + NVBIT(pDevEvo->numApiHeads) - 1; } } @@ -3046,10 +3953,11 @@ } } -NvU32 -nvApiHeadAddRgLine1Callback(const NVDispEvoRec *pDispEvo, +NVRgLine1CallbackPtr +nvApiHeadAddRgLine1Callback(NVDispEvoRec *pDispEvo, const NvU32 apiHead, - NV0092_REGISTER_RG_LINE_CALLBACK_FN pCallback) + NVRgLine1CallbackProc pCallbackProc, + void *pUserData) { /* * All the hardware heads mapped on the input api head should be @@ -3061,5 +3969,23 @@ if (head == NV_INVALID_HEAD) { return FALSE; } - return nvRmAddRgLine1Callback(pDispEvo, head, pCallback); + return nvRmAddRgLine1Callback(pDispEvo, head, pCallbackProc, pUserData); +} + + +void nvApiHeadGetScanLine(const NVDispEvoRec *pDispEvo, + const NvU32 apiHead, + NvU16 *pScanLine, + NvBool *pInBlankingPeriod) +{ + /* + * All the hardware heads mapped on the input api head should be + * rasterlocked; therefore it is sufficient to get scanline only for the + * primary hardware head. + */ + const NvU32 head = nvGetPrimaryHwHead(pDispEvo, apiHead); + + nvAssert(head != NV_INVALID_HEAD); + pDispEvo->pDevEvo->hal->GetScanLine(pDispEvo, head, pScanLine, + pInBlankingPeriod); } diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia-modeset/src/nvkms-prealloc.c nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia-modeset/src/nvkms-prealloc.c --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia-modeset/src/nvkms-prealloc.c 2023-10-25 20:22:41.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia-modeset/src/nvkms-prealloc.c 2024-03-05 22:12:23.000000000 +0000 @@ -50,8 +50,18 @@ case PREALLOC_TYPE_VALIDATE_MODE_HW_MODE_TIMINGS: /* fallthrough */ case PREALLOC_TYPE_HS_INIT_CONFIG_HW_TIMINGS: return sizeof(NVHwModeTimingsEvo); + case PREALLOC_TYPE_VALIDATE_MODE_HDMI_FRL_CONFIG: + return sizeof(HDMI_FRL_CONFIG); + case PREALLOC_TYPE_VALIDATE_MODE_DSC_INFO: + return sizeof(NVDscInfoEvoRec); case PREALLOC_TYPE_HS_PATCHED_MODESET_REQUEST: return sizeof(struct NvKmsSetModeRequest); + case PREALLOC_TYPE_MODE_SET_REPLY_TMP_USAGE_BOUNDS: + return sizeof(struct NvKmsUsageBounds); + case PREALLOC_TYPE_VALIDATE_MODE_IMP_OUT_HW_MODE_TIMINGS: + return sizeof(NVHwModeTimingsEvo) * NVKMS_MAX_HEADS_PER_DISP; + case PREALLOC_TYPE_VALIDATE_MODE_TMP_USAGE_BOUNDS: + return sizeof(struct NvKmsUsageBounds); case PREALLOC_TYPE_MAX: /* Not a real option, but added for -Wswitch-enum */ break; diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia-modeset/src/nvkms-rm.c nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia-modeset/src/nvkms-rm.c --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia-modeset/src/nvkms-rm.c 2023-10-25 20:22:41.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia-modeset/src/nvkms-rm.c 2024-03-05 22:12:23.000000000 +0000 @@ -88,6 +88,8 @@ #include "displayport/dpcd.h" +#define NVKMS_SYNCPT_ID_INVALID (0xFFFFFFFF) + static NvU32 GetLegacyConnectorType(NVDispEvoPtr pDispEvo, NVDpyId dpyId); static void RmFreeEvoChannel(NVDevEvoPtr pDevEvo, NVEvoChannelPtr pChannel); @@ -276,31 +278,31 @@ static void FreeDisplay(NVDispEvoPtr pDispEvo) { - NvU32 head; - if (pDispEvo == NULL) { return; } - for (head = 0; head < ARRAY_LEN(pDispEvo->pSwapGroup); head++) { + nvAssert(pDispEvo->vrrSetTimeoutEventUsageCount == 0); + nvAssert(pDispEvo->vrrSetTimeoutEventHandle == 0); + #if defined(DEBUG) - const NvU32 apiHead = nvHardwareHeadToApiHead(head); + for (NvU32 apiHead = 0; + apiHead < ARRAY_LEN(pDispEvo->pSwapGroup); apiHead++) { nvAssert(pDispEvo->pSwapGroup[apiHead] == NULL); -#endif - nvAssert(nvListIsEmpty(&pDispEvo->headState[head].vblankCallbackList)); } +#endif nvAssert(nvListIsEmpty(&pDispEvo->dpyList)); nvkms_free_ref_ptr(pDispEvo->ref_ptr); + nvInvalidateTopologiesEvo(); nvFree(pDispEvo); } static inline NVDispEvoPtr AllocDisplay(NVDevEvoPtr pDevEvo) { - NvU32 head; NVDispEvoPtr pDispEvo = nvCalloc(1, sizeof(NVDispEvoRec)); if (pDispEvo == NULL) { @@ -316,10 +318,6 @@ pDispEvo->framelock.clients = nvEmptyDpyIdList(); pDispEvo->framelock.currentServerHead = NV_INVALID_HEAD; - for (head = 0; head < ARRAY_LEN(pDispEvo->headState); head++) { - nvListInit(&pDispEvo->headState[head].vblankCallbackList); - } - pDispEvo->ref_ptr = nvkms_alloc_ref_ptr(pDispEvo); if (!pDispEvo->ref_ptr) { goto fail; @@ -737,46 +735,6 @@ pConnectorEvo->dfpInfo = GetDfpInfo(pConnectorEvo); - /* - * Change-list 6909651 has disabled YCbCr* color space for DisplayPort, it - * says - - * "Disable anything other than RGB for DisplayPort; on FERMI at least, - * there are problems YCbCr* on DP (but not HDMI), since the limited range - * must be implemented by EVO HW, and not the LUT (per EVO error checks)." - * - * TODO Investigate if YCbCr* color space for DisplayPort allowed on Kepler - * onward (also take DP-MST into consideration). - */ - if (!nvConnectorUsesDPLib(pConnectorEvo)) { - /* check for color space (YCbCr422, YCbCr444) capability of GPU */ - if (FLD_TEST_DRF(0073, _CTRL_DFP_FLAGS_FORMAT, _YCBCR422_CAPABLE, _TRUE, - pConnectorEvo->dfpInfo)) { - pConnectorEvo->colorSpaceCaps.ycbcr422Capable = TRUE; - } - - if (FLD_TEST_DRF(0073, _CTRL_DFP_FLAGS_FORMAT, _YCBCR444_CAPABLE, _TRUE, - pConnectorEvo->dfpInfo)) { - pConnectorEvo->colorSpaceCaps.ycbcr444Capable = TRUE; - } - } else { - pConnectorEvo->colorSpaceCaps.ycbcr422Capable = FALSE; - pConnectorEvo->colorSpaceCaps.ycbcr444Capable = FALSE; - } - - if (pConnectorEvo->signalFormat == NVKMS_CONNECTOR_SIGNAL_FORMAT_DSI) { - nvAssert(pDevEvo->numHeads >= 1); - // DSI supports only HEAD0 assignment - pConnectorEvo->validHeadMask = 0x1; - - if (pConnectorEvo->type != NVKMS_CONNECTOR_TYPE_DSI) { - nvEvoLogDisp(pDispEvo, EVO_LOG_ERROR, - "Mismatch between connector type and signal format for DSI!"); - goto fail; - } - } else { - pConnectorEvo->validHeadMask = (1 << pDevEvo->numHeads) - 1; - } - /* Assign connector indices. */ pConnectorEvo->legacyType = @@ -1176,11 +1134,11 @@ } else { // Track the SOR assignment for this connector. See the comment in // nvRmGetConnectorORInfo() for why this is deferred until now. - nvAssert(pConnectorEvo->or.mask == 0x0); - pConnectorEvo->or.mask |= NVBIT(params.index); + nvAssert(pConnectorEvo->or.primary == NV_INVALID_OR); + pConnectorEvo->or.primary = params.index; } } - nvAssert((pConnectorEvo->or.mask & NVBIT(params.index)) != 0x0); + nvAssert(pConnectorEvo->or.primary == params.index); pHeadState = &pDispEvo->headState[head]; @@ -2062,7 +2020,8 @@ return; } pConnectorEvo->or.type = NV0073_CTRL_SPECIFIC_OR_TYPE_DAC; - pConnectorEvo->or.mask = 0; + pConnectorEvo->or.primary = NV_INVALID_OR; + pConnectorEvo->or.secondaryMask = 0; pConnectorEvo->or.protocol = NV0073_CTRL_SPECIFIC_OR_PROTOCOL_DAC_RGB_CRT; pConnectorEvo->or.ditherType = NV0073_CTRL_SPECIFIC_OR_DITHER_TYPE_OFF; @@ -2085,9 +2044,11 @@ // // All we really need to know is which SOR is assigned to the boot // display, so we defer the query to MarkConnectorBootHeadActive(). - pConnectorEvo->or.mask = 0x0; + pConnectorEvo->or.secondaryMask = 0x0; + pConnectorEvo->or.primary = NV_INVALID_OR; } else { - pConnectorEvo->or.mask = NVBIT(params.index); + pConnectorEvo->or.secondaryMask = 0x0; + pConnectorEvo->or.primary = params.index; } pConnectorEvo->or.protocol = params.protocol; pConnectorEvo->or.ditherType = params.ditherType; @@ -2095,7 +2056,7 @@ pConnectorEvo->or.location = params.location; } else { nvAssert(pConnectorEvo->or.type == params.type); - nvAssert((pConnectorEvo->or.mask & NVBIT(params.index)) != 0x0); + nvAssert(pConnectorEvo->or.primary == params.index); nvAssert(pConnectorEvo->or.protocol == params.protocol); nvAssert(pConnectorEvo->or.ditherType == params.ditherType); nvAssert(pConnectorEvo->or.ditherAlgo == params.ditherAlgo); @@ -2253,11 +2214,11 @@ NV5070_CTRL_CMD_SET_DAC_PWR_PARAMS powerParams = { { 0 }, 0 }; powerParams.base.subdeviceIndex = pDispEvo->displayOwner; - if (pConnectorEvo->or.mask == 0x0) { - nvAssert(pConnectorEvo->or.mask != 0x0); + if (pConnectorEvo->or.primary == NV_INVALID_OR) { + nvAssert(pConnectorEvo->or.primary != NV_INVALID_OR); return FALSE; } - powerParams.orNumber = nvEvoConnectorGetPrimaryOr(pConnectorEvo); + powerParams.orNumber = pConnectorEvo->or.primary; switch (value) { case NV_KMS_DPY_ATTRIBUTE_DPMS_ON: @@ -2622,24 +2583,6 @@ } } -static void -CompletionNotifierEventDeferredWork(void *dataPtr, NvU32 dataU32) -{ - NVEvoChannelPtr pChannel = dataPtr; - - nvSendFlipOccurredEventEvo(pChannel->pb.pDevEvo, pChannel->channelMask); -} - -static void CompletionNotifierEvent(void *arg, void *pEventDataVoid, - NvU32 hEvent, NvU32 Data, NV_STATUS Status) -{ - (void) nvkms_alloc_timer_with_ref_ptr( - CompletionNotifierEventDeferredWork, /* callback */ - arg, /* argument (this is a ref_ptr to a pChannel) */ - 0, /* dataU32 */ - 0); /* timeout: schedule the work immediately */ -} - /*****************************************************************************/ /* RmAllocEvoChannel () * Allocates the EVO channel and associated notifier surfaces and ctxdmas. @@ -2793,30 +2736,6 @@ buffer->pDevEvo = pDevEvo; buffer->currentSubDevMask = SUBDEVICE_MASK_ALL; - if (!FLD_TEST_DRF64(_EVO, _CHANNEL_MASK, _CORE, _ENABLE, channelMask)) { - pChannel->ref_ptr = nvkms_alloc_ref_ptr(pChannel); - - if (pChannel->ref_ptr == NULL) { - goto fail; - } - - pChannel->completionNotifierEventHandle = - nvGenerateUnixRmHandle(&pDevEvo->handleAllocator); - - if (!nvRmRegisterCallback(pDevEvo, - &pChannel->completionNotifierEventCallback, - pChannel->ref_ptr, - pChannel->pb.channel_handle, - pChannel->completionNotifierEventHandle, - CompletionNotifierEvent, - 0)) { - nvFreeUnixRmHandle(&pDevEvo->handleAllocator, - pChannel->completionNotifierEventHandle); - pChannel->completionNotifierEventHandle = 0; - goto fail; - } - } - pChannel->imm.type = NV_EVO_IMM_CHANNEL_NONE; pDevEvo->hal->InitChannel(pDevEvo, pChannel); @@ -2918,8 +2837,6 @@ pChannel->completionNotifierEventHandle = 0; } - nvkms_free_ref_ptr(pChannel->ref_ptr); - for (sd = 0; sd < pDevEvo->numSubDevices; sd++) { if (pChannel->pb.control[sd]) { if (nvRmApiUnmapMemory(nvEvoGlobal.clientHandle, @@ -3176,6 +3093,9 @@ return FALSE; } + /*! Set syncpt id to invalid to avoid un-intended Free */ + pEvoSyncptOut->id = NVKMS_SYNCPT_ID_INVALID; + /* * HW engine on Orin is called HOST1X, all syncpts are in internal RAM of * HOST1X. @@ -3187,13 +3107,18 @@ return FALSE; } id = params.alloc.id; - result = nvRmEvoAllocAndBindSyncpt( - pDevEvo, pChannel, id, &hSyncpt, &hSyncptCtxDma); + + /* Post syncpt max val is tracked locally. Init the value here. */ + params.read_minval.id = id; + result = nvkms_syncpt_op(NVKMS_SYNCPT_OP_READ_MINVAL, ¶ms); if (!result) { - /*! put back syncpt as register failed */ - params.put.id = id; - nvkms_syncpt_op(NVKMS_SYNCPT_OP_PUT, ¶ms); - return FALSE; + goto failed; + } + + result = nvRmEvoAllocAndBindSyncpt(pDevEvo, pChannel, id, + &hSyncpt, &hSyncptCtxDma); + if (!result) { + goto failed; } /*! Populate syncpt values to return. */ @@ -3201,7 +3126,15 @@ pEvoSyncptOut->hCtxDma = hSyncptCtxDma; pEvoSyncptOut->hSyncpt = hSyncpt; pEvoSyncptOut->channelMask = pChannel->channelMask; + pEvoSyncptOut->syncptMaxVal = params.read_minval.minval; + return TRUE; + +failed: + /*! put back syncpt as operation failed */ + params.put.id = id; + nvkms_syncpt_op(NVKMS_SYNCPT_OP_PUT, ¶ms); + return FALSE; } static NvBool AllocPostSyncptPerChannel(NVDevEvoPtr pDevEvo, @@ -3217,7 +3150,7 @@ NvBool nvRMAllocateWindowChannels(NVDevEvoPtr pDevEvo) { int index; - NvU32 window; + NvU32 window, sd; static const struct { NvU32 windowClass; @@ -3258,6 +3191,18 @@ return FALSE; } + for (sd = 0; sd < pDevEvo->numSubDevices; sd++) { + NvU32 ret = nvRmEvoBindDispContextDMA(pDevEvo, + pDevEvo->window[window], + pDevEvo->window[window]->notifiersDma[sd].ctxHandle); + if (ret != NVOS_STATUS_SUCCESS) { + nvEvoLogDev(pDevEvo, EVO_LOG_ERROR, + "Failed to bind(window channel) display engine notify context DMA: 0x%x (%s)", + ret, nvstatusToString(ret)); + return FALSE; + } + } + if (!AllocImmediateChannelDma(pDevEvo, pDevEvo->window[window], c->immClass)) { return FALSE; @@ -3345,7 +3290,7 @@ } /* Pre-allocate the vblank syncpts, store in NVDispHeadStateEvoRec. */ -static void AllocCoreRGSyncpts(NVDevEvoPtr pDevEvo) +void nvRmAllocCoreRGSyncpts(NVDevEvoPtr pDevEvo) { NVDispEvoPtr pDispEvo = NULL; @@ -3361,21 +3306,22 @@ pDispEvo = pDevEvo->pDispEvo[0]; /* Initialize all heads' vblank sync object counts to zero. */ - for (int i = 0; i < pDevEvo->numHeads; i++) { - pDispEvo->headState[i].numVblankSyncObjectsCreated = 0; + for (int i = 0; i < pDevEvo->numApiHeads; i++) { + pDispEvo->apiHeadState[i].numVblankSyncObjectsCreated = 0; } /* For each core RG syncpt index: */ for (syncptIdx = 0; syncptIdx < NVKMS_MAX_VBLANK_SYNC_OBJECTS_PER_HEAD; syncptIdx++) { /* For each Head: */ - for (int i = 0; i < pDevEvo->numHeads; i++) { + for (int i = 0; i < pDevEvo->numApiHeads; i++) { NvBool result = FALSE; - NVDispHeadStateEvoPtr pHeadState = &pDispEvo->headState[i]; + NVDispApiHeadStateEvoRec *pApiHeadState = + &pDispEvo->apiHeadState[i]; result = AllocSyncpt(pDevEvo, pDevEvo->core, - &pHeadState->vblankSyncObjects[syncptIdx].evoSyncpt); + &pApiHeadState->vblankSyncObjects[syncptIdx].evoSyncpt); if (!result) { /* * Stop trying to allocate more syncpts if none are @@ -3388,9 +3334,9 @@ } /* Populate the index of the syncpt in the NVVblankSyncObjectRec. */ - pHeadState->vblankSyncObjects[syncptIdx].index = syncptIdx; + pApiHeadState->vblankSyncObjects[syncptIdx].index = syncptIdx; /* Update the count. */ - pHeadState->numVblankSyncObjectsCreated = syncptIdx + 1; + pApiHeadState->numVblankSyncObjectsCreated = syncptIdx + 1; } } } @@ -3418,8 +3364,6 @@ } } - AllocCoreRGSyncpts(pDevEvo); - nvInitEvoSubDevMask(pDevEvo); /* @@ -3468,7 +3412,7 @@ } /* Frees the Core RG Syncpts. */ -static void FreeCoreRGSyncpts(NVDevEvoPtr pDevEvo) +void nvRmFreeCoreRGSyncpts(NVDevEvoPtr pDevEvo) { NVDispEvoPtr pDispEvo = NULL; @@ -3488,21 +3432,20 @@ pDispEvo = pDevEvo->pDispEvo[0]; /* For each Head: */ - for (int i = 0; i < pDevEvo->numHeads; i++) { + for (int i = 0; i < pDevEvo->numApiHeads; i++) { /* Free all core RG syncpts. */ - NVDispHeadStateEvoRec *pHeadState = &pDispEvo->headState[i]; - for (int j = 0; j < pHeadState->numVblankSyncObjectsCreated; j++) { + NVDispApiHeadStateEvoRec *pApiHeadState = &pDispEvo->apiHeadState[i]; + for (int j = 0; j < pApiHeadState->numVblankSyncObjectsCreated; j++) { + nvAssert(!pApiHeadState->vblankSyncObjects[j].inUse); nvRmEvoFreeSyncpt(pDevEvo, - &pHeadState->vblankSyncObjects[j].evoSyncpt); + &pApiHeadState->vblankSyncObjects[j].evoSyncpt); } - pHeadState->numVblankSyncObjectsCreated = 0; + pApiHeadState->numVblankSyncObjectsCreated = 0; } } void nvRMFreeEvoCoreChannel(NVDevEvoPtr pDevEvo) { - FreeCoreRGSyncpts(pDevEvo); - if (pDevEvo->core != NULL) { EvoFreeCoreChannel(pDevEvo, pDevEvo->core); pDevEvo->core = NULL; @@ -3794,7 +3737,8 @@ NVDevEvoRec *pDevEvo, NVEvoSyncpt *pEvoSyncpt) { - if ((pEvoSyncpt == NULL) || !pDevEvo->supportsSyncpts) { + if ((pEvoSyncpt == NULL) || !pDevEvo->supportsSyncpts || + (pEvoSyncpt->id == NVKMS_SYNCPT_ID_INVALID)) { return; } @@ -5237,6 +5181,41 @@ return TRUE; } +typedef struct _NVRmRgLine1CallbackRec { + NVRgLine1CallbackRec base; + struct nvkms_ref_ptr *ref_ptr; + NvU32 rmHandle; + NVDispEvoRec *pDispEvo; + NvU32 head; +} NVRmRgLine1CallbackRec; + +static void RGLine1ServiceInterrupt(void *dataPtr, NvU32 dataU32) +{ + NVRmRgLine1CallbackRec *pRmCallback = (NVRmRgLine1CallbackRec*)dataPtr; + pRmCallback->base.pCallbackProc(pRmCallback->pDispEvo, pRmCallback->head, + &pRmCallback->base); +} + +/*! + * Receive RG line 1 interrupt notification from resman. + * + * This function is registered as the kernel callback function from resman when + * the RG line 1 interrupt is generated. + * + * This function is called within resman's context, so we schedule a zero timer + * callback to process the swapgroup check and release without holding the + * resman lock. + */ +static void RGLine1InterruptCallback(NvU32 rgIntrLine, void *param1, + NvBool bIsIrqlIsr /* unused */) +{ + (void) nvkms_alloc_timer_with_ref_ptr( + RGLine1ServiceInterrupt, /* callback */ + param1, /* argument (this is a ref_ptr to a NVRmRgLine1CallbackRec*) */ + 0, /* dataU32 */ + 0); /* usec */ +} + /*! * Register an RM callback function for the RG line 1 interrupt. * @@ -5246,38 +5225,40 @@ * * \param[in] pCallback The callback function pointer to be registered * - * \return Handle to callback object on success, 0 on failure. This same - * handle must be used to unregister the callback. + * \return Pointer to callback object on success, NULL on failure. This same + * pointer must be used to unregister the callback. */ -NvU32 nvRmAddRgLine1Callback( - const NVDispEvoRec *pDispEvo, - NvU32 head, - NV0092_REGISTER_RG_LINE_CALLBACK_FN pCallback) +NVRgLine1CallbackPtr +nvRmAddRgLine1Callback(NVDispEvoRec *pDispEvo, + NvU32 head, + NVRgLine1CallbackProc pCallbackProc, + void *pUserData) { NV0092_RG_LINE_CALLBACK_ALLOCATION_PARAMETERS rgLineParams = { 0 }; NVDevEvoPtr pDevEvo = pDispEvo->pDevEvo; NvU32 handle = nvGenerateUnixRmHandle(&pDevEvo->handleAllocator); NvU32 ret; + NVRmRgLine1CallbackRec *pRmCallback = nvCalloc(1, sizeof(*pRmCallback)); + + if (pRmCallback == NULL) { + goto failed; + } + + pRmCallback->ref_ptr = nvkms_alloc_ref_ptr(pRmCallback); + if (pRmCallback->ref_ptr == NULL) { + goto failed; + } + pRmCallback->base.pCallbackProc = pCallbackProc; + pRmCallback->base.pUserData = pUserData; + pRmCallback->rmHandle = handle; + pRmCallback->pDispEvo = pDispEvo; + pRmCallback->head = head; rgLineParams.subDeviceInstance = pDispEvo->displayOwner; rgLineParams.head = head; rgLineParams.rgLineNum = 1; - rgLineParams.pCallbkFn = pCallback; - - /* - * This object only takes a single pointer, but we want it to operate - * on a {pDispEvo,head} tuple, but we want to allocate the callback - * in NVKMS using a ref_ptr to allow for the pDispEvo being freed while - * callbacks are outstanding, so we bundle pDispEvo->ref_ptr and head - * into a single value here before passing it to RM, then decouple them - * in the RM callback function before allocating the NVKMS timer callback. - * - * This works because pDispEvo->ref_ptr will never have the lowest 2 - * bits set, and RM doesn't do anything with pCallbkParams aside from - * passing it back to the callback function. - */ - nvAssert(!((NvUPtr)pDispEvo->ref_ptr & head)); - rgLineParams.pCallbkParams = (void*)((NvUPtr)pDispEvo->ref_ptr | head); + rgLineParams.pCallbkFn = RGLine1InterruptCallback; + rgLineParams.pCallbkParams = pRmCallback->ref_ptr; ret = nvRmApiAlloc(nvEvoGlobal.clientHandle, pDevEvo->displayCommonHandle, @@ -5286,47 +5267,60 @@ &rgLineParams); if (ret == NVOS_STATUS_SUCCESS) { - return handle; - } else { - nvEvoLogDevDebug(pDevEvo, EVO_LOG_ERROR, - "Failed to enable RG line interrupt, ret: %d", ret); - nvFreeUnixRmHandle(&pDevEvo->handleAllocator, handle); - return 0; + return &pRmCallback->base; + } + + nvEvoLogDevDebug(pDevEvo, EVO_LOG_ERROR, + "Failed to enable RG line interrupt, ret: %d", ret); + /* fall through */ + +failed: + if (pRmCallback != NULL) { + nvkms_free_ref_ptr(pRmCallback->ref_ptr); + nvFree(pRmCallback); } + + nvFreeUnixRmHandle(&pDevEvo->handleAllocator, handle); + + return NULL; } /*! * Unregister an RM callback function previously registered with * nvRmAddRgLine1Callback. * - * \param[in] pDispEvo The display on which to unregister the - * callback + * \param[in] pDispEvo The display on which to unregister the + * callback * - * \param[in] callbackObjectHandle Handle to the previously allocated - * callback object + * \param[in] pCallback Pointer to the previously allocated + * callback object */ void nvRmRemoveRgLine1Callback(const NVDispEvoRec *pDispEvo, - NvU32 callbackObjectHandle) + NVRgLine1CallbackPtr pCallback) { + NVRmRgLine1CallbackRec *pRmCallback; NVDevEvoPtr pDevEvo = pDispEvo->pDevEvo; NvU32 ret; - if (callbackObjectHandle == 0) { + if (pCallback == NULL) { nvEvoLogDevDebug(pDevEvo, EVO_LOG_ERROR, - "Failed to disable RG line interrupt, obj handle 0"); + "Failed to disable RG line interrupt, obj pointer NULL"); return; } + pRmCallback = nv_container_of(pCallback, NVRmRgLine1CallbackRec, base); ret = nvRmApiFree(nvEvoGlobal.clientHandle, pDevEvo->displayCommonHandle, - callbackObjectHandle); + pRmCallback->rmHandle); if (ret != NVOS_STATUS_SUCCESS) { nvEvoLogDevDebug(pDevEvo, EVO_LOG_ERROR, "Failed to disable RG line interrupt, ret: %d", ret); } - nvFreeUnixRmHandle(&pDevEvo->handleAllocator, callbackObjectHandle); + nvFreeUnixRmHandle(&pDevEvo->handleAllocator, pRmCallback->rmHandle); + nvkms_free_ref_ptr(pRmCallback->ref_ptr); + nvFree(pRmCallback); } /*! @@ -5344,7 +5338,8 @@ NvU32 nvRmAddVBlankCallback( const NVDispEvoRec *pDispEvo, NvU32 head, - OSVBLANKCALLBACKPROC pCallback) + OSVBLANKCALLBACKPROC pCallback, + void *pParam2) { NVDevEvoPtr pDevEvo = pDispEvo->pDevEvo; const NvU32 sd = pDispEvo->displayOwner; @@ -5355,12 +5350,7 @@ .pProc = pCallback, .LogicalHead = head, .pParm1 = pDispEvo->ref_ptr, - - /* - * The callback's second argument is a pointer, which is large enough to - * store the head number. - */ - .pParm2 = (void *)(NvUPtr)head, + .pParm2 = pParam2, }; ret = nvRmApiAlloc(nvEvoGlobal.clientHandle, diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia-modeset/src/nvkms-surface.c nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia-modeset/src/nvkms-surface.c --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia-modeset/src/nvkms-surface.c 2023-10-25 20:22:41.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia-modeset/src/nvkms-surface.c 2024-03-05 22:12:23.000000000 +0000 @@ -594,7 +594,7 @@ } layer[NVKMS_MAX_LAYERS_PER_HEAD]; NvBool flipCursorToNull : 1; - } head[NVKMS_MAX_SUBDEVICES][NVKMS_MAX_HEADS_PER_DISP]; + } apiHead[NVKMS_MAX_SUBDEVICES][NVKMS_MAX_HEADS_PER_DISP]; }; /* @@ -607,69 +607,67 @@ struct ClearSurfaceUsageCache *pCache) { NVDispEvoPtr pDispEvo; - NvU32 head, sd; + NvU32 apiHead, sd; FOR_ALL_EVO_DISPLAYS(pDispEvo, sd, pDevEvo) { - for (head = 0; head < pDevEvo->numHeads; head++) { - - const NVEvoSubDevHeadStateRec *pSdHeadState = - &pDevEvo->gpus[sd].headState[head]; - const NVFlipChannelEvoHwState *pMainFlipState = - &pSdHeadState->layer[NVKMS_MAIN_LAYER]; + for (apiHead = 0; apiHead < pDevEvo->numApiHeads; apiHead++) { + NvU32 usageMaskOneHead = nvCollectSurfaceUsageMaskOneApiHead(pDispEvo, + apiHead, pSurfaceEvo); + NvU32 usageMaskMainLayer = DRF_IDX_VAL(_SURFACE, + _USAGE_MASK, _LAYER, NVKMS_MAIN_LAYER, usageMaskOneHead); NvU32 layer; - if (!nvHeadIsActive(pDispEvo, head)) { - continue; - } - /* * XXX NVKMS TODO: flip across heads/subdevices for all scenarios * that are flip locked. */ - if (!pMainFlipState->syncObject.usingSyncpt && - (pSurfaceEvo == pMainFlipState->syncObject.u.semaphores.acquireSurface.pSurfaceEvo || - pSurfaceEvo == pMainFlipState->syncObject.u.semaphores.releaseSurface.pSurfaceEvo)) { - pCache->head[sd][head].layer[NVKMS_MAIN_LAYER].flipSemaphoreToNull = TRUE; - } - - if (pSurfaceEvo == pMainFlipState->pSurfaceEvo[NVKMS_LEFT] || - pSurfaceEvo == pMainFlipState->pSurfaceEvo[NVKMS_RIGHT] || - pSurfaceEvo == pMainFlipState->completionNotifier.surface.pSurfaceEvo) { - pCache->head[sd][head].layer[NVKMS_MAIN_LAYER].flipToNull = TRUE; - } - - for (layer = 0; layer < pDevEvo->head[head].numLayers; layer++) { - const NVFlipChannelEvoHwState *pLayerFlipState = - &pSdHeadState->layer[layer]; + if (FLD_TEST_DRF(_SURFACE, _USAGE_MASK_LAYER, _SEMAPHORE, + _ENABLE, usageMaskMainLayer)) { + pCache->apiHead[sd][apiHead].layer[NVKMS_MAIN_LAYER]. + flipSemaphoreToNull = TRUE; + } + + if (FLD_TEST_DRF(_SURFACE, _USAGE_MASK_LAYER, _NOTIFIER, + _ENABLE, usageMaskMainLayer) || + FLD_TEST_DRF(_SURFACE, _USAGE_MASK_LAYER, _SCANOUT, + _ENABLE, usageMaskMainLayer)) { + pCache->apiHead[sd][apiHead].layer[NVKMS_MAIN_LAYER]. + flipToNull = TRUE; + } + + for (layer = 0; + layer < pDevEvo->apiHead[apiHead].numLayers; layer++) { + NvU32 usageMaskOneLayer = DRF_IDX_VAL(_SURFACE, + _USAGE_MASK, _LAYER, layer, usageMaskOneHead); if (layer == NVKMS_MAIN_LAYER) { continue; } - if (pSurfaceEvo == pLayerFlipState->pSurfaceEvo[NVKMS_LEFT] || - pSurfaceEvo == pLayerFlipState->pSurfaceEvo[NVKMS_RIGHT] || - pSurfaceEvo == pLayerFlipState->completionNotifier.surface.pSurfaceEvo || - (!pLayerFlipState->syncObject.usingSyncpt && - (pSurfaceEvo == pLayerFlipState->syncObject.u.semaphores.acquireSurface.pSurfaceEvo || - pSurfaceEvo == pLayerFlipState->syncObject.u.semaphores.releaseSurface.pSurfaceEvo))) { - pCache->head[sd][head].layer[layer].flipToNull = TRUE; - } - - /* - * EVO requires that, when flipping the base channel (aka main layer) to - * NULL, overlay channel is also flipped to NULL. - */ - if (pCache->head[sd][head].layer[NVKMS_MAIN_LAYER].flipToNull && - (pLayerFlipState->pSurfaceEvo[NVKMS_LEFT] != NULL || - pLayerFlipState->pSurfaceEvo[NVKMS_RIGHT] != NULL)) { - pCache->head[sd][head].layer[layer].flipToNull = TRUE; + if (usageMaskOneLayer != 0x0) { + pCache->apiHead[sd][apiHead].layer[layer]. + flipToNull = TRUE; + } if (pCache->apiHead[sd][apiHead].layer[NVKMS_MAIN_LAYER]. + flipToNull) { + NVSurfaceEvoPtr pSurfaceEvos[NVKMS_MAX_EYES] = { }; + /* + * EVO requires that, when flipping the base channel + * (aka main layer) to NULL, overlay channel is also + * flipped to NULL. + */ + if ((pSurfaceEvos[NVKMS_LEFT] != NULL) || + (pSurfaceEvos[NVKMS_RIGHT] != NULL)) { + pCache->apiHead[sd][apiHead].layer[layer]. + flipToNull = TRUE; + } } } - if (pSurfaceEvo == pSdHeadState->cursor.pSurfaceEvo) { - pCache->head[sd][head].flipCursorToNull = TRUE; + if (FLD_TEST_DRF(_SURFACE, _USAGE_MASK, _CURSOR, + _ENABLE, usageMaskOneHead) != 0x0) { + pCache->apiHead[sd][apiHead].flipCursorToNull = TRUE; } } } @@ -700,11 +698,13 @@ NvBool skipUpdate) { NVDispEvoPtr pDispEvo; - NvU32 head, sd; - NvBool found = FALSE; - struct NvKmsFlipRequest *request = nvCalloc(1, sizeof(*request)); + NvU32 apiHead, sd; + const NvU32 maxApiHeads = pDevEvo->numApiHeads * pDevEvo->numSubDevices; + struct NvKmsFlipRequestOneHead *pFlipApiHead = + nvCalloc(1, sizeof(*pFlipApiHead) * maxApiHeads); + NvU32 numFlipApiHeads = 0; - if (request == NULL) { + if (pFlipApiHead == NULL) { nvAssert(!"Failed to allocate memory"); return; } @@ -712,46 +712,59 @@ /* 1. Issue a flip of any overlay layer to NULL */ FOR_ALL_EVO_DISPLAYS(pDispEvo, sd, pDevEvo) { - for (head = 0; head < pDevEvo->numHeads; head++) { + for (apiHead = 0; apiHead < pDevEvo->numApiHeads; apiHead++) { - struct NvKmsFlipCommonParams *pRequestOneHead = - &request->sd[sd].head[head]; + struct NvKmsFlipCommonParams *pRequestOneApiHead = + &pFlipApiHead[numFlipApiHeads].flip; NvU32 layer; + NvBool found = FALSE; - if (!nvHeadIsActive(pDispEvo, head)) { + if (!nvApiHeadIsActive(pDispEvo, apiHead)) { continue; } - for (layer = 0; layer < pDevEvo->head[head].numLayers; layer++) { + for (layer = 0; + layer < pDevEvo->apiHead[apiHead].numLayers; layer++) { if (layer == NVKMS_MAIN_LAYER) { continue; } - if (pCache->head[sd][head].layer[layer].flipToNull) { - pRequestOneHead->layer[layer].surface.specified = TRUE; + if (pCache->apiHead[sd][apiHead].layer[layer].flipToNull) { + pRequestOneApiHead->layer[layer].surface.specified = TRUE; // No need to specify sizeIn/sizeOut as we are flipping NULL surface. - pRequestOneHead->layer[layer].compositionParams.specified = TRUE; - pRequestOneHead->layer[layer].syncObjects.specified = TRUE; - pRequestOneHead->layer[layer].completionNotifier.specified = TRUE; + pRequestOneApiHead->layer[layer].compositionParams.specified = TRUE; + pRequestOneApiHead->layer[layer].syncObjects.specified = TRUE; + pRequestOneApiHead->layer[layer].completionNotifier.specified = TRUE; - request->sd[sd].requestedHeadsBitMask |= NVBIT(head); found = TRUE; - pCache->head[sd][head].layer[layer].needToIdle = TRUE; + pCache->apiHead[sd][apiHead].layer[layer].needToIdle = TRUE; } } + + if (found) { + pFlipApiHead[numFlipApiHeads].sd = sd; + pFlipApiHead[numFlipApiHeads].head = apiHead; + numFlipApiHeads++; + nvAssert(numFlipApiHeads <= maxApiHeads); + } } } - if (found) { - request->commit = NV_TRUE; - - nvFlipEvo(pDevEvo, pDevEvo->pNvKmsOpenDev, request, NULL, skipUpdate, + if (numFlipApiHeads > 0) { + nvFlipEvo(pDevEvo, pDevEvo->pNvKmsOpenDev, + pFlipApiHead, + numFlipApiHeads, + TRUE /* commit */, + FALSE /* allowVrr */, + NULL /* pReply */, + skipUpdate, FALSE /* allowFlipLock */); - nvkms_memset(request, 0, sizeof(*request)); - found = FALSE; + nvkms_memset(pFlipApiHead, 0, + sizeof(pFlipApiHead[0]) * numFlipApiHeads); + numFlipApiHeads = 0; } /* @@ -766,46 +779,58 @@ /* 2. Issue a flip of any main layer to NULL */ FOR_ALL_EVO_DISPLAYS(pDispEvo, sd, pDevEvo) { - for (head = 0; head < pDevEvo->numHeads; head++) { + for (apiHead = 0; apiHead < pDevEvo->numApiHeads; apiHead++) { - struct NvKmsFlipCommonParams *pRequestOneHead = - &request->sd[sd].head[head]; + struct NvKmsFlipCommonParams *pRequestOneApiHead = + &pFlipApiHead[numFlipApiHeads].flip; + NvBool found = FALSE; - if (!nvHeadIsActive(pDispEvo, head)) { + if (!nvApiHeadIsActive(pDispEvo, apiHead)) { continue; } - if (pCache->head[sd][head].layer[NVKMS_MAIN_LAYER].flipToNull || - pCache->head[sd][head].layer[NVKMS_MAIN_LAYER].flipSemaphoreToNull) { + if (pCache->apiHead[sd][apiHead].layer[NVKMS_MAIN_LAYER].flipToNull || + pCache->apiHead[sd][apiHead].layer[NVKMS_MAIN_LAYER].flipSemaphoreToNull) { - if (pCache->head[sd][head].layer[NVKMS_MAIN_LAYER].flipToNull) { - pRequestOneHead->layer[NVKMS_MAIN_LAYER].surface.specified = TRUE; + if (pCache->apiHead[sd][apiHead].layer[NVKMS_MAIN_LAYER].flipToNull) { + pRequestOneApiHead->layer[NVKMS_MAIN_LAYER].surface.specified = TRUE; // No need to specify sizeIn/sizeOut as we are flipping NULL surface. - pRequestOneHead->layer[NVKMS_MAIN_LAYER].completionNotifier.specified = TRUE; + pRequestOneApiHead->layer[NVKMS_MAIN_LAYER].completionNotifier.specified = TRUE; - pCache->head[sd][head].layer[NVKMS_MAIN_LAYER].needToIdle = TRUE; + pCache->apiHead[sd][apiHead].layer[NVKMS_MAIN_LAYER].needToIdle = TRUE; } /* XXX arguably we should also idle for this case, but we * don't currently have a way to do so without also * clearing the ISO surface */ - pRequestOneHead->layer[NVKMS_MAIN_LAYER].syncObjects.val.useSyncpt = FALSE; - pRequestOneHead->layer[NVKMS_MAIN_LAYER].syncObjects.specified = TRUE; + pRequestOneApiHead->layer[NVKMS_MAIN_LAYER].syncObjects.val.useSyncpt = FALSE; + pRequestOneApiHead->layer[NVKMS_MAIN_LAYER].syncObjects.specified = TRUE; - request->sd[sd].requestedHeadsBitMask |= NVBIT(head); found = TRUE; } + + if (found) { + pFlipApiHead[numFlipApiHeads].sd = sd; + pFlipApiHead[numFlipApiHeads].head = apiHead; + numFlipApiHeads++; + nvAssert(numFlipApiHeads <= maxApiHeads); + } } } - if (found) { - request->commit = NV_TRUE; - - nvFlipEvo(pDevEvo, pDevEvo->pNvKmsOpenDev, request, NULL, skipUpdate, + if (numFlipApiHeads > 0) { + nvFlipEvo(pDevEvo, pDevEvo->pNvKmsOpenDev, + pFlipApiHead, + numFlipApiHeads, + TRUE /* commit */, + FALSE /* allowVrr */, + NULL /* pReply */, + skipUpdate, FALSE /* allowFlipLock */); - nvkms_memset(request, 0, sizeof(*request)); - found = FALSE; + nvkms_memset(pFlipApiHead, 0, + sizeof(pFlipApiHead[0]) * numFlipApiHeads); + numFlipApiHeads = 0; } /* @@ -814,111 +839,52 @@ * forcibly idle any problematic channels. */ if (!skipUpdate) { - NvU64 startTime = 0; - const NvU32 timeout = 500000; // .5 seconds - NvBool allIdle; - - do { - allIdle = TRUE; - FOR_ALL_EVO_DISPLAYS(pDispEvo, sd, pDevEvo) { - - for (head = 0; head < pDevEvo->numHeads; head++) { - NvU32 layer; - - if (!nvHeadIsActive(pDispEvo, head)) { - continue; - } - - for (layer = 0; layer < pDevEvo->head[head].numLayers; layer++) { - NvBool isMethodPending; - - if (!pCache->head[sd][head].layer[layer].needToIdle) { - continue; - } - - if (pDevEvo->hal->IsChannelMethodPending( - pDevEvo, pDevEvo->head[head].layer[layer], sd, - &isMethodPending) && - isMethodPending) { - - allIdle = FALSE; - } else { - /* This has been completed, no need to keep trying */ - pCache->head[sd][head].layer[layer].needToIdle = FALSE; - } + NvU32 layerMaskPerSdApiHead[NVKMS_MAX_SUBDEVICES] + [NVKMS_MAX_HEADS_PER_DISP] = { }; + FOR_ALL_EVO_DISPLAYS(pDispEvo, sd, pDevEvo) { + for (apiHead = 0; apiHead < pDevEvo->numApiHeads; apiHead++) { + for (NvU32 layer = 0; + layer < pDevEvo->apiHead[apiHead].numLayers; layer++) { + if (pCache->apiHead[sd][apiHead].layer[layer].needToIdle) { + layerMaskPerSdApiHead[sd][apiHead] |= NVBIT(layer); } } } - - if (!allIdle) { - if (nvExceedsTimeoutUSec(&startTime, timeout)) { - break; - } - nvkms_yield(); - } - } while (!allIdle); - - /* If we timed out above, force things to be idle. */ - if (!allIdle) { - NVEvoIdleChannelState idleChannelState = { }; - NvBool tryToForceIdle = FALSE; - - FOR_ALL_EVO_DISPLAYS(pDispEvo, sd, pDevEvo) { - - for (head = 0; head < pDevEvo->numHeads; head++) { - NvU32 layer; - - if (!nvHeadIsActive(pDispEvo, head)) { - continue; - } - - for (layer = 0; layer < pDevEvo->head[head].numLayers; layer++) { - if (pCache->head[sd][head].layer[layer].needToIdle) { - idleChannelState.subdev[sd].channelMask |= - pDevEvo->head[head].layer[layer]->channelMask; - tryToForceIdle = TRUE; - } - } - } - } - - if (tryToForceIdle) { - NvBool ret = pDevEvo->hal->ForceIdleSatelliteChannel(pDevEvo, &idleChannelState); - if (!ret) { - nvAssert(ret); - } - } } + nvIdleLayerChannels(pDevEvo, layerMaskPerSdApiHead); } /* 4. Issue a flip of any core channels to NULL */ FOR_ALL_EVO_DISPLAYS(pDispEvo, sd, pDevEvo) { - for (head = 0; head < pDevEvo->numHeads; head++) { - - struct NvKmsFlipCommonParams *pRequestOneHead = - &request->sd[sd].head[head]; + for (apiHead = 0; apiHead < pDevEvo->numApiHeads; apiHead++) { - if (!nvHeadIsActive(pDispEvo, head)) { + if (!nvApiHeadIsActive(pDispEvo, apiHead)) { continue; } - if (pCache->head[sd][head].flipCursorToNull) { - pRequestOneHead->cursor.imageSpecified = TRUE; - request->sd[sd].requestedHeadsBitMask |= NVBIT(head); - found = TRUE; + if (pCache->apiHead[sd][apiHead].flipCursorToNull) { + pFlipApiHead[numFlipApiHeads].flip.cursor.imageSpecified = TRUE; + pFlipApiHead[numFlipApiHeads].sd = sd; + pFlipApiHead[numFlipApiHeads].head = apiHead; + numFlipApiHeads++; + nvAssert(numFlipApiHeads <= maxApiHeads); } } } - if (found) { - request->commit = NV_TRUE; - - nvFlipEvo(pDevEvo, pDevEvo->pNvKmsOpenDev, request, NULL, skipUpdate, + if (numFlipApiHeads > 0) { + nvFlipEvo(pDevEvo, pDevEvo->pNvKmsOpenDev, + pFlipApiHead, + numFlipApiHeads, + TRUE /* commit */, + FALSE /* allowVrr */, + NULL /* pReply */, + skipUpdate, FALSE /* allowFlipLock */); } - nvFree(request); + nvFree(pFlipApiHead); } /* @@ -1090,37 +1056,7 @@ * flips. (Bug 2050970) */ if (pSurfaceEvo->requireCtxDma) { - /* - * XXX NVKMS TODO - * Make the sync more efficient: we only need to sync if the - * in-flight methods flip away from this surface. - */ - NvU32 head; - - /* - * If the core channel is no longer allocated, we don't need to - * sync. This assumes the channels are allocated/deallocated - * together. - */ - if (pDevEvo->core) { - - if (pDevEvo->hal->ClearSurfaceUsage != NULL) { - pDevEvo->hal->ClearSurfaceUsage(pDevEvo, pSurfaceEvo); - } - - nvRMSyncEvoChannel(pDevEvo, pDevEvo->core, __LINE__); - - for (head = 0; head < pDevEvo->numHeads; head++) { - NvU32 layer; - - for (layer = 0; layer < pDevEvo->head[head].numLayers; layer++) { - NVEvoChannelPtr pChannel = - pDevEvo->head[head].layer[layer]; - - nvRMSyncEvoChannel(pDevEvo, pChannel, __LINE__); - } - } - } + nvEvoClearSurfaceUsage(pDevEvo, pSurfaceEvo); } FreeSurfaceEvoRm(pDevEvo, pSurfaceEvo); diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia-modeset/src/nvkms-utils-flip.c nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia-modeset/src/nvkms-utils-flip.c --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia-modeset/src/nvkms-utils-flip.c 1970-01-01 00:00:00.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia-modeset/src/nvkms-utils-flip.c 2024-03-05 22:12:23.000000000 +0000 @@ -0,0 +1,399 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2014 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#include "nvkms-utils-flip.h" +#include "nvkms-private.h" +#include "nvkms-surface.h" +#include "nvkms-cursor.h" +#include "nvkms-sync.h" + +/*! + * Assign the elements in an NVSurfaceEvoPtr[NVKMS_MAX_EYES] array. + * + * Use NVEvoApiHandlesRec to translate an + * NvKmsSurfaceHandle[NVKMS_MAX_EYES] array into an an + * NVSurfaceEvoPtr[NVKMS_MAX_EYES] array. + * + * \param[in] pOpenDevSurfaceHandles The client's surfaces. + * \param[in] surfaceHandles The handles naming surfaces. + * \param[out] pSurfaceEvos The surface pointers. + * + * \return Return TRUE if all surfaceHandles could be successfully + * translated into pSurfaceEvos. Otherwise, return FALSE. + */ +NvBool nvAssignSurfaceArray( + const NVDevEvoRec *pDevEvo, + const NVEvoApiHandlesRec *pOpenDevSurfaceHandles, + const NvKmsSurfaceHandle surfaceHandles[NVKMS_MAX_EYES], + const NvBool isUsedByCursorChannel, + const NvBool isUsedByLayerChannel, + NVSurfaceEvoPtr pSurfaceEvos[NVKMS_MAX_EYES]) +{ + NvU32 eye; + + nvkms_memset(pSurfaceEvos, 0, sizeof(NVSurfaceEvoRec *) * NVKMS_MAX_EYES); + + for (eye = 0; eye < NVKMS_MAX_EYES; eye++) { + if (surfaceHandles[eye] != 0) { + pSurfaceEvos[eye] = + nvEvoGetSurfaceFromHandle(pDevEvo, + pOpenDevSurfaceHandles, + surfaceHandles[eye], + isUsedByCursorChannel, + isUsedByLayerChannel); + if ((pSurfaceEvos[eye] == NULL) || + (pSurfaceEvos[eye]->isoType != NVKMS_MEMORY_ISO)) { + return FALSE; + } + } + } + return TRUE; +} + + +/*! + * Assign the NVFlipNIsoSurfaceEvoHwState. + * + * Use the given NvKmsNIsoSurface to populate the + * NVFlipNIsoSurfaceEvoHwState. Validate that NvKmsNIsoSurface + * description is legitimate. + * + * \param[in] pDevEvo The device where the surface will be used. + * \param[in] pOpenDevSurfaceHandles The client's surfaces. + * \param[in] pParamsNIso The client's description of the NISO surface. + * \param[in] notifier Whether the NISO surface is a notifier. + * \param[in] pChannel The channel where the surface will be used. + * \param[out] pNIsoState The NVKMS presentation of the NISO surface. + * + * \return Return TRUE if the NVFlipNIsoSurfaceEvoHwState could be + * assigned and validated. Otherwise, return FALSE and leave + * the NVFlipNIsoSurfaceEvoHwState untouched. + */ +NvBool nvAssignNIsoEvoHwState( + const NVDevEvoRec *pDevEvo, + const NVEvoApiHandlesRec *pOpenDevSurfaceHandles, + const struct NvKmsNIsoSurface *pParamsNIso, + const NvBool notifier, /* TRUE=notifier; FALSE=semaphore */ + const NvU32 layer, + NVFlipNIsoSurfaceEvoHwState *pNIsoState) +{ + NVSurfaceEvoPtr pSurfaceEvo; + NvU32 elementSizeInBytes = 0, offsetInBytes, maxBytes; + + nvAssert(pParamsNIso->surfaceHandle != 0); + + pSurfaceEvo = + nvEvoGetSurfaceFromHandle(pDevEvo, + pOpenDevSurfaceHandles, + pParamsNIso->surfaceHandle, + FALSE /* isUsedByCursorChannel */, + TRUE /* isUsedByLayerChannel */); + if (pSurfaceEvo == NULL) { + return FALSE; + } + + /* Attempt to validate the surface: */ + + /* Only pitch surfaces can be used */ + if (pSurfaceEvo->layout != NvKmsSurfaceMemoryLayoutPitch) { + return FALSE; + } + + if (pSurfaceEvo->isoType != NVKMS_MEMORY_NISO) { + return FALSE; + } + + if ((pParamsNIso->format != NVKMS_NISO_FORMAT_FOUR_WORD) && + (pParamsNIso->format != NVKMS_NISO_FORMAT_FOUR_WORD_NVDISPLAY) && + (pParamsNIso->format != NVKMS_NISO_FORMAT_LEGACY)) { + return FALSE; + } + + if ((pDevEvo->caps.validNIsoFormatMask & + (1 << pParamsNIso->format)) == 0) { + return FALSE; + } + + /* Check that the item fits within the surface. */ + switch (pParamsNIso->format) { + case NVKMS_NISO_FORMAT_FOUR_WORD: + case NVKMS_NISO_FORMAT_FOUR_WORD_NVDISPLAY: + elementSizeInBytes = 16; + break; + case NVKMS_NISO_FORMAT_LEGACY: + if (notifier) { + /* Legacy notifier size depends on the layer. */ + elementSizeInBytes = + pDevEvo->caps.legacyNotifierFormatSizeBytes[layer]; + } else { + /* Legacy semaphores are always 4 bytes. */ + elementSizeInBytes = 4; + } + break; + } + +#if defined(DEBUG) + /* Assert that the size calculated by nvkms-sync library is the same as the + * one we derived from channel caps above. */ + if (notifier) { + NvBool overlay = (layer != NVKMS_MAIN_LAYER); + NvU32 libSize = nvKmsSizeOfNotifier(pParamsNIso->format, overlay); + nvAssert(libSize == elementSizeInBytes); + } else { + nvAssert(nvKmsSizeOfSemaphore(pParamsNIso->format) == elementSizeInBytes); + } +#endif + /* + * offsetInWords is an NvU16 and offsetInBytes is an NvU32, so + * neither of the expressions: + * offsetInWords * 4 + * offsetInBytes + elementSizeInBytes + * should ever overflow. + */ + + ct_assert(sizeof(pParamsNIso->offsetInWords) == 2); + + offsetInBytes = ((NvU32)pParamsNIso->offsetInWords) * 4; + + /* + * Compute the upper extent of the NISO element within the surface. + */ + + maxBytes = offsetInBytes + elementSizeInBytes; + + if (maxBytes > pSurfaceEvo->planes[0].rmObjectSizeInBytes) { + return FALSE; + } + + /* EVO expects the NISO element to fit within a 4k page. */ + + if (maxBytes > 4096) { + return FALSE; + } + + /* + * XXX NVKMS TODO: Check that the surface is in vidmem if + * NV5070_CTRL_SYSTEM_CAPS_BUG_644815_DNISO_VIDMEM_ONLY + */ + + pNIsoState->pSurfaceEvo = pSurfaceEvo; + pNIsoState->format = pParamsNIso->format; + pNIsoState->offsetInWords = pParamsNIso->offsetInWords; + + return TRUE; +} + +NvBool nvAssignCompletionNotifierEvoHwState( + const NVDevEvoRec *pDevEvo, + const NVEvoApiHandlesRec *pOpenDevSurfaceHandles, + const struct NvKmsCompletionNotifierDescription *pParamsNotif, + const NvU32 layer, + NVFlipCompletionNotifierEvoHwState *pNotif) +{ + NvBool ret; + + nvkms_memset(pNotif, 0, sizeof(*pNotif)); + + /* If no surface is specified, we should not use a notifier. */ + if (pParamsNotif->surface.surfaceHandle == 0) { + return TRUE; + } + + ret = nvAssignNIsoEvoHwState(pDevEvo, + pOpenDevSurfaceHandles, + &pParamsNotif->surface, + TRUE, /* notifier */ + layer, + &pNotif->surface); + if (ret) { + pNotif->awaken = pParamsNotif->awaken; + } + + return ret; +} + +NvBool nvAssignSemaphoreEvoHwState( + const NVDevEvoRec *pDevEvo, + const NVEvoApiHandlesRec *pOpenDevSurfaceHandles, + const NvU32 layer, + const NvU32 sd, + const struct NvKmsChannelSyncObjects *pChannelSyncObjects, + NVFlipSyncObjectEvoHwState *pFlipSyncObject) +{ + NvBool ret; + + nvAssert(!pChannelSyncObjects->useSyncpt); + + nvkms_memset(pFlipSyncObject, 0, sizeof(*pFlipSyncObject)); + + if (!pDevEvo->hal->caps.supportsIndependentAcqRelSemaphore) { + /*! acquire and release sema surface needs to be same */ + if (pChannelSyncObjects->u.semaphores.acquire.surface.surfaceHandle != + pChannelSyncObjects->u.semaphores.release.surface.surfaceHandle) { + return FALSE; + } + if (pChannelSyncObjects->u.semaphores.acquire.surface.format != + pChannelSyncObjects->u.semaphores.release.surface.format) { + return FALSE; + } + if (pChannelSyncObjects->u.semaphores.acquire.surface.offsetInWords != + pChannelSyncObjects->u.semaphores.release.surface.offsetInWords) { + return FALSE; + } + } + + /*! If no surface is specified, we should not use a semaphore.*/ + if (pChannelSyncObjects->u.semaphores.acquire.surface.surfaceHandle != 0) { + + ret = nvAssignNIsoEvoHwState( + pDevEvo, + pOpenDevSurfaceHandles, + &pChannelSyncObjects->u.semaphores.acquire.surface, + FALSE, /* notifier */ + layer, + &pFlipSyncObject->u.semaphores.acquireSurface); + if (ret) { + pFlipSyncObject->u.semaphores.acquireValue = + pChannelSyncObjects->u.semaphores.acquire.value; + } else { + return ret; + } + } + + /*! If no surface is specified, we should not use a semaphore.*/ + if (pChannelSyncObjects->u.semaphores.release.surface.surfaceHandle != 0) { + + ret = nvAssignNIsoEvoHwState( + pDevEvo, + pOpenDevSurfaceHandles, + &pChannelSyncObjects->u.semaphores.release.surface, + FALSE, /* notifier */ + layer, + &pFlipSyncObject->u.semaphores.releaseSurface); + if (ret) { + pFlipSyncObject->u.semaphores.releaseValue = + pChannelSyncObjects->u.semaphores.release.value; + } else { + return ret; + } + } + + return TRUE; +} + +NvBool nvValidatePerLayerCompParams( + const struct NvKmsCompositionParams *pCompParams, + const struct NvKmsCompositionCapabilities *pCaps, + NVSurfaceEvoPtr pSurfaceEvo) +{ + const NvKmsSurfaceMemoryFormatInfo *pFormatInfo = (pSurfaceEvo != NULL) ? + nvKmsGetSurfaceMemoryFormatInfo(pSurfaceEvo->format) : NULL; + const enum NvKmsCompositionColorKeySelect colorKeySelect = + pCompParams->colorKeySelect; + NvU32 match; + + if ((pCaps->supportedColorKeySelects & NVBIT(colorKeySelect)) == 0x0) { + return FALSE; + } + + NVKMS_COMPOSITION_FOR_MATCH_BITS(colorKeySelect, match) { + if ((pCaps->colorKeySelect[colorKeySelect].supportedBlendModes[match] & + NVBIT(pCompParams->blendingMode[match])) == 0x0) { + return FALSE; + } + + switch (pCompParams->blendingMode[match]) { + case NVKMS_COMPOSITION_BLENDING_MODE_NON_PREMULT_ALPHA: + case NVKMS_COMPOSITION_BLENDING_MODE_PREMULT_ALPHA: + if (pCompParams->surfaceAlpha != 0) { + return FALSE; + } + break; + default: + break; + } + } + + /* Match and nomatch pixels should not use alpha blending mode at once. */ + if ((colorKeySelect != NVKMS_COMPOSITION_COLOR_KEY_SELECT_DISABLE) && + (NvKmsIsCompositionModeUseAlpha(pCompParams->blendingMode[0])) && + (NvKmsIsCompositionModeUseAlpha(pCompParams->blendingMode[1]))) { + return FALSE; + } + + /* + * If surface is NULL, no further validation required. The composition + * parameters do not take effect if surface is NULL. + */ + if (pFormatInfo == NULL || pFormatInfo->isYUV) { + return TRUE; + } + + /* Disable color keying for 8 Bpp surfaces. */ + if ((colorKeySelect == NVKMS_COMPOSITION_COLOR_KEY_SELECT_SRC) || + (colorKeySelect == NVKMS_COMPOSITION_COLOR_KEY_SELECT_DST)) { + + if (pFormatInfo->rgb.bytesPerPixel > 4) { + return FALSE; + } + } + + return TRUE; +} + +NvBool +nvAssignCursorSurface(const struct NvKmsPerOpenDev *pOpenDev, + const NVDevEvoRec *pDevEvo, + const struct NvKmsSetCursorImageCommonParams *pImgParams, + NVSurfaceEvoPtr *pSurfaceEvo) + +{ + const NVEvoApiHandlesRec *pOpenDevSurfaceHandles = + nvGetSurfaceHandlesFromOpenDevConst(pOpenDev); + NVSurfaceEvoPtr pSurfaceEvos[NVKMS_MAX_EYES] = { }; + + if (!nvGetCursorImageSurfaces(pDevEvo, + pOpenDevSurfaceHandles, + pImgParams, + pSurfaceEvos)) { + return FALSE; + } + + /* XXX NVKMS TODO: add support for stereo cursor */ + if (pSurfaceEvos[NVKMS_RIGHT] != NULL) { + return FALSE; + } + + if (pSurfaceEvos[NVKMS_LEFT] != NULL) { + if (!nvValidatePerLayerCompParams(&pImgParams->cursorCompParams, + &pDevEvo->caps.cursorCompositionCaps, + pSurfaceEvos[NVKMS_LEFT])) { + return FALSE; + } + } + + *pSurfaceEvo = pSurfaceEvos[NVKMS_LEFT]; + + return TRUE; +} + diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia-modeset/src/nvkms-utils.c nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia-modeset/src/nvkms-utils.c --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia-modeset/src/nvkms-utils.c 2023-10-25 20:22:41.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia-modeset/src/nvkms-utils.c 2024-03-05 22:12:23.000000000 +0000 @@ -489,12 +489,19 @@ NvU8 nvPixelDepthToBitsPerComponent(enum nvKmsPixelDepth pixelDepth) { + /* + * Note: The 444 formats have three components per pixel, thus we compute + * bpc as depth/3. The 422 formats effectively store two components per + * pixel, so we compute bpc for those as depth/2. + */ switch (pixelDepth) { case NVKMS_PIXEL_DEPTH_18_444: return 6; case NVKMS_PIXEL_DEPTH_24_444: + case NVKMS_PIXEL_DEPTH_16_422: return 8; case NVKMS_PIXEL_DEPTH_30_444: + case NVKMS_PIXEL_DEPTH_20_422: return 10; } nvAssert(!"Unknown NVKMS_PIXEL_DEPTH"); diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia-modeset/src/nvkms-vrr.c nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia-modeset/src/nvkms-vrr.c --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia-modeset/src/nvkms-vrr.c 2023-10-25 20:22:41.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia-modeset/src/nvkms-vrr.c 2024-03-05 22:12:23.000000000 +0000 @@ -29,8 +29,78 @@ #include "dp/nvdp-connector-event-sink.h" #include "nvkms-hdmi.h" #include "nvkms-dpy.h" +#include "nvkms-sync.h" #include +#include /* NV01_MEMORY_LOCAL_USER */ +#include /* NV20_SUBDEVICE_0 */ +#include /* NV2080_CTRL_CMD_EVENT_SET_NOTIFICATION */ + +#define MAX_VRR_NOTIFIER_SLOTS_PER_HEAD 4 +#define MAX_NOTIFIER_SIZE 0x10 +#define NOTIFIER_BYTES_PER_HEAD \ + (MAX_VRR_NOTIFIER_SLOTS_PER_HEAD * MAX_NOTIFIER_SIZE) + +#define MAX_VRR_FLIP_DELAY_TIME_RETRY_COUNT 5 + +typedef struct _vrrSurfaceNotifier +{ + NvU8 notifier[NV_MAX_HEADS][NOTIFIER_BYTES_PER_HEAD]; +} vrrSurfaceNotifier, *vrrSurfaceNotifierPtr; + +/*! + * This file contains routines for handling Variable Refresh Rate (VRR) display + * mode, also known as G-SYNC (not to be confused with the feature formerly + * known as G-SYNC, which is now called Quadro Sync). + * + * VRR in NVKMS is handled in several phases: + * + * 1. During modeset, if NvKmsSetModeRequest::allowVrr is true and VRR-capable + * dpys are present, VRR is "enabled". This means that + * + * a. VRR is disabled, if it was enabled before. + * b. The raster timings are adjusted by extending the back porch by 2 + * lines. This signals to the monitor that it should enter G-SYNC mode. + * c. The mode is set. + * d. (EVO only) The RM VRR state machine is initialized, but left in + * "suspended" mode. + * e. Raster lock and frame lock are disabled. + * + * pDevEvo->vrr.enabled indicates whether VRR was enabled successfully at + * modeset time. + * + * 2. At flip time, if NvKmsFlipRequest::allowVrr is true, VRR is "activated". + * + * a. Stall lock is enabled. + * b. (NVDisplay only) The RG is switched from continuous mode to one-shot + * mode. + * c. (EVO only) RM's VRR state machine is enabled. + * d. (EVO only) The NVKMS client is told to release a special frame ready + * semaphore which tells RM to unstall the head. + * e. (NVDisplay only) The window channel flip is submitted with + * NVC37E_UPDATE_RELEASE_ELV_TRUE to trigger an unstall when the frame is + * ready. + * + * pDevEvo->vrr.active (not to be confused with pDevEvo->vrr.enabled, + * described above) indicates whether VRR was activated successfully at flip + * time. + * + * 3. Also at flip time, if NvKmsFlipRequest::allowVrr is false, VRR is + * "deactivated". + * + * a. Stall lock is disabled. + * b. (NVDisplay only) the RG is switched from one-shot mode to continuous + * mode. + * c. (EVO only) RM's VRR state machine is suspended. + */ + +static NvBool SetVrrActivePriv(NVDevEvoPtr pDevEvo, NvBool active); +static void ConfigVrrPstateSwitch(NVDispEvoPtr pDispEvo, + NvBool vrrEnabled, + NvBool vrrState, + NvBool vrrDirty, + NvU32 head); + /*! * Allocate the VRR semaphore surface. @@ -105,15 +175,612 @@ return status == NVOS_STATUS_SUCCESS; } -NvBool nvDispSupportsVrr( - const NVDispEvoRec *pDispEvo) +/*! + * Return TRUE dpy support G-SYNC. + */ +static NvBool DpyIsGsync(const NVDpyEvoRec *pDpyEvo) +{ + return pDpyEvo->vrr.type == NVKMS_DPY_VRR_TYPE_GSYNC; +} + +static NvBool AnyEnabledAdaptiveSyncDpys(const NVDevEvoRec *pDevEvo) { + NVDispEvoPtr pDispEvo; + NvU32 dispIndex; + + FOR_ALL_EVO_DISPLAYS(pDispEvo, dispIndex, pDevEvo) { + NvU32 head; + + for (head = 0; head < pDevEvo->numHeads; head++) { + const NVDispHeadStateEvoRec *pHeadState = + &pDispEvo->headState[head]; + + if (nvIsAdaptiveSyncDpyVrrType(pHeadState->timings.vrr.type)) { + return TRUE; + } + } + } + return FALSE; } +static NvBool DpyAllowsAdaptiveSync( + const NVDpyEvoRec *pDpyEvo, + const enum NvKmsAllowAdaptiveSync allowAdaptiveSync, + const NvModeTimings *pTimings) +{ + /* + * HDMI VRR and HDMI 3D both use the vendor specific infoframe in HW, + * so disallow HDMI VRR when attempting to set an HDMI 3D mode. + */ + + if (pTimings->hdmi3D) { + return FALSE; + } + + return ((allowAdaptiveSync == + NVKMS_ALLOW_ADAPTIVE_SYNC_DEFAULTLISTED_ONLY) && + (pDpyEvo->vrr.type == + NVKMS_DPY_VRR_TYPE_ADAPTIVE_SYNC_DEFAULTLISTED)) || + ((allowAdaptiveSync == NVKMS_ALLOW_ADAPTIVE_SYNC_ALL) && + nvDpyIsAdaptiveSync(pDpyEvo)); +} + +NvBool nvDispSupportsVrr(const NVDispEvoRec *pDispEvo) +{ + // Don't allow VRR if a framelock device is present. + // (In other words, don't allow G-SYNC with Quadro Sync). + return !pDispEvo->pFrameLockEvo; +} + +enum NvKmsDpyVRRType +nvGetAllowedDpyVrrType(const NVDpyEvoRec *pDpyEvo, + const NvModeTimings *pTimings, + enum NvKmsStereoMode stereoMode, + const NvBool allowGsync, + const enum NvKmsAllowAdaptiveSync allowAdaptiveSync) +{ + /* + * Mark these mode timings as indicating a VRR mode, even if the timings + * don't need to be adjusted; this is used to distinguish between VRR and + * non-VRR heads elsewhere. + */ + + if ((stereoMode == NVKMS_STEREO_DISABLED) && + ((allowGsync && DpyIsGsync(pDpyEvo)) || + DpyAllowsAdaptiveSync(pDpyEvo, allowAdaptiveSync, pTimings))) { + return pDpyEvo->vrr.type; + } + + return NVKMS_DPY_VRR_TYPE_NONE; +} + +/*! Adjust mode timings as necessary for VRR. */ +void nvAdjustHwModeTimingsForVrrEvo(NVHwModeTimingsEvoPtr pTimings, + const enum NvKmsDpyVRRType vrrType, + const NvU32 edidTimeoutMicroseconds, + const NvU32 vrrOverrideMinRefreshRate, + const NvBool needsSwFramePacing) +{ + if (vrrType == NVKMS_DPY_VRR_TYPE_NONE) { + return; + } + + /* + * On G-SYNC panels, the back porch extension is used to indicate to + * the monitor that VRR is enabled. It is not necessary on + * Adaptive-Sync displays. + */ + if (vrrType == NVKMS_DPY_VRR_TYPE_GSYNC) { + pTimings->rasterSize.y += 2; + pTimings->rasterBlankEnd.y += 2; + pTimings->rasterBlankStart.y += 2; + } + + // Allow overriding the EDID min refresh rate on Adaptive-Sync + // displays. + if (nvIsAdaptiveSyncDpyVrrType(vrrType) && vrrOverrideMinRefreshRate) { + NvU32 minMinRefreshRate, maxMinRefreshRate; + NvU32 clampedMinRefreshRate; + + nvGetDpyMinRefreshRateValidValues(pTimings, + vrrType, + edidTimeoutMicroseconds, + &minMinRefreshRate, + &maxMinRefreshRate); + + clampedMinRefreshRate = + NV_MAX(vrrOverrideMinRefreshRate, minMinRefreshRate); + + clampedMinRefreshRate = + NV_MIN(clampedMinRefreshRate, maxMinRefreshRate); + + pTimings->vrr.timeoutMicroseconds = 1000000 / + clampedMinRefreshRate; + } else { + pTimings->vrr.timeoutMicroseconds = edidTimeoutMicroseconds; + } + pTimings->vrr.needsSwFramePacing = needsSwFramePacing; + pTimings->vrr.type = vrrType; +} + +static void TellRMAboutVrrHead(NVDispEvoPtr pDispEvo, + NVDispHeadStateEvoRec *pHeadState, + NvBool vrrPossible) +{ + if (pHeadState->activeRmId != 0) { + NV0073_CTRL_SYSTEM_VRR_DISPLAY_INFO_PARAMS params = { }; + NvU32 ret; + + params.subDeviceInstance = pDispEvo->displayOwner; + params.displayId = pHeadState->activeRmId; + params.bAddition = vrrPossible; + + ret = nvRmApiControl(nvEvoGlobal.clientHandle, + pDispEvo->pDevEvo->displayCommonHandle, + NV0073_CTRL_CMD_SYSTEM_VRR_DISPLAY_INFO, + ¶ms, sizeof(params)); + if (ret != NVOS_STATUS_SUCCESS) { + nvEvoLogDispDebug(pDispEvo, EVO_LOG_WARN, + "NV0073_CTRL_CMD_SYSTEM_VRR_DISPLAY_INFO failed"); + } + } +} + +static void RmDisableVrr(NVDevEvoPtr pDevEvo) +{ + NVDispEvoPtr pDispEvo; + NvU32 head, dispIndex; + + FOR_ALL_EVO_DISPLAYS(pDispEvo, dispIndex, pDevEvo) { + for (head = 0; head < pDevEvo->numHeads; head++) { + ConfigVrrPstateSwitch(pDispEvo, FALSE /* vrrEnabled */, + FALSE /* vrrState */, + TRUE /* vrrDirty */, + head); + } + } + nvAssert(pDevEvo->hal->caps.supportsDisplayRate); +} + +NvU16 nvPrepareNextVrrNotifier(NVEvoChannelPtr pChannel, NvU32 sd, NvU32 head) +{ + enum NvKmsNIsoFormat nIsoFormat = NVKMS_NISO_FORMAT_FOUR_WORD_NVDISPLAY; + + vrrSurfaceNotifierPtr pNotifiers = pChannel->notifiersDma[sd].subDeviceAddress[sd]; + + const NvU32 notifierSize = + nvKmsSizeOfNotifier(nIsoFormat, FALSE /* overlay */); + + const NvU8 nextSlot = + pChannel->notifiersDma[sd].vrrNotifierHead[head].vrrNotifierNextSlot; + + const NvU8 *headBase = pNotifiers->notifier[head]; + + const NvU8 offsetInBytes = + (headBase - ((const NvU8 *) pNotifiers)) + (notifierSize * nextSlot); + + nvAssert(notifierSize <= MAX_NOTIFIER_SIZE); + + nvKmsResetNotifier(nIsoFormat, FALSE /* overlay */, + nextSlot, pNotifiers->notifier[head]); + + pChannel->notifiersDma[sd].vrrNotifierHead[head].vrrNotifierNextSlot = + (nextSlot + 1) % MAX_VRR_NOTIFIER_SLOTS_PER_HEAD; + + return offsetInBytes / 4; +} + +static void SetTimeoutPerFrame(void *dataPtr, NvU32 dataU32) +{ + // Set the timeout after which the current frame will self-refresh. + NVDispEvoPtr pDispEvo = dataPtr; + NVDevEvoPtr pDevEvo = pDispEvo->pDevEvo; + NVEvoUpdateState updateState = { }; + NvU32 head; + NvU32 inputHead = dataU32; + NVDispHeadStateEvoRec *pInputHeadState = &pDispEvo->headState[inputHead]; + NvU32 displayRate = pInputHeadState->displayRate; + struct NvKmsVrrFramePacingInfo *pInputVrrFramePacingInfo = + &(pInputHeadState->vrrFramePacingInfo); + const NvU32 headsMask = pInputHeadState->mergeModeVrrSecondaryHeadMask | + NVBIT(inputHead); + volatile NV0073_CTRL_RM_VRR_SHARED_DATA *pData = pInputVrrFramePacingInfo->pData; + + /* + * XXX[2Heads1OR] Implement per api-head frame pacing and remove this + * mergeMode check and NVDispEvoRec::mergeModeVrrSecondaryHeadMask. + */ + if ((pInputHeadState->mergeMode == NV_EVO_MERGE_MODE_SECONDARY) || + !pInputVrrFramePacingInfo->framePacingActive || + (displayRate == pData->timeout)) { + return; + } + + nvPushEvoSubDevMaskDisp(pDispEvo); + FOR_EACH_EVO_HW_HEAD_IN_MASK(headsMask, head) { + pDispEvo->headState[head].displayRate = pData->timeout; + + pDevEvo->hal->SetDisplayRate(pDispEvo, head, + TRUE /* enable */, + &updateState, + pDispEvo->headState[head].displayRate / 1000); + } + + /* + * In order to change the one shot self refresh timeout mid-frame without + * immediately triggering a new frame, skip setting RELEASE_ELV for this + * update. + */ + nvEvoUpdateAndKickOff(pDispEvo, FALSE, &updateState, + FALSE /* releaseElv */); + nvPopEvoSubDevMask(pDevEvo); +} + +static void SetTimeoutEvent(void *arg, void *pEventDataVoid, NvU32 hEvent, + NvU32 Data, NV_STATUS Status) +{ + Nv2080VrrSetTimeoutNotification *pParams = pEventDataVoid; + + (void) nvkms_alloc_timer_with_ref_ptr( + SetTimeoutPerFrame, /* callback */ + arg, /* argument (this is a ref_ptr to a pDispEvo) */ + pParams->head, /* dataU32 */ + 0); +} + +static void DisableVrrSetTimeoutEvent(NVDispEvoRec *pDispEvo) +{ + NVDevEvoPtr pDevEvo = pDispEvo->pDevEvo; + NvU32 sd = pDispEvo->displayOwner; + NvU32 subdeviceHandle = pDevEvo->pSubDevices[sd]->handle; + NV2080_CTRL_EVENT_SET_NOTIFICATION_PARAMS setEventParams = {0}; + NvU32 ret; + + nvAssert(pDispEvo->vrrSetTimeoutEventUsageCount != 0); + + pDispEvo->vrrSetTimeoutEventUsageCount--; + if (pDispEvo->vrrSetTimeoutEventUsageCount != 0) { + return; + } + + nvAssert(pDispEvo->vrrSetTimeoutEventHandle != 0); + + setEventParams.event = NV2080_NOTIFIERS_VRR_SET_TIMEOUT; + setEventParams.action = NV2080_CTRL_EVENT_SET_NOTIFICATION_ACTION_DISABLE; + ret = nvRmApiControl(nvEvoGlobal.clientHandle, + subdeviceHandle, + NV2080_CTRL_CMD_EVENT_SET_NOTIFICATION, + &setEventParams, + sizeof(setEventParams)); + if (ret != NVOS_STATUS_SUCCESS) { + nvEvoLogDev(pDevEvo, EVO_LOG_WARN, + "NV2080_CTRL_EVENT_SET_NOTIFICATION_ACTION_DISABLE failed for vrr %d", ret); + } + + ret = nvRmApiFree(nvEvoGlobal.clientHandle, + subdeviceHandle, + pDispEvo->vrrSetTimeoutEventHandle); + if (ret != NVOS_STATUS_SUCCESS) { + nvEvoLogDev(pDevEvo, EVO_LOG_WARN, + "nvRmApiFree(notify) failed for vrr %d", ret); + } + + nvFreeUnixRmHandle(&pDevEvo->handleAllocator, + pDispEvo->vrrSetTimeoutEventHandle); + pDispEvo->vrrSetTimeoutEventHandle = 0; +} + +static NvBool EnableVrrSetTimeoutEvent(NVDispEvoRec *pDispEvo) +{ + NVDevEvoPtr pDevEvo = pDispEvo->pDevEvo; + NvU32 sd = pDispEvo->displayOwner; + NvU32 subdeviceHandle = pDevEvo->pSubDevices[sd]->handle; + NV2080_CTRL_EVENT_SET_NOTIFICATION_PARAMS setEventParams = { }; + NvU32 ret; + + if (pDispEvo->vrrSetTimeoutEventUsageCount != 0) { + nvAssert(pDispEvo->vrrSetTimeoutEventHandle != 0); + goto done; + } + + nvAssert(pDispEvo->vrrSetTimeoutEventHandle == 0); + + pDispEvo->vrrSetTimeoutEventHandle = + nvGenerateUnixRmHandle(&pDevEvo->handleAllocator); + + if (!nvRmRegisterCallback(pDevEvo, + &pDispEvo->vrrSetTimeoutCallback, + pDispEvo->ref_ptr, + subdeviceHandle, + pDispEvo->vrrSetTimeoutEventHandle, + SetTimeoutEvent, + NV2080_NOTIFIERS_VRR_SET_TIMEOUT)) { + nvFreeUnixRmHandle(&pDevEvo->handleAllocator, + pDispEvo->vrrSetTimeoutEventHandle); + nvEvoLogDev(pDevEvo, EVO_LOG_ERROR, + "nvRmRegisterCallback failed for vrr"); + return FALSE; + } + + // Enable VRR notifications from this subdevice. + setEventParams.event = NV2080_NOTIFIERS_VRR_SET_TIMEOUT; + setEventParams.action = NV2080_CTRL_EVENT_SET_NOTIFICATION_ACTION_REPEAT; + ret = nvRmApiControl(nvEvoGlobal.clientHandle, + subdeviceHandle, + NV2080_CTRL_CMD_EVENT_SET_NOTIFICATION, + &setEventParams, + sizeof(setEventParams)); + if (ret != NVOS_STATUS_SUCCESS) { + nvEvoLogDev(pDevEvo, EVO_LOG_ERROR, + "NV2080_CTRL_EVENT_SET_NOTIFICATION_ACTION_REPEAT failed for vrr 0x%x", ret); + nvRmApiFree(nvEvoGlobal.clientHandle, + subdeviceHandle, pDispEvo->vrrSetTimeoutEventHandle); + nvFreeUnixRmHandle(&pDevEvo->handleAllocator, + pDispEvo->vrrSetTimeoutEventHandle); + pDispEvo->vrrSetTimeoutEventHandle = 0; + return FALSE; + } + +done: + pDispEvo->vrrSetTimeoutEventUsageCount++; + return TRUE; +} + +static NvBool VrrRgLineActiveSessionOpen(NVDispEvoPtr pDispEvo, + struct NvKmsVrrFramePacingInfo *pVrrFramePacingInfo) +{ + NvU32 ret = 0; + NVDevEvoPtr pDevEvo = pDispEvo->pDevEvo; + NvU32 sd = pDispEvo->displayOwner; + NvU32 subdeviceHandle = pDevEvo->pSubDevices[sd]->handle; + NV_MEMORY_ALLOCATION_PARAMS memAllocParams = { }; + NvHandle memoryHandle; + void *address = NULL; + + if (!EnableVrrSetTimeoutEvent(pDispEvo)) { + return FALSE; + } + + /* allocate memory from vidmem */ + memoryHandle = nvGenerateUnixRmHandle(&pDevEvo->handleAllocator); + memAllocParams.owner = NVKMS_RM_HEAP_ID; + memAllocParams.type = NVOS32_TYPE_DMA; + memAllocParams.size = sizeof(NV0073_CTRL_RM_VRR_SHARED_DATA); + memAllocParams.attr = DRF_DEF(OS32, _ATTR, _PAGE_SIZE, _4KB) | + DRF_DEF(OS32, _ATTR, _PHYSICALITY, _CONTIGUOUS) | + DRF_DEF(OS32, _ATTR, _COHERENCY, _UNCACHED) | + DRF_DEF(OS32, _ATTR, _LOCATION, _VIDMEM); + + memAllocParams.flags |= (NVOS32_ALLOC_FLAGS_ALLOCATE_KERNEL_PRIVILEGED | + NVOS32_ALLOC_FLAGS_PERSISTENT_VIDMEM); + + ret = nvRmApiAlloc(nvEvoGlobal.clientHandle, + pDevEvo->deviceHandle, + memoryHandle, + NV01_MEMORY_LOCAL_USER, + &memAllocParams); + + if (ret != NVOS_STATUS_SUCCESS) { + nvEvoLogDev(pDevEvo, EVO_LOG_ERROR, "nvRmApiAlloc(memory) failed for vrr 0x%x", ret); + goto free_memory_handle; + } + + ret = nvRmApiMapMemory(nvEvoGlobal.clientHandle, + subdeviceHandle, + memoryHandle, + 0, + sizeof(NV0073_CTRL_RM_VRR_SHARED_DATA), + &address, + 0); + if ((ret != NVOS_STATUS_SUCCESS) || (address == NULL)) { + nvEvoLogDev(pDevEvo, EVO_LOG_ERROR, " nvRmApiMapMemory failed for vrr 0x%x addr: %p", + ret, address); + nvRmApiFree(nvEvoGlobal.clientHandle, + subdeviceHandle, memoryHandle); + goto free_memory_handle; + } + + pVrrFramePacingInfo->pData = (NV0073_CTRL_RM_VRR_SHARED_DATA *)address; + pVrrFramePacingInfo->memoryHandle = memoryHandle; + + return TRUE; + +free_memory_handle: + nvFreeUnixRmHandle(&pDevEvo->handleAllocator, memoryHandle); + DisableVrrSetTimeoutEvent(pDispEvo); + return FALSE; +} + +static void VrrRgLineActiveSessionClose(NVDispEvoPtr pDispEvo, + struct NvKmsVrrFramePacingInfo *pVrrFramePacingInfo) +{ + NVDevEvoPtr pDevEvo = pDispEvo->pDevEvo; + NvU32 sd = pDispEvo->displayOwner; + NvU32 subdeviceHandle = pDevEvo->pSubDevices[sd]->handle; + NvU32 ret = 0; + + // clean up allocated memory + ret = nvRmApiUnmapMemory(nvEvoGlobal.clientHandle, + subdeviceHandle, + pVrrFramePacingInfo->memoryHandle, + (void *)pVrrFramePacingInfo->pData, + 0); + if (ret != NVOS_STATUS_SUCCESS) { + nvEvoLogDev(pDevEvo, EVO_LOG_WARN, "nvRmApiUnmapMemory failed for vrr %d", ret); + } + + ret = nvRmApiFree(nvEvoGlobal.clientHandle, + subdeviceHandle, + pVrrFramePacingInfo->memoryHandle); + if (ret != NVOS_STATUS_SUCCESS) { + nvEvoLogDev(pDevEvo, EVO_LOG_WARN, "nvRmApiFree(memory) failed for vrr %d", ret); + } + + nvFreeUnixRmHandle(&pDevEvo->handleAllocator, pVrrFramePacingInfo->memoryHandle); + + DisableVrrSetTimeoutEvent(pDispEvo); +} + +/*! + * Enable or disable SW Frame Pacing for one head. + * + * This will reset the NVDispHeadStateEvoRec::NvKmsVrrFramePacingInfo state used + * to track Frame pacing per head and call RM to set an interrupt to be called + * at every first RG scanline of every frame (whether initiated by a flip or + * a self-refresh). + */ +static NvBool SetSwFramePacing(NVDispEvoPtr pDispEvo, NvU32 head, NvBool enable) +{ + NVDevEvoPtr pDevEvo = pDispEvo->pDevEvo; + NVDispHeadStateEvoRec *pHeadState = &pDispEvo->headState[head]; + struct NvKmsVrrFramePacingInfo *pVrrFramePacingInfo = + &pHeadState->vrrFramePacingInfo; + const NVHwModeTimingsEvo *pTimings = &pHeadState->timings; + const NvU32 timeout = pTimings->vrr.timeoutMicroseconds; + struct NV0073_CTRL_CMD_SYSTEM_VRR_SET_RGLINE_ACTIVE_PARAMS params = { }; + NvU32 maxFrameTime = 0; + NvU32 minFrameTime = 0; + + if (pVrrFramePacingInfo->framePacingActive == enable) { + return TRUE; + } + + if (enable) { + maxFrameTime = timeout * 1000; + minFrameTime = 1000 * + axb_div_c(pTimings->rasterSize.y * 1000, + pTimings->rasterSize.x, + pTimings->pixelClock); + + /* + * SW Frame pacing won't work with infinite self-refresh adaptive sync + * or direct drive panels (none of which currently exist) or when + * driving a mode below the panel's minimum refresh rate. + */ + if ((maxFrameTime == 0) || + (minFrameTime == 0) || + (minFrameTime >= maxFrameTime)) { + nvEvoLogDev(pDevEvo, EVO_LOG_ERROR, + "Failed to set variable refresh rate with invalid " + "minimum frame time (%u ns) or maximum frame time " + "(%u ns)", minFrameTime, maxFrameTime); + return FALSE; + } + + if (!VrrRgLineActiveSessionOpen(pDispEvo, pVrrFramePacingInfo)) { + nvEvoLogDev(pDevEvo, EVO_LOG_ERROR, + "Failed to setup Rgline active session for vrr"); + return FALSE; + } + } + + params.head = head; + params.height = 1; + params.bEnable = enable; + params.subDeviceInstance = pDispEvo->displayOwner; + params.maxFrameTime = maxFrameTime; + params.minFrameTime = minFrameTime; + params.hMemory = pVrrFramePacingInfo->memoryHandle; + if (nvRmApiControl(nvEvoGlobal.clientHandle, + pDispEvo->pDevEvo->displayCommonHandle, + NV0073_CTRL_CMD_SYSTEM_VRR_SET_RGLINE_ACTIVE, + ¶ms, sizeof(params)) + != NVOS_STATUS_SUCCESS) { + nvAssert(!"NV0073_CTRL_CMD_SYSTEM_VRR_SET_RGLINE_ACTIVE failed"); + VrrRgLineActiveSessionClose(pDispEvo, pVrrFramePacingInfo); + return FALSE; + } + + if (!enable) { + VrrRgLineActiveSessionClose(pDispEvo, pVrrFramePacingInfo); + + // Reset the state used to track SW Frame pacing. + nvkms_memset(pVrrFramePacingInfo, 0, sizeof(*pVrrFramePacingInfo)); + } + + pVrrFramePacingInfo->framePacingActive = enable; + return TRUE; +} + void nvDisableVrr(NVDevEvoPtr pDevEvo) { - return; + NVDispEvoPtr pDispEvo; + NvU32 head, dispIndex; + + FOR_ALL_EVO_DISPLAYS(pDispEvo, dispIndex, pDevEvo) { + for (head = 0; head < pDevEvo->numHeads; head++) { + NVDispHeadStateEvoRec *pHeadState = &pDispEvo->headState[head]; + + TellRMAboutVrrHead(pDispEvo, pHeadState, FALSE); + + SetSwFramePacing(pDispEvo, head, FALSE); + } + } + + if (!pDevEvo->vrr.enabled) { + return; + } + + SetVrrActivePriv(pDevEvo, FALSE); + RmDisableVrr(pDevEvo); + + FOR_ALL_EVO_DISPLAYS(pDispEvo, dispIndex, pDevEvo) { + for (head = 0; head < pDevEvo->numHeads; head++) { + NVDispHeadStateEvoRec *pHeadState = &pDispEvo->headState[head]; + + if ((pHeadState->pConnectorEvo != NULL) && + nvIsAdaptiveSyncDpyVrrType(pHeadState->timings.vrr.type)) { + if (nvConnectorUsesDPLib(pHeadState->pConnectorEvo)) { + nvDPLibSetAdaptiveSync(pDispEvo, head, FALSE); + } else { + nvHdmiSetVRR(pDispEvo, head, FALSE); + } + } + } + } + + pDevEvo->vrr.enabled = FALSE; + nvAssert(!pDevEvo->vrr.active); +} + +static NvBool AnyEnabledGsyncDpys(const NVDevEvoRec *pDevEvo) +{ + NVDispEvoPtr pDispEvo; + NvU32 dispIndex; + + FOR_ALL_EVO_DISPLAYS(pDispEvo, dispIndex, pDevEvo) { + NvU32 head; + + for (head = 0; head < pDevEvo->numHeads; head++) { + const NVDispHeadStateEvoRec *pHeadState = &pDispEvo->headState[head]; + + if (pHeadState->timings.vrr.type == NVKMS_DPY_VRR_TYPE_GSYNC) { + return TRUE; + } + } + } + + return FALSE; +} + +static NvBool RmEnableVrr(NVDevEvoPtr pDevEvo) +{ + NVDispEvoPtr pDispEvo; + NvU32 dispIndex, head; + + FOR_ALL_EVO_DISPLAYS(pDispEvo, dispIndex, pDevEvo) { + for (head = 0; head < pDevEvo->numHeads; head++) { + ConfigVrrPstateSwitch(pDispEvo, TRUE /* vrrEnabled */, + FALSE /* vrrState */, + TRUE/* vrrDirty */, + head); + } + } + nvAssert(pDevEvo->hal->caps.supportsDisplayRate); + return TRUE; + + return FALSE; } void nvGetDpyMinRefreshRateValidValues( @@ -123,58 +790,507 @@ NvU32 *minMinRefreshRate, NvU32 *maxMinRefreshRate) { - return; + NvU32 edidMinRefreshRate; + + if (nvIsAdaptiveSyncDpyVrrType(vrrType)) { + /* + * Adaptive-Sync monitors must always define a nonzero minimum refresh + * rate in the EDID, and a modeset may override this within a range + * of NVKMS_VRR_MIN_REFRESH_RATE_MAX_VARIANCE, as long as the minimum + * is not below 1hz and the maximum does not exceed the current + * refresh rate. + */ + NvU32 minTimeoutMicroseconds = + axb_div_c(pTimings->rasterSize.y * 1000, + pTimings->rasterSize.x, pTimings->pixelClock); + NvU32 maxRefreshRate = 1000000 / minTimeoutMicroseconds; + + nvAssert(edidTimeoutMicroseconds != 0); + + edidMinRefreshRate = + 1000000 / edidTimeoutMicroseconds; + + if (edidMinRefreshRate <= NVKMS_VRR_MIN_REFRESH_RATE_MAX_VARIANCE) { + *minMinRefreshRate = 1; + } else { + *minMinRefreshRate = edidMinRefreshRate - + NVKMS_VRR_MIN_REFRESH_RATE_MAX_VARIANCE; + } + + *maxMinRefreshRate = NV_MIN(maxRefreshRate, + edidMinRefreshRate + NVKMS_VRR_MIN_REFRESH_RATE_MAX_VARIANCE); + } else { + /* + * Non-Adaptive-Sync panels may not override the EDID-provided minimum + * refresh rate, which will be 1hz for most G-SYNC panels or 0hz for + * true self-refresh panels. + */ + edidMinRefreshRate = edidTimeoutMicroseconds ? + 1000000 / edidTimeoutMicroseconds : 0; + *minMinRefreshRate = *maxMinRefreshRate = edidMinRefreshRate; + } +} + +/*! + * Modify the VRR state to enable (but not activate) VRR at modeset time. + * + * This prepares VRR displays for VRR (through a DP MSA override for + * Adaptive-Sync and a backporch extension for G-SYNC) and sets up the RM + * VRR state machine (for pre-nvdisplay) but does not actually start VRR + * flipping until nvSetVrrActive() is called at flip time. + * + * \param[in] pDevEvo The device that is enabling VRR. + */ +void nvEnableVrr(NVDevEvoPtr pDevEvo) +{ + NVDispEvoPtr pDispEvo; + NvU32 head, dispIndex; + + nvAssert(!pDevEvo->vrr.enabled); + + FOR_ALL_EVO_DISPLAYS(pDispEvo, dispIndex, pDevEvo) { + for (head = 0; head < pDevEvo->numHeads; head++) { + NVDispHeadStateEvoRec *pHeadState = &pDispEvo->headState[head]; + + if ((pHeadState->pConnectorEvo != NULL) && + nvIsAdaptiveSyncDpyVrrType(pHeadState->timings.vrr.type)) { + if (nvConnectorUsesDPLib(pHeadState->pConnectorEvo)) { + nvDPLibSetAdaptiveSync(pDispEvo, head, TRUE); + } else { + nvHdmiSetVRR(pDispEvo, head, TRUE); + } + } + } + } + + FOR_ALL_EVO_DISPLAYS(pDispEvo, dispIndex, pDevEvo) { + for (head = 0; head < pDevEvo->numHeads; head++) { + NVDispHeadStateEvoRec *pHeadState = &pDispEvo->headState[head]; + + // To allow VRR-based mclk switching, RM needs to know which heads + // are driving VRR displays capable of extending vblank. This + // includes all G-SYNC displays (regardless of whether the modeset + // indicates that G-SYNC is allowed) but only Adaptive-Sync + // displays which put the display into Adaptive-Sync mode by calling + // nvDPLibSetAdaptiveSync above. + TellRMAboutVrrHead(pDispEvo, + pHeadState, + (pHeadState->timings.vrr.type != + NVKMS_DPY_VRR_TYPE_NONE)); + } + } + + if (!(AnyEnabledGsyncDpys(pDevEvo) || + AnyEnabledAdaptiveSyncDpys(pDevEvo))) { + return; + } + + if (!RmEnableVrr(pDevEvo)) { + return; + } + + pDevEvo->vrr.enabled = TRUE; +} + +static void ClearElvBlock(NVDispEvoPtr pDispEvo, NvU32 head) +{ + const NVDispHeadStateEvoRec *pHeadState = &pDispEvo->headState[head]; + NV0073_CTRL_SYSTEM_CLEAR_ELV_BLOCK_PARAMS params = { }; + + params.subDeviceInstance = pDispEvo->displayOwner; + params.displayId = pHeadState->activeRmId; + + if (nvRmApiControl(nvEvoGlobal.clientHandle, + pDispEvo->pDevEvo->displayCommonHandle, + NV0073_CTRL_CMD_SYSTEM_CLEAR_ELV_BLOCK, + ¶ms, sizeof(params)) + != NVOS_STATUS_SUCCESS) { + nvAssert(!"CLEAR_ELV_BLOCK failed"); + } +} + +static void ConfigVrrPstateSwitch(NVDispEvoPtr pDispEvo, NvBool vrrEnabled, + NvBool vrrState, NvBool vrrDirty, NvU32 head) +{ + NV0073_CTRL_SYSTEM_CONFIG_VRR_PSTATE_SWITCH_PARAMS params = { }; + NvU32 ret; + const NVDispHeadStateEvoRec *pHeadState = &pDispEvo->headState[head]; + const NVHwModeTimingsEvo *pTimings = &pHeadState->timings; + + if (nvkms_disable_vrr_memclk_switch() || + (pTimings->vrr.type == NVKMS_DPY_VRR_TYPE_NONE)) { + return; + } + + /* + * An inactive head should always have pTimings->vrr.type == + * NVKMS_DPY_VRR_TYPE_NONE and therefore return early above. + */ + nvAssert(nvHeadIsActive(pDispEvo, head)); + + params.displayId = pHeadState->activeRmId; + params.bVrrEnabled = vrrEnabled; + params.bVrrState = vrrState; + params.bVrrDirty = vrrDirty; + + if (params.bVrrDirty) { + NvU64 frameTimeUs = axb_div_c(pTimings->rasterSize.y * 1000ULL, + pTimings->rasterSize.x, pTimings->pixelClock); + NvU64 timePerLineNs = (frameTimeUs * 1000ULL) / pTimings->rasterSize.y; + + NvU64 maxFrameTimeUs = pTimings->vrr.timeoutMicroseconds; + NvU64 maxVblankExtTimeNs = (maxFrameTimeUs - frameTimeUs) * 1000ULL; + + params.maxVblankExtension = maxVblankExtTimeNs / timePerLineNs; + } + + ret = nvRmApiControl(nvEvoGlobal.clientHandle, + pDispEvo->pDevEvo->displayCommonHandle, + NV0073_CTRL_CMD_SYSTEM_CONFIG_VRR_PSTATE_SWITCH, + ¶ms, sizeof(params)); + if (ret != NVOS_STATUS_SUCCESS) { + nvEvoLogDispDebug(pDispEvo, EVO_LOG_WARN, + "NV0073_CTRL_CMD_SYSTEM_CONFIG_VRR_PSTATE_SWITCH failed"); + } +} + +static void SetStallLockOneDisp(NVDispEvoPtr pDispEvo, NvBool enable) +{ + NVDevEvoPtr pDevEvo = pDispEvo->pDevEvo; + NvBool enableVrrOnHead[NVKMS_MAX_HEADS_PER_DISP]; + NVEvoUpdateState updateState = { }; + NvU32 head; + + if (enable) { + for (head = 0; head < pDevEvo->numHeads; head++) { + ConfigVrrPstateSwitch(pDispEvo, TRUE /* vrrEnabled */, + TRUE /* vrrState */, + FALSE/* vrrDirty */, + head); + } + } + + nvPushEvoSubDevMaskDisp(pDispEvo); + + // Make sure any pending updates that we didn't wait for previously have + // completed. + nvRMSyncEvoChannel(pDevEvo, pDevEvo->core, __LINE__); + + for (head = 0; head < pDevEvo->numHeads; head++) { + const NVDispHeadStateEvoRec *pHeadState = &pDispEvo->headState[head]; + const NvU32 timeout = pHeadState->timings.vrr.timeoutMicroseconds; + + enableVrrOnHead[head] = ((pHeadState->timings.vrr.type != + NVKMS_DPY_VRR_TYPE_NONE) && enable); + + nvEvoArmLightweightSupervisor(pDispEvo, head, + enableVrrOnHead[head], TRUE); + if (!enableVrrOnHead[head]) { + ClearElvBlock(pDispEvo, head); + } + pDevEvo->hal->SetStallLock(pDispEvo, head, + enableVrrOnHead[head], + &updateState); + + if (pDevEvo->hal->caps.supportsDisplayRate) { + pDevEvo->hal->SetDisplayRate(pDispEvo, head, + enableVrrOnHead[head], + &updateState, + timeout); + + if ((pHeadState->timings.vrr.type != + NVKMS_DPY_VRR_TYPE_NONE) && + pHeadState->timings.vrr.needsSwFramePacing) { + SetSwFramePacing(pDispEvo, head, + enableVrrOnHead[head]); + } + } + } + + nvEvoUpdateAndKickOff(pDispEvo, TRUE, &updateState, + TRUE /* releaseElv */); + + for (head = 0; head < pDevEvo->numHeads; head++) { + nvEvoArmLightweightSupervisor(pDispEvo, head, + enableVrrOnHead[head], FALSE); + } + + nvPopEvoSubDevMask(pDevEvo); + + if (!enable) { + for (head = 0; head < pDevEvo->numHeads; head++) { + ConfigVrrPstateSwitch(pDispEvo, TRUE /* vrrEnabled */, + FALSE /* vrrState */, + FALSE /* vrrDirty */, + head); + } + } +} + +static void SetStallLockOneDev(NVDevEvoPtr pDevEvo, NvBool enable) +{ + NVDispEvoPtr pDispEvo; + NvU32 dispIndex; + + FOR_ALL_EVO_DISPLAYS(pDispEvo, dispIndex, pDevEvo) { + SetStallLockOneDisp(pDispEvo, enable); + } } -void nvEnableVrr( - NVDevEvoPtr pDevEvo, - const struct NvKmsSetModeRequest *pRequest) +/*! + * Modify the VRR state to activate or deactivate VRR on the heads of a pDevEvo. + */ +static NvBool SetVrrActivePriv(NVDevEvoPtr pDevEvo, NvBool active) { - return; + if (!pDevEvo->vrr.enabled || + pDevEvo->vrr.active == active) { + return NV_TRUE; + } + + // TODO: Drain the base channel first? + SetStallLockOneDev(pDevEvo, active); + + pDevEvo->vrr.active = active; + pDevEvo->vrr.flipCounter = 0; + return NV_TRUE; } -void nvSetVrrActive( - NVDevEvoPtr pDevEvo, - NvBool active) +void nvSetVrrActive(NVDevEvoPtr pDevEvo, NvBool active) { - return; + if (!SetVrrActivePriv(pDevEvo, active)) { + nvDisableVrr(pDevEvo); + } } -void nvApplyVrrBaseFlipOverrides( - const NVDispEvoRec *pDispEvo, - NvU32 head, - const NVFlipChannelEvoHwState *pOld, - NVFlipChannelEvoHwState *pNew) +/*! + * Track the minimum and average time between flips over the last 16 flips, and + * add a timestamp to delay the next flip to adjust Frame pacing if necessary. + */ +void nvTrackAndDelayFlipForVrrSwFramePacing(NVDispEvoPtr pDispEvo, + const struct NvKmsVrrFramePacingInfo *pVrrFramePacingInfo, + NVFlipChannelEvoHwState *pFlip) { - return; + volatile NV0073_CTRL_RM_VRR_SHARED_DATA *pData = pVrrFramePacingInfo->pData; + NvU32 retryCount = MAX_VRR_FLIP_DELAY_TIME_RETRY_COUNT; + NvU64 flipTimeStamp = 0; + NvU64 dataTimeStamp1 = 0, dataTimeStamp2 = 0; + NvU32 expectedFrameNum = 0; + NvBool bFlipTimeAdjustment = NV_FALSE; + NvBool bCheckFlipTime = NV_FALSE; + + // If the RG interrupt isn't active, then SW Frame pacing isn't in use. + if (!pVrrFramePacingInfo->framePacingActive) { + return; + } + + do { + // read the data timestamp first + dataTimeStamp1 = pData->dataTimeStamp; + + // now read the actual data required + expectedFrameNum = pData->expectedFrameNum; + bFlipTimeAdjustment = pData->bFlipTimeAdjustment; + bCheckFlipTime = pData->bCheckFlipTime; + flipTimeStamp = pData->flipTimeStamp; + + // read the data timestamp again to check if values were updated + // by RM in between while nvkms was reading them. + dataTimeStamp2 = pData->dataTimeStamp; + } while ((dataTimeStamp1 != dataTimeStamp2) && --retryCount); + + if (retryCount == 0) { + nvEvoLogDisp(pDispEvo, EVO_LOG_ERROR, + "Failed to sync with RM to get flipTimeStamp related data"); + return; + } + + if (expectedFrameNum > 1) { + pFlip->tearing = FALSE; + } + + if (bFlipTimeAdjustment && !(pFlip->tearing && bCheckFlipTime)) { + pFlip->timeStamp = flipTimeStamp; + } +} + +/*! + * Override flip parameters for a head based on VRR state. + */ +void nvApplyVrrBaseFlipOverrides(const NVDispEvoRec *pDispEvo, NvU32 head, + const NVFlipChannelEvoHwState *pOld, + NVFlipChannelEvoHwState *pNew) +{ + const NVDevEvoRec *pDevEvo = pDispEvo->pDevEvo; + const NVDispHeadStateEvoRec *pHeadState = NULL; + + if (!pDevEvo->vrr.enabled) { + return; + } + + if (head != NV_INVALID_HEAD) { + pHeadState = &pDispEvo->headState[head]; + nvAssert(pDevEvo->head[head].layer[NVKMS_MAIN_LAYER]->caps.vrrTearingFlips); + } + + // Tell RM the real requested tearing mode so that it can honor + // __GL_SYNC_TO_VBLANK. + pNew->vrrTearing = pNew->tearing; + + // If this head is driving non-VRR displays, force swap interval to be 0. + // RM will block the flips as necessary using the pre-update trap methods + // based on the vrrTearing flag above. + if (pHeadState != NULL && + (pHeadState->timings.vrr.type == NVKMS_DPY_VRR_TYPE_NONE)) { + pNew->tearing = TRUE; + pNew->minPresentInterval = 0; + } + + // If oneshot mode is in use, and the previous flip was non-tearing with + // nonzero MIN_PRESENT_INTERVAL, and the new flip will be tearing with + // MIN_PRESENT_INTERVAL 0, then force this first new flip to be + // non-tearing to WAR bug 2406398 which causes these transitional flips + // to stall for up to the display's minimum refresh rate. + if ((pHeadState != NULL) && + (pHeadState->timings.vrr.type != NVKMS_DPY_VRR_TYPE_NONE) && + !pOld->tearing && + (pOld->minPresentInterval != 0) && + pNew->tearing && + (pNew->minPresentInterval == 0)) { + pNew->tearing = FALSE; + } } -void nvCancelVrrFrameReleaseTimers( - NVDevEvoPtr pDevEvo) +void nvCancelVrrFrameReleaseTimers(NVDevEvoPtr pDevEvo) { - return; + NVDispEvoPtr pDispEvo; + NvU32 dispIndex; + + FOR_ALL_EVO_DISPLAYS(pDispEvo, dispIndex, pDevEvo) { + nvkms_free_timer(pDispEvo->vrr.unstallTimer); + pDispEvo->vrr.unstallTimer = NULL; + } } +/* Get active vrr type used by the flips. */ enum NvKmsVrrFlipType nvGetActiveVrrType(const NVDevEvoRec *pDevEvo) { + /* + * If VRR is active, and any connected display is G-SYNC, then report that + * this flip was a G-SYNC flip, otherwise report it as an Adaptive-Sync + * flip. + * + * XXX NVKMS TODO: We could be smarter about reporting whether this flip + * exclusively changed surfaces on Adaptive-Sync or G-SYNC heads. + */ + if (pDevEvo->vrr.active) { + if (AnyEnabledGsyncDpys(pDevEvo)) { + return NV_KMS_VRR_FLIP_GSYNC; + } else { + return NV_KMS_VRR_FLIP_ADAPTIVE_SYNC; + } + } + return NV_KMS_VRR_FLIP_NON_VRR; } +/*! + * Get the next VRR semaphore index to be released + * by the client, increments the counter and handles wrapping. + */ NvS32 nvIncVrrSemaphoreIndex(NVDevEvoPtr pDevEvo) { - return -1; + NvS32 vrrSemaphoreIndex = -1; + + // If there are pending unstall timers (e.g. triggered by cursor motion), + // cancel them now. The flip that was just requested will trigger an + // unstall. + nvCancelVrrFrameReleaseTimers(pDevEvo); + + if (pDevEvo->vrr.active && !pDevEvo->hal->caps.supportsDisplayRate) { + vrrSemaphoreIndex = pDevEvo->vrr.flipCounter++; + if (pDevEvo->vrr.flipCounter >= + NVKMS_VRR_SEMAPHORE_SURFACE_SIZE / sizeof(NvU32)) { + pDevEvo->vrr.flipCounter = 0; + } + } + + return vrrSemaphoreIndex; } -void nvTriggerVrrUnstallMoveCursor( - NVDispEvoPtr pDispEvo) +static void +VrrUnstallNow(NVDispEvoPtr pDispEvo) { - return; + NVDevEvoPtr pDevEvo = pDispEvo->pDevEvo; + NvU32 head; + + nvAssert(pDevEvo->hal->caps.supportsDisplayRate); + + for (head = 0; head < pDevEvo->numHeads; head++) { + if (!nvHeadIsActive(pDispEvo, head)) { + continue; + } + + pDevEvo->cursorHal->ReleaseElv(pDevEvo, pDispEvo->displayOwner, head); + } } -void nvTriggerVrrUnstallSetCursorImage( - NVDispEvoPtr pDispEvo, - NvBool ctxDmaChanged) +static void +VrrUnstallTimer(void *dataPtr, NvU32 dataU32) { - return; + NVDispEvoPtr pDispEvo = dataPtr; + + VrrUnstallNow(pDispEvo); + pDispEvo->vrr.unstallTimer = NULL; +} + +/*! + * Schedule a timer to trigger a VRR unstall if no flip occurs soon. + * + * When VRR is active and something other than a flip (i.e. cursor motion) + * changes the screen, RM needs to be notified so that it can trigger a VRR + * unstall to present the new frame. However, if it does that immediately, then + * applications that flip in response to cursor motion will end up always + * flipping during the unstall, causing stutter. So instead, schedule a timeout + * for some time in the future in order to give the application some time to + * respond, but force a minimum refresh rate if it doesn't. + * + * On nvdisplay, this schedules an nvkms timer and uses a method to trigger an + * unstall. On EVO, it calls into RM to do something equivalent. + */ +void nvTriggerVrrUnstallMoveCursor(NVDispEvoPtr pDispEvo) +{ + NVDevEvoPtr pDevEvo = pDispEvo->pDevEvo; + const NvU32 timeoutMs = 33; // 30 fps + + if (!pDevEvo->vrr.active) { + return; + } + + { + if (!pDispEvo->vrr.unstallTimer) { + pDispEvo->vrr.unstallTimer = + nvkms_alloc_timer(VrrUnstallTimer, pDispEvo, 0, timeoutMs * 1000); + } + } +} + +/*! + * Trigger a VRR unstall in response to a cursor image change. + */ +void nvTriggerVrrUnstallSetCursorImage(NVDispEvoPtr pDispEvo, + NvBool elvReleased) +{ + NVDevEvoPtr pDevEvo = pDispEvo->pDevEvo; + + if (pDevEvo->vrr.active) { + if (!elvReleased) { + // On nvdisplay, no unstall is necessary if the cursor image update + // path did a releaseElv=true Update. + // + // But, if elv was not released, then force an immediate unstall + // now. + VrrUnstallNow(pDispEvo); + } + } } diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia-modeset/src/nvkms.c nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia-modeset/src/nvkms.c --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia-modeset/src/nvkms.c 2023-10-25 20:22:41.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia-modeset/src/nvkms.c 2024-03-05 22:12:24.000000000 +0000 @@ -36,6 +36,7 @@ #include "nvkms-modepool.h" #include "nvkms-modeset.h" #include "nvkms-attributes.h" +#include "nvkms-dpy-override.h" #include "nvkms-framelock.h" #include "nvkms-surface.h" #include "nvkms-3dvision.h" @@ -43,6 +44,7 @@ #include "nvkms-headsurface.h" #include "nvkms-headsurface-ioctl.h" #include "nvkms-headsurface-swapgroup.h" +#include "nvkms-flip.h" /* nvFlipEvo */ #include "nvkms-vrr.h" #include "dp/nvdp-connector.h" @@ -209,7 +211,7 @@ struct { NvKmsGenericHandle hCallback; struct NvKmsPerOpenDisp *pOpenDisp; - NvU32 head; + NvU32 apiHead; } vblankNotification; } e; } unicastEvent; @@ -219,6 +221,9 @@ static void AllocSurfaceCtxDmasForAllOpens(NVDevEvoRec *pDevEvo); static void FreeSurfaceCtxDmasForAllOpens(NVDevEvoRec *pDevEvo); +static void EnableAndSetupVblankSyncObjectForAllOpens(NVDevEvoRec *pDevEvo); +static void DisableAndCleanVblankSyncObjectForAllOpens(NVDevEvoRec *pDevEvo); + static NVListRec perOpenList = NV_LIST_INIT(&perOpenList); static NVListRec perOpenIoctlList = NV_LIST_INIT(&perOpenIoctlList); @@ -818,7 +823,7 @@ continue; } - if (nvHasBitAboveMax(layerMask, pDevEvo->head[h].numLayers)) { + if (nvHasBitAboveMax(layerMask, pDevEvo->apiHead[h].numLayers)) { return FALSE; } @@ -832,7 +837,7 @@ return FALSE; } - if (h >= pDevEvo->numHeads) { + if (h >= pDevEvo->numApiHeads) { return FALSE; } } @@ -860,7 +865,7 @@ return FALSE; } - if (h >= pDevEvo->numHeads) { + if (h >= pDevEvo->numApiHeads) { return FALSE; } } @@ -880,14 +885,14 @@ const NVDevEvoRec *pDevEvo, struct NvKmsFlipPermissions *pPermissions) { - NvU32 dispIndex, head; + NvU32 dispIndex, apiHead; nvkms_memset(pPermissions, 0, sizeof(*pPermissions)); for (dispIndex = 0; dispIndex < pDevEvo->nDispEvo; dispIndex++) { - for (head = 0; head < pDevEvo->numHeads; head++) { - pPermissions->disp[dispIndex].head[head].layerMask = - NVBIT(pDevEvo->head[head].numLayers) - 1; + for (apiHead = 0; apiHead < pDevEvo->numApiHeads; apiHead++) { + pPermissions->disp[dispIndex].head[apiHead].layerMask = + NVBIT(pDevEvo->apiHead[apiHead].numLayers) - 1; } } } @@ -896,13 +901,13 @@ const NVDevEvoRec *pDevEvo, struct NvKmsModesetPermissions *pPermissions) { - NvU32 dispIndex, head; + NvU32 dispIndex, apiHead; nvkms_memset(pPermissions, 0, sizeof(*pPermissions)); for (dispIndex = 0; dispIndex < pDevEvo->nDispEvo; dispIndex++) { - for (head = 0; head < pDevEvo->numHeads; head++) { - pPermissions->disp[dispIndex].head[head].dpyIdList = + for (apiHead = 0; apiHead < pDevEvo->numApiHeads; apiHead++) { + pPermissions->disp[dispIndex].head[apiHead].dpyIdList = nvAllDpyIdList(); } } @@ -943,6 +948,61 @@ return TRUE; } +/* + * If not NULL, remove pRemoveFlip from pFlip. Returns true if there are still + * some remaining permissions. + */ +static NvBool RemoveFlipPermissions(struct NvKmsFlipPermissions *pFlip, + const struct NvKmsFlipPermissions *pRemoveFlip) +{ + NvU32 d, h, dLen, hLen; + NvBool remainingPermissions = FALSE; + + dLen = ARRAY_LEN(pFlip->disp); + for (d = 0; d < dLen; d++) { + hLen = ARRAY_LEN(pFlip->disp[d].head); + for (h = 0; h < hLen; h++) { + + if (pRemoveFlip) { + pFlip->disp[d].head[h].layerMask &= + ~pRemoveFlip->disp[d].head[h].layerMask; + } + + remainingPermissions |= (pFlip->disp[d].head[h].layerMask != 0); + } + } + + return remainingPermissions; +} + +/* + * If not NULL, remove pRemoveModeset from pModeset. Returns true if there are + * still some remaining permissions. + */ +static NvBool RemoveModesetPermissions(struct NvKmsModesetPermissions *pModeset, + const struct NvKmsModesetPermissions *pRemoveModeset) +{ + NvU32 d, h, dLen, hLen; + NvBool remainingPermissions = FALSE; + + dLen = ARRAY_LEN(pModeset->disp); + for (d = 0; d < dLen; d++) { + hLen = ARRAY_LEN(pModeset->disp[d].head); + for (h = 0; h < hLen; h++) { + + if (pRemoveModeset) { + pModeset->disp[d].head[h].dpyIdList = nvDpyIdListMinusDpyIdList( + pModeset->disp[d].head[h].dpyIdList, + pRemoveModeset->disp[d].head[h].dpyIdList); + } + + remainingPermissions |= + !nvDpyIdListIsEmpty(pModeset->disp[d].head[h].dpyIdList); + } + } + + return remainingPermissions; +} /*! * Clear permissions on the specified device for all NvKmsPerOpens. @@ -1004,6 +1064,7 @@ // If that didn't work, free the core channel to trigger RM's console // restore code. FreeSurfaceCtxDmasForAllOpens(pDevEvo); + DisableAndCleanVblankSyncObjectForAllOpens(pDevEvo); nvFreeCoreChannelEvo(pDevEvo); // Reallocate the core channel right after freeing it. This makes sure @@ -1011,6 +1072,7 @@ // started. if (nvAllocCoreChannelEvo(pDevEvo)) { nvDPSetAllowMultiStreaming(pDevEvo, TRUE /* allowMST */); + EnableAndSetupVblankSyncObjectForAllOpens(pDevEvo); AllocSurfaceCtxDmasForAllOpens(pDevEvo); } } @@ -1254,7 +1316,7 @@ struct NvKmsAllocDeviceParams *pParams = pParamsVoid; NVDevEvoPtr pDevEvo; struct NvKmsPerOpenDev *pOpenDev; - NvU32 disp, head; + NvU32 disp, apiHead; NvU8 layer; nvkms_memset(&pParams->reply, 0, sizeof(pParams->reply)); @@ -1312,7 +1374,7 @@ pParams->reply.deviceHandle = pOpenDev->nvKmsApiHandle; pParams->reply.subDeviceMask = NV_TWO_N_MINUS_ONE(pDevEvo->numSubDevices); - pParams->reply.numHeads = pDevEvo->numHeads; + pParams->reply.numHeads = pDevEvo->numApiHeads; pParams->reply.numDisps = pDevEvo->nDispEvo; ct_assert(ARRAY_LEN(pParams->reply.dispHandles) == @@ -1327,8 +1389,8 @@ ct_assert(ARRAY_LEN(pParams->reply.layerCaps) == ARRAY_LEN(pDevEvo->caps.layerCaps)); - for (head = 0; head < pDevEvo->numHeads; head++) { - pParams->reply.numLayers[head] = pDevEvo->head[head].numLayers; + for (apiHead = 0; apiHead < pDevEvo->numApiHeads; apiHead++) { + pParams->reply.numLayers[apiHead] = pDevEvo->apiHead[apiHead].numLayers; } for (layer = 0; @@ -1405,11 +1467,10 @@ * Forward declaration since this function is used by * DisableRemainingVblankSyncObjects(). */ -static void DisableAndCleanVblankSyncObject(struct NvKmsPerOpenDisp *pOpenDisp, - NvU32 head, +static void DisableAndCleanVblankSyncObject(NVDispEvoRec *pDispEvo, + const NvU32 apiHead, NVVblankSyncObjectRec *pVblankSyncObject, - NVEvoUpdateState *pUpdateState, - NvKmsVblankSyncObjectHandle handle); + NVEvoUpdateState *pUpdateState); static void DisableRemainingVblankSyncObjects(struct NvKmsPerOpen *pOpen, struct NvKmsPerOpenDev *pOpenDev) @@ -1418,7 +1479,7 @@ NvKmsGenericHandle disp; NVVblankSyncObjectRec *pVblankSyncObject; NvKmsVblankSyncObjectHandle handle; - NvU32 head = 0; + NvU32 apiHead = 0; nvAssert(pOpen->type == NvKmsPerOpenTypeIoctl); @@ -1436,17 +1497,18 @@ NVEvoUpdateState updateState = { }; /* For each head: */ - for (head = 0; head < ARRAY_LEN(pOpenDisp->vblankSyncObjectHandles); head++) { + for (apiHead = 0; apiHead < ARRAY_LEN(pOpenDisp->vblankSyncObjectHandles); apiHead++) { NVEvoApiHandlesRec *pHandles = - &pOpenDisp->vblankSyncObjectHandles[head]; + &pOpenDisp->vblankSyncObjectHandles[apiHead]; /* For each still-active vblank sync object: */ FOR_ALL_POINTERS_IN_EVO_API_HANDLES(pHandles, pVblankSyncObject, handle) { - DisableAndCleanVblankSyncObject(pOpenDisp, head, + DisableAndCleanVblankSyncObject(pOpenDisp->pDispEvo, apiHead, pVblankSyncObject, - &updateState, - handle); + &updateState); + /* Remove the handle from the map. */ + nvEvoDestroyApiHandle(pHandles, handle); } } @@ -1599,7 +1661,6 @@ pParams->reply.signalFormat = pConnectorEvo->signalFormat; pParams->reply.physicalIndex = pConnectorEvo->physicalIndex; pParams->reply.physicalLocation = pConnectorEvo->physicalLocation; - pParams->reply.headMask = pConnectorEvo->validHeadMask; pParams->reply.isLvds = (pConnectorEvo->or.type == NV0073_CTRL_SPECIFIC_OR_TYPE_SOR) && @@ -1700,6 +1761,7 @@ pParams->reply.mobileInternal = pDpyEvo->internal; pParams->reply.isDpMST = nvDpyEvoIsDPMST(pDpyEvo); + pParams->reply.headMask = nvDpyGetPossibleApiHeadsMask(pDpyEvo); return TRUE; } @@ -1996,20 +2058,20 @@ { struct NvKmsSetModeParams *pParams = pParamsVoid; struct NvKmsSetModeRequest *pReq = &pParams->request; - NvU32 disp, head, dispFailed, headFailed; + NvU32 disp, apiHead, dispFailed, apiHeadFailed; /* Iterate over all of the common LUT ramp pointers embedded in the SetMode * request, and copy in each one. */ for (disp = 0; disp < ARRAY_LEN(pReq->disp); disp++) { - for (head = 0; head < ARRAY_LEN(pReq->disp[disp].head); head++) { + for (apiHead = 0; apiHead < ARRAY_LEN(pReq->disp[disp].head); apiHead++) { struct NvKmsSetLutCommonParams *pCommonLutParams = - &pReq->disp[disp].head[head].lut; + &pReq->disp[disp].head[apiHead].lut; if (!CopyInLutParams(pCommonLutParams)) { /* Remember how far we got through these loops before we * failed, so that we can undo everything up to this point. */ dispFailed = disp; - headFailed = head; + apiHeadFailed = apiHead; goto fail; } } @@ -2019,12 +2081,12 @@ fail: for (disp = 0; disp < ARRAY_LEN(pReq->disp); disp++) { - for (head = 0; head < ARRAY_LEN(pReq->disp[disp].head); head++) { + for (apiHead = 0; apiHead < ARRAY_LEN(pReq->disp[disp].head); apiHead++) { struct NvKmsSetLutCommonParams *pCommonLutParams = - &pReq->disp[disp].head[head].lut; + &pReq->disp[disp].head[apiHead].lut; if (disp > dispFailed || - (disp == dispFailed && head >= headFailed)) { + (disp == dispFailed && apiHead >= apiHeadFailed)) { break; } @@ -2044,12 +2106,12 @@ { struct NvKmsSetModeParams *pParams = pParamsVoid; struct NvKmsSetModeRequest *pReq = &pParams->request; - NvU32 disp, head; + NvU32 disp, apiHead; for (disp = 0; disp < ARRAY_LEN(pReq->disp); disp++) { - for (head = 0; head < ARRAY_LEN(pReq->disp[disp].head); head++) { + for (apiHead = 0; apiHead < ARRAY_LEN(pReq->disp[disp].head); apiHead++) { struct NvKmsSetLutCommonParams *pCommonLutParams = - &pReq->disp[disp].head[head].lut; + &pReq->disp[disp].head[apiHead].lut; FreeCopiedInLutParams(pCommonLutParams); } @@ -2100,7 +2162,7 @@ pDispEvo = pOpenDisp->pDispEvo; - if (!nvHeadIsActive(pDispEvo, pParams->request.head)) { + if (!nvApiHeadIsActive(pDispEvo, pParams->request.head)) { return FALSE; } @@ -2130,7 +2192,7 @@ pDispEvo = pOpenDisp->pDispEvo; - if (!nvHeadIsActive(pDispEvo, pParams->request.head)) { + if (!nvApiHeadIsActive(pDispEvo, pParams->request.head)) { return FALSE; } @@ -2194,7 +2256,7 @@ pDispEvo = pOpenDisp->pDispEvo; - if (!nvHeadIsActive(pDispEvo, pParams->request.head)) { + if (!nvApiHeadIsActive(pDispEvo, pParams->request.head)) { return FALSE; } @@ -2214,28 +2276,15 @@ /*! * Return whether the specified head is idle. */ -static NvBool IdleBaseChannelCheckIdleOneHead( +static NvBool IdleMainLayerChannelCheckIdleOneApiHead( NVDispEvoPtr pDispEvo, - NvU32 head) + NvU32 apiHead) { - NVDevEvoPtr pDevEvo = pDispEvo->pDevEvo; - - const NvU32 apiHead = nvHardwareHeadToApiHead(head); - NVHsChannelEvoPtr pHsChannel = pDispEvo->pHsChannel[apiHead]; - - if (pHsChannel != NULL) { - return nvHsIdleFlipQueue(pHsChannel, FALSE /* force */); - } else - { - NVEvoChannelPtr pMainLayerChannel = - pDevEvo->head[head].layer[NVKMS_MAIN_LAYER]; - NvBool isMethodPending = FALSE; - NvBool ret; - - ret = pDevEvo->hal->IsChannelMethodPending(pDevEvo, pMainLayerChannel, - pDispEvo->displayOwner, &isMethodPending); - return !ret || !isMethodPending; + if (pDispEvo->pHsChannel[apiHead] != NULL) { + return nvHsIdleFlipQueue(pDispEvo->pHsChannel[apiHead], + FALSE /* force */); } + return nvIdleMainLayerChannelCheckIdleOneApiHead(pDispEvo, apiHead); } /*! @@ -2251,28 +2300,28 @@ const struct NvKmsIdleBaseChannelRequest *pRequest, struct NvKmsIdleBaseChannelReply *pReply) { - NvU32 head, sd; + NvU32 apiHead, sd; NVDispEvoPtr pDispEvo; NvBool allIdle = TRUE; FOR_ALL_EVO_DISPLAYS(pDispEvo, sd, pDevEvo) { - for (head = 0; head < pDevEvo->numHeads; head++) { + for (apiHead = 0; apiHead < pDevEvo->numApiHeads; apiHead++) { NvBool idle; - if (!nvHeadIsActive(pDispEvo, head)) { + if (!nvApiHeadIsActive(pDispEvo, apiHead)) { continue; } - if ((pRequest->subDevicesPerHead[head] & NVBIT(sd)) == 0) { + if ((pRequest->subDevicesPerHead[apiHead] & NVBIT(sd)) == 0) { continue; } - idle = IdleBaseChannelCheckIdleOneHead(pDispEvo, head); + idle = IdleMainLayerChannelCheckIdleOneApiHead(pDispEvo, apiHead); if (!idle) { - pReply->stopSubDevicesPerHead[head] |= NVBIT(sd); + pReply->stopSubDevicesPerHead[apiHead] |= NVBIT(sd); } allIdle = allIdle && idle; } @@ -2358,6 +2407,96 @@ } +struct NvKmsFlipExtraUserState +{ + // Nothing needed. +}; + +static NvBool FlipPrepUser( + void *pParamsVoid, + void *pExtraUserStateVoid) +{ + struct NvKmsFlipParams *pParams = pParamsVoid; + struct NvKmsFlipRequest *pRequest = &pParams->request; + struct NvKmsFlipRequestOneHead *pFlipHeadKernel = NULL; + NvU64 pFlipHeadUser = pRequest->pFlipHead; + size_t size; + int status; + + if (!nvKmsNvU64AddressIsSafe(pFlipHeadUser)) { + return FALSE; + } + + if (pRequest->numFlipHeads <= 0 || + pRequest->numFlipHeads > NV_MAX_FLIP_REQUEST_HEADS) { + return FALSE; + } + + size = sizeof(*pFlipHeadKernel) * pRequest->numFlipHeads; + pFlipHeadKernel = nvAlloc(size); + if (!pFlipHeadKernel) { + return FALSE; + } + + status = nvkms_copyin((char *)pFlipHeadKernel, pFlipHeadUser, size); + if (status != 0) { + nvFree(pFlipHeadKernel); + return FALSE; + } + + pRequest->pFlipHead = nvKmsPointerToNvU64(pFlipHeadKernel); + + return TRUE; +} + +static NvBool FlipDoneUser( + void *pParamsVoid, + void *pExtraUserStateVoid) +{ + struct NvKmsFlipParams *pParams = pParamsVoid; + struct NvKmsFlipRequest *pRequest = &pParams->request; + + nvFree(nvKmsNvU64ToPointer(pRequest->pFlipHead)); + /* The request is not copied back out to userspace (only the reply is), so + * we don't need to worry about restoring the user pointer */ + pRequest->pFlipHead = 0; + + return TRUE; +} + +/*! + * For each entry in the array pointed to by 'pFlipHead', of length + * 'numFlipHeads', verify that the sd and head values specified are within + * bounds and that there are no duplicates. + */ +static NvBool ValidateFlipHeads( + NVDevEvoPtr pDevEvo, + const struct NvKmsFlipRequestOneHead *pFlipHead, + NvU32 numFlipHeads) +{ + NvU32 i; + ct_assert(NVKMS_MAX_HEADS_PER_DISP <= 8); + NvU8 apiHeadsUsed[NVKMS_MAX_SUBDEVICES] = { }; + + for (i = 0; i < numFlipHeads; i++) { + const NvU32 sd = pFlipHead[i].sd; + const NvU32 apiHead = pFlipHead[i].head; + + if (sd >= pDevEvo->numSubDevices) { + return FALSE; + } + if (apiHead >= pDevEvo->numApiHeads) { + return FALSE; + } + if ((apiHeadsUsed[sd] & (1 << apiHead)) != 0) { + return FALSE; + } + apiHeadsUsed[sd] |= (1 << apiHead); + } + + return TRUE; +} + /*! * Flip the specified head. */ @@ -2366,6 +2505,11 @@ { struct NvKmsFlipParams *pParams = pParamsVoid; struct NvKmsPerOpenDev *pOpenDev; + NVDevEvoPtr pDevEvo = NULL; + const struct NvKmsFlipRequest *pRequest = &pParams->request; + const struct NvKmsFlipRequestOneHead *pFlipHead = + nvKmsNvU64ToPointer(pRequest->pFlipHead); + const NvU32 numFlipHeads = pRequest->numFlipHeads; pOpenDev = GetPerOpenDev(pOpen, pParams->request.deviceHandle); @@ -2373,8 +2517,16 @@ return FALSE; } - return nvHsIoctlFlip(pOpenDev->pDevEvo, pOpenDev, - &pParams->request, &pParams->reply); + pDevEvo = pOpenDev->pDevEvo; + + if (!ValidateFlipHeads(pDevEvo, pFlipHead, numFlipHeads)) { + return FALSE; + } + + return nvHsIoctlFlip(pDevEvo, pOpenDev, + pFlipHead, numFlipHeads, + pRequest->commit, pRequest->allowVrr, + &pParams->reply); } @@ -3191,6 +3343,86 @@ return TRUE; } +/*! + * Clear the set of permissions from pRevokingOpenDev. + * + * For NvKmsPerOpen::type==Ioctl, clear from permissions. It doesn't clear + * itself or privileged. + * + * For NvKmsPerOpen::type==GrantPermissions, clear from + * NvKmsPerOpen::grantPermissions, and reset NvKmsPerOpen::type to Undefined + * if it is empty. + */ +static NvBool RevokePermissionsSet( + struct NvKmsPerOpenDev *pRevokingOpenDev, + const struct NvKmsPermissions *pRevokingPermissions) +{ + const NVDevEvoRec *pDevEvo; + struct NvKmsPerOpen *pOpen; + const struct NvKmsFlipPermissions *pRemoveFlip; + const struct NvKmsModesetPermissions *pRemoveModeset; + + // Only process valid permissions. + if (pRevokingPermissions->type != NV_KMS_PERMISSIONS_TYPE_FLIPPING && + pRevokingPermissions->type != NV_KMS_PERMISSIONS_TYPE_MODESET) { + return FALSE; + } + + pDevEvo = pRevokingOpenDev->pDevEvo; + pRemoveFlip = + (pRevokingPermissions->type == NV_KMS_PERMISSIONS_TYPE_FLIPPING) + ? &pRevokingPermissions->flip + : NULL; + pRemoveModeset = + (pRevokingPermissions->type == NV_KMS_PERMISSIONS_TYPE_MODESET) + ? &pRevokingPermissions->modeset + : NULL; + + nvListForEachEntry(pOpen, &perOpenList, perOpenListEntry) { + if ((pOpen->type == NvKmsPerOpenTypeGrantPermissions) && + (pOpen->grantPermissions.pDevEvo == pDevEvo)) { + NvBool remainingPermissions = FALSE; + struct NvKmsPermissions *pFdPermissions = + &pOpen->grantPermissions.permissions; + + if (pFdPermissions->type == NV_KMS_PERMISSIONS_TYPE_FLIPPING) { + remainingPermissions = + RemoveFlipPermissions(&pFdPermissions->flip, pRemoveFlip); + } else { + remainingPermissions = RemoveModesetPermissions( + &pFdPermissions->modeset, pRemoveModeset); + } + + // Reset if it is empty. + if (!remainingPermissions) { + nvkms_memset(&pOpen->grantPermissions, 0, + sizeof(pOpen->grantPermissions)); + pOpen->type = NvKmsPerOpenTypeUndefined; + } + + } else if (pOpen->type == NvKmsPerOpenTypeIoctl) { + + struct NvKmsPerOpenDev *pOpenDev = DevEvoToOpenDev(pOpen, pDevEvo); + if (pOpenDev == NULL) { + continue; + } + + if (pOpenDev == pRevokingOpenDev || pOpenDev->isPrivileged) { + continue; + } + + if (pRevokingPermissions->type == NV_KMS_PERMISSIONS_TYPE_FLIPPING) { + RemoveFlipPermissions(&pOpenDev->flipPermissions, pRemoveFlip); + } else { + RemoveModesetPermissions(&pOpenDev->modesetPermissions, + pRemoveModeset); + } + } + } + + return TRUE; +} + static NvBool RevokePermissions(struct NvKmsPerOpen *pOpen, void *pParamsVoid) { struct NvKmsRevokePermissionsParams *pParams = pParamsVoid; @@ -3215,11 +3447,18 @@ return FALSE; } - /* Revoke permissions for everyone except the caller. */ + if (pParams->request.permissionsTypeBitmask > 0) { + // Old behavior, revoke all permissions of a type. + + /* Revoke permissions for everyone except the caller. */ + RevokePermissionsInternal(pParams->request.permissionsTypeBitmask, + pOpenDev->pDevEvo, + pOpenDev /* pOpenDevExclude */); + } else { + /* If not using bitmask, revoke using the set. */ + return RevokePermissionsSet(pOpenDev, &pParams->request.permissions); + } - RevokePermissionsInternal(pParams->request.permissionsTypeBitmask, - pOpenDev->pDevEvo, - pOpenDev /* pOpenDevExclude */); return TRUE; } @@ -3341,7 +3580,7 @@ pDispEvo = pOpenDisp->pDispEvo; - if (!nvHeadIsActive(pDispEvo, pParams->request.head)) { + if (!nvApiHeadIsActive(pDispEvo, pParams->request.head)) { return FALSE; } @@ -3352,8 +3591,18 @@ crcOut.compositorCrc32 = &(pParams->reply.compositorCrc32); crcOut.outputCrc32 = &(pParams->reply.outputCrc32); - if (!nvReadCRC32Evo(pDispEvo, pParams->request.head, &crcOut)) { - return FALSE; + { + /* + * XXX[2Heads1OR] Is it sufficient to query CRC only for the primary + * hardware head? + */ + NvU32 head = nvGetPrimaryHwHead(pDispEvo, pParams->request.head); + + nvAssert(head != NV_INVALID_HEAD); + + if (!nvReadCRC32Evo(pDispEvo, head, &crcOut)) { + return FALSE; + } } return TRUE; @@ -3812,17 +4061,103 @@ return nvExportVrrSemaphoreSurface(pOpenDev->pDevEvo, req->memFd); } +static void EnableAndSetupVblankSyncObject(NVDispEvoRec *pDispEvo, + const NvU32 apiHead, + NVVblankSyncObjectRec *pVblankSyncObject, + NVEvoUpdateState *pUpdateState) +{ + /* + * The core channel re-allocation code path may end up allocating + * the fewer number of sync objects than the number of sync objects which + * are allocated and in use by the NVKMS clients, hCtxDma = 0 if the + * nvAllocCoreChannelEvo()-> InitApiHeadState()-> nvRmAllocCoreRGSyncpts() + * code path failes to re-allocate that sync object. + */ + if (nvApiHeadIsActive(pDispEvo, apiHead) && + (pVblankSyncObject->evoSyncpt.hCtxDma != 0)) { + NvU32 head = nvGetPrimaryHwHead(pDispEvo, apiHead); + + nvAssert(head != NV_INVALID_HEAD); + + pDispEvo->pDevEvo->hal->ConfigureVblankSyncObject( + pDispEvo->pDevEvo, + pDispEvo->headState[head].timings.rasterBlankStart.y, + head, + pVblankSyncObject->index, + pVblankSyncObject->evoSyncpt.hCtxDma, + pUpdateState); + + pVblankSyncObject->enabled = TRUE; + } + + pVblankSyncObject->inUse = TRUE; +} + +static void EnableAndSetupVblankSyncObjectForAllOpens(NVDevEvoRec *pDevEvo) +{ + /* + * An NVEvoUpdateState has disp-scope, and we will only have + * one disp when programming syncpts. + */ + NVEvoUpdateState updateState = { }; + struct NvKmsPerOpen *pOpen; + + if (!pDevEvo->supportsSyncpts || + !pDevEvo->hal->caps.supportsVblankSyncObjects) { + return; + } + + /* If Syncpts are supported, we're on Orin, which only has one display. */ + nvAssert(pDevEvo->nDispEvo == 1); + + nvListForEachEntry(pOpen, &perOpenIoctlList, perOpenIoctlListEntry) { + struct NvKmsPerOpenDev *pOpenDev = DevEvoToOpenDev(pOpen, pDevEvo); + struct NvKmsPerOpenDisp *pOpenDisp; + NvKmsGenericHandle disp; + + if (pOpenDev == NULL) { + continue; + } + + FOR_ALL_POINTERS_IN_EVO_API_HANDLES(&pOpenDev->dispHandles, + pOpenDisp, disp) { + + nvAssert(pOpenDisp->pDispEvo == pDevEvo->pDispEvo[0]); + + for (NvU32 apiHead = 0; apiHead < + ARRAY_LEN(pOpenDisp->vblankSyncObjectHandles); apiHead++) { + NVEvoApiHandlesRec *pHandles = + &pOpenDisp->vblankSyncObjectHandles[apiHead]; + NVVblankSyncObjectRec *pVblankSyncObject; + NvKmsVblankSyncObjectHandle handle; + + FOR_ALL_POINTERS_IN_EVO_API_HANDLES(pHandles, + pVblankSyncObject, handle) { + EnableAndSetupVblankSyncObject(pOpenDisp->pDispEvo, apiHead, + pVblankSyncObject, + &updateState); + } + } + } + } + + if (!nvIsUpdateStateEmpty(pDevEvo, &updateState)) { + nvEvoUpdateAndKickOff(pDevEvo->pDispEvo[0], TRUE, &updateState, + TRUE); + } +} + static NvBool EnableVblankSyncObject( struct NvKmsPerOpen *pOpen, void *pParamsVoid) { struct NvKmsEnableVblankSyncObjectParams *pParams = pParamsVoid; struct NvKmsPerOpenDisp* pOpenDisp = NULL; - NVDispHeadStateEvoRec *pHeadState = NULL; + NVDispApiHeadStateEvoRec *pApiHeadState = NULL; NVDevEvoPtr pDevEvo = NULL; NvKmsVblankSyncObjectHandle vblankHandle = 0; int freeVblankSyncObjectIdx = 0; - NvU32 head = pParams->request.head; + NvU32 apiHead = pParams->request.head; NVVblankSyncObjectRec *vblankSyncObjects = NULL; NVDispEvoPtr pDispEvo = NULL; NVEvoUpdateState updateState = { }; @@ -3847,12 +4182,12 @@ } /* Validate requested head because it comes from user input. */ - if (head >= ARRAY_LEN(pDispEvo->headState)) { - nvEvoLogDebug(EVO_LOG_ERROR, "Invalid head requested, head=%d.", head); + if (apiHead >= ARRAY_LEN(pDispEvo->apiHeadState)) { + nvEvoLogDebug(EVO_LOG_ERROR, "Invalid head requested, head=%d.", apiHead); return FALSE; } - pHeadState = &pDispEvo->headState[head]; - vblankSyncObjects = pHeadState->vblankSyncObjects; + pApiHeadState = &pDispEvo->apiHeadState[apiHead]; + vblankSyncObjects = pApiHeadState->vblankSyncObjects; pDevEvo = pDispEvo->pDevEvo; /* @@ -3860,69 +4195,51 @@ * use. */ for (freeVblankSyncObjectIdx = 0; - freeVblankSyncObjectIdx < pHeadState->numVblankSyncObjectsCreated; + freeVblankSyncObjectIdx < pApiHeadState->numVblankSyncObjectsCreated; freeVblankSyncObjectIdx++) { if (!vblankSyncObjects[freeVblankSyncObjectIdx].inUse) { break; } } - if (freeVblankSyncObjectIdx == pHeadState->numVblankSyncObjectsCreated) { + if (freeVblankSyncObjectIdx == pApiHeadState->numVblankSyncObjectsCreated) { return FALSE; } /* Save the created vblank handle if it is valid. */ vblankHandle = - nvEvoCreateApiHandle(&pOpenDisp->vblankSyncObjectHandles[head], + nvEvoCreateApiHandle(&pOpenDisp->vblankSyncObjectHandles[apiHead], &vblankSyncObjects[freeVblankSyncObjectIdx]); if (vblankHandle == 0) { nvEvoLogDebug(EVO_LOG_ERROR, "Unable to create vblank handle."); return FALSE; } - if (nvHeadIsActive(pDispEvo, head)) { - /* - * Instruct the hardware to enable a semaphore corresponding to this - * syncpt. The Update State will be populated. - */ - pDevEvo->hal->ConfigureVblankSyncObject( - pDevEvo, - pHeadState->timings.rasterBlankStart.y, - head, - freeVblankSyncObjectIdx, - vblankSyncObjects[freeVblankSyncObjectIdx].evoSyncpt.hCtxDma, - &updateState); - - /* - * Instruct hardware to execute the staged commands from the - * ConfigureVblankSyncObject() call above. This will set up and wait for a - * notification that the hardware execution actually completed. - */ + EnableAndSetupVblankSyncObject(pDispEvo, apiHead, + &vblankSyncObjects[freeVblankSyncObjectIdx], + &updateState); + if (!nvIsUpdateStateEmpty(pOpenDisp->pDispEvo->pDevEvo, &updateState)) { nvEvoUpdateAndKickOff(pDispEvo, TRUE, &updateState, TRUE); - - vblankSyncObjects[freeVblankSyncObjectIdx].enabled = TRUE; } - /* Populate the vblankSyncObjects array. */ - vblankSyncObjects[freeVblankSyncObjectIdx].inUse = TRUE; - /* Populate the reply field. */ pParams->reply.vblankHandle = vblankHandle; /* Note: the syncpt ID is NOT the same as the vblank handle. */ pParams->reply.syncptId = - pHeadState->vblankSyncObjects[freeVblankSyncObjectIdx].evoSyncpt.id; + pApiHeadState->vblankSyncObjects[freeVblankSyncObjectIdx].evoSyncpt.id; return TRUE; } -static void DisableAndCleanVblankSyncObject(struct NvKmsPerOpenDisp *pOpenDisp, - NvU32 head, +static void DisableAndCleanVblankSyncObject(NVDispEvoRec *pDispEvo, + const NvU32 apiHead, NVVblankSyncObjectRec *pVblankSyncObject, - NVEvoUpdateState *pUpdateState, - NvKmsVblankSyncObjectHandle handle) + NVEvoUpdateState *pUpdateState) { - NVDispEvoPtr pDispEvo = pOpenDisp->pDispEvo; + if (nvApiHeadIsActive(pDispEvo, apiHead)) { + NvU32 head = nvGetPrimaryHwHead(pDispEvo, apiHead); + + nvAssert(head != NV_INVALID_HEAD); - if (nvHeadIsActive(pDispEvo, head)) { /* * Instruct the hardware to disable the semaphore corresponding to this * syncpt. The Update State will be populated. @@ -3944,9 +4261,60 @@ pVblankSyncObject->inUse = FALSE; pVblankSyncObject->enabled = FALSE; +} - /* Remove the handle from the map. */ - nvEvoDestroyApiHandle(&pOpenDisp->vblankSyncObjectHandles[head], handle); +static void DisableAndCleanVblankSyncObjectForAllOpens(NVDevEvoRec *pDevEvo) +{ + /* + * An NVEvoUpdateState has disp-scope, and we will only have + * one disp when programming syncpts. + */ + NVEvoUpdateState updateState = { }; + struct NvKmsPerOpen *pOpen; + + if (!pDevEvo->supportsSyncpts || + !pDevEvo->hal->caps.supportsVblankSyncObjects) { + return; + } + + /* If Syncpts are supported, we're on Orin, which only has one display. */ + nvAssert(pDevEvo->nDispEvo == 1); + + nvListForEachEntry(pOpen, &perOpenIoctlList, perOpenIoctlListEntry) { + struct NvKmsPerOpenDev *pOpenDev = DevEvoToOpenDev(pOpen, pDevEvo); + struct NvKmsPerOpenDisp *pOpenDisp; + NvKmsGenericHandle disp; + + if (pOpenDev == NULL) { + continue; + } + + FOR_ALL_POINTERS_IN_EVO_API_HANDLES(&pOpenDev->dispHandles, + pOpenDisp, disp) { + + nvAssert(pOpenDisp->pDispEvo == pDevEvo->pDispEvo[0]); + + for (NvU32 apiHead = 0; apiHead < + ARRAY_LEN(pOpenDisp->vblankSyncObjectHandles); apiHead++) { + NVEvoApiHandlesRec *pHandles = + &pOpenDisp->vblankSyncObjectHandles[apiHead]; + NVVblankSyncObjectRec *pVblankSyncObject; + NvKmsVblankSyncObjectHandle handle; + + FOR_ALL_POINTERS_IN_EVO_API_HANDLES(pHandles, + pVblankSyncObject, handle) { + DisableAndCleanVblankSyncObject(pOpenDisp->pDispEvo, apiHead, + pVblankSyncObject, + &updateState); + } + } + } + } + + if (!nvIsUpdateStateEmpty(pDevEvo, &updateState)) { + nvEvoUpdateAndKickOff(pDevEvo->pDispEvo[0], TRUE, &updateState, + TRUE); + } } static NvBool DisableVblankSyncObject( @@ -3958,7 +4326,7 @@ GetPerOpenDisp(pOpen, pParams->request.deviceHandle, pParams->request.dispHandle); NVVblankSyncObjectRec *pVblankSyncObject = NULL; - NvU32 head = pParams->request.head; + NvU32 apiHead = pParams->request.head; NVDevEvoPtr pDevEvo = NULL; NVEvoUpdateState updateState = { }; @@ -3978,14 +4346,14 @@ } /* Validate requested head because it comes from user input. */ - if (head >= ARRAY_LEN(pOpenDisp->pDispEvo->headState)) { - nvEvoLogDebug(EVO_LOG_ERROR, "Invalid head requested, head=%d.", head); + if (apiHead >= ARRAY_LEN(pOpenDisp->pDispEvo->apiHeadState)) { + nvEvoLogDebug(EVO_LOG_ERROR, "Invalid head requested, head=%d.", apiHead); return FALSE; } /* Mark the indicated object as free. */ pVblankSyncObject = - nvEvoGetPointerFromApiHandle(&pOpenDisp->vblankSyncObjectHandles[head], + nvEvoGetPointerFromApiHandle(&pOpenDisp->vblankSyncObjectHandles[apiHead], pParams->request.vblankHandle); if (pVblankSyncObject == NULL) { nvEvoLogDebug(EVO_LOG_ERROR, "unable to find object with provided " @@ -3993,8 +4361,8 @@ return FALSE; } - DisableAndCleanVblankSyncObject(pOpenDisp, head, pVblankSyncObject, - &updateState, pParams->request.vblankHandle); + DisableAndCleanVblankSyncObject(pOpenDisp->pDispEvo, apiHead, + pVblankSyncObject, &updateState); if (!nvIsUpdateStateEmpty(pOpenDisp->pDispEvo->pDevEvo, &updateState)) { /* @@ -4006,11 +4374,14 @@ nvEvoUpdateAndKickOff(pOpenDisp->pDispEvo, TRUE, &updateState, TRUE); } + /* Remove the handle from the map. */ + nvEvoDestroyApiHandle(&pOpenDisp->vblankSyncObjectHandles[apiHead], + pParams->request.vblankHandle); + return TRUE; } static void NotifyVblankCallback(NVDispEvoRec *pDispEvo, - const NvU32 head, NVVBlankCallbackPtr pCallbackData) { struct NvKmsPerOpen *pEventOpenFd = pCallbackData->pUserData; @@ -4034,7 +4405,7 @@ struct NvKmsPerOpenDisp* pOpenDisp = GetPerOpenDisp(pOpen, pParams->request.deviceHandle, pParams->request.dispHandle); - NvU32 head = pParams->request.head; + const NvU32 apiHead = pParams->request.head; pEventOpenFd = nvkms_get_per_open_data(pParams->request.unicastEvent.fd); @@ -4048,25 +4419,23 @@ pEventOpenFd->type = NvKmsPerOpenTypeUnicastEvent; - pCallbackData = nvRegisterVBlankCallback(pOpenDisp->pDispEvo, - head, - NotifyVblankCallback, - pEventOpenFd); + pCallbackData = nvApiHeadRegisterVBlankCallback(pOpenDisp->pDispEvo, + apiHead, + NotifyVblankCallback, + pEventOpenFd); if (pCallbackData == NULL) { return NV_FALSE; } pEventOpenFd->unicastEvent.type = NvKmsUnicastEventTypeVblankNotification; pEventOpenFd->unicastEvent.e.vblankNotification.pOpenDisp = pOpenDisp; - pEventOpenFd->unicastEvent.e.vblankNotification.head = head; + pEventOpenFd->unicastEvent.e.vblankNotification.apiHead = apiHead; pEventOpenFd->unicastEvent.e.vblankNotification.hCallback - = nvEvoCreateApiHandle(&pOpenDisp->vblankCallbackHandles[head], + = nvEvoCreateApiHandle(&pOpenDisp->vblankCallbackHandles[apiHead], pCallbackData); if (pEventOpenFd->unicastEvent.e.vblankNotification.hCallback == 0) { - nvUnregisterVBlankCallback(pOpenDisp->pDispEvo, - head, - pCallbackData); + nvApiHeadUnregisterVBlankCallback(pOpenDisp->pDispEvo, pCallbackData); return NV_FALSE; } @@ -4145,7 +4514,7 @@ ENTRY(NVKMS_IOCTL_MOVE_CURSOR, MoveCursor), ENTRY_CUSTOM_USER(NVKMS_IOCTL_SET_LUT, SetLut), ENTRY(NVKMS_IOCTL_IDLE_BASE_CHANNEL, IdleBaseChannel), - ENTRY(NVKMS_IOCTL_FLIP, Flip), + ENTRY_CUSTOM_USER(NVKMS_IOCTL_FLIP, Flip), ENTRY(NVKMS_IOCTL_DECLARE_DYNAMIC_DPY_INTEREST, DeclareDynamicDpyInterest), ENTRY(NVKMS_IOCTL_REGISTER_SURFACE, RegisterSurface), @@ -4568,7 +4937,7 @@ case NvKmsUnicastEventTypeVblankNotification: nvEvoLogInfoString(&infoString, " head : %x", - pOpen->unicastEvent.e.vblankNotification.head); + pOpen->unicastEvent.e.vblankNotification.apiHead); break; default: break; @@ -4753,7 +5122,7 @@ { NVDevEvoPtr pDevEvo; NVDispEvoPtr pDispEvo; - NvU32 dispIndex, head; + NvU32 dispIndex, apiHead; NVEvoInfoStringRec infoString; FOR_ALL_EVO_DEVS(pDevEvo) { @@ -4772,9 +5141,9 @@ dispIndex, pDispEvo); outString(data, buffer); - for (head = 0; head < pDevEvo->numHeads; head++) { + for (apiHead = 0; apiHead < pDevEvo->numApiHeads; apiHead++) { nvInitInfoString(&infoString, buffer, size); - nvHsProcFs(&infoString, pDevEvo, dispIndex, head); + nvHsProcFs(&infoString, pDevEvo, dispIndex, apiHead); nvEvoLogInfoString(&infoString, ""); outString(data, buffer); } @@ -5078,6 +5447,8 @@ static void FreeGlobalState(void) { + nvInvalidateTopologiesEvo(); + nvKmsClose(nvEvoGlobal.nvKmsPerOpen); nvEvoGlobal.nvKmsPerOpen = NULL; @@ -5086,6 +5457,8 @@ nvEvoGlobal.clientHandle); nvEvoGlobal.clientHandle = 0; } + + nvClearDpyOverrides(); } NvBool nvKmsModuleLoad(void) @@ -5295,34 +5668,11 @@ } -void nvSendFlipOccurredEventEvo( - const NVDevEvoRec *pDevEvo, - NVEvoChannelMask channelMask) +void nvSendFlipOccurredEventEvo(const NVDispEvoRec *pDispEvo, + const NvU32 apiHead, const NvU32 layer) { struct NvKmsPerOpen *pOpen; const NvU32 eventType = NVKMS_EVENT_TYPE_FLIP_OCCURRED; - const NvU32 dispIndex = 0; /* XXX NVKMS TODO: need disp-scope in event */ - const NVDispEvoRec *pDispEvo = pDevEvo->pDispEvo[dispIndex]; - NvU32 head, layer; - - nvAssert(NV_EVO_CHANNEL_MASK_POPCOUNT(channelMask) == 1); - - for (head = 0; head < pDevEvo->numHeads; head++) { - for (layer = 0; layer < pDevEvo->head[head].numLayers; layer++) { - if (pDevEvo->head[head].layer[layer]->channelMask == channelMask) { - break; - } - } - - if (layer < pDevEvo->head[head].numLayers) { - break; - } - } - - if (head >= pDevEvo->numHeads) { - nvAssert(!"Bad channelMask"); - return; - } nvListForEachEntry(pOpen, &perOpenIoctlList, perOpenIoctlListEntry) { @@ -5333,7 +5683,7 @@ struct NvKmsPerOpenDev *pOpenDev; const struct NvKmsFlipPermissions *pFlipPermissions; - pOpenDev = DevEvoToOpenDev(pOpen, pDevEvo); + pOpenDev = DevEvoToOpenDev(pOpen, pDispEvo->pDevEvo); if (pOpenDev == NULL) { continue; @@ -5345,8 +5695,8 @@ pFlipPermissions = &pOpenDev->flipPermissions; - if ((pFlipPermissions->disp[dispIndex].head[head].layerMask & - NVBIT(layer)) == 0x0) { + if ((pFlipPermissions->disp[pDispEvo->displayOwner]. + head[apiHead].layerMask & NVBIT(layer)) == 0x0) { continue; } @@ -5358,7 +5708,7 @@ event.eventType = eventType; event.u.flipOccurred.deviceHandle = deviceHandle; event.u.flipOccurred.dispHandle = dispHandle; - event.u.flipOccurred.head = head; + event.u.flipOccurred.head = apiHead; event.u.flipOccurred.layer = layer; SendEvent(pOpen, &event); @@ -5383,7 +5733,7 @@ NvKmsGenericHandle callbackHandle; NVVBlankCallbackPtr pCallbackData; struct NvKmsPerOpenDisp *pOpenDisp; - NvU32 head; + NvU32 apiHead; if (pOpen == NULL) { return; @@ -5406,24 +5756,23 @@ pOpen->unicastEvent.e.vblankNotification.hCallback; pOpenDisp = pOpen->unicastEvent.e.vblankNotification.pOpenDisp; - head = pOpen->unicastEvent.e.vblankNotification.head; + apiHead = pOpen->unicastEvent.e.vblankNotification.apiHead; /* Unregister the vblank callback */ pCallbackData = - nvEvoGetPointerFromApiHandle(&pOpenDisp->vblankCallbackHandles[head], + nvEvoGetPointerFromApiHandle(&pOpenDisp->vblankCallbackHandles[apiHead], callbackHandle); - nvUnregisterVBlankCallback(pOpenDisp->pDispEvo, - head, - pCallbackData); + nvApiHeadUnregisterVBlankCallback(pOpenDisp->pDispEvo, + pCallbackData); - nvEvoDestroyApiHandle(&pOpenDisp->vblankCallbackHandles[head], + nvEvoDestroyApiHandle(&pOpenDisp->vblankCallbackHandles[apiHead], callbackHandle); /* invalidate the pOpen data */ pOpen->unicastEvent.e.vblankNotification.hCallback = 0; pOpen->unicastEvent.e.vblankNotification.pOpenDisp = NULL; - pOpen->unicastEvent.e.vblankNotification.head = NV_INVALID_HEAD; + pOpen->unicastEvent.e.vblankNotification.apiHead = NV_INVALID_HEAD; break; default: nvAssert("Invalid Unicast Event Type!"); @@ -5631,10 +5980,12 @@ * that becomes stale after suspend. Shutting the heads down here * clears the relevant state explicitly. */ - nvShutDownHeads(pDevEvo, - NULL /* pTestFunc, shut down all heads */); + nvShutDownApiHeads(pDevEvo, + NULL /* pTestFunc, shut down all heads */); pDevEvo->skipConsoleRestore = TRUE; + DisableAndCleanVblankSyncObjectForAllOpens(pDevEvo); + FreeSurfaceCtxDmasForAllOpens(pDevEvo); nvSuspendDevEvo(pDevEvo); @@ -5656,6 +6007,7 @@ if (nvResumeDevEvo(pDevEvo)) { nvDPSetAllowMultiStreaming(pDevEvo, TRUE /* allowMST */); + EnableAndSetupVblankSyncObjectForAllOpens(pDevEvo); AllocSurfaceCtxDmasForAllOpens(pDevEvo); } diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia-modeset/src/shaders/g_ampere_shader_info.h nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia-modeset/src/shaders/g_ampere_shader_info.h --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia-modeset/src/shaders/g_ampere_shader_info.h 2023-10-25 20:22:42.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia-modeset/src/shaders/g_ampere_shader_info.h 2024-03-05 22:12:24.000000000 +0000 @@ -1,4 +1,4 @@ -// Generated using 'Offline GLSL Shader Compiler Version 13.0.0.0.465.00.dev/gpu_drv/dev_a-14542' +// Generated using 'Offline GLSL Shader Compiler Version 13.0.0.0.530.00.dev/gpu_drv/dev_a-15624' // WARNING: This file is auto-generated! Do not hand-edit! // Instead, edit the GLSL shaders and run 'unix-build nvmake @generate'. @@ -9,7 +9,7 @@ static const Nv3dProgramInfo AmpereProgramInfo[NUM_PROGRAMS] = { // nvidia_headsurface_vertex { .offset = 0x00000000, - .registerCount = 16, + .registerCount = 15, .type = NV3D_SHADER_TYPE_VERTEX, .constIndex = -1, .stage = NV3D_HW_SHADER_STAGE_VERTEX_B, Binary files /srv/release.debian.org/tmp/sDtPvc6wfL/nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia-modeset/src/shaders/g_ampere_shaders and /srv/release.debian.org/tmp/PYKxhEfHRB/nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia-modeset/src/shaders/g_ampere_shaders differ diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia-modeset/src/shaders/g_hopper_shader_info.h nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia-modeset/src/shaders/g_hopper_shader_info.h --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia-modeset/src/shaders/g_hopper_shader_info.h 2023-10-25 20:22:42.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia-modeset/src/shaders/g_hopper_shader_info.h 2024-03-05 22:12:24.000000000 +0000 @@ -1,4 +1,4 @@ -// Generated using 'Offline GLSL Shader Compiler Version 13.0.0.0.465.00.dev/gpu_drv/dev_a-14542' +// Generated using 'Offline GLSL Shader Compiler Version 13.0.0.0.530.00.dev/gpu_drv/dev_a-15624' // WARNING: This file is auto-generated! Do not hand-edit! // Instead, edit the GLSL shaders and run 'unix-build nvmake @generate'. @@ -9,7 +9,7 @@ static const Nv3dProgramInfo HopperProgramInfo[NUM_PROGRAMS] = { // nvidia_headsurface_vertex { .offset = 0x00000000, - .registerCount = 13, + .registerCount = 14, .type = NV3D_SHADER_TYPE_VERTEX, .constIndex = -1, .stage = NV3D_HW_SHADER_STAGE_VERTEX_B, Binary files /srv/release.debian.org/tmp/sDtPvc6wfL/nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia-modeset/src/shaders/g_hopper_shaders and /srv/release.debian.org/tmp/PYKxhEfHRB/nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia-modeset/src/shaders/g_hopper_shaders differ diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia-modeset/src/shaders/g_maxwell_shader_info.h nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia-modeset/src/shaders/g_maxwell_shader_info.h --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia-modeset/src/shaders/g_maxwell_shader_info.h 2023-10-25 20:22:42.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia-modeset/src/shaders/g_maxwell_shader_info.h 2024-03-05 22:12:24.000000000 +0000 @@ -1,4 +1,4 @@ -// Generated using 'Offline GLSL Shader Compiler Version 13.0.0.0.465.00.dev/gpu_drv/dev_a-14542' +// Generated using 'Offline GLSL Shader Compiler Version 13.0.0.0.530.00.dev/gpu_drv/dev_a-15624' // WARNING: This file is auto-generated! Do not hand-edit! // Instead, edit the GLSL shaders and run 'unix-build nvmake @generate'. @@ -9,7 +9,7 @@ static const Nv3dProgramInfo MaxwellProgramInfo[NUM_PROGRAMS] = { // nvidia_headsurface_vertex { .offset = 0x00000030, - .registerCount = 11, + .registerCount = 13, .type = NV3D_SHADER_TYPE_VERTEX, .constIndex = -1, .stage = NV3D_HW_SHADER_STAGE_VERTEX_B, @@ -322,9 +322,9 @@ 0x000012f8, // 6.80471e-42 0x00001478, // 7.3428e-42 0x00001630, // 7.95938e-42 - 0x00001a40, // 9.41673e-42 - 0x00001de0, // 1.07171e-41 - 0x000022e0, // 1.25108e-41 + 0x00001a38, // 9.40552e-42 + 0x00001df0, // 1.07396e-41 + 0x000022f0, // 1.25332e-41 0x00002880, // 1.45287e-41 0x00002a00, // 1.50668e-41 0x00002bb8, // 1.56833e-41 @@ -346,9 +346,9 @@ 0x000012f8, // 6.80471e-42 0x00001478, // 7.3428e-42 0x00001630, // 7.95938e-42 - 0x00001a70, // 9.48399e-42 - 0x00001e10, // 1.07844e-41 - 0x00002310, // 1.25781e-41 + 0x00001a60, // 9.46157e-42 + 0x00001e18, // 1.07956e-41 + 0x00002318, // 1.25893e-41 0x000028b0, // 1.45959e-41 0x00002a30, // 1.5134e-41 0x00002be0, // 1.57394e-41 @@ -361,9 +361,9 @@ 0x000012f8, // 6.80471e-42 0x00001478, // 7.3428e-42 0x00001630, // 7.95938e-42 - 0x00001ab0, // 9.57367e-42 - 0x00001e50, // 1.08741e-41 - 0x00002350, // 1.26677e-41 + 0x00001aa0, // 9.55125e-42 + 0x00001e58, // 1.08853e-41 + 0x00002358, // 1.26789e-41 0x000028f0, // 1.46856e-41 0x00002a70, // 1.52237e-41 0x00002c20, // 1.58291e-41 @@ -376,9 +376,9 @@ 0x00001300, // 6.81592e-42 0x00001480, // 7.35401e-42 0x00001638, // 7.97059e-42 - 0x00001a90, // 9.52883e-42 - 0x00001e30, // 1.08292e-41 - 0x00002330, // 1.26229e-41 + 0x00001a80, // 9.50641e-42 + 0x00001e38, // 1.08404e-41 + 0x00002338, // 1.26341e-41 0x000028d0, // 1.46408e-41 0x00002a50, // 1.51789e-41 0x00002c00, // 1.57842e-41 @@ -391,9 +391,9 @@ 0x00001300, // 6.81592e-42 0x00001480, // 7.35401e-42 0x00001638, // 7.97059e-42 - 0x00001ad0, // 9.61851e-42 - 0x00001e70, // 1.09189e-41 - 0x00002370, // 1.27126e-41 + 0x00001ac0, // 9.59609e-42 + 0x00001e78, // 1.09301e-41 + 0x00002378, // 1.27238e-41 0x00002910, // 1.47304e-41 0x00002a90, // 1.52685e-41 0x00002c40, // 1.58739e-41 Binary files /srv/release.debian.org/tmp/sDtPvc6wfL/nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia-modeset/src/shaders/g_maxwell_shaders and /srv/release.debian.org/tmp/PYKxhEfHRB/nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia-modeset/src/shaders/g_maxwell_shaders differ diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia-modeset/src/shaders/g_pascal_shader_info.h nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia-modeset/src/shaders/g_pascal_shader_info.h --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia-modeset/src/shaders/g_pascal_shader_info.h 2023-10-25 20:22:42.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia-modeset/src/shaders/g_pascal_shader_info.h 2024-03-05 22:12:24.000000000 +0000 @@ -1,4 +1,4 @@ -// Generated using 'Offline GLSL Shader Compiler Version 13.0.0.0.465.00.dev/gpu_drv/dev_a-14542' +// Generated using 'Offline GLSL Shader Compiler Version 13.0.0.0.530.00.dev/gpu_drv/dev_a-15624' // WARNING: This file is auto-generated! Do not hand-edit! // Instead, edit the GLSL shaders and run 'unix-build nvmake @generate'. @@ -9,7 +9,7 @@ static const Nv3dProgramInfo PascalProgramInfo[NUM_PROGRAMS] = { // nvidia_headsurface_vertex { .offset = 0x00000030, - .registerCount = 11, + .registerCount = 13, .type = NV3D_SHADER_TYPE_VERTEX, .constIndex = -1, .stage = NV3D_HW_SHADER_STAGE_VERTEX_B, @@ -322,9 +322,9 @@ 0x000012f8, // 6.80471e-42 0x00001478, // 7.3428e-42 0x00001630, // 7.95938e-42 - 0x00001a40, // 9.41673e-42 - 0x00001de0, // 1.07171e-41 - 0x000022e0, // 1.25108e-41 + 0x00001a38, // 9.40552e-42 + 0x00001df0, // 1.07396e-41 + 0x000022f0, // 1.25332e-41 0x00002880, // 1.45287e-41 0x00002a00, // 1.50668e-41 0x00002bb8, // 1.56833e-41 @@ -346,9 +346,9 @@ 0x000012f8, // 6.80471e-42 0x00001478, // 7.3428e-42 0x00001630, // 7.95938e-42 - 0x00001a70, // 9.48399e-42 - 0x00001e10, // 1.07844e-41 - 0x00002310, // 1.25781e-41 + 0x00001a60, // 9.46157e-42 + 0x00001e18, // 1.07956e-41 + 0x00002318, // 1.25893e-41 0x000028b0, // 1.45959e-41 0x00002a30, // 1.5134e-41 0x00002be0, // 1.57394e-41 @@ -361,9 +361,9 @@ 0x000012f8, // 6.80471e-42 0x00001478, // 7.3428e-42 0x00001630, // 7.95938e-42 - 0x00001ab0, // 9.57367e-42 - 0x00001e50, // 1.08741e-41 - 0x00002350, // 1.26677e-41 + 0x00001aa0, // 9.55125e-42 + 0x00001e58, // 1.08853e-41 + 0x00002358, // 1.26789e-41 0x000028f0, // 1.46856e-41 0x00002a70, // 1.52237e-41 0x00002c20, // 1.58291e-41 @@ -376,9 +376,9 @@ 0x00001300, // 6.81592e-42 0x00001480, // 7.35401e-42 0x00001638, // 7.97059e-42 - 0x00001a90, // 9.52883e-42 - 0x00001e30, // 1.08292e-41 - 0x00002330, // 1.26229e-41 + 0x00001a80, // 9.50641e-42 + 0x00001e38, // 1.08404e-41 + 0x00002338, // 1.26341e-41 0x000028d0, // 1.46408e-41 0x00002a50, // 1.51789e-41 0x00002c00, // 1.57842e-41 @@ -391,9 +391,9 @@ 0x00001300, // 6.81592e-42 0x00001480, // 7.35401e-42 0x00001638, // 7.97059e-42 - 0x00001ad0, // 9.61851e-42 - 0x00001e70, // 1.09189e-41 - 0x00002370, // 1.27126e-41 + 0x00001ac0, // 9.59609e-42 + 0x00001e78, // 1.09301e-41 + 0x00002378, // 1.27238e-41 0x00002910, // 1.47304e-41 0x00002a90, // 1.52685e-41 0x00002c40, // 1.58739e-41 Binary files /srv/release.debian.org/tmp/sDtPvc6wfL/nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia-modeset/src/shaders/g_pascal_shaders and /srv/release.debian.org/tmp/PYKxhEfHRB/nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia-modeset/src/shaders/g_pascal_shaders differ diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia-modeset/src/shaders/g_turing_shader_info.h nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia-modeset/src/shaders/g_turing_shader_info.h --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia-modeset/src/shaders/g_turing_shader_info.h 2023-10-25 20:22:42.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia-modeset/src/shaders/g_turing_shader_info.h 2024-03-05 22:12:24.000000000 +0000 @@ -1,4 +1,4 @@ -// Generated using 'Offline GLSL Shader Compiler Version 13.0.0.0.465.00.dev/gpu_drv/dev_a-14542' +// Generated using 'Offline GLSL Shader Compiler Version 13.0.0.0.530.00.dev/gpu_drv/dev_a-15624' // WARNING: This file is auto-generated! Do not hand-edit! // Instead, edit the GLSL shaders and run 'unix-build nvmake @generate'. @@ -9,7 +9,7 @@ static const Nv3dProgramInfo TuringProgramInfo[NUM_PROGRAMS] = { // nvidia_headsurface_vertex { .offset = 0x00000000, - .registerCount = 16, + .registerCount = 15, .type = NV3D_SHADER_TYPE_VERTEX, .constIndex = -1, .stage = NV3D_HW_SHADER_STAGE_VERTEX_B, Binary files /srv/release.debian.org/tmp/sDtPvc6wfL/nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia-modeset/src/shaders/g_turing_shaders and /srv/release.debian.org/tmp/PYKxhEfHRB/nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia-modeset/src/shaders/g_turing_shaders differ diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia-modeset/src/shaders/g_volta_shader_info.h nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia-modeset/src/shaders/g_volta_shader_info.h --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia-modeset/src/shaders/g_volta_shader_info.h 2023-10-25 20:22:42.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia-modeset/src/shaders/g_volta_shader_info.h 2024-03-05 22:12:24.000000000 +0000 @@ -1,4 +1,4 @@ -// Generated using 'Offline GLSL Shader Compiler Version 13.0.0.0.465.00.dev/gpu_drv/dev_a-14542' +// Generated using 'Offline GLSL Shader Compiler Version 13.0.0.0.530.00.dev/gpu_drv/dev_a-15624' // WARNING: This file is auto-generated! Do not hand-edit! // Instead, edit the GLSL shaders and run 'unix-build nvmake @generate'. @@ -9,7 +9,7 @@ static const Nv3dProgramInfo VoltaProgramInfo[NUM_PROGRAMS] = { // nvidia_headsurface_vertex { .offset = 0x00000030, - .registerCount = 16, + .registerCount = 15, .type = NV3D_SHADER_TYPE_VERTEX, .constIndex = -1, .stage = NV3D_HW_SHADER_STAGE_VERTEX_B, Binary files /srv/release.debian.org/tmp/sDtPvc6wfL/nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia-modeset/src/shaders/g_volta_shaders and /srv/release.debian.org/tmp/PYKxhEfHRB/nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia-modeset/src/shaders/g_volta_shaders differ diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia-modeset/srcs.mk nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia-modeset/srcs.mk --- nvidia-open-gpu-kernel-modules-525.147.05/src/nvidia-modeset/srcs.mk 2023-10-25 20:22:13.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/src/nvidia-modeset/srcs.mk 2024-03-05 22:11:43.000000000 +0000 @@ -153,8 +153,8 @@ SRCS += ../common/unix/nvidia-3d/src/nvidia-3d-volta.c SRCS += ../common/unix/nvidia-push/src/nvidia-push-init.c SRCS += ../common/unix/nvidia-push/src/nvidia-push.c -SRCS += kapi/src/nvkms-kapi-channelevent.c SRCS += kapi/src/nvkms-kapi-notifiers.c +SRCS += kapi/src/nvkms-kapi-sync.c SRCS += kapi/src/nvkms-kapi.c SRCS += lib/nvkms-format.c SRCS += lib/nvkms-sync.c @@ -167,12 +167,14 @@ SRCS += src/g_nvkms-evo-states.c SRCS += src/nvkms-3dvision.c SRCS += src/nvkms-attributes.c +SRCS += src/nvkms-conf.c SRCS += src/nvkms-console-restore.c SRCS += src/nvkms-cursor.c SRCS += src/nvkms-cursor2.c SRCS += src/nvkms-cursor3.c SRCS += src/nvkms-difr.c SRCS += src/nvkms-dma.c +SRCS += src/nvkms-dpy-override.c SRCS += src/nvkms-dpy.c SRCS += src/nvkms-event.c SRCS += src/nvkms-evo.c @@ -183,6 +185,7 @@ SRCS += src/nvkms-framelock.c SRCS += src/nvkms-hal.c SRCS += src/nvkms-hdmi.c +SRCS += src/nvkms-hw-flip.c SRCS += src/nvkms-headsurface-3d.c SRCS += src/nvkms-headsurface-config.c SRCS += src/nvkms-headsurface-ioctl.c @@ -200,6 +203,7 @@ SRCS += src/nvkms-rmapi-dgpu.c SRCS += src/nvkms-stereo.c SRCS += src/nvkms-surface.c +SRCS += src/nvkms-utils-flip.c SRCS += src/nvkms-utils.c SRCS += src/nvkms-vrr.c SRCS += src/nvkms.c diff -Nru nvidia-open-gpu-kernel-modules-525.147.05/version.mk nvidia-open-gpu-kernel-modules-535.161.08/version.mk --- nvidia-open-gpu-kernel-modules-525.147.05/version.mk 2023-10-25 21:08:29.000000000 +0000 +++ nvidia-open-gpu-kernel-modules-535.161.08/version.mk 2024-03-05 23:13:29.000000000 +0000 @@ -1,4 +1,4 @@ -NVIDIA_VERSION = 525.147.05 +NVIDIA_VERSION = 535.161.08 # This file. VERSION_MK_FILE := $(lastword $(MAKEFILE_LIST))